From 8b22960ddcc92ef97c01d5a115bb2bb2b9c870c1 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 26 Oct 2020 23:59:20 -0600 Subject: [PATCH] [Design] Added FPGA22 design with SKY130_FD_SC_HD --- .gitignore | 5 + .../OpenFPGAEngine.info | 55 + .../SRC/define_simulation.v | 18 + .../SRC/fabric_netlists.v | 66 + .../FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v | 1347 + .../SRC/fpga_defines.v | 16 + .../FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v | 1346 + .../FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v | 292 + .../SRC/lb/grid_io_bottom.v | 75 + .../SRC/lb/grid_io_left.v | 75 + .../SRC/lb/grid_io_right.v | 75 + .../SRC/lb/grid_io_top.v | 75 + .../SRC/lb/logical_tile_clb_mode_clb_.v | 598 + .../lb/logical_tile_clb_mode_default__fle.v | 143 + ..._mode_default__fle_mode_physical__fabric.v | 203 + ...e_mode_physical__fabric_mode_default__ff.v | 59 + ...hysical__fabric_mode_default__frac_logic.v | 99 + ...ault__frac_logic_mode_default__frac_lut4.v | 71 + .../SRC/lb/logical_tile_io_mode_io_.v | 82 + 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mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v create mode 100644 FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..02b3645 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +**/SRCOriginal +**/SRCOutline +**/TaskConfigCopy +**/*_task/run001 +**/*_task/latest diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info new file mode 100644 index 0000000..167cc03 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info @@ -0,0 +1,55 @@ +commit 48b2bff0d909e2c6d0740d2a5386123eb238349f +Author: tangxifan +Date: Sun Sep 27 20:08:11 2020 -0600 + + [OpenFPGA Tool] Update fabric key data structure to support regions + +commit bbdea4a46b7aadd8a6f0fc45abdd39d1cc6d3057 +Author: tangxifan +Date: Sun Sep 27 19:23:13 2020 -0600 + + [Regression Test] Remove out-of-update sub modules + +commit e95eacfbd9ec5e8d9aecab7572d4bad5265d9590 +Merge: 32c43ffb 94047037 +Author: tangxifan +Date: Sun Sep 27 17:01:57 2020 -0600 + + Merge branch 'dev' into ganesh_dev + +commit 94047037c570b6a432fea8f363a5147df9bc918d +Author: tangxifan +Date: Sun Sep 27 14:33:14 2020 -0600 + + [OpenFPGA Tool] Streamline codes in openfpga arch parser + +commit 94a1324f0527276546c3b2571b1a1b7700a473f7 +Author: tangxifan +Date: Sat Sep 26 14:31:57 2020 -0600 + + [Documentation] Remove deprecated XML syntax +On branch dev +Your branch is up to date with 'origin/dev'. + +Untracked files: + (use "git add ..." to include in what will be committed) + openfpga/openfpga + openfpga_flow/tasks/FPGA128128_FLAT_task + openfpga_flow/tasks/FPGA1616_FLAT_task + openfpga_flow/tasks/FPGA22_FLAT_task + openfpga_flow/tasks/FPGA22_FRAME_task + openfpga_flow/tasks/FPGA22_HIER_SKY_task + openfpga_flow/tasks/FPGA22_HIER_task + openfpga_flow/tasks/FPGA22_MB_task + openfpga_flow/tasks/FPGA22_MODULAR_task + openfpga_flow/tasks/FPGA22_SPY_task + openfpga_flow/tasks/FPGA3232_FLAT_task + openfpga_flow/tasks/FPGA44_FLAT_task + openfpga_flow/tasks/FPGA6464_FLAT_task + openfpga_flow/tasks/FPGA66_FLAT_task + openfpga_flow/tasks/FPGA88_FLAT_task + openfpga_flow/tasks/routing_test/ + openfpga_flow/tasks/skywater_openfpga_task + vpr/vpr + +nothing added to commit but untracked files present (use "git add" to track) diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v new file mode 100644 index 0000000..8cbaaf5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v @@ -0,0 +1,18 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +`define INITIAL_SIMULATION 1 + +`define AUTOCHECKED_SIMULATION 1 + +`define ENABLE_FORMAL_VERIFICATION 1 + +`define FORMAL_SIMULATION 1 + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v new file mode 100644 index 0000000..523cc86 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v @@ -0,0 +1,66 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +`include "./SRC/fpga_defines.v" + +// +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrbp/sky130_fd_sc_hd__dfxbp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/std_cell_extract.v" +// +`include "./SRC/sub_module/inv_buf_passgate.v" +`include "./SRC/sub_module/arch_encoder.v" +`include "./SRC/sub_module/local_encoder.v" +`include "./SRC/sub_module/muxes.v" +`include "./SRC/sub_module/luts.v" +`include "./SRC/sub_module/wires.v" +`include "./SRC/sub_module/memories.v" + +// +`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v" +`include "./SRC/lb/logical_tile_io_mode_io_.v" +`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v" +`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v" +`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v" +`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" +`include "./SRC/lb/logical_tile_clb_mode_default__fle.v" +`include "./SRC/lb/logical_tile_clb_mode_clb_.v" +`include "./SRC/lb/grid_io_top.v" +`include "./SRC/lb/grid_io_right.v" +`include "./SRC/lb/grid_io_bottom.v" +`include "./SRC/lb/grid_io_left.v" +`include "./SRC/lb/grid_clb.v" + +// +`include "./SRC/routing/sb_0__0_.v" +`include "./SRC/routing/sb_0__1_.v" +`include "./SRC/routing/sb_0__2_.v" +`include "./SRC/routing/sb_1__0_.v" +`include "./SRC/routing/sb_1__1_.v" +`include "./SRC/routing/sb_1__2_.v" +`include "./SRC/routing/sb_2__0_.v" +`include "./SRC/routing/sb_2__1_.v" +`include "./SRC/routing/sb_2__2_.v" +`include "./SRC/routing/cbx_1__0_.v" +`include "./SRC/routing/cbx_1__1_.v" +`include "./SRC/routing/cbx_1__2_.v" +`include "./SRC/routing/cby_0__1_.v" +`include "./SRC/routing/cby_1__1_.v" + +// +`include "./SRC/fpga_top.v" + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v new file mode 100644 index 0000000..e5e1c6b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v @@ -0,0 +1,1347 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module fpga_core(prog_clk, + Test_en, + clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + ccff_head, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +output [0:7] gfpga_pad_GPIO_A; +// +output [0:7] gfpga_pad_GPIO_IE; +// +output [0:7] gfpga_pad_GPIO_OE; +// +inout [0:7] gfpga_pad_GPIO_Y; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__0_ccff_tail; +wire [0:19] cbx_1__0__0_chanx_left_out; +wire [0:19] cbx_1__0__0_chanx_right_out; +wire [0:0] cbx_1__0__0_top_grid_pin_16_; +wire [0:0] cbx_1__0__0_top_grid_pin_17_; +wire [0:0] cbx_1__0__0_top_grid_pin_18_; +wire [0:0] cbx_1__0__0_top_grid_pin_19_; +wire [0:0] cbx_1__0__0_top_grid_pin_20_; +wire [0:0] cbx_1__0__0_top_grid_pin_21_; +wire [0:0] cbx_1__0__0_top_grid_pin_22_; +wire [0:0] cbx_1__0__0_top_grid_pin_23_; +wire [0:0] cbx_1__0__0_top_grid_pin_24_; +wire [0:0] cbx_1__0__0_top_grid_pin_25_; +wire [0:0] cbx_1__0__0_top_grid_pin_26_; +wire [0:0] cbx_1__0__0_top_grid_pin_27_; +wire [0:0] cbx_1__0__0_top_grid_pin_28_; +wire [0:0] cbx_1__0__0_top_grid_pin_29_; +wire [0:0] cbx_1__0__0_top_grid_pin_30_; +wire [0:0] cbx_1__0__0_top_grid_pin_31_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__1_ccff_tail; +wire [0:19] cbx_1__0__1_chanx_left_out; +wire [0:19] cbx_1__0__1_chanx_right_out; +wire [0:0] cbx_1__0__1_top_grid_pin_16_; +wire [0:0] cbx_1__0__1_top_grid_pin_17_; +wire [0:0] cbx_1__0__1_top_grid_pin_18_; +wire [0:0] cbx_1__0__1_top_grid_pin_19_; +wire [0:0] cbx_1__0__1_top_grid_pin_20_; +wire [0:0] cbx_1__0__1_top_grid_pin_21_; +wire [0:0] cbx_1__0__1_top_grid_pin_22_; +wire [0:0] cbx_1__0__1_top_grid_pin_23_; +wire [0:0] cbx_1__0__1_top_grid_pin_24_; +wire [0:0] cbx_1__0__1_top_grid_pin_25_; +wire [0:0] cbx_1__0__1_top_grid_pin_26_; +wire [0:0] cbx_1__0__1_top_grid_pin_27_; +wire [0:0] cbx_1__0__1_top_grid_pin_28_; +wire [0:0] cbx_1__0__1_top_grid_pin_29_; +wire [0:0] cbx_1__0__1_top_grid_pin_30_; +wire [0:0] cbx_1__0__1_top_grid_pin_31_; +wire [0:0] cbx_1__1__0_ccff_tail; +wire [0:19] cbx_1__1__0_chanx_left_out; +wire [0:19] cbx_1__1__0_chanx_right_out; +wire [0:0] cbx_1__1__0_top_grid_pin_16_; +wire [0:0] cbx_1__1__0_top_grid_pin_17_; +wire [0:0] cbx_1__1__0_top_grid_pin_18_; +wire [0:0] cbx_1__1__0_top_grid_pin_19_; +wire [0:0] cbx_1__1__0_top_grid_pin_20_; +wire [0:0] cbx_1__1__0_top_grid_pin_21_; +wire [0:0] cbx_1__1__0_top_grid_pin_22_; +wire [0:0] cbx_1__1__0_top_grid_pin_23_; +wire [0:0] cbx_1__1__0_top_grid_pin_24_; +wire [0:0] cbx_1__1__0_top_grid_pin_25_; +wire [0:0] cbx_1__1__0_top_grid_pin_26_; +wire [0:0] cbx_1__1__0_top_grid_pin_27_; +wire [0:0] cbx_1__1__0_top_grid_pin_28_; +wire [0:0] cbx_1__1__0_top_grid_pin_29_; +wire [0:0] cbx_1__1__0_top_grid_pin_30_; +wire [0:0] cbx_1__1__0_top_grid_pin_31_; +wire [0:0] cbx_1__1__1_ccff_tail; +wire [0:19] cbx_1__1__1_chanx_left_out; +wire [0:19] cbx_1__1__1_chanx_right_out; +wire [0:0] cbx_1__1__1_top_grid_pin_16_; +wire [0:0] cbx_1__1__1_top_grid_pin_17_; +wire [0:0] cbx_1__1__1_top_grid_pin_18_; +wire [0:0] cbx_1__1__1_top_grid_pin_19_; +wire [0:0] cbx_1__1__1_top_grid_pin_20_; +wire [0:0] cbx_1__1__1_top_grid_pin_21_; +wire [0:0] cbx_1__1__1_top_grid_pin_22_; +wire [0:0] cbx_1__1__1_top_grid_pin_23_; +wire [0:0] cbx_1__1__1_top_grid_pin_24_; +wire [0:0] cbx_1__1__1_top_grid_pin_25_; +wire [0:0] cbx_1__1__1_top_grid_pin_26_; +wire [0:0] cbx_1__1__1_top_grid_pin_27_; +wire [0:0] cbx_1__1__1_top_grid_pin_28_; +wire [0:0] cbx_1__1__1_top_grid_pin_29_; +wire [0:0] cbx_1__1__1_top_grid_pin_30_; +wire [0:0] cbx_1__1__1_top_grid_pin_31_; +wire [0:0] cbx_1__2__0_ccff_tail; +wire [0:19] cbx_1__2__0_chanx_left_out; +wire [0:19] cbx_1__2__0_chanx_right_out; +wire [0:0] cbx_1__2__0_top_grid_pin_0_; +wire [0:0] cbx_1__2__1_ccff_tail; +wire [0:19] cbx_1__2__1_chanx_left_out; +wire [0:19] cbx_1__2__1_chanx_right_out; +wire [0:0] cbx_1__2__1_top_grid_pin_0_; +wire [0:0] cby_0__1__0_ccff_tail; +wire [0:19] cby_0__1__0_chany_bottom_out; +wire [0:19] cby_0__1__0_chany_top_out; +wire [0:0] cby_0__1__0_left_grid_pin_0_; +wire [0:0] cby_0__1__0_right_grid_pin_52_; +wire [0:0] cby_0__1__1_ccff_tail; +wire [0:19] cby_0__1__1_chany_bottom_out; +wire [0:19] cby_0__1__1_chany_top_out; +wire [0:0] cby_0__1__1_left_grid_pin_0_; +wire [0:0] cby_0__1__1_right_grid_pin_52_; +wire [0:0] cby_1__1__0_ccff_tail; +wire [0:19] cby_1__1__0_chany_bottom_out; +wire [0:19] cby_1__1__0_chany_top_out; +wire [0:0] cby_1__1__0_left_grid_pin_0_; +wire [0:0] cby_1__1__0_left_grid_pin_10_; +wire [0:0] cby_1__1__0_left_grid_pin_11_; +wire [0:0] cby_1__1__0_left_grid_pin_12_; +wire [0:0] cby_1__1__0_left_grid_pin_13_; +wire [0:0] cby_1__1__0_left_grid_pin_14_; +wire [0:0] cby_1__1__0_left_grid_pin_15_; +wire [0:0] cby_1__1__0_left_grid_pin_1_; +wire [0:0] cby_1__1__0_left_grid_pin_2_; +wire [0:0] cby_1__1__0_left_grid_pin_3_; +wire [0:0] cby_1__1__0_left_grid_pin_4_; +wire [0:0] cby_1__1__0_left_grid_pin_5_; +wire [0:0] cby_1__1__0_left_grid_pin_6_; +wire [0:0] cby_1__1__0_left_grid_pin_7_; +wire [0:0] cby_1__1__0_left_grid_pin_8_; +wire [0:0] cby_1__1__0_left_grid_pin_9_; +wire [0:0] cby_1__1__0_right_grid_pin_52_; +wire [0:0] cby_1__1__1_ccff_tail; +wire [0:19] cby_1__1__1_chany_bottom_out; +wire [0:19] cby_1__1__1_chany_top_out; +wire [0:0] cby_1__1__1_left_grid_pin_0_; +wire [0:0] cby_1__1__1_left_grid_pin_10_; +wire [0:0] cby_1__1__1_left_grid_pin_11_; +wire [0:0] cby_1__1__1_left_grid_pin_12_; +wire [0:0] cby_1__1__1_left_grid_pin_13_; +wire [0:0] cby_1__1__1_left_grid_pin_14_; +wire [0:0] cby_1__1__1_left_grid_pin_15_; +wire [0:0] cby_1__1__1_left_grid_pin_1_; +wire [0:0] cby_1__1__1_left_grid_pin_2_; +wire [0:0] cby_1__1__1_left_grid_pin_3_; +wire [0:0] cby_1__1__1_left_grid_pin_4_; +wire [0:0] cby_1__1__1_left_grid_pin_5_; +wire [0:0] cby_1__1__1_left_grid_pin_6_; +wire [0:0] cby_1__1__1_left_grid_pin_7_; +wire [0:0] cby_1__1__1_left_grid_pin_8_; +wire [0:0] cby_1__1__1_left_grid_pin_9_; +wire [0:0] cby_1__1__1_right_grid_pin_52_; +wire [0:0] cby_1__1__2_ccff_tail; +wire [0:19] cby_1__1__2_chany_bottom_out; +wire [0:19] cby_1__1__2_chany_top_out; +wire [0:0] cby_1__1__2_left_grid_pin_0_; +wire [0:0] cby_1__1__2_left_grid_pin_10_; +wire [0:0] cby_1__1__2_left_grid_pin_11_; +wire [0:0] cby_1__1__2_left_grid_pin_12_; +wire [0:0] cby_1__1__2_left_grid_pin_13_; +wire [0:0] cby_1__1__2_left_grid_pin_14_; +wire [0:0] cby_1__1__2_left_grid_pin_15_; +wire [0:0] cby_1__1__2_left_grid_pin_1_; +wire [0:0] cby_1__1__2_left_grid_pin_2_; +wire [0:0] cby_1__1__2_left_grid_pin_3_; +wire [0:0] cby_1__1__2_left_grid_pin_4_; +wire [0:0] cby_1__1__2_left_grid_pin_5_; +wire [0:0] cby_1__1__2_left_grid_pin_6_; +wire [0:0] cby_1__1__2_left_grid_pin_7_; +wire [0:0] cby_1__1__2_left_grid_pin_8_; +wire [0:0] cby_1__1__2_left_grid_pin_9_; +wire [0:0] cby_1__1__2_right_grid_pin_52_; +wire [0:0] cby_1__1__3_ccff_tail; +wire [0:19] cby_1__1__3_chany_bottom_out; +wire [0:19] cby_1__1__3_chany_top_out; +wire [0:0] cby_1__1__3_left_grid_pin_0_; +wire [0:0] cby_1__1__3_left_grid_pin_10_; +wire [0:0] cby_1__1__3_left_grid_pin_11_; +wire [0:0] cby_1__1__3_left_grid_pin_12_; +wire [0:0] cby_1__1__3_left_grid_pin_13_; +wire [0:0] cby_1__1__3_left_grid_pin_14_; +wire [0:0] cby_1__1__3_left_grid_pin_15_; +wire [0:0] cby_1__1__3_left_grid_pin_1_; +wire [0:0] cby_1__1__3_left_grid_pin_2_; +wire [0:0] cby_1__1__3_left_grid_pin_3_; +wire [0:0] cby_1__1__3_left_grid_pin_4_; +wire [0:0] cby_1__1__3_left_grid_pin_5_; +wire [0:0] cby_1__1__3_left_grid_pin_6_; +wire [0:0] cby_1__1__3_left_grid_pin_7_; +wire [0:0] cby_1__1__3_left_grid_pin_8_; +wire [0:0] cby_1__1__3_left_grid_pin_9_; +wire [0:0] cby_1__1__3_right_grid_pin_52_; +wire [0:0] direct_interc_0_out; +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_0_ccff_tail; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_1_ccff_tail; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_ccff_tail; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_3_ccff_tail; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_io_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_1_ccff_tail; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_0_ccff_tail; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_1_ccff_tail; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_0_ccff_tail; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_1_ccff_tail; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_0_ccff_tail; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_1_ccff_tail; +wire [0:19] sb_0__0__0_chanx_right_out; +wire [0:19] sb_0__0__0_chany_top_out; +wire [0:0] sb_0__1__0_ccff_tail; +wire [0:19] sb_0__1__0_chanx_right_out; +wire [0:19] sb_0__1__0_chany_bottom_out; +wire [0:19] sb_0__1__0_chany_top_out; +wire [0:0] sb_0__2__0_ccff_tail; +wire [0:19] sb_0__2__0_chanx_right_out; +wire [0:19] sb_0__2__0_chany_bottom_out; +wire [0:0] sb_1__0__0_ccff_tail; +wire [0:19] sb_1__0__0_chanx_left_out; +wire [0:19] sb_1__0__0_chanx_right_out; +wire [0:19] sb_1__0__0_chany_top_out; +wire [0:0] sb_1__1__0_ccff_tail; +wire [0:19] sb_1__1__0_chanx_left_out; +wire [0:19] sb_1__1__0_chanx_right_out; +wire [0:19] sb_1__1__0_chany_bottom_out; +wire [0:19] sb_1__1__0_chany_top_out; +wire [0:0] sb_1__2__0_ccff_tail; +wire [0:19] sb_1__2__0_chanx_left_out; +wire [0:19] sb_1__2__0_chanx_right_out; +wire [0:19] sb_1__2__0_chany_bottom_out; +wire [0:0] sb_2__0__0_ccff_tail; +wire [0:19] sb_2__0__0_chanx_left_out; +wire [0:19] sb_2__0__0_chany_top_out; +wire [0:0] sb_2__1__0_ccff_tail; +wire [0:19] sb_2__1__0_chanx_left_out; +wire [0:19] sb_2__1__0_chany_bottom_out; +wire [0:19] sb_2__1__0_chany_top_out; +wire [0:0] sb_2__2__0_ccff_tail; +wire [0:19] sb_2__2__0_chanx_left_out; +wire [0:19] sb_2__2__0_chany_bottom_out; + +// +// +// +// + + grid_clb grid_clb_1__1_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), + .ccff_head(grid_io_left_0_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_0_ccff_tail[0])); + + grid_clb grid_clb_1__2_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), + .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), + .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), + .ccff_head(grid_io_left_1_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_1_ccff_tail[0])); + + grid_clb grid_clb_2__1_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__0_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_2_ccff_tail[0])); + + grid_clb grid_clb_2__2_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__1_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_3_ccff_tail[0])); + + grid_io_top grid_io_top_1__3_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .ccff_head(cbx_1__2__0_ccff_tail[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_0_ccff_tail[0])); + + grid_io_top grid_io_top_2__3_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .ccff_head(cbx_1__2__1_ccff_tail[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_1_ccff_tail[0])); + + grid_io_right grid_io_right_3__1_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), + .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__2_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_0_ccff_tail[0])); + + grid_io_right grid_io_right_3__2_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), + .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__3_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_1_ccff_tail[0])); + + grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), + .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .ccff_head(cbx_1__0__0_ccff_tail[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + + grid_io_bottom grid_io_bottom_2__0_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), + .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .ccff_head(cbx_1__0__1_ccff_tail[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_bottom_1_ccff_tail[0])); + + grid_io_left grid_io_left_0__1_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), + .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_head(cby_0__1__0_ccff_tail[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_0_ccff_tail[0])); + + grid_io_left grid_io_left_0__2_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), + .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_head(cby_0__1__1_ccff_tail[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_1_ccff_tail[0])); + + sb_0__0_ sb_0__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .chany_top_out(sb_0__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), + .ccff_tail(ccff_tail[0])); + + sb_0__1_ sb_0__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(cbx_1__1__0_ccff_tail[0]), + .chany_top_out(sb_0__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__1__0_ccff_tail[0])); + + sb_0__2_ sb_0__2_ ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_0_ccff_tail[0]), + .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__2__0_ccff_tail[0])); + + sb_1__0_ sb_1__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .chany_top_out(sb_1__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__0__0_ccff_tail[0])); + + sb_1__1_ sb_1__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .ccff_head(cbx_1__1__1_ccff_tail[0]), + .chany_top_out(sb_1__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__1__0_ccff_tail[0])); + + sb_1__2_ sb_1__2_ ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_top_1_ccff_tail[0]), + .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__2__0_ccff_tail[0])); + + sb_2__0_ sb_2__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), + .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_right_0_ccff_tail[0]), + .chany_top_out(sb_2__0__0_chany_top_out[0:19]), + .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__0__0_ccff_tail[0])); + + sb_2__1_ sb_2__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), + .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .ccff_head(grid_io_right_1_ccff_tail[0]), + .chany_top_out(sb_2__1__0_chany_top_out[0:19]), + .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__1__0_ccff_tail[0])); + + sb_2__2_ sb_2__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_head(ccff_head[0]), + .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__2__0_ccff_tail[0])); + + cbx_1__0_ cbx_1__0_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), + .ccff_head(sb_1__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .ccff_tail(cbx_1__0__0_ccff_tail[0])); + + cbx_1__0_ cbx_2__0_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), + .ccff_head(sb_2__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .ccff_tail(cbx_1__0__1_ccff_tail[0])); + + cbx_1__1_ cbx_1__1_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), + .ccff_head(sb_1__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .ccff_tail(cbx_1__1__0_ccff_tail[0])); + + cbx_1__1_ cbx_2__1_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), + .ccff_head(sb_2__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .ccff_tail(cbx_1__1__1_ccff_tail[0])); + + cbx_1__2_ cbx_1__2_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), + .ccff_head(sb_1__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .ccff_tail(cbx_1__2__0_ccff_tail[0])); + + cbx_1__2_ cbx_2__2_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), + .ccff_head(sb_2__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .ccff_tail(cbx_1__2__1_ccff_tail[0])); + + cby_0__1_ cby_0__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__1__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__0_chany_top_out[0:19]), + .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_tail(cby_0__1__0_ccff_tail[0])); + + cby_0__1_ cby_0__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), + .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__2__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__1_chany_top_out[0:19]), + .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_tail(cby_0__1__1_ccff_tail[0])); + + cby_1__1_ cby_1__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_0_ccff_tail[0]), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__0_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__0_ccff_tail[0])); + + cby_1__1_ cby_1__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), + .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_1_ccff_tail[0]), + .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__1_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__1_ccff_tail[0])); + + cby_1__1_ cby_2__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), + .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_2_ccff_tail[0]), + .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__2_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__2_ccff_tail[0])); + + cby_1__1_ cby_2__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), + .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_3_ccff_tail[0]), + .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__3_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__3_ccff_tail[0])); + + direct_interc direct_interc_0_ ( + .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_0_out[0])); + + direct_interc direct_interc_1_ ( + .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_1_out[0])); + + direct_interc direct_interc_2_ ( + .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_2_out[0])); + + direct_interc direct_interc_3_ ( + .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_3_out[0])); + + direct_interc direct_interc_4_ ( + .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_4_out[0])); + + direct_interc direct_interc_5_ ( + .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_5_out[0])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v new file mode 100644 index 0000000..48f3ef2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v @@ -0,0 +1,16 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +`define ENABLE_TIMING 1 + +`define ENABLE_SIGNAL_INITIALIZATION 1 + +`define ICARUS_SIMULATOR 1 + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v new file mode 100644 index 0000000..5ccd1a3 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v @@ -0,0 +1,1346 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module fpga_topfpga_top(prog_clk, Test_en, clk, gfpga_pad_GPIO_A, gfpga_pad_GPIO_IE, gfpga_pad_GPIO_OE, gfpga_pad_GPIO_Y, ccff_head, ccff_tail); prog_clk; + Test_en; + clk; + gfpga_pad_GPIO_A; + gfpga_pad_GPIO_IE; + gfpga_pad_GPIO_OE; + gfpga_pad_GPIO_Y; + ccff_head;; +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +output [0:7] gfpga_pad_GPIO_A; +// +output [0:7] gfpga_pad_GPIO_IE; +// +output [0:7] gfpga_pad_GPIO_OE; +// +inout [0:7] gfpga_pad_GPIO_Y; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__0_ccff_tail; +wire [0:19] cbx_1__0__0_chanx_left_out; +wire [0:19] cbx_1__0__0_chanx_right_out; +wire [0:0] cbx_1__0__0_top_grid_pin_16_; +wire [0:0] cbx_1__0__0_top_grid_pin_17_; +wire [0:0] cbx_1__0__0_top_grid_pin_18_; +wire [0:0] cbx_1__0__0_top_grid_pin_19_; +wire [0:0] cbx_1__0__0_top_grid_pin_20_; +wire [0:0] cbx_1__0__0_top_grid_pin_21_; +wire [0:0] cbx_1__0__0_top_grid_pin_22_; +wire [0:0] cbx_1__0__0_top_grid_pin_23_; +wire [0:0] cbx_1__0__0_top_grid_pin_24_; +wire [0:0] cbx_1__0__0_top_grid_pin_25_; +wire [0:0] cbx_1__0__0_top_grid_pin_26_; +wire [0:0] cbx_1__0__0_top_grid_pin_27_; +wire [0:0] cbx_1__0__0_top_grid_pin_28_; +wire [0:0] cbx_1__0__0_top_grid_pin_29_; +wire [0:0] cbx_1__0__0_top_grid_pin_30_; +wire [0:0] cbx_1__0__0_top_grid_pin_31_; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; +wire [0:0] cbx_1__0__1_ccff_tail; +wire [0:19] cbx_1__0__1_chanx_left_out; +wire [0:19] cbx_1__0__1_chanx_right_out; +wire [0:0] cbx_1__0__1_top_grid_pin_16_; +wire [0:0] cbx_1__0__1_top_grid_pin_17_; +wire [0:0] cbx_1__0__1_top_grid_pin_18_; +wire [0:0] cbx_1__0__1_top_grid_pin_19_; +wire [0:0] cbx_1__0__1_top_grid_pin_20_; +wire [0:0] cbx_1__0__1_top_grid_pin_21_; +wire [0:0] cbx_1__0__1_top_grid_pin_22_; +wire [0:0] cbx_1__0__1_top_grid_pin_23_; +wire [0:0] cbx_1__0__1_top_grid_pin_24_; +wire [0:0] cbx_1__0__1_top_grid_pin_25_; +wire [0:0] cbx_1__0__1_top_grid_pin_26_; +wire [0:0] cbx_1__0__1_top_grid_pin_27_; +wire [0:0] cbx_1__0__1_top_grid_pin_28_; +wire [0:0] cbx_1__0__1_top_grid_pin_29_; +wire [0:0] cbx_1__0__1_top_grid_pin_30_; +wire [0:0] cbx_1__0__1_top_grid_pin_31_; +wire [0:0] cbx_1__1__0_ccff_tail; +wire [0:19] cbx_1__1__0_chanx_left_out; +wire [0:19] cbx_1__1__0_chanx_right_out; +wire [0:0] cbx_1__1__0_top_grid_pin_16_; +wire [0:0] cbx_1__1__0_top_grid_pin_17_; +wire [0:0] cbx_1__1__0_top_grid_pin_18_; +wire [0:0] cbx_1__1__0_top_grid_pin_19_; +wire [0:0] cbx_1__1__0_top_grid_pin_20_; +wire [0:0] cbx_1__1__0_top_grid_pin_21_; +wire [0:0] cbx_1__1__0_top_grid_pin_22_; +wire [0:0] cbx_1__1__0_top_grid_pin_23_; +wire [0:0] cbx_1__1__0_top_grid_pin_24_; +wire [0:0] cbx_1__1__0_top_grid_pin_25_; +wire [0:0] cbx_1__1__0_top_grid_pin_26_; +wire [0:0] cbx_1__1__0_top_grid_pin_27_; +wire [0:0] cbx_1__1__0_top_grid_pin_28_; +wire [0:0] cbx_1__1__0_top_grid_pin_29_; +wire [0:0] cbx_1__1__0_top_grid_pin_30_; +wire [0:0] cbx_1__1__0_top_grid_pin_31_; +wire [0:0] cbx_1__1__1_ccff_tail; +wire [0:19] cbx_1__1__1_chanx_left_out; +wire [0:19] cbx_1__1__1_chanx_right_out; +wire [0:0] cbx_1__1__1_top_grid_pin_16_; +wire [0:0] cbx_1__1__1_top_grid_pin_17_; +wire [0:0] cbx_1__1__1_top_grid_pin_18_; +wire [0:0] cbx_1__1__1_top_grid_pin_19_; +wire [0:0] cbx_1__1__1_top_grid_pin_20_; +wire [0:0] cbx_1__1__1_top_grid_pin_21_; +wire [0:0] cbx_1__1__1_top_grid_pin_22_; +wire [0:0] cbx_1__1__1_top_grid_pin_23_; +wire [0:0] cbx_1__1__1_top_grid_pin_24_; +wire [0:0] cbx_1__1__1_top_grid_pin_25_; +wire [0:0] cbx_1__1__1_top_grid_pin_26_; +wire [0:0] cbx_1__1__1_top_grid_pin_27_; +wire [0:0] cbx_1__1__1_top_grid_pin_28_; +wire [0:0] cbx_1__1__1_top_grid_pin_29_; +wire [0:0] cbx_1__1__1_top_grid_pin_30_; +wire [0:0] cbx_1__1__1_top_grid_pin_31_; +wire [0:0] cbx_1__2__0_ccff_tail; +wire [0:19] cbx_1__2__0_chanx_left_out; +wire [0:19] cbx_1__2__0_chanx_right_out; +wire [0:0] cbx_1__2__0_top_grid_pin_0_; +wire [0:0] cbx_1__2__1_ccff_tail; +wire [0:19] cbx_1__2__1_chanx_left_out; +wire [0:19] cbx_1__2__1_chanx_right_out; +wire [0:0] cbx_1__2__1_top_grid_pin_0_; +wire [0:0] cby_0__1__0_ccff_tail; +wire [0:19] cby_0__1__0_chany_bottom_out; +wire [0:19] cby_0__1__0_chany_top_out; +wire [0:0] cby_0__1__0_left_grid_pin_0_; +wire [0:0] cby_0__1__0_right_grid_pin_52_; +wire [0:0] cby_0__1__1_ccff_tail; +wire [0:19] cby_0__1__1_chany_bottom_out; +wire [0:19] cby_0__1__1_chany_top_out; +wire [0:0] cby_0__1__1_left_grid_pin_0_; +wire [0:0] cby_0__1__1_right_grid_pin_52_; +wire [0:0] cby_1__1__0_ccff_tail; +wire [0:19] cby_1__1__0_chany_bottom_out; +wire [0:19] cby_1__1__0_chany_top_out; +wire [0:0] cby_1__1__0_left_grid_pin_0_; +wire [0:0] cby_1__1__0_left_grid_pin_10_; +wire [0:0] cby_1__1__0_left_grid_pin_11_; +wire [0:0] cby_1__1__0_left_grid_pin_12_; +wire [0:0] cby_1__1__0_left_grid_pin_13_; +wire [0:0] cby_1__1__0_left_grid_pin_14_; +wire [0:0] cby_1__1__0_left_grid_pin_15_; +wire [0:0] cby_1__1__0_left_grid_pin_1_; +wire [0:0] cby_1__1__0_left_grid_pin_2_; +wire [0:0] cby_1__1__0_left_grid_pin_3_; +wire [0:0] cby_1__1__0_left_grid_pin_4_; +wire [0:0] cby_1__1__0_left_grid_pin_5_; +wire [0:0] cby_1__1__0_left_grid_pin_6_; +wire [0:0] cby_1__1__0_left_grid_pin_7_; +wire [0:0] cby_1__1__0_left_grid_pin_8_; +wire [0:0] cby_1__1__0_left_grid_pin_9_; +wire [0:0] cby_1__1__0_right_grid_pin_52_; +wire [0:0] cby_1__1__1_ccff_tail; +wire [0:19] cby_1__1__1_chany_bottom_out; +wire [0:19] cby_1__1__1_chany_top_out; +wire [0:0] cby_1__1__1_left_grid_pin_0_; +wire [0:0] cby_1__1__1_left_grid_pin_10_; +wire [0:0] cby_1__1__1_left_grid_pin_11_; +wire [0:0] cby_1__1__1_left_grid_pin_12_; +wire [0:0] cby_1__1__1_left_grid_pin_13_; +wire [0:0] cby_1__1__1_left_grid_pin_14_; +wire [0:0] cby_1__1__1_left_grid_pin_15_; +wire [0:0] cby_1__1__1_left_grid_pin_1_; +wire [0:0] cby_1__1__1_left_grid_pin_2_; +wire [0:0] cby_1__1__1_left_grid_pin_3_; +wire [0:0] cby_1__1__1_left_grid_pin_4_; +wire [0:0] cby_1__1__1_left_grid_pin_5_; +wire [0:0] cby_1__1__1_left_grid_pin_6_; +wire [0:0] cby_1__1__1_left_grid_pin_7_; +wire [0:0] cby_1__1__1_left_grid_pin_8_; +wire [0:0] cby_1__1__1_left_grid_pin_9_; +wire [0:0] cby_1__1__1_right_grid_pin_52_; +wire [0:0] cby_1__1__2_ccff_tail; +wire [0:19] cby_1__1__2_chany_bottom_out; +wire [0:19] cby_1__1__2_chany_top_out; +wire [0:0] cby_1__1__2_left_grid_pin_0_; +wire [0:0] cby_1__1__2_left_grid_pin_10_; +wire [0:0] cby_1__1__2_left_grid_pin_11_; +wire [0:0] cby_1__1__2_left_grid_pin_12_; +wire [0:0] cby_1__1__2_left_grid_pin_13_; +wire [0:0] cby_1__1__2_left_grid_pin_14_; +wire [0:0] cby_1__1__2_left_grid_pin_15_; +wire [0:0] cby_1__1__2_left_grid_pin_1_; +wire [0:0] cby_1__1__2_left_grid_pin_2_; +wire [0:0] cby_1__1__2_left_grid_pin_3_; +wire [0:0] cby_1__1__2_left_grid_pin_4_; +wire [0:0] cby_1__1__2_left_grid_pin_5_; +wire [0:0] cby_1__1__2_left_grid_pin_6_; +wire [0:0] cby_1__1__2_left_grid_pin_7_; +wire [0:0] cby_1__1__2_left_grid_pin_8_; +wire [0:0] cby_1__1__2_left_grid_pin_9_; +wire [0:0] cby_1__1__2_right_grid_pin_52_; +wire [0:0] cby_1__1__3_ccff_tail; +wire [0:19] cby_1__1__3_chany_bottom_out; +wire [0:19] cby_1__1__3_chany_top_out; +wire [0:0] cby_1__1__3_left_grid_pin_0_; +wire [0:0] cby_1__1__3_left_grid_pin_10_; +wire [0:0] cby_1__1__3_left_grid_pin_11_; +wire [0:0] cby_1__1__3_left_grid_pin_12_; +wire [0:0] cby_1__1__3_left_grid_pin_13_; +wire [0:0] cby_1__1__3_left_grid_pin_14_; +wire [0:0] cby_1__1__3_left_grid_pin_15_; +wire [0:0] cby_1__1__3_left_grid_pin_1_; +wire [0:0] cby_1__1__3_left_grid_pin_2_; +wire [0:0] cby_1__1__3_left_grid_pin_3_; +wire [0:0] cby_1__1__3_left_grid_pin_4_; +wire [0:0] cby_1__1__3_left_grid_pin_5_; +wire [0:0] cby_1__1__3_left_grid_pin_6_; +wire [0:0] cby_1__1__3_left_grid_pin_7_; +wire [0:0] cby_1__1__3_left_grid_pin_8_; +wire [0:0] cby_1__1__3_left_grid_pin_9_; +wire [0:0] cby_1__1__3_right_grid_pin_52_; +wire [0:0] direct_interc_0_out; +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_0_ccff_tail; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_1_ccff_tail; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_2_ccff_tail; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; +wire [0:0] grid_clb_3_ccff_tail; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper; +wire [0:0] grid_io_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_bottom_1_ccff_tail; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_0_ccff_tail; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_left_1_ccff_tail; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_0_ccff_tail; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_right_1_ccff_tail; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_0_ccff_tail; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; +wire [0:0] grid_io_top_1_ccff_tail; +wire [0:19] sb_0__0__0_chanx_right_out; +wire [0:19] sb_0__0__0_chany_top_out; +wire [0:0] sb_0__1__0_ccff_tail; +wire [0:19] sb_0__1__0_chanx_right_out; +wire [0:19] sb_0__1__0_chany_bottom_out; +wire [0:19] sb_0__1__0_chany_top_out; +wire [0:0] sb_0__2__0_ccff_tail; +wire [0:19] sb_0__2__0_chanx_right_out; +wire [0:19] sb_0__2__0_chany_bottom_out; +wire [0:0] sb_1__0__0_ccff_tail; +wire [0:19] sb_1__0__0_chanx_left_out; +wire [0:19] sb_1__0__0_chanx_right_out; +wire [0:19] sb_1__0__0_chany_top_out; +wire [0:0] sb_1__1__0_ccff_tail; +wire [0:19] sb_1__1__0_chanx_left_out; +wire [0:19] sb_1__1__0_chanx_right_out; +wire [0:19] sb_1__1__0_chany_bottom_out; +wire [0:19] sb_1__1__0_chany_top_out; +wire [0:0] sb_1__2__0_ccff_tail; +wire [0:19] sb_1__2__0_chanx_left_out; +wire [0:19] sb_1__2__0_chanx_right_out; +wire [0:19] sb_1__2__0_chany_bottom_out; +wire [0:0] sb_2__0__0_ccff_tail; +wire [0:19] sb_2__0__0_chanx_left_out; +wire [0:19] sb_2__0__0_chany_top_out; +wire [0:0] sb_2__1__0_ccff_tail; +wire [0:19] sb_2__1__0_chanx_left_out; +wire [0:19] sb_2__1__0_chany_bottom_out; +wire [0:19] sb_2__1__0_chany_top_out; +wire [0:0] sb_2__2__0_ccff_tail; +wire [0:19] sb_2__2__0_chanx_left_out; +wire [0:19] sb_2__2__0_chany_bottom_out; + +// +// +// +// + + grid_clb grid_clb_1__1_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__0_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__0_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__0_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__0_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__0_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__0_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__0_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__0_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__0_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__0_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__0_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__0_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__0_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__0_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__0_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_0__1__0_right_grid_pin_52_[0]), + .ccff_head(grid_io_left_0_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_0_ccff_tail[0])); + + grid_clb grid_clb_1__2_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), + .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), + .right_width_0_height_0__pin_0_(cby_1__1__1_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__1_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__1_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__1_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__1_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__1_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__1_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__1_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__1_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__1_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__1_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__1_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__1_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__1_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__1_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_0__1__1_right_grid_pin_52_[0]), + .ccff_head(grid_io_left_1_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_1_ccff_tail[0])); + + grid_clb grid_clb_2__1_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__2_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__2_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__2_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__2_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__2_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__2_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__2_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__2_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__2_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__2_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__2_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__2_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__2_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__2_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__2_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__2_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__0_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_2_ccff_tail[0])); + + grid_clb grid_clb_2__2_ ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), + .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), + .right_width_0_height_0__pin_0_(cby_1__1__3_left_grid_pin_0_[0]), + .right_width_0_height_0__pin_1_(cby_1__1__3_left_grid_pin_1_[0]), + .right_width_0_height_0__pin_2_(cby_1__1__3_left_grid_pin_2_[0]), + .right_width_0_height_0__pin_3_(cby_1__1__3_left_grid_pin_3_[0]), + .right_width_0_height_0__pin_4_(cby_1__1__3_left_grid_pin_4_[0]), + .right_width_0_height_0__pin_5_(cby_1__1__3_left_grid_pin_5_[0]), + .right_width_0_height_0__pin_6_(cby_1__1__3_left_grid_pin_6_[0]), + .right_width_0_height_0__pin_7_(cby_1__1__3_left_grid_pin_7_[0]), + .right_width_0_height_0__pin_8_(cby_1__1__3_left_grid_pin_8_[0]), + .right_width_0_height_0__pin_9_(cby_1__1__3_left_grid_pin_9_[0]), + .right_width_0_height_0__pin_10_(cby_1__1__3_left_grid_pin_10_[0]), + .right_width_0_height_0__pin_11_(cby_1__1__3_left_grid_pin_11_[0]), + .right_width_0_height_0__pin_12_(cby_1__1__3_left_grid_pin_12_[0]), + .right_width_0_height_0__pin_13_(cby_1__1__3_left_grid_pin_13_[0]), + .right_width_0_height_0__pin_14_(cby_1__1__3_left_grid_pin_14_[0]), + .right_width_0_height_0__pin_15_(cby_1__1__3_left_grid_pin_15_[0]), + .bottom_width_0_height_0__pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), + .bottom_width_0_height_0__pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), + .bottom_width_0_height_0__pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), + .bottom_width_0_height_0__pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), + .bottom_width_0_height_0__pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), + .bottom_width_0_height_0__pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), + .bottom_width_0_height_0__pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), + .bottom_width_0_height_0__pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), + .bottom_width_0_height_0__pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), + .bottom_width_0_height_0__pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), + .bottom_width_0_height_0__pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), + .bottom_width_0_height_0__pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), + .bottom_width_0_height_0__pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), + .bottom_width_0_height_0__pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), + .bottom_width_0_height_0__pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), + .bottom_width_0_height_0__pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .left_width_0_height_0__pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__1_ccff_tail[0]), + .right_width_0_height_0__pin_34_upper(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), + .right_width_0_height_0__pin_34_lower(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), + .right_width_0_height_0__pin_35_upper(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), + .right_width_0_height_0__pin_35_lower(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), + .right_width_0_height_0__pin_36_upper(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), + .right_width_0_height_0__pin_36_lower(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), + .right_width_0_height_0__pin_37_upper(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), + .right_width_0_height_0__pin_37_lower(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), + .right_width_0_height_0__pin_38_upper(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), + .right_width_0_height_0__pin_38_lower(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), + .right_width_0_height_0__pin_39_upper(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), + .right_width_0_height_0__pin_39_lower(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), + .right_width_0_height_0__pin_40_upper(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), + .right_width_0_height_0__pin_40_lower(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), + .right_width_0_height_0__pin_41_upper(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .right_width_0_height_0__pin_41_lower(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), + .bottom_width_0_height_0__pin_42_upper(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), + .bottom_width_0_height_0__pin_42_lower(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), + .bottom_width_0_height_0__pin_43_upper(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), + .bottom_width_0_height_0__pin_43_lower(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), + .bottom_width_0_height_0__pin_44_upper(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), + .bottom_width_0_height_0__pin_44_lower(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), + .bottom_width_0_height_0__pin_45_upper(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), + .bottom_width_0_height_0__pin_45_lower(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), + .bottom_width_0_height_0__pin_46_upper(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), + .bottom_width_0_height_0__pin_46_lower(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), + .bottom_width_0_height_0__pin_47_upper(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), + .bottom_width_0_height_0__pin_47_lower(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), + .bottom_width_0_height_0__pin_48_upper(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), + .bottom_width_0_height_0__pin_48_lower(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), + .bottom_width_0_height_0__pin_49_upper(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .bottom_width_0_height_0__pin_49_lower(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(grid_clb_3_ccff_tail[0])); + + grid_io_top grid_io_top_1__3_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .ccff_head(cbx_1__2__0_ccff_tail[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_0_ccff_tail[0])); + + grid_io_top grid_io_top_2__3_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[1]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[1]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[1]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[1]), + .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .ccff_head(cbx_1__2__1_ccff_tail[0]), + .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_top_1_ccff_tail[0])); + + grid_io_right grid_io_right_3__1_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[2]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[2]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[2]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[2]), + .left_width_0_height_0__pin_0_(cby_1__1__2_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__2_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_0_ccff_tail[0])); + + grid_io_right grid_io_right_3__2_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[3]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[3]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[3]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[3]), + .left_width_0_height_0__pin_0_(cby_1__1__3_right_grid_pin_52_[0]), + .ccff_head(cby_1__1__3_ccff_tail[0]), + .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_right_1_ccff_tail[0])); + + grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[4]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[4]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[4]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[4]), + .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .ccff_head(cbx_1__0__0_ccff_tail[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_bottom_0_ccff_tail[0])); + + grid_io_bottom grid_io_bottom_2__0_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[5]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[5]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[5]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[5]), + .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .ccff_head(cbx_1__0__1_ccff_tail[0]), + .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_bottom_1_ccff_tail[0])); + + grid_io_left grid_io_left_0__1_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[6]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[6]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[6]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[6]), + .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_head(cby_0__1__0_ccff_tail[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_0_ccff_tail[0])); + + grid_io_left grid_io_left_0__2_ ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[7]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[7]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[7]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[7]), + .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_head(cby_0__1__1_ccff_tail[0]), + .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .ccff_tail(grid_io_left_1_ccff_tail[0])); + + sb_0__0_ sb_0__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_bottom_0_ccff_tail[0]), + .chany_top_out(sb_0__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), + .ccff_tail(ccff_tail[0])); + + sb_0__1_ sb_0__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_upper[0]), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(cbx_1__1__0_ccff_tail[0]), + .chany_top_out(sb_0__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__1__0_ccff_tail[0])); + + sb_0__2_ sb_0__2_ ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), + .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), + .ccff_head(grid_io_top_0_ccff_tail[0]), + .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_tail(sb_0__2__0_ccff_tail[0])); + + sb_1__0_ sb_1__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_lower[0]), + .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_upper[0]), + .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_0_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_0_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_0_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_0_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_0_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_0_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_0_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_bottom_1_ccff_tail[0]), + .chany_top_out(sb_1__0__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__0__0_ccff_tail[0])); + + sb_1__1_ sb_1__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_lower[0]), + .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), + .right_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_upper[0]), + .right_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_upper[0]), + .right_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_upper[0]), + .right_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_upper[0]), + .right_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_upper[0]), + .right_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_upper[0]), + .right_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_upper[0]), + .right_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_upper[0]), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), + .bottom_left_grid_pin_34_(grid_clb_0_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_0_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_0_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_0_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_0_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_0_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_0_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_0_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_1_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_1_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_1_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_1_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_1_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_1_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_1_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_1_bottom_width_0_height_0__pin_49_lower[0]), + .ccff_head(cbx_1__1__1_ccff_tail[0]), + .chany_top_out(sb_1__1__0_chany_top_out[0:19]), + .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__1__0_ccff_tail[0])); + + sb_1__2_ sb_1__2_ ( + .prog_clk(prog_clk[0]), + .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), + .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), + .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), + .bottom_left_grid_pin_34_(grid_clb_1_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_1_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_1_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_1_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_1_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_1_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_1_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_1_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_top_1_ccff_tail[0]), + .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), + .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_1__2__0_ccff_tail[0])); + + sb_2__0_ sb_2__0_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__2_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_lower[0]), + .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), + .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_2_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_2_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_2_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_2_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_2_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_2_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_2_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_2_bottom_width_0_height_0__pin_49_lower[0]), + .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), + .ccff_head(grid_io_right_0_ccff_tail[0]), + .chany_top_out(sb_2__0__0_chany_top_out[0:19]), + .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__0__0_ccff_tail[0])); + + sb_2__1_ sb_2__1_ ( + .prog_clk(prog_clk[0]), + .chany_top_in(cby_1__1__3_chany_bottom_out[0:19]), + .top_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_lower[0]), + .top_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_lower[0]), + .top_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_lower[0]), + .top_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_lower[0]), + .top_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_lower[0]), + .top_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_lower[0]), + .top_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_lower[0]), + .top_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_lower[0]), + .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), + .chany_bottom_in(cby_1__1__2_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_34_(grid_clb_2_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_2_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_2_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_2_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_2_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_2_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_2_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_2_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), + .left_top_grid_pin_42_(grid_clb_3_bottom_width_0_height_0__pin_42_lower[0]), + .left_top_grid_pin_43_(grid_clb_3_bottom_width_0_height_0__pin_43_lower[0]), + .left_top_grid_pin_44_(grid_clb_3_bottom_width_0_height_0__pin_44_lower[0]), + .left_top_grid_pin_45_(grid_clb_3_bottom_width_0_height_0__pin_45_lower[0]), + .left_top_grid_pin_46_(grid_clb_3_bottom_width_0_height_0__pin_46_lower[0]), + .left_top_grid_pin_47_(grid_clb_3_bottom_width_0_height_0__pin_47_lower[0]), + .left_top_grid_pin_48_(grid_clb_3_bottom_width_0_height_0__pin_48_lower[0]), + .left_top_grid_pin_49_(grid_clb_3_bottom_width_0_height_0__pin_49_lower[0]), + .ccff_head(grid_io_right_1_ccff_tail[0]), + .chany_top_out(sb_2__1__0_chany_top_out[0:19]), + .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__1__0_ccff_tail[0])); + + sb_2__2_ sb_2__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(cby_1__1__3_chany_top_out[0:19]), + .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), + .bottom_left_grid_pin_34_(grid_clb_3_right_width_0_height_0__pin_34_upper[0]), + .bottom_left_grid_pin_35_(grid_clb_3_right_width_0_height_0__pin_35_upper[0]), + .bottom_left_grid_pin_36_(grid_clb_3_right_width_0_height_0__pin_36_upper[0]), + .bottom_left_grid_pin_37_(grid_clb_3_right_width_0_height_0__pin_37_upper[0]), + .bottom_left_grid_pin_38_(grid_clb_3_right_width_0_height_0__pin_38_upper[0]), + .bottom_left_grid_pin_39_(grid_clb_3_right_width_0_height_0__pin_39_upper[0]), + .bottom_left_grid_pin_40_(grid_clb_3_right_width_0_height_0__pin_40_upper[0]), + .bottom_left_grid_pin_41_(grid_clb_3_right_width_0_height_0__pin_41_upper[0]), + .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), + .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), + .ccff_head(ccff_head[0]), + .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), + .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), + .ccff_tail(sb_2__2__0_ccff_tail[0])); + + cbx_1__0_ cbx_1__0_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), + .ccff_head(sb_1__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__0__0_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__0__0_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__0__0_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__0__0_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__0__0_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__0__0_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__0__0_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__0__0_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__0__0_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__0__0_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__0__0_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__0__0_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__0__0_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__0__0_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__0__0_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__0__0_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), + .ccff_tail(cbx_1__0__0_ccff_tail[0])); + + cbx_1__0_ cbx_2__0_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), + .ccff_head(sb_2__0__0_ccff_tail[0]), + .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__0__1_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__0__1_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__0__1_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__0__1_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__0__1_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__0__1_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__0__1_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__0__1_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__0__1_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__0__1_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__0__1_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__0__1_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__0__1_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__0__1_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__0__1_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__0__1_top_grid_pin_31_[0]), + .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), + .ccff_tail(cbx_1__0__1_ccff_tail[0])); + + cbx_1__1_ cbx_1__1_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), + .ccff_head(sb_1__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__1__0_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__1__0_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__1__0_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__1__0_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__1__0_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__1__0_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__1__0_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__1__0_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__1__0_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__1__0_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__1__0_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__1__0_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__1__0_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__1__0_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__1__0_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__1__0_top_grid_pin_31_[0]), + .ccff_tail(cbx_1__1__0_ccff_tail[0])); + + cbx_1__1_ cbx_2__1_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), + .ccff_head(sb_2__1__0_ccff_tail[0]), + .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), + .top_grid_pin_16_(cbx_1__1__1_top_grid_pin_16_[0]), + .top_grid_pin_17_(cbx_1__1__1_top_grid_pin_17_[0]), + .top_grid_pin_18_(cbx_1__1__1_top_grid_pin_18_[0]), + .top_grid_pin_19_(cbx_1__1__1_top_grid_pin_19_[0]), + .top_grid_pin_20_(cbx_1__1__1_top_grid_pin_20_[0]), + .top_grid_pin_21_(cbx_1__1__1_top_grid_pin_21_[0]), + .top_grid_pin_22_(cbx_1__1__1_top_grid_pin_22_[0]), + .top_grid_pin_23_(cbx_1__1__1_top_grid_pin_23_[0]), + .top_grid_pin_24_(cbx_1__1__1_top_grid_pin_24_[0]), + .top_grid_pin_25_(cbx_1__1__1_top_grid_pin_25_[0]), + .top_grid_pin_26_(cbx_1__1__1_top_grid_pin_26_[0]), + .top_grid_pin_27_(cbx_1__1__1_top_grid_pin_27_[0]), + .top_grid_pin_28_(cbx_1__1__1_top_grid_pin_28_[0]), + .top_grid_pin_29_(cbx_1__1__1_top_grid_pin_29_[0]), + .top_grid_pin_30_(cbx_1__1__1_top_grid_pin_30_[0]), + .top_grid_pin_31_(cbx_1__1__1_top_grid_pin_31_[0]), + .ccff_tail(cbx_1__1__1_ccff_tail[0])); + + cbx_1__2_ cbx_1__2_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), + .ccff_head(sb_1__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), + .ccff_tail(cbx_1__2__0_ccff_tail[0])); + + cbx_1__2_ cbx_2__2_ ( + .prog_clk(prog_clk[0]), + .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), + .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), + .ccff_head(sb_2__2__0_ccff_tail[0]), + .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), + .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), + .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), + .ccff_tail(cbx_1__2__1_ccff_tail[0])); + + cby_0__1_ cby_0__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__1__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__0_chany_top_out[0:19]), + .right_grid_pin_52_(cby_0__1__0_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), + .ccff_tail(cby_0__1__0_ccff_tail[0])); + + cby_0__1_ cby_0__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), + .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), + .ccff_head(sb_0__2__0_ccff_tail[0]), + .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_0__1__1_chany_top_out[0:19]), + .right_grid_pin_52_(cby_0__1__1_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), + .ccff_tail(cby_0__1__1_ccff_tail[0])); + + cby_1__1_ cby_1__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_0_ccff_tail[0]), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__0_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__0_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__0_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__0_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__0_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__0_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__0_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__0_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__0_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__0_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__0_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__0_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__0_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__0_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__0_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__0_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__0_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__0_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__0_ccff_tail[0])); + + cby_1__1_ cby_1__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), + .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_1_ccff_tail[0]), + .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__1_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__1_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__1_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__1_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__1_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__1_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__1_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__1_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__1_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__1_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__1_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__1_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__1_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__1_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__1_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__1_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__1_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__1_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__1_ccff_tail[0])); + + cby_1__1_ cby_2__1_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), + .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_2_ccff_tail[0]), + .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__2_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__2_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__2_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__2_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__2_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__2_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__2_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__2_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__2_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__2_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__2_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__2_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__2_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__2_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__2_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__2_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__2_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__2_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__2_ccff_tail[0])); + + cby_1__1_ cby_2__2_ ( + .prog_clk(prog_clk[0]), + .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), + .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), + .ccff_head(grid_clb_3_ccff_tail[0]), + .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:19]), + .chany_top_out(cby_1__1__3_chany_top_out[0:19]), + .right_grid_pin_52_(cby_1__1__3_right_grid_pin_52_[0]), + .left_grid_pin_0_(cby_1__1__3_left_grid_pin_0_[0]), + .left_grid_pin_1_(cby_1__1__3_left_grid_pin_1_[0]), + .left_grid_pin_2_(cby_1__1__3_left_grid_pin_2_[0]), + .left_grid_pin_3_(cby_1__1__3_left_grid_pin_3_[0]), + .left_grid_pin_4_(cby_1__1__3_left_grid_pin_4_[0]), + .left_grid_pin_5_(cby_1__1__3_left_grid_pin_5_[0]), + .left_grid_pin_6_(cby_1__1__3_left_grid_pin_6_[0]), + .left_grid_pin_7_(cby_1__1__3_left_grid_pin_7_[0]), + .left_grid_pin_8_(cby_1__1__3_left_grid_pin_8_[0]), + .left_grid_pin_9_(cby_1__1__3_left_grid_pin_9_[0]), + .left_grid_pin_10_(cby_1__1__3_left_grid_pin_10_[0]), + .left_grid_pin_11_(cby_1__1__3_left_grid_pin_11_[0]), + .left_grid_pin_12_(cby_1__1__3_left_grid_pin_12_[0]), + .left_grid_pin_13_(cby_1__1__3_left_grid_pin_13_[0]), + .left_grid_pin_14_(cby_1__1__3_left_grid_pin_14_[0]), + .left_grid_pin_15_(cby_1__1__3_left_grid_pin_15_[0]), + .ccff_tail(cby_1__1__3_ccff_tail[0])); + + direct_interc direct_interc_0_ ( + .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_0_out[0])); + + direct_interc direct_interc_1_ ( + .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_1_out[0])); + + direct_interc direct_interc_2_ ( + .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), + .out(direct_interc_2_out[0])); + + direct_interc direct_interc_3_ ( + .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_3_out[0])); + + direct_interc direct_interc_4_ ( + .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_4_out[0])); + + direct_interc direct_interc_5_ ( + .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), + .out(direct_interc_5_out[0])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v new file mode 100644 index 0000000..e0f7d9d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v @@ -0,0 +1,292 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module grid_clb(prog_clk, + Test_en, + clk, + top_width_0_height_0__pin_32_, + top_width_0_height_0__pin_33_, + right_width_0_height_0__pin_0_, + right_width_0_height_0__pin_1_, + right_width_0_height_0__pin_2_, + right_width_0_height_0__pin_3_, + right_width_0_height_0__pin_4_, + right_width_0_height_0__pin_5_, + right_width_0_height_0__pin_6_, + right_width_0_height_0__pin_7_, + right_width_0_height_0__pin_8_, + right_width_0_height_0__pin_9_, + right_width_0_height_0__pin_10_, + right_width_0_height_0__pin_11_, + right_width_0_height_0__pin_12_, + right_width_0_height_0__pin_13_, + right_width_0_height_0__pin_14_, + right_width_0_height_0__pin_15_, + bottom_width_0_height_0__pin_16_, + bottom_width_0_height_0__pin_17_, + bottom_width_0_height_0__pin_18_, + bottom_width_0_height_0__pin_19_, + bottom_width_0_height_0__pin_20_, + bottom_width_0_height_0__pin_21_, + bottom_width_0_height_0__pin_22_, + bottom_width_0_height_0__pin_23_, + bottom_width_0_height_0__pin_24_, + bottom_width_0_height_0__pin_25_, + bottom_width_0_height_0__pin_26_, + bottom_width_0_height_0__pin_27_, + bottom_width_0_height_0__pin_28_, + bottom_width_0_height_0__pin_29_, + bottom_width_0_height_0__pin_30_, + bottom_width_0_height_0__pin_31_, + left_width_0_height_0__pin_52_, + ccff_head, + right_width_0_height_0__pin_34_upper, + right_width_0_height_0__pin_34_lower, + right_width_0_height_0__pin_35_upper, + right_width_0_height_0__pin_35_lower, + right_width_0_height_0__pin_36_upper, + right_width_0_height_0__pin_36_lower, + right_width_0_height_0__pin_37_upper, + right_width_0_height_0__pin_37_lower, + right_width_0_height_0__pin_38_upper, + right_width_0_height_0__pin_38_lower, + right_width_0_height_0__pin_39_upper, + right_width_0_height_0__pin_39_lower, + right_width_0_height_0__pin_40_upper, + right_width_0_height_0__pin_40_lower, + right_width_0_height_0__pin_41_upper, + right_width_0_height_0__pin_41_lower, + bottom_width_0_height_0__pin_42_upper, + bottom_width_0_height_0__pin_42_lower, + bottom_width_0_height_0__pin_43_upper, + bottom_width_0_height_0__pin_43_lower, + bottom_width_0_height_0__pin_44_upper, + bottom_width_0_height_0__pin_44_lower, + bottom_width_0_height_0__pin_45_upper, + bottom_width_0_height_0__pin_45_lower, + bottom_width_0_height_0__pin_46_upper, + bottom_width_0_height_0__pin_46_lower, + bottom_width_0_height_0__pin_47_upper, + bottom_width_0_height_0__pin_47_lower, + bottom_width_0_height_0__pin_48_upper, + bottom_width_0_height_0__pin_48_lower, + bottom_width_0_height_0__pin_49_upper, + bottom_width_0_height_0__pin_49_lower, + bottom_width_0_height_0__pin_50_, + bottom_width_0_height_0__pin_51_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +input [0:0] top_width_0_height_0__pin_32_; +// +input [0:0] top_width_0_height_0__pin_33_; +// +input [0:0] right_width_0_height_0__pin_0_; +// +input [0:0] right_width_0_height_0__pin_1_; +// +input [0:0] right_width_0_height_0__pin_2_; +// +input [0:0] right_width_0_height_0__pin_3_; +// +input [0:0] right_width_0_height_0__pin_4_; +// +input [0:0] right_width_0_height_0__pin_5_; +// +input [0:0] right_width_0_height_0__pin_6_; +// +input [0:0] right_width_0_height_0__pin_7_; +// +input [0:0] right_width_0_height_0__pin_8_; +// +input [0:0] right_width_0_height_0__pin_9_; +// +input [0:0] right_width_0_height_0__pin_10_; +// +input [0:0] right_width_0_height_0__pin_11_; +// +input [0:0] right_width_0_height_0__pin_12_; +// +input [0:0] right_width_0_height_0__pin_13_; +// +input [0:0] right_width_0_height_0__pin_14_; +// +input [0:0] right_width_0_height_0__pin_15_; +// +input [0:0] bottom_width_0_height_0__pin_16_; +// +input [0:0] bottom_width_0_height_0__pin_17_; +// +input [0:0] bottom_width_0_height_0__pin_18_; +// +input [0:0] bottom_width_0_height_0__pin_19_; +// +input [0:0] bottom_width_0_height_0__pin_20_; +// +input [0:0] bottom_width_0_height_0__pin_21_; +// +input [0:0] bottom_width_0_height_0__pin_22_; +// +input [0:0] bottom_width_0_height_0__pin_23_; +// +input [0:0] bottom_width_0_height_0__pin_24_; +// +input [0:0] bottom_width_0_height_0__pin_25_; +// +input [0:0] bottom_width_0_height_0__pin_26_; +// +input [0:0] bottom_width_0_height_0__pin_27_; +// +input [0:0] bottom_width_0_height_0__pin_28_; +// +input [0:0] bottom_width_0_height_0__pin_29_; +// +input [0:0] bottom_width_0_height_0__pin_30_; +// +input [0:0] bottom_width_0_height_0__pin_31_; +// +input [0:0] left_width_0_height_0__pin_52_; +// +input [0:0] ccff_head; +// +output [0:0] right_width_0_height_0__pin_34_upper; +// +output [0:0] right_width_0_height_0__pin_34_lower; +// +output [0:0] right_width_0_height_0__pin_35_upper; +// +output [0:0] right_width_0_height_0__pin_35_lower; +// +output [0:0] right_width_0_height_0__pin_36_upper; +// +output [0:0] right_width_0_height_0__pin_36_lower; +// +output [0:0] right_width_0_height_0__pin_37_upper; +// +output [0:0] right_width_0_height_0__pin_37_lower; +// +output [0:0] right_width_0_height_0__pin_38_upper; +// +output [0:0] right_width_0_height_0__pin_38_lower; +// +output [0:0] right_width_0_height_0__pin_39_upper; +// +output [0:0] right_width_0_height_0__pin_39_lower; +// +output [0:0] right_width_0_height_0__pin_40_upper; +// +output [0:0] right_width_0_height_0__pin_40_lower; +// +output [0:0] right_width_0_height_0__pin_41_upper; +// +output [0:0] right_width_0_height_0__pin_41_lower; +// +output [0:0] bottom_width_0_height_0__pin_42_upper; +// +output [0:0] bottom_width_0_height_0__pin_42_lower; +// +output [0:0] bottom_width_0_height_0__pin_43_upper; +// +output [0:0] bottom_width_0_height_0__pin_43_lower; +// +output [0:0] bottom_width_0_height_0__pin_44_upper; +// +output [0:0] bottom_width_0_height_0__pin_44_lower; +// +output [0:0] bottom_width_0_height_0__pin_45_upper; +// +output [0:0] bottom_width_0_height_0__pin_45_lower; +// +output [0:0] bottom_width_0_height_0__pin_46_upper; +// +output [0:0] bottom_width_0_height_0__pin_46_lower; +// +output [0:0] bottom_width_0_height_0__pin_47_upper; +// +output [0:0] bottom_width_0_height_0__pin_47_lower; +// +output [0:0] bottom_width_0_height_0__pin_48_upper; +// +output [0:0] bottom_width_0_height_0__pin_48_lower; +// +output [0:0] bottom_width_0_height_0__pin_49_upper; +// +output [0:0] bottom_width_0_height_0__pin_49_lower; +// +output [0:0] bottom_width_0_height_0__pin_50_; +// +output [0:0] bottom_width_0_height_0__pin_51_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + + +// +// +// + assign right_width_0_height_0__pin_34_lower[0] = right_width_0_height_0__pin_34_upper[0]; + assign right_width_0_height_0__pin_35_lower[0] = right_width_0_height_0__pin_35_upper[0]; + assign right_width_0_height_0__pin_36_lower[0] = right_width_0_height_0__pin_36_upper[0]; + assign right_width_0_height_0__pin_37_lower[0] = right_width_0_height_0__pin_37_upper[0]; + assign right_width_0_height_0__pin_38_lower[0] = right_width_0_height_0__pin_38_upper[0]; + assign right_width_0_height_0__pin_39_lower[0] = right_width_0_height_0__pin_39_upper[0]; + assign right_width_0_height_0__pin_40_lower[0] = right_width_0_height_0__pin_40_upper[0]; + assign right_width_0_height_0__pin_41_lower[0] = right_width_0_height_0__pin_41_upper[0]; + assign bottom_width_0_height_0__pin_42_lower[0] = bottom_width_0_height_0__pin_42_upper[0]; + assign bottom_width_0_height_0__pin_43_lower[0] = bottom_width_0_height_0__pin_43_upper[0]; + assign bottom_width_0_height_0__pin_44_lower[0] = bottom_width_0_height_0__pin_44_upper[0]; + assign bottom_width_0_height_0__pin_45_lower[0] = bottom_width_0_height_0__pin_45_upper[0]; + assign bottom_width_0_height_0__pin_46_lower[0] = bottom_width_0_height_0__pin_46_upper[0]; + assign bottom_width_0_height_0__pin_47_lower[0] = bottom_width_0_height_0__pin_47_upper[0]; + assign bottom_width_0_height_0__pin_48_lower[0] = bottom_width_0_height_0__pin_48_upper[0]; + assign bottom_width_0_height_0__pin_49_lower[0] = bottom_width_0_height_0__pin_49_upper[0]; +// + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .clb_I0({right_width_0_height_0__pin_0_[0], right_width_0_height_0__pin_1_[0], right_width_0_height_0__pin_2_[0], right_width_0_height_0__pin_3_[0]}), + .clb_I1({right_width_0_height_0__pin_4_[0], right_width_0_height_0__pin_5_[0], right_width_0_height_0__pin_6_[0], right_width_0_height_0__pin_7_[0]}), + .clb_I2({right_width_0_height_0__pin_8_[0], right_width_0_height_0__pin_9_[0], right_width_0_height_0__pin_10_[0], right_width_0_height_0__pin_11_[0]}), + .clb_I3({right_width_0_height_0__pin_12_[0], right_width_0_height_0__pin_13_[0], right_width_0_height_0__pin_14_[0], right_width_0_height_0__pin_15_[0]}), + .clb_I4({bottom_width_0_height_0__pin_16_[0], bottom_width_0_height_0__pin_17_[0], bottom_width_0_height_0__pin_18_[0], bottom_width_0_height_0__pin_19_[0]}), + .clb_I5({bottom_width_0_height_0__pin_20_[0], bottom_width_0_height_0__pin_21_[0], bottom_width_0_height_0__pin_22_[0], bottom_width_0_height_0__pin_23_[0]}), + .clb_I6({bottom_width_0_height_0__pin_24_[0], bottom_width_0_height_0__pin_25_[0], bottom_width_0_height_0__pin_26_[0], bottom_width_0_height_0__pin_27_[0]}), + .clb_I7({bottom_width_0_height_0__pin_28_[0], bottom_width_0_height_0__pin_29_[0], bottom_width_0_height_0__pin_30_[0], bottom_width_0_height_0__pin_31_[0]}), + .clb_regin(top_width_0_height_0__pin_32_[0]), + .clb_scin(top_width_0_height_0__pin_33_[0]), + .clb_clk(left_width_0_height_0__pin_52_[0]), + .ccff_head(ccff_head[0]), + .clb_O({right_width_0_height_0__pin_34_upper[0], right_width_0_height_0__pin_35_upper[0], right_width_0_height_0__pin_36_upper[0], right_width_0_height_0__pin_37_upper[0], right_width_0_height_0__pin_38_upper[0], right_width_0_height_0__pin_39_upper[0], right_width_0_height_0__pin_40_upper[0], right_width_0_height_0__pin_41_upper[0], bottom_width_0_height_0__pin_42_upper[0], bottom_width_0_height_0__pin_43_upper[0], bottom_width_0_height_0__pin_44_upper[0], bottom_width_0_height_0__pin_45_upper[0], bottom_width_0_height_0__pin_46_upper[0], bottom_width_0_height_0__pin_47_upper[0], bottom_width_0_height_0__pin_48_upper[0], bottom_width_0_height_0__pin_49_upper[0]}), + .clb_regout(bottom_width_0_height_0__pin_50_[0]), + .clb_scout(bottom_width_0_height_0__pin_51_[0]), + .ccff_tail(ccff_tail[0])); + +endmodule +// + + +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v new file mode 100644 index 0000000..654b409 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v @@ -0,0 +1,75 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module grid_io_bottom(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + top_width_0_height_0__pin_0_, + ccff_head, + top_width_0_height_0__pin_1_upper, + top_width_0_height_0__pin_1_lower, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] top_width_0_height_0__pin_0_; +// +input [0:0] ccff_head; +// +output [0:0] top_width_0_height_0__pin_1_upper; +// +output [0:0] top_width_0_height_0__pin_1_lower; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + + +// +// +// + assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; +// + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .io_outpad(top_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_head[0]), + .io_inpad(top_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0])); + +endmodule +// + + +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v new file mode 100644 index 0000000..2426295 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v @@ -0,0 +1,75 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module grid_io_left(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + right_width_0_height_0__pin_0_, + ccff_head, + right_width_0_height_0__pin_1_upper, + right_width_0_height_0__pin_1_lower, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] right_width_0_height_0__pin_0_; +// +input [0:0] ccff_head; +// +output [0:0] right_width_0_height_0__pin_1_upper; +// +output [0:0] right_width_0_height_0__pin_1_lower; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + + +// +// +// + assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0]; +// + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .io_outpad(right_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_head[0]), + .io_inpad(right_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0])); + +endmodule +// + + +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v new file mode 100644 index 0000000..2d402ca --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v @@ -0,0 +1,75 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module grid_io_right(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + left_width_0_height_0__pin_0_, + ccff_head, + left_width_0_height_0__pin_1_upper, + left_width_0_height_0__pin_1_lower, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] left_width_0_height_0__pin_0_; +// +input [0:0] ccff_head; +// +output [0:0] left_width_0_height_0__pin_1_upper; +// +output [0:0] left_width_0_height_0__pin_1_lower; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + + +// +// +// + assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0]; +// + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .io_outpad(left_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_head[0]), + .io_inpad(left_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0])); + +endmodule +// + + +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v new file mode 100644 index 0000000..c21d0d6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v @@ -0,0 +1,75 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module grid_io_top(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + bottom_width_0_height_0__pin_0_, + ccff_head, + bottom_width_0_height_0__pin_1_upper, + bottom_width_0_height_0__pin_1_lower, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] bottom_width_0_height_0__pin_0_; +// +input [0:0] ccff_head; +// +output [0:0] bottom_width_0_height_0__pin_1_upper; +// +output [0:0] bottom_width_0_height_0__pin_1_lower; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + + +// +// +// + assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0]; +// + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .io_outpad(bottom_width_0_height_0__pin_0_[0]), + .ccff_head(ccff_head[0]), + .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), + .ccff_tail(ccff_tail[0])); + +endmodule +// + + +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v new file mode 100644 index 0000000..9b755b2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v @@ -0,0 +1,598 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module logical_tile_clb_mode_clb_(prog_clk, + Test_en, + clk, + clb_I0, + clb_I1, + clb_I2, + clb_I3, + clb_I4, + clb_I5, + clb_I6, + clb_I7, + clb_regin, + clb_scin, + clb_clk, + ccff_head, + clb_O, + clb_regout, + clb_scout, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +input [0:3] clb_I0; +// +input [0:3] clb_I1; +// +input [0:3] clb_I2; +// +input [0:3] clb_I3; +// +input [0:3] clb_I4; +// +input [0:3] clb_I5; +// +input [0:3] clb_I6; +// +input [0:3] clb_I7; +// +input [0:0] clb_regin; +// +input [0:0] clb_scin; +// +input [0:0] clb_clk; +// +input [0:0] ccff_head; +// +output [0:15] clb_O; +// +output [0:0] clb_regout; +// +output [0:0] clb_scout; +// +output [0:0] ccff_tail; + +// +wire [0:3] clb_I0; +wire [0:3] clb_I1; +wire [0:3] clb_I2; +wire [0:3] clb_I3; +wire [0:3] clb_I4; +wire [0:3] clb_I5; +wire [0:3] clb_I6; +wire [0:3] clb_I7; +wire [0:0] clb_regin; +wire [0:0] clb_scin; +wire [0:0] clb_clk; +wire [0:15] clb_O; +wire [0:0] clb_regout; +wire [0:0] clb_scout; +// + + +// +// + + +wire [0:0] direct_interc_18_out; +wire [0:0] direct_interc_19_out; +wire [0:0] direct_interc_20_out; +wire [0:0] direct_interc_21_out; +wire [0:0] direct_interc_22_out; +wire [0:0] direct_interc_23_out; +wire [0:0] direct_interc_24_out; +wire [0:0] direct_interc_25_out; +wire [0:0] direct_interc_26_out; +wire [0:0] direct_interc_27_out; +wire [0:0] direct_interc_28_out; +wire [0:0] direct_interc_29_out; +wire [0:0] direct_interc_30_out; +wire [0:0] direct_interc_31_out; +wire [0:0] direct_interc_32_out; +wire [0:0] direct_interc_33_out; +wire [0:0] direct_interc_34_out; +wire [0:0] direct_interc_35_out; +wire [0:0] direct_interc_36_out; +wire [0:0] direct_interc_37_out; +wire [0:0] direct_interc_38_out; +wire [0:0] direct_interc_39_out; +wire [0:0] direct_interc_40_out; +wire [0:0] direct_interc_41_out; +wire [0:0] direct_interc_42_out; +wire [0:0] direct_interc_43_out; +wire [0:0] direct_interc_44_out; +wire [0:0] direct_interc_45_out; +wire [0:0] direct_interc_46_out; +wire [0:0] direct_interc_47_out; +wire [0:0] direct_interc_48_out; +wire [0:0] direct_interc_49_out; +wire [0:0] direct_interc_50_out; +wire [0:0] direct_interc_51_out; +wire [0:0] direct_interc_52_out; +wire [0:0] direct_interc_53_out; +wire [0:0] direct_interc_54_out; +wire [0:0] direct_interc_55_out; +wire [0:0] direct_interc_56_out; +wire [0:0] direct_interc_57_out; +wire [0:0] direct_interc_58_out; +wire [0:0] direct_interc_59_out; +wire [0:0] direct_interc_60_out; +wire [0:0] direct_interc_61_out; +wire [0:0] direct_interc_62_out; +wire [0:0] direct_interc_63_out; +wire [0:0] direct_interc_64_out; +wire [0:0] direct_interc_65_out; +wire [0:0] direct_interc_66_out; +wire [0:0] direct_interc_67_out; +wire [0:0] direct_interc_68_out; +wire [0:0] direct_interc_69_out; +wire [0:0] direct_interc_70_out; +wire [0:0] direct_interc_71_out; +wire [0:0] direct_interc_72_out; +wire [0:0] direct_interc_73_out; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout; +wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout; +wire [0:0] logical_tile_clb_mode_default__fle_7_fle_scout; + +// +// +// +// + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}), + .fle_regin(direct_interc_22_out[0]), + .fle_scin(direct_interc_23_out[0]), + .fle_clk(direct_interc_24_out[0]), + .ccff_head(ccff_head[0]), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}), + .fle_regin(direct_interc_29_out[0]), + .fle_scin(direct_interc_30_out[0]), + .fle_clk(direct_interc_31_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}), + .fle_regin(direct_interc_36_out[0]), + .fle_scin(direct_interc_37_out[0]), + .fle_clk(direct_interc_38_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}), + .fle_regin(direct_interc_43_out[0]), + .fle_scin(direct_interc_44_out[0]), + .fle_clk(direct_interc_45_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}), + .fle_regin(direct_interc_50_out[0]), + .fle_scin(direct_interc_51_out[0]), + .fle_clk(direct_interc_52_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}), + .fle_regin(direct_interc_57_out[0]), + .fle_scin(direct_interc_58_out[0]), + .fle_clk(direct_interc_59_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}), + .fle_regin(direct_interc_64_out[0]), + .fle_scin(direct_interc_65_out[0]), + .fle_clk(direct_interc_66_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0])); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}), + .fle_regin(direct_interc_71_out[0]), + .fle_scin(direct_interc_72_out[0]), + .fle_clk(direct_interc_73_out[0]), + .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]), + .fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]), + .fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]), + .fle_scout(logical_tile_clb_mode_default__fle_7_fle_scout[0]), + .ccff_tail(ccff_tail[0])); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[1]), + .out(clb_O[0])); + + direct_interc direct_interc_1_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_out[0]), + .out(clb_O[1])); + + direct_interc direct_interc_2_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[1]), + .out(clb_O[2])); + + direct_interc direct_interc_3_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_out[0]), + .out(clb_O[3])); + + direct_interc direct_interc_4_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[1]), + .out(clb_O[4])); + + direct_interc direct_interc_5_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_out[0]), + .out(clb_O[5])); + + direct_interc direct_interc_6_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[1]), + .out(clb_O[6])); + + direct_interc direct_interc_7_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_out[0]), + .out(clb_O[7])); + + direct_interc direct_interc_8_ ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[1]), + .out(clb_O[8])); + + direct_interc direct_interc_9_ ( + .in(logical_tile_clb_mode_default__fle_4_fle_out[0]), + .out(clb_O[9])); + + direct_interc direct_interc_10_ ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[1]), + .out(clb_O[10])); + + direct_interc direct_interc_11_ ( + .in(logical_tile_clb_mode_default__fle_5_fle_out[0]), + .out(clb_O[11])); + + direct_interc direct_interc_12_ ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[1]), + .out(clb_O[12])); + + direct_interc direct_interc_13_ ( + .in(logical_tile_clb_mode_default__fle_6_fle_out[0]), + .out(clb_O[13])); + + direct_interc direct_interc_14_ ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[1]), + .out(clb_O[14])); + + direct_interc direct_interc_15_ ( + .in(logical_tile_clb_mode_default__fle_7_fle_out[0]), + .out(clb_O[15])); + + direct_interc direct_interc_16_ ( + .in(logical_tile_clb_mode_default__fle_7_fle_regout[0]), + .out(clb_regout[0])); + + direct_interc direct_interc_17_ ( + .in(logical_tile_clb_mode_default__fle_7_fle_scout[0]), + .out(clb_scout[0])); + + direct_interc direct_interc_18_ ( + .in(clb_I0[0]), + .out(direct_interc_18_out[0])); + + direct_interc direct_interc_19_ ( + .in(clb_I0[1]), + .out(direct_interc_19_out[0])); + + direct_interc direct_interc_20_ ( + .in(clb_I0[2]), + .out(direct_interc_20_out[0])); + + direct_interc direct_interc_21_ ( + .in(clb_I0[3]), + .out(direct_interc_21_out[0])); + + direct_interc direct_interc_22_ ( + .in(clb_regin[0]), + .out(direct_interc_22_out[0])); + + direct_interc direct_interc_23_ ( + .in(clb_scin[0]), + .out(direct_interc_23_out[0])); + + direct_interc direct_interc_24_ ( + .in(clb_clk[0]), + .out(direct_interc_24_out[0])); + + direct_interc direct_interc_25_ ( + .in(clb_I1[0]), + .out(direct_interc_25_out[0])); + + direct_interc direct_interc_26_ ( + .in(clb_I1[1]), + .out(direct_interc_26_out[0])); + + direct_interc direct_interc_27_ ( + .in(clb_I1[2]), + .out(direct_interc_27_out[0])); + + direct_interc direct_interc_28_ ( + .in(clb_I1[3]), + .out(direct_interc_28_out[0])); + + direct_interc direct_interc_29_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_regout[0]), + .out(direct_interc_29_out[0])); + + direct_interc direct_interc_30_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_scout[0]), + .out(direct_interc_30_out[0])); + + direct_interc direct_interc_31_ ( + .in(clb_clk[0]), + .out(direct_interc_31_out[0])); + + direct_interc direct_interc_32_ ( + .in(clb_I2[0]), + .out(direct_interc_32_out[0])); + + direct_interc direct_interc_33_ ( + .in(clb_I2[1]), + .out(direct_interc_33_out[0])); + + direct_interc direct_interc_34_ ( + .in(clb_I2[2]), + .out(direct_interc_34_out[0])); + + direct_interc direct_interc_35_ ( + .in(clb_I2[3]), + .out(direct_interc_35_out[0])); + + direct_interc direct_interc_36_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_regout[0]), + .out(direct_interc_36_out[0])); + + direct_interc direct_interc_37_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_scout[0]), + .out(direct_interc_37_out[0])); + + direct_interc direct_interc_38_ ( + .in(clb_clk[0]), + .out(direct_interc_38_out[0])); + + direct_interc direct_interc_39_ ( + .in(clb_I3[0]), + .out(direct_interc_39_out[0])); + + direct_interc direct_interc_40_ ( + .in(clb_I3[1]), + .out(direct_interc_40_out[0])); + + direct_interc direct_interc_41_ ( + .in(clb_I3[2]), + .out(direct_interc_41_out[0])); + + direct_interc direct_interc_42_ ( + .in(clb_I3[3]), + .out(direct_interc_42_out[0])); + + direct_interc direct_interc_43_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_regout[0]), + .out(direct_interc_43_out[0])); + + direct_interc direct_interc_44_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_scout[0]), + .out(direct_interc_44_out[0])); + + direct_interc direct_interc_45_ ( + .in(clb_clk[0]), + .out(direct_interc_45_out[0])); + + direct_interc direct_interc_46_ ( + .in(clb_I4[0]), + .out(direct_interc_46_out[0])); + + direct_interc direct_interc_47_ ( + .in(clb_I4[1]), + .out(direct_interc_47_out[0])); + + direct_interc direct_interc_48_ ( + .in(clb_I4[2]), + .out(direct_interc_48_out[0])); + + direct_interc direct_interc_49_ ( + .in(clb_I4[3]), + .out(direct_interc_49_out[0])); + + direct_interc direct_interc_50_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_regout[0]), + .out(direct_interc_50_out[0])); + + direct_interc direct_interc_51_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_scout[0]), + .out(direct_interc_51_out[0])); + + direct_interc direct_interc_52_ ( + .in(clb_clk[0]), + .out(direct_interc_52_out[0])); + + direct_interc direct_interc_53_ ( + .in(clb_I5[0]), + .out(direct_interc_53_out[0])); + + direct_interc direct_interc_54_ ( + .in(clb_I5[1]), + .out(direct_interc_54_out[0])); + + direct_interc direct_interc_55_ ( + .in(clb_I5[2]), + .out(direct_interc_55_out[0])); + + direct_interc direct_interc_56_ ( + .in(clb_I5[3]), + .out(direct_interc_56_out[0])); + + direct_interc direct_interc_57_ ( + .in(logical_tile_clb_mode_default__fle_4_fle_regout[0]), + .out(direct_interc_57_out[0])); + + direct_interc direct_interc_58_ ( + .in(logical_tile_clb_mode_default__fle_4_fle_scout[0]), + .out(direct_interc_58_out[0])); + + direct_interc direct_interc_59_ ( + .in(clb_clk[0]), + .out(direct_interc_59_out[0])); + + direct_interc direct_interc_60_ ( + .in(clb_I6[0]), + .out(direct_interc_60_out[0])); + + direct_interc direct_interc_61_ ( + .in(clb_I6[1]), + .out(direct_interc_61_out[0])); + + direct_interc direct_interc_62_ ( + .in(clb_I6[2]), + .out(direct_interc_62_out[0])); + + direct_interc direct_interc_63_ ( + .in(clb_I6[3]), + .out(direct_interc_63_out[0])); + + direct_interc direct_interc_64_ ( + .in(logical_tile_clb_mode_default__fle_5_fle_regout[0]), + .out(direct_interc_64_out[0])); + + direct_interc direct_interc_65_ ( + .in(logical_tile_clb_mode_default__fle_5_fle_scout[0]), + .out(direct_interc_65_out[0])); + + direct_interc direct_interc_66_ ( + .in(clb_clk[0]), + .out(direct_interc_66_out[0])); + + direct_interc direct_interc_67_ ( + .in(clb_I7[0]), + .out(direct_interc_67_out[0])); + + direct_interc direct_interc_68_ ( + .in(clb_I7[1]), + .out(direct_interc_68_out[0])); + + direct_interc direct_interc_69_ ( + .in(clb_I7[2]), + .out(direct_interc_69_out[0])); + + direct_interc direct_interc_70_ ( + .in(clb_I7[3]), + .out(direct_interc_70_out[0])); + + direct_interc direct_interc_71_ ( + .in(logical_tile_clb_mode_default__fle_6_fle_regout[0]), + .out(direct_interc_71_out[0])); + + direct_interc direct_interc_72_ ( + .in(logical_tile_clb_mode_default__fle_6_fle_scout[0]), + .out(direct_interc_72_out[0])); + + direct_interc direct_interc_73_ ( + .in(clb_clk[0]), + .out(direct_interc_73_out[0])); + +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v new file mode 100644 index 0000000..b7b27e9 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,143 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module logical_tile_clb_mode_default__fle(prog_clk, + Test_en, + clk, + fle_in, + fle_regin, + fle_scin, + fle_clk, + ccff_head, + fle_out, + fle_regout, + fle_scout, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +input [0:3] fle_in; +// +input [0:0] fle_regin; +// +input [0:0] fle_scin; +// +input [0:0] fle_clk; +// +input [0:0] ccff_head; +// +output [0:1] fle_out; +// +output [0:0] fle_regout; +// +output [0:0] fle_scout; +// +output [0:0] ccff_tail; + +// +wire [0:3] fle_in; +wire [0:0] fle_regin; +wire [0:0] fle_scin; +wire [0:0] fle_clk; +wire [0:1] fle_out; +wire [0:0] fle_regout; +wire [0:0] fle_scout; +// + + +// +// + + +wire [0:0] direct_interc_10_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] direct_interc_6_out; +wire [0:0] direct_interc_7_out; +wire [0:0] direct_interc_8_out; +wire [0:0] direct_interc_9_out; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout; + +// +// +// +// + + logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}), + .fabric_regin(direct_interc_8_out[0]), + .fabric_scin(direct_interc_9_out[0]), + .fabric_clk(direct_interc_10_out[0]), + .ccff_head(ccff_head[0]), + .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]), + .fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), + .fabric_scout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), + .ccff_tail(ccff_tail[0])); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]), + .out(fle_out[0])); + + direct_interc direct_interc_1_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]), + .out(fle_out[1])); + + direct_interc direct_interc_2_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), + .out(fle_regout[0])); + + direct_interc direct_interc_3_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_scout[0]), + .out(fle_scout[0])); + + direct_interc direct_interc_4_ ( + .in(fle_in[0]), + .out(direct_interc_4_out[0])); + + direct_interc direct_interc_5_ ( + .in(fle_in[1]), + .out(direct_interc_5_out[0])); + + direct_interc direct_interc_6_ ( + .in(fle_in[2]), + .out(direct_interc_6_out[0])); + + direct_interc direct_interc_7_ ( + .in(fle_in[3]), + .out(direct_interc_7_out[0])); + + direct_interc direct_interc_8_ ( + .in(fle_regin[0]), + .out(direct_interc_8_out[0])); + + direct_interc direct_interc_9_ ( + .in(fle_scin[0]), + .out(direct_interc_9_out[0])); + + direct_interc direct_interc_10_ ( + .in(fle_clk[0]), + .out(direct_interc_10_out[0])); + +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v new file mode 100644 index 0000000..0364910 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -0,0 +1,203 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk, + Test_en, + clk, + fabric_in, + fabric_regin, + fabric_scin, + fabric_clk, + ccff_head, + fabric_out, + fabric_regout, + fabric_scout, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:0] Test_en; +// +input [0:0] clk; +// +input [0:3] fabric_in; +// +input [0:0] fabric_regin; +// +input [0:0] fabric_scin; +// +input [0:0] fabric_clk; +// +input [0:0] ccff_head; +// +output [0:1] fabric_out; +// +output [0:0] fabric_regout; +// +output [0:0] fabric_scout; +// +output [0:0] ccff_tail; + +// +wire [0:3] fabric_in; +wire [0:0] fabric_regin; +wire [0:0] fabric_scin; +wire [0:0] fabric_clk; +wire [0:1] fabric_out; +wire [0:0] fabric_regout; +wire [0:0] fabric_scout; +// + + +// +// + + +wire [0:0] direct_interc_10_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] direct_interc_6_out; +wire [0:0] direct_interc_7_out; +wire [0:0] direct_interc_8_out; +wire [0:0] direct_interc_9_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; +wire [0:1] mux_tree_size2_0_sram; +wire [0:1] mux_tree_size2_0_sram_inv; +wire [0:1] mux_tree_size2_1_sram; +wire [0:1] mux_tree_size2_1_sram_inv; +wire [0:0] mux_tree_size2_2_out; +wire [0:1] mux_tree_size2_2_sram; +wire [0:1] mux_tree_size2_2_sram_inv; +wire [0:0] mux_tree_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_size2_mem_1_ccff_tail; + +// +// +// +// + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk(prog_clk[0]), + .frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}), + .ccff_head(ccff_head[0]), + .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0])); + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en(Test_en[0]), + .clk(clk[0]), + .ff_D(mux_tree_size2_2_out[0]), + .ff_DI(direct_interc_6_out[0]), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), + .ff_clk(direct_interc_7_out[0])); + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en(Test_en[0]), + .clk(clk[0]), + .ff_D(direct_interc_8_out[0]), + .ff_DI(direct_interc_9_out[0]), + .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), + .ff_clk(direct_interc_10_out[0])); + + mux_tree_size2 mux_fabric_out_0 ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), + .sram(mux_tree_size2_0_sram[0:1]), + .sram_inv(mux_tree_size2_0_sram_inv[0:1]), + .out(fabric_out[0])); + + mux_tree_size2 mux_fabric_out_1 ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), + .sram(mux_tree_size2_1_sram[0:1]), + .sram_inv(mux_tree_size2_1_sram_inv[0:1]), + .out(fabric_out[1])); + + mux_tree_size2 mux_ff_0_D_0 ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_regin[0]}), + .sram(mux_tree_size2_2_sram[0:1]), + .sram_inv(mux_tree_size2_2_sram_inv[0:1]), + .out(mux_tree_size2_2_out[0])); + + mux_tree_size2_mem mem_fabric_out_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]), + .ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_size2_0_sram[0:1]), + .mem_outb(mux_tree_size2_0_sram_inv[0:1])); + + mux_tree_size2_mem mem_fabric_out_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_size2_1_sram[0:1]), + .mem_outb(mux_tree_size2_1_sram_inv[0:1])); + + mux_tree_size2_mem mem_ff_0_D_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_size2_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_size2_2_sram[0:1]), + .mem_outb(mux_tree_size2_2_sram_inv[0:1])); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), + .out(fabric_regout[0])); + + direct_interc direct_interc_1_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), + .out(fabric_scout[0])); + + direct_interc direct_interc_2_ ( + .in(fabric_in[0]), + .out(direct_interc_2_out[0])); + + direct_interc direct_interc_3_ ( + .in(fabric_in[1]), + .out(direct_interc_3_out[0])); + + direct_interc direct_interc_4_ ( + .in(fabric_in[2]), + .out(direct_interc_4_out[0])); + + direct_interc direct_interc_5_ ( + .in(fabric_in[3]), + .out(direct_interc_5_out[0])); + + direct_interc direct_interc_6_ ( + .in(fabric_scin[0]), + .out(direct_interc_6_out[0])); + + direct_interc direct_interc_7_ ( + .in(fabric_clk[0]), + .out(direct_interc_7_out[0])); + + direct_interc direct_interc_8_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]), + .out(direct_interc_8_out[0])); + + direct_interc direct_interc_9_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), + .out(direct_interc_9_out[0])); + + direct_interc direct_interc_10_ ( + .in(fabric_clk[0]), + .out(direct_interc_10_out[0])); + +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v new file mode 100644 index 0000000..824e4d4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -0,0 +1,59 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en, + clk, + ff_D, + ff_DI, + ff_Q, + ff_clk); +// +input [0:0] Test_en; +// +input [0:0] clk; +// +input [0:0] ff_D; +// +input [0:0] ff_DI; +// +output [0:0] ff_Q; +// +input [0:0] ff_clk; + +// +wire [0:0] ff_D; +wire [0:0] ff_DI; +wire [0:0] ff_Q; +wire [0:0] ff_clk; +// + + +// +// + + + +// +// +// +// + + sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( + .SCE(Test_en[0]), + .CLK(clk[0]), + .D(ff_D[0]), + .SCD(ff_DI[0]), + .Q(ff_Q[0])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v new file mode 100644 index 0000000..83abac9 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -0,0 +1,99 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_clk, + frac_logic_in, + ccff_head, + frac_logic_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:3] frac_logic_in; +// +input [0:0] ccff_head; +// +output [0:1] frac_logic_out; +// +output [0:0] ccff_tail; + +// +wire [0:3] frac_logic_in; +wire [0:1] frac_logic_out; +// + + +// +// + + +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; +wire [0:1] mux_tree_size2_0_sram; +wire [0:1] mux_tree_size2_0_sram_inv; + +// +// +// +// + + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk(prog_clk[0]), + .frac_lut4_in({direct_interc_1_out[0], direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0]}), + .ccff_head(ccff_head[0]), + .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]), + .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0])); + + mux_tree_size2 mux_frac_logic_out_0 ( + .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), + .sram(mux_tree_size2_0_sram[0:1]), + .sram_inv(mux_tree_size2_0_sram_inv[0:1]), + .out(frac_logic_out[0])); + + mux_tree_size2_mem mem_frac_logic_out_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_size2_0_sram[0:1]), + .mem_outb(mux_tree_size2_0_sram_inv[0:1])); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), + .out(frac_logic_out[1])); + + direct_interc direct_interc_1_ ( + .in(frac_logic_in[0]), + .out(direct_interc_1_out[0])); + + direct_interc direct_interc_2_ ( + .in(frac_logic_in[1]), + .out(direct_interc_2_out[0])); + + direct_interc direct_interc_3_ ( + .in(frac_logic_in[2]), + .out(direct_interc_3_out[0])); + + direct_interc direct_interc_4_ ( + .in(frac_logic_in[3]), + .out(direct_interc_4_out[0])); + +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v new file mode 100644 index 0000000..d27a5da --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -0,0 +1,71 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_clk, + frac_lut4_in, + ccff_head, + frac_lut4_lut3_out, + frac_lut4_lut4_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:3] frac_lut4_in; +// +input [0:0] ccff_head; +// +output [0:1] frac_lut4_lut3_out; +// +output [0:0] frac_lut4_lut4_out; +// +output [0:0] ccff_tail; + +// +wire [0:3] frac_lut4_in; +wire [0:1] frac_lut4_lut3_out; +wire [0:0] frac_lut4_lut4_out; +// + + +// +// + + +wire [0:0] frac_lut4_0_mode; +wire [0:0] frac_lut4_0_mode_inv; +wire [0:15] frac_lut4_0_sram; +wire [0:15] frac_lut4_0_sram_inv; + +// +// +// +// + + frac_lut4 frac_lut4_0_ ( + .in(frac_lut4_in[0:3]), + .sram(frac_lut4_0_sram[0:15]), + .sram_inv(frac_lut4_0_sram_inv[0:15]), + .mode(frac_lut4_0_mode[0]), + .mode_inv(frac_lut4_0_mode_inv[0]), + .lut3_out(frac_lut4_lut3_out[0:1]), + .lut4_out(frac_lut4_lut4_out[0])); + + frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}), + .mem_outb({frac_lut4_0_sram_inv[0:15], frac_lut4_0_mode_inv[0]})); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v new file mode 100644 index 0000000..247d7f4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v @@ -0,0 +1,82 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module logical_tile_io_mode_io_(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + io_outpad, + ccff_head, + io_inpad, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] io_outpad; +// +input [0:0] ccff_head; +// +output [0:0] io_inpad; +// +output [0:0] ccff_tail; + +// +wire [0:0] io_outpad; +wire [0:0] io_inpad; +// + + +// +// + + +wire [0:0] direct_interc_1_out; +wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; + +// +// +// +// + + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk(prog_clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0]), + .iopad_outpad(direct_interc_1_out[0]), + .ccff_head(ccff_head[0]), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), + .ccff_tail(ccff_tail[0])); + + direct_interc direct_interc_0_ ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), + .out(io_inpad[0])); + + direct_interc direct_interc_1_ ( + .in(io_outpad[0]), + .out(direct_interc_1_out[0])); + +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 0000000..a39f079 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,77 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module logical_tile_io_mode_physical__iopad(prog_clk, + gfpga_pad_GPIO_A, + gfpga_pad_GPIO_IE, + gfpga_pad_GPIO_OE, + gfpga_pad_GPIO_Y, + iopad_outpad, + ccff_head, + iopad_inpad, + ccff_tail); +// +input [0:0] prog_clk; +// +output [0:0] gfpga_pad_GPIO_A; +// +output [0:0] gfpga_pad_GPIO_IE; +// +output [0:0] gfpga_pad_GPIO_OE; +// +inout [0:0] gfpga_pad_GPIO_Y; +// +input [0:0] iopad_outpad; +// +input [0:0] ccff_head; +// +output [0:0] iopad_inpad; +// +output [0:0] ccff_tail; + +// +wire [0:0] iopad_outpad; +wire [0:0] iopad_inpad; +// + + +// +// + + +wire [0:0] GPIO_0_en; +wire [0:0] GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; + +// +// +// +// + + GPIO GPIO_0_ ( + .A(gfpga_pad_GPIO_A[0]), + .IE(gfpga_pad_GPIO_IE[0]), + .OE(gfpga_pad_GPIO_OE[0]), + .Y(gfpga_pad_GPIO_Y[0]), + .in(iopad_outpad[0]), + .mem_out(GPIO_0_en[0]), + .out(iopad_inpad[0])); + + GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(GPIO_0_en[0]), + .mem_outb(GPIO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v new file mode 100644 index 0000000..8be116b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v @@ -0,0 +1,534 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module cbx_1__0_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_pin_16_, + top_grid_pin_17_, + top_grid_pin_18_, + top_grid_pin_19_, + top_grid_pin_20_, + top_grid_pin_21_, + top_grid_pin_22_, + top_grid_pin_23_, + top_grid_pin_24_, + top_grid_pin_25_, + top_grid_pin_26_, + top_grid_pin_27_, + top_grid_pin_28_, + top_grid_pin_29_, + top_grid_pin_30_, + top_grid_pin_31_, + bottom_grid_pin_0_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chanx_left_in; +// +input [0:19] chanx_right_in; +// +input [0:0] ccff_head; +// +output [0:19] chanx_left_out; +// +output [0:19] chanx_right_out; +// +output [0:0] top_grid_pin_16_; +// +output [0:0] top_grid_pin_17_; +// +output [0:0] top_grid_pin_18_; +// +output [0:0] top_grid_pin_19_; +// +output [0:0] top_grid_pin_20_; +// +output [0:0] top_grid_pin_21_; +// +output [0:0] top_grid_pin_22_; +// +output [0:0] top_grid_pin_23_; +// +output [0:0] top_grid_pin_24_; +// +output [0:0] top_grid_pin_25_; +// +output [0:0] top_grid_pin_26_; +// +output [0:0] top_grid_pin_27_; +// +output [0:0] top_grid_pin_28_; +// +output [0:0] top_grid_pin_29_; +// +output [0:0] top_grid_pin_30_; +// +output [0:0] top_grid_pin_31_; +// +output [0:0] bottom_grid_pin_0_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_8_sram; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_3_sram; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_4_sram; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_5_sram; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_6_sram; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_7_sram; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; + +// +// +// +// + assign chanx_right_out[0] = chanx_left_in[0]; +// +// +// + assign chanx_right_out[1] = chanx_left_in[1]; +// +// +// + assign chanx_right_out[2] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[3]; +// +// +// + assign chanx_right_out[4] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[7]; +// +// +// + assign chanx_right_out[8] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[11]; +// +// +// + assign chanx_right_out[12] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[15]; +// +// +// + assign chanx_right_out[16] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[18]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[19]; +// +// +// + assign chanx_left_out[0] = chanx_right_in[0]; +// +// +// + assign chanx_left_out[1] = chanx_right_in[1]; +// +// +// + assign chanx_left_out[2] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[3] = chanx_right_in[3]; +// +// +// + assign chanx_left_out[4] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[7]; +// +// +// + assign chanx_left_out[8] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[11]; +// +// +// + assign chanx_left_out[12] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[15]; +// +// +// + assign chanx_left_out[16] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[18]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[19]; +// +// +// + + mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(top_grid_pin_16_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(top_grid_pin_17_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(top_grid_pin_20_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(top_grid_pin_21_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(top_grid_pin_24_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(top_grid_pin_25_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(top_grid_pin_28_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(top_grid_pin_29_[0])); + + mux_tree_tapbuf_size10 mux_top_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(bottom_grid_pin_0_[0])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(top_grid_pin_18_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(top_grid_pin_19_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(top_grid_pin_22_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(top_grid_pin_23_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(top_grid_pin_26_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(top_grid_pin_27_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(top_grid_pin_30_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(top_grid_pin_31_[0])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v new file mode 100644 index 0000000..d3201ef --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v @@ -0,0 +1,515 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module cbx_1__1_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_pin_16_, + top_grid_pin_17_, + top_grid_pin_18_, + top_grid_pin_19_, + top_grid_pin_20_, + top_grid_pin_21_, + top_grid_pin_22_, + top_grid_pin_23_, + top_grid_pin_24_, + top_grid_pin_25_, + top_grid_pin_26_, + top_grid_pin_27_, + top_grid_pin_28_, + top_grid_pin_29_, + top_grid_pin_30_, + top_grid_pin_31_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chanx_left_in; +// +input [0:19] chanx_right_in; +// +input [0:0] ccff_head; +// +output [0:19] chanx_left_out; +// +output [0:19] chanx_right_out; +// +output [0:0] top_grid_pin_16_; +// +output [0:0] top_grid_pin_17_; +// +output [0:0] top_grid_pin_18_; +// +output [0:0] top_grid_pin_19_; +// +output [0:0] top_grid_pin_20_; +// +output [0:0] top_grid_pin_21_; +// +output [0:0] top_grid_pin_22_; +// +output [0:0] top_grid_pin_23_; +// +output [0:0] top_grid_pin_24_; +// +output [0:0] top_grid_pin_25_; +// +output [0:0] top_grid_pin_26_; +// +output [0:0] top_grid_pin_27_; +// +output [0:0] top_grid_pin_28_; +// +output [0:0] top_grid_pin_29_; +// +output [0:0] top_grid_pin_30_; +// +output [0:0] top_grid_pin_31_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_3_sram; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_4_sram; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_5_sram; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_6_sram; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_7_sram; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + +// +// +// +// + assign chanx_right_out[0] = chanx_left_in[0]; +// +// +// + assign chanx_right_out[1] = chanx_left_in[1]; +// +// +// + assign chanx_right_out[2] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[3]; +// +// +// + assign chanx_right_out[4] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[7]; +// +// +// + assign chanx_right_out[8] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[11]; +// +// +// + assign chanx_right_out[12] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[15]; +// +// +// + assign chanx_right_out[16] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[18]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[19]; +// +// +// + assign chanx_left_out[0] = chanx_right_in[0]; +// +// +// + assign chanx_left_out[1] = chanx_right_in[1]; +// +// +// + assign chanx_left_out[2] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[3] = chanx_right_in[3]; +// +// +// + assign chanx_left_out[4] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[7]; +// +// +// + assign chanx_left_out[8] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[11]; +// +// +// + assign chanx_left_out[12] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[15]; +// +// +// + assign chanx_left_out[16] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[18]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[19]; +// +// +// + + mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(top_grid_pin_16_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_1 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(top_grid_pin_17_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_4 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(top_grid_pin_20_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_5 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(top_grid_pin_21_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_8 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(top_grid_pin_24_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(top_grid_pin_25_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_12 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(top_grid_pin_28_[0])); + + mux_tree_tapbuf_size10 mux_bottom_ipin_13 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(top_grid_pin_29_[0])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_2 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(top_grid_pin_18_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_3 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(top_grid_pin_19_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_6 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(top_grid_pin_22_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(top_grid_pin_23_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_10 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(top_grid_pin_26_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_11 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(top_grid_pin_27_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_14 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(top_grid_pin_30_[0])); + + mux_tree_tapbuf_size8 mux_bottom_ipin_15 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19]}), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(top_grid_pin_31_[0])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_ipin_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v new file mode 100644 index 0000000..23694e7 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v @@ -0,0 +1,230 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module cbx_1__2_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_pin_0_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chanx_left_in; +// +input [0:19] chanx_right_in; +// +input [0:0] ccff_head; +// +output [0:19] chanx_left_out; +// +output [0:19] chanx_right_out; +// +output [0:0] top_grid_pin_0_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; + +// +// +// +// + assign chanx_right_out[0] = chanx_left_in[0]; +// +// +// + assign chanx_right_out[1] = chanx_left_in[1]; +// +// +// + assign chanx_right_out[2] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[3]; +// +// +// + assign chanx_right_out[4] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[7]; +// +// +// + assign chanx_right_out[8] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[11]; +// +// +// + assign chanx_right_out[12] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[15]; +// +// +// + assign chanx_right_out[16] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[18]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[19]; +// +// +// + assign chanx_left_out[0] = chanx_right_in[0]; +// +// +// + assign chanx_left_out[1] = chanx_right_in[1]; +// +// +// + assign chanx_left_out[2] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[3] = chanx_right_in[3]; +// +// +// + assign chanx_left_out[4] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[7]; +// +// +// + assign chanx_left_out[8] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[11]; +// +// +// + assign chanx_left_out[12] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[15]; +// +// +// + assign chanx_left_out[16] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[18]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[19]; +// +// +// + + mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(top_grid_pin_0_[0])); + + mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v new file mode 100644 index 0000000..169d56d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v @@ -0,0 +1,249 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module cby_0__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_pin_52_, + left_grid_pin_0_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_bottom_in; +// +input [0:19] chany_top_in; +// +input [0:0] ccff_head; +// +output [0:19] chany_bottom_out; +// +output [0:19] chany_top_out; +// +output [0:0] right_grid_pin_52_; +// +output [0:0] left_grid_pin_0_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; + +// +// +// +// + assign chany_top_out[0] = chany_bottom_in[0]; +// +// +// + assign chany_top_out[1] = chany_bottom_in[1]; +// +// +// + assign chany_top_out[2] = chany_bottom_in[2]; +// +// +// + assign chany_top_out[3] = chany_bottom_in[3]; +// +// +// + assign chany_top_out[4] = chany_bottom_in[4]; +// +// +// + assign chany_top_out[5] = chany_bottom_in[5]; +// +// +// + assign chany_top_out[6] = chany_bottom_in[6]; +// +// +// + assign chany_top_out[7] = chany_bottom_in[7]; +// +// +// + assign chany_top_out[8] = chany_bottom_in[8]; +// +// +// + assign chany_top_out[9] = chany_bottom_in[9]; +// +// +// + assign chany_top_out[10] = chany_bottom_in[10]; +// +// +// + assign chany_top_out[11] = chany_bottom_in[11]; +// +// +// + assign chany_top_out[12] = chany_bottom_in[12]; +// +// +// + assign chany_top_out[13] = chany_bottom_in[13]; +// +// +// + assign chany_top_out[14] = chany_bottom_in[14]; +// +// +// + assign chany_top_out[15] = chany_bottom_in[15]; +// +// +// + assign chany_top_out[16] = chany_bottom_in[16]; +// +// +// + assign chany_top_out[17] = chany_bottom_in[17]; +// +// +// + assign chany_top_out[18] = chany_bottom_in[18]; +// +// +// + assign chany_top_out[19] = chany_bottom_in[19]; +// +// +// + assign chany_bottom_out[0] = chany_top_in[0]; +// +// +// + assign chany_bottom_out[1] = chany_top_in[1]; +// +// +// + assign chany_bottom_out[2] = chany_top_in[2]; +// +// +// + assign chany_bottom_out[3] = chany_top_in[3]; +// +// +// + assign chany_bottom_out[4] = chany_top_in[4]; +// +// +// + assign chany_bottom_out[5] = chany_top_in[5]; +// +// +// + assign chany_bottom_out[6] = chany_top_in[6]; +// +// +// + assign chany_bottom_out[7] = chany_top_in[7]; +// +// +// + assign chany_bottom_out[8] = chany_top_in[8]; +// +// +// + assign chany_bottom_out[9] = chany_top_in[9]; +// +// +// + assign chany_bottom_out[10] = chany_top_in[10]; +// +// +// + assign chany_bottom_out[11] = chany_top_in[11]; +// +// +// + assign chany_bottom_out[12] = chany_top_in[12]; +// +// +// + assign chany_bottom_out[13] = chany_top_in[13]; +// +// +// + assign chany_bottom_out[14] = chany_top_in[14]; +// +// +// + assign chany_bottom_out[15] = chany_top_in[15]; +// +// +// + assign chany_bottom_out[16] = chany_top_in[16]; +// +// +// + assign chany_bottom_out[17] = chany_top_in[17]; +// +// +// + assign chany_bottom_out[18] = chany_top_in[18]; +// +// +// + assign chany_bottom_out[19] = chany_top_in[19]; +// +// +// + + mux_tree_tapbuf_size10 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(right_grid_pin_52_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_0_[0])); + + mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v new file mode 100644 index 0000000..72ba185 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v @@ -0,0 +1,534 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module cby_1__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_pin_52_, + left_grid_pin_0_, + left_grid_pin_1_, + left_grid_pin_2_, + left_grid_pin_3_, + left_grid_pin_4_, + left_grid_pin_5_, + left_grid_pin_6_, + left_grid_pin_7_, + left_grid_pin_8_, + left_grid_pin_9_, + left_grid_pin_10_, + left_grid_pin_11_, + left_grid_pin_12_, + left_grid_pin_13_, + left_grid_pin_14_, + left_grid_pin_15_, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_bottom_in; +// +input [0:19] chany_top_in; +// +input [0:0] ccff_head; +// +output [0:19] chany_bottom_out; +// +output [0:19] chany_top_out; +// +output [0:0] right_grid_pin_52_; +// +output [0:0] left_grid_pin_0_; +// +output [0:0] left_grid_pin_1_; +// +output [0:0] left_grid_pin_2_; +// +output [0:0] left_grid_pin_3_; +// +output [0:0] left_grid_pin_4_; +// +output [0:0] left_grid_pin_5_; +// +output [0:0] left_grid_pin_6_; +// +output [0:0] left_grid_pin_7_; +// +output [0:0] left_grid_pin_8_; +// +output [0:0] left_grid_pin_9_; +// +output [0:0] left_grid_pin_10_; +// +output [0:0] left_grid_pin_11_; +// +output [0:0] left_grid_pin_12_; +// +output [0:0] left_grid_pin_13_; +// +output [0:0] left_grid_pin_14_; +// +output [0:0] left_grid_pin_15_; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_8_sram; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_3_sram; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_4_sram; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_5_sram; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_6_sram; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_7_sram; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; + +// +// +// +// + assign chany_top_out[0] = chany_bottom_in[0]; +// +// +// + assign chany_top_out[1] = chany_bottom_in[1]; +// +// +// + assign chany_top_out[2] = chany_bottom_in[2]; +// +// +// + assign chany_top_out[3] = chany_bottom_in[3]; +// +// +// + assign chany_top_out[4] = chany_bottom_in[4]; +// +// +// + assign chany_top_out[5] = chany_bottom_in[5]; +// +// +// + assign chany_top_out[6] = chany_bottom_in[6]; +// +// +// + assign chany_top_out[7] = chany_bottom_in[7]; +// +// +// + assign chany_top_out[8] = chany_bottom_in[8]; +// +// +// + assign chany_top_out[9] = chany_bottom_in[9]; +// +// +// + assign chany_top_out[10] = chany_bottom_in[10]; +// +// +// + assign chany_top_out[11] = chany_bottom_in[11]; +// +// +// + assign chany_top_out[12] = chany_bottom_in[12]; +// +// +// + assign chany_top_out[13] = chany_bottom_in[13]; +// +// +// + assign chany_top_out[14] = chany_bottom_in[14]; +// +// +// + assign chany_top_out[15] = chany_bottom_in[15]; +// +// +// + assign chany_top_out[16] = chany_bottom_in[16]; +// +// +// + assign chany_top_out[17] = chany_bottom_in[17]; +// +// +// + assign chany_top_out[18] = chany_bottom_in[18]; +// +// +// + assign chany_top_out[19] = chany_bottom_in[19]; +// +// +// + assign chany_bottom_out[0] = chany_top_in[0]; +// +// +// + assign chany_bottom_out[1] = chany_top_in[1]; +// +// +// + assign chany_bottom_out[2] = chany_top_in[2]; +// +// +// + assign chany_bottom_out[3] = chany_top_in[3]; +// +// +// + assign chany_bottom_out[4] = chany_top_in[4]; +// +// +// + assign chany_bottom_out[5] = chany_top_in[5]; +// +// +// + assign chany_bottom_out[6] = chany_top_in[6]; +// +// +// + assign chany_bottom_out[7] = chany_top_in[7]; +// +// +// + assign chany_bottom_out[8] = chany_top_in[8]; +// +// +// + assign chany_bottom_out[9] = chany_top_in[9]; +// +// +// + assign chany_bottom_out[10] = chany_top_in[10]; +// +// +// + assign chany_bottom_out[11] = chany_top_in[11]; +// +// +// + assign chany_bottom_out[12] = chany_top_in[12]; +// +// +// + assign chany_bottom_out[13] = chany_top_in[13]; +// +// +// + assign chany_bottom_out[14] = chany_top_in[14]; +// +// +// + assign chany_bottom_out[15] = chany_top_in[15]; +// +// +// + assign chany_bottom_out[16] = chany_top_in[16]; +// +// +// + assign chany_bottom_out[17] = chany_top_in[17]; +// +// +// + assign chany_bottom_out[18] = chany_top_in[18]; +// +// +// + assign chany_bottom_out[19] = chany_top_in[19]; +// +// +// + + mux_tree_tapbuf_size10 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(right_grid_pin_52_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(left_grid_pin_0_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_1 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(left_grid_pin_1_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_4 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(left_grid_pin_4_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_5 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(left_grid_pin_5_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(left_grid_pin_8_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[14], chany_top_in[14]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(left_grid_pin_9_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_12 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(left_grid_pin_12_[0])); + + mux_tree_tapbuf_size10 mux_right_ipin_13 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[18], chany_top_in[18]}), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(left_grid_pin_13_[0])); + + mux_tree_tapbuf_size10_mem mem_left_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_ipin_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); + + mux_tree_tapbuf_size8 mux_right_ipin_2 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(left_grid_pin_2_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_3 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(left_grid_pin_3_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_6 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(left_grid_pin_6_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(left_grid_pin_7_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_10 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15]}), + .sram(mux_tree_tapbuf_size8_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .out(left_grid_pin_10_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_11 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[16], chany_top_in[16]}), + .sram(mux_tree_tapbuf_size8_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .out(left_grid_pin_11_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_14 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19]}), + .sram(mux_tree_tapbuf_size8_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .out(left_grid_pin_14_[0])); + + mux_tree_tapbuf_size8 mux_right_ipin_15 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size8_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .out(left_grid_pin_15_[0])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_ipin_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v new file mode 100644 index 0000000..4dabe79 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v @@ -0,0 +1,456 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_0__0_(prog_clk, + chany_top_in, + top_left_grid_pin_1_, + chanx_right_in, + right_top_grid_pin_42_, + right_top_grid_pin_43_, + right_top_grid_pin_44_, + right_top_grid_pin_45_, + right_top_grid_pin_46_, + right_top_grid_pin_47_, + right_top_grid_pin_48_, + right_top_grid_pin_49_, + right_bottom_grid_pin_1_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_1_; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_42_; +// +input [0:0] right_top_grid_pin_43_; +// +input [0:0] right_top_grid_pin_44_; +// +input [0:0] right_top_grid_pin_45_; +// +input [0:0] right_top_grid_pin_46_; +// +input [0:0] right_top_grid_pin_47_; +// +input [0:0] right_top_grid_pin_48_; +// +input [0:0] right_top_grid_pin_49_; +// +input [0:0] right_bottom_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chanx_right_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + +// +// +// +// + assign chanx_right_out[14] = chany_top_in[13]; +// +// +// + assign chanx_right_out[15] = chany_top_in[14]; +// +// +// + assign chanx_right_out[16] = chany_top_in[15]; +// +// +// + assign chanx_right_out[17] = chany_top_in[16]; +// +// +// + assign chanx_right_out[18] = chany_top_in[17]; +// +// +// + assign chanx_right_out[19] = chany_top_in[18]; +// +// +// + assign chany_top_out[19] = chanx_right_in[0]; +// +// +// + assign chany_top_out[1] = chanx_right_in[2]; +// +// +// + assign chany_top_out[3] = chanx_right_in[4]; +// +// +// + assign chany_top_out[5] = chanx_right_in[6]; +// +// +// + assign chany_top_out[6] = chanx_right_in[7]; +// +// +// + assign chany_top_out[7] = chanx_right_in[8]; +// +// +// + assign chany_top_out[8] = chanx_right_in[9]; +// +// +// + assign chany_top_out[9] = chanx_right_in[10]; +// +// +// + assign chany_top_out[10] = chanx_right_in[11]; +// +// +// + assign chany_top_out[11] = chanx_right_in[12]; +// +// +// + assign chany_top_out[13] = chanx_right_in[14]; +// +// +// + assign chany_top_out[14] = chanx_right_in[15]; +// +// +// + assign chany_top_out[15] = chanx_right_in[16]; +// +// +// + assign chany_top_out[16] = chanx_right_in[17]; +// +// +// + assign chany_top_out[17] = chanx_right_in[18]; +// +// +// + assign chany_top_out[18] = chanx_right_in[19]; +// +// +// + + mux_tree_tapbuf_size2 mux_top_track_0 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size2 mux_top_track_4 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size2 mux_top_track_8 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size2 mux_top_track_24 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[13]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size2 mux_right_track_10 ( + .in({chany_top_in[4], right_top_grid_pin_43_[0]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size2 mux_right_track_12 ( + .in({chany_top_in[5], right_top_grid_pin_44_[0]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size2 mux_right_track_14 ( + .in({chany_top_in[6], right_top_grid_pin_45_[0]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size2 mux_right_track_16 ( + .in({chany_top_in[7], right_top_grid_pin_46_[0]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({chany_top_in[8], right_top_grid_pin_47_[0]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({chany_top_in[9], right_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({chany_top_in[10], right_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2 mux_right_track_26 ( + .in({chany_top_in[12], right_top_grid_pin_43_[0]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chanx_right_out[13])); + + mux_tree_tapbuf_size2_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_26 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); + + mux_tree_tapbuf_size6 mux_right_track_0 ( + .in({chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size6 mux_right_track_4 ( + .in({chany_top_in[1], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size6_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size5 mux_right_track_2 ( + .in({chany_top_in[0], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size5 mux_right_track_6 ( + .in({chany_top_in[2], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size5_mem mem_right_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_8 ( + .in({chany_top_in[3], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({chany_top_in[11], right_top_grid_pin_42_[0], right_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v new file mode 100644 index 0000000..ae0f810 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v @@ -0,0 +1,658 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_0__1_(prog_clk, + chany_top_in, + top_left_grid_pin_1_, + chanx_right_in, + right_top_grid_pin_42_, + right_top_grid_pin_43_, + right_top_grid_pin_44_, + right_top_grid_pin_45_, + right_top_grid_pin_46_, + right_top_grid_pin_47_, + right_top_grid_pin_48_, + right_top_grid_pin_49_, + chany_bottom_in, + bottom_left_grid_pin_1_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_1_; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_42_; +// +input [0:0] right_top_grid_pin_43_; +// +input [0:0] right_top_grid_pin_44_; +// +input [0:0] right_top_grid_pin_45_; +// +input [0:0] right_top_grid_pin_46_; +// +input [0:0] right_top_grid_pin_47_; +// +input [0:0] right_top_grid_pin_48_; +// +input [0:0] right_top_grid_pin_49_; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_left_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chanx_right_out; +// +output [0:19] chany_bottom_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_6_sram; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + +// +// +// +// + assign chany_bottom_out[3] = chany_top_in[2]; +// +// +// + assign chany_bottom_out[5] = chany_top_in[4]; +// +// +// + assign chany_bottom_out[6] = chany_top_in[5]; +// +// +// + assign chany_bottom_out[7] = chany_top_in[6]; +// +// +// + assign chany_bottom_out[9] = chany_top_in[8]; +// +// +// + assign chany_bottom_out[10] = chany_top_in[9]; +// +// +// + assign chany_bottom_out[11] = chany_top_in[10]; +// +// +// + assign chany_bottom_out[13] = chany_top_in[12]; +// +// +// + assign chany_bottom_out[14] = chany_top_in[13]; +// +// +// + assign chany_bottom_out[15] = chany_top_in[14]; +// +// +// + assign chany_bottom_out[17] = chany_top_in[16]; +// +// +// + assign chany_bottom_out[18] = chany_top_in[17]; +// +// +// + assign chany_bottom_out[19] = chany_top_in[18]; +// +// +// + assign chanx_right_out[18] = chany_bottom_in[0]; +// +// +// + assign chanx_right_out[17] = chany_bottom_in[1]; +// +// +// + assign chany_top_out[3] = chany_bottom_in[2]; +// +// +// + assign chanx_right_out[16] = chany_bottom_in[3]; +// +// +// + assign chany_top_out[5] = chany_bottom_in[4]; +// +// +// + assign chany_top_out[6] = chany_bottom_in[5]; +// +// +// + assign chany_top_out[7] = chany_bottom_in[6]; +// +// +// + assign chanx_right_out[15] = chany_bottom_in[7]; +// +// +// + assign chany_top_out[9] = chany_bottom_in[8]; +// +// +// + assign chany_top_out[10] = chany_bottom_in[9]; +// +// +// + assign chany_top_out[11] = chany_bottom_in[10]; +// +// +// + assign chanx_right_out[14] = chany_bottom_in[11]; +// +// +// + assign chany_top_out[13] = chany_bottom_in[12]; +// +// +// + assign chany_top_out[14] = chany_bottom_in[13]; +// +// +// + assign chany_top_out[15] = chany_bottom_in[14]; +// +// +// + assign chany_top_out[17] = chany_bottom_in[16]; +// +// +// + assign chany_top_out[18] = chany_bottom_in[17]; +// +// +// + assign chany_top_out[19] = chany_bottom_in[18]; +// +// +// + + mux_tree_tapbuf_size6 mux_top_track_0 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size6 mux_top_track_4 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size6 mux_top_track_8 ( + .in({top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size6 mux_right_track_0 ( + .in({chany_top_in[2], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size6 mux_bottom_track_1 ( + .in({chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in({chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in({chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size6_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size5 mux_top_track_2 ( + .in({chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size5 mux_top_track_16 ( + .in({chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size5 mux_bottom_track_3 ( + .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size5 mux_bottom_track_17 ( + .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size5 mux_bottom_track_25 ( + .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14]}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size5_mem mem_top_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4 mux_top_track_24 ( + .in({chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size4 mux_top_track_32 ( + .in({chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size4 mux_right_track_8 ( + .in({chany_top_in[7:8], right_top_grid_pin_42_[0], chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size4 mux_right_track_10 ( + .in({chany_top_in[9], chany_top_in[11], right_top_grid_pin_43_[0], chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_44_[0], chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_14 ( + .in({chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size4 mux_right_track_24 ( + .in({chany_top_in[18], right_top_grid_pin_42_[0], chany_bottom_in[18:19]}), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size4_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])); + + mux_tree_tapbuf_size7 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[4], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size7 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[5], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size7 mux_right_track_6 ( + .in({chany_top_in[3], chany_top_in[6], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size7_mem mem_right_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({chany_top_in[13], right_top_grid_pin_46_[0], chany_bottom_in[13]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_18 ( + .in({chany_top_in[14], right_top_grid_pin_47_[0], chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size3 mux_right_track_20 ( + .in({chany_top_in[16], right_top_grid_pin_48_[0], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size3 mux_right_track_22 ( + .in({chany_top_in[17], right_top_grid_pin_49_[0], chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size3 mux_bottom_track_33 ( + .in({chany_top_in[10], chanx_right_in[6], chanx_right_in[13]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_18 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_20 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_right_track_26 ( + .in({right_top_grid_pin_43_[0], chany_bottom_in[15]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[13])); + + mux_tree_tapbuf_size2_mem mem_right_track_26 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v new file mode 100644 index 0000000..62bac18 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v @@ -0,0 +1,312 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_0__2_(prog_clk, + chanx_right_in, + right_top_grid_pin_1_, + chany_bottom_in, + bottom_left_grid_pin_1_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_1_; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_left_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chanx_right_out; +// +output [0:19] chany_bottom_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; + +// +// +// +// + assign chany_bottom_out[18] = chanx_right_in[0]; +// +// +// + assign chany_bottom_out[17] = chanx_right_in[1]; +// +// +// + assign chany_bottom_out[16] = chanx_right_in[2]; +// +// +// + assign chany_bottom_out[15] = chanx_right_in[3]; +// +// +// + assign chany_bottom_out[14] = chanx_right_in[4]; +// +// +// + assign chany_bottom_out[13] = chanx_right_in[5]; +// +// +// + assign chany_bottom_out[11] = chanx_right_in[7]; +// +// +// + assign chany_bottom_out[10] = chanx_right_in[8]; +// +// +// + assign chany_bottom_out[9] = chanx_right_in[9]; +// +// +// + assign chany_bottom_out[8] = chanx_right_in[10]; +// +// +// + assign chany_bottom_out[7] = chanx_right_in[11]; +// +// +// + assign chany_bottom_out[6] = chanx_right_in[12]; +// +// +// + assign chany_bottom_out[5] = chanx_right_in[13]; +// +// +// + assign chany_bottom_out[3] = chanx_right_in[15]; +// +// +// + assign chany_bottom_out[1] = chanx_right_in[17]; +// +// +// + assign chany_bottom_out[19] = chanx_right_in[19]; +// +// +// + assign chanx_right_out[18] = chany_bottom_in[0]; +// +// +// + assign chanx_right_out[17] = chany_bottom_in[1]; +// +// +// + assign chanx_right_out[16] = chany_bottom_in[2]; +// +// +// + assign chanx_right_out[15] = chany_bottom_in[3]; +// +// +// + assign chanx_right_out[14] = chany_bottom_in[4]; +// +// +// + assign chanx_right_out[13] = chany_bottom_in[5]; +// +// +// + assign chanx_right_out[11] = chany_bottom_in[7]; +// +// +// + assign chanx_right_out[10] = chany_bottom_in[8]; +// +// +// + assign chanx_right_out[9] = chany_bottom_in[9]; +// +// +// + assign chanx_right_out[8] = chany_bottom_in[10]; +// +// +// + assign chanx_right_out[7] = chany_bottom_in[11]; +// +// +// + assign chanx_right_out[6] = chany_bottom_in[12]; +// +// +// + assign chanx_right_out[5] = chany_bottom_in[13]; +// +// +// + assign chanx_right_out[3] = chany_bottom_in[15]; +// +// +// + assign chanx_right_out[1] = chany_bottom_in[17]; +// +// +// + assign chanx_right_out[19] = chany_bottom_in[19]; +// +// +// + + mux_tree_tapbuf_size2 mux_right_track_0 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size2 mux_right_track_4 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[16]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size2 mux_right_track_8 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size2 mux_right_track_24 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size2 mux_bottom_track_1 ( + .in({chanx_right_in[18], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size2 mux_bottom_track_5 ( + .in({chanx_right_in[16], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size2 mux_bottom_track_9 ( + .in({chanx_right_in[14], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size2 mux_bottom_track_25 ( + .in({chanx_right_in[6], bottom_left_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size2_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v new file mode 100644 index 0000000..2ed68b1 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v @@ -0,0 +1,770 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_1__0_(prog_clk, + chany_top_in, + top_left_grid_pin_34_, + top_left_grid_pin_35_, + top_left_grid_pin_36_, + top_left_grid_pin_37_, + top_left_grid_pin_38_, + top_left_grid_pin_39_, + top_left_grid_pin_40_, + top_left_grid_pin_41_, + chanx_right_in, + right_top_grid_pin_42_, + right_top_grid_pin_43_, + right_top_grid_pin_44_, + right_top_grid_pin_45_, + right_top_grid_pin_46_, + right_top_grid_pin_47_, + right_top_grid_pin_48_, + right_top_grid_pin_49_, + right_bottom_grid_pin_1_, + chanx_left_in, + left_top_grid_pin_42_, + left_top_grid_pin_43_, + left_top_grid_pin_44_, + left_top_grid_pin_45_, + left_top_grid_pin_46_, + left_top_grid_pin_47_, + left_top_grid_pin_48_, + left_top_grid_pin_49_, + left_bottom_grid_pin_1_, + ccff_head, + chany_top_out, + chanx_right_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_34_; +// +input [0:0] top_left_grid_pin_35_; +// +input [0:0] top_left_grid_pin_36_; +// +input [0:0] top_left_grid_pin_37_; +// +input [0:0] top_left_grid_pin_38_; +// +input [0:0] top_left_grid_pin_39_; +// +input [0:0] top_left_grid_pin_40_; +// +input [0:0] top_left_grid_pin_41_; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_42_; +// +input [0:0] right_top_grid_pin_43_; +// +input [0:0] right_top_grid_pin_44_; +// +input [0:0] right_top_grid_pin_45_; +// +input [0:0] right_top_grid_pin_46_; +// +input [0:0] right_top_grid_pin_47_; +// +input [0:0] right_top_grid_pin_48_; +// +input [0:0] right_top_grid_pin_49_; +// +input [0:0] right_bottom_grid_pin_1_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_42_; +// +input [0:0] left_top_grid_pin_43_; +// +input [0:0] left_top_grid_pin_44_; +// +input [0:0] left_top_grid_pin_45_; +// +input [0:0] left_top_grid_pin_46_; +// +input [0:0] left_top_grid_pin_47_; +// +input [0:0] left_top_grid_pin_48_; +// +input [0:0] left_top_grid_pin_49_; +// +input [0:0] left_bottom_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chanx_right_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:3] mux_tree_tapbuf_size14_0_sram; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size14_1_sram; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_5_sram; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_6_sram; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_3_sram; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; +wire [0:3] mux_tree_tapbuf_size9_0_sram; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size9_1_sram; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; + +// +// +// +// + assign chany_top_out[13] = top_left_grid_pin_35_[0]; +// +// +// + assign chanx_left_out[3] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[18]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[18]; +// +// +// + + mux_tree_tapbuf_size8 mux_top_track_0 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size8 mux_right_track_8 ( + .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], right_bottom_grid_pin_1_[0], chanx_left_in[6], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size8 mux_left_track_3 ( + .in({chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size8 mux_left_track_9 ( + .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size8_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size8_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_left_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])); + + mux_tree_tapbuf_size7 mux_top_track_2 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size7 mux_top_track_4 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size7 mux_top_track_6 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size7 mux_right_track_16 ( + .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size7 mux_right_track_24 ( + .in({chany_top_in[4], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size7 mux_left_track_17 ( + .in({chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size7 mux_left_track_25 ( + .in({chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size7_mem mem_top_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); + + mux_tree_tapbuf_size4 mux_top_track_8 ( + .in({top_left_grid_pin_34_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size4 mux_top_track_10 ( + .in({top_left_grid_pin_35_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size4_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_12 ( + .in({top_left_grid_pin_36_[0], chanx_right_in[10], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size3 mux_top_track_14 ( + .in({top_left_grid_pin_37_[0], chanx_right_in[12], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_left_grid_pin_38_[0], chanx_right_in[13], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_top_track_18 ( + .in({top_left_grid_pin_39_[0], chanx_right_in[14], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size3 mux_top_track_20 ( + .in({top_left_grid_pin_40_[0], chanx_right_in[16], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size3 mux_top_track_22 ( + .in({top_left_grid_pin_41_[0], chanx_right_in[17], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size3 mux_top_track_24 ( + .in({top_left_grid_pin_34_[0], chanx_right_in[18], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size3 mux_top_track_38 ( + .in({top_left_grid_pin_41_[0], chanx_right_in[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chany_top_out[19])); + + mux_tree_tapbuf_size3_mem mem_top_track_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_18 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_20 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_22 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_38 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_28 ( + .in({top_left_grid_pin_36_[0], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size2 mux_top_track_30 ( + .in({top_left_grid_pin_37_[0], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[15])); + + mux_tree_tapbuf_size2 mux_top_track_32 ( + .in({top_left_grid_pin_38_[0], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size2 mux_top_track_34 ( + .in({top_left_grid_pin_39_[0], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[17])); + + mux_tree_tapbuf_size2 mux_top_track_36 ( + .in({top_left_grid_pin_40_[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size2_mem mem_top_track_28 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_30 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_34 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_36 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size9 mux_right_track_0 ( + .in({chany_top_in[6], chany_top_in[13], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], right_bottom_grid_pin_1_[0], chanx_left_in[2], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size9 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size9_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size9_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); + + mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3])); + + mux_tree_tapbuf_size14 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], right_bottom_grid_pin_1_[0], chanx_left_in[5], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size14 mux_left_track_5 ( + .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); + + mux_tree_tapbuf_size14_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); + + mux_tree_tapbuf_size6 mux_right_track_32 ( + .in({chany_top_in[5], chany_top_in[12], chany_top_in[19], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size6 mux_left_track_33 ( + .in({chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size6_mem mem_right_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size10 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size10_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v new file mode 100644 index 0000000..3e6c226 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v @@ -0,0 +1,814 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_1__1_(prog_clk, + chany_top_in, + top_left_grid_pin_34_, + top_left_grid_pin_35_, + top_left_grid_pin_36_, + top_left_grid_pin_37_, + top_left_grid_pin_38_, + top_left_grid_pin_39_, + top_left_grid_pin_40_, + top_left_grid_pin_41_, + chanx_right_in, + right_top_grid_pin_42_, + right_top_grid_pin_43_, + right_top_grid_pin_44_, + right_top_grid_pin_45_, + right_top_grid_pin_46_, + right_top_grid_pin_47_, + right_top_grid_pin_48_, + right_top_grid_pin_49_, + chany_bottom_in, + bottom_left_grid_pin_34_, + bottom_left_grid_pin_35_, + bottom_left_grid_pin_36_, + bottom_left_grid_pin_37_, + bottom_left_grid_pin_38_, + bottom_left_grid_pin_39_, + bottom_left_grid_pin_40_, + bottom_left_grid_pin_41_, + chanx_left_in, + left_top_grid_pin_42_, + left_top_grid_pin_43_, + left_top_grid_pin_44_, + left_top_grid_pin_45_, + left_top_grid_pin_46_, + left_top_grid_pin_47_, + left_top_grid_pin_48_, + left_top_grid_pin_49_, + ccff_head, + chany_top_out, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_34_; +// +input [0:0] top_left_grid_pin_35_; +// +input [0:0] top_left_grid_pin_36_; +// +input [0:0] top_left_grid_pin_37_; +// +input [0:0] top_left_grid_pin_38_; +// +input [0:0] top_left_grid_pin_39_; +// +input [0:0] top_left_grid_pin_40_; +// +input [0:0] top_left_grid_pin_41_; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_42_; +// +input [0:0] right_top_grid_pin_43_; +// +input [0:0] right_top_grid_pin_44_; +// +input [0:0] right_top_grid_pin_45_; +// +input [0:0] right_top_grid_pin_46_; +// +input [0:0] right_top_grid_pin_47_; +// +input [0:0] right_top_grid_pin_48_; +// +input [0:0] right_top_grid_pin_49_; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_left_grid_pin_34_; +// +input [0:0] bottom_left_grid_pin_35_; +// +input [0:0] bottom_left_grid_pin_36_; +// +input [0:0] bottom_left_grid_pin_37_; +// +input [0:0] bottom_left_grid_pin_38_; +// +input [0:0] bottom_left_grid_pin_39_; +// +input [0:0] bottom_left_grid_pin_40_; +// +input [0:0] bottom_left_grid_pin_41_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_42_; +// +input [0:0] left_top_grid_pin_43_; +// +input [0:0] left_top_grid_pin_44_; +// +input [0:0] left_top_grid_pin_45_; +// +input [0:0] left_top_grid_pin_46_; +// +input [0:0] left_top_grid_pin_47_; +// +input [0:0] left_top_grid_pin_48_; +// +input [0:0] left_top_grid_pin_49_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chanx_right_out; +// +output [0:19] chany_bottom_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_10_sram; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_11_sram; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_2_sram; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_3_sram; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_4_sram; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_5_sram; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_6_sram; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_7_sram; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_8_sram; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_9_sram; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; +wire [0:3] mux_tree_tapbuf_size12_0_sram; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_1_sram; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_2_sram; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_3_sram; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_4_sram; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_5_sram; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_6_sram; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; +wire [0:3] mux_tree_tapbuf_size12_7_sram; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; +wire [0:4] mux_tree_tapbuf_size16_0_sram; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; +wire [0:4] mux_tree_tapbuf_size16_1_sram; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; +wire [0:4] mux_tree_tapbuf_size16_2_sram; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; +wire [0:4] mux_tree_tapbuf_size16_3_sram; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; + +// +// +// +// + assign chany_bottom_out[3] = chany_top_in[2]; +// +// +// + assign chany_bottom_out[5] = chany_top_in[4]; +// +// +// + assign chany_bottom_out[6] = chany_top_in[5]; +// +// +// + assign chany_bottom_out[7] = chany_top_in[6]; +// +// +// + assign chany_bottom_out[9] = chany_top_in[8]; +// +// +// + assign chany_bottom_out[10] = chany_top_in[9]; +// +// +// + assign chany_bottom_out[11] = chany_top_in[10]; +// +// +// + assign chany_bottom_out[13] = chany_top_in[12]; +// +// +// + assign chany_bottom_out[14] = chany_top_in[13]; +// +// +// + assign chany_bottom_out[15] = chany_top_in[14]; +// +// +// + assign chany_bottom_out[17] = chany_top_in[16]; +// +// +// + assign chany_bottom_out[18] = chany_top_in[17]; +// +// +// + assign chany_bottom_out[19] = chany_top_in[18]; +// +// +// + assign chanx_left_out[3] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[18]; +// +// +// + assign chany_top_out[3] = chany_bottom_in[2]; +// +// +// + assign chany_top_out[5] = chany_bottom_in[4]; +// +// +// + assign chany_top_out[6] = chany_bottom_in[5]; +// +// +// + assign chany_top_out[7] = chany_bottom_in[6]; +// +// +// + assign chany_top_out[9] = chany_bottom_in[8]; +// +// +// + assign chany_top_out[10] = chany_bottom_in[9]; +// +// +// + assign chany_top_out[11] = chany_bottom_in[10]; +// +// +// + assign chany_top_out[13] = chany_bottom_in[12]; +// +// +// + assign chany_top_out[14] = chany_bottom_in[13]; +// +// +// + assign chany_top_out[15] = chany_bottom_in[14]; +// +// +// + assign chany_top_out[17] = chany_bottom_in[16]; +// +// +// + assign chany_top_out[18] = chany_bottom_in[17]; +// +// +// + assign chany_top_out[19] = chany_bottom_in[18]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[18]; +// +// +// + + mux_tree_tapbuf_size12 mux_top_track_0 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size12_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size12 mux_top_track_2 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size12_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size12 mux_right_track_0 ( + .in({chany_top_in[2], chany_top_in[12], chany_top_in[19], right_top_grid_pin_42_[0], right_top_grid_pin_44_[0], right_top_grid_pin_46_[0], right_top_grid_pin_48_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size12_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size12 mux_right_track_2 ( + .in({chany_top_in[0], chany_top_in[4], chany_top_in[13], right_top_grid_pin_43_[0], right_top_grid_pin_45_[0], right_top_grid_pin_47_[0], right_top_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size12_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size12 mux_bottom_track_1 ( + .in({chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size12_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size12 mux_bottom_track_3 ( + .in({chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size12_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size12 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size12_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size12 mux_left_track_3 ( + .in({chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size12_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size12_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_top_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_right_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_bottom_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3])); + + mux_tree_tapbuf_size12_mem mem_left_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3])); + + mux_tree_tapbuf_size16 mux_top_track_4 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15]}), + .sram(mux_tree_tapbuf_size16_0_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size16 mux_right_track_4 ( + .in({chany_top_in[1], chany_top_in[5], chany_top_in[14], right_top_grid_pin_42_[0], right_top_grid_pin_43_[0], right_top_grid_pin_44_[0], right_top_grid_pin_45_[0], right_top_grid_pin_46_[0], right_top_grid_pin_47_[0], right_top_grid_pin_48_[0], right_top_grid_pin_49_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size16_1_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size16 mux_bottom_track_5 ( + .in({chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size16_2_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size16 mux_left_track_5 ( + .in({chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_top_grid_pin_42_[0], left_top_grid_pin_43_[0], left_top_grid_pin_44_[0], left_top_grid_pin_45_[0], left_top_grid_pin_46_[0], left_top_grid_pin_47_[0], left_top_grid_pin_48_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size16_3_sram[0:4]), + .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size16_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4])); + + mux_tree_tapbuf_size16_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4])); + + mux_tree_tapbuf_size16_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4])); + + mux_tree_tapbuf_size16_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), + .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4])); + + mux_tree_tapbuf_size10 mux_top_track_8 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size10 mux_top_track_16 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size10 mux_top_track_24 ( + .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size10_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size10 mux_right_track_8 ( + .in({chany_top_in[3], chany_top_in[6], chany_top_in[16], right_top_grid_pin_42_[0], right_top_grid_pin_46_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size10_3_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size10 mux_right_track_16 ( + .in({chany_top_in[7:8], chany_top_in[17], right_top_grid_pin_43_[0], right_top_grid_pin_47_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size10_4_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size10 mux_right_track_24 ( + .in({chany_top_in[9], chany_top_in[11], chany_top_in[18], right_top_grid_pin_44_[0], right_top_grid_pin_48_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size10_5_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size10 mux_bottom_track_9 ( + .in({chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size10_6_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size10 mux_bottom_track_17 ( + .in({chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size10_7_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size10 mux_bottom_track_25 ( + .in({chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[9], chanx_left_in[18:19]}), + .sram(mux_tree_tapbuf_size10_8_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size10 mux_left_track_9 ( + .in({chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_top_grid_pin_42_[0], left_top_grid_pin_46_[0]}), + .sram(mux_tree_tapbuf_size10_9_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size10 mux_left_track_17 ( + .in({chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_47_[0]}), + .sram(mux_tree_tapbuf_size10_10_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size10 mux_left_track_25 ( + .in({chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_top_grid_pin_44_[0], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size10_11_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size10_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3])); + + mux_tree_tapbuf_size7 mux_top_track_32 ( + .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size7 mux_right_track_32 ( + .in({chany_top_in[10], chany_top_in[15], right_top_grid_pin_45_[0], right_top_grid_pin_49_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size7 mux_bottom_track_33 ( + .in({chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[0], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size7 mux_left_track_33 ( + .in({chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_45_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size7_mem mem_top_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_right_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v new file mode 100644 index 0000000..0897208 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v @@ -0,0 +1,734 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_1__2_(prog_clk, + chanx_right_in, + right_top_grid_pin_1_, + chany_bottom_in, + bottom_left_grid_pin_34_, + bottom_left_grid_pin_35_, + bottom_left_grid_pin_36_, + bottom_left_grid_pin_37_, + bottom_left_grid_pin_38_, + bottom_left_grid_pin_39_, + bottom_left_grid_pin_40_, + bottom_left_grid_pin_41_, + chanx_left_in, + left_top_grid_pin_1_, + ccff_head, + chanx_right_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chanx_right_in; +// +input [0:0] right_top_grid_pin_1_; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_left_grid_pin_34_; +// +input [0:0] bottom_left_grid_pin_35_; +// +input [0:0] bottom_left_grid_pin_36_; +// +input [0:0] bottom_left_grid_pin_37_; +// +input [0:0] bottom_left_grid_pin_38_; +// +input [0:0] bottom_left_grid_pin_39_; +// +input [0:0] bottom_left_grid_pin_40_; +// +input [0:0] bottom_left_grid_pin_41_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chanx_right_out; +// +output [0:19] chany_bottom_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_4_sram; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_5_sram; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_6_sram; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; + +// +// +// +// + assign chanx_left_out[3] = chanx_right_in[2]; +// +// +// + assign chanx_left_out[5] = chanx_right_in[4]; +// +// +// + assign chanx_left_out[6] = chanx_right_in[5]; +// +// +// + assign chanx_left_out[7] = chanx_right_in[6]; +// +// +// + assign chanx_left_out[9] = chanx_right_in[8]; +// +// +// + assign chanx_left_out[10] = chanx_right_in[9]; +// +// +// + assign chanx_left_out[11] = chanx_right_in[10]; +// +// +// + assign chanx_left_out[13] = chanx_right_in[12]; +// +// +// + assign chanx_left_out[14] = chanx_right_in[13]; +// +// +// + assign chanx_left_out[15] = chanx_right_in[14]; +// +// +// + assign chanx_left_out[17] = chanx_right_in[16]; +// +// +// + assign chanx_left_out[18] = chanx_right_in[17]; +// +// +// + assign chanx_left_out[19] = chanx_right_in[18]; +// +// +// + assign chanx_right_out[3] = chanx_left_in[2]; +// +// +// + assign chanx_right_out[5] = chanx_left_in[4]; +// +// +// + assign chanx_right_out[6] = chanx_left_in[5]; +// +// +// + assign chanx_right_out[7] = chanx_left_in[6]; +// +// +// + assign chanx_right_out[9] = chanx_left_in[8]; +// +// +// + assign chanx_right_out[10] = chanx_left_in[9]; +// +// +// + assign chanx_right_out[11] = chanx_left_in[10]; +// +// +// + assign chanx_right_out[13] = chanx_left_in[12]; +// +// +// + assign chanx_right_out[14] = chanx_left_in[13]; +// +// +// + assign chanx_right_out[15] = chanx_left_in[14]; +// +// +// + assign chanx_right_out[17] = chanx_left_in[16]; +// +// +// + assign chanx_right_out[18] = chanx_left_in[17]; +// +// +// + assign chanx_right_out[19] = chanx_left_in[18]; +// +// +// + + mux_tree_tapbuf_size6 mux_right_track_0 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size6 mux_right_track_4 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size6 mux_right_track_8 ( + .in({right_top_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size6 mux_left_track_5 ( + .in({chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size6 mux_left_track_9 ( + .in({chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size6_mem mem_right_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size5 mux_right_track_2 ( + .in({chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size5 mux_right_track_16 ( + .in({chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size5 mux_right_track_24 ( + .in({chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size5 mux_left_track_1 ( + .in({chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size5 mux_left_track_3 ( + .in({chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14]}), + .sram(mux_tree_tapbuf_size5_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size5 mux_left_track_17 ( + .in({chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17]}), + .sram(mux_tree_tapbuf_size5_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_5_sram_inv[0:2]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size5 mux_left_track_25 ( + .in({chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18]}), + .sram(mux_tree_tapbuf_size5_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_6_sram_inv[0:2]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size5_mem mem_right_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_right_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_5_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_6_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_32 ( + .in({chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[16])); + + mux_tree_tapbuf_size3 mux_bottom_track_13 ( + .in({chanx_right_in[10], bottom_left_grid_pin_36_[0], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size3 mux_bottom_track_15 ( + .in({chanx_right_in[12], bottom_left_grid_pin_37_[0], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size3 mux_bottom_track_17 ( + .in({chanx_right_in[13], bottom_left_grid_pin_38_[0], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size3 mux_bottom_track_19 ( + .in({chanx_right_in[14], bottom_left_grid_pin_39_[0], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size3 mux_bottom_track_21 ( + .in({chanx_right_in[16], bottom_left_grid_pin_40_[0], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .in({chanx_right_in[17], bottom_left_grid_pin_41_[0], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size3_mem mem_right_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_19 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_21 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size7 mux_bottom_track_1 ( + .in({chanx_right_in[2], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[1:2]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size7 mux_bottom_track_3 ( + .in({chanx_right_in[4], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3:4]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size7 mux_bottom_track_5 ( + .in({chanx_right_in[5], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[5], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size7 mux_bottom_track_7 ( + .in({chanx_right_in[6], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[6], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4 mux_bottom_track_9 ( + .in({chanx_right_in[8], bottom_left_grid_pin_34_[0], chanx_left_in[8], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size4 mux_bottom_track_11 ( + .in({chanx_right_in[9], bottom_left_grid_pin_35_[0], chanx_left_in[9], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size4 mux_bottom_track_25 ( + .in({chanx_right_in[18:19], bottom_left_grid_pin_34_[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size4 mux_left_track_33 ( + .in({chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[16])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in({chanx_right_in[15], bottom_left_grid_pin_35_[0]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[13])); + + mux_tree_tapbuf_size2 mux_bottom_track_29 ( + .in({chanx_right_in[11], bottom_left_grid_pin_36_[0]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size2 mux_bottom_track_31 ( + .in({chanx_right_in[7], bottom_left_grid_pin_37_[0]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[15])); + + mux_tree_tapbuf_size2 mux_bottom_track_33 ( + .in({chanx_right_in[3], bottom_left_grid_pin_38_[0]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size2 mux_bottom_track_35 ( + .in({chanx_right_in[1], bottom_left_grid_pin_39_[0]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[17])); + + mux_tree_tapbuf_size2 mux_bottom_track_37 ( + .in({chanx_right_in[0], bottom_left_grid_pin_40_[0]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in({bottom_left_grid_pin_41_[0], chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[19])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v new file mode 100644 index 0000000..07d171b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v @@ -0,0 +1,672 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_2__0_(prog_clk, + chany_top_in, + top_left_grid_pin_34_, + top_left_grid_pin_35_, + top_left_grid_pin_36_, + top_left_grid_pin_37_, + top_left_grid_pin_38_, + top_left_grid_pin_39_, + top_left_grid_pin_40_, + top_left_grid_pin_41_, + top_right_grid_pin_1_, + chanx_left_in, + left_top_grid_pin_42_, + left_top_grid_pin_43_, + left_top_grid_pin_44_, + left_top_grid_pin_45_, + left_top_grid_pin_46_, + left_top_grid_pin_47_, + left_top_grid_pin_48_, + left_top_grid_pin_49_, + left_bottom_grid_pin_1_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_34_; +// +input [0:0] top_left_grid_pin_35_; +// +input [0:0] top_left_grid_pin_36_; +// +input [0:0] top_left_grid_pin_37_; +// +input [0:0] top_left_grid_pin_38_; +// +input [0:0] top_left_grid_pin_39_; +// +input [0:0] top_left_grid_pin_40_; +// +input [0:0] top_left_grid_pin_41_; +// +input [0:0] top_right_grid_pin_1_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_42_; +// +input [0:0] left_top_grid_pin_43_; +// +input [0:0] left_top_grid_pin_44_; +// +input [0:0] left_top_grid_pin_45_; +// +input [0:0] left_top_grid_pin_46_; +// +input [0:0] left_top_grid_pin_47_; +// +input [0:0] left_top_grid_pin_48_; +// +input [0:0] left_top_grid_pin_49_; +// +input [0:0] left_bottom_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_18_sram; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_19_sram; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_20_sram; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_21_sram; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_2_sram; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_3_sram; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; + +// +// +// +// + assign chanx_left_out[19] = chany_top_in[1]; +// +// +// + assign chanx_left_out[18] = chany_top_in[2]; +// +// +// + assign chanx_left_out[17] = chany_top_in[3]; +// +// +// + assign chanx_left_out[16] = chany_top_in[4]; +// +// +// + assign chanx_left_out[15] = chany_top_in[5]; +// +// +// + assign chanx_left_out[14] = chany_top_in[6]; +// +// +// + + mux_tree_tapbuf_size6 mux_top_track_0 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size6 mux_top_track_4 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size6 mux_left_track_1 ( + .in({chany_top_in[0], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size6 mux_left_track_5 ( + .in({chany_top_in[18], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size6_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size5 mux_top_track_2 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size5 mux_top_track_6 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size5 mux_left_track_3 ( + .in({chany_top_in[19], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size5_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size5 mux_left_track_7 ( + .in({chany_top_in[17], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size5_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size5_mem mem_top_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_top_track_6 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_left_track_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_8 ( + .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size3 mux_top_track_24 ( + .in({top_left_grid_pin_34_[0], top_right_grid_pin_1_[0], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size3 mux_left_track_9 ( + .in({chany_top_in[16], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_top_in[8], left_top_grid_pin_42_[0], left_bottom_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_10 ( + .in({top_left_grid_pin_35_[0], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size2 mux_top_track_12 ( + .in({top_left_grid_pin_36_[0], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size2 mux_top_track_14 ( + .in({top_left_grid_pin_37_[0], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size2 mux_top_track_16 ( + .in({top_left_grid_pin_38_[0], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_left_grid_pin_39_[0], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_left_grid_pin_40_[0], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_left_grid_pin_41_[0], chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_top_track_26 ( + .in({top_left_grid_pin_35_[0], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_top_out[13])); + + mux_tree_tapbuf_size2 mux_top_track_28 ( + .in({top_left_grid_pin_36_[0], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chany_top_out[14])); + + mux_tree_tapbuf_size2 mux_top_track_30 ( + .in({top_left_grid_pin_37_[0], chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chany_top_out[15])); + + mux_tree_tapbuf_size2 mux_top_track_32 ( + .in({top_left_grid_pin_38_[0], chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size2 mux_top_track_34 ( + .in({top_left_grid_pin_39_[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chany_top_out[17])); + + mux_tree_tapbuf_size2 mux_top_track_36 ( + .in({top_left_grid_pin_40_[0], chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chany_top_out[18])); + + mux_tree_tapbuf_size2 mux_top_track_38 ( + .in({top_left_grid_pin_41_[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chany_top_out[19])); + + mux_tree_tapbuf_size2 mux_left_track_11 ( + .in({chany_top_in[15], left_top_grid_pin_43_[0]}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size2 mux_left_track_13 ( + .in({chany_top_in[14], left_top_grid_pin_44_[0]}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size2 mux_left_track_15 ( + .in({chany_top_in[13], left_top_grid_pin_45_[0]}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size2 mux_left_track_17 ( + .in({chany_top_in[12], left_top_grid_pin_46_[0]}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_top_in[11], left_top_grid_pin_47_[0]}), + .sram(mux_tree_tapbuf_size2_18_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_top_in[10], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size2_19_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_top_in[9], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size2_20_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2 mux_left_track_27 ( + .in({chany_top_in[7], left_top_grid_pin_43_[0]}), + .sram(mux_tree_tapbuf_size2_21_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), + .out(chanx_left_out[13])); + + mux_tree_tapbuf_size2_mem mem_top_track_10 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_12 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_14 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_26 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_28 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_30 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_34 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_36 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_38 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_27 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v new file mode 100644 index 0000000..bc9f272 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v @@ -0,0 +1,698 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_2__1_(prog_clk, + chany_top_in, + top_left_grid_pin_34_, + top_left_grid_pin_35_, + top_left_grid_pin_36_, + top_left_grid_pin_37_, + top_left_grid_pin_38_, + top_left_grid_pin_39_, + top_left_grid_pin_40_, + top_left_grid_pin_41_, + top_right_grid_pin_1_, + chany_bottom_in, + bottom_right_grid_pin_1_, + bottom_left_grid_pin_34_, + bottom_left_grid_pin_35_, + bottom_left_grid_pin_36_, + bottom_left_grid_pin_37_, + bottom_left_grid_pin_38_, + bottom_left_grid_pin_39_, + bottom_left_grid_pin_40_, + bottom_left_grid_pin_41_, + chanx_left_in, + left_top_grid_pin_42_, + left_top_grid_pin_43_, + left_top_grid_pin_44_, + left_top_grid_pin_45_, + left_top_grid_pin_46_, + left_top_grid_pin_47_, + left_top_grid_pin_48_, + left_top_grid_pin_49_, + ccff_head, + chany_top_out, + chany_bottom_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_top_in; +// +input [0:0] top_left_grid_pin_34_; +// +input [0:0] top_left_grid_pin_35_; +// +input [0:0] top_left_grid_pin_36_; +// +input [0:0] top_left_grid_pin_37_; +// +input [0:0] top_left_grid_pin_38_; +// +input [0:0] top_left_grid_pin_39_; +// +input [0:0] top_left_grid_pin_40_; +// +input [0:0] top_left_grid_pin_41_; +// +input [0:0] top_right_grid_pin_1_; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_right_grid_pin_1_; +// +input [0:0] bottom_left_grid_pin_34_; +// +input [0:0] bottom_left_grid_pin_35_; +// +input [0:0] bottom_left_grid_pin_36_; +// +input [0:0] bottom_left_grid_pin_37_; +// +input [0:0] bottom_left_grid_pin_38_; +// +input [0:0] bottom_left_grid_pin_39_; +// +input [0:0] bottom_left_grid_pin_40_; +// +input [0:0] bottom_left_grid_pin_41_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_42_; +// +input [0:0] left_top_grid_pin_43_; +// +input [0:0] left_top_grid_pin_44_; +// +input [0:0] left_top_grid_pin_45_; +// +input [0:0] left_top_grid_pin_46_; +// +input [0:0] left_top_grid_pin_47_; +// +input [0:0] left_top_grid_pin_48_; +// +input [0:0] left_top_grid_pin_49_; +// +input [0:0] ccff_head; +// +output [0:19] chany_top_out; +// +output [0:19] chany_bottom_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:3] mux_tree_tapbuf_size10_0_sram; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size10_1_sram; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; +wire [0:3] mux_tree_tapbuf_size14_0_sram; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size14_1_sram; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:2] mux_tree_tapbuf_size7_0_sram; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_1_sram; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_2_sram; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_3_sram; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_4_sram; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_5_sram; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size7_6_sram; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; +wire [0:3] mux_tree_tapbuf_size8_0_sram; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_1_sram; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; +wire [0:3] mux_tree_tapbuf_size8_2_sram; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; +wire [0:3] mux_tree_tapbuf_size9_0_sram; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; + +// +// +// +// + assign chanx_left_out[19] = chany_top_in[1]; +// +// +// + assign chany_bottom_out[3] = chany_top_in[2]; +// +// +// + assign chanx_left_out[18] = chany_top_in[3]; +// +// +// + assign chany_bottom_out[5] = chany_top_in[4]; +// +// +// + assign chany_bottom_out[6] = chany_top_in[5]; +// +// +// + assign chany_bottom_out[7] = chany_top_in[6]; +// +// +// + assign chanx_left_out[17] = chany_top_in[7]; +// +// +// + assign chany_bottom_out[9] = chany_top_in[8]; +// +// +// + assign chany_bottom_out[10] = chany_top_in[9]; +// +// +// + assign chany_bottom_out[11] = chany_top_in[10]; +// +// +// + assign chanx_left_out[16] = chany_top_in[11]; +// +// +// + assign chany_bottom_out[13] = chany_top_in[12]; +// +// +// + assign chany_bottom_out[14] = chany_top_in[13]; +// +// +// + assign chany_bottom_out[15] = chany_top_in[14]; +// +// +// + assign chanx_left_out[15] = chany_top_in[15]; +// +// +// + assign chany_bottom_out[17] = chany_top_in[16]; +// +// +// + assign chany_bottom_out[18] = chany_top_in[17]; +// +// +// + assign chany_bottom_out[19] = chany_top_in[18]; +// +// +// + assign chanx_left_out[14] = chany_top_in[19]; +// +// +// + assign chany_top_out[3] = chany_bottom_in[2]; +// +// +// + assign chany_top_out[5] = chany_bottom_in[4]; +// +// +// + assign chany_top_out[6] = chany_bottom_in[5]; +// +// +// + assign chany_top_out[7] = chany_bottom_in[6]; +// +// +// + assign chany_top_out[9] = chany_bottom_in[8]; +// +// +// + assign chany_top_out[10] = chany_bottom_in[9]; +// +// +// + assign chany_top_out[11] = chany_bottom_in[10]; +// +// +// + assign chany_top_out[13] = chany_bottom_in[12]; +// +// +// + assign chany_top_out[14] = chany_bottom_in[13]; +// +// +// + assign chany_top_out[15] = chany_bottom_in[14]; +// +// +// + assign chany_top_out[17] = chany_bottom_in[16]; +// +// +// + assign chany_top_out[18] = chany_bottom_in[17]; +// +// +// + assign chany_top_out[19] = chany_bottom_in[18]; +// +// +// + assign chanx_left_out[13] = left_top_grid_pin_43_[0]; +// +// +// + + mux_tree_tapbuf_size10 mux_top_track_0 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_36_[0], top_left_grid_pin_38_[0], top_left_grid_pin_40_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size10_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size10 mux_bottom_track_1 ( + .in({chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size10_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size10_mem mem_top_track_0 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])); + + mux_tree_tapbuf_size10_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8 mux_top_track_2 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_37_[0], top_left_grid_pin_39_[0], top_left_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size8_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size8 mux_top_track_8 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_38_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size8_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size8 mux_bottom_track_9 ( + .in({chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_41_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size8_2_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size8_mem mem_top_track_2 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_top_track_8 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])); + + mux_tree_tapbuf_size8_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])); + + mux_tree_tapbuf_size14 mux_top_track_4 ( + .in({top_left_grid_pin_34_[0], top_left_grid_pin_35_[0], top_left_grid_pin_36_[0], top_left_grid_pin_37_[0], top_left_grid_pin_38_[0], top_left_grid_pin_39_[0], top_left_grid_pin_40_[0], top_left_grid_pin_41_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size14_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size14 mux_bottom_track_5 ( + .in({chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_40_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size14_1_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size14_mem mem_top_track_4 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3])); + + mux_tree_tapbuf_size14_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3])); + + mux_tree_tapbuf_size7 mux_top_track_16 ( + .in({top_left_grid_pin_35_[0], top_left_grid_pin_39_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size7_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size7 mux_top_track_24 ( + .in({top_left_grid_pin_36_[0], top_left_grid_pin_40_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size7_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size7 mux_bottom_track_17 ( + .in({chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_38_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size7_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size7 mux_left_track_1 ( + .in({chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size7_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size7 mux_left_track_3 ( + .in({chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size7_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size7 mux_left_track_5 ( + .in({chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_top_grid_pin_42_[0], left_top_grid_pin_44_[0], left_top_grid_pin_46_[0], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size7_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size7 mux_left_track_7 ( + .in({chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_top_grid_pin_43_[0], left_top_grid_pin_45_[0], left_top_grid_pin_47_[0], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size7_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size7_mem mem_top_track_16 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_top_track_24 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_bottom_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2])); + + mux_tree_tapbuf_size7_mem mem_left_track_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6 mux_top_track_32 ( + .in({top_left_grid_pin_37_[0], top_left_grid_pin_41_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_top_out[16])); + + mux_tree_tapbuf_size6 mux_bottom_track_25 ( + .in({chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_39_[0], chanx_left_in[6], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size6 mux_bottom_track_33 ( + .in({chany_top_in[10], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_40_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size6_mem mem_top_track_32 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size9 mux_bottom_track_3 ( + .in({chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size9_0_sram[0:3]), + .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), + .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3])); + + mux_tree_tapbuf_size4 mux_left_track_9 ( + .in({chany_top_in[8], chany_bottom_in[7:8], left_top_grid_pin_42_[0]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size4 mux_left_track_11 ( + .in({chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_top_grid_pin_43_[0]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_top_grid_pin_44_[0]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_15 ( + .in({chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_top_grid_pin_45_[0]}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size4_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_top_in[13], chany_bottom_in[13], left_top_grid_pin_46_[0]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_19 ( + .in({chany_top_in[14], chany_bottom_in[14], left_top_grid_pin_47_[0]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size3 mux_left_track_21 ( + .in({chany_top_in[16], chany_bottom_in[16], left_top_grid_pin_48_[0]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size3 mux_left_track_23 ( + .in({chany_top_in[17], chany_bottom_in[17], left_top_grid_pin_49_[0]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_top_in[18], chany_bottom_in[18], left_top_grid_pin_42_[0]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_19 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_21 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_23 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v new file mode 100644 index 0000000..da1d675 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v @@ -0,0 +1,528 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module sb_2__2_(prog_clk, + chany_bottom_in, + bottom_right_grid_pin_1_, + bottom_left_grid_pin_34_, + bottom_left_grid_pin_35_, + bottom_left_grid_pin_36_, + bottom_left_grid_pin_37_, + bottom_left_grid_pin_38_, + bottom_left_grid_pin_39_, + bottom_left_grid_pin_40_, + bottom_left_grid_pin_41_, + chanx_left_in, + left_top_grid_pin_1_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail); +// +input [0:0] prog_clk; +// +input [0:19] chany_bottom_in; +// +input [0:0] bottom_right_grid_pin_1_; +// +input [0:0] bottom_left_grid_pin_34_; +// +input [0:0] bottom_left_grid_pin_35_; +// +input [0:0] bottom_left_grid_pin_36_; +// +input [0:0] bottom_left_grid_pin_37_; +// +input [0:0] bottom_left_grid_pin_38_; +// +input [0:0] bottom_left_grid_pin_39_; +// +input [0:0] bottom_left_grid_pin_40_; +// +input [0:0] bottom_left_grid_pin_41_; +// +input [0:19] chanx_left_in; +// +input [0:0] left_top_grid_pin_1_; +// +input [0:0] ccff_head; +// +output [0:19] chany_bottom_out; +// +output [0:19] chanx_left_out; +// +output [0:0] ccff_tail; + +// +// + + +// +// + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_10_sram; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_11_sram; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_12_sram; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_13_sram; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_14_sram; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_15_sram; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_16_sram; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_17_sram; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_7_sram; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_8_sram; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_9_sram; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:2] mux_tree_tapbuf_size5_0_sram; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size5_1_sram; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; + +// +// +// +// + assign chanx_left_out[1] = chany_bottom_in[0]; +// +// +// + assign chanx_left_out[3] = chany_bottom_in[2]; +// +// +// + assign chanx_left_out[5] = chany_bottom_in[4]; +// +// +// + assign chanx_left_out[6] = chany_bottom_in[5]; +// +// +// + assign chanx_left_out[7] = chany_bottom_in[6]; +// +// +// + assign chanx_left_out[8] = chany_bottom_in[7]; +// +// +// + assign chanx_left_out[9] = chany_bottom_in[8]; +// +// +// + assign chanx_left_out[10] = chany_bottom_in[9]; +// +// +// + assign chanx_left_out[11] = chany_bottom_in[10]; +// +// +// + assign chanx_left_out[13] = chany_bottom_in[12]; +// +// +// + assign chanx_left_out[14] = chany_bottom_in[13]; +// +// +// + assign chanx_left_out[15] = chany_bottom_in[14]; +// +// +// + assign chanx_left_out[16] = chany_bottom_in[15]; +// +// +// + assign chanx_left_out[17] = chany_bottom_in[16]; +// +// +// + assign chanx_left_out[18] = chany_bottom_in[17]; +// +// +// + assign chanx_left_out[19] = chany_bottom_in[18]; +// +// +// + + mux_tree_tapbuf_size6 mux_bottom_track_1 ( + .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_35_[0], bottom_left_grid_pin_37_[0], bottom_left_grid_pin_39_[0], bottom_left_grid_pin_41_[0], chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(ccff_head[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size5 mux_bottom_track_3 ( + .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size5_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size5 mux_bottom_track_7 ( + .in({bottom_left_grid_pin_34_[0], bottom_left_grid_pin_36_[0], bottom_left_grid_pin_38_[0], bottom_left_grid_pin_40_[0], chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size5_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_3 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2])); + + mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size3 mux_bottom_track_25 ( + .in({bottom_right_grid_pin_1_[0], bottom_left_grid_pin_41_[0], chanx_left_in[13]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_bottom_track_11 ( + .in({bottom_left_grid_pin_34_[0], chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size2 mux_bottom_track_13 ( + .in({bottom_left_grid_pin_35_[0], chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size2 mux_bottom_track_15 ( + .in({bottom_left_grid_pin_36_[0], chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size2 mux_bottom_track_17 ( + .in({bottom_left_grid_pin_37_[0], chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({bottom_left_grid_pin_38_[0], chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({bottom_left_grid_pin_39_[0], chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({bottom_left_grid_pin_40_[0], chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_27 ( + .in({bottom_left_grid_pin_34_[0], chanx_left_in[14]}), + .sram(mux_tree_tapbuf_size2_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .out(chany_bottom_out[13])); + + mux_tree_tapbuf_size2 mux_bottom_track_29 ( + .in({bottom_left_grid_pin_35_[0], chanx_left_in[15]}), + .sram(mux_tree_tapbuf_size2_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .out(chany_bottom_out[14])); + + mux_tree_tapbuf_size2 mux_bottom_track_31 ( + .in({bottom_left_grid_pin_36_[0], chanx_left_in[16]}), + .sram(mux_tree_tapbuf_size2_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .out(chany_bottom_out[15])); + + mux_tree_tapbuf_size2 mux_bottom_track_33 ( + .in({bottom_left_grid_pin_37_[0], chanx_left_in[17]}), + .sram(mux_tree_tapbuf_size2_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .out(chany_bottom_out[16])); + + mux_tree_tapbuf_size2 mux_bottom_track_35 ( + .in({bottom_left_grid_pin_38_[0], chanx_left_in[18]}), + .sram(mux_tree_tapbuf_size2_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .out(chany_bottom_out[17])); + + mux_tree_tapbuf_size2 mux_bottom_track_37 ( + .in({bottom_left_grid_pin_39_[0], chanx_left_in[19]}), + .sram(mux_tree_tapbuf_size2_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .out(chany_bottom_out[18])); + + mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in({bottom_left_grid_pin_40_[0], chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size2_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .out(chany_bottom_out[19])); + + mux_tree_tapbuf_size2 mux_left_track_1 ( + .in({chany_bottom_in[19], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size2 mux_left_track_5 ( + .in({chany_bottom_in[1], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size2 mux_left_track_9 ( + .in({chany_bottom_in[3], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_16_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size2 mux_left_track_25 ( + .in({chany_bottom_in[11], left_top_grid_pin_1_[0]}), + .sram(mux_tree_tapbuf_size2_17_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_11 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_13 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_15 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_17 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_29 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_31 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_33 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_35 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_37 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_1 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_5 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_9 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), + .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_25 ( + .prog_clk(prog_clk[0]), + .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), + .ccff_tail(ccff_tail[0]), + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v new file mode 100644 index 0000000..f234114 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v @@ -0,0 +1,10 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v new file mode 100644 index 0000000..faa32c6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v @@ -0,0 +1,42 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module const0(const0); +// +output [0:0] const0; + +// +// + + +// +// + + assign const0[0] = 1'b0; +endmodule +// + +// +module const1(const1); +// +output [0:0] const1; + +// +// + + +// +// + + assign const1[0] = 1'b1; +endmodule +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v new file mode 100644 index 0000000..f234114 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v @@ -0,0 +1,10 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v new file mode 100644 index 0000000..ff797ff --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v @@ -0,0 +1,107 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module frac_lut4(in, + sram, + sram_inv, + mode, + mode_inv, + lut3_out, + lut4_out); +// +input [0:3] in; +// +input [0:15] sram; +// +input [0:15] sram_inv; +// +input [0:0] mode; +// +input [0:0] mode_inv; +// +output [0:1] lut3_out; +// +output [0:0] lut4_out; + +// +wire [0:3] in; +wire [0:1] lut3_out; +wire [0:0] lut4_out; +// + + +// +// + + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X; + +// +// +// +// + + sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ ( + .A(mode[0]), + .B(in[3]), + .X(sky130_fd_sc_hd__or2_1_0_X[0])); + + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( + .A(in[0]), + .Y(sky130_fd_sc_hd__inv_1_0_Y[0])); + + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( + .A(in[1]), + .Y(sky130_fd_sc_hd__inv_1_1_Y[0])); + + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( + .A(in[2]), + .Y(sky130_fd_sc_hd__inv_1_2_Y[0])); + + sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A(sky130_fd_sc_hd__or2_1_0_X[0]), + .Y(sky130_fd_sc_hd__inv_1_3_Y[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( + .A(in[0]), + .X(sky130_fd_sc_hd__buf_2_0_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( + .A(in[1]), + .X(sky130_fd_sc_hd__buf_2_1_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( + .A(in[2]), + .X(sky130_fd_sc_hd__buf_2_2_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( + .A(sky130_fd_sc_hd__or2_1_0_X[0]), + .X(sky130_fd_sc_hd__buf_2_3_X[0])); + + frac_lut4_mux frac_lut4_mux_0_ ( + .in(sram[0:15]), + .sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}), + .sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}), + .lut3_out(lut3_out[0:1]), + .lut4_out(lut4_out[0])); + +endmodule +// + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v new file mode 100644 index 0000000..bbe4829 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v @@ -0,0 +1,931 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module mux_tree_tapbuf_size10_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size8_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size6_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size5_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size3_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:1] mem_out; +// +output [0:1] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:1] mem_out; +// +output [0:1] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size12_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:3] mem_out; +// +output [0:3] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[3]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size16_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:4] mem_out; +// +output [0:4] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[4]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( + .CLK(prog_clk[0]), + .D(mem_out[3]), + .Q(mem_out[4]), + .Q_N(mem_outb[4])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size4_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:2] mem_out; +// +output [0:2] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[2]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + +endmodule +// + + + +// +module mux_tree_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:1] mem_out; +// +output [0:1] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[1]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + +endmodule +// + + + +// +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:16] mem_out; +// +output [0:16] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[16]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + .CLK(prog_clk[0]), + .D(mem_out[0]), + .Q(mem_out[1]), + .Q_N(mem_outb[1])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + .CLK(prog_clk[0]), + .D(mem_out[1]), + .Q(mem_out[2]), + .Q_N(mem_outb[2])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + .CLK(prog_clk[0]), + .D(mem_out[2]), + .Q(mem_out[3]), + .Q_N(mem_outb[3])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( + .CLK(prog_clk[0]), + .D(mem_out[3]), + .Q(mem_out[4]), + .Q_N(mem_outb[4])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( + .CLK(prog_clk[0]), + .D(mem_out[4]), + .Q(mem_out[5]), + .Q_N(mem_outb[5])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( + .CLK(prog_clk[0]), + .D(mem_out[5]), + .Q(mem_out[6]), + .Q_N(mem_outb[6])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( + .CLK(prog_clk[0]), + .D(mem_out[6]), + .Q(mem_out[7]), + .Q_N(mem_outb[7])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( + .CLK(prog_clk[0]), + .D(mem_out[7]), + .Q(mem_out[8]), + .Q_N(mem_outb[8])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( + .CLK(prog_clk[0]), + .D(mem_out[8]), + .Q(mem_out[9]), + .Q_N(mem_outb[9])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( + .CLK(prog_clk[0]), + .D(mem_out[9]), + .Q(mem_out[10]), + .Q_N(mem_outb[10])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( + .CLK(prog_clk[0]), + .D(mem_out[10]), + .Q(mem_out[11]), + .Q_N(mem_outb[11])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( + .CLK(prog_clk[0]), + .D(mem_out[11]), + .Q(mem_out[12]), + .Q_N(mem_outb[12])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( + .CLK(prog_clk[0]), + .D(mem_out[12]), + .Q(mem_out[13]), + .Q_N(mem_outb[13])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( + .CLK(prog_clk[0]), + .D(mem_out[13]), + .Q(mem_out[14]), + .Q_N(mem_outb[14])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( + .CLK(prog_clk[0]), + .D(mem_out[14]), + .Q(mem_out[15]), + .Q_N(mem_outb[15])); + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( + .CLK(prog_clk[0]), + .D(mem_out[15]), + .Q(mem_out[16]), + .Q_N(mem_outb[16])); + +endmodule +// + + + +// +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +// +input [0:0] prog_clk; +// +input [0:0] ccff_head; +// +output [0:0] ccff_tail; +// +output [0:0] mem_out; +// +output [0:0] mem_outb; + +// +// + + +// +// + + + +// +// +// + assign ccff_tail[0] = mem_out[0]; +// + + sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + .CLK(prog_clk[0]), + .D(ccff_head[0]), + .Q(mem_out[0]), + .Q_N(mem_outb[0])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v new file mode 100644 index 0000000..7ddd317 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v @@ -0,0 +1,1397 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +module mux_tree_tapbuf_size10(in, + sram, + sram_inv, + out); +// +input [0:9] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_9_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[7]), + .A0(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[9]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size8(in, + sram, + sram_inv, + out); +// +input [0:7] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_7_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[5]), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[7]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size6(in, + sram, + sram_inv, + out); +// +input [0:5] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_5_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size5(in, + sram, + sram_inv, + out); +// +input [0:4] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_4_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[4]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size14(in, + sram, + sram_inv, + out); +// +input [0:13] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_13_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_13_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size3(in, + sram, + sram_inv, + out); +// +input [0:2] in; +// +input [0:1] sram; +// +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_2_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +// +input [0:1] in; +// +input [0:1] sram; +// +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_1_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size7(in, + sram, + sram_inv, + out); +// +input [0:6] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_6_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(const1_0_const1[0]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size9(in, + sram, + sram_inv, + out); +// +input [0:8] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_8_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[8]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size12(in, + sram, + sram_inv, + out); +// +input [0:11] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_11_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[11]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size16(in, + sram, + sram_inv, + out); +// +input [0:15] in; +// +input [0:4] sram; +// +input [0:4] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_15_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(in[4]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(in[5]), + .A0(in[6]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(in[7]), + .A0(in[8]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( + .A1(in[9]), + .A0(in[10]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( + .A1(in[11]), + .A0(in[12]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( + .A1(in[13]), + .A0(in[14]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( + .A1(in[15]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_13_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_14_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_13_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_14_X[0]), + .S(sram[4]), + .X(sky130_fd_sc_hd__mux2_1_15_X[0])); + +endmodule +// + + + +// +module mux_tree_tapbuf_size4(in, + sram, + sram_inv, + out); +// +input [0:3] in; +// +input [0:2] sram; +// +input [0:2] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A(sky130_fd_sc_hd__mux2_1_3_X[0]), + .X(out[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(in[2]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(in[3]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + +endmodule +// + + + +// +module mux_tree_size2(in, + sram, + sram_inv, + out); +// +input [0:1] in; +// +input [0:1] sram; +// +input [0:1] sram_inv; +// +output [0:0] out; + +// +// + + +// +// + + +wire [0:0] const1_0_const1; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; + +// +// +// +// + + const1 const1_0_ ( + .const1(const1_0_const1[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(const1_0_const1[0]), + .S(sram[1]), + .X(out[0])); + +endmodule +// + + + +// +module frac_lut4_mux(in, + sram, + sram_inv, + lut3_out, + lut4_out); +// +input [0:15] in; +// +input [0:3] sram; +// +input [0:3] sram_inv; +// +output [0:1] lut3_out; +// +output [0:0] lut4_out; + +// +// + + +// +// + + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; + +// +// +// +// + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( + .A(sky130_fd_sc_hd__mux2_1_12_X[0]), + .X(lut3_out[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( + .A(sky130_fd_sc_hd__mux2_1_13_X[0]), + .X(lut3_out[1])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( + .A(sky130_fd_sc_hd__mux2_1_14_X[0]), + .X(lut4_out[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( + .A(sky130_fd_sc_hd__mux2_1_8_X[0]), + .X(sky130_fd_sc_hd__buf_2_3_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( + .A(sky130_fd_sc_hd__mux2_1_9_X[0]), + .X(sky130_fd_sc_hd__buf_2_4_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( + .A(sky130_fd_sc_hd__mux2_1_10_X[0]), + .X(sky130_fd_sc_hd__buf_2_5_X[0])); + + sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( + .A(sky130_fd_sc_hd__mux2_1_11_X[0]), + .X(sky130_fd_sc_hd__buf_2_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( + .A1(in[0]), + .A0(in[1]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_0_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( + .A1(in[2]), + .A0(in[3]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_1_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( + .A1(in[4]), + .A0(in[5]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_2_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( + .A1(in[6]), + .A0(in[7]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_3_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( + .A1(in[8]), + .A0(in[9]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_4_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( + .A1(in[10]), + .A0(in[11]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_5_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( + .A1(in[12]), + .A0(in[13]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_6_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( + .A1(in[14]), + .A0(in[15]), + .S(sram[0]), + .X(sky130_fd_sc_hd__mux2_1_7_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_8_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_9_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_10_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), + .S(sram[1]), + .X(sky130_fd_sc_hd__mux2_1_11_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A1(sky130_fd_sc_hd__buf_2_3_X[0]), + .A0(sky130_fd_sc_hd__buf_2_4_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_12_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A1(sky130_fd_sc_hd__buf_2_5_X[0]), + .A0(sky130_fd_sc_hd__buf_2_6_X[0]), + .S(sram[2]), + .X(sky130_fd_sc_hd__mux2_1_13_X[0])); + + sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A1(sky130_fd_sc_hd__mux2_1_12_X[0]), + .A0(sky130_fd_sc_hd__mux2_1_13_X[0]), + .S(sram[3]), + .X(sky130_fd_sc_hd__mux2_1_14_X[0])); + +endmodule +// + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v new file mode 100644 index 0000000..be56f7f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v @@ -0,0 +1,29 @@ +`timescale 1ns/1ps + +// +// +// +// +// +// + +// +// +// + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v new file mode 100644 index 0000000..8bbc5d8 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v @@ -0,0 +1,34 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +// +module direct_interc(in, + out); +// +input [0:0] in; +// +output [0:0] out; + +// +// + + +// +// + +wire [0:0] in; +wire [0:0] out; + assign out[0] = in[0]; +endmodule +// + + +// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v new file mode 100644 index 0000000..d288329 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v @@ -0,0 +1,2274 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +module top_autocheck_top_tb; +// +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] clk; + +// +wire [0:7] gfpga_pad_GPIO_Y; + + +wire [0:7] gfpga_pad_GPIO_A; +wire [0:7] gfpga_pad_GPIO_IE; +wire [0:7] gfpga_pad_GPIO_OE; + +reg [0:0] config_done; +wire [0:0] prog_clock; +reg [0:0] prog_clock_reg; +wire [0:0] op_clock; +reg [0:0] op_clock_reg; +reg [0:0] prog_reset; +reg [0:0] prog_set; +reg [0:0] greset; +reg [0:0] gset; +// +reg [0:0] ccff_head; +// +wire [0:0] ccff_tail; +// + reg [0:0] a; + reg [0:0] b; + +// + wire [0:0] out:c_fpga; + +`ifdef AUTOCHECKED_SIMULATION + +// + wire [0:0] out:c_benchmark; + +// + reg [0:0] out:c_flag; + +`endif + +// + integer nb_error= 1; +// +// +initial + begin + config_done[0] = 1'b0; + end + +// + +// +initial + begin + prog_clock_reg[0] = 1'b0; + end +always + begin + #5 prog_clock_reg[0] = ~prog_clock_reg[0]; + end + +// + +// + assign prog_clock[0] = prog_clock_reg[0] & (~config_done[0]) & (~prog_reset[0]); + +// +initial + begin + op_clock_reg[0] = 1'b0; + end +always wait(~greset) + begin + #0.4159859717 op_clock_reg[0] = ~op_clock_reg[0]; + end + +// +// + assign op_clock[0] = op_clock_reg[0] & config_done[0]; + +// +initial + begin + prog_reset[0] = 1'b1; + #10 prog_reset[0] = 1'b0; + end + +// + +// +initial + begin + prog_set[0] = 1'b1; + #10 prog_set[0] = 1'b0; + end + +// + +// +// +initial + begin + greset[0] = 1'b1; + wait(config_done) + #0.8319719434 greset[0] = 1'b1; + #1.663943887 greset[0] = 1'b0; + end + +// +// +initial + begin + gset[0] = 1'b0; + end + +// + +// + assign clk[0] = op_clock[0]; + assign prog_clk[0] = prog_clock[0]; + assign Test_en[0] = 1'b0; +// +// + fpga_top FPGA_DUT ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0])); + +// +// + assign gfpga_pad_GPIO_Y[4] = a[0]; +// + assign gfpga_pad_GPIO_Y[6] = b[0]; +// + assign out:c_fpga[0] = gfpga_pad_GPIO_Y[5]; + +// + assign gfpga_pad_GPIO_Y[0] = 1'b0; + assign gfpga_pad_GPIO_Y[1] = 1'b0; + assign gfpga_pad_GPIO_Y[2] = 1'b0; + assign gfpga_pad_GPIO_Y[3] = 1'b0; + assign gfpga_pad_GPIO_Y[7] = 1'b0; + +`ifdef AUTOCHECKED_SIMULATION +// + top REF_DUT( + .a(a), + .b(b), + .c(out:c_benchmark) ); +// + +`endif + + +// +task prog_cycle_task; +input [0:0] ccff_head_val; + begin + @(negedge prog_clock[0]); + ccff_head[0] = ccff_head_val[0]; + end +endtask + +// +initial + begin +// + ccff_head[0] = 1'b0; + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + 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prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + 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prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + @(negedge prog_clock[0]); + config_done[0] <= 1'b1; + end +// +// + initial begin + a <= 1'b0; + b <= 1'b0; + + out:c_flag[0] <= 1'b0; + end + +// + always@(negedge op_clock[0]) begin + a <= $random; + b <= $random; + end + +`ifdef AUTOCHECKED_SIMULATION +// +// + reg [0:0] sim_start; + + always@(negedge op_clock[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else begin + if(!(out:c_fpga === out:c_benchmark) && !(out:c_benchmark === 1'bx)) begin + out:c_flag <= 1'b1; + end else begin + out:c_flag<= 1'b0; + end + end + end + + always@(posedge out:c_flag) begin + if(out:c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on out:c_fpga at time = %t", $realtime); + end + end + +`endif + +`ifdef AUTOCHECKED_SIMULATION +// + always@(posedge config_done[0]) begin + nb_error = nb_error - 1; + end +`endif + +`ifdef ICARUS_SIMULATOR +// + initial begin + $dumpfile("top_formal.vcd"); + $dumpvars(1, top_autocheck_top_tb); + end +`endif +// + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// + #20121 + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + +endmodule +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v new file mode 100644 index 0000000..0a9714c --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_formal_random_top_tb.v @@ -0,0 +1,126 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +module top_top_formal_verification_random_tb; +// + reg [0:0] clk; + +// + reg [0:0] a; + reg [0:0] b; + +// + wire [0:0] out:c_gfpga; + +`ifdef AUTOCHECKED_SIMULATION + +// + wire [0:0] out:c_bench; + +// + reg [0:0] out:c_flag; + +`endif + +// + integer nb_error= 0; + +// + top_top_formal_verification FPGA_DUT( + .a_fm(a), + .b_fm(b), + .out:c_fm(out:c_gfpga) ); +// + +`ifdef AUTOCHECKED_SIMULATION +// + top REF_DUT( + .a(a), + .b(b), + .c(out:c_bench) ); +// + +`endif + +// + initial begin + clk[0] <= 1'b0; + while(1) begin + #0.4159859701 + clk[0] <= !clk[0]; + end + end + +// + initial begin + a <= 1'b0; + b <= 1'b0; + + out:c_flag[0] <= 1'b0; + end + +// + always@(negedge clk[0]) begin + a <= $random; + b <= $random; + end + +`ifdef AUTOCHECKED_SIMULATION +// +// + reg [0:0] sim_start; + + always@(negedge clk[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else begin + if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin + out:c_flag <= 1'b1; + end else begin + out:c_flag<= 1'b0; + end + end + end + + always@(posedge out:c_flag) begin + if(out:c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on out:c_gfpga at time = %t", $realtime); + end + end + +`endif + +`ifdef ICARUS_SIMULATOR +// + initial begin + $dumpfile("top_formal.vcd"); + $dumpvars(1, top_top_formal_verification_random_tb); + end +`endif +// + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// + #332 + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + +endmodule +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v new file mode 100644 index 0000000..50c918d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v @@ -0,0 +1,31 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +// +`include "./SRC/define_simulation.v" + +// +`include "./SRC/fabric_netlists.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "top_output_verilog.v" +`endif + +`ifdef ENABLE_FORMAL_VERIFICATION + `include "./SRC/top_top_formal_verification.v" + `ifdef FORMAL_SIMULATION + `include "./SRC/top_formal_random_top_tb.v" + `endif +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "./SRC/top_autocheck_top_tb.v" +`endif + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v new file mode 100644 index 0000000..a68418f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v @@ -0,0 +1,2242 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps + +module top_top_formal_verification ( +input [0:0] a_fm, +input [0:0] b_fm, +output [0:0] out:c_fm); + +// +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] clk; +wire [0:7] gfpga_pad_GPIO_Y; +wire [0:7] gfpga_pad_GPIO_A; +wire [0:7] gfpga_pad_GPIO_IE; +wire [0:7] gfpga_pad_GPIO_OE; +wire [0:0] ccff_head; +wire [0:0] ccff_tail; + +// + fpga_top U0_formal_verification ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .gfpga_pad_GPIO_A(gfpga_pad_GPIO_A[0:7]), + .gfpga_pad_GPIO_IE(gfpga_pad_GPIO_IE[0:7]), + .gfpga_pad_GPIO_OE(gfpga_pad_GPIO_OE[0:7]), + .gfpga_pad_GPIO_Y(gfpga_pad_GPIO_Y[0:7]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0])); + +// + assign prog_clk[0] = 1'b0; + assign Test_en[0] = 1'b0; +// + +// +// + assign gfpga_pad_GPIO_Y[4] = a_fm[0]; +// + assign gfpga_pad_GPIO_Y[6] = b_fm[0]; +// + assign out:c_fm[0] = gfpga_pad_GPIO_Y[5]; + +// + assign gfpga_pad_GPIO_Y[0] = 1'b0; + assign gfpga_pad_GPIO_Y[1] = 1'b0; + assign gfpga_pad_GPIO_Y[2] = 1'b0; + assign gfpga_pad_GPIO_Y[3] = 1'b0; + assign gfpga_pad_GPIO_Y[7] = 1'b0; + +// +`ifdef ICARUS_SIMULATOR +// + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000110000001; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; + assign U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b010; + assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b1}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = 3'b110; + assign U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = 3'b010; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3] = 4'b0010; + assign U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_4.mem_out[0:4] = {5{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_24.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_4.mem_out[0:4] = {5{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4] = {5{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:4] = {5{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_15.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:2] = {3{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b1}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b1}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b1}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; + assign U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; +initial begin + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111001111110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = 2'b10; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b101; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = 3'b001; + force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = 3'b101; + force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3] = 4'b1101; + force U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_4.mem_outb[0:4] = {5{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_24.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_4.mem_outb[0:4] = {5{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4] = {5{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:4] = {5{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_11.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b0}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; +end +// +`else +// +initial begin + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + 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$deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b010); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b101); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], 3'b110); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], 3'b001); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_16.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], 3'b010); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], 3'b101); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:3], 4'b0010); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:3], 4'b1101); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_4.mem_out[0:4], {5{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_4.mem_outb[0:4], {5{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_24.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_24.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_4.mem_out[0:4], {5{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_4.mem_outb[0:4], {5{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4], {5{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4], {5{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:4], {5{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:4], {5{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_6.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_14.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_20.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_28.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_30.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_32.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_34.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_36.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_11.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_13.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_24.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_11.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_13.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_13.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_15.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_15.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:2], {3{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_31.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_35.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_37.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_39.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); + $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__1_.mem_bottom_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_0__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); + $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); +end +// +`endif +// +endmodule +// + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit new file mode 100644 index 0000000..546bf36 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit @@ -0,0 +1 @@ +00000000000000000000000011111010000000001000000000000111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log new file mode 100644 index 0000000..56a83fa --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log @@ -0,0 +1,904 @@ +/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga +Reading script file top_run.openfpga... + + ___ _____ ____ ____ _ + / _ \ _ __ ___ _ __ | ___| _ \ / ___| / \ + | | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \ + | |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \ + \___/| .__/ \___|_| |_|_| |_| \____/_/ \_\ + |_| + + OpenFPGA: An Open-source FPGA IP Generator + Versatile Place and Route (VPR) + FPGA-Verilog + FPGA-SPICE + FPGA-SDC + FPGA-Bitstream + + This is a free software under the MIT License + + Copyright (c) 2018 LNIS - The University of Utah + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + + + +Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off +VPR FPGA Placement and Routing. +Version: 0.0.0+48b2bff0 +Revision: 48b2bff0 +Compiled: 2020-09-27T20:43:27 +Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 +Build Info: release VTR_ASSERT_LEVEL=2 + +University of Toronto +verilogtorouting.org +vtr-users@googlegroups.com +This is free open source code under MIT license. + +VPR was run with the following command-line: +vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off + + +Architecture file: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml +Circuit name: top + +# Loading Architecture Description +Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) +Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) +# Loading Architecture Description took 0.01 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB) +# Building complex block graph +Warning 6: [LINE 546] false logically-equivalent pin clb[0].I0[1]. +Warning 7: [LINE 546] false logically-equivalent pin clb[0].I0[2]. +Warning 8: [LINE 546] false logically-equivalent pin clb[0].I0[3]. +Warning 9: [LINE 548] false logically-equivalent pin clb[0].I1[1]. +Warning 10: [LINE 548] false logically-equivalent pin clb[0].I1[2]. +Warning 11: [LINE 548] false logically-equivalent pin clb[0].I1[3]. +Warning 12: [LINE 550] false logically-equivalent pin clb[0].I2[1]. +Warning 13: [LINE 550] false logically-equivalent pin clb[0].I2[2]. +Warning 14: [LINE 550] false logically-equivalent pin clb[0].I2[3]. +Warning 15: [LINE 552] false logically-equivalent pin clb[0].I3[1]. +Warning 16: [LINE 552] false logically-equivalent pin clb[0].I3[2]. +Warning 17: [LINE 552] false logically-equivalent pin clb[0].I3[3]. +Warning 18: [LINE 554] false logically-equivalent pin clb[0].I4[1]. +Warning 19: [LINE 554] false logically-equivalent pin clb[0].I4[2]. +Warning 20: [LINE 554] false logically-equivalent pin clb[0].I4[3]. +Warning 21: [LINE 556] false logically-equivalent pin clb[0].I5[1]. +Warning 22: [LINE 556] false logically-equivalent pin clb[0].I5[2]. +Warning 23: [LINE 556] false logically-equivalent pin clb[0].I5[3]. +Warning 24: [LINE 558] false logically-equivalent pin clb[0].I6[1]. +Warning 25: [LINE 558] false logically-equivalent pin clb[0].I6[2]. +Warning 26: [LINE 558] false logically-equivalent pin clb[0].I6[3]. +Warning 27: [LINE 560] false logically-equivalent pin clb[0].I7[1]. +Warning 28: [LINE 560] false logically-equivalent pin clb[0].I7[2]. +Warning 29: [LINE 560] false logically-equivalent pin clb[0].I7[3]. +# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.8 MiB) +# Load circuit +# Load circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.3 MiB) +# Clean circuit +Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs +Inferred 0 additional primitive pins as constant generators due to constant inputs +Swept input(s) : 0 +Swept output(s) : 0 (0 dangling, 0 constant) +Swept net(s) : 0 +Swept block(s) : 0 +Constant Pins Marked: 0 +# Clean circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Compress circuit +# Compress circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +# Verify circuit +# Verify circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +Circuit Statistics: + Blocks: 4 + .input : 2 + .output: 1 + 4-LUT : 1 + Nets : 3 + Avg Fanout: 1.0 + Max Fanout: 1.0 + Min Fanout: 1.0 + Netlist Clocks: 0 +# Build Timing Graph + Timing Graph Nodes: 6 + Timing Graph Edges: 5 + Timing Graph Levels: 4 +# Build Timing Graph took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +Netlist contains 0 clocks +# Load Timing Constraints + +SDC file 'top.sdc' not found +Setting default timing constraints: + * constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock' + * optimize virtual clock to run as fast as possible +Timing constraints created 1 clocks + Constrained Clock 'virtual_io_clock' (Virtual Clock) + +# Load Timing Constraints took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB) +Timing analysis: ON +Circuit netlist file: top.net +Circuit placement file: top.place +Circuit routing file: top.route +Circuit SDC file: top.sdc + +Packer: ENABLED +Placer: ENABLED +Router: ENABLED +Analysis: ENABLED + +NetlistOpts.abosrb_buffer_luts : false +NetlistOpts.sweep_dangling_primary_ios : true +NetlistOpts.sweep_dangling_nets : true +NetlistOpts.sweep_dangling_blocks : true +NetlistOpts.sweep_constant_primary_outputs: false + +PackerOpts.allow_unrelated_clustering: auto +PackerOpts.alpha_clustering: 0.750000 +PackerOpts.beta_clustering: 0.900000 +PackerOpts.cluster_seed_type: BLEND2 +PackerOpts.connection_driven: true +PackerOpts.global_clocks: true +PackerOpts.hill_climbing_flag: false +PackerOpts.inter_cluster_net_delay: 1.000000 +PackerOpts.timing_driven: true +PackerOpts.target_external_pin_util: auto +PlacerOpts.place_freq: PLACE_ONCE +PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE +PlacerOpts.pad_loc_type: FREE +PlacerOpts.place_cost_exp: 1.000000 +PlacerOpts.place_chan_width: 40 +PlacerOpts.inner_loop_recompute_divider: 0 +PlacerOpts.recompute_crit_iter: 1 +PlacerOpts.timing_tradeoff: 0.500000 +PlacerOpts.td_place_exp_first: 1.000000 +PlacerOpts.td_place_exp_last: 8.000000 +PlaceOpts.seed: 1 +AnnealSched.type: AUTO_SCHED +AnnealSched.inner_num: 1.000000 + +RouterOpts.route_type: DETAILED +RouterOpts.router_algorithm: TIMING_DRIVEN +RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH +RouterOpts.fixed_channel_width: 40 +RouterOpts.trim_empty_chan: false +RouterOpts.trim_obs_chan: false +RouterOpts.acc_fac: 1.000000 +RouterOpts.bb_factor: 3 +RouterOpts.bend_cost: 0.000000 +RouterOpts.first_iter_pres_fac: 0.000000 +RouterOpts.initial_pres_fac: 0.500000 +RouterOpts.pres_fac_mult: 1.300000 +RouterOpts.max_router_iterations: 50 +RouterOpts.min_incremental_reroute_fanout: 16 +RouterOpts.astar_fac: 1.200000 +RouterOpts.criticality_exp: 1.000000 +RouterOpts.max_criticality: 0.990000 +RouterOpts.routing_failure_predictor = SAFE +RouterOpts.routing_budgets_algorithm = DISABLE + +AnalysisOpts.gen_post_synthesis_netlist: false + +RoutingArch.directionality: UNI_DIRECTIONAL +RoutingArch.switch_block_type: WILTON +RoutingArch.Fs: 3 + +# Packing +Begin packing 'top.blif'. + +After removing unused inputs... + total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1 +Begin prepacking. +Finish prepacking. +Using inter-cluster delay: 1.33777e-09 +Packing with pin utilization targets: io:1,1 clb:0.8,1 +Packing with high fanout thresholds: io:128 clb:32 +Not enough resources expand FPGA size to (4 x 4) +Complex block 0: 'c' (clb) . +Complex block 1: 'out:c' (io) . +Complex block 2: 'a' (io) . +Complex block 3: 'b' (io) . + +Pb types usage... + inpad : 2 + outpad : 1 + fle : 1 + clb : 1 + lut3inter : 1 + ble3 : 1 + io : 3 + lut3 : 1 + lut : 1 + + +Logic Element (fle) detailed count: + Total number of Logic Elements used : 1 + LEs used for logic and registers : 0 + LEs used for logic only : 1 + LEs used for registers only : 0 + + EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0 + io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 + clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 +Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. +FPGA sized to 4 x 4 (2x2) +Device Utilization: 0.25 (target 1.00) + Block Utilization: 0.38 Type: io + Block Utilization: 0.25 Type: clb + + +Netlist conversion complete. + +# Packing took 0.01 seconds (max_rss 10.5 MiB, delta_rss +0.7 MiB) +# Load Packing +Begin loading packed FPGA netlist file. +Netlist generated from file 'top.net'. +Detected 0 constant generators (to see names run with higher pack verbosity) +Finished loading packed FPGA netlist file (took 0.02 seconds). +Warning 30: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). +# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) +Warning 31: Netlist contains 0 global net to non-global architecture pin connections + +Netlist num_nets: 3 +Netlist num_blocks: 4 +Netlist EMPTY blocks: 0. +Netlist io blocks: 3. +Netlist clb blocks: 1. +Netlist inputs pins: 2 +Netlist output pins: 1 + +# Create Device +## Build Device Grid +FPGA sized to 4 x 4: 16 grid tiles (2x2) + +Resource usage... + Netlist + 3 blocks of type: io + Architecture + 8 blocks of type: io + Netlist + 1 blocks of type: clb + Architecture + 4 blocks of type: clb + +Device Utilization: 0.25 (target 1.00) + Physical Tile io: + Block Utilization: 0.38 Logical Block: io + Physical Tile clb: + Block Utilization: 0.25 Logical Block: clb + +## Build Device Grid took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.0 MiB) +## Build tileable routing resource graph +X-direction routing channel width is 40 +Y-direction routing channel width is 40 +Warning 32: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 33: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 34: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 35: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 36: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. + This is possible on a fringe node based on low Fc_out, N, and certain lengths. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) + RR Graph Nodes: 684 + RR Graph Edges: 2780 +# Create Device took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB) + +# Placement +## Computing placement delta delay look-up +### Build routing resource graph +Warning 37: in check_rr_node: RR node: 109 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 38: in check_rr_node: RR node: 110 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 39: in check_rr_node: RR node: 293 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 40: in check_rr_node: RR node: 294 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 41: in check_rr_graph: fringe node 2 IPIN at (0,1) has no fanin. + This is possible on a fringe node based on low Fc_out, N, and certain lengths. +### Build routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 732 + RR Graph Edges: 2188 +### Computing delta delays +### Computing delta delays took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) +## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB) + +There are 3 point to point connections in this circuit. + + +BB estimate of min-dist (placement) wire length: 11 + +Completed placement consistency check successfully. +Initial placement cost: 1 bb_cost: 0.275 td_cost: 5.6541e-10 +Initial placement estimated Critical Path Delay (CPD): 0.69331 ns +Initial placement estimated setup Total Negative Slack (sTNS): -0.69331 ns +Initial placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns + +Initial placement estimated setup slack histogram: +[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +Placement contains 0 placement macros involving 0 blocks (average macro size -nan) + +------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ + T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha +------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ +5.6e-01 0.892 0.21 5.1708e-10 0.693 -0.693 -0.693 1.000 0.0754 3.0 1.00 6 0.500 +2.8e-01 1.001 0.25 5.8474e-10 0.693 -0.693 -0.693 1.000 0.1044 3.0 1.00 12 0.500 +1.4e-01 0.828 0.19 5.1901e-10 0.751 -0.751 -0.751 0.833 0.0971 3.0 1.00 18 0.900 +1.3e-01 1.119 0.21 5.3388e-10 0.693 -0.693 -0.693 0.500 0.0412 3.0 1.00 24 0.950 +1.2e-01 1.017 0.24 5.3998e-10 0.693 -0.693 -0.693 0.833 0.0366 3.0 1.00 30 0.900 +1.1e-01 0.960 0.24 5.3641e-10 0.693 -0.693 -0.693 1.000 0.0433 3.0 1.00 36 0.500 +5.4e-02 0.970 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0405 3.0 1.00 42 0.950 +5.1e-02 0.974 0.19 4.4803e-10 0.635 -0.635 -0.635 0.667 0.0470 3.0 1.00 48 0.950 +4.9e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 54 0.950 +4.6e-02 1.063 0.19 4.5701e-10 0.635 -0.635 -0.635 0.500 0.0549 2.7 2.12 60 0.950 +4.4e-02 1.019 0.21 4.9794e-10 0.693 -0.693 -0.693 0.667 0.0458 2.8 1.56 66 0.950 +4.2e-02 1.043 0.21 5.1943e-10 0.693 -0.693 -0.693 0.667 0.0215 3.0 1.00 72 0.950 +4.0e-02 0.903 0.18 4.7533e-10 0.751 -0.751 -0.751 0.500 0.0052 3.0 1.00 78 0.950 +3.8e-02 1.042 0.20 4.4941e-10 0.693 -0.693 -0.693 0.333 0.0000 3.0 1.00 84 0.950 +3.6e-02 1.000 0.20 4.2544e-10 0.635 -0.635 -0.635 0.167 0.0000 2.7 2.12 90 0.950 +3.4e-02 1.069 0.22 4.4576e-10 0.635 -0.635 -0.635 0.667 0.0458 1.9 4.68 96 0.950 +3.2e-02 0.969 0.21 4.6916e-10 0.693 -0.693 -0.693 0.667 0.0361 2.4 3.14 102 0.950 +3.1e-02 0.968 0.19 4.7066e-10 0.693 -0.693 -0.693 0.500 0.0537 2.9 1.24 108 0.950 +2.9e-02 0.997 0.18 4.322e-10 0.635 -0.635 -0.635 0.500 0.0000 3.0 1.00 114 0.950 +2.8e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 120 0.950 +2.6e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 2.7 2.12 126 0.950 +2.5e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 2.8 1.56 132 0.950 +2.4e-02 0.994 0.18 4.0763e-10 0.635 -0.635 -0.635 0.167 0.0000 2.5 2.62 138 0.950 +2.3e-02 0.996 0.18 3.9202e-10 0.635 -0.635 -0.635 0.500 0.0064 1.8 5.05 144 0.950 +2.1e-02 1.000 0.18 4.0247e-10 0.635 -0.635 -0.635 0.333 0.0000 2.0 4.66 150 0.950 +2.0e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.7 5.39 156 0.950 +1.9e-02 1.071 0.20 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 7.06 162 0.950 +1.8e-02 0.967 0.18 5.0741e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.79 168 0.950 +1.7e-02 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 174 0.950 +1.7e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 180 0.950 +1.6e-02 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 186 0.950 +1.5e-02 0.989 0.18 3.5797e-10 0.635 -0.635 -0.635 0.667 0.0076 1.1 7.79 192 0.950 +1.4e-02 1.000 0.18 3.8602e-10 0.635 -0.635 -0.635 0.667 0.0000 1.3 6.95 198 0.950 +1.3e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.6 5.92 204 0.950 +1.3e-02 0.991 0.18 3.7094e-10 0.635 -0.635 -0.635 0.500 0.0078 1.4 6.51 210 0.950 +1.2e-02 0.995 0.18 3.809e-10 0.635 -0.635 -0.635 0.333 0.0113 1.5 6.21 216 0.950 +1.2e-02 1.000 0.18 4.1466e-10 0.693 -0.693 -0.693 0.167 0.0000 1.3 6.78 222 0.950 +1.1e-02 0.971 0.18 3.491e-10 0.693 -0.693 -0.693 0.500 0.0000 1.0 8.00 228 0.950 +1.0e-02 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 234 0.950 +9.9e-03 1.015 0.18 4.086e-10 0.635 -0.635 -0.635 0.333 0.0205 1.0 8.00 240 0.950 +9.4e-03 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 246 0.950 +9.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.667 0.0000 1.0 8.00 252 0.950 +8.5e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.333 0.0000 1.2 7.21 258 0.950 +8.1e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.66 264 0.950 +7.7e-03 1.000 0.18 3.8297e-10 0.635 -0.635 -0.635 0.167 0.0000 1.2 7.43 270 0.950 +7.3e-03 0.992 0.18 3.6408e-10 0.635 -0.635 -0.635 0.667 0.0090 1.0 8.00 276 0.950 +6.9e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.500 0.0000 1.2 7.21 282 0.950 +6.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 6.95 288 0.950 +6.3e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.4 6.68 294 0.950 +5.9e-03 1.000 0.18 3.8973e-10 0.635 -0.635 -0.635 0.500 0.0000 1.5 6.39 300 0.950 +5.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.5 6.08 306 0.950 +5.4e-03 0.995 0.18 3.788e-10 0.635 -0.635 -0.635 0.500 0.0079 1.4 6.66 312 0.950 +5.1e-03 1.000 0.18 3.8986e-10 0.635 -0.635 -0.635 0.167 0.0000 1.5 6.37 318 0.950 +4.8e-03 1.000 0.18 3.8095e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.77 324 0.950 +4.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.55 330 0.950 +4.4e-03 0.995 0.18 3.7402e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.31 336 0.950 +4.1e-03 0.986 0.18 3.5684e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 7.06 342 0.950 +3.9e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 348 0.950 +3.7e-03 0.985 0.18 3.5034e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 354 0.950 +3.6e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 360 0.950 +3.4e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 366 0.950 +3.2e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.79 372 0.950 +3.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.57 378 0.950 +2.9e-03 0.995 0.18 3.7386e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.33 384 0.950 +2.8e-03 0.990 0.18 3.6614e-10 0.635 -0.635 -0.635 0.500 0.0082 1.3 7.08 390 0.950 +2.6e-03 1.000 0.18 3.8688e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.82 396 0.950 +2.5e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 402 0.950 +2.4e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.000 0.0000 1.1 7.79 408 0.950 +2.2e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 414 0.950 +2.1e-03 0.995 0.18 3.7067e-10 0.635 -0.635 -0.635 0.500 0.0088 1.1 7.79 420 0.950 +2.0e-03 0.985 0.18 3.5227e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.57 426 0.950 +1.9e-03 0.992 0.18 3.6418e-10 0.635 -0.635 -0.635 0.333 0.0110 1.0 7.99 432 0.950 +1.8e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 438 0.950 +1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 444 0.950 +1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 450 0.000 + +BB estimate of min-dist (placement) wire length: 7 + +Completed placement consistency check successfully. + +Swaps called: 454 + +Placement estimated critical path delay: 0.63531 ns +Placement estimated setup Total Negative Slack (sTNS): -0.63531 ns +Placement estimated setup Worst Negative Slack (sWNS): -0.63531 ns + +Placement estimated setup slack histogram: +[ -6.4e-10: -6.4e-10) 1 (100.0%) |************************************************** +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | +[ -6.4e-10: -6.4e-10) 0 ( 0.0%) | + +Placement cost: 1, bb_cost: 0.175, td_cost: 4.4941e-10, + +Placement resource usage: + io implemented as io : 3 + clb implemented as clb: 1 + +Placement number of temperatures: 75 +Placement total # of swap attempts: 454 + Swaps accepted: 208 (45.8 %) + Swaps rejected: 246 (54.2 %) + Swaps aborted : 0 ( 0.0 %) + +Aborted Move Reasons: +# Placement took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.5 MiB) + +# Routing +## Build tileable routing resource graph +X-direction routing channel width is 40 +Y-direction routing channel width is 40 +Warning 42: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 43: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 44: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. +Warning 45: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges. +Warning 46: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin. + This is possible on a fringe node based on low Fc_out, N, and certain lengths. +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.0 MiB) + RR Graph Nodes: 684 + RR Graph Edges: 2780 +Confirming router algorithm: TIMING_DRIVEN. +---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- +Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ + (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter +---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- + 1 0.0 0.0 0 80 3 3 0 ( 0.000%) 6 ( 1.2%) 0.693 -0.6933 -0.693 0.000 0.000 N/A +Restoring best routing +Critical path: 0.69331 ns +Successfully routed after 1 routing iterations. +Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 80 total_heap_pops: 45 +# Routing took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.1 MiB) + +Checking to ensure routing is legal... +Completed routing consistency check successfully. + +Serial number (magic cookie) for the routing is: -11536 +Circuit successfully routed with a channel width factor of 40. + +Average number of bends per net: 0.333333 Maximum # of bends: 1 + +Number of global nets: 0 +Number of routed nets (nonglobal): 3 +Wire length results (in units of 1 clb segments)... + Total wirelength: 6, average net length: 2.00000 + Maximum net length: 3 + +Wire length results in terms of physical segments... + Total wiring segments used: 5, average wire segments per net: 1.66667 + Maximum segments used by a net: 2 + Total local nets with reserved CLB opins: 0 + +Routing channel utilization histogram: +[ 1: inf) 0 ( 0.0%) | +[ 0.9: 1) 0 ( 0.0%) | +[ 0.8: 0.9) 0 ( 0.0%) | +[ 0.7: 0.8) 0 ( 0.0%) | +[ 0.5: 0.6) 0 ( 0.0%) | +[ 0.4: 0.5) 0 ( 0.0%) | +[ 0.3: 0.4) 0 ( 0.0%) | +[ 0.2: 0.3) 0 ( 0.0%) | +[ 0.1: 0.2) 0 ( 0.0%) | +[ 0: 0.1) 18 (100.0%) |************************************************ +Maximum routing channel utilization: 0.075 at (1,0) + +X - Directed channels: j max occ ave occ capacity + ---- ------- ------- -------- + 0 3 1.250 40 + 1 0 0.000 40 + 2 0 0.000 40 +Y - Directed channels: i max occ ave occ capacity + ---- ------- ------- -------- + 0 1 0.250 40 + 1 0 0.000 40 + 2 0 0.000 40 + +Total tracks in x-direction: 120, in y-direction: 120 + +Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)... + Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576 + Total used logic block area: 53894 + +Routing area (in minimum width transistor areas)... + Total routing area: 22261.4, per logic tile: 1391.34 + +Segment usage by type (index): type utilization + ---- ----------- + 0 0.0833 + 1 0.0278 + 2 0 + +Segment usage by length: length utilization + ------ ----------- + 1 0.0833 + 2 0.0278 + 4 0 + + +Hold Worst Negative Slack (hWNS): 0 ns +Hold Total Negative Slack (hTNS): 0 ns + +Hold slack histogram: +[ 5.5e-10: 5.5e-10) 1 (100.0%) |************************************************** +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | +[ 5.5e-10: 5.5e-10) 0 ( 0.0%) | + +Final critical path: 0.69331 ns, Fmax: 1442.36 MHz +Setup Worst Negative Slack (sWNS): -0.69331 ns +Setup Total Negative Slack (sTNS): -0.69331 ns + +Setup slack histogram: +[ -6.9e-10: -6.9e-10) 1 (100.0%) |************************************************** +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | +[ -6.9e-10: -6.9e-10) 0 ( 0.0%) | + +Timing analysis took 0.000535006 seconds (0.000479183 STA, 5.5823e-05 slack) (80 full updates: 78 setup, 0 hold, 2 combined). +VPR suceeded +The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) + +Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml + +Confirm selected options when call command 'read_openfpga_arch': +--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml +Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... +Read OpenFPGA architecture +Warning 47: Automatically set circuit model 'frac_lut4' to be default in its type. +Warning 48: Automatically set circuit model 'sky130_fd_sc_hd__sdfxbp_1' to be default in its type. +Warning 49: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. +Warning 50: Automatically set circuit model 'GPIO' to be default in its type. +Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') +Read OpenFPGA architecture took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.3 MiB) +Check circuit library +Checking circuit library passed. +Check circuit library took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +Found 0 errors when checking configurable memory circuit models! + +Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +Confirm selected options when call command 'read_openfpga_simulation_setting': +--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... +Read OpenFPGA simulation settings +Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) + +Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges + +Confirm selected options when call command 'link_openfpga_arch': +--activity_file: top_ace_out.act +--sort_gsb_chan_node_in_edges: on +--verbose: off +Link OpenFPGA architecture to VPR architecture + +Building annotation for physical modes in pb_type...Done +Check physical mode annotation for pb_types passed. + +Building annotation about physical types for pb_type interconnection...Done + +Building annotation between operating and physical pb_types...Done +Check physical pb_type annotation for pb_types passed. + +Building annotation between physical pb_types and circuit models...Done +Check physical pb_type annotation for circuit model passed. + +Building annotation between physical pb_types and mode selection bits...Done +Check pb_type annotation for mode selection bits passed. +Assigning unique indices for primitive pb_graph nodes...Done +Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done +Check pb_graph annotation for physical nodes and pins passed. +Binded 4 routing resource graph switches to circuit models +Binded 3 routing segments to circuit models +Binded 2 direct connections to circuit models +Annotating rr_node with routed nets...Done with 11 nodes mapping +Annotating previous nodes for rr_node...Warning 51: Override the previous node '89' by previous node '90' for node '37' with in routing context annotation! +Done with 14 nodes mapping +# Build General Switch Block(GSB) annotation on top of routing resource graph +[11%] Backannotated GSB[0][0] +[22%] Backannotated GSB[0][1] +[33%] Backannotated GSB[0][2] +[44%] Backannotated GSB[1][0] +[55%] Backannotated GSB[1][1] +[66%] Backannotated GSB[1][2] +[77%] Backannotated GSB[2][0] +[88%] Backannotated GSB[2][1] +[100%] Backannotated GSB[2][2] +Backannotated 9 General Switch Blocks (GSBs). +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) +[11%] Sorted edges for GSB[0][0] +[22%] Sorted edges for GSB[0][1] +[33%] Sorted edges for GSB[0][2] +[44%] Sorted edges for GSB[1][0] +[55%] Sorted edges for GSB[1][1] +[66%] Sorted edges for GSB[1][2] +[77%] Sorted edges for GSB[2][0] +[88%] Sorted edges for GSB[2][1] +[100%] Sorted edges for GSB[2][2] +Sorted edges for 9 General Switch Blocks (GSBs). +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB) +# Build a library of physical multiplexers +Built a multiplexer library of 14 physical multiplexers. +Maximum multiplexer size is 17. +# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) +# Build the annotation about direct connection between tiles +Built 6 tile-to-tile direct connections +# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) +Building annotation for mapped blocks on grid locations...Done +User specified the operating clock frequency to use VPR results +Use VPR critical path delay 8.31972e-19 [ns] with a 20 [%] slack in OpenFPGA. +Will apply operating clock frequency 1201.96 [MHz] to simulations +User specified the number of operating clock cycles to be inferred from signal activities +Average net density: 0.42 +Median net density: 0.00 +Average net density after weighting: 0.42 +Will apply 2 operating clock cycles to simulations +Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB) + +Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml + +Confirm selected options when call command 'build_fabric': +--frame_view: off +--compress_routing: on +--duplicate_grid_pin: on +--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml +--write_fabric_key: off +--generate_random_fabric_key: off +--verbose: off +Identify unique General Switch Blocks (GSBs) +Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%) +Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) + +Read Fabric Key +Read Fabric Key took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) + +Build fabric module graph +# Build constant generator modules +# Build constant generator modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build user-defined modules +# Build user-defined modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build essential (inverter/buffer/logic gate) modules +# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Build local encoder (for multiplexers) modules +# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +# Building multiplexer modules +# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) +# Build Look-Up Table (LUT) modules +# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.0 MiB) +# Build wire modules +# Build wire modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.0 MiB) +# Build memory modules +# Build memory modules took 0.00 seconds (max_rss 13.1 MiB, delta_rss +0.3 MiB) +# Build grid modules +Building logical tiles...Done +Building physical tiles...Done +# Build grid modules took 0.00 seconds (max_rss 13.6 MiB, delta_rss +0.5 MiB) +# Build unique routing modules... +# Build unique routing modules... took 0.01 seconds (max_rss 15.9 MiB, delta_rss +2.3 MiB) +# Build FPGA fabric module +## Add grid instances to top module +## Add grid instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add switch block instances to top module +## Add switch block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module +## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module +## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB) +## Add module nets between grids and GSBs +## Add module nets between grids and GSBs took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.5 MiB) +## Add module nets for inter-tile connections +## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.0 MiB) +## Add module nets for configuration buses +## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.1 MiB) +# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +0.9 MiB) +Build fabric module graph took 0.02 seconds (max_rss 16.8 MiB, delta_rss +4.2 MiB) + +Command line to execute: repack + +Confirm selected options when call command 'repack': +--verbose: off +Build routing resource graph for the physical implementation of logical tile +Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.3 MiB) +Repack clustered blocks to physical implementation of logical tile +Repack clustered block 'c'...Done +Repack clustered block 'out:c'...Done +Repack clustered block 'a'...Done +Repack clustered block 'b'...Done +Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) +Build truth tables for physical LUTs +Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB) + +Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml + +Confirm selected options when call command 'build_architecture_bitstream': +--write_file: fabric_indepenent_bitstream.xml +--read_file: off +--verbose: off + +Build fabric-independent bitstream for implementation 'top' + +Generating bitstream for Switch blocks...Done +Generating bitstream for X-direction Connection blocks ...Done +Generating bitstream for Y-direction Connection blocks ...Done + +Build fabric-independent bitstream for implementation 'top' + took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) +Warning 52: Directory path is empty and nothing will be created. +Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' +Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + +Command line to execute: build_fabric_bitstream + +Confirm selected options when call command 'build_fabric_bitstream': +--verbose: off + +Build fabric dependent bitstream + + +Build fabric dependent bitstream + took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + +Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit + +Confirm selected options when call command 'write_fabric_bitstream': +--file, -f: fabric_bitstream.bit +--format: plain_text +--verbose: off +Warning 53: Directory path is empty and nothing will be created. +Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' +Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + +Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml + +Confirm selected options when call command 'write_fabric_bitstream': +--file, -f: fabric_bitstream.xml +--format: xml +--verbose: off +Warning 54: Directory path is empty and nothing will be created. +Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' +Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) + +Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose + +Confirm selected options when call command 'write_fabric_verilog': +--file, -f: ./SRC +--explicit_port_mapping: on +--include_timing: on +--include_signal_init: on +--support_icarus_simulator: on +--print_user_defined_template: off +--verbose: on +Write Verilog netlists for FPGA fabric + +Succeed to create directory './SRC' +Succeed to create directory './SRC/sub_module' +Succeed to create directory './SRC/lb' +Succeed to create directory './SRC/routing' +Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done +Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done +Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done +Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done +Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done +Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done +Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done + +Writing logical tiles... +Writing Verilog netlists for logic tile 'io' ... +Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done +Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ... +Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done +Done + +Writing Verilog netlists for logic tile 'clb' ... +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ... +Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done +Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ... +Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done +Done + +Writing logical tiles...Done + +Building physical tiles... +Writing Verilog Netlist './SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done +Writing Verilog Netlist './SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done +Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done +Building physical tiles...Done + +Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done +Written 70 Verilog modules in total +Write Verilog netlists for FPGA fabric + took 0.14 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) + +Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +Confirm selected options when call command 'write_verilog_testbench': +--file, -f: ./SRC +--reference_benchmark_file_path: top_output_verilog.v +--print_top_testbench: on +--fast_configuration: off +--print_formal_verification_top_netlist: off +--print_preconfig_top_testbench: on +--print_simulation_ini: ./SimulationDeck/simulation_deck.ini +--explicit_port_mapping: on +--verbose: off +Warning 55: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled +Write Verilog testbenches for FPGA fabric + +Warning 56: Directory './SRC' already exists. Will overwrite contents +# Write pre-configured FPGA top-level Verilog netlist for design 'top' +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' +Will use 2010 configuration clock cycles to top testbench +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +Succeed to create directory './SimulationDeck' +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +Write Verilog testbenches for FPGA fabric + took 0.03 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) + +Command line to execute: exit + +Confirm selected options when call command 'exit': + +Finish execution with 0 errors + +The entire OpenFPGA flow took 0.22 seconds + +Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl new file mode 100644 index 0000000..d322db5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl @@ -0,0 +1,12 @@ +set DIE_HEIGHT 1200 +set DIE_WIDTH 1200 +set DESIGN_NAME fpga_core +set TASK_NAME FPGA22_HIER_SKY_task +set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog +set FPGA_ROW 2 +set FPGA_COL 2 +set INIT_DESIGN_INPUT DP_RM_NDM +set TECHNOLOGY skywater +set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ grid_clb grid_io_bottom grid_io_left grid_io_right grid_io_top]; +set DP_FLOW "hier"; +set DESIGN_STYLE "hier"; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml new file mode 100644 index 0000000..1f3d05a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml new file mode 100644 index 0000000..2f3088b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml @@ -0,0 +1,255 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml new file mode 100644 index 0000000..536b9fc --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml @@ -0,0 +1,598 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.regin clb.scin + clb.O[7:0] clb.I0 clb.I1 clb.I2 clb.I3 + clb.regout clb.scout clb.O[15:8] clb.I4 clb.I5 clb.I6 clb.I7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf new file mode 100644 index 0000000..e372ec2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf @@ -0,0 +1,37 @@ + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif + +[SYNTHESIS_PARAM] +bench0_top = top +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf new file mode 100644 index 0000000..e372ec2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf @@ -0,0 +1,37 @@ + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif + +[SYNTHESIS_PARAM] +bench0_top = top +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf new file mode 100644 index 0000000..0f65eca --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf @@ -0,0 +1,33 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif + +[SYNTHESIS_PARAM] +bench0_top = top +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py new file mode 100644 index 0000000..75f4ab1 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py @@ -0,0 +1,71 @@ +import yaml +import argparse +import pprint as pp +import glob +import os + + +def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60) + + +parser = argparse.ArgumentParser(formatter_class=formatter) + +# Mandatory arguments +parser.add_argument('--hierfile', type=str, default="design.hier") +parser.add_argument('--shellscript_name', type=str, default="sdc_expand.sh") +parser.add_argument('--in_dir', type=str, default="./sdc/") +parser.add_argument('--out_dir', type=str, default="./sdc/expanded") +parser.add_argument('--extract_format', type=str, default="tcl") +parser.add_argument('--compress', type=bool, default=False) +args = parser.parse_args() + +print(f"In_dir = {args.in_dir}") +print(f"Out_dir = {args.out_dir}") +if args.extract_format == "sdc": + with open(args.hierfile) as f: + with open(args.shellscript_name, 'w') as fp: + designHier = yaml.load(f, Loader=yaml.FullLoader) + for eachHier in designHier: + for eachMod, instanceList in eachHier.items(): + fp.write(f"mkdir -p {eachMod}\n") + for eachInst in instanceList: + eachInst = eachInst.replace("/", "_") + st = (f"sed \"s/{eachMod}/{eachInst}/g\" {args.in_dir}/{eachMod}.sdc " + + f"> {args.out_dir}/{eachInst}/{eachInst}.sdc\n") + fp.write(st) + if args.compress: + fp.write(f"tar -zcvf {args.out_dir}/{eachMod}.tar.gz " + f"{args.out_dir}/{eachInst}/") +elif args.extract_format == "tcl": + files = glob.glob(os.path.join(args.in_dir, 'grid*.txt')) + filename = files[0] + print(f"Reading {filename}") + with open(filename) as f: + with open(args.shellscript_name, 'w') as fp: + designHier = yaml.load(f, Loader=yaml.FullLoader)[:5] + for eachModule in designHier: + ForLoopStruct = [] + while True: + instList = eachModule[list(eachModule.keys())[0]] + iterAgain = all([isinstance(ele, str) for ele in instList]) + if (iterAgain): + # print(list(eachModule.keys())[0]) + # print(f">> leaf Instance {instList}") + ForLoopStruct.append({ + list(eachModule.keys())[0]: + instList + }) + break + else: + ForLoopStruct.append({ + list(eachModule.keys())[0]: + [list(ee.keys())[0] for ee in instList] + }) + # print(list(eachModule.keys())[0]) + # print([list(ee.keys())[0] for ee in instList]) + eachModule = instList[0] + del ForLoopStruct[1::2] + print("= = "*10) + print("ForLoop Struct") + pp.pprint(ForLoopStruct) + print("= = "*10) diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga new file mode 100644 index 0000000..2c8e5b5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga @@ -0,0 +1,46 @@ +# This script is designed to generate fabric Verilog netlists +# with a fixed device layout +# It will only output netlists to be used by backend tools, +# i.e., Synopsys ICC2, including +# - Verilog netlists +# - fabric hierarchy description for ICC2's hierarchical flow +# - Timing/Design constraints +# +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack + +build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml + +build_fabric_bitstream +write_fabric_bitstream --format plain_text --file fabric_bitstream.bit +write_fabric_bitstream --format xml --file fabric_bitstream.xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose + +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga new file mode 100644 index 0000000..124dbcd --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga @@ -0,0 +1,70 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200 + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml + +build_fabric_bitstream + +# Build fabric-dependent bitstream +build_fabric_bitstream +write_fabric_bitstream --format plain_text --file fabric_bitstream.bit +write_fabric_bitstream --format xml --file fabric_bitstream.xml +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act new file mode 100644 index 0000000..0f77bc6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act @@ -0,0 +1,3 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.25 diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif new file mode 100644 index 0000000..67d9787 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif @@ -0,0 +1,8 @@ +.model top +.inputs a b +.outputs c + +.names a b c +11 1 + +.end diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v new file mode 100644 index 0000000..876f1c6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v @@ -0,0 +1,14 @@ +`timescale 1ns / 1ps + +module top( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a & b; + +endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v new file mode 100644 index 0000000..be56f7f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v @@ -0,0 +1,29 @@ +`timescale 1ns/1ps + +// +// +// +// +// +// + +// +// +// + +module GPIO (A, IE, OE, Y, in, out, mem_out); + output A; + output IE; + output OE; + output Y; + input in; + output out; + input mem_out; + + assign A = in; + assign out = Y; + assign IE = mem_out; + sky130_fd_sc_hd__inv_1 ie_oe_inv ( + .A (mem_out), + .Y (OE) ); +endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/skywater b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/skywater new file mode 120000 index 0000000..a240d7a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/skywater @@ -0,0 +1 @@ +/research/ece/lnis/CAD_TOOLS/DKITS/skywater \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/README.md b/FPGA22_HIER_SKY_PNR/README.md new file mode 100644 index 0000000..79a751b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/README.md @@ -0,0 +1,24 @@ +FPGA22_HIER_SKY_PNR +==================== + +2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD` + +Directory Structure +------------------- +**FPGA22_HIER_SKY_task** :- OpenFPGA task directory and all related files +**FPGA22_HIER_SKY_Verilog** :- Verilog-netlist used for this design +**modules** :- Final files of each module (lef,def,spef,v,gds) +**fpga_core** :- Final files of fpga_core (eFPGA design) +**fpga_top** :- Reserved for design with GPIOs or caravel + +Checks +--------- +- .tech file DRC - Clean +- Timing SignOff - Clean + +Pending +--------- +- Tap cell addition +- DRC SignOff +- PostPnR function simulation + diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v new file mode 100644 index 0000000..396cb2d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v @@ -0,0 +1,32472 @@ +// +// +// +// +// +// +module direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_7_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_3_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; + +mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; + +mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; + +mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_8_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_8_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_3_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; + +mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_7_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_20_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_11_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_7_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_5_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_5_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_4_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_4_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_3_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_2_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_2_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_0_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_25_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_23_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_23_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_22_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_22_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_21_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_21_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_20_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_20_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_19_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_19_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_18_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_17_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_17_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_16_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_16_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_15_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_15_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_14_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_14_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_13_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_13_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_12_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_12_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_11_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_11_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_10_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_9_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_8_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_8_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_7_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_7_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_6_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_5_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_4_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_4_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_3_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_0_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; + +mux_tree_tapbuf_size10_11 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size14_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_8 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_32_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_26_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_26_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_25_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_25_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_24_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_24_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_23_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_23_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_21_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_20_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_14_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_11_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_10_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_9_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_8_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_8_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_6_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_4_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_4_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_0_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; + +mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6_8 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_9 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_21 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_27_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_26_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_26_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_25_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_24_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_23_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_23_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_22_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_22_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_21_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_21_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_20_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_20_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_19_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_19_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_18_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_18_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_17_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_17_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_16_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_15_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_15_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_14_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_14_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_13_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_13_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_12_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_12_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_11_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_10_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_10_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_9_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_9_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_8_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_8_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_7_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_6_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_4_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_4_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_3_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_2_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; + +mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_7 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_8 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4_7 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_26_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_26_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_25_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_25_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_24_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_24_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_23_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_23_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_22_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_22_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_21_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_21_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_20_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_20_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_19_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_19_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_18_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_18_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_17_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_17_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_16_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_16_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_15_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_15_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_14_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_14_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_13_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_13_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_12_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_12_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_11_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_10_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_10_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_9_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_9_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_8_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_6_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_5_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_4_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_3_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_2_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_0_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; +mux_tree_tapbuf_size7_6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_30_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_30_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_29_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_29_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_28_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_28_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_27_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_27_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module const1_26_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_26_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_25_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_25_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_24_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_23_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_23_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_20_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_20_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_19_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_19_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_18_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_18_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_17_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_17_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_16_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_15_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_15_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_14_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_14_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_13_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_13_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_12_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_12_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_11_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_11_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_10_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_9_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_8_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_8_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_7_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_7_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_6_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_6_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_5_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_5_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_4_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_4_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_0_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_0_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size4_6 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_7 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_5_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_5_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_4_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_4_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_3_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_3_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_2_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_2_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_0_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_0_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; + +mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_26_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_26_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_25_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_24_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_23_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_23_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_22_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_22_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_21_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_21_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_20_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_20_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_19_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_19_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_18_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_17_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_17_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_16_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_16_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_15_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_15_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_14_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_14_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_13_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_13_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_12_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_12_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_11_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_10_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_10_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_9_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_8_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_8_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_7_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_6_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_6_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_5_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_4_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_4_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_3_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_0_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; +mux_tree_tapbuf_size5_1 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_16_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_15_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_14_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_14_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_13_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_13_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_12_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_12_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_7_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_5_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_5_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_4_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_4_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_3_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_3_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_2_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_0_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) ) ; +endmodule + + +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_aps_2 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_11 ( .A ( net_aps_2 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_3 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , + ccff_head , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_14 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( right_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_15 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_8 ( .A ( aps_rename_2_ ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_14 ) , + .X ( gfpga_pad_GPIO_IE[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_2 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , + ccff_head , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( top_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_17 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_6 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( BUF_net_6 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_581 ( .A ( ropt_net_19 ) , + .X ( gfpga_pad_GPIO_IE[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_579 ( .A ( ropt_net_16 ) , + .X ( ropt_net_19 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_580 ( .A ( ropt_net_17 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_1 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_8 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_8 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_11 ( .A ( BUF_net_8 ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , + ccff_head , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] left_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_13 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_9 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_12 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_12 ) , + .X ( ropt_net_15 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_13 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_net_7 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_7 ( .A ( net_net_7 ) , + .X ( net_net_6 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_10 ( .A ( net_net_6 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_9 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( BUF_net_9 ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , + ccff_head , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( ccff_head ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_14 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_5 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( BUF_net_5 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_14 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_21 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +output p_abuf1 ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( p_abuf1 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_108 ( .A ( p_abuf1 ) , + .X ( net_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_133 ( .A ( net_net_133 ) , + .X ( ff_Q[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , + p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign p_abuf0 = p_abuf1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf1 ( p_abuf1 ) ) ; +mux_tree_size2_21 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_22 mux_fabric_out_1 ( + .in ( { p_abuf1 , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_23 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__269 ( .A ( fabric_scout[0] ) , + .X ( fabric_regout[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__46 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_18 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_19 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_20 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__41 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_29 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_15 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_16 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_17 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_28 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_12 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_13 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_14 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_10 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_9 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p2 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_26 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_6 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_7 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_8 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_25 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_25 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , + p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_3 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_4 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_5 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; +input p1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_1 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_0 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_1 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_2 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , + clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , + clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , + p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , + p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] clb_I0 ; +input [0:3] clb_I1 ; +input [0:3] clb_I2 ; +input [0:3] clb_I3 ; +input [0:3] clb_I4 ; +input [0:3] clb_I5 ; +input [0:3] clb_I6 ; +input [0:3] clb_I7 ; +input [0:0] clb_regin ; +input [0:0] clb_scin ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_regout ; +output [0:0] clb_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_2_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; + +logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I1 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .p0 ( p0 ) , .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I2 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { p_abuf4 , logical_tile_clb_mode_default__fle_2_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I3 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , logical_tile_clb_mode_default__fle_3_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .p2 ( p3 ) ) ; +logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I4 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I5 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I6 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I7 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , + .p2 ( p3 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( clb_O[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( clb_O[2] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( clb_O[3] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_out ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf4 } ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( clb_O[7] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( clb_O[9] ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( clb_O[10] ) ) ; +direct_interc direct_interc_11_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; +direct_interc direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( clb_O[12] ) ) ; +direct_interc direct_interc_13_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; +direct_interc direct_interc_14_ ( + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .out ( clb_O[14] ) ) ; +direct_interc direct_interc_15_ ( + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , + .out ( clb_O[15] ) ) ; +direct_interc direct_interc_16_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , + .out ( { p_abuf16 } ) ) ; +direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , + .out ( { p_abuf17 } ) ) ; +direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , + .out ( clb_I0[0] ) ) ; +direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .out ( clb_I0[1] ) ) ; +direct_interc direct_interc_20_ ( + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , + .out ( clb_I0[2] ) ) ; +direct_interc direct_interc_21_ ( + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .out ( clb_I0[3] ) ) ; +direct_interc direct_interc_22_ ( + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , + .out ( clb_regin ) ) ; +direct_interc direct_interc_23_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , + .out ( clb_scin ) ) ; +direct_interc direct_interc_24_ ( + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_25_ ( + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , + .out ( clb_I1[0] ) ) ; +direct_interc direct_interc_26_ ( + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I1[1] ) ) ; +direct_interc direct_interc_27_ ( + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , + .out ( clb_I1[2] ) ) ; +direct_interc direct_interc_28_ ( + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .out ( clb_I1[3] ) ) ; +direct_interc direct_interc_29_ ( + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; +direct_interc direct_interc_30_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; +direct_interc direct_interc_31_ ( + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_32_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , + .out ( clb_I2[0] ) ) ; +direct_interc direct_interc_33_ ( + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I2[1] ) ) ; +direct_interc direct_interc_34_ ( + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , + .out ( clb_I2[2] ) ) ; +direct_interc direct_interc_35_ ( + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .out ( clb_I2[3] ) ) ; +direct_interc direct_interc_36_ ( + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; +direct_interc direct_interc_37_ ( + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; +direct_interc direct_interc_38_ ( + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_39_ ( + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , + .out ( clb_I3[0] ) ) ; +direct_interc direct_interc_40_ ( + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I3[1] ) ) ; +direct_interc direct_interc_41_ ( + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , + .out ( clb_I3[2] ) ) ; +direct_interc direct_interc_42_ ( + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .out ( clb_I3[3] ) ) ; +direct_interc direct_interc_43_ ( + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; +direct_interc direct_interc_44_ ( + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; +direct_interc direct_interc_45_ ( + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_46_ ( + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , + .out ( clb_I4[0] ) ) ; +direct_interc direct_interc_47_ ( + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I4[1] ) ) ; +direct_interc direct_interc_48_ ( + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , + .out ( clb_I4[2] ) ) ; +direct_interc direct_interc_49_ ( + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .out ( clb_I4[3] ) ) ; +direct_interc direct_interc_50_ ( + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; +direct_interc direct_interc_51_ ( + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; +direct_interc direct_interc_52_ ( + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_53_ ( + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , + .out ( clb_I5[0] ) ) ; +direct_interc direct_interc_54_ ( + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I5[1] ) ) ; +direct_interc direct_interc_55_ ( + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .out ( clb_I5[2] ) ) ; +direct_interc direct_interc_56_ ( + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .out ( clb_I5[3] ) ) ; +direct_interc direct_interc_57_ ( + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; +direct_interc direct_interc_58_ ( + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; +direct_interc direct_interc_59_ ( + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , + .out ( clb_I6[0] ) ) ; +direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I6[1] ) ) ; +direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , + .out ( clb_I6[2] ) ) ; +direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .out ( clb_I6[3] ) ) ; +direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; +direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; +direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , + .out ( clb_I7[0] ) ) ; +direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_69 } ) , + .out ( clb_I7[1] ) ) ; +direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_70 } ) , + .out ( clb_I7[2] ) ) ; +direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_71 } ) , + .out ( clb_I7[3] ) ) ; +direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_72 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; +direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_73 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; +direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .out ( clb_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( clb_O[1] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( .A ( p_abuf4 ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( clb_O[2] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , .X ( clb_O[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( clb_O[7] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( clb_O[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( clb_O[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_62 ) , + .X ( p_abuf2 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_83 ( .A ( clb_O[12] ) , + .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( clb_O[15] ) , + .X ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , + .X ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_64 ) , + .X ( p_abuf3 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_67 ) , + .X ( p_abuf5 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_106 ( .A ( BUF_net_69 ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( BUF_net_58 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( clb_O[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_71 ) , + .X ( p_abuf7 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_73 ) , + .X ( p_abuf8 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_75 ) , + .X ( p_abuf9 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( .A ( BUF_net_77 ) , + .X ( p_abuf10 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_118 ( .A ( BUF_net_79 ) , + .X ( p_abuf11 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( BUF_net_81 ) , + .X ( p_abuf12 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_83 ) , + .X ( p_abuf13 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( BUF_net_85 ) , + .X ( p_abuf14 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_87 ) , + .X ( p_abuf15 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( BUF_net_106 ) , + .X ( p_abuf6 ) ) ; +endmodule + + +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , + right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , + right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , + right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , + right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , + right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , + right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , + right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , + bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , + bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , + bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , + bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , + bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , + bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , + bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , + bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , right_width_0_height_0__pin_34_upper , + right_width_0_height_0__pin_34_lower , + right_width_0_height_0__pin_35_upper , + right_width_0_height_0__pin_35_lower , + right_width_0_height_0__pin_36_upper , + right_width_0_height_0__pin_36_lower , + right_width_0_height_0__pin_37_upper , + right_width_0_height_0__pin_37_lower , + right_width_0_height_0__pin_38_upper , + right_width_0_height_0__pin_38_lower , + right_width_0_height_0__pin_39_upper , + right_width_0_height_0__pin_39_lower , + right_width_0_height_0__pin_40_upper , + right_width_0_height_0__pin_40_lower , + right_width_0_height_0__pin_41_upper , + right_width_0_height_0__pin_41_lower , + bottom_width_0_height_0__pin_42_upper , + bottom_width_0_height_0__pin_42_lower , + bottom_width_0_height_0__pin_43_upper , + bottom_width_0_height_0__pin_43_lower , + bottom_width_0_height_0__pin_44_upper , + bottom_width_0_height_0__pin_44_lower , + bottom_width_0_height_0__pin_45_upper , + bottom_width_0_height_0__pin_45_lower , + bottom_width_0_height_0__pin_46_upper , + bottom_width_0_height_0__pin_46_lower , + bottom_width_0_height_0__pin_47_upper , + bottom_width_0_height_0__pin_47_lower , + bottom_width_0_height_0__pin_48_upper , + bottom_width_0_height_0__pin_48_lower , + bottom_width_0_height_0__pin_49_upper , + bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] right_width_0_height_0__pin_1_ ; +input [0:0] right_width_0_height_0__pin_2_ ; +input [0:0] right_width_0_height_0__pin_3_ ; +input [0:0] right_width_0_height_0__pin_4_ ; +input [0:0] right_width_0_height_0__pin_5_ ; +input [0:0] right_width_0_height_0__pin_6_ ; +input [0:0] right_width_0_height_0__pin_7_ ; +input [0:0] right_width_0_height_0__pin_8_ ; +input [0:0] right_width_0_height_0__pin_9_ ; +input [0:0] right_width_0_height_0__pin_10_ ; +input [0:0] right_width_0_height_0__pin_11_ ; +input [0:0] right_width_0_height_0__pin_12_ ; +input [0:0] right_width_0_height_0__pin_13_ ; +input [0:0] right_width_0_height_0__pin_14_ ; +input [0:0] right_width_0_height_0__pin_15_ ; +input [0:0] bottom_width_0_height_0__pin_16_ ; +input [0:0] bottom_width_0_height_0__pin_17_ ; +input [0:0] bottom_width_0_height_0__pin_18_ ; +input [0:0] bottom_width_0_height_0__pin_19_ ; +input [0:0] bottom_width_0_height_0__pin_20_ ; +input [0:0] bottom_width_0_height_0__pin_21_ ; +input [0:0] bottom_width_0_height_0__pin_22_ ; +input [0:0] bottom_width_0_height_0__pin_23_ ; +input [0:0] bottom_width_0_height_0__pin_24_ ; +input [0:0] bottom_width_0_height_0__pin_25_ ; +input [0:0] bottom_width_0_height_0__pin_26_ ; +input [0:0] bottom_width_0_height_0__pin_27_ ; +input [0:0] bottom_width_0_height_0__pin_28_ ; +input [0:0] bottom_width_0_height_0__pin_29_ ; +input [0:0] bottom_width_0_height_0__pin_30_ ; +input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] left_width_0_height_0__pin_52_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_34_upper ; +output [0:0] right_width_0_height_0__pin_34_lower ; +output [0:0] right_width_0_height_0__pin_35_upper ; +output [0:0] right_width_0_height_0__pin_35_lower ; +output [0:0] right_width_0_height_0__pin_36_upper ; +output [0:0] right_width_0_height_0__pin_36_lower ; +output [0:0] right_width_0_height_0__pin_37_upper ; +output [0:0] right_width_0_height_0__pin_37_lower ; +output [0:0] right_width_0_height_0__pin_38_upper ; +output [0:0] right_width_0_height_0__pin_38_lower ; +output [0:0] right_width_0_height_0__pin_39_upper ; +output [0:0] right_width_0_height_0__pin_39_lower ; +output [0:0] right_width_0_height_0__pin_40_upper ; +output [0:0] right_width_0_height_0__pin_40_lower ; +output [0:0] right_width_0_height_0__pin_41_upper ; +output [0:0] right_width_0_height_0__pin_41_lower ; +output [0:0] bottom_width_0_height_0__pin_42_upper ; +output [0:0] bottom_width_0_height_0__pin_42_lower ; +output [0:0] bottom_width_0_height_0__pin_43_upper ; +output [0:0] bottom_width_0_height_0__pin_43_lower ; +output [0:0] bottom_width_0_height_0__pin_44_upper ; +output [0:0] bottom_width_0_height_0__pin_44_lower ; +output [0:0] bottom_width_0_height_0__pin_45_upper ; +output [0:0] bottom_width_0_height_0__pin_45_lower ; +output [0:0] bottom_width_0_height_0__pin_46_upper ; +output [0:0] bottom_width_0_height_0__pin_46_lower ; +output [0:0] bottom_width_0_height_0__pin_47_upper ; +output [0:0] bottom_width_0_height_0__pin_47_lower ; +output [0:0] bottom_width_0_height_0__pin_48_upper ; +output [0:0] bottom_width_0_height_0__pin_48_lower ; +output [0:0] bottom_width_0_height_0__pin_49_upper ; +output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] bottom_width_0_height_0__pin_50_ ; +output [0:0] bottom_width_0_height_0__pin_51_ ; +output [0:0] ccff_tail ; + +wire ropt_net_161 ; +wire ropt_net_160 ; +wire ropt_net_157 ; +wire ropt_net_151 ; +wire ropt_net_152 ; +wire p_abuf4 ; +wire ropt_net_148 ; +wire ropt_net_156 ; +wire ropt_net_145 ; +wire ropt_net_159 ; +wire ropt_net_165 ; +wire ropt_net_167 ; +wire ropt_net_184 ; +wire ropt_net_163 ; + +logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .clb_I0 ( { right_width_0_height_0__pin_0_[0] , + right_width_0_height_0__pin_1_[0] , + right_width_0_height_0__pin_2_[0] , + right_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { right_width_0_height_0__pin_4_[0] , + right_width_0_height_0__pin_5_[0] , + right_width_0_height_0__pin_6_[0] , + right_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { right_width_0_height_0__pin_8_[0] , + right_width_0_height_0__pin_9_[0] , + right_width_0_height_0__pin_10_[0] , + right_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { right_width_0_height_0__pin_12_[0] , + right_width_0_height_0__pin_13_[0] , + right_width_0_height_0__pin_14_[0] , + right_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , + bottom_width_0_height_0__pin_17_[0] , + bottom_width_0_height_0__pin_18_[0] , + bottom_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , + bottom_width_0_height_0__pin_21_[0] , + bottom_width_0_height_0__pin_22_[0] , + bottom_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , + bottom_width_0_height_0__pin_25_[0] , + bottom_width_0_height_0__pin_26_[0] , + bottom_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , + bottom_width_0_height_0__pin_29_[0] , + bottom_width_0_height_0__pin_30_[0] , + bottom_width_0_height_0__pin_31_[0] } ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_130_ , aps_rename_132_ , aps_rename_134_ , + aps_rename_136_ , aps_rename_138_ , + right_width_0_height_0__pin_39_upper[0] , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + aps_rename_149_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_155_ , aps_rename_157_ , aps_rename_158_ } ) , + .clb_regout ( bottom_width_0_height_0__pin_50_ ) , + .clb_scout ( bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( { ropt_net_168 } ) , + .p_abuf0 ( ropt_net_160 ) , .p_abuf1 ( ropt_net_161 ) , + .p_abuf2 ( ropt_net_151 ) , .p_abuf3 ( ropt_net_157 ) , + .p_abuf4 ( p_abuf4 ) , .p_abuf5 ( ropt_net_152 ) , + .p_abuf6 ( ropt_net_148 ) , + .p_abuf7 ( right_width_0_height_0__pin_40_upper[0] ) , + .p_abuf8 ( bottom_width_0_height_0__pin_43_upper[0] ) , + .p_abuf9 ( ropt_net_156 ) , .p_abuf10 ( ropt_net_159 ) , + .p_abuf11 ( ropt_net_145 ) , .p_abuf12 ( ropt_net_167 ) , + .p_abuf13 ( ropt_net_165 ) , .p_abuf14 ( ropt_net_163 ) , + .p_abuf15 ( ropt_net_184 ) , .p0 ( optlc_net_135 ) , + .p1 ( optlc_net_136 ) , .p2 ( optlc_net_137 ) , .p3 ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_130_ ) , + .X ( aps_rename_131_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( aps_rename_132_ ) , + .X ( aps_rename_133_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_134_ ) , + .X ( aps_rename_135_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_136_ ) , + .X ( aps_rename_137_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_138_ ) , + .X ( aps_rename_139_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_140_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_141_ ) , + .X ( aps_rename_142_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_143_ ) , + .X ( aps_rename_144_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( aps_rename_145_ ) , + .X ( aps_rename_146_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_147_ ) , + .X ( aps_rename_148_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_149_ ) , + .X ( aps_rename_150_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_153_ ) , + .X ( aps_rename_154_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_155_ ) , + .X ( aps_rename_156_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_142_ ) , + .X ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_144_ ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_148_ ) , + .X ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_156_ ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( aps_rename_159_ ) , + .X ( bottom_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( .A ( BUF_net_93 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( .A ( BUF_net_95 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( BUF_net_126 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( .A ( BUF_net_96 ) , + .X ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( BUF_net_98 ) , + .X ( bottom_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( BUF_net_99 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_129 ( .A ( BUF_net_101 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( BUF_net_102 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_963 ( .A ( ropt_net_143 ) , + .X ( bottom_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_964 ( .A ( ropt_net_144 ) , + .X ( bottom_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_965 ( .A ( ropt_net_145 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_966 ( .A ( ropt_net_146 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_967 ( .A ( ropt_net_147 ) , + .X ( right_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_968 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_969 ( .A ( ropt_net_149 ) , + .X ( bottom_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_970 ( .A ( ropt_net_150 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_971 ( .A ( ropt_net_151 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_972 ( .A ( ropt_net_152 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_973 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_36_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_974 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_975 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_976 ( .A ( ropt_net_156 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_977 ( .A ( ropt_net_157 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_978 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_979 ( .A ( ropt_net_159 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_980 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_981 ( .A ( ropt_net_161 ) , + .X ( right_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_982 ( .A ( ropt_net_162 ) , + .X ( right_width_0_height_0__pin_40_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_983 ( .A ( ropt_net_163 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_984 ( .A ( ropt_net_164 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_986 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_989 ( .A ( ropt_net_166 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_990 ( .A ( ropt_net_167 ) , + .X ( bottom_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_168 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_997 ( .A ( ropt_net_170 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_998 ( .A ( ropt_net_171 ) , + .X ( bottom_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_999 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1000 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1001 ( .A ( ropt_net_174 ) , + .X ( bottom_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1002 ( .A ( ropt_net_175 ) , + .X ( bottom_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1004 ( .A ( ropt_net_176 ) , + .X ( right_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1005 ( .A ( ropt_net_177 ) , + .X ( bottom_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1006 ( .A ( ropt_net_178 ) , + .X ( right_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1007 ( .A ( ropt_net_179 ) , + .X ( right_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1009 ( .A ( ropt_net_180 ) , + .X ( bottom_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1012 ( .A ( ropt_net_181 ) , + .X ( bottom_width_0_height_0__pin_46_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1013 ( .A ( ropt_net_182 ) , + .X ( bottom_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1015 ( .A ( ropt_net_183 ) , + .X ( right_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1016 ( .A ( ropt_net_184 ) , + .X ( bottom_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1020 ( .A ( ropt_net_185 ) , + .X ( right_width_0_height_0__pin_36_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1022 ( .A ( ropt_net_186 ) , + .X ( right_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1027 ( .A ( ropt_net_187 ) , + .X ( right_width_0_height_0__pin_41_lower[0] ) ) ; +endmodule + + +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +output [0:7] gfpga_pad_GPIO_A ; +output [0:7] gfpga_pad_GPIO_IE ; +output [0:7] gfpga_pad_GPIO_OE ; +inout [0:7] gfpga_pad_GPIO_Y ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:19] cbx_1__0__0_chanx_left_out ; +wire [0:19] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:19] cbx_1__0__1_chanx_left_out ; +wire [0:19] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:19] cbx_1__1__0_chanx_left_out ; +wire [0:19] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:19] cbx_1__1__1_chanx_left_out ; +wire [0:19] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:19] cbx_1__2__0_chanx_left_out ; +wire [0:19] cbx_1__2__0_chanx_right_out ; +wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:19] cbx_1__2__1_chanx_left_out ; +wire [0:19] cbx_1__2__1_chanx_right_out ; +wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:19] cby_0__1__0_chany_bottom_out ; +wire [0:19] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__0_right_grid_pin_52_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:19] cby_0__1__1_chany_bottom_out ; +wire [0:19] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:19] cby_1__1__0_chany_bottom_out ; +wire [0:19] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_0_ ; +wire [0:0] cby_1__1__0_left_grid_pin_10_ ; +wire [0:0] cby_1__1__0_left_grid_pin_11_ ; +wire [0:0] cby_1__1__0_left_grid_pin_12_ ; +wire [0:0] cby_1__1__0_left_grid_pin_13_ ; +wire [0:0] cby_1__1__0_left_grid_pin_14_ ; +wire [0:0] cby_1__1__0_left_grid_pin_15_ ; +wire [0:0] cby_1__1__0_left_grid_pin_1_ ; +wire [0:0] cby_1__1__0_left_grid_pin_2_ ; +wire [0:0] cby_1__1__0_left_grid_pin_3_ ; +wire [0:0] cby_1__1__0_left_grid_pin_4_ ; +wire [0:0] cby_1__1__0_left_grid_pin_5_ ; +wire [0:0] cby_1__1__0_left_grid_pin_6_ ; +wire [0:0] cby_1__1__0_left_grid_pin_7_ ; +wire [0:0] cby_1__1__0_left_grid_pin_8_ ; +wire [0:0] cby_1__1__0_left_grid_pin_9_ ; +wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:19] cby_1__1__1_chany_bottom_out ; +wire [0:19] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_0_ ; +wire [0:0] cby_1__1__1_left_grid_pin_10_ ; +wire [0:0] cby_1__1__1_left_grid_pin_11_ ; +wire [0:0] cby_1__1__1_left_grid_pin_12_ ; +wire [0:0] cby_1__1__1_left_grid_pin_13_ ; +wire [0:0] cby_1__1__1_left_grid_pin_14_ ; +wire [0:0] cby_1__1__1_left_grid_pin_15_ ; +wire [0:0] cby_1__1__1_left_grid_pin_1_ ; +wire [0:0] cby_1__1__1_left_grid_pin_2_ ; +wire [0:0] cby_1__1__1_left_grid_pin_3_ ; +wire [0:0] cby_1__1__1_left_grid_pin_4_ ; +wire [0:0] cby_1__1__1_left_grid_pin_5_ ; +wire [0:0] cby_1__1__1_left_grid_pin_6_ ; +wire [0:0] cby_1__1__1_left_grid_pin_7_ ; +wire [0:0] cby_1__1__1_left_grid_pin_8_ ; +wire [0:0] cby_1__1__1_left_grid_pin_9_ ; +wire [0:0] cby_1__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:19] cby_1__1__2_chany_bottom_out ; +wire [0:19] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_0_ ; +wire [0:0] cby_1__1__2_left_grid_pin_10_ ; +wire [0:0] cby_1__1__2_left_grid_pin_11_ ; +wire [0:0] cby_1__1__2_left_grid_pin_12_ ; +wire [0:0] cby_1__1__2_left_grid_pin_13_ ; +wire [0:0] cby_1__1__2_left_grid_pin_14_ ; +wire [0:0] cby_1__1__2_left_grid_pin_15_ ; +wire [0:0] cby_1__1__2_left_grid_pin_1_ ; +wire [0:0] cby_1__1__2_left_grid_pin_2_ ; +wire [0:0] cby_1__1__2_left_grid_pin_3_ ; +wire [0:0] cby_1__1__2_left_grid_pin_4_ ; +wire [0:0] cby_1__1__2_left_grid_pin_5_ ; +wire [0:0] cby_1__1__2_left_grid_pin_6_ ; +wire [0:0] cby_1__1__2_left_grid_pin_7_ ; +wire [0:0] cby_1__1__2_left_grid_pin_8_ ; +wire [0:0] cby_1__1__2_left_grid_pin_9_ ; +wire [0:0] cby_1__1__2_right_grid_pin_52_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:19] cby_1__1__3_chany_bottom_out ; +wire [0:19] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_0_ ; +wire [0:0] cby_1__1__3_left_grid_pin_10_ ; +wire [0:0] cby_1__1__3_left_grid_pin_11_ ; +wire [0:0] cby_1__1__3_left_grid_pin_12_ ; +wire [0:0] cby_1__1__3_left_grid_pin_13_ ; +wire [0:0] cby_1__1__3_left_grid_pin_14_ ; +wire [0:0] cby_1__1__3_left_grid_pin_15_ ; +wire [0:0] cby_1__1__3_left_grid_pin_1_ ; +wire [0:0] cby_1__1__3_left_grid_pin_2_ ; +wire [0:0] cby_1__1__3_left_grid_pin_3_ ; +wire [0:0] cby_1__1__3_left_grid_pin_4_ ; +wire [0:0] cby_1__1__3_left_grid_pin_5_ ; +wire [0:0] cby_1__1__3_left_grid_pin_6_ ; +wire [0:0] cby_1__1__3_left_grid_pin_7_ ; +wire [0:0] cby_1__1__3_left_grid_pin_8_ ; +wire [0:0] cby_1__1__3_left_grid_pin_9_ ; +wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:19] sb_0__0__0_chanx_right_out ; +wire [0:19] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:19] sb_0__1__0_chanx_right_out ; +wire [0:19] sb_0__1__0_chany_bottom_out ; +wire [0:19] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__2__0_ccff_tail ; +wire [0:19] sb_0__2__0_chanx_right_out ; +wire [0:19] sb_0__2__0_chany_bottom_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:19] sb_1__0__0_chanx_left_out ; +wire [0:19] sb_1__0__0_chanx_right_out ; +wire [0:19] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:19] sb_1__1__0_chanx_left_out ; +wire [0:19] sb_1__1__0_chanx_right_out ; +wire [0:19] sb_1__1__0_chany_bottom_out ; +wire [0:19] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__2__0_ccff_tail ; +wire [0:19] sb_1__2__0_chanx_left_out ; +wire [0:19] sb_1__2__0_chanx_right_out ; +wire [0:19] sb_1__2__0_chany_bottom_out ; +wire [0:0] sb_2__0__0_ccff_tail ; +wire [0:19] sb_2__0__0_chanx_left_out ; +wire [0:19] sb_2__0__0_chany_top_out ; +wire [0:0] sb_2__1__0_ccff_tail ; +wire [0:19] sb_2__1__0_chanx_left_out ; +wire [0:19] sb_2__1__0_chany_bottom_out ; +wire [0:19] sb_2__1__0_chany_top_out ; +wire [0:0] sb_2__2__0_ccff_tail ; +wire [0:19] sb_2__2__0_chanx_left_out ; +wire [0:19] sb_2__2__0_chany_bottom_out ; +// + +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1827 } ) , + .Test_en ( { BUF_net_9 } ) , + .clk ( clk ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_33 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_40 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_1_ccff_tail ) ) ; +grid_clb grid_clb_2__1_ ( + .prog_clk ( { ctsbuf_net_413 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_2_ccff_tail ) ) ; +grid_clb grid_clb_2__2_ ( + .prog_clk ( { ctsbuf_net_615 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_3_ccff_tail ) ) ; +grid_io_top grid_io_top_1__3_ ( + .prog_clk ( { ctsbuf_net_918 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__0_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) ) ; +grid_io_top grid_io_top_2__3_ ( + .prog_clk ( { ctsbuf_net_514 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__1_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) ) ; +grid_io_right grid_io_right_3__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) ) ; +grid_io_right grid_io_right_3__2_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) ) ; +grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__0_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) ) ; +grid_io_bottom grid_io_bottom_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__1_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) ) ; +grid_io_left grid_io_left_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__0_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) ) ; +grid_io_left grid_io_left_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__1_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) ) ; +sb_0__1_ sb_0__1_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; +sb_0__2_ sb_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( { ropt_net_38 } ) , + .chanx_right_out ( sb_0__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , + .ccff_tail ( sb_0__2__0_ccff_tail ) ) ; +sb_1__0_ sb_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_1423 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; +sb_1__2_ sb_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( { ropt_net_36 } ) , + .chanx_right_out ( sb_1__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__2__0_chanx_left_out ) , + .ccff_tail ( sb_1__2__0_ccff_tail ) ) ; +sb_2__0_ sb_2__0_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_2__0__0_chany_top_out ) , + .chanx_left_out ( sb_2__0__0_chanx_left_out ) , + .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; +sb_2__1_ sb_2__1_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_2__1__0_chany_top_out ) , + .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__1__0_chanx_left_out ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; +sb_2__2_ sb_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__2__0_chanx_left_out ) , + .ccff_tail ( sb_2__2__0_ccff_tail ) ) ; +cbx_1__0_ cbx_1__0_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__0_ccff_tail ) ) ; +cbx_1__0_ cbx_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_2__0__0_chanx_left_out ) , + .ccff_head ( sb_2__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__1_ccff_tail ) ) ; +cbx_1__1_ cbx_1__1_ ( + .prog_clk ( { ctsbuf_net_1726 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) ) ; +cbx_1__1_ cbx_2__1_ ( + .prog_clk ( { ctsbuf_net_1120 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_2__1__0_chanx_left_out ) , + .ccff_head ( sb_2__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) ) ; +cbx_1__2_ cbx_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .chanx_left_in ( sb_0__2__0_chanx_right_out ) , + .chanx_right_in ( sb_1__2__0_chanx_left_out ) , + .ccff_head ( sb_1__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__0_ccff_tail ) ) ; +cbx_1__2_ cbx_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chanx_left_in ( sb_1__2__0_chanx_right_out ) , + .chanx_right_in ( sb_2__2__0_chanx_left_out ) , + .ccff_head ( sb_2__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__1_ccff_tail ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__0_ccff_tail ) ) ; +cby_0__1_ cby_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__2__0_chany_bottom_out ) , + .ccff_head ( sb_0__2__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__1_ccff_tail ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; +cby_1__1_ cby_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; +cby_1__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_bottom_in ( sb_2__0__0_chany_top_out ) , + .chany_top_in ( sb_2__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) ) ; +cby_1__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( sb_2__1__0_chany_top_out ) , + .chany_top_in ( sb_2__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) ) ; +direct_interc_0 direct_interc_0_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_0_out ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_1_out ) ) ; +direct_interc_2 direct_interc_2_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_2_out ) ) ; +direct_interc_3 direct_interc_3_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_3_out ) ) ; +direct_interc_4 direct_interc_4_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_4_out ) ) ; +direct_interc_5 direct_interc_5_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_5_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7749 ( + .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_31 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7750 ( .A ( ropt_net_31 ) , + .X ( ropt_net_32 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7751 ( .A ( ropt_net_32 ) , + .X ( ropt_net_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_9 ( .A ( Test_en[0] ) , + .X ( BUF_net_9 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7752 ( + .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_34 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73507625 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_110 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73517626 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_211 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73527627 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_312 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73537628 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_413 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73547629 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_514 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73557630 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_615 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73567631 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_716 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73577632 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_817 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73587633 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_918 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73597634 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1019 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7753 ( .A ( ropt_net_34 ) , + .X ( ropt_net_35 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73617636 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1221 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73627637 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1322 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7754 ( .A ( ropt_net_35 ) , + .X ( ropt_net_36 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73647639 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1524 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73657640 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1625 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7755 ( + .A ( grid_io_top_0_ccff_tail[0] ) , .X ( ropt_net_37 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73677642 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1827 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_73667641_73687643 ( + .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) ) ; +sky130_fd_sc_hd__bufinv_16 cts_inv_73607635_73697644 ( + .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( SYNOPSYS_UNCONNECTED_4 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7756 ( .A ( ropt_net_37 ) , + .X ( ropt_net_38 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73827657 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1928 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73837658 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2029 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73847659 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7757 ( + .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_39 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7758 ( .A ( ropt_net_39 ) , + .X ( ropt_net_40 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds new file mode 100644 index 0000000..687a129 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:358640051a76fbac401181226ce7e5a3f0efb79632b5cdae23fc7380e48cd187 +size 15460352 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef new file mode 100644 index 0000000..f844858 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef @@ -0,0 +1,363 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v new file mode 100644 index 0000000..e4cdab6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v @@ -0,0 +1,289543 @@ +// +// +// +// +// +// +module direct_interc_5 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module direct_interc_4 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module direct_interc_3 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module direct_interc_2 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module direct_interc_1 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module direct_interc_0 ( in , out , VDD , VSS ) ; +input [0:0] in ; +output [0:0] out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x96600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x59800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x64400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail , VDD , + VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x947600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x929200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x938400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x105800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x947600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x64400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x874000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x59800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x105800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size10_11 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_8 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x64400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x64400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6_8 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_9 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_21 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_7 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_8 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4_7 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x993600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1366200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1094800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1311000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1347800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1384600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1131600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1214400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1223600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1366200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1131600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1209800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1320200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1311000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1081000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1219000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1237400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1311000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1117800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1311000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1366200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1274200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1292600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1301800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1311000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1347800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1384600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1228200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1246600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1357000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1393800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1076400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1315600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1209800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1320200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1163800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1182200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1094800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1113200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1343200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1380000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1315600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1150000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1297200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1315600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1297200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1297200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1334000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1370800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x998200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1030400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1366200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1209800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1357000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1393800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1315600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1297200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1214400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1320200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x998200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1242000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1311000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1315600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1168400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1186800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1306400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1177600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1186800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1306400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x993600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1306400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x975200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x993600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1076400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1292600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1251200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1260400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1186800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1196000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x938400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1094800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1159200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1246600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1232800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1370800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1177600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1274200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1292600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1265000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1159200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1136200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1265000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1274200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1366200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1403000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1145400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1191400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1200600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1191400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1209800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1324800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1334000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1370800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1131600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1219000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1357000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1393800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x929200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_6 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_7 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1343200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1380000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1232800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1242000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1315600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1196000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1269600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1269600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1113200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1242000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1260400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1288000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1306400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1315600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1163800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1182200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1228200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1237400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1343200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1209800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1288000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1306400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1297200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1334000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1163800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1269600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1329400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1228200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1288000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1306400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1246600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1094800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1214400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1136200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1338600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1076400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1209800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1274200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1292600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1173000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1232800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1278800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1076400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1131600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1251200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1237400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1048800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1076400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1306400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1343200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1380000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x998200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_1 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_aps_2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_11 ( .A ( net_aps_2 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module GPIO_3 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; +input VDD ; +input VSS ; + +wire aps_rename_1_ ; +supply1 VDD ; +supply0 VSS ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] GPIO_0_en ; +supply1 VDD ; +supply0 VSS ; + +GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , + ccff_head , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_14 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( right_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_15 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_8 ( .A ( aps_rename_2_ ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_14 ) , + .X ( gfpga_pad_GPIO_IE[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x46000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module GPIO_2 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; +input VDD ; +input VSS ; + +wire aps_rename_1_ ; +supply1 VDD ; +supply0 VSS ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , .X ( IE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] GPIO_0_en ; +supply1 VDD ; +supply0 VSS ; + +GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , + ccff_head , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( top_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_17 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( BUF_net_6 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_581 ( .A ( ropt_net_19 ) , + .X ( gfpga_pad_GPIO_IE[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_579 ( .A ( ropt_net_16 ) , + .X ( ropt_net_19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_580 ( .A ( ropt_net_17 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_2!x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module GPIO_1 ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; +input VDD ; +input VSS ; + +wire aps_rename_1_ ; +supply1 VDD ; +supply0 VSS ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_8 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_11 ( .A ( BUF_net_8 ) , .X ( IE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] GPIO_0_en ; +supply1 VDD ; +supply0 VSS ; + +GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , + ccff_head , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] left_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_13 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_9 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_12 ) , + .X ( ropt_net_15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_13 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_net_7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_7 ( .A ( net_net_7 ) , + .X ( net_net_6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_10 ( .A ( net_net_6 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module GPIO ( A , IE , OE , Y , in , out , mem_out , VDD , VSS ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; +input VDD ; +input VSS ; + +wire aps_rename_1_ ; +supply1 VDD ; +supply0 VSS ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( BUF_net_9 ) , .X ( IE ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] GPIO_0_en ; +supply1 VDD ; +supply0 VSS ; + +GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , + ccff_head , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( ccff_head ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_14 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( BUF_net_5 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_14 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS , p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; +output p_abuf1 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( p_abuf1 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_108 ( .A ( p_abuf1 ) , + .X ( net_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_133 ( .A ( net_net_133 ) , + .X ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign p_abuf0 = p_abuf1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf1 ( p_abuf1 ) ) ; +mux_tree_size2_21 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_22 mux_fabric_out_1 ( + .in ( { p_abuf1 , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_23 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__269 ( .A ( fabric_scout[0] ) , + .X ( fabric_regout[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__46 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_18 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_19 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_20 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__41 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_29 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_15 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_16 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_17 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_28 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_12 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_13 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_14 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_26 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_6 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_7 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_8 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_25 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_25 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p0 , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_3 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_4 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +mux_tree_size2_5 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p0 , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; +input p1 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , + .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , + VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , VDD , + VSS , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_0 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_1 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_2 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , VDD , VSS , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; + +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , + clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , + clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , + p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , + p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] clb_I0 ; +input [0:3] clb_I1 ; +input [0:3] clb_I2 ; +input [0:3] clb_I3 ; +input [0:3] clb_I4 ; +input [0:3] clb_I5 ; +input [0:3] clb_I6 ; +input [0:3] clb_I7 ; +input [0:0] clb_regin ; +input [0:0] clb_scin ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_regout ; +output [0:0] clb_scout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_2_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I1 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I2 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { p_abuf4 , logical_tile_clb_mode_default__fle_2_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I3 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , logical_tile_clb_mode_default__fle_3_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p3 ) ) ; +logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I4 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I5 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I6 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I7 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , .p2 ( p3 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( clb_O[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( clb_O[2] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( clb_O[3] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_out ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf4 } ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( clb_O[7] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( clb_O[9] ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( clb_O[10] ) ) ; +direct_interc direct_interc_11_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; +direct_interc direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( clb_O[12] ) ) ; +direct_interc direct_interc_13_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; +direct_interc direct_interc_14_ ( + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .out ( clb_O[14] ) ) ; +direct_interc direct_interc_15_ ( + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , + .out ( clb_O[15] ) ) ; +direct_interc direct_interc_16_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , + .out ( { p_abuf16 } ) ) ; +direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , + .out ( { p_abuf17 } ) ) ; +direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , + .out ( clb_I0[0] ) ) ; +direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .out ( clb_I0[1] ) ) ; +direct_interc direct_interc_20_ ( + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , + .out ( clb_I0[2] ) ) ; +direct_interc direct_interc_21_ ( + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .out ( clb_I0[3] ) ) ; +direct_interc direct_interc_22_ ( + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , + .out ( clb_regin ) ) ; +direct_interc direct_interc_23_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , + .out ( clb_scin ) ) ; +direct_interc direct_interc_24_ ( + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_25_ ( + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , + .out ( clb_I1[0] ) ) ; +direct_interc direct_interc_26_ ( + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I1[1] ) ) ; +direct_interc direct_interc_27_ ( + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , + .out ( clb_I1[2] ) ) ; +direct_interc direct_interc_28_ ( + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .out ( clb_I1[3] ) ) ; +direct_interc direct_interc_29_ ( + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; +direct_interc direct_interc_30_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; +direct_interc direct_interc_31_ ( + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_32_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , + .out ( clb_I2[0] ) ) ; +direct_interc direct_interc_33_ ( + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I2[1] ) ) ; +direct_interc direct_interc_34_ ( + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , + .out ( clb_I2[2] ) ) ; +direct_interc direct_interc_35_ ( + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .out ( clb_I2[3] ) ) ; +direct_interc direct_interc_36_ ( + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; +direct_interc direct_interc_37_ ( + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; +direct_interc direct_interc_38_ ( + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_39_ ( + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , + .out ( clb_I3[0] ) ) ; +direct_interc direct_interc_40_ ( + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I3[1] ) ) ; +direct_interc direct_interc_41_ ( + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , + .out ( clb_I3[2] ) ) ; +direct_interc direct_interc_42_ ( + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .out ( clb_I3[3] ) ) ; +direct_interc direct_interc_43_ ( + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; +direct_interc direct_interc_44_ ( + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; +direct_interc direct_interc_45_ ( + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_46_ ( + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , + .out ( clb_I4[0] ) ) ; +direct_interc direct_interc_47_ ( + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I4[1] ) ) ; +direct_interc direct_interc_48_ ( + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , + .out ( clb_I4[2] ) ) ; +direct_interc direct_interc_49_ ( + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .out ( clb_I4[3] ) ) ; +direct_interc direct_interc_50_ ( + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; +direct_interc direct_interc_51_ ( + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; +direct_interc direct_interc_52_ ( + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_53_ ( + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , + .out ( clb_I5[0] ) ) ; +direct_interc direct_interc_54_ ( + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I5[1] ) ) ; +direct_interc direct_interc_55_ ( + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .out ( clb_I5[2] ) ) ; +direct_interc direct_interc_56_ ( + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .out ( clb_I5[3] ) ) ; +direct_interc direct_interc_57_ ( + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; +direct_interc direct_interc_58_ ( + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; +direct_interc direct_interc_59_ ( + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , + .out ( clb_I6[0] ) ) ; +direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I6[1] ) ) ; +direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , + .out ( clb_I6[2] ) ) ; +direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .out ( clb_I6[3] ) ) ; +direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; +direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; +direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , + .out ( clb_I7[0] ) ) ; +direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_69 } ) , + .out ( clb_I7[1] ) ) ; +direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_70 } ) , + .out ( clb_I7[2] ) ) ; +direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_71 } ) , + .out ( clb_I7[3] ) ) ; +direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_72 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; +direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_73 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; +direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .out ( clb_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( clb_O[1] ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , + .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( .A ( p_abuf4 ) , + .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( clb_O[2] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , .X ( clb_O[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( clb_O[7] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , + .X ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( clb_O[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( clb_O[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_62 ) , + .X ( p_abuf2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_83 ( .A ( clb_O[12] ) , + .X ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( clb_O[15] ) , + .X ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , + .X ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_64 ) , + .X ( p_abuf3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_67 ) , + .X ( p_abuf5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_106 ( .A ( BUF_net_69 ) , + .X ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( BUF_net_58 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( clb_O[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_71 ) , + .X ( p_abuf7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_73 ) , + .X ( p_abuf8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_75 ) , + .X ( p_abuf9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( .A ( BUF_net_77 ) , + .X ( p_abuf10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_118 ( .A ( BUF_net_79 ) , + .X ( p_abuf11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( BUF_net_81 ) , + .X ( p_abuf12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_83 ) , + .X ( p_abuf13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( BUF_net_85 ) , + .X ( p_abuf14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_87 ) , + .X ( p_abuf15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( BUF_net_106 ) , + .X ( p_abuf6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , + right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , + right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , + right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , + right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , + right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , + right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , + right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , + bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , + bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , + bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , + bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , + bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , + bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , + bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , + bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , right_width_0_height_0__pin_34_upper , + right_width_0_height_0__pin_34_lower , + right_width_0_height_0__pin_35_upper , + right_width_0_height_0__pin_35_lower , + right_width_0_height_0__pin_36_upper , + right_width_0_height_0__pin_36_lower , + right_width_0_height_0__pin_37_upper , + right_width_0_height_0__pin_37_lower , + right_width_0_height_0__pin_38_upper , + right_width_0_height_0__pin_38_lower , + right_width_0_height_0__pin_39_upper , + right_width_0_height_0__pin_39_lower , + right_width_0_height_0__pin_40_upper , + right_width_0_height_0__pin_40_lower , + right_width_0_height_0__pin_41_upper , + right_width_0_height_0__pin_41_lower , + bottom_width_0_height_0__pin_42_upper , + bottom_width_0_height_0__pin_42_lower , + bottom_width_0_height_0__pin_43_upper , + bottom_width_0_height_0__pin_43_lower , + bottom_width_0_height_0__pin_44_upper , + bottom_width_0_height_0__pin_44_lower , + bottom_width_0_height_0__pin_45_upper , + bottom_width_0_height_0__pin_45_lower , + bottom_width_0_height_0__pin_46_upper , + bottom_width_0_height_0__pin_46_lower , + bottom_width_0_height_0__pin_47_upper , + bottom_width_0_height_0__pin_47_lower , + bottom_width_0_height_0__pin_48_upper , + bottom_width_0_height_0__pin_48_lower , + bottom_width_0_height_0__pin_49_upper , + bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] right_width_0_height_0__pin_1_ ; +input [0:0] right_width_0_height_0__pin_2_ ; +input [0:0] right_width_0_height_0__pin_3_ ; +input [0:0] right_width_0_height_0__pin_4_ ; +input [0:0] right_width_0_height_0__pin_5_ ; +input [0:0] right_width_0_height_0__pin_6_ ; +input [0:0] right_width_0_height_0__pin_7_ ; +input [0:0] right_width_0_height_0__pin_8_ ; +input [0:0] right_width_0_height_0__pin_9_ ; +input [0:0] right_width_0_height_0__pin_10_ ; +input [0:0] right_width_0_height_0__pin_11_ ; +input [0:0] right_width_0_height_0__pin_12_ ; +input [0:0] right_width_0_height_0__pin_13_ ; +input [0:0] right_width_0_height_0__pin_14_ ; +input [0:0] right_width_0_height_0__pin_15_ ; +input [0:0] bottom_width_0_height_0__pin_16_ ; +input [0:0] bottom_width_0_height_0__pin_17_ ; +input [0:0] bottom_width_0_height_0__pin_18_ ; +input [0:0] bottom_width_0_height_0__pin_19_ ; +input [0:0] bottom_width_0_height_0__pin_20_ ; +input [0:0] bottom_width_0_height_0__pin_21_ ; +input [0:0] bottom_width_0_height_0__pin_22_ ; +input [0:0] bottom_width_0_height_0__pin_23_ ; +input [0:0] bottom_width_0_height_0__pin_24_ ; +input [0:0] bottom_width_0_height_0__pin_25_ ; +input [0:0] bottom_width_0_height_0__pin_26_ ; +input [0:0] bottom_width_0_height_0__pin_27_ ; +input [0:0] bottom_width_0_height_0__pin_28_ ; +input [0:0] bottom_width_0_height_0__pin_29_ ; +input [0:0] bottom_width_0_height_0__pin_30_ ; +input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] left_width_0_height_0__pin_52_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_34_upper ; +output [0:0] right_width_0_height_0__pin_34_lower ; +output [0:0] right_width_0_height_0__pin_35_upper ; +output [0:0] right_width_0_height_0__pin_35_lower ; +output [0:0] right_width_0_height_0__pin_36_upper ; +output [0:0] right_width_0_height_0__pin_36_lower ; +output [0:0] right_width_0_height_0__pin_37_upper ; +output [0:0] right_width_0_height_0__pin_37_lower ; +output [0:0] right_width_0_height_0__pin_38_upper ; +output [0:0] right_width_0_height_0__pin_38_lower ; +output [0:0] right_width_0_height_0__pin_39_upper ; +output [0:0] right_width_0_height_0__pin_39_lower ; +output [0:0] right_width_0_height_0__pin_40_upper ; +output [0:0] right_width_0_height_0__pin_40_lower ; +output [0:0] right_width_0_height_0__pin_41_upper ; +output [0:0] right_width_0_height_0__pin_41_lower ; +output [0:0] bottom_width_0_height_0__pin_42_upper ; +output [0:0] bottom_width_0_height_0__pin_42_lower ; +output [0:0] bottom_width_0_height_0__pin_43_upper ; +output [0:0] bottom_width_0_height_0__pin_43_lower ; +output [0:0] bottom_width_0_height_0__pin_44_upper ; +output [0:0] bottom_width_0_height_0__pin_44_lower ; +output [0:0] bottom_width_0_height_0__pin_45_upper ; +output [0:0] bottom_width_0_height_0__pin_45_lower ; +output [0:0] bottom_width_0_height_0__pin_46_upper ; +output [0:0] bottom_width_0_height_0__pin_46_lower ; +output [0:0] bottom_width_0_height_0__pin_47_upper ; +output [0:0] bottom_width_0_height_0__pin_47_lower ; +output [0:0] bottom_width_0_height_0__pin_48_upper ; +output [0:0] bottom_width_0_height_0__pin_48_lower ; +output [0:0] bottom_width_0_height_0__pin_49_upper ; +output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] bottom_width_0_height_0__pin_50_ ; +output [0:0] bottom_width_0_height_0__pin_51_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire ropt_net_161 ; +wire ropt_net_160 ; +wire ropt_net_157 ; +wire ropt_net_151 ; +wire ropt_net_152 ; +wire p_abuf4 ; +wire ropt_net_148 ; +wire ropt_net_156 ; +wire ropt_net_145 ; +wire ropt_net_159 ; +wire ropt_net_165 ; +wire ropt_net_167 ; +wire ropt_net_184 ; +wire ropt_net_163 ; +supply1 VDD ; +supply0 VSS ; + +logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .clb_I0 ( { right_width_0_height_0__pin_0_[0] , + right_width_0_height_0__pin_1_[0] , + right_width_0_height_0__pin_2_[0] , + right_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { right_width_0_height_0__pin_4_[0] , + right_width_0_height_0__pin_5_[0] , + right_width_0_height_0__pin_6_[0] , + right_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { right_width_0_height_0__pin_8_[0] , + right_width_0_height_0__pin_9_[0] , + right_width_0_height_0__pin_10_[0] , + right_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { right_width_0_height_0__pin_12_[0] , + right_width_0_height_0__pin_13_[0] , + right_width_0_height_0__pin_14_[0] , + right_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , + bottom_width_0_height_0__pin_17_[0] , + bottom_width_0_height_0__pin_18_[0] , + bottom_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , + bottom_width_0_height_0__pin_21_[0] , + bottom_width_0_height_0__pin_22_[0] , + bottom_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , + bottom_width_0_height_0__pin_25_[0] , + bottom_width_0_height_0__pin_26_[0] , + bottom_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , + bottom_width_0_height_0__pin_29_[0] , + bottom_width_0_height_0__pin_30_[0] , + bottom_width_0_height_0__pin_31_[0] } ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_130_ , aps_rename_132_ , aps_rename_134_ , + aps_rename_136_ , aps_rename_138_ , + right_width_0_height_0__pin_39_upper[0] , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + aps_rename_149_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_155_ , aps_rename_157_ , aps_rename_158_ } ) , + .clb_regout ( bottom_width_0_height_0__pin_50_ ) , + .clb_scout ( bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_160 ) , + .p_abuf1 ( ropt_net_161 ) , .p_abuf2 ( ropt_net_151 ) , + .p_abuf3 ( ropt_net_157 ) , .p_abuf4 ( p_abuf4 ) , + .p_abuf5 ( ropt_net_152 ) , .p_abuf6 ( ropt_net_148 ) , + .p_abuf7 ( right_width_0_height_0__pin_40_upper[0] ) , + .p_abuf8 ( bottom_width_0_height_0__pin_43_upper[0] ) , + .p_abuf9 ( ropt_net_156 ) , .p_abuf10 ( ropt_net_159 ) , + .p_abuf11 ( ropt_net_145 ) , .p_abuf12 ( ropt_net_167 ) , + .p_abuf13 ( ropt_net_165 ) , .p_abuf14 ( ropt_net_163 ) , + .p_abuf15 ( ropt_net_184 ) , .p0 ( optlc_net_135 ) , + .p1 ( optlc_net_136 ) , .p2 ( optlc_net_137 ) , .p3 ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_130_ ) , + .X ( aps_rename_131_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( aps_rename_132_ ) , + .X ( aps_rename_133_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_134_ ) , + .X ( aps_rename_135_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_136_ ) , + .X ( aps_rename_137_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_138_ ) , + .X ( aps_rename_139_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_140_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_141_ ) , + .X ( aps_rename_142_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_143_ ) , + .X ( aps_rename_144_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( aps_rename_145_ ) , + .X ( aps_rename_146_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_147_ ) , + .X ( aps_rename_148_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_149_ ) , + .X ( aps_rename_150_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_153_ ) , + .X ( aps_rename_154_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_155_ ) , + .X ( aps_rename_156_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_142_ ) , + .X ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_144_ ) , + .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_148_ ) , + .X ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_156_ ) , + .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( aps_rename_159_ ) , + .X ( bottom_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( .A ( BUF_net_93 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( .A ( BUF_net_95 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( BUF_net_126 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( .A ( BUF_net_96 ) , + .X ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( BUF_net_98 ) , + .X ( bottom_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( BUF_net_99 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_129 ( .A ( BUF_net_101 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( BUF_net_102 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_963 ( .A ( ropt_net_143 ) , + .X ( bottom_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_964 ( .A ( ropt_net_144 ) , + .X ( bottom_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_965 ( .A ( ropt_net_145 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_966 ( .A ( ropt_net_146 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_967 ( .A ( ropt_net_147 ) , + .X ( right_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_968 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_969 ( .A ( ropt_net_149 ) , + .X ( bottom_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_970 ( .A ( ropt_net_150 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_971 ( .A ( ropt_net_151 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_972 ( .A ( ropt_net_152 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_973 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_36_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_974 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_975 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_976 ( .A ( ropt_net_156 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_977 ( .A ( ropt_net_157 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_978 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_979 ( .A ( ropt_net_159 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_980 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_981 ( .A ( ropt_net_161 ) , + .X ( right_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_982 ( .A ( ropt_net_162 ) , + .X ( right_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_983 ( .A ( ropt_net_163 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_984 ( .A ( ropt_net_164 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_986 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_989 ( .A ( ropt_net_166 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_990 ( .A ( ropt_net_167 ) , + .X ( bottom_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_168 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_997 ( .A ( ropt_net_170 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_998 ( .A ( ropt_net_171 ) , + .X ( bottom_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_999 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1000 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1001 ( .A ( ropt_net_174 ) , + .X ( bottom_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1002 ( .A ( ropt_net_175 ) , + .X ( bottom_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1004 ( .A ( ropt_net_176 ) , + .X ( right_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1005 ( .A ( ropt_net_177 ) , + .X ( bottom_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1006 ( .A ( ropt_net_178 ) , + .X ( right_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1007 ( .A ( ropt_net_179 ) , + .X ( right_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1009 ( .A ( ropt_net_180 ) , + .X ( bottom_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1012 ( .A ( ropt_net_181 ) , + .X ( bottom_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1013 ( .A ( ropt_net_182 ) , + .X ( bottom_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1015 ( .A ( ropt_net_183 ) , + .X ( right_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1016 ( .A ( ropt_net_184 ) , + .X ( bottom_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1020 ( .A ( ropt_net_185 ) , + .X ( right_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1022 ( .A ( ropt_net_186 ) , + .X ( right_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1027 ( .A ( ropt_net_187 ) , + .X ( right_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1398400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1435200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1472000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1508800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1076400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1182200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x59800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1315600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1412200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1071800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1366200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1177600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1301800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1081000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1090200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1200600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1278800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1370800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1380000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1472000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1508800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1173000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1315600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1389200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1444400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1495000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1513400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1242000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1416800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1513400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1044200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1186800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1357000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1407600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1453600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1472000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1104000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1191400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1200600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1278800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1315600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1389200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1407600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1430600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1467400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1476600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1159200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1550200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1200600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1292600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1329400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1389200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1435200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1472000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1531800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1550200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1122400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1214400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1223600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1389200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1444400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1536400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1242000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1278800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1297200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1306400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1398400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1481200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1518000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1536400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1186800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1196000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1361600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1412200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1421400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1513400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1550200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1136200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1182200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1430600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1209800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1283400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1357000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1375400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1416800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1462800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1499600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1573200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1154600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1163800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1255800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1274200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1370800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1407600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1099400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1200600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1297200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1315600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1361600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1370800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1416800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1426000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1467400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1573200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1186800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1274200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1292600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1338600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1357000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1490400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1527200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1536400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1577800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1168400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1242000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1545600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1564000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1573200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1177600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1269600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1278800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1320200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1357000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1416800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1426000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1209800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1219000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1265000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1393800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1444400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1485800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1495000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1541000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1587000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1605400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1117800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1136200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1269600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1306400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1398400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1435200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1481200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1518000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1554800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1292600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1311000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1320200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1435200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1472000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1481200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1522600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1541000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1343200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1380000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1389200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1568600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1159200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1251200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1260400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1352400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1444400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1481200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1518000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1536400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1237400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1274200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1347800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1444400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1545600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1564000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1573200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1214400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1306400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1384600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1462800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1481200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1490400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1531800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1131600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1223600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1260400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1297200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1453600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1559400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1596200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1030400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1122400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1352400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1389200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1439800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1476600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1527200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1545600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1104000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1223600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1301800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1398400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1435200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1495000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1531800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1550200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1094800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1182200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1191400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1435200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1472000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1490400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1577800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1297200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1375400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1412200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1462800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1554800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1587000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1605400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1012000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1315600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1495000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1260400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1278800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1288000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1306400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1315600y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1334000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1370800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1462800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1518000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1564000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1600800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1389200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1444400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1246600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1283400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1334000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1370800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1462800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1499600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1518000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1568600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1605400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1324800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1334000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1536400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1573200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1260400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1269600y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1311000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1403000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1421400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1467400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1476600y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1334000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1370800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1407600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1444400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1462800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1504200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1541000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1559400y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1577800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1191400y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1232800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1269600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1288000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1311000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1150000y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1191400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1334000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1370800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1380000y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1426000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1462800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1499600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1508800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1587000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1605400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x975200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1283400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1301800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1398400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1113200y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1196000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1228200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1324800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1343200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1352400y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1393800y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1476600y1278400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1518000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1536400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1228200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1265000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1301800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1320200y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1366200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1375400y1305600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1508800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y1332800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1196000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1214400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1421400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1458200y1332800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1550200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1587000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1605400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1614600y1332800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1223600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1242000y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1361600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1370800y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1416800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1453600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1462800y1360000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y1387200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1255800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1292600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1499600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1536400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1200600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1237400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1255800y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1301800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1444400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1453600y1414400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y1441600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1329400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1366200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1384600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1393800y1441600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1407600y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1453600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1490400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1508800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1518000y1468800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y1496000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1421400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1191400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1209800y1523200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1301800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1338600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1375400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1324800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1334000y1550400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1426000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1444400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1398400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1435200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1453600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1591600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1610000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1214400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1251200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1288000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1324800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1361600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1398400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1435200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1472000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1508800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1545600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1582400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +output [0:7] gfpga_pad_GPIO_A ; +output [0:7] gfpga_pad_GPIO_IE ; +output [0:7] gfpga_pad_GPIO_OE ; +inout [0:7] gfpga_pad_GPIO_Y ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:19] cbx_1__0__0_chanx_left_out ; +wire [0:19] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:19] cbx_1__0__1_chanx_left_out ; +wire [0:19] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:19] cbx_1__1__0_chanx_left_out ; +wire [0:19] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:19] cbx_1__1__1_chanx_left_out ; +wire [0:19] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:19] cbx_1__2__0_chanx_left_out ; +wire [0:19] cbx_1__2__0_chanx_right_out ; +wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:19] cbx_1__2__1_chanx_left_out ; +wire [0:19] cbx_1__2__1_chanx_right_out ; +wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:19] cby_0__1__0_chany_bottom_out ; +wire [0:19] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__0_right_grid_pin_52_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:19] cby_0__1__1_chany_bottom_out ; +wire [0:19] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:19] cby_1__1__0_chany_bottom_out ; +wire [0:19] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_0_ ; +wire [0:0] cby_1__1__0_left_grid_pin_10_ ; +wire [0:0] cby_1__1__0_left_grid_pin_11_ ; +wire [0:0] cby_1__1__0_left_grid_pin_12_ ; +wire [0:0] cby_1__1__0_left_grid_pin_13_ ; +wire [0:0] cby_1__1__0_left_grid_pin_14_ ; +wire [0:0] cby_1__1__0_left_grid_pin_15_ ; +wire [0:0] cby_1__1__0_left_grid_pin_1_ ; +wire [0:0] cby_1__1__0_left_grid_pin_2_ ; +wire [0:0] cby_1__1__0_left_grid_pin_3_ ; +wire [0:0] cby_1__1__0_left_grid_pin_4_ ; +wire [0:0] cby_1__1__0_left_grid_pin_5_ ; +wire [0:0] cby_1__1__0_left_grid_pin_6_ ; +wire [0:0] cby_1__1__0_left_grid_pin_7_ ; +wire [0:0] cby_1__1__0_left_grid_pin_8_ ; +wire [0:0] cby_1__1__0_left_grid_pin_9_ ; +wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:19] cby_1__1__1_chany_bottom_out ; +wire [0:19] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_0_ ; +wire [0:0] cby_1__1__1_left_grid_pin_10_ ; +wire [0:0] cby_1__1__1_left_grid_pin_11_ ; +wire [0:0] cby_1__1__1_left_grid_pin_12_ ; +wire [0:0] cby_1__1__1_left_grid_pin_13_ ; +wire [0:0] cby_1__1__1_left_grid_pin_14_ ; +wire [0:0] cby_1__1__1_left_grid_pin_15_ ; +wire [0:0] cby_1__1__1_left_grid_pin_1_ ; +wire [0:0] cby_1__1__1_left_grid_pin_2_ ; +wire [0:0] cby_1__1__1_left_grid_pin_3_ ; +wire [0:0] cby_1__1__1_left_grid_pin_4_ ; +wire [0:0] cby_1__1__1_left_grid_pin_5_ ; +wire [0:0] cby_1__1__1_left_grid_pin_6_ ; +wire [0:0] cby_1__1__1_left_grid_pin_7_ ; +wire [0:0] cby_1__1__1_left_grid_pin_8_ ; +wire [0:0] cby_1__1__1_left_grid_pin_9_ ; +wire [0:0] cby_1__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:19] cby_1__1__2_chany_bottom_out ; +wire [0:19] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_0_ ; +wire [0:0] cby_1__1__2_left_grid_pin_10_ ; +wire [0:0] cby_1__1__2_left_grid_pin_11_ ; +wire [0:0] cby_1__1__2_left_grid_pin_12_ ; +wire [0:0] cby_1__1__2_left_grid_pin_13_ ; +wire [0:0] cby_1__1__2_left_grid_pin_14_ ; +wire [0:0] cby_1__1__2_left_grid_pin_15_ ; +wire [0:0] cby_1__1__2_left_grid_pin_1_ ; +wire [0:0] cby_1__1__2_left_grid_pin_2_ ; +wire [0:0] cby_1__1__2_left_grid_pin_3_ ; +wire [0:0] cby_1__1__2_left_grid_pin_4_ ; +wire [0:0] cby_1__1__2_left_grid_pin_5_ ; +wire [0:0] cby_1__1__2_left_grid_pin_6_ ; +wire [0:0] cby_1__1__2_left_grid_pin_7_ ; +wire [0:0] cby_1__1__2_left_grid_pin_8_ ; +wire [0:0] cby_1__1__2_left_grid_pin_9_ ; +wire [0:0] cby_1__1__2_right_grid_pin_52_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:19] cby_1__1__3_chany_bottom_out ; +wire [0:19] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_0_ ; +wire [0:0] cby_1__1__3_left_grid_pin_10_ ; +wire [0:0] cby_1__1__3_left_grid_pin_11_ ; +wire [0:0] cby_1__1__3_left_grid_pin_12_ ; +wire [0:0] cby_1__1__3_left_grid_pin_13_ ; +wire [0:0] cby_1__1__3_left_grid_pin_14_ ; +wire [0:0] cby_1__1__3_left_grid_pin_15_ ; +wire [0:0] cby_1__1__3_left_grid_pin_1_ ; +wire [0:0] cby_1__1__3_left_grid_pin_2_ ; +wire [0:0] cby_1__1__3_left_grid_pin_3_ ; +wire [0:0] cby_1__1__3_left_grid_pin_4_ ; +wire [0:0] cby_1__1__3_left_grid_pin_5_ ; +wire [0:0] cby_1__1__3_left_grid_pin_6_ ; +wire [0:0] cby_1__1__3_left_grid_pin_7_ ; +wire [0:0] cby_1__1__3_left_grid_pin_8_ ; +wire [0:0] cby_1__1__3_left_grid_pin_9_ ; +wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:19] sb_0__0__0_chanx_right_out ; +wire [0:19] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:19] sb_0__1__0_chanx_right_out ; +wire [0:19] sb_0__1__0_chany_bottom_out ; +wire [0:19] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__2__0_ccff_tail ; +wire [0:19] sb_0__2__0_chanx_right_out ; +wire [0:19] sb_0__2__0_chany_bottom_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:19] sb_1__0__0_chanx_left_out ; +wire [0:19] sb_1__0__0_chanx_right_out ; +wire [0:19] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:19] sb_1__1__0_chanx_left_out ; +wire [0:19] sb_1__1__0_chanx_right_out ; +wire [0:19] sb_1__1__0_chany_bottom_out ; +wire [0:19] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__2__0_ccff_tail ; +wire [0:19] sb_1__2__0_chanx_left_out ; +wire [0:19] sb_1__2__0_chanx_right_out ; +wire [0:19] sb_1__2__0_chany_bottom_out ; +wire [0:0] sb_2__0__0_ccff_tail ; +wire [0:19] sb_2__0__0_chanx_left_out ; +wire [0:19] sb_2__0__0_chany_top_out ; +wire [0:0] sb_2__1__0_ccff_tail ; +wire [0:19] sb_2__1__0_chanx_left_out ; +wire [0:19] sb_2__1__0_chany_bottom_out ; +wire [0:19] sb_2__1__0_chany_top_out ; +wire [0:0] sb_2__2__0_ccff_tail ; +wire [0:19] sb_2__2__0_chanx_left_out ; +wire [0:19] sb_2__2__0_chany_bottom_out ; +supply1 VDD ; +supply0 VSS ; +// + +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1827 } ) , + .Test_en ( { BUF_net_9 } ) , + .clk ( clk ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_33 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_40 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__1_ ( + .prog_clk ( { ctsbuf_net_413 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__2_ ( + .prog_clk ( { ctsbuf_net_615 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_top grid_io_top_1__3_ ( + .prog_clk ( { ctsbuf_net_918 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__0_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_top grid_io_top_2__3_ ( + .prog_clk ( { ctsbuf_net_514 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__1_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_right grid_io_right_3__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_right grid_io_right_3__2_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__0_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_bottom grid_io_bottom_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__1_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_left grid_io_left_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__0_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_io_left grid_io_left_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__1_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__1_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2_ sb_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( { ropt_net_38 } ) , + .chanx_right_out ( sb_0__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , + .ccff_tail ( sb_0__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_1423 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( { ropt_net_36 } ) , + .chanx_right_out ( sb_1__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__2__0_chanx_left_out ) , + .ccff_tail ( sb_1__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0_ sb_2__0_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_2__0__0_chany_top_out ) , + .chanx_left_out ( sb_2__0__0_chanx_left_out ) , + .ccff_tail ( sb_2__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_2__1_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_2__1__0_chany_top_out ) , + .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__1__0_chanx_left_out ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2_ sb_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__2__0_chanx_left_out ) , + .ccff_tail ( sb_2__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0_ cbx_1__0_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0_ cbx_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_2__0__0_chanx_left_out ) , + .ccff_head ( sb_2__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__1_ ( + .prog_clk ( { ctsbuf_net_1726 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__1_ ( + .prog_clk ( { ctsbuf_net_1120 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_2__1__0_chanx_left_out ) , + .ccff_head ( sb_2__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2_ cbx_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .chanx_left_in ( sb_0__2__0_chanx_right_out ) , + .chanx_right_in ( sb_1__2__0_chanx_left_out ) , + .ccff_head ( sb_1__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2_ cbx_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chanx_left_in ( sb_1__2__0_chanx_right_out ) , + .chanx_right_in ( sb_2__2__0_chanx_left_out ) , + .ccff_head ( sb_2__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__2__0_chany_bottom_out ) , + .ccff_head ( sb_0__2__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_bottom_in ( sb_2__0__0_chany_top_out ) , + .chany_top_in ( sb_2__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( sb_2__1__0_chany_top_out ) , + .chany_top_in ( sb_2__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_0 direct_interc_0_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_2 direct_interc_2_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_3 direct_interc_3_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_4 direct_interc_4_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +direct_interc_5 direct_interc_5_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_5_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7749 ( + .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_31 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7750 ( .A ( ropt_net_31 ) , + .X ( ropt_net_32 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7751 ( .A ( ropt_net_32 ) , + .X ( ropt_net_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_9 ( .A ( Test_en[0] ) , + .X ( BUF_net_9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7752 ( + .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_34 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73507625 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73517626 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73527627 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_312 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73537628 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_413 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73547629 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73557630 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73567631 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_716 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73577632 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_817 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73587633 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_918 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73597634 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1019 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7753 ( .A ( ropt_net_34 ) , + .X ( ropt_net_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73617636 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73627637 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1322 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7754 ( .A ( ropt_net_35 ) , + .X ( ropt_net_36 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73647639 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73657640 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7755 ( + .A ( grid_io_top_0_ccff_tail[0] ) , .X ( ropt_net_37 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73677642 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1827 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_73667641_73687643 ( + .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufinv_16 cts_inv_73607635_73697644 ( + .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( SYNOPSYS_UNCONNECTED_4 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7756 ( .A ( ropt_net_37 ) , + .X ( ropt_net_38 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73827657 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1928 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73837658 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2029 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73847659 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7757 ( + .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_39 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7758 ( .A ( ropt_net_39 ) , + .X ( ropt_net_40 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2980800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8261600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8298400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8335200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8372000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8408800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8445600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8482400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8519200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8556000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8592800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8629600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8666400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8703200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8740000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8776800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8813600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8850400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8887200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8924000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8960800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8997600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9034400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9071200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9108000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9144800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9181600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9218400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5115200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5170400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5474000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2741600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6384800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2796800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2879600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2916400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2953200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2990000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3026800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3063600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3100400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3137200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3174000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3210800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3247600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3284400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3321200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3358000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3394800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3431600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3468400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3505200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3542000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3578800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3615600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3652400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3689200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3726000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3762800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3781200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2898000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2934800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2971600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3781200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5520000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6274400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6384800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5133600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5152000y5440000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5469400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5478600y5440000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6329600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6348000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6670000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6706800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6743600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6780400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6817200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6854000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6890800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6927600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6964400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7001200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7038000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7074800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7111600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7148400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7185200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7222000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7258800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7295600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7332400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7369200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7406000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7442800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7479600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7516400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7553200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7590000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7626800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7663600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7700400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8068400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8086800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5152000y5494400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5469400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5478600y5494400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x8077600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2502400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5115200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5170400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5474000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x7728000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x7783200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7829200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7866000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7902800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7939600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7976400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8013200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8050000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x8086800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6963200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y6990400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7017600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7044800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7072000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7099200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7126400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7153600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7180800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7208000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7235200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7262400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7289600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7316800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7344000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7371200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7398400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7425600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7452800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7480000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7507200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7534400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7561600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7588800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7616000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7643200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7670400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7697600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7724800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2539200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2741600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2778400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2815200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2852000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x9052800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y7752000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3772000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6274400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6384800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7779200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2760000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2778400y7806400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2852000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2888800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2925600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2962400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3772000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7806400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7833600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7860800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7888000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7915200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7942400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7969600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y7996800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8024000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8051200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8078400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8105600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8132800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8160000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8187200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8214400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8241600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8268800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8296000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8323200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8350400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8377600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8404800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8432000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8459200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8486400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8513600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8540800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8568000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8595200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8622400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8649600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8676800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8704000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8731200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8758400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8785600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8812800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8840000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8867200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8894400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8921600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y8948800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4195200y8976000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5616600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5635000y8976000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6320400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6357200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6394000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6430800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6467600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6504400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6541200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6578000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6688400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6725200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6762000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6798800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6835600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6872400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6909200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6946000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6982800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7019600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7056400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7093200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7130000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7166800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7203600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7240400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7277200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7314000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7350800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7387600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7424400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7461200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7498000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7534800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7571600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7608400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7645200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7682000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7718800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7755600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7792400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7829200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7866000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7902800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7939600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7976400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8013200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8050000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8086800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8123600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8160400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8197200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8234000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8270800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8307600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8344400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8381200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8418000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8454800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8491600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8528400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8565200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8602000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8638800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8675600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8712400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8749200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8786000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8822800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8859600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8896400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8933200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8970000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9006800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9043600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9080400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9117200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9154000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9190800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9227600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9264400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9301200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9338000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9374800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9411600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9448400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9485200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9522000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9558800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9595600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9632400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9669200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9706000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9742800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9779600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9816400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9853200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9890000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9926800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9963600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10000400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10037200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10074000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10110800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10147600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10184400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10221200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10258000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10294800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10331600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10368400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10405200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10442000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10478800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10515600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10552400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10589200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10626000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10662800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10699600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10736400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10773200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10810000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10846800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10883600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10920400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10957200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10994000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11030800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11067600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11104400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11141200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11178000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11214800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11251600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11288400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11325200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11362000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11398800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11435600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11472400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11509200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11546000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11582800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11619600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11656400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11693200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11730000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11766800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11803600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11840400y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11877200y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11914000y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11950800y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y8976000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9003200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9030400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9057600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6559600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6578000y9084800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6614800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6651600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9084800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3937600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3956000y9112000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4071000y9112000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6559600y9112000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6637800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6674600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6683800y9112000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9112000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9139200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9166400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9193600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5124400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5161200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5198000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5234800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5271600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5308400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6265200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6302000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6338800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6375600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6412400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6449200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6486000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6522800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6559600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6596400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6633200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6670000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7737200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7774000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7810800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7847600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7884400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7921200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7958000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7994800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8031600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8068400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8105200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8142000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8178800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8215600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8252400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8289200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8326000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8362800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8399600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8436400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8473200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8510000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8546800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8583600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8620400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8657200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8694000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8730800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8767600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8804400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8841200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8878000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8914800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8951600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8988400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9025200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9062000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9098800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9135600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9172400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9209200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9246000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9282800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9319600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9356400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9393200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9430000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9466800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9503600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9540400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9577200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9614000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9650800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9687600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9724400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9761200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9798000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9834800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9871600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9908400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9945200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9982000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10018800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10055600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10092400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10129200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10166000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10202800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10239600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10276400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10313200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10350000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10386800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10423600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10460400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10497200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10534000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10570800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10607600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10644400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10681200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10718000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10754800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10791600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10828400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10865200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10902000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10938800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10975600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11012400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11049200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11086000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11122800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11159600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11196400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11233200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11270000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11306800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11343600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11380400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11417200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11454000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11490800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11527600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11564400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11601200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11638000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11674800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11711600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11748400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11785200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11822000y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11858800y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11895600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11932400y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11969200y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x11987600y9220800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9248000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9275200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9302400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9329600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9356800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9384000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9411200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9438400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9465600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9492800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9520000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9547200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9574400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9601600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9628800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9656000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9683200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9710400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9737600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9764800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9792000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9819200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9846400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9873600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9900800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9928000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9955200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y9982400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10009600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10036800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10064000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10091200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10118400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10145600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10172800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10200000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10227200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10254400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10281600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10308800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10336000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10363200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10390400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10417600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10444800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10472000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10499200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10526400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10553600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10580800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2980800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4324000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4360800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4397600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4434400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4471200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4508000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4544800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4581600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4618400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4655200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4692000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4728800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4765600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4802400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4839200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4876000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4912800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4949600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5391200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5428000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5464800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5501600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5538400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5575200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5612000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5648800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5685600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5722400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5759200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5796000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5832800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5869600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5906400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5943200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5980000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6016800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6053600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6090400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6127200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6164000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6200800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6237600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6274400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6311200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6348000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6384800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6421600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6458400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6495200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6532000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6568800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6605600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6642400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6679200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6716000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6752800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6789600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6826400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6863200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6900000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6936800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6973600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7010400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7047200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7084000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7120800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7157600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7194400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7231200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7268000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7304800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7341600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7378400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7415200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7452000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7488800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7525600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7562400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7599200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7636000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7672800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7709600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7746400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7783200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7820000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7856800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7893600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7930400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7967200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8004000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8040800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8077600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8114400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8151200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8188000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8224800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8261600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8298400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8335200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8372000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8408800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8445600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8482400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8519200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8556000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8592800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8629600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8666400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8703200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8740000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8776800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8813600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8850400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8887200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8924000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8960800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8997600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9034400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9071200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9108000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9144800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9181600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9218400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9255200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9292000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9328800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9365600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9402400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9439200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9476000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9512800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9549600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9586400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9623200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9660000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9696800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9733600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9770400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9807200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9844000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9880800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9917600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9954400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9991200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10028000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10064800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10101600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10138400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10175200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10212000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10248800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10285600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10322400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10359200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10396000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10432800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10469600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10506400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10543200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10580000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10616800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10653600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10690400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10727200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10764000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10800800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10837600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10874400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10911200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10948000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10984800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11021600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11058400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11095200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11132000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11168800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11205600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11242400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11279200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11316000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11352800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11389600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11426400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11463200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11500000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11536800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11573600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11610400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11647200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11684000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11720800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11757600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11794400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11831200y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11868000y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11904800y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11941600y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x11978400y10608000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10635200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10662400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10689600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10716800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10744000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10771200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10798400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10825600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10852800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10880000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10907200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10934400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10961600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y10988800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11016000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11043200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11070400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11097600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11124800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11152000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11179200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11206400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11233600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11260800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11288000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11315200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11342400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11369600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11396800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11424000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11451200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11478400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11505600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11532800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11560000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11587200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11614400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11641600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11668800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11696000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11723200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11750400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11777600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11804800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11832000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11859200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11886400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11913600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1398400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1435200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1472000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1508800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1545600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1582400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1619200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1656000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1840000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1876800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1913600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1950400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2060800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2097600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2134400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2171200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2208000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2244800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2281600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2318400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2355200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2392000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2428800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3054400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3091200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3128000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3164800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3201600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3238400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3275200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3312000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3348800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3385600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3422400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3459200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3496000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3532800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3569600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3606400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3643200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3680000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3716800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4305600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4342400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4379200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4416000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4452800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4489600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4526400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4563200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4600000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4636800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4673600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4894400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4931200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5041600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5078400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5115200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5152000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5188800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5225600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5262400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5299200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5336000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5372800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5409600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5446400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5483200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5520000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5556800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5593600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5630400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5667200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5704000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5740800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5777600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6955200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6992000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7028800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7065600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7102400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7139200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7176000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7212800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7249600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7286400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7323200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7360000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7396800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7433600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7470400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7507200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7544000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7580800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7617600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7654400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7691200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7728000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7764800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7801600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7838400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7875200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7912000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7948800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x7985600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8022400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8059200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8096000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8132800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8169600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8206400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8243200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8280000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8316800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8353600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8390400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8427200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8464000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8500800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8537600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8574400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8611200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8648000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8684800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8721600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8758400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8795200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8832000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8868800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8905600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8942400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x8979200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9016000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9052800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9089600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9126400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9163200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9200000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9236800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9273600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9310400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9347200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9384000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9420800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9457600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9494400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9531200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9568000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9604800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9641600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9678400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9715200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9752000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9788800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9825600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9862400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9899200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9936000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x9972800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10009600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10046400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10083200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10120000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10156800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10193600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10230400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10267200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10304000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10340800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10377600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10414400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10451200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10488000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10524800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10561600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10598400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10635200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10672000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10708800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10745600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10782400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10819200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10856000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10892800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10929600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x10966400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11003200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11040000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11076800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11113600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11150400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11187200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11224000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11260800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11297600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11334400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11371200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11408000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11444800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11481600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11518400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11555200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11592000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11628800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11665600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11702400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11739200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11776000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11812800y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11849600y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11886400y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11923200y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x11960000y11940800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef new file mode 100644 index 0000000..5c928f2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef @@ -0,0 +1,33630 @@ +*SPEF "1481-1998" +*DESIGN "fpga_core" +*DATE "Mon Oct 26 23:01:55 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 0.297 591.600 +Test_en[0] I *C 1199.383 601.800 +clk[0] I *C 1199.383 602.480 +gfpga_pad_GPIO_A[0] O *C 506.460 1196.558 +gfpga_pad_GPIO_A[1] O *C 694.140 1196.558 +gfpga_pad_GPIO_A[2] O *C 1199.383 463.080 +gfpga_pad_GPIO_A[3] O *C 1199.383 756.840 +gfpga_pad_GPIO_A[4] O *C 470.120 0.243 +gfpga_pad_GPIO_A[5] O *C 701.500 0.243 +gfpga_pad_GPIO_A[6] O *C 0.297 475.320 +gfpga_pad_GPIO_A[7] O *C 0.297 725.220 +gfpga_pad_GPIO_IE[0] O *C 465.520 1196.558 +gfpga_pad_GPIO_IE[1] O *C 726.800 1196.558 +gfpga_pad_GPIO_IE[2] O *C 1199.383 460.360 +gfpga_pad_GPIO_IE[3] O *C 1199.383 721.480 +gfpga_pad_GPIO_IE[4] O *C 459.080 0.243 +gfpga_pad_GPIO_IE[5] O *C 720.360 0.243 +gfpga_pad_GPIO_IE[6] O *C 0.297 458.660 +gfpga_pad_GPIO_IE[7] O *C 0.297 719.780 +gfpga_pad_GPIO_OE[0] O *C 450.340 1196.558 +gfpga_pad_GPIO_OE[1] O *C 711.620 1196.558 +gfpga_pad_GPIO_OE[2] O *C 1199.383 450.160 +gfpga_pad_GPIO_OE[3] O *C 1199.383 711.280 +gfpga_pad_GPIO_OE[4] O *C 445.740 0.243 +gfpga_pad_GPIO_OE[5] O *C 707.020 0.243 +gfpga_pad_GPIO_OE[6] O *C 0.297 433.840 +gfpga_pad_GPIO_OE[7] O *C 0.297 694.960 +gfpga_pad_GPIO_Y[0] I *C 430.560 1196.558 +gfpga_pad_GPIO_Y[1] I *C 736.000 1196.558 +gfpga_pad_GPIO_Y[2] I *C 1199.383 499.800 +gfpga_pad_GPIO_Y[3] I *C 1199.383 708.220 +gfpga_pad_GPIO_Y[4] I *C 418.140 0.243 +gfpga_pad_GPIO_Y[5] I *C 675.280 0.243 +gfpga_pad_GPIO_Y[6] I *C 0.297 457.640 +gfpga_pad_GPIO_Y[7] I *C 0.297 680.680 +ccff_head[0] I *C 799.940 1196.558 +ccff_tail[0] O *C 0.297 362.440 +VDD I *C 599.840 598.400 +VSS I *C 599.840 598.400 + +*D_NET Test_en[0] 0.1399642 //LENGTH 1392.735 LUMPCC 0.01206547 DR + +*CONN +*P Test_en[0] I *L 0 *C 1199.155 601.800 +*I grid_clb_2__1_:Test_en[0] I *L 0 *C 802.090 520.880 +*I BUFT_P_9:A I *L 0.001746 *C 554.300 523.600 +*I grid_clb_2__2_:Test_en[0] I *L 0 *C 802.090 782.000 +*I grid_clb_1__2_:Test_en[0] I *L 0 *C 540.810 782.000 +*N Test_en[0]:5 *C 541.413 782.000 +*N Test_en[0]:6 *C 541.420 782.058 +*N Test_en[0]:7 *C 541.420 786.023 +*N Test_en[0]:8 *C 541.428 786.080 +*N Test_en[0]:9 *C 591.255 786.080 +*N Test_en[0]:10 *C 633.860 786.080 +*N Test_en[0]:11 *C 633.880 786.088 +*N Test_en[0]:12 *C 633.880 810.553 +*N Test_en[0]:13 *C 633.900 810.560 +*N Test_en[0]:14 *C 667.519 810.560 +*N Test_en[0]:15 *C 667.520 810.560 +*N Test_en[0]:16 *C 683.690 810.560 +*N Test_en[0]:17 *C 733.690 810.560 +*N Test_en[0]:18 *C 783.690 810.560 +*N Test_en[0]:19 *C 804.060 810.560 +*N Test_en[0]:20 *C 804.080 810.553 +*N Test_en[0]:21 *C 804.060 782.000 +*N Test_en[0]:22 *C 804.080 782.000 +*N Test_en[0]:23 *C 804.080 779.288 +*N Test_en[0]:24 *C 804.100 779.280 +*N Test_en[0]:25 *C 853.890 779.280 +*N Test_en[0]:26 *C 891.519 779.280 +*N Test_en[0]:27 *C 891.520 779.280 +*N Test_en[0]:28 *C 903.420 779.280 +*N Test_en[0]:29 *C 903.440 779.273 +*N Test_en[0]:30 *C 903.440 752.995 +*N Test_en[0]:31 *C 903.440 702.995 +*N Test_en[0]:32 *C 903.440 667.520 +*N Test_en[0]:33 *C 903.440 667.519 +*N Test_en[0]:34 *C 903.440 652.995 +*N Test_en[0]:35 *C 903.440 603.168 +*N Test_en[0]:36 *C 903.460 603.160 +*N Test_en[0]:37 *C 917.220 603.160 +*N Test_en[0]:38 *C 917.240 603.153 +*N Test_en[0]:39 *C 554.300 523.615 +*N Test_en[0]:40 *C 554.300 523.940 +*N Test_en[0]:41 *C 554.300 523.985 +*N Test_en[0]:42 *C 554.300 525.935 +*N Test_en[0]:43 *C 554.345 525.980 +*N Test_en[0]:44 *C 604.140 525.980 +*N Test_en[0]:45 *C 634.755 525.980 +*N Test_en[0]:46 *C 634.800 526.025 +*N Test_en[0]:47 *C 634.800 545.655 +*N Test_en[0]:48 *C 634.845 545.700 +*N Test_en[0]:49 *C 667.519 545.700 +*N Test_en[0]:50 *C 667.520 545.700 +*N Test_en[0]:51 *C 684.640 545.700 +*N Test_en[0]:52 *C 734.640 545.700 +*N Test_en[0]:53 *C 784.640 545.700 +*N Test_en[0]:54 *C 803.115 545.700 +*N Test_en[0]:55 *C 803.160 545.655 +*N Test_en[0]:56 *C 803.160 526.378 +*N Test_en[0]:57 *C 803.168 526.320 +*N Test_en[0]:58 *C 804.980 520.880 +*N Test_en[0]:59 *C 805.000 520.888 +*N Test_en[0]:60 *C 805.000 526.312 +*N Test_en[0]:61 *C 805.000 526.320 +*N Test_en[0]:62 *C 855.000 526.320 +*N Test_en[0]:63 *C 891.519 526.320 +*N Test_en[0]:64 *C 891.520 526.320 +*N Test_en[0]:65 *C 905.000 526.320 +*N Test_en[0]:66 *C 917.220 526.320 +*N Test_en[0]:67 *C 917.240 526.327 +*N Test_en[0]:68 *C 917.240 576.155 +*N Test_en[0]:69 *C 917.240 601.800 +*N Test_en[0]:70 *C 917.260 601.800 +*N Test_en[0]:71 *C 967.050 601.800 +*N Test_en[0]:72 *C 1017.050 601.800 +*N Test_en[0]:73 *C 1067.050 601.800 +*N Test_en[0]:74 *C 1115.519 601.800 +*N Test_en[0]:75 *C 1115.520 601.800 +*N Test_en[0]:76 *C 1117.050 601.800 +*N Test_en[0]:77 *C 1167.050 601.800 +*N Test_en[0]:78 *C 1198.753 601.800 +*N Test_en[0]:79 *C 1198.760 601.800 +*N Test_en[0]:80 *C 1198.805 601.800 + +*CAP +0 Test_en[0] 2.888966e-05 +1 grid_clb_2__1_:Test_en[0] 0.0001852348 +2 BUFT_P_9:A 1e-06 +3 grid_clb_2__2_:Test_en[0] 0.0001076267 +4 grid_clb_1__2_:Test_en[0] 0.0001121013 +5 Test_en[0]:5 0.0001121013 +6 Test_en[0]:6 0.0002565065 +7 Test_en[0]:7 0.0002565065 +8 Test_en[0]:8 0.002223193 +9 Test_en[0]:9 0.004073875 +10 Test_en[0]:10 0.001850683 +11 Test_en[0]:11 0.001255824 +12 Test_en[0]:12 0.001255824 +13 Test_en[0]:13 0.001285395 +14 Test_en[0]:14 0.001285395 +15 Test_en[0]:15 0.0004979158 +16 Test_en[0]:16 0.001971785 +17 Test_en[0]:17 0.002999675 +18 Test_en[0]:18 0.002343946 +19 Test_en[0]:19 0.0008181387 +20 Test_en[0]:20 0.001339421 +21 Test_en[0]:21 0.0001076267 +22 Test_en[0]:22 0.001493745 +23 Test_en[0]:23 0.0001543235 +24 Test_en[0]:24 0.002984205 +25 Test_en[0]:25 0.005374456 +26 Test_en[0]:26 0.00239025 +27 Test_en[0]:27 0.0004673245 +28 Test_en[0]:28 0.0004673245 +29 Test_en[0]:29 0.001075826 +30 Test_en[0]:30 0.003031488 +31 Test_en[0]:31 0.003322075 +32 Test_en[0]:32 0.001366413 +33 Test_en[0]:33 0.000664668 +34 Test_en[0]:34 0.002495839 +35 Test_en[0]:35 0.001831171 +36 Test_en[0]:36 0.0006365847 +37 Test_en[0]:37 0.0006365847 +38 Test_en[0]:38 6.989982e-05 +39 Test_en[0]:39 3.048138e-05 +40 Test_en[0]:40 5.823372e-05 +41 Test_en[0]:41 0.0001167858 +42 Test_en[0]:42 0.0001167858 +43 Test_en[0]:43 0.00279753 +44 Test_en[0]:44 0.004451192 +45 Test_en[0]:45 0.001653662 +46 Test_en[0]:46 0.0009430735 +47 Test_en[0]:47 0.0009430735 +48 Test_en[0]:48 0.001889392 +49 Test_en[0]:49 0.001889392 +50 Test_en[0]:50 0.0009605181 +51 Test_en[0]:51 0.003770723 +52 Test_en[0]:52 0.005624368 +53 Test_en[0]:53 0.003854699 +54 Test_en[0]:54 0.001040536 +55 Test_en[0]:55 0.0008900589 +56 Test_en[0]:56 0.0008900589 +57 Test_en[0]:57 8.121394e-05 +58 Test_en[0]:58 0.0001852348 +59 Test_en[0]:59 0.000270995 +60 Test_en[0]:60 0.000270995 +61 Test_en[0]:61 0.003164388 +62 Test_en[0]:62 0.005402716 +63 Test_en[0]:63 0.002319543 +64 Test_en[0]:64 0.0006148934 +65 Test_en[0]:65 0.001150561 +66 Test_en[0]:66 0.0005356673 +67 Test_en[0]:67 0.001839599 +68 Test_en[0]:68 0.002792177 +69 Test_en[0]:69 0.001022478 +70 Test_en[0]:70 0.002097075 +71 Test_en[0]:71 0.00418153 +72 Test_en[0]:72 0.00416609 +73 Test_en[0]:73 0.004100516 +74 Test_en[0]:74 0.002018881 +75 Test_en[0]:75 6.40434e-05 +76 Test_en[0]:76 0.002143594 +77 Test_en[0]:77 0.003371185 +78 Test_en[0]:78 0.001291634 +79 Test_en[0]:79 3.332888e-05 +80 Test_en[0]:80 2.888966e-05 +81 Test_en[0] clk[0] 1.232618e-05 +82 grid_clb_1__2_:Test_en[0] grid_clb_1__2_:clk[0] 4.768238e-06 +83 grid_clb_2__2_:Test_en[0] grid_clb_2__2_:clk[0] 5.069699e-05 +84 Test_en[0]:78 clk[0]:84 9.815069e-05 +85 Test_en[0]:80 clk[0]:87 1.232618e-05 +86 Test_en[0]:28 clk[0]:8 0.0002519766 +87 Test_en[0]:28 clk[0]:9 3.704762e-05 +88 Test_en[0]:24 grid_clb_2__2_:clk[0] 0.0008642827 +89 Test_en[0]:24 clk[0]:5 2.91031e-05 +90 Test_en[0]:8 grid_clb_1__2_:clk[0] 6.999164e-07 +91 Test_en[0]:5 clk[0]:22 4.768238e-06 +92 Test_en[0]:21 clk[0]:5 5.069699e-05 +93 Test_en[0]:47 clk[0]:40 1.189506e-06 +94 Test_en[0]:46 clk[0]:39 1.189506e-06 +95 Test_en[0]:9 clk[0]:22 6.999164e-07 +96 Test_en[0]:25 clk[0]:5 0.001494469 +97 Test_en[0]:25 clk[0]:6 2.91031e-05 +98 Test_en[0]:77 clk[0]:85 9.815069e-05 +99 Test_en[0]:27 clk[0]:8 3.704762e-05 +100 Test_en[0]:27 clk[0]:7 0.0002519766 +101 Test_en[0]:26 clk[0]:6 0.0006301859 +102 Test_en[0]:13 cbx_1__2__1_chanx_left_out[14]:5 2.739735e-05 +103 Test_en[0]:16 cbx_1__2__1_chanx_left_out[14]:8 5.255961e-05 +104 Test_en[0]:15 cbx_1__2__1_chanx_left_out[14]:7 5.255961e-05 +105 Test_en[0]:14 cbx_1__2__1_chanx_left_out[14]:6 2.739735e-05 +106 Test_en[0]:13 direct_interc_2_out[0]:9 0.0003902735 +107 Test_en[0]:12 direct_interc_2_out[0]:10 0.0001525327 +108 Test_en[0]:11 direct_interc_2_out[0]:11 0.0001525327 +109 Test_en[0]:47 direct_interc_2_out[0]:26 3.105926e-05 +110 Test_en[0]:46 direct_interc_2_out[0]:27 3.105926e-05 +111 Test_en[0]:16 direct_interc_2_out[0]:6 0.0007894946 +112 Test_en[0]:16 direct_interc_2_out[0]:7 5.820147e-05 +113 Test_en[0]:17 direct_interc_2_out[0]:6 0.0001220297 +114 Test_en[0]:17 direct_interc_2_out[0]:5 0.001074846 +115 Test_en[0]:18 direct_interc_2_out[0]:4 0.000488191 +116 Test_en[0]:18 direct_interc_2_out[0]:5 6.38282e-05 +117 Test_en[0]:15 direct_interc_2_out[0]:7 0.0002028396 +118 Test_en[0]:14 direct_interc_2_out[0]:8 0.0003902735 +119 Test_en[0]:56 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 2.577347e-05 +120 Test_en[0]:57 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] 1.831939e-05 +121 Test_en[0]:55 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 2.577347e-05 +122 Test_en[0]:61 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] 1.348515e-05 +123 Test_en[0]:61 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 1.831939e-05 +124 Test_en[0]:62 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 1.348515e-05 +125 Test_en[0]:20 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 0.000175375 +126 Test_en[0]:22 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 0.000175375 +127 Test_en[0]:19 ctsbuf_net_312:11 0.0001572697 +128 Test_en[0]:20 ctsbuf_net_312:9 1.335429e-05 +129 Test_en[0]:20 ctsbuf_net_312:10 2.782057e-05 +130 Test_en[0]:13 ctsbuf_net_312:19 1.481498e-05 +131 Test_en[0]:22 ctsbuf_net_312:5 1.335429e-05 +132 Test_en[0]:22 ctsbuf_net_312:9 2.782057e-05 +133 Test_en[0]:16 ctsbuf_net_312:14 0.0002975839 +134 Test_en[0]:16 ctsbuf_net_312:13 0.0001698855 +135 Test_en[0]:17 ctsbuf_net_312:13 0.0005959724 +136 Test_en[0]:17 ctsbuf_net_312:12 0.0001803342 +137 Test_en[0]:18 ctsbuf_net_312:11 9.138983e-05 +138 Test_en[0]:18 ctsbuf_net_312:12 0.0004556583 +139 Test_en[0]:15 ctsbuf_net_312:14 8.094108e-05 +140 Test_en[0]:14 ctsbuf_net_312:18 1.481498e-05 +141 Test_en[0]:10 ctsbuf_net_2130:24 2.493984e-05 +142 Test_en[0]:10 ctsbuf_net_2130:25 0.0002743822 +143 Test_en[0]:10 ctsbuf_net_2130:26 8.925112e-06 +144 Test_en[0]:8 ctsbuf_net_2130:27 0.0003870621 +145 Test_en[0]:9 ctsbuf_net_2130:27 8.925112e-06 +146 Test_en[0]:9 ctsbuf_net_2130:25 2.493984e-05 +147 Test_en[0]:9 ctsbuf_net_2130:26 0.0006614443 + +*RES +0 Test_en[0] Test_en[0]:80 0.0003125 +1 Test_en[0]:70 Test_en[0]:69 0.00341 +2 Test_en[0]:69 Test_en[0]:68 0.004017716 +3 Test_en[0]:69 Test_en[0]:38 0.0002118916 +4 Test_en[0]:79 Test_en[0]:78 0.00341 +5 Test_en[0]:78 Test_en[0]:77 0.004966725 +6 Test_en[0]:80 Test_en[0]:79 0.0045 +7 Test_en[0]:66 Test_en[0]:65 0.001914467 +8 Test_en[0]:67 Test_en[0]:66 0.00341 +9 Test_en[0]:37 Test_en[0]:36 0.002155733 +10 Test_en[0]:38 Test_en[0]:37 0.00341 +11 Test_en[0]:36 Test_en[0]:35 0.00341 +12 Test_en[0]:35 Test_en[0]:34 0.007806308 +13 Test_en[0]:28 Test_en[0]:27 0.001864333 +14 Test_en[0]:29 Test_en[0]:28 0.00341 +15 Test_en[0]:24 Test_en[0]:23 0.00341 +16 Test_en[0]:23 Test_en[0]:22 0.0004249583 +17 Test_en[0]:19 Test_en[0]:18 0.0031913 +18 Test_en[0]:20 Test_en[0]:19 0.00341 +19 Test_en[0]:13 Test_en[0]:12 0.00341 +20 Test_en[0]:12 Test_en[0]:11 0.00383285 +21 Test_en[0]:10 Test_en[0]:9 0.006674783 +22 Test_en[0]:11 Test_en[0]:10 0.00341 +23 Test_en[0]:7 Test_en[0]:6 0.003540179 +24 Test_en[0]:8 Test_en[0]:7 0.00341 +25 Test_en[0]:6 Test_en[0]:5 0.00341 +26 Test_en[0]:5 grid_clb_1__2_:Test_en[0] 9.439165e-05 +27 Test_en[0]:21 grid_clb_2__2_:Test_en[0] 0.0003086333 +28 Test_en[0]:22 Test_en[0]:21 0.00341 +29 Test_en[0]:22 Test_en[0]:20 0.004473225 +30 Test_en[0]:56 Test_en[0]:55 0.01721206 +31 Test_en[0]:57 Test_en[0]:56 0.00341 +32 Test_en[0]:54 Test_en[0]:53 0.01649554 +33 Test_en[0]:55 Test_en[0]:54 0.0045 +34 Test_en[0]:48 Test_en[0]:47 0.0045 +35 Test_en[0]:47 Test_en[0]:46 0.01752679 +36 Test_en[0]:45 Test_en[0]:44 0.02733482 +37 Test_en[0]:46 Test_en[0]:45 0.0045 +38 Test_en[0]:43 Test_en[0]:42 0.0045 +39 Test_en[0]:42 Test_en[0]:41 0.001741071 +40 Test_en[0]:40 Test_en[0]:39 0.0001766304 +41 Test_en[0]:41 Test_en[0]:40 0.0045 +42 Test_en[0]:39 BUFT_P_9:A 0.152 +43 Test_en[0]:61 Test_en[0]:60 0.00341 +44 Test_en[0]:61 Test_en[0]:57 0.0002870917 +45 Test_en[0]:60 Test_en[0]:59 0.0008499166 +46 Test_en[0]:58 grid_clb_2__1_:Test_en[0] 0.0004527666 +47 Test_en[0]:59 Test_en[0]:58 0.00341 +48 Test_en[0]:44 Test_en[0]:43 0.04445983 +49 Test_en[0]:51 Test_en[0]:50 0.01528571 +50 Test_en[0]:52 Test_en[0]:51 0.04464286 +51 Test_en[0]:53 Test_en[0]:52 0.04464286 +52 Test_en[0]:9 Test_en[0]:8 0.007806308 +53 Test_en[0]:16 Test_en[0]:15 0.0025333 +54 Test_en[0]:17 Test_en[0]:16 0.007833333 +55 Test_en[0]:18 Test_en[0]:17 0.007833333 +56 Test_en[0]:62 Test_en[0]:61 0.007833333 +57 Test_en[0]:65 Test_en[0]:64 0.002111867 +58 Test_en[0]:25 Test_en[0]:24 0.007800432 +59 Test_en[0]:71 Test_en[0]:70 0.007800433 +60 Test_en[0]:72 Test_en[0]:71 0.007833333 +61 Test_en[0]:73 Test_en[0]:72 0.007833333 +62 Test_en[0]:76 Test_en[0]:75 0.0002397 +63 Test_en[0]:77 Test_en[0]:76 0.007833333 +64 Test_en[0]:34 Test_en[0]:33 0.002275426 +65 Test_en[0]:31 Test_en[0]:30 0.007833333 +66 Test_en[0]:30 Test_en[0]:29 0.004116808 +67 Test_en[0]:68 Test_en[0]:67 0.007806308 +68 Test_en[0]:27 Test_en[0]:26 1e-05 +69 Test_en[0]:26 Test_en[0]:25 0.005895209 +70 Test_en[0]:50 Test_en[0]:49 1e-05 +71 Test_en[0]:49 Test_en[0]:48 0.02917322 +72 Test_en[0]:15 Test_en[0]:14 1e-05 +73 Test_en[0]:14 Test_en[0]:13 0.005266977 +74 Test_en[0]:64 Test_en[0]:63 1e-05 +75 Test_en[0]:63 Test_en[0]:62 0.00572131 +76 Test_en[0]:75 Test_en[0]:74 1e-05 +77 Test_en[0]:74 Test_en[0]:73 0.007593476 +78 Test_en[0]:32 Test_en[0]:31 0.00555775 +79 Test_en[0]:33 Test_en[0]:32 1e-05 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[5] 0.001566639 //LENGTH 7.660 LUMPCC 0.0004235531 DR + +*CONN +*I cbx_2__1_:chanx_left_out[5] O *L 0 *C 668.990 622.880 +*I sb_1__1_:chanx_right_in[5] I *L 0 *C 661.330 622.880 +*N cbx_1__1__1_chanx_left_out[5]:2 *C 667.519 622.880 +*N cbx_1__1__1_chanx_left_out[5]:3 *C 667.520 622.880 + +*CAP +0 cbx_2__1_:chanx_left_out[5] 0.0002209402 +1 sb_1__1_:chanx_right_in[5] 0.0003506028 +2 cbx_1__1__1_chanx_left_out[5]:2 0.0003506028 +3 cbx_1__1__1_chanx_left_out[5]:3 0.0002209402 +4 sb_1__1_:chanx_right_in[5] sb_1__1_:chanx_right_in[4] 0.0001070368 +5 cbx_1__1__1_chanx_left_out[5]:2 cbx_1__1__1_chanx_left_out[4]:2 0.0001070368 +6 sb_1__1_:chanx_right_in[5] sb_1__1_:chanx_right_in[12] 0.0001047398 +7 cbx_1__1__1_chanx_left_out[5]:2 cbx_1__1__1_chanx_left_out[12]:2 0.0001047398 + +*RES +0 cbx_2__1_:chanx_left_out[5] cbx_1__1__1_chanx_left_out[5]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[5]:3 cbx_1__1__1_chanx_left_out[5]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[5]:2 sb_1__1_:chanx_right_in[5] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[9] 0.001429521 //LENGTH 7.660 LUMPCC 0.0003216677 DR + +*CONN +*I cbx_2__1_:chanx_left_out[9] O *L 0 *C 668.990 578.680 +*I sb_1__1_:chanx_right_in[9] I *L 0 *C 661.330 578.680 +*N cbx_1__1__1_chanx_left_out[9]:2 *C 667.519 578.680 +*N cbx_1__1__1_chanx_left_out[9]:3 *C 667.520 578.680 + +*CAP +0 cbx_2__1_:chanx_left_out[9] 0.0002071506 +1 sb_1__1_:chanx_right_in[9] 0.0003467757 +2 cbx_1__1__1_chanx_left_out[9]:2 0.0003467757 +3 cbx_1__1__1_chanx_left_out[9]:3 0.0002071506 +4 sb_1__1_:chanx_right_in[9] sb_1__1_:chanx_right_in[0] 2.790978e-05 +5 cbx_1__1__1_chanx_left_out[9]:2 cbx_1__1__1_chanx_left_out[0]:2 2.790978e-05 +6 sb_1__1_:chanx_right_in[9] sb_1__1_:chanx_right_out[14] 2.163164e-05 +7 cbx_1__1__1_chanx_left_out[9]:2 sb_1__1__0_chanx_right_out[14]:3 2.163164e-05 +8 sb_1__1_:chanx_right_in[9] sb_1__1_:chanx_right_out[18] 0.0001112924 +9 cbx_1__1__1_chanx_left_out[9]:2 sb_1__1__0_chanx_right_out[18]:3 0.0001112924 + +*RES +0 cbx_2__1_:chanx_left_out[9] cbx_1__1__1_chanx_left_out[9]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[9]:3 cbx_1__1__1_chanx_left_out[9]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[9]:2 sb_1__1_:chanx_right_in[9] 0.0009696101 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[12] 0.001508248 //LENGTH 7.660 LUMPCC 0.0003064614 DR + +*CONN +*I cbx_2__1_:chanx_left_out[12] O *L 0 *C 668.990 624.240 +*I sb_1__1_:chanx_right_in[12] I *L 0 *C 661.330 624.240 +*N cbx_1__1__1_chanx_left_out[12]:2 *C 667.519 624.240 +*N cbx_1__1__1_chanx_left_out[12]:3 *C 667.520 624.240 + +*CAP +0 cbx_2__1_:chanx_left_out[12] 0.0002216876 +1 sb_1__1_:chanx_right_in[12] 0.0003792058 +2 cbx_1__1__1_chanx_left_out[12]:2 0.0003792058 +3 cbx_1__1__1_chanx_left_out[12]:3 0.0002216876 +4 sb_1__1_:chanx_right_in[12] sb_1__1_:chanx_right_in[1] 4.849091e-05 +5 cbx_1__1__1_chanx_left_out[12]:2 cbx_1__1__1_chanx_left_out[1]:2 4.849091e-05 +6 sb_1__1_:chanx_right_in[12] sb_1__1_:chanx_right_in[5] 0.0001047398 +7 cbx_1__1__1_chanx_left_out[12]:2 cbx_1__1__1_chanx_left_out[5]:2 0.0001047398 + +*RES +0 cbx_2__1_:chanx_left_out[12] cbx_1__1__1_chanx_left_out[12]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[12]:3 cbx_1__1__1_chanx_left_out[12]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[12]:2 sb_1__1_:chanx_right_in[12] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[15] 0.001536316 //LENGTH 7.660 LUMPCC 0.0004478718 DR + +*CONN +*I cbx_2__1_:chanx_left_out[15] O *L 0 *C 668.990 584.800 +*I sb_1__1_:chanx_right_in[15] I *L 0 *C 661.330 584.800 +*N cbx_1__1__1_chanx_left_out[15]:2 *C 667.519 584.800 +*N cbx_1__1__1_chanx_left_out[15]:3 *C 667.520 584.800 + +*CAP +0 cbx_2__1_:chanx_left_out[15] 0.0002192392 +1 sb_1__1_:chanx_right_in[15] 0.0003249829 +2 cbx_1__1__1_chanx_left_out[15]:2 0.0003249829 +3 cbx_1__1__1_chanx_left_out[15]:3 0.0002192392 +4 sb_1__1_:chanx_right_in[15] sb_1__1_:chanx_right_in[2] 0.0001107108 +5 cbx_1__1__1_chanx_left_out[15]:2 cbx_1__1__1_chanx_left_out[2]:2 0.0001107108 +6 sb_1__1_:chanx_right_in[15] sb_1__1_:chanx_right_out[6] 0.0001132251 +7 cbx_1__1__1_chanx_left_out[15]:2 sb_1__1__0_chanx_right_out[6]:3 0.0001132251 + +*RES +0 cbx_2__1_:chanx_left_out[15] cbx_1__1__1_chanx_left_out[15]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[15]:3 cbx_1__1__1_chanx_left_out[15]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[15]:2 sb_1__1_:chanx_right_in[15] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[18] 0.006071969 //LENGTH 52.660 LUMPCC 0.0002878348 DR + +*CONN +*I cbx_2__1_:chanx_left_out[18] O *L 0 *C 672.060 630.970 +*I sb_1__1_:chanx_right_in[18] I *L 0 *C 661.330 592.960 +*N cbx_1__1__1_chanx_left_out[18]:2 *C 665.140 592.960 +*N cbx_1__1__1_chanx_left_out[18]:3 *C 665.160 592.967 +*N cbx_1__1__1_chanx_left_out[18]:4 *C 665.160 632.393 +*N cbx_1__1__1_chanx_left_out[18]:5 *C 665.180 632.400 +*N cbx_1__1__1_chanx_left_out[18]:6 *C 667.519 632.400 +*N cbx_1__1__1_chanx_left_out[18]:7 *C 667.520 632.400 +*N cbx_1__1__1_chanx_left_out[18]:8 *C 672.053 632.400 +*N cbx_1__1__1_chanx_left_out[18]:9 *C 672.060 632.343 + +*CAP +0 cbx_2__1_:chanx_left_out[18] 7.655821e-05 +1 sb_1__1_:chanx_right_in[18] 0.0002602841 +2 cbx_1__1__1_chanx_left_out[18]:2 0.0002602841 +3 cbx_1__1__1_chanx_left_out[18]:3 0.002153903 +4 cbx_1__1__1_chanx_left_out[18]:4 0.002153903 +5 cbx_1__1__1_chanx_left_out[18]:5 0.000127862 +6 cbx_1__1__1_chanx_left_out[18]:6 0.000127862 +7 cbx_1__1__1_chanx_left_out[18]:7 0.0002734603 +8 cbx_1__1__1_chanx_left_out[18]:8 0.0002734603 +9 cbx_1__1__1_chanx_left_out[18]:9 7.655821e-05 +10 cbx_2__1_:chanx_left_out[18] cbx_2__1_:top_grid_pin_24_[0] 1.868594e-05 +11 cbx_1__1__1_chanx_left_out[18]:9 grid_clb_2__2_:bottom_width_0_height_0__pin_24_[0] 1.868594e-05 +12 sb_1__1_:chanx_right_in[18] sb_1__1_:chanx_right_out[9] 6.794652e-05 +13 cbx_1__1__1_chanx_left_out[18]:2 sb_1__1__0_chanx_right_out[9]:3 6.794652e-05 +14 sb_1__1_:chanx_right_in[18] sb_1__1_:chanx_right_out[17] 5.728492e-05 +15 cbx_1__1__1_chanx_left_out[18]:2 sb_1__1__0_chanx_right_out[17]:3 5.728492e-05 + +*RES +0 cbx_2__1_:chanx_left_out[18] cbx_1__1__1_chanx_left_out[18]:9 0.001225446 +1 cbx_1__1__1_chanx_left_out[18]:9 cbx_1__1__1_chanx_left_out[18]:8 0.00341 +2 cbx_1__1__1_chanx_left_out[18]:8 cbx_1__1__1_chanx_left_out[18]:7 0.0007100917 +3 cbx_1__1__1_chanx_left_out[18]:5 cbx_1__1__1_chanx_left_out[18]:4 0.00341 +4 cbx_1__1__1_chanx_left_out[18]:4 cbx_1__1__1_chanx_left_out[18]:3 0.006176583 +5 cbx_1__1__1_chanx_left_out[18]:2 sb_1__1_:chanx_right_in[18] 0.0005969 +6 cbx_1__1__1_chanx_left_out[18]:3 cbx_1__1__1_chanx_left_out[18]:2 0.00341 +7 cbx_1__1__1_chanx_left_out[18]:7 cbx_1__1__1_chanx_left_out[18]:6 1e-05 +8 cbx_1__1__1_chanx_left_out[18]:6 cbx_1__1__1_chanx_left_out[18]:5 0.0003664433 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[3] 0.00160164 //LENGTH 7.660 LUMPCC 0.0003719851 DR + +*CONN +*I cbx_2__1_:chanx_right_out[3] O *L 0 *C 773.570 567.120 +*I sb_2__1_:chanx_left_in[3] I *L 0 *C 781.230 567.120 + +*CAP +0 cbx_2__1_:chanx_right_out[3] 0.0006148276 +1 sb_2__1_:chanx_left_in[3] 0.0006148276 +2 cbx_2__1_:chanx_right_out[3] cbx_2__1_:chanx_right_out[1] 9.299627e-05 +3 sb_2__1_:chanx_left_in[3] sb_2__1_:chanx_left_in[1] 9.299627e-05 +4 cbx_2__1_:chanx_right_out[3] sb_2__1__0_chanx_left_out[15]:7 9.299627e-05 +5 sb_2__1_:chanx_left_in[3] sb_2__1_:chanx_left_out[15] 9.299627e-05 + +*RES +0 cbx_2__1_:chanx_right_out[3] sb_2__1_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[6] 0.001463492 //LENGTH 7.660 LUMPCC 0.0003203179 DR + +*CONN +*I cbx_2__1_:chanx_right_out[6] O *L 0 *C 773.570 561.680 +*I sb_2__1_:chanx_left_in[6] I *L 0 *C 781.230 561.680 + +*CAP +0 cbx_2__1_:chanx_right_out[6] 0.0005715869 +1 sb_2__1_:chanx_left_in[6] 0.0005715869 +2 cbx_2__1_:chanx_right_out[6] cbx_1__1__1_chanx_right_out[19]:2 0.0001063349 +3 sb_2__1_:chanx_left_in[6] sb_2__1_:chanx_left_in[19] 0.0001063349 +4 cbx_2__1_:chanx_right_out[6] cbx_2__1_:chanx_right_in[16] 5.382402e-05 +5 sb_2__1_:chanx_left_in[6] sb_2__1_:chanx_left_out[16] 5.382402e-05 + +*RES +0 cbx_2__1_:chanx_right_out[6] sb_2__1_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[9] 0.001434518 //LENGTH 7.660 LUMPCC 0.0003183331 DR + +*CONN +*I cbx_2__1_:chanx_right_out[9] O *L 0 *C 773.570 599.760 +*I sb_2__1_:chanx_left_in[9] I *L 0 *C 781.230 599.760 + +*CAP +0 cbx_2__1_:chanx_right_out[9] 0.0005580925 +1 sb_2__1_:chanx_left_in[9] 0.0005580925 +2 cbx_2__1_:chanx_right_out[9] cbx_2__1_:chanx_right_in[3] 3.885734e-05 +3 sb_2__1_:chanx_left_in[9] sb_2__1_:chanx_left_out[3] 3.885734e-05 +4 cbx_2__1_:chanx_right_out[9] cbx_2__1_:chanx_right_in[18] 0.0001203092 +5 sb_2__1_:chanx_left_in[9] sb_2__1_:chanx_left_out[18] 0.0001203092 + +*RES +0 cbx_2__1_:chanx_right_out[9] sb_2__1_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[12] 0.001587959 //LENGTH 7.660 LUMPCC 0.0003962806 DR + +*CONN +*I cbx_2__1_:chanx_right_out[12] O *L 0 *C 773.570 625.600 +*I sb_2__1_:chanx_left_in[12] I *L 0 *C 781.230 625.600 + +*CAP +0 cbx_2__1_:chanx_right_out[12] 0.000595839 +1 sb_2__1_:chanx_left_in[12] 0.000595839 +2 cbx_2__1_:chanx_right_out[12] cbx_2__1_:chanx_right_in[11] 9.562019e-05 +3 sb_2__1_:chanx_left_in[12] sb_2__1_:chanx_left_out[11] 9.562019e-05 +4 cbx_2__1_:chanx_right_out[12] cbx_2__1_:chanx_right_in[13] 0.0001025201 +5 sb_2__1_:chanx_left_in[12] sb_2__1_:chanx_left_out[13] 0.0001025201 + +*RES +0 cbx_2__1_:chanx_right_out[12] sb_2__1_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[15] 0.00154886 //LENGTH 7.660 LUMPCC 0.000265193 DR + +*CONN +*I cbx_2__1_:chanx_right_out[15] O *L 0 *C 773.570 605.200 +*I sb_2__1_:chanx_left_in[15] I *L 0 *C 781.230 605.200 + +*CAP +0 cbx_2__1_:chanx_right_out[15] 0.0006418333 +1 sb_2__1_:chanx_left_in[15] 0.0006418333 +2 cbx_2__1_:chanx_right_out[15] cbx_2__1_:chanx_right_out[0] 9.428097e-05 +3 sb_2__1_:chanx_left_in[15] sb_2__1_:chanx_left_in[0] 9.428097e-05 +4 cbx_2__1_:chanx_right_out[15] cbx_2__1_:chanx_right_in[4] 3.831551e-05 +5 sb_2__1_:chanx_left_in[15] sb_2__1_:chanx_left_out[4] 3.831551e-05 + +*RES +0 cbx_2__1_:chanx_right_out[15] sb_2__1_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[18] 0.006203612 //LENGTH 47.660 LUMPCC 0.001456447 DR + +*CONN +*I cbx_2__1_:chanx_right_out[18] O *L 0 *C 771.420 630.970 +*I sb_2__1_:chanx_left_in[18] I *L 0 *C 781.230 595.680 +*N cbx_1__1__1_chanx_right_out[18]:2 *C 779.260 595.680 +*N cbx_1__1__1_chanx_right_out[18]:3 *C 779.240 595.688 +*N cbx_1__1__1_chanx_right_out[18]:4 *C 779.240 631.712 +*N cbx_1__1__1_chanx_right_out[18]:5 *C 779.220 631.720 +*N cbx_1__1__1_chanx_right_out[18]:6 *C 771.428 631.720 +*N cbx_1__1__1_chanx_right_out[18]:7 *C 771.420 631.663 + +*CAP +0 cbx_2__1_:chanx_right_out[18] 6.144747e-05 +1 sb_2__1_:chanx_left_in[18] 0.0002676748 +2 cbx_1__1__1_chanx_right_out[18]:2 0.0002676748 +3 cbx_1__1__1_chanx_right_out[18]:3 0.001579254 +4 cbx_1__1__1_chanx_right_out[18]:4 0.001579254 +5 cbx_1__1__1_chanx_right_out[18]:5 0.0004652063 +6 cbx_1__1__1_chanx_right_out[18]:6 0.0004652063 +7 cbx_1__1__1_chanx_right_out[18]:7 6.144747e-05 +8 cbx_1__1__1_chanx_right_out[18]:3 direct_interc_4_out[0]:6 0.0007282233 +9 cbx_1__1__1_chanx_right_out[18]:4 direct_interc_4_out[0]:7 0.0007282233 + +*RES +0 cbx_2__1_:chanx_right_out[18] cbx_1__1__1_chanx_right_out[18]:7 0.0006183035 +1 cbx_1__1__1_chanx_right_out[18]:2 sb_2__1_:chanx_left_in[18] 0.0003086333 +2 cbx_1__1__1_chanx_right_out[18]:3 cbx_1__1__1_chanx_right_out[18]:2 0.00341 +3 cbx_1__1__1_chanx_right_out[18]:5 cbx_1__1__1_chanx_right_out[18]:4 0.00341 +4 cbx_1__1__1_chanx_right_out[18]:4 cbx_1__1__1_chanx_right_out[18]:3 0.005643916 +5 cbx_1__1__1_chanx_right_out[18]:7 cbx_1__1__1_chanx_right_out[18]:6 0.00341 +6 cbx_1__1__1_chanx_right_out[18]:6 cbx_1__1__1_chanx_right_out[18]:5 0.001220825 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_17_[0] 0.00128901 //LENGTH 11.020 LUMPCC 0.0006314216 DR + +*CONN +*I cbx_2__1_:top_grid_pin_17_[0] O *L 0 *C 704.720 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] I *L 0 *C 704.720 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_17_[0] 0.0003287942 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 0.0003287942 +2 cbx_2__1_:top_grid_pin_17_[0] cbx_2__1_:top_grid_pin_18_[0] 0.0001447094 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] 0.0001447094 +4 cbx_2__1_:top_grid_pin_17_[0] cbx_2__1_:top_grid_pin_19_[0] 7.866155e-05 +5 cbx_2__1_:top_grid_pin_17_[0] cbx_1__1__1_top_grid_pin_19_[0]:4 7.687044e-05 +6 cbx_2__1_:top_grid_pin_17_[0] cbx_1__1__1_top_grid_pin_19_[0]:2 1.546943e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_19_[0] 1.546943e-05 +8 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] cbx_1__1__1_top_grid_pin_19_[0]:3 7.687044e-05 +9 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] cbx_1__1__1_top_grid_pin_19_[0]:5 7.866155e-05 + +*RES +0 cbx_2__1_:top_grid_pin_17_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_20_[0] 0.001080763 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__1_:top_grid_pin_20_[0] O *L 0 *C 726.340 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_20_[0] I *L 0 *C 726.340 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_20_[0] 0.0005403816 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_20_[0] 0.0005403816 + +*RES +0 cbx_2__1_:top_grid_pin_20_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_20_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_22_[0] 0.001367748 //LENGTH 12.500 LUMPCC 0.0003496864 DR + +*CONN +*I cbx_2__1_:top_grid_pin_22_[0] O *L 0 *C 701.960 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_22_[0] I *L 0 *C 701.960 641.990 +*N cbx_1__1__1_top_grid_pin_22_[0]:2 *C 701.960 639.200 +*N cbx_1__1__1_top_grid_pin_22_[0]:3 *C 702.420 639.200 +*N cbx_1__1__1_top_grid_pin_22_[0]:4 *C 702.420 636.480 +*N cbx_1__1__1_top_grid_pin_22_[0]:5 *C 701.960 636.480 + +*CAP +0 cbx_2__1_:top_grid_pin_22_[0] 0.0001876122 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_22_[0] 0.0001611897 +2 cbx_1__1__1_top_grid_pin_22_[0]:2 0.0001889038 +3 cbx_1__1__1_top_grid_pin_22_[0]:3 0.0001345876 +4 cbx_1__1__1_top_grid_pin_22_[0]:4 0.0001325146 +5 cbx_1__1__1_top_grid_pin_22_[0]:5 0.0002132532 +6 cbx_2__1_:top_grid_pin_22_[0] cbx_2__1_:top_grid_pin_16_[0] 8.090731e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_22_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 1.554563e-05 +8 cbx_1__1__1_top_grid_pin_22_[0]:5 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 8.090731e-05 +9 cbx_1__1__1_top_grid_pin_22_[0]:4 cbx_2__1_:top_grid_pin_16_[0] 7.839025e-05 +10 cbx_1__1__1_top_grid_pin_22_[0]:2 cbx_2__1_:top_grid_pin_16_[0] 1.554563e-05 +11 cbx_1__1__1_top_grid_pin_22_[0]:3 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 7.839025e-05 + +*RES +0 cbx_2__1_:top_grid_pin_22_[0] cbx_1__1__1_top_grid_pin_22_[0]:5 0.004919643 +1 cbx_1__1__1_top_grid_pin_22_[0]:5 cbx_1__1__1_top_grid_pin_22_[0]:4 0.0004107143 +2 cbx_1__1__1_top_grid_pin_22_[0]:4 cbx_1__1__1_top_grid_pin_22_[0]:3 0.002428572 +3 cbx_1__1__1_top_grid_pin_22_[0]:2 grid_clb_2__2_:bottom_width_0_height_0__pin_22_[0] 0.002491071 +4 cbx_1__1__1_top_grid_pin_22_[0]:3 cbx_1__1__1_top_grid_pin_22_[0]:2 0.0004107143 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_26_[0] 0.001248204 //LENGTH 11.020 LUMPCC 0.0005730883 DR + +*CONN +*I cbx_2__1_:top_grid_pin_26_[0] O *L 0 *C 682.180 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] I *L 0 *C 682.180 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_26_[0] 0.0003375577 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] 0.0003375577 +2 cbx_2__1_:top_grid_pin_26_[0] cbx_2__1_:top_grid_pin_25_[0] 0.0001432721 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_25_[0] 0.0001432721 +4 cbx_2__1_:top_grid_pin_26_[0] cbx_2__1_:top_grid_pin_27_[0] 0.0001432721 +5 grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] 0.0001432721 + +*RES +0 cbx_2__1_:top_grid_pin_26_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_30_[0] 0.001394439 //LENGTH 12.500 LUMPCC 0.0003394816 DR + +*CONN +*I cbx_2__1_:top_grid_pin_30_[0] O *L 0 *C 745.200 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_30_[0] I *L 0 *C 745.200 641.990 +*N cbx_1__1__1_top_grid_pin_30_[0]:2 *C 745.200 639.200 +*N cbx_1__1__1_top_grid_pin_30_[0]:3 *C 744.740 639.200 +*N cbx_1__1__1_top_grid_pin_30_[0]:4 *C 744.740 636.480 +*N cbx_1__1__1_top_grid_pin_30_[0]:5 *C 745.200 636.480 + +*CAP +0 cbx_2__1_:top_grid_pin_30_[0] 0.0002004034 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_30_[0] 0.0001672436 +2 cbx_1__1__1_top_grid_pin_30_[0]:2 0.0001961176 +3 cbx_1__1__1_top_grid_pin_30_[0]:3 0.0001328252 +4 cbx_1__1__1_top_grid_pin_30_[0]:4 0.0001309579 +5 cbx_1__1__1_top_grid_pin_30_[0]:5 0.00022741 +6 cbx_2__1_:top_grid_pin_30_[0] cbx_2__1_:top_grid_pin_31_[0] 7.782238e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_30_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 1.533745e-05 +8 cbx_1__1__1_top_grid_pin_30_[0]:4 cbx_2__1_:top_grid_pin_31_[0] 7.658094e-05 +9 cbx_1__1__1_top_grid_pin_30_[0]:3 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 7.658094e-05 +10 cbx_1__1__1_top_grid_pin_30_[0]:5 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 7.782238e-05 +11 cbx_1__1__1_top_grid_pin_30_[0]:2 cbx_2__1_:top_grid_pin_31_[0] 1.533745e-05 + +*RES +0 cbx_2__1_:top_grid_pin_30_[0] cbx_1__1__1_top_grid_pin_30_[0]:5 0.004919643 +1 cbx_1__1__1_top_grid_pin_30_[0]:4 cbx_1__1__1_top_grid_pin_30_[0]:3 0.002428572 +2 cbx_1__1__1_top_grid_pin_30_[0]:3 cbx_1__1__1_top_grid_pin_30_[0]:2 0.0004107143 +3 cbx_1__1__1_top_grid_pin_30_[0]:5 cbx_1__1__1_top_grid_pin_30_[0]:4 0.0004107143 +4 cbx_1__1__1_top_grid_pin_30_[0]:2 grid_clb_2__2_:bottom_width_0_height_0__pin_30_[0] 0.002491071 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[1] 0.001295663 //LENGTH 7.660 LUMPCC 0.0006530824 DR + +*CONN +*I cbx_1__2_:chanx_left_out[1] O *L 0 *C 407.710 845.920 +*I sb_0__2_:chanx_right_in[1] I *L 0 *C 400.050 845.920 + +*CAP +0 cbx_1__2_:chanx_left_out[1] 0.0003212901 +1 sb_0__2_:chanx_right_in[1] 0.0003212901 +2 cbx_1__2_:chanx_left_out[1] cbx_1__2_:chanx_left_out[11] 0.0001633815 +3 sb_0__2_:chanx_right_in[1] sb_0__2_:chanx_right_in[11] 0.0001633815 +4 cbx_1__2_:chanx_left_out[1] cbx_1__2_:chanx_left_out[15] 0.0001631597 +5 sb_0__2_:chanx_right_in[1] sb_0__2_:chanx_right_in[15] 0.0001631597 + +*RES +0 cbx_1__2_:chanx_left_out[1] sb_0__2_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[5] 0.001303575 //LENGTH 7.660 LUMPCC 0.0006582855 DR + +*CONN +*I cbx_1__2_:chanx_left_out[5] O *L 0 *C 407.710 851.360 +*I sb_0__2_:chanx_right_in[5] I *L 0 *C 400.050 851.360 + +*CAP +0 cbx_1__2_:chanx_left_out[5] 0.0003226447 +1 sb_0__2_:chanx_right_in[5] 0.0003226447 +2 cbx_1__2_:chanx_left_out[5] cbx_1__2_:chanx_left_out[17] 0.0001646661 +3 sb_0__2_:chanx_right_in[5] sb_0__2_:chanx_right_in[17] 0.0001646661 +4 cbx_1__2_:chanx_left_out[5] cbx_1__2_:chanx_left_in[16] 0.0001644766 +5 sb_0__2_:chanx_right_in[5] sb_0__2_:chanx_right_out[16] 0.0001644766 + +*RES +0 cbx_1__2_:chanx_left_out[5] sb_0__2_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[9] 0.001304118 //LENGTH 7.660 LUMPCC 0.0006396779 DR + +*CONN +*I cbx_1__2_:chanx_left_out[9] O *L 0 *C 407.710 824.160 +*I sb_0__2_:chanx_right_in[9] I *L 0 *C 400.050 824.160 + +*CAP +0 cbx_1__2_:chanx_left_out[9] 0.0003322198 +1 sb_0__2_:chanx_right_in[9] 0.0003322198 +2 cbx_1__2_:chanx_left_out[9] cbx_1__2_:chanx_left_out[4] 0.0001599195 +3 sb_0__2_:chanx_right_in[9] sb_0__2_:chanx_right_in[4] 0.0001599195 +4 cbx_1__2_:chanx_left_out[9] cbx_1__2_:chanx_left_out[13] 0.0001599195 +5 sb_0__2_:chanx_right_in[9] sb_0__2_:chanx_right_in[13] 0.0001599195 + +*RES +0 cbx_1__2_:chanx_left_out[9] sb_0__2_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[13] 0.00122424 //LENGTH 7.660 LUMPCC 0.0004502962 DR + +*CONN +*I cbx_1__2_:chanx_left_out[13] O *L 0 *C 407.710 825.520 +*I sb_0__2_:chanx_right_in[13] I *L 0 *C 400.050 825.520 + +*CAP +0 cbx_1__2_:chanx_left_out[13] 0.000386972 +1 sb_0__2_:chanx_right_in[13] 0.000386972 +2 cbx_1__2_:chanx_left_out[13] cbx_1__2_:chanx_left_out[9] 0.0001599195 +3 sb_0__2_:chanx_right_in[13] sb_0__2_:chanx_right_in[9] 0.0001599195 +4 cbx_1__2_:chanx_left_out[13] cbx_1__2_:chanx_left_out[18] 6.522864e-05 +5 sb_0__2_:chanx_right_in[13] sb_0__2_:chanx_right_in[18] 6.522864e-05 + +*RES +0 cbx_1__2_:chanx_left_out[13] sb_0__2_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[17] 0.00121193 //LENGTH 7.660 LUMPCC 0.0004669803 DR + +*CONN +*I cbx_1__2_:chanx_left_out[17] O *L 0 *C 407.710 850.000 +*I sb_0__2_:chanx_right_in[17] I *L 0 *C 400.050 850.000 + +*CAP +0 cbx_1__2_:chanx_left_out[17] 0.000372475 +1 sb_0__2_:chanx_right_in[17] 0.000372475 +2 cbx_1__2_:chanx_left_out[17] cbx_1__2_:chanx_left_out[5] 0.0001646661 +3 sb_0__2_:chanx_right_in[17] sb_0__2_:chanx_right_in[5] 0.0001646661 +4 cbx_1__2_:chanx_left_out[17] cbx_1__2_:chanx_left_out[11] 6.882404e-05 +5 sb_0__2_:chanx_right_in[17] sb_0__2_:chanx_right_in[11] 6.882404e-05 + +*RES +0 cbx_1__2_:chanx_left_out[17] sb_0__2_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[0] 0.001319468 //LENGTH 7.660 LUMPCC 0.0003868155 DR + +*CONN +*I cbx_1__2_:chanx_right_out[0] O *L 0 *C 512.290 828.240 +*I sb_1__2_:chanx_left_in[0] I *L 0 *C 519.950 828.240 + +*CAP +0 cbx_1__2_:chanx_right_out[0] 0.0004663262 +1 sb_1__2_:chanx_left_in[0] 0.0004663262 +2 cbx_1__2_:chanx_right_out[0] cbx_1__2_:chanx_right_out[1] 5.062331e-05 +3 sb_1__2_:chanx_left_in[0] sb_1__2_:chanx_left_in[1] 5.062331e-05 +4 cbx_1__2_:chanx_right_out[0] cbx_1__2_:chanx_right_out[18] 0.0001427845 +5 sb_1__2_:chanx_left_in[0] sb_1__2_:chanx_left_in[18] 0.0001427845 + +*RES +0 cbx_1__2_:chanx_right_out[0] sb_1__2_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[3] 0.001302995 //LENGTH 7.660 LUMPCC 0.0003965543 DR + +*CONN +*I cbx_1__2_:chanx_right_out[3] O *L 0 *C 512.290 850.000 +*I sb_1__2_:chanx_left_in[3] I *L 0 *C 519.950 850.000 + +*CAP +0 cbx_1__2_:chanx_right_out[3] 0.0004532204 +1 sb_1__2_:chanx_left_in[3] 0.0004532204 +2 cbx_1__2_:chanx_right_out[3] cbx_1__2_:chanx_right_out[11] 4.900574e-05 +3 sb_1__2_:chanx_left_in[3] sb_1__2_:chanx_left_in[11] 4.900574e-05 +4 cbx_1__2_:chanx_right_out[3] cbx_1__2_:chanx_right_out[14] 0.0001492714 +5 sb_1__2_:chanx_left_in[3] sb_1__2_:chanx_left_in[14] 0.0001492714 + +*RES +0 cbx_1__2_:chanx_right_out[3] sb_1__2_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[6] 0.001308873 //LENGTH 7.660 LUMPCC 0.0002820931 DR + +*CONN +*I cbx_1__2_:chanx_right_out[6] O *L 0 *C 512.290 820.080 +*I sb_1__2_:chanx_left_in[6] I *L 0 *C 519.950 820.080 + +*CAP +0 cbx_1__2_:chanx_right_out[6] 0.0005133901 +1 sb_1__2_:chanx_left_in[6] 0.0005133901 +2 cbx_1__2_:chanx_right_out[6] cbx_1__2_:chanx_right_out[12] 0.0001410465 +3 sb_1__2_:chanx_left_in[6] sb_1__2_:chanx_left_in[12] 0.0001410465 + +*RES +0 cbx_1__2_:chanx_right_out[6] sb_1__2_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[8] 0.001396153 //LENGTH 7.660 LUMPCC 0.0005656857 DR + +*CONN +*I cbx_1__2_:chanx_right_out[8] O *L 0 *C 512.290 864.960 +*I sb_1__2_:chanx_left_in[8] I *L 0 *C 519.950 864.960 + +*CAP +0 cbx_1__2_:chanx_right_out[8] 0.0004152338 +1 sb_1__2_:chanx_left_in[8] 0.0004152338 +2 cbx_1__2_:chanx_right_out[8] cbx_1__2_:chanx_right_out[13] 0.0001423629 +3 sb_1__2_:chanx_left_in[8] sb_1__2_:chanx_left_in[13] 0.0001423629 +4 cbx_1__2_:chanx_right_out[8] cbx_1__2_:ccff_head[0] 0.0001404799 +5 sb_1__2_:chanx_left_in[8] sb_1__2_:ccff_tail[0] 0.0001404799 + +*RES +0 cbx_1__2_:chanx_right_out[8] sb_1__2_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[11] 0.00131505 //LENGTH 7.660 LUMPCC 0.0003957156 DR + +*CONN +*I cbx_1__2_:chanx_right_out[11] O *L 0 *C 512.290 852.720 +*I sb_1__2_:chanx_left_in[11] I *L 0 *C 519.950 852.720 + +*CAP +0 cbx_1__2_:chanx_right_out[11] 0.0004596674 +1 sb_1__2_:chanx_left_in[11] 0.0004596674 +2 cbx_1__2_:chanx_right_out[11] cbx_1__2_:chanx_right_out[3] 4.900574e-05 +3 sb_1__2_:chanx_left_in[11] sb_1__2_:chanx_left_in[3] 4.900574e-05 +4 cbx_1__2_:chanx_right_out[11] cbx_1__2_:chanx_right_in[9] 0.000148852 +5 sb_1__2_:chanx_left_in[11] sb_1__2_:chanx_left_out[9] 0.000148852 + +*RES +0 cbx_1__2_:chanx_right_out[11] sb_1__2_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[14] 0.001356098 //LENGTH 7.660 LUMPCC 0.0005981053 DR + +*CONN +*I cbx_1__2_:chanx_right_out[14] O *L 0 *C 512.290 848.640 +*I sb_1__2_:chanx_left_in[14] I *L 0 *C 519.950 848.640 + +*CAP +0 cbx_1__2_:chanx_right_out[14] 0.0003789963 +1 sb_1__2_:chanx_left_in[14] 0.0003789963 +2 cbx_1__2_:chanx_right_out[14] cbx_1__2_:chanx_right_out[3] 0.0001492714 +3 sb_1__2_:chanx_left_in[14] sb_1__2_:chanx_left_in[3] 0.0001492714 +4 cbx_1__2_:chanx_right_out[14] cbx_1__2_:chanx_right_in[4] 0.0001497812 +5 sb_1__2_:chanx_left_in[14] sb_1__2_:chanx_left_out[4] 0.0001497812 + +*RES +0 cbx_1__2_:chanx_right_out[14] sb_1__2_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[18] 0.001386122 //LENGTH 7.660 LUMPCC 0.0005694385 DR + +*CONN +*I cbx_1__2_:chanx_right_out[18] O *L 0 *C 512.290 826.880 +*I sb_1__2_:chanx_left_in[18] I *L 0 *C 519.950 826.880 + +*CAP +0 cbx_1__2_:chanx_right_out[18] 0.0004083417 +1 sb_1__2_:chanx_left_in[18] 0.0004083417 +2 cbx_1__2_:chanx_right_out[18] cbx_1__2_:chanx_right_out[0] 0.0001427845 +3 sb_1__2_:chanx_left_in[18] sb_1__2_:chanx_left_in[0] 0.0001427845 +4 cbx_1__2_:chanx_right_out[18] cbx_1__2_:chanx_right_out[10] 0.0001419348 +5 sb_1__2_:chanx_left_in[18] sb_1__2_:chanx_left_in[10] 0.0001419348 + +*RES +0 cbx_1__2_:chanx_right_out[18] sb_1__2_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[0] 0.003413685 //LENGTH 28.620 LUMPCC 0.0003000055 DR + +*CONN +*I cbx_2__2_:chanx_left_out[0] O *L 0 *C 671.140 892.090 +*I sb_1__2_:chanx_right_in[0] I *L 0 *C 661.330 875.840 +*N cbx_1__2__1_chanx_left_out[0]:2 *C 665.140 875.840 +*N cbx_1__2__1_chanx_left_out[0]:3 *C 665.160 875.848 +*N cbx_1__2__1_chanx_left_out[0]:4 *C 665.160 891.519 +*N cbx_1__2__1_chanx_left_out[0]:5 *C 665.160 891.520 +*N cbx_1__2__1_chanx_left_out[0]:6 *C 665.160 892.833 +*N cbx_1__2__1_chanx_left_out[0]:7 *C 665.180 892.840 +*N cbx_1__2__1_chanx_left_out[0]:8 *C 667.519 892.840 +*N cbx_1__2__1_chanx_left_out[0]:9 *C 667.520 892.840 +*N cbx_1__2__1_chanx_left_out[0]:10 *C 671.133 892.840 +*N cbx_1__2__1_chanx_left_out[0]:11 *C 671.140 892.783 + +*CAP +0 cbx_2__2_:chanx_left_out[0] 5.358395e-05 +1 sb_1__2_:chanx_right_in[0] 0.0002173912 +2 cbx_1__2__1_chanx_left_out[0]:2 0.0002173912 +3 cbx_1__2__1_chanx_left_out[0]:3 0.0008506469 +4 cbx_1__2__1_chanx_left_out[0]:4 0.0008506469 +5 cbx_1__2__1_chanx_left_out[0]:5 6.357172e-05 +6 cbx_1__2__1_chanx_left_out[0]:6 6.357172e-05 +7 cbx_1__2__1_chanx_left_out[0]:7 0.0001178714 +8 cbx_1__2__1_chanx_left_out[0]:8 0.0001178714 +9 cbx_1__2__1_chanx_left_out[0]:9 0.0002537747 +10 cbx_1__2__1_chanx_left_out[0]:10 0.0002537747 +11 cbx_1__2__1_chanx_left_out[0]:11 5.358395e-05 +12 sb_1__2_:chanx_right_in[0] sb_1__2_:chanx_right_out[8] 7.500139e-05 +13 cbx_1__2__1_chanx_left_out[0]:2 sb_1__2__0_chanx_right_out[8]:3 7.500139e-05 +14 sb_1__2_:chanx_right_in[0] sb_1__2_:chanx_right_out[17] 7.500139e-05 +15 cbx_1__2__1_chanx_left_out[0]:2 sb_1__2__0_chanx_right_out[17]:3 7.500139e-05 + +*RES +0 cbx_2__2_:chanx_left_out[0] cbx_1__2__1_chanx_left_out[0]:11 0.0006183035 +1 cbx_1__2__1_chanx_left_out[0]:11 cbx_1__2__1_chanx_left_out[0]:10 0.00341 +2 cbx_1__2__1_chanx_left_out[0]:10 cbx_1__2__1_chanx_left_out[0]:9 0.0005659583 +3 cbx_1__2__1_chanx_left_out[0]:7 cbx_1__2__1_chanx_left_out[0]:6 0.00341 +4 cbx_1__2__1_chanx_left_out[0]:6 cbx_1__2__1_chanx_left_out[0]:5 0.000205625 +5 cbx_1__2__1_chanx_left_out[0]:2 sb_1__2_:chanx_right_in[0] 0.0005969 +6 cbx_1__2__1_chanx_left_out[0]:3 cbx_1__2__1_chanx_left_out[0]:2 0.00341 +7 cbx_1__2__1_chanx_left_out[0]:9 cbx_1__2__1_chanx_left_out[0]:8 1e-05 +8 cbx_1__2__1_chanx_left_out[0]:8 cbx_1__2__1_chanx_left_out[0]:7 0.0003664433 +9 cbx_1__2__1_chanx_left_out[0]:5 cbx_1__2__1_chanx_left_out[0]:4 1e-05 +10 cbx_1__2__1_chanx_left_out[0]:4 cbx_1__2__1_chanx_left_out[0]:3 0.002455201 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[6] 0.001306931 //LENGTH 7.660 LUMPCC 0.0001645426 DR + +*CONN +*I cbx_2__2_:chanx_left_out[6] O *L 0 *C 668.990 820.080 +*I sb_1__2_:chanx_right_in[6] I *L 0 *C 661.330 820.080 +*N cbx_1__2__1_chanx_left_out[6]:2 *C 667.519 820.080 +*N cbx_1__2__1_chanx_left_out[6]:3 *C 667.520 820.080 + +*CAP +0 cbx_2__2_:chanx_left_out[6] 0.0001993109 +1 sb_1__2_:chanx_right_in[6] 0.000371883 +2 cbx_1__2__1_chanx_left_out[6]:2 0.000371883 +3 cbx_1__2__1_chanx_left_out[6]:3 0.0001993109 +4 sb_1__2_:chanx_right_in[6] sb_1__2_:chanx_right_in[4] 5.142411e-05 +5 cbx_1__2__1_chanx_left_out[6]:2 cbx_1__2__1_chanx_left_out[4]:2 5.142411e-05 +6 sb_1__2_:chanx_right_in[6] ctsbuf_net_312:19 3.084719e-05 +7 cbx_1__2__1_chanx_left_out[6]:2 ctsbuf_net_312:18 3.084719e-05 + +*RES +0 cbx_2__2_:chanx_left_out[6] cbx_1__2__1_chanx_left_out[6]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[6]:3 cbx_1__2__1_chanx_left_out[6]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[6]:2 sb_1__2_:chanx_right_in[6] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[10] 0.001382804 //LENGTH 7.660 LUMPCC 0.0003971866 DR + +*CONN +*I cbx_2__2_:chanx_left_out[10] O *L 0 *C 668.990 869.040 +*I sb_1__2_:chanx_right_in[10] I *L 0 *C 661.330 869.040 +*N cbx_1__2__1_chanx_left_out[10]:2 *C 667.519 869.040 +*N cbx_1__2__1_chanx_left_out[10]:3 *C 667.520 869.040 + +*CAP +0 cbx_2__2_:chanx_left_out[10] 0.0002006812 +1 sb_1__2_:chanx_right_in[10] 0.0002921277 +2 cbx_1__2__1_chanx_left_out[10]:2 0.0002921277 +3 cbx_1__2__1_chanx_left_out[10]:3 0.0002006812 +4 sb_1__2_:chanx_right_in[10] sb_1__2_:chanx_right_out[3] 6.249905e-05 +5 cbx_1__2__1_chanx_left_out[10]:2 sb_1__2__0_chanx_right_out[3]:3 6.249905e-05 +6 cbx_2__2_:chanx_left_out[10] cbx_2__2_:chanx_left_in[4] 6.577123e-06 +7 sb_1__2_:chanx_right_in[10] sb_1__2_:chanx_right_out[4] 0.0001295171 +8 cbx_1__2__1_chanx_left_out[10]:3 sb_1__2__0_chanx_right_out[4]:2 6.577123e-06 +9 cbx_1__2__1_chanx_left_out[10]:2 sb_1__2__0_chanx_right_out[4]:3 0.0001295171 + +*RES +0 cbx_2__2_:chanx_left_out[10] cbx_1__2__1_chanx_left_out[10]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[10]:3 cbx_1__2__1_chanx_left_out[10]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[10]:2 sb_1__2_:chanx_right_in[10] 0.00096961 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[14] 0.004150295 //LENGTH 33.640 LUMPCC 0.0009492796 DR + +*CONN +*I cbx_2__2_:chanx_left_out[14] O *L 0 *C 673.440 816.070 +*I sb_1__2_:chanx_right_in[14] I *L 0 *C 661.330 832.320 +*N cbx_1__2__1_chanx_left_out[14]:2 *C 665.140 832.320 +*N cbx_1__2__1_chanx_left_out[14]:3 *C 665.160 832.312 +*N cbx_1__2__1_chanx_left_out[14]:4 *C 665.160 813.968 +*N cbx_1__2__1_chanx_left_out[14]:5 *C 665.180 813.960 +*N cbx_1__2__1_chanx_left_out[14]:6 *C 667.519 813.960 +*N cbx_1__2__1_chanx_left_out[14]:7 *C 667.520 813.960 +*N cbx_1__2__1_chanx_left_out[14]:8 *C 673.433 813.960 +*N cbx_1__2__1_chanx_left_out[14]:9 *C 673.440 814.018 + +*CAP +0 cbx_2__2_:chanx_left_out[14] 0.0001122926 +1 sb_1__2_:chanx_right_in[14] 0.0002824696 +2 cbx_1__2__1_chanx_left_out[14]:2 0.0002824696 +3 cbx_1__2__1_chanx_left_out[14]:3 0.0009734936 +4 cbx_1__2__1_chanx_left_out[14]:4 0.0009734936 +5 cbx_1__2__1_chanx_left_out[14]:5 5.467594e-05 +6 cbx_1__2__1_chanx_left_out[14]:6 5.467594e-05 +7 cbx_1__2__1_chanx_left_out[14]:7 0.0001775759 +8 cbx_1__2__1_chanx_left_out[14]:8 0.0001775758 +9 cbx_1__2__1_chanx_left_out[14]:9 0.0001122926 +10 cbx_1__2__1_chanx_left_out[14]:8 Test_en[0]:16 5.255961e-05 +11 cbx_1__2__1_chanx_left_out[14]:5 Test_en[0]:13 2.739735e-05 +12 cbx_1__2__1_chanx_left_out[14]:7 Test_en[0]:15 5.255961e-05 +13 cbx_1__2__1_chanx_left_out[14]:6 Test_en[0]:14 2.739735e-05 +14 sb_1__2_:chanx_right_in[14] sb_1__2_:chanx_right_out[9] 5.75082e-05 +15 cbx_1__2__1_chanx_left_out[14]:2 sb_1__2__0_chanx_right_out[9]:3 5.75082e-05 +16 sb_1__2_:chanx_right_in[14] sb_1__2_:chanx_right_out[12] 5.75082e-05 +17 cbx_1__2__1_chanx_left_out[14]:2 sb_1__2__0_chanx_right_out[12]:3 5.75082e-05 +18 cbx_2__2_:chanx_left_out[14] cbx_2__2_:prog_clk[0] 3.167166e-06 +19 cbx_2__2_:chanx_left_out[14] ctsbuf_net_312:16 6.1162e-06 +20 cbx_1__2__1_chanx_left_out[14]:9 ctsbuf_net_312:15 3.167166e-06 +21 cbx_1__2__1_chanx_left_out[14]:9 ctsbuf_net_312:14 6.1162e-06 +22 cbx_1__2__1_chanx_left_out[14]:8 ctsbuf_net_312:16 9.952665e-05 +23 cbx_1__2__1_chanx_left_out[14]:8 ctsbuf_net_312:13 9.835635e-05 +24 cbx_1__2__1_chanx_left_out[14]:5 ctsbuf_net_312:19 6.56738e-05 +25 cbx_1__2__1_chanx_left_out[14]:4 ctsbuf_net_312:20 6.826302e-06 +26 cbx_1__2__1_chanx_left_out[14]:3 ctsbuf_net_312:21 6.826302e-06 +27 cbx_1__2__1_chanx_left_out[14]:7 ctsbuf_net_312:14 9.835635e-05 +28 cbx_1__2__1_chanx_left_out[14]:7 ctsbuf_net_312:17 9.952665e-05 +29 cbx_1__2__1_chanx_left_out[14]:6 ctsbuf_net_312:18 6.56738e-05 + +*RES +0 cbx_2__2_:chanx_left_out[14] cbx_1__2__1_chanx_left_out[14]:9 0.001832589 +1 cbx_1__2__1_chanx_left_out[14]:9 cbx_1__2__1_chanx_left_out[14]:8 0.00341 +2 cbx_1__2__1_chanx_left_out[14]:8 cbx_1__2__1_chanx_left_out[14]:7 0.0009262916 +3 cbx_1__2__1_chanx_left_out[14]:5 cbx_1__2__1_chanx_left_out[14]:4 0.00341 +4 cbx_1__2__1_chanx_left_out[14]:4 cbx_1__2__1_chanx_left_out[14]:3 0.00287405 +5 cbx_1__2__1_chanx_left_out[14]:2 sb_1__2_:chanx_right_in[14] 0.0005968999 +6 cbx_1__2__1_chanx_left_out[14]:3 cbx_1__2__1_chanx_left_out[14]:2 0.00341 +7 cbx_1__2__1_chanx_left_out[14]:7 cbx_1__2__1_chanx_left_out[14]:6 1e-05 +8 cbx_1__2__1_chanx_left_out[14]:6 cbx_1__2__1_chanx_left_out[14]:5 0.0003664433 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[0] 0.00133857 //LENGTH 7.660 LUMPCC 0.000376513 DR + +*CONN +*I cbx_2__2_:chanx_right_out[0] O *L 0 *C 773.570 828.240 +*I sb_2__2_:chanx_left_in[0] I *L 0 *C 781.230 828.240 + +*CAP +0 cbx_2__2_:chanx_right_out[0] 0.0004810284 +1 sb_2__2_:chanx_left_in[0] 0.0004810284 +2 cbx_2__2_:chanx_right_out[0] cbx_2__2_:chanx_right_out[1] 6.021191e-05 +3 sb_2__2_:chanx_left_in[0] sb_2__2_:chanx_left_in[1] 6.021191e-05 +4 cbx_2__2_:chanx_right_out[0] cbx_2__2_:chanx_right_out[18] 0.0001280446 +5 sb_2__2_:chanx_left_in[0] sb_2__2_:chanx_left_in[18] 0.0001280446 + +*RES +0 cbx_2__2_:chanx_right_out[0] sb_2__2_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[3] 0.001412371 //LENGTH 7.660 LUMPCC 0.000379102 DR + +*CONN +*I cbx_2__2_:chanx_right_out[3] O *L 0 *C 773.570 850.000 +*I sb_2__2_:chanx_left_in[3] I *L 0 *C 781.230 850.000 + +*CAP +0 cbx_2__2_:chanx_right_out[3] 0.0005166347 +1 sb_2__2_:chanx_left_in[3] 0.0005166347 +2 cbx_2__2_:chanx_right_out[3] cbx_2__2_:chanx_right_out[11] 6.375641e-05 +3 sb_2__2_:chanx_left_in[3] sb_2__2_:chanx_left_in[11] 6.375641e-05 +4 cbx_2__2_:chanx_right_out[3] cbx_2__2_:chanx_right_out[14] 0.0001257946 +5 sb_2__2_:chanx_left_in[3] sb_2__2_:chanx_left_in[14] 0.0001257946 + +*RES +0 cbx_2__2_:chanx_right_out[3] sb_2__2_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[6] 0.001320494 //LENGTH 7.660 LUMPCC 0.0003236081 DR + +*CONN +*I cbx_2__2_:chanx_right_out[6] O *L 0 *C 773.570 820.080 +*I sb_2__2_:chanx_left_in[6] I *L 0 *C 781.230 820.080 + +*CAP +0 cbx_2__2_:chanx_right_out[6] 0.0004984432 +1 sb_2__2_:chanx_left_in[6] 0.0004984432 +2 cbx_2__2_:chanx_right_out[6] cbx_2__2_:chanx_right_out[12] 0.0001331701 +3 sb_2__2_:chanx_left_in[6] sb_2__2_:chanx_left_in[12] 0.0001331701 +4 cbx_2__2_:chanx_right_out[6] ctsbuf_net_312:12 2.863395e-05 +5 sb_2__2_:chanx_left_in[6] ctsbuf_net_312:11 2.863395e-05 + +*RES +0 cbx_2__2_:chanx_right_out[6] sb_2__2_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[10] 0.00142955 //LENGTH 7.660 LUMPCC 0.00036691 DR + +*CONN +*I cbx_2__2_:chanx_right_out[10] O *L 0 *C 773.570 825.520 +*I sb_2__2_:chanx_left_in[10] I *L 0 *C 781.230 825.520 + +*CAP +0 cbx_2__2_:chanx_right_out[10] 0.0005313202 +1 sb_2__2_:chanx_left_in[10] 0.0005313202 +2 cbx_2__2_:chanx_right_out[10] cbx_2__2_:chanx_right_out[18] 0.0001244305 +3 sb_2__2_:chanx_left_in[10] sb_2__2_:chanx_left_in[18] 0.0001244305 +4 cbx_2__2_:chanx_right_out[10] cbx_2__2_:chanx_right_in[2] 5.902442e-05 +5 sb_2__2_:chanx_left_in[10] sb_2__2_:chanx_left_out[2] 5.902442e-05 + +*RES +0 cbx_2__2_:chanx_right_out[10] sb_2__2_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[14] 0.001442099 //LENGTH 7.660 LUMPCC 0.0005419726 DR + +*CONN +*I cbx_2__2_:chanx_right_out[14] O *L 0 *C 773.570 848.640 +*I sb_2__2_:chanx_left_in[14] I *L 0 *C 781.230 848.640 + +*CAP +0 cbx_2__2_:chanx_right_out[14] 0.0004500634 +1 sb_2__2_:chanx_left_in[14] 0.0004500634 +2 cbx_2__2_:chanx_right_out[14] cbx_2__2_:chanx_right_out[3] 0.0001257946 +3 sb_2__2_:chanx_left_in[14] sb_2__2_:chanx_left_in[3] 0.0001257946 +4 cbx_2__2_:chanx_right_out[14] cbx_2__2_:chanx_right_in[4] 0.0001451917 +5 sb_2__2_:chanx_left_in[14] sb_2__2_:chanx_left_out[4] 0.0001451917 + +*RES +0 cbx_2__2_:chanx_right_out[14] sb_2__2_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[18] 0.001489079 //LENGTH 7.660 LUMPCC 0.0005049503 DR + +*CONN +*I cbx_2__2_:chanx_right_out[18] O *L 0 *C 773.570 826.880 +*I sb_2__2_:chanx_left_in[18] I *L 0 *C 781.230 826.880 + +*CAP +0 cbx_2__2_:chanx_right_out[18] 0.0004920642 +1 sb_2__2_:chanx_left_in[18] 0.0004920642 +2 cbx_2__2_:chanx_right_out[18] cbx_2__2_:chanx_right_out[0] 0.0001280446 +3 sb_2__2_:chanx_left_in[18] sb_2__2_:chanx_left_in[0] 0.0001280446 +4 cbx_2__2_:chanx_right_out[18] cbx_2__2_:chanx_right_out[10] 0.0001244305 +5 sb_2__2_:chanx_left_in[18] sb_2__2_:chanx_left_in[10] 0.0001244305 + +*RES +0 cbx_2__2_:chanx_right_out[18] sb_2__2_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[1] 0.00115067 //LENGTH 11.020 LUMPCC 0.0002970275 DR + +*CONN +*I cby_0__1_:chany_bottom_out[1] O *L 0 *C 349.140 408.070 +*I sb_0__0_:chany_top_in[1] I *L 0 *C 349.140 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[1] 0.0004268212 +1 sb_0__0_:chany_top_in[1] 0.0004268212 +2 cby_0__1_:chany_bottom_out[1] cby_0__1_:chany_bottom_out[8] 0.0001485138 +3 sb_0__0_:chany_top_in[1] sb_0__0_:chany_top_in[8] 0.0001485138 + +*RES +0 cby_0__1_:chany_bottom_out[1] sb_0__0_:chany_top_in[1] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[5] 0.001070666 //LENGTH 11.020 LUMPCC 0.0001862591 DR + +*CONN +*I cby_0__1_:chany_bottom_out[5] O *L 0 *C 316.020 408.070 +*I sb_0__0_:chany_top_in[5] I *L 0 *C 316.020 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[5] 0.0004422033 +1 sb_0__0_:chany_top_in[5] 0.0004422033 +2 cby_0__1_:chany_bottom_out[5] cby_0__1_:chany_bottom_out[14] 3.396055e-05 +3 sb_0__0_:chany_top_in[5] sb_0__0_:chany_top_in[14] 3.396055e-05 +4 cby_0__1_:chany_bottom_out[5] cby_0__1_:chany_bottom_in[1] 2.696987e-05 +5 sb_0__0_:chany_top_in[5] sb_0__0_:chany_top_out[1] 2.696987e-05 +6 cby_0__1_:chany_bottom_out[5] cby_0__1_:chany_bottom_in[19] 3.219911e-05 +7 sb_0__0_:chany_top_in[5] sb_0__0_:chany_top_out[19] 3.219911e-05 + +*RES +0 cby_0__1_:chany_bottom_out[5] sb_0__0_:chany_top_in[5] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[11] 0.001126865 //LENGTH 11.020 LUMPCC 0.0003115926 DR + +*CONN +*I cby_0__1_:chany_bottom_out[11] O *L 0 *C 328.900 408.070 +*I sb_0__0_:chany_top_in[11] I *L 0 *C 328.900 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[11] 0.0004076362 +1 sb_0__0_:chany_top_in[11] 0.0004076362 +2 cby_0__1_:chany_bottom_out[11] cby_0__1_:chany_bottom_in[0] 0.0001557963 +3 sb_0__0_:chany_top_in[11] sb_0__0_:chany_top_out[0] 0.0001557963 + +*RES +0 cby_0__1_:chany_bottom_out[11] sb_0__0_:chany_top_in[11] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[14] 0.001268857 //LENGTH 11.180 LUMPCC 6.792111e-05 DR + +*CONN +*I cby_0__1_:chany_bottom_out[14] O *L 0 *C 316.480 408.150 +*I sb_0__0_:chany_top_in[14] I *L 0 *C 316.480 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[14] 0.0006004681 +1 sb_0__0_:chany_top_in[14] 0.0006004681 +2 cby_0__1_:chany_bottom_out[14] cby_0__1_:chany_bottom_out[5] 3.396055e-05 +3 sb_0__0_:chany_top_in[14] sb_0__0_:chany_top_in[5] 3.396055e-05 + +*RES +0 cby_0__1_:chany_bottom_out[14] sb_0__0_:chany_top_in[14] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[19] 0.001241236 //LENGTH 11.020 LUMPCC 0.0005926823 DR + +*CONN +*I cby_0__1_:chany_bottom_out[19] O *L 0 *C 334.420 408.070 +*I sb_0__0_:chany_top_in[19] I *L 0 *C 334.420 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[19] 0.0003242769 +1 sb_0__0_:chany_top_in[19] 0.0003242769 +2 cby_0__1_:chany_bottom_out[19] cby_0__1_:chany_bottom_in[10] 0.0001481706 +3 sb_0__0_:chany_top_in[19] sb_0__0_:chany_top_out[10] 0.0001481706 +4 cby_0__1_:chany_bottom_out[19] cby_0__1_:chany_bottom_in[16] 0.0001481706 +5 sb_0__0_:chany_top_in[19] sb_0__0_:chany_top_out[16] 0.0001481706 + +*RES +0 cby_0__1_:chany_bottom_out[19] sb_0__0_:chany_top_in[19] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_top_out[4] 0.001222479 //LENGTH 11.020 LUMPCC 0.0002584376 DR + +*CONN +*I cby_0__1_:chany_top_out[4] O *L 0 *C 360.180 516.730 +*I sb_0__1_:chany_bottom_in[4] I *L 0 *C 360.180 527.750 + +*CAP +0 cby_0__1_:chany_top_out[4] 0.0004820208 +1 sb_0__1_:chany_bottom_in[4] 0.0004820208 +2 cby_0__1_:chany_top_out[4] cby_0__1_:chany_top_out[13] 0.0001292188 +3 sb_0__1_:chany_bottom_in[4] sb_0__1_:chany_bottom_in[13] 0.0001292188 + +*RES +0 cby_0__1_:chany_top_out[4] sb_0__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[9] 0.001288776 //LENGTH 11.020 LUMPCC 0.0005185666 DR + +*CONN +*I cby_0__1_:chany_top_out[9] O *L 0 *C 310.040 516.730 +*I sb_0__1_:chany_bottom_in[9] I *L 0 *C 310.040 527.750 + +*CAP +0 cby_0__1_:chany_top_out[9] 0.0003851046 +1 sb_0__1_:chany_bottom_in[9] 0.0003851046 +2 cby_0__1_:chany_top_out[9] cby_0__1_:chany_top_out[7] 0.0001296416 +3 sb_0__1_:chany_bottom_in[9] sb_0__1_:chany_bottom_in[7] 0.0001296416 +4 cby_0__1_:chany_top_out[9] cby_0__1_:chany_top_out[8] 0.0001296416 +5 sb_0__1_:chany_bottom_in[9] sb_0__1_:chany_bottom_in[8] 0.0001296416 + +*RES +0 cby_0__1_:chany_top_out[9] sb_0__1_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[14] 0.001287043 //LENGTH 11.020 LUMPCC 0.0005186471 DR + +*CONN +*I cby_0__1_:chany_top_out[14] O *L 0 *C 330.740 516.730 +*I sb_0__1_:chany_bottom_in[14] I *L 0 *C 330.740 527.750 + +*CAP +0 cby_0__1_:chany_top_out[14] 0.0003841981 +1 sb_0__1_:chany_bottom_in[14] 0.0003841981 +2 cby_0__1_:chany_top_out[14] cby_0__1_:chany_top_in[3] 0.0001296618 +3 sb_0__1_:chany_bottom_in[14] sb_0__1_:chany_bottom_out[3] 0.0001296618 +4 cby_0__1_:chany_top_out[14] cby_0__1_:chany_top_in[10] 0.0001296618 +5 sb_0__1_:chany_bottom_in[14] sb_0__1_:chany_bottom_out[10] 0.0001296618 + +*RES +0 cby_0__1_:chany_top_out[14] sb_0__1_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[19] 0.001288776 //LENGTH 11.020 LUMPCC 0.0005185666 DR + +*CONN +*I cby_0__1_:chany_top_out[19] O *L 0 *C 311.880 516.730 +*I sb_0__1_:chany_bottom_in[19] I *L 0 *C 311.880 527.750 + +*CAP +0 cby_0__1_:chany_top_out[19] 0.0003851046 +1 sb_0__1_:chany_bottom_in[19] 0.0003851046 +2 cby_0__1_:chany_top_out[19] cby_0__1_:chany_top_out[8] 0.0001296416 +3 sb_0__1_:chany_bottom_in[19] sb_0__1_:chany_bottom_in[8] 0.0001296416 +4 cby_0__1_:chany_top_out[19] cby_0__1_:chany_top_in[9] 0.0001296416 +5 sb_0__1_:chany_bottom_in[19] sb_0__1_:chany_bottom_out[9] 0.0001296416 + +*RES +0 cby_0__1_:chany_top_out[19] sb_0__1_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[4] 0.001245208 //LENGTH 11.020 LUMPCC 0.0005807617 DR + +*CONN +*I cby_0__2_:chany_bottom_out[4] O *L 0 *C 330.740 669.190 +*I sb_0__1_:chany_top_in[4] I *L 0 *C 330.740 658.170 +*N cby_0__1__1_chany_bottom_out[4]:2 *C 330.740 667.519 +*N cby_0__1__1_chany_bottom_out[4]:3 *C 330.740 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[4] 0.0001108695 +1 sb_0__1_:chany_top_in[4] 0.0002213537 +2 cby_0__1__1_chany_bottom_out[4]:2 0.0002213537 +3 cby_0__1__1_chany_bottom_out[4]:3 0.0001108695 +4 cby_0__2_:chany_bottom_out[4] cby_0__2_:chany_bottom_in[0] 7.348477e-06 +5 sb_0__1_:chany_top_in[4] sb_0__1_:chany_top_out[0] 0.0001378419 +6 cby_0__1__1_chany_bottom_out[4]:3 sb_0__1__0_chany_top_out[0]:2 7.348477e-06 +7 cby_0__1__1_chany_bottom_out[4]:2 sb_0__1__0_chany_top_out[0]:3 0.0001378419 +8 cby_0__2_:chany_bottom_out[4] cby_0__2_:chany_bottom_in[5] 7.348477e-06 +9 sb_0__1_:chany_top_in[4] sb_0__1_:chany_top_out[5] 0.0001378419 +10 cby_0__1__1_chany_bottom_out[4]:3 sb_0__1__0_chany_top_out[5]:2 7.348477e-06 +11 cby_0__1__1_chany_bottom_out[4]:2 sb_0__1__0_chany_top_out[5]:3 0.0001378419 + +*RES +0 cby_0__2_:chany_bottom_out[4] cby_0__1__1_chany_bottom_out[4]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[4]:3 cby_0__1__1_chany_bottom_out[4]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[4]:2 sb_0__1_:chany_top_in[4] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[11] 0.00116334 //LENGTH 11.020 LUMPCC 0.0002903808 DR + +*CONN +*I cby_0__2_:chany_bottom_out[11] O *L 0 *C 328.900 669.190 +*I sb_0__1_:chany_top_in[11] I *L 0 *C 328.900 658.170 +*N cby_0__1__1_chany_bottom_out[11]:2 *C 328.900 667.519 +*N cby_0__1__1_chany_bottom_out[11]:3 *C 328.900 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[11] 0.0001188786 +1 sb_0__1_:chany_top_in[11] 0.000317601 +2 cby_0__1__1_chany_bottom_out[11]:2 0.000317601 +3 cby_0__1__1_chany_bottom_out[11]:3 0.0001188786 +4 cby_0__2_:chany_bottom_out[11] cby_0__2_:chany_bottom_in[0] 7.348477e-06 +5 sb_0__1_:chany_top_in[11] sb_0__1_:chany_top_out[0] 0.0001378419 +6 cby_0__1__1_chany_bottom_out[11]:3 sb_0__1__0_chany_top_out[0]:2 7.348477e-06 +7 cby_0__1__1_chany_bottom_out[11]:2 sb_0__1__0_chany_top_out[0]:3 0.0001378419 + +*RES +0 cby_0__2_:chany_bottom_out[11] cby_0__1__1_chany_bottom_out[11]:3 0.001491071 +1 cby_0__1__1_chany_bottom_out[11]:3 cby_0__1__1_chany_bottom_out[11]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[11]:2 sb_0__1_:chany_top_in[11] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[16] 0.001521108 //LENGTH 11.180 LUMPCC 0 DR + +*CONN +*I cby_0__2_:chany_bottom_out[16] O *L 0 *C 345.920 669.270 +*I sb_0__1_:chany_top_in[16] I *L 0 *C 345.920 658.090 +*N cby_0__1__1_chany_bottom_out[16]:2 *C 345.920 667.519 +*N cby_0__1__1_chany_bottom_out[16]:3 *C 345.920 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[16] 0.0002255614 +1 sb_0__1_:chany_top_in[16] 0.0005349924 +2 cby_0__1__1_chany_bottom_out[16]:2 0.0005349924 +3 cby_0__1__1_chany_bottom_out[16]:3 0.0002255614 + +*RES +0 cby_0__2_:chany_bottom_out[16] cby_0__1__1_chany_bottom_out[16]:3 0.0002741667 +1 cby_0__1__1_chany_bottom_out[16]:3 cby_0__1__1_chany_bottom_out[16]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[16]:2 sb_0__1_:chany_top_in[16] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_top_out[2] 0.001258694 //LENGTH 11.020 LUMPCC 0.0005589473 DR + +*CONN +*I cby_0__2_:chany_top_out[2] O *L 0 *C 358.340 777.850 +*I sb_0__2_:chany_bottom_in[2] I *L 0 *C 358.340 788.870 + +*CAP +0 cby_0__2_:chany_top_out[2] 0.0003498734 +1 sb_0__2_:chany_bottom_in[2] 0.0003498734 +2 cby_0__2_:chany_top_out[2] cby_0__2_:chany_top_out[13] 0.0001397368 +3 sb_0__2_:chany_bottom_in[2] sb_0__2_:chany_bottom_in[13] 0.0001397368 +4 cby_0__2_:chany_top_out[2] cby_0__2_:chany_top_in[6] 0.0001397368 +5 sb_0__2_:chany_bottom_in[2] sb_0__2_:chany_bottom_out[6] 0.0001397368 + +*RES +0 cby_0__2_:chany_top_out[2] sb_0__2_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[10] 0.001256142 //LENGTH 11.020 LUMPCC 0.0005659095 DR + +*CONN +*I cby_0__2_:chany_top_out[10] O *L 0 *C 339.020 777.850 +*I sb_0__2_:chany_bottom_in[10] I *L 0 *C 339.020 788.870 + +*CAP +0 cby_0__2_:chany_top_out[10] 0.0003451162 +1 sb_0__2_:chany_bottom_in[10] 0.0003451162 +2 cby_0__2_:chany_top_out[10] cby_0__2_:chany_top_out[6] 0.0001430462 +3 sb_0__2_:chany_bottom_in[10] sb_0__2_:chany_bottom_in[6] 0.0001430462 +4 cby_0__2_:chany_top_out[10] cby_0__2_:chany_top_in[4] 0.0001399086 +5 sb_0__2_:chany_bottom_in[10] sb_0__2_:chany_bottom_out[4] 0.0001399086 + +*RES +0 cby_0__2_:chany_top_out[10] sb_0__2_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_0__1__1_right_grid_pin_52_[0] 0.001133421 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_0__2_:right_grid_pin_52_[0] O *L 0 *C 371.530 748.000 +*I grid_clb_1__2_:left_width_0_height_0__pin_52_[0] I *L 0 *C 379.190 748.000 + +*CAP +0 cby_0__2_:right_grid_pin_52_[0] 0.0005667104 +1 grid_clb_1__2_:left_width_0_height_0__pin_52_[0] 0.0005667104 + +*RES +0 cby_0__2_:right_grid_pin_52_[0] grid_clb_1__2_:left_width_0_height_0__pin_52_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[4] 0.001230983 //LENGTH 11.020 LUMPCC 0.0005890562 DR + +*CONN +*I cby_1__1_:chany_bottom_out[4] O *L 0 *C 571.780 408.070 +*I sb_1__0_:chany_top_in[4] I *L 0 *C 571.780 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[4] 0.0003209633 +1 sb_1__0_:chany_top_in[4] 0.0003209633 +2 cby_1__1_:chany_bottom_out[4] cby_1__1_:chany_bottom_out[12] 0.000147264 +3 sb_1__0_:chany_top_in[4] sb_1__0_:chany_top_in[12] 0.000147264 +4 cby_1__1_:chany_bottom_out[4] cby_1__1_:chany_bottom_in[15] 0.000147264 +5 sb_1__0_:chany_top_in[4] sb_1__0_:chany_top_out[15] 0.000147264 + +*RES +0 cby_1__1_:chany_bottom_out[4] sb_1__0_:chany_top_in[4] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[14] 0.001136784 //LENGTH 11.020 LUMPCC 0.0003792299 DR + +*CONN +*I cby_1__1_:chany_bottom_out[14] O *L 0 *C 574.540 408.070 +*I sb_1__0_:chany_top_in[14] I *L 0 *C 574.540 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[14] 0.0003787772 +1 sb_1__0_:chany_top_in[14] 0.0003787772 +2 cby_1__1_:chany_bottom_out[14] cby_1__1_:chany_bottom_out[1] 3.733719e-05 +3 sb_1__0_:chany_top_in[14] sb_1__0_:chany_top_in[1] 3.733719e-05 +4 cby_1__1_:chany_bottom_out[14] cby_1__1_:chany_bottom_out[15] 0.0001522778 +5 sb_1__0_:chany_top_in[14] sb_1__0_:chany_top_in[15] 0.0001522778 + +*RES +0 cby_1__1_:chany_bottom_out[14] sb_1__0_:chany_top_in[14] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[4] 0.001293202 //LENGTH 11.020 LUMPCC 0.0005016136 DR + +*CONN +*I cby_1__1_:chany_top_out[4] O *L 0 *C 585.120 516.730 +*I sb_1__1_:chany_bottom_in[4] I *L 0 *C 585.120 527.750 + +*CAP +0 cby_1__1_:chany_top_out[4] 0.000395794 +1 sb_1__1_:chany_bottom_in[4] 0.000395794 +2 cby_1__1_:chany_top_out[4] cby_1__1_:chany_top_out[14] 0.0001254034 +3 sb_1__1_:chany_bottom_in[4] sb_1__1_:chany_bottom_in[14] 0.0001254034 +4 cby_1__1_:chany_top_out[4] cby_1__1_:chany_top_in[16] 0.0001254034 +5 sb_1__1_:chany_bottom_in[4] sb_1__1_:chany_bottom_out[16] 0.0001254034 + +*RES +0 cby_1__1_:chany_top_out[4] sb_1__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[13] 0.00128887 //LENGTH 11.020 LUMPCC 0.0005102205 DR + +*CONN +*I cby_1__1_:chany_top_out[13] O *L 0 *C 587.880 516.730 +*I sb_1__1_:chany_bottom_in[13] I *L 0 *C 587.880 527.750 + +*CAP +0 cby_1__1_:chany_top_out[13] 0.0003893248 +1 sb_1__1_:chany_bottom_in[13] 0.0003893248 +2 cby_1__1_:chany_top_out[13] cby_1__1_:chany_top_out[1] 0.0001275551 +3 sb_1__1_:chany_bottom_in[13] sb_1__1_:chany_bottom_in[1] 0.0001275551 +4 cby_1__1_:chany_top_out[13] cby_1__1_:chany_top_in[3] 0.0001275551 +5 sb_1__1_:chany_bottom_in[13] sb_1__1_:chany_bottom_out[3] 0.0001275551 + +*RES +0 cby_1__1_:chany_top_out[13] sb_1__1_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_11_[0] 0.001436877 //LENGTH 7.660 LUMPCC 0.0005402758 DR + +*CONN +*I cby_1__1_:left_grid_pin_11_[0] O *L 0 *C 548.470 485.520 +*I grid_clb_1__1_:right_width_0_height_0__pin_11_[0] I *L 0 *C 540.810 485.520 + +*CAP +0 cby_1__1_:left_grid_pin_11_[0] 0.0004483005 +1 grid_clb_1__1_:right_width_0_height_0__pin_11_[0] 0.0004483005 +2 cby_1__1_:left_grid_pin_11_[0] cby_1__1_:left_grid_pin_10_[0] 0.0001311915 +3 grid_clb_1__1_:right_width_0_height_0__pin_11_[0] grid_clb_1__1_:right_width_0_height_0__pin_10_[0] 0.0001311915 +4 cby_1__1_:left_grid_pin_11_[0] cby_1__1_:left_grid_pin_8_[0] 0.0001389464 +5 grid_clb_1__1_:right_width_0_height_0__pin_11_[0] grid_clb_1__1_:right_width_0_height_0__pin_8_[0] 0.0001389464 + +*RES +0 cby_1__1_:left_grid_pin_11_[0] grid_clb_1__1_:right_width_0_height_0__pin_11_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_7_[0] 0.001454094 //LENGTH 7.660 LUMPCC 0.0005044909 DR + +*CONN +*I cby_1__1_:left_grid_pin_7_[0] O *L 0 *C 548.470 507.280 +*I grid_clb_1__1_:right_width_0_height_0__pin_7_[0] I *L 0 *C 540.810 507.280 + +*CAP +0 cby_1__1_:left_grid_pin_7_[0] 0.0004748018 +1 grid_clb_1__1_:right_width_0_height_0__pin_7_[0] 0.0004748018 +2 cby_1__1_:left_grid_pin_7_[0] cby_1__1_:left_grid_pin_2_[0] 0.0001333385 +3 grid_clb_1__1_:right_width_0_height_0__pin_7_[0] grid_clb_1__1_:right_width_0_height_0__pin_2_[0] 0.0001333385 +4 cby_1__1_:left_grid_pin_7_[0] cby_1__1_:left_grid_pin_4_[0] 0.0001189069 +5 grid_clb_1__1_:right_width_0_height_0__pin_7_[0] grid_clb_1__1_:right_width_0_height_0__pin_4_[0] 0.0001189069 + +*RES +0 cby_1__1_:left_grid_pin_7_[0] grid_clb_1__1_:right_width_0_height_0__pin_7_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[5] 0.001250537 //LENGTH 11.020 LUMPCC 0.0005737565 DR + +*CONN +*I cby_1__2_:chany_bottom_out[5] O *L 0 *C 580.060 669.190 +*I sb_1__1_:chany_top_in[5] I *L 0 *C 580.060 658.170 +*N cby_1__1__1_chany_bottom_out[5]:2 *C 580.060 667.519 +*N cby_1__1__1_chany_bottom_out[5]:3 *C 580.060 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[5] 0.0001111417 +1 sb_1__1_:chany_top_in[5] 0.0002272485 +2 cby_1__1__1_chany_bottom_out[5]:2 0.0002272485 +3 cby_1__1__1_chany_bottom_out[5]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[5] cby_1__2_:chany_bottom_out[19] 7.295327e-06 +5 sb_1__1_:chany_top_in[5] sb_1__1_:chany_top_in[19] 0.0001361438 +6 cby_1__1__1_chany_bottom_out[5]:3 cby_1__1__1_chany_bottom_out[19]:3 7.295327e-06 +7 cby_1__1__1_chany_bottom_out[5]:2 cby_1__1__1_chany_bottom_out[19]:2 0.0001361438 +8 cby_1__2_:chany_bottom_out[5] cby_1__2_:chany_bottom_in[1] 7.295327e-06 +9 sb_1__1_:chany_top_in[5] sb_1__1_:chany_top_out[1] 0.0001361438 +10 cby_1__1__1_chany_bottom_out[5]:3 sb_1__1__0_chany_top_out[1]:2 7.295327e-06 +11 cby_1__1__1_chany_bottom_out[5]:2 sb_1__1__0_chany_top_out[1]:3 0.0001361438 + +*RES +0 cby_1__2_:chany_bottom_out[5] cby_1__1__1_chany_bottom_out[5]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[5]:3 cby_1__1__1_chany_bottom_out[5]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[5]:2 sb_1__1_:chany_top_in[5] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[14] 0.001148759 //LENGTH 11.020 LUMPCC 0.0003822193 DR + +*CONN +*I cby_1__2_:chany_bottom_out[14] O *L 0 *C 574.540 669.190 +*I sb_1__1_:chany_top_in[14] I *L 0 *C 574.540 658.170 +*N cby_1__1__1_chany_bottom_out[14]:2 *C 574.540 667.519 +*N cby_1__1__1_chany_bottom_out[14]:3 *C 574.540 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[14] 0.0001179203 +1 sb_1__1_:chany_top_in[14] 0.0002653497 +2 cby_1__1__1_chany_bottom_out[14]:2 0.0002653497 +3 cby_1__1__1_chany_bottom_out[14]:3 0.0001179203 +4 sb_1__1_:chany_top_in[14] sb_1__1_:chany_top_in[1] 4.036643e-05 +5 cby_1__1__1_chany_bottom_out[14]:2 cby_1__1__1_chany_bottom_out[1]:2 4.036643e-05 +6 cby_1__2_:chany_bottom_out[14] cby_1__2_:chany_bottom_out[15] 7.341718e-06 +7 sb_1__1_:chany_top_in[14] sb_1__1_:chany_top_in[15] 0.0001434015 +8 cby_1__1__1_chany_bottom_out[14]:3 cby_1__1__1_chany_bottom_out[15]:3 7.341718e-06 +9 cby_1__1__1_chany_bottom_out[14]:2 cby_1__1__1_chany_bottom_out[15]:2 0.0001434015 + +*RES +0 cby_1__2_:chany_bottom_out[14] cby_1__1__1_chany_bottom_out[14]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[14]:3 cby_1__1__1_chany_bottom_out[14]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[14]:2 sb_1__1_:chany_top_in[14] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_top_out[3] 0.001201385 //LENGTH 11.020 LUMPCC 0.0002666161 DR + +*CONN +*I cby_1__2_:chany_top_out[3] O *L 0 *C 608.120 777.850 +*I sb_1__2_:chany_bottom_in[3] I *L 0 *C 608.120 788.870 + +*CAP +0 cby_1__2_:chany_top_out[3] 0.0004673843 +1 sb_1__2_:chany_bottom_in[3] 0.0004673843 +2 cby_1__2_:chany_top_out[3] cby_1__2_:chany_top_out[7] 0.0001333081 +3 sb_1__2_:chany_bottom_in[3] sb_1__2_:chany_bottom_in[7] 0.0001333081 + +*RES +0 cby_1__2_:chany_top_out[3] sb_1__2_:chany_bottom_in[3] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[13] 0.001272042 //LENGTH 11.020 LUMPCC 0.0005339056 DR + +*CONN +*I cby_1__2_:chany_top_out[13] O *L 0 *C 587.880 777.850 +*I sb_1__2_:chany_bottom_in[13] I *L 0 *C 587.880 788.870 + +*CAP +0 cby_1__2_:chany_top_out[13] 0.0003690684 +1 sb_1__2_:chany_bottom_in[13] 0.0003690684 +2 cby_1__2_:chany_top_out[13] cby_1__2_:chany_top_out[1] 0.0001334764 +3 sb_1__2_:chany_bottom_in[13] sb_1__2_:chany_bottom_in[1] 0.0001334764 +4 cby_1__2_:chany_top_out[13] cby_1__2_:chany_top_in[3] 0.0001334764 +5 sb_1__2_:chany_bottom_in[13] sb_1__2_:chany_bottom_out[3] 0.0001334764 + +*RES +0 cby_1__2_:chany_top_out[13] sb_1__2_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_12_[0] 0.001385622 //LENGTH 7.660 LUMPCC 0.0002537467 DR + +*CONN +*I cby_1__2_:left_grid_pin_12_[0] O *L 0 *C 548.470 704.480 +*I grid_clb_1__2_:right_width_0_height_0__pin_12_[0] I *L 0 *C 540.810 704.480 + +*CAP +0 cby_1__2_:left_grid_pin_12_[0] 0.0005659376 +1 grid_clb_1__2_:right_width_0_height_0__pin_12_[0] 0.0005659376 +2 cby_1__2_:left_grid_pin_12_[0] cby_1__2_:left_grid_pin_15_[0] 0.0001268733 +3 grid_clb_1__2_:right_width_0_height_0__pin_12_[0] grid_clb_1__2_:right_width_0_height_0__pin_15_[0] 0.0001268733 + +*RES +0 cby_1__2_:left_grid_pin_12_[0] grid_clb_1__2_:right_width_0_height_0__pin_12_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_6_[0] 0.001546388 //LENGTH 7.660 LUMPCC 0.0004342251 DR + +*CONN +*I cby_1__2_:left_grid_pin_6_[0] O *L 0 *C 548.470 749.360 +*I grid_clb_1__2_:right_width_0_height_0__pin_6_[0] I *L 0 *C 540.810 749.360 + +*CAP +0 cby_1__2_:left_grid_pin_6_[0] 0.0005560813 +1 grid_clb_1__2_:right_width_0_height_0__pin_6_[0] 0.0005560813 +2 cby_1__2_:left_grid_pin_6_[0] cby_1__2_:left_grid_pin_10_[0] 0.0001041227 +3 grid_clb_1__2_:right_width_0_height_0__pin_6_[0] grid_clb_1__2_:right_width_0_height_0__pin_10_[0] 0.0001041227 +4 cby_1__2_:left_grid_pin_6_[0] cby_1__2_:left_grid_pin_9_[0] 0.0001129898 +5 grid_clb_1__2_:right_width_0_height_0__pin_6_[0] grid_clb_1__2_:right_width_0_height_0__pin_9_[0] 0.0001129898 + +*RES +0 cby_1__2_:left_grid_pin_6_[0] grid_clb_1__2_:right_width_0_height_0__pin_6_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[7] 0.001164831 //LENGTH 11.020 LUMPCC 0.000395277 DR + +*CONN +*I cby_2__1_:chany_bottom_out[7] O *L 0 *C 847.780 408.070 +*I sb_2__0_:chany_top_in[7] I *L 0 *C 847.780 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[7] 0.0003847768 +1 sb_2__0_:chany_top_in[7] 0.0003847768 +2 cby_2__1_:chany_bottom_out[7] cby_2__1_:chany_bottom_out[9] 0.0001448879 +3 sb_2__0_:chany_top_in[7] sb_2__0_:chany_top_in[9] 0.0001448879 +4 cby_2__1_:chany_bottom_out[7] cby_2__1_:chany_bottom_in[13] 5.275058e-05 +5 sb_2__0_:chany_top_in[7] sb_2__0_:chany_top_out[13] 5.275058e-05 + +*RES +0 cby_2__1_:chany_bottom_out[7] sb_2__0_:chany_top_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[18] 0.001142898 //LENGTH 11.020 LUMPCC 0.0004008621 DR + +*CONN +*I cby_2__1_:chany_bottom_out[18] O *L 0 *C 865.720 408.070 +*I sb_2__0_:chany_top_in[18] I *L 0 *C 865.720 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[18] 0.0003710177 +1 sb_2__0_:chany_top_in[18] 0.0003710177 +2 cby_2__1_:chany_bottom_out[18] cby_2__1_:chany_bottom_in[5] 0.0001521467 +3 sb_2__0_:chany_top_in[18] sb_2__0_:chany_top_out[5] 0.0001521467 +4 cby_2__1_:chany_bottom_out[18] cby_2__1_:chany_bottom_in[16] 4.82844e-05 +5 sb_2__0_:chany_top_in[18] sb_2__0_:chany_top_out[16] 4.82844e-05 + +*RES +0 cby_2__1_:chany_bottom_out[18] sb_2__0_:chany_top_in[18] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[9] 0.001201844 //LENGTH 11.020 LUMPCC 0.000340784 DR + +*CONN +*I cby_2__1_:chany_top_out[9] O *L 0 *C 865.260 516.730 +*I sb_2__1_:chany_bottom_in[9] I *L 0 *C 865.260 527.750 + +*CAP +0 cby_2__1_:chany_top_out[9] 0.0004305298 +1 sb_2__1_:chany_bottom_in[9] 0.0004305298 +2 cby_2__1_:chany_top_out[9] cby_2__1_:chany_top_out[11] 3.864707e-05 +3 sb_2__1_:chany_bottom_in[9] sb_2__1_:chany_bottom_in[11] 3.864707e-05 +4 cby_2__1_:chany_top_out[9] cby_2__1_:chany_top_in[0] 0.0001317449 +5 sb_2__1_:chany_bottom_in[9] sb_2__1_:chany_bottom_out[0] 0.0001317449 + +*RES +0 cby_2__1_:chany_top_out[9] sb_2__1_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_0_[0] 0.001205351 //LENGTH 7.660 LUMPCC 0.000727553 DR + +*CONN +*I cby_2__1_:left_grid_pin_0_[0] O *L 0 *C 809.750 510.000 +*I grid_clb_2__1_:right_width_0_height_0__pin_0_[0] I *L 0 *C 802.090 510.000 + +*CAP +0 cby_2__1_:left_grid_pin_0_[0] 0.000238899 +1 grid_clb_2__1_:right_width_0_height_0__pin_0_[0] 0.000238899 +2 cby_2__1_:left_grid_pin_0_[0] cby_2__1_:left_grid_pin_4_[0] 0.0001818883 +3 grid_clb_2__1_:right_width_0_height_0__pin_0_[0] grid_clb_2__1_:right_width_0_height_0__pin_4_[0] 0.0001818883 +4 cby_2__1_:left_grid_pin_0_[0] cby_2__1_:left_grid_pin_5_[0] 0.0001818883 +5 grid_clb_2__1_:right_width_0_height_0__pin_0_[0] grid_clb_2__1_:right_width_0_height_0__pin_5_[0] 0.0001818883 + +*RES +0 cby_2__1_:left_grid_pin_0_[0] grid_clb_2__1_:right_width_0_height_0__pin_0_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_6_[0] 0.001215779 //LENGTH 7.660 LUMPCC 0.0007181676 DR + +*CONN +*I cby_2__1_:left_grid_pin_6_[0] O *L 0 *C 809.750 488.240 +*I grid_clb_2__1_:right_width_0_height_0__pin_6_[0] I *L 0 *C 802.090 488.240 + +*CAP +0 cby_2__1_:left_grid_pin_6_[0] 0.0002488056 +1 grid_clb_2__1_:right_width_0_height_0__pin_6_[0] 0.0002488056 +2 cby_2__1_:left_grid_pin_6_[0] cby_2__1_:left_grid_pin_10_[0] 0.0001795419 +3 grid_clb_2__1_:right_width_0_height_0__pin_6_[0] grid_clb_2__1_:right_width_0_height_0__pin_10_[0] 0.0001795419 +4 cby_2__1_:left_grid_pin_6_[0] cby_2__1_:left_grid_pin_9_[0] 0.0001795419 +5 grid_clb_2__1_:right_width_0_height_0__pin_6_[0] grid_clb_2__1_:right_width_0_height_0__pin_9_[0] 0.0001795419 + +*RES +0 cby_2__1_:left_grid_pin_6_[0] grid_clb_2__1_:right_width_0_height_0__pin_6_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[5] 0.001257977 //LENGTH 11.020 LUMPCC 0.0005502676 DR + +*CONN +*I cby_2__2_:chany_bottom_out[5] O *L 0 *C 841.340 669.190 +*I sb_2__1_:chany_top_in[5] I *L 0 *C 841.340 658.170 +*N cby_1__1__3_chany_bottom_out[5]:2 *C 841.340 667.519 +*N cby_1__1__3_chany_bottom_out[5]:3 *C 841.340 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[5] 0.0001109378 +1 sb_2__1_:chany_top_in[5] 0.0002429168 +2 cby_1__1__3_chany_bottom_out[5]:2 0.0002429168 +3 cby_1__1__3_chany_bottom_out[5]:3 0.0001109378 +4 cby_2__2_:chany_bottom_out[5] cby_2__2_:chany_bottom_out[19] 7.340369e-06 +5 sb_2__1_:chany_top_in[5] sb_2__1_:chany_top_in[19] 0.0001302265 +6 cby_1__1__3_chany_bottom_out[5]:3 cby_1__1__3_chany_bottom_out[19]:3 7.340369e-06 +7 cby_1__1__3_chany_bottom_out[5]:2 cby_1__1__3_chany_bottom_out[19]:2 0.0001302265 +8 cby_2__2_:chany_bottom_out[5] cby_2__2_:chany_bottom_in[1] 7.340369e-06 +9 sb_2__1_:chany_top_in[5] sb_2__1_:chany_top_out[1] 0.0001302265 +10 cby_1__1__3_chany_bottom_out[5]:3 sb_2__1__0_chany_top_out[1]:2 7.340369e-06 +11 cby_1__1__3_chany_bottom_out[5]:2 sb_2__1__0_chany_top_out[1]:3 0.0001302265 + +*RES +0 cby_2__2_:chany_bottom_out[5] cby_1__1__3_chany_bottom_out[5]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[5]:3 cby_1__1__3_chany_bottom_out[5]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[5]:2 sb_2__1_:chany_top_in[5] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[16] 0.001265445 //LENGTH 11.020 LUMPCC 0.0005421289 DR + +*CONN +*I cby_2__2_:chany_bottom_out[16] O *L 0 *C 850.540 669.190 +*I sb_2__1_:chany_top_in[16] I *L 0 *C 850.540 658.170 +*N cby_1__1__3_chany_bottom_out[16]:2 *C 850.540 667.519 +*N cby_1__1__3_chany_bottom_out[16]:3 *C 850.540 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[16] 0.0001111417 +1 sb_2__1_:chany_top_in[16] 0.0002505166 +2 cby_1__1__3_chany_bottom_out[16]:2 0.0002505166 +3 cby_1__1__3_chany_bottom_out[16]:3 0.0001111417 +4 cby_2__2_:chany_bottom_out[16] cby_2__2_:chany_bottom_in[6] 7.294814e-06 +5 sb_2__1_:chany_top_in[16] sb_2__1_:chany_top_out[6] 0.0001283662 +6 cby_1__1__3_chany_bottom_out[16]:3 sb_2__1__0_chany_top_out[6]:2 7.294814e-06 +7 cby_1__1__3_chany_bottom_out[16]:2 sb_2__1__0_chany_top_out[6]:3 0.0001283662 +8 cby_2__2_:chany_bottom_out[16] cby_2__2_:chany_bottom_in[8] 7.294814e-06 +9 sb_2__1_:chany_top_in[16] sb_2__1_:chany_top_out[8] 0.0001281086 +10 cby_1__1__3_chany_bottom_out[16]:3 sb_2__1__0_chany_top_out[8]:2 7.294814e-06 +11 cby_1__1__3_chany_bottom_out[16]:2 sb_2__1__0_chany_top_out[8]:3 0.0001281086 + +*RES +0 cby_2__2_:chany_bottom_out[16] cby_1__1__3_chany_bottom_out[16]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[16]:3 cby_1__1__3_chany_bottom_out[16]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[16]:2 sb_2__1_:chany_top_in[16] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_top_out[10] 0.001236644 //LENGTH 11.020 LUMPCC 0.000587663 DR + +*CONN +*I cby_2__2_:chany_top_out[10] O *L 0 *C 843.640 777.850 +*I sb_2__2_:chany_bottom_in[10] I *L 0 *C 843.640 788.870 + +*CAP +0 cby_2__2_:chany_top_out[10] 0.0003244906 +1 sb_2__2_:chany_bottom_in[10] 0.0003244906 +2 cby_2__2_:chany_top_out[10] cby_2__2_:chany_top_in[8] 0.0001469158 +3 sb_2__2_:chany_bottom_in[10] sb_2__2_:chany_bottom_out[8] 0.0001469158 +4 cby_2__2_:chany_top_out[10] cby_2__2_:chany_top_in[13] 0.0001469158 +5 sb_2__2_:chany_bottom_in[10] sb_2__2_:chany_bottom_out[13] 0.0001469158 + +*RES +0 cby_2__2_:chany_top_out[10] sb_2__2_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_12_[0] 0.001099642 //LENGTH 7.660 LUMPCC 0.0003535021 DR + +*CONN +*I cby_2__2_:left_grid_pin_12_[0] O *L 0 *C 809.750 704.480 +*I grid_clb_2__2_:right_width_0_height_0__pin_12_[0] I *L 0 *C 802.090 704.480 + +*CAP +0 cby_2__2_:left_grid_pin_12_[0] 0.0003730699 +1 grid_clb_2__2_:right_width_0_height_0__pin_12_[0] 0.0003730699 +2 cby_2__2_:left_grid_pin_12_[0] cby_2__2_:left_grid_pin_15_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_12_[0] grid_clb_2__2_:right_width_0_height_0__pin_15_[0] 0.0001767511 + +*RES +0 cby_2__2_:left_grid_pin_12_[0] grid_clb_2__2_:right_width_0_height_0__pin_12_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_7_[0] 0.001231423 //LENGTH 7.660 LUMPCC 0.0006944634 DR + +*CONN +*I cby_2__2_:left_grid_pin_7_[0] O *L 0 *C 809.750 768.400 +*I grid_clb_2__2_:right_width_0_height_0__pin_7_[0] I *L 0 *C 802.090 768.400 + +*CAP +0 cby_2__2_:left_grid_pin_7_[0] 0.0002684799 +1 grid_clb_2__2_:right_width_0_height_0__pin_7_[0] 0.0002684799 +2 cby_2__2_:left_grid_pin_7_[0] cby_2__2_:left_grid_pin_2_[0] 0.0001736158 +3 grid_clb_2__2_:right_width_0_height_0__pin_7_[0] grid_clb_2__2_:right_width_0_height_0__pin_2_[0] 0.0001736158 +4 cby_2__2_:left_grid_pin_7_[0] cby_2__2_:left_grid_pin_4_[0] 0.0001736158 +5 grid_clb_2__2_:right_width_0_height_0__pin_7_[0] grid_clb_2__2_:right_width_0_height_0__pin_4_[0] 0.0001736158 + +*RES +0 cby_2__2_:left_grid_pin_7_[0] grid_clb_2__2_:right_width_0_height_0__pin_7_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_42_upper[0] 0.001234117 //LENGTH 11.020 LUMPCC 0.0005948123 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] O *L 0 *C 396.980 380.870 +*I sb_0__0_:right_top_grid_pin_42_[0] I *L 0 *C 396.980 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] 0.0003196523 +1 sb_0__0_:right_top_grid_pin_42_[0] 0.0003196523 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_44_upper[0] 0.0001487031 +3 sb_0__0_:right_top_grid_pin_42_[0] sb_0__0_:right_top_grid_pin_44_[0] 0.0001487031 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0001487031 +5 sb_0__0_:right_top_grid_pin_42_[0] sb_0__0_:right_top_grid_pin_45_[0] 0.0001487031 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] sb_0__0_:right_top_grid_pin_42_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_47_lower[0] 0.001252512 //LENGTH 11.020 LUMPCC 0.0005622869 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] O *L 0 *C 523.020 380.870 +*I sb_1__0_:left_top_grid_pin_47_[0] I *L 0 *C 523.020 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0003451123 +1 sb_1__0_:left_top_grid_pin_47_[0] 0.0003451123 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0001405717 +3 sb_1__0_:left_top_grid_pin_47_[0] sb_1__0_:left_top_grid_pin_44_[0] 0.0001405717 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_46_lower[0] 0.0001405717 +5 sb_1__0_:left_top_grid_pin_47_[0] sb_1__0_:left_top_grid_pin_46_[0] 0.0001405717 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] sb_1__0_:left_top_grid_pin_47_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_37_upper[0] 0.001489897 //LENGTH 7.660 LUMPCC 0.0003412899 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] O *L 0 *C 540.810 531.080 +*I sb_1__1_:bottom_left_grid_pin_37_[0] I *L 0 *C 548.470 531.080 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] 0.0005743034 +1 sb_1__1_:bottom_left_grid_pin_37_[0] 0.0005743034 +2 grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] 0.0001035548 +3 sb_1__1_:bottom_left_grid_pin_37_[0] sb_1__1_:bottom_left_grid_pin_38_[0] 0.0001035548 +4 grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_41_upper[0] 6.709016e-05 +5 sb_1__1_:bottom_left_grid_pin_37_[0] grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 6.709016e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] sb_1__1_:bottom_left_grid_pin_37_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_43_lower[0] 0.001464059 //LENGTH 7.660 LUMPCC 0.0002819033 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] O *L 0 *C 540.810 646.680 +*I sb_1__1_:left_top_grid_pin_43_[0] I *L 0 *C 548.470 646.680 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] 0.0005910779 +1 sb_1__1_:left_top_grid_pin_43_[0] 0.0005910779 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] 3.50267e-05 +3 sb_1__1_:left_top_grid_pin_43_[0] sb_1__1_:top_left_grid_pin_40_[0] 3.50267e-05 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_41_lower[0] 0.0001059249 +5 sb_1__1_:left_top_grid_pin_43_[0] sb_1__1_:top_left_grid_pin_41_[0] 0.0001059249 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] sb_1__1_:left_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_ccff_tail[0] 0.001385575 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_1__2_:ccff_tail[0] O *L 0 *C 540.810 682.720 +*I cby_1__2_:ccff_head[0] I *L 0 *C 548.470 682.720 + +*CAP +0 grid_clb_1__2_:ccff_tail[0] 0.0006927877 +1 cby_1__2_:ccff_head[0] 0.0006927877 + +*RES +0 grid_clb_1__2_:ccff_tail[0] cby_1__2_:ccff_head[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_36_lower[0] 0.00137506 //LENGTH 7.660 LUMPCC 0.0001315736 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_36_lower[0] O *L 0 *C 540.810 654.840 +*I sb_1__1_:top_left_grid_pin_36_[0] I *L 0 *C 548.470 654.840 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_36_lower[0] 0.0006217433 +1 sb_1__1_:top_left_grid_pin_36_[0] 0.0006217433 +2 grid_clb_1__2_:right_width_0_height_0__pin_36_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] 6.578679e-05 +3 sb_1__1_:top_left_grid_pin_36_[0] sb_1__1_:top_left_grid_pin_38_[0] 6.578679e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_36_lower[0] sb_1__1_:top_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_41_upper[0] 0.003083878 //LENGTH 20.610 LUMPCC 0.0007881557 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_41_upper[0] O *L 0 *C 540.810 790.840 +*I sb_1__2_:bottom_left_grid_pin_41_[0] I *L 0 *C 548.470 803.080 +*N grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 *C 544.660 803.080 +*N grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 *C 544.640 803.072 +*N grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 *C 544.640 790.848 +*N grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 *C 544.620 790.840 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_41_upper[0] 0.0003180093 +1 sb_1__2_:bottom_left_grid_pin_41_[0] 0.0003190414 +2 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 0.0003190414 +3 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 0.0005108107 +4 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 0.0005108107 +5 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 0.0003180093 +6 grid_clb_1__2_:right_width_0_height_0__pin_41_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] 6.066622e-05 +7 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 sb_1__2_:bottom_left_grid_pin_37_[0] 6.066622e-05 +8 sb_1__2_:bottom_left_grid_pin_41_[0] sb_1__2_:bottom_left_grid_pin_40_[0] 5.611754e-05 +9 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] 5.611754e-05 +10 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 ctsbuf_net_2130:20 0.0002772941 +11 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 ctsbuf_net_2130:28 0.0002772941 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_41_upper[0] grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 0.0005968999 +1 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 sb_1__2_:bottom_left_grid_pin_41_[0] 0.0005969 +2 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 0.00341 +3 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 0.00341 +4 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 0.00191525 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_48_lower[0] 0.001141802 //LENGTH 11.020 LUMPCC 0.0002992378 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_48_lower[0] O *L 0 *C 792.580 380.870 +*I sb_2__0_:left_top_grid_pin_48_[0] I *L 0 *C 792.580 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_48_lower[0] 0.0004212819 +1 sb_2__0_:left_top_grid_pin_48_[0] 0.0004212819 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_48_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] 0.0001496189 +3 sb_2__0_:left_top_grid_pin_48_[0] sb_2__0_:left_top_grid_pin_49_[0] 0.0001496189 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_48_lower[0] sb_2__0_:left_top_grid_pin_48_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_37_upper[0] 0.00119343 //LENGTH 7.660 LUMPCC 0.0005959271 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] O *L 0 *C 802.090 531.080 +*I sb_2__1_:bottom_left_grid_pin_37_[0] I *L 0 *C 809.750 531.080 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] 0.0002987513 +1 sb_2__1_:bottom_left_grid_pin_37_[0] 0.0002987513 +2 grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] 0.0001792434 +3 sb_2__1_:bottom_left_grid_pin_37_[0] sb_2__1_:bottom_left_grid_pin_38_[0] 0.0001792434 +4 grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] 0.0001187201 +5 sb_2__1_:bottom_left_grid_pin_37_[0] grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 0.0001187201 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] sb_2__1_:bottom_left_grid_pin_37_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_43_lower[0] 0.001097457 //LENGTH 7.660 LUMPCC 0.0004592965 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] O *L 0 *C 802.090 646.680 +*I sb_2__1_:left_top_grid_pin_43_[0] I *L 0 *C 809.750 646.680 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] 0.0003190803 +1 sb_2__1_:left_top_grid_pin_43_[0] 0.0003190803 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] 4.805342e-05 +3 sb_2__1_:left_top_grid_pin_43_[0] sb_2__1_:top_left_grid_pin_40_[0] 4.805342e-05 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] 0.0001815948 +5 sb_2__1_:left_top_grid_pin_43_[0] sb_2__1_:top_left_grid_pin_41_[0] 0.0001815948 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] sb_2__1_:left_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_50_[0] 0.0004435088 //LENGTH 3.275 LUMPCC 0 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_50_[0] O *L 0 *C 776.480 641.990 +*I direct_interc_1_\/FTB_2__1:A I *L 0.001746 *C 775.100 640.560 +*N grid_clb_3_bottom_width_0_height_0__pin_50_[0]:2 *C 775.138 640.560 +*N grid_clb_3_bottom_width_0_height_0__pin_50_[0]:3 *C 776.435 640.560 +*N grid_clb_3_bottom_width_0_height_0__pin_50_[0]:4 *C 776.480 640.605 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_50_[0] 0.0001101156 +1 direct_interc_1_\/FTB_2__1:A 1e-06 +2 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:2 0.0001111388 +3 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:3 0.0001111388 +4 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:4 0.0001101156 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_50_[0] grid_clb_3_bottom_width_0_height_0__pin_50_[0]:4 0.001236607 +1 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:3 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:2 0.001158482 +2 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:4 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:3 0.0045 +3 grid_clb_3_bottom_width_0_height_0__pin_50_[0]:2 direct_interc_1_\/FTB_2__1:A 0.152 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_38_upper[0] 0.001241372 //LENGTH 7.660 LUMPCC 0.000502285 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] O *L 0 *C 802.090 793.560 +*I sb_2__2_:bottom_left_grid_pin_38_[0] I *L 0 *C 809.750 793.560 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] 0.0003695434 +1 sb_2__2_:bottom_left_grid_pin_38_[0] 0.0003695434 +2 grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] 8.998787e-05 +3 sb_2__2_:bottom_left_grid_pin_38_[0] sb_2__2_:bottom_left_grid_pin_36_[0] 8.998787e-05 +4 grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] 0.0001611546 +5 sb_2__2_:bottom_left_grid_pin_38_[0] sb_2__2_:bottom_left_grid_pin_37_[0] 0.0001611546 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] sb_2__2_:bottom_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0] 0.00251134 //LENGTH 24.820 LUMPCC 9.796538e-05 DR + +*CONN +*I grid_io_bottom_2__0_:top_width_0_height_0__pin_1_upper[0] O *L 0 *C 672.060 282.810 +*I sb_1__0_:right_bottom_grid_pin_1_[0] I *L 0 *C 659.180 293.830 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 *C 659.180 289.340 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 *C 659.640 289.340 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:4 *C 659.640 286.665 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:5 *C 659.685 286.620 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:6 *C 667.519 286.620 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:7 *C 667.520 286.620 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:8 *C 672.015 286.620 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:9 *C 672.060 286.575 + +*CAP +0 grid_io_bottom_2__0_:top_width_0_height_0__pin_1_upper[0] 0.000197119 +1 sb_1__0_:right_bottom_grid_pin_1_[0] 0.0002274269 +2 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 0.0002398112 +3 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 0.0001574471 +4 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:4 0.0001450628 +5 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:5 0.0003864876 +6 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:6 0.0003864876 +7 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:7 0.0002382068 +8 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:8 0.0002382068 +9 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:9 0.000197119 +10 sb_1__0_:right_bottom_grid_pin_1_[0] sb_1__0_:ccff_head[0] 3.531082e-05 +11 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 grid_io_bottom_1_ccff_tail[0]:2 3.531082e-05 +12 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 grid_io_bottom_1_ccff_tail[0]:3 1.367187e-05 +13 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 grid_io_bottom_1_ccff_tail[0]:4 1.367187e-05 + +*RES +0 grid_io_bottom_2__0_:top_width_0_height_0__pin_1_upper[0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:9 0.003361607 +1 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:5 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:4 0.0045 +2 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:4 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 0.002388393 +3 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:8 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:7 0.004013393 +4 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:9 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:8 0.0045 +5 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 sb_1__0_:right_bottom_grid_pin_1_[0] 0.004008928 +6 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 0.0004107143 +7 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:7 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:6 1e-05 +8 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:6 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:5 0.006994643 + +*END + +*D_NET grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0] 0.002262929 //LENGTH 23.680 LUMPCC 0 DR + +*CONN +*I grid_io_top_2__3_:bottom_width_0_height_0__pin_1_lower[0] O *L 0 *C 771.420 903.110 +*I sb_2__2_:left_top_grid_pin_1_[0] I *L 0 *C 783.380 892.090 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:2 *C 783.380 898.223 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:3 *C 783.373 898.280 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:4 *C 771.428 898.280 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:5 *C 771.420 898.338 + +*CAP +0 grid_io_top_2__3_:bottom_width_0_height_0__pin_1_lower[0] 0.0002681144 +1 sb_2__2_:left_top_grid_pin_1_[0] 0.0002953574 +2 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:2 0.0002953574 +3 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:3 0.0005679925 +4 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:4 0.0005679925 +5 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:5 0.0002681144 + +*RES +0 grid_io_top_2__3_:bottom_width_0_height_0__pin_1_lower[0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:5 0.004261161 +1 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:2 sb_2__2_:left_top_grid_pin_1_[0] 0.005475447 +2 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:3 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:5 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:4 grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]:3 0.001871383 + +*END + +*D_NET sb_0__0__0_chanx_right_out[8] 0.00117119 //LENGTH 7.660 LUMPCC 0.000502302 DR + +*CONN +*I sb_0__0_:chanx_right_out[8] O *L 0 *C 400.050 327.760 +*I cbx_1__0_:chanx_left_in[8] I *L 0 *C 407.710 327.760 + +*CAP +0 sb_0__0_:chanx_right_out[8] 0.0003344439 +1 cbx_1__0_:chanx_left_in[8] 0.0003344439 +2 sb_0__0_:chanx_right_out[8] sb_0__0_:chanx_right_in[6] 7.471367e-05 +3 cbx_1__0_:chanx_left_in[8] cbx_1__0_:chanx_left_out[6] 7.471367e-05 +4 sb_0__0_:chanx_right_out[8] sb_0__0_:chanx_right_out[4] 0.0001764373 +5 cbx_1__0_:chanx_left_in[8] cbx_1__0_:chanx_left_in[4] 0.0001764373 + +*RES +0 sb_0__0_:chanx_right_out[8] cbx_1__0_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[0] 0.001217314 //LENGTH 11.020 LUMPCC 0.0006231852 DR + +*CONN +*I sb_0__0_:chany_top_out[0] O *L 0 *C 329.820 397.050 +*I cby_0__1_:chany_bottom_in[0] I *L 0 *C 329.820 408.070 + +*CAP +0 sb_0__0_:chany_top_out[0] 0.0002970644 +1 cby_0__1_:chany_bottom_in[0] 0.0002970644 +2 sb_0__0_:chany_top_out[0] sb_0__0_:chany_top_in[4] 0.0001557963 +3 cby_0__1_:chany_bottom_in[0] cby_0__1_:chany_bottom_out[4] 0.0001557963 +4 sb_0__0_:chany_top_out[0] sb_0__0_:chany_top_in[11] 0.0001557963 +5 cby_0__1_:chany_bottom_in[0] cby_0__1_:chany_bottom_out[11] 0.0001557963 + +*RES +0 sb_0__0_:chany_top_out[0] cby_0__1_:chany_bottom_in[0] 0.009839285 + +*END + +*D_NET sb_0__0__0_chany_top_out[15] 0.0015309 //LENGTH 11.180 LUMPCC 0.0008817699 DR + +*CONN +*I sb_0__0_:chany_top_out[15] O *L 0 *C 333.040 396.970 +*I cby_0__1_:chany_bottom_in[15] I *L 0 *C 333.040 408.150 + +*CAP +0 sb_0__0_:chany_top_out[15] 0.0003245649 +1 cby_0__1_:chany_bottom_in[15] 0.0003245649 +2 sb_0__0_:chany_top_out[15] sb_0__0_:chany_top_in[18] 0.0002226262 +3 cby_0__1_:chany_bottom_in[15] cby_0__1_:chany_bottom_out[18] 0.0002226262 +4 sb_0__0_:chany_top_out[15] sb_0__0_:chany_top_out[18] 0.0002182588 +5 cby_0__1_:chany_bottom_in[15] cby_0__1_:chany_bottom_in[18] 0.0002182588 + +*RES +0 sb_0__0_:chany_top_out[15] cby_0__1_:chany_bottom_in[15] 0.001751533 + +*END + +*D_NET sb_0__1__0_chanx_right_out[7] 0.001326256 //LENGTH 7.660 LUMPCC 0.0006110418 DR + +*CONN +*I sb_0__1_:chanx_right_out[7] O *L 0 *C 400.050 563.040 +*I cbx_1__1_:chanx_left_in[7] I *L 0 *C 407.710 563.040 + +*CAP +0 sb_0__1_:chanx_right_out[7] 0.000357607 +1 cbx_1__1_:chanx_left_in[7] 0.000357607 +2 sb_0__1_:chanx_right_out[7] sb_0__1_:chanx_right_in[10] 0.0001502787 +3 cbx_1__1_:chanx_left_in[7] cbx_1__1_:chanx_left_out[10] 0.0001502787 +4 sb_0__1_:chanx_right_out[7] sb_0__1_:chanx_right_in[17] 0.0001552422 +5 cbx_1__1_:chanx_left_in[7] cbx_1__1_:chanx_left_out[17] 0.0001552422 + +*RES +0 sb_0__1_:chanx_right_out[7] cbx_1__1_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[2] 0.0012836 //LENGTH 11.020 LUMPCC 0.0005182978 DR + +*CONN +*I sb_0__1_:chany_bottom_out[2] O *L 0 *C 353.740 527.750 +*I cby_0__1_:chany_top_in[2] I *L 0 *C 353.740 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[2] 0.0003826512 +1 cby_0__1_:chany_top_in[2] 0.0003826512 +2 sb_0__1_:chany_bottom_out[2] sb_0__1_:chany_bottom_in[0] 0.0001295745 +3 cby_0__1_:chany_top_in[2] cby_0__1_:chany_top_out[0] 0.0001295745 +4 sb_0__1_:chany_bottom_out[2] sb_0__1_:chany_bottom_out[12] 0.0001295745 +5 cby_0__1_:chany_top_in[2] cby_0__1_:chany_top_in[12] 0.0001295745 + +*RES +0 sb_0__1_:chany_bottom_out[2] cby_0__1_:chany_top_in[2] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[16] 0.001214561 //LENGTH 11.020 LUMPCC 0.0002269496 DR + +*CONN +*I sb_0__1_:chany_bottom_out[16] O *L 0 *C 315.560 527.750 +*I cby_0__1_:chany_top_in[16] I *L 0 *C 315.560 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[16] 0.0004938055 +1 cby_0__1_:chany_top_in[16] 0.0004938055 +2 sb_0__1_:chany_bottom_out[16] sb_0__1_:chany_bottom_in[17] 7.104993e-05 +3 cby_0__1_:chany_top_in[16] cby_0__1_:chany_top_out[17] 7.104993e-05 +4 sb_0__1_:chany_bottom_out[16] sb_0__1_:chany_bottom_in[18] 4.242487e-05 +5 cby_0__1_:chany_top_in[16] cby_0__1_:chany_top_out[18] 4.242487e-05 + +*RES +0 sb_0__1_:chany_bottom_out[16] cby_0__1_:chany_top_in[16] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_top_out[11] 0.001253941 //LENGTH 11.020 LUMPCC 0.0005649955 DR + +*CONN +*I sb_0__1_:chany_top_out[11] O *L 0 *C 338.100 658.170 +*I cby_0__2_:chany_bottom_in[11] I *L 0 *C 338.100 669.190 +*N sb_0__1__0_chany_top_out[11]:2 *C 338.100 667.520 +*N sb_0__1__0_chany_top_out[11]:3 *C 338.100 667.519 + +*CAP +0 sb_0__1_:chany_top_out[11] 0.000233132 +1 cby_0__2_:chany_bottom_in[11] 0.0001113409 +2 sb_0__1__0_chany_top_out[11]:2 0.0001113409 +3 sb_0__1__0_chany_top_out[11]:3 0.000233132 +4 sb_0__1_:chany_top_out[11] sb_0__1_:chany_top_in[9] 0.0001340003 +5 cby_0__2_:chany_bottom_in[11] cby_0__2_:chany_bottom_out[9] 7.248536e-06 +6 sb_0__1__0_chany_top_out[11]:2 cby_0__1__1_chany_bottom_out[9]:3 7.248536e-06 +7 sb_0__1__0_chany_top_out[11]:3 cby_0__1__1_chany_bottom_out[9]:2 0.0001340003 +8 sb_0__1_:chany_top_out[11] sb_0__1_:chany_top_in[10] 0.0001340003 +9 cby_0__2_:chany_bottom_in[11] cby_0__2_:chany_bottom_out[10] 7.248536e-06 +10 sb_0__1__0_chany_top_out[11]:2 cby_0__1__1_chany_bottom_out[10]:3 7.248536e-06 +11 sb_0__1__0_chany_top_out[11]:3 cby_0__1__1_chany_bottom_out[10]:2 0.0001340003 + +*RES +0 sb_0__1_:chany_top_out[11] sb_0__1__0_chany_top_out[11]:3 0.008347321 +1 sb_0__1__0_chany_top_out[11]:2 cby_0__2_:chany_bottom_in[11] 0.001491072 +2 sb_0__1__0_chany_top_out[11]:3 sb_0__1__0_chany_top_out[11]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[2] 0.001220366 //LENGTH 7.660 LUMPCC 0.000442428 DR + +*CONN +*I sb_0__2_:chanx_right_out[2] O *L 0 *C 400.050 841.840 +*I cbx_1__2_:chanx_left_in[2] I *L 0 *C 407.710 841.840 + +*CAP +0 sb_0__2_:chanx_right_out[2] 0.000388969 +1 cbx_1__2_:chanx_left_in[2] 0.000388969 +2 sb_0__2_:chanx_right_out[2] sb_0__2_:chanx_right_in[15] 5.73949e-05 +3 cbx_1__2_:chanx_left_in[2] cbx_1__2_:chanx_left_out[15] 5.73949e-05 +4 sb_0__2_:chanx_right_out[2] sb_0__2_:chanx_right_out[10] 0.0001638191 +5 cbx_1__2_:chanx_left_in[2] cbx_1__2_:chanx_left_in[10] 0.0001638191 + +*RES +0 sb_0__2_:chanx_right_out[2] cbx_1__2_:chanx_left_in[2] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[15] 0.00129774 //LENGTH 7.660 LUMPCC 0.0006571593 DR + +*CONN +*I sb_0__2_:chanx_right_out[15] O *L 0 *C 400.050 856.800 +*I cbx_1__2_:chanx_left_in[15] I *L 0 *C 407.710 856.800 + +*CAP +0 sb_0__2_:chanx_right_out[15] 0.0003202906 +1 cbx_1__2_:chanx_left_in[15] 0.0003202906 +2 sb_0__2_:chanx_right_out[15] sb_0__2_:chanx_right_out[11] 0.0001638813 +3 cbx_1__2_:chanx_left_in[15] cbx_1__2_:chanx_left_in[11] 0.0001638813 +4 sb_0__2_:chanx_right_out[15] sb_0__2_:chanx_right_out[13] 0.0001646984 +5 cbx_1__2_:chanx_left_in[15] cbx_1__2_:chanx_left_in[13] 0.0001646984 + +*RES +0 sb_0__2_:chanx_right_out[15] cbx_1__2_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[10] 0.001248554 //LENGTH 11.020 LUMPCC 0.0005760535 DR + +*CONN +*I sb_0__2_:chany_bottom_out[10] O *L 0 *C 329.820 788.870 +*I cby_0__2_:chany_top_in[10] I *L 0 *C 329.820 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[10] 0.0003362503 +1 cby_0__2_:chany_top_in[10] 0.0003362503 +2 sb_0__2_:chany_bottom_out[10] sb_0__2_:chany_bottom_in[14] 0.0001440134 +3 cby_0__2_:chany_top_in[10] cby_0__2_:chany_top_out[14] 0.0001440134 +4 sb_0__2_:chany_bottom_out[10] sb_0__2_:chany_bottom_in[16] 0.0001440134 +5 cby_0__2_:chany_top_in[10] cby_0__2_:chany_top_out[16] 0.0001440134 + +*RES +0 sb_0__2_:chany_bottom_out[10] cby_0__2_:chany_top_in[10] 0.009839286 + +*END + +*D_NET sb_1__0__0_chanx_left_out[3] 0.001389168 //LENGTH 7.660 LUMPCC 0.000568696 DR + +*CONN +*I sb_1__0_:chanx_left_out[3] O *L 0 *C 519.950 353.600 +*I cbx_1__0_:chanx_right_in[3] I *L 0 *C 512.290 353.600 + +*CAP +0 sb_1__0_:chanx_left_out[3] 0.0004102358 +1 cbx_1__0_:chanx_right_in[3] 0.0004102358 +2 sb_1__0_:chanx_left_out[3] sb_1__0_:chanx_left_out[5] 0.0001419191 +3 cbx_1__0_:chanx_right_in[3] cbx_1__0_:chanx_right_in[5] 0.0001419191 +4 sb_1__0_:chanx_left_out[3] sb_1__0_:chanx_left_out[19] 0.0001424289 +5 cbx_1__0_:chanx_right_in[3] cbx_1__0_:chanx_right_in[19] 0.0001424289 + +*RES +0 sb_1__0_:chanx_left_out[3] cbx_1__0_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[16] 0.001235045 //LENGTH 7.660 LUMPCC 0.0004600095 DR + +*CONN +*I sb_1__0_:chanx_left_out[16] O *L 0 *C 519.950 325.040 +*I cbx_1__0_:chanx_right_in[16] I *L 0 *C 512.290 325.040 + +*CAP +0 sb_1__0_:chanx_left_out[16] 0.0003875176 +1 cbx_1__0_:chanx_right_in[16] 0.0003875176 +2 sb_1__0_:chanx_left_out[16] sb_1__0_:chanx_left_in[8] 0.0001602759 +3 cbx_1__0_:chanx_right_in[16] cbx_1__0_:chanx_right_out[8] 0.0001602759 +4 sb_1__0_:chanx_left_out[16] sb_1__0_:chanx_left_in[16] 6.972889e-05 +5 cbx_1__0_:chanx_right_in[16] cbx_1__0_:chanx_right_out[16] 6.972889e-05 + +*RES +0 sb_1__0_:chanx_left_out[16] cbx_1__0_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[9] 0.001413302 //LENGTH 7.660 LUMPCC 0.0005598758 DR + +*CONN +*I sb_1__0_:chanx_right_out[9] O *L 0 *C 661.330 334.560 +*I cbx_2__0_:chanx_left_in[9] I *L 0 *C 668.990 334.560 +*N sb_1__0__0_chanx_right_out[9]:2 *C 667.520 334.560 +*N sb_1__0__0_chanx_right_out[9]:3 *C 667.519 334.560 + +*CAP +0 sb_1__0_:chanx_right_out[9] 0.0002471929 +1 cbx_2__0_:chanx_left_in[9] 0.00017952 +2 sb_1__0__0_chanx_right_out[9]:2 0.00017952 +3 sb_1__0__0_chanx_right_out[9]:3 0.0002471929 +4 sb_1__0_:chanx_right_out[9] sb_1__0_:chanx_right_in[15] 0.0001295691 +5 cbx_2__0_:chanx_left_in[9] cbx_2__0_:chanx_left_out[15] 6.577123e-06 +6 sb_1__0__0_chanx_right_out[9]:2 cbx_1__0__1_chanx_left_out[15]:3 6.577123e-06 +7 sb_1__0__0_chanx_right_out[9]:3 cbx_1__0__1_chanx_left_out[15]:2 0.0001295691 +8 sb_1__0_:chanx_right_out[9] sb_1__0_:chanx_right_out[15] 0.000133926 +9 cbx_2__0_:chanx_left_in[9] cbx_2__0_:chanx_left_in[15] 9.865685e-06 +10 sb_1__0__0_chanx_right_out[9]:2 sb_1__0__0_chanx_right_out[15]:2 9.865685e-06 +11 sb_1__0__0_chanx_right_out[9]:3 sb_1__0__0_chanx_right_out[15]:3 0.000133926 + +*RES +0 sb_1__0_:chanx_right_out[9] sb_1__0__0_chanx_right_out[9]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[9]:2 cbx_2__0_:chanx_left_in[9] 0.0002303 +2 sb_1__0__0_chanx_right_out[9]:3 sb_1__0__0_chanx_right_out[9]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[5] 0.001188504 //LENGTH 11.020 LUMPCC 0.0004821397 DR + +*CONN +*I sb_1__0_:chany_top_out[5] O *L 0 *C 603.520 397.050 +*I cby_1__1_:chany_bottom_in[5] I *L 0 *C 603.520 408.070 + +*CAP +0 sb_1__0_:chany_top_out[5] 0.0003531821 +1 cby_1__1_:chany_bottom_in[5] 0.0003531821 +2 sb_1__0_:chany_top_out[5] sb_1__0_:chany_top_in[2] 9.50579e-05 +3 cby_1__1_:chany_bottom_in[5] cby_1__1_:chany_bottom_out[2] 9.50579e-05 +4 sb_1__0_:chany_top_out[5] sb_1__0_:chany_top_in[18] 0.0001460119 +5 cby_1__1_:chany_bottom_in[5] cby_1__1_:chany_bottom_out[18] 0.0001460119 + +*RES +0 sb_1__0_:chany_top_out[5] cby_1__1_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET sb_1__0__0_chany_top_out[18] 0.001147278 //LENGTH 11.020 LUMPCC 0.0004373166 DR + +*CONN +*I sb_1__0_:chany_top_out[18] O *L 0 *C 615.480 397.050 +*I cby_1__1_:chany_bottom_in[18] I *L 0 *C 615.480 408.070 + +*CAP +0 sb_1__0_:chany_top_out[18] 0.0003549806 +1 cby_1__1_:chany_bottom_in[18] 0.0003549806 +2 sb_1__0_:chany_top_out[18] sb_1__0_:chany_top_out[10] 0.0001527924 +3 cby_1__1_:chany_bottom_in[18] cby_1__1_:chany_bottom_in[10] 0.0001527924 +4 sb_1__0_:chany_top_out[18] sb_1__0_:chany_top_out[11] 6.586591e-05 +5 cby_1__1_:chany_bottom_in[18] cby_1__1_:chany_bottom_in[11] 6.586591e-05 + +*RES +0 sb_1__0_:chany_top_out[18] cby_1__1_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET sb_1__1__0_chanx_left_out[12] 0.001367473 //LENGTH 7.660 LUMPCC 0.0004098431 DR + +*CONN +*I sb_1__1_:chanx_left_out[12] O *L 0 *C 519.950 572.560 +*I cbx_1__1_:chanx_right_in[12] I *L 0 *C 512.290 572.560 + +*CAP +0 sb_1__1_:chanx_left_out[12] 0.0004788151 +1 cbx_1__1_:chanx_right_in[12] 0.0004788151 +2 sb_1__1_:chanx_left_out[12] sb_1__1_:chanx_left_in[8] 0.0001398553 +3 cbx_1__1_:chanx_right_in[12] cbx_1__1_:chanx_right_out[8] 0.0001398553 +4 sb_1__1_:chanx_left_out[12] sb_1__1_:chanx_left_in[19] 4.232395e-05 +5 cbx_1__1_:chanx_right_in[12] cbx_1__1__0_chanx_right_out[19]:2 4.232395e-05 +6 sb_1__1_:chanx_left_out[12] sb_1__1_:chanx_left_out[5] 2.274232e-05 +7 cbx_1__1_:chanx_right_in[12] cbx_1__1_:chanx_right_in[5] 2.274232e-05 + +*RES +0 sb_1__1_:chanx_left_out[12] cbx_1__1_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[5] 0.001341738 //LENGTH 7.660 LUMPCC 0.0002368634 DR + +*CONN +*I sb_1__1_:chanx_right_out[5] O *L 0 *C 661.330 599.760 +*I cbx_2__1_:chanx_left_in[5] I *L 0 *C 668.990 599.760 +*N sb_1__1__0_chanx_right_out[5]:2 *C 667.520 599.760 +*N sb_1__1__0_chanx_right_out[5]:3 *C 667.519 599.760 + +*CAP +0 sb_1__1_:chanx_right_out[5] 0.0003538337 +1 cbx_2__1_:chanx_left_in[5] 0.0001986036 +2 sb_1__1__0_chanx_right_out[5]:2 0.0001986036 +3 sb_1__1__0_chanx_right_out[5]:3 0.0003538337 +4 sb_1__1_:chanx_right_out[5] sb_1__1_:chanx_right_in[7] 4.950478e-05 +5 sb_1__1__0_chanx_right_out[5]:3 cbx_1__1__1_chanx_left_out[7]:2 4.950478e-05 +6 sb_1__1_:chanx_right_out[5] sb_1__1_:chanx_right_out[3] 6.892695e-05 +7 sb_1__1__0_chanx_right_out[5]:3 sb_1__1__0_chanx_right_out[3]:3 6.892695e-05 + +*RES +0 sb_1__1_:chanx_right_out[5] sb_1__1__0_chanx_right_out[5]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[5]:2 cbx_2__1_:chanx_left_in[5] 0.0002303 +2 sb_1__1__0_chanx_right_out[5]:3 sb_1__1__0_chanx_right_out[5]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[14] 0.00150538 //LENGTH 7.660 LUMPCC 0.000345863 DR + +*CONN +*I sb_1__1_:chanx_right_out[14] O *L 0 *C 661.330 575.280 +*I cbx_2__1_:chanx_left_in[14] I *L 0 *C 668.990 575.280 +*N sb_1__1__0_chanx_right_out[14]:2 *C 667.520 575.280 +*N sb_1__1__0_chanx_right_out[14]:3 *C 667.519 575.280 + +*CAP +0 sb_1__1_:chanx_right_out[14] 0.0003604934 +1 cbx_2__1_:chanx_left_in[14] 0.0002192653 +2 sb_1__1__0_chanx_right_out[14]:2 0.0002192653 +3 sb_1__1__0_chanx_right_out[14]:3 0.0003604934 +4 sb_1__1_:chanx_right_out[14] sb_1__1_:chanx_right_in[0] 4.437987e-05 +5 sb_1__1__0_chanx_right_out[14]:3 cbx_1__1__1_chanx_left_out[0]:2 4.437987e-05 +6 sb_1__1_:chanx_right_out[14] sb_1__1_:chanx_right_in[9] 2.163164e-05 +7 sb_1__1__0_chanx_right_out[14]:3 cbx_1__1__1_chanx_left_out[9]:2 2.163164e-05 +8 sb_1__1_:chanx_right_out[14] sb_1__1_:chanx_right_out[8] 0.00010692 +9 sb_1__1__0_chanx_right_out[14]:3 sb_1__1__0_chanx_right_out[8]:3 0.00010692 + +*RES +0 sb_1__1_:chanx_right_out[14] sb_1__1__0_chanx_right_out[14]:3 0.0009696101 +1 sb_1__1__0_chanx_right_out[14]:2 cbx_2__1_:chanx_left_in[14] 0.0002303 +2 sb_1__1__0_chanx_right_out[14]:3 sb_1__1__0_chanx_right_out[14]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[8] 0.001293202 //LENGTH 11.020 LUMPCC 0.0005003437 DR + +*CONN +*I sb_1__1_:chany_bottom_out[8] O *L 0 *C 583.280 527.750 +*I cby_1__1_:chany_top_in[8] I *L 0 *C 583.280 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[8] 0.000396429 +1 cby_1__1_:chany_top_in[8] 0.000396429 +2 sb_1__1_:chany_bottom_out[8] sb_1__1_:chany_bottom_in[10] 0.0001247684 +3 cby_1__1_:chany_top_in[8] cby_1__1_:chany_top_out[10] 0.0001247684 +4 sb_1__1_:chany_bottom_out[8] sb_1__1_:chany_bottom_out[16] 0.0001254034 +5 cby_1__1_:chany_top_in[8] cby_1__1_:chany_top_in[16] 0.0001254034 + +*RES +0 sb_1__1_:chany_bottom_out[8] cby_1__1_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[2] 0.001226785 //LENGTH 11.020 LUMPCC 0.0006029896 DR + +*CONN +*I sb_1__1_:chany_top_out[2] O *L 0 *C 597.540 658.170 +*I cby_1__2_:chany_bottom_in[2] I *L 0 *C 597.540 669.190 +*N sb_1__1__0_chany_top_out[2]:2 *C 597.540 667.520 +*N sb_1__1__0_chany_top_out[2]:3 *C 597.540 667.519 + +*CAP +0 sb_1__1_:chany_top_out[2] 0.0002014367 +1 cby_1__2_:chany_bottom_in[2] 0.0001104609 +2 sb_1__1__0_chany_top_out[2]:2 0.0001104609 +3 sb_1__1__0_chany_top_out[2]:3 0.0002014367 +4 sb_1__1_:chany_top_out[2] sb_1__1_:chany_top_out[0] 0.000143306 +5 cby_1__2_:chany_bottom_in[2] cby_1__2_:chany_bottom_in[0] 7.441422e-06 +6 sb_1__1__0_chany_top_out[2]:2 sb_1__1__0_chany_top_out[0]:2 7.441422e-06 +7 sb_1__1__0_chany_top_out[2]:3 sb_1__1__0_chany_top_out[0]:3 0.000143306 +8 sb_1__1_:chany_top_out[2] sb_1__1_:chany_top_out[19] 0.000143306 +9 cby_1__2_:chany_bottom_in[2] cby_1__2_:chany_bottom_in[19] 7.441422e-06 +10 sb_1__1__0_chany_top_out[2]:2 sb_1__1__0_chany_top_out[19]:2 7.441422e-06 +11 sb_1__1__0_chany_top_out[2]:3 sb_1__1__0_chany_top_out[19]:3 0.000143306 + +*RES +0 sb_1__1_:chany_top_out[2] sb_1__1__0_chany_top_out[2]:3 0.008347321 +1 sb_1__1__0_chany_top_out[2]:2 cby_1__2_:chany_bottom_in[2] 0.001491072 +2 sb_1__1__0_chany_top_out[2]:3 sb_1__1__0_chany_top_out[2]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[14] 0.001178095 //LENGTH 11.020 LUMPCC 0.0004990617 DR + +*CONN +*I sb_1__1_:chany_top_out[14] O *L 0 *C 617.320 658.170 +*I cby_1__2_:chany_bottom_in[14] I *L 0 *C 617.320 669.190 +*N sb_1__1__0_chany_top_out[14]:2 *C 617.320 667.520 +*N sb_1__1__0_chany_top_out[14]:3 *C 617.320 667.519 + +*CAP +0 sb_1__1_:chany_top_out[14] 0.000222731 +1 cby_1__2_:chany_bottom_in[14] 0.0001167858 +2 sb_1__1__0_chany_top_out[14]:2 0.0001167858 +3 sb_1__1__0_chany_top_out[14]:3 0.000222731 +4 sb_1__1_:chany_top_out[14] sb_1__1_:chany_top_out[4] 9.743153e-05 +5 cby_1__2_:chany_bottom_in[14] cby_1__2_:chany_bottom_in[4] 1.522179e-06 +6 sb_1__1__0_chany_top_out[14]:2 sb_1__1__0_chany_top_out[4]:2 1.522179e-06 +7 sb_1__1__0_chany_top_out[14]:3 sb_1__1__0_chany_top_out[4]:3 9.743153e-05 +8 sb_1__1_:chany_top_out[14] sb_1__1_:chany_top_out[10] 0.0001431353 +9 cby_1__2_:chany_bottom_in[14] cby_1__2_:chany_bottom_in[10] 7.441891e-06 +10 sb_1__1__0_chany_top_out[14]:2 sb_1__1__0_chany_top_out[10]:2 7.441891e-06 +11 sb_1__1__0_chany_top_out[14]:3 sb_1__1__0_chany_top_out[10]:3 0.0001431353 + +*RES +0 sb_1__1_:chany_top_out[14] sb_1__1__0_chany_top_out[14]:3 0.008347322 +1 sb_1__1__0_chany_top_out[14]:2 cby_1__2_:chany_bottom_in[14] 0.001491072 +2 sb_1__1__0_chany_top_out[14]:3 sb_1__1__0_chany_top_out[14]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[6] 0.001395867 //LENGTH 7.660 LUMPCC 0.0005632931 DR + +*CONN +*I sb_1__2_:chanx_left_out[6] O *L 0 *C 519.950 832.320 +*I cbx_1__2_:chanx_right_in[6] I *L 0 *C 512.290 832.320 + +*CAP +0 sb_1__2_:chanx_left_out[6] 0.0004162869 +1 cbx_1__2_:chanx_right_in[6] 0.0004162869 +2 sb_1__2_:chanx_left_out[6] sb_1__2_:chanx_left_in[1] 0.0001408233 +3 cbx_1__2_:chanx_right_in[6] cbx_1__2_:chanx_right_out[1] 0.0001408233 +4 sb_1__2_:chanx_left_out[6] sb_1__2_:chanx_left_out[15] 0.0001408233 +5 cbx_1__2_:chanx_right_in[6] cbx_1__2_:chanx_right_in[15] 0.0001408233 + +*RES +0 sb_1__2_:chanx_left_out[6] cbx_1__2_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[16] 0.001365055 //LENGTH 7.660 LUMPCC 0.000591417 DR + +*CONN +*I sb_1__2_:chanx_left_out[16] O *L 0 *C 519.950 843.200 +*I cbx_1__2_:chanx_right_in[16] I *L 0 *C 512.290 843.200 + +*CAP +0 sb_1__2_:chanx_left_out[16] 0.0003868192 +1 cbx_1__2_:chanx_right_in[16] 0.0003868192 +2 sb_1__2_:chanx_left_out[16] sb_1__2_:chanx_left_in[16] 0.0001475856 +3 cbx_1__2_:chanx_right_in[16] cbx_1__2_:chanx_right_out[16] 0.0001475856 +4 sb_1__2_:chanx_left_out[16] sb_1__2_:chanx_left_in[17] 0.0001481229 +5 cbx_1__2_:chanx_right_in[16] cbx_1__2_:chanx_right_out[17] 0.0001481229 + +*RES +0 sb_1__2_:chanx_left_out[16] cbx_1__2_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[9] 0.001480754 //LENGTH 7.660 LUMPCC 0.0003563608 DR + +*CONN +*I sb_1__2_:chanx_right_out[9] O *L 0 *C 661.330 833.680 +*I cbx_2__2_:chanx_left_in[9] I *L 0 *C 668.990 833.680 +*N sb_1__2__0_chanx_right_out[9]:2 *C 667.520 833.680 +*N sb_1__2__0_chanx_right_out[9]:3 *C 667.519 833.680 + +*CAP +0 sb_1__2_:chanx_right_out[9] 0.0003421581 +1 cbx_2__2_:chanx_left_in[9] 0.0002200387 +2 sb_1__2__0_chanx_right_out[9]:2 0.0002200387 +3 sb_1__2__0_chanx_right_out[9]:3 0.0003421581 +4 sb_1__2_:chanx_right_out[9] sb_1__2_:chanx_right_in[14] 5.75082e-05 +5 sb_1__2__0_chanx_right_out[9]:3 cbx_1__2__1_chanx_left_out[14]:2 5.75082e-05 +6 sb_1__2_:chanx_right_out[9] sb_1__2_:chanx_right_out[19] 0.0001206722 +7 sb_1__2__0_chanx_right_out[9]:3 sb_1__2__0_chanx_right_out[19]:3 0.0001206722 + +*RES +0 sb_1__2_:chanx_right_out[9] sb_1__2__0_chanx_right_out[9]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[9]:2 cbx_2__2_:chanx_left_in[9] 0.0002303 +2 sb_1__2__0_chanx_right_out[9]:3 sb_1__2__0_chanx_right_out[9]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[18] 0.001496472 //LENGTH 7.660 LUMPCC 0.0004832933 DR + +*CONN +*I sb_1__2_:chanx_right_out[18] O *L 0 *C 661.330 878.560 +*I cbx_2__2_:chanx_left_in[18] I *L 0 *C 668.990 878.560 +*N sb_1__2__0_chanx_right_out[18]:2 *C 667.520 878.560 +*N sb_1__2__0_chanx_right_out[18]:3 *C 667.519 878.560 + +*CAP +0 sb_1__2_:chanx_right_out[18] 0.0003059506 +1 cbx_2__2_:chanx_left_in[18] 0.0002006385 +2 sb_1__2__0_chanx_right_out[18]:2 0.0002006385 +3 sb_1__2__0_chanx_right_out[18]:3 0.0003059506 +4 sb_1__2_:chanx_right_out[18] sb_1__2_:chanx_right_out[14] 0.0001090126 +5 sb_1__2__0_chanx_right_out[18]:3 sb_1__2__0_chanx_right_out[14]:3 0.0001090126 +6 sb_1__2_:chanx_right_out[18] sb_1__2_:chanx_right_out[17] 0.0001260579 +7 cbx_2__2_:chanx_left_in[18] cbx_2__2_:chanx_left_in[17] 6.576165e-06 +8 sb_1__2__0_chanx_right_out[18]:2 sb_1__2__0_chanx_right_out[17]:2 6.576165e-06 +9 sb_1__2__0_chanx_right_out[18]:3 sb_1__2__0_chanx_right_out[17]:3 0.0001260579 + +*RES +0 sb_1__2_:chanx_right_out[18] sb_1__2__0_chanx_right_out[18]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[18]:2 cbx_2__2_:chanx_left_in[18] 0.0002303 +2 sb_1__2__0_chanx_right_out[18]:3 sb_1__2__0_chanx_right_out[18]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[7] 0.001279574 //LENGTH 11.020 LUMPCC 0.0005195668 DR + +*CONN +*I sb_1__2_:chany_bottom_out[7] O *L 0 *C 580.520 788.870 +*I cby_1__2_:chany_top_in[7] I *L 0 *C 580.520 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[7] 0.0003800038 +1 cby_1__2_:chany_top_in[7] 0.0003800038 +2 sb_1__2_:chany_bottom_out[7] sb_1__2_:chany_bottom_out[1] 0.0001298917 +3 cby_1__2_:chany_top_in[7] cby_1__2_:chany_top_in[1] 0.0001298917 +4 sb_1__2_:chany_bottom_out[7] sb_1__2_:chany_bottom_out[13] 0.0001298917 +5 cby_1__2_:chany_top_in[7] cby_1__2_:chany_top_in[13] 0.0001298917 + +*RES +0 sb_1__2_:chany_bottom_out[7] cby_1__2_:chany_top_in[7] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[19] 0.001272058 //LENGTH 11.020 LUMPCC 0.0005339056 DR + +*CONN +*I sb_1__2_:chany_bottom_out[19] O *L 0 *C 590.640 788.870 +*I cby_1__2_:chany_top_in[19] I *L 0 *C 590.640 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[19] 0.0003690762 +1 cby_1__2_:chany_top_in[19] 0.0003690762 +2 sb_1__2_:chany_bottom_out[19] sb_1__2_:chany_bottom_in[17] 0.0001334764 +3 cby_1__2_:chany_top_in[19] cby_1__2_:chany_top_out[17] 0.0001334764 +4 sb_1__2_:chany_bottom_out[19] sb_1__2_:chany_bottom_out[5] 0.0001334764 +5 cby_1__2_:chany_top_in[19] cby_1__2_:chany_top_in[5] 0.0001334764 + +*RES +0 sb_1__2_:chany_bottom_out[19] cby_1__2_:chany_top_in[19] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[11] 0.001455383 //LENGTH 7.660 LUMPCC 0.0005468546 DR + +*CONN +*I sb_2__0_:chanx_left_out[11] O *L 0 *C 781.230 331.840 +*I cbx_2__0_:chanx_right_in[11] I *L 0 *C 773.570 331.840 + +*CAP +0 sb_2__0_:chanx_left_out[11] 0.0004542644 +1 cbx_2__0_:chanx_right_in[11] 0.0004542644 +2 sb_2__0_:chanx_left_out[11] sb_2__0_:chanx_left_in[12] 0.0001297982 +3 cbx_2__0_:chanx_right_in[11] cbx_2__0_:chanx_right_out[12] 0.0001297982 +4 sb_2__0_:chanx_left_out[11] sb_2__0_:chanx_left_out[15] 0.0001436291 +5 cbx_2__0_:chanx_right_in[11] cbx_2__0_:chanx_right_in[15] 0.0001436291 + +*RES +0 sb_2__0_:chanx_left_out[11] cbx_2__0_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[0] 0.001228799 //LENGTH 11.020 LUMPCC 0.0005917205 DR + +*CONN +*I sb_2__0_:chany_top_out[0] O *L 0 *C 857.900 397.050 +*I cby_2__1_:chany_bottom_in[0] I *L 0 *C 857.900 408.070 + +*CAP +0 sb_2__0_:chany_top_out[0] 0.0003185394 +1 cby_2__1_:chany_bottom_in[0] 0.0003185394 +2 sb_2__0_:chany_top_out[0] sb_2__0_:chany_top_in[11] 0.0001479301 +3 cby_2__1_:chany_bottom_in[0] cby_2__1_:chany_bottom_out[11] 0.0001479301 +4 sb_2__0_:chany_top_out[0] sb_2__0_:chany_top_out[2] 0.0001479301 +5 cby_2__1_:chany_bottom_in[0] cby_2__1_:chany_bottom_in[2] 0.0001479301 + +*RES +0 sb_2__0_:chany_top_out[0] cby_2__1_:chany_bottom_in[0] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[12] 0.001236828 //LENGTH 11.020 LUMPCC 0.0005862518 DR + +*CONN +*I sb_2__0_:chany_top_out[12] O *L 0 *C 860.660 397.050 +*I cby_2__1_:chany_bottom_in[12] I *L 0 *C 860.660 408.070 + +*CAP +0 sb_2__0_:chany_top_out[12] 0.0003252879 +1 cby_2__1_:chany_bottom_in[12] 0.0003252879 +2 sb_2__0_:chany_top_out[12] sb_2__0_:chany_top_in[0] 0.0001451958 +3 cby_2__1_:chany_bottom_in[12] cby_2__1_:chany_bottom_out[0] 0.0001451958 +4 sb_2__0_:chany_top_out[12] sb_2__0_:chany_top_out[19] 0.0001479301 +5 cby_2__1_:chany_bottom_in[12] cby_2__1_:chany_bottom_in[19] 0.0001479301 + +*RES +0 sb_2__0_:chany_top_out[12] cby_2__1_:chany_bottom_in[12] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[6] 0.001534908 //LENGTH 7.660 LUMPCC 0.0002613808 DR + +*CONN +*I sb_2__1_:chanx_left_out[6] O *L 0 *C 781.230 578.000 +*I cbx_2__1_:chanx_right_in[6] I *L 0 *C 773.570 578.000 + +*CAP +0 sb_2__1_:chanx_left_out[6] 0.0006367636 +1 cbx_2__1_:chanx_right_in[6] 0.0006367636 +2 sb_2__1_:chanx_left_out[6] sb_2__1_:chanx_left_out[8] 9.437184e-05 +3 cbx_2__1_:chanx_right_in[6] cbx_2__1_:chanx_right_in[8] 9.437184e-05 +4 sb_2__1_:chanx_left_out[6] sb_2__1_:chanx_left_out[10] 3.631858e-05 +5 cbx_2__1_:chanx_right_in[6] cbx_2__1_:chanx_right_in[10] 3.631858e-05 + +*RES +0 sb_2__1_:chanx_left_out[6] cbx_2__1_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[2] 0.001209144 //LENGTH 11.020 LUMPCC 0.0002659477 DR + +*CONN +*I sb_2__1_:chany_bottom_out[2] O *L 0 *C 833.520 527.750 +*I cby_2__1_:chany_top_in[2] I *L 0 *C 833.520 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[2] 0.000471598 +1 cby_2__1_:chany_top_in[2] 0.000471598 +2 sb_2__1_:chany_bottom_out[2] sb_2__1_:chany_bottom_in[15] 0.0001329739 +3 cby_2__1_:chany_top_in[2] cby_2__1_:chany_top_out[15] 0.0001329739 + +*RES +0 sb_2__1_:chany_bottom_out[2] cby_2__1_:chany_top_in[2] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[12] 0.001287871 //LENGTH 11.020 LUMPCC 0.0005225042 DR + +*CONN +*I sb_2__1_:chany_bottom_out[12] O *L 0 *C 861.580 527.750 +*I cby_2__1_:chany_top_in[12] I *L 0 *C 861.580 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[12] 0.0003826836 +1 cby_2__1_:chany_top_in[12] 0.0003826836 +2 sb_2__1_:chany_bottom_out[12] sb_2__1_:chany_bottom_in[2] 0.0001317449 +3 cby_2__1_:chany_top_in[12] cby_2__1_:chany_top_out[2] 0.0001317449 +4 sb_2__1_:chany_bottom_out[12] sb_2__1_:chany_bottom_in[12] 0.0001295071 +5 cby_2__1_:chany_top_in[12] cby_2__1_:chany_top_out[12] 0.0001295071 + +*RES +0 sb_2__1_:chany_bottom_out[12] cby_2__1_:chany_top_in[12] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[5] 0.001207291 //LENGTH 11.020 LUMPCC 0.0004524908 DR + +*CONN +*I sb_2__1_:chany_top_out[5] O *L 0 *C 864.800 658.170 +*I cby_2__2_:chany_bottom_in[5] I *L 0 *C 864.800 669.190 +*N sb_2__1__0_chany_top_out[5]:2 *C 864.800 667.520 +*N sb_2__1__0_chany_top_out[5]:3 *C 864.800 667.519 + +*CAP +0 sb_2__1_:chany_top_out[5] 0.0002580431 +1 cby_2__2_:chany_bottom_in[5] 0.0001193568 +2 sb_2__1__0_chany_top_out[5]:2 0.0001193568 +3 sb_2__1__0_chany_top_out[5]:3 0.0002580431 +4 sb_2__1_:chany_top_out[5] sb_2__1_:chany_top_in[2] 8.1924e-05 +5 cby_2__2_:chany_bottom_in[5] cby_2__2_:chany_bottom_out[2] 1.470669e-06 +6 sb_2__1__0_chany_top_out[5]:2 cby_1__1__3_chany_bottom_out[2]:3 1.470669e-06 +7 sb_2__1__0_chany_top_out[5]:3 cby_1__1__3_chany_bottom_out[2]:2 8.1924e-05 +8 sb_2__1_:chany_top_out[5] sb_2__1_:chany_top_in[18] 0.000135509 +9 cby_2__2_:chany_bottom_in[5] cby_2__2_:chany_bottom_out[18] 7.341718e-06 +10 sb_2__1__0_chany_top_out[5]:2 cby_1__1__3_chany_bottom_out[18]:3 7.341718e-06 +11 sb_2__1__0_chany_top_out[5]:3 cby_1__1__3_chany_bottom_out[18]:2 0.000135509 + +*RES +0 sb_2__1_:chany_top_out[5] sb_2__1__0_chany_top_out[5]:3 0.008347322 +1 sb_2__1__0_chany_top_out[5]:2 cby_2__2_:chany_bottom_in[5] 0.001491072 +2 sb_2__1__0_chany_top_out[5]:3 sb_2__1__0_chany_top_out[5]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[0] 0.001400612 //LENGTH 7.660 LUMPCC 0.0003496529 DR + +*CONN +*I sb_2__2_:chanx_left_out[0] O *L 0 *C 781.230 869.040 +*I cbx_2__2_:chanx_right_in[0] I *L 0 *C 773.570 869.040 + +*CAP +0 sb_2__2_:chanx_left_out[0] 0.0005254794 +1 cbx_2__2_:chanx_right_in[0] 0.0005254794 +2 sb_2__2_:chanx_left_out[0] sb_2__2_:chanx_left_in[19] 0.0001159588 +3 cbx_2__2_:chanx_right_in[0] cbx_2__2_:chanx_right_out[19] 0.0001159588 +4 sb_2__2_:chanx_left_out[0] sb_2__2_:ccff_tail[0] 5.886764e-05 +5 cbx_2__2_:chanx_right_in[0] cbx_2__2_:ccff_head[0] 5.886764e-05 + +*RES +0 sb_2__2_:chanx_left_out[0] cbx_2__2_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[14] 0.00136984 //LENGTH 7.660 LUMPCC 0.0004552805 DR + +*CONN +*I sb_2__2_:chanx_left_out[14] O *L 0 *C 781.230 858.160 +*I cbx_2__2_:chanx_right_in[14] I *L 0 *C 773.570 858.160 + +*CAP +0 sb_2__2_:chanx_left_out[14] 0.0004572798 +1 cbx_2__2_:chanx_right_in[14] 0.0004572798 +2 sb_2__2_:chanx_left_out[14] sb_2__2_:chanx_left_in[2] 5.135179e-05 +3 cbx_2__2_:chanx_right_in[14] cbx_1__2__1_chanx_right_out[2]:2 5.135179e-05 +4 sb_2__2_:chanx_left_out[14] sb_2__2_:chanx_left_out[5] 0.0001339431 +5 cbx_2__2_:chanx_right_in[14] cbx_2__2_:chanx_right_in[5] 0.0001339431 +6 sb_2__2_:chanx_left_out[14] sb_2__2_:chanx_left_out[18] 4.234528e-05 +7 cbx_2__2_:chanx_right_in[14] cbx_2__2_:chanx_right_in[18] 4.234528e-05 + +*RES +0 sb_2__2_:chanx_left_out[14] cbx_2__2_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[11] 0.001254699 //LENGTH 11.020 LUMPCC 0.0005709875 DR + +*CONN +*I sb_2__2_:chany_bottom_out[11] O *L 0 *C 855.140 788.870 +*I cby_2__2_:chany_top_in[11] I *L 0 *C 855.140 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[11] 0.0003418556 +1 cby_2__2_:chany_top_in[11] 0.0003418556 +2 sb_2__2_:chany_bottom_out[11] sb_2__2_:chany_bottom_out[6] 0.0001427469 +3 cby_2__2_:chany_top_in[11] cby_2__2_:chany_top_in[6] 0.0001427469 +4 sb_2__2_:chany_bottom_out[11] sb_2__2_:chany_bottom_out[18] 0.0001427469 +5 cby_2__2_:chany_top_in[11] cby_2__2_:chany_top_in[18] 0.0001427469 + +*RES +0 sb_2__2_:chany_bottom_out[11] cby_2__2_:chany_top_in[11] 0.009839286 + +*END + +*D_NET ctsbuf_net_312 0.04300877 //LENGTH 397.575 LUMPCC 0.002904223 DR + +*CONN +*I cts_inv_73527627:Y O *L 0 *C 564.880 898.960 +*I cbx_2__2_:prog_clk[0] I *L 0 *C 672.060 816.070 +*I sb_2__2_:prog_clk[0] I *L 0 *C 811.900 788.870 +*I cby_2__2_:prog_clk[0] I *L 0 *C 809.750 758.880 +*N ctsbuf_net_312:4 *C 805.008 758.880 +*N ctsbuf_net_312:5 *C 805.000 758.938 +*N ctsbuf_net_312:6 *C 811.900 787.498 +*N ctsbuf_net_312:7 *C 811.893 787.440 +*N ctsbuf_net_312:8 *C 805.008 787.440 +*N ctsbuf_net_312:9 *C 805.000 787.440 +*N ctsbuf_net_312:10 *C 805.000 814.583 +*N ctsbuf_net_312:11 *C 804.993 814.640 +*N ctsbuf_net_312:12 *C 771.910 814.640 +*N ctsbuf_net_312:13 *C 721.910 814.640 +*N ctsbuf_net_312:14 *C 672.060 814.640 +*N ctsbuf_net_312:15 *C 672.060 815.378 +*N ctsbuf_net_312:16 *C 672.060 815.312 +*N ctsbuf_net_312:17 *C 667.520 815.320 +*N ctsbuf_net_312:18 *C 667.519 815.320 +*N ctsbuf_net_312:19 *C 662.868 815.320 +*N ctsbuf_net_312:20 *C 662.860 815.378 +*N ctsbuf_net_312:21 *C 662.860 865.135 +*N ctsbuf_net_312:22 *C 662.860 891.519 +*N ctsbuf_net_312:23 *C 662.860 891.520 +*N ctsbuf_net_312:24 *C 662.860 894.143 +*N ctsbuf_net_312:25 *C 662.853 894.200 +*N ctsbuf_net_312:26 *C 623.915 894.200 +*N ctsbuf_net_312:27 *C 574.087 894.200 +*N ctsbuf_net_312:28 *C 574.080 894.258 +*N ctsbuf_net_312:29 *C 574.080 898.915 +*N ctsbuf_net_312:30 *C 574.035 898.960 +*N ctsbuf_net_312:31 *C 564.918 898.960 + +*CAP +0 cts_inv_73527627:Y 1e-06 +1 cbx_2__2_:prog_clk[0] 6.26361e-05 +2 sb_2__2_:prog_clk[0] 8.30678e-05 +3 cby_2__2_:prog_clk[0] 0.0003645899 +4 ctsbuf_net_312:4 0.0003645899 +5 ctsbuf_net_312:5 0.001316336 +6 ctsbuf_net_312:6 8.30678e-05 +7 ctsbuf_net_312:7 0.0003412708 +8 ctsbuf_net_312:8 0.0003412708 +9 ctsbuf_net_312:9 0.00256986 +10 ctsbuf_net_312:10 0.001226334 +11 ctsbuf_net_312:11 0.001434753 +12 ctsbuf_net_312:12 0.003699128 +13 ctsbuf_net_312:13 0.004476779 +14 ctsbuf_net_312:14 0.002253286 +15 ctsbuf_net_312:15 6.26361e-05 +16 ctsbuf_net_312:16 0.0003312722 +17 ctsbuf_net_312:17 0.0002903906 +18 ctsbuf_net_312:18 0.0001390388 +19 ctsbuf_net_312:19 0.0001390388 +20 ctsbuf_net_312:20 0.002819144 +21 ctsbuf_net_312:21 0.004318533 +22 ctsbuf_net_312:22 0.001499388 +23 ctsbuf_net_312:23 0.0001369207 +24 ctsbuf_net_312:24 0.0001369207 +25 ctsbuf_net_312:25 0.002176723 +26 ctsbuf_net_312:26 0.005089642 +27 ctsbuf_net_312:27 0.00291292 +28 ctsbuf_net_312:28 0.0002464827 +29 ctsbuf_net_312:29 0.0002464827 +30 ctsbuf_net_312:30 0.0004705222 +31 ctsbuf_net_312:31 0.0004705222 +32 ctsbuf_net_312:19 Test_en[0]:13 1.481498e-05 +33 ctsbuf_net_312:5 Test_en[0]:22 1.335429e-05 +34 ctsbuf_net_312:9 Test_en[0]:20 1.335429e-05 +35 ctsbuf_net_312:9 Test_en[0]:22 2.782057e-05 +36 ctsbuf_net_312:10 Test_en[0]:20 2.782057e-05 +37 ctsbuf_net_312:11 Test_en[0]:18 9.138983e-05 +38 ctsbuf_net_312:11 Test_en[0]:19 0.0001572697 +39 ctsbuf_net_312:14 Test_en[0]:15 8.094108e-05 +40 ctsbuf_net_312:14 Test_en[0]:16 0.0002975839 +41 ctsbuf_net_312:13 Test_en[0]:16 0.0001698855 +42 ctsbuf_net_312:13 Test_en[0]:17 0.0005959724 +43 ctsbuf_net_312:12 Test_en[0]:17 0.0001803342 +44 ctsbuf_net_312:12 Test_en[0]:18 0.0004556583 +45 ctsbuf_net_312:18 Test_en[0]:14 1.481498e-05 +46 ctsbuf_net_312:19 sb_1__2_:chanx_right_in[6] 3.084719e-05 +47 ctsbuf_net_312:18 cbx_1__2__1_chanx_left_out[6]:2 3.084719e-05 +48 cbx_2__2_:prog_clk[0] cbx_2__2_:chanx_left_out[14] 3.167166e-06 +49 ctsbuf_net_312:20 cbx_1__2__1_chanx_left_out[14]:4 6.826302e-06 +50 ctsbuf_net_312:19 cbx_1__2__1_chanx_left_out[14]:5 6.56738e-05 +51 ctsbuf_net_312:15 cbx_1__2__1_chanx_left_out[14]:9 3.167166e-06 +52 ctsbuf_net_312:16 cbx_2__2_:chanx_left_out[14] 6.1162e-06 +53 ctsbuf_net_312:16 cbx_1__2__1_chanx_left_out[14]:8 9.952665e-05 +54 ctsbuf_net_312:14 cbx_1__2__1_chanx_left_out[14]:7 9.835635e-05 +55 ctsbuf_net_312:14 cbx_1__2__1_chanx_left_out[14]:9 6.1162e-06 +56 ctsbuf_net_312:21 cbx_1__2__1_chanx_left_out[14]:3 6.826302e-06 +57 ctsbuf_net_312:13 cbx_1__2__1_chanx_left_out[14]:8 9.835635e-05 +58 ctsbuf_net_312:17 cbx_1__2__1_chanx_left_out[14]:7 9.952665e-05 +59 ctsbuf_net_312:18 cbx_1__2__1_chanx_left_out[14]:6 6.56738e-05 +60 ctsbuf_net_312:11 sb_2__2_:chanx_left_in[6] 2.863395e-05 +61 ctsbuf_net_312:12 cbx_2__2_:chanx_right_out[6] 2.863395e-05 +62 ctsbuf_net_312:9 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 3.274103e-05 +63 ctsbuf_net_312:8 grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] 9.71502e-06 +64 ctsbuf_net_312:7 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 9.71502e-06 +65 ctsbuf_net_312:10 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 3.274103e-05 + +*RES +0 cts_inv_73527627:Y ctsbuf_net_312:31 0.152 +1 ctsbuf_net_312:20 ctsbuf_net_312:19 0.00341 +2 ctsbuf_net_312:19 ctsbuf_net_312:18 0.000728735 +3 ctsbuf_net_312:24 ctsbuf_net_312:23 0.002341518 +4 ctsbuf_net_312:25 ctsbuf_net_312:24 0.00341 +5 ctsbuf_net_312:28 ctsbuf_net_312:27 0.00341 +6 ctsbuf_net_312:27 ctsbuf_net_312:26 0.007806308 +7 ctsbuf_net_312:30 ctsbuf_net_312:29 0.0045 +8 ctsbuf_net_312:29 ctsbuf_net_312:28 0.004158482 +9 ctsbuf_net_312:31 ctsbuf_net_312:30 0.008140625 +10 ctsbuf_net_312:5 ctsbuf_net_312:4 0.00341 +11 ctsbuf_net_312:4 cby_2__2_:prog_clk[0] 0.0007429916 +12 ctsbuf_net_312:15 cbx_2__2_:prog_clk[0] 0.0006183035 +13 ctsbuf_net_312:16 ctsbuf_net_312:15 0.00341 +14 ctsbuf_net_312:16 ctsbuf_net_312:14 0.0001053583 +15 ctsbuf_net_312:9 ctsbuf_net_312:8 0.00341 +16 ctsbuf_net_312:9 ctsbuf_net_312:5 0.02544866 +17 ctsbuf_net_312:8 ctsbuf_net_312:7 0.00107865 +18 ctsbuf_net_312:6 sb_2__2_:prog_clk[0] 0.001225446 +19 ctsbuf_net_312:7 ctsbuf_net_312:6 0.00341 +20 ctsbuf_net_312:10 ctsbuf_net_312:9 0.02423438 +21 ctsbuf_net_312:11 ctsbuf_net_312:10 0.00341 +22 ctsbuf_net_312:14 ctsbuf_net_312:13 0.007809833 +23 ctsbuf_net_312:21 ctsbuf_net_312:20 0.04442634 +24 ctsbuf_net_312:26 ctsbuf_net_312:25 0.006100208 +25 ctsbuf_net_312:13 ctsbuf_net_312:12 0.007833333 +26 ctsbuf_net_312:12 ctsbuf_net_312:11 0.005182925 +27 ctsbuf_net_312:23 ctsbuf_net_312:22 1e-05 +28 ctsbuf_net_312:22 ctsbuf_net_312:21 0.02355715 +29 ctsbuf_net_312:17 ctsbuf_net_312:16 0.0007112666 +30 ctsbuf_net_312:18 ctsbuf_net_312:17 1e-05 + +*END + +*D_NET prog_clk[0] 0.03133233 //LENGTH 308.590 LUMPCC 0 DR + +*CONN +*P prog_clk[0] I *L 0 *C 0.460 591.600 +*I cts_inv_73837658:A I *L 0.005046 *C 252.430 588.725 +*I cts_inv_73847659:A I *L 0.005046 *C 276.230 615.915 +*I cts_inv_73827657:A I *L 0.005046 *C 276.255 610.375 +*N prog_clk[0]:4 *C 276.255 610.375 +*N prog_clk[0]:5 *C 276.875 610.300 +*N prog_clk[0]:6 *C 276.920 610.290 +*N prog_clk[0]:7 *C 276.920 609.960 +*N prog_clk[0]:8 *C 276.913 609.960 +*N prog_clk[0]:9 *C 276.230 615.915 +*N prog_clk[0]:10 *C 276.000 615.825 +*N prog_clk[0]:11 *C 276.000 615.825 +*N prog_clk[0]:12 *C 276.000 610.720 +*N prog_clk[0]:13 *C 276.000 609.983 +*N prog_clk[0]:14 *C 276.007 609.960 +*N prog_clk[0]:15 *C 254.840 609.960 +*N prog_clk[0]:16 *C 254.840 609.938 +*N prog_clk[0]:17 *C 254.840 591.623 +*N prog_clk[0]:18 *C 254.840 591.600 +*N prog_clk[0]:19 *C 252.430 588.725 +*N prog_clk[0]:20 *C 252.540 588.815 +*N prog_clk[0]:21 *C 252.540 590.920 +*N prog_clk[0]:22 *C 253.000 590.920 +*N prog_clk[0]:23 *C 253.000 591.543 +*N prog_clk[0]:24 *C 253.000 591.600 +*N prog_clk[0]:25 *C 219.520 591.600 +*N prog_clk[0]:26 *C 219.519 591.600 +*N prog_clk[0]:27 *C 200.160 591.600 +*N prog_clk[0]:28 *C 150.160 591.600 +*N prog_clk[0]:29 *C 100.160 591.600 +*N prog_clk[0]:30 *C 50.160 591.600 +*N prog_clk[0]:31 *C 0.460 591.600 +*N prog_clk[0]:32 *C 0.460 591.600 + +*CAP +0 prog_clk[0] 1e-06 +1 cts_inv_73837658:A 1e-06 +2 cts_inv_73847659:A 1e-06 +3 cts_inv_73827657:A 1e-06 +4 prog_clk[0]:4 9.809228e-05 +5 prog_clk[0]:5 5.592311e-05 +6 prog_clk[0]:6 4.956091e-05 +7 prog_clk[0]:7 5.321323e-05 +8 prog_clk[0]:8 5.977775e-05 +9 prog_clk[0]:9 5.9676e-05 +10 prog_clk[0]:10 5.797985e-05 +11 prog_clk[0]:11 0.0003004673 +12 prog_clk[0]:12 0.0003189233 +13 prog_clk[0]:13 5.513567e-05 +14 prog_clk[0]:14 0.001140092 +15 prog_clk[0]:15 0.001080314 +16 prog_clk[0]:16 0.0009721846 +17 prog_clk[0]:17 0.0009721846 +18 prog_clk[0]:18 0.0001154831 +19 prog_clk[0]:19 3.258614e-05 +20 prog_clk[0]:20 0.0001511546 +21 prog_clk[0]:21 0.0001464655 +22 prog_clk[0]:22 7.542619e-05 +23 prog_clk[0]:23 4.662562e-05 +24 prog_clk[0]:24 0.001798786 +25 prog_clk[0]:25 0.001683303 +26 prog_clk[0]:26 0.000962134 +27 prog_clk[0]:27 0.003470664 +28 prog_clk[0]:28 0.005011245 +29 prog_clk[0]:29 0.005009893 +30 prog_clk[0]:30 0.005011656 +31 prog_clk[0]:31 0.002504478 +32 prog_clk[0]:32 3.489814e-05 + +*RES +0 prog_clk[0] prog_clk[0]:32 0.0045 +1 prog_clk[0]:17 prog_clk[0]:16 0.00817634 +2 prog_clk[0]:18 prog_clk[0]:17 0.00341 +3 prog_clk[0]:16 prog_clk[0]:15 0.00341 +4 prog_clk[0]:15 prog_clk[0]:14 0.001658121 +5 prog_clk[0]:13 prog_clk[0]:12 0.0003292411 +6 prog_clk[0]:14 prog_clk[0]:13 0.00341 +7 prog_clk[0]:14 prog_clk[0]:8 0.0001417833 +8 prog_clk[0]:10 prog_clk[0]:9 0.000125 +9 prog_clk[0]:11 prog_clk[0]:10 0.0045 +10 prog_clk[0]:9 cts_inv_73847659:A 0.152 +11 prog_clk[0]:23 prog_clk[0]:22 0.0005558036 +12 prog_clk[0]:24 prog_clk[0]:23 0.00341 +13 prog_clk[0]:24 prog_clk[0]:18 0.0001441333 +14 prog_clk[0]:19 cts_inv_73837658:A 0.152 +15 prog_clk[0]:20 prog_clk[0]:19 0.0045 +16 prog_clk[0]:7 prog_clk[0]:6 0.0001586538 +17 prog_clk[0]:8 prog_clk[0]:7 0.00341 +18 prog_clk[0]:5 prog_clk[0]:4 0.0005535715 +19 prog_clk[0]:6 prog_clk[0]:5 0.0045 +20 prog_clk[0]:4 cts_inv_73827657:A 0.152 +21 prog_clk[0]:32 prog_clk[0]:31 0.00341 +22 prog_clk[0]:31 prog_clk[0]:30 0.003893166 +23 prog_clk[0]:21 prog_clk[0]:20 0.001879464 +24 prog_clk[0]:22 prog_clk[0]:21 0.0004107143 +25 prog_clk[0]:12 prog_clk[0]:11 0.004558036 +26 prog_clk[0]:30 prog_clk[0]:29 0.003916666 +27 prog_clk[0]:29 prog_clk[0]:28 0.003916666 +28 prog_clk[0]:28 prog_clk[0]:27 0.003916666 +29 prog_clk[0]:27 prog_clk[0]:26 0.001516455 +30 prog_clk[0]:25 prog_clk[0]:24 0.0026226 +31 prog_clk[0]:26 prog_clk[0]:25 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_IE[3] 0.03029202 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__2_:gfpga_pad_GPIO_IE[0] O *L 0 *C 925.370 721.480 +*P gfpga_pad_GPIO_IE[3] O *L 0 *C 1199.155 721.480 +*N gfpga_pad_GPIO_IE[3]:2 *C 1179.960 721.480 +*N gfpga_pad_GPIO_IE[3]:3 *C 1129.960 721.480 +*N gfpga_pad_GPIO_IE[3]:4 *C 1115.520 721.480 +*N gfpga_pad_GPIO_IE[3]:5 *C 1115.519 721.480 +*N gfpga_pad_GPIO_IE[3]:6 *C 1079.960 721.480 +*N gfpga_pad_GPIO_IE[3]:7 *C 1029.960 721.480 +*N gfpga_pad_GPIO_IE[3]:8 *C 979.960 721.480 +*N gfpga_pad_GPIO_IE[3]:9 *C 930.165 721.480 +*N gfpga_pad_GPIO_IE[3]:10 *C 930.120 721.480 +*N gfpga_pad_GPIO_IE[3]:11 *C 930.113 721.480 + +*CAP +0 grid_io_right_3__2_:gfpga_pad_GPIO_IE[0] 0.0003843942 +1 gfpga_pad_GPIO_IE[3] 0.001060353 +2 gfpga_pad_GPIO_IE[3]:2 0.003794406 +3 gfpga_pad_GPIO_IE[3]:3 0.003518411 +4 gfpga_pad_GPIO_IE[3]:4 0.0007843579 +5 gfpga_pad_GPIO_IE[3]:5 0.001939904 +6 gfpga_pad_GPIO_IE[3]:6 0.004675442 +7 gfpga_pad_GPIO_IE[3]:7 0.005470953 +8 gfpga_pad_GPIO_IE[3]:8 0.005492757 +9 gfpga_pad_GPIO_IE[3]:9 0.002757343 +10 gfpga_pad_GPIO_IE[3]:10 2.930293e-05 +11 gfpga_pad_GPIO_IE[3]:11 0.0003843942 + +*RES +0 grid_io_right_3__2_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[3]:11 0.0007429916 +1 gfpga_pad_GPIO_IE[3]:10 gfpga_pad_GPIO_IE[3]:9 0.0045 +2 gfpga_pad_GPIO_IE[3]:11 gfpga_pad_GPIO_IE[3]:10 0.00341 +3 gfpga_pad_GPIO_IE[3]:9 gfpga_pad_GPIO_IE[3]:8 0.04445982 +4 gfpga_pad_GPIO_IE[3]:8 gfpga_pad_GPIO_IE[3]:7 0.04464286 +5 gfpga_pad_GPIO_IE[3]:7 gfpga_pad_GPIO_IE[3]:6 0.04464286 +6 gfpga_pad_GPIO_IE[3]:6 gfpga_pad_GPIO_IE[3]:5 0.03174911 +7 gfpga_pad_GPIO_IE[3]:3 gfpga_pad_GPIO_IE[3]:2 0.04464286 +8 gfpga_pad_GPIO_IE[3]:2 gfpga_pad_GPIO_IE[3] 0.01713839 +9 gfpga_pad_GPIO_IE[3]:4 gfpga_pad_GPIO_IE[3]:3 0.01289286 +10 gfpga_pad_GPIO_IE[3]:5 gfpga_pad_GPIO_IE[3]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_IE[4] 0.0223553 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_1__0_:gfpga_pad_GPIO_IE[0] O *L 0 *C 459.080 261.190 +*P gfpga_pad_GPIO_IE[4] O *L 0 *C 459.080 0.415 +*N gfpga_pad_GPIO_IE[4]:2 *C 459.080 50.415 +*N gfpga_pad_GPIO_IE[4]:3 *C 459.080 100.415 +*N gfpga_pad_GPIO_IE[4]:4 *C 459.080 150.415 +*N gfpga_pad_GPIO_IE[4]:5 *C 459.080 200.415 +*N gfpga_pad_GPIO_IE[4]:6 *C 459.080 219.519 +*N gfpga_pad_GPIO_IE[4]:7 *C 459.080 219.520 +*N gfpga_pad_GPIO_IE[4]:8 *C 459.080 250.415 + +*CAP +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_IE[0] 0.0004941316 +1 gfpga_pad_GPIO_IE[4] 0.002147436 +2 gfpga_pad_GPIO_IE[4]:2 0.004270541 +3 gfpga_pad_GPIO_IE[4]:3 0.004263517 +4 gfpga_pad_GPIO_IE[4]:4 0.004284487 +5 gfpga_pad_GPIO_IE[4]:5 0.002945671 +6 gfpga_pad_GPIO_IE[4]:6 0.0008015948 +7 gfpga_pad_GPIO_IE[4]:7 0.001326894 +8 gfpga_pad_GPIO_IE[4]:8 0.001821025 + +*RES +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[4]:8 0.009620536 +1 gfpga_pad_GPIO_IE[4]:2 gfpga_pad_GPIO_IE[4] 0.04464286 +2 gfpga_pad_GPIO_IE[4]:3 gfpga_pad_GPIO_IE[4]:2 0.04464286 +3 gfpga_pad_GPIO_IE[4]:4 gfpga_pad_GPIO_IE[4]:3 0.04464286 +4 gfpga_pad_GPIO_IE[4]:5 gfpga_pad_GPIO_IE[4]:4 0.04464286 +5 gfpga_pad_GPIO_IE[4]:8 gfpga_pad_GPIO_IE[4]:7 0.02758482 +6 gfpga_pad_GPIO_IE[4]:7 gfpga_pad_GPIO_IE[4]:6 1e-05 +7 gfpga_pad_GPIO_IE[4]:6 gfpga_pad_GPIO_IE[4]:5 0.01705714 + +*END + +*D_NET gfpga_pad_GPIO_IE[5] 0.02144674 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_2__0_:gfpga_pad_GPIO_IE[0] O *L 0 *C 720.360 261.190 +*P gfpga_pad_GPIO_IE[5] O *L 0 *C 720.360 0.415 +*N gfpga_pad_GPIO_IE[5]:2 *C 720.360 50.415 +*N gfpga_pad_GPIO_IE[5]:3 *C 720.360 100.415 +*N gfpga_pad_GPIO_IE[5]:4 *C 720.360 150.415 +*N gfpga_pad_GPIO_IE[5]:5 *C 720.360 200.415 +*N gfpga_pad_GPIO_IE[5]:6 *C 720.360 219.519 +*N gfpga_pad_GPIO_IE[5]:7 *C 720.360 219.520 +*N gfpga_pad_GPIO_IE[5]:8 *C 720.360 250.415 + +*CAP +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_IE[0] 0.0004776808 +1 gfpga_pad_GPIO_IE[5] 0.002058909 +2 gfpga_pad_GPIO_IE[5]:2 0.004095871 +3 gfpga_pad_GPIO_IE[5]:3 0.004098087 +4 gfpga_pad_GPIO_IE[5]:4 0.004115978 +5 gfpga_pad_GPIO_IE[5]:5 0.002821998 +6 gfpga_pad_GPIO_IE[5]:6 0.0007671448 +7 gfpga_pad_GPIO_IE[5]:7 0.001266696 +8 gfpga_pad_GPIO_IE[5]:8 0.001744377 + +*RES +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[5]:8 0.009620536 +1 gfpga_pad_GPIO_IE[5]:2 gfpga_pad_GPIO_IE[5] 0.04464286 +2 gfpga_pad_GPIO_IE[5]:3 gfpga_pad_GPIO_IE[5]:2 0.04464286 +3 gfpga_pad_GPIO_IE[5]:4 gfpga_pad_GPIO_IE[5]:3 0.04464286 +4 gfpga_pad_GPIO_IE[5]:5 gfpga_pad_GPIO_IE[5]:4 0.04464286 +5 gfpga_pad_GPIO_IE[5]:8 gfpga_pad_GPIO_IE[5]:7 0.02758482 +6 gfpga_pad_GPIO_IE[5]:7 gfpga_pad_GPIO_IE[5]:6 1e-05 +7 gfpga_pad_GPIO_IE[5]:6 gfpga_pad_GPIO_IE[5]:5 0.01705714 + +*END + +*D_NET gfpga_pad_GPIO_IE[6] 0.02589008 //LENGTH 274.035 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__1_:gfpga_pad_GPIO_IE[0] O *L 0 *C 255.910 476.000 +*P gfpga_pad_GPIO_IE[6] O *L 0 *C 0.525 458.660 +*N gfpga_pad_GPIO_IE[6]:2 *C 3.635 458.660 +*N gfpga_pad_GPIO_IE[6]:3 *C 3.680 458.705 +*N gfpga_pad_GPIO_IE[6]:4 *C 3.680 466.095 +*N gfpga_pad_GPIO_IE[6]:5 *C 3.725 466.140 +*N gfpga_pad_GPIO_IE[6]:6 *C 53.520 466.140 +*N gfpga_pad_GPIO_IE[6]:7 *C 103.520 466.140 +*N gfpga_pad_GPIO_IE[6]:8 *C 153.520 466.140 +*N gfpga_pad_GPIO_IE[6]:9 *C 203.520 466.140 +*N gfpga_pad_GPIO_IE[6]:10 *C 219.519 466.140 +*N gfpga_pad_GPIO_IE[6]:11 *C 219.520 466.140 +*N gfpga_pad_GPIO_IE[6]:12 *C 225.815 466.140 +*N gfpga_pad_GPIO_IE[6]:13 *C 225.860 466.185 +*N gfpga_pad_GPIO_IE[6]:14 *C 225.860 475.942 +*N gfpga_pad_GPIO_IE[6]:15 *C 225.868 476.000 + +*CAP +0 grid_io_left_0__1_:gfpga_pad_GPIO_IE[0] 0.001357412 +1 gfpga_pad_GPIO_IE[6] 0.0001762403 +2 gfpga_pad_GPIO_IE[6]:2 0.0001762403 +3 gfpga_pad_GPIO_IE[6]:3 0.0003391386 +4 gfpga_pad_GPIO_IE[6]:4 0.0003391386 +5 gfpga_pad_GPIO_IE[6]:5 0.002396438 +6 gfpga_pad_GPIO_IE[6]:6 0.004790726 +7 gfpga_pad_GPIO_IE[6]:7 0.004788652 +8 gfpga_pad_GPIO_IE[6]:8 0.004788244 +9 gfpga_pad_GPIO_IE[6]:9 0.003155221 +10 gfpga_pad_GPIO_IE[6]:10 0.0007613411 +11 gfpga_pad_GPIO_IE[6]:11 0.0003121947 +12 gfpga_pad_GPIO_IE[6]:12 0.0003121947 +13 gfpga_pad_GPIO_IE[6]:13 0.0004197442 +14 gfpga_pad_GPIO_IE[6]:14 0.0004197442 +15 gfpga_pad_GPIO_IE[6]:15 0.001357412 + +*RES +0 grid_io_left_0__1_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[6]:15 0.004706658 +1 gfpga_pad_GPIO_IE[6]:14 gfpga_pad_GPIO_IE[6]:13 0.008712054 +2 gfpga_pad_GPIO_IE[6]:15 gfpga_pad_GPIO_IE[6]:14 0.00341 +3 gfpga_pad_GPIO_IE[6]:12 gfpga_pad_GPIO_IE[6]:11 0.005620536 +4 gfpga_pad_GPIO_IE[6]:13 gfpga_pad_GPIO_IE[6]:12 0.0045 +5 gfpga_pad_GPIO_IE[6]:5 gfpga_pad_GPIO_IE[6]:4 0.0045 +6 gfpga_pad_GPIO_IE[6]:4 gfpga_pad_GPIO_IE[6]:3 0.006598215 +7 gfpga_pad_GPIO_IE[6]:2 gfpga_pad_GPIO_IE[6] 0.002776786 +8 gfpga_pad_GPIO_IE[6]:3 gfpga_pad_GPIO_IE[6]:2 0.0045 +9 gfpga_pad_GPIO_IE[6]:6 gfpga_pad_GPIO_IE[6]:5 0.04445983 +10 gfpga_pad_GPIO_IE[6]:7 gfpga_pad_GPIO_IE[6]:6 0.04464286 +11 gfpga_pad_GPIO_IE[6]:8 gfpga_pad_GPIO_IE[6]:7 0.04464286 +12 gfpga_pad_GPIO_IE[6]:9 gfpga_pad_GPIO_IE[6]:8 0.04464286 +13 gfpga_pad_GPIO_IE[6]:11 gfpga_pad_GPIO_IE[6]:10 1e-05 +14 gfpga_pad_GPIO_IE[6]:10 gfpga_pad_GPIO_IE[6]:9 0.01428482 + +*END + +*D_NET gfpga_pad_GPIO_IE[7] 0.02235265 //LENGTH 273.395 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__2_:gfpga_pad_GPIO_IE[0] O *L 0 *C 255.910 737.120 +*P gfpga_pad_GPIO_IE[7] O *L 0 *C 0.525 719.780 +*N gfpga_pad_GPIO_IE[7]:2 *C 10.995 719.780 +*N gfpga_pad_GPIO_IE[7]:3 *C 11.040 719.825 +*N gfpga_pad_GPIO_IE[7]:4 *C 11.040 737.062 +*N gfpga_pad_GPIO_IE[7]:5 *C 11.048 737.120 +*N gfpga_pad_GPIO_IE[7]:6 *C 60.875 737.120 +*N gfpga_pad_GPIO_IE[7]:7 *C 110.875 737.120 +*N gfpga_pad_GPIO_IE[7]:8 *C 160.875 737.120 +*N gfpga_pad_GPIO_IE[7]:9 *C 210.875 737.120 +*N gfpga_pad_GPIO_IE[7]:10 *C 219.519 737.120 +*N gfpga_pad_GPIO_IE[7]:11 *C 219.520 737.120 + +*CAP +0 grid_io_left_0__2_:gfpga_pad_GPIO_IE[0] 0.001537286 +1 gfpga_pad_GPIO_IE[7] 0.0005353144 +2 gfpga_pad_GPIO_IE[7]:2 0.0005353144 +3 gfpga_pad_GPIO_IE[7]:3 0.0007631159 +4 gfpga_pad_GPIO_IE[7]:4 0.0007631159 +5 gfpga_pad_GPIO_IE[7]:5 0.002003172 +6 gfpga_pad_GPIO_IE[7]:6 0.004000757 +7 gfpga_pad_GPIO_IE[7]:7 0.003997726 +8 gfpga_pad_GPIO_IE[7]:8 0.003995645 +9 gfpga_pad_GPIO_IE[7]:9 0.002339709 +10 gfpga_pad_GPIO_IE[7]:10 0.0003442057 +11 gfpga_pad_GPIO_IE[7]:11 0.001537286 + +*RES +0 grid_io_left_0__2_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[7]:11 0.0057011 +1 gfpga_pad_GPIO_IE[7]:4 gfpga_pad_GPIO_IE[7]:3 0.01539063 +2 gfpga_pad_GPIO_IE[7]:5 gfpga_pad_GPIO_IE[7]:4 0.00341 +3 gfpga_pad_GPIO_IE[7]:2 gfpga_pad_GPIO_IE[7] 0.009348215 +4 gfpga_pad_GPIO_IE[7]:3 gfpga_pad_GPIO_IE[7]:2 0.0045 +5 gfpga_pad_GPIO_IE[7]:6 gfpga_pad_GPIO_IE[7]:5 0.007806308 +6 gfpga_pad_GPIO_IE[7]:7 gfpga_pad_GPIO_IE[7]:6 0.007833333 +7 gfpga_pad_GPIO_IE[7]:8 gfpga_pad_GPIO_IE[7]:7 0.007833333 +8 gfpga_pad_GPIO_IE[7]:9 gfpga_pad_GPIO_IE[7]:8 0.007833333 +9 gfpga_pad_GPIO_IE[7]:11 gfpga_pad_GPIO_IE[7]:10 1e-05 +10 gfpga_pad_GPIO_IE[7]:10 gfpga_pad_GPIO_IE[7]:9 0.001354227 + +*END + +*D_NET gfpga_pad_GPIO_OE[0] 0.02385205 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*I grid_io_top_1__3_:gfpga_pad_GPIO_OE[0] O *L 0 *C 450.340 924.730 +*P gfpga_pad_GPIO_OE[0] O *L 0 *C 450.340 1196.385 +*N gfpga_pad_GPIO_OE[0]:2 *C 450.340 1174.730 +*N gfpga_pad_GPIO_OE[0]:3 *C 450.340 1124.730 +*N gfpga_pad_GPIO_OE[0]:4 *C 450.340 1115.520 +*N gfpga_pad_GPIO_OE[0]:5 *C 450.340 1115.519 +*N gfpga_pad_GPIO_OE[0]:6 *C 450.340 1074.730 +*N gfpga_pad_GPIO_OE[0]:7 *C 450.340 1024.730 +*N gfpga_pad_GPIO_OE[0]:8 *C 450.340 974.730 + +*CAP +0 grid_io_top_1__3_:gfpga_pad_GPIO_OE[0] 0.002250391 +1 gfpga_pad_GPIO_OE[0] 0.0009395955 +2 gfpga_pad_GPIO_OE[0]:2 0.003124422 +3 gfpga_pad_GPIO_OE[0]:3 0.00257798 +4 gfpga_pad_GPIO_OE[0]:4 0.0003931536 +5 gfpga_pad_GPIO_OE[0]:5 0.001792509 +6 gfpga_pad_GPIO_OE[0]:6 0.00397203 +7 gfpga_pad_GPIO_OE[0]:7 0.004365548 +8 gfpga_pad_GPIO_OE[0]:8 0.004436418 + +*RES +0 grid_io_top_1__3_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[0]:8 0.04464286 +1 gfpga_pad_GPIO_OE[0]:8 gfpga_pad_GPIO_OE[0]:7 0.04464286 +2 gfpga_pad_GPIO_OE[0]:7 gfpga_pad_GPIO_OE[0]:6 0.04464286 +3 gfpga_pad_GPIO_OE[0]:6 gfpga_pad_GPIO_OE[0]:5 0.03641875 +4 gfpga_pad_GPIO_OE[0]:3 gfpga_pad_GPIO_OE[0]:2 0.04464286 +5 gfpga_pad_GPIO_OE[0]:2 gfpga_pad_GPIO_OE[0] 0.01933482 +6 gfpga_pad_GPIO_OE[0]:4 gfpga_pad_GPIO_OE[0]:3 0.008223215 +7 gfpga_pad_GPIO_OE[0]:5 gfpga_pad_GPIO_OE[0]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_OE[1] 0.02326166 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*I grid_io_top_2__3_:gfpga_pad_GPIO_OE[0] O *L 0 *C 711.620 924.730 +*P gfpga_pad_GPIO_OE[1] O *L 0 *C 711.620 1196.385 +*N gfpga_pad_GPIO_OE[1]:2 *C 711.620 1174.730 +*N gfpga_pad_GPIO_OE[1]:3 *C 711.620 1124.730 +*N gfpga_pad_GPIO_OE[1]:4 *C 711.620 1115.520 +*N gfpga_pad_GPIO_OE[1]:5 *C 711.620 1115.519 +*N gfpga_pad_GPIO_OE[1]:6 *C 711.620 1074.730 +*N gfpga_pad_GPIO_OE[1]:7 *C 711.620 1024.730 +*N gfpga_pad_GPIO_OE[1]:8 *C 711.620 974.730 + +*CAP +0 grid_io_top_2__3_:gfpga_pad_GPIO_OE[0] 0.002195536 +1 gfpga_pad_GPIO_OE[1] 0.0009126809 +2 gfpga_pad_GPIO_OE[1]:2 0.003044432 +3 gfpga_pad_GPIO_OE[1]:3 0.002523786 +4 gfpga_pad_GPIO_OE[1]:4 0.000392035 +5 gfpga_pad_GPIO_OE[1]:5 0.001745778 +6 gfpga_pad_GPIO_OE[1]:6 0.003867887 +7 gfpga_pad_GPIO_OE[1]:7 0.004253048 +8 gfpga_pad_GPIO_OE[1]:8 0.004326475 + +*RES +0 grid_io_top_2__3_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[1]:8 0.04464286 +1 gfpga_pad_GPIO_OE[1]:8 gfpga_pad_GPIO_OE[1]:7 0.04464286 +2 gfpga_pad_GPIO_OE[1]:7 gfpga_pad_GPIO_OE[1]:6 0.04464286 +3 gfpga_pad_GPIO_OE[1]:6 gfpga_pad_GPIO_OE[1]:5 0.03641875 +4 gfpga_pad_GPIO_OE[1]:3 gfpga_pad_GPIO_OE[1]:2 0.04464286 +5 gfpga_pad_GPIO_OE[1]:2 gfpga_pad_GPIO_OE[1] 0.01933482 +6 gfpga_pad_GPIO_OE[1]:4 gfpga_pad_GPIO_OE[1]:3 0.008223215 +7 gfpga_pad_GPIO_OE[1]:5 gfpga_pad_GPIO_OE[1]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_OE[2] 0.02597139 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__1_:gfpga_pad_GPIO_OE[0] O *L 0 *C 925.370 450.160 +*P gfpga_pad_GPIO_OE[2] O *L 0 *C 1199.155 450.160 +*N gfpga_pad_GPIO_OE[2]:2 *C 1179.960 450.160 +*N gfpga_pad_GPIO_OE[2]:3 *C 1129.960 450.160 +*N gfpga_pad_GPIO_OE[2]:4 *C 1115.520 450.160 +*N gfpga_pad_GPIO_OE[2]:5 *C 1115.519 450.160 +*N gfpga_pad_GPIO_OE[2]:6 *C 1079.960 450.160 +*N gfpga_pad_GPIO_OE[2]:7 *C 1029.960 450.160 +*N gfpga_pad_GPIO_OE[2]:8 *C 979.960 450.160 +*N gfpga_pad_GPIO_OE[2]:9 *C 930.165 450.160 +*N gfpga_pad_GPIO_OE[2]:10 *C 930.120 450.160 +*N gfpga_pad_GPIO_OE[2]:11 *C 930.113 450.160 + +*CAP +0 grid_io_right_3__1_:gfpga_pad_GPIO_OE[0] 0.0003717891 +1 gfpga_pad_GPIO_OE[2] 0.0009018279 +2 gfpga_pad_GPIO_OE[2]:2 0.003241068 +3 gfpga_pad_GPIO_OE[2]:3 0.003014068 +4 gfpga_pad_GPIO_OE[2]:4 0.0006748272 +5 gfpga_pad_GPIO_OE[2]:5 0.001664186 +6 gfpga_pad_GPIO_OE[2]:6 0.004002919 +7 gfpga_pad_GPIO_OE[2]:7 0.004678518 +8 gfpga_pad_GPIO_OE[2]:8 0.004679314 +9 gfpga_pad_GPIO_OE[2]:9 0.002339529 +10 gfpga_pad_GPIO_OE[2]:10 3.155341e-05 +11 gfpga_pad_GPIO_OE[2]:11 0.0003717891 + +*RES +0 grid_io_right_3__1_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[2]:11 0.0007429916 +1 gfpga_pad_GPIO_OE[2]:10 gfpga_pad_GPIO_OE[2]:9 0.0045 +2 gfpga_pad_GPIO_OE[2]:11 gfpga_pad_GPIO_OE[2]:10 0.00341 +3 gfpga_pad_GPIO_OE[2]:9 gfpga_pad_GPIO_OE[2]:8 0.04445982 +4 gfpga_pad_GPIO_OE[2]:8 gfpga_pad_GPIO_OE[2]:7 0.04464286 +5 gfpga_pad_GPIO_OE[2]:7 gfpga_pad_GPIO_OE[2]:6 0.04464286 +6 gfpga_pad_GPIO_OE[2]:6 gfpga_pad_GPIO_OE[2]:5 0.03174911 +7 gfpga_pad_GPIO_OE[2]:3 gfpga_pad_GPIO_OE[2]:2 0.04464286 +8 gfpga_pad_GPIO_OE[2]:2 gfpga_pad_GPIO_OE[2] 0.01713839 +9 gfpga_pad_GPIO_OE[2]:4 gfpga_pad_GPIO_OE[2]:3 0.01289286 +10 gfpga_pad_GPIO_OE[2]:5 gfpga_pad_GPIO_OE[2]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_OE[3] 0.02574531 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__2_:gfpga_pad_GPIO_OE[0] O *L 0 *C 925.370 711.280 +*P gfpga_pad_GPIO_OE[3] O *L 0 *C 1199.155 711.280 +*N gfpga_pad_GPIO_OE[3]:2 *C 1179.960 711.280 +*N gfpga_pad_GPIO_OE[3]:3 *C 1129.960 711.280 +*N gfpga_pad_GPIO_OE[3]:4 *C 1115.520 711.280 +*N gfpga_pad_GPIO_OE[3]:5 *C 1115.519 711.280 +*N gfpga_pad_GPIO_OE[3]:6 *C 1079.960 711.280 +*N gfpga_pad_GPIO_OE[3]:7 *C 1029.960 711.280 +*N gfpga_pad_GPIO_OE[3]:8 *C 979.960 711.280 +*N gfpga_pad_GPIO_OE[3]:9 *C 930.165 711.280 +*N gfpga_pad_GPIO_OE[3]:10 *C 930.120 711.280 +*N gfpga_pad_GPIO_OE[3]:11 *C 930.113 711.280 + +*CAP +0 grid_io_right_3__2_:gfpga_pad_GPIO_OE[0] 0.0003743292 +1 gfpga_pad_GPIO_OE[3] 0.0008998496 +2 gfpga_pad_GPIO_OE[3]:2 0.003216431 +3 gfpga_pad_GPIO_OE[3]:3 0.002980675 +4 gfpga_pad_GPIO_OE[3]:4 0.0006640945 +5 gfpga_pad_GPIO_OE[3]:5 0.0016428 +6 gfpga_pad_GPIO_OE[3]:6 0.003960421 +7 gfpga_pad_GPIO_OE[3]:7 0.004635096 +8 gfpga_pad_GPIO_OE[3]:8 0.004643835 +9 gfpga_pad_GPIO_OE[3]:9 0.00232636 +10 gfpga_pad_GPIO_OE[3]:10 2.709101e-05 +11 gfpga_pad_GPIO_OE[3]:11 0.0003743292 + +*RES +0 grid_io_right_3__2_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[3]:11 0.0007429916 +1 gfpga_pad_GPIO_OE[3]:10 gfpga_pad_GPIO_OE[3]:9 0.0045 +2 gfpga_pad_GPIO_OE[3]:11 gfpga_pad_GPIO_OE[3]:10 0.00341 +3 gfpga_pad_GPIO_OE[3]:9 gfpga_pad_GPIO_OE[3]:8 0.04445982 +4 gfpga_pad_GPIO_OE[3]:8 gfpga_pad_GPIO_OE[3]:7 0.04464286 +5 gfpga_pad_GPIO_OE[3]:7 gfpga_pad_GPIO_OE[3]:6 0.04464286 +6 gfpga_pad_GPIO_OE[3]:6 gfpga_pad_GPIO_OE[3]:5 0.03174911 +7 gfpga_pad_GPIO_OE[3]:3 gfpga_pad_GPIO_OE[3]:2 0.04464286 +8 gfpga_pad_GPIO_OE[3]:2 gfpga_pad_GPIO_OE[3] 0.01713839 +9 gfpga_pad_GPIO_OE[3]:4 gfpga_pad_GPIO_OE[3]:3 0.01289286 +10 gfpga_pad_GPIO_OE[3]:5 gfpga_pad_GPIO_OE[3]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_OE[4] 0.02223261 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_1__0_:gfpga_pad_GPIO_OE[0] O *L 0 *C 445.740 261.190 +*P gfpga_pad_GPIO_OE[4] O *L 0 *C 445.740 0.415 +*N gfpga_pad_GPIO_OE[4]:2 *C 445.740 50.415 +*N gfpga_pad_GPIO_OE[4]:3 *C 445.740 100.415 +*N gfpga_pad_GPIO_OE[4]:4 *C 445.740 150.415 +*N gfpga_pad_GPIO_OE[4]:5 *C 445.740 200.415 +*N gfpga_pad_GPIO_OE[4]:6 *C 445.740 219.519 +*N gfpga_pad_GPIO_OE[4]:7 *C 445.740 219.520 +*N gfpga_pad_GPIO_OE[4]:8 *C 445.740 250.415 + +*CAP +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_OE[0] 0.0004911486 +1 gfpga_pad_GPIO_OE[4] 0.002134561 +2 gfpga_pad_GPIO_OE[4]:2 0.004246138 +3 gfpga_pad_GPIO_OE[4]:3 0.004240511 +4 gfpga_pad_GPIO_OE[4]:4 0.004260564 +5 gfpga_pad_GPIO_OE[4]:5 0.002929549 +6 gfpga_pad_GPIO_OE[4]:6 0.0007979195 +7 gfpga_pad_GPIO_OE[4]:7 0.001320534 +8 gfpga_pad_GPIO_OE[4]:8 0.001811682 + +*RES +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[4]:8 0.009620536 +1 gfpga_pad_GPIO_OE[4]:2 gfpga_pad_GPIO_OE[4] 0.04464286 +2 gfpga_pad_GPIO_OE[4]:3 gfpga_pad_GPIO_OE[4]:2 0.04464286 +3 gfpga_pad_GPIO_OE[4]:4 gfpga_pad_GPIO_OE[4]:3 0.04464286 +4 gfpga_pad_GPIO_OE[4]:5 gfpga_pad_GPIO_OE[4]:4 0.04464286 +5 gfpga_pad_GPIO_OE[4]:8 gfpga_pad_GPIO_OE[4]:7 0.02758482 +6 gfpga_pad_GPIO_OE[4]:7 gfpga_pad_GPIO_OE[4]:6 1e-05 +7 gfpga_pad_GPIO_OE[4]:6 gfpga_pad_GPIO_OE[4]:5 0.01705714 + +*END + +*D_NET gfpga_pad_GPIO_OE[5] 0.02242615 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_2__0_:gfpga_pad_GPIO_OE[0] O *L 0 *C 707.020 261.190 +*P gfpga_pad_GPIO_OE[5] O *L 0 *C 707.020 0.415 +*N gfpga_pad_GPIO_OE[5]:2 *C 707.020 50.415 +*N gfpga_pad_GPIO_OE[5]:3 *C 707.020 100.415 +*N gfpga_pad_GPIO_OE[5]:4 *C 707.020 150.415 +*N gfpga_pad_GPIO_OE[5]:5 *C 707.020 200.415 +*N gfpga_pad_GPIO_OE[5]:6 *C 707.020 219.519 +*N gfpga_pad_GPIO_OE[5]:7 *C 707.020 219.520 +*N gfpga_pad_GPIO_OE[5]:8 *C 707.020 250.415 + +*CAP +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_OE[0] 0.0004951781 +1 gfpga_pad_GPIO_OE[5] 0.002153759 +2 gfpga_pad_GPIO_OE[5]:2 0.00428388 +3 gfpga_pad_GPIO_OE[5]:3 0.004282322 +4 gfpga_pad_GPIO_OE[5]:4 0.004302882 +5 gfpga_pad_GPIO_OE[5]:5 0.002952707 +6 gfpga_pad_GPIO_OE[5]:6 0.0008020251 +7 gfpga_pad_GPIO_OE[5]:7 0.001329109 +8 gfpga_pad_GPIO_OE[5]:8 0.001824287 + +*RES +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[5]:8 0.009620536 +1 gfpga_pad_GPIO_OE[5]:2 gfpga_pad_GPIO_OE[5] 0.04464286 +2 gfpga_pad_GPIO_OE[5]:3 gfpga_pad_GPIO_OE[5]:2 0.04464286 +3 gfpga_pad_GPIO_OE[5]:4 gfpga_pad_GPIO_OE[5]:3 0.04464286 +4 gfpga_pad_GPIO_OE[5]:5 gfpga_pad_GPIO_OE[5]:4 0.04464286 +5 gfpga_pad_GPIO_OE[5]:8 gfpga_pad_GPIO_OE[5]:7 0.02758482 +6 gfpga_pad_GPIO_OE[5]:7 gfpga_pad_GPIO_OE[5]:6 1e-05 +7 gfpga_pad_GPIO_OE[5]:6 gfpga_pad_GPIO_OE[5]:5 0.01705714 + +*END + +*D_NET gfpga_pad_GPIO_OE[6] 0.02372169 //LENGTH 255.710 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__1_:gfpga_pad_GPIO_OE[0] O *L 0 *C 255.910 433.840 +*P gfpga_pad_GPIO_OE[6] O *L 0 *C 0.525 433.840 +*N gfpga_pad_GPIO_OE[6]:2 *C 50.525 433.840 +*N gfpga_pad_GPIO_OE[6]:3 *C 100.525 433.840 +*N gfpga_pad_GPIO_OE[6]:4 *C 150.525 433.840 +*N gfpga_pad_GPIO_OE[6]:5 *C 200.525 433.840 +*N gfpga_pad_GPIO_OE[6]:6 *C 219.519 433.840 +*N gfpga_pad_GPIO_OE[6]:7 *C 219.520 433.840 +*N gfpga_pad_GPIO_OE[6]:8 *C 250.195 433.840 +*N gfpga_pad_GPIO_OE[6]:9 *C 250.240 433.840 +*N gfpga_pad_GPIO_OE[6]:10 *C 250.248 433.840 + +*CAP +0 grid_io_left_0__1_:gfpga_pad_GPIO_OE[0] 0.0003210462 +1 gfpga_pad_GPIO_OE[6] 0.002310679 +2 gfpga_pad_GPIO_OE[6]:2 0.004615626 +3 gfpga_pad_GPIO_OE[6]:3 0.004610067 +4 gfpga_pad_GPIO_OE[6]:4 0.004610487 +5 gfpga_pad_GPIO_OE[6]:5 0.003180901 +6 gfpga_pad_GPIO_OE[6]:6 0.0008755345 +7 gfpga_pad_GPIO_OE[6]:7 0.001424967 +8 gfpga_pad_GPIO_OE[6]:8 0.001424967 +9 gfpga_pad_GPIO_OE[6]:9 2.636775e-05 +10 gfpga_pad_GPIO_OE[6]:10 0.0003210462 + +*RES +0 grid_io_left_0__1_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[6]:10 0.000887125 +1 gfpga_pad_GPIO_OE[6]:9 gfpga_pad_GPIO_OE[6]:8 0.0045 +2 gfpga_pad_GPIO_OE[6]:10 gfpga_pad_GPIO_OE[6]:9 0.00341 +3 gfpga_pad_GPIO_OE[6]:8 gfpga_pad_GPIO_OE[6]:7 0.0273884 +4 gfpga_pad_GPIO_OE[6]:2 gfpga_pad_GPIO_OE[6] 0.04464286 +5 gfpga_pad_GPIO_OE[6]:3 gfpga_pad_GPIO_OE[6]:2 0.04464286 +6 gfpga_pad_GPIO_OE[6]:4 gfpga_pad_GPIO_OE[6]:3 0.04464286 +7 gfpga_pad_GPIO_OE[6]:5 gfpga_pad_GPIO_OE[6]:4 0.04464286 +8 gfpga_pad_GPIO_OE[6]:7 gfpga_pad_GPIO_OE[6]:6 1e-05 +9 gfpga_pad_GPIO_OE[6]:6 gfpga_pad_GPIO_OE[6]:5 0.01695893 + +*END + +*D_NET gfpga_pad_GPIO_OE[7] 0.02385717 //LENGTH 255.710 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__2_:gfpga_pad_GPIO_OE[0] O *L 0 *C 255.910 694.960 +*P gfpga_pad_GPIO_OE[7] O *L 0 *C 0.525 694.960 +*N gfpga_pad_GPIO_OE[7]:2 *C 50.525 694.960 +*N gfpga_pad_GPIO_OE[7]:3 *C 100.525 694.960 +*N gfpga_pad_GPIO_OE[7]:4 *C 150.525 694.960 +*N gfpga_pad_GPIO_OE[7]:5 *C 200.525 694.960 +*N gfpga_pad_GPIO_OE[7]:6 *C 219.519 694.960 +*N gfpga_pad_GPIO_OE[7]:7 *C 219.520 694.960 +*N gfpga_pad_GPIO_OE[7]:8 *C 250.195 694.960 +*N gfpga_pad_GPIO_OE[7]:9 *C 250.240 694.960 +*N gfpga_pad_GPIO_OE[7]:10 *C 250.248 694.960 + +*CAP +0 grid_io_left_0__2_:gfpga_pad_GPIO_OE[0] 0.00031421 +1 gfpga_pad_GPIO_OE[7] 0.00233333 +2 gfpga_pad_GPIO_OE[7]:2 0.004654331 +3 gfpga_pad_GPIO_OE[7]:3 0.004641529 +4 gfpga_pad_GPIO_OE[7]:4 0.004641565 +5 gfpga_pad_GPIO_OE[7]:5 0.00319716 +6 gfpga_pad_GPIO_OE[7]:6 0.0008761245 +7 gfpga_pad_GPIO_OE[7]:7 0.001428367 +8 gfpga_pad_GPIO_OE[7]:8 0.001428367 +9 gfpga_pad_GPIO_OE[7]:9 2.797697e-05 +10 gfpga_pad_GPIO_OE[7]:10 0.00031421 + +*RES +0 grid_io_left_0__2_:gfpga_pad_GPIO_OE[0] gfpga_pad_GPIO_OE[7]:10 0.000887125 +1 gfpga_pad_GPIO_OE[7]:9 gfpga_pad_GPIO_OE[7]:8 0.0045 +2 gfpga_pad_GPIO_OE[7]:10 gfpga_pad_GPIO_OE[7]:9 0.00341 +3 gfpga_pad_GPIO_OE[7]:8 gfpga_pad_GPIO_OE[7]:7 0.0273884 +4 gfpga_pad_GPIO_OE[7]:2 gfpga_pad_GPIO_OE[7] 0.04464286 +5 gfpga_pad_GPIO_OE[7]:3 gfpga_pad_GPIO_OE[7]:2 0.04464286 +6 gfpga_pad_GPIO_OE[7]:4 gfpga_pad_GPIO_OE[7]:3 0.04464286 +7 gfpga_pad_GPIO_OE[7]:5 gfpga_pad_GPIO_OE[7]:4 0.04464286 +8 gfpga_pad_GPIO_OE[7]:7 gfpga_pad_GPIO_OE[7]:6 1e-05 +9 gfpga_pad_GPIO_OE[7]:6 gfpga_pad_GPIO_OE[7]:5 0.01695893 + +*END + +*D_NET gfpga_pad_GPIO_Y[0] 0.02224221 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[0] I *L 0 *C 430.560 1196.385 +*I grid_io_top_1__3_:gfpga_pad_GPIO_Y[0] I *L 0 *C 430.560 924.730 +*N gfpga_pad_GPIO_Y[0]:2 *C 430.560 974.730 +*N gfpga_pad_GPIO_Y[0]:3 *C 430.560 1024.730 +*N gfpga_pad_GPIO_Y[0]:4 *C 430.560 1074.730 +*N gfpga_pad_GPIO_Y[0]:5 *C 430.560 1115.519 +*N gfpga_pad_GPIO_Y[0]:6 *C 430.560 1115.520 +*N gfpga_pad_GPIO_Y[0]:7 *C 430.560 1124.730 +*N gfpga_pad_GPIO_Y[0]:8 *C 430.560 1174.730 + +*CAP +0 gfpga_pad_GPIO_Y[0] 0.0008760901 +1 grid_io_top_1__3_:gfpga_pad_GPIO_Y[0] 0.002104438 +2 gfpga_pad_GPIO_Y[0]:2 0.004139718 +3 gfpga_pad_GPIO_Y[0]:3 0.004069141 +4 gfpga_pad_GPIO_Y[0]:4 0.003705012 +5 gfpga_pad_GPIO_Y[0]:5 0.00167115 +6 gfpga_pad_GPIO_Y[0]:6 0.0003654005 +7 gfpga_pad_GPIO_Y[0]:7 0.002400286 +8 gfpga_pad_GPIO_Y[0]:8 0.002910976 + +*RES +0 gfpga_pad_GPIO_Y[0] gfpga_pad_GPIO_Y[0]:8 0.01933482 +1 gfpga_pad_GPIO_Y[0]:2 grid_io_top_1__3_:gfpga_pad_GPIO_Y[0] 0.04464286 +2 gfpga_pad_GPIO_Y[0]:3 gfpga_pad_GPIO_Y[0]:2 0.04464286 +3 gfpga_pad_GPIO_Y[0]:4 gfpga_pad_GPIO_Y[0]:3 0.04464286 +4 gfpga_pad_GPIO_Y[0]:7 gfpga_pad_GPIO_Y[0]:6 0.008223215 +5 gfpga_pad_GPIO_Y[0]:8 gfpga_pad_GPIO_Y[0]:7 0.04464286 +6 gfpga_pad_GPIO_Y[0]:6 gfpga_pad_GPIO_Y[0]:5 1e-05 +7 gfpga_pad_GPIO_Y[0]:5 gfpga_pad_GPIO_Y[0]:4 0.03641875 + +*END + +*D_NET gfpga_pad_GPIO_Y[1] 0.02758849 //LENGTH 316.455 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[1] I *L 0 *C 736.000 1196.385 +*I grid_io_top_2__3_:gfpga_pad_GPIO_Y[0] I *L 0 *C 691.840 924.730 +*N gfpga_pad_GPIO_Y[1]:2 *C 691.840 974.730 +*N gfpga_pad_GPIO_Y[1]:3 *C 691.840 1024.730 +*N gfpga_pad_GPIO_Y[1]:4 *C 691.840 1074.730 +*N gfpga_pad_GPIO_Y[1]:5 *C 691.840 1115.519 +*N gfpga_pad_GPIO_Y[1]:6 *C 691.840 1115.520 +*N gfpga_pad_GPIO_Y[1]:7 *C 691.840 1121.615 +*N gfpga_pad_GPIO_Y[1]:8 *C 691.885 1121.660 +*N gfpga_pad_GPIO_Y[1]:9 *C 735.955 1121.660 +*N gfpga_pad_GPIO_Y[1]:10 *C 736.000 1121.705 +*N gfpga_pad_GPIO_Y[1]:11 *C 736.000 1171.500 + +*CAP +0 gfpga_pad_GPIO_Y[1] 0.001070127 +1 grid_io_top_2__3_:gfpga_pad_GPIO_Y[0] 0.00218972 +2 gfpga_pad_GPIO_Y[1]:2 0.00431361 +3 gfpga_pad_GPIO_Y[1]:3 0.004239234 +4 gfpga_pad_GPIO_Y[1]:4 0.003855873 +5 gfpga_pad_GPIO_Y[1]:5 0.00174053 +6 gfpga_pad_GPIO_Y[1]:6 0.0002508157 +7 gfpga_pad_GPIO_Y[1]:7 0.0002508157 +8 gfpga_pad_GPIO_Y[1]:8 0.002160663 +9 gfpga_pad_GPIO_Y[1]:9 0.002160663 +10 gfpga_pad_GPIO_Y[1]:10 0.002143156 +11 gfpga_pad_GPIO_Y[1]:11 0.003213283 + +*RES +0 gfpga_pad_GPIO_Y[1] gfpga_pad_GPIO_Y[1]:11 0.02221875 +1 gfpga_pad_GPIO_Y[1]:8 gfpga_pad_GPIO_Y[1]:7 0.0045 +2 gfpga_pad_GPIO_Y[1]:7 gfpga_pad_GPIO_Y[1]:6 0.005441965 +3 gfpga_pad_GPIO_Y[1]:9 gfpga_pad_GPIO_Y[1]:8 0.03934822 +4 gfpga_pad_GPIO_Y[1]:10 gfpga_pad_GPIO_Y[1]:9 0.0045 +5 gfpga_pad_GPIO_Y[1]:2 grid_io_top_2__3_:gfpga_pad_GPIO_Y[0] 0.04464286 +6 gfpga_pad_GPIO_Y[1]:3 gfpga_pad_GPIO_Y[1]:2 0.04464286 +7 gfpga_pad_GPIO_Y[1]:4 gfpga_pad_GPIO_Y[1]:3 0.04464286 +8 gfpga_pad_GPIO_Y[1]:11 gfpga_pad_GPIO_Y[1]:10 0.04445982 +9 gfpga_pad_GPIO_Y[1]:6 gfpga_pad_GPIO_Y[1]:5 1e-05 +10 gfpga_pad_GPIO_Y[1]:5 gfpga_pad_GPIO_Y[1]:4 0.03641875 + +*END + +*D_NET gfpga_pad_GPIO_Y[2] 0.03086634 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[2] I *L 0 *C 1199.155 499.800 +*I grid_io_right_3__1_:gfpga_pad_GPIO_Y[0] I *L 0 *C 925.370 499.800 +*N gfpga_pad_GPIO_Y[2]:2 *C 927.353 499.800 +*N gfpga_pad_GPIO_Y[2]:3 *C 927.360 499.800 +*N gfpga_pad_GPIO_Y[2]:4 *C 927.405 499.800 +*N gfpga_pad_GPIO_Y[2]:5 *C 977.200 499.800 +*N gfpga_pad_GPIO_Y[2]:6 *C 1027.200 499.800 +*N gfpga_pad_GPIO_Y[2]:7 *C 1077.200 499.800 +*N gfpga_pad_GPIO_Y[2]:8 *C 1115.519 499.800 +*N gfpga_pad_GPIO_Y[2]:9 *C 1115.520 499.800 +*N gfpga_pad_GPIO_Y[2]:10 *C 1127.200 499.800 +*N gfpga_pad_GPIO_Y[2]:11 *C 1177.200 499.800 + +*CAP +0 gfpga_pad_GPIO_Y[2] 0.001230615 +1 grid_io_right_3__1_:gfpga_pad_GPIO_Y[0] 0.0002482439 +2 gfpga_pad_GPIO_Y[2]:2 0.0002482439 +3 gfpga_pad_GPIO_Y[2]:3 3.437844e-05 +4 gfpga_pad_GPIO_Y[2]:4 0.002794866 +5 gfpga_pad_GPIO_Y[2]:5 0.005585021 +6 gfpga_pad_GPIO_Y[2]:6 0.005580846 +7 gfpga_pad_GPIO_Y[2]:7 0.004920308 +8 gfpga_pad_GPIO_Y[2]:8 0.002129618 +9 gfpga_pad_GPIO_Y[2]:9 0.0006440619 +10 gfpga_pad_GPIO_Y[2]:10 0.003431794 +11 gfpga_pad_GPIO_Y[2]:11 0.004018347 + +*RES +0 gfpga_pad_GPIO_Y[2] gfpga_pad_GPIO_Y[2]:11 0.01960268 +1 gfpga_pad_GPIO_Y[2]:3 gfpga_pad_GPIO_Y[2]:2 0.00341 +2 gfpga_pad_GPIO_Y[2]:2 grid_io_right_3__1_:gfpga_pad_GPIO_Y[0] 0.0003105917 +3 gfpga_pad_GPIO_Y[2]:4 gfpga_pad_GPIO_Y[2]:3 0.0045 +4 gfpga_pad_GPIO_Y[2]:5 gfpga_pad_GPIO_Y[2]:4 0.04445983 +5 gfpga_pad_GPIO_Y[2]:6 gfpga_pad_GPIO_Y[2]:5 0.04464286 +6 gfpga_pad_GPIO_Y[2]:7 gfpga_pad_GPIO_Y[2]:6 0.04464286 +7 gfpga_pad_GPIO_Y[2]:10 gfpga_pad_GPIO_Y[2]:9 0.01042857 +8 gfpga_pad_GPIO_Y[2]:11 gfpga_pad_GPIO_Y[2]:10 0.04464286 +9 gfpga_pad_GPIO_Y[2]:9 gfpga_pad_GPIO_Y[2]:8 1e-05 +10 gfpga_pad_GPIO_Y[2]:8 gfpga_pad_GPIO_Y[2]:7 0.0342134 + +*END + +*D_NET gfpga_pad_GPIO_Y[3] 0.03081236 //LENGTH 327.155 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[3] I *L 0 *C 1199.155 708.220 +*I grid_io_right_3__2_:gfpga_pad_GPIO_Y[0] I *L 0 *C 925.370 760.920 +*N gfpga_pad_GPIO_Y[3]:2 *C 962.773 760.920 +*N gfpga_pad_GPIO_Y[3]:3 *C 962.780 760.863 +*N gfpga_pad_GPIO_Y[3]:4 *C 962.780 708.265 +*N gfpga_pad_GPIO_Y[3]:5 *C 962.825 708.220 +*N gfpga_pad_GPIO_Y[3]:6 *C 1012.620 708.220 +*N gfpga_pad_GPIO_Y[3]:7 *C 1062.620 708.220 +*N gfpga_pad_GPIO_Y[3]:8 *C 1112.620 708.220 +*N gfpga_pad_GPIO_Y[3]:9 *C 1115.519 708.220 +*N gfpga_pad_GPIO_Y[3]:10 *C 1115.520 708.220 +*N gfpga_pad_GPIO_Y[3]:11 *C 1162.620 708.220 + +*CAP +0 gfpga_pad_GPIO_Y[3] 0.0017575 +1 grid_io_right_3__2_:gfpga_pad_GPIO_Y[0] 0.001735329 +2 gfpga_pad_GPIO_Y[3]:2 0.001735329 +3 gfpga_pad_GPIO_Y[3]:3 0.002358709 +4 gfpga_pad_GPIO_Y[3]:4 0.002358709 +5 gfpga_pad_GPIO_Y[3]:5 0.002392154 +6 gfpga_pad_GPIO_Y[3]:6 0.004783263 +7 gfpga_pad_GPIO_Y[3]:7 0.004778164 +8 gfpga_pad_GPIO_Y[3]:8 0.002524911 +9 gfpga_pad_GPIO_Y[3]:9 0.0001378559 +10 gfpga_pad_GPIO_Y[3]:10 0.00224647 +11 gfpga_pad_GPIO_Y[3]:11 0.00400397 + +*RES +0 gfpga_pad_GPIO_Y[3] gfpga_pad_GPIO_Y[3]:11 0.03262054 +1 gfpga_pad_GPIO_Y[3]:3 gfpga_pad_GPIO_Y[3]:2 0.00341 +2 gfpga_pad_GPIO_Y[3]:2 grid_io_right_3__2_:gfpga_pad_GPIO_Y[0] 0.005859724 +3 gfpga_pad_GPIO_Y[3]:5 gfpga_pad_GPIO_Y[3]:4 0.0045 +4 gfpga_pad_GPIO_Y[3]:4 gfpga_pad_GPIO_Y[3]:3 0.04696206 +5 gfpga_pad_GPIO_Y[3]:6 gfpga_pad_GPIO_Y[3]:5 0.04445982 +6 gfpga_pad_GPIO_Y[3]:7 gfpga_pad_GPIO_Y[3]:6 0.04464286 +7 gfpga_pad_GPIO_Y[3]:8 gfpga_pad_GPIO_Y[3]:7 0.04464286 +8 gfpga_pad_GPIO_Y[3]:11 gfpga_pad_GPIO_Y[3]:10 0.04205357 +9 gfpga_pad_GPIO_Y[3]:10 gfpga_pad_GPIO_Y[3]:9 1e-05 +10 gfpga_pad_GPIO_Y[3]:9 gfpga_pad_GPIO_Y[3]:8 0.002588393 + +*END + +*D_NET gfpga_pad_GPIO_Y[4] 0.02277945 //LENGTH 265.555 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[4] I *L 0 *C 418.140 0.415 +*I grid_io_bottom_1__0_:gfpga_pad_GPIO_Y[0] I *L 0 *C 414.000 261.190 +*N gfpga_pad_GPIO_Y[4]:2 *C 414.000 256.745 +*N gfpga_pad_GPIO_Y[4]:3 *C 414.045 256.700 +*N gfpga_pad_GPIO_Y[4]:4 *C 418.095 256.700 +*N gfpga_pad_GPIO_Y[4]:5 *C 418.140 256.655 +*N gfpga_pad_GPIO_Y[4]:6 *C 418.140 250.415 +*N gfpga_pad_GPIO_Y[4]:7 *C 418.140 219.520 +*N gfpga_pad_GPIO_Y[4]:8 *C 418.140 219.519 +*N gfpga_pad_GPIO_Y[4]:9 *C 418.140 200.415 +*N gfpga_pad_GPIO_Y[4]:10 *C 418.140 150.415 +*N gfpga_pad_GPIO_Y[4]:11 *C 418.140 100.415 +*N gfpga_pad_GPIO_Y[4]:12 *C 418.140 50.415 + +*CAP +0 gfpga_pad_GPIO_Y[4] 0.002143083 +1 grid_io_bottom_1__0_:gfpga_pad_GPIO_Y[0] 0.0002437344 +2 gfpga_pad_GPIO_Y[4]:2 0.0002437344 +3 gfpga_pad_GPIO_Y[4]:3 0.000221881 +4 gfpga_pad_GPIO_Y[4]:4 0.000221881 +5 gfpga_pad_GPIO_Y[4]:5 0.000261333 +6 gfpga_pad_GPIO_Y[4]:6 0.001584483 +7 gfpga_pad_GPIO_Y[4]:7 0.00132315 +8 gfpga_pad_GPIO_Y[4]:8 0.0007989333 +9 gfpga_pad_GPIO_Y[4]:9 0.002938969 +10 gfpga_pad_GPIO_Y[4]:10 0.004276599 +11 gfpga_pad_GPIO_Y[4]:11 0.004257576 +12 gfpga_pad_GPIO_Y[4]:12 0.004264096 + +*RES +0 gfpga_pad_GPIO_Y[4] gfpga_pad_GPIO_Y[4]:12 0.04464286 +1 gfpga_pad_GPIO_Y[4]:3 gfpga_pad_GPIO_Y[4]:2 0.0045 +2 gfpga_pad_GPIO_Y[4]:2 grid_io_bottom_1__0_:gfpga_pad_GPIO_Y[0] 0.00396875 +3 gfpga_pad_GPIO_Y[4]:4 gfpga_pad_GPIO_Y[4]:3 0.003616071 +4 gfpga_pad_GPIO_Y[4]:5 gfpga_pad_GPIO_Y[4]:4 0.0045 +5 gfpga_pad_GPIO_Y[4]:12 gfpga_pad_GPIO_Y[4]:11 0.04464286 +6 gfpga_pad_GPIO_Y[4]:11 gfpga_pad_GPIO_Y[4]:10 0.04464286 +7 gfpga_pad_GPIO_Y[4]:10 gfpga_pad_GPIO_Y[4]:9 0.04464286 +8 gfpga_pad_GPIO_Y[4]:9 gfpga_pad_GPIO_Y[4]:8 0.01705714 +9 gfpga_pad_GPIO_Y[4]:6 gfpga_pad_GPIO_Y[4]:5 0.005571429 +10 gfpga_pad_GPIO_Y[4]:7 gfpga_pad_GPIO_Y[4]:6 0.02758482 +11 gfpga_pad_GPIO_Y[4]:8 gfpga_pad_GPIO_Y[4]:7 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_Y[5] 0.02231022 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[5] I *L 0 *C 675.280 0.415 +*I grid_io_bottom_2__0_:gfpga_pad_GPIO_Y[0] I *L 0 *C 675.280 261.190 +*N gfpga_pad_GPIO_Y[5]:2 *C 675.280 250.415 +*N gfpga_pad_GPIO_Y[5]:3 *C 675.280 219.520 +*N gfpga_pad_GPIO_Y[5]:4 *C 675.280 219.519 +*N gfpga_pad_GPIO_Y[5]:5 *C 675.280 200.415 +*N gfpga_pad_GPIO_Y[5]:6 *C 675.280 150.415 +*N gfpga_pad_GPIO_Y[5]:7 *C 675.280 100.415 +*N gfpga_pad_GPIO_Y[5]:8 *C 675.280 50.415 + +*CAP +0 gfpga_pad_GPIO_Y[5] 0.002143034 +1 grid_io_bottom_2__0_:gfpga_pad_GPIO_Y[0] 0.0004934301 +2 gfpga_pad_GPIO_Y[5]:2 0.001817812 +3 gfpga_pad_GPIO_Y[5]:3 0.001324382 +4 gfpga_pad_GPIO_Y[5]:4 0.000800461 +5 gfpga_pad_GPIO_Y[5]:5 0.002939865 +6 gfpga_pad_GPIO_Y[5]:6 0.004275477 +7 gfpga_pad_GPIO_Y[5]:7 0.004254397 +8 gfpga_pad_GPIO_Y[5]:8 0.004261359 + +*RES +0 gfpga_pad_GPIO_Y[5] gfpga_pad_GPIO_Y[5]:8 0.04464286 +1 gfpga_pad_GPIO_Y[5]:8 gfpga_pad_GPIO_Y[5]:7 0.04464286 +2 gfpga_pad_GPIO_Y[5]:7 gfpga_pad_GPIO_Y[5]:6 0.04464286 +3 gfpga_pad_GPIO_Y[5]:6 gfpga_pad_GPIO_Y[5]:5 0.04464286 +4 gfpga_pad_GPIO_Y[5]:5 gfpga_pad_GPIO_Y[5]:4 0.01705714 +5 gfpga_pad_GPIO_Y[5]:2 grid_io_bottom_2__0_:gfpga_pad_GPIO_Y[0] 0.009620536 +6 gfpga_pad_GPIO_Y[5]:3 gfpga_pad_GPIO_Y[5]:2 0.02758482 +7 gfpga_pad_GPIO_Y[5]:4 gfpga_pad_GPIO_Y[5]:3 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_Y[6] 0.02816848 //LENGTH 255.710 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[6] I *L 0 *C 0.525 457.640 +*I grid_io_left_0__1_:gfpga_pad_GPIO_Y[0] I *L 0 *C 255.910 457.640 +*N gfpga_pad_GPIO_Y[6]:2 *C 250.248 457.640 +*N gfpga_pad_GPIO_Y[6]:3 *C 250.240 457.640 +*N gfpga_pad_GPIO_Y[6]:4 *C 250.195 457.640 +*N gfpga_pad_GPIO_Y[6]:5 *C 219.520 457.640 +*N gfpga_pad_GPIO_Y[6]:6 *C 219.519 457.640 +*N gfpga_pad_GPIO_Y[6]:7 *C 200.525 457.640 +*N gfpga_pad_GPIO_Y[6]:8 *C 150.525 457.640 +*N gfpga_pad_GPIO_Y[6]:9 *C 100.525 457.640 +*N gfpga_pad_GPIO_Y[6]:10 *C 50.525 457.640 + +*CAP +0 gfpga_pad_GPIO_Y[6] 0.002769787 +1 grid_io_left_0__1_:gfpga_pad_GPIO_Y[0] 0.0003232506 +2 gfpga_pad_GPIO_Y[6]:2 0.0003232506 +3 gfpga_pad_GPIO_Y[6]:3 2.897629e-05 +4 gfpga_pad_GPIO_Y[6]:4 0.001694737 +5 gfpga_pad_GPIO_Y[6]:5 0.001694737 +6 gfpga_pad_GPIO_Y[6]:6 0.001040976 +7 gfpga_pad_GPIO_Y[6]:7 0.003788309 +8 gfpga_pad_GPIO_Y[6]:8 0.00549412 +9 gfpga_pad_GPIO_Y[6]:9 0.005493667 +10 gfpga_pad_GPIO_Y[6]:10 0.005516667 + +*RES +0 gfpga_pad_GPIO_Y[6] gfpga_pad_GPIO_Y[6]:10 0.04464286 +1 gfpga_pad_GPIO_Y[6]:3 gfpga_pad_GPIO_Y[6]:2 0.00341 +2 gfpga_pad_GPIO_Y[6]:2 grid_io_left_0__1_:gfpga_pad_GPIO_Y[0] 0.000887125 +3 gfpga_pad_GPIO_Y[6]:4 gfpga_pad_GPIO_Y[6]:3 0.0045 +4 gfpga_pad_GPIO_Y[6]:10 gfpga_pad_GPIO_Y[6]:9 0.04464286 +5 gfpga_pad_GPIO_Y[6]:9 gfpga_pad_GPIO_Y[6]:8 0.04464286 +6 gfpga_pad_GPIO_Y[6]:8 gfpga_pad_GPIO_Y[6]:7 0.04464286 +7 gfpga_pad_GPIO_Y[6]:7 gfpga_pad_GPIO_Y[6]:6 0.01695893 +8 gfpga_pad_GPIO_Y[6]:5 gfpga_pad_GPIO_Y[6]:4 0.0273884 +9 gfpga_pad_GPIO_Y[6]:6 gfpga_pad_GPIO_Y[6]:5 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_Y[7] 0.02470541 //LENGTH 294.135 LUMPCC 0 DR + +*CONN +*P gfpga_pad_GPIO_Y[7] I *L 0 *C 0.525 680.680 +*I grid_io_left_0__2_:gfpga_pad_GPIO_Y[0] I *L 0 *C 255.910 718.760 +*N gfpga_pad_GPIO_Y[7]:2 *C 250.755 718.760 +*N gfpga_pad_GPIO_Y[7]:3 *C 219.520 718.760 +*N gfpga_pad_GPIO_Y[7]:4 *C 219.519 718.760 +*N gfpga_pad_GPIO_Y[7]:5 *C 200.755 718.760 +*N gfpga_pad_GPIO_Y[7]:6 *C 150.755 718.760 +*N gfpga_pad_GPIO_Y[7]:7 *C 100.755 718.760 +*N gfpga_pad_GPIO_Y[7]:8 *C 50.755 718.760 +*N gfpga_pad_GPIO_Y[7]:9 *C 0.927 718.760 +*N gfpga_pad_GPIO_Y[7]:10 *C 0.920 718.702 +*N gfpga_pad_GPIO_Y[7]:11 *C 0.920 680.725 +*N gfpga_pad_GPIO_Y[7]:12 *C 0.875 680.680 + +*CAP +0 gfpga_pad_GPIO_Y[7] 3.689177e-05 +1 grid_io_left_0__2_:gfpga_pad_GPIO_Y[0] 0.0002934891 +2 gfpga_pad_GPIO_Y[7]:2 0.001594096 +3 gfpga_pad_GPIO_Y[7]:3 0.001300607 +4 gfpga_pad_GPIO_Y[7]:4 0.0007744973 +5 gfpga_pad_GPIO_Y[7]:5 0.002861017 +6 gfpga_pad_GPIO_Y[7]:6 0.004169057 +7 gfpga_pad_GPIO_Y[7]:7 0.00416772 +8 gfpga_pad_GPIO_Y[7]:8 0.004184009 +9 gfpga_pad_GPIO_Y[7]:9 0.002098826 +10 gfpga_pad_GPIO_Y[7]:10 0.001594152 +11 gfpga_pad_GPIO_Y[7]:11 0.001594152 +12 gfpga_pad_GPIO_Y[7]:12 3.689177e-05 + +*RES +0 gfpga_pad_GPIO_Y[7] gfpga_pad_GPIO_Y[7]:12 0.0003125 +1 gfpga_pad_GPIO_Y[7]:10 gfpga_pad_GPIO_Y[7]:9 0.00341 +2 gfpga_pad_GPIO_Y[7]:9 gfpga_pad_GPIO_Y[7]:8 0.007806308 +3 gfpga_pad_GPIO_Y[7]:12 gfpga_pad_GPIO_Y[7]:11 0.0045 +4 gfpga_pad_GPIO_Y[7]:11 gfpga_pad_GPIO_Y[7]:10 0.03390849 +5 gfpga_pad_GPIO_Y[7]:8 gfpga_pad_GPIO_Y[7]:7 0.007833333 +6 gfpga_pad_GPIO_Y[7]:7 gfpga_pad_GPIO_Y[7]:6 0.007833333 +7 gfpga_pad_GPIO_Y[7]:6 gfpga_pad_GPIO_Y[7]:5 0.007833333 +8 gfpga_pad_GPIO_Y[7]:5 gfpga_pad_GPIO_Y[7]:4 0.002939693 +9 gfpga_pad_GPIO_Y[7]:2 grid_io_left_0__2_:gfpga_pad_GPIO_Y[0] 0.0008076166 +10 gfpga_pad_GPIO_Y[7]:3 gfpga_pad_GPIO_Y[7]:2 0.004893483 +11 gfpga_pad_GPIO_Y[7]:4 gfpga_pad_GPIO_Y[7]:3 1e-05 + +*END + +*D_NET ccff_head[0] 0.02642738 //LENGTH 304.295 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0 *C 799.940 1196.385 +*I sb_2__2_:ccff_head[0] I *L 0 *C 799.940 892.090 +*N ccff_head[0]:2 *C 799.940 942.090 +*N ccff_head[0]:3 *C 799.940 992.090 +*N ccff_head[0]:4 *C 799.940 1042.090 +*N ccff_head[0]:5 *C 799.940 1092.090 +*N ccff_head[0]:6 *C 799.940 1115.519 +*N ccff_head[0]:7 *C 799.940 1115.520 +*N ccff_head[0]:8 *C 799.940 1142.090 + +*CAP +0 ccff_head[0] 0.002357 +1 sb_2__2_:ccff_head[0] 0.002160436 +2 ccff_head[0]:2 0.004342278 +3 ccff_head[0]:3 0.004357662 +4 ccff_head[0]:4 0.004337051 +5 ccff_head[0]:5 0.003199846 +6 ccff_head[0]:6 0.001038614 +7 ccff_head[0]:7 0.001138744 +8 ccff_head[0]:8 0.003495744 + +*RES +0 ccff_head[0] ccff_head[0]:8 0.04847769 +1 ccff_head[0]:2 sb_2__2_:ccff_head[0] 0.04464286 +2 ccff_head[0]:3 ccff_head[0]:2 0.04464286 +3 ccff_head[0]:4 ccff_head[0]:3 0.04464286 +4 ccff_head[0]:5 ccff_head[0]:4 0.04464286 +5 ccff_head[0]:8 ccff_head[0]:7 0.02372321 +6 ccff_head[0]:7 ccff_head[0]:6 1e-05 +7 ccff_head[0]:6 ccff_head[0]:5 0.02091875 + +*END + +*D_NET ccff_tail[0] 0.03204415 //LENGTH 286.990 LUMPCC 0 DR + +*CONN +*I sb_0__0_:ccff_tail[0] O *L 0 *C 287.190 362.440 +*P ccff_tail[0] O *L 0 *C 0.525 362.440 +*N ccff_tail[0]:2 *C 50.525 362.440 +*N ccff_tail[0]:3 *C 100.525 362.440 +*N ccff_tail[0]:4 *C 150.525 362.440 +*N ccff_tail[0]:5 *C 200.525 362.440 +*N ccff_tail[0]:6 *C 219.519 362.440 +*N ccff_tail[0]:7 *C 219.520 362.440 +*N ccff_tail[0]:8 *C 250.525 362.440 +*N ccff_tail[0]:9 *C 285.615 362.440 +*N ccff_tail[0]:10 *C 285.660 362.440 +*N ccff_tail[0]:11 *C 285.668 362.440 + +*CAP +0 sb_0__0_:ccff_tail[0] 0.0001440434 +1 ccff_tail[0] 0.002788402 +2 ccff_tail[0]:2 0.005570785 +3 ccff_tail[0]:3 0.005564171 +4 ccff_tail[0]:4 0.005564203 +5 ccff_tail[0]:5 0.003829446 +6 ccff_tail[0]:6 0.001047032 +7 ccff_tail[0]:7 0.001713606 +8 ccff_tail[0]:8 0.00367936 +9 ccff_tail[0]:9 0.001965754 +10 ccff_tail[0]:10 3.330885e-05 +11 ccff_tail[0]:11 0.0001440434 + +*RES +0 sb_0__0_:ccff_tail[0] ccff_tail[0]:11 0.000238525 +1 ccff_tail[0]:10 ccff_tail[0]:9 0.0045 +2 ccff_tail[0]:11 ccff_tail[0]:10 0.00341 +3 ccff_tail[0]:9 ccff_tail[0]:8 0.03133036 +4 ccff_tail[0]:2 ccff_tail[0] 0.04464286 +5 ccff_tail[0]:3 ccff_tail[0]:2 0.04464286 +6 ccff_tail[0]:4 ccff_tail[0]:3 0.04464286 +7 ccff_tail[0]:5 ccff_tail[0]:4 0.04464286 +8 ccff_tail[0]:8 ccff_tail[0]:7 0.02768304 +9 ccff_tail[0]:7 ccff_tail[0]:6 1e-05 +10 ccff_tail[0]:6 ccff_tail[0]:5 0.01695893 + +*END + +*D_NET cbx_1__0__0_ccff_tail[0] 0.001101314 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__0_:ccff_tail[0] O *L 0 *C 465.060 293.830 +*I grid_io_bottom_1__0_:ccff_head[0] I *L 0 *C 465.060 282.810 + +*CAP +0 cbx_1__0_:ccff_tail[0] 0.0005506569 +1 grid_io_bottom_1__0_:ccff_head[0] 0.0005506569 + +*RES +0 cbx_1__0_:ccff_tail[0] grid_io_bottom_1__0_:ccff_head[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[0] 0.001257426 //LENGTH 7.660 LUMPCC 0.0006887737 DR + +*CONN +*I cbx_1__0_:chanx_left_out[0] O *L 0 *C 407.710 340.000 +*I sb_0__0_:chanx_right_in[0] I *L 0 *C 400.050 340.000 + +*CAP +0 cbx_1__0_:chanx_left_out[0] 0.0002843261 +1 sb_0__0_:chanx_right_in[0] 0.0002843261 +2 cbx_1__0_:chanx_left_out[0] cbx_1__0_:chanx_left_out[7] 0.0001721934 +3 sb_0__0_:chanx_right_in[0] sb_0__0_:chanx_right_in[7] 0.0001721934 +4 cbx_1__0_:chanx_left_out[0] cbx_1__0_:chanx_left_out[13] 0.0001721934 +5 sb_0__0_:chanx_right_in[0] sb_0__0_:chanx_right_in[13] 0.0001721934 + +*RES +0 cbx_1__0_:chanx_left_out[0] sb_0__0_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[1] 0.003152352 //LENGTH 28.550 LUMPCC 0.000453423 DR + +*CONN +*I cbx_1__0_:chanx_left_out[1] O *L 0 *C 409.860 293.830 +*I sb_0__0_:chanx_right_in[1] I *L 0 *C 400.050 310.080 +*N cbx_1__0__0_chanx_left_out[1]:2 *C 405.252 310.080 +*N cbx_1__0__0_chanx_left_out[1]:3 *C 405.260 310.023 +*N cbx_1__0__0_chanx_left_out[1]:4 *C 405.260 293.125 +*N cbx_1__0__0_chanx_left_out[1]:5 *C 405.305 293.080 +*N cbx_1__0__0_chanx_left_out[1]:6 *C 409.815 293.080 +*N cbx_1__0__0_chanx_left_out[1]:7 *C 409.860 293.125 + +*CAP +0 cbx_1__0_:chanx_left_out[1] 6.505539e-05 +1 sb_0__0_:chanx_right_in[1] 0.0002188638 +2 cbx_1__0__0_chanx_left_out[1]:2 0.0002188638 +3 cbx_1__0__0_chanx_left_out[1]:3 0.0007760837 +4 cbx_1__0__0_chanx_left_out[1]:4 0.0007760837 +5 cbx_1__0__0_chanx_left_out[1]:5 0.0002894616 +6 cbx_1__0__0_chanx_left_out[1]:6 0.0002894616 +7 cbx_1__0__0_chanx_left_out[1]:7 6.505539e-05 +8 sb_0__0_:chanx_right_in[1] sb_0__0_:chanx_right_in[8] 0.0001120261 +9 cbx_1__0__0_chanx_left_out[1]:2 cbx_1__0_:chanx_left_out[8] 0.0001120261 +10 sb_0__0_:chanx_right_in[1] sb_0__0_:chanx_right_in[14] 0.0001146854 +11 cbx_1__0__0_chanx_left_out[1]:2 cbx_1__0_:chanx_left_out[14] 0.0001146854 + +*RES +0 cbx_1__0_:chanx_left_out[1] cbx_1__0__0_chanx_left_out[1]:7 0.0006294643 +1 cbx_1__0__0_chanx_left_out[1]:6 cbx_1__0__0_chanx_left_out[1]:5 0.004026786 +2 cbx_1__0__0_chanx_left_out[1]:7 cbx_1__0__0_chanx_left_out[1]:6 0.0045 +3 cbx_1__0__0_chanx_left_out[1]:5 cbx_1__0__0_chanx_left_out[1]:4 0.0045 +4 cbx_1__0__0_chanx_left_out[1]:4 cbx_1__0__0_chanx_left_out[1]:3 0.01508705 +5 cbx_1__0__0_chanx_left_out[1]:3 cbx_1__0__0_chanx_left_out[1]:2 0.00341 +6 cbx_1__0__0_chanx_left_out[1]:2 sb_0__0_:chanx_right_in[1] 0.0008150584 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[2] 0.00117924 //LENGTH 7.660 LUMPCC 0.0004826619 DR + +*CONN +*I cbx_1__0_:chanx_left_out[2] O *L 0 *C 407.710 306.000 +*I sb_0__0_:chanx_right_in[2] I *L 0 *C 400.050 306.000 + +*CAP +0 cbx_1__0_:chanx_left_out[2] 0.000348289 +1 sb_0__0_:chanx_right_in[2] 0.000348289 +2 cbx_1__0_:chanx_left_out[2] cbx_1__0_:chanx_left_out[4] 0.0001697184 +3 sb_0__0_:chanx_right_in[2] sb_0__0_:chanx_right_in[4] 0.0001697184 +4 cbx_1__0_:chanx_left_out[2] cbx_1__0_:chanx_left_out[5] 7.161257e-05 +5 sb_0__0_:chanx_right_in[2] sb_0__0_:chanx_right_in[5] 7.161257e-05 + +*RES +0 cbx_1__0_:chanx_left_out[2] sb_0__0_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[3] 0.001264741 //LENGTH 7.660 LUMPCC 0.0006775733 DR + +*CONN +*I cbx_1__0_:chanx_left_out[3] O *L 0 *C 407.710 301.920 +*I sb_0__0_:chanx_right_in[3] I *L 0 *C 400.050 301.920 + +*CAP +0 cbx_1__0_:chanx_left_out[3] 0.0002935839 +1 sb_0__0_:chanx_right_in[3] 0.0002935839 +2 cbx_1__0_:chanx_left_out[3] cbx_1__0_:chanx_left_out[5] 0.0001693933 +3 sb_0__0_:chanx_right_in[3] sb_0__0_:chanx_right_in[5] 0.0001693933 +4 cbx_1__0_:chanx_left_out[3] cbx_1__0_:chanx_left_in[2] 0.0001693933 +5 sb_0__0_:chanx_right_in[3] sb_0__0_:chanx_right_out[2] 0.0001693933 + +*RES +0 cbx_1__0_:chanx_left_out[3] sb_0__0_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[4] 0.00126423 //LENGTH 7.660 LUMPCC 0.0006788736 DR + +*CONN +*I cbx_1__0_:chanx_left_out[4] O *L 0 *C 407.710 307.360 +*I sb_0__0_:chanx_right_in[4] I *L 0 *C 400.050 307.360 + +*CAP +0 cbx_1__0_:chanx_left_out[4] 0.0002926782 +1 sb_0__0_:chanx_right_in[4] 0.0002926782 +2 cbx_1__0_:chanx_left_out[4] cbx_1__0_:chanx_left_out[2] 0.0001697184 +3 sb_0__0_:chanx_right_in[4] sb_0__0_:chanx_right_in[2] 0.0001697184 +4 cbx_1__0_:chanx_left_out[4] cbx_1__0_:chanx_left_out[8] 0.0001697184 +5 sb_0__0_:chanx_right_in[4] sb_0__0_:chanx_right_in[8] 0.0001697184 + +*RES +0 cbx_1__0_:chanx_left_out[4] sb_0__0_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[5] 0.001179529 //LENGTH 7.660 LUMPCC 0.0004820118 DR + +*CONN +*I cbx_1__0_:chanx_left_out[5] O *L 0 *C 407.710 303.280 +*I sb_0__0_:chanx_right_in[5] I *L 0 *C 400.050 303.280 + +*CAP +0 cbx_1__0_:chanx_left_out[5] 0.0003487588 +1 sb_0__0_:chanx_right_in[5] 0.0003487588 +2 cbx_1__0_:chanx_left_out[5] cbx_1__0_:chanx_left_out[2] 7.161257e-05 +3 sb_0__0_:chanx_right_in[5] sb_0__0_:chanx_right_in[2] 7.161257e-05 +4 cbx_1__0_:chanx_left_out[5] cbx_1__0_:chanx_left_out[3] 0.0001693933 +5 sb_0__0_:chanx_right_in[5] sb_0__0_:chanx_right_in[3] 0.0001693933 + +*RES +0 cbx_1__0_:chanx_left_out[5] sb_0__0_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[6] 0.001167504 //LENGTH 7.660 LUMPCC 0.0004944605 DR + +*CONN +*I cbx_1__0_:chanx_left_out[6] O *L 0 *C 407.710 325.040 +*I sb_0__0_:chanx_right_in[6] I *L 0 *C 400.050 325.040 + +*CAP +0 cbx_1__0_:chanx_left_out[6] 0.0003365216 +1 sb_0__0_:chanx_right_in[6] 0.0003365216 +2 cbx_1__0_:chanx_left_out[6] cbx_1__0_:chanx_left_out[11] 0.0001725166 +3 sb_0__0_:chanx_right_in[6] sb_0__0_:chanx_right_in[11] 0.0001725166 +4 cbx_1__0_:chanx_left_out[6] cbx_1__0_:chanx_left_in[8] 7.471367e-05 +5 sb_0__0_:chanx_right_in[6] sb_0__0_:chanx_right_out[8] 7.471367e-05 + +*RES +0 cbx_1__0_:chanx_left_out[6] sb_0__0_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[7] 0.001162379 //LENGTH 7.660 LUMPCC 0.0004981176 DR + +*CONN +*I cbx_1__0_:chanx_left_out[7] O *L 0 *C 407.710 341.360 +*I sb_0__0_:chanx_right_in[7] I *L 0 *C 400.050 341.360 + +*CAP +0 cbx_1__0_:chanx_left_out[7] 0.0003321307 +1 sb_0__0_:chanx_right_in[7] 0.0003321307 +2 cbx_1__0_:chanx_left_out[7] cbx_1__0_:chanx_left_out[0] 0.0001721934 +3 sb_0__0_:chanx_right_in[7] sb_0__0_:chanx_right_in[0] 0.0001721934 +4 cbx_1__0_:chanx_left_out[7] cbx_1__0_:chanx_left_out[18] 7.686536e-05 +5 sb_0__0_:chanx_right_in[7] sb_0__0_:chanx_right_in[18] 7.686536e-05 + +*RES +0 cbx_1__0_:chanx_left_out[7] sb_0__0_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[8] 0.001223383 //LENGTH 7.660 LUMPCC 0.0006263009 DR + +*CONN +*I cbx_1__0_:chanx_left_out[8] O *L 0 *C 407.710 308.720 +*I sb_0__0_:chanx_right_in[8] I *L 0 *C 400.050 308.720 + +*CAP +0 cbx_1__0_:chanx_left_out[8] 0.0002985412 +1 sb_0__0_:chanx_right_in[8] 0.0002985412 +2 cbx_1__0_:chanx_left_out[8] cbx_1__0__0_chanx_left_out[1]:2 0.0001120261 +3 sb_0__0_:chanx_right_in[8] sb_0__0_:chanx_right_in[1] 0.0001120261 +4 cbx_1__0_:chanx_left_out[8] cbx_1__0_:chanx_left_out[4] 0.0001697184 +5 sb_0__0_:chanx_right_in[8] sb_0__0_:chanx_right_in[4] 0.0001697184 +6 cbx_1__0_:chanx_left_out[8] cbx_1__0_:chanx_left_out[14] 3.140595e-05 +7 sb_0__0_:chanx_right_in[8] sb_0__0_:chanx_right_in[14] 3.140595e-05 + +*RES +0 cbx_1__0_:chanx_left_out[8] sb_0__0_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[9] 0.001131945 //LENGTH 7.660 LUMPCC 0.0001269543 DR + +*CONN +*I cbx_1__0_:chanx_left_out[9] O *L 0 *C 407.710 365.840 +*I sb_0__0_:chanx_right_in[9] I *L 0 *C 400.050 365.840 + +*CAP +0 cbx_1__0_:chanx_left_out[9] 0.0005024952 +1 sb_0__0_:chanx_right_in[9] 0.0005024952 +2 cbx_1__0_:chanx_left_out[9] cbx_1__0_:chanx_left_in[12] 6.347717e-05 +3 sb_0__0_:chanx_right_in[9] sb_0__0_:chanx_right_out[12] 6.347717e-05 + +*RES +0 cbx_1__0_:chanx_left_out[9] sb_0__0_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[10] 0.001175718 //LENGTH 7.660 LUMPCC 0.0004937064 DR + +*CONN +*I cbx_1__0_:chanx_left_out[10] O *L 0 *C 407.710 319.600 +*I sb_0__0_:chanx_right_in[10] I *L 0 *C 400.050 319.600 + +*CAP +0 cbx_1__0_:chanx_left_out[10] 0.0003410058 +1 sb_0__0_:chanx_right_in[10] 0.0003410058 +2 cbx_1__0_:chanx_left_out[10] cbx_1__0_:chanx_left_in[6] 7.461307e-05 +3 sb_0__0_:chanx_right_in[10] sb_0__0_:chanx_right_out[6] 7.461307e-05 +4 cbx_1__0_:chanx_left_out[10] cbx_1__0_:chanx_left_in[10] 0.0001722401 +5 sb_0__0_:chanx_right_in[10] sb_0__0_:chanx_right_out[10] 0.0001722401 + +*RES +0 cbx_1__0_:chanx_left_out[10] sb_0__0_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[11] 0.001258375 //LENGTH 7.660 LUMPCC 0.0006899569 DR + +*CONN +*I cbx_1__0_:chanx_left_out[11] O *L 0 *C 407.710 323.680 +*I sb_0__0_:chanx_right_in[11] I *L 0 *C 400.050 323.680 + +*CAP +0 cbx_1__0_:chanx_left_out[11] 0.0002842092 +1 sb_0__0_:chanx_right_in[11] 0.0002842092 +2 cbx_1__0_:chanx_left_out[11] cbx_1__0_:chanx_left_out[6] 0.0001725166 +3 sb_0__0_:chanx_right_in[11] sb_0__0_:chanx_right_in[6] 0.0001725166 +4 cbx_1__0_:chanx_left_out[11] cbx_1__0_:chanx_left_in[6] 0.0001724619 +5 sb_0__0_:chanx_right_in[11] sb_0__0_:chanx_right_out[6] 0.0001724619 + +*RES +0 cbx_1__0_:chanx_left_out[11] sb_0__0_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[12] 0.001264411 //LENGTH 7.660 LUMPCC 0.0006970388 DR + +*CONN +*I cbx_1__0_:chanx_left_out[12] O *L 0 *C 407.710 312.800 +*I sb_0__0_:chanx_right_in[12] I *L 0 *C 400.050 312.800 + +*CAP +0 cbx_1__0_:chanx_left_out[12] 0.0002836863 +1 sb_0__0_:chanx_right_in[12] 0.0002836863 +2 cbx_1__0_:chanx_left_out[12] cbx_1__0_:chanx_left_out[14] 0.0001741488 +3 sb_0__0_:chanx_right_in[12] sb_0__0_:chanx_right_in[14] 0.0001741488 +4 cbx_1__0_:chanx_left_out[12] cbx_1__0_:chanx_left_in[18] 0.0001743706 +5 sb_0__0_:chanx_right_in[12] sb_0__0_:chanx_right_out[18] 0.0001743706 + +*RES +0 cbx_1__0_:chanx_left_out[12] sb_0__0_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[13] 0.001176217 //LENGTH 7.660 LUMPCC 0.0004669367 DR + +*CONN +*I cbx_1__0_:chanx_left_out[13] O *L 0 *C 407.710 338.640 +*I sb_0__0_:chanx_right_in[13] I *L 0 *C 400.050 338.640 + +*CAP +0 cbx_1__0_:chanx_left_out[13] 0.0003546402 +1 sb_0__0_:chanx_right_in[13] 0.0003546402 +2 cbx_1__0_:chanx_left_out[13] cbx_1__0_:chanx_left_out[0] 0.0001721934 +3 sb_0__0_:chanx_right_in[13] sb_0__0_:chanx_right_in[0] 0.0001721934 +4 cbx_1__0_:chanx_left_out[13] cbx_1__0_:chanx_left_out[15] 6.127494e-05 +5 sb_0__0_:chanx_right_in[13] sb_0__0_:chanx_right_in[15] 6.127494e-05 + +*RES +0 cbx_1__0_:chanx_left_out[13] sb_0__0_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[14] 0.00122358 //LENGTH 7.660 LUMPCC 0.0006404803 DR + +*CONN +*I cbx_1__0_:chanx_left_out[14] O *L 0 *C 407.710 311.440 +*I sb_0__0_:chanx_right_in[14] I *L 0 *C 400.050 311.440 + +*CAP +0 cbx_1__0_:chanx_left_out[14] 0.0002915498 +1 sb_0__0_:chanx_right_in[14] 0.0002915498 +2 cbx_1__0_:chanx_left_out[14] cbx_1__0__0_chanx_left_out[1]:2 0.0001146854 +3 sb_0__0_:chanx_right_in[14] sb_0__0_:chanx_right_in[1] 0.0001146854 +4 cbx_1__0_:chanx_left_out[14] cbx_1__0_:chanx_left_out[8] 3.140595e-05 +5 sb_0__0_:chanx_right_in[14] sb_0__0_:chanx_right_in[8] 3.140595e-05 +6 cbx_1__0_:chanx_left_out[14] cbx_1__0_:chanx_left_out[12] 0.0001741488 +7 sb_0__0_:chanx_right_in[14] sb_0__0_:chanx_right_in[12] 0.0001741488 + +*RES +0 cbx_1__0_:chanx_left_out[14] sb_0__0_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[15] 0.001193805 //LENGTH 7.660 LUMPCC 0.000467524 DR + +*CONN +*I cbx_1__0_:chanx_left_out[15] O *L 0 *C 407.710 335.920 +*I sb_0__0_:chanx_right_in[15] I *L 0 *C 400.050 335.920 + +*CAP +0 cbx_1__0_:chanx_left_out[15] 0.0003631403 +1 sb_0__0_:chanx_right_in[15] 0.0003631403 +2 cbx_1__0_:chanx_left_out[15] cbx_1__0_:chanx_left_out[13] 6.127494e-05 +3 sb_0__0_:chanx_right_in[15] sb_0__0_:chanx_right_in[13] 6.127494e-05 +4 cbx_1__0_:chanx_left_out[15] cbx_1__0_:chanx_left_in[9] 0.000172487 +5 sb_0__0_:chanx_right_in[15] sb_0__0_:chanx_right_out[9] 0.000172487 + +*RES +0 cbx_1__0_:chanx_left_out[15] sb_0__0_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[16] 0.001076072 //LENGTH 7.660 LUMPCC 0.0001160561 DR + +*CONN +*I cbx_1__0_:chanx_left_out[16] O *L 0 *C 407.710 297.840 +*I sb_0__0_:chanx_right_in[16] I *L 0 *C 400.050 297.840 + +*CAP +0 cbx_1__0_:chanx_left_out[16] 0.000480008 +1 sb_0__0_:chanx_right_in[16] 0.000480008 +2 cbx_1__0_:chanx_left_out[16] cbx_1__0_:chanx_left_in[2] 5.802804e-05 +3 sb_0__0_:chanx_right_in[16] sb_0__0_:chanx_right_out[2] 5.802804e-05 + +*RES +0 cbx_1__0_:chanx_left_out[16] sb_0__0_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[17] 0.001216883 //LENGTH 7.660 LUMPCC 0.0004618516 DR + +*CONN +*I cbx_1__0_:chanx_left_out[17] O *L 0 *C 407.710 357.680 +*I sb_0__0_:chanx_right_in[17] I *L 0 *C 400.050 357.680 + +*CAP +0 cbx_1__0_:chanx_left_out[17] 0.0003775157 +1 sb_0__0_:chanx_right_in[17] 0.0003775157 +2 cbx_1__0_:chanx_left_out[17] cbx_1__0_:chanx_left_in[1] 6.640785e-05 +3 sb_0__0_:chanx_right_in[17] sb_0__0_:chanx_right_out[1] 6.640785e-05 +4 cbx_1__0_:chanx_left_out[17] cbx_1__0_:chanx_left_in[17] 0.000164518 +5 sb_0__0_:chanx_right_in[17] sb_0__0_:chanx_right_out[17] 0.000164518 + +*RES +0 cbx_1__0_:chanx_left_out[17] sb_0__0_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[18] 0.001161983 //LENGTH 7.660 LUMPCC 0.0005025248 DR + +*CONN +*I cbx_1__0_:chanx_left_out[18] O *L 0 *C 407.710 344.080 +*I sb_0__0_:chanx_right_in[18] I *L 0 *C 400.050 344.080 + +*CAP +0 cbx_1__0_:chanx_left_out[18] 0.0003297289 +1 sb_0__0_:chanx_right_in[18] 0.0003297289 +2 cbx_1__0_:chanx_left_out[18] cbx_1__0_:chanx_left_out[7] 7.686536e-05 +3 sb_0__0_:chanx_right_in[18] sb_0__0_:chanx_right_in[7] 7.686536e-05 +4 cbx_1__0_:chanx_left_out[18] cbx_1__0_:chanx_left_in[7] 0.000174397 +5 sb_0__0_:chanx_right_in[18] sb_0__0_:chanx_right_out[7] 0.000174397 + +*RES +0 cbx_1__0_:chanx_left_out[18] sb_0__0_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_left_out[19] 0.001246436 //LENGTH 7.660 LUMPCC 0.0006357708 DR + +*CONN +*I cbx_1__0_:chanx_left_out[19] O *L 0 *C 407.710 352.240 +*I sb_0__0_:chanx_right_in[19] I *L 0 *C 400.050 352.240 + +*CAP +0 cbx_1__0_:chanx_left_out[19] 0.0003053324 +1 sb_0__0_:chanx_right_in[19] 0.0003053324 +2 cbx_1__0_:chanx_left_out[19] sb_0__0__0_chanx_right_out[0]:7 0.0001258722 +3 sb_0__0_:chanx_right_in[19] sb_0__0_:chanx_right_out[0] 0.0001258722 +4 cbx_1__0_:chanx_left_out[19] cbx_1__0_:chanx_left_in[5] 0.0001719349 +5 sb_0__0_:chanx_right_in[19] sb_0__0_:chanx_right_out[5] 0.0001719349 +6 cbx_1__0_:chanx_left_out[19] cbx_1__0_:chanx_left_in[13] 2.007841e-05 +7 sb_0__0_:chanx_right_in[19] sb_0__0_:chanx_right_out[13] 2.007841e-05 + +*RES +0 cbx_1__0_:chanx_left_out[19] sb_0__0_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[0] 0.002751013 //LENGTH 24.270 LUMPCC 0.0003795431 DR + +*CONN +*I cbx_1__0_:chanx_right_out[0] O *L 0 *C 508.300 369.850 +*I sb_1__0_:chanx_left_in[0] I *L 0 *C 519.950 361.080 +*N cbx_1__0__0_chanx_right_out[0]:2 *C 517.048 361.080 +*N cbx_1__0__0_chanx_right_out[0]:3 *C 517.040 361.138 +*N cbx_1__0__0_chanx_right_out[0]:4 *C 517.040 371.235 +*N cbx_1__0__0_chanx_right_out[0]:5 *C 516.995 371.280 +*N cbx_1__0__0_chanx_right_out[0]:6 *C 508.345 371.280 +*N cbx_1__0__0_chanx_right_out[0]:7 *C 508.300 371.235 + +*CAP +0 cbx_1__0_:chanx_right_out[0] 0.0001083121 +1 sb_1__0_:chanx_left_in[0] 0.000168058 +2 cbx_1__0__0_chanx_right_out[0]:2 0.000168058 +3 cbx_1__0__0_chanx_right_out[0]:3 0.0004827412 +4 cbx_1__0__0_chanx_right_out[0]:4 0.0004827412 +5 cbx_1__0__0_chanx_right_out[0]:5 0.0004266238 +6 cbx_1__0__0_chanx_right_out[0]:6 0.0004266238 +7 cbx_1__0__0_chanx_right_out[0]:7 0.0001083121 +8 cbx_1__0_:chanx_right_out[0] cbx_1__0_:chanx_right_out[4] 4.600269e-07 +9 cbx_1__0__0_chanx_right_out[0]:6 cbx_1__0__0_chanx_right_out[4]:6 7.585785e-05 +10 cbx_1__0__0_chanx_right_out[0]:7 cbx_1__0__0_chanx_right_out[4]:7 4.600269e-07 +11 cbx_1__0__0_chanx_right_out[0]:5 cbx_1__0__0_chanx_right_out[4]:5 7.585785e-05 +12 cbx_1__0__0_chanx_right_out[0]:4 cbx_1__0__0_chanx_right_out[4]:4 1.680261e-05 +13 cbx_1__0__0_chanx_right_out[0]:3 cbx_1__0__0_chanx_right_out[4]:3 1.680261e-05 +14 sb_1__0_:chanx_left_in[0] sb_1__0_:chanx_left_in[11] 3.638849e-05 +15 cbx_1__0__0_chanx_right_out[0]:2 cbx_1__0_:chanx_right_out[11] 3.638849e-05 +16 sb_1__0_:chanx_left_in[0] sb_1__0_:chanx_left_out[13] 6.026256e-05 +17 cbx_1__0__0_chanx_right_out[0]:2 cbx_1__0_:chanx_right_in[13] 6.026256e-05 + +*RES +0 cbx_1__0_:chanx_right_out[0] cbx_1__0__0_chanx_right_out[0]:7 0.001236607 +1 cbx_1__0__0_chanx_right_out[0]:6 cbx_1__0__0_chanx_right_out[0]:5 0.007723215 +2 cbx_1__0__0_chanx_right_out[0]:7 cbx_1__0__0_chanx_right_out[0]:6 0.0045 +3 cbx_1__0__0_chanx_right_out[0]:5 cbx_1__0__0_chanx_right_out[0]:4 0.0045 +4 cbx_1__0__0_chanx_right_out[0]:4 cbx_1__0__0_chanx_right_out[0]:3 0.009015625 +5 cbx_1__0__0_chanx_right_out[0]:3 cbx_1__0__0_chanx_right_out[0]:2 0.00341 +6 cbx_1__0__0_chanx_right_out[0]:2 sb_1__0_:chanx_left_in[0] 0.000454725 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[1] 0.001358026 //LENGTH 7.660 LUMPCC 0.0005976933 DR + +*CONN +*I cbx_1__0_:chanx_right_out[1] O *L 0 *C 512.290 348.160 +*I sb_1__0_:chanx_left_in[1] I *L 0 *C 519.950 348.160 + +*CAP +0 cbx_1__0_:chanx_right_out[1] 0.0003801662 +1 sb_1__0_:chanx_left_in[1] 0.0003801662 +2 cbx_1__0_:chanx_right_out[1] cbx_1__0_:chanx_right_out[3] 0.0001494233 +3 sb_1__0_:chanx_left_in[1] sb_1__0_:chanx_left_in[3] 0.0001494233 +4 cbx_1__0_:chanx_right_out[1] cbx_1__0_:ccff_head[0] 0.0001494233 +5 sb_1__0_:chanx_left_in[1] sb_1__0_:ccff_tail[0] 0.0001494233 + +*RES +0 cbx_1__0_:chanx_right_out[1] sb_1__0_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[2] 0.005593386 //LENGTH 44.605 LUMPCC 0.001193116 DR + +*CONN +*I cbx_1__0_:chanx_right_out[2] O *L 0 *C 507.840 369.770 +*I sb_1__0_:chanx_left_in[2] I *L 0 *C 519.950 345.440 +*N cbx_1__0__0_chanx_right_out[2]:2 *C 517.980 345.440 +*N cbx_1__0__0_chanx_right_out[2]:3 *C 517.960 345.447 +*N cbx_1__0__0_chanx_right_out[2]:4 *C 517.960 373.312 +*N cbx_1__0__0_chanx_right_out[2]:5 *C 517.940 373.320 +*N cbx_1__0__0_chanx_right_out[2]:6 *C 507.860 373.320 +*N cbx_1__0__0_chanx_right_out[2]:7 *C 507.840 373.312 + +*CAP +0 cbx_1__0_:chanx_right_out[2] 0.0002337919 +1 sb_1__0_:chanx_left_in[2] 0.0001040141 +2 cbx_1__0__0_chanx_right_out[2]:2 0.0001040141 +3 cbx_1__0__0_chanx_right_out[2]:3 0.001334459 +4 cbx_1__0__0_chanx_right_out[2]:4 0.001334459 +5 cbx_1__0__0_chanx_right_out[2]:5 0.0005278701 +6 cbx_1__0__0_chanx_right_out[2]:6 0.0005278701 +7 cbx_1__0__0_chanx_right_out[2]:7 0.0002337919 +8 sb_1__0_:chanx_left_in[2] sb_1__0_:chanx_left_in[3] 4.573824e-05 +9 cbx_1__0__0_chanx_right_out[2]:2 cbx_1__0_:chanx_right_out[3] 4.573824e-05 +10 sb_1__0_:chanx_left_in[2] sb_1__0_:chanx_left_in[5] 5.130521e-05 +11 cbx_1__0__0_chanx_right_out[2]:2 cbx_1__0_:chanx_right_out[5] 5.130521e-05 +12 cbx_1__0__0_chanx_right_out[2]:4 cbx_1__0__0_chanx_right_out[10]:4 0.0003978454 +13 cbx_1__0__0_chanx_right_out[2]:3 cbx_1__0__0_chanx_right_out[10]:3 0.0003978454 +14 cbx_1__0__0_chanx_right_out[2]:6 ctsbuf_net_1019:4 0.0001016692 +15 cbx_1__0__0_chanx_right_out[2]:5 ctsbuf_net_1019:5 0.0001016692 + +*RES +0 cbx_1__0_:chanx_right_out[2] cbx_1__0__0_chanx_right_out[2]:7 0.0005549917 +1 cbx_1__0__0_chanx_right_out[2]:6 cbx_1__0__0_chanx_right_out[2]:5 0.0015792 +2 cbx_1__0__0_chanx_right_out[2]:7 cbx_1__0__0_chanx_right_out[2]:6 0.00341 +3 cbx_1__0__0_chanx_right_out[2]:5 cbx_1__0__0_chanx_right_out[2]:4 0.00341 +4 cbx_1__0__0_chanx_right_out[2]:4 cbx_1__0__0_chanx_right_out[2]:3 0.004365516 +5 cbx_1__0__0_chanx_right_out[2]:2 sb_1__0_:chanx_left_in[2] 0.0003086333 +6 cbx_1__0__0_chanx_right_out[2]:3 cbx_1__0__0_chanx_right_out[2]:2 0.00341 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[3] 0.001333413 //LENGTH 7.660 LUMPCC 0.0004587068 DR + +*CONN +*I cbx_1__0_:chanx_right_out[3] O *L 0 *C 512.290 346.800 +*I sb_1__0_:chanx_left_in[3] I *L 0 *C 519.950 346.800 + +*CAP +0 cbx_1__0_:chanx_right_out[3] 0.0004373533 +1 sb_1__0_:chanx_left_in[3] 0.0004373533 +2 cbx_1__0_:chanx_right_out[3] cbx_1__0_:chanx_right_out[1] 0.0001494233 +3 sb_1__0_:chanx_left_in[3] sb_1__0_:chanx_left_in[1] 0.0001494233 +4 cbx_1__0_:chanx_right_out[3] cbx_1__0__0_chanx_right_out[2]:2 4.573824e-05 +5 sb_1__0_:chanx_left_in[3] sb_1__0_:chanx_left_in[2] 4.573824e-05 +6 cbx_1__0_:chanx_right_out[3] cbx_1__0_:chanx_right_out[5] 3.419181e-05 +7 sb_1__0_:chanx_left_in[3] sb_1__0_:chanx_left_in[5] 3.419181e-05 + +*RES +0 cbx_1__0_:chanx_right_out[3] sb_1__0_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[4] 0.003262428 //LENGTH 25.830 LUMPCC 0.0008773984 DR + +*CONN +*I cbx_1__0_:chanx_right_out[4] O *L 0 *C 510.140 369.850 +*I sb_1__0_:chanx_left_in[4] I *L 0 *C 519.950 356.320 +*N cbx_1__0__0_chanx_right_out[4]:2 *C 514.288 356.320 +*N cbx_1__0__0_chanx_right_out[4]:3 *C 514.280 356.377 +*N cbx_1__0__0_chanx_right_out[4]:4 *C 514.280 370.555 +*N cbx_1__0__0_chanx_right_out[4]:5 *C 514.235 370.600 +*N cbx_1__0__0_chanx_right_out[4]:6 *C 510.185 370.600 +*N cbx_1__0__0_chanx_right_out[4]:7 *C 510.140 370.555 + +*CAP +0 cbx_1__0_:chanx_right_out[4] 6.508863e-05 +1 sb_1__0_:chanx_left_in[4] 0.0003231477 +2 cbx_1__0__0_chanx_right_out[4]:2 0.0003231477 +3 cbx_1__0__0_chanx_right_out[4]:3 0.0005831406 +4 cbx_1__0__0_chanx_right_out[4]:4 0.0005831406 +5 cbx_1__0__0_chanx_right_out[4]:5 0.0002211379 +6 cbx_1__0__0_chanx_right_out[4]:6 0.0002211379 +7 cbx_1__0__0_chanx_right_out[4]:7 6.508863e-05 +8 cbx_1__0_:chanx_right_out[4] cbx_1__0_:chanx_right_out[0] 4.600269e-07 +9 cbx_1__0__0_chanx_right_out[4]:6 cbx_1__0__0_chanx_right_out[0]:6 7.585785e-05 +10 cbx_1__0__0_chanx_right_out[4]:7 cbx_1__0__0_chanx_right_out[0]:7 4.600269e-07 +11 cbx_1__0__0_chanx_right_out[4]:5 cbx_1__0__0_chanx_right_out[0]:5 7.585785e-05 +12 cbx_1__0__0_chanx_right_out[4]:4 cbx_1__0__0_chanx_right_out[0]:4 1.680261e-05 +13 cbx_1__0__0_chanx_right_out[4]:3 cbx_1__0__0_chanx_right_out[0]:3 1.680261e-05 +14 sb_1__0_:chanx_left_in[4] sb_1__0_:chanx_left_out[1] 6.380571e-05 +15 cbx_1__0__0_chanx_right_out[4]:2 cbx_1__0_:chanx_right_in[1] 6.380571e-05 +16 sb_1__0_:chanx_left_in[4] sb_1__0_:chanx_left_out[5] 0.0001066989 +17 cbx_1__0__0_chanx_right_out[4]:2 cbx_1__0_:chanx_right_in[5] 0.0001066989 +18 cbx_1__0__0_chanx_right_out[4]:4 ctsbuf_net_211:6 0.0001750741 +19 cbx_1__0__0_chanx_right_out[4]:3 ctsbuf_net_211:5 0.0001750741 + +*RES +0 cbx_1__0_:chanx_right_out[4] cbx_1__0__0_chanx_right_out[4]:7 0.0006294643 +1 cbx_1__0__0_chanx_right_out[4]:6 cbx_1__0__0_chanx_right_out[4]:5 0.003616072 +2 cbx_1__0__0_chanx_right_out[4]:7 cbx_1__0__0_chanx_right_out[4]:6 0.0045 +3 cbx_1__0__0_chanx_right_out[4]:5 cbx_1__0__0_chanx_right_out[4]:4 0.0045 +4 cbx_1__0__0_chanx_right_out[4]:4 cbx_1__0__0_chanx_right_out[4]:3 0.01265848 +5 cbx_1__0__0_chanx_right_out[4]:3 cbx_1__0__0_chanx_right_out[4]:2 0.00341 +6 cbx_1__0__0_chanx_right_out[4]:2 sb_1__0_:chanx_left_in[4] 0.0008871249 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[5] 0.001263328 //LENGTH 7.660 LUMPCC 0.0004963146 DR + +*CONN +*I cbx_1__0_:chanx_right_out[5] O *L 0 *C 512.290 344.080 +*I sb_1__0_:chanx_left_in[5] I *L 0 *C 519.950 344.080 + +*CAP +0 cbx_1__0_:chanx_right_out[5] 0.0003835064 +1 sb_1__0_:chanx_left_in[5] 0.0003835064 +2 cbx_1__0_:chanx_right_out[5] cbx_1__0__0_chanx_right_out[2]:2 5.130521e-05 +3 sb_1__0_:chanx_left_in[5] sb_1__0_:chanx_left_in[2] 5.130521e-05 +4 cbx_1__0_:chanx_right_out[5] cbx_1__0_:chanx_right_out[3] 3.419181e-05 +5 sb_1__0_:chanx_left_in[5] sb_1__0_:chanx_left_in[3] 3.419181e-05 +6 cbx_1__0_:chanx_right_out[5] cbx_1__0_:chanx_right_in[7] 0.0001626603 +7 sb_1__0_:chanx_left_in[5] sb_1__0_:chanx_left_out[7] 0.0001626603 + +*RES +0 cbx_1__0_:chanx_right_out[5] sb_1__0_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[6] 0.001197528 //LENGTH 7.660 LUMPCC 0.0004591575 DR + +*CONN +*I cbx_1__0_:chanx_right_out[6] O *L 0 *C 512.290 341.360 +*I sb_1__0_:chanx_left_in[6] I *L 0 *C 519.950 341.360 + +*CAP +0 cbx_1__0_:chanx_right_out[6] 0.0003691854 +1 sb_1__0_:chanx_left_in[6] 0.0003691854 +2 cbx_1__0_:chanx_right_out[6] cbx_1__0_:chanx_right_out[13] 6.691849e-05 +3 sb_1__0_:chanx_left_in[6] sb_1__0_:chanx_left_in[13] 6.691849e-05 +4 cbx_1__0_:chanx_right_out[6] cbx_1__0_:chanx_right_in[7] 0.0001626603 +5 sb_1__0_:chanx_left_in[6] sb_1__0_:chanx_left_out[7] 0.0001626603 + +*RES +0 cbx_1__0_:chanx_right_out[6] sb_1__0_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[7] 0.001401721 //LENGTH 7.660 LUMPCC 0.0005444887 DR + +*CONN +*I cbx_1__0_:chanx_right_out[7] O *L 0 *C 512.290 364.480 +*I sb_1__0_:chanx_left_in[7] I *L 0 *C 519.950 364.480 + +*CAP +0 cbx_1__0_:chanx_right_out[7] 0.0004286162 +1 sb_1__0_:chanx_left_in[7] 0.0004286162 +2 cbx_1__0_:chanx_right_out[7] cbx_1__0_:chanx_right_out[9] 0.0001359522 +3 sb_1__0_:chanx_left_in[7] sb_1__0_:chanx_left_in[9] 0.0001359522 +4 cbx_1__0_:chanx_right_out[7] cbx_1__0_:chanx_right_out[11] 0.0001362921 +5 sb_1__0_:chanx_left_in[7] sb_1__0_:chanx_left_in[11] 0.0001362921 + +*RES +0 cbx_1__0_:chanx_right_out[7] sb_1__0_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[8] 0.001318368 //LENGTH 7.660 LUMPCC 0.0006404237 DR + +*CONN +*I cbx_1__0_:chanx_right_out[8] O *L 0 *C 512.290 326.400 +*I sb_1__0_:chanx_left_in[8] I *L 0 *C 519.950 326.400 + +*CAP +0 cbx_1__0_:chanx_right_out[8] 0.0003389723 +1 sb_1__0_:chanx_left_in[8] 0.0003389723 +2 cbx_1__0_:chanx_right_out[8] cbx_1__0_:chanx_right_in[9] 0.000159936 +3 sb_1__0_:chanx_left_in[8] sb_1__0_:chanx_left_out[9] 0.000159936 +4 cbx_1__0_:chanx_right_out[8] cbx_1__0_:chanx_right_in[16] 0.0001602759 +5 sb_1__0_:chanx_left_in[8] sb_1__0_:chanx_left_out[16] 0.0001602759 + +*RES +0 cbx_1__0_:chanx_right_out[8] sb_1__0_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[9] 0.001338141 //LENGTH 7.660 LUMPCC 0.0002719045 DR + +*CONN +*I cbx_1__0_:chanx_right_out[9] O *L 0 *C 512.290 365.840 +*I sb_1__0_:chanx_left_in[9] I *L 0 *C 519.950 365.840 + +*CAP +0 cbx_1__0_:chanx_right_out[9] 0.0005331182 +1 sb_1__0_:chanx_left_in[9] 0.0005331182 +2 cbx_1__0_:chanx_right_out[9] cbx_1__0_:chanx_right_out[7] 0.0001359522 +3 sb_1__0_:chanx_left_in[9] sb_1__0_:chanx_left_in[7] 0.0001359522 + +*RES +0 cbx_1__0_:chanx_right_out[9] sb_1__0_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[10] 0.004392853 //LENGTH 32.260 LUMPCC 0.001408915 DR + +*CONN +*I cbx_1__0_:chanx_right_out[10] O *L 0 *C 509.220 369.850 +*I sb_1__0_:chanx_left_in[10] I *L 0 *C 519.950 350.880 +*N cbx_1__0__0_chanx_right_out[10]:2 *C 516.140 350.880 +*N cbx_1__0__0_chanx_right_out[10]:3 *C 516.120 350.887 +*N cbx_1__0__0_chanx_right_out[10]:4 *C 516.120 370.593 +*N cbx_1__0__0_chanx_right_out[10]:5 *C 516.100 370.600 +*N cbx_1__0__0_chanx_right_out[10]:6 *C 509.228 370.600 +*N cbx_1__0__0_chanx_right_out[10]:7 *C 509.220 370.543 + +*CAP +0 cbx_1__0_:chanx_right_out[10] 6.782555e-05 +1 sb_1__0_:chanx_left_in[10] 0.0001780894 +2 cbx_1__0__0_chanx_right_out[10]:2 0.0001780894 +3 cbx_1__0__0_chanx_right_out[10]:3 0.0008312378 +4 cbx_1__0__0_chanx_right_out[10]:4 0.0008312378 +5 cbx_1__0__0_chanx_right_out[10]:5 0.0004148165 +6 cbx_1__0__0_chanx_right_out[10]:6 0.0004148165 +7 cbx_1__0__0_chanx_right_out[10]:7 6.782555e-05 +8 cbx_1__0__0_chanx_right_out[10]:4 cbx_1__0__0_chanx_right_out[2]:4 0.0003978454 +9 cbx_1__0__0_chanx_right_out[10]:3 cbx_1__0__0_chanx_right_out[2]:3 0.0003978454 +10 sb_1__0_:chanx_left_in[10] sb_1__0_:ccff_tail[0] 8.331719e-05 +11 cbx_1__0__0_chanx_right_out[10]:2 cbx_1__0_:ccff_head[0] 8.331719e-05 +12 sb_1__0_:chanx_left_in[10] sb_1__0_:chanx_left_out[19] 8.416687e-05 +13 cbx_1__0__0_chanx_right_out[10]:2 cbx_1__0_:chanx_right_in[19] 8.416687e-05 +14 cbx_1__0__0_chanx_right_out[10]:6 ctsbuf_net_1019:4 0.0001391282 +15 cbx_1__0__0_chanx_right_out[10]:5 ctsbuf_net_1019:5 0.0001391282 + +*RES +0 cbx_1__0_:chanx_right_out[10] cbx_1__0__0_chanx_right_out[10]:7 0.0006183035 +1 cbx_1__0__0_chanx_right_out[10]:7 cbx_1__0__0_chanx_right_out[10]:6 0.00341 +2 cbx_1__0__0_chanx_right_out[10]:6 cbx_1__0__0_chanx_right_out[10]:5 0.001076692 +3 cbx_1__0__0_chanx_right_out[10]:5 cbx_1__0__0_chanx_right_out[10]:4 0.00341 +4 cbx_1__0__0_chanx_right_out[10]:4 cbx_1__0__0_chanx_right_out[10]:3 0.003087117 +5 cbx_1__0__0_chanx_right_out[10]:2 sb_1__0_:chanx_left_in[10] 0.0005968999 +6 cbx_1__0__0_chanx_right_out[10]:3 cbx_1__0__0_chanx_right_out[10]:2 0.00341 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[11] 0.001344713 //LENGTH 7.660 LUMPCC 0.0003453612 DR + +*CONN +*I cbx_1__0_:chanx_right_out[11] O *L 0 *C 512.290 363.120 +*I sb_1__0_:chanx_left_in[11] I *L 0 *C 519.950 363.120 + +*CAP +0 cbx_1__0_:chanx_right_out[11] 0.0004996757 +1 sb_1__0_:chanx_left_in[11] 0.0004996757 +2 cbx_1__0_:chanx_right_out[11] cbx_1__0__0_chanx_right_out[0]:2 3.638849e-05 +3 sb_1__0_:chanx_left_in[11] sb_1__0_:chanx_left_in[0] 3.638849e-05 +4 cbx_1__0_:chanx_right_out[11] cbx_1__0_:chanx_right_out[7] 0.0001362921 +5 sb_1__0_:chanx_left_in[11] sb_1__0_:chanx_left_in[7] 0.0001362921 + +*RES +0 cbx_1__0_:chanx_right_out[11] sb_1__0_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[12] 0.00124391 //LENGTH 7.660 LUMPCC 0.0004596052 DR + +*CONN +*I cbx_1__0_:chanx_right_out[12] O *L 0 *C 512.290 330.480 +*I sb_1__0_:chanx_left_in[12] I *L 0 *C 519.950 330.480 + +*CAP +0 cbx_1__0_:chanx_right_out[12] 0.0003921523 +1 sb_1__0_:chanx_left_in[12] 0.0003921523 +2 cbx_1__0_:chanx_right_out[12] cbx_1__0_:chanx_right_in[9] 6.613527e-05 +3 sb_1__0_:chanx_left_in[12] sb_1__0_:chanx_left_out[9] 6.613527e-05 +4 cbx_1__0_:chanx_right_out[12] cbx_1__0_:chanx_right_in[11] 0.0001636673 +5 sb_1__0_:chanx_left_in[12] sb_1__0_:chanx_left_out[11] 0.0001636673 + +*RES +0 cbx_1__0_:chanx_right_out[12] sb_1__0_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[13] 0.001251198 //LENGTH 7.660 LUMPCC 0.0004536574 DR + +*CONN +*I cbx_1__0_:chanx_right_out[13] O *L 0 *C 512.290 338.640 +*I sb_1__0_:chanx_left_in[13] I *L 0 *C 519.950 338.640 + +*CAP +0 cbx_1__0_:chanx_right_out[13] 0.0003987706 +1 sb_1__0_:chanx_left_in[13] 0.0003987706 +2 cbx_1__0_:chanx_right_out[13] cbx_1__0_:chanx_right_out[6] 6.691849e-05 +3 sb_1__0_:chanx_left_in[13] sb_1__0_:chanx_left_in[6] 6.691849e-05 +4 cbx_1__0_:chanx_right_out[13] cbx_1__0_:chanx_right_in[17] 0.0001599102 +5 sb_1__0_:chanx_left_in[13] sb_1__0_:chanx_left_out[17] 0.0001599102 + +*RES +0 cbx_1__0_:chanx_right_out[13] sb_1__0_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[14] 0.002027459 //LENGTH 10.220 LUMPCC 0.0009775726 DR + +*CONN +*I cbx_1__0_:chanx_right_out[14] O *L 0 *C 512.290 300.560 +*I sb_1__0_:chanx_left_in[14] I *L 0 *C 519.950 300.560 +*N cbx_1__0__0_chanx_right_out[14]:2 *C 519.340 300.560 +*N cbx_1__0__0_chanx_right_out[14]:3 *C 519.340 299.880 +*N cbx_1__0__0_chanx_right_out[14]:4 *C 513.360 299.880 +*N cbx_1__0__0_chanx_right_out[14]:5 *C 513.360 300.560 + +*CAP +0 cbx_1__0_:chanx_right_out[14] 0.0001498362 +1 sb_1__0_:chanx_left_in[14] 0.0001045879 +2 cbx_1__0__0_chanx_right_out[14]:2 0.0001617018 +3 cbx_1__0__0_chanx_right_out[14]:3 0.0003024466 +4 cbx_1__0__0_chanx_right_out[14]:4 0.0002134049 +5 cbx_1__0__0_chanx_right_out[14]:5 0.0001179084 +6 cbx_1__0_:chanx_right_out[14] cbx_1__0_:chanx_right_out[18] 6.423301e-06 +7 sb_1__0_:chanx_left_in[14] sb_1__0_:chanx_left_in[18] 7.824093e-07 +8 cbx_1__0__0_chanx_right_out[14]:5 sb_1__0_:chanx_left_in[18] 6.423301e-06 +9 cbx_1__0__0_chanx_right_out[14]:4 cbx_1__0_:chanx_right_out[18] 0.0003533912 +10 cbx_1__0__0_chanx_right_out[14]:3 sb_1__0_:chanx_left_in[18] 0.0003533912 +11 cbx_1__0__0_chanx_right_out[14]:2 cbx_1__0_:chanx_right_out[18] 7.824093e-07 +12 sb_1__0_:chanx_left_in[14] sb_1__0_:chanx_left_out[18] 4.231682e-06 +13 cbx_1__0__0_chanx_right_out[14]:4 cbx_1__0_:chanx_right_in[18] 2.448635e-05 +14 cbx_1__0__0_chanx_right_out[14]:3 sb_1__0_:chanx_left_out[18] 2.448635e-05 +15 cbx_1__0__0_chanx_right_out[14]:2 cbx_1__0_:chanx_right_in[18] 4.231682e-06 +16 cbx_1__0__0_chanx_right_out[14]:5 ctsbuf_net_211:5 9.947135e-05 +17 cbx_1__0__0_chanx_right_out[14]:4 ctsbuf_net_211:4 9.947135e-05 + +*RES +0 cbx_1__0_:chanx_right_out[14] cbx_1__0__0_chanx_right_out[14]:5 0.0001676333 +1 cbx_1__0__0_chanx_right_out[14]:5 cbx_1__0__0_chanx_right_out[14]:4 0.0001065333 +2 cbx_1__0__0_chanx_right_out[14]:4 cbx_1__0__0_chanx_right_out[14]:3 0.0009368666 +3 cbx_1__0__0_chanx_right_out[14]:3 cbx_1__0__0_chanx_right_out[14]:2 0.0001065333 +4 cbx_1__0__0_chanx_right_out[14]:2 sb_1__0_:chanx_left_in[14] 9.556666e-05 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[15] 0.001242851 //LENGTH 7.660 LUMPCC 0.0004586006 DR + +*CONN +*I cbx_1__0_:chanx_right_out[15] O *L 0 *C 512.290 335.920 +*I sb_1__0_:chanx_left_in[15] I *L 0 *C 519.950 335.920 + +*CAP +0 cbx_1__0_:chanx_right_out[15] 0.0003921251 +1 sb_1__0_:chanx_left_in[15] 0.0003921251 +2 cbx_1__0_:chanx_right_out[15] cbx_1__0_:chanx_right_in[15] 6.915362e-05 +3 sb_1__0_:chanx_left_in[15] sb_1__0_:chanx_left_out[15] 6.915362e-05 +4 cbx_1__0_:chanx_right_out[15] cbx_1__0_:chanx_right_in[17] 0.0001601467 +5 sb_1__0_:chanx_left_in[15] sb_1__0_:chanx_left_out[17] 0.0001601467 + +*RES +0 cbx_1__0_:chanx_right_out[15] sb_1__0_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[16] 0.001235387 //LENGTH 7.660 LUMPCC 0.0004595348 DR + +*CONN +*I cbx_1__0_:chanx_right_out[16] O *L 0 *C 512.290 322.320 +*I sb_1__0_:chanx_left_in[16] I *L 0 *C 519.950 322.320 + +*CAP +0 cbx_1__0_:chanx_right_out[16] 0.0003879259 +1 sb_1__0_:chanx_left_in[16] 0.0003879259 +2 cbx_1__0_:chanx_right_out[16] cbx_1__0_:chanx_right_in[0] 0.0001600385 +3 sb_1__0_:chanx_left_in[16] sb_1__0_:chanx_left_out[0] 0.0001600385 +4 cbx_1__0_:chanx_right_out[16] cbx_1__0_:chanx_right_in[16] 6.972889e-05 +5 sb_1__0_:chanx_left_in[16] sb_1__0_:chanx_left_out[16] 6.972889e-05 + +*RES +0 cbx_1__0_:chanx_right_out[16] sb_1__0_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[17] 0.003636108 //LENGTH 31.340 LUMPCC 0.0003607137 DR + +*CONN +*I cbx_1__0_:chanx_right_out[17] O *L 0 *C 510.140 293.830 +*I sb_1__0_:chanx_left_in[17] I *L 0 *C 519.950 312.800 +*N cbx_1__0__0_chanx_right_out[17]:2 *C 517.060 312.800 +*N cbx_1__0__0_chanx_right_out[17]:3 *C 517.040 312.793 +*N cbx_1__0__0_chanx_right_out[17]:4 *C 517.040 293.088 +*N cbx_1__0__0_chanx_right_out[17]:5 *C 517.020 293.080 +*N cbx_1__0__0_chanx_right_out[17]:6 *C 510.148 293.080 +*N cbx_1__0__0_chanx_right_out[17]:7 *C 510.140 293.137 + +*CAP +0 cbx_1__0_:chanx_right_out[17] 6.382105e-05 +1 sb_1__0_:chanx_left_in[17] 0.0001287537 +2 cbx_1__0__0_chanx_right_out[17]:2 0.0001287537 +3 cbx_1__0__0_chanx_right_out[17]:3 0.001042662 +4 cbx_1__0__0_chanx_right_out[17]:4 0.001042662 +5 cbx_1__0__0_chanx_right_out[17]:5 0.0004024602 +6 cbx_1__0__0_chanx_right_out[17]:6 0.0004024602 +7 cbx_1__0__0_chanx_right_out[17]:7 6.382105e-05 +8 cbx_1__0__0_chanx_right_out[17]:6 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 4.245471e-05 +9 cbx_1__0__0_chanx_right_out[17]:5 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 4.245471e-05 +10 sb_1__0_:chanx_left_in[17] sb_1__0_:chanx_left_out[10] 6.937591e-05 +11 cbx_1__0__0_chanx_right_out[17]:2 cbx_1__0_:chanx_right_in[10] 6.937591e-05 +12 sb_1__0_:chanx_left_in[17] sb_1__0_:chanx_left_out[14] 6.852623e-05 +13 cbx_1__0__0_chanx_right_out[17]:2 cbx_1__0_:chanx_right_in[14] 6.852623e-05 + +*RES +0 cbx_1__0_:chanx_right_out[17] cbx_1__0__0_chanx_right_out[17]:7 0.0006183035 +1 cbx_1__0__0_chanx_right_out[17]:7 cbx_1__0__0_chanx_right_out[17]:6 0.00341 +2 cbx_1__0__0_chanx_right_out[17]:6 cbx_1__0__0_chanx_right_out[17]:5 0.001076692 +3 cbx_1__0__0_chanx_right_out[17]:5 cbx_1__0__0_chanx_right_out[17]:4 0.00341 +4 cbx_1__0__0_chanx_right_out[17]:4 cbx_1__0__0_chanx_right_out[17]:3 0.003087116 +5 cbx_1__0__0_chanx_right_out[17]:2 sb_1__0_:chanx_left_in[17] 0.0004527667 +6 cbx_1__0__0_chanx_right_out[17]:3 cbx_1__0__0_chanx_right_out[17]:2 0.00341 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[18] 0.001669463 //LENGTH 7.660 LUMPCC 0.001020064 DR + +*CONN +*I cbx_1__0_:chanx_right_out[18] O *L 0 *C 512.290 299.200 +*I sb_1__0_:chanx_left_in[18] I *L 0 *C 519.950 299.200 + +*CAP +0 cbx_1__0_:chanx_right_out[18] 0.0003246998 +1 sb_1__0_:chanx_left_in[18] 0.0003246997 +2 cbx_1__0_:chanx_right_out[18] cbx_1__0_:chanx_right_out[14] 6.423301e-06 +3 cbx_1__0_:chanx_right_out[18] cbx_1__0__0_chanx_right_out[14]:2 7.824093e-07 +4 cbx_1__0_:chanx_right_out[18] cbx_1__0__0_chanx_right_out[14]:4 0.0003533912 +5 sb_1__0_:chanx_left_in[18] sb_1__0_:chanx_left_in[14] 7.824093e-07 +6 sb_1__0_:chanx_left_in[18] cbx_1__0__0_chanx_right_out[14]:3 0.0003533912 +7 sb_1__0_:chanx_left_in[18] cbx_1__0__0_chanx_right_out[14]:5 6.423301e-06 +8 cbx_1__0_:chanx_right_out[18] cbx_1__0_:chanx_right_out[19] 0.000149435 +9 sb_1__0_:chanx_left_in[18] sb_1__0_:chanx_left_in[19] 0.000149435 + +*RES +0 cbx_1__0_:chanx_right_out[18] sb_1__0_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_16_[0] 0.001346125 //LENGTH 11.020 LUMPCC 0.0007131024 DR + +*CONN +*I cbx_1__0_:top_grid_pin_16_[0] O *L 0 *C 441.600 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] I *L 0 *C 441.600 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_16_[0] 0.0003165115 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 0.0003165114 +2 cbx_1__0_:top_grid_pin_16_[0] cbx_1__0_:top_grid_pin_18_[0] 0.0001452514 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] 0.0001452514 +4 cbx_1__0_:top_grid_pin_16_[0] cbx_1__0_:top_grid_pin_22_[0] 8.364983e-06 +5 cbx_1__0_:top_grid_pin_16_[0] cbx_1__0__0_top_grid_pin_22_[0]:4 0.0001557978 +6 cbx_1__0_:top_grid_pin_16_[0] cbx_1__0__0_top_grid_pin_22_[0]:2 4.713709e-05 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_22_[0] 4.713709e-05 +8 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] cbx_1__0__0_top_grid_pin_22_[0]:5 8.364983e-06 +9 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] cbx_1__0__0_top_grid_pin_22_[0]:3 0.0001557978 + +*RES +0 cbx_1__0_:top_grid_pin_16_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_17_[0] 0.001351911 //LENGTH 11.020 LUMPCC 0.00071191 DR + +*CONN +*I cbx_1__0_:top_grid_pin_17_[0] O *L 0 *C 443.440 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] I *L 0 *C 443.440 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_17_[0] 0.0003200004 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 0.0003200004 +2 cbx_1__0_:top_grid_pin_17_[0] cbx_1__0_:top_grid_pin_18_[0] 0.000143749 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] 0.000143749 +4 cbx_1__0_:top_grid_pin_17_[0] cbx_1__0_:top_grid_pin_19_[0] 8.93018e-06 +5 cbx_1__0_:top_grid_pin_17_[0] cbx_1__0__0_top_grid_pin_19_[0]:4 0.0001561387 +6 cbx_1__0_:top_grid_pin_17_[0] cbx_1__0__0_top_grid_pin_19_[0]:2 4.713708e-05 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_19_[0] 4.713708e-05 +8 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] cbx_1__0__0_top_grid_pin_19_[0]:5 8.93018e-06 +9 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] cbx_1__0__0_top_grid_pin_19_[0]:3 0.0001561387 + +*RES +0 cbx_1__0_:top_grid_pin_17_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_18_[0] 0.001252346 //LENGTH 11.020 LUMPCC 0.0005780007 DR + +*CONN +*I cbx_1__0_:top_grid_pin_18_[0] O *L 0 *C 442.520 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] I *L 0 *C 442.520 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_18_[0] 0.0003371727 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] 0.0003371727 +2 cbx_1__0_:top_grid_pin_18_[0] cbx_1__0_:top_grid_pin_16_[0] 0.0001452514 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 0.0001452514 +4 cbx_1__0_:top_grid_pin_18_[0] cbx_1__0_:top_grid_pin_17_[0] 0.000143749 +5 grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 0.000143749 + +*RES +0 cbx_1__0_:top_grid_pin_18_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_18_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_19_[0] 0.001411867 //LENGTH 12.500 LUMPCC 0.000424412 DR + +*CONN +*I cbx_1__0_:top_grid_pin_19_[0] O *L 0 *C 444.360 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_19_[0] I *L 0 *C 444.360 380.870 +*N cbx_1__0__0_top_grid_pin_19_[0]:2 *C 444.360 377.060 +*N cbx_1__0__0_top_grid_pin_19_[0]:3 *C 443.900 377.060 +*N cbx_1__0__0_top_grid_pin_19_[0]:4 *C 443.900 371.620 +*N cbx_1__0__0_top_grid_pin_19_[0]:5 *C 444.360 371.620 + +*CAP +0 cbx_1__0_:top_grid_pin_19_[0] 0.0001137019 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_19_[0] 0.0001507154 +2 cbx_1__0__0_top_grid_pin_19_[0]:2 0.0001755991 +3 cbx_1__0__0_top_grid_pin_19_[0]:3 0.000197541 +4 cbx_1__0__0_top_grid_pin_19_[0]:4 0.0002044265 +5 cbx_1__0__0_top_grid_pin_19_[0]:5 0.0001454712 +6 cbx_1__0_:top_grid_pin_19_[0] cbx_1__0_:top_grid_pin_17_[0] 8.93018e-06 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_19_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 4.713708e-05 +8 cbx_1__0__0_top_grid_pin_19_[0]:4 cbx_1__0_:top_grid_pin_17_[0] 0.0001561387 +9 cbx_1__0__0_top_grid_pin_19_[0]:5 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 8.93018e-06 +10 cbx_1__0__0_top_grid_pin_19_[0]:3 grid_clb_1__1_:bottom_width_0_height_0__pin_17_[0] 0.0001561387 +11 cbx_1__0__0_top_grid_pin_19_[0]:2 cbx_1__0_:top_grid_pin_17_[0] 4.713708e-05 + +*RES +0 cbx_1__0_:top_grid_pin_19_[0] cbx_1__0__0_top_grid_pin_19_[0]:5 0.001580357 +1 cbx_1__0__0_top_grid_pin_19_[0]:4 cbx_1__0__0_top_grid_pin_19_[0]:3 0.004857143 +2 cbx_1__0__0_top_grid_pin_19_[0]:5 cbx_1__0__0_top_grid_pin_19_[0]:4 0.0004107143 +3 cbx_1__0__0_top_grid_pin_19_[0]:3 cbx_1__0__0_top_grid_pin_19_[0]:2 0.0004107143 +4 cbx_1__0__0_top_grid_pin_19_[0]:2 grid_clb_1__1_:bottom_width_0_height_0__pin_19_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_20_[0] 0.001039339 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__0_:top_grid_pin_20_[0] O *L 0 *C 465.060 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_20_[0] I *L 0 *C 465.060 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_20_[0] 0.0005196697 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_20_[0] 0.0005196697 + +*RES +0 cbx_1__0_:top_grid_pin_20_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_20_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_21_[0] 0.001446578 //LENGTH 12.500 LUMPCC 0.0004245911 DR + +*CONN +*I cbx_1__0_:top_grid_pin_21_[0] O *L 0 *C 423.660 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_21_[0] I *L 0 *C 423.660 380.870 +*N cbx_1__0__0_top_grid_pin_21_[0]:2 *C 423.660 377.060 +*N cbx_1__0__0_top_grid_pin_21_[0]:3 *C 423.200 377.060 +*N cbx_1__0__0_top_grid_pin_21_[0]:4 *C 423.200 371.620 +*N cbx_1__0__0_top_grid_pin_21_[0]:5 *C 423.660 371.620 + +*CAP +0 cbx_1__0_:top_grid_pin_21_[0] 0.0001241022 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_21_[0] 0.0001535846 +2 cbx_1__0__0_top_grid_pin_21_[0]:2 0.0001791604 +3 cbx_1__0__0_top_grid_pin_21_[0]:3 0.0002012436 +4 cbx_1__0__0_top_grid_pin_21_[0]:4 0.000207731 +5 cbx_1__0__0_top_grid_pin_21_[0]:5 0.0001561654 +6 cbx_1__0_:top_grid_pin_21_[0] cbx_1__0_:top_grid_pin_23_[0] 8.935975e-06 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_21_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 4.713447e-05 +8 cbx_1__0__0_top_grid_pin_21_[0]:4 cbx_1__0_:top_grid_pin_23_[0] 0.0001562251 +9 cbx_1__0__0_top_grid_pin_21_[0]:5 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 8.935975e-06 +10 cbx_1__0__0_top_grid_pin_21_[0]:3 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 0.0001562251 +11 cbx_1__0__0_top_grid_pin_21_[0]:2 cbx_1__0_:top_grid_pin_23_[0] 4.713447e-05 + +*RES +0 cbx_1__0_:top_grid_pin_21_[0] cbx_1__0__0_top_grid_pin_21_[0]:5 0.001580357 +1 cbx_1__0__0_top_grid_pin_21_[0]:4 cbx_1__0__0_top_grid_pin_21_[0]:3 0.004857143 +2 cbx_1__0__0_top_grid_pin_21_[0]:5 cbx_1__0__0_top_grid_pin_21_[0]:4 0.0004107143 +3 cbx_1__0__0_top_grid_pin_21_[0]:3 cbx_1__0__0_top_grid_pin_21_[0]:2 0.0004107143 +4 cbx_1__0__0_top_grid_pin_21_[0]:2 grid_clb_1__1_:bottom_width_0_height_0__pin_21_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_22_[0] 0.001432788 //LENGTH 12.500 LUMPCC 0.0004225997 DR + +*CONN +*I cbx_1__0_:top_grid_pin_22_[0] O *L 0 *C 440.680 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_22_[0] I *L 0 *C 440.680 380.870 +*N cbx_1__0__0_top_grid_pin_22_[0]:2 *C 440.680 377.060 +*N cbx_1__0__0_top_grid_pin_22_[0]:3 *C 441.140 377.060 +*N cbx_1__0__0_top_grid_pin_22_[0]:4 *C 441.140 371.620 +*N cbx_1__0__0_top_grid_pin_22_[0]:5 *C 440.680 371.620 + +*CAP +0 cbx_1__0_:top_grid_pin_22_[0] 0.0001210323 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_22_[0] 0.000146673 +2 cbx_1__0__0_top_grid_pin_22_[0]:2 0.0001715134 +3 cbx_1__0__0_top_grid_pin_22_[0]:3 0.00020535 +4 cbx_1__0__0_top_grid_pin_22_[0]:4 0.0002125483 +5 cbx_1__0__0_top_grid_pin_22_[0]:5 0.000153071 +6 cbx_1__0_:top_grid_pin_22_[0] cbx_1__0_:top_grid_pin_16_[0] 8.364983e-06 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_22_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 4.713709e-05 +8 cbx_1__0__0_top_grid_pin_22_[0]:5 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 8.364983e-06 +9 cbx_1__0__0_top_grid_pin_22_[0]:4 cbx_1__0_:top_grid_pin_16_[0] 0.0001557978 +10 cbx_1__0__0_top_grid_pin_22_[0]:2 cbx_1__0_:top_grid_pin_16_[0] 4.713709e-05 +11 cbx_1__0__0_top_grid_pin_22_[0]:3 grid_clb_1__1_:bottom_width_0_height_0__pin_16_[0] 0.0001557978 + +*RES +0 cbx_1__0_:top_grid_pin_22_[0] cbx_1__0__0_top_grid_pin_22_[0]:5 0.001580357 +1 cbx_1__0__0_top_grid_pin_22_[0]:5 cbx_1__0__0_top_grid_pin_22_[0]:4 0.0004107143 +2 cbx_1__0__0_top_grid_pin_22_[0]:4 cbx_1__0__0_top_grid_pin_22_[0]:3 0.004857143 +3 cbx_1__0__0_top_grid_pin_22_[0]:2 grid_clb_1__1_:bottom_width_0_height_0__pin_22_[0] 0.003401786 +4 cbx_1__0__0_top_grid_pin_22_[0]:3 cbx_1__0__0_top_grid_pin_22_[0]:2 0.0004107143 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_23_[0] 0.001352712 //LENGTH 11.020 LUMPCC 0.0007151539 DR + +*CONN +*I cbx_1__0_:top_grid_pin_23_[0] O *L 0 *C 422.740 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] I *L 0 *C 422.740 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_23_[0] 0.0003187793 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 0.0003187793 +2 cbx_1__0_:top_grid_pin_23_[0] cbx_1__0_:top_grid_pin_21_[0] 8.935975e-06 +3 cbx_1__0_:top_grid_pin_23_[0] cbx_1__0__0_top_grid_pin_21_[0]:2 4.713447e-05 +4 cbx_1__0_:top_grid_pin_23_[0] cbx_1__0__0_top_grid_pin_21_[0]:4 0.0001562251 +5 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_21_[0] 4.713447e-05 +6 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] cbx_1__0__0_top_grid_pin_21_[0]:3 0.0001562251 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] cbx_1__0__0_top_grid_pin_21_[0]:5 8.935975e-06 +8 cbx_1__0_:top_grid_pin_23_[0] cbx_1__0_:top_grid_pin_27_[0] 0.0001452814 +9 grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] 0.0001452814 + +*RES +0 cbx_1__0_:top_grid_pin_23_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_24_[0] 0.001070431 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__0_:top_grid_pin_24_[0] O *L 0 *C 409.860 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_24_[0] I *L 0 *C 409.860 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_24_[0] 0.0005352154 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_24_[0] 0.0005352154 + +*RES +0 cbx_1__0_:top_grid_pin_24_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_24_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_25_[0] 0.001164522 //LENGTH 11.020 LUMPCC 0.0002903098 DR + +*CONN +*I cbx_1__0_:top_grid_pin_25_[0] O *L 0 *C 419.980 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_25_[0] I *L 0 *C 419.980 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_25_[0] 0.0004371061 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_25_[0] 0.0004371061 +2 cbx_1__0_:top_grid_pin_25_[0] cbx_1__0_:top_grid_pin_26_[0] 0.0001451549 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_25_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] 0.0001451549 + +*RES +0 cbx_1__0_:top_grid_pin_25_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_25_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_26_[0] 0.001249833 //LENGTH 11.020 LUMPCC 0.0005806196 DR + +*CONN +*I cbx_1__0_:top_grid_pin_26_[0] O *L 0 *C 420.900 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] I *L 0 *C 420.900 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_26_[0] 0.0003346069 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] 0.0003346069 +2 cbx_1__0_:top_grid_pin_26_[0] cbx_1__0_:top_grid_pin_25_[0] 0.0001451549 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_25_[0] 0.0001451549 +4 cbx_1__0_:top_grid_pin_26_[0] cbx_1__0_:top_grid_pin_27_[0] 0.0001451549 +5 grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] 0.0001451549 + +*RES +0 cbx_1__0_:top_grid_pin_26_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_27_[0] 0.001253873 //LENGTH 11.020 LUMPCC 0.0005808726 DR + +*CONN +*I cbx_1__0_:top_grid_pin_27_[0] O *L 0 *C 421.820 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] I *L 0 *C 421.820 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_27_[0] 0.0003365004 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] 0.0003365004 +2 cbx_1__0_:top_grid_pin_27_[0] cbx_1__0_:top_grid_pin_23_[0] 0.0001452814 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_23_[0] 0.0001452814 +4 cbx_1__0_:top_grid_pin_27_[0] cbx_1__0_:top_grid_pin_26_[0] 0.0001451549 +5 grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_26_[0] 0.0001451549 + +*RES +0 cbx_1__0_:top_grid_pin_27_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_27_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_28_[0] 0.00115233 //LENGTH 11.020 LUMPCC 0.0002990605 DR + +*CONN +*I cbx_1__0_:top_grid_pin_28_[0] O *L 0 *C 481.160 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_28_[0] I *L 0 *C 481.160 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_28_[0] 0.0004266347 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_28_[0] 0.0004266347 +2 cbx_1__0_:top_grid_pin_28_[0] cbx_1__0_:top_grid_pin_29_[0] 0.0001495303 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_28_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] 0.0001495303 + +*RES +0 cbx_1__0_:top_grid_pin_28_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_28_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_29_[0] 0.001235625 //LENGTH 11.020 LUMPCC 0.000598121 DR + +*CONN +*I cbx_1__0_:top_grid_pin_29_[0] O *L 0 *C 482.080 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] I *L 0 *C 482.080 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_29_[0] 0.0003187521 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] 0.0003187521 +2 cbx_1__0_:top_grid_pin_29_[0] cbx_1__0_:top_grid_pin_28_[0] 0.0001495303 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_28_[0] 0.0001495303 +4 cbx_1__0_:top_grid_pin_29_[0] cbx_1__0_:top_grid_pin_31_[0] 0.0001495303 +5 grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 0.0001495303 + +*RES +0 cbx_1__0_:top_grid_pin_29_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_30_[0] 0.001419898 //LENGTH 12.500 LUMPCC 0.000431562 DR + +*CONN +*I cbx_1__0_:top_grid_pin_30_[0] O *L 0 *C 483.920 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_30_[0] I *L 0 *C 483.920 380.870 +*N cbx_1__0__0_top_grid_pin_30_[0]:2 *C 483.920 377.060 +*N cbx_1__0__0_top_grid_pin_30_[0]:3 *C 483.460 377.060 +*N cbx_1__0__0_top_grid_pin_30_[0]:4 *C 483.460 371.620 +*N cbx_1__0__0_top_grid_pin_30_[0]:5 *C 483.920 371.620 + +*CAP +0 cbx_1__0_:top_grid_pin_30_[0] 0.0001097894 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_30_[0] 0.0001509785 +2 cbx_1__0__0_top_grid_pin_30_[0]:2 0.0001764076 +3 cbx_1__0__0_top_grid_pin_30_[0]:3 0.00020159 +4 cbx_1__0__0_top_grid_pin_30_[0]:4 0.0002079708 +5 cbx_1__0__0_top_grid_pin_30_[0]:5 0.0001415994 +6 cbx_1__0_:top_grid_pin_30_[0] cbx_1__0_:top_grid_pin_31_[0] 1.284918e-05 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_30_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 4.714103e-05 +8 cbx_1__0__0_top_grid_pin_30_[0]:4 cbx_1__0_:top_grid_pin_31_[0] 0.0001557908 +9 cbx_1__0__0_top_grid_pin_30_[0]:5 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 1.284918e-05 +10 cbx_1__0__0_top_grid_pin_30_[0]:3 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 0.0001557908 +11 cbx_1__0__0_top_grid_pin_30_[0]:2 cbx_1__0_:top_grid_pin_31_[0] 4.714103e-05 + +*RES +0 cbx_1__0_:top_grid_pin_30_[0] cbx_1__0__0_top_grid_pin_30_[0]:5 0.001580357 +1 cbx_1__0__0_top_grid_pin_30_[0]:4 cbx_1__0__0_top_grid_pin_30_[0]:3 0.004857143 +2 cbx_1__0__0_top_grid_pin_30_[0]:5 cbx_1__0__0_top_grid_pin_30_[0]:4 0.0004107143 +3 cbx_1__0__0_top_grid_pin_30_[0]:3 cbx_1__0__0_top_grid_pin_30_[0]:2 0.0004107143 +4 cbx_1__0__0_top_grid_pin_30_[0]:2 grid_clb_1__1_:bottom_width_0_height_0__pin_30_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__0_top_grid_pin_31_[0] 0.00133549 //LENGTH 11.020 LUMPCC 0.0007306225 DR + +*CONN +*I cbx_1__0_:top_grid_pin_31_[0] O *L 0 *C 483.000 369.850 +*I grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] I *L 0 *C 483.000 380.870 + +*CAP +0 cbx_1__0_:top_grid_pin_31_[0] 0.0003024339 +1 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 0.0003024339 +2 cbx_1__0_:top_grid_pin_31_[0] cbx_1__0_:top_grid_pin_29_[0] 0.0001495303 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_29_[0] 0.0001495303 +4 cbx_1__0_:top_grid_pin_31_[0] cbx_1__0_:top_grid_pin_30_[0] 1.284918e-05 +5 cbx_1__0_:top_grid_pin_31_[0] cbx_1__0__0_top_grid_pin_30_[0]:2 4.714103e-05 +6 cbx_1__0_:top_grid_pin_31_[0] cbx_1__0__0_top_grid_pin_30_[0]:4 0.0001557908 +7 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_30_[0] 4.714103e-05 +8 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] cbx_1__0__0_top_grid_pin_30_[0]:3 0.0001557908 +9 grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] cbx_1__0__0_top_grid_pin_30_[0]:5 1.284918e-05 + +*RES +0 cbx_1__0_:top_grid_pin_31_[0] grid_clb_1__1_:bottom_width_0_height_0__pin_31_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_bottom_grid_pin_0_[0] 0.00111169 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__0_:bottom_grid_pin_0_[0] O *L 0 *C 766.360 293.830 +*I grid_io_bottom_2__0_:top_width_0_height_0__pin_0_[0] I *L 0 *C 766.360 282.810 + +*CAP +0 cbx_2__0_:bottom_grid_pin_0_[0] 0.0005558448 +1 grid_io_bottom_2__0_:top_width_0_height_0__pin_0_[0] 0.0005558448 + +*RES +0 cbx_2__0_:bottom_grid_pin_0_[0] grid_io_bottom_2__0_:top_width_0_height_0__pin_0_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_ccff_tail[0] 0.00114036 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__0_:ccff_tail[0] O *L 0 *C 726.340 293.830 +*I grid_io_bottom_2__0_:ccff_head[0] I *L 0 *C 726.340 282.810 + +*CAP +0 cbx_2__0_:ccff_tail[0] 0.0005701801 +1 grid_io_bottom_2__0_:ccff_head[0] 0.0005701801 + +*RES +0 cbx_2__0_:ccff_tail[0] grid_io_bottom_2__0_:ccff_head[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[0] 0.001504307 //LENGTH 7.660 LUMPCC 0.000492598 DR + +*CONN +*I cbx_2__0_:chanx_left_out[0] O *L 0 *C 668.990 340.000 +*I sb_1__0_:chanx_right_in[0] I *L 0 *C 661.330 340.000 +*N cbx_1__0__1_chanx_left_out[0]:2 *C 667.519 340.000 +*N cbx_1__0__1_chanx_left_out[0]:3 *C 667.520 340.000 + +*CAP +0 cbx_2__0_:chanx_left_out[0] 0.0002176217 +1 sb_1__0_:chanx_right_in[0] 0.0002882328 +2 cbx_1__0__1_chanx_left_out[0]:2 0.0002882328 +3 cbx_1__0__1_chanx_left_out[0]:3 0.0002176217 +4 cbx_2__0_:chanx_left_out[0] cbx_2__0_:chanx_left_out[7] 1.643599e-06 +5 sb_1__0_:chanx_right_in[0] sb_1__0_:chanx_right_in[7] 0.0001250896 +6 cbx_1__0__1_chanx_left_out[0]:3 cbx_1__0__1_chanx_left_out[7]:3 1.643599e-06 +7 cbx_1__0__1_chanx_left_out[0]:2 cbx_1__0__1_chanx_left_out[7]:2 0.0001250896 +8 sb_1__0_:chanx_right_in[0] sb_1__0_:chanx_right_in[13] 0.0001195658 +9 cbx_1__0__1_chanx_left_out[0]:2 cbx_1__0__1_chanx_left_out[13]:2 0.0001195658 + +*RES +0 cbx_2__0_:chanx_left_out[0] cbx_1__0__1_chanx_left_out[0]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[0]:3 cbx_1__0__1_chanx_left_out[0]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[0]:2 sb_1__0_:chanx_right_in[0] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[1] 0.003660654 //LENGTH 28.620 LUMPCC 0.0002359815 DR + +*CONN +*I cbx_2__0_:chanx_left_out[1] O *L 0 *C 671.140 293.830 +*I sb_1__0_:chanx_right_in[1] I *L 0 *C 661.330 310.080 +*N cbx_1__0__1_chanx_left_out[1]:2 *C 665.140 310.080 +*N cbx_1__0__1_chanx_left_out[1]:3 *C 665.160 310.072 +*N cbx_1__0__1_chanx_left_out[1]:4 *C 665.160 293.088 +*N cbx_1__0__1_chanx_left_out[1]:5 *C 665.180 293.080 +*N cbx_1__0__1_chanx_left_out[1]:6 *C 667.519 293.080 +*N cbx_1__0__1_chanx_left_out[1]:7 *C 667.520 293.080 +*N cbx_1__0__1_chanx_left_out[1]:8 *C 671.133 293.080 +*N cbx_1__0__1_chanx_left_out[1]:9 *C 671.140 293.137 + +*CAP +0 cbx_2__0_:chanx_left_out[1] 6.226464e-05 +1 sb_1__0_:chanx_right_in[1] 0.0002760084 +2 cbx_1__0__1_chanx_left_out[1]:2 0.0002760084 +3 cbx_1__0__1_chanx_left_out[1]:3 0.0009241771 +4 cbx_1__0__1_chanx_left_out[1]:4 0.0009241771 +5 cbx_1__0__1_chanx_left_out[1]:5 0.0001196998 +6 cbx_1__0__1_chanx_left_out[1]:6 0.0001196998 +7 cbx_1__0__1_chanx_left_out[1]:7 0.0003301865 +8 cbx_1__0__1_chanx_left_out[1]:8 0.0003301865 +9 cbx_1__0__1_chanx_left_out[1]:9 6.226464e-05 +10 sb_1__0_:chanx_right_in[1] sb_1__0_:chanx_right_in[8] 5.723669e-05 +11 cbx_1__0__1_chanx_left_out[1]:2 cbx_1__0__1_chanx_left_out[8]:2 5.723669e-05 +12 sb_1__0_:chanx_right_in[1] sb_1__0_:chanx_right_in[14] 6.075404e-05 +13 cbx_1__0__1_chanx_left_out[1]:2 cbx_1__0__1_chanx_left_out[14]:2 6.075404e-05 + +*RES +0 cbx_2__0_:chanx_left_out[1] cbx_1__0__1_chanx_left_out[1]:9 0.0006183035 +1 cbx_1__0__1_chanx_left_out[1]:9 cbx_1__0__1_chanx_left_out[1]:8 0.00341 +2 cbx_1__0__1_chanx_left_out[1]:8 cbx_1__0__1_chanx_left_out[1]:7 0.0005659584 +3 cbx_1__0__1_chanx_left_out[1]:5 cbx_1__0__1_chanx_left_out[1]:4 0.00341 +4 cbx_1__0__1_chanx_left_out[1]:4 cbx_1__0__1_chanx_left_out[1]:3 0.002660983 +5 cbx_1__0__1_chanx_left_out[1]:2 sb_1__0_:chanx_right_in[1] 0.0005968999 +6 cbx_1__0__1_chanx_left_out[1]:3 cbx_1__0__1_chanx_left_out[1]:2 0.00341 +7 cbx_1__0__1_chanx_left_out[1]:7 cbx_1__0__1_chanx_left_out[1]:6 1e-05 +8 cbx_1__0__1_chanx_left_out[1]:6 cbx_1__0__1_chanx_left_out[1]:5 0.0003664433 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[2] 0.001376307 //LENGTH 7.660 LUMPCC 0.0003574693 DR + +*CONN +*I cbx_2__0_:chanx_left_out[2] O *L 0 *C 668.990 306.000 +*I sb_1__0_:chanx_right_in[2] I *L 0 *C 661.330 306.000 +*N cbx_1__0__1_chanx_left_out[2]:2 *C 667.519 306.000 +*N cbx_1__0__1_chanx_left_out[2]:3 *C 667.520 306.000 + +*CAP +0 cbx_2__0_:chanx_left_out[2] 0.0001892661 +1 sb_1__0_:chanx_right_in[2] 0.0003201526 +2 cbx_1__0__1_chanx_left_out[2]:2 0.0003201526 +3 cbx_1__0__1_chanx_left_out[2]:3 0.0001892661 +4 cbx_2__0_:chanx_left_out[2] cbx_2__0_:chanx_left_out[4] 6.576453e-06 +5 sb_1__0_:chanx_right_in[2] sb_1__0_:chanx_right_in[4] 0.0001201509 +6 cbx_1__0__1_chanx_left_out[2]:3 cbx_1__0__1_chanx_left_out[4]:3 6.576453e-06 +7 cbx_1__0__1_chanx_left_out[2]:2 cbx_1__0__1_chanx_left_out[4]:2 0.0001201509 +8 sb_1__0_:chanx_right_in[2] sb_1__0_:chanx_right_in[5] 5.20073e-05 +9 cbx_1__0__1_chanx_left_out[2]:2 cbx_1__0__1_chanx_left_out[5]:2 5.20073e-05 + +*RES +0 cbx_2__0_:chanx_left_out[2] cbx_1__0__1_chanx_left_out[2]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[2]:3 cbx_1__0__1_chanx_left_out[2]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[2]:2 sb_1__0_:chanx_right_in[2] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[3] 0.001541661 //LENGTH 7.660 LUMPCC 0.0004529821 DR + +*CONN +*I cbx_2__0_:chanx_left_out[3] O *L 0 *C 668.990 301.920 +*I sb_1__0_:chanx_right_in[3] I *L 0 *C 661.330 301.920 +*N cbx_1__0__1_chanx_left_out[3]:2 *C 667.519 301.920 +*N cbx_1__0__1_chanx_left_out[3]:3 *C 667.520 301.920 + +*CAP +0 cbx_2__0_:chanx_left_out[3] 0.0002176477 +1 sb_1__0_:chanx_right_in[3] 0.0003266918 +2 cbx_1__0__1_chanx_left_out[3]:2 0.0003266918 +3 cbx_1__0__1_chanx_left_out[3]:3 0.0002176477 +4 cbx_2__0_:chanx_left_out[3] cbx_2__0_:chanx_left_out[5] 1.644113e-06 +5 sb_1__0_:chanx_right_in[3] sb_1__0_:chanx_right_in[5] 0.0001151864 +6 cbx_1__0__1_chanx_left_out[3]:3 cbx_1__0__1_chanx_left_out[5]:3 1.644113e-06 +7 cbx_1__0__1_chanx_left_out[3]:2 cbx_1__0__1_chanx_left_out[5]:2 0.0001151864 +8 sb_1__0_:chanx_right_in[3] sb_1__0_:chanx_right_out[2] 0.0001096605 +9 cbx_1__0__1_chanx_left_out[3]:2 sb_1__0__0_chanx_right_out[2]:3 0.0001096605 + +*RES +0 cbx_2__0_:chanx_left_out[3] cbx_1__0__1_chanx_left_out[3]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[3]:3 cbx_1__0__1_chanx_left_out[3]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[3]:2 sb_1__0_:chanx_right_in[3] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[4] 0.001493437 //LENGTH 7.660 LUMPCC 0.0004778926 DR + +*CONN +*I cbx_2__0_:chanx_left_out[4] O *L 0 *C 668.990 307.360 +*I sb_1__0_:chanx_right_in[4] I *L 0 *C 661.330 307.360 +*N cbx_1__0__1_chanx_left_out[4]:2 *C 667.519 307.360 +*N cbx_1__0__1_chanx_left_out[4]:3 *C 667.520 307.360 + +*CAP +0 cbx_2__0_:chanx_left_out[4] 0.0002006711 +1 sb_1__0_:chanx_right_in[4] 0.0003071009 +2 cbx_1__0__1_chanx_left_out[4]:2 0.0003071009 +3 cbx_1__0__1_chanx_left_out[4]:3 0.0002006711 +4 cbx_2__0_:chanx_left_out[4] cbx_2__0_:chanx_left_out[2] 6.576453e-06 +5 sb_1__0_:chanx_right_in[4] sb_1__0_:chanx_right_in[2] 0.0001201509 +6 cbx_1__0__1_chanx_left_out[4]:3 cbx_1__0__1_chanx_left_out[2]:3 6.576453e-06 +7 cbx_1__0__1_chanx_left_out[4]:2 cbx_1__0__1_chanx_left_out[2]:2 0.0001201509 +8 sb_1__0_:chanx_right_in[4] sb_1__0_:chanx_right_in[8] 0.0001122189 +9 cbx_1__0__1_chanx_left_out[4]:2 cbx_1__0__1_chanx_left_out[8]:2 0.0001122189 + +*RES +0 cbx_2__0_:chanx_left_out[4] cbx_1__0__1_chanx_left_out[4]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[4]:3 cbx_1__0__1_chanx_left_out[4]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[4]:2 sb_1__0_:chanx_right_in[4] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[5] 0.001369403 //LENGTH 7.660 LUMPCC 0.0003376757 DR + +*CONN +*I cbx_2__0_:chanx_left_out[5] O *L 0 *C 668.990 303.280 +*I sb_1__0_:chanx_right_in[5] I *L 0 *C 661.330 303.280 +*N cbx_1__0__1_chanx_left_out[5]:2 *C 667.519 303.280 +*N cbx_1__0__1_chanx_left_out[5]:3 *C 667.520 303.280 + +*CAP +0 cbx_2__0_:chanx_left_out[5] 0.0002047488 +1 sb_1__0_:chanx_right_in[5] 0.0003111149 +2 cbx_1__0__1_chanx_left_out[5]:2 0.0003111149 +3 cbx_1__0__1_chanx_left_out[5]:3 0.0002047488 +4 sb_1__0_:chanx_right_in[5] sb_1__0_:chanx_right_in[2] 5.20073e-05 +5 cbx_1__0__1_chanx_left_out[5]:2 cbx_1__0__1_chanx_left_out[2]:2 5.20073e-05 +6 cbx_2__0_:chanx_left_out[5] cbx_2__0_:chanx_left_out[3] 1.644113e-06 +7 sb_1__0_:chanx_right_in[5] sb_1__0_:chanx_right_in[3] 0.0001151864 +8 cbx_1__0__1_chanx_left_out[5]:3 cbx_1__0__1_chanx_left_out[3]:3 1.644113e-06 +9 cbx_1__0__1_chanx_left_out[5]:2 cbx_1__0__1_chanx_left_out[3]:2 0.0001151864 + +*RES +0 cbx_2__0_:chanx_left_out[5] cbx_1__0__1_chanx_left_out[5]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[5]:3 cbx_1__0__1_chanx_left_out[5]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[5]:2 sb_1__0_:chanx_right_in[5] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[6] 0.001335639 //LENGTH 7.660 LUMPCC 0.0004135853 DR + +*CONN +*I cbx_2__0_:chanx_left_out[6] O *L 0 *C 668.990 325.040 +*I sb_1__0_:chanx_right_in[6] I *L 0 *C 661.330 325.040 +*N cbx_1__0__1_chanx_left_out[6]:2 *C 667.519 325.040 +*N cbx_1__0__1_chanx_left_out[6]:3 *C 667.520 325.040 + +*CAP +0 cbx_2__0_:chanx_left_out[6] 0.0001871056 +1 sb_1__0_:chanx_right_in[6] 0.0002739214 +2 cbx_1__0__1_chanx_left_out[6]:2 0.0002739214 +3 cbx_1__0__1_chanx_left_out[6]:3 0.0001871056 +4 cbx_2__0_:chanx_left_out[6] cbx_2__0_:chanx_left_out[11] 9.866816e-06 +5 sb_1__0_:chanx_right_in[6] sb_1__0_:chanx_right_in[11] 0.0001342492 +6 cbx_1__0__1_chanx_left_out[6]:3 cbx_1__0__1_chanx_left_out[11]:3 9.866816e-06 +7 cbx_1__0__1_chanx_left_out[6]:2 cbx_1__0__1_chanx_left_out[11]:2 0.0001342492 +8 sb_1__0_:chanx_right_in[6] sb_1__0_:chanx_right_out[8] 6.267661e-05 +9 cbx_1__0__1_chanx_left_out[6]:2 sb_1__0__0_chanx_right_out[8]:3 6.267661e-05 + +*RES +0 cbx_2__0_:chanx_left_out[6] cbx_1__0__1_chanx_left_out[6]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[6]:3 cbx_1__0__1_chanx_left_out[6]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[6]:2 sb_1__0_:chanx_right_in[6] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[7] 0.001323503 //LENGTH 7.660 LUMPCC 0.000382576 DR + +*CONN +*I cbx_2__0_:chanx_left_out[7] O *L 0 *C 668.990 341.360 +*I sb_1__0_:chanx_right_in[7] I *L 0 *C 661.330 341.360 +*N cbx_1__0__1_chanx_left_out[7]:2 *C 667.519 341.360 +*N cbx_1__0__1_chanx_left_out[7]:3 *C 667.520 341.360 + +*CAP +0 cbx_2__0_:chanx_left_out[7] 0.0002070988 +1 sb_1__0_:chanx_right_in[7] 0.0002633648 +2 cbx_1__0__1_chanx_left_out[7]:2 0.0002633648 +3 cbx_1__0__1_chanx_left_out[7]:3 0.0002070988 +4 cbx_2__0_:chanx_left_out[7] cbx_2__0_:chanx_left_out[0] 1.643599e-06 +5 sb_1__0_:chanx_right_in[7] sb_1__0_:chanx_right_in[0] 0.0001250896 +6 cbx_1__0__1_chanx_left_out[7]:3 cbx_1__0__1_chanx_left_out[0]:3 1.643599e-06 +7 cbx_1__0__1_chanx_left_out[7]:2 cbx_1__0__1_chanx_left_out[0]:2 0.0001250896 +8 sb_1__0_:chanx_right_in[7] sb_1__0_:chanx_right_in[18] 6.455478e-05 +9 cbx_1__0__1_chanx_left_out[7]:2 cbx_1__0__1_chanx_left_out[18]:2 6.455478e-05 + +*RES +0 cbx_2__0_:chanx_left_out[7] cbx_1__0__1_chanx_left_out[7]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[7]:3 cbx_1__0__1_chanx_left_out[7]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[7]:2 sb_1__0_:chanx_right_in[7] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[8] 0.001515405 //LENGTH 7.660 LUMPCC 0.0003389112 DR + +*CONN +*I cbx_2__0_:chanx_left_out[8] O *L 0 *C 668.990 308.720 +*I sb_1__0_:chanx_right_in[8] I *L 0 *C 661.330 308.720 +*N cbx_1__0__1_chanx_left_out[8]:2 *C 667.519 308.720 +*N cbx_1__0__1_chanx_left_out[8]:3 *C 667.520 308.720 + +*CAP +0 cbx_2__0_:chanx_left_out[8] 0.0002198903 +1 sb_1__0_:chanx_right_in[8] 0.0003683564 +2 cbx_1__0__1_chanx_left_out[8]:2 0.0003683564 +3 cbx_1__0__1_chanx_left_out[8]:3 0.0002198903 +4 sb_1__0_:chanx_right_in[8] sb_1__0_:chanx_right_in[1] 5.723669e-05 +5 cbx_1__0__1_chanx_left_out[8]:2 cbx_1__0__1_chanx_left_out[1]:2 5.723669e-05 +6 sb_1__0_:chanx_right_in[8] sb_1__0_:chanx_right_in[4] 0.0001122189 +7 cbx_1__0__1_chanx_left_out[8]:2 cbx_1__0__1_chanx_left_out[4]:2 0.0001122189 + +*RES +0 cbx_2__0_:chanx_left_out[8] cbx_1__0__1_chanx_left_out[8]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[8]:3 cbx_1__0__1_chanx_left_out[8]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[8]:2 sb_1__0_:chanx_right_in[8] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[9] 0.001330119 //LENGTH 7.660 LUMPCC 0.0001228341 DR + +*CONN +*I cbx_2__0_:chanx_left_out[9] O *L 0 *C 668.990 365.840 +*I sb_1__0_:chanx_right_in[9] I *L 0 *C 661.330 365.840 +*N cbx_1__0__1_chanx_left_out[9]:2 *C 667.519 365.840 +*N cbx_1__0__1_chanx_left_out[9]:3 *C 667.520 365.840 + +*CAP +0 cbx_2__0_:chanx_left_out[9] 0.000220624 +1 sb_1__0_:chanx_right_in[9] 0.0003830185 +2 cbx_1__0__1_chanx_left_out[9]:2 0.0003830185 +3 cbx_1__0__1_chanx_left_out[9]:3 0.000220624 +4 sb_1__0_:chanx_right_in[9] sb_1__0_:chanx_right_out[12] 6.141703e-05 +5 cbx_1__0__1_chanx_left_out[9]:2 sb_1__0__0_chanx_right_out[12]:3 6.141703e-05 + +*RES +0 cbx_2__0_:chanx_left_out[9] cbx_1__0__1_chanx_left_out[9]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[9]:3 cbx_1__0__1_chanx_left_out[9]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[9]:2 sb_1__0_:chanx_right_in[9] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[10] 0.001431729 //LENGTH 7.660 LUMPCC 0.0003649245 DR + +*CONN +*I cbx_2__0_:chanx_left_out[10] O *L 0 *C 668.990 319.600 +*I sb_1__0_:chanx_right_in[10] I *L 0 *C 661.330 319.600 +*N cbx_1__0__1_chanx_left_out[10]:2 *C 667.519 319.600 +*N cbx_1__0__1_chanx_left_out[10]:3 *C 667.520 319.600 + +*CAP +0 cbx_2__0_:chanx_left_out[10] 0.0002200254 +1 sb_1__0_:chanx_right_in[10] 0.0003133768 +2 cbx_1__0__1_chanx_left_out[10]:2 0.0003133768 +3 cbx_1__0__1_chanx_left_out[10]:3 0.0002200254 +4 sb_1__0_:chanx_right_in[10] sb_1__0_:chanx_right_out[6] 6.280022e-05 +5 cbx_1__0__1_chanx_left_out[10]:2 sb_1__0__0_chanx_right_out[6]:3 6.280022e-05 +6 sb_1__0_:chanx_right_in[10] sb_1__0_:chanx_right_out[10] 0.000119662 +7 cbx_1__0__1_chanx_left_out[10]:2 sb_1__0__0_chanx_right_out[10]:3 0.000119662 + +*RES +0 cbx_2__0_:chanx_left_out[10] cbx_1__0__1_chanx_left_out[10]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[10]:3 cbx_1__0__1_chanx_left_out[10]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[10]:2 sb_1__0_:chanx_right_in[10] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[11] 0.001403378 //LENGTH 7.660 LUMPCC 0.0005767465 DR + +*CONN +*I cbx_2__0_:chanx_left_out[11] O *L 0 *C 668.990 323.680 +*I sb_1__0_:chanx_right_in[11] I *L 0 *C 661.330 323.680 +*N cbx_1__0__1_chanx_left_out[11]:2 *C 667.519 323.680 +*N cbx_1__0__1_chanx_left_out[11]:3 *C 667.520 323.680 + +*CAP +0 cbx_2__0_:chanx_left_out[11] 0.0001747544 +1 sb_1__0_:chanx_right_in[11] 0.0002385611 +2 cbx_1__0__1_chanx_left_out[11]:2 0.0002385611 +3 cbx_1__0__1_chanx_left_out[11]:3 0.0001747544 +4 cbx_2__0_:chanx_left_out[11] cbx_2__0_:chanx_left_out[6] 9.866816e-06 +5 sb_1__0_:chanx_right_in[11] sb_1__0_:chanx_right_in[6] 0.0001342492 +6 cbx_1__0__1_chanx_left_out[11]:3 cbx_1__0__1_chanx_left_out[6]:3 9.866816e-06 +7 cbx_1__0__1_chanx_left_out[11]:2 cbx_1__0__1_chanx_left_out[6]:2 0.0001342492 +8 cbx_2__0_:chanx_left_out[11] cbx_2__0_:chanx_left_in[6] 9.863077e-06 +9 sb_1__0_:chanx_right_in[11] sb_1__0_:chanx_right_out[6] 0.0001343942 +10 cbx_1__0__1_chanx_left_out[11]:3 sb_1__0__0_chanx_right_out[6]:2 9.863077e-06 +11 cbx_1__0__1_chanx_left_out[11]:2 sb_1__0__0_chanx_right_out[6]:3 0.0001343942 + +*RES +0 cbx_2__0_:chanx_left_out[11] cbx_1__0__1_chanx_left_out[11]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[11]:3 cbx_1__0__1_chanx_left_out[11]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[11]:2 sb_1__0_:chanx_right_in[11] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[12] 0.001465705 //LENGTH 7.660 LUMPCC 0.0005304179 DR + +*CONN +*I cbx_2__0_:chanx_left_out[12] O *L 0 *C 668.990 312.800 +*I sb_1__0_:chanx_right_in[12] I *L 0 *C 661.330 312.800 +*N cbx_1__0__1_chanx_left_out[12]:2 *C 667.519 312.800 +*N cbx_1__0__1_chanx_left_out[12]:3 *C 667.520 312.800 + +*CAP +0 cbx_2__0_:chanx_left_out[12] 0.0001949588 +1 sb_1__0_:chanx_right_in[12] 0.0002726849 +2 cbx_1__0__1_chanx_left_out[12]:2 0.0002726849 +3 cbx_1__0__1_chanx_left_out[12]:3 0.0001949588 +4 cbx_2__0_:chanx_left_out[12] cbx_2__0_:chanx_left_out[14] 1.643549e-06 +5 sb_1__0_:chanx_right_in[12] sb_1__0_:chanx_right_in[14] 0.0001221465 +6 cbx_1__0__1_chanx_left_out[12]:3 cbx_1__0__1_chanx_left_out[14]:3 1.643549e-06 +7 cbx_1__0__1_chanx_left_out[12]:2 cbx_1__0__1_chanx_left_out[14]:2 0.0001221465 +8 cbx_2__0_:chanx_left_out[12] cbx_2__0_:chanx_left_in[18] 9.861294e-06 +9 sb_1__0_:chanx_right_in[12] sb_1__0_:chanx_right_out[18] 0.0001315576 +10 cbx_1__0__1_chanx_left_out[12]:3 sb_1__0__0_chanx_right_out[18]:2 9.861294e-06 +11 cbx_1__0__1_chanx_left_out[12]:2 sb_1__0__0_chanx_right_out[18]:3 0.0001315576 + +*RES +0 cbx_2__0_:chanx_left_out[12] cbx_1__0__1_chanx_left_out[12]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[12]:3 cbx_1__0__1_chanx_left_out[12]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[12]:2 sb_1__0_:chanx_right_in[12] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[13] 0.001432186 //LENGTH 7.660 LUMPCC 0.0003624339 DR + +*CONN +*I cbx_2__0_:chanx_left_out[13] O *L 0 *C 668.990 338.640 +*I sb_1__0_:chanx_right_in[13] I *L 0 *C 661.330 338.640 +*N cbx_1__0__1_chanx_left_out[13]:2 *C 667.519 338.640 +*N cbx_1__0__1_chanx_left_out[13]:3 *C 667.520 338.640 + +*CAP +0 cbx_2__0_:chanx_left_out[13] 0.0002200131 +1 sb_1__0_:chanx_right_in[13] 0.000314863 +2 cbx_1__0__1_chanx_left_out[13]:2 0.000314863 +3 cbx_1__0__1_chanx_left_out[13]:3 0.0002200131 +4 sb_1__0_:chanx_right_in[13] sb_1__0_:chanx_right_in[0] 0.0001195658 +5 cbx_1__0__1_chanx_left_out[13]:2 cbx_1__0__1_chanx_left_out[0]:2 0.0001195658 +6 sb_1__0_:chanx_right_in[13] sb_1__0_:chanx_right_in[15] 6.165115e-05 +7 cbx_1__0__1_chanx_left_out[13]:2 cbx_1__0__1_chanx_left_out[15]:2 6.165115e-05 + +*RES +0 cbx_2__0_:chanx_left_out[13] cbx_1__0__1_chanx_left_out[13]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[13]:3 cbx_1__0__1_chanx_left_out[13]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[13]:2 sb_1__0_:chanx_right_in[13] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[14] 0.001491786 //LENGTH 7.660 LUMPCC 0.0003690882 DR + +*CONN +*I cbx_2__0_:chanx_left_out[14] O *L 0 *C 668.990 311.440 +*I sb_1__0_:chanx_right_in[14] I *L 0 *C 661.330 311.440 +*N cbx_1__0__1_chanx_left_out[14]:2 *C 667.519 311.440 +*N cbx_1__0__1_chanx_left_out[14]:3 *C 667.520 311.440 + +*CAP +0 cbx_2__0_:chanx_left_out[14] 0.000218485 +1 sb_1__0_:chanx_right_in[14] 0.0003428637 +2 cbx_1__0__1_chanx_left_out[14]:2 0.0003428637 +3 cbx_1__0__1_chanx_left_out[14]:3 0.000218485 +4 sb_1__0_:chanx_right_in[14] sb_1__0_:chanx_right_in[1] 6.075404e-05 +5 cbx_1__0__1_chanx_left_out[14]:2 cbx_1__0__1_chanx_left_out[1]:2 6.075404e-05 +6 cbx_2__0_:chanx_left_out[14] cbx_2__0_:chanx_left_out[12] 1.643549e-06 +7 sb_1__0_:chanx_right_in[14] sb_1__0_:chanx_right_in[12] 0.0001221465 +8 cbx_1__0__1_chanx_left_out[14]:3 cbx_1__0__1_chanx_left_out[12]:3 1.643549e-06 +9 cbx_1__0__1_chanx_left_out[14]:2 cbx_1__0__1_chanx_left_out[12]:2 0.0001221465 + +*RES +0 cbx_2__0_:chanx_left_out[14] cbx_1__0__1_chanx_left_out[14]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[14]:3 cbx_1__0__1_chanx_left_out[14]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[14]:2 sb_1__0_:chanx_right_in[14] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[15] 0.001385048 //LENGTH 7.660 LUMPCC 0.0003955947 DR + +*CONN +*I cbx_2__0_:chanx_left_out[15] O *L 0 *C 668.990 335.920 +*I sb_1__0_:chanx_right_in[15] I *L 0 *C 661.330 335.920 +*N cbx_1__0__1_chanx_left_out[15]:2 *C 667.519 335.920 +*N cbx_1__0__1_chanx_left_out[15]:3 *C 667.520 335.920 + +*CAP +0 cbx_2__0_:chanx_left_out[15] 0.0002006812 +1 sb_1__0_:chanx_right_in[15] 0.0002940457 +2 cbx_1__0__1_chanx_left_out[15]:2 0.0002940457 +3 cbx_1__0__1_chanx_left_out[15]:3 0.0002006812 +4 sb_1__0_:chanx_right_in[15] sb_1__0_:chanx_right_in[13] 6.165115e-05 +5 cbx_1__0__1_chanx_left_out[15]:2 cbx_1__0__1_chanx_left_out[13]:2 6.165115e-05 +6 cbx_2__0_:chanx_left_out[15] cbx_2__0_:chanx_left_in[9] 6.577123e-06 +7 sb_1__0_:chanx_right_in[15] sb_1__0_:chanx_right_out[9] 0.0001295691 +8 cbx_1__0__1_chanx_left_out[15]:3 sb_1__0__0_chanx_right_out[9]:2 6.577123e-06 +9 cbx_1__0__1_chanx_left_out[15]:2 sb_1__0__0_chanx_right_out[9]:3 0.0001295691 + +*RES +0 cbx_2__0_:chanx_left_out[15] cbx_1__0__1_chanx_left_out[15]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[15]:3 cbx_1__0__1_chanx_left_out[15]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[15]:2 sb_1__0_:chanx_right_in[15] 0.00096961 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[16] 0.001351434 //LENGTH 7.660 LUMPCC 0.0001027444 DR + +*CONN +*I cbx_2__0_:chanx_left_out[16] O *L 0 *C 668.990 297.840 +*I sb_1__0_:chanx_right_in[16] I *L 0 *C 661.330 297.840 +*N cbx_1__0__1_chanx_left_out[16]:2 *C 667.519 297.840 +*N cbx_1__0__1_chanx_left_out[16]:3 *C 667.520 297.840 + +*CAP +0 cbx_2__0_:chanx_left_out[16] 0.0002101583 +1 sb_1__0_:chanx_right_in[16] 0.0004141866 +2 cbx_1__0__1_chanx_left_out[16]:2 0.0004141866 +3 cbx_1__0__1_chanx_left_out[16]:3 0.0002101583 +4 sb_1__0_:chanx_right_in[16] sb_1__0_:chanx_right_out[2] 5.137222e-05 +5 cbx_1__0__1_chanx_left_out[16]:2 sb_1__0__0_chanx_right_out[2]:3 5.137222e-05 + +*RES +0 cbx_2__0_:chanx_left_out[16] cbx_1__0__1_chanx_left_out[16]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[16]:3 cbx_1__0__1_chanx_left_out[16]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[16]:2 sb_1__0_:chanx_right_in[16] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[17] 0.001427176 //LENGTH 7.660 LUMPCC 0.0003740563 DR + +*CONN +*I cbx_2__0_:chanx_left_out[17] O *L 0 *C 668.990 357.680 +*I sb_1__0_:chanx_right_in[17] I *L 0 *C 661.330 357.680 +*N cbx_1__0__1_chanx_left_out[17]:2 *C 667.519 357.680 +*N cbx_1__0__1_chanx_left_out[17]:3 *C 667.520 357.680 + +*CAP +0 cbx_2__0_:chanx_left_out[17] 0.0002203569 +1 sb_1__0_:chanx_right_in[17] 0.0003062029 +2 cbx_1__0__1_chanx_left_out[17]:2 0.0003062029 +3 cbx_1__0__1_chanx_left_out[17]:3 0.0002203569 +4 sb_1__0_:chanx_right_in[17] sb_1__0_:chanx_right_out[1] 6.395851e-05 +5 cbx_1__0__1_chanx_left_out[17]:2 sb_1__0__0_chanx_right_out[1]:3 6.395851e-05 +6 sb_1__0_:chanx_right_in[17] sb_1__0_:chanx_right_out[17] 0.0001230697 +7 cbx_1__0__1_chanx_left_out[17]:2 sb_1__0__0_chanx_right_out[17]:3 0.0001230697 + +*RES +0 cbx_2__0_:chanx_left_out[17] cbx_1__0__1_chanx_left_out[17]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[17]:3 cbx_1__0__1_chanx_left_out[17]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[17]:2 sb_1__0_:chanx_right_in[17] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[18] 0.001330066 //LENGTH 7.660 LUMPCC 0.0004057403 DR + +*CONN +*I cbx_2__0_:chanx_left_out[18] O *L 0 *C 668.990 344.080 +*I sb_1__0_:chanx_right_in[18] I *L 0 *C 661.330 344.080 +*N cbx_1__0__1_chanx_left_out[18]:2 *C 667.519 344.080 +*N cbx_1__0__1_chanx_left_out[18]:3 *C 667.520 344.080 + +*CAP +0 cbx_2__0_:chanx_left_out[18] 0.0001916152 +1 sb_1__0_:chanx_right_in[18] 0.0002705476 +2 cbx_1__0__1_chanx_left_out[18]:2 0.0002705476 +3 cbx_1__0__1_chanx_left_out[18]:3 0.0001916152 +4 sb_1__0_:chanx_right_in[18] sb_1__0_:chanx_right_in[7] 6.455478e-05 +5 cbx_1__0__1_chanx_left_out[18]:2 cbx_1__0__1_chanx_left_out[7]:2 6.455478e-05 +6 cbx_2__0_:chanx_left_out[18] cbx_2__0_:chanx_left_in[7] 6.576165e-06 +7 sb_1__0_:chanx_right_in[18] sb_1__0_:chanx_right_out[7] 0.0001317392 +8 cbx_1__0__1_chanx_left_out[18]:3 sb_1__0__0_chanx_right_out[7]:2 6.576165e-06 +9 cbx_1__0__1_chanx_left_out[18]:2 sb_1__0__0_chanx_right_out[7]:3 0.0001317392 + +*RES +0 cbx_2__0_:chanx_left_out[18] cbx_1__0__1_chanx_left_out[18]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[18]:3 cbx_1__0__1_chanx_left_out[18]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[18]:2 sb_1__0_:chanx_right_in[18] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_left_out[19] 0.001478398 //LENGTH 7.660 LUMPCC 0.0005224562 DR + +*CONN +*I cbx_2__0_:chanx_left_out[19] O *L 0 *C 668.990 352.240 +*I sb_1__0_:chanx_right_in[19] I *L 0 *C 661.330 352.240 +*N cbx_1__0__1_chanx_left_out[19]:2 *C 667.519 352.240 +*N cbx_1__0__1_chanx_left_out[19]:3 *C 667.520 352.240 + +*CAP +0 cbx_2__0_:chanx_left_out[19] 0.0001990544 +1 sb_1__0_:chanx_right_in[19] 0.0002789163 +2 cbx_1__0__1_chanx_left_out[19]:2 0.0002789163 +3 cbx_1__0__1_chanx_left_out[19]:3 0.0001990544 +4 sb_1__0_:chanx_right_in[19] sb_1__0_:chanx_right_out[0] 0.0001339056 +5 cbx_1__0__1_chanx_left_out[19]:2 sb_1__0__0_chanx_right_out[0]:9 0.0001339056 +6 cbx_2__0_:chanx_left_out[19] cbx_2__0_:chanx_left_in[5] 9.865685e-06 +7 sb_1__0_:chanx_right_in[19] sb_1__0_:chanx_right_out[5] 0.0001174568 +8 cbx_1__0__1_chanx_left_out[19]:3 sb_1__0__0_chanx_right_out[5]:2 9.865685e-06 +9 cbx_1__0__1_chanx_left_out[19]:2 sb_1__0__0_chanx_right_out[5]:3 0.0001174568 + +*RES +0 cbx_2__0_:chanx_left_out[19] cbx_1__0__1_chanx_left_out[19]:3 0.0002303 +1 cbx_1__0__1_chanx_left_out[19]:3 cbx_1__0__1_chanx_left_out[19]:2 1e-05 +2 cbx_1__0__1_chanx_left_out[19]:2 sb_1__0_:chanx_right_in[19] 0.0009696099 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[0] 0.004714538 //LENGTH 38.550 LUMPCC 0.001027907 DR + +*CONN +*I cbx_2__0_:chanx_right_out[0] O *L 0 *C 769.580 369.850 +*I sb_2__0_:chanx_left_in[0] I *L 0 *C 781.230 345.440 +*N cbx_1__0__1_chanx_right_out[0]:2 *C 778.327 345.440 +*N cbx_1__0__1_chanx_right_out[0]:3 *C 778.320 345.498 +*N cbx_1__0__1_chanx_right_out[0]:4 *C 778.320 370.555 +*N cbx_1__0__1_chanx_right_out[0]:5 *C 778.275 370.600 +*N cbx_1__0__1_chanx_right_out[0]:6 *C 769.625 370.600 +*N cbx_1__0__1_chanx_right_out[0]:7 *C 769.580 370.555 + +*CAP +0 cbx_2__0_:chanx_right_out[0] 5.934172e-05 +1 sb_2__0_:chanx_left_in[0] 0.0002284223 +2 cbx_1__0__1_chanx_right_out[0]:2 0.0002284223 +3 cbx_1__0__1_chanx_right_out[0]:3 0.001130812 +4 cbx_1__0__1_chanx_right_out[0]:4 0.001130812 +5 cbx_1__0__1_chanx_right_out[0]:5 0.0004247398 +6 cbx_1__0__1_chanx_right_out[0]:6 0.0004247398 +7 cbx_1__0__1_chanx_right_out[0]:7 5.934172e-05 +8 sb_2__0_:chanx_left_in[0] sb_2__0_:chanx_left_in[3] 3.634151e-05 +9 cbx_1__0__1_chanx_right_out[0]:2 cbx_2__0_:chanx_right_out[3] 3.634151e-05 +10 sb_2__0_:chanx_left_in[0] sb_2__0_:chanx_left_in[5] 4.831976e-05 +11 cbx_1__0__1_chanx_right_out[0]:2 cbx_2__0_:chanx_right_out[5] 4.831976e-05 +12 cbx_2__0_:chanx_right_out[0] cbx_2__0_:chanx_right_out[10] 6.58791e-06 +13 cbx_1__0__1_chanx_right_out[0]:6 cbx_1__0__1_chanx_right_out[10]:6 0.0003004843 +14 cbx_1__0__1_chanx_right_out[0]:7 cbx_1__0__1_chanx_right_out[10]:7 6.58791e-06 +15 cbx_1__0__1_chanx_right_out[0]:5 cbx_1__0__1_chanx_right_out[10]:5 0.0003004843 +16 cbx_1__0__1_chanx_right_out[0]:4 cbx_1__0__1_chanx_right_out[10]:4 0.0001222202 +17 cbx_1__0__1_chanx_right_out[0]:3 cbx_1__0__1_chanx_right_out[10]:3 0.0001222202 + +*RES +0 cbx_2__0_:chanx_right_out[0] cbx_1__0__1_chanx_right_out[0]:7 0.0006294642 +1 cbx_1__0__1_chanx_right_out[0]:6 cbx_1__0__1_chanx_right_out[0]:5 0.007723215 +2 cbx_1__0__1_chanx_right_out[0]:7 cbx_1__0__1_chanx_right_out[0]:6 0.0045 +3 cbx_1__0__1_chanx_right_out[0]:5 cbx_1__0__1_chanx_right_out[0]:4 0.0045 +4 cbx_1__0__1_chanx_right_out[0]:4 cbx_1__0__1_chanx_right_out[0]:3 0.02237277 +5 cbx_1__0__1_chanx_right_out[0]:3 cbx_1__0__1_chanx_right_out[0]:2 0.00341 +6 cbx_1__0__1_chanx_right_out[0]:2 sb_2__0_:chanx_left_in[0] 0.000454725 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[1] 0.001531178 //LENGTH 7.660 LUMPCC 0.0004617306 DR + +*CONN +*I cbx_2__0_:chanx_right_out[1] O *L 0 *C 773.570 348.160 +*I sb_2__0_:chanx_left_in[1] I *L 0 *C 781.230 348.160 + +*CAP +0 cbx_2__0_:chanx_right_out[1] 0.0005347238 +1 sb_2__0_:chanx_left_in[1] 0.0005347238 +2 cbx_2__0_:chanx_right_out[1] cbx_2__0_:chanx_right_out[3] 0.0001161231 +3 sb_2__0_:chanx_left_in[1] sb_2__0_:chanx_left_in[3] 0.0001161231 +4 cbx_2__0_:chanx_right_out[1] cbx_2__0_:ccff_head[0] 0.0001147421 +5 sb_2__0_:chanx_left_in[1] sb_2__0_:ccff_tail[0] 0.0001147421 + +*RES +0 cbx_2__0_:chanx_right_out[1] sb_2__0_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[2] 0.004738226 //LENGTH 33.725 LUMPCC 0.0007797366 DR + +*CONN +*I cbx_2__0_:chanx_right_out[2] O *L 0 *C 769.120 369.770 +*I sb_2__0_:chanx_left_in[2] I *L 0 *C 781.230 350.880 +*N cbx_1__0__1_chanx_right_out[2]:2 *C 778.340 350.880 +*N cbx_1__0__1_chanx_right_out[2]:3 *C 778.320 350.887 +*N cbx_1__0__1_chanx_right_out[2]:4 *C 778.320 370.593 +*N cbx_1__0__1_chanx_right_out[2]:5 *C 778.300 370.600 +*N cbx_1__0__1_chanx_right_out[2]:6 *C 769.140 370.600 +*N cbx_1__0__1_chanx_right_out[2]:7 *C 769.120 370.593 + +*CAP +0 cbx_2__0_:chanx_right_out[2] 8.873276e-05 +1 sb_2__0_:chanx_left_in[2] 0.0002279815 +2 cbx_1__0__1_chanx_right_out[2]:2 0.0002279815 +3 cbx_1__0__1_chanx_right_out[2]:3 0.00111495 +4 cbx_1__0__1_chanx_right_out[2]:4 0.00111495 +5 cbx_1__0__1_chanx_right_out[2]:5 0.0005475807 +6 cbx_1__0__1_chanx_right_out[2]:6 0.0005475807 +7 cbx_1__0__1_chanx_right_out[2]:7 8.873276e-05 +8 sb_2__0_:chanx_left_in[2] sb_2__0_:ccff_tail[0] 4.031344e-05 +9 cbx_1__0__1_chanx_right_out[2]:2 cbx_2__0_:ccff_head[0] 4.031344e-05 +10 sb_2__0_:chanx_left_in[2] sb_2__0_:chanx_left_out[19] 4.971271e-05 +11 cbx_1__0__1_chanx_right_out[2]:2 cbx_2__0_:chanx_right_in[19] 4.971271e-05 +12 cbx_1__0__1_chanx_right_out[2]:6 ctsbuf_net_817:8 0.0002998422 +13 cbx_1__0__1_chanx_right_out[2]:5 ctsbuf_net_817:7 0.0002998422 + +*RES +0 cbx_2__0_:chanx_right_out[2] cbx_1__0__1_chanx_right_out[2]:7 0.0001288583 +1 cbx_1__0__1_chanx_right_out[2]:6 cbx_1__0__1_chanx_right_out[2]:5 0.001435067 +2 cbx_1__0__1_chanx_right_out[2]:7 cbx_1__0__1_chanx_right_out[2]:6 0.00341 +3 cbx_1__0__1_chanx_right_out[2]:5 cbx_1__0__1_chanx_right_out[2]:4 0.00341 +4 cbx_1__0__1_chanx_right_out[2]:4 cbx_1__0__1_chanx_right_out[2]:3 0.003087117 +5 cbx_1__0__1_chanx_right_out[2]:2 sb_2__0_:chanx_left_in[2] 0.0004527667 +6 cbx_1__0__1_chanx_right_out[2]:3 cbx_1__0__1_chanx_right_out[2]:2 0.00341 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[3] 0.001461641 //LENGTH 7.660 LUMPCC 0.0003907876 DR + +*CONN +*I cbx_2__0_:chanx_right_out[3] O *L 0 *C 773.570 346.800 +*I sb_2__0_:chanx_left_in[3] I *L 0 *C 781.230 346.800 + +*CAP +0 cbx_2__0_:chanx_right_out[3] 0.0005354268 +1 sb_2__0_:chanx_left_in[3] 0.0005354268 +2 cbx_2__0_:chanx_right_out[3] cbx_1__0__1_chanx_right_out[0]:2 3.634151e-05 +3 sb_2__0_:chanx_left_in[3] sb_2__0_:chanx_left_in[0] 3.634151e-05 +4 cbx_2__0_:chanx_right_out[3] cbx_2__0_:chanx_right_out[1] 0.0001161231 +5 sb_2__0_:chanx_left_in[3] sb_2__0_:chanx_left_in[1] 0.0001161231 +6 cbx_2__0_:chanx_right_out[3] cbx_2__0_:chanx_right_out[5] 4.292918e-05 +7 sb_2__0_:chanx_left_in[3] sb_2__0_:chanx_left_in[5] 4.292918e-05 + +*RES +0 cbx_2__0_:chanx_right_out[3] sb_2__0_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[4] 0.003452499 //LENGTH 27.190 LUMPCC 0.0009297175 DR + +*CONN +*I cbx_2__0_:chanx_right_out[4] O *L 0 *C 771.420 369.850 +*I sb_2__0_:chanx_left_in[4] I *L 0 *C 781.230 356.320 +*N cbx_1__0__1_chanx_right_out[4]:2 *C 775.567 356.320 +*N cbx_1__0__1_chanx_right_out[4]:3 *C 775.560 356.377 +*N cbx_1__0__1_chanx_right_out[4]:4 *C 775.560 371.235 +*N cbx_1__0__1_chanx_right_out[4]:5 *C 775.515 371.280 +*N cbx_1__0__1_chanx_right_out[4]:6 *C 771.465 371.280 +*N cbx_1__0__1_chanx_right_out[4]:7 *C 771.420 371.235 + +*CAP +0 cbx_2__0_:chanx_right_out[4] 0.0001005516 +1 sb_2__0_:chanx_left_in[4] 0.0003440152 +2 cbx_1__0__1_chanx_right_out[4]:2 0.0003440152 +3 cbx_1__0__1_chanx_right_out[4]:3 0.0006221855 +4 cbx_1__0__1_chanx_right_out[4]:4 0.0006221855 +5 cbx_1__0__1_chanx_right_out[4]:5 0.0001946384 +6 cbx_1__0__1_chanx_right_out[4]:6 0.0001946384 +7 cbx_1__0__1_chanx_right_out[4]:7 0.0001005516 +8 cbx_2__0_:chanx_right_out[4] cbx_2__0_:chanx_right_out[10] 8.234275e-06 +9 cbx_1__0__1_chanx_right_out[4]:6 cbx_1__0__1_chanx_right_out[10]:6 0.0001412751 +10 cbx_1__0__1_chanx_right_out[4]:7 cbx_1__0__1_chanx_right_out[10]:7 8.234275e-06 +11 cbx_1__0__1_chanx_right_out[4]:5 cbx_1__0__1_chanx_right_out[10]:5 0.0001412751 +12 cbx_1__0__1_chanx_right_out[4]:4 cbx_1__0__1_chanx_right_out[10]:4 1.636727e-06 +13 cbx_1__0__1_chanx_right_out[4]:3 cbx_1__0__1_chanx_right_out[10]:3 1.636727e-06 +14 sb_2__0_:chanx_left_in[4] sb_2__0_:chanx_left_out[1] 6.34922e-05 +15 cbx_1__0__1_chanx_right_out[4]:2 cbx_2__0_:chanx_right_in[1] 6.34922e-05 +16 sb_2__0_:chanx_left_in[4] sb_2__0_:chanx_left_out[5] 9.790535e-05 +17 cbx_1__0__1_chanx_right_out[4]:2 cbx_2__0_:chanx_right_in[5] 9.790535e-05 +18 cbx_1__0__1_chanx_right_out[4]:4 ctsbuf_net_817:6 0.0001523151 +19 cbx_1__0__1_chanx_right_out[4]:3 ctsbuf_net_817:5 0.0001523151 + +*RES +0 cbx_2__0_:chanx_right_out[4] cbx_1__0__1_chanx_right_out[4]:7 0.001236607 +1 cbx_1__0__1_chanx_right_out[4]:6 cbx_1__0__1_chanx_right_out[4]:5 0.003616071 +2 cbx_1__0__1_chanx_right_out[4]:7 cbx_1__0__1_chanx_right_out[4]:6 0.0045 +3 cbx_1__0__1_chanx_right_out[4]:5 cbx_1__0__1_chanx_right_out[4]:4 0.0045 +4 cbx_1__0__1_chanx_right_out[4]:4 cbx_1__0__1_chanx_right_out[4]:3 0.01326563 +5 cbx_1__0__1_chanx_right_out[4]:3 cbx_1__0__1_chanx_right_out[4]:2 0.00341 +6 cbx_1__0__1_chanx_right_out[4]:2 sb_2__0_:chanx_left_in[4] 0.0008871249 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[5] 0.001350925 //LENGTH 7.660 LUMPCC 0.0004735098 DR + +*CONN +*I cbx_2__0_:chanx_right_out[5] O *L 0 *C 773.570 344.080 +*I sb_2__0_:chanx_left_in[5] I *L 0 *C 781.230 344.080 + +*CAP +0 cbx_2__0_:chanx_right_out[5] 0.0004387075 +1 sb_2__0_:chanx_left_in[5] 0.0004387075 +2 cbx_2__0_:chanx_right_out[5] cbx_1__0__1_chanx_right_out[0]:2 4.831976e-05 +3 sb_2__0_:chanx_left_in[5] sb_2__0_:chanx_left_in[0] 4.831976e-05 +4 cbx_2__0_:chanx_right_out[5] cbx_2__0_:chanx_right_out[3] 4.292918e-05 +5 sb_2__0_:chanx_left_in[5] sb_2__0_:chanx_left_in[3] 4.292918e-05 +6 cbx_2__0_:chanx_right_out[5] cbx_2__0_:chanx_right_in[7] 0.000145506 +7 sb_2__0_:chanx_left_in[5] sb_2__0_:chanx_left_out[7] 0.000145506 + +*RES +0 cbx_2__0_:chanx_right_out[5] sb_2__0_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[6] 0.001388401 //LENGTH 7.660 LUMPCC 0.0003834238 DR + +*CONN +*I cbx_2__0_:chanx_right_out[6] O *L 0 *C 773.570 341.360 +*I sb_2__0_:chanx_left_in[6] I *L 0 *C 781.230 341.360 + +*CAP +0 cbx_2__0_:chanx_right_out[6] 0.0005024887 +1 sb_2__0_:chanx_left_in[6] 0.0005024887 +2 cbx_2__0_:chanx_right_out[6] cbx_2__0_:chanx_right_out[13] 6.232323e-05 +3 sb_2__0_:chanx_left_in[6] sb_2__0_:chanx_left_in[13] 6.232323e-05 +4 cbx_2__0_:chanx_right_out[6] cbx_2__0_:chanx_right_in[7] 0.0001293887 +5 sb_2__0_:chanx_left_in[6] sb_2__0_:chanx_left_out[7] 0.0001293887 + +*RES +0 cbx_2__0_:chanx_right_out[6] sb_2__0_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[7] 0.001516251 //LENGTH 7.660 LUMPCC 0.0004347771 DR + +*CONN +*I cbx_2__0_:chanx_right_out[7] O *L 0 *C 773.570 364.480 +*I sb_2__0_:chanx_left_in[7] I *L 0 *C 781.230 364.480 + +*CAP +0 cbx_2__0_:chanx_right_out[7] 0.0005407367 +1 sb_2__0_:chanx_left_in[7] 0.0005407367 +2 cbx_2__0_:chanx_right_out[7] cbx_2__0_:chanx_right_out[9] 0.0001002795 +3 sb_2__0_:chanx_left_in[7] sb_2__0_:chanx_left_in[9] 0.0001002795 +4 cbx_2__0_:chanx_right_out[7] cbx_2__0_:chanx_right_out[11] 0.000117109 +5 sb_2__0_:chanx_left_in[7] sb_2__0_:chanx_left_in[11] 0.000117109 + +*RES +0 cbx_2__0_:chanx_right_out[7] sb_2__0_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[8] 0.001458163 //LENGTH 7.660 LUMPCC 0.0005110296 DR + +*CONN +*I cbx_2__0_:chanx_right_out[8] O *L 0 *C 773.570 326.400 +*I sb_2__0_:chanx_left_in[8] I *L 0 *C 781.230 326.400 + +*CAP +0 cbx_2__0_:chanx_right_out[8] 0.0004735667 +1 sb_2__0_:chanx_left_in[8] 0.0004735667 +2 cbx_2__0_:chanx_right_out[8] cbx_2__0_:chanx_right_in[9] 0.0001193389 +3 sb_2__0_:chanx_left_in[8] sb_2__0_:chanx_left_out[9] 0.0001193389 +4 cbx_2__0_:chanx_right_out[8] cbx_2__0_:chanx_right_in[16] 0.0001361759 +5 sb_2__0_:chanx_left_in[8] sb_2__0_:chanx_left_out[16] 0.0001361759 + +*RES +0 cbx_2__0_:chanx_right_out[8] sb_2__0_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[9] 0.001487889 //LENGTH 7.660 LUMPCC 0.0002005591 DR + +*CONN +*I cbx_2__0_:chanx_right_out[9] O *L 0 *C 773.570 365.840 +*I sb_2__0_:chanx_left_in[9] I *L 0 *C 781.230 365.840 + +*CAP +0 cbx_2__0_:chanx_right_out[9] 0.0006436652 +1 sb_2__0_:chanx_left_in[9] 0.0006436652 +2 cbx_2__0_:chanx_right_out[9] cbx_2__0_:chanx_right_out[7] 0.0001002795 +3 sb_2__0_:chanx_left_in[9] sb_2__0_:chanx_left_in[7] 0.0001002795 + +*RES +0 cbx_2__0_:chanx_right_out[9] sb_2__0_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[10] 0.003250528 //LENGTH 22.670 LUMPCC 0.001160877 DR + +*CONN +*I cbx_2__0_:chanx_right_out[10] O *L 0 *C 770.500 369.850 +*I sb_2__0_:chanx_left_in[10] I *L 0 *C 781.230 361.080 +*N cbx_1__0__1_chanx_right_out[10]:2 *C 779.248 361.080 +*N cbx_1__0__1_chanx_right_out[10]:3 *C 779.240 361.138 +*N cbx_1__0__1_chanx_right_out[10]:4 *C 779.240 370.895 +*N cbx_1__0__1_chanx_right_out[10]:5 *C 779.195 370.940 +*N cbx_1__0__1_chanx_right_out[10]:6 *C 770.545 370.940 +*N cbx_1__0__1_chanx_right_out[10]:7 *C 770.500 370.895 + +*CAP +0 cbx_2__0_:chanx_right_out[10] 7.365139e-05 +1 sb_2__0_:chanx_left_in[10] 0.0002626572 +2 cbx_1__0__1_chanx_right_out[10]:2 0.0002626572 +3 cbx_1__0__1_chanx_right_out[10]:3 0.0003971697 +4 cbx_1__0__1_chanx_right_out[10]:4 0.0003971697 +5 cbx_1__0__1_chanx_right_out[10]:5 0.0003113473 +6 cbx_1__0__1_chanx_right_out[10]:6 0.0003113473 +7 cbx_1__0__1_chanx_right_out[10]:7 7.365139e-05 +8 cbx_2__0_:chanx_right_out[10] cbx_2__0_:chanx_right_out[0] 6.58791e-06 +9 cbx_1__0__1_chanx_right_out[10]:6 cbx_1__0__1_chanx_right_out[0]:6 0.0003004843 +10 cbx_1__0__1_chanx_right_out[10]:7 cbx_1__0__1_chanx_right_out[0]:7 6.58791e-06 +11 cbx_1__0__1_chanx_right_out[10]:5 cbx_1__0__1_chanx_right_out[0]:5 0.0003004843 +12 cbx_1__0__1_chanx_right_out[10]:4 cbx_1__0__1_chanx_right_out[0]:4 0.0001222202 +13 cbx_1__0__1_chanx_right_out[10]:3 cbx_1__0__1_chanx_right_out[0]:3 0.0001222202 +14 cbx_2__0_:chanx_right_out[10] cbx_2__0_:chanx_right_out[4] 8.234275e-06 +15 cbx_1__0__1_chanx_right_out[10]:6 cbx_1__0__1_chanx_right_out[4]:6 0.0001412751 +16 cbx_1__0__1_chanx_right_out[10]:7 cbx_1__0__1_chanx_right_out[4]:7 8.234275e-06 +17 cbx_1__0__1_chanx_right_out[10]:5 cbx_1__0__1_chanx_right_out[4]:5 0.0001412751 +18 cbx_1__0__1_chanx_right_out[10]:4 cbx_1__0__1_chanx_right_out[4]:4 1.636727e-06 +19 cbx_1__0__1_chanx_right_out[10]:3 cbx_1__0__1_chanx_right_out[4]:3 1.636727e-06 + +*RES +0 cbx_2__0_:chanx_right_out[10] cbx_1__0__1_chanx_right_out[10]:7 0.0009330357 +1 cbx_1__0__1_chanx_right_out[10]:6 cbx_1__0__1_chanx_right_out[10]:5 0.007723215 +2 cbx_1__0__1_chanx_right_out[10]:7 cbx_1__0__1_chanx_right_out[10]:6 0.0045 +3 cbx_1__0__1_chanx_right_out[10]:5 cbx_1__0__1_chanx_right_out[10]:4 0.0045 +4 cbx_1__0__1_chanx_right_out[10]:4 cbx_1__0__1_chanx_right_out[10]:3 0.008712054 +5 cbx_1__0__1_chanx_right_out[10]:3 cbx_1__0__1_chanx_right_out[10]:2 0.00341 +6 cbx_1__0__1_chanx_right_out[10]:2 sb_2__0_:chanx_left_in[10] 0.0003105916 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[11] 0.001410744 //LENGTH 7.660 LUMPCC 0.0002946965 DR + +*CONN +*I cbx_2__0_:chanx_right_out[11] O *L 0 *C 773.570 363.120 +*I sb_2__0_:chanx_left_in[11] I *L 0 *C 781.230 363.120 + +*CAP +0 cbx_2__0_:chanx_right_out[11] 0.0005580236 +1 sb_2__0_:chanx_left_in[11] 0.0005580236 +2 cbx_2__0_:chanx_right_out[11] cbx_2__0_:chanx_right_out[7] 0.000117109 +3 sb_2__0_:chanx_left_in[11] sb_2__0_:chanx_left_in[7] 0.000117109 +4 cbx_2__0_:chanx_right_out[11] cbx_2__0_:chanx_right_in[13] 3.023926e-05 +5 sb_2__0_:chanx_left_in[11] sb_2__0_:chanx_left_out[13] 3.023926e-05 + +*RES +0 cbx_2__0_:chanx_right_out[11] sb_2__0_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[12] 0.001418083 //LENGTH 7.660 LUMPCC 0.00039264 DR + +*CONN +*I cbx_2__0_:chanx_right_out[12] O *L 0 *C 773.570 330.480 +*I sb_2__0_:chanx_left_in[12] I *L 0 *C 781.230 330.480 + +*CAP +0 cbx_2__0_:chanx_right_out[12] 0.0005127215 +1 sb_2__0_:chanx_left_in[12] 0.0005127215 +2 cbx_2__0_:chanx_right_out[12] cbx_2__0_:chanx_right_in[9] 6.652179e-05 +3 sb_2__0_:chanx_left_in[12] sb_2__0_:chanx_left_out[9] 6.652179e-05 +4 cbx_2__0_:chanx_right_out[12] cbx_2__0_:chanx_right_in[11] 0.0001297982 +5 sb_2__0_:chanx_left_in[12] sb_2__0_:chanx_left_out[11] 0.0001297982 + +*RES +0 cbx_2__0_:chanx_right_out[12] sb_2__0_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[13] 0.001442499 //LENGTH 7.660 LUMPCC 0.0003604409 DR + +*CONN +*I cbx_2__0_:chanx_right_out[13] O *L 0 *C 773.570 338.640 +*I sb_2__0_:chanx_left_in[13] I *L 0 *C 781.230 338.640 + +*CAP +0 cbx_2__0_:chanx_right_out[13] 0.0005410292 +1 sb_2__0_:chanx_left_in[13] 0.0005410292 +2 cbx_2__0_:chanx_right_out[13] cbx_2__0_:chanx_right_out[6] 6.232323e-05 +3 sb_2__0_:chanx_left_in[13] sb_2__0_:chanx_left_in[6] 6.232323e-05 +4 cbx_2__0_:chanx_right_out[13] cbx_2__0_:chanx_right_in[17] 0.0001178972 +5 sb_2__0_:chanx_left_in[13] sb_2__0_:chanx_left_out[17] 0.0001178972 + +*RES +0 cbx_2__0_:chanx_right_out[13] sb_2__0_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[14] 0.001425562 //LENGTH 7.660 LUMPCC 0.0003243075 DR + +*CONN +*I cbx_2__0_:chanx_right_out[14] O *L 0 *C 773.570 300.560 +*I sb_2__0_:chanx_left_in[14] I *L 0 *C 781.230 300.560 + +*CAP +0 cbx_2__0_:chanx_right_out[14] 0.0005506274 +1 sb_2__0_:chanx_left_in[14] 0.0005506274 +2 cbx_2__0_:chanx_right_out[14] cbx_2__0_:chanx_right_out[18] 0.0001161462 +3 sb_2__0_:chanx_left_in[14] sb_2__0_:chanx_left_in[18] 0.0001161462 +4 cbx_2__0_:chanx_right_out[14] cbx_2__0_:chanx_right_in[18] 4.600756e-05 +5 sb_2__0_:chanx_left_in[14] sb_2__0_:chanx_left_out[18] 4.600756e-05 + +*RES +0 cbx_2__0_:chanx_right_out[14] sb_2__0_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[15] 0.001395644 //LENGTH 7.660 LUMPCC 0.0003617976 DR + +*CONN +*I cbx_2__0_:chanx_right_out[15] O *L 0 *C 773.570 335.920 +*I sb_2__0_:chanx_left_in[15] I *L 0 *C 781.230 335.920 + +*CAP +0 cbx_2__0_:chanx_right_out[15] 0.000516923 +1 sb_2__0_:chanx_left_in[15] 0.000516923 +2 cbx_2__0_:chanx_right_out[15] cbx_2__0_:chanx_right_in[15] 6.180091e-05 +3 sb_2__0_:chanx_left_in[15] sb_2__0_:chanx_left_out[15] 6.180091e-05 +4 cbx_2__0_:chanx_right_out[15] cbx_2__0_:chanx_right_in[17] 0.0001190979 +5 sb_2__0_:chanx_left_in[15] sb_2__0_:chanx_left_out[17] 0.0001190979 + +*RES +0 cbx_2__0_:chanx_right_out[15] sb_2__0_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[16] 0.001333422 //LENGTH 7.660 LUMPCC 0.0003777607 DR + +*CONN +*I cbx_2__0_:chanx_right_out[16] O *L 0 *C 773.570 322.320 +*I sb_2__0_:chanx_left_in[16] I *L 0 *C 781.230 322.320 + +*CAP +0 cbx_2__0_:chanx_right_out[16] 0.0004778305 +1 sb_2__0_:chanx_left_in[16] 0.0004778305 +2 cbx_2__0_:chanx_right_out[16] cbx_2__0_:chanx_right_in[0] 0.0001264714 +3 sb_2__0_:chanx_left_in[16] sb_2__0_:chanx_left_out[0] 0.0001264714 +4 cbx_2__0_:chanx_right_out[16] cbx_2__0_:chanx_right_in[16] 6.240896e-05 +5 sb_2__0_:chanx_left_in[16] sb_2__0_:chanx_left_out[16] 6.240896e-05 + +*RES +0 cbx_2__0_:chanx_right_out[16] sb_2__0_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[17] 0.003428608 //LENGTH 31.270 LUMPCC 0.0001894747 DR + +*CONN +*I cbx_2__0_:chanx_right_out[17] O *L 0 *C 771.420 293.830 +*I sb_2__0_:chanx_left_in[17] I *L 0 *C 781.230 312.800 +*N cbx_1__0__1_chanx_right_out[17]:2 *C 778.327 312.800 +*N cbx_1__0__1_chanx_right_out[17]:3 *C 778.320 312.743 +*N cbx_1__0__1_chanx_right_out[17]:4 *C 778.320 293.125 +*N cbx_1__0__1_chanx_right_out[17]:5 *C 778.275 293.080 +*N cbx_1__0__1_chanx_right_out[17]:6 *C 771.465 293.080 +*N cbx_1__0__1_chanx_right_out[17]:7 *C 771.420 293.125 + +*CAP +0 cbx_2__0_:chanx_right_out[17] 6.029628e-05 +1 sb_2__0_:chanx_left_in[17] 0.0002164161 +2 cbx_1__0__1_chanx_right_out[17]:2 0.0002164161 +3 cbx_1__0__1_chanx_right_out[17]:3 0.0009186128 +4 cbx_1__0__1_chanx_right_out[17]:4 0.0009186128 +5 cbx_1__0__1_chanx_right_out[17]:5 0.0004242414 +6 cbx_1__0__1_chanx_right_out[17]:6 0.0004242414 +7 cbx_1__0__1_chanx_right_out[17]:7 6.029628e-05 +8 sb_2__0_:chanx_left_in[17] sb_2__0_:chanx_left_out[10] 5.207383e-05 +9 cbx_1__0__1_chanx_right_out[17]:2 cbx_2__0_:chanx_right_in[10] 5.207383e-05 +10 sb_2__0_:chanx_left_in[17] sb_2__0_:chanx_left_out[14] 4.266354e-05 +11 cbx_1__0__1_chanx_right_out[17]:2 cbx_2__0_:chanx_right_in[14] 4.266354e-05 + +*RES +0 cbx_2__0_:chanx_right_out[17] cbx_1__0__1_chanx_right_out[17]:7 0.0006294643 +1 cbx_1__0__1_chanx_right_out[17]:6 cbx_1__0__1_chanx_right_out[17]:5 0.006080357 +2 cbx_1__0__1_chanx_right_out[17]:7 cbx_1__0__1_chanx_right_out[17]:6 0.0045 +3 cbx_1__0__1_chanx_right_out[17]:5 cbx_1__0__1_chanx_right_out[17]:4 0.0045 +4 cbx_1__0__1_chanx_right_out[17]:4 cbx_1__0__1_chanx_right_out[17]:3 0.01751563 +5 cbx_1__0__1_chanx_right_out[17]:3 cbx_1__0__1_chanx_right_out[17]:2 0.00341 +6 cbx_1__0__1_chanx_right_out[17]:2 sb_2__0_:chanx_left_in[17] 0.000454725 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[18] 0.001511647 //LENGTH 7.660 LUMPCC 0.0004645848 DR + +*CONN +*I cbx_2__0_:chanx_right_out[18] O *L 0 *C 773.570 299.200 +*I sb_2__0_:chanx_left_in[18] I *L 0 *C 781.230 299.200 + +*CAP +0 cbx_2__0_:chanx_right_out[18] 0.0005235311 +1 sb_2__0_:chanx_left_in[18] 0.0005235311 +2 cbx_2__0_:chanx_right_out[18] cbx_2__0_:chanx_right_out[14] 0.0001161462 +3 sb_2__0_:chanx_left_in[18] sb_2__0_:chanx_left_in[14] 0.0001161462 +4 cbx_2__0_:chanx_right_out[18] cbx_2__0_:chanx_right_out[19] 0.0001161462 +5 sb_2__0_:chanx_left_in[18] sb_2__0_:chanx_left_in[19] 0.0001161462 + +*RES +0 cbx_2__0_:chanx_right_out[18] sb_2__0_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET cbx_1__0__1_chanx_right_out[19] 0.001369445 //LENGTH 7.660 LUMPCC 0.0002322924 DR + +*CONN +*I cbx_2__0_:chanx_right_out[19] O *L 0 *C 773.570 297.840 +*I sb_2__0_:chanx_left_in[19] I *L 0 *C 781.230 297.840 + +*CAP +0 cbx_2__0_:chanx_right_out[19] 0.0005685763 +1 sb_2__0_:chanx_left_in[19] 0.0005685763 +2 cbx_2__0_:chanx_right_out[19] cbx_2__0_:chanx_right_out[18] 0.0001161462 +3 sb_2__0_:chanx_left_in[19] sb_2__0_:chanx_left_in[18] 0.0001161462 + +*RES +0 cbx_2__0_:chanx_right_out[19] sb_2__0_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_16_[0] 0.001327698 //LENGTH 11.020 LUMPCC 0.000720888 DR + +*CONN +*I cbx_2__0_:top_grid_pin_16_[0] O *L 0 *C 702.880 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] I *L 0 *C 702.880 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_16_[0] 0.0003034048 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 0.0003034049 +2 cbx_2__0_:top_grid_pin_16_[0] cbx_2__0_:top_grid_pin_18_[0] 0.0001503629 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] 0.0001503629 +4 cbx_2__0_:top_grid_pin_16_[0] cbx_2__0_:top_grid_pin_22_[0] 1.50643e-05 +5 cbx_2__0_:top_grid_pin_16_[0] cbx_1__0__1_top_grid_pin_22_[0]:4 0.0001470562 +6 cbx_2__0_:top_grid_pin_16_[0] cbx_1__0__1_top_grid_pin_22_[0]:2 4.796057e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_22_[0] 4.796057e-05 +8 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] cbx_1__0__1_top_grid_pin_22_[0]:5 1.50643e-05 +9 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] cbx_1__0__1_top_grid_pin_22_[0]:3 0.0001470562 + +*RES +0 cbx_2__0_:top_grid_pin_16_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_17_[0] 0.001343469 //LENGTH 11.020 LUMPCC 0.000699808 DR + +*CONN +*I cbx_2__0_:top_grid_pin_17_[0] O *L 0 *C 704.720 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] I *L 0 *C 704.720 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_17_[0] 0.0003218303 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 0.0003218303 +2 cbx_2__0_:top_grid_pin_17_[0] cbx_2__0_:top_grid_pin_18_[0] 0.0001437994 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] 0.0001437994 +4 cbx_2__0_:top_grid_pin_17_[0] cbx_2__0_:top_grid_pin_19_[0] 1.507345e-05 +5 cbx_2__0_:top_grid_pin_17_[0] cbx_1__0__1_top_grid_pin_19_[0]:4 0.0001441297 +6 cbx_2__0_:top_grid_pin_17_[0] cbx_1__0__1_top_grid_pin_19_[0]:2 4.690145e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_19_[0] 4.690145e-05 +8 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] cbx_1__0__1_top_grid_pin_19_[0]:5 1.507345e-05 +9 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] cbx_1__0__1_top_grid_pin_19_[0]:3 0.0001441297 + +*RES +0 cbx_2__0_:top_grid_pin_17_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_18_[0] 0.001244154 //LENGTH 11.020 LUMPCC 0.0005883247 DR + +*CONN +*I cbx_2__0_:top_grid_pin_18_[0] O *L 0 *C 703.800 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] I *L 0 *C 703.800 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_18_[0] 0.0003279148 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] 0.0003279148 +2 cbx_2__0_:top_grid_pin_18_[0] cbx_2__0_:top_grid_pin_16_[0] 0.0001503629 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 0.0001503629 +4 cbx_2__0_:top_grid_pin_18_[0] cbx_2__0_:top_grid_pin_17_[0] 0.0001437994 +5 grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 0.0001437994 + +*RES +0 cbx_2__0_:top_grid_pin_18_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_18_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_19_[0] 0.001421998 //LENGTH 12.500 LUMPCC 0.0004122091 DR + +*CONN +*I cbx_2__0_:top_grid_pin_19_[0] O *L 0 *C 705.640 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_19_[0] I *L 0 *C 705.640 380.870 +*N cbx_1__0__1_top_grid_pin_19_[0]:2 *C 705.640 377.060 +*N cbx_1__0__1_top_grid_pin_19_[0]:3 *C 705.180 377.060 +*N cbx_1__0__1_top_grid_pin_19_[0]:4 *C 705.180 371.960 +*N cbx_1__0__1_top_grid_pin_19_[0]:5 *C 705.640 371.960 + +*CAP +0 cbx_2__0_:top_grid_pin_19_[0] 0.0001292056 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_19_[0] 0.0001521075 +2 cbx_1__0__1_top_grid_pin_19_[0]:2 0.0001772646 +3 cbx_1__0__1_top_grid_pin_19_[0]:3 0.000196026 +4 cbx_1__0__1_top_grid_pin_19_[0]:4 0.000198424 +5 cbx_1__0__1_top_grid_pin_19_[0]:5 0.0001567607 +6 cbx_2__0_:top_grid_pin_19_[0] cbx_2__0_:top_grid_pin_17_[0] 1.507345e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_19_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 4.690145e-05 +8 cbx_1__0__1_top_grid_pin_19_[0]:4 cbx_2__0_:top_grid_pin_17_[0] 0.0001441297 +9 cbx_1__0__1_top_grid_pin_19_[0]:5 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 1.507345e-05 +10 cbx_1__0__1_top_grid_pin_19_[0]:3 grid_clb_2__1_:bottom_width_0_height_0__pin_17_[0] 0.0001441297 +11 cbx_1__0__1_top_grid_pin_19_[0]:2 cbx_2__0_:top_grid_pin_17_[0] 4.690145e-05 + +*RES +0 cbx_2__0_:top_grid_pin_19_[0] cbx_1__0__1_top_grid_pin_19_[0]:5 0.001883929 +1 cbx_1__0__1_top_grid_pin_19_[0]:4 cbx_1__0__1_top_grid_pin_19_[0]:3 0.004553572 +2 cbx_1__0__1_top_grid_pin_19_[0]:5 cbx_1__0__1_top_grid_pin_19_[0]:4 0.0004107143 +3 cbx_1__0__1_top_grid_pin_19_[0]:3 cbx_1__0__1_top_grid_pin_19_[0]:2 0.0004107143 +4 cbx_1__0__1_top_grid_pin_19_[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_19_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_20_[0] 0.001086602 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__0_:top_grid_pin_20_[0] O *L 0 *C 726.340 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_20_[0] I *L 0 *C 726.340 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_20_[0] 0.0005433008 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_20_[0] 0.0005433008 + +*RES +0 cbx_2__0_:top_grid_pin_20_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_20_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_21_[0] 0.00144007 //LENGTH 12.500 LUMPCC 0.0004086623 DR + +*CONN +*I cbx_2__0_:top_grid_pin_21_[0] O *L 0 *C 684.940 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_21_[0] I *L 0 *C 684.940 380.870 +*N cbx_1__0__1_top_grid_pin_21_[0]:2 *C 684.940 377.060 +*N cbx_1__0__1_top_grid_pin_21_[0]:3 *C 684.480 377.060 +*N cbx_1__0__1_top_grid_pin_21_[0]:4 *C 684.480 371.960 +*N cbx_1__0__1_top_grid_pin_21_[0]:5 *C 684.940 371.960 + +*CAP +0 cbx_2__0_:top_grid_pin_21_[0] 0.0001297538 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_21_[0] 0.0001563388 +2 cbx_1__0__1_top_grid_pin_21_[0]:2 0.0001822986 +3 cbx_1__0__1_top_grid_pin_21_[0]:3 0.0002014359 +4 cbx_1__0__1_top_grid_pin_21_[0]:4 0.0002036513 +5 cbx_1__0__1_top_grid_pin_21_[0]:5 0.000157929 +6 cbx_2__0_:top_grid_pin_21_[0] cbx_2__0_:top_grid_pin_23_[0] 1.498914e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_21_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 4.617783e-05 +8 cbx_1__0__1_top_grid_pin_21_[0]:4 cbx_2__0_:top_grid_pin_23_[0] 0.0001431642 +9 cbx_1__0__1_top_grid_pin_21_[0]:5 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 1.498914e-05 +10 cbx_1__0__1_top_grid_pin_21_[0]:3 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 0.0001431642 +11 cbx_1__0__1_top_grid_pin_21_[0]:2 cbx_2__0_:top_grid_pin_23_[0] 4.617783e-05 + +*RES +0 cbx_2__0_:top_grid_pin_21_[0] cbx_1__0__1_top_grid_pin_21_[0]:5 0.001883929 +1 cbx_1__0__1_top_grid_pin_21_[0]:4 cbx_1__0__1_top_grid_pin_21_[0]:3 0.004553572 +2 cbx_1__0__1_top_grid_pin_21_[0]:5 cbx_1__0__1_top_grid_pin_21_[0]:4 0.0004107143 +3 cbx_1__0__1_top_grid_pin_21_[0]:3 cbx_1__0__1_top_grid_pin_21_[0]:2 0.0004107143 +4 cbx_1__0__1_top_grid_pin_21_[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_21_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_22_[0] 0.001405147 //LENGTH 12.500 LUMPCC 0.0004201621 DR + +*CONN +*I cbx_2__0_:top_grid_pin_22_[0] O *L 0 *C 701.960 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_22_[0] I *L 0 *C 701.960 380.870 +*N cbx_1__0__1_top_grid_pin_22_[0]:2 *C 701.960 377.060 +*N cbx_1__0__1_top_grid_pin_22_[0]:3 *C 702.420 377.060 +*N cbx_1__0__1_top_grid_pin_22_[0]:4 *C 702.420 371.960 +*N cbx_1__0__1_top_grid_pin_22_[0]:5 *C 701.960 371.960 + +*CAP +0 cbx_2__0_:top_grid_pin_22_[0] 0.0001249447 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_22_[0] 0.0001454032 +2 cbx_1__0__1_top_grid_pin_22_[0]:2 0.000170234 +3 cbx_1__0__1_top_grid_pin_22_[0]:3 0.0001955657 +4 cbx_1__0__1_top_grid_pin_22_[0]:4 0.0001973138 +5 cbx_1__0__1_top_grid_pin_22_[0]:5 0.0001515236 +6 cbx_2__0_:top_grid_pin_22_[0] cbx_2__0_:top_grid_pin_16_[0] 1.50643e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_22_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 4.796057e-05 +8 cbx_1__0__1_top_grid_pin_22_[0]:5 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 1.50643e-05 +9 cbx_1__0__1_top_grid_pin_22_[0]:4 cbx_2__0_:top_grid_pin_16_[0] 0.0001470562 +10 cbx_1__0__1_top_grid_pin_22_[0]:2 cbx_2__0_:top_grid_pin_16_[0] 4.796057e-05 +11 cbx_1__0__1_top_grid_pin_22_[0]:3 grid_clb_2__1_:bottom_width_0_height_0__pin_16_[0] 0.0001470562 + +*RES +0 cbx_2__0_:top_grid_pin_22_[0] cbx_1__0__1_top_grid_pin_22_[0]:5 0.001883929 +1 cbx_1__0__1_top_grid_pin_22_[0]:5 cbx_1__0__1_top_grid_pin_22_[0]:4 0.0004107143 +2 cbx_1__0__1_top_grid_pin_22_[0]:4 cbx_1__0__1_top_grid_pin_22_[0]:3 0.004553572 +3 cbx_1__0__1_top_grid_pin_22_[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_22_[0] 0.003401786 +4 cbx_1__0__1_top_grid_pin_22_[0]:3 cbx_1__0__1_top_grid_pin_22_[0]:2 0.0004107143 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_23_[0] 0.001348084 //LENGTH 11.020 LUMPCC 0.0006942049 DR + +*CONN +*I cbx_2__0_:top_grid_pin_23_[0] O *L 0 *C 684.020 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] I *L 0 *C 684.020 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_23_[0] 0.0003269394 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 0.0003269395 +2 cbx_2__0_:top_grid_pin_23_[0] cbx_2__0_:top_grid_pin_21_[0] 1.498914e-05 +3 cbx_2__0_:top_grid_pin_23_[0] cbx_1__0__1_top_grid_pin_21_[0]:2 4.617783e-05 +4 cbx_2__0_:top_grid_pin_23_[0] cbx_1__0__1_top_grid_pin_21_[0]:4 0.0001431642 +5 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_21_[0] 4.617783e-05 +6 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] cbx_1__0__1_top_grid_pin_21_[0]:3 0.0001431642 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] cbx_1__0__1_top_grid_pin_21_[0]:5 1.498914e-05 +8 cbx_2__0_:top_grid_pin_23_[0] cbx_2__0_:top_grid_pin_27_[0] 0.0001427713 +9 grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] 0.0001427713 + +*RES +0 cbx_2__0_:top_grid_pin_23_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_24_[0] 0.001067511 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__0_:top_grid_pin_24_[0] O *L 0 *C 671.140 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_24_[0] I *L 0 *C 671.140 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_24_[0] 0.0005337555 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_24_[0] 0.0005337555 + +*RES +0 cbx_2__0_:top_grid_pin_24_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_24_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_25_[0] 0.001173396 //LENGTH 11.020 LUMPCC 0.0002855426 DR + +*CONN +*I cbx_2__0_:top_grid_pin_25_[0] O *L 0 *C 681.260 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_25_[0] I *L 0 *C 681.260 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_25_[0] 0.0004439268 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_25_[0] 0.0004439268 +2 cbx_2__0_:top_grid_pin_25_[0] cbx_2__0_:top_grid_pin_26_[0] 0.0001427713 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_25_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] 0.0001427713 + +*RES +0 cbx_2__0_:top_grid_pin_25_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_25_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_26_[0] 0.001250093 //LENGTH 11.020 LUMPCC 0.0005710853 DR + +*CONN +*I cbx_2__0_:top_grid_pin_26_[0] O *L 0 *C 682.180 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] I *L 0 *C 682.180 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_26_[0] 0.000339504 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] 0.000339504 +2 cbx_2__0_:top_grid_pin_26_[0] cbx_2__0_:top_grid_pin_25_[0] 0.0001427713 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_25_[0] 0.0001427713 +4 cbx_2__0_:top_grid_pin_26_[0] cbx_2__0_:top_grid_pin_27_[0] 0.0001427713 +5 grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] 0.0001427713 + +*RES +0 cbx_2__0_:top_grid_pin_26_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_27_[0] 0.001250046 //LENGTH 11.020 LUMPCC 0.0005710853 DR + +*CONN +*I cbx_2__0_:top_grid_pin_27_[0] O *L 0 *C 683.100 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] I *L 0 *C 683.100 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_27_[0] 0.0003394803 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] 0.0003394803 +2 cbx_2__0_:top_grid_pin_27_[0] cbx_2__0_:top_grid_pin_23_[0] 0.0001427713 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_23_[0] 0.0001427713 +4 cbx_2__0_:top_grid_pin_27_[0] cbx_2__0_:top_grid_pin_26_[0] 0.0001427713 +5 grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_26_[0] 0.0001427713 + +*RES +0 cbx_2__0_:top_grid_pin_27_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_27_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_28_[0] 0.001136917 //LENGTH 11.020 LUMPCC 0.0003020416 DR + +*CONN +*I cbx_2__0_:top_grid_pin_28_[0] O *L 0 *C 742.440 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_28_[0] I *L 0 *C 742.440 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_28_[0] 0.0004174375 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_28_[0] 0.0004174375 +2 cbx_2__0_:top_grid_pin_28_[0] cbx_2__0_:top_grid_pin_29_[0] 0.0001510208 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_28_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] 0.0001510208 + +*RES +0 cbx_2__0_:top_grid_pin_28_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_28_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_29_[0] 0.001224674 //LENGTH 11.020 LUMPCC 0.0006040831 DR + +*CONN +*I cbx_2__0_:top_grid_pin_29_[0] O *L 0 *C 743.360 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] I *L 0 *C 743.360 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_29_[0] 0.0003102954 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] 0.0003102954 +2 cbx_2__0_:top_grid_pin_29_[0] cbx_2__0_:top_grid_pin_28_[0] 0.0001510208 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_28_[0] 0.0001510208 +4 cbx_2__0_:top_grid_pin_29_[0] cbx_2__0_:top_grid_pin_31_[0] 0.0001510208 +5 grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 0.0001510208 + +*RES +0 cbx_2__0_:top_grid_pin_29_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_30_[0] 0.001434818 //LENGTH 12.500 LUMPCC 0.0004085505 DR + +*CONN +*I cbx_2__0_:top_grid_pin_30_[0] O *L 0 *C 745.200 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_30_[0] I *L 0 *C 745.200 380.870 +*N cbx_1__0__1_top_grid_pin_30_[0]:2 *C 745.200 377.060 +*N cbx_1__0__1_top_grid_pin_30_[0]:3 *C 744.740 377.060 +*N cbx_1__0__1_top_grid_pin_30_[0]:4 *C 744.740 371.960 +*N cbx_1__0__1_top_grid_pin_30_[0]:5 *C 745.200 371.960 + +*CAP +0 cbx_2__0_:top_grid_pin_30_[0] 0.0001296314 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_30_[0] 0.0001548279 +2 cbx_1__0__1_top_grid_pin_30_[0]:2 0.0001804526 +3 cbx_1__0__1_top_grid_pin_30_[0]:3 0.0002005001 +4 cbx_1__0__1_top_grid_pin_30_[0]:4 0.0002030497 +5 cbx_1__0__1_top_grid_pin_30_[0]:5 0.0001578057 +6 cbx_2__0_:top_grid_pin_30_[0] cbx_2__0_:top_grid_pin_31_[0] 1.4987e-05 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_30_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 4.628832e-05 +8 cbx_1__0__1_top_grid_pin_30_[0]:4 cbx_2__0_:top_grid_pin_31_[0] 0.000143 +9 cbx_1__0__1_top_grid_pin_30_[0]:5 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 1.4987e-05 +10 cbx_1__0__1_top_grid_pin_30_[0]:3 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 0.000143 +11 cbx_1__0__1_top_grid_pin_30_[0]:2 cbx_2__0_:top_grid_pin_31_[0] 4.628832e-05 + +*RES +0 cbx_2__0_:top_grid_pin_30_[0] cbx_1__0__1_top_grid_pin_30_[0]:5 0.001883929 +1 cbx_1__0__1_top_grid_pin_30_[0]:4 cbx_1__0__1_top_grid_pin_30_[0]:3 0.004553572 +2 cbx_1__0__1_top_grid_pin_30_[0]:5 cbx_1__0__1_top_grid_pin_30_[0]:4 0.0004107143 +3 cbx_1__0__1_top_grid_pin_30_[0]:3 cbx_1__0__1_top_grid_pin_30_[0]:2 0.0004107143 +4 cbx_1__0__1_top_grid_pin_30_[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_30_[0] 0.003401786 + +*END + +*D_NET cbx_1__0__1_top_grid_pin_31_[0] 0.001345588 //LENGTH 11.020 LUMPCC 0.0007105921 DR + +*CONN +*I cbx_2__0_:top_grid_pin_31_[0] O *L 0 *C 744.280 369.850 +*I grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] I *L 0 *C 744.280 380.870 + +*CAP +0 cbx_2__0_:top_grid_pin_31_[0] 0.0003174978 +1 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 0.0003174978 +2 cbx_2__0_:top_grid_pin_31_[0] cbx_2__0_:top_grid_pin_29_[0] 0.0001510208 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_29_[0] 0.0001510208 +4 cbx_2__0_:top_grid_pin_31_[0] cbx_2__0_:top_grid_pin_30_[0] 1.4987e-05 +5 cbx_2__0_:top_grid_pin_31_[0] cbx_1__0__1_top_grid_pin_30_[0]:2 4.628832e-05 +6 cbx_2__0_:top_grid_pin_31_[0] cbx_1__0__1_top_grid_pin_30_[0]:4 0.000143 +7 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_30_[0] 4.628832e-05 +8 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] cbx_1__0__1_top_grid_pin_30_[0]:3 0.000143 +9 grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] cbx_1__0__1_top_grid_pin_30_[0]:5 1.4987e-05 + +*RES +0 cbx_2__0_:top_grid_pin_31_[0] grid_clb_2__1_:bottom_width_0_height_0__pin_31_[0] 0.009839286 + +*END + +*D_NET cbx_1__1__0_ccff_tail[0] 0.001196286 //LENGTH 7.660 LUMPCC 0.0004641715 DR + +*CONN +*I cbx_1__1_:ccff_tail[0] O *L 0 *C 407.710 616.080 +*I sb_0__1_:ccff_head[0] I *L 0 *C 400.050 616.080 + +*CAP +0 cbx_1__1_:ccff_tail[0] 0.0003660573 +1 sb_0__1_:ccff_head[0] 0.0003660573 +2 cbx_1__1_:ccff_tail[0] cbx_1__1_:chanx_left_in[13] 6.118615e-05 +3 sb_0__1_:ccff_head[0] sb_0__1_:chanx_right_out[13] 6.118615e-05 +4 cbx_1__1_:ccff_tail[0] cbx_1__1_:chanx_left_in[19] 0.0001708996 +5 sb_0__1_:ccff_head[0] sb_0__1_:chanx_right_out[19] 0.0001708996 + +*RES +0 cbx_1__1_:ccff_tail[0] sb_0__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[0] 0.004403692 //LENGTH 37.795 LUMPCC 0.001384929 DR + +*CONN +*I cbx_1__1_:chanx_left_out[0] O *L 0 *C 412.160 555.030 +*I sb_0__1_:chanx_right_in[0] I *L 0 *C 400.050 576.640 +*N cbx_1__1__0_chanx_left_out[0]:2 *C 403.873 576.640 +*N cbx_1__1__0_chanx_left_out[0]:3 *C 403.880 576.582 +*N cbx_1__1__0_chanx_left_out[0]:4 *C 403.880 553.577 +*N cbx_1__1__0_chanx_left_out[0]:5 *C 403.888 553.520 +*N cbx_1__1__0_chanx_left_out[0]:6 *C 412.140 553.520 +*N cbx_1__1__0_chanx_left_out[0]:7 *C 412.160 553.528 + +*CAP +0 cbx_1__1_:chanx_left_out[0] 9.12929e-05 +1 sb_0__1_:chanx_right_in[0] 0.0002278405 +2 cbx_1__1__0_chanx_left_out[0]:2 0.0002278405 +3 cbx_1__1__0_chanx_left_out[0]:3 0.0009007437 +4 cbx_1__1__0_chanx_left_out[0]:4 0.0009007437 +5 cbx_1__1__0_chanx_left_out[0]:5 0.0002895042 +6 cbx_1__1__0_chanx_left_out[0]:6 0.0002895042 +7 cbx_1__1__0_chanx_left_out[0]:7 9.12929e-05 +8 cbx_1__1__0_chanx_left_out[0]:6 cbx_1__1__0_chanx_left_out[3]:6 5.410738e-06 +9 cbx_1__1__0_chanx_left_out[0]:4 cbx_1__1__0_chanx_left_out[3]:4 0.000151621 +10 cbx_1__1__0_chanx_left_out[0]:5 cbx_1__1__0_chanx_left_out[3]:5 5.410738e-06 +11 cbx_1__1__0_chanx_left_out[0]:3 cbx_1__1__0_chanx_left_out[3]:3 0.000151621 +12 sb_0__1_:chanx_right_in[0] sb_0__1_:chanx_right_in[9] 4.054436e-05 +13 cbx_1__1__0_chanx_left_out[0]:2 cbx_1__1_:chanx_left_out[9] 4.054436e-05 +14 cbx_1__1__0_chanx_left_out[0]:6 cbx_1__1__0_chanx_left_out[11]:6 0.0002705261 +15 cbx_1__1__0_chanx_left_out[0]:5 cbx_1__1__0_chanx_left_out[11]:5 0.0002705261 +16 cbx_1__1__0_chanx_left_out[0]:4 cbx_1__1__0_chanx_left_out[13]:4 5.23926e-05 +17 cbx_1__1__0_chanx_left_out[0]:3 cbx_1__1__0_chanx_left_out[13]:3 5.23926e-05 +18 sb_0__1_:chanx_right_in[0] sb_0__1_:chanx_right_out[14] 7.709654e-05 +19 cbx_1__1__0_chanx_left_out[0]:2 cbx_1__1_:chanx_left_in[14] 7.709654e-05 +20 cbx_1__1__0_chanx_left_out[0]:6 ctsbuf_net_1928:37 9.487315e-05 +21 cbx_1__1__0_chanx_left_out[0]:5 ctsbuf_net_1928:38 9.487315e-05 + +*RES +0 cbx_1__1_:chanx_left_out[0] cbx_1__1__0_chanx_left_out[0]:7 0.0002353916 +1 cbx_1__1__0_chanx_left_out[0]:6 cbx_1__1__0_chanx_left_out[0]:5 0.001292892 +2 cbx_1__1__0_chanx_left_out[0]:7 cbx_1__1__0_chanx_left_out[0]:6 0.00341 +3 cbx_1__1__0_chanx_left_out[0]:4 cbx_1__1__0_chanx_left_out[0]:3 0.02054018 +4 cbx_1__1__0_chanx_left_out[0]:5 cbx_1__1__0_chanx_left_out[0]:4 0.00341 +5 cbx_1__1__0_chanx_left_out[0]:3 cbx_1__1__0_chanx_left_out[0]:2 0.00341 +6 cbx_1__1__0_chanx_left_out[0]:2 sb_0__1_:chanx_right_in[0] 0.0005988583 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[1] 0.001058797 //LENGTH 7.660 LUMPCC 0.0001935037 DR + +*CONN +*I cbx_1__1_:chanx_left_out[1] O *L 0 *C 407.710 626.960 +*I sb_0__1_:chanx_right_in[1] I *L 0 *C 400.050 626.960 + +*CAP +0 cbx_1__1_:chanx_left_out[1] 0.0004326465 +1 sb_0__1_:chanx_right_in[1] 0.0004326465 +2 cbx_1__1_:chanx_left_out[1] cbx_1__1_:chanx_left_out[12] 7.102055e-05 +3 sb_0__1_:chanx_right_in[1] sb_0__1_:chanx_right_in[12] 7.102055e-05 +4 cbx_1__1_:chanx_left_out[1] cbx_1__1__0_chanx_left_out[18]:6 2.573127e-05 +5 sb_0__1_:chanx_right_in[1] cbx_1__1__0_chanx_left_out[18]:5 2.573127e-05 + +*RES +0 cbx_1__1_:chanx_left_out[1] sb_0__1_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[2] 0.00114526 //LENGTH 7.660 LUMPCC 0.0004433002 DR + +*CONN +*I cbx_1__1_:chanx_left_out[2] O *L 0 *C 407.710 583.440 +*I sb_0__1_:chanx_right_in[2] I *L 0 *C 400.050 583.440 + +*CAP +0 cbx_1__1_:chanx_left_out[2] 0.00035098 +1 sb_0__1_:chanx_right_in[2] 0.00035098 +2 cbx_1__1_:chanx_left_out[2] cbx_1__1_:chanx_left_out[15] 0.0001742478 +3 sb_0__1_:chanx_right_in[2] sb_0__1_:chanx_right_in[15] 0.0001742478 +4 cbx_1__1_:chanx_left_out[2] cbx_1__1_:chanx_left_in[18] 4.740231e-05 +5 sb_0__1_:chanx_right_in[2] sb_0__1_:chanx_right_out[18] 4.740231e-05 + +*RES +0 cbx_1__1_:chanx_left_out[2] sb_0__1_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[3] 0.004029407 //LENGTH 36.290 LUMPCC 0.0007702014 DR + +*CONN +*I cbx_1__1_:chanx_left_out[3] O *L 0 *C 412.160 554.950 +*I sb_0__1_:chanx_right_in[3] I *L 0 *C 400.050 571.200 +*N cbx_1__1__0_chanx_left_out[3]:2 *C 405.252 571.200 +*N cbx_1__1__0_chanx_left_out[3]:3 *C 405.260 571.143 +*N cbx_1__1__0_chanx_left_out[3]:4 *C 405.260 551.525 +*N cbx_1__1__0_chanx_left_out[3]:5 *C 405.305 551.480 +*N cbx_1__1__0_chanx_left_out[3]:6 *C 412.115 551.480 +*N cbx_1__1__0_chanx_left_out[3]:7 *C 412.160 551.525 + +*CAP +0 cbx_1__1_:chanx_left_out[3] 0.0001905058 +1 sb_0__1_:chanx_right_in[3] 0.0002187406 +2 cbx_1__1__0_chanx_left_out[3]:2 0.0002187406 +3 cbx_1__1__0_chanx_left_out[3]:3 0.000802307 +4 cbx_1__1__0_chanx_left_out[3]:4 0.000802307 +5 cbx_1__1__0_chanx_left_out[3]:5 0.0004180496 +6 cbx_1__1__0_chanx_left_out[3]:6 0.0004180496 +7 cbx_1__1__0_chanx_left_out[3]:7 0.0001905058 +8 cbx_1__1__0_chanx_left_out[3]:6 cbx_1__1__0_chanx_left_out[0]:6 5.410738e-06 +9 cbx_1__1__0_chanx_left_out[3]:5 cbx_1__1__0_chanx_left_out[0]:5 5.410738e-06 +10 cbx_1__1__0_chanx_left_out[3]:4 cbx_1__1__0_chanx_left_out[0]:4 0.000151621 +11 cbx_1__1__0_chanx_left_out[3]:3 cbx_1__1__0_chanx_left_out[0]:3 0.000151621 +12 sb_0__1_:chanx_right_in[3] sb_0__1_:chanx_right_in[8] 0.0001140345 +13 cbx_1__1__0_chanx_left_out[3]:2 cbx_1__1_:chanx_left_out[8] 0.0001140345 +14 sb_0__1_:chanx_right_in[3] sb_0__1_:chanx_right_out[12] 0.0001140345 +15 cbx_1__1__0_chanx_left_out[3]:2 cbx_1__1_:chanx_left_in[12] 0.0001140345 + +*RES +0 cbx_1__1_:chanx_left_out[3] cbx_1__1__0_chanx_left_out[3]:7 0.003058035 +1 cbx_1__1__0_chanx_left_out[3]:6 cbx_1__1__0_chanx_left_out[3]:5 0.006080357 +2 cbx_1__1__0_chanx_left_out[3]:7 cbx_1__1__0_chanx_left_out[3]:6 0.0045 +3 cbx_1__1__0_chanx_left_out[3]:5 cbx_1__1__0_chanx_left_out[3]:4 0.0045 +4 cbx_1__1__0_chanx_left_out[3]:4 cbx_1__1__0_chanx_left_out[3]:3 0.01751563 +5 cbx_1__1__0_chanx_left_out[3]:3 cbx_1__1__0_chanx_left_out[3]:2 0.00341 +6 cbx_1__1__0_chanx_left_out[3]:2 sb_0__1_:chanx_right_in[3] 0.0008150584 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[4] 0.001178863 //LENGTH 7.660 LUMPCC 0.0004850243 DR + +*CONN +*I cbx_1__1_:chanx_left_out[4] O *L 0 *C 407.710 621.520 +*I sb_0__1_:chanx_right_in[4] I *L 0 *C 400.050 621.520 + +*CAP +0 cbx_1__1_:chanx_left_out[4] 0.0003469195 +1 sb_0__1_:chanx_right_in[4] 0.0003469195 +2 cbx_1__1_:chanx_left_out[4] cbx_1__1_:chanx_left_out[5] 0.0001701349 +3 sb_0__1_:chanx_right_in[4] sb_0__1_:chanx_right_in[5] 0.0001701349 +4 cbx_1__1_:chanx_left_out[4] cbx_1__1_:chanx_left_out[14] 7.23773e-05 +5 sb_0__1_:chanx_right_in[4] sb_0__1_:chanx_right_in[14] 7.23773e-05 + +*RES +0 cbx_1__1_:chanx_left_out[4] sb_0__1_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[5] 0.001265939 //LENGTH 7.660 LUMPCC 0.000677896 DR + +*CONN +*I cbx_1__1_:chanx_left_out[5] O *L 0 *C 407.710 622.880 +*I sb_0__1_:chanx_right_in[5] I *L 0 *C 400.050 622.880 + +*CAP +0 cbx_1__1_:chanx_left_out[5] 0.0002940214 +1 sb_0__1_:chanx_right_in[5] 0.0002940214 +2 cbx_1__1_:chanx_left_out[5] cbx_1__1_:chanx_left_out[4] 0.0001701349 +3 sb_0__1_:chanx_right_in[5] sb_0__1_:chanx_right_in[4] 0.0001701349 +4 cbx_1__1_:chanx_left_out[5] cbx_1__1_:chanx_left_out[12] 0.0001688131 +5 sb_0__1_:chanx_right_in[5] sb_0__1_:chanx_right_in[12] 0.0001688131 + +*RES +0 cbx_1__1_:chanx_left_out[5] sb_0__1_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[6] 0.001173804 //LENGTH 7.660 LUMPCC 0.0004282641 DR + +*CONN +*I cbx_1__1_:chanx_left_out[6] O *L 0 *C 407.710 605.200 +*I sb_0__1_:chanx_right_in[6] I *L 0 *C 400.050 605.200 + +*CAP +0 cbx_1__1_:chanx_left_out[6] 0.0003727698 +1 sb_0__1_:chanx_right_in[6] 0.0003727698 +2 cbx_1__1_:chanx_left_out[6] cbx_1__1_:chanx_left_in[3] 4.478417e-05 +3 sb_0__1_:chanx_right_in[6] sb_0__1_:chanx_right_out[3] 4.478417e-05 +4 cbx_1__1_:chanx_left_out[6] cbx_1__1_:chanx_left_in[11] 0.0001693479 +5 sb_0__1_:chanx_right_in[6] sb_0__1_:chanx_right_out[11] 0.0001693479 + +*RES +0 cbx_1__1_:chanx_left_out[6] sb_0__1_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[7] 0.00117926 //LENGTH 7.660 LUMPCC 0.0004884291 DR + +*CONN +*I cbx_1__1_:chanx_left_out[7] O *L 0 *C 407.710 597.040 +*I sb_0__1_:chanx_right_in[7] I *L 0 *C 400.050 597.040 + +*CAP +0 cbx_1__1_:chanx_left_out[7] 0.0003454152 +1 sb_0__1_:chanx_right_in[7] 0.0003454152 +2 cbx_1__1_:chanx_left_out[7] cbx_1__1_:chanx_left_in[5] 7.23773e-05 +3 sb_0__1_:chanx_right_in[7] sb_0__1_:chanx_right_out[5] 7.23773e-05 +4 cbx_1__1_:chanx_left_out[7] cbx_1__1_:chanx_left_in[15] 0.0001718373 +5 sb_0__1_:chanx_right_in[7] sb_0__1_:chanx_right_out[15] 0.0001718373 + +*RES +0 cbx_1__1_:chanx_left_out[7] sb_0__1_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[8] 0.0012295 //LENGTH 7.660 LUMPCC 0.0006393886 DR + +*CONN +*I cbx_1__1_:chanx_left_out[8] O *L 0 *C 407.710 572.560 +*I sb_0__1_:chanx_right_in[8] I *L 0 *C 400.050 572.560 + +*CAP +0 cbx_1__1_:chanx_left_out[8] 0.0002950558 +1 sb_0__1_:chanx_right_in[8] 0.0002950558 +2 cbx_1__1_:chanx_left_out[8] cbx_1__1__0_chanx_left_out[3]:2 0.0001140345 +3 sb_0__1_:chanx_right_in[8] sb_0__1_:chanx_right_in[3] 0.0001140345 +4 cbx_1__1_:chanx_left_out[8] cbx_1__1_:chanx_left_in[8] 0.0001727402 +5 sb_0__1_:chanx_right_in[8] sb_0__1_:chanx_right_out[8] 0.0001727402 +6 cbx_1__1_:chanx_left_out[8] cbx_1__1_:chanx_left_in[12] 3.291964e-05 +7 sb_0__1_:chanx_right_in[8] sb_0__1_:chanx_right_out[12] 3.291964e-05 + +*RES +0 cbx_1__1_:chanx_left_out[8] sb_0__1_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[9] 0.001170489 //LENGTH 7.660 LUMPCC 0.0004979624 DR + +*CONN +*I cbx_1__1_:chanx_left_out[9] O *L 0 *C 407.710 578.680 +*I sb_0__1_:chanx_right_in[9] I *L 0 *C 400.050 578.680 + +*CAP +0 cbx_1__1_:chanx_left_out[9] 0.0003362633 +1 sb_0__1_:chanx_right_in[9] 0.0003362633 +2 cbx_1__1_:chanx_left_out[9] cbx_1__1__0_chanx_left_out[0]:2 4.054436e-05 +3 sb_0__1_:chanx_right_in[9] sb_0__1_:chanx_right_in[0] 4.054436e-05 +4 cbx_1__1_:chanx_left_out[9] cbx_1__1_:chanx_left_in[14] 3.650287e-05 +5 sb_0__1_:chanx_right_in[9] sb_0__1_:chanx_right_out[14] 3.650287e-05 +6 cbx_1__1_:chanx_left_out[9] cbx_1__1_:chanx_left_in[18] 0.000171934 +7 sb_0__1_:chanx_right_in[9] sb_0__1_:chanx_right_out[18] 0.000171934 + +*RES +0 cbx_1__1_:chanx_left_out[9] sb_0__1_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[10] 0.001280324 //LENGTH 7.660 LUMPCC 0.0005140217 DR + +*CONN +*I cbx_1__1_:chanx_left_out[10] O *L 0 *C 407.710 564.400 +*I sb_0__1_:chanx_right_in[10] I *L 0 *C 400.050 564.400 + +*CAP +0 cbx_1__1_:chanx_left_out[10] 0.000383151 +1 sb_0__1_:chanx_right_in[10] 0.000383151 +2 cbx_1__1_:chanx_left_out[10] cbx_1__1__0_chanx_left_out[11]:2 7.414389e-05 +3 sb_0__1_:chanx_right_in[10] sb_0__1_:chanx_right_in[11] 7.414389e-05 +4 cbx_1__1_:chanx_left_out[10] cbx_1__1_:chanx_left_out[16] 3.258831e-05 +5 sb_0__1_:chanx_right_in[10] sb_0__1_:chanx_right_in[16] 3.258831e-05 +6 cbx_1__1_:chanx_left_out[10] cbx_1__1_:chanx_left_in[7] 0.0001502787 +7 sb_0__1_:chanx_right_in[10] sb_0__1_:chanx_right_out[7] 0.0001502787 + +*RES +0 cbx_1__1_:chanx_left_out[10] sb_0__1_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[11] 0.00391679 //LENGTH 26.400 LUMPCC 0.0008847954 DR + +*CONN +*I cbx_1__1_:chanx_left_out[11] O *L 0 *C 413.080 554.950 +*I sb_0__1_:chanx_right_in[11] I *L 0 *C 400.050 565.760 +*N cbx_1__1__0_chanx_left_out[11]:2 *C 403.860 565.760 +*N cbx_1__1__0_chanx_left_out[11]:3 *C 403.880 565.753 +*N cbx_1__1__0_chanx_left_out[11]:4 *C 403.880 554.207 +*N cbx_1__1__0_chanx_left_out[11]:5 *C 403.900 554.200 +*N cbx_1__1__0_chanx_left_out[11]:6 *C 413.073 554.200 +*N cbx_1__1__0_chanx_left_out[11]:7 *C 413.080 554.258 + +*CAP +0 cbx_1__1_:chanx_left_out[11] 5.623066e-05 +1 sb_0__1_:chanx_right_in[11] 0.0002060121 +2 cbx_1__1__0_chanx_left_out[11]:2 0.0002060121 +3 cbx_1__1__0_chanx_left_out[11]:3 0.0006308341 +4 cbx_1__1__0_chanx_left_out[11]:4 0.0006308341 +5 cbx_1__1__0_chanx_left_out[11]:5 0.0006229205 +6 cbx_1__1__0_chanx_left_out[11]:6 0.0006229205 +7 cbx_1__1__0_chanx_left_out[11]:7 5.623066e-05 +8 cbx_1__1__0_chanx_left_out[11]:6 cbx_1__1__0_chanx_left_out[0]:6 0.0002705261 +9 cbx_1__1__0_chanx_left_out[11]:5 cbx_1__1__0_chanx_left_out[0]:5 0.0002705261 +10 sb_0__1_:chanx_right_in[11] sb_0__1_:chanx_right_in[10] 7.414389e-05 +11 cbx_1__1__0_chanx_left_out[11]:2 cbx_1__1_:chanx_left_out[10] 7.414389e-05 +12 sb_0__1_:chanx_right_in[11] sb_0__1_:chanx_right_in[16] 7.564466e-05 +13 cbx_1__1__0_chanx_left_out[11]:2 cbx_1__1_:chanx_left_out[16] 7.564466e-05 +14 cbx_1__1__0_chanx_left_out[11]:6 cbx_1__1_:chanx_left_out[19] 2.208313e-05 +15 cbx_1__1__0_chanx_left_out[11]:5 sb_0__1_:chanx_right_in[19] 2.208313e-05 + +*RES +0 cbx_1__1_:chanx_left_out[11] cbx_1__1__0_chanx_left_out[11]:7 0.0006183035 +1 cbx_1__1__0_chanx_left_out[11]:7 cbx_1__1__0_chanx_left_out[11]:6 0.00341 +2 cbx_1__1__0_chanx_left_out[11]:6 cbx_1__1__0_chanx_left_out[11]:5 0.001437025 +3 cbx_1__1__0_chanx_left_out[11]:5 cbx_1__1__0_chanx_left_out[11]:4 0.00341 +4 cbx_1__1__0_chanx_left_out[11]:4 cbx_1__1__0_chanx_left_out[11]:3 0.001808717 +5 cbx_1__1__0_chanx_left_out[11]:2 sb_0__1_:chanx_right_in[11] 0.0005969 +6 cbx_1__1__0_chanx_left_out[11]:3 cbx_1__1__0_chanx_left_out[11]:2 0.00341 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[12] 0.001187432 //LENGTH 7.660 LUMPCC 0.0004796674 DR + +*CONN +*I cbx_1__1_:chanx_left_out[12] O *L 0 *C 407.710 624.240 +*I sb_0__1_:chanx_right_in[12] I *L 0 *C 400.050 624.240 + +*CAP +0 cbx_1__1_:chanx_left_out[12] 0.0003538821 +1 sb_0__1_:chanx_right_in[12] 0.0003538821 +2 cbx_1__1_:chanx_left_out[12] cbx_1__1_:chanx_left_out[1] 7.102055e-05 +3 sb_0__1_:chanx_right_in[12] sb_0__1_:chanx_right_in[1] 7.102055e-05 +4 cbx_1__1_:chanx_left_out[12] cbx_1__1_:chanx_left_out[5] 0.0001688131 +5 sb_0__1_:chanx_right_in[12] sb_0__1_:chanx_right_in[5] 0.0001688131 + +*RES +0 cbx_1__1_:chanx_left_out[12] sb_0__1_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[13] 0.002608306 //LENGTH 21.810 LUMPCC 0.0002848244 DR + +*CONN +*I cbx_1__1_:chanx_left_out[13] O *L 0 *C 414.000 554.950 +*I sb_0__1_:chanx_right_in[13] I *L 0 *C 400.050 560.320 +*N cbx_1__1__0_chanx_left_out[13]:2 *C 402.493 560.320 +*N cbx_1__1__0_chanx_left_out[13]:3 *C 402.500 560.263 +*N cbx_1__1__0_chanx_left_out[13]:4 *C 402.500 554.245 +*N cbx_1__1__0_chanx_left_out[13]:5 *C 402.545 554.200 +*N cbx_1__1__0_chanx_left_out[13]:6 *C 413.955 554.200 +*N cbx_1__1__0_chanx_left_out[13]:7 *C 414.000 554.245 + +*CAP +0 cbx_1__1_:chanx_left_out[13] 5.207646e-05 +1 sb_0__1_:chanx_right_in[13] 0.0001584232 +2 cbx_1__1__0_chanx_left_out[13]:2 0.0001584232 +3 cbx_1__1__0_chanx_left_out[13]:3 0.0002601377 +4 cbx_1__1__0_chanx_left_out[13]:4 0.0002601377 +5 cbx_1__1__0_chanx_left_out[13]:5 0.0006911036 +6 cbx_1__1__0_chanx_left_out[13]:6 0.0006911036 +7 cbx_1__1__0_chanx_left_out[13]:7 5.207646e-05 +8 cbx_1__1__0_chanx_left_out[13]:4 cbx_1__1__0_chanx_left_out[0]:4 5.23926e-05 +9 cbx_1__1__0_chanx_left_out[13]:3 cbx_1__1__0_chanx_left_out[0]:3 5.23926e-05 +10 sb_0__1_:chanx_right_in[13] sb_0__1_:chanx_right_in[17] 4.587459e-05 +11 cbx_1__1__0_chanx_left_out[13]:2 cbx_1__1_:chanx_left_out[17] 4.587459e-05 +12 sb_0__1_:chanx_right_in[13] sb_0__1_:chanx_right_in[19] 4.414502e-05 +13 cbx_1__1__0_chanx_left_out[13]:2 cbx_1__1_:chanx_left_out[19] 4.414502e-05 + +*RES +0 cbx_1__1_:chanx_left_out[13] cbx_1__1__0_chanx_left_out[13]:7 0.0006294643 +1 cbx_1__1__0_chanx_left_out[13]:6 cbx_1__1__0_chanx_left_out[13]:5 0.0101875 +2 cbx_1__1__0_chanx_left_out[13]:7 cbx_1__1__0_chanx_left_out[13]:6 0.0045 +3 cbx_1__1__0_chanx_left_out[13]:5 cbx_1__1__0_chanx_left_out[13]:4 0.0045 +4 cbx_1__1__0_chanx_left_out[13]:4 cbx_1__1__0_chanx_left_out[13]:3 0.005372768 +5 cbx_1__1__0_chanx_left_out[13]:3 cbx_1__1__0_chanx_left_out[13]:2 0.00341 +6 cbx_1__1__0_chanx_left_out[13]:2 sb_0__1_:chanx_right_in[13] 0.0003826583 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[14] 0.001173439 //LENGTH 7.660 LUMPCC 0.0004869974 DR + +*CONN +*I cbx_1__1_:chanx_left_out[14] O *L 0 *C 407.710 618.800 +*I sb_0__1_:chanx_right_in[14] I *L 0 *C 400.050 618.800 + +*CAP +0 cbx_1__1_:chanx_left_out[14] 0.0003432207 +1 sb_0__1_:chanx_right_in[14] 0.0003432207 +2 cbx_1__1_:chanx_left_out[14] cbx_1__1_:chanx_left_out[4] 7.23773e-05 +3 sb_0__1_:chanx_right_in[14] sb_0__1_:chanx_right_in[4] 7.23773e-05 +4 cbx_1__1_:chanx_left_out[14] cbx_1__1_:chanx_left_in[19] 0.0001711214 +5 sb_0__1_:chanx_right_in[14] sb_0__1_:chanx_right_out[19] 0.0001711214 + +*RES +0 cbx_1__1_:chanx_left_out[14] sb_0__1_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[15] 0.001251133 //LENGTH 7.660 LUMPCC 0.0006969911 DR + +*CONN +*I cbx_1__1_:chanx_left_out[15] O *L 0 *C 407.710 584.800 +*I sb_0__1_:chanx_right_in[15] I *L 0 *C 400.050 584.800 + +*CAP +0 cbx_1__1_:chanx_left_out[15] 0.0002770711 +1 sb_0__1_:chanx_right_in[15] 0.0002770711 +2 cbx_1__1_:chanx_left_out[15] cbx_1__1_:chanx_left_out[2] 0.0001742478 +3 sb_0__1_:chanx_right_in[15] sb_0__1_:chanx_right_in[2] 0.0001742478 +4 cbx_1__1_:chanx_left_out[15] cbx_1__1_:chanx_left_in[6] 0.0001742478 +5 sb_0__1_:chanx_right_in[15] sb_0__1_:chanx_right_out[6] 0.0001742478 + +*RES +0 cbx_1__1_:chanx_left_out[15] sb_0__1_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[16] 0.001237569 //LENGTH 7.660 LUMPCC 0.0005398993 DR + +*CONN +*I cbx_1__1_:chanx_left_out[16] O *L 0 *C 407.710 567.120 +*I sb_0__1_:chanx_right_in[16] I *L 0 *C 400.050 567.120 + +*CAP +0 cbx_1__1_:chanx_left_out[16] 0.0003488351 +1 sb_0__1_:chanx_right_in[16] 0.0003488351 +2 cbx_1__1_:chanx_left_out[16] cbx_1__1_:chanx_left_out[10] 3.258831e-05 +3 sb_0__1_:chanx_right_in[16] sb_0__1_:chanx_right_in[10] 3.258831e-05 +4 cbx_1__1_:chanx_left_out[16] cbx_1__1__0_chanx_left_out[11]:2 7.564466e-05 +5 sb_0__1_:chanx_right_in[16] sb_0__1_:chanx_right_in[11] 7.564466e-05 +6 cbx_1__1_:chanx_left_out[16] cbx_1__1_:chanx_left_in[16] 0.0001617167 +7 sb_0__1_:chanx_right_in[16] sb_0__1_:chanx_right_out[16] 0.0001617167 + +*RES +0 cbx_1__1_:chanx_left_out[16] sb_0__1_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[17] 0.001250222 //LENGTH 7.660 LUMPCC 0.0004969019 DR + +*CONN +*I cbx_1__1_:chanx_left_out[17] O *L 0 *C 407.710 561.680 +*I sb_0__1_:chanx_right_in[17] I *L 0 *C 400.050 561.680 + +*CAP +0 cbx_1__1_:chanx_left_out[17] 0.0003766601 +1 sb_0__1_:chanx_right_in[17] 0.0003766601 +2 cbx_1__1_:chanx_left_out[17] cbx_1__1__0_chanx_left_out[13]:2 4.587459e-05 +3 sb_0__1_:chanx_right_in[17] sb_0__1_:chanx_right_in[13] 4.587459e-05 +4 cbx_1__1_:chanx_left_out[17] cbx_1__1_:chanx_left_out[19] 4.733413e-05 +5 sb_0__1_:chanx_right_in[17] sb_0__1_:chanx_right_in[19] 4.733413e-05 +6 cbx_1__1_:chanx_left_out[17] cbx_1__1_:chanx_left_in[7] 0.0001552422 +7 sb_0__1_:chanx_right_in[17] sb_0__1_:chanx_right_out[7] 0.0001552422 + +*RES +0 cbx_1__1_:chanx_left_out[17] sb_0__1_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[18] 0.005149369 //LENGTH 51.290 LUMPCC 0.0003625322 DR + +*CONN +*I cbx_1__1_:chanx_left_out[18] O *L 0 *C 410.780 630.970 +*I sb_0__1_:chanx_right_in[18] I *L 0 *C 400.050 592.960 +*N cbx_1__1__0_chanx_left_out[18]:2 *C 403.873 592.960 +*N cbx_1__1__0_chanx_left_out[18]:3 *C 403.880 593.018 +*N cbx_1__1__0_chanx_left_out[18]:4 *C 403.880 631.663 +*N cbx_1__1__0_chanx_left_out[18]:5 *C 403.888 631.720 +*N cbx_1__1__0_chanx_left_out[18]:6 *C 410.773 631.720 +*N cbx_1__1__0_chanx_left_out[18]:7 *C 410.780 631.663 + +*CAP +0 cbx_1__1_:chanx_left_out[18] 7.272032e-05 +1 sb_0__1_:chanx_right_in[18] 0.0001974483 +2 cbx_1__1__0_chanx_left_out[18]:2 0.0001974483 +3 cbx_1__1__0_chanx_left_out[18]:3 0.001753947 +4 cbx_1__1__0_chanx_left_out[18]:4 0.001753947 +5 cbx_1__1__0_chanx_left_out[18]:5 0.0003693026 +6 cbx_1__1__0_chanx_left_out[18]:6 0.0003693026 +7 cbx_1__1__0_chanx_left_out[18]:7 7.272032e-05 +8 cbx_1__1__0_chanx_left_out[18]:6 cbx_1__1_:chanx_left_out[1] 2.573127e-05 +9 cbx_1__1__0_chanx_left_out[18]:5 sb_0__1_:chanx_right_in[1] 2.573127e-05 +10 sb_0__1_:chanx_right_in[18] sb_0__1_:chanx_right_out[9] 7.776741e-05 +11 cbx_1__1__0_chanx_left_out[18]:2 cbx_1__1_:chanx_left_in[9] 7.776741e-05 +12 sb_0__1_:chanx_right_in[18] sb_0__1_:chanx_right_out[17] 7.776741e-05 +13 cbx_1__1__0_chanx_left_out[18]:2 cbx_1__1_:chanx_left_in[17] 7.776741e-05 + +*RES +0 cbx_1__1_:chanx_left_out[18] cbx_1__1__0_chanx_left_out[18]:7 0.0006183035 +1 cbx_1__1__0_chanx_left_out[18]:7 cbx_1__1__0_chanx_left_out[18]:6 0.00341 +2 cbx_1__1__0_chanx_left_out[18]:6 cbx_1__1__0_chanx_left_out[18]:5 0.00107865 +3 cbx_1__1__0_chanx_left_out[18]:4 cbx_1__1__0_chanx_left_out[18]:3 0.03450447 +4 cbx_1__1__0_chanx_left_out[18]:5 cbx_1__1__0_chanx_left_out[18]:4 0.00341 +5 cbx_1__1__0_chanx_left_out[18]:3 cbx_1__1__0_chanx_left_out[18]:2 0.00341 +6 cbx_1__1__0_chanx_left_out[18]:2 sb_0__1_:chanx_right_in[18] 0.0005988583 + +*END + +*D_NET cbx_1__1__0_chanx_left_out[19] 0.001164724 //LENGTH 7.660 LUMPCC 0.0002271246 DR + +*CONN +*I cbx_1__1_:chanx_left_out[19] O *L 0 *C 407.710 558.960 +*I sb_0__1_:chanx_right_in[19] I *L 0 *C 400.050 558.960 + +*CAP +0 cbx_1__1_:chanx_left_out[19] 0.0004687995 +1 sb_0__1_:chanx_right_in[19] 0.0004687995 +2 cbx_1__1_:chanx_left_out[19] cbx_1__1__0_chanx_left_out[11]:6 2.208313e-05 +3 sb_0__1_:chanx_right_in[19] cbx_1__1__0_chanx_left_out[11]:5 2.208313e-05 +4 cbx_1__1_:chanx_left_out[19] cbx_1__1__0_chanx_left_out[13]:2 4.414502e-05 +5 sb_0__1_:chanx_right_in[19] sb_0__1_:chanx_right_in[13] 4.414502e-05 +6 cbx_1__1_:chanx_left_out[19] cbx_1__1_:chanx_left_out[17] 4.733413e-05 +7 sb_0__1_:chanx_right_in[19] sb_0__1_:chanx_right_in[17] 4.733413e-05 + +*RES +0 cbx_1__1_:chanx_left_out[19] sb_0__1_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[0] 0.001373082 //LENGTH 7.660 LUMPCC 0.0005716293 DR + +*CONN +*I cbx_1__1_:chanx_right_out[0] O *L 0 *C 512.290 603.840 +*I sb_1__1_:chanx_left_in[0] I *L 0 *C 519.950 603.840 + +*CAP +0 cbx_1__1_:chanx_right_out[0] 0.0004007265 +1 sb_1__1_:chanx_left_in[0] 0.0004007265 +2 cbx_1__1_:chanx_right_out[0] cbx_1__1_:chanx_right_out[15] 0.0001429073 +3 sb_1__1_:chanx_left_in[0] sb_1__1_:chanx_left_in[15] 0.0001429073 +4 cbx_1__1_:chanx_right_out[0] cbx_1__1_:chanx_right_in[3] 0.0001429073 +5 sb_1__1_:chanx_left_in[0] sb_1__1_:chanx_left_out[3] 0.0001429073 + +*RES +0 cbx_1__1_:chanx_right_out[0] sb_1__1_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[1] 0.001406958 //LENGTH 7.660 LUMPCC 0.0005344288 DR + +*CONN +*I cbx_1__1_:chanx_right_out[1] O *L 0 *C 512.290 565.760 +*I sb_1__1_:chanx_left_in[1] I *L 0 *C 519.950 565.760 + +*CAP +0 cbx_1__1_:chanx_right_out[1] 0.0004362648 +1 sb_1__1_:chanx_left_in[1] 0.0004362648 +2 cbx_1__1_:chanx_right_out[1] cbx_1__1_:chanx_right_out[3] 0.0001344401 +3 sb_1__1_:chanx_left_in[1] sb_1__1_:chanx_left_in[3] 0.0001344401 +4 cbx_1__1_:chanx_right_out[1] cbx_1__1_:chanx_right_out[11] 0.0001327743 +5 sb_1__1_:chanx_left_in[1] sb_1__1_:chanx_left_in[11] 0.0001327743 + +*RES +0 cbx_1__1_:chanx_right_out[1] sb_1__1_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[2] 0.002736112 //LENGTH 22.230 LUMPCC 0.0007327393 DR + +*CONN +*I cbx_1__1_:chanx_right_out[2] O *L 0 *C 508.300 554.950 +*I sb_1__1_:chanx_left_in[2] I *L 0 *C 519.950 563.040 +*N cbx_1__1__0_chanx_right_out[2]:2 *C 517.048 563.040 +*N cbx_1__1__0_chanx_right_out[2]:3 *C 517.040 562.983 +*N cbx_1__1__0_chanx_right_out[2]:4 *C 517.040 554.245 +*N cbx_1__1__0_chanx_right_out[2]:5 *C 516.995 554.200 +*N cbx_1__1__0_chanx_right_out[2]:6 *C 508.345 554.200 +*N cbx_1__1__0_chanx_right_out[2]:7 *C 508.300 554.245 + +*CAP +0 cbx_1__1_:chanx_right_out[2] 5.696427e-05 +1 sb_1__1_:chanx_left_in[2] 0.0001603649 +2 cbx_1__1__0_chanx_right_out[2]:2 0.0001603649 +3 cbx_1__1__0_chanx_right_out[2]:3 0.0002929903 +4 cbx_1__1__0_chanx_right_out[2]:4 0.0002929903 +5 cbx_1__1__0_chanx_right_out[2]:5 0.000491367 +6 cbx_1__1__0_chanx_right_out[2]:6 0.000491367 +7 cbx_1__1__0_chanx_right_out[2]:7 5.696427e-05 +8 sb_1__1_:chanx_left_in[2] sb_1__1_:chanx_left_in[6] 5.921805e-05 +9 cbx_1__1__0_chanx_right_out[2]:2 cbx_1__1_:chanx_right_out[6] 5.921805e-05 +10 sb_1__1_:chanx_left_in[2] sb_1__1_:chanx_left_in[11] 5.836838e-05 +11 cbx_1__1__0_chanx_right_out[2]:2 cbx_1__1_:chanx_right_out[11] 5.836838e-05 +12 cbx_1__1__0_chanx_right_out[2]:4 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] 0.0001238171 +13 cbx_1__1__0_chanx_right_out[2]:3 direct_interc_3_out[0]:2 0.0001238171 +14 cbx_1__1__0_chanx_right_out[2]:4 direct_interc_5_out[0]:24 4.971748e-05 +15 cbx_1__1__0_chanx_right_out[2]:3 direct_interc_5_out[0]:23 4.971748e-05 +16 cbx_1__1__0_chanx_right_out[2]:6 sb_1__1__0_chanx_left_out[15]:3 7.524867e-05 +17 cbx_1__1__0_chanx_right_out[2]:5 sb_1__1__0_chanx_left_out[15]:4 7.524867e-05 + +*RES +0 cbx_1__1_:chanx_right_out[2] cbx_1__1__0_chanx_right_out[2]:7 0.0006294643 +1 cbx_1__1__0_chanx_right_out[2]:6 cbx_1__1__0_chanx_right_out[2]:5 0.007723215 +2 cbx_1__1__0_chanx_right_out[2]:7 cbx_1__1__0_chanx_right_out[2]:6 0.0045 +3 cbx_1__1__0_chanx_right_out[2]:5 cbx_1__1__0_chanx_right_out[2]:4 0.0045 +4 cbx_1__1__0_chanx_right_out[2]:4 cbx_1__1__0_chanx_right_out[2]:3 0.00780134 +5 cbx_1__1__0_chanx_right_out[2]:3 cbx_1__1__0_chanx_right_out[2]:2 0.00341 +6 cbx_1__1__0_chanx_right_out[2]:2 sb_1__1_:chanx_left_in[2] 0.000454725 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[3] 0.001422173 //LENGTH 7.660 LUMPCC 0.0004782366 DR + +*CONN +*I cbx_1__1_:chanx_right_out[3] O *L 0 *C 512.290 567.120 +*I sb_1__1_:chanx_left_in[3] I *L 0 *C 519.950 567.120 + +*CAP +0 cbx_1__1_:chanx_right_out[3] 0.000471968 +1 sb_1__1_:chanx_left_in[3] 0.000471968 +2 cbx_1__1_:chanx_right_out[3] cbx_1__1_:chanx_right_out[1] 0.0001344401 +3 sb_1__1_:chanx_left_in[3] sb_1__1_:chanx_left_in[1] 0.0001344401 +4 cbx_1__1_:chanx_right_out[3] sb_1__1__0_chanx_left_out[15]:7 0.0001046782 +5 sb_1__1_:chanx_left_in[3] sb_1__1_:chanx_left_out[15] 0.0001046782 + +*RES +0 cbx_1__1_:chanx_right_out[3] sb_1__1_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[4] 0.00132653 //LENGTH 7.660 LUMPCC 0.0003824009 DR + +*CONN +*I cbx_1__1_:chanx_right_out[4] O *L 0 *C 512.290 613.360 +*I sb_1__1_:chanx_left_in[4] I *L 0 *C 519.950 613.360 + +*CAP +0 cbx_1__1_:chanx_right_out[4] 0.0004720645 +1 sb_1__1_:chanx_left_in[4] 0.0004720645 +2 cbx_1__1_:chanx_right_out[4] cbx_1__1_:chanx_right_out[5] 0.000145017 +3 sb_1__1_:chanx_left_in[4] sb_1__1_:chanx_left_in[5] 0.000145017 +4 cbx_1__1_:chanx_right_out[4] cbx_1__1_:chanx_right_in[2] 4.618341e-05 +5 sb_1__1_:chanx_left_in[4] sb_1__1_:chanx_left_out[2] 4.618341e-05 + +*RES +0 cbx_1__1_:chanx_right_out[4] sb_1__1_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[5] 0.001375372 //LENGTH 7.660 LUMPCC 0.0005785925 DR + +*CONN +*I cbx_1__1_:chanx_right_out[5] O *L 0 *C 512.290 614.720 +*I sb_1__1_:chanx_left_in[5] I *L 0 *C 519.950 614.720 + +*CAP +0 cbx_1__1_:chanx_right_out[5] 0.0003983897 +1 sb_1__1_:chanx_left_in[5] 0.0003983897 +2 cbx_1__1_:chanx_right_out[5] cbx_1__1_:chanx_right_out[4] 0.000145017 +3 sb_1__1_:chanx_left_in[5] sb_1__1_:chanx_left_in[4] 0.000145017 +4 cbx_1__1_:chanx_right_out[5] cbx_1__1_:chanx_right_in[17] 0.0001442792 +5 sb_1__1_:chanx_left_in[5] sb_1__1_:chanx_left_out[17] 0.0001442792 + +*RES +0 cbx_1__1_:chanx_right_out[5] sb_1__1_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[6] 0.001336011 //LENGTH 7.660 LUMPCC 0.000299684 DR + +*CONN +*I cbx_1__1_:chanx_right_out[6] O *L 0 *C 512.290 561.680 +*I sb_1__1_:chanx_left_in[6] I *L 0 *C 519.950 561.680 + +*CAP +0 cbx_1__1_:chanx_right_out[6] 0.0005181636 +1 sb_1__1_:chanx_left_in[6] 0.0005181636 +2 cbx_1__1_:chanx_right_out[6] cbx_1__1__0_chanx_right_out[2]:2 5.921805e-05 +3 sb_1__1_:chanx_left_in[6] sb_1__1_:chanx_left_in[2] 5.921805e-05 +4 cbx_1__1_:chanx_right_out[6] cbx_1__1_:chanx_right_out[11] 2.089426e-05 +5 sb_1__1_:chanx_left_in[6] sb_1__1_:chanx_left_in[11] 2.089426e-05 +6 cbx_1__1_:chanx_right_out[6] cbx_1__1_:chanx_right_in[16] 6.972968e-05 +7 sb_1__1_:chanx_left_in[6] sb_1__1_:chanx_left_out[16] 6.972968e-05 + +*RES +0 cbx_1__1_:chanx_right_out[6] sb_1__1_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[7] 0.00138306 //LENGTH 7.660 LUMPCC 0.0004944931 DR + +*CONN +*I cbx_1__1_:chanx_right_out[7] O *L 0 *C 512.290 569.840 +*I sb_1__1_:chanx_left_in[7] I *L 0 *C 519.950 569.840 + +*CAP +0 cbx_1__1_:chanx_right_out[7] 0.0004442837 +1 sb_1__1_:chanx_left_in[7] 0.0004442837 +2 cbx_1__1_:chanx_right_out[7] cbx_1__1_:chanx_right_out[8] 0.0001398553 +3 sb_1__1_:chanx_left_in[7] sb_1__1_:chanx_left_in[8] 0.0001398553 +4 cbx_1__1_:chanx_right_out[7] sb_1__1__0_chanx_left_out[15]:7 0.0001073912 +5 sb_1__1_:chanx_left_in[7] sb_1__1_:chanx_left_out[15] 0.0001073912 + +*RES +0 cbx_1__1_:chanx_right_out[7] sb_1__1_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[8] 0.001398157 //LENGTH 7.660 LUMPCC 0.0005594212 DR + +*CONN +*I cbx_1__1_:chanx_right_out[8] O *L 0 *C 512.290 571.200 +*I sb_1__1_:chanx_left_in[8] I *L 0 *C 519.950 571.200 + +*CAP +0 cbx_1__1_:chanx_right_out[8] 0.0004193678 +1 sb_1__1_:chanx_left_in[8] 0.0004193678 +2 cbx_1__1_:chanx_right_out[8] cbx_1__1_:chanx_right_out[7] 0.0001398553 +3 sb_1__1_:chanx_left_in[8] sb_1__1_:chanx_left_in[7] 0.0001398553 +4 cbx_1__1_:chanx_right_out[8] cbx_1__1_:chanx_right_in[12] 0.0001398553 +5 sb_1__1_:chanx_left_in[8] sb_1__1_:chanx_left_out[12] 0.0001398553 + +*RES +0 cbx_1__1_:chanx_right_out[8] sb_1__1_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[9] 0.001298336 //LENGTH 7.660 LUMPCC 0.0003891037 DR + +*CONN +*I cbx_1__1_:chanx_right_out[9] O *L 0 *C 512.290 599.760 +*I sb_1__1_:chanx_left_in[9] I *L 0 *C 519.950 599.760 + +*CAP +0 cbx_1__1_:chanx_right_out[9] 0.0004546161 +1 sb_1__1_:chanx_left_in[9] 0.0004546161 +2 cbx_1__1_:chanx_right_out[9] cbx_1__1_:chanx_right_in[3] 4.982339e-05 +3 sb_1__1_:chanx_left_in[9] sb_1__1_:chanx_left_out[3] 4.982339e-05 +4 cbx_1__1_:chanx_right_out[9] cbx_1__1_:chanx_right_in[18] 0.0001447284 +5 sb_1__1_:chanx_left_in[9] sb_1__1_:chanx_left_out[18] 0.0001447284 + +*RES +0 cbx_1__1_:chanx_right_out[9] sb_1__1_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[10] 0.001157876 //LENGTH 7.660 LUMPCC 0.0002473629 DR + +*CONN +*I cbx_1__1_:chanx_right_out[10] O *L 0 *C 512.290 586.840 +*I sb_1__1_:chanx_left_in[10] I *L 0 *C 519.950 586.840 + +*CAP +0 cbx_1__1_:chanx_right_out[10] 0.0004552564 +1 sb_1__1_:chanx_left_in[10] 0.0004552564 +2 cbx_1__1_:chanx_right_out[10] cbx_1__1__0_chanx_right_out[17]:4 2.329557e-05 +3 cbx_1__1_:chanx_right_out[10] cbx_1__1__0_chanx_right_out[17]:2 9.056761e-06 +4 sb_1__1_:chanx_left_in[10] sb_1__1_:chanx_left_in[17] 9.056761e-06 +5 sb_1__1_:chanx_left_in[10] cbx_1__1__0_chanx_right_out[17]:3 2.329557e-05 +6 cbx_1__1_:chanx_right_out[10] cbx_1__1_:chanx_right_in[0] 9.13291e-05 +7 sb_1__1_:chanx_left_in[10] sb_1__1_:chanx_left_out[0] 9.13291e-05 + +*RES +0 cbx_1__1_:chanx_right_out[10] sb_1__1_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[11] 0.001390351 //LENGTH 7.660 LUMPCC 0.0004240738 DR + +*CONN +*I cbx_1__1_:chanx_right_out[11] O *L 0 *C 512.290 564.400 +*I sb_1__1_:chanx_left_in[11] I *L 0 *C 519.950 564.400 + +*CAP +0 cbx_1__1_:chanx_right_out[11] 0.0004831386 +1 sb_1__1_:chanx_left_in[11] 0.0004831386 +2 cbx_1__1_:chanx_right_out[11] cbx_1__1_:chanx_right_out[1] 0.0001327743 +3 sb_1__1_:chanx_left_in[11] sb_1__1_:chanx_left_in[1] 0.0001327743 +4 cbx_1__1_:chanx_right_out[11] cbx_1__1__0_chanx_right_out[2]:2 5.836838e-05 +5 sb_1__1_:chanx_left_in[11] sb_1__1_:chanx_left_in[2] 5.836838e-05 +6 cbx_1__1_:chanx_right_out[11] cbx_1__1_:chanx_right_out[6] 2.089426e-05 +7 sb_1__1_:chanx_left_in[11] sb_1__1_:chanx_left_in[6] 2.089426e-05 + +*RES +0 cbx_1__1_:chanx_right_out[11] sb_1__1_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[12] 0.001372546 //LENGTH 7.660 LUMPCC 0.0005719297 DR + +*CONN +*I cbx_1__1_:chanx_right_out[12] O *L 0 *C 512.290 625.600 +*I sb_1__1_:chanx_left_in[12] I *L 0 *C 519.950 625.600 + +*CAP +0 cbx_1__1_:chanx_right_out[12] 0.0004003083 +1 sb_1__1_:chanx_left_in[12] 0.0004003083 +2 cbx_1__1_:chanx_right_out[12] cbx_1__1_:chanx_right_in[11] 0.0001429824 +3 sb_1__1_:chanx_left_in[12] sb_1__1_:chanx_left_out[11] 0.0001429824 +4 cbx_1__1_:chanx_right_out[12] cbx_1__1_:chanx_right_in[13] 0.0001429824 +5 sb_1__1_:chanx_left_in[12] sb_1__1_:chanx_left_out[13] 0.0001429824 + +*RES +0 cbx_1__1_:chanx_right_out[12] sb_1__1_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[13] 0.001328219 //LENGTH 7.660 LUMPCC 0.0003696789 DR + +*CONN +*I cbx_1__1_:chanx_right_out[13] O *L 0 *C 512.290 621.520 +*I sb_1__1_:chanx_left_in[13] I *L 0 *C 519.950 621.520 + +*CAP +0 cbx_1__1_:chanx_right_out[13] 0.0004792703 +1 sb_1__1_:chanx_left_in[13] 0.0004792703 +2 cbx_1__1_:chanx_right_out[13] cbx_1__1_:chanx_right_out[14] 0.0001399578 +3 sb_1__1_:chanx_left_in[13] sb_1__1_:chanx_left_in[14] 0.0001399578 +4 cbx_1__1_:chanx_right_out[13] cbx_1__1_:chanx_right_in[11] 4.488169e-05 +5 sb_1__1_:chanx_left_in[13] sb_1__1_:chanx_left_out[11] 4.488169e-05 + +*RES +0 cbx_1__1_:chanx_right_out[13] sb_1__1_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[14] 0.001377194 //LENGTH 7.660 LUMPCC 0.0005693304 DR + +*CONN +*I cbx_1__1_:chanx_right_out[14] O *L 0 *C 512.290 620.160 +*I sb_1__1_:chanx_left_in[14] I *L 0 *C 519.950 620.160 + +*CAP +0 cbx_1__1_:chanx_right_out[14] 0.000403932 +1 sb_1__1_:chanx_left_in[14] 0.000403932 +2 cbx_1__1_:chanx_right_out[14] cbx_1__1_:chanx_right_out[13] 0.0001399578 +3 sb_1__1_:chanx_left_in[14] sb_1__1_:chanx_left_in[13] 0.0001399578 +4 cbx_1__1_:chanx_right_out[14] cbx_1__1_:chanx_right_in[19] 0.0001447074 +5 sb_1__1_:chanx_left_in[14] sb_1__1_:chanx_left_out[19] 0.0001447074 + +*RES +0 cbx_1__1_:chanx_right_out[14] sb_1__1_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[15] 0.001320636 //LENGTH 7.660 LUMPCC 0.0003842977 DR + +*CONN +*I cbx_1__1_:chanx_right_out[15] O *L 0 *C 512.290 605.200 +*I sb_1__1_:chanx_left_in[15] I *L 0 *C 519.950 605.200 + +*CAP +0 cbx_1__1_:chanx_right_out[15] 0.000468169 +1 sb_1__1_:chanx_left_in[15] 0.000468169 +2 cbx_1__1_:chanx_right_out[15] cbx_1__1_:chanx_right_out[0] 0.0001429073 +3 sb_1__1_:chanx_left_in[15] sb_1__1_:chanx_left_in[0] 0.0001429073 +4 cbx_1__1_:chanx_right_out[15] cbx_1__1_:chanx_right_in[4] 4.924156e-05 +5 sb_1__1_:chanx_left_in[15] sb_1__1_:chanx_left_out[4] 4.924156e-05 + +*RES +0 cbx_1__1_:chanx_right_out[15] sb_1__1_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[16] 0.00555857 //LENGTH 45.860 LUMPCC 0.001134123 DR + +*CONN +*I cbx_1__1_:chanx_right_out[16] O *L 0 *C 509.220 554.950 +*I sb_1__1_:chanx_left_in[16] I *L 0 *C 519.950 579.360 +*N cbx_1__1__0_chanx_right_out[16]:2 *C 515.220 579.360 +*N cbx_1__1__0_chanx_right_out[16]:3 *C 515.200 579.353 +*N cbx_1__1__0_chanx_right_out[16]:4 *C 515.200 550.128 +*N cbx_1__1__0_chanx_right_out[16]:5 *C 515.180 550.120 +*N cbx_1__1__0_chanx_right_out[16]:6 *C 509.228 550.120 +*N cbx_1__1__0_chanx_right_out[16]:7 *C 509.220 550.178 + +*CAP +0 cbx_1__1_:chanx_right_out[16] 0.0002723644 +1 sb_1__1_:chanx_left_in[16] 0.0001760878 +2 cbx_1__1__0_chanx_right_out[16]:2 0.0001760878 +3 cbx_1__1__0_chanx_right_out[16]:3 0.001499585 +4 cbx_1__1__0_chanx_right_out[16]:4 0.001499585 +5 cbx_1__1__0_chanx_right_out[16]:5 0.0002641861 +6 cbx_1__1__0_chanx_right_out[16]:6 0.0002641861 +7 cbx_1__1__0_chanx_right_out[16]:7 0.0002723644 +8 cbx_1__1__0_chanx_right_out[16]:4 cbx_1__1__0_chanx_right_out[19]:4 0.0002392006 +9 cbx_1__1__0_chanx_right_out[16]:3 cbx_1__1__0_chanx_right_out[19]:3 0.0002392006 +10 sb_1__1_:chanx_left_in[16] sb_1__1_:chanx_left_out[6] 0.0001105525 +11 cbx_1__1__0_chanx_right_out[16]:2 cbx_1__1_:chanx_right_in[6] 0.0001105525 +12 sb_1__1_:chanx_left_in[16] sb_1__1_:chanx_left_out[10] 0.0001112282 +13 cbx_1__1__0_chanx_right_out[16]:2 cbx_1__1_:chanx_right_in[10] 0.0001112282 +14 cbx_1__1__0_chanx_right_out[16]:6 ctsbuf_net_1928:30 0.0001060801 +15 cbx_1__1__0_chanx_right_out[16]:5 ctsbuf_net_1928:29 0.0001060801 + +*RES +0 cbx_1__1_:chanx_right_out[16] cbx_1__1__0_chanx_right_out[16]:7 0.004261161 +1 cbx_1__1__0_chanx_right_out[16]:7 cbx_1__1__0_chanx_right_out[16]:6 0.00341 +2 cbx_1__1__0_chanx_right_out[16]:6 cbx_1__1__0_chanx_right_out[16]:5 0.0009325583 +3 cbx_1__1__0_chanx_right_out[16]:5 cbx_1__1__0_chanx_right_out[16]:4 0.00341 +4 cbx_1__1__0_chanx_right_out[16]:4 cbx_1__1__0_chanx_right_out[16]:3 0.004578583 +5 cbx_1__1__0_chanx_right_out[16]:2 sb_1__1_:chanx_left_in[16] 0.0007410333 +6 cbx_1__1__0_chanx_right_out[16]:3 cbx_1__1__0_chanx_right_out[16]:2 0.00341 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[17] 0.001985807 //LENGTH 10.220 LUMPCC 0.0008224313 DR + +*CONN +*I cbx_1__1_:chanx_right_out[17] O *L 0 *C 512.290 583.440 +*I sb_1__1_:chanx_left_in[17] I *L 0 *C 519.950 583.440 +*N cbx_1__1__0_chanx_right_out[17]:2 *C 518.880 583.440 +*N cbx_1__1__0_chanx_right_out[17]:3 *C 518.880 582.760 +*N cbx_1__1__0_chanx_right_out[17]:4 *C 513.360 582.760 +*N cbx_1__1__0_chanx_right_out[17]:5 *C 513.360 583.440 + +*CAP +0 cbx_1__1_:chanx_right_out[17] 0.0001493759 +1 sb_1__1_:chanx_left_in[17] 0.0001324003 +2 cbx_1__1__0_chanx_right_out[17]:2 0.0001608795 +3 cbx_1__1__0_chanx_right_out[17]:3 0.000254767 +4 cbx_1__1__0_chanx_right_out[17]:4 0.0002714322 +5 cbx_1__1__0_chanx_right_out[17]:5 0.0001945204 +6 sb_1__1_:chanx_left_in[17] sb_1__1_:chanx_left_in[10] 9.056761e-06 +7 cbx_1__1__0_chanx_right_out[17]:4 cbx_1__1_:chanx_right_out[10] 2.329557e-05 +8 cbx_1__1__0_chanx_right_out[17]:3 sb_1__1_:chanx_left_in[10] 2.329557e-05 +9 cbx_1__1__0_chanx_right_out[17]:2 cbx_1__1_:chanx_right_out[10] 9.056761e-06 +10 cbx_1__1__0_chanx_right_out[17]:5 direct_interc_0_out[0]:2 2.098518e-05 +11 cbx_1__1__0_chanx_right_out[17]:4 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 2.098518e-05 +12 cbx_1__1__0_chanx_right_out[17]:3 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 2.053743e-05 +13 cbx_1__1__0_chanx_right_out[17]:2 direct_interc_0_out[0]:2 2.053743e-05 +14 cbx_1__1_:chanx_right_out[17] cbx_1__1_:chanx_right_in[14] 6.378637e-06 +15 sb_1__1_:chanx_left_in[17] sb_1__1_:chanx_left_out[14] 3.388373e-06 +16 cbx_1__1__0_chanx_right_out[17]:5 sb_1__1_:chanx_left_out[14] 6.378637e-06 +17 cbx_1__1__0_chanx_right_out[17]:4 cbx_1__1_:chanx_right_in[14] 0.0003275737 +18 cbx_1__1__0_chanx_right_out[17]:3 sb_1__1_:chanx_left_out[14] 0.0003275737 +19 cbx_1__1__0_chanx_right_out[17]:2 cbx_1__1_:chanx_right_in[14] 3.388373e-06 + +*RES +0 cbx_1__1_:chanx_right_out[17] cbx_1__1__0_chanx_right_out[17]:5 0.0001676333 +1 cbx_1__1__0_chanx_right_out[17]:5 cbx_1__1__0_chanx_right_out[17]:4 0.0001065333 +2 cbx_1__1__0_chanx_right_out[17]:4 cbx_1__1__0_chanx_right_out[17]:3 0.0008647999 +3 cbx_1__1__0_chanx_right_out[17]:3 cbx_1__1__0_chanx_right_out[17]:2 0.0001065333 +4 cbx_1__1__0_chanx_right_out[17]:2 sb_1__1_:chanx_left_in[17] 0.0001676333 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[18] 0.005554583 //LENGTH 49.020 LUMPCC 0.0002363757 DR + +*CONN +*I cbx_1__1_:chanx_right_out[18] O *L 0 *C 510.140 630.970 +*I sb_1__1_:chanx_left_in[18] I *L 0 *C 519.950 595.680 +*N cbx_1__1__0_chanx_right_out[18]:2 *C 517.060 595.680 +*N cbx_1__1__0_chanx_right_out[18]:3 *C 517.040 595.688 +*N cbx_1__1__0_chanx_right_out[18]:4 *C 517.040 632.393 +*N cbx_1__1__0_chanx_right_out[18]:5 *C 517.020 632.400 +*N cbx_1__1__0_chanx_right_out[18]:6 *C 510.148 632.400 +*N cbx_1__1__0_chanx_right_out[18]:7 *C 510.140 632.343 + +*CAP +0 cbx_1__1_:chanx_right_out[18] 8.993295e-05 +1 sb_1__1_:chanx_left_in[18] 0.0001278053 +2 cbx_1__1__0_chanx_right_out[18]:2 0.0001278053 +3 cbx_1__1__0_chanx_right_out[18]:3 0.002066258 +4 cbx_1__1__0_chanx_right_out[18]:4 0.002066258 +5 cbx_1__1__0_chanx_right_out[18]:5 0.0003751073 +6 cbx_1__1__0_chanx_right_out[18]:6 0.0003751073 +7 cbx_1__1__0_chanx_right_out[18]:7 8.993295e-05 +8 sb_1__1_:chanx_left_in[18] sb_1__1_:chanx_left_out[7] 4.769616e-05 +9 cbx_1__1__0_chanx_right_out[18]:2 cbx_1__1_:chanx_right_in[7] 4.769616e-05 +10 sb_1__1_:chanx_left_in[18] sb_1__1_:chanx_left_out[9] 7.049166e-05 +11 cbx_1__1__0_chanx_right_out[18]:2 cbx_1__1_:chanx_right_in[9] 7.049166e-05 + +*RES +0 cbx_1__1_:chanx_right_out[18] cbx_1__1__0_chanx_right_out[18]:7 0.001225446 +1 cbx_1__1__0_chanx_right_out[18]:7 cbx_1__1__0_chanx_right_out[18]:6 0.00341 +2 cbx_1__1__0_chanx_right_out[18]:6 cbx_1__1__0_chanx_right_out[18]:5 0.001076692 +3 cbx_1__1__0_chanx_right_out[18]:5 cbx_1__1__0_chanx_right_out[18]:4 0.00341 +4 cbx_1__1__0_chanx_right_out[18]:4 cbx_1__1__0_chanx_right_out[18]:3 0.00575045 +5 cbx_1__1__0_chanx_right_out[18]:2 sb_1__1_:chanx_left_in[18] 0.0004527667 +6 cbx_1__1__0_chanx_right_out[18]:3 cbx_1__1__0_chanx_right_out[18]:2 0.00341 + +*END + +*D_NET cbx_1__1__0_chanx_right_out[19] 0.004363081 //LENGTH 33.725 LUMPCC 0.0008449655 DR + +*CONN +*I cbx_1__1_:chanx_right_out[19] O *L 0 *C 507.840 555.030 +*I sb_1__1_:chanx_left_in[19] I *L 0 *C 519.950 573.920 +*N cbx_1__1__0_chanx_right_out[19]:2 *C 517.980 573.920 +*N cbx_1__1__0_chanx_right_out[19]:3 *C 517.960 573.913 +*N cbx_1__1__0_chanx_right_out[19]:4 *C 517.960 554.207 +*N cbx_1__1__0_chanx_right_out[19]:5 *C 517.940 554.200 +*N cbx_1__1__0_chanx_right_out[19]:6 *C 507.860 554.200 +*N cbx_1__1__0_chanx_right_out[19]:7 *C 507.840 554.207 + +*CAP +0 cbx_1__1_:chanx_right_out[19] 7.482506e-05 +1 sb_1__1_:chanx_left_in[19] 0.0001159582 +2 cbx_1__1__0_chanx_right_out[19]:2 0.0001159582 +3 cbx_1__1__0_chanx_right_out[19]:3 0.0009707318 +4 cbx_1__1__0_chanx_right_out[19]:4 0.0009707318 +5 cbx_1__1__0_chanx_right_out[19]:5 0.0005975429 +6 cbx_1__1__0_chanx_right_out[19]:6 0.0005975429 +7 cbx_1__1__0_chanx_right_out[19]:7 7.482506e-05 +8 cbx_1__1__0_chanx_right_out[19]:4 cbx_1__1__0_chanx_right_out[16]:4 0.0002392006 +9 cbx_1__1__0_chanx_right_out[19]:3 cbx_1__1__0_chanx_right_out[16]:3 0.0002392006 +10 sb_1__1_:chanx_left_in[19] sb_1__1_:chanx_left_out[5] 4.434828e-05 +11 cbx_1__1__0_chanx_right_out[19]:2 cbx_1__1_:chanx_right_in[5] 4.434828e-05 +12 sb_1__1_:chanx_left_in[19] sb_1__1_:chanx_left_out[12] 4.232395e-05 +13 cbx_1__1__0_chanx_right_out[19]:2 cbx_1__1_:chanx_right_in[12] 4.232395e-05 +14 cbx_1__1__0_chanx_right_out[19]:6 ctsbuf_net_1928:30 9.660986e-05 +15 cbx_1__1__0_chanx_right_out[19]:5 ctsbuf_net_1928:29 9.660986e-05 + +*RES +0 cbx_1__1_:chanx_right_out[19] cbx_1__1__0_chanx_right_out[19]:7 0.0001288583 +1 cbx_1__1__0_chanx_right_out[19]:6 cbx_1__1__0_chanx_right_out[19]:5 0.0015792 +2 cbx_1__1__0_chanx_right_out[19]:7 cbx_1__1__0_chanx_right_out[19]:6 0.00341 +3 cbx_1__1__0_chanx_right_out[19]:5 cbx_1__1__0_chanx_right_out[19]:4 0.00341 +4 cbx_1__1__0_chanx_right_out[19]:4 cbx_1__1__0_chanx_right_out[19]:3 0.003087116 +5 cbx_1__1__0_chanx_right_out[19]:2 sb_1__1_:chanx_left_in[19] 0.0003086333 +6 cbx_1__1__0_chanx_right_out[19]:3 cbx_1__1__0_chanx_right_out[19]:2 0.00341 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_16_[0] 0.0012516 //LENGTH 11.020 LUMPCC 0.0005632483 DR + +*CONN +*I cbx_1__1_:top_grid_pin_16_[0] O *L 0 *C 441.600 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] I *L 0 *C 441.600 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_16_[0] 0.000344176 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] 0.000344176 +2 cbx_1__1_:top_grid_pin_16_[0] cbx_1__1_:top_grid_pin_18_[0] 0.0001408121 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] 0.0001408121 +4 cbx_1__1_:top_grid_pin_16_[0] cbx_1__1_:top_grid_pin_22_[0] 0.0001408121 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_22_[0] 0.0001408121 + +*RES +0 cbx_1__1_:top_grid_pin_16_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_17_[0] 0.001251604 //LENGTH 11.020 LUMPCC 0.0005632483 DR + +*CONN +*I cbx_1__1_:top_grid_pin_17_[0] O *L 0 *C 443.440 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] I *L 0 *C 443.440 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_17_[0] 0.0003441778 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] 0.0003441778 +2 cbx_1__1_:top_grid_pin_17_[0] cbx_1__1_:top_grid_pin_18_[0] 0.0001408121 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] 0.0001408121 +4 cbx_1__1_:top_grid_pin_17_[0] cbx_1__1_:top_grid_pin_19_[0] 0.0001408121 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_19_[0] 0.0001408121 + +*RES +0 cbx_1__1_:top_grid_pin_17_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_18_[0] 0.001251535 //LENGTH 11.020 LUMPCC 0.0005632483 DR + +*CONN +*I cbx_1__1_:top_grid_pin_18_[0] O *L 0 *C 442.520 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] I *L 0 *C 442.520 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_18_[0] 0.0003441431 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] 0.0003441431 +2 cbx_1__1_:top_grid_pin_18_[0] cbx_1__1_:top_grid_pin_16_[0] 0.0001408121 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] 0.0001408121 +4 cbx_1__1_:top_grid_pin_18_[0] cbx_1__1_:top_grid_pin_17_[0] 0.0001408121 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] 0.0001408121 + +*RES +0 cbx_1__1_:top_grid_pin_18_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_18_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_19_[0] 0.001155747 //LENGTH 11.020 LUMPCC 0.0002816241 DR + +*CONN +*I cbx_1__1_:top_grid_pin_19_[0] O *L 0 *C 444.360 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_19_[0] I *L 0 *C 444.360 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_19_[0] 0.0004370612 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_19_[0] 0.0004370612 +2 cbx_1__1_:top_grid_pin_19_[0] cbx_1__1_:top_grid_pin_17_[0] 0.0001408121 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_19_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_17_[0] 0.0001408121 + +*RES +0 cbx_1__1_:top_grid_pin_19_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_19_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_20_[0] 0.00106039 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__1_:top_grid_pin_20_[0] O *L 0 *C 465.060 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_20_[0] I *L 0 *C 465.060 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_20_[0] 0.000530195 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_20_[0] 0.000530195 + +*RES +0 cbx_1__1_:top_grid_pin_20_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_20_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_21_[0] 0.001179002 //LENGTH 11.020 LUMPCC 0.0002818653 DR + +*CONN +*I cbx_1__1_:top_grid_pin_21_[0] O *L 0 *C 423.660 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_21_[0] I *L 0 *C 423.660 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_21_[0] 0.0004485684 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_21_[0] 0.0004485684 +2 cbx_1__1_:top_grid_pin_21_[0] cbx_1__1_:top_grid_pin_23_[0] 0.0001409327 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_21_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] 0.0001409327 + +*RES +0 cbx_1__1_:top_grid_pin_21_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_21_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_22_[0] 0.001166118 //LENGTH 11.020 LUMPCC 0.0002816241 DR + +*CONN +*I cbx_1__1_:top_grid_pin_22_[0] O *L 0 *C 440.680 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_22_[0] I *L 0 *C 440.680 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_22_[0] 0.0004422471 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_22_[0] 0.0004422471 +2 cbx_1__1_:top_grid_pin_22_[0] cbx_1__1_:top_grid_pin_16_[0] 0.0001408121 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_22_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_16_[0] 0.0001408121 + +*RES +0 cbx_1__1_:top_grid_pin_22_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_22_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_23_[0] 0.001258339 //LENGTH 11.020 LUMPCC 0.0005637307 DR + +*CONN +*I cbx_1__1_:top_grid_pin_23_[0] O *L 0 *C 422.740 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] I *L 0 *C 422.740 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_23_[0] 0.0003473042 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] 0.0003473042 +2 cbx_1__1_:top_grid_pin_23_[0] cbx_1__1_:top_grid_pin_21_[0] 0.0001409327 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_21_[0] 0.0001409327 +4 cbx_1__1_:top_grid_pin_23_[0] cbx_1__1_:top_grid_pin_27_[0] 0.0001409327 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] 0.0001409327 + +*RES +0 cbx_1__1_:top_grid_pin_23_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_24_[0] 0.001095339 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__1_:top_grid_pin_24_[0] O *L 0 *C 409.860 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_24_[0] I *L 0 *C 409.860 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_24_[0] 0.0005476697 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_24_[0] 0.0005476697 + +*RES +0 cbx_1__1_:top_grid_pin_24_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_24_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_25_[0] 0.001171699 //LENGTH 11.020 LUMPCC 0.0002810394 DR + +*CONN +*I cbx_1__1_:top_grid_pin_25_[0] O *L 0 *C 419.980 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_25_[0] I *L 0 *C 419.980 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_25_[0] 0.0004453297 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_25_[0] 0.0004453297 +2 cbx_1__1_:top_grid_pin_25_[0] cbx_1__1_:top_grid_pin_26_[0] 0.0001405197 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_25_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] 0.0001405197 + +*RES +0 cbx_1__1_:top_grid_pin_25_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_25_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_26_[0] 0.0012551 //LENGTH 11.020 LUMPCC 0.0005620788 DR + +*CONN +*I cbx_1__1_:top_grid_pin_26_[0] O *L 0 *C 420.900 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] I *L 0 *C 420.900 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_26_[0] 0.0003465105 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] 0.0003465105 +2 cbx_1__1_:top_grid_pin_26_[0] cbx_1__1_:top_grid_pin_25_[0] 0.0001405197 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_25_[0] 0.0001405197 +4 cbx_1__1_:top_grid_pin_26_[0] cbx_1__1_:top_grid_pin_27_[0] 0.0001405197 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] 0.0001405197 + +*RES +0 cbx_1__1_:top_grid_pin_26_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_27_[0] 0.001258268 //LENGTH 11.020 LUMPCC 0.0005629048 DR + +*CONN +*I cbx_1__1_:top_grid_pin_27_[0] O *L 0 *C 421.820 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] I *L 0 *C 421.820 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_27_[0] 0.0003476815 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] 0.0003476815 +2 cbx_1__1_:top_grid_pin_27_[0] cbx_1__1_:top_grid_pin_23_[0] 0.0001409327 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_23_[0] 0.0001409327 +4 cbx_1__1_:top_grid_pin_27_[0] cbx_1__1_:top_grid_pin_26_[0] 0.0001405197 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_26_[0] 0.0001405197 + +*RES +0 cbx_1__1_:top_grid_pin_27_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_27_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_28_[0] 0.001168059 //LENGTH 11.020 LUMPCC 0.0002861042 DR + +*CONN +*I cbx_1__1_:top_grid_pin_28_[0] O *L 0 *C 481.160 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_28_[0] I *L 0 *C 481.160 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_28_[0] 0.0004409776 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_28_[0] 0.0004409776 +2 cbx_1__1_:top_grid_pin_28_[0] cbx_1__1_:top_grid_pin_29_[0] 0.0001430521 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_28_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] 0.0001430521 + +*RES +0 cbx_1__1_:top_grid_pin_28_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_28_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_29_[0] 0.001246707 //LENGTH 11.020 LUMPCC 0.0005722084 DR + +*CONN +*I cbx_1__1_:top_grid_pin_29_[0] O *L 0 *C 482.080 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] I *L 0 *C 482.080 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_29_[0] 0.0003372493 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] 0.0003372493 +2 cbx_1__1_:top_grid_pin_29_[0] cbx_1__1_:top_grid_pin_28_[0] 0.0001430521 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_28_[0] 0.0001430521 +4 cbx_1__1_:top_grid_pin_29_[0] cbx_1__1_:top_grid_pin_31_[0] 0.0001430521 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] 0.0001430521 + +*RES +0 cbx_1__1_:top_grid_pin_29_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_30_[0] 0.001153152 //LENGTH 11.020 LUMPCC 0.0002861042 DR + +*CONN +*I cbx_1__1_:top_grid_pin_30_[0] O *L 0 *C 483.920 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_30_[0] I *L 0 *C 483.920 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_30_[0] 0.0004335238 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_30_[0] 0.0004335238 +2 cbx_1__1_:top_grid_pin_30_[0] cbx_1__1_:top_grid_pin_31_[0] 0.0001430521 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_30_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] 0.0001430521 + +*RES +0 cbx_1__1_:top_grid_pin_30_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_30_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__0_top_grid_pin_31_[0] 0.001246707 //LENGTH 11.020 LUMPCC 0.0005722084 DR + +*CONN +*I cbx_1__1_:top_grid_pin_31_[0] O *L 0 *C 483.000 630.970 +*I grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] I *L 0 *C 483.000 641.990 + +*CAP +0 cbx_1__1_:top_grid_pin_31_[0] 0.0003372493 +1 grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] 0.0003372493 +2 cbx_1__1_:top_grid_pin_31_[0] cbx_1__1_:top_grid_pin_29_[0] 0.0001430521 +3 grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_29_[0] 0.0001430521 +4 cbx_1__1_:top_grid_pin_31_[0] cbx_1__1_:top_grid_pin_30_[0] 0.0001430521 +5 grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_30_[0] 0.0001430521 + +*RES +0 cbx_1__1_:top_grid_pin_31_[0] grid_clb_1__2_:bottom_width_0_height_0__pin_31_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_ccff_tail[0] 0.001487747 //LENGTH 7.660 LUMPCC 0.0003272284 DR + +*CONN +*I cbx_2__1_:ccff_tail[0] O *L 0 *C 668.990 616.080 +*I sb_1__1_:ccff_head[0] I *L 0 *C 661.330 616.080 +*N cbx_1__1__1_ccff_tail[0]:2 *C 667.519 616.080 +*N cbx_1__1__1_ccff_tail[0]:3 *C 667.520 616.080 + +*CAP +0 cbx_2__1_:ccff_tail[0] 0.0002176192 +1 sb_1__1_:ccff_head[0] 0.0003626402 +2 cbx_1__1__1_ccff_tail[0]:2 0.0003626402 +3 cbx_1__1__1_ccff_tail[0]:3 0.0002176192 +4 sb_1__1_:ccff_head[0] sb_1__1_:chanx_right_out[13] 4.980435e-05 +5 cbx_1__1__1_ccff_tail[0]:2 sb_1__1__0_chanx_right_out[13]:3 4.980435e-05 +6 cbx_2__1_:ccff_tail[0] cbx_2__1_:chanx_left_in[19] 1.643549e-06 +7 sb_1__1_:ccff_head[0] sb_1__1_:chanx_right_out[19] 0.0001121663 +8 cbx_1__1__1_ccff_tail[0]:3 sb_1__1__0_chanx_right_out[19]:2 1.643549e-06 +9 cbx_1__1__1_ccff_tail[0]:2 sb_1__1__0_chanx_right_out[19]:3 0.0001121663 + +*RES +0 cbx_2__1_:ccff_tail[0] cbx_1__1__1_ccff_tail[0]:3 0.0002303 +1 cbx_1__1__1_ccff_tail[0]:3 cbx_1__1__1_ccff_tail[0]:2 1e-05 +2 cbx_1__1__1_ccff_tail[0]:2 sb_1__1_:ccff_head[0] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[0] 0.005652618 //LENGTH 37.795 LUMPCC 0.002654397 DR + +*CONN +*I cbx_2__1_:chanx_left_out[0] O *L 0 *C 673.440 555.030 +*I sb_1__1_:chanx_right_in[0] I *L 0 *C 661.330 576.640 +*N cbx_1__1__1_chanx_left_out[0]:2 *C 664.692 576.640 +*N cbx_1__1__1_chanx_left_out[0]:3 *C 664.700 576.582 +*N cbx_1__1__1_chanx_left_out[0]:4 *C 664.700 553.577 +*N cbx_1__1__1_chanx_left_out[0]:5 *C 664.707 553.520 +*N cbx_1__1__1_chanx_left_out[0]:6 *C 667.519 553.520 +*N cbx_1__1__1_chanx_left_out[0]:7 *C 667.520 553.520 +*N cbx_1__1__1_chanx_left_out[0]:8 *C 673.420 553.520 +*N cbx_1__1__1_chanx_left_out[0]:9 *C 673.440 553.528 + +*CAP +0 cbx_2__1_:chanx_left_out[0] 0.0001276041 +1 sb_1__1_:chanx_right_in[0] 0.0002845174 +2 cbx_1__1__1_chanx_left_out[0]:2 0.0002845174 +3 cbx_1__1__1_chanx_left_out[0]:3 0.000933013 +4 cbx_1__1__1_chanx_left_out[0]:4 0.000933013 +5 cbx_1__1__1_chanx_left_out[0]:5 5.341237e-05 +6 cbx_1__1__1_chanx_left_out[0]:6 5.341237e-05 +7 cbx_1__1__1_chanx_left_out[0]:7 0.0001005639 +8 cbx_1__1__1_chanx_left_out[0]:8 0.0001005639 +9 cbx_1__1__1_chanx_left_out[0]:9 0.0001276041 +10 cbx_1__1__1_chanx_left_out[0]:8 clk[0]:44 0.0003375046 +11 cbx_1__1__1_chanx_left_out[0]:5 clk[0]:41 0.0001663756 +12 cbx_1__1__1_chanx_left_out[0]:7 clk[0]:43 0.0003375046 +13 cbx_1__1__1_chanx_left_out[0]:6 clk[0]:42 0.0001663756 +14 cbx_1__1__1_chanx_left_out[0]:4 cbx_1__1__1_chanx_left_out[3]:4 9.214532e-05 +15 cbx_1__1__1_chanx_left_out[0]:3 cbx_1__1__1_chanx_left_out[3]:3 9.214532e-05 +16 sb_1__1_:chanx_right_in[0] sb_1__1_:chanx_right_in[9] 2.790978e-05 +17 cbx_1__1__1_chanx_left_out[0]:2 cbx_1__1__1_chanx_left_out[9]:2 2.790978e-05 +18 cbx_1__1__1_chanx_left_out[0]:8 cbx_1__1__1_chanx_left_out[11]:8 1.880641e-05 +19 cbx_1__1__1_chanx_left_out[0]:4 cbx_1__1__1_chanx_left_out[11]:4 0.0001361966 +20 cbx_1__1__1_chanx_left_out[0]:3 cbx_1__1__1_chanx_left_out[11]:3 0.0001361966 +21 cbx_1__1__1_chanx_left_out[0]:7 cbx_1__1__1_chanx_left_out[11]:7 1.880641e-05 +22 sb_1__1_:chanx_right_in[0] sb_1__1_:chanx_right_out[14] 4.437987e-05 +23 cbx_1__1__1_chanx_left_out[0]:2 sb_1__1__0_chanx_right_out[14]:3 4.437987e-05 +24 cbx_1__1__1_chanx_left_out[0]:8 ctsbuf_net_1221:23 0.0003375046 +25 cbx_1__1__1_chanx_left_out[0]:5 ctsbuf_net_1221:26 0.0001663756 +26 cbx_1__1__1_chanx_left_out[0]:7 ctsbuf_net_1221:24 0.0003375046 +27 cbx_1__1__1_chanx_left_out[0]:6 ctsbuf_net_1221:25 0.0001663756 + +*RES +0 cbx_2__1_:chanx_left_out[0] cbx_1__1__1_chanx_left_out[0]:9 0.0002353916 +1 cbx_1__1__1_chanx_left_out[0]:8 cbx_1__1__1_chanx_left_out[0]:7 0.0009243333 +2 cbx_1__1__1_chanx_left_out[0]:9 cbx_1__1__1_chanx_left_out[0]:8 0.00341 +3 cbx_1__1__1_chanx_left_out[0]:4 cbx_1__1__1_chanx_left_out[0]:3 0.02054018 +4 cbx_1__1__1_chanx_left_out[0]:5 cbx_1__1__1_chanx_left_out[0]:4 0.00341 +5 cbx_1__1__1_chanx_left_out[0]:3 cbx_1__1__1_chanx_left_out[0]:2 0.00341 +6 cbx_1__1__1_chanx_left_out[0]:2 sb_1__1_:chanx_right_in[0] 0.0005267916 +7 cbx_1__1__1_chanx_left_out[0]:7 cbx_1__1__1_chanx_left_out[0]:6 1e-05 +8 cbx_1__1__1_chanx_left_out[0]:6 cbx_1__1__1_chanx_left_out[0]:5 0.0004404683 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[1] 0.00132583 //LENGTH 7.660 LUMPCC 9.698182e-05 DR + +*CONN +*I cbx_2__1_:chanx_left_out[1] O *L 0 *C 668.990 626.960 +*I sb_1__1_:chanx_right_in[1] I *L 0 *C 661.330 626.960 +*N cbx_1__1__1_chanx_left_out[1]:2 *C 667.519 626.960 +*N cbx_1__1__1_chanx_left_out[1]:3 *C 667.520 626.960 + +*CAP +0 cbx_2__1_:chanx_left_out[1] 0.0001863456 +1 sb_1__1_:chanx_right_in[1] 0.0004280783 +2 cbx_1__1__1_chanx_left_out[1]:2 0.0004280783 +3 cbx_1__1__1_chanx_left_out[1]:3 0.0001863456 +4 sb_1__1_:chanx_right_in[1] sb_1__1_:chanx_right_in[12] 4.849091e-05 +5 cbx_1__1__1_chanx_left_out[1]:2 cbx_1__1__1_chanx_left_out[12]:2 4.849091e-05 + +*RES +0 cbx_2__1_:chanx_left_out[1] cbx_1__1__1_chanx_left_out[1]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[1]:3 cbx_1__1__1_chanx_left_out[1]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[1]:2 sb_1__1_:chanx_right_in[1] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[2] 0.001415483 //LENGTH 7.660 LUMPCC 0.0002970469 DR + +*CONN +*I cbx_2__1_:chanx_left_out[2] O *L 0 *C 668.990 583.440 +*I sb_1__1_:chanx_right_in[2] I *L 0 *C 661.330 583.440 +*N cbx_1__1__1_chanx_left_out[2]:2 *C 667.519 583.440 +*N cbx_1__1__1_chanx_left_out[2]:3 *C 667.520 583.440 + +*CAP +0 cbx_2__1_:chanx_left_out[2] 0.0002094739 +1 sb_1__1_:chanx_right_in[2] 0.000349744 +2 cbx_1__1__1_chanx_left_out[2]:2 0.000349744 +3 cbx_1__1__1_chanx_left_out[2]:3 0.0002094739 +4 sb_1__1_:chanx_right_in[2] sb_1__1_:chanx_right_in[15] 0.0001107108 +5 cbx_1__1__1_chanx_left_out[2]:2 cbx_1__1__1_chanx_left_out[15]:2 0.0001107108 +6 sb_1__1_:chanx_right_in[2] sb_1__1_:chanx_right_out[18] 3.781267e-05 +7 cbx_1__1__1_chanx_left_out[2]:2 sb_1__1__0_chanx_right_out[18]:3 3.781267e-05 + +*RES +0 cbx_2__1_:chanx_left_out[2] cbx_1__1__1_chanx_left_out[2]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[2]:3 cbx_1__1__1_chanx_left_out[2]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[2]:2 sb_1__1_:chanx_right_in[2] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[3] 0.003133321 //LENGTH 25.410 LUMPCC 0.0005048642 DR + +*CONN +*I cbx_2__1_:chanx_left_out[3] O *L 0 *C 673.440 554.950 +*I sb_1__1_:chanx_right_in[3] I *L 0 *C 661.330 565.760 +*N cbx_1__1__1_chanx_left_out[3]:2 *C 663.312 565.760 +*N cbx_1__1__1_chanx_left_out[3]:3 *C 663.320 565.702 +*N cbx_1__1__1_chanx_left_out[3]:4 *C 663.320 554.245 +*N cbx_1__1__1_chanx_left_out[3]:5 *C 663.365 554.200 +*N cbx_1__1__1_chanx_left_out[3]:6 *C 667.519 554.200 +*N cbx_1__1__1_chanx_left_out[3]:7 *C 667.520 554.200 +*N cbx_1__1__1_chanx_left_out[3]:8 *C 673.395 554.200 +*N cbx_1__1__1_chanx_left_out[3]:9 *C 673.440 554.245 + +*CAP +0 cbx_2__1_:chanx_left_out[3] 4.757039e-05 +1 sb_1__1_:chanx_right_in[3] 0.0002652233 +2 cbx_1__1__1_chanx_left_out[3]:2 0.0002652233 +3 cbx_1__1__1_chanx_left_out[3]:3 0.0004927567 +4 cbx_1__1__1_chanx_left_out[3]:4 0.0004927567 +5 cbx_1__1__1_chanx_left_out[3]:5 0.0002366144 +6 cbx_1__1__1_chanx_left_out[3]:6 0.0002366144 +7 cbx_1__1__1_chanx_left_out[3]:7 0.0002720636 +8 cbx_1__1__1_chanx_left_out[3]:8 0.0002720636 +9 cbx_1__1__1_chanx_left_out[3]:9 4.757039e-05 +10 cbx_1__1__1_chanx_left_out[3]:4 cbx_1__1__1_chanx_left_out[0]:4 9.214532e-05 +11 cbx_1__1__1_chanx_left_out[3]:3 cbx_1__1__1_chanx_left_out[0]:3 9.214532e-05 +12 cbx_2__1_:chanx_left_out[3] cbx_2__1_:chanx_left_out[11] 1.012453e-05 +13 cbx_1__1__1_chanx_left_out[3]:8 cbx_1__1__1_chanx_left_out[11]:8 0.0001184022 +14 cbx_1__1__1_chanx_left_out[3]:9 cbx_1__1__1_chanx_left_out[11]:9 1.012453e-05 +15 cbx_1__1__1_chanx_left_out[3]:5 cbx_1__1__1_chanx_left_out[11]:5 3.084064e-05 +16 cbx_1__1__1_chanx_left_out[3]:4 cbx_1__1__1_chanx_left_out[11]:4 9.194359e-07 +17 cbx_1__1__1_chanx_left_out[3]:3 cbx_1__1__1_chanx_left_out[11]:3 9.194359e-07 +18 cbx_1__1__1_chanx_left_out[3]:7 cbx_1__1__1_chanx_left_out[11]:7 0.0001184022 +19 cbx_1__1__1_chanx_left_out[3]:6 cbx_1__1__1_chanx_left_out[11]:6 3.084064e-05 + +*RES +0 cbx_2__1_:chanx_left_out[3] cbx_1__1__1_chanx_left_out[3]:9 0.0006294642 +1 cbx_1__1__1_chanx_left_out[3]:8 cbx_1__1__1_chanx_left_out[3]:7 0.005245536 +2 cbx_1__1__1_chanx_left_out[3]:9 cbx_1__1__1_chanx_left_out[3]:8 0.0045 +3 cbx_1__1__1_chanx_left_out[3]:5 cbx_1__1__1_chanx_left_out[3]:4 0.0045 +4 cbx_1__1__1_chanx_left_out[3]:4 cbx_1__1__1_chanx_left_out[3]:3 0.01022991 +5 cbx_1__1__1_chanx_left_out[3]:3 cbx_1__1__1_chanx_left_out[3]:2 0.00341 +6 cbx_1__1__1_chanx_left_out[3]:2 sb_1__1_:chanx_right_in[3] 0.0003105916 +7 cbx_1__1__1_chanx_left_out[3]:7 cbx_1__1__1_chanx_left_out[3]:6 1e-05 +8 cbx_1__1__1_chanx_left_out[3]:6 cbx_1__1__1_chanx_left_out[3]:5 0.003708929 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[4] 0.001440666 //LENGTH 7.660 LUMPCC 0.0003130831 DR + +*CONN +*I cbx_2__1_:chanx_left_out[4] O *L 0 *C 668.990 621.520 +*I sb_1__1_:chanx_right_in[4] I *L 0 *C 661.330 621.520 +*N cbx_1__1__1_chanx_left_out[4]:2 *C 667.519 621.520 +*N cbx_1__1__1_chanx_left_out[4]:3 *C 667.520 621.520 + +*CAP +0 cbx_2__1_:chanx_left_out[4] 0.0002095016 +1 sb_1__1_:chanx_right_in[4] 0.0003542901 +2 cbx_1__1__1_chanx_left_out[4]:2 0.0003542901 +3 cbx_1__1__1_chanx_left_out[4]:3 0.0002095016 +4 sb_1__1_:chanx_right_in[4] sb_1__1_:chanx_right_in[5] 0.0001070368 +5 cbx_1__1__1_chanx_left_out[4]:2 cbx_1__1__1_chanx_left_out[5]:2 0.0001070368 +6 sb_1__1_:chanx_right_in[4] sb_1__1_:chanx_right_in[14] 4.950478e-05 +7 cbx_1__1__1_chanx_left_out[4]:2 cbx_1__1__1_chanx_left_out[14]:2 4.950478e-05 + +*RES +0 cbx_2__1_:chanx_left_out[4] cbx_1__1__1_chanx_left_out[4]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[4]:3 cbx_1__1__1_chanx_left_out[4]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[4]:2 sb_1__1_:chanx_right_in[4] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[6] 0.001480384 //LENGTH 7.660 LUMPCC 0.0002849103 DR + +*CONN +*I cbx_2__1_:chanx_left_out[6] O *L 0 *C 668.990 605.200 +*I sb_1__1_:chanx_right_in[6] I *L 0 *C 661.330 605.200 +*N cbx_1__1__1_chanx_left_out[6]:2 *C 667.519 605.200 +*N cbx_1__1__1_chanx_left_out[6]:3 *C 667.520 605.200 + +*CAP +0 cbx_2__1_:chanx_left_out[6] 0.0002200387 +1 sb_1__1_:chanx_right_in[6] 0.0003776982 +2 cbx_1__1__1_chanx_left_out[6]:2 0.0003776982 +3 cbx_1__1__1_chanx_left_out[6]:3 0.0002200387 +4 sb_1__1_:chanx_right_in[6] sb_1__1_:chanx_right_out[3] 3.59257e-05 +5 cbx_1__1__1_chanx_left_out[6]:2 sb_1__1__0_chanx_right_out[3]:3 3.59257e-05 +6 sb_1__1_:chanx_right_in[6] sb_1__1_:chanx_right_out[11] 0.0001065295 +7 cbx_1__1__1_chanx_left_out[6]:2 sb_1__1__0_chanx_right_out[11]:3 0.0001065295 + +*RES +0 cbx_2__1_:chanx_left_out[6] cbx_1__1__1_chanx_left_out[6]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[6]:3 cbx_1__1__1_chanx_left_out[6]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[6]:2 sb_1__1_:chanx_right_in[6] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[7] 0.001482806 //LENGTH 7.660 LUMPCC 0.0003185545 DR + +*CONN +*I cbx_2__1_:chanx_left_out[7] O *L 0 *C 668.990 597.040 +*I sb_1__1_:chanx_right_in[7] I *L 0 *C 661.330 597.040 +*N cbx_1__1__1_chanx_left_out[7]:2 *C 667.519 597.040 +*N cbx_1__1__1_chanx_left_out[7]:3 *C 667.520 597.040 + +*CAP +0 cbx_2__1_:chanx_left_out[7] 0.0002200131 +1 sb_1__1_:chanx_right_in[7] 0.0003621125 +2 cbx_1__1__1_chanx_left_out[7]:2 0.0003621125 +3 cbx_1__1__1_chanx_left_out[7]:3 0.0002200131 +4 sb_1__1_:chanx_right_in[7] sb_1__1_:chanx_right_out[5] 4.950478e-05 +5 cbx_1__1__1_chanx_left_out[7]:2 sb_1__1__0_chanx_right_out[5]:3 4.950478e-05 +6 sb_1__1_:chanx_right_in[7] sb_1__1_:chanx_right_out[15] 0.0001097725 +7 cbx_1__1__1_chanx_left_out[7]:2 sb_1__1__0_chanx_right_out[15]:3 0.0001097725 + +*RES +0 cbx_2__1_:chanx_left_out[7] cbx_1__1__1_chanx_left_out[7]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[7]:3 cbx_1__1__1_chanx_left_out[7]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[7]:2 sb_1__1_:chanx_right_in[7] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[8] 0.001443916 //LENGTH 7.660 LUMPCC 0.0004327009 DR + +*CONN +*I cbx_2__1_:chanx_left_out[8] O *L 0 *C 668.990 572.560 +*I sb_1__1_:chanx_right_in[8] I *L 0 *C 661.330 572.560 +*N cbx_1__1__1_chanx_left_out[8]:2 *C 667.519 572.560 +*N cbx_1__1__1_chanx_left_out[8]:3 *C 667.520 572.560 + +*CAP +0 cbx_2__1_:chanx_left_out[8] 0.0001916152 +1 sb_1__1_:chanx_right_in[8] 0.0003139923 +2 cbx_1__1__1_chanx_left_out[8]:2 0.0003139923 +3 cbx_1__1__1_chanx_left_out[8]:3 0.0001916152 +4 sb_1__1_:chanx_right_in[8] sb_1__1_:chanx_right_in[11] 9.202773e-05 +5 cbx_1__1__1_chanx_left_out[8]:2 cbx_1__1__1_chanx_left_out[11]:2 9.202773e-05 +6 cbx_2__1_:chanx_left_out[8] cbx_2__1_:chanx_left_in[8] 6.576165e-06 +7 sb_1__1_:chanx_right_in[8] sb_1__1_:chanx_right_out[8] 0.0001177465 +8 cbx_1__1__1_chanx_left_out[8]:3 sb_1__1__0_chanx_right_out[8]:2 6.576165e-06 +9 cbx_1__1__1_chanx_left_out[8]:2 sb_1__1__0_chanx_right_out[8]:3 0.0001177465 + +*RES +0 cbx_2__1_:chanx_left_out[8] cbx_1__1__1_chanx_left_out[8]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[8]:3 cbx_1__1__1_chanx_left_out[8]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[8]:2 sb_1__1_:chanx_right_in[8] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[10] 0.001462486 //LENGTH 7.660 LUMPCC 0.0003139121 DR + +*CONN +*I cbx_2__1_:chanx_left_out[10] O *L 0 *C 668.990 564.400 +*I sb_1__1_:chanx_right_in[10] I *L 0 *C 661.330 564.400 +*N cbx_1__1__1_chanx_left_out[10]:2 *C 667.519 564.400 +*N cbx_1__1__1_chanx_left_out[10]:3 *C 667.520 564.400 + +*CAP +0 cbx_2__1_:chanx_left_out[10] 0.0002006812 +1 sb_1__1_:chanx_right_in[10] 0.0003736056 +2 cbx_1__1__1_chanx_left_out[10]:2 0.0003736056 +3 cbx_1__1__1_chanx_left_out[10]:3 0.0002006812 +4 sb_1__1_:chanx_right_in[10] sb_1__1_:chanx_right_in[16] 3.988636e-05 +5 cbx_1__1__1_chanx_left_out[10]:2 cbx_1__1__1_chanx_left_out[16]:2 3.988636e-05 +6 cbx_2__1_:chanx_left_out[10] cbx_2__1_:chanx_left_in[7] 6.577123e-06 +7 sb_1__1_:chanx_right_in[10] sb_1__1_:chanx_right_out[7] 0.0001104926 +8 cbx_1__1__1_chanx_left_out[10]:3 sb_1__1__0_chanx_right_out[7]:2 6.577123e-06 +9 cbx_1__1__1_chanx_left_out[10]:2 sb_1__1__0_chanx_right_out[7]:3 0.0001104926 + +*RES +0 cbx_2__1_:chanx_left_out[10] cbx_1__1__1_chanx_left_out[10]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[10]:3 cbx_1__1__1_chanx_left_out[10]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[10]:2 sb_1__1_:chanx_right_in[10] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[11] 0.003776497 //LENGTH 33.130 LUMPCC 0.0009986904 DR + +*CONN +*I cbx_2__1_:chanx_left_out[11] O *L 0 *C 674.360 554.950 +*I sb_1__1_:chanx_right_in[11] I *L 0 *C 661.330 571.200 +*N cbx_1__1__1_chanx_left_out[11]:2 *C 666.072 571.200 +*N cbx_1__1__1_chanx_left_out[11]:3 *C 666.080 571.143 +*N cbx_1__1__1_chanx_left_out[11]:4 *C 666.080 553.565 +*N cbx_1__1__1_chanx_left_out[11]:5 *C 666.125 553.520 +*N cbx_1__1__1_chanx_left_out[11]:6 *C 667.519 553.520 +*N cbx_1__1__1_chanx_left_out[11]:7 *C 667.520 553.520 +*N cbx_1__1__1_chanx_left_out[11]:8 *C 674.315 553.520 +*N cbx_1__1__1_chanx_left_out[11]:9 *C 674.360 553.565 + +*CAP +0 cbx_2__1_:chanx_left_out[11] 8.749864e-05 +1 sb_1__1_:chanx_right_in[11] 0.0002542782 +2 cbx_1__1__1_chanx_left_out[11]:2 0.0002542782 +3 cbx_1__1__1_chanx_left_out[11]:3 0.0007469534 +4 cbx_1__1__1_chanx_left_out[11]:4 0.0007469534 +5 cbx_1__1__1_chanx_left_out[11]:5 5.747514e-05 +6 cbx_1__1__1_chanx_left_out[11]:6 5.747514e-05 +7 cbx_1__1__1_chanx_left_out[11]:7 0.0002426981 +8 cbx_1__1__1_chanx_left_out[11]:8 0.0002426981 +9 cbx_1__1__1_chanx_left_out[11]:9 8.749864e-05 +10 cbx_1__1__1_chanx_left_out[11]:8 cbx_1__1__1_chanx_left_out[0]:8 1.880641e-05 +11 cbx_1__1__1_chanx_left_out[11]:4 cbx_1__1__1_chanx_left_out[0]:4 0.0001361966 +12 cbx_1__1__1_chanx_left_out[11]:3 cbx_1__1__1_chanx_left_out[0]:3 0.0001361966 +13 cbx_1__1__1_chanx_left_out[11]:7 cbx_1__1__1_chanx_left_out[0]:7 1.880641e-05 +14 cbx_2__1_:chanx_left_out[11] cbx_2__1_:chanx_left_out[3] 1.012453e-05 +15 cbx_1__1__1_chanx_left_out[11]:8 cbx_1__1__1_chanx_left_out[3]:8 0.0001184022 +16 cbx_1__1__1_chanx_left_out[11]:9 cbx_1__1__1_chanx_left_out[3]:9 1.012453e-05 +17 cbx_1__1__1_chanx_left_out[11]:5 cbx_1__1__1_chanx_left_out[3]:5 3.084064e-05 +18 cbx_1__1__1_chanx_left_out[11]:4 cbx_1__1__1_chanx_left_out[3]:4 9.194359e-07 +19 cbx_1__1__1_chanx_left_out[11]:3 cbx_1__1__1_chanx_left_out[3]:3 9.194359e-07 +20 cbx_1__1__1_chanx_left_out[11]:7 cbx_1__1__1_chanx_left_out[3]:7 0.0001184022 +21 cbx_1__1__1_chanx_left_out[11]:6 cbx_1__1__1_chanx_left_out[3]:6 3.084064e-05 +22 sb_1__1_:chanx_right_in[11] sb_1__1_:chanx_right_in[8] 9.202773e-05 +23 cbx_1__1__1_chanx_left_out[11]:2 cbx_1__1__1_chanx_left_out[8]:2 9.202773e-05 +24 sb_1__1_:chanx_right_in[11] sb_1__1_:chanx_right_out[12] 9.202773e-05 +25 cbx_1__1__1_chanx_left_out[11]:2 sb_1__1__0_chanx_right_out[12]:3 9.202773e-05 + +*RES +0 cbx_2__1_:chanx_left_out[11] cbx_1__1__1_chanx_left_out[11]:9 0.001236607 +1 cbx_1__1__1_chanx_left_out[11]:8 cbx_1__1__1_chanx_left_out[11]:7 0.006066964 +2 cbx_1__1__1_chanx_left_out[11]:9 cbx_1__1__1_chanx_left_out[11]:8 0.0045 +3 cbx_1__1__1_chanx_left_out[11]:5 cbx_1__1__1_chanx_left_out[11]:4 0.0045 +4 cbx_1__1__1_chanx_left_out[11]:4 cbx_1__1__1_chanx_left_out[11]:3 0.0156942 +5 cbx_1__1__1_chanx_left_out[11]:3 cbx_1__1__1_chanx_left_out[11]:2 0.00341 +6 cbx_1__1__1_chanx_left_out[11]:2 sb_1__1_:chanx_right_in[11] 0.0007429917 +7 cbx_1__1__1_chanx_left_out[11]:7 cbx_1__1__1_chanx_left_out[11]:6 1e-05 +8 cbx_1__1__1_chanx_left_out[11]:6 cbx_1__1__1_chanx_left_out[11]:5 0.001244643 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[13] 0.003705897 //LENGTH 27.320 LUMPCC 0.001138631 DR + +*CONN +*I cbx_2__1_:chanx_left_out[13] O *L 0 *C 675.280 554.950 +*I sb_1__1_:chanx_right_in[13] I *L 0 *C 661.330 560.320 +*N cbx_1__1__1_chanx_left_out[13]:2 *C 662.380 560.320 +*N cbx_1__1__1_chanx_left_out[13]:3 *C 662.400 560.312 +*N cbx_1__1__1_chanx_left_out[13]:4 *C 662.400 551.488 +*N cbx_1__1__1_chanx_left_out[13]:5 *C 662.420 551.480 +*N cbx_1__1__1_chanx_left_out[13]:6 *C 667.519 551.480 +*N cbx_1__1__1_chanx_left_out[13]:7 *C 667.520 551.480 +*N cbx_1__1__1_chanx_left_out[13]:8 *C 675.273 551.480 +*N cbx_1__1__1_chanx_left_out[13]:9 *C 675.280 551.538 + +*CAP +0 cbx_2__1_:chanx_left_out[13] 0.0002087689 +1 sb_1__1_:chanx_right_in[13] 0.0001501081 +2 cbx_1__1__1_chanx_left_out[13]:2 0.0001501081 +3 cbx_1__1__1_chanx_left_out[13]:3 0.0004977865 +4 cbx_1__1__1_chanx_left_out[13]:4 0.0004977865 +5 cbx_1__1__1_chanx_left_out[13]:5 0.0001496788 +6 cbx_1__1__1_chanx_left_out[13]:6 0.0001496788 +7 cbx_1__1__1_chanx_left_out[13]:7 0.0002772906 +8 cbx_1__1__1_chanx_left_out[13]:8 0.0002772906 +9 cbx_1__1__1_chanx_left_out[13]:9 0.0002087689 +10 cbx_1__1__1_chanx_left_out[13]:8 clk[0]:44 0.0001768981 +11 cbx_1__1__1_chanx_left_out[13]:5 clk[0]:41 0.0001224029 +12 cbx_1__1__1_chanx_left_out[13]:7 clk[0]:43 0.0001768981 +13 cbx_1__1__1_chanx_left_out[13]:6 clk[0]:42 0.0001224029 +14 cbx_1__1__1_chanx_left_out[13]:5 direct_interc_2_out[0]:25 8.141912e-05 +15 cbx_1__1__1_chanx_left_out[13]:4 direct_interc_2_out[0]:23 0.0001033751 +16 cbx_1__1__1_chanx_left_out[13]:3 direct_interc_2_out[0]:22 0.0001033751 +17 cbx_1__1__1_chanx_left_out[13]:6 direct_interc_2_out[0]:24 8.141912e-05 +18 cbx_1__1__1_chanx_left_out[13]:8 ctsbuf_net_1928:14 6.809765e-05 +19 cbx_1__1__1_chanx_left_out[13]:5 ctsbuf_net_1928:17 1.712275e-05 +20 cbx_1__1__1_chanx_left_out[13]:7 ctsbuf_net_1928:15 6.809765e-05 +21 cbx_1__1__1_chanx_left_out[13]:6 ctsbuf_net_1928:16 1.712275e-05 + +*RES +0 cbx_2__1_:chanx_left_out[13] cbx_1__1__1_chanx_left_out[13]:9 0.003046875 +1 cbx_1__1__1_chanx_left_out[13]:9 cbx_1__1__1_chanx_left_out[13]:8 0.00341 +2 cbx_1__1__1_chanx_left_out[13]:8 cbx_1__1__1_chanx_left_out[13]:7 0.001214558 +3 cbx_1__1__1_chanx_left_out[13]:5 cbx_1__1__1_chanx_left_out[13]:4 0.00341 +4 cbx_1__1__1_chanx_left_out[13]:4 cbx_1__1__1_chanx_left_out[13]:3 0.001382583 +5 cbx_1__1__1_chanx_left_out[13]:2 sb_1__1_:chanx_right_in[13] 0.0001645 +6 cbx_1__1__1_chanx_left_out[13]:3 cbx_1__1__1_chanx_left_out[13]:2 0.00341 +7 cbx_1__1__1_chanx_left_out[13]:7 cbx_1__1__1_chanx_left_out[13]:6 1e-05 +8 cbx_1__1__1_chanx_left_out[13]:6 cbx_1__1__1_chanx_left_out[13]:5 0.0007988433 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[14] 0.001385803 //LENGTH 7.660 LUMPCC 0.0003616666 DR + +*CONN +*I cbx_2__1_:chanx_left_out[14] O *L 0 *C 668.990 618.800 +*I sb_1__1_:chanx_right_in[14] I *L 0 *C 661.330 618.800 +*N cbx_1__1__1_chanx_left_out[14]:2 *C 667.519 618.800 +*N cbx_1__1__1_chanx_left_out[14]:3 *C 667.520 618.800 + +*CAP +0 cbx_2__1_:chanx_left_out[14] 0.0001867774 +1 sb_1__1_:chanx_right_in[14] 0.0003252907 +2 cbx_1__1__1_chanx_left_out[14]:2 0.0003252907 +3 cbx_1__1__1_chanx_left_out[14]:3 0.0001867774 +4 sb_1__1_:chanx_right_in[14] sb_1__1_:chanx_right_in[4] 4.950478e-05 +5 cbx_1__1__1_chanx_left_out[14]:2 cbx_1__1__1_chanx_left_out[4]:2 4.950478e-05 +6 cbx_2__1_:chanx_left_out[14] cbx_2__1_:chanx_left_in[19] 9.861294e-06 +7 sb_1__1_:chanx_right_in[14] sb_1__1_:chanx_right_out[19] 0.0001214672 +8 cbx_1__1__1_chanx_left_out[14]:3 sb_1__1__0_chanx_right_out[19]:2 9.861294e-06 +9 cbx_1__1__1_chanx_left_out[14]:2 sb_1__1__0_chanx_right_out[19]:3 0.0001214672 + +*RES +0 cbx_2__1_:chanx_left_out[14] cbx_1__1__1_chanx_left_out[14]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[14]:3 cbx_1__1__1_chanx_left_out[14]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[14]:2 sb_1__1_:chanx_right_in[14] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[16] 0.001520823 //LENGTH 7.660 LUMPCC 0.0002812915 DR + +*CONN +*I cbx_2__1_:chanx_left_out[16] O *L 0 *C 668.990 567.120 +*I sb_1__1_:chanx_right_in[16] I *L 0 *C 661.330 567.120 +*N cbx_1__1__1_chanx_left_out[16]:2 *C 667.519 567.120 +*N cbx_1__1__1_chanx_left_out[16]:3 *C 667.520 567.120 + +*CAP +0 cbx_2__1_:chanx_left_out[16] 0.0002200131 +1 sb_1__1_:chanx_right_in[16] 0.0003997528 +2 cbx_1__1__1_chanx_left_out[16]:2 0.0003997528 +3 cbx_1__1__1_chanx_left_out[16]:3 0.0002200131 +4 sb_1__1_:chanx_right_in[16] sb_1__1_:chanx_right_in[10] 3.988636e-05 +5 cbx_1__1__1_chanx_left_out[16]:2 cbx_1__1__1_chanx_left_out[10]:2 3.988636e-05 +6 sb_1__1_:chanx_right_in[16] sb_1__1_:chanx_right_out[16] 0.0001007594 +7 cbx_1__1__1_chanx_left_out[16]:2 sb_1__1__0_chanx_right_out[16]:3 0.0001007594 + +*RES +0 cbx_2__1_:chanx_left_out[16] cbx_1__1__1_chanx_left_out[16]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[16]:3 cbx_1__1__1_chanx_left_out[16]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[16]:2 sb_1__1_:chanx_right_in[16] 0.0009696099 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[17] 0.001437085 //LENGTH 7.660 LUMPCC 0.0003175026 DR + +*CONN +*I cbx_2__1_:chanx_left_out[17] O *L 0 *C 668.990 561.680 +*I sb_1__1_:chanx_right_in[17] I *L 0 *C 661.330 561.680 +*N cbx_1__1__1_chanx_left_out[17]:2 *C 667.519 561.680 +*N cbx_1__1__1_chanx_left_out[17]:3 *C 667.520 561.680 + +*CAP +0 cbx_2__1_:chanx_left_out[17] 0.0002108621 +1 sb_1__1_:chanx_right_in[17] 0.0003489291 +2 cbx_1__1__1_chanx_left_out[17]:2 0.0003489291 +3 cbx_1__1__1_chanx_left_out[17]:3 0.0002108621 +4 sb_1__1_:chanx_right_in[17] sb_1__1_:chanx_right_in[19] 4.403194e-05 +5 cbx_1__1__1_chanx_left_out[17]:2 cbx_1__1__1_chanx_left_out[19]:2 4.403194e-05 +6 sb_1__1_:chanx_right_in[17] sb_1__1_:chanx_right_out[7] 0.0001147194 +7 cbx_1__1__1_chanx_left_out[17]:2 sb_1__1__0_chanx_right_out[7]:3 0.0001147194 + +*RES +0 cbx_2__1_:chanx_left_out[17] cbx_1__1__1_chanx_left_out[17]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[17]:3 cbx_1__1__1_chanx_left_out[17]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[17]:2 sb_1__1_:chanx_right_in[17] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_left_out[19] 0.001431059 //LENGTH 7.660 LUMPCC 8.806388e-05 DR + +*CONN +*I cbx_2__1_:chanx_left_out[19] O *L 0 *C 668.990 558.960 +*I sb_1__1_:chanx_right_in[19] I *L 0 *C 661.330 558.960 +*N cbx_1__1__1_chanx_left_out[19]:2 *C 667.519 558.960 +*N cbx_1__1__1_chanx_left_out[19]:3 *C 667.520 558.960 + +*CAP +0 cbx_2__1_:chanx_left_out[19] 0.0002202893 +1 sb_1__1_:chanx_right_in[19] 0.0004512081 +2 cbx_1__1__1_chanx_left_out[19]:2 0.0004512081 +3 cbx_1__1__1_chanx_left_out[19]:3 0.0002202893 +4 sb_1__1_:chanx_right_in[19] sb_1__1_:chanx_right_in[17] 4.403194e-05 +5 cbx_1__1__1_chanx_left_out[19]:2 cbx_1__1__1_chanx_left_out[17]:2 4.403194e-05 + +*RES +0 cbx_2__1_:chanx_left_out[19] cbx_1__1__1_chanx_left_out[19]:3 0.0002303 +1 cbx_1__1__1_chanx_left_out[19]:3 cbx_1__1__1_chanx_left_out[19]:2 1e-05 +2 cbx_1__1__1_chanx_left_out[19]:2 sb_1__1_:chanx_right_in[19] 0.00096961 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[0] 0.001600871 //LENGTH 7.660 LUMPCC 0.0003797518 DR + +*CONN +*I cbx_2__1_:chanx_right_out[0] O *L 0 *C 773.570 603.840 +*I sb_2__1_:chanx_left_in[0] I *L 0 *C 781.230 603.840 + +*CAP +0 cbx_2__1_:chanx_right_out[0] 0.0006105594 +1 sb_2__1_:chanx_left_in[0] 0.0006105594 +2 cbx_2__1_:chanx_right_out[0] cbx_2__1_:chanx_right_out[15] 9.428097e-05 +3 sb_2__1_:chanx_left_in[0] sb_2__1_:chanx_left_in[15] 9.428097e-05 +4 cbx_2__1_:chanx_right_out[0] cbx_2__1_:chanx_right_in[3] 9.55949e-05 +5 sb_2__1_:chanx_left_in[0] sb_2__1_:chanx_left_out[3] 9.55949e-05 + +*RES +0 cbx_2__1_:chanx_right_out[0] sb_2__1_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[1] 0.001585589 //LENGTH 7.660 LUMPCC 0.0003335308 DR + +*CONN +*I cbx_2__1_:chanx_right_out[1] O *L 0 *C 773.570 565.760 +*I sb_2__1_:chanx_left_in[1] I *L 0 *C 781.230 565.760 + +*CAP +0 cbx_2__1_:chanx_right_out[1] 0.0006260292 +1 sb_2__1_:chanx_left_in[1] 0.0006260292 +2 cbx_2__1_:chanx_right_out[1] cbx_2__1_:chanx_right_out[3] 9.299627e-05 +3 sb_2__1_:chanx_left_in[1] sb_2__1_:chanx_left_in[3] 9.299627e-05 +4 cbx_2__1_:chanx_right_out[1] cbx_2__1_:chanx_right_out[11] 4.132848e-05 +5 cbx_2__1_:chanx_right_out[1] cbx_1__1__1_chanx_right_out[11]:4 3.909788e-06 +6 cbx_2__1_:chanx_right_out[1] cbx_1__1__1_chanx_right_out[11]:2 2.853087e-05 +7 sb_2__1_:chanx_left_in[1] sb_2__1_:chanx_left_in[11] 2.853087e-05 +8 sb_2__1_:chanx_left_in[1] cbx_1__1__1_chanx_right_out[11]:5 4.132848e-05 +9 sb_2__1_:chanx_left_in[1] cbx_1__1__1_chanx_right_out[11]:3 3.909788e-06 + +*RES +0 cbx_2__1_:chanx_right_out[1] sb_2__1_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[2] 0.003984167 //LENGTH 33.110 LUMPCC 0.001245309 DR + +*CONN +*I cbx_2__1_:chanx_right_out[2] O *L 0 *C 769.580 554.950 +*I sb_2__1_:chanx_left_in[2] I *L 0 *C 781.230 573.920 +*N cbx_1__1__1_chanx_right_out[2]:2 *C 777.408 573.920 +*N cbx_1__1__1_chanx_right_out[2]:3 *C 777.400 573.863 +*N cbx_1__1__1_chanx_right_out[2]:4 *C 777.400 554.245 +*N cbx_1__1__1_chanx_right_out[2]:5 *C 777.355 554.200 +*N cbx_1__1__1_chanx_right_out[2]:6 *C 769.625 554.200 +*N cbx_1__1__1_chanx_right_out[2]:7 *C 769.580 554.245 + +*CAP +0 cbx_2__1_:chanx_right_out[2] 5.676301e-05 +1 sb_2__1_:chanx_left_in[2] 0.0002877169 +2 cbx_1__1__1_chanx_right_out[2]:2 0.0002877169 +3 cbx_1__1__1_chanx_right_out[2]:3 0.0005725212 +4 cbx_1__1__1_chanx_right_out[2]:4 0.0005725212 +5 cbx_1__1__1_chanx_right_out[2]:5 0.0004524282 +6 cbx_1__1__1_chanx_right_out[2]:6 0.0004524282 +7 cbx_1__1__1_chanx_right_out[2]:7 5.676301e-05 +8 cbx_1__1__1_chanx_right_out[2]:3 clk[0]:48 9.813355e-05 +9 cbx_1__1__1_chanx_right_out[2]:4 clk[0]:47 9.813355e-05 +10 cbx_1__1__1_chanx_right_out[2]:3 cbx_1__1__1_chanx_right_out[11]:5 4.305203e-05 +11 cbx_1__1__1_chanx_right_out[2]:3 cbx_1__1__1_chanx_right_out[11]:2 5.783038e-05 +12 cbx_1__1__1_chanx_right_out[2]:4 cbx_1__1__1_chanx_right_out[11]:4 4.305203e-05 +13 cbx_1__1__1_chanx_right_out[2]:4 cbx_1__1__1_chanx_right_out[11]:3 5.783038e-05 +14 cbx_1__1__1_chanx_right_out[2]:3 direct_interc_1_out[0]:2 0.0002577573 +15 cbx_1__1__1_chanx_right_out[2]:4 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 0.0002577573 +16 sb_2__1_:chanx_left_in[2] sb_2__1_:chanx_left_out[5] 4.94577e-05 +17 cbx_1__1__1_chanx_right_out[2]:2 cbx_2__1_:chanx_right_in[5] 4.94577e-05 +18 sb_2__1_:chanx_left_in[2] sb_2__1_:chanx_left_out[12] 5.956342e-05 +19 cbx_1__1__1_chanx_right_out[2]:2 cbx_2__1_:chanx_right_in[12] 5.956342e-05 +20 cbx_1__1__1_chanx_right_out[2]:5 sb_2__1__0_chanx_left_out[15]:4 5.685991e-05 +21 cbx_1__1__1_chanx_right_out[2]:6 sb_2__1__0_chanx_left_out[15]:3 5.685991e-05 + +*RES +0 cbx_2__1_:chanx_right_out[2] cbx_1__1__1_chanx_right_out[2]:7 0.0006294643 +1 cbx_1__1__1_chanx_right_out[2]:3 cbx_1__1__1_chanx_right_out[2]:2 0.00341 +2 cbx_1__1__1_chanx_right_out[2]:2 sb_2__1_:chanx_left_in[2] 0.0005988583 +3 cbx_1__1__1_chanx_right_out[2]:5 cbx_1__1__1_chanx_right_out[2]:4 0.0045 +4 cbx_1__1__1_chanx_right_out[2]:4 cbx_1__1__1_chanx_right_out[2]:3 0.01751563 +5 cbx_1__1__1_chanx_right_out[2]:6 cbx_1__1__1_chanx_right_out[2]:5 0.006901786 +6 cbx_1__1__1_chanx_right_out[2]:7 cbx_1__1__1_chanx_right_out[2]:6 0.0045 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[4] 0.001537759 //LENGTH 7.660 LUMPCC 0.0002730743 DR + +*CONN +*I cbx_2__1_:chanx_right_out[4] O *L 0 *C 773.570 613.360 +*I sb_2__1_:chanx_left_in[4] I *L 0 *C 781.230 613.360 + +*CAP +0 cbx_2__1_:chanx_right_out[4] 0.0006323421 +1 sb_2__1_:chanx_left_in[4] 0.0006323421 +2 cbx_2__1_:chanx_right_out[4] cbx_2__1_:chanx_right_out[5] 9.707651e-05 +3 sb_2__1_:chanx_left_in[4] sb_2__1_:chanx_left_in[5] 9.707651e-05 +4 cbx_2__1_:chanx_right_out[4] cbx_2__1_:chanx_right_in[2] 3.946064e-05 +5 sb_2__1_:chanx_left_in[4] sb_2__1_:chanx_left_out[2] 3.946064e-05 + +*RES +0 cbx_2__1_:chanx_right_out[4] sb_2__1_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[5] 0.001594959 //LENGTH 7.660 LUMPCC 0.0003870044 DR + +*CONN +*I cbx_2__1_:chanx_right_out[5] O *L 0 *C 773.570 614.720 +*I sb_2__1_:chanx_left_in[5] I *L 0 *C 781.230 614.720 + +*CAP +0 cbx_2__1_:chanx_right_out[5] 0.0006039774 +1 sb_2__1_:chanx_left_in[5] 0.0006039774 +2 cbx_2__1_:chanx_right_out[5] cbx_2__1_:chanx_right_out[4] 9.707651e-05 +3 sb_2__1_:chanx_left_in[5] sb_2__1_:chanx_left_in[4] 9.707651e-05 +4 cbx_2__1_:chanx_right_out[5] cbx_2__1_:chanx_right_in[17] 9.642568e-05 +5 sb_2__1_:chanx_left_in[5] sb_2__1_:chanx_left_out[17] 9.642568e-05 + +*RES +0 cbx_2__1_:chanx_right_out[5] sb_2__1_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[7] 0.001544295 //LENGTH 7.660 LUMPCC 0.0004361249 DR + +*CONN +*I cbx_2__1_:chanx_right_out[7] O *L 0 *C 773.570 569.840 +*I sb_2__1_:chanx_left_in[7] I *L 0 *C 781.230 569.840 + +*CAP +0 cbx_2__1_:chanx_right_out[7] 0.0005540851 +1 sb_2__1_:chanx_left_in[7] 0.0005540851 +2 cbx_2__1_:chanx_right_out[7] cbx_2__1_:chanx_right_out[8] 0.0001198102 +3 sb_2__1_:chanx_left_in[7] sb_2__1_:chanx_left_in[8] 0.0001198102 +4 cbx_2__1_:chanx_right_out[7] sb_2__1__0_chanx_left_out[15]:7 9.825232e-05 +5 sb_2__1_:chanx_left_in[7] sb_2__1_:chanx_left_out[15] 9.825232e-05 + +*RES +0 cbx_2__1_:chanx_right_out[7] sb_2__1_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[8] 0.001533073 //LENGTH 7.660 LUMPCC 0.0004480209 DR + +*CONN +*I cbx_2__1_:chanx_right_out[8] O *L 0 *C 773.570 571.200 +*I sb_2__1_:chanx_left_in[8] I *L 0 *C 781.230 571.200 + +*CAP +0 cbx_2__1_:chanx_right_out[8] 0.000542526 +1 sb_2__1_:chanx_left_in[8] 0.000542526 +2 cbx_2__1_:chanx_right_out[8] cbx_2__1_:chanx_right_out[7] 0.0001198102 +3 sb_2__1_:chanx_left_in[8] sb_2__1_:chanx_left_in[7] 0.0001198102 +4 cbx_2__1_:chanx_right_out[8] cbx_2__1_:chanx_right_in[12] 0.0001042003 +5 sb_2__1_:chanx_left_in[8] sb_2__1_:chanx_left_out[12] 0.0001042003 + +*RES +0 cbx_2__1_:chanx_right_out[8] sb_2__1_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[10] 0.001333878 //LENGTH 7.660 LUMPCC 0.0002116004 DR + +*CONN +*I cbx_2__1_:chanx_right_out[10] O *L 0 *C 773.570 586.840 +*I sb_2__1_:chanx_left_in[10] I *L 0 *C 781.230 586.840 + +*CAP +0 cbx_2__1_:chanx_right_out[10] 0.0005611388 +1 sb_2__1_:chanx_left_in[10] 0.0005611388 +2 cbx_2__1_:chanx_right_out[10] cbx_2__1_:chanx_right_out[17] 3.524227e-05 +3 sb_2__1_:chanx_left_in[10] sb_2__1_:chanx_left_in[17] 3.524227e-05 +4 cbx_2__1_:chanx_right_out[10] cbx_2__1_:chanx_right_in[0] 7.055791e-05 +5 sb_2__1_:chanx_left_in[10] sb_2__1_:chanx_left_out[0] 7.055791e-05 + +*RES +0 cbx_2__1_:chanx_right_out[10] sb_2__1_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[11] 0.002060668 //LENGTH 10.220 LUMPCC 0.001046117 DR + +*CONN +*I cbx_2__1_:chanx_right_out[11] O *L 0 *C 773.570 564.400 +*I sb_2__1_:chanx_left_in[11] I *L 0 *C 781.230 564.400 +*N cbx_1__1__1_chanx_right_out[11]:2 *C 778.320 564.400 +*N cbx_1__1__1_chanx_right_out[11]:3 *C 778.320 563.720 +*N cbx_1__1__1_chanx_right_out[11]:4 *C 776.940 563.720 +*N cbx_1__1__1_chanx_right_out[11]:5 *C 776.940 564.400 + +*CAP +0 cbx_2__1_:chanx_right_out[11] 0.000321707 +1 sb_2__1_:chanx_left_in[11] 0.0002853627 +2 cbx_1__1__1_chanx_right_out[11]:2 0.0001760295 +3 cbx_1__1__1_chanx_right_out[11]:3 1e-09 +4 cbx_1__1__1_chanx_right_out[11]:4 1e-09 +5 cbx_1__1__1_chanx_right_out[11]:5 0.0002314517 +6 cbx_1__1__1_chanx_right_out[11]:3 clk[0]:47 5.783038e-05 +7 cbx_1__1__1_chanx_right_out[11]:2 clk[0]:48 5.783038e-05 +8 cbx_2__1_:chanx_right_out[11] cbx_2__1_:chanx_right_out[1] 4.132848e-05 +9 sb_2__1_:chanx_left_in[11] sb_2__1_:chanx_left_in[1] 2.853087e-05 +10 cbx_1__1__1_chanx_right_out[11]:5 sb_2__1_:chanx_left_in[1] 4.132848e-05 +11 cbx_1__1__1_chanx_right_out[11]:4 cbx_2__1_:chanx_right_out[1] 3.909788e-06 +12 cbx_1__1__1_chanx_right_out[11]:3 sb_2__1_:chanx_left_in[1] 3.909788e-06 +13 cbx_1__1__1_chanx_right_out[11]:2 cbx_2__1_:chanx_right_out[1] 2.853087e-05 +14 cbx_1__1__1_chanx_right_out[11]:5 cbx_1__1__1_chanx_right_out[2]:3 4.305203e-05 +15 cbx_1__1__1_chanx_right_out[11]:4 cbx_1__1__1_chanx_right_out[2]:4 4.305203e-05 +16 cbx_1__1__1_chanx_right_out[11]:3 cbx_1__1__1_chanx_right_out[2]:4 5.783038e-05 +17 cbx_1__1__1_chanx_right_out[11]:2 cbx_1__1__1_chanx_right_out[2]:3 5.783038e-05 +18 cbx_2__1_:chanx_right_out[11] cbx_1__1__1_chanx_right_out[19]:2 2.519703e-05 +19 sb_2__1_:chanx_left_in[11] sb_2__1_:chanx_left_in[19] 2.757648e-05 +20 cbx_1__1__1_chanx_right_out[11]:5 sb_2__1_:chanx_left_in[19] 2.519703e-05 +21 cbx_1__1__1_chanx_right_out[11]:4 cbx_1__1__1_chanx_right_out[19]:2 9.011399e-05 +22 cbx_1__1__1_chanx_right_out[11]:3 sb_2__1_:chanx_left_in[19] 9.011399e-05 +23 cbx_1__1__1_chanx_right_out[11]:2 cbx_1__1__1_chanx_right_out[19]:2 2.757648e-05 +24 cbx_1__1__1_chanx_right_out[11]:5 direct_interc_1_out[0]:2 4.305203e-05 +25 cbx_1__1__1_chanx_right_out[11]:4 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 4.305203e-05 +26 cbx_1__1__1_chanx_right_out[11]:5 sb_2__1__0_chanx_left_out[15]:6 4.792587e-05 +27 cbx_1__1__1_chanx_right_out[11]:4 sb_2__1__0_chanx_left_out[15]:5 4.792587e-05 +28 cbx_1__1__1_chanx_right_out[11]:3 ctsbuf_net_1221:20 5.671138e-05 +29 cbx_1__1__1_chanx_right_out[11]:2 ctsbuf_net_1221:19 5.671138e-05 + +*RES +0 cbx_2__1_:chanx_right_out[11] cbx_1__1__1_chanx_right_out[11]:5 0.0005279667 +1 cbx_1__1__1_chanx_right_out[11]:5 cbx_1__1__1_chanx_right_out[11]:4 0.0001065333 +2 cbx_1__1__1_chanx_right_out[11]:4 cbx_1__1__1_chanx_right_out[11]:3 0.0002162 +3 cbx_1__1__1_chanx_right_out[11]:3 cbx_1__1__1_chanx_right_out[11]:2 0.0001065333 +4 cbx_1__1__1_chanx_right_out[11]:2 sb_2__1_:chanx_left_in[11] 0.0004559 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[13] 0.001491096 //LENGTH 7.660 LUMPCC 0.0002904368 DR + +*CONN +*I cbx_2__1_:chanx_right_out[13] O *L 0 *C 773.570 621.520 +*I sb_2__1_:chanx_left_in[13] I *L 0 *C 781.230 621.520 + +*CAP +0 cbx_2__1_:chanx_right_out[13] 0.0006003295 +1 sb_2__1_:chanx_left_in[13] 0.0006003295 +2 cbx_2__1_:chanx_right_out[13] cbx_2__1_:chanx_right_out[14] 0.000106361 +3 sb_2__1_:chanx_left_in[13] sb_2__1_:chanx_left_in[14] 0.000106361 +4 cbx_2__1_:chanx_right_out[13] cbx_2__1_:chanx_right_in[11] 3.885734e-05 +5 sb_2__1_:chanx_left_in[13] sb_2__1_:chanx_left_out[11] 3.885734e-05 + +*RES +0 cbx_2__1_:chanx_right_out[13] sb_2__1_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[14] 0.001554375 //LENGTH 7.660 LUMPCC 0.0004226822 DR + +*CONN +*I cbx_2__1_:chanx_right_out[14] O *L 0 *C 773.570 620.160 +*I sb_2__1_:chanx_left_in[14] I *L 0 *C 781.230 620.160 + +*CAP +0 cbx_2__1_:chanx_right_out[14] 0.0005658463 +1 sb_2__1_:chanx_left_in[14] 0.0005658463 +2 cbx_2__1_:chanx_right_out[14] cbx_2__1_:chanx_right_out[13] 0.000106361 +3 sb_2__1_:chanx_left_in[14] sb_2__1_:chanx_left_in[13] 0.000106361 +4 cbx_2__1_:chanx_right_out[14] cbx_2__1_:chanx_right_in[19] 0.00010498 +5 sb_2__1_:chanx_left_in[14] sb_2__1_:chanx_left_out[19] 0.00010498 + +*RES +0 cbx_2__1_:chanx_right_out[14] sb_2__1_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[16] 0.005861927 //LENGTH 43.140 LUMPCC 0.001521543 DR + +*CONN +*I cbx_2__1_:chanx_right_out[16] O *L 0 *C 770.500 554.950 +*I sb_2__1_:chanx_left_in[16] I *L 0 *C 781.230 579.360 +*N cbx_1__1__1_chanx_right_out[16]:2 *C 779.260 579.360 +*N cbx_1__1__1_chanx_right_out[16]:3 *C 779.240 579.353 +*N cbx_1__1__1_chanx_right_out[16]:4 *C 779.240 551.488 +*N cbx_1__1__1_chanx_right_out[16]:5 *C 779.220 551.480 +*N cbx_1__1__1_chanx_right_out[16]:6 *C 770.508 551.480 +*N cbx_1__1__1_chanx_right_out[16]:7 *C 770.500 551.538 + +*CAP +0 cbx_2__1_:chanx_right_out[16] 0.0002072416 +1 sb_2__1_:chanx_left_in[16] 0.000228748 +2 cbx_1__1__1_chanx_right_out[16]:2 0.000228748 +3 cbx_1__1__1_chanx_right_out[16]:3 0.001305133 +4 cbx_1__1__1_chanx_right_out[16]:4 0.001305133 +5 cbx_1__1__1_chanx_right_out[16]:5 0.0004290697 +6 cbx_1__1__1_chanx_right_out[16]:6 0.0004290697 +7 cbx_1__1__1_chanx_right_out[16]:7 0.0002072416 +8 cbx_1__1__1_chanx_right_out[16]:3 clk[0]:48 7.146557e-06 +9 cbx_1__1__1_chanx_right_out[16]:5 clk[0]:46 0.0001922867 +10 cbx_1__1__1_chanx_right_out[16]:4 clk[0]:47 7.146557e-06 +11 cbx_1__1__1_chanx_right_out[16]:6 clk[0]:45 0.0001922867 +12 cbx_1__1__1_chanx_right_out[16]:3 direct_interc_4_out[0]:6 0.0005354855 +13 cbx_1__1__1_chanx_right_out[16]:4 direct_interc_4_out[0]:5 0.0005354855 +14 sb_2__1_:chanx_left_in[16] sb_2__1_:chanx_left_out[10] 2.585295e-05 +15 cbx_1__1__1_chanx_right_out[16]:2 cbx_2__1_:chanx_right_in[10] 2.585295e-05 + +*RES +0 cbx_2__1_:chanx_right_out[16] cbx_1__1__1_chanx_right_out[16]:7 0.003046875 +1 cbx_1__1__1_chanx_right_out[16]:2 sb_2__1_:chanx_left_in[16] 0.0003086333 +2 cbx_1__1__1_chanx_right_out[16]:3 cbx_1__1__1_chanx_right_out[16]:2 0.00341 +3 cbx_1__1__1_chanx_right_out[16]:5 cbx_1__1__1_chanx_right_out[16]:4 0.00341 +4 cbx_1__1__1_chanx_right_out[16]:4 cbx_1__1__1_chanx_right_out[16]:3 0.004365516 +5 cbx_1__1__1_chanx_right_out[16]:7 cbx_1__1__1_chanx_right_out[16]:6 0.00341 +6 cbx_1__1__1_chanx_right_out[16]:6 cbx_1__1__1_chanx_right_out[16]:5 0.001364958 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[17] 0.001430819 //LENGTH 7.660 LUMPCC 0.0003028921 DR + +*CONN +*I cbx_2__1_:chanx_right_out[17] O *L 0 *C 773.570 583.440 +*I sb_2__1_:chanx_left_in[17] I *L 0 *C 781.230 583.440 + +*CAP +0 cbx_2__1_:chanx_right_out[17] 0.0005639633 +1 sb_2__1_:chanx_left_in[17] 0.0005639633 +2 cbx_2__1_:chanx_right_out[17] cbx_2__1_:chanx_right_out[10] 3.524227e-05 +3 sb_2__1_:chanx_left_in[17] sb_2__1_:chanx_left_in[10] 3.524227e-05 +4 cbx_2__1_:chanx_right_out[17] cbx_2__1_:chanx_right_in[14] 0.0001162038 +5 sb_2__1_:chanx_left_in[17] sb_2__1_:chanx_left_out[14] 0.0001162038 + +*RES +0 cbx_2__1_:chanx_right_out[17] sb_2__1_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET cbx_1__1__1_chanx_right_out[19] 0.00413354 //LENGTH 24.195 LUMPCC 0.002256209 DR + +*CONN +*I cbx_2__1_:chanx_right_out[19] O *L 0 *C 769.120 555.030 +*I sb_2__1_:chanx_left_in[19] I *L 0 *C 781.230 563.040 +*N cbx_1__1__1_chanx_right_out[19]:2 *C 775.108 563.040 +*N cbx_1__1__1_chanx_right_out[19]:3 *C 775.100 562.983 +*N cbx_1__1__1_chanx_right_out[19]:4 *C 775.100 553.577 +*N cbx_1__1__1_chanx_right_out[19]:5 *C 775.093 553.520 +*N cbx_1__1__1_chanx_right_out[19]:6 *C 769.140 553.520 +*N cbx_1__1__1_chanx_right_out[19]:7 *C 769.120 553.528 + +*CAP +0 cbx_2__1_:chanx_right_out[19] 0.0001186128 +1 sb_2__1_:chanx_left_in[19] 0.0003644862 +2 cbx_1__1__1_chanx_right_out[19]:2 0.0003644862 +3 cbx_1__1__1_chanx_right_out[19]:3 0.0003318201 +4 cbx_1__1__1_chanx_right_out[19]:4 0.0003318201 +5 cbx_1__1__1_chanx_right_out[19]:5 0.0001237464 +6 cbx_1__1__1_chanx_right_out[19]:6 0.0001237464 +7 cbx_1__1__1_chanx_right_out[19]:7 0.0001186128 +8 cbx_1__1__1_chanx_right_out[19]:5 clk[0]:46 0.0003476924 +9 cbx_1__1__1_chanx_right_out[19]:6 clk[0]:45 0.0003476924 +10 sb_2__1_:chanx_left_in[19] sb_2__1_:chanx_left_in[6] 0.0001063349 +11 cbx_1__1__1_chanx_right_out[19]:2 cbx_2__1_:chanx_right_out[6] 0.0001063349 +12 sb_2__1_:chanx_left_in[19] sb_2__1_:chanx_left_in[11] 2.757648e-05 +13 sb_2__1_:chanx_left_in[19] cbx_1__1__1_chanx_right_out[11]:3 9.011399e-05 +14 sb_2__1_:chanx_left_in[19] cbx_1__1__1_chanx_right_out[11]:5 2.519703e-05 +15 cbx_1__1__1_chanx_right_out[19]:2 cbx_2__1_:chanx_right_out[11] 2.519703e-05 +16 cbx_1__1__1_chanx_right_out[19]:2 cbx_1__1__1_chanx_right_out[11]:2 2.757648e-05 +17 cbx_1__1__1_chanx_right_out[19]:2 cbx_1__1__1_chanx_right_out[11]:4 9.011399e-05 +18 cbx_1__1__1_chanx_right_out[19]:3 direct_interc_1_out[0]:2 7.945814e-05 +19 cbx_1__1__1_chanx_right_out[19]:4 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 7.945814e-05 +20 cbx_1__1__1_chanx_right_out[19]:3 cbx_2__1_:chanx_right_in[15] 4.797034e-07 +21 cbx_1__1__1_chanx_right_out[19]:3 sb_2__1__0_chanx_left_out[15]:6 9.7926e-05 +22 cbx_1__1__1_chanx_right_out[19]:4 sb_2__1__0_chanx_left_out[15]:5 9.7926e-05 +23 cbx_1__1__1_chanx_right_out[19]:4 sb_2__1__0_chanx_left_out[15]:2 4.797034e-07 +24 cbx_1__1__1_chanx_right_out[19]:5 sb_2__1__0_chanx_left_out[15]:4 5.633308e-06 +25 cbx_1__1__1_chanx_right_out[19]:6 sb_2__1__0_chanx_left_out[15]:3 5.633308e-06 +26 cbx_1__1__1_chanx_right_out[19]:5 ctsbuf_net_1221:21 0.0003476924 +27 cbx_1__1__1_chanx_right_out[19]:6 ctsbuf_net_1221:22 0.0003476924 + +*RES +0 cbx_2__1_:chanx_right_out[19] cbx_1__1__1_chanx_right_out[19]:7 0.0002353916 +1 cbx_1__1__1_chanx_right_out[19]:3 cbx_1__1__1_chanx_right_out[19]:2 0.00341 +2 cbx_1__1__1_chanx_right_out[19]:2 sb_2__1_:chanx_left_in[19] 0.0009591916 +3 cbx_1__1__1_chanx_right_out[19]:4 cbx_1__1__1_chanx_right_out[19]:3 0.008397322 +4 cbx_1__1__1_chanx_right_out[19]:5 cbx_1__1__1_chanx_right_out[19]:4 0.00341 +5 cbx_1__1__1_chanx_right_out[19]:6 cbx_1__1__1_chanx_right_out[19]:5 0.0009325583 +6 cbx_1__1__1_chanx_right_out[19]:7 cbx_1__1__1_chanx_right_out[19]:6 0.00341 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_16_[0] 0.0012779 //LENGTH 11.020 LUMPCC 0.0006489825 DR + +*CONN +*I cbx_2__1_:top_grid_pin_16_[0] O *L 0 *C 702.880 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] I *L 0 *C 702.880 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_16_[0] 0.0003144589 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 0.0003144589 +2 cbx_2__1_:top_grid_pin_16_[0] cbx_2__1_:top_grid_pin_18_[0] 0.0001496481 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] 0.0001496481 +4 cbx_2__1_:top_grid_pin_16_[0] cbx_2__1_:top_grid_pin_22_[0] 8.090731e-05 +5 cbx_2__1_:top_grid_pin_16_[0] cbx_1__1__1_top_grid_pin_22_[0]:4 7.839025e-05 +6 cbx_2__1_:top_grid_pin_16_[0] cbx_1__1__1_top_grid_pin_22_[0]:2 1.554563e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_22_[0] 1.554563e-05 +8 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] cbx_1__1__1_top_grid_pin_22_[0]:5 8.090731e-05 +9 grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] cbx_1__1__1_top_grid_pin_22_[0]:3 7.839025e-05 + +*RES +0 cbx_2__1_:top_grid_pin_16_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_18_[0] 0.001239456 //LENGTH 11.020 LUMPCC 0.0005887148 DR + +*CONN +*I cbx_2__1_:top_grid_pin_18_[0] O *L 0 *C 703.800 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] I *L 0 *C 703.800 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_18_[0] 0.0003253703 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] 0.0003253703 +2 cbx_2__1_:top_grid_pin_18_[0] cbx_2__1_:top_grid_pin_16_[0] 0.0001496481 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_16_[0] 0.0001496481 +4 cbx_2__1_:top_grid_pin_18_[0] cbx_2__1_:top_grid_pin_17_[0] 0.0001447094 +5 grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 0.0001447094 + +*RES +0 cbx_2__1_:top_grid_pin_18_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_18_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_19_[0] 0.001384476 //LENGTH 12.500 LUMPCC 0.0003420028 DR + +*CONN +*I cbx_2__1_:top_grid_pin_19_[0] O *L 0 *C 705.640 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_19_[0] I *L 0 *C 705.640 641.990 +*N cbx_1__1__1_top_grid_pin_19_[0]:2 *C 705.640 639.200 +*N cbx_1__1__1_top_grid_pin_19_[0]:3 *C 705.180 639.200 +*N cbx_1__1__1_top_grid_pin_19_[0]:4 *C 705.180 636.480 +*N cbx_1__1__1_top_grid_pin_19_[0]:5 *C 705.640 636.480 + +*CAP +0 cbx_2__1_:top_grid_pin_19_[0] 0.0001969195 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_19_[0] 0.0001663773 +2 cbx_1__1__1_top_grid_pin_19_[0]:2 0.0001949031 +3 cbx_1__1__1_top_grid_pin_19_[0]:3 0.0001313979 +4 cbx_1__1__1_top_grid_pin_19_[0]:4 0.0001294142 +5 cbx_1__1__1_top_grid_pin_19_[0]:5 0.0002234615 +6 cbx_2__1_:top_grid_pin_19_[0] cbx_2__1_:top_grid_pin_17_[0] 7.866155e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_19_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 1.546943e-05 +8 cbx_1__1__1_top_grid_pin_19_[0]:4 cbx_2__1_:top_grid_pin_17_[0] 7.687044e-05 +9 cbx_1__1__1_top_grid_pin_19_[0]:3 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 7.687044e-05 +10 cbx_1__1__1_top_grid_pin_19_[0]:5 grid_clb_2__2_:bottom_width_0_height_0__pin_17_[0] 7.866155e-05 +11 cbx_1__1__1_top_grid_pin_19_[0]:2 cbx_2__1_:top_grid_pin_17_[0] 1.546943e-05 + +*RES +0 cbx_2__1_:top_grid_pin_19_[0] cbx_1__1__1_top_grid_pin_19_[0]:5 0.004919643 +1 cbx_1__1__1_top_grid_pin_19_[0]:4 cbx_1__1__1_top_grid_pin_19_[0]:3 0.002428572 +2 cbx_1__1__1_top_grid_pin_19_[0]:3 cbx_1__1__1_top_grid_pin_19_[0]:2 0.0004107143 +3 cbx_1__1__1_top_grid_pin_19_[0]:5 cbx_1__1__1_top_grid_pin_19_[0]:4 0.0004107143 +4 cbx_1__1__1_top_grid_pin_19_[0]:2 grid_clb_2__2_:bottom_width_0_height_0__pin_19_[0] 0.002491071 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_21_[0] 0.001400585 //LENGTH 12.500 LUMPCC 0.0003399036 DR + +*CONN +*I cbx_2__1_:top_grid_pin_21_[0] O *L 0 *C 684.940 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_21_[0] I *L 0 *C 684.940 641.990 +*N cbx_1__1__1_top_grid_pin_21_[0]:2 *C 684.940 639.200 +*N cbx_1__1__1_top_grid_pin_21_[0]:3 *C 684.480 639.200 +*N cbx_1__1__1_top_grid_pin_21_[0]:4 *C 684.480 636.480 +*N cbx_1__1__1_top_grid_pin_21_[0]:5 *C 684.940 636.480 + +*CAP +0 cbx_2__1_:top_grid_pin_21_[0] 0.0002018432 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_21_[0] 0.0001675916 +2 cbx_1__1__1_top_grid_pin_21_[0]:2 0.0001966657 +3 cbx_1__1__1_top_grid_pin_21_[0]:3 0.0001334733 +4 cbx_1__1__1_top_grid_pin_21_[0]:4 0.0001318317 +5 cbx_1__1__1_top_grid_pin_21_[0]:5 0.0002292758 +6 cbx_2__1_:top_grid_pin_21_[0] cbx_2__1_:top_grid_pin_23_[0] 7.794624e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_21_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 1.535413e-05 +8 cbx_1__1__1_top_grid_pin_21_[0]:4 cbx_2__1_:top_grid_pin_23_[0] 7.665145e-05 +9 cbx_1__1__1_top_grid_pin_21_[0]:3 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 7.665145e-05 +10 cbx_1__1__1_top_grid_pin_21_[0]:5 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 7.794624e-05 +11 cbx_1__1__1_top_grid_pin_21_[0]:2 cbx_2__1_:top_grid_pin_23_[0] 1.535413e-05 + +*RES +0 cbx_2__1_:top_grid_pin_21_[0] cbx_1__1__1_top_grid_pin_21_[0]:5 0.004919643 +1 cbx_1__1__1_top_grid_pin_21_[0]:4 cbx_1__1__1_top_grid_pin_21_[0]:3 0.002428572 +2 cbx_1__1__1_top_grid_pin_21_[0]:3 cbx_1__1__1_top_grid_pin_21_[0]:2 0.0004107143 +3 cbx_1__1__1_top_grid_pin_21_[0]:5 cbx_1__1__1_top_grid_pin_21_[0]:4 0.0004107143 +4 cbx_1__1__1_top_grid_pin_21_[0]:2 grid_clb_2__2_:bottom_width_0_height_0__pin_21_[0] 0.002491071 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_23_[0] 0.001297385 //LENGTH 11.020 LUMPCC 0.0006264478 DR + +*CONN +*I cbx_2__1_:top_grid_pin_23_[0] O *L 0 *C 684.020 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] I *L 0 *C 684.020 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_23_[0] 0.0003354688 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 0.0003354688 +2 cbx_2__1_:top_grid_pin_23_[0] cbx_2__1_:top_grid_pin_21_[0] 7.794624e-05 +3 cbx_2__1_:top_grid_pin_23_[0] cbx_1__1__1_top_grid_pin_21_[0]:2 1.535413e-05 +4 cbx_2__1_:top_grid_pin_23_[0] cbx_1__1__1_top_grid_pin_21_[0]:4 7.665145e-05 +5 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_21_[0] 1.535413e-05 +6 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] cbx_1__1__1_top_grid_pin_21_[0]:3 7.665145e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] cbx_1__1__1_top_grid_pin_21_[0]:5 7.794624e-05 +8 cbx_2__1_:top_grid_pin_23_[0] cbx_2__1_:top_grid_pin_27_[0] 0.0001432721 +9 grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] 0.0001432721 + +*RES +0 cbx_2__1_:top_grid_pin_23_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_24_[0] 0.001093836 //LENGTH 11.020 LUMPCC 3.737187e-05 DR + +*CONN +*I cbx_2__1_:top_grid_pin_24_[0] O *L 0 *C 671.140 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_24_[0] I *L 0 *C 671.140 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_24_[0] 0.0005282321 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_24_[0] 0.0005282321 +2 cbx_2__1_:top_grid_pin_24_[0] cbx_2__1_:chanx_left_out[18] 1.868594e-05 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_24_[0] cbx_1__1__1_chanx_left_out[18]:9 1.868594e-05 + +*RES +0 cbx_2__1_:top_grid_pin_24_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_24_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_25_[0] 0.001168915 //LENGTH 11.020 LUMPCC 0.0002865441 DR + +*CONN +*I cbx_2__1_:top_grid_pin_25_[0] O *L 0 *C 681.260 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_25_[0] I *L 0 *C 681.260 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_25_[0] 0.0004411852 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_25_[0] 0.0004411852 +2 cbx_2__1_:top_grid_pin_25_[0] cbx_2__1_:top_grid_pin_26_[0] 0.0001432721 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_25_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] 0.0001432721 + +*RES +0 cbx_2__1_:top_grid_pin_25_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_25_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_27_[0] 0.001248031 //LENGTH 11.020 LUMPCC 0.0005730883 DR + +*CONN +*I cbx_2__1_:top_grid_pin_27_[0] O *L 0 *C 683.100 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] I *L 0 *C 683.100 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_27_[0] 0.0003374711 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] 0.0003374711 +2 cbx_2__1_:top_grid_pin_27_[0] cbx_2__1_:top_grid_pin_23_[0] 0.0001432721 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_23_[0] 0.0001432721 +4 cbx_2__1_:top_grid_pin_27_[0] cbx_2__1_:top_grid_pin_26_[0] 0.0001432721 +5 grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_26_[0] 0.0001432721 + +*RES +0 cbx_2__1_:top_grid_pin_27_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_27_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_28_[0] 0.001137818 //LENGTH 11.020 LUMPCC 0.0003002025 DR + +*CONN +*I cbx_2__1_:top_grid_pin_28_[0] O *L 0 *C 742.440 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_28_[0] I *L 0 *C 742.440 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_28_[0] 0.000418808 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_28_[0] 0.000418808 +2 cbx_2__1_:top_grid_pin_28_[0] cbx_2__1_:top_grid_pin_29_[0] 0.0001501012 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_28_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] 0.0001501012 + +*RES +0 cbx_2__1_:top_grid_pin_28_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_28_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_29_[0] 0.001226738 //LENGTH 11.020 LUMPCC 0.000600405 DR + +*CONN +*I cbx_2__1_:top_grid_pin_29_[0] O *L 0 *C 743.360 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] I *L 0 *C 743.360 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_29_[0] 0.0003131665 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] 0.0003131665 +2 cbx_2__1_:top_grid_pin_29_[0] cbx_2__1_:top_grid_pin_28_[0] 0.0001501012 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_28_[0] 0.0001501012 +4 cbx_2__1_:top_grid_pin_29_[0] cbx_2__1_:top_grid_pin_31_[0] 0.0001501012 +5 grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 0.0001501012 + +*RES +0 cbx_2__1_:top_grid_pin_29_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] 0.009839285 + +*END + +*D_NET cbx_1__1__1_top_grid_pin_31_[0] 0.001294734 //LENGTH 11.020 LUMPCC 0.000639684 DR + +*CONN +*I cbx_2__1_:top_grid_pin_31_[0] O *L 0 *C 744.280 630.970 +*I grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] I *L 0 *C 744.280 641.990 + +*CAP +0 cbx_2__1_:top_grid_pin_31_[0] 0.0003275252 +1 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 0.0003275252 +2 cbx_2__1_:top_grid_pin_31_[0] cbx_2__1_:top_grid_pin_29_[0] 0.0001501012 +3 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_29_[0] 0.0001501012 +4 cbx_2__1_:top_grid_pin_31_[0] cbx_2__1_:top_grid_pin_30_[0] 7.782238e-05 +5 cbx_2__1_:top_grid_pin_31_[0] cbx_1__1__1_top_grid_pin_30_[0]:2 1.533745e-05 +6 cbx_2__1_:top_grid_pin_31_[0] cbx_1__1__1_top_grid_pin_30_[0]:4 7.658094e-05 +7 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_30_[0] 1.533745e-05 +8 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] cbx_1__1__1_top_grid_pin_30_[0]:3 7.658094e-05 +9 grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] cbx_1__1__1_top_grid_pin_30_[0]:5 7.782238e-05 + +*RES +0 cbx_2__1_:top_grid_pin_31_[0] grid_clb_2__2_:bottom_width_0_height_0__pin_31_[0] 0.009839285 + +*END + +*D_NET cbx_1__2__0_ccff_tail[0] 0.001117431 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__2_:ccff_tail[0] O *L 0 *C 465.060 892.090 +*I grid_io_top_1__3_:ccff_head[0] I *L 0 *C 465.060 903.110 + +*CAP +0 cbx_1__2_:ccff_tail[0] 0.0005587155 +1 grid_io_top_1__3_:ccff_head[0] 0.0005587155 + +*RES +0 cbx_1__2_:ccff_tail[0] grid_io_top_1__3_:ccff_head[0] 0.009839286 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[0] 0.003135688 //LENGTH 28.550 LUMPCC 0.0004331664 DR + +*CONN +*I cbx_1__2_:chanx_left_out[0] O *L 0 *C 409.860 892.090 +*I sb_0__2_:chanx_right_in[0] I *L 0 *C 400.050 875.840 +*N cbx_1__2__0_chanx_left_out[0]:2 *C 405.252 875.840 +*N cbx_1__2__0_chanx_left_out[0]:3 *C 405.260 875.898 +*N cbx_1__2__0_chanx_left_out[0]:4 *C 405.260 891.519 +*N cbx_1__2__0_chanx_left_out[0]:5 *C 405.260 891.520 +*N cbx_1__2__0_chanx_left_out[0]:6 *C 405.260 892.795 +*N cbx_1__2__0_chanx_left_out[0]:7 *C 405.305 892.840 +*N cbx_1__2__0_chanx_left_out[0]:8 *C 409.815 892.840 +*N cbx_1__2__0_chanx_left_out[0]:9 *C 409.860 892.795 + +*CAP +0 cbx_1__2_:chanx_left_out[0] 5.266827e-05 +1 sb_0__2_:chanx_right_in[0] 0.0002428852 +2 cbx_1__2__0_chanx_left_out[0]:2 0.0002428852 +3 cbx_1__2__0_chanx_left_out[0]:3 0.0007066572 +4 cbx_1__2__0_chanx_left_out[0]:4 0.0007066572 +5 cbx_1__2__0_chanx_left_out[0]:5 6.981714e-05 +6 cbx_1__2__0_chanx_left_out[0]:6 6.981714e-05 +7 cbx_1__2__0_chanx_left_out[0]:7 0.000279233 +8 cbx_1__2__0_chanx_left_out[0]:8 0.000279233 +9 cbx_1__2__0_chanx_left_out[0]:9 5.266827e-05 +10 sb_0__2_:chanx_right_in[0] sb_0__2_:chanx_right_out[8] 0.0001082916 +11 cbx_1__2__0_chanx_left_out[0]:2 cbx_1__2_:chanx_left_in[8] 0.0001082916 +12 sb_0__2_:chanx_right_in[0] sb_0__2_:chanx_right_out[17] 0.0001082916 +13 cbx_1__2__0_chanx_left_out[0]:2 cbx_1__2_:chanx_left_in[17] 0.0001082916 + +*RES +0 cbx_1__2_:chanx_left_out[0] cbx_1__2__0_chanx_left_out[0]:9 0.0006294643 +1 cbx_1__2__0_chanx_left_out[0]:3 cbx_1__2__0_chanx_left_out[0]:2 0.00341 +2 cbx_1__2__0_chanx_left_out[0]:2 sb_0__2_:chanx_right_in[0] 0.0008150584 +3 cbx_1__2__0_chanx_left_out[0]:7 cbx_1__2__0_chanx_left_out[0]:6 0.0045 +4 cbx_1__2__0_chanx_left_out[0]:6 cbx_1__2__0_chanx_left_out[0]:5 0.001138393 +5 cbx_1__2__0_chanx_left_out[0]:8 cbx_1__2__0_chanx_left_out[0]:7 0.004026786 +6 cbx_1__2__0_chanx_left_out[0]:9 cbx_1__2__0_chanx_left_out[0]:8 0.0045 +7 cbx_1__2__0_chanx_left_out[0]:5 cbx_1__2__0_chanx_left_out[0]:4 1e-05 +8 cbx_1__2__0_chanx_left_out[0]:4 cbx_1__2__0_chanx_left_out[0]:3 0.01394777 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[2] 0.001125932 //LENGTH 7.660 LUMPCC 0.0001801345 DR + +*CONN +*I cbx_1__2_:chanx_left_out[2] O *L 0 *C 407.710 888.080 +*I sb_0__2_:chanx_right_in[2] I *L 0 *C 400.050 888.080 + +*CAP +0 cbx_1__2_:chanx_left_out[2] 0.0004728989 +1 sb_0__2_:chanx_right_in[2] 0.0004728989 +2 cbx_1__2_:chanx_left_out[2] cbx_1__2_:chanx_left_out[3] 6.427897e-05 +3 sb_0__2_:chanx_right_in[2] sb_0__2_:chanx_right_in[3] 6.427897e-05 +4 cbx_1__2_:chanx_left_out[2] ctsbuf_net_514:14 2.578827e-05 +5 sb_0__2_:chanx_right_in[2] ctsbuf_net_514:15 2.578827e-05 + +*RES +0 cbx_1__2_:chanx_left_out[2] sb_0__2_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[3] 0.001227517 //LENGTH 7.660 LUMPCC 0.0004494096 DR + +*CONN +*I cbx_1__2_:chanx_left_out[3] O *L 0 *C 407.710 885.360 +*I sb_0__2_:chanx_right_in[3] I *L 0 *C 400.050 885.360 + +*CAP +0 cbx_1__2_:chanx_left_out[3] 0.0003890537 +1 sb_0__2_:chanx_right_in[3] 0.0003890537 +2 cbx_1__2_:chanx_left_out[3] cbx_1__2_:chanx_left_out[2] 6.427897e-05 +3 sb_0__2_:chanx_right_in[3] sb_0__2_:chanx_right_in[2] 6.427897e-05 +4 cbx_1__2_:chanx_left_out[3] cbx_1__2_:chanx_left_in[5] 0.0001604258 +5 sb_0__2_:chanx_right_in[3] sb_0__2_:chanx_right_out[5] 0.0001604258 + +*RES +0 cbx_1__2_:chanx_left_out[3] sb_0__2_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[4] 0.001232103 //LENGTH 7.660 LUMPCC 0.0004477653 DR + +*CONN +*I cbx_1__2_:chanx_left_out[4] O *L 0 *C 407.710 822.800 +*I sb_0__2_:chanx_right_in[4] I *L 0 *C 400.050 822.800 + +*CAP +0 cbx_1__2_:chanx_left_out[4] 0.0003921688 +1 sb_0__2_:chanx_right_in[4] 0.0003921688 +2 cbx_1__2_:chanx_left_out[4] cbx_1__2_:chanx_left_out[6] 6.396315e-05 +3 sb_0__2_:chanx_right_in[4] sb_0__2_:chanx_right_in[6] 6.396315e-05 +4 cbx_1__2_:chanx_left_out[4] cbx_1__2_:chanx_left_out[9] 0.0001599195 +5 sb_0__2_:chanx_right_in[4] sb_0__2_:chanx_right_in[9] 0.0001599195 + +*RES +0 cbx_1__2_:chanx_left_out[4] sb_0__2_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[6] 0.001115427 //LENGTH 7.660 LUMPCC 0.0001279263 DR + +*CONN +*I cbx_1__2_:chanx_left_out[6] O *L 0 *C 407.710 820.080 +*I sb_0__2_:chanx_right_in[6] I *L 0 *C 400.050 820.080 + +*CAP +0 cbx_1__2_:chanx_left_out[6] 0.0004937505 +1 sb_0__2_:chanx_right_in[6] 0.0004937505 +2 cbx_1__2_:chanx_left_out[6] cbx_1__2_:chanx_left_out[4] 6.396315e-05 +3 sb_0__2_:chanx_right_in[6] sb_0__2_:chanx_right_in[4] 6.396315e-05 + +*RES +0 cbx_1__2_:chanx_left_out[6] sb_0__2_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[7] 0.001212775 //LENGTH 7.660 LUMPCC 0.0004679013 DR + +*CONN +*I cbx_1__2_:chanx_left_out[7] O *L 0 *C 407.710 839.120 +*I sb_0__2_:chanx_right_in[7] I *L 0 *C 400.050 839.120 + +*CAP +0 cbx_1__2_:chanx_left_out[7] 0.0003724369 +1 sb_0__2_:chanx_right_in[7] 0.0003724369 +2 cbx_1__2_:chanx_left_out[7] cbx_1__2_:chanx_left_in[1] 7.013153e-05 +3 sb_0__2_:chanx_right_in[7] sb_0__2_:chanx_right_out[1] 7.013153e-05 +4 cbx_1__2_:chanx_left_out[7] cbx_1__2_:chanx_left_in[10] 0.0001638191 +5 sb_0__2_:chanx_right_in[7] sb_0__2_:chanx_right_out[10] 0.0001638191 + +*RES +0 cbx_1__2_:chanx_left_out[7] sb_0__2_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[8] 0.001217381 //LENGTH 7.660 LUMPCC 0.0004650371 DR + +*CONN +*I cbx_1__2_:chanx_left_out[8] O *L 0 *C 407.710 866.320 +*I sb_0__2_:chanx_right_in[8] I *L 0 *C 400.050 866.320 + +*CAP +0 cbx_1__2_:chanx_left_out[8] 0.0003761717 +1 sb_0__2_:chanx_right_in[8] 0.0003761717 +2 cbx_1__2_:chanx_left_out[8] cbx_1__2_:chanx_left_out[12] 6.935707e-05 +3 sb_0__2_:chanx_right_in[8] sb_0__2_:chanx_right_in[12] 6.935707e-05 +4 cbx_1__2_:chanx_left_out[8] cbx_1__2_:chanx_left_in[4] 0.0001631615 +5 sb_0__2_:chanx_right_in[8] sb_0__2_:chanx_right_out[4] 0.0001631615 + +*RES +0 cbx_1__2_:chanx_left_out[8] sb_0__2_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[10] 0.001230712 //LENGTH 7.660 LUMPCC 0.0004389908 DR + +*CONN +*I cbx_1__2_:chanx_left_out[10] O *L 0 *C 407.710 869.040 +*I sb_0__2_:chanx_right_in[10] I *L 0 *C 400.050 869.040 + +*CAP +0 cbx_1__2_:chanx_left_out[10] 0.0003958607 +1 sb_0__2_:chanx_right_in[10] 0.0003958607 +2 cbx_1__2_:chanx_left_out[10] cbx_1__2_:chanx_left_in[3] 5.655564e-05 +3 sb_0__2_:chanx_right_in[10] sb_0__2_:chanx_right_out[3] 5.655564e-05 +4 cbx_1__2_:chanx_left_out[10] cbx_1__2_:chanx_left_in[4] 0.0001629397 +5 sb_0__2_:chanx_right_in[10] sb_0__2_:chanx_right_out[4] 0.0001629397 + +*RES +0 cbx_1__2_:chanx_left_out[10] sb_0__2_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[11] 0.001206817 //LENGTH 7.660 LUMPCC 0.000464411 DR + +*CONN +*I cbx_1__2_:chanx_left_out[11] O *L 0 *C 407.710 847.280 +*I sb_0__2_:chanx_right_in[11] I *L 0 *C 400.050 847.280 + +*CAP +0 cbx_1__2_:chanx_left_out[11] 0.0003712032 +1 sb_0__2_:chanx_right_in[11] 0.0003712032 +2 cbx_1__2_:chanx_left_out[11] cbx_1__2_:chanx_left_out[1] 0.0001633815 +3 sb_0__2_:chanx_right_in[11] sb_0__2_:chanx_right_in[1] 0.0001633815 +4 cbx_1__2_:chanx_left_out[11] cbx_1__2_:chanx_left_out[17] 6.882404e-05 +5 sb_0__2_:chanx_right_in[11] sb_0__2_:chanx_right_in[17] 6.882404e-05 + +*RES +0 cbx_1__2_:chanx_left_out[11] sb_0__2_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[12] 0.001208409 //LENGTH 7.660 LUMPCC 0.0004690819 DR + +*CONN +*I cbx_1__2_:chanx_left_out[12] O *L 0 *C 407.710 863.600 +*I sb_0__2_:chanx_right_in[12] I *L 0 *C 400.050 863.600 + +*CAP +0 cbx_1__2_:chanx_left_out[12] 0.0003696635 +1 sb_0__2_:chanx_right_in[12] 0.0003696635 +2 cbx_1__2_:chanx_left_out[12] cbx_1__2_:chanx_left_out[8] 6.935707e-05 +3 sb_0__2_:chanx_right_in[12] sb_0__2_:chanx_right_in[8] 6.935707e-05 +4 cbx_1__2_:chanx_left_out[12] cbx_1__2_:chanx_left_in[0] 0.0001651839 +5 sb_0__2_:chanx_right_in[12] sb_0__2_:chanx_right_out[0] 0.0001651839 + +*RES +0 cbx_1__2_:chanx_left_out[12] sb_0__2_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[14] 0.003441827 //LENGTH 30.850 LUMPCC 0.0004239595 DR + +*CONN +*I cbx_1__2_:chanx_left_out[14] O *L 0 *C 412.160 816.070 +*I sb_0__2_:chanx_right_in[14] I *L 0 *C 400.050 832.320 +*N cbx_1__2__0_chanx_left_out[14]:2 *C 405.252 832.320 +*N cbx_1__2__0_chanx_left_out[14]:3 *C 405.260 832.263 +*N cbx_1__2__0_chanx_left_out[14]:4 *C 405.260 815.365 +*N cbx_1__2__0_chanx_left_out[14]:5 *C 405.305 815.320 +*N cbx_1__2__0_chanx_left_out[14]:6 *C 412.115 815.320 +*N cbx_1__2__0_chanx_left_out[14]:7 *C 412.160 815.365 + +*CAP +0 cbx_1__2_:chanx_left_out[14] 7.10261e-05 +1 sb_0__2_:chanx_right_in[14] 0.0002490066 +2 cbx_1__2__0_chanx_left_out[14]:2 0.0002490066 +3 cbx_1__2__0_chanx_left_out[14]:3 0.0007849797 +4 cbx_1__2__0_chanx_left_out[14]:4 0.0007849797 +5 cbx_1__2__0_chanx_left_out[14]:5 0.0004039214 +6 cbx_1__2__0_chanx_left_out[14]:6 0.0004039214 +7 cbx_1__2__0_chanx_left_out[14]:7 7.10261e-05 +8 sb_0__2_:chanx_right_in[14] sb_0__2_:chanx_right_out[9] 0.0001059899 +9 cbx_1__2__0_chanx_left_out[14]:2 cbx_1__2_:chanx_left_in[9] 0.0001059899 +10 sb_0__2_:chanx_right_in[14] sb_0__2_:chanx_right_out[12] 0.0001059899 +11 cbx_1__2__0_chanx_left_out[14]:2 cbx_1__2_:chanx_left_in[12] 0.0001059899 + +*RES +0 cbx_1__2_:chanx_left_out[14] cbx_1__2__0_chanx_left_out[14]:7 0.0006294643 +1 cbx_1__2__0_chanx_left_out[14]:3 cbx_1__2__0_chanx_left_out[14]:2 0.00341 +2 cbx_1__2__0_chanx_left_out[14]:2 sb_0__2_:chanx_right_in[14] 0.0008150584 +3 cbx_1__2__0_chanx_left_out[14]:5 cbx_1__2__0_chanx_left_out[14]:4 0.0045 +4 cbx_1__2__0_chanx_left_out[14]:4 cbx_1__2__0_chanx_left_out[14]:3 0.01508706 +5 cbx_1__2__0_chanx_left_out[14]:6 cbx_1__2__0_chanx_left_out[14]:5 0.006080357 +6 cbx_1__2__0_chanx_left_out[14]:7 cbx_1__2__0_chanx_left_out[14]:6 0.0045 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[15] 0.001226487 //LENGTH 7.660 LUMPCC 0.0004411092 DR + +*CONN +*I cbx_1__2_:chanx_left_out[15] O *L 0 *C 407.710 844.560 +*I sb_0__2_:chanx_right_in[15] I *L 0 *C 400.050 844.560 + +*CAP +0 cbx_1__2_:chanx_left_out[15] 0.0003926888 +1 sb_0__2_:chanx_right_in[15] 0.0003926888 +2 cbx_1__2_:chanx_left_out[15] cbx_1__2_:chanx_left_out[1] 0.0001631597 +3 sb_0__2_:chanx_right_in[15] sb_0__2_:chanx_right_in[1] 0.0001631597 +4 cbx_1__2_:chanx_left_out[15] cbx_1__2_:chanx_left_in[2] 5.73949e-05 +5 sb_0__2_:chanx_right_in[15] sb_0__2_:chanx_right_out[2] 5.73949e-05 + +*RES +0 cbx_1__2_:chanx_left_out[15] sb_0__2_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[16] 0.00130471 //LENGTH 7.660 LUMPCC 0.0006465855 DR + +*CONN +*I cbx_1__2_:chanx_left_out[16] O *L 0 *C 407.710 829.600 +*I sb_0__2_:chanx_right_in[16] I *L 0 *C 400.050 829.600 + +*CAP +0 cbx_1__2_:chanx_left_out[16] 0.0003290622 +1 sb_0__2_:chanx_right_in[16] 0.0003290622 +2 cbx_1__2_:chanx_left_out[16] cbx_1__2_:chanx_left_out[18] 0.0001613748 +3 sb_0__2_:chanx_right_in[16] sb_0__2_:chanx_right_in[18] 0.0001613748 +4 cbx_1__2_:chanx_left_out[16] cbx_1__2_:chanx_left_in[12] 0.000161918 +5 sb_0__2_:chanx_right_in[16] sb_0__2_:chanx_right_out[12] 0.000161918 + +*RES +0 cbx_1__2_:chanx_left_out[16] sb_0__2_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[18] 0.001218731 //LENGTH 7.660 LUMPCC 0.0004532069 DR + +*CONN +*I cbx_1__2_:chanx_left_out[18] O *L 0 *C 407.710 828.240 +*I sb_0__2_:chanx_right_in[18] I *L 0 *C 400.050 828.240 + +*CAP +0 cbx_1__2_:chanx_left_out[18] 0.0003827619 +1 sb_0__2_:chanx_right_in[18] 0.0003827619 +2 cbx_1__2_:chanx_left_out[18] cbx_1__2_:chanx_left_out[13] 6.522864e-05 +3 sb_0__2_:chanx_right_in[18] sb_0__2_:chanx_right_in[13] 6.522864e-05 +4 cbx_1__2_:chanx_left_out[18] cbx_1__2_:chanx_left_out[16] 0.0001613748 +5 sb_0__2_:chanx_right_in[18] sb_0__2_:chanx_right_in[16] 0.0001613748 + +*RES +0 cbx_1__2_:chanx_left_out[18] sb_0__2_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_left_out[19] 0.001211303 //LENGTH 7.660 LUMPCC 0.0004659115 DR + +*CONN +*I cbx_1__2_:chanx_left_out[19] O *L 0 *C 407.710 860.880 +*I sb_0__2_:chanx_right_in[19] I *L 0 *C 400.050 860.880 + +*CAP +0 cbx_1__2_:chanx_left_out[19] 0.0003726956 +1 sb_0__2_:chanx_right_in[19] 0.0003726956 +2 cbx_1__2_:chanx_left_out[19] cbx_1__2_:chanx_left_in[0] 0.0001651839 +3 sb_0__2_:chanx_right_in[19] sb_0__2_:chanx_right_out[0] 0.0001651839 +4 cbx_1__2_:chanx_left_out[19] cbx_1__2_:chanx_left_in[11] 6.777188e-05 +5 sb_0__2_:chanx_right_in[19] sb_0__2_:chanx_right_out[11] 6.777188e-05 + +*RES +0 cbx_1__2_:chanx_left_out[19] sb_0__2_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[1] 0.001332769 //LENGTH 7.660 LUMPCC 0.0003828932 DR + +*CONN +*I cbx_1__2_:chanx_right_out[1] O *L 0 *C 512.290 830.960 +*I sb_1__2_:chanx_left_in[1] I *L 0 *C 519.950 830.960 + +*CAP +0 cbx_1__2_:chanx_right_out[1] 0.000474938 +1 sb_1__2_:chanx_left_in[1] 0.000474938 +2 cbx_1__2_:chanx_right_out[1] cbx_1__2_:chanx_right_out[0] 5.062331e-05 +3 sb_1__2_:chanx_left_in[1] sb_1__2_:chanx_left_in[0] 5.062331e-05 +4 cbx_1__2_:chanx_right_out[1] cbx_1__2_:chanx_right_in[6] 0.0001408233 +5 sb_1__2_:chanx_left_in[1] sb_1__2_:chanx_left_out[6] 0.0001408233 + +*RES +0 cbx_1__2_:chanx_right_out[1] sb_1__2_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[2] 0.006071285 //LENGTH 47.660 LUMPCC 0.001805661 DR + +*CONN +*I cbx_1__2_:chanx_right_out[2] O *L 0 *C 510.140 892.090 +*I sb_1__2_:chanx_left_in[2] I *L 0 *C 519.950 856.800 +*N cbx_1__2__0_chanx_right_out[2]:2 *C 515.220 856.800 +*N cbx_1__2__0_chanx_right_out[2]:3 *C 515.200 856.808 +*N cbx_1__2__0_chanx_right_out[2]:4 *C 515.200 891.519 +*N cbx_1__2__0_chanx_right_out[2]:5 *C 515.200 891.520 +*N cbx_1__2__0_chanx_right_out[2]:6 *C 515.200 892.833 +*N cbx_1__2__0_chanx_right_out[2]:7 *C 515.180 892.840 +*N cbx_1__2__0_chanx_right_out[2]:8 *C 510.148 892.840 +*N cbx_1__2__0_chanx_right_out[2]:9 *C 510.140 892.783 + +*CAP +0 cbx_1__2_:chanx_right_out[2] 5.290293e-05 +1 sb_1__2_:chanx_left_in[2] 0.0002048256 +2 cbx_1__2__0_chanx_right_out[2]:2 0.0002048256 +3 cbx_1__2__0_chanx_right_out[2]:3 0.001571936 +4 cbx_1__2__0_chanx_right_out[2]:4 0.001571936 +5 cbx_1__2__0_chanx_right_out[2]:5 3.752717e-05 +6 cbx_1__2__0_chanx_right_out[2]:6 3.752717e-05 +7 cbx_1__2__0_chanx_right_out[2]:7 0.00026562 +8 cbx_1__2__0_chanx_right_out[2]:8 0.00026562 +9 cbx_1__2__0_chanx_right_out[2]:9 5.290293e-05 +10 sb_1__2_:chanx_left_in[2] sb_1__2_:chanx_left_out[14] 0.0001036087 +11 cbx_1__2__0_chanx_right_out[2]:2 cbx_1__2_:chanx_right_in[14] 0.0001036087 +12 sb_1__2_:chanx_left_in[2] sb_1__2_:chanx_left_out[18] 0.0001078059 +13 cbx_1__2__0_chanx_right_out[2]:2 cbx_1__2_:chanx_right_in[18] 0.0001078059 +14 cbx_1__2__0_chanx_right_out[2]:7 ctsbuf_net_514:10 0.0001968898 +15 cbx_1__2__0_chanx_right_out[2]:8 ctsbuf_net_514:11 0.0001968898 +16 cbx_1__2__0_chanx_right_out[2]:3 ctsbuf_net_2130:17 5.239841e-05 +17 cbx_1__2__0_chanx_right_out[2]:3 ctsbuf_net_2130:16 0.0004140867 +18 cbx_1__2__0_chanx_right_out[2]:6 ctsbuf_net_2130:13 2.804113e-05 +19 cbx_1__2__0_chanx_right_out[2]:5 ctsbuf_net_2130:14 2.804113e-05 +20 cbx_1__2__0_chanx_right_out[2]:4 ctsbuf_net_2130:16 5.239841e-05 +21 cbx_1__2__0_chanx_right_out[2]:4 ctsbuf_net_2130:15 0.0004140867 + +*RES +0 cbx_1__2_:chanx_right_out[2] cbx_1__2__0_chanx_right_out[2]:9 0.0006183035 +1 cbx_1__2__0_chanx_right_out[2]:2 sb_1__2_:chanx_left_in[2] 0.0007410333 +2 cbx_1__2__0_chanx_right_out[2]:3 cbx_1__2__0_chanx_right_out[2]:2 0.00341 +3 cbx_1__2__0_chanx_right_out[2]:7 cbx_1__2__0_chanx_right_out[2]:6 0.00341 +4 cbx_1__2__0_chanx_right_out[2]:6 cbx_1__2__0_chanx_right_out[2]:5 0.000205625 +5 cbx_1__2__0_chanx_right_out[2]:9 cbx_1__2__0_chanx_right_out[2]:8 0.00341 +6 cbx_1__2__0_chanx_right_out[2]:8 cbx_1__2__0_chanx_right_out[2]:7 0.000788425 +7 cbx_1__2__0_chanx_right_out[2]:5 cbx_1__2__0_chanx_right_out[2]:4 1e-05 +8 cbx_1__2__0_chanx_right_out[2]:4 cbx_1__2__0_chanx_right_out[2]:3 0.005438135 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[4] 0.001291646 //LENGTH 7.660 LUMPCC 0.0003943715 DR + +*CONN +*I cbx_1__2_:chanx_right_out[4] O *L 0 *C 512.290 839.120 +*I sb_1__2_:chanx_left_in[4] I *L 0 *C 519.950 839.120 + +*CAP +0 cbx_1__2_:chanx_right_out[4] 0.0004486371 +1 sb_1__2_:chanx_left_in[4] 0.0004486371 +2 cbx_1__2_:chanx_right_out[4] cbx_1__2_:chanx_right_out[17] 4.821318e-05 +3 sb_1__2_:chanx_left_in[4] sb_1__2_:chanx_left_in[17] 4.821318e-05 +4 cbx_1__2_:chanx_right_out[4] cbx_1__2_:chanx_right_in[3] 0.0001489726 +5 sb_1__2_:chanx_left_in[4] sb_1__2_:chanx_left_out[3] 0.0001489726 + +*RES +0 cbx_1__2_:chanx_right_out[4] sb_1__2_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[5] 0.003863797 //LENGTH 31.340 LUMPCC 0.0008526954 DR + +*CONN +*I cbx_1__2_:chanx_right_out[5] O *L 0 *C 510.140 816.070 +*I sb_1__2_:chanx_left_in[5] I *L 0 *C 519.950 835.040 +*N cbx_1__2__0_chanx_right_out[5]:2 *C 515.220 835.040 +*N cbx_1__2__0_chanx_right_out[5]:3 *C 515.200 835.033 +*N cbx_1__2__0_chanx_right_out[5]:4 *C 515.200 815.327 +*N cbx_1__2__0_chanx_right_out[5]:5 *C 515.180 815.320 +*N cbx_1__2__0_chanx_right_out[5]:6 *C 510.148 815.320 +*N cbx_1__2__0_chanx_right_out[5]:7 *C 510.140 815.378 + +*CAP +0 cbx_1__2_:chanx_right_out[5] 6.375345e-05 +1 sb_1__2_:chanx_left_in[5] 0.0002664318 +2 cbx_1__2__0_chanx_right_out[5]:2 0.0002664318 +3 cbx_1__2__0_chanx_right_out[5]:3 0.0008661339 +4 cbx_1__2__0_chanx_right_out[5]:4 0.0008661339 +5 cbx_1__2__0_chanx_right_out[5]:5 0.0003092316 +6 cbx_1__2__0_chanx_right_out[5]:6 0.0003092316 +7 cbx_1__2__0_chanx_right_out[5]:7 6.375345e-05 +8 sb_1__2_:chanx_left_in[5] sb_1__2_:chanx_left_out[7] 0.0001044988 +9 cbx_1__2__0_chanx_right_out[5]:2 cbx_1__2_:chanx_right_in[7] 0.0001044988 +10 sb_1__2_:chanx_left_in[5] sb_1__2_:chanx_left_out[15] 4.500828e-05 +11 cbx_1__2__0_chanx_right_out[5]:2 cbx_1__2_:chanx_right_in[15] 4.500828e-05 +12 cbx_1__2__0_chanx_right_out[5]:3 ctsbuf_net_2130:16 0.0002768406 +13 cbx_1__2__0_chanx_right_out[5]:4 ctsbuf_net_2130:17 0.0002768406 + +*RES +0 cbx_1__2_:chanx_right_out[5] cbx_1__2__0_chanx_right_out[5]:7 0.0006183035 +1 cbx_1__2__0_chanx_right_out[5]:2 sb_1__2_:chanx_left_in[5] 0.0007410333 +2 cbx_1__2__0_chanx_right_out[5]:3 cbx_1__2__0_chanx_right_out[5]:2 0.00341 +3 cbx_1__2__0_chanx_right_out[5]:5 cbx_1__2__0_chanx_right_out[5]:4 0.00341 +4 cbx_1__2__0_chanx_right_out[5]:4 cbx_1__2__0_chanx_right_out[5]:3 0.003087116 +5 cbx_1__2__0_chanx_right_out[5]:7 cbx_1__2__0_chanx_right_out[5]:6 0.00341 +6 cbx_1__2__0_chanx_right_out[5]:6 cbx_1__2__0_chanx_right_out[5]:5 0.000788425 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[7] 0.001335338 //LENGTH 7.660 LUMPCC 0.0003720468 DR + +*CONN +*I cbx_1__2_:chanx_right_out[7] O *L 0 *C 512.290 860.880 +*I sb_1__2_:chanx_left_in[7] I *L 0 *C 519.950 860.880 + +*CAP +0 cbx_1__2_:chanx_right_out[7] 0.0004816458 +1 sb_1__2_:chanx_left_in[7] 0.0004816458 +2 cbx_1__2_:chanx_right_out[7] cbx_1__2_:chanx_right_out[13] 4.418423e-05 +3 sb_1__2_:chanx_left_in[7] sb_1__2_:chanx_left_in[13] 4.418423e-05 +4 cbx_1__2_:chanx_right_out[7] cbx_1__2_:chanx_right_in[5] 0.0001418392 +5 sb_1__2_:chanx_left_in[7] sb_1__2_:chanx_left_out[5] 0.0001418392 + +*RES +0 cbx_1__2_:chanx_right_out[7] sb_1__2_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[9] 0.001309556 //LENGTH 7.660 LUMPCC 0.0002815941 DR + +*CONN +*I cbx_1__2_:chanx_right_out[9] O *L 0 *C 512.290 888.080 +*I sb_1__2_:chanx_left_in[9] I *L 0 *C 519.950 888.080 + +*CAP +0 cbx_1__2_:chanx_right_out[9] 0.0005139809 +1 sb_1__2_:chanx_left_in[9] 0.0005139809 +2 cbx_1__2_:chanx_right_out[9] cbx_1__2_:chanx_right_in[10] 0.0001407971 +3 sb_1__2_:chanx_left_in[9] sb_1__2_:chanx_left_out[10] 0.0001407971 + +*RES +0 cbx_1__2_:chanx_right_out[9] sb_1__2_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[10] 0.001338931 //LENGTH 7.660 LUMPCC 0.0003688849 DR + +*CONN +*I cbx_1__2_:chanx_right_out[10] O *L 0 *C 512.290 825.520 +*I sb_1__2_:chanx_left_in[10] I *L 0 *C 519.950 825.520 + +*CAP +0 cbx_1__2_:chanx_right_out[10] 0.000485023 +1 sb_1__2_:chanx_left_in[10] 0.000485023 +2 cbx_1__2_:chanx_right_out[10] cbx_1__2_:chanx_right_out[18] 0.0001419348 +3 sb_1__2_:chanx_left_in[10] sb_1__2_:chanx_left_in[18] 0.0001419348 +4 cbx_1__2_:chanx_right_out[10] cbx_1__2_:chanx_right_in[2] 4.250762e-05 +5 sb_1__2_:chanx_left_in[10] sb_1__2_:chanx_left_out[2] 4.250762e-05 + +*RES +0 cbx_1__2_:chanx_right_out[10] sb_1__2_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[12] 0.00139084 //LENGTH 7.660 LUMPCC 0.0005635064 DR + +*CONN +*I cbx_1__2_:chanx_right_out[12] O *L 0 *C 512.290 821.440 +*I sb_1__2_:chanx_left_in[12] I *L 0 *C 519.950 821.440 + +*CAP +0 cbx_1__2_:chanx_right_out[12] 0.0004136666 +1 sb_1__2_:chanx_left_in[12] 0.0004136666 +2 cbx_1__2_:chanx_right_out[12] cbx_1__2_:chanx_right_out[6] 0.0001410465 +3 sb_1__2_:chanx_left_in[12] sb_1__2_:chanx_left_in[6] 0.0001410465 +4 cbx_1__2_:chanx_right_out[12] cbx_1__2_:chanx_right_in[2] 0.0001407067 +5 sb_1__2_:chanx_left_in[12] sb_1__2_:chanx_left_out[2] 0.0001407067 + +*RES +0 cbx_1__2_:chanx_right_out[12] sb_1__2_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[13] 0.001335581 //LENGTH 7.660 LUMPCC 0.0003730943 DR + +*CONN +*I cbx_1__2_:chanx_right_out[13] O *L 0 *C 512.290 863.600 +*I sb_1__2_:chanx_left_in[13] I *L 0 *C 519.950 863.600 + +*CAP +0 cbx_1__2_:chanx_right_out[13] 0.0004812435 +1 sb_1__2_:chanx_left_in[13] 0.0004812435 +2 cbx_1__2_:chanx_right_out[13] cbx_1__2_:chanx_right_out[7] 4.418423e-05 +3 sb_1__2_:chanx_left_in[13] sb_1__2_:chanx_left_in[7] 4.418423e-05 +4 cbx_1__2_:chanx_right_out[13] cbx_1__2_:chanx_right_out[8] 0.0001423629 +5 sb_1__2_:chanx_left_in[13] sb_1__2_:chanx_left_in[8] 0.0001423629 + +*RES +0 cbx_1__2_:chanx_right_out[13] sb_1__2_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[16] 0.001296785 //LENGTH 7.660 LUMPCC 0.0004063108 DR + +*CONN +*I cbx_1__2_:chanx_right_out[16] O *L 0 *C 512.290 844.560 +*I sb_1__2_:chanx_left_in[16] I *L 0 *C 519.950 844.560 + +*CAP +0 cbx_1__2_:chanx_right_out[16] 0.0004452369 +1 sb_1__2_:chanx_left_in[16] 0.0004452369 +2 cbx_1__2_:chanx_right_out[16] cbx_1__2_:chanx_right_in[4] 5.556981e-05 +3 sb_1__2_:chanx_left_in[16] sb_1__2_:chanx_left_out[4] 5.556981e-05 +4 cbx_1__2_:chanx_right_out[16] cbx_1__2_:chanx_right_in[16] 0.0001475856 +5 sb_1__2_:chanx_left_in[16] sb_1__2_:chanx_left_out[16] 0.0001475856 + +*RES +0 cbx_1__2_:chanx_right_out[16] sb_1__2_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[17] 0.001309317 //LENGTH 7.660 LUMPCC 0.0003926721 DR + +*CONN +*I cbx_1__2_:chanx_right_out[17] O *L 0 *C 512.290 841.840 +*I sb_1__2_:chanx_left_in[17] I *L 0 *C 519.950 841.840 + +*CAP +0 cbx_1__2_:chanx_right_out[17] 0.0004583226 +1 sb_1__2_:chanx_left_in[17] 0.0004583226 +2 cbx_1__2_:chanx_right_out[17] cbx_1__2_:chanx_right_out[4] 4.821318e-05 +3 sb_1__2_:chanx_left_in[17] sb_1__2_:chanx_left_in[4] 4.821318e-05 +4 cbx_1__2_:chanx_right_out[17] cbx_1__2_:chanx_right_in[16] 0.0001481229 +5 sb_1__2_:chanx_left_in[17] sb_1__2_:chanx_left_out[16] 0.0001481229 + +*RES +0 cbx_1__2_:chanx_right_out[17] sb_1__2_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[19] 0.001394388 //LENGTH 7.660 LUMPCC 0.0005628581 DR + +*CONN +*I cbx_1__2_:chanx_right_out[19] O *L 0 *C 512.290 870.400 +*I sb_1__2_:chanx_left_in[19] I *L 0 *C 519.950 870.400 + +*CAP +0 cbx_1__2_:chanx_right_out[19] 0.0004157649 +1 sb_1__2_:chanx_left_in[19] 0.0004157649 +2 cbx_1__2_:chanx_right_out[19] cbx_1__2_:chanx_right_in[0] 0.0001404799 +3 sb_1__2_:chanx_left_in[19] sb_1__2_:chanx_left_out[0] 0.0001404799 +4 cbx_1__2_:chanx_right_out[19] cbx_1__2_:chanx_right_in[12] 0.0001409491 +5 sb_1__2_:chanx_left_in[19] sb_1__2_:chanx_left_out[12] 0.0001409491 + +*RES +0 cbx_1__2_:chanx_right_out[19] sb_1__2_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET cbx_1__2__1_ccff_tail[0] 0.001138979 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__2_:ccff_tail[0] O *L 0 *C 726.340 892.090 +*I grid_io_top_2__3_:ccff_head[0] I *L 0 *C 726.340 903.110 + +*CAP +0 cbx_2__2_:ccff_tail[0] 0.0005694894 +1 grid_io_top_2__3_:ccff_head[0] 0.0005694894 + +*RES +0 cbx_2__2_:ccff_tail[0] grid_io_top_2__3_:ccff_head[0] 0.009839286 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[1] 0.001451224 //LENGTH 7.660 LUMPCC 0.0005407982 DR + +*CONN +*I cbx_2__2_:chanx_left_out[1] O *L 0 *C 668.990 845.920 +*I sb_1__2_:chanx_right_in[1] I *L 0 *C 661.330 845.920 +*N cbx_1__2__1_chanx_left_out[1]:2 *C 667.519 845.920 +*N cbx_1__2__1_chanx_left_out[1]:3 *C 667.520 845.920 + +*CAP +0 cbx_2__2_:chanx_left_out[1] 0.0001949588 +1 sb_1__2_:chanx_right_in[1] 0.0002602541 +2 cbx_1__2__1_chanx_left_out[1]:2 0.0002602541 +3 cbx_1__2__1_chanx_left_out[1]:3 0.0001949588 +4 cbx_2__2_:chanx_left_out[1] cbx_2__2_:chanx_left_out[11] 9.861294e-06 +5 sb_1__2_:chanx_right_in[1] sb_1__2_:chanx_right_in[11] 0.000133952 +6 cbx_1__2__1_chanx_left_out[1]:3 cbx_1__2__1_chanx_left_out[11]:3 9.861294e-06 +7 cbx_1__2__1_chanx_left_out[1]:2 cbx_1__2__1_chanx_left_out[11]:2 0.000133952 +8 cbx_2__2_:chanx_left_out[1] cbx_2__2_:chanx_left_out[15] 1.643549e-06 +9 sb_1__2_:chanx_right_in[1] sb_1__2_:chanx_right_in[15] 0.0001249422 +10 cbx_1__2__1_chanx_left_out[1]:3 cbx_1__2__1_chanx_left_out[15]:3 1.643549e-06 +11 cbx_1__2__1_chanx_left_out[1]:2 cbx_1__2__1_chanx_left_out[15]:2 0.0001249422 + +*RES +0 cbx_2__2_:chanx_left_out[1] cbx_1__2__1_chanx_left_out[1]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[1]:3 cbx_1__2__1_chanx_left_out[1]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[1]:2 sb_1__2_:chanx_right_in[1] 0.00096961 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[3] 0.001386761 //LENGTH 7.660 LUMPCC 0.0003681282 DR + +*CONN +*I cbx_2__2_:chanx_left_out[3] O *L 0 *C 668.990 885.360 +*I sb_1__2_:chanx_right_in[3] I *L 0 *C 661.330 885.360 +*N cbx_1__2__1_chanx_left_out[3]:2 *C 667.519 885.360 +*N cbx_1__2__1_chanx_left_out[3]:3 *C 667.520 885.360 + +*CAP +0 cbx_2__2_:chanx_left_out[3] 0.0001868252 +1 sb_1__2_:chanx_right_in[3] 0.0003224909 +2 cbx_1__2__1_chanx_left_out[3]:2 0.0003224909 +3 cbx_1__2__1_chanx_left_out[3]:3 0.0001868252 +4 sb_1__2_:chanx_right_in[3] sb_1__2_:chanx_right_in[2] 5.102319e-05 +5 cbx_1__2__1_chanx_left_out[3]:2 cbx_1__2__1_chanx_left_out[2]:2 5.102319e-05 +6 cbx_2__2_:chanx_left_out[3] cbx_2__2_:chanx_left_in[5] 9.865685e-06 +7 sb_1__2_:chanx_right_in[3] sb_1__2_:chanx_right_out[5] 0.0001231752 +8 cbx_1__2__1_chanx_left_out[3]:3 sb_1__2__0_chanx_right_out[5]:2 9.865685e-06 +9 cbx_1__2__1_chanx_left_out[3]:2 sb_1__2__0_chanx_right_out[5]:3 0.0001231752 + +*RES +0 cbx_2__2_:chanx_left_out[3] cbx_1__2__1_chanx_left_out[3]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[3]:3 cbx_1__2__1_chanx_left_out[3]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[3]:2 sb_1__2_:chanx_right_in[3] 0.00096961 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[5] 0.001508488 //LENGTH 7.660 LUMPCC 0.0004818134 DR + +*CONN +*I cbx_2__2_:chanx_left_out[5] O *L 0 *C 668.990 851.360 +*I sb_1__2_:chanx_right_in[5] I *L 0 *C 661.330 851.360 +*N cbx_1__2__1_chanx_left_out[5]:2 *C 667.519 851.360 +*N cbx_1__2__1_chanx_left_out[5]:3 *C 667.520 851.360 + +*CAP +0 cbx_2__2_:chanx_left_out[5] 0.0002192781 +1 sb_1__2_:chanx_right_in[5] 0.0002940592 +2 cbx_1__2__1_chanx_left_out[5]:2 0.0002940592 +3 cbx_1__2__1_chanx_left_out[5]:3 0.0002192781 +4 sb_1__2_:chanx_right_in[5] sb_1__2_:chanx_right_in[17] 0.0001207714 +5 cbx_1__2__1_chanx_left_out[5]:2 cbx_1__2__1_chanx_left_out[17]:2 0.0001207714 +6 sb_1__2_:chanx_right_in[5] sb_1__2_:chanx_right_out[16] 0.0001201353 +7 cbx_1__2__1_chanx_left_out[5]:2 sb_1__2__0_chanx_right_out[16]:3 0.0001201353 + +*RES +0 cbx_2__2_:chanx_left_out[5] cbx_1__2__1_chanx_left_out[5]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[5]:3 cbx_1__2__1_chanx_left_out[5]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[5]:2 sb_1__2_:chanx_right_in[5] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[7] 0.001337146 //LENGTH 7.660 LUMPCC 0.0004018364 DR + +*CONN +*I cbx_2__2_:chanx_left_out[7] O *L 0 *C 668.990 839.120 +*I sb_1__2_:chanx_right_in[7] I *L 0 *C 661.330 839.120 +*N cbx_1__2__1_chanx_left_out[7]:2 *C 667.519 839.120 +*N cbx_1__2__1_chanx_left_out[7]:3 *C 667.520 839.120 + +*CAP +0 cbx_2__2_:chanx_left_out[7] 0.0001916202 +1 sb_1__2_:chanx_right_in[7] 0.0002760345 +2 cbx_1__2__1_chanx_left_out[7]:2 0.0002760345 +3 cbx_1__2__1_chanx_left_out[7]:3 0.0001916202 +4 sb_1__2_:chanx_right_in[7] sb_1__2_:chanx_right_out[1] 6.398198e-05 +5 cbx_1__2__1_chanx_left_out[7]:2 sb_1__2__0_chanx_right_out[1]:3 6.398198e-05 +6 cbx_2__2_:chanx_left_out[7] cbx_2__2_:chanx_left_in[10] 6.576453e-06 +7 sb_1__2_:chanx_right_in[7] sb_1__2_:chanx_right_out[10] 0.0001303597 +8 cbx_1__2__1_chanx_left_out[7]:3 sb_1__2__0_chanx_right_out[10]:2 6.576453e-06 +9 cbx_1__2__1_chanx_left_out[7]:2 sb_1__2__0_chanx_right_out[10]:3 0.0001303597 + +*RES +0 cbx_2__2_:chanx_left_out[7] cbx_1__2__1_chanx_left_out[7]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[7]:3 cbx_1__2__1_chanx_left_out[7]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[7]:2 sb_1__2_:chanx_right_in[7] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[9] 0.001550462 //LENGTH 7.660 LUMPCC 0.0004364082 DR + +*CONN +*I cbx_2__2_:chanx_left_out[9] O *L 0 *C 668.990 824.160 +*I sb_1__2_:chanx_right_in[9] I *L 0 *C 661.330 824.160 +*N cbx_1__2__1_chanx_left_out[9]:2 *C 667.519 824.160 +*N cbx_1__2__1_chanx_left_out[9]:3 *C 667.520 824.160 + +*CAP +0 cbx_2__2_:chanx_left_out[9] 0.0002200254 +1 sb_1__2_:chanx_right_in[9] 0.0003370013 +2 cbx_1__2__1_chanx_left_out[9]:2 0.0003370013 +3 cbx_1__2__1_chanx_left_out[9]:3 0.0002200254 +4 sb_1__2_:chanx_right_in[9] sb_1__2_:chanx_right_in[4] 0.000109102 +5 cbx_1__2__1_chanx_left_out[9]:2 cbx_1__2__1_chanx_left_out[4]:2 0.000109102 +6 sb_1__2_:chanx_right_in[9] sb_1__2_:chanx_right_in[13] 0.000109102 +7 cbx_1__2__1_chanx_left_out[9]:2 cbx_1__2__1_chanx_left_out[13]:2 0.000109102 + +*RES +0 cbx_2__2_:chanx_left_out[9] cbx_1__2__1_chanx_left_out[9]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[9]:3 cbx_1__2__1_chanx_left_out[9]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[9]:2 sb_1__2_:chanx_right_in[9] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[11] 0.001326239 //LENGTH 7.660 LUMPCC 0.000415635 DR + +*CONN +*I cbx_2__2_:chanx_left_out[11] O *L 0 *C 668.990 847.280 +*I sb_1__2_:chanx_right_in[11] I *L 0 *C 661.330 847.280 +*N cbx_1__2__1_chanx_left_out[11]:2 *C 667.519 847.280 +*N cbx_1__2__1_chanx_left_out[11]:3 *C 667.520 847.280 + +*CAP +0 cbx_2__2_:chanx_left_out[11] 0.0001867774 +1 sb_1__2_:chanx_right_in[11] 0.0002685245 +2 cbx_1__2__1_chanx_left_out[11]:2 0.0002685245 +3 cbx_1__2__1_chanx_left_out[11]:3 0.0001867774 +4 cbx_2__2_:chanx_left_out[11] cbx_2__2_:chanx_left_out[1] 9.861294e-06 +5 sb_1__2_:chanx_right_in[11] sb_1__2_:chanx_right_in[1] 0.000133952 +6 cbx_1__2__1_chanx_left_out[11]:3 cbx_1__2__1_chanx_left_out[1]:3 9.861294e-06 +7 cbx_1__2__1_chanx_left_out[11]:2 cbx_1__2__1_chanx_left_out[1]:2 0.000133952 +8 sb_1__2_:chanx_right_in[11] sb_1__2_:chanx_right_in[17] 6.400417e-05 +9 cbx_1__2__1_chanx_left_out[11]:2 cbx_1__2__1_chanx_left_out[17]:2 6.400417e-05 + +*RES +0 cbx_2__2_:chanx_left_out[11] cbx_1__2__1_chanx_left_out[11]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[11]:3 cbx_1__2__1_chanx_left_out[11]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[11]:2 sb_1__2_:chanx_right_in[11] 0.00096961 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[12] 0.001418869 //LENGTH 7.660 LUMPCC 0.00037198 DR + +*CONN +*I cbx_2__2_:chanx_left_out[12] O *L 0 *C 668.990 863.600 +*I sb_1__2_:chanx_right_in[12] I *L 0 *C 661.330 863.600 +*N cbx_1__2__1_chanx_left_out[12]:2 *C 667.519 863.600 +*N cbx_1__2__1_chanx_left_out[12]:3 *C 667.520 863.600 + +*CAP +0 cbx_2__2_:chanx_left_out[12] 0.0002199879 +1 sb_1__2_:chanx_right_in[12] 0.0003034565 +2 cbx_1__2__1_chanx_left_out[12]:2 0.0003034565 +3 cbx_1__2__1_chanx_left_out[12]:3 0.0002199879 +4 sb_1__2_:chanx_right_in[12] sb_1__2_:chanx_right_in[8] 6.462134e-05 +5 cbx_1__2__1_chanx_left_out[12]:2 cbx_1__2__1_chanx_left_out[8]:2 6.462134e-05 +6 sb_1__2_:chanx_right_in[12] sb_1__2_:chanx_right_out[0] 0.0001213686 +7 cbx_1__2__1_chanx_left_out[12]:2 sb_1__2__0_chanx_right_out[0]:3 0.0001213686 + +*RES +0 cbx_2__2_:chanx_left_out[12] cbx_1__2__1_chanx_left_out[12]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[12]:3 cbx_1__2__1_chanx_left_out[12]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[12]:2 sb_1__2_:chanx_right_in[12] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[15] 0.001427023 //LENGTH 7.660 LUMPCC 0.0003798763 DR + +*CONN +*I cbx_2__2_:chanx_left_out[15] O *L 0 *C 668.990 844.560 +*I sb_1__2_:chanx_right_in[15] I *L 0 *C 661.330 844.560 +*N cbx_1__2__1_chanx_left_out[15]:2 *C 667.519 844.560 +*N cbx_1__2__1_chanx_left_out[15]:3 *C 667.520 844.560 + +*CAP +0 cbx_2__2_:chanx_left_out[15] 0.0002176192 +1 sb_1__2_:chanx_right_in[15] 0.0003059541 +2 cbx_1__2__1_chanx_left_out[15]:2 0.0003059541 +3 cbx_1__2__1_chanx_left_out[15]:3 0.0002176192 +4 cbx_2__2_:chanx_left_out[15] cbx_2__2_:chanx_left_out[1] 1.643549e-06 +5 sb_1__2_:chanx_right_in[15] sb_1__2_:chanx_right_in[1] 0.0001249422 +6 cbx_1__2__1_chanx_left_out[15]:3 cbx_1__2__1_chanx_left_out[1]:3 1.643549e-06 +7 cbx_1__2__1_chanx_left_out[15]:2 cbx_1__2__1_chanx_left_out[1]:2 0.0001249422 +8 sb_1__2_:chanx_right_in[15] sb_1__2_:chanx_right_out[2] 6.33524e-05 +9 cbx_1__2__1_chanx_left_out[15]:2 sb_1__2__0_chanx_right_out[2]:3 6.33524e-05 + +*RES +0 cbx_2__2_:chanx_left_out[15] cbx_1__2__1_chanx_left_out[15]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[15]:3 cbx_1__2__1_chanx_left_out[15]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[15]:2 sb_1__2_:chanx_right_in[15] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[16] 0.001446469 //LENGTH 7.660 LUMPCC 0.0005232542 DR + +*CONN +*I cbx_2__2_:chanx_left_out[16] O *L 0 *C 668.990 829.600 +*I sb_1__2_:chanx_right_in[16] I *L 0 *C 661.330 829.600 +*N cbx_1__2__1_chanx_left_out[16]:2 *C 667.519 829.600 +*N cbx_1__2__1_chanx_left_out[16]:3 *C 667.520 829.600 + +*CAP +0 cbx_2__2_:chanx_left_out[16] 0.0001794724 +1 sb_1__2_:chanx_right_in[16] 0.000282135 +2 cbx_1__2__1_chanx_left_out[16]:2 0.000282135 +3 cbx_1__2__1_chanx_left_out[16]:3 0.0001794724 +4 cbx_2__2_:chanx_left_out[16] cbx_2__2_:chanx_left_out[18] 9.861594e-06 +5 sb_1__2_:chanx_right_in[16] sb_1__2_:chanx_right_in[18] 0.0001246128 +6 cbx_1__2__1_chanx_left_out[16]:3 cbx_1__2__1_chanx_left_out[18]:3 9.861594e-06 +7 cbx_1__2__1_chanx_left_out[16]:2 cbx_1__2__1_chanx_left_out[18]:2 0.0001246128 +8 cbx_2__2_:chanx_left_out[16] cbx_2__2_:chanx_left_in[12] 6.574196e-06 +9 sb_1__2_:chanx_right_in[16] sb_1__2_:chanx_right_out[12] 0.0001205785 +10 cbx_1__2__1_chanx_left_out[16]:3 sb_1__2__0_chanx_right_out[12]:2 6.574196e-06 +11 cbx_1__2__1_chanx_left_out[16]:2 sb_1__2__0_chanx_right_out[12]:3 0.0001205785 + +*RES +0 cbx_2__2_:chanx_left_out[16] cbx_1__2__1_chanx_left_out[16]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[16]:3 cbx_1__2__1_chanx_left_out[16]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[16]:2 sb_1__2_:chanx_right_in[16] 0.00096961 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[18] 0.001377288 //LENGTH 7.660 LUMPCC 0.0003742267 DR + +*CONN +*I cbx_2__2_:chanx_left_out[18] O *L 0 *C 668.990 828.240 +*I sb_1__2_:chanx_right_in[18] I *L 0 *C 661.330 828.240 +*N cbx_1__2__1_chanx_left_out[18]:2 *C 667.519 828.240 +*N cbx_1__2__1_chanx_left_out[18]:3 *C 667.520 828.240 + +*CAP +0 cbx_2__2_:chanx_left_out[18] 0.0001867978 +1 sb_1__2_:chanx_right_in[18] 0.0003147328 +2 cbx_1__2__1_chanx_left_out[18]:2 0.0003147328 +3 cbx_1__2__1_chanx_left_out[18]:3 0.0001867978 +4 sb_1__2_:chanx_right_in[18] sb_1__2_:chanx_right_in[13] 5.263901e-05 +5 cbx_1__2__1_chanx_left_out[18]:2 cbx_1__2__1_chanx_left_out[13]:2 5.263901e-05 +6 cbx_2__2_:chanx_left_out[18] cbx_2__2_:chanx_left_out[16] 9.861594e-06 +7 sb_1__2_:chanx_right_in[18] sb_1__2_:chanx_right_in[16] 0.0001246128 +8 cbx_1__2__1_chanx_left_out[18]:3 cbx_1__2__1_chanx_left_out[16]:3 9.861594e-06 +9 cbx_1__2__1_chanx_left_out[18]:2 cbx_1__2__1_chanx_left_out[16]:2 0.0001246128 + +*RES +0 cbx_2__2_:chanx_left_out[18] cbx_1__2__1_chanx_left_out[18]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[18]:3 cbx_1__2__1_chanx_left_out[18]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[18]:2 sb_1__2_:chanx_right_in[18] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[1] 0.001399302 //LENGTH 7.660 LUMPCC 0.0003548908 DR + +*CONN +*I cbx_2__2_:chanx_right_out[1] O *L 0 *C 773.570 830.960 +*I sb_2__2_:chanx_left_in[1] I *L 0 *C 781.230 830.960 + +*CAP +0 cbx_2__2_:chanx_right_out[1] 0.0005222054 +1 sb_2__2_:chanx_left_in[1] 0.0005222054 +2 cbx_2__2_:chanx_right_out[1] cbx_2__2_:chanx_right_out[0] 6.021191e-05 +3 sb_2__2_:chanx_left_in[1] sb_2__2_:chanx_left_in[0] 6.021191e-05 +4 cbx_2__2_:chanx_right_out[1] cbx_2__2_:chanx_right_in[6] 0.0001172335 +5 sb_2__2_:chanx_left_in[1] sb_2__2_:chanx_left_out[6] 0.0001172335 + +*RES +0 cbx_2__2_:chanx_right_out[1] sb_2__2_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[2] 0.004929621 //LENGTH 47.590 LUMPCC 0.000208162 DR + +*CONN +*I cbx_2__2_:chanx_right_out[2] O *L 0 *C 771.420 892.090 +*I sb_2__2_:chanx_left_in[2] I *L 0 *C 781.230 856.800 +*N cbx_1__2__1_chanx_right_out[2]:2 *C 778.327 856.800 +*N cbx_1__2__1_chanx_right_out[2]:3 *C 778.320 856.858 +*N cbx_1__2__1_chanx_right_out[2]:4 *C 778.320 891.519 +*N cbx_1__2__1_chanx_right_out[2]:5 *C 778.320 891.520 +*N cbx_1__2__1_chanx_right_out[2]:6 *C 778.320 892.795 +*N cbx_1__2__1_chanx_right_out[2]:7 *C 778.275 892.840 +*N cbx_1__2__1_chanx_right_out[2]:8 *C 771.465 892.840 +*N cbx_1__2__1_chanx_right_out[2]:9 *C 771.420 892.795 + +*CAP +0 cbx_2__2_:chanx_right_out[2] 5.197477e-05 +1 sb_2__2_:chanx_left_in[2] 0.0001948617 +2 cbx_1__2__1_chanx_right_out[2]:2 0.0001948617 +3 cbx_1__2__1_chanx_right_out[2]:3 0.001638869 +4 cbx_1__2__1_chanx_right_out[2]:4 0.001638869 +5 cbx_1__2__1_chanx_right_out[2]:5 6.835152e-05 +6 cbx_1__2__1_chanx_right_out[2]:6 6.835152e-05 +7 cbx_1__2__1_chanx_right_out[2]:7 0.0004066722 +8 cbx_1__2__1_chanx_right_out[2]:8 0.0004066722 +9 cbx_1__2__1_chanx_right_out[2]:9 5.197477e-05 +10 sb_2__2_:chanx_left_in[2] sb_2__2_:chanx_left_out[14] 5.135179e-05 +11 cbx_1__2__1_chanx_right_out[2]:2 cbx_2__2_:chanx_right_in[14] 5.135179e-05 +12 sb_2__2_:chanx_left_in[2] sb_2__2_:chanx_left_out[18] 5.272921e-05 +13 cbx_1__2__1_chanx_right_out[2]:2 cbx_2__2_:chanx_right_in[18] 5.272921e-05 + +*RES +0 cbx_2__2_:chanx_right_out[2] cbx_1__2__1_chanx_right_out[2]:9 0.0006294643 +1 cbx_1__2__1_chanx_right_out[2]:3 cbx_1__2__1_chanx_right_out[2]:2 0.00341 +2 cbx_1__2__1_chanx_right_out[2]:2 sb_2__2_:chanx_left_in[2] 0.000454725 +3 cbx_1__2__1_chanx_right_out[2]:7 cbx_1__2__1_chanx_right_out[2]:6 0.0045 +4 cbx_1__2__1_chanx_right_out[2]:6 cbx_1__2__1_chanx_right_out[2]:5 0.001138393 +5 cbx_1__2__1_chanx_right_out[2]:8 cbx_1__2__1_chanx_right_out[2]:7 0.006080357 +6 cbx_1__2__1_chanx_right_out[2]:9 cbx_1__2__1_chanx_right_out[2]:8 0.0045 +7 cbx_1__2__1_chanx_right_out[2]:5 cbx_1__2__1_chanx_right_out[2]:4 1e-05 +8 cbx_1__2__1_chanx_right_out[2]:4 cbx_1__2__1_chanx_right_out[2]:3 0.03094777 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[4] 0.00132647 //LENGTH 7.660 LUMPCC 0.0004147956 DR + +*CONN +*I cbx_2__2_:chanx_right_out[4] O *L 0 *C 773.570 839.120 +*I sb_2__2_:chanx_left_in[4] I *L 0 *C 781.230 839.120 + +*CAP +0 cbx_2__2_:chanx_right_out[4] 0.0004558372 +1 sb_2__2_:chanx_left_in[4] 0.0004558372 +2 cbx_2__2_:chanx_right_out[4] cbx_2__2_:chanx_right_out[17] 6.294859e-05 +3 sb_2__2_:chanx_left_in[4] sb_2__2_:chanx_left_in[17] 6.294859e-05 +4 cbx_2__2_:chanx_right_out[4] cbx_2__2_:chanx_right_in[3] 0.0001444492 +5 sb_2__2_:chanx_left_in[4] sb_2__2_:chanx_left_out[3] 0.0001444492 + +*RES +0 cbx_2__2_:chanx_right_out[4] sb_2__2_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[7] 0.001455807 //LENGTH 7.660 LUMPCC 0.0003523702 DR + +*CONN +*I cbx_2__2_:chanx_right_out[7] O *L 0 *C 773.570 860.880 +*I sb_2__2_:chanx_left_in[7] I *L 0 *C 781.230 860.880 + +*CAP +0 cbx_2__2_:chanx_right_out[7] 0.0005517183 +1 sb_2__2_:chanx_left_in[7] 0.0005517183 +2 cbx_2__2_:chanx_right_out[7] cbx_2__2_:chanx_right_out[13] 6.066482e-05 +3 sb_2__2_:chanx_left_in[7] sb_2__2_:chanx_left_in[13] 6.066482e-05 +4 cbx_2__2_:chanx_right_out[7] cbx_2__2_:chanx_right_in[5] 0.0001155203 +5 sb_2__2_:chanx_left_in[7] sb_2__2_:chanx_left_out[5] 0.0001155203 + +*RES +0 cbx_2__2_:chanx_right_out[7] sb_2__2_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[8] 0.001458782 //LENGTH 7.660 LUMPCC 0.000530927 DR + +*CONN +*I cbx_2__2_:chanx_right_out[8] O *L 0 *C 773.570 864.960 +*I sb_2__2_:chanx_left_in[8] I *L 0 *C 781.230 864.960 + +*CAP +0 cbx_2__2_:chanx_right_out[8] 0.0004639276 +1 sb_2__2_:chanx_left_in[8] 0.0004639276 +2 cbx_2__2_:chanx_right_out[8] cbx_2__2_:chanx_right_out[13] 0.000124901 +3 sb_2__2_:chanx_left_in[8] sb_2__2_:chanx_left_in[13] 0.000124901 +4 cbx_2__2_:chanx_right_out[8] cbx_2__2_:ccff_head[0] 0.0001405625 +5 sb_2__2_:chanx_left_in[8] sb_2__2_:ccff_tail[0] 0.0001405625 + +*RES +0 cbx_2__2_:chanx_right_out[8] sb_2__2_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[11] 0.001434549 //LENGTH 7.660 LUMPCC 0.0003683916 DR + +*CONN +*I cbx_2__2_:chanx_right_out[11] O *L 0 *C 773.570 852.720 +*I sb_2__2_:chanx_left_in[11] I *L 0 *C 781.230 852.720 + +*CAP +0 cbx_2__2_:chanx_right_out[11] 0.0005330786 +1 sb_2__2_:chanx_left_in[11] 0.0005330786 +2 cbx_2__2_:chanx_right_out[11] cbx_2__2_:chanx_right_out[3] 6.375641e-05 +3 sb_2__2_:chanx_left_in[11] sb_2__2_:chanx_left_in[3] 6.375641e-05 +4 cbx_2__2_:chanx_right_out[11] cbx_2__2_:chanx_right_in[9] 0.0001204394 +5 sb_2__2_:chanx_left_in[11] sb_2__2_:chanx_left_out[9] 0.0001204394 + +*RES +0 cbx_2__2_:chanx_right_out[11] sb_2__2_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[12] 0.001462596 //LENGTH 7.660 LUMPCC 0.0004986614 DR + +*CONN +*I cbx_2__2_:chanx_right_out[12] O *L 0 *C 773.570 821.440 +*I sb_2__2_:chanx_left_in[12] I *L 0 *C 781.230 821.440 + +*CAP +0 cbx_2__2_:chanx_right_out[12] 0.0004819673 +1 sb_2__2_:chanx_left_in[12] 0.0004819673 +2 cbx_2__2_:chanx_right_out[12] cbx_2__2_:chanx_right_out[6] 0.0001331701 +3 sb_2__2_:chanx_left_in[12] sb_2__2_:chanx_left_in[6] 0.0001331701 +4 cbx_2__2_:chanx_right_out[12] cbx_2__2_:chanx_right_in[2] 0.0001161606 +5 sb_2__2_:chanx_left_in[12] sb_2__2_:chanx_left_out[2] 0.0001161606 + +*RES +0 cbx_2__2_:chanx_right_out[12] sb_2__2_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[15] 0.001344778 //LENGTH 7.660 LUMPCC 0.0003995032 DR + +*CONN +*I cbx_2__2_:chanx_right_out[15] O *L 0 *C 773.570 885.360 +*I sb_2__2_:chanx_left_in[15] I *L 0 *C 781.230 885.360 + +*CAP +0 cbx_2__2_:chanx_right_out[15] 0.0004726374 +1 sb_2__2_:chanx_left_in[15] 0.0004726374 +2 cbx_2__2_:chanx_right_out[15] cbx_2__2_:chanx_right_in[1] 5.905084e-05 +3 sb_2__2_:chanx_left_in[15] sb_2__2_:chanx_left_out[1] 5.905084e-05 +4 cbx_2__2_:chanx_right_out[15] cbx_2__2_:chanx_right_in[10] 0.0001407008 +5 sb_2__2_:chanx_left_in[15] sb_2__2_:chanx_left_out[10] 0.0001407008 + +*RES +0 cbx_2__2_:chanx_right_out[15] sb_2__2_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[16] 0.001427409 //LENGTH 7.660 LUMPCC 0.0003632026 DR + +*CONN +*I cbx_2__2_:chanx_right_out[16] O *L 0 *C 773.570 844.560 +*I sb_2__2_:chanx_left_in[16] I *L 0 *C 781.230 844.560 + +*CAP +0 cbx_2__2_:chanx_right_out[16] 0.0005321031 +1 sb_2__2_:chanx_left_in[16] 0.0005321031 +2 cbx_2__2_:chanx_right_out[16] cbx_2__2_:chanx_right_in[4] 6.232323e-05 +3 sb_2__2_:chanx_left_in[16] sb_2__2_:chanx_left_out[4] 6.232323e-05 +4 cbx_2__2_:chanx_right_out[16] cbx_2__2_:chanx_right_in[16] 0.0001192781 +5 sb_2__2_:chanx_left_in[16] sb_2__2_:chanx_left_out[16] 0.0001192781 + +*RES +0 cbx_2__2_:chanx_right_out[16] sb_2__2_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[19] 0.001512015 //LENGTH 7.660 LUMPCC 0.0004659384 DR + +*CONN +*I cbx_2__2_:chanx_right_out[19] O *L 0 *C 773.570 870.400 +*I sb_2__2_:chanx_left_in[19] I *L 0 *C 781.230 870.400 + +*CAP +0 cbx_2__2_:chanx_right_out[19] 0.0005230382 +1 sb_2__2_:chanx_left_in[19] 0.0005230382 +2 cbx_2__2_:chanx_right_out[19] cbx_2__2_:chanx_right_in[0] 0.0001159588 +3 sb_2__2_:chanx_left_in[19] sb_2__2_:chanx_left_out[0] 0.0001159588 +4 cbx_2__2_:chanx_right_out[19] cbx_2__2_:chanx_right_in[12] 0.0001170104 +5 sb_2__2_:chanx_left_in[19] sb_2__2_:chanx_left_out[12] 0.0001170104 + +*RES +0 cbx_2__2_:chanx_right_out[19] sb_2__2_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET cbx_1__2__1_top_grid_pin_0_[0] 0.001124318 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_2__2_:top_grid_pin_0_[0] O *L 0 *C 747.960 892.090 +*I grid_io_top_2__3_:bottom_width_0_height_0__pin_0_[0] I *L 0 *C 747.960 903.110 + +*CAP +0 cbx_2__2_:top_grid_pin_0_[0] 0.0005621588 +1 grid_io_top_2__3_:bottom_width_0_height_0__pin_0_[0] 0.0005621588 + +*RES +0 cbx_2__2_:top_grid_pin_0_[0] grid_io_top_2__3_:bottom_width_0_height_0__pin_0_[0] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[0] 0.001144611 //LENGTH 11.020 LUMPCC 0.0003008513 DR + +*CONN +*I cby_0__1_:chany_bottom_out[0] O *L 0 *C 354.660 408.070 +*I sb_0__0_:chany_top_in[0] I *L 0 *C 354.660 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[0] 0.0004218799 +1 sb_0__0_:chany_top_in[0] 0.0004218799 +2 cby_0__1_:chany_bottom_out[0] cby_0__1_:chany_bottom_out[7] 0.0001504257 +3 sb_0__0_:chany_top_in[0] sb_0__0_:chany_top_in[7] 0.0001504257 + +*RES +0 cby_0__1_:chany_bottom_out[0] sb_0__0_:chany_top_in[0] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[2] 0.001230882 //LENGTH 11.020 LUMPCC 0.0006017026 DR + +*CONN +*I cby_0__1_:chany_bottom_out[2] O *L 0 *C 357.420 408.070 +*I sb_0__0_:chany_top_in[2] I *L 0 *C 357.420 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[2] 0.0003145897 +1 sb_0__0_:chany_top_in[2] 0.0003145897 +2 cby_0__1_:chany_bottom_out[2] cby_0__1_:chany_bottom_out[6] 0.0001504257 +3 sb_0__0_:chany_top_in[2] sb_0__0_:chany_top_in[6] 0.0001504257 +4 cby_0__1_:chany_bottom_out[2] cby_0__1_:chany_bottom_in[2] 0.0001504257 +5 sb_0__0_:chany_top_in[2] sb_0__0_:chany_top_out[2] 0.0001504257 + +*RES +0 cby_0__1_:chany_bottom_out[2] sb_0__0_:chany_top_in[2] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[4] 0.001217218 //LENGTH 11.020 LUMPCC 0.0006231852 DR + +*CONN +*I cby_0__1_:chany_bottom_out[4] O *L 0 *C 330.740 408.070 +*I sb_0__0_:chany_top_in[4] I *L 0 *C 330.740 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[4] 0.0002970164 +1 sb_0__0_:chany_top_in[4] 0.0002970164 +2 cby_0__1_:chany_bottom_out[4] cby_0__1_:chany_bottom_in[0] 0.0001557963 +3 sb_0__0_:chany_top_in[4] sb_0__0_:chany_top_out[0] 0.0001557963 +4 cby_0__1_:chany_bottom_out[4] cby_0__1_:chany_bottom_in[5] 0.0001557963 +5 sb_0__0_:chany_top_in[4] sb_0__0_:chany_top_out[5] 0.0001557963 + +*RES +0 cby_0__1_:chany_bottom_out[4] sb_0__0_:chany_top_in[4] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[6] 0.001230882 //LENGTH 11.020 LUMPCC 0.0006017026 DR + +*CONN +*I cby_0__1_:chany_bottom_out[6] O *L 0 *C 356.500 408.070 +*I sb_0__0_:chany_top_in[6] I *L 0 *C 356.500 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[6] 0.0003145897 +1 sb_0__0_:chany_top_in[6] 0.0003145897 +2 cby_0__1_:chany_bottom_out[6] cby_0__1_:chany_bottom_out[2] 0.0001504257 +3 sb_0__0_:chany_top_in[6] sb_0__0_:chany_top_in[2] 0.0001504257 +4 cby_0__1_:chany_bottom_out[6] cby_0__1_:chany_bottom_out[7] 0.0001504257 +5 sb_0__0_:chany_top_in[6] sb_0__0_:chany_top_in[7] 0.0001504257 + +*RES +0 cby_0__1_:chany_bottom_out[6] sb_0__0_:chany_top_in[6] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[8] 0.001107169 //LENGTH 11.020 LUMPCC 0.0002970275 DR + +*CONN +*I cby_0__1_:chany_bottom_out[8] O *L 0 *C 350.060 408.070 +*I sb_0__0_:chany_top_in[8] I *L 0 *C 350.060 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[8] 0.0004050708 +1 sb_0__0_:chany_top_in[8] 0.0004050708 +2 cby_0__1_:chany_bottom_out[8] cby_0__1_:chany_bottom_out[1] 0.0001485138 +3 sb_0__0_:chany_top_in[8] sb_0__0_:chany_top_in[1] 0.0001485138 + +*RES +0 cby_0__1_:chany_bottom_out[8] sb_0__0_:chany_top_in[8] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[10] 0.00122511 //LENGTH 11.020 LUMPCC 0.0006079205 DR + +*CONN +*I cby_0__1_:chany_bottom_out[10] O *L 0 *C 337.180 408.070 +*I sb_0__0_:chany_top_in[10] I *L 0 *C 337.180 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[10] 0.0003085948 +1 sb_0__0_:chany_top_in[10] 0.0003085948 +2 cby_0__1_:chany_bottom_out[10] cby_0__1_:chany_bottom_in[3] 0.0001519801 +3 sb_0__0_:chany_top_in[10] sb_0__0_:chany_top_out[3] 0.0001519801 +4 cby_0__1_:chany_bottom_out[10] cby_0__1_:chany_bottom_in[11] 0.0001519801 +5 sb_0__0_:chany_top_in[10] sb_0__0_:chany_top_out[11] 0.0001519801 + +*RES +0 cby_0__1_:chany_bottom_out[10] sb_0__0_:chany_top_in[10] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[13] 0.001341164 //LENGTH 11.180 LUMPCC 0.000602139 DR + +*CONN +*I cby_0__1_:chany_bottom_out[13] O *L 0 *C 307.280 408.150 +*I sb_0__0_:chany_top_in[13] I *L 0 *C 307.280 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[13] 0.0003695127 +1 sb_0__0_:chany_top_in[13] 0.0003695127 +2 cby_0__1_:chany_bottom_out[13] cby_0__1_:chany_bottom_out[17] 6.979892e-05 +3 sb_0__0_:chany_top_in[13] sb_0__0_:chany_top_in[17] 6.979892e-05 +4 cby_0__1_:chany_bottom_out[13] cby_0__1_:chany_bottom_in[8] 0.0002312706 +5 sb_0__0_:chany_top_in[13] sb_0__0_:chany_top_out[8] 0.0002312706 + +*RES +0 cby_0__1_:chany_bottom_out[13] sb_0__0_:chany_top_in[13] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[15] 0.001311964 //LENGTH 11.180 LUMPCC 0.0004365176 DR + +*CONN +*I cby_0__1_:chany_bottom_out[15] O *L 0 *C 336.720 408.150 +*I sb_0__0_:chany_top_in[15] I *L 0 *C 336.720 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[15] 0.0004377231 +1 sb_0__0_:chany_top_in[15] 0.0004377231 +2 cby_0__1_:chany_bottom_out[15] cby_0__1_:chany_bottom_in[18] 0.0002182588 +3 sb_0__0_:chany_top_in[15] sb_0__0_:chany_top_out[18] 0.0002182588 + +*RES +0 cby_0__1_:chany_bottom_out[15] sb_0__0_:chany_top_in[15] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[18] 0.001518183 //LENGTH 11.180 LUMPCC 0.0004452524 DR + +*CONN +*I cby_0__1_:chany_bottom_out[18] O *L 0 *C 331.200 408.150 +*I sb_0__0_:chany_top_in[18] I *L 0 *C 331.200 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[18] 0.0005364653 +1 sb_0__0_:chany_top_in[18] 0.0005364653 +2 cby_0__1_:chany_bottom_out[18] cby_0__1_:chany_bottom_in[15] 0.0002226262 +3 sb_0__0_:chany_top_in[18] sb_0__0_:chany_top_out[15] 0.0002226262 + +*RES +0 cby_0__1_:chany_bottom_out[18] sb_0__0_:chany_top_in[18] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_top_out[0] 0.001242849 //LENGTH 11.020 LUMPCC 0.0003499397 DR + +*CONN +*I cby_0__1_:chany_top_out[0] O *L 0 *C 352.820 516.730 +*I sb_0__1_:chany_bottom_in[0] I *L 0 *C 352.820 527.750 + +*CAP +0 cby_0__1_:chany_top_out[0] 0.0004464549 +1 sb_0__1_:chany_bottom_in[0] 0.0004464549 +2 cby_0__1_:chany_top_out[0] cby_0__1_:chany_top_out[12] 4.539541e-05 +3 sb_0__1_:chany_bottom_in[0] sb_0__1_:chany_bottom_in[12] 4.539541e-05 +4 cby_0__1_:chany_top_out[0] cby_0__1_:chany_top_in[2] 0.0001295745 +5 sb_0__1_:chany_bottom_in[0] sb_0__1_:chany_bottom_out[2] 0.0001295745 + +*RES +0 cby_0__1_:chany_top_out[0] sb_0__1_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[2] 0.001286253 //LENGTH 11.020 LUMPCC 0.0005169292 DR + +*CONN +*I cby_0__1_:chany_top_out[2] O *L 0 *C 358.340 516.730 +*I sb_0__1_:chany_bottom_in[2] I *L 0 *C 358.340 527.750 + +*CAP +0 cby_0__1_:chany_top_out[2] 0.000384662 +1 sb_0__1_:chany_bottom_in[2] 0.000384662 +2 cby_0__1_:chany_top_out[2] cby_0__1_:chany_top_out[13] 0.0001292323 +3 sb_0__1_:chany_bottom_in[2] sb_0__1_:chany_bottom_in[13] 0.0001292323 +4 cby_0__1_:chany_top_out[2] cby_0__1_:chany_top_in[6] 0.0001292323 +5 sb_0__1_:chany_bottom_in[2] sb_0__1_:chany_bottom_out[6] 0.0001292323 + +*RES +0 cby_0__1_:chany_top_out[2] sb_0__1_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[6] 0.001262411 //LENGTH 11.020 LUMPCC 0.0003985038 DR + +*CONN +*I cby_0__1_:chany_top_out[6] O *L 0 *C 339.940 516.730 +*I sb_0__1_:chany_bottom_in[6] I *L 0 *C 339.940 527.750 + +*CAP +0 cby_0__1_:chany_top_out[6] 0.0004319537 +1 sb_0__1_:chany_bottom_in[6] 0.0004319537 +2 cby_0__1_:chany_top_out[6] cby_0__1_:chany_top_out[10] 0.0001285164 +3 sb_0__1_:chany_bottom_in[6] sb_0__1_:chany_bottom_in[10] 0.0001285164 +4 cby_0__1_:chany_top_out[6] cby_0__1_:ccff_head[0] 7.073553e-05 +5 sb_0__1_:chany_bottom_in[6] sb_0__1_:ccff_tail[0] 7.073553e-05 + +*RES +0 cby_0__1_:chany_top_out[6] sb_0__1_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[8] 0.001288776 //LENGTH 11.020 LUMPCC 0.0005185666 DR + +*CONN +*I cby_0__1_:chany_top_out[8] O *L 0 *C 310.960 516.730 +*I sb_0__1_:chany_bottom_in[8] I *L 0 *C 310.960 527.750 + +*CAP +0 cby_0__1_:chany_top_out[8] 0.0003851046 +1 sb_0__1_:chany_bottom_in[8] 0.0003851046 +2 cby_0__1_:chany_top_out[8] cby_0__1_:chany_top_out[9] 0.0001296416 +3 sb_0__1_:chany_bottom_in[8] sb_0__1_:chany_bottom_in[9] 0.0001296416 +4 cby_0__1_:chany_top_out[8] cby_0__1_:chany_top_out[19] 0.0001296416 +5 sb_0__1_:chany_bottom_in[8] sb_0__1_:chany_bottom_in[19] 0.0001296416 + +*RES +0 cby_0__1_:chany_top_out[8] sb_0__1_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[10] 0.001297261 //LENGTH 11.020 LUMPCC 0.0005061823 DR + +*CONN +*I cby_0__1_:chany_top_out[10] O *L 0 *C 339.020 516.730 +*I sb_0__1_:chany_bottom_in[10] I *L 0 *C 339.020 527.750 + +*CAP +0 cby_0__1_:chany_top_out[10] 0.0003955394 +1 sb_0__1_:chany_bottom_in[10] 0.0003955394 +2 cby_0__1_:chany_top_out[10] cby_0__1_:chany_top_out[6] 0.0001285164 +3 sb_0__1_:chany_bottom_in[10] sb_0__1_:chany_bottom_in[6] 0.0001285164 +4 cby_0__1_:chany_top_out[10] cby_0__1_:chany_top_in[4] 0.0001245748 +5 sb_0__1_:chany_bottom_in[10] sb_0__1_:chany_bottom_out[4] 0.0001245748 + +*RES +0 cby_0__1_:chany_top_out[10] sb_0__1_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[13] 0.001288262 //LENGTH 11.020 LUMPCC 0.0005169022 DR + +*CONN +*I cby_0__1_:chany_top_out[13] O *L 0 *C 359.260 516.730 +*I sb_0__1_:chany_bottom_in[13] I *L 0 *C 359.260 527.750 + +*CAP +0 cby_0__1_:chany_top_out[13] 0.0003856799 +1 sb_0__1_:chany_bottom_in[13] 0.0003856799 +2 cby_0__1_:chany_top_out[13] cby_0__1_:chany_top_out[2] 0.0001292323 +3 sb_0__1_:chany_bottom_in[13] sb_0__1_:chany_bottom_in[2] 0.0001292323 +4 cby_0__1_:chany_top_out[13] cby_0__1_:chany_top_out[4] 0.0001292188 +5 sb_0__1_:chany_bottom_in[13] sb_0__1_:chany_bottom_in[4] 0.0001292188 + +*RES +0 cby_0__1_:chany_top_out[13] sb_0__1_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[16] 0.001226766 //LENGTH 11.020 LUMPCC 0.0002593236 DR + +*CONN +*I cby_0__1_:chany_top_out[16] O *L 0 *C 328.900 516.730 +*I sb_0__1_:chany_bottom_in[16] I *L 0 *C 328.900 527.750 + +*CAP +0 cby_0__1_:chany_top_out[16] 0.0004837213 +1 sb_0__1_:chany_bottom_in[16] 0.0004837213 +2 cby_0__1_:chany_top_out[16] cby_0__1_:chany_top_in[10] 0.0001296618 +3 sb_0__1_:chany_bottom_in[16] sb_0__1_:chany_bottom_out[10] 0.0001296618 + +*RES +0 cby_0__1_:chany_top_out[16] sb_0__1_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[18] 0.001244408 //LENGTH 11.020 LUMPCC 0.000344133 DR + +*CONN +*I cby_0__1_:chany_top_out[18] O *L 0 *C 313.720 516.730 +*I sb_0__1_:chany_bottom_in[18] I *L 0 *C 313.720 527.750 + +*CAP +0 cby_0__1_:chany_top_out[18] 0.0004501376 +1 sb_0__1_:chany_bottom_in[18] 0.0004501376 +2 cby_0__1_:chany_top_out[18] cby_0__1_:chany_top_in[9] 0.0001296416 +3 sb_0__1_:chany_bottom_in[18] sb_0__1_:chany_bottom_out[9] 0.0001296416 +4 cby_0__1_:chany_top_out[18] cby_0__1_:chany_top_in[16] 4.242487e-05 +5 sb_0__1_:chany_bottom_in[18] sb_0__1_:chany_bottom_out[16] 4.242487e-05 + +*RES +0 cby_0__1_:chany_top_out[18] sb_0__1_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_0__1__0_left_grid_pin_0_[0] 0.001656114 //LENGTH 13.180 LUMPCC 0.000402891 DR + +*CONN +*I cby_0__1_:left_grid_pin_0_[0] O *L 0 *C 287.190 507.280 +*I grid_io_left_0__1_:right_width_0_height_0__pin_0_[0] I *L 0 *C 274.010 507.280 + +*CAP +0 cby_0__1_:left_grid_pin_0_[0] 0.0006266115 +1 grid_io_left_0__1_:right_width_0_height_0__pin_0_[0] 0.0006266115 +2 cby_0__1_:left_grid_pin_0_[0] grid_io_left_0_ccff_tail[0]:9 0.0002014455 +3 grid_io_left_0__1_:right_width_0_height_0__pin_0_[0] grid_io_left_0__1_:ccff_tail[0] 0.0002014455 + +*RES +0 cby_0__1_:left_grid_pin_0_[0] grid_io_left_0__1_:right_width_0_height_0__pin_0_[0] 0.002064867 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[0] 0.001182371 //LENGTH 11.020 LUMPCC 0.0002797402 DR + +*CONN +*I cby_0__2_:chany_bottom_out[0] O *L 0 *C 354.660 669.190 +*I sb_0__1_:chany_top_in[0] I *L 0 *C 354.660 658.170 +*N cby_0__1__1_chany_bottom_out[0]:2 *C 354.660 667.519 +*N cby_0__1__1_chany_bottom_out[0]:3 *C 354.660 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[0] 0.0001192405 +1 sb_0__1_:chany_top_in[0] 0.0003320749 +2 cby_0__1__1_chany_bottom_out[0]:2 0.0003320749 +3 cby_0__1__1_chany_bottom_out[0]:3 0.0001192405 +4 cby_0__2_:chany_bottom_out[0] cby_0__2_:chany_bottom_out[7] 7.234533e-06 +5 sb_0__1_:chany_top_in[0] sb_0__1_:chany_top_in[7] 0.0001326356 +6 cby_0__1__1_chany_bottom_out[0]:3 cby_0__1__1_chany_bottom_out[7]:3 7.234533e-06 +7 cby_0__1__1_chany_bottom_out[0]:2 cby_0__1__1_chany_bottom_out[7]:2 0.0001326356 + +*RES +0 cby_0__2_:chany_bottom_out[0] cby_0__1__1_chany_bottom_out[0]:3 0.001491071 +1 cby_0__1__1_chany_bottom_out[0]:3 cby_0__1__1_chany_bottom_out[0]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[0]:2 sb_0__1_:chany_top_in[0] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[2] 0.001259526 //LENGTH 11.020 LUMPCC 0.0005594804 DR + +*CONN +*I cby_0__2_:chany_bottom_out[2] O *L 0 *C 357.420 669.190 +*I sb_0__1_:chany_top_in[2] I *L 0 *C 357.420 658.170 +*N cby_0__1__1_chany_bottom_out[2]:2 *C 357.420 667.519 +*N cby_0__1__1_chany_bottom_out[2]:3 *C 357.420 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[2] 0.0001113406 +1 sb_0__1_:chany_top_in[2] 0.0002386824 +2 cby_0__1__1_chany_bottom_out[2]:2 0.0002386824 +3 cby_0__1__1_chany_bottom_out[2]:3 0.0001113406 +4 cby_0__2_:chany_bottom_out[2] cby_0__2_:chany_bottom_out[6] 7.234533e-06 +5 sb_0__1_:chany_top_in[2] sb_0__1_:chany_top_in[6] 0.0001326356 +6 cby_0__1__1_chany_bottom_out[2]:3 cby_0__1__1_chany_bottom_out[6]:3 7.234533e-06 +7 cby_0__1__1_chany_bottom_out[2]:2 cby_0__1__1_chany_bottom_out[6]:2 0.0001326356 +8 cby_0__2_:chany_bottom_out[2] cby_0__2_:chany_bottom_in[2] 7.234533e-06 +9 sb_0__1_:chany_top_in[2] sb_0__1_:chany_top_out[2] 0.0001326356 +10 cby_0__1__1_chany_bottom_out[2]:3 sb_0__1__0_chany_top_out[2]:2 7.234533e-06 +11 cby_0__1__1_chany_bottom_out[2]:2 sb_0__1__0_chany_top_out[2]:3 0.0001326356 + +*RES +0 cby_0__2_:chany_bottom_out[2] cby_0__1__1_chany_bottom_out[2]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[2]:3 cby_0__1__1_chany_bottom_out[2]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[2]:2 sb_0__1_:chany_top_in[2] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[5] 0.001113125 //LENGTH 11.020 LUMPCC 0.0001614631 DR + +*CONN +*I cby_0__2_:chany_bottom_out[5] O *L 0 *C 316.020 669.190 +*I sb_0__1_:chany_top_in[5] I *L 0 *C 316.020 658.170 +*N cby_0__1__1_chany_bottom_out[5]:2 *C 316.020 667.519 +*N cby_0__1__1_chany_bottom_out[5]:3 *C 316.020 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[5] 0.0001263262 +1 sb_0__1_:chany_top_in[5] 0.0003495046 +2 cby_0__1__1_chany_bottom_out[5]:2 0.0003495046 +3 cby_0__1__1_chany_bottom_out[5]:3 0.0001263262 +4 sb_0__1_:chany_top_in[5] sb_0__1_:chany_top_in[14] 2.90727e-05 +5 cby_0__1__1_chany_bottom_out[5]:2 cby_0__1__1_chany_bottom_out[14]:2 2.90727e-05 +6 sb_0__1_:chany_top_in[5] sb_0__1_:chany_top_out[1] 2.407552e-05 +7 cby_0__1__1_chany_bottom_out[5]:2 sb_0__1__0_chany_top_out[1]:3 2.407552e-05 +8 sb_0__1_:chany_top_in[5] sb_0__1_:chany_top_out[19] 2.758333e-05 +9 cby_0__1__1_chany_bottom_out[5]:2 sb_0__1__0_chany_top_out[19]:3 2.758333e-05 + +*RES +0 cby_0__2_:chany_bottom_out[5] cby_0__1__1_chany_bottom_out[5]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[5]:3 cby_0__1__1_chany_bottom_out[5]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[5]:2 sb_0__1_:chany_top_in[5] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[7] 0.001259584 //LENGTH 11.020 LUMPCC 0.0005594804 DR + +*CONN +*I cby_0__2_:chany_bottom_out[7] O *L 0 *C 355.580 669.190 +*I sb_0__1_:chany_top_in[7] I *L 0 *C 355.580 658.170 +*N cby_0__1__1_chany_bottom_out[7]:2 *C 355.580 667.519 +*N cby_0__1__1_chany_bottom_out[7]:3 *C 355.580 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[7] 0.0001113406 +1 sb_0__1_:chany_top_in[7] 0.0002387115 +2 cby_0__1__1_chany_bottom_out[7]:2 0.0002387115 +3 cby_0__1__1_chany_bottom_out[7]:3 0.0001113406 +4 cby_0__2_:chany_bottom_out[7] cby_0__2_:chany_bottom_out[0] 7.234533e-06 +5 sb_0__1_:chany_top_in[7] sb_0__1_:chany_top_in[0] 0.0001326356 +6 cby_0__1__1_chany_bottom_out[7]:3 cby_0__1__1_chany_bottom_out[0]:3 7.234533e-06 +7 cby_0__1__1_chany_bottom_out[7]:2 cby_0__1__1_chany_bottom_out[0]:2 0.0001326356 +8 cby_0__2_:chany_bottom_out[7] cby_0__2_:chany_bottom_out[6] 7.234533e-06 +9 sb_0__1_:chany_top_in[7] sb_0__1_:chany_top_in[6] 0.0001326356 +10 cby_0__1__1_chany_bottom_out[7]:3 cby_0__1__1_chany_bottom_out[6]:3 7.234533e-06 +11 cby_0__1__1_chany_bottom_out[7]:2 cby_0__1__1_chany_bottom_out[6]:2 0.0001326356 + +*RES +0 cby_0__2_:chany_bottom_out[7] cby_0__1__1_chany_bottom_out[7]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[7]:3 cby_0__1__1_chany_bottom_out[7]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[7]:2 sb_0__1_:chany_top_in[7] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[8] 0.001146435 //LENGTH 11.020 LUMPCC 0.000275843 DR + +*CONN +*I cby_0__2_:chany_bottom_out[8] O *L 0 *C 350.060 669.190 +*I sb_0__1_:chany_top_in[8] I *L 0 *C 350.060 658.170 +*N cby_0__1__1_chany_bottom_out[8]:2 *C 350.060 667.519 +*N cby_0__1__1_chany_bottom_out[8]:3 *C 350.060 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[8] 0.0001187055 +1 sb_0__1_:chany_top_in[8] 0.0003165903 +2 cby_0__1__1_chany_bottom_out[8]:2 0.0003165903 +3 cby_0__1__1_chany_bottom_out[8]:3 0.0001187055 +4 cby_0__2_:chany_bottom_out[8] cby_0__2_:chany_bottom_out[1] 7.180468e-06 +5 sb_0__1_:chany_top_in[8] sb_0__1_:chany_top_in[1] 0.0001307411 +6 cby_0__1__1_chany_bottom_out[8]:3 cby_0__1__1_chany_bottom_out[1]:3 7.180468e-06 +7 cby_0__1__1_chany_bottom_out[8]:2 cby_0__1__1_chany_bottom_out[1]:2 0.0001307411 + +*RES +0 cby_0__2_:chany_bottom_out[8] cby_0__1__1_chany_bottom_out[8]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[8]:3 cby_0__1__1_chany_bottom_out[8]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[8]:2 sb_0__1_:chany_top_in[8] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[10] 0.001253941 //LENGTH 11.020 LUMPCC 0.0005649955 DR + +*CONN +*I cby_0__2_:chany_bottom_out[10] O *L 0 *C 337.180 669.190 +*I sb_0__1_:chany_top_in[10] I *L 0 *C 337.180 658.170 +*N cby_0__1__1_chany_bottom_out[10]:2 *C 337.180 667.519 +*N cby_0__1__1_chany_bottom_out[10]:3 *C 337.180 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[10] 0.0001113409 +1 sb_0__1_:chany_top_in[10] 0.000233132 +2 cby_0__1__1_chany_bottom_out[10]:2 0.000233132 +3 cby_0__1__1_chany_bottom_out[10]:3 0.0001113409 +4 cby_0__2_:chany_bottom_out[10] cby_0__2_:chany_bottom_in[3] 7.248536e-06 +5 sb_0__1_:chany_top_in[10] sb_0__1_:chany_top_out[3] 0.0001340003 +6 cby_0__1__1_chany_bottom_out[10]:3 sb_0__1__0_chany_top_out[3]:2 7.248536e-06 +7 cby_0__1__1_chany_bottom_out[10]:2 sb_0__1__0_chany_top_out[3]:3 0.0001340003 +8 cby_0__2_:chany_bottom_out[10] cby_0__2_:chany_bottom_in[11] 7.248536e-06 +9 sb_0__1_:chany_top_in[10] sb_0__1_:chany_top_out[11] 0.0001340003 +10 cby_0__1__1_chany_bottom_out[10]:3 sb_0__1__0_chany_top_out[11]:2 7.248536e-06 +11 cby_0__1__1_chany_bottom_out[10]:2 sb_0__1__0_chany_top_out[11]:3 0.0001340003 + +*RES +0 cby_0__2_:chany_bottom_out[10] cby_0__1__1_chany_bottom_out[10]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[10]:3 cby_0__1__1_chany_bottom_out[10]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[10]:2 sb_0__1_:chany_top_in[10] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[14] 0.001487216 //LENGTH 11.180 LUMPCC 5.814539e-05 DR + +*CONN +*I cby_0__2_:chany_bottom_out[14] O *L 0 *C 316.480 669.270 +*I sb_0__1_:chany_top_in[14] I *L 0 *C 316.480 658.090 +*N cby_0__1__1_chany_bottom_out[14]:2 *C 316.480 667.519 +*N cby_0__1__1_chany_bottom_out[14]:3 *C 316.480 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[14] 0.0002156536 +1 sb_0__1_:chany_top_in[14] 0.0004988814 +2 cby_0__1__1_chany_bottom_out[14]:2 0.0004988814 +3 cby_0__1__1_chany_bottom_out[14]:3 0.0002156536 +4 sb_0__1_:chany_top_in[14] sb_0__1_:chany_top_in[5] 2.90727e-05 +5 cby_0__1__1_chany_bottom_out[14]:2 cby_0__1__1_chany_bottom_out[5]:2 2.90727e-05 + +*RES +0 cby_0__2_:chany_bottom_out[14] cby_0__1__1_chany_bottom_out[14]:3 0.0002741667 +1 cby_0__1__1_chany_bottom_out[14]:3 cby_0__1__1_chany_bottom_out[14]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[14]:2 sb_0__1_:chany_top_in[14] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[15] 0.001509634 //LENGTH 11.180 LUMPCC 0.0004311476 DR + +*CONN +*I cby_0__2_:chany_bottom_out[15] O *L 0 *C 336.720 669.270 +*I sb_0__1_:chany_top_in[15] I *L 0 *C 336.720 658.090 +*N cby_0__1__1_chany_bottom_out[15]:2 *C 336.720 667.519 +*N cby_0__1__1_chany_bottom_out[15]:3 *C 336.720 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[15] 0.0002108179 +1 sb_0__1_:chany_top_in[15] 0.0003284251 +2 cby_0__1__1_chany_bottom_out[15]:2 0.0003284251 +3 cby_0__1__1_chany_bottom_out[15]:3 0.0002108179 +4 cby_0__2_:chany_bottom_out[15] cby_0__2_:chany_bottom_in[18] 9.041499e-06 +5 sb_0__1_:chany_top_in[15] sb_0__1_:chany_top_out[18] 0.0002065323 +6 cby_0__1__1_chany_bottom_out[15]:3 sb_0__1__0_chany_top_out[18]:2 9.041499e-06 +7 cby_0__1__1_chany_bottom_out[15]:2 sb_0__1__0_chany_top_out[18]:3 0.0002065323 + +*RES +0 cby_0__2_:chany_bottom_out[15] cby_0__1__1_chany_bottom_out[15]:3 0.0002741666 +1 cby_0__1__1_chany_bottom_out[15]:3 cby_0__1__1_chany_bottom_out[15]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[15]:2 sb_0__1_:chany_top_in[15] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_top_out[0] 0.00118036 //LENGTH 11.020 LUMPCC 0.0004192142 DR + +*CONN +*I cby_0__2_:chany_top_out[0] O *L 0 *C 352.820 777.850 +*I sb_0__2_:chany_bottom_in[0] I *L 0 *C 352.820 788.870 + +*CAP +0 cby_0__2_:chany_top_out[0] 0.000380573 +1 sb_0__2_:chany_bottom_in[0] 0.000380573 +2 cby_0__2_:chany_top_out[0] cby_0__2_:chany_top_out[12] 6.540296e-05 +3 sb_0__2_:chany_bottom_in[0] sb_0__2_:chany_bottom_in[12] 6.540296e-05 +4 cby_0__2_:chany_top_out[0] cby_0__2_:chany_top_in[2] 0.0001442041 +5 sb_0__2_:chany_bottom_in[0] sb_0__2_:chany_bottom_out[2] 0.0001442041 + +*RES +0 cby_0__2_:chany_top_out[0] sb_0__2_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[5] 0.001251036 //LENGTH 11.020 LUMPCC 0.0005630559 DR + +*CONN +*I cby_0__2_:chany_top_out[5] O *L 0 *C 336.260 777.850 +*I sb_0__2_:chany_bottom_in[5] I *L 0 *C 336.260 788.870 + +*CAP +0 cby_0__2_:chany_top_out[5] 0.0003439898 +1 sb_0__2_:chany_bottom_in[5] 0.0003439898 +2 cby_0__2_:chany_top_out[5] cby_0__2_:chany_top_in[0] 0.0001430462 +3 sb_0__2_:chany_bottom_in[5] sb_0__2_:chany_bottom_out[0] 0.0001430462 +4 cby_0__2_:chany_top_out[5] cby_0__2_:chany_top_in[11] 0.0001384818 +5 sb_0__2_:chany_bottom_in[5] sb_0__2_:chany_bottom_out[11] 0.0001384818 + +*RES +0 cby_0__2_:chany_top_out[5] sb_0__2_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[8] 0.001256822 //LENGTH 11.020 LUMPCC 0.0005621223 DR + +*CONN +*I cby_0__2_:chany_top_out[8] O *L 0 *C 310.960 777.850 +*I sb_0__2_:chany_bottom_in[8] I *L 0 *C 310.960 788.870 + +*CAP +0 cby_0__2_:chany_top_out[8] 0.0003473497 +1 sb_0__2_:chany_bottom_in[8] 0.0003473497 +2 cby_0__2_:chany_top_out[8] cby_0__2_:chany_top_out[9] 0.0001405306 +3 sb_0__2_:chany_bottom_in[8] sb_0__2_:chany_bottom_in[9] 0.0001405306 +4 cby_0__2_:chany_top_out[8] cby_0__2_:chany_top_out[19] 0.0001405306 +5 sb_0__2_:chany_bottom_in[8] sb_0__2_:chany_bottom_in[19] 0.0001405306 + +*RES +0 cby_0__2_:chany_top_out[8] sb_0__2_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[14] 0.001248496 //LENGTH 11.020 LUMPCC 0.0005760535 DR + +*CONN +*I cby_0__2_:chany_top_out[14] O *L 0 *C 330.740 777.850 +*I sb_0__2_:chany_bottom_in[14] I *L 0 *C 330.740 788.870 + +*CAP +0 cby_0__2_:chany_top_out[14] 0.0003362213 +1 sb_0__2_:chany_bottom_in[14] 0.0003362213 +2 cby_0__2_:chany_top_out[14] cby_0__2_:chany_top_in[3] 0.0001440134 +3 sb_0__2_:chany_bottom_in[14] sb_0__2_:chany_bottom_out[3] 0.0001440134 +4 cby_0__2_:chany_top_out[14] cby_0__2_:chany_top_in[10] 0.0001440134 +5 sb_0__2_:chany_bottom_in[14] sb_0__2_:chany_bottom_out[10] 0.0001440134 + +*RES +0 cby_0__2_:chany_top_out[14] sb_0__2_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[17] 0.001227805 //LENGTH 11.020 LUMPCC 0.0004406365 DR + +*CONN +*I cby_0__2_:chany_top_out[17] O *L 0 *C 316.940 777.850 +*I sb_0__2_:chany_bottom_in[17] I *L 0 *C 316.940 788.870 + +*CAP +0 cby_0__2_:chany_top_out[17] 0.0003935842 +1 sb_0__2_:chany_bottom_in[17] 0.0003935842 +2 cby_0__2_:chany_top_out[17] cby_0__2_:chany_top_out[11] 0.0001369426 +3 sb_0__2_:chany_bottom_in[17] sb_0__2_:chany_bottom_in[11] 0.0001369426 +4 cby_0__2_:chany_top_out[17] cby_0__2_:chany_top_in[16] 8.33756e-05 +5 sb_0__2_:chany_bottom_in[17] sb_0__2_:chany_bottom_out[16] 8.33756e-05 + +*RES +0 cby_0__2_:chany_top_out[17] sb_0__2_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[0] 0.001214412 //LENGTH 11.020 LUMPCC 0.0006106543 DR + +*CONN +*I cby_1__1_:chany_bottom_out[0] O *L 0 *C 600.300 408.070 +*I sb_1__0_:chany_top_in[0] I *L 0 *C 600.300 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[0] 0.0003018787 +1 sb_1__0_:chany_top_in[0] 0.0003018787 +2 cby_1__1_:chany_bottom_out[0] cby_1__1_:chany_bottom_out[17] 0.0001525348 +3 sb_1__0_:chany_top_in[0] sb_1__0_:chany_top_in[17] 0.0001525348 +4 cby_1__1_:chany_bottom_out[0] cby_1__1_:chany_bottom_in[12] 0.0001527924 +5 sb_1__0_:chany_top_in[0] sb_1__0_:chany_top_out[12] 0.0001527924 + +*RES +0 cby_1__1_:chany_bottom_out[0] sb_1__0_:chany_top_in[0] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[6] 0.001237409 //LENGTH 11.020 LUMPCC 0.000580085 DR + +*CONN +*I cby_1__1_:chany_bottom_out[6] O *L 0 *C 594.780 408.070 +*I sb_1__0_:chany_top_in[6] I *L 0 *C 594.780 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[6] 0.000328662 +1 sb_1__0_:chany_top_in[6] 0.000328662 +2 cby_1__1_:chany_bottom_out[6] cby_1__1_:chany_bottom_out[3] 0.0001450212 +3 sb_1__0_:chany_top_in[6] sb_1__0_:chany_top_in[3] 0.0001450212 +4 cby_1__1_:chany_bottom_out[6] cby_1__1_:chany_bottom_out[11] 0.0001450212 +5 sb_1__0_:chany_top_in[6] sb_1__0_:chany_top_in[11] 0.0001450212 + +*RES +0 cby_1__1_:chany_bottom_out[6] sb_1__0_:chany_top_in[6] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[10] 0.001237409 //LENGTH 11.020 LUMPCC 0.000580085 DR + +*CONN +*I cby_1__1_:chany_bottom_out[10] O *L 0 *C 592.940 408.070 +*I sb_1__0_:chany_top_in[10] I *L 0 *C 592.940 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[10] 0.000328662 +1 sb_1__0_:chany_top_in[10] 0.000328662 +2 cby_1__1_:chany_bottom_out[10] cby_1__1_:chany_bottom_out[3] 0.0001450212 +3 sb_1__0_:chany_top_in[10] sb_1__0_:chany_top_in[3] 0.0001450212 +4 cby_1__1_:chany_bottom_out[10] cby_1__1_:chany_bottom_out[8] 0.0001450212 +5 sb_1__0_:chany_top_in[10] sb_1__0_:chany_top_in[8] 0.0001450212 + +*RES +0 cby_1__1_:chany_bottom_out[10] sb_1__0_:chany_top_in[10] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[13] 0.001184743 //LENGTH 11.020 LUMPCC 0.0004781088 DR + +*CONN +*I cby_1__1_:chany_bottom_out[13] O *L 0 *C 583.280 408.070 +*I sb_1__0_:chany_top_in[13] I *L 0 *C 583.280 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[13] 0.000353317 +1 sb_1__0_:chany_top_in[13] 0.000353317 +2 cby_1__1_:chany_bottom_out[13] cby_1__1_:chany_bottom_in[13] 0.0001480614 +3 sb_1__0_:chany_top_in[13] sb_1__0_:chany_top_out[13] 0.0001480614 +4 cby_1__1_:chany_bottom_out[13] cby_1__1_:chany_bottom_in[17] 9.099299e-05 +5 sb_1__0_:chany_top_in[13] sb_1__0_:chany_top_out[17] 9.099299e-05 + +*RES +0 cby_1__1_:chany_bottom_out[13] sb_1__0_:chany_top_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[19] 0.001236731 //LENGTH 11.020 LUMPCC 0.0005813158 DR + +*CONN +*I cby_1__1_:chany_bottom_out[19] O *L 0 *C 579.140 408.070 +*I sb_1__0_:chany_top_in[19] I *L 0 *C 579.140 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[19] 0.0003277076 +1 sb_1__0_:chany_top_in[19] 0.0003277076 +2 cby_1__1_:chany_bottom_out[19] cby_1__1_:chany_bottom_out[5] 0.000145329 +3 sb_1__0_:chany_top_in[19] sb_1__0_:chany_top_in[5] 0.000145329 +4 cby_1__1_:chany_bottom_out[19] cby_1__1_:chany_bottom_in[9] 0.000145329 +5 sb_1__0_:chany_top_in[19] sb_1__0_:chany_top_out[9] 0.000145329 + +*RES +0 cby_1__1_:chany_bottom_out[19] sb_1__0_:chany_top_in[19] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[3] 0.001226607 //LENGTH 11.020 LUMPCC 0.0002533873 DR + +*CONN +*I cby_1__1_:chany_top_out[3] O *L 0 *C 608.120 516.730 +*I sb_1__1_:chany_bottom_in[3] I *L 0 *C 608.120 527.750 + +*CAP +0 cby_1__1_:chany_top_out[3] 0.0004866101 +1 sb_1__1_:chany_bottom_in[3] 0.0004866101 +2 cby_1__1_:chany_top_out[3] cby_1__1_:chany_top_out[7] 0.0001266936 +3 sb_1__1_:chany_bottom_in[3] sb_1__1_:chany_bottom_in[7] 0.0001266936 + +*RES +0 cby_1__1_:chany_top_out[3] sb_1__1_:chany_bottom_in[3] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[7] 0.001290351 //LENGTH 11.020 LUMPCC 0.0005067745 DR + +*CONN +*I cby_1__1_:chany_top_out[7] O *L 0 *C 607.200 516.730 +*I sb_1__1_:chany_bottom_in[7] I *L 0 *C 607.200 527.750 + +*CAP +0 cby_1__1_:chany_top_out[7] 0.0003917882 +1 sb_1__1_:chany_bottom_in[7] 0.0003917882 +2 cby_1__1_:chany_top_out[7] cby_1__1_:chany_top_out[3] 0.0001266936 +3 sb_1__1_:chany_bottom_in[7] sb_1__1_:chany_bottom_in[3] 0.0001266936 +4 cby_1__1_:chany_top_out[7] cby_1__1_:chany_top_out[11] 0.0001266936 +5 sb_1__1_:chany_bottom_in[7] sb_1__1_:chany_bottom_in[11] 0.0001266936 + +*RES +0 cby_1__1_:chany_top_out[7] sb_1__1_:chany_bottom_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[12] 0.001288243 //LENGTH 11.020 LUMPCC 0.0005108983 DR + +*CONN +*I cby_1__1_:chany_top_out[12] O *L 0 *C 599.380 516.730 +*I sb_1__1_:chany_bottom_in[12] I *L 0 *C 599.380 527.750 + +*CAP +0 cby_1__1_:chany_top_out[12] 0.0003886723 +1 sb_1__1_:chany_bottom_in[12] 0.0003886723 +2 cby_1__1_:chany_top_out[12] cby_1__1_:chany_top_out[19] 0.0001289014 +3 sb_1__1_:chany_bottom_in[12] sb_1__1_:chany_bottom_in[19] 0.0001289014 +4 cby_1__1_:chany_top_out[12] cby_1__1_:chany_top_in[12] 0.0001265478 +5 sb_1__1_:chany_bottom_in[12] sb_1__1_:chany_bottom_out[12] 0.0001265478 + +*RES +0 cby_1__1_:chany_top_out[12] sb_1__1_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[17] 0.00128887 //LENGTH 11.020 LUMPCC 0.0005102205 DR + +*CONN +*I cby_1__1_:chany_top_out[17] O *L 0 *C 589.720 516.730 +*I sb_1__1_:chany_bottom_in[17] I *L 0 *C 589.720 527.750 + +*CAP +0 cby_1__1_:chany_top_out[17] 0.0003893248 +1 sb_1__1_:chany_bottom_in[17] 0.0003893248 +2 cby_1__1_:chany_top_out[17] cby_1__1_:chany_top_in[3] 0.0001275551 +3 sb_1__1_:chany_bottom_in[17] sb_1__1_:chany_bottom_out[3] 0.0001275551 +4 cby_1__1_:chany_top_out[17] cby_1__1_:chany_top_in[19] 0.0001275551 +5 sb_1__1_:chany_bottom_in[17] sb_1__1_:chany_bottom_out[19] 0.0001275551 + +*RES +0 cby_1__1_:chany_top_out[17] sb_1__1_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_12_[0] 0.001396284 //LENGTH 7.660 LUMPCC 0.0002347577 DR + +*CONN +*I cby_1__1_:left_grid_pin_12_[0] O *L 0 *C 548.470 443.360 +*I grid_clb_1__1_:right_width_0_height_0__pin_12_[0] I *L 0 *C 540.810 443.360 + +*CAP +0 cby_1__1_:left_grid_pin_12_[0] 0.0005807631 +1 grid_clb_1__1_:right_width_0_height_0__pin_12_[0] 0.0005807631 +2 cby_1__1_:left_grid_pin_12_[0] cby_1__1_:left_grid_pin_15_[0] 0.0001173788 +3 grid_clb_1__1_:right_width_0_height_0__pin_12_[0] grid_clb_1__1_:right_width_0_height_0__pin_15_[0] 0.0001173788 + +*RES +0 cby_1__1_:left_grid_pin_12_[0] grid_clb_1__1_:right_width_0_height_0__pin_12_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_15_[0] 0.001396284 //LENGTH 7.660 LUMPCC 0.0002347577 DR + +*CONN +*I cby_1__1_:left_grid_pin_15_[0] O *L 0 *C 548.470 442.000 +*I grid_clb_1__1_:right_width_0_height_0__pin_15_[0] I *L 0 *C 540.810 442.000 + +*CAP +0 cby_1__1_:left_grid_pin_15_[0] 0.000580763 +1 grid_clb_1__1_:right_width_0_height_0__pin_15_[0] 0.000580763 +2 cby_1__1_:left_grid_pin_15_[0] cby_1__1_:left_grid_pin_12_[0] 0.0001173788 +3 grid_clb_1__1_:right_width_0_height_0__pin_15_[0] grid_clb_1__1_:right_width_0_height_0__pin_12_[0] 0.0001173788 + +*RES +0 cby_1__1_:left_grid_pin_15_[0] grid_clb_1__1_:right_width_0_height_0__pin_15_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_6_[0] 0.001462881 //LENGTH 7.660 LUMPCC 0.0004993617 DR + +*CONN +*I cby_1__1_:left_grid_pin_6_[0] O *L 0 *C 548.470 488.240 +*I grid_clb_1__1_:right_width_0_height_0__pin_6_[0] I *L 0 *C 540.810 488.240 + +*CAP +0 cby_1__1_:left_grid_pin_6_[0] 0.0004817594 +1 grid_clb_1__1_:right_width_0_height_0__pin_6_[0] 0.0004817594 +2 cby_1__1_:left_grid_pin_6_[0] cby_1__1_:left_grid_pin_10_[0] 0.0001329495 +3 grid_clb_1__1_:right_width_0_height_0__pin_6_[0] grid_clb_1__1_:right_width_0_height_0__pin_10_[0] 0.0001329495 +4 cby_1__1_:left_grid_pin_6_[0] cby_1__1_:left_grid_pin_9_[0] 0.0001167313 +5 grid_clb_1__1_:right_width_0_height_0__pin_6_[0] grid_clb_1__1_:right_width_0_height_0__pin_9_[0] 0.0001167313 + +*RES +0 cby_1__1_:left_grid_pin_6_[0] grid_clb_1__1_:right_width_0_height_0__pin_6_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[0] 0.001231933 //LENGTH 11.020 LUMPCC 0.0006005091 DR + +*CONN +*I cby_1__2_:chany_bottom_out[0] O *L 0 *C 600.300 669.190 +*I sb_1__1_:chany_top_in[0] I *L 0 *C 600.300 658.170 +*N cby_1__1__1_chany_bottom_out[0]:2 *C 600.300 667.519 +*N cby_1__1__1_chany_bottom_out[0]:3 *C 600.300 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[0] 0.0001142751 +1 sb_1__1_:chany_top_in[0] 0.0002014367 +2 cby_1__1__1_chany_bottom_out[0]:2 0.0002014367 +3 cby_1__1__1_chany_bottom_out[0]:3 0.0001142751 +4 cby_1__2_:chany_bottom_out[0] cby_1__2_:chany_bottom_out[17] 6.201185e-06 +5 sb_1__1_:chany_top_in[0] sb_1__1_:chany_top_in[17] 0.000143306 +6 cby_1__1__1_chany_bottom_out[0]:3 cby_1__1__1_chany_bottom_out[17]:3 6.201185e-06 +7 cby_1__1__1_chany_bottom_out[0]:2 cby_1__1__1_chany_bottom_out[17]:2 0.000143306 +8 cby_1__2_:chany_bottom_out[0] cby_1__2_:chany_bottom_in[12] 7.441422e-06 +9 sb_1__1_:chany_top_in[0] sb_1__1_:chany_top_out[12] 0.000143306 +10 cby_1__1__1_chany_bottom_out[0]:3 sb_1__1__0_chany_top_out[12]:2 7.441422e-06 +11 cby_1__1__1_chany_bottom_out[0]:2 sb_1__1__0_chany_top_out[12]:3 0.000143306 + +*RES +0 cby_1__2_:chany_bottom_out[0] cby_1__1__1_chany_bottom_out[0]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[0]:3 cby_1__1__1_chany_bottom_out[0]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[0]:2 sb_1__1_:chany_top_in[0] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[7] 0.001167459 //LENGTH 11.020 LUMPCC 0.0003968722 DR + +*CONN +*I cby_1__2_:chany_bottom_out[7] O *L 0 *C 586.500 669.190 +*I sb_1__1_:chany_top_in[7] I *L 0 *C 586.500 658.170 +*N cby_1__1__1_chany_bottom_out[7]:2 *C 586.500 667.519 +*N cby_1__1__1_chany_bottom_out[7]:3 *C 586.500 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[7] 0.0001189228 +1 sb_1__1_:chany_top_in[7] 0.0002663707 +2 cby_1__1__1_chany_bottom_out[7]:2 0.0002663707 +3 cby_1__1__1_chany_bottom_out[7]:3 0.0001189228 +4 cby_1__2_:chany_bottom_out[7] cby_1__2_:chany_bottom_out[9] 7.340376e-06 +5 sb_1__1_:chany_top_in[7] sb_1__1_:chany_top_in[9] 0.0001387437 +6 cby_1__1__1_chany_bottom_out[7]:3 cby_1__1__1_chany_bottom_out[9]:3 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[7]:2 cby_1__1__1_chany_bottom_out[9]:2 0.0001387437 +8 sb_1__1_:chany_top_in[7] sb_1__1_:chany_top_out[13] 5.235202e-05 +9 cby_1__1__1_chany_bottom_out[7]:2 sb_1__1__0_chany_top_out[13]:3 5.235202e-05 + +*RES +0 cby_1__2_:chany_bottom_out[7] cby_1__1__1_chany_bottom_out[7]:3 0.001491071 +1 cby_1__1__1_chany_bottom_out[7]:3 cby_1__1__1_chany_bottom_out[7]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[7]:2 sb_1__1_:chany_top_in[7] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[10] 0.00125099 //LENGTH 11.020 LUMPCC 0.00057206 DR + +*CONN +*I cby_1__2_:chany_bottom_out[10] O *L 0 *C 592.940 669.190 +*I sb_1__1_:chany_top_in[10] I *L 0 *C 592.940 658.170 +*N cby_1__1__1_chany_bottom_out[10]:2 *C 592.940 667.519 +*N cby_1__1__1_chany_bottom_out[10]:3 *C 592.940 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[10] 0.0001111417 +1 sb_1__1_:chany_top_in[10] 0.0002283233 +2 cby_1__1__1_chany_bottom_out[10]:2 0.0002283233 +3 cby_1__1__1_chany_bottom_out[10]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[10] cby_1__2_:chany_bottom_out[3] 7.294814e-06 +5 sb_1__1_:chany_top_in[10] sb_1__1_:chany_top_in[3] 0.0001357202 +6 cby_1__1__1_chany_bottom_out[10]:3 cby_1__1__1_chany_bottom_out[3]:3 7.294814e-06 +7 cby_1__1__1_chany_bottom_out[10]:2 cby_1__1__1_chany_bottom_out[3]:2 0.0001357202 +8 cby_1__2_:chany_bottom_out[10] cby_1__2_:chany_bottom_out[8] 7.294814e-06 +9 sb_1__1_:chany_top_in[10] sb_1__1_:chany_top_in[8] 0.0001357202 +10 cby_1__1__1_chany_bottom_out[10]:3 cby_1__1__1_chany_bottom_out[8]:3 7.294814e-06 +11 cby_1__1__1_chany_bottom_out[10]:2 cby_1__1__1_chany_bottom_out[8]:2 0.0001357202 + +*RES +0 cby_1__2_:chany_bottom_out[10] cby_1__1__1_chany_bottom_out[10]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[10]:3 cby_1__1__1_chany_bottom_out[10]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[10]:2 sb_1__1_:chany_top_in[10] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[17] 0.001250316 //LENGTH 11.020 LUMPCC 0.0005897048 DR + +*CONN +*I cby_1__2_:chany_bottom_out[17] O *L 0 *C 601.220 669.190 +*I sb_1__1_:chany_top_in[17] I *L 0 *C 601.220 658.170 +*N cby_1__1__1_chany_bottom_out[17]:2 *C 601.220 667.519 +*N cby_1__1__1_chany_bottom_out[17]:3 *C 601.220 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[17] 0.0001146407 +1 sb_1__1_:chany_top_in[17] 0.0002156648 +2 cby_1__1__1_chany_bottom_out[17]:2 0.0002156648 +3 cby_1__1__1_chany_bottom_out[17]:3 0.0001146407 +4 cby_1__2_:chany_bottom_out[17] cby_1__2_:chany_bottom_out[0] 6.201185e-06 +5 sb_1__1_:chany_top_in[17] sb_1__1_:chany_top_in[0] 0.000143306 +6 cby_1__1__1_chany_bottom_out[17]:3 cby_1__1__1_chany_bottom_out[0]:3 6.201185e-06 +7 cby_1__1__1_chany_bottom_out[17]:2 cby_1__1__1_chany_bottom_out[0]:2 0.000143306 +8 cby_1__2_:chany_bottom_out[17] cby_1__2_:chany_bottom_out[2] 7.340369e-06 +9 sb_1__1_:chany_top_in[17] sb_1__1_:chany_top_in[2] 0.0001380049 +10 cby_1__1__1_chany_bottom_out[17]:3 cby_1__1__1_chany_bottom_out[2]:3 7.340369e-06 +11 cby_1__1__1_chany_bottom_out[17]:2 cby_1__1__1_chany_bottom_out[2]:2 0.0001380049 + +*RES +0 cby_1__2_:chany_bottom_out[17] cby_1__1__1_chany_bottom_out[17]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[17]:3 cby_1__1__1_chany_bottom_out[17]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[17]:2 sb_1__1_:chany_top_in[17] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_top_out[1] 0.001272042 //LENGTH 11.020 LUMPCC 0.000530115 DR + +*CONN +*I cby_1__2_:chany_top_out[1] O *L 0 *C 586.960 777.850 +*I sb_1__2_:chany_bottom_in[1] I *L 0 *C 586.960 788.870 + +*CAP +0 cby_1__2_:chany_top_out[1] 0.0003709637 +1 sb_1__2_:chany_bottom_in[1] 0.0003709637 +2 cby_1__2_:chany_top_out[1] cby_1__2_:chany_top_out[13] 0.0001334764 +3 sb_1__2_:chany_bottom_in[1] sb_1__2_:chany_bottom_in[13] 0.0001334764 +4 cby_1__2_:chany_top_out[1] cby_1__2_:chany_top_out[14] 0.0001315811 +5 sb_1__2_:chany_bottom_in[1] sb_1__2_:chany_bottom_in[14] 0.0001315811 + +*RES +0 cby_1__2_:chany_top_out[1] sb_1__2_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[5] 0.001289161 //LENGTH 11.020 LUMPCC 0.0005110332 DR + +*CONN +*I cby_1__2_:chany_top_out[5] O *L 0 *C 595.700 777.850 +*I sb_1__2_:chany_bottom_in[5] I *L 0 *C 595.700 788.870 + +*CAP +0 cby_1__2_:chany_top_out[5] 0.0003890638 +1 sb_1__2_:chany_bottom_in[5] 0.0003890638 +2 cby_1__2_:chany_top_out[5] cby_1__2_:chany_top_out[16] 0.0001259201 +3 sb_1__2_:chany_bottom_in[5] sb_1__2_:chany_bottom_in[16] 0.0001259201 +4 cby_1__2_:chany_top_out[5] cby_1__2_:chany_top_in[6] 0.0001295966 +5 sb_1__2_:chany_bottom_in[5] sb_1__2_:chany_bottom_out[6] 0.0001295966 + +*RES +0 cby_1__2_:chany_top_out[5] sb_1__2_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[9] 0.00121372 //LENGTH 11.020 LUMPCC 0.0003396573 DR + +*CONN +*I cby_1__2_:chany_top_out[9] O *L 0 *C 603.980 777.850 +*I sb_1__2_:chany_bottom_in[9] I *L 0 *C 603.980 788.870 + +*CAP +0 cby_1__2_:chany_top_out[9] 0.0004370313 +1 sb_1__2_:chany_bottom_in[9] 0.0004370313 +2 cby_1__2_:chany_top_out[9] cby_1__2_:chany_top_out[11] 3.863406e-05 +3 sb_1__2_:chany_bottom_in[9] sb_1__2_:chany_bottom_in[11] 3.863406e-05 +4 cby_1__2_:chany_top_out[9] cby_1__2_:chany_top_in[0] 0.0001311946 +5 sb_1__2_:chany_bottom_in[9] sb_1__2_:chany_bottom_out[0] 0.0001311946 + +*RES +0 cby_1__2_:chany_top_out[9] sb_1__2_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[15] 0.001301571 //LENGTH 11.020 LUMPCC 0.0005419198 DR + +*CONN +*I cby_1__2_:chany_top_out[15] O *L 0 *C 573.160 777.850 +*I sb_1__2_:chany_bottom_in[15] I *L 0 *C 573.160 788.870 + +*CAP +0 cby_1__2_:chany_top_out[15] 0.0003798255 +1 sb_1__2_:chany_bottom_in[15] 0.0003798255 +2 cby_1__2_:chany_top_out[15] cby_1__2_:chany_top_in[2] 4.900551e-05 +3 cby_1__2_:chany_top_out[15] sb_1__2__0_chany_bottom_out[2]:3 5.05203e-05 +4 cby_1__2_:chany_top_out[15] sb_1__2__0_chany_bottom_out[2]:5 4.03335e-05 +5 sb_1__2_:chany_bottom_in[15] sb_1__2_:chany_bottom_out[2] 4.03335e-05 +6 sb_1__2_:chany_bottom_in[15] sb_1__2__0_chany_bottom_out[2]:2 4.900551e-05 +7 sb_1__2_:chany_bottom_in[15] sb_1__2__0_chany_bottom_out[2]:4 5.05203e-05 +8 cby_1__2_:chany_top_out[15] cby_1__2_:chany_top_in[9] 0.0001311006 +9 sb_1__2_:chany_bottom_in[15] sb_1__2_:chany_bottom_out[9] 0.0001311006 + +*RES +0 cby_1__2_:chany_top_out[15] sb_1__2_:chany_bottom_in[15] 0.009839287 + +*END + +*D_NET cby_1__1__1_left_grid_pin_10_[0] 0.001555176 //LENGTH 7.660 LUMPCC 0.0004164909 DR + +*CONN +*I cby_1__2_:left_grid_pin_10_[0] O *L 0 *C 548.470 748.000 +*I grid_clb_1__2_:right_width_0_height_0__pin_10_[0] I *L 0 *C 540.810 748.000 + +*CAP +0 cby_1__2_:left_grid_pin_10_[0] 0.0005693424 +1 grid_clb_1__2_:right_width_0_height_0__pin_10_[0] 0.0005693424 +2 cby_1__2_:left_grid_pin_10_[0] cby_1__2_:left_grid_pin_11_[0] 0.0001041227 +3 grid_clb_1__2_:right_width_0_height_0__pin_10_[0] grid_clb_1__2_:right_width_0_height_0__pin_11_[0] 0.0001041227 +4 cby_1__2_:left_grid_pin_10_[0] cby_1__2_:left_grid_pin_6_[0] 0.0001041227 +5 grid_clb_1__2_:right_width_0_height_0__pin_10_[0] grid_clb_1__2_:right_width_0_height_0__pin_6_[0] 0.0001041227 + +*RES +0 cby_1__2_:left_grid_pin_10_[0] grid_clb_1__2_:right_width_0_height_0__pin_10_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_1_[0] 0.001435601 //LENGTH 7.660 LUMPCC 0.0002088609 DR + +*CONN +*I cby_1__2_:left_grid_pin_1_[0] O *L 0 *C 548.470 764.320 +*I grid_clb_1__2_:right_width_0_height_0__pin_1_[0] I *L 0 *C 540.810 764.320 + +*CAP +0 cby_1__2_:left_grid_pin_1_[0] 0.0006133701 +1 grid_clb_1__2_:right_width_0_height_0__pin_1_[0] 0.0006133701 +2 cby_1__2_:left_grid_pin_1_[0] cby_1__2_:left_grid_pin_3_[0] 0.0001044305 +3 grid_clb_1__2_:right_width_0_height_0__pin_1_[0] grid_clb_1__2_:right_width_0_height_0__pin_3_[0] 0.0001044305 + +*RES +0 cby_1__2_:left_grid_pin_1_[0] grid_clb_1__2_:right_width_0_height_0__pin_1_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_7_[0] 0.001550116 //LENGTH 7.660 LUMPCC 0.0004304253 DR + +*CONN +*I cby_1__2_:left_grid_pin_7_[0] O *L 0 *C 548.470 768.400 +*I grid_clb_1__2_:right_width_0_height_0__pin_7_[0] I *L 0 *C 540.810 768.400 + +*CAP +0 cby_1__2_:left_grid_pin_7_[0] 0.0005598453 +1 grid_clb_1__2_:right_width_0_height_0__pin_7_[0] 0.0005598453 +2 cby_1__2_:left_grid_pin_7_[0] cby_1__2_:left_grid_pin_2_[0] 0.0001040338 +3 grid_clb_1__2_:right_width_0_height_0__pin_7_[0] grid_clb_1__2_:right_width_0_height_0__pin_2_[0] 0.0001040338 +4 cby_1__2_:left_grid_pin_7_[0] cby_1__2_:left_grid_pin_4_[0] 0.0001111788 +5 grid_clb_1__2_:right_width_0_height_0__pin_7_[0] grid_clb_1__2_:right_width_0_height_0__pin_4_[0] 0.0001111788 + +*RES +0 cby_1__2_:left_grid_pin_7_[0] grid_clb_1__2_:right_width_0_height_0__pin_7_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[1] 0.001151743 //LENGTH 11.020 LUMPCC 0.0003648679 DR + +*CONN +*I cby_2__1_:chany_bottom_out[1] O *L 0 *C 838.580 408.070 +*I sb_2__0_:chany_top_in[1] I *L 0 *C 838.580 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[1] 0.0003934374 +1 sb_2__0_:chany_top_in[1] 0.0003934374 +2 cby_2__1_:chany_bottom_out[1] cby_2__1_:chany_bottom_out[14] 3.533055e-05 +3 sb_2__0_:chany_top_in[1] sb_2__0_:chany_top_in[14] 3.533055e-05 +4 cby_2__1_:chany_bottom_out[1] cby_2__1_:chany_bottom_in[9] 0.0001471034 +5 sb_2__0_:chany_top_in[1] sb_2__0_:chany_top_out[9] 0.0001471034 + +*RES +0 cby_2__1_:chany_bottom_out[1] sb_2__0_:chany_top_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[8] 0.001231928 //LENGTH 11.020 LUMPCC 0.0005937052 DR + +*CONN +*I cby_2__1_:chany_bottom_out[8] O *L 0 *C 853.300 408.070 +*I sb_2__0_:chany_top_in[8] I *L 0 *C 853.300 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[8] 0.0003191112 +1 sb_2__0_:chany_top_in[8] 0.0003191112 +2 cby_2__1_:chany_bottom_out[8] cby_2__1_:chany_bottom_out[10] 0.0001484263 +3 sb_2__0_:chany_top_in[8] sb_2__0_:chany_top_in[10] 0.0001484263 +4 cby_2__1_:chany_bottom_out[8] cby_2__1_:chany_bottom_in[3] 0.0001484263 +5 sb_2__0_:chany_top_in[8] sb_2__0_:chany_top_out[3] 0.0001484263 + +*RES +0 cby_2__1_:chany_bottom_out[8] sb_2__0_:chany_top_in[8] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[12] 0.001231844 //LENGTH 11.020 LUMPCC 0.0005923904 DR + +*CONN +*I cby_2__1_:chany_bottom_out[12] O *L 0 *C 833.980 408.070 +*I sb_2__0_:chany_top_in[12] I *L 0 *C 833.980 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[12] 0.0003197266 +1 sb_2__0_:chany_top_in[12] 0.0003197266 +2 cby_2__1_:chany_bottom_out[12] cby_2__1_:chany_bottom_out[4] 0.000147909 +3 sb_2__0_:chany_top_in[12] sb_2__0_:chany_top_in[4] 0.000147909 +4 cby_2__1_:chany_bottom_out[12] cby_2__1_:chany_bottom_out[15] 0.0001482862 +5 sb_2__0_:chany_top_in[12] sb_2__0_:chany_top_in[15] 0.0001482862 + +*RES +0 cby_2__1_:chany_bottom_out[12] sb_2__0_:chany_top_in[12] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[19] 0.001231501 //LENGTH 11.020 LUMPCC 0.0005884135 DR + +*CONN +*I cby_2__1_:chany_bottom_out[19] O *L 0 *C 840.420 408.070 +*I sb_2__0_:chany_top_in[19] I *L 0 *C 840.420 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[19] 0.0003215438 +1 sb_2__0_:chany_top_in[19] 0.0003215438 +2 cby_2__1_:chany_bottom_out[19] cby_2__1_:chany_bottom_out[5] 0.0001471034 +3 sb_2__0_:chany_top_in[19] sb_2__0_:chany_top_in[5] 0.0001471034 +4 cby_2__1_:chany_bottom_out[19] cby_2__1_:chany_bottom_in[9] 0.0001471034 +5 sb_2__0_:chany_top_in[19] sb_2__0_:chany_top_out[9] 0.0001471034 + +*RES +0 cby_2__1_:chany_bottom_out[19] sb_2__0_:chany_top_in[19] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[4] 0.001261363 //LENGTH 11.020 LUMPCC 0.0005510945 DR + +*CONN +*I cby_2__1_:chany_top_out[4] O *L 0 *C 846.400 516.730 +*I sb_2__1_:chany_bottom_in[4] I *L 0 *C 846.400 527.750 + +*CAP +0 cby_2__1_:chany_top_out[4] 0.0003551343 +1 sb_2__1_:chany_bottom_in[4] 0.0003551343 +2 cby_2__1_:chany_top_out[4] cby_2__1_:chany_top_out[14] 0.0001377736 +3 sb_2__1_:chany_bottom_in[4] sb_2__1_:chany_bottom_in[14] 0.0001377736 +4 cby_2__1_:chany_top_out[4] cby_2__1_:chany_top_in[16] 0.0001377736 +5 sb_2__1_:chany_bottom_in[4] sb_2__1_:chany_bottom_out[16] 0.0001377736 + +*RES +0 cby_2__1_:chany_top_out[4] sb_2__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[10] 0.001261363 //LENGTH 11.020 LUMPCC 0.0005510945 DR + +*CONN +*I cby_2__1_:chany_top_out[10] O *L 0 *C 843.640 516.730 +*I sb_2__1_:chany_bottom_in[10] I *L 0 *C 843.640 527.750 + +*CAP +0 cby_2__1_:chany_top_out[10] 0.0003551343 +1 sb_2__1_:chany_bottom_in[10] 0.0003551343 +2 cby_2__1_:chany_top_out[10] cby_2__1_:chany_top_in[8] 0.0001377736 +3 sb_2__1_:chany_bottom_in[10] sb_2__1_:chany_bottom_out[8] 0.0001377736 +4 cby_2__1_:chany_top_out[10] cby_2__1_:chany_top_in[13] 0.0001377736 +5 sb_2__1_:chany_bottom_in[10] sb_2__1_:chany_bottom_out[13] 0.0001377736 + +*RES +0 cby_2__1_:chany_top_out[10] sb_2__1_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[14] 0.001281393 //LENGTH 11.020 LUMPCC 0.0005388171 DR + +*CONN +*I cby_2__1_:chany_top_out[14] O *L 0 *C 847.320 516.730 +*I sb_2__1_:chany_bottom_in[14] I *L 0 *C 847.320 527.750 + +*CAP +0 cby_2__1_:chany_top_out[14] 0.000371288 +1 sb_2__1_:chany_bottom_in[14] 0.000371288 +2 cby_2__1_:chany_top_out[14] cby_2__1_:chany_top_out[1] 0.0001316349 +3 sb_2__1_:chany_bottom_in[14] sb_2__1_:chany_bottom_in[1] 0.0001316349 +4 cby_2__1_:chany_top_out[14] cby_2__1_:chany_top_out[4] 0.0001377736 +5 sb_2__1_:chany_bottom_in[14] sb_2__1_:chany_bottom_in[4] 0.0001377736 + +*RES +0 cby_2__1_:chany_top_out[14] sb_2__1_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_10_[0] 0.001215779 //LENGTH 7.660 LUMPCC 0.0007181676 DR + +*CONN +*I cby_2__1_:left_grid_pin_10_[0] O *L 0 *C 809.750 486.880 +*I grid_clb_2__1_:right_width_0_height_0__pin_10_[0] I *L 0 *C 802.090 486.880 + +*CAP +0 cby_2__1_:left_grid_pin_10_[0] 0.0002488056 +1 grid_clb_2__1_:right_width_0_height_0__pin_10_[0] 0.0002488056 +2 cby_2__1_:left_grid_pin_10_[0] cby_2__1_:left_grid_pin_11_[0] 0.0001795419 +3 grid_clb_2__1_:right_width_0_height_0__pin_10_[0] grid_clb_2__1_:right_width_0_height_0__pin_11_[0] 0.0001795419 +4 cby_2__1_:left_grid_pin_10_[0] cby_2__1_:left_grid_pin_6_[0] 0.0001795419 +5 grid_clb_2__1_:right_width_0_height_0__pin_10_[0] grid_clb_2__1_:right_width_0_height_0__pin_6_[0] 0.0001795419 + +*RES +0 cby_2__1_:left_grid_pin_10_[0] grid_clb_2__1_:right_width_0_height_0__pin_10_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_1_[0] 0.001083464 //LENGTH 7.660 LUMPCC 0.0003590583 DR + +*CONN +*I cby_2__1_:left_grid_pin_1_[0] O *L 0 *C 809.750 503.200 +*I grid_clb_2__1_:right_width_0_height_0__pin_1_[0] I *L 0 *C 802.090 503.200 + +*CAP +0 cby_2__1_:left_grid_pin_1_[0] 0.000362203 +1 grid_clb_2__1_:right_width_0_height_0__pin_1_[0] 0.000362203 +2 cby_2__1_:left_grid_pin_1_[0] cby_2__1_:left_grid_pin_3_[0] 0.0001795292 +3 grid_clb_2__1_:right_width_0_height_0__pin_1_[0] grid_clb_2__1_:right_width_0_height_0__pin_3_[0] 0.0001795292 + +*RES +0 cby_2__1_:left_grid_pin_1_[0] grid_clb_2__1_:right_width_0_height_0__pin_1_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_5_[0] 0.001096476 //LENGTH 7.660 LUMPCC 0.0003637765 DR + +*CONN +*I cby_2__1_:left_grid_pin_5_[0] O *L 0 *C 809.750 511.360 +*I grid_clb_2__1_:right_width_0_height_0__pin_5_[0] I *L 0 *C 802.090 511.360 + +*CAP +0 cby_2__1_:left_grid_pin_5_[0] 0.0003663498 +1 grid_clb_2__1_:right_width_0_height_0__pin_5_[0] 0.0003663498 +2 cby_2__1_:left_grid_pin_5_[0] cby_2__1_:left_grid_pin_0_[0] 0.0001818883 +3 grid_clb_2__1_:right_width_0_height_0__pin_5_[0] grid_clb_2__1_:right_width_0_height_0__pin_0_[0] 0.0001818883 + +*RES +0 cby_2__1_:left_grid_pin_5_[0] grid_clb_2__1_:right_width_0_height_0__pin_5_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_right_grid_pin_52_[0] 0.001721974 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_2__1_:right_grid_pin_52_[0] O *L 0 *C 894.090 486.880 +*I grid_io_right_3__1_:left_width_0_height_0__pin_0_[0] I *L 0 *C 907.270 486.880 + +*CAP +0 cby_2__1_:right_grid_pin_52_[0] 0.0008609872 +1 grid_io_right_3__1_:left_width_0_height_0__pin_0_[0] 0.0008609872 + +*RES +0 cby_2__1_:right_grid_pin_52_[0] grid_io_right_3__1_:left_width_0_height_0__pin_0_[0] 0.002064867 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[2] 0.001222901 //LENGTH 11.020 LUMPCC 0.0004377299 DR + +*CONN +*I cby_2__2_:chany_bottom_out[2] O *L 0 *C 863.420 669.190 +*I sb_2__1_:chany_top_in[2] I *L 0 *C 863.420 658.170 +*N cby_1__1__3_chany_bottom_out[2]:2 *C 863.420 667.519 +*N cby_1__1__3_chany_bottom_out[2]:3 *C 863.420 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[2] 0.000117268 +1 sb_2__1_:chany_top_in[2] 0.0002753175 +2 cby_1__1__3_chany_bottom_out[2]:2 0.0002753175 +3 cby_1__1__3_chany_bottom_out[2]:3 0.000117268 +4 cby_2__2_:chany_bottom_out[2] cby_2__2_:chany_bottom_out[17] 7.295327e-06 +5 sb_2__1_:chany_top_in[2] sb_2__1_:chany_top_in[17] 0.000128175 +6 cby_1__1__3_chany_bottom_out[2]:3 cby_1__1__3_chany_bottom_out[17]:3 7.295327e-06 +7 cby_1__1__3_chany_bottom_out[2]:2 cby_1__1__3_chany_bottom_out[17]:2 0.000128175 +8 cby_2__2_:chany_bottom_out[2] cby_2__2_:chany_bottom_in[5] 1.470669e-06 +9 sb_2__1_:chany_top_in[2] sb_2__1_:chany_top_out[5] 8.1924e-05 +10 cby_1__1__3_chany_bottom_out[2]:3 sb_2__1__0_chany_top_out[5]:2 1.470669e-06 +11 cby_1__1__3_chany_bottom_out[2]:2 sb_2__1__0_chany_top_out[5]:3 8.1924e-05 + +*RES +0 cby_2__2_:chany_bottom_out[2] cby_1__1__3_chany_bottom_out[2]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[2]:3 cby_1__1__3_chany_bottom_out[2]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[2]:2 sb_2__1_:chany_top_in[2] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[7] 0.001198851 //LENGTH 11.020 LUMPCC 0.0003681188 DR + +*CONN +*I cby_2__2_:chany_bottom_out[7] O *L 0 *C 847.780 669.190 +*I sb_2__1_:chany_top_in[7] I *L 0 *C 847.780 658.170 +*N cby_1__1__3_chany_bottom_out[7]:2 *C 847.780 667.519 +*N cby_1__1__3_chany_bottom_out[7]:3 *C 847.780 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[7] 0.000118814 +1 sb_2__1_:chany_top_in[7] 0.0002965521 +2 cby_1__1__3_chany_bottom_out[7]:2 0.0002965521 +3 cby_1__1__3_chany_bottom_out[7]:3 0.000118814 +4 cby_2__2_:chany_bottom_out[7] cby_2__2_:chany_bottom_out[9] 7.294814e-06 +5 sb_2__1_:chany_top_in[7] sb_2__1_:chany_top_in[9] 0.0001283662 +6 cby_1__1__3_chany_bottom_out[7]:3 cby_1__1__3_chany_bottom_out[9]:3 7.294814e-06 +7 cby_1__1__3_chany_bottom_out[7]:2 cby_1__1__3_chany_bottom_out[9]:2 0.0001283662 +8 sb_2__1_:chany_top_in[7] sb_2__1_:chany_top_out[13] 4.839835e-05 +9 cby_1__1__3_chany_bottom_out[7]:2 sb_2__1__0_chany_top_out[13]:3 4.839835e-05 + +*RES +0 cby_2__2_:chany_bottom_out[7] cby_1__1__3_chany_bottom_out[7]:3 0.001491071 +1 cby_1__1__3_chany_bottom_out[7]:3 cby_1__1__3_chany_bottom_out[7]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[7]:2 sb_2__1_:chany_top_in[7] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[13] 0.001194998 //LENGTH 11.020 LUMPCC 0.0004646215 DR + +*CONN +*I cby_2__2_:chany_bottom_out[13] O *L 0 *C 844.560 669.190 +*I sb_2__1_:chany_top_in[13] I *L 0 *C 844.560 658.170 +*N cby_1__1__3_chany_bottom_out[13]:2 *C 844.560 667.519 +*N cby_1__1__3_chany_bottom_out[13]:3 *C 844.560 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[13] 0.0001176985 +1 sb_2__1_:chany_top_in[13] 0.0002474897 +2 cby_1__1__3_chany_bottom_out[13]:2 0.0002474897 +3 cby_1__1__3_chany_bottom_out[13]:3 0.0001176985 +4 cby_2__2_:chany_bottom_out[13] cby_2__2_:chany_bottom_in[13] 7.441422e-06 +5 sb_2__1_:chany_top_in[13] sb_2__1_:chany_top_out[13] 0.0001353879 +6 cby_1__1__3_chany_bottom_out[13]:3 sb_2__1__0_chany_top_out[13]:2 7.441422e-06 +7 cby_1__1__3_chany_bottom_out[13]:2 sb_2__1__0_chany_top_out[13]:3 0.0001353879 +8 cby_2__2_:chany_bottom_out[13] cby_2__2_:chany_bottom_in[17] 6.088952e-07 +9 sb_2__1_:chany_top_in[13] sb_2__1_:chany_top_out[17] 8.88725e-05 +10 cby_1__1__3_chany_bottom_out[13]:3 sb_2__1__0_chany_top_out[17]:2 6.088952e-07 +11 cby_1__1__3_chany_bottom_out[13]:2 sb_2__1__0_chany_top_out[17]:3 8.88725e-05 + +*RES +0 cby_2__2_:chany_bottom_out[13] cby_1__1__3_chany_bottom_out[13]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[13]:3 cby_1__1__3_chany_bottom_out[13]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[13]:2 sb_2__1_:chany_top_in[13] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_top_out[1] 0.00126029 //LENGTH 11.020 LUMPCC 0.0005569746 DR + +*CONN +*I cby_2__2_:chany_top_out[1] O *L 0 *C 848.240 777.850 +*I sb_2__2_:chany_bottom_in[1] I *L 0 *C 848.240 788.870 + +*CAP +0 cby_2__2_:chany_top_out[1] 0.0003516579 +1 sb_2__2_:chany_bottom_in[1] 0.0003516579 +2 cby_2__2_:chany_top_out[1] cby_2__2_:chany_top_out[13] 0.0001392436 +3 sb_2__2_:chany_bottom_in[1] sb_2__2_:chany_bottom_in[13] 0.0001392436 +4 cby_2__2_:chany_top_out[1] cby_2__2_:chany_top_out[14] 0.0001392436 +5 sb_2__2_:chany_bottom_in[1] sb_2__2_:chany_bottom_in[14] 0.0001392436 + +*RES +0 cby_2__2_:chany_top_out[1] sb_2__2_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[6] 0.001171785 //LENGTH 11.020 LUMPCC 0.0003884984 DR + +*CONN +*I cby_2__2_:chany_top_out[6] O *L 0 *C 875.380 777.850 +*I sb_2__2_:chany_bottom_in[6] I *L 0 *C 875.380 788.870 + +*CAP +0 cby_2__2_:chany_top_out[6] 0.0003916434 +1 sb_2__2_:chany_bottom_in[6] 0.0003916434 +2 cby_2__2_:chany_top_out[6] cby_2__2_:chany_top_in[4] 5.026654e-05 +3 sb_2__2_:chany_bottom_in[6] sb_2__2_:chany_bottom_out[4] 5.026654e-05 +4 cby_2__2_:chany_top_out[6] cby_2__2_:chany_top_in[10] 0.0001439826 +5 sb_2__2_:chany_bottom_in[6] sb_2__2_:chany_bottom_out[10] 0.0001439826 + +*RES +0 cby_2__2_:chany_top_out[6] sb_2__2_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[13] 0.00126029 //LENGTH 11.020 LUMPCC 0.0005569746 DR + +*CONN +*I cby_2__2_:chany_top_out[13] O *L 0 *C 849.160 777.850 +*I sb_2__2_:chany_bottom_in[13] I *L 0 *C 849.160 788.870 + +*CAP +0 cby_2__2_:chany_top_out[13] 0.0003516579 +1 sb_2__2_:chany_bottom_in[13] 0.0003516579 +2 cby_2__2_:chany_top_out[13] cby_2__2_:chany_top_out[1] 0.0001392436 +3 sb_2__2_:chany_bottom_in[13] sb_2__2_:chany_bottom_in[1] 0.0001392436 +4 cby_2__2_:chany_top_out[13] cby_2__2_:chany_top_in[3] 0.0001392436 +5 sb_2__2_:chany_bottom_in[13] sb_2__2_:chany_bottom_out[3] 0.0001392436 + +*RES +0 cby_2__2_:chany_top_out[13] sb_2__2_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[18] 0.001143015 //LENGTH 11.020 LUMPCC 0.0002694291 DR + +*CONN +*I cby_2__2_:chany_top_out[18] O *L 0 *C 838.580 777.850 +*I sb_2__2_:chany_bottom_in[18] I *L 0 *C 838.580 788.870 + +*CAP +0 cby_2__2_:chany_top_out[18] 0.000436793 +1 sb_2__2_:chany_bottom_in[18] 0.000436793 +2 cby_2__2_:chany_top_out[18] cby_2__2_:chany_top_in[15] 4.537184e-05 +3 sb_2__2_:chany_bottom_in[18] sb_2__2_:chany_bottom_out[15] 4.537184e-05 +4 cby_2__2_:chany_top_out[18] cby_2__2_:chany_top_in[17] 8.934273e-05 +5 sb_2__2_:chany_bottom_in[18] sb_2__2_:chany_bottom_out[17] 8.934273e-05 + +*RES +0 cby_2__2_:chany_top_out[18] sb_2__2_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_14_[0] 0.001087852 //LENGTH 7.660 LUMPCC 0.0003573897 DR + +*CONN +*I cby_2__2_:left_grid_pin_14_[0] O *L 0 *C 809.750 724.880 +*I grid_clb_2__2_:right_width_0_height_0__pin_14_[0] I *L 0 *C 802.090 724.880 + +*CAP +0 cby_2__2_:left_grid_pin_14_[0] 0.0003652311 +1 grid_clb_2__2_:right_width_0_height_0__pin_14_[0] 0.0003652311 +2 cby_2__2_:left_grid_pin_14_[0] cby_2__2_:left_grid_pin_13_[0] 0.0001786949 +3 grid_clb_2__2_:right_width_0_height_0__pin_14_[0] grid_clb_2__2_:right_width_0_height_0__pin_13_[0] 0.0001786949 + +*RES +0 cby_2__2_:left_grid_pin_14_[0] grid_clb_2__2_:right_width_0_height_0__pin_14_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_6_[0] 0.001220462 //LENGTH 7.660 LUMPCC 0.0007117843 DR + +*CONN +*I cby_2__2_:left_grid_pin_6_[0] O *L 0 *C 809.750 749.360 +*I grid_clb_2__2_:right_width_0_height_0__pin_6_[0] I *L 0 *C 802.090 749.360 + +*CAP +0 cby_2__2_:left_grid_pin_6_[0] 0.0002543388 +1 grid_clb_2__2_:right_width_0_height_0__pin_6_[0] 0.0002543388 +2 cby_2__2_:left_grid_pin_6_[0] cby_2__2_:left_grid_pin_10_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_6_[0] grid_clb_2__2_:right_width_0_height_0__pin_10_[0] 0.0001767511 +4 cby_2__2_:left_grid_pin_6_[0] cby_2__2_:left_grid_pin_9_[0] 0.0001791411 +5 grid_clb_2__2_:right_width_0_height_0__pin_6_[0] grid_clb_2__2_:right_width_0_height_0__pin_9_[0] 0.0001791411 + +*RES +0 cby_2__2_:left_grid_pin_6_[0] grid_clb_2__2_:right_width_0_height_0__pin_6_[0] 0.001200067 + +*END + +*D_NET direct_interc_5_out[0] 0.07608429 //LENGTH 736.140 LUMPCC 0.006804959 DR + +*CONN +*I direct_interc_5_\/FTB_6__5:X O *L 0 *C 521.415 379.100 +*I grid_clb_2__2_:top_width_0_height_0__pin_33_[0] I *L 0 *C 777.400 805.050 +*N direct_interc_5_out[0]:2 *C 777.400 805.755 +*N direct_interc_5_out[0]:3 *C 777.355 805.800 +*N direct_interc_5_out[0]:4 *C 734.640 805.800 +*N direct_interc_5_out[0]:5 *C 684.640 805.800 +*N direct_interc_5_out[0]:6 *C 667.520 805.800 +*N direct_interc_5_out[0]:7 *C 667.519 805.800 +*N direct_interc_5_out[0]:8 *C 634.845 805.800 +*N direct_interc_5_out[0]:9 *C 634.800 805.755 +*N direct_interc_5_out[0]:10 *C 634.800 784.425 +*N direct_interc_5_out[0]:11 *C 634.755 784.380 +*N direct_interc_5_out[0]:12 *C 594.940 784.380 +*N direct_interc_5_out[0]:13 *C 545.145 784.380 +*N direct_interc_5_out[0]:14 *C 545.100 784.335 +*N direct_interc_5_out[0]:15 *C 545.100 734.620 +*N direct_interc_5_out[0]:16 *C 545.100 684.620 +*N direct_interc_5_out[0]:17 *C 545.100 667.520 +*N direct_interc_5_out[0]:18 *C 545.100 667.519 +*N direct_interc_5_out[0]:19 *C 545.100 634.825 +*N direct_interc_5_out[0]:20 *C 545.055 634.780 +*N direct_interc_5_out[0]:21 *C 518.925 634.780 +*N direct_interc_5_out[0]:22 *C 518.880 634.735 +*N direct_interc_5_out[0]:23 *C 518.880 603.020 +*N direct_interc_5_out[0]:24 *C 518.880 553.225 +*N direct_interc_5_out[0]:25 *C 518.925 553.180 +*N direct_interc_5_out[0]:26 *C 543.675 553.180 +*N direct_interc_5_out[0]:27 *C 543.720 553.135 +*N direct_interc_5_out[0]:28 *C 543.720 528.940 +*N direct_interc_5_out[0]:29 *C 543.720 478.940 +*N direct_interc_5_out[0]:30 *C 543.720 443.520 +*N direct_interc_5_out[0]:31 *C 543.720 443.519 +*N direct_interc_5_out[0]:32 *C 543.720 428.940 +*N direct_interc_5_out[0]:33 *C 543.720 379.145 +*N direct_interc_5_out[0]:34 *C 543.675 379.100 +*N direct_interc_5_out[0]:35 *C 521.452 379.100 + +*CAP +0 direct_interc_5_\/FTB_6__5:X 1e-06 +1 grid_clb_2__2_:top_width_0_height_0__pin_33_[0] 7.22194e-05 +2 direct_interc_5_out[0]:2 7.22194e-05 +3 direct_interc_5_out[0]:3 0.002727136 +4 direct_interc_5_out[0]:4 0.005901633 +5 direct_interc_5_out[0]:5 0.00426445 +6 direct_interc_5_out[0]:6 0.001089953 +7 direct_interc_5_out[0]:7 0.002057817 +8 direct_interc_5_out[0]:8 0.002057817 +9 direct_interc_5_out[0]:9 0.0009884761 +10 direct_interc_5_out[0]:10 0.0009884761 +11 direct_interc_5_out[0]:11 0.002035476 +12 direct_interc_5_out[0]:12 0.004560156 +13 direct_interc_5_out[0]:13 0.00252468 +14 direct_interc_5_out[0]:14 0.002165603 +15 direct_interc_5_out[0]:15 0.004385345 +16 direct_interc_5_out[0]:16 0.002980179 +17 direct_interc_5_out[0]:17 0.0007604377 +18 direct_interc_5_out[0]:18 0.00143316 +19 direct_interc_5_out[0]:19 0.00143316 +20 direct_interc_5_out[0]:20 0.001326195 +21 direct_interc_5_out[0]:21 0.001326195 +22 direct_interc_5_out[0]:22 0.001237296 +23 direct_interc_5_out[0]:23 0.003329127 +24 direct_interc_5_out[0]:24 0.002091831 +25 direct_interc_5_out[0]:25 0.00126038 +26 direct_interc_5_out[0]:26 0.00126038 +27 direct_interc_5_out[0]:27 0.0007931237 +28 direct_interc_5_out[0]:28 0.002814693 +29 direct_interc_5_out[0]:29 0.003412769 +30 direct_interc_5_out[0]:30 0.001391199 +31 direct_interc_5_out[0]:31 0.0005847157 +32 direct_interc_5_out[0]:32 0.00241061 +33 direct_interc_5_out[0]:33 0.001825895 +34 direct_interc_5_out[0]:34 0.0008577626 +35 direct_interc_5_out[0]:35 0.0008577626 +36 direct_interc_5_out[0]:24 cbx_1__1__0_chanx_right_out[2]:4 4.971748e-05 +37 direct_interc_5_out[0]:23 cbx_1__1__0_chanx_right_out[2]:3 4.971748e-05 +38 grid_clb_2__2_:top_width_0_height_0__pin_33_[0] grid_clb_2__2_:top_width_0_height_0__pin_32_[0] 3.124996e-06 +39 direct_interc_5_out[0]:3 direct_interc_2_out[0]:4 4.625643e-05 +40 direct_interc_5_out[0]:3 direct_interc_2_out[0]:5 5.770687e-06 +41 direct_interc_5_out[0]:2 direct_interc_2_out[0]:3 3.124996e-06 +42 direct_interc_5_out[0]:8 direct_interc_2_out[0]:9 3.392201e-05 +43 direct_interc_5_out[0]:9 direct_interc_2_out[0]:10 3.862638e-05 +44 direct_interc_5_out[0]:10 direct_interc_2_out[0]:11 3.862638e-05 +45 direct_interc_5_out[0]:34 direct_interc_2_out[0]:37 0.0004318054 +46 direct_interc_5_out[0]:33 direct_interc_2_out[0]:36 0.0003086128 +47 direct_interc_5_out[0]:35 direct_interc_2_out[0]:38 0.0004318054 +48 direct_interc_5_out[0]:5 direct_interc_2_out[0]:6 7.525101e-05 +49 direct_interc_5_out[0]:5 direct_interc_2_out[0]:7 5.769043e-06 +50 direct_interc_5_out[0]:4 direct_interc_2_out[0]:5 0.0001040643 +51 direct_interc_5_out[0]:4 direct_interc_2_out[0]:6 1.153973e-05 +52 direct_interc_5_out[0]:32 direct_interc_2_out[0]:35 0.0003086128 +53 direct_interc_5_out[0]:6 direct_interc_2_out[0]:7 1.744316e-05 +54 direct_interc_5_out[0]:7 direct_interc_2_out[0]:8 3.392201e-05 +55 direct_interc_5_out[0]:22 direct_interc_3_out[0]:6 0.0001714074 +56 direct_interc_5_out[0]:22 direct_interc_3_out[0]:7 0.0002440483 +57 direct_interc_5_out[0]:24 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] 6.310035e-06 +58 direct_interc_5_out[0]:24 direct_interc_3_out[0]:5 0.00045315 +59 direct_interc_5_out[0]:23 direct_interc_3_out[0]:2 6.310035e-06 +60 direct_interc_5_out[0]:23 direct_interc_3_out[0]:5 0.0001714074 +61 direct_interc_5_out[0]:23 direct_interc_3_out[0]:6 0.0006971983 +62 direct_interc_5_out[0]:33 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 2.476164e-05 +63 direct_interc_5_out[0]:33 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 2.335628e-05 +64 direct_interc_5_out[0]:32 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 2.476164e-05 +65 direct_interc_5_out[0]:32 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 2.335628e-05 +66 direct_interc_5_out[0]:19 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 7.971468e-05 +67 direct_interc_5_out[0]:16 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 1.367442e-05 +68 direct_interc_5_out[0]:17 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 1.367442e-05 +69 direct_interc_5_out[0]:18 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 7.971468e-05 +70 direct_interc_5_out[0]:13 sb_1__2__0_chany_bottom_out[2]:2 1.898727e-05 +71 direct_interc_5_out[0]:13 sb_1__2__0_chany_bottom_out[2]:5 2.388444e-05 +72 direct_interc_5_out[0]:12 sb_1__2__0_chany_bottom_out[2]:3 1.898727e-05 +73 direct_interc_5_out[0]:12 sb_1__2__0_chany_bottom_out[2]:4 2.388444e-05 +74 direct_interc_5_out[0]:11 sb_1__2__0_chany_bottom_out[14]:8 3.082647e-05 +75 direct_interc_5_out[0]:12 sb_1__2__0_chany_bottom_out[14]:7 3.082647e-05 +76 direct_interc_5_out[0]:33 ctsbuf_net_211:13 6.457772e-05 +77 direct_interc_5_out[0]:33 ctsbuf_net_211:9 2.425511e-06 +78 direct_interc_5_out[0]:32 ctsbuf_net_211:13 3.813218e-05 +79 direct_interc_5_out[0]:32 ctsbuf_net_211:14 6.457772e-05 +80 direct_interc_5_out[0]:29 ctsbuf_net_211:16 6.157121e-05 +81 direct_interc_5_out[0]:29 ctsbuf_net_211:17 0.0001344093 +82 direct_interc_5_out[0]:28 ctsbuf_net_211:18 5.386257e-05 +83 direct_interc_5_out[0]:28 ctsbuf_net_211:17 4.772252e-05 +84 direct_interc_5_out[0]:30 ctsbuf_net_211:16 8.054676e-05 +85 direct_interc_5_out[0]:30 ctsbuf_net_211:15 1.38487e-05 +86 direct_interc_5_out[0]:31 ctsbuf_net_211:14 3.570667e-05 +87 direct_interc_5_out[0]:13 ctsbuf_net_716:4 8.970885e-06 +88 direct_interc_5_out[0]:14 ctsbuf_net_716:9 0.0001206958 +89 direct_interc_5_out[0]:12 ctsbuf_net_716:3 8.970885e-06 +90 direct_interc_5_out[0]:15 ctsbuf_net_716:8 0.0001206958 +91 direct_interc_5_out[0]:33 ctsbuf_net_1019:6 0.0001107969 +92 direct_interc_5_out[0]:33 ctsbuf_net_1019:7 1.946896e-05 +93 direct_interc_5_out[0]:32 ctsbuf_net_1019:7 0.0001519206 +94 direct_interc_5_out[0]:32 ctsbuf_net_1019:8 1.946896e-05 +95 direct_interc_5_out[0]:29 ctsbuf_net_1019:12 1.916155e-05 +96 direct_interc_5_out[0]:29 ctsbuf_net_1019:13 3.410022e-05 +97 direct_interc_5_out[0]:29 ctsbuf_net_1019:10 0.0001293115 +98 direct_interc_5_out[0]:28 ctsbuf_net_1019:14 3.410022e-05 +99 direct_interc_5_out[0]:28 ctsbuf_net_1019:12 4.908455e-05 +100 direct_interc_5_out[0]:30 ctsbuf_net_1019:10 1.916155e-05 +101 direct_interc_5_out[0]:30 ctsbuf_net_1019:9 8.022691e-05 +102 direct_interc_5_out[0]:31 ctsbuf_net_1019:8 4.112373e-05 +103 direct_interc_5_out[0]:25 ctsbuf_net_1928:30 1.61847e-05 +104 direct_interc_5_out[0]:25 ctsbuf_net_1928:29 1.049368e-05 +105 direct_interc_5_out[0]:26 ctsbuf_net_1928:28 1.049368e-05 +106 direct_interc_5_out[0]:26 ctsbuf_net_1928:29 1.61847e-05 +107 direct_interc_5_out[0]:27 ctsbuf_net_1928:27 0.0002079 +108 direct_interc_5_out[0]:29 ctsbuf_net_1928:26 2.705551e-05 +109 direct_interc_5_out[0]:28 ctsbuf_net_1928:27 2.705551e-05 +110 direct_interc_5_out[0]:28 ctsbuf_net_1928:26 0.0002079 +111 direct_interc_5_out[0]:27 ctsbuf_net_2029:35 0.0002022201 +112 direct_interc_5_out[0]:29 ctsbuf_net_2029:34 6.732917e-05 +113 direct_interc_5_out[0]:28 ctsbuf_net_2029:34 0.0002022201 +114 direct_interc_5_out[0]:28 ctsbuf_net_2029:35 6.732917e-05 + +*RES +0 direct_interc_5_\/FTB_6__5:X direct_interc_5_out[0]:35 0.152 +1 direct_interc_5_out[0]:3 direct_interc_5_out[0]:2 0.0045 +2 direct_interc_5_out[0]:2 grid_clb_2__2_:top_width_0_height_0__pin_33_[0] 0.0006294643 +3 direct_interc_5_out[0]:8 direct_interc_5_out[0]:7 0.02917322 +4 direct_interc_5_out[0]:9 direct_interc_5_out[0]:8 0.0045 +5 direct_interc_5_out[0]:11 direct_interc_5_out[0]:10 0.0045 +6 direct_interc_5_out[0]:10 direct_interc_5_out[0]:9 0.01904465 +7 direct_interc_5_out[0]:13 direct_interc_5_out[0]:12 0.04445983 +8 direct_interc_5_out[0]:14 direct_interc_5_out[0]:13 0.0045 +9 direct_interc_5_out[0]:20 direct_interc_5_out[0]:19 0.0045 +10 direct_interc_5_out[0]:19 direct_interc_5_out[0]:18 0.02919107 +11 direct_interc_5_out[0]:21 direct_interc_5_out[0]:20 0.02333036 +12 direct_interc_5_out[0]:22 direct_interc_5_out[0]:21 0.0045 +13 direct_interc_5_out[0]:25 direct_interc_5_out[0]:24 0.0045 +14 direct_interc_5_out[0]:24 direct_interc_5_out[0]:23 0.04445982 +15 direct_interc_5_out[0]:26 direct_interc_5_out[0]:25 0.02209822 +16 direct_interc_5_out[0]:27 direct_interc_5_out[0]:26 0.0045 +17 direct_interc_5_out[0]:34 direct_interc_5_out[0]:33 0.0045 +18 direct_interc_5_out[0]:33 direct_interc_5_out[0]:32 0.04445983 +19 direct_interc_5_out[0]:35 direct_interc_5_out[0]:34 0.01984152 +20 direct_interc_5_out[0]:12 direct_interc_5_out[0]:11 0.03554911 +21 direct_interc_5_out[0]:5 direct_interc_5_out[0]:4 0.04464286 +22 direct_interc_5_out[0]:4 direct_interc_5_out[0]:3 0.0381384 +23 direct_interc_5_out[0]:23 direct_interc_5_out[0]:22 0.02831697 +24 direct_interc_5_out[0]:32 direct_interc_5_out[0]:31 0.01301696 +25 direct_interc_5_out[0]:29 direct_interc_5_out[0]:28 0.04464286 +26 direct_interc_5_out[0]:28 direct_interc_5_out[0]:27 0.02160268 +27 direct_interc_5_out[0]:16 direct_interc_5_out[0]:15 0.04464286 +28 direct_interc_5_out[0]:15 direct_interc_5_out[0]:14 0.0443884 +29 direct_interc_5_out[0]:6 direct_interc_5_out[0]:5 0.01528571 +30 direct_interc_5_out[0]:7 direct_interc_5_out[0]:6 1e-05 +31 direct_interc_5_out[0]:30 direct_interc_5_out[0]:29 0.031625 +32 direct_interc_5_out[0]:31 direct_interc_5_out[0]:30 1e-05 +33 direct_interc_5_out[0]:17 direct_interc_5_out[0]:16 0.01526786 +34 direct_interc_5_out[0]:18 direct_interc_5_out[0]:17 1e-05 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_50_[0] 0.0008158414 //LENGTH 7.690 LUMPCC 9.073467e-05 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_50_[0] O *L 0 *C 515.200 380.870 +*I direct_interc_2_\/FTB_3__2:A I *L 0.001746 *C 513.820 379.440 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:2 *C 513.820 379.440 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 *C 513.820 379.395 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 *C 513.820 377.445 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:5 *C 513.865 377.400 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:6 *C 515.155 377.400 +*N grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 *C 515.200 377.445 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_50_[0] 0.0001815841 +1 direct_interc_2_\/FTB_3__2:A 1e-06 +2 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:2 3.220866e-05 +3 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 6.417189e-05 +4 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 6.417189e-05 +5 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:5 0.000100193 +6 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:6 0.000100193 +7 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 0.0001815841 +8 grid_clb_1__1_:bottom_width_0_height_0__pin_50_[0] ctsbuf_net_211:6 3.698759e-06 +9 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 ctsbuf_net_211:6 4.166857e-05 +10 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 ctsbuf_net_211:5 4.166857e-05 +11 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 ctsbuf_net_211:5 3.698759e-06 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_50_[0] grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 0.003058036 +1 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:2 direct_interc_2_\/FTB_3__2:A 0.152 +2 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:2 0.0045 +3 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:5 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 0.0045 +4 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 0.001741072 +5 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:6 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:5 0.001151786 +6 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:6 0.0045 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_35_lower[0] 0.002640109 //LENGTH 20.775 LUMPCC 0.0007595135 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] O *L 0 *C 540.810 405.280 +*I sb_1__0_:top_left_grid_pin_35_[0] I *L 0 *C 552.920 396.970 +*N grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 *C 552.920 405.273 +*N grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 *C 552.900 405.280 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] 0.0004764156 +1 sb_1__0_:top_left_grid_pin_35_[0] 0.000463882 +2 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 0.000463882 +3 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 0.0004764156 +4 grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] direct_interc_2_out[0]:34 0.0001023637 +5 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 direct_interc_2_out[0]:33 0.0001023637 +6 grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] 0.0002721755 +7 sb_1__0_:top_left_grid_pin_35_[0] sb_1__0_:top_left_grid_pin_34_[0] 5.217548e-06 +8 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 0.0002721755 +9 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 5.217548e-06 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 0.0018941 +1 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 0.00341 +2 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 sb_1__0_:top_left_grid_pin_35_[0] 0.001300725 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_38_upper[0] 0.001500615 //LENGTH 7.660 LUMPCC 0.0003382426 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] O *L 0 *C 540.810 532.440 +*I sb_1__1_:bottom_left_grid_pin_38_[0] I *L 0 *C 548.470 532.440 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] 0.000581186 +1 sb_1__1_:bottom_left_grid_pin_38_[0] 0.000581186 +2 grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] 6.556654e-05 +3 sb_1__1_:bottom_left_grid_pin_38_[0] sb_1__1_:bottom_left_grid_pin_36_[0] 6.556654e-05 +4 grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] 0.0001035548 +5 sb_1__1_:bottom_left_grid_pin_38_[0] sb_1__1_:bottom_left_grid_pin_37_[0] 0.0001035548 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] sb_1__1_:bottom_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_46_upper[0] 0.001271059 //LENGTH 7.660 LUMPCC 0.0003001954 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_46_upper[0] O *L 0 *C 379.190 646.680 +*I sb_0__1_:right_top_grid_pin_46_[0] I *L 0 *C 371.530 646.680 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_46_upper[0] 0.0004854318 +1 sb_0__1_:right_top_grid_pin_46_[0] 0.0004854318 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_47_upper[0] 0.0001500977 +3 sb_0__1_:right_top_grid_pin_46_[0] sb_0__1_:right_top_grid_pin_47_[0] 0.0001500977 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_46_upper[0] sb_0__1_:right_top_grid_pin_46_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_49_lower[0] 0.001172928 //LENGTH 11.020 LUMPCC 0.0003291383 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] O *L 0 *C 530.380 641.990 +*I sb_1__1_:left_top_grid_pin_49_[0] I *L 0 *C 530.380 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] 0.0004218951 +1 sb_1__1_:left_top_grid_pin_49_[0] 0.0004218951 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] 2.410214e-05 +3 sb_1__1_:left_top_grid_pin_49_[0] sb_1__1_:left_top_grid_pin_42_[0] 2.410214e-05 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_48_lower[0] 0.000140467 +5 sb_1__1_:left_top_grid_pin_49_[0] sb_1__1_:left_top_grid_pin_48_[0] 0.000140467 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] sb_1__1_:left_top_grid_pin_49_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_37_lower[0] 0.002486498 //LENGTH 21.750 LUMPCC 0.0004361132 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_37_lower[0] O *L 0 *C 540.810 669.120 +*I sb_1__1_:top_left_grid_pin_37_[0] I *L 0 *C 550.620 658.170 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 *C 550.620 659.215 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:3 *C 550.575 659.260 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:4 *C 546.525 659.260 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 *C 546.480 659.305 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 *C 546.480 667.519 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 *C 546.480 667.520 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 *C 546.480 669.062 +*N grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 *C 546.473 669.120 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_37_lower[0] 0.0003731477 +1 sb_1__1_:top_left_grid_pin_37_[0] 5.643877e-05 +2 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 5.643877e-05 +3 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:3 0.0002179867 +4 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:4 0.0002179867 +5 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 0.0003034095 +6 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 0.0003034095 +7 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 7.420982e-05 +8 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 7.420982e-05 +9 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 0.0003731477 +10 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 direct_interc_5_out[0]:16 1.367442e-05 +11 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 direct_interc_5_out[0]:19 7.971468e-05 +12 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 direct_interc_5_out[0]:17 1.367442e-05 +13 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 direct_interc_5_out[0]:18 7.971468e-05 +14 grid_clb_1__2_:right_width_0_height_0__pin_37_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] 0.0001086187 +15 sb_1__1_:top_left_grid_pin_37_[0] sb_1__1_:top_left_grid_pin_34_[0] 1.604878e-05 +16 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 0.0001086187 +17 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 1.604878e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_37_lower[0] grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 0.0008871249 +1 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 0.001377232 +2 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:8 0.00341 +3 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:4 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:3 0.003616072 +4 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:4 0.0045 +5 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:3 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 0.0045 +6 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 sb_1__1_:top_left_grid_pin_37_[0] 0.0009330357 +7 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 1e-05 +8 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:6 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:5 0.007333929 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_41_lower[0] 0.001420752 //LENGTH 7.660 LUMPCC 0.0002118499 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_41_lower[0] O *L 0 *C 540.810 645.320 +*I sb_1__1_:top_left_grid_pin_41_[0] I *L 0 *C 548.470 645.320 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_41_lower[0] 0.0006044513 +1 sb_1__1_:top_left_grid_pin_41_[0] 0.0006044513 +2 grid_clb_1__2_:right_width_0_height_0__pin_41_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] 0.0001059249 +3 sb_1__1_:top_left_grid_pin_41_[0] sb_1__1_:left_top_grid_pin_43_[0] 0.0001059249 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_41_lower[0] sb_1__1_:top_left_grid_pin_41_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_42_lower[0] 0.001104373 //LENGTH 11.020 LUMPCC 0.0001316507 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] O *L 0 *C 788.440 380.870 +*I sb_2__0_:left_top_grid_pin_42_[0] I *L 0 *C 788.440 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] 0.0004863612 +1 sb_2__0_:left_top_grid_pin_42_[0] 0.0004863612 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] 4.085038e-05 +3 sb_2__0_:left_top_grid_pin_42_[0] sb_2__0_:left_top_grid_pin_45_[0] 4.085038e-05 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] 2.497497e-05 +5 sb_2__0_:left_top_grid_pin_42_[0] sb_2__0_:left_top_grid_pin_49_[0] 2.497497e-05 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] sb_2__0_:left_top_grid_pin_42_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_45_upper[0] 0.001252424 //LENGTH 11.020 LUMPCC 0.0005678821 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] O *L 0 *C 657.340 380.870 +*I sb_1__0_:right_top_grid_pin_45_[0] I *L 0 *C 657.340 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0003422708 +1 sb_1__0_:right_top_grid_pin_45_[0] 0.0003422708 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] 0.0001419705 +3 sb_1__0_:right_top_grid_pin_45_[0] sb_1__0_:right_top_grid_pin_42_[0] 0.0001419705 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] 0.0001419705 +5 sb_1__0_:right_top_grid_pin_45_[0] sb_1__0_:right_top_grid_pin_49_[0] 0.0001419705 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] sb_1__0_:right_top_grid_pin_45_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_49_lower[0] 0.001146005 //LENGTH 11.020 LUMPCC 0.0003491877 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] O *L 0 *C 791.660 380.870 +*I sb_2__0_:left_top_grid_pin_49_[0] I *L 0 *C 791.660 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] 0.0003984086 +1 sb_2__0_:left_top_grid_pin_49_[0] 0.0003984086 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] 2.497497e-05 +3 sb_2__0_:left_top_grid_pin_49_[0] sb_2__0_:left_top_grid_pin_42_[0] 2.497497e-05 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_48_lower[0] 0.0001496189 +5 sb_2__0_:left_top_grid_pin_49_[0] sb_2__0_:left_top_grid_pin_48_[0] 0.0001496189 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_49_lower[0] sb_2__0_:left_top_grid_pin_49_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_36_upper[0] 0.00114486 //LENGTH 7.660 LUMPCC 0.0005858687 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] O *L 0 *C 802.090 534.480 +*I sb_2__1_:bottom_left_grid_pin_36_[0] I *L 0 *C 809.750 534.480 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] 0.0002794956 +1 sb_2__1_:bottom_left_grid_pin_36_[0] 0.0002794956 +2 grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] 0.0001814562 +3 sb_2__1_:bottom_left_grid_pin_36_[0] sb_2__1_:bottom_left_grid_pin_35_[0] 0.0001814562 +4 grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] 0.0001114781 +5 sb_2__1_:bottom_left_grid_pin_36_[0] sb_2__1_:bottom_left_grid_pin_38_[0] 0.0001114781 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] sb_2__1_:bottom_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_39_upper[0] 0.001215802 //LENGTH 7.660 LUMPCC 0.0007068657 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] O *L 0 *C 802.090 539.240 +*I sb_2__1_:bottom_left_grid_pin_39_[0] I *L 0 *C 809.750 539.240 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] 0.0002544681 +1 sb_2__1_:bottom_left_grid_pin_39_[0] 0.0002544681 +2 grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] 0.0001767164 +3 sb_2__1_:bottom_left_grid_pin_39_[0] sb_2__1_:bottom_left_grid_pin_34_[0] 0.0001767164 +4 grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] 0.0001767164 +5 sb_2__1_:bottom_left_grid_pin_39_[0] sb_2__1_:bottom_left_grid_pin_40_[0] 0.0001767164 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] sb_2__1_:bottom_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_43_upper[0] 0.00104696 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_43_upper[0] O *L 0 *C 640.470 654.160 +*I sb_1__1_:right_top_grid_pin_43_[0] I *L 0 *C 632.810 654.160 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_43_upper[0] 0.0005234801 +1 sb_1__1_:right_top_grid_pin_43_[0] 0.0005234801 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_43_upper[0] sb_1__1_:right_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_45_lower[0] 0.001189031 //LENGTH 11.020 LUMPCC 0.0003592201 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] O *L 0 *C 786.140 641.990 +*I sb_2__1_:left_top_grid_pin_45_[0] I *L 0 *C 786.140 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] 0.0004149053 +1 sb_2__1_:left_top_grid_pin_45_[0] 0.0004149053 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] 3.994296e-05 +3 sb_2__1_:left_top_grid_pin_45_[0] sb_2__1_:left_top_grid_pin_42_[0] 3.994296e-05 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0001396671 +5 sb_2__1_:left_top_grid_pin_45_[0] sb_2__1_:left_top_grid_pin_44_[0] 0.0001396671 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] sb_2__1_:left_top_grid_pin_45_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_48_lower[0] 0.001163282 //LENGTH 11.020 LUMPCC 0.0002831015 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_48_lower[0] O *L 0 *C 792.580 641.990 +*I sb_2__1_:left_top_grid_pin_48_[0] I *L 0 *C 792.580 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_48_lower[0] 0.00044009 +1 sb_2__1_:left_top_grid_pin_48_[0] 0.00044009 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_48_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] 0.0001415508 +3 sb_2__1_:left_top_grid_pin_48_[0] sb_2__1_:left_top_grid_pin_49_[0] 0.0001415508 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_48_lower[0] sb_2__1_:left_top_grid_pin_48_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_34_upper[0] 0.001236664 //LENGTH 7.660 LUMPCC 0.0004987638 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] O *L 0 *C 802.090 799.000 +*I sb_2__2_:bottom_left_grid_pin_34_[0] I *L 0 *C 809.750 799.000 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] 0.0003689502 +1 sb_2__2_:bottom_left_grid_pin_34_[0] 0.0003689502 +2 grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] 8.998787e-05 +3 sb_2__2_:bottom_left_grid_pin_34_[0] sb_2__2_:bottom_left_grid_pin_35_[0] 8.998787e-05 +4 grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] 0.000159394 +5 sb_2__2_:bottom_left_grid_pin_34_[0] sb_2__2_:bottom_left_grid_pin_39_[0] 0.000159394 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] sb_2__2_:bottom_left_grid_pin_34_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_39_lower[0] 0.001212644 //LENGTH 7.660 LUMPCC 0.0007342546 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] O *L 0 *C 802.090 651.440 +*I sb_2__1_:top_left_grid_pin_39_[0] I *L 0 *C 809.750 651.440 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] 0.0002391949 +1 sb_2__1_:top_left_grid_pin_39_[0] 0.0002391949 +2 grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] 0.0001835637 +3 sb_2__1_:top_left_grid_pin_39_[0] sb_2__1_:top_left_grid_pin_38_[0] 0.0001835637 +4 grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] 0.0001835637 +5 sb_2__1_:top_left_grid_pin_39_[0] sb_2__1_:top_left_grid_pin_40_[0] 0.0001835637 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] sb_2__1_:top_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_41_upper[0] 0.002815804 //LENGTH 20.610 LUMPCC 0.0007760113 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] O *L 0 *C 802.090 790.840 +*I sb_2__2_:bottom_left_grid_pin_41_[0] I *L 0 *C 809.750 803.080 +*N grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 *C 805.940 803.080 +*N grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 *C 805.920 803.072 +*N grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 *C 805.920 790.848 +*N grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 *C 805.900 790.840 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] 0.000192355 +1 sb_2__2_:bottom_left_grid_pin_41_[0] 0.0002477595 +2 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 0.0002477595 +3 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 0.0005797817 +4 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 0.0005797817 +5 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 0.000192355 +6 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 Test_en[0]:20 0.000175375 +7 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 Test_en[0]:22 0.000175375 +8 grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] 8.977603e-05 +9 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 sb_2__2_:bottom_left_grid_pin_37_[0] 8.977603e-05 +10 sb_2__2_:bottom_left_grid_pin_41_[0] sb_2__2_:bottom_left_grid_pin_40_[0] 8.039849e-05 +11 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] 8.039849e-05 +12 grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] ctsbuf_net_312:8 9.71502e-06 +13 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 ctsbuf_net_312:10 3.274103e-05 +14 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 ctsbuf_net_312:7 9.71502e-06 +15 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 ctsbuf_net_312:9 3.274103e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 0.0005968999 +1 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 sb_2__2_:bottom_left_grid_pin_41_[0] 0.0005969 +2 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 0.00341 +3 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 0.00341 +4 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:4 grid_clb_3_right_width_0_height_0__pin_41_upper[0]:3 0.00191525 + +*END + +*D_NET grid_io_left_1_right_width_0_height_0__pin_1_upper[0] 0.003460703 //LENGTH 30.520 LUMPCC 0.0004855282 DR + +*CONN +*I grid_io_left_0__2_:right_width_0_height_0__pin_1_upper[0] O *L 0 *C 270.480 777.850 +*I sb_0__2_:bottom_left_grid_pin_1_[0] I *L 0 *C 289.340 788.870 +*N grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:2 *C 289.340 782.385 +*N grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 *C 289.295 782.340 +*N grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 *C 270.525 782.340 +*N grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:5 *C 270.480 782.295 + +*CAP +0 grid_io_left_0__2_:right_width_0_height_0__pin_1_upper[0] 0.0002703657 +1 sb_0__2_:bottom_left_grid_pin_1_[0] 0.0002876746 +2 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:2 0.0002876746 +3 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 0.0009295472 +4 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 0.0009295472 +5 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:5 0.0002703657 +6 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 ropt_net_39:6 0.0002427641 +7 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 ropt_net_39:5 0.0002427641 + +*RES +0 grid_io_left_0__2_:right_width_0_height_0__pin_1_upper[0] grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:5 0.00396875 +1 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:2 0.0045 +2 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:2 sb_0__2_:bottom_left_grid_pin_1_[0] 0.005790179 +3 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 0.01675893 +4 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:5 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 0.0045 + +*END + +*D_NET grid_io_right_1_left_width_0_height_0__pin_1_lower[0] 0.003503502 //LENGTH 31.960 LUMPCC 0.001576344 DR + +*CONN +*I grid_io_right_3__2_:left_width_0_height_0__pin_1_lower[0] O *L 0 *C 909.420 669.190 +*I sb_2__1_:top_right_grid_pin_1_[0] I *L 0 *C 889.180 658.170 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:2 *C 889.180 661.582 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 *C 889.188 661.640 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 *C 891.519 661.640 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 *C 891.520 661.640 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 *C 909.413 661.640 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 *C 909.420 661.697 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 *C 909.420 667.519 +*N grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:9 *C 909.420 667.520 + +*CAP +0 grid_io_right_3__2_:left_width_0_height_0__pin_1_lower[0] 0.0001228989 +1 sb_2__1_:top_right_grid_pin_1_[0] 0.0001770002 +2 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:2 0.0001770002 +3 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 7.424736e-05 +4 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 7.424736e-05 +5 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 0.0003558191 +6 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 0.0003558191 +7 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 0.0002336135 +8 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 0.0002336135 +9 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:9 0.0001228989 +10 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 grid_io_right_1_ccff_tail[0]:3 2.14717e-05 +11 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 grid_io_right_1_ccff_tail[0]:6 0.0001957717 +12 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 grid_io_right_1_ccff_tail[0]:5 0.0001957717 +13 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 grid_io_right_1_ccff_tail[0]:4 2.14717e-05 +14 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 ctsbuf_net_1221:12 5.965147e-05 +15 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 ctsbuf_net_1221:7 3.804012e-05 +16 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 ctsbuf_net_1221:8 0.0001602069 +17 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 ctsbuf_net_1221:9 0.0003130302 +18 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 ctsbuf_net_1221:6 3.804012e-05 +19 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 ctsbuf_net_1221:9 0.0001602069 +20 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 ctsbuf_net_1221:10 0.0003130302 +21 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 ctsbuf_net_1221:11 5.965147e-05 + +*RES +0 grid_io_right_3__2_:left_width_0_height_0__pin_1_lower[0] grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:9 0.001491072 +1 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:2 sb_2__1_:top_right_grid_pin_1_[0] 0.003046875 +2 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 0.00341 +4 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 0.002803158 +5 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:9 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 1e-05 +6 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 0.005197768 +7 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 1e-05 +8 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 0.0003652683 + +*END + +*D_NET sb_0__0__0_chanx_right_out[1] 0.001217876 //LENGTH 7.660 LUMPCC 0.0004569365 DR + +*CONN +*I sb_0__0_:chanx_right_out[1] O *L 0 *C 400.050 360.400 +*I cbx_1__0_:chanx_left_in[1] I *L 0 *C 407.710 360.400 + +*CAP +0 sb_0__0_:chanx_right_out[1] 0.0003804697 +1 cbx_1__0_:chanx_left_in[1] 0.0003804697 +2 sb_0__0_:chanx_right_out[1] sb_0__0_:chanx_right_in[17] 6.640785e-05 +3 cbx_1__0_:chanx_left_in[1] cbx_1__0_:chanx_left_out[17] 6.640785e-05 +4 sb_0__0_:chanx_right_out[1] sb_0__0_:chanx_right_out[3] 0.0001620604 +5 cbx_1__0_:chanx_left_in[1] cbx_1__0_:chanx_left_in[3] 0.0001620604 + +*RES +0 sb_0__0_:chanx_right_out[1] cbx_1__0_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[9] 0.001266155 //LENGTH 7.660 LUMPCC 0.0006903916 DR + +*CONN +*I sb_0__0_:chanx_right_out[9] O *L 0 *C 400.050 334.560 +*I cbx_1__0_:chanx_left_in[9] I *L 0 *C 407.710 334.560 + +*CAP +0 sb_0__0_:chanx_right_out[9] 0.0002878817 +1 cbx_1__0_:chanx_left_in[9] 0.0002878817 +2 sb_0__0_:chanx_right_out[9] sb_0__0_:chanx_right_in[15] 0.000172487 +3 cbx_1__0_:chanx_left_in[9] cbx_1__0_:chanx_left_out[15] 0.000172487 +4 sb_0__0_:chanx_right_out[9] sb_0__0_:chanx_right_out[15] 0.0001727088 +5 cbx_1__0_:chanx_left_in[9] cbx_1__0_:chanx_left_in[15] 0.0001727088 + +*RES +0 sb_0__0_:chanx_right_out[9] cbx_1__0_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[15] 0.001180449 //LENGTH 7.660 LUMPCC 0.0005043321 DR + +*CONN +*I sb_0__0_:chanx_right_out[15] O *L 0 *C 400.050 333.200 +*I cbx_1__0_:chanx_left_in[15] I *L 0 *C 407.710 333.200 + +*CAP +0 sb_0__0_:chanx_right_out[15] 0.0003380582 +1 cbx_1__0_:chanx_left_in[15] 0.0003380582 +2 sb_0__0_:chanx_right_out[15] sb_0__0_:chanx_right_out[9] 0.0001727088 +3 cbx_1__0_:chanx_left_in[15] cbx_1__0_:chanx_left_in[9] 0.0001727088 +4 sb_0__0_:chanx_right_out[15] sb_0__0_:chanx_right_out[16] 7.945725e-05 +5 cbx_1__0_:chanx_left_in[15] cbx_1__0_:chanx_left_in[16] 7.945725e-05 + +*RES +0 sb_0__0_:chanx_right_out[15] cbx_1__0_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[2] 0.001230984 //LENGTH 11.020 LUMPCC 0.0006017026 DR + +*CONN +*I sb_0__0_:chany_top_out[2] O *L 0 *C 358.340 397.050 +*I cby_0__1_:chany_bottom_in[2] I *L 0 *C 358.340 408.070 + +*CAP +0 sb_0__0_:chany_top_out[2] 0.0003146408 +1 cby_0__1_:chany_bottom_in[2] 0.0003146408 +2 sb_0__0_:chany_top_out[2] sb_0__0_:chany_top_in[2] 0.0001504257 +3 cby_0__1_:chany_bottom_in[2] cby_0__1_:chany_bottom_out[2] 0.0001504257 +4 sb_0__0_:chany_top_out[2] sb_0__0_:chany_top_in[12] 0.0001504257 +5 cby_0__1_:chany_bottom_in[2] cby_0__1_:chany_bottom_out[12] 0.0001504257 + +*RES +0 sb_0__0_:chany_top_out[2] cby_0__1_:chany_bottom_in[2] 0.009839285 + +*END + +*D_NET sb_0__0__0_chany_top_out[9] 0.001365849 //LENGTH 11.180 LUMPCC 0.0004356003 DR + +*CONN +*I sb_0__0_:chany_top_out[9] O *L 0 *C 296.240 396.970 +*I cby_0__1_:chany_bottom_in[9] I *L 0 *C 296.240 408.150 + +*CAP +0 sb_0__0_:chany_top_out[9] 0.0004651241 +1 cby_0__1_:chany_bottom_in[9] 0.0004651241 +2 sb_0__0_:chany_top_out[9] sb_0__0_:chany_top_out[14] 0.0002178002 +3 cby_0__1_:chany_bottom_in[9] cby_0__1_:chany_bottom_in[14] 0.0002178002 + +*RES +0 sb_0__0_:chany_top_out[9] cby_0__1_:chany_bottom_in[9] 0.001751533 + +*END + +*D_NET sb_0__0__0_chany_top_out[16] 0.001241233 //LENGTH 11.020 LUMPCC 0.0005926823 DR + +*CONN +*I sb_0__0_:chany_top_out[16] O *L 0 *C 335.340 397.050 +*I cby_0__1_:chany_bottom_in[16] I *L 0 *C 335.340 408.070 + +*CAP +0 sb_0__0_:chany_top_out[16] 0.0003242753 +1 cby_0__1_:chany_bottom_in[16] 0.0003242753 +2 sb_0__0_:chany_top_out[16] sb_0__0_:chany_top_in[19] 0.0001481706 +3 cby_0__1_:chany_bottom_in[16] cby_0__1_:chany_bottom_out[19] 0.0001481706 +4 sb_0__0_:chany_top_out[16] sb_0__0_:chany_top_out[3] 0.0001481706 +5 cby_0__1_:chany_bottom_in[16] cby_0__1_:chany_bottom_in[3] 0.0001481706 + +*RES +0 sb_0__0_:chany_top_out[16] cby_0__1_:chany_bottom_in[16] 0.009839285 + +*END + +*D_NET sb_0__1__0_chanx_right_out[1] 0.001184346 //LENGTH 7.660 LUMPCC 0.0004876767 DR + +*CONN +*I sb_0__1_:chanx_right_out[1] O *L 0 *C 400.050 610.640 +*I cbx_1__1_:chanx_left_in[1] I *L 0 *C 407.710 610.640 + +*CAP +0 sb_0__1_:chanx_right_out[1] 0.0003483346 +1 cbx_1__1_:chanx_left_in[1] 0.0003483346 +2 sb_0__1_:chanx_right_out[1] sb_0__1_:chanx_right_out[0] 0.0001722672 +3 cbx_1__1_:chanx_left_in[1] cbx_1__1_:chanx_left_in[0] 0.0001722672 +4 sb_0__1_:chanx_right_out[1] sb_0__1_:chanx_right_out[4] 7.15712e-05 +5 cbx_1__1_:chanx_left_in[1] cbx_1__1_:chanx_left_in[4] 7.15712e-05 + +*RES +0 sb_0__1_:chanx_right_out[1] cbx_1__1_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[8] 0.001266341 //LENGTH 7.660 LUMPCC 0.000687256 DR + +*CONN +*I sb_0__1_:chanx_right_out[8] O *L 0 *C 400.050 573.920 +*I cbx_1__1_:chanx_left_in[8] I *L 0 *C 407.710 573.920 + +*CAP +0 sb_0__1_:chanx_right_out[8] 0.0002895426 +1 cbx_1__1_:chanx_left_in[8] 0.0002895426 +2 sb_0__1_:chanx_right_out[8] sb_0__1_:chanx_right_in[8] 0.0001727402 +3 cbx_1__1_:chanx_left_in[8] cbx_1__1_:chanx_left_out[8] 0.0001727402 +4 sb_0__1_:chanx_right_out[8] sb_0__1_:chanx_right_out[14] 0.0001708878 +5 cbx_1__1_:chanx_left_in[8] cbx_1__1_:chanx_left_in[14] 0.0001708878 + +*RES +0 sb_0__1_:chanx_right_out[8] cbx_1__1_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[14] 0.001195779 //LENGTH 7.660 LUMPCC 0.0005689744 DR + +*CONN +*I sb_0__1_:chanx_right_out[14] O *L 0 *C 400.050 575.280 +*I cbx_1__1_:chanx_left_in[14] I *L 0 *C 407.710 575.280 + +*CAP +0 sb_0__1_:chanx_right_out[14] 0.0003134025 +1 cbx_1__1_:chanx_left_in[14] 0.0003134025 +2 sb_0__1_:chanx_right_out[14] sb_0__1_:chanx_right_in[0] 7.709654e-05 +3 cbx_1__1_:chanx_left_in[14] cbx_1__1__0_chanx_left_out[0]:2 7.709654e-05 +4 sb_0__1_:chanx_right_out[14] sb_0__1_:chanx_right_in[9] 3.650287e-05 +5 cbx_1__1_:chanx_left_in[14] cbx_1__1_:chanx_left_out[9] 3.650287e-05 +6 sb_0__1_:chanx_right_out[14] sb_0__1_:chanx_right_out[8] 0.0001708878 +7 cbx_1__1_:chanx_left_in[14] cbx_1__1_:chanx_left_in[8] 0.0001708878 + +*RES +0 sb_0__1_:chanx_right_out[14] cbx_1__1_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[3] 0.001293099 //LENGTH 11.020 LUMPCC 0.0005162829 DR + +*CONN +*I sb_0__1_:chany_bottom_out[3] O *L 0 *C 331.660 527.750 +*I cby_0__1_:chany_top_in[3] I *L 0 *C 331.660 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[3] 0.0003884081 +1 cby_0__1_:chany_top_in[3] 0.0003884081 +2 sb_0__1_:chany_bottom_out[3] sb_0__1_:chany_bottom_in[14] 0.0001296618 +3 cby_0__1_:chany_top_in[3] cby_0__1_:chany_top_out[14] 0.0001296618 +4 sb_0__1_:chany_bottom_out[3] sb_0__1_:chany_bottom_out[5] 0.0001284796 +5 cby_0__1_:chany_top_in[3] cby_0__1_:chany_top_in[5] 0.0001284796 + +*RES +0 sb_0__1_:chany_bottom_out[3] cby_0__1_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[9] 0.001288776 //LENGTH 11.020 LUMPCC 0.0005185666 DR + +*CONN +*I sb_0__1_:chany_bottom_out[9] O *L 0 *C 312.800 527.750 +*I cby_0__1_:chany_top_in[9] I *L 0 *C 312.800 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[9] 0.0003851046 +1 cby_0__1_:chany_top_in[9] 0.0003851046 +2 sb_0__1_:chany_bottom_out[9] sb_0__1_:chany_bottom_in[18] 0.0001296416 +3 cby_0__1_:chany_top_in[9] cby_0__1_:chany_top_out[18] 0.0001296416 +4 sb_0__1_:chany_bottom_out[9] sb_0__1_:chany_bottom_in[19] 0.0001296416 +5 cby_0__1_:chany_top_in[9] cby_0__1_:chany_top_out[19] 0.0001296416 + +*RES +0 sb_0__1_:chany_bottom_out[9] cby_0__1_:chany_top_in[9] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[17] 0.001293099 //LENGTH 11.020 LUMPCC 0.0005139186 DR + +*CONN +*I sb_0__1_:chany_bottom_out[17] O *L 0 *C 334.420 527.750 +*I cby_0__1_:chany_top_in[17] I *L 0 *C 334.420 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[17] 0.0003895902 +1 cby_0__1_:chany_top_in[17] 0.0003895902 +2 sb_0__1_:chany_bottom_out[17] sb_0__1_:chany_bottom_in[15] 0.0001284796 +3 cby_0__1_:chany_top_in[17] cby_0__1_:chany_top_out[15] 0.0001284796 +4 sb_0__1_:chany_bottom_out[17] sb_0__1_:chany_bottom_out[11] 0.0001284796 +5 cby_0__1_:chany_top_in[17] cby_0__1_:chany_top_in[11] 0.0001284796 + +*RES +0 sb_0__1_:chany_bottom_out[17] cby_0__1_:chany_top_in[17] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_top_out[3] 0.001253941 //LENGTH 11.020 LUMPCC 0.0005583286 DR + +*CONN +*I sb_0__1_:chany_top_out[3] O *L 0 *C 336.260 658.170 +*I cby_0__2_:chany_bottom_in[3] I *L 0 *C 336.260 669.190 +*N sb_0__1__0_chany_top_out[3]:2 *C 336.260 667.520 +*N sb_0__1__0_chany_top_out[3]:3 *C 336.260 667.519 + +*CAP +0 sb_0__1_:chany_top_out[3] 0.0002364105 +1 cby_0__2_:chany_bottom_in[3] 0.0001113958 +2 sb_0__1__0_chany_top_out[3]:2 0.0001113958 +3 sb_0__1__0_chany_top_out[3]:3 0.0002364105 +4 sb_0__1_:chany_top_out[3] sb_0__1_:chany_top_in[10] 0.0001340003 +5 cby_0__2_:chany_bottom_in[3] cby_0__2_:chany_bottom_out[10] 7.248536e-06 +6 sb_0__1__0_chany_top_out[3]:2 cby_0__1__1_chany_bottom_out[10]:3 7.248536e-06 +7 sb_0__1__0_chany_top_out[3]:3 cby_0__1__1_chany_bottom_out[10]:2 0.0001340003 +8 sb_0__1_:chany_top_out[3] sb_0__1_:chany_top_out[16] 0.0001307218 +9 cby_0__2_:chany_bottom_in[3] cby_0__2_:chany_bottom_in[16] 7.193657e-06 +10 sb_0__1__0_chany_top_out[3]:2 sb_0__1__0_chany_top_out[16]:2 7.193657e-06 +11 sb_0__1__0_chany_top_out[3]:3 sb_0__1__0_chany_top_out[16]:3 0.0001307218 + +*RES +0 sb_0__1_:chany_top_out[3] sb_0__1__0_chany_top_out[3]:3 0.008347321 +1 sb_0__1__0_chany_top_out[3]:2 cby_0__2_:chany_bottom_in[3] 0.001491072 +2 sb_0__1__0_chany_top_out[3]:3 sb_0__1__0_chany_top_out[3]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[12] 0.001293286 //LENGTH 12.500 LUMPCC 5.078827e-05 DR + +*CONN +*I sb_0__1_:chany_top_out[12] O *L 0 *C 294.400 658.170 +*I cby_0__2_:chany_bottom_in[12] I *L 0 *C 294.400 669.190 +*N sb_0__1__0_chany_top_out[12]:2 *C 294.400 667.520 +*N sb_0__1__0_chany_top_out[12]:3 *C 294.400 667.519 +*N sb_0__1__0_chany_top_out[12]:4 *C 294.400 666.400 +*N sb_0__1__0_chany_top_out[12]:5 *C 293.940 666.400 +*N sb_0__1__0_chany_top_out[12]:6 *C 293.940 663.680 +*N sb_0__1__0_chany_top_out[12]:7 *C 294.400 663.680 + +*CAP +0 sb_0__1_:chany_top_out[12] 0.0002415879 +1 cby_0__2_:chany_bottom_in[12] 0.0001262728 +2 sb_0__1__0_chany_top_out[12]:2 0.0001262728 +3 sb_0__1__0_chany_top_out[12]:3 6.552417e-05 +4 sb_0__1__0_chany_top_out[12]:4 9.333847e-05 +5 sb_0__1__0_chany_top_out[12]:5 0.0001620568 +6 sb_0__1__0_chany_top_out[12]:6 0.0001600498 +7 sb_0__1__0_chany_top_out[12]:7 0.0002673953 +8 sb_0__1_:chany_top_out[12] sb_0__1_:chany_top_out[14] 2.00682e-05 +9 sb_0__1__0_chany_top_out[12]:6 sb_0__1_:chany_top_out[14] 5.325931e-06 +10 sb_0__1__0_chany_top_out[12]:5 sb_0__1__0_chany_top_out[14]:3 5.325931e-06 +11 sb_0__1__0_chany_top_out[12]:7 sb_0__1__0_chany_top_out[14]:3 2.00682e-05 + +*RES +0 sb_0__1_:chany_top_out[12] sb_0__1__0_chany_top_out[12]:7 0.004919644 +1 sb_0__1__0_chany_top_out[12]:6 sb_0__1__0_chany_top_out[12]:5 0.002428572 +2 sb_0__1__0_chany_top_out[12]:5 sb_0__1__0_chany_top_out[12]:4 0.0004107143 +3 sb_0__1__0_chany_top_out[12]:7 sb_0__1__0_chany_top_out[12]:6 0.0004107143 +4 sb_0__1__0_chany_top_out[12]:4 sb_0__1__0_chany_top_out[12]:3 0.0009991071 +5 sb_0__1__0_chany_top_out[12]:2 cby_0__2_:chany_bottom_in[12] 0.001491071 +6 sb_0__1__0_chany_top_out[12]:3 sb_0__1__0_chany_top_out[12]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[18] 0.001689437 //LENGTH 11.180 LUMPCC 0.0008622952 DR + +*CONN +*I sb_0__1_:chany_top_out[18] O *L 0 *C 334.880 658.090 +*I cby_0__2_:chany_bottom_in[18] I *L 0 *C 334.880 669.270 +*N sb_0__1__0_chany_top_out[18]:2 *C 334.880 667.520 +*N sb_0__1__0_chany_top_out[18]:3 *C 334.880 667.519 + +*CAP +0 sb_0__1_:chany_top_out[18] 0.0001981499 +1 cby_0__2_:chany_bottom_in[18] 0.0002154209 +2 sb_0__1__0_chany_top_out[18]:2 0.0002154209 +3 sb_0__1__0_chany_top_out[18]:3 0.0001981499 +4 sb_0__1_:chany_top_out[18] sb_0__1_:chany_top_in[15] 0.0002065323 +5 cby_0__2_:chany_bottom_in[18] cby_0__2_:chany_bottom_out[15] 9.041499e-06 +6 sb_0__1__0_chany_top_out[18]:2 cby_0__1__1_chany_bottom_out[15]:3 9.041499e-06 +7 sb_0__1__0_chany_top_out[18]:3 cby_0__1__1_chany_bottom_out[15]:2 0.0002065323 +8 sb_0__1_:chany_top_out[18] sb_0__1_:chany_top_out[15] 0.0002065323 +9 cby_0__2_:chany_bottom_in[18] cby_0__2_:chany_bottom_in[15] 9.041499e-06 +10 sb_0__1__0_chany_top_out[18]:2 sb_0__1__0_chany_top_out[15]:2 9.041499e-06 +11 sb_0__1__0_chany_top_out[18]:3 sb_0__1__0_chany_top_out[15]:3 0.0002065323 + +*RES +0 sb_0__1_:chany_top_out[18] sb_0__1__0_chany_top_out[18]:3 0.00147721 +1 sb_0__1__0_chany_top_out[18]:2 cby_0__2_:chany_bottom_in[18] 0.0002741666 +2 sb_0__1__0_chany_top_out[18]:3 sb_0__1__0_chany_top_out[18]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[6] 0.001297939 //LENGTH 7.660 LUMPCC 0.0006569981 DR + +*CONN +*I sb_0__2_:chanx_right_out[6] O *L 0 *C 400.050 873.120 +*I cbx_1__2_:chanx_left_in[6] I *L 0 *C 407.710 873.120 + +*CAP +0 sb_0__2_:chanx_right_out[6] 0.0003204703 +1 cbx_1__2_:chanx_left_in[6] 0.0003204703 +2 sb_0__2_:chanx_right_out[6] sb_0__2_:chanx_right_out[3] 0.0001642495 +3 cbx_1__2_:chanx_left_in[6] cbx_1__2_:chanx_left_in[3] 0.0001642495 +4 sb_0__2_:chanx_right_out[6] sb_0__2_:chanx_right_out[8] 0.0001642495 +5 cbx_1__2_:chanx_left_in[6] cbx_1__2_:chanx_left_in[8] 0.0001642495 + +*RES +0 sb_0__2_:chanx_right_out[6] cbx_1__2_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[12] 0.001266837 //LENGTH 7.660 LUMPCC 0.0005948077 DR + +*CONN +*I sb_0__2_:chanx_right_out[12] O *L 0 *C 400.050 830.960 +*I cbx_1__2_:chanx_left_in[12] I *L 0 *C 407.710 830.960 + +*CAP +0 sb_0__2_:chanx_right_out[12] 0.0003360147 +1 cbx_1__2_:chanx_left_in[12] 0.0003360147 +2 sb_0__2_:chanx_right_out[12] sb_0__2_:chanx_right_in[14] 0.0001059899 +3 cbx_1__2_:chanx_left_in[12] cbx_1__2__0_chanx_left_out[14]:2 0.0001059899 +4 sb_0__2_:chanx_right_out[12] sb_0__2_:chanx_right_in[16] 0.000161918 +5 cbx_1__2_:chanx_left_in[12] cbx_1__2_:chanx_left_out[16] 0.000161918 +6 sb_0__2_:chanx_right_out[12] sb_0__2_:chanx_right_out[9] 2.949601e-05 +7 cbx_1__2_:chanx_left_in[12] cbx_1__2_:chanx_left_in[9] 2.949601e-05 + +*RES +0 sb_0__2_:chanx_right_out[12] cbx_1__2_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[1] 0.001109067 //LENGTH 11.020 LUMPCC 0.0001516071 DR + +*CONN +*I sb_0__2_:chany_bottom_out[1] O *L 0 *C 321.540 788.870 +*I cby_0__2_:chany_top_in[1] I *L 0 *C 321.540 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[1] 0.00047873 +1 cby_0__2_:chany_top_in[1] 0.00047873 +2 sb_0__2_:chany_bottom_out[1] sb_0__2_:chany_bottom_in[11] 1.922567e-05 +3 cby_0__2_:chany_top_in[1] cby_0__2_:chany_top_out[11] 1.922567e-05 +4 sb_0__2_:chany_bottom_out[1] sb_0__2_:prog_clk[0] 5.657789e-05 +5 cby_0__2_:chany_top_in[1] ctsbuf_net_1524:5 5.657789e-05 + +*RES +0 sb_0__2_:chany_bottom_out[1] cby_0__2_:chany_top_in[1] 0.009839285 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[8] 0.001258694 //LENGTH 11.020 LUMPCC 0.0005589473 DR + +*CONN +*I sb_0__2_:chany_bottom_out[8] O *L 0 *C 356.500 788.870 +*I cby_0__2_:chany_top_in[8] I *L 0 *C 356.500 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[8] 0.0003498734 +1 cby_0__2_:chany_top_in[8] 0.0003498734 +2 sb_0__2_:chany_bottom_out[8] sb_0__2_:chany_bottom_out[6] 0.0001397368 +3 cby_0__2_:chany_top_in[8] cby_0__2_:chany_top_in[6] 0.0001397368 +4 sb_0__2_:chany_bottom_out[8] sb_0__2_:chany_bottom_out[7] 0.0001397368 +5 cby_0__2_:chany_top_in[8] cby_0__2_:chany_top_in[7] 0.0001397368 + +*RES +0 sb_0__2_:chany_bottom_out[8] cby_0__2_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[13] 0.001522767 //LENGTH 11.180 LUMPCC 0.0004278983 DR + +*CONN +*I sb_0__2_:chany_bottom_out[13] O *L 0 *C 336.720 788.950 +*I cby_0__2_:chany_top_in[13] I *L 0 *C 336.720 777.770 + +*CAP +0 sb_0__2_:chany_bottom_out[13] 0.0005474343 +1 cby_0__2_:chany_top_in[13] 0.0005474343 +2 sb_0__2_:chany_bottom_out[13] sb_0__2_:chany_bottom_out[15] 0.0002139492 +3 cby_0__2_:chany_top_in[13] cby_0__2_:chany_top_in[15] 0.0002139492 + +*RES +0 sb_0__2_:chany_bottom_out[13] cby_0__2_:chany_top_in[13] 0.001751533 + +*END + +*D_NET sb_1__0__0_ccff_tail[0] 0.001383551 //LENGTH 7.660 LUMPCC 0.000465481 DR + +*CONN +*I sb_1__0_:ccff_tail[0] O *L 0 *C 519.950 349.520 +*I cbx_1__0_:ccff_head[0] I *L 0 *C 512.290 349.520 + +*CAP +0 sb_1__0_:ccff_tail[0] 0.000459035 +1 cbx_1__0_:ccff_head[0] 0.000459035 +2 sb_1__0_:ccff_tail[0] sb_1__0_:chanx_left_in[1] 0.0001494233 +3 cbx_1__0_:ccff_head[0] cbx_1__0_:chanx_right_out[1] 0.0001494233 +4 sb_1__0_:ccff_tail[0] sb_1__0_:chanx_left_in[10] 8.331719e-05 +5 cbx_1__0_:ccff_head[0] cbx_1__0__0_chanx_right_out[10]:2 8.331719e-05 + +*RES +0 sb_1__0_:ccff_tail[0] cbx_1__0_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[4] 0.001270593 //LENGTH 7.660 LUMPCC 0.0003602709 DR + +*CONN +*I sb_1__0_:chanx_left_out[4] O *L 0 *C 519.950 305.320 +*I cbx_1__0_:chanx_right_in[4] I *L 0 *C 512.290 305.320 + +*CAP +0 sb_1__0_:chanx_left_out[4] 0.0004551611 +1 cbx_1__0_:chanx_right_in[4] 0.0004551611 +2 sb_1__0_:chanx_left_out[4] sb_1__0_:chanx_left_out[2] 3.015819e-05 +3 cbx_1__0_:chanx_right_in[4] cbx_1__0_:chanx_right_in[2] 3.015819e-05 +4 sb_1__0_:chanx_left_out[4] sb_1__0_:chanx_left_out[18] 0.0001499772 +5 cbx_1__0_:chanx_right_in[4] cbx_1__0_:chanx_right_in[18] 0.0001499772 + +*RES +0 sb_1__0_:chanx_left_out[4] cbx_1__0_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[13] 0.001380507 //LENGTH 7.660 LUMPCC 0.0004036229 DR + +*CONN +*I sb_1__0_:chanx_left_out[13] O *L 0 *C 519.950 359.720 +*I cbx_1__0_:chanx_right_in[13] I *L 0 *C 512.290 359.720 + +*CAP +0 sb_1__0_:chanx_left_out[13] 0.0004884421 +1 cbx_1__0_:chanx_right_in[13] 0.0004884421 +2 sb_1__0_:chanx_left_out[13] sb_1__0_:chanx_left_in[0] 6.026256e-05 +3 cbx_1__0_:chanx_right_in[13] cbx_1__0__0_chanx_right_out[0]:2 6.026256e-05 +4 sb_1__0_:chanx_left_out[13] sb_1__0_:chanx_left_out[1] 0.0001415489 +5 cbx_1__0_:chanx_right_in[13] cbx_1__0_:chanx_right_in[1] 0.0001415489 + +*RES +0 sb_1__0_:chanx_left_out[13] cbx_1__0_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[19] 0.001378126 //LENGTH 7.660 LUMPCC 0.0004531915 DR + +*CONN +*I sb_1__0_:chanx_left_out[19] O *L 0 *C 519.950 352.240 +*I cbx_1__0_:chanx_right_in[19] I *L 0 *C 512.290 352.240 + +*CAP +0 sb_1__0_:chanx_left_out[19] 0.0004624671 +1 cbx_1__0_:chanx_right_in[19] 0.0004624671 +2 sb_1__0_:chanx_left_out[19] sb_1__0_:chanx_left_in[10] 8.416687e-05 +3 cbx_1__0_:chanx_right_in[19] cbx_1__0__0_chanx_right_out[10]:2 8.416687e-05 +4 sb_1__0_:chanx_left_out[19] sb_1__0_:chanx_left_out[3] 0.0001424289 +5 cbx_1__0_:chanx_right_in[19] cbx_1__0_:chanx_right_in[3] 0.0001424289 + +*RES +0 sb_1__0_:chanx_left_out[19] cbx_1__0_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[5] 0.001497576 //LENGTH 7.660 LUMPCC 0.0005069462 DR + +*CONN +*I sb_1__0_:chanx_right_out[5] O *L 0 *C 661.330 350.880 +*I cbx_2__0_:chanx_left_in[5] I *L 0 *C 668.990 350.880 +*N sb_1__0__0_chanx_right_out[5]:2 *C 667.520 350.880 +*N sb_1__0__0_chanx_right_out[5]:3 *C 667.519 350.880 + +*CAP +0 sb_1__0_:chanx_right_out[5] 0.0003003132 +1 cbx_2__0_:chanx_left_in[5] 0.0001950017 +2 sb_1__0__0_chanx_right_out[5]:2 0.0001950017 +3 sb_1__0__0_chanx_right_out[5]:3 0.0003003132 +4 sb_1__0_:chanx_right_out[5] sb_1__0_:chanx_right_in[19] 0.0001174568 +5 cbx_2__0_:chanx_left_in[5] cbx_2__0_:chanx_left_out[19] 9.865685e-06 +6 sb_1__0__0_chanx_right_out[5]:2 cbx_1__0__1_chanx_left_out[19]:3 9.865685e-06 +7 sb_1__0__0_chanx_right_out[5]:3 cbx_1__0__1_chanx_left_out[19]:2 0.0001174568 +8 sb_1__0_:chanx_right_out[5] sb_1__0_:chanx_right_out[11] 0.0001245063 +9 cbx_2__0_:chanx_left_in[5] cbx_2__0_:chanx_left_in[11] 1.644281e-06 +10 sb_1__0__0_chanx_right_out[5]:2 sb_1__0__0_chanx_right_out[11]:2 1.644281e-06 +11 sb_1__0__0_chanx_right_out[5]:3 sb_1__0__0_chanx_right_out[11]:3 0.0001245063 + +*RES +0 sb_1__0_:chanx_right_out[5] sb_1__0__0_chanx_right_out[5]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[5]:2 cbx_2__0_:chanx_left_in[5] 0.0002303 +2 sb_1__0__0_chanx_right_out[5]:3 sb_1__0__0_chanx_right_out[5]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[12] 0.001338956 //LENGTH 7.660 LUMPCC 0.0004084794 DR + +*CONN +*I sb_1__0_:chanx_right_out[12] O *L 0 *C 661.330 363.120 +*I cbx_2__0_:chanx_left_in[12] I *L 0 *C 668.990 363.120 +*N sb_1__0__0_chanx_right_out[12]:2 *C 667.520 363.120 +*N sb_1__0__0_chanx_right_out[12]:3 *C 667.519 363.120 + +*CAP +0 sb_1__0_:chanx_right_out[12] 0.0002781792 +1 cbx_2__0_:chanx_left_in[12] 0.0001870592 +2 sb_1__0__0_chanx_right_out[12]:2 0.0001870592 +3 sb_1__0__0_chanx_right_out[12]:3 0.0002781792 +4 sb_1__0_:chanx_right_out[12] sb_1__0_:chanx_right_in[9] 6.141703e-05 +5 sb_1__0__0_chanx_right_out[12]:3 cbx_1__0__1_chanx_left_out[9]:2 6.141703e-05 +6 sb_1__0_:chanx_right_out[12] sb_1__0_:chanx_right_out[3] 0.0001329559 +7 cbx_2__0_:chanx_left_in[12] cbx_2__0_:chanx_left_in[3] 9.866816e-06 +8 sb_1__0__0_chanx_right_out[12]:2 sb_1__0__0_chanx_right_out[3]:2 9.866816e-06 +9 sb_1__0__0_chanx_right_out[12]:3 sb_1__0__0_chanx_right_out[3]:3 0.0001329559 + +*RES +0 sb_1__0_:chanx_right_out[12] sb_1__0__0_chanx_right_out[12]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[12]:2 cbx_2__0_:chanx_left_in[12] 0.0002303 +2 sb_1__0__0_chanx_right_out[12]:3 sb_1__0__0_chanx_right_out[12]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[0] 0.001213397 //LENGTH 11.020 LUMPCC 0.0005956272 DR + +*CONN +*I sb_1__0_:chany_top_out[0] O *L 0 *C 596.620 397.050 +*I cby_1__1_:chany_bottom_in[0] I *L 0 *C 596.620 408.070 + +*CAP +0 sb_1__0_:chany_top_out[0] 0.0003088848 +1 cby_1__1_:chany_bottom_in[0] 0.0003088848 +2 sb_1__0_:chany_top_out[0] sb_1__0_:chany_top_in[11] 0.0001450212 +3 cby_1__1_:chany_bottom_in[0] cby_1__1_:chany_bottom_out[11] 0.0001450212 +4 sb_1__0_:chany_top_out[0] sb_1__0_:chany_top_out[2] 0.0001527924 +5 cby_1__1_:chany_bottom_in[0] cby_1__1_:chany_bottom_in[2] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[0] cby_1__1_:chany_bottom_in[0] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[7] 0.001430161 //LENGTH 12.500 LUMPCC 0.0004018203 DR + +*CONN +*I sb_1__0_:chany_top_out[7] O *L 0 *C 569.940 397.050 +*I cby_1__1_:chany_bottom_in[7] I *L 0 *C 569.940 408.070 +*N sb_1__0__0_chany_top_out[7]:2 *C 569.940 404.260 +*N sb_1__0__0_chany_top_out[7]:3 *C 570.400 404.260 +*N sb_1__0__0_chany_top_out[7]:4 *C 570.400 399.160 +*N sb_1__0__0_chany_top_out[7]:5 *C 569.940 399.160 + +*CAP +0 sb_1__0_:chany_top_out[7] 0.0001275987 +1 cby_1__1_:chany_bottom_in[7] 0.0001499433 +2 sb_1__0__0_chany_top_out[7]:2 0.0001729967 +3 sb_1__0__0_chany_top_out[7]:3 0.0002085656 +4 sb_1__0__0_chany_top_out[7]:4 0.0002135748 +5 sb_1__0__0_chany_top_out[7]:5 0.0001556613 +6 sb_1__0_:chany_top_out[7] sb_1__0_:chany_top_out[15] 1.267975e-05 +7 cby_1__1_:chany_bottom_in[7] cby_1__1_:chany_bottom_in[15] 4.409693e-05 +8 sb_1__0__0_chany_top_out[7]:5 cby_1__1_:chany_bottom_in[15] 1.267975e-05 +9 sb_1__0__0_chany_top_out[7]:4 sb_1__0_:chany_top_out[15] 0.0001441335 +10 sb_1__0__0_chany_top_out[7]:2 sb_1__0_:chany_top_out[15] 4.409693e-05 +11 sb_1__0__0_chany_top_out[7]:3 cby_1__1_:chany_bottom_in[15] 0.0001441335 + +*RES +0 sb_1__0_:chany_top_out[7] sb_1__0__0_chany_top_out[7]:5 0.001883929 +1 sb_1__0__0_chany_top_out[7]:5 sb_1__0__0_chany_top_out[7]:4 0.0004107142 +2 sb_1__0__0_chany_top_out[7]:4 sb_1__0__0_chany_top_out[7]:3 0.004553572 +3 sb_1__0__0_chany_top_out[7]:2 cby_1__1_:chany_bottom_in[7] 0.003401786 +4 sb_1__0__0_chany_top_out[7]:3 sb_1__0__0_chany_top_out[7]:2 0.0004107143 + +*END + +*D_NET sb_1__0__0_chany_top_out[15] 0.001325718 //LENGTH 11.020 LUMPCC 0.0006963483 DR + +*CONN +*I sb_1__0_:chany_top_out[15] O *L 0 *C 570.860 397.050 +*I cby_1__1_:chany_bottom_in[15] I *L 0 *C 570.860 408.070 + +*CAP +0 sb_1__0_:chany_top_out[15] 0.000314685 +1 cby_1__1_:chany_bottom_in[15] 0.000314685 +2 sb_1__0_:chany_top_out[15] sb_1__0_:chany_top_in[4] 0.000147264 +3 cby_1__1_:chany_bottom_in[15] cby_1__1_:chany_bottom_out[4] 0.000147264 +4 sb_1__0_:chany_top_out[15] sb_1__0_:chany_top_out[7] 1.267975e-05 +5 sb_1__0_:chany_top_out[15] sb_1__0__0_chany_top_out[7]:2 4.409693e-05 +6 sb_1__0_:chany_top_out[15] sb_1__0__0_chany_top_out[7]:4 0.0001441335 +7 cby_1__1_:chany_bottom_in[15] cby_1__1_:chany_bottom_in[7] 4.409693e-05 +8 cby_1__1_:chany_bottom_in[15] sb_1__0__0_chany_top_out[7]:3 0.0001441335 +9 cby_1__1_:chany_bottom_in[15] sb_1__0__0_chany_top_out[7]:5 1.267975e-05 + +*RES +0 sb_1__0_:chany_top_out[15] cby_1__1_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET sb_1__1__0_chanx_left_out[5] 0.00135115 //LENGTH 7.660 LUMPCC 0.0004239317 DR + +*CONN +*I sb_1__1_:chanx_left_out[5] O *L 0 *C 519.950 575.280 +*I cbx_1__1_:chanx_right_in[5] I *L 0 *C 512.290 575.280 + +*CAP +0 sb_1__1_:chanx_left_out[5] 0.0004636091 +1 cbx_1__1_:chanx_right_in[5] 0.0004636091 +2 sb_1__1_:chanx_left_out[5] sb_1__1_:chanx_left_in[19] 4.434828e-05 +3 cbx_1__1_:chanx_right_in[5] cbx_1__1__0_chanx_right_out[19]:2 4.434828e-05 +4 sb_1__1_:chanx_left_out[5] sb_1__1_:chanx_left_out[8] 0.0001448753 +5 cbx_1__1_:chanx_right_in[5] cbx_1__1_:chanx_right_in[8] 0.0001448753 +6 sb_1__1_:chanx_left_out[5] sb_1__1_:chanx_left_out[12] 2.274232e-05 +7 cbx_1__1_:chanx_right_in[5] cbx_1__1_:chanx_right_in[12] 2.274232e-05 + +*RES +0 sb_1__1_:chanx_left_out[5] cbx_1__1_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[13] 0.00128527 //LENGTH 7.660 LUMPCC 0.0002859649 DR + +*CONN +*I sb_1__1_:chanx_left_out[13] O *L 0 *C 519.950 626.960 +*I cbx_1__1_:chanx_right_in[13] I *L 0 *C 512.290 626.960 + +*CAP +0 sb_1__1_:chanx_left_out[13] 0.0004996526 +1 cbx_1__1_:chanx_right_in[13] 0.0004996526 +2 sb_1__1_:chanx_left_out[13] sb_1__1_:chanx_left_in[12] 0.0001429824 +3 cbx_1__1_:chanx_right_in[13] cbx_1__1_:chanx_right_out[12] 0.0001429824 + +*RES +0 sb_1__1_:chanx_left_out[13] cbx_1__1_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[18] 0.001366906 //LENGTH 7.660 LUMPCC 0.0005772144 DR + +*CONN +*I sb_1__1_:chanx_left_out[18] O *L 0 *C 519.950 598.400 +*I cbx_1__1_:chanx_right_in[18] I *L 0 *C 512.290 598.400 + +*CAP +0 sb_1__1_:chanx_left_out[18] 0.0003948456 +1 cbx_1__1_:chanx_right_in[18] 0.0003948456 +2 sb_1__1_:chanx_left_out[18] sb_1__1_:chanx_left_in[9] 0.0001447284 +3 cbx_1__1_:chanx_right_in[18] cbx_1__1_:chanx_right_out[9] 0.0001447284 +4 sb_1__1_:chanx_left_out[18] sb_1__1_:chanx_left_out[9] 0.0001438788 +5 cbx_1__1_:chanx_right_in[18] cbx_1__1_:chanx_right_in[9] 0.0001438788 + +*RES +0 sb_1__1_:chanx_left_out[18] cbx_1__1_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[6] 0.001486072 //LENGTH 7.660 LUMPCC 0.0003115369 DR + +*CONN +*I sb_1__1_:chanx_right_out[6] O *L 0 *C 661.330 586.160 +*I cbx_2__1_:chanx_left_in[6] I *L 0 *C 668.990 586.160 +*N sb_1__1__0_chanx_right_out[6]:2 *C 667.520 586.160 +*N sb_1__1__0_chanx_right_out[6]:3 *C 667.519 586.160 + +*CAP +0 sb_1__1_:chanx_right_out[6] 0.0003669105 +1 cbx_2__1_:chanx_left_in[6] 0.0002203569 +2 sb_1__1__0_chanx_right_out[6]:2 0.0002203569 +3 sb_1__1__0_chanx_right_out[6]:3 0.0003669105 +4 sb_1__1_:chanx_right_out[6] sb_1__1_:chanx_right_in[15] 0.0001132251 +5 sb_1__1__0_chanx_right_out[6]:3 cbx_1__1__1_chanx_left_out[15]:2 0.0001132251 +6 sb_1__1_:chanx_right_out[6] sb_1__1_:chanx_right_out[10] 4.254332e-05 +7 sb_1__1__0_chanx_right_out[6]:3 sb_1__1__0_chanx_right_out[10]:3 4.254332e-05 + +*RES +0 sb_1__1_:chanx_right_out[6] sb_1__1__0_chanx_right_out[6]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[6]:2 cbx_2__1_:chanx_left_in[6] 0.0002303 +2 sb_1__1__0_chanx_right_out[6]:3 sb_1__1__0_chanx_right_out[6]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[11] 0.001549005 //LENGTH 7.660 LUMPCC 0.0004404579 DR + +*CONN +*I sb_1__1_:chanx_right_out[11] O *L 0 *C 661.330 606.560 +*I cbx_2__1_:chanx_left_in[11] I *L 0 *C 668.990 606.560 +*N sb_1__1__0_chanx_right_out[11]:2 *C 667.520 606.560 +*N sb_1__1__0_chanx_right_out[11]:3 *C 667.519 606.560 + +*CAP +0 sb_1__1_:chanx_right_out[11] 0.0003366257 +1 cbx_2__1_:chanx_left_in[11] 0.0002176477 +2 sb_1__1__0_chanx_right_out[11]:2 0.0002176477 +3 sb_1__1__0_chanx_right_out[11]:3 0.0003366257 +4 sb_1__1_:chanx_right_out[11] sb_1__1_:chanx_right_in[6] 0.0001065295 +5 sb_1__1__0_chanx_right_out[11]:3 cbx_1__1__1_chanx_left_out[6]:2 0.0001065295 +6 sb_1__1_:chanx_right_out[11] sb_1__1_:chanx_right_out[4] 0.0001120554 +7 cbx_2__1_:chanx_left_in[11] cbx_2__1_:chanx_left_in[4] 1.644113e-06 +8 sb_1__1__0_chanx_right_out[11]:2 sb_1__1__0_chanx_right_out[4]:2 1.644113e-06 +9 sb_1__1__0_chanx_right_out[11]:3 sb_1__1__0_chanx_right_out[4]:3 0.0001120554 + +*RES +0 sb_1__1_:chanx_right_out[11] sb_1__1__0_chanx_right_out[11]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[11]:2 cbx_2__1_:chanx_left_in[11] 0.0002303 +2 sb_1__1__0_chanx_right_out[11]:3 sb_1__1__0_chanx_right_out[11]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[0] 0.001292694 //LENGTH 11.020 LUMPCC 0.0005025816 DR + +*CONN +*I sb_1__1_:chany_bottom_out[0] O *L 0 *C 603.060 527.750 +*I cby_1__1_:chany_top_in[0] I *L 0 *C 603.060 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[0] 0.0003950563 +1 cby_1__1_:chany_top_in[0] 0.0003950563 +2 sb_1__1_:chany_bottom_out[0] sb_1__1_:chany_bottom_in[0] 0.0001256454 +3 cby_1__1_:chany_top_in[0] cby_1__1_:chany_top_out[0] 0.0001256454 +4 sb_1__1_:chany_bottom_out[0] sb_1__1_:chany_bottom_in[9] 0.0001256454 +5 cby_1__1_:chany_top_in[0] cby_1__1_:chany_top_out[9] 0.0001256454 + +*RES +0 sb_1__1_:chany_bottom_out[0] cby_1__1_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[5] 0.001264048 //LENGTH 11.020 LUMPCC 0.0003914102 DR + +*CONN +*I sb_1__1_:chany_bottom_out[5] O *L 0 *C 591.560 527.750 +*I cby_1__1_:chany_top_in[5] I *L 0 *C 591.560 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[5] 0.0004363189 +1 cby_1__1_:chany_top_in[5] 0.0004363189 +2 sb_1__1_:chany_bottom_out[5] sb_1__1_:chany_bottom_out[18] 6.814997e-05 +3 cby_1__1_:chany_top_in[5] cby_1__1_:chany_top_in[18] 6.814997e-05 +4 sb_1__1_:chany_bottom_out[5] sb_1__1_:chany_bottom_out[19] 0.0001275551 +5 cby_1__1_:chany_top_in[5] cby_1__1_:chany_top_in[19] 0.0001275551 + +*RES +0 sb_1__1_:chany_bottom_out[5] cby_1__1_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[14] 0.001835411 //LENGTH 14.005 LUMPCC 0.0002869283 DR + +*CONN +*I sb_1__1_:chany_bottom_out[14] O *L 0 *C 617.320 527.750 +*I cby_1__1_:chany_top_in[14] I *L 0 *C 617.320 516.730 +*N sb_1__1__0_chany_bottom_out[14]:2 *C 616.920 517.480 +*N sb_1__1__0_chany_bottom_out[14]:3 *C 617.320 517.423 +*N sb_1__1__0_chany_bottom_out[14]:4 *C 617.320 517.480 +*N sb_1__1__0_chany_bottom_out[14]:5 *C 617.320 517.488 +*N sb_1__1__0_chany_bottom_out[14]:6 *C 617.320 520.533 +*N sb_1__1__0_chany_bottom_out[14]:7 *C 617.305 520.540 +*N sb_1__1__0_chany_bottom_out[14]:8 *C 616.863 520.540 +*N sb_1__1__0_chany_bottom_out[14]:9 *C 616.860 520.597 +*N sb_1__1__0_chany_bottom_out[14]:10 *C 616.860 522.240 +*N sb_1__1__0_chany_bottom_out[14]:11 *C 617.320 522.240 + +*CAP +0 sb_1__1_:chany_bottom_out[14] 0.0002618003 +1 cby_1__1_:chany_top_in[14] 5.622801e-05 +2 sb_1__1__0_chany_bottom_out[14]:2 6.924962e-05 +3 sb_1__1__0_chany_bottom_out[14]:3 5.622801e-05 +4 sb_1__1__0_chany_bottom_out[14]:4 6.924962e-05 +5 sb_1__1__0_chany_bottom_out[14]:5 0.0002540064 +6 sb_1__1__0_chany_bottom_out[14]:6 0.0002540064 +7 sb_1__1__0_chany_bottom_out[14]:7 3.551113e-05 +8 sb_1__1__0_chany_bottom_out[14]:8 3.551113e-05 +9 sb_1__1__0_chany_bottom_out[14]:9 7.138291e-05 +10 sb_1__1__0_chany_bottom_out[14]:10 9.744588e-05 +11 sb_1__1__0_chany_bottom_out[14]:11 0.0002878633 +12 sb_1__1__0_chany_bottom_out[14]:4 clk[0]:37 9.325306e-06 +13 sb_1__1__0_chany_bottom_out[14]:7 clk[0]:38 2.332518e-05 +14 sb_1__1__0_chany_bottom_out[14]:8 clk[0]:37 2.332518e-05 +15 sb_1__1__0_chany_bottom_out[14]:2 clk[0]:38 9.325306e-06 +16 sb_1__1_:chany_bottom_out[14] sb_1__1_:chany_bottom_out[4] 5.216231e-05 +17 cby_1__1_:chany_top_in[14] cby_1__1_:chany_top_in[4] 7.986142e-06 +18 sb_1__1__0_chany_bottom_out[14]:3 sb_1__1_:chany_bottom_out[4] 7.986142e-06 +19 sb_1__1__0_chany_bottom_out[14]:9 cby_1__1_:chany_top_in[4] 5.06652e-05 +20 sb_1__1__0_chany_bottom_out[14]:10 sb_1__1_:chany_bottom_out[4] 5.06652e-05 +21 sb_1__1__0_chany_bottom_out[14]:11 cby_1__1_:chany_top_in[4] 5.216231e-05 + +*RES +0 sb_1__1_:chany_bottom_out[14] sb_1__1__0_chany_bottom_out[14]:11 0.004919643 +1 sb_1__1__0_chany_bottom_out[14]:3 cby_1__1_:chany_top_in[14] 0.0006183035 +2 sb_1__1__0_chany_bottom_out[14]:4 sb_1__1__0_chany_bottom_out[14]:3 0.00341 +3 sb_1__1__0_chany_bottom_out[14]:4 sb_1__1__0_chany_bottom_out[14]:2 5.69697e-05 +4 sb_1__1__0_chany_bottom_out[14]:5 sb_1__1__0_chany_bottom_out[14]:4 0.00341 +5 sb_1__1__0_chany_bottom_out[14]:7 sb_1__1__0_chany_bottom_out[14]:6 0.00341 +6 sb_1__1__0_chany_bottom_out[14]:6 sb_1__1__0_chany_bottom_out[14]:5 0.00047705 +7 sb_1__1__0_chany_bottom_out[14]:9 sb_1__1__0_chany_bottom_out[14]:8 0.00341 +8 sb_1__1__0_chany_bottom_out[14]:8 sb_1__1__0_chany_bottom_out[14]:7 6.499219e-05 +9 sb_1__1__0_chany_bottom_out[14]:10 sb_1__1__0_chany_bottom_out[14]:9 0.001466518 +10 sb_1__1__0_chany_bottom_out[14]:11 sb_1__1__0_chany_bottom_out[14]:10 0.0004107143 + +*END + +*D_NET sb_1__1__0_chany_top_out[5] 0.001199282 //LENGTH 11.020 LUMPCC 0.0004782986 DR + +*CONN +*I sb_1__1_:chany_top_out[5] O *L 0 *C 603.520 658.170 +*I cby_1__2_:chany_bottom_in[5] I *L 0 *C 603.520 669.190 +*N sb_1__1__0_chany_top_out[5]:2 *C 603.520 667.520 +*N sb_1__1__0_chany_top_out[5]:3 *C 603.520 667.519 + +*CAP +0 sb_1__1_:chany_top_out[5] 0.0002434932 +1 cby_1__2_:chany_bottom_in[5] 0.0001169987 +2 sb_1__1__0_chany_top_out[5]:2 0.0001169987 +3 sb_1__1__0_chany_top_out[5]:3 0.0002434932 +4 sb_1__1_:chany_top_out[5] sb_1__1_:chany_top_in[2] 9.231795e-05 +5 cby_1__2_:chany_bottom_in[5] cby_1__2_:chany_bottom_out[2] 1.486125e-06 +6 sb_1__1__0_chany_top_out[5]:2 cby_1__1__1_chany_bottom_out[2]:3 1.486125e-06 +7 sb_1__1__0_chany_top_out[5]:3 cby_1__1__1_chany_bottom_out[2]:2 9.231795e-05 +8 sb_1__1_:chany_top_out[5] sb_1__1_:chany_top_in[18] 0.0001380049 +9 cby_1__2_:chany_bottom_in[5] cby_1__2_:chany_bottom_out[18] 7.340369e-06 +10 sb_1__1__0_chany_top_out[5]:2 cby_1__1__1_chany_bottom_out[18]:3 7.340369e-06 +11 sb_1__1__0_chany_top_out[5]:3 cby_1__1__1_chany_bottom_out[18]:2 0.0001380049 + +*RES +0 sb_1__1_:chany_top_out[5] sb_1__1__0_chany_top_out[5]:3 0.008347322 +1 sb_1__1__0_chany_top_out[5]:2 cby_1__2_:chany_bottom_in[5] 0.001491072 +2 sb_1__1__0_chany_top_out[5]:3 sb_1__1__0_chany_top_out[5]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[11] 0.001086537 //LENGTH 11.020 LUMPCC 0.0001356114 DR + +*CONN +*I sb_1__1_:chany_top_out[11] O *L 0 *C 613.640 658.170 +*I cby_1__2_:chany_bottom_in[11] I *L 0 *C 613.640 669.190 +*N sb_1__1__0_chany_top_out[11]:2 *C 613.640 667.520 +*N sb_1__1__0_chany_top_out[11]:3 *C 613.640 667.519 + +*CAP +0 sb_1__1_:chany_top_out[11] 0.0003486885 +1 cby_1__2_:chany_bottom_in[11] 0.0001267742 +2 sb_1__1__0_chany_top_out[11]:2 0.0001267742 +3 sb_1__1__0_chany_top_out[11]:3 0.0003486885 +4 sb_1__1_:chany_top_out[11] sb_1__1_:chany_top_out[18] 6.780568e-05 +5 sb_1__1__0_chany_top_out[11]:3 sb_1__1__0_chany_top_out[18]:3 6.780568e-05 + +*RES +0 sb_1__1_:chany_top_out[11] sb_1__1__0_chany_top_out[11]:3 0.008347322 +1 sb_1__1__0_chany_top_out[11]:2 cby_1__2_:chany_bottom_in[11] 0.001491072 +2 sb_1__1__0_chany_top_out[11]:3 sb_1__1__0_chany_top_out[11]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[18] 0.001157876 //LENGTH 11.020 LUMPCC 0.0004367657 DR + +*CONN +*I sb_1__1_:chany_top_out[18] O *L 0 *C 615.480 658.170 +*I cby_1__2_:chany_bottom_in[18] I *L 0 *C 615.480 669.190 +*N sb_1__1__0_chany_top_out[18]:2 *C 615.480 667.520 +*N sb_1__1__0_chany_top_out[18]:3 *C 615.480 667.519 + +*CAP +0 sb_1__1_:chany_top_out[18] 0.0002417581 +1 cby_1__2_:chany_bottom_in[18] 0.0001187971 +2 sb_1__1__0_chany_top_out[18]:2 0.0001187971 +3 sb_1__1__0_chany_top_out[18]:3 0.0002417581 +4 sb_1__1_:chany_top_out[18] sb_1__1_:chany_top_out[10] 0.0001431353 +5 cby_1__2_:chany_bottom_in[18] cby_1__2_:chany_bottom_in[10] 7.441891e-06 +6 sb_1__1__0_chany_top_out[18]:2 sb_1__1__0_chany_top_out[10]:2 7.441891e-06 +7 sb_1__1__0_chany_top_out[18]:3 sb_1__1__0_chany_top_out[10]:3 0.0001431353 +8 sb_1__1_:chany_top_out[18] sb_1__1_:chany_top_out[11] 6.780568e-05 +9 sb_1__1__0_chany_top_out[18]:3 sb_1__1__0_chany_top_out[11]:3 6.780568e-05 + +*RES +0 sb_1__1_:chany_top_out[18] sb_1__1__0_chany_top_out[18]:3 0.008347322 +1 sb_1__1__0_chany_top_out[18]:2 cby_1__2_:chany_bottom_in[18] 0.001491072 +2 sb_1__1__0_chany_top_out[18]:3 sb_1__1__0_chany_top_out[18]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[3] 0.001358747 //LENGTH 7.660 LUMPCC 0.0005896685 DR + +*CONN +*I sb_1__2_:chanx_left_out[3] O *L 0 *C 519.950 837.760 +*I cbx_1__2_:chanx_right_in[3] I *L 0 *C 512.290 837.760 + +*CAP +0 sb_1__2_:chanx_left_out[3] 0.0003845393 +1 cbx_1__2_:chanx_right_in[3] 0.0003845393 +2 sb_1__2_:chanx_left_out[3] sb_1__2_:chanx_left_in[4] 0.0001489726 +3 cbx_1__2_:chanx_right_in[3] cbx_1__2_:chanx_right_out[4] 0.0001489726 +4 sb_1__2_:chanx_left_out[3] sb_1__2_:chanx_left_out[7] 0.0001458617 +5 cbx_1__2_:chanx_right_in[3] cbx_1__2_:chanx_right_in[7] 0.0001458617 + +*RES +0 sb_1__2_:chanx_left_out[3] cbx_1__2_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[10] 0.001393474 //LENGTH 7.660 LUMPCC 0.0005648875 DR + +*CONN +*I sb_1__2_:chanx_left_out[10] O *L 0 *C 519.950 886.720 +*I cbx_1__2_:chanx_right_in[10] I *L 0 *C 512.290 886.720 + +*CAP +0 sb_1__2_:chanx_left_out[10] 0.000414293 +1 cbx_1__2_:chanx_right_in[10] 0.000414293 +2 sb_1__2_:chanx_left_out[10] sb_1__2_:chanx_left_in[9] 0.0001407971 +3 cbx_1__2_:chanx_right_in[10] cbx_1__2_:chanx_right_out[9] 0.0001407971 +4 sb_1__2_:chanx_left_out[10] sb_1__2_:chanx_left_in[15] 0.0001416467 +5 cbx_1__2_:chanx_right_in[10] cbx_1__2_:chanx_right_out[15] 0.0001416467 + +*RES +0 sb_1__2_:chanx_left_out[10] cbx_1__2_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[18] 0.001357552 //LENGTH 7.660 LUMPCC 0.0005133158 DR + +*CONN +*I sb_1__2_:chanx_left_out[18] O *L 0 *C 519.950 855.440 +*I cbx_1__2_:chanx_right_in[18] I *L 0 *C 512.290 855.440 + +*CAP +0 sb_1__2_:chanx_left_out[18] 0.0004221181 +1 cbx_1__2_:chanx_right_in[18] 0.0004221181 +2 sb_1__2_:chanx_left_out[18] sb_1__2_:chanx_left_in[2] 0.0001078059 +3 cbx_1__2_:chanx_right_in[18] cbx_1__2__0_chanx_right_out[2]:2 0.0001078059 +4 sb_1__2_:chanx_left_out[18] sb_1__2_:chanx_left_out[9] 0.000148852 +5 cbx_1__2_:chanx_right_in[18] cbx_1__2_:chanx_right_in[9] 0.000148852 + +*RES +0 sb_1__2_:chanx_left_out[18] cbx_1__2_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[6] 0.001506936 //LENGTH 7.660 LUMPCC 0.000493101 DR + +*CONN +*I sb_1__2_:chanx_right_out[6] O *L 0 *C 661.330 873.120 +*I cbx_2__2_:chanx_left_in[6] I *L 0 *C 668.990 873.120 +*N sb_1__2__0_chanx_right_out[6]:2 *C 667.520 873.120 +*N sb_1__2__0_chanx_right_out[6]:3 *C 667.519 873.120 + +*CAP +0 sb_1__2_:chanx_right_out[6] 0.000289296 +1 cbx_2__2_:chanx_left_in[6] 0.0002176217 +2 sb_1__2__0_chanx_right_out[6]:2 0.0002176217 +3 sb_1__2__0_chanx_right_out[6]:3 0.000289296 +4 sb_1__2_:chanx_right_out[6] sb_1__2_:chanx_right_out[3] 0.0001197279 +5 sb_1__2__0_chanx_right_out[6]:3 sb_1__2__0_chanx_right_out[3]:3 0.0001197279 +6 sb_1__2_:chanx_right_out[6] sb_1__2_:chanx_right_out[8] 0.000125179 +7 cbx_2__2_:chanx_left_in[6] cbx_2__2_:chanx_left_in[8] 1.643599e-06 +8 sb_1__2__0_chanx_right_out[6]:2 sb_1__2__0_chanx_right_out[8]:2 1.643599e-06 +9 sb_1__2__0_chanx_right_out[6]:3 sb_1__2__0_chanx_right_out[8]:3 0.000125179 + +*RES +0 sb_1__2_:chanx_right_out[6] sb_1__2__0_chanx_right_out[6]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[6]:2 cbx_2__2_:chanx_left_in[6] 0.0002303 +2 sb_1__2__0_chanx_right_out[6]:3 sb_1__2__0_chanx_right_out[6]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[12] 0.001466512 //LENGTH 7.660 LUMPCC 0.0003693218 DR + +*CONN +*I sb_1__2_:chanx_right_out[12] O *L 0 *C 661.330 830.960 +*I cbx_2__2_:chanx_left_in[12] I *L 0 *C 668.990 830.960 +*N sb_1__2__0_chanx_right_out[12]:2 *C 667.520 830.960 +*N sb_1__2__0_chanx_right_out[12]:3 *C 667.519 830.960 + +*CAP +0 sb_1__2_:chanx_right_out[12] 0.0003479577 +1 cbx_2__2_:chanx_left_in[12] 0.0002006373 +2 sb_1__2__0_chanx_right_out[12]:2 0.0002006373 +3 sb_1__2__0_chanx_right_out[12]:3 0.0003479577 +4 sb_1__2_:chanx_right_out[12] sb_1__2_:chanx_right_in[14] 5.75082e-05 +5 sb_1__2__0_chanx_right_out[12]:3 cbx_1__2__1_chanx_left_out[14]:2 5.75082e-05 +6 sb_1__2_:chanx_right_out[12] sb_1__2_:chanx_right_in[16] 0.0001205785 +7 cbx_2__2_:chanx_left_in[12] cbx_2__2_:chanx_left_out[16] 6.574196e-06 +8 sb_1__2__0_chanx_right_out[12]:2 cbx_1__2__1_chanx_left_out[16]:3 6.574196e-06 +9 sb_1__2__0_chanx_right_out[12]:3 cbx_1__2__1_chanx_left_out[16]:2 0.0001205785 + +*RES +0 sb_1__2_:chanx_right_out[12] sb_1__2__0_chanx_right_out[12]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[12]:2 cbx_2__2_:chanx_left_in[12] 0.0002303 +2 sb_1__2__0_chanx_right_out[12]:3 sb_1__2__0_chanx_right_out[12]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[0] 0.001275997 //LENGTH 11.020 LUMPCC 0.0005247784 DR + +*CONN +*I sb_1__2_:chany_bottom_out[0] O *L 0 *C 603.060 788.870 +*I cby_1__2_:chany_top_in[0] I *L 0 *C 603.060 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[0] 0.0003756092 +1 cby_1__2_:chany_top_in[0] 0.0003756092 +2 sb_1__2_:chany_bottom_out[0] sb_1__2_:chany_bottom_in[0] 0.0001311946 +3 cby_1__2_:chany_top_in[0] cby_1__2_:chany_top_out[0] 0.0001311946 +4 sb_1__2_:chany_bottom_out[0] sb_1__2_:chany_bottom_in[9] 0.0001311946 +5 cby_1__2_:chany_top_in[0] cby_1__2_:chany_top_out[9] 0.0001311946 + +*RES +0 sb_1__2_:chany_bottom_out[0] cby_1__2_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[6] 0.001280263 //LENGTH 11.020 LUMPCC 0.0005183863 DR + +*CONN +*I sb_1__2_:chany_bottom_out[6] O *L 0 *C 594.780 788.870 +*I cby_1__2_:chany_top_in[6] I *L 0 *C 594.780 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[6] 0.0003809386 +1 cby_1__2_:chany_top_in[6] 0.0003809386 +2 sb_1__2_:chany_bottom_out[6] sb_1__2_:chany_bottom_in[5] 0.0001295966 +3 cby_1__2_:chany_top_in[6] cby_1__2_:chany_top_out[5] 0.0001295966 +4 sb_1__2_:chany_bottom_out[6] sb_1__2_:chany_bottom_out[11] 0.0001295966 +5 cby_1__2_:chany_top_in[6] cby_1__2_:chany_top_in[11] 0.0001295966 + +*RES +0 sb_1__2_:chany_bottom_out[6] cby_1__2_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[16] 0.001274636 //LENGTH 11.020 LUMPCC 0.0005263244 DR + +*CONN +*I sb_1__2_:chany_bottom_out[16] O *L 0 *C 584.200 788.870 +*I cby_1__2_:chany_top_in[16] I *L 0 *C 584.200 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[16] 0.0003741559 +1 cby_1__2_:chany_top_in[16] 0.0003741559 +2 sb_1__2_:chany_bottom_out[16] sb_1__2_:chany_bottom_in[4] 0.0001315811 +3 cby_1__2_:chany_top_in[16] cby_1__2_:chany_top_out[4] 0.0001315811 +4 sb_1__2_:chany_bottom_out[16] sb_1__2_:chany_bottom_out[8] 0.0001315811 +5 cby_1__2_:chany_top_in[16] cby_1__2_:chany_top_in[8] 0.0001315811 + +*RES +0 sb_1__2_:chany_bottom_out[16] cby_1__2_:chany_top_in[16] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[2] 0.00127093 //LENGTH 7.660 LUMPCC 0.0002376325 DR + +*CONN +*I sb_2__0_:chanx_left_out[2] O *L 0 *C 781.230 309.400 +*I cbx_2__0_:chanx_right_in[2] I *L 0 *C 773.570 309.400 + +*CAP +0 sb_2__0_:chanx_left_out[2] 0.0005166486 +1 cbx_2__0_:chanx_right_in[2] 0.0005166486 +2 sb_2__0_:chanx_left_out[2] sb_2__0_:chanx_left_out[4] 3.660679e-05 +3 cbx_2__0_:chanx_right_in[2] cbx_2__0_:chanx_right_in[4] 3.660679e-05 +4 sb_2__0_:chanx_left_out[2] sb_2__0_:chanx_left_out[14] 8.220947e-05 +5 cbx_2__0_:chanx_right_in[2] cbx_2__0_:chanx_right_in[14] 8.220947e-05 + +*RES +0 sb_2__0_:chanx_left_out[2] cbx_2__0_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[7] 0.001439584 //LENGTH 7.660 LUMPCC 0.0005497893 DR + +*CONN +*I sb_2__0_:chanx_left_out[7] O *L 0 *C 781.230 342.720 +*I cbx_2__0_:chanx_right_in[7] I *L 0 *C 773.570 342.720 + +*CAP +0 sb_2__0_:chanx_left_out[7] 0.0004448973 +1 cbx_2__0_:chanx_right_in[7] 0.0004448973 +2 sb_2__0_:chanx_left_out[7] sb_2__0_:chanx_left_in[5] 0.000145506 +3 cbx_2__0_:chanx_right_in[7] cbx_2__0_:chanx_right_out[5] 0.000145506 +4 sb_2__0_:chanx_left_out[7] sb_2__0_:chanx_left_in[6] 0.0001293887 +5 cbx_2__0_:chanx_right_in[7] cbx_2__0_:chanx_right_out[6] 0.0001293887 + +*RES +0 sb_2__0_:chanx_left_out[7] cbx_2__0_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[16] 0.00134104 //LENGTH 7.660 LUMPCC 0.0003971698 DR + +*CONN +*I sb_2__0_:chanx_left_out[16] O *L 0 *C 781.230 325.040 +*I cbx_2__0_:chanx_right_in[16] I *L 0 *C 773.570 325.040 + +*CAP +0 sb_2__0_:chanx_left_out[16] 0.000471935 +1 cbx_2__0_:chanx_right_in[16] 0.000471935 +2 sb_2__0_:chanx_left_out[16] sb_2__0_:chanx_left_in[8] 0.0001361759 +3 cbx_2__0_:chanx_right_in[16] cbx_2__0_:chanx_right_out[8] 0.0001361759 +4 sb_2__0_:chanx_left_out[16] sb_2__0_:chanx_left_in[16] 6.240896e-05 +5 cbx_2__0_:chanx_right_in[16] cbx_2__0_:chanx_right_out[16] 6.240896e-05 + +*RES +0 sb_2__0_:chanx_left_out[16] cbx_2__0_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[4] 0.0011117 //LENGTH 11.020 LUMPCC 0.0001816951 DR + +*CONN +*I sb_2__0_:chany_top_out[4] O *L 0 *C 879.980 397.050 +*I cby_2__1_:chany_bottom_in[4] I *L 0 *C 879.980 408.070 + +*CAP +0 sb_2__0_:chany_top_out[4] 0.0004650022 +1 cby_2__1_:chany_bottom_in[4] 0.0004650022 +2 sb_2__0_:chany_top_out[4] sb_2__0_:chany_top_out[14] 9.084754e-05 +3 cby_2__1_:chany_bottom_in[4] cby_2__1_:chany_bottom_in[14] 9.084754e-05 + +*RES +0 sb_2__0_:chany_top_out[4] cby_2__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET sb_2__0__0_chany_top_out[9] 0.001231586 //LENGTH 11.020 LUMPCC 0.0005884135 DR + +*CONN +*I sb_2__0_:chany_top_out[9] O *L 0 *C 839.500 397.050 +*I cby_2__1_:chany_bottom_in[9] I *L 0 *C 839.500 408.070 + +*CAP +0 sb_2__0_:chany_top_out[9] 0.0003215864 +1 cby_2__1_:chany_bottom_in[9] 0.0003215864 +2 sb_2__0_:chany_top_out[9] sb_2__0_:chany_top_in[1] 0.0001471034 +3 cby_2__1_:chany_bottom_in[9] cby_2__1_:chany_bottom_out[1] 0.0001471034 +4 sb_2__0_:chany_top_out[9] sb_2__0_:chany_top_in[19] 0.0001471034 +5 cby_2__1_:chany_bottom_in[9] cby_2__1_:chany_bottom_out[19] 0.0001471034 + +*RES +0 sb_2__0_:chany_top_out[9] cby_2__1_:chany_bottom_in[9] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[17] 0.001170019 //LENGTH 11.020 LUMPCC 0.0005017929 DR + +*CONN +*I sb_2__0_:chany_top_out[17] O *L 0 *C 843.180 397.050 +*I cby_2__1_:chany_bottom_in[17] I *L 0 *C 843.180 408.070 + +*CAP +0 sb_2__0_:chany_top_out[17] 0.0003341131 +1 cby_2__1_:chany_bottom_in[17] 0.0003341131 +2 sb_2__0_:chany_top_out[17] sb_2__0_:chany_top_in[13] 9.82392e-05 +3 cby_2__1_:chany_bottom_in[17] cby_2__1_:chany_bottom_out[13] 9.82392e-05 +4 sb_2__0_:chany_top_out[17] sb_2__0_:chany_top_out[1] 0.0001526573 +5 cby_2__1_:chany_bottom_in[17] cby_2__1_:chany_bottom_in[1] 0.0001526573 + +*RES +0 sb_2__0_:chany_top_out[17] cby_2__1_:chany_bottom_in[17] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[2] 0.001439072 //LENGTH 7.660 LUMPCC 0.0003212674 DR + +*CONN +*I sb_2__1_:chanx_left_out[2] O *L 0 *C 781.230 610.640 +*I cbx_2__1_:chanx_right_in[2] I *L 0 *C 773.570 610.640 + +*CAP +0 sb_2__1_:chanx_left_out[2] 0.0005589025 +1 cbx_2__1_:chanx_right_in[2] 0.0005589025 +2 sb_2__1_:chanx_left_out[2] sb_2__1_:chanx_left_in[4] 3.946064e-05 +3 cbx_2__1_:chanx_right_in[2] cbx_2__1_:chanx_right_out[4] 3.946064e-05 +4 sb_2__1_:chanx_left_out[2] sb_2__1_:chanx_left_out[1] 0.0001211731 +5 cbx_2__1_:chanx_right_in[2] cbx_2__1_:chanx_right_in[1] 0.0001211731 + +*RES +0 sb_2__1_:chanx_left_out[2] cbx_2__1_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[10] 0.001419783 //LENGTH 7.660 LUMPCC 0.0003716191 DR + +*CONN +*I sb_2__1_:chanx_left_out[10] O *L 0 *C 781.230 580.720 +*I cbx_2__1_:chanx_right_in[10] I *L 0 *C 773.570 580.720 + +*CAP +0 sb_2__1_:chanx_left_out[10] 0.0005240822 +1 cbx_2__1_:chanx_right_in[10] 0.0005240822 +2 sb_2__1_:chanx_left_out[10] sb_2__1_:chanx_left_in[16] 2.585295e-05 +3 cbx_2__1_:chanx_right_in[10] cbx_1__1__1_chanx_right_out[16]:2 2.585295e-05 +4 sb_2__1_:chanx_left_out[10] sb_2__1_:chanx_left_out[6] 3.631858e-05 +5 cbx_2__1_:chanx_right_in[10] cbx_2__1_:chanx_right_in[6] 3.631858e-05 +6 sb_2__1_:chanx_left_out[10] sb_2__1_:chanx_left_out[14] 0.000123638 +7 cbx_2__1_:chanx_right_in[10] cbx_2__1_:chanx_right_in[14] 0.000123638 + +*RES +0 sb_2__1_:chanx_left_out[10] cbx_2__1_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[19] 0.0014767 //LENGTH 7.660 LUMPCC 0.0002873785 DR + +*CONN +*I sb_2__1_:chanx_left_out[19] O *L 0 *C 781.230 618.800 +*I cbx_2__1_:chanx_right_in[19] I *L 0 *C 773.570 618.800 + +*CAP +0 sb_2__1_:chanx_left_out[19] 0.0005946609 +1 cbx_2__1_:chanx_right_in[19] 0.0005946609 +2 sb_2__1_:chanx_left_out[19] sb_2__1_:chanx_left_in[14] 0.00010498 +3 cbx_2__1_:chanx_right_in[19] cbx_2__1_:chanx_right_out[14] 0.00010498 +4 sb_2__1_:chanx_left_out[19] sb_2__1_:chanx_left_out[17] 3.870922e-05 +5 cbx_2__1_:chanx_right_in[19] cbx_2__1_:chanx_right_in[17] 3.870922e-05 + +*RES +0 sb_2__1_:chanx_left_out[19] cbx_2__1_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[5] 0.001245397 //LENGTH 11.020 LUMPCC 0.0004193347 DR + +*CONN +*I sb_2__1_:chany_bottom_out[5] O *L 0 *C 852.840 527.750 +*I cby_2__1_:chany_top_in[5] I *L 0 *C 852.840 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[5] 0.0004130311 +1 cby_2__1_:chany_top_in[5] 0.0004130311 +2 sb_2__1_:chany_bottom_out[5] sb_2__1_:chany_bottom_out[18] 7.581322e-05 +3 cby_2__1_:chany_top_in[5] cby_2__1_:chany_top_in[18] 7.581322e-05 +4 sb_2__1_:chany_bottom_out[5] sb_2__1_:chany_bottom_out[19] 0.0001338541 +5 cby_2__1_:chany_top_in[5] cby_2__1_:chany_top_in[19] 0.0001338541 + +*RES +0 sb_2__1_:chany_bottom_out[5] cby_2__1_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[15] 0.001218097 //LENGTH 11.020 LUMPCC 0.0003207036 DR + +*CONN +*I sb_2__1_:chany_bottom_out[15] O *L 0 *C 836.280 527.750 +*I cby_2__1_:chany_top_in[15] I *L 0 *C 836.280 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[15] 0.0004486964 +1 cby_2__1_:chany_top_in[15] 0.0004486964 +2 sb_2__1_:chany_bottom_out[15] sb_2__1_:chany_bottom_in[18] 2.737794e-05 +3 cby_2__1_:chany_top_in[15] cby_2__1_:chany_top_out[18] 2.737794e-05 +4 sb_2__1_:chany_bottom_out[15] sb_2__1_:chany_bottom_out[9] 0.0001329739 +5 cby_2__1_:chany_top_in[15] cby_2__1_:chany_top_in[9] 0.0001329739 + +*RES +0 sb_2__1_:chany_bottom_out[15] cby_2__1_:chany_top_in[15] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[3] 0.001258107 //LENGTH 11.020 LUMPCC 0.0005567565 DR + +*CONN +*I sb_2__1_:chany_top_out[3] O *L 0 *C 852.380 658.170 +*I cby_2__2_:chany_bottom_in[3] I *L 0 *C 852.380 669.190 +*N sb_2__1__0_chany_top_out[3]:2 *C 852.380 667.520 +*N sb_2__1__0_chany_top_out[3]:3 *C 852.380 667.519 + +*CAP +0 sb_2__1_:chany_top_out[3] 0.0002397372 +1 cby_2__2_:chany_bottom_in[3] 0.0001109382 +2 sb_2__1__0_chany_top_out[3]:2 0.0001109382 +3 sb_2__1__0_chany_top_out[3]:3 0.0002397372 +4 sb_2__1_:chany_top_out[3] sb_2__1_:chany_top_in[8] 0.0001318429 +5 cby_2__2_:chany_bottom_in[3] cby_2__2_:chany_bottom_out[8] 7.346249e-06 +6 sb_2__1__0_chany_top_out[3]:2 cby_1__1__3_chany_bottom_out[8]:3 7.346249e-06 +7 sb_2__1__0_chany_top_out[3]:3 cby_1__1__3_chany_bottom_out[8]:2 0.0001318429 +8 sb_2__1_:chany_top_out[3] sb_2__1_:chany_top_out[6] 0.0001318429 +9 cby_2__2_:chany_bottom_in[3] cby_2__2_:chany_bottom_in[6] 7.346249e-06 +10 sb_2__1__0_chany_top_out[3]:2 sb_2__1__0_chany_top_out[6]:2 7.346249e-06 +11 sb_2__1__0_chany_top_out[3]:3 sb_2__1__0_chany_top_out[6]:3 0.0001318429 + +*RES +0 sb_2__1_:chany_top_out[3] sb_2__1__0_chany_top_out[3]:3 0.008347321 +1 sb_2__1__0_chany_top_out[3]:2 cby_2__2_:chany_bottom_in[3] 0.001491072 +2 sb_2__1__0_chany_top_out[3]:3 sb_2__1__0_chany_top_out[3]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[11] 0.00110501 //LENGTH 11.020 LUMPCC 0.0001224192 DR + +*CONN +*I sb_2__1_:chany_top_out[11] O *L 0 *C 874.920 658.170 +*I cby_2__2_:chany_bottom_in[11] I *L 0 *C 874.920 669.190 +*N sb_2__1__0_chany_top_out[11]:2 *C 874.920 667.520 +*N sb_2__1__0_chany_top_out[11]:3 *C 874.920 667.519 + +*CAP +0 sb_2__1_:chany_top_out[11] 0.0003646287 +1 cby_2__2_:chany_bottom_in[11] 0.0001266665 +2 sb_2__1__0_chany_top_out[11]:2 0.0001266665 +3 sb_2__1__0_chany_top_out[11]:3 0.0003646287 +4 sb_2__1_:chany_top_out[11] sb_2__1_:chany_top_out[18] 6.120958e-05 +5 sb_2__1__0_chany_top_out[11]:3 sb_2__1__0_chany_top_out[18]:3 6.120958e-05 + +*RES +0 sb_2__1_:chany_top_out[11] sb_2__1__0_chany_top_out[11]:3 0.008347322 +1 sb_2__1__0_chany_top_out[11]:2 cby_2__2_:chany_bottom_in[11] 0.001491072 +2 sb_2__1__0_chany_top_out[11]:3 sb_2__1__0_chany_top_out[11]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[16] 0.001090829 //LENGTH 11.020 LUMPCC 8.903442e-05 DR + +*CONN +*I sb_2__1_:chany_top_out[16] O *L 0 *C 868.020 658.170 +*I cby_2__2_:chany_bottom_in[16] I *L 0 *C 868.020 669.190 +*N sb_2__1__0_chany_top_out[16]:2 *C 868.020 667.520 +*N sb_2__1__0_chany_top_out[16]:3 *C 868.020 667.519 + +*CAP +0 sb_2__1_:chany_top_out[16] 0.0003754833 +1 cby_2__2_:chany_bottom_in[16] 0.0001254142 +2 sb_2__1__0_chany_top_out[16]:2 0.0001254142 +3 sb_2__1__0_chany_top_out[16]:3 0.0003754833 +4 sb_2__1_:chany_top_out[16] sb_2__1_:chany_top_in[18] 4.451721e-05 +5 sb_2__1__0_chany_top_out[16]:3 cby_1__1__3_chany_bottom_out[18]:2 4.451721e-05 + +*RES +0 sb_2__1_:chany_top_out[16] sb_2__1__0_chany_top_out[16]:3 0.008347322 +1 sb_2__1__0_chany_top_out[16]:2 cby_2__2_:chany_bottom_in[16] 0.001491072 +2 sb_2__1__0_chany_top_out[16]:3 sb_2__1__0_chany_top_out[16]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[2] 0.001433511 //LENGTH 7.660 LUMPCC 0.0003503701 DR + +*CONN +*I sb_2__2_:chanx_left_out[2] O *L 0 *C 781.230 822.800 +*I cbx_2__2_:chanx_right_in[2] I *L 0 *C 773.570 822.800 + +*CAP +0 sb_2__2_:chanx_left_out[2] 0.0005415704 +1 cbx_2__2_:chanx_right_in[2] 0.0005415704 +2 sb_2__2_:chanx_left_out[2] sb_2__2_:chanx_left_in[10] 5.902442e-05 +3 cbx_2__2_:chanx_right_in[2] cbx_2__2_:chanx_right_out[10] 5.902442e-05 +4 sb_2__2_:chanx_left_out[2] sb_2__2_:chanx_left_in[12] 0.0001161606 +5 cbx_2__2_:chanx_right_in[2] cbx_2__2_:chanx_right_out[12] 0.0001161606 + +*RES +0 sb_2__2_:chanx_left_out[2] cbx_2__2_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[8] 0.001361096 //LENGTH 7.660 LUMPCC 0.0004087753 DR + +*CONN +*I sb_2__2_:chanx_left_out[8] O *L 0 *C 781.230 874.480 +*I cbx_2__2_:chanx_right_in[8] I *L 0 *C 773.570 874.480 + +*CAP +0 sb_2__2_:chanx_left_out[8] 0.0004761603 +1 cbx_2__2_:chanx_right_in[8] 0.0004761603 +2 sb_2__2_:chanx_left_out[8] sb_2__2_:chanx_left_out[12] 5.985417e-05 +3 cbx_2__2_:chanx_right_in[8] cbx_2__2_:chanx_right_in[12] 5.985417e-05 +4 sb_2__2_:chanx_left_out[8] sb_2__2_:chanx_left_out[13] 0.0001445335 +5 cbx_2__2_:chanx_right_in[8] cbx_2__2_:chanx_right_in[13] 0.0001445335 + +*RES +0 sb_2__2_:chanx_left_out[8] cbx_2__2_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[17] 0.00144044 //LENGTH 7.660 LUMPCC 0.0003591949 DR + +*CONN +*I sb_2__2_:chanx_left_out[17] O *L 0 *C 781.230 879.920 +*I cbx_2__2_:chanx_right_in[17] I *L 0 *C 773.570 879.920 + +*CAP +0 sb_2__2_:chanx_left_out[17] 0.0005406224 +1 cbx_2__2_:chanx_right_in[17] 0.0005406224 +2 sb_2__2_:chanx_left_out[17] sb_2__2_:chanx_left_out[11] 0.000116313 +3 cbx_2__2_:chanx_right_in[17] cbx_2__2_:chanx_right_in[11] 0.000116313 +4 sb_2__2_:chanx_left_out[17] sb_2__2_:chanx_left_out[19] 6.32845e-05 +5 cbx_2__2_:chanx_right_in[17] cbx_2__2_:chanx_right_in[19] 6.32845e-05 + +*RES +0 sb_2__2_:chanx_left_out[17] cbx_2__2_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[4] 0.001172096 //LENGTH 11.020 LUMPCC 0.0003884984 DR + +*CONN +*I sb_2__2_:chany_bottom_out[4] O *L 0 *C 877.680 788.870 +*I cby_2__2_:chany_top_in[4] I *L 0 *C 877.680 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[4] 0.0003917987 +1 cby_2__2_:chany_top_in[4] 0.0003917987 +2 sb_2__2_:chany_bottom_out[4] sb_2__2_:chany_bottom_in[6] 5.026654e-05 +3 cby_2__2_:chany_top_in[4] cby_2__2_:chany_top_out[6] 5.026654e-05 +4 sb_2__2_:chany_bottom_out[4] sb_2__2_:chany_bottom_out[14] 0.0001439826 +5 cby_2__2_:chany_top_in[4] cby_2__2_:chany_top_in[14] 0.0001439826 + +*RES +0 sb_2__2_:chany_bottom_out[4] cby_2__2_:chany_top_in[4] 0.009839285 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[13] 0.001236644 //LENGTH 11.020 LUMPCC 0.000576671 DR + +*CONN +*I sb_2__2_:chany_bottom_out[13] O *L 0 *C 842.720 788.870 +*I cby_2__2_:chany_top_in[13] I *L 0 *C 842.720 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[13] 0.0003299866 +1 cby_2__2_:chany_top_in[13] 0.0003299866 +2 sb_2__2_:chany_bottom_out[13] sb_2__2_:chany_bottom_in[10] 0.0001469158 +3 cby_2__2_:chany_top_in[13] cby_2__2_:chany_top_out[10] 0.0001469158 +4 sb_2__2_:chany_bottom_out[13] sb_2__2_:chany_bottom_out[7] 0.0001414197 +5 cby_2__2_:chany_top_in[13] cby_2__2_:chany_top_in[7] 0.0001414197 + +*RES +0 sb_2__2_:chany_bottom_out[13] cby_2__2_:chany_top_in[13] 0.009839286 + +*END + +*D_NET ropt_net_32 0.0009382431 //LENGTH 8.825 LUMPCC 8.61046e-05 DR + +*CONN +*I ropt_h_inst_7750:X O *L 0 *C 287.735 520.540 +*I ropt_h_inst_7751:A I *L 0.001746 *C 282.900 523.600 +*N ropt_net_32:2 *C 282.938 523.600 +*N ropt_net_32:3 *C 285.155 523.600 +*N ropt_net_32:4 *C 285.200 523.555 +*N ropt_net_32:5 *C 285.200 520.585 +*N ropt_net_32:6 *C 285.245 520.540 +*N ropt_net_32:7 *C 287.697 520.540 + +*CAP +0 ropt_h_inst_7750:X 1e-06 +1 ropt_h_inst_7751:A 1e-06 +2 ropt_net_32:2 0.0001324994 +3 ropt_net_32:3 0.0001324994 +4 ropt_net_32:4 0.0001567841 +5 ropt_net_32:5 0.0001567841 +6 ropt_net_32:6 0.0001357858 +7 ropt_net_32:7 0.0001357858 +8 ropt_net_32:6 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 4.30523e-05 +9 ropt_net_32:7 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 4.30523e-05 + +*RES +0 ropt_h_inst_7750:X ropt_net_32:7 0.152 +1 ropt_net_32:2 ropt_h_inst_7751:A 0.152 +2 ropt_net_32:3 ropt_net_32:2 0.001979911 +3 ropt_net_32:4 ropt_net_32:3 0.0045 +4 ropt_net_32:6 ropt_net_32:5 0.0045 +5 ropt_net_32:5 ropt_net_32:4 0.002651786 +6 ropt_net_32:7 ropt_net_32:6 0.002189732 + +*END + +*D_NET ctsbuf_net_514 0.06723882 //LENGTH 658.785 LUMPCC 0.003336527 DR + +*CONN +*I cts_inv_73547629:Y O *L 0 *C 276.920 641.240 +*I grid_io_top_2__3_:prog_clk[0] I *L 0 *C 668.990 906.440 +*N ctsbuf_net_514:2 *C 667.520 906.440 +*N ctsbuf_net_514:3 *C 667.519 906.440 +*N ctsbuf_net_514:4 *C 663.195 906.440 +*N ctsbuf_net_514:5 *C 613.195 906.440 +*N ctsbuf_net_514:6 *C 563.195 906.440 +*N ctsbuf_net_514:7 *C 513.368 906.440 +*N ctsbuf_net_514:8 *C 513.360 906.383 +*N ctsbuf_net_514:9 *C 513.360 893.577 +*N ctsbuf_net_514:10 *C 513.353 893.520 +*N ctsbuf_net_514:11 *C 481.815 893.520 +*N ctsbuf_net_514:12 *C 443.520 893.520 +*N ctsbuf_net_514:13 *C 443.519 893.520 +*N ctsbuf_net_514:14 *C 431.815 893.520 +*N ctsbuf_net_514:15 *C 381.815 893.520 +*N ctsbuf_net_514:16 *C 331.815 893.520 +*N ctsbuf_net_514:17 *C 281.988 893.520 +*N ctsbuf_net_514:18 *C 281.980 893.463 +*N ctsbuf_net_514:19 *C 281.980 891.520 +*N ctsbuf_net_514:20 *C 281.980 891.519 +*N ctsbuf_net_514:21 *C 281.980 841.080 +*N ctsbuf_net_514:22 *C 281.980 791.080 +*N ctsbuf_net_514:23 *C 281.980 741.080 +*N ctsbuf_net_514:24 *C 281.980 691.080 +*N ctsbuf_net_514:25 *C 281.980 667.520 +*N ctsbuf_net_514:26 *C 281.980 667.519 +*N ctsbuf_net_514:27 *C 281.980 641.285 +*N ctsbuf_net_514:28 *C 281.935 641.240 +*N ctsbuf_net_514:29 *C 276.958 641.240 + +*CAP +0 cts_inv_73547629:Y 1e-06 +1 grid_io_top_2__3_:prog_clk[0] 0.0002161195 +2 ctsbuf_net_514:2 0.0002161195 +3 ctsbuf_net_514:3 0.0001504329 +4 ctsbuf_net_514:4 0.00250676 +5 ctsbuf_net_514:5 0.004783689 +6 ctsbuf_net_514:6 0.00486286 +7 ctsbuf_net_514:7 0.002435498 +8 ctsbuf_net_514:8 0.0006455552 +9 ctsbuf_net_514:9 0.0006455552 +10 ctsbuf_net_514:10 0.001750685 +11 ctsbuf_net_514:11 0.00397198 +12 ctsbuf_net_514:12 0.002221296 +13 ctsbuf_net_514:13 0.0006833436 +14 ctsbuf_net_514:14 0.00354177 +15 ctsbuf_net_514:15 0.005724539 +16 ctsbuf_net_514:16 0.005688917 +17 ctsbuf_net_514:17 0.002822805 +18 ctsbuf_net_514:18 0.000103334 +19 ctsbuf_net_514:19 0.000103334 +20 ctsbuf_net_514:20 0.002240824 +21 ctsbuf_net_514:21 0.004476156 +22 ctsbuf_net_514:22 0.004163543 +23 ctsbuf_net_514:23 0.003801132 +24 ctsbuf_net_514:24 0.002735128 +25 ctsbuf_net_514:25 0.0008622081 +26 ctsbuf_net_514:26 0.0009603548 +27 ctsbuf_net_514:27 0.0009603548 +28 ctsbuf_net_514:28 0.0003135015 +29 ctsbuf_net_514:29 0.0003135015 +30 ctsbuf_net_514:15 sb_0__2_:chanx_right_in[2] 2.578827e-05 +31 ctsbuf_net_514:14 cbx_1__2_:chanx_left_out[2] 2.578827e-05 +32 ctsbuf_net_514:10 cbx_1__2__0_chanx_right_out[2]:7 0.0001968898 +33 ctsbuf_net_514:11 cbx_1__2__0_chanx_right_out[2]:8 0.0001968898 +34 ctsbuf_net_514:23 grid_io_left_1_ccff_tail[0]:5 2.605602e-05 +35 ctsbuf_net_514:23 grid_io_left_1_ccff_tail[0]:9 8.521618e-05 +36 ctsbuf_net_514:22 grid_io_left_1_ccff_tail[0]:4 2.605602e-05 +37 ctsbuf_net_514:22 grid_io_left_1_ccff_tail[0]:8 8.521618e-05 +38 ctsbuf_net_514:5 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 4.218768e-05 +39 ctsbuf_net_514:4 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 4.739757e-05 +40 ctsbuf_net_514:4 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 4.218768e-05 +41 ctsbuf_net_514:3 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 4.739757e-05 +42 ctsbuf_net_514:27 ctsbuf_net_1524:21 0.0003792233 +43 ctsbuf_net_514:24 ctsbuf_net_1524:13 0.0002296201 +44 ctsbuf_net_514:24 ctsbuf_net_1524:16 7.622104e-05 +45 ctsbuf_net_514:24 ctsbuf_net_1524:12 0.0002802022 +46 ctsbuf_net_514:23 ctsbuf_net_1524:12 0.0004526802 +47 ctsbuf_net_514:23 ctsbuf_net_1524:11 0.0001965266 +48 ctsbuf_net_514:22 ctsbuf_net_1524:10 5.640123e-05 +49 ctsbuf_net_514:22 ctsbuf_net_1524:11 0.0002230601 +50 ctsbuf_net_514:25 ctsbuf_net_1524:13 0.0001400768 +51 ctsbuf_net_514:25 ctsbuf_net_1524:17 7.622104e-05 +52 ctsbuf_net_514:26 ctsbuf_net_1524:18 0.0003792233 + +*RES +0 cts_inv_73547629:Y ctsbuf_net_514:29 0.152 +1 ctsbuf_net_514:8 ctsbuf_net_514:7 0.00341 +2 ctsbuf_net_514:7 ctsbuf_net_514:6 0.007806308 +3 ctsbuf_net_514:9 ctsbuf_net_514:8 0.01143304 +4 ctsbuf_net_514:10 ctsbuf_net_514:9 0.00341 +5 ctsbuf_net_514:18 ctsbuf_net_514:17 0.00341 +6 ctsbuf_net_514:17 ctsbuf_net_514:16 0.007806308 +7 ctsbuf_net_514:28 ctsbuf_net_514:27 0.0045 +8 ctsbuf_net_514:27 ctsbuf_net_514:26 0.02342322 +9 ctsbuf_net_514:29 ctsbuf_net_514:28 0.004444197 +10 ctsbuf_net_514:24 ctsbuf_net_514:23 0.04464286 +11 ctsbuf_net_514:23 ctsbuf_net_514:22 0.04464286 +12 ctsbuf_net_514:22 ctsbuf_net_514:21 0.04464286 +13 ctsbuf_net_514:21 ctsbuf_net_514:20 0.04503483 +14 ctsbuf_net_514:16 ctsbuf_net_514:15 0.007833333 +15 ctsbuf_net_514:15 ctsbuf_net_514:14 0.007833333 +16 ctsbuf_net_514:14 ctsbuf_net_514:13 0.001833627 +17 ctsbuf_net_514:11 ctsbuf_net_514:10 0.004940875 +18 ctsbuf_net_514:6 ctsbuf_net_514:5 0.007833333 +19 ctsbuf_net_514:5 ctsbuf_net_514:4 0.007833333 +20 ctsbuf_net_514:4 ctsbuf_net_514:3 0.0006774266 +21 ctsbuf_net_514:19 ctsbuf_net_514:18 0.001734375 +22 ctsbuf_net_514:20 ctsbuf_net_514:19 1e-05 +23 ctsbuf_net_514:2 grid_io_top_2__3_:prog_clk[0] 0.0002303 +24 ctsbuf_net_514:3 ctsbuf_net_514:2 1e-05 +25 ctsbuf_net_514:25 ctsbuf_net_514:24 0.02103572 +26 ctsbuf_net_514:26 ctsbuf_net_514:25 1e-05 +27 ctsbuf_net_514:12 ctsbuf_net_514:11 0.00599955 +28 ctsbuf_net_514:13 ctsbuf_net_514:12 1e-05 + +*END + +*D_NET ctsbuf_net_1827 0.002871017 //LENGTH 24.405 LUMPCC 0.00036758 DR + +*CONN +*I cts_inv_73677642:Y O *L 0 *C 372.600 544.680 +*I grid_clb_1__1_:prog_clk[0] I *L 0 *C 379.190 527.680 +*N ctsbuf_net_1827:2 *C 378.127 527.680 +*N ctsbuf_net_1827:3 *C 378.120 527.738 +*N ctsbuf_net_1827:4 *C 378.120 544.635 +*N ctsbuf_net_1827:5 *C 378.075 544.680 +*N ctsbuf_net_1827:6 *C 372.638 544.680 + +*CAP +0 cts_inv_73677642:Y 1e-06 +1 grid_clb_1__1_:prog_clk[0] 0.0001374388 +2 ctsbuf_net_1827:2 0.0001374388 +3 ctsbuf_net_1827:3 0.0007915873 +4 ctsbuf_net_1827:4 0.0007915873 +5 ctsbuf_net_1827:5 0.0003221922 +6 ctsbuf_net_1827:6 0.0003221922 +7 ctsbuf_net_1827:6 ctsbuf_net_1928:40 2.896962e-06 +8 ctsbuf_net_1827:6 ctsbuf_net_1928:42 4.342113e-05 +9 ctsbuf_net_1827:5 ctsbuf_net_1928:43 4.342113e-05 +10 ctsbuf_net_1827:5 ctsbuf_net_1928:41 2.896962e-06 +11 ctsbuf_net_1827:4 ctsbuf_net_2029:46 0.0001374719 +12 ctsbuf_net_1827:3 ctsbuf_net_2029:47 0.0001374719 + +*RES +0 cts_inv_73677642:Y ctsbuf_net_1827:6 0.152 +1 ctsbuf_net_1827:6 ctsbuf_net_1827:5 0.004854911 +2 ctsbuf_net_1827:5 ctsbuf_net_1827:4 0.0045 +3 ctsbuf_net_1827:4 ctsbuf_net_1827:3 0.01508706 +4 ctsbuf_net_1827:3 ctsbuf_net_1827:2 0.00341 +5 ctsbuf_net_1827:2 grid_clb_1__1_:prog_clk[0] 0.0001664583 + +*END + +*D_NET ropt_net_34 9.404471e-05 //LENGTH 0.920 LUMPCC 0 DR + +*CONN +*I ropt_h_inst_7752:X O *L 0 *C 659.930 912.560 +*I ropt_h_inst_7753:A I *L 0.001746 *C 660.560 912.560 +*N ropt_net_34:2 *C 660.523 912.560 +*N ropt_net_34:3 *C 659.968 912.560 + +*CAP +0 ropt_h_inst_7752:X 1e-06 +1 ropt_h_inst_7753:A 1e-06 +2 ropt_net_34:2 4.602236e-05 +3 ropt_net_34:3 4.602236e-05 + +*RES +0 ropt_h_inst_7752:X ropt_net_34:3 0.152 +1 ropt_net_34:2 ropt_h_inst_7753:A 0.152 +2 ropt_net_34:3 ropt_net_34:2 0.0004955357 + +*END + +*D_NET ropt_net_37 9.580351e-05 //LENGTH 0.920 LUMPCC 0 DR + +*CONN +*I ropt_h_inst_7755:X O *L 0 *C 399.570 912.560 +*I ropt_h_inst_7756:A I *L 0.001746 *C 400.200 912.560 +*N ropt_net_37:2 *C 400.163 912.560 +*N ropt_net_37:3 *C 399.608 912.560 + +*CAP +0 ropt_h_inst_7755:X 1e-06 +1 ropt_h_inst_7756:A 1e-06 +2 ropt_net_37:2 4.690175e-05 +3 ropt_net_37:3 4.690175e-05 + +*RES +0 ropt_h_inst_7755:X ropt_net_37:3 0.152 +1 ropt_net_37:2 ropt_h_inst_7756:A 0.152 +2 ropt_net_37:3 ropt_net_37:2 0.0004955357 + +*END + +*D_NET ropt_net_39 0.001188676 //LENGTH 7.475 LUMPCC 0.0004855282 DR + +*CONN +*I ropt_h_inst_7757:X O *L 0 *C 284.930 782.680 +*I ropt_h_inst_7758:A I *L 0.001776 *C 278.760 782.000 +*N ropt_net_39:2 *C 278.760 782.000 +*N ropt_net_39:3 *C 278.760 782.045 +*N ropt_net_39:4 *C 278.760 782.635 +*N ropt_net_39:5 *C 278.805 782.680 +*N ropt_net_39:6 *C 284.893 782.680 + +*CAP +0 ropt_h_inst_7757:X 1e-06 +1 ropt_h_inst_7758:A 1e-06 +2 ropt_net_39:2 3.138686e-05 +3 ropt_net_39:3 5.138759e-05 +4 ropt_net_39:4 5.138759e-05 +5 ropt_net_39:5 0.0002834931 +6 ropt_net_39:6 0.0002834931 +7 ropt_net_39:6 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:3 0.0002427641 +8 ropt_net_39:5 grid_io_left_1_right_width_0_height_0__pin_1_upper[0]:4 0.0002427641 + +*RES +0 ropt_h_inst_7757:X ropt_net_39:6 0.152 +1 ropt_net_39:6 ropt_net_39:5 0.005435268 +2 ropt_net_39:5 ropt_net_39:4 0.0045 +3 ropt_net_39:4 ropt_net_39:3 0.0005267857 +4 ropt_net_39:2 ropt_h_inst_7758:A 0.152 +5 ropt_net_39:3 ropt_net_39:2 0.0045 + +*END + +*D_NET gfpga_pad_GPIO_A[0] 0.02326683 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*I grid_io_top_1__3_:gfpga_pad_GPIO_A[0] O *L 0 *C 506.460 924.730 +*P gfpga_pad_GPIO_A[0] O *L 0 *C 506.460 1196.385 +*N gfpga_pad_GPIO_A[0]:2 *C 506.460 1174.730 +*N gfpga_pad_GPIO_A[0]:3 *C 506.460 1124.730 +*N gfpga_pad_GPIO_A[0]:4 *C 506.460 1115.520 +*N gfpga_pad_GPIO_A[0]:5 *C 506.460 1115.519 +*N gfpga_pad_GPIO_A[0]:6 *C 506.460 1074.730 +*N gfpga_pad_GPIO_A[0]:7 *C 506.460 1024.730 +*N gfpga_pad_GPIO_A[0]:8 *C 506.460 974.730 + +*CAP +0 grid_io_top_1__3_:gfpga_pad_GPIO_A[0] 0.002198176 +1 gfpga_pad_GPIO_A[0] 0.0009160322 +2 gfpga_pad_GPIO_A[0]:2 0.003045773 +3 gfpga_pad_GPIO_A[0]:3 0.002510283 +4 gfpga_pad_GPIO_A[0]:4 0.0003805416 +5 gfpga_pad_GPIO_A[0]:5 0.001747034 +6 gfpga_pad_GPIO_A[0]:6 0.00387723 +7 gfpga_pad_GPIO_A[0]:7 0.004261892 +8 gfpga_pad_GPIO_A[0]:8 0.004329871 + +*RES +0 grid_io_top_1__3_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[0]:8 0.04464286 +1 gfpga_pad_GPIO_A[0]:8 gfpga_pad_GPIO_A[0]:7 0.04464286 +2 gfpga_pad_GPIO_A[0]:7 gfpga_pad_GPIO_A[0]:6 0.04464286 +3 gfpga_pad_GPIO_A[0]:6 gfpga_pad_GPIO_A[0]:5 0.03641875 +4 gfpga_pad_GPIO_A[0]:3 gfpga_pad_GPIO_A[0]:2 0.04464286 +5 gfpga_pad_GPIO_A[0]:2 gfpga_pad_GPIO_A[0] 0.01933482 +6 gfpga_pad_GPIO_A[0]:4 gfpga_pad_GPIO_A[0]:3 0.008223215 +7 gfpga_pad_GPIO_A[0]:5 gfpga_pad_GPIO_A[0]:4 1e-05 + +*END + +*D_NET cby_1__1__1_chany_top_out[14] 0.001274636 //LENGTH 11.020 LUMPCC 0.0005263244 DR + +*CONN +*I cby_1__2_:chany_top_out[14] O *L 0 *C 586.040 777.850 +*I sb_1__2_:chany_bottom_in[14] I *L 0 *C 586.040 788.870 + +*CAP +0 cby_1__2_:chany_top_out[14] 0.0003741559 +1 sb_1__2_:chany_bottom_in[14] 0.0003741559 +2 cby_1__2_:chany_top_out[14] cby_1__2_:chany_top_out[1] 0.0001315811 +3 sb_1__2_:chany_bottom_in[14] sb_1__2_:chany_bottom_in[1] 0.0001315811 +4 cby_1__2_:chany_top_out[14] cby_1__2_:chany_top_out[4] 0.0001315811 +5 sb_1__2_:chany_bottom_in[14] sb_1__2_:chany_bottom_in[4] 0.0001315811 + +*RES +0 cby_1__2_:chany_top_out[14] sb_1__2_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_15_[0] 0.001380974 //LENGTH 7.660 LUMPCC 0.0002537467 DR + +*CONN +*I cby_1__2_:left_grid_pin_15_[0] O *L 0 *C 548.470 703.120 +*I grid_clb_1__2_:right_width_0_height_0__pin_15_[0] I *L 0 *C 540.810 703.120 + +*CAP +0 cby_1__2_:left_grid_pin_15_[0] 0.0005636135 +1 grid_clb_1__2_:right_width_0_height_0__pin_15_[0] 0.0005636135 +2 cby_1__2_:left_grid_pin_15_[0] cby_1__2_:left_grid_pin_12_[0] 0.0001268733 +3 grid_clb_1__2_:right_width_0_height_0__pin_15_[0] grid_clb_1__2_:right_width_0_height_0__pin_12_[0] 0.0001268733 + +*RES +0 cby_1__2_:left_grid_pin_15_[0] grid_clb_1__2_:right_width_0_height_0__pin_15_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[0] 0.001237842 //LENGTH 11.020 LUMPCC 0.0005802679 DR + +*CONN +*I cby_2__1_:chany_bottom_out[0] O *L 0 *C 861.580 408.070 +*I sb_2__0_:chany_top_in[0] I *L 0 *C 861.580 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[0] 0.0003287869 +1 sb_2__0_:chany_top_in[0] 0.0003287869 +2 cby_2__1_:chany_bottom_out[0] cby_2__1_:chany_bottom_out[17] 0.0001449382 +3 sb_2__0_:chany_top_in[0] sb_2__0_:chany_top_in[17] 0.0001449382 +4 cby_2__1_:chany_bottom_out[0] cby_2__1_:chany_bottom_in[12] 0.0001451958 +5 sb_2__0_:chany_top_in[0] sb_2__0_:chany_top_out[12] 0.0001451958 + +*RES +0 cby_2__1_:chany_bottom_out[0] sb_2__0_:chany_top_in[0] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[15] 0.001231936 //LENGTH 11.020 LUMPCC 0.0005931448 DR + +*CONN +*I cby_2__1_:chany_bottom_out[15] O *L 0 *C 834.900 408.070 +*I sb_2__0_:chany_top_in[15] I *L 0 *C 834.900 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[15] 0.0003193958 +1 sb_2__0_:chany_top_in[15] 0.0003193958 +2 cby_2__1_:chany_bottom_out[15] cby_2__1_:chany_bottom_out[12] 0.0001482862 +3 sb_2__0_:chany_top_in[15] sb_2__0_:chany_top_in[12] 0.0001482862 +4 cby_2__1_:chany_bottom_out[15] cby_2__1_:chany_bottom_out[14] 0.0001482862 +5 sb_2__0_:chany_top_in[15] sb_2__0_:chany_top_in[14] 0.0001482862 + +*RES +0 cby_2__1_:chany_bottom_out[15] sb_2__0_:chany_top_in[15] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[12] 0.001287871 //LENGTH 11.020 LUMPCC 0.0005265675 DR + +*CONN +*I cby_2__1_:chany_top_out[12] O *L 0 *C 860.660 516.730 +*I sb_2__1_:chany_bottom_in[12] I *L 0 *C 860.660 527.750 + +*CAP +0 cby_2__1_:chany_top_out[12] 0.0003806519 +1 sb_2__1_:chany_bottom_in[12] 0.0003806519 +2 cby_2__1_:chany_top_out[12] cby_2__1_:chany_top_out[19] 0.0001337766 +3 sb_2__1_:chany_bottom_in[12] sb_2__1_:chany_bottom_in[19] 0.0001337766 +4 cby_2__1_:chany_top_out[12] cby_2__1_:chany_top_in[12] 0.0001295071 +5 sb_2__1_:chany_bottom_in[12] sb_2__1_:chany_bottom_out[12] 0.0001295071 + +*RES +0 cby_2__1_:chany_top_out[12] sb_2__1_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_12_[0] 0.001070575 //LENGTH 7.660 LUMPCC 0.0003665466 DR + +*CONN +*I cby_2__1_:left_grid_pin_12_[0] O *L 0 *C 809.750 443.360 +*I grid_clb_2__1_:right_width_0_height_0__pin_12_[0] I *L 0 *C 802.090 443.360 + +*CAP +0 cby_2__1_:left_grid_pin_12_[0] 0.0003520143 +1 grid_clb_2__1_:right_width_0_height_0__pin_12_[0] 0.0003520143 +2 cby_2__1_:left_grid_pin_12_[0] cby_2__1_:left_grid_pin_15_[0] 0.0001832733 +3 grid_clb_2__1_:right_width_0_height_0__pin_12_[0] grid_clb_2__1_:right_width_0_height_0__pin_15_[0] 0.0001832733 + +*RES +0 cby_2__1_:left_grid_pin_12_[0] grid_clb_2__1_:right_width_0_height_0__pin_12_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_9_[0] 0.001095037 //LENGTH 7.660 LUMPCC 0.0003590838 DR + +*CONN +*I cby_2__1_:left_grid_pin_9_[0] O *L 0 *C 809.750 489.600 +*I grid_clb_2__1_:right_width_0_height_0__pin_9_[0] I *L 0 *C 802.090 489.600 + +*CAP +0 cby_2__1_:left_grid_pin_9_[0] 0.0003679763 +1 grid_clb_2__1_:right_width_0_height_0__pin_9_[0] 0.0003679763 +2 cby_2__1_:left_grid_pin_9_[0] cby_2__1_:left_grid_pin_6_[0] 0.0001795419 +3 grid_clb_2__1_:right_width_0_height_0__pin_9_[0] grid_clb_2__1_:right_width_0_height_0__pin_6_[0] 0.0001795419 + +*RES +0 cby_2__1_:left_grid_pin_9_[0] grid_clb_2__1_:right_width_0_height_0__pin_9_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[9] 0.001264483 //LENGTH 11.020 LUMPCC 0.0005426441 DR + +*CONN +*I cby_2__2_:chany_bottom_out[9] O *L 0 *C 848.700 669.190 +*I sb_2__1_:chany_top_in[9] I *L 0 *C 848.700 658.170 +*N cby_1__1__3_chany_bottom_out[9]:2 *C 848.700 667.519 +*N cby_1__1__3_chany_bottom_out[9]:3 *C 848.700 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[9] 0.0001111417 +1 sb_2__1_:chany_top_in[9] 0.000249778 +2 cby_1__1__3_chany_bottom_out[9]:2 0.000249778 +3 cby_1__1__3_chany_bottom_out[9]:3 0.0001111417 +4 cby_2__2_:chany_bottom_out[9] cby_2__2_:chany_bottom_out[7] 7.294814e-06 +5 sb_2__1_:chany_top_in[9] sb_2__1_:chany_top_in[7] 0.0001283662 +6 cby_1__1__3_chany_bottom_out[9]:3 cby_1__1__3_chany_bottom_out[7]:3 7.294814e-06 +7 cby_1__1__3_chany_bottom_out[9]:2 cby_1__1__3_chany_bottom_out[7]:2 0.0001283662 +8 cby_2__2_:chany_bottom_out[9] cby_2__2_:chany_bottom_in[8] 7.294814e-06 +9 sb_2__1_:chany_top_in[9] sb_2__1_:chany_top_out[8] 0.0001283662 +10 cby_1__1__3_chany_bottom_out[9]:3 sb_2__1__0_chany_top_out[8]:2 7.294814e-06 +11 cby_1__1__3_chany_bottom_out[9]:2 sb_2__1__0_chany_top_out[8]:3 0.0001283662 + +*RES +0 cby_2__2_:chany_bottom_out[9] cby_1__1__3_chany_bottom_out[9]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[9]:3 cby_1__1__3_chany_bottom_out[9]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[9]:2 sb_2__1_:chany_top_in[9] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_top_out[5] 0.001256755 //LENGTH 11.020 LUMPCC 0.0005666443 DR + +*CONN +*I cby_2__2_:chany_top_out[5] O *L 0 *C 856.980 777.850 +*I sb_2__2_:chany_bottom_in[5] I *L 0 *C 856.980 788.870 + +*CAP +0 cby_2__2_:chany_top_out[5] 0.0003450552 +1 sb_2__2_:chany_bottom_in[5] 0.0003450552 +2 cby_2__2_:chany_top_out[5] cby_2__2_:chany_top_out[16] 0.0001410753 +3 sb_2__2_:chany_bottom_in[5] sb_2__2_:chany_bottom_in[16] 0.0001410753 +4 cby_2__2_:chany_top_out[5] cby_2__2_:chany_top_in[6] 0.0001422469 +5 sb_2__2_:chany_bottom_in[5] sb_2__2_:chany_bottom_out[6] 0.0001422469 + +*RES +0 cby_2__2_:chany_top_out[5] sb_2__2_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_11_[0] 0.001223386 //LENGTH 7.660 LUMPCC 0.0007070043 DR + +*CONN +*I cby_2__2_:left_grid_pin_11_[0] O *L 0 *C 809.750 746.640 +*I grid_clb_2__2_:right_width_0_height_0__pin_11_[0] I *L 0 *C 802.090 746.640 + +*CAP +0 cby_2__2_:left_grid_pin_11_[0] 0.000258191 +1 grid_clb_2__2_:right_width_0_height_0__pin_11_[0] 0.000258191 +2 cby_2__2_:left_grid_pin_11_[0] cby_2__2_:left_grid_pin_10_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_11_[0] grid_clb_2__2_:right_width_0_height_0__pin_10_[0] 0.0001767511 +4 cby_2__2_:left_grid_pin_11_[0] cby_2__2_:left_grid_pin_8_[0] 0.0001767511 +5 grid_clb_2__2_:right_width_0_height_0__pin_11_[0] grid_clb_2__2_:right_width_0_height_0__pin_8_[0] 0.0001767511 + +*RES +0 cby_2__2_:left_grid_pin_11_[0] grid_clb_2__2_:right_width_0_height_0__pin_11_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_43_lower[0] 0.002181091 //LENGTH 10.145 LUMPCC 0.001407226 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_43_lower[0] O *L 0 *C 540.810 385.560 +*I sb_1__0_:left_top_grid_pin_43_[0] I *L 0 *C 548.395 385.560 +*N grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 *C 547.860 385.560 +*N grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 *C 547.860 384.880 +*N grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 *C 541.420 384.880 +*N grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 *C 541.420 385.560 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_43_lower[0] 0.0001182206 +1 sb_1__0_:left_top_grid_pin_43_[0] 0.0001045389 +2 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 4.519905e-05 +3 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 0.000225624 +4 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 0.0002235127 +5 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 5.67695e-05 +6 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 direct_interc_2_out[0]:35 2.335628e-05 +7 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 direct_interc_2_out[0]:36 2.335628e-05 +8 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 direct_interc_2_out[0]:36 3.492634e-05 +9 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 direct_interc_2_out[0]:35 3.492634e-05 +10 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 direct_interc_5_out[0]:32 2.476164e-05 +11 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 direct_interc_5_out[0]:33 2.476164e-05 +12 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 direct_interc_5_out[0]:33 2.335628e-05 +13 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 direct_interc_5_out[0]:32 2.335628e-05 +14 grid_clb_1__1_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] 2.15815e-06 +15 sb_1__0_:left_top_grid_pin_43_[0] sb_1__0_:top_left_grid_pin_41_[0] 2.092879e-06 +16 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 2.15815e-06 +17 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 1.693953e-05 +18 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] 9.741985e-05 +19 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 0.0002279304 +20 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 9.880071e-05 +21 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 1.693953e-05 +22 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 sb_1__0_:top_left_grid_pin_41_[0] 9.880071e-05 +23 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 9.741985e-05 +24 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 0.0002279304 +25 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 1.366383e-05 +26 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 1.366383e-05 +27 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 2.092879e-06 +28 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 ctsbuf_net_211:9 6.258812e-05 +29 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 ctsbuf_net_211:13 6.258812e-05 +30 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 ctsbuf_net_1019:7 7.561906e-05 +31 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 ctsbuf_net_1019:6 7.561906e-05 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 9.556666e-05 +1 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 0.0001065333 +2 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 0.001008933 +3 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 0.0001065333 +4 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 sb_1__0_:left_top_grid_pin_43_[0] 8.381665e-05 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_36_upper[0] 0.001430733 //LENGTH 7.660 LUMPCC 0.0003714104 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] O *L 0 *C 540.810 534.480 +*I sb_1__1_:bottom_left_grid_pin_36_[0] I *L 0 *C 548.470 534.480 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] 0.0005296612 +1 sb_1__1_:bottom_left_grid_pin_36_[0] 0.0005296612 +2 grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] 0.0001201387 +3 sb_1__1_:bottom_left_grid_pin_36_[0] sb_1__1_:bottom_left_grid_pin_35_[0] 0.0001201387 +4 grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_38_upper[0] 6.556654e-05 +5 sb_1__1_:bottom_left_grid_pin_36_[0] sb_1__1_:bottom_left_grid_pin_38_[0] 6.556654e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] sb_1__1_:bottom_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_44_lower[0] 0.001252591 //LENGTH 11.020 LUMPCC 0.0005593378 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] O *L 0 *C 523.940 641.990 +*I sb_1__1_:left_top_grid_pin_44_[0] I *L 0 *C 523.940 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0003466268 +1 sb_1__1_:left_top_grid_pin_44_[0] 0.0003466268 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] 0.0001398345 +3 sb_1__1_:left_top_grid_pin_44_[0] sb_1__1_:left_top_grid_pin_45_[0] 0.0001398345 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0001398345 +5 sb_1__1_:left_top_grid_pin_44_[0] sb_1__1_:left_top_grid_pin_47_[0] 0.0001398345 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] sb_1__1_:left_top_grid_pin_44_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_35_lower[0] 0.002392468 //LENGTH 22.560 LUMPCC 7.518662e-05 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_35_lower[0] O *L 0 *C 540.810 666.400 +*I sb_1__1_:top_left_grid_pin_35_[0] I *L 0 *C 552.460 658.170 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 *C 552.460 659.543 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:3 *C 552.462 659.600 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:4 *C 552.905 659.600 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:5 *C 552.920 659.608 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:6 *C 552.920 661.633 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:7 *C 552.900 661.640 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:8 *C 542.348 661.640 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:9 *C 542.340 661.697 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:10 *C 542.340 666.343 +*N grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 *C 542.332 666.400 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_35_lower[0] 0.0001833126 +1 sb_1__1_:top_left_grid_pin_35_[0] 7.018176e-05 +2 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 7.018176e-05 +3 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:3 3.343499e-05 +4 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:4 3.343499e-05 +5 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:5 0.0001026 +6 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:6 0.0001026 +7 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:7 0.0005337138 +8 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:8 0.0005337138 +9 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:9 0.0002353975 +10 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:10 0.0002353975 +11 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 0.0001833126 +12 grid_clb_1__2_:right_width_0_height_0__pin_35_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] 1.757948e-05 +13 sb_1__1_:top_left_grid_pin_35_[0] sb_1__1_:top_left_grid_pin_34_[0] 2.001383e-05 +14 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 1.757948e-05 +15 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 2.001383e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_35_lower[0] grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 0.000238525 +1 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:10 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:9 0.004147321 +2 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:10 0.00341 +3 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:9 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:8 0.00341 +4 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:8 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:7 0.001653225 +5 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:7 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:6 0.00341 +6 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:6 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:5 0.00031725 +7 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:4 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:3 6.499219e-05 +8 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:5 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:4 0.00341 +9 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 sb_1__1_:top_left_grid_pin_35_[0] 0.001225446 +10 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 0.00341 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_45_lower[0] 0.001178375 //LENGTH 11.020 LUMPCC 0.0003731462 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] O *L 0 *C 786.140 380.870 +*I sb_2__0_:left_top_grid_pin_45_[0] I *L 0 *C 786.140 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] 0.0004026144 +1 sb_2__0_:left_top_grid_pin_45_[0] 0.0004026144 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_42_lower[0] 4.085038e-05 +3 sb_2__0_:left_top_grid_pin_45_[0] sb_2__0_:left_top_grid_pin_42_[0] 4.085038e-05 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0001457227 +5 sb_2__0_:left_top_grid_pin_45_[0] sb_2__0_:left_top_grid_pin_44_[0] 0.0001457227 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] sb_2__0_:left_top_grid_pin_45_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_38_lower[0] 0.001158178 //LENGTH 7.660 LUMPCC 0.0006431274 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] O *L 0 *C 802.090 391.680 +*I sb_2__0_:top_left_grid_pin_38_[0] I *L 0 *C 809.750 391.680 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] 0.0002575252 +1 sb_2__0_:top_left_grid_pin_38_[0] 0.0002575252 +2 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_36_lower[0] 1.139335e-05 +3 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 0.000122113 +4 sb_2__0_:top_left_grid_pin_38_[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 0.000122113 +5 sb_2__0_:top_left_grid_pin_38_[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 1.139335e-05 +6 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] 0.0001880573 +7 sb_2__0_:top_left_grid_pin_38_[0] sb_2__0_:top_left_grid_pin_39_[0] 0.0001880573 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] sb_2__0_:top_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_46_upper[0] 0.001132292 //LENGTH 7.660 LUMPCC 0.000345612 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_46_upper[0] O *L 0 *C 640.470 646.680 +*I sb_1__1_:right_top_grid_pin_46_[0] I *L 0 *C 632.810 646.680 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_46_upper[0] 0.00039334 +1 sb_1__1_:right_top_grid_pin_46_[0] 0.00039334 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_47_upper[0] 0.000172806 +3 sb_1__1_:right_top_grid_pin_46_[0] sb_1__1_:right_top_grid_pin_47_[0] 0.000172806 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_46_upper[0] sb_1__1_:right_top_grid_pin_46_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_36_upper[0] 0.00124806 //LENGTH 7.660 LUMPCC 0.0005000117 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] O *L 0 *C 802.090 795.600 +*I sb_2__2_:bottom_left_grid_pin_36_[0] I *L 0 *C 809.750 795.600 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] 0.0003740243 +1 sb_2__2_:bottom_left_grid_pin_36_[0] 0.0003740243 +2 grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] 0.000160018 +3 sb_2__2_:bottom_left_grid_pin_36_[0] sb_2__2_:bottom_left_grid_pin_35_[0] 0.000160018 +4 grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] 8.998787e-05 +5 sb_2__2_:bottom_left_grid_pin_36_[0] sb_2__2_:bottom_left_grid_pin_38_[0] 8.998787e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] sb_2__2_:bottom_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_io_left_0_ccff_tail[0] 0.002746464 //LENGTH 25.920 LUMPCC 0.000402891 DR + +*CONN +*I grid_io_left_0__1_:ccff_tail[0] O *L 0 *C 274.010 505.920 +*I ropt_h_inst_7749:A I *L 0.001746 *C 281.060 520.880 +*N grid_io_left_0_ccff_tail[0]:2 *C 281.060 520.880 +*N grid_io_left_0_ccff_tail[0]:3 *C 281.060 520.835 +*N grid_io_left_0_ccff_tail[0]:4 *C 281.060 520.245 +*N grid_io_left_0_ccff_tail[0]:5 *C 281.105 520.200 +*N grid_io_left_0_ccff_tail[0]:6 *C 282.395 520.200 +*N grid_io_left_0_ccff_tail[0]:7 *C 282.440 520.155 +*N grid_io_left_0_ccff_tail[0]:8 *C 282.440 505.978 +*N grid_io_left_0_ccff_tail[0]:9 *C 282.433 505.920 + +*CAP +0 grid_io_left_0__1_:ccff_tail[0] 0.0003565577 +1 ropt_h_inst_7749:A 1e-06 +2 grid_io_left_0_ccff_tail[0]:2 2.852061e-05 +3 grid_io_left_0_ccff_tail[0]:3 4.07992e-05 +4 grid_io_left_0_ccff_tail[0]:4 4.07992e-05 +5 grid_io_left_0_ccff_tail[0]:5 0.0001066841 +6 grid_io_left_0_ccff_tail[0]:6 0.0001066841 +7 grid_io_left_0_ccff_tail[0]:7 0.0006529851 +8 grid_io_left_0_ccff_tail[0]:8 0.0006529851 +9 grid_io_left_0_ccff_tail[0]:9 0.0003565577 +10 grid_io_left_0__1_:ccff_tail[0] grid_io_left_0__1_:right_width_0_height_0__pin_0_[0] 0.0002014455 +11 grid_io_left_0_ccff_tail[0]:9 cby_0__1_:left_grid_pin_0_[0] 0.0002014455 + +*RES +0 grid_io_left_0__1_:ccff_tail[0] grid_io_left_0_ccff_tail[0]:9 0.001319525 +1 grid_io_left_0_ccff_tail[0]:2 ropt_h_inst_7749:A 0.152 +2 grid_io_left_0_ccff_tail[0]:3 grid_io_left_0_ccff_tail[0]:2 0.0045 +3 grid_io_left_0_ccff_tail[0]:5 grid_io_left_0_ccff_tail[0]:4 0.0045 +4 grid_io_left_0_ccff_tail[0]:4 grid_io_left_0_ccff_tail[0]:3 0.0005267857 +5 grid_io_left_0_ccff_tail[0]:6 grid_io_left_0_ccff_tail[0]:5 0.001151786 +6 grid_io_left_0_ccff_tail[0]:7 grid_io_left_0_ccff_tail[0]:6 0.0045 +7 grid_io_left_0_ccff_tail[0]:8 grid_io_left_0_ccff_tail[0]:7 0.01265848 +8 grid_io_left_0_ccff_tail[0]:9 grid_io_left_0_ccff_tail[0]:8 0.00341 + +*END + +*D_NET grid_io_top_1_ccff_tail[0] 0.001773878 //LENGTH 14.285 LUMPCC 0.0004424262 DR + +*CONN +*I grid_io_top_2__3_:ccff_tail[0] O *L 0 *C 668.990 911.200 +*I ropt_h_inst_7752:A I *L 0.001746 *C 656.880 912.560 +*N grid_io_top_1_ccff_tail[0]:2 *C 656.918 912.560 +*N grid_io_top_1_ccff_tail[0]:3 *C 658.215 912.560 +*N grid_io_top_1_ccff_tail[0]:4 *C 658.260 912.515 +*N grid_io_top_1_ccff_tail[0]:5 *C 658.260 911.258 +*N grid_io_top_1_ccff_tail[0]:6 *C 658.268 911.200 +*N grid_io_top_1_ccff_tail[0]:7 *C 667.519 911.200 +*N grid_io_top_1_ccff_tail[0]:8 *C 667.520 911.200 + +*CAP +0 grid_io_top_2__3_:ccff_tail[0] 0.0002152292 +1 ropt_h_inst_7752:A 1e-06 +2 grid_io_top_1_ccff_tail[0]:2 8.280156e-05 +3 grid_io_top_1_ccff_tail[0]:3 8.280156e-05 +4 grid_io_top_1_ccff_tail[0]:4 7.839395e-05 +5 grid_io_top_1_ccff_tail[0]:5 7.839395e-05 +6 grid_io_top_1_ccff_tail[0]:6 0.0002888014 +7 grid_io_top_1_ccff_tail[0]:7 0.0002888014 +8 grid_io_top_1_ccff_tail[0]:8 0.0002152292 +9 grid_io_top_1_ccff_tail[0]:6 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 0.0002212131 +10 grid_io_top_1_ccff_tail[0]:7 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 0.0002212131 + +*RES +0 grid_io_top_2__3_:ccff_tail[0] grid_io_top_1_ccff_tail[0]:8 0.0002303 +1 grid_io_top_1_ccff_tail[0]:5 grid_io_top_1_ccff_tail[0]:4 0.001122768 +2 grid_io_top_1_ccff_tail[0]:6 grid_io_top_1_ccff_tail[0]:5 0.00341 +3 grid_io_top_1_ccff_tail[0]:3 grid_io_top_1_ccff_tail[0]:2 0.001158482 +4 grid_io_top_1_ccff_tail[0]:4 grid_io_top_1_ccff_tail[0]:3 0.0045 +5 grid_io_top_1_ccff_tail[0]:2 ropt_h_inst_7752:A 0.152 +6 grid_io_top_1_ccff_tail[0]:8 grid_io_top_1_ccff_tail[0]:7 1e-05 +7 grid_io_top_1_ccff_tail[0]:7 grid_io_top_1_ccff_tail[0]:6 0.001449402 + +*END + +*D_NET sb_0__0__0_chanx_right_out[13] 0.001265871 //LENGTH 7.660 LUMPCC 0.0006209371 DR + +*CONN +*I sb_0__0_:chanx_right_out[13] O *L 0 *C 400.050 354.960 +*I cbx_1__0_:chanx_left_in[13] I *L 0 *C 407.710 354.960 + +*CAP +0 sb_0__0_:chanx_right_out[13] 0.0003224669 +1 cbx_1__0_:chanx_left_in[13] 0.0003224669 +2 sb_0__0_:chanx_right_out[13] sb_0__0_:chanx_right_in[19] 2.007841e-05 +3 cbx_1__0_:chanx_left_in[13] cbx_1__0_:chanx_left_out[19] 2.007841e-05 +4 sb_0__0_:chanx_right_out[13] sb_0__0_:chanx_right_out[0] 0.0001258722 +5 cbx_1__0_:chanx_left_in[13] sb_0__0__0_chanx_right_out[0]:7 0.0001258722 +6 sb_0__0_:chanx_right_out[13] sb_0__0_:chanx_right_out[17] 0.000164518 +7 cbx_1__0_:chanx_left_in[13] cbx_1__0_:chanx_left_in[17] 0.000164518 + +*RES +0 sb_0__0_:chanx_right_out[13] cbx_1__0_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[13] 0.001513306 //LENGTH 11.180 LUMPCC 0.0009138882 DR + +*CONN +*I sb_0__0_:chany_top_out[13] O *L 0 *C 310.960 396.970 +*I cby_0__1_:chany_bottom_in[13] I *L 0 *C 310.960 408.150 + +*CAP +0 sb_0__0_:chany_top_out[13] 0.0002997091 +1 cby_0__1_:chany_bottom_in[13] 0.0002997091 +2 sb_0__0_:chany_top_out[13] sb_0__0_:chany_top_out[8] 0.0002284721 +3 cby_0__1_:chany_bottom_in[13] cby_0__1_:chany_bottom_in[8] 0.0002284721 +4 sb_0__0_:chany_top_out[13] sb_0__0_:chany_top_out[19] 0.0002284721 +5 cby_0__1_:chany_bottom_in[13] cby_0__1_:chany_bottom_in[19] 0.0002284721 + +*RES +0 sb_0__0_:chany_top_out[13] cby_0__1_:chany_bottom_in[13] 0.001751533 + +*END + +*D_NET sb_0__1__0_chanx_right_out[10] 0.001168956 //LENGTH 7.660 LUMPCC 0.0004730283 DR + +*CONN +*I sb_0__1_:chanx_right_out[10] O *L 0 *C 400.050 588.880 +*I cbx_1__1_:chanx_left_in[10] I *L 0 *C 407.710 588.880 + +*CAP +0 sb_0__1_:chanx_right_out[10] 0.000347964 +1 cbx_1__1_:chanx_left_in[10] 0.000347964 +2 sb_0__1_:chanx_right_out[10] sb_0__1_:chanx_right_out[2] 0.0001729695 +3 cbx_1__1_:chanx_left_in[10] cbx_1__1_:chanx_left_in[2] 0.0001729695 +4 sb_0__1_:chanx_right_out[10] sb_0__1_:chanx_right_out[6] 6.354468e-05 +5 cbx_1__1_:chanx_left_in[10] cbx_1__1_:chanx_left_in[6] 6.354468e-05 + +*RES +0 sb_0__1_:chanx_right_out[10] cbx_1__1_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[6] 0.001286253 //LENGTH 11.020 LUMPCC 0.0005169292 DR + +*CONN +*I sb_0__1_:chany_bottom_out[6] O *L 0 *C 357.420 527.750 +*I cby_0__1_:chany_top_in[6] I *L 0 *C 357.420 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[6] 0.000384662 +1 cby_0__1_:chany_top_in[6] 0.000384662 +2 sb_0__1_:chany_bottom_out[6] sb_0__1_:chany_bottom_in[2] 0.0001292323 +3 cby_0__1_:chany_top_in[6] cby_0__1_:chany_top_out[2] 0.0001292323 +4 sb_0__1_:chany_bottom_out[6] sb_0__1_:chany_bottom_out[8] 0.0001292323 +5 cby_0__1_:chany_top_in[6] cby_0__1_:chany_top_in[8] 0.0001292323 + +*RES +0 sb_0__1_:chany_bottom_out[6] cby_0__1_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_top_out[5] 0.001269324 //LENGTH 11.020 LUMPCC 0.0005662117 DR + +*CONN +*I sb_0__1_:chany_top_out[5] O *L 0 *C 331.660 658.170 +*I cby_0__2_:chany_bottom_in[5] I *L 0 *C 331.660 669.190 +*N sb_0__1__0_chany_top_out[5]:2 *C 331.660 667.520 +*N sb_0__1__0_chany_top_out[5]:3 *C 331.660 667.519 + +*CAP +0 sb_0__1_:chany_top_out[5] 0.0002401703 +1 cby_0__2_:chany_bottom_in[5] 0.0001113856 +2 sb_0__1__0_chany_top_out[5]:2 0.0001113856 +3 sb_0__1__0_chany_top_out[5]:3 0.0002401703 +4 sb_0__1_:chany_top_out[5] sb_0__1_:chany_top_in[3] 0.0001307218 +5 cby_0__2_:chany_bottom_in[5] cby_0__2_:chany_bottom_out[3] 7.193657e-06 +6 sb_0__1__0_chany_top_out[5]:2 cby_0__1__1_chany_bottom_out[3]:3 7.193657e-06 +7 sb_0__1__0_chany_top_out[5]:3 cby_0__1__1_chany_bottom_out[3]:2 0.0001307218 +8 sb_0__1_:chany_top_out[5] sb_0__1_:chany_top_in[4] 0.0001378419 +9 cby_0__2_:chany_bottom_in[5] cby_0__2_:chany_bottom_out[4] 7.348477e-06 +10 sb_0__1__0_chany_top_out[5]:2 cby_0__1__1_chany_bottom_out[4]:3 7.348477e-06 +11 sb_0__1__0_chany_top_out[5]:3 cby_0__1__1_chany_bottom_out[4]:2 0.0001378419 + +*RES +0 sb_0__1_:chany_top_out[5] sb_0__1__0_chany_top_out[5]:3 0.008347321 +1 sb_0__1__0_chany_top_out[5]:2 cby_0__2_:chany_bottom_in[5] 0.001491072 +2 sb_0__1__0_chany_top_out[5]:3 sb_0__1__0_chany_top_out[5]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[1] 0.001217528 //LENGTH 7.660 LUMPCC 0.0004717558 DR + +*CONN +*I sb_0__2_:chanx_right_out[1] O *L 0 *C 400.050 836.400 +*I cbx_1__2_:chanx_left_in[1] I *L 0 *C 407.710 836.400 + +*CAP +0 sb_0__2_:chanx_right_out[1] 0.0003728859 +1 cbx_1__2_:chanx_left_in[1] 0.0003728859 +2 sb_0__2_:chanx_right_out[1] sb_0__2_:chanx_right_in[7] 7.013153e-05 +3 cbx_1__2_:chanx_left_in[1] cbx_1__2_:chanx_left_out[7] 7.013153e-05 +4 sb_0__2_:chanx_right_out[1] sb_0__2_:chanx_right_out[19] 0.0001657464 +5 cbx_1__2_:chanx_left_in[1] cbx_1__2_:chanx_left_in[19] 0.0001657464 + +*RES +0 sb_0__2_:chanx_right_out[1] cbx_1__2_:chanx_left_in[1] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[17] 0.001259821 //LENGTH 7.660 LUMPCC 0.0006123732 DR + +*CONN +*I sb_0__2_:chanx_right_out[17] O *L 0 *C 400.050 877.200 +*I cbx_1__2_:chanx_left_in[17] I *L 0 *C 407.710 877.200 + +*CAP +0 sb_0__2_:chanx_right_out[17] 0.0003237239 +1 cbx_1__2_:chanx_left_in[17] 0.0003237239 +2 sb_0__2_:chanx_right_out[17] sb_0__2_:chanx_right_in[0] 0.0001082916 +3 cbx_1__2_:chanx_left_in[17] cbx_1__2__0_chanx_left_out[0]:2 0.0001082916 +4 sb_0__2_:chanx_right_out[17] sb_0__2_:chanx_right_out[8] 3.190323e-05 +5 cbx_1__2_:chanx_left_in[17] cbx_1__2_:chanx_left_in[8] 3.190323e-05 +6 sb_0__2_:chanx_right_out[17] sb_0__2_:chanx_right_out[18] 0.0001659918 +7 cbx_1__2_:chanx_left_in[17] cbx_1__2_:chanx_left_in[18] 0.0001659918 + +*RES +0 sb_0__2_:chanx_right_out[17] cbx_1__2_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[18] 0.00157596 //LENGTH 11.180 LUMPCC 0.0004134618 DR + +*CONN +*I sb_0__2_:chany_bottom_out[18] O *L 0 *C 310.960 788.950 +*I cby_0__2_:chany_top_in[18] I *L 0 *C 310.960 777.770 + +*CAP +0 sb_0__2_:chany_bottom_out[18] 0.0005812492 +1 cby_0__2_:chany_top_in[18] 0.0005812492 +2 sb_0__2_:chany_bottom_out[18] sb_0__2_:chany_bottom_out[19] 0.0002067309 +3 cby_0__2_:chany_top_in[18] cby_0__2_:chany_top_in[19] 0.0002067309 + +*RES +0 sb_0__2_:chany_bottom_out[18] cby_0__2_:chany_top_in[18] 0.001751533 + +*END + +*D_NET sb_1__0__0_chanx_left_out[8] 0.001310157 //LENGTH 7.660 LUMPCC 0.0006491081 DR + +*CONN +*I sb_1__0_:chanx_left_out[8] O *L 0 *C 519.950 315.520 +*I cbx_1__0_:chanx_right_in[8] I *L 0 *C 512.290 315.520 + +*CAP +0 sb_1__0_:chanx_left_out[8] 0.0003305242 +1 cbx_1__0_:chanx_right_in[8] 0.0003305242 +2 sb_1__0_:chanx_left_out[8] sb_1__0_:chanx_left_out[10] 0.0001625319 +3 cbx_1__0_:chanx_right_in[8] cbx_1__0_:chanx_right_in[10] 0.0001625319 +4 sb_1__0_:chanx_left_out[8] sb_1__0_:chanx_left_out[12] 0.0001620221 +5 cbx_1__0_:chanx_right_in[8] cbx_1__0_:chanx_right_in[12] 0.0001620221 + +*RES +0 sb_1__0_:chanx_left_out[8] cbx_1__0_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[3] 0.001408157 //LENGTH 7.660 LUMPCC 0.0005712907 DR + +*CONN +*I sb_1__0_:chanx_right_out[3] O *L 0 *C 661.330 361.760 +*I cbx_2__0_:chanx_left_in[3] I *L 0 *C 668.990 361.760 +*N sb_1__0__0_chanx_right_out[3]:2 *C 667.520 361.760 +*N sb_1__0__0_chanx_right_out[3]:3 *C 667.519 361.760 + +*CAP +0 sb_1__0_:chanx_right_out[3] 0.0002436823 +1 cbx_2__0_:chanx_left_in[3] 0.0001747507 +2 sb_1__0__0_chanx_right_out[3]:2 0.0001747507 +3 sb_1__0__0_chanx_right_out[3]:3 0.0002436823 +4 sb_1__0_:chanx_right_out[3] sb_1__0_:chanx_right_out[1] 0.0001329559 +5 cbx_2__0_:chanx_left_in[3] cbx_2__0_:chanx_left_in[1] 9.866816e-06 +6 sb_1__0__0_chanx_right_out[3]:2 sb_1__0__0_chanx_right_out[1]:2 9.866816e-06 +7 sb_1__0__0_chanx_right_out[3]:3 sb_1__0__0_chanx_right_out[1]:3 0.0001329559 +8 sb_1__0_:chanx_right_out[3] sb_1__0_:chanx_right_out[12] 0.0001329559 +9 cbx_2__0_:chanx_left_in[3] cbx_2__0_:chanx_left_in[12] 9.866816e-06 +10 sb_1__0__0_chanx_right_out[3]:2 sb_1__0__0_chanx_right_out[12]:2 9.866816e-06 +11 sb_1__0__0_chanx_right_out[3]:3 sb_1__0__0_chanx_right_out[12]:3 0.0001329559 + +*RES +0 sb_1__0_:chanx_right_out[3] sb_1__0__0_chanx_right_out[3]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[3]:2 cbx_2__0_:chanx_left_in[3] 0.0002303 +2 sb_1__0__0_chanx_right_out[3]:3 sb_1__0__0_chanx_right_out[3]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[3] 0.001231796 //LENGTH 11.020 LUMPCC 0.0005942238 DR + +*CONN +*I sb_1__0_:chany_top_out[3] O *L 0 *C 591.100 397.050 +*I cby_1__1_:chany_bottom_in[3] I *L 0 *C 591.100 408.070 + +*CAP +0 sb_1__0_:chany_top_out[3] 0.0003187861 +1 cby_1__1_:chany_bottom_in[3] 0.0003187861 +2 sb_1__0_:chany_top_out[3] sb_1__0_:chany_top_in[8] 0.000148556 +3 cby_1__1_:chany_bottom_in[3] cby_1__1_:chany_bottom_out[8] 0.000148556 +4 sb_1__0_:chany_top_out[3] sb_1__0_:chany_top_out[6] 0.000148556 +5 cby_1__1_:chany_bottom_in[3] cby_1__1_:chany_bottom_in[6] 0.000148556 + +*RES +0 sb_1__0_:chany_top_out[3] cby_1__1_:chany_bottom_in[3] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[1] 0.001371595 //LENGTH 7.660 LUMPCC 0.0005800267 DR + +*CONN +*I sb_1__1_:chanx_left_out[1] O *L 0 *C 519.950 609.280 +*I cbx_1__1_:chanx_right_in[1] I *L 0 *C 512.290 609.280 + +*CAP +0 sb_1__1_:chanx_left_out[1] 0.0003957842 +1 cbx_1__1_:chanx_right_in[1] 0.0003957842 +2 sb_1__1_:chanx_left_out[1] sb_1__1_:chanx_left_out[2] 0.0001458667 +3 cbx_1__1_:chanx_right_in[1] cbx_1__1_:chanx_right_in[2] 0.0001458667 +4 sb_1__1_:chanx_left_out[1] sb_1__1_:chanx_left_out[4] 0.0001441466 +5 cbx_1__1_:chanx_right_in[1] cbx_1__1_:chanx_right_in[4] 0.0001441466 + +*RES +0 sb_1__1_:chanx_left_out[1] cbx_1__1_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[15] 0.003342714 //LENGTH 27.190 LUMPCC 0.0007833571 DR + +*CONN +*I sb_1__1_:chanx_left_out[15] O *L 0 *C 519.950 568.480 +*I cbx_1__1_:chanx_right_in[15] I *L 0 *C 510.140 554.950 +*N sb_1__1__0_chanx_left_out[15]:2 *C 510.140 553.565 +*N sb_1__1__0_chanx_left_out[15]:3 *C 510.185 553.520 +*N sb_1__1__0_chanx_left_out[15]:4 *C 513.775 553.520 +*N sb_1__1__0_chanx_left_out[15]:5 *C 513.820 553.565 +*N sb_1__1__0_chanx_left_out[15]:6 *C 513.820 568.423 +*N sb_1__1__0_chanx_left_out[15]:7 *C 513.827 568.480 + +*CAP +0 sb_1__1_:chanx_left_out[15] 0.0003582551 +1 cbx_1__1_:chanx_right_in[15] 9.30739e-05 +2 sb_1__1__0_chanx_left_out[15]:2 9.30739e-05 +3 sb_1__1__0_chanx_left_out[15]:3 0.000145656 +4 sb_1__1__0_chanx_left_out[15]:4 0.000145656 +5 sb_1__1__0_chanx_left_out[15]:5 0.0006826936 +6 sb_1__1__0_chanx_left_out[15]:6 0.0006826936 +7 sb_1__1__0_chanx_left_out[15]:7 0.0003582551 +8 sb_1__1__0_chanx_left_out[15]:3 cbx_1__1__0_chanx_right_out[2]:6 7.524867e-05 +9 sb_1__1__0_chanx_left_out[15]:4 cbx_1__1__0_chanx_right_out[2]:5 7.524867e-05 +10 sb_1__1_:chanx_left_out[15] sb_1__1_:chanx_left_in[3] 0.0001046782 +11 sb_1__1__0_chanx_left_out[15]:7 cbx_1__1_:chanx_right_out[3] 0.0001046782 +12 sb_1__1_:chanx_left_out[15] sb_1__1_:chanx_left_in[7] 0.0001073912 +13 sb_1__1__0_chanx_left_out[15]:7 cbx_1__1_:chanx_right_out[7] 0.0001073912 +14 sb_1__1__0_chanx_left_out[15]:5 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 0.0001043604 +15 sb_1__1__0_chanx_left_out[15]:6 direct_interc_0_out[0]:2 0.0001043604 + +*RES +0 sb_1__1_:chanx_left_out[15] sb_1__1__0_chanx_left_out[15]:7 0.0009591916 +1 sb_1__1__0_chanx_left_out[15]:3 sb_1__1__0_chanx_left_out[15]:2 0.0045 +2 sb_1__1__0_chanx_left_out[15]:2 cbx_1__1_:chanx_right_in[15] 0.001236607 +3 sb_1__1__0_chanx_left_out[15]:4 sb_1__1__0_chanx_left_out[15]:3 0.003205357 +4 sb_1__1__0_chanx_left_out[15]:5 sb_1__1__0_chanx_left_out[15]:4 0.0045 +5 sb_1__1__0_chanx_left_out[15]:6 sb_1__1__0_chanx_left_out[15]:5 0.01326563 +6 sb_1__1__0_chanx_left_out[15]:7 sb_1__1__0_chanx_left_out[15]:6 0.00341 + +*END + +*D_NET sb_1__1__0_chanx_right_out[17] 0.00151845 //LENGTH 7.660 LUMPCC 0.0003341147 DR + +*CONN +*I sb_1__1_:chanx_right_out[17] O *L 0 *C 661.330 594.320 +*I cbx_2__1_:chanx_left_in[17] I *L 0 *C 668.990 594.320 +*N sb_1__1__0_chanx_right_out[17]:2 *C 667.520 594.320 +*N sb_1__1__0_chanx_right_out[17]:3 *C 667.519 594.320 + +*CAP +0 sb_1__1_:chanx_right_out[17] 0.0003717736 +1 cbx_2__1_:chanx_left_in[17] 0.0002203943 +2 sb_1__1__0_chanx_right_out[17]:2 0.0002203943 +3 sb_1__1__0_chanx_right_out[17]:3 0.0003717736 +4 sb_1__1_:chanx_right_out[17] sb_1__1_:chanx_right_in[18] 5.728492e-05 +5 sb_1__1__0_chanx_right_out[17]:3 cbx_1__1__1_chanx_left_out[18]:2 5.728492e-05 +6 sb_1__1_:chanx_right_out[17] sb_1__1_:chanx_right_out[15] 0.0001097725 +7 sb_1__1__0_chanx_right_out[17]:3 sb_1__1__0_chanx_right_out[15]:3 0.0001097725 + +*RES +0 sb_1__1_:chanx_right_out[17] sb_1__1__0_chanx_right_out[17]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[17]:2 cbx_2__1_:chanx_left_in[17] 0.0002303 +2 sb_1__1__0_chanx_right_out[17]:3 sb_1__1__0_chanx_right_out[17]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[13] 0.001295275 //LENGTH 11.020 LUMPCC 0.0004990738 DR + +*CONN +*I sb_1__1_:chany_bottom_out[13] O *L 0 *C 581.440 527.750 +*I cby_1__1_:chany_top_in[13] I *L 0 *C 581.440 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[13] 0.0003981007 +1 cby_1__1_:chany_top_in[13] 0.0003981007 +2 sb_1__1_:chany_bottom_out[13] sb_1__1_:chany_bottom_in[10] 0.0001247684 +3 cby_1__1_:chany_top_in[13] cby_1__1_:chany_top_out[10] 0.0001247684 +4 sb_1__1_:chany_bottom_out[13] sb_1__1_:chany_bottom_out[7] 0.0001247684 +5 cby_1__1_:chany_top_in[13] cby_1__1_:chany_top_in[7] 0.0001247684 + +*RES +0 sb_1__1_:chany_bottom_out[13] cby_1__1_:chany_top_in[13] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[8] 0.001245865 //LENGTH 11.020 LUMPCC 0.0005875931 DR + +*CONN +*I sb_1__1_:chany_top_out[8] O *L 0 *C 588.340 658.170 +*I cby_1__2_:chany_bottom_in[8] I *L 0 *C 588.340 669.190 +*N sb_1__1__0_chany_top_out[8]:2 *C 588.340 667.520 +*N sb_1__1__0_chany_top_out[8]:3 *C 588.340 667.519 + +*CAP +0 sb_1__1_:chany_top_out[8] 0.0002181978 +1 cby_1__2_:chany_bottom_in[8] 0.0001109382 +2 sb_1__1__0_chany_top_out[8]:2 0.0001109382 +3 sb_1__1__0_chany_top_out[8]:3 0.0002181978 +4 sb_1__1_:chany_top_out[8] sb_1__1_:chany_top_in[9] 0.000139552 +5 cby_1__2_:chany_bottom_in[8] cby_1__2_:chany_bottom_out[9] 7.346249e-06 +6 sb_1__1__0_chany_top_out[8]:2 cby_1__1__1_chany_bottom_out[9]:3 7.346249e-06 +7 sb_1__1__0_chany_top_out[8]:3 cby_1__1__1_chany_bottom_out[9]:2 0.000139552 +8 sb_1__1_:chany_top_out[8] sb_1__1_:chany_top_in[16] 0.000139552 +9 cby_1__2_:chany_bottom_in[8] cby_1__2_:chany_bottom_out[16] 7.346249e-06 +10 sb_1__1__0_chany_top_out[8]:2 cby_1__1__1_chany_bottom_out[16]:3 7.346249e-06 +11 sb_1__1__0_chany_top_out[8]:3 cby_1__1__1_chany_bottom_out[16]:2 0.000139552 + +*RES +0 sb_1__1_:chany_top_out[8] sb_1__1__0_chany_top_out[8]:3 0.008347321 +1 sb_1__1__0_chany_top_out[8]:2 cby_1__2_:chany_bottom_in[8] 0.001491072 +2 sb_1__1__0_chany_top_out[8]:3 sb_1__1__0_chany_top_out[8]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[4] 0.001284206 //LENGTH 7.660 LUMPCC 0.0004107021 DR + +*CONN +*I sb_1__2_:chanx_left_out[4] O *L 0 *C 519.950 847.280 +*I cbx_1__2_:chanx_right_in[4] I *L 0 *C 512.290 847.280 + +*CAP +0 sb_1__2_:chanx_left_out[4] 0.0004367522 +1 cbx_1__2_:chanx_right_in[4] 0.0004367522 +2 sb_1__2_:chanx_left_out[4] sb_1__2_:chanx_left_in[14] 0.0001497812 +3 cbx_1__2_:chanx_right_in[4] cbx_1__2_:chanx_right_out[14] 0.0001497812 +4 sb_1__2_:chanx_left_out[4] sb_1__2_:chanx_left_in[16] 5.556981e-05 +5 cbx_1__2_:chanx_right_in[4] cbx_1__2_:chanx_right_out[16] 5.556981e-05 + +*RES +0 sb_1__2_:chanx_left_out[4] cbx_1__2_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[0] 0.001504953 //LENGTH 7.660 LUMPCC 0.0004854746 DR + +*CONN +*I sb_1__2_:chanx_right_out[0] O *L 0 *C 661.330 862.240 +*I cbx_2__2_:chanx_left_in[0] I *L 0 *C 668.990 862.240 +*N sb_1__2__0_chanx_right_out[0]:2 *C 667.520 862.240 +*N sb_1__2__0_chanx_right_out[0]:3 *C 667.519 862.240 + +*CAP +0 sb_1__2_:chanx_right_out[0] 0.0002897516 +1 cbx_2__2_:chanx_left_in[0] 0.0002199879 +2 sb_1__2__0_chanx_right_out[0]:2 0.0002199879 +3 sb_1__2__0_chanx_right_out[0]:3 0.0002897516 +4 sb_1__2_:chanx_right_out[0] sb_1__2_:chanx_right_in[12] 0.0001213686 +5 sb_1__2__0_chanx_right_out[0]:3 cbx_1__2__1_chanx_left_out[12]:2 0.0001213686 +6 sb_1__2_:chanx_right_out[0] sb_1__2_:chanx_right_in[19] 0.0001213686 +7 sb_1__2__0_chanx_right_out[0]:3 cbx_1__2__1_chanx_left_out[19]:2 0.0001213686 + +*RES +0 sb_1__2_:chanx_right_out[0] sb_1__2__0_chanx_right_out[0]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[0]:2 cbx_2__2_:chanx_left_in[0] 0.0002303 +2 sb_1__2__0_chanx_right_out[0]:3 sb_1__2__0_chanx_right_out[0]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[15] 0.001405733 //LENGTH 7.660 LUMPCC 0.0005770607 DR + +*CONN +*I sb_1__2_:chanx_right_out[15] O *L 0 *C 661.330 856.800 +*I cbx_2__2_:chanx_left_in[15] I *L 0 *C 668.990 856.800 +*N sb_1__2__0_chanx_right_out[15]:2 *C 667.520 856.800 +*N sb_1__2__0_chanx_right_out[15]:3 *C 667.519 856.800 + +*CAP +0 sb_1__2_:chanx_right_out[15] 0.0002395818 +1 cbx_2__2_:chanx_left_in[15] 0.0001747544 +2 sb_1__2__0_chanx_right_out[15]:2 0.0001747544 +3 sb_1__2__0_chanx_right_out[15]:3 0.0002395818 +4 sb_1__2_:chanx_right_out[15] sb_1__2_:chanx_right_out[11] 0.0001338862 +5 cbx_2__2_:chanx_left_in[15] cbx_2__2_:chanx_left_in[11] 9.866816e-06 +6 sb_1__2__0_chanx_right_out[15]:2 sb_1__2__0_chanx_right_out[11]:2 9.866816e-06 +7 sb_1__2__0_chanx_right_out[15]:3 sb_1__2__0_chanx_right_out[11]:3 0.0001338862 +8 sb_1__2_:chanx_right_out[15] sb_1__2_:chanx_right_out[13] 0.0001349142 +9 cbx_2__2_:chanx_left_in[15] cbx_2__2_:chanx_left_in[13] 9.863077e-06 +10 sb_1__2__0_chanx_right_out[15]:2 sb_1__2__0_chanx_right_out[13]:2 9.863077e-06 +11 sb_1__2__0_chanx_right_out[15]:3 sb_1__2__0_chanx_right_out[13]:3 0.0001349142 + +*RES +0 sb_1__2_:chanx_right_out[15] sb_1__2__0_chanx_right_out[15]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[15]:2 cbx_2__2_:chanx_left_in[15] 0.0002303 +2 sb_1__2__0_chanx_right_out[15]:3 sb_1__2__0_chanx_right_out[15]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[13] 0.001279574 //LENGTH 11.020 LUMPCC 0.0005195668 DR + +*CONN +*I sb_1__2_:chany_bottom_out[13] O *L 0 *C 581.440 788.870 +*I cby_1__2_:chany_top_in[13] I *L 0 *C 581.440 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[13] 0.0003800038 +1 cby_1__2_:chany_top_in[13] 0.0003800038 +2 sb_1__2_:chany_bottom_out[13] sb_1__2_:chany_bottom_in[10] 0.0001298917 +3 cby_1__2_:chany_top_in[13] cby_1__2_:chany_top_out[10] 0.0001298917 +4 sb_1__2_:chany_bottom_out[13] sb_1__2_:chany_bottom_out[7] 0.0001298917 +5 cby_1__2_:chany_top_in[13] cby_1__2_:chany_top_in[7] 0.0001298917 + +*RES +0 sb_1__2_:chany_bottom_out[13] cby_1__2_:chany_top_in[13] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[5] 0.00149709 //LENGTH 7.660 LUMPCC 0.0004471476 DR + +*CONN +*I sb_2__0_:chanx_left_out[5] O *L 0 *C 781.230 354.960 +*I cbx_2__0_:chanx_right_in[5] I *L 0 *C 773.570 354.960 + +*CAP +0 sb_2__0_:chanx_left_out[5] 0.0005249709 +1 cbx_2__0_:chanx_right_in[5] 0.0005249709 +2 sb_2__0_:chanx_left_out[5] sb_2__0_:chanx_left_in[4] 9.790535e-05 +3 cbx_2__0_:chanx_right_in[5] cbx_1__0__1_chanx_right_out[4]:2 9.790535e-05 +4 sb_2__0_:chanx_left_out[5] sb_2__0_:chanx_left_out[3] 0.0001256684 +5 cbx_2__0_:chanx_right_in[5] cbx_2__0_:chanx_right_in[3] 0.0001256684 + +*RES +0 sb_2__0_:chanx_left_out[5] cbx_2__0_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[18] 0.001426293 //LENGTH 7.660 LUMPCC 0.0003252477 DR + +*CONN +*I sb_2__0_:chanx_left_out[18] O *L 0 *C 781.230 303.960 +*I cbx_2__0_:chanx_right_in[18] I *L 0 *C 773.570 303.960 + +*CAP +0 sb_2__0_:chanx_left_out[18] 0.0005505228 +1 cbx_2__0_:chanx_right_in[18] 0.0005505228 +2 sb_2__0_:chanx_left_out[18] sb_2__0_:chanx_left_in[14] 4.600756e-05 +3 cbx_2__0_:chanx_right_in[18] cbx_2__0_:chanx_right_out[14] 4.600756e-05 +4 sb_2__0_:chanx_left_out[18] sb_2__0_:chanx_left_out[4] 0.0001166163 +5 cbx_2__0_:chanx_right_in[18] cbx_2__0_:chanx_right_in[4] 0.0001166163 + +*RES +0 sb_2__0_:chanx_left_out[18] cbx_2__0_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[14] 0.001193176 //LENGTH 11.020 LUMPCC 0.0004809881 DR + +*CONN +*I sb_2__0_:chany_top_out[14] O *L 0 *C 878.600 397.050 +*I cby_2__1_:chany_bottom_in[14] I *L 0 *C 878.600 408.070 + +*CAP +0 sb_2__0_:chany_top_out[14] 0.0003560942 +1 cby_2__1_:chany_bottom_in[14] 0.0003560942 +2 sb_2__0_:chany_top_out[14] sb_2__0_:chany_top_out[4] 9.084754e-05 +3 cby_2__1_:chany_bottom_in[14] cby_2__1_:chany_bottom_in[4] 9.084754e-05 +4 sb_2__0_:chany_top_out[14] sb_2__0_:chany_top_out[10] 0.0001496465 +5 cby_2__1_:chany_bottom_in[14] cby_2__1_:chany_bottom_in[10] 0.0001496465 + +*RES +0 sb_2__0_:chany_top_out[14] cby_2__1_:chany_bottom_in[14] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[11] 0.001538338 //LENGTH 7.660 LUMPCC 0.0002689551 DR + +*CONN +*I sb_2__1_:chanx_left_out[11] O *L 0 *C 781.230 624.240 +*I cbx_2__1_:chanx_right_in[11] I *L 0 *C 773.570 624.240 + +*CAP +0 sb_2__1_:chanx_left_out[11] 0.0006346917 +1 cbx_2__1_:chanx_right_in[11] 0.0006346917 +2 sb_2__1_:chanx_left_out[11] sb_2__1_:chanx_left_in[12] 9.562019e-05 +3 cbx_2__1_:chanx_right_in[11] cbx_2__1_:chanx_right_out[12] 9.562019e-05 +4 sb_2__1_:chanx_left_out[11] sb_2__1_:chanx_left_in[13] 3.885734e-05 +5 cbx_2__1_:chanx_right_in[11] cbx_2__1_:chanx_right_out[13] 3.885734e-05 + +*RES +0 sb_2__1_:chanx_left_out[11] cbx_2__1_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[6] 0.001274831 //LENGTH 11.020 LUMPCC 0.0005352615 DR + +*CONN +*I sb_2__1_:chany_bottom_out[6] O *L 0 *C 856.060 527.750 +*I cby_2__1_:chany_top_in[6] I *L 0 *C 856.060 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[6] 0.0003697848 +1 cby_2__1_:chany_top_in[6] 0.0003697848 +2 sb_2__1_:chany_bottom_out[6] sb_2__1_:chany_bottom_in[5] 0.0001337766 +3 cby_2__1_:chany_top_in[6] cby_2__1_:chany_top_out[5] 0.0001337766 +4 sb_2__1_:chany_bottom_out[6] sb_2__1_:chany_bottom_out[11] 0.0001338541 +5 cby_2__1_:chany_top_in[6] cby_2__1_:chany_top_in[11] 0.0001338541 + +*RES +0 sb_2__1_:chany_bottom_out[6] cby_2__1_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[4] 0.001147902 //LENGTH 11.020 LUMPCC 0.0001676726 DR + +*CONN +*I sb_2__1_:chany_top_out[4] O *L 0 *C 879.980 658.170 +*I cby_2__2_:chany_bottom_in[4] I *L 0 *C 879.980 669.190 +*N sb_2__1__0_chany_top_out[4]:2 *C 879.980 667.520 +*N sb_2__1__0_chany_top_out[4]:3 *C 879.980 667.519 + +*CAP +0 sb_2__1_:chany_top_out[4] 0.0003643539 +1 cby_2__2_:chany_bottom_in[4] 0.0001257606 +2 sb_2__1__0_chany_top_out[4]:2 0.0001257606 +3 sb_2__1__0_chany_top_out[4]:3 0.0003643539 +4 sb_2__1_:chany_top_out[4] sb_2__1_:chany_top_out[14] 8.235022e-05 +5 cby_2__2_:chany_bottom_in[4] cby_2__2_:chany_bottom_in[14] 1.486063e-06 +6 sb_2__1__0_chany_top_out[4]:2 sb_2__1__0_chany_top_out[14]:2 1.486063e-06 +7 sb_2__1__0_chany_top_out[4]:3 sb_2__1__0_chany_top_out[14]:3 8.235022e-05 + +*RES +0 sb_2__1_:chany_top_out[4] sb_2__1__0_chany_top_out[4]:3 0.008347322 +1 sb_2__1__0_chany_top_out[4]:2 cby_2__2_:chany_bottom_in[4] 0.001491072 +2 sb_2__1__0_chany_top_out[4]:3 sb_2__1__0_chany_top_out[4]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[19] 0.001255388 //LENGTH 11.020 LUMPCC 0.0005531847 DR + +*CONN +*I sb_2__1_:chany_top_out[19] O *L 0 *C 859.740 658.170 +*I cby_2__2_:chany_bottom_in[19] I *L 0 *C 859.740 669.190 +*N sb_2__1__0_chany_top_out[19]:2 *C 859.740 667.520 +*N sb_2__1__0_chany_top_out[19]:3 *C 859.740 667.519 + +*CAP +0 sb_2__1_:chany_top_out[19] 0.0002401642 +1 cby_2__2_:chany_bottom_in[19] 0.0001109373 +2 sb_2__1__0_chany_top_out[19]:2 0.0001109373 +3 sb_2__1__0_chany_top_out[19]:3 0.0002401642 +4 sb_2__1_:chany_top_out[19] sb_2__1_:chany_top_out[2] 0.0001309558 +5 cby_2__2_:chany_bottom_in[19] cby_2__2_:chany_bottom_in[2] 7.340376e-06 +6 sb_2__1__0_chany_top_out[19]:2 sb_2__1__0_chany_top_out[2]:2 7.340376e-06 +7 sb_2__1__0_chany_top_out[19]:3 sb_2__1__0_chany_top_out[2]:3 0.0001309558 +8 sb_2__1_:chany_top_out[19] sb_2__1_:chany_top_out[12] 0.0001309558 +9 cby_2__2_:chany_bottom_in[19] cby_2__2_:chany_bottom_in[12] 7.340376e-06 +10 sb_2__1__0_chany_top_out[19]:2 sb_2__1__0_chany_top_out[12]:2 7.340376e-06 +11 sb_2__1__0_chany_top_out[19]:3 sb_2__1__0_chany_top_out[12]:3 0.0001309558 + +*RES +0 sb_2__1_:chany_top_out[19] sb_2__1__0_chany_top_out[19]:3 0.008347321 +1 sb_2__1__0_chany_top_out[19]:2 cby_2__2_:chany_bottom_in[19] 0.001491072 +2 sb_2__1__0_chany_top_out[19]:3 sb_2__1__0_chany_top_out[19]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[0] 0.001259665 //LENGTH 11.020 LUMPCC 0.0005582116 DR + +*CONN +*I sb_2__2_:chany_bottom_out[0] O *L 0 *C 864.340 788.870 +*I cby_2__2_:chany_top_in[0] I *L 0 *C 864.340 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[0] 0.0003507265 +1 cby_2__2_:chany_top_in[0] 0.0003507265 +2 sb_2__2_:chany_bottom_out[0] sb_2__2_:chany_bottom_in[0] 0.0001395529 +3 cby_2__2_:chany_top_in[0] cby_2__2_:chany_top_out[0] 0.0001395529 +4 sb_2__2_:chany_bottom_out[0] sb_2__2_:chany_bottom_in[9] 0.0001395529 +5 cby_2__2_:chany_top_in[0] cby_2__2_:chany_top_out[9] 0.0001395529 + +*RES +0 sb_2__2_:chany_bottom_out[0] cby_2__2_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[16] 0.001236644 //LENGTH 11.020 LUMPCC 0.000587663 DR + +*CONN +*I sb_2__2_:chany_bottom_out[16] O *L 0 *C 845.480 788.870 +*I cby_2__2_:chany_top_in[16] I *L 0 *C 845.480 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[16] 0.0003244906 +1 cby_2__2_:chany_top_in[16] 0.0003244906 +2 sb_2__2_:chany_bottom_out[16] sb_2__2_:chany_bottom_in[4] 0.0001469158 +3 cby_2__2_:chany_top_in[16] cby_2__2_:chany_top_out[4] 0.0001469158 +4 sb_2__2_:chany_bottom_out[16] sb_2__2_:chany_bottom_out[8] 0.0001469158 +5 cby_2__2_:chany_top_in[16] cby_2__2_:chany_top_in[8] 0.0001469158 + +*RES +0 sb_2__2_:chany_bottom_out[16] cby_2__2_:chany_top_in[16] 0.009839286 + +*END + +*D_NET ctsbuf_net_1221 0.05181983 //LENGTH 404.490 LUMPCC 0.01632402 DR + +*CONN +*I cts_inv_73617636:Y O *L 0 *C 636.640 546.040 +*I grid_io_right_3__2_:prog_clk[0] I *L 0 *C 911.260 669.190 +*I sb_2__1_:prog_clk[0] I *L 0 *C 783.380 554.950 +*N ctsbuf_net_1221:3 *C 783.380 554.258 +*N ctsbuf_net_1221:4 *C 783.373 554.200 +*N ctsbuf_net_1221:5 *C 911.260 667.520 +*N ctsbuf_net_1221:6 *C 911.260 667.519 +*N ctsbuf_net_1221:7 *C 911.260 660.337 +*N ctsbuf_net_1221:8 *C 911.253 660.280 +*N ctsbuf_net_1221:9 *C 903.455 660.280 +*N ctsbuf_net_1221:10 *C 891.520 660.280 +*N ctsbuf_net_1221:11 *C 891.519 660.280 +*N ctsbuf_net_1221:12 *C 853.455 660.280 +*N ctsbuf_net_1221:13 *C 803.628 660.280 +*N ctsbuf_net_1221:14 *C 803.620 660.223 +*N ctsbuf_net_1221:15 *C 803.620 633.138 +*N ctsbuf_net_1221:16 *C 803.613 633.080 +*N ctsbuf_net_1221:17 *C 780.168 633.080 +*N ctsbuf_net_1221:18 *C 780.160 633.023 +*N ctsbuf_net_1221:19 *C 780.160 604.015 +*N ctsbuf_net_1221:20 *C 780.160 554.258 +*N ctsbuf_net_1221:21 *C 780.160 554.200 +*N ctsbuf_net_1221:22 *C 739.235 554.200 +*N ctsbuf_net_1221:23 *C 689.235 554.200 +*N ctsbuf_net_1221:24 *C 667.520 554.200 +*N ctsbuf_net_1221:25 *C 667.519 554.200 +*N ctsbuf_net_1221:26 *C 639.408 554.200 +*N ctsbuf_net_1221:27 *C 639.400 554.143 +*N ctsbuf_net_1221:28 *C 639.400 546.085 +*N ctsbuf_net_1221:29 *C 639.355 546.040 +*N ctsbuf_net_1221:30 *C 636.678 546.040 + +*CAP +0 cts_inv_73617636:Y 1e-06 +1 grid_io_right_3__2_:prog_clk[0] 0.0001287729 +2 sb_2__1_:prog_clk[0] 5.121407e-05 +3 ctsbuf_net_1221:3 5.121407e-05 +4 ctsbuf_net_1221:4 0.0001992049 +5 ctsbuf_net_1221:5 0.0001287729 +6 ctsbuf_net_1221:6 0.0003181255 +7 ctsbuf_net_1221:7 0.0003181255 +8 ctsbuf_net_1221:8 0.0001456685 +9 ctsbuf_net_1221:9 0.0003225949 +10 ctsbuf_net_1221:10 0.0001769264 +11 ctsbuf_net_1221:11 0.001320468 +12 ctsbuf_net_1221:12 0.002989105 +13 ctsbuf_net_1221:13 0.001668637 +14 ctsbuf_net_1221:14 0.001283588 +15 ctsbuf_net_1221:15 0.001283588 +16 ctsbuf_net_1221:16 0.001225587 +17 ctsbuf_net_1221:17 0.001225587 +18 ctsbuf_net_1221:18 0.001327775 +19 ctsbuf_net_1221:19 0.003569316 +20 ctsbuf_net_1221:20 0.00224154 +21 ctsbuf_net_1221:21 0.002276069 +22 ctsbuf_net_1221:22 0.004607112 +23 ctsbuf_net_1221:23 0.00365408 +24 ctsbuf_net_1221:24 0.001123831 +25 ctsbuf_net_1221:25 0.001333955 +26 ctsbuf_net_1221:26 0.001333955 +27 ctsbuf_net_1221:27 0.0003462429 +28 ctsbuf_net_1221:28 0.0003462429 +29 ctsbuf_net_1221:29 0.0002487509 +30 ctsbuf_net_1221:30 0.0002487509 +31 ctsbuf_net_1221:20 clk[0]:47 0.0006256229 +32 ctsbuf_net_1221:20 clk[0]:48 1.766467e-05 +33 ctsbuf_net_1221:21 clk[0]:46 0.0007832176 +34 ctsbuf_net_1221:18 clk[0]:49 0.0003816097 +35 ctsbuf_net_1221:13 clk[0]:54 0.001108246 +36 ctsbuf_net_1221:8 clk[0]:58 0.0001194283 +37 ctsbuf_net_1221:8 clk[0]:59 8.869322e-05 +38 ctsbuf_net_1221:27 clk[0]:40 9.536724e-05 +39 ctsbuf_net_1221:26 clk[0]:41 0.0006011912 +40 ctsbuf_net_1221:28 clk[0]:39 9.536724e-05 +41 ctsbuf_net_1221:19 clk[0]:48 0.001007233 +42 ctsbuf_net_1221:19 clk[0]:49 1.766467e-05 +43 ctsbuf_net_1221:23 clk[0]:44 0.001512426 +44 ctsbuf_net_1221:23 clk[0]:45 4.512586e-05 +45 ctsbuf_net_1221:22 clk[0]:45 0.001956793 +46 ctsbuf_net_1221:22 clk[0]:46 2.252895e-05 +47 ctsbuf_net_1221:12 clk[0]:54 0.0001008271 +48 ctsbuf_net_1221:12 clk[0]:55 0.001919396 +49 ctsbuf_net_1221:9 clk[0]:57 0.0001194283 +50 ctsbuf_net_1221:9 clk[0]:58 0.0004017234 +51 ctsbuf_net_1221:24 clk[0]:43 0.0003388506 +52 ctsbuf_net_1221:24 clk[0]:44 2.259691e-05 +53 ctsbuf_net_1221:25 clk[0]:42 0.0006011912 +54 ctsbuf_net_1221:10 clk[0]:57 0.0003130302 +55 ctsbuf_net_1221:11 clk[0]:55 0.0001008271 +56 ctsbuf_net_1221:11 clk[0]:56 0.0008111507 +57 ctsbuf_net_1221:26 cbx_1__1__1_chanx_left_out[0]:5 0.0001663756 +58 ctsbuf_net_1221:23 cbx_1__1__1_chanx_left_out[0]:8 0.0003375046 +59 ctsbuf_net_1221:24 cbx_1__1__1_chanx_left_out[0]:7 0.0003375046 +60 ctsbuf_net_1221:25 cbx_1__1__1_chanx_left_out[0]:6 0.0001663756 +61 ctsbuf_net_1221:20 cbx_1__1__1_chanx_right_out[11]:3 5.671138e-05 +62 ctsbuf_net_1221:19 cbx_1__1__1_chanx_right_out[11]:2 5.671138e-05 +63 ctsbuf_net_1221:21 cbx_1__1__1_chanx_right_out[19]:5 0.0003476924 +64 ctsbuf_net_1221:22 cbx_1__1__1_chanx_right_out[19]:6 0.0003476924 +65 ctsbuf_net_1221:13 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 5.851133e-05 +66 ctsbuf_net_1221:12 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 5.851133e-05 +67 ctsbuf_net_1221:13 grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] 2.06856e-05 +68 ctsbuf_net_1221:12 sb_2__1_:top_left_grid_pin_36_[0] 2.06856e-05 +69 ctsbuf_net_1221:7 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:7 3.804012e-05 +70 ctsbuf_net_1221:8 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 0.0001602069 +71 ctsbuf_net_1221:12 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 5.965147e-05 +72 ctsbuf_net_1221:9 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 0.0001602069 +73 ctsbuf_net_1221:9 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 0.0003130302 +74 ctsbuf_net_1221:6 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:8 3.804012e-05 +75 ctsbuf_net_1221:10 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 0.0003130302 +76 ctsbuf_net_1221:11 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 5.965147e-05 + +*RES +0 cts_inv_73617636:Y ctsbuf_net_1221:30 0.152 +1 ctsbuf_net_1221:20 ctsbuf_net_1221:19 0.04442634 +2 ctsbuf_net_1221:21 ctsbuf_net_1221:20 0.00341 +3 ctsbuf_net_1221:21 ctsbuf_net_1221:4 0.0005032917 +4 ctsbuf_net_1221:18 ctsbuf_net_1221:17 0.00341 +5 ctsbuf_net_1221:17 ctsbuf_net_1221:16 0.00367305 +6 ctsbuf_net_1221:15 ctsbuf_net_1221:14 0.02418304 +7 ctsbuf_net_1221:16 ctsbuf_net_1221:15 0.00341 +8 ctsbuf_net_1221:14 ctsbuf_net_1221:13 0.00341 +9 ctsbuf_net_1221:13 ctsbuf_net_1221:12 0.007806308 +10 ctsbuf_net_1221:7 ctsbuf_net_1221:6 0.006412054 +11 ctsbuf_net_1221:8 ctsbuf_net_1221:7 0.00341 +12 ctsbuf_net_1221:3 sb_2__1_:prog_clk[0] 0.0006183035 +13 ctsbuf_net_1221:4 ctsbuf_net_1221:3 0.00341 +14 ctsbuf_net_1221:27 ctsbuf_net_1221:26 0.00341 +15 ctsbuf_net_1221:26 ctsbuf_net_1221:25 0.004404135 +16 ctsbuf_net_1221:29 ctsbuf_net_1221:28 0.0045 +17 ctsbuf_net_1221:28 ctsbuf_net_1221:27 0.007194197 +18 ctsbuf_net_1221:30 ctsbuf_net_1221:29 0.002390625 +19 ctsbuf_net_1221:19 ctsbuf_net_1221:18 0.02589956 +20 ctsbuf_net_1221:23 ctsbuf_net_1221:22 0.007833333 +21 ctsbuf_net_1221:22 ctsbuf_net_1221:21 0.006411583 +22 ctsbuf_net_1221:12 ctsbuf_net_1221:11 0.005963359 +23 ctsbuf_net_1221:9 ctsbuf_net_1221:8 0.001221608 +24 ctsbuf_net_1221:5 grid_io_right_3__2_:prog_clk[0] 0.001491072 +25 ctsbuf_net_1221:6 ctsbuf_net_1221:5 1e-05 +26 ctsbuf_net_1221:24 ctsbuf_net_1221:23 0.003402017 +27 ctsbuf_net_1221:25 ctsbuf_net_1221:24 1e-05 +28 ctsbuf_net_1221:10 ctsbuf_net_1221:9 0.001869817 +29 ctsbuf_net_1221:11 ctsbuf_net_1221:10 1e-05 + +*END + +*D_NET clk[0] 0.2305216 //LENGTH 2239.905 LUMPCC 0.02780011 DR + +*CONN +*P clk[0] I *L 0 *C 1199.155 602.480 +*I grid_clb_2__1_:clk[0] I *L 0 *C 802.090 519.520 +*I grid_clb_1__1_:clk[0] I *L 0 *C 540.810 519.520 +*I grid_clb_1__2_:clk[0] I *L 0 *C 540.810 780.640 +*I grid_clb_2__2_:clk[0] I *L 0 *C 802.090 780.640 +*N clk[0]:5 *C 852.090 780.640 +*N clk[0]:6 *C 891.519 780.640 +*N clk[0]:7 *C 891.520 780.640 +*N clk[0]:8 *C 902.090 780.640 +*N clk[0]:9 *C 952.090 780.640 +*N clk[0]:10 *C 1002.090 780.640 +*N clk[0]:11 *C 1052.090 780.640 +*N clk[0]:12 *C 1102.090 780.640 +*N clk[0]:13 *C 1115.519 780.640 +*N clk[0]:14 *C 1115.520 780.640 +*N clk[0]:15 *C 1152.090 780.640 +*N clk[0]:16 *C 1199.213 780.640 +*N clk[0]:17 *C 1199.220 780.582 +*N clk[0]:18 *C 1199.220 758.920 +*N clk[0]:19 *C 1199.220 708.920 +*N clk[0]:20 *C 1199.220 667.520 +*N clk[0]:21 *C 1199.220 667.519 +*N clk[0]:22 *C 545.100 780.640 +*N clk[0]:23 *C 545.100 779.960 +*N clk[0]:24 *C 594.950 779.960 +*N clk[0]:25 *C 637.553 779.960 +*N clk[0]:26 *C 637.560 779.903 +*N clk[0]:27 *C 637.560 740.375 +*N clk[0]:28 *C 637.560 690.375 +*N clk[0]:29 *C 637.560 667.520 +*N clk[0]:30 *C 637.560 667.519 +*N clk[0]:31 *C 637.560 640.618 +*N clk[0]:32 *C 637.567 640.560 +*N clk[0]:33 *C 667.519 640.560 +*N clk[0]:34 *C 667.520 640.560 +*N clk[0]:35 *C 687.395 640.560 +*N clk[0]:36 *C 737.395 640.560 +*N clk[0]:37 *C 590.810 519.520 +*N clk[0]:38 *C 638.473 519.520 +*N clk[0]:39 *C 638.480 519.577 +*N clk[0]:40 *C 638.480 552.783 +*N clk[0]:41 *C 638.488 552.840 +*N clk[0]:42 *C 667.519 552.840 +*N clk[0]:43 *C 667.520 552.840 +*N clk[0]:44 *C 688.315 552.840 +*N clk[0]:45 *C 738.315 552.840 +*N clk[0]:46 *C 779.233 552.840 +*N clk[0]:47 *C 779.240 552.898 +*N clk[0]:48 *C 779.240 602.655 +*N clk[0]:49 *C 779.240 640.503 +*N clk[0]:50 *C 779.240 640.560 +*N clk[0]:51 *C 808.213 640.560 +*N clk[0]:52 *C 808.220 640.618 +*N clk[0]:53 *C 808.220 658.863 +*N clk[0]:54 *C 808.228 658.920 +*N clk[0]:55 *C 858.055 658.920 +*N clk[0]:56 *C 891.519 658.920 +*N clk[0]:57 *C 891.520 658.920 +*N clk[0]:58 *C 908.055 658.920 +*N clk[0]:59 *C 958.055 658.920 +*N clk[0]:60 *C 1008.055 658.920 +*N clk[0]:61 *C 1058.055 658.920 +*N clk[0]:62 *C 1108.055 658.920 +*N clk[0]:63 *C 1115.519 658.920 +*N clk[0]:64 *C 1115.520 658.920 +*N clk[0]:65 *C 1158.055 658.920 +*N clk[0]:66 *C 1199.213 658.920 +*N clk[0]:67 *C 1199.220 658.920 +*N clk[0]:68 *C 1199.220 652.480 +*N clk[0]:69 *C 852.090 519.520 +*N clk[0]:70 *C 891.519 519.520 +*N clk[0]:71 *C 891.520 519.520 +*N clk[0]:72 *C 902.090 519.520 +*N clk[0]:73 *C 952.090 519.520 +*N clk[0]:74 *C 1002.090 519.520 +*N clk[0]:75 *C 1052.090 519.520 +*N clk[0]:76 *C 1102.090 519.520 +*N clk[0]:77 *C 1115.519 519.520 +*N clk[0]:78 *C 1115.520 519.520 +*N clk[0]:79 *C 1152.090 519.520 +*N clk[0]:80 *C 1199.213 519.520 +*N clk[0]:81 *C 1199.220 519.577 +*N clk[0]:82 *C 1199.220 569.335 +*N clk[0]:83 *C 1199.220 602.480 +*N clk[0]:84 *C 1199.213 602.480 +*N clk[0]:85 *C 1197.388 602.480 +*N clk[0]:86 *C 1197.380 602.480 +*N clk[0]:87 *C 1197.425 602.480 + +*CAP +0 clk[0] 9.350451e-05 +1 grid_clb_2__1_:clk[0] 0.003293061 +2 grid_clb_1__1_:clk[0] 0.003151383 +3 grid_clb_1__2_:clk[0] 0.0003409624 +4 grid_clb_2__2_:clk[0] 0.002068445 +5 clk[0]:5 0.003782326 +6 clk[0]:6 0.001713881 +7 clk[0]:7 0.0003275914 +8 clk[0]:8 0.002574955 +9 clk[0]:9 0.004462189 +10 clk[0]:10 0.004420923 +11 clk[0]:11 0.004420891 +12 clk[0]:12 0.00280664 +13 clk[0]:13 0.0005918466 +14 clk[0]:14 0.001612561 +15 clk[0]:15 0.003705753 +16 clk[0]:16 0.002093191 +17 clk[0]:17 0.0009211076 +18 clk[0]:18 0.003026995 +19 clk[0]:19 0.003829486 +20 clk[0]:20 0.001723598 +21 clk[0]:21 0.0003833936 +22 clk[0]:22 0.0003997795 +23 clk[0]:23 0.002270234 +24 clk[0]:24 0.004154827 +25 clk[0]:25 0.00194341 +26 clk[0]:26 0.00171157 +27 clk[0]:27 0.00383376 +28 clk[0]:28 0.003085146 +29 clk[0]:29 0.0009629567 +30 clk[0]:30 0.001196182 +31 clk[0]:31 0.001196182 +32 clk[0]:32 0.001629918 +33 clk[0]:33 0.001629918 +34 clk[0]:34 0.001135879 +35 clk[0]:35 0.003852156 +36 clk[0]:36 0.005035875 +37 clk[0]:37 0.00618376 +38 clk[0]:38 0.003032377 +39 clk[0]:39 0.001247966 +40 clk[0]:40 0.001247966 +41 clk[0]:41 0.0007833289 +42 clk[0]:42 0.0007833289 +43 clk[0]:43 0.0006275469 +44 clk[0]:44 0.002164851 +45 clk[0]:45 0.002837019 +46 clk[0]:46 0.001299716 +47 clk[0]:47 0.001819373 +48 clk[0]:48 0.003309275 +49 clk[0]:49 0.001489902 +50 clk[0]:50 0.00391882 +51 clk[0]:51 0.001599222 +52 clk[0]:52 0.0009863449 +53 clk[0]:53 0.0009863449 +54 clk[0]:54 0.002407083 +55 clk[0]:55 0.004047694 +56 clk[0]:56 0.001640612 +57 clk[0]:57 0.0005282573 +58 clk[0]:58 0.002540587 +59 clk[0]:59 0.004073658 +60 clk[0]:60 0.004116574 +61 clk[0]:61 0.004114759 +62 clk[0]:62 0.002366422 +63 clk[0]:63 0.0003069089 +64 clk[0]:64 0.001748674 +65 clk[0]:65 0.003459033 +66 clk[0]:66 0.001710359 +67 clk[0]:67 0.0007150733 +68 clk[0]:68 0.002554738 +69 clk[0]:69 0.006059312 +70 clk[0]:70 0.002766251 +71 clk[0]:71 0.0005281819 +72 clk[0]:72 0.003059054 +73 clk[0]:73 0.004734077 +74 clk[0]:74 0.004401035 +75 clk[0]:75 0.004401525 +76 clk[0]:76 0.002791959 +77 clk[0]:77 0.0005882625 +78 clk[0]:78 0.001605945 +79 clk[0]:79 0.003685948 +80 clk[0]:80 0.002080003 +81 clk[0]:81 0.002246072 +82 clk[0]:82 0.003734324 +83 clk[0]:83 0.003774339 +84 clk[0]:84 5.332289e-05 +85 clk[0]:85 5.332289e-05 +86 clk[0]:86 3.499532e-05 +87 clk[0]:87 9.350451e-05 +88 clk[0] Test_en[0] 1.232618e-05 +89 grid_clb_2__2_:clk[0] grid_clb_2__2_:Test_en[0] 5.069699e-05 +90 grid_clb_2__2_:clk[0] Test_en[0]:24 0.0008642827 +91 grid_clb_1__2_:clk[0] grid_clb_1__2_:Test_en[0] 4.768238e-06 +92 grid_clb_1__2_:clk[0] Test_en[0]:8 6.999164e-07 +93 clk[0]:40 Test_en[0]:47 1.189506e-06 +94 clk[0]:39 Test_en[0]:46 1.189506e-06 +95 clk[0]:84 Test_en[0]:78 9.815069e-05 +96 clk[0]:85 Test_en[0]:77 9.815069e-05 +97 clk[0]:87 Test_en[0]:80 1.232618e-05 +98 clk[0]:22 Test_en[0]:5 4.768238e-06 +99 clk[0]:22 Test_en[0]:9 6.999164e-07 +100 clk[0]:5 Test_en[0]:21 5.069699e-05 +101 clk[0]:5 Test_en[0]:24 2.91031e-05 +102 clk[0]:5 Test_en[0]:25 0.001494469 +103 clk[0]:8 Test_en[0]:27 3.704762e-05 +104 clk[0]:8 Test_en[0]:28 0.0002519766 +105 clk[0]:9 Test_en[0]:28 3.704762e-05 +106 clk[0]:7 Test_en[0]:27 0.0002519766 +107 clk[0]:6 Test_en[0]:25 2.91031e-05 +108 clk[0]:6 Test_en[0]:26 0.0006301859 +109 clk[0]:41 cbx_1__1__1_chanx_left_out[0]:5 0.0001663756 +110 clk[0]:44 cbx_1__1__1_chanx_left_out[0]:8 0.0003375046 +111 clk[0]:43 cbx_1__1__1_chanx_left_out[0]:7 0.0003375046 +112 clk[0]:42 cbx_1__1__1_chanx_left_out[0]:6 0.0001663756 +113 clk[0]:41 cbx_1__1__1_chanx_left_out[13]:5 0.0001224029 +114 clk[0]:44 cbx_1__1__1_chanx_left_out[13]:8 0.0001768981 +115 clk[0]:43 cbx_1__1__1_chanx_left_out[13]:7 0.0001768981 +116 clk[0]:42 cbx_1__1__1_chanx_left_out[13]:6 0.0001224029 +117 clk[0]:47 cbx_1__1__1_chanx_right_out[2]:4 9.813355e-05 +118 clk[0]:48 cbx_1__1__1_chanx_right_out[2]:3 9.813355e-05 +119 clk[0]:47 cbx_1__1__1_chanx_right_out[11]:3 5.783038e-05 +120 clk[0]:48 cbx_1__1__1_chanx_right_out[11]:2 5.783038e-05 +121 clk[0]:47 cbx_1__1__1_chanx_right_out[16]:4 7.146557e-06 +122 clk[0]:46 cbx_1__1__1_chanx_right_out[16]:5 0.0001922867 +123 clk[0]:48 cbx_1__1__1_chanx_right_out[16]:3 7.146557e-06 +124 clk[0]:45 cbx_1__1__1_chanx_right_out[16]:6 0.0001922867 +125 clk[0]:46 cbx_1__1__1_chanx_right_out[19]:5 0.0003476924 +126 clk[0]:45 cbx_1__1__1_chanx_right_out[19]:6 0.0003476924 +127 clk[0]:49 direct_interc_1_out[0]:7 3.526572e-05 +128 clk[0]:49 direct_interc_1_out[0]:3 8.818282e-05 +129 clk[0]:47 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 5.193616e-05 +130 clk[0]:47 direct_interc_1_out[0]:2 2.093162e-05 +131 clk[0]:48 direct_interc_1_out[0]:6 3.526572e-05 +132 clk[0]:48 direct_interc_1_out[0]:3 2.093162e-05 +133 clk[0]:48 direct_interc_1_out[0]:2 0.000140119 +134 clk[0]:31 direct_interc_2_out[0]:16 2.7726e-05 +135 clk[0]:26 direct_interc_2_out[0]:11 7.767113e-05 +136 clk[0]:41 direct_interc_2_out[0]:25 0.0003100793 +137 clk[0]:28 direct_interc_2_out[0]:13 0.0001295701 +138 clk[0]:28 direct_interc_2_out[0]:12 1.942522e-05 +139 clk[0]:27 direct_interc_2_out[0]:12 0.0001695974 +140 clk[0]:27 direct_interc_2_out[0]:11 1.003389e-05 +141 clk[0]:29 direct_interc_2_out[0]:13 9.391332e-06 +142 clk[0]:29 direct_interc_2_out[0]:14 3.764384e-05 +143 clk[0]:30 direct_interc_2_out[0]:15 2.7726e-05 +144 clk[0]:42 direct_interc_2_out[0]:24 0.0003100793 +145 clk[0]:51 sb_2__1_:top_left_grid_pin_41_[0] 2.787808e-05 +146 clk[0]:50 grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] 2.787808e-05 +147 clk[0]:38 sb_1__1__0_chany_bottom_out[14]:7 2.332518e-05 +148 clk[0]:38 sb_1__1__0_chany_bottom_out[14]:2 9.325306e-06 +149 clk[0]:37 sb_1__1__0_chany_bottom_out[14]:4 9.325306e-06 +150 clk[0]:37 sb_1__1__0_chany_bottom_out[14]:8 2.332518e-05 +151 grid_clb_1__1_:clk[0] grid_clb_1__1_:Test_en[0] 0.0001784555 +152 clk[0]:37 BUF_net_9:2 0.0001784555 +153 clk[0]:40 ctsbuf_net_413:3 5.218217e-05 +154 clk[0]:39 ctsbuf_net_413:4 5.218217e-05 +155 clk[0]:38 ctsbuf_net_413:5 3.293142e-05 +156 clk[0]:37 ctsbuf_net_413:6 3.293142e-05 +157 clk[0]:54 ctsbuf_net_1221:13 0.001108246 +158 clk[0]:54 ctsbuf_net_1221:12 0.0001008271 +159 clk[0]:49 ctsbuf_net_1221:18 0.0003816097 +160 clk[0]:49 ctsbuf_net_1221:19 1.766467e-05 +161 clk[0]:47 ctsbuf_net_1221:20 0.0006256229 +162 clk[0]:46 ctsbuf_net_1221:21 0.0007832176 +163 clk[0]:46 ctsbuf_net_1221:22 2.252895e-05 +164 clk[0]:40 ctsbuf_net_1221:27 9.536724e-05 +165 clk[0]:41 ctsbuf_net_1221:26 0.0006011912 +166 clk[0]:39 ctsbuf_net_1221:28 9.536724e-05 +167 clk[0]:48 ctsbuf_net_1221:20 1.766467e-05 +168 clk[0]:48 ctsbuf_net_1221:19 0.001007233 +169 clk[0]:44 ctsbuf_net_1221:23 0.001512426 +170 clk[0]:44 ctsbuf_net_1221:24 2.259691e-05 +171 clk[0]:45 ctsbuf_net_1221:23 4.512586e-05 +172 clk[0]:45 ctsbuf_net_1221:22 0.001956793 +173 clk[0]:55 ctsbuf_net_1221:12 0.001919396 +174 clk[0]:55 ctsbuf_net_1221:11 0.0001008271 +175 clk[0]:58 ctsbuf_net_1221:8 0.0001194283 +176 clk[0]:58 ctsbuf_net_1221:9 0.0004017234 +177 clk[0]:59 ctsbuf_net_1221:8 8.869322e-05 +178 clk[0]:43 ctsbuf_net_1221:24 0.0003388506 +179 clk[0]:42 ctsbuf_net_1221:25 0.0006011912 +180 clk[0]:57 ctsbuf_net_1221:9 0.0001194283 +181 clk[0]:57 ctsbuf_net_1221:10 0.0003130302 +182 clk[0]:56 ctsbuf_net_1221:11 0.0008111507 +183 clk[0]:46 ctsbuf_net_1928:12 0.0001986295 +184 clk[0]:40 ctsbuf_net_1928:21 0.0002256667 +185 clk[0]:40 ctsbuf_net_1928:18 2.699283e-05 +186 clk[0]:39 ctsbuf_net_1928:21 2.699283e-05 +187 clk[0]:39 ctsbuf_net_1928:22 0.0002256667 +188 clk[0]:44 ctsbuf_net_1928:14 0.0003721622 +189 clk[0]:44 ctsbuf_net_1928:13 2.057909e-05 +190 clk[0]:45 ctsbuf_net_1928:13 0.0005006063 +191 clk[0]:45 ctsbuf_net_1928:12 1.029659e-05 +192 clk[0]:43 ctsbuf_net_1928:14 1.02825e-05 +193 clk[0]:43 ctsbuf_net_1928:15 7.018542e-05 +194 grid_clb_1__1_:clk[0] ctsbuf_net_2029:33 0.0002093283 +195 clk[0]:38 ctsbuf_net_2029:31 0.0001767444 +196 clk[0]:38 ctsbuf_net_2029:27 6.657097e-06 +197 clk[0]:38 ctsbuf_net_2029:25 6.274608e-06 +198 clk[0]:38 ctsbuf_net_2029:32 5.198141e-06 +199 clk[0]:37 ctsbuf_net_2029:33 5.198141e-06 +200 clk[0]:37 ctsbuf_net_2029:31 6.657097e-06 +201 clk[0]:37 ctsbuf_net_2029:24 6.274608e-06 +202 clk[0]:37 ctsbuf_net_2029:32 0.0003860728 +203 grid_clb_1__2_:clk[0] ctsbuf_net_2130:33 1.241664e-05 +204 grid_clb_1__2_:clk[0] ctsbuf_net_2130:27 7.118451e-05 +205 clk[0]:25 ctsbuf_net_2130:25 0.0005526321 +206 clk[0]:22 ctsbuf_net_2130:34 1.241664e-05 +207 clk[0]:22 ctsbuf_net_2130:26 7.118451e-05 +208 clk[0]:23 ctsbuf_net_2130:27 0.000800427 +209 clk[0]:23 ctsbuf_net_2130:26 3.997418e-05 +210 clk[0]:24 ctsbuf_net_2130:25 3.997418e-05 +211 clk[0]:24 ctsbuf_net_2130:26 0.001353059 + +*RES +0 clk[0] clk[0]:87 0.001544643 +1 clk[0]:67 clk[0]:66 0.00341 +2 clk[0]:67 clk[0]:21 0.007677679 +3 clk[0]:66 clk[0]:65 0.006448008 +4 clk[0]:53 clk[0]:52 0.01629018 +5 clk[0]:54 clk[0]:53 0.00341 +6 clk[0]:52 clk[0]:51 0.00341 +7 clk[0]:51 clk[0]:50 0.004539025 +8 clk[0]:17 clk[0]:16 0.00341 +9 clk[0]:16 clk[0]:15 0.007382524 +10 clk[0]:81 clk[0]:80 0.00341 +11 clk[0]:80 clk[0]:79 0.007382524 +12 clk[0]:31 clk[0]:30 0.0240192 +13 clk[0]:32 clk[0]:31 0.00341 +14 clk[0]:26 clk[0]:25 0.00341 +15 clk[0]:25 clk[0]:24 0.006674391 +16 clk[0]:49 clk[0]:48 0.03379241 +17 clk[0]:50 clk[0]:49 0.00341 +18 clk[0]:50 clk[0]:36 0.006555716 +19 clk[0]:47 clk[0]:46 0.00341 +20 clk[0]:46 clk[0]:45 0.006410408 +21 clk[0]:40 clk[0]:39 0.02964733 +22 clk[0]:41 clk[0]:40 0.00341 +23 clk[0]:39 clk[0]:38 0.00341 +24 clk[0]:38 clk[0]:37 0.007467124 +25 clk[0]:83 clk[0]:82 0.02959375 +26 clk[0]:83 clk[0]:68 0.04464286 +27 clk[0]:84 clk[0]:83 0.00341 +28 clk[0]:86 clk[0]:85 0.00341 +29 clk[0]:85 clk[0]:84 0.0002859167 +30 clk[0]:87 clk[0]:86 0.0045 +31 clk[0]:22 grid_clb_1__2_:clk[0] 0.0006721 +32 clk[0]:23 clk[0]:22 0.0001065333 +33 clk[0]:28 clk[0]:27 0.04464286 +34 clk[0]:27 clk[0]:26 0.03529242 +35 clk[0]:48 clk[0]:47 0.04442634 +36 clk[0]:82 clk[0]:81 0.04442634 +37 clk[0]:68 clk[0]:67 0.00575 +38 clk[0]:19 clk[0]:18 0.04464286 +39 clk[0]:18 clk[0]:17 0.01934152 +40 clk[0]:37 grid_clb_1__1_:clk[0] 0.007833333 +41 clk[0]:24 clk[0]:23 0.007809833 +42 clk[0]:35 clk[0]:34 0.00311375 +43 clk[0]:36 clk[0]:35 0.007833333 +44 clk[0]:44 clk[0]:43 0.003257883 +45 clk[0]:45 clk[0]:44 0.007833333 +46 clk[0]:69 grid_clb_2__1_:clk[0] 0.007833333 +47 clk[0]:72 clk[0]:71 0.001655967 +48 clk[0]:73 clk[0]:72 0.007833333 +49 clk[0]:74 clk[0]:73 0.007833333 +50 clk[0]:75 clk[0]:74 0.007833333 +51 clk[0]:76 clk[0]:75 0.007833333 +52 clk[0]:79 clk[0]:78 0.0057293 +53 clk[0]:5 grid_clb_2__2_:clk[0] 0.007833333 +54 clk[0]:8 clk[0]:7 0.001655967 +55 clk[0]:9 clk[0]:8 0.007833333 +56 clk[0]:10 clk[0]:9 0.007833333 +57 clk[0]:11 clk[0]:10 0.007833333 +58 clk[0]:12 clk[0]:11 0.007833333 +59 clk[0]:15 clk[0]:14 0.0057293 +60 clk[0]:55 clk[0]:54 0.007806308 +61 clk[0]:58 clk[0]:57 0.002590483 +62 clk[0]:59 clk[0]:58 0.007833333 +63 clk[0]:60 clk[0]:59 0.007833333 +64 clk[0]:61 clk[0]:60 0.007833333 +65 clk[0]:62 clk[0]:61 0.007833333 +66 clk[0]:65 clk[0]:64 0.006663817 +67 clk[0]:29 clk[0]:28 0.02040625 +68 clk[0]:30 clk[0]:29 1e-05 +69 clk[0]:20 clk[0]:19 0.03696429 +70 clk[0]:21 clk[0]:20 1e-05 +71 clk[0]:34 clk[0]:33 1e-05 +72 clk[0]:33 clk[0]:32 0.004692402 +73 clk[0]:43 clk[0]:42 1e-05 +74 clk[0]:42 clk[0]:41 0.004548268 +75 clk[0]:71 clk[0]:70 1e-05 +76 clk[0]:70 clk[0]:69 0.00617721 +77 clk[0]:78 clk[0]:77 1e-05 +78 clk[0]:77 clk[0]:76 0.002103877 +79 clk[0]:7 clk[0]:6 1e-05 +80 clk[0]:6 clk[0]:5 0.00617721 +81 clk[0]:14 clk[0]:13 1e-05 +82 clk[0]:13 clk[0]:12 0.002103877 +83 clk[0]:57 clk[0]:56 1e-05 +84 clk[0]:56 clk[0]:55 0.005242693 +85 clk[0]:64 clk[0]:63 1e-05 +86 clk[0]:63 clk[0]:62 0.00116936 + +*END + +*D_NET cby_0__1__1_chany_top_out[18] 0.001208873 //LENGTH 11.020 LUMPCC 0.0003931342 DR + +*CONN +*I cby_0__2_:chany_top_out[18] O *L 0 *C 313.720 777.850 +*I sb_0__2_:chany_bottom_in[18] I *L 0 *C 313.720 788.870 + +*CAP +0 cby_0__2_:chany_top_out[18] 0.0004078695 +1 sb_0__2_:chany_bottom_in[18] 0.0004078695 +2 cby_0__2_:chany_top_out[18] cby_0__2_:chany_top_in[9] 0.0001405306 +3 sb_0__2_:chany_bottom_in[18] sb_0__2_:chany_bottom_out[9] 0.0001405306 +4 cby_0__2_:chany_top_out[18] cby_0__2_:chany_top_in[16] 5.60365e-05 +5 sb_0__2_:chany_bottom_in[18] sb_0__2_:chany_bottom_out[16] 5.60365e-05 + +*RES +0 cby_0__2_:chany_top_out[18] sb_0__2_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[5] 0.001236731 //LENGTH 11.020 LUMPCC 0.0005813158 DR + +*CONN +*I cby_1__1_:chany_bottom_out[5] O *L 0 *C 580.060 408.070 +*I sb_1__0_:chany_top_in[5] I *L 0 *C 580.060 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[5] 0.0003277076 +1 sb_1__0_:chany_top_in[5] 0.0003277076 +2 cby_1__1_:chany_bottom_out[5] cby_1__1_:chany_bottom_out[19] 0.000145329 +3 sb_1__0_:chany_top_in[5] sb_1__0_:chany_top_in[19] 0.000145329 +4 cby_1__1_:chany_bottom_out[5] cby_1__1_:chany_bottom_in[1] 0.000145329 +5 sb_1__0_:chany_top_in[5] sb_1__0_:chany_top_out[1] 0.000145329 + +*RES +0 cby_1__1_:chany_bottom_out[5] sb_1__0_:chany_top_in[5] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[11] 0.001237409 //LENGTH 11.020 LUMPCC 0.000580085 DR + +*CONN +*I cby_1__1_:chany_bottom_out[11] O *L 0 *C 595.700 408.070 +*I sb_1__0_:chany_top_in[11] I *L 0 *C 595.700 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[11] 0.000328662 +1 sb_1__0_:chany_top_in[11] 0.000328662 +2 cby_1__1_:chany_bottom_out[11] cby_1__1_:chany_bottom_out[6] 0.0001450212 +3 sb_1__0_:chany_top_in[11] sb_1__0_:chany_top_in[6] 0.0001450212 +4 cby_1__1_:chany_bottom_out[11] cby_1__1_:chany_bottom_in[0] 0.0001450212 +5 sb_1__0_:chany_top_in[11] sb_1__0_:chany_top_out[0] 0.0001450212 + +*RES +0 cby_1__1_:chany_bottom_out[11] sb_1__0_:chany_top_in[11] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[17] 0.001232405 //LENGTH 11.020 LUMPCC 0.0005995386 DR + +*CONN +*I cby_1__1_:chany_bottom_out[17] O *L 0 *C 601.220 408.070 +*I sb_1__0_:chany_top_in[17] I *L 0 *C 601.220 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[17] 0.0003164331 +1 sb_1__0_:chany_top_in[17] 0.0003164331 +2 cby_1__1_:chany_bottom_out[17] cby_1__1_:chany_bottom_out[0] 0.0001525348 +3 sb_1__0_:chany_top_in[17] sb_1__0_:chany_top_in[0] 0.0001525348 +4 cby_1__1_:chany_bottom_out[17] cby_1__1_:chany_bottom_out[2] 0.0001472345 +5 sb_1__0_:chany_top_in[17] sb_1__0_:chany_top_in[2] 0.0001472345 + +*RES +0 cby_1__1_:chany_bottom_out[17] sb_1__0_:chany_top_in[17] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[5] 0.001303161 //LENGTH 11.020 LUMPCC 0.0004912275 DR + +*CONN +*I cby_1__1_:chany_top_out[5] O *L 0 *C 595.700 516.730 +*I sb_1__1_:chany_bottom_in[5] I *L 0 *C 595.700 527.750 + +*CAP +0 cby_1__1_:chany_top_out[5] 0.0004059668 +1 sb_1__1_:chany_bottom_in[5] 0.0004059668 +2 cby_1__1_:chany_top_out[5] cby_1__1_:chany_top_out[16] 0.0001209422 +3 sb_1__1_:chany_bottom_in[5] sb_1__1_:chany_bottom_in[16] 0.0001209422 +4 cby_1__1_:chany_top_out[5] cby_1__1_:chany_top_in[6] 0.0001246715 +5 sb_1__1_:chany_bottom_in[5] sb_1__1_:chany_bottom_out[6] 0.0001246715 + +*RES +0 cby_1__1_:chany_top_out[5] sb_1__1_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[11] 0.001233866 //LENGTH 11.020 LUMPCC 0.0003191747 DR + +*CONN +*I cby_1__1_:chany_top_out[11] O *L 0 *C 606.280 516.730 +*I sb_1__1_:chany_bottom_in[11] I *L 0 *C 606.280 527.750 + +*CAP +0 cby_1__1_:chany_top_out[11] 0.0004573456 +1 sb_1__1_:chany_bottom_in[11] 0.0004573456 +2 cby_1__1_:chany_top_out[11] cby_1__1_:chany_top_out[7] 0.0001266936 +3 sb_1__1_:chany_bottom_in[11] sb_1__1_:chany_bottom_in[7] 0.0001266936 +4 cby_1__1_:chany_top_out[11] cby_1__1_:chany_top_out[9] 3.289369e-05 +5 sb_1__1_:chany_bottom_in[11] sb_1__1_:chany_bottom_in[9] 3.289369e-05 + +*RES +0 cby_1__1_:chany_top_out[11] sb_1__1_:chany_bottom_in[11] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[18] 0.001201755 //LENGTH 11.020 LUMPCC 0.0001897448 DR + +*CONN +*I cby_1__1_:chany_top_out[18] O *L 0 *C 577.300 516.730 +*I sb_1__1_:chany_bottom_in[18] I *L 0 *C 577.300 527.750 + +*CAP +0 cby_1__1_:chany_top_out[18] 0.0005060053 +1 sb_1__1_:chany_bottom_in[18] 0.0005060053 +2 cby_1__1_:chany_top_out[18] cby_1__1_:chany_top_in[15] 2.503735e-05 +3 sb_1__1_:chany_bottom_in[18] sb_1__1_:chany_bottom_out[15] 2.503735e-05 +4 cby_1__1_:chany_top_out[18] cby_1__1_:chany_top_in[17] 6.983505e-05 +5 sb_1__1_:chany_bottom_in[18] sb_1__1_:chany_bottom_out[17] 6.983505e-05 + +*RES +0 cby_1__1_:chany_top_out[18] sb_1__1_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_13_[0] 0.001312697 //LENGTH 7.660 LUMPCC 0.0002480144 DR + +*CONN +*I cby_1__1_:left_grid_pin_13_[0] O *L 0 *C 548.470 465.120 +*I grid_clb_1__1_:right_width_0_height_0__pin_13_[0] I *L 0 *C 540.810 465.120 + +*CAP +0 cby_1__1_:left_grid_pin_13_[0] 0.0005323415 +1 grid_clb_1__1_:right_width_0_height_0__pin_13_[0] 0.0005323415 +2 cby_1__1_:left_grid_pin_13_[0] cby_1__1_:left_grid_pin_14_[0] 0.0001240072 +3 grid_clb_1__1_:right_width_0_height_0__pin_13_[0] grid_clb_1__1_:right_width_0_height_0__pin_14_[0] 0.0001240072 + +*RES +0 cby_1__1_:left_grid_pin_13_[0] grid_clb_1__1_:right_width_0_height_0__pin_13_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_4_[0] 0.001495596 //LENGTH 7.660 LUMPCC 0.0004756276 DR + +*CONN +*I cby_1__1_:left_grid_pin_4_[0] O *L 0 *C 548.470 508.640 +*I grid_clb_1__1_:right_width_0_height_0__pin_4_[0] I *L 0 *C 540.810 508.640 + +*CAP +0 cby_1__1_:left_grid_pin_4_[0] 0.0005099843 +1 grid_clb_1__1_:right_width_0_height_0__pin_4_[0] 0.0005099843 +2 cby_1__1_:left_grid_pin_4_[0] cby_1__1_:left_grid_pin_0_[0] 0.0001189069 +3 grid_clb_1__1_:right_width_0_height_0__pin_4_[0] grid_clb_1__1_:right_width_0_height_0__pin_0_[0] 0.0001189069 +4 cby_1__1_:left_grid_pin_4_[0] cby_1__1_:left_grid_pin_7_[0] 0.0001189069 +5 grid_clb_1__1_:right_width_0_height_0__pin_4_[0] grid_clb_1__1_:right_width_0_height_0__pin_7_[0] 0.0001189069 + +*RES +0 cby_1__1_:left_grid_pin_4_[0] grid_clb_1__1_:right_width_0_height_0__pin_4_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[1] 0.001149414 //LENGTH 11.020 LUMPCC 0.0003822193 DR + +*CONN +*I cby_1__2_:chany_bottom_out[1] O *L 0 *C 577.300 669.190 +*I sb_1__1_:chany_top_in[1] I *L 0 *C 577.300 658.170 +*N cby_1__1__1_chany_bottom_out[1]:2 *C 577.300 667.519 +*N cby_1__1__1_chany_bottom_out[1]:3 *C 577.300 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[1] 0.0001182479 +1 sb_1__1_:chany_top_in[1] 0.0002653497 +2 cby_1__1__1_chany_bottom_out[1]:2 0.0002653497 +3 cby_1__1__1_chany_bottom_out[1]:3 0.0001182479 +4 sb_1__1_:chany_top_in[1] sb_1__1_:chany_top_in[14] 4.036643e-05 +5 cby_1__1__1_chany_bottom_out[1]:2 cby_1__1__1_chany_bottom_out[14]:2 4.036643e-05 +6 cby_1__2_:chany_bottom_out[1] cby_1__2_:chany_bottom_in[9] 7.341718e-06 +7 sb_1__1_:chany_top_in[1] sb_1__1_:chany_top_out[9] 0.0001434015 +8 cby_1__1__1_chany_bottom_out[1]:3 sb_1__1__0_chany_top_out[9]:2 7.341718e-06 +9 cby_1__1__1_chany_bottom_out[1]:2 sb_1__1__0_chany_top_out[9]:3 0.0001434015 + +*RES +0 cby_1__2_:chany_bottom_out[1] cby_1__1__1_chany_bottom_out[1]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[1]:3 cby_1__1__1_chany_bottom_out[1]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[1]:2 sb_1__1_:chany_top_in[1] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[8] 0.00125099 //LENGTH 11.020 LUMPCC 0.0005798265 DR + +*CONN +*I cby_1__2_:chany_bottom_out[8] O *L 0 *C 592.020 669.190 +*I sb_1__1_:chany_top_in[8] I *L 0 *C 592.020 658.170 +*N cby_1__1__1_chany_bottom_out[8]:2 *C 592.020 667.519 +*N cby_1__1__1_chany_bottom_out[8]:3 *C 592.020 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[8] 0.0001110902 +1 sb_1__1_:chany_top_in[8] 0.0002244915 +2 cby_1__1__1_chany_bottom_out[8]:2 0.0002244915 +3 cby_1__1__1_chany_bottom_out[8]:3 0.0001110902 +4 cby_1__2_:chany_bottom_out[8] cby_1__2_:chany_bottom_out[10] 7.294814e-06 +5 sb_1__1_:chany_top_in[8] sb_1__1_:chany_top_in[10] 0.0001357202 +6 cby_1__1__1_chany_bottom_out[8]:3 cby_1__1__1_chany_bottom_out[10]:3 7.294814e-06 +7 cby_1__1__1_chany_bottom_out[8]:2 cby_1__1__1_chany_bottom_out[10]:2 0.0001357202 +8 cby_1__2_:chany_bottom_out[8] cby_1__2_:chany_bottom_in[3] 7.346249e-06 +9 sb_1__1_:chany_top_in[8] sb_1__1_:chany_top_out[3] 0.000139552 +10 cby_1__1__1_chany_bottom_out[8]:3 sb_1__1__0_chany_top_out[3]:2 7.346249e-06 +11 cby_1__1__1_chany_bottom_out[8]:2 sb_1__1__0_chany_top_out[3]:3 0.000139552 + +*RES +0 cby_1__2_:chany_bottom_out[8] cby_1__1__1_chany_bottom_out[8]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[8]:3 cby_1__1__1_chany_bottom_out[8]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[8]:2 sb_1__1_:chany_top_in[8] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[13] 0.001197339 //LENGTH 11.020 LUMPCC 0.0004738705 DR + +*CONN +*I cby_1__2_:chany_bottom_out[13] O *L 0 *C 583.280 669.190 +*I sb_1__1_:chany_top_in[13] I *L 0 *C 583.280 658.170 +*N cby_1__1__1_chany_bottom_out[13]:2 *C 583.280 667.519 +*N cby_1__1__1_chany_bottom_out[13]:3 *C 583.280 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[13] 0.0001183478 +1 sb_1__1_:chany_top_in[13] 0.0002433864 +2 cby_1__1__1_chany_bottom_out[13]:2 0.0002433864 +3 cby_1__1__1_chany_bottom_out[13]:3 0.0001183478 +4 cby_1__2_:chany_bottom_out[13] cby_1__2_:chany_bottom_in[13] 7.340376e-06 +5 sb_1__1_:chany_top_in[13] sb_1__1_:chany_top_out[13] 0.0001387437 +6 cby_1__1__1_chany_bottom_out[13]:3 sb_1__1__0_chany_top_out[13]:2 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[13]:2 sb_1__1__0_chany_top_out[13]:3 0.0001387437 +8 cby_1__2_:chany_bottom_out[13] cby_1__2_:chany_bottom_in[17] 5.882677e-07 +9 sb_1__1_:chany_top_in[13] sb_1__1_:chany_top_out[17] 9.026287e-05 +10 cby_1__1__1_chany_bottom_out[13]:3 sb_1__1__0_chany_top_out[17]:2 5.882677e-07 +11 cby_1__1__1_chany_bottom_out[13]:2 sb_1__1__0_chany_top_out[17]:3 9.026287e-05 + +*RES +0 cby_1__2_:chany_bottom_out[13] cby_1__1__1_chany_bottom_out[13]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[13]:3 cby_1__1__1_chany_bottom_out[13]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[13]:2 sb_1__1_:chany_top_in[13] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[18] 0.001170388 //LENGTH 11.020 LUMPCC 0.0003934109 DR + +*CONN +*I cby_1__2_:chany_bottom_out[18] O *L 0 *C 604.440 669.190 +*I sb_1__1_:chany_top_in[18] I *L 0 *C 604.440 658.170 +*N cby_1__1__1_chany_bottom_out[18]:2 *C 604.440 667.519 +*N cby_1__1__1_chany_bottom_out[18]:3 *C 604.440 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[18] 0.0001178596 +1 sb_1__1_:chany_top_in[18] 0.0002706291 +2 cby_1__1__1_chany_bottom_out[18]:2 0.0002706291 +3 cby_1__1__1_chany_bottom_out[18]:3 0.0001178596 +4 cby_1__2_:chany_bottom_out[18] cby_1__2_:chany_bottom_in[5] 7.340369e-06 +5 sb_1__1_:chany_top_in[18] sb_1__1_:chany_top_out[5] 0.0001380049 +6 cby_1__1__1_chany_bottom_out[18]:3 sb_1__1__0_chany_top_out[5]:2 7.340369e-06 +7 cby_1__1__1_chany_bottom_out[18]:2 sb_1__1__0_chany_top_out[5]:3 0.0001380049 +8 sb_1__1_:chany_top_in[18] sb_1__1_:chany_top_out[16] 5.136023e-05 +9 cby_1__1__1_chany_bottom_out[18]:2 sb_1__1__0_chany_top_out[16]:3 5.136023e-05 + +*RES +0 cby_1__2_:chany_bottom_out[18] cby_1__1__1_chany_bottom_out[18]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[18]:3 cby_1__1__1_chany_bottom_out[18]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[18]:2 sb_1__1_:chany_top_in[18] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_top_out[6] 0.001209973 //LENGTH 11.020 LUMPCC 0.000322255 DR + +*CONN +*I cby_1__2_:chany_top_out[6] O *L 0 *C 614.100 777.850 +*I sb_1__2_:chany_bottom_in[6] I *L 0 *C 614.100 788.870 + +*CAP +0 cby_1__2_:chany_top_out[6] 0.0004438592 +1 sb_1__2_:chany_bottom_in[6] 0.0004438592 +2 cby_1__2_:chany_top_out[6] cby_1__2_:chany_top_in[10] 0.0001316805 +3 sb_1__2_:chany_bottom_in[6] sb_1__2_:chany_bottom_out[10] 0.0001316805 +4 cby_1__2_:chany_top_out[6] sb_1__2__0_chany_bottom_out[14]:5 2.944697e-05 +5 sb_1__2_:chany_bottom_in[6] sb_1__2__0_chany_bottom_out[14]:6 2.944697e-05 + +*RES +0 cby_1__2_:chany_top_out[6] sb_1__2_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[11] 0.001209252 //LENGTH 11.020 LUMPCC 0.0003438843 DR + +*CONN +*I cby_1__2_:chany_top_out[11] O *L 0 *C 606.280 777.850 +*I sb_1__2_:chany_bottom_in[11] I *L 0 *C 606.280 788.870 + +*CAP +0 cby_1__2_:chany_top_out[11] 0.0004326839 +1 sb_1__2_:chany_bottom_in[11] 0.0004326839 +2 cby_1__2_:chany_top_out[11] cby_1__2_:chany_top_out[7] 0.0001333081 +3 sb_1__2_:chany_bottom_in[11] sb_1__2_:chany_bottom_in[7] 0.0001333081 +4 cby_1__2_:chany_top_out[11] cby_1__2_:chany_top_out[9] 3.863406e-05 +5 sb_1__2_:chany_bottom_in[11] sb_1__2_:chany_bottom_in[9] 3.863406e-05 + +*RES +0 cby_1__2_:chany_top_out[11] sb_1__2_:chany_bottom_in[11] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[17] 0.001272042 //LENGTH 11.020 LUMPCC 0.0005339056 DR + +*CONN +*I cby_1__2_:chany_top_out[17] O *L 0 *C 589.720 777.850 +*I sb_1__2_:chany_bottom_in[17] I *L 0 *C 589.720 788.870 + +*CAP +0 cby_1__2_:chany_top_out[17] 0.0003690684 +1 sb_1__2_:chany_bottom_in[17] 0.0003690684 +2 cby_1__2_:chany_top_out[17] cby_1__2_:chany_top_in[3] 0.0001334764 +3 sb_1__2_:chany_bottom_in[17] sb_1__2_:chany_bottom_out[3] 0.0001334764 +4 cby_1__2_:chany_top_out[17] cby_1__2_:chany_top_in[19] 0.0001334764 +5 sb_1__2_:chany_bottom_in[17] sb_1__2_:chany_bottom_out[19] 0.0001334764 + +*RES +0 cby_1__2_:chany_top_out[17] sb_1__2_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_13_[0] 0.001425395 //LENGTH 7.660 LUMPCC 0.0002443562 DR + +*CONN +*I cby_1__2_:left_grid_pin_13_[0] O *L 0 *C 548.470 726.240 +*I grid_clb_1__2_:right_width_0_height_0__pin_13_[0] I *L 0 *C 540.810 726.240 + +*CAP +0 cby_1__2_:left_grid_pin_13_[0] 0.0005905195 +1 grid_clb_1__2_:right_width_0_height_0__pin_13_[0] 0.0005905195 +2 cby_1__2_:left_grid_pin_13_[0] cby_1__2_:left_grid_pin_14_[0] 0.0001221781 +3 grid_clb_1__2_:right_width_0_height_0__pin_13_[0] grid_clb_1__2_:right_width_0_height_0__pin_14_[0] 0.0001221781 + +*RES +0 cby_1__2_:left_grid_pin_13_[0] grid_clb_1__2_:right_width_0_height_0__pin_13_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_2_[0] 0.001556485 //LENGTH 7.660 LUMPCC 0.0004169286 DR + +*CONN +*I cby_1__2_:left_grid_pin_2_[0] O *L 0 *C 548.470 767.040 +*I grid_clb_1__2_:right_width_0_height_0__pin_2_[0] I *L 0 *C 540.810 767.040 + +*CAP +0 cby_1__2_:left_grid_pin_2_[0] 0.0005697781 +1 grid_clb_1__2_:right_width_0_height_0__pin_2_[0] 0.0005697781 +2 cby_1__2_:left_grid_pin_2_[0] cby_1__2_:left_grid_pin_3_[0] 0.0001044305 +3 grid_clb_1__2_:right_width_0_height_0__pin_2_[0] grid_clb_1__2_:right_width_0_height_0__pin_3_[0] 0.0001044305 +4 cby_1__2_:left_grid_pin_2_[0] cby_1__2_:left_grid_pin_7_[0] 0.0001040338 +5 grid_clb_1__2_:right_width_0_height_0__pin_2_[0] grid_clb_1__2_:right_width_0_height_0__pin_7_[0] 0.0001040338 + +*RES +0 cby_1__2_:left_grid_pin_2_[0] grid_clb_1__2_:right_width_0_height_0__pin_2_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_9_[0] 0.001377797 //LENGTH 7.660 LUMPCC 0.0002259797 DR + +*CONN +*I cby_1__2_:left_grid_pin_9_[0] O *L 0 *C 548.470 750.720 +*I grid_clb_1__2_:right_width_0_height_0__pin_9_[0] I *L 0 *C 540.810 750.720 + +*CAP +0 cby_1__2_:left_grid_pin_9_[0] 0.0005759087 +1 grid_clb_1__2_:right_width_0_height_0__pin_9_[0] 0.0005759087 +2 cby_1__2_:left_grid_pin_9_[0] cby_1__2_:left_grid_pin_6_[0] 0.0001129898 +3 grid_clb_1__2_:right_width_0_height_0__pin_9_[0] grid_clb_1__2_:right_width_0_height_0__pin_6_[0] 0.0001129898 + +*RES +0 cby_1__2_:left_grid_pin_9_[0] grid_clb_1__2_:right_width_0_height_0__pin_9_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[4] 0.001228755 //LENGTH 11.020 LUMPCC 0.0005916361 DR + +*CONN +*I cby_2__1_:chany_bottom_out[4] O *L 0 *C 833.060 408.070 +*I sb_2__0_:chany_top_in[4] I *L 0 *C 833.060 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[4] 0.0003185596 +1 sb_2__0_:chany_top_in[4] 0.0003185596 +2 cby_2__1_:chany_bottom_out[4] cby_2__1_:chany_bottom_out[12] 0.000147909 +3 sb_2__0_:chany_top_in[4] sb_2__0_:chany_top_in[12] 0.000147909 +4 cby_2__1_:chany_bottom_out[4] cby_2__1_:chany_bottom_in[15] 0.000147909 +5 sb_2__0_:chany_top_in[4] sb_2__0_:chany_top_out[15] 0.000147909 + +*RES +0 cby_2__1_:chany_bottom_out[4] sb_2__0_:chany_top_in[4] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[10] 0.001231928 //LENGTH 11.020 LUMPCC 0.0005937052 DR + +*CONN +*I cby_2__1_:chany_bottom_out[10] O *L 0 *C 854.220 408.070 +*I sb_2__0_:chany_top_in[10] I *L 0 *C 854.220 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[10] 0.0003191112 +1 sb_2__0_:chany_top_in[10] 0.0003191112 +2 cby_2__1_:chany_bottom_out[10] cby_2__1_:chany_bottom_out[3] 0.0001484263 +3 sb_2__0_:chany_top_in[10] sb_2__0_:chany_top_in[3] 0.0001484263 +4 cby_2__1_:chany_bottom_out[10] cby_2__1_:chany_bottom_out[8] 0.0001484263 +5 sb_2__0_:chany_top_in[10] sb_2__0_:chany_top_in[8] 0.0001484263 + +*RES +0 cby_2__1_:chany_bottom_out[10] sb_2__0_:chany_top_in[10] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[16] 0.001237502 //LENGTH 11.020 LUMPCC 0.0005795517 DR + +*CONN +*I cby_2__1_:chany_bottom_out[16] O *L 0 *C 850.540 408.070 +*I sb_2__0_:chany_top_in[16] I *L 0 *C 850.540 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[16] 0.0003289752 +1 sb_2__0_:chany_top_in[16] 0.0003289752 +2 cby_2__1_:chany_bottom_out[16] cby_2__1_:chany_bottom_in[6] 0.0001448879 +3 sb_2__0_:chany_top_in[16] sb_2__0_:chany_top_out[6] 0.0001448879 +4 cby_2__1_:chany_bottom_out[16] cby_2__1_:chany_bottom_in[8] 0.0001448879 +5 sb_2__0_:chany_top_in[16] sb_2__0_:chany_top_out[8] 0.0001448879 + +*RES +0 cby_2__1_:chany_bottom_out[16] sb_2__0_:chany_top_in[16] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[3] 0.001201546 //LENGTH 11.020 LUMPCC 0.0002732998 DR + +*CONN +*I cby_2__1_:chany_top_out[3] O *L 0 *C 869.400 516.730 +*I sb_2__1_:chany_bottom_in[3] I *L 0 *C 869.400 527.750 + +*CAP +0 cby_2__1_:chany_top_out[3] 0.0004641231 +1 sb_2__1_:chany_bottom_in[3] 0.0004641231 +2 cby_2__1_:chany_top_out[3] cby_2__1_:chany_top_out[7] 0.0001366499 +3 sb_2__1_:chany_bottom_in[3] sb_2__1_:chany_bottom_in[7] 0.0001366499 + +*RES +0 cby_2__1_:chany_top_out[3] sb_2__1_:chany_bottom_in[3] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[5] 0.001281527 //LENGTH 11.020 LUMPCC 0.0005305507 DR + +*CONN +*I cby_2__1_:chany_top_out[5] O *L 0 *C 856.980 516.730 +*I sb_2__1_:chany_bottom_in[5] I *L 0 *C 856.980 527.750 + +*CAP +0 cby_2__1_:chany_top_out[5] 0.0003754879 +1 sb_2__1_:chany_bottom_in[5] 0.0003754879 +2 cby_2__1_:chany_top_out[5] cby_2__1_:chany_top_out[16] 0.0001314988 +3 sb_2__1_:chany_bottom_in[5] sb_2__1_:chany_bottom_in[16] 0.0001314988 +4 cby_2__1_:chany_top_out[5] cby_2__1_:chany_top_in[6] 0.0001337766 +5 sb_2__1_:chany_bottom_in[5] sb_2__1_:chany_bottom_out[6] 0.0001337766 + +*RES +0 cby_2__1_:chany_top_out[5] sb_2__1_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[13] 0.001281393 //LENGTH 11.020 LUMPCC 0.0005265397 DR + +*CONN +*I cby_2__1_:chany_top_out[13] O *L 0 *C 849.160 516.730 +*I sb_2__1_:chany_bottom_in[13] I *L 0 *C 849.160 527.750 + +*CAP +0 cby_2__1_:chany_top_out[13] 0.0003774267 +1 sb_2__1_:chany_bottom_in[13] 0.0003774267 +2 cby_2__1_:chany_top_out[13] cby_2__1_:chany_top_out[1] 0.0001316349 +3 sb_2__1_:chany_bottom_in[13] sb_2__1_:chany_bottom_in[1] 0.0001316349 +4 cby_2__1_:chany_top_out[13] cby_2__1_:chany_top_in[3] 0.0001316349 +5 sb_2__1_:chany_bottom_in[13] sb_2__1_:chany_bottom_out[3] 0.0001316349 + +*RES +0 cby_2__1_:chany_top_out[13] sb_2__1_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[18] 0.001184831 //LENGTH 11.020 LUMPCC 0.0002079356 DR + +*CONN +*I cby_2__1_:chany_top_out[18] O *L 0 *C 838.580 516.730 +*I sb_2__1_:chany_bottom_in[18] I *L 0 *C 838.580 527.750 + +*CAP +0 cby_2__1_:chany_top_out[18] 0.0004884476 +1 sb_2__1_:chany_bottom_in[18] 0.0004884476 +2 cby_2__1_:chany_top_out[18] cby_2__1_:chany_top_in[15] 2.737794e-05 +3 sb_2__1_:chany_bottom_in[18] sb_2__1_:chany_bottom_out[15] 2.737794e-05 +4 cby_2__1_:chany_top_out[18] cby_2__1_:chany_top_in[17] 7.658988e-05 +5 sb_2__1_:chany_bottom_in[18] sb_2__1_:chany_bottom_out[17] 7.658988e-05 + +*RES +0 cby_2__1_:chany_top_out[18] sb_2__1_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_13_[0] 0.001080148 //LENGTH 7.660 LUMPCC 0.0003595714 DR + +*CONN +*I cby_2__1_:left_grid_pin_13_[0] O *L 0 *C 809.750 465.120 +*I grid_clb_2__1_:right_width_0_height_0__pin_13_[0] I *L 0 *C 802.090 465.120 + +*CAP +0 cby_2__1_:left_grid_pin_13_[0] 0.0003602881 +1 grid_clb_2__1_:right_width_0_height_0__pin_13_[0] 0.0003602881 +2 cby_2__1_:left_grid_pin_13_[0] cby_2__1_:left_grid_pin_14_[0] 0.0001797857 +3 grid_clb_2__1_:right_width_0_height_0__pin_13_[0] grid_clb_2__1_:right_width_0_height_0__pin_14_[0] 0.0001797857 + +*RES +0 cby_2__1_:left_grid_pin_13_[0] grid_clb_2__1_:right_width_0_height_0__pin_13_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_2_[0] 0.001215787 //LENGTH 7.660 LUMPCC 0.0007181166 DR + +*CONN +*I cby_2__1_:left_grid_pin_2_[0] O *L 0 *C 809.750 505.920 +*I grid_clb_2__1_:right_width_0_height_0__pin_2_[0] I *L 0 *C 802.090 505.920 + +*CAP +0 cby_2__1_:left_grid_pin_2_[0] 0.0002488354 +1 grid_clb_2__1_:right_width_0_height_0__pin_2_[0] 0.0002488354 +2 cby_2__1_:left_grid_pin_2_[0] cby_2__1_:left_grid_pin_3_[0] 0.0001795292 +3 grid_clb_2__1_:right_width_0_height_0__pin_2_[0] grid_clb_2__1_:right_width_0_height_0__pin_3_[0] 0.0001795292 +4 cby_2__1_:left_grid_pin_2_[0] cby_2__1_:left_grid_pin_7_[0] 0.0001795292 +5 grid_clb_2__1_:right_width_0_height_0__pin_2_[0] grid_clb_2__1_:right_width_0_height_0__pin_7_[0] 0.0001795292 + +*RES +0 cby_2__1_:left_grid_pin_2_[0] grid_clb_2__1_:right_width_0_height_0__pin_2_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_ccff_tail[0] 0.001886758 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_2__2_:ccff_tail[0] O *L 0 *C 894.090 768.400 +*I grid_io_right_3__2_:ccff_head[0] I *L 0 *C 907.270 768.400 + +*CAP +0 cby_2__2_:ccff_tail[0] 0.0009433792 +1 grid_io_right_3__2_:ccff_head[0] 0.0009433792 + +*RES +0 cby_2__2_:ccff_tail[0] grid_io_right_3__2_:ccff_head[0] 0.002064866 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[4] 0.001255609 //LENGTH 11.020 LUMPCC 0.0005537507 DR + +*CONN +*I cby_2__2_:chany_bottom_out[4] O *L 0 *C 833.060 669.190 +*I sb_2__1_:chany_top_in[4] I *L 0 *C 833.060 658.170 +*N cby_1__1__3_chany_bottom_out[4]:2 *C 833.060 667.519 +*N cby_1__1__3_chany_bottom_out[4]:3 *C 833.060 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[4] 0.0001109378 +1 sb_2__1_:chany_top_in[4] 0.0002399915 +2 cby_1__1__3_chany_bottom_out[4]:2 0.0002399915 +3 cby_1__1__3_chany_bottom_out[4]:3 0.0001109378 +4 cby_2__2_:chany_bottom_out[4] cby_2__2_:chany_bottom_out[12] 7.339873e-06 +5 sb_2__1_:chany_top_in[4] sb_2__1_:chany_top_in[12] 0.0001310978 +6 cby_1__1__3_chany_bottom_out[4]:3 cby_1__1__3_chany_bottom_out[12]:3 7.339873e-06 +7 cby_1__1__3_chany_bottom_out[4]:2 cby_1__1__3_chany_bottom_out[12]:2 0.0001310978 +8 cby_2__2_:chany_bottom_out[4] cby_2__2_:chany_bottom_in[15] 7.339873e-06 +9 sb_2__1_:chany_top_in[4] sb_2__1_:chany_top_out[15] 0.0001310978 +10 cby_1__1__3_chany_bottom_out[4]:3 sb_2__1__0_chany_top_out[15]:2 7.339873e-06 +11 cby_1__1__3_chany_bottom_out[4]:2 sb_2__1__0_chany_top_out[15]:3 0.0001310978 + +*RES +0 cby_2__2_:chany_bottom_out[4] cby_1__1__3_chany_bottom_out[4]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[4]:3 cby_1__1__3_chany_bottom_out[4]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[4]:2 sb_2__1_:chany_top_in[4] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[11] 0.001256403 //LENGTH 11.020 LUMPCC 0.0005526695 DR + +*CONN +*I cby_2__2_:chany_bottom_out[11] O *L 0 *C 856.980 669.190 +*I sb_2__1_:chany_top_in[11] I *L 0 *C 856.980 658.170 +*N cby_1__1__3_chany_bottom_out[11]:2 *C 856.980 667.519 +*N cby_1__1__3_chany_bottom_out[11]:3 *C 856.980 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[11] 0.0001109373 +1 sb_2__1_:chany_top_in[11] 0.0002409292 +2 cby_1__1__3_chany_bottom_out[11]:2 0.0002409292 +3 cby_1__1__3_chany_bottom_out[11]:3 0.0001109373 +4 cby_2__2_:chany_bottom_out[11] cby_2__2_:chany_bottom_out[6] 7.340376e-06 +5 sb_2__1_:chany_top_in[11] sb_2__1_:chany_top_in[6] 0.0001309558 +6 cby_1__1__3_chany_bottom_out[11]:3 cby_1__1__3_chany_bottom_out[6]:3 7.340376e-06 +7 cby_1__1__3_chany_bottom_out[11]:2 cby_1__1__3_chany_bottom_out[6]:2 0.0001309558 +8 cby_2__2_:chany_bottom_out[11] cby_2__2_:chany_bottom_in[0] 7.340376e-06 +9 sb_2__1_:chany_top_in[11] sb_2__1_:chany_top_out[0] 0.0001306982 +10 cby_1__1__3_chany_bottom_out[11]:3 sb_2__1__0_chany_top_out[0]:2 7.340376e-06 +11 cby_1__1__3_chany_bottom_out[11]:2 sb_2__1__0_chany_top_out[0]:3 0.0001306982 + +*RES +0 cby_2__2_:chany_bottom_out[11] cby_1__1__3_chany_bottom_out[11]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[11]:3 cby_1__1__3_chany_bottom_out[11]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[11]:2 sb_2__1_:chany_top_in[11] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[17] 0.001269576 //LENGTH 11.020 LUMPCC 0.0005399646 DR + +*CONN +*I cby_2__2_:chany_bottom_out[17] O *L 0 *C 862.500 669.190 +*I sb_2__1_:chany_top_in[17] I *L 0 *C 862.500 658.170 +*N cby_1__1__3_chany_bottom_out[17]:2 *C 862.500 667.519 +*N cby_1__1__3_chany_bottom_out[17]:3 *C 862.500 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[17] 0.0001149169 +1 sb_2__1_:chany_top_in[17] 0.0002498888 +2 cby_1__1__3_chany_bottom_out[17]:2 0.0002498888 +3 cby_1__1__3_chany_bottom_out[17]:3 0.0001149169 +4 cby_2__2_:chany_bottom_out[17] cby_2__2_:chany_bottom_out[0] 6.079439e-06 +5 sb_2__1_:chany_top_in[17] sb_2__1_:chany_top_in[0] 0.0001284326 +6 cby_1__1__3_chany_bottom_out[17]:3 cby_1__1__3_chany_bottom_out[0]:3 6.079439e-06 +7 cby_1__1__3_chany_bottom_out[17]:2 cby_1__1__3_chany_bottom_out[0]:2 0.0001284326 +8 cby_2__2_:chany_bottom_out[17] cby_2__2_:chany_bottom_out[2] 7.295327e-06 +9 sb_2__1_:chany_top_in[17] sb_2__1_:chany_top_in[2] 0.000128175 +10 cby_1__1__3_chany_bottom_out[17]:3 cby_1__1__3_chany_bottom_out[2]:3 7.295327e-06 +11 cby_1__1__3_chany_bottom_out[17]:2 cby_1__1__3_chany_bottom_out[2]:2 0.000128175 + +*RES +0 cby_2__2_:chany_bottom_out[17] cby_1__1__3_chany_bottom_out[17]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[17]:3 cby_1__1__3_chany_bottom_out[17]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[17]:2 sb_2__1_:chany_top_in[17] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_top_out[7] 0.00124246 //LENGTH 11.020 LUMPCC 0.0005859361 DR + +*CONN +*I cby_2__2_:chany_top_out[7] O *L 0 *C 868.480 777.850 +*I sb_2__2_:chany_bottom_in[7] I *L 0 *C 868.480 788.870 + +*CAP +0 cby_2__2_:chany_top_out[7] 0.0003282622 +1 sb_2__2_:chany_bottom_in[7] 0.0003282622 +2 cby_2__2_:chany_top_out[7] cby_2__2_:chany_top_out[3] 0.000146484 +3 sb_2__2_:chany_bottom_in[7] sb_2__2_:chany_bottom_in[3] 0.000146484 +4 cby_2__2_:chany_top_out[7] cby_2__2_:chany_top_out[11] 0.000146484 +5 sb_2__2_:chany_bottom_in[7] sb_2__2_:chany_bottom_in[11] 0.000146484 + +*RES +0 cby_2__2_:chany_top_out[7] sb_2__2_:chany_bottom_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[16] 0.001256755 //LENGTH 11.020 LUMPCC 0.0005666443 DR + +*CONN +*I cby_2__2_:chany_top_out[16] O *L 0 *C 857.900 777.850 +*I sb_2__2_:chany_bottom_in[16] I *L 0 *C 857.900 788.870 + +*CAP +0 cby_2__2_:chany_top_out[16] 0.0003450552 +1 sb_2__2_:chany_bottom_in[16] 0.0003450552 +2 cby_2__2_:chany_top_out[16] cby_2__2_:chany_top_out[5] 0.0001410753 +3 sb_2__2_:chany_bottom_in[16] sb_2__2_:chany_bottom_in[5] 0.0001410753 +4 cby_2__2_:chany_top_out[16] cby_2__2_:chany_top_out[8] 0.0001422469 +5 sb_2__2_:chany_bottom_in[16] sb_2__2_:chany_bottom_in[8] 0.0001422469 + +*RES +0 cby_2__2_:chany_top_out[16] sb_2__2_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_13_[0] 0.001110321 //LENGTH 7.660 LUMPCC 0.0003573897 DR + +*CONN +*I cby_2__2_:left_grid_pin_13_[0] O *L 0 *C 809.750 726.240 +*I grid_clb_2__2_:right_width_0_height_0__pin_13_[0] I *L 0 *C 802.090 726.240 + +*CAP +0 cby_2__2_:left_grid_pin_13_[0] 0.0003764658 +1 grid_clb_2__2_:right_width_0_height_0__pin_13_[0] 0.0003764658 +2 cby_2__2_:left_grid_pin_13_[0] cby_2__2_:left_grid_pin_14_[0] 0.0001786949 +3 grid_clb_2__2_:right_width_0_height_0__pin_13_[0] grid_clb_2__2_:right_width_0_height_0__pin_14_[0] 0.0001786949 + +*RES +0 cby_2__2_:left_grid_pin_13_[0] grid_clb_2__2_:right_width_0_height_0__pin_13_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_4_[0] 0.001231423 //LENGTH 7.660 LUMPCC 0.0006944634 DR + +*CONN +*I cby_2__2_:left_grid_pin_4_[0] O *L 0 *C 809.750 769.760 +*I grid_clb_2__2_:right_width_0_height_0__pin_4_[0] I *L 0 *C 802.090 769.760 + +*CAP +0 cby_2__2_:left_grid_pin_4_[0] 0.0002684799 +1 grid_clb_2__2_:right_width_0_height_0__pin_4_[0] 0.0002684799 +2 cby_2__2_:left_grid_pin_4_[0] cby_2__2_:left_grid_pin_0_[0] 0.0001736158 +3 grid_clb_2__2_:right_width_0_height_0__pin_4_[0] grid_clb_2__2_:right_width_0_height_0__pin_0_[0] 0.0001736158 +4 cby_2__2_:left_grid_pin_4_[0] cby_2__2_:left_grid_pin_7_[0] 0.0001736158 +5 grid_clb_2__2_:right_width_0_height_0__pin_4_[0] grid_clb_2__2_:right_width_0_height_0__pin_7_[0] 0.0001736158 + +*RES +0 cby_2__2_:left_grid_pin_4_[0] grid_clb_2__2_:right_width_0_height_0__pin_4_[0] 0.001200067 + +*END + +*D_NET direct_interc_3_out[0] 0.01079746 //LENGTH 103.080 LUMPCC 0.002993428 DR + +*CONN +*I direct_interc_3_\/FTB_4__3:X O *L 0 *C 521.415 640.220 +*I grid_clb_1__1_:top_width_0_height_0__pin_33_[0] I *L 0 *C 516.120 543.930 +*N direct_interc_3_out[0]:2 *C 516.120 566.735 +*N direct_interc_3_out[0]:3 *C 516.165 566.780 +*N direct_interc_3_out[0]:4 *C 517.915 566.780 +*N direct_interc_3_out[0]:5 *C 517.960 566.825 +*N direct_interc_3_out[0]:6 *C 517.960 616.620 +*N direct_interc_3_out[0]:7 *C 517.960 637.455 +*N direct_interc_3_out[0]:8 *C 518.005 637.500 +*N direct_interc_3_out[0]:9 *C 521.135 637.500 +*N direct_interc_3_out[0]:10 *C 521.180 637.545 +*N direct_interc_3_out[0]:11 *C 521.180 640.175 +*N direct_interc_3_out[0]:12 *C 521.180 640.220 +*N direct_interc_3_out[0]:13 *C 521.415 640.220 + +*CAP +0 direct_interc_3_\/FTB_4__3:X 1e-06 +1 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] 0.0008680976 +2 direct_interc_3_out[0]:2 0.0008680976 +3 direct_interc_3_out[0]:3 0.0001164416 +4 direct_interc_3_out[0]:4 0.0001164416 +5 direct_interc_3_out[0]:5 0.001828213 +6 direct_interc_3_out[0]:6 0.002556873 +7 direct_interc_3_out[0]:7 0.0007286606 +8 direct_interc_3_out[0]:8 0.0001892369 +9 direct_interc_3_out[0]:9 0.0001892369 +10 direct_interc_3_out[0]:10 0.0001219504 +11 direct_interc_3_out[0]:11 0.0001219504 +12 direct_interc_3_out[0]:12 4.974905e-05 +13 direct_interc_3_out[0]:13 4.808425e-05 +14 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] cbx_1__1__0_chanx_right_out[2]:4 0.0001238171 +15 direct_interc_3_out[0]:2 cbx_1__1__0_chanx_right_out[2]:3 0.0001238171 +16 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 0.0002789327 +17 direct_interc_3_out[0]:7 direct_interc_0_out[0]:3 6.521259e-05 +18 direct_interc_3_out[0]:5 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 6.25747e-05 +19 direct_interc_3_out[0]:5 direct_interc_0_out[0]:2 5.367279e-05 +20 direct_interc_3_out[0]:2 direct_interc_0_out[0]:2 0.0002789327 +21 direct_interc_3_out[0]:6 direct_interc_0_out[0]:2 0.0001277873 +22 direct_interc_3_out[0]:6 direct_interc_0_out[0]:3 5.367279e-05 +23 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] direct_interc_5_out[0]:24 6.310035e-06 +24 direct_interc_3_out[0]:7 direct_interc_5_out[0]:22 0.0002440483 +25 direct_interc_3_out[0]:5 direct_interc_5_out[0]:24 0.00045315 +26 direct_interc_3_out[0]:5 direct_interc_5_out[0]:23 0.0001714074 +27 direct_interc_3_out[0]:2 direct_interc_5_out[0]:23 6.310035e-06 +28 direct_interc_3_out[0]:6 direct_interc_5_out[0]:22 0.0001714074 +29 direct_interc_3_out[0]:6 direct_interc_5_out[0]:23 0.0006971983 +30 direct_interc_3_out[0]:11 grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] 3.758868e-05 +31 direct_interc_3_out[0]:10 sb_1__1_:left_top_grid_pin_46_[0] 3.758868e-05 + +*RES +0 direct_interc_3_\/FTB_4__3:X direct_interc_3_out[0]:13 0.152 +1 direct_interc_3_out[0]:13 direct_interc_3_out[0]:12 0.0001277174 +2 direct_interc_3_out[0]:12 direct_interc_3_out[0]:11 0.0045 +3 direct_interc_3_out[0]:11 direct_interc_3_out[0]:10 0.002348214 +4 direct_interc_3_out[0]:9 direct_interc_3_out[0]:8 0.002794643 +5 direct_interc_3_out[0]:10 direct_interc_3_out[0]:9 0.0045 +6 direct_interc_3_out[0]:8 direct_interc_3_out[0]:7 0.0045 +7 direct_interc_3_out[0]:7 direct_interc_3_out[0]:6 0.01860268 +8 direct_interc_3_out[0]:4 direct_interc_3_out[0]:3 0.0015625 +9 direct_interc_3_out[0]:5 direct_interc_3_out[0]:4 0.0045 +10 direct_interc_3_out[0]:3 direct_interc_3_out[0]:2 0.0045 +11 direct_interc_3_out[0]:2 grid_clb_1__1_:top_width_0_height_0__pin_33_[0] 0.02036161 +12 direct_interc_3_out[0]:6 direct_interc_3_out[0]:5 0.04445983 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_46_lower[0] 0.001177062 //LENGTH 11.020 LUMPCC 0.0002811435 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_46_lower[0] O *L 0 *C 522.100 380.870 +*I sb_1__0_:left_top_grid_pin_46_[0] I *L 0 *C 522.100 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_46_lower[0] 0.0004479594 +1 sb_1__0_:left_top_grid_pin_46_[0] 0.0004479594 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_46_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0001405717 +3 sb_1__0_:left_top_grid_pin_46_[0] sb_1__0_:left_top_grid_pin_47_[0] 0.0001405717 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_46_lower[0] sb_1__0_:left_top_grid_pin_46_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_49_lower[0] 0.001182156 //LENGTH 11.020 LUMPCC 0.000318454 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] O *L 0 *C 530.380 380.870 +*I sb_1__0_:left_top_grid_pin_49_[0] I *L 0 *C 530.380 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] 0.0004318508 +1 sb_1__0_:left_top_grid_pin_49_[0] 0.0004318508 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] 2.046466e-05 +3 sb_1__0_:left_top_grid_pin_49_[0] sb_1__0_:left_top_grid_pin_42_[0] 2.046466e-05 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_48_lower[0] 0.0001387623 +5 sb_1__0_:left_top_grid_pin_49_[0] sb_1__0_:left_top_grid_pin_48_[0] 0.0001387623 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] sb_1__0_:left_top_grid_pin_49_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_ccff_tail[0] 0.001254531 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_1__1_:ccff_tail[0] O *L 0 *C 540.810 421.600 +*I cby_1__1_:ccff_head[0] I *L 0 *C 548.470 421.600 + +*CAP +0 grid_clb_1__1_:ccff_tail[0] 0.0006272656 +1 cby_1__1_:ccff_head[0] 0.0006272656 + +*RES +0 grid_clb_1__1_:ccff_tail[0] cby_1__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_35_upper[0] 0.00146448 //LENGTH 7.660 LUMPCC 0.00037102 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] O *L 0 *C 540.810 535.840 +*I sb_1__1_:bottom_left_grid_pin_35_[0] I *L 0 *C 548.470 535.840 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] 0.0005467299 +1 sb_1__1_:bottom_left_grid_pin_35_[0] 0.0005467299 +2 grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] 6.537135e-05 +3 sb_1__1_:bottom_left_grid_pin_35_[0] sb_1__1_:bottom_left_grid_pin_34_[0] 6.537135e-05 +4 grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_36_upper[0] 0.0001201387 +5 sb_1__1_:bottom_left_grid_pin_35_[0] sb_1__1_:bottom_left_grid_pin_36_[0] 0.0001201387 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] sb_1__1_:bottom_left_grid_pin_35_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_39_lower[0] 0.001411409 //LENGTH 7.660 LUMPCC 0.0005580278 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] O *L 0 *C 540.810 390.320 +*I sb_1__0_:top_left_grid_pin_39_[0] I *L 0 *C 548.470 390.320 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] 0.0004266906 +1 sb_1__0_:top_left_grid_pin_39_[0] 0.0004266906 +2 grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] 0.0001418794 +3 sb_1__0_:top_left_grid_pin_39_[0] sb_1__0_:top_left_grid_pin_38_[0] 0.0001418794 +4 grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] 0.0001371345 +5 sb_1__0_:top_left_grid_pin_39_[0] sb_1__0_:top_left_grid_pin_40_[0] 0.0001371345 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] sb_1__0_:top_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_44_upper[0] 0.001162601 //LENGTH 11.020 LUMPCC 0.0002848384 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_44_upper[0] O *L 0 *C 397.900 641.990 +*I sb_0__1_:right_top_grid_pin_44_[0] I *L 0 *C 397.900 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_44_upper[0] 0.0004388814 +1 sb_0__1_:right_top_grid_pin_44_[0] 0.0004388814 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_44_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0001424192 +3 sb_0__1_:right_top_grid_pin_44_[0] sb_0__1_:right_top_grid_pin_42_[0] 0.0001424192 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_44_upper[0] sb_0__1_:right_top_grid_pin_44_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_48_lower[0] 0.001169683 //LENGTH 11.020 LUMPCC 0.000280934 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_48_lower[0] O *L 0 *C 531.300 641.990 +*I sb_1__1_:left_top_grid_pin_48_[0] I *L 0 *C 531.300 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_48_lower[0] 0.0004443746 +1 sb_1__1_:left_top_grid_pin_48_[0] 0.0004443746 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_48_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] 0.000140467 +3 sb_1__1_:left_top_grid_pin_48_[0] sb_1__1_:left_top_grid_pin_49_[0] 0.000140467 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_48_lower[0] sb_1__1_:left_top_grid_pin_48_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_34_upper[0] 0.001527409 //LENGTH 7.660 LUMPCC 0.0003161471 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] O *L 0 *C 540.810 799.000 +*I sb_1__2_:bottom_left_grid_pin_34_[0] I *L 0 *C 548.470 799.000 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] 0.0006056311 +1 sb_1__2_:bottom_left_grid_pin_34_[0] 0.0006056311 +2 grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] 5.850615e-05 +3 sb_1__2_:bottom_left_grid_pin_34_[0] sb_1__2_:bottom_left_grid_pin_35_[0] 5.850615e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] 9.956743e-05 +5 sb_1__2_:bottom_left_grid_pin_34_[0] sb_1__2_:bottom_left_grid_pin_39_[0] 9.956743e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] sb_1__2_:bottom_left_grid_pin_34_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_39_upper[0] 0.001573714 //LENGTH 7.660 LUMPCC 0.0003982697 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] O *L 0 *C 540.810 800.360 +*I sb_1__2_:bottom_left_grid_pin_39_[0] I *L 0 *C 548.470 800.360 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] 0.0005877223 +1 sb_1__2_:bottom_left_grid_pin_39_[0] 0.0005877223 +2 grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] 9.956743e-05 +3 sb_1__2_:bottom_left_grid_pin_39_[0] sb_1__2_:bottom_left_grid_pin_34_[0] 9.956743e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] 9.956743e-05 +5 sb_1__2_:bottom_left_grid_pin_39_[0] sb_1__2_:bottom_left_grid_pin_40_[0] 9.956743e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] sb_1__2_:bottom_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_42_upper[0] 0.001252426 //LENGTH 11.020 LUMPCC 0.0005678821 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] O *L 0 *C 658.260 380.870 +*I sb_1__0_:right_top_grid_pin_42_[0] I *L 0 *C 658.260 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] 0.000342272 +1 sb_1__0_:right_top_grid_pin_42_[0] 0.000342272 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_44_upper[0] 0.0001419705 +3 sb_1__0_:right_top_grid_pin_42_[0] sb_1__0_:right_top_grid_pin_44_[0] 0.0001419705 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0001419705 +5 sb_1__0_:right_top_grid_pin_42_[0] sb_1__0_:right_top_grid_pin_45_[0] 0.0001419705 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] sb_1__0_:right_top_grid_pin_42_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_47_upper[0] 0.001367506 //LENGTH 7.660 LUMPCC 0.0007271298 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] O *L 0 *C 640.470 384.200 +*I sb_1__0_:right_top_grid_pin_47_[0] I *L 0 *C 632.810 384.200 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] 0.0003201879 +1 sb_1__0_:right_top_grid_pin_47_[0] 0.0003201879 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_46_upper[0] 1.506677e-05 +3 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 2.415562e-06 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 0.0003460826 +5 sb_1__0_:right_top_grid_pin_47_[0] sb_1__0_:right_top_grid_pin_46_[0] 2.415562e-06 +6 sb_1__0_:right_top_grid_pin_47_[0] grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 0.0003460826 +7 sb_1__0_:right_top_grid_pin_47_[0] grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 1.506677e-05 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] sb_1__0_:right_top_grid_pin_47_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_36_lower[0] 0.002063168 //LENGTH 15.080 LUMPCC 0.0003696338 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_36_lower[0] O *L 0 *C 802.090 393.720 +*I sb_2__0_:top_left_grid_pin_36_[0] I *L 0 *C 809.750 387.600 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 *C 808.228 387.600 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:3 *C 808.220 387.658 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:4 *C 808.220 392.983 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 *C 808.213 393.040 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 *C 803.620 393.040 +*N grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 *C 803.620 393.720 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_36_lower[0] 0.0001256047 +1 sb_2__0_:top_left_grid_pin_36_[0] 0.0001073074 +2 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 0.0001073074 +3 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:3 0.0003043523 +4 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:4 0.0003043523 +5 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 0.0002667896 +6 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 0.000309503 +7 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 0.0001683181 +8 sb_2__0_:top_left_grid_pin_36_[0] sb_2__0_:left_top_grid_pin_43_[0] 1.669889e-05 +9 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] 1.669889e-05 +10 grid_clb_2__1_:right_width_0_height_0__pin_36_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] 1.139335e-05 +11 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 sb_2__0_:top_left_grid_pin_38_[0] 0.000122113 +12 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 sb_2__0_:top_left_grid_pin_38_[0] 1.139335e-05 +13 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] 0.000122113 +14 sb_2__0_:top_left_grid_pin_36_[0] sb_2__0_:top_left_grid_pin_40_[0] 3.461167e-05 +15 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] 3.461167e-05 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_36_lower[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 0.0002397 +1 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 0.00341 +2 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 sb_2__0_:top_left_grid_pin_36_[0] 0.000238525 +3 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:4 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:3 0.004754464 +4 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:4 0.00341 +5 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:7 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 0.0001065333 +6 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:6 grid_clb_2_right_width_0_height_0__pin_36_lower[0]:5 0.0007194916 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_42_upper[0] 0.001254207 //LENGTH 11.020 LUMPCC 0.0005577554 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] O *L 0 *C 658.260 641.990 +*I sb_1__1_:right_top_grid_pin_42_[0] I *L 0 *C 658.260 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0003482259 +1 sb_1__1_:right_top_grid_pin_42_[0] 0.0003482259 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_44_upper[0] 0.0001394388 +3 sb_1__1_:right_top_grid_pin_42_[0] sb_1__1_:right_top_grid_pin_44_[0] 0.0001394388 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0001394388 +5 sb_1__1_:right_top_grid_pin_42_[0] sb_1__1_:right_top_grid_pin_45_[0] 0.0001394388 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] sb_1__1_:right_top_grid_pin_42_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_47_upper[0] 0.001129765 //LENGTH 7.660 LUMPCC 0.000345612 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_47_upper[0] O *L 0 *C 640.470 645.320 +*I sb_1__1_:right_top_grid_pin_47_[0] I *L 0 *C 632.810 645.320 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_47_upper[0] 0.0003920765 +1 sb_1__1_:right_top_grid_pin_47_[0] 0.0003920765 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_46_upper[0] 0.000172806 +3 sb_1__1_:right_top_grid_pin_47_[0] sb_1__1_:right_top_grid_pin_46_[0] 0.000172806 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_47_upper[0] sb_1__1_:right_top_grid_pin_47_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_51_[0] 0.0006192233 //LENGTH 4.305 LUMPCC 0 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_51_[0] O *L 0 *C 777.400 641.990 +*I direct_interc_4_\/FTB_5__4:A I *L 0.001746 *C 779.700 640.560 +*N grid_clb_3_bottom_width_0_height_0__pin_51_[0]:2 *C 779.700 640.560 +*N grid_clb_3_bottom_width_0_height_0__pin_51_[0]:3 *C 779.700 640.900 +*N grid_clb_3_bottom_width_0_height_0__pin_51_[0]:4 *C 777.445 640.900 +*N grid_clb_3_bottom_width_0_height_0__pin_51_[0]:5 *C 777.400 640.945 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_51_[0] 9.053303e-05 +1 direct_interc_4_\/FTB_5__4:A 1e-06 +2 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:2 6.275756e-05 +3 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:3 0.000202496 +4 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:4 0.0001719037 +5 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:5 9.053303e-05 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_51_[0] grid_clb_3_bottom_width_0_height_0__pin_51_[0]:5 0.0009330357 +1 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:4 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:3 0.002013393 +2 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:5 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:4 0.0045 +3 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:2 direct_interc_4_\/FTB_5__4:A 0.152 +4 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:3 grid_clb_3_bottom_width_0_height_0__pin_51_[0]:2 0.0003035714 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_36_lower[0] 0.001021404 //LENGTH 7.660 LUMPCC 0.0002740146 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] O *L 0 *C 802.090 654.840 +*I sb_2__1_:top_left_grid_pin_36_[0] I *L 0 *C 809.750 654.840 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] 0.0003736949 +1 sb_2__1_:top_left_grid_pin_36_[0] 0.0003736949 +2 grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] 0.0001163217 +3 sb_2__1_:top_left_grid_pin_36_[0] sb_2__1_:top_left_grid_pin_38_[0] 0.0001163217 +4 grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] ctsbuf_net_1221:13 2.06856e-05 +5 sb_2__1_:top_left_grid_pin_36_[0] ctsbuf_net_1221:12 2.06856e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] sb_2__1_:top_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_39_upper[0] 0.001290222 //LENGTH 7.660 LUMPCC 0.0006375762 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] O *L 0 *C 802.090 800.360 +*I sb_2__2_:bottom_left_grid_pin_39_[0] I *L 0 *C 809.750 800.360 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] 0.0003263227 +1 sb_2__2_:bottom_left_grid_pin_39_[0] 0.0003263227 +2 grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] 0.000159394 +3 sb_2__2_:bottom_left_grid_pin_39_[0] sb_2__2_:bottom_left_grid_pin_34_[0] 0.000159394 +4 grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] 0.000159394 +5 sb_2__2_:bottom_left_grid_pin_39_[0] sb_2__2_:bottom_left_grid_pin_40_[0] 0.000159394 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] sb_2__2_:bottom_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0] 0.002289989 //LENGTH 23.680 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_2__0_:top_width_0_height_0__pin_1_lower[0] O *L 0 *C 771.420 282.810 +*I sb_2__0_:left_bottom_grid_pin_1_[0] I *L 0 *C 783.380 293.830 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:2 *C 783.380 289.058 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:3 *C 783.373 289.000 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:4 *C 771.428 289.000 +*N grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:5 *C 771.420 288.942 + +*CAP +0 grid_io_bottom_2__0_:top_width_0_height_0__pin_1_lower[0] 0.0003101398 +1 sb_2__0_:left_bottom_grid_pin_1_[0] 0.0002586851 +2 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:2 0.0002586851 +3 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:3 0.0005761699 +4 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:4 0.0005761699 +5 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:5 0.0003101398 + +*RES +0 grid_io_bottom_2__0_:top_width_0_height_0__pin_1_lower[0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:5 0.005475447 +1 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:2 sb_2__0_:left_bottom_grid_pin_1_[0] 0.004261161 +2 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:3 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:5 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:4 grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]:3 0.001871383 + +*END + +*D_NET grid_io_right_0_ccff_tail[0] 0.003432533 //LENGTH 35.120 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__1_:ccff_tail[0] O *L 0 *C 912.640 408.070 +*I sb_2__0_:ccff_head[0] I *L 0 *C 889.180 397.050 +*N grid_io_right_0_ccff_tail[0]:2 *C 889.180 403.535 +*N grid_io_right_0_ccff_tail[0]:3 *C 889.225 403.580 +*N grid_io_right_0_ccff_tail[0]:4 *C 891.519 403.580 +*N grid_io_right_0_ccff_tail[0]:5 *C 891.520 403.580 +*N grid_io_right_0_ccff_tail[0]:6 *C 912.595 403.580 +*N grid_io_right_0_ccff_tail[0]:7 *C 912.640 403.625 + +*CAP +0 grid_io_right_3__1_:ccff_tail[0] 0.000220384 +1 sb_2__0_:ccff_head[0] 0.0003465185 +2 grid_io_right_0_ccff_tail[0]:2 0.0003465185 +3 grid_io_right_0_ccff_tail[0]:3 0.0001195732 +4 grid_io_right_0_ccff_tail[0]:4 0.0001195732 +5 grid_io_right_0_ccff_tail[0]:5 0.001029791 +6 grid_io_right_0_ccff_tail[0]:6 0.001029791 +7 grid_io_right_0_ccff_tail[0]:7 0.000220384 + +*RES +0 grid_io_right_3__1_:ccff_tail[0] grid_io_right_0_ccff_tail[0]:7 0.00396875 +1 grid_io_right_0_ccff_tail[0]:3 grid_io_right_0_ccff_tail[0]:2 0.0045 +2 grid_io_right_0_ccff_tail[0]:2 sb_2__0_:ccff_head[0] 0.005790179 +3 grid_io_right_0_ccff_tail[0]:6 grid_io_right_0_ccff_tail[0]:5 0.01881696 +4 grid_io_right_0_ccff_tail[0]:7 grid_io_right_0_ccff_tail[0]:6 0.0045 +5 grid_io_right_0_ccff_tail[0]:5 grid_io_right_0_ccff_tail[0]:4 1e-05 +6 grid_io_right_0_ccff_tail[0]:4 grid_io_right_0_ccff_tail[0]:3 0.002048214 + +*END + +*D_NET grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0] 0.002517685 //LENGTH 24.320 LUMPCC 0 DR + +*CONN +*I grid_io_top_1__3_:bottom_width_0_height_0__pin_1_lower[0] O *L 0 *C 510.140 903.110 +*I sb_1__2_:left_top_grid_pin_1_[0] I *L 0 *C 522.100 892.090 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:2 *C 522.100 892.795 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:3 *C 522.055 892.840 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:4 *C 519.845 892.840 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:5 *C 519.800 892.885 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:6 *C 519.800 901.623 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:7 *C 519.793 901.680 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:8 *C 510.148 901.680 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:9 *C 510.140 901.738 + +*CAP +0 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_lower[0] 0.0001048224 +1 sb_1__2_:left_top_grid_pin_1_[0] 5.115504e-05 +2 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:2 5.115504e-05 +3 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:3 0.0001514978 +4 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:4 0.0001514978 +5 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:5 0.0004204404 +6 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:6 0.0004204404 +7 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:7 0.0005309269 +8 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:8 0.0005309269 +9 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:9 0.0001048224 + +*RES +0 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_lower[0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:9 0.001225446 +1 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:9 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:8 0.00341 +2 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:8 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:7 0.00151105 +3 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:6 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:5 0.007801339 +4 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:7 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:6 0.00341 +5 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:4 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:3 0.001973214 +6 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:5 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:4 0.0045 +7 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:3 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:2 0.0045 +8 grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]:2 sb_1__2_:left_top_grid_pin_1_[0] 0.0006294643 + +*END + +*D_NET sb_0__0__0_chanx_right_out[3] 0.001297475 //LENGTH 7.660 LUMPCC 0.0006482415 DR + +*CONN +*I sb_0__0_:chanx_right_out[3] O *L 0 *C 400.050 361.760 +*I cbx_1__0_:chanx_left_in[3] I *L 0 *C 407.710 361.760 + +*CAP +0 sb_0__0_:chanx_right_out[3] 0.0003246166 +1 cbx_1__0_:chanx_left_in[3] 0.0003246166 +2 sb_0__0_:chanx_right_out[3] sb_0__0_:chanx_right_out[1] 0.0001620604 +3 cbx_1__0_:chanx_left_in[3] cbx_1__0_:chanx_left_in[1] 0.0001620604 +4 sb_0__0_:chanx_right_out[3] sb_0__0_:chanx_right_out[12] 0.0001620604 +5 cbx_1__0_:chanx_left_in[3] cbx_1__0_:chanx_left_in[12] 0.0001620604 + +*RES +0 sb_0__0_:chanx_right_out[3] cbx_1__0_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[10] 0.001257582 //LENGTH 7.660 LUMPCC 0.0006928396 DR + +*CONN +*I sb_0__0_:chanx_right_out[10] O *L 0 *C 400.050 318.240 +*I cbx_1__0_:chanx_left_in[10] I *L 0 *C 407.710 318.240 + +*CAP +0 sb_0__0_:chanx_right_out[10] 0.0002823711 +1 cbx_1__0_:chanx_left_in[10] 0.0002823711 +2 sb_0__0_:chanx_right_out[10] sb_0__0_:chanx_right_in[10] 0.0001722401 +3 cbx_1__0_:chanx_left_in[10] cbx_1__0_:chanx_left_out[10] 0.0001722401 +4 sb_0__0_:chanx_right_out[10] sb_0__0_:chanx_right_out[14] 0.0001741797 +5 cbx_1__0_:chanx_left_in[10] cbx_1__0_:chanx_left_in[14] 0.0001741797 + +*RES +0 sb_0__0_:chanx_right_out[10] cbx_1__0_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[19] 0.001175948 //LENGTH 7.660 LUMPCC 0.0004675417 DR + +*CONN +*I sb_0__0_:chanx_right_out[19] O *L 0 *C 400.050 346.800 +*I cbx_1__0_:chanx_left_in[19] I *L 0 *C 407.710 346.800 + +*CAP +0 sb_0__0_:chanx_right_out[19] 0.0003542033 +1 cbx_1__0_:chanx_left_in[19] 0.0003542033 +2 sb_0__0_:chanx_right_out[19] sb_0__0_:chanx_right_out[7] 0.0001721845 +3 cbx_1__0_:chanx_left_in[19] cbx_1__0_:chanx_left_in[7] 0.0001721845 +4 sb_0__0_:chanx_right_out[19] sb_0__0_:chanx_right_out[11] 6.15864e-05 +5 cbx_1__0_:chanx_left_in[19] cbx_1__0_:chanx_left_in[11] 6.15864e-05 + +*RES +0 sb_0__0_:chanx_right_out[19] cbx_1__0_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[8] 0.001513306 //LENGTH 11.180 LUMPCC 0.0009194852 DR + +*CONN +*I sb_0__0_:chany_top_out[8] O *L 0 *C 309.120 396.970 +*I cby_0__1_:chany_bottom_in[8] I *L 0 *C 309.120 408.150 + +*CAP +0 sb_0__0_:chany_top_out[8] 0.0002969106 +1 cby_0__1_:chany_bottom_in[8] 0.0002969106 +2 sb_0__0_:chany_top_out[8] sb_0__0_:chany_top_in[13] 0.0002312706 +3 cby_0__1_:chany_bottom_in[8] cby_0__1_:chany_bottom_out[13] 0.0002312706 +4 sb_0__0_:chany_top_out[8] sb_0__0_:chany_top_out[13] 0.0002284721 +5 cby_0__1_:chany_bottom_in[8] cby_0__1_:chany_bottom_in[13] 0.0002284721 + +*RES +0 sb_0__0_:chany_top_out[8] cby_0__1_:chany_bottom_in[8] 0.001751533 + +*END + +*D_NET sb_0__0__0_chany_top_out[18] 0.0015309 //LENGTH 11.180 LUMPCC 0.0008730351 DR + +*CONN +*I sb_0__0_:chany_top_out[18] O *L 0 *C 334.880 396.970 +*I cby_0__1_:chany_bottom_in[18] I *L 0 *C 334.880 408.150 + +*CAP +0 sb_0__0_:chany_top_out[18] 0.0003289323 +1 cby_0__1_:chany_bottom_in[18] 0.0003289323 +2 sb_0__0_:chany_top_out[18] sb_0__0_:chany_top_in[15] 0.0002182588 +3 cby_0__1_:chany_bottom_in[18] cby_0__1_:chany_bottom_out[15] 0.0002182588 +4 sb_0__0_:chany_top_out[18] sb_0__0_:chany_top_out[15] 0.0002182588 +5 cby_0__1_:chany_bottom_in[18] cby_0__1_:chany_bottom_in[15] 0.0002182588 + +*RES +0 sb_0__0_:chany_top_out[18] cby_0__1_:chany_bottom_in[18] 0.001751533 + +*END + +*D_NET sb_0__1__0_chanx_right_out[4] 0.001179679 //LENGTH 7.660 LUMPCC 0.0004818381 DR + +*CONN +*I sb_0__1_:chanx_right_out[4] O *L 0 *C 400.050 607.920 +*I cbx_1__1_:chanx_left_in[4] I *L 0 *C 407.710 607.920 + +*CAP +0 sb_0__1_:chanx_right_out[4] 0.0003489204 +1 cbx_1__1_:chanx_left_in[4] 0.0003489204 +2 sb_0__1_:chanx_right_out[4] sb_0__1_:chanx_right_out[1] 7.15712e-05 +3 cbx_1__1_:chanx_left_in[4] cbx_1__1_:chanx_left_in[1] 7.15712e-05 +4 sb_0__1_:chanx_right_out[4] sb_0__1_:chanx_right_out[11] 0.0001693479 +5 cbx_1__1_:chanx_left_in[4] cbx_1__1_:chanx_left_in[11] 0.0001693479 + +*RES +0 sb_0__1_:chanx_right_out[4] cbx_1__1_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[12] 0.001229896 //LENGTH 7.660 LUMPCC 0.0006173417 DR + +*CONN +*I sb_0__1_:chanx_right_out[12] O *L 0 *C 400.050 569.840 +*I cbx_1__1_:chanx_left_in[12] I *L 0 *C 407.710 569.840 + +*CAP +0 sb_0__1_:chanx_right_out[12] 0.0003062774 +1 cbx_1__1_:chanx_left_in[12] 0.0003062774 +2 sb_0__1_:chanx_right_out[12] sb_0__1_:chanx_right_in[3] 0.0001140345 +3 cbx_1__1_:chanx_left_in[12] cbx_1__1__0_chanx_left_out[3]:2 0.0001140345 +4 sb_0__1_:chanx_right_out[12] sb_0__1_:chanx_right_in[8] 3.291964e-05 +5 cbx_1__1_:chanx_left_in[12] cbx_1__1_:chanx_left_out[8] 3.291964e-05 +6 sb_0__1_:chanx_right_out[12] sb_0__1_:chanx_right_out[16] 0.0001617167 +7 cbx_1__1_:chanx_left_in[12] cbx_1__1_:chanx_left_in[16] 0.0001617167 + +*RES +0 sb_0__1_:chanx_right_out[12] cbx_1__1_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[0] 0.001290527 //LENGTH 11.020 LUMPCC 0.0005140656 DR + +*CONN +*I sb_0__1_:chany_bottom_out[0] O *L 0 *C 337.180 527.750 +*I cby_0__1_:chany_top_in[0] I *L 0 *C 337.180 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[0] 0.0003882309 +1 cby_0__1_:chany_top_in[0] 0.0003882309 +2 sb_0__1_:chany_bottom_out[0] sb_0__1_:chany_bottom_in[5] 0.0001285164 +3 cby_0__1_:chany_top_in[0] cby_0__1_:chany_top_out[5] 0.0001285164 +4 sb_0__1_:chany_bottom_out[0] sb_0__1_:chany_bottom_out[4] 0.0001285164 +5 cby_0__1_:chany_top_in[0] cby_0__1_:chany_top_in[4] 0.0001285164 + +*RES +0 sb_0__1_:chany_bottom_out[0] cby_0__1_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[8] 0.001286253 //LENGTH 11.020 LUMPCC 0.0005169292 DR + +*CONN +*I sb_0__1_:chany_bottom_out[8] O *L 0 *C 356.500 527.750 +*I cby_0__1_:chany_top_in[8] I *L 0 *C 356.500 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[8] 0.000384662 +1 cby_0__1_:chany_top_in[8] 0.000384662 +2 sb_0__1_:chany_bottom_out[8] sb_0__1_:chany_bottom_out[6] 0.0001292323 +3 cby_0__1_:chany_top_in[8] cby_0__1_:chany_top_in[6] 0.0001292323 +4 sb_0__1_:chany_bottom_out[8] sb_0__1_:chany_bottom_out[7] 0.0001292323 +5 cby_0__1_:chany_top_in[8] cby_0__1_:chany_top_in[7] 0.0001292323 + +*RES +0 sb_0__1_:chany_bottom_out[8] cby_0__1_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[15] 0.001607634 //LENGTH 11.180 LUMPCC 0.0004186922 DR + +*CONN +*I sb_0__1_:chany_bottom_out[15] O *L 0 *C 334.880 527.830 +*I cby_0__1_:chany_top_in[15] I *L 0 *C 334.880 516.650 + +*CAP +0 sb_0__1_:chany_bottom_out[15] 0.0005944712 +1 cby_0__1_:chany_top_in[15] 0.0005944712 +2 sb_0__1_:chany_bottom_out[15] sb_0__1_:chany_bottom_out[13] 0.0001046731 +3 cby_0__1_:chany_top_in[15] cby_0__1_:chany_top_in[13] 0.0001046731 +4 sb_0__1_:chany_bottom_out[15] sb_0__1_:chany_bottom_out[14] 0.0001046731 +5 cby_0__1_:chany_top_in[15] cby_0__1_:chany_top_in[14] 0.0001046731 + +*RES +0 sb_0__1_:chany_bottom_out[15] cby_0__1_:chany_top_in[15] 0.001751533 + +*END + +*D_NET sb_0__1__0_chany_top_out[4] 0.001087551 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I sb_0__1_:chany_top_out[4] O *L 0 *C 323.380 658.170 +*I cby_0__2_:chany_bottom_in[4] I *L 0 *C 323.380 669.190 +*N sb_0__1__0_chany_top_out[4]:2 *C 323.380 667.520 +*N sb_0__1__0_chany_top_out[4]:3 *C 323.380 667.519 + +*CAP +0 sb_0__1_:chany_top_out[4] 0.0004177973 +1 cby_0__2_:chany_bottom_in[4] 0.000125978 +2 sb_0__1__0_chany_top_out[4]:2 0.000125978 +3 sb_0__1__0_chany_top_out[4]:3 0.0004177973 + +*RES +0 sb_0__1_:chany_top_out[4] sb_0__1__0_chany_top_out[4]:3 0.008347322 +1 sb_0__1__0_chany_top_out[4]:2 cby_0__2_:chany_bottom_in[4] 0.001491071 +2 sb_0__1__0_chany_top_out[4]:3 sb_0__1__0_chany_top_out[4]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[9] 0.001514024 //LENGTH 11.180 LUMPCC 0.0004468703 DR + +*CONN +*I sb_0__1_:chany_top_out[9] O *L 0 *C 296.240 658.090 +*I cby_0__2_:chany_bottom_in[9] I *L 0 *C 296.240 669.270 +*N sb_0__1__0_chany_top_out[9]:2 *C 296.240 667.520 +*N sb_0__1__0_chany_top_out[9]:3 *C 296.240 667.519 + +*CAP +0 sb_0__1_:chany_top_out[9] 0.0003224609 +1 cby_0__2_:chany_bottom_in[9] 0.0002111161 +2 sb_0__1__0_chany_top_out[9]:2 0.0002111161 +3 sb_0__1__0_chany_top_out[9]:3 0.0003224609 +4 sb_0__1_:chany_top_out[9] sb_0__1_:chany_top_out[14] 0.0002139862 +5 cby_0__2_:chany_bottom_in[9] cby_0__2_:chany_bottom_in[14] 9.448956e-06 +6 sb_0__1__0_chany_top_out[9]:2 sb_0__1__0_chany_top_out[14]:2 9.448956e-06 +7 sb_0__1__0_chany_top_out[9]:3 sb_0__1__0_chany_top_out[14]:3 0.0002139862 + +*RES +0 sb_0__1_:chany_top_out[9] sb_0__1__0_chany_top_out[9]:3 0.00147721 +1 sb_0__1__0_chany_top_out[9]:2 cby_0__2_:chany_bottom_in[9] 0.0002741666 +2 sb_0__1__0_chany_top_out[9]:3 sb_0__1__0_chany_top_out[9]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[16] 0.001269324 //LENGTH 11.020 LUMPCC 0.0005516617 DR + +*CONN +*I sb_0__1_:chany_top_out[16] O *L 0 *C 335.340 658.170 +*I cby_0__2_:chany_bottom_in[16] I *L 0 *C 335.340 669.190 +*N sb_0__1__0_chany_top_out[16]:2 *C 335.340 667.520 +*N sb_0__1__0_chany_top_out[16]:3 *C 335.340 667.519 + +*CAP +0 sb_0__1_:chany_top_out[16] 0.0002472905 +1 cby_0__2_:chany_bottom_in[16] 0.0001115404 +2 sb_0__1__0_chany_top_out[16]:2 0.0001115404 +3 sb_0__1__0_chany_top_out[16]:3 0.0002472905 +4 sb_0__1_:chany_top_out[16] sb_0__1_:chany_top_in[19] 0.0001307218 +5 cby_0__2_:chany_bottom_in[16] cby_0__2_:chany_bottom_out[19] 7.193657e-06 +6 sb_0__1__0_chany_top_out[16]:2 cby_0__1__1_chany_bottom_out[19]:3 7.193657e-06 +7 sb_0__1__0_chany_top_out[16]:3 cby_0__1__1_chany_bottom_out[19]:2 0.0001307218 +8 sb_0__1_:chany_top_out[16] sb_0__1_:chany_top_out[3] 0.0001307218 +9 cby_0__2_:chany_bottom_in[16] cby_0__2_:chany_bottom_in[3] 7.193657e-06 +10 sb_0__1__0_chany_top_out[16]:2 sb_0__1__0_chany_top_out[3]:2 7.193657e-06 +11 sb_0__1__0_chany_top_out[16]:3 sb_0__1__0_chany_top_out[3]:3 0.0001307218 + +*RES +0 sb_0__1_:chany_top_out[16] sb_0__1__0_chany_top_out[16]:3 0.008347321 +1 sb_0__1__0_chany_top_out[16]:2 cby_0__2_:chany_bottom_in[16] 0.001491072 +2 sb_0__1__0_chany_top_out[16]:3 sb_0__1__0_chany_top_out[16]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[3] 0.001225227 //LENGTH 7.660 LUMPCC 0.0004416103 DR + +*CONN +*I sb_0__2_:chanx_right_out[3] O *L 0 *C 400.050 871.760 +*I cbx_1__2_:chanx_left_in[3] I *L 0 *C 407.710 871.760 + +*CAP +0 sb_0__2_:chanx_right_out[3] 0.0003918081 +1 cbx_1__2_:chanx_left_in[3] 0.0003918081 +2 sb_0__2_:chanx_right_out[3] sb_0__2_:chanx_right_in[10] 5.655564e-05 +3 cbx_1__2_:chanx_left_in[3] cbx_1__2_:chanx_left_out[10] 5.655564e-05 +4 sb_0__2_:chanx_right_out[3] sb_0__2_:chanx_right_out[6] 0.0001642495 +5 cbx_1__2_:chanx_left_in[3] cbx_1__2_:chanx_left_in[6] 0.0001642495 + +*RES +0 sb_0__2_:chanx_right_out[3] cbx_1__2_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[11] 0.001214524 //LENGTH 7.660 LUMPCC 0.0004633063 DR + +*CONN +*I sb_0__2_:chanx_right_out[11] O *L 0 *C 400.050 858.160 +*I cbx_1__2_:chanx_left_in[11] I *L 0 *C 407.710 858.160 + +*CAP +0 sb_0__2_:chanx_right_out[11] 0.0003756087 +1 cbx_1__2_:chanx_left_in[11] 0.0003756087 +2 sb_0__2_:chanx_right_out[11] sb_0__2_:chanx_right_in[19] 6.777188e-05 +3 cbx_1__2_:chanx_left_in[11] cbx_1__2_:chanx_left_out[19] 6.777188e-05 +4 sb_0__2_:chanx_right_out[11] sb_0__2_:chanx_right_out[15] 0.0001638813 +5 cbx_1__2_:chanx_left_in[11] cbx_1__2_:chanx_left_in[15] 0.0001638813 + +*RES +0 sb_0__2_:chanx_right_out[11] cbx_1__2_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[19] 0.001297722 //LENGTH 7.660 LUMPCC 0.0006629855 DR + +*CONN +*I sb_0__2_:chanx_right_out[19] O *L 0 *C 400.050 835.040 +*I cbx_1__2_:chanx_left_in[19] I *L 0 *C 407.710 835.040 + +*CAP +0 sb_0__2_:chanx_right_out[19] 0.000317368 +1 cbx_1__2_:chanx_left_in[19] 0.000317368 +2 sb_0__2_:chanx_right_out[19] sb_0__2_:chanx_right_out[1] 0.0001657464 +3 cbx_1__2_:chanx_left_in[19] cbx_1__2_:chanx_left_in[1] 0.0001657464 +4 sb_0__2_:chanx_right_out[19] sb_0__2_:chanx_right_out[9] 0.0001657464 +5 cbx_1__2_:chanx_left_in[19] cbx_1__2_:chanx_left_in[9] 0.0001657464 + +*RES +0 sb_0__2_:chanx_right_out[19] cbx_1__2_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[6] 0.001258694 //LENGTH 11.020 LUMPCC 0.0005589473 DR + +*CONN +*I sb_0__2_:chany_bottom_out[6] O *L 0 *C 357.420 788.870 +*I cby_0__2_:chany_top_in[6] I *L 0 *C 357.420 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[6] 0.0003498734 +1 cby_0__2_:chany_top_in[6] 0.0003498734 +2 sb_0__2_:chany_bottom_out[6] sb_0__2_:chany_bottom_in[2] 0.0001397368 +3 cby_0__2_:chany_top_in[6] cby_0__2_:chany_top_out[2] 0.0001397368 +4 sb_0__2_:chany_bottom_out[6] sb_0__2_:chany_bottom_out[8] 0.0001397368 +5 cby_0__2_:chany_top_in[6] cby_0__2_:chany_top_in[8] 0.0001397368 + +*RES +0 sb_0__2_:chany_bottom_out[6] cby_0__2_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[14] 0.001551873 //LENGTH 11.180 LUMPCC 0.0004278983 DR + +*CONN +*I sb_0__2_:chany_bottom_out[14] O *L 0 *C 333.040 788.950 +*I cby_0__2_:chany_top_in[14] I *L 0 *C 333.040 777.770 + +*CAP +0 sb_0__2_:chany_bottom_out[14] 0.0005619872 +1 cby_0__2_:chany_top_in[14] 0.0005619872 +2 sb_0__2_:chany_bottom_out[14] sb_0__2_:chany_bottom_out[15] 0.0002139492 +3 cby_0__2_:chany_top_in[14] cby_0__2_:chany_top_in[15] 0.0002139492 + +*RES +0 sb_0__2_:chany_bottom_out[14] cby_0__2_:chany_top_in[14] 0.001751533 + +*END + +*D_NET sb_1__0__0_chanx_left_out[1] 0.001330024 //LENGTH 7.660 LUMPCC 0.0004107092 DR + +*CONN +*I sb_1__0_:chanx_left_out[1] O *L 0 *C 519.950 358.360 +*I cbx_1__0_:chanx_right_in[1] I *L 0 *C 512.290 358.360 + +*CAP +0 sb_1__0_:chanx_left_out[1] 0.0004596576 +1 cbx_1__0_:chanx_right_in[1] 0.0004596576 +2 sb_1__0_:chanx_left_out[1] sb_1__0_:chanx_left_in[4] 6.380571e-05 +3 cbx_1__0_:chanx_right_in[1] cbx_1__0__0_chanx_right_out[4]:2 6.380571e-05 +4 sb_1__0_:chanx_left_out[1] sb_1__0_:chanx_left_out[13] 0.0001415489 +5 cbx_1__0_:chanx_right_in[1] cbx_1__0_:chanx_right_in[13] 0.0001415489 + +*RES +0 sb_1__0_:chanx_left_out[1] cbx_1__0_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[9] 0.001243659 //LENGTH 7.660 LUMPCC 0.0004521425 DR + +*CONN +*I sb_1__0_:chanx_left_out[9] O *L 0 *C 519.950 327.760 +*I cbx_1__0_:chanx_right_in[9] I *L 0 *C 512.290 327.760 + +*CAP +0 sb_1__0_:chanx_left_out[9] 0.0003957583 +1 cbx_1__0_:chanx_right_in[9] 0.0003957583 +2 sb_1__0_:chanx_left_out[9] sb_1__0_:chanx_left_in[8] 0.000159936 +3 cbx_1__0_:chanx_right_in[9] cbx_1__0_:chanx_right_out[8] 0.000159936 +4 sb_1__0_:chanx_left_out[9] sb_1__0_:chanx_left_in[12] 6.613527e-05 +5 cbx_1__0_:chanx_right_in[9] cbx_1__0_:chanx_right_out[12] 6.613527e-05 + +*RES +0 sb_1__0_:chanx_left_out[9] cbx_1__0_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[18] 0.001272958 //LENGTH 7.660 LUMPCC 0.0003573906 DR + +*CONN +*I sb_1__0_:chanx_left_out[18] O *L 0 *C 519.950 303.960 +*I cbx_1__0_:chanx_right_in[18] I *L 0 *C 512.290 303.960 + +*CAP +0 sb_1__0_:chanx_left_out[18] 0.0004577837 +1 cbx_1__0_:chanx_right_in[18] 0.0004577837 +2 sb_1__0_:chanx_left_out[18] sb_1__0_:chanx_left_in[14] 4.231682e-06 +3 sb_1__0_:chanx_left_out[18] cbx_1__0__0_chanx_right_out[14]:3 2.448635e-05 +4 cbx_1__0_:chanx_right_in[18] cbx_1__0__0_chanx_right_out[14]:2 4.231682e-06 +5 cbx_1__0_:chanx_right_in[18] cbx_1__0__0_chanx_right_out[14]:4 2.448635e-05 +6 sb_1__0_:chanx_left_out[18] sb_1__0_:chanx_left_out[4] 0.0001499772 +7 cbx_1__0_:chanx_right_in[18] cbx_1__0_:chanx_right_in[4] 0.0001499772 + +*RES +0 sb_1__0_:chanx_left_out[18] cbx_1__0_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[6] 0.001342728 //LENGTH 7.660 LUMPCC 0.0004141149 DR + +*CONN +*I sb_1__0_:chanx_right_out[6] O *L 0 *C 661.330 322.320 +*I cbx_2__0_:chanx_left_in[6] I *L 0 *C 668.990 322.320 +*N sb_1__0__0_chanx_right_out[6]:2 *C 667.520 322.320 +*N sb_1__0__0_chanx_right_out[6]:3 *C 667.519 322.320 + +*CAP +0 sb_1__0_:chanx_right_out[6] 0.0002902089 +1 cbx_2__0_:chanx_left_in[6] 0.0001740976 +2 sb_1__0__0_chanx_right_out[6]:2 0.0001740976 +3 sb_1__0__0_chanx_right_out[6]:3 0.0002902089 +4 sb_1__0_:chanx_right_out[6] sb_1__0_:chanx_right_in[10] 6.280022e-05 +5 sb_1__0__0_chanx_right_out[6]:3 cbx_1__0__1_chanx_left_out[10]:2 6.280022e-05 +6 sb_1__0_:chanx_right_out[6] sb_1__0_:chanx_right_in[11] 0.0001343942 +7 cbx_2__0_:chanx_left_in[6] cbx_2__0_:chanx_left_out[11] 9.863077e-06 +8 sb_1__0__0_chanx_right_out[6]:2 cbx_1__0__1_chanx_left_out[11]:3 9.863077e-06 +9 sb_1__0__0_chanx_right_out[6]:3 cbx_1__0__1_chanx_left_out[11]:2 0.0001343942 + +*RES +0 sb_1__0_:chanx_right_out[6] sb_1__0__0_chanx_right_out[6]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[6]:2 cbx_2__0_:chanx_left_in[6] 0.0002303 +2 sb_1__0__0_chanx_right_out[6]:3 sb_1__0__0_chanx_right_out[6]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[14] 0.001370364 //LENGTH 7.660 LUMPCC 0.0003705291 DR + +*CONN +*I sb_1__0_:chanx_right_out[14] O *L 0 *C 661.330 316.880 +*I cbx_2__0_:chanx_left_in[14] I *L 0 *C 668.990 316.880 +*N sb_1__0__0_chanx_right_out[14]:2 *C 667.520 316.880 +*N sb_1__0__0_chanx_right_out[14]:3 *C 667.519 316.880 + +*CAP +0 sb_1__0_:chanx_right_out[14] 0.0002904156 +1 cbx_2__0_:chanx_left_in[14] 0.0002095016 +2 sb_1__0__0_chanx_right_out[14]:2 0.0002095016 +3 sb_1__0__0_chanx_right_out[14]:3 0.0002904156 +4 sb_1__0_:chanx_right_out[14] sb_1__0_:chanx_right_out[10] 0.0001209859 +5 sb_1__0__0_chanx_right_out[14]:3 sb_1__0__0_chanx_right_out[10]:3 0.0001209859 +6 sb_1__0_:chanx_right_out[14] sb_1__0_:chanx_right_out[18] 6.427868e-05 +7 sb_1__0__0_chanx_right_out[14]:3 sb_1__0__0_chanx_right_out[18]:3 6.427868e-05 + +*RES +0 sb_1__0_:chanx_right_out[14] sb_1__0__0_chanx_right_out[14]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[14]:2 cbx_2__0_:chanx_left_in[14] 0.0002303 +2 sb_1__0__0_chanx_right_out[14]:3 sb_1__0__0_chanx_right_out[14]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[1] 0.001236797 //LENGTH 11.020 LUMPCC 0.0005813158 DR + +*CONN +*I sb_1__0_:chany_top_out[1] O *L 0 *C 580.980 397.050 +*I cby_1__1_:chany_bottom_in[1] I *L 0 *C 580.980 408.070 + +*CAP +0 sb_1__0_:chany_top_out[1] 0.0003277404 +1 cby_1__1_:chany_bottom_in[1] 0.0003277404 +2 sb_1__0_:chany_top_out[1] sb_1__0_:chany_top_in[5] 0.000145329 +3 cby_1__1_:chany_bottom_in[1] cby_1__1_:chany_bottom_out[5] 0.000145329 +4 sb_1__0_:chany_top_out[1] sb_1__0_:chany_top_out[17] 0.000145329 +5 cby_1__1_:chany_bottom_in[1] cby_1__1_:chany_bottom_in[17] 0.000145329 + +*RES +0 sb_1__0_:chany_top_out[1] cby_1__1_:chany_bottom_in[1] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[9] 0.00123682 //LENGTH 11.020 LUMPCC 0.0005952134 DR + +*CONN +*I sb_1__0_:chany_top_out[9] O *L 0 *C 578.220 397.050 +*I cby_1__1_:chany_bottom_in[9] I *L 0 *C 578.220 408.070 + +*CAP +0 sb_1__0_:chany_top_out[9] 0.0003208035 +1 cby_1__1_:chany_bottom_in[9] 0.0003208035 +2 sb_1__0_:chany_top_out[9] sb_1__0_:chany_top_in[1] 0.0001522778 +3 cby_1__1_:chany_bottom_in[9] cby_1__1_:chany_bottom_out[1] 0.0001522778 +4 sb_1__0_:chany_top_out[9] sb_1__0_:chany_top_in[19] 0.000145329 +5 cby_1__1_:chany_bottom_in[9] cby_1__1_:chany_bottom_out[19] 0.000145329 + +*RES +0 sb_1__0_:chany_top_out[9] cby_1__1_:chany_bottom_in[9] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[16] 0.00107323 //LENGTH 11.020 LUMPCC 9.644519e-05 DR + +*CONN +*I sb_1__0_:chany_top_out[16] O *L 0 *C 606.740 397.050 +*I cby_1__1_:chany_bottom_in[16] I *L 0 *C 606.740 408.070 + +*CAP +0 sb_1__0_:chany_top_out[16] 0.0004883925 +1 cby_1__1_:chany_bottom_in[16] 0.0004883925 +2 sb_1__0_:chany_top_out[16] sb_1__0_:chany_top_in[18] 4.82226e-05 +3 cby_1__1_:chany_bottom_in[16] cby_1__1_:chany_bottom_out[18] 4.82226e-05 + +*RES +0 sb_1__0_:chany_top_out[16] cby_1__1_:chany_bottom_in[16] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[3] 0.001299869 //LENGTH 7.660 LUMPCC 0.0003854614 DR + +*CONN +*I sb_1__1_:chanx_left_out[3] O *L 0 *C 519.950 602.480 +*I cbx_1__1_:chanx_right_in[3] I *L 0 *C 512.290 602.480 + +*CAP +0 sb_1__1_:chanx_left_out[3] 0.000457204 +1 cbx_1__1_:chanx_right_in[3] 0.000457204 +2 sb_1__1_:chanx_left_out[3] sb_1__1_:chanx_left_in[0] 0.0001429073 +3 cbx_1__1_:chanx_right_in[3] cbx_1__1_:chanx_right_out[0] 0.0001429073 +4 sb_1__1_:chanx_left_out[3] sb_1__1_:chanx_left_in[9] 4.982339e-05 +5 cbx_1__1_:chanx_right_in[3] cbx_1__1_:chanx_right_out[9] 4.982339e-05 + +*RES +0 sb_1__1_:chanx_left_out[3] cbx_1__1_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[10] 0.001339983 //LENGTH 7.660 LUMPCC 0.0005234776 DR + +*CONN +*I sb_1__1_:chanx_left_out[10] O *L 0 *C 519.950 580.720 +*I cbx_1__1_:chanx_right_in[10] I *L 0 *C 512.290 580.720 + +*CAP +0 sb_1__1_:chanx_left_out[10] 0.0004082528 +1 cbx_1__1_:chanx_right_in[10] 0.0004082528 +2 sb_1__1_:chanx_left_out[10] sb_1__1_:chanx_left_in[16] 0.0001112282 +3 cbx_1__1_:chanx_right_in[10] cbx_1__1__0_chanx_right_out[16]:2 0.0001112282 +4 sb_1__1_:chanx_left_out[10] sb_1__1_:chanx_left_out[14] 0.0001505106 +5 cbx_1__1_:chanx_right_in[10] cbx_1__1_:chanx_right_in[14] 0.0001505106 + +*RES +0 sb_1__1_:chanx_left_out[10] cbx_1__1_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[0] 0.001502678 //LENGTH 7.660 LUMPCC 0.0004638099 DR + +*CONN +*I sb_1__1_:chanx_right_out[0] O *L 0 *C 661.330 612.000 +*I cbx_2__1_:chanx_left_in[0] I *L 0 *C 668.990 612.000 +*N sb_1__1__0_chanx_right_out[0]:2 *C 667.520 612.000 +*N sb_1__1__0_chanx_right_out[0]:3 *C 667.519 612.000 + +*CAP +0 sb_1__1_:chanx_right_out[0] 0.0003187626 +1 cbx_2__1_:chanx_left_in[0] 0.0002006711 +2 sb_1__1__0_chanx_right_out[0]:2 0.0002006711 +3 sb_1__1__0_chanx_right_out[0]:3 0.0003187626 +4 sb_1__1_:chanx_right_out[0] sb_1__1_:chanx_right_out[1] 0.0001179583 +5 cbx_2__1_:chanx_left_in[0] cbx_2__1_:chanx_left_in[1] 6.576453e-06 +6 sb_1__1__0_chanx_right_out[0]:2 sb_1__1__0_chanx_right_out[1]:2 6.576453e-06 +7 sb_1__1__0_chanx_right_out[0]:3 sb_1__1__0_chanx_right_out[1]:3 0.0001179583 +8 sb_1__1_:chanx_right_out[0] sb_1__1_:chanx_right_out[13] 0.0001073702 +9 sb_1__1__0_chanx_right_out[0]:3 sb_1__1__0_chanx_right_out[13]:3 0.0001073702 + +*RES +0 sb_1__1_:chanx_right_out[0] sb_1__1__0_chanx_right_out[0]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[0]:2 cbx_2__1_:chanx_left_in[0] 0.0002303 +2 sb_1__1__0_chanx_right_out[0]:3 sb_1__1__0_chanx_right_out[0]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[7] 0.001500088 //LENGTH 7.660 LUMPCC 0.0004635781 DR + +*CONN +*I sb_1__1_:chanx_right_out[7] O *L 0 *C 661.330 563.040 +*I cbx_2__1_:chanx_left_in[7] I *L 0 *C 668.990 563.040 +*N sb_1__1__0_chanx_right_out[7]:2 *C 667.520 563.040 +*N sb_1__1__0_chanx_right_out[7]:3 *C 667.519 563.040 + +*CAP +0 sb_1__1_:chanx_right_out[7] 0.0003144187 +1 cbx_2__1_:chanx_left_in[7] 0.0002038362 +2 sb_1__1__0_chanx_right_out[7]:2 0.0002038362 +3 sb_1__1__0_chanx_right_out[7]:3 0.0003144187 +4 sb_1__1_:chanx_right_out[7] sb_1__1_:chanx_right_in[10] 0.0001104926 +5 cbx_2__1_:chanx_left_in[7] cbx_2__1_:chanx_left_out[10] 6.577123e-06 +6 sb_1__1__0_chanx_right_out[7]:2 cbx_1__1__1_chanx_left_out[10]:3 6.577123e-06 +7 sb_1__1__0_chanx_right_out[7]:3 cbx_1__1__1_chanx_left_out[10]:2 0.0001104926 +8 sb_1__1_:chanx_right_out[7] sb_1__1_:chanx_right_in[17] 0.0001147194 +9 sb_1__1__0_chanx_right_out[7]:3 cbx_1__1__1_chanx_left_out[17]:2 0.0001147194 + +*RES +0 sb_1__1_:chanx_right_out[7] sb_1__1__0_chanx_right_out[7]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[7]:2 cbx_2__1_:chanx_left_in[7] 0.0002303 +2 sb_1__1__0_chanx_right_out[7]:3 sb_1__1__0_chanx_right_out[7]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[15] 0.001549111 //LENGTH 7.660 LUMPCC 0.0004390898 DR + +*CONN +*I sb_1__1_:chanx_right_out[15] O *L 0 *C 661.330 595.680 +*I cbx_2__1_:chanx_left_in[15] I *L 0 *C 668.990 595.680 +*N sb_1__1__0_chanx_right_out[15]:2 *C 667.520 595.680 +*N sb_1__1__0_chanx_right_out[15]:3 *C 667.519 595.680 + +*CAP +0 sb_1__1_:chanx_right_out[15] 0.000334985 +1 cbx_2__1_:chanx_left_in[15] 0.0002200254 +2 sb_1__1__0_chanx_right_out[15]:2 0.0002200254 +3 sb_1__1__0_chanx_right_out[15]:3 0.000334985 +4 sb_1__1_:chanx_right_out[15] sb_1__1_:chanx_right_in[7] 0.0001097725 +5 sb_1__1__0_chanx_right_out[15]:3 cbx_1__1__1_chanx_left_out[7]:2 0.0001097725 +6 sb_1__1_:chanx_right_out[15] sb_1__1_:chanx_right_out[17] 0.0001097725 +7 sb_1__1__0_chanx_right_out[15]:3 sb_1__1__0_chanx_right_out[17]:3 0.0001097725 + +*RES +0 sb_1__1_:chanx_right_out[15] sb_1__1__0_chanx_right_out[15]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[15]:2 cbx_2__1_:chanx_left_in[15] 0.0002303 +2 sb_1__1__0_chanx_right_out[15]:3 sb_1__1__0_chanx_right_out[15]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[3] 0.00128887 //LENGTH 11.020 LUMPCC 0.0005102205 DR + +*CONN +*I sb_1__1_:chany_bottom_out[3] O *L 0 *C 588.800 527.750 +*I cby_1__1_:chany_top_in[3] I *L 0 *C 588.800 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[3] 0.0003893248 +1 cby_1__1_:chany_top_in[3] 0.0003893248 +2 sb_1__1_:chany_bottom_out[3] sb_1__1_:chany_bottom_in[13] 0.0001275551 +3 cby_1__1_:chany_top_in[3] cby_1__1_:chany_top_out[13] 0.0001275551 +4 sb_1__1_:chany_bottom_out[3] sb_1__1_:chany_bottom_in[17] 0.0001275551 +5 cby_1__1_:chany_top_in[3] cby_1__1_:chany_top_out[17] 0.0001275551 + +*RES +0 sb_1__1_:chany_bottom_out[3] cby_1__1_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[12] 0.001288243 //LENGTH 11.020 LUMPCC 0.0005108983 DR + +*CONN +*I sb_1__1_:chany_bottom_out[12] O *L 0 *C 600.300 527.750 +*I cby_1__1_:chany_top_in[12] I *L 0 *C 600.300 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[12] 0.0003886723 +1 cby_1__1_:chany_top_in[12] 0.0003886723 +2 sb_1__1_:chany_bottom_out[12] sb_1__1_:chany_bottom_in[2] 0.0001289014 +3 cby_1__1_:chany_top_in[12] cby_1__1_:chany_top_out[2] 0.0001289014 +4 sb_1__1_:chany_bottom_out[12] sb_1__1_:chany_bottom_in[12] 0.0001265478 +5 cby_1__1_:chany_top_in[12] cby_1__1_:chany_top_out[12] 0.0001265478 + +*RES +0 sb_1__1_:chany_bottom_out[12] cby_1__1_:chany_top_in[12] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[19] 0.00128887 //LENGTH 11.020 LUMPCC 0.0005102205 DR + +*CONN +*I sb_1__1_:chany_bottom_out[19] O *L 0 *C 590.640 527.750 +*I cby_1__1_:chany_top_in[19] I *L 0 *C 590.640 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[19] 0.0003893248 +1 cby_1__1_:chany_top_in[19] 0.0003893248 +2 sb_1__1_:chany_bottom_out[19] sb_1__1_:chany_bottom_in[17] 0.0001275551 +3 cby_1__1_:chany_top_in[19] cby_1__1_:chany_top_out[17] 0.0001275551 +4 sb_1__1_:chany_bottom_out[19] sb_1__1_:chany_bottom_out[5] 0.0001275551 +5 cby_1__1_:chany_top_in[19] cby_1__1_:chany_top_in[5] 0.0001275551 + +*RES +0 sb_1__1_:chany_bottom_out[19] cby_1__1_:chany_top_in[19] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[7] 0.001379218 //LENGTH 12.500 LUMPCC 0.0003326005 DR + +*CONN +*I sb_1__1_:chany_top_out[7] O *L 0 *C 569.940 658.170 +*I cby_1__2_:chany_bottom_in[7] I *L 0 *C 569.940 669.190 +*N sb_1__1__0_chany_top_out[7]:2 *C 569.940 667.520 +*N sb_1__1__0_chany_top_out[7]:3 *C 569.940 667.519 +*N sb_1__1__0_chany_top_out[7]:4 *C 569.940 667.080 +*N sb_1__1__0_chany_top_out[7]:5 *C 570.400 667.080 +*N sb_1__1__0_chany_top_out[7]:6 *C 570.400 664.700 +*N sb_1__1__0_chany_top_out[7]:7 *C 569.940 664.700 + +*CAP +0 sb_1__1_:chany_top_out[7] 0.0002351427 +1 cby_1__2_:chany_bottom_in[7] 0.0001192524 +2 sb_1__1__0_chany_top_out[7]:2 0.0001192524 +3 sb_1__1__0_chany_top_out[7]:3 2.04498e-05 +4 sb_1__1__0_chany_top_out[7]:4 4.748977e-05 +5 sb_1__1__0_chany_top_out[7]:5 0.0001243581 +6 sb_1__1__0_chany_top_out[7]:6 0.0001214238 +7 sb_1__1__0_chany_top_out[7]:7 0.0002592484 +8 sb_1__1_:chany_top_out[7] sb_1__1_:chany_top_out[15] 8.626484e-05 +9 cby_1__2_:chany_bottom_in[7] cby_1__2_:chany_bottom_in[15] 7.340376e-06 +10 sb_1__1__0_chany_top_out[7]:7 sb_1__1__0_chany_top_out[15]:3 8.626484e-05 +11 sb_1__1__0_chany_top_out[7]:6 sb_1__1_:chany_top_out[15] 6.935558e-05 +12 sb_1__1__0_chany_top_out[7]:4 sb_1__1_:chany_top_out[15] 3.339434e-06 +13 sb_1__1__0_chany_top_out[7]:5 sb_1__1__0_chany_top_out[15]:3 6.935558e-05 +14 sb_1__1__0_chany_top_out[7]:2 sb_1__1__0_chany_top_out[15]:2 7.340376e-06 +15 sb_1__1__0_chany_top_out[7]:3 sb_1__1__0_chany_top_out[15]:3 3.339434e-06 + +*RES +0 sb_1__1_:chany_top_out[7] sb_1__1__0_chany_top_out[7]:7 0.005830358 +1 sb_1__1__0_chany_top_out[7]:7 sb_1__1__0_chany_top_out[7]:6 0.0004107143 +2 sb_1__1__0_chany_top_out[7]:6 sb_1__1__0_chany_top_out[7]:5 0.002125 +3 sb_1__1__0_chany_top_out[7]:4 sb_1__1__0_chany_top_out[7]:3 0.0003919643 +4 sb_1__1__0_chany_top_out[7]:5 sb_1__1__0_chany_top_out[7]:4 0.0004107143 +5 sb_1__1__0_chany_top_out[7]:2 cby_1__2_:chany_bottom_in[7] 0.001491071 +6 sb_1__1__0_chany_top_out[7]:3 sb_1__1__0_chany_top_out[7]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[17] 0.001209579 //LENGTH 11.020 LUMPCC 0.0004685805 DR + +*CONN +*I sb_1__1_:chany_top_out[17] O *L 0 *C 581.900 658.170 +*I cby_1__2_:chany_bottom_in[17] I *L 0 *C 581.900 669.190 +*N sb_1__1__0_chany_top_out[17]:2 *C 581.900 667.520 +*N sb_1__1__0_chany_top_out[17]:3 *C 581.900 667.519 + +*CAP +0 sb_1__1_:chany_top_out[17] 0.0002508363 +1 cby_1__2_:chany_bottom_in[17] 0.0001196628 +2 sb_1__1__0_chany_top_out[17]:2 0.0001196628 +3 sb_1__1__0_chany_top_out[17]:3 0.0002508363 +4 sb_1__1_:chany_top_out[17] sb_1__1_:chany_top_in[13] 9.026287e-05 +5 cby_1__2_:chany_bottom_in[17] cby_1__2_:chany_bottom_out[13] 5.882677e-07 +6 sb_1__1__0_chany_top_out[17]:2 cby_1__1__1_chany_bottom_out[13]:3 5.882677e-07 +7 sb_1__1__0_chany_top_out[17]:3 cby_1__1__1_chany_bottom_out[13]:2 9.026287e-05 +8 sb_1__1_:chany_top_out[17] sb_1__1_:chany_top_out[1] 0.0001361438 +9 cby_1__2_:chany_bottom_in[17] cby_1__2_:chany_bottom_in[1] 7.295327e-06 +10 sb_1__1__0_chany_top_out[17]:2 sb_1__1__0_chany_top_out[1]:2 7.295327e-06 +11 sb_1__1__0_chany_top_out[17]:3 sb_1__1__0_chany_top_out[1]:3 0.0001361438 + +*RES +0 sb_1__1_:chany_top_out[17] sb_1__1__0_chany_top_out[17]:3 0.008347322 +1 sb_1__1__0_chany_top_out[17]:2 cby_1__2_:chany_bottom_in[17] 0.001491072 +2 sb_1__1__0_chany_top_out[17]:3 sb_1__1__0_chany_top_out[17]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[5] 0.001388957 //LENGTH 7.660 LUMPCC 0.0005680365 DR + +*CONN +*I sb_1__2_:chanx_left_out[5] O *L 0 *C 519.950 859.520 +*I cbx_1__2_:chanx_right_in[5] I *L 0 *C 512.290 859.520 + +*CAP +0 sb_1__2_:chanx_left_out[5] 0.0004104601 +1 cbx_1__2_:chanx_right_in[5] 0.0004104601 +2 sb_1__2_:chanx_left_out[5] sb_1__2_:chanx_left_in[7] 0.0001418392 +3 cbx_1__2_:chanx_right_in[5] cbx_1__2_:chanx_right_out[7] 0.0001418392 +4 sb_1__2_:chanx_left_out[5] sb_1__2_:chanx_left_out[14] 0.0001421791 +5 cbx_1__2_:chanx_right_in[5] cbx_1__2_:chanx_right_in[14] 0.0001421791 + +*RES +0 sb_1__2_:chanx_left_out[5] cbx_1__2_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[14] 0.001378085 //LENGTH 7.660 LUMPCC 0.0004915755 DR + +*CONN +*I sb_1__2_:chanx_left_out[14] O *L 0 *C 519.950 858.160 +*I cbx_1__2_:chanx_right_in[14] I *L 0 *C 512.290 858.160 + +*CAP +0 sb_1__2_:chanx_left_out[14] 0.0004432547 +1 cbx_1__2_:chanx_right_in[14] 0.0004432547 +2 sb_1__2_:chanx_left_out[14] sb_1__2_:chanx_left_in[2] 0.0001036087 +3 cbx_1__2_:chanx_right_in[14] cbx_1__2__0_chanx_right_out[2]:2 0.0001036087 +4 sb_1__2_:chanx_left_out[14] sb_1__2_:chanx_left_out[5] 0.0001421791 +5 cbx_1__2_:chanx_right_in[14] cbx_1__2_:chanx_right_in[5] 0.0001421791 + +*RES +0 sb_1__2_:chanx_left_out[14] cbx_1__2_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[3] 0.001435511 //LENGTH 7.660 LUMPCC 0.0003644539 DR + +*CONN +*I sb_1__2_:chanx_right_out[3] O *L 0 *C 661.330 871.760 +*I cbx_2__2_:chanx_left_in[3] I *L 0 *C 668.990 871.760 +*N sb_1__2__0_chanx_right_out[3]:2 *C 667.520 871.760 +*N sb_1__2__0_chanx_right_out[3]:3 *C 667.519 871.760 + +*CAP +0 sb_1__2_:chanx_right_out[3] 0.0003155154 +1 cbx_2__2_:chanx_left_in[3] 0.0002200131 +2 sb_1__2__0_chanx_right_out[3]:2 0.0002200131 +3 sb_1__2__0_chanx_right_out[3]:3 0.0003155154 +4 sb_1__2_:chanx_right_out[3] sb_1__2_:chanx_right_in[10] 6.249905e-05 +5 sb_1__2__0_chanx_right_out[3]:3 cbx_1__2__1_chanx_left_out[10]:2 6.249905e-05 +6 sb_1__2_:chanx_right_out[3] sb_1__2_:chanx_right_out[6] 0.0001197279 +7 sb_1__2__0_chanx_right_out[3]:3 sb_1__2__0_chanx_right_out[6]:3 0.0001197279 + +*RES +0 sb_1__2_:chanx_right_out[3] sb_1__2__0_chanx_right_out[3]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[3]:2 cbx_2__2_:chanx_left_in[3] 0.0002303 +2 sb_1__2__0_chanx_right_out[3]:3 sb_1__2__0_chanx_right_out[3]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[10] 0.00145588 //LENGTH 7.660 LUMPCC 0.0005141621 DR + +*CONN +*I sb_1__2_:chanx_right_out[10] O *L 0 *C 661.330 840.480 +*I cbx_2__2_:chanx_left_in[10] I *L 0 *C 668.990 840.480 +*N sb_1__2__0_chanx_right_out[10]:2 *C 667.520 840.480 +*N sb_1__2__0_chanx_right_out[10]:3 *C 667.519 840.480 + +*CAP +0 sb_1__2_:chanx_right_out[10] 0.000270188 +1 cbx_2__2_:chanx_left_in[10] 0.0002006711 +2 sb_1__2__0_chanx_right_out[10]:2 0.0002006711 +3 sb_1__2__0_chanx_right_out[10]:3 0.000270188 +4 sb_1__2_:chanx_right_out[10] sb_1__2_:chanx_right_in[7] 0.0001303597 +5 cbx_2__2_:chanx_left_in[10] cbx_2__2_:chanx_left_out[7] 6.576453e-06 +6 sb_1__2__0_chanx_right_out[10]:2 cbx_1__2__1_chanx_left_out[7]:3 6.576453e-06 +7 sb_1__2__0_chanx_right_out[10]:3 cbx_1__2__1_chanx_left_out[7]:2 0.0001303597 +8 sb_1__2_:chanx_right_out[10] sb_1__2_:chanx_right_out[2] 0.0001201449 +9 sb_1__2__0_chanx_right_out[10]:3 sb_1__2__0_chanx_right_out[2]:3 0.0001201449 + +*RES +0 sb_1__2_:chanx_right_out[10] sb_1__2__0_chanx_right_out[10]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[10]:2 cbx_2__2_:chanx_left_in[10] 0.0002303 +2 sb_1__2__0_chanx_right_out[10]:3 sb_1__2__0_chanx_right_out[10]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[1] 0.00127959 //LENGTH 11.020 LUMPCC 0.0005195668 DR + +*CONN +*I sb_1__2_:chany_bottom_out[1] O *L 0 *C 579.600 788.870 +*I cby_1__2_:chany_top_in[1] I *L 0 *C 579.600 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[1] 0.0003800118 +1 cby_1__2_:chany_top_in[1] 0.0003800118 +2 sb_1__2_:chany_bottom_out[1] sb_1__2_:chany_bottom_out[7] 0.0001298917 +3 cby_1__2_:chany_top_in[1] cby_1__2_:chany_top_in[7] 0.0001298917 +4 sb_1__2_:chany_bottom_out[1] sb_1__2_:chany_bottom_out[17] 0.0001298917 +5 cby_1__2_:chany_top_in[1] cby_1__2_:chany_top_in[17] 0.0001298917 + +*RES +0 sb_1__2_:chany_bottom_out[1] cby_1__2_:chany_top_in[1] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[11] 0.001280241 //LENGTH 11.020 LUMPCC 0.0005183863 DR + +*CONN +*I sb_1__2_:chany_bottom_out[11] O *L 0 *C 593.860 788.870 +*I cby_1__2_:chany_top_in[11] I *L 0 *C 593.860 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[11] 0.0003809272 +1 cby_1__2_:chany_top_in[11] 0.0003809272 +2 sb_1__2_:chany_bottom_out[11] sb_1__2_:chany_bottom_out[6] 0.0001295966 +3 cby_1__2_:chany_top_in[11] cby_1__2_:chany_top_in[6] 0.0001295966 +4 sb_1__2_:chany_bottom_out[11] sb_1__2_:chany_bottom_out[18] 0.0001295966 +5 cby_1__2_:chany_top_in[11] cby_1__2_:chany_top_in[18] 0.0001295966 + +*RES +0 sb_1__2_:chany_bottom_out[11] cby_1__2_:chany_top_in[11] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[0] 0.001507768 //LENGTH 7.660 LUMPCC 0.0004916394 DR + +*CONN +*I sb_2__0_:chanx_left_out[0] O *L 0 *C 781.230 320.960 +*I cbx_2__0_:chanx_right_in[0] I *L 0 *C 773.570 320.960 + +*CAP +0 sb_2__0_:chanx_left_out[0] 0.0005080642 +1 cbx_2__0_:chanx_right_in[0] 0.0005080642 +2 sb_2__0_:chanx_left_out[0] sb_2__0_:chanx_left_in[16] 0.0001264714 +3 cbx_2__0_:chanx_right_in[0] cbx_2__0_:chanx_right_out[16] 0.0001264714 +4 sb_2__0_:chanx_left_out[0] sb_2__0_:chanx_left_out[6] 0.0001193483 +5 cbx_2__0_:chanx_right_in[0] cbx_2__0_:chanx_right_in[6] 0.0001193483 + +*RES +0 sb_2__0_:chanx_left_out[0] cbx_2__0_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[10] 0.001348677 //LENGTH 7.660 LUMPCC 0.0004760859 DR + +*CONN +*I sb_2__0_:chanx_left_out[10] O *L 0 *C 781.230 314.160 +*I cbx_2__0_:chanx_right_in[10] I *L 0 *C 773.570 314.160 + +*CAP +0 sb_2__0_:chanx_left_out[10] 0.0004362955 +1 cbx_2__0_:chanx_right_in[10] 0.0004362955 +2 sb_2__0_:chanx_left_out[10] sb_2__0_:chanx_left_in[17] 5.207383e-05 +3 cbx_2__0_:chanx_right_in[10] cbx_1__0__1_chanx_right_out[17]:2 5.207383e-05 +4 sb_2__0_:chanx_left_out[10] sb_2__0_:chanx_left_out[8] 0.000145226 +5 cbx_2__0_:chanx_right_in[10] cbx_2__0_:chanx_right_in[8] 0.000145226 +6 sb_2__0_:chanx_left_out[10] sb_2__0_:chanx_left_out[14] 4.074317e-05 +7 cbx_2__0_:chanx_right_in[10] cbx_2__0_:chanx_right_in[14] 4.074317e-05 + +*RES +0 sb_2__0_:chanx_left_out[10] cbx_2__0_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[1] 0.001213554 //LENGTH 11.020 LUMPCC 0.0005995213 DR + +*CONN +*I sb_2__0_:chany_top_out[1] O *L 0 *C 842.260 397.050 +*I cby_2__1_:chany_bottom_in[1] I *L 0 *C 842.260 408.070 + +*CAP +0 sb_2__0_:chany_top_out[1] 0.0003070164 +1 cby_2__1_:chany_bottom_in[1] 0.0003070164 +2 sb_2__0_:chany_top_out[1] sb_2__0_:chany_top_in[5] 0.0001471034 +3 cby_2__1_:chany_bottom_in[1] cby_2__1_:chany_bottom_out[5] 0.0001471034 +4 sb_2__0_:chany_top_out[1] sb_2__0_:chany_top_out[17] 0.0001526573 +5 cby_2__1_:chany_bottom_in[1] cby_2__1_:chany_bottom_in[17] 0.0001526573 + +*RES +0 sb_2__0_:chany_top_out[1] cby_2__1_:chany_bottom_in[1] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[8] 0.001237502 //LENGTH 11.020 LUMPCC 0.0005795517 DR + +*CONN +*I sb_2__0_:chany_top_out[8] O *L 0 *C 849.620 397.050 +*I cby_2__1_:chany_bottom_in[8] I *L 0 *C 849.620 408.070 + +*CAP +0 sb_2__0_:chany_top_out[8] 0.0003289752 +1 cby_2__1_:chany_bottom_in[8] 0.0003289752 +2 sb_2__0_:chany_top_out[8] sb_2__0_:chany_top_in[9] 0.0001448879 +3 cby_2__1_:chany_bottom_in[8] cby_2__1_:chany_bottom_out[9] 0.0001448879 +4 sb_2__0_:chany_top_out[8] sb_2__0_:chany_top_in[16] 0.0001448879 +5 cby_2__1_:chany_bottom_in[8] cby_2__1_:chany_bottom_out[16] 0.0001448879 + +*RES +0 sb_2__0_:chany_top_out[8] cby_2__1_:chany_bottom_in[8] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[19] 0.00123291 //LENGTH 11.020 LUMPCC 0.0005893015 DR + +*CONN +*I sb_2__0_:chany_top_out[19] O *L 0 *C 859.740 397.050 +*I cby_2__1_:chany_bottom_in[19] I *L 0 *C 859.740 408.070 + +*CAP +0 sb_2__0_:chany_top_out[19] 0.0003218044 +1 cby_2__1_:chany_bottom_in[19] 0.0003218044 +2 sb_2__0_:chany_top_out[19] sb_2__0_:chany_top_out[2] 0.0001467206 +3 cby_2__1_:chany_bottom_in[19] cby_2__1_:chany_bottom_in[2] 0.0001467206 +4 sb_2__0_:chany_top_out[19] sb_2__0_:chany_top_out[12] 0.0001479301 +5 cby_2__1_:chany_bottom_in[19] cby_2__1_:chany_bottom_in[12] 0.0001479301 + +*RES +0 sb_2__0_:chany_top_out[19] cby_2__1_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET sb_2__1__0_chanx_left_out[5] 0.001565988 //LENGTH 7.660 LUMPCC 0.0002903068 DR + +*CONN +*I sb_2__1_:chanx_left_out[5] O *L 0 *C 781.230 575.280 +*I cbx_2__1_:chanx_right_in[5] I *L 0 *C 773.570 575.280 + +*CAP +0 sb_2__1_:chanx_left_out[5] 0.0006378406 +1 cbx_2__1_:chanx_right_in[5] 0.0006378406 +2 sb_2__1_:chanx_left_out[5] sb_2__1_:chanx_left_in[2] 4.94577e-05 +3 cbx_2__1_:chanx_right_in[5] cbx_1__1__1_chanx_right_out[2]:2 4.94577e-05 +4 sb_2__1_:chanx_left_out[5] sb_2__1_:chanx_left_out[8] 9.569569e-05 +5 cbx_2__1_:chanx_right_in[5] cbx_2__1_:chanx_right_in[8] 9.569569e-05 + +*RES +0 sb_2__1_:chanx_left_out[5] cbx_2__1_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[15] 0.003726294 //LENGTH 27.190 LUMPCC 0.0008001468 DR + +*CONN +*I sb_2__1_:chanx_left_out[15] O *L 0 *C 781.230 568.480 +*I cbx_2__1_:chanx_right_in[15] I *L 0 *C 771.420 554.950 +*N sb_2__1__0_chanx_left_out[15]:2 *C 771.420 553.565 +*N sb_2__1__0_chanx_left_out[15]:3 *C 771.465 553.520 +*N sb_2__1__0_chanx_left_out[15]:4 *C 774.135 553.520 +*N sb_2__1__0_chanx_left_out[15]:5 *C 774.180 553.565 +*N sb_2__1__0_chanx_left_out[15]:6 *C 774.180 568.423 +*N sb_2__1__0_chanx_left_out[15]:7 *C 774.188 568.480 + +*CAP +0 sb_2__1_:chanx_left_out[15] 0.0005219217 +1 cbx_2__1_:chanx_right_in[15] 9.739709e-05 +2 sb_2__1__0_chanx_left_out[15]:2 9.739709e-05 +3 sb_2__1__0_chanx_left_out[15]:3 0.0001118248 +4 sb_2__1__0_chanx_left_out[15]:4 0.0001118248 +5 sb_2__1__0_chanx_left_out[15]:5 0.0007319301 +6 sb_2__1__0_chanx_left_out[15]:6 0.0007319301 +7 sb_2__1__0_chanx_left_out[15]:7 0.0005219217 +8 sb_2__1__0_chanx_left_out[15]:4 cbx_1__1__1_chanx_right_out[2]:5 5.685991e-05 +9 sb_2__1__0_chanx_left_out[15]:3 cbx_1__1__1_chanx_right_out[2]:6 5.685991e-05 +10 sb_2__1_:chanx_left_out[15] sb_2__1_:chanx_left_in[3] 9.299627e-05 +11 sb_2__1__0_chanx_left_out[15]:7 cbx_2__1_:chanx_right_out[3] 9.299627e-05 +12 sb_2__1_:chanx_left_out[15] sb_2__1_:chanx_left_in[7] 9.825232e-05 +13 sb_2__1__0_chanx_left_out[15]:7 cbx_2__1_:chanx_right_out[7] 9.825232e-05 +14 sb_2__1__0_chanx_left_out[15]:6 cbx_1__1__1_chanx_right_out[11]:5 4.792587e-05 +15 sb_2__1__0_chanx_left_out[15]:5 cbx_1__1__1_chanx_right_out[11]:4 4.792587e-05 +16 cbx_2__1_:chanx_right_in[15] cbx_1__1__1_chanx_right_out[19]:3 4.797034e-07 +17 sb_2__1__0_chanx_left_out[15]:6 cbx_1__1__1_chanx_right_out[19]:3 9.7926e-05 +18 sb_2__1__0_chanx_left_out[15]:4 cbx_1__1__1_chanx_right_out[19]:5 5.633308e-06 +19 sb_2__1__0_chanx_left_out[15]:5 cbx_1__1__1_chanx_right_out[19]:4 9.7926e-05 +20 sb_2__1__0_chanx_left_out[15]:3 cbx_1__1__1_chanx_right_out[19]:6 5.633308e-06 +21 sb_2__1__0_chanx_left_out[15]:2 cbx_1__1__1_chanx_right_out[19]:4 4.797034e-07 + +*RES +0 sb_2__1_:chanx_left_out[15] sb_2__1__0_chanx_left_out[15]:7 0.001103325 +1 sb_2__1__0_chanx_left_out[15]:6 sb_2__1__0_chanx_left_out[15]:5 0.01326563 +2 sb_2__1__0_chanx_left_out[15]:7 sb_2__1__0_chanx_left_out[15]:6 0.00341 +3 sb_2__1__0_chanx_left_out[15]:4 sb_2__1__0_chanx_left_out[15]:3 0.002383929 +4 sb_2__1__0_chanx_left_out[15]:5 sb_2__1__0_chanx_left_out[15]:4 0.0045 +5 sb_2__1__0_chanx_left_out[15]:3 sb_2__1__0_chanx_left_out[15]:2 0.0045 +6 sb_2__1__0_chanx_left_out[15]:2 cbx_2__1_:chanx_right_in[15] 0.001236607 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[8] 0.001261363 //LENGTH 11.020 LUMPCC 0.0005510945 DR + +*CONN +*I sb_2__1_:chany_bottom_out[8] O *L 0 *C 844.560 527.750 +*I cby_2__1_:chany_top_in[8] I *L 0 *C 844.560 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[8] 0.0003551343 +1 cby_2__1_:chany_top_in[8] 0.0003551343 +2 sb_2__1_:chany_bottom_out[8] sb_2__1_:chany_bottom_in[10] 0.0001377736 +3 cby_2__1_:chany_top_in[8] cby_2__1_:chany_top_out[10] 0.0001377736 +4 sb_2__1_:chany_bottom_out[8] sb_2__1_:chany_bottom_out[16] 0.0001377736 +5 cby_2__1_:chany_top_in[8] cby_2__1_:chany_top_in[16] 0.0001377736 + +*RES +0 sb_2__1_:chany_bottom_out[8] cby_2__1_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[19] 0.001278076 //LENGTH 11.020 LUMPCC 0.0005309782 DR + +*CONN +*I sb_2__1_:chany_bottom_out[19] O *L 0 *C 851.920 527.750 +*I cby_2__1_:chany_top_in[19] I *L 0 *C 851.920 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[19] 0.0003735489 +1 cby_2__1_:chany_top_in[19] 0.0003735489 +2 sb_2__1_:chany_bottom_out[19] sb_2__1_:chany_bottom_in[17] 0.0001316349 +3 cby_2__1_:chany_top_in[19] cby_2__1_:chany_top_out[17] 0.0001316349 +4 sb_2__1_:chany_bottom_out[19] sb_2__1_:chany_bottom_out[5] 0.0001338541 +5 cby_2__1_:chany_top_in[19] cby_2__1_:chany_top_in[5] 0.0001338541 + +*RES +0 sb_2__1_:chany_bottom_out[19] cby_2__1_:chany_top_in[19] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[9] 0.001258027 //LENGTH 11.020 LUMPCC 0.0005502676 DR + +*CONN +*I sb_2__1_:chany_top_out[9] O *L 0 *C 839.500 658.170 +*I cby_2__2_:chany_bottom_in[9] I *L 0 *C 839.500 669.190 +*N sb_2__1__0_chany_top_out[9]:2 *C 839.500 667.520 +*N sb_2__1__0_chany_top_out[9]:3 *C 839.500 667.519 + +*CAP +0 sb_2__1_:chany_top_out[9] 0.000242942 +1 cby_2__2_:chany_bottom_in[9] 0.0001109378 +2 sb_2__1__0_chany_top_out[9]:2 0.0001109378 +3 sb_2__1__0_chany_top_out[9]:3 0.000242942 +4 sb_2__1_:chany_top_out[9] sb_2__1_:chany_top_in[1] 0.0001302265 +5 cby_2__2_:chany_bottom_in[9] cby_2__2_:chany_bottom_out[1] 7.340369e-06 +6 sb_2__1__0_chany_top_out[9]:2 cby_1__1__3_chany_bottom_out[1]:3 7.340369e-06 +7 sb_2__1__0_chany_top_out[9]:3 cby_1__1__3_chany_bottom_out[1]:2 0.0001302265 +8 sb_2__1_:chany_top_out[9] sb_2__1_:chany_top_in[19] 0.0001302265 +9 cby_2__2_:chany_bottom_in[9] cby_2__2_:chany_bottom_out[19] 7.340369e-06 +10 sb_2__1__0_chany_top_out[9]:2 cby_1__1__3_chany_bottom_out[19]:3 7.340369e-06 +11 sb_2__1__0_chany_top_out[9]:3 cby_1__1__3_chany_bottom_out[19]:2 0.0001302265 + +*RES +0 sb_2__1_:chany_top_out[9] sb_2__1__0_chany_top_out[9]:3 0.008347321 +1 sb_2__1__0_chany_top_out[9]:2 cby_2__2_:chany_bottom_in[9] 0.001491072 +2 sb_2__1__0_chany_top_out[9]:3 sb_2__1__0_chany_top_out[9]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[18] 0.001188179 //LENGTH 11.020 LUMPCC 0.0004027769 DR + +*CONN +*I sb_2__1_:chany_top_out[18] O *L 0 *C 876.760 658.170 +*I cby_2__2_:chany_bottom_in[18] I *L 0 *C 876.760 669.190 +*N sb_2__1__0_chany_top_out[18]:2 *C 876.760 667.520 +*N sb_2__1__0_chany_top_out[18]:3 *C 876.760 667.519 + +*CAP +0 sb_2__1_:chany_top_out[18] 0.0002738898 +1 cby_2__2_:chany_bottom_in[18] 0.0001188112 +2 sb_2__1__0_chany_top_out[18]:2 0.0001188112 +3 sb_2__1__0_chany_top_out[18]:3 0.0002738898 +4 sb_2__1_:chany_top_out[18] sb_2__1_:chany_top_out[10] 0.0001328241 +5 cby_2__2_:chany_bottom_in[18] cby_2__2_:chany_bottom_in[10] 7.354774e-06 +6 sb_2__1__0_chany_top_out[18]:2 sb_2__1__0_chany_top_out[10]:2 7.354774e-06 +7 sb_2__1__0_chany_top_out[18]:3 sb_2__1__0_chany_top_out[10]:3 0.0001328241 +8 sb_2__1_:chany_top_out[18] sb_2__1_:chany_top_out[11] 6.120958e-05 +9 sb_2__1__0_chany_top_out[18]:3 sb_2__1__0_chany_top_out[11]:3 6.120958e-05 + +*RES +0 sb_2__1_:chany_top_out[18] sb_2__1__0_chany_top_out[18]:3 0.008347322 +1 sb_2__1__0_chany_top_out[18]:2 cby_2__2_:chany_bottom_in[18] 0.001491072 +2 sb_2__1__0_chany_top_out[18]:3 sb_2__1__0_chany_top_out[18]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[7] 0.001406451 //LENGTH 7.660 LUMPCC 0.0004580714 DR + +*CONN +*I sb_2__2_:chanx_left_out[7] O *L 0 *C 781.230 836.400 +*I cbx_2__2_:chanx_right_in[7] I *L 0 *C 773.570 836.400 + +*CAP +0 sb_2__2_:chanx_left_out[7] 0.0004741897 +1 cbx_2__2_:chanx_right_in[7] 0.0004741897 +2 sb_2__2_:chanx_left_out[7] sb_2__2_:chanx_left_in[5] 4.298147e-05 +3 cbx_2__2_:chanx_right_in[7] cbx_1__2__1_chanx_right_out[5]:2 4.298147e-05 +4 sb_2__2_:chanx_left_out[7] sb_2__2_:chanx_left_out[3] 0.0001442828 +5 cbx_2__2_:chanx_right_in[7] cbx_2__2_:chanx_right_in[3] 0.0001442828 +6 sb_2__2_:chanx_left_out[7] sb_2__2_:chanx_left_out[15] 4.17714e-05 +7 cbx_2__2_:chanx_right_in[7] cbx_2__2_:chanx_right_in[15] 4.17714e-05 + +*RES +0 sb_2__2_:chanx_left_out[7] cbx_2__2_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[19] 0.001337163 //LENGTH 7.660 LUMPCC 0.0004156359 DR + +*CONN +*I sb_2__2_:chanx_left_out[19] O *L 0 *C 781.230 877.200 +*I cbx_2__2_:chanx_right_in[19] I *L 0 *C 773.570 877.200 + +*CAP +0 sb_2__2_:chanx_left_out[19] 0.0004607634 +1 cbx_2__2_:chanx_right_in[19] 0.0004607634 +2 sb_2__2_:chanx_left_out[19] sb_2__2_:chanx_left_out[13] 0.0001445335 +3 cbx_2__2_:chanx_right_in[19] cbx_2__2_:chanx_right_in[13] 0.0001445335 +4 sb_2__2_:chanx_left_out[19] sb_2__2_:chanx_left_out[17] 6.32845e-05 +5 cbx_2__2_:chanx_right_in[19] cbx_2__2_:chanx_right_in[17] 6.32845e-05 + +*RES +0 sb_2__2_:chanx_left_out[19] cbx_2__2_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[8] 0.001236644 //LENGTH 11.020 LUMPCC 0.000587663 DR + +*CONN +*I sb_2__2_:chany_bottom_out[8] O *L 0 *C 844.560 788.870 +*I cby_2__2_:chany_top_in[8] I *L 0 *C 844.560 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[8] 0.0003244906 +1 cby_2__2_:chany_top_in[8] 0.0003244906 +2 sb_2__2_:chany_bottom_out[8] sb_2__2_:chany_bottom_in[10] 0.0001469158 +3 cby_2__2_:chany_top_in[8] cby_2__2_:chany_top_out[10] 0.0001469158 +4 sb_2__2_:chany_bottom_out[8] sb_2__2_:chany_bottom_out[16] 0.0001469158 +5 cby_2__2_:chany_top_in[8] cby_2__2_:chany_top_in[16] 0.0001469158 + +*RES +0 sb_2__2_:chany_bottom_out[8] cby_2__2_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[18] 0.001215029 //LENGTH 11.020 LUMPCC 0.0004637854 DR + +*CONN +*I sb_2__2_:chany_bottom_out[18] O *L 0 *C 854.220 788.870 +*I cby_2__2_:chany_top_in[18] I *L 0 *C 854.220 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[18] 0.0003756216 +1 cby_2__2_:chany_top_in[18] 0.0003756216 +2 sb_2__2_:chany_bottom_out[18] sb_2__2_:chany_bottom_out[5] 8.91458e-05 +3 cby_2__2_:chany_top_in[18] cby_2__2_:chany_top_in[5] 8.91458e-05 +4 sb_2__2_:chany_bottom_out[18] sb_2__2_:chany_bottom_out[11] 0.0001427469 +5 cby_2__2_:chany_top_in[18] cby_2__2_:chany_top_in[11] 0.0001427469 + +*RES +0 sb_2__2_:chany_bottom_out[18] cby_2__2_:chany_top_in[18] 0.009839286 + +*END + +*D_NET ctsbuf_net_413 0.001765939 //LENGTH 14.840 LUMPCC 0.0003482471 DR + +*CONN +*I cts_inv_73537628:Y O *L 0 *C 630.200 524.280 +*I grid_clb_2__1_:prog_clk[0] I *L 0 *C 640.470 527.680 +*N ctsbuf_net_413:2 *C 639.408 527.680 +*N ctsbuf_net_413:3 *C 639.400 527.623 +*N ctsbuf_net_413:4 *C 639.400 524.337 +*N ctsbuf_net_413:5 *C 639.393 524.280 +*N ctsbuf_net_413:6 *C 632.048 524.280 +*N ctsbuf_net_413:7 *C 632.040 524.280 +*N ctsbuf_net_413:8 *C 631.995 524.280 +*N ctsbuf_net_413:9 *C 630.238 524.280 + +*CAP +0 cts_inv_73537628:Y 1e-06 +1 grid_clb_2__1_:prog_clk[0] 8.13674e-05 +2 ctsbuf_net_413:2 8.13674e-05 +3 ctsbuf_net_413:3 0.0001498014 +4 ctsbuf_net_413:4 0.0001498014 +5 ctsbuf_net_413:5 0.0003310943 +6 ctsbuf_net_413:6 0.0003310943 +7 ctsbuf_net_413:7 3.685795e-05 +8 ctsbuf_net_413:8 0.0001276542 +9 ctsbuf_net_413:9 0.0001276542 +10 ctsbuf_net_413:6 clk[0]:37 3.293142e-05 +11 ctsbuf_net_413:4 clk[0]:39 5.218217e-05 +12 ctsbuf_net_413:5 clk[0]:38 3.293142e-05 +13 ctsbuf_net_413:3 clk[0]:40 5.218217e-05 +14 ctsbuf_net_413:6 ctsbuf_net_1928:24 8.900995e-05 +15 ctsbuf_net_413:5 ctsbuf_net_1928:23 8.900995e-05 + +*RES +0 cts_inv_73537628:Y ctsbuf_net_413:9 0.152 +1 ctsbuf_net_413:9 ctsbuf_net_413:8 0.001569196 +2 ctsbuf_net_413:8 ctsbuf_net_413:7 0.0045 +3 ctsbuf_net_413:7 ctsbuf_net_413:6 0.00341 +4 ctsbuf_net_413:6 ctsbuf_net_413:5 0.001150717 +5 ctsbuf_net_413:4 ctsbuf_net_413:3 0.002933036 +6 ctsbuf_net_413:5 ctsbuf_net_413:4 0.00341 +7 ctsbuf_net_413:3 ctsbuf_net_413:2 0.00341 +8 ctsbuf_net_413:2 grid_clb_2__1_:prog_clk[0] 0.0001664583 + +*END + +*D_NET ctsbuf_net_1322 0.009364948 //LENGTH 81.295 LUMPCC 0.001597657 DR + +*CONN +*I cts_inv_73627637:Y O *L 0 *C 368.920 779.960 +*I grid_clb_1__2_:prog_clk[0] I *L 0 *C 379.190 788.800 +*I cbx_1__2_:prog_clk[0] I *L 0 *C 410.780 816.070 +*N ctsbuf_net_1322:3 *C 410.780 807.218 +*N ctsbuf_net_1322:4 *C 410.773 807.160 +*N ctsbuf_net_1322:5 *C 378.127 807.160 +*N ctsbuf_net_1322:6 *C 378.120 807.103 +*N ctsbuf_net_1322:7 *C 378.120 788.800 +*N ctsbuf_net_1322:8 *C 378.588 788.800 +*N ctsbuf_net_1322:9 *C 378.580 788.743 +*N ctsbuf_net_1322:10 *C 378.580 780.005 +*N ctsbuf_net_1322:11 *C 378.535 779.960 +*N ctsbuf_net_1322:12 *C 368.958 779.960 + +*CAP +0 cts_inv_73627637:Y 1e-06 +1 grid_clb_1__2_:prog_clk[0] 9.464878e-05 +2 cbx_1__2_:prog_clk[0] 0.0004398254 +3 ctsbuf_net_1322:3 0.0004398254 +4 ctsbuf_net_1322:4 0.00127954 +5 ctsbuf_net_1322:5 0.00127954 +6 ctsbuf_net_1322:6 0.0009467087 +7 ctsbuf_net_1322:7 0.0009826672 +8 ctsbuf_net_1322:8 9.464878e-05 +9 ctsbuf_net_1322:9 0.0005148705 +10 ctsbuf_net_1322:10 0.0004789119 +11 ctsbuf_net_1322:11 0.000607552 +12 ctsbuf_net_1322:12 0.000607552 +13 ctsbuf_net_1322:6 ctsbuf_net_2130:66 3.047685e-05 +14 ctsbuf_net_1322:5 ctsbuf_net_2130:65 0.0007356532 +15 ctsbuf_net_1322:4 ctsbuf_net_2130:64 0.0007356532 +16 ctsbuf_net_1322:11 ctsbuf_net_2130:70 1.922761e-05 +17 ctsbuf_net_1322:10 ctsbuf_net_2130:67 1.347071e-05 +18 ctsbuf_net_1322:12 ctsbuf_net_2130:69 1.922761e-05 +19 ctsbuf_net_1322:9 ctsbuf_net_2130:66 1.347071e-05 +20 ctsbuf_net_1322:7 ctsbuf_net_2130:67 3.047685e-05 + +*RES +0 cts_inv_73627637:Y ctsbuf_net_1322:12 0.152 +1 ctsbuf_net_1322:6 ctsbuf_net_1322:5 0.00341 +2 ctsbuf_net_1322:5 ctsbuf_net_1322:4 0.005114383 +3 ctsbuf_net_1322:3 cbx_1__2_:prog_clk[0] 0.007904018 +4 ctsbuf_net_1322:4 ctsbuf_net_1322:3 0.00341 +5 ctsbuf_net_1322:11 ctsbuf_net_1322:10 0.0045 +6 ctsbuf_net_1322:10 ctsbuf_net_1322:9 0.007801339 +7 ctsbuf_net_1322:12 ctsbuf_net_1322:11 0.00855134 +8 ctsbuf_net_1322:9 ctsbuf_net_1322:8 0.00341 +9 ctsbuf_net_1322:9 ctsbuf_net_1322:7 0.0004107143 +10 ctsbuf_net_1322:8 grid_clb_1__2_:prog_clk[0] 9.439164e-05 +11 ctsbuf_net_1322:7 ctsbuf_net_1322:6 0.01634152 + +*END + +*D_NET ctsbuf_net_1928 0.0897424 //LENGTH 700.825 LUMPCC 0.01560054 DR + +*CONN +*I cts_inv_73827657:Y O *L 0 *C 276.920 610.715 +*I cts_inv_73677642:A I *L 0.005046 *C 372.140 545.435 +*I cts_inv_73617636:A I *L 0.005046 *C 636.180 545.095 +*I cts_inv_73507625:A I *L 0.005046 *C 799.020 553.595 +*N ctsbuf_net_1928:4 *C 799.020 553.595 +*N ctsbuf_net_1928:5 *C 799.940 553.580 +*N ctsbuf_net_1928:6 *C 799.940 553.580 +*N ctsbuf_net_1928:7 *C 799.933 553.520 +*N ctsbuf_net_1928:8 *C 795.348 553.520 +*N ctsbuf_net_1928:9 *C 795.340 553.498 +*N ctsbuf_net_1928:10 *C 795.340 547.423 +*N ctsbuf_net_1928:11 *C 795.340 547.400 +*N ctsbuf_net_1928:12 *C 786.800 547.400 +*N ctsbuf_net_1928:13 *C 736.800 547.400 +*N ctsbuf_net_1928:14 *C 686.800 547.400 +*N ctsbuf_net_1928:15 *C 667.520 547.400 +*N ctsbuf_net_1928:16 *C 667.519 547.400 +*N ctsbuf_net_1928:17 *C 637.100 547.400 +*N ctsbuf_net_1928:18 *C 637.100 547.378 +*N ctsbuf_net_1928:19 *C 636.180 545.095 +*N ctsbuf_net_1928:20 *C 637.100 545.090 +*N ctsbuf_net_1928:21 *C 637.100 545.090 +*N ctsbuf_net_1928:22 *C 637.100 526.342 +*N ctsbuf_net_1928:23 *C 637.100 526.320 +*N ctsbuf_net_1928:24 *C 594.800 526.320 +*N ctsbuf_net_1928:25 *C 545.100 526.320 +*N ctsbuf_net_1928:26 *C 545.100 526.342 +*N ctsbuf_net_1928:27 *C 545.100 552.138 +*N ctsbuf_net_1928:28 *C 545.100 552.160 +*N ctsbuf_net_1928:29 *C 535.780 552.160 +*N ctsbuf_net_1928:30 *C 485.780 552.160 +*N ctsbuf_net_1928:31 *C 443.520 552.160 +*N ctsbuf_net_1928:32 *C 443.519 552.160 +*N ctsbuf_net_1928:33 *C 436.080 552.160 +*N ctsbuf_net_1928:34 *C 436.080 552.138 +*N ctsbuf_net_1928:35 *C 436.080 550.143 +*N ctsbuf_net_1928:36 *C 436.080 550.120 +*N ctsbuf_net_1928:37 *C 423.220 550.120 +*N ctsbuf_net_1928:38 *C 373.520 550.120 +*N ctsbuf_net_1928:39 *C 373.520 550.098 +*N ctsbuf_net_1928:40 *C 372.140 545.435 +*N ctsbuf_net_1928:41 *C 372.600 545.360 +*N ctsbuf_net_1928:42 *C 372.600 545.020 +*N ctsbuf_net_1928:43 *C 373.520 545.070 +*N ctsbuf_net_1928:44 *C 373.520 545.070 +*N ctsbuf_net_1928:45 *C 373.520 524.303 +*N ctsbuf_net_1928:46 *C 373.520 524.280 +*N ctsbuf_net_1928:47 *C 327.540 524.280 +*N ctsbuf_net_1928:48 *C 277.840 524.280 +*N ctsbuf_net_1928:49 *C 277.840 524.303 +*N ctsbuf_net_1928:50 *C 277.840 574.095 +*N ctsbuf_net_1928:51 *C 277.840 605.215 +*N ctsbuf_net_1928:52 *C 277.840 610.460 +*N ctsbuf_net_1928:53 *C 277.840 610.460 +*N ctsbuf_net_1928:54 *C 276.958 610.655 + +*CAP +0 cts_inv_73827657:Y 1e-06 +1 cts_inv_73677642:A 1e-06 +2 cts_inv_73617636:A 1e-06 +3 cts_inv_73507625:A 1e-06 +4 ctsbuf_net_1928:4 0.0001030432 +5 ctsbuf_net_1928:5 0.000108094 +6 ctsbuf_net_1928:6 3.971639e-05 +7 ctsbuf_net_1928:7 0.0002808362 +8 ctsbuf_net_1928:8 0.0002808362 +9 ctsbuf_net_1928:9 0.0003631893 +10 ctsbuf_net_1928:10 0.0003631893 +11 ctsbuf_net_1928:11 0.0004768343 +12 ctsbuf_net_1928:12 0.003112406 +13 ctsbuf_net_1928:13 0.005055901 +14 ctsbuf_net_1928:14 0.003395826 +15 ctsbuf_net_1928:15 0.0009754972 +16 ctsbuf_net_1928:16 0.001313397 +17 ctsbuf_net_1928:17 0.001313397 +18 ctsbuf_net_1928:18 0.0001162249 +19 ctsbuf_net_1928:19 0.0001152018 +20 ctsbuf_net_1928:20 0.0001215487 +21 ctsbuf_net_1928:21 0.0009654664 +22 ctsbuf_net_1928:22 0.0008139032 +23 ctsbuf_net_1928:23 0.002869394 +24 ctsbuf_net_1928:24 0.006261525 +25 ctsbuf_net_1928:25 0.003392129 +26 ctsbuf_net_1928:26 0.001171349 +27 ctsbuf_net_1928:27 0.001171349 +28 ctsbuf_net_1928:28 0.0004518265 +29 ctsbuf_net_1928:29 0.003131836 +30 ctsbuf_net_1928:30 0.005109138 +31 ctsbuf_net_1928:31 0.002429128 +32 ctsbuf_net_1928:32 0.0004794247 +33 ctsbuf_net_1928:33 0.0004794247 +34 ctsbuf_net_1928:34 0.0001415675 +35 ctsbuf_net_1928:35 0.0001415675 +36 ctsbuf_net_1928:36 0.0005780379 +37 ctsbuf_net_1928:37 0.002667492 +38 ctsbuf_net_1928:38 0.002089454 +39 ctsbuf_net_1928:39 0.0002857518 +40 ctsbuf_net_1928:40 7.956128e-05 +41 ctsbuf_net_1928:41 6.241948e-05 +42 ctsbuf_net_1928:42 5.91219e-05 +43 ctsbuf_net_1928:43 9.495943e-05 +44 ctsbuf_net_1928:44 0.001387879 +45 ctsbuf_net_1928:45 0.001067442 +46 ctsbuf_net_1928:46 0.002943367 +47 ctsbuf_net_1928:47 0.005786537 +48 ctsbuf_net_1928:48 0.00284317 +49 ctsbuf_net_1928:49 0.001984252 +50 ctsbuf_net_1928:50 0.003477661 +51 ctsbuf_net_1928:51 0.001740088 +52 ctsbuf_net_1928:52 0.0002806587 +53 ctsbuf_net_1928:53 0.0001029385 +54 ctsbuf_net_1928:54 6.292476e-05 +55 ctsbuf_net_1928:21 clk[0]:39 2.699283e-05 +56 ctsbuf_net_1928:21 clk[0]:40 0.0002256667 +57 ctsbuf_net_1928:22 clk[0]:39 0.0002256667 +58 ctsbuf_net_1928:18 clk[0]:40 2.699283e-05 +59 ctsbuf_net_1928:14 clk[0]:43 1.02825e-05 +60 ctsbuf_net_1928:14 clk[0]:44 0.0003721622 +61 ctsbuf_net_1928:13 clk[0]:44 2.057909e-05 +62 ctsbuf_net_1928:13 clk[0]:45 0.0005006063 +63 ctsbuf_net_1928:12 clk[0]:45 1.029659e-05 +64 ctsbuf_net_1928:12 clk[0]:46 0.0001986295 +65 ctsbuf_net_1928:15 clk[0]:43 7.018542e-05 +66 ctsbuf_net_1928:38 cbx_1__1__0_chanx_left_out[0]:5 9.487315e-05 +67 ctsbuf_net_1928:37 cbx_1__1__0_chanx_left_out[0]:6 9.487315e-05 +68 ctsbuf_net_1928:30 cbx_1__1__0_chanx_right_out[16]:6 0.0001060801 +69 ctsbuf_net_1928:29 cbx_1__1__0_chanx_right_out[16]:5 0.0001060801 +70 ctsbuf_net_1928:30 cbx_1__1__0_chanx_right_out[19]:6 9.660986e-05 +71 ctsbuf_net_1928:29 cbx_1__1__0_chanx_right_out[19]:5 9.660986e-05 +72 ctsbuf_net_1928:17 cbx_1__1__1_chanx_left_out[13]:5 1.712275e-05 +73 ctsbuf_net_1928:14 cbx_1__1__1_chanx_left_out[13]:8 6.809765e-05 +74 ctsbuf_net_1928:15 cbx_1__1__1_chanx_left_out[13]:7 6.809765e-05 +75 ctsbuf_net_1928:16 cbx_1__1__1_chanx_left_out[13]:6 1.712275e-05 +76 ctsbuf_net_1928:17 direct_interc_2_out[0]:25 0.0004447224 +77 ctsbuf_net_1928:16 direct_interc_2_out[0]:24 0.0004447224 +78 ctsbuf_net_1928:27 direct_interc_5_out[0]:27 0.0002079 +79 ctsbuf_net_1928:27 direct_interc_5_out[0]:28 2.705551e-05 +80 ctsbuf_net_1928:28 direct_interc_5_out[0]:26 1.049368e-05 +81 ctsbuf_net_1928:26 direct_interc_5_out[0]:28 0.0002079 +82 ctsbuf_net_1928:26 direct_interc_5_out[0]:29 2.705551e-05 +83 ctsbuf_net_1928:30 direct_interc_5_out[0]:25 1.61847e-05 +84 ctsbuf_net_1928:29 direct_interc_5_out[0]:25 1.049368e-05 +85 ctsbuf_net_1928:29 direct_interc_5_out[0]:26 1.61847e-05 +86 ctsbuf_net_1928:27 ctsbuf_net_211:18 0.0001189888 +87 ctsbuf_net_1928:28 ctsbuf_net_211:19 0.0001825343 +88 ctsbuf_net_1928:26 ctsbuf_net_211:17 0.0001189888 +89 ctsbuf_net_1928:30 ctsbuf_net_211:20 0.000334968 +90 ctsbuf_net_1928:29 ctsbuf_net_211:19 0.000334968 +91 ctsbuf_net_1928:29 ctsbuf_net_211:20 0.0001825343 +92 ctsbuf_net_1928:23 ctsbuf_net_413:5 8.900995e-05 +93 ctsbuf_net_1928:24 ctsbuf_net_413:6 8.900995e-05 +94 ctsbuf_net_1928:43 ctsbuf_net_1827:5 4.342113e-05 +95 ctsbuf_net_1928:40 ctsbuf_net_1827:6 2.896962e-06 +96 ctsbuf_net_1928:41 ctsbuf_net_1827:5 2.896962e-06 +97 ctsbuf_net_1928:42 ctsbuf_net_1827:6 4.342113e-05 +98 ctsbuf_net_1928:44 ctsbuf_net_2029:47 9.022113e-06 +99 ctsbuf_net_1928:44 ctsbuf_net_2029:46 8.952415e-05 +100 ctsbuf_net_1928:39 ctsbuf_net_2029:46 9.022113e-06 +101 ctsbuf_net_1928:38 ctsbuf_net_2029:45 0.000594722 +102 ctsbuf_net_1928:36 ctsbuf_net_2029:44 2.883806e-05 +103 ctsbuf_net_1928:36 ctsbuf_net_2029:43 0.0001340686 +104 ctsbuf_net_1928:33 ctsbuf_net_2029:44 3.242728e-05 +105 ctsbuf_net_1928:25 ctsbuf_net_2029:33 0.0005312886 +106 ctsbuf_net_1928:25 ctsbuf_net_2029:32 2.844165e-05 +107 ctsbuf_net_1928:23 ctsbuf_net_2029:31 0.0003871987 +108 ctsbuf_net_1928:23 ctsbuf_net_2029:27 1.543263e-05 +109 ctsbuf_net_1928:45 ctsbuf_net_2029:47 8.952415e-05 +110 ctsbuf_net_1928:46 ctsbuf_net_2029:48 0.0002884779 +111 ctsbuf_net_1928:46 ctsbuf_net_2029:49 0.0004590023 +112 ctsbuf_net_1928:49 ctsbuf_net_2029:10 0.0004193719 +113 ctsbuf_net_1928:49 ctsbuf_net_2029:11 0.0005409202 +114 ctsbuf_net_1928:48 ctsbuf_net_2029:51 0.0005794652 +115 ctsbuf_net_1928:48 ctsbuf_net_2029:50 0.0003110614 +116 ctsbuf_net_1928:51 ctsbuf_net_2029:12 0.0002041128 +117 ctsbuf_net_1928:50 ctsbuf_net_2029:12 0.0005409202 +118 ctsbuf_net_1928:50 ctsbuf_net_2029:11 0.0006234847 +119 ctsbuf_net_1928:47 ctsbuf_net_2029:50 0.001038468 +120 ctsbuf_net_1928:47 ctsbuf_net_2029:49 0.0005995394 +121 ctsbuf_net_1928:37 ctsbuf_net_2029:45 2.883806e-05 +122 ctsbuf_net_1928:37 ctsbuf_net_2029:44 0.0007287906 +123 ctsbuf_net_1928:30 ctsbuf_net_2029:37 1.469313e-05 +124 ctsbuf_net_1928:30 ctsbuf_net_2029:40 5.921104e-05 +125 ctsbuf_net_1928:30 ctsbuf_net_2029:41 0.0003680002 +126 ctsbuf_net_1928:29 ctsbuf_net_2029:36 1.469313e-05 +127 ctsbuf_net_1928:29 ctsbuf_net_2029:40 0.0001554905 +128 ctsbuf_net_1928:24 ctsbuf_net_2029:31 4.387428e-05 +129 ctsbuf_net_1928:24 ctsbuf_net_2029:32 0.0009184873 +130 ctsbuf_net_1928:31 ctsbuf_net_2029:41 5.921104e-05 +131 ctsbuf_net_1928:31 ctsbuf_net_2029:42 0.0002125097 +132 ctsbuf_net_1928:32 ctsbuf_net_2029:43 3.242728e-05 + +*RES +0 cts_inv_73827657:Y ctsbuf_net_1928:54 0.152 +1 ctsbuf_net_1928:43 ctsbuf_net_1928:42 0.0008214285 +2 ctsbuf_net_1928:44 ctsbuf_net_1928:43 0.0045 +3 ctsbuf_net_1928:44 ctsbuf_net_1928:39 0.00224442 +4 ctsbuf_net_1928:40 cts_inv_73677642:A 0.152 +5 ctsbuf_net_1928:20 ctsbuf_net_1928:19 0.0008214285 +6 ctsbuf_net_1928:21 ctsbuf_net_1928:20 0.0045 +7 ctsbuf_net_1928:21 ctsbuf_net_1928:18 0.001021205 +8 ctsbuf_net_1928:19 cts_inv_73617636:A 0.152 +9 ctsbuf_net_1928:39 ctsbuf_net_1928:38 0.00341 +10 ctsbuf_net_1928:38 ctsbuf_net_1928:37 0.003893166 +11 ctsbuf_net_1928:35 ctsbuf_net_1928:34 0.000890625 +12 ctsbuf_net_1928:36 ctsbuf_net_1928:35 0.00341 +13 ctsbuf_net_1928:34 ctsbuf_net_1928:33 0.00341 +14 ctsbuf_net_1928:33 ctsbuf_net_1928:32 0.0005827217 +15 ctsbuf_net_1928:27 ctsbuf_net_1928:26 0.01151563 +16 ctsbuf_net_1928:28 ctsbuf_net_1928:27 0.00341 +17 ctsbuf_net_1928:26 ctsbuf_net_1928:25 0.00341 +18 ctsbuf_net_1928:25 ctsbuf_net_1928:24 0.003893166 +19 ctsbuf_net_1928:22 ctsbuf_net_1928:21 0.008369421 +20 ctsbuf_net_1928:23 ctsbuf_net_1928:22 0.00341 +21 ctsbuf_net_1928:45 ctsbuf_net_1928:44 0.009271206 +22 ctsbuf_net_1928:46 ctsbuf_net_1928:45 0.00341 +23 ctsbuf_net_1928:49 ctsbuf_net_1928:48 0.00341 +24 ctsbuf_net_1928:48 ctsbuf_net_1928:47 0.003893166 +25 ctsbuf_net_1928:53 ctsbuf_net_1928:52 0.0045 +26 ctsbuf_net_1928:52 ctsbuf_net_1928:51 0.004683036 +27 ctsbuf_net_1928:54 ctsbuf_net_1928:53 0.0007879465 +28 ctsbuf_net_1928:18 ctsbuf_net_1928:17 0.00341 +29 ctsbuf_net_1928:17 ctsbuf_net_1928:16 0.002382822 +30 ctsbuf_net_1928:10 ctsbuf_net_1928:9 0.002712054 +31 ctsbuf_net_1928:11 ctsbuf_net_1928:10 0.00341 +32 ctsbuf_net_1928:9 ctsbuf_net_1928:8 0.00341 +33 ctsbuf_net_1928:8 ctsbuf_net_1928:7 0.0007183166 +34 ctsbuf_net_1928:6 ctsbuf_net_1928:5 0.0045 +35 ctsbuf_net_1928:7 ctsbuf_net_1928:6 0.00341 +36 ctsbuf_net_1928:5 ctsbuf_net_1928:4 0.0008214285 +37 ctsbuf_net_1928:4 cts_inv_73507625:A 0.152 +38 ctsbuf_net_1928:41 ctsbuf_net_1928:40 0.0004107143 +39 ctsbuf_net_1928:42 ctsbuf_net_1928:41 0.0003035715 +40 ctsbuf_net_1928:51 ctsbuf_net_1928:50 0.01389286 +41 ctsbuf_net_1928:50 ctsbuf_net_1928:49 0.0222288 +42 ctsbuf_net_1928:47 ctsbuf_net_1928:46 0.003601766 +43 ctsbuf_net_1928:37 ctsbuf_net_1928:36 0.001007367 +44 ctsbuf_net_1928:30 ctsbuf_net_1928:29 0.003916666 +45 ctsbuf_net_1928:29 ctsbuf_net_1928:28 0.0007300666 +46 ctsbuf_net_1928:24 ctsbuf_net_1928:23 0.0033135 +47 ctsbuf_net_1928:14 ctsbuf_net_1928:13 0.003916666 +48 ctsbuf_net_1928:13 ctsbuf_net_1928:12 0.003916666 +49 ctsbuf_net_1928:12 ctsbuf_net_1928:11 0.0006689666 +50 ctsbuf_net_1928:31 ctsbuf_net_1928:30 0.003310367 +51 ctsbuf_net_1928:32 ctsbuf_net_1928:31 1e-05 +52 ctsbuf_net_1928:15 ctsbuf_net_1928:14 0.001510267 +53 ctsbuf_net_1928:16 ctsbuf_net_1928:15 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_A[1] 0.0305291 //LENGTH 345.895 LUMPCC 0 DR + +*CONN +*I grid_io_top_2__3_:gfpga_pad_GPIO_A[0] O *L 0 *C 767.740 924.730 +*P gfpga_pad_GPIO_A[1] O *L 0 *C 694.140 1196.385 +*N gfpga_pad_GPIO_A[1]:2 *C 694.140 1174.220 +*N gfpga_pad_GPIO_A[1]:3 *C 694.140 1124.425 +*N gfpga_pad_GPIO_A[1]:4 *C 694.185 1124.380 +*N gfpga_pad_GPIO_A[1]:5 *C 743.980 1124.380 +*N gfpga_pad_GPIO_A[1]:6 *C 767.695 1124.380 +*N gfpga_pad_GPIO_A[1]:7 *C 767.740 1124.335 +*N gfpga_pad_GPIO_A[1]:8 *C 767.740 1115.520 +*N gfpga_pad_GPIO_A[1]:9 *C 767.740 1115.519 +*N gfpga_pad_GPIO_A[1]:10 *C 767.740 1074.730 +*N gfpga_pad_GPIO_A[1]:11 *C 767.740 1024.730 +*N gfpga_pad_GPIO_A[1]:12 *C 767.740 974.730 + +*CAP +0 grid_io_top_2__3_:gfpga_pad_GPIO_A[0] 0.002209091 +1 gfpga_pad_GPIO_A[1] 0.0009322873 +2 gfpga_pad_GPIO_A[1]:2 0.003056131 +3 gfpga_pad_GPIO_A[1]:3 0.002123844 +4 gfpga_pad_GPIO_A[1]:4 0.00242841 +5 gfpga_pad_GPIO_A[1]:5 0.003583067 +6 gfpga_pad_GPIO_A[1]:6 0.001154657 +7 gfpga_pad_GPIO_A[1]:7 0.0003776479 +8 gfpga_pad_GPIO_A[1]:8 0.0003776479 +9 gfpga_pad_GPIO_A[1]:9 0.001756092 +10 gfpga_pad_GPIO_A[1]:10 0.003896233 +11 gfpga_pad_GPIO_A[1]:11 0.004282523 +12 gfpga_pad_GPIO_A[1]:12 0.004351473 + +*RES +0 grid_io_top_2__3_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[1]:12 0.04464286 +1 gfpga_pad_GPIO_A[1]:6 gfpga_pad_GPIO_A[1]:5 0.02117411 +2 gfpga_pad_GPIO_A[1]:7 gfpga_pad_GPIO_A[1]:6 0.0045 +3 gfpga_pad_GPIO_A[1]:4 gfpga_pad_GPIO_A[1]:3 0.0045 +4 gfpga_pad_GPIO_A[1]:3 gfpga_pad_GPIO_A[1]:2 0.04445983 +5 gfpga_pad_GPIO_A[1]:5 gfpga_pad_GPIO_A[1]:4 0.04445982 +6 gfpga_pad_GPIO_A[1]:2 gfpga_pad_GPIO_A[1] 0.01979018 +7 gfpga_pad_GPIO_A[1]:12 gfpga_pad_GPIO_A[1]:11 0.04464286 +8 gfpga_pad_GPIO_A[1]:11 gfpga_pad_GPIO_A[1]:10 0.04464286 +9 gfpga_pad_GPIO_A[1]:10 gfpga_pad_GPIO_A[1]:9 0.03641875 +10 gfpga_pad_GPIO_A[1]:8 gfpga_pad_GPIO_A[1]:7 0.007870536 +11 gfpga_pad_GPIO_A[1]:9 gfpga_pad_GPIO_A[1]:8 1e-05 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[19] 0.001269324 //LENGTH 11.020 LUMPCC 0.0005516617 DR + +*CONN +*I cby_0__2_:chany_bottom_out[19] O *L 0 *C 334.420 669.190 +*I sb_0__1_:chany_top_in[19] I *L 0 *C 334.420 658.170 +*N cby_0__1__1_chany_bottom_out[19]:2 *C 334.420 667.519 +*N cby_0__1__1_chany_bottom_out[19]:3 *C 334.420 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[19] 0.0001115404 +1 sb_0__1_:chany_top_in[19] 0.0002472905 +2 cby_0__1__1_chany_bottom_out[19]:2 0.0002472905 +3 cby_0__1__1_chany_bottom_out[19]:3 0.0001115404 +4 cby_0__2_:chany_bottom_out[19] cby_0__2_:chany_bottom_in[10] 7.193657e-06 +5 sb_0__1_:chany_top_in[19] sb_0__1_:chany_top_out[10] 0.0001307218 +6 cby_0__1__1_chany_bottom_out[19]:3 sb_0__1__0_chany_top_out[10]:2 7.193657e-06 +7 cby_0__1__1_chany_bottom_out[19]:2 sb_0__1__0_chany_top_out[10]:3 0.0001307218 +8 cby_0__2_:chany_bottom_out[19] cby_0__2_:chany_bottom_in[16] 7.193657e-06 +9 sb_0__1_:chany_top_in[19] sb_0__1_:chany_top_out[16] 0.0001307218 +10 cby_0__1__1_chany_bottom_out[19]:3 sb_0__1__0_chany_top_out[16]:2 7.193657e-06 +11 cby_0__1__1_chany_bottom_out[19]:2 sb_0__1__0_chany_top_out[16]:3 0.0001307218 + +*RES +0 cby_0__2_:chany_bottom_out[19] cby_0__1__1_chany_bottom_out[19]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[19]:3 cby_0__1__1_chany_bottom_out[19]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[19]:2 sb_0__1_:chany_top_in[19] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_top_out[9] 0.00125688 //LENGTH 11.020 LUMPCC 0.0005621223 DR + +*CONN +*I cby_0__2_:chany_top_out[9] O *L 0 *C 310.040 777.850 +*I sb_0__2_:chany_bottom_in[9] I *L 0 *C 310.040 788.870 + +*CAP +0 cby_0__2_:chany_top_out[9] 0.0003473787 +1 sb_0__2_:chany_bottom_in[9] 0.0003473787 +2 cby_0__2_:chany_top_out[9] cby_0__2_:chany_top_out[7] 0.0001405306 +3 sb_0__2_:chany_bottom_in[9] sb_0__2_:chany_bottom_in[7] 0.0001405306 +4 cby_0__2_:chany_top_out[9] cby_0__2_:chany_top_out[8] 0.0001405306 +5 sb_0__2_:chany_bottom_in[9] sb_0__2_:chany_bottom_in[8] 0.0001405306 + +*RES +0 cby_0__2_:chany_top_out[9] sb_0__2_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[15] 0.001268302 //LENGTH 11.020 LUMPCC 0.000553927 DR + +*CONN +*I cby_0__2_:chany_top_out[15] O *L 0 *C 333.500 777.850 +*I sb_0__2_:chany_bottom_in[15] I *L 0 *C 333.500 788.870 + +*CAP +0 cby_0__2_:chany_top_out[15] 0.0003571876 +1 sb_0__2_:chany_bottom_in[15] 0.0003571876 +2 cby_0__2_:chany_top_out[15] cby_0__2_:chany_top_in[5] 0.0001384818 +3 sb_0__2_:chany_bottom_in[15] sb_0__2_:chany_bottom_out[5] 0.0001384818 +4 cby_0__2_:chany_top_out[15] cby_0__2_:chany_top_in[17] 0.0001384818 +5 sb_0__2_:chany_bottom_in[15] sb_0__2_:chany_bottom_out[17] 0.0001384818 + +*RES +0 cby_0__2_:chany_top_out[15] sb_0__2_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[1] 0.001136784 //LENGTH 11.020 LUMPCC 0.0003792299 DR + +*CONN +*I cby_1__1_:chany_bottom_out[1] O *L 0 *C 577.300 408.070 +*I sb_1__0_:chany_top_in[1] I *L 0 *C 577.300 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[1] 0.0003787772 +1 sb_1__0_:chany_top_in[1] 0.0003787772 +2 cby_1__1_:chany_bottom_out[1] cby_1__1_:chany_bottom_out[14] 3.733719e-05 +3 sb_1__0_:chany_top_in[1] sb_1__0_:chany_top_in[14] 3.733719e-05 +4 cby_1__1_:chany_bottom_out[1] cby_1__1_:chany_bottom_in[9] 0.0001522778 +5 sb_1__0_:chany_top_in[1] sb_1__0_:chany_top_out[9] 0.0001522778 + +*RES +0 cby_1__1_:chany_bottom_out[1] sb_1__0_:chany_top_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[9] 0.001231889 //LENGTH 11.020 LUMPCC 0.0005932347 DR + +*CONN +*I cby_1__1_:chany_bottom_out[9] O *L 0 *C 587.420 408.070 +*I sb_1__0_:chany_top_in[9] I *L 0 *C 587.420 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[9] 0.0003193272 +1 sb_1__0_:chany_top_in[9] 0.0003193272 +2 cby_1__1_:chany_bottom_out[9] cby_1__1_:chany_bottom_out[7] 0.0001480614 +3 sb_1__0_:chany_top_in[9] sb_1__0_:chany_top_in[7] 0.0001480614 +4 cby_1__1_:chany_bottom_out[9] cby_1__1_:chany_bottom_in[8] 0.000148556 +5 sb_1__0_:chany_top_in[9] sb_1__0_:chany_top_out[8] 0.000148556 + +*RES +0 cby_1__1_:chany_bottom_out[9] sb_1__0_:chany_top_in[9] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[15] 0.001219382 //LENGTH 11.020 LUMPCC 0.0005990836 DR + +*CONN +*I cby_1__1_:chany_bottom_out[15] O *L 0 *C 573.620 408.070 +*I sb_1__0_:chany_top_in[15] I *L 0 *C 573.620 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[15] 0.0003101493 +1 sb_1__0_:chany_top_in[15] 0.0003101493 +2 cby_1__1_:chany_bottom_out[15] cby_1__1_:chany_bottom_out[12] 0.000147264 +3 sb_1__0_:chany_top_in[15] sb_1__0_:chany_top_in[12] 0.000147264 +4 cby_1__1_:chany_bottom_out[15] cby_1__1_:chany_bottom_out[14] 0.0001522778 +5 sb_1__0_:chany_top_in[15] sb_1__0_:chany_top_in[14] 0.0001522778 + +*RES +0 cby_1__1_:chany_bottom_out[15] sb_1__0_:chany_top_in[15] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[2] 0.001292694 //LENGTH 11.020 LUMPCC 0.0005090936 DR + +*CONN +*I cby_1__1_:chany_top_out[2] O *L 0 *C 601.220 516.730 +*I sb_1__1_:chany_bottom_in[2] I *L 0 *C 601.220 527.750 + +*CAP +0 cby_1__1_:chany_top_out[2] 0.0003918004 +1 sb_1__1_:chany_bottom_in[2] 0.0003918004 +2 cby_1__1_:chany_top_out[2] cby_1__1_:chany_top_out[0] 0.0001256454 +3 sb_1__1_:chany_bottom_in[2] sb_1__1_:chany_bottom_in[0] 0.0001256454 +4 cby_1__1_:chany_top_out[2] cby_1__1_:chany_top_in[12] 0.0001289014 +5 sb_1__1_:chany_bottom_in[2] sb_1__1_:chany_bottom_out[12] 0.0001289014 + +*RES +0 cby_1__1_:chany_top_out[2] sb_1__1_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[10] 0.001295275 //LENGTH 11.020 LUMPCC 0.0004990738 DR + +*CONN +*I cby_1__1_:chany_top_out[10] O *L 0 *C 582.360 516.730 +*I sb_1__1_:chany_bottom_in[10] I *L 0 *C 582.360 527.750 + +*CAP +0 cby_1__1_:chany_top_out[10] 0.0003981007 +1 sb_1__1_:chany_bottom_in[10] 0.0003981007 +2 cby_1__1_:chany_top_out[10] cby_1__1_:chany_top_in[8] 0.0001247684 +3 sb_1__1_:chany_bottom_in[10] sb_1__1_:chany_bottom_out[8] 0.0001247684 +4 cby_1__1_:chany_top_out[10] cby_1__1_:chany_top_in[13] 0.0001247684 +5 sb_1__1_:chany_bottom_in[10] sb_1__1_:chany_bottom_out[13] 0.0001247684 + +*RES +0 cby_1__1_:chany_top_out[10] sb_1__1_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[16] 0.001288243 //LENGTH 11.020 LUMPCC 0.0004996872 DR + +*CONN +*I cby_1__1_:chany_top_out[16] O *L 0 *C 596.620 516.730 +*I sb_1__1_:chany_bottom_in[16] I *L 0 *C 596.620 527.750 + +*CAP +0 cby_1__1_:chany_top_out[16] 0.0003942778 +1 sb_1__1_:chany_bottom_in[16] 0.0003942778 +2 cby_1__1_:chany_top_out[16] cby_1__1_:chany_top_out[5] 0.0001209422 +3 sb_1__1_:chany_bottom_in[16] sb_1__1_:chany_bottom_in[5] 0.0001209422 +4 cby_1__1_:chany_top_out[16] cby_1__1_:chany_top_out[8] 0.0001289014 +5 sb_1__1_:chany_bottom_in[16] sb_1__1_:chany_bottom_in[8] 0.0001289014 + +*RES +0 cby_1__1_:chany_top_out[16] sb_1__1_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_14_[0] 0.001397359 //LENGTH 7.660 LUMPCC 0.0002480144 DR + +*CONN +*I cby_1__1_:left_grid_pin_14_[0] O *L 0 *C 548.470 463.760 +*I grid_clb_1__1_:right_width_0_height_0__pin_14_[0] I *L 0 *C 540.810 463.760 + +*CAP +0 cby_1__1_:left_grid_pin_14_[0] 0.0005746725 +1 grid_clb_1__1_:right_width_0_height_0__pin_14_[0] 0.0005746725 +2 cby_1__1_:left_grid_pin_14_[0] cby_1__1_:left_grid_pin_13_[0] 0.0001240072 +3 grid_clb_1__1_:right_width_0_height_0__pin_14_[0] grid_clb_1__1_:right_width_0_height_0__pin_13_[0] 0.0001240072 + +*RES +0 cby_1__1_:left_grid_pin_14_[0] grid_clb_1__1_:right_width_0_height_0__pin_14_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_5_[0] 0.001408769 //LENGTH 7.660 LUMPCC 0.0002378138 DR + +*CONN +*I cby_1__1_:left_grid_pin_5_[0] O *L 0 *C 548.470 511.360 +*I grid_clb_1__1_:right_width_0_height_0__pin_5_[0] I *L 0 *C 540.810 511.360 + +*CAP +0 cby_1__1_:left_grid_pin_5_[0] 0.0005854777 +1 grid_clb_1__1_:right_width_0_height_0__pin_5_[0] 0.0005854777 +2 cby_1__1_:left_grid_pin_5_[0] cby_1__1_:left_grid_pin_0_[0] 0.0001189069 +3 grid_clb_1__1_:right_width_0_height_0__pin_5_[0] grid_clb_1__1_:right_width_0_height_0__pin_0_[0] 0.0001189069 + +*RES +0 cby_1__1_:left_grid_pin_5_[0] grid_clb_1__1_:right_width_0_height_0__pin_5_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_8_[0] 0.001317091 //LENGTH 7.660 LUMPCC 0.0002778929 DR + +*CONN +*I cby_1__1_:left_grid_pin_8_[0] O *L 0 *C 548.470 484.160 +*I grid_clb_1__1_:right_width_0_height_0__pin_8_[0] I *L 0 *C 540.810 484.160 + +*CAP +0 cby_1__1_:left_grid_pin_8_[0] 0.0005195988 +1 grid_clb_1__1_:right_width_0_height_0__pin_8_[0] 0.0005195988 +2 cby_1__1_:left_grid_pin_8_[0] cby_1__1_:left_grid_pin_11_[0] 0.0001389464 +3 grid_clb_1__1_:right_width_0_height_0__pin_8_[0] grid_clb_1__1_:right_width_0_height_0__pin_11_[0] 0.0001389464 + +*RES +0 cby_1__1_:left_grid_pin_8_[0] grid_clb_1__1_:right_width_0_height_0__pin_8_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[3] 0.001250985 //LENGTH 11.020 LUMPCC 0.00057206 DR + +*CONN +*I cby_1__2_:chany_bottom_out[3] O *L 0 *C 593.860 669.190 +*I sb_1__1_:chany_top_in[3] I *L 0 *C 593.860 658.170 +*N cby_1__1__1_chany_bottom_out[3]:2 *C 593.860 667.519 +*N cby_1__1__1_chany_bottom_out[3]:3 *C 593.860 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[3] 0.0001111417 +1 sb_1__1_:chany_top_in[3] 0.0002283207 +2 cby_1__1__1_chany_bottom_out[3]:2 0.0002283207 +3 cby_1__1__1_chany_bottom_out[3]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[3] cby_1__2_:chany_bottom_out[6] 7.294814e-06 +5 sb_1__1_:chany_top_in[3] sb_1__1_:chany_top_in[6] 0.0001357202 +6 cby_1__1__1_chany_bottom_out[3]:3 cby_1__1__1_chany_bottom_out[6]:3 7.294814e-06 +7 cby_1__1__1_chany_bottom_out[3]:2 cby_1__1__1_chany_bottom_out[6]:2 0.0001357202 +8 cby_1__2_:chany_bottom_out[3] cby_1__2_:chany_bottom_out[10] 7.294814e-06 +9 sb_1__1_:chany_top_in[3] sb_1__1_:chany_top_in[10] 0.0001357202 +10 cby_1__1__1_chany_bottom_out[3]:3 cby_1__1__1_chany_bottom_out[10]:3 7.294814e-06 +11 cby_1__1__1_chany_bottom_out[3]:2 cby_1__1__1_chany_bottom_out[10]:2 0.0001357202 + +*RES +0 cby_1__2_:chany_bottom_out[3] cby_1__1__1_chany_bottom_out[3]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[3]:3 cby_1__1__1_chany_bottom_out[3]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[3]:2 sb_1__1_:chany_top_in[3] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[11] 0.001252005 //LENGTH 11.020 LUMPCC 0.0005715448 DR + +*CONN +*I cby_1__2_:chany_bottom_out[11] O *L 0 *C 595.700 669.190 +*I sb_1__1_:chany_top_in[11] I *L 0 *C 595.700 658.170 +*N cby_1__1__1_chany_bottom_out[11]:2 *C 595.700 667.519 +*N cby_1__1__1_chany_bottom_out[11]:3 *C 595.700 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[11] 0.0001111417 +1 sb_1__1_:chany_top_in[11] 0.0002290884 +2 cby_1__1__1_chany_bottom_out[11]:2 0.0002290884 +3 cby_1__1__1_chany_bottom_out[11]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[11] cby_1__2_:chany_bottom_out[6] 7.294814e-06 +5 sb_1__1_:chany_top_in[11] sb_1__1_:chany_top_in[6] 0.0001354626 +6 cby_1__1__1_chany_bottom_out[11]:3 cby_1__1__1_chany_bottom_out[6]:3 7.294814e-06 +7 cby_1__1__1_chany_bottom_out[11]:2 cby_1__1__1_chany_bottom_out[6]:2 0.0001354626 +8 cby_1__2_:chany_bottom_out[11] cby_1__2_:chany_bottom_in[0] 7.294814e-06 +9 sb_1__1_:chany_top_in[11] sb_1__1_:chany_top_out[0] 0.0001357202 +10 cby_1__1__1_chany_bottom_out[11]:3 sb_1__1__0_chany_top_out[0]:2 7.294814e-06 +11 cby_1__1__1_chany_bottom_out[11]:2 sb_1__1__0_chany_top_out[0]:3 0.0001357202 + +*RES +0 cby_1__2_:chany_bottom_out[11] cby_1__1__1_chany_bottom_out[11]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[11]:3 cby_1__1__1_chany_bottom_out[11]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[11]:2 sb_1__1_:chany_top_in[11] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[19] 0.001250537 //LENGTH 11.020 LUMPCC 0.0005737565 DR + +*CONN +*I cby_1__2_:chany_bottom_out[19] O *L 0 *C 579.140 669.190 +*I sb_1__1_:chany_top_in[19] I *L 0 *C 579.140 658.170 +*N cby_1__1__1_chany_bottom_out[19]:2 *C 579.140 667.519 +*N cby_1__1__1_chany_bottom_out[19]:3 *C 579.140 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[19] 0.0001111417 +1 sb_1__1_:chany_top_in[19] 0.0002272485 +2 cby_1__1__1_chany_bottom_out[19]:2 0.0002272485 +3 cby_1__1__1_chany_bottom_out[19]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[19] cby_1__2_:chany_bottom_out[5] 7.295327e-06 +5 sb_1__1_:chany_top_in[19] sb_1__1_:chany_top_in[5] 0.0001361438 +6 cby_1__1__1_chany_bottom_out[19]:3 cby_1__1__1_chany_bottom_out[5]:3 7.295327e-06 +7 cby_1__1__1_chany_bottom_out[19]:2 cby_1__1__1_chany_bottom_out[5]:2 0.0001361438 +8 cby_1__2_:chany_bottom_out[19] cby_1__2_:chany_bottom_in[9] 7.295327e-06 +9 sb_1__1_:chany_top_in[19] sb_1__1_:chany_top_out[9] 0.0001361438 +10 cby_1__1__1_chany_bottom_out[19]:3 sb_1__1__0_chany_top_out[9]:2 7.295327e-06 +11 cby_1__1__1_chany_bottom_out[19]:2 sb_1__1__0_chany_top_out[9]:3 0.0001361438 + +*RES +0 cby_1__2_:chany_bottom_out[19] cby_1__1__1_chany_bottom_out[19]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[19]:3 cby_1__1__1_chany_bottom_out[19]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[19]:2 sb_1__1_:chany_top_in[19] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_top_out[8] 0.001260929 //LENGTH 11.020 LUMPCC 0.0005428599 DR + +*CONN +*I cby_1__2_:chany_top_out[8] O *L 0 *C 597.540 777.850 +*I sb_1__2_:chany_bottom_in[8] I *L 0 *C 597.540 788.870 + +*CAP +0 cby_1__2_:chany_top_out[8] 0.0003590344 +1 sb_1__2_:chany_bottom_in[8] 0.0003590344 +2 cby_1__2_:chany_top_out[8] cby_1__2_:chany_top_out[16] 0.000135715 +3 sb_1__2_:chany_bottom_in[8] sb_1__2_:chany_bottom_in[16] 0.000135715 +4 cby_1__2_:chany_top_out[8] cby_1__2_:chany_top_out[19] 0.000135715 +5 sb_1__2_:chany_bottom_in[8] sb_1__2_:chany_bottom_in[19] 0.000135715 + +*RES +0 cby_1__2_:chany_top_out[8] sb_1__2_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[18] 0.001164097 //LENGTH 11.020 LUMPCC 0.0002398979 DR + +*CONN +*I cby_1__2_:chany_top_out[18] O *L 0 *C 577.300 777.850 +*I sb_1__2_:chany_bottom_in[18] I *L 0 *C 577.300 788.870 + +*CAP +0 cby_1__2_:chany_top_out[18] 0.0004620996 +1 sb_1__2_:chany_bottom_in[18] 0.0004620996 +2 cby_1__2_:chany_top_out[18] cby_1__2_:chany_top_in[15] 3.864802e-05 +3 sb_1__2_:chany_bottom_in[18] sb_1__2_:chany_bottom_out[15] 3.864802e-05 +4 cby_1__2_:chany_top_out[18] cby_1__2_:chany_top_in[17] 8.130095e-05 +5 sb_1__2_:chany_bottom_in[18] sb_1__2_:chany_bottom_out[17] 8.130095e-05 + +*RES +0 cby_1__2_:chany_top_out[18] sb_1__2_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_14_[0] 0.001382867 //LENGTH 7.660 LUMPCC 0.0002443562 DR + +*CONN +*I cby_1__2_:left_grid_pin_14_[0] O *L 0 *C 548.470 724.880 +*I grid_clb_1__2_:right_width_0_height_0__pin_14_[0] I *L 0 *C 540.810 724.880 + +*CAP +0 cby_1__2_:left_grid_pin_14_[0] 0.0005692554 +1 grid_clb_1__2_:right_width_0_height_0__pin_14_[0] 0.0005692554 +2 cby_1__2_:left_grid_pin_14_[0] cby_1__2_:left_grid_pin_13_[0] 0.0001221781 +3 grid_clb_1__2_:right_width_0_height_0__pin_14_[0] grid_clb_1__2_:right_width_0_height_0__pin_13_[0] 0.0001221781 + +*RES +0 cby_1__2_:left_grid_pin_14_[0] grid_clb_1__2_:right_width_0_height_0__pin_14_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_8_[0] 0.001436287 //LENGTH 7.660 LUMPCC 0.0002082454 DR + +*CONN +*I cby_1__2_:left_grid_pin_8_[0] O *L 0 *C 548.470 745.280 +*I grid_clb_1__2_:right_width_0_height_0__pin_8_[0] I *L 0 *C 540.810 745.280 + +*CAP +0 cby_1__2_:left_grid_pin_8_[0] 0.0006140206 +1 grid_clb_1__2_:right_width_0_height_0__pin_8_[0] 0.0006140206 +2 cby_1__2_:left_grid_pin_8_[0] cby_1__2_:left_grid_pin_11_[0] 0.0001041227 +3 grid_clb_1__2_:right_width_0_height_0__pin_8_[0] grid_clb_1__2_:right_width_0_height_0__pin_11_[0] 0.0001041227 + +*RES +0 cby_1__2_:left_grid_pin_8_[0] grid_clb_1__2_:right_width_0_height_0__pin_8_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[3] 0.001231928 //LENGTH 11.020 LUMPCC 0.0005937052 DR + +*CONN +*I cby_2__1_:chany_bottom_out[3] O *L 0 *C 855.140 408.070 +*I sb_2__0_:chany_top_in[3] I *L 0 *C 855.140 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[3] 0.0003191112 +1 sb_2__0_:chany_top_in[3] 0.0003191112 +2 cby_2__1_:chany_bottom_out[3] cby_2__1_:chany_bottom_out[6] 0.0001484263 +3 sb_2__0_:chany_top_in[3] sb_2__0_:chany_top_in[6] 0.0001484263 +4 cby_2__1_:chany_bottom_out[3] cby_2__1_:chany_bottom_out[10] 0.0001484263 +5 sb_2__0_:chany_top_in[3] sb_2__0_:chany_top_in[10] 0.0001484263 + +*RES +0 cby_2__1_:chany_bottom_out[3] sb_2__0_:chany_top_in[3] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[11] 0.001228792 //LENGTH 11.020 LUMPCC 0.0005917205 DR + +*CONN +*I cby_2__1_:chany_bottom_out[11] O *L 0 *C 856.980 408.070 +*I sb_2__0_:chany_top_in[11] I *L 0 *C 856.980 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[11] 0.0003185358 +1 sb_2__0_:chany_top_in[11] 0.0003185358 +2 cby_2__1_:chany_bottom_out[11] cby_2__1_:chany_bottom_out[6] 0.0001479301 +3 sb_2__0_:chany_top_in[11] sb_2__0_:chany_top_in[6] 0.0001479301 +4 cby_2__1_:chany_bottom_out[11] cby_2__1_:chany_bottom_in[0] 0.0001479301 +5 sb_2__0_:chany_top_in[11] sb_2__0_:chany_top_out[0] 0.0001479301 + +*RES +0 cby_2__1_:chany_bottom_out[11] sb_2__0_:chany_top_in[11] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[0] 0.001281216 //LENGTH 11.020 LUMPCC 0.0005269798 DR + +*CONN +*I cby_2__1_:chany_top_out[0] O *L 0 *C 863.420 516.730 +*I sb_2__1_:chany_bottom_in[0] I *L 0 *C 863.420 527.750 + +*CAP +0 cby_2__1_:chany_top_out[0] 0.0003771181 +1 sb_2__1_:chany_bottom_in[0] 0.0003771181 +2 cby_2__1_:chany_top_out[0] cby_2__1_:chany_top_out[2] 0.0001317449 +3 sb_2__1_:chany_bottom_in[0] sb_2__1_:chany_bottom_in[2] 0.0001317449 +4 cby_2__1_:chany_top_out[0] cby_2__1_:chany_top_in[0] 0.0001317449 +5 sb_2__1_:chany_bottom_in[0] sb_2__1_:chany_bottom_out[0] 0.0001317449 + +*RES +0 cby_2__1_:chany_top_out[0] sb_2__1_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[7] 0.001267166 //LENGTH 11.020 LUMPCC 0.0005465996 DR + +*CONN +*I cby_2__1_:chany_top_out[7] O *L 0 *C 868.480 516.730 +*I sb_2__1_:chany_bottom_in[7] I *L 0 *C 868.480 527.750 + +*CAP +0 cby_2__1_:chany_top_out[7] 0.000360283 +1 sb_2__1_:chany_bottom_in[7] 0.000360283 +2 cby_2__1_:chany_top_out[7] cby_2__1_:chany_top_out[3] 0.0001366499 +3 sb_2__1_:chany_bottom_in[7] sb_2__1_:chany_bottom_in[3] 0.0001366499 +4 cby_2__1_:chany_top_out[7] cby_2__1_:chany_top_out[11] 0.0001366499 +5 sb_2__1_:chany_bottom_in[7] sb_2__1_:chany_bottom_in[11] 0.0001366499 + +*RES +0 cby_2__1_:chany_top_out[7] sb_2__1_:chany_bottom_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[16] 0.001281526 //LENGTH 11.020 LUMPCC 0.0005305507 DR + +*CONN +*I cby_2__1_:chany_top_out[16] O *L 0 *C 857.900 516.730 +*I sb_2__1_:chany_bottom_in[16] I *L 0 *C 857.900 527.750 + +*CAP +0 cby_2__1_:chany_top_out[16] 0.0003754878 +1 sb_2__1_:chany_bottom_in[16] 0.0003754878 +2 cby_2__1_:chany_top_out[16] cby_2__1_:chany_top_out[5] 0.0001314988 +3 sb_2__1_:chany_bottom_in[16] sb_2__1_:chany_bottom_in[5] 0.0001314988 +4 cby_2__1_:chany_top_out[16] cby_2__1_:chany_top_out[8] 0.0001337766 +5 sb_2__1_:chany_bottom_in[16] sb_2__1_:chany_bottom_in[8] 0.0001337766 + +*RES +0 cby_2__1_:chany_top_out[16] sb_2__1_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_14_[0] 0.001091851 //LENGTH 7.660 LUMPCC 0.0003595714 DR + +*CONN +*I cby_2__1_:left_grid_pin_14_[0] O *L 0 *C 809.750 463.760 +*I grid_clb_2__1_:right_width_0_height_0__pin_14_[0] I *L 0 *C 802.090 463.760 + +*CAP +0 cby_2__1_:left_grid_pin_14_[0] 0.0003661396 +1 grid_clb_2__1_:right_width_0_height_0__pin_14_[0] 0.0003661396 +2 cby_2__1_:left_grid_pin_14_[0] cby_2__1_:left_grid_pin_13_[0] 0.0001797857 +3 grid_clb_2__1_:right_width_0_height_0__pin_14_[0] grid_clb_2__1_:right_width_0_height_0__pin_13_[0] 0.0001797857 + +*RES +0 cby_2__1_:left_grid_pin_14_[0] grid_clb_2__1_:right_width_0_height_0__pin_14_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_7_[0] 0.001205351 //LENGTH 7.660 LUMPCC 0.0007228348 DR + +*CONN +*I cby_2__1_:left_grid_pin_7_[0] O *L 0 *C 809.750 507.280 +*I grid_clb_2__1_:right_width_0_height_0__pin_7_[0] I *L 0 *C 802.090 507.280 + +*CAP +0 cby_2__1_:left_grid_pin_7_[0] 0.0002412581 +1 grid_clb_2__1_:right_width_0_height_0__pin_7_[0] 0.0002412581 +2 cby_2__1_:left_grid_pin_7_[0] cby_2__1_:left_grid_pin_2_[0] 0.0001795292 +3 grid_clb_2__1_:right_width_0_height_0__pin_7_[0] grid_clb_2__1_:right_width_0_height_0__pin_2_[0] 0.0001795292 +4 cby_2__1_:left_grid_pin_7_[0] cby_2__1_:left_grid_pin_4_[0] 0.0001818883 +5 grid_clb_2__1_:right_width_0_height_0__pin_7_[0] grid_clb_2__1_:right_width_0_height_0__pin_4_[0] 0.0001818883 + +*RES +0 cby_2__1_:left_grid_pin_7_[0] grid_clb_2__1_:right_width_0_height_0__pin_7_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[3] 0.001258107 //LENGTH 11.020 LUMPCC 0.0005567565 DR + +*CONN +*I cby_2__2_:chany_bottom_out[3] O *L 0 *C 855.140 669.190 +*I sb_2__1_:chany_top_in[3] I *L 0 *C 855.140 658.170 +*N cby_1__1__3_chany_bottom_out[3]:2 *C 855.140 667.519 +*N cby_1__1__3_chany_bottom_out[3]:3 *C 855.140 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[3] 0.0001109382 +1 sb_2__1_:chany_top_in[3] 0.0002397372 +2 cby_1__1__3_chany_bottom_out[3]:2 0.0002397372 +3 cby_1__1__3_chany_bottom_out[3]:3 0.0001109382 +4 cby_2__2_:chany_bottom_out[3] cby_2__2_:chany_bottom_out[6] 7.346249e-06 +5 sb_2__1_:chany_top_in[3] sb_2__1_:chany_top_in[6] 0.0001318429 +6 cby_1__1__3_chany_bottom_out[3]:3 cby_1__1__3_chany_bottom_out[6]:3 7.346249e-06 +7 cby_1__1__3_chany_bottom_out[3]:2 cby_1__1__3_chany_bottom_out[6]:2 0.0001318429 +8 cby_2__2_:chany_bottom_out[3] cby_2__2_:chany_bottom_out[10] 7.346249e-06 +9 sb_2__1_:chany_top_in[3] sb_2__1_:chany_top_in[10] 0.0001318429 +10 cby_1__1__3_chany_bottom_out[3]:3 cby_1__1__3_chany_bottom_out[10]:3 7.346249e-06 +11 cby_1__1__3_chany_bottom_out[3]:2 cby_1__1__3_chany_bottom_out[10]:2 0.0001318429 + +*RES +0 cby_2__2_:chany_bottom_out[3] cby_1__1__3_chany_bottom_out[3]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[3]:3 cby_1__1__3_chany_bottom_out[3]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[3]:2 sb_2__1_:chany_top_in[3] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[14] 0.00118593 //LENGTH 11.020 LUMPCC 0.0003414615 DR + +*CONN +*I cby_2__2_:chany_bottom_out[14] O *L 0 *C 835.820 669.190 +*I sb_2__1_:chany_top_in[14] I *L 0 *C 835.820 658.170 +*N cby_1__1__3_chany_bottom_out[14]:2 *C 835.820 667.519 +*N cby_1__1__3_chany_bottom_out[14]:3 *C 835.820 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[14] 0.0001184705 +1 sb_2__1_:chany_top_in[14] 0.0003037639 +2 cby_1__1__3_chany_bottom_out[14]:2 0.0003037639 +3 cby_1__1__3_chany_bottom_out[14]:3 0.0001184705 +4 sb_2__1_:chany_top_in[14] sb_2__1_:chany_top_in[1] 3.174563e-05 +5 cby_1__1__3_chany_bottom_out[14]:2 cby_1__1__3_chany_bottom_out[1]:2 3.174563e-05 +6 cby_2__2_:chany_bottom_out[14] cby_2__2_:chany_bottom_out[15] 7.244793e-06 +7 sb_2__1_:chany_top_in[14] sb_2__1_:chany_top_in[15] 0.0001317403 +8 cby_1__1__3_chany_bottom_out[14]:3 cby_1__1__3_chany_bottom_out[15]:3 7.244793e-06 +9 cby_1__1__3_chany_bottom_out[14]:2 cby_1__1__3_chany_bottom_out[15]:2 0.0001317403 + +*RES +0 cby_2__2_:chany_bottom_out[14] cby_1__1__3_chany_bottom_out[14]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[14]:3 cby_1__1__3_chany_bottom_out[14]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[14]:2 sb_2__1_:chany_top_in[14] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_top_out[3] 0.001169159 //LENGTH 11.020 LUMPCC 0.0002929681 DR + +*CONN +*I cby_2__2_:chany_top_out[3] O *L 0 *C 869.400 777.850 +*I sb_2__2_:chany_bottom_in[3] I *L 0 *C 869.400 788.870 + +*CAP +0 cby_2__2_:chany_top_out[3] 0.0004380953 +1 sb_2__2_:chany_bottom_in[3] 0.0004380953 +2 cby_2__2_:chany_top_out[3] cby_2__2_:chany_top_out[7] 0.000146484 +3 sb_2__2_:chany_bottom_in[3] sb_2__2_:chany_bottom_in[7] 0.000146484 + +*RES +0 cby_2__2_:chany_top_out[3] sb_2__2_:chany_bottom_in[3] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[12] 0.001264694 //LENGTH 11.020 LUMPCC 0.0005612715 DR + +*CONN +*I cby_2__2_:chany_top_out[12] O *L 0 *C 860.660 777.850 +*I sb_2__2_:chany_bottom_in[12] I *L 0 *C 860.660 788.870 + +*CAP +0 cby_2__2_:chany_top_out[12] 0.0003517115 +1 sb_2__2_:chany_bottom_in[12] 0.0003517115 +2 cby_2__2_:chany_top_out[12] cby_2__2_:chany_top_out[19] 0.0001422469 +3 sb_2__2_:chany_bottom_in[12] sb_2__2_:chany_bottom_in[19] 0.0001422469 +4 cby_2__2_:chany_top_out[12] cby_2__2_:chany_top_in[12] 0.0001383889 +5 sb_2__2_:chany_bottom_in[12] sb_2__2_:chany_bottom_out[12] 0.0001383889 + +*RES +0 cby_2__2_:chany_top_out[12] sb_2__2_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_10_[0] 0.001223386 //LENGTH 7.660 LUMPCC 0.0007070043 DR + +*CONN +*I cby_2__2_:left_grid_pin_10_[0] O *L 0 *C 809.750 748.000 +*I grid_clb_2__2_:right_width_0_height_0__pin_10_[0] I *L 0 *C 802.090 748.000 + +*CAP +0 cby_2__2_:left_grid_pin_10_[0] 0.000258191 +1 grid_clb_2__2_:right_width_0_height_0__pin_10_[0] 0.000258191 +2 cby_2__2_:left_grid_pin_10_[0] cby_2__2_:left_grid_pin_11_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_10_[0] grid_clb_2__2_:right_width_0_height_0__pin_11_[0] 0.0001767511 +4 cby_2__2_:left_grid_pin_10_[0] cby_2__2_:left_grid_pin_6_[0] 0.0001767511 +5 grid_clb_2__2_:right_width_0_height_0__pin_10_[0] grid_clb_2__2_:right_width_0_height_0__pin_6_[0] 0.0001767511 + +*RES +0 cby_2__2_:left_grid_pin_10_[0] grid_clb_2__2_:right_width_0_height_0__pin_10_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_5_[0] 0.00110824 //LENGTH 7.660 LUMPCC 0.000356805 DR + +*CONN +*I cby_2__2_:left_grid_pin_5_[0] O *L 0 *C 809.750 772.480 +*I grid_clb_2__2_:right_width_0_height_0__pin_5_[0] I *L 0 *C 802.090 772.480 + +*CAP +0 cby_2__2_:left_grid_pin_5_[0] 0.0003757176 +1 grid_clb_2__2_:right_width_0_height_0__pin_5_[0] 0.0003757176 +2 cby_2__2_:left_grid_pin_5_[0] cby_2__2_:left_grid_pin_0_[0] 0.0001784025 +3 grid_clb_2__2_:right_width_0_height_0__pin_5_[0] grid_clb_2__2_:right_width_0_height_0__pin_0_[0] 0.0001784025 + +*RES +0 cby_2__2_:left_grid_pin_5_[0] grid_clb_2__2_:right_width_0_height_0__pin_5_[0] 0.001200067 + +*END + +*D_NET direct_interc_0_out[0] 0.009682275 //LENGTH 98.030 LUMPCC 0.001212551 DR + +*CONN +*I direct_interc_0_\/FTB_1__0:X O *L 0 *C 516.815 639.880 +*I grid_clb_1__1_:top_width_0_height_0__pin_32_[0] I *L 0 *C 515.200 543.930 +*N direct_interc_0_out[0]:2 *C 515.200 593.930 +*N direct_interc_0_out[0]:3 *C 515.200 639.835 +*N direct_interc_0_out[0]:4 *C 515.245 639.880 +*N direct_interc_0_out[0]:5 *C 516.778 639.880 + +*CAP +0 direct_interc_0_\/FTB_1__0:X 1e-06 +1 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 0.002058384 +2 direct_interc_0_out[0]:2 0.004114287 +3 direct_interc_0_out[0]:3 0.002055902 +4 direct_interc_0_out[0]:4 0.0001200756 +5 direct_interc_0_out[0]:5 0.0001200756 +6 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] cbx_1__1__0_chanx_right_out[17]:3 2.053743e-05 +7 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] cbx_1__1__0_chanx_right_out[17]:4 2.098518e-05 +8 direct_interc_0_out[0]:2 cbx_1__1__0_chanx_right_out[17]:2 2.053743e-05 +9 direct_interc_0_out[0]:2 cbx_1__1__0_chanx_right_out[17]:5 2.098518e-05 +10 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] grid_clb_1__1_:top_width_0_height_0__pin_33_[0] 0.0002789327 +11 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] direct_interc_3_out[0]:5 6.25747e-05 +12 direct_interc_0_out[0]:3 direct_interc_3_out[0]:7 6.521259e-05 +13 direct_interc_0_out[0]:3 direct_interc_3_out[0]:6 5.367279e-05 +14 direct_interc_0_out[0]:2 direct_interc_3_out[0]:5 5.367279e-05 +15 direct_interc_0_out[0]:2 direct_interc_3_out[0]:2 0.0002789327 +16 direct_interc_0_out[0]:2 direct_interc_3_out[0]:6 0.0001277873 +17 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] sb_1__1__0_chanx_left_out[15]:5 0.0001043604 +18 direct_interc_0_out[0]:2 sb_1__1__0_chanx_left_out[15]:6 0.0001043604 + +*RES +0 direct_interc_0_\/FTB_1__0:X direct_interc_0_out[0]:5 0.152 +1 direct_interc_0_out[0]:5 direct_interc_0_out[0]:4 0.001368304 +2 direct_interc_0_out[0]:4 direct_interc_0_out[0]:3 0.0045 +3 direct_interc_0_out[0]:3 direct_interc_0_out[0]:2 0.04098661 +4 direct_interc_0_out[0]:2 grid_clb_1__1_:top_width_0_height_0__pin_32_[0] 0.04464286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_44_upper[0] 0.001147271 //LENGTH 11.020 LUMPCC 0.0002974061 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_44_upper[0] O *L 0 *C 397.900 380.870 +*I sb_0__0_:right_top_grid_pin_44_[0] I *L 0 *C 397.900 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_44_upper[0] 0.0004249323 +1 sb_0__0_:right_top_grid_pin_44_[0] 0.0004249323 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_44_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] 0.0001487031 +3 sb_0__0_:right_top_grid_pin_44_[0] sb_0__0_:right_top_grid_pin_42_[0] 0.0001487031 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_44_upper[0] sb_0__0_:right_top_grid_pin_44_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_46_upper[0] 0.001889886 //LENGTH 10.220 LUMPCC 0.0006563768 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_46_upper[0] O *L 0 *C 379.190 385.560 +*I sb_0__0_:right_top_grid_pin_46_[0] I *L 0 *C 371.530 385.560 +*N grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 *C 372.600 385.560 +*N grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 *C 372.600 384.880 +*N grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 *C 377.660 384.880 +*N grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 *C 377.660 385.560 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_46_upper[0] 0.0001802542 +1 sb_0__0_:right_top_grid_pin_46_[0] 0.000137643 +2 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 0.0001806219 +3 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 0.0002385189 +4 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 0.0002558783 +5 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 0.0002405924 +6 grid_clb_1__1_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] 1.254446e-05 +7 sb_0__0_:right_top_grid_pin_46_[0] sb_0__0_:right_top_grid_pin_47_[0] 4.183733e-06 +8 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] 4.183733e-06 +9 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 sb_0__0_:right_top_grid_pin_47_[0] 0.0003114602 +10 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] 0.0003114602 +11 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 sb_0__0_:right_top_grid_pin_47_[0] 1.254446e-05 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 0.0002397 +1 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 sb_0__0_:right_top_grid_pin_46_[0] 0.0001676333 +2 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 0.0001065333 +3 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 0.0007927333 +4 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 0.0001065333 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_36_lower[0] 0.001257188 //LENGTH 7.660 LUMPCC 0.0001686342 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_36_lower[0] O *L 0 *C 540.810 393.720 +*I sb_1__0_:top_left_grid_pin_36_[0] I *L 0 *C 548.470 393.720 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_36_lower[0] 0.000544277 +1 sb_1__0_:top_left_grid_pin_36_[0] 0.000544277 +2 grid_clb_1__1_:right_width_0_height_0__pin_36_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] 8.431709e-05 +3 sb_1__0_:top_left_grid_pin_36_[0] sb_1__0_:top_left_grid_pin_38_[0] 8.431709e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_36_lower[0] sb_1__0_:top_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_41_lower[0] 0.002143985 //LENGTH 11.715 LUMPCC 0.0009905464 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] O *L 0 *C 540.810 384.200 +*I sb_1__0_:top_left_grid_pin_41_[0] I *L 0 *C 548.395 384.200 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 *C 546.500 384.200 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 *C 546.480 384.208 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 *C 546.480 385.553 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 *C 546.460 385.560 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 *C 542.808 385.560 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:7 *C 542.800 385.502 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:8 *C 542.800 384.257 +*N grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 *C 542.793 384.200 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] 0.000161776 +1 sb_1__0_:top_left_grid_pin_41_[0] 0.0001635646 +2 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 0.0001635646 +3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 6.042942e-05 +4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 6.042942e-05 +5 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 9.883709e-05 +6 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 9.883709e-05 +7 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:7 9.211199e-05 +8 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:8 9.211199e-05 +9 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 0.000161776 +10 grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_43_lower[0] 2.15815e-06 +11 grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 9.741985e-05 +12 sb_1__0_:top_left_grid_pin_41_[0] sb_1__0_:left_top_grid_pin_43_[0] 2.092879e-06 +13 sb_1__0_:top_left_grid_pin_41_[0] grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 9.880071e-05 +14 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 9.741985e-05 +15 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 2.15815e-06 +16 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 0.0002279304 +17 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 0.0002279304 +18 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 1.366383e-05 +19 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 1.693953e-05 +20 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 2.092879e-06 +21 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 9.880071e-05 +22 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 1.366383e-05 +23 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 1.693953e-05 +24 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] 3.626794e-05 +25 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 sb_1__0_:top_left_grid_pin_40_[0] 3.626794e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_41_lower[0] grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 0.0003105917 +1 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:8 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:7 0.001111607 +2 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:9 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:8 0.00341 +3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:7 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 0.00341 +4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 0.000572225 +5 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 0.00341 +6 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:4 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 0.0002107167 +7 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 sb_1__0_:top_left_grid_pin_41_[0] 0.0002968833 +8 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_41_lower[0]:2 0.00341 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_48_upper[0] 0.001145813 //LENGTH 11.020 LUMPCC 0.0002954312 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_48_upper[0] O *L 0 *C 394.220 641.990 +*I sb_0__1_:right_top_grid_pin_48_[0] I *L 0 *C 394.220 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_48_upper[0] 0.0004251911 +1 sb_0__1_:right_top_grid_pin_48_[0] 0.0004251911 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_48_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0001477156 +3 sb_0__1_:right_top_grid_pin_48_[0] sb_0__1_:right_top_grid_pin_49_[0] 0.0001477156 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_48_upper[0] sb_0__1_:right_top_grid_pin_48_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_35_upper[0] 0.001533326 //LENGTH 7.660 LUMPCC 0.0003142457 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] O *L 0 *C 540.810 796.960 +*I sb_1__2_:bottom_left_grid_pin_35_[0] I *L 0 *C 548.470 796.960 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] 0.0006095399 +1 sb_1__2_:bottom_left_grid_pin_35_[0] 0.0006095399 +2 grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_34_upper[0] 5.850615e-05 +3 sb_1__2_:bottom_left_grid_pin_35_[0] sb_1__2_:bottom_left_grid_pin_34_[0] 5.850615e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] 9.861671e-05 +5 sb_1__2_:bottom_left_grid_pin_35_[0] sb_1__2_:bottom_left_grid_pin_36_[0] 9.861671e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] sb_1__2_:bottom_left_grid_pin_35_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_40_lower[0] 0.001444949 //LENGTH 7.660 LUMPCC 0.0002813578 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] O *L 0 *C 540.810 650.080 +*I sb_1__1_:top_left_grid_pin_40_[0] I *L 0 *C 548.470 650.080 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] 0.0005817956 +1 sb_1__1_:top_left_grid_pin_40_[0] 0.0005817956 +2 grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_43_lower[0] 3.50267e-05 +3 sb_1__1_:top_left_grid_pin_40_[0] sb_1__1_:left_top_grid_pin_43_[0] 3.50267e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] 0.0001056522 +5 sb_1__1_:top_left_grid_pin_40_[0] sb_1__1_:top_left_grid_pin_39_[0] 0.0001056522 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] sb_1__1_:top_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_44_lower[0] 0.001245889 //LENGTH 11.020 LUMPCC 0.0005828909 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] O *L 0 *C 785.220 380.870 +*I sb_2__0_:left_top_grid_pin_44_[0] I *L 0 *C 785.220 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0003314991 +1 sb_2__0_:left_top_grid_pin_44_[0] 0.0003314991 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_45_lower[0] 0.0001457227 +3 sb_2__0_:left_top_grid_pin_44_[0] sb_2__0_:left_top_grid_pin_45_[0] 0.0001457227 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0001457227 +5 sb_2__0_:left_top_grid_pin_44_[0] sb_2__0_:left_top_grid_pin_47_[0] 0.0001457227 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] sb_2__0_:left_top_grid_pin_44_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_ccff_tail[0] 0.0009460438 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_2__1_:ccff_tail[0] O *L 0 *C 802.090 421.600 +*I cby_2__1_:ccff_head[0] I *L 0 *C 809.750 421.600 + +*CAP +0 grid_clb_2__1_:ccff_tail[0] 0.0004730219 +1 cby_2__1_:ccff_head[0] 0.0004730219 + +*RES +0 grid_clb_2__1_:ccff_tail[0] cby_2__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_34_lower[0] 0.002422248 //LENGTH 21.590 LUMPCC 0.0008273496 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] O *L 0 *C 802.090 406.640 +*I sb_2__0_:top_left_grid_pin_34_[0] I *L 0 *C 813.740 397.050 +*N grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 *C 813.740 406.583 +*N grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 *C 813.733 406.640 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] 0.0003772276 +1 sb_2__0_:top_left_grid_pin_34_[0] 0.0004202213 +2 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 0.0004202213 +3 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 0.0003772276 +4 grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] 0.0002570318 +5 sb_2__0_:top_left_grid_pin_34_[0] sb_2__0_:top_left_grid_pin_35_[0] 4.217083e-05 +6 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 4.217083e-05 +7 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 0.0002570318 +8 grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_37_lower[0] 0.0001030099 +9 sb_2__0_:top_left_grid_pin_34_[0] sb_2__0_:top_left_grid_pin_37_[0] 1.146225e-05 +10 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 1.146225e-05 +11 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 0.0001030099 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 0.001823992 +1 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 sb_2__0_:top_left_grid_pin_34_[0] 0.008511161 +2 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 0.00341 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_40_upper[0] 0.001117822 //LENGTH 7.660 LUMPCC 0.0004889948 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] O *L 0 *C 802.090 540.600 +*I sb_2__1_:bottom_left_grid_pin_40_[0] I *L 0 *C 809.750 540.600 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] 0.0003144139 +1 sb_2__1_:bottom_left_grid_pin_40_[0] 0.0003144139 +2 grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] 0.0001767164 +3 sb_2__1_:bottom_left_grid_pin_40_[0] sb_2__1_:bottom_left_grid_pin_39_[0] 0.0001767164 +4 grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 6.778097e-05 +5 sb_2__1_:bottom_left_grid_pin_40_[0] sb_2__1_:bottom_left_grid_pin_41_[0] 6.778097e-05 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] sb_2__1_:bottom_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_45_upper[0] 0.001254037 //LENGTH 11.020 LUMPCC 0.0005577554 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] O *L 0 *C 657.340 641.990 +*I sb_1__1_:right_top_grid_pin_45_[0] I *L 0 *C 657.340 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0003481411 +1 sb_1__1_:right_top_grid_pin_45_[0] 0.0003481411 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0001394388 +3 sb_1__1_:right_top_grid_pin_45_[0] sb_1__1_:right_top_grid_pin_42_[0] 0.0001394388 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0001394388 +5 sb_1__1_:right_top_grid_pin_45_[0] sb_1__1_:right_top_grid_pin_49_[0] 0.0001394388 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] sb_1__1_:right_top_grid_pin_45_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_34_lower[0] 0.002525788 //LENGTH 21.590 LUMPCC 0.0006653449 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] O *L 0 *C 802.090 667.760 +*I sb_2__1_:top_left_grid_pin_34_[0] I *L 0 *C 813.740 658.170 +*N grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 *C 813.740 667.519 +*N grid_clb_3_right_width_0_height_0__pin_34_lower[0]:3 *C 813.740 667.520 +*N grid_clb_3_right_width_0_height_0__pin_34_lower[0]:4 *C 813.740 667.702 +*N grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 *C 813.733 667.760 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] 0.0005060465 +1 sb_2__1_:top_left_grid_pin_34_[0] 0.0003955176 +2 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 0.0003955176 +3 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:3 2.865734e-05 +4 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:4 2.865734e-05 +5 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 0.0005060465 +6 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_35_lower[0] 0.0001040524 +7 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 4.562606e-05 +8 sb_2__1_:top_left_grid_pin_34_[0] sb_2__1_:top_left_grid_pin_35_[0] 2.707244e-05 +9 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 4.562606e-05 +10 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 0.0001040524 +11 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 2.707244e-05 +12 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_37_lower[0] 0.0001409002 +13 sb_2__1_:top_left_grid_pin_34_[0] sb_2__1_:top_left_grid_pin_37_[0] 1.502129e-05 +14 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 0.0001409002 +15 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 1.502129e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 0.001823992 +1 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:4 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:3 0.0001629464 +2 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:4 0.00341 +3 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 1e-05 +4 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 sb_2__1_:top_left_grid_pin_34_[0] 0.008347322 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_41_lower[0] 0.001078389 //LENGTH 7.660 LUMPCC 0.0004189458 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] O *L 0 *C 802.090 645.320 +*I sb_2__1_:top_left_grid_pin_41_[0] I *L 0 *C 809.750 645.320 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] 0.0003297217 +1 sb_2__1_:top_left_grid_pin_41_[0] 0.0003297217 +2 grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] clk[0]:50 2.787808e-05 +3 sb_2__1_:top_left_grid_pin_41_[0] clk[0]:51 2.787808e-05 +4 grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] 0.0001815948 +5 sb_2__1_:top_left_grid_pin_41_[0] sb_2__1_:left_top_grid_pin_43_[0] 0.0001815948 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_41_lower[0] sb_2__1_:top_left_grid_pin_41_[0] 0.001200067 + +*END + +*D_NET grid_io_left_0_right_width_0_height_0__pin_1_lower[0] 0.002515557 //LENGTH 29.200 LUMPCC 8.87487e-05 DR + +*CONN +*I grid_io_left_0__1_:right_width_0_height_0__pin_1_lower[0] O *L 0 *C 271.860 408.070 +*I sb_0__0_:top_left_grid_pin_1_[0] I *L 0 *C 289.340 397.050 +*N grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:2 *C 289.340 403.183 +*N grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 *C 289.333 403.240 +*N grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 *C 271.868 403.240 +*N grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:5 *C 271.860 403.298 + +*CAP +0 grid_io_left_0__1_:right_width_0_height_0__pin_1_lower[0] 0.0002210928 +1 sb_0__0_:top_left_grid_pin_1_[0] 0.0003137148 +2 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:2 0.0003137148 +3 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 0.0006785968 +4 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 0.0006785968 +5 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:5 0.0002210928 +6 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 ctsbuf_net_1625:9 4.437435e-05 +7 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 ctsbuf_net_1625:10 4.437435e-05 + +*RES +0 grid_io_left_0__1_:right_width_0_height_0__pin_1_lower[0] grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:5 0.004261161 +1 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:2 sb_0__0_:top_left_grid_pin_1_[0] 0.005475447 +2 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:5 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 0.002736183 + +*END + +*D_NET grid_io_right_1_ccff_tail[0] 0.003603186 //LENGTH 35.725 LUMPCC 0.0004344869 DR + +*CONN +*I grid_io_right_3__2_:ccff_tail[0] O *L 0 *C 912.640 669.190 +*I sb_2__1_:ccff_head[0] I *L 0 *C 888.720 658.090 +*N grid_io_right_1_ccff_tail[0]:2 *C 888.720 665.033 +*N grid_io_right_1_ccff_tail[0]:3 *C 888.740 665.040 +*N grid_io_right_1_ccff_tail[0]:4 *C 891.519 665.040 +*N grid_io_right_1_ccff_tail[0]:5 *C 891.520 665.040 +*N grid_io_right_1_ccff_tail[0]:6 *C 912.633 665.040 +*N grid_io_right_1_ccff_tail[0]:7 *C 912.640 665.098 +*N grid_io_right_1_ccff_tail[0]:8 *C 912.640 667.519 +*N grid_io_right_1_ccff_tail[0]:9 *C 912.640 667.520 + +*CAP +0 grid_io_right_3__2_:ccff_tail[0] 0.000126545 +1 sb_2__1_:ccff_head[0] 0.0004057226 +2 grid_io_right_1_ccff_tail[0]:2 0.0004057226 +3 grid_io_right_1_ccff_tail[0]:3 0.00012563 +4 grid_io_right_1_ccff_tail[0]:4 0.00012563 +5 grid_io_right_1_ccff_tail[0]:5 0.000798765 +6 grid_io_right_1_ccff_tail[0]:6 0.000798765 +7 grid_io_right_1_ccff_tail[0]:7 0.0001276868 +8 grid_io_right_1_ccff_tail[0]:8 0.0001276868 +9 grid_io_right_1_ccff_tail[0]:9 0.000126545 +10 grid_io_right_1_ccff_tail[0]:3 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:3 2.14717e-05 +11 grid_io_right_1_ccff_tail[0]:6 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:6 0.0001957717 +12 grid_io_right_1_ccff_tail[0]:5 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:5 0.0001957717 +13 grid_io_right_1_ccff_tail[0]:4 grid_io_right_1_left_width_0_height_0__pin_1_lower[0]:4 2.14717e-05 + +*RES +0 grid_io_right_3__2_:ccff_tail[0] grid_io_right_1_ccff_tail[0]:9 0.001491072 +1 grid_io_right_1_ccff_tail[0]:3 grid_io_right_1_ccff_tail[0]:2 0.00341 +2 grid_io_right_1_ccff_tail[0]:2 sb_2__1_:ccff_head[0] 0.001087658 +3 grid_io_right_1_ccff_tail[0]:7 grid_io_right_1_ccff_tail[0]:6 0.00341 +4 grid_io_right_1_ccff_tail[0]:6 grid_io_right_1_ccff_tail[0]:5 0.003307625 +5 grid_io_right_1_ccff_tail[0]:9 grid_io_right_1_ccff_tail[0]:8 1e-05 +6 grid_io_right_1_ccff_tail[0]:8 grid_io_right_1_ccff_tail[0]:7 0.002162054 +7 grid_io_right_1_ccff_tail[0]:5 grid_io_right_1_ccff_tail[0]:4 1e-05 +8 grid_io_right_1_ccff_tail[0]:4 grid_io_right_1_ccff_tail[0]:3 0.0004353767 + +*END + +*D_NET sb_0__0__0_chanx_right_out[2] 0.001186331 //LENGTH 7.660 LUMPCC 0.0004548427 DR + +*CONN +*I sb_0__0_:chanx_right_out[2] O *L 0 *C 400.050 300.560 +*I cbx_1__0_:chanx_left_in[2] I *L 0 *C 407.710 300.560 + +*CAP +0 sb_0__0_:chanx_right_out[2] 0.0003657443 +1 cbx_1__0_:chanx_left_in[2] 0.0003657443 +2 sb_0__0_:chanx_right_out[2] sb_0__0_:chanx_right_in[3] 0.0001693933 +3 cbx_1__0_:chanx_left_in[2] cbx_1__0_:chanx_left_out[3] 0.0001693933 +4 sb_0__0_:chanx_right_out[2] sb_0__0_:chanx_right_in[16] 5.802804e-05 +5 cbx_1__0_:chanx_left_in[2] cbx_1__0_:chanx_left_out[16] 5.802804e-05 + +*RES +0 sb_0__0_:chanx_right_out[2] cbx_1__0_:chanx_left_in[2] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[11] 0.001201011 //LENGTH 7.660 LUMPCC 0.000466599 DR + +*CONN +*I sb_0__0_:chanx_right_out[11] O *L 0 *C 400.050 349.520 +*I cbx_1__0_:chanx_left_in[11] I *L 0 *C 407.710 349.520 + +*CAP +0 sb_0__0_:chanx_right_out[11] 0.0003672062 +1 cbx_1__0_:chanx_left_in[11] 0.0003672062 +2 sb_0__0_:chanx_right_out[11] sb_0__0_:chanx_right_out[5] 0.0001717131 +3 cbx_1__0_:chanx_left_in[11] cbx_1__0_:chanx_left_in[5] 0.0001717131 +4 sb_0__0_:chanx_right_out[11] sb_0__0_:chanx_right_out[19] 6.15864e-05 +5 cbx_1__0_:chanx_left_in[11] cbx_1__0_:chanx_left_in[19] 6.15864e-05 + +*RES +0 sb_0__0_:chanx_right_out[11] cbx_1__0_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[3] 0.00122511 //LENGTH 11.020 LUMPCC 0.0006003014 DR + +*CONN +*I sb_0__0_:chany_top_out[3] O *L 0 *C 336.260 397.050 +*I cby_0__1_:chany_bottom_in[3] I *L 0 *C 336.260 408.070 + +*CAP +0 sb_0__0_:chany_top_out[3] 0.0003124044 +1 cby_0__1_:chany_bottom_in[3] 0.0003124044 +2 sb_0__0_:chany_top_out[3] sb_0__0_:chany_top_in[10] 0.0001519801 +3 cby_0__1_:chany_bottom_in[3] cby_0__1_:chany_bottom_out[10] 0.0001519801 +4 sb_0__0_:chany_top_out[3] sb_0__0_:chany_top_out[16] 0.0001481706 +5 cby_0__1_:chany_bottom_in[3] cby_0__1_:chany_bottom_in[16] 0.0001481706 + +*RES +0 sb_0__0_:chany_top_out[3] cby_0__1_:chany_bottom_in[3] 0.009839285 + +*END + +*D_NET sb_0__0__0_chany_top_out[14] 0.001554753 //LENGTH 11.180 LUMPCC 0.0009631515 DR + +*CONN +*I sb_0__0_:chany_top_out[14] O *L 0 *C 294.400 396.970 +*I cby_0__1_:chany_bottom_in[14] I *L 0 *C 294.400 408.150 + +*CAP +0 sb_0__0_:chany_top_out[14] 0.0002958008 +1 cby_0__1_:chany_bottom_in[14] 0.0002958008 +2 sb_0__0_:chany_top_out[14] sb_0__0_:chany_top_out[6] 0.0002178002 +3 cby_0__1_:chany_bottom_in[14] cby_0__1_:chany_bottom_in[6] 0.0002178002 +4 sb_0__0_:chany_top_out[14] sb_0__0_:chany_top_out[9] 0.0002178002 +5 cby_0__1_:chany_bottom_in[14] cby_0__1_:chany_bottom_in[9] 0.0002178002 +6 sb_0__0_:chany_top_out[14] sb_0__0_:chany_top_out[12] 4.597537e-05 +7 cby_0__1_:chany_bottom_in[14] cby_0__1_:chany_bottom_in[12] 4.597537e-05 + +*RES +0 sb_0__0_:chany_top_out[14] cby_0__1_:chany_bottom_in[14] 0.001751533 + +*END + +*D_NET sb_0__1__0_chanx_right_out[5] 0.001104032 //LENGTH 7.660 LUMPCC 0.0003519249 DR + +*CONN +*I sb_0__1_:chanx_right_out[5] O *L 0 *C 400.050 599.760 +*I cbx_1__1_:chanx_left_in[5] I *L 0 *C 407.710 599.760 + +*CAP +0 sb_0__1_:chanx_right_out[5] 0.0003760536 +1 cbx_1__1_:chanx_left_in[5] 0.0003760536 +2 sb_0__1_:chanx_right_out[5] sb_0__1_:chanx_right_in[7] 7.23773e-05 +3 cbx_1__1_:chanx_left_in[5] cbx_1__1_:chanx_left_out[7] 7.23773e-05 +4 sb_0__1_:chanx_right_out[5] sb_0__1_:chanx_right_out[3] 0.0001035851 +5 cbx_1__1_:chanx_left_in[5] cbx_1__1_:chanx_left_in[3] 0.0001035851 + +*RES +0 sb_0__1_:chanx_right_out[5] cbx_1__1_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[17] 0.001212397 //LENGTH 7.660 LUMPCC 0.000596009 DR + +*CONN +*I sb_0__1_:chanx_right_out[17] O *L 0 *C 400.050 594.320 +*I cbx_1__1_:chanx_left_in[17] I *L 0 *C 407.710 594.320 + +*CAP +0 sb_0__1_:chanx_right_out[17] 0.000308194 +1 cbx_1__1_:chanx_left_in[17] 0.000308194 +2 sb_0__1_:chanx_right_out[17] sb_0__1_:chanx_right_in[18] 7.776741e-05 +3 cbx_1__1_:chanx_left_in[17] cbx_1__1__0_chanx_left_out[18]:2 7.776741e-05 +4 sb_0__1_:chanx_right_out[17] sb_0__1_:chanx_right_out[9] 4.839982e-05 +5 cbx_1__1_:chanx_left_in[17] cbx_1__1_:chanx_left_in[9] 4.839982e-05 +6 sb_0__1_:chanx_right_out[17] sb_0__1_:chanx_right_out[15] 0.0001718373 +7 cbx_1__1_:chanx_left_in[17] cbx_1__1_:chanx_left_in[15] 0.0001718373 + +*RES +0 sb_0__1_:chanx_right_out[17] cbx_1__1_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[11] 0.001293099 //LENGTH 11.020 LUMPCC 0.0005139186 DR + +*CONN +*I sb_0__1_:chany_bottom_out[11] O *L 0 *C 335.340 527.750 +*I cby_0__1_:chany_top_in[11] I *L 0 *C 335.340 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[11] 0.0003895902 +1 cby_0__1_:chany_top_in[11] 0.0003895902 +2 sb_0__1_:chany_bottom_out[11] sb_0__1_:chany_bottom_in[5] 0.0001284796 +3 cby_0__1_:chany_top_in[11] cby_0__1_:chany_top_out[5] 0.0001284796 +4 sb_0__1_:chany_bottom_out[11] sb_0__1_:chany_bottom_out[17] 0.0001284796 +5 cby_0__1_:chany_top_in[11] cby_0__1_:chany_top_in[17] 0.0001284796 + +*RES +0 sb_0__1_:chany_bottom_out[11] cby_0__1_:chany_top_in[11] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_top_out[2] 0.001259585 //LENGTH 11.020 LUMPCC 0.0005594805 DR + +*CONN +*I sb_0__1_:chany_top_out[2] O *L 0 *C 358.340 658.170 +*I cby_0__2_:chany_bottom_in[2] I *L 0 *C 358.340 669.190 +*N sb_0__1__0_chany_top_out[2]:2 *C 358.340 667.520 +*N sb_0__1__0_chany_top_out[2]:3 *C 358.340 667.519 + +*CAP +0 sb_0__1_:chany_top_out[2] 0.0002387115 +1 cby_0__2_:chany_bottom_in[2] 0.0001113406 +2 sb_0__1__0_chany_top_out[2]:2 0.0001113406 +3 sb_0__1__0_chany_top_out[2]:3 0.0002387115 +4 sb_0__1_:chany_top_out[2] sb_0__1_:chany_top_in[2] 0.0001326356 +5 cby_0__2_:chany_bottom_in[2] cby_0__2_:chany_bottom_out[2] 7.234533e-06 +6 sb_0__1__0_chany_top_out[2]:2 cby_0__1__1_chany_bottom_out[2]:3 7.234533e-06 +7 sb_0__1__0_chany_top_out[2]:3 cby_0__1__1_chany_bottom_out[2]:2 0.0001326356 +8 sb_0__1_:chany_top_out[2] sb_0__1_:chany_top_in[12] 0.0001326356 +9 cby_0__2_:chany_bottom_in[2] cby_0__2_:chany_bottom_out[12] 7.234533e-06 +10 sb_0__1__0_chany_top_out[2]:2 cby_0__1__1_chany_bottom_out[12]:3 7.234533e-06 +11 sb_0__1__0_chany_top_out[2]:3 cby_0__1__1_chany_bottom_out[12]:2 0.0001326356 + +*RES +0 sb_0__1_:chany_top_out[2] sb_0__1__0_chany_top_out[2]:3 0.008347321 +1 sb_0__1__0_chany_top_out[2]:2 cby_0__2_:chany_bottom_in[2] 0.001491072 +2 sb_0__1__0_chany_top_out[2]:3 sb_0__1__0_chany_top_out[2]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[15] 0.001695722 //LENGTH 11.180 LUMPCC 0.0008699538 DR + +*CONN +*I sb_0__1_:chany_top_out[15] O *L 0 *C 333.040 658.090 +*I cby_0__2_:chany_bottom_in[15] I *L 0 *C 333.040 669.270 +*N sb_0__1__0_chany_top_out[15]:2 *C 333.040 667.520 +*N sb_0__1__0_chany_top_out[15]:3 *C 333.040 667.519 + +*CAP +0 sb_0__1_:chany_top_out[15] 0.0001942748 +1 cby_0__2_:chany_bottom_in[15] 0.0002186091 +2 sb_0__1__0_chany_top_out[15]:2 0.0002186091 +3 sb_0__1__0_chany_top_out[15]:3 0.0001942748 +4 sb_0__1_:chany_top_out[15] sb_0__1_:chany_top_in[18] 0.0002104074 +5 cby_0__2_:chany_bottom_in[15] cby_0__2_:chany_bottom_out[18] 8.99572e-06 +6 sb_0__1__0_chany_top_out[15]:2 cby_0__1__1_chany_bottom_out[18]:3 8.99572e-06 +7 sb_0__1__0_chany_top_out[15]:3 cby_0__1__1_chany_bottom_out[18]:2 0.0002104074 +8 sb_0__1_:chany_top_out[15] sb_0__1_:chany_top_out[18] 0.0002065323 +9 cby_0__2_:chany_bottom_in[15] cby_0__2_:chany_bottom_in[18] 9.041499e-06 +10 sb_0__1__0_chany_top_out[15]:2 sb_0__1__0_chany_top_out[18]:2 9.041499e-06 +11 sb_0__1__0_chany_top_out[15]:3 sb_0__1__0_chany_top_out[18]:3 0.0002065323 + +*RES +0 sb_0__1_:chany_top_out[15] sb_0__1__0_chany_top_out[15]:3 0.00147721 +1 sb_0__1__0_chany_top_out[15]:2 cby_0__2_:chany_bottom_in[15] 0.0002741666 +2 sb_0__1__0_chany_top_out[15]:3 sb_0__1__0_chany_top_out[15]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[5] 0.001306176 //LENGTH 7.660 LUMPCC 0.0006412598 DR + +*CONN +*I sb_0__2_:chanx_right_out[5] O *L 0 *C 400.050 884.000 +*I cbx_1__2_:chanx_left_in[5] I *L 0 *C 407.710 884.000 + +*CAP +0 sb_0__2_:chanx_right_out[5] 0.0003324579 +1 cbx_1__2_:chanx_left_in[5] 0.0003324579 +2 sb_0__2_:chanx_right_out[5] sb_0__2_:chanx_right_in[3] 0.0001604258 +3 cbx_1__2_:chanx_left_in[5] cbx_1__2_:chanx_left_out[3] 0.0001604258 +4 sb_0__2_:chanx_right_out[5] sb_0__2_:chanx_right_out[7] 0.0001602041 +5 cbx_1__2_:chanx_left_in[5] cbx_1__2_:chanx_left_in[7] 0.0001602041 + +*RES +0 sb_0__2_:chanx_right_out[5] cbx_1__2_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[16] 0.001231196 //LENGTH 7.660 LUMPCC 0.0004661309 DR + +*CONN +*I sb_0__2_:chanx_right_out[16] O *L 0 *C 400.050 852.720 +*I cbx_1__2_:chanx_left_in[16] I *L 0 *C 407.710 852.720 + +*CAP +0 sb_0__2_:chanx_right_out[16] 0.0003825327 +1 cbx_1__2_:chanx_left_in[16] 0.0003825327 +2 sb_0__2_:chanx_right_out[16] sb_0__2_:chanx_right_in[5] 0.0001644766 +3 cbx_1__2_:chanx_left_in[16] cbx_1__2_:chanx_left_out[5] 0.0001644766 +4 sb_0__2_:chanx_right_out[16] sb_0__2_:chanx_right_out[13] 6.858881e-05 +5 cbx_1__2_:chanx_left_in[16] cbx_1__2_:chanx_left_in[13] 6.858881e-05 + +*RES +0 sb_0__2_:chanx_right_out[16] cbx_1__2_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[5] 0.001268302 //LENGTH 11.020 LUMPCC 0.000553927 DR + +*CONN +*I sb_0__2_:chany_bottom_out[5] O *L 0 *C 332.580 788.870 +*I cby_0__2_:chany_top_in[5] I *L 0 *C 332.580 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[5] 0.0003571876 +1 cby_0__2_:chany_top_in[5] 0.0003571876 +2 sb_0__2_:chany_bottom_out[5] sb_0__2_:chany_bottom_in[15] 0.0001384818 +3 cby_0__2_:chany_top_in[5] cby_0__2_:chany_top_out[15] 0.0001384818 +4 sb_0__2_:chany_bottom_out[5] sb_0__2_:chany_bottom_out[3] 0.0001384818 +5 cby_0__2_:chany_top_in[5] cby_0__2_:chany_top_in[3] 0.0001384818 + +*RES +0 sb_0__2_:chany_bottom_out[5] cby_0__2_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[17] 0.001268302 //LENGTH 11.020 LUMPCC 0.000553927 DR + +*CONN +*I sb_0__2_:chany_bottom_out[17] O *L 0 *C 334.420 788.870 +*I cby_0__2_:chany_top_in[17] I *L 0 *C 334.420 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[17] 0.0003571876 +1 cby_0__2_:chany_top_in[17] 0.0003571876 +2 sb_0__2_:chany_bottom_out[17] sb_0__2_:chany_bottom_in[15] 0.0001384818 +3 cby_0__2_:chany_top_in[17] cby_0__2_:chany_top_out[15] 0.0001384818 +4 sb_0__2_:chany_bottom_out[17] sb_0__2_:chany_bottom_out[11] 0.0001384818 +5 cby_0__2_:chany_top_in[17] cby_0__2_:chany_top_in[11] 0.0001384818 + +*RES +0 sb_0__2_:chany_bottom_out[17] cby_0__2_:chany_top_in[17] 0.009839286 + +*END + +*D_NET sb_1__0__0_chanx_left_out[7] 0.001308472 //LENGTH 7.660 LUMPCC 0.0006506412 DR + +*CONN +*I sb_1__0_:chanx_left_out[7] O *L 0 *C 519.950 342.720 +*I cbx_1__0_:chanx_right_in[7] I *L 0 *C 512.290 342.720 + +*CAP +0 sb_1__0_:chanx_left_out[7] 0.0003289156 +1 cbx_1__0_:chanx_right_in[7] 0.0003289156 +2 sb_1__0_:chanx_left_out[7] sb_1__0_:chanx_left_in[5] 0.0001626603 +3 cbx_1__0_:chanx_right_in[7] cbx_1__0_:chanx_right_out[5] 0.0001626603 +4 sb_1__0_:chanx_left_out[7] sb_1__0_:chanx_left_in[6] 0.0001626603 +5 cbx_1__0_:chanx_right_in[7] cbx_1__0_:chanx_right_out[6] 0.0001626603 + +*RES +0 sb_1__0_:chanx_left_out[7] cbx_1__0_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[17] 0.001318937 //LENGTH 7.660 LUMPCC 0.0006401137 DR + +*CONN +*I sb_1__0_:chanx_left_out[17] O *L 0 *C 519.950 337.280 +*I cbx_1__0_:chanx_right_in[17] I *L 0 *C 512.290 337.280 + +*CAP +0 sb_1__0_:chanx_left_out[17] 0.0003394114 +1 cbx_1__0_:chanx_right_in[17] 0.0003394114 +2 sb_1__0_:chanx_left_out[17] sb_1__0_:chanx_left_in[13] 0.0001599102 +3 cbx_1__0_:chanx_right_in[17] cbx_1__0_:chanx_right_out[13] 0.0001599102 +4 sb_1__0_:chanx_left_out[17] sb_1__0_:chanx_left_in[15] 0.0001601467 +5 cbx_1__0_:chanx_right_in[17] cbx_1__0_:chanx_right_out[15] 0.0001601467 + +*RES +0 sb_1__0_:chanx_left_out[17] cbx_1__0_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[7] 0.001456174 //LENGTH 7.660 LUMPCC 0.0005157623 DR + +*CONN +*I sb_1__0_:chanx_right_out[7] O *L 0 *C 661.330 345.440 +*I cbx_2__0_:chanx_left_in[7] I *L 0 *C 668.990 345.440 +*N sb_1__0__0_chanx_right_out[7]:2 *C 667.520 345.440 +*N sb_1__0__0_chanx_right_out[7]:3 *C 667.519 345.440 + +*CAP +0 sb_1__0_:chanx_right_out[7] 0.0002695675 +1 cbx_2__0_:chanx_left_in[7] 0.0002006385 +2 sb_1__0__0_chanx_right_out[7]:2 0.0002006385 +3 sb_1__0__0_chanx_right_out[7]:3 0.0002695675 +4 sb_1__0_:chanx_right_out[7] sb_1__0_:chanx_right_in[18] 0.0001317392 +5 cbx_2__0_:chanx_left_in[7] cbx_2__0_:chanx_left_out[18] 6.576165e-06 +6 sb_1__0__0_chanx_right_out[7]:2 cbx_1__0__1_chanx_left_out[18]:3 6.576165e-06 +7 sb_1__0__0_chanx_right_out[7]:3 cbx_1__0__1_chanx_left_out[18]:2 0.0001317392 +8 sb_1__0_:chanx_right_out[7] sb_1__0_:chanx_right_out[19] 0.0001195658 +9 sb_1__0__0_chanx_right_out[7]:3 sb_1__0__0_chanx_right_out[19]:3 0.0001195658 + +*RES +0 sb_1__0_:chanx_right_out[7] sb_1__0__0_chanx_right_out[7]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[7]:2 cbx_2__0_:chanx_left_in[7] 0.0002303 +2 sb_1__0__0_chanx_right_out[7]:3 sb_1__0__0_chanx_right_out[7]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[18] 0.001324503 //LENGTH 7.660 LUMPCC 0.0004113951 DR + +*CONN +*I sb_1__0_:chanx_right_out[18] O *L 0 *C 661.330 314.160 +*I cbx_2__0_:chanx_left_in[18] I *L 0 *C 668.990 314.160 +*N sb_1__0__0_chanx_right_out[18]:2 *C 667.520 314.160 +*N sb_1__0__0_chanx_right_out[18]:3 *C 667.519 314.160 + +*CAP +0 sb_1__0_:chanx_right_out[18] 0.0002697763 +1 cbx_2__0_:chanx_left_in[18] 0.0001867774 +2 sb_1__0__0_chanx_right_out[18]:2 0.0001867774 +3 sb_1__0__0_chanx_right_out[18]:3 0.0002697763 +4 sb_1__0_:chanx_right_out[18] sb_1__0_:chanx_right_in[12] 0.0001315576 +5 cbx_2__0_:chanx_left_in[18] cbx_2__0_:chanx_left_out[12] 9.861294e-06 +6 sb_1__0__0_chanx_right_out[18]:2 cbx_1__0__1_chanx_left_out[12]:3 9.861294e-06 +7 sb_1__0__0_chanx_right_out[18]:3 cbx_1__0__1_chanx_left_out[12]:2 0.0001315576 +8 sb_1__0_:chanx_right_out[18] sb_1__0_:chanx_right_out[14] 6.427868e-05 +9 sb_1__0__0_chanx_right_out[18]:3 sb_1__0__0_chanx_right_out[14]:3 6.427868e-05 + +*RES +0 sb_1__0_:chanx_right_out[18] sb_1__0__0_chanx_right_out[18]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[18]:2 cbx_2__0_:chanx_left_in[18] 0.0002303 +2 sb_1__0__0_chanx_right_out[18]:3 sb_1__0__0_chanx_right_out[18]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[8] 0.001231796 //LENGTH 11.020 LUMPCC 0.0005942238 DR + +*CONN +*I sb_1__0_:chany_top_out[8] O *L 0 *C 588.340 397.050 +*I cby_1__1_:chany_bottom_in[8] I *L 0 *C 588.340 408.070 + +*CAP +0 sb_1__0_:chany_top_out[8] 0.0003187861 +1 cby_1__1_:chany_bottom_in[8] 0.0003187861 +2 sb_1__0_:chany_top_out[8] sb_1__0_:chany_top_in[9] 0.000148556 +3 cby_1__1_:chany_bottom_in[8] cby_1__1_:chany_bottom_out[9] 0.000148556 +4 sb_1__0_:chany_top_out[8] sb_1__0_:chany_top_in[16] 0.000148556 +5 cby_1__1_:chany_bottom_in[8] cby_1__1_:chany_bottom_out[16] 0.000148556 + +*RES +0 sb_1__0_:chany_top_out[8] cby_1__1_:chany_bottom_in[8] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[17] 0.001195937 //LENGTH 11.020 LUMPCC 0.0004726439 DR + +*CONN +*I sb_1__0_:chany_top_out[17] O *L 0 *C 581.900 397.050 +*I cby_1__1_:chany_bottom_in[17] I *L 0 *C 581.900 408.070 + +*CAP +0 sb_1__0_:chany_top_out[17] 0.0003616464 +1 cby_1__1_:chany_bottom_in[17] 0.0003616464 +2 sb_1__0_:chany_top_out[17] sb_1__0_:chany_top_in[13] 9.099299e-05 +3 cby_1__1_:chany_bottom_in[17] cby_1__1_:chany_bottom_out[13] 9.099299e-05 +4 sb_1__0_:chany_top_out[17] sb_1__0_:chany_top_out[1] 0.000145329 +5 cby_1__1_:chany_bottom_in[17] cby_1__1_:chany_bottom_in[1] 0.000145329 + +*RES +0 sb_1__0_:chany_top_out[17] cby_1__1_:chany_bottom_in[17] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[7] 0.001268377 //LENGTH 7.660 LUMPCC 0.0004052843 DR + +*CONN +*I sb_1__1_:chanx_left_out[7] O *L 0 *C 519.950 593.640 +*I cbx_1__1_:chanx_right_in[7] I *L 0 *C 512.290 593.640 + +*CAP +0 sb_1__1_:chanx_left_out[7] 0.0004315464 +1 cbx_1__1_:chanx_right_in[7] 0.0004315464 +2 sb_1__1_:chanx_left_out[7] sb_1__1_:chanx_left_in[18] 4.769616e-05 +3 cbx_1__1_:chanx_right_in[7] cbx_1__1__0_chanx_right_out[18]:2 4.769616e-05 +4 sb_1__1_:chanx_left_out[7] sb_1__1_:ccff_tail[0] 0.000154946 +5 cbx_1__1_:chanx_right_in[7] cbx_1__1_:ccff_head[0] 0.000154946 + +*RES +0 sb_1__1_:chanx_left_out[7] cbx_1__1_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[17] 0.001311176 //LENGTH 7.660 LUMPCC 0.0003941694 DR + +*CONN +*I sb_1__1_:chanx_left_out[17] O *L 0 *C 519.950 616.080 +*I cbx_1__1_:chanx_right_in[17] I *L 0 *C 512.290 616.080 + +*CAP +0 sb_1__1_:chanx_left_out[17] 0.0004585034 +1 cbx_1__1_:chanx_right_in[17] 0.0004585034 +2 sb_1__1_:chanx_left_out[17] sb_1__1_:chanx_left_in[5] 0.0001442792 +3 cbx_1__1_:chanx_right_in[17] cbx_1__1_:chanx_right_out[5] 0.0001442792 +4 sb_1__1_:chanx_left_out[17] sb_1__1_:chanx_left_out[19] 5.280546e-05 +5 cbx_1__1_:chanx_right_in[17] cbx_1__1_:chanx_right_in[19] 5.280546e-05 + +*RES +0 sb_1__1_:chanx_left_out[17] cbx_1__1_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[8] 0.0015021 //LENGTH 7.660 LUMPCC 0.0004624854 DR + +*CONN +*I sb_1__1_:chanx_right_out[8] O *L 0 *C 661.330 573.920 +*I cbx_2__1_:chanx_left_in[8] I *L 0 *C 668.990 573.920 +*N sb_1__1__0_chanx_right_out[8]:2 *C 667.520 573.920 +*N sb_1__1__0_chanx_right_out[8]:3 *C 667.519 573.920 + +*CAP +0 sb_1__1_:chanx_right_out[8] 0.0003191688 +1 cbx_2__1_:chanx_left_in[8] 0.0002006385 +2 sb_1__1__0_chanx_right_out[8]:2 0.0002006385 +3 sb_1__1__0_chanx_right_out[8]:3 0.0003191688 +4 sb_1__1_:chanx_right_out[8] sb_1__1_:chanx_right_in[8] 0.0001177465 +5 cbx_2__1_:chanx_left_in[8] cbx_2__1_:chanx_left_out[8] 6.576165e-06 +6 sb_1__1__0_chanx_right_out[8]:2 cbx_1__1__1_chanx_left_out[8]:3 6.576165e-06 +7 sb_1__1__0_chanx_right_out[8]:3 cbx_1__1__1_chanx_left_out[8]:2 0.0001177465 +8 sb_1__1_:chanx_right_out[8] sb_1__1_:chanx_right_out[14] 0.00010692 +9 sb_1__1__0_chanx_right_out[8]:3 sb_1__1__0_chanx_right_out[14]:3 0.00010692 + +*RES +0 sb_1__1_:chanx_right_out[8] sb_1__1__0_chanx_right_out[8]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[8]:2 cbx_2__1_:chanx_left_in[8] 0.0002303 +2 sb_1__1__0_chanx_right_out[8]:3 sb_1__1__0_chanx_right_out[8]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[19] 0.00149718 //LENGTH 7.660 LUMPCC 0.0004902767 DR + +*CONN +*I sb_1__1_:chanx_right_out[19] O *L 0 *C 661.330 617.440 +*I cbx_2__1_:chanx_left_in[19] I *L 0 *C 668.990 617.440 +*N sb_1__1__0_chanx_right_out[19]:2 *C 667.520 617.440 +*N sb_1__1__0_chanx_right_out[19]:3 *C 667.519 617.440 + +*CAP +0 sb_1__1_:chanx_right_out[19] 0.0003084926 +1 cbx_2__1_:chanx_left_in[19] 0.0001949588 +2 sb_1__1__0_chanx_right_out[19]:2 0.0001949588 +3 sb_1__1__0_chanx_right_out[19]:3 0.0003084926 +4 sb_1__1_:chanx_right_out[19] sb_1__1_:ccff_head[0] 0.0001121663 +5 cbx_2__1_:chanx_left_in[19] cbx_2__1_:ccff_tail[0] 1.643549e-06 +6 sb_1__1__0_chanx_right_out[19]:2 cbx_1__1__1_ccff_tail[0]:3 1.643549e-06 +7 sb_1__1__0_chanx_right_out[19]:3 cbx_1__1__1_ccff_tail[0]:2 0.0001121663 +8 sb_1__1_:chanx_right_out[19] sb_1__1_:chanx_right_in[14] 0.0001214672 +9 cbx_2__1_:chanx_left_in[19] cbx_2__1_:chanx_left_out[14] 9.861294e-06 +10 sb_1__1__0_chanx_right_out[19]:2 cbx_1__1__1_chanx_left_out[14]:3 9.861294e-06 +11 sb_1__1__0_chanx_right_out[19]:3 cbx_1__1__1_chanx_left_out[14]:2 0.0001214672 + +*RES +0 sb_1__1_:chanx_right_out[19] sb_1__1__0_chanx_right_out[19]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[19]:2 cbx_2__1_:chanx_left_in[19] 0.0002303 +2 sb_1__1__0_chanx_right_out[19]:3 sb_1__1__0_chanx_right_out[19]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[11] 0.001295469 //LENGTH 11.020 LUMPCC 0.000498686 DR + +*CONN +*I sb_1__1_:chany_bottom_out[11] O *L 0 *C 593.860 527.750 +*I cby_1__1_:chany_top_in[11] I *L 0 *C 593.860 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[11] 0.0003983915 +1 cby_1__1_:chany_top_in[11] 0.0003983915 +2 sb_1__1_:chany_bottom_out[11] sb_1__1_:chany_bottom_out[6] 0.0001246715 +3 cby_1__1_:chany_top_in[11] cby_1__1_:chany_top_in[6] 0.0001246715 +4 sb_1__1_:chany_bottom_out[11] sb_1__1_:chany_bottom_out[18] 0.0001246715 +5 cby_1__1_:chany_top_in[11] cby_1__1_:chany_top_in[18] 0.0001246715 + +*RES +0 sb_1__1_:chany_bottom_out[11] cby_1__1_:chany_top_in[11] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[1] 0.001250553 //LENGTH 11.020 LUMPCC 0.0005737565 DR + +*CONN +*I sb_1__1_:chany_top_out[1] O *L 0 *C 580.980 658.170 +*I cby_1__2_:chany_bottom_in[1] I *L 0 *C 580.980 669.190 +*N sb_1__1__0_chany_top_out[1]:2 *C 580.980 667.520 +*N sb_1__1__0_chany_top_out[1]:3 *C 580.980 667.519 + +*CAP +0 sb_1__1_:chany_top_out[1] 0.0002272564 +1 cby_1__2_:chany_bottom_in[1] 0.0001111417 +2 sb_1__1__0_chany_top_out[1]:2 0.0001111417 +3 sb_1__1__0_chany_top_out[1]:3 0.0002272564 +4 sb_1__1_:chany_top_out[1] sb_1__1_:chany_top_in[5] 0.0001361438 +5 cby_1__2_:chany_bottom_in[1] cby_1__2_:chany_bottom_out[5] 7.295327e-06 +6 sb_1__1__0_chany_top_out[1]:2 cby_1__1__1_chany_bottom_out[5]:3 7.295327e-06 +7 sb_1__1__0_chany_top_out[1]:3 cby_1__1__1_chany_bottom_out[5]:2 0.0001361438 +8 sb_1__1_:chany_top_out[1] sb_1__1_:chany_top_out[17] 0.0001361438 +9 cby_1__2_:chany_bottom_in[1] cby_1__2_:chany_bottom_in[17] 7.295327e-06 +10 sb_1__1__0_chany_top_out[1]:2 sb_1__1__0_chany_top_out[17]:2 7.295327e-06 +11 sb_1__1__0_chany_top_out[1]:3 sb_1__1__0_chany_top_out[17]:3 0.0001361438 + +*RES +0 sb_1__1_:chany_top_out[1] sb_1__1__0_chany_top_out[1]:3 0.008347321 +1 sb_1__1__0_chany_top_out[1]:2 cby_1__2_:chany_bottom_in[1] 0.001491072 +2 sb_1__1__0_chany_top_out[1]:3 sb_1__1__0_chany_top_out[1]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[13] 0.001173198 //LENGTH 11.020 LUMPCC 0.0003968722 DR + +*CONN +*I sb_1__1_:chany_top_out[13] O *L 0 *C 584.200 658.170 +*I cby_1__2_:chany_bottom_in[13] I *L 0 *C 584.200 669.190 +*N sb_1__1__0_chany_top_out[13]:2 *C 584.200 667.520 +*N sb_1__1__0_chany_top_out[13]:3 *C 584.200 667.519 + +*CAP +0 sb_1__1_:chany_top_out[13] 0.0002663785 +1 cby_1__2_:chany_bottom_in[13] 0.0001217842 +2 sb_1__1__0_chany_top_out[13]:2 0.0001217842 +3 sb_1__1__0_chany_top_out[13]:3 0.0002663785 +4 sb_1__1_:chany_top_out[13] sb_1__1_:chany_top_in[7] 5.235202e-05 +5 sb_1__1__0_chany_top_out[13]:3 cby_1__1__1_chany_bottom_out[7]:2 5.235202e-05 +6 sb_1__1_:chany_top_out[13] sb_1__1_:chany_top_in[13] 0.0001387437 +7 cby_1__2_:chany_bottom_in[13] cby_1__2_:chany_bottom_out[13] 7.340376e-06 +8 sb_1__1__0_chany_top_out[13]:2 cby_1__1__1_chany_bottom_out[13]:3 7.340376e-06 +9 sb_1__1__0_chany_top_out[13]:3 cby_1__1__1_chany_bottom_out[13]:2 0.0001387437 + +*RES +0 sb_1__1_:chany_top_out[13] sb_1__1__0_chany_top_out[13]:3 0.008347322 +1 sb_1__1__0_chany_top_out[13]:2 cby_1__2_:chany_bottom_in[13] 0.001491072 +2 sb_1__1__0_chany_top_out[13]:3 sb_1__1__0_chany_top_out[13]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[0] 0.00133334 //LENGTH 7.660 LUMPCC 0.0003788198 DR + +*CONN +*I sb_1__2_:chanx_left_out[0] O *L 0 *C 519.950 869.040 +*I cbx_1__2_:chanx_right_in[0] I *L 0 *C 512.290 869.040 + +*CAP +0 sb_1__2_:chanx_left_out[0] 0.0004772601 +1 cbx_1__2_:chanx_right_in[0] 0.0004772601 +2 sb_1__2_:chanx_left_out[0] sb_1__2_:chanx_left_in[19] 0.0001404799 +3 cbx_1__2_:chanx_right_in[0] cbx_1__2_:chanx_right_out[19] 0.0001404799 +4 sb_1__2_:chanx_left_out[0] sb_1__2_:ccff_tail[0] 4.892996e-05 +5 cbx_1__2_:chanx_right_in[0] cbx_1__2_:ccff_head[0] 4.892996e-05 + +*RES +0 sb_1__2_:chanx_left_out[0] cbx_1__2_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[9] 0.00136724 //LENGTH 7.660 LUMPCC 0.0005954081 DR + +*CONN +*I sb_1__2_:chanx_left_out[9] O *L 0 *C 519.950 854.080 +*I cbx_1__2_:chanx_right_in[9] I *L 0 *C 512.290 854.080 + +*CAP +0 sb_1__2_:chanx_left_out[9] 0.0003859159 +1 cbx_1__2_:chanx_right_in[9] 0.0003859159 +2 sb_1__2_:chanx_left_out[9] sb_1__2_:chanx_left_in[11] 0.000148852 +3 cbx_1__2_:chanx_right_in[9] cbx_1__2_:chanx_right_out[11] 0.000148852 +4 sb_1__2_:chanx_left_out[9] sb_1__2_:chanx_left_out[18] 0.000148852 +5 cbx_1__2_:chanx_right_in[9] cbx_1__2_:chanx_right_in[18] 0.000148852 + +*RES +0 sb_1__2_:chanx_left_out[9] cbx_1__2_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[15] 0.001315406 //LENGTH 7.660 LUMPCC 0.0003716631 DR + +*CONN +*I sb_1__2_:chanx_left_out[15] O *L 0 *C 519.950 833.680 +*I cbx_1__2_:chanx_right_in[15] I *L 0 *C 512.290 833.680 + +*CAP +0 sb_1__2_:chanx_left_out[15] 0.0004718715 +1 cbx_1__2_:chanx_right_in[15] 0.0004718715 +2 sb_1__2_:chanx_left_out[15] sb_1__2_:chanx_left_in[5] 4.500828e-05 +3 cbx_1__2_:chanx_right_in[15] cbx_1__2__0_chanx_right_out[5]:2 4.500828e-05 +4 sb_1__2_:chanx_left_out[15] sb_1__2_:chanx_left_out[6] 0.0001408233 +5 cbx_1__2_:chanx_right_in[15] cbx_1__2_:chanx_right_in[6] 0.0001408233 + +*RES +0 sb_1__2_:chanx_left_out[15] cbx_1__2_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[5] 0.001492597 //LENGTH 7.660 LUMPCC 0.0004976912 DR + +*CONN +*I sb_1__2_:chanx_right_out[5] O *L 0 *C 661.330 884.000 +*I cbx_2__2_:chanx_left_in[5] I *L 0 *C 668.990 884.000 +*N sb_1__2__0_chanx_right_out[5]:2 *C 667.520 884.000 +*N sb_1__2__0_chanx_right_out[5]:3 *C 667.519 884.000 + +*CAP +0 sb_1__2_:chanx_right_out[5] 0.0003024513 +1 cbx_2__2_:chanx_left_in[5] 0.0001950017 +2 sb_1__2__0_chanx_right_out[5]:2 0.0001950017 +3 sb_1__2__0_chanx_right_out[5]:3 0.0003024513 +4 sb_1__2_:chanx_right_out[5] sb_1__2_:chanx_right_in[3] 0.0001231752 +5 cbx_2__2_:chanx_left_in[5] cbx_2__2_:chanx_left_out[3] 9.865685e-06 +6 sb_1__2__0_chanx_right_out[5]:2 cbx_1__2__1_chanx_left_out[3]:3 9.865685e-06 +7 sb_1__2__0_chanx_right_out[5]:3 cbx_1__2__1_chanx_left_out[3]:2 0.0001231752 +8 sb_1__2_:chanx_right_out[5] sb_1__2_:chanx_right_out[7] 0.0001141604 +9 cbx_2__2_:chanx_left_in[5] cbx_2__2_:chanx_left_in[7] 1.644281e-06 +10 sb_1__2__0_chanx_right_out[5]:2 sb_1__2__0_chanx_right_out[7]:2 1.644281e-06 +11 sb_1__2__0_chanx_right_out[5]:3 sb_1__2__0_chanx_right_out[7]:3 0.0001141604 + +*RES +0 sb_1__2_:chanx_right_out[5] sb_1__2__0_chanx_right_out[5]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[5]:2 cbx_2__2_:chanx_left_in[5] 0.0002303 +2 sb_1__2__0_chanx_right_out[5]:3 sb_1__2__0_chanx_right_out[5]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[14] 0.001477282 //LENGTH 7.660 LUMPCC 0.0003206754 DR + +*CONN +*I sb_1__2_:chanx_right_out[14] O *L 0 *C 661.330 879.920 +*I cbx_2__2_:chanx_left_in[14] I *L 0 *C 668.990 879.920 +*N sb_1__2__0_chanx_right_out[14]:2 *C 667.520 879.920 +*N sb_1__2__0_chanx_right_out[14]:3 *C 667.519 879.920 + +*CAP +0 sb_1__2_:chanx_right_out[14] 0.000359038 +1 cbx_2__2_:chanx_left_in[14] 0.0002192653 +2 sb_1__2__0_chanx_right_out[14]:2 0.0002192653 +3 sb_1__2__0_chanx_right_out[14]:3 0.000359038 +4 sb_1__2_:chanx_right_out[14] sb_1__2_:chanx_right_out[7] 5.132505e-05 +5 sb_1__2__0_chanx_right_out[14]:3 sb_1__2__0_chanx_right_out[7]:3 5.132505e-05 +6 sb_1__2_:chanx_right_out[14] sb_1__2_:chanx_right_out[18] 0.0001090126 +7 sb_1__2__0_chanx_right_out[14]:3 sb_1__2__0_chanx_right_out[18]:3 0.0001090126 + +*RES +0 sb_1__2_:chanx_right_out[14] sb_1__2__0_chanx_right_out[14]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[14]:2 cbx_2__2_:chanx_left_in[14] 0.0002303 +2 sb_1__2__0_chanx_right_out[14]:3 sb_1__2__0_chanx_right_out[14]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[3] 0.001272042 //LENGTH 11.020 LUMPCC 0.0005339056 DR + +*CONN +*I sb_1__2_:chany_bottom_out[3] O *L 0 *C 588.800 788.870 +*I cby_1__2_:chany_top_in[3] I *L 0 *C 588.800 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[3] 0.0003690684 +1 cby_1__2_:chany_top_in[3] 0.0003690684 +2 sb_1__2_:chany_bottom_out[3] sb_1__2_:chany_bottom_in[13] 0.0001334764 +3 cby_1__2_:chany_top_in[3] cby_1__2_:chany_top_out[13] 0.0001334764 +4 sb_1__2_:chany_bottom_out[3] sb_1__2_:chany_bottom_in[17] 0.0001334764 +5 cby_1__2_:chany_top_in[3] cby_1__2_:chany_top_out[17] 0.0001334764 + +*RES +0 sb_1__2_:chany_bottom_out[3] cby_1__2_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[9] 0.001265465 //LENGTH 11.020 LUMPCC 0.000532871 DR + +*CONN +*I sb_1__2_:chany_bottom_out[9] O *L 0 *C 574.080 788.870 +*I cby_1__2_:chany_top_in[9] I *L 0 *C 574.080 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[9] 0.000366297 +1 cby_1__2_:chany_top_in[9] 0.000366297 +2 sb_1__2_:chany_bottom_out[9] sb_1__2_:chany_bottom_in[15] 0.0001311006 +3 cby_1__2_:chany_top_in[9] cby_1__2_:chany_top_out[15] 0.0001311006 +4 sb_1__2_:chany_bottom_out[9] sb_1__2_:chany_bottom_out[15] 0.0001353349 +5 cby_1__2_:chany_top_in[9] cby_1__2_:chany_top_in[15] 0.0001353349 + +*RES +0 sb_1__2_:chany_bottom_out[9] cby_1__2_:chany_top_in[9] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[17] 0.001245249 //LENGTH 11.020 LUMPCC 0.0004223853 DR + +*CONN +*I sb_1__2_:chany_bottom_out[17] O *L 0 *C 578.680 788.870 +*I cby_1__2_:chany_top_in[17] I *L 0 *C 578.680 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[17] 0.0004114317 +1 cby_1__2_:chany_top_in[17] 0.0004114317 +2 sb_1__2_:chany_bottom_out[17] sb_1__2_:chany_bottom_in[18] 8.130095e-05 +3 cby_1__2_:chany_top_in[17] cby_1__2_:chany_top_out[18] 8.130095e-05 +4 sb_1__2_:chany_bottom_out[17] sb_1__2_:chany_bottom_out[1] 0.0001298917 +5 cby_1__2_:chany_top_in[17] cby_1__2_:chany_top_in[1] 0.0001298917 + +*RES +0 sb_1__2_:chany_bottom_out[17] cby_1__2_:chany_top_in[17] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[4] 0.001419475 //LENGTH 7.660 LUMPCC 0.0003064462 DR + +*CONN +*I sb_2__0_:chanx_left_out[4] O *L 0 *C 781.230 305.320 +*I cbx_2__0_:chanx_right_in[4] I *L 0 *C 773.570 305.320 + +*CAP +0 sb_2__0_:chanx_left_out[4] 0.0005565144 +1 cbx_2__0_:chanx_right_in[4] 0.0005565144 +2 sb_2__0_:chanx_left_out[4] sb_2__0_:chanx_left_out[2] 3.660679e-05 +3 cbx_2__0_:chanx_right_in[4] cbx_2__0_:chanx_right_in[2] 3.660679e-05 +4 sb_2__0_:chanx_left_out[4] sb_2__0_:chanx_left_out[18] 0.0001166163 +5 cbx_2__0_:chanx_right_in[4] cbx_2__0_:chanx_right_in[18] 0.0001166163 + +*RES +0 sb_2__0_:chanx_left_out[4] cbx_2__0_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[13] 0.001449842 //LENGTH 7.660 LUMPCC 0.000306645 DR + +*CONN +*I sb_2__0_:chanx_left_out[13] O *L 0 *C 781.230 359.720 +*I cbx_2__0_:chanx_right_in[13] I *L 0 *C 773.570 359.720 + +*CAP +0 sb_2__0_:chanx_left_out[13] 0.0005715987 +1 cbx_2__0_:chanx_right_in[13] 0.0005715987 +2 sb_2__0_:chanx_left_out[13] sb_2__0_:chanx_left_in[11] 3.023926e-05 +3 cbx_2__0_:chanx_right_in[13] cbx_2__0_:chanx_right_out[11] 3.023926e-05 +4 sb_2__0_:chanx_left_out[13] sb_2__0_:chanx_left_out[1] 0.0001230833 +5 cbx_2__0_:chanx_right_in[13] cbx_2__0_:chanx_right_in[1] 0.0001230833 + +*RES +0 sb_2__0_:chanx_left_out[13] cbx_2__0_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[3] 0.001231928 //LENGTH 11.020 LUMPCC 0.0005937052 DR + +*CONN +*I sb_2__0_:chany_top_out[3] O *L 0 *C 852.380 397.050 +*I cby_2__1_:chany_bottom_in[3] I *L 0 *C 852.380 408.070 + +*CAP +0 sb_2__0_:chany_top_out[3] 0.0003191112 +1 cby_2__1_:chany_bottom_in[3] 0.0003191112 +2 sb_2__0_:chany_top_out[3] sb_2__0_:chany_top_in[8] 0.0001484263 +3 cby_2__1_:chany_bottom_in[3] cby_2__1_:chany_bottom_out[8] 0.0001484263 +4 sb_2__0_:chany_top_out[3] sb_2__0_:chany_top_out[6] 0.0001484263 +5 cby_2__1_:chany_bottom_in[3] cby_2__1_:chany_bottom_in[6] 0.0001484263 + +*RES +0 sb_2__0_:chany_top_out[3] cby_2__1_:chany_bottom_in[3] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[11] 0.001065134 //LENGTH 11.020 LUMPCC 0.000135296 DR + +*CONN +*I sb_2__0_:chany_top_out[11] O *L 0 *C 874.920 397.050 +*I cby_2__1_:chany_bottom_in[11] I *L 0 *C 874.920 408.070 + +*CAP +0 sb_2__0_:chany_top_out[11] 0.0004649188 +1 cby_2__1_:chany_bottom_in[11] 0.0004649188 +2 sb_2__0_:chany_top_out[11] sb_2__0_:chany_top_out[18] 6.764799e-05 +3 cby_2__1_:chany_bottom_in[11] cby_2__1_:chany_bottom_in[18] 6.764799e-05 + +*RES +0 sb_2__0_:chany_top_out[11] cby_2__1_:chany_bottom_in[11] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[18] 0.001157354 //LENGTH 11.020 LUMPCC 0.000434589 DR + +*CONN +*I sb_2__0_:chany_top_out[18] O *L 0 *C 876.760 397.050 +*I cby_2__1_:chany_bottom_in[18] I *L 0 *C 876.760 408.070 + +*CAP +0 sb_2__0_:chany_top_out[18] 0.0003613826 +1 cby_2__1_:chany_bottom_in[18] 0.0003613826 +2 sb_2__0_:chany_top_out[18] sb_2__0_:chany_top_out[10] 0.0001496465 +3 cby_2__1_:chany_bottom_in[18] cby_2__1_:chany_bottom_in[10] 0.0001496465 +4 sb_2__0_:chany_top_out[18] sb_2__0_:chany_top_out[11] 6.764799e-05 +5 cby_2__1_:chany_bottom_in[18] cby_2__1_:chany_bottom_in[11] 6.764799e-05 + +*RES +0 sb_2__0_:chany_top_out[18] cby_2__1_:chany_bottom_in[18] 0.009839286 + +*END + +*D_NET sb_2__1__0_chanx_left_out[7] 0.001402043 //LENGTH 7.660 LUMPCC 0.0002792389 DR + +*CONN +*I sb_2__1_:chanx_left_out[7] O *L 0 *C 781.230 593.640 +*I cbx_2__1_:chanx_right_in[7] I *L 0 *C 773.570 593.640 + +*CAP +0 sb_2__1_:chanx_left_out[7] 0.0005614021 +1 cbx_2__1_:chanx_right_in[7] 0.0005614021 +2 sb_2__1_:chanx_left_out[7] sb_2__1_:ccff_tail[0] 0.0001110417 +3 cbx_2__1_:chanx_right_in[7] cbx_2__1_:ccff_head[0] 0.0001110417 +4 sb_2__1_:chanx_left_out[7] sb_2__1_:chanx_left_out[9] 2.857778e-05 +5 cbx_2__1_:chanx_right_in[7] cbx_2__1_:chanx_right_in[9] 2.857778e-05 + +*RES +0 sb_2__1_:chanx_left_out[7] cbx_2__1_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[18] 0.001531535 //LENGTH 7.660 LUMPCC 0.0004472838 DR + +*CONN +*I sb_2__1_:chanx_left_out[18] O *L 0 *C 781.230 598.400 +*I cbx_2__1_:chanx_right_in[18] I *L 0 *C 773.570 598.400 + +*CAP +0 sb_2__1_:chanx_left_out[18] 0.0005421257 +1 cbx_2__1_:chanx_right_in[18] 0.0005421257 +2 sb_2__1_:chanx_left_out[18] sb_2__1_:chanx_left_in[9] 0.0001203092 +3 cbx_2__1_:chanx_right_in[18] cbx_2__1_:chanx_right_out[9] 0.0001203092 +4 sb_2__1_:chanx_left_out[18] sb_2__1_:chanx_left_out[9] 0.0001033327 +5 cbx_2__1_:chanx_right_in[18] cbx_2__1_:chanx_right_in[9] 0.0001033327 + +*RES +0 sb_2__1_:chanx_left_out[18] cbx_2__1_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[10] 0.001194867 //LENGTH 11.020 LUMPCC 0.0002693979 DR + +*CONN +*I sb_2__1_:chany_bottom_out[10] O *L 0 *C 874.460 527.750 +*I cby_2__1_:chany_top_in[10] I *L 0 *C 874.460 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[10] 0.0004627344 +1 cby_2__1_:chany_top_in[10] 0.0004627344 +2 sb_2__1_:chany_bottom_out[10] sb_2__1_:chany_bottom_in[6] 0.0001346989 +3 cby_2__1_:chany_top_in[10] cby_2__1_:chany_top_out[6] 0.0001346989 + +*RES +0 sb_2__1_:chany_bottom_out[10] cby_2__1_:chany_top_in[10] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[18] 0.001249778 //LENGTH 11.020 LUMPCC 0.0004193347 DR + +*CONN +*I sb_2__1_:chany_bottom_out[18] O *L 0 *C 854.220 527.750 +*I cby_2__1_:chany_top_in[18] I *L 0 *C 854.220 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[18] 0.0004152216 +1 cby_2__1_:chany_top_in[18] 0.0004152216 +2 sb_2__1_:chany_bottom_out[18] sb_2__1_:chany_bottom_out[5] 7.581322e-05 +3 cby_2__1_:chany_top_in[18] cby_2__1_:chany_top_in[5] 7.581322e-05 +4 sb_2__1_:chany_bottom_out[18] sb_2__1_:chany_bottom_out[11] 0.0001338541 +5 cby_2__1_:chany_top_in[18] cby_2__1_:chany_top_in[11] 0.0001338541 + +*RES +0 sb_2__1_:chany_bottom_out[18] cby_2__1_:chany_top_in[18] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[10] 0.001249368 //LENGTH 11.020 LUMPCC 0.0005607155 DR + +*CONN +*I sb_2__1_:chany_top_out[10] O *L 0 *C 877.680 658.170 +*I cby_2__2_:chany_bottom_in[10] I *L 0 *C 877.680 669.190 +*N sb_2__1__0_chany_top_out[10]:2 *C 877.680 667.520 +*N sb_2__1__0_chany_top_out[10]:3 *C 877.680 667.519 + +*CAP +0 sb_2__1_:chany_top_out[10] 0.0002334566 +1 cby_2__2_:chany_bottom_in[10] 0.0001108697 +2 sb_2__1__0_chany_top_out[10]:2 0.0001108697 +3 sb_2__1__0_chany_top_out[10]:3 0.0002334566 +4 sb_2__1_:chany_top_out[10] sb_2__1_:chany_top_out[14] 0.0001328241 +5 cby_2__2_:chany_bottom_in[10] cby_2__2_:chany_bottom_in[14] 7.354774e-06 +6 sb_2__1__0_chany_top_out[10]:2 sb_2__1__0_chany_top_out[14]:2 7.354774e-06 +7 sb_2__1__0_chany_top_out[10]:3 sb_2__1__0_chany_top_out[14]:3 0.0001328241 +8 sb_2__1_:chany_top_out[10] sb_2__1_:chany_top_out[18] 0.0001328241 +9 cby_2__2_:chany_bottom_in[10] cby_2__2_:chany_bottom_in[18] 7.354774e-06 +10 sb_2__1__0_chany_top_out[10]:2 sb_2__1__0_chany_top_out[18]:2 7.354774e-06 +11 sb_2__1__0_chany_top_out[10]:3 sb_2__1__0_chany_top_out[18]:3 0.0001328241 + +*RES +0 sb_2__1_:chany_top_out[10] sb_2__1__0_chany_top_out[10]:3 0.008347322 +1 sb_2__1__0_chany_top_out[10]:2 cby_2__2_:chany_bottom_in[10] 0.001491072 +2 sb_2__1__0_chany_top_out[10]:3 sb_2__1__0_chany_top_out[10]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[1] 0.001442943 //LENGTH 7.660 LUMPCC 0.0003507276 DR + +*CONN +*I sb_2__2_:chanx_left_out[1] O *L 0 *C 781.230 882.640 +*I cbx_2__2_:chanx_right_in[1] I *L 0 *C 773.570 882.640 + +*CAP +0 sb_2__2_:chanx_left_out[1] 0.0005461077 +1 cbx_2__2_:chanx_right_in[1] 0.0005461077 +2 sb_2__2_:chanx_left_out[1] sb_2__2_:chanx_left_in[15] 5.905084e-05 +3 cbx_2__2_:chanx_right_in[1] cbx_2__2_:chanx_right_out[15] 5.905084e-05 +4 sb_2__2_:chanx_left_out[1] sb_2__2_:chanx_left_out[11] 0.000116313 +5 cbx_2__2_:chanx_right_in[1] cbx_2__2_:chanx_right_in[11] 0.000116313 + +*RES +0 sb_2__2_:chanx_left_out[1] cbx_2__2_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[11] 0.001518139 //LENGTH 7.660 LUMPCC 0.0004652519 DR + +*CONN +*I sb_2__2_:chanx_left_out[11] O *L 0 *C 781.230 881.280 +*I cbx_2__2_:chanx_right_in[11] I *L 0 *C 773.570 881.280 + +*CAP +0 sb_2__2_:chanx_left_out[11] 0.0005264437 +1 cbx_2__2_:chanx_right_in[11] 0.0005264437 +2 sb_2__2_:chanx_left_out[11] sb_2__2_:chanx_left_out[1] 0.000116313 +3 cbx_2__2_:chanx_right_in[11] cbx_2__2_:chanx_right_in[1] 0.000116313 +4 sb_2__2_:chanx_left_out[11] sb_2__2_:chanx_left_out[17] 0.000116313 +5 cbx_2__2_:chanx_right_in[11] cbx_2__2_:chanx_right_in[17] 0.000116313 + +*RES +0 sb_2__2_:chanx_left_out[11] cbx_2__2_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[2] 0.00138936 //LENGTH 12.500 LUMPCC 0.000319917 DR + +*CONN +*I sb_2__2_:chany_bottom_out[2] O *L 0 *C 833.520 788.870 +*I cby_2__2_:chany_top_in[2] I *L 0 *C 833.520 777.850 +*N sb_2__2__0_chany_bottom_out[2]:2 *C 833.520 784.380 +*N sb_2__2__0_chany_bottom_out[2]:3 *C 833.980 784.380 +*N sb_2__2__0_chany_bottom_out[2]:4 *C 833.980 786.760 +*N sb_2__2__0_chany_bottom_out[2]:5 *C 833.520 786.760 + +*CAP +0 sb_2__2_:chany_bottom_out[2] 0.0001025839 +1 cby_2__2_:chany_top_in[2] 0.0003036505 +2 sb_2__2__0_chany_bottom_out[2]:2 0.0003231125 +3 sb_2__2__0_chany_bottom_out[2]:3 0.0001050874 +4 sb_2__2__0_chany_bottom_out[2]:4 0.0001090252 +5 sb_2__2__0_chany_bottom_out[2]:5 0.0001259838 +6 sb_2__2_:chany_bottom_out[2] sb_2__2_:chany_bottom_in[15] 1.638596e-05 +7 cby_2__2_:chany_top_in[2] cby_2__2_:chany_top_out[15] 6.950935e-05 +8 sb_2__2__0_chany_bottom_out[2]:2 sb_2__2_:chany_bottom_in[15] 6.950935e-05 +9 sb_2__2__0_chany_bottom_out[2]:3 cby_2__2_:chany_top_out[15] 7.40632e-05 +10 sb_2__2__0_chany_bottom_out[2]:5 cby_2__2_:chany_top_out[15] 1.638596e-05 +11 sb_2__2__0_chany_bottom_out[2]:4 sb_2__2_:chany_bottom_in[15] 7.40632e-05 + +*RES +0 sb_2__2_:chany_bottom_out[2] sb_2__2__0_chany_bottom_out[2]:5 0.001883929 +1 sb_2__2__0_chany_bottom_out[2]:2 cby_2__2_:chany_top_in[2] 0.005830357 +2 sb_2__2__0_chany_bottom_out[2]:3 sb_2__2__0_chany_bottom_out[2]:2 0.0004107143 +3 sb_2__2__0_chany_bottom_out[2]:5 sb_2__2__0_chany_bottom_out[2]:4 0.0004107143 +4 sb_2__2__0_chany_bottom_out[2]:4 sb_2__2__0_chany_bottom_out[2]:3 0.002125 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[17] 0.001213782 //LENGTH 11.020 LUMPCC 0.0004615249 DR + +*CONN +*I sb_2__2_:chany_bottom_out[17] O *L 0 *C 839.960 788.870 +*I cby_2__2_:chany_top_in[17] I *L 0 *C 839.960 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[17] 0.0003761287 +1 cby_2__2_:chany_top_in[17] 0.0003761287 +2 sb_2__2_:chany_bottom_out[17] sb_2__2_:chany_bottom_in[18] 8.934273e-05 +3 cby_2__2_:chany_top_in[17] cby_2__2_:chany_top_out[18] 8.934273e-05 +4 sb_2__2_:chany_bottom_out[17] sb_2__2_:chany_bottom_out[1] 0.0001414197 +5 cby_2__2_:chany_top_in[17] cby_2__2_:chany_top_in[1] 0.0001414197 + +*RES +0 sb_2__2_:chany_bottom_out[17] cby_2__2_:chany_top_in[17] 0.009839286 + +*END + +*D_NET ctsbuf_net_817 0.04214018 //LENGTH 389.010 LUMPCC 0.001498919 DR + +*CONN +*I cts_inv_73577632:Y O *L 0 *C 630.200 518.160 +*I grid_io_bottom_2__0_:prog_clk[0] I *L 0 *C 773.570 278.120 +*I cbx_2__0_:prog_clk[0] I *L 0 *C 759.460 369.850 +*N ctsbuf_net_817:3 *C 774.633 278.120 +*N ctsbuf_net_817:4 *C 774.640 278.178 +*N ctsbuf_net_817:5 *C 774.640 327.935 +*N ctsbuf_net_817:6 *C 774.640 371.223 +*N ctsbuf_net_817:7 *C 774.633 371.280 +*N ctsbuf_net_817:8 *C 759.468 371.280 +*N ctsbuf_net_817:9 *C 759.460 371.280 +*N ctsbuf_net_817:10 *C 759.460 375.983 +*N ctsbuf_net_817:11 *C 759.452 376.040 +*N ctsbuf_net_817:12 *C 733.715 376.040 +*N ctsbuf_net_817:13 *C 683.715 376.040 +*N ctsbuf_net_817:14 *C 667.520 376.040 +*N ctsbuf_net_817:15 *C 667.519 376.040 +*N ctsbuf_net_817:16 *C 633.888 376.040 +*N ctsbuf_net_817:17 *C 633.880 376.098 +*N ctsbuf_net_817:18 *C 633.880 425.855 +*N ctsbuf_net_817:19 *C 633.880 443.519 +*N ctsbuf_net_817:20 *C 633.880 443.520 +*N ctsbuf_net_817:21 *C 633.880 475.855 +*N ctsbuf_net_817:22 *C 633.880 518.115 +*N ctsbuf_net_817:23 *C 633.835 518.160 +*N ctsbuf_net_817:24 *C 630.238 518.160 + +*CAP +0 cts_inv_73577632:Y 1e-06 +1 grid_io_bottom_2__0_:prog_clk[0] 0.0001870335 +2 cbx_2__0_:prog_clk[0] 9.749883e-05 +3 ctsbuf_net_817:3 0.0001870335 +4 ctsbuf_net_817:4 0.002770717 +5 ctsbuf_net_817:5 0.005162093 +6 ctsbuf_net_817:6 0.002391377 +7 ctsbuf_net_817:7 0.00109727 +8 ctsbuf_net_817:8 0.00109727 +9 ctsbuf_net_817:9 0.0003880271 +10 ctsbuf_net_817:10 0.0002498274 +11 ctsbuf_net_817:11 0.001268057 +12 ctsbuf_net_817:12 0.003716129 +13 ctsbuf_net_817:13 0.003276267 +14 ctsbuf_net_817:14 0.0008281951 +15 ctsbuf_net_817:15 0.001671235 +16 ctsbuf_net_817:16 0.001671235 +17 ctsbuf_net_817:17 0.002462176 +18 ctsbuf_net_817:18 0.003346432 +19 ctsbuf_net_817:19 0.0008842559 +20 ctsbuf_net_817:20 0.001600179 +21 ctsbuf_net_817:21 0.003725033 +22 ctsbuf_net_817:22 0.002124854 +23 ctsbuf_net_817:23 0.000219031 +24 ctsbuf_net_817:24 0.000219031 +25 ctsbuf_net_817:8 cbx_1__0__1_chanx_right_out[2]:6 0.0002998422 +26 ctsbuf_net_817:7 cbx_1__0__1_chanx_right_out[2]:5 0.0002998422 +27 ctsbuf_net_817:6 cbx_1__0__1_chanx_right_out[4]:4 0.0001523151 +28 ctsbuf_net_817:5 cbx_1__0__1_chanx_right_out[4]:3 0.0001523151 +29 ctsbuf_net_817:17 direct_interc_2_out[0]:31 4.530455e-05 +30 ctsbuf_net_817:22 direct_interc_2_out[0]:26 2.641074e-05 +31 ctsbuf_net_817:22 direct_interc_2_out[0]:27 7.199373e-05 +32 ctsbuf_net_817:18 direct_interc_2_out[0]:30 4.530455e-05 +33 ctsbuf_net_817:18 direct_interc_2_out[0]:31 3.817279e-05 +34 ctsbuf_net_817:21 direct_interc_2_out[0]:27 8.30296e-05 +35 ctsbuf_net_817:21 direct_interc_2_out[0]:28 9.504078e-05 +36 ctsbuf_net_817:20 direct_interc_2_out[0]:28 5.661887e-05 +37 ctsbuf_net_817:20 direct_interc_2_out[0]:29 2.304706e-05 +38 ctsbuf_net_817:19 direct_interc_2_out[0]:30 3.817279e-05 +39 ctsbuf_net_817:17 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 3.575435e-05 +40 ctsbuf_net_817:18 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 3.575435e-05 + +*RES +0 cts_inv_73577632:Y ctsbuf_net_817:24 0.152 +1 ctsbuf_net_817:10 ctsbuf_net_817:9 0.004198661 +2 ctsbuf_net_817:11 ctsbuf_net_817:10 0.00341 +3 ctsbuf_net_817:17 ctsbuf_net_817:16 0.00341 +4 ctsbuf_net_817:16 ctsbuf_net_817:15 0.005268935 +5 ctsbuf_net_817:23 ctsbuf_net_817:22 0.0045 +6 ctsbuf_net_817:22 ctsbuf_net_817:21 0.03773215 +7 ctsbuf_net_817:24 ctsbuf_net_817:23 0.003212054 +8 ctsbuf_net_817:9 ctsbuf_net_817:8 0.00341 +9 ctsbuf_net_817:9 cbx_2__0_:prog_clk[0] 0.001276786 +10 ctsbuf_net_817:8 ctsbuf_net_817:7 0.00237585 +11 ctsbuf_net_817:6 ctsbuf_net_817:5 0.03864956 +12 ctsbuf_net_817:7 ctsbuf_net_817:6 0.00341 +13 ctsbuf_net_817:4 ctsbuf_net_817:3 0.00341 +14 ctsbuf_net_817:3 grid_io_bottom_2__0_:prog_clk[0] 0.0001664583 +15 ctsbuf_net_817:18 ctsbuf_net_817:17 0.04442634 +16 ctsbuf_net_817:21 ctsbuf_net_817:20 0.02887054 +17 ctsbuf_net_817:5 ctsbuf_net_817:4 0.04442634 +18 ctsbuf_net_817:13 ctsbuf_net_817:12 0.007833333 +19 ctsbuf_net_817:12 ctsbuf_net_817:11 0.004032208 +20 ctsbuf_net_817:20 ctsbuf_net_817:19 1e-05 +21 ctsbuf_net_817:19 ctsbuf_net_817:18 0.01577143 +22 ctsbuf_net_817:14 ctsbuf_net_817:13 0.002537217 +23 ctsbuf_net_817:15 ctsbuf_net_817:14 1e-05 + +*END + +*D_NET ropt_net_35 0.0008306094 //LENGTH 7.555 LUMPCC 9.951392e-05 DR + +*CONN +*I ropt_h_inst_7753:X O *L 0 *C 663.555 911.880 +*I ropt_h_inst_7754:A I *L 0.001776 *C 658.720 909.840 +*N ropt_net_35:2 *C 658.758 909.840 +*N ropt_net_35:3 *C 663.275 909.840 +*N ropt_net_35:4 *C 663.320 909.885 +*N ropt_net_35:5 *C 663.320 911.835 +*N ropt_net_35:6 *C 663.320 911.880 +*N ropt_net_35:7 *C 663.555 911.880 + +*CAP +0 ropt_h_inst_7753:X 1e-06 +1 ropt_h_inst_7754:A 1e-06 +2 ropt_net_35:2 0.0002080279 +3 ropt_net_35:3 0.0002080279 +4 ropt_net_35:4 0.0001074707 +5 ropt_net_35:5 0.0001074707 +6 ropt_net_35:6 4.875391e-05 +7 ropt_net_35:7 4.934456e-05 +8 ropt_net_35:2 ropt_net_36:3 4.975696e-05 +9 ropt_net_35:3 ropt_net_36:4 4.975696e-05 + +*RES +0 ropt_h_inst_7753:X ropt_net_35:7 0.152 +1 ropt_net_35:2 ropt_h_inst_7754:A 0.152 +2 ropt_net_35:3 ropt_net_35:2 0.004033482 +3 ropt_net_35:4 ropt_net_35:3 0.0045 +4 ropt_net_35:6 ropt_net_35:5 0.0045 +5 ropt_net_35:5 ropt_net_35:4 0.001741072 +6 ropt_net_35:7 ropt_net_35:6 0.0001277174 + +*END + +*D_NET ropt_net_40 0.01688986 //LENGTH 112.600 LUMPCC 0.001436047 DR + +*CONN +*I ropt_h_inst_7758:X O *L 0 *C 281.060 781.660 +*I grid_clb_1__2_:ccff_head[0] I *L 0 *C 379.190 768.400 +*N ropt_net_40:2 *C 373.528 768.400 +*N ropt_net_40:3 *C 373.520 768.457 +*N ropt_net_40:4 *C 373.520 779.223 +*N ropt_net_40:5 *C 373.513 779.280 +*N ropt_net_40:6 *C 330.895 779.280 +*N ropt_net_40:7 *C 281.067 779.280 +*N ropt_net_40:8 *C 281.060 779.338 +*N ropt_net_40:9 *C 281.060 781.615 +*N ropt_net_40:10 *C 281.060 781.660 + +*CAP +0 ropt_h_inst_7758:X 1e-06 +1 grid_clb_1__2_:ccff_head[0] 0.0004267567 +2 ropt_net_40:2 0.0004267567 +3 ropt_net_40:3 0.0004990698 +4 ropt_net_40:4 0.0004990698 +5 ropt_net_40:5 0.003355109 +6 ropt_net_40:6 0.006627503 +7 ropt_net_40:7 0.003272394 +8 ropt_net_40:8 0.0001552667 +9 ropt_net_40:9 0.0001552667 +10 ropt_net_40:10 3.562545e-05 +11 ropt_net_40:7 ctsbuf_net_1524:8 7.00504e-05 +12 ropt_net_40:7 ctsbuf_net_1524:9 0.000647973 +13 ropt_net_40:6 ctsbuf_net_1524:6 0.000647973 +14 ropt_net_40:6 ctsbuf_net_1524:9 7.00504e-05 + +*RES +0 ropt_h_inst_7758:X ropt_net_40:10 0.152 +1 ropt_net_40:10 ropt_net_40:9 0.0045 +2 ropt_net_40:9 ropt_net_40:8 0.002033482 +3 ropt_net_40:8 ropt_net_40:7 0.00341 +4 ropt_net_40:7 ropt_net_40:6 0.007806308 +5 ropt_net_40:4 ropt_net_40:3 0.009611608 +6 ropt_net_40:5 ropt_net_40:4 0.00341 +7 ropt_net_40:3 ropt_net_40:2 0.00341 +8 ropt_net_40:2 grid_clb_1__2_:ccff_head[0] 0.0008871249 +9 ropt_net_40:6 ropt_net_40:5 0.006676741 + +*END + +*D_NET gfpga_pad_GPIO_A[2] 0.03078057 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__1_:gfpga_pad_GPIO_A[0] O *L 0 *C 925.370 463.080 +*P gfpga_pad_GPIO_A[2] O *L 0 *C 1199.155 463.080 +*N gfpga_pad_GPIO_A[2]:2 *C 1179.960 463.080 +*N gfpga_pad_GPIO_A[2]:3 *C 1129.960 463.080 +*N gfpga_pad_GPIO_A[2]:4 *C 1115.520 463.080 +*N gfpga_pad_GPIO_A[2]:5 *C 1115.519 463.080 +*N gfpga_pad_GPIO_A[2]:6 *C 1079.960 463.080 +*N gfpga_pad_GPIO_A[2]:7 *C 1029.960 463.080 +*N gfpga_pad_GPIO_A[2]:8 *C 979.960 463.080 +*N gfpga_pad_GPIO_A[2]:9 *C 930.165 463.080 +*N gfpga_pad_GPIO_A[2]:10 *C 930.120 463.080 +*N gfpga_pad_GPIO_A[2]:11 *C 930.113 463.080 + +*CAP +0 grid_io_right_3__1_:gfpga_pad_GPIO_A[0] 0.0003640873 +1 gfpga_pad_GPIO_A[2] 0.001076456 +2 gfpga_pad_GPIO_A[2]:2 0.003865472 +3 gfpga_pad_GPIO_A[2]:3 0.003585953 +4 gfpga_pad_GPIO_A[2]:4 0.0007969374 +5 gfpga_pad_GPIO_A[2]:5 0.001975368 +6 gfpga_pad_GPIO_A[2]:6 0.004766157 +7 gfpga_pad_GPIO_A[2]:7 0.005581331 +8 gfpga_pad_GPIO_A[2]:8 0.005581859 +9 gfpga_pad_GPIO_A[2]:9 0.002791317 +10 gfpga_pad_GPIO_A[2]:10 3.154598e-05 +11 gfpga_pad_GPIO_A[2]:11 0.0003640873 + +*RES +0 grid_io_right_3__1_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[2]:11 0.0007429916 +1 gfpga_pad_GPIO_A[2]:10 gfpga_pad_GPIO_A[2]:9 0.0045 +2 gfpga_pad_GPIO_A[2]:11 gfpga_pad_GPIO_A[2]:10 0.00341 +3 gfpga_pad_GPIO_A[2]:9 gfpga_pad_GPIO_A[2]:8 0.04445982 +4 gfpga_pad_GPIO_A[2]:8 gfpga_pad_GPIO_A[2]:7 0.04464286 +5 gfpga_pad_GPIO_A[2]:7 gfpga_pad_GPIO_A[2]:6 0.04464286 +6 gfpga_pad_GPIO_A[2]:6 gfpga_pad_GPIO_A[2]:5 0.03174911 +7 gfpga_pad_GPIO_A[2]:3 gfpga_pad_GPIO_A[2]:2 0.04464286 +8 gfpga_pad_GPIO_A[2]:2 gfpga_pad_GPIO_A[2] 0.01713839 +9 gfpga_pad_GPIO_A[2]:4 gfpga_pad_GPIO_A[2]:3 0.01289286 +10 gfpga_pad_GPIO_A[2]:5 gfpga_pad_GPIO_A[2]:4 1e-05 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[13] 0.001526552 //LENGTH 11.180 LUMPCC 0.0005883717 DR + +*CONN +*I cby_0__2_:chany_bottom_out[13] O *L 0 *C 307.280 669.270 +*I sb_0__1_:chany_top_in[13] I *L 0 *C 307.280 658.090 +*N cby_0__1__1_chany_bottom_out[13]:2 *C 307.280 667.519 +*N cby_0__1__1_chany_bottom_out[13]:3 *C 307.280 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[13] 0.0002272921 +1 sb_0__1_:chany_top_in[13] 0.0002417983 +2 cby_0__1__1_chany_bottom_out[13]:2 0.0002417983 +3 cby_0__1__1_chany_bottom_out[13]:3 0.0002272921 +4 sb_0__1_:chany_top_in[13] sb_0__1_:chany_top_in[17] 6.727079e-05 +5 cby_0__1__1_chany_bottom_out[13]:2 cby_0__1__1_chany_bottom_out[17]:2 6.727079e-05 +6 cby_0__2_:chany_bottom_out[13] cby_0__2_:chany_bottom_in[8] 8.965721e-06 +7 sb_0__1_:chany_top_in[13] sb_0__1_:chany_top_out[8] 0.0002179493 +8 cby_0__1__1_chany_bottom_out[13]:3 sb_0__1__0_chany_top_out[8]:2 8.965721e-06 +9 cby_0__1__1_chany_bottom_out[13]:2 sb_0__1__0_chany_top_out[8]:3 0.0002179493 + +*RES +0 cby_0__2_:chany_bottom_out[13] cby_0__1__1_chany_bottom_out[13]:3 0.0002741666 +1 cby_0__1__1_chany_bottom_out[13]:3 cby_0__1__1_chany_bottom_out[13]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[13]:2 sb_0__1_:chany_top_in[13] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[18] 0.001681339 //LENGTH 11.180 LUMPCC 0.0004388062 DR + +*CONN +*I cby_0__2_:chany_bottom_out[18] O *L 0 *C 331.200 669.270 +*I sb_0__1_:chany_top_in[18] I *L 0 *C 331.200 658.090 +*N cby_0__1__1_chany_bottom_out[18]:2 *C 331.200 667.519 +*N cby_0__1__1_chany_bottom_out[18]:3 *C 331.200 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[18] 0.0002154154 +1 sb_0__1_:chany_top_in[18] 0.0004058511 +2 cby_0__1__1_chany_bottom_out[18]:2 0.0004058511 +3 cby_0__1__1_chany_bottom_out[18]:3 0.0002154154 +4 cby_0__2_:chany_bottom_out[18] cby_0__2_:chany_bottom_in[15] 8.99572e-06 +5 sb_0__1_:chany_top_in[18] sb_0__1_:chany_top_out[15] 0.0002104074 +6 cby_0__1__1_chany_bottom_out[18]:3 sb_0__1__0_chany_top_out[15]:2 8.99572e-06 +7 cby_0__1__1_chany_bottom_out[18]:2 sb_0__1__0_chany_top_out[15]:3 0.0002104074 + +*RES +0 cby_0__2_:chany_bottom_out[18] cby_0__1__1_chany_bottom_out[18]:3 0.0002741666 +1 cby_0__1__1_chany_bottom_out[18]:3 cby_0__1__1_chany_bottom_out[18]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[18]:2 sb_0__1_:chany_top_in[18] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_top_out[3] 0.001184551 //LENGTH 11.020 LUMPCC 0.0002743332 DR + +*CONN +*I cby_0__2_:chany_top_out[3] O *L 0 *C 300.840 777.850 +*I sb_0__2_:chany_bottom_in[3] I *L 0 *C 300.840 788.870 + +*CAP +0 cby_0__2_:chany_top_out[3] 0.0004551088 +1 sb_0__2_:chany_bottom_in[3] 0.0004551088 +2 cby_0__2_:chany_top_out[3] cby_0__2_:chany_top_out[1] 0.0001371666 +3 sb_0__2_:chany_bottom_in[3] sb_0__2_:chany_bottom_in[1] 0.0001371666 + +*RES +0 cby_0__2_:chany_top_out[3] sb_0__2_:chany_bottom_in[3] 0.009839285 + +*END + +*D_NET cby_0__1__1_chany_top_out[6] 0.001209785 //LENGTH 11.020 LUMPCC 0.0004638451 DR + +*CONN +*I cby_0__2_:chany_top_out[6] O *L 0 *C 339.940 777.850 +*I sb_0__2_:chany_bottom_in[6] I *L 0 *C 339.940 788.870 + +*CAP +0 cby_0__2_:chany_top_out[6] 0.0003729701 +1 sb_0__2_:chany_bottom_in[6] 0.0003729701 +2 cby_0__2_:chany_top_out[6] cby_0__2_:chany_top_out[10] 0.0001430462 +3 sb_0__2_:chany_bottom_in[6] sb_0__2_:chany_bottom_in[10] 0.0001430462 +4 cby_0__2_:chany_top_out[6] cby_0__2_:ccff_head[0] 8.887635e-05 +5 sb_0__2_:chany_bottom_in[6] sb_0__2_:ccff_tail[0] 8.887635e-05 + +*RES +0 cby_0__2_:chany_top_out[6] sb_0__2_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[11] 0.001192866 //LENGTH 11.020 LUMPCC 0.0003123366 DR + +*CONN +*I cby_0__2_:chany_top_out[11] O *L 0 *C 317.860 777.850 +*I sb_0__2_:chany_bottom_in[11] I *L 0 *C 317.860 788.870 + +*CAP +0 cby_0__2_:chany_top_out[11] 0.0004402646 +1 sb_0__2_:chany_bottom_in[11] 0.0004402646 +2 cby_0__2_:chany_top_out[11] cby_0__2_:chany_top_out[17] 0.0001369426 +3 sb_0__2_:chany_bottom_in[11] sb_0__2_:chany_bottom_in[17] 0.0001369426 +4 cby_0__2_:chany_top_out[11] cby_0__2_:chany_top_in[1] 1.922567e-05 +5 sb_0__2_:chany_bottom_in[11] sb_0__2_:chany_bottom_out[1] 1.922567e-05 + +*RES +0 cby_0__2_:chany_top_out[11] sb_0__2_:chany_bottom_in[11] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[16] 0.001168949 //LENGTH 11.020 LUMPCC 0.0002880268 DR + +*CONN +*I cby_0__2_:chany_top_out[16] O *L 0 *C 328.900 777.850 +*I sb_0__2_:chany_bottom_in[16] I *L 0 *C 328.900 788.870 + +*CAP +0 cby_0__2_:chany_top_out[16] 0.000440461 +1 sb_0__2_:chany_bottom_in[16] 0.000440461 +2 cby_0__2_:chany_top_out[16] cby_0__2_:chany_top_in[10] 0.0001440134 +3 sb_0__2_:chany_bottom_in[16] sb_0__2_:chany_bottom_out[10] 0.0001440134 + +*RES +0 cby_0__2_:chany_top_out[16] sb_0__2_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_0__1__1_left_grid_pin_0_[0] 0.001726749 //LENGTH 13.180 LUMPCC 0.0002815861 DR + +*CONN +*I cby_0__2_:left_grid_pin_0_[0] O *L 0 *C 287.190 768.400 +*I grid_io_left_0__2_:right_width_0_height_0__pin_0_[0] I *L 0 *C 274.010 768.400 + +*CAP +0 cby_0__2_:left_grid_pin_0_[0] 0.0007225816 +1 grid_io_left_0__2_:right_width_0_height_0__pin_0_[0] 0.0007225816 +2 cby_0__2_:left_grid_pin_0_[0] grid_io_left_1_ccff_tail[0]:10 0.000140793 +3 grid_io_left_0__2_:right_width_0_height_0__pin_0_[0] grid_io_left_0__2_:ccff_tail[0] 0.000140793 + +*RES +0 cby_0__2_:left_grid_pin_0_[0] grid_io_left_0__2_:right_width_0_height_0__pin_0_[0] 0.002064867 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[2] 0.001184261 //LENGTH 11.020 LUMPCC 0.0004845848 DR + +*CONN +*I cby_1__1_:chany_bottom_out[2] O *L 0 *C 602.140 408.070 +*I sb_1__0_:chany_top_in[2] I *L 0 *C 602.140 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[2] 0.000349838 +1 sb_1__0_:chany_top_in[2] 0.000349838 +2 cby_1__1_:chany_bottom_out[2] cby_1__1_:chany_bottom_out[17] 0.0001472345 +3 sb_1__0_:chany_top_in[2] sb_1__0_:chany_top_in[17] 0.0001472345 +4 cby_1__1_:chany_bottom_out[2] cby_1__1_:chany_bottom_in[5] 9.50579e-05 +5 sb_1__0_:chany_top_in[2] sb_1__0_:chany_top_out[5] 9.50579e-05 + +*RES +0 cby_1__1_:chany_bottom_out[2] sb_1__0_:chany_top_in[2] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[8] 0.001237409 //LENGTH 11.020 LUMPCC 0.0005871544 DR + +*CONN +*I cby_1__1_:chany_bottom_out[8] O *L 0 *C 592.020 408.070 +*I sb_1__0_:chany_top_in[8] I *L 0 *C 592.020 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[8] 0.0003251273 +1 sb_1__0_:chany_top_in[8] 0.0003251273 +2 cby_1__1_:chany_bottom_out[8] cby_1__1_:chany_bottom_out[10] 0.0001450212 +3 sb_1__0_:chany_top_in[8] sb_1__0_:chany_top_in[10] 0.0001450212 +4 cby_1__1_:chany_bottom_out[8] cby_1__1_:chany_bottom_in[3] 0.000148556 +5 sb_1__0_:chany_top_in[8] sb_1__0_:chany_top_out[3] 0.000148556 + +*RES +0 cby_1__1_:chany_bottom_out[8] sb_1__0_:chany_top_in[8] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[16] 0.001231796 //LENGTH 11.020 LUMPCC 0.0005942238 DR + +*CONN +*I cby_1__1_:chany_bottom_out[16] O *L 0 *C 589.260 408.070 +*I sb_1__0_:chany_top_in[16] I *L 0 *C 589.260 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[16] 0.0003187861 +1 sb_1__0_:chany_top_in[16] 0.0003187861 +2 cby_1__1_:chany_bottom_out[16] cby_1__1_:chany_bottom_in[6] 0.000148556 +3 sb_1__0_:chany_top_in[16] sb_1__0_:chany_top_out[6] 0.000148556 +4 cby_1__1_:chany_bottom_out[16] cby_1__1_:chany_bottom_in[8] 0.000148556 +5 sb_1__0_:chany_top_in[16] sb_1__0_:chany_top_out[8] 0.000148556 + +*RES +0 cby_1__1_:chany_bottom_out[16] sb_1__0_:chany_top_in[16] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[1] 0.00128887 //LENGTH 11.020 LUMPCC 0.0005059171 DR + +*CONN +*I cby_1__1_:chany_top_out[1] O *L 0 *C 586.960 516.730 +*I sb_1__1_:chany_bottom_in[1] I *L 0 *C 586.960 527.750 + +*CAP +0 cby_1__1_:chany_top_out[1] 0.0003914766 +1 sb_1__1_:chany_bottom_in[1] 0.0003914766 +2 cby_1__1_:chany_top_out[1] cby_1__1_:chany_top_out[13] 0.0001275551 +3 sb_1__1_:chany_bottom_in[1] sb_1__1_:chany_bottom_in[13] 0.0001275551 +4 cby_1__1_:chany_top_out[1] cby_1__1_:chany_top_out[14] 0.0001254034 +5 sb_1__1_:chany_bottom_in[1] sb_1__1_:chany_bottom_in[14] 0.0001254034 + +*RES +0 cby_1__1_:chany_top_out[1] sb_1__1_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[8] 0.00128147 //LENGTH 11.020 LUMPCC 0.0005156055 DR + +*CONN +*I cby_1__1_:chany_top_out[8] O *L 0 *C 597.540 516.730 +*I sb_1__1_:chany_bottom_in[8] I *L 0 *C 597.540 527.750 + +*CAP +0 cby_1__1_:chany_top_out[8] 0.0003829321 +1 sb_1__1_:chany_bottom_in[8] 0.0003829321 +2 cby_1__1_:chany_top_out[8] cby_1__1_:chany_top_out[16] 0.0001289014 +3 sb_1__1_:chany_bottom_in[8] sb_1__1_:chany_bottom_in[16] 0.0001289014 +4 cby_1__1_:chany_top_out[8] cby_1__1_:chany_top_out[19] 0.0001289014 +5 sb_1__1_:chany_bottom_in[8] sb_1__1_:chany_bottom_in[19] 0.0001289014 + +*RES +0 cby_1__1_:chany_top_out[8] sb_1__1_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[15] 0.001293074 //LENGTH 11.020 LUMPCC 0.0005019171 DR + +*CONN +*I cby_1__1_:chany_top_out[15] O *L 0 *C 573.160 516.730 +*I sb_1__1_:chany_bottom_in[15] I *L 0 *C 573.160 527.750 + +*CAP +0 cby_1__1_:chany_top_out[15] 0.0003955785 +1 sb_1__1_:chany_bottom_in[15] 0.0003955785 +2 cby_1__1_:chany_top_out[15] cby_1__1_:chany_top_in[2] 0.0001254793 +3 sb_1__1_:chany_bottom_in[15] sb_1__1_:chany_bottom_out[2] 0.0001254793 +4 cby_1__1_:chany_top_out[15] cby_1__1_:chany_top_in[9] 0.0001254793 +5 sb_1__1_:chany_bottom_in[15] sb_1__1_:chany_bottom_out[9] 0.0001254793 + +*RES +0 cby_1__1_:chany_top_out[15] sb_1__1_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_0_[0] 0.00150197 //LENGTH 7.660 LUMPCC 0.0004756276 DR + +*CONN +*I cby_1__1_:left_grid_pin_0_[0] O *L 0 *C 548.470 510.000 +*I grid_clb_1__1_:right_width_0_height_0__pin_0_[0] I *L 0 *C 540.810 510.000 + +*CAP +0 cby_1__1_:left_grid_pin_0_[0] 0.0005131713 +1 grid_clb_1__1_:right_width_0_height_0__pin_0_[0] 0.0005131713 +2 cby_1__1_:left_grid_pin_0_[0] cby_1__1_:left_grid_pin_4_[0] 0.0001189069 +3 grid_clb_1__1_:right_width_0_height_0__pin_0_[0] grid_clb_1__1_:right_width_0_height_0__pin_4_[0] 0.0001189069 +4 cby_1__1_:left_grid_pin_0_[0] cby_1__1_:left_grid_pin_5_[0] 0.0001189069 +5 grid_clb_1__1_:right_width_0_height_0__pin_0_[0] grid_clb_1__1_:right_width_0_height_0__pin_5_[0] 0.0001189069 + +*RES +0 cby_1__1_:left_grid_pin_0_[0] grid_clb_1__1_:right_width_0_height_0__pin_0_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_2_[0] 0.001419627 //LENGTH 7.660 LUMPCC 0.0005453302 DR + +*CONN +*I cby_1__1_:left_grid_pin_2_[0] O *L 0 *C 548.470 505.920 +*I grid_clb_1__1_:right_width_0_height_0__pin_2_[0] I *L 0 *C 540.810 505.920 + +*CAP +0 cby_1__1_:left_grid_pin_2_[0] 0.0004371486 +1 grid_clb_1__1_:right_width_0_height_0__pin_2_[0] 0.0004371486 +2 cby_1__1_:left_grid_pin_2_[0] cby_1__1_:left_grid_pin_3_[0] 0.0001393266 +3 grid_clb_1__1_:right_width_0_height_0__pin_2_[0] grid_clb_1__1_:right_width_0_height_0__pin_3_[0] 0.0001393266 +4 cby_1__1_:left_grid_pin_2_[0] cby_1__1_:left_grid_pin_7_[0] 0.0001333385 +5 grid_clb_1__1_:right_width_0_height_0__pin_2_[0] grid_clb_1__1_:right_width_0_height_0__pin_7_[0] 0.0001333385 + +*RES +0 cby_1__1_:left_grid_pin_2_[0] grid_clb_1__1_:right_width_0_height_0__pin_2_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_9_[0] 0.00140029 //LENGTH 7.660 LUMPCC 0.0002334626 DR + +*CONN +*I cby_1__1_:left_grid_pin_9_[0] O *L 0 *C 548.470 489.600 +*I grid_clb_1__1_:right_width_0_height_0__pin_9_[0] I *L 0 *C 540.810 489.600 + +*CAP +0 cby_1__1_:left_grid_pin_9_[0] 0.0005834138 +1 grid_clb_1__1_:right_width_0_height_0__pin_9_[0] 0.0005834138 +2 cby_1__1_:left_grid_pin_9_[0] cby_1__1_:left_grid_pin_6_[0] 0.0001167313 +3 grid_clb_1__1_:right_width_0_height_0__pin_9_[0] grid_clb_1__1_:right_width_0_height_0__pin_6_[0] 0.0001167313 + +*RES +0 cby_1__1_:left_grid_pin_9_[0] grid_clb_1__1_:right_width_0_height_0__pin_9_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[2] 0.001199065 //LENGTH 11.020 LUMPCC 0.0004782986 DR + +*CONN +*I cby_1__2_:chany_bottom_out[2] O *L 0 *C 602.140 669.190 +*I sb_1__1_:chany_top_in[2] I *L 0 *C 602.140 658.170 +*N cby_1__1__1_chany_bottom_out[2]:2 *C 602.140 667.519 +*N cby_1__1__1_chany_bottom_out[2]:3 *C 602.140 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[2] 0.0001169096 +1 sb_1__1_:chany_top_in[2] 0.0002434735 +2 cby_1__1__1_chany_bottom_out[2]:2 0.0002434735 +3 cby_1__1__1_chany_bottom_out[2]:3 0.0001169096 +4 cby_1__2_:chany_bottom_out[2] cby_1__2_:chany_bottom_out[17] 7.340369e-06 +5 sb_1__1_:chany_top_in[2] sb_1__1_:chany_top_in[17] 0.0001380049 +6 cby_1__1__1_chany_bottom_out[2]:3 cby_1__1__1_chany_bottom_out[17]:3 7.340369e-06 +7 cby_1__1__1_chany_bottom_out[2]:2 cby_1__1__1_chany_bottom_out[17]:2 0.0001380049 +8 cby_1__2_:chany_bottom_out[2] cby_1__2_:chany_bottom_in[5] 1.486125e-06 +9 sb_1__1_:chany_top_in[2] sb_1__1_:chany_top_out[5] 9.231795e-05 +10 cby_1__1__1_chany_bottom_out[2]:3 sb_1__1__0_chany_top_out[5]:2 1.486125e-06 +11 cby_1__1__1_chany_bottom_out[2]:2 sb_1__1__0_chany_top_out[5]:3 9.231795e-05 + +*RES +0 cby_1__2_:chany_bottom_out[2] cby_1__1__1_chany_bottom_out[2]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[2]:3 cby_1__1__1_chany_bottom_out[2]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[2]:2 sb_1__1_:chany_top_in[2] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[9] 0.001245923 //LENGTH 11.020 LUMPCC 0.0005859647 DR + +*CONN +*I cby_1__2_:chany_bottom_out[9] O *L 0 *C 587.420 669.190 +*I sb_1__1_:chany_top_in[9] I *L 0 *C 587.420 658.170 +*N cby_1__1__1_chany_bottom_out[9]:2 *C 587.420 667.519 +*N cby_1__1__1_chany_bottom_out[9]:3 *C 587.420 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[9] 0.000110944 +1 sb_1__1_:chany_top_in[9] 0.0002190351 +2 cby_1__1__1_chany_bottom_out[9]:2 0.0002190351 +3 cby_1__1__1_chany_bottom_out[9]:3 0.000110944 +4 cby_1__2_:chany_bottom_out[9] cby_1__2_:chany_bottom_out[7] 7.340376e-06 +5 sb_1__1_:chany_top_in[9] sb_1__1_:chany_top_in[7] 0.0001387437 +6 cby_1__1__1_chany_bottom_out[9]:3 cby_1__1__1_chany_bottom_out[7]:3 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[9]:2 cby_1__1__1_chany_bottom_out[7]:2 0.0001387437 +8 cby_1__2_:chany_bottom_out[9] cby_1__2_:chany_bottom_in[8] 7.346249e-06 +9 sb_1__1_:chany_top_in[9] sb_1__1_:chany_top_out[8] 0.000139552 +10 cby_1__1__1_chany_bottom_out[9]:3 sb_1__1__0_chany_top_out[8]:2 7.346249e-06 +11 cby_1__1__1_chany_bottom_out[9]:2 sb_1__1__0_chany_top_out[8]:3 0.000139552 + +*RES +0 cby_1__2_:chany_bottom_out[9] cby_1__1__1_chany_bottom_out[9]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[9]:3 cby_1__1__1_chany_bottom_out[9]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[9]:2 sb_1__1_:chany_top_in[9] 0.008347322 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[15] 0.001233269 //LENGTH 11.020 LUMPCC 0.000591761 DR + +*CONN +*I cby_1__2_:chany_bottom_out[15] O *L 0 *C 573.620 669.190 +*I sb_1__1_:chany_top_in[15] I *L 0 *C 573.620 658.170 +*N cby_1__1__1_chany_bottom_out[15]:2 *C 573.620 667.519 +*N cby_1__1__1_chany_bottom_out[15]:3 *C 573.620 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[15] 0.0001108085 +1 sb_1__1_:chany_top_in[15] 0.0002099457 +2 cby_1__1__1_chany_bottom_out[15]:2 0.0002099457 +3 cby_1__1__1_chany_bottom_out[15]:3 0.0001108085 +4 cby_1__2_:chany_bottom_out[15] cby_1__2_:chany_bottom_out[12] 7.340376e-06 +5 sb_1__1_:chany_top_in[15] sb_1__1_:chany_top_in[12] 0.0001377969 +6 cby_1__1__1_chany_bottom_out[15]:3 cby_1__1__1_chany_bottom_out[12]:3 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[15]:2 cby_1__1__1_chany_bottom_out[12]:2 0.0001377969 +8 cby_1__2_:chany_bottom_out[15] cby_1__2_:chany_bottom_out[14] 7.341718e-06 +9 sb_1__1_:chany_top_in[15] sb_1__1_:chany_top_in[14] 0.0001434015 +10 cby_1__1__1_chany_bottom_out[15]:3 cby_1__1__1_chany_bottom_out[14]:3 7.341718e-06 +11 cby_1__1__1_chany_bottom_out[15]:2 cby_1__1__1_chany_bottom_out[14]:2 0.0001434015 + +*RES +0 cby_1__2_:chany_bottom_out[15] cby_1__1__1_chany_bottom_out[15]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[15]:3 cby_1__1__1_chany_bottom_out[15]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[15]:2 sb_1__1_:chany_top_in[15] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_top_out[0] 0.001275946 //LENGTH 11.020 LUMPCC 0.0005247784 DR + +*CONN +*I cby_1__2_:chany_top_out[0] O *L 0 *C 602.140 777.850 +*I sb_1__2_:chany_bottom_in[0] I *L 0 *C 602.140 788.870 + +*CAP +0 cby_1__2_:chany_top_out[0] 0.0003755839 +1 sb_1__2_:chany_bottom_in[0] 0.0003755839 +2 cby_1__2_:chany_top_out[0] cby_1__2_:chany_top_out[2] 0.0001311946 +3 sb_1__2_:chany_bottom_in[0] sb_1__2_:chany_bottom_in[2] 0.0001311946 +4 cby_1__2_:chany_top_out[0] cby_1__2_:chany_top_in[0] 0.0001311946 +5 sb_1__2_:chany_bottom_in[0] sb_1__2_:chany_bottom_out[0] 0.0001311946 + +*RES +0 cby_1__2_:chany_top_out[0] sb_1__2_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[4] 0.001274636 //LENGTH 11.020 LUMPCC 0.0005263244 DR + +*CONN +*I cby_1__2_:chany_top_out[4] O *L 0 *C 585.120 777.850 +*I sb_1__2_:chany_bottom_in[4] I *L 0 *C 585.120 788.870 + +*CAP +0 cby_1__2_:chany_top_out[4] 0.0003741559 +1 sb_1__2_:chany_bottom_in[4] 0.0003741559 +2 cby_1__2_:chany_top_out[4] cby_1__2_:chany_top_out[14] 0.0001315811 +3 sb_1__2_:chany_bottom_in[4] sb_1__2_:chany_bottom_in[14] 0.0001315811 +4 cby_1__2_:chany_top_out[4] cby_1__2_:chany_top_in[16] 0.0001315811 +5 sb_1__2_:chany_bottom_in[4] sb_1__2_:chany_bottom_out[16] 0.0001315811 + +*RES +0 cby_1__2_:chany_top_out[4] sb_1__2_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[10] 0.001279574 //LENGTH 11.020 LUMPCC 0.0005195668 DR + +*CONN +*I cby_1__2_:chany_top_out[10] O *L 0 *C 582.360 777.850 +*I sb_1__2_:chany_bottom_in[10] I *L 0 *C 582.360 788.870 + +*CAP +0 cby_1__2_:chany_top_out[10] 0.0003800038 +1 sb_1__2_:chany_bottom_in[10] 0.0003800038 +2 cby_1__2_:chany_top_out[10] cby_1__2_:chany_top_in[8] 0.0001298917 +3 sb_1__2_:chany_bottom_in[10] sb_1__2_:chany_bottom_out[8] 0.0001298917 +4 cby_1__2_:chany_top_out[10] cby_1__2_:chany_top_in[13] 0.0001298917 +5 sb_1__2_:chany_bottom_in[10] sb_1__2_:chany_bottom_out[13] 0.0001298917 + +*RES +0 cby_1__2_:chany_top_out[10] sb_1__2_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[16] 0.001267079 //LENGTH 11.020 LUMPCC 0.00052327 DR + +*CONN +*I cby_1__2_:chany_top_out[16] O *L 0 *C 596.620 777.850 +*I sb_1__2_:chany_bottom_in[16] I *L 0 *C 596.620 788.870 + +*CAP +0 cby_1__2_:chany_top_out[16] 0.0003719044 +1 sb_1__2_:chany_bottom_in[16] 0.0003719044 +2 cby_1__2_:chany_top_out[16] cby_1__2_:chany_top_out[5] 0.0001259201 +3 sb_1__2_:chany_bottom_in[16] sb_1__2_:chany_bottom_in[5] 0.0001259201 +4 cby_1__2_:chany_top_out[16] cby_1__2_:chany_top_out[8] 0.000135715 +5 sb_1__2_:chany_bottom_in[16] sb_1__2_:chany_bottom_in[8] 0.000135715 + +*RES +0 cby_1__2_:chany_top_out[16] sb_1__2_:chany_bottom_in[16] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_11_[0] 0.001548723 //LENGTH 7.660 LUMPCC 0.0004164909 DR + +*CONN +*I cby_1__2_:left_grid_pin_11_[0] O *L 0 *C 548.470 746.640 +*I grid_clb_1__2_:right_width_0_height_0__pin_11_[0] I *L 0 *C 540.810 746.640 + +*CAP +0 cby_1__2_:left_grid_pin_11_[0] 0.0005661161 +1 grid_clb_1__2_:right_width_0_height_0__pin_11_[0] 0.0005661161 +2 cby_1__2_:left_grid_pin_11_[0] cby_1__2_:left_grid_pin_10_[0] 0.0001041227 +3 grid_clb_1__2_:right_width_0_height_0__pin_11_[0] grid_clb_1__2_:right_width_0_height_0__pin_10_[0] 0.0001041227 +4 cby_1__2_:left_grid_pin_11_[0] cby_1__2_:left_grid_pin_8_[0] 0.0001041227 +5 grid_clb_1__2_:right_width_0_height_0__pin_11_[0] grid_clb_1__2_:right_width_0_height_0__pin_8_[0] 0.0001041227 + +*RES +0 cby_1__2_:left_grid_pin_11_[0] grid_clb_1__2_:right_width_0_height_0__pin_11_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_5_[0] 0.001380909 //LENGTH 7.660 LUMPCC 0.0002581568 DR + +*CONN +*I cby_1__2_:left_grid_pin_5_[0] O *L 0 *C 548.470 772.480 +*I grid_clb_1__2_:right_width_0_height_0__pin_5_[0] I *L 0 *C 540.810 772.480 + +*CAP +0 cby_1__2_:left_grid_pin_5_[0] 0.0005613763 +1 grid_clb_1__2_:right_width_0_height_0__pin_5_[0] 0.0005613763 +2 cby_1__2_:left_grid_pin_5_[0] cby_1__2_:left_grid_pin_0_[0] 0.0001290784 +3 grid_clb_1__2_:right_width_0_height_0__pin_5_[0] grid_clb_1__2_:right_width_0_height_0__pin_0_[0] 0.0001290784 + +*RES +0 cby_1__2_:left_grid_pin_5_[0] grid_clb_1__2_:right_width_0_height_0__pin_5_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_right_grid_pin_52_[0] 0.001105643 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_1__2_:right_grid_pin_52_[0] O *L 0 *C 632.810 748.000 +*I grid_clb_2__2_:left_width_0_height_0__pin_52_[0] I *L 0 *C 640.470 748.000 + +*CAP +0 cby_1__2_:right_grid_pin_52_[0] 0.0005528216 +1 grid_clb_2__2_:left_width_0_height_0__pin_52_[0] 0.0005528216 + +*RES +0 cby_1__2_:right_grid_pin_52_[0] grid_clb_2__2_:left_width_0_height_0__pin_52_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[2] 0.001193286 //LENGTH 11.020 LUMPCC 0.0004722831 DR + +*CONN +*I cby_2__1_:chany_bottom_out[2] O *L 0 *C 863.420 408.070 +*I sb_2__0_:chany_top_in[2] I *L 0 *C 863.420 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[2] 0.0003605015 +1 sb_2__0_:chany_top_in[2] 0.0003605015 +2 cby_2__1_:chany_bottom_out[2] cby_2__1_:chany_bottom_out[17] 0.0001451958 +3 sb_2__0_:chany_top_in[2] sb_2__0_:chany_top_in[17] 0.0001451958 +4 cby_2__1_:chany_bottom_out[2] cby_2__1_:chany_bottom_in[5] 9.094577e-05 +5 sb_2__0_:chany_top_in[2] sb_2__0_:chany_top_out[5] 9.094577e-05 + +*RES +0 cby_2__1_:chany_bottom_out[2] sb_2__0_:chany_top_in[2] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[9] 0.00123756 //LENGTH 11.020 LUMPCC 0.0005795517 DR + +*CONN +*I cby_2__1_:chany_bottom_out[9] O *L 0 *C 848.700 408.070 +*I sb_2__0_:chany_top_in[9] I *L 0 *C 848.700 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[9] 0.0003290043 +1 sb_2__0_:chany_top_in[9] 0.0003290043 +2 cby_2__1_:chany_bottom_out[9] cby_2__1_:chany_bottom_out[7] 0.0001448879 +3 sb_2__0_:chany_top_in[9] sb_2__0_:chany_top_in[7] 0.0001448879 +4 cby_2__1_:chany_bottom_out[9] cby_2__1_:chany_bottom_in[8] 0.0001448879 +5 sb_2__0_:chany_top_in[9] sb_2__0_:chany_top_out[8] 0.0001448879 + +*RES +0 cby_2__1_:chany_bottom_out[9] sb_2__0_:chany_top_in[9] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[14] 0.001153695 //LENGTH 11.020 LUMPCC 0.0003672335 DR + +*CONN +*I cby_2__1_:chany_bottom_out[14] O *L 0 *C 835.820 408.070 +*I sb_2__0_:chany_top_in[14] I *L 0 *C 835.820 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[14] 0.0003932307 +1 sb_2__0_:chany_top_in[14] 0.0003932307 +2 cby_2__1_:chany_bottom_out[14] cby_2__1_:chany_bottom_out[1] 3.533055e-05 +3 sb_2__0_:chany_top_in[14] sb_2__0_:chany_top_in[1] 3.533055e-05 +4 cby_2__1_:chany_bottom_out[14] cby_2__1_:chany_bottom_out[15] 0.0001482862 +5 sb_2__0_:chany_top_in[14] sb_2__0_:chany_top_in[15] 0.0001482862 + +*RES +0 cby_2__1_:chany_bottom_out[14] sb_2__0_:chany_top_in[14] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[2] 0.001281216 //LENGTH 11.020 LUMPCC 0.0005269798 DR + +*CONN +*I cby_2__1_:chany_top_out[2] O *L 0 *C 862.500 516.730 +*I sb_2__1_:chany_bottom_in[2] I *L 0 *C 862.500 527.750 + +*CAP +0 cby_2__1_:chany_top_out[2] 0.0003771181 +1 sb_2__1_:chany_bottom_in[2] 0.0003771181 +2 cby_2__1_:chany_top_out[2] cby_2__1_:chany_top_out[0] 0.0001317449 +3 sb_2__1_:chany_bottom_in[2] sb_2__1_:chany_bottom_in[0] 0.0001317449 +4 cby_2__1_:chany_top_out[2] cby_2__1_:chany_top_in[12] 0.0001317449 +5 sb_2__1_:chany_bottom_in[2] sb_2__1_:chany_bottom_out[12] 0.0001317449 + +*RES +0 cby_2__1_:chany_top_out[2] sb_2__1_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[11] 0.001201798 //LENGTH 11.020 LUMPCC 0.0003505939 DR + +*CONN +*I cby_2__1_:chany_top_out[11] O *L 0 *C 867.560 516.730 +*I sb_2__1_:chany_bottom_in[11] I *L 0 *C 867.560 527.750 + +*CAP +0 cby_2__1_:chany_top_out[11] 0.0004256018 +1 sb_2__1_:chany_bottom_in[11] 0.0004256018 +2 cby_2__1_:chany_top_out[11] cby_2__1_:chany_top_out[7] 0.0001366499 +3 sb_2__1_:chany_bottom_in[11] sb_2__1_:chany_bottom_in[7] 0.0001366499 +4 cby_2__1_:chany_top_out[11] cby_2__1_:chany_top_out[9] 3.864707e-05 +5 sb_2__1_:chany_bottom_in[11] sb_2__1_:chany_bottom_in[9] 3.864707e-05 + +*RES +0 cby_2__1_:chany_top_out[11] sb_2__1_:chany_bottom_in[11] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[15] 0.001279521 //LENGTH 11.020 LUMPCC 0.0005318955 DR + +*CONN +*I cby_2__1_:chany_top_out[15] O *L 0 *C 834.440 516.730 +*I sb_2__1_:chany_bottom_in[15] I *L 0 *C 834.440 527.750 + +*CAP +0 cby_2__1_:chany_top_out[15] 0.0003738126 +1 sb_2__1_:chany_bottom_in[15] 0.0003738126 +2 cby_2__1_:chany_top_out[15] cby_2__1_:chany_top_in[2] 0.0001329739 +3 sb_2__1_:chany_bottom_in[15] sb_2__1_:chany_bottom_out[2] 0.0001329739 +4 cby_2__1_:chany_top_out[15] cby_2__1_:chany_top_in[9] 0.0001329739 +5 sb_2__1_:chany_bottom_in[15] sb_2__1_:chany_bottom_out[9] 0.0001329739 + +*RES +0 cby_2__1_:chany_top_out[15] sb_2__1_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_11_[0] 0.001215779 //LENGTH 7.660 LUMPCC 0.0007181676 DR + +*CONN +*I cby_2__1_:left_grid_pin_11_[0] O *L 0 *C 809.750 485.520 +*I grid_clb_2__1_:right_width_0_height_0__pin_11_[0] I *L 0 *C 802.090 485.520 + +*CAP +0 cby_2__1_:left_grid_pin_11_[0] 0.0002488056 +1 grid_clb_2__1_:right_width_0_height_0__pin_11_[0] 0.0002488056 +2 cby_2__1_:left_grid_pin_11_[0] cby_2__1_:left_grid_pin_10_[0] 0.0001795419 +3 grid_clb_2__1_:right_width_0_height_0__pin_11_[0] grid_clb_2__1_:right_width_0_height_0__pin_10_[0] 0.0001795419 +4 cby_2__1_:left_grid_pin_11_[0] cby_2__1_:left_grid_pin_8_[0] 0.0001795419 +5 grid_clb_2__1_:right_width_0_height_0__pin_11_[0] grid_clb_2__1_:right_width_0_height_0__pin_8_[0] 0.0001795419 + +*RES +0 cby_2__1_:left_grid_pin_11_[0] grid_clb_2__1_:right_width_0_height_0__pin_11_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_3_[0] 0.001215787 //LENGTH 7.660 LUMPCC 0.0007181166 DR + +*CONN +*I cby_2__1_:left_grid_pin_3_[0] O *L 0 *C 809.750 504.560 +*I grid_clb_2__1_:right_width_0_height_0__pin_3_[0] I *L 0 *C 802.090 504.560 + +*CAP +0 cby_2__1_:left_grid_pin_3_[0] 0.0002488354 +1 grid_clb_2__1_:right_width_0_height_0__pin_3_[0] 0.0002488354 +2 cby_2__1_:left_grid_pin_3_[0] cby_2__1_:left_grid_pin_1_[0] 0.0001795292 +3 grid_clb_2__1_:right_width_0_height_0__pin_3_[0] grid_clb_2__1_:right_width_0_height_0__pin_1_[0] 0.0001795292 +4 cby_2__1_:left_grid_pin_3_[0] cby_2__1_:left_grid_pin_2_[0] 0.0001795292 +5 grid_clb_2__1_:right_width_0_height_0__pin_3_[0] grid_clb_2__1_:right_width_0_height_0__pin_2_[0] 0.0001795292 + +*RES +0 cby_2__1_:left_grid_pin_3_[0] grid_clb_2__1_:right_width_0_height_0__pin_3_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[0] 0.001268542 //LENGTH 11.020 LUMPCC 0.0005404799 DR + +*CONN +*I cby_2__2_:chany_bottom_out[0] O *L 0 *C 861.580 669.190 +*I sb_2__1_:chany_top_in[0] I *L 0 *C 861.580 658.170 +*N cby_1__1__3_chany_bottom_out[0]:2 *C 861.580 667.519 +*N cby_1__1__3_chany_bottom_out[0]:3 *C 861.580 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[0] 0.0001149169 +1 sb_2__1_:chany_top_in[0] 0.0002491141 +2 cby_1__1__3_chany_bottom_out[0]:2 0.0002491141 +3 cby_1__1__3_chany_bottom_out[0]:3 0.0001149169 +4 cby_2__2_:chany_bottom_out[0] cby_2__2_:chany_bottom_out[17] 6.079439e-06 +5 sb_2__1_:chany_top_in[0] sb_2__1_:chany_top_in[17] 0.0001284326 +6 cby_1__1__3_chany_bottom_out[0]:3 cby_1__1__3_chany_bottom_out[17]:3 6.079439e-06 +7 cby_1__1__3_chany_bottom_out[0]:2 cby_1__1__3_chany_bottom_out[17]:2 0.0001284326 +8 cby_2__2_:chany_bottom_out[0] cby_2__2_:chany_bottom_in[12] 7.295327e-06 +9 sb_2__1_:chany_top_in[0] sb_2__1_:chany_top_out[12] 0.0001284326 +10 cby_1__1__3_chany_bottom_out[0]:3 sb_2__1__0_chany_top_out[12]:2 7.295327e-06 +11 cby_1__1__3_chany_bottom_out[0]:2 sb_2__1__0_chany_top_out[12]:3 0.0001284326 + +*RES +0 cby_2__2_:chany_bottom_out[0] cby_1__1__3_chany_bottom_out[0]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[0]:3 cby_1__1__3_chany_bottom_out[0]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[0]:2 sb_2__1_:chany_top_in[0] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[8] 0.001258107 //LENGTH 11.020 LUMPCC 0.0005567565 DR + +*CONN +*I cby_2__2_:chany_bottom_out[8] O *L 0 *C 853.300 669.190 +*I sb_2__1_:chany_top_in[8] I *L 0 *C 853.300 658.170 +*N cby_1__1__3_chany_bottom_out[8]:2 *C 853.300 667.519 +*N cby_1__1__3_chany_bottom_out[8]:3 *C 853.300 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[8] 0.0001109382 +1 sb_2__1_:chany_top_in[8] 0.0002397372 +2 cby_1__1__3_chany_bottom_out[8]:2 0.0002397372 +3 cby_1__1__3_chany_bottom_out[8]:3 0.0001109382 +4 cby_2__2_:chany_bottom_out[8] cby_2__2_:chany_bottom_out[10] 7.346249e-06 +5 sb_2__1_:chany_top_in[8] sb_2__1_:chany_top_in[10] 0.0001318429 +6 cby_1__1__3_chany_bottom_out[8]:3 cby_1__1__3_chany_bottom_out[10]:3 7.346249e-06 +7 cby_1__1__3_chany_bottom_out[8]:2 cby_1__1__3_chany_bottom_out[10]:2 0.0001318429 +8 cby_2__2_:chany_bottom_out[8] cby_2__2_:chany_bottom_in[3] 7.346249e-06 +9 sb_2__1_:chany_top_in[8] sb_2__1_:chany_top_out[3] 0.0001318429 +10 cby_1__1__3_chany_bottom_out[8]:3 sb_2__1__0_chany_top_out[3]:2 7.346249e-06 +11 cby_1__1__3_chany_bottom_out[8]:2 sb_2__1__0_chany_top_out[3]:3 0.0001318429 + +*RES +0 cby_2__2_:chany_bottom_out[8] cby_1__1__3_chany_bottom_out[8]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[8]:3 cby_1__1__3_chany_bottom_out[8]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[8]:2 sb_2__1_:chany_top_in[8] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[15] 0.00125812 //LENGTH 11.020 LUMPCC 0.0005559404 DR + +*CONN +*I cby_2__2_:chany_bottom_out[15] O *L 0 *C 834.900 669.190 +*I sb_2__1_:chany_top_in[15] I *L 0 *C 834.900 658.170 +*N cby_1__1__3_chany_bottom_out[15]:2 *C 834.900 667.519 +*N cby_1__1__3_chany_bottom_out[15]:3 *C 834.900 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[15] 0.0001112829 +1 sb_2__1_:chany_top_in[15] 0.0002398067 +2 cby_1__1__3_chany_bottom_out[15]:2 0.0002398067 +3 cby_1__1__3_chany_bottom_out[15]:3 0.0001112829 +4 cby_2__2_:chany_bottom_out[15] cby_2__2_:chany_bottom_out[12] 7.244793e-06 +5 sb_2__1_:chany_top_in[15] sb_2__1_:chany_top_in[12] 0.0001317403 +6 cby_1__1__3_chany_bottom_out[15]:3 cby_1__1__3_chany_bottom_out[12]:3 7.244793e-06 +7 cby_1__1__3_chany_bottom_out[15]:2 cby_1__1__3_chany_bottom_out[12]:2 0.0001317403 +8 cby_2__2_:chany_bottom_out[15] cby_2__2_:chany_bottom_out[14] 7.244793e-06 +9 sb_2__1_:chany_top_in[15] sb_2__1_:chany_top_in[14] 0.0001317403 +10 cby_1__1__3_chany_bottom_out[15]:3 cby_1__1__3_chany_bottom_out[14]:3 7.244793e-06 +11 cby_1__1__3_chany_bottom_out[15]:2 cby_1__1__3_chany_bottom_out[14]:2 0.0001317403 + +*RES +0 cby_2__2_:chany_bottom_out[15] cby_1__1__3_chany_bottom_out[15]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[15]:3 cby_1__1__3_chany_bottom_out[15]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[15]:2 sb_2__1_:chany_top_in[15] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_top_out[2] 0.001259614 //LENGTH 11.020 LUMPCC 0.0005582116 DR + +*CONN +*I cby_2__2_:chany_top_out[2] O *L 0 *C 862.500 777.850 +*I sb_2__2_:chany_bottom_in[2] I *L 0 *C 862.500 788.870 + +*CAP +0 cby_2__2_:chany_top_out[2] 0.0003507012 +1 sb_2__2_:chany_bottom_in[2] 0.0003507012 +2 cby_2__2_:chany_top_out[2] cby_2__2_:chany_top_out[0] 0.0001395529 +3 sb_2__2_:chany_bottom_in[2] sb_2__2_:chany_bottom_in[0] 0.0001395529 +4 cby_2__2_:chany_top_out[2] cby_2__2_:chany_top_in[12] 0.0001395529 +5 sb_2__2_:chany_bottom_in[2] sb_2__2_:chany_bottom_out[12] 0.0001395529 + +*RES +0 cby_2__2_:chany_top_out[2] sb_2__2_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[11] 0.001167731 //LENGTH 11.020 LUMPCC 0.0003888179 DR + +*CONN +*I cby_2__2_:chany_top_out[11] O *L 0 *C 867.560 777.850 +*I sb_2__2_:chany_bottom_in[11] I *L 0 *C 867.560 788.870 + +*CAP +0 cby_2__2_:chany_top_out[11] 0.0003894566 +1 sb_2__2_:chany_bottom_in[11] 0.0003894566 +2 cby_2__2_:chany_top_out[11] cby_2__2_:chany_top_out[7] 0.000146484 +3 sb_2__2_:chany_bottom_in[11] sb_2__2_:chany_bottom_in[7] 0.000146484 +4 cby_2__2_:chany_top_out[11] cby_2__2_:chany_top_out[9] 4.792491e-05 +5 sb_2__2_:chany_bottom_in[11] sb_2__2_:chany_bottom_in[9] 4.792491e-05 + +*RES +0 cby_2__2_:chany_top_out[11] sb_2__2_:chany_bottom_in[11] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[19] 0.001251666 //LENGTH 11.020 LUMPCC 0.0005689875 DR + +*CONN +*I cby_2__2_:chany_top_out[19] O *L 0 *C 859.740 777.850 +*I sb_2__2_:chany_bottom_in[19] I *L 0 *C 859.740 788.870 + +*CAP +0 cby_2__2_:chany_top_out[19] 0.0003413391 +1 sb_2__2_:chany_bottom_in[19] 0.0003413391 +2 cby_2__2_:chany_top_out[19] cby_2__2_:chany_top_out[8] 0.0001422469 +3 sb_2__2_:chany_bottom_in[19] sb_2__2_:chany_bottom_in[8] 0.0001422469 +4 cby_2__2_:chany_top_out[19] cby_2__2_:chany_top_out[12] 0.0001422469 +5 sb_2__2_:chany_bottom_in[19] sb_2__2_:chany_bottom_in[12] 0.0001422469 + +*RES +0 cby_2__2_:chany_top_out[19] sb_2__2_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_2_[0] 0.001231423 //LENGTH 7.660 LUMPCC 0.000695502 DR + +*CONN +*I cby_2__2_:left_grid_pin_2_[0] O *L 0 *C 809.750 767.040 +*I grid_clb_2__2_:right_width_0_height_0__pin_2_[0] I *L 0 *C 802.090 767.040 + +*CAP +0 cby_2__2_:left_grid_pin_2_[0] 0.0002679606 +1 grid_clb_2__2_:right_width_0_height_0__pin_2_[0] 0.0002679606 +2 cby_2__2_:left_grid_pin_2_[0] cby_2__2_:left_grid_pin_3_[0] 0.0001741351 +3 grid_clb_2__2_:right_width_0_height_0__pin_2_[0] grid_clb_2__2_:right_width_0_height_0__pin_3_[0] 0.0001741351 +4 cby_2__2_:left_grid_pin_2_[0] cby_2__2_:left_grid_pin_7_[0] 0.0001736158 +5 grid_clb_2__2_:right_width_0_height_0__pin_2_[0] grid_clb_2__2_:right_width_0_height_0__pin_7_[0] 0.0001736158 + +*RES +0 cby_2__2_:left_grid_pin_2_[0] grid_clb_2__2_:right_width_0_height_0__pin_2_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_9_[0] 0.001092983 //LENGTH 7.660 LUMPCC 0.0003582822 DR + +*CONN +*I cby_2__2_:left_grid_pin_9_[0] O *L 0 *C 809.750 750.720 +*I grid_clb_2__2_:right_width_0_height_0__pin_9_[0] I *L 0 *C 802.090 750.720 + +*CAP +0 cby_2__2_:left_grid_pin_9_[0] 0.0003673503 +1 grid_clb_2__2_:right_width_0_height_0__pin_9_[0] 0.0003673503 +2 cby_2__2_:left_grid_pin_9_[0] cby_2__2_:left_grid_pin_6_[0] 0.0001791411 +3 grid_clb_2__2_:right_width_0_height_0__pin_9_[0] grid_clb_2__2_:right_width_0_height_0__pin_6_[0] 0.0001791411 + +*RES +0 cby_2__2_:left_grid_pin_9_[0] grid_clb_2__2_:right_width_0_height_0__pin_9_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_42_lower[0] 0.001134118 //LENGTH 11.020 LUMPCC 0.0001114362 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] O *L 0 *C 527.160 380.870 +*I sb_1__0_:left_top_grid_pin_42_[0] I *L 0 *C 527.160 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] 0.000511341 +1 sb_1__0_:left_top_grid_pin_42_[0] 0.000511341 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] 3.525343e-05 +3 sb_1__0_:left_top_grid_pin_42_[0] sb_1__0_:left_top_grid_pin_45_[0] 3.525343e-05 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] 2.046466e-05 +5 sb_1__0_:left_top_grid_pin_42_[0] sb_1__0_:left_top_grid_pin_49_[0] 2.046466e-05 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] sb_1__0_:left_top_grid_pin_42_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_45_lower[0] 0.001200587 //LENGTH 11.020 LUMPCC 0.0003516503 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] O *L 0 *C 524.860 380.870 +*I sb_1__0_:left_top_grid_pin_45_[0] I *L 0 *C 524.860 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] 0.0004244685 +1 sb_1__0_:left_top_grid_pin_45_[0] 0.0004244685 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_42_lower[0] 3.525343e-05 +3 sb_1__0_:left_top_grid_pin_45_[0] sb_1__0_:left_top_grid_pin_42_[0] 3.525343e-05 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0001405717 +5 sb_1__0_:left_top_grid_pin_45_[0] sb_1__0_:left_top_grid_pin_44_[0] 0.0001405717 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] sb_1__0_:left_top_grid_pin_45_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_48_upper[0] 0.001128126 //LENGTH 11.020 LUMPCC 0.0003090526 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_48_upper[0] O *L 0 *C 394.220 380.870 +*I sb_0__0_:right_top_grid_pin_48_[0] I *L 0 *C 394.220 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_48_upper[0] 0.0004095366 +1 sb_0__0_:right_top_grid_pin_48_[0] 0.0004095366 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_48_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] 0.0001545263 +3 sb_0__0_:right_top_grid_pin_48_[0] sb_0__0_:right_top_grid_pin_49_[0] 0.0001545263 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_48_upper[0] sb_0__0_:right_top_grid_pin_48_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_51_[0] 0.000583813 //LENGTH 4.950 LUMPCC 0 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_51_[0] O *L 0 *C 516.120 380.835 +*I direct_interc_5_\/FTB_6__5:A I *L 0.001746 *C 518.420 379.440 +*N grid_clb_0_bottom_width_0_height_0__pin_51_[0]:2 *C 518.420 379.440 +*N grid_clb_0_bottom_width_0_height_0__pin_51_[0]:3 *C 518.420 379.100 +*N grid_clb_0_bottom_width_0_height_0__pin_51_[0]:4 *C 516.165 379.100 +*N grid_clb_0_bottom_width_0_height_0__pin_51_[0]:5 *C 516.120 379.145 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_51_[0] 0.000101321 +1 direct_interc_5_\/FTB_6__5:A 1e-06 +2 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:2 5.375298e-05 +3 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:3 0.0001764443 +4 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:4 0.0001499737 +5 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:5 0.000101321 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_51_[0] grid_clb_0_bottom_width_0_height_0__pin_51_[0]:5 0.001508929 +1 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:4 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:3 0.002013393 +2 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:5 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:4 0.0045 +3 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:2 direct_interc_5_\/FTB_6__5:A 0.152 +4 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:3 grid_clb_0_bottom_width_0_height_0__pin_51_[0]:2 0.0003035715 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_34_upper[0] 0.001422289 //LENGTH 7.660 LUMPCC 0.000376608 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] O *L 0 *C 540.810 537.880 +*I sb_1__1_:bottom_left_grid_pin_34_[0] I *L 0 *C 548.470 537.880 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] 0.0005228408 +1 sb_1__1_:bottom_left_grid_pin_34_[0] 0.0005228408 +2 grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_35_upper[0] 6.537135e-05 +3 sb_1__1_:bottom_left_grid_pin_34_[0] sb_1__1_:bottom_left_grid_pin_35_[0] 6.537135e-05 +4 grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] 0.0001229326 +5 sb_1__1_:bottom_left_grid_pin_34_[0] sb_1__1_:bottom_left_grid_pin_39_[0] 0.0001229326 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] sb_1__1_:bottom_left_grid_pin_34_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_39_upper[0] 0.001468949 //LENGTH 7.660 LUMPCC 0.000479449 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] O *L 0 *C 540.810 539.240 +*I sb_1__1_:bottom_left_grid_pin_39_[0] I *L 0 *C 548.470 539.240 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] 0.0004947502 +1 sb_1__1_:bottom_left_grid_pin_39_[0] 0.0004947502 +2 grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_34_upper[0] 0.0001229326 +3 sb_1__1_:bottom_left_grid_pin_39_[0] sb_1__1_:bottom_left_grid_pin_34_[0] 0.0001229326 +4 grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] 0.0001167919 +5 sb_1__1_:bottom_left_grid_pin_39_[0] sb_1__1_:bottom_left_grid_pin_40_[0] 0.0001167919 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] sb_1__1_:bottom_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_42_lower[0] 0.001116077 //LENGTH 11.020 LUMPCC 0.0001297981 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] O *L 0 *C 527.160 641.990 +*I sb_1__1_:left_top_grid_pin_42_[0] I *L 0 *C 527.160 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] 0.0004931395 +1 sb_1__1_:left_top_grid_pin_42_[0] 0.0004931395 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] 4.079689e-05 +3 sb_1__1_:left_top_grid_pin_42_[0] sb_1__1_:left_top_grid_pin_45_[0] 4.079689e-05 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_49_lower[0] 2.410214e-05 +5 sb_1__1_:left_top_grid_pin_42_[0] sb_1__1_:left_top_grid_pin_49_[0] 2.410214e-05 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] sb_1__1_:left_top_grid_pin_42_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_46_lower[0] 0.001198478 //LENGTH 11.020 LUMPCC 0.0003548463 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] O *L 0 *C 522.100 641.990 +*I sb_1__1_:left_top_grid_pin_46_[0] I *L 0 *C 522.100 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] 0.0004218159 +1 sb_1__1_:left_top_grid_pin_46_[0] 0.0004218159 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] direct_interc_3_out[0]:11 3.758868e-05 +3 sb_1__1_:left_top_grid_pin_46_[0] direct_interc_3_out[0]:10 3.758868e-05 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0001398345 +5 sb_1__1_:left_top_grid_pin_46_[0] sb_1__1_:left_top_grid_pin_47_[0] 0.0001398345 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] sb_1__1_:left_top_grid_pin_46_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_49_upper[0] 0.001244499 //LENGTH 11.020 LUMPCC 0.0005802696 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] O *L 0 *C 395.140 641.990 +*I sb_0__1_:right_top_grid_pin_49_[0] I *L 0 *C 395.140 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0003321147 +1 sb_0__1_:right_top_grid_pin_49_[0] 0.0003321147 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0001424192 +3 sb_0__1_:right_top_grid_pin_49_[0] sb_0__1_:right_top_grid_pin_45_[0] 0.0001424192 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_48_upper[0] 0.0001477156 +5 sb_0__1_:right_top_grid_pin_49_[0] sb_0__1_:right_top_grid_pin_48_[0] 0.0001477156 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] sb_0__1_:right_top_grid_pin_49_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_37_upper[0] 0.001538984 //LENGTH 7.660 LUMPCC 0.0003397268 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] O *L 0 *C 540.810 792.200 +*I sb_1__2_:bottom_left_grid_pin_37_[0] I *L 0 *C 548.470 792.200 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] 0.0005996288 +1 sb_1__2_:bottom_left_grid_pin_37_[0] 0.0005996288 +2 grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] 0.0001091972 +3 sb_1__2_:bottom_left_grid_pin_37_[0] sb_1__2_:bottom_left_grid_pin_38_[0] 0.0001091972 +4 grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_41_upper[0] 6.066622e-05 +5 sb_1__2_:bottom_left_grid_pin_37_[0] grid_clb_1_right_width_0_height_0__pin_41_upper[0]:5 6.066622e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] sb_1__2_:bottom_left_grid_pin_37_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_40_upper[0] 0.001532141 //LENGTH 7.660 LUMPCC 0.0003113699 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] O *L 0 *C 540.810 801.720 +*I sb_1__2_:bottom_left_grid_pin_40_[0] I *L 0 *C 548.470 801.720 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] 0.0006103857 +1 sb_1__2_:bottom_left_grid_pin_40_[0] 0.0006103857 +2 grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_39_upper[0] 9.956743e-05 +3 sb_1__2_:bottom_left_grid_pin_40_[0] sb_1__2_:bottom_left_grid_pin_39_[0] 9.956743e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] grid_clb_1_right_width_0_height_0__pin_41_upper[0]:2 5.611754e-05 +5 sb_1__2_:bottom_left_grid_pin_40_[0] sb_1__2_:bottom_left_grid_pin_41_[0] 5.611754e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_40_upper[0] sb_1__2_:bottom_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_43_upper[0] 0.0009782736 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_43_upper[0] O *L 0 *C 640.470 393.040 +*I sb_1__0_:right_top_grid_pin_43_[0] I *L 0 *C 632.810 393.040 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_43_upper[0] 0.0004891368 +1 sb_1__0_:right_top_grid_pin_43_[0] 0.0004891368 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_43_upper[0] sb_1__0_:right_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_46_upper[0] 0.001894607 //LENGTH 10.220 LUMPCC 0.0007986385 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_46_upper[0] O *L 0 *C 640.470 385.560 +*I sb_1__0_:right_top_grid_pin_46_[0] I *L 0 *C 632.810 385.560 +*N grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 *C 633.420 385.560 +*N grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 *C 633.420 384.880 +*N grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 *C 638.940 384.880 +*N grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 *C 638.940 385.560 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_46_upper[0] 0.0001309352 +1 sb_1__0_:right_top_grid_pin_46_[0] 9.544256e-05 +2 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 0.0001218419 +3 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 0.0002743706 +4 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 0.0002952069 +5 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 0.000178171 +6 grid_clb_2__1_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] 1.506677e-05 +7 sb_1__0_:right_top_grid_pin_46_[0] sb_1__0_:right_top_grid_pin_47_[0] 2.415562e-06 +8 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] 2.415562e-06 +9 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 sb_1__0_:right_top_grid_pin_47_[0] 0.0003460826 +10 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 grid_clb_2__1_:bottom_width_0_height_0__pin_47_upper[0] 0.0003460826 +11 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 sb_1__0_:right_top_grid_pin_47_[0] 1.506677e-05 +12 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 ctsbuf_net_817:18 3.575435e-05 +13 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 ctsbuf_net_817:17 3.575435e-05 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_46_upper[0] grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 0.0002397 +1 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 sb_1__0_:right_top_grid_pin_46_[0] 9.556666e-05 +2 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:2 0.0001065333 +3 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:3 0.0008647999 +4 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:5 grid_clb_2_bottom_width_0_height_0__pin_46_upper[0]:4 0.0001065333 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_35_lower[0] 0.002006958 //LENGTH 18.390 LUMPCC 0.0007060703 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] O *L 0 *C 802.090 405.280 +*I sb_2__0_:top_left_grid_pin_35_[0] I *L 0 *C 811.900 397.050 +*N grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 *C 811.900 405.223 +*N grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 *C 811.893 405.280 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] 0.000290279 +1 sb_2__0_:top_left_grid_pin_35_[0] 0.0003601646 +2 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 0.0003601646 +3 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 0.000290279 +4 grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] 0.0002570318 +5 sb_2__0_:top_left_grid_pin_35_[0] sb_2__0_:top_left_grid_pin_34_[0] 4.217083e-05 +6 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 4.217083e-05 +7 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 0.0002570318 +8 grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] ctsbuf_net_110:11 3.504183e-05 +9 sb_2__0_:top_left_grid_pin_35_[0] ctsbuf_net_110:12 1.045257e-05 +10 sb_2__0_:top_left_grid_pin_35_[0] ctsbuf_net_110:5 8.338122e-06 +11 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 ctsbuf_net_110:12 8.338122e-06 +12 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 ctsbuf_net_110:13 1.045257e-05 +13 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 ctsbuf_net_110:10 3.504183e-05 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 0.001535725 +1 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 sb_2__0_:top_left_grid_pin_35_[0] 0.007296876 +2 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 0.00341 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_40_lower[0] 0.001091166 //LENGTH 7.660 LUMPCC 0.0005370394 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] O *L 0 *C 802.090 388.960 +*I sb_2__0_:top_left_grid_pin_40_[0] I *L 0 *C 809.750 388.960 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] 0.0002770633 +1 sb_2__0_:top_left_grid_pin_40_[0] 0.0002770633 +2 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] 4.933096e-05 +3 sb_2__0_:top_left_grid_pin_40_[0] sb_2__0_:left_top_grid_pin_43_[0] 4.933096e-05 +4 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 3.461167e-05 +5 sb_2__0_:top_left_grid_pin_40_[0] sb_2__0_:top_left_grid_pin_36_[0] 3.461167e-05 +6 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] 0.000184577 +7 sb_2__0_:top_left_grid_pin_40_[0] sb_2__0_:top_left_grid_pin_39_[0] 0.000184577 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] sb_2__0_:top_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_46_lower[0] 0.00120471 //LENGTH 11.020 LUMPCC 0.0004266574 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] O *L 0 *C 783.380 641.990 +*I sb_2__1_:left_top_grid_pin_46_[0] I *L 0 *C 783.380 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] 0.0003890265 +1 sb_2__1_:left_top_grid_pin_46_[0] 0.0003890265 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] direct_interc_4_out[0]:11 7.095894e-05 +3 sb_2__1_:left_top_grid_pin_46_[0] direct_interc_4_out[0]:10 7.095894e-05 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0001423698 +5 sb_2__1_:left_top_grid_pin_46_[0] sb_2__1_:left_top_grid_pin_47_[0] 0.0001423698 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] sb_2__1_:left_top_grid_pin_46_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_ccff_tail[0] 0.0009828152 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_2__2_:ccff_tail[0] O *L 0 *C 802.090 682.720 +*I cby_2__2_:ccff_head[0] I *L 0 *C 809.750 682.720 + +*CAP +0 grid_clb_2__2_:ccff_tail[0] 0.0004914076 +1 cby_2__2_:ccff_head[0] 0.0004914076 + +*RES +0 grid_clb_2__2_:ccff_tail[0] cby_2__2_:ccff_head[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_35_lower[0] 0.001941565 //LENGTH 19.100 LUMPCC 0.0004705245 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_35_lower[0] O *L 0 *C 802.090 666.400 +*I sb_2__1_:top_left_grid_pin_35_[0] I *L 0 *C 811.900 658.170 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 *C 811.900 663.623 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 *C 811.893 663.680 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 *C 805.940 663.680 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:5 *C 805.920 663.688 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:6 *C 805.920 666.393 +*N grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 *C 805.900 666.400 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_35_lower[0] 0.0001509349 +1 sb_2__1_:top_left_grid_pin_35_[0] 0.0002428422 +2 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 0.0002428422 +3 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 0.0001934766 +4 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 0.0001934766 +5 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:5 0.0001482665 +6 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:6 0.0001482665 +7 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 0.0001509349 +8 grid_clb_2__2_:right_width_0_height_0__pin_35_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] 0.0001040524 +9 sb_2__1_:top_left_grid_pin_35_[0] sb_2__1_:top_left_grid_pin_34_[0] 2.707244e-05 +10 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 2.707244e-05 +11 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 4.562606e-05 +12 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] 4.562606e-05 +13 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 0.0001040524 +14 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 ctsbuf_net_1221:12 5.851133e-05 +15 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 ctsbuf_net_1221:13 5.851133e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_35_lower[0] grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 0.0005968999 +1 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 sb_2__1_:top_left_grid_pin_35_[0] 0.004868304 +2 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:2 0.00341 +3 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:3 0.0009325583 +4 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:4 0.00341 +5 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:7 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:6 0.00341 +6 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:6 grid_clb_3_right_width_0_height_0__pin_35_lower[0]:5 0.0004237833 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_40_upper[0] 0.001235338 //LENGTH 7.660 LUMPCC 0.0004795851 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] O *L 0 *C 802.090 801.720 +*I sb_2__2_:bottom_left_grid_pin_40_[0] I *L 0 *C 809.750 801.720 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] 0.0003778764 +1 sb_2__2_:bottom_left_grid_pin_40_[0] 0.0003778764 +2 grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_39_upper[0] 0.000159394 +3 sb_2__2_:bottom_left_grid_pin_40_[0] sb_2__2_:bottom_left_grid_pin_39_[0] 0.000159394 +4 grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] grid_clb_3_right_width_0_height_0__pin_41_upper[0]:2 8.039849e-05 +5 sb_2__2_:bottom_left_grid_pin_40_[0] sb_2__2_:bottom_left_grid_pin_41_[0] 8.039849e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_40_upper[0] sb_2__2_:bottom_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_io_left_0_right_width_0_height_0__pin_1_upper[0] 0.003251364 //LENGTH 30.520 LUMPCC 0.0001600322 DR + +*CONN +*I grid_io_left_0__1_:right_width_0_height_0__pin_1_upper[0] O *L 0 *C 270.480 516.730 +*I sb_0__1_:bottom_left_grid_pin_1_[0] I *L 0 *C 289.340 527.750 +*N grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:2 *C 289.340 521.265 +*N grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 *C 289.295 521.220 +*N grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 *C 270.525 521.220 +*N grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:5 *C 270.480 521.175 + +*CAP +0 grid_io_left_0__1_:right_width_0_height_0__pin_1_upper[0] 0.0002579654 +1 sb_0__1_:bottom_left_grid_pin_1_[0] 0.0003378476 +2 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:2 0.0003378476 +3 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 0.0009498527 +4 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 0.0009498527 +5 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:5 0.0002579654 +6 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 ropt_net_31:2 3.696381e-05 +7 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 ropt_net_31:3 3.696381e-05 +8 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 ropt_net_32:7 4.30523e-05 +9 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 ropt_net_32:6 4.30523e-05 + +*RES +0 grid_io_left_0__1_:right_width_0_height_0__pin_1_upper[0] grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:5 0.00396875 +1 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:2 0.0045 +2 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:2 sb_0__1_:bottom_left_grid_pin_1_[0] 0.005790179 +3 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 0.01675893 +4 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:5 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 0.0045 + +*END + +*D_NET grid_io_right_0_left_width_0_height_0__pin_1_upper[0] 0.002980862 //LENGTH 30.980 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__1_:left_width_0_height_0__pin_1_upper[0] O *L 0 *C 911.260 516.730 +*I sb_2__1_:bottom_right_grid_pin_1_[0] I *L 0 *C 891.940 527.750 +*N grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:2 *C 891.940 520.925 +*N grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:3 *C 891.985 520.880 +*N grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:4 *C 911.215 520.880 +*N grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:5 *C 911.260 520.835 + +*CAP +0 grid_io_right_3__1_:left_width_0_height_0__pin_1_upper[0] 0.0002393388 +1 sb_2__1_:bottom_right_grid_pin_1_[0] 0.0003361126 +2 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:2 0.0003361126 +3 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:3 0.0009149794 +4 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:4 0.0009149794 +5 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:5 0.0002393388 + +*RES +0 grid_io_right_3__1_:left_width_0_height_0__pin_1_upper[0] grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:5 0.003665179 +1 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:3 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:2 0.0045 +2 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:2 sb_2__1_:bottom_right_grid_pin_1_[0] 0.00609375 +3 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:4 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:3 0.01716965 +4 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:5 grid_io_right_0_left_width_0_height_0__pin_1_upper[0]:4 0.0045 + +*END + +*D_NET grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0] 0.003156211 //LENGTH 27.910 LUMPCC 0.001100879 DR + +*CONN +*I grid_io_top_2__3_:bottom_width_0_height_0__pin_1_upper[0] O *L 0 *C 668.990 909.840 +*I sb_1__2_:right_top_grid_pin_1_[0] I *L 0 *C 659.180 892.090 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 *C 659.180 909.783 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 *C 659.188 909.840 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 *C 667.519 909.840 +*N grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:5 *C 667.520 909.840 + +*CAP +0 grid_io_top_2__3_:bottom_width_0_height_0__pin_1_upper[0] 0.0002156673 +1 sb_1__2_:right_top_grid_pin_1_[0] 0.0006388363 +2 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 0.0006388363 +3 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 0.0001731622 +4 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 0.0001731622 +5 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:5 0.0002156673 +6 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 grid_io_top_1_ccff_tail[0]:6 0.0002212131 +7 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 grid_io_top_1_ccff_tail[0]:7 0.0002212131 +8 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 ctsbuf_net_514:5 4.218768e-05 +9 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 ctsbuf_net_514:4 4.739757e-05 +10 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 ctsbuf_net_514:4 4.218768e-05 +11 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 ctsbuf_net_514:3 4.739757e-05 +12 sb_1__2_:right_top_grid_pin_1_[0] sb_1__2_:ccff_head[0] 0.0002396411 +13 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 ropt_net_36:2 0.0002396411 + +*RES +0 grid_io_top_2__3_:bottom_width_0_height_0__pin_1_upper[0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:5 0.0002303 +1 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 sb_1__2_:right_top_grid_pin_1_[0] 0.01579688 +2 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 0.00341 +3 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:5 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 1e-05 +4 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:4 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:3 0.001305268 + +*END + +*D_NET sb_0__0__0_chanx_right_out[5] 0.001271571 //LENGTH 7.660 LUMPCC 0.000687296 DR + +*CONN +*I sb_0__0_:chanx_right_out[5] O *L 0 *C 400.050 350.880 +*I cbx_1__0_:chanx_left_in[5] I *L 0 *C 407.710 350.880 + +*CAP +0 sb_0__0_:chanx_right_out[5] 0.0002921373 +1 cbx_1__0_:chanx_left_in[5] 0.0002921373 +2 sb_0__0_:chanx_right_out[5] sb_0__0_:chanx_right_in[19] 0.0001719349 +3 cbx_1__0_:chanx_left_in[5] cbx_1__0_:chanx_left_out[19] 0.0001719349 +4 sb_0__0_:chanx_right_out[5] sb_0__0_:chanx_right_out[11] 0.0001717131 +5 cbx_1__0_:chanx_left_in[5] cbx_1__0_:chanx_left_in[11] 0.0001717131 + +*RES +0 sb_0__0_:chanx_right_out[5] cbx_1__0_:chanx_left_in[5] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[14] 0.00116681 //LENGTH 7.660 LUMPCC 0.0005017172 DR + +*CONN +*I sb_0__0_:chanx_right_out[14] O *L 0 *C 400.050 316.880 +*I cbx_1__0_:chanx_left_in[14] I *L 0 *C 407.710 316.880 + +*CAP +0 sb_0__0_:chanx_right_out[14] 0.0003325462 +1 cbx_1__0_:chanx_left_in[14] 0.0003325462 +2 sb_0__0_:chanx_right_out[14] sb_0__0_:chanx_right_out[10] 0.0001741797 +3 cbx_1__0_:chanx_left_in[14] cbx_1__0_:chanx_left_in[10] 0.0001741797 +4 sb_0__0_:chanx_right_out[14] sb_0__0_:chanx_right_out[18] 7.667893e-05 +5 cbx_1__0_:chanx_left_in[14] cbx_1__0_:chanx_left_in[18] 7.667893e-05 + +*RES +0 sb_0__0_:chanx_right_out[14] cbx_1__0_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[4] 0.001041532 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I sb_0__0_:chany_top_out[4] O *L 0 *C 323.380 397.050 +*I cby_0__1_:chany_bottom_in[4] I *L 0 *C 323.380 408.070 + +*CAP +0 sb_0__0_:chany_top_out[4] 0.000520766 +1 cby_0__1_:chany_bottom_in[4] 0.000520766 + +*RES +0 sb_0__0_:chany_top_out[4] cby_0__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET sb_0__0__0_chany_top_out[7] 0.001226475 //LENGTH 11.180 LUMPCC 0 DR + +*CONN +*I sb_0__0_:chany_top_out[7] O *L 0 *C 356.040 396.970 +*I cby_0__1_:chany_bottom_in[7] I *L 0 *C 356.040 408.150 + +*CAP +0 sb_0__0_:chany_top_out[7] 0.0006132373 +1 cby_0__1_:chany_bottom_in[7] 0.0006132373 + +*RES +0 sb_0__0_:chany_top_out[7] cby_0__1_:chany_bottom_in[7] 0.001751533 + +*END + +*D_NET sb_0__0__0_chany_top_out[11] 0.00122511 //LENGTH 11.020 LUMPCC 0.0006079205 DR + +*CONN +*I sb_0__0_:chany_top_out[11] O *L 0 *C 338.100 397.050 +*I cby_0__1_:chany_bottom_in[11] I *L 0 *C 338.100 408.070 + +*CAP +0 sb_0__0_:chany_top_out[11] 0.0003085948 +1 cby_0__1_:chany_bottom_in[11] 0.0003085948 +2 sb_0__0_:chany_top_out[11] sb_0__0_:chany_top_in[9] 0.0001519801 +3 cby_0__1_:chany_bottom_in[11] cby_0__1_:chany_bottom_out[9] 0.0001519801 +4 sb_0__0_:chany_top_out[11] sb_0__0_:chany_top_in[10] 0.0001519801 +5 cby_0__1_:chany_bottom_in[11] cby_0__1_:chany_bottom_out[10] 0.0001519801 + +*RES +0 sb_0__0_:chany_top_out[11] cby_0__1_:chany_bottom_in[11] 0.009839285 + +*END + +*D_NET sb_0__1__0_chanx_right_out[0] 0.001267733 //LENGTH 7.660 LUMPCC 0.0006890686 DR + +*CONN +*I sb_0__1_:chanx_right_out[0] O *L 0 *C 400.050 612.000 +*I cbx_1__1_:chanx_left_in[0] I *L 0 *C 407.710 612.000 + +*CAP +0 sb_0__1_:chanx_right_out[0] 0.0002893321 +1 cbx_1__1_:chanx_left_in[0] 0.0002893321 +2 sb_0__1_:chanx_right_out[0] sb_0__1_:chanx_right_out[1] 0.0001722672 +3 cbx_1__1_:chanx_left_in[0] cbx_1__1_:chanx_left_in[1] 0.0001722672 +4 sb_0__1_:chanx_right_out[0] sb_0__1_:chanx_right_out[13] 0.0001722672 +5 cbx_1__1_:chanx_left_in[0] cbx_1__1_:chanx_left_in[13] 0.0001722672 + +*RES +0 sb_0__1_:chanx_right_out[0] cbx_1__1_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[9] 0.001211351 //LENGTH 7.660 LUMPCC 0.0005982735 DR + +*CONN +*I sb_0__1_:chanx_right_out[9] O *L 0 *C 400.050 591.600 +*I cbx_1__1_:chanx_left_in[9] I *L 0 *C 407.710 591.600 + +*CAP +0 sb_0__1_:chanx_right_out[9] 0.0003065389 +1 cbx_1__1_:chanx_left_in[9] 0.0003065389 +2 sb_0__1_:chanx_right_out[9] sb_0__1_:chanx_right_in[18] 7.776741e-05 +3 cbx_1__1_:chanx_left_in[9] cbx_1__1__0_chanx_left_out[18]:2 7.776741e-05 +4 sb_0__1_:chanx_right_out[9] sb_0__1_:chanx_right_out[2] 0.0001729695 +5 cbx_1__1_:chanx_left_in[9] cbx_1__1_:chanx_left_in[2] 0.0001729695 +6 sb_0__1_:chanx_right_out[9] sb_0__1_:chanx_right_out[17] 4.839982e-05 +7 cbx_1__1_:chanx_left_in[9] cbx_1__1_:chanx_left_in[17] 4.839982e-05 + +*RES +0 sb_0__1_:chanx_right_out[9] cbx_1__1_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[16] 0.001288805 //LENGTH 7.660 LUMPCC 0.0006468669 DR + +*CONN +*I sb_0__1_:chanx_right_out[16] O *L 0 *C 400.050 568.480 +*I cbx_1__1_:chanx_left_in[16] I *L 0 *C 407.710 568.480 + +*CAP +0 sb_0__1_:chanx_right_out[16] 0.0003209689 +1 cbx_1__1_:chanx_left_in[16] 0.0003209689 +2 sb_0__1_:chanx_right_out[16] sb_0__1_:chanx_right_in[16] 0.0001617167 +3 cbx_1__1_:chanx_left_in[16] cbx_1__1_:chanx_left_out[16] 0.0001617167 +4 sb_0__1_:chanx_right_out[16] sb_0__1_:chanx_right_out[12] 0.0001617167 +5 cbx_1__1_:chanx_left_in[16] cbx_1__1_:chanx_left_in[12] 0.0001617167 + +*RES +0 sb_0__1_:chanx_right_out[16] cbx_1__1_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[5] 0.001293099 //LENGTH 11.020 LUMPCC 0.0005139186 DR + +*CONN +*I sb_0__1_:chany_bottom_out[5] O *L 0 *C 332.580 527.750 +*I cby_0__1_:chany_top_in[5] I *L 0 *C 332.580 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[5] 0.0003895902 +1 cby_0__1_:chany_top_in[5] 0.0003895902 +2 sb_0__1_:chany_bottom_out[5] sb_0__1_:chany_bottom_in[15] 0.0001284796 +3 cby_0__1_:chany_top_in[5] cby_0__1_:chany_top_out[15] 0.0001284796 +4 sb_0__1_:chany_bottom_out[5] sb_0__1_:chany_bottom_out[3] 0.0001284796 +5 cby_0__1_:chany_top_in[5] cby_0__1_:chany_top_in[3] 0.0001284796 + +*RES +0 sb_0__1_:chany_bottom_out[5] cby_0__1_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[12] 0.001286253 //LENGTH 11.020 LUMPCC 0.0005176135 DR + +*CONN +*I sb_0__1_:chany_bottom_out[12] O *L 0 *C 354.660 527.750 +*I cby_0__1_:chany_top_in[12] I *L 0 *C 354.660 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[12] 0.0003843199 +1 cby_0__1_:chany_top_in[12] 0.0003843199 +2 sb_0__1_:chany_bottom_out[12] sb_0__1_:chany_bottom_out[2] 0.0001295745 +3 cby_0__1_:chany_top_in[12] cby_0__1_:chany_top_in[2] 0.0001295745 +4 sb_0__1_:chany_bottom_out[12] sb_0__1_:chany_bottom_out[7] 0.0001292323 +5 cby_0__1_:chany_top_in[12] cby_0__1_:chany_top_in[7] 0.0001292323 + +*RES +0 sb_0__1_:chany_bottom_out[12] cby_0__1_:chany_top_in[12] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_top_out[1] 0.001087498 //LENGTH 11.020 LUMPCC 0.0001614583 DR + +*CONN +*I sb_0__1_:chany_top_out[1] O *L 0 *C 312.800 658.170 +*I cby_0__2_:chany_bottom_in[1] I *L 0 *C 312.800 669.190 +*N sb_0__1__0_chany_top_out[1]:2 *C 312.800 667.520 +*N sb_0__1__0_chany_top_out[1]:3 *C 312.800 667.519 + +*CAP +0 sb_0__1_:chany_top_out[1] 0.0003372827 +1 cby_0__2_:chany_bottom_in[1] 0.0001257373 +2 sb_0__1__0_chany_top_out[1]:2 0.0001257373 +3 sb_0__1__0_chany_top_out[1]:3 0.0003372827 +4 sb_0__1_:chany_top_out[1] sb_0__1_:chany_top_in[5] 2.407552e-05 +5 sb_0__1__0_chany_top_out[1]:3 cby_0__1__1_chany_bottom_out[5]:2 2.407552e-05 +6 sb_0__1_:chany_top_out[1] sb_0__1_:chany_top_out[19] 5.665364e-05 +7 sb_0__1__0_chany_top_out[1]:3 sb_0__1__0_chany_top_out[19]:3 5.665364e-05 + +*RES +0 sb_0__1_:chany_top_out[1] sb_0__1__0_chany_top_out[1]:3 0.008347322 +1 sb_0__1__0_chany_top_out[1]:2 cby_0__2_:chany_bottom_in[1] 0.001491071 +2 sb_0__1__0_chany_top_out[1]:3 sb_0__1__0_chany_top_out[1]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[10] 0.001269324 //LENGTH 11.020 LUMPCC 0.0005516617 DR + +*CONN +*I sb_0__1_:chany_top_out[10] O *L 0 *C 333.500 658.170 +*I cby_0__2_:chany_bottom_in[10] I *L 0 *C 333.500 669.190 +*N sb_0__1__0_chany_top_out[10]:2 *C 333.500 667.520 +*N sb_0__1__0_chany_top_out[10]:3 *C 333.500 667.519 + +*CAP +0 sb_0__1_:chany_top_out[10] 0.0002472905 +1 cby_0__2_:chany_bottom_in[10] 0.0001115404 +2 sb_0__1__0_chany_top_out[10]:2 0.0001115404 +3 sb_0__1__0_chany_top_out[10]:3 0.0002472905 +4 sb_0__1_:chany_top_out[10] sb_0__1_:chany_top_in[3] 0.0001307218 +5 cby_0__2_:chany_bottom_in[10] cby_0__2_:chany_bottom_out[3] 7.193657e-06 +6 sb_0__1__0_chany_top_out[10]:2 cby_0__1__1_chany_bottom_out[3]:3 7.193657e-06 +7 sb_0__1__0_chany_top_out[10]:3 cby_0__1__1_chany_bottom_out[3]:2 0.0001307218 +8 sb_0__1_:chany_top_out[10] sb_0__1_:chany_top_in[19] 0.0001307218 +9 cby_0__2_:chany_bottom_in[10] cby_0__2_:chany_bottom_out[19] 7.193657e-06 +10 sb_0__1__0_chany_top_out[10]:2 cby_0__1__1_chany_bottom_out[19]:3 7.193657e-06 +11 sb_0__1__0_chany_top_out[10]:3 cby_0__1__1_chany_bottom_out[19]:2 0.0001307218 + +*RES +0 sb_0__1_:chany_top_out[10] sb_0__1__0_chany_top_out[10]:3 0.008347321 +1 sb_0__1__0_chany_top_out[10]:2 cby_0__2_:chany_bottom_in[10] 0.001491072 +2 sb_0__1__0_chany_top_out[10]:3 sb_0__1__0_chany_top_out[10]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[19] 0.001673634 //LENGTH 11.180 LUMPCC 0.0006171641 DR + +*CONN +*I sb_0__1_:chany_top_out[19] O *L 0 *C 312.800 658.090 +*I cby_0__2_:chany_bottom_in[19] I *L 0 *C 312.800 669.270 +*N sb_0__1__0_chany_top_out[19]:2 *C 312.800 667.520 +*N sb_0__1__0_chany_top_out[19]:3 *C 312.800 667.519 + +*CAP +0 sb_0__1_:chany_top_out[19] 0.0003127486 +1 cby_0__2_:chany_bottom_in[19] 0.0002154864 +2 sb_0__1__0_chany_top_out[19]:2 0.0002154864 +3 sb_0__1__0_chany_top_out[19]:3 0.0003127486 +4 sb_0__1_:chany_top_out[19] sb_0__1_:chany_top_in[5] 2.758333e-05 +5 sb_0__1__0_chany_top_out[19]:3 cby_0__1__1_chany_bottom_out[5]:2 2.758333e-05 +6 sb_0__1_:chany_top_out[19] sb_0__1_:chany_top_out[1] 5.665364e-05 +7 sb_0__1__0_chany_top_out[19]:3 sb_0__1__0_chany_top_out[1]:3 5.665364e-05 +8 sb_0__1_:chany_top_out[19] sb_0__1_:chany_top_out[13] 0.0002153793 +9 cby_0__2_:chany_bottom_in[19] cby_0__2_:chany_bottom_in[13] 8.965721e-06 +10 sb_0__1__0_chany_top_out[19]:2 sb_0__1__0_chany_top_out[13]:2 8.965721e-06 +11 sb_0__1__0_chany_top_out[19]:3 sb_0__1__0_chany_top_out[13]:3 0.0002153793 + +*RES +0 sb_0__1_:chany_top_out[19] sb_0__1__0_chany_top_out[19]:3 0.00147721 +1 sb_0__1__0_chany_top_out[19]:2 cby_0__2_:chany_bottom_in[19] 0.0002741667 +2 sb_0__1__0_chany_top_out[19]:3 sb_0__1__0_chany_top_out[19]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[7] 0.001241364 //LENGTH 7.660 LUMPCC 0.0004286353 DR + +*CONN +*I sb_0__2_:chanx_right_out[7] O *L 0 *C 400.050 882.640 +*I cbx_1__2_:chanx_left_in[7] I *L 0 *C 407.710 882.640 + +*CAP +0 sb_0__2_:chanx_right_out[7] 0.0004063645 +1 cbx_1__2_:chanx_left_in[7] 0.0004063645 +2 sb_0__2_:chanx_right_out[7] sb_0__2_:chanx_right_out[5] 0.0001602041 +3 cbx_1__2_:chanx_left_in[7] cbx_1__2_:chanx_left_in[5] 0.0001602041 +4 sb_0__2_:chanx_right_out[7] sb_0__2_:chanx_right_out[14] 5.411359e-05 +5 cbx_1__2_:chanx_left_in[7] cbx_1__2_:chanx_left_in[14] 5.411359e-05 + +*RES +0 sb_0__2_:chanx_right_out[7] cbx_1__2_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[13] 0.001215359 //LENGTH 7.660 LUMPCC 0.0004665744 DR + +*CONN +*I sb_0__2_:chanx_right_out[13] O *L 0 *C 400.050 855.440 +*I cbx_1__2_:chanx_left_in[13] I *L 0 *C 407.710 855.440 + +*CAP +0 sb_0__2_:chanx_right_out[13] 0.0003743921 +1 cbx_1__2_:chanx_left_in[13] 0.0003743921 +2 sb_0__2_:chanx_right_out[13] sb_0__2_:chanx_right_out[15] 0.0001646984 +3 cbx_1__2_:chanx_left_in[13] cbx_1__2_:chanx_left_in[15] 0.0001646984 +4 sb_0__2_:chanx_right_out[13] sb_0__2_:chanx_right_out[16] 6.858881e-05 +5 cbx_1__2_:chanx_left_in[13] cbx_1__2_:chanx_left_in[16] 6.858881e-05 + +*RES +0 sb_0__2_:chanx_right_out[13] cbx_1__2_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[3] 0.001268302 //LENGTH 11.020 LUMPCC 0.0005649903 DR + +*CONN +*I sb_0__2_:chany_bottom_out[3] O *L 0 *C 331.660 788.870 +*I cby_0__2_:chany_top_in[3] I *L 0 *C 331.660 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[3] 0.0003516559 +1 cby_0__2_:chany_top_in[3] 0.0003516559 +2 sb_0__2_:chany_bottom_out[3] sb_0__2_:chany_bottom_in[14] 0.0001440134 +3 cby_0__2_:chany_top_in[3] cby_0__2_:chany_top_out[14] 0.0001440134 +4 sb_0__2_:chany_bottom_out[3] sb_0__2_:chany_bottom_out[5] 0.0001384818 +5 cby_0__2_:chany_top_in[3] cby_0__2_:chany_top_in[5] 0.0001384818 + +*RES +0 sb_0__2_:chany_bottom_out[3] cby_0__2_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[11] 0.001268302 //LENGTH 11.020 LUMPCC 0.000553927 DR + +*CONN +*I sb_0__2_:chany_bottom_out[11] O *L 0 *C 335.340 788.870 +*I cby_0__2_:chany_top_in[11] I *L 0 *C 335.340 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[11] 0.0003571876 +1 cby_0__2_:chany_top_in[11] 0.0003571876 +2 sb_0__2_:chany_bottom_out[11] sb_0__2_:chany_bottom_in[5] 0.0001384818 +3 cby_0__2_:chany_top_in[11] cby_0__2_:chany_top_out[5] 0.0001384818 +4 sb_0__2_:chany_bottom_out[11] sb_0__2_:chany_bottom_out[17] 0.0001384818 +5 cby_0__2_:chany_top_in[11] cby_0__2_:chany_top_in[17] 0.0001384818 + +*RES +0 sb_0__2_:chany_bottom_out[11] cby_0__2_:chany_top_in[11] 0.009839286 + +*END + +*D_NET sb_1__0__0_chanx_left_out[2] 0.001207934 //LENGTH 7.660 LUMPCC 0.0002373811 DR + +*CONN +*I sb_1__0_:chanx_left_out[2] O *L 0 *C 519.950 309.400 +*I cbx_1__0_:chanx_right_in[2] I *L 0 *C 512.290 309.400 + +*CAP +0 sb_1__0_:chanx_left_out[2] 0.0004852766 +1 cbx_1__0_:chanx_right_in[2] 0.0004852766 +2 sb_1__0_:chanx_left_out[2] sb_1__0_:chanx_left_out[4] 3.015819e-05 +3 cbx_1__0_:chanx_right_in[2] cbx_1__0_:chanx_right_in[4] 3.015819e-05 +4 sb_1__0_:chanx_left_out[2] sb_1__0_:chanx_left_out[14] 8.853238e-05 +5 cbx_1__0_:chanx_right_in[2] cbx_1__0_:chanx_right_in[14] 8.853238e-05 + +*RES +0 sb_1__0_:chanx_left_out[2] cbx_1__0_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[10] 0.001279 //LENGTH 7.660 LUMPCC 0.0005132931 DR + +*CONN +*I sb_1__0_:chanx_left_out[10] O *L 0 *C 519.950 314.160 +*I cbx_1__0_:chanx_right_in[10] I *L 0 *C 512.290 314.160 + +*CAP +0 sb_1__0_:chanx_left_out[10] 0.0003828536 +1 cbx_1__0_:chanx_right_in[10] 0.0003828536 +2 sb_1__0_:chanx_left_out[10] sb_1__0_:chanx_left_in[17] 6.937591e-05 +3 cbx_1__0_:chanx_right_in[10] cbx_1__0__0_chanx_right_out[17]:2 6.937591e-05 +4 sb_1__0_:chanx_left_out[10] sb_1__0_:chanx_left_out[8] 0.0001625319 +5 cbx_1__0_:chanx_right_in[10] cbx_1__0_:chanx_right_in[8] 0.0001625319 +6 sb_1__0_:chanx_left_out[10] sb_1__0_:chanx_left_out[14] 2.473871e-05 +7 cbx_1__0_:chanx_right_in[10] cbx_1__0_:chanx_right_in[14] 2.473871e-05 + +*RES +0 sb_1__0_:chanx_left_out[10] cbx_1__0_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[1] 0.001326731 //LENGTH 7.660 LUMPCC 0.0004135623 DR + +*CONN +*I sb_1__0_:chanx_right_out[1] O *L 0 *C 661.330 360.400 +*I cbx_2__0_:chanx_left_in[1] I *L 0 *C 668.990 360.400 +*N sb_1__0__0_chanx_right_out[1]:2 *C 667.520 360.400 +*N sb_1__0__0_chanx_right_out[1]:3 *C 667.519 360.400 + +*CAP +0 sb_1__0_:chanx_right_out[1] 0.0002725442 +1 cbx_2__0_:chanx_left_in[1] 0.0001840399 +2 sb_1__0__0_chanx_right_out[1]:2 0.0001840399 +3 sb_1__0__0_chanx_right_out[1]:3 0.0002725442 +4 sb_1__0_:chanx_right_out[1] sb_1__0_:chanx_right_in[17] 6.395851e-05 +5 sb_1__0__0_chanx_right_out[1]:3 cbx_1__0__1_chanx_left_out[17]:2 6.395851e-05 +6 sb_1__0_:chanx_right_out[1] sb_1__0_:chanx_right_out[3] 0.0001329559 +7 cbx_2__0_:chanx_left_in[1] cbx_2__0_:chanx_left_in[3] 9.866816e-06 +8 sb_1__0__0_chanx_right_out[1]:2 sb_1__0__0_chanx_right_out[3]:2 9.866816e-06 +9 sb_1__0__0_chanx_right_out[1]:3 sb_1__0__0_chanx_right_out[3]:3 0.0001329559 + +*RES +0 sb_1__0_:chanx_right_out[1] sb_1__0__0_chanx_right_out[1]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[1]:2 cbx_2__0_:chanx_left_in[1] 0.0002303 +2 sb_1__0__0_chanx_right_out[1]:3 sb_1__0__0_chanx_right_out[1]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[10] 0.001504037 //LENGTH 7.660 LUMPCC 0.0004812958 DR + +*CONN +*I sb_1__0_:chanx_right_out[10] O *L 0 *C 661.330 318.240 +*I cbx_2__0_:chanx_left_in[10] I *L 0 *C 668.990 318.240 +*N sb_1__0__0_chanx_right_out[10]:2 *C 667.520 318.240 +*N sb_1__0__0_chanx_right_out[10]:3 *C 667.519 318.240 + +*CAP +0 sb_1__0_:chanx_right_out[10] 0.0002920926 +1 cbx_2__0_:chanx_left_in[10] 0.0002192781 +2 sb_1__0__0_chanx_right_out[10]:2 0.0002192781 +3 sb_1__0__0_chanx_right_out[10]:3 0.0002920926 +4 sb_1__0_:chanx_right_out[10] sb_1__0_:chanx_right_in[10] 0.000119662 +5 sb_1__0__0_chanx_right_out[10]:3 cbx_1__0__1_chanx_left_out[10]:2 0.000119662 +6 sb_1__0_:chanx_right_out[10] sb_1__0_:chanx_right_out[14] 0.0001209859 +7 sb_1__0__0_chanx_right_out[10]:3 sb_1__0__0_chanx_right_out[14]:3 0.0001209859 + +*RES +0 sb_1__0_:chanx_right_out[10] sb_1__0__0_chanx_right_out[10]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[10]:2 cbx_2__0_:chanx_left_in[10] 0.0002303 +2 sb_1__0__0_chanx_right_out[10]:3 sb_1__0__0_chanx_right_out[10]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[16] 0.00142066 //LENGTH 7.660 LUMPCC 0.0003777919 DR + +*CONN +*I sb_1__0_:chanx_right_out[16] O *L 0 *C 661.330 330.480 +*I cbx_2__0_:chanx_left_in[16] I *L 0 *C 668.990 330.480 +*N sb_1__0__0_chanx_right_out[16]:2 *C 667.520 330.480 +*N sb_1__0__0_chanx_right_out[16]:3 *C 667.519 330.480 + +*CAP +0 sb_1__0_:chanx_right_out[16] 0.0003014462 +1 cbx_2__0_:chanx_left_in[16] 0.0002199879 +2 sb_1__0__0_chanx_right_out[16]:2 0.0002199879 +3 sb_1__0__0_chanx_right_out[16]:3 0.0003014462 +4 sb_1__0_:chanx_right_out[16] sb_1__0_:chanx_right_out[4] 0.000122508 +5 sb_1__0__0_chanx_right_out[16]:3 sb_1__0__0_chanx_right_out[4]:3 0.000122508 +6 sb_1__0_:chanx_right_out[16] sb_1__0_:chanx_right_out[15] 6.63879e-05 +7 sb_1__0__0_chanx_right_out[16]:3 sb_1__0__0_chanx_right_out[15]:3 6.63879e-05 + +*RES +0 sb_1__0_:chanx_right_out[16] sb_1__0__0_chanx_right_out[16]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[16]:2 cbx_2__0_:chanx_left_in[16] 0.0002303 +2 sb_1__0__0_chanx_right_out[16]:3 sb_1__0__0_chanx_right_out[16]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[2] 0.001213397 //LENGTH 11.020 LUMPCC 0.0006111696 DR + +*CONN +*I sb_1__0_:chany_top_out[2] O *L 0 *C 597.540 397.050 +*I cby_1__1_:chany_bottom_in[2] I *L 0 *C 597.540 408.070 + +*CAP +0 sb_1__0_:chany_top_out[2] 0.0003011136 +1 cby_1__1_:chany_bottom_in[2] 0.0003011136 +2 sb_1__0_:chany_top_out[2] sb_1__0_:chany_top_out[0] 0.0001527924 +3 cby_1__1_:chany_bottom_in[2] cby_1__1_:chany_bottom_in[0] 0.0001527924 +4 sb_1__0_:chany_top_out[2] sb_1__0_:chany_top_out[19] 0.0001527924 +5 cby_1__1_:chany_bottom_in[2] cby_1__1_:chany_bottom_in[19] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[2] cby_1__1_:chany_bottom_in[2] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[12] 0.001213392 //LENGTH 11.020 LUMPCC 0.0006111696 DR + +*CONN +*I sb_1__0_:chany_top_out[12] O *L 0 *C 599.380 397.050 +*I cby_1__1_:chany_bottom_in[12] I *L 0 *C 599.380 408.070 + +*CAP +0 sb_1__0_:chany_top_out[12] 0.0003011111 +1 cby_1__1_:chany_bottom_in[12] 0.0003011111 +2 sb_1__0_:chany_top_out[12] sb_1__0_:chany_top_in[0] 0.0001527924 +3 cby_1__1_:chany_bottom_in[12] cby_1__1_:chany_bottom_out[0] 0.0001527924 +4 sb_1__0_:chany_top_out[12] sb_1__0_:chany_top_out[19] 0.0001527924 +5 cby_1__1_:chany_bottom_in[12] cby_1__1_:chany_bottom_in[19] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[12] cby_1__1_:chany_bottom_in[12] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[0] 0.001182546 //LENGTH 7.660 LUMPCC 0.0002646986 DR + +*CONN +*I sb_1__1_:chanx_left_out[0] O *L 0 *C 519.950 588.880 +*I cbx_1__1_:chanx_right_in[0] I *L 0 *C 512.290 588.880 + +*CAP +0 sb_1__1_:chanx_left_out[0] 0.0004589235 +1 cbx_1__1_:chanx_right_in[0] 0.0004589235 +2 sb_1__1_:chanx_left_out[0] sb_1__1_:chanx_left_in[10] 9.13291e-05 +3 cbx_1__1_:chanx_right_in[0] cbx_1__1_:chanx_right_out[10] 9.13291e-05 +4 sb_1__1_:chanx_left_out[0] sb_1__1_:ccff_tail[0] 4.102018e-05 +5 cbx_1__1_:chanx_right_in[0] cbx_1__1_:ccff_head[0] 4.102018e-05 + +*RES +0 sb_1__1_:chanx_left_out[0] cbx_1__1_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[6] 0.001344866 //LENGTH 7.660 LUMPCC 0.0005108556 DR + +*CONN +*I sb_1__1_:chanx_left_out[6] O *L 0 *C 519.950 578.000 +*I cbx_1__1_:chanx_right_in[6] I *L 0 *C 512.290 578.000 + +*CAP +0 sb_1__1_:chanx_left_out[6] 0.0004170053 +1 cbx_1__1_:chanx_right_in[6] 0.0004170053 +2 sb_1__1_:chanx_left_out[6] sb_1__1_:chanx_left_in[16] 0.0001105525 +3 cbx_1__1_:chanx_right_in[6] cbx_1__1__0_chanx_right_out[16]:2 0.0001105525 +4 sb_1__1_:chanx_left_out[6] sb_1__1_:chanx_left_out[8] 0.0001448753 +5 cbx_1__1_:chanx_right_in[6] cbx_1__1_:chanx_right_in[8] 0.0001448753 + +*RES +0 sb_1__1_:chanx_left_out[6] cbx_1__1_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[16] 0.001289534 //LENGTH 7.660 LUMPCC 0.0001394594 DR + +*CONN +*I sb_1__1_:chanx_left_out[16] O *L 0 *C 519.950 559.640 +*I cbx_1__1_:chanx_right_in[16] I *L 0 *C 512.290 559.640 + +*CAP +0 sb_1__1_:chanx_left_out[16] 0.0005750374 +1 cbx_1__1_:chanx_right_in[16] 0.0005750374 +2 sb_1__1_:chanx_left_out[16] sb_1__1_:chanx_left_in[6] 6.972968e-05 +3 cbx_1__1_:chanx_right_in[16] cbx_1__1_:chanx_right_out[6] 6.972968e-05 + +*RES +0 sb_1__1_:chanx_left_out[16] cbx_1__1_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[2] 0.001420435 //LENGTH 7.660 LUMPCC 0.0005549089 DR + +*CONN +*I sb_1__1_:chanx_right_out[2] O *L 0 *C 661.330 590.240 +*I cbx_2__1_:chanx_left_in[2] I *L 0 *C 668.990 590.240 +*N sb_1__1__0_chanx_right_out[2]:2 *C 667.520 590.240 +*N sb_1__1__0_chanx_right_out[2]:3 *C 667.519 590.240 + +*CAP +0 sb_1__1_:chanx_right_out[2] 0.0002580123 +1 cbx_2__1_:chanx_left_in[2] 0.0001747507 +2 sb_1__1__0_chanx_right_out[2]:2 0.0001747507 +3 sb_1__1__0_chanx_right_out[2]:3 0.0002580123 +4 sb_1__1_:chanx_right_out[2] sb_1__1_:chanx_right_out[9] 0.0001288604 +5 cbx_2__1_:chanx_left_in[2] cbx_2__1_:chanx_left_in[9] 9.866816e-06 +6 sb_1__1__0_chanx_right_out[2]:2 sb_1__1__0_chanx_right_out[9]:2 9.866816e-06 +7 sb_1__1__0_chanx_right_out[2]:3 sb_1__1__0_chanx_right_out[9]:3 0.0001288604 +8 sb_1__1_:chanx_right_out[2] sb_1__1_:chanx_right_out[10] 0.0001288604 +9 cbx_2__1_:chanx_left_in[2] cbx_2__1_:chanx_left_in[10] 9.866816e-06 +10 sb_1__1__0_chanx_right_out[2]:2 sb_1__1__0_chanx_right_out[10]:2 9.866816e-06 +11 sb_1__1__0_chanx_right_out[2]:3 sb_1__1__0_chanx_right_out[10]:3 0.0001288604 + +*RES +0 sb_1__1_:chanx_right_out[2] sb_1__1__0_chanx_right_out[2]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[2]:2 cbx_2__1_:chanx_left_in[2] 0.0002303 +2 sb_1__1__0_chanx_right_out[2]:3 sb_1__1__0_chanx_right_out[2]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[12] 0.001508699 //LENGTH 7.660 LUMPCC 0.0003888614 DR + +*CONN +*I sb_1__1_:chanx_right_out[12] O *L 0 *C 661.330 569.840 +*I cbx_2__1_:chanx_left_in[12] I *L 0 *C 668.990 569.840 +*N sb_1__1__0_chanx_right_out[12]:2 *C 667.520 569.840 +*N sb_1__1__0_chanx_right_out[12]:3 *C 667.519 569.840 + +*CAP +0 sb_1__1_:chanx_right_out[12] 0.0003528198 +1 cbx_2__1_:chanx_left_in[12] 0.0002070988 +2 sb_1__1__0_chanx_right_out[12]:2 0.0002070988 +3 sb_1__1__0_chanx_right_out[12]:3 0.0003528198 +4 sb_1__1_:chanx_right_out[12] sb_1__1_:chanx_right_in[11] 9.202773e-05 +5 sb_1__1__0_chanx_right_out[12]:3 cbx_1__1__1_chanx_left_out[11]:2 9.202773e-05 +6 sb_1__1_:chanx_right_out[12] sb_1__1_:chanx_right_out[16] 0.0001007594 +7 cbx_2__1_:chanx_left_in[12] cbx_2__1_:chanx_left_in[16] 1.643599e-06 +8 sb_1__1__0_chanx_right_out[12]:2 sb_1__1__0_chanx_right_out[16]:2 1.643599e-06 +9 sb_1__1__0_chanx_right_out[12]:3 sb_1__1__0_chanx_right_out[16]:3 0.0001007594 + +*RES +0 sb_1__1_:chanx_right_out[12] sb_1__1__0_chanx_right_out[12]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[12]:2 cbx_2__1_:chanx_left_in[12] 0.0002303 +2 sb_1__1__0_chanx_right_out[12]:3 sb_1__1__0_chanx_right_out[12]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[2] 0.001228652 //LENGTH 11.020 LUMPCC 0.0002509585 DR + +*CONN +*I sb_1__1_:chany_bottom_out[2] O *L 0 *C 572.240 527.750 +*I cby_1__1_:chany_top_in[2] I *L 0 *C 572.240 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[2] 0.0004888466 +1 cby_1__1_:chany_top_in[2] 0.0004888466 +2 sb_1__1_:chany_bottom_out[2] sb_1__1_:chany_bottom_in[15] 0.0001254793 +3 cby_1__1_:chany_top_in[2] cby_1__1_:chany_top_out[15] 0.0001254793 + +*RES +0 sb_1__1_:chany_bottom_out[2] cby_1__1_:chany_top_in[2] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[6] 0.001295469 //LENGTH 11.020 LUMPCC 0.000498686 DR + +*CONN +*I sb_1__1_:chany_bottom_out[6] O *L 0 *C 594.780 527.750 +*I cby_1__1_:chany_top_in[6] I *L 0 *C 594.780 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[6] 0.0003983915 +1 cby_1__1_:chany_top_in[6] 0.0003983915 +2 sb_1__1_:chany_bottom_out[6] sb_1__1_:chany_bottom_in[5] 0.0001246715 +3 cby_1__1_:chany_top_in[6] cby_1__1_:chany_top_out[5] 0.0001246715 +4 sb_1__1_:chany_bottom_out[6] sb_1__1_:chany_bottom_out[11] 0.0001246715 +5 cby_1__1_:chany_top_in[6] cby_1__1_:chany_top_in[11] 0.0001246715 + +*RES +0 sb_1__1_:chany_bottom_out[6] cby_1__1_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[15] 0.001228675 //LENGTH 11.020 LUMPCC 0.0003058225 DR + +*CONN +*I sb_1__1_:chany_bottom_out[15] O *L 0 *C 575.000 527.750 +*I cby_1__1_:chany_top_in[15] I *L 0 *C 575.000 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[15] 0.0004614263 +1 cby_1__1_:chany_top_in[15] 0.0004614263 +2 sb_1__1_:chany_bottom_out[15] sb_1__1_:chany_bottom_in[18] 2.503735e-05 +3 cby_1__1_:chany_top_in[15] cby_1__1_:chany_top_out[18] 2.503735e-05 +4 sb_1__1_:chany_bottom_out[15] sb_1__1_:chany_bottom_out[9] 0.0001278739 +5 cby_1__1_:chany_top_in[15] cby_1__1_:chany_top_in[9] 0.0001278739 + +*RES +0 sb_1__1_:chany_bottom_out[15] cby_1__1_:chany_top_in[15] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[3] 0.001245865 //LENGTH 11.020 LUMPCC 0.0005875931 DR + +*CONN +*I sb_1__1_:chany_top_out[3] O *L 0 *C 591.100 658.170 +*I cby_1__2_:chany_bottom_in[3] I *L 0 *C 591.100 669.190 +*N sb_1__1__0_chany_top_out[3]:2 *C 591.100 667.520 +*N sb_1__1__0_chany_top_out[3]:3 *C 591.100 667.519 + +*CAP +0 sb_1__1_:chany_top_out[3] 0.0002181978 +1 cby_1__2_:chany_bottom_in[3] 0.0001109382 +2 sb_1__1__0_chany_top_out[3]:2 0.0001109382 +3 sb_1__1__0_chany_top_out[3]:3 0.0002181978 +4 sb_1__1_:chany_top_out[3] sb_1__1_:chany_top_in[8] 0.000139552 +5 cby_1__2_:chany_bottom_in[3] cby_1__2_:chany_bottom_out[8] 7.346249e-06 +6 sb_1__1__0_chany_top_out[3]:2 cby_1__1__1_chany_bottom_out[8]:3 7.346249e-06 +7 sb_1__1__0_chany_top_out[3]:3 cby_1__1__1_chany_bottom_out[8]:2 0.000139552 +8 sb_1__1_:chany_top_out[3] sb_1__1_:chany_top_out[6] 0.000139552 +9 cby_1__2_:chany_bottom_in[3] cby_1__2_:chany_bottom_in[6] 7.346249e-06 +10 sb_1__1__0_chany_top_out[3]:2 sb_1__1__0_chany_top_out[6]:2 7.346249e-06 +11 sb_1__1__0_chany_top_out[3]:3 sb_1__1__0_chany_top_out[6]:3 0.000139552 + +*RES +0 sb_1__1_:chany_top_out[3] sb_1__1__0_chany_top_out[3]:3 0.008347321 +1 sb_1__1__0_chany_top_out[3]:2 cby_1__2_:chany_bottom_in[3] 0.001491072 +2 sb_1__1__0_chany_top_out[3]:3 sb_1__1__0_chany_top_out[3]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[10] 0.001226502 //LENGTH 11.020 LUMPCC 0.0006023085 DR + +*CONN +*I sb_1__1_:chany_top_out[10] O *L 0 *C 616.400 658.170 +*I cby_1__2_:chany_bottom_in[10] I *L 0 *C 616.400 669.190 +*N sb_1__1__0_chany_top_out[10]:2 *C 616.400 667.520 +*N sb_1__1__0_chany_top_out[10]:3 *C 616.400 667.519 + +*CAP +0 sb_1__1_:chany_top_out[10] 0.0002016359 +1 cby_1__2_:chany_bottom_in[10] 0.000110461 +2 sb_1__1__0_chany_top_out[10]:2 0.000110461 +3 sb_1__1__0_chany_top_out[10]:3 0.0002016359 +4 sb_1__1_:chany_top_out[10] sb_1__1_:chany_top_out[14] 0.0001431353 +5 cby_1__2_:chany_bottom_in[10] cby_1__2_:chany_bottom_in[14] 7.441891e-06 +6 sb_1__1__0_chany_top_out[10]:2 sb_1__1__0_chany_top_out[14]:2 7.441891e-06 +7 sb_1__1__0_chany_top_out[10]:3 sb_1__1__0_chany_top_out[14]:3 0.0001431353 +8 sb_1__1_:chany_top_out[10] sb_1__1_:chany_top_out[18] 0.0001431353 +9 cby_1__2_:chany_bottom_in[10] cby_1__2_:chany_bottom_in[18] 7.441891e-06 +10 sb_1__1__0_chany_top_out[10]:2 sb_1__1__0_chany_top_out[18]:2 7.441891e-06 +11 sb_1__1__0_chany_top_out[10]:3 sb_1__1__0_chany_top_out[18]:3 0.0001431353 + +*RES +0 sb_1__1_:chany_top_out[10] sb_1__1__0_chany_top_out[10]:3 0.008347322 +1 sb_1__1__0_chany_top_out[10]:2 cby_1__2_:chany_bottom_in[10] 0.001491072 +2 sb_1__1__0_chany_top_out[10]:3 sb_1__1__0_chany_top_out[10]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[1] 0.001334789 //LENGTH 7.660 LUMPCC 0.000380504 DR + +*CONN +*I sb_1__2_:chanx_left_out[1] O *L 0 *C 519.950 882.640 +*I cbx_1__2_:chanx_right_in[1] I *L 0 *C 512.290 882.640 + +*CAP +0 sb_1__2_:chanx_left_out[1] 0.0004771425 +1 cbx_1__2_:chanx_right_in[1] 0.0004771425 +2 sb_1__2_:chanx_left_out[1] sb_1__2_:chanx_left_in[15] 4.923313e-05 +3 cbx_1__2_:chanx_right_in[1] cbx_1__2_:chanx_right_out[15] 4.923313e-05 +4 sb_1__2_:chanx_left_out[1] sb_1__2_:chanx_left_out[11] 0.0001410189 +5 cbx_1__2_:chanx_right_in[1] cbx_1__2_:chanx_right_in[11] 0.0001410189 + +*RES +0 sb_1__2_:chanx_left_out[1] cbx_1__2_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[12] 0.001346894 //LENGTH 7.660 LUMPCC 0.0003756626 DR + +*CONN +*I sb_1__2_:chanx_left_out[12] O *L 0 *C 519.950 871.760 +*I cbx_1__2_:chanx_right_in[12] I *L 0 *C 512.290 871.760 + +*CAP +0 sb_1__2_:chanx_left_out[12] 0.0004856159 +1 cbx_1__2_:chanx_right_in[12] 0.0004856159 +2 sb_1__2_:chanx_left_out[12] sb_1__2_:chanx_left_in[19] 0.0001409491 +3 cbx_1__2_:chanx_right_in[12] cbx_1__2_:chanx_right_out[19] 0.0001409491 +4 sb_1__2_:chanx_left_out[12] sb_1__2_:chanx_left_out[8] 4.688213e-05 +5 cbx_1__2_:chanx_right_in[12] cbx_1__2_:chanx_right_in[8] 4.688213e-05 + +*RES +0 sb_1__2_:chanx_left_out[12] cbx_1__2_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[1] 0.001382121 //LENGTH 7.660 LUMPCC 0.0003835938 DR + +*CONN +*I sb_1__2_:chanx_right_out[1] O *L 0 *C 661.330 836.400 +*I cbx_2__2_:chanx_left_in[1] I *L 0 *C 668.990 836.400 +*N sb_1__2__0_chanx_right_out[1]:2 *C 667.520 836.400 +*N sb_1__2__0_chanx_right_out[1]:3 *C 667.519 836.400 + +*CAP +0 sb_1__2_:chanx_right_out[1] 0.0002921609 +1 cbx_2__2_:chanx_left_in[1] 0.0002071029 +2 sb_1__2__0_chanx_right_out[1]:2 0.0002071029 +3 sb_1__2__0_chanx_right_out[1]:3 0.0002921609 +4 sb_1__2_:chanx_right_out[1] sb_1__2_:chanx_right_in[7] 6.398198e-05 +5 sb_1__2__0_chanx_right_out[1]:3 cbx_1__2__1_chanx_left_out[7]:2 6.398198e-05 +6 sb_1__2_:chanx_right_out[1] sb_1__2_:chanx_right_out[19] 0.0001261708 +7 cbx_2__2_:chanx_left_in[1] cbx_2__2_:chanx_left_in[19] 1.644113e-06 +8 sb_1__2__0_chanx_right_out[1]:2 sb_1__2__0_chanx_right_out[19]:2 1.644113e-06 +9 sb_1__2__0_chanx_right_out[1]:3 sb_1__2__0_chanx_right_out[19]:3 0.0001261708 + +*RES +0 sb_1__2_:chanx_right_out[1] sb_1__2__0_chanx_right_out[1]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[1]:2 cbx_2__2_:chanx_left_in[1] 0.0002303 +2 sb_1__2__0_chanx_right_out[1]:3 sb_1__2__0_chanx_right_out[1]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[11] 0.001338433 //LENGTH 7.660 LUMPCC 0.0004124883 DR + +*CONN +*I sb_1__2_:chanx_right_out[11] O *L 0 *C 661.330 858.160 +*I cbx_2__2_:chanx_left_in[11] I *L 0 *C 668.990 858.160 +*N sb_1__2__0_chanx_right_out[11]:2 *C 667.520 858.160 +*N sb_1__2__0_chanx_right_out[11]:3 *C 667.519 858.160 + +*CAP +0 sb_1__2_:chanx_right_out[11] 0.0002758666 +1 cbx_2__2_:chanx_left_in[11] 0.0001871056 +2 sb_1__2__0_chanx_right_out[11]:2 0.0001871056 +3 sb_1__2__0_chanx_right_out[11]:3 0.0002758666 +4 sb_1__2_:chanx_right_out[11] sb_1__2_:chanx_right_in[19] 6.249115e-05 +5 sb_1__2__0_chanx_right_out[11]:3 cbx_1__2__1_chanx_left_out[19]:2 6.249115e-05 +6 sb_1__2_:chanx_right_out[11] sb_1__2_:chanx_right_out[15] 0.0001338862 +7 cbx_2__2_:chanx_left_in[11] cbx_2__2_:chanx_left_in[15] 9.866816e-06 +8 sb_1__2__0_chanx_right_out[11]:2 sb_1__2__0_chanx_right_out[15]:2 9.866816e-06 +9 sb_1__2__0_chanx_right_out[11]:3 sb_1__2__0_chanx_right_out[15]:3 0.0001338862 + +*RES +0 sb_1__2_:chanx_right_out[11] sb_1__2__0_chanx_right_out[11]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[11]:2 cbx_2__2_:chanx_left_in[11] 0.0002303 +2 sb_1__2__0_chanx_right_out[11]:3 sb_1__2__0_chanx_right_out[11]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[2] 0.001427654 //LENGTH 12.500 LUMPCC 0.000365462 DR + +*CONN +*I sb_1__2_:chany_bottom_out[2] O *L 0 *C 572.240 788.870 +*I cby_1__2_:chany_top_in[2] I *L 0 *C 572.240 777.850 +*N sb_1__2__0_chany_bottom_out[2]:2 *C 572.240 783.360 +*N sb_1__2__0_chany_bottom_out[2]:3 *C 572.700 783.360 +*N sb_1__2__0_chany_bottom_out[2]:4 *C 572.700 785.060 +*N sb_1__2__0_chany_bottom_out[2]:5 *C 572.240 785.060 + +*CAP +0 sb_1__2_:chany_bottom_out[2] 0.0001626954 +1 cby_1__2_:chany_top_in[2] 0.000281483 +2 sb_1__2__0_chany_bottom_out[2]:2 0.0002886691 +3 sb_1__2__0_chany_bottom_out[2]:3 8.545362e-05 +4 sb_1__2__0_chany_bottom_out[2]:4 7.97314e-05 +5 sb_1__2__0_chany_bottom_out[2]:5 0.0001641593 +6 sb_1__2_:chany_bottom_out[2] sb_1__2_:chany_bottom_in[15] 4.03335e-05 +7 cby_1__2_:chany_top_in[2] cby_1__2_:chany_top_out[15] 4.900551e-05 +8 sb_1__2__0_chany_bottom_out[2]:2 sb_1__2_:chany_bottom_in[15] 4.900551e-05 +9 sb_1__2__0_chany_bottom_out[2]:3 cby_1__2_:chany_top_out[15] 5.05203e-05 +10 sb_1__2__0_chany_bottom_out[2]:5 cby_1__2_:chany_top_out[15] 4.03335e-05 +11 sb_1__2__0_chany_bottom_out[2]:4 sb_1__2_:chany_bottom_in[15] 5.05203e-05 +12 sb_1__2__0_chany_bottom_out[2]:2 direct_interc_5_out[0]:13 1.898727e-05 +13 sb_1__2__0_chany_bottom_out[2]:3 direct_interc_5_out[0]:12 1.898727e-05 +14 sb_1__2__0_chany_bottom_out[2]:5 direct_interc_5_out[0]:13 2.388444e-05 +15 sb_1__2__0_chany_bottom_out[2]:4 direct_interc_5_out[0]:12 2.388444e-05 + +*RES +0 sb_1__2_:chany_bottom_out[2] sb_1__2__0_chany_bottom_out[2]:5 0.003401786 +1 sb_1__2__0_chany_bottom_out[2]:2 cby_1__2_:chany_top_in[2] 0.004919643 +2 sb_1__2__0_chany_bottom_out[2]:3 sb_1__2__0_chany_bottom_out[2]:2 0.0004107143 +3 sb_1__2__0_chany_bottom_out[2]:5 sb_1__2__0_chany_bottom_out[2]:4 0.0004107143 +4 sb_1__2__0_chany_bottom_out[2]:4 sb_1__2__0_chany_bottom_out[2]:3 0.001517857 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[15] 0.00120025 //LENGTH 11.020 LUMPCC 0.0003479659 DR + +*CONN +*I sb_1__2_:chany_bottom_out[15] O *L 0 *C 575.000 788.870 +*I cby_1__2_:chany_top_in[15] I *L 0 *C 575.000 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[15] 0.000426142 +1 cby_1__2_:chany_top_in[15] 0.000426142 +2 sb_1__2_:chany_bottom_out[15] sb_1__2_:chany_bottom_in[18] 3.864802e-05 +3 cby_1__2_:chany_top_in[15] cby_1__2_:chany_top_out[18] 3.864802e-05 +4 sb_1__2_:chany_bottom_out[15] sb_1__2_:chany_bottom_out[9] 0.0001353349 +5 cby_1__2_:chany_top_in[15] cby_1__2_:chany_top_in[9] 0.0001353349 + +*RES +0 sb_1__2_:chany_bottom_out[15] cby_1__2_:chany_top_in[15] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[3] 0.001451856 //LENGTH 7.660 LUMPCC 0.000517842 DR + +*CONN +*I sb_2__0_:chanx_left_out[3] O *L 0 *C 781.230 353.600 +*I cbx_2__0_:chanx_right_in[3] I *L 0 *C 773.570 353.600 + +*CAP +0 sb_2__0_:chanx_left_out[3] 0.0004670068 +1 cbx_2__0_:chanx_right_in[3] 0.0004670068 +2 sb_2__0_:chanx_left_out[3] sb_2__0_:chanx_left_out[5] 0.0001256684 +3 cbx_2__0_:chanx_right_in[3] cbx_2__0_:chanx_right_in[5] 0.0001256684 +4 sb_2__0_:chanx_left_out[3] sb_2__0_:chanx_left_out[19] 0.0001332525 +5 cbx_2__0_:chanx_right_in[3] cbx_2__0_:chanx_right_in[19] 0.0001332525 + +*RES +0 sb_2__0_:chanx_left_out[3] cbx_2__0_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[14] 0.001408159 //LENGTH 7.660 LUMPCC 0.0003312324 DR + +*CONN +*I sb_2__0_:chanx_left_out[14] O *L 0 *C 781.230 311.440 +*I cbx_2__0_:chanx_right_in[14] I *L 0 *C 773.570 311.440 + +*CAP +0 sb_2__0_:chanx_left_out[14] 0.0005384634 +1 cbx_2__0_:chanx_right_in[14] 0.0005384634 +2 sb_2__0_:chanx_left_out[14] sb_2__0_:chanx_left_in[17] 4.266354e-05 +3 cbx_2__0_:chanx_right_in[14] cbx_1__0__1_chanx_right_out[17]:2 4.266354e-05 +4 sb_2__0_:chanx_left_out[14] sb_2__0_:chanx_left_out[2] 8.220947e-05 +5 cbx_2__0_:chanx_right_in[14] cbx_2__0_:chanx_right_in[2] 8.220947e-05 +6 sb_2__0_:chanx_left_out[14] sb_2__0_:chanx_left_out[10] 4.074317e-05 +7 cbx_2__0_:chanx_right_in[14] cbx_2__0_:chanx_right_in[10] 4.074317e-05 + +*RES +0 sb_2__0_:chanx_left_out[14] cbx_2__0_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[6] 0.001231928 //LENGTH 11.020 LUMPCC 0.0005866284 DR + +*CONN +*I sb_2__0_:chany_top_out[6] O *L 0 *C 851.460 397.050 +*I cby_2__1_:chany_bottom_in[6] I *L 0 *C 851.460 408.070 + +*CAP +0 sb_2__0_:chany_top_out[6] 0.0003226495 +1 cby_2__1_:chany_bottom_in[6] 0.0003226495 +2 sb_2__0_:chany_top_out[6] sb_2__0_:chany_top_in[16] 0.0001448879 +3 cby_2__1_:chany_bottom_in[6] cby_2__1_:chany_bottom_out[16] 0.0001448879 +4 sb_2__0_:chany_top_out[6] sb_2__0_:chany_top_out[3] 0.0001484263 +5 cby_2__1_:chany_bottom_in[6] cby_2__1_:chany_bottom_in[3] 0.0001484263 + +*RES +0 sb_2__0_:chany_top_out[6] cby_2__1_:chany_bottom_in[6] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[13] 0.001134065 //LENGTH 11.020 LUMPCC 0.0004108157 DR + +*CONN +*I sb_2__0_:chany_top_out[13] O *L 0 *C 845.480 397.050 +*I cby_2__1_:chany_bottom_in[13] I *L 0 *C 845.480 408.070 + +*CAP +0 sb_2__0_:chany_top_out[13] 0.0003616246 +1 cby_2__1_:chany_bottom_in[13] 0.0003616246 +2 sb_2__0_:chany_top_out[13] sb_2__0_:chany_top_in[7] 5.275058e-05 +3 cby_2__1_:chany_bottom_in[13] cby_2__1_:chany_bottom_out[7] 5.275058e-05 +4 sb_2__0_:chany_top_out[13] sb_2__0_:chany_top_in[13] 0.0001526573 +5 cby_2__1_:chany_bottom_in[13] cby_2__1_:chany_bottom_out[13] 0.0001526573 + +*RES +0 sb_2__0_:chany_top_out[13] cby_2__1_:chany_bottom_in[13] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[1] 0.001486759 //LENGTH 7.660 LUMPCC 0.0004820224 DR + +*CONN +*I sb_2__1_:chanx_left_out[1] O *L 0 *C 781.230 609.280 +*I cbx_2__1_:chanx_right_in[1] I *L 0 *C 773.570 609.280 + +*CAP +0 sb_2__1_:chanx_left_out[1] 0.0005023683 +1 cbx_2__1_:chanx_right_in[1] 0.0005023683 +2 sb_2__1_:chanx_left_out[1] sb_2__1_:chanx_left_out[2] 0.0001211731 +3 cbx_2__1_:chanx_right_in[1] cbx_2__1_:chanx_right_in[2] 0.0001211731 +4 sb_2__1_:chanx_left_out[1] sb_2__1_:chanx_left_out[4] 0.0001198381 +5 cbx_2__1_:chanx_right_in[1] cbx_2__1_:chanx_right_in[4] 0.0001198381 + +*RES +0 sb_2__1_:chanx_left_out[1] cbx_2__1_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[12] 0.001516337 //LENGTH 7.660 LUMPCC 0.0003275274 DR + +*CONN +*I sb_2__1_:chanx_left_out[12] O *L 0 *C 781.230 572.560 +*I cbx_2__1_:chanx_right_in[12] I *L 0 *C 773.570 572.560 + +*CAP +0 sb_2__1_:chanx_left_out[12] 0.0005944046 +1 cbx_2__1_:chanx_right_in[12] 0.0005944046 +2 sb_2__1_:chanx_left_out[12] sb_2__1_:chanx_left_in[2] 5.956342e-05 +3 cbx_2__1_:chanx_right_in[12] cbx_1__1__1_chanx_right_out[2]:2 5.956342e-05 +4 sb_2__1_:chanx_left_out[12] sb_2__1_:chanx_left_in[8] 0.0001042003 +5 cbx_2__1_:chanx_right_in[12] cbx_2__1_:chanx_right_out[8] 0.0001042003 + +*RES +0 sb_2__1_:chanx_left_out[12] cbx_2__1_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[0] 0.001281216 //LENGTH 11.020 LUMPCC 0.0005269798 DR + +*CONN +*I sb_2__1_:chany_bottom_out[0] O *L 0 *C 864.340 527.750 +*I cby_2__1_:chany_top_in[0] I *L 0 *C 864.340 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[0] 0.0003771181 +1 cby_2__1_:chany_top_in[0] 0.0003771181 +2 sb_2__1_:chany_bottom_out[0] sb_2__1_:chany_bottom_in[0] 0.0001317449 +3 cby_2__1_:chany_top_in[0] cby_2__1_:chany_top_out[0] 0.0001317449 +4 sb_2__1_:chany_bottom_out[0] sb_2__1_:chany_bottom_in[9] 0.0001317449 +5 cby_2__1_:chany_top_in[0] cby_2__1_:chany_top_out[9] 0.0001317449 + +*RES +0 sb_2__1_:chany_bottom_out[0] cby_2__1_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[7] 0.001276208 //LENGTH 11.020 LUMPCC 0.0005337231 DR + +*CONN +*I sb_2__1_:chany_bottom_out[7] O *L 0 *C 841.800 527.750 +*I cby_2__1_:chany_top_in[7] I *L 0 *C 841.800 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[7] 0.0003712427 +1 cby_2__1_:chany_top_in[7] 0.0003712427 +2 sb_2__1_:chany_bottom_out[7] sb_2__1_:chany_bottom_out[1] 0.0001334308 +3 cby_2__1_:chany_top_in[7] cby_2__1_:chany_top_in[1] 0.0001334308 +4 sb_2__1_:chany_bottom_out[7] sb_2__1_:chany_bottom_out[13] 0.0001334308 +5 cby_2__1_:chany_top_in[7] cby_2__1_:chany_top_in[13] 0.0001334308 + +*RES +0 sb_2__1_:chany_bottom_out[7] cby_2__1_:chany_top_in[7] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[17] 0.001246244 //LENGTH 11.020 LUMPCC 0.0004200413 DR + +*CONN +*I sb_2__1_:chany_bottom_out[17] O *L 0 *C 839.960 527.750 +*I cby_2__1_:chany_top_in[17] I *L 0 *C 839.960 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[17] 0.0004131016 +1 cby_2__1_:chany_top_in[17] 0.0004131016 +2 sb_2__1_:chany_bottom_out[17] sb_2__1_:chany_bottom_in[18] 7.658988e-05 +3 cby_2__1_:chany_top_in[17] cby_2__1_:chany_top_out[18] 7.658988e-05 +4 sb_2__1_:chany_bottom_out[17] sb_2__1_:chany_bottom_out[1] 0.0001334308 +5 cby_2__1_:chany_top_in[17] cby_2__1_:chany_top_in[1] 0.0001334308 + +*RES +0 sb_2__1_:chany_bottom_out[17] cby_2__1_:chany_top_in[17] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[7] 0.001176126 //LENGTH 11.020 LUMPCC 0.0002768753 DR + +*CONN +*I sb_2__1_:chany_top_out[7] O *L 0 *C 831.220 658.170 +*I cby_2__2_:chany_bottom_in[7] I *L 0 *C 831.220 669.190 +*N sb_2__1__0_chany_top_out[7]:2 *C 831.220 667.520 +*N sb_2__1__0_chany_top_out[7]:3 *C 831.220 667.519 + +*CAP +0 sb_2__1_:chany_top_out[7] 0.0003307028 +1 cby_2__2_:chany_bottom_in[7] 0.0001189227 +2 sb_2__1__0_chany_top_out[7]:2 0.0001189227 +3 sb_2__1__0_chany_top_out[7]:3 0.0003307028 +4 sb_2__1_:chany_top_out[7] sb_2__1_:chany_top_out[15] 0.0001310978 +5 cby_2__2_:chany_bottom_in[7] cby_2__2_:chany_bottom_in[15] 7.339873e-06 +6 sb_2__1__0_chany_top_out[7]:2 sb_2__1__0_chany_top_out[15]:2 7.339873e-06 +7 sb_2__1__0_chany_top_out[7]:3 sb_2__1__0_chany_top_out[15]:3 0.0001310978 + +*RES +0 sb_2__1_:chany_top_out[7] sb_2__1__0_chany_top_out[7]:3 0.008347322 +1 sb_2__1__0_chany_top_out[7]:2 cby_2__2_:chany_bottom_in[7] 0.001491071 +2 sb_2__1__0_chany_top_out[7]:3 sb_2__1__0_chany_top_out[7]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[14] 0.00122185 //LENGTH 11.020 LUMPCC 0.0004480303 DR + +*CONN +*I sb_2__1_:chany_top_out[14] O *L 0 *C 878.600 658.170 +*I cby_2__2_:chany_bottom_in[14] I *L 0 *C 878.600 669.190 +*N sb_2__1__0_chany_top_out[14]:2 *C 878.600 667.520 +*N sb_2__1__0_chany_top_out[14]:3 *C 878.600 667.519 + +*CAP +0 sb_2__1_:chany_top_out[14] 0.00026947 +1 cby_2__2_:chany_bottom_in[14] 0.0001174397 +2 sb_2__1__0_chany_top_out[14]:2 0.0001174397 +3 sb_2__1__0_chany_top_out[14]:3 0.00026947 +4 sb_2__1_:chany_top_out[14] sb_2__1_:chany_top_out[4] 8.235022e-05 +5 cby_2__2_:chany_bottom_in[14] cby_2__2_:chany_bottom_in[4] 1.486063e-06 +6 sb_2__1__0_chany_top_out[14]:2 sb_2__1__0_chany_top_out[4]:2 1.486063e-06 +7 sb_2__1__0_chany_top_out[14]:3 sb_2__1__0_chany_top_out[4]:3 8.235022e-05 +8 sb_2__1_:chany_top_out[14] sb_2__1_:chany_top_out[10] 0.0001328241 +9 cby_2__2_:chany_bottom_in[14] cby_2__2_:chany_bottom_in[10] 7.354774e-06 +10 sb_2__1__0_chany_top_out[14]:2 sb_2__1__0_chany_top_out[10]:2 7.354774e-06 +11 sb_2__1__0_chany_top_out[14]:3 sb_2__1__0_chany_top_out[10]:3 0.0001328241 + +*RES +0 sb_2__1_:chany_top_out[14] sb_2__1__0_chany_top_out[14]:3 0.008347322 +1 sb_2__1__0_chany_top_out[14]:2 cby_2__2_:chany_bottom_in[14] 0.001491072 +2 sb_2__1__0_chany_top_out[14]:3 sb_2__1__0_chany_top_out[14]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[3] 0.001399443 //LENGTH 7.660 LUMPCC 0.0005774641 DR + +*CONN +*I sb_2__2_:chanx_left_out[3] O *L 0 *C 781.230 837.760 +*I cbx_2__2_:chanx_right_in[3] I *L 0 *C 773.570 837.760 + +*CAP +0 sb_2__2_:chanx_left_out[3] 0.0004109893 +1 cbx_2__2_:chanx_right_in[3] 0.0004109893 +2 sb_2__2_:chanx_left_out[3] sb_2__2_:chanx_left_in[4] 0.0001444492 +3 cbx_2__2_:chanx_right_in[3] cbx_2__2_:chanx_right_out[4] 0.0001444492 +4 sb_2__2_:chanx_left_out[3] sb_2__2_:chanx_left_out[7] 0.0001442828 +5 cbx_2__2_:chanx_right_in[3] cbx_2__2_:chanx_right_in[7] 0.0001442828 + +*RES +0 sb_2__2_:chanx_left_out[3] cbx_2__2_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[12] 0.001440734 //LENGTH 7.660 LUMPCC 0.0003537291 DR + +*CONN +*I sb_2__2_:chanx_left_out[12] O *L 0 *C 781.230 871.760 +*I cbx_2__2_:chanx_right_in[12] I *L 0 *C 773.570 871.760 + +*CAP +0 sb_2__2_:chanx_left_out[12] 0.0005435025 +1 cbx_2__2_:chanx_right_in[12] 0.0005435025 +2 sb_2__2_:chanx_left_out[12] sb_2__2_:chanx_left_in[19] 0.0001170104 +3 cbx_2__2_:chanx_right_in[12] cbx_2__2_:chanx_right_out[19] 0.0001170104 +4 sb_2__2_:chanx_left_out[12] sb_2__2_:chanx_left_out[8] 5.985417e-05 +5 cbx_2__2_:chanx_right_in[12] cbx_2__2_:chanx_right_in[8] 5.985417e-05 + +*RES +0 sb_2__2_:chanx_left_out[12] cbx_2__2_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[3] 0.00126029 //LENGTH 11.020 LUMPCC 0.0005569746 DR + +*CONN +*I sb_2__2_:chany_bottom_out[3] O *L 0 *C 850.080 788.870 +*I cby_2__2_:chany_top_in[3] I *L 0 *C 850.080 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[3] 0.0003516579 +1 cby_2__2_:chany_top_in[3] 0.0003516579 +2 sb_2__2_:chany_bottom_out[3] sb_2__2_:chany_bottom_in[13] 0.0001392436 +3 cby_2__2_:chany_top_in[3] cby_2__2_:chany_top_out[13] 0.0001392436 +4 sb_2__2_:chany_bottom_out[3] sb_2__2_:chany_bottom_in[17] 0.0001392436 +5 cby_2__2_:chany_top_in[3] cby_2__2_:chany_top_out[17] 0.0001392436 + +*RES +0 sb_2__2_:chany_bottom_out[3] cby_2__2_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[14] 0.001178311 //LENGTH 11.020 LUMPCC 0.0002879653 DR + +*CONN +*I sb_2__2_:chany_bottom_out[14] O *L 0 *C 878.600 788.870 +*I cby_2__2_:chany_top_in[14] I *L 0 *C 878.600 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[14] 0.0004451727 +1 cby_2__2_:chany_top_in[14] 0.0004451727 +2 sb_2__2_:chany_bottom_out[14] sb_2__2_:chany_bottom_out[4] 0.0001439826 +3 cby_2__2_:chany_top_in[14] cby_2__2_:chany_top_in[4] 0.0001439826 + +*RES +0 sb_2__2_:chany_bottom_out[14] cby_2__2_:chany_top_in[14] 0.009839286 + +*END + +*D_NET BUF_net_9 0.002465447 //LENGTH 19.285 LUMPCC 0.0006460819 DR + +*CONN +*I BUFT_P_9:X O *L 0 *C 557.240 522.920 +*I grid_clb_1__1_:Test_en[0] I *L 0 *C 540.810 520.880 +*N BUF_net_9:2 *C 549.233 520.880 +*N BUF_net_9:3 *C 549.240 520.938 +*N BUF_net_9:4 *C 549.240 522.875 +*N BUF_net_9:5 *C 549.285 522.920 +*N BUF_net_9:6 *C 557.202 522.920 + +*CAP +0 BUFT_P_9:X 1e-06 +1 grid_clb_1__1_:Test_en[0] 0.0003342536 +2 BUF_net_9:2 0.0003342536 +3 BUF_net_9:3 0.0001097946 +4 BUF_net_9:4 0.0001097946 +5 BUF_net_9:5 0.0004651343 +6 BUF_net_9:6 0.0004651343 +7 grid_clb_1__1_:Test_en[0] grid_clb_1__1_:clk[0] 0.0001784555 +8 BUF_net_9:2 clk[0]:37 0.0001784555 +9 grid_clb_1__1_:Test_en[0] ctsbuf_net_2029:33 0.0001371272 +10 BUF_net_9:2 ctsbuf_net_2029:32 0.0001371272 +11 BUF_net_9:5 ctsbuf_net_2029:33 7.458331e-06 +12 BUF_net_9:6 ctsbuf_net_2029:32 7.458331e-06 + +*RES +0 BUFT_P_9:X BUF_net_9:6 0.152 +1 BUF_net_9:3 BUF_net_9:2 0.00341 +2 BUF_net_9:2 grid_clb_1__1_:Test_en[0] 0.001319525 +3 BUF_net_9:5 BUF_net_9:4 0.0045 +4 BUF_net_9:4 BUF_net_9:3 0.001729911 +5 BUF_net_9:6 BUF_net_9:5 0.007069197 + +*END + +*D_NET ctsbuf_net_1019 0.02955956 //LENGTH 253.327 LUMPCC 0.002147997 DR + +*CONN +*I cts_inv_73597634:Y O *L 0 *C 516.580 545.020 +*I cby_1__1_:prog_clk[0] I *L 0 *C 548.470 497.760 +*I cbx_1__0_:prog_clk[0] I *L 0 *C 498.180 369.850 +*N ctsbuf_net_1019:3 *C 498.180 371.903 +*N ctsbuf_net_1019:4 *C 498.188 371.960 +*N ctsbuf_net_1019:5 *C 541.873 371.960 +*N ctsbuf_net_1019:6 *C 541.880 372.018 +*N ctsbuf_net_1019:7 *C 541.880 421.775 +*N ctsbuf_net_1019:8 *C 541.880 443.519 +*N ctsbuf_net_1019:9 *C 541.880 443.520 +*N ctsbuf_net_1019:10 *C 541.880 471.775 +*N ctsbuf_net_1019:11 *C 541.888 497.760 +*N ctsbuf_net_1019:12 *C 541.880 497.703 +*N ctsbuf_net_1019:13 *C 541.420 497.760 +*N ctsbuf_net_1019:14 *C 541.420 545.303 +*N ctsbuf_net_1019:15 *C 541.413 545.360 +*N ctsbuf_net_1019:16 *C 525.327 545.360 +*N ctsbuf_net_1019:17 *C 525.320 545.360 +*N ctsbuf_net_1019:18 *C 525.320 545.020 +*N ctsbuf_net_1019:19 *C 525.275 545.020 +*N ctsbuf_net_1019:20 *C 516.618 545.020 + +*CAP +0 cts_inv_73597634:Y 1e-06 +1 cby_1__1_:prog_clk[0] 0.0004796313 +2 cbx_1__0_:prog_clk[0] 0.0001451547 +3 ctsbuf_net_1019:3 0.0001451547 +4 ctsbuf_net_1019:4 0.002130725 +5 ctsbuf_net_1019:5 0.002130725 +6 ctsbuf_net_1019:6 0.00263198 +7 ctsbuf_net_1019:7 0.003821605 +8 ctsbuf_net_1019:8 0.001189626 +9 ctsbuf_net_1019:9 0.001539163 +10 ctsbuf_net_1019:10 0.002971979 +11 ctsbuf_net_1019:11 0.0004796313 +12 ctsbuf_net_1019:12 0.001470742 +13 ctsbuf_net_1019:13 0.00251486 +14 ctsbuf_net_1019:14 0.002476933 +15 ctsbuf_net_1019:15 0.001069203 +16 ctsbuf_net_1019:16 0.001069203 +17 ctsbuf_net_1019:17 5.932891e-05 +18 ctsbuf_net_1019:18 5.533945e-05 +19 ctsbuf_net_1019:19 0.000514789 +20 ctsbuf_net_1019:20 0.000514789 +21 ctsbuf_net_1019:5 cbx_1__0__0_chanx_right_out[2]:5 0.0001016692 +22 ctsbuf_net_1019:4 cbx_1__0__0_chanx_right_out[2]:6 0.0001016692 +23 ctsbuf_net_1019:5 cbx_1__0__0_chanx_right_out[10]:5 0.0001391282 +24 ctsbuf_net_1019:4 cbx_1__0__0_chanx_right_out[10]:6 0.0001391282 +25 cby_1__1_:prog_clk[0] cby_1__1_:left_grid_pin_1_[0] 2.413176e-05 +26 ctsbuf_net_1019:11 grid_clb_1__1_:right_width_0_height_0__pin_1_[0] 2.413176e-05 +27 ctsbuf_net_1019:14 direct_interc_5_out[0]:28 3.410022e-05 +28 ctsbuf_net_1019:6 direct_interc_5_out[0]:33 0.0001107969 +29 ctsbuf_net_1019:12 direct_interc_5_out[0]:28 4.908455e-05 +30 ctsbuf_net_1019:12 direct_interc_5_out[0]:29 1.916155e-05 +31 ctsbuf_net_1019:13 direct_interc_5_out[0]:29 3.410022e-05 +32 ctsbuf_net_1019:7 direct_interc_5_out[0]:32 0.0001519206 +33 ctsbuf_net_1019:7 direct_interc_5_out[0]:33 1.946896e-05 +34 ctsbuf_net_1019:10 direct_interc_5_out[0]:29 0.0001293115 +35 ctsbuf_net_1019:10 direct_interc_5_out[0]:30 1.916155e-05 +36 ctsbuf_net_1019:9 direct_interc_5_out[0]:30 8.022691e-05 +37 ctsbuf_net_1019:8 direct_interc_5_out[0]:31 4.112373e-05 +38 ctsbuf_net_1019:8 direct_interc_5_out[0]:32 1.946896e-05 +39 ctsbuf_net_1019:6 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 7.561906e-05 +40 ctsbuf_net_1019:7 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 7.561906e-05 +41 ctsbuf_net_1019:14 ctsbuf_net_2029:35 0.0002633473 +42 ctsbuf_net_1019:15 ctsbuf_net_2029:36 8.857888e-05 +43 ctsbuf_net_1019:16 ctsbuf_net_2029:37 8.857888e-05 +44 ctsbuf_net_1019:19 ctsbuf_net_2029:15 2.756124e-05 +45 ctsbuf_net_1019:20 ctsbuf_net_2029:14 2.756124e-05 +46 ctsbuf_net_1019:13 ctsbuf_net_2029:34 0.0002633473 + +*RES +0 cts_inv_73597634:Y ctsbuf_net_1019:20 0.152 +1 ctsbuf_net_1019:14 ctsbuf_net_1019:13 0.04244867 +2 ctsbuf_net_1019:15 ctsbuf_net_1019:14 0.00341 +3 ctsbuf_net_1019:17 ctsbuf_net_1019:16 0.00341 +4 ctsbuf_net_1019:16 ctsbuf_net_1019:15 0.002519983 +5 ctsbuf_net_1019:19 ctsbuf_net_1019:18 0.0045 +6 ctsbuf_net_1019:18 ctsbuf_net_1019:17 0.0001634615 +7 ctsbuf_net_1019:20 ctsbuf_net_1019:19 0.007729912 +8 ctsbuf_net_1019:6 ctsbuf_net_1019:5 0.00341 +9 ctsbuf_net_1019:5 ctsbuf_net_1019:4 0.006843983 +10 ctsbuf_net_1019:3 cbx_1__0_:prog_clk[0] 0.001832589 +11 ctsbuf_net_1019:4 ctsbuf_net_1019:3 0.00341 +12 ctsbuf_net_1019:12 ctsbuf_net_1019:11 0.00341 +13 ctsbuf_net_1019:12 ctsbuf_net_1019:10 0.02314956 +14 ctsbuf_net_1019:11 cby_1__1_:prog_clk[0] 0.001031258 +15 ctsbuf_net_1019:13 ctsbuf_net_1019:12 0.0004107143 +16 ctsbuf_net_1019:7 ctsbuf_net_1019:6 0.04442634 +17 ctsbuf_net_1019:10 ctsbuf_net_1019:9 0.02522768 +18 ctsbuf_net_1019:9 ctsbuf_net_1019:8 1e-05 +19 ctsbuf_net_1019:8 ctsbuf_net_1019:7 0.01941429 + +*END + +*D_NET ctsbuf_net_2130 0.1368493 //LENGTH 1158.200 LUMPCC 0.009859205 DR + +*CONN +*I cts_inv_73847659:Y O *L 0 *C 276.920 616.420 +*I cts_inv_73647639:A I *L 0.005046 *C 276.460 637.650 +*I cts_inv_73547629:A I *L 0.005046 *C 276.460 640.560 +*I cts_inv_73627637:A I *L 0.005046 *C 368.460 779.355 +*I cts_inv_73587633:A I *L 0.005046 *C 420.440 898.805 +*I cts_inv_73567631:A I *L 0.005046 *C 541.420 779.355 +*I cts_inv_73557630:A I *L 0.005046 *C 629.740 779.280 +*I cts_inv_73527627:A I *L 0.005046 *C 564.420 898.815 +*N ctsbuf_net_2130:8 *C 564.420 898.815 +*N ctsbuf_net_2130:9 *C 564.420 898.815 +*N ctsbuf_net_2130:10 *C 564.413 898.960 +*N ctsbuf_net_2130:11 *C 559.180 898.960 +*N ctsbuf_net_2130:12 *C 517.960 898.960 +*N ctsbuf_net_2130:13 *C 517.960 898.960 +*N ctsbuf_net_2130:14 *C 517.960 891.520 +*N ctsbuf_net_2130:15 *C 517.960 891.519 +*N ctsbuf_net_2130:16 *C 517.960 860.940 +*N ctsbuf_net_2130:17 *C 517.960 811.240 +*N ctsbuf_net_2130:18 *C 517.960 811.240 +*N ctsbuf_net_2130:19 *C 542.800 811.240 +*N ctsbuf_net_2130:20 *C 542.800 811.240 +*N ctsbuf_net_2130:21 *C 629.740 779.370 +*N ctsbuf_net_2130:22 *C 629.740 779.370 +*N ctsbuf_net_2130:23 *C 629.740 781.942 +*N ctsbuf_net_2130:24 *C 629.733 782.000 +*N ctsbuf_net_2130:25 *C 627.075 782.000 +*N ctsbuf_net_2130:26 *C 592.500 782.000 +*N ctsbuf_net_2130:27 *C 542.800 782.000 +*N ctsbuf_net_2130:28 *C 542.800 782.000 +*N ctsbuf_net_2130:29 *C 541.420 779.355 +*N ctsbuf_net_2130:30 *C 542.340 779.100 +*N ctsbuf_net_2130:31 *C 542.340 779.100 +*N ctsbuf_net_2130:32 *C 542.340 779.280 +*N ctsbuf_net_2130:33 *C 542.340 779.280 +*N ctsbuf_net_2130:34 *C 542.788 779.280 +*N ctsbuf_net_2130:35 *C 542.800 779.280 +*N ctsbuf_net_2130:36 *C 542.800 738.220 +*N ctsbuf_net_2130:37 *C 542.800 688.220 +*N ctsbuf_net_2130:38 *C 542.800 667.520 +*N ctsbuf_net_2130:39 *C 542.800 667.519 +*N ctsbuf_net_2130:40 *C 542.800 638.520 +*N ctsbuf_net_2130:41 *C 542.800 638.520 +*N ctsbuf_net_2130:42 *C 525.060 638.520 +*N ctsbuf_net_2130:43 *C 475.060 638.520 +*N ctsbuf_net_2130:44 *C 443.520 638.520 +*N ctsbuf_net_2130:45 *C 443.519 638.520 +*N ctsbuf_net_2130:46 *C 425.060 638.520 +*N ctsbuf_net_2130:47 *C 375.360 638.520 +*N ctsbuf_net_2130:48 *C 375.360 638.520 +*N ctsbuf_net_2130:49 *C 375.360 660.960 +*N ctsbuf_net_2130:50 *C 375.360 660.960 +*N ctsbuf_net_2130:51 *C 332.440 660.960 +*N ctsbuf_net_2130:52 *C 420.440 898.715 +*N ctsbuf_net_2130:53 *C 420.440 898.715 +*N ctsbuf_net_2130:54 *C 420.373 898.960 +*N ctsbuf_net_2130:55 *C 419.980 898.960 +*N ctsbuf_net_2130:56 *C 419.973 898.960 +*N ctsbuf_net_2130:57 *C 415.210 898.960 +*N ctsbuf_net_2130:58 *C 402.960 898.960 +*N ctsbuf_net_2130:59 *C 402.960 898.960 +*N ctsbuf_net_2130:60 *C 402.960 891.520 +*N ctsbuf_net_2130:61 *C 402.960 891.519 +*N ctsbuf_net_2130:62 *C 402.960 858.220 +*N ctsbuf_net_2130:63 *C 402.960 808.520 +*N ctsbuf_net_2130:64 *C 402.960 808.520 +*N ctsbuf_net_2130:65 *C 375.360 808.520 +*N ctsbuf_net_2130:66 *C 375.360 808.520 +*N ctsbuf_net_2130:67 *C 375.360 783.360 +*N ctsbuf_net_2130:68 *C 375.360 783.360 +*N ctsbuf_net_2130:69 *C 368.460 779.355 +*N ctsbuf_net_2130:70 *C 369.840 779.215 +*N ctsbuf_net_2130:71 *C 369.840 779.215 +*N ctsbuf_net_2130:72 *C 369.840 783.303 +*N ctsbuf_net_2130:73 *C 369.840 783.360 +*N ctsbuf_net_2130:74 *C 332.140 783.360 +*N ctsbuf_net_2130:75 *C 282.440 783.360 +*N ctsbuf_net_2130:76 *C 282.440 783.360 +*N ctsbuf_net_2130:77 *C 282.440 760.660 +*N ctsbuf_net_2130:78 *C 282.440 710.660 +*N ctsbuf_net_2130:79 *C 282.440 667.520 +*N ctsbuf_net_2130:80 *C 282.440 667.519 +*N ctsbuf_net_2130:81 *C 282.440 660.960 +*N ctsbuf_net_2130:82 *C 282.440 660.960 +*N ctsbuf_net_2130:83 *C 280.600 660.960 +*N ctsbuf_net_2130:84 *C 280.600 660.960 +*N ctsbuf_net_2130:85 *C 276.460 640.470 +*N ctsbuf_net_2130:86 *C 276.460 640.470 +*N ctsbuf_net_2130:87 *C 276.460 637.740 +*N ctsbuf_net_2130:88 *C 276.460 637.740 +*N ctsbuf_net_2130:89 *C 276.460 638.520 +*N ctsbuf_net_2130:90 *C 276.460 638.520 +*N ctsbuf_net_2130:91 *C 280.600 638.520 +*N ctsbuf_net_2130:92 *C 280.600 638.520 +*N ctsbuf_net_2130:93 *C 280.600 618.048 +*N ctsbuf_net_2130:94 *C 280.600 617.440 +*N ctsbuf_net_2130:95 *C 280.580 617.440 +*N ctsbuf_net_2130:96 *C 276.928 617.440 +*N ctsbuf_net_2130:97 *C 276.920 617.383 +*N ctsbuf_net_2130:98 *C 276.920 616.510 +*N ctsbuf_net_2130:99 *C 276.920 616.510 + +*CAP +0 cts_inv_73847659:Y 1e-06 +1 cts_inv_73647639:A 1e-06 +2 cts_inv_73547629:A 1e-06 +3 cts_inv_73627637:A 1e-06 +4 cts_inv_73587633:A 1e-06 +5 cts_inv_73567631:A 1e-06 +6 cts_inv_73557630:A 1e-06 +7 cts_inv_73527627:A 1e-06 +8 ctsbuf_net_2130:8 3.835392e-05 +9 ctsbuf_net_2130:9 3.659839e-05 +10 ctsbuf_net_2130:10 0.0003025246 +11 ctsbuf_net_2130:11 0.002450118 +12 ctsbuf_net_2130:12 0.002147594 +13 ctsbuf_net_2130:13 0.0003250749 +14 ctsbuf_net_2130:14 0.0003250749 +15 ctsbuf_net_2130:15 0.001770778 +16 ctsbuf_net_2130:16 0.004909382 +17 ctsbuf_net_2130:17 0.003138605 +18 ctsbuf_net_2130:18 0.001277587 +19 ctsbuf_net_2130:19 0.001277587 +20 ctsbuf_net_2130:20 0.001632631 +21 ctsbuf_net_2130:21 4.978568e-05 +22 ctsbuf_net_2130:22 0.0001987317 +23 ctsbuf_net_2130:23 0.0001546379 +24 ctsbuf_net_2130:24 0.0001352131 +25 ctsbuf_net_2130:25 0.001577787 +26 ctsbuf_net_2130:26 0.003533141 +27 ctsbuf_net_2130:27 0.002090567 +28 ctsbuf_net_2130:28 0.00182218 +29 ctsbuf_net_2130:29 0.0001272241 +30 ctsbuf_net_2130:30 0.0001181566 +31 ctsbuf_net_2130:31 5.64167e-05 +32 ctsbuf_net_2130:32 5.317981e-05 +33 ctsbuf_net_2130:33 4.799104e-05 +34 ctsbuf_net_2130:34 4.799104e-05 +35 ctsbuf_net_2130:35 0.00270932 +36 ctsbuf_net_2130:36 0.00520502 +37 ctsbuf_net_2130:37 0.003838585 +38 ctsbuf_net_2130:38 0.001153335 +39 ctsbuf_net_2130:39 0.001719009 +40 ctsbuf_net_2130:40 0.001719009 +41 ctsbuf_net_2130:41 0.001027273 +42 ctsbuf_net_2130:42 0.003912362 +43 ctsbuf_net_2130:43 0.004662341 +44 ctsbuf_net_2130:44 0.001777252 +45 ctsbuf_net_2130:45 0.001062401 +46 ctsbuf_net_2130:46 0.003934301 +47 ctsbuf_net_2130:47 0.0028719 +48 ctsbuf_net_2130:48 0.001201229 +49 ctsbuf_net_2130:49 0.001201229 +50 ctsbuf_net_2130:50 0.002687109 +51 ctsbuf_net_2130:51 0.005892755 +52 ctsbuf_net_2130:52 4.014453e-05 +53 ctsbuf_net_2130:53 4.315415e-05 +54 ctsbuf_net_2130:54 5.961936e-05 +55 ctsbuf_net_2130:55 6.635935e-05 +56 ctsbuf_net_2130:56 0.0001697408 +57 ctsbuf_net_2130:57 0.0007847547 +58 ctsbuf_net_2130:58 0.0006150139 +59 ctsbuf_net_2130:59 0.000377906 +60 ctsbuf_net_2130:60 0.000377906 +61 ctsbuf_net_2130:61 0.002413674 +62 ctsbuf_net_2130:62 0.00583778 +63 ctsbuf_net_2130:63 0.003424107 +64 ctsbuf_net_2130:64 0.001198589 +65 ctsbuf_net_2130:65 0.001198589 +66 ctsbuf_net_2130:66 0.001132458 +67 ctsbuf_net_2130:67 0.001132458 +68 ctsbuf_net_2130:68 0.000316159 +69 ctsbuf_net_2130:69 0.0001263465 +70 ctsbuf_net_2130:70 0.0001307226 +71 ctsbuf_net_2130:71 0.0002776376 +72 ctsbuf_net_2130:72 0.00023351 +73 ctsbuf_net_2130:73 0.002700238 +74 ctsbuf_net_2130:74 0.005036248 +75 ctsbuf_net_2130:75 0.002652169 +76 ctsbuf_net_2130:76 0.001185824 +77 ctsbuf_net_2130:77 0.00343047 +78 ctsbuf_net_2130:78 0.00417984 +79 ctsbuf_net_2130:79 0.001935195 +80 ctsbuf_net_2130:80 0.0003811871 +81 ctsbuf_net_2130:81 0.0003811871 +82 ctsbuf_net_2130:82 0.003331664 +83 ctsbuf_net_2130:83 0.0001260188 +84 ctsbuf_net_2130:84 0.0009828813 +85 ctsbuf_net_2130:85 4.206324e-05 +86 ctsbuf_net_2130:86 0.0001499002 +87 ctsbuf_net_2130:87 4.34419e-05 +88 ctsbuf_net_2130:88 8.690335e-05 +89 ctsbuf_net_2130:89 0.0001943838 +90 ctsbuf_net_2130:90 0.0003025295 +91 ctsbuf_net_2130:91 0.0003025295 +92 ctsbuf_net_2130:92 0.001829214 +93 ctsbuf_net_2130:93 0.0008893652 +94 ctsbuf_net_2130:94 4.303228e-05 +95 ctsbuf_net_2130:95 0.0001983579 +96 ctsbuf_net_2130:96 0.0001983579 +97 ctsbuf_net_2130:97 6.157363e-05 +98 ctsbuf_net_2130:98 9.825337e-05 +99 ctsbuf_net_2130:99 4.328022e-05 +100 ctsbuf_net_2130:27 Test_en[0]:8 0.0003870621 +101 ctsbuf_net_2130:27 Test_en[0]:9 8.925112e-06 +102 ctsbuf_net_2130:24 Test_en[0]:10 2.493984e-05 +103 ctsbuf_net_2130:25 Test_en[0]:9 2.493984e-05 +104 ctsbuf_net_2130:25 Test_en[0]:10 0.0002743822 +105 ctsbuf_net_2130:26 Test_en[0]:9 0.0006614443 +106 ctsbuf_net_2130:26 Test_en[0]:10 8.925112e-06 +107 ctsbuf_net_2130:34 clk[0]:22 1.241664e-05 +108 ctsbuf_net_2130:33 grid_clb_1__2_:clk[0] 1.241664e-05 +109 ctsbuf_net_2130:27 grid_clb_1__2_:clk[0] 7.118451e-05 +110 ctsbuf_net_2130:27 clk[0]:23 0.000800427 +111 ctsbuf_net_2130:25 clk[0]:24 3.997418e-05 +112 ctsbuf_net_2130:25 clk[0]:25 0.0005526321 +113 ctsbuf_net_2130:26 clk[0]:22 7.118451e-05 +114 ctsbuf_net_2130:26 clk[0]:23 3.997418e-05 +115 ctsbuf_net_2130:26 clk[0]:24 0.001353059 +116 ctsbuf_net_2130:17 cbx_1__2__0_chanx_right_out[2]:3 5.239841e-05 +117 ctsbuf_net_2130:13 cbx_1__2__0_chanx_right_out[2]:6 2.804113e-05 +118 ctsbuf_net_2130:16 cbx_1__2__0_chanx_right_out[2]:3 0.0004140867 +119 ctsbuf_net_2130:16 cbx_1__2__0_chanx_right_out[2]:4 5.239841e-05 +120 ctsbuf_net_2130:14 cbx_1__2__0_chanx_right_out[2]:5 2.804113e-05 +121 ctsbuf_net_2130:15 cbx_1__2__0_chanx_right_out[2]:4 0.0004140867 +122 ctsbuf_net_2130:17 cbx_1__2__0_chanx_right_out[5]:4 0.0002768406 +123 ctsbuf_net_2130:16 cbx_1__2__0_chanx_right_out[5]:3 0.0002768406 +124 ctsbuf_net_2130:20 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:3 0.0002772941 +125 ctsbuf_net_2130:28 grid_clb_1_right_width_0_height_0__pin_41_upper[0]:4 0.0002772941 +126 ctsbuf_net_2130:82 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 8.736921e-06 +127 ctsbuf_net_2130:82 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 4.039568e-05 +128 ctsbuf_net_2130:83 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 8.736921e-06 +129 ctsbuf_net_2130:51 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 4.039568e-05 +130 ctsbuf_net_2130:58 ctsbuf_net_918:5 0.0001685696 +131 ctsbuf_net_2130:56 ctsbuf_net_918:6 9.265107e-05 +132 ctsbuf_net_2130:57 ctsbuf_net_918:5 9.265107e-05 +133 ctsbuf_net_2130:57 ctsbuf_net_918:6 0.0001685696 +134 ctsbuf_net_2130:69 ctsbuf_net_1322:12 1.922761e-05 +135 ctsbuf_net_2130:70 ctsbuf_net_1322:11 1.922761e-05 +136 ctsbuf_net_2130:67 ctsbuf_net_1322:7 3.047685e-05 +137 ctsbuf_net_2130:67 ctsbuf_net_1322:10 1.347071e-05 +138 ctsbuf_net_2130:65 ctsbuf_net_1322:5 0.0007356532 +139 ctsbuf_net_2130:66 ctsbuf_net_1322:6 3.047685e-05 +140 ctsbuf_net_2130:66 ctsbuf_net_1322:9 1.347071e-05 +141 ctsbuf_net_2130:64 ctsbuf_net_1322:4 0.0007356532 +142 ctsbuf_net_2130:75 ctsbuf_net_1524:8 2.035789e-05 +143 ctsbuf_net_2130:75 ctsbuf_net_1524:9 0.0004934358 +144 ctsbuf_net_2130:92 ctsbuf_net_1524:21 8.602231e-05 +145 ctsbuf_net_2130:84 ctsbuf_net_1524:18 4.599952e-05 +146 ctsbuf_net_2130:93 ctsbuf_net_1524:20 4.002279e-05 +147 ctsbuf_net_2130:74 ctsbuf_net_1524:6 0.0004934358 +148 ctsbuf_net_2130:74 ctsbuf_net_1524:9 2.035789e-05 + +*RES +0 cts_inv_73847659:Y ctsbuf_net_2130:99 0.152 +1 ctsbuf_net_2130:75 ctsbuf_net_2130:74 0.003893166 +2 ctsbuf_net_2130:76 ctsbuf_net_2130:75 0.00341 +3 ctsbuf_net_2130:82 ctsbuf_net_2130:81 0.00341 +4 ctsbuf_net_2130:82 ctsbuf_net_2130:51 0.003916666 +5 ctsbuf_net_2130:81 ctsbuf_net_2130:80 0.0005137883 +6 ctsbuf_net_2130:69 cts_inv_73627637:A 0.152 +7 ctsbuf_net_2130:70 ctsbuf_net_2130:69 0.001232143 +8 ctsbuf_net_2130:71 ctsbuf_net_2130:70 0.0045 +9 ctsbuf_net_2130:72 ctsbuf_net_2130:71 0.003649554 +10 ctsbuf_net_2130:73 ctsbuf_net_2130:72 0.00341 +11 ctsbuf_net_2130:73 ctsbuf_net_2130:68 0.0004324 +12 ctsbuf_net_2130:41 ctsbuf_net_2130:40 0.00341 +13 ctsbuf_net_2130:40 ctsbuf_net_2130:39 0.002271588 +14 ctsbuf_net_2130:47 ctsbuf_net_2130:46 0.003893166 +15 ctsbuf_net_2130:48 ctsbuf_net_2130:47 0.00341 +16 ctsbuf_net_2130:50 ctsbuf_net_2130:49 0.00341 +17 ctsbuf_net_2130:49 ctsbuf_net_2130:48 0.0017578 +18 ctsbuf_net_2130:68 ctsbuf_net_2130:67 0.00341 +19 ctsbuf_net_2130:67 ctsbuf_net_2130:66 0.001970866 +20 ctsbuf_net_2130:65 ctsbuf_net_2130:64 0.002162 +21 ctsbuf_net_2130:66 ctsbuf_net_2130:65 0.00341 +22 ctsbuf_net_2130:64 ctsbuf_net_2130:63 0.00341 +23 ctsbuf_net_2130:63 ctsbuf_net_2130:62 0.003893166 +24 ctsbuf_net_2130:58 ctsbuf_net_2130:57 0.0009595833 +25 ctsbuf_net_2130:59 ctsbuf_net_2130:58 0.00341 +26 ctsbuf_net_2130:55 ctsbuf_net_2130:54 0.0003504464 +27 ctsbuf_net_2130:56 ctsbuf_net_2130:55 0.00341 +28 ctsbuf_net_2130:52 cts_inv_73587633:A 0.152 +29 ctsbuf_net_2130:53 ctsbuf_net_2130:52 0.0045 +30 ctsbuf_net_2130:89 ctsbuf_net_2130:88 0.0006964286 +31 ctsbuf_net_2130:89 ctsbuf_net_2130:86 0.001741072 +32 ctsbuf_net_2130:90 ctsbuf_net_2130:89 0.00341 +33 ctsbuf_net_2130:91 ctsbuf_net_2130:90 0.0003243 +34 ctsbuf_net_2130:92 ctsbuf_net_2130:91 0.00341 +35 ctsbuf_net_2130:92 ctsbuf_net_2130:84 0.0017578 +36 ctsbuf_net_2130:95 ctsbuf_net_2130:94 0.00341 +37 ctsbuf_net_2130:94 ctsbuf_net_2130:93 8.652273e-05 +38 ctsbuf_net_2130:97 ctsbuf_net_2130:96 0.00341 +39 ctsbuf_net_2130:96 ctsbuf_net_2130:95 0.000572225 +40 ctsbuf_net_2130:99 ctsbuf_net_2130:98 0.0045 +41 ctsbuf_net_2130:98 ctsbuf_net_2130:97 0.0007790179 +42 ctsbuf_net_2130:34 ctsbuf_net_2130:33 6.373485e-05 +43 ctsbuf_net_2130:35 ctsbuf_net_2130:34 0.00341 +44 ctsbuf_net_2130:35 ctsbuf_net_2130:28 0.0002130667 +45 ctsbuf_net_2130:32 ctsbuf_net_2130:31 8.035715e-05 +46 ctsbuf_net_2130:33 ctsbuf_net_2130:32 0.00341 +47 ctsbuf_net_2130:30 ctsbuf_net_2130:29 0.0008214287 +48 ctsbuf_net_2130:31 ctsbuf_net_2130:30 0.0045 +49 ctsbuf_net_2130:29 cts_inv_73567631:A 0.152 +50 ctsbuf_net_2130:83 ctsbuf_net_2130:82 0.0001441333 +51 ctsbuf_net_2130:84 ctsbuf_net_2130:83 0.00341 +52 ctsbuf_net_2130:87 cts_inv_73647639:A 0.152 +53 ctsbuf_net_2130:88 ctsbuf_net_2130:87 0.0045 +54 ctsbuf_net_2130:19 ctsbuf_net_2130:18 0.0019458 +55 ctsbuf_net_2130:20 ctsbuf_net_2130:19 0.00341 +56 ctsbuf_net_2130:18 ctsbuf_net_2130:17 0.00341 +57 ctsbuf_net_2130:17 ctsbuf_net_2130:16 0.003893166 +58 ctsbuf_net_2130:12 ctsbuf_net_2130:11 0.0032289 +59 ctsbuf_net_2130:13 ctsbuf_net_2130:12 0.00341 +60 ctsbuf_net_2130:9 ctsbuf_net_2130:8 0.0045 +61 ctsbuf_net_2130:10 ctsbuf_net_2130:9 0.00341 +62 ctsbuf_net_2130:8 cts_inv_73527627:A 0.152 +63 ctsbuf_net_2130:85 cts_inv_73547629:A 0.152 +64 ctsbuf_net_2130:86 ctsbuf_net_2130:85 0.0045 +65 ctsbuf_net_2130:27 ctsbuf_net_2130:26 0.003893166 +66 ctsbuf_net_2130:28 ctsbuf_net_2130:27 0.00341 +67 ctsbuf_net_2130:28 ctsbuf_net_2130:20 0.002290467 +68 ctsbuf_net_2130:23 ctsbuf_net_2130:22 0.002296875 +69 ctsbuf_net_2130:24 ctsbuf_net_2130:23 0.00341 +70 ctsbuf_net_2130:21 cts_inv_73557630:A 0.152 +71 ctsbuf_net_2130:22 ctsbuf_net_2130:21 0.0045 +72 ctsbuf_net_2130:54 ctsbuf_net_2130:53 0.0001331522 +73 ctsbuf_net_2130:57 ctsbuf_net_2130:56 0.0007461249 +74 ctsbuf_net_2130:11 ctsbuf_net_2130:10 0.0008197583 +75 ctsbuf_net_2130:25 ctsbuf_net_2130:24 0.0004163416 +76 ctsbuf_net_2130:93 ctsbuf_net_2130:92 0.001603679 +77 ctsbuf_net_2130:51 ctsbuf_net_2130:50 0.003362067 +78 ctsbuf_net_2130:74 ctsbuf_net_2130:73 0.002953166 +79 ctsbuf_net_2130:46 ctsbuf_net_2130:45 0.001445955 +80 ctsbuf_net_2130:43 ctsbuf_net_2130:42 0.003916666 +81 ctsbuf_net_2130:42 ctsbuf_net_2130:41 0.001389633 +82 ctsbuf_net_2130:26 ctsbuf_net_2130:25 0.002708375 +83 ctsbuf_net_2130:78 ctsbuf_net_2130:77 0.003916666 +84 ctsbuf_net_2130:77 ctsbuf_net_2130:76 0.001778167 +85 ctsbuf_net_2130:62 ctsbuf_net_2130:61 0.002608421 +86 ctsbuf_net_2130:16 ctsbuf_net_2130:15 0.002395355 +87 ctsbuf_net_2130:37 ctsbuf_net_2130:36 0.003916666 +88 ctsbuf_net_2130:36 ctsbuf_net_2130:35 0.003216367 +89 ctsbuf_net_2130:60 ctsbuf_net_2130:59 0.0005828 +90 ctsbuf_net_2130:61 ctsbuf_net_2130:60 1e-05 +91 ctsbuf_net_2130:14 ctsbuf_net_2130:13 0.0005828 +92 ctsbuf_net_2130:15 ctsbuf_net_2130:14 1e-05 +93 ctsbuf_net_2130:44 ctsbuf_net_2130:43 0.002470633 +94 ctsbuf_net_2130:45 ctsbuf_net_2130:44 1e-05 +95 ctsbuf_net_2130:79 ctsbuf_net_2130:78 0.0033793 +96 ctsbuf_net_2130:80 ctsbuf_net_2130:79 1e-05 +97 ctsbuf_net_2130:38 ctsbuf_net_2130:37 0.0016215 +98 ctsbuf_net_2130:39 ctsbuf_net_2130:38 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_A[3] 0.03291171 //LENGTH 307.095 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__2_:gfpga_pad_GPIO_A[0] O *L 0 *C 925.370 724.200 +*P gfpga_pad_GPIO_A[3] O *L 0 *C 1199.155 756.840 +*N gfpga_pad_GPIO_A[3]:2 *C 1159.860 756.840 +*N gfpga_pad_GPIO_A[3]:3 *C 1115.520 756.840 +*N gfpga_pad_GPIO_A[3]:4 *C 1115.519 756.840 +*N gfpga_pad_GPIO_A[3]:5 *C 1109.860 756.840 +*N gfpga_pad_GPIO_A[3]:6 *C 1059.860 756.840 +*N gfpga_pad_GPIO_A[3]:7 *C 1009.860 756.840 +*N gfpga_pad_GPIO_A[3]:8 *C 960.065 756.840 +*N gfpga_pad_GPIO_A[3]:9 *C 960.020 756.795 +*N gfpga_pad_GPIO_A[3]:10 *C 960.020 724.258 +*N gfpga_pad_GPIO_A[3]:11 *C 960.013 724.200 + +*CAP +0 grid_io_right_3__2_:gfpga_pad_GPIO_A[0] 0.00160107 +1 gfpga_pad_GPIO_A[3] 0.002207649 +2 gfpga_pad_GPIO_A[3]:2 0.004677651 +3 gfpga_pad_GPIO_A[3]:3 0.002470001 +4 gfpga_pad_GPIO_A[3]:4 0.0003138183 +5 gfpga_pad_GPIO_A[3]:5 0.00310472 +6 gfpga_pad_GPIO_A[3]:6 0.005587796 +7 gfpga_pad_GPIO_A[3]:7 0.00560333 +8 gfpga_pad_GPIO_A[3]:8 0.002806436 +9 gfpga_pad_GPIO_A[3]:9 0.001469083 +10 gfpga_pad_GPIO_A[3]:10 0.001469083 +11 gfpga_pad_GPIO_A[3]:11 0.00160107 + +*RES +0 grid_io_right_3__2_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[3]:11 0.005427325 +1 gfpga_pad_GPIO_A[3]:10 gfpga_pad_GPIO_A[3]:9 0.02905134 +2 gfpga_pad_GPIO_A[3]:11 gfpga_pad_GPIO_A[3]:10 0.00341 +3 gfpga_pad_GPIO_A[3]:8 gfpga_pad_GPIO_A[3]:7 0.04445983 +4 gfpga_pad_GPIO_A[3]:9 gfpga_pad_GPIO_A[3]:8 0.0045 +5 gfpga_pad_GPIO_A[3]:7 gfpga_pad_GPIO_A[3]:6 0.04464286 +6 gfpga_pad_GPIO_A[3]:6 gfpga_pad_GPIO_A[3]:5 0.04464286 +7 gfpga_pad_GPIO_A[3]:5 gfpga_pad_GPIO_A[3]:4 0.005052679 +8 gfpga_pad_GPIO_A[3]:2 gfpga_pad_GPIO_A[3] 0.03508483 +9 gfpga_pad_GPIO_A[3]:3 gfpga_pad_GPIO_A[3]:2 0.03958929 +10 gfpga_pad_GPIO_A[3]:4 gfpga_pad_GPIO_A[3]:3 1e-05 + +*END + +*D_NET cbx_1__2__0_chanx_right_out[15] 0.001330066 //LENGTH 7.660 LUMPCC 0.0003817597 DR + +*CONN +*I cbx_1__2_:chanx_right_out[15] O *L 0 *C 512.290 885.360 +*I sb_1__2_:chanx_left_in[15] I *L 0 *C 519.950 885.360 + +*CAP +0 cbx_1__2_:chanx_right_out[15] 0.0004741529 +1 sb_1__2_:chanx_left_in[15] 0.0004741529 +2 cbx_1__2_:chanx_right_out[15] cbx_1__2_:chanx_right_in[1] 4.923313e-05 +3 sb_1__2_:chanx_left_in[15] sb_1__2_:chanx_left_out[1] 4.923313e-05 +4 cbx_1__2_:chanx_right_out[15] cbx_1__2_:chanx_right_in[10] 0.0001416467 +5 sb_1__2_:chanx_left_in[15] sb_1__2_:chanx_left_out[10] 0.0001416467 + +*RES +0 cbx_1__2_:chanx_right_out[15] sb_1__2_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET cbx_1__2__0_top_grid_pin_0_[0] 0.001105868 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__2_:top_grid_pin_0_[0] O *L 0 *C 486.680 892.090 +*I grid_io_top_1__3_:bottom_width_0_height_0__pin_0_[0] I *L 0 *C 486.680 903.110 + +*CAP +0 cbx_1__2_:top_grid_pin_0_[0] 0.0005529339 +1 grid_io_top_1__3_:bottom_width_0_height_0__pin_0_[0] 0.0005529339 + +*RES +0 cbx_1__2_:top_grid_pin_0_[0] grid_io_top_1__3_:bottom_width_0_height_0__pin_0_[0] 0.009839286 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[2] 0.001338602 //LENGTH 7.660 LUMPCC 0.0001020464 DR + +*CONN +*I cbx_2__2_:chanx_left_out[2] O *L 0 *C 668.990 888.080 +*I sb_1__2_:chanx_right_in[2] I *L 0 *C 661.330 888.080 +*N cbx_1__2__1_chanx_left_out[2]:2 *C 667.519 888.080 +*N cbx_1__2__1_chanx_left_out[2]:3 *C 667.520 888.080 + +*CAP +0 cbx_2__2_:chanx_left_out[2] 0.0002103571 +1 sb_1__2_:chanx_right_in[2] 0.0004079208 +2 cbx_1__2__1_chanx_left_out[2]:2 0.0004079208 +3 cbx_1__2__1_chanx_left_out[2]:3 0.0002103571 +4 sb_1__2_:chanx_right_in[2] sb_1__2_:chanx_right_in[3] 5.102319e-05 +5 cbx_1__2__1_chanx_left_out[2]:2 cbx_1__2__1_chanx_left_out[3]:2 5.102319e-05 + +*RES +0 cbx_2__2_:chanx_left_out[2] cbx_1__2__1_chanx_left_out[2]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[2]:3 cbx_1__2__1_chanx_left_out[2]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[2]:2 sb_1__2_:chanx_right_in[2] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[4] 0.001483121 //LENGTH 7.660 LUMPCC 0.0003210523 DR + +*CONN +*I cbx_2__2_:chanx_left_out[4] O *L 0 *C 668.990 822.800 +*I sb_1__2_:chanx_right_in[4] I *L 0 *C 661.330 822.800 +*N cbx_1__2__1_chanx_left_out[4]:2 *C 667.519 822.800 +*N cbx_1__2__1_chanx_left_out[4]:3 *C 667.520 822.800 + +*CAP +0 cbx_2__2_:chanx_left_out[4] 0.0002200254 +1 sb_1__2_:chanx_right_in[4] 0.0003610089 +2 cbx_1__2__1_chanx_left_out[4]:2 0.0003610089 +3 cbx_1__2__1_chanx_left_out[4]:3 0.0002200254 +4 sb_1__2_:chanx_right_in[4] sb_1__2_:chanx_right_in[6] 5.142411e-05 +5 cbx_1__2__1_chanx_left_out[4]:2 cbx_1__2__1_chanx_left_out[6]:2 5.142411e-05 +6 sb_1__2_:chanx_right_in[4] sb_1__2_:chanx_right_in[9] 0.000109102 +7 cbx_1__2__1_chanx_left_out[4]:2 cbx_1__2__1_chanx_left_out[9]:2 0.000109102 + +*RES +0 cbx_2__2_:chanx_left_out[4] cbx_1__2__1_chanx_left_out[4]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[4]:3 cbx_1__2__1_chanx_left_out[4]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[4]:2 sb_1__2_:chanx_right_in[4] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[8] 0.001337126 //LENGTH 7.660 LUMPCC 0.0004164221 DR + +*CONN +*I cbx_2__2_:chanx_left_out[8] O *L 0 *C 668.990 866.320 +*I sb_1__2_:chanx_right_in[8] I *L 0 *C 661.330 866.320 +*N cbx_1__2__1_chanx_left_out[8]:2 *C 667.519 866.320 +*N cbx_1__2__1_chanx_left_out[8]:3 *C 667.520 866.320 + +*CAP +0 cbx_2__2_:chanx_left_out[8] 0.0001868447 +1 sb_1__2_:chanx_right_in[8] 0.0002735075 +2 cbx_1__2__1_chanx_left_out[8]:2 0.0002735075 +3 cbx_1__2__1_chanx_left_out[8]:3 0.0001868447 +4 sb_1__2_:chanx_right_in[8] sb_1__2_:chanx_right_in[12] 6.462134e-05 +5 cbx_1__2__1_chanx_left_out[8]:2 cbx_1__2__1_chanx_left_out[12]:2 6.462134e-05 +6 cbx_2__2_:chanx_left_out[8] cbx_2__2_:chanx_left_in[4] 9.865685e-06 +7 sb_1__2_:chanx_right_in[8] sb_1__2_:chanx_right_out[4] 0.000133724 +8 cbx_1__2__1_chanx_left_out[8]:3 sb_1__2__0_chanx_right_out[4]:2 9.865685e-06 +9 cbx_1__2__1_chanx_left_out[8]:2 sb_1__2__0_chanx_right_out[4]:3 0.000133724 + +*RES +0 cbx_2__2_:chanx_left_out[8] cbx_1__2__1_chanx_left_out[8]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[8]:3 cbx_1__2__1_chanx_left_out[8]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[8]:2 sb_1__2_:chanx_right_in[8] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[13] 0.001473478 //LENGTH 7.660 LUMPCC 0.0003234821 DR + +*CONN +*I cbx_2__2_:chanx_left_out[13] O *L 0 *C 668.990 825.520 +*I sb_1__2_:chanx_right_in[13] I *L 0 *C 661.330 825.520 +*N cbx_1__2__1_chanx_left_out[13]:2 *C 667.519 825.520 +*N cbx_1__2__1_chanx_left_out[13]:3 *C 667.520 825.520 + +*CAP +0 cbx_2__2_:chanx_left_out[13] 0.0002200131 +1 sb_1__2_:chanx_right_in[13] 0.0003549849 +2 cbx_1__2__1_chanx_left_out[13]:2 0.0003549849 +3 cbx_1__2__1_chanx_left_out[13]:3 0.0002200131 +4 sb_1__2_:chanx_right_in[13] sb_1__2_:chanx_right_in[9] 0.000109102 +5 cbx_1__2__1_chanx_left_out[13]:2 cbx_1__2__1_chanx_left_out[9]:2 0.000109102 +6 sb_1__2_:chanx_right_in[13] sb_1__2_:chanx_right_in[18] 5.263901e-05 +7 cbx_1__2__1_chanx_left_out[13]:2 cbx_1__2__1_chanx_left_out[18]:2 5.263901e-05 + +*RES +0 cbx_2__2_:chanx_left_out[13] cbx_1__2__1_chanx_left_out[13]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[13]:3 cbx_1__2__1_chanx_left_out[13]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[13]:2 sb_1__2_:chanx_right_in[13] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[17] 0.001380884 //LENGTH 7.660 LUMPCC 0.0003695511 DR + +*CONN +*I cbx_2__2_:chanx_left_out[17] O *L 0 *C 668.990 850.000 +*I sb_1__2_:chanx_right_in[17] I *L 0 *C 661.330 850.000 +*N cbx_1__2__1_chanx_left_out[17]:2 *C 667.519 850.000 +*N cbx_1__2__1_chanx_left_out[17]:3 *C 667.520 850.000 + +*CAP +0 cbx_2__2_:chanx_left_out[17] 0.0002095016 +1 sb_1__2_:chanx_right_in[17] 0.000296165 +2 cbx_1__2__1_chanx_left_out[17]:2 0.000296165 +3 cbx_1__2__1_chanx_left_out[17]:3 0.0002095016 +4 sb_1__2_:chanx_right_in[17] sb_1__2_:chanx_right_in[5] 0.0001207714 +5 cbx_1__2__1_chanx_left_out[17]:2 cbx_1__2__1_chanx_left_out[5]:2 0.0001207714 +6 sb_1__2_:chanx_right_in[17] sb_1__2_:chanx_right_in[11] 6.400417e-05 +7 cbx_1__2__1_chanx_left_out[17]:2 cbx_1__2__1_chanx_left_out[11]:2 6.400417e-05 + +*RES +0 cbx_2__2_:chanx_left_out[17] cbx_1__2__1_chanx_left_out[17]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[17]:3 cbx_1__2__1_chanx_left_out[17]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[17]:2 sb_1__2_:chanx_right_in[17] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_left_out[19] 0.001422654 //LENGTH 7.660 LUMPCC 0.0003677196 DR + +*CONN +*I cbx_2__2_:chanx_left_out[19] O *L 0 *C 668.990 860.880 +*I sb_1__2_:chanx_right_in[19] I *L 0 *C 661.330 860.880 +*N cbx_1__2__1_chanx_left_out[19]:2 *C 667.519 860.880 +*N cbx_1__2__1_chanx_left_out[19]:3 *C 667.520 860.880 + +*CAP +0 cbx_2__2_:chanx_left_out[19] 0.0002199879 +1 sb_1__2_:chanx_right_in[19] 0.0003074795 +2 cbx_1__2__1_chanx_left_out[19]:2 0.0003074795 +3 cbx_1__2__1_chanx_left_out[19]:3 0.0002199879 +4 sb_1__2_:chanx_right_in[19] sb_1__2_:chanx_right_out[0] 0.0001213686 +5 cbx_1__2__1_chanx_left_out[19]:2 sb_1__2__0_chanx_right_out[0]:3 0.0001213686 +6 sb_1__2_:chanx_right_in[19] sb_1__2_:chanx_right_out[11] 6.249115e-05 +7 cbx_1__2__1_chanx_left_out[19]:2 sb_1__2__0_chanx_right_out[11]:3 6.249115e-05 + +*RES +0 cbx_2__2_:chanx_left_out[19] cbx_1__2__1_chanx_left_out[19]:3 0.0002303 +1 cbx_1__2__1_chanx_left_out[19]:3 cbx_1__2__1_chanx_left_out[19]:2 1e-05 +2 cbx_1__2__1_chanx_left_out[19]:2 sb_1__2_:chanx_right_in[19] 0.0009696099 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[5] 0.003454699 //LENGTH 31.270 LUMPCC 0.000160715 DR + +*CONN +*I cbx_2__2_:chanx_right_out[5] O *L 0 *C 771.420 816.070 +*I sb_2__2_:chanx_left_in[5] I *L 0 *C 781.230 835.040 +*N cbx_1__2__1_chanx_right_out[5]:2 *C 778.327 835.040 +*N cbx_1__2__1_chanx_right_out[5]:3 *C 778.320 834.983 +*N cbx_1__2__1_chanx_right_out[5]:4 *C 778.320 815.365 +*N cbx_1__2__1_chanx_right_out[5]:5 *C 778.275 815.320 +*N cbx_1__2__1_chanx_right_out[5]:6 *C 771.465 815.320 +*N cbx_1__2__1_chanx_right_out[5]:7 *C 771.420 815.365 + +*CAP +0 cbx_2__2_:chanx_right_out[5] 6.086217e-05 +1 sb_2__2_:chanx_left_in[5] 0.0002444395 +2 cbx_1__2__1_chanx_right_out[5]:2 0.0002444395 +3 cbx_1__2__1_chanx_right_out[5]:3 0.0009412136 +4 cbx_1__2__1_chanx_right_out[5]:4 0.0009412136 +5 cbx_1__2__1_chanx_right_out[5]:5 0.0004004769 +6 cbx_1__2__1_chanx_right_out[5]:6 0.0004004769 +7 cbx_1__2__1_chanx_right_out[5]:7 6.086217e-05 +8 sb_2__2_:chanx_left_in[5] sb_2__2_:chanx_left_out[7] 4.298147e-05 +9 cbx_1__2__1_chanx_right_out[5]:2 cbx_2__2_:chanx_right_in[7] 4.298147e-05 +10 sb_2__2_:chanx_left_in[5] sb_2__2_:chanx_left_out[15] 3.737602e-05 +11 cbx_1__2__1_chanx_right_out[5]:2 cbx_2__2_:chanx_right_in[15] 3.737602e-05 + +*RES +0 cbx_2__2_:chanx_right_out[5] cbx_1__2__1_chanx_right_out[5]:7 0.0006294643 +1 cbx_1__2__1_chanx_right_out[5]:3 cbx_1__2__1_chanx_right_out[5]:2 0.00341 +2 cbx_1__2__1_chanx_right_out[5]:2 sb_2__2_:chanx_left_in[5] 0.0004547249 +3 cbx_1__2__1_chanx_right_out[5]:5 cbx_1__2__1_chanx_right_out[5]:4 0.0045 +4 cbx_1__2__1_chanx_right_out[5]:4 cbx_1__2__1_chanx_right_out[5]:3 0.01751563 +5 cbx_1__2__1_chanx_right_out[5]:6 cbx_1__2__1_chanx_right_out[5]:5 0.006080357 +6 cbx_1__2__1_chanx_right_out[5]:7 cbx_1__2__1_chanx_right_out[5]:6 0.0045 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[9] 0.001392251 //LENGTH 7.660 LUMPCC 0.0002425737 DR + +*CONN +*I cbx_2__2_:chanx_right_out[9] O *L 0 *C 773.570 888.080 +*I sb_2__2_:chanx_left_in[9] I *L 0 *C 781.230 888.080 + +*CAP +0 cbx_2__2_:chanx_right_out[9] 0.0005748386 +1 sb_2__2_:chanx_left_in[9] 0.0005748386 +2 cbx_2__2_:chanx_right_out[9] cbx_2__2_:chanx_right_in[10] 0.0001212868 +3 sb_2__2_:chanx_left_in[9] sb_2__2_:chanx_left_out[10] 0.0001212868 + +*RES +0 cbx_2__2_:chanx_right_out[9] sb_2__2_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[13] 0.001425661 //LENGTH 7.660 LUMPCC 0.0003711316 DR + +*CONN +*I cbx_2__2_:chanx_right_out[13] O *L 0 *C 773.570 863.600 +*I sb_2__2_:chanx_left_in[13] I *L 0 *C 781.230 863.600 + +*CAP +0 cbx_2__2_:chanx_right_out[13] 0.0005272646 +1 sb_2__2_:chanx_left_in[13] 0.0005272646 +2 cbx_2__2_:chanx_right_out[13] cbx_2__2_:chanx_right_out[7] 6.066482e-05 +3 sb_2__2_:chanx_left_in[13] sb_2__2_:chanx_left_in[7] 6.066482e-05 +4 cbx_2__2_:chanx_right_out[13] cbx_2__2_:chanx_right_out[8] 0.000124901 +5 sb_2__2_:chanx_left_in[13] sb_2__2_:chanx_left_in[8] 0.000124901 + +*RES +0 cbx_2__2_:chanx_right_out[13] sb_2__2_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET cbx_1__2__1_chanx_right_out[17] 0.001426202 //LENGTH 7.660 LUMPCC 0.0003655982 DR + +*CONN +*I cbx_2__2_:chanx_right_out[17] O *L 0 *C 773.570 841.840 +*I sb_2__2_:chanx_left_in[17] I *L 0 *C 781.230 841.840 + +*CAP +0 cbx_2__2_:chanx_right_out[17] 0.0005303019 +1 sb_2__2_:chanx_left_in[17] 0.0005303019 +2 cbx_2__2_:chanx_right_out[17] cbx_2__2_:chanx_right_out[4] 6.294859e-05 +3 sb_2__2_:chanx_left_in[17] sb_2__2_:chanx_left_in[4] 6.294859e-05 +4 cbx_2__2_:chanx_right_out[17] cbx_2__2_:chanx_right_in[16] 0.0001198505 +5 sb_2__2_:chanx_left_in[17] sb_2__2_:chanx_left_out[16] 0.0001198505 + +*RES +0 cbx_2__2_:chanx_right_out[17] sb_2__2_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET cby_0__1__0_ccff_tail[0] 0.001488339 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_0__1_:ccff_tail[0] O *L 0 *C 287.190 486.880 +*I grid_io_left_0__1_:ccff_head[0] I *L 0 *C 274.010 486.880 + +*CAP +0 cby_0__1_:ccff_tail[0] 0.0007441696 +1 grid_io_left_0__1_:ccff_head[0] 0.0007441696 + +*RES +0 cby_0__1_:ccff_tail[0] grid_io_left_0__1_:ccff_head[0] 0.002064867 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[3] 0.001245328 //LENGTH 11.020 LUMPCC 0.0005902692 DR + +*CONN +*I cby_0__1_:chany_bottom_out[3] O *L 0 *C 332.580 408.070 +*I sb_0__0_:chany_top_in[3] I *L 0 *C 332.580 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[3] 0.0003275294 +1 sb_0__0_:chany_top_in[3] 0.0003275294 +2 cby_0__1_:chany_bottom_out[3] cby_0__1_:chany_bottom_in[5] 0.0001481706 +3 sb_0__0_:chany_top_in[3] sb_0__0_:chany_top_out[5] 0.0001481706 +4 cby_0__1_:chany_bottom_out[3] cby_0__1_:chany_bottom_in[10] 0.000146964 +5 sb_0__0_:chany_top_in[3] sb_0__0_:chany_top_out[10] 0.000146964 + +*RES +0 cby_0__1_:chany_bottom_out[3] sb_0__0_:chany_top_in[3] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[7] 0.001230984 //LENGTH 11.020 LUMPCC 0.0006017026 DR + +*CONN +*I cby_0__1_:chany_bottom_out[7] O *L 0 *C 355.580 408.070 +*I sb_0__0_:chany_top_in[7] I *L 0 *C 355.580 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[7] 0.0003146408 +1 sb_0__0_:chany_top_in[7] 0.0003146408 +2 cby_0__1_:chany_bottom_out[7] cby_0__1_:chany_bottom_out[0] 0.0001504257 +3 sb_0__0_:chany_top_in[7] sb_0__0_:chany_top_in[0] 0.0001504257 +4 cby_0__1_:chany_bottom_out[7] cby_0__1_:chany_bottom_out[6] 0.0001504257 +5 sb_0__0_:chany_top_in[7] sb_0__0_:chany_top_in[6] 0.0001504257 + +*RES +0 cby_0__1_:chany_bottom_out[7] sb_0__0_:chany_top_in[7] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[12] 0.001130382 //LENGTH 11.020 LUMPCC 0.0003008513 DR + +*CONN +*I cby_0__1_:chany_bottom_out[12] O *L 0 *C 359.260 408.070 +*I sb_0__0_:chany_top_in[12] I *L 0 *C 359.260 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[12] 0.0004147651 +1 sb_0__0_:chany_top_in[12] 0.0004147651 +2 cby_0__1_:chany_bottom_out[12] cby_0__1_:chany_bottom_in[2] 0.0001504257 +3 sb_0__0_:chany_top_in[12] sb_0__0_:chany_top_out[2] 0.0001504257 + +*RES +0 cby_0__1_:chany_bottom_out[12] sb_0__0_:chany_top_in[12] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[17] 0.001366288 //LENGTH 11.180 LUMPCC 0.0002076459 DR + +*CONN +*I cby_0__1_:chany_bottom_out[17] O *L 0 *C 301.760 408.150 +*I sb_0__0_:chany_top_in[17] I *L 0 *C 301.760 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[17] 0.0005793209 +1 sb_0__0_:chany_top_in[17] 0.0005793209 +2 cby_0__1_:chany_bottom_out[17] cby_0__1_:chany_bottom_out[13] 6.979892e-05 +3 sb_0__0_:chany_top_in[17] sb_0__0_:chany_top_in[13] 6.979892e-05 +4 cby_0__1_:chany_bottom_out[17] ctsbuf_net_1625:8 3.402403e-05 +5 sb_0__0_:chany_top_in[17] sb_0__0_:prog_clk[0] 3.402403e-05 + +*RES +0 cby_0__1_:chany_bottom_out[17] sb_0__0_:chany_top_in[17] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_top_out[3] 0.001215373 //LENGTH 11.020 LUMPCC 0.0002600501 DR + +*CONN +*I cby_0__1_:chany_top_out[3] O *L 0 *C 300.840 516.730 +*I sb_0__1_:chany_bottom_in[3] I *L 0 *C 300.840 527.750 + +*CAP +0 cby_0__1_:chany_top_out[3] 0.0004776613 +1 sb_0__1_:chany_bottom_in[3] 0.0004776613 +2 cby_0__1_:chany_top_out[3] cby_0__1_:chany_top_out[1] 0.0001300251 +3 sb_0__1_:chany_bottom_in[3] sb_0__1_:chany_bottom_in[1] 0.0001300251 + +*RES +0 cby_0__1_:chany_top_out[3] sb_0__1_:chany_bottom_in[3] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[7] 0.001224703 //LENGTH 11.020 LUMPCC 0.0002592833 DR + +*CONN +*I cby_0__1_:chany_top_out[7] O *L 0 *C 309.120 516.730 +*I sb_0__1_:chany_bottom_in[7] I *L 0 *C 309.120 527.750 + +*CAP +0 cby_0__1_:chany_top_out[7] 0.00048271 +1 sb_0__1_:chany_bottom_in[7] 0.00048271 +2 cby_0__1_:chany_top_out[7] cby_0__1_:chany_top_out[9] 0.0001296416 +3 sb_0__1_:chany_bottom_in[7] sb_0__1_:chany_bottom_in[9] 0.0001296416 + +*RES +0 cby_0__1_:chany_top_out[7] sb_0__1_:chany_bottom_in[7] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[12] 0.001169206 //LENGTH 11.020 LUMPCC 9.079081e-05 DR + +*CONN +*I cby_0__1_:chany_top_out[12] O *L 0 *C 350.980 516.730 +*I sb_0__1_:chany_bottom_in[12] I *L 0 *C 350.980 527.750 + +*CAP +0 cby_0__1_:chany_top_out[12] 0.0005392078 +1 sb_0__1_:chany_bottom_in[12] 0.0005392078 +2 cby_0__1_:chany_top_out[12] cby_0__1_:chany_top_out[0] 4.539541e-05 +3 sb_0__1_:chany_bottom_in[12] sb_0__1_:chany_bottom_in[0] 4.539541e-05 + +*RES +0 cby_0__1_:chany_top_out[12] sb_0__1_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[17] 0.001260311 //LENGTH 11.020 LUMPCC 0.0004000175 DR + +*CONN +*I cby_0__1_:chany_top_out[17] O *L 0 *C 316.940 516.730 +*I sb_0__1_:chany_bottom_in[17] I *L 0 *C 316.940 527.750 + +*CAP +0 cby_0__1_:chany_top_out[17] 0.0004301466 +1 sb_0__1_:chany_bottom_in[17] 0.0004301466 +2 cby_0__1_:chany_top_out[17] cby_0__1_:chany_top_out[11] 0.0001289588 +3 sb_0__1_:chany_bottom_in[17] sb_0__1_:chany_bottom_in[11] 0.0001289588 +4 cby_0__1_:chany_top_out[17] cby_0__1_:chany_top_in[16] 7.104993e-05 +5 sb_0__1_:chany_bottom_in[17] sb_0__1_:chany_bottom_out[16] 7.104993e-05 + +*RES +0 cby_0__1_:chany_top_out[17] sb_0__1_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_0__1__1_ccff_tail[0] 0.001597696 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_0__2_:ccff_tail[0] O *L 0 *C 287.190 748.000 +*I grid_io_left_0__2_:ccff_head[0] I *L 0 *C 274.010 748.000 + +*CAP +0 cby_0__2_:ccff_tail[0] 0.0007988479 +1 grid_io_left_0__2_:ccff_head[0] 0.0007988479 + +*RES +0 cby_0__2_:ccff_tail[0] grid_io_left_0__2_:ccff_head[0] 0.002064867 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[3] 0.001269324 //LENGTH 11.020 LUMPCC 0.0005516617 DR + +*CONN +*I cby_0__2_:chany_bottom_out[3] O *L 0 *C 332.580 669.190 +*I sb_0__1_:chany_top_in[3] I *L 0 *C 332.580 658.170 +*N cby_0__1__1_chany_bottom_out[3]:2 *C 332.580 667.519 +*N cby_0__1__1_chany_bottom_out[3]:3 *C 332.580 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[3] 0.0001115404 +1 sb_0__1_:chany_top_in[3] 0.0002472905 +2 cby_0__1__1_chany_bottom_out[3]:2 0.0002472905 +3 cby_0__1__1_chany_bottom_out[3]:3 0.0001115404 +4 cby_0__2_:chany_bottom_out[3] cby_0__2_:chany_bottom_in[5] 7.193657e-06 +5 sb_0__1_:chany_top_in[3] sb_0__1_:chany_top_out[5] 0.0001307218 +6 cby_0__1__1_chany_bottom_out[3]:3 sb_0__1__0_chany_top_out[5]:2 7.193657e-06 +7 cby_0__1__1_chany_bottom_out[3]:2 sb_0__1__0_chany_top_out[5]:3 0.0001307218 +8 cby_0__2_:chany_bottom_out[3] cby_0__2_:chany_bottom_in[10] 7.193657e-06 +9 sb_0__1_:chany_top_in[3] sb_0__1_:chany_top_out[10] 0.0001307218 +10 cby_0__1__1_chany_bottom_out[3]:3 sb_0__1__0_chany_top_out[10]:2 7.193657e-06 +11 cby_0__1__1_chany_bottom_out[3]:2 sb_0__1__0_chany_top_out[10]:3 0.0001307218 + +*RES +0 cby_0__2_:chany_bottom_out[3] cby_0__1__1_chany_bottom_out[3]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[3]:3 cby_0__1__1_chany_bottom_out[3]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[3]:2 sb_0__1_:chany_top_in[3] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[9] 0.001253999 //LENGTH 11.020 LUMPCC 0.0005649955 DR + +*CONN +*I cby_0__2_:chany_bottom_out[9] O *L 0 *C 339.020 669.190 +*I sb_0__1_:chany_top_in[9] I *L 0 *C 339.020 658.170 +*N cby_0__1__1_chany_bottom_out[9]:2 *C 339.020 667.519 +*N cby_0__1__1_chany_bottom_out[9]:3 *C 339.020 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[9] 0.0001113409 +1 sb_0__1_:chany_top_in[9] 0.000233161 +2 cby_0__1__1_chany_bottom_out[9]:2 0.000233161 +3 cby_0__1__1_chany_bottom_out[9]:3 0.0001113409 +4 cby_0__2_:chany_bottom_out[9] cby_0__2_:chany_bottom_in[11] 7.248536e-06 +5 sb_0__1_:chany_top_in[9] sb_0__1_:chany_top_out[11] 0.0001340003 +6 cby_0__1__1_chany_bottom_out[9]:3 sb_0__1__0_chany_top_out[11]:2 7.248536e-06 +7 cby_0__1__1_chany_bottom_out[9]:2 sb_0__1__0_chany_top_out[11]:3 0.0001340003 +8 cby_0__2_:chany_bottom_out[9] cby_0__2_:chany_bottom_in[17] 7.248536e-06 +9 sb_0__1_:chany_top_in[9] sb_0__1_:chany_top_out[17] 0.0001340003 +10 cby_0__1__1_chany_bottom_out[9]:3 sb_0__1__0_chany_top_out[17]:2 7.248536e-06 +11 cby_0__1__1_chany_bottom_out[9]:2 sb_0__1__0_chany_top_out[17]:3 0.0001340003 + +*RES +0 cby_0__2_:chany_bottom_out[9] cby_0__1__1_chany_bottom_out[9]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[9]:3 cby_0__1__1_chany_bottom_out[9]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[9]:2 sb_0__1_:chany_top_in[9] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[17] 0.001524261 //LENGTH 11.180 LUMPCC 0.0001345416 DR + +*CONN +*I cby_0__2_:chany_bottom_out[17] O *L 0 *C 301.760 669.270 +*I sb_0__1_:chany_top_in[17] I *L 0 *C 301.760 658.090 +*N cby_0__1__1_chany_bottom_out[17]:2 *C 301.760 667.519 +*N cby_0__1__1_chany_bottom_out[17]:3 *C 301.760 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[17] 0.0002251 +1 sb_0__1_:chany_top_in[17] 0.0004697596 +2 cby_0__1__1_chany_bottom_out[17]:2 0.0004697596 +3 cby_0__1__1_chany_bottom_out[17]:3 0.0002251 +4 sb_0__1_:chany_top_in[17] sb_0__1_:chany_top_in[13] 6.727079e-05 +5 cby_0__1__1_chany_bottom_out[17]:2 cby_0__1__1_chany_bottom_out[13]:2 6.727079e-05 + +*RES +0 cby_0__2_:chany_bottom_out[17] cby_0__1__1_chany_bottom_out[17]:3 0.0002741666 +1 cby_0__1__1_chany_bottom_out[17]:3 cby_0__1__1_chany_bottom_out[17]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[17]:2 sb_0__1_:chany_top_in[17] 0.00147721 + +*END + +*D_NET cby_0__1__1_chany_top_out[4] 0.001165017 //LENGTH 11.020 LUMPCC 0.0002880744 DR + +*CONN +*I cby_0__2_:chany_top_out[4] O *L 0 *C 360.180 777.850 +*I sb_0__2_:chany_bottom_in[4] I *L 0 *C 360.180 788.870 + +*CAP +0 cby_0__2_:chany_top_out[4] 0.0004384712 +1 sb_0__2_:chany_bottom_in[4] 0.0004384712 +2 cby_0__2_:chany_top_out[4] cby_0__2_:chany_top_out[13] 0.0001440372 +3 sb_0__2_:chany_bottom_in[4] sb_0__2_:chany_bottom_in[13] 0.0001440372 + +*RES +0 cby_0__2_:chany_top_out[4] sb_0__2_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[12] 0.001091574 //LENGTH 11.020 LUMPCC 0.0001308059 DR + +*CONN +*I cby_0__2_:chany_top_out[12] O *L 0 *C 350.980 777.850 +*I sb_0__2_:chany_bottom_in[12] I *L 0 *C 350.980 788.870 + +*CAP +0 cby_0__2_:chany_top_out[12] 0.0004803841 +1 sb_0__2_:chany_bottom_in[12] 0.0004803841 +2 cby_0__2_:chany_top_out[12] cby_0__2_:chany_top_out[0] 6.540296e-05 +3 sb_0__2_:chany_bottom_in[12] sb_0__2_:chany_bottom_in[0] 6.540296e-05 + +*RES +0 cby_0__2_:chany_top_out[12] sb_0__2_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[19] 0.001256822 //LENGTH 11.020 LUMPCC 0.0005621223 DR + +*CONN +*I cby_0__2_:chany_top_out[19] O *L 0 *C 311.880 777.850 +*I sb_0__2_:chany_bottom_in[19] I *L 0 *C 311.880 788.870 + +*CAP +0 cby_0__2_:chany_top_out[19] 0.0003473497 +1 sb_0__2_:chany_bottom_in[19] 0.0003473497 +2 cby_0__2_:chany_top_out[19] cby_0__2_:chany_top_out[8] 0.0001405306 +3 sb_0__2_:chany_bottom_in[19] sb_0__2_:chany_bottom_in[8] 0.0001405306 +4 cby_0__2_:chany_top_out[19] cby_0__2_:chany_top_in[9] 0.0001405306 +5 sb_0__2_:chany_bottom_in[19] sb_0__2_:chany_bottom_out[9] 0.0001405306 + +*RES +0 cby_0__2_:chany_top_out[19] sb_0__2_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[7] 0.001153223 //LENGTH 11.020 LUMPCC 0.0003944698 DR + +*CONN +*I cby_1__1_:chany_bottom_out[7] O *L 0 *C 586.500 408.070 +*I sb_1__0_:chany_top_in[7] I *L 0 *C 586.500 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[7] 0.0003793763 +1 sb_1__0_:chany_top_in[7] 0.0003793763 +2 cby_1__1_:chany_bottom_out[7] cby_1__1_:chany_bottom_out[9] 0.0001480614 +3 sb_1__0_:chany_top_in[7] sb_1__0_:chany_top_in[9] 0.0001480614 +4 cby_1__1_:chany_bottom_out[7] cby_1__1_:chany_bottom_in[13] 4.917351e-05 +5 sb_1__0_:chany_top_in[7] sb_1__0_:chany_top_out[13] 4.917351e-05 + +*RES +0 cby_1__1_:chany_bottom_out[7] sb_1__0_:chany_top_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[18] 0.001161604 //LENGTH 11.020 LUMPCC 0.0003884691 DR + +*CONN +*I cby_1__1_:chany_bottom_out[18] O *L 0 *C 604.440 408.070 +*I sb_1__0_:chany_top_in[18] I *L 0 *C 604.440 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[18] 0.0003865675 +1 sb_1__0_:chany_top_in[18] 0.0003865675 +2 cby_1__1_:chany_bottom_out[18] cby_1__1_:chany_bottom_in[5] 0.0001460119 +3 sb_1__0_:chany_top_in[18] sb_1__0_:chany_top_out[5] 0.0001460119 +4 cby_1__1_:chany_bottom_out[18] cby_1__1_:chany_bottom_in[16] 4.82226e-05 +5 sb_1__0_:chany_top_in[18] sb_1__0_:chany_top_out[16] 4.82226e-05 + +*RES +0 cby_1__1_:chany_bottom_out[18] sb_1__0_:chany_top_in[18] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[9] 0.001235129 //LENGTH 11.020 LUMPCC 0.0003170782 DR + +*CONN +*I cby_1__1_:chany_top_out[9] O *L 0 *C 603.980 516.730 +*I sb_1__1_:chany_bottom_in[9] I *L 0 *C 603.980 527.750 + +*CAP +0 cby_1__1_:chany_top_out[9] 0.0004590254 +1 sb_1__1_:chany_bottom_in[9] 0.0004590254 +2 cby_1__1_:chany_top_out[9] cby_1__1_:chany_top_out[11] 3.289369e-05 +3 sb_1__1_:chany_bottom_in[9] sb_1__1_:chany_bottom_in[11] 3.289369e-05 +4 cby_1__1_:chany_top_out[9] cby_1__1_:chany_top_in[0] 0.0001256454 +5 sb_1__1_:chany_bottom_in[9] sb_1__1_:chany_bottom_out[0] 0.0001256454 + +*RES +0 cby_1__1_:chany_top_out[9] sb_1__1_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[19] 0.00128147 //LENGTH 11.020 LUMPCC 0.0005156055 DR + +*CONN +*I cby_1__1_:chany_top_out[19] O *L 0 *C 598.460 516.730 +*I sb_1__1_:chany_bottom_in[19] I *L 0 *C 598.460 527.750 + +*CAP +0 cby_1__1_:chany_top_out[19] 0.0003829321 +1 sb_1__1_:chany_bottom_in[19] 0.0003829321 +2 cby_1__1_:chany_top_out[19] cby_1__1_:chany_top_out[8] 0.0001289014 +3 sb_1__1_:chany_bottom_in[19] sb_1__1_:chany_bottom_in[8] 0.0001289014 +4 cby_1__1_:chany_top_out[19] cby_1__1_:chany_top_out[12] 0.0001289014 +5 sb_1__1_:chany_bottom_in[19] sb_1__1_:chany_bottom_in[12] 0.0001289014 + +*RES +0 cby_1__1_:chany_top_out[19] sb_1__1_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_1_[0] 0.001317927 //LENGTH 7.660 LUMPCC 0.0003269167 DR + +*CONN +*I cby_1__1_:left_grid_pin_1_[0] O *L 0 *C 548.470 503.200 +*I grid_clb_1__1_:right_width_0_height_0__pin_1_[0] I *L 0 *C 540.810 503.200 + +*CAP +0 cby_1__1_:left_grid_pin_1_[0] 0.0004955052 +1 grid_clb_1__1_:right_width_0_height_0__pin_1_[0] 0.0004955052 +2 cby_1__1_:left_grid_pin_1_[0] cby_1__1_:left_grid_pin_3_[0] 0.0001393266 +3 grid_clb_1__1_:right_width_0_height_0__pin_1_[0] grid_clb_1__1_:right_width_0_height_0__pin_3_[0] 0.0001393266 +4 cby_1__1_:left_grid_pin_1_[0] cby_1__1_:prog_clk[0] 2.413176e-05 +5 grid_clb_1__1_:right_width_0_height_0__pin_1_[0] ctsbuf_net_1019:11 2.413176e-05 + +*RES +0 cby_1__1_:left_grid_pin_1_[0] grid_clb_1__1_:right_width_0_height_0__pin_1_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_ccff_tail[0] 0.001088117 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_1__2_:ccff_tail[0] O *L 0 *C 632.810 768.400 +*I grid_clb_2__2_:ccff_head[0] I *L 0 *C 640.470 768.400 + +*CAP +0 cby_1__2_:ccff_tail[0] 0.0005440586 +1 grid_clb_2__2_:ccff_head[0] 0.0005440586 + +*RES +0 cby_1__2_:ccff_tail[0] grid_clb_2__2_:ccff_head[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[6] 0.001252005 //LENGTH 11.020 LUMPCC 0.0005715448 DR + +*CONN +*I cby_1__2_:chany_bottom_out[6] O *L 0 *C 594.780 669.190 +*I sb_1__1_:chany_top_in[6] I *L 0 *C 594.780 658.170 +*N cby_1__1__1_chany_bottom_out[6]:2 *C 594.780 667.519 +*N cby_1__1__1_chany_bottom_out[6]:3 *C 594.780 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[6] 0.0001111417 +1 sb_1__1_:chany_top_in[6] 0.0002290884 +2 cby_1__1__1_chany_bottom_out[6]:2 0.0002290884 +3 cby_1__1__1_chany_bottom_out[6]:3 0.0001111417 +4 cby_1__2_:chany_bottom_out[6] cby_1__2_:chany_bottom_out[3] 7.294814e-06 +5 sb_1__1_:chany_top_in[6] sb_1__1_:chany_top_in[3] 0.0001357202 +6 cby_1__1__1_chany_bottom_out[6]:3 cby_1__1__1_chany_bottom_out[3]:3 7.294814e-06 +7 cby_1__1__1_chany_bottom_out[6]:2 cby_1__1__1_chany_bottom_out[3]:2 0.0001357202 +8 cby_1__2_:chany_bottom_out[6] cby_1__2_:chany_bottom_out[11] 7.294814e-06 +9 sb_1__1_:chany_top_in[6] sb_1__1_:chany_top_in[11] 0.0001354626 +10 cby_1__1__1_chany_bottom_out[6]:3 cby_1__1__1_chany_bottom_out[11]:3 7.294814e-06 +11 cby_1__1__1_chany_bottom_out[6]:2 cby_1__1__1_chany_bottom_out[11]:2 0.0001354626 + +*RES +0 cby_1__2_:chany_bottom_out[6] cby_1__1__1_chany_bottom_out[6]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[6]:3 cby_1__1__1_chany_bottom_out[6]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[6]:2 sb_1__1_:chany_top_in[6] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[16] 0.001245865 //LENGTH 11.020 LUMPCC 0.0005875931 DR + +*CONN +*I cby_1__2_:chany_bottom_out[16] O *L 0 *C 589.260 669.190 +*I sb_1__1_:chany_top_in[16] I *L 0 *C 589.260 658.170 +*N cby_1__1__1_chany_bottom_out[16]:2 *C 589.260 667.519 +*N cby_1__1__1_chany_bottom_out[16]:3 *C 589.260 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[16] 0.0001109382 +1 sb_1__1_:chany_top_in[16] 0.0002181978 +2 cby_1__1__1_chany_bottom_out[16]:2 0.0002181978 +3 cby_1__1__1_chany_bottom_out[16]:3 0.0001109382 +4 cby_1__2_:chany_bottom_out[16] cby_1__2_:chany_bottom_in[6] 7.346249e-06 +5 sb_1__1_:chany_top_in[16] sb_1__1_:chany_top_out[6] 0.000139552 +6 cby_1__1__1_chany_bottom_out[16]:3 sb_1__1__0_chany_top_out[6]:2 7.346249e-06 +7 cby_1__1__1_chany_bottom_out[16]:2 sb_1__1__0_chany_top_out[6]:3 0.000139552 +8 cby_1__2_:chany_bottom_out[16] cby_1__2_:chany_bottom_in[8] 7.346249e-06 +9 sb_1__1_:chany_top_in[16] sb_1__1_:chany_top_out[8] 0.000139552 +10 cby_1__1__1_chany_bottom_out[16]:3 sb_1__1__0_chany_top_out[8]:2 7.346249e-06 +11 cby_1__1__1_chany_bottom_out[16]:2 sb_1__1__0_chany_top_out[8]:3 0.000139552 + +*RES +0 cby_1__2_:chany_bottom_out[16] cby_1__1__1_chany_bottom_out[16]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[16]:3 cby_1__1__1_chany_bottom_out[16]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[16]:2 sb_1__1_:chany_top_in[16] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_top_out[7] 0.001272234 //LENGTH 11.020 LUMPCC 0.0005332323 DR + +*CONN +*I cby_1__2_:chany_top_out[7] O *L 0 *C 607.200 777.850 +*I sb_1__2_:chany_bottom_in[7] I *L 0 *C 607.200 788.870 + +*CAP +0 cby_1__2_:chany_top_out[7] 0.0003695007 +1 sb_1__2_:chany_bottom_in[7] 0.0003695007 +2 cby_1__2_:chany_top_out[7] cby_1__2_:chany_top_out[3] 0.0001333081 +3 sb_1__2_:chany_bottom_in[7] sb_1__2_:chany_bottom_in[3] 0.0001333081 +4 cby_1__2_:chany_top_out[7] cby_1__2_:chany_top_out[11] 0.0001333081 +5 sb_1__2_:chany_bottom_in[7] sb_1__2_:chany_bottom_in[11] 0.0001333081 + +*RES +0 cby_1__2_:chany_top_out[7] sb_1__2_:chany_bottom_in[7] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[19] 0.001260934 //LENGTH 11.020 LUMPCC 0.0005428599 DR + +*CONN +*I cby_1__2_:chany_top_out[19] O *L 0 *C 598.460 777.850 +*I sb_1__2_:chany_bottom_in[19] I *L 0 *C 598.460 788.870 + +*CAP +0 cby_1__2_:chany_top_out[19] 0.000359037 +1 sb_1__2_:chany_bottom_in[19] 0.000359037 +2 cby_1__2_:chany_top_out[19] cby_1__2_:chany_top_out[8] 0.000135715 +3 sb_1__2_:chany_bottom_in[19] sb_1__2_:chany_bottom_in[8] 0.000135715 +4 cby_1__2_:chany_top_out[19] cby_1__2_:chany_top_out[12] 0.000135715 +5 sb_1__2_:chany_bottom_in[19] sb_1__2_:chany_bottom_in[12] 0.000135715 + +*RES +0 cby_1__2_:chany_top_out[19] sb_1__2_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_4_[0] 0.001457294 //LENGTH 7.660 LUMPCC 0.0004751765 DR + +*CONN +*I cby_1__2_:left_grid_pin_4_[0] O *L 0 *C 548.470 769.760 +*I grid_clb_1__2_:right_width_0_height_0__pin_4_[0] I *L 0 *C 540.810 769.760 + +*CAP +0 cby_1__2_:left_grid_pin_4_[0] 0.0004910587 +1 grid_clb_1__2_:right_width_0_height_0__pin_4_[0] 0.0004910587 +2 cby_1__2_:left_grid_pin_4_[0] cby_1__2_:left_grid_pin_0_[0] 0.0001264095 +3 grid_clb_1__2_:right_width_0_height_0__pin_4_[0] grid_clb_1__2_:right_width_0_height_0__pin_0_[0] 0.0001264095 +4 cby_1__2_:left_grid_pin_4_[0] cby_1__2_:left_grid_pin_7_[0] 0.0001111788 +5 grid_clb_1__2_:right_width_0_height_0__pin_4_[0] grid_clb_1__2_:right_width_0_height_0__pin_7_[0] 0.0001111788 + +*RES +0 cby_1__2_:left_grid_pin_4_[0] grid_clb_1__2_:right_width_0_height_0__pin_4_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[6] 0.001228792 //LENGTH 11.020 LUMPCC 0.0005927128 DR + +*CONN +*I cby_2__1_:chany_bottom_out[6] O *L 0 *C 856.060 408.070 +*I sb_2__0_:chany_top_in[6] I *L 0 *C 856.060 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[6] 0.0003180396 +1 sb_2__0_:chany_top_in[6] 0.0003180396 +2 cby_2__1_:chany_bottom_out[6] cby_2__1_:chany_bottom_out[3] 0.0001484263 +3 sb_2__0_:chany_top_in[6] sb_2__0_:chany_top_in[3] 0.0001484263 +4 cby_2__1_:chany_bottom_out[6] cby_2__1_:chany_bottom_out[11] 0.0001479301 +5 sb_2__0_:chany_top_in[6] sb_2__0_:chany_top_in[11] 0.0001479301 + +*RES +0 cby_2__1_:chany_bottom_out[6] sb_2__0_:chany_top_in[6] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[17] 0.001237891 //LENGTH 11.020 LUMPCC 0.0005802679 DR + +*CONN +*I cby_2__1_:chany_bottom_out[17] O *L 0 *C 862.500 408.070 +*I sb_2__0_:chany_top_in[17] I *L 0 *C 862.500 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[17] 0.0003288116 +1 sb_2__0_:chany_top_in[17] 0.0003288116 +2 cby_2__1_:chany_bottom_out[17] cby_2__1_:chany_bottom_out[0] 0.0001449382 +3 sb_2__0_:chany_top_in[17] sb_2__0_:chany_top_in[0] 0.0001449382 +4 cby_2__1_:chany_bottom_out[17] cby_2__1_:chany_bottom_out[2] 0.0001451958 +5 sb_2__0_:chany_top_in[17] sb_2__0_:chany_top_in[2] 0.0001451958 + +*RES +0 cby_2__1_:chany_bottom_out[17] sb_2__0_:chany_top_in[17] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_top_out[6] 0.001202747 //LENGTH 11.020 LUMPCC 0.0003229759 DR + +*CONN +*I cby_2__1_:chany_top_out[6] O *L 0 *C 875.380 516.730 +*I sb_2__1_:chany_bottom_in[6] I *L 0 *C 875.380 527.750 + +*CAP +0 cby_2__1_:chany_top_out[6] 0.0004398858 +1 sb_2__1_:chany_bottom_in[6] 0.0004398858 +2 cby_2__1_:chany_top_out[6] cby_2__1_:chany_top_in[4] 2.678904e-05 +3 sb_2__1_:chany_bottom_in[6] sb_2__1_:chany_bottom_out[4] 2.678904e-05 +4 cby_2__1_:chany_top_out[6] cby_2__1_:chany_top_in[10] 0.0001346989 +5 sb_2__1_:chany_bottom_in[6] sb_2__1_:chany_bottom_out[10] 0.0001346989 + +*RES +0 cby_2__1_:chany_top_out[6] sb_2__1_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[19] 0.001274831 //LENGTH 11.020 LUMPCC 0.0005351064 DR + +*CONN +*I cby_2__1_:chany_top_out[19] O *L 0 *C 859.740 516.730 +*I sb_2__1_:chany_bottom_in[19] I *L 0 *C 859.740 527.750 + +*CAP +0 cby_2__1_:chany_top_out[19] 0.0003698624 +1 sb_2__1_:chany_bottom_in[19] 0.0003698624 +2 cby_2__1_:chany_top_out[19] cby_2__1_:chany_top_out[8] 0.0001337766 +3 sb_2__1_:chany_bottom_in[19] sb_2__1_:chany_bottom_in[8] 0.0001337766 +4 cby_2__1_:chany_top_out[19] cby_2__1_:chany_top_out[12] 0.0001337766 +5 sb_2__1_:chany_bottom_in[19] sb_2__1_:chany_bottom_in[12] 0.0001337766 + +*RES +0 cby_2__1_:chany_top_out[19] sb_2__1_:chany_bottom_in[19] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_4_[0] 0.001205351 //LENGTH 7.660 LUMPCC 0.000727553 DR + +*CONN +*I cby_2__1_:left_grid_pin_4_[0] O *L 0 *C 809.750 508.640 +*I grid_clb_2__1_:right_width_0_height_0__pin_4_[0] I *L 0 *C 802.090 508.640 + +*CAP +0 cby_2__1_:left_grid_pin_4_[0] 0.000238899 +1 grid_clb_2__1_:right_width_0_height_0__pin_4_[0] 0.000238899 +2 cby_2__1_:left_grid_pin_4_[0] cby_2__1_:left_grid_pin_0_[0] 0.0001818883 +3 grid_clb_2__1_:right_width_0_height_0__pin_4_[0] grid_clb_2__1_:right_width_0_height_0__pin_0_[0] 0.0001818883 +4 cby_2__1_:left_grid_pin_4_[0] cby_2__1_:left_grid_pin_7_[0] 0.0001818883 +5 grid_clb_2__1_:right_width_0_height_0__pin_4_[0] grid_clb_2__1_:right_width_0_height_0__pin_7_[0] 0.0001818883 + +*RES +0 cby_2__1_:left_grid_pin_4_[0] grid_clb_2__1_:right_width_0_height_0__pin_4_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[6] 0.001255383 //LENGTH 11.020 LUMPCC 0.0005549706 DR + +*CONN +*I cby_2__2_:chany_bottom_out[6] O *L 0 *C 856.060 669.190 +*I sb_2__1_:chany_top_in[6] I *L 0 *C 856.060 658.170 +*N cby_1__1__3_chany_bottom_out[6]:2 *C 856.060 667.519 +*N cby_1__1__3_chany_bottom_out[6]:3 *C 856.060 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[6] 0.0001109314 +1 sb_2__1_:chany_top_in[6] 0.0002392745 +2 cby_1__1__3_chany_bottom_out[6]:2 0.0002392745 +3 cby_1__1__3_chany_bottom_out[6]:3 0.0001109314 +4 cby_2__2_:chany_bottom_out[6] cby_2__2_:chany_bottom_out[3] 7.346249e-06 +5 sb_2__1_:chany_top_in[6] sb_2__1_:chany_top_in[3] 0.0001318429 +6 cby_1__1__3_chany_bottom_out[6]:3 cby_1__1__3_chany_bottom_out[3]:3 7.346249e-06 +7 cby_1__1__3_chany_bottom_out[6]:2 cby_1__1__3_chany_bottom_out[3]:2 0.0001318429 +8 cby_2__2_:chany_bottom_out[6] cby_2__2_:chany_bottom_out[11] 7.340376e-06 +9 sb_2__1_:chany_top_in[6] sb_2__1_:chany_top_in[11] 0.0001309558 +10 cby_1__1__3_chany_bottom_out[6]:3 cby_1__1__3_chany_bottom_out[11]:3 7.340376e-06 +11 cby_1__1__3_chany_bottom_out[6]:2 cby_1__1__3_chany_bottom_out[11]:2 0.0001309558 + +*RES +0 cby_2__2_:chany_bottom_out[6] cby_1__1__3_chany_bottom_out[6]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[6]:3 cby_1__1__3_chany_bottom_out[6]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[6]:2 sb_2__1_:chany_top_in[6] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_top_out[0] 0.001259614 //LENGTH 11.020 LUMPCC 0.0005582116 DR + +*CONN +*I cby_2__2_:chany_top_out[0] O *L 0 *C 863.420 777.850 +*I sb_2__2_:chany_bottom_in[0] I *L 0 *C 863.420 788.870 + +*CAP +0 cby_2__2_:chany_top_out[0] 0.0003507012 +1 sb_2__2_:chany_bottom_in[0] 0.0003507012 +2 cby_2__2_:chany_top_out[0] cby_2__2_:chany_top_out[2] 0.0001395529 +3 sb_2__2_:chany_bottom_in[0] sb_2__2_:chany_bottom_in[2] 0.0001395529 +4 cby_2__2_:chany_top_out[0] cby_2__2_:chany_top_in[0] 0.0001395529 +5 sb_2__2_:chany_bottom_in[0] sb_2__2_:chany_bottom_out[0] 0.0001395529 + +*RES +0 cby_2__2_:chany_top_out[0] sb_2__2_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[14] 0.00126029 //LENGTH 11.020 LUMPCC 0.0005723188 DR + +*CONN +*I cby_2__2_:chany_top_out[14] O *L 0 *C 847.320 777.850 +*I sb_2__2_:chany_bottom_in[14] I *L 0 *C 847.320 788.870 + +*CAP +0 cby_2__2_:chany_top_out[14] 0.0003439858 +1 sb_2__2_:chany_bottom_in[14] 0.0003439858 +2 cby_2__2_:chany_top_out[14] cby_2__2_:chany_top_out[1] 0.0001392436 +3 sb_2__2_:chany_bottom_in[14] sb_2__2_:chany_bottom_in[1] 0.0001392436 +4 cby_2__2_:chany_top_out[14] cby_2__2_:chany_top_out[4] 0.0001469158 +5 sb_2__2_:chany_bottom_in[14] sb_2__2_:chany_bottom_in[4] 0.0001469158 + +*RES +0 cby_2__2_:chany_top_out[14] sb_2__2_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_1_[0] 0.001111967 //LENGTH 7.660 LUMPCC 0.0003482703 DR + +*CONN +*I cby_2__2_:left_grid_pin_1_[0] O *L 0 *C 809.750 764.320 +*I grid_clb_2__2_:right_width_0_height_0__pin_1_[0] I *L 0 *C 802.090 764.320 + +*CAP +0 cby_2__2_:left_grid_pin_1_[0] 0.0003818482 +1 grid_clb_2__2_:right_width_0_height_0__pin_1_[0] 0.0003818482 +2 cby_2__2_:left_grid_pin_1_[0] cby_2__2_:left_grid_pin_3_[0] 0.0001741351 +3 grid_clb_2__2_:right_width_0_height_0__pin_1_[0] grid_clb_2__2_:right_width_0_height_0__pin_3_[0] 0.0001741351 + +*RES +0 cby_2__2_:left_grid_pin_1_[0] grid_clb_2__2_:right_width_0_height_0__pin_1_[0] 0.001200067 + +*END + +*D_NET direct_interc_1_out[0] 0.009802223 //LENGTH 99.220 LUMPCC 0.001153167 DR + +*CONN +*I direct_interc_1_\/FTB_2__1:X O *L 0 *C 778.095 640.220 +*I grid_clb_2__1_:top_width_0_height_0__pin_32_[0] I *L 0 *C 776.480 543.930 +*N direct_interc_1_out[0]:2 *C 776.480 593.930 +*N direct_interc_1_out[0]:3 *C 776.480 637.455 +*N direct_interc_1_out[0]:4 *C 776.525 637.500 +*N direct_interc_1_out[0]:5 *C 778.275 637.500 +*N direct_interc_1_out[0]:6 *C 778.320 637.545 +*N direct_interc_1_out[0]:7 *C 778.320 640.175 +*N direct_interc_1_out[0]:8 *C 778.320 640.220 +*N direct_interc_1_out[0]:9 *C 778.095 640.220 + +*CAP +0 direct_interc_1_\/FTB_2__1:X 1e-06 +1 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 0.002081308 +2 direct_interc_1_out[0]:2 0.004030382 +3 direct_interc_1_out[0]:3 0.001949074 +4 direct_interc_1_out[0]:4 0.0001159238 +5 direct_interc_1_out[0]:5 0.0001159238 +6 direct_interc_1_out[0]:6 0.0001258056 +7 direct_interc_1_out[0]:7 0.0001258056 +8 direct_interc_1_out[0]:8 5.184763e-05 +9 direct_interc_1_out[0]:9 5.198474e-05 +10 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] clk[0]:47 5.193616e-05 +11 direct_interc_1_out[0]:7 clk[0]:49 3.526572e-05 +12 direct_interc_1_out[0]:6 clk[0]:48 3.526572e-05 +13 direct_interc_1_out[0]:3 clk[0]:48 2.093162e-05 +14 direct_interc_1_out[0]:3 clk[0]:49 8.818282e-05 +15 direct_interc_1_out[0]:2 clk[0]:47 2.093162e-05 +16 direct_interc_1_out[0]:2 clk[0]:48 0.000140119 +17 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] cbx_1__1__1_chanx_right_out[2]:4 0.0002577573 +18 direct_interc_1_out[0]:2 cbx_1__1__1_chanx_right_out[2]:3 0.0002577573 +19 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] cbx_1__1__1_chanx_right_out[11]:4 4.305203e-05 +20 direct_interc_1_out[0]:2 cbx_1__1__1_chanx_right_out[11]:5 4.305203e-05 +21 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] cbx_1__1__1_chanx_right_out[19]:4 7.945814e-05 +22 direct_interc_1_out[0]:2 cbx_1__1__1_chanx_right_out[19]:3 7.945814e-05 + +*RES +0 direct_interc_1_\/FTB_2__1:X direct_interc_1_out[0]:9 0.152 +1 direct_interc_1_out[0]:9 direct_interc_1_out[0]:8 0.0001222826 +2 direct_interc_1_out[0]:8 direct_interc_1_out[0]:7 0.0045 +3 direct_interc_1_out[0]:7 direct_interc_1_out[0]:6 0.002348214 +4 direct_interc_1_out[0]:5 direct_interc_1_out[0]:4 0.0015625 +5 direct_interc_1_out[0]:6 direct_interc_1_out[0]:5 0.0045 +6 direct_interc_1_out[0]:4 direct_interc_1_out[0]:3 0.0045 +7 direct_interc_1_out[0]:3 direct_interc_1_out[0]:2 0.03886161 +8 direct_interc_1_out[0]:2 grid_clb_2__1_:top_width_0_height_0__pin_32_[0] 0.04464286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_48_lower[0] 0.001179468 //LENGTH 11.020 LUMPCC 0.0002775246 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_48_lower[0] O *L 0 *C 531.300 380.870 +*I sb_1__0_:left_top_grid_pin_48_[0] I *L 0 *C 531.300 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_48_lower[0] 0.0004509714 +1 sb_1__0_:left_top_grid_pin_48_[0] 0.0004509714 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_48_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_49_lower[0] 0.0001387623 +3 sb_1__0_:left_top_grid_pin_48_[0] sb_1__0_:left_top_grid_pin_49_[0] 0.0001387623 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_48_lower[0] sb_1__0_:left_top_grid_pin_48_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_37_lower[0] 0.002655345 //LENGTH 23.200 LUMPCC 0.0003720981 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_37_lower[0] O *L 0 *C 540.810 408.000 +*I sb_1__0_:top_left_grid_pin_37_[0] I *L 0 *C 552.000 397.050 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 *C 552.000 399.783 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 *C 551.993 399.840 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 *C 544.660 399.840 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:5 *C 544.640 399.848 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:6 *C 544.640 407.993 +*N grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 *C 544.620 408.000 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_37_lower[0] 0.0002574926 +1 sb_1__0_:top_left_grid_pin_37_[0] 0.000152783 +2 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 0.000152783 +3 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 0.0003072926 +4 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 0.0003072926 +5 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:5 0.0004240552 +6 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:6 0.0004240552 +7 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 0.0002574926 +8 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 direct_interc_2_out[0]:33 9.244033e-05 +9 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 direct_interc_2_out[0]:34 9.244033e-05 +10 grid_clb_1__1_:right_width_0_height_0__pin_37_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] 6.476565e-05 +11 sb_1__0_:top_left_grid_pin_37_[0] sb_1__0_:top_left_grid_pin_34_[0] 2.884306e-05 +12 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 2.884306e-05 +13 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 6.476565e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_37_lower[0] grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 0.0005968999 +1 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 sb_1__0_:top_left_grid_pin_37_[0] 0.002439732 +2 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 0.00341 +3 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 0.001148758 +4 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:5 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 0.00341 +5 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:6 0.00341 +6 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:6 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:5 0.00127605 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_43_upper[0] 0.001208466 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_43_upper[0] O *L 0 *C 379.190 654.160 +*I sb_0__1_:right_top_grid_pin_43_[0] I *L 0 *C 371.530 654.160 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_43_upper[0] 0.0006042329 +1 sb_0__1_:right_top_grid_pin_43_[0] 0.0006042329 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_43_upper[0] sb_0__1_:right_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_47_lower[0] 0.001252608 //LENGTH 11.020 LUMPCC 0.0005593378 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] O *L 0 *C 523.020 641.990 +*I sb_1__1_:left_top_grid_pin_47_[0] I *L 0 *C 523.020 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0003466352 +1 sb_1__1_:left_top_grid_pin_47_[0] 0.0003466352 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0001398345 +3 sb_1__1_:left_top_grid_pin_47_[0] sb_1__1_:left_top_grid_pin_44_[0] 0.0001398345 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_46_lower[0] 0.0001398345 +5 sb_1__1_:left_top_grid_pin_47_[0] sb_1__1_:left_top_grid_pin_46_[0] 0.0001398345 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_47_lower[0] sb_1__1_:left_top_grid_pin_47_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_38_upper[0] 0.001445786 //LENGTH 7.660 LUMPCC 0.0003365231 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] O *L 0 *C 540.810 793.560 +*I sb_1__2_:bottom_left_grid_pin_38_[0] I *L 0 *C 548.470 793.560 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] 0.0005546315 +1 sb_1__2_:bottom_left_grid_pin_38_[0] 0.0005546315 +2 grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] 5.906435e-05 +3 sb_1__2_:bottom_left_grid_pin_38_[0] sb_1__2_:bottom_left_grid_pin_36_[0] 5.906435e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_37_upper[0] 0.0001091972 +5 sb_1__2_:bottom_left_grid_pin_38_[0] sb_1__2_:bottom_left_grid_pin_37_[0] 0.0001091972 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] sb_1__2_:bottom_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_43_lower[0] 0.001085523 //LENGTH 7.660 LUMPCC 0.0005024645 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] O *L 0 *C 802.090 385.560 +*I sb_2__0_:left_top_grid_pin_43_[0] I *L 0 *C 809.750 385.560 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] 0.0002915291 +1 sb_2__0_:left_top_grid_pin_43_[0] 0.0002915291 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_2_right_width_0_height_0__pin_36_lower[0]:2 1.669889e-05 +3 sb_2__0_:left_top_grid_pin_43_[0] sb_2__0_:top_left_grid_pin_36_[0] 1.669889e-05 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] 4.933096e-05 +5 sb_2__0_:left_top_grid_pin_43_[0] sb_2__0_:top_left_grid_pin_40_[0] 4.933096e-05 +6 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_41_lower[0] 0.0001852024 +7 sb_2__0_:left_top_grid_pin_43_[0] sb_2__0_:top_left_grid_pin_41_[0] 0.0001852024 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] sb_2__0_:left_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_34_upper[0] 0.001140767 //LENGTH 7.660 LUMPCC 0.0005816606 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] O *L 0 *C 802.090 537.880 +*I sb_2__1_:bottom_left_grid_pin_34_[0] I *L 0 *C 809.750 537.880 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] 0.0002795534 +1 sb_2__1_:bottom_left_grid_pin_34_[0] 0.0002795534 +2 grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] 0.0001141139 +3 sb_2__1_:bottom_left_grid_pin_34_[0] sb_2__1_:bottom_left_grid_pin_35_[0] 0.0001141139 +4 grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_39_upper[0] 0.0001767164 +5 sb_2__1_:bottom_left_grid_pin_34_[0] sb_2__1_:bottom_left_grid_pin_39_[0] 0.0001767164 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] sb_2__1_:bottom_left_grid_pin_34_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_42_lower[0] 0.001116998 //LENGTH 11.020 LUMPCC 0.0001262651 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] O *L 0 *C 788.440 641.990 +*I sb_2__1_:left_top_grid_pin_42_[0] I *L 0 *C 788.440 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] 0.0004953662 +1 sb_2__1_:left_top_grid_pin_42_[0] 0.0004953662 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] 3.994296e-05 +3 sb_2__1_:left_top_grid_pin_42_[0] sb_2__1_:left_top_grid_pin_45_[0] 3.994296e-05 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] 2.31896e-05 +5 sb_2__1_:left_top_grid_pin_42_[0] sb_2__1_:left_top_grid_pin_49_[0] 2.31896e-05 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] sb_2__1_:left_top_grid_pin_42_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_48_upper[0] 0.001179322 //LENGTH 11.020 LUMPCC 0.0002788777 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_48_upper[0] O *L 0 *C 655.500 641.990 +*I sb_1__1_:right_top_grid_pin_48_[0] I *L 0 *C 655.500 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_48_upper[0] 0.0004502221 +1 sb_1__1_:right_top_grid_pin_48_[0] 0.0004502221 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_48_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0001394388 +3 sb_1__1_:right_top_grid_pin_48_[0] sb_1__1_:right_top_grid_pin_49_[0] 0.0001394388 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_48_upper[0] sb_1__1_:right_top_grid_pin_48_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_38_lower[0] 0.001142975 //LENGTH 7.660 LUMPCC 0.0005997707 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] O *L 0 *C 802.090 652.800 +*I sb_2__1_:top_left_grid_pin_38_[0] I *L 0 *C 809.750 652.800 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] 0.000271602 +1 sb_2__1_:top_left_grid_pin_38_[0] 0.000271602 +2 grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_36_lower[0] 0.0001163217 +3 sb_2__1_:top_left_grid_pin_38_[0] sb_2__1_:top_left_grid_pin_36_[0] 0.0001163217 +4 grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] 0.0001835637 +5 sb_2__1_:top_left_grid_pin_38_[0] sb_2__1_:top_left_grid_pin_39_[0] 0.0001835637 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_38_lower[0] sb_2__1_:top_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_io_bottom_1_ccff_tail[0] 0.005158502 //LENGTH 47.080 LUMPCC 9.796538e-05 DR + +*CONN +*I grid_io_bottom_2__0_:ccff_tail[0] O *L 0 *C 693.680 282.810 +*I sb_1__0_:ccff_head[0] I *L 0 *C 658.260 293.830 +*N grid_io_bottom_1_ccff_tail[0]:2 *C 658.260 290.405 +*N grid_io_bottom_1_ccff_tail[0]:3 *C 658.305 290.360 +*N grid_io_bottom_1_ccff_tail[0]:4 *C 667.519 290.360 +*N grid_io_bottom_1_ccff_tail[0]:5 *C 667.520 290.360 +*N grid_io_bottom_1_ccff_tail[0]:6 *C 693.635 290.360 +*N grid_io_bottom_1_ccff_tail[0]:7 *C 693.680 290.315 + +*CAP +0 grid_io_bottom_2__0_:ccff_tail[0] 0.0003654574 +1 sb_1__0_:ccff_head[0] 0.0001831584 +2 grid_io_bottom_1_ccff_tail[0]:2 0.0001831584 +3 grid_io_bottom_1_ccff_tail[0]:3 0.0005142578 +4 grid_io_bottom_1_ccff_tail[0]:4 0.0005142578 +5 grid_io_bottom_1_ccff_tail[0]:5 0.001467395 +6 grid_io_bottom_1_ccff_tail[0]:6 0.001467395 +7 grid_io_bottom_1_ccff_tail[0]:7 0.0003654574 +8 sb_1__0_:ccff_head[0] sb_1__0_:right_bottom_grid_pin_1_[0] 3.531082e-05 +9 grid_io_bottom_1_ccff_tail[0]:3 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 1.367187e-05 +10 grid_io_bottom_1_ccff_tail[0]:2 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:2 3.531082e-05 +11 grid_io_bottom_1_ccff_tail[0]:4 grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]:3 1.367187e-05 + +*RES +0 grid_io_bottom_2__0_:ccff_tail[0] grid_io_bottom_1_ccff_tail[0]:7 0.006700893 +1 grid_io_bottom_1_ccff_tail[0]:3 grid_io_bottom_1_ccff_tail[0]:2 0.0045 +2 grid_io_bottom_1_ccff_tail[0]:2 sb_1__0_:ccff_head[0] 0.003058036 +3 grid_io_bottom_1_ccff_tail[0]:6 grid_io_bottom_1_ccff_tail[0]:5 0.02331697 +4 grid_io_bottom_1_ccff_tail[0]:7 grid_io_bottom_1_ccff_tail[0]:6 0.0045 +5 grid_io_bottom_1_ccff_tail[0]:5 grid_io_bottom_1_ccff_tail[0]:4 1e-05 +6 grid_io_bottom_1_ccff_tail[0]:4 grid_io_bottom_1_ccff_tail[0]:3 0.008226786 + +*END + +*D_NET grid_io_right_1_left_width_0_height_0__pin_1_upper[0] 0.003045912 //LENGTH 30.980 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__2_:left_width_0_height_0__pin_1_upper[0] O *L 0 *C 911.260 777.850 +*I sb_2__2_:bottom_right_grid_pin_1_[0] I *L 0 *C 891.940 788.870 +*N grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:2 *C 891.940 781.705 +*N grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:3 *C 891.985 781.660 +*N grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:4 *C 911.215 781.660 +*N grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:5 *C 911.260 781.615 + +*CAP +0 grid_io_right_3__2_:left_width_0_height_0__pin_1_upper[0] 0.0002353443 +1 sb_2__2_:bottom_right_grid_pin_1_[0] 0.0003280832 +2 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:2 0.0003280832 +3 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:3 0.0009595285 +4 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:4 0.0009595285 +5 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:5 0.0002353443 + +*RES +0 grid_io_right_3__2_:left_width_0_height_0__pin_1_upper[0] grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:5 0.003361607 +1 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:3 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:2 0.0045 +2 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:2 sb_2__2_:bottom_right_grid_pin_1_[0] 0.006397322 +3 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:4 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:3 0.01716965 +4 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:5 grid_io_right_1_left_width_0_height_0__pin_1_upper[0]:4 0.0045 + +*END + +*D_NET sb_0__0__0_chanx_right_out[4] 0.001254712 //LENGTH 7.660 LUMPCC 0.0007057493 DR + +*CONN +*I sb_0__0_:chanx_right_out[4] O *L 0 *C 400.050 329.120 +*I cbx_1__0_:chanx_left_in[4] I *L 0 *C 407.710 329.120 + +*CAP +0 sb_0__0_:chanx_right_out[4] 0.0002744815 +1 cbx_1__0_:chanx_left_in[4] 0.0002744815 +2 sb_0__0_:chanx_right_out[4] sb_0__0_:chanx_right_out[8] 0.0001764373 +3 cbx_1__0_:chanx_left_in[4] cbx_1__0_:chanx_left_in[8] 0.0001764373 +4 sb_0__0_:chanx_right_out[4] sb_0__0_:chanx_right_out[16] 0.0001764373 +5 cbx_1__0_:chanx_left_in[4] cbx_1__0_:chanx_left_in[16] 0.0001764373 + +*RES +0 sb_0__0_:chanx_right_out[4] cbx_1__0_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[18] 0.001161376 //LENGTH 7.660 LUMPCC 0.0005020991 DR + +*CONN +*I sb_0__0_:chanx_right_out[18] O *L 0 *C 400.050 314.160 +*I cbx_1__0_:chanx_left_in[18] I *L 0 *C 407.710 314.160 + +*CAP +0 sb_0__0_:chanx_right_out[18] 0.0003296387 +1 cbx_1__0_:chanx_left_in[18] 0.0003296387 +2 sb_0__0_:chanx_right_out[18] sb_0__0_:chanx_right_in[12] 0.0001743706 +3 cbx_1__0_:chanx_left_in[18] cbx_1__0_:chanx_left_out[12] 0.0001743706 +4 sb_0__0_:chanx_right_out[18] sb_0__0_:chanx_right_out[14] 7.667893e-05 +5 cbx_1__0_:chanx_left_in[18] cbx_1__0_:chanx_left_in[14] 7.667893e-05 + +*RES +0 sb_0__0_:chanx_right_out[18] cbx_1__0_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[12] 0.001081593 //LENGTH 11.020 LUMPCC 9.195074e-05 DR + +*CONN +*I sb_0__0_:chany_top_out[12] O *L 0 *C 294.400 397.050 +*I cby_0__1_:chany_bottom_in[12] I *L 0 *C 294.400 408.070 + +*CAP +0 sb_0__0_:chany_top_out[12] 0.0004948213 +1 cby_0__1_:chany_bottom_in[12] 0.0004948213 +2 sb_0__0_:chany_top_out[12] sb_0__0_:chany_top_out[14] 4.597537e-05 +3 cby_0__1_:chany_bottom_in[12] cby_0__1_:chany_bottom_in[14] 4.597537e-05 + +*RES +0 sb_0__0_:chany_top_out[12] cby_0__1_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET sb_0__1__0_chanx_right_out[2] 0.001259704 //LENGTH 7.660 LUMPCC 0.0006918779 DR + +*CONN +*I sb_0__1_:chanx_right_out[2] O *L 0 *C 400.050 590.240 +*I cbx_1__1_:chanx_left_in[2] I *L 0 *C 407.710 590.240 + +*CAP +0 sb_0__1_:chanx_right_out[2] 0.000283913 +1 cbx_1__1_:chanx_left_in[2] 0.000283913 +2 sb_0__1_:chanx_right_out[2] sb_0__1_:chanx_right_out[9] 0.0001729695 +3 cbx_1__1_:chanx_left_in[2] cbx_1__1_:chanx_left_in[9] 0.0001729695 +4 sb_0__1_:chanx_right_out[2] sb_0__1_:chanx_right_out[10] 0.0001729695 +5 cbx_1__1_:chanx_left_in[2] cbx_1__1_:chanx_left_in[10] 0.0001729695 + +*RES +0 sb_0__1_:chanx_right_out[2] cbx_1__1_:chanx_left_in[2] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[18] 0.001169144 //LENGTH 7.660 LUMPCC 0.0004386725 DR + +*CONN +*I sb_0__1_:chanx_right_out[18] O *L 0 *C 400.050 580.040 +*I cbx_1__1_:chanx_left_in[18] I *L 0 *C 407.710 580.040 + +*CAP +0 sb_0__1_:chanx_right_out[18] 0.0003652357 +1 cbx_1__1_:chanx_left_in[18] 0.0003652357 +2 sb_0__1_:chanx_right_out[18] sb_0__1_:chanx_right_in[2] 4.740231e-05 +3 cbx_1__1_:chanx_left_in[18] cbx_1__1_:chanx_left_out[2] 4.740231e-05 +4 sb_0__1_:chanx_right_out[18] sb_0__1_:chanx_right_in[9] 0.000171934 +5 cbx_1__1_:chanx_left_in[18] cbx_1__1_:chanx_left_out[9] 0.000171934 + +*RES +0 sb_0__1_:chanx_right_out[18] cbx_1__1_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[13] 0.001422769 //LENGTH 11.180 LUMPCC 0.0002093461 DR + +*CONN +*I sb_0__1_:chany_bottom_out[13] O *L 0 *C 336.720 527.830 +*I cby_0__1_:chany_top_in[13] I *L 0 *C 336.720 516.650 + +*CAP +0 sb_0__1_:chany_bottom_out[13] 0.0006067115 +1 cby_0__1_:chany_top_in[13] 0.0006067115 +2 sb_0__1_:chany_bottom_out[13] sb_0__1_:chany_bottom_out[15] 0.0001046731 +3 cby_0__1_:chany_top_in[13] cby_0__1_:chany_top_in[15] 0.0001046731 + +*RES +0 sb_0__1_:chany_bottom_out[13] cby_0__1_:chany_top_in[13] 0.001751533 + +*END + +*D_NET sb_0__1__0_chany_top_out[6] 0.001518714 //LENGTH 11.180 LUMPCC 0.0004468703 DR + +*CONN +*I sb_0__1_:chany_top_out[6] O *L 0 *C 292.560 658.090 +*I cby_0__2_:chany_bottom_in[6] I *L 0 *C 292.560 669.270 +*N sb_0__1__0_chany_top_out[6]:2 *C 292.560 667.520 +*N sb_0__1__0_chany_top_out[6]:3 *C 292.560 667.519 + +*CAP +0 sb_0__1_:chany_top_out[6] 0.0003127863 +1 cby_0__2_:chany_bottom_in[6] 0.0002231358 +2 sb_0__1__0_chany_top_out[6]:2 0.0002231358 +3 sb_0__1__0_chany_top_out[6]:3 0.0003127863 +4 sb_0__1_:chany_top_out[6] sb_0__1_:chany_top_out[14] 0.0002139862 +5 cby_0__2_:chany_bottom_in[6] cby_0__2_:chany_bottom_in[14] 9.448956e-06 +6 sb_0__1__0_chany_top_out[6]:2 sb_0__1__0_chany_top_out[14]:2 9.448956e-06 +7 sb_0__1__0_chany_top_out[6]:3 sb_0__1__0_chany_top_out[14]:3 0.0002139862 + +*RES +0 sb_0__1_:chany_top_out[6] sb_0__1__0_chany_top_out[6]:3 0.00147721 +1 sb_0__1__0_chany_top_out[6]:2 cby_0__2_:chany_bottom_in[6] 0.0002741666 +2 sb_0__1__0_chany_top_out[6]:3 sb_0__1__0_chany_top_out[6]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[17] 0.001172855 //LENGTH 11.020 LUMPCC 0.0002824977 DR + +*CONN +*I sb_0__1_:chany_top_out[17] O *L 0 *C 339.940 658.170 +*I cby_0__2_:chany_bottom_in[17] I *L 0 *C 339.940 669.190 +*N sb_0__1__0_chany_top_out[17]:2 *C 339.940 667.520 +*N sb_0__1__0_chany_top_out[17]:3 *C 339.940 667.519 + +*CAP +0 sb_0__1_:chany_top_out[17] 0.0003264058 +1 cby_0__2_:chany_bottom_in[17] 0.0001187727 +2 sb_0__1__0_chany_top_out[17]:2 0.0001187727 +3 sb_0__1__0_chany_top_out[17]:3 0.0003264058 +4 sb_0__1_:chany_top_out[17] sb_0__1_:chany_top_in[9] 0.0001340003 +5 cby_0__2_:chany_bottom_in[17] cby_0__2_:chany_bottom_out[9] 7.248536e-06 +6 sb_0__1__0_chany_top_out[17]:2 cby_0__1__1_chany_bottom_out[9]:3 7.248536e-06 +7 sb_0__1__0_chany_top_out[17]:3 cby_0__1__1_chany_bottom_out[9]:2 0.0001340003 + +*RES +0 sb_0__1_:chany_top_out[17] sb_0__1__0_chany_top_out[17]:3 0.008347322 +1 sb_0__1__0_chany_top_out[17]:2 cby_0__2_:chany_bottom_in[17] 0.001491072 +2 sb_0__1__0_chany_top_out[17]:3 sb_0__1__0_chany_top_out[17]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[8] 0.001260217 //LENGTH 7.660 LUMPCC 0.0006088887 DR + +*CONN +*I sb_0__2_:chanx_right_out[8] O *L 0 *C 400.050 874.480 +*I cbx_1__2_:chanx_left_in[8] I *L 0 *C 407.710 874.480 + +*CAP +0 sb_0__2_:chanx_right_out[8] 0.0003256642 +1 cbx_1__2_:chanx_left_in[8] 0.0003256642 +2 sb_0__2_:chanx_right_out[8] sb_0__2_:chanx_right_in[0] 0.0001082916 +3 cbx_1__2_:chanx_left_in[8] cbx_1__2__0_chanx_left_out[0]:2 0.0001082916 +4 sb_0__2_:chanx_right_out[8] sb_0__2_:chanx_right_out[6] 0.0001642495 +5 cbx_1__2_:chanx_left_in[8] cbx_1__2_:chanx_left_in[6] 0.0001642495 +6 sb_0__2_:chanx_right_out[8] sb_0__2_:chanx_right_out[17] 3.190323e-05 +7 cbx_1__2_:chanx_left_in[8] cbx_1__2_:chanx_left_in[17] 3.190323e-05 + +*RES +0 sb_0__2_:chanx_right_out[8] cbx_1__2_:chanx_left_in[8] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[2] 0.001243091 //LENGTH 11.020 LUMPCC 0.0005768166 DR + +*CONN +*I sb_0__2_:chany_bottom_out[2] O *L 0 *C 353.740 788.870 +*I cby_0__2_:chany_top_in[2] I *L 0 *C 353.740 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[2] 0.0003331373 +1 cby_0__2_:chany_top_in[2] 0.0003331373 +2 sb_0__2_:chany_bottom_out[2] sb_0__2_:chany_bottom_in[0] 0.0001442041 +3 cby_0__2_:chany_top_in[2] cby_0__2_:chany_top_out[0] 0.0001442041 +4 sb_0__2_:chany_bottom_out[2] sb_0__2_:chany_bottom_out[12] 0.0001442041 +5 cby_0__2_:chany_top_in[2] cby_0__2_:chany_top_in[12] 0.0001442041 + +*RES +0 sb_0__2_:chany_bottom_out[2] cby_0__2_:chany_top_in[2] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[16] 0.001169388 //LENGTH 11.020 LUMPCC 0.0002788242 DR + +*CONN +*I sb_0__2_:chany_bottom_out[16] O *L 0 *C 315.560 788.870 +*I cby_0__2_:chany_top_in[16] I *L 0 *C 315.560 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[16] 0.000445282 +1 cby_0__2_:chany_top_in[16] 0.000445282 +2 sb_0__2_:chany_bottom_out[16] sb_0__2_:chany_bottom_in[17] 8.33756e-05 +3 cby_0__2_:chany_top_in[16] cby_0__2_:chany_top_out[17] 8.33756e-05 +4 sb_0__2_:chany_bottom_out[16] sb_0__2_:chany_bottom_in[18] 5.60365e-05 +5 cby_0__2_:chany_top_in[16] cby_0__2_:chany_top_out[18] 5.60365e-05 + +*RES +0 sb_0__2_:chany_bottom_out[16] cby_0__2_:chany_top_in[16] 0.009839286 + +*END + +*D_NET sb_1__0__0_chanx_left_out[11] 0.001321891 //LENGTH 7.660 LUMPCC 0.0006493273 DR + +*CONN +*I sb_1__0_:chanx_left_out[11] O *L 0 *C 519.950 331.840 +*I cbx_1__0_:chanx_right_in[11] I *L 0 *C 512.290 331.840 + +*CAP +0 sb_1__0_:chanx_left_out[11] 0.0003362817 +1 cbx_1__0_:chanx_right_in[11] 0.0003362817 +2 sb_1__0_:chanx_left_out[11] sb_1__0_:chanx_left_in[12] 0.0001636673 +3 cbx_1__0_:chanx_right_in[11] cbx_1__0_:chanx_right_out[12] 0.0001636673 +4 sb_1__0_:chanx_left_out[11] sb_1__0_:chanx_left_out[15] 0.0001609963 +5 cbx_1__0_:chanx_right_in[11] cbx_1__0_:chanx_right_in[15] 0.0001609963 + +*RES +0 sb_1__0_:chanx_left_out[11] cbx_1__0_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[2] 0.001479883 //LENGTH 7.660 LUMPCC 0.0003220654 DR + +*CONN +*I sb_1__0_:chanx_right_out[2] O *L 0 *C 661.330 300.560 +*I cbx_2__0_:chanx_left_in[2] I *L 0 *C 668.990 300.560 +*N sb_1__0__0_chanx_right_out[2]:2 *C 667.520 300.560 +*N sb_1__0__0_chanx_right_out[2]:3 *C 667.519 300.560 + +*CAP +0 sb_1__0_:chanx_right_out[2] 0.00035887 +1 cbx_2__0_:chanx_left_in[2] 0.0002200387 +2 sb_1__0__0_chanx_right_out[2]:2 0.0002200387 +3 sb_1__0__0_chanx_right_out[2]:3 0.00035887 +4 sb_1__0_:chanx_right_out[2] sb_1__0_:chanx_right_in[3] 0.0001096605 +5 sb_1__0__0_chanx_right_out[2]:3 cbx_1__0__1_chanx_left_out[3]:2 0.0001096605 +6 sb_1__0_:chanx_right_out[2] sb_1__0_:chanx_right_in[16] 5.137222e-05 +7 sb_1__0__0_chanx_right_out[2]:3 cbx_1__0__1_chanx_left_out[16]:2 5.137222e-05 + +*RES +0 sb_1__0_:chanx_right_out[2] sb_1__0__0_chanx_right_out[2]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[2]:2 cbx_2__0_:chanx_left_in[2] 0.0002303 +2 sb_1__0__0_chanx_right_out[2]:3 sb_1__0__0_chanx_right_out[2]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[15] 0.001339205 //LENGTH 7.660 LUMPCC 0.0004203592 DR + +*CONN +*I sb_1__0_:chanx_right_out[15] O *L 0 *C 661.330 333.200 +*I cbx_2__0_:chanx_left_in[15] I *L 0 *C 668.990 333.200 +*N sb_1__0__0_chanx_right_out[15]:2 *C 667.520 333.200 +*N sb_1__0__0_chanx_right_out[15]:3 *C 667.519 333.200 + +*CAP +0 sb_1__0_:chanx_right_out[15] 0.000272578 +1 cbx_2__0_:chanx_left_in[15] 0.0001868447 +2 sb_1__0__0_chanx_right_out[15]:2 0.0001868447 +3 sb_1__0__0_chanx_right_out[15]:3 0.000272578 +4 sb_1__0_:chanx_right_out[15] sb_1__0_:chanx_right_out[9] 0.000133926 +5 cbx_2__0_:chanx_left_in[15] cbx_2__0_:chanx_left_in[9] 9.865685e-06 +6 sb_1__0__0_chanx_right_out[15]:2 sb_1__0__0_chanx_right_out[9]:2 9.865685e-06 +7 sb_1__0__0_chanx_right_out[15]:3 sb_1__0__0_chanx_right_out[9]:3 0.000133926 +8 sb_1__0_:chanx_right_out[15] sb_1__0_:chanx_right_out[16] 6.63879e-05 +9 sb_1__0__0_chanx_right_out[15]:3 sb_1__0__0_chanx_right_out[16]:3 6.63879e-05 + +*RES +0 sb_1__0_:chanx_right_out[15] sb_1__0__0_chanx_right_out[15]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[15]:2 cbx_2__0_:chanx_left_in[15] 0.0002303 +2 sb_1__0__0_chanx_right_out[15]:3 sb_1__0__0_chanx_right_out[15]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[11] 0.001076452 //LENGTH 11.020 LUMPCC 0.0001317318 DR + +*CONN +*I sb_1__0_:chany_top_out[11] O *L 0 *C 613.640 397.050 +*I cby_1__1_:chany_bottom_in[11] I *L 0 *C 613.640 408.070 + +*CAP +0 sb_1__0_:chany_top_out[11] 0.0004723603 +1 cby_1__1_:chany_bottom_in[11] 0.0004723603 +2 sb_1__0_:chany_top_out[11] sb_1__0_:chany_top_out[18] 6.586591e-05 +3 cby_1__1_:chany_bottom_in[11] cby_1__1_:chany_bottom_in[18] 6.586591e-05 + +*RES +0 sb_1__0_:chany_top_out[11] cby_1__1_:chany_bottom_in[11] 0.009839285 + +*END + +*D_NET sb_1__1__0_ccff_tail[0] 0.001268602 //LENGTH 7.660 LUMPCC 0.0003919323 DR + +*CONN +*I sb_1__1_:ccff_tail[0] O *L 0 *C 519.950 592.280 +*I cbx_1__1_:ccff_head[0] I *L 0 *C 512.290 592.280 + +*CAP +0 sb_1__1_:ccff_tail[0] 0.000438335 +1 cbx_1__1_:ccff_head[0] 0.000438335 +2 sb_1__1_:ccff_tail[0] sb_1__1_:chanx_left_out[0] 4.102018e-05 +3 cbx_1__1_:ccff_head[0] cbx_1__1_:chanx_right_in[0] 4.102018e-05 +4 sb_1__1_:ccff_tail[0] sb_1__1_:chanx_left_out[7] 0.000154946 +5 cbx_1__1_:ccff_head[0] cbx_1__1_:chanx_right_in[7] 0.000154946 + +*RES +0 sb_1__1_:ccff_tail[0] cbx_1__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[11] 0.001322232 //LENGTH 7.660 LUMPCC 0.0003757282 DR + +*CONN +*I sb_1__1_:chanx_left_out[11] O *L 0 *C 519.950 624.240 +*I cbx_1__1_:chanx_right_in[11] I *L 0 *C 512.290 624.240 + +*CAP +0 sb_1__1_:chanx_left_out[11] 0.0004732518 +1 cbx_1__1_:chanx_right_in[11] 0.0004732518 +2 sb_1__1_:chanx_left_out[11] sb_1__1_:chanx_left_in[12] 0.0001429824 +3 cbx_1__1_:chanx_right_in[11] cbx_1__1_:chanx_right_out[12] 0.0001429824 +4 sb_1__1_:chanx_left_out[11] sb_1__1_:chanx_left_in[13] 4.488169e-05 +5 cbx_1__1_:chanx_right_in[11] cbx_1__1_:chanx_right_out[13] 4.488169e-05 + +*RES +0 sb_1__1_:chanx_left_out[11] cbx_1__1_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[3] 0.001425557 //LENGTH 7.660 LUMPCC 0.0002097053 DR + +*CONN +*I sb_1__1_:chanx_right_out[3] O *L 0 *C 661.330 601.800 +*I cbx_2__1_:chanx_left_in[3] I *L 0 *C 668.990 601.800 +*N sb_1__1__0_chanx_right_out[3]:2 *C 667.520 601.800 +*N sb_1__1__0_chanx_right_out[3]:3 *C 667.519 601.800 + +*CAP +0 sb_1__1_:chanx_right_out[3] 0.0003878154 +1 cbx_2__1_:chanx_left_in[3] 0.0002201106 +2 sb_1__1__0_chanx_right_out[3]:2 0.0002201106 +3 sb_1__1__0_chanx_right_out[3]:3 0.0003878154 +4 sb_1__1_:chanx_right_out[3] sb_1__1_:chanx_right_in[6] 3.59257e-05 +5 sb_1__1__0_chanx_right_out[3]:3 cbx_1__1__1_chanx_left_out[6]:2 3.59257e-05 +6 sb_1__1_:chanx_right_out[3] sb_1__1_:chanx_right_out[5] 6.892695e-05 +7 sb_1__1__0_chanx_right_out[3]:3 sb_1__1__0_chanx_right_out[5]:3 6.892695e-05 + +*RES +0 sb_1__1_:chanx_right_out[3] sb_1__1__0_chanx_right_out[3]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[3]:2 cbx_2__1_:chanx_left_in[3] 0.0002303 +2 sb_1__1__0_chanx_right_out[3]:3 sb_1__1__0_chanx_right_out[3]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[16] 0.001590767 //LENGTH 7.660 LUMPCC 0.0004063247 DR + +*CONN +*I sb_1__1_:chanx_right_out[16] O *L 0 *C 661.330 568.480 +*I cbx_2__1_:chanx_left_in[16] I *L 0 *C 668.990 568.480 +*N sb_1__1__0_chanx_right_out[16]:2 *C 667.520 568.480 +*N sb_1__1__0_chanx_right_out[16]:3 *C 667.519 568.480 + +*CAP +0 sb_1__1_:chanx_right_out[16] 0.0003745994 +1 cbx_2__1_:chanx_left_in[16] 0.0002176217 +2 sb_1__1__0_chanx_right_out[16]:2 0.0002176217 +3 sb_1__1__0_chanx_right_out[16]:3 0.0003745994 +4 sb_1__1_:chanx_right_out[16] sb_1__1_:chanx_right_in[16] 0.0001007594 +5 sb_1__1__0_chanx_right_out[16]:3 cbx_1__1__1_chanx_left_out[16]:2 0.0001007594 +6 sb_1__1_:chanx_right_out[16] sb_1__1_:chanx_right_out[12] 0.0001007594 +7 cbx_2__1_:chanx_left_in[16] cbx_2__1_:chanx_left_in[12] 1.643599e-06 +8 sb_1__1__0_chanx_right_out[16]:2 sb_1__1__0_chanx_right_out[12]:2 1.643599e-06 +9 sb_1__1__0_chanx_right_out[16]:3 sb_1__1__0_chanx_right_out[12]:3 0.0001007594 + +*RES +0 sb_1__1_:chanx_right_out[16] sb_1__1__0_chanx_right_out[16]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[16]:2 cbx_2__1_:chanx_left_in[16] 0.0002303 +2 sb_1__1__0_chanx_right_out[16]:3 sb_1__1__0_chanx_right_out[16]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[10] 0.001228038 //LENGTH 11.020 LUMPCC 0.0002511719 DR + +*CONN +*I sb_1__1_:chany_bottom_out[10] O *L 0 *C 613.180 527.750 +*I cby_1__1_:chany_top_in[10] I *L 0 *C 613.180 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[10] 0.0004884328 +1 cby_1__1_:chany_top_in[10] 0.0004884328 +2 sb_1__1_:chany_bottom_out[10] sb_1__1_:chany_bottom_in[6] 0.000125586 +3 cby_1__1_:chany_top_in[10] cby_1__1_:chany_top_out[6] 0.000125586 + +*RES +0 sb_1__1_:chany_bottom_out[10] cby_1__1_:chany_top_in[10] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[0] 0.00122678 //LENGTH 11.020 LUMPCC 0.0005875248 DR + +*CONN +*I sb_1__1_:chany_top_out[0] O *L 0 *C 596.620 658.170 +*I cby_1__2_:chany_bottom_in[0] I *L 0 *C 596.620 669.190 +*N sb_1__1__0_chany_top_out[0]:2 *C 596.620 667.520 +*N sb_1__1__0_chany_top_out[0]:3 *C 596.620 667.519 + +*CAP +0 sb_1__1_:chany_top_out[0] 0.0002090199 +1 cby_1__2_:chany_bottom_in[0] 0.0001106075 +2 sb_1__1__0_chany_top_out[0]:2 0.0001106075 +3 sb_1__1__0_chany_top_out[0]:3 0.0002090199 +4 sb_1__1_:chany_top_out[0] sb_1__1_:chany_top_in[11] 0.0001357202 +5 cby_1__2_:chany_bottom_in[0] cby_1__2_:chany_bottom_out[11] 7.294814e-06 +6 sb_1__1__0_chany_top_out[0]:2 cby_1__1__1_chany_bottom_out[11]:3 7.294814e-06 +7 sb_1__1__0_chany_top_out[0]:3 cby_1__1__1_chany_bottom_out[11]:2 0.0001357202 +8 sb_1__1_:chany_top_out[0] sb_1__1_:chany_top_out[2] 0.000143306 +9 cby_1__2_:chany_bottom_in[0] cby_1__2_:chany_bottom_in[2] 7.441422e-06 +10 sb_1__1__0_chany_top_out[0]:2 sb_1__1__0_chany_top_out[2]:2 7.441422e-06 +11 sb_1__1__0_chany_top_out[0]:3 sb_1__1__0_chany_top_out[2]:3 0.000143306 + +*RES +0 sb_1__1_:chany_top_out[0] sb_1__1__0_chany_top_out[0]:3 0.008347321 +1 sb_1__1__0_chany_top_out[0]:2 cby_1__2_:chany_bottom_in[0] 0.001491072 +2 sb_1__1__0_chany_top_out[0]:3 sb_1__1__0_chany_top_out[0]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[15] 0.001282269 //LENGTH 11.020 LUMPCC 0.000622875 DR + +*CONN +*I sb_1__1_:chany_top_out[15] O *L 0 *C 570.860 658.170 +*I cby_1__2_:chany_bottom_in[15] I *L 0 *C 570.860 669.190 +*N sb_1__1__0_chany_top_out[15]:2 *C 570.860 667.520 +*N sb_1__1__0_chany_top_out[15]:3 *C 570.860 667.519 + +*CAP +0 sb_1__1_:chany_top_out[15] 0.0002187595 +1 cby_1__2_:chany_bottom_in[15] 0.0001109373 +2 sb_1__1__0_chany_top_out[15]:2 0.0001109373 +3 sb_1__1__0_chany_top_out[15]:3 0.0002187595 +4 sb_1__1_:chany_top_out[15] sb_1__1_:chany_top_in[4] 0.0001377969 +5 cby_1__2_:chany_bottom_in[15] cby_1__2_:chany_bottom_out[4] 7.340376e-06 +6 sb_1__1__0_chany_top_out[15]:2 cby_1__1__1_chany_bottom_out[4]:3 7.340376e-06 +7 sb_1__1__0_chany_top_out[15]:3 cby_1__1__1_chany_bottom_out[4]:2 0.0001377969 +8 sb_1__1_:chany_top_out[15] sb_1__1_:chany_top_out[7] 8.626484e-05 +9 sb_1__1_:chany_top_out[15] sb_1__1__0_chany_top_out[7]:4 3.339434e-06 +10 sb_1__1_:chany_top_out[15] sb_1__1__0_chany_top_out[7]:6 6.935558e-05 +11 cby_1__2_:chany_bottom_in[15] cby_1__2_:chany_bottom_in[7] 7.340376e-06 +12 sb_1__1__0_chany_top_out[15]:2 sb_1__1__0_chany_top_out[7]:2 7.340376e-06 +13 sb_1__1__0_chany_top_out[15]:3 sb_1__1__0_chany_top_out[7]:3 3.339434e-06 +14 sb_1__1__0_chany_top_out[15]:3 sb_1__1__0_chany_top_out[7]:5 6.935558e-05 +15 sb_1__1__0_chany_top_out[15]:3 sb_1__1__0_chany_top_out[7]:7 8.626484e-05 + +*RES +0 sb_1__1_:chany_top_out[15] sb_1__1__0_chany_top_out[15]:3 0.008347322 +1 sb_1__1__0_chany_top_out[15]:2 cby_1__2_:chany_bottom_in[15] 0.001491072 +2 sb_1__1__0_chany_top_out[15]:3 sb_1__1__0_chany_top_out[15]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[11] 0.001393607 //LENGTH 7.660 LUMPCC 0.0005640754 DR + +*CONN +*I sb_1__2_:chanx_left_out[11] O *L 0 *C 519.950 881.280 +*I cbx_1__2_:chanx_right_in[11] I *L 0 *C 512.290 881.280 + +*CAP +0 sb_1__2_:chanx_left_out[11] 0.0004147657 +1 cbx_1__2_:chanx_right_in[11] 0.0004147657 +2 sb_1__2_:chanx_left_out[11] sb_1__2_:chanx_left_out[1] 0.0001410189 +3 cbx_1__2_:chanx_right_in[11] cbx_1__2_:chanx_right_in[1] 0.0001410189 +4 sb_1__2_:chanx_left_out[11] sb_1__2_:chanx_left_out[17] 0.0001410189 +5 cbx_1__2_:chanx_right_in[11] cbx_1__2_:chanx_right_in[17] 0.0001410189 + +*RES +0 sb_1__2_:chanx_left_out[11] cbx_1__2_:chanx_right_in[11] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[4] 0.001412455 //LENGTH 7.660 LUMPCC 0.0005593678 DR + +*CONN +*I sb_1__2_:chanx_right_out[4] O *L 0 *C 661.330 867.680 +*I cbx_2__2_:chanx_left_in[4] I *L 0 *C 668.990 867.680 +*N sb_1__2__0_chanx_right_out[4]:2 *C 667.520 867.680 +*N sb_1__2__0_chanx_right_out[4]:3 *C 667.519 867.680 + +*CAP +0 sb_1__2_:chanx_right_out[4] 0.0002470235 +1 cbx_2__2_:chanx_left_in[4] 0.00017952 +2 sb_1__2__0_chanx_right_out[4]:2 0.00017952 +3 sb_1__2__0_chanx_right_out[4]:3 0.0002470235 +4 sb_1__2_:chanx_right_out[4] sb_1__2_:chanx_right_in[8] 0.000133724 +5 cbx_2__2_:chanx_left_in[4] cbx_2__2_:chanx_left_out[8] 9.865685e-06 +6 sb_1__2__0_chanx_right_out[4]:2 cbx_1__2__1_chanx_left_out[8]:3 9.865685e-06 +7 sb_1__2__0_chanx_right_out[4]:3 cbx_1__2__1_chanx_left_out[8]:2 0.000133724 +8 sb_1__2_:chanx_right_out[4] sb_1__2_:chanx_right_in[10] 0.0001295171 +9 cbx_2__2_:chanx_left_in[4] cbx_2__2_:chanx_left_out[10] 6.577123e-06 +10 sb_1__2__0_chanx_right_out[4]:2 cbx_1__2__1_chanx_left_out[10]:3 6.577123e-06 +11 sb_1__2__0_chanx_right_out[4]:3 cbx_1__2__1_chanx_left_out[10]:2 0.0001295171 + +*RES +0 sb_1__2_:chanx_right_out[4] sb_1__2__0_chanx_right_out[4]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[4]:2 cbx_2__2_:chanx_left_in[4] 0.0002303 +2 sb_1__2__0_chanx_right_out[4]:3 sb_1__2__0_chanx_right_out[4]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[17] 0.001406278 //LENGTH 7.660 LUMPCC 0.0004624816 DR + +*CONN +*I sb_1__2_:chanx_right_out[17] O *L 0 *C 661.330 877.200 +*I cbx_2__2_:chanx_left_in[17] I *L 0 *C 668.990 877.200 +*N sb_1__2__0_chanx_right_out[17]:2 *C 667.520 877.200 +*N sb_1__2__0_chanx_right_out[17]:3 *C 667.519 877.200 + +*CAP +0 sb_1__2_:chanx_right_out[17] 0.0002802828 +1 cbx_2__2_:chanx_left_in[17] 0.0001916152 +2 sb_1__2__0_chanx_right_out[17]:2 0.0001916152 +3 sb_1__2__0_chanx_right_out[17]:3 0.0002802828 +4 sb_1__2_:chanx_right_out[17] sb_1__2_:chanx_right_in[0] 7.500139e-05 +5 sb_1__2__0_chanx_right_out[17]:3 cbx_1__2__1_chanx_left_out[0]:2 7.500139e-05 +6 sb_1__2_:chanx_right_out[17] sb_1__2_:chanx_right_out[8] 2.360538e-05 +7 sb_1__2__0_chanx_right_out[17]:3 sb_1__2__0_chanx_right_out[8]:3 2.360538e-05 +8 sb_1__2_:chanx_right_out[17] sb_1__2_:chanx_right_out[18] 0.0001260579 +9 cbx_2__2_:chanx_left_in[17] cbx_2__2_:chanx_left_in[18] 6.576165e-06 +10 sb_1__2__0_chanx_right_out[17]:2 sb_1__2__0_chanx_right_out[18]:2 6.576165e-06 +11 sb_1__2__0_chanx_right_out[17]:3 sb_1__2__0_chanx_right_out[18]:3 0.0001260579 + +*RES +0 sb_1__2_:chanx_right_out[17] sb_1__2__0_chanx_right_out[17]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[17]:2 cbx_2__2_:chanx_left_in[17] 0.0002303 +2 sb_1__2__0_chanx_right_out[17]:3 sb_1__2__0_chanx_right_out[17]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[10] 0.001202686 //LENGTH 11.020 LUMPCC 0.000263361 DR + +*CONN +*I sb_1__2_:chany_bottom_out[10] O *L 0 *C 613.180 788.870 +*I cby_1__2_:chany_top_in[10] I *L 0 *C 613.180 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[10] 0.0004696627 +1 cby_1__2_:chany_top_in[10] 0.0004696627 +2 sb_1__2_:chany_bottom_out[10] sb_1__2_:chany_bottom_in[6] 0.0001316805 +3 cby_1__2_:chany_top_in[10] cby_1__2_:chany_top_out[6] 0.0001316805 + +*RES +0 sb_1__2_:chany_bottom_out[10] cby_1__2_:chany_top_in[10] 0.009839285 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[18] 0.00124668 //LENGTH 11.020 LUMPCC 0.0004131921 DR + +*CONN +*I sb_1__2_:chany_bottom_out[18] O *L 0 *C 592.940 788.870 +*I cby_1__2_:chany_top_in[18] I *L 0 *C 592.940 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[18] 0.0004167438 +1 cby_1__2_:chany_top_in[18] 0.0004167438 +2 sb_1__2_:chany_bottom_out[18] sb_1__2_:chany_bottom_out[5] 7.69995e-05 +3 cby_1__2_:chany_top_in[18] cby_1__2_:chany_top_in[5] 7.69995e-05 +4 sb_1__2_:chany_bottom_out[18] sb_1__2_:chany_bottom_out[11] 0.0001295966 +5 cby_1__2_:chany_top_in[18] cby_1__2_:chany_top_in[11] 0.0001295966 + +*RES +0 sb_1__2_:chany_bottom_out[18] cby_1__2_:chany_top_in[18] 0.009839286 + +*END + +*D_NET sb_2__0__0_chanx_left_out[8] 0.001405661 //LENGTH 7.660 LUMPCC 0.000565909 DR + +*CONN +*I sb_2__0_:chanx_left_out[8] O *L 0 *C 781.230 315.520 +*I cbx_2__0_:chanx_right_in[8] I *L 0 *C 773.570 315.520 + +*CAP +0 sb_2__0_:chanx_left_out[8] 0.0004198758 +1 cbx_2__0_:chanx_right_in[8] 0.0004198758 +2 sb_2__0_:chanx_left_out[8] sb_2__0_:chanx_left_out[10] 0.000145226 +3 cbx_2__0_:chanx_right_in[8] cbx_2__0_:chanx_right_in[10] 0.000145226 +4 sb_2__0_:chanx_left_out[8] sb_2__0_:chanx_left_out[12] 0.0001377285 +5 cbx_2__0_:chanx_right_in[8] cbx_2__0_:chanx_right_in[12] 0.0001377285 + +*RES +0 sb_2__0_:chanx_left_out[8] cbx_2__0_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[19] 0.001410018 //LENGTH 7.660 LUMPCC 0.0004266647 DR + +*CONN +*I sb_2__0_:chanx_left_out[19] O *L 0 *C 781.230 352.240 +*I cbx_2__0_:chanx_right_in[19] I *L 0 *C 773.570 352.240 + +*CAP +0 sb_2__0_:chanx_left_out[19] 0.0004916765 +1 cbx_2__0_:chanx_right_in[19] 0.0004916765 +2 sb_2__0_:chanx_left_out[19] sb_2__0_:chanx_left_in[2] 4.971271e-05 +3 cbx_2__0_:chanx_right_in[19] cbx_1__0__1_chanx_right_out[2]:2 4.971271e-05 +4 sb_2__0_:chanx_left_out[19] sb_2__0_:ccff_tail[0] 3.036709e-05 +5 cbx_2__0_:chanx_right_in[19] cbx_2__0_:ccff_head[0] 3.036709e-05 +6 sb_2__0_:chanx_left_out[19] sb_2__0_:chanx_left_out[3] 0.0001332525 +7 cbx_2__0_:chanx_right_in[19] cbx_2__0_:chanx_right_in[3] 0.0001332525 + +*RES +0 sb_2__0_:chanx_left_out[19] cbx_2__0_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[16] 0.001051979 //LENGTH 11.020 LUMPCC 9.656881e-05 DR + +*CONN +*I sb_2__0_:chany_top_out[16] O *L 0 *C 868.020 397.050 +*I cby_2__1_:chany_bottom_in[16] I *L 0 *C 868.020 408.070 + +*CAP +0 sb_2__0_:chany_top_out[16] 0.000477705 +1 cby_2__1_:chany_bottom_in[16] 0.000477705 +2 sb_2__0_:chany_top_out[16] sb_2__0_:chany_top_in[18] 4.82844e-05 +3 cby_2__1_:chany_bottom_in[16] cby_2__1_:chany_bottom_out[18] 4.82844e-05 + +*RES +0 sb_2__0_:chany_top_out[16] cby_2__1_:chany_bottom_in[16] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[3] 0.001490766 //LENGTH 7.660 LUMPCC 0.0002689045 DR + +*CONN +*I sb_2__1_:chanx_left_out[3] O *L 0 *C 781.230 602.480 +*I cbx_2__1_:chanx_right_in[3] I *L 0 *C 773.570 602.480 + +*CAP +0 sb_2__1_:chanx_left_out[3] 0.000610931 +1 cbx_2__1_:chanx_right_in[3] 0.000610931 +2 sb_2__1_:chanx_left_out[3] sb_2__1_:chanx_left_in[0] 9.55949e-05 +3 cbx_2__1_:chanx_right_in[3] cbx_2__1_:chanx_right_out[0] 9.55949e-05 +4 sb_2__1_:chanx_left_out[3] sb_2__1_:chanx_left_in[9] 3.885734e-05 +5 cbx_2__1_:chanx_right_in[3] cbx_2__1_:chanx_right_out[9] 3.885734e-05 + +*RES +0 sb_2__1_:chanx_left_out[3] cbx_2__1_:chanx_right_in[3] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[17] 0.001537779 //LENGTH 7.660 LUMPCC 0.0002702698 DR + +*CONN +*I sb_2__1_:chanx_left_out[17] O *L 0 *C 781.230 616.080 +*I cbx_2__1_:chanx_right_in[17] I *L 0 *C 773.570 616.080 + +*CAP +0 sb_2__1_:chanx_left_out[17] 0.0006337547 +1 cbx_2__1_:chanx_right_in[17] 0.0006337547 +2 sb_2__1_:chanx_left_out[17] sb_2__1_:chanx_left_in[5] 9.642568e-05 +3 cbx_2__1_:chanx_right_in[17] cbx_2__1_:chanx_right_out[5] 9.642568e-05 +4 sb_2__1_:chanx_left_out[17] sb_2__1_:chanx_left_out[19] 3.870922e-05 +5 cbx_2__1_:chanx_right_in[17] cbx_2__1_:chanx_right_in[19] 3.870922e-05 + +*RES +0 sb_2__1_:chanx_left_out[17] cbx_2__1_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[14] 0.001208477 //LENGTH 11.020 LUMPCC 0.0002693979 DR + +*CONN +*I sb_2__1_:chany_bottom_out[14] O *L 0 *C 878.600 527.750 +*I cby_2__1_:chany_top_in[14] I *L 0 *C 878.600 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[14] 0.0004695396 +1 cby_2__1_:chany_top_in[14] 0.0004695396 +2 sb_2__1_:chany_bottom_out[14] sb_2__1_:chany_bottom_out[4] 0.0001346989 +3 cby_2__1_:chany_top_in[14] cby_2__1_:chany_top_in[4] 0.0001346989 + +*RES +0 sb_2__1_:chany_bottom_out[14] cby_2__1_:chany_top_in[14] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[2] 0.001255383 //LENGTH 11.020 LUMPCC 0.0005531847 DR + +*CONN +*I sb_2__1_:chany_top_out[2] O *L 0 *C 858.820 658.170 +*I cby_2__2_:chany_bottom_in[2] I *L 0 *C 858.820 669.190 +*N sb_2__1__0_chany_top_out[2]:2 *C 858.820 667.520 +*N sb_2__1__0_chany_top_out[2]:3 *C 858.820 667.519 + +*CAP +0 sb_2__1_:chany_top_out[2] 0.0002401616 +1 cby_2__2_:chany_bottom_in[2] 0.0001109373 +2 sb_2__1__0_chany_top_out[2]:2 0.0001109373 +3 sb_2__1__0_chany_top_out[2]:3 0.0002401616 +4 sb_2__1_:chany_top_out[2] sb_2__1_:chany_top_out[0] 0.0001309558 +5 cby_2__2_:chany_bottom_in[2] cby_2__2_:chany_bottom_in[0] 7.340376e-06 +6 sb_2__1__0_chany_top_out[2]:2 sb_2__1__0_chany_top_out[0]:2 7.340376e-06 +7 sb_2__1__0_chany_top_out[2]:3 sb_2__1__0_chany_top_out[0]:3 0.0001309558 +8 sb_2__1_:chany_top_out[2] sb_2__1_:chany_top_out[19] 0.0001309558 +9 cby_2__2_:chany_bottom_in[2] cby_2__2_:chany_bottom_in[19] 7.340376e-06 +10 sb_2__1__0_chany_top_out[2]:2 sb_2__1__0_chany_top_out[19]:2 7.340376e-06 +11 sb_2__1__0_chany_top_out[2]:3 sb_2__1__0_chany_top_out[19]:3 0.0001309558 + +*RES +0 sb_2__1_:chany_top_out[2] sb_2__1__0_chany_top_out[2]:3 0.008347321 +1 sb_2__1__0_chany_top_out[2]:2 cby_2__2_:chany_bottom_in[2] 0.001491072 +2 sb_2__1__0_chany_top_out[2]:3 sb_2__1__0_chany_top_out[2]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[17] 0.00119958 //LENGTH 11.020 LUMPCC 0.0004646215 DR + +*CONN +*I sb_2__1_:chany_top_out[17] O *L 0 *C 843.180 658.170 +*I cby_2__2_:chany_bottom_in[17] I *L 0 *C 843.180 669.190 +*N sb_2__1__0_chany_top_out[17]:2 *C 843.180 667.520 +*N sb_2__1__0_chany_top_out[17]:3 *C 843.180 667.519 + +*CAP +0 sb_2__1_:chany_top_out[17] 0.0002478072 +1 cby_2__2_:chany_bottom_in[17] 0.0001196719 +2 sb_2__1__0_chany_top_out[17]:2 0.0001196719 +3 sb_2__1__0_chany_top_out[17]:3 0.0002478072 +4 sb_2__1_:chany_top_out[17] sb_2__1_:chany_top_in[13] 8.88725e-05 +5 cby_2__2_:chany_bottom_in[17] cby_2__2_:chany_bottom_out[13] 6.088952e-07 +6 sb_2__1__0_chany_top_out[17]:2 cby_1__1__3_chany_bottom_out[13]:3 6.088952e-07 +7 sb_2__1__0_chany_top_out[17]:3 cby_1__1__3_chany_bottom_out[13]:2 8.88725e-05 +8 sb_2__1_:chany_top_out[17] sb_2__1_:chany_top_out[1] 0.0001353879 +9 cby_2__2_:chany_bottom_in[17] cby_2__2_:chany_bottom_in[1] 7.441422e-06 +10 sb_2__1__0_chany_top_out[17]:2 sb_2__1__0_chany_top_out[1]:2 7.441422e-06 +11 sb_2__1__0_chany_top_out[17]:3 sb_2__1__0_chany_top_out[1]:3 0.0001353879 + +*RES +0 sb_2__1_:chany_top_out[17] sb_2__1__0_chany_top_out[17]:3 0.008347322 +1 sb_2__1__0_chany_top_out[17]:2 cby_2__2_:chany_bottom_in[17] 0.001491072 +2 sb_2__1__0_chany_top_out[17]:3 sb_2__1__0_chany_top_out[17]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[13] 0.001407195 //LENGTH 7.660 LUMPCC 0.0005781339 DR + +*CONN +*I sb_2__2_:chanx_left_out[13] O *L 0 *C 781.230 875.840 +*I cbx_2__2_:chanx_right_in[13] I *L 0 *C 773.570 875.840 + +*CAP +0 sb_2__2_:chanx_left_out[13] 0.0004145304 +1 cbx_2__2_:chanx_right_in[13] 0.0004145304 +2 sb_2__2_:chanx_left_out[13] sb_2__2_:chanx_left_out[8] 0.0001445335 +3 cbx_2__2_:chanx_right_in[13] cbx_2__2_:chanx_right_in[8] 0.0001445335 +4 sb_2__2_:chanx_left_out[13] sb_2__2_:chanx_left_out[19] 0.0001445335 +5 cbx_2__2_:chanx_right_in[13] cbx_2__2_:chanx_right_in[19] 0.0001445335 + +*RES +0 sb_2__2_:chanx_left_out[13] cbx_2__2_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[7] 0.001254364 //LENGTH 11.020 LUMPCC 0.0005656789 DR + +*CONN +*I sb_2__2_:chany_bottom_out[7] O *L 0 *C 841.800 788.870 +*I cby_2__2_:chany_top_in[7] I *L 0 *C 841.800 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[7] 0.0003443428 +1 cby_2__2_:chany_top_in[7] 0.0003443428 +2 sb_2__2_:chany_bottom_out[7] sb_2__2_:chany_bottom_out[1] 0.0001414197 +3 cby_2__2_:chany_top_in[7] cby_2__2_:chany_top_in[1] 0.0001414197 +4 sb_2__2_:chany_bottom_out[7] sb_2__2_:chany_bottom_out[13] 0.0001414197 +5 cby_2__2_:chany_top_in[7] cby_2__2_:chany_top_in[13] 0.0001414197 + +*RES +0 sb_2__2_:chany_bottom_out[7] cby_2__2_:chany_top_in[7] 0.009839286 + +*END + +*D_NET ctsbuf_net_110 0.02951904 //LENGTH 280.725 LUMPCC 0.000788955 DR + +*CONN +*I cts_inv_73507625:Y O *L 0 *C 799.480 552.840 +*I cby_2__1_:prog_clk[0] I *L 0 *C 809.750 497.760 +*I grid_io_right_3__1_:prog_clk[0] I *L 0 *C 911.260 408.070 +*I sb_2__0_:prog_clk[0] I *L 0 *C 809.750 393.720 +*N ctsbuf_net_110:4 *C 808.688 393.720 +*N ctsbuf_net_110:5 *C 808.680 393.778 +*N ctsbuf_net_110:6 *C 911.260 401.938 +*N ctsbuf_net_110:7 *C 911.253 401.880 +*N ctsbuf_net_110:8 *C 891.520 401.880 +*N ctsbuf_net_110:9 *C 891.519 401.880 +*N ctsbuf_net_110:10 *C 858.515 401.880 +*N ctsbuf_net_110:11 *C 808.688 401.880 +*N ctsbuf_net_110:12 *C 808.680 401.880 +*N ctsbuf_net_110:13 *C 808.680 443.519 +*N ctsbuf_net_110:14 *C 808.680 443.520 +*N ctsbuf_net_110:15 *C 808.680 451.880 +*N ctsbuf_net_110:16 *C 808.688 497.760 +*N ctsbuf_net_110:17 *C 808.680 497.760 +*N ctsbuf_net_110:18 *C 808.680 547.760 +*N ctsbuf_net_110:19 *C 808.680 552.795 +*N ctsbuf_net_110:20 *C 808.635 552.840 +*N ctsbuf_net_110:21 *C 799.518 552.840 + +*CAP +0 cts_inv_73507625:Y 1e-06 +1 cby_2__1_:prog_clk[0] 0.0001207111 +2 grid_io_right_3__1_:prog_clk[0] 0.0002750922 +3 sb_2__0_:prog_clk[0] 0.0001418525 +4 ctsbuf_net_110:4 0.0001418525 +5 ctsbuf_net_110:5 0.0004175991 +6 ctsbuf_net_110:6 0.0002750922 +7 ctsbuf_net_110:7 0.0007054301 +8 ctsbuf_net_110:8 0.0007054301 +9 ctsbuf_net_110:9 0.001694056 +10 ctsbuf_net_110:10 0.00429007 +11 ctsbuf_net_110:11 0.002596014 +12 ctsbuf_net_110:12 0.002584947 +13 ctsbuf_net_110:13 0.002133694 +14 ctsbuf_net_110:14 0.0004321283 +15 ctsbuf_net_110:15 0.00283682 +16 ctsbuf_net_110:16 0.0001207111 +17 ctsbuf_net_110:17 0.004986428 +18 ctsbuf_net_110:18 0.002821637 +19 ctsbuf_net_110:19 0.0002757592 +20 ctsbuf_net_110:20 0.0005868819 +21 ctsbuf_net_110:21 0.0005868819 +22 ctsbuf_net_110:12 sb_2__0_:top_left_grid_pin_35_[0] 1.045257e-05 +23 ctsbuf_net_110:12 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 8.338122e-06 +24 ctsbuf_net_110:11 grid_clb_2__1_:right_width_0_height_0__pin_35_lower[0] 3.504183e-05 +25 ctsbuf_net_110:5 sb_2__0_:top_left_grid_pin_35_[0] 8.338122e-06 +26 ctsbuf_net_110:10 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:3 3.504183e-05 +27 ctsbuf_net_110:13 grid_clb_2_right_width_0_height_0__pin_35_lower[0]:2 1.045257e-05 +28 ctsbuf_net_110:17 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 4.692768e-05 +29 ctsbuf_net_110:18 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 4.692768e-05 +30 grid_io_right_3__1_:prog_clk[0] grid_io_right_3__1_:left_width_0_height_0__pin_1_lower[0] 4.573536e-05 +31 ctsbuf_net_110:6 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 4.573536e-05 +32 ctsbuf_net_110:7 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 0.000247982 +33 ctsbuf_net_110:8 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 0.000247982 + +*RES +0 cts_inv_73507625:Y ctsbuf_net_110:21 0.152 +1 ctsbuf_net_110:20 ctsbuf_net_110:19 0.0045 +2 ctsbuf_net_110:19 ctsbuf_net_110:18 0.004495536 +3 ctsbuf_net_110:21 ctsbuf_net_110:20 0.008140625 +4 ctsbuf_net_110:17 ctsbuf_net_110:16 0.00341 +5 ctsbuf_net_110:17 ctsbuf_net_110:15 0.04096429 +6 ctsbuf_net_110:16 cby_2__1_:prog_clk[0] 0.0001664583 +7 ctsbuf_net_110:12 ctsbuf_net_110:11 0.00341 +8 ctsbuf_net_110:12 ctsbuf_net_110:5 0.007234375 +9 ctsbuf_net_110:11 ctsbuf_net_110:10 0.007806308 +10 ctsbuf_net_110:6 grid_io_right_3__1_:prog_clk[0] 0.005475447 +11 ctsbuf_net_110:7 ctsbuf_net_110:6 0.00341 +12 ctsbuf_net_110:5 ctsbuf_net_110:4 0.00341 +13 ctsbuf_net_110:4 sb_2__0_:prog_clk[0] 0.0001664583 +14 ctsbuf_net_110:15 ctsbuf_net_110:14 0.007464286 +15 ctsbuf_net_110:18 ctsbuf_net_110:17 0.04464286 +16 ctsbuf_net_110:10 ctsbuf_net_110:9 0.005170627 +17 ctsbuf_net_110:8 ctsbuf_net_110:7 0.003091425 +18 ctsbuf_net_110:9 ctsbuf_net_110:8 1e-05 +19 ctsbuf_net_110:14 ctsbuf_net_110:13 1e-05 +20 ctsbuf_net_110:13 ctsbuf_net_110:12 0.03717768 + +*END + +*D_NET ropt_net_36 0.002113165 //LENGTH 20.295 LUMPCC 0.0005787962 DR + +*CONN +*I ropt_h_inst_7754:X O *L 0 *C 661.020 909.160 +*I sb_1__2_:ccff_head[0] I *L 0 *C 658.260 892.090 +*N ropt_net_36:2 *C 658.260 909.115 +*N ropt_net_36:3 *C 658.305 909.160 +*N ropt_net_36:4 *C 660.983 909.160 + +*CAP +0 ropt_h_inst_7754:X 1e-06 +1 sb_1__2_:ccff_head[0] 0.0006221783 +2 ropt_net_36:2 0.0006221783 +3 ropt_net_36:3 0.0001445061 +4 ropt_net_36:4 0.0001445061 +5 sb_1__2_:ccff_head[0] sb_1__2_:right_top_grid_pin_1_[0] 0.0002396411 +6 ropt_net_36:2 grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]:2 0.0002396411 +7 ropt_net_36:3 ropt_net_35:2 4.975696e-05 +8 ropt_net_36:4 ropt_net_35:3 4.975696e-05 + +*RES +0 ropt_h_inst_7754:X ropt_net_36:4 0.152 +1 ropt_net_36:3 ropt_net_36:2 0.0045 +2 ropt_net_36:2 sb_1__2_:ccff_head[0] 0.01520089 +3 ropt_net_36:4 ropt_net_36:3 0.002390625 + +*END + +*D_NET gfpga_pad_GPIO_A[4] 0.02318491 //LENGTH 260.775 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_1__0_:gfpga_pad_GPIO_A[0] O *L 0 *C 470.120 261.190 +*P gfpga_pad_GPIO_A[4] O *L 0 *C 470.120 0.415 +*N gfpga_pad_GPIO_A[4]:2 *C 470.120 50.415 +*N gfpga_pad_GPIO_A[4]:3 *C 470.120 100.415 +*N gfpga_pad_GPIO_A[4]:4 *C 470.120 150.415 +*N gfpga_pad_GPIO_A[4]:5 *C 470.120 200.415 +*N gfpga_pad_GPIO_A[4]:6 *C 470.120 219.519 +*N gfpga_pad_GPIO_A[4]:7 *C 470.120 219.520 +*N gfpga_pad_GPIO_A[4]:8 *C 470.120 250.415 + +*CAP +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_A[0] 0.0005076892 +1 gfpga_pad_GPIO_A[4] 0.002229644 +2 gfpga_pad_GPIO_A[4]:2 0.004434092 +3 gfpga_pad_GPIO_A[4]:3 0.004425321 +4 gfpga_pad_GPIO_A[4]:4 0.004446289 +5 gfpga_pad_GPIO_A[4]:5 0.003055012 +6 gfpga_pad_GPIO_A[4]:6 0.0008295974 +7 gfpga_pad_GPIO_A[4]:7 0.001374788 +8 gfpga_pad_GPIO_A[4]:8 0.001882477 + +*RES +0 grid_io_bottom_1__0_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[4]:8 0.009620536 +1 gfpga_pad_GPIO_A[4]:2 gfpga_pad_GPIO_A[4] 0.04464286 +2 gfpga_pad_GPIO_A[4]:3 gfpga_pad_GPIO_A[4]:2 0.04464286 +3 gfpga_pad_GPIO_A[4]:4 gfpga_pad_GPIO_A[4]:3 0.04464286 +4 gfpga_pad_GPIO_A[4]:5 gfpga_pad_GPIO_A[4]:4 0.04464286 +5 gfpga_pad_GPIO_A[4]:8 gfpga_pad_GPIO_A[4]:7 0.02758482 +6 gfpga_pad_GPIO_A[4]:7 gfpga_pad_GPIO_A[4]:6 1e-05 +7 gfpga_pad_GPIO_A[4]:6 gfpga_pad_GPIO_A[4]:5 0.01705714 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[9] 0.001225212 //LENGTH 11.020 LUMPCC 0.0006079205 DR + +*CONN +*I cby_0__1_:chany_bottom_out[9] O *L 0 *C 339.020 408.070 +*I sb_0__0_:chany_top_in[9] I *L 0 *C 339.020 397.050 + +*CAP +0 cby_0__1_:chany_bottom_out[9] 0.0003086459 +1 sb_0__0_:chany_top_in[9] 0.0003086459 +2 cby_0__1_:chany_bottom_out[9] cby_0__1_:chany_bottom_in[11] 0.0001519801 +3 sb_0__0_:chany_top_in[9] sb_0__0_:chany_top_out[11] 0.0001519801 +4 cby_0__1_:chany_bottom_out[9] cby_0__1_:chany_bottom_in[17] 0.0001519801 +5 sb_0__0_:chany_top_in[9] sb_0__0_:chany_top_out[17] 0.0001519801 + +*RES +0 cby_0__1_:chany_bottom_out[9] sb_0__0_:chany_top_in[9] 0.009839285 + +*END + +*D_NET cby_0__1__0_chany_bottom_out[16] 0.001327819 //LENGTH 11.180 LUMPCC 0 DR + +*CONN +*I cby_0__1_:chany_bottom_out[16] O *L 0 *C 345.920 408.150 +*I sb_0__0_:chany_top_in[16] I *L 0 *C 345.920 396.970 + +*CAP +0 cby_0__1_:chany_bottom_out[16] 0.0006639095 +1 sb_0__0_:chany_top_in[16] 0.0006639095 + +*RES +0 cby_0__1_:chany_bottom_out[16] sb_0__0_:chany_top_in[16] 0.001751533 + +*END + +*D_NET cby_0__1__0_chany_top_out[1] 0.001215373 //LENGTH 11.020 LUMPCC 0.0002600501 DR + +*CONN +*I cby_0__1_:chany_top_out[1] O *L 0 *C 301.760 516.730 +*I sb_0__1_:chany_bottom_in[1] I *L 0 *C 301.760 527.750 + +*CAP +0 cby_0__1_:chany_top_out[1] 0.0004776613 +1 sb_0__1_:chany_bottom_in[1] 0.0004776613 +2 cby_0__1_:chany_top_out[1] cby_0__1_:chany_top_out[3] 0.0001300251 +3 sb_0__1_:chany_bottom_in[1] sb_0__1_:chany_bottom_in[3] 0.0001300251 + +*RES +0 cby_0__1_:chany_top_out[1] sb_0__1_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[5] 0.001290527 //LENGTH 11.020 LUMPCC 0.000513992 DR + +*CONN +*I cby_0__1_:chany_top_out[5] O *L 0 *C 336.260 516.730 +*I sb_0__1_:chany_bottom_in[5] I *L 0 *C 336.260 527.750 + +*CAP +0 cby_0__1_:chany_top_out[5] 0.0003882677 +1 sb_0__1_:chany_bottom_in[5] 0.0003882677 +2 cby_0__1_:chany_top_out[5] cby_0__1_:chany_top_in[0] 0.0001285164 +3 sb_0__1_:chany_bottom_in[5] sb_0__1_:chany_bottom_out[0] 0.0001285164 +4 cby_0__1_:chany_top_out[5] cby_0__1_:chany_top_in[11] 0.0001284796 +5 sb_0__1_:chany_bottom_in[5] sb_0__1_:chany_bottom_out[11] 0.0001284796 + +*RES +0 cby_0__1_:chany_top_out[5] sb_0__1_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[11] 0.001223799 //LENGTH 11.020 LUMPCC 0.0002579176 DR + +*CONN +*I cby_0__1_:chany_top_out[11] O *L 0 *C 317.860 516.730 +*I sb_0__1_:chany_bottom_in[11] I *L 0 *C 317.860 527.750 + +*CAP +0 cby_0__1_:chany_top_out[11] 0.0004829409 +1 sb_0__1_:chany_bottom_in[11] 0.0004829409 +2 cby_0__1_:chany_top_out[11] cby_0__1_:chany_top_out[17] 0.0001289588 +3 sb_0__1_:chany_bottom_in[11] sb_0__1_:chany_bottom_in[17] 0.0001289588 + +*RES +0 cby_0__1_:chany_top_out[11] sb_0__1_:chany_bottom_in[11] 0.009839286 + +*END + +*D_NET cby_0__1__0_chany_top_out[15] 0.001293099 //LENGTH 11.020 LUMPCC 0.0005139186 DR + +*CONN +*I cby_0__1_:chany_top_out[15] O *L 0 *C 333.500 516.730 +*I sb_0__1_:chany_bottom_in[15] I *L 0 *C 333.500 527.750 + +*CAP +0 cby_0__1_:chany_top_out[15] 0.0003895902 +1 sb_0__1_:chany_bottom_in[15] 0.0003895902 +2 cby_0__1_:chany_top_out[15] cby_0__1_:chany_top_in[5] 0.0001284796 +3 sb_0__1_:chany_bottom_in[15] sb_0__1_:chany_bottom_out[5] 0.0001284796 +4 cby_0__1_:chany_top_out[15] cby_0__1_:chany_top_in[17] 0.0001284796 +5 sb_0__1_:chany_bottom_in[15] sb_0__1_:chany_bottom_out[17] 0.0001284796 + +*RES +0 cby_0__1_:chany_top_out[15] sb_0__1_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET cby_0__1__0_right_grid_pin_52_[0] 0.001103203 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_0__1_:right_grid_pin_52_[0] O *L 0 *C 371.530 486.880 +*I grid_clb_1__1_:left_width_0_height_0__pin_52_[0] I *L 0 *C 379.190 486.880 + +*CAP +0 cby_0__1_:right_grid_pin_52_[0] 0.0005516013 +1 grid_clb_1__1_:left_width_0_height_0__pin_52_[0] 0.0005516013 + +*RES +0 cby_0__1_:right_grid_pin_52_[0] grid_clb_1__1_:left_width_0_height_0__pin_52_[0] 0.001200067 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[1] 0.001187226 //LENGTH 11.020 LUMPCC 0.000275843 DR + +*CONN +*I cby_0__2_:chany_bottom_out[1] O *L 0 *C 349.140 669.190 +*I sb_0__1_:chany_top_in[1] I *L 0 *C 349.140 658.170 +*N cby_0__1__1_chany_bottom_out[1]:2 *C 349.140 667.519 +*N cby_0__1__1_chany_bottom_out[1]:3 *C 349.140 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[1] 0.0001189035 +1 sb_0__1_:chany_top_in[1] 0.0003367878 +2 cby_0__1__1_chany_bottom_out[1]:2 0.0003367878 +3 cby_0__1__1_chany_bottom_out[1]:3 0.0001189035 +4 cby_0__2_:chany_bottom_out[1] cby_0__2_:chany_bottom_out[8] 7.180468e-06 +5 sb_0__1_:chany_top_in[1] sb_0__1_:chany_top_in[8] 0.0001307411 +6 cby_0__1__1_chany_bottom_out[1]:3 cby_0__1__1_chany_bottom_out[8]:3 7.180468e-06 +7 cby_0__1__1_chany_bottom_out[1]:2 cby_0__1__1_chany_bottom_out[8]:2 0.0001307411 + +*RES +0 cby_0__2_:chany_bottom_out[1] cby_0__1__1_chany_bottom_out[1]:3 0.001491071 +1 cby_0__1__1_chany_bottom_out[1]:3 cby_0__1__1_chany_bottom_out[1]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[1]:2 sb_0__1_:chany_top_in[1] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[6] 0.001259526 //LENGTH 11.020 LUMPCC 0.0005594804 DR + +*CONN +*I cby_0__2_:chany_bottom_out[6] O *L 0 *C 356.500 669.190 +*I sb_0__1_:chany_top_in[6] I *L 0 *C 356.500 658.170 +*N cby_0__1__1_chany_bottom_out[6]:2 *C 356.500 667.519 +*N cby_0__1__1_chany_bottom_out[6]:3 *C 356.500 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[6] 0.0001113406 +1 sb_0__1_:chany_top_in[6] 0.0002386824 +2 cby_0__1__1_chany_bottom_out[6]:2 0.0002386824 +3 cby_0__1__1_chany_bottom_out[6]:3 0.0001113406 +4 cby_0__2_:chany_bottom_out[6] cby_0__2_:chany_bottom_out[2] 7.234533e-06 +5 sb_0__1_:chany_top_in[6] sb_0__1_:chany_top_in[2] 0.0001326356 +6 cby_0__1__1_chany_bottom_out[6]:3 cby_0__1__1_chany_bottom_out[2]:3 7.234533e-06 +7 cby_0__1__1_chany_bottom_out[6]:2 cby_0__1__1_chany_bottom_out[2]:2 0.0001326356 +8 cby_0__2_:chany_bottom_out[6] cby_0__2_:chany_bottom_out[7] 7.234533e-06 +9 sb_0__1_:chany_top_in[6] sb_0__1_:chany_top_in[7] 0.0001326356 +10 cby_0__1__1_chany_bottom_out[6]:3 cby_0__1__1_chany_bottom_out[7]:3 7.234533e-06 +11 cby_0__1__1_chany_bottom_out[6]:2 cby_0__1__1_chany_bottom_out[7]:2 0.0001326356 + +*RES +0 cby_0__2_:chany_bottom_out[6] cby_0__1__1_chany_bottom_out[6]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[6]:3 cby_0__1__1_chany_bottom_out[6]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[6]:2 sb_0__1_:chany_top_in[6] 0.008347321 + +*END + +*D_NET cby_0__1__1_chany_bottom_out[12] 0.001167444 //LENGTH 11.020 LUMPCC 0.0002797402 DR + +*CONN +*I cby_0__2_:chany_bottom_out[12] O *L 0 *C 359.260 669.190 +*I sb_0__1_:chany_top_in[12] I *L 0 *C 359.260 658.170 +*N cby_0__1__1_chany_bottom_out[12]:2 *C 359.260 667.519 +*N cby_0__1__1_chany_bottom_out[12]:3 *C 359.260 667.520 + +*CAP +0 cby_0__2_:chany_bottom_out[12] 0.0001187175 +1 sb_0__1_:chany_top_in[12] 0.0003251345 +2 cby_0__1__1_chany_bottom_out[12]:2 0.0003251345 +3 cby_0__1__1_chany_bottom_out[12]:3 0.0001187175 +4 cby_0__2_:chany_bottom_out[12] cby_0__2_:chany_bottom_in[2] 7.234533e-06 +5 sb_0__1_:chany_top_in[12] sb_0__1_:chany_top_out[2] 0.0001326356 +6 cby_0__1__1_chany_bottom_out[12]:3 sb_0__1__0_chany_top_out[2]:2 7.234533e-06 +7 cby_0__1__1_chany_bottom_out[12]:2 sb_0__1__0_chany_top_out[2]:3 0.0001326356 + +*RES +0 cby_0__2_:chany_bottom_out[12] cby_0__1__1_chany_bottom_out[12]:3 0.001491072 +1 cby_0__1__1_chany_bottom_out[12]:3 cby_0__1__1_chany_bottom_out[12]:2 1e-05 +2 cby_0__1__1_chany_bottom_out[12]:2 sb_0__1_:chany_top_in[12] 0.008347322 + +*END + +*D_NET cby_0__1__1_chany_top_out[1] 0.001184775 //LENGTH 11.020 LUMPCC 0.0002743332 DR + +*CONN +*I cby_0__2_:chany_top_out[1] O *L 0 *C 301.760 777.850 +*I sb_0__2_:chany_bottom_in[1] I *L 0 *C 301.760 788.870 + +*CAP +0 cby_0__2_:chany_top_out[1] 0.0004552209 +1 sb_0__2_:chany_bottom_in[1] 0.0004552209 +2 cby_0__2_:chany_top_out[1] cby_0__2_:chany_top_out[3] 0.0001371666 +3 sb_0__2_:chany_bottom_in[1] sb_0__2_:chany_bottom_in[3] 0.0001371666 + +*RES +0 cby_0__2_:chany_top_out[1] sb_0__2_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_0__1__1_chany_top_out[7] 0.00117936 //LENGTH 11.020 LUMPCC 0.0002810612 DR + +*CONN +*I cby_0__2_:chany_top_out[7] O *L 0 *C 309.120 777.850 +*I sb_0__2_:chany_bottom_in[7] I *L 0 *C 309.120 788.870 + +*CAP +0 cby_0__2_:chany_top_out[7] 0.0004491495 +1 sb_0__2_:chany_bottom_in[7] 0.0004491495 +2 cby_0__2_:chany_top_out[7] cby_0__2_:chany_top_out[9] 0.0001405306 +3 sb_0__2_:chany_bottom_in[7] sb_0__2_:chany_bottom_in[9] 0.0001405306 + +*RES +0 cby_0__2_:chany_top_out[7] sb_0__2_:chany_bottom_in[7] 0.009839285 + +*END + +*D_NET cby_0__1__1_chany_top_out[13] 0.001248145 //LENGTH 11.020 LUMPCC 0.000567548 DR + +*CONN +*I cby_0__2_:chany_top_out[13] O *L 0 *C 359.260 777.850 +*I sb_0__2_:chany_bottom_in[13] I *L 0 *C 359.260 788.870 + +*CAP +0 cby_0__2_:chany_top_out[13] 0.0003402984 +1 sb_0__2_:chany_bottom_in[13] 0.0003402984 +2 cby_0__2_:chany_top_out[13] cby_0__2_:chany_top_out[2] 0.0001397368 +3 sb_0__2_:chany_bottom_in[13] sb_0__2_:chany_bottom_in[2] 0.0001397368 +4 cby_0__2_:chany_top_out[13] cby_0__2_:chany_top_out[4] 0.0001440372 +5 sb_0__2_:chany_bottom_in[13] sb_0__2_:chany_bottom_in[4] 0.0001440372 + +*RES +0 cby_0__2_:chany_top_out[13] sb_0__2_:chany_bottom_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__0_ccff_tail[0] 0.001018684 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_1__1_:ccff_tail[0] O *L 0 *C 632.810 507.280 +*I grid_clb_2__1_:ccff_head[0] I *L 0 *C 640.470 507.280 + +*CAP +0 cby_1__1_:ccff_tail[0] 0.0005093418 +1 grid_clb_2__1_:ccff_head[0] 0.0005093418 + +*RES +0 cby_1__1_:ccff_tail[0] grid_clb_2__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[3] 0.001237409 //LENGTH 11.020 LUMPCC 0.000580085 DR + +*CONN +*I cby_1__1_:chany_bottom_out[3] O *L 0 *C 593.860 408.070 +*I sb_1__0_:chany_top_in[3] I *L 0 *C 593.860 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[3] 0.000328662 +1 sb_1__0_:chany_top_in[3] 0.000328662 +2 cby_1__1_:chany_bottom_out[3] cby_1__1_:chany_bottom_out[6] 0.0001450212 +3 sb_1__0_:chany_top_in[3] sb_1__0_:chany_top_in[6] 0.0001450212 +4 cby_1__1_:chany_bottom_out[3] cby_1__1_:chany_bottom_out[10] 0.0001450212 +5 sb_1__0_:chany_top_in[3] sb_1__0_:chany_top_in[10] 0.0001450212 + +*RES +0 cby_1__1_:chany_bottom_out[3] sb_1__0_:chany_top_in[3] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_bottom_out[12] 0.001230983 //LENGTH 11.020 LUMPCC 0.0005890562 DR + +*CONN +*I cby_1__1_:chany_bottom_out[12] O *L 0 *C 572.700 408.070 +*I sb_1__0_:chany_top_in[12] I *L 0 *C 572.700 397.050 + +*CAP +0 cby_1__1_:chany_bottom_out[12] 0.0003209633 +1 sb_1__0_:chany_top_in[12] 0.0003209633 +2 cby_1__1_:chany_bottom_out[12] cby_1__1_:chany_bottom_out[4] 0.000147264 +3 sb_1__0_:chany_top_in[12] sb_1__0_:chany_top_in[4] 0.000147264 +4 cby_1__1_:chany_bottom_out[12] cby_1__1_:chany_bottom_out[15] 0.000147264 +5 sb_1__0_:chany_top_in[12] sb_1__0_:chany_top_in[15] 0.000147264 + +*RES +0 cby_1__1_:chany_bottom_out[12] sb_1__0_:chany_top_in[12] 0.009839285 + +*END + +*D_NET cby_1__1__0_chany_top_out[0] 0.001292694 //LENGTH 11.020 LUMPCC 0.0005025816 DR + +*CONN +*I cby_1__1_:chany_top_out[0] O *L 0 *C 602.140 516.730 +*I sb_1__1_:chany_bottom_in[0] I *L 0 *C 602.140 527.750 + +*CAP +0 cby_1__1_:chany_top_out[0] 0.0003950563 +1 sb_1__1_:chany_bottom_in[0] 0.0003950563 +2 cby_1__1_:chany_top_out[0] cby_1__1_:chany_top_out[2] 0.0001256454 +3 sb_1__1_:chany_bottom_in[0] sb_1__1_:chany_bottom_in[2] 0.0001256454 +4 cby_1__1_:chany_top_out[0] cby_1__1_:chany_top_in[0] 0.0001256454 +5 sb_1__1_:chany_bottom_in[0] sb_1__1_:chany_bottom_out[0] 0.0001256454 + +*RES +0 cby_1__1_:chany_top_out[0] sb_1__1_:chany_bottom_in[0] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[6] 0.001226405 //LENGTH 11.020 LUMPCC 0.0002922946 DR + +*CONN +*I cby_1__1_:chany_top_out[6] O *L 0 *C 614.100 516.730 +*I sb_1__1_:chany_bottom_in[6] I *L 0 *C 614.100 527.750 + +*CAP +0 cby_1__1_:chany_top_out[6] 0.0004670554 +1 sb_1__1_:chany_bottom_in[6] 0.0004670554 +2 cby_1__1_:chany_top_out[6] cby_1__1_:chany_top_in[4] 2.056134e-05 +3 sb_1__1_:chany_bottom_in[6] sb_1__1_:chany_bottom_out[4] 2.056134e-05 +4 cby_1__1_:chany_top_out[6] cby_1__1_:chany_top_in[10] 0.000125586 +5 sb_1__1_:chany_bottom_in[6] sb_1__1_:chany_bottom_out[10] 0.000125586 + +*RES +0 cby_1__1_:chany_top_out[6] sb_1__1_:chany_bottom_in[6] 0.009839286 + +*END + +*D_NET cby_1__1__0_chany_top_out[14] 0.001293202 //LENGTH 11.020 LUMPCC 0.0005016136 DR + +*CONN +*I cby_1__1_:chany_top_out[14] O *L 0 *C 586.040 516.730 +*I sb_1__1_:chany_bottom_in[14] I *L 0 *C 586.040 527.750 + +*CAP +0 cby_1__1_:chany_top_out[14] 0.000395794 +1 sb_1__1_:chany_bottom_in[14] 0.000395794 +2 cby_1__1_:chany_top_out[14] cby_1__1_:chany_top_out[1] 0.0001254034 +3 sb_1__1_:chany_bottom_in[14] sb_1__1_:chany_bottom_in[1] 0.0001254034 +4 cby_1__1_:chany_top_out[14] cby_1__1_:chany_top_out[4] 0.0001254034 +5 sb_1__1_:chany_bottom_in[14] sb_1__1_:chany_bottom_in[4] 0.0001254034 + +*RES +0 cby_1__1_:chany_top_out[14] sb_1__1_:chany_bottom_in[14] 0.009839286 + +*END + +*D_NET cby_1__1__0_left_grid_pin_10_[0] 0.001442235 //LENGTH 7.660 LUMPCC 0.0005282819 DR + +*CONN +*I cby_1__1_:left_grid_pin_10_[0] O *L 0 *C 548.470 486.880 +*I grid_clb_1__1_:right_width_0_height_0__pin_10_[0] I *L 0 *C 540.810 486.880 + +*CAP +0 cby_1__1_:left_grid_pin_10_[0] 0.0004569766 +1 grid_clb_1__1_:right_width_0_height_0__pin_10_[0] 0.0004569766 +2 cby_1__1_:left_grid_pin_10_[0] cby_1__1_:left_grid_pin_11_[0] 0.0001311915 +3 grid_clb_1__1_:right_width_0_height_0__pin_10_[0] grid_clb_1__1_:right_width_0_height_0__pin_11_[0] 0.0001311915 +4 cby_1__1_:left_grid_pin_10_[0] cby_1__1_:left_grid_pin_6_[0] 0.0001329495 +5 grid_clb_1__1_:right_width_0_height_0__pin_10_[0] grid_clb_1__1_:right_width_0_height_0__pin_6_[0] 0.0001329495 + +*RES +0 cby_1__1_:left_grid_pin_10_[0] grid_clb_1__1_:right_width_0_height_0__pin_10_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_left_grid_pin_3_[0] 0.001414273 //LENGTH 7.660 LUMPCC 0.0005573063 DR + +*CONN +*I cby_1__1_:left_grid_pin_3_[0] O *L 0 *C 548.470 504.560 +*I grid_clb_1__1_:right_width_0_height_0__pin_3_[0] I *L 0 *C 540.810 504.560 + +*CAP +0 cby_1__1_:left_grid_pin_3_[0] 0.0004284833 +1 grid_clb_1__1_:right_width_0_height_0__pin_3_[0] 0.0004284833 +2 cby_1__1_:left_grid_pin_3_[0] cby_1__1_:left_grid_pin_1_[0] 0.0001393266 +3 grid_clb_1__1_:right_width_0_height_0__pin_3_[0] grid_clb_1__1_:right_width_0_height_0__pin_1_[0] 0.0001393266 +4 cby_1__1_:left_grid_pin_3_[0] cby_1__1_:left_grid_pin_2_[0] 0.0001393266 +5 grid_clb_1__1_:right_width_0_height_0__pin_3_[0] grid_clb_1__1_:right_width_0_height_0__pin_2_[0] 0.0001393266 + +*RES +0 cby_1__1_:left_grid_pin_3_[0] grid_clb_1__1_:right_width_0_height_0__pin_3_[0] 0.001200067 + +*END + +*D_NET cby_1__1__0_right_grid_pin_52_[0] 0.001032791 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I cby_1__1_:right_grid_pin_52_[0] O *L 0 *C 632.810 486.880 +*I grid_clb_2__1_:left_width_0_height_0__pin_52_[0] I *L 0 *C 640.470 486.880 + +*CAP +0 cby_1__1_:right_grid_pin_52_[0] 0.0005163957 +1 grid_clb_2__1_:left_width_0_height_0__pin_52_[0] 0.0005163957 + +*RES +0 cby_1__1_:right_grid_pin_52_[0] grid_clb_2__1_:left_width_0_height_0__pin_52_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[4] 0.001244318 //LENGTH 11.020 LUMPCC 0.000580549 DR + +*CONN +*I cby_1__2_:chany_bottom_out[4] O *L 0 *C 571.780 669.190 +*I sb_1__1_:chany_top_in[4] I *L 0 *C 571.780 658.170 +*N cby_1__1__1_chany_bottom_out[4]:2 *C 571.780 667.519 +*N cby_1__1__1_chany_bottom_out[4]:3 *C 571.780 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[4] 0.0001109373 +1 sb_1__1_:chany_top_in[4] 0.0002209471 +2 cby_1__1__1_chany_bottom_out[4]:2 0.0002209471 +3 cby_1__1__1_chany_bottom_out[4]:3 0.0001109373 +4 cby_1__2_:chany_bottom_out[4] cby_1__2_:chany_bottom_out[12] 7.340376e-06 +5 sb_1__1_:chany_top_in[4] sb_1__1_:chany_top_in[12] 0.0001377969 +6 cby_1__1__1_chany_bottom_out[4]:3 cby_1__1__1_chany_bottom_out[12]:3 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[4]:2 cby_1__1__1_chany_bottom_out[12]:2 0.0001377969 +8 cby_1__2_:chany_bottom_out[4] cby_1__2_:chany_bottom_in[15] 7.340376e-06 +9 sb_1__1_:chany_top_in[4] sb_1__1_:chany_top_out[15] 0.0001377969 +10 cby_1__1__1_chany_bottom_out[4]:3 sb_1__1__0_chany_top_out[15]:2 7.340376e-06 +11 cby_1__1__1_chany_bottom_out[4]:2 sb_1__1__0_chany_top_out[15]:3 0.0001377969 + +*RES +0 cby_1__2_:chany_bottom_out[4] cby_1__1__1_chany_bottom_out[4]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[4]:3 cby_1__1__1_chany_bottom_out[4]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[4]:2 sb_1__1_:chany_top_in[4] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_bottom_out[12] 0.001244318 //LENGTH 11.020 LUMPCC 0.000580549 DR + +*CONN +*I cby_1__2_:chany_bottom_out[12] O *L 0 *C 572.700 669.190 +*I sb_1__1_:chany_top_in[12] I *L 0 *C 572.700 658.170 +*N cby_1__1__1_chany_bottom_out[12]:2 *C 572.700 667.519 +*N cby_1__1__1_chany_bottom_out[12]:3 *C 572.700 667.520 + +*CAP +0 cby_1__2_:chany_bottom_out[12] 0.0001109373 +1 sb_1__1_:chany_top_in[12] 0.0002209471 +2 cby_1__1__1_chany_bottom_out[12]:2 0.0002209471 +3 cby_1__1__1_chany_bottom_out[12]:3 0.0001109373 +4 cby_1__2_:chany_bottom_out[12] cby_1__2_:chany_bottom_out[4] 7.340376e-06 +5 sb_1__1_:chany_top_in[12] sb_1__1_:chany_top_in[4] 0.0001377969 +6 cby_1__1__1_chany_bottom_out[12]:3 cby_1__1__1_chany_bottom_out[4]:3 7.340376e-06 +7 cby_1__1__1_chany_bottom_out[12]:2 cby_1__1__1_chany_bottom_out[4]:2 0.0001377969 +8 cby_1__2_:chany_bottom_out[12] cby_1__2_:chany_bottom_out[15] 7.340376e-06 +9 sb_1__1_:chany_top_in[12] sb_1__1_:chany_top_in[15] 0.0001377969 +10 cby_1__1__1_chany_bottom_out[12]:3 cby_1__1__1_chany_bottom_out[15]:3 7.340376e-06 +11 cby_1__1__1_chany_bottom_out[12]:2 cby_1__1__1_chany_bottom_out[15]:2 0.0001377969 + +*RES +0 cby_1__2_:chany_bottom_out[12] cby_1__1__1_chany_bottom_out[12]:3 0.001491072 +1 cby_1__1__1_chany_bottom_out[12]:3 cby_1__1__1_chany_bottom_out[12]:2 1e-05 +2 cby_1__1__1_chany_bottom_out[12]:2 sb_1__1_:chany_top_in[12] 0.008347321 + +*END + +*D_NET cby_1__1__1_chany_top_out[2] 0.001275946 //LENGTH 11.020 LUMPCC 0.0005338191 DR + +*CONN +*I cby_1__2_:chany_top_out[2] O *L 0 *C 601.220 777.850 +*I sb_1__2_:chany_bottom_in[2] I *L 0 *C 601.220 788.870 + +*CAP +0 cby_1__2_:chany_top_out[2] 0.0003710636 +1 sb_1__2_:chany_bottom_in[2] 0.0003710636 +2 cby_1__2_:chany_top_out[2] cby_1__2_:chany_top_out[0] 0.0001311946 +3 sb_1__2_:chany_bottom_in[2] sb_1__2_:chany_bottom_in[0] 0.0001311946 +4 cby_1__2_:chany_top_out[2] cby_1__2_:chany_top_in[12] 0.000135715 +5 sb_1__2_:chany_bottom_in[2] sb_1__2_:chany_bottom_out[12] 0.000135715 + +*RES +0 cby_1__2_:chany_top_out[2] sb_1__2_:chany_bottom_in[2] 0.009839286 + +*END + +*D_NET cby_1__1__1_chany_top_out[12] 0.001266064 //LENGTH 11.020 LUMPCC 0.0005404066 DR + +*CONN +*I cby_1__2_:chany_top_out[12] O *L 0 *C 599.380 777.850 +*I sb_1__2_:chany_bottom_in[12] I *L 0 *C 599.380 788.870 + +*CAP +0 cby_1__2_:chany_top_out[12] 0.0003628287 +1 sb_1__2_:chany_bottom_in[12] 0.0003628287 +2 cby_1__2_:chany_top_out[12] cby_1__2_:chany_top_out[19] 0.000135715 +3 sb_1__2_:chany_bottom_in[12] sb_1__2_:chany_bottom_in[19] 0.000135715 +4 cby_1__2_:chany_top_out[12] cby_1__2_:chany_top_in[12] 0.0001344883 +5 sb_1__2_:chany_bottom_in[12] sb_1__2_:chany_bottom_out[12] 0.0001344883 + +*RES +0 cby_1__2_:chany_top_out[12] sb_1__2_:chany_bottom_in[12] 0.009839286 + +*END + +*D_NET cby_1__1__1_left_grid_pin_0_[0] 0.001459481 //LENGTH 7.660 LUMPCC 0.0005109757 DR + +*CONN +*I cby_1__2_:left_grid_pin_0_[0] O *L 0 *C 548.470 771.120 +*I grid_clb_1__2_:right_width_0_height_0__pin_0_[0] I *L 0 *C 540.810 771.120 + +*CAP +0 cby_1__2_:left_grid_pin_0_[0] 0.0004742526 +1 grid_clb_1__2_:right_width_0_height_0__pin_0_[0] 0.0004742526 +2 cby_1__2_:left_grid_pin_0_[0] cby_1__2_:left_grid_pin_4_[0] 0.0001264095 +3 grid_clb_1__2_:right_width_0_height_0__pin_0_[0] grid_clb_1__2_:right_width_0_height_0__pin_4_[0] 0.0001264095 +4 cby_1__2_:left_grid_pin_0_[0] cby_1__2_:left_grid_pin_5_[0] 0.0001290784 +5 grid_clb_1__2_:right_width_0_height_0__pin_0_[0] grid_clb_1__2_:right_width_0_height_0__pin_5_[0] 0.0001290784 + +*RES +0 cby_1__2_:left_grid_pin_0_[0] grid_clb_1__2_:right_width_0_height_0__pin_0_[0] 0.001200067 + +*END + +*D_NET cby_1__1__1_left_grid_pin_3_[0] 0.001549206 //LENGTH 7.660 LUMPCC 0.0004177218 DR + +*CONN +*I cby_1__2_:left_grid_pin_3_[0] O *L 0 *C 548.470 765.680 +*I grid_clb_1__2_:right_width_0_height_0__pin_3_[0] I *L 0 *C 540.810 765.680 + +*CAP +0 cby_1__2_:left_grid_pin_3_[0] 0.0005657418 +1 grid_clb_1__2_:right_width_0_height_0__pin_3_[0] 0.0005657418 +2 cby_1__2_:left_grid_pin_3_[0] cby_1__2_:left_grid_pin_1_[0] 0.0001044305 +3 grid_clb_1__2_:right_width_0_height_0__pin_3_[0] grid_clb_1__2_:right_width_0_height_0__pin_1_[0] 0.0001044305 +4 cby_1__2_:left_grid_pin_3_[0] cby_1__2_:left_grid_pin_2_[0] 0.0001044305 +5 grid_clb_1__2_:right_width_0_height_0__pin_3_[0] grid_clb_1__2_:right_width_0_height_0__pin_2_[0] 0.0001044305 + +*RES +0 cby_1__2_:left_grid_pin_3_[0] grid_clb_1__2_:right_width_0_height_0__pin_3_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_ccff_tail[0] 0.001732542 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_2__1_:ccff_tail[0] O *L 0 *C 894.090 507.280 +*I grid_io_right_3__1_:ccff_head[0] I *L 0 *C 907.270 507.280 + +*CAP +0 cby_2__1_:ccff_tail[0] 0.000866271 +1 grid_io_right_3__1_:ccff_head[0] 0.000866271 + +*RES +0 cby_2__1_:ccff_tail[0] grid_io_right_3__1_:ccff_head[0] 0.002064867 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[5] 0.001231501 //LENGTH 11.020 LUMPCC 0.0005884135 DR + +*CONN +*I cby_2__1_:chany_bottom_out[5] O *L 0 *C 841.340 408.070 +*I sb_2__0_:chany_top_in[5] I *L 0 *C 841.340 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[5] 0.0003215438 +1 sb_2__0_:chany_top_in[5] 0.0003215438 +2 cby_2__1_:chany_bottom_out[5] cby_2__1_:chany_bottom_out[19] 0.0001471034 +3 sb_2__0_:chany_top_in[5] sb_2__0_:chany_top_in[19] 0.0001471034 +4 cby_2__1_:chany_bottom_out[5] cby_2__1_:chany_bottom_in[1] 0.0001471034 +5 sb_2__0_:chany_top_in[5] sb_2__0_:chany_top_out[1] 0.0001471034 + +*RES +0 cby_2__1_:chany_bottom_out[5] sb_2__0_:chany_top_in[5] 0.009839285 + +*END + +*D_NET cby_1__1__2_chany_bottom_out[13] 0.001166449 //LENGTH 11.020 LUMPCC 0.0005017929 DR + +*CONN +*I cby_2__1_:chany_bottom_out[13] O *L 0 *C 844.560 408.070 +*I sb_2__0_:chany_top_in[13] I *L 0 *C 844.560 397.050 + +*CAP +0 cby_2__1_:chany_bottom_out[13] 0.000332328 +1 sb_2__0_:chany_top_in[13] 0.000332328 +2 cby_2__1_:chany_bottom_out[13] cby_2__1_:chany_bottom_in[13] 0.0001526573 +3 sb_2__0_:chany_top_in[13] sb_2__0_:chany_top_out[13] 0.0001526573 +4 cby_2__1_:chany_bottom_out[13] cby_2__1_:chany_bottom_in[17] 9.82392e-05 +5 sb_2__0_:chany_top_in[13] sb_2__0_:chany_top_out[17] 9.82392e-05 + +*RES +0 cby_2__1_:chany_bottom_out[13] sb_2__0_:chany_top_in[13] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[1] 0.001281393 //LENGTH 11.020 LUMPCC 0.0005265397 DR + +*CONN +*I cby_2__1_:chany_top_out[1] O *L 0 *C 848.240 516.730 +*I sb_2__1_:chany_bottom_in[1] I *L 0 *C 848.240 527.750 + +*CAP +0 cby_2__1_:chany_top_out[1] 0.0003774267 +1 sb_2__1_:chany_bottom_in[1] 0.0003774267 +2 cby_2__1_:chany_top_out[1] cby_2__1_:chany_top_out[13] 0.0001316349 +3 sb_2__1_:chany_bottom_in[1] sb_2__1_:chany_bottom_in[13] 0.0001316349 +4 cby_2__1_:chany_top_out[1] cby_2__1_:chany_top_out[14] 0.0001316349 +5 sb_2__1_:chany_bottom_in[1] sb_2__1_:chany_bottom_in[14] 0.0001316349 + +*RES +0 cby_2__1_:chany_top_out[1] sb_2__1_:chany_bottom_in[1] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[8] 0.001274831 //LENGTH 11.020 LUMPCC 0.0005351064 DR + +*CONN +*I cby_2__1_:chany_top_out[8] O *L 0 *C 858.820 516.730 +*I sb_2__1_:chany_bottom_in[8] I *L 0 *C 858.820 527.750 + +*CAP +0 cby_2__1_:chany_top_out[8] 0.0003698624 +1 sb_2__1_:chany_bottom_in[8] 0.0003698624 +2 cby_2__1_:chany_top_out[8] cby_2__1_:chany_top_out[16] 0.0001337766 +3 sb_2__1_:chany_bottom_in[8] sb_2__1_:chany_bottom_in[16] 0.0001337766 +4 cby_2__1_:chany_top_out[8] cby_2__1_:chany_top_out[19] 0.0001337766 +5 sb_2__1_:chany_bottom_in[8] sb_2__1_:chany_bottom_in[19] 0.0001337766 + +*RES +0 cby_2__1_:chany_top_out[8] sb_2__1_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_1__1__2_chany_top_out[17] 0.001281393 //LENGTH 11.020 LUMPCC 0.0005265397 DR + +*CONN +*I cby_2__1_:chany_top_out[17] O *L 0 *C 851.000 516.730 +*I sb_2__1_:chany_bottom_in[17] I *L 0 *C 851.000 527.750 + +*CAP +0 cby_2__1_:chany_top_out[17] 0.0003774267 +1 sb_2__1_:chany_bottom_in[17] 0.0003774267 +2 cby_2__1_:chany_top_out[17] cby_2__1_:chany_top_in[3] 0.0001316349 +3 sb_2__1_:chany_bottom_in[17] sb_2__1_:chany_bottom_out[3] 0.0001316349 +4 cby_2__1_:chany_top_out[17] cby_2__1_:chany_top_in[19] 0.0001316349 +5 sb_2__1_:chany_bottom_in[17] sb_2__1_:chany_bottom_out[19] 0.0001316349 + +*RES +0 cby_2__1_:chany_top_out[17] sb_2__1_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_1__1__2_left_grid_pin_15_[0] 0.001070575 //LENGTH 7.660 LUMPCC 0.0003665466 DR + +*CONN +*I cby_2__1_:left_grid_pin_15_[0] O *L 0 *C 809.750 442.000 +*I grid_clb_2__1_:right_width_0_height_0__pin_15_[0] I *L 0 *C 802.090 442.000 + +*CAP +0 cby_2__1_:left_grid_pin_15_[0] 0.0003520143 +1 grid_clb_2__1_:right_width_0_height_0__pin_15_[0] 0.0003520143 +2 cby_2__1_:left_grid_pin_15_[0] cby_2__1_:left_grid_pin_12_[0] 0.0001832733 +3 grid_clb_2__1_:right_width_0_height_0__pin_15_[0] grid_clb_2__1_:right_width_0_height_0__pin_12_[0] 0.0001832733 + +*RES +0 cby_2__1_:left_grid_pin_15_[0] grid_clb_2__1_:right_width_0_height_0__pin_15_[0] 0.001200067 + +*END + +*D_NET cby_1__1__2_left_grid_pin_8_[0] 0.001083444 //LENGTH 7.660 LUMPCC 0.0003590838 DR + +*CONN +*I cby_2__1_:left_grid_pin_8_[0] O *L 0 *C 809.750 484.160 +*I grid_clb_2__1_:right_width_0_height_0__pin_8_[0] I *L 0 *C 802.090 484.160 + +*CAP +0 cby_2__1_:left_grid_pin_8_[0] 0.00036218 +1 grid_clb_2__1_:right_width_0_height_0__pin_8_[0] 0.00036218 +2 cby_2__1_:left_grid_pin_8_[0] cby_2__1_:left_grid_pin_11_[0] 0.0001795419 +3 grid_clb_2__1_:right_width_0_height_0__pin_8_[0] grid_clb_2__1_:right_width_0_height_0__pin_11_[0] 0.0001795419 + +*RES +0 cby_2__1_:left_grid_pin_8_[0] grid_clb_2__1_:right_width_0_height_0__pin_8_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[1] 0.001184321 //LENGTH 11.020 LUMPCC 0.0003386251 DR + +*CONN +*I cby_2__2_:chany_bottom_out[1] O *L 0 *C 838.580 669.190 +*I sb_2__1_:chany_top_in[1] I *L 0 *C 838.580 658.170 +*N cby_1__1__3_chany_bottom_out[1]:2 *C 838.580 667.519 +*N cby_1__1__3_chany_bottom_out[1]:3 *C 838.580 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[1] 0.0001182028 +1 sb_2__1_:chany_top_in[1] 0.0003046449 +2 cby_1__1__3_chany_bottom_out[1]:2 0.0003046449 +3 cby_1__1__3_chany_bottom_out[1]:3 0.0001182028 +4 sb_2__1_:chany_top_in[1] sb_2__1_:chany_top_in[14] 3.174563e-05 +5 cby_1__1__3_chany_bottom_out[1]:2 cby_1__1__3_chany_bottom_out[14]:2 3.174563e-05 +6 cby_2__2_:chany_bottom_out[1] cby_2__2_:chany_bottom_in[9] 7.340369e-06 +7 sb_2__1_:chany_top_in[1] sb_2__1_:chany_top_out[9] 0.0001302265 +8 cby_1__1__3_chany_bottom_out[1]:3 sb_2__1__0_chany_top_out[9]:2 7.340369e-06 +9 cby_1__1__3_chany_bottom_out[1]:2 sb_2__1__0_chany_top_out[9]:3 0.0001302265 + +*RES +0 cby_2__2_:chany_bottom_out[1] cby_1__1__3_chany_bottom_out[1]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[1]:3 cby_1__1__3_chany_bottom_out[1]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[1]:2 sb_2__1_:chany_top_in[1] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[10] 0.001258107 //LENGTH 11.020 LUMPCC 0.0005567565 DR + +*CONN +*I cby_2__2_:chany_bottom_out[10] O *L 0 *C 854.220 669.190 +*I sb_2__1_:chany_top_in[10] I *L 0 *C 854.220 658.170 +*N cby_1__1__3_chany_bottom_out[10]:2 *C 854.220 667.519 +*N cby_1__1__3_chany_bottom_out[10]:3 *C 854.220 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[10] 0.0001109382 +1 sb_2__1_:chany_top_in[10] 0.0002397372 +2 cby_1__1__3_chany_bottom_out[10]:2 0.0002397372 +3 cby_1__1__3_chany_bottom_out[10]:3 0.0001109382 +4 cby_2__2_:chany_bottom_out[10] cby_2__2_:chany_bottom_out[3] 7.346249e-06 +5 sb_2__1_:chany_top_in[10] sb_2__1_:chany_top_in[3] 0.0001318429 +6 cby_1__1__3_chany_bottom_out[10]:3 cby_1__1__3_chany_bottom_out[3]:3 7.346249e-06 +7 cby_1__1__3_chany_bottom_out[10]:2 cby_1__1__3_chany_bottom_out[3]:2 0.0001318429 +8 cby_2__2_:chany_bottom_out[10] cby_2__2_:chany_bottom_out[8] 7.346249e-06 +9 sb_2__1_:chany_top_in[10] sb_2__1_:chany_top_in[8] 0.0001318429 +10 cby_1__1__3_chany_bottom_out[10]:3 cby_1__1__3_chany_bottom_out[8]:3 7.346249e-06 +11 cby_1__1__3_chany_bottom_out[10]:2 cby_1__1__3_chany_bottom_out[8]:2 0.0001318429 + +*RES +0 cby_2__2_:chany_bottom_out[10] cby_1__1__3_chany_bottom_out[10]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[10]:3 cby_1__1__3_chany_bottom_out[10]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[10]:2 sb_2__1_:chany_top_in[10] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[18] 0.001173738 //LENGTH 11.020 LUMPCC 0.0003747359 DR + +*CONN +*I cby_2__2_:chany_bottom_out[18] O *L 0 *C 865.720 669.190 +*I sb_2__1_:chany_top_in[18] I *L 0 *C 865.720 658.170 +*N cby_1__1__3_chany_bottom_out[18]:2 *C 865.720 667.519 +*N cby_1__1__3_chany_bottom_out[18]:3 *C 865.720 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[18] 0.0001177659 +1 sb_2__1_:chany_top_in[18] 0.0002817354 +2 cby_1__1__3_chany_bottom_out[18]:2 0.0002817354 +3 cby_1__1__3_chany_bottom_out[18]:3 0.0001177659 +4 cby_2__2_:chany_bottom_out[18] cby_2__2_:chany_bottom_in[5] 7.341718e-06 +5 sb_2__1_:chany_top_in[18] sb_2__1_:chany_top_out[5] 0.000135509 +6 cby_1__1__3_chany_bottom_out[18]:3 sb_2__1__0_chany_top_out[5]:2 7.341718e-06 +7 cby_1__1__3_chany_bottom_out[18]:2 sb_2__1__0_chany_top_out[5]:3 0.000135509 +8 sb_2__1_:chany_top_in[18] sb_2__1_:chany_top_out[16] 4.451721e-05 +9 cby_1__1__3_chany_bottom_out[18]:2 sb_2__1__0_chany_top_out[16]:3 4.451721e-05 + +*RES +0 cby_2__2_:chany_bottom_out[18] cby_1__1__3_chany_bottom_out[18]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[18]:3 cby_1__1__3_chany_bottom_out[18]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[18]:2 sb_2__1_:chany_top_in[18] 0.008347322 + +*END + +*D_NET cby_1__1__3_chany_top_out[8] 0.001251666 //LENGTH 11.020 LUMPCC 0.0005689875 DR + +*CONN +*I cby_2__2_:chany_top_out[8] O *L 0 *C 858.820 777.850 +*I sb_2__2_:chany_bottom_in[8] I *L 0 *C 858.820 788.870 + +*CAP +0 cby_2__2_:chany_top_out[8] 0.0003413391 +1 sb_2__2_:chany_bottom_in[8] 0.0003413391 +2 cby_2__2_:chany_top_out[8] cby_2__2_:chany_top_out[16] 0.0001422469 +3 sb_2__2_:chany_bottom_in[8] sb_2__2_:chany_bottom_in[16] 0.0001422469 +4 cby_2__2_:chany_top_out[8] cby_2__2_:chany_top_out[19] 0.0001422469 +5 sb_2__2_:chany_bottom_in[8] sb_2__2_:chany_bottom_in[19] 0.0001422469 + +*RES +0 cby_2__2_:chany_top_out[8] sb_2__2_:chany_bottom_in[8] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[17] 0.00126029 //LENGTH 11.020 LUMPCC 0.0005569746 DR + +*CONN +*I cby_2__2_:chany_top_out[17] O *L 0 *C 851.000 777.850 +*I sb_2__2_:chany_bottom_in[17] I *L 0 *C 851.000 788.870 + +*CAP +0 cby_2__2_:chany_top_out[17] 0.0003516579 +1 sb_2__2_:chany_bottom_in[17] 0.0003516579 +2 cby_2__2_:chany_top_out[17] cby_2__2_:chany_top_in[3] 0.0001392436 +3 sb_2__2_:chany_bottom_in[17] sb_2__2_:chany_bottom_out[3] 0.0001392436 +4 cby_2__2_:chany_top_out[17] cby_2__2_:chany_top_in[19] 0.0001392436 +5 sb_2__2_:chany_bottom_in[17] sb_2__2_:chany_bottom_out[19] 0.0001392436 + +*RES +0 cby_2__2_:chany_top_out[17] sb_2__2_:chany_bottom_in[17] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_3_[0] 0.001230035 //LENGTH 7.660 LUMPCC 0.0006965406 DR + +*CONN +*I cby_2__2_:left_grid_pin_3_[0] O *L 0 *C 809.750 765.680 +*I grid_clb_2__2_:right_width_0_height_0__pin_3_[0] I *L 0 *C 802.090 765.680 + +*CAP +0 cby_2__2_:left_grid_pin_3_[0] 0.000266747 +1 grid_clb_2__2_:right_width_0_height_0__pin_3_[0] 0.000266747 +2 cby_2__2_:left_grid_pin_3_[0] cby_2__2_:left_grid_pin_1_[0] 0.0001741351 +3 grid_clb_2__2_:right_width_0_height_0__pin_3_[0] grid_clb_2__2_:right_width_0_height_0__pin_1_[0] 0.0001741351 +4 cby_2__2_:left_grid_pin_3_[0] cby_2__2_:left_grid_pin_2_[0] 0.0001741351 +5 grid_clb_2__2_:right_width_0_height_0__pin_3_[0] grid_clb_2__2_:right_width_0_height_0__pin_2_[0] 0.0001741351 + +*RES +0 cby_2__2_:left_grid_pin_3_[0] grid_clb_2__2_:right_width_0_height_0__pin_3_[0] 0.001200067 + +*END + +*D_NET direct_interc_2_out[0] 0.0739476 //LENGTH 748.290 LUMPCC 0.009310457 DR + +*CONN +*I direct_interc_2_\/FTB_3__2:X O *L 0 *C 516.770 379.780 +*I grid_clb_2__2_:top_width_0_height_0__pin_32_[0] I *L 0 *C 776.480 805.050 +*N direct_interc_2_out[0]:2 *C 664.760 587.520 +*N direct_interc_2_out[0]:3 *C 776.480 807.783 +*N direct_interc_2_out[0]:4 *C 776.473 807.840 +*N direct_interc_2_out[0]:5 *C 738.290 807.840 +*N direct_interc_2_out[0]:6 *C 688.290 807.840 +*N direct_interc_2_out[0]:7 *C 667.520 807.840 +*N direct_interc_2_out[0]:8 *C 667.519 807.840 +*N direct_interc_2_out[0]:9 *C 638.500 807.840 +*N direct_interc_2_out[0]:10 *C 638.480 807.833 +*N direct_interc_2_out[0]:11 *C 638.480 783.595 +*N direct_interc_2_out[0]:12 *C 638.480 733.595 +*N direct_interc_2_out[0]:13 *C 638.480 683.595 +*N direct_interc_2_out[0]:14 *C 638.480 667.520 +*N direct_interc_2_out[0]:15 *C 638.480 667.519 +*N direct_interc_2_out[0]:16 *C 638.480 633.768 +*N direct_interc_2_out[0]:17 *C 638.500 633.760 +*N direct_interc_2_out[0]:18 *C 665.153 633.760 +*N direct_interc_2_out[0]:19 *C 665.160 633.702 +*N direct_interc_2_out[0]:20 *C 665.160 587.577 +*N direct_interc_2_out[0]:21 *C 665.160 587.520 +*N direct_interc_2_out[0]:22 *C 665.160 587.513 +*N direct_interc_2_out[0]:23 *C 665.160 550.128 +*N direct_interc_2_out[0]:24 *C 665.140 550.120 +*N direct_interc_2_out[0]:25 *C 635.740 550.120 +*N direct_interc_2_out[0]:26 *C 635.720 550.113 +*N direct_interc_2_out[0]:27 *C 635.720 502.395 +*N direct_interc_2_out[0]:28 *C 635.720 452.395 +*N direct_interc_2_out[0]:29 *C 635.720 443.520 +*N direct_interc_2_out[0]:30 *C 635.720 443.519 +*N direct_interc_2_out[0]:31 *C 635.720 402.567 +*N direct_interc_2_out[0]:32 *C 635.700 402.560 +*N direct_interc_2_out[0]:33 *C 594.475 402.560 +*N direct_interc_2_out[0]:34 *C 544.648 402.560 +*N direct_interc_2_out[0]:35 *C 544.640 402.502 +*N direct_interc_2_out[0]:36 *C 544.640 379.825 +*N direct_interc_2_out[0]:37 *C 544.595 379.780 +*N direct_interc_2_out[0]:38 *C 516.808 379.780 + +*CAP +0 direct_interc_2_\/FTB_3__2:X 1e-06 +1 grid_clb_2__2_:top_width_0_height_0__pin_32_[0] 0.0001828655 +2 direct_interc_2_out[0]:2 4.330443e-05 +3 direct_interc_2_out[0]:3 0.0001828655 +4 direct_interc_2_out[0]:4 0.001443781 +5 direct_interc_2_out[0]:5 0.003269022 +6 direct_interc_2_out[0]:6 0.002625797 +7 direct_interc_2_out[0]:7 0.0008005559 +8 direct_interc_2_out[0]:8 0.001031207 +9 direct_interc_2_out[0]:9 0.001031207 +10 direct_interc_2_out[0]:10 0.0008987418 +11 direct_interc_2_out[0]:11 0.003073443 +12 direct_interc_2_out[0]:12 0.004267163 +13 direct_interc_2_out[0]:13 0.002760315 +14 direct_interc_2_out[0]:14 0.000667853 +15 direct_interc_2_out[0]:15 0.001505929 +16 direct_interc_2_out[0]:16 0.001505929 +17 direct_interc_2_out[0]:17 0.001255321 +18 direct_interc_2_out[0]:18 0.001255321 +19 direct_interc_2_out[0]:19 0.002216199 +20 direct_interc_2_out[0]:20 0.002216199 +21 direct_interc_2_out[0]:21 4.330443e-05 +22 direct_interc_2_out[0]:22 0.002056948 +23 direct_interc_2_out[0]:23 0.002056948 +24 direct_interc_2_out[0]:24 0.0007413189 +25 direct_interc_2_out[0]:25 0.0007413189 +26 direct_interc_2_out[0]:26 0.002340515 +27 direct_interc_2_out[0]:27 0.0047487 +28 direct_interc_2_out[0]:28 0.002829084 +29 direct_interc_2_out[0]:29 0.0004208997 +30 direct_interc_2_out[0]:30 0.0018991 +31 direct_interc_2_out[0]:31 0.0018991 +32 direct_interc_2_out[0]:32 0.001994753 +33 direct_interc_2_out[0]:33 0.004364661 +34 direct_interc_2_out[0]:34 0.002369908 +35 direct_interc_2_out[0]:35 0.0007802523 +36 direct_interc_2_out[0]:36 0.0007802523 +37 direct_interc_2_out[0]:37 0.001168028 +38 direct_interc_2_out[0]:38 0.001168028 +39 direct_interc_2_out[0]:26 Test_en[0]:47 3.105926e-05 +40 direct_interc_2_out[0]:9 Test_en[0]:13 0.0003902735 +41 direct_interc_2_out[0]:10 Test_en[0]:12 0.0001525327 +42 direct_interc_2_out[0]:4 Test_en[0]:18 0.000488191 +43 direct_interc_2_out[0]:6 Test_en[0]:16 0.0007894946 +44 direct_interc_2_out[0]:6 Test_en[0]:17 0.0001220297 +45 direct_interc_2_out[0]:5 Test_en[0]:17 0.001074846 +46 direct_interc_2_out[0]:5 Test_en[0]:18 6.38282e-05 +47 direct_interc_2_out[0]:27 Test_en[0]:46 3.105926e-05 +48 direct_interc_2_out[0]:11 Test_en[0]:11 0.0001525327 +49 direct_interc_2_out[0]:7 Test_en[0]:15 0.0002028396 +50 direct_interc_2_out[0]:7 Test_en[0]:16 5.820147e-05 +51 direct_interc_2_out[0]:8 Test_en[0]:14 0.0003902735 +52 direct_interc_2_out[0]:25 clk[0]:41 0.0003100793 +53 direct_interc_2_out[0]:24 clk[0]:42 0.0003100793 +54 direct_interc_2_out[0]:16 clk[0]:31 2.7726e-05 +55 direct_interc_2_out[0]:13 clk[0]:28 0.0001295701 +56 direct_interc_2_out[0]:13 clk[0]:29 9.391332e-06 +57 direct_interc_2_out[0]:12 clk[0]:27 0.0001695974 +58 direct_interc_2_out[0]:12 clk[0]:28 1.942522e-05 +59 direct_interc_2_out[0]:11 clk[0]:26 7.767113e-05 +60 direct_interc_2_out[0]:11 clk[0]:27 1.003389e-05 +61 direct_interc_2_out[0]:14 clk[0]:29 3.764384e-05 +62 direct_interc_2_out[0]:15 clk[0]:30 2.7726e-05 +63 direct_interc_2_out[0]:25 cbx_1__1__1_chanx_left_out[13]:5 8.141912e-05 +64 direct_interc_2_out[0]:24 cbx_1__1__1_chanx_left_out[13]:6 8.141912e-05 +65 direct_interc_2_out[0]:23 cbx_1__1__1_chanx_left_out[13]:4 0.0001033751 +66 direct_interc_2_out[0]:22 cbx_1__1__1_chanx_left_out[13]:3 0.0001033751 +67 grid_clb_2__2_:top_width_0_height_0__pin_32_[0] grid_clb_2__2_:top_width_0_height_0__pin_33_[0] 3.124996e-06 +68 direct_interc_2_out[0]:38 direct_interc_5_out[0]:35 0.0004318054 +69 direct_interc_2_out[0]:37 direct_interc_5_out[0]:34 0.0004318054 +70 direct_interc_2_out[0]:36 direct_interc_5_out[0]:33 0.0003086128 +71 direct_interc_2_out[0]:35 direct_interc_5_out[0]:32 0.0003086128 +72 direct_interc_2_out[0]:9 direct_interc_5_out[0]:8 3.392201e-05 +73 direct_interc_2_out[0]:10 direct_interc_5_out[0]:9 3.862638e-05 +74 direct_interc_2_out[0]:3 direct_interc_5_out[0]:2 3.124996e-06 +75 direct_interc_2_out[0]:4 direct_interc_5_out[0]:3 4.625643e-05 +76 direct_interc_2_out[0]:6 direct_interc_5_out[0]:5 7.525101e-05 +77 direct_interc_2_out[0]:6 direct_interc_5_out[0]:4 1.153973e-05 +78 direct_interc_2_out[0]:5 direct_interc_5_out[0]:3 5.770687e-06 +79 direct_interc_2_out[0]:5 direct_interc_5_out[0]:4 0.0001040643 +80 direct_interc_2_out[0]:11 direct_interc_5_out[0]:10 3.862638e-05 +81 direct_interc_2_out[0]:7 direct_interc_5_out[0]:5 5.769043e-06 +82 direct_interc_2_out[0]:7 direct_interc_5_out[0]:6 1.744316e-05 +83 direct_interc_2_out[0]:8 direct_interc_5_out[0]:7 3.392201e-05 +84 direct_interc_2_out[0]:36 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:4 2.335628e-05 +85 direct_interc_2_out[0]:36 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 3.492634e-05 +86 direct_interc_2_out[0]:35 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:5 2.335628e-05 +87 direct_interc_2_out[0]:35 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 3.492634e-05 +88 direct_interc_2_out[0]:34 grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] 0.0001023637 +89 direct_interc_2_out[0]:33 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 0.0001023637 +90 direct_interc_2_out[0]:34 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:4 9.244033e-05 +91 direct_interc_2_out[0]:33 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:3 9.244033e-05 +92 direct_interc_2_out[0]:21 sb_1__1_:chanx_right_out[10] 2.388634e-05 +93 direct_interc_2_out[0]:2 sb_1__1__0_chanx_right_out[10]:3 2.388634e-05 +94 direct_interc_2_out[0]:31 ctsbuf_net_817:17 4.530455e-05 +95 direct_interc_2_out[0]:31 ctsbuf_net_817:18 3.817279e-05 +96 direct_interc_2_out[0]:26 ctsbuf_net_817:22 2.641074e-05 +97 direct_interc_2_out[0]:28 ctsbuf_net_817:21 9.504078e-05 +98 direct_interc_2_out[0]:28 ctsbuf_net_817:20 5.661887e-05 +99 direct_interc_2_out[0]:27 ctsbuf_net_817:22 7.199373e-05 +100 direct_interc_2_out[0]:27 ctsbuf_net_817:21 8.30296e-05 +101 direct_interc_2_out[0]:29 ctsbuf_net_817:20 2.304706e-05 +102 direct_interc_2_out[0]:30 ctsbuf_net_817:18 4.530455e-05 +103 direct_interc_2_out[0]:30 ctsbuf_net_817:19 3.817279e-05 +104 direct_interc_2_out[0]:25 ctsbuf_net_1928:17 0.0004447224 +105 direct_interc_2_out[0]:24 ctsbuf_net_1928:16 0.0004447224 + +*RES +0 direct_interc_2_\/FTB_3__2:X direct_interc_2_out[0]:38 0.152 +1 direct_interc_2_out[0]:38 direct_interc_2_out[0]:37 0.02481027 +2 direct_interc_2_out[0]:37 direct_interc_2_out[0]:36 0.0045 +3 direct_interc_2_out[0]:36 direct_interc_2_out[0]:35 0.02024777 +4 direct_interc_2_out[0]:35 direct_interc_2_out[0]:34 0.00341 +5 direct_interc_2_out[0]:34 direct_interc_2_out[0]:33 0.007806308 +6 direct_interc_2_out[0]:32 direct_interc_2_out[0]:31 0.00341 +7 direct_interc_2_out[0]:31 direct_interc_2_out[0]:30 0.006415735 +8 direct_interc_2_out[0]:25 direct_interc_2_out[0]:24 0.004606 +9 direct_interc_2_out[0]:26 direct_interc_2_out[0]:25 0.00341 +10 direct_interc_2_out[0]:24 direct_interc_2_out[0]:23 0.00341 +11 direct_interc_2_out[0]:23 direct_interc_2_out[0]:22 0.005856983 +12 direct_interc_2_out[0]:21 direct_interc_2_out[0]:20 0.00341 +13 direct_interc_2_out[0]:21 direct_interc_2_out[0]:2 5.69697e-05 +14 direct_interc_2_out[0]:22 direct_interc_2_out[0]:21 0.00341 +15 direct_interc_2_out[0]:20 direct_interc_2_out[0]:19 0.04118304 +16 direct_interc_2_out[0]:19 direct_interc_2_out[0]:18 0.00341 +17 direct_interc_2_out[0]:18 direct_interc_2_out[0]:17 0.004175558 +18 direct_interc_2_out[0]:17 direct_interc_2_out[0]:16 0.00341 +19 direct_interc_2_out[0]:16 direct_interc_2_out[0]:15 0.005287735 +20 direct_interc_2_out[0]:9 direct_interc_2_out[0]:8 0.00454631 +21 direct_interc_2_out[0]:10 direct_interc_2_out[0]:9 0.00341 +22 direct_interc_2_out[0]:3 grid_clb_2__2_:top_width_0_height_0__pin_32_[0] 0.002439732 +23 direct_interc_2_out[0]:4 direct_interc_2_out[0]:3 0.00341 +24 direct_interc_2_out[0]:33 direct_interc_2_out[0]:32 0.006458583 +25 direct_interc_2_out[0]:6 direct_interc_2_out[0]:5 0.007833333 +26 direct_interc_2_out[0]:5 direct_interc_2_out[0]:4 0.005981924 +27 direct_interc_2_out[0]:28 direct_interc_2_out[0]:27 0.007833333 +28 direct_interc_2_out[0]:27 direct_interc_2_out[0]:26 0.007475741 +29 direct_interc_2_out[0]:13 direct_interc_2_out[0]:12 0.007833333 +30 direct_interc_2_out[0]:12 direct_interc_2_out[0]:11 0.007833333 +31 direct_interc_2_out[0]:11 direct_interc_2_out[0]:10 0.003797208 +32 direct_interc_2_out[0]:7 direct_interc_2_out[0]:6 0.003253967 +33 direct_interc_2_out[0]:8 direct_interc_2_out[0]:7 1e-05 +34 direct_interc_2_out[0]:29 direct_interc_2_out[0]:28 0.001390417 +35 direct_interc_2_out[0]:30 direct_interc_2_out[0]:29 1e-05 +36 direct_interc_2_out[0]:14 direct_interc_2_out[0]:13 0.002518417 +37 direct_interc_2_out[0]:15 direct_interc_2_out[0]:14 1e-05 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_40_upper[0] 0.001475277 //LENGTH 7.660 LUMPCC 0.0003307406 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] O *L 0 *C 540.810 540.600 +*I sb_1__1_:bottom_left_grid_pin_40_[0] I *L 0 *C 548.470 540.600 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] 0.0005722679 +1 sb_1__1_:bottom_left_grid_pin_40_[0] 0.0005722679 +2 grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_39_upper[0] 0.0001167919 +3 sb_1__1_:bottom_left_grid_pin_40_[0] sb_1__1_:bottom_left_grid_pin_39_[0] 0.0001167919 +4 grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 4.857847e-05 +5 sb_1__1_:bottom_left_grid_pin_40_[0] sb_1__1_:bottom_left_grid_pin_41_[0] 4.857847e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] sb_1__1_:bottom_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_45_lower[0] 0.001188655 //LENGTH 11.020 LUMPCC 0.0003612627 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] O *L 0 *C 524.860 641.990 +*I sb_1__1_:left_top_grid_pin_45_[0] I *L 0 *C 524.860 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] 0.000413696 +1 sb_1__1_:left_top_grid_pin_45_[0] 0.000413696 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_42_lower[0] 4.079689e-05 +3 sb_1__1_:left_top_grid_pin_45_[0] sb_1__1_:left_top_grid_pin_42_[0] 4.079689e-05 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] grid_clb_1__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0001398345 +5 sb_1__1_:left_top_grid_pin_45_[0] sb_1__1_:left_top_grid_pin_44_[0] 0.0001398345 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_45_lower[0] sb_1__1_:left_top_grid_pin_45_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_51_[0] 0.0005063734 //LENGTH 4.195 LUMPCC 0 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_51_[0] O *L 0 *C 516.120 641.990 +*I direct_interc_3_\/FTB_4__3:A I *L 0.001746 *C 518.420 640.560 +*N grid_clb_1_bottom_width_0_height_0__pin_51_[0]:2 *C 518.383 640.560 +*N grid_clb_1_bottom_width_0_height_0__pin_51_[0]:3 *C 516.165 640.560 +*N grid_clb_1_bottom_width_0_height_0__pin_51_[0]:4 *C 516.120 640.605 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_51_[0] 0.0001075407 +1 direct_interc_3_\/FTB_4__3:A 1e-06 +2 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:2 0.000145146 +3 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:3 0.000145146 +4 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:4 0.0001075407 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_51_[0] grid_clb_1_bottom_width_0_height_0__pin_51_[0]:4 0.001236607 +1 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:2 direct_interc_3_\/FTB_4__3:A 0.152 +2 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:3 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:2 0.001979911 +3 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:4 grid_clb_1_bottom_width_0_height_0__pin_51_[0]:3 0.0045 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_36_upper[0] 0.001535269 //LENGTH 7.660 LUMPCC 0.0003153621 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] O *L 0 *C 540.810 795.600 +*I sb_1__2_:bottom_left_grid_pin_36_[0] I *L 0 *C 548.470 795.600 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] 0.0006099537 +1 sb_1__2_:bottom_left_grid_pin_36_[0] 0.0006099537 +2 grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_35_upper[0] 9.861671e-05 +3 sb_1__2_:bottom_left_grid_pin_36_[0] sb_1__2_:bottom_left_grid_pin_35_[0] 9.861671e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] grid_clb_1__2_:right_width_0_height_0__pin_38_upper[0] 5.906435e-05 +5 sb_1__2_:bottom_left_grid_pin_36_[0] sb_1__2_:bottom_left_grid_pin_38_[0] 5.906435e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_36_upper[0] sb_1__2_:bottom_left_grid_pin_36_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_44_upper[0] 0.001113349 //LENGTH 11.020 LUMPCC 0.000283941 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_44_upper[0] O *L 0 *C 659.180 380.870 +*I sb_1__0_:right_top_grid_pin_44_[0] I *L 0 *C 659.180 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_44_upper[0] 0.0004147041 +1 sb_1__0_:right_top_grid_pin_44_[0] 0.0004147041 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_44_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_42_upper[0] 0.0001419705 +3 sb_1__0_:right_top_grid_pin_44_[0] sb_1__0_:right_top_grid_pin_42_[0] 0.0001419705 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_44_upper[0] sb_1__0_:right_top_grid_pin_44_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_48_upper[0] 0.001175319 //LENGTH 11.020 LUMPCC 0.000283941 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_48_upper[0] O *L 0 *C 655.500 380.870 +*I sb_1__0_:right_top_grid_pin_48_[0] I *L 0 *C 655.500 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_48_upper[0] 0.0004456892 +1 sb_1__0_:right_top_grid_pin_48_[0] 0.0004456892 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_48_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] 0.0001419705 +3 sb_1__0_:right_top_grid_pin_48_[0] sb_1__0_:right_top_grid_pin_49_[0] 0.0001419705 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_48_upper[0] sb_1__0_:right_top_grid_pin_48_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_37_lower[0] 0.002458895 //LENGTH 22.740 LUMPCC 0.0002289444 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_37_lower[0] O *L 0 *C 802.090 408.000 +*I sb_2__0_:top_left_grid_pin_37_[0] I *L 0 *C 812.820 397.050 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 *C 812.820 398.423 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:3 *C 812.812 398.480 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:4 *C 805.940 398.480 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:5 *C 805.920 398.488 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:6 *C 805.920 407.993 +*N grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 *C 805.900 408.000 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_37_lower[0] 0.000137371 +1 sb_2__0_:top_left_grid_pin_37_[0] 0.0001005418 +2 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 0.0001005418 +3 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:3 0.000431076 +4 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:4 0.000431076 +5 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:5 0.0004459866 +6 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:6 0.0004459866 +7 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 0.000137371 +8 grid_clb_2__1_:right_width_0_height_0__pin_37_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_34_lower[0] 0.0001030099 +9 sb_2__0_:top_left_grid_pin_37_[0] sb_2__0_:top_left_grid_pin_34_[0] 1.146225e-05 +10 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:2 1.146225e-05 +11 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_2_right_width_0_height_0__pin_34_lower[0]:3 0.0001030099 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_37_lower[0] grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 0.0005968999 +1 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 sb_2__0_:top_left_grid_pin_37_[0] 0.001225446 +2 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:3 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:2 0.00341 +3 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:4 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:3 0.001076692 +4 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:5 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:4 0.00341 +5 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:6 0.00341 +6 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:6 grid_clb_2_right_width_0_height_0__pin_37_lower[0]:5 0.001489117 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_41_lower[0] 0.001051217 //LENGTH 7.660 LUMPCC 0.0003704049 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_41_lower[0] O *L 0 *C 802.090 384.200 +*I sb_2__0_:top_left_grid_pin_41_[0] I *L 0 *C 809.750 384.200 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_41_lower[0] 0.0003404059 +1 sb_2__0_:top_left_grid_pin_41_[0] 0.0003404059 +2 grid_clb_2__1_:right_width_0_height_0__pin_41_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_43_lower[0] 0.0001852024 +3 sb_2__0_:top_left_grid_pin_41_[0] sb_2__0_:left_top_grid_pin_43_[0] 0.0001852024 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_41_lower[0] sb_2__0_:top_left_grid_pin_41_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_44_upper[0] 0.001133157 //LENGTH 11.020 LUMPCC 0.0002788777 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_44_upper[0] O *L 0 *C 659.180 641.990 +*I sb_1__1_:right_top_grid_pin_44_[0] I *L 0 *C 659.180 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_44_upper[0] 0.0004271397 +1 sb_1__1_:right_top_grid_pin_44_[0] 0.0004271397 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_44_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0001394388 +3 sb_1__1_:right_top_grid_pin_44_[0] sb_1__1_:right_top_grid_pin_42_[0] 0.0001394388 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_44_upper[0] sb_1__1_:right_top_grid_pin_44_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_49_lower[0] 0.001167719 //LENGTH 11.020 LUMPCC 0.0003294807 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] O *L 0 *C 791.660 641.990 +*I sb_2__1_:left_top_grid_pin_49_[0] I *L 0 *C 791.660 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] 0.000419119 +1 sb_2__1_:left_top_grid_pin_49_[0] 0.000419119 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_42_lower[0] 2.31896e-05 +3 sb_2__1_:left_top_grid_pin_49_[0] sb_2__1_:left_top_grid_pin_42_[0] 2.31896e-05 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_48_lower[0] 0.0001415508 +5 sb_2__1_:left_top_grid_pin_49_[0] sb_2__1_:left_top_grid_pin_48_[0] 0.0001415508 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_49_lower[0] sb_2__1_:left_top_grid_pin_49_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_37_upper[0] 0.001276235 //LENGTH 7.660 LUMPCC 0.0005018613 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] O *L 0 *C 802.090 792.200 +*I sb_2__2_:bottom_left_grid_pin_37_[0] I *L 0 *C 809.750 792.200 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] 0.000387187 +1 sb_2__2_:bottom_left_grid_pin_37_[0] 0.000387187 +2 grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_38_upper[0] 0.0001611546 +3 sb_2__2_:bottom_left_grid_pin_37_[0] sb_2__2_:bottom_left_grid_pin_38_[0] 0.0001611546 +4 grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_41_upper[0] 8.977603e-05 +5 sb_2__2_:bottom_left_grid_pin_37_[0] grid_clb_3_right_width_0_height_0__pin_41_upper[0]:5 8.977603e-05 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_37_upper[0] sb_2__2_:bottom_left_grid_pin_37_[0] 0.001200067 + +*END + +*D_NET grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0] 0.002318301 //LENGTH 23.680 LUMPCC 8.490942e-05 DR + +*CONN +*I grid_io_bottom_1__0_:top_width_0_height_0__pin_1_lower[0] O *L 0 *C 510.140 282.810 +*I sb_1__0_:left_bottom_grid_pin_1_[0] I *L 0 *C 522.100 293.830 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:2 *C 522.100 289.058 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 *C 522.092 289.000 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 *C 510.148 289.000 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:5 *C 510.140 288.942 + +*CAP +0 grid_io_bottom_1__0_:top_width_0_height_0__pin_1_lower[0] 0.0003039741 +1 sb_1__0_:left_bottom_grid_pin_1_[0] 0.0002702125 +2 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:2 0.0002702125 +3 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 0.0005425092 +4 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 0.0005425092 +5 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:5 0.0003039741 +6 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 cbx_1__0__0_chanx_right_out[17]:5 4.245471e-05 +7 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 cbx_1__0__0_chanx_right_out[17]:6 4.245471e-05 + +*RES +0 grid_io_bottom_1__0_:top_width_0_height_0__pin_1_lower[0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:5 0.005475447 +1 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:2 sb_1__0_:left_bottom_grid_pin_1_[0] 0.004261161 +2 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:5 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:4 grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]:3 0.001871383 + +*END + +*D_NET grid_io_left_1_right_width_0_height_0__pin_1_lower[0] 0.002792438 //LENGTH 29.200 LUMPCC 9.82652e-05 DR + +*CONN +*I grid_io_left_0__2_:right_width_0_height_0__pin_1_lower[0] O *L 0 *C 271.860 669.190 +*I sb_0__1_:top_left_grid_pin_1_[0] I *L 0 *C 289.340 658.170 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:2 *C 289.340 667.023 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 *C 289.333 667.080 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 *C 271.868 667.080 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:5 *C 271.860 667.138 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:6 *C 271.860 667.519 +*N grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:7 *C 271.860 667.520 + +*CAP +0 grid_io_left_0__2_:right_width_0_height_0__pin_1_lower[0] 0.0001258078 +1 sb_0__1_:top_left_grid_pin_1_[0] 0.0003955569 +2 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:2 0.0003955569 +3 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 0.0007966934 +4 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 0.0007966933 +5 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:5 2.902862e-05 +6 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:6 2.902862e-05 +7 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:7 0.0001258078 +8 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 ctsbuf_net_2130:82 8.736921e-06 +9 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 ctsbuf_net_2130:51 4.039568e-05 +10 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 ctsbuf_net_2130:82 4.039568e-05 +11 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 ctsbuf_net_2130:83 8.736921e-06 + +*RES +0 grid_io_left_0__2_:right_width_0_height_0__pin_1_lower[0] grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:7 0.001491071 +1 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:2 sb_0__1_:top_left_grid_pin_1_[0] 0.007904018 +2 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:5 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:4 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:3 0.002736183 +5 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:7 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:6 1e-05 +6 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:6 grid_io_left_1_right_width_0_height_0__pin_1_lower[0]:5 0.000340625 + +*END + +*D_NET grid_io_top_0_ccff_tail[0] 0.001477908 //LENGTH 13.365 LUMPCC 0.0005147847 DR + +*CONN +*I grid_io_top_1__3_:ccff_tail[0] O *L 0 *C 407.710 911.200 +*I ropt_h_inst_7755:A I *L 0.001746 *C 396.520 912.560 +*N grid_io_top_0_ccff_tail[0]:2 *C 396.558 912.560 +*N grid_io_top_0_ccff_tail[0]:3 *C 397.855 912.560 +*N grid_io_top_0_ccff_tail[0]:4 *C 397.900 912.515 +*N grid_io_top_0_ccff_tail[0]:5 *C 397.900 911.258 +*N grid_io_top_0_ccff_tail[0]:6 *C 397.908 911.200 + +*CAP +0 grid_io_top_1__3_:ccff_tail[0] 0.0003167825 +1 ropt_h_inst_7755:A 1e-06 +2 grid_io_top_0_ccff_tail[0]:2 8.400634e-05 +3 grid_io_top_0_ccff_tail[0]:3 8.400634e-05 +4 grid_io_top_0_ccff_tail[0]:4 8.027257e-05 +5 grid_io_top_0_ccff_tail[0]:5 8.027257e-05 +6 grid_io_top_0_ccff_tail[0]:6 0.0003167825 +7 grid_io_top_1__3_:ccff_tail[0] grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] 0.0002573924 +8 grid_io_top_0_ccff_tail[0]:6 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 0.0002573924 + +*RES +0 grid_io_top_1__3_:ccff_tail[0] grid_io_top_0_ccff_tail[0]:6 0.001535725 +1 grid_io_top_0_ccff_tail[0]:5 grid_io_top_0_ccff_tail[0]:4 0.001122768 +2 grid_io_top_0_ccff_tail[0]:6 grid_io_top_0_ccff_tail[0]:5 0.00341 +3 grid_io_top_0_ccff_tail[0]:3 grid_io_top_0_ccff_tail[0]:2 0.001158482 +4 grid_io_top_0_ccff_tail[0]:4 grid_io_top_0_ccff_tail[0]:3 0.0045 +5 grid_io_top_0_ccff_tail[0]:2 ropt_h_inst_7755:A 0.152 + +*END + +*D_NET sb_0__0__0_chanx_right_out[6] 0.001159308 //LENGTH 7.660 LUMPCC 0.0004941499 DR + +*CONN +*I sb_0__0_:chanx_right_out[6] O *L 0 *C 400.050 322.320 +*I cbx_1__0_:chanx_left_in[6] I *L 0 *C 407.710 322.320 + +*CAP +0 sb_0__0_:chanx_right_out[6] 0.0003325791 +1 cbx_1__0_:chanx_left_in[6] 0.0003325791 +2 sb_0__0_:chanx_right_out[6] sb_0__0_:chanx_right_in[10] 7.461307e-05 +3 cbx_1__0_:chanx_left_in[6] cbx_1__0_:chanx_left_out[10] 7.461307e-05 +4 sb_0__0_:chanx_right_out[6] sb_0__0_:chanx_right_in[11] 0.0001724619 +5 cbx_1__0_:chanx_left_in[6] cbx_1__0_:chanx_left_out[11] 0.0001724619 + +*RES +0 sb_0__0_:chanx_right_out[6] cbx_1__0_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[16] 0.001168178 //LENGTH 7.660 LUMPCC 0.0005117891 DR + +*CONN +*I sb_0__0_:chanx_right_out[16] O *L 0 *C 400.050 330.480 +*I cbx_1__0_:chanx_left_in[16] I *L 0 *C 407.710 330.480 + +*CAP +0 sb_0__0_:chanx_right_out[16] 0.0003281944 +1 cbx_1__0_:chanx_left_in[16] 0.0003281944 +2 sb_0__0_:chanx_right_out[16] sb_0__0_:chanx_right_out[4] 0.0001764373 +3 cbx_1__0_:chanx_left_in[16] cbx_1__0_:chanx_left_in[4] 0.0001764373 +4 sb_0__0_:chanx_right_out[16] sb_0__0_:chanx_right_out[15] 7.945725e-05 +5 cbx_1__0_:chanx_left_in[16] cbx_1__0_:chanx_left_in[15] 7.945725e-05 + +*RES +0 sb_0__0_:chanx_right_out[16] cbx_1__0_:chanx_left_in[16] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[5] 0.001241236 //LENGTH 11.020 LUMPCC 0.0006079337 DR + +*CONN +*I sb_0__0_:chany_top_out[5] O *L 0 *C 331.660 397.050 +*I cby_0__1_:chany_bottom_in[5] I *L 0 *C 331.660 408.070 + +*CAP +0 sb_0__0_:chany_top_out[5] 0.0003166511 +1 cby_0__1_:chany_bottom_in[5] 0.0003166511 +2 sb_0__0_:chany_top_out[5] sb_0__0_:chany_top_in[3] 0.0001481706 +3 cby_0__1_:chany_bottom_in[5] cby_0__1_:chany_bottom_out[3] 0.0001481706 +4 sb_0__0_:chany_top_out[5] sb_0__0_:chany_top_in[4] 0.0001557963 +5 cby_0__1_:chany_bottom_in[5] cby_0__1_:chany_bottom_out[4] 0.0001557963 + +*RES +0 sb_0__0_:chany_top_out[5] cby_0__1_:chany_bottom_in[5] 0.009839285 + +*END + +*D_NET sb_0__0__0_chany_top_out[19] 0.001509694 //LENGTH 11.180 LUMPCC 0.0006530192 DR + +*CONN +*I sb_0__0_:chany_top_out[19] O *L 0 *C 312.800 396.970 +*I cby_0__1_:chany_bottom_in[19] I *L 0 *C 312.800 408.150 + +*CAP +0 sb_0__0_:chany_top_out[19] 0.0004283372 +1 cby_0__1_:chany_bottom_in[19] 0.0004283372 +2 sb_0__0_:chany_top_out[19] sb_0__0_:chany_top_in[5] 3.219911e-05 +3 cby_0__1_:chany_bottom_in[19] cby_0__1_:chany_bottom_out[5] 3.219911e-05 +4 sb_0__0_:chany_top_out[19] sb_0__0_:chany_top_out[1] 6.58384e-05 +5 cby_0__1_:chany_bottom_in[19] cby_0__1_:chany_bottom_in[1] 6.58384e-05 +6 sb_0__0_:chany_top_out[19] sb_0__0_:chany_top_out[13] 0.0002284721 +7 cby_0__1_:chany_bottom_in[19] cby_0__1_:chany_bottom_in[13] 0.0002284721 + +*RES +0 sb_0__0_:chany_top_out[19] cby_0__1_:chany_bottom_in[19] 0.001751533 + +*END + +*D_NET sb_0__1__0_chanx_right_out[11] 0.001264763 //LENGTH 7.660 LUMPCC 0.0006773915 DR + +*CONN +*I sb_0__1_:chanx_right_out[11] O *L 0 *C 400.050 606.560 +*I cbx_1__1_:chanx_left_in[11] I *L 0 *C 407.710 606.560 + +*CAP +0 sb_0__1_:chanx_right_out[11] 0.0002936858 +1 cbx_1__1_:chanx_left_in[11] 0.0002936858 +2 sb_0__1_:chanx_right_out[11] sb_0__1_:chanx_right_in[6] 0.0001693479 +3 cbx_1__1_:chanx_left_in[11] cbx_1__1_:chanx_left_out[6] 0.0001693479 +4 sb_0__1_:chanx_right_out[11] sb_0__1_:chanx_right_out[4] 0.0001693479 +5 cbx_1__1_:chanx_left_in[11] cbx_1__1_:chanx_left_in[4] 0.0001693479 + +*RES +0 sb_0__1_:chanx_right_out[11] cbx_1__1_:chanx_left_in[11] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[1] 0.001155368 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I sb_0__1_:chany_bottom_out[1] O *L 0 *C 321.540 527.750 +*I cby_0__1_:chany_top_in[1] I *L 0 *C 321.540 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[1] 0.0005776841 +1 cby_0__1_:chany_top_in[1] 0.0005776841 + +*RES +0 sb_0__1_:chany_bottom_out[1] cby_0__1_:chany_top_in[1] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[7] 0.001286253 //LENGTH 11.020 LUMPCC 0.0005169292 DR + +*CONN +*I sb_0__1_:chany_bottom_out[7] O *L 0 *C 355.580 527.750 +*I cby_0__1_:chany_top_in[7] I *L 0 *C 355.580 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[7] 0.000384662 +1 cby_0__1_:chany_top_in[7] 0.000384662 +2 sb_0__1_:chany_bottom_out[7] sb_0__1_:chany_bottom_out[8] 0.0001292323 +3 cby_0__1_:chany_top_in[7] cby_0__1_:chany_top_in[8] 0.0001292323 +4 sb_0__1_:chany_bottom_out[7] sb_0__1_:chany_bottom_out[12] 0.0001292323 +5 cby_0__1_:chany_top_in[7] cby_0__1_:chany_top_in[12] 0.0001292323 + +*RES +0 sb_0__1_:chany_bottom_out[7] cby_0__1_:chany_top_in[7] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[19] 0.001645666 //LENGTH 11.180 LUMPCC 0.0002091652 DR + +*CONN +*I sb_0__1_:chany_bottom_out[19] O *L 0 *C 312.800 527.830 +*I cby_0__1_:chany_top_in[19] I *L 0 *C 312.800 516.650 + +*CAP +0 sb_0__1_:chany_bottom_out[19] 0.0007182505 +1 cby_0__1_:chany_top_in[19] 0.0007182505 +2 sb_0__1_:chany_bottom_out[19] sb_0__1_:chany_bottom_out[18] 0.0001045826 +3 cby_0__1_:chany_top_in[19] cby_0__1_:chany_top_in[18] 0.0001045826 + +*RES +0 sb_0__1_:chany_bottom_out[19] cby_0__1_:chany_top_in[19] 0.001751533 + +*END + +*D_NET sb_0__1__0_chany_top_out[7] 0.001429221 //LENGTH 11.180 LUMPCC 0 DR + +*CONN +*I sb_0__1_:chany_top_out[7] O *L 0 *C 356.040 658.090 +*I cby_0__2_:chany_bottom_in[7] I *L 0 *C 356.040 669.270 +*N sb_0__1__0_chany_top_out[7]:2 *C 356.040 667.520 +*N sb_0__1__0_chany_top_out[7]:3 *C 356.040 667.519 + +*CAP +0 sb_0__1_:chany_top_out[7] 0.0004951401 +1 cby_0__2_:chany_bottom_in[7] 0.0002194702 +2 sb_0__1__0_chany_top_out[7]:2 0.0002194702 +3 sb_0__1__0_chany_top_out[7]:3 0.0004951401 + +*RES +0 sb_0__1_:chany_top_out[7] sb_0__1__0_chany_top_out[7]:3 0.00147721 +1 sb_0__1__0_chany_top_out[7]:2 cby_0__2_:chany_bottom_in[7] 0.0002741666 +2 sb_0__1__0_chany_top_out[7]:3 sb_0__1__0_chany_top_out[7]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[14] 0.001682405 //LENGTH 11.180 LUMPCC 0.0009445289 DR + +*CONN +*I sb_0__1_:chany_top_out[14] O *L 0 *C 294.400 658.090 +*I cby_0__2_:chany_bottom_in[14] I *L 0 *C 294.400 669.270 +*N sb_0__1__0_chany_top_out[14]:2 *C 294.400 667.520 +*N sb_0__1__0_chany_top_out[14]:3 *C 294.400 667.519 + +*CAP +0 sb_0__1_:chany_top_out[14] 0.0001514755 +1 cby_0__2_:chany_bottom_in[14] 0.0002174628 +2 sb_0__1__0_chany_top_out[14]:2 0.0002174628 +3 sb_0__1__0_chany_top_out[14]:3 0.0001514755 +4 sb_0__1_:chany_top_out[14] sb_0__1_:chany_top_out[6] 0.0002139862 +5 cby_0__2_:chany_bottom_in[14] cby_0__2_:chany_bottom_in[6] 9.448956e-06 +6 sb_0__1__0_chany_top_out[14]:2 sb_0__1__0_chany_top_out[6]:2 9.448956e-06 +7 sb_0__1__0_chany_top_out[14]:3 sb_0__1__0_chany_top_out[6]:3 0.0002139862 +8 sb_0__1_:chany_top_out[14] sb_0__1_:chany_top_out[9] 0.0002139862 +9 cby_0__2_:chany_bottom_in[14] cby_0__2_:chany_bottom_in[9] 9.448956e-06 +10 sb_0__1__0_chany_top_out[14]:2 sb_0__1__0_chany_top_out[9]:2 9.448956e-06 +11 sb_0__1__0_chany_top_out[14]:3 sb_0__1__0_chany_top_out[9]:3 0.0002139862 +12 sb_0__1_:chany_top_out[14] sb_0__1_:chany_top_out[12] 2.00682e-05 +13 sb_0__1_:chany_top_out[14] sb_0__1__0_chany_top_out[12]:6 5.325931e-06 +14 sb_0__1__0_chany_top_out[14]:3 sb_0__1__0_chany_top_out[12]:5 5.325931e-06 +15 sb_0__1__0_chany_top_out[14]:3 sb_0__1__0_chany_top_out[12]:7 2.00682e-05 + +*RES +0 sb_0__1_:chany_top_out[14] sb_0__1__0_chany_top_out[14]:3 0.00147721 +1 sb_0__1__0_chany_top_out[14]:2 cby_0__2_:chany_bottom_in[14] 0.0002741666 +2 sb_0__1__0_chany_top_out[14]:3 sb_0__1__0_chany_top_out[14]:2 1e-05 + +*END + +*D_NET sb_0__2__0_chanx_right_out[9] 0.001257739 //LENGTH 7.660 LUMPCC 0.0006024645 DR + +*CONN +*I sb_0__2_:chanx_right_out[9] O *L 0 *C 400.050 833.680 +*I cbx_1__2_:chanx_left_in[9] I *L 0 *C 407.710 833.680 + +*CAP +0 sb_0__2_:chanx_right_out[9] 0.0003276372 +1 cbx_1__2_:chanx_left_in[9] 0.0003276372 +2 sb_0__2_:chanx_right_out[9] sb_0__2_:chanx_right_in[14] 0.0001059899 +3 cbx_1__2_:chanx_left_in[9] cbx_1__2__0_chanx_left_out[14]:2 0.0001059899 +4 sb_0__2_:chanx_right_out[9] sb_0__2_:chanx_right_out[12] 2.949601e-05 +5 cbx_1__2_:chanx_left_in[9] cbx_1__2_:chanx_left_in[12] 2.949601e-05 +6 sb_0__2_:chanx_right_out[9] sb_0__2_:chanx_right_out[19] 0.0001657464 +7 cbx_1__2_:chanx_left_in[9] cbx_1__2_:chanx_left_in[19] 0.0001657464 + +*RES +0 sb_0__2_:chanx_right_out[9] cbx_1__2_:chanx_left_in[9] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[18] 0.001303339 //LENGTH 7.660 LUMPCC 0.0006531183 DR + +*CONN +*I sb_0__2_:chanx_right_out[18] O *L 0 *C 400.050 878.560 +*I cbx_1__2_:chanx_left_in[18] I *L 0 *C 407.710 878.560 + +*CAP +0 sb_0__2_:chanx_right_out[18] 0.0003251104 +1 cbx_1__2_:chanx_left_in[18] 0.0003251104 +2 sb_0__2_:chanx_right_out[18] sb_0__2_:chanx_right_out[14] 0.0001605674 +3 cbx_1__2_:chanx_left_in[18] cbx_1__2_:chanx_left_in[14] 0.0001605674 +4 sb_0__2_:chanx_right_out[18] sb_0__2_:chanx_right_out[17] 0.0001659918 +5 cbx_1__2_:chanx_left_in[18] cbx_1__2_:chanx_left_in[17] 0.0001659918 + +*RES +0 sb_0__2_:chanx_right_out[18] cbx_1__2_:chanx_left_in[18] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[7] 0.001258694 //LENGTH 11.020 LUMPCC 0.0005589473 DR + +*CONN +*I sb_0__2_:chany_bottom_out[7] O *L 0 *C 355.580 788.870 +*I cby_0__2_:chany_top_in[7] I *L 0 *C 355.580 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[7] 0.0003498734 +1 cby_0__2_:chany_top_in[7] 0.0003498734 +2 sb_0__2_:chany_bottom_out[7] sb_0__2_:chany_bottom_out[8] 0.0001397368 +3 cby_0__2_:chany_top_in[7] cby_0__2_:chany_top_in[8] 0.0001397368 +4 sb_0__2_:chany_bottom_out[7] sb_0__2_:chany_bottom_out[12] 0.0001397368 +5 cby_0__2_:chany_top_in[7] cby_0__2_:chany_top_in[12] 0.0001397368 + +*RES +0 sb_0__2_:chany_bottom_out[7] cby_0__2_:chany_top_in[7] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[15] 0.001699956 //LENGTH 11.180 LUMPCC 0.0008557967 DR + +*CONN +*I sb_0__2_:chany_bottom_out[15] O *L 0 *C 334.880 788.950 +*I cby_0__2_:chany_top_in[15] I *L 0 *C 334.880 777.770 + +*CAP +0 sb_0__2_:chany_bottom_out[15] 0.0004220795 +1 cby_0__2_:chany_top_in[15] 0.0004220795 +2 sb_0__2_:chany_bottom_out[15] sb_0__2_:chany_bottom_out[13] 0.0002139492 +3 cby_0__2_:chany_top_in[15] cby_0__2_:chany_top_in[13] 0.0002139492 +4 sb_0__2_:chany_bottom_out[15] sb_0__2_:chany_bottom_out[14] 0.0002139492 +5 cby_0__2_:chany_top_in[15] cby_0__2_:chany_top_in[14] 0.0002139492 + +*RES +0 sb_0__2_:chany_bottom_out[15] cby_0__2_:chany_top_in[15] 0.001751533 + +*END + +*D_NET sb_1__0__0_chanx_left_out[5] 0.001401758 //LENGTH 7.660 LUMPCC 0.0004972359 DR + +*CONN +*I sb_1__0_:chanx_left_out[5] O *L 0 *C 519.950 354.960 +*I cbx_1__0_:chanx_right_in[5] I *L 0 *C 512.290 354.960 + +*CAP +0 sb_1__0_:chanx_left_out[5] 0.0004522609 +1 cbx_1__0_:chanx_right_in[5] 0.0004522609 +2 sb_1__0_:chanx_left_out[5] sb_1__0_:chanx_left_in[4] 0.0001066989 +3 cbx_1__0_:chanx_right_in[5] cbx_1__0__0_chanx_right_out[4]:2 0.0001066989 +4 sb_1__0_:chanx_left_out[5] sb_1__0_:chanx_left_out[3] 0.0001419191 +5 cbx_1__0_:chanx_right_in[5] cbx_1__0_:chanx_right_in[3] 0.0001419191 + +*RES +0 sb_1__0_:chanx_left_out[5] cbx_1__0_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[14] 0.00128983 //LENGTH 7.660 LUMPCC 0.0003635947 DR + +*CONN +*I sb_1__0_:chanx_left_out[14] O *L 0 *C 519.950 311.440 +*I cbx_1__0_:chanx_right_in[14] I *L 0 *C 512.290 311.440 + +*CAP +0 sb_1__0_:chanx_left_out[14] 0.0004631178 +1 cbx_1__0_:chanx_right_in[14] 0.0004631178 +2 sb_1__0_:chanx_left_out[14] sb_1__0_:chanx_left_in[17] 6.852623e-05 +3 cbx_1__0_:chanx_right_in[14] cbx_1__0__0_chanx_right_out[17]:2 6.852623e-05 +4 sb_1__0_:chanx_left_out[14] sb_1__0_:chanx_left_out[2] 8.853238e-05 +5 cbx_1__0_:chanx_right_in[14] cbx_1__0_:chanx_right_in[2] 8.853238e-05 +6 sb_1__0_:chanx_left_out[14] sb_1__0_:chanx_left_out[10] 2.473871e-05 +7 cbx_1__0_:chanx_right_in[14] cbx_1__0_:chanx_right_in[10] 2.473871e-05 + +*RES +0 sb_1__0_:chanx_left_out[14] cbx_1__0_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[4] 0.001505794 //LENGTH 7.660 LUMPCC 0.0004900322 DR + +*CONN +*I sb_1__0_:chanx_right_out[4] O *L 0 *C 661.330 329.120 +*I cbx_2__0_:chanx_left_in[4] I *L 0 *C 668.990 329.120 +*N sb_1__0__0_chanx_right_out[4]:2 *C 667.520 329.120 +*N sb_1__0__0_chanx_right_out[4]:3 *C 667.519 329.120 + +*CAP +0 sb_1__0_:chanx_right_out[4] 0.0002878931 +1 cbx_2__0_:chanx_left_in[4] 0.0002199879 +2 sb_1__0__0_chanx_right_out[4]:2 0.0002199879 +3 sb_1__0__0_chanx_right_out[4]:3 0.0002878931 +4 sb_1__0_:chanx_right_out[4] sb_1__0_:chanx_right_out[8] 0.000122508 +5 sb_1__0__0_chanx_right_out[4]:3 sb_1__0__0_chanx_right_out[8]:3 0.000122508 +6 sb_1__0_:chanx_right_out[4] sb_1__0_:chanx_right_out[16] 0.000122508 +7 sb_1__0__0_chanx_right_out[4]:3 sb_1__0__0_chanx_right_out[16]:3 0.000122508 + +*RES +0 sb_1__0_:chanx_right_out[4] sb_1__0__0_chanx_right_out[4]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[4]:2 cbx_2__0_:chanx_left_in[4] 0.0002303 +2 sb_1__0__0_chanx_right_out[4]:3 sb_1__0__0_chanx_right_out[4]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[13] 0.001454726 //LENGTH 7.660 LUMPCC 0.0005047799 DR + +*CONN +*I sb_1__0_:chanx_right_out[13] O *L 0 *C 661.330 354.960 +*I cbx_2__0_:chanx_left_in[13] I *L 0 *C 668.990 354.960 +*N sb_1__0__0_chanx_right_out[13]:2 *C 667.520 354.960 +*N sb_1__0__0_chanx_right_out[13]:3 *C 667.519 354.960 + +*CAP +0 sb_1__0_:chanx_right_out[13] 0.0002702272 +1 cbx_2__0_:chanx_left_in[13] 0.0002047459 +2 sb_1__0__0_chanx_right_out[13]:2 0.0002047459 +3 sb_1__0__0_chanx_right_out[13]:3 0.0002702272 +4 sb_1__0_:chanx_right_out[13] sb_1__0_:chanx_right_out[0] 0.0001295192 +5 cbx_2__0_:chanx_left_in[13] sb_1__0__0_chanx_right_out[0]:7 2.32644e-06 +6 sb_1__0__0_chanx_right_out[13]:2 sb_1__0__0_chanx_right_out[0]:8 2.32644e-06 +7 sb_1__0__0_chanx_right_out[13]:3 sb_1__0__0_chanx_right_out[0]:9 0.0001295192 +8 sb_1__0_:chanx_right_out[13] sb_1__0_:chanx_right_out[17] 0.0001205442 +9 sb_1__0__0_chanx_right_out[13]:3 sb_1__0__0_chanx_right_out[17]:3 0.0001205442 + +*RES +0 sb_1__0_:chanx_right_out[13] sb_1__0__0_chanx_right_out[13]:3 0.00096961 +1 sb_1__0__0_chanx_right_out[13]:2 cbx_2__0_:chanx_left_in[13] 0.0002303 +2 sb_1__0__0_chanx_right_out[13]:3 sb_1__0__0_chanx_right_out[13]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[4] 0.001086858 //LENGTH 11.020 LUMPCC 0.0001965753 DR + +*CONN +*I sb_1__0_:chany_top_out[4] O *L 0 *C 618.700 397.050 +*I cby_1__1_:chany_bottom_in[4] I *L 0 *C 618.700 408.070 + +*CAP +0 sb_1__0_:chany_top_out[4] 0.0004451415 +1 cby_1__1_:chany_bottom_in[4] 0.0004451415 +2 sb_1__0_:chany_top_out[4] sb_1__0_:chany_top_out[14] 9.828763e-05 +3 cby_1__1_:chany_bottom_in[4] cby_1__1_:chany_bottom_in[14] 9.828763e-05 + +*RES +0 sb_1__0_:chany_top_out[4] cby_1__1_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET sb_1__0__0_chany_top_out[13] 0.001154491 //LENGTH 11.020 LUMPCC 0.0003944698 DR + +*CONN +*I sb_1__0_:chany_top_out[13] O *L 0 *C 584.200 397.050 +*I cby_1__1_:chany_bottom_in[13] I *L 0 *C 584.200 408.070 + +*CAP +0 sb_1__0_:chany_top_out[13] 0.0003800107 +1 cby_1__1_:chany_bottom_in[13] 0.0003800107 +2 sb_1__0_:chany_top_out[13] sb_1__0_:chany_top_in[7] 4.917351e-05 +3 cby_1__1_:chany_bottom_in[13] cby_1__1_:chany_bottom_out[7] 4.917351e-05 +4 sb_1__0_:chany_top_out[13] sb_1__0_:chany_top_in[13] 0.0001480614 +5 cby_1__1_:chany_bottom_in[13] cby_1__1_:chany_bottom_out[13] 0.0001480614 + +*RES +0 sb_1__0_:chany_top_out[13] cby_1__1_:chany_bottom_in[13] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[2] 0.001309324 //LENGTH 7.660 LUMPCC 0.0003841002 DR + +*CONN +*I sb_1__1_:chanx_left_out[2] O *L 0 *C 519.950 610.640 +*I cbx_1__1_:chanx_right_in[2] I *L 0 *C 512.290 610.640 + +*CAP +0 sb_1__1_:chanx_left_out[2] 0.000462612 +1 cbx_1__1_:chanx_right_in[2] 0.000462612 +2 sb_1__1_:chanx_left_out[2] sb_1__1_:chanx_left_in[4] 4.618341e-05 +3 cbx_1__1_:chanx_right_in[2] cbx_1__1_:chanx_right_out[4] 4.618341e-05 +4 sb_1__1_:chanx_left_out[2] sb_1__1_:chanx_left_out[1] 0.0001458667 +5 cbx_1__1_:chanx_right_in[2] cbx_1__1_:chanx_right_in[1] 0.0001458667 + +*RES +0 sb_1__1_:chanx_left_out[2] cbx_1__1_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[9] 0.001356997 //LENGTH 7.660 LUMPCC 0.0004287409 DR + +*CONN +*I sb_1__1_:chanx_left_out[9] O *L 0 *C 519.950 597.040 +*I cbx_1__1_:chanx_right_in[9] I *L 0 *C 512.290 597.040 + +*CAP +0 sb_1__1_:chanx_left_out[9] 0.000464128 +1 cbx_1__1_:chanx_right_in[9] 0.000464128 +2 sb_1__1_:chanx_left_out[9] sb_1__1_:chanx_left_in[18] 7.049166e-05 +3 cbx_1__1_:chanx_right_in[9] cbx_1__1__0_chanx_right_out[18]:2 7.049166e-05 +4 sb_1__1_:chanx_left_out[9] sb_1__1_:chanx_left_out[18] 0.0001438788 +5 cbx_1__1_:chanx_right_in[9] cbx_1__1_:chanx_right_in[18] 0.0001438788 + +*RES +0 sb_1__1_:chanx_left_out[9] cbx_1__1_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[19] 0.001298242 //LENGTH 7.660 LUMPCC 0.0003950258 DR + +*CONN +*I sb_1__1_:chanx_left_out[19] O *L 0 *C 519.950 618.800 +*I cbx_1__1_:chanx_right_in[19] I *L 0 *C 512.290 618.800 + +*CAP +0 sb_1__1_:chanx_left_out[19] 0.000451608 +1 cbx_1__1_:chanx_right_in[19] 0.000451608 +2 sb_1__1_:chanx_left_out[19] sb_1__1_:chanx_left_in[14] 0.0001447074 +3 cbx_1__1_:chanx_right_in[19] cbx_1__1_:chanx_right_out[14] 0.0001447074 +4 sb_1__1_:chanx_left_out[19] sb_1__1_:chanx_left_out[17] 5.280546e-05 +5 cbx_1__1_:chanx_right_in[19] cbx_1__1_:chanx_right_in[17] 5.280546e-05 + +*RES +0 sb_1__1_:chanx_left_out[19] cbx_1__1_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[9] 0.001417226 //LENGTH 7.660 LUMPCC 0.0004133475 DR + +*CONN +*I sb_1__1_:chanx_right_out[9] O *L 0 *C 661.330 591.600 +*I cbx_2__1_:chanx_left_in[9] I *L 0 *C 668.990 591.600 +*N sb_1__1__0_chanx_right_out[9]:2 *C 667.520 591.600 +*N sb_1__1__0_chanx_right_out[9]:3 *C 667.519 591.600 + +*CAP +0 sb_1__1_:chanx_right_out[9] 0.0003174784 +1 cbx_2__1_:chanx_left_in[9] 0.000184461 +2 sb_1__1__0_chanx_right_out[9]:2 0.000184461 +3 sb_1__1__0_chanx_right_out[9]:3 0.0003174784 +4 sb_1__1_:chanx_right_out[9] sb_1__1_:chanx_right_in[18] 6.794652e-05 +5 sb_1__1__0_chanx_right_out[9]:3 cbx_1__1__1_chanx_left_out[18]:2 6.794652e-05 +6 sb_1__1_:chanx_right_out[9] sb_1__1_:chanx_right_out[2] 0.0001288604 +7 cbx_2__1_:chanx_left_in[9] cbx_2__1_:chanx_left_in[2] 9.866816e-06 +8 sb_1__1__0_chanx_right_out[9]:2 sb_1__1__0_chanx_right_out[2]:2 9.866816e-06 +9 sb_1__1__0_chanx_right_out[9]:3 sb_1__1__0_chanx_right_out[2]:3 0.0001288604 + +*RES +0 sb_1__1_:chanx_right_out[9] sb_1__1__0_chanx_right_out[9]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[9]:2 cbx_2__1_:chanx_left_in[9] 0.0002303 +2 sb_1__1__0_chanx_right_out[9]:3 sb_1__1__0_chanx_right_out[9]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[18] 0.001469865 //LENGTH 7.660 LUMPCC 0.0002982102 DR + +*CONN +*I sb_1__1_:chanx_right_out[18] O *L 0 *C 661.330 580.040 +*I cbx_2__1_:chanx_left_in[18] I *L 0 *C 668.990 580.040 +*N sb_1__1__0_chanx_right_out[18]:2 *C 667.520 580.040 +*N sb_1__1__0_chanx_right_out[18]:3 *C 667.519 580.040 + +*CAP +0 sb_1__1_:chanx_right_out[18] 0.0003659285 +1 cbx_2__1_:chanx_left_in[18] 0.0002198988 +2 sb_1__1__0_chanx_right_out[18]:2 0.0002198988 +3 sb_1__1__0_chanx_right_out[18]:3 0.0003659285 +4 sb_1__1_:chanx_right_out[18] sb_1__1_:chanx_right_in[2] 3.781267e-05 +5 sb_1__1__0_chanx_right_out[18]:3 cbx_1__1__1_chanx_left_out[2]:2 3.781267e-05 +6 sb_1__1_:chanx_right_out[18] sb_1__1_:chanx_right_in[9] 0.0001112924 +7 sb_1__1__0_chanx_right_out[18]:3 cbx_1__1__1_chanx_left_out[9]:2 0.0001112924 + +*RES +0 sb_1__1_:chanx_right_out[18] sb_1__1__0_chanx_right_out[18]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[18]:2 cbx_2__1_:chanx_left_in[18] 0.0002303 +2 sb_1__1__0_chanx_right_out[18]:3 sb_1__1__0_chanx_right_out[18]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[7] 0.001295275 //LENGTH 11.020 LUMPCC 0.0004990738 DR + +*CONN +*I sb_1__1_:chany_bottom_out[7] O *L 0 *C 580.520 527.750 +*I cby_1__1_:chany_top_in[7] I *L 0 *C 580.520 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[7] 0.0003981007 +1 cby_1__1_:chany_top_in[7] 0.0003981007 +2 sb_1__1_:chany_bottom_out[7] sb_1__1_:chany_bottom_out[1] 0.0001247684 +3 cby_1__1_:chany_top_in[7] cby_1__1_:chany_top_in[1] 0.0001247684 +4 sb_1__1_:chany_bottom_out[7] sb_1__1_:chany_bottom_out[13] 0.0001247684 +5 cby_1__1_:chany_top_in[7] cby_1__1_:chany_top_in[13] 0.0001247684 + +*RES +0 sb_1__1_:chany_bottom_out[7] cby_1__1_:chany_top_in[7] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[17] 0.001270539 //LENGTH 11.020 LUMPCC 0.000389207 DR + +*CONN +*I sb_1__1_:chany_bottom_out[17] O *L 0 *C 578.680 527.750 +*I cby_1__1_:chany_top_in[17] I *L 0 *C 578.680 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[17] 0.0004406661 +1 cby_1__1_:chany_top_in[17] 0.0004406661 +2 sb_1__1_:chany_bottom_out[17] sb_1__1_:chany_bottom_in[18] 6.983505e-05 +3 cby_1__1_:chany_top_in[17] cby_1__1_:chany_top_out[18] 6.983505e-05 +4 sb_1__1_:chany_bottom_out[17] sb_1__1_:chany_bottom_out[1] 0.0001247684 +5 cby_1__1_:chany_top_in[17] cby_1__1_:chany_top_in[1] 0.0001247684 + +*RES +0 sb_1__1_:chany_bottom_out[17] cby_1__1_:chany_top_in[17] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[6] 0.001245865 //LENGTH 11.020 LUMPCC 0.0005875931 DR + +*CONN +*I sb_1__1_:chany_top_out[6] O *L 0 *C 590.180 658.170 +*I cby_1__2_:chany_bottom_in[6] I *L 0 *C 590.180 669.190 +*N sb_1__1__0_chany_top_out[6]:2 *C 590.180 667.520 +*N sb_1__1__0_chany_top_out[6]:3 *C 590.180 667.519 + +*CAP +0 sb_1__1_:chany_top_out[6] 0.0002181978 +1 cby_1__2_:chany_bottom_in[6] 0.0001109382 +2 sb_1__1__0_chany_top_out[6]:2 0.0001109382 +3 sb_1__1__0_chany_top_out[6]:3 0.0002181978 +4 sb_1__1_:chany_top_out[6] sb_1__1_:chany_top_in[16] 0.000139552 +5 cby_1__2_:chany_bottom_in[6] cby_1__2_:chany_bottom_out[16] 7.346249e-06 +6 sb_1__1__0_chany_top_out[6]:2 cby_1__1__1_chany_bottom_out[16]:3 7.346249e-06 +7 sb_1__1__0_chany_top_out[6]:3 cby_1__1__1_chany_bottom_out[16]:2 0.000139552 +8 sb_1__1_:chany_top_out[6] sb_1__1_:chany_top_out[3] 0.000139552 +9 cby_1__2_:chany_bottom_in[6] cby_1__2_:chany_bottom_in[3] 7.346249e-06 +10 sb_1__1__0_chany_top_out[6]:2 sb_1__1__0_chany_top_out[3]:2 7.346249e-06 +11 sb_1__1__0_chany_top_out[6]:3 sb_1__1__0_chany_top_out[3]:3 0.000139552 + +*RES +0 sb_1__1_:chany_top_out[6] sb_1__1__0_chany_top_out[6]:3 0.008347321 +1 sb_1__1__0_chany_top_out[6]:2 cby_1__2_:chany_bottom_in[6] 0.001491072 +2 sb_1__1__0_chany_top_out[6]:3 sb_1__1__0_chany_top_out[6]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[16] 0.00108455 //LENGTH 11.020 LUMPCC 0.0001027205 DR + +*CONN +*I sb_1__1_:chany_top_out[16] O *L 0 *C 606.740 658.170 +*I cby_1__2_:chany_bottom_in[16] I *L 0 *C 606.740 669.190 +*N sb_1__1__0_chany_top_out[16]:2 *C 606.740 667.520 +*N sb_1__1__0_chany_top_out[16]:3 *C 606.740 667.519 + +*CAP +0 sb_1__1_:chany_top_out[16] 0.0003652168 +1 cby_1__2_:chany_bottom_in[16] 0.0001256978 +2 sb_1__1__0_chany_top_out[16]:2 0.0001256978 +3 sb_1__1__0_chany_top_out[16]:3 0.0003652168 +4 sb_1__1_:chany_top_out[16] sb_1__1_:chany_top_in[18] 5.136023e-05 +5 sb_1__1__0_chany_top_out[16]:3 cby_1__1__1_chany_bottom_out[18]:2 5.136023e-05 + +*RES +0 sb_1__1_:chany_top_out[16] sb_1__1__0_chany_top_out[16]:3 0.008347322 +1 sb_1__1__0_chany_top_out[16]:2 cby_1__2_:chany_bottom_in[16] 0.001491072 +2 sb_1__1__0_chany_top_out[16]:3 sb_1__1__0_chany_top_out[16]:2 1e-05 + +*END + +*D_NET sb_1__2__0_ccff_tail[0] 0.001332813 //LENGTH 7.660 LUMPCC 0.0003788198 DR + +*CONN +*I sb_1__2_:ccff_tail[0] O *L 0 *C 519.950 866.320 +*I cbx_1__2_:ccff_head[0] I *L 0 *C 512.290 866.320 + +*CAP +0 sb_1__2_:ccff_tail[0] 0.0004769967 +1 cbx_1__2_:ccff_head[0] 0.0004769967 +2 sb_1__2_:ccff_tail[0] sb_1__2_:chanx_left_in[8] 0.0001404799 +3 cbx_1__2_:ccff_head[0] cbx_1__2_:chanx_right_out[8] 0.0001404799 +4 sb_1__2_:ccff_tail[0] sb_1__2_:chanx_left_out[0] 4.892996e-05 +5 cbx_1__2_:ccff_head[0] cbx_1__2_:chanx_right_in[0] 4.892996e-05 + +*RES +0 sb_1__2_:ccff_tail[0] cbx_1__2_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[8] 0.001299129 //LENGTH 7.660 LUMPCC 0.0003813968 DR + +*CONN +*I sb_1__2_:chanx_left_out[8] O *L 0 *C 519.950 874.480 +*I cbx_1__2_:chanx_right_in[8] I *L 0 *C 512.290 874.480 + +*CAP +0 sb_1__2_:chanx_left_out[8] 0.0004588658 +1 cbx_1__2_:chanx_right_in[8] 0.0004588658 +2 sb_1__2_:chanx_left_out[8] sb_1__2_:chanx_left_out[12] 4.688213e-05 +3 cbx_1__2_:chanx_right_in[8] cbx_1__2_:chanx_right_in[12] 4.688213e-05 +4 sb_1__2_:chanx_left_out[8] sb_1__2_:chanx_left_out[13] 0.0001438163 +5 cbx_1__2_:chanx_right_in[8] cbx_1__2_:chanx_right_in[13] 0.0001438163 + +*RES +0 sb_1__2_:chanx_left_out[8] cbx_1__2_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[17] 0.001345669 //LENGTH 7.660 LUMPCC 0.0003732805 DR + +*CONN +*I sb_1__2_:chanx_left_out[17] O *L 0 *C 519.950 879.920 +*I cbx_1__2_:chanx_right_in[17] I *L 0 *C 512.290 879.920 + +*CAP +0 sb_1__2_:chanx_left_out[17] 0.0004861941 +1 cbx_1__2_:chanx_right_in[17] 0.0004861941 +2 sb_1__2_:chanx_left_out[17] sb_1__2_:chanx_left_out[11] 0.0001410189 +3 cbx_1__2_:chanx_right_in[17] cbx_1__2_:chanx_right_in[11] 0.0001410189 +4 sb_1__2_:chanx_left_out[17] sb_1__2_:chanx_left_out[19] 4.56214e-05 +5 cbx_1__2_:chanx_right_in[17] cbx_1__2_:chanx_right_in[19] 4.56214e-05 + +*RES +0 sb_1__2_:chanx_left_out[17] cbx_1__2_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[7] 0.00148082 //LENGTH 7.660 LUMPCC 0.0003342595 DR + +*CONN +*I sb_1__2_:chanx_right_out[7] O *L 0 *C 661.330 882.640 +*I cbx_2__2_:chanx_left_in[7] I *L 0 *C 668.990 882.640 +*N sb_1__2__0_chanx_right_out[7]:2 *C 667.520 882.640 +*N sb_1__2__0_chanx_right_out[7]:3 *C 667.519 882.640 + +*CAP +0 sb_1__2_:chanx_right_out[7] 0.000355624 +1 cbx_2__2_:chanx_left_in[7] 0.0002176561 +2 sb_1__2__0_chanx_right_out[7]:2 0.0002176561 +3 sb_1__2__0_chanx_right_out[7]:3 0.000355624 +4 sb_1__2_:chanx_right_out[7] sb_1__2_:chanx_right_out[5] 0.0001141604 +5 cbx_2__2_:chanx_left_in[7] cbx_2__2_:chanx_left_in[5] 1.644281e-06 +6 sb_1__2__0_chanx_right_out[7]:2 sb_1__2__0_chanx_right_out[5]:2 1.644281e-06 +7 sb_1__2__0_chanx_right_out[7]:3 sb_1__2__0_chanx_right_out[5]:3 0.0001141604 +8 sb_1__2_:chanx_right_out[7] sb_1__2_:chanx_right_out[14] 5.132505e-05 +9 sb_1__2__0_chanx_right_out[7]:3 sb_1__2__0_chanx_right_out[14]:3 5.132505e-05 + +*RES +0 sb_1__2_:chanx_right_out[7] sb_1__2__0_chanx_right_out[7]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[7]:2 cbx_2__2_:chanx_left_in[7] 0.0002303 +2 sb_1__2__0_chanx_right_out[7]:3 sb_1__2__0_chanx_right_out[7]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[16] 0.001437813 //LENGTH 7.660 LUMPCC 0.0003665803 DR + +*CONN +*I sb_1__2_:chanx_right_out[16] O *L 0 *C 661.330 852.720 +*I cbx_2__2_:chanx_left_in[16] I *L 0 *C 668.990 852.720 +*N sb_1__2__0_chanx_right_out[16]:2 *C 667.520 852.720 +*N sb_1__2__0_chanx_right_out[16]:3 *C 667.519 852.720 + +*CAP +0 sb_1__2_:chanx_right_out[16] 0.0003155908 +1 cbx_2__2_:chanx_left_in[16] 0.0002200254 +2 sb_1__2__0_chanx_right_out[16]:2 0.0002200254 +3 sb_1__2__0_chanx_right_out[16]:3 0.0003155908 +4 sb_1__2_:chanx_right_out[16] sb_1__2_:chanx_right_in[5] 0.0001201353 +5 sb_1__2__0_chanx_right_out[16]:3 cbx_1__2__1_chanx_left_out[5]:2 0.0001201353 +6 sb_1__2_:chanx_right_out[16] sb_1__2_:chanx_right_out[13] 6.315485e-05 +7 sb_1__2__0_chanx_right_out[16]:3 sb_1__2__0_chanx_right_out[13]:3 6.315485e-05 + +*RES +0 sb_1__2_:chanx_right_out[16] sb_1__2__0_chanx_right_out[16]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[16]:2 cbx_2__2_:chanx_left_in[16] 0.0002303 +2 sb_1__2__0_chanx_right_out[16]:3 sb_1__2__0_chanx_right_out[16]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[4] 0.001337362 //LENGTH 11.020 LUMPCC 0.0004339307 DR + +*CONN +*I sb_1__2_:chany_bottom_out[4] O *L 0 *C 616.400 788.870 +*I cby_1__2_:chany_top_in[4] I *L 0 *C 616.400 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[4] 0.0004517156 +1 cby_1__2_:chany_top_in[4] 0.0004517156 +2 sb_1__2_:chany_bottom_out[4] sb_1__2_:chany_bottom_out[14] 5.599678e-05 +3 sb_1__2_:chany_bottom_out[4] sb_1__2__0_chany_bottom_out[14]:2 1.488356e-05 +4 sb_1__2_:chany_bottom_out[4] sb_1__2__0_chany_bottom_out[14]:6 0.000146085 +5 cby_1__2_:chany_top_in[4] cby_1__2_:chany_top_in[14] 1.488356e-05 +6 cby_1__2_:chany_top_in[4] sb_1__2__0_chany_bottom_out[14]:5 0.000146085 +7 cby_1__2_:chany_top_in[4] sb_1__2__0_chany_bottom_out[14]:9 5.599678e-05 + +*RES +0 sb_1__2_:chany_bottom_out[4] cby_1__2_:chany_top_in[4] 0.009839285 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[12] 0.001266064 //LENGTH 11.020 LUMPCC 0.0005404066 DR + +*CONN +*I sb_1__2_:chany_bottom_out[12] O *L 0 *C 600.300 788.870 +*I cby_1__2_:chany_top_in[12] I *L 0 *C 600.300 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[12] 0.0003628287 +1 cby_1__2_:chany_top_in[12] 0.0003628287 +2 sb_1__2_:chany_bottom_out[12] sb_1__2_:chany_bottom_in[2] 0.000135715 +3 cby_1__2_:chany_top_in[12] cby_1__2_:chany_top_out[2] 0.000135715 +4 sb_1__2_:chany_bottom_out[12] sb_1__2_:chany_bottom_in[12] 0.0001344883 +5 cby_1__2_:chany_top_in[12] cby_1__2_:chany_top_out[12] 0.0001344883 + +*RES +0 sb_1__2_:chany_bottom_out[12] cby_1__2_:chany_top_in[12] 0.009839286 + +*END + +*D_NET sb_2__0__0_ccff_tail[0] 0.001522329 //LENGTH 7.660 LUMPCC 0.0003708453 DR + +*CONN +*I sb_2__0_:ccff_tail[0] O *L 0 *C 781.230 349.520 +*I cbx_2__0_:ccff_head[0] I *L 0 *C 773.570 349.520 + +*CAP +0 sb_2__0_:ccff_tail[0] 0.0005757419 +1 cbx_2__0_:ccff_head[0] 0.0005757419 +2 sb_2__0_:ccff_tail[0] sb_2__0_:chanx_left_in[1] 0.0001147421 +3 cbx_2__0_:ccff_head[0] cbx_2__0_:chanx_right_out[1] 0.0001147421 +4 sb_2__0_:ccff_tail[0] sb_2__0_:chanx_left_in[2] 4.031344e-05 +5 cbx_2__0_:ccff_head[0] cbx_1__0__1_chanx_right_out[2]:2 4.031344e-05 +6 sb_2__0_:ccff_tail[0] sb_2__0_:chanx_left_out[19] 3.036709e-05 +7 cbx_2__0_:ccff_head[0] cbx_2__0_:chanx_right_in[19] 3.036709e-05 + +*RES +0 sb_2__0_:ccff_tail[0] cbx_2__0_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[9] 0.001416987 //LENGTH 7.660 LUMPCC 0.0003717214 DR + +*CONN +*I sb_2__0_:chanx_left_out[9] O *L 0 *C 781.230 327.760 +*I cbx_2__0_:chanx_right_in[9] I *L 0 *C 773.570 327.760 + +*CAP +0 sb_2__0_:chanx_left_out[9] 0.0005226327 +1 cbx_2__0_:chanx_right_in[9] 0.0005226327 +2 sb_2__0_:chanx_left_out[9] sb_2__0_:chanx_left_in[8] 0.0001193389 +3 cbx_2__0_:chanx_right_in[9] cbx_2__0_:chanx_right_out[8] 0.0001193389 +4 sb_2__0_:chanx_left_out[9] sb_2__0_:chanx_left_in[12] 6.652179e-05 +5 cbx_2__0_:chanx_right_in[9] cbx_2__0_:chanx_right_out[12] 6.652179e-05 + +*RES +0 sb_2__0_:chanx_left_out[9] cbx_2__0_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[17] 0.001517529 //LENGTH 7.660 LUMPCC 0.0004739902 DR + +*CONN +*I sb_2__0_:chanx_left_out[17] O *L 0 *C 781.230 337.280 +*I cbx_2__0_:chanx_right_in[17] I *L 0 *C 773.570 337.280 + +*CAP +0 sb_2__0_:chanx_left_out[17] 0.0005217694 +1 cbx_2__0_:chanx_right_in[17] 0.0005217694 +2 sb_2__0_:chanx_left_out[17] sb_2__0_:chanx_left_in[13] 0.0001178972 +3 cbx_2__0_:chanx_right_in[17] cbx_2__0_:chanx_right_out[13] 0.0001178972 +4 sb_2__0_:chanx_left_out[17] sb_2__0_:chanx_left_in[15] 0.0001190979 +5 cbx_2__0_:chanx_right_in[17] cbx_2__0_:chanx_right_out[15] 0.0001190979 + +*RES +0 sb_2__0_:chanx_left_out[17] cbx_2__0_:chanx_right_in[17] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[7] 0.00147028 //LENGTH 12.500 LUMPCC 0.0003765071 DR + +*CONN +*I sb_2__0_:chany_top_out[7] O *L 0 *C 831.220 397.050 +*I cby_2__1_:chany_bottom_in[7] I *L 0 *C 831.220 408.070 +*N sb_2__0__0_chany_top_out[7]:2 *C 831.220 405.960 +*N sb_2__0__0_chany_top_out[7]:3 *C 831.680 405.960 +*N sb_2__0__0_chany_top_out[7]:4 *C 831.680 400.860 +*N sb_2__0__0_chany_top_out[7]:5 *C 831.220 400.860 + +*CAP +0 sb_2__0_:chany_top_out[7] 0.0002067115 +1 cby_2__1_:chany_bottom_in[7] 0.0001054323 +2 sb_2__0__0_chany_top_out[7]:2 0.0001286155 +3 sb_2__0__0_chany_top_out[7]:3 0.000206764 +4 sb_2__0__0_chany_top_out[7]:4 0.0002115594 +5 sb_2__0__0_chany_top_out[7]:5 0.0002346901 +6 sb_2__0_:chany_top_out[7] sb_2__0_:chany_top_out[15] 2.585697e-05 +7 cby_2__1_:chany_bottom_in[7] cby_2__1_:chany_bottom_in[15] 1.431606e-05 +8 sb_2__0__0_chany_top_out[7]:5 cby_2__1_:chany_bottom_in[15] 2.585697e-05 +9 sb_2__0__0_chany_top_out[7]:4 sb_2__0_:chany_top_out[15] 0.0001480805 +10 sb_2__0__0_chany_top_out[7]:2 sb_2__0_:chany_top_out[15] 1.431606e-05 +11 sb_2__0__0_chany_top_out[7]:3 cby_2__1_:chany_bottom_in[15] 0.0001480805 + +*RES +0 sb_2__0_:chany_top_out[7] sb_2__0__0_chany_top_out[7]:5 0.003401786 +1 sb_2__0__0_chany_top_out[7]:5 sb_2__0__0_chany_top_out[7]:4 0.0004107143 +2 sb_2__0__0_chany_top_out[7]:4 sb_2__0__0_chany_top_out[7]:3 0.004553571 +3 sb_2__0__0_chany_top_out[7]:2 cby_2__1_:chany_bottom_in[7] 0.001883929 +4 sb_2__0__0_chany_top_out[7]:3 sb_2__0__0_chany_top_out[7]:2 0.0004107143 + +*END + +*D_NET sb_2__1__0_ccff_tail[0] 0.001497558 //LENGTH 7.660 LUMPCC 0.0002888592 DR + +*CONN +*I sb_2__1_:ccff_tail[0] O *L 0 *C 781.230 592.280 +*I cbx_2__1_:ccff_head[0] I *L 0 *C 773.570 592.280 + +*CAP +0 sb_2__1_:ccff_tail[0] 0.0006043495 +1 cbx_2__1_:ccff_head[0] 0.0006043495 +2 sb_2__1_:ccff_tail[0] sb_2__1_:chanx_left_out[0] 3.338791e-05 +3 cbx_2__1_:ccff_head[0] cbx_2__1_:chanx_right_in[0] 3.338791e-05 +4 sb_2__1_:ccff_tail[0] sb_2__1_:chanx_left_out[7] 0.0001110417 +5 cbx_2__1_:ccff_head[0] cbx_2__1_:chanx_right_in[7] 0.0001110417 + +*RES +0 sb_2__1_:ccff_tail[0] cbx_2__1_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[9] 0.001529557 //LENGTH 7.660 LUMPCC 0.000263821 DR + +*CONN +*I sb_2__1_:chanx_left_out[9] O *L 0 *C 781.230 597.040 +*I cbx_2__1_:chanx_right_in[9] I *L 0 *C 773.570 597.040 + +*CAP +0 sb_2__1_:chanx_left_out[9] 0.0006328682 +1 cbx_2__1_:chanx_right_in[9] 0.0006328682 +2 sb_2__1_:chanx_left_out[9] sb_2__1_:chanx_left_out[7] 2.857778e-05 +3 cbx_2__1_:chanx_right_in[9] cbx_2__1_:chanx_right_in[7] 2.857778e-05 +4 sb_2__1_:chanx_left_out[9] sb_2__1_:chanx_left_out[18] 0.0001033327 +5 cbx_2__1_:chanx_right_in[9] cbx_2__1_:chanx_right_in[18] 0.0001033327 + +*RES +0 sb_2__1_:chanx_left_out[9] cbx_2__1_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[3] 0.001281393 //LENGTH 11.020 LUMPCC 0.0005265397 DR + +*CONN +*I sb_2__1_:chany_bottom_out[3] O *L 0 *C 850.080 527.750 +*I cby_2__1_:chany_top_in[3] I *L 0 *C 850.080 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[3] 0.0003774267 +1 cby_2__1_:chany_top_in[3] 0.0003774267 +2 sb_2__1_:chany_bottom_out[3] sb_2__1_:chany_bottom_in[13] 0.0001316349 +3 cby_2__1_:chany_top_in[3] cby_2__1_:chany_top_out[13] 0.0001316349 +4 sb_2__1_:chany_bottom_out[3] sb_2__1_:chany_bottom_in[17] 0.0001316349 +5 cby_2__1_:chany_top_in[3] cby_2__1_:chany_top_out[17] 0.0001316349 + +*RES +0 sb_2__1_:chany_bottom_out[3] cby_2__1_:chany_top_in[3] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[13] 0.001261363 //LENGTH 11.020 LUMPCC 0.0005424088 DR + +*CONN +*I sb_2__1_:chany_bottom_out[13] O *L 0 *C 842.720 527.750 +*I cby_2__1_:chany_top_in[13] I *L 0 *C 842.720 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[13] 0.0003594771 +1 cby_2__1_:chany_top_in[13] 0.0003594771 +2 sb_2__1_:chany_bottom_out[13] sb_2__1_:chany_bottom_in[10] 0.0001377736 +3 cby_2__1_:chany_top_in[13] cby_2__1_:chany_top_out[10] 0.0001377736 +4 sb_2__1_:chany_bottom_out[13] sb_2__1_:chany_bottom_out[7] 0.0001334308 +5 cby_2__1_:chany_top_in[13] cby_2__1_:chany_top_in[7] 0.0001334308 + +*RES +0 sb_2__1_:chany_bottom_out[13] cby_2__1_:chany_top_in[13] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[1] 0.001240112 //LENGTH 11.020 LUMPCC 0.0005607925 DR + +*CONN +*I sb_2__1_:chany_top_out[1] O *L 0 *C 842.260 658.170 +*I cby_2__2_:chany_bottom_in[1] I *L 0 *C 842.260 669.190 +*N sb_2__1__0_chany_top_out[1]:2 *C 842.260 667.520 +*N sb_2__1__0_chany_top_out[1]:3 *C 842.260 667.519 + +*CAP +0 sb_2__1_:chany_top_out[1] 0.0002290978 +1 cby_2__2_:chany_bottom_in[1] 0.0001105619 +2 sb_2__1__0_chany_top_out[1]:2 0.0001105619 +3 sb_2__1__0_chany_top_out[1]:3 0.0002290978 +4 sb_2__1_:chany_top_out[1] sb_2__1_:chany_top_in[5] 0.0001302265 +5 cby_2__2_:chany_bottom_in[1] cby_2__2_:chany_bottom_out[5] 7.340369e-06 +6 sb_2__1__0_chany_top_out[1]:2 cby_1__1__3_chany_bottom_out[5]:3 7.340369e-06 +7 sb_2__1__0_chany_top_out[1]:3 cby_1__1__3_chany_bottom_out[5]:2 0.0001302265 +8 sb_2__1_:chany_top_out[1] sb_2__1_:chany_top_out[17] 0.0001353879 +9 cby_2__2_:chany_bottom_in[1] cby_2__2_:chany_bottom_in[17] 7.441422e-06 +10 sb_2__1__0_chany_top_out[1]:2 sb_2__1__0_chany_top_out[17]:2 7.441422e-06 +11 sb_2__1__0_chany_top_out[1]:3 sb_2__1__0_chany_top_out[17]:3 0.0001353879 + +*RES +0 sb_2__1_:chany_top_out[1] sb_2__1__0_chany_top_out[1]:3 0.008347321 +1 sb_2__1__0_chany_top_out[1]:2 cby_2__2_:chany_bottom_in[1] 0.001491072 +2 sb_2__1__0_chany_top_out[1]:3 sb_2__1__0_chany_top_out[1]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[13] 0.001170037 //LENGTH 11.020 LUMPCC 0.0003824555 DR + +*CONN +*I sb_2__1_:chany_top_out[13] O *L 0 *C 845.480 658.170 +*I cby_2__2_:chany_bottom_in[13] I *L 0 *C 845.480 669.190 +*N sb_2__1__0_chany_top_out[13]:2 *C 845.480 667.520 +*N sb_2__1__0_chany_top_out[13]:3 *C 845.480 667.519 + +*CAP +0 sb_2__1_:chany_top_out[13] 0.0002736528 +1 cby_2__2_:chany_bottom_in[13] 0.000120138 +2 sb_2__1__0_chany_top_out[13]:2 0.000120138 +3 sb_2__1__0_chany_top_out[13]:3 0.0002736528 +4 sb_2__1_:chany_top_out[13] sb_2__1_:chany_top_in[7] 4.839835e-05 +5 sb_2__1__0_chany_top_out[13]:3 cby_1__1__3_chany_bottom_out[7]:2 4.839835e-05 +6 sb_2__1_:chany_top_out[13] sb_2__1_:chany_top_in[13] 0.0001353879 +7 cby_2__2_:chany_bottom_in[13] cby_2__2_:chany_bottom_out[13] 7.441422e-06 +8 sb_2__1__0_chany_top_out[13]:2 cby_1__1__3_chany_bottom_out[13]:3 7.441422e-06 +9 sb_2__1__0_chany_top_out[13]:3 cby_1__1__3_chany_bottom_out[13]:2 0.0001353879 + +*RES +0 sb_2__1_:chany_top_out[13] sb_2__1__0_chany_top_out[13]:3 0.008347322 +1 sb_2__1__0_chany_top_out[13]:2 cby_2__2_:chany_bottom_in[13] 0.001491072 +2 sb_2__1__0_chany_top_out[13]:3 sb_2__1__0_chany_top_out[13]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[5] 0.001477149 //LENGTH 7.660 LUMPCC 0.0004989268 DR + +*CONN +*I sb_2__2_:chanx_left_out[5] O *L 0 *C 781.230 859.520 +*I cbx_2__2_:chanx_right_in[5] I *L 0 *C 773.570 859.520 + +*CAP +0 sb_2__2_:chanx_left_out[5] 0.0004891112 +1 cbx_2__2_:chanx_right_in[5] 0.0004891112 +2 sb_2__2_:chanx_left_out[5] sb_2__2_:chanx_left_in[7] 0.0001155203 +3 cbx_2__2_:chanx_right_in[5] cbx_2__2_:chanx_right_out[7] 0.0001155203 +4 sb_2__2_:chanx_left_out[5] sb_2__2_:chanx_left_out[14] 0.0001339431 +5 cbx_2__2_:chanx_right_in[5] cbx_2__2_:chanx_right_in[14] 0.0001339431 + +*RES +0 sb_2__2_:chanx_left_out[5] cbx_2__2_:chanx_right_in[5] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[15] 0.001475549 //LENGTH 7.660 LUMPCC 0.0003899716 DR + +*CONN +*I sb_2__2_:chanx_left_out[15] O *L 0 *C 781.230 833.680 +*I cbx_2__2_:chanx_right_in[15] I *L 0 *C 773.570 833.680 + +*CAP +0 sb_2__2_:chanx_left_out[15] 0.0005427888 +1 cbx_2__2_:chanx_right_in[15] 0.0005427888 +2 sb_2__2_:chanx_left_out[15] sb_2__2_:chanx_left_in[5] 3.737602e-05 +3 cbx_2__2_:chanx_right_in[15] cbx_1__2__1_chanx_right_out[5]:2 3.737602e-05 +4 sb_2__2_:chanx_left_out[15] sb_2__2_:chanx_left_out[6] 0.0001158384 +5 cbx_2__2_:chanx_right_in[15] cbx_2__2_:chanx_right_in[6] 0.0001158384 +6 sb_2__2_:chanx_left_out[15] sb_2__2_:chanx_left_out[7] 4.17714e-05 +7 cbx_2__2_:chanx_right_in[15] cbx_2__2_:chanx_right_in[7] 4.17714e-05 + +*RES +0 sb_2__2_:chanx_left_out[15] cbx_2__2_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[6] 0.001251666 //LENGTH 11.020 LUMPCC 0.0005699875 DR + +*CONN +*I sb_2__2_:chany_bottom_out[6] O *L 0 *C 856.060 788.870 +*I cby_2__2_:chany_top_in[6] I *L 0 *C 856.060 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[6] 0.0003408391 +1 cby_2__2_:chany_top_in[6] 0.0003408391 +2 sb_2__2_:chany_bottom_out[6] sb_2__2_:chany_bottom_in[5] 0.0001422469 +3 cby_2__2_:chany_top_in[6] cby_2__2_:chany_top_out[5] 0.0001422469 +4 sb_2__2_:chany_bottom_out[6] sb_2__2_:chany_bottom_out[11] 0.0001427469 +5 cby_2__2_:chany_top_in[6] cby_2__2_:chany_top_in[11] 0.0001427469 + +*RES +0 sb_2__2_:chany_bottom_out[6] cby_2__2_:chany_top_in[6] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[19] 0.001254698 //LENGTH 11.020 LUMPCC 0.0005639811 DR + +*CONN +*I sb_2__2_:chany_bottom_out[19] O *L 0 *C 851.920 788.870 +*I cby_2__2_:chany_top_in[19] I *L 0 *C 851.920 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[19] 0.0003453587 +1 cby_2__2_:chany_top_in[19] 0.0003453587 +2 sb_2__2_:chany_bottom_out[19] sb_2__2_:chany_bottom_in[17] 0.0001392436 +3 cby_2__2_:chany_top_in[19] cby_2__2_:chany_top_out[17] 0.0001392436 +4 sb_2__2_:chany_bottom_out[19] sb_2__2_:chany_bottom_out[5] 0.0001427469 +5 cby_2__2_:chany_top_in[19] cby_2__2_:chany_top_in[5] 0.0001427469 + +*RES +0 sb_2__2_:chany_bottom_out[19] cby_2__2_:chany_top_in[19] 0.009839286 + +*END + +*D_NET ctsbuf_net_918 0.002948151 //LENGTH 22.420 LUMPCC 0.0005224413 DR + +*CONN +*I cts_inv_73587633:Y O *L 0 *C 420.900 899.640 +*I grid_io_top_1__3_:prog_clk[0] I *L 0 *C 407.710 906.440 +*N ctsbuf_net_918:2 *C 407.108 906.440 +*N ctsbuf_net_918:3 *C 407.100 906.383 +*N ctsbuf_net_918:4 *C 407.100 901.058 +*N ctsbuf_net_918:5 *C 407.108 901.000 +*N ctsbuf_net_918:6 *C 420.893 901.000 +*N ctsbuf_net_918:7 *C 420.900 900.942 +*N ctsbuf_net_918:8 *C 420.900 899.685 +*N ctsbuf_net_918:9 *C 420.900 899.640 + +*CAP +0 cts_inv_73587633:Y 1e-06 +1 grid_io_top_1__3_:prog_clk[0] 6.866638e-05 +2 ctsbuf_net_918:2 6.866638e-05 +3 ctsbuf_net_918:3 0.0002581925 +4 ctsbuf_net_918:4 0.0002581925 +5 ctsbuf_net_918:5 0.0007825523 +6 ctsbuf_net_918:6 0.0007825523 +7 ctsbuf_net_918:7 8.713584e-05 +8 ctsbuf_net_918:8 8.713584e-05 +9 ctsbuf_net_918:9 3.161508e-05 +10 ctsbuf_net_918:5 ctsbuf_net_2130:58 0.0001685696 +11 ctsbuf_net_918:5 ctsbuf_net_2130:57 9.265107e-05 +12 ctsbuf_net_918:6 ctsbuf_net_2130:56 9.265107e-05 +13 ctsbuf_net_918:6 ctsbuf_net_2130:57 0.0001685696 + +*RES +0 cts_inv_73587633:Y ctsbuf_net_918:9 0.152 +1 ctsbuf_net_918:3 ctsbuf_net_918:2 0.00341 +2 ctsbuf_net_918:2 grid_io_top_1__3_:prog_clk[0] 9.439166e-05 +3 ctsbuf_net_918:4 ctsbuf_net_918:3 0.004754464 +4 ctsbuf_net_918:5 ctsbuf_net_918:4 0.00341 +5 ctsbuf_net_918:7 ctsbuf_net_918:6 0.00341 +6 ctsbuf_net_918:6 ctsbuf_net_918:5 0.00215965 +7 ctsbuf_net_918:9 ctsbuf_net_918:8 0.0045 +8 ctsbuf_net_918:8 ctsbuf_net_918:7 0.001122768 + +*END + +*D_NET ctsbuf_net_1625 0.01480049 //LENGTH 156.390 LUMPCC 0.0001567968 DR + +*CONN +*I cts_inv_73657640:Y O *L 0 *C 276.920 491.640 +*I sb_0__0_:prog_clk[0] I *L 0 *C 301.760 397.050 +*I cby_0__1_:prog_clk[0] I *L 0 *C 287.190 411.400 +*I grid_io_left_0__1_:prog_clk[0] I *L 0 *C 271.860 516.730 +*N ctsbuf_net_1625:4 *C 271.860 517.423 +*N ctsbuf_net_1625:5 *C 271.868 517.480 +*N ctsbuf_net_1625:6 *C 278.752 517.480 +*N ctsbuf_net_1625:7 *C 278.760 517.423 +*N ctsbuf_net_1625:8 *C 301.760 405.903 +*N ctsbuf_net_1625:9 *C 301.752 405.960 +*N ctsbuf_net_1625:10 *C 286.588 405.960 +*N ctsbuf_net_1625:11 *C 286.580 406.018 +*N ctsbuf_net_1625:12 *C 286.580 411.343 +*N ctsbuf_net_1625:13 *C 286.580 411.400 +*N ctsbuf_net_1625:14 *C 278.768 411.400 +*N ctsbuf_net_1625:15 *C 278.760 411.458 +*N ctsbuf_net_1625:16 *C 278.760 443.519 +*N ctsbuf_net_1625:17 *C 278.760 443.520 +*N ctsbuf_net_1625:18 *C 278.760 461.215 +*N ctsbuf_net_1625:19 *C 278.760 491.300 +*N ctsbuf_net_1625:20 *C 278.715 491.300 +*N ctsbuf_net_1625:21 *C 277.380 491.300 +*N ctsbuf_net_1625:22 *C 277.380 491.640 +*N ctsbuf_net_1625:23 *C 276.958 491.640 + +*CAP +0 cts_inv_73657640:Y 1e-06 +1 sb_0__0_:prog_clk[0] 0.000418591 +2 cby_0__1_:prog_clk[0] 9.911916e-05 +3 grid_io_left_0__1_:prog_clk[0] 6.44247e-05 +4 ctsbuf_net_1625:4 6.44247e-05 +5 ctsbuf_net_1625:5 0.0003922302 +6 ctsbuf_net_1625:6 0.0003922302 +7 ctsbuf_net_1625:7 0.001196584 +8 ctsbuf_net_1625:8 0.000418591 +9 ctsbuf_net_1625:9 0.0008474675 +10 ctsbuf_net_1625:10 0.0008474675 +11 ctsbuf_net_1625:11 0.0002873282 +12 ctsbuf_net_1625:12 0.0002873282 +13 ctsbuf_net_1625:13 0.0004750954 +14 ctsbuf_net_1625:14 0.0003759762 +15 ctsbuf_net_1625:15 0.001397854 +16 ctsbuf_net_1625:16 0.001397854 +17 ctsbuf_net_1625:17 0.000750148 +18 ctsbuf_net_1625:18 0.002064789 +19 ctsbuf_net_1625:19 0.002538415 +20 ctsbuf_net_1625:20 8.424363e-05 +21 ctsbuf_net_1625:21 0.000114984 +22 ctsbuf_net_1625:22 7.914566e-05 +23 ctsbuf_net_1625:23 4.840529e-05 +24 sb_0__0_:prog_clk[0] sb_0__0_:chany_top_in[17] 3.402403e-05 +25 ctsbuf_net_1625:8 cby_0__1_:chany_bottom_out[17] 3.402403e-05 +26 ctsbuf_net_1625:10 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:4 4.437435e-05 +27 ctsbuf_net_1625:9 grid_io_left_0_right_width_0_height_0__pin_1_lower[0]:3 4.437435e-05 + +*RES +0 cts_inv_73657640:Y ctsbuf_net_1625:23 0.152 +1 ctsbuf_net_1625:7 ctsbuf_net_1625:6 0.00341 +2 ctsbuf_net_1625:6 ctsbuf_net_1625:5 0.00107865 +3 ctsbuf_net_1625:4 grid_io_left_0__1_:prog_clk[0] 0.0006183037 +4 ctsbuf_net_1625:5 ctsbuf_net_1625:4 0.00341 +5 ctsbuf_net_1625:15 ctsbuf_net_1625:14 0.00341 +6 ctsbuf_net_1625:14 ctsbuf_net_1625:13 0.001223958 +7 ctsbuf_net_1625:20 ctsbuf_net_1625:19 0.0045 +8 ctsbuf_net_1625:19 ctsbuf_net_1625:18 0.02686161 +9 ctsbuf_net_1625:19 ctsbuf_net_1625:7 0.02332366 +10 ctsbuf_net_1625:23 ctsbuf_net_1625:22 0.0003772322 +11 ctsbuf_net_1625:12 ctsbuf_net_1625:11 0.004754465 +12 ctsbuf_net_1625:13 ctsbuf_net_1625:12 0.00341 +13 ctsbuf_net_1625:13 cby_0__1_:prog_clk[0] 9.556665e-05 +14 ctsbuf_net_1625:11 ctsbuf_net_1625:10 0.00341 +15 ctsbuf_net_1625:10 ctsbuf_net_1625:9 0.00237585 +16 ctsbuf_net_1625:8 sb_0__0_:prog_clk[0] 0.007904018 +17 ctsbuf_net_1625:9 ctsbuf_net_1625:8 0.00341 +18 ctsbuf_net_1625:22 ctsbuf_net_1625:21 0.0003035715 +19 ctsbuf_net_1625:21 ctsbuf_net_1625:20 0.001191964 +20 ctsbuf_net_1625:18 ctsbuf_net_1625:17 0.01579911 +21 ctsbuf_net_1625:17 ctsbuf_net_1625:16 1e-05 +22 ctsbuf_net_1625:16 ctsbuf_net_1625:15 0.02862634 + +*END + +*D_NET gfpga_pad_GPIO_A[5] 0.02523686 //LENGTH 291.315 LUMPCC 0 DR + +*CONN +*I grid_io_bottom_2__0_:gfpga_pad_GPIO_A[0] O *L 0 *C 731.400 261.190 +*P gfpga_pad_GPIO_A[5] O *L 0 *C 701.500 0.415 +*N gfpga_pad_GPIO_A[5]:2 *C 701.500 50.415 +*N gfpga_pad_GPIO_A[5]:3 *C 701.500 100.415 +*N gfpga_pad_GPIO_A[5]:4 *C 701.500 107.055 +*N gfpga_pad_GPIO_A[5]:5 *C 701.545 107.100 +*N gfpga_pad_GPIO_A[5]:6 *C 731.355 107.100 +*N gfpga_pad_GPIO_A[5]:7 *C 731.400 107.145 +*N gfpga_pad_GPIO_A[5]:8 *C 731.400 156.940 +*N gfpga_pad_GPIO_A[5]:9 *C 731.400 206.940 +*N gfpga_pad_GPIO_A[5]:10 *C 731.400 219.519 +*N gfpga_pad_GPIO_A[5]:11 *C 731.400 219.520 + +*CAP +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_A[0] 0.001812779 +1 gfpga_pad_GPIO_A[5] 0.002127689 +2 gfpga_pad_GPIO_A[5]:2 0.004231802 +3 gfpga_pad_GPIO_A[5]:3 0.002399183 +4 gfpga_pad_GPIO_A[5]:4 0.0002950708 +5 gfpga_pad_GPIO_A[5]:5 0.001499061 +6 gfpga_pad_GPIO_A[5]:6 0.001499061 +7 gfpga_pad_GPIO_A[5]:7 0.002122432 +8 gfpga_pad_GPIO_A[5]:8 0.004243203 +9 gfpga_pad_GPIO_A[5]:9 0.002657284 +10 gfpga_pad_GPIO_A[5]:10 0.0005365126 +11 gfpga_pad_GPIO_A[5]:11 0.001812779 + +*RES +0 grid_io_bottom_2__0_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[5]:11 0.03720536 +1 gfpga_pad_GPIO_A[5]:6 gfpga_pad_GPIO_A[5]:5 0.02661607 +2 gfpga_pad_GPIO_A[5]:7 gfpga_pad_GPIO_A[5]:6 0.0045 +3 gfpga_pad_GPIO_A[5]:5 gfpga_pad_GPIO_A[5]:4 0.0045 +4 gfpga_pad_GPIO_A[5]:4 gfpga_pad_GPIO_A[5]:3 0.005928572 +5 gfpga_pad_GPIO_A[5]:2 gfpga_pad_GPIO_A[5] 0.04464286 +6 gfpga_pad_GPIO_A[5]:3 gfpga_pad_GPIO_A[5]:2 0.04464286 +7 gfpga_pad_GPIO_A[5]:8 gfpga_pad_GPIO_A[5]:7 0.04445982 +8 gfpga_pad_GPIO_A[5]:9 gfpga_pad_GPIO_A[5]:8 0.04464286 +9 gfpga_pad_GPIO_A[5]:11 gfpga_pad_GPIO_A[5]:10 1e-05 +10 gfpga_pad_GPIO_A[5]:10 gfpga_pad_GPIO_A[5]:9 0.01123125 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[12] 0.001258069 //LENGTH 11.020 LUMPCC 0.0005548456 DR + +*CONN +*I cby_2__2_:chany_bottom_out[12] O *L 0 *C 833.980 669.190 +*I sb_2__1_:chany_top_in[12] I *L 0 *C 833.980 658.170 +*N cby_1__1__3_chany_bottom_out[12]:2 *C 833.980 667.519 +*N cby_1__1__3_chany_bottom_out[12]:3 *C 833.980 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[12] 0.0001111879 +1 sb_2__1_:chany_top_in[12] 0.0002404239 +2 cby_1__1__3_chany_bottom_out[12]:2 0.0002404239 +3 cby_1__1__3_chany_bottom_out[12]:3 0.0001111879 +4 cby_2__2_:chany_bottom_out[12] cby_2__2_:chany_bottom_out[4] 7.339873e-06 +5 sb_2__1_:chany_top_in[12] sb_2__1_:chany_top_in[4] 0.0001310978 +6 cby_1__1__3_chany_bottom_out[12]:3 cby_1__1__3_chany_bottom_out[4]:3 7.339873e-06 +7 cby_1__1__3_chany_bottom_out[12]:2 cby_1__1__3_chany_bottom_out[4]:2 0.0001310978 +8 cby_2__2_:chany_bottom_out[12] cby_2__2_:chany_bottom_out[15] 7.244793e-06 +9 sb_2__1_:chany_top_in[12] sb_2__1_:chany_top_in[15] 0.0001317403 +10 cby_1__1__3_chany_bottom_out[12]:3 cby_1__1__3_chany_bottom_out[15]:3 7.244793e-06 +11 cby_1__1__3_chany_bottom_out[12]:2 cby_1__1__3_chany_bottom_out[15]:2 0.0001317403 + +*RES +0 cby_2__2_:chany_bottom_out[12] cby_1__1__3_chany_bottom_out[12]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[12]:3 cby_1__1__3_chany_bottom_out[12]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[12]:2 sb_2__1_:chany_top_in[12] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_bottom_out[19] 0.001257977 //LENGTH 11.020 LUMPCC 0.0005502676 DR + +*CONN +*I cby_2__2_:chany_bottom_out[19] O *L 0 *C 840.420 669.190 +*I sb_2__1_:chany_top_in[19] I *L 0 *C 840.420 658.170 +*N cby_1__1__3_chany_bottom_out[19]:2 *C 840.420 667.519 +*N cby_1__1__3_chany_bottom_out[19]:3 *C 840.420 667.520 + +*CAP +0 cby_2__2_:chany_bottom_out[19] 0.0001109378 +1 sb_2__1_:chany_top_in[19] 0.0002429168 +2 cby_1__1__3_chany_bottom_out[19]:2 0.0002429168 +3 cby_1__1__3_chany_bottom_out[19]:3 0.0001109378 +4 cby_2__2_:chany_bottom_out[19] cby_2__2_:chany_bottom_out[5] 7.340369e-06 +5 sb_2__1_:chany_top_in[19] sb_2__1_:chany_top_in[5] 0.0001302265 +6 cby_1__1__3_chany_bottom_out[19]:3 cby_1__1__3_chany_bottom_out[5]:3 7.340369e-06 +7 cby_1__1__3_chany_bottom_out[19]:2 cby_1__1__3_chany_bottom_out[5]:2 0.0001302265 +8 cby_2__2_:chany_bottom_out[19] cby_2__2_:chany_bottom_in[9] 7.340369e-06 +9 sb_2__1_:chany_top_in[19] sb_2__1_:chany_top_out[9] 0.0001302265 +10 cby_1__1__3_chany_bottom_out[19]:3 sb_2__1__0_chany_top_out[9]:2 7.340369e-06 +11 cby_1__1__3_chany_bottom_out[19]:2 sb_2__1__0_chany_top_out[9]:3 0.0001302265 + +*RES +0 cby_2__2_:chany_bottom_out[19] cby_1__1__3_chany_bottom_out[19]:3 0.001491072 +1 cby_1__1__3_chany_bottom_out[19]:3 cby_1__1__3_chany_bottom_out[19]:2 1e-05 +2 cby_1__1__3_chany_bottom_out[19]:2 sb_2__1_:chany_top_in[19] 0.008347321 + +*END + +*D_NET cby_1__1__3_chany_top_out[4] 0.001236644 //LENGTH 11.020 LUMPCC 0.000587663 DR + +*CONN +*I cby_2__2_:chany_top_out[4] O *L 0 *C 846.400 777.850 +*I sb_2__2_:chany_bottom_in[4] I *L 0 *C 846.400 788.870 + +*CAP +0 cby_2__2_:chany_top_out[4] 0.0003244906 +1 sb_2__2_:chany_bottom_in[4] 0.0003244906 +2 cby_2__2_:chany_top_out[4] cby_2__2_:chany_top_out[14] 0.0001469158 +3 sb_2__2_:chany_bottom_in[4] sb_2__2_:chany_bottom_in[14] 0.0001469158 +4 cby_2__2_:chany_top_out[4] cby_2__2_:chany_top_in[16] 0.0001469158 +5 sb_2__2_:chany_bottom_in[4] sb_2__2_:chany_bottom_out[16] 0.0001469158 + +*RES +0 cby_2__2_:chany_top_out[4] sb_2__2_:chany_bottom_in[4] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[9] 0.001168644 //LENGTH 11.020 LUMPCC 0.0003749556 DR + +*CONN +*I cby_2__2_:chany_top_out[9] O *L 0 *C 865.260 777.850 +*I sb_2__2_:chany_bottom_in[9] I *L 0 *C 865.260 788.870 + +*CAP +0 cby_2__2_:chany_top_out[9] 0.0003968441 +1 sb_2__2_:chany_bottom_in[9] 0.0003968441 +2 cby_2__2_:chany_top_out[9] cby_2__2_:chany_top_out[11] 4.792491e-05 +3 sb_2__2_:chany_bottom_in[9] sb_2__2_:chany_bottom_in[11] 4.792491e-05 +4 cby_2__2_:chany_top_out[9] cby_2__2_:chany_top_in[0] 0.0001395529 +5 sb_2__2_:chany_bottom_in[9] sb_2__2_:chany_bottom_out[0] 0.0001395529 + +*RES +0 cby_2__2_:chany_top_out[9] sb_2__2_:chany_bottom_in[9] 0.009839286 + +*END + +*D_NET cby_1__1__3_chany_top_out[15] 0.001293915 //LENGTH 11.020 LUMPCC 0.0006052724 DR + +*CONN +*I cby_2__2_:chany_top_out[15] O *L 0 *C 834.440 777.850 +*I sb_2__2_:chany_bottom_in[15] I *L 0 *C 834.440 788.870 + +*CAP +0 cby_2__2_:chany_top_out[15] 0.0003443212 +1 sb_2__2_:chany_bottom_in[15] 0.0003443212 +2 cby_2__2_:chany_top_out[15] cby_2__2_:chany_top_in[2] 6.950935e-05 +3 cby_2__2_:chany_top_out[15] sb_2__2__0_chany_bottom_out[2]:3 7.40632e-05 +4 cby_2__2_:chany_top_out[15] sb_2__2__0_chany_bottom_out[2]:5 1.638596e-05 +5 sb_2__2_:chany_bottom_in[15] sb_2__2_:chany_bottom_out[2] 1.638596e-05 +6 sb_2__2_:chany_bottom_in[15] sb_2__2__0_chany_bottom_out[2]:2 6.950935e-05 +7 sb_2__2_:chany_bottom_in[15] sb_2__2__0_chany_bottom_out[2]:4 7.40632e-05 +8 cby_2__2_:chany_top_out[15] cby_2__2_:chany_top_in[9] 0.0001426777 +9 sb_2__2_:chany_bottom_in[15] sb_2__2_:chany_bottom_out[9] 0.0001426777 + +*RES +0 cby_2__2_:chany_top_out[15] sb_2__2_:chany_bottom_in[15] 0.009839286 + +*END + +*D_NET cby_1__1__3_left_grid_pin_0_[0] 0.001231 //LENGTH 7.660 LUMPCC 0.0007040367 DR + +*CONN +*I cby_2__2_:left_grid_pin_0_[0] O *L 0 *C 809.750 771.120 +*I grid_clb_2__2_:right_width_0_height_0__pin_0_[0] I *L 0 *C 802.090 771.120 + +*CAP +0 cby_2__2_:left_grid_pin_0_[0] 0.0002634815 +1 grid_clb_2__2_:right_width_0_height_0__pin_0_[0] 0.0002634815 +2 cby_2__2_:left_grid_pin_0_[0] cby_2__2_:left_grid_pin_4_[0] 0.0001736158 +3 grid_clb_2__2_:right_width_0_height_0__pin_0_[0] grid_clb_2__2_:right_width_0_height_0__pin_4_[0] 0.0001736158 +4 cby_2__2_:left_grid_pin_0_[0] cby_2__2_:left_grid_pin_5_[0] 0.0001784025 +5 grid_clb_2__2_:right_width_0_height_0__pin_0_[0] grid_clb_2__2_:right_width_0_height_0__pin_5_[0] 0.0001784025 + +*RES +0 cby_2__2_:left_grid_pin_0_[0] grid_clb_2__2_:right_width_0_height_0__pin_0_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_15_[0] 0.001094417 //LENGTH 7.660 LUMPCC 0.0003535021 DR + +*CONN +*I cby_2__2_:left_grid_pin_15_[0] O *L 0 *C 809.750 703.120 +*I grid_clb_2__2_:right_width_0_height_0__pin_15_[0] I *L 0 *C 802.090 703.120 + +*CAP +0 cby_2__2_:left_grid_pin_15_[0] 0.0003704575 +1 grid_clb_2__2_:right_width_0_height_0__pin_15_[0] 0.0003704575 +2 cby_2__2_:left_grid_pin_15_[0] cby_2__2_:left_grid_pin_12_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_15_[0] grid_clb_2__2_:right_width_0_height_0__pin_12_[0] 0.0001767511 + +*RES +0 cby_2__2_:left_grid_pin_15_[0] grid_clb_2__2_:right_width_0_height_0__pin_15_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_left_grid_pin_8_[0] 0.001100726 //LENGTH 7.660 LUMPCC 0.0003535021 DR + +*CONN +*I cby_2__2_:left_grid_pin_8_[0] O *L 0 *C 809.750 745.280 +*I grid_clb_2__2_:right_width_0_height_0__pin_8_[0] I *L 0 *C 802.090 745.280 + +*CAP +0 cby_2__2_:left_grid_pin_8_[0] 0.0003736122 +1 grid_clb_2__2_:right_width_0_height_0__pin_8_[0] 0.0003736122 +2 cby_2__2_:left_grid_pin_8_[0] cby_2__2_:left_grid_pin_11_[0] 0.0001767511 +3 grid_clb_2__2_:right_width_0_height_0__pin_8_[0] grid_clb_2__2_:right_width_0_height_0__pin_11_[0] 0.0001767511 + +*RES +0 cby_2__2_:left_grid_pin_8_[0] grid_clb_2__2_:right_width_0_height_0__pin_8_[0] 0.001200067 + +*END + +*D_NET cby_1__1__3_right_grid_pin_52_[0] 0.001867374 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I cby_2__2_:right_grid_pin_52_[0] O *L 0 *C 894.090 748.000 +*I grid_io_right_3__2_:left_width_0_height_0__pin_0_[0] I *L 0 *C 907.270 748.000 + +*CAP +0 cby_2__2_:right_grid_pin_52_[0] 0.0009336869 +1 grid_io_right_3__2_:left_width_0_height_0__pin_0_[0] 0.0009336869 + +*RES +0 cby_2__2_:right_grid_pin_52_[0] grid_io_right_3__2_:left_width_0_height_0__pin_0_[0] 0.002064867 + +*END + +*D_NET direct_interc_4_out[0] 0.01227906 //LENGTH 103.545 LUMPCC 0.002669335 DR + +*CONN +*I direct_interc_4_\/FTB_5__4:X O *L 0 *C 782.695 639.880 +*I grid_clb_2__1_:top_width_0_height_0__pin_33_[0] I *L 0 *C 777.400 543.930 +*N direct_interc_4_out[0]:2 *C 776.690 545.360 +*N direct_interc_4_out[0]:3 *C 777.400 545.303 +*N direct_interc_4_out[0]:4 *C 777.398 545.360 +*N direct_interc_4_out[0]:5 *C 777.400 545.368 +*N direct_interc_4_out[0]:6 *C 777.400 595.195 +*N direct_interc_4_out[0]:7 *C 777.400 635.113 +*N direct_interc_4_out[0]:8 *C 777.420 635.120 +*N direct_interc_4_out[0]:9 *C 782.452 635.120 +*N direct_interc_4_out[0]:10 *C 782.460 635.178 +*N direct_interc_4_out[0]:11 *C 782.460 639.835 +*N direct_interc_4_out[0]:12 *C 782.460 639.880 +*N direct_interc_4_out[0]:13 *C 782.695 639.880 + +*CAP +0 direct_interc_4_\/FTB_5__4:X 1e-06 +1 grid_clb_2__1_:top_width_0_height_0__pin_33_[0] 0.0001088149 +2 direct_interc_4_out[0]:2 9.869894e-05 +3 direct_interc_4_out[0]:3 0.0001088149 +4 direct_interc_4_out[0]:4 9.869894e-05 +5 direct_interc_4_out[0]:5 0.002418562 +6 direct_interc_4_out[0]:6 0.004092202 +7 direct_interc_4_out[0]:7 0.00167364 +8 direct_interc_4_out[0]:8 0.0002743895 +9 direct_interc_4_out[0]:9 0.0002743895 +10 direct_interc_4_out[0]:10 0.0001817745 +11 direct_interc_4_out[0]:11 0.0001817745 +12 direct_interc_4_out[0]:12 4.898935e-05 +13 direct_interc_4_out[0]:13 4.79787e-05 +14 direct_interc_4_out[0]:5 cbx_1__1__1_chanx_right_out[16]:4 0.0005354855 +15 direct_interc_4_out[0]:6 cbx_1__1__1_chanx_right_out[16]:3 0.0005354855 +16 direct_interc_4_out[0]:7 cbx_1__1__1_chanx_right_out[18]:4 0.0007282233 +17 direct_interc_4_out[0]:6 cbx_1__1__1_chanx_right_out[18]:3 0.0007282233 +18 direct_interc_4_out[0]:11 grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] 7.095894e-05 +19 direct_interc_4_out[0]:10 sb_2__1_:left_top_grid_pin_46_[0] 7.095894e-05 + +*RES +0 direct_interc_4_\/FTB_5__4:X direct_interc_4_out[0]:13 0.152 +1 direct_interc_4_out[0]:13 direct_interc_4_out[0]:12 0.0001277174 +2 direct_interc_4_out[0]:12 direct_interc_4_out[0]:11 0.0045 +3 direct_interc_4_out[0]:11 direct_interc_4_out[0]:10 0.004158482 +4 direct_interc_4_out[0]:10 direct_interc_4_out[0]:9 0.00341 +5 direct_interc_4_out[0]:9 direct_interc_4_out[0]:8 0.0007884249 +6 direct_interc_4_out[0]:8 direct_interc_4_out[0]:7 0.00341 +7 direct_interc_4_out[0]:7 direct_interc_4_out[0]:6 0.006253741 +8 direct_interc_4_out[0]:4 direct_interc_4_out[0]:3 0.00341 +9 direct_interc_4_out[0]:4 direct_interc_4_out[0]:2 0.0001039141 +10 direct_interc_4_out[0]:5 direct_interc_4_out[0]:4 0.00341 +11 direct_interc_4_out[0]:3 grid_clb_2__1_:top_width_0_height_0__pin_33_[0] 0.001225446 +12 direct_interc_4_out[0]:6 direct_interc_4_out[0]:5 0.007806308 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_43_upper[0] 0.00109432 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_43_upper[0] O *L 0 *C 379.190 393.040 +*I sb_0__0_:right_top_grid_pin_43_[0] I *L 0 *C 371.530 393.040 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_43_upper[0] 0.0005471599 +1 sb_0__0_:right_top_grid_pin_43_[0] 0.0005471599 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_43_upper[0] sb_0__0_:right_top_grid_pin_43_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_44_lower[0] 0.001252507 //LENGTH 11.020 LUMPCC 0.0005622869 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] O *L 0 *C 523.940 380.870 +*I sb_1__0_:left_top_grid_pin_44_[0] I *L 0 *C 523.940 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0003451098 +1 sb_1__0_:left_top_grid_pin_44_[0] 0.0003451098 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_45_lower[0] 0.0001405717 +3 sb_1__0_:left_top_grid_pin_44_[0] sb_1__0_:left_top_grid_pin_45_[0] 0.0001405717 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_1__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0001405717 +5 sb_1__0_:left_top_grid_pin_44_[0] sb_1__0_:left_top_grid_pin_47_[0] 0.0001405717 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_44_lower[0] sb_1__0_:left_top_grid_pin_44_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_45_upper[0] 0.00123408 //LENGTH 11.020 LUMPCC 0.0005948123 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] O *L 0 *C 396.060 380.870 +*I sb_0__0_:right_top_grid_pin_45_[0] I *L 0 *C 396.060 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0003196339 +1 sb_0__0_:right_top_grid_pin_45_[0] 0.0003196339 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_42_upper[0] 0.0001487031 +3 sb_0__0_:right_top_grid_pin_45_[0] sb_0__0_:right_top_grid_pin_42_[0] 0.0001487031 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] 0.0001487031 +5 sb_0__0_:right_top_grid_pin_45_[0] sb_0__0_:right_top_grid_pin_49_[0] 0.0001487031 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] sb_0__0_:right_top_grid_pin_45_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_47_upper[0] 0.00146733 //LENGTH 7.660 LUMPCC 0.0006563768 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] O *L 0 *C 379.190 384.200 +*I sb_0__0_:right_top_grid_pin_47_[0] I *L 0 *C 371.530 384.200 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] 0.0004054764 +1 sb_0__0_:right_top_grid_pin_47_[0] 0.0004054764 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_46_upper[0] 1.254446e-05 +3 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:2 4.183733e-06 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:4 0.0003114602 +5 sb_0__0_:right_top_grid_pin_47_[0] sb_0__0_:right_top_grid_pin_46_[0] 4.183733e-06 +6 sb_0__0_:right_top_grid_pin_47_[0] grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:3 0.0003114602 +7 sb_0__0_:right_top_grid_pin_47_[0] grid_clb_0_bottom_width_0_height_0__pin_46_upper[0]:5 1.254446e-05 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_47_upper[0] sb_0__0_:right_top_grid_pin_47_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_bottom_width_0_height_0__pin_49_upper[0] 0.001234117 //LENGTH 11.020 LUMPCC 0.0006064588 DR + +*CONN +*I grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] O *L 0 *C 395.140 380.870 +*I sb_0__0_:right_top_grid_pin_49_[0] I *L 0 *C 395.140 369.850 + +*CAP +0 grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] 0.000313829 +1 sb_0__0_:right_top_grid_pin_49_[0] 0.000313829 +2 grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0001487031 +3 sb_0__0_:right_top_grid_pin_49_[0] sb_0__0_:right_top_grid_pin_45_[0] 0.0001487031 +4 grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_1__1_:bottom_width_0_height_0__pin_48_upper[0] 0.0001545263 +5 sb_0__0_:right_top_grid_pin_49_[0] sb_0__0_:right_top_grid_pin_48_[0] 0.0001545263 + +*RES +0 grid_clb_1__1_:bottom_width_0_height_0__pin_49_upper[0] sb_0__0_:right_top_grid_pin_49_[0] 0.009839286 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_34_lower[0] 0.002748539 //LENGTH 22.050 LUMPCC 0.0007420034 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] O *L 0 *C 540.810 406.640 +*I sb_1__0_:top_left_grid_pin_34_[0] I *L 0 *C 552.920 397.050 +*N grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 *C 552.920 406.583 +*N grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 *C 552.913 406.640 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] 0.0005522179 +1 sb_1__0_:top_left_grid_pin_34_[0] 0.0004510499 +2 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 0.0004510499 +3 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 0.0005522179 +4 grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_35_lower[0] 0.0002721755 +5 sb_1__0_:top_left_grid_pin_34_[0] sb_1__0_:top_left_grid_pin_35_[0] 5.217548e-06 +6 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:2 5.217548e-06 +7 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_35_lower[0]:3 0.0002721755 +8 grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_37_lower[0] 6.476565e-05 +9 sb_1__0_:top_left_grid_pin_34_[0] sb_1__0_:top_left_grid_pin_37_[0] 2.884306e-05 +10 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:2 2.884306e-05 +11 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_37_lower[0]:7 6.476565e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_34_lower[0] grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 0.001896058 +1 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 sb_1__0_:top_left_grid_pin_34_[0] 0.008511161 +2 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_0_right_width_0_height_0__pin_34_lower[0]:2 0.00341 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_38_lower[0] 0.00136206 //LENGTH 7.660 LUMPCC 0.0004523929 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] O *L 0 *C 540.810 391.680 +*I sb_1__0_:top_left_grid_pin_38_[0] I *L 0 *C 548.470 391.680 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] 0.0004548334 +1 sb_1__0_:top_left_grid_pin_38_[0] 0.0004548334 +2 grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_36_lower[0] 8.431709e-05 +3 sb_1__0_:top_left_grid_pin_38_[0] sb_1__0_:top_left_grid_pin_36_[0] 8.431709e-05 +4 grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] 0.0001418794 +5 sb_1__0_:top_left_grid_pin_38_[0] sb_1__0_:top_left_grid_pin_39_[0] 0.0001418794 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_38_lower[0] sb_1__0_:top_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_40_lower[0] 0.00133959 //LENGTH 7.660 LUMPCC 0.000346805 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] O *L 0 *C 540.810 388.960 +*I sb_1__0_:top_left_grid_pin_40_[0] I *L 0 *C 548.470 388.960 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] 0.0004963927 +1 sb_1__0_:top_left_grid_pin_40_[0] 0.0004963927 +2 grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] grid_clb_1__1_:right_width_0_height_0__pin_39_lower[0] 0.0001371345 +3 sb_1__0_:top_left_grid_pin_40_[0] sb_1__0_:top_left_grid_pin_39_[0] 0.0001371345 +4 grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] grid_clb_0_right_width_0_height_0__pin_41_lower[0]:6 3.626794e-05 +5 sb_1__0_:top_left_grid_pin_40_[0] grid_clb_0_right_width_0_height_0__pin_41_lower[0]:5 3.626794e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_40_lower[0] sb_1__0_:top_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_clb_0_right_width_0_height_0__pin_41_upper[0] 0.002962008 //LENGTH 20.610 LUMPCC 0.0002313373 DR + +*CONN +*I grid_clb_1__1_:right_width_0_height_0__pin_41_upper[0] O *L 0 *C 540.810 529.720 +*I sb_1__1_:bottom_left_grid_pin_41_[0] I *L 0 *C 548.470 541.960 +*N grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 *C 544.660 541.960 +*N grid_clb_0_right_width_0_height_0__pin_41_upper[0]:3 *C 544.640 541.952 +*N grid_clb_0_right_width_0_height_0__pin_41_upper[0]:4 *C 544.640 529.728 +*N grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 *C 544.620 529.720 + +*CAP +0 grid_clb_1__1_:right_width_0_height_0__pin_41_upper[0] 0.0002877588 +1 sb_1__1_:bottom_left_grid_pin_41_[0] 0.0003396595 +2 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 0.0003396595 +3 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:3 0.0007379173 +4 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:4 0.0007379173 +5 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 0.0002877588 +6 grid_clb_1__1_:right_width_0_height_0__pin_41_upper[0] grid_clb_1__1_:right_width_0_height_0__pin_37_upper[0] 6.709016e-05 +7 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 sb_1__1_:bottom_left_grid_pin_37_[0] 6.709016e-05 +8 sb_1__1_:bottom_left_grid_pin_41_[0] sb_1__1_:bottom_left_grid_pin_40_[0] 4.857847e-05 +9 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 grid_clb_1__1_:right_width_0_height_0__pin_40_upper[0] 4.857847e-05 + +*RES +0 grid_clb_1__1_:right_width_0_height_0__pin_41_upper[0] grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 0.0005969 +1 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 sb_1__1_:bottom_left_grid_pin_41_[0] 0.0005969 +2 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:3 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:2 0.00341 +3 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:5 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:4 0.00341 +4 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:4 grid_clb_0_right_width_0_height_0__pin_41_upper[0]:3 0.00191525 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_42_upper[0] 0.001244499 //LENGTH 11.020 LUMPCC 0.0005696768 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] O *L 0 *C 396.980 641.990 +*I sb_0__1_:right_top_grid_pin_42_[0] I *L 0 *C 396.980 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0003374111 +1 sb_0__1_:right_top_grid_pin_42_[0] 0.0003374111 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_44_upper[0] 0.0001424192 +3 sb_0__1_:right_top_grid_pin_42_[0] sb_0__1_:right_top_grid_pin_44_[0] 0.0001424192 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0001424192 +5 sb_0__1_:right_top_grid_pin_42_[0] sb_0__1_:right_top_grid_pin_45_[0] 0.0001424192 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] sb_0__1_:right_top_grid_pin_42_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_45_upper[0] 0.00124434 //LENGTH 11.020 LUMPCC 0.0005696768 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] O *L 0 *C 396.060 641.990 +*I sb_0__1_:right_top_grid_pin_45_[0] I *L 0 *C 396.060 630.970 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0003373318 +1 sb_0__1_:right_top_grid_pin_45_[0] 0.0003373318 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_42_upper[0] 0.0001424192 +3 sb_0__1_:right_top_grid_pin_45_[0] sb_0__1_:right_top_grid_pin_42_[0] 0.0001424192 +4 grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0001424192 +5 sb_0__1_:right_top_grid_pin_45_[0] sb_0__1_:right_top_grid_pin_49_[0] 0.0001424192 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_45_upper[0] sb_0__1_:right_top_grid_pin_45_[0] 0.009839285 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_47_upper[0] 0.001262598 //LENGTH 7.660 LUMPCC 0.0003001954 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_47_upper[0] O *L 0 *C 379.190 645.320 +*I sb_0__1_:right_top_grid_pin_47_[0] I *L 0 *C 371.530 645.320 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_47_upper[0] 0.0004812011 +1 sb_0__1_:right_top_grid_pin_47_[0] 0.0004812011 +2 grid_clb_1__2_:bottom_width_0_height_0__pin_47_upper[0] grid_clb_1__2_:bottom_width_0_height_0__pin_46_upper[0] 0.0001500977 +3 sb_0__1_:right_top_grid_pin_47_[0] sb_0__1_:right_top_grid_pin_46_[0] 0.0001500977 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_47_upper[0] sb_0__1_:right_top_grid_pin_47_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_bottom_width_0_height_0__pin_50_[0] 0.0004663992 //LENGTH 3.385 LUMPCC 0 DR + +*CONN +*I grid_clb_1__2_:bottom_width_0_height_0__pin_50_[0] O *L 0 *C 515.200 641.990 +*I direct_interc_0_\/FTB_1__0:A I *L 0.001746 *C 513.820 640.560 +*N grid_clb_1_bottom_width_0_height_0__pin_50_[0]:2 *C 513.820 640.560 +*N grid_clb_1_bottom_width_0_height_0__pin_50_[0]:3 *C 513.820 640.900 +*N grid_clb_1_bottom_width_0_height_0__pin_50_[0]:4 *C 515.155 640.900 +*N grid_clb_1_bottom_width_0_height_0__pin_50_[0]:5 *C 515.200 640.945 + +*CAP +0 grid_clb_1__2_:bottom_width_0_height_0__pin_50_[0] 8.960105e-05 +1 direct_interc_0_\/FTB_1__0:A 1e-06 +2 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:2 5.553429e-05 +3 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:3 0.0001297704 +4 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:4 0.0001008923 +5 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:5 8.960105e-05 + +*RES +0 grid_clb_1__2_:bottom_width_0_height_0__pin_50_[0] grid_clb_1_bottom_width_0_height_0__pin_50_[0]:5 0.0009330358 +1 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:4 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:3 0.001191964 +2 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:5 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:4 0.0045 +3 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:2 direct_interc_0_\/FTB_1__0:A 0.152 +4 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:3 grid_clb_1_bottom_width_0_height_0__pin_50_[0]:2 0.0003035715 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_34_lower[0] 0.002546557 //LENGTH 20.670 LUMPCC 0.0003245216 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] O *L 0 *C 540.810 667.760 +*I sb_1__1_:top_left_grid_pin_34_[0] I *L 0 *C 551.540 658.170 +*N grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 *C 551.540 667.519 +*N grid_clb_1_right_width_0_height_0__pin_34_lower[0]:3 *C 551.540 667.520 +*N grid_clb_1_right_width_0_height_0__pin_34_lower[0]:4 *C 551.540 667.702 +*N grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 *C 551.533 667.760 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] 0.000682233 +1 sb_1__1_:top_left_grid_pin_34_[0] 0.0004001795 +2 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 0.0004001795 +3 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:3 2.860539e-05 +4 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:4 2.860539e-05 +5 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 0.000682233 +6 grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_35_lower[0] 1.757948e-05 +7 sb_1__1_:top_left_grid_pin_34_[0] sb_1__1_:top_left_grid_pin_35_[0] 2.001383e-05 +8 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:11 1.757948e-05 +9 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_1_right_width_0_height_0__pin_35_lower[0]:2 2.001383e-05 +10 grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_37_lower[0] 0.0001086187 +11 sb_1__1_:top_left_grid_pin_34_[0] sb_1__1_:top_left_grid_pin_37_[0] 1.604878e-05 +12 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:9 0.0001086187 +13 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 grid_clb_1_right_width_0_height_0__pin_37_lower[0]:2 1.604878e-05 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_34_lower[0] grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 0.001679858 +1 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:4 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:3 0.0001629464 +2 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:5 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:4 0.00341 +3 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:3 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 1e-05 +4 grid_clb_1_right_width_0_height_0__pin_34_lower[0]:2 sb_1__1_:top_left_grid_pin_34_[0] 0.008347322 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_38_lower[0] 0.001504181 //LENGTH 7.660 LUMPCC 0.0003428779 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] O *L 0 *C 540.810 652.800 +*I sb_1__1_:top_left_grid_pin_38_[0] I *L 0 *C 548.470 652.800 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] 0.0005806514 +1 sb_1__1_:top_left_grid_pin_38_[0] 0.0005806514 +2 grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_36_lower[0] 6.578679e-05 +3 sb_1__1_:top_left_grid_pin_38_[0] sb_1__1_:top_left_grid_pin_36_[0] 6.578679e-05 +4 grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] 0.0001056522 +5 sb_1__1_:top_left_grid_pin_38_[0] sb_1__1_:top_left_grid_pin_39_[0] 0.0001056522 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] sb_1__1_:top_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_1_right_width_0_height_0__pin_39_lower[0] 0.001544239 //LENGTH 7.660 LUMPCC 0.0004226087 DR + +*CONN +*I grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] O *L 0 *C 540.810 651.440 +*I sb_1__1_:top_left_grid_pin_39_[0] I *L 0 *C 548.470 651.440 + +*CAP +0 grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] 0.000560815 +1 sb_1__1_:top_left_grid_pin_39_[0] 0.000560815 +2 grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_38_lower[0] 0.0001056522 +3 sb_1__1_:top_left_grid_pin_39_[0] sb_1__1_:top_left_grid_pin_38_[0] 0.0001056522 +4 grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] grid_clb_1__2_:right_width_0_height_0__pin_40_lower[0] 0.0001056522 +5 sb_1__1_:top_left_grid_pin_39_[0] sb_1__1_:top_left_grid_pin_40_[0] 0.0001056522 + +*RES +0 grid_clb_1__2_:right_width_0_height_0__pin_39_lower[0] sb_1__1_:top_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_46_lower[0] 0.001101814 //LENGTH 11.020 LUMPCC 0.0003164089 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_46_lower[0] O *L 0 *C 783.380 380.870 +*I sb_2__0_:left_top_grid_pin_46_[0] I *L 0 *C 783.380 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_46_lower[0] 0.0003927026 +1 sb_2__0_:left_top_grid_pin_46_[0] 0.0003927026 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_46_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0001582045 +3 sb_2__0_:left_top_grid_pin_46_[0] sb_2__0_:left_top_grid_pin_47_[0] 0.0001582045 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_46_lower[0] sb_2__0_:left_top_grid_pin_46_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_47_lower[0] 0.001245896 //LENGTH 11.020 LUMPCC 0.0006078543 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] O *L 0 *C 784.300 380.870 +*I sb_2__0_:left_top_grid_pin_47_[0] I *L 0 *C 784.300 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] 0.0003190209 +1 sb_2__0_:left_top_grid_pin_47_[0] 0.0003190209 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_44_lower[0] 0.0001457227 +3 sb_2__0_:left_top_grid_pin_47_[0] sb_2__0_:left_top_grid_pin_44_[0] 0.0001457227 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_2__1_:bottom_width_0_height_0__pin_46_lower[0] 0.0001582045 +5 sb_2__0_:left_top_grid_pin_47_[0] sb_2__0_:left_top_grid_pin_46_[0] 0.0001582045 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_47_lower[0] sb_2__0_:left_top_grid_pin_47_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_bottom_width_0_height_0__pin_49_upper[0] 0.001252426 //LENGTH 11.020 LUMPCC 0.0005678821 DR + +*CONN +*I grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] O *L 0 *C 656.420 380.870 +*I sb_1__0_:right_top_grid_pin_49_[0] I *L 0 *C 656.420 369.850 + +*CAP +0 grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] 0.000342272 +1 sb_1__0_:right_top_grid_pin_49_[0] 0.000342272 +2 grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_45_upper[0] 0.0001419705 +3 sb_1__0_:right_top_grid_pin_49_[0] sb_1__0_:right_top_grid_pin_45_[0] 0.0001419705 +4 grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_2__1_:bottom_width_0_height_0__pin_48_upper[0] 0.0001419705 +5 sb_1__0_:right_top_grid_pin_49_[0] sb_1__0_:right_top_grid_pin_48_[0] 0.0001419705 + +*RES +0 grid_clb_2__1_:bottom_width_0_height_0__pin_49_upper[0] sb_1__0_:right_top_grid_pin_49_[0] 0.009839286 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_35_upper[0] 0.00115444 //LENGTH 7.660 LUMPCC 0.0005911402 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] O *L 0 *C 802.090 535.840 +*I sb_2__1_:bottom_left_grid_pin_35_[0] I *L 0 *C 809.750 535.840 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] 0.0002816498 +1 sb_2__1_:bottom_left_grid_pin_35_[0] 0.0002816498 +2 grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_34_upper[0] 0.0001141139 +3 sb_2__1_:bottom_left_grid_pin_35_[0] sb_2__1_:bottom_left_grid_pin_34_[0] 0.0001141139 +4 grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] 0.0001814562 +5 sb_2__1_:bottom_left_grid_pin_35_[0] sb_2__1_:bottom_left_grid_pin_36_[0] 0.0001814562 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_35_upper[0] sb_2__1_:bottom_left_grid_pin_35_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_38_upper[0] 0.001152265 //LENGTH 7.660 LUMPCC 0.0005814431 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] O *L 0 *C 802.090 532.440 +*I sb_2__1_:bottom_left_grid_pin_38_[0] I *L 0 *C 809.750 532.440 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] 0.0002854111 +1 sb_2__1_:bottom_left_grid_pin_38_[0] 0.0002854111 +2 grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_36_upper[0] 0.0001114781 +3 sb_2__1_:bottom_left_grid_pin_38_[0] sb_2__1_:bottom_left_grid_pin_36_[0] 0.0001114781 +4 grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] 0.0001792434 +5 sb_2__1_:bottom_left_grid_pin_38_[0] sb_2__1_:bottom_left_grid_pin_37_[0] 0.0001792434 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_38_upper[0] sb_2__1_:bottom_left_grid_pin_38_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_39_lower[0] 0.00120055 //LENGTH 7.660 LUMPCC 0.0007452688 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] O *L 0 *C 802.090 390.320 +*I sb_2__0_:top_left_grid_pin_39_[0] I *L 0 *C 809.750 390.320 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] 0.0002276405 +1 sb_2__0_:top_left_grid_pin_39_[0] 0.0002276405 +2 grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_38_lower[0] 0.0001880573 +3 sb_2__0_:top_left_grid_pin_39_[0] sb_2__0_:top_left_grid_pin_38_[0] 0.0001880573 +4 grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] grid_clb_2__1_:right_width_0_height_0__pin_40_lower[0] 0.000184577 +5 sb_2__0_:top_left_grid_pin_39_[0] sb_2__0_:top_left_grid_pin_40_[0] 0.000184577 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_39_lower[0] sb_2__0_:top_left_grid_pin_39_[0] 0.001200067 + +*END + +*D_NET grid_clb_2_right_width_0_height_0__pin_41_upper[0] 0.002326888 //LENGTH 20.600 LUMPCC 0.0005820135 DR + +*CONN +*I grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] O *L 0 *C 802.090 529.720 +*I sb_2__1_:bottom_left_grid_pin_41_[0] I *L 0 *C 809.750 541.960 +*N grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 *C 806.388 541.960 +*N grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 *C 806.380 541.903 +*N grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 *C 806.380 529.778 +*N grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 *C 806.373 529.720 + +*CAP +0 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] 0.0001253148 +1 sb_2__1_:bottom_left_grid_pin_41_[0] 0.0002362058 +2 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 0.0002362058 +3 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 0.0005109163 +4 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 0.0005109163 +5 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 0.0001253148 +6 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] Test_en[0]:57 1.831939e-05 +7 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] Test_en[0]:61 1.348515e-05 +8 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 Test_en[0]:55 2.577347e-05 +9 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 Test_en[0]:56 2.577347e-05 +10 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 Test_en[0]:61 1.831939e-05 +11 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 Test_en[0]:62 1.348515e-05 +12 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] grid_clb_2__1_:right_width_0_height_0__pin_37_upper[0] 0.0001187201 +13 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 sb_2__1_:bottom_left_grid_pin_37_[0] 0.0001187201 +14 sb_2__1_:bottom_left_grid_pin_41_[0] sb_2__1_:bottom_left_grid_pin_40_[0] 6.778097e-05 +15 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 grid_clb_2__1_:right_width_0_height_0__pin_40_upper[0] 6.778097e-05 +16 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 ctsbuf_net_110:18 4.692768e-05 +17 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 ctsbuf_net_110:17 4.692768e-05 + +*RES +0 grid_clb_2__1_:right_width_0_height_0__pin_41_upper[0] grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 0.000670925 +1 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 0.00341 +2 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:2 sb_2__1_:bottom_left_grid_pin_41_[0] 0.0005267917 +3 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:3 0.01082589 +4 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:5 grid_clb_2_right_width_0_height_0__pin_41_upper[0]:4 0.00341 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_44_lower[0] 0.001254075 //LENGTH 11.020 LUMPCC 0.0005586683 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] O *L 0 *C 785.220 641.990 +*I sb_2__1_:left_top_grid_pin_44_[0] I *L 0 *C 785.220 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0003477031 +1 sb_2__1_:left_top_grid_pin_44_[0] 0.0003477031 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_45_lower[0] 0.0001396671 +3 sb_2__1_:left_top_grid_pin_44_[0] sb_2__1_:left_top_grid_pin_45_[0] 0.0001396671 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0001396671 +5 sb_2__1_:left_top_grid_pin_44_[0] sb_2__1_:left_top_grid_pin_47_[0] 0.0001396671 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] sb_2__1_:left_top_grid_pin_44_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_47_lower[0] 0.001254095 //LENGTH 11.020 LUMPCC 0.0005640737 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] O *L 0 *C 784.300 641.990 +*I sb_2__1_:left_top_grid_pin_47_[0] I *L 0 *C 784.300 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] 0.0003450105 +1 sb_2__1_:left_top_grid_pin_47_[0] 0.0003450105 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_44_lower[0] 0.0001396671 +3 sb_2__1_:left_top_grid_pin_47_[0] sb_2__1_:left_top_grid_pin_44_[0] 0.0001396671 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_46_lower[0] 0.0001423698 +5 sb_2__1_:left_top_grid_pin_47_[0] sb_2__1_:left_top_grid_pin_46_[0] 0.0001423698 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_47_lower[0] sb_2__1_:left_top_grid_pin_47_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_bottom_width_0_height_0__pin_49_upper[0] 0.001254207 //LENGTH 11.020 LUMPCC 0.0005577554 DR + +*CONN +*I grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] O *L 0 *C 656.420 641.990 +*I sb_1__1_:right_top_grid_pin_49_[0] I *L 0 *C 656.420 630.970 + +*CAP +0 grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] 0.0003482259 +1 sb_1__1_:right_top_grid_pin_49_[0] 0.0003482259 +2 grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_45_upper[0] 0.0001394388 +3 sb_1__1_:right_top_grid_pin_49_[0] sb_1__1_:right_top_grid_pin_45_[0] 0.0001394388 +4 grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] grid_clb_2__2_:bottom_width_0_height_0__pin_48_upper[0] 0.0001394388 +5 sb_1__1_:right_top_grid_pin_49_[0] sb_1__1_:right_top_grid_pin_48_[0] 0.0001394388 + +*RES +0 grid_clb_2__2_:bottom_width_0_height_0__pin_49_upper[0] sb_1__1_:right_top_grid_pin_49_[0] 0.009839285 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_35_upper[0] 0.001243277 //LENGTH 7.660 LUMPCC 0.0005000116 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] O *L 0 *C 802.090 796.960 +*I sb_2__2_:bottom_left_grid_pin_35_[0] I *L 0 *C 809.750 796.960 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] 0.0003716328 +1 sb_2__2_:bottom_left_grid_pin_35_[0] 0.0003716328 +2 grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_34_upper[0] 8.998787e-05 +3 sb_2__2_:bottom_left_grid_pin_35_[0] sb_2__2_:bottom_left_grid_pin_34_[0] 8.998787e-05 +4 grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] grid_clb_2__2_:right_width_0_height_0__pin_36_upper[0] 0.000160018 +5 sb_2__2_:bottom_left_grid_pin_35_[0] sb_2__2_:bottom_left_grid_pin_36_[0] 0.000160018 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_35_upper[0] sb_2__2_:bottom_left_grid_pin_35_[0] 0.001200067 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_37_lower[0] 0.002368738 //LENGTH 22.670 LUMPCC 0.000311843 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_37_lower[0] O *L 0 *C 802.090 669.120 +*I sb_2__1_:top_left_grid_pin_37_[0] I *L 0 *C 812.820 658.170 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 *C 812.820 659.215 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:3 *C 812.775 659.260 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:4 *C 807.345 659.260 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:5 *C 807.300 659.305 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:6 *C 807.300 667.519 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:7 *C 807.300 667.520 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:8 *C 807.300 669.062 +*N grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 *C 807.293 669.120 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_37_lower[0] 0.0002014375 +1 sb_2__1_:top_left_grid_pin_37_[0] 6.324321e-05 +2 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 6.324321e-05 +3 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:3 0.0002955975 +4 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:4 0.0002955975 +5 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:5 0.0003813751 +6 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:6 0.0003813751 +7 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:7 8.679448e-05 +8 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:8 8.679448e-05 +9 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 0.0002014375 +10 grid_clb_2__2_:right_width_0_height_0__pin_37_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_34_lower[0] 0.0001409002 +11 sb_2__1_:top_left_grid_pin_37_[0] sb_2__1_:top_left_grid_pin_34_[0] 1.502129e-05 +12 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:2 1.502129e-05 +13 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 grid_clb_3_right_width_0_height_0__pin_34_lower[0]:5 0.0001409002 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_37_lower[0] grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 0.0008150583 +1 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:3 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 0.0045 +2 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:2 sb_2__1_:top_left_grid_pin_37_[0] 0.0009330357 +3 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:4 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:3 0.004848214 +4 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:5 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:4 0.0045 +5 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:8 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:7 0.001377232 +6 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:9 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:8 0.00341 +7 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:7 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:6 1e-05 +8 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:6 grid_clb_3_right_width_0_height_0__pin_37_lower[0]:5 0.007333929 + +*END + +*D_NET grid_clb_3_right_width_0_height_0__pin_40_lower[0] 0.001107802 //LENGTH 7.660 LUMPCC 0.0004632341 DR + +*CONN +*I grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] O *L 0 *C 802.090 650.080 +*I sb_2__1_:top_left_grid_pin_40_[0] I *L 0 *C 809.750 650.080 + +*CAP +0 grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] 0.000322284 +1 sb_2__1_:top_left_grid_pin_40_[0] 0.000322284 +2 grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] grid_clb_2__2_:bottom_width_0_height_0__pin_43_lower[0] 4.805342e-05 +3 sb_2__1_:top_left_grid_pin_40_[0] sb_2__1_:left_top_grid_pin_43_[0] 4.805342e-05 +4 grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] grid_clb_2__2_:right_width_0_height_0__pin_39_lower[0] 0.0001835637 +5 sb_2__1_:top_left_grid_pin_40_[0] sb_2__1_:top_left_grid_pin_39_[0] 0.0001835637 + +*RES +0 grid_clb_2__2_:right_width_0_height_0__pin_40_lower[0] sb_2__1_:top_left_grid_pin_40_[0] 0.001200067 + +*END + +*D_NET grid_io_bottom_0_ccff_tail[0] 0.004556174 //LENGTH 46.160 LUMPCC 9.742071e-05 DR + +*CONN +*I grid_io_bottom_1__0_:ccff_tail[0] O *L 0 *C 432.400 282.810 +*I sb_0__0_:ccff_head[0] I *L 0 *C 397.900 293.830 +*N grid_io_bottom_0_ccff_tail[0]:2 *C 397.900 289.385 +*N grid_io_bottom_0_ccff_tail[0]:3 *C 397.945 289.340 +*N grid_io_bottom_0_ccff_tail[0]:4 *C 432.355 289.340 +*N grid_io_bottom_0_ccff_tail[0]:5 *C 432.400 289.295 + +*CAP +0 grid_io_bottom_1__0_:ccff_tail[0] 0.0003062138 +1 sb_0__0_:ccff_head[0] 0.0002196248 +2 grid_io_bottom_0_ccff_tail[0]:2 0.0002196248 +3 grid_io_bottom_0_ccff_tail[0]:3 0.001703538 +4 grid_io_bottom_0_ccff_tail[0]:4 0.001703538 +5 grid_io_bottom_0_ccff_tail[0]:5 0.0003062138 +6 sb_0__0_:ccff_head[0] sb_0__0_:right_bottom_grid_pin_1_[0] 4.871036e-05 +7 grid_io_bottom_0_ccff_tail[0]:2 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 4.871036e-05 + +*RES +0 grid_io_bottom_1__0_:ccff_tail[0] grid_io_bottom_0_ccff_tail[0]:5 0.005790179 +1 grid_io_bottom_0_ccff_tail[0]:3 grid_io_bottom_0_ccff_tail[0]:2 0.0045 +2 grid_io_bottom_0_ccff_tail[0]:2 sb_0__0_:ccff_head[0] 0.00396875 +3 grid_io_bottom_0_ccff_tail[0]:4 grid_io_bottom_0_ccff_tail[0]:3 0.03072322 +4 grid_io_bottom_0_ccff_tail[0]:5 grid_io_bottom_0_ccff_tail[0]:4 0.0045 + +*END + +*D_NET grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0] 0.00258152 //LENGTH 25.460 LUMPCC 9.742071e-05 DR + +*CONN +*I grid_io_bottom_1__0_:top_width_0_height_0__pin_1_upper[0] O *L 0 *C 410.780 282.810 +*I sb_0__0_:right_bottom_grid_pin_1_[0] I *L 0 *C 396.980 293.830 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 *C 396.980 286.665 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:3 *C 397.025 286.620 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:4 *C 410.735 286.620 +*N grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:5 *C 410.780 286.575 + +*CAP +0 grid_io_bottom_1__0_:top_width_0_height_0__pin_1_upper[0] 0.0002011474 +1 sb_0__0_:right_bottom_grid_pin_1_[0] 0.0003419508 +2 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 0.0003419508 +3 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:3 0.0006989511 +4 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:4 0.0006989511 +5 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:5 0.0002011474 +6 sb_0__0_:right_bottom_grid_pin_1_[0] sb_0__0_:ccff_head[0] 4.871036e-05 +7 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 grid_io_bottom_0_ccff_tail[0]:2 4.871036e-05 + +*RES +0 grid_io_bottom_1__0_:top_width_0_height_0__pin_1_upper[0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:5 0.003361607 +1 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:3 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 0.0045 +2 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:2 sb_0__0_:right_bottom_grid_pin_1_[0] 0.006397322 +3 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:4 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:3 0.01224107 +4 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:5 grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]:4 0.0045 + +*END + +*D_NET grid_io_left_1_ccff_tail[0] 0.002660543 //LENGTH 24.385 LUMPCC 0.0005041305 DR + +*CONN +*I grid_io_left_0__2_:ccff_tail[0] O *L 0 *C 274.010 767.040 +*I ropt_h_inst_7757:A I *L 0.001746 *C 281.980 782.000 +*N grid_io_left_1_ccff_tail[0]:2 *C 281.942 782.000 +*N grid_io_left_1_ccff_tail[0]:3 *C 281.565 782.000 +*N grid_io_left_1_ccff_tail[0]:4 *C 281.520 781.955 +*N grid_io_left_1_ccff_tail[0]:5 *C 281.520 781.365 +*N grid_io_left_1_ccff_tail[0]:6 *C 281.475 781.320 +*N grid_io_left_1_ccff_tail[0]:7 *C 280.185 781.320 +*N grid_io_left_1_ccff_tail[0]:8 *C 280.140 781.275 +*N grid_io_left_1_ccff_tail[0]:9 *C 280.140 767.098 +*N grid_io_left_1_ccff_tail[0]:10 *C 280.132 767.040 + +*CAP +0 grid_io_left_0__2_:ccff_tail[0] 0.000292048 +1 ropt_h_inst_7757:A 1e-06 +2 grid_io_left_1_ccff_tail[0]:2 5.985149e-05 +3 grid_io_left_1_ccff_tail[0]:3 5.985149e-05 +4 grid_io_left_1_ccff_tail[0]:4 4.336855e-05 +5 grid_io_left_1_ccff_tail[0]:5 4.336855e-05 +6 grid_io_left_1_ccff_tail[0]:6 0.0001101853 +7 grid_io_left_1_ccff_tail[0]:7 0.0001101853 +8 grid_io_left_1_ccff_tail[0]:8 0.000572253 +9 grid_io_left_1_ccff_tail[0]:9 0.000572253 +10 grid_io_left_1_ccff_tail[0]:10 0.000292048 +11 grid_io_left_0__2_:ccff_tail[0] grid_io_left_0__2_:right_width_0_height_0__pin_0_[0] 0.000140793 +12 grid_io_left_1_ccff_tail[0]:10 cby_0__2_:left_grid_pin_0_[0] 0.000140793 +13 grid_io_left_1_ccff_tail[0]:4 ctsbuf_net_514:22 2.605602e-05 +14 grid_io_left_1_ccff_tail[0]:5 ctsbuf_net_514:23 2.605602e-05 +15 grid_io_left_1_ccff_tail[0]:8 ctsbuf_net_514:22 8.521618e-05 +16 grid_io_left_1_ccff_tail[0]:9 ctsbuf_net_514:23 8.521618e-05 + +*RES +0 grid_io_left_0__2_:ccff_tail[0] grid_io_left_1_ccff_tail[0]:10 0.0009591916 +1 grid_io_left_1_ccff_tail[0]:2 ropt_h_inst_7757:A 0.152 +2 grid_io_left_1_ccff_tail[0]:3 grid_io_left_1_ccff_tail[0]:2 0.0003370536 +3 grid_io_left_1_ccff_tail[0]:4 grid_io_left_1_ccff_tail[0]:3 0.0045 +4 grid_io_left_1_ccff_tail[0]:6 grid_io_left_1_ccff_tail[0]:5 0.0045 +5 grid_io_left_1_ccff_tail[0]:5 grid_io_left_1_ccff_tail[0]:4 0.0005267857 +6 grid_io_left_1_ccff_tail[0]:7 grid_io_left_1_ccff_tail[0]:6 0.001151786 +7 grid_io_left_1_ccff_tail[0]:8 grid_io_left_1_ccff_tail[0]:7 0.0045 +8 grid_io_left_1_ccff_tail[0]:9 grid_io_left_1_ccff_tail[0]:8 0.01265848 +9 grid_io_left_1_ccff_tail[0]:10 grid_io_left_1_ccff_tail[0]:9 0.00341 + +*END + +*D_NET grid_io_right_0_left_width_0_height_0__pin_1_lower[0] 0.002794871 //LENGTH 29.200 LUMPCC 0.0005874346 DR + +*CONN +*I grid_io_right_3__1_:left_width_0_height_0__pin_1_lower[0] O *L 0 *C 909.420 408.070 +*I sb_2__0_:top_right_grid_pin_1_[0] I *L 0 *C 891.940 397.050 +*N grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:2 *C 891.940 399.103 +*N grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 *C 891.947 399.160 +*N grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 *C 909.413 399.160 +*N grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 *C 909.420 399.218 + +*CAP +0 grid_io_right_3__1_:left_width_0_height_0__pin_1_lower[0] 0.0003696304 +1 sb_2__0_:top_right_grid_pin_1_[0] 0.0001523831 +2 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:2 0.0001523831 +3 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 0.0005817045 +4 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 0.0005817045 +5 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 0.0003696304 +6 grid_io_right_3__1_:left_width_0_height_0__pin_1_lower[0] grid_io_right_3__1_:prog_clk[0] 4.573536e-05 +7 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 ctsbuf_net_110:8 0.000247982 +8 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 ctsbuf_net_110:6 4.573536e-05 +9 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 ctsbuf_net_110:7 0.000247982 + +*RES +0 grid_io_right_3__1_:left_width_0_height_0__pin_1_lower[0] grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 0.007904018 +1 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:2 sb_2__0_:top_right_grid_pin_1_[0] 0.001832589 +2 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:2 0.00341 +3 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:5 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 0.00341 +4 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:4 grid_io_right_0_left_width_0_height_0__pin_1_lower[0]:3 0.002736183 + +*END + +*D_NET grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0] 0.002995363 //LENGTH 28.830 LUMPCC 0.001024208 DR + +*CONN +*I grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] O *L 0 *C 407.710 909.840 +*I sb_0__2_:right_top_grid_pin_1_[0] I *L 0 *C 396.980 892.090 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 *C 396.980 909.783 +*N grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 *C 396.988 909.840 + +*CAP +0 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] 0.0003520804 +1 sb_0__2_:right_top_grid_pin_1_[0] 0.0006334968 +2 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 0.0006334968 +3 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 0.0003520804 +4 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] grid_io_top_1__3_:ccff_tail[0] 0.0002573924 +5 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 grid_io_top_0_ccff_tail[0]:6 0.0002573924 +6 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] ropt_net_38:4 8.297387e-06 +7 sb_0__2_:right_top_grid_pin_1_[0] sb_0__2_:ccff_head[0] 0.0002464143 +8 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 ropt_net_38:2 0.0002464143 +9 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 ropt_net_38:3 8.297387e-06 + +*RES +0 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 0.001679858 +1 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 sb_0__2_:right_top_grid_pin_1_[0] 0.01579688 +2 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 0.00341 + +*END + +*D_NET sb_0__0__0_chanx_right_out[0] 0.003892429 //LENGTH 30.900 LUMPCC 0.0005034888 DR + +*CONN +*I sb_0__0_:chanx_right_out[0] O *L 0 *C 400.050 353.600 +*I cbx_1__0_:chanx_left_in[0] I *L 0 *C 410.780 369.850 +*N sb_0__0__0_chanx_right_out[0]:2 *C 410.780 371.223 +*N sb_0__0__0_chanx_right_out[0]:3 *C 410.773 371.280 +*N sb_0__0__0_chanx_right_out[0]:4 *C 405.740 371.280 +*N sb_0__0__0_chanx_right_out[0]:5 *C 405.720 371.273 +*N sb_0__0__0_chanx_right_out[0]:6 *C 405.720 353.608 +*N sb_0__0__0_chanx_right_out[0]:7 *C 405.700 353.600 + +*CAP +0 sb_0__0_:chanx_right_out[0] 0.0002290569 +1 cbx_1__0_:chanx_left_in[0] 0.0001186062 +2 sb_0__0__0_chanx_right_out[0]:2 0.0001186062 +3 sb_0__0__0_chanx_right_out[0]:3 0.0003600232 +4 sb_0__0__0_chanx_right_out[0]:4 0.0003600232 +5 sb_0__0__0_chanx_right_out[0]:5 0.000986784 +6 sb_0__0__0_chanx_right_out[0]:6 0.000986784 +7 sb_0__0__0_chanx_right_out[0]:7 0.0002290569 +8 sb_0__0_:chanx_right_out[0] sb_0__0_:chanx_right_in[19] 0.0001258722 +9 sb_0__0__0_chanx_right_out[0]:7 cbx_1__0_:chanx_left_out[19] 0.0001258722 +10 sb_0__0_:chanx_right_out[0] sb_0__0_:chanx_right_out[13] 0.0001258722 +11 sb_0__0__0_chanx_right_out[0]:7 cbx_1__0_:chanx_left_in[13] 0.0001258722 + +*RES +0 sb_0__0_:chanx_right_out[0] sb_0__0__0_chanx_right_out[0]:7 0.0008851667 +1 sb_0__0__0_chanx_right_out[0]:2 cbx_1__0_:chanx_left_in[0] 0.001225446 +2 sb_0__0__0_chanx_right_out[0]:3 sb_0__0__0_chanx_right_out[0]:2 0.00341 +3 sb_0__0__0_chanx_right_out[0]:4 sb_0__0__0_chanx_right_out[0]:3 0.000788425 +4 sb_0__0__0_chanx_right_out[0]:5 sb_0__0__0_chanx_right_out[0]:4 0.00341 +5 sb_0__0__0_chanx_right_out[0]:7 sb_0__0__0_chanx_right_out[0]:6 0.00341 +6 sb_0__0__0_chanx_right_out[0]:6 sb_0__0__0_chanx_right_out[0]:5 0.002767517 + +*END + +*D_NET sb_0__0__0_chanx_right_out[7] 0.001256702 //LENGTH 7.660 LUMPCC 0.000693163 DR + +*CONN +*I sb_0__0_:chanx_right_out[7] O *L 0 *C 400.050 345.440 +*I cbx_1__0_:chanx_left_in[7] I *L 0 *C 407.710 345.440 + +*CAP +0 sb_0__0_:chanx_right_out[7] 0.0002817695 +1 cbx_1__0_:chanx_left_in[7] 0.0002817695 +2 sb_0__0_:chanx_right_out[7] sb_0__0_:chanx_right_in[18] 0.000174397 +3 cbx_1__0_:chanx_left_in[7] cbx_1__0_:chanx_left_out[18] 0.000174397 +4 sb_0__0_:chanx_right_out[7] sb_0__0_:chanx_right_out[19] 0.0001721845 +5 cbx_1__0_:chanx_left_in[7] cbx_1__0_:chanx_left_in[19] 0.0001721845 + +*RES +0 sb_0__0_:chanx_right_out[7] cbx_1__0_:chanx_left_in[7] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[12] 0.001214625 //LENGTH 7.660 LUMPCC 0.0004510751 DR + +*CONN +*I sb_0__0_:chanx_right_out[12] O *L 0 *C 400.050 363.120 +*I cbx_1__0_:chanx_left_in[12] I *L 0 *C 407.710 363.120 + +*CAP +0 sb_0__0_:chanx_right_out[12] 0.0003817747 +1 cbx_1__0_:chanx_left_in[12] 0.0003817747 +2 sb_0__0_:chanx_right_out[12] sb_0__0_:chanx_right_in[9] 6.347717e-05 +3 cbx_1__0_:chanx_left_in[12] cbx_1__0_:chanx_left_out[9] 6.347717e-05 +4 sb_0__0_:chanx_right_out[12] sb_0__0_:chanx_right_out[3] 0.0001620604 +5 cbx_1__0_:chanx_left_in[12] cbx_1__0_:chanx_left_in[3] 0.0001620604 + +*RES +0 sb_0__0_:chanx_right_out[12] cbx_1__0_:chanx_left_in[12] 0.001200067 + +*END + +*D_NET sb_0__0__0_chanx_right_out[17] 0.00129007 //LENGTH 7.660 LUMPCC 0.0006580718 DR + +*CONN +*I sb_0__0_:chanx_right_out[17] O *L 0 *C 400.050 356.320 +*I cbx_1__0_:chanx_left_in[17] I *L 0 *C 407.710 356.320 + +*CAP +0 sb_0__0_:chanx_right_out[17] 0.0003159989 +1 cbx_1__0_:chanx_left_in[17] 0.0003159989 +2 sb_0__0_:chanx_right_out[17] sb_0__0_:chanx_right_in[17] 0.000164518 +3 cbx_1__0_:chanx_left_in[17] cbx_1__0_:chanx_left_out[17] 0.000164518 +4 sb_0__0_:chanx_right_out[17] sb_0__0_:chanx_right_out[13] 0.000164518 +5 cbx_1__0_:chanx_left_in[17] cbx_1__0_:chanx_left_in[13] 0.000164518 + +*RES +0 sb_0__0_:chanx_right_out[17] cbx_1__0_:chanx_left_in[17] 0.001200067 + +*END + +*D_NET sb_0__0__0_chany_top_out[1] 0.001044745 //LENGTH 11.020 LUMPCC 0.0001856165 DR + +*CONN +*I sb_0__0_:chany_top_out[1] O *L 0 *C 312.800 397.050 +*I cby_0__1_:chany_bottom_in[1] I *L 0 *C 312.800 408.070 + +*CAP +0 sb_0__0_:chany_top_out[1] 0.0004295642 +1 cby_0__1_:chany_bottom_in[1] 0.0004295642 +2 sb_0__0_:chany_top_out[1] sb_0__0_:chany_top_in[5] 2.696987e-05 +3 cby_0__1_:chany_bottom_in[1] cby_0__1_:chany_bottom_out[5] 2.696987e-05 +4 sb_0__0_:chany_top_out[1] sb_0__0_:chany_top_out[19] 6.58384e-05 +5 cby_0__1_:chany_bottom_in[1] cby_0__1_:chany_bottom_in[19] 6.58384e-05 + +*RES +0 sb_0__0_:chany_top_out[1] cby_0__1_:chany_bottom_in[1] 0.009839285 + +*END + +*D_NET sb_0__0__0_chany_top_out[6] 0.001392691 //LENGTH 11.180 LUMPCC 0.0004356003 DR + +*CONN +*I sb_0__0_:chany_top_out[6] O *L 0 *C 292.560 396.970 +*I cby_0__1_:chany_bottom_in[6] I *L 0 *C 292.560 408.150 + +*CAP +0 sb_0__0_:chany_top_out[6] 0.0004785454 +1 cby_0__1_:chany_bottom_in[6] 0.0004785454 +2 sb_0__0_:chany_top_out[6] sb_0__0_:chany_top_out[14] 0.0002178002 +3 cby_0__1_:chany_bottom_in[6] cby_0__1_:chany_bottom_in[14] 0.0002178002 + +*RES +0 sb_0__0_:chany_top_out[6] cby_0__1_:chany_bottom_in[6] 0.001751533 + +*END + +*D_NET sb_0__0__0_chany_top_out[10] 0.001245328 //LENGTH 11.020 LUMPCC 0.0005902692 DR + +*CONN +*I sb_0__0_:chany_top_out[10] O *L 0 *C 333.500 397.050 +*I cby_0__1_:chany_bottom_in[10] I *L 0 *C 333.500 408.070 + +*CAP +0 sb_0__0_:chany_top_out[10] 0.0003275294 +1 cby_0__1_:chany_bottom_in[10] 0.0003275294 +2 sb_0__0_:chany_top_out[10] sb_0__0_:chany_top_in[3] 0.000146964 +3 cby_0__1_:chany_bottom_in[10] cby_0__1_:chany_bottom_out[3] 0.000146964 +4 sb_0__0_:chany_top_out[10] sb_0__0_:chany_top_in[19] 0.0001481706 +5 cby_0__1_:chany_bottom_in[10] cby_0__1_:chany_bottom_out[19] 0.0001481706 + +*RES +0 sb_0__0_:chany_top_out[10] cby_0__1_:chany_bottom_in[10] 0.009839286 + +*END + +*D_NET sb_0__0__0_chany_top_out[17] 0.001135643 //LENGTH 11.020 LUMPCC 0.0003039602 DR + +*CONN +*I sb_0__0_:chany_top_out[17] O *L 0 *C 339.940 397.050 +*I cby_0__1_:chany_bottom_in[17] I *L 0 *C 339.940 408.070 + +*CAP +0 sb_0__0_:chany_top_out[17] 0.0004158413 +1 cby_0__1_:chany_bottom_in[17] 0.0004158413 +2 sb_0__0_:chany_top_out[17] sb_0__0_:chany_top_in[9] 0.0001519801 +3 cby_0__1_:chany_bottom_in[17] cby_0__1_:chany_bottom_out[9] 0.0001519801 + +*RES +0 sb_0__0_:chany_top_out[17] cby_0__1_:chany_bottom_in[17] 0.009839285 + +*END + +*D_NET sb_0__1__0_ccff_tail[0] 0.001204415 //LENGTH 11.020 LUMPCC 0.0001414711 DR + +*CONN +*I sb_0__1_:ccff_tail[0] O *L 0 *C 341.320 527.750 +*I cby_0__1_:ccff_head[0] I *L 0 *C 341.320 516.730 + +*CAP +0 sb_0__1_:ccff_tail[0] 0.0005314719 +1 cby_0__1_:ccff_head[0] 0.0005314719 +2 sb_0__1_:ccff_tail[0] sb_0__1_:chany_bottom_in[6] 7.073553e-05 +3 cby_0__1_:ccff_head[0] cby_0__1_:chany_top_out[6] 7.073553e-05 + +*RES +0 sb_0__1_:ccff_tail[0] cby_0__1_:ccff_head[0] 0.009839286 + +*END + +*D_NET sb_0__1__0_chanx_right_out[3] 0.001113653 //LENGTH 7.660 LUMPCC 0.0002967386 DR + +*CONN +*I sb_0__1_:chanx_right_out[3] O *L 0 *C 400.050 601.800 +*I cbx_1__1_:chanx_left_in[3] I *L 0 *C 407.710 601.800 + +*CAP +0 sb_0__1_:chanx_right_out[3] 0.0004084573 +1 cbx_1__1_:chanx_left_in[3] 0.0004084573 +2 sb_0__1_:chanx_right_out[3] sb_0__1_:chanx_right_in[6] 4.478417e-05 +3 cbx_1__1_:chanx_left_in[3] cbx_1__1_:chanx_left_out[6] 4.478417e-05 +4 sb_0__1_:chanx_right_out[3] sb_0__1_:chanx_right_out[5] 0.0001035851 +5 cbx_1__1_:chanx_left_in[3] cbx_1__1_:chanx_left_in[5] 0.0001035851 + +*RES +0 sb_0__1_:chanx_right_out[3] cbx_1__1_:chanx_left_in[3] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[6] 0.001164823 //LENGTH 7.660 LUMPCC 0.0004755849 DR + +*CONN +*I sb_0__1_:chanx_right_out[6] O *L 0 *C 400.050 586.160 +*I cbx_1__1_:chanx_left_in[6] I *L 0 *C 407.710 586.160 + +*CAP +0 sb_0__1_:chanx_right_out[6] 0.0003446189 +1 cbx_1__1_:chanx_left_in[6] 0.0003446189 +2 sb_0__1_:chanx_right_out[6] sb_0__1_:chanx_right_in[15] 0.0001742478 +3 cbx_1__1_:chanx_left_in[6] cbx_1__1_:chanx_left_out[15] 0.0001742478 +4 sb_0__1_:chanx_right_out[6] sb_0__1_:chanx_right_out[10] 6.354468e-05 +5 cbx_1__1_:chanx_left_in[6] cbx_1__1_:chanx_left_in[10] 6.354468e-05 + +*RES +0 sb_0__1_:chanx_right_out[6] cbx_1__1_:chanx_left_in[6] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[13] 0.001191674 //LENGTH 7.660 LUMPCC 0.0004669066 DR + +*CONN +*I sb_0__1_:chanx_right_out[13] O *L 0 *C 400.050 613.360 +*I cbx_1__1_:chanx_left_in[13] I *L 0 *C 407.710 613.360 + +*CAP +0 sb_0__1_:chanx_right_out[13] 0.0003623839 +1 cbx_1__1_:chanx_left_in[13] 0.0003623839 +2 sb_0__1_:chanx_right_out[13] sb_0__1_:ccff_head[0] 6.118615e-05 +3 cbx_1__1_:chanx_left_in[13] cbx_1__1_:ccff_tail[0] 6.118615e-05 +4 sb_0__1_:chanx_right_out[13] sb_0__1_:chanx_right_out[0] 0.0001722672 +5 cbx_1__1_:chanx_left_in[13] cbx_1__1_:chanx_left_in[0] 0.0001722672 + +*RES +0 sb_0__1_:chanx_right_out[13] cbx_1__1_:chanx_left_in[13] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[15] 0.001272505 //LENGTH 7.660 LUMPCC 0.000687349 DR + +*CONN +*I sb_0__1_:chanx_right_out[15] O *L 0 *C 400.050 595.680 +*I cbx_1__1_:chanx_left_in[15] I *L 0 *C 407.710 595.680 + +*CAP +0 sb_0__1_:chanx_right_out[15] 0.0002925778 +1 cbx_1__1_:chanx_left_in[15] 0.0002925778 +2 sb_0__1_:chanx_right_out[15] sb_0__1_:chanx_right_in[7] 0.0001718373 +3 cbx_1__1_:chanx_left_in[15] cbx_1__1_:chanx_left_out[7] 0.0001718373 +4 sb_0__1_:chanx_right_out[15] sb_0__1_:chanx_right_out[17] 0.0001718373 +5 cbx_1__1_:chanx_left_in[15] cbx_1__1_:chanx_left_in[17] 0.0001718373 + +*RES +0 sb_0__1_:chanx_right_out[15] cbx_1__1_:chanx_left_in[15] 0.001200067 + +*END + +*D_NET sb_0__1__0_chanx_right_out[19] 0.001268088 //LENGTH 7.660 LUMPCC 0.000684042 DR + +*CONN +*I sb_0__1_:chanx_right_out[19] O *L 0 *C 400.050 617.440 +*I cbx_1__1_:chanx_left_in[19] I *L 0 *C 407.710 617.440 + +*CAP +0 sb_0__1_:chanx_right_out[19] 0.0002920231 +1 cbx_1__1_:chanx_left_in[19] 0.0002920231 +2 sb_0__1_:chanx_right_out[19] sb_0__1_:ccff_head[0] 0.0001708996 +3 cbx_1__1_:chanx_left_in[19] cbx_1__1_:ccff_tail[0] 0.0001708996 +4 sb_0__1_:chanx_right_out[19] sb_0__1_:chanx_right_in[14] 0.0001711214 +5 cbx_1__1_:chanx_left_in[19] cbx_1__1_:chanx_left_out[14] 0.0001711214 + +*RES +0 sb_0__1_:chanx_right_out[19] cbx_1__1_:chanx_left_in[19] 0.001200067 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[4] 0.001298334 //LENGTH 11.020 LUMPCC 0.0005061823 DR + +*CONN +*I sb_0__1_:chany_bottom_out[4] O *L 0 *C 338.100 527.750 +*I cby_0__1_:chany_top_in[4] I *L 0 *C 338.100 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[4] 0.0003960756 +1 cby_0__1_:chany_top_in[4] 0.0003960756 +2 sb_0__1_:chany_bottom_out[4] sb_0__1_:chany_bottom_in[10] 0.0001245748 +3 cby_0__1_:chany_top_in[4] cby_0__1_:chany_top_out[10] 0.0001245748 +4 sb_0__1_:chany_bottom_out[4] sb_0__1_:chany_bottom_out[0] 0.0001285164 +5 cby_0__1_:chany_top_in[4] cby_0__1_:chany_top_in[0] 0.0001285164 + +*RES +0 sb_0__1_:chany_bottom_out[4] cby_0__1_:chany_top_in[4] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[10] 0.001287043 //LENGTH 11.020 LUMPCC 0.0005186471 DR + +*CONN +*I sb_0__1_:chany_bottom_out[10] O *L 0 *C 329.820 527.750 +*I cby_0__1_:chany_top_in[10] I *L 0 *C 329.820 516.730 + +*CAP +0 sb_0__1_:chany_bottom_out[10] 0.0003841981 +1 cby_0__1_:chany_top_in[10] 0.0003841981 +2 sb_0__1_:chany_bottom_out[10] sb_0__1_:chany_bottom_in[14] 0.0001296618 +3 cby_0__1_:chany_top_in[10] cby_0__1_:chany_top_out[14] 0.0001296618 +4 sb_0__1_:chany_bottom_out[10] sb_0__1_:chany_bottom_in[16] 0.0001296618 +5 cby_0__1_:chany_top_in[10] cby_0__1_:chany_top_out[16] 0.0001296618 + +*RES +0 sb_0__1_:chany_bottom_out[10] cby_0__1_:chany_top_in[10] 0.009839286 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[14] 0.001444216 //LENGTH 11.180 LUMPCC 0.0002093461 DR + +*CONN +*I sb_0__1_:chany_bottom_out[14] O *L 0 *C 333.040 527.830 +*I cby_0__1_:chany_top_in[14] I *L 0 *C 333.040 516.650 + +*CAP +0 sb_0__1_:chany_bottom_out[14] 0.000617435 +1 cby_0__1_:chany_top_in[14] 0.000617435 +2 sb_0__1_:chany_bottom_out[14] sb_0__1_:chany_bottom_out[15] 0.0001046731 +3 cby_0__1_:chany_top_in[14] cby_0__1_:chany_top_in[15] 0.0001046731 + +*RES +0 sb_0__1_:chany_bottom_out[14] cby_0__1_:chany_top_in[14] 0.001751533 + +*END + +*D_NET sb_0__1__0_chany_bottom_out[18] 0.001420144 //LENGTH 11.180 LUMPCC 0.0002091652 DR + +*CONN +*I sb_0__1_:chany_bottom_out[18] O *L 0 *C 310.960 527.830 +*I cby_0__1_:chany_top_in[18] I *L 0 *C 310.960 516.650 + +*CAP +0 sb_0__1_:chany_bottom_out[18] 0.0006054896 +1 cby_0__1_:chany_top_in[18] 0.0006054896 +2 sb_0__1_:chany_bottom_out[18] sb_0__1_:chany_bottom_out[19] 0.0001045826 +3 cby_0__1_:chany_top_in[18] cby_0__1_:chany_top_in[19] 0.0001045826 + +*RES +0 sb_0__1_:chany_bottom_out[18] cby_0__1_:chany_top_in[18] 0.001751533 + +*END + +*D_NET sb_0__1__0_chany_top_out[0] 0.001245266 //LENGTH 11.020 LUMPCC 0.0005807617 DR + +*CONN +*I sb_0__1_:chany_top_out[0] O *L 0 *C 329.820 658.170 +*I cby_0__2_:chany_bottom_in[0] I *L 0 *C 329.820 669.190 +*N sb_0__1__0_chany_top_out[0]:2 *C 329.820 667.520 +*N sb_0__1__0_chany_top_out[0]:3 *C 329.820 667.519 + +*CAP +0 sb_0__1_:chany_top_out[0] 0.0002213827 +1 cby_0__2_:chany_bottom_in[0] 0.0001108695 +2 sb_0__1__0_chany_top_out[0]:2 0.0001108695 +3 sb_0__1__0_chany_top_out[0]:3 0.0002213827 +4 sb_0__1_:chany_top_out[0] sb_0__1_:chany_top_in[4] 0.0001378419 +5 cby_0__2_:chany_bottom_in[0] cby_0__2_:chany_bottom_out[4] 7.348477e-06 +6 sb_0__1__0_chany_top_out[0]:2 cby_0__1__1_chany_bottom_out[4]:3 7.348477e-06 +7 sb_0__1__0_chany_top_out[0]:3 cby_0__1__1_chany_bottom_out[4]:2 0.0001378419 +8 sb_0__1_:chany_top_out[0] sb_0__1_:chany_top_in[11] 0.0001378419 +9 cby_0__2_:chany_bottom_in[0] cby_0__2_:chany_bottom_out[11] 7.348477e-06 +10 sb_0__1__0_chany_top_out[0]:2 cby_0__1__1_chany_bottom_out[11]:3 7.348477e-06 +11 sb_0__1__0_chany_top_out[0]:3 cby_0__1__1_chany_bottom_out[11]:2 0.0001378419 + +*RES +0 sb_0__1_:chany_top_out[0] sb_0__1__0_chany_top_out[0]:3 0.008347322 +1 sb_0__1__0_chany_top_out[0]:2 cby_0__2_:chany_bottom_in[0] 0.001491072 +2 sb_0__1__0_chany_top_out[0]:3 sb_0__1__0_chany_top_out[0]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[8] 0.001674947 //LENGTH 11.180 LUMPCC 0.0009025202 DR + +*CONN +*I sb_0__1_:chany_top_out[8] O *L 0 *C 309.120 658.090 +*I cby_0__2_:chany_bottom_in[8] I *L 0 *C 309.120 669.270 +*N sb_0__1__0_chany_top_out[8]:2 *C 309.120 667.520 +*N sb_0__1__0_chany_top_out[8]:3 *C 309.120 667.519 + +*CAP +0 sb_0__1_:chany_top_out[8] 0.000170663 +1 cby_0__2_:chany_bottom_in[8] 0.0002155504 +2 sb_0__1__0_chany_top_out[8]:2 0.0002155504 +3 sb_0__1__0_chany_top_out[8]:3 0.000170663 +4 sb_0__1_:chany_top_out[8] sb_0__1_:chany_top_in[13] 0.0002179493 +5 cby_0__2_:chany_bottom_in[8] cby_0__2_:chany_bottom_out[13] 8.965721e-06 +6 sb_0__1__0_chany_top_out[8]:2 cby_0__1__1_chany_bottom_out[13]:3 8.965721e-06 +7 sb_0__1__0_chany_top_out[8]:3 cby_0__1__1_chany_bottom_out[13]:2 0.0002179493 +8 sb_0__1_:chany_top_out[8] sb_0__1_:chany_top_out[13] 0.0002153793 +9 cby_0__2_:chany_bottom_in[8] cby_0__2_:chany_bottom_in[13] 8.965721e-06 +10 sb_0__1__0_chany_top_out[8]:2 sb_0__1__0_chany_top_out[13]:2 8.965721e-06 +11 sb_0__1__0_chany_top_out[8]:3 sb_0__1__0_chany_top_out[13]:3 0.0002153793 + +*RES +0 sb_0__1_:chany_top_out[8] sb_0__1__0_chany_top_out[8]:3 0.00147721 +1 sb_0__1__0_chany_top_out[8]:2 cby_0__2_:chany_bottom_in[8] 0.0002741666 +2 sb_0__1__0_chany_top_out[8]:3 sb_0__1__0_chany_top_out[8]:2 1e-05 + +*END + +*D_NET sb_0__1__0_chany_top_out[13] 0.001681232 //LENGTH 11.180 LUMPCC 0.0008973803 DR + +*CONN +*I sb_0__1_:chany_top_out[13] O *L 0 *C 310.960 658.090 +*I cby_0__2_:chany_bottom_in[13] I *L 0 *C 310.960 669.270 +*N sb_0__1__0_chany_top_out[13]:2 *C 310.960 667.520 +*N sb_0__1__0_chany_top_out[13]:3 *C 310.960 667.519 + +*CAP +0 sb_0__1_:chany_top_out[13] 0.000173233 +1 cby_0__2_:chany_bottom_in[13] 0.0002186927 +2 sb_0__1__0_chany_top_out[13]:2 0.0002186927 +3 sb_0__1__0_chany_top_out[13]:3 0.000173233 +4 sb_0__1_:chany_top_out[13] sb_0__1_:chany_top_out[8] 0.0002153793 +5 cby_0__2_:chany_bottom_in[13] cby_0__2_:chany_bottom_in[8] 8.965721e-06 +6 sb_0__1__0_chany_top_out[13]:2 sb_0__1__0_chany_top_out[8]:2 8.965721e-06 +7 sb_0__1__0_chany_top_out[13]:3 sb_0__1__0_chany_top_out[8]:3 0.0002153793 +8 sb_0__1_:chany_top_out[13] sb_0__1_:chany_top_out[19] 0.0002153793 +9 cby_0__2_:chany_bottom_in[13] cby_0__2_:chany_bottom_in[19] 8.965721e-06 +10 sb_0__1__0_chany_top_out[13]:2 sb_0__1__0_chany_top_out[19]:2 8.965721e-06 +11 sb_0__1__0_chany_top_out[13]:3 sb_0__1__0_chany_top_out[19]:3 0.0002153793 + +*RES +0 sb_0__1_:chany_top_out[13] sb_0__1__0_chany_top_out[13]:3 0.00147721 +1 sb_0__1__0_chany_top_out[13]:2 cby_0__2_:chany_bottom_in[13] 0.0002741666 +2 sb_0__1__0_chany_top_out[13]:3 sb_0__1__0_chany_top_out[13]:2 1e-05 + +*END + +*D_NET sb_0__2__0_ccff_tail[0] 0.001144023 //LENGTH 11.020 LUMPCC 0.0001777527 DR + +*CONN +*I sb_0__2_:ccff_tail[0] O *L 0 *C 341.320 788.870 +*I cby_0__2_:ccff_head[0] I *L 0 *C 341.320 777.850 + +*CAP +0 sb_0__2_:ccff_tail[0] 0.0004831351 +1 cby_0__2_:ccff_head[0] 0.0004831351 +2 sb_0__2_:ccff_tail[0] sb_0__2_:chany_bottom_in[6] 8.887635e-05 +3 cby_0__2_:ccff_head[0] cby_0__2_:chany_top_out[6] 8.887635e-05 + +*RES +0 sb_0__2_:ccff_tail[0] cby_0__2_:ccff_head[0] 0.009839286 + +*END + +*D_NET sb_0__2__0_chanx_right_out[0] 0.001289534 //LENGTH 7.660 LUMPCC 0.0006607355 DR + +*CONN +*I sb_0__2_:chanx_right_out[0] O *L 0 *C 400.050 862.240 +*I cbx_1__2_:chanx_left_in[0] I *L 0 *C 407.710 862.240 + +*CAP +0 sb_0__2_:chanx_right_out[0] 0.000314399 +1 cbx_1__2_:chanx_left_in[0] 0.000314399 +2 sb_0__2_:chanx_right_out[0] sb_0__2_:chanx_right_in[12] 0.0001651839 +3 cbx_1__2_:chanx_left_in[0] cbx_1__2_:chanx_left_out[12] 0.0001651839 +4 sb_0__2_:chanx_right_out[0] sb_0__2_:chanx_right_in[19] 0.0001651839 +5 cbx_1__2_:chanx_left_in[0] cbx_1__2_:chanx_left_out[19] 0.0001651839 + +*RES +0 sb_0__2_:chanx_right_out[0] cbx_1__2_:chanx_left_in[0] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[4] 0.001298427 //LENGTH 7.660 LUMPCC 0.0006522025 DR + +*CONN +*I sb_0__2_:chanx_right_out[4] O *L 0 *C 400.050 867.680 +*I cbx_1__2_:chanx_left_in[4] I *L 0 *C 407.710 867.680 + +*CAP +0 sb_0__2_:chanx_right_out[4] 0.0003231125 +1 cbx_1__2_:chanx_left_in[4] 0.0003231125 +2 sb_0__2_:chanx_right_out[4] sb_0__2_:chanx_right_in[8] 0.0001631615 +3 cbx_1__2_:chanx_left_in[4] cbx_1__2_:chanx_left_out[8] 0.0001631615 +4 sb_0__2_:chanx_right_out[4] sb_0__2_:chanx_right_in[10] 0.0001629397 +5 cbx_1__2_:chanx_left_in[4] cbx_1__2_:chanx_left_out[10] 0.0001629397 + +*RES +0 sb_0__2_:chanx_right_out[4] cbx_1__2_:chanx_left_in[4] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[10] 0.001294214 //LENGTH 7.660 LUMPCC 0.0006552764 DR + +*CONN +*I sb_0__2_:chanx_right_out[10] O *L 0 *C 400.050 840.480 +*I cbx_1__2_:chanx_left_in[10] I *L 0 *C 407.710 840.480 + +*CAP +0 sb_0__2_:chanx_right_out[10] 0.0003194687 +1 cbx_1__2_:chanx_left_in[10] 0.0003194687 +2 sb_0__2_:chanx_right_out[10] sb_0__2_:chanx_right_in[7] 0.0001638191 +3 cbx_1__2_:chanx_left_in[10] cbx_1__2_:chanx_left_out[7] 0.0001638191 +4 sb_0__2_:chanx_right_out[10] sb_0__2_:chanx_right_out[2] 0.0001638191 +5 cbx_1__2_:chanx_left_in[10] cbx_1__2_:chanx_left_in[2] 0.0001638191 + +*RES +0 sb_0__2_:chanx_right_out[10] cbx_1__2_:chanx_left_in[10] 0.001200067 + +*END + +*D_NET sb_0__2__0_chanx_right_out[14] 0.001233177 //LENGTH 7.660 LUMPCC 0.0004293619 DR + +*CONN +*I sb_0__2_:chanx_right_out[14] O *L 0 *C 400.050 879.920 +*I cbx_1__2_:chanx_left_in[14] I *L 0 *C 407.710 879.920 + +*CAP +0 sb_0__2_:chanx_right_out[14] 0.0004019075 +1 cbx_1__2_:chanx_left_in[14] 0.0004019075 +2 sb_0__2_:chanx_right_out[14] sb_0__2_:chanx_right_out[7] 5.411359e-05 +3 cbx_1__2_:chanx_left_in[14] cbx_1__2_:chanx_left_in[7] 5.411359e-05 +4 sb_0__2_:chanx_right_out[14] sb_0__2_:chanx_right_out[18] 0.0001605674 +5 cbx_1__2_:chanx_left_in[14] cbx_1__2_:chanx_left_in[18] 0.0001605674 + +*RES +0 sb_0__2_:chanx_right_out[14] cbx_1__2_:chanx_left_in[14] 0.001200067 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[0] 0.001251036 //LENGTH 11.020 LUMPCC 0.0005721848 DR + +*CONN +*I sb_0__2_:chany_bottom_out[0] O *L 0 *C 337.180 788.870 +*I cby_0__2_:chany_top_in[0] I *L 0 *C 337.180 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[0] 0.0003394254 +1 cby_0__2_:chany_top_in[0] 0.0003394254 +2 sb_0__2_:chany_bottom_out[0] sb_0__2_:chany_bottom_in[5] 0.0001430462 +3 cby_0__2_:chany_top_in[0] cby_0__2_:chany_top_out[5] 0.0001430462 +4 sb_0__2_:chany_bottom_out[0] sb_0__2_:chany_bottom_out[4] 0.0001430462 +5 cby_0__2_:chany_top_in[0] cby_0__2_:chany_top_in[4] 0.0001430462 + +*RES +0 sb_0__2_:chany_bottom_out[0] cby_0__2_:chany_top_in[0] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[4] 0.001258825 //LENGTH 11.020 LUMPCC 0.0005659095 DR + +*CONN +*I sb_0__2_:chany_bottom_out[4] O *L 0 *C 338.100 788.870 +*I cby_0__2_:chany_top_in[4] I *L 0 *C 338.100 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[4] 0.0003464579 +1 cby_0__2_:chany_top_in[4] 0.0003464579 +2 sb_0__2_:chany_bottom_out[4] sb_0__2_:chany_bottom_in[10] 0.0001399086 +3 cby_0__2_:chany_top_in[4] cby_0__2_:chany_top_out[10] 0.0001399086 +4 sb_0__2_:chany_bottom_out[4] sb_0__2_:chany_bottom_out[0] 0.0001430462 +5 cby_0__2_:chany_top_in[4] cby_0__2_:chany_top_in[0] 0.0001430462 + +*RES +0 sb_0__2_:chany_bottom_out[4] cby_0__2_:chany_top_in[4] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[9] 0.00125683 //LENGTH 11.020 LUMPCC 0.0005621223 DR + +*CONN +*I sb_0__2_:chany_bottom_out[9] O *L 0 *C 312.800 788.870 +*I cby_0__2_:chany_top_in[9] I *L 0 *C 312.800 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[9] 0.0003473536 +1 cby_0__2_:chany_top_in[9] 0.0003473536 +2 sb_0__2_:chany_bottom_out[9] sb_0__2_:chany_bottom_in[18] 0.0001405306 +3 cby_0__2_:chany_top_in[9] cby_0__2_:chany_top_out[18] 0.0001405306 +4 sb_0__2_:chany_bottom_out[9] sb_0__2_:chany_bottom_in[19] 0.0001405306 +5 cby_0__2_:chany_top_in[9] cby_0__2_:chany_top_out[19] 0.0001405306 + +*RES +0 sb_0__2_:chany_bottom_out[9] cby_0__2_:chany_top_in[9] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[12] 0.001258694 //LENGTH 11.020 LUMPCC 0.000567882 DR + +*CONN +*I sb_0__2_:chany_bottom_out[12] O *L 0 *C 354.660 788.870 +*I cby_0__2_:chany_top_in[12] I *L 0 *C 354.660 777.850 + +*CAP +0 sb_0__2_:chany_bottom_out[12] 0.0003454061 +1 cby_0__2_:chany_top_in[12] 0.0003454061 +2 sb_0__2_:chany_bottom_out[12] sb_0__2_:chany_bottom_out[2] 0.0001442041 +3 cby_0__2_:chany_top_in[12] cby_0__2_:chany_top_in[2] 0.0001442041 +4 sb_0__2_:chany_bottom_out[12] sb_0__2_:chany_bottom_out[7] 0.0001397368 +5 cby_0__2_:chany_top_in[12] cby_0__2_:chany_top_in[7] 0.0001397368 + +*RES +0 sb_0__2_:chany_bottom_out[12] cby_0__2_:chany_top_in[12] 0.009839286 + +*END + +*D_NET sb_0__2__0_chany_bottom_out[19] 0.00173165 //LENGTH 11.180 LUMPCC 0.0004134618 DR + +*CONN +*I sb_0__2_:chany_bottom_out[19] O *L 0 *C 312.800 788.950 +*I cby_0__2_:chany_top_in[19] I *L 0 *C 312.800 777.770 + +*CAP +0 sb_0__2_:chany_bottom_out[19] 0.000659094 +1 cby_0__2_:chany_top_in[19] 0.000659094 +2 sb_0__2_:chany_bottom_out[19] sb_0__2_:chany_bottom_out[18] 0.0002067309 +3 cby_0__2_:chany_top_in[19] cby_0__2_:chany_top_in[18] 0.0002067309 + +*RES +0 sb_0__2_:chany_bottom_out[19] cby_0__2_:chany_top_in[19] 0.001751533 + +*END + +*D_NET sb_1__0__0_chanx_left_out[0] 0.001338138 //LENGTH 7.660 LUMPCC 0.0006248277 DR + +*CONN +*I sb_1__0_:chanx_left_out[0] O *L 0 *C 519.950 320.960 +*I cbx_1__0_:chanx_right_in[0] I *L 0 *C 512.290 320.960 + +*CAP +0 sb_1__0_:chanx_left_out[0] 0.0003566552 +1 cbx_1__0_:chanx_right_in[0] 0.0003566552 +2 sb_1__0_:chanx_left_out[0] sb_1__0_:chanx_left_in[16] 0.0001600385 +3 cbx_1__0_:chanx_right_in[0] cbx_1__0_:chanx_right_out[16] 0.0001600385 +4 sb_1__0_:chanx_left_out[0] sb_1__0_:chanx_left_out[6] 0.0001523754 +5 cbx_1__0_:chanx_right_in[0] cbx_1__0_:chanx_right_in[6] 0.0001523754 + +*RES +0 sb_1__0_:chanx_left_out[0] cbx_1__0_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[6] 0.001270185 //LENGTH 7.660 LUMPCC 0.0004327587 DR + +*CONN +*I sb_1__0_:chanx_left_out[6] O *L 0 *C 519.950 319.600 +*I cbx_1__0_:chanx_right_in[6] I *L 0 *C 512.290 319.600 + +*CAP +0 sb_1__0_:chanx_left_out[6] 0.0004187132 +1 cbx_1__0_:chanx_right_in[6] 0.0004187132 +2 sb_1__0_:chanx_left_out[6] sb_1__0_:chanx_left_out[0] 0.0001523754 +3 cbx_1__0_:chanx_right_in[6] cbx_1__0_:chanx_right_in[0] 0.0001523754 +4 sb_1__0_:chanx_left_out[6] sb_1__0_:chanx_left_out[12] 6.400394e-05 +5 cbx_1__0_:chanx_right_in[6] cbx_1__0_:chanx_right_in[12] 6.400394e-05 + +*RES +0 sb_1__0_:chanx_left_out[6] cbx_1__0_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[12] 0.001242486 //LENGTH 7.660 LUMPCC 0.0004520522 DR + +*CONN +*I sb_1__0_:chanx_left_out[12] O *L 0 *C 519.950 316.880 +*I cbx_1__0_:chanx_right_in[12] I *L 0 *C 512.290 316.880 + +*CAP +0 sb_1__0_:chanx_left_out[12] 0.0003952171 +1 cbx_1__0_:chanx_right_in[12] 0.0003952171 +2 sb_1__0_:chanx_left_out[12] sb_1__0_:chanx_left_out[6] 6.400394e-05 +3 cbx_1__0_:chanx_right_in[12] cbx_1__0_:chanx_right_in[6] 6.400394e-05 +4 sb_1__0_:chanx_left_out[12] sb_1__0_:chanx_left_out[8] 0.0001620221 +5 cbx_1__0_:chanx_right_in[12] cbx_1__0_:chanx_right_in[8] 0.0001620221 + +*RES +0 sb_1__0_:chanx_left_out[12] cbx_1__0_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_left_out[15] 0.001241608 //LENGTH 7.660 LUMPCC 0.0004602999 DR + +*CONN +*I sb_1__0_:chanx_left_out[15] O *L 0 *C 519.950 333.200 +*I cbx_1__0_:chanx_right_in[15] I *L 0 *C 512.290 333.200 + +*CAP +0 sb_1__0_:chanx_left_out[15] 0.0003906542 +1 cbx_1__0_:chanx_right_in[15] 0.0003906542 +2 sb_1__0_:chanx_left_out[15] sb_1__0_:chanx_left_in[15] 6.915362e-05 +3 cbx_1__0_:chanx_right_in[15] cbx_1__0_:chanx_right_out[15] 6.915362e-05 +4 sb_1__0_:chanx_left_out[15] sb_1__0_:chanx_left_out[11] 0.0001609963 +5 cbx_1__0_:chanx_right_in[15] cbx_1__0_:chanx_right_in[11] 0.0001609963 + +*RES +0 sb_1__0_:chanx_left_out[15] cbx_1__0_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET sb_1__0__0_chanx_right_out[0] 0.004811671 //LENGTH 30.900 LUMPCC 0.0005315025 DR + +*CONN +*I sb_1__0_:chanx_right_out[0] O *L 0 *C 661.330 353.600 +*I cbx_2__0_:chanx_left_in[0] I *L 0 *C 672.060 369.850 +*N sb_1__0__0_chanx_right_out[0]:2 *C 672.060 371.223 +*N sb_1__0__0_chanx_right_out[0]:3 *C 672.053 371.280 +*N sb_1__0__0_chanx_right_out[0]:4 *C 667.940 371.280 +*N sb_1__0__0_chanx_right_out[0]:5 *C 667.920 371.273 +*N sb_1__0__0_chanx_right_out[0]:6 *C 667.920 353.608 +*N sb_1__0__0_chanx_right_out[0]:7 *C 667.900 353.600 +*N sb_1__0__0_chanx_right_out[0]:8 *C 667.520 353.600 +*N sb_1__0__0_chanx_right_out[0]:9 *C 667.519 353.600 + +*CAP +0 sb_1__0_:chanx_right_out[0] 0.000247729 +1 cbx_2__0_:chanx_left_in[0] 0.0001094645 +2 sb_1__0__0_chanx_right_out[0]:2 0.0001094645 +3 sb_1__0__0_chanx_right_out[0]:3 0.0003612442 +4 sb_1__0__0_chanx_right_out[0]:4 0.0003612442 +5 sb_1__0__0_chanx_right_out[0]:5 0.001349743 +6 sb_1__0__0_chanx_right_out[0]:6 0.001349743 +7 sb_1__0__0_chanx_right_out[0]:7 7.190328e-05 +8 sb_1__0__0_chanx_right_out[0]:8 7.190328e-05 +9 sb_1__0__0_chanx_right_out[0]:9 0.000247729 +10 sb_1__0_:chanx_right_out[0] sb_1__0_:chanx_right_in[19] 0.0001339056 +11 sb_1__0__0_chanx_right_out[0]:9 cbx_1__0__1_chanx_left_out[19]:2 0.0001339056 +12 sb_1__0_:chanx_right_out[0] sb_1__0_:chanx_right_out[13] 0.0001295192 +13 sb_1__0__0_chanx_right_out[0]:7 cbx_2__0_:chanx_left_in[13] 2.32644e-06 +14 sb_1__0__0_chanx_right_out[0]:8 sb_1__0__0_chanx_right_out[13]:2 2.32644e-06 +15 sb_1__0__0_chanx_right_out[0]:9 sb_1__0__0_chanx_right_out[13]:3 0.0001295192 + +*RES +0 sb_1__0_:chanx_right_out[0] sb_1__0__0_chanx_right_out[0]:9 0.00096961 +1 sb_1__0__0_chanx_right_out[0]:2 cbx_2__0_:chanx_left_in[0] 0.001225446 +2 sb_1__0__0_chanx_right_out[0]:3 sb_1__0__0_chanx_right_out[0]:2 0.00341 +3 sb_1__0__0_chanx_right_out[0]:4 sb_1__0__0_chanx_right_out[0]:3 0.0006442916 +4 sb_1__0__0_chanx_right_out[0]:5 sb_1__0__0_chanx_right_out[0]:4 0.00341 +5 sb_1__0__0_chanx_right_out[0]:7 sb_1__0__0_chanx_right_out[0]:6 0.00341 +6 sb_1__0__0_chanx_right_out[0]:6 sb_1__0__0_chanx_right_out[0]:5 0.002767517 +7 sb_1__0__0_chanx_right_out[0]:8 sb_1__0__0_chanx_right_out[0]:7 5.953333e-05 +8 sb_1__0__0_chanx_right_out[0]:9 sb_1__0__0_chanx_right_out[0]:8 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[8] 0.001424504 //LENGTH 7.660 LUMPCC 0.0003703693 DR + +*CONN +*I sb_1__0_:chanx_right_out[8] O *L 0 *C 661.330 327.760 +*I cbx_2__0_:chanx_left_in[8] I *L 0 *C 668.990 327.760 +*N sb_1__0__0_chanx_right_out[8]:2 *C 667.520 327.760 +*N sb_1__0__0_chanx_right_out[8]:3 *C 667.519 327.760 + +*CAP +0 sb_1__0_:chanx_right_out[8] 0.0003070795 +1 cbx_2__0_:chanx_left_in[8] 0.0002199879 +2 sb_1__0__0_chanx_right_out[8]:2 0.0002199879 +3 sb_1__0__0_chanx_right_out[8]:3 0.0003070795 +4 sb_1__0_:chanx_right_out[8] sb_1__0_:chanx_right_in[6] 6.267661e-05 +5 sb_1__0__0_chanx_right_out[8]:3 cbx_1__0__1_chanx_left_out[6]:2 6.267661e-05 +6 sb_1__0_:chanx_right_out[8] sb_1__0_:chanx_right_out[4] 0.000122508 +7 sb_1__0__0_chanx_right_out[8]:3 sb_1__0__0_chanx_right_out[4]:3 0.000122508 + +*RES +0 sb_1__0_:chanx_right_out[8] sb_1__0__0_chanx_right_out[8]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[8]:2 cbx_2__0_:chanx_left_in[8] 0.0002303 +2 sb_1__0__0_chanx_right_out[8]:3 sb_1__0__0_chanx_right_out[8]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[11] 0.001434543 //LENGTH 7.660 LUMPCC 0.000377698 DR + +*CONN +*I sb_1__0_:chanx_right_out[11] O *L 0 *C 661.330 349.520 +*I cbx_2__0_:chanx_left_in[11] I *L 0 *C 668.990 349.520 +*N sb_1__0__0_chanx_right_out[11]:2 *C 667.520 349.520 +*N sb_1__0__0_chanx_right_out[11]:3 *C 667.519 349.520 + +*CAP +0 sb_1__0_:chanx_right_out[11] 0.0003107666 +1 cbx_2__0_:chanx_left_in[11] 0.0002176561 +2 sb_1__0__0_chanx_right_out[11]:2 0.0002176561 +3 sb_1__0__0_chanx_right_out[11]:3 0.0003107666 +4 sb_1__0_:chanx_right_out[11] sb_1__0_:chanx_right_out[5] 0.0001245063 +5 cbx_2__0_:chanx_left_in[11] cbx_2__0_:chanx_left_in[5] 1.644281e-06 +6 sb_1__0__0_chanx_right_out[11]:2 sb_1__0__0_chanx_right_out[5]:2 1.644281e-06 +7 sb_1__0__0_chanx_right_out[11]:3 sb_1__0__0_chanx_right_out[5]:3 0.0001245063 +8 sb_1__0_:chanx_right_out[11] sb_1__0_:chanx_right_out[19] 6.269842e-05 +9 sb_1__0__0_chanx_right_out[11]:3 sb_1__0__0_chanx_right_out[19]:3 6.269842e-05 + +*RES +0 sb_1__0_:chanx_right_out[11] sb_1__0__0_chanx_right_out[11]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[11]:2 cbx_2__0_:chanx_left_in[11] 0.0002303 +2 sb_1__0__0_chanx_right_out[11]:3 sb_1__0__0_chanx_right_out[11]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[17] 0.00150277 //LENGTH 7.660 LUMPCC 0.0004872278 DR + +*CONN +*I sb_1__0_:chanx_right_out[17] O *L 0 *C 661.330 356.320 +*I cbx_2__0_:chanx_left_in[17] I *L 0 *C 668.990 356.320 +*N sb_1__0__0_chanx_right_out[17]:2 *C 667.520 356.320 +*N sb_1__0__0_chanx_right_out[17]:3 *C 667.519 356.320 + +*CAP +0 sb_1__0_:chanx_right_out[17] 0.0002885319 +1 cbx_2__0_:chanx_left_in[17] 0.0002192392 +2 sb_1__0__0_chanx_right_out[17]:2 0.0002192392 +3 sb_1__0__0_chanx_right_out[17]:3 0.0002885319 +4 sb_1__0_:chanx_right_out[17] sb_1__0_:chanx_right_in[17] 0.0001230697 +5 sb_1__0__0_chanx_right_out[17]:3 cbx_1__0__1_chanx_left_out[17]:2 0.0001230697 +6 sb_1__0_:chanx_right_out[17] sb_1__0_:chanx_right_out[13] 0.0001205442 +7 sb_1__0__0_chanx_right_out[17]:3 sb_1__0__0_chanx_right_out[13]:3 0.0001205442 + +*RES +0 sb_1__0_:chanx_right_out[17] sb_1__0__0_chanx_right_out[17]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[17]:2 cbx_2__0_:chanx_left_in[17] 0.0002303 +2 sb_1__0__0_chanx_right_out[17]:3 sb_1__0__0_chanx_right_out[17]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chanx_right_out[19] 0.00142586 //LENGTH 7.660 LUMPCC 0.0003645284 DR + +*CONN +*I sb_1__0_:chanx_right_out[19] O *L 0 *C 661.330 346.800 +*I cbx_2__0_:chanx_left_in[19] I *L 0 *C 668.990 346.800 +*N sb_1__0__0_chanx_right_out[19]:2 *C 667.520 346.800 +*N sb_1__0__0_chanx_right_out[19]:3 *C 667.519 346.800 + +*CAP +0 sb_1__0_:chanx_right_out[19] 0.0003114004 +1 cbx_2__0_:chanx_left_in[19] 0.0002192653 +2 sb_1__0__0_chanx_right_out[19]:2 0.0002192653 +3 sb_1__0__0_chanx_right_out[19]:3 0.0003114004 +4 sb_1__0_:chanx_right_out[19] sb_1__0_:chanx_right_out[7] 0.0001195658 +5 sb_1__0__0_chanx_right_out[19]:3 sb_1__0__0_chanx_right_out[7]:3 0.0001195658 +6 sb_1__0_:chanx_right_out[19] sb_1__0_:chanx_right_out[11] 6.269842e-05 +7 sb_1__0__0_chanx_right_out[19]:3 sb_1__0__0_chanx_right_out[11]:3 6.269842e-05 + +*RES +0 sb_1__0_:chanx_right_out[19] sb_1__0__0_chanx_right_out[19]:3 0.0009696099 +1 sb_1__0__0_chanx_right_out[19]:2 cbx_2__0_:chanx_left_in[19] 0.0002303 +2 sb_1__0__0_chanx_right_out[19]:3 sb_1__0__0_chanx_right_out[19]:2 1e-05 + +*END + +*D_NET sb_1__0__0_chany_top_out[6] 0.001231796 //LENGTH 11.020 LUMPCC 0.0005942238 DR + +*CONN +*I sb_1__0_:chany_top_out[6] O *L 0 *C 590.180 397.050 +*I cby_1__1_:chany_bottom_in[6] I *L 0 *C 590.180 408.070 + +*CAP +0 sb_1__0_:chany_top_out[6] 0.0003187861 +1 cby_1__1_:chany_bottom_in[6] 0.0003187861 +2 sb_1__0_:chany_top_out[6] sb_1__0_:chany_top_in[16] 0.000148556 +3 cby_1__1_:chany_bottom_in[6] cby_1__1_:chany_bottom_out[16] 0.000148556 +4 sb_1__0_:chany_top_out[6] sb_1__0_:chany_top_out[3] 0.000148556 +5 cby_1__1_:chany_bottom_in[6] cby_1__1_:chany_bottom_in[3] 0.000148556 + +*RES +0 sb_1__0_:chany_top_out[6] cby_1__1_:chany_bottom_in[6] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[10] 0.001213493 //LENGTH 11.020 LUMPCC 0.0006111696 DR + +*CONN +*I sb_1__0_:chany_top_out[10] O *L 0 *C 616.400 397.050 +*I cby_1__1_:chany_bottom_in[10] I *L 0 *C 616.400 408.070 + +*CAP +0 sb_1__0_:chany_top_out[10] 0.0003011617 +1 cby_1__1_:chany_bottom_in[10] 0.0003011617 +2 sb_1__0_:chany_top_out[10] sb_1__0_:chany_top_out[14] 0.0001527924 +3 cby_1__1_:chany_bottom_in[10] cby_1__1_:chany_bottom_in[14] 0.0001527924 +4 sb_1__0_:chany_top_out[10] sb_1__0_:chany_top_out[18] 0.0001527924 +5 cby_1__1_:chany_bottom_in[10] cby_1__1_:chany_bottom_in[18] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[10] cby_1__1_:chany_bottom_in[10] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[14] 0.001166283 //LENGTH 11.020 LUMPCC 0.0005021601 DR + +*CONN +*I sb_1__0_:chany_top_out[14] O *L 0 *C 617.320 397.050 +*I cby_1__1_:chany_bottom_in[14] I *L 0 *C 617.320 408.070 + +*CAP +0 sb_1__0_:chany_top_out[14] 0.0003320613 +1 cby_1__1_:chany_bottom_in[14] 0.0003320613 +2 sb_1__0_:chany_top_out[14] sb_1__0_:chany_top_out[4] 9.828763e-05 +3 cby_1__1_:chany_bottom_in[14] cby_1__1_:chany_bottom_in[4] 9.828763e-05 +4 sb_1__0_:chany_top_out[14] sb_1__0_:chany_top_out[10] 0.0001527924 +5 cby_1__1_:chany_bottom_in[14] cby_1__1_:chany_bottom_in[10] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[14] cby_1__1_:chany_bottom_in[14] 0.009839285 + +*END + +*D_NET sb_1__0__0_chany_top_out[19] 0.001213397 //LENGTH 11.020 LUMPCC 0.0006111696 DR + +*CONN +*I sb_1__0_:chany_top_out[19] O *L 0 *C 598.460 397.050 +*I cby_1__1_:chany_bottom_in[19] I *L 0 *C 598.460 408.070 + +*CAP +0 sb_1__0_:chany_top_out[19] 0.0003011136 +1 cby_1__1_:chany_bottom_in[19] 0.0003011136 +2 sb_1__0_:chany_top_out[19] sb_1__0_:chany_top_out[2] 0.0001527924 +3 cby_1__1_:chany_bottom_in[19] cby_1__1_:chany_bottom_in[2] 0.0001527924 +4 sb_1__0_:chany_top_out[19] sb_1__0_:chany_top_out[12] 0.0001527924 +5 cby_1__1_:chany_bottom_in[19] cby_1__1_:chany_bottom_in[12] 0.0001527924 + +*RES +0 sb_1__0_:chany_top_out[19] cby_1__1_:chany_bottom_in[19] 0.009839285 + +*END + +*D_NET sb_1__1__0_chanx_left_out[4] 0.001275649 //LENGTH 7.660 LUMPCC 0.0003867764 DR + +*CONN +*I sb_1__1_:chanx_left_out[4] O *L 0 *C 519.950 607.920 +*I cbx_1__1_:chanx_right_in[4] I *L 0 *C 512.290 607.920 + +*CAP +0 sb_1__1_:chanx_left_out[4] 0.0004444363 +1 cbx_1__1_:chanx_right_in[4] 0.0004444363 +2 sb_1__1_:chanx_left_out[4] sb_1__1_:chanx_left_in[15] 4.924156e-05 +3 cbx_1__1_:chanx_right_in[4] cbx_1__1_:chanx_right_out[15] 4.924156e-05 +4 sb_1__1_:chanx_left_out[4] sb_1__1_:chanx_left_out[1] 0.0001441466 +5 cbx_1__1_:chanx_right_in[4] cbx_1__1_:chanx_right_in[1] 0.0001441466 + +*RES +0 sb_1__1_:chanx_left_out[4] cbx_1__1_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[8] 0.001373629 //LENGTH 7.660 LUMPCC 0.000579501 DR + +*CONN +*I sb_1__1_:chanx_left_out[8] O *L 0 *C 519.950 576.640 +*I cbx_1__1_:chanx_right_in[8] I *L 0 *C 512.290 576.640 + +*CAP +0 sb_1__1_:chanx_left_out[8] 0.0003970639 +1 cbx_1__1_:chanx_right_in[8] 0.0003970639 +2 sb_1__1_:chanx_left_out[8] sb_1__1_:chanx_left_out[5] 0.0001448753 +3 cbx_1__1_:chanx_right_in[8] cbx_1__1_:chanx_right_in[5] 0.0001448753 +4 sb_1__1_:chanx_left_out[8] sb_1__1_:chanx_left_out[6] 0.0001448753 +5 cbx_1__1_:chanx_right_in[8] cbx_1__1_:chanx_right_in[6] 0.0001448753 + +*RES +0 sb_1__1_:chanx_left_out[8] cbx_1__1_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_left_out[14] 0.001637109 //LENGTH 7.660 LUMPCC 0.0009757025 DR + +*CONN +*I sb_1__1_:chanx_left_out[14] O *L 0 *C 519.950 582.080 +*I cbx_1__1_:chanx_right_in[14] I *L 0 *C 512.290 582.080 + +*CAP +0 sb_1__1_:chanx_left_out[14] 0.0003307032 +1 cbx_1__1_:chanx_right_in[14] 0.0003307032 +2 sb_1__1_:chanx_left_out[14] sb_1__1_:chanx_left_in[17] 3.388373e-06 +3 sb_1__1_:chanx_left_out[14] cbx_1__1__0_chanx_right_out[17]:3 0.0003275737 +4 sb_1__1_:chanx_left_out[14] cbx_1__1__0_chanx_right_out[17]:5 6.378637e-06 +5 cbx_1__1_:chanx_right_in[14] cbx_1__1_:chanx_right_out[17] 6.378637e-06 +6 cbx_1__1_:chanx_right_in[14] cbx_1__1__0_chanx_right_out[17]:2 3.388373e-06 +7 cbx_1__1_:chanx_right_in[14] cbx_1__1__0_chanx_right_out[17]:4 0.0003275737 +8 sb_1__1_:chanx_left_out[14] sb_1__1_:chanx_left_out[10] 0.0001505106 +9 cbx_1__1_:chanx_right_in[14] cbx_1__1_:chanx_right_in[10] 0.0001505106 + +*RES +0 sb_1__1_:chanx_left_out[14] cbx_1__1_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_1__1__0_chanx_right_out[1] 0.001398817 //LENGTH 7.660 LUMPCC 0.0003469535 DR + +*CONN +*I sb_1__1_:chanx_right_out[1] O *L 0 *C 661.330 610.640 +*I cbx_2__1_:chanx_left_in[1] I *L 0 *C 668.990 610.640 +*N sb_1__1__0_chanx_right_out[1]:2 *C 667.520 610.640 +*N sb_1__1__0_chanx_right_out[1]:3 *C 667.519 610.640 + +*CAP +0 sb_1__1_:chanx_right_out[1] 0.0003343115 +1 cbx_2__1_:chanx_left_in[1] 0.0001916202 +2 sb_1__1__0_chanx_right_out[1]:2 0.0001916202 +3 sb_1__1__0_chanx_right_out[1]:3 0.0003343115 +4 sb_1__1_:chanx_right_out[1] sb_1__1_:chanx_right_out[0] 0.0001179583 +5 cbx_2__1_:chanx_left_in[1] cbx_2__1_:chanx_left_in[0] 6.576453e-06 +6 sb_1__1__0_chanx_right_out[1]:2 sb_1__1__0_chanx_right_out[0]:2 6.576453e-06 +7 sb_1__1__0_chanx_right_out[1]:3 sb_1__1__0_chanx_right_out[0]:3 0.0001179583 +8 sb_1__1_:chanx_right_out[1] sb_1__1_:chanx_right_out[4] 4.894203e-05 +9 sb_1__1__0_chanx_right_out[1]:3 sb_1__1__0_chanx_right_out[4]:3 4.894203e-05 + +*RES +0 sb_1__1_:chanx_right_out[1] sb_1__1__0_chanx_right_out[1]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[1]:2 cbx_2__1_:chanx_left_in[1] 0.0002303 +2 sb_1__1__0_chanx_right_out[1]:3 sb_1__1__0_chanx_right_out[1]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[4] 0.001389537 //LENGTH 7.660 LUMPCC 0.0003252831 DR + +*CONN +*I sb_1__1_:chanx_right_out[4] O *L 0 *C 661.330 607.920 +*I cbx_2__1_:chanx_left_in[4] I *L 0 *C 668.990 607.920 +*N sb_1__1__0_chanx_right_out[4]:2 *C 667.520 607.920 +*N sb_1__1__0_chanx_right_out[4]:3 *C 667.519 607.920 + +*CAP +0 sb_1__1_:chanx_right_out[4] 0.0003250241 +1 cbx_2__1_:chanx_left_in[4] 0.0002071029 +2 sb_1__1__0_chanx_right_out[4]:2 0.0002071029 +3 sb_1__1__0_chanx_right_out[4]:3 0.0003250241 +4 sb_1__1_:chanx_right_out[4] sb_1__1_:chanx_right_out[1] 4.894203e-05 +5 sb_1__1__0_chanx_right_out[4]:3 sb_1__1__0_chanx_right_out[1]:3 4.894203e-05 +6 sb_1__1_:chanx_right_out[4] sb_1__1_:chanx_right_out[11] 0.0001120554 +7 cbx_2__1_:chanx_left_in[4] cbx_2__1_:chanx_left_in[11] 1.644113e-06 +8 sb_1__1__0_chanx_right_out[4]:2 sb_1__1__0_chanx_right_out[11]:2 1.644113e-06 +9 sb_1__1__0_chanx_right_out[4]:3 sb_1__1__0_chanx_right_out[11]:3 0.0001120554 + +*RES +0 sb_1__1_:chanx_right_out[4] sb_1__1__0_chanx_right_out[4]:3 0.00096961 +1 sb_1__1__0_chanx_right_out[4]:2 cbx_2__1_:chanx_left_in[4] 0.0002303 +2 sb_1__1__0_chanx_right_out[4]:3 sb_1__1__0_chanx_right_out[4]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[10] 0.001368202 //LENGTH 7.660 LUMPCC 0.0004103138 DR + +*CONN +*I sb_1__1_:chanx_right_out[10] O *L 0 *C 661.330 588.880 +*I cbx_2__1_:chanx_left_in[10] I *L 0 *C 668.990 588.880 +*N sb_1__1__0_chanx_right_out[10]:2 *C 667.520 588.880 +*N sb_1__1__0_chanx_right_out[10]:3 *C 667.519 588.880 + +*CAP +0 sb_1__1_:chanx_right_out[10] 0.0002928945 +1 cbx_2__1_:chanx_left_in[10] 0.0001860494 +2 sb_1__1__0_chanx_right_out[10]:2 0.0001860494 +3 sb_1__1__0_chanx_right_out[10]:3 0.0002928945 +4 sb_1__1_:chanx_right_out[10] direct_interc_2_out[0]:21 2.388634e-05 +5 sb_1__1__0_chanx_right_out[10]:3 direct_interc_2_out[0]:2 2.388634e-05 +6 sb_1__1_:chanx_right_out[10] sb_1__1_:chanx_right_out[2] 0.0001288604 +7 cbx_2__1_:chanx_left_in[10] cbx_2__1_:chanx_left_in[2] 9.866816e-06 +8 sb_1__1__0_chanx_right_out[10]:2 sb_1__1__0_chanx_right_out[2]:2 9.866816e-06 +9 sb_1__1__0_chanx_right_out[10]:3 sb_1__1__0_chanx_right_out[2]:3 0.0001288604 +10 sb_1__1_:chanx_right_out[10] sb_1__1_:chanx_right_out[6] 4.254332e-05 +11 sb_1__1__0_chanx_right_out[10]:3 sb_1__1__0_chanx_right_out[6]:3 4.254332e-05 + +*RES +0 sb_1__1_:chanx_right_out[10] sb_1__1__0_chanx_right_out[10]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[10]:2 cbx_2__1_:chanx_left_in[10] 0.0002303 +2 sb_1__1__0_chanx_right_out[10]:3 sb_1__1__0_chanx_right_out[10]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chanx_right_out[13] 0.001486306 //LENGTH 7.660 LUMPCC 0.0003143492 DR + +*CONN +*I sb_1__1_:chanx_right_out[13] O *L 0 *C 661.330 613.360 +*I cbx_2__1_:chanx_left_in[13] I *L 0 *C 668.990 613.360 +*N sb_1__1__0_chanx_right_out[13]:2 *C 667.520 613.360 +*N sb_1__1__0_chanx_right_out[13]:3 *C 667.519 613.360 + +*CAP +0 sb_1__1_:chanx_right_out[13] 0.0003666866 +1 cbx_2__1_:chanx_left_in[13] 0.0002192918 +2 sb_1__1__0_chanx_right_out[13]:2 0.0002192918 +3 sb_1__1__0_chanx_right_out[13]:3 0.0003666866 +4 sb_1__1_:chanx_right_out[13] sb_1__1_:ccff_head[0] 4.980435e-05 +5 sb_1__1__0_chanx_right_out[13]:3 cbx_1__1__1_ccff_tail[0]:2 4.980435e-05 +6 sb_1__1_:chanx_right_out[13] sb_1__1_:chanx_right_out[0] 0.0001073702 +7 sb_1__1__0_chanx_right_out[13]:3 sb_1__1__0_chanx_right_out[0]:3 0.0001073702 + +*RES +0 sb_1__1_:chanx_right_out[13] sb_1__1__0_chanx_right_out[13]:3 0.0009696099 +1 sb_1__1__0_chanx_right_out[13]:2 cbx_2__1_:chanx_left_in[13] 0.0002303 +2 sb_1__1__0_chanx_right_out[13]:3 sb_1__1__0_chanx_right_out[13]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[1] 0.001295275 //LENGTH 11.020 LUMPCC 0.0004990738 DR + +*CONN +*I sb_1__1_:chany_bottom_out[1] O *L 0 *C 579.600 527.750 +*I cby_1__1_:chany_top_in[1] I *L 0 *C 579.600 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[1] 0.0003981007 +1 cby_1__1_:chany_top_in[1] 0.0003981007 +2 sb_1__1_:chany_bottom_out[1] sb_1__1_:chany_bottom_out[7] 0.0001247684 +3 cby_1__1_:chany_top_in[1] cby_1__1_:chany_top_in[7] 0.0001247684 +4 sb_1__1_:chany_bottom_out[1] sb_1__1_:chany_bottom_out[17] 0.0001247684 +5 cby_1__1_:chany_top_in[1] cby_1__1_:chany_top_in[17] 0.0001247684 + +*RES +0 sb_1__1_:chany_bottom_out[1] cby_1__1_:chany_top_in[1] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[4] 0.001259712 //LENGTH 11.020 LUMPCC 0.00026275 DR + +*CONN +*I sb_1__1_:chany_bottom_out[4] O *L 0 *C 616.400 527.750 +*I cby_1__1_:chany_top_in[4] I *L 0 *C 616.400 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[4] 0.000498481 +1 cby_1__1_:chany_top_in[4] 0.000498481 +2 sb_1__1_:chany_bottom_out[4] sb_1__1_:chany_bottom_in[6] 2.056134e-05 +3 cby_1__1_:chany_top_in[4] cby_1__1_:chany_top_out[6] 2.056134e-05 +4 sb_1__1_:chany_bottom_out[4] sb_1__1_:chany_bottom_out[14] 5.216231e-05 +5 sb_1__1_:chany_bottom_out[4] sb_1__1__0_chany_bottom_out[14]:3 7.986142e-06 +6 sb_1__1_:chany_bottom_out[4] sb_1__1__0_chany_bottom_out[14]:10 5.06652e-05 +7 cby_1__1_:chany_top_in[4] cby_1__1_:chany_top_in[14] 7.986142e-06 +8 cby_1__1_:chany_top_in[4] sb_1__1__0_chany_bottom_out[14]:9 5.06652e-05 +9 cby_1__1_:chany_top_in[4] sb_1__1__0_chany_bottom_out[14]:11 5.216231e-05 + +*RES +0 sb_1__1_:chany_bottom_out[4] cby_1__1_:chany_top_in[4] 0.009839285 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[9] 0.001286232 //LENGTH 11.020 LUMPCC 0.0005067064 DR + +*CONN +*I sb_1__1_:chany_bottom_out[9] O *L 0 *C 574.080 527.750 +*I cby_1__1_:chany_top_in[9] I *L 0 *C 574.080 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[9] 0.000389763 +1 cby_1__1_:chany_top_in[9] 0.000389763 +2 sb_1__1_:chany_bottom_out[9] sb_1__1_:chany_bottom_in[15] 0.0001254793 +3 cby_1__1_:chany_top_in[9] cby_1__1_:chany_top_out[15] 0.0001254793 +4 sb_1__1_:chany_bottom_out[9] sb_1__1_:chany_bottom_out[15] 0.0001278739 +5 cby_1__1_:chany_top_in[9] cby_1__1_:chany_top_in[15] 0.0001278739 + +*RES +0 sb_1__1_:chany_bottom_out[9] cby_1__1_:chany_top_in[9] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[16] 0.001293202 //LENGTH 11.020 LUMPCC 0.0005016136 DR + +*CONN +*I sb_1__1_:chany_bottom_out[16] O *L 0 *C 584.200 527.750 +*I cby_1__1_:chany_top_in[16] I *L 0 *C 584.200 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[16] 0.000395794 +1 cby_1__1_:chany_top_in[16] 0.000395794 +2 sb_1__1_:chany_bottom_out[16] sb_1__1_:chany_bottom_in[4] 0.0001254034 +3 cby_1__1_:chany_top_in[16] cby_1__1_:chany_top_out[4] 0.0001254034 +4 sb_1__1_:chany_bottom_out[16] sb_1__1_:chany_bottom_out[8] 0.0001254034 +5 cby_1__1_:chany_top_in[16] cby_1__1_:chany_top_in[8] 0.0001254034 + +*RES +0 sb_1__1_:chany_bottom_out[16] cby_1__1_:chany_top_in[16] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_bottom_out[18] 0.001271985 //LENGTH 11.020 LUMPCC 0.0003856429 DR + +*CONN +*I sb_1__1_:chany_bottom_out[18] O *L 0 *C 592.940 527.750 +*I cby_1__1_:chany_top_in[18] I *L 0 *C 592.940 516.730 + +*CAP +0 sb_1__1_:chany_bottom_out[18] 0.0004431711 +1 cby_1__1_:chany_top_in[18] 0.0004431711 +2 sb_1__1_:chany_bottom_out[18] sb_1__1_:chany_bottom_out[5] 6.814997e-05 +3 cby_1__1_:chany_top_in[18] cby_1__1_:chany_top_in[5] 6.814997e-05 +4 sb_1__1_:chany_bottom_out[18] sb_1__1_:chany_bottom_out[11] 0.0001246715 +5 cby_1__1_:chany_top_in[18] cby_1__1_:chany_top_in[11] 0.0001246715 + +*RES +0 sb_1__1_:chany_bottom_out[18] cby_1__1_:chany_top_in[18] 0.009839286 + +*END + +*D_NET sb_1__1__0_chany_top_out[4] 0.001098395 //LENGTH 11.020 LUMPCC 0.0001979074 DR + +*CONN +*I sb_1__1_:chany_top_out[4] O *L 0 *C 618.700 658.170 +*I cby_1__2_:chany_bottom_in[4] I *L 0 *C 618.700 669.190 +*N sb_1__1__0_chany_top_out[4]:2 *C 618.700 667.520 +*N sb_1__1__0_chany_top_out[4]:3 *C 618.700 667.519 + +*CAP +0 sb_1__1_:chany_top_out[4] 0.0003243866 +1 cby_1__2_:chany_bottom_in[4] 0.0001258571 +2 sb_1__1__0_chany_top_out[4]:2 0.0001258571 +3 sb_1__1__0_chany_top_out[4]:3 0.0003243866 +4 sb_1__1_:chany_top_out[4] sb_1__1_:chany_top_out[14] 9.743153e-05 +5 cby_1__2_:chany_bottom_in[4] cby_1__2_:chany_bottom_in[14] 1.522179e-06 +6 sb_1__1__0_chany_top_out[4]:2 sb_1__1__0_chany_top_out[14]:2 1.522179e-06 +7 sb_1__1__0_chany_top_out[4]:3 sb_1__1__0_chany_top_out[14]:3 9.743153e-05 + +*RES +0 sb_1__1_:chany_top_out[4] sb_1__1__0_chany_top_out[4]:3 0.008347322 +1 sb_1__1__0_chany_top_out[4]:2 cby_1__2_:chany_bottom_in[4] 0.001491072 +2 sb_1__1__0_chany_top_out[4]:3 sb_1__1__0_chany_top_out[4]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[9] 0.001250587 //LENGTH 11.020 LUMPCC 0.0005883647 DR + +*CONN +*I sb_1__1_:chany_top_out[9] O *L 0 *C 578.220 658.170 +*I cby_1__2_:chany_bottom_in[9] I *L 0 *C 578.220 669.190 +*N sb_1__1__0_chany_top_out[9]:2 *C 578.220 667.520 +*N sb_1__1__0_chany_top_out[9]:3 *C 578.220 667.519 + +*CAP +0 sb_1__1_:chany_top_out[9] 0.000220016 +1 cby_1__2_:chany_bottom_in[9] 0.0001110953 +2 sb_1__1__0_chany_top_out[9]:2 0.0001110953 +3 sb_1__1__0_chany_top_out[9]:3 0.000220016 +4 sb_1__1_:chany_top_out[9] sb_1__1_:chany_top_in[1] 0.0001434015 +5 cby_1__2_:chany_bottom_in[9] cby_1__2_:chany_bottom_out[1] 7.341718e-06 +6 sb_1__1__0_chany_top_out[9]:2 cby_1__1__1_chany_bottom_out[1]:3 7.341718e-06 +7 sb_1__1__0_chany_top_out[9]:3 cby_1__1__1_chany_bottom_out[1]:2 0.0001434015 +8 sb_1__1_:chany_top_out[9] sb_1__1_:chany_top_in[19] 0.0001361438 +9 cby_1__2_:chany_bottom_in[9] cby_1__2_:chany_bottom_out[19] 7.295327e-06 +10 sb_1__1__0_chany_top_out[9]:2 cby_1__1__1_chany_bottom_out[19]:3 7.295327e-06 +11 sb_1__1__0_chany_top_out[9]:3 cby_1__1__1_chany_bottom_out[19]:2 0.0001361438 + +*RES +0 sb_1__1_:chany_top_out[9] sb_1__1__0_chany_top_out[9]:3 0.008347321 +1 sb_1__1__0_chany_top_out[9]:2 cby_1__2_:chany_bottom_in[9] 0.001491072 +2 sb_1__1__0_chany_top_out[9]:3 sb_1__1__0_chany_top_out[9]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[12] 0.001226785 //LENGTH 11.020 LUMPCC 0.0006029896 DR + +*CONN +*I sb_1__1_:chany_top_out[12] O *L 0 *C 599.380 658.170 +*I cby_1__2_:chany_bottom_in[12] I *L 0 *C 599.380 669.190 +*N sb_1__1__0_chany_top_out[12]:2 *C 599.380 667.520 +*N sb_1__1__0_chany_top_out[12]:3 *C 599.380 667.519 + +*CAP +0 sb_1__1_:chany_top_out[12] 0.0002014367 +1 cby_1__2_:chany_bottom_in[12] 0.0001104609 +2 sb_1__1__0_chany_top_out[12]:2 0.0001104609 +3 sb_1__1__0_chany_top_out[12]:3 0.0002014367 +4 sb_1__1_:chany_top_out[12] sb_1__1_:chany_top_in[0] 0.000143306 +5 cby_1__2_:chany_bottom_in[12] cby_1__2_:chany_bottom_out[0] 7.441422e-06 +6 sb_1__1__0_chany_top_out[12]:2 cby_1__1__1_chany_bottom_out[0]:3 7.441422e-06 +7 sb_1__1__0_chany_top_out[12]:3 cby_1__1__1_chany_bottom_out[0]:2 0.000143306 +8 sb_1__1_:chany_top_out[12] sb_1__1_:chany_top_out[19] 0.000143306 +9 cby_1__2_:chany_bottom_in[12] cby_1__2_:chany_bottom_in[19] 7.441422e-06 +10 sb_1__1__0_chany_top_out[12]:2 sb_1__1__0_chany_top_out[19]:2 7.441422e-06 +11 sb_1__1__0_chany_top_out[12]:3 sb_1__1__0_chany_top_out[19]:3 0.000143306 + +*RES +0 sb_1__1_:chany_top_out[12] sb_1__1__0_chany_top_out[12]:3 0.008347321 +1 sb_1__1__0_chany_top_out[12]:2 cby_1__2_:chany_bottom_in[12] 0.001491072 +2 sb_1__1__0_chany_top_out[12]:3 sb_1__1__0_chany_top_out[12]:2 1e-05 + +*END + +*D_NET sb_1__1__0_chany_top_out[19] 0.001226785 //LENGTH 11.020 LUMPCC 0.0006029896 DR + +*CONN +*I sb_1__1_:chany_top_out[19] O *L 0 *C 598.460 658.170 +*I cby_1__2_:chany_bottom_in[19] I *L 0 *C 598.460 669.190 +*N sb_1__1__0_chany_top_out[19]:2 *C 598.460 667.520 +*N sb_1__1__0_chany_top_out[19]:3 *C 598.460 667.519 + +*CAP +0 sb_1__1_:chany_top_out[19] 0.0002014367 +1 cby_1__2_:chany_bottom_in[19] 0.0001104609 +2 sb_1__1__0_chany_top_out[19]:2 0.0001104609 +3 sb_1__1__0_chany_top_out[19]:3 0.0002014367 +4 sb_1__1_:chany_top_out[19] sb_1__1_:chany_top_out[2] 0.000143306 +5 cby_1__2_:chany_bottom_in[19] cby_1__2_:chany_bottom_in[2] 7.441422e-06 +6 sb_1__1__0_chany_top_out[19]:2 sb_1__1__0_chany_top_out[2]:2 7.441422e-06 +7 sb_1__1__0_chany_top_out[19]:3 sb_1__1__0_chany_top_out[2]:3 0.000143306 +8 sb_1__1_:chany_top_out[19] sb_1__1_:chany_top_out[12] 0.000143306 +9 cby_1__2_:chany_bottom_in[19] cby_1__2_:chany_bottom_in[12] 7.441422e-06 +10 sb_1__1__0_chany_top_out[19]:2 sb_1__1__0_chany_top_out[12]:2 7.441422e-06 +11 sb_1__1__0_chany_top_out[19]:3 sb_1__1__0_chany_top_out[12]:3 0.000143306 + +*RES +0 sb_1__1_:chany_top_out[19] sb_1__1__0_chany_top_out[19]:3 0.008347321 +1 sb_1__1__0_chany_top_out[19]:2 cby_1__2_:chany_bottom_in[19] 0.001491072 +2 sb_1__1__0_chany_top_out[19]:3 sb_1__1__0_chany_top_out[19]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_left_out[2] 0.00134531 //LENGTH 7.660 LUMPCC 0.0003664286 DR + +*CONN +*I sb_1__2_:chanx_left_out[2] O *L 0 *C 519.950 822.800 +*I cbx_1__2_:chanx_right_in[2] I *L 0 *C 512.290 822.800 + +*CAP +0 sb_1__2_:chanx_left_out[2] 0.0004894405 +1 cbx_1__2_:chanx_right_in[2] 0.0004894405 +2 sb_1__2_:chanx_left_out[2] sb_1__2_:chanx_left_in[10] 4.250762e-05 +3 cbx_1__2_:chanx_right_in[2] cbx_1__2_:chanx_right_out[10] 4.250762e-05 +4 sb_1__2_:chanx_left_out[2] sb_1__2_:chanx_left_in[12] 0.0001407067 +5 cbx_1__2_:chanx_right_in[2] cbx_1__2_:chanx_right_out[12] 0.0001407067 + +*RES +0 sb_1__2_:chanx_left_out[2] cbx_1__2_:chanx_right_in[2] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[7] 0.001359168 //LENGTH 7.660 LUMPCC 0.000500721 DR + +*CONN +*I sb_1__2_:chanx_left_out[7] O *L 0 *C 519.950 836.400 +*I cbx_1__2_:chanx_right_in[7] I *L 0 *C 512.290 836.400 + +*CAP +0 sb_1__2_:chanx_left_out[7] 0.0004292237 +1 cbx_1__2_:chanx_right_in[7] 0.0004292237 +2 sb_1__2_:chanx_left_out[7] sb_1__2_:chanx_left_in[5] 0.0001044988 +3 cbx_1__2_:chanx_right_in[7] cbx_1__2__0_chanx_right_out[5]:2 0.0001044988 +4 sb_1__2_:chanx_left_out[7] sb_1__2_:chanx_left_out[3] 0.0001458617 +5 cbx_1__2_:chanx_right_in[7] cbx_1__2_:chanx_right_in[3] 0.0001458617 + +*RES +0 sb_1__2_:chanx_left_out[7] cbx_1__2_:chanx_right_in[7] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[13] 0.001388351 //LENGTH 7.660 LUMPCC 0.0005752651 DR + +*CONN +*I sb_1__2_:chanx_left_out[13] O *L 0 *C 519.950 875.840 +*I cbx_1__2_:chanx_right_in[13] I *L 0 *C 512.290 875.840 + +*CAP +0 sb_1__2_:chanx_left_out[13] 0.000406543 +1 cbx_1__2_:chanx_right_in[13] 0.000406543 +2 sb_1__2_:chanx_left_out[13] sb_1__2_:chanx_left_out[8] 0.0001438163 +3 cbx_1__2_:chanx_right_in[13] cbx_1__2_:chanx_right_in[8] 0.0001438163 +4 sb_1__2_:chanx_left_out[13] sb_1__2_:chanx_left_out[19] 0.0001438163 +5 cbx_1__2_:chanx_right_in[13] cbx_1__2_:chanx_right_in[19] 0.0001438163 + +*RES +0 sb_1__2_:chanx_left_out[13] cbx_1__2_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_left_out[19] 0.001327115 //LENGTH 7.660 LUMPCC 0.0003788753 DR + +*CONN +*I sb_1__2_:chanx_left_out[19] O *L 0 *C 519.950 877.200 +*I cbx_1__2_:chanx_right_in[19] I *L 0 *C 512.290 877.200 + +*CAP +0 sb_1__2_:chanx_left_out[19] 0.0004741201 +1 cbx_1__2_:chanx_right_in[19] 0.0004741201 +2 sb_1__2_:chanx_left_out[19] sb_1__2_:chanx_left_out[13] 0.0001438163 +3 cbx_1__2_:chanx_right_in[19] cbx_1__2_:chanx_right_in[13] 0.0001438163 +4 sb_1__2_:chanx_left_out[19] sb_1__2_:chanx_left_out[17] 4.56214e-05 +5 cbx_1__2_:chanx_right_in[19] cbx_1__2_:chanx_right_in[17] 4.56214e-05 + +*RES +0 sb_1__2_:chanx_left_out[19] cbx_1__2_:chanx_right_in[19] 0.001200067 + +*END + +*D_NET sb_1__2__0_chanx_right_out[2] 0.001424367 //LENGTH 7.660 LUMPCC 0.0003669945 DR + +*CONN +*I sb_1__2_:chanx_right_out[2] O *L 0 *C 661.330 841.840 +*I cbx_2__2_:chanx_left_in[2] I *L 0 *C 668.990 841.840 +*N sb_1__2__0_chanx_right_out[2]:2 *C 667.520 841.840 +*N sb_1__2__0_chanx_right_out[2]:3 *C 667.519 841.840 + +*CAP +0 sb_1__2_:chanx_right_out[2] 0.0003093945 +1 cbx_2__2_:chanx_left_in[2] 0.0002192918 +2 sb_1__2__0_chanx_right_out[2]:2 0.0002192918 +3 sb_1__2__0_chanx_right_out[2]:3 0.0003093945 +4 sb_1__2_:chanx_right_out[2] sb_1__2_:chanx_right_in[15] 6.33524e-05 +5 sb_1__2__0_chanx_right_out[2]:3 cbx_1__2__1_chanx_left_out[15]:2 6.33524e-05 +6 sb_1__2_:chanx_right_out[2] sb_1__2_:chanx_right_out[10] 0.0001201449 +7 sb_1__2__0_chanx_right_out[2]:3 sb_1__2__0_chanx_right_out[10]:3 0.0001201449 + +*RES +0 sb_1__2_:chanx_right_out[2] sb_1__2__0_chanx_right_out[2]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[2]:2 cbx_2__2_:chanx_left_in[2] 0.0002303 +2 sb_1__2__0_chanx_right_out[2]:3 sb_1__2__0_chanx_right_out[2]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[8] 0.00139977 //LENGTH 7.660 LUMPCC 0.0004508587 DR + +*CONN +*I sb_1__2_:chanx_right_out[8] O *L 0 *C 661.330 874.480 +*I cbx_2__2_:chanx_left_in[8] I *L 0 *C 668.990 874.480 +*N sb_1__2__0_chanx_right_out[8]:2 *C 667.520 874.480 +*N sb_1__2__0_chanx_right_out[8]:3 *C 667.519 874.480 + +*CAP +0 sb_1__2_:chanx_right_out[8] 0.0002673571 +1 cbx_2__2_:chanx_left_in[8] 0.0002070988 +2 sb_1__2__0_chanx_right_out[8]:2 0.0002070988 +3 sb_1__2__0_chanx_right_out[8]:3 0.0002673571 +4 sb_1__2_:chanx_right_out[8] sb_1__2_:chanx_right_in[0] 7.500139e-05 +5 sb_1__2__0_chanx_right_out[8]:3 cbx_1__2__1_chanx_left_out[0]:2 7.500139e-05 +6 sb_1__2_:chanx_right_out[8] sb_1__2_:chanx_right_out[6] 0.000125179 +7 cbx_2__2_:chanx_left_in[8] cbx_2__2_:chanx_left_in[6] 1.643599e-06 +8 sb_1__2__0_chanx_right_out[8]:2 sb_1__2__0_chanx_right_out[6]:2 1.643599e-06 +9 sb_1__2__0_chanx_right_out[8]:3 sb_1__2__0_chanx_right_out[6]:3 0.000125179 +10 sb_1__2_:chanx_right_out[8] sb_1__2_:chanx_right_out[17] 2.360538e-05 +11 sb_1__2__0_chanx_right_out[8]:3 sb_1__2__0_chanx_right_out[17]:3 2.360538e-05 + +*RES +0 sb_1__2_:chanx_right_out[8] sb_1__2__0_chanx_right_out[8]:3 0.00096961 +1 sb_1__2__0_chanx_right_out[8]:2 cbx_2__2_:chanx_left_in[8] 0.0002303 +2 sb_1__2__0_chanx_right_out[8]:3 sb_1__2__0_chanx_right_out[8]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[13] 0.001348999 //LENGTH 7.660 LUMPCC 0.0004158643 DR + +*CONN +*I sb_1__2_:chanx_right_out[13] O *L 0 *C 661.330 855.440 +*I cbx_2__2_:chanx_left_in[13] I *L 0 *C 668.990 855.440 +*N sb_1__2__0_chanx_right_out[13]:2 *C 667.520 855.440 +*N sb_1__2__0_chanx_right_out[13]:3 *C 667.519 855.440 + +*CAP +0 sb_1__2_:chanx_right_out[13] 0.0002924699 +1 cbx_2__2_:chanx_left_in[13] 0.0001740976 +2 sb_1__2__0_chanx_right_out[13]:2 0.0001740976 +3 sb_1__2__0_chanx_right_out[13]:3 0.0002924699 +4 sb_1__2_:chanx_right_out[13] sb_1__2_:chanx_right_out[15] 0.0001349142 +5 cbx_2__2_:chanx_left_in[13] cbx_2__2_:chanx_left_in[15] 9.863077e-06 +6 sb_1__2__0_chanx_right_out[13]:2 sb_1__2__0_chanx_right_out[15]:2 9.863077e-06 +7 sb_1__2__0_chanx_right_out[13]:3 sb_1__2__0_chanx_right_out[15]:3 0.0001349142 +8 sb_1__2_:chanx_right_out[13] sb_1__2_:chanx_right_out[16] 6.315485e-05 +9 sb_1__2__0_chanx_right_out[13]:3 sb_1__2__0_chanx_right_out[16]:3 6.315485e-05 + +*RES +0 sb_1__2_:chanx_right_out[13] sb_1__2__0_chanx_right_out[13]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[13]:2 cbx_2__2_:chanx_left_in[13] 0.0002303 +2 sb_1__2__0_chanx_right_out[13]:3 sb_1__2__0_chanx_right_out[13]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chanx_right_out[19] 0.001506263 //LENGTH 7.660 LUMPCC 0.0004969742 DR + +*CONN +*I sb_1__2_:chanx_right_out[19] O *L 0 *C 661.330 835.040 +*I cbx_2__2_:chanx_left_in[19] I *L 0 *C 668.990 835.040 +*N sb_1__2__0_chanx_right_out[19]:2 *C 667.520 835.040 +*N sb_1__2__0_chanx_right_out[19]:3 *C 667.519 835.040 + +*CAP +0 sb_1__2_:chanx_right_out[19] 0.0002869969 +1 cbx_2__2_:chanx_left_in[19] 0.0002176477 +2 sb_1__2__0_chanx_right_out[19]:2 0.0002176477 +3 sb_1__2__0_chanx_right_out[19]:3 0.0002869969 +4 sb_1__2_:chanx_right_out[19] sb_1__2_:chanx_right_out[1] 0.0001261708 +5 cbx_2__2_:chanx_left_in[19] cbx_2__2_:chanx_left_in[1] 1.644113e-06 +6 sb_1__2__0_chanx_right_out[19]:2 sb_1__2__0_chanx_right_out[1]:2 1.644113e-06 +7 sb_1__2__0_chanx_right_out[19]:3 sb_1__2__0_chanx_right_out[1]:3 0.0001261708 +8 sb_1__2_:chanx_right_out[19] sb_1__2_:chanx_right_out[9] 0.0001206722 +9 sb_1__2__0_chanx_right_out[19]:3 sb_1__2__0_chanx_right_out[9]:3 0.0001206722 + +*RES +0 sb_1__2_:chanx_right_out[19] sb_1__2__0_chanx_right_out[19]:3 0.0009696099 +1 sb_1__2__0_chanx_right_out[19]:2 cbx_2__2_:chanx_left_in[19] 0.0002303 +2 sb_1__2__0_chanx_right_out[19]:3 sb_1__2__0_chanx_right_out[19]:2 1e-05 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[5] 0.001242077 //LENGTH 11.020 LUMPCC 0.0004209518 DR + +*CONN +*I sb_1__2_:chany_bottom_out[5] O *L 0 *C 591.560 788.870 +*I cby_1__2_:chany_top_in[5] I *L 0 *C 591.560 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[5] 0.0004105628 +1 cby_1__2_:chany_top_in[5] 0.0004105628 +2 sb_1__2_:chany_bottom_out[5] sb_1__2_:chany_bottom_out[18] 7.69995e-05 +3 cby_1__2_:chany_top_in[5] cby_1__2_:chany_top_in[18] 7.69995e-05 +4 sb_1__2_:chany_bottom_out[5] sb_1__2_:chany_bottom_out[19] 0.0001334764 +5 cby_1__2_:chany_top_in[5] cby_1__2_:chany_top_in[19] 0.0001334764 + +*RES +0 sb_1__2_:chany_bottom_out[5] cby_1__2_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[8] 0.001274636 //LENGTH 11.020 LUMPCC 0.0005229456 DR + +*CONN +*I sb_1__2_:chany_bottom_out[8] O *L 0 *C 583.280 788.870 +*I cby_1__2_:chany_top_in[8] I *L 0 *C 583.280 777.850 + +*CAP +0 sb_1__2_:chany_bottom_out[8] 0.0003758454 +1 cby_1__2_:chany_top_in[8] 0.0003758454 +2 sb_1__2_:chany_bottom_out[8] sb_1__2_:chany_bottom_in[10] 0.0001298917 +3 cby_1__2_:chany_top_in[8] cby_1__2_:chany_top_out[10] 0.0001298917 +4 sb_1__2_:chany_bottom_out[8] sb_1__2_:chany_bottom_out[16] 0.0001315811 +5 cby_1__2_:chany_top_in[8] cby_1__2_:chany_top_in[16] 0.0001315811 + +*RES +0 sb_1__2_:chany_bottom_out[8] cby_1__2_:chany_top_in[8] 0.009839286 + +*END + +*D_NET sb_1__2__0_chany_bottom_out[14] 0.001773558 //LENGTH 15.060 LUMPCC 0.0005544776 DR + +*CONN +*I sb_1__2_:chany_bottom_out[14] O *L 0 *C 617.320 788.870 +*I cby_1__2_:chany_top_in[14] I *L 0 *C 617.320 777.850 +*N sb_1__2__0_chany_bottom_out[14]:2 *C 617.320 779.915 +*N sb_1__2__0_chany_bottom_out[14]:3 *C 617.275 779.960 +*N sb_1__2__0_chany_bottom_out[14]:4 *C 615.985 779.960 +*N sb_1__2__0_chany_bottom_out[14]:5 *C 615.940 780.005 +*N sb_1__2__0_chany_bottom_out[14]:6 *C 615.940 785.015 +*N sb_1__2__0_chany_bottom_out[14]:7 *C 615.985 785.060 +*N sb_1__2__0_chany_bottom_out[14]:8 *C 617.275 785.060 +*N sb_1__2__0_chany_bottom_out[14]:9 *C 617.320 785.105 + +*CAP +0 sb_1__2_:chany_bottom_out[14] 0.0001442552 +1 cby_1__2_:chany_top_in[14] 0.0001412671 +2 sb_1__2__0_chany_bottom_out[14]:2 0.0001412671 +3 sb_1__2__0_chany_bottom_out[14]:3 0.0001027359 +4 sb_1__2__0_chany_bottom_out[14]:4 0.0001027359 +5 sb_1__2__0_chany_bottom_out[14]:5 0.0001522659 +6 sb_1__2__0_chany_bottom_out[14]:6 0.0001522659 +7 sb_1__2__0_chany_bottom_out[14]:7 6.901596e-05 +8 sb_1__2__0_chany_bottom_out[14]:8 6.901596e-05 +9 sb_1__2__0_chany_bottom_out[14]:9 0.0001442552 +10 sb_1__2__0_chany_bottom_out[14]:5 cby_1__2_:chany_top_out[6] 2.944697e-05 +11 sb_1__2__0_chany_bottom_out[14]:6 sb_1__2_:chany_bottom_in[6] 2.944697e-05 +12 sb_1__2__0_chany_bottom_out[14]:7 direct_interc_5_out[0]:12 3.082647e-05 +13 sb_1__2__0_chany_bottom_out[14]:8 direct_interc_5_out[0]:11 3.082647e-05 +14 sb_1__2_:chany_bottom_out[14] sb_1__2_:chany_bottom_out[4] 5.599678e-05 +15 cby_1__2_:chany_top_in[14] cby_1__2_:chany_top_in[4] 1.488356e-05 +16 sb_1__2__0_chany_bottom_out[14]:2 sb_1__2_:chany_bottom_out[4] 1.488356e-05 +17 sb_1__2__0_chany_bottom_out[14]:5 cby_1__2_:chany_top_in[4] 0.000146085 +18 sb_1__2__0_chany_bottom_out[14]:6 sb_1__2_:chany_bottom_out[4] 0.000146085 +19 sb_1__2__0_chany_bottom_out[14]:9 cby_1__2_:chany_top_in[4] 5.599678e-05 + +*RES +0 sb_1__2_:chany_bottom_out[14] sb_1__2__0_chany_bottom_out[14]:9 0.003361607 +1 sb_1__2__0_chany_bottom_out[14]:3 sb_1__2__0_chany_bottom_out[14]:2 0.0045 +2 sb_1__2__0_chany_bottom_out[14]:2 cby_1__2_:chany_top_in[14] 0.00184375 +3 sb_1__2__0_chany_bottom_out[14]:4 sb_1__2__0_chany_bottom_out[14]:3 0.001151786 +4 sb_1__2__0_chany_bottom_out[14]:5 sb_1__2__0_chany_bottom_out[14]:4 0.0045 +5 sb_1__2__0_chany_bottom_out[14]:7 sb_1__2__0_chany_bottom_out[14]:6 0.0045 +6 sb_1__2__0_chany_bottom_out[14]:6 sb_1__2__0_chany_bottom_out[14]:5 0.004473215 +7 sb_1__2__0_chany_bottom_out[14]:8 sb_1__2__0_chany_bottom_out[14]:7 0.001151786 +8 sb_1__2__0_chany_bottom_out[14]:9 sb_1__2__0_chany_bottom_out[14]:8 0.0045 + +*END + +*D_NET sb_2__0__0_chanx_left_out[1] 0.001406199 //LENGTH 7.660 LUMPCC 0.0003731509 DR + +*CONN +*I sb_2__0_:chanx_left_out[1] O *L 0 *C 781.230 358.360 +*I cbx_2__0_:chanx_right_in[1] I *L 0 *C 773.570 358.360 + +*CAP +0 sb_2__0_:chanx_left_out[1] 0.0005165242 +1 cbx_2__0_:chanx_right_in[1] 0.0005165242 +2 sb_2__0_:chanx_left_out[1] sb_2__0_:chanx_left_in[4] 6.34922e-05 +3 cbx_2__0_:chanx_right_in[1] cbx_1__0__1_chanx_right_out[4]:2 6.34922e-05 +4 sb_2__0_:chanx_left_out[1] sb_2__0_:chanx_left_out[13] 0.0001230833 +5 cbx_2__0_:chanx_right_in[1] cbx_2__0_:chanx_right_in[13] 0.0001230833 + +*RES +0 sb_2__0_:chanx_left_out[1] cbx_2__0_:chanx_right_in[1] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[6] 0.001433882 //LENGTH 7.660 LUMPCC 0.0003670202 DR + +*CONN +*I sb_2__0_:chanx_left_out[6] O *L 0 *C 781.230 319.600 +*I cbx_2__0_:chanx_right_in[6] I *L 0 *C 773.570 319.600 + +*CAP +0 sb_2__0_:chanx_left_out[6] 0.0005334311 +1 cbx_2__0_:chanx_right_in[6] 0.0005334311 +2 sb_2__0_:chanx_left_out[6] sb_2__0_:chanx_left_out[0] 0.0001193483 +3 cbx_2__0_:chanx_right_in[6] cbx_2__0_:chanx_right_in[0] 0.0001193483 +4 sb_2__0_:chanx_left_out[6] sb_2__0_:chanx_left_out[12] 6.41618e-05 +5 cbx_2__0_:chanx_right_in[6] cbx_2__0_:chanx_right_in[12] 6.41618e-05 + +*RES +0 sb_2__0_:chanx_left_out[6] cbx_2__0_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[12] 0.001372227 //LENGTH 7.660 LUMPCC 0.0004037806 DR + +*CONN +*I sb_2__0_:chanx_left_out[12] O *L 0 *C 781.230 316.880 +*I cbx_2__0_:chanx_right_in[12] I *L 0 *C 773.570 316.880 + +*CAP +0 sb_2__0_:chanx_left_out[12] 0.000484223 +1 cbx_2__0_:chanx_right_in[12] 0.000484223 +2 sb_2__0_:chanx_left_out[12] sb_2__0_:chanx_left_out[6] 6.41618e-05 +3 cbx_2__0_:chanx_right_in[12] cbx_2__0_:chanx_right_in[6] 6.41618e-05 +4 sb_2__0_:chanx_left_out[12] sb_2__0_:chanx_left_out[8] 0.0001377285 +5 cbx_2__0_:chanx_right_in[12] cbx_2__0_:chanx_right_in[8] 0.0001377285 + +*RES +0 sb_2__0_:chanx_left_out[12] cbx_2__0_:chanx_right_in[12] 0.001200067 + +*END + +*D_NET sb_2__0__0_chanx_left_out[15] 0.001338445 //LENGTH 7.660 LUMPCC 0.00041086 DR + +*CONN +*I sb_2__0_:chanx_left_out[15] O *L 0 *C 781.230 333.200 +*I cbx_2__0_:chanx_right_in[15] I *L 0 *C 773.570 333.200 + +*CAP +0 sb_2__0_:chanx_left_out[15] 0.0004637924 +1 cbx_2__0_:chanx_right_in[15] 0.0004637924 +2 sb_2__0_:chanx_left_out[15] sb_2__0_:chanx_left_in[15] 6.180091e-05 +3 cbx_2__0_:chanx_right_in[15] cbx_2__0_:chanx_right_out[15] 6.180091e-05 +4 sb_2__0_:chanx_left_out[15] sb_2__0_:chanx_left_out[11] 0.0001436291 +5 cbx_2__0_:chanx_right_in[15] cbx_2__0_:chanx_right_in[11] 0.0001436291 + +*RES +0 sb_2__0_:chanx_left_out[15] cbx_2__0_:chanx_right_in[15] 0.001200067 + +*END + +*D_NET sb_2__0__0_chany_top_out[2] 0.00123291 //LENGTH 11.020 LUMPCC 0.0005893015 DR + +*CONN +*I sb_2__0_:chany_top_out[2] O *L 0 *C 858.820 397.050 +*I cby_2__1_:chany_bottom_in[2] I *L 0 *C 858.820 408.070 + +*CAP +0 sb_2__0_:chany_top_out[2] 0.0003218045 +1 cby_2__1_:chany_bottom_in[2] 0.0003218045 +2 sb_2__0_:chany_top_out[2] sb_2__0_:chany_top_out[0] 0.0001479301 +3 cby_2__1_:chany_bottom_in[2] cby_2__1_:chany_bottom_in[0] 0.0001479301 +4 sb_2__0_:chany_top_out[2] sb_2__0_:chany_top_out[19] 0.0001467206 +5 cby_2__1_:chany_bottom_in[2] cby_2__1_:chany_bottom_in[19] 0.0001467206 + +*RES +0 sb_2__0_:chany_top_out[2] cby_2__1_:chany_bottom_in[2] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[5] 0.00117803 //LENGTH 11.020 LUMPCC 0.0004861848 DR + +*CONN +*I sb_2__0_:chany_top_out[5] O *L 0 *C 864.800 397.050 +*I cby_2__1_:chany_bottom_in[5] I *L 0 *C 864.800 408.070 + +*CAP +0 sb_2__0_:chany_top_out[5] 0.0003459226 +1 cby_2__1_:chany_bottom_in[5] 0.0003459226 +2 sb_2__0_:chany_top_out[5] sb_2__0_:chany_top_in[2] 9.094577e-05 +3 cby_2__1_:chany_bottom_in[5] cby_2__1_:chany_bottom_out[2] 9.094577e-05 +4 sb_2__0_:chany_top_out[5] sb_2__0_:chany_top_in[18] 0.0001521467 +5 cby_2__1_:chany_bottom_in[5] cby_2__1_:chany_bottom_out[18] 0.0001521467 + +*RES +0 sb_2__0_:chany_top_out[5] cby_2__1_:chany_bottom_in[5] 0.009839286 + +*END + +*D_NET sb_2__0__0_chany_top_out[10] 0.00122219 //LENGTH 11.020 LUMPCC 0.000598586 DR + +*CONN +*I sb_2__0_:chany_top_out[10] O *L 0 *C 877.680 397.050 +*I cby_2__1_:chany_bottom_in[10] I *L 0 *C 877.680 408.070 + +*CAP +0 sb_2__0_:chany_top_out[10] 0.0003118021 +1 cby_2__1_:chany_bottom_in[10] 0.0003118021 +2 sb_2__0_:chany_top_out[10] sb_2__0_:chany_top_out[14] 0.0001496465 +3 cby_2__1_:chany_bottom_in[10] cby_2__1_:chany_bottom_in[14] 0.0001496465 +4 sb_2__0_:chany_top_out[10] sb_2__0_:chany_top_out[18] 0.0001496465 +5 cby_2__1_:chany_bottom_in[10] cby_2__1_:chany_bottom_in[18] 0.0001496465 + +*RES +0 sb_2__0_:chany_top_out[10] cby_2__1_:chany_bottom_in[10] 0.009839285 + +*END + +*D_NET sb_2__0__0_chany_top_out[15] 0.001309885 //LENGTH 11.020 LUMPCC 0.0006723251 DR + +*CONN +*I sb_2__0_:chany_top_out[15] O *L 0 *C 832.140 397.050 +*I cby_2__1_:chany_bottom_in[15] I *L 0 *C 832.140 408.070 + +*CAP +0 sb_2__0_:chany_top_out[15] 0.00031878 +1 cby_2__1_:chany_bottom_in[15] 0.00031878 +2 sb_2__0_:chany_top_out[15] sb_2__0_:chany_top_in[4] 0.000147909 +3 cby_2__1_:chany_bottom_in[15] cby_2__1_:chany_bottom_out[4] 0.000147909 +4 sb_2__0_:chany_top_out[15] sb_2__0_:chany_top_out[7] 2.585697e-05 +5 sb_2__0_:chany_top_out[15] sb_2__0__0_chany_top_out[7]:2 1.431606e-05 +6 sb_2__0_:chany_top_out[15] sb_2__0__0_chany_top_out[7]:4 0.0001480805 +7 cby_2__1_:chany_bottom_in[15] cby_2__1_:chany_bottom_in[7] 1.431606e-05 +8 cby_2__1_:chany_bottom_in[15] sb_2__0__0_chany_top_out[7]:3 0.0001480805 +9 cby_2__1_:chany_bottom_in[15] sb_2__0__0_chany_top_out[7]:5 2.585697e-05 + +*RES +0 sb_2__0_:chany_top_out[15] cby_2__1_:chany_bottom_in[15] 0.009839285 + +*END + +*D_NET sb_2__1__0_chanx_left_out[0] 0.001351255 //LENGTH 7.660 LUMPCC 0.0002078916 DR + +*CONN +*I sb_2__1_:chanx_left_out[0] O *L 0 *C 781.230 588.880 +*I cbx_2__1_:chanx_right_in[0] I *L 0 *C 773.570 588.880 + +*CAP +0 sb_2__1_:chanx_left_out[0] 0.0005716815 +1 cbx_2__1_:chanx_right_in[0] 0.0005716815 +2 sb_2__1_:chanx_left_out[0] sb_2__1_:chanx_left_in[10] 7.055791e-05 +3 cbx_2__1_:chanx_right_in[0] cbx_2__1_:chanx_right_out[10] 7.055791e-05 +4 sb_2__1_:chanx_left_out[0] sb_2__1_:ccff_tail[0] 3.338791e-05 +5 cbx_2__1_:chanx_right_in[0] cbx_2__1_:ccff_head[0] 3.338791e-05 + +*RES +0 sb_2__1_:chanx_left_out[0] cbx_2__1_:chanx_right_in[0] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[4] 0.001461064 //LENGTH 7.660 LUMPCC 0.0003163072 DR + +*CONN +*I sb_2__1_:chanx_left_out[4] O *L 0 *C 781.230 607.920 +*I cbx_2__1_:chanx_right_in[4] I *L 0 *C 773.570 607.920 + +*CAP +0 sb_2__1_:chanx_left_out[4] 0.0005723782 +1 cbx_2__1_:chanx_right_in[4] 0.0005723782 +2 sb_2__1_:chanx_left_out[4] sb_2__1_:chanx_left_in[15] 3.831551e-05 +3 cbx_2__1_:chanx_right_in[4] cbx_2__1_:chanx_right_out[15] 3.831551e-05 +4 sb_2__1_:chanx_left_out[4] sb_2__1_:chanx_left_out[1] 0.0001198381 +5 cbx_2__1_:chanx_right_in[4] cbx_2__1_:chanx_right_in[1] 0.0001198381 + +*RES +0 sb_2__1_:chanx_left_out[4] cbx_2__1_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[13] 0.00142889 //LENGTH 7.660 LUMPCC 0.0002050403 DR + +*CONN +*I sb_2__1_:chanx_left_out[13] O *L 0 *C 781.230 626.960 +*I cbx_2__1_:chanx_right_in[13] I *L 0 *C 773.570 626.960 + +*CAP +0 sb_2__1_:chanx_left_out[13] 0.0006119247 +1 cbx_2__1_:chanx_right_in[13] 0.0006119247 +2 sb_2__1_:chanx_left_out[13] sb_2__1_:chanx_left_in[12] 0.0001025201 +3 cbx_2__1_:chanx_right_in[13] cbx_2__1_:chanx_right_out[12] 0.0001025201 + +*RES +0 sb_2__1_:chanx_left_out[13] cbx_2__1_:chanx_right_in[13] 0.001200067 + +*END + +*D_NET sb_2__1__0_chanx_left_out[14] 0.00147798 //LENGTH 7.660 LUMPCC 0.0004796836 DR + +*CONN +*I sb_2__1_:chanx_left_out[14] O *L 0 *C 781.230 582.080 +*I cbx_2__1_:chanx_right_in[14] I *L 0 *C 773.570 582.080 + +*CAP +0 sb_2__1_:chanx_left_out[14] 0.0004991484 +1 cbx_2__1_:chanx_right_in[14] 0.0004991484 +2 sb_2__1_:chanx_left_out[14] sb_2__1_:chanx_left_in[17] 0.0001162038 +3 cbx_2__1_:chanx_right_in[14] cbx_2__1_:chanx_right_out[17] 0.0001162038 +4 sb_2__1_:chanx_left_out[14] sb_2__1_:chanx_left_out[10] 0.000123638 +5 cbx_2__1_:chanx_right_in[14] cbx_2__1_:chanx_right_in[10] 0.000123638 + +*RES +0 sb_2__1_:chanx_left_out[14] cbx_2__1_:chanx_right_in[14] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[1] 0.001276208 //LENGTH 11.020 LUMPCC 0.0005337231 DR + +*CONN +*I sb_2__1_:chany_bottom_out[1] O *L 0 *C 840.880 527.750 +*I cby_2__1_:chany_top_in[1] I *L 0 *C 840.880 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[1] 0.0003712427 +1 cby_2__1_:chany_top_in[1] 0.0003712427 +2 sb_2__1_:chany_bottom_out[1] sb_2__1_:chany_bottom_out[7] 0.0001334308 +3 cby_2__1_:chany_top_in[1] cby_2__1_:chany_top_in[7] 0.0001334308 +4 sb_2__1_:chany_bottom_out[1] sb_2__1_:chany_bottom_out[17] 0.0001334308 +5 cby_2__1_:chany_top_in[1] cby_2__1_:chany_top_in[17] 0.0001334308 + +*RES +0 sb_2__1_:chany_bottom_out[1] cby_2__1_:chany_top_in[1] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[4] 0.001202747 //LENGTH 11.020 LUMPCC 0.0003229759 DR + +*CONN +*I sb_2__1_:chany_bottom_out[4] O *L 0 *C 877.680 527.750 +*I cby_2__1_:chany_top_in[4] I *L 0 *C 877.680 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[4] 0.0004398858 +1 cby_2__1_:chany_top_in[4] 0.0004398858 +2 sb_2__1_:chany_bottom_out[4] sb_2__1_:chany_bottom_in[6] 2.678904e-05 +3 cby_2__1_:chany_top_in[4] cby_2__1_:chany_top_out[6] 2.678904e-05 +4 sb_2__1_:chany_bottom_out[4] sb_2__1_:chany_bottom_out[14] 0.0001346989 +5 cby_2__1_:chany_top_in[4] cby_2__1_:chany_top_in[14] 0.0001346989 + +*RES +0 sb_2__1_:chany_bottom_out[4] cby_2__1_:chany_top_in[4] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[11] 0.001278076 //LENGTH 11.020 LUMPCC 0.0005354166 DR + +*CONN +*I sb_2__1_:chany_bottom_out[11] O *L 0 *C 855.140 527.750 +*I cby_2__1_:chany_top_in[11] I *L 0 *C 855.140 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[11] 0.0003713297 +1 cby_2__1_:chany_top_in[11] 0.0003713297 +2 sb_2__1_:chany_bottom_out[11] sb_2__1_:chany_bottom_out[6] 0.0001338541 +3 cby_2__1_:chany_top_in[11] cby_2__1_:chany_top_in[6] 0.0001338541 +4 sb_2__1_:chany_bottom_out[11] sb_2__1_:chany_bottom_out[18] 0.0001338541 +5 cby_2__1_:chany_top_in[11] cby_2__1_:chany_top_in[18] 0.0001338541 + +*RES +0 sb_2__1_:chany_bottom_out[11] cby_2__1_:chany_top_in[11] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[16] 0.001261363 //LENGTH 11.020 LUMPCC 0.0005510945 DR + +*CONN +*I sb_2__1_:chany_bottom_out[16] O *L 0 *C 845.480 527.750 +*I cby_2__1_:chany_top_in[16] I *L 0 *C 845.480 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[16] 0.0003551343 +1 cby_2__1_:chany_top_in[16] 0.0003551343 +2 sb_2__1_:chany_bottom_out[16] sb_2__1_:chany_bottom_in[4] 0.0001377736 +3 cby_2__1_:chany_top_in[16] cby_2__1_:chany_top_out[4] 0.0001377736 +4 sb_2__1_:chany_bottom_out[16] sb_2__1_:chany_bottom_out[8] 0.0001377736 +5 cby_2__1_:chany_top_in[16] cby_2__1_:chany_top_in[8] 0.0001377736 + +*RES +0 sb_2__1_:chany_bottom_out[16] cby_2__1_:chany_top_in[16] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[0] 0.001256403 //LENGTH 11.020 LUMPCC 0.0005526695 DR + +*CONN +*I sb_2__1_:chany_top_out[0] O *L 0 *C 857.900 658.170 +*I cby_2__2_:chany_bottom_in[0] I *L 0 *C 857.900 669.190 +*N sb_2__1__0_chany_top_out[0]:2 *C 857.900 667.520 +*N sb_2__1__0_chany_top_out[0]:3 *C 857.900 667.519 + +*CAP +0 sb_2__1_:chany_top_out[0] 0.0002409292 +1 cby_2__2_:chany_bottom_in[0] 0.0001109373 +2 sb_2__1__0_chany_top_out[0]:2 0.0001109373 +3 sb_2__1__0_chany_top_out[0]:3 0.0002409292 +4 sb_2__1_:chany_top_out[0] sb_2__1_:chany_top_in[11] 0.0001306982 +5 cby_2__2_:chany_bottom_in[0] cby_2__2_:chany_bottom_out[11] 7.340376e-06 +6 sb_2__1__0_chany_top_out[0]:2 cby_1__1__3_chany_bottom_out[11]:3 7.340376e-06 +7 sb_2__1__0_chany_top_out[0]:3 cby_1__1__3_chany_bottom_out[11]:2 0.0001306982 +8 sb_2__1_:chany_top_out[0] sb_2__1_:chany_top_out[2] 0.0001309558 +9 cby_2__2_:chany_bottom_in[0] cby_2__2_:chany_bottom_in[2] 7.340376e-06 +10 sb_2__1__0_chany_top_out[0]:2 sb_2__1__0_chany_top_out[2]:2 7.340376e-06 +11 sb_2__1__0_chany_top_out[0]:3 sb_2__1__0_chany_top_out[2]:3 0.0001309558 + +*RES +0 sb_2__1_:chany_top_out[0] sb_2__1__0_chany_top_out[0]:3 0.008347321 +1 sb_2__1__0_chany_top_out[0]:2 cby_2__2_:chany_bottom_in[0] 0.001491072 +2 sb_2__1__0_chany_top_out[0]:3 sb_2__1__0_chany_top_out[0]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[8] 0.001265445 //LENGTH 11.020 LUMPCC 0.0005421289 DR + +*CONN +*I sb_2__1_:chany_top_out[8] O *L 0 *C 849.620 658.170 +*I cby_2__2_:chany_bottom_in[8] I *L 0 *C 849.620 669.190 +*N sb_2__1__0_chany_top_out[8]:2 *C 849.620 667.520 +*N sb_2__1__0_chany_top_out[8]:3 *C 849.620 667.519 + +*CAP +0 sb_2__1_:chany_top_out[8] 0.0002505166 +1 cby_2__2_:chany_bottom_in[8] 0.0001111417 +2 sb_2__1__0_chany_top_out[8]:2 0.0001111417 +3 sb_2__1__0_chany_top_out[8]:3 0.0002505166 +4 sb_2__1_:chany_top_out[8] sb_2__1_:chany_top_in[9] 0.0001283662 +5 cby_2__2_:chany_bottom_in[8] cby_2__2_:chany_bottom_out[9] 7.294814e-06 +6 sb_2__1__0_chany_top_out[8]:2 cby_1__1__3_chany_bottom_out[9]:3 7.294814e-06 +7 sb_2__1__0_chany_top_out[8]:3 cby_1__1__3_chany_bottom_out[9]:2 0.0001283662 +8 sb_2__1_:chany_top_out[8] sb_2__1_:chany_top_in[16] 0.0001281086 +9 cby_2__2_:chany_bottom_in[8] cby_2__2_:chany_bottom_out[16] 7.294814e-06 +10 sb_2__1__0_chany_top_out[8]:2 cby_1__1__3_chany_bottom_out[16]:3 7.294814e-06 +11 sb_2__1__0_chany_top_out[8]:3 cby_1__1__3_chany_bottom_out[16]:2 0.0001281086 + +*RES +0 sb_2__1_:chany_top_out[8] sb_2__1__0_chany_top_out[8]:3 0.008347321 +1 sb_2__1__0_chany_top_out[8]:2 cby_2__2_:chany_bottom_in[8] 0.001491072 +2 sb_2__1__0_chany_top_out[8]:3 sb_2__1__0_chany_top_out[8]:2 1e-05 + +*END + +*D_NET sb_2__1__0_chany_top_out[12] 0.001263428 //LENGTH 11.020 LUMPCC 0.0005480482 DR + +*CONN +*I sb_2__1_:chany_top_out[12] O *L 0 *C 860.660 658.170 +*I cby_2__2_:chany_bottom_in[12] I *L 0 *C 860.660 669.190 +*N sb_2__1__0_chany_top_out[12]:2 *C 860.660 667.520 +*N sb_2__1__0_chany_top_out[12]:3 *C 860.660 667.519 + +*CAP +0 sb_2__1_:chany_top_out[12] 0.0002465935 +1 cby_2__2_:chany_bottom_in[12] 0.0001110966 +2 sb_2__1__0_chany_top_out[12]:2 0.0001110966 +3 sb_2__1__0_chany_top_out[12]:3 0.0002465935 +4 sb_2__1_:chany_top_out[12] sb_2__1_:chany_top_in[0] 0.0001284326 +5 cby_2__2_:chany_bottom_in[12] cby_2__2_:chany_bottom_out[0] 7.295327e-06 +6 sb_2__1__0_chany_top_out[12]:2 cby_1__1__3_chany_bottom_out[0]:3 7.295327e-06 +7 sb_2__1__0_chany_top_out[12]:3 cby_1__1__3_chany_bottom_out[0]:2 0.0001284326 +8 sb_2__1_:chany_top_out[12] sb_2__1_:chany_top_out[19] 0.0001309558 +9 cby_2__2_:chany_bottom_in[12] cby_2__2_:chany_bottom_in[19] 7.340376e-06 +10 sb_2__1__0_chany_top_out[12]:2 sb_2__1__0_chany_top_out[19]:2 7.340376e-06 +11 sb_2__1__0_chany_top_out[12]:3 sb_2__1__0_chany_top_out[19]:3 0.0001309558 + +*RES +0 sb_2__1_:chany_top_out[12] sb_2__1__0_chany_top_out[12]:3 0.008347321 +1 sb_2__1__0_chany_top_out[12]:2 cby_2__2_:chany_bottom_in[12] 0.001491072 +2 sb_2__1__0_chany_top_out[12]:3 sb_2__1__0_chany_top_out[12]:2 1e-05 + +*END + +*D_NET sb_2__2__0_ccff_tail[0] 0.001343183 //LENGTH 7.660 LUMPCC 0.0003988603 DR + +*CONN +*I sb_2__2_:ccff_tail[0] O *L 0 *C 781.230 866.320 +*I cbx_2__2_:ccff_head[0] I *L 0 *C 773.570 866.320 + +*CAP +0 sb_2__2_:ccff_tail[0] 0.0004721613 +1 cbx_2__2_:ccff_head[0] 0.0004721613 +2 sb_2__2_:ccff_tail[0] sb_2__2_:chanx_left_in[8] 0.0001405625 +3 cbx_2__2_:ccff_head[0] cbx_2__2_:chanx_right_out[8] 0.0001405625 +4 sb_2__2_:ccff_tail[0] sb_2__2_:chanx_left_out[0] 5.886764e-05 +5 cbx_2__2_:ccff_head[0] cbx_2__2_:chanx_right_in[0] 5.886764e-05 + +*RES +0 sb_2__2_:ccff_tail[0] cbx_2__2_:ccff_head[0] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[4] 0.001323514 //LENGTH 7.660 LUMPCC 0.0004150299 DR + +*CONN +*I sb_2__2_:chanx_left_out[4] O *L 0 *C 781.230 847.280 +*I cbx_2__2_:chanx_right_in[4] I *L 0 *C 773.570 847.280 + +*CAP +0 sb_2__2_:chanx_left_out[4] 0.0004542423 +1 cbx_2__2_:chanx_right_in[4] 0.0004542423 +2 sb_2__2_:chanx_left_out[4] sb_2__2_:chanx_left_in[14] 0.0001451917 +3 cbx_2__2_:chanx_right_in[4] cbx_2__2_:chanx_right_out[14] 0.0001451917 +4 sb_2__2_:chanx_left_out[4] sb_2__2_:chanx_left_in[16] 6.232323e-05 +5 cbx_2__2_:chanx_right_in[4] cbx_2__2_:chanx_right_out[16] 6.232323e-05 + +*RES +0 sb_2__2_:chanx_left_out[4] cbx_2__2_:chanx_right_in[4] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[9] 0.001506693 //LENGTH 7.660 LUMPCC 0.0004963333 DR + +*CONN +*I sb_2__2_:chanx_left_out[9] O *L 0 *C 781.230 854.080 +*I cbx_2__2_:chanx_right_in[9] I *L 0 *C 773.570 854.080 + +*CAP +0 sb_2__2_:chanx_left_out[9] 0.00050518 +1 cbx_2__2_:chanx_right_in[9] 0.00050518 +2 sb_2__2_:chanx_left_out[9] sb_2__2_:chanx_left_in[11] 0.0001204394 +3 cbx_2__2_:chanx_right_in[9] cbx_2__2_:chanx_right_out[11] 0.0001204394 +4 sb_2__2_:chanx_left_out[9] sb_2__2_:chanx_left_out[18] 0.0001277273 +5 cbx_2__2_:chanx_right_in[9] cbx_2__2_:chanx_right_in[18] 0.0001277273 + +*RES +0 sb_2__2_:chanx_left_out[9] cbx_2__2_:chanx_right_in[9] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[16] 0.001509559 //LENGTH 7.660 LUMPCC 0.0004782571 DR + +*CONN +*I sb_2__2_:chanx_left_out[16] O *L 0 *C 781.230 843.200 +*I cbx_2__2_:chanx_right_in[16] I *L 0 *C 773.570 843.200 + +*CAP +0 sb_2__2_:chanx_left_out[16] 0.0005156508 +1 cbx_2__2_:chanx_right_in[16] 0.0005156508 +2 sb_2__2_:chanx_left_out[16] sb_2__2_:chanx_left_in[16] 0.0001192781 +3 cbx_2__2_:chanx_right_in[16] cbx_2__2_:chanx_right_out[16] 0.0001192781 +4 sb_2__2_:chanx_left_out[16] sb_2__2_:chanx_left_in[17] 0.0001198505 +5 cbx_2__2_:chanx_right_in[16] cbx_2__2_:chanx_right_out[17] 0.0001198505 + +*RES +0 sb_2__2_:chanx_left_out[16] cbx_2__2_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[1] 0.00125438 //LENGTH 11.020 LUMPCC 0.0005656789 DR + +*CONN +*I sb_2__2_:chany_bottom_out[1] O *L 0 *C 840.880 788.870 +*I cby_2__2_:chany_top_in[1] I *L 0 *C 840.880 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[1] 0.0003443506 +1 cby_2__2_:chany_top_in[1] 0.0003443506 +2 sb_2__2_:chany_bottom_out[1] sb_2__2_:chany_bottom_out[7] 0.0001414197 +3 cby_2__2_:chany_top_in[1] cby_2__2_:chany_top_in[7] 0.0001414197 +4 sb_2__2_:chany_bottom_out[1] sb_2__2_:chany_bottom_out[17] 0.0001414197 +5 cby_2__2_:chany_top_in[1] cby_2__2_:chany_top_in[17] 0.0001414197 + +*RES +0 sb_2__2_:chany_bottom_out[1] cby_2__2_:chany_top_in[1] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[5] 0.001212385 //LENGTH 11.020 LUMPCC 0.0004637854 DR + +*CONN +*I sb_2__2_:chany_bottom_out[5] O *L 0 *C 852.840 788.870 +*I cby_2__2_:chany_top_in[5] I *L 0 *C 852.840 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[5] 0.0003743001 +1 cby_2__2_:chany_top_in[5] 0.0003743001 +2 sb_2__2_:chany_bottom_out[5] sb_2__2_:chany_bottom_out[18] 8.91458e-05 +3 cby_2__2_:chany_top_in[5] cby_2__2_:chany_top_in[18] 8.91458e-05 +4 sb_2__2_:chany_bottom_out[5] sb_2__2_:chany_bottom_out[19] 0.0001427469 +5 cby_2__2_:chany_top_in[5] cby_2__2_:chany_top_in[19] 0.0001427469 + +*RES +0 sb_2__2_:chany_bottom_out[5] cby_2__2_:chany_top_in[5] 0.009839286 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[10] 0.001156275 //LENGTH 11.020 LUMPCC 0.0002879653 DR + +*CONN +*I sb_2__2_:chany_bottom_out[10] O *L 0 *C 874.460 788.870 +*I cby_2__2_:chany_top_in[10] I *L 0 *C 874.460 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[10] 0.0004341548 +1 cby_2__2_:chany_top_in[10] 0.0004341548 +2 sb_2__2_:chany_bottom_out[10] sb_2__2_:chany_bottom_in[6] 0.0001439826 +3 cby_2__2_:chany_top_in[10] cby_2__2_:chany_top_out[6] 0.0001439826 + +*RES +0 sb_2__2_:chany_bottom_out[10] cby_2__2_:chany_top_in[10] 0.009839285 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[15] 0.001183691 //LENGTH 11.020 LUMPCC 0.000376099 DR + +*CONN +*I sb_2__2_:chany_bottom_out[15] O *L 0 *C 836.280 788.870 +*I cby_2__2_:chany_top_in[15] I *L 0 *C 836.280 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[15] 0.0004037959 +1 cby_2__2_:chany_top_in[15] 0.0004037959 +2 sb_2__2_:chany_bottom_out[15] sb_2__2_:chany_bottom_in[18] 4.537184e-05 +3 cby_2__2_:chany_top_in[15] cby_2__2_:chany_top_out[18] 4.537184e-05 +4 sb_2__2_:chany_bottom_out[15] sb_2__2_:chany_bottom_out[9] 0.0001426777 +5 cby_2__2_:chany_top_in[15] cby_2__2_:chany_top_in[9] 0.0001426777 + +*RES +0 sb_2__2_:chany_bottom_out[15] cby_2__2_:chany_top_in[15] 0.009839286 + +*END + +*D_NET ropt_net_33 0.01105873 //LENGTH 110.430 LUMPCC 0 DR + +*CONN +*I ropt_h_inst_7751:X O *L 0 *C 285.895 523.600 +*I grid_clb_1__1_:ccff_head[0] I *L 0 *C 379.190 507.280 +*N ropt_net_33:2 *C 374.908 507.280 +*N ropt_net_33:3 *C 374.900 507.338 +*N ropt_net_33:4 *C 374.900 523.555 +*N ropt_net_33:5 *C 374.855 523.600 +*N ropt_net_33:6 *C 335.750 523.600 +*N ropt_net_33:7 *C 285.933 523.600 + +*CAP +0 ropt_h_inst_7751:X 1e-06 +1 grid_clb_1__1_:ccff_head[0] 0.000363454 +2 ropt_net_33:2 0.000363454 +3 ropt_net_33:3 0.0007183441 +4 ropt_net_33:4 0.0007183441 +5 ropt_net_33:5 0.001956338 +6 ropt_net_33:6 0.004447065 +7 ropt_net_33:7 0.002490728 + +*RES +0 ropt_h_inst_7751:X ropt_net_33:7 0.152 +1 ropt_net_33:7 ropt_net_33:6 0.04447991 +2 ropt_net_33:5 ropt_net_33:4 0.0045 +3 ropt_net_33:4 ropt_net_33:3 0.01447991 +4 ropt_net_33:3 ropt_net_33:2 0.00341 +5 ropt_net_33:2 grid_clb_1__1_:ccff_head[0] 0.000670925 +6 ropt_net_33:6 ropt_net_33:5 0.03491518 + +*END + +*D_NET ctsbuf_net_615 0.002146631 //LENGTH 19.925 LUMPCC 0 DR + +*CONN +*I cts_inv_73557630:Y O *L 0 *C 630.200 779.960 +*I grid_clb_2__2_:prog_clk[0] I *L 0 *C 640.470 788.800 +*N ctsbuf_net_615:2 *C 639.408 788.800 +*N ctsbuf_net_615:3 *C 639.400 788.743 +*N ctsbuf_net_615:4 *C 639.400 780.005 +*N ctsbuf_net_615:5 *C 639.355 779.960 +*N ctsbuf_net_615:6 *C 630.238 779.960 + +*CAP +0 cts_inv_73557630:Y 1e-06 +1 grid_clb_2__2_:prog_clk[0] 8.668037e-05 +2 ctsbuf_net_615:2 8.668037e-05 +3 ctsbuf_net_615:3 0.000433439 +4 ctsbuf_net_615:4 0.000433439 +5 ctsbuf_net_615:5 0.000552696 +6 ctsbuf_net_615:6 0.000552696 + +*RES +0 cts_inv_73557630:Y ctsbuf_net_615:6 0.152 +1 ctsbuf_net_615:3 ctsbuf_net_615:2 0.00341 +2 ctsbuf_net_615:2 grid_clb_2__2_:prog_clk[0] 0.0001664583 +3 ctsbuf_net_615:5 ctsbuf_net_615:4 0.0045 +4 ctsbuf_net_615:4 ctsbuf_net_615:3 0.007801339 +5 ctsbuf_net_615:6 ctsbuf_net_615:5 0.008140625 + +*END + +*D_NET ctsbuf_net_1524 0.02821158 //LENGTH 275.435 LUMPCC 0.005238291 DR + +*CONN +*I cts_inv_73647639:Y O *L 0 *C 276.920 638.520 +*I sb_0__1_:prog_clk[0] I *L 0 *C 287.190 586.840 +*I grid_io_left_0__2_:prog_clk[0] I *L 0 *C 271.860 777.850 +*I sb_0__2_:prog_clk[0] I *L 0 *C 323.380 788.870 +*I cby_0__2_:prog_clk[0] I *L 0 *C 287.190 672.520 +*N ctsbuf_net_1524:5 *C 323.380 780.697 +*N ctsbuf_net_1524:6 *C 323.373 780.640 +*N ctsbuf_net_1524:7 *C 271.860 780.582 +*N ctsbuf_net_1524:8 *C 271.868 780.640 +*N ctsbuf_net_1524:9 *C 283.820 780.640 +*N ctsbuf_net_1524:10 *C 283.820 780.582 +*N ctsbuf_net_1524:11 *C 283.820 772.335 +*N ctsbuf_net_1524:12 *C 283.820 722.335 +*N ctsbuf_net_1524:13 *C 283.820 672.577 +*N ctsbuf_net_1524:14 *C 283.820 672.520 +*N ctsbuf_net_1524:15 *C 281.067 672.520 +*N ctsbuf_net_1524:16 *C 281.060 672.462 +*N ctsbuf_net_1524:17 *C 281.060 667.520 +*N ctsbuf_net_1524:18 *C 281.060 667.519 +*N ctsbuf_net_1524:19 *C 281.067 586.840 +*N ctsbuf_net_1524:20 *C 281.060 586.898 +*N ctsbuf_net_1524:21 *C 281.060 638.180 +*N ctsbuf_net_1524:22 *C 281.015 638.180 +*N ctsbuf_net_1524:23 *C 277.380 638.180 +*N ctsbuf_net_1524:24 *C 277.380 638.520 +*N ctsbuf_net_1524:25 *C 276.958 638.520 + +*CAP +0 cts_inv_73647639:Y 1e-06 +1 sb_0__1_:prog_clk[0] 0.0003332577 +2 grid_io_left_0__2_:prog_clk[0] 0.0001937361 +3 sb_0__2_:prog_clk[0] 0.0003478176 +4 cby_0__2_:prog_clk[0] 0.0002456375 +5 ctsbuf_net_1524:5 0.0003478176 +6 ctsbuf_net_1524:6 0.001368596 +7 ctsbuf_net_1524:7 0.0001937361 +8 ctsbuf_net_1524:8 0.0005404177 +9 ctsbuf_net_1524:9 0.001909014 +10 ctsbuf_net_1524:10 0.0003641721 +11 ctsbuf_net_1524:11 0.002426614 +12 ctsbuf_net_1524:12 0.004115385 +13 ctsbuf_net_1524:13 0.002052943 +14 ctsbuf_net_1524:14 0.0003979027 +15 ctsbuf_net_1524:15 0.0001522652 +16 ctsbuf_net_1524:16 0.0001797538 +17 ctsbuf_net_1524:17 0.0001797538 +18 ctsbuf_net_1524:18 0.001061704 +19 ctsbuf_net_1524:19 0.0003332577 +20 ctsbuf_net_1524:20 0.002292952 +21 ctsbuf_net_1524:21 0.003386313 +22 ctsbuf_net_1524:22 0.0002054163 +23 ctsbuf_net_1524:23 0.0002327883 +24 ctsbuf_net_1524:24 6.920913e-05 +25 ctsbuf_net_1524:25 4.183707e-05 +26 sb_0__2_:prog_clk[0] sb_0__2_:chany_bottom_out[1] 5.657789e-05 +27 ctsbuf_net_1524:5 cby_0__2_:chany_top_in[1] 5.657789e-05 +28 ctsbuf_net_1524:10 ctsbuf_net_514:22 5.640123e-05 +29 ctsbuf_net_1524:13 ctsbuf_net_514:24 0.0002296201 +30 ctsbuf_net_1524:13 ctsbuf_net_514:25 0.0001400768 +31 ctsbuf_net_1524:16 ctsbuf_net_514:24 7.622104e-05 +32 ctsbuf_net_1524:21 ctsbuf_net_514:27 0.0003792233 +33 ctsbuf_net_1524:12 ctsbuf_net_514:23 0.0004526802 +34 ctsbuf_net_1524:12 ctsbuf_net_514:24 0.0002802022 +35 ctsbuf_net_1524:11 ctsbuf_net_514:22 0.0002230601 +36 ctsbuf_net_1524:11 ctsbuf_net_514:23 0.0001965266 +37 ctsbuf_net_1524:17 ctsbuf_net_514:25 7.622104e-05 +38 ctsbuf_net_1524:18 ctsbuf_net_514:26 0.0003792233 +39 ctsbuf_net_1524:9 ctsbuf_net_2130:75 0.0004934358 +40 ctsbuf_net_1524:9 ctsbuf_net_2130:74 2.035789e-05 +41 ctsbuf_net_1524:8 ctsbuf_net_2130:75 2.035789e-05 +42 ctsbuf_net_1524:20 ctsbuf_net_2130:93 4.002279e-05 +43 ctsbuf_net_1524:21 ctsbuf_net_2130:92 8.602231e-05 +44 ctsbuf_net_1524:6 ctsbuf_net_2130:74 0.0004934358 +45 ctsbuf_net_1524:18 ctsbuf_net_2130:84 4.599952e-05 +46 ctsbuf_net_1524:9 ropt_net_40:7 0.000647973 +47 ctsbuf_net_1524:9 ropt_net_40:6 7.00504e-05 +48 ctsbuf_net_1524:8 ropt_net_40:7 7.00504e-05 +49 ctsbuf_net_1524:6 ropt_net_40:6 0.000647973 + +*RES +0 cts_inv_73647639:Y ctsbuf_net_1524:25 0.152 +1 ctsbuf_net_1524:10 ctsbuf_net_1524:9 0.00341 +2 ctsbuf_net_1524:9 ctsbuf_net_1524:8 0.001872558 +3 ctsbuf_net_1524:9 ctsbuf_net_1524:6 0.006196558 +4 ctsbuf_net_1524:13 ctsbuf_net_1524:12 0.04442634 +5 ctsbuf_net_1524:14 ctsbuf_net_1524:13 0.00341 +6 ctsbuf_net_1524:14 cby_0__2_:prog_clk[0] 0.0005279667 +7 ctsbuf_net_1524:7 grid_io_left_0__2_:prog_clk[0] 0.002439732 +8 ctsbuf_net_1524:8 ctsbuf_net_1524:7 0.00341 +9 ctsbuf_net_1524:16 ctsbuf_net_1524:15 0.00341 +10 ctsbuf_net_1524:15 ctsbuf_net_1524:14 0.000431225 +11 ctsbuf_net_1524:20 ctsbuf_net_1524:19 0.00341 +12 ctsbuf_net_1524:19 sb_0__1_:prog_clk[0] 0.0009591916 +13 ctsbuf_net_1524:22 ctsbuf_net_1524:21 0.0045 +14 ctsbuf_net_1524:21 ctsbuf_net_1524:20 0.04578795 +15 ctsbuf_net_1524:21 ctsbuf_net_1524:18 0.02619554 +16 ctsbuf_net_1524:25 ctsbuf_net_1524:24 0.0003772322 +17 ctsbuf_net_1524:5 sb_0__2_:prog_clk[0] 0.007296875 +18 ctsbuf_net_1524:6 ctsbuf_net_1524:5 0.00341 +19 ctsbuf_net_1524:24 ctsbuf_net_1524:23 0.0003035715 +20 ctsbuf_net_1524:23 ctsbuf_net_1524:22 0.003245536 +21 ctsbuf_net_1524:12 ctsbuf_net_1524:11 0.04464286 +22 ctsbuf_net_1524:11 ctsbuf_net_1524:10 0.00736384 +23 ctsbuf_net_1524:17 ctsbuf_net_1524:16 0.004412947 +24 ctsbuf_net_1524:18 ctsbuf_net_1524:17 1e-05 + +*END + +*D_NET ropt_net_38 0.002695665 //LENGTH 26.620 LUMPCC 0.0005094234 DR + +*CONN +*I ropt_h_inst_7756:X O *L 0 *C 403.195 912.560 +*I sb_0__2_:ccff_head[0] I *L 0 *C 397.900 892.090 +*N ropt_net_38:2 *C 397.900 909.455 +*N ropt_net_38:3 *C 397.945 909.500 +*N ropt_net_38:4 *C 402.915 909.500 +*N ropt_net_38:5 *C 402.960 909.545 +*N ropt_net_38:6 *C 402.960 912.515 +*N ropt_net_38:7 *C 402.960 912.560 +*N ropt_net_38:8 *C 403.195 912.560 + +*CAP +0 ropt_h_inst_7756:X 1e-06 +1 sb_0__2_:ccff_head[0] 0.0006147337 +2 ropt_net_38:2 0.0006147337 +3 ropt_net_38:3 0.0002721967 +4 ropt_net_38:4 0.0002721967 +5 ropt_net_38:5 0.000162801 +6 ropt_net_38:6 0.000162801 +7 ropt_net_38:7 4.485254e-05 +8 ropt_net_38:8 4.09263e-05 +9 sb_0__2_:ccff_head[0] sb_0__2_:right_top_grid_pin_1_[0] 0.0002464143 +10 ropt_net_38:3 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:3 8.297387e-06 +11 ropt_net_38:2 grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]:2 0.0002464143 +12 ropt_net_38:4 grid_io_top_1__3_:bottom_width_0_height_0__pin_1_upper[0] 8.297387e-06 + +*RES +0 ropt_h_inst_7756:X ropt_net_38:8 0.152 +1 ropt_net_38:3 ropt_net_38:2 0.0045 +2 ropt_net_38:2 sb_0__2_:ccff_head[0] 0.01550446 +3 ropt_net_38:4 ropt_net_38:3 0.0044375 +4 ropt_net_38:5 ropt_net_38:4 0.0045 +5 ropt_net_38:7 ropt_net_38:6 0.0045 +6 ropt_net_38:6 ropt_net_38:5 0.002651786 +7 ropt_net_38:8 ropt_net_38:7 0.0001277174 + +*END + +*D_NET gfpga_pad_GPIO_A[6] 0.02251342 //LENGTH 267.615 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__1_:gfpga_pad_GPIO_A[0] O *L 0 *C 255.910 463.760 +*P gfpga_pad_GPIO_A[6] O *L 0 *C 0.525 475.320 +*N gfpga_pad_GPIO_A[6]:2 *C 0.875 475.320 +*N gfpga_pad_GPIO_A[6]:3 *C 0.920 475.275 +*N gfpga_pad_GPIO_A[6]:4 *C 0.920 463.817 +*N gfpga_pad_GPIO_A[6]:5 *C 0.927 463.760 +*N gfpga_pad_GPIO_A[6]:6 *C 50.755 463.760 +*N gfpga_pad_GPIO_A[6]:7 *C 100.755 463.760 +*N gfpga_pad_GPIO_A[6]:8 *C 150.755 463.760 +*N gfpga_pad_GPIO_A[6]:9 *C 200.755 463.760 +*N gfpga_pad_GPIO_A[6]:10 *C 219.519 463.760 +*N gfpga_pad_GPIO_A[6]:11 *C 219.520 463.760 +*N gfpga_pad_GPIO_A[6]:12 *C 250.755 463.760 + +*CAP +0 grid_io_left_0__1_:gfpga_pad_GPIO_A[0] 0.0002992033 +1 gfpga_pad_GPIO_A[6] 3.716182e-05 +2 gfpga_pad_GPIO_A[6]:2 3.716182e-05 +3 gfpga_pad_GPIO_A[6]:3 0.0004941908 +4 gfpga_pad_GPIO_A[6]:4 0.0004941908 +5 gfpga_pad_GPIO_A[6]:5 0.002096811 +6 gfpga_pad_GPIO_A[6]:6 0.004181994 +7 gfpga_pad_GPIO_A[6]:7 0.00416772 +8 gfpga_pad_GPIO_A[6]:8 0.004169057 +9 gfpga_pad_GPIO_A[6]:9 0.002861017 +10 gfpga_pad_GPIO_A[6]:10 0.0007744973 +11 gfpga_pad_GPIO_A[6]:11 0.001300607 +12 gfpga_pad_GPIO_A[6]:12 0.00159981 + +*RES +0 grid_io_left_0__1_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[6]:12 0.0008076166 +1 gfpga_pad_GPIO_A[6]:4 gfpga_pad_GPIO_A[6]:3 0.01022991 +2 gfpga_pad_GPIO_A[6]:5 gfpga_pad_GPIO_A[6]:4 0.00341 +3 gfpga_pad_GPIO_A[6]:2 gfpga_pad_GPIO_A[6] 0.0003125 +4 gfpga_pad_GPIO_A[6]:3 gfpga_pad_GPIO_A[6]:2 0.0045 +5 gfpga_pad_GPIO_A[6]:6 gfpga_pad_GPIO_A[6]:5 0.007806308 +6 gfpga_pad_GPIO_A[6]:7 gfpga_pad_GPIO_A[6]:6 0.007833333 +7 gfpga_pad_GPIO_A[6]:8 gfpga_pad_GPIO_A[6]:7 0.007833333 +8 gfpga_pad_GPIO_A[6]:9 gfpga_pad_GPIO_A[6]:8 0.007833333 +9 gfpga_pad_GPIO_A[6]:12 gfpga_pad_GPIO_A[6]:11 0.004893483 +10 gfpga_pad_GPIO_A[6]:11 gfpga_pad_GPIO_A[6]:10 1e-05 +11 gfpga_pad_GPIO_A[6]:10 gfpga_pad_GPIO_A[6]:9 0.002939693 + +*END + +*D_NET sb_2__1__0_chanx_left_out[8] 0.001609351 //LENGTH 7.660 LUMPCC 0.0003801351 DR + +*CONN +*I sb_2__1_:chanx_left_out[8] O *L 0 *C 781.230 576.640 +*I cbx_2__1_:chanx_right_in[8] I *L 0 *C 773.570 576.640 + +*CAP +0 sb_2__1_:chanx_left_out[8] 0.0006146079 +1 cbx_2__1_:chanx_right_in[8] 0.0006146079 +2 sb_2__1_:chanx_left_out[8] sb_2__1_:chanx_left_out[5] 9.569569e-05 +3 cbx_2__1_:chanx_right_in[8] cbx_2__1_:chanx_right_in[5] 9.569569e-05 +4 sb_2__1_:chanx_left_out[8] sb_2__1_:chanx_left_out[6] 9.437184e-05 +5 cbx_2__1_:chanx_right_in[8] cbx_2__1_:chanx_right_in[6] 9.437184e-05 + +*RES +0 sb_2__1_:chanx_left_out[8] cbx_2__1_:chanx_right_in[8] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_bottom_out[9] 0.001279521 //LENGTH 11.020 LUMPCC 0.0005318955 DR + +*CONN +*I sb_2__1_:chany_bottom_out[9] O *L 0 *C 835.360 527.750 +*I cby_2__1_:chany_top_in[9] I *L 0 *C 835.360 516.730 + +*CAP +0 sb_2__1_:chany_bottom_out[9] 0.0003738126 +1 cby_2__1_:chany_top_in[9] 0.0003738126 +2 sb_2__1_:chany_bottom_out[9] sb_2__1_:chany_bottom_in[15] 0.0001329739 +3 cby_2__1_:chany_top_in[9] cby_2__1_:chany_top_out[15] 0.0001329739 +4 sb_2__1_:chany_bottom_out[9] sb_2__1_:chany_bottom_out[15] 0.0001329739 +5 cby_2__1_:chany_top_in[9] cby_2__1_:chany_top_in[15] 0.0001329739 + +*RES +0 sb_2__1_:chany_bottom_out[9] cby_2__1_:chany_top_in[9] 0.009839286 + +*END + +*D_NET sb_2__1__0_chany_top_out[15] 0.001255655 //LENGTH 11.020 LUMPCC 0.0005537507 DR + +*CONN +*I sb_2__1_:chany_top_out[15] O *L 0 *C 832.140 658.170 +*I cby_2__2_:chany_bottom_in[15] I *L 0 *C 832.140 669.190 +*N sb_2__1__0_chany_top_out[15]:2 *C 832.140 667.520 +*N sb_2__1__0_chany_top_out[15]:3 *C 832.140 667.519 + +*CAP +0 sb_2__1_:chany_top_out[15] 0.0002400145 +1 cby_2__2_:chany_bottom_in[15] 0.0001109378 +2 sb_2__1__0_chany_top_out[15]:2 0.0001109378 +3 sb_2__1__0_chany_top_out[15]:3 0.0002400145 +4 sb_2__1_:chany_top_out[15] sb_2__1_:chany_top_in[4] 0.0001310978 +5 cby_2__2_:chany_bottom_in[15] cby_2__2_:chany_bottom_out[4] 7.339873e-06 +6 sb_2__1__0_chany_top_out[15]:2 cby_1__1__3_chany_bottom_out[4]:3 7.339873e-06 +7 sb_2__1__0_chany_top_out[15]:3 cby_1__1__3_chany_bottom_out[4]:2 0.0001310978 +8 sb_2__1_:chany_top_out[15] sb_2__1_:chany_top_out[7] 0.0001310978 +9 cby_2__2_:chany_bottom_in[15] cby_2__2_:chany_bottom_in[7] 7.339873e-06 +10 sb_2__1__0_chany_top_out[15]:2 sb_2__1__0_chany_top_out[7]:2 7.339873e-06 +11 sb_2__1__0_chany_top_out[15]:3 sb_2__1__0_chany_top_out[7]:3 0.0001310978 + +*RES +0 sb_2__1_:chany_top_out[15] sb_2__1__0_chany_top_out[15]:3 0.008347322 +1 sb_2__1__0_chany_top_out[15]:2 cby_2__2_:chany_bottom_in[15] 0.001491072 +2 sb_2__1__0_chany_top_out[15]:3 sb_2__1__0_chany_top_out[15]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[10] 0.001456486 //LENGTH 7.660 LUMPCC 0.0005239752 DR + +*CONN +*I sb_2__2_:chanx_left_out[10] O *L 0 *C 781.230 886.720 +*I cbx_2__2_:chanx_right_in[10] I *L 0 *C 773.570 886.720 + +*CAP +0 sb_2__2_:chanx_left_out[10] 0.0004662556 +1 cbx_2__2_:chanx_right_in[10] 0.0004662556 +2 sb_2__2_:chanx_left_out[10] sb_2__2_:chanx_left_in[9] 0.0001212868 +3 cbx_2__2_:chanx_right_in[10] cbx_2__2_:chanx_right_out[9] 0.0001212868 +4 sb_2__2_:chanx_left_out[10] sb_2__2_:chanx_left_in[15] 0.0001407008 +5 cbx_2__2_:chanx_right_in[10] cbx_2__2_:chanx_right_out[15] 0.0001407008 + +*RES +0 sb_2__2_:chanx_left_out[10] cbx_2__2_:chanx_right_in[10] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[12] 0.001264694 //LENGTH 11.020 LUMPCC 0.0005558836 DR + +*CONN +*I sb_2__2_:chany_bottom_out[12] O *L 0 *C 861.580 788.870 +*I cby_2__2_:chany_top_in[12] I *L 0 *C 861.580 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[12] 0.0003544054 +1 cby_2__2_:chany_top_in[12] 0.0003544054 +2 sb_2__2_:chany_bottom_out[12] sb_2__2_:chany_bottom_in[2] 0.0001395529 +3 cby_2__2_:chany_top_in[12] cby_2__2_:chany_top_out[2] 0.0001395529 +4 sb_2__2_:chany_bottom_out[12] sb_2__2_:chany_bottom_in[12] 0.0001383889 +5 cby_2__2_:chany_top_in[12] cby_2__2_:chany_top_out[12] 0.0001383889 + +*RES +0 sb_2__2_:chany_bottom_out[12] cby_2__2_:chany_top_in[12] 0.009839286 + +*END + +*D_NET ctsbuf_net_211 0.03851399 //LENGTH 345.580 LUMPCC 0.004256336 DR + +*CONN +*I cts_inv_73517626:Y O *L 0 *C 516.580 551.140 +*I sb_1__0_:prog_clk[0] I *L 0 *C 550.620 397.085 +*I grid_io_bottom_1__0_:prog_clk[0] I *L 0 *C 512.290 278.120 +*N ctsbuf_net_211:3 *C 513.353 278.120 +*N ctsbuf_net_211:4 *C 513.360 278.178 +*N ctsbuf_net_211:5 *C 513.360 327.935 +*N ctsbuf_net_211:6 *C 513.360 378.703 +*N ctsbuf_net_211:7 *C 513.368 378.760 +*N ctsbuf_net_211:8 *C 547.393 378.760 +*N ctsbuf_net_211:9 *C 547.400 378.817 +*N ctsbuf_net_211:10 *C 550.620 397.755 +*N ctsbuf_net_211:11 *C 550.575 397.800 +*N ctsbuf_net_211:12 *C 547.445 397.800 +*N ctsbuf_net_211:13 *C 547.400 397.800 +*N ctsbuf_net_211:14 *C 547.400 443.519 +*N ctsbuf_net_211:15 *C 547.400 443.520 +*N ctsbuf_net_211:16 *C 547.400 447.800 +*N ctsbuf_net_211:17 *C 547.400 497.800 +*N ctsbuf_net_211:18 *C 547.400 550.062 +*N ctsbuf_net_211:19 *C 547.393 550.120 +*N ctsbuf_net_211:20 *C 517.967 550.120 +*N ctsbuf_net_211:21 *C 517.960 550.178 +*N ctsbuf_net_211:22 *C 517.960 551.095 +*N ctsbuf_net_211:23 *C 517.915 551.140 +*N ctsbuf_net_211:24 *C 516.618 551.140 + +*CAP +0 cts_inv_73517626:Y 1e-06 +1 sb_1__0_:prog_clk[0] 5.984053e-05 +2 grid_io_bottom_1__0_:prog_clk[0] 0.0001303446 +3 ctsbuf_net_211:3 0.0001303446 +4 ctsbuf_net_211:4 0.002508022 +5 ctsbuf_net_211:5 0.005055821 +6 ctsbuf_net_211:6 0.002547799 +7 ctsbuf_net_211:7 0.00186354 +8 ctsbuf_net_211:8 0.00186354 +9 ctsbuf_net_211:9 0.001010914 +10 ctsbuf_net_211:10 5.984053e-05 +11 ctsbuf_net_211:11 0.0002223518 +12 ctsbuf_net_211:12 0.0002223518 +13 ctsbuf_net_211:13 0.003427104 +14 ctsbuf_net_211:14 0.002382023 +15 ctsbuf_net_211:15 0.0002236441 +16 ctsbuf_net_211:16 0.002895877 +17 ctsbuf_net_211:17 0.00537669 +18 ctsbuf_net_211:18 0.002704457 +19 ctsbuf_net_211:19 0.0006314816 +20 ctsbuf_net_211:20 0.0006314816 +21 ctsbuf_net_211:21 6.498081e-05 +22 ctsbuf_net_211:22 6.498081e-05 +23 ctsbuf_net_211:23 8.960983e-05 +24 ctsbuf_net_211:24 8.960983e-05 +25 ctsbuf_net_211:6 cbx_1__0__0_chanx_right_out[4]:4 0.0001750741 +26 ctsbuf_net_211:5 cbx_1__0__0_chanx_right_out[4]:3 0.0001750741 +27 ctsbuf_net_211:4 cbx_1__0__0_chanx_right_out[14]:4 9.947135e-05 +28 ctsbuf_net_211:5 cbx_1__0__0_chanx_right_out[14]:5 9.947135e-05 +29 ctsbuf_net_211:18 direct_interc_5_out[0]:28 5.386257e-05 +30 ctsbuf_net_211:13 direct_interc_5_out[0]:32 3.813218e-05 +31 ctsbuf_net_211:13 direct_interc_5_out[0]:33 6.457772e-05 +32 ctsbuf_net_211:9 direct_interc_5_out[0]:33 2.425511e-06 +33 ctsbuf_net_211:16 direct_interc_5_out[0]:29 6.157121e-05 +34 ctsbuf_net_211:16 direct_interc_5_out[0]:30 8.054676e-05 +35 ctsbuf_net_211:17 direct_interc_5_out[0]:28 4.772252e-05 +36 ctsbuf_net_211:17 direct_interc_5_out[0]:29 0.0001344093 +37 ctsbuf_net_211:15 direct_interc_5_out[0]:30 1.38487e-05 +38 ctsbuf_net_211:14 direct_interc_5_out[0]:31 3.570667e-05 +39 ctsbuf_net_211:14 direct_interc_5_out[0]:32 6.457772e-05 +40 ctsbuf_net_211:13 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:2 6.258812e-05 +41 ctsbuf_net_211:9 grid_clb_0_bottom_width_0_height_0__pin_43_lower[0]:3 6.258812e-05 +42 ctsbuf_net_211:6 grid_clb_1__1_:bottom_width_0_height_0__pin_50_[0] 3.698759e-06 +43 ctsbuf_net_211:6 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:3 4.166857e-05 +44 ctsbuf_net_211:5 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:4 4.166857e-05 +45 ctsbuf_net_211:5 grid_clb_0_bottom_width_0_height_0__pin_50_[0]:7 3.698759e-06 +46 ctsbuf_net_211:18 ctsbuf_net_1928:27 0.0001189888 +47 ctsbuf_net_211:19 ctsbuf_net_1928:28 0.0001825343 +48 ctsbuf_net_211:19 ctsbuf_net_1928:29 0.000334968 +49 ctsbuf_net_211:20 ctsbuf_net_1928:30 0.000334968 +50 ctsbuf_net_211:20 ctsbuf_net_1928:29 0.0001825343 +51 ctsbuf_net_211:17 ctsbuf_net_1928:26 0.0001189888 +52 ctsbuf_net_211:19 ctsbuf_net_2029:36 0.0007901932 +53 ctsbuf_net_211:21 ctsbuf_net_2029:38 9.588973e-06 +54 ctsbuf_net_211:20 ctsbuf_net_2029:37 0.0007901932 +55 ctsbuf_net_211:23 ctsbuf_net_2029:20 1.070351e-05 +56 ctsbuf_net_211:22 ctsbuf_net_2029:21 9.588973e-06 +57 ctsbuf_net_211:24 ctsbuf_net_2029:19 1.070351e-05 + +*RES +0 cts_inv_73517626:Y ctsbuf_net_211:24 0.152 +1 ctsbuf_net_211:18 ctsbuf_net_211:17 0.04666295 +2 ctsbuf_net_211:19 ctsbuf_net_211:18 0.00341 +3 ctsbuf_net_211:21 ctsbuf_net_211:20 0.00341 +4 ctsbuf_net_211:20 ctsbuf_net_211:19 0.004609916 +5 ctsbuf_net_211:23 ctsbuf_net_211:22 0.0045 +6 ctsbuf_net_211:22 ctsbuf_net_211:21 0.0008191965 +7 ctsbuf_net_211:24 ctsbuf_net_211:23 0.001158482 +8 ctsbuf_net_211:12 ctsbuf_net_211:11 0.002794643 +9 ctsbuf_net_211:13 ctsbuf_net_211:12 0.0045 +10 ctsbuf_net_211:13 ctsbuf_net_211:9 0.01694866 +11 ctsbuf_net_211:11 ctsbuf_net_211:10 0.0045 +12 ctsbuf_net_211:10 sb_1__0_:prog_clk[0] 0.0005982143 +13 ctsbuf_net_211:9 ctsbuf_net_211:8 0.00341 +14 ctsbuf_net_211:8 ctsbuf_net_211:7 0.005330583 +15 ctsbuf_net_211:6 ctsbuf_net_211:5 0.04532813 +16 ctsbuf_net_211:7 ctsbuf_net_211:6 0.00341 +17 ctsbuf_net_211:4 ctsbuf_net_211:3 0.00341 +18 ctsbuf_net_211:3 grid_io_bottom_1__0_:prog_clk[0] 0.0001664583 +19 ctsbuf_net_211:5 ctsbuf_net_211:4 0.04442634 +20 ctsbuf_net_211:16 ctsbuf_net_211:15 0.003821429 +21 ctsbuf_net_211:17 ctsbuf_net_211:16 0.04464286 +22 ctsbuf_net_211:15 ctsbuf_net_211:14 1e-05 +23 ctsbuf_net_211:14 ctsbuf_net_211:13 0.04082054 + +*END + +*D_NET gfpga_pad_GPIO_A[7] 0.0244999 //LENGTH 256.030 LUMPCC 0 DR + +*CONN +*I grid_io_left_0__2_:gfpga_pad_GPIO_A[0] O *L 0 *C 255.910 724.880 +*P gfpga_pad_GPIO_A[7] O *L 0 *C 0.525 725.220 +*N gfpga_pad_GPIO_A[7]:2 *C 50.525 725.220 +*N gfpga_pad_GPIO_A[7]:3 *C 100.525 725.220 +*N gfpga_pad_GPIO_A[7]:4 *C 150.525 725.220 +*N gfpga_pad_GPIO_A[7]:5 *C 200.525 725.220 +*N gfpga_pad_GPIO_A[7]:6 *C 219.519 725.220 +*N gfpga_pad_GPIO_A[7]:7 *C 219.520 725.220 +*N gfpga_pad_GPIO_A[7]:8 *C 250.195 725.220 +*N gfpga_pad_GPIO_A[7]:9 *C 250.240 725.220 +*N gfpga_pad_GPIO_A[7]:10 *C 250.240 724.880 +*N gfpga_pad_GPIO_A[7]:11 *C 250.248 724.880 + +*CAP +0 grid_io_left_0__2_:gfpga_pad_GPIO_A[0] 0.0003112123 +1 gfpga_pad_GPIO_A[7] 0.00239368 +2 gfpga_pad_GPIO_A[7]:2 0.004774388 +3 gfpga_pad_GPIO_A[7]:3 0.004761177 +4 gfpga_pad_GPIO_A[7]:4 0.004761151 +5 gfpga_pad_GPIO_A[7]:5 0.003279099 +6 gfpga_pad_GPIO_A[7]:6 0.0008984168 +7 gfpga_pad_GPIO_A[7]:7 0.001464749 +8 gfpga_pad_GPIO_A[7]:8 0.001464749 +9 gfpga_pad_GPIO_A[7]:9 3.863624e-05 +10 gfpga_pad_GPIO_A[7]:10 4.143173e-05 +11 gfpga_pad_GPIO_A[7]:11 0.0003112123 + +*RES +0 grid_io_left_0__2_:gfpga_pad_GPIO_A[0] gfpga_pad_GPIO_A[7]:11 0.000887125 +1 gfpga_pad_GPIO_A[7]:10 gfpga_pad_GPIO_A[7]:9 0.0001634615 +2 gfpga_pad_GPIO_A[7]:11 gfpga_pad_GPIO_A[7]:10 0.00341 +3 gfpga_pad_GPIO_A[7]:8 gfpga_pad_GPIO_A[7]:7 0.0273884 +4 gfpga_pad_GPIO_A[7]:9 gfpga_pad_GPIO_A[7]:8 0.0045 +5 gfpga_pad_GPIO_A[7]:2 gfpga_pad_GPIO_A[7] 0.04464286 +6 gfpga_pad_GPIO_A[7]:3 gfpga_pad_GPIO_A[7]:2 0.04464286 +7 gfpga_pad_GPIO_A[7]:4 gfpga_pad_GPIO_A[7]:3 0.04464286 +8 gfpga_pad_GPIO_A[7]:5 gfpga_pad_GPIO_A[7]:4 0.04464286 +9 gfpga_pad_GPIO_A[7]:7 gfpga_pad_GPIO_A[7]:6 1e-05 +10 gfpga_pad_GPIO_A[7]:6 gfpga_pad_GPIO_A[7]:5 0.01695893 + +*END + +*D_NET sb_2__1__0_chanx_left_out[16] 0.001450586 //LENGTH 7.660 LUMPCC 0.000107648 DR + +*CONN +*I sb_2__1_:chanx_left_out[16] O *L 0 *C 781.230 559.640 +*I cbx_2__1_:chanx_right_in[16] I *L 0 *C 773.570 559.640 + +*CAP +0 sb_2__1_:chanx_left_out[16] 0.000671469 +1 cbx_2__1_:chanx_right_in[16] 0.000671469 +2 sb_2__1_:chanx_left_out[16] sb_2__1_:chanx_left_in[6] 5.382402e-05 +3 cbx_2__1_:chanx_right_in[16] cbx_2__1_:chanx_right_out[6] 5.382402e-05 + +*RES +0 sb_2__1_:chanx_left_out[16] cbx_2__1_:chanx_right_in[16] 0.001200067 + +*END + +*D_NET sb_2__1__0_chany_top_out[6] 0.001258102 //LENGTH 11.020 LUMPCC 0.0005497003 DR + +*CONN +*I sb_2__1_:chany_top_out[6] O *L 0 *C 851.460 658.170 +*I cby_2__2_:chany_bottom_in[6] I *L 0 *C 851.460 669.190 +*N sb_2__1__0_chany_top_out[6]:2 *C 851.460 667.520 +*N sb_2__1__0_chany_top_out[6]:3 *C 851.460 667.519 + +*CAP +0 sb_2__1_:chany_top_out[6] 0.0002432113 +1 cby_2__2_:chany_bottom_in[6] 0.0001109896 +2 sb_2__1__0_chany_top_out[6]:2 0.0001109896 +3 sb_2__1__0_chany_top_out[6]:3 0.0002432113 +4 sb_2__1_:chany_top_out[6] sb_2__1_:chany_top_in[16] 0.0001283662 +5 cby_2__2_:chany_bottom_in[6] cby_2__2_:chany_bottom_out[16] 7.294814e-06 +6 sb_2__1__0_chany_top_out[6]:2 cby_1__1__3_chany_bottom_out[16]:3 7.294814e-06 +7 sb_2__1__0_chany_top_out[6]:3 cby_1__1__3_chany_bottom_out[16]:2 0.0001283662 +8 sb_2__1_:chany_top_out[6] sb_2__1_:chany_top_out[3] 0.0001318429 +9 cby_2__2_:chany_bottom_in[6] cby_2__2_:chany_bottom_in[3] 7.346249e-06 +10 sb_2__1__0_chany_top_out[6]:2 sb_2__1__0_chany_top_out[3]:2 7.346249e-06 +11 sb_2__1__0_chany_top_out[6]:3 sb_2__1__0_chany_top_out[3]:3 0.0001318429 + +*RES +0 sb_2__1_:chany_top_out[6] sb_2__1__0_chany_top_out[6]:3 0.008347321 +1 sb_2__1__0_chany_top_out[6]:2 cby_2__2_:chany_bottom_in[6] 0.001491072 +2 sb_2__1__0_chany_top_out[6]:3 sb_2__1__0_chany_top_out[6]:2 1e-05 + +*END + +*D_NET sb_2__2__0_chanx_left_out[6] 0.001525548 //LENGTH 7.660 LUMPCC 0.0004661438 DR + +*CONN +*I sb_2__2_:chanx_left_out[6] O *L 0 *C 781.230 832.320 +*I cbx_2__2_:chanx_right_in[6] I *L 0 *C 773.570 832.320 + +*CAP +0 sb_2__2_:chanx_left_out[6] 0.0005297022 +1 cbx_2__2_:chanx_right_in[6] 0.0005297022 +2 sb_2__2_:chanx_left_out[6] sb_2__2_:chanx_left_in[1] 0.0001172335 +3 cbx_2__2_:chanx_right_in[6] cbx_2__2_:chanx_right_out[1] 0.0001172335 +4 sb_2__2_:chanx_left_out[6] sb_2__2_:chanx_left_out[15] 0.0001158384 +5 cbx_2__2_:chanx_right_in[6] cbx_2__2_:chanx_right_in[15] 0.0001158384 + +*RES +0 sb_2__2_:chanx_left_out[6] cbx_2__2_:chanx_right_in[6] 0.001200067 + +*END + +*D_NET sb_2__2__0_chanx_left_out[18] 0.0013579 //LENGTH 7.660 LUMPCC 0.0004456036 DR + +*CONN +*I sb_2__2_:chanx_left_out[18] O *L 0 *C 781.230 855.440 +*I cbx_2__2_:chanx_right_in[18] I *L 0 *C 773.570 855.440 + +*CAP +0 sb_2__2_:chanx_left_out[18] 0.0004561479 +1 cbx_2__2_:chanx_right_in[18] 0.0004561479 +2 sb_2__2_:chanx_left_out[18] sb_2__2_:chanx_left_in[2] 5.272921e-05 +3 cbx_2__2_:chanx_right_in[18] cbx_1__2__1_chanx_right_out[2]:2 5.272921e-05 +4 sb_2__2_:chanx_left_out[18] sb_2__2_:chanx_left_out[9] 0.0001277273 +5 cbx_2__2_:chanx_right_in[18] cbx_2__2_:chanx_right_in[9] 0.0001277273 +6 sb_2__2_:chanx_left_out[18] sb_2__2_:chanx_left_out[14] 4.234528e-05 +7 cbx_2__2_:chanx_right_in[18] cbx_2__2_:chanx_right_in[14] 4.234528e-05 + +*RES +0 sb_2__2_:chanx_left_out[18] cbx_2__2_:chanx_right_in[18] 0.001200067 + +*END + +*D_NET sb_2__2__0_chany_bottom_out[9] 0.001254542 //LENGTH 11.020 LUMPCC 0.0005707106 DR + +*CONN +*I sb_2__2_:chany_bottom_out[9] O *L 0 *C 835.360 788.870 +*I cby_2__2_:chany_top_in[9] I *L 0 *C 835.360 777.850 + +*CAP +0 sb_2__2_:chany_bottom_out[9] 0.0003419156 +1 cby_2__2_:chany_top_in[9] 0.0003419156 +2 sb_2__2_:chany_bottom_out[9] sb_2__2_:chany_bottom_in[15] 0.0001426777 +3 cby_2__2_:chany_top_in[9] cby_2__2_:chany_top_out[15] 0.0001426777 +4 sb_2__2_:chany_bottom_out[9] sb_2__2_:chany_bottom_out[15] 0.0001426777 +5 cby_2__2_:chany_top_in[9] cby_2__2_:chany_top_in[15] 0.0001426777 + +*RES +0 sb_2__2_:chany_bottom_out[9] cby_2__2_:chany_top_in[9] 0.009839286 + +*END + +*D_NET ropt_net_31 0.0001594391 //LENGTH 0.980 LUMPCC 7.392762e-05 DR + +*CONN +*I ropt_h_inst_7749:X O *L 0 *C 284.050 520.880 +*I ropt_h_inst_7750:A I *L 0.001746 *C 284.740 520.880 +*N ropt_net_31:2 *C 284.702 520.880 +*N ropt_net_31:3 *C 284.088 520.880 + +*CAP +0 ropt_h_inst_7749:X 1e-06 +1 ropt_h_inst_7750:A 1e-06 +2 ropt_net_31:2 4.175572e-05 +3 ropt_net_31:3 4.175572e-05 +4 ropt_net_31:3 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:4 3.696381e-05 +5 ropt_net_31:2 grid_io_left_0_right_width_0_height_0__pin_1_upper[0]:3 3.696381e-05 + +*RES +0 ropt_h_inst_7749:X ropt_net_31:3 0.152 +1 ropt_net_31:3 ropt_net_31:2 0.0005491072 +2 ropt_net_31:2 ropt_h_inst_7750:A 0.152 + +*END + +*D_NET ctsbuf_net_716 0.004850315 //LENGTH 41.515 LUMPCC 0.0002593334 DR + +*CONN +*I cts_inv_73567631:Y O *L 0 *C 541.880 779.960 +*I cby_1__2_:prog_clk[0] I *L 0 *C 548.470 758.880 +*I sb_1__2_:prog_clk[0] I *L 0 *C 550.620 788.870 +*N ctsbuf_net_716:3 *C 550.620 783.360 +*N ctsbuf_net_716:4 *C 550.160 783.360 +*N ctsbuf_net_716:5 *C 550.160 780.005 +*N ctsbuf_net_716:6 *C 550.115 779.960 +*N ctsbuf_net_716:7 *C 546.947 758.880 +*N ctsbuf_net_716:8 *C 546.940 758.938 +*N ctsbuf_net_716:9 *C 546.940 779.915 +*N ctsbuf_net_716:10 *C 546.940 779.960 +*N ctsbuf_net_716:11 *C 541.918 779.960 + +*CAP +0 cts_inv_73567631:Y 1e-06 +1 cby_1__2_:prog_clk[0] 0.0002298686 +2 sb_1__2_:prog_clk[0] 0.0002711619 +3 ctsbuf_net_716:3 0.0002939117 +4 ctsbuf_net_716:4 0.0002075728 +5 ctsbuf_net_716:5 0.000184823 +6 ctsbuf_net_716:6 0.000197097 +7 ctsbuf_net_716:7 0.0002298686 +8 ctsbuf_net_716:8 0.001059943 +9 ctsbuf_net_716:9 0.001059943 +10 ctsbuf_net_716:10 0.0005428011 +11 ctsbuf_net_716:11 0.0003129898 +12 ctsbuf_net_716:9 direct_interc_5_out[0]:14 0.0001206958 +13 ctsbuf_net_716:8 direct_interc_5_out[0]:15 0.0001206958 +14 ctsbuf_net_716:4 direct_interc_5_out[0]:13 8.970885e-06 +15 ctsbuf_net_716:3 direct_interc_5_out[0]:12 8.970885e-06 + +*RES +0 cts_inv_73567631:Y ctsbuf_net_716:11 0.152 +1 ctsbuf_net_716:11 ctsbuf_net_716:10 0.004484375 +2 ctsbuf_net_716:10 ctsbuf_net_716:9 0.0045 +3 ctsbuf_net_716:10 ctsbuf_net_716:6 0.002834822 +4 ctsbuf_net_716:9 ctsbuf_net_716:8 0.01872991 +5 ctsbuf_net_716:8 ctsbuf_net_716:7 0.00341 +6 ctsbuf_net_716:7 cby_1__2_:prog_clk[0] 0.000238525 +7 ctsbuf_net_716:6 ctsbuf_net_716:5 0.0045 +8 ctsbuf_net_716:5 ctsbuf_net_716:4 0.002995536 +9 ctsbuf_net_716:4 ctsbuf_net_716:3 0.0004107143 +10 ctsbuf_net_716:3 sb_1__2_:prog_clk[0] 0.004919643 + +*END + +*D_NET ctsbuf_net_2029 0.07714115 //LENGTH 625.560 LUMPCC 0.01448213 DR + +*CONN +*I cts_inv_73837658:Y O *L 0 *C 253.000 588.200 +*I cts_inv_73537628:A I *L 0.005046 *C 629.740 523.600 +*I cts_inv_73577632:A I *L 0.005046 *C 629.520 518.015 +*I cts_inv_73517626:A I *L 0.005046 *C 516.120 550.875 +*I cts_inv_73597634:A I *L 0.005046 *C 516.120 545.435 +*I cts_inv_73657640:A I *L 0.005046 *C 276.255 490.695 +*N ctsbuf_net_2029:6 *C 276.255 490.695 +*N ctsbuf_net_2029:7 *C 276.870 490.620 +*N ctsbuf_net_2029:8 *C 276.920 490.875 +*N ctsbuf_net_2029:9 *C 276.920 490.875 +*N ctsbuf_net_2029:10 *C 276.920 496.210 +*N ctsbuf_net_2029:11 *C 276.920 546.105 +*N ctsbuf_net_2029:12 *C 276.920 584.778 +*N ctsbuf_net_2029:13 *C 276.920 584.800 +*N ctsbuf_net_2029:14 *C 516.120 545.435 +*N ctsbuf_net_2029:15 *C 517.040 545.395 +*N ctsbuf_net_2029:16 *C 517.040 545.395 +*N ctsbuf_net_2029:17 *C 516.120 550.875 +*N ctsbuf_net_2029:18 *C 514.280 550.800 +*N ctsbuf_net_2029:19 *C 514.280 550.460 +*N ctsbuf_net_2029:20 *C 517.040 550.520 +*N ctsbuf_net_2029:21 *C 517.040 550.520 +*N ctsbuf_net_2029:22 *C 629.520 518.015 +*N ctsbuf_net_2029:23 *C 629.740 518.105 +*N ctsbuf_net_2029:24 *C 629.740 518.105 +*N ctsbuf_net_2029:25 *C 630.660 518.160 +*N ctsbuf_net_2029:26 *C 630.660 522.863 +*N ctsbuf_net_2029:27 *C 630.660 522.920 +*N ctsbuf_net_2029:28 *C 629.740 523.510 +*N ctsbuf_net_2029:29 *C 629.740 523.510 +*N ctsbuf_net_2029:30 *C 629.740 522.978 +*N ctsbuf_net_2029:31 *C 629.740 522.920 +*N ctsbuf_net_2029:32 *C 592.040 522.920 +*N ctsbuf_net_2029:33 *C 542.340 522.920 +*N ctsbuf_net_2029:34 *C 542.340 522.942 +*N ctsbuf_net_2029:35 *C 542.340 548.738 +*N ctsbuf_net_2029:36 *C 542.340 548.760 +*N ctsbuf_net_2029:37 *C 517.040 548.760 +*N ctsbuf_net_2029:38 *C 517.040 548.817 +*N ctsbuf_net_2029:39 *C 517.040 546.685 +*N ctsbuf_net_2029:40 *C 517.040 546.720 +*N ctsbuf_net_2029:41 *C 475.980 546.720 +*N ctsbuf_net_2029:42 *C 443.520 546.720 +*N ctsbuf_net_2029:43 *C 443.519 546.720 +*N ctsbuf_net_2029:44 *C 425.980 546.720 +*N ctsbuf_net_2029:45 *C 376.280 546.720 +*N ctsbuf_net_2029:46 *C 376.280 546.697 +*N ctsbuf_net_2029:47 *C 376.280 526.342 +*N ctsbuf_net_2029:48 *C 376.280 526.320 +*N ctsbuf_net_2029:49 *C 357.760 526.320 +*N ctsbuf_net_2029:50 *C 307.760 526.320 +*N ctsbuf_net_2029:51 *C 258.060 526.320 +*N ctsbuf_net_2029:52 *C 258.060 526.342 +*N ctsbuf_net_2029:53 *C 258.060 576.135 +*N ctsbuf_net_2029:54 *C 258.060 584.778 +*N ctsbuf_net_2029:55 *C 258.060 584.800 +*N ctsbuf_net_2029:56 *C 254.985 584.800 +*N ctsbuf_net_2029:57 *C 253.008 584.800 +*N ctsbuf_net_2029:58 *C 253.000 584.858 +*N ctsbuf_net_2029:59 *C 253.000 588.110 +*N ctsbuf_net_2029:60 *C 253.000 588.110 + +*CAP +0 cts_inv_73837658:Y 1e-06 +1 cts_inv_73537628:A 1e-06 +2 cts_inv_73577632:A 1e-06 +3 cts_inv_73517626:A 1e-06 +4 cts_inv_73597634:A 1e-06 +5 cts_inv_73657640:A 1e-06 +6 ctsbuf_net_2029:6 8.917482e-05 +7 ctsbuf_net_2029:7 8.173825e-05 +8 ctsbuf_net_2029:8 8.819687e-05 +9 ctsbuf_net_2029:9 0.0003165122 +10 ctsbuf_net_2029:10 0.002772065 +11 ctsbuf_net_2029:11 0.004053356 +12 ctsbuf_net_2029:12 0.001558348 +13 ctsbuf_net_2029:13 0.0008922212 +14 ctsbuf_net_2029:14 0.0001104721 +15 ctsbuf_net_2029:15 0.0001215006 +16 ctsbuf_net_2029:16 0.0001404335 +17 ctsbuf_net_2029:17 0.0001797312 +18 ctsbuf_net_2029:18 0.0001498457 +19 ctsbuf_net_2029:19 9.847792e-05 +20 ctsbuf_net_2029:20 0.0001269938 +21 ctsbuf_net_2029:21 0.0001442917 +22 ctsbuf_net_2029:22 5.698096e-05 +23 ctsbuf_net_2029:23 6.384138e-05 +24 ctsbuf_net_2029:24 0.0001008539 +25 ctsbuf_net_2029:25 0.000303626 +26 ctsbuf_net_2029:26 0.0002458948 +27 ctsbuf_net_2029:27 4.645355e-05 +28 ctsbuf_net_2029:28 4.14378e-05 +29 ctsbuf_net_2029:29 7.519266e-05 +30 ctsbuf_net_2029:30 4.085997e-05 +31 ctsbuf_net_2029:31 0.001805839 +32 ctsbuf_net_2029:32 0.003972794 +33 ctsbuf_net_2029:33 0.002213408 +34 ctsbuf_net_2029:34 0.001093645 +35 ctsbuf_net_2029:35 0.001093645 +36 ctsbuf_net_2029:36 0.0009383974 +37 ctsbuf_net_2029:37 0.0009383974 +38 ctsbuf_net_2029:38 0.0002615175 +39 ctsbuf_net_2029:39 0.0002530888 +40 ctsbuf_net_2029:40 0.00217675 +41 ctsbuf_net_2029:41 0.003779473 +42 ctsbuf_net_2029:42 0.001602723 +43 ctsbuf_net_2029:43 0.0008377983 +44 ctsbuf_net_2029:44 0.003123303 +45 ctsbuf_net_2029:45 0.002285505 +46 ctsbuf_net_2029:46 0.000911176 +47 ctsbuf_net_2029:47 0.000911176 +48 ctsbuf_net_2029:48 0.0011464 +49 ctsbuf_net_2029:49 0.004720633 +50 ctsbuf_net_2029:50 0.006223707 +51 ctsbuf_net_2029:51 0.002649474 +52 ctsbuf_net_2029:52 0.002521292 +53 ctsbuf_net_2029:53 0.002985922 +54 ctsbuf_net_2029:54 0.0004646295 +55 ctsbuf_net_2029:55 0.001049157 +56 ctsbuf_net_2029:56 0.0002589475 +57 ctsbuf_net_2029:57 0.0001020123 +58 ctsbuf_net_2029:58 0.0001709324 +59 ctsbuf_net_2029:59 0.0002073495 +60 ctsbuf_net_2029:60 5.542786e-05 +61 ctsbuf_net_2029:33 grid_clb_1__1_:clk[0] 0.0002093283 +62 ctsbuf_net_2029:33 clk[0]:37 5.198141e-06 +63 ctsbuf_net_2029:31 clk[0]:37 6.657097e-06 +64 ctsbuf_net_2029:31 clk[0]:38 0.0001767444 +65 ctsbuf_net_2029:27 clk[0]:38 6.657097e-06 +66 ctsbuf_net_2029:24 clk[0]:37 6.274608e-06 +67 ctsbuf_net_2029:25 clk[0]:38 6.274608e-06 +68 ctsbuf_net_2029:32 clk[0]:37 0.0003860728 +69 ctsbuf_net_2029:32 clk[0]:38 5.198141e-06 +70 ctsbuf_net_2029:34 direct_interc_5_out[0]:28 0.0002022201 +71 ctsbuf_net_2029:34 direct_interc_5_out[0]:29 6.732917e-05 +72 ctsbuf_net_2029:35 direct_interc_5_out[0]:27 0.0002022201 +73 ctsbuf_net_2029:35 direct_interc_5_out[0]:28 6.732917e-05 +74 ctsbuf_net_2029:33 grid_clb_1__1_:Test_en[0] 0.0001371272 +75 ctsbuf_net_2029:33 BUF_net_9:5 7.458331e-06 +76 ctsbuf_net_2029:32 BUF_net_9:2 0.0001371272 +77 ctsbuf_net_2029:32 BUF_net_9:6 7.458331e-06 +78 ctsbuf_net_2029:20 ctsbuf_net_211:23 1.070351e-05 +79 ctsbuf_net_2029:21 ctsbuf_net_211:22 9.588973e-06 +80 ctsbuf_net_2029:36 ctsbuf_net_211:19 0.0007901932 +81 ctsbuf_net_2029:38 ctsbuf_net_211:21 9.588973e-06 +82 ctsbuf_net_2029:37 ctsbuf_net_211:20 0.0007901932 +83 ctsbuf_net_2029:19 ctsbuf_net_211:24 1.070351e-05 +84 ctsbuf_net_2029:34 ctsbuf_net_1019:13 0.0002633473 +85 ctsbuf_net_2029:35 ctsbuf_net_1019:14 0.0002633473 +86 ctsbuf_net_2029:36 ctsbuf_net_1019:15 8.857888e-05 +87 ctsbuf_net_2029:37 ctsbuf_net_1019:16 8.857888e-05 +88 ctsbuf_net_2029:15 ctsbuf_net_1019:19 2.756124e-05 +89 ctsbuf_net_2029:14 ctsbuf_net_1019:20 2.756124e-05 +90 ctsbuf_net_2029:47 ctsbuf_net_1827:3 0.0001374719 +91 ctsbuf_net_2029:46 ctsbuf_net_1827:4 0.0001374719 +92 ctsbuf_net_2029:33 ctsbuf_net_1928:25 0.0005312886 +93 ctsbuf_net_2029:36 ctsbuf_net_1928:29 1.469313e-05 +94 ctsbuf_net_2029:37 ctsbuf_net_1928:30 1.469313e-05 +95 ctsbuf_net_2029:31 ctsbuf_net_1928:23 0.0003871987 +96 ctsbuf_net_2029:31 ctsbuf_net_1928:24 4.387428e-05 +97 ctsbuf_net_2029:51 ctsbuf_net_1928:48 0.0005794652 +98 ctsbuf_net_2029:47 ctsbuf_net_1928:44 9.022113e-06 +99 ctsbuf_net_2029:47 ctsbuf_net_1928:45 8.952415e-05 +100 ctsbuf_net_2029:48 ctsbuf_net_1928:46 0.0002884779 +101 ctsbuf_net_2029:46 ctsbuf_net_1928:39 9.022113e-06 +102 ctsbuf_net_2029:46 ctsbuf_net_1928:44 8.952415e-05 +103 ctsbuf_net_2029:45 ctsbuf_net_1928:37 2.883806e-05 +104 ctsbuf_net_2029:45 ctsbuf_net_1928:38 0.000594722 +105 ctsbuf_net_2029:40 ctsbuf_net_1928:29 0.0001554905 +106 ctsbuf_net_2029:40 ctsbuf_net_1928:30 5.921104e-05 +107 ctsbuf_net_2029:12 ctsbuf_net_1928:50 0.0005409202 +108 ctsbuf_net_2029:12 ctsbuf_net_1928:51 0.0002041128 +109 ctsbuf_net_2029:27 ctsbuf_net_1928:23 1.543263e-05 +110 ctsbuf_net_2029:10 ctsbuf_net_1928:49 0.0004193719 +111 ctsbuf_net_2029:11 ctsbuf_net_1928:49 0.0005409202 +112 ctsbuf_net_2029:11 ctsbuf_net_1928:50 0.0006234847 +113 ctsbuf_net_2029:50 ctsbuf_net_1928:47 0.001038468 +114 ctsbuf_net_2029:50 ctsbuf_net_1928:48 0.0003110614 +115 ctsbuf_net_2029:49 ctsbuf_net_1928:46 0.0004590023 +116 ctsbuf_net_2029:49 ctsbuf_net_1928:47 0.0005995394 +117 ctsbuf_net_2029:44 ctsbuf_net_1928:33 3.242728e-05 +118 ctsbuf_net_2029:44 ctsbuf_net_1928:36 2.883806e-05 +119 ctsbuf_net_2029:44 ctsbuf_net_1928:37 0.0007287906 +120 ctsbuf_net_2029:41 ctsbuf_net_1928:30 0.0003680002 +121 ctsbuf_net_2029:41 ctsbuf_net_1928:31 5.921104e-05 +122 ctsbuf_net_2029:32 ctsbuf_net_1928:24 0.0009184873 +123 ctsbuf_net_2029:32 ctsbuf_net_1928:25 2.844165e-05 +124 ctsbuf_net_2029:42 ctsbuf_net_1928:31 0.0002125097 +125 ctsbuf_net_2029:43 ctsbuf_net_1928:32 3.242728e-05 +126 ctsbuf_net_2029:43 ctsbuf_net_1928:36 0.0001340686 + +*RES +0 cts_inv_73837658:Y ctsbuf_net_2029:60 0.152 +1 ctsbuf_net_2029:20 ctsbuf_net_2029:19 0.002464286 +2 ctsbuf_net_2029:21 ctsbuf_net_2029:20 0.0045 +3 ctsbuf_net_2029:17 cts_inv_73517626:A 0.152 +4 ctsbuf_net_2029:60 ctsbuf_net_2029:59 0.0045 +5 ctsbuf_net_2029:59 ctsbuf_net_2029:58 0.002904018 +6 ctsbuf_net_2029:58 ctsbuf_net_2029:57 0.00341 +7 ctsbuf_net_2029:57 ctsbuf_net_2029:56 0.0003098083 +8 ctsbuf_net_2029:34 ctsbuf_net_2029:33 0.00341 +9 ctsbuf_net_2029:33 ctsbuf_net_2029:32 0.003893166 +10 ctsbuf_net_2029:35 ctsbuf_net_2029:34 0.01151563 +11 ctsbuf_net_2029:36 ctsbuf_net_2029:35 0.00341 +12 ctsbuf_net_2029:38 ctsbuf_net_2029:37 0.00341 +13 ctsbuf_net_2029:38 ctsbuf_net_2029:21 0.001520089 +14 ctsbuf_net_2029:37 ctsbuf_net_2029:36 0.001981833 +15 ctsbuf_net_2029:28 cts_inv_73537628:A 0.152 +16 ctsbuf_net_2029:29 ctsbuf_net_2029:28 0.0045 +17 ctsbuf_net_2029:30 ctsbuf_net_2029:29 0.0004754465 +18 ctsbuf_net_2029:31 ctsbuf_net_2029:30 0.00341 +19 ctsbuf_net_2029:31 ctsbuf_net_2029:27 7.206666e-05 +20 ctsbuf_net_2029:54 ctsbuf_net_2029:53 0.003858259 +21 ctsbuf_net_2029:55 ctsbuf_net_2029:54 0.00341 +22 ctsbuf_net_2029:55 ctsbuf_net_2029:13 0.001477367 +23 ctsbuf_net_2029:52 ctsbuf_net_2029:51 0.00341 +24 ctsbuf_net_2029:51 ctsbuf_net_2029:50 0.003893166 +25 ctsbuf_net_2029:47 ctsbuf_net_2029:46 0.009087054 +26 ctsbuf_net_2029:48 ctsbuf_net_2029:47 0.00341 +27 ctsbuf_net_2029:46 ctsbuf_net_2029:45 0.00341 +28 ctsbuf_net_2029:45 ctsbuf_net_2029:44 0.003893166 +29 ctsbuf_net_2029:39 ctsbuf_net_2029:38 0.0009520089 +30 ctsbuf_net_2029:39 ctsbuf_net_2029:16 0.001151786 +31 ctsbuf_net_2029:40 ctsbuf_net_2029:39 0.00341 +32 ctsbuf_net_2029:6 cts_inv_73657640:A 0.152 +33 ctsbuf_net_2029:15 ctsbuf_net_2029:14 0.0008214285 +34 ctsbuf_net_2029:16 ctsbuf_net_2029:15 0.0045 +35 ctsbuf_net_2029:14 cts_inv_73597634:A 0.152 +36 ctsbuf_net_2029:8 ctsbuf_net_2029:7 0.00010625 +37 ctsbuf_net_2029:9 ctsbuf_net_2029:8 0.0045 +38 ctsbuf_net_2029:12 ctsbuf_net_2029:11 0.01726451 +39 ctsbuf_net_2029:13 ctsbuf_net_2029:12 0.00341 +40 ctsbuf_net_2029:26 ctsbuf_net_2029:25 0.004198661 +41 ctsbuf_net_2029:27 ctsbuf_net_2029:26 0.00341 +42 ctsbuf_net_2029:23 ctsbuf_net_2029:22 0.0001195652 +43 ctsbuf_net_2029:24 ctsbuf_net_2029:23 0.0045 +44 ctsbuf_net_2029:22 cts_inv_73577632:A 0.152 +45 ctsbuf_net_2029:7 ctsbuf_net_2029:6 0.0005491071 +46 ctsbuf_net_2029:19 ctsbuf_net_2029:18 0.0003035715 +47 ctsbuf_net_2029:18 ctsbuf_net_2029:17 0.001642857 +48 ctsbuf_net_2029:10 ctsbuf_net_2029:9 0.004763393 +49 ctsbuf_net_2029:25 ctsbuf_net_2029:24 0.0008214285 +50 ctsbuf_net_2029:56 ctsbuf_net_2029:55 0.000240875 +51 ctsbuf_net_2029:53 ctsbuf_net_2029:52 0.0222288 +52 ctsbuf_net_2029:11 ctsbuf_net_2029:10 0.02227456 +53 ctsbuf_net_2029:50 ctsbuf_net_2029:49 0.003916666 +54 ctsbuf_net_2029:49 ctsbuf_net_2029:48 0.001450733 +55 ctsbuf_net_2029:44 ctsbuf_net_2029:43 0.001373888 +56 ctsbuf_net_2029:41 ctsbuf_net_2029:40 0.003216367 +57 ctsbuf_net_2029:32 ctsbuf_net_2029:31 0.002953166 +58 ctsbuf_net_2029:42 ctsbuf_net_2029:41 0.0025427 +59 ctsbuf_net_2029:43 ctsbuf_net_2029:42 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_IE[0] 0.02301862 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*I grid_io_top_1__3_:gfpga_pad_GPIO_IE[0] O *L 0 *C 465.520 924.730 +*P gfpga_pad_GPIO_IE[0] O *L 0 *C 465.520 1196.385 +*N gfpga_pad_GPIO_IE[0]:2 *C 465.520 1174.730 +*N gfpga_pad_GPIO_IE[0]:3 *C 465.520 1124.730 +*N gfpga_pad_GPIO_IE[0]:4 *C 465.520 1115.520 +*N gfpga_pad_GPIO_IE[0]:5 *C 465.520 1115.519 +*N gfpga_pad_GPIO_IE[0]:6 *C 465.520 1074.730 +*N gfpga_pad_GPIO_IE[0]:7 *C 465.520 1024.730 +*N gfpga_pad_GPIO_IE[0]:8 *C 465.520 974.730 + +*CAP +0 grid_io_top_1__3_:gfpga_pad_GPIO_IE[0] 0.002175201 +1 gfpga_pad_GPIO_IE[0] 0.0009033415 +2 gfpga_pad_GPIO_IE[0]:2 0.003013856 +3 gfpga_pad_GPIO_IE[0]:3 0.002485787 +4 gfpga_pad_GPIO_IE[0]:4 0.0003752726 +5 gfpga_pad_GPIO_IE[0]:5 0.001730721 +6 gfpga_pad_GPIO_IE[0]:6 0.003834091 +7 gfpga_pad_GPIO_IE[0]:7 0.004214257 +8 gfpga_pad_GPIO_IE[0]:8 0.004286089 + +*RES +0 grid_io_top_1__3_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[0]:8 0.04464286 +1 gfpga_pad_GPIO_IE[0]:8 gfpga_pad_GPIO_IE[0]:7 0.04464286 +2 gfpga_pad_GPIO_IE[0]:7 gfpga_pad_GPIO_IE[0]:6 0.04464286 +3 gfpga_pad_GPIO_IE[0]:6 gfpga_pad_GPIO_IE[0]:5 0.03641875 +4 gfpga_pad_GPIO_IE[0]:3 gfpga_pad_GPIO_IE[0]:2 0.04464286 +5 gfpga_pad_GPIO_IE[0]:2 gfpga_pad_GPIO_IE[0] 0.01933482 +6 gfpga_pad_GPIO_IE[0]:4 gfpga_pad_GPIO_IE[0]:3 0.008223215 +7 gfpga_pad_GPIO_IE[0]:5 gfpga_pad_GPIO_IE[0]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_IE[1] 0.02414696 //LENGTH 271.655 LUMPCC 0 DR + +*CONN +*I grid_io_top_2__3_:gfpga_pad_GPIO_IE[0] O *L 0 *C 726.800 924.730 +*P gfpga_pad_GPIO_IE[1] O *L 0 *C 726.800 1196.385 +*N gfpga_pad_GPIO_IE[1]:2 *C 726.800 1174.730 +*N gfpga_pad_GPIO_IE[1]:3 *C 726.800 1124.730 +*N gfpga_pad_GPIO_IE[1]:4 *C 726.800 1115.520 +*N gfpga_pad_GPIO_IE[1]:5 *C 726.800 1115.519 +*N gfpga_pad_GPIO_IE[1]:6 *C 726.800 1074.730 +*N gfpga_pad_GPIO_IE[1]:7 *C 726.800 1024.730 +*N gfpga_pad_GPIO_IE[1]:8 *C 726.800 974.730 + +*CAP +0 grid_io_top_2__3_:gfpga_pad_GPIO_IE[0] 0.00227295 +1 gfpga_pad_GPIO_IE[1] 0.0009500976 +2 gfpga_pad_GPIO_IE[1]:2 0.003160979 +3 gfpga_pad_GPIO_IE[1]:3 0.002616063 +4 gfpga_pad_GPIO_IE[1]:4 0.0004051816 +5 gfpga_pad_GPIO_IE[1]:5 0.001813738 +6 gfpga_pad_GPIO_IE[1]:6 0.004023382 +7 gfpga_pad_GPIO_IE[1]:7 0.004420632 +8 gfpga_pad_GPIO_IE[1]:8 0.004483938 + +*RES +0 grid_io_top_2__3_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[1]:8 0.04464286 +1 gfpga_pad_GPIO_IE[1]:8 gfpga_pad_GPIO_IE[1]:7 0.04464286 +2 gfpga_pad_GPIO_IE[1]:7 gfpga_pad_GPIO_IE[1]:6 0.04464286 +3 gfpga_pad_GPIO_IE[1]:6 gfpga_pad_GPIO_IE[1]:5 0.03641875 +4 gfpga_pad_GPIO_IE[1]:3 gfpga_pad_GPIO_IE[1]:2 0.04464286 +5 gfpga_pad_GPIO_IE[1]:2 gfpga_pad_GPIO_IE[1] 0.01933482 +6 gfpga_pad_GPIO_IE[1]:4 gfpga_pad_GPIO_IE[1]:3 0.008223215 +7 gfpga_pad_GPIO_IE[1]:5 gfpga_pad_GPIO_IE[1]:4 1e-05 + +*END + +*D_NET gfpga_pad_GPIO_IE[2] 0.03035562 //LENGTH 274.110 LUMPCC 0 DR + +*CONN +*I grid_io_right_3__1_:gfpga_pad_GPIO_IE[0] O *L 0 *C 925.370 460.360 +*P gfpga_pad_GPIO_IE[2] O *L 0 *C 1199.155 460.360 +*N gfpga_pad_GPIO_IE[2]:2 *C 1179.960 460.360 +*N gfpga_pad_GPIO_IE[2]:3 *C 1129.960 460.360 +*N gfpga_pad_GPIO_IE[2]:4 *C 1115.520 460.360 +*N gfpga_pad_GPIO_IE[2]:5 *C 1115.519 460.360 +*N gfpga_pad_GPIO_IE[2]:6 *C 1079.960 460.360 +*N gfpga_pad_GPIO_IE[2]:7 *C 1029.960 460.360 +*N gfpga_pad_GPIO_IE[2]:8 *C 979.960 460.360 +*N gfpga_pad_GPIO_IE[2]:9 *C 930.165 460.360 +*N gfpga_pad_GPIO_IE[2]:10 *C 930.120 460.360 +*N gfpga_pad_GPIO_IE[2]:11 *C 930.113 460.360 + +*CAP +0 grid_io_right_3__1_:gfpga_pad_GPIO_IE[0] 0.0003695578 +1 gfpga_pad_GPIO_IE[2] 0.00106019 +2 gfpga_pad_GPIO_IE[2]:2 0.003807093 +3 gfpga_pad_GPIO_IE[2]:3 0.003537592 +4 gfpga_pad_GPIO_IE[2]:4 0.0007906892 +5 gfpga_pad_GPIO_IE[2]:5 0.001951946 +6 gfpga_pad_GPIO_IE[2]:6 0.004699299 +7 gfpga_pad_GPIO_IE[2]:7 0.005495186 +8 gfpga_pad_GPIO_IE[2]:8 0.005495911 +9 gfpga_pad_GPIO_IE[2]:9 0.002748078 +10 gfpga_pad_GPIO_IE[2]:10 3.052078e-05 +11 gfpga_pad_GPIO_IE[2]:11 0.0003695578 + +*RES +0 grid_io_right_3__1_:gfpga_pad_GPIO_IE[0] gfpga_pad_GPIO_IE[2]:11 0.0007429916 +1 gfpga_pad_GPIO_IE[2]:10 gfpga_pad_GPIO_IE[2]:9 0.0045 +2 gfpga_pad_GPIO_IE[2]:11 gfpga_pad_GPIO_IE[2]:10 0.00341 +3 gfpga_pad_GPIO_IE[2]:9 gfpga_pad_GPIO_IE[2]:8 0.04445982 +4 gfpga_pad_GPIO_IE[2]:8 gfpga_pad_GPIO_IE[2]:7 0.04464286 +5 gfpga_pad_GPIO_IE[2]:7 gfpga_pad_GPIO_IE[2]:6 0.04464286 +6 gfpga_pad_GPIO_IE[2]:6 gfpga_pad_GPIO_IE[2]:5 0.03174911 +7 gfpga_pad_GPIO_IE[2]:3 gfpga_pad_GPIO_IE[2]:2 0.04464286 +8 gfpga_pad_GPIO_IE[2]:2 gfpga_pad_GPIO_IE[2] 0.01713839 +9 gfpga_pad_GPIO_IE[2]:4 gfpga_pad_GPIO_IE[2]:3 0.01289286 +10 gfpga_pad_GPIO_IE[2]:5 gfpga_pad_GPIO_IE[2]:4 1e-05 + +*END + +*D_NET cbx_1__0__0_bottom_grid_pin_0_[0] 0.001105953 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I cbx_1__0_:bottom_grid_pin_0_[0] O *L 0 *C 505.080 293.830 +*I grid_io_bottom_1__0_:top_width_0_height_0__pin_0_[0] I *L 0 *C 505.080 282.810 + +*CAP +0 cbx_1__0_:bottom_grid_pin_0_[0] 0.0005529766 +1 grid_io_bottom_1__0_:top_width_0_height_0__pin_0_[0] 0.0005529766 + +*RES +0 cbx_1__0_:bottom_grid_pin_0_[0] grid_io_bottom_1__0_:top_width_0_height_0__pin_0_[0] 0.009839286 + +*END + +*D_NET cbx_1__0__0_chanx_right_out[19] 0.001265374 //LENGTH 7.660 LUMPCC 0.00029887 DR + +*CONN +*I cbx_1__0_:chanx_right_out[19] O *L 0 *C 512.290 297.840 +*I sb_1__0_:chanx_left_in[19] I *L 0 *C 519.950 297.840 + +*CAP +0 cbx_1__0_:chanx_right_out[19] 0.0004832519 +1 sb_1__0_:chanx_left_in[19] 0.0004832519 +2 cbx_1__0_:chanx_right_out[19] cbx_1__0_:chanx_right_out[18] 0.000149435 +3 sb_1__0_:chanx_left_in[19] sb_1__0_:chanx_left_in[18] 0.000149435 + +*RES +0 cbx_1__0_:chanx_right_out[19] sb_1__0_:chanx_left_in[19] 0.001200067 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v new file mode 100644 index 0000000..d5400b4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v @@ -0,0 +1,30239 @@ +// +// +// +// +// +// +module direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; + +mux_tree_tapbuf_size10_0_5 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1_3 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2_3 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6_3 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7_2 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_16 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4_3 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0_5 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_3 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_3 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_16 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5_2 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_9 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0_4 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1_4 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2_3 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3_2 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_9 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; + +mux_tree_tapbuf_size10_0_4 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10_15 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0_4 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_15 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; + +mux_tree_tapbuf_size10_14 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem_14 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; + +mux_tree_tapbuf_size10_0_3 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1_2 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4_2 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5_2 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6_2 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_13 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3_2 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0_3 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_2 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_2 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_2 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_2 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_13 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_2 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_4_1 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5_1 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6_1 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0_3 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1_3 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3_1 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4_1 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5_1 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6_1 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_8 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_3 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_3 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3_1 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; + +mux_tree_tapbuf_size10_0_2 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4_1 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5_1 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6_1 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7_1 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2_1 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3_1 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_12 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0_2 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4_1 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5_1 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6_1 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7_1 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2_1 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3_1 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_12 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_7 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0_2 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1_2 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2_1 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_7 mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_2 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1_2 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2_1 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +mux_tree_tapbuf_size6_0_6 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_10 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0_6 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_10 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_8 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_8 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_11 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem_11 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_2 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8_2 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9_2 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10_2 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11_1 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12_1 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13_1 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14_1 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16_1 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_22 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15_1 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_2 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8_2 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11_1 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12_1 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13_1 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_22 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; + +mux_tree_tapbuf_size10_11 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem_11 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0_1 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size14_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_5_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_8 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4_1 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_8 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size6_9 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0_5 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1_3 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem_9 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size9_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_8 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0_3 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1_2 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem_8 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_2 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1_4 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2_4 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_10 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_4 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_10 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; + +mux_tree_tapbuf_size6_2_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6_8 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0_4 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1_2 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_8 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_2_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0_3 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1_2 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_9 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2_3 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1_3 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0_4 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem_9 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_3 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_3 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_8_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_21 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0_4 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1_4 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2_4 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3_4 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5_3 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6_2 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7_1 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9_1 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_21 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_4 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_4 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; + +mux_tree_tapbuf_size6_2_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_7 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0_3 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_7 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_6 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0_2 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3_1 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2_1 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_6 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_8 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5_1 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem_8 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5_1 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_7 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_2_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0_2 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4_7 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_2 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_7 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_3 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1_3 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2_3 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4_2 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5_2 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_14 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_3 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4_2 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_2 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; +mux_tree_tapbuf_size7_6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem_6 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size4_6 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0_1 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_7 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_7 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_0_2 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1_2 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3_2 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0_2 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_2 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_2 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0_2 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; + +mux_tree_tapbuf_size2_4_1 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6_1 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_12 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5_1 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0_1 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2_1 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3_1 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3_1 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_1 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0_1 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; +mux_tree_tapbuf_size5_1 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0_1 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0_1 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_4 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) ) ; +endmodule + + +module direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_aps_2 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_11 ( .A ( net_aps_2 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_3 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_5 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_3 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_3 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_4 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_left ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , right_width_0_height_0__pin_0_ , + ccff_head , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__3 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_14 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( right_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_15 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( right_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_8 ( .A ( aps_rename_2_ ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_14 ) , + .X ( gfpga_pad_GPIO_IE[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_2 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_2 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_2 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_3 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_bottom ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , top_width_0_height_0__pin_0_ , + ccff_head , top_width_0_height_0__pin_1_upper , + top_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__2 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( { ropt_net_16 } ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( top_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_17 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( top_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_6 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_6 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( BUF_net_6 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_581 ( .A ( ropt_net_19 ) , + .X ( gfpga_pad_GPIO_IE[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_579 ( .A ( ropt_net_16 ) , + .X ( ropt_net_19 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_580 ( .A ( ropt_net_17 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO_1 ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_8 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_8 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_11 ( .A ( BUF_net_8 ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO_1 GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem_1 GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_2 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_right ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , left_width_0_height_0__pin_0_ , + ccff_head , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] left_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io__1 logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( ccff_head ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_13 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( left_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_15 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_9 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_12 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_576 ( .A ( ropt_net_12 ) , + .X ( ropt_net_15 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( ropt_net_13 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module direct_interc_1 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__2 ( .A ( mem_out[0] ) , + .X ( net_net_7 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_7 ( .A ( net_net_7 ) , + .X ( net_net_6 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_10 ( .A ( net_net_6 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module GPIO ( A , IE , OE , Y , in , out , mem_out ) ; +output A ; +output IE ; +output OE ; +output Y ; +input in ; +output out ; +input mem_out ; + +wire aps_rename_1_ ; + +assign A = in ; +assign out = Y ; + +sky130_fd_sc_hd__inv_1 ie_oe_inv ( .A ( aps_rename_1_ ) , .Y ( OE ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__1 ( .A ( mem_out ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_9 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_9 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_12 ( .A ( BUF_net_9 ) , .X ( IE ) ) ; +endmodule + + +module logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , iopad_outpad , + ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] GPIO_0_en ; + +GPIO GPIO_0_ ( .A ( gfpga_pad_GPIO_A[0] ) , .IE ( gfpga_pad_GPIO_IE[0] ) , + .OE ( gfpga_pad_GPIO_OE[0] ) , .Y ( gfpga_pad_GPIO_Y[0] ) , + .in ( iopad_outpad[0] ) , .out ( iopad_inpad[0] ) , + .mem_out ( GPIO_0_en[0] ) ) ; +GPIO_sky130_fd_sc_hd__dfxbp_1_mem GPIO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( GPIO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +endmodule + + +module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , io_outpad , + ccff_head , io_inpad , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , .iopad_outpad ( io_outpad ) , + .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , + .ccff_tail ( ccff_tail ) ) ; +direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_inpad ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module grid_io_top ( prog_clk , gfpga_pad_GPIO_A , gfpga_pad_GPIO_IE , + gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , bottom_width_0_height_0__pin_0_ , + ccff_head , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , ccff_tail ) ; +input [0:0] prog_clk ; +output [0:0] gfpga_pad_GPIO_A ; +output [0:0] gfpga_pad_GPIO_IE ; +output [0:0] gfpga_pad_GPIO_OE ; +inout [0:0] gfpga_pad_GPIO_Y ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +input [0:0] ccff_head ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +output [0:0] ccff_tail ; + +logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( ccff_head ) , + .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , + .ccff_tail ( { ropt_net_14 } ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( + .A ( bottom_width_0_height_0__pin_1_upper[0] ) , .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_5 ( .A ( aps_rename_2_ ) , + .X ( BUF_net_5 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_577 ( .A ( BUF_net_5 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_578 ( .A ( ropt_net_14 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_21 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +output p_abuf1 ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( p_abuf1 ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_108 ( .A ( p_abuf1 ) , + .X ( net_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_133 ( .A ( net_net_133 ) , + .X ( ff_Q[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__51 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , + p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign p_abuf0 = p_abuf1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .p_abuf1 ( p_abuf1 ) ) ; +mux_tree_size2_21 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_22 mux_fabric_out_1 ( + .in ( { p_abuf1 , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_23 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__269 ( .A ( fabric_scout[0] ) , + .X ( fabric_regout[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf0 } ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( { p_abuf1 } ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__46 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_18 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_19 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_20 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__41 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_29 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_15 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_16 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_17 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_28 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_12 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_13 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_14 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_10 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_9 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p2 ( p2 ) ) ; +mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p2 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_26 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_6 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_7 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_8 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p0 ( p0 ) ) ; +mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_25 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_25 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p0 , + p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_3 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_4 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p0 ( p0 ) ) ; +mux_tree_size2_5 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p0 , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p0 ; +input p1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_1 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .Q_N ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , + mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , + lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , + Test_en , clk , fabric_in , fabric_regin , fabric_scin , fabric_clk , + ccff_head , fabric_out , fabric_regout , fabric_scout , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_scin ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_scout ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_scout[0] ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_scin ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_scout ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +mux_tree_size2_0 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_1 mux_fabric_out_1 ( + .in ( { fabric_scout[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p1 ( p1 ) ) ; +mux_tree_size2_2 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p1 ( p1 ) ) ; +mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_scout ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_scin ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , + fle_in , fle_regin , fle_scin , fle_clk , ccff_head , fle_out , + fle_regout , fle_scout , ccff_tail , p1 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_scin ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_scout ; +output [0:0] ccff_tail ; +input p1 ; + +logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_scin ( fle_scin ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_scout ( fle_scout ) , + .ccff_tail ( ccff_tail ) , .p1 ( p1 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( fle_out[0] ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_out[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_regout ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_scout ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[0] ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[1] ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[2] ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[3] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_regin ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_scin ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , + clb_I1 , clb_I2 , clb_I3 , clb_I4 , clb_I5 , clb_I6 , clb_I7 , clb_regin , + clb_scin , clb_clk , ccff_head , clb_O , clb_regout , clb_scout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , + p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , + p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] clb_I0 ; +input [0:3] clb_I1 ; +input [0:3] clb_I2 ; +input [0:3] clb_I3 ; +input [0:3] clb_I4 ; +input [0:3] clb_I5 ; +input [0:3] clb_I6 ; +input [0:3] clb_I7 ; +input [0:0] clb_regin ; +input [0:0] clb_scin ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_regout ; +output [0:0] clb_scout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_0_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_2_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_3_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_scout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_scout ; + +logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I0 ) , .fle_regin ( clb_regin ) , .fle_scin ( clb_scin ) , + .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , logical_tile_clb_mode_default__fle_0_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I1 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_0_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .p0 ( p0 ) , .p1 ( p2 ) ) ; +logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I2 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_1_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { p_abuf4 , logical_tile_clb_mode_default__fle_2_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .p0 ( p0 ) ) ; +logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I3 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_2_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , logical_tile_clb_mode_default__fle_3_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .p2 ( p3 ) ) ; +logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I4 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_3_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I5 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_4_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_5_fle_out[0] , clb_O[10] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I6 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_5_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { logical_tile_clb_mode_default__fle_6_fle_out[0] , clb_O[12] } ) , + .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scout ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .p0 ( p1 ) ) ; +logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fle_in ( clb_I7 ) , + .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , + .fle_scin ( logical_tile_clb_mode_default__fle_6_fle_scout ) , + .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_regout ( clb_regout ) , .fle_scout ( clb_scout ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf16 ) , .p_abuf1 ( p_abuf17 ) , + .p2 ( p3 ) ) ; +direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_out ) ) ; +direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( clb_O[1] ) ) ; +direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( clb_O[2] ) ) ; +direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( clb_O[3] ) ) ; +direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_out ) ) ; +direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf4 } ) ) ; +direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; +direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( clb_O[7] ) ) ; +direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; +direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( clb_O[9] ) ) ; +direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( clb_O[10] ) ) ; +direct_interc direct_interc_11_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_out ) ) ; +direct_interc direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( clb_O[12] ) ) ; +direct_interc direct_interc_13_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_out ) ) ; +direct_interc direct_interc_14_ ( + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .out ( clb_O[14] ) ) ; +direct_interc direct_interc_15_ ( + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , + .out ( clb_O[15] ) ) ; +direct_interc direct_interc_16_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , + .out ( { p_abuf16 } ) ) ; +direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , + .out ( { p_abuf17 } ) ) ; +direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , + .out ( clb_I0[0] ) ) ; +direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .out ( clb_I0[1] ) ) ; +direct_interc direct_interc_20_ ( + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , + .out ( clb_I0[2] ) ) ; +direct_interc direct_interc_21_ ( + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .out ( clb_I0[3] ) ) ; +direct_interc direct_interc_22_ ( + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , + .out ( clb_regin ) ) ; +direct_interc direct_interc_23_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , + .out ( clb_scin ) ) ; +direct_interc direct_interc_24_ ( + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_25_ ( + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , + .out ( clb_I1[0] ) ) ; +direct_interc direct_interc_26_ ( + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I1[1] ) ) ; +direct_interc direct_interc_27_ ( + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , + .out ( clb_I1[2] ) ) ; +direct_interc direct_interc_28_ ( + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .out ( clb_I1[3] ) ) ; +direct_interc direct_interc_29_ ( + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; +direct_interc direct_interc_30_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , + .out ( logical_tile_clb_mode_default__fle_0_fle_scout ) ) ; +direct_interc direct_interc_31_ ( + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_32_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , + .out ( clb_I2[0] ) ) ; +direct_interc direct_interc_33_ ( + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I2[1] ) ) ; +direct_interc direct_interc_34_ ( + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , + .out ( clb_I2[2] ) ) ; +direct_interc direct_interc_35_ ( + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .out ( clb_I2[3] ) ) ; +direct_interc direct_interc_36_ ( + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; +direct_interc direct_interc_37_ ( + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , + .out ( logical_tile_clb_mode_default__fle_1_fle_scout ) ) ; +direct_interc direct_interc_38_ ( + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_39_ ( + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , + .out ( clb_I3[0] ) ) ; +direct_interc direct_interc_40_ ( + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I3[1] ) ) ; +direct_interc direct_interc_41_ ( + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , + .out ( clb_I3[2] ) ) ; +direct_interc direct_interc_42_ ( + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .out ( clb_I3[3] ) ) ; +direct_interc direct_interc_43_ ( + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; +direct_interc direct_interc_44_ ( + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , + .out ( logical_tile_clb_mode_default__fle_2_fle_scout ) ) ; +direct_interc direct_interc_45_ ( + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_46_ ( + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , + .out ( clb_I4[0] ) ) ; +direct_interc direct_interc_47_ ( + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I4[1] ) ) ; +direct_interc direct_interc_48_ ( + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , + .out ( clb_I4[2] ) ) ; +direct_interc direct_interc_49_ ( + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .out ( clb_I4[3] ) ) ; +direct_interc direct_interc_50_ ( + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; +direct_interc direct_interc_51_ ( + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , + .out ( logical_tile_clb_mode_default__fle_3_fle_scout ) ) ; +direct_interc direct_interc_52_ ( + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_53_ ( + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , + .out ( clb_I5[0] ) ) ; +direct_interc direct_interc_54_ ( + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I5[1] ) ) ; +direct_interc direct_interc_55_ ( + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .out ( clb_I5[2] ) ) ; +direct_interc direct_interc_56_ ( + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .out ( clb_I5[3] ) ) ; +direct_interc direct_interc_57_ ( + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; +direct_interc direct_interc_58_ ( + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , + .out ( logical_tile_clb_mode_default__fle_4_fle_scout ) ) ; +direct_interc direct_interc_59_ ( + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , + .out ( clb_I6[0] ) ) ; +direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I6[1] ) ) ; +direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , + .out ( clb_I6[2] ) ) ; +direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .out ( clb_I6[3] ) ) ; +direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; +direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_scout ) ) ; +direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , + .out ( clb_clk ) ) ; +direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , + .out ( clb_I7[0] ) ) ; +direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_69 } ) , + .out ( clb_I7[1] ) ) ; +direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_70 } ) , + .out ( clb_I7[2] ) ) ; +direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_71 } ) , + .out ( clb_I7[3] ) ) ; +direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_72 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; +direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_73 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_scout ) ) ; +direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .out ( clb_clk ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , .X ( clb_O[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( clb_O[1] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( logical_tile_clb_mode_default__fle_0_fle_out[1] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( .A ( p_abuf4 ) , + .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( clb_O[3] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( clb_O[2] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , .X ( clb_O[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( logical_tile_clb_mode_default__fle_2_fle_out[1] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , .X ( clb_O[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( clb_O[7] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( + .A ( logical_tile_clb_mode_default__fle_3_fle_out[1] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( + .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( clb_O[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( + .A ( logical_tile_clb_mode_default__fle_5_fle_out[0] ) , + .X ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( clb_O[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , + .X ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( + .A ( logical_tile_clb_mode_default__fle_6_fle_out[0] ) , + .X ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_62 ) , + .X ( p_abuf2 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_83 ( .A ( clb_O[12] ) , + .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( clb_O[15] ) , + .X ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( clb_O[14] ) , + .X ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_104 ( .A ( BUF_net_64 ) , + .X ( p_abuf3 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_67 ) , + .X ( p_abuf5 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_106 ( .A ( BUF_net_69 ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( BUF_net_58 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , + .X ( clb_O[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_71 ) , + .X ( p_abuf7 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_73 ) , + .X ( p_abuf8 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_75 ) , + .X ( p_abuf9 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( .A ( BUF_net_77 ) , + .X ( p_abuf10 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_118 ( .A ( BUF_net_79 ) , + .X ( p_abuf11 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( BUF_net_81 ) , + .X ( p_abuf12 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_83 ) , + .X ( p_abuf13 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( BUF_net_85 ) , + .X ( p_abuf14 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_87 ) , + .X ( p_abuf15 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( BUF_net_106 ) , + .X ( p_abuf6 ) ) ; +endmodule + + +module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_0_ , + right_width_0_height_0__pin_1_ , right_width_0_height_0__pin_2_ , + right_width_0_height_0__pin_3_ , right_width_0_height_0__pin_4_ , + right_width_0_height_0__pin_5_ , right_width_0_height_0__pin_6_ , + right_width_0_height_0__pin_7_ , right_width_0_height_0__pin_8_ , + right_width_0_height_0__pin_9_ , right_width_0_height_0__pin_10_ , + right_width_0_height_0__pin_11_ , right_width_0_height_0__pin_12_ , + right_width_0_height_0__pin_13_ , right_width_0_height_0__pin_14_ , + right_width_0_height_0__pin_15_ , bottom_width_0_height_0__pin_16_ , + bottom_width_0_height_0__pin_17_ , bottom_width_0_height_0__pin_18_ , + bottom_width_0_height_0__pin_19_ , bottom_width_0_height_0__pin_20_ , + bottom_width_0_height_0__pin_21_ , bottom_width_0_height_0__pin_22_ , + bottom_width_0_height_0__pin_23_ , bottom_width_0_height_0__pin_24_ , + bottom_width_0_height_0__pin_25_ , bottom_width_0_height_0__pin_26_ , + bottom_width_0_height_0__pin_27_ , bottom_width_0_height_0__pin_28_ , + bottom_width_0_height_0__pin_29_ , bottom_width_0_height_0__pin_30_ , + bottom_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , + ccff_head , right_width_0_height_0__pin_34_upper , + right_width_0_height_0__pin_34_lower , + right_width_0_height_0__pin_35_upper , + right_width_0_height_0__pin_35_lower , + right_width_0_height_0__pin_36_upper , + right_width_0_height_0__pin_36_lower , + right_width_0_height_0__pin_37_upper , + right_width_0_height_0__pin_37_lower , + right_width_0_height_0__pin_38_upper , + right_width_0_height_0__pin_38_lower , + right_width_0_height_0__pin_39_upper , + right_width_0_height_0__pin_39_lower , + right_width_0_height_0__pin_40_upper , + right_width_0_height_0__pin_40_lower , + right_width_0_height_0__pin_41_upper , + right_width_0_height_0__pin_41_lower , + bottom_width_0_height_0__pin_42_upper , + bottom_width_0_height_0__pin_42_lower , + bottom_width_0_height_0__pin_43_upper , + bottom_width_0_height_0__pin_43_lower , + bottom_width_0_height_0__pin_44_upper , + bottom_width_0_height_0__pin_44_lower , + bottom_width_0_height_0__pin_45_upper , + bottom_width_0_height_0__pin_45_lower , + bottom_width_0_height_0__pin_46_upper , + bottom_width_0_height_0__pin_46_lower , + bottom_width_0_height_0__pin_47_upper , + bottom_width_0_height_0__pin_47_lower , + bottom_width_0_height_0__pin_48_upper , + bottom_width_0_height_0__pin_48_lower , + bottom_width_0_height_0__pin_49_upper , + bottom_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , + bottom_width_0_height_0__pin_51_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] right_width_0_height_0__pin_0_ ; +input [0:0] right_width_0_height_0__pin_1_ ; +input [0:0] right_width_0_height_0__pin_2_ ; +input [0:0] right_width_0_height_0__pin_3_ ; +input [0:0] right_width_0_height_0__pin_4_ ; +input [0:0] right_width_0_height_0__pin_5_ ; +input [0:0] right_width_0_height_0__pin_6_ ; +input [0:0] right_width_0_height_0__pin_7_ ; +input [0:0] right_width_0_height_0__pin_8_ ; +input [0:0] right_width_0_height_0__pin_9_ ; +input [0:0] right_width_0_height_0__pin_10_ ; +input [0:0] right_width_0_height_0__pin_11_ ; +input [0:0] right_width_0_height_0__pin_12_ ; +input [0:0] right_width_0_height_0__pin_13_ ; +input [0:0] right_width_0_height_0__pin_14_ ; +input [0:0] right_width_0_height_0__pin_15_ ; +input [0:0] bottom_width_0_height_0__pin_16_ ; +input [0:0] bottom_width_0_height_0__pin_17_ ; +input [0:0] bottom_width_0_height_0__pin_18_ ; +input [0:0] bottom_width_0_height_0__pin_19_ ; +input [0:0] bottom_width_0_height_0__pin_20_ ; +input [0:0] bottom_width_0_height_0__pin_21_ ; +input [0:0] bottom_width_0_height_0__pin_22_ ; +input [0:0] bottom_width_0_height_0__pin_23_ ; +input [0:0] bottom_width_0_height_0__pin_24_ ; +input [0:0] bottom_width_0_height_0__pin_25_ ; +input [0:0] bottom_width_0_height_0__pin_26_ ; +input [0:0] bottom_width_0_height_0__pin_27_ ; +input [0:0] bottom_width_0_height_0__pin_28_ ; +input [0:0] bottom_width_0_height_0__pin_29_ ; +input [0:0] bottom_width_0_height_0__pin_30_ ; +input [0:0] bottom_width_0_height_0__pin_31_ ; +input [0:0] left_width_0_height_0__pin_52_ ; +input [0:0] ccff_head ; +output [0:0] right_width_0_height_0__pin_34_upper ; +output [0:0] right_width_0_height_0__pin_34_lower ; +output [0:0] right_width_0_height_0__pin_35_upper ; +output [0:0] right_width_0_height_0__pin_35_lower ; +output [0:0] right_width_0_height_0__pin_36_upper ; +output [0:0] right_width_0_height_0__pin_36_lower ; +output [0:0] right_width_0_height_0__pin_37_upper ; +output [0:0] right_width_0_height_0__pin_37_lower ; +output [0:0] right_width_0_height_0__pin_38_upper ; +output [0:0] right_width_0_height_0__pin_38_lower ; +output [0:0] right_width_0_height_0__pin_39_upper ; +output [0:0] right_width_0_height_0__pin_39_lower ; +output [0:0] right_width_0_height_0__pin_40_upper ; +output [0:0] right_width_0_height_0__pin_40_lower ; +output [0:0] right_width_0_height_0__pin_41_upper ; +output [0:0] right_width_0_height_0__pin_41_lower ; +output [0:0] bottom_width_0_height_0__pin_42_upper ; +output [0:0] bottom_width_0_height_0__pin_42_lower ; +output [0:0] bottom_width_0_height_0__pin_43_upper ; +output [0:0] bottom_width_0_height_0__pin_43_lower ; +output [0:0] bottom_width_0_height_0__pin_44_upper ; +output [0:0] bottom_width_0_height_0__pin_44_lower ; +output [0:0] bottom_width_0_height_0__pin_45_upper ; +output [0:0] bottom_width_0_height_0__pin_45_lower ; +output [0:0] bottom_width_0_height_0__pin_46_upper ; +output [0:0] bottom_width_0_height_0__pin_46_lower ; +output [0:0] bottom_width_0_height_0__pin_47_upper ; +output [0:0] bottom_width_0_height_0__pin_47_lower ; +output [0:0] bottom_width_0_height_0__pin_48_upper ; +output [0:0] bottom_width_0_height_0__pin_48_lower ; +output [0:0] bottom_width_0_height_0__pin_49_upper ; +output [0:0] bottom_width_0_height_0__pin_49_lower ; +output [0:0] bottom_width_0_height_0__pin_50_ ; +output [0:0] bottom_width_0_height_0__pin_51_ ; +output [0:0] ccff_tail ; + +wire ropt_net_161 ; +wire ropt_net_160 ; +wire ropt_net_157 ; +wire ropt_net_151 ; +wire ropt_net_152 ; +wire p_abuf4 ; +wire ropt_net_148 ; +wire ropt_net_156 ; +wire ropt_net_145 ; +wire ropt_net_159 ; +wire ropt_net_165 ; +wire ropt_net_167 ; +wire ropt_net_184 ; +wire ropt_net_163 ; + +logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .clb_I0 ( { right_width_0_height_0__pin_0_[0] , + right_width_0_height_0__pin_1_[0] , + right_width_0_height_0__pin_2_[0] , + right_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { right_width_0_height_0__pin_4_[0] , + right_width_0_height_0__pin_5_[0] , + right_width_0_height_0__pin_6_[0] , + right_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { right_width_0_height_0__pin_8_[0] , + right_width_0_height_0__pin_9_[0] , + right_width_0_height_0__pin_10_[0] , + right_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { right_width_0_height_0__pin_12_[0] , + right_width_0_height_0__pin_13_[0] , + right_width_0_height_0__pin_14_[0] , + right_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { bottom_width_0_height_0__pin_16_[0] , + bottom_width_0_height_0__pin_17_[0] , + bottom_width_0_height_0__pin_18_[0] , + bottom_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { bottom_width_0_height_0__pin_20_[0] , + bottom_width_0_height_0__pin_21_[0] , + bottom_width_0_height_0__pin_22_[0] , + bottom_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { bottom_width_0_height_0__pin_24_[0] , + bottom_width_0_height_0__pin_25_[0] , + bottom_width_0_height_0__pin_26_[0] , + bottom_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { bottom_width_0_height_0__pin_28_[0] , + bottom_width_0_height_0__pin_29_[0] , + bottom_width_0_height_0__pin_30_[0] , + bottom_width_0_height_0__pin_31_[0] } ) , + .clb_regin ( top_width_0_height_0__pin_32_ ) , + .clb_scin ( top_width_0_height_0__pin_33_ ) , + .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_130_ , aps_rename_132_ , aps_rename_134_ , + aps_rename_136_ , aps_rename_138_ , + right_width_0_height_0__pin_39_upper[0] , aps_rename_141_ , + aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , + aps_rename_149_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_155_ , aps_rename_157_ , aps_rename_158_ } ) , + .clb_regout ( bottom_width_0_height_0__pin_50_ ) , + .clb_scout ( bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( { ropt_net_168 } ) , + .p_abuf0 ( ropt_net_160 ) , .p_abuf1 ( ropt_net_161 ) , + .p_abuf2 ( ropt_net_151 ) , .p_abuf3 ( ropt_net_157 ) , + .p_abuf4 ( p_abuf4 ) , .p_abuf5 ( ropt_net_152 ) , + .p_abuf6 ( ropt_net_148 ) , + .p_abuf7 ( right_width_0_height_0__pin_40_upper[0] ) , + .p_abuf8 ( bottom_width_0_height_0__pin_43_upper[0] ) , + .p_abuf9 ( ropt_net_156 ) , .p_abuf10 ( ropt_net_159 ) , + .p_abuf11 ( ropt_net_145 ) , .p_abuf12 ( ropt_net_167 ) , + .p_abuf13 ( ropt_net_165 ) , .p_abuf14 ( ropt_net_163 ) , + .p_abuf15 ( ropt_net_184 ) , .p0 ( optlc_net_135 ) , + .p1 ( optlc_net_136 ) , .p2 ( optlc_net_137 ) , .p3 ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( aps_rename_130_ ) , + .X ( aps_rename_131_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( aps_rename_132_ ) , + .X ( aps_rename_133_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( aps_rename_134_ ) , + .X ( aps_rename_135_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( aps_rename_136_ ) , + .X ( aps_rename_137_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( aps_rename_138_ ) , + .X ( aps_rename_139_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( p_abuf4 ) , + .X ( aps_rename_140_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_141_ ) , + .X ( aps_rename_142_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( aps_rename_143_ ) , + .X ( aps_rename_144_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( aps_rename_145_ ) , + .X ( aps_rename_146_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( aps_rename_147_ ) , + .X ( aps_rename_148_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( aps_rename_149_ ) , + .X ( aps_rename_150_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( aps_rename_153_ ) , + .X ( aps_rename_154_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( aps_rename_155_ ) , + .X ( aps_rename_156_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( aps_rename_131_ ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( aps_rename_133_ ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_135_ ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_137_ ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_142_ ) , + .X ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_144_ ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_146_ ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( .A ( aps_rename_148_ ) , + .X ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_99 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_156_ ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( aps_rename_159_ ) , + .X ( bottom_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( .A ( BUF_net_93 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( .A ( BUF_net_95 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( BUF_net_126 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( .A ( BUF_net_96 ) , + .X ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( BUF_net_98 ) , + .X ( bottom_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( BUF_net_99 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_129 ( .A ( BUF_net_101 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( BUF_net_102 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_963 ( .A ( ropt_net_143 ) , + .X ( bottom_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_964 ( .A ( ropt_net_144 ) , + .X ( bottom_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_965 ( .A ( ropt_net_145 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_966 ( .A ( ropt_net_146 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_967 ( .A ( ropt_net_147 ) , + .X ( right_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_968 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_969 ( .A ( ropt_net_149 ) , + .X ( bottom_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_970 ( .A ( ropt_net_150 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_971 ( .A ( ropt_net_151 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_972 ( .A ( ropt_net_152 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_973 ( .A ( ropt_net_153 ) , + .X ( right_width_0_height_0__pin_36_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_974 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_975 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_976 ( .A ( ropt_net_156 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_977 ( .A ( ropt_net_157 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_978 ( .A ( ropt_net_158 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_979 ( .A ( ropt_net_159 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_980 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_981 ( .A ( ropt_net_161 ) , + .X ( right_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_982 ( .A ( ropt_net_162 ) , + .X ( right_width_0_height_0__pin_40_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_983 ( .A ( ropt_net_163 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_984 ( .A ( ropt_net_164 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_986 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_989 ( .A ( ropt_net_166 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_990 ( .A ( ropt_net_167 ) , + .X ( bottom_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_168 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_997 ( .A ( ropt_net_170 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_998 ( .A ( ropt_net_171 ) , + .X ( bottom_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_999 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1000 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1001 ( .A ( ropt_net_174 ) , + .X ( bottom_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1002 ( .A ( ropt_net_175 ) , + .X ( bottom_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1004 ( .A ( ropt_net_176 ) , + .X ( right_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1005 ( .A ( ropt_net_177 ) , + .X ( bottom_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1006 ( .A ( ropt_net_178 ) , + .X ( right_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1007 ( .A ( ropt_net_179 ) , + .X ( right_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1009 ( .A ( ropt_net_180 ) , + .X ( bottom_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1012 ( .A ( ropt_net_181 ) , + .X ( bottom_width_0_height_0__pin_46_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1013 ( .A ( ropt_net_182 ) , + .X ( bottom_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1015 ( .A ( ropt_net_183 ) , + .X ( right_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1016 ( .A ( ropt_net_184 ) , + .X ( bottom_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1020 ( .A ( ropt_net_185 ) , + .X ( right_width_0_height_0__pin_36_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1022 ( .A ( ropt_net_186 ) , + .X ( right_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_1027 ( .A ( ropt_net_187 ) , + .X ( right_width_0_height_0__pin_41_lower[0] ) ) ; +endmodule + + +module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_GPIO_A , + gfpga_pad_GPIO_IE , gfpga_pad_GPIO_OE , gfpga_pad_GPIO_Y , ccff_head , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +output [0:7] gfpga_pad_GPIO_A ; +output [0:7] gfpga_pad_GPIO_IE ; +output [0:7] gfpga_pad_GPIO_OE ; +inout [0:7] gfpga_pad_GPIO_Y ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:19] cbx_1__0__0_chanx_left_out ; +wire [0:19] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:19] cbx_1__0__1_chanx_left_out ; +wire [0:19] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__0__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:19] cbx_1__1__0_chanx_left_out ; +wire [0:19] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__0_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__0_top_grid_pin_31_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:19] cbx_1__1__1_chanx_left_out ; +wire [0:19] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__1_top_grid_pin_16_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_17_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_18_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_19_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_20_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_21_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_22_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_23_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_24_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_25_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_26_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_27_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_28_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_29_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_30_ ; +wire [0:0] cbx_1__1__1_top_grid_pin_31_ ; +wire [0:0] cbx_1__2__0_ccff_tail ; +wire [0:19] cbx_1__2__0_chanx_left_out ; +wire [0:19] cbx_1__2__0_chanx_right_out ; +wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__2__1_ccff_tail ; +wire [0:19] cbx_1__2__1_chanx_left_out ; +wire [0:19] cbx_1__2__1_chanx_right_out ; +wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:19] cby_0__1__0_chany_bottom_out ; +wire [0:19] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__0_right_grid_pin_52_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:19] cby_0__1__1_chany_bottom_out ; +wire [0:19] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:19] cby_1__1__0_chany_bottom_out ; +wire [0:19] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_0_ ; +wire [0:0] cby_1__1__0_left_grid_pin_10_ ; +wire [0:0] cby_1__1__0_left_grid_pin_11_ ; +wire [0:0] cby_1__1__0_left_grid_pin_12_ ; +wire [0:0] cby_1__1__0_left_grid_pin_13_ ; +wire [0:0] cby_1__1__0_left_grid_pin_14_ ; +wire [0:0] cby_1__1__0_left_grid_pin_15_ ; +wire [0:0] cby_1__1__0_left_grid_pin_1_ ; +wire [0:0] cby_1__1__0_left_grid_pin_2_ ; +wire [0:0] cby_1__1__0_left_grid_pin_3_ ; +wire [0:0] cby_1__1__0_left_grid_pin_4_ ; +wire [0:0] cby_1__1__0_left_grid_pin_5_ ; +wire [0:0] cby_1__1__0_left_grid_pin_6_ ; +wire [0:0] cby_1__1__0_left_grid_pin_7_ ; +wire [0:0] cby_1__1__0_left_grid_pin_8_ ; +wire [0:0] cby_1__1__0_left_grid_pin_9_ ; +wire [0:0] cby_1__1__0_right_grid_pin_52_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:19] cby_1__1__1_chany_bottom_out ; +wire [0:19] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_0_ ; +wire [0:0] cby_1__1__1_left_grid_pin_10_ ; +wire [0:0] cby_1__1__1_left_grid_pin_11_ ; +wire [0:0] cby_1__1__1_left_grid_pin_12_ ; +wire [0:0] cby_1__1__1_left_grid_pin_13_ ; +wire [0:0] cby_1__1__1_left_grid_pin_14_ ; +wire [0:0] cby_1__1__1_left_grid_pin_15_ ; +wire [0:0] cby_1__1__1_left_grid_pin_1_ ; +wire [0:0] cby_1__1__1_left_grid_pin_2_ ; +wire [0:0] cby_1__1__1_left_grid_pin_3_ ; +wire [0:0] cby_1__1__1_left_grid_pin_4_ ; +wire [0:0] cby_1__1__1_left_grid_pin_5_ ; +wire [0:0] cby_1__1__1_left_grid_pin_6_ ; +wire [0:0] cby_1__1__1_left_grid_pin_7_ ; +wire [0:0] cby_1__1__1_left_grid_pin_8_ ; +wire [0:0] cby_1__1__1_left_grid_pin_9_ ; +wire [0:0] cby_1__1__1_right_grid_pin_52_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:19] cby_1__1__2_chany_bottom_out ; +wire [0:19] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_0_ ; +wire [0:0] cby_1__1__2_left_grid_pin_10_ ; +wire [0:0] cby_1__1__2_left_grid_pin_11_ ; +wire [0:0] cby_1__1__2_left_grid_pin_12_ ; +wire [0:0] cby_1__1__2_left_grid_pin_13_ ; +wire [0:0] cby_1__1__2_left_grid_pin_14_ ; +wire [0:0] cby_1__1__2_left_grid_pin_15_ ; +wire [0:0] cby_1__1__2_left_grid_pin_1_ ; +wire [0:0] cby_1__1__2_left_grid_pin_2_ ; +wire [0:0] cby_1__1__2_left_grid_pin_3_ ; +wire [0:0] cby_1__1__2_left_grid_pin_4_ ; +wire [0:0] cby_1__1__2_left_grid_pin_5_ ; +wire [0:0] cby_1__1__2_left_grid_pin_6_ ; +wire [0:0] cby_1__1__2_left_grid_pin_7_ ; +wire [0:0] cby_1__1__2_left_grid_pin_8_ ; +wire [0:0] cby_1__1__2_left_grid_pin_9_ ; +wire [0:0] cby_1__1__2_right_grid_pin_52_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:19] cby_1__1__3_chany_bottom_out ; +wire [0:19] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_0_ ; +wire [0:0] cby_1__1__3_left_grid_pin_10_ ; +wire [0:0] cby_1__1__3_left_grid_pin_11_ ; +wire [0:0] cby_1__1__3_left_grid_pin_12_ ; +wire [0:0] cby_1__1__3_left_grid_pin_13_ ; +wire [0:0] cby_1__1__3_left_grid_pin_14_ ; +wire [0:0] cby_1__1__3_left_grid_pin_15_ ; +wire [0:0] cby_1__1__3_left_grid_pin_1_ ; +wire [0:0] cby_1__1__3_left_grid_pin_2_ ; +wire [0:0] cby_1__1__3_left_grid_pin_3_ ; +wire [0:0] cby_1__1__3_left_grid_pin_4_ ; +wire [0:0] cby_1__1__3_left_grid_pin_5_ ; +wire [0:0] cby_1__1__3_left_grid_pin_6_ ; +wire [0:0] cby_1__1__3_left_grid_pin_7_ ; +wire [0:0] cby_1__1__3_left_grid_pin_8_ ; +wire [0:0] cby_1__1__3_left_grid_pin_9_ ; +wire [0:0] cby_1__1__3_right_grid_pin_52_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; +wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_34_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_35_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_41_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:19] sb_0__0__0_chanx_right_out ; +wire [0:19] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:19] sb_0__1__0_chanx_right_out ; +wire [0:19] sb_0__1__0_chany_bottom_out ; +wire [0:19] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__2__0_ccff_tail ; +wire [0:19] sb_0__2__0_chanx_right_out ; +wire [0:19] sb_0__2__0_chany_bottom_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:19] sb_1__0__0_chanx_left_out ; +wire [0:19] sb_1__0__0_chanx_right_out ; +wire [0:19] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:19] sb_1__1__0_chanx_left_out ; +wire [0:19] sb_1__1__0_chanx_right_out ; +wire [0:19] sb_1__1__0_chany_bottom_out ; +wire [0:19] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__2__0_ccff_tail ; +wire [0:19] sb_1__2__0_chanx_left_out ; +wire [0:19] sb_1__2__0_chanx_right_out ; +wire [0:19] sb_1__2__0_chany_bottom_out ; +wire [0:0] sb_2__0__0_ccff_tail ; +wire [0:19] sb_2__0__0_chanx_left_out ; +wire [0:19] sb_2__0__0_chany_top_out ; +wire [0:0] sb_2__1__0_ccff_tail ; +wire [0:19] sb_2__1__0_chanx_left_out ; +wire [0:19] sb_2__1__0_chany_bottom_out ; +wire [0:19] sb_2__1__0_chany_top_out ; +wire [0:0] sb_2__2__0_ccff_tail ; +wire [0:19] sb_2__2__0_chanx_left_out ; +wire [0:19] sb_2__2__0_chany_bottom_out ; +// + +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1827 } ) , + .Test_en ( { BUF_net_9 } ) , + .clk ( clk ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_3_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_33 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .ccff_head ( { ropt_net_40 } ) , + + .right_width_0_height_0__pin_34_upper ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_1_ccff_tail ) ) ; +grid_clb grid_clb_2__1_ ( + .prog_clk ( { ctsbuf_net_413 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_4_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_2_ccff_tail ) ) ; +grid_clb grid_clb_2__2_ ( + .prog_clk ( { ctsbuf_net_615 } ) , + .Test_en ( Test_en ) , .clk ( clk ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .right_width_0_height_0__pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .right_width_0_height_0__pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .right_width_0_height_0__pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .right_width_0_height_0__pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .right_width_0_height_0__pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .right_width_0_height_0__pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .right_width_0_height_0__pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .right_width_0_height_0__pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .right_width_0_height_0__pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .right_width_0_height_0__pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .right_width_0_height_0__pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .right_width_0_height_0__pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .right_width_0_height_0__pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .right_width_0_height_0__pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .right_width_0_height_0__pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .bottom_width_0_height_0__pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .bottom_width_0_height_0__pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .bottom_width_0_height_0__pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .bottom_width_0_height_0__pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .bottom_width_0_height_0__pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .bottom_width_0_height_0__pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .bottom_width_0_height_0__pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .bottom_width_0_height_0__pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .bottom_width_0_height_0__pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .bottom_width_0_height_0__pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .bottom_width_0_height_0__pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .bottom_width_0_height_0__pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .bottom_width_0_height_0__pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .bottom_width_0_height_0__pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .bottom_width_0_height_0__pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .bottom_width_0_height_0__pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .left_width_0_height_0__pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .right_width_0_height_0__pin_34_upper ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .right_width_0_height_0__pin_34_lower ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .right_width_0_height_0__pin_35_upper ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .right_width_0_height_0__pin_35_lower ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .right_width_0_height_0__pin_36_upper ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .right_width_0_height_0__pin_36_lower ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .right_width_0_height_0__pin_37_upper ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .right_width_0_height_0__pin_37_lower ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .right_width_0_height_0__pin_38_upper ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .right_width_0_height_0__pin_38_lower ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .right_width_0_height_0__pin_39_upper ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .right_width_0_height_0__pin_39_lower ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .right_width_0_height_0__pin_40_upper ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .right_width_0_height_0__pin_40_lower ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .right_width_0_height_0__pin_41_upper ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .right_width_0_height_0__pin_41_lower ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .bottom_width_0_height_0__pin_42_upper ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .bottom_width_0_height_0__pin_42_lower ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .bottom_width_0_height_0__pin_43_upper ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .bottom_width_0_height_0__pin_43_lower ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .bottom_width_0_height_0__pin_44_upper ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .bottom_width_0_height_0__pin_44_lower ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .bottom_width_0_height_0__pin_45_upper ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .bottom_width_0_height_0__pin_45_lower ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .bottom_width_0_height_0__pin_46_upper ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .bottom_width_0_height_0__pin_46_lower ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .bottom_width_0_height_0__pin_47_upper ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .bottom_width_0_height_0__pin_47_lower ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .bottom_width_0_height_0__pin_48_upper ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .bottom_width_0_height_0__pin_48_lower ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .bottom_width_0_height_0__pin_49_upper ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .bottom_width_0_height_0__pin_49_lower ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .ccff_tail ( grid_clb_3_ccff_tail ) ) ; +grid_io_top grid_io_top_1__3_ ( + .prog_clk ( { ctsbuf_net_918 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[0] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[0] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[0] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__0_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) ) ; +grid_io_top grid_io_top_2__3_ ( + .prog_clk ( { ctsbuf_net_514 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[1] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[1] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[1] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_head ( cbx_1__2__1_ccff_tail ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) ) ; +grid_io_right grid_io_right_3__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[2] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[2] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[2] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[2] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__2_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) ) ; +grid_io_right grid_io_right_3__2_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[3] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[3] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[3] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[3] ) , + .left_width_0_height_0__pin_0_ ( cby_1__1__3_right_grid_pin_52_ ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) ) ; +grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[4] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[4] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[4] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[4] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__0_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) ) ; +grid_io_bottom grid_io_bottom_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[5] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[5] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[5] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[5] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_head ( cbx_1__0__1_ccff_tail ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) ) ; +grid_io_left grid_io_left_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[6] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[6] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[6] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[6] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__0_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) ) ; +grid_io_left grid_io_left_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .gfpga_pad_GPIO_A ( gfpga_pad_GPIO_A[7] ) , + .gfpga_pad_GPIO_IE ( gfpga_pad_GPIO_IE[7] ) , + .gfpga_pad_GPIO_OE ( gfpga_pad_GPIO_OE[7] ) , + .gfpga_pad_GPIO_Y ( gfpga_pad_GPIO_Y[7] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_head ( cby_0__1__1_ccff_tail ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) ) ; +sb_0__1_ sb_0__1_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; +sb_0__2_ sb_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( { ropt_net_38 } ) , + .chanx_right_out ( sb_0__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , + .ccff_tail ( sb_0__2__0_ccff_tail ) ) ; +sb_1__0_ sb_1__0_ ( + .prog_clk ( { ctsbuf_net_211 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_upper ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_0_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_0_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_0_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_0_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_0_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_0_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_0_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_0_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_1423 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_upper ) , + .right_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_upper ) , + .right_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_upper ) , + .right_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_upper ) , + .right_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_upper ) , + .right_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_upper ) , + .right_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_upper ) , + .right_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_0_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_0_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_0_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_0_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_0_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_0_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_0_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_0_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_1_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_1_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_1_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_1_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_1_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_1_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_1_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_1_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; +sb_1__2_ sb_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_34_ ( grid_clb_1_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_1_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_1_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_1_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_1_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_1_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_1_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_1_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( { ropt_net_36 } ) , + .chanx_right_out ( sb_1__2__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__2__0_chanx_left_out ) , + .ccff_tail ( sb_1__2__0_ccff_tail ) ) ; +sb_2__0_ sb_2__0_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_2_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_2_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_2_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_2_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_2_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_2_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_2_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_2_bottom_width_0_height_0__pin_49_lower ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_2__0__0_chany_top_out ) , + .chanx_left_out ( sb_2__0__0_chanx_left_out ) , + .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; +sb_2__1_ sb_2__1_ ( + .prog_clk ( { ctsbuf_net_1221 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_lower ) , + .top_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_lower ) , + .top_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_lower ) , + .top_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_lower ) , + .top_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_lower ) , + .top_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_lower ) , + .top_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_lower ) , + .top_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_2_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_2_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_2_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_2_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_2_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_2_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_2_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_2_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_top_grid_pin_42_ ( grid_clb_3_bottom_width_0_height_0__pin_42_lower ) , + .left_top_grid_pin_43_ ( grid_clb_3_bottom_width_0_height_0__pin_43_lower ) , + .left_top_grid_pin_44_ ( grid_clb_3_bottom_width_0_height_0__pin_44_lower ) , + .left_top_grid_pin_45_ ( grid_clb_3_bottom_width_0_height_0__pin_45_lower ) , + .left_top_grid_pin_46_ ( grid_clb_3_bottom_width_0_height_0__pin_46_lower ) , + .left_top_grid_pin_47_ ( grid_clb_3_bottom_width_0_height_0__pin_47_lower ) , + .left_top_grid_pin_48_ ( grid_clb_3_bottom_width_0_height_0__pin_48_lower ) , + .left_top_grid_pin_49_ ( grid_clb_3_bottom_width_0_height_0__pin_49_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_2__1__0_chany_top_out ) , + .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__1__0_chanx_left_out ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; +sb_2__2_ sb_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_34_ ( grid_clb_3_right_width_0_height_0__pin_34_upper ) , + .bottom_left_grid_pin_35_ ( grid_clb_3_right_width_0_height_0__pin_35_upper ) , + .bottom_left_grid_pin_36_ ( grid_clb_3_right_width_0_height_0__pin_36_upper ) , + .bottom_left_grid_pin_37_ ( grid_clb_3_right_width_0_height_0__pin_37_upper ) , + .bottom_left_grid_pin_38_ ( grid_clb_3_right_width_0_height_0__pin_38_upper ) , + .bottom_left_grid_pin_39_ ( grid_clb_3_right_width_0_height_0__pin_39_upper ) , + .bottom_left_grid_pin_40_ ( grid_clb_3_right_width_0_height_0__pin_40_upper ) , + .bottom_left_grid_pin_41_ ( grid_clb_3_right_width_0_height_0__pin_41_upper ) , + .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , + .chanx_left_out ( sb_2__2__0_chanx_left_out ) , + .ccff_tail ( sb_2__2__0_ccff_tail ) ) ; +cbx_1__0_ cbx_1__0_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__0_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__0_ccff_tail ) ) ; +cbx_1__0_ cbx_2__0_ ( + .prog_clk ( { ctsbuf_net_817 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_2__0__0_chanx_left_out ) , + .ccff_head ( sb_2__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__0__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__0__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__0__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__0__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__0__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__0__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__0__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__0__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__0__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__0__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__0__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__0__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__0__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__0__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__0__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__0__1_top_grid_pin_31_ ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .ccff_tail ( cbx_1__0__1_ccff_tail ) ) ; +cbx_1__1_ cbx_1__1_ ( + .prog_clk ( { ctsbuf_net_1726 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__0_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__0_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__0_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__0_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__0_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__0_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__0_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__0_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__0_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__0_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__0_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__0_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__0_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__0_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__0_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__0_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) ) ; +cbx_1__1_ cbx_2__1_ ( + .prog_clk ( { ctsbuf_net_1120 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_2__1__0_chanx_left_out ) , + .ccff_head ( sb_2__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .top_grid_pin_16_ ( cbx_1__1__1_top_grid_pin_16_ ) , + .top_grid_pin_17_ ( cbx_1__1__1_top_grid_pin_17_ ) , + .top_grid_pin_18_ ( cbx_1__1__1_top_grid_pin_18_ ) , + .top_grid_pin_19_ ( cbx_1__1__1_top_grid_pin_19_ ) , + .top_grid_pin_20_ ( cbx_1__1__1_top_grid_pin_20_ ) , + .top_grid_pin_21_ ( cbx_1__1__1_top_grid_pin_21_ ) , + .top_grid_pin_22_ ( cbx_1__1__1_top_grid_pin_22_ ) , + .top_grid_pin_23_ ( cbx_1__1__1_top_grid_pin_23_ ) , + .top_grid_pin_24_ ( cbx_1__1__1_top_grid_pin_24_ ) , + .top_grid_pin_25_ ( cbx_1__1__1_top_grid_pin_25_ ) , + .top_grid_pin_26_ ( cbx_1__1__1_top_grid_pin_26_ ) , + .top_grid_pin_27_ ( cbx_1__1__1_top_grid_pin_27_ ) , + .top_grid_pin_28_ ( cbx_1__1__1_top_grid_pin_28_ ) , + .top_grid_pin_29_ ( cbx_1__1__1_top_grid_pin_29_ ) , + .top_grid_pin_30_ ( cbx_1__1__1_top_grid_pin_30_ ) , + .top_grid_pin_31_ ( cbx_1__1__1_top_grid_pin_31_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) ) ; +cbx_1__2_ cbx_1__2_ ( + .prog_clk ( { ctsbuf_net_1322 } ) , + .chanx_left_in ( sb_0__2__0_chanx_right_out ) , + .chanx_right_in ( sb_1__2__0_chanx_left_out ) , + .ccff_head ( sb_1__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__0_ccff_tail ) ) ; +cbx_1__2_ cbx_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chanx_left_in ( sb_1__2__0_chanx_right_out ) , + .chanx_right_in ( sb_2__2__0_chanx_left_out ) , + .ccff_head ( sb_2__2__0_ccff_tail ) , + .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , + .ccff_tail ( cbx_1__2__1_ccff_tail ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1625 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__0_ccff_tail ) ) ; +cby_0__1_ cby_0__2_ ( + .prog_clk ( { ctsbuf_net_1524 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__2__0_chany_bottom_out ) , + .ccff_head ( sb_0__2__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_0__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( cby_0__1__1_ccff_tail ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_1019 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__0_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__0_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__0_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__0_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__0_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__0_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__0_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__0_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__0_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__0_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__0_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__0_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__0_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__0_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__0_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__0_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__0_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; +cby_1__1_ cby_1__2_ ( + .prog_clk ( { ctsbuf_net_716 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__1_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__1_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__1_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__1_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__1_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__1_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__1_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__1_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__1_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__1_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__1_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__1_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__1_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__1_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__1_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__1_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__1_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; +cby_1__1_ cby_2__1_ ( + .prog_clk ( { ctsbuf_net_110 } ) , + .chany_bottom_in ( sb_2__0__0_chany_top_out ) , + .chany_top_in ( sb_2__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__2_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__2_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__2_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__2_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__2_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__2_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__2_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__2_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__2_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__2_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__2_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__2_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__2_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__2_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__2_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__2_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__2_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) ) ; +cby_1__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_312 } ) , + .chany_bottom_in ( sb_2__1__0_chany_top_out ) , + .chany_top_in ( sb_2__2__0_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .right_grid_pin_52_ ( cby_1__1__3_right_grid_pin_52_ ) , + .left_grid_pin_0_ ( cby_1__1__3_left_grid_pin_0_ ) , + .left_grid_pin_1_ ( cby_1__1__3_left_grid_pin_1_ ) , + .left_grid_pin_2_ ( cby_1__1__3_left_grid_pin_2_ ) , + .left_grid_pin_3_ ( cby_1__1__3_left_grid_pin_3_ ) , + .left_grid_pin_4_ ( cby_1__1__3_left_grid_pin_4_ ) , + .left_grid_pin_5_ ( cby_1__1__3_left_grid_pin_5_ ) , + .left_grid_pin_6_ ( cby_1__1__3_left_grid_pin_6_ ) , + .left_grid_pin_7_ ( cby_1__1__3_left_grid_pin_7_ ) , + .left_grid_pin_8_ ( cby_1__1__3_left_grid_pin_8_ ) , + .left_grid_pin_9_ ( cby_1__1__3_left_grid_pin_9_ ) , + .left_grid_pin_10_ ( cby_1__1__3_left_grid_pin_10_ ) , + .left_grid_pin_11_ ( cby_1__1__3_left_grid_pin_11_ ) , + .left_grid_pin_12_ ( cby_1__1__3_left_grid_pin_12_ ) , + .left_grid_pin_13_ ( cby_1__1__3_left_grid_pin_13_ ) , + .left_grid_pin_14_ ( cby_1__1__3_left_grid_pin_14_ ) , + .left_grid_pin_15_ ( cby_1__1__3_left_grid_pin_15_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) ) ; +direct_interc_0 direct_interc_0_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_0_out ) ) ; +direct_interc_1 direct_interc_1_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_1_out ) ) ; +direct_interc_2 direct_interc_2_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .out ( direct_interc_2_out ) ) ; +direct_interc_3 direct_interc_3_ ( + .in ( grid_clb_1_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_3_out ) ) ; +direct_interc_4 direct_interc_4_ ( + .in ( grid_clb_3_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_4_out ) ) ; +direct_interc_5 direct_interc_5_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .out ( direct_interc_5_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7749 ( + .A ( grid_io_left_0_ccff_tail[0] ) , .X ( ropt_net_31 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7750 ( .A ( ropt_net_31 ) , + .X ( ropt_net_32 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7751 ( .A ( ropt_net_32 ) , + .X ( ropt_net_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_9 ( .A ( Test_en[0] ) , + .X ( BUF_net_9 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7752 ( + .A ( grid_io_top_1_ccff_tail[0] ) , .X ( ropt_net_34 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73507625 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_110 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73517626 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_211 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73527627 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_312 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73537628 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_413 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73547629 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_514 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73557630 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_615 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73567631 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_716 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73577632 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_817 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73587633 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_918 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73597634 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1019 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7753 ( .A ( ropt_net_34 ) , + .X ( ropt_net_35 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73617636 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1221 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73627637 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1322 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7754 ( .A ( ropt_net_35 ) , + .X ( ropt_net_36 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73647639 ( .A ( ctsbuf_net_2130 ) , + .Y ( ctsbuf_net_1524 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73657640 ( .A ( ctsbuf_net_2029 ) , + .Y ( ctsbuf_net_1625 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7755 ( + .A ( grid_io_top_0_ccff_tail[0] ) , .X ( ropt_net_37 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73677642 ( .A ( ctsbuf_net_1928 ) , + .Y ( ctsbuf_net_1827 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_73667641_73687643 ( + .A ( SYNOPSYS_UNCONNECTED_1 ) , .Y ( SYNOPSYS_UNCONNECTED_2 ) ) ; +sky130_fd_sc_hd__bufinv_16 cts_inv_73607635_73697644 ( + .A ( SYNOPSYS_UNCONNECTED_3 ) , .Y ( SYNOPSYS_UNCONNECTED_4 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7756 ( .A ( ropt_net_37 ) , + .X ( ropt_net_38 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73827657 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_1928 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73837658 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2029 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_73847659 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_7757 ( + .A ( grid_io_left_1_ccff_tail[0] ) , .X ( ropt_net_39 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_7758 ( .A ( ropt_net_39 ) , + .X ( ropt_net_40 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds 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@@ -0,0 +1,2066 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 104.88 BY 76.16 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 90.55 74.8 90.69 76.16 ; + END + END prog_clk[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 74.8 3.29 76.16 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.41 1.38 28.71 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.33 1.38 24.63 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[19] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 27.05 104.88 27.35 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 64.45 104.88 64.75 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 15.49 104.88 15.79 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 59.69 104.88 59.99 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 11.41 104.88 11.71 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 61.05 104.88 61.35 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 25.69 104.88 25.99 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 48.81 104.88 49.11 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 21.61 104.88 21.91 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 33.85 104.88 34.15 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 20.25 104.88 20.55 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 37.93 104.88 38.23 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 22.97 104.88 23.27 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 65.81 104.88 66.11 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 17.53 104.88 17.83 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 39.29 104.88 39.59 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 31.13 104.88 31.43 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 43.37 104.88 43.67 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 10.05 104.88 10.35 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 58.33 104.88 58.63 ; + END + END chanx_right_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 55.61 104.88 55.91 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 12.09 1.38 12.39 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 8.01 1.38 8.31 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 9.37 1.38 9.67 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.81 1.38 15.11 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.69 1.38 25.99 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.77 1.38 30.07 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 3.93 1.38 4.23 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 63.77 1.38 64.07 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.67 74.8 100.81 76.16 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 54.25 104.88 54.55 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 100.13 74.8 100.43 76.16 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 52.89 104.88 53.19 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 74.8 102.65 76.16 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 50.17 104.88 50.47 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 47.45 104.88 47.75 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 70.57 104.88 70.87 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 32.49 104.88 32.79 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 71.93 104.88 72.23 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.59 74.8 101.73 76.16 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 69.21 104.88 69.51 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 36.57 104.88 36.87 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 44.73 104.88 45.03 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 6.65 104.88 6.95 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 42.01 104.88 42.31 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 28.41 104.88 28.71 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 0 102.65 1.36 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 5.29 104.88 5.59 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 3.93 104.88 4.23 ; + END + END chanx_right_out[19] + PIN top_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.97 74.8 34.11 76.16 ; + END + END top_grid_pin_16_[0] + PIN top_grid_pin_17_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 74.8 35.95 76.16 ; + END + END top_grid_pin_17_[0] + PIN top_grid_pin_18_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.89 74.8 35.03 76.16 ; + END + END top_grid_pin_18_[0] + PIN top_grid_pin_19_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.73 74.8 36.87 76.16 ; + END + END top_grid_pin_19_[0] + PIN top_grid_pin_20_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 74.8 57.57 76.16 ; + END + END top_grid_pin_20_[0] + PIN top_grid_pin_21_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.03 74.8 16.17 76.16 ; + END + END top_grid_pin_21_[0] + PIN top_grid_pin_22_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.05 74.8 33.19 76.16 ; + END + END top_grid_pin_22_[0] + PIN top_grid_pin_23_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.11 74.8 15.25 76.16 ; + END + END top_grid_pin_23_[0] + PIN top_grid_pin_24_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 74.8 2.37 76.16 ; + END + END top_grid_pin_24_[0] + PIN top_grid_pin_25_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.35 74.8 12.49 76.16 ; + END + END top_grid_pin_25_[0] + PIN top_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.27 74.8 13.41 76.16 ; + END + END top_grid_pin_26_[0] + PIN top_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.19 74.8 14.33 76.16 ; + END + END top_grid_pin_27_[0] + PIN top_grid_pin_28_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.53 74.8 73.67 76.16 ; + END + END top_grid_pin_28_[0] + PIN top_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.45 74.8 74.59 76.16 ; + END + END top_grid_pin_29_[0] + PIN top_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.29 74.8 76.43 76.16 ; + END + END top_grid_pin_30_[0] + PIN top_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.37 74.8 75.51 76.16 ; + END + END top_grid_pin_31_[0] + PIN bottom_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 0 97.59 1.36 ; + END + END bottom_grid_pin_0_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 101.68 16.08 104.88 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 101.68 56.88 104.88 60.08 ; + LAYER met4 ; + RECT 15.34 0 15.94 0.6 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 103.66 0 104.26 0.6 ; + RECT 15.34 75.56 15.94 76.16 ; + RECT 44.78 75.56 45.38 76.16 ; + RECT 74.22 75.56 74.82 76.16 ; + RECT 103.66 75.56 104.26 76.16 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 104.4 2.48 104.88 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 104.4 7.92 104.88 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 104.4 13.36 104.88 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 104.4 18.8 104.88 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 104.4 24.24 104.88 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 104.4 29.68 104.88 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 104.4 35.12 104.88 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 104.4 40.56 104.88 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 104.4 46 104.88 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 104.4 51.44 104.88 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 104.4 56.88 104.88 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 104.4 62.32 104.88 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 104.4 67.76 104.88 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 104.4 73.2 104.88 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 101.68 36.48 104.88 39.68 ; + LAYER met4 ; + RECT 0.62 0 1.22 0.6 ; + RECT 30.06 0 30.66 0.6 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 0.62 75.56 1.22 76.16 ; + RECT 30.06 75.56 30.66 76.16 ; + RECT 59.5 75.56 60.1 76.16 ; + RECT 88.94 75.56 89.54 76.16 ; + LAYER met1 ; + RECT 0 0 104.88 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 104.4 5.2 104.88 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 104.4 10.64 104.88 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 104.4 16.08 104.88 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 104.4 21.52 104.88 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 104.4 26.96 104.88 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 104.4 32.4 104.88 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 104.4 37.84 104.88 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 104.4 43.28 104.88 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 104.4 48.72 104.88 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 104.4 54.16 104.88 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 104.4 59.6 104.88 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 104.4 65.04 104.88 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 104.4 70.48 104.88 70.96 ; + RECT 0 75.92 104.88 76.16 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 76.075 104.88 76.245 ; + RECT 103.04 73.355 104.88 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.96 70.635 104.88 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 103.96 67.915 104.88 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 103.96 65.195 104.88 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 103.96 62.475 104.88 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 103.96 59.755 104.88 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 103.96 57.035 104.88 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 103.96 54.315 104.88 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 103.96 51.595 104.88 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 103.96 48.875 104.88 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 103.96 46.155 104.88 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 103.96 43.435 104.88 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 103.96 40.715 104.88 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 103.96 37.995 104.88 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 103.96 35.275 104.88 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 103.96 32.555 104.88 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 103.96 29.835 104.88 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 101.2 27.115 104.88 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 101.2 24.395 104.88 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.04 21.675 104.88 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 104.42 18.955 104.88 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 101.2 16.235 104.88 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 101.2 13.515 104.88 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 103.96 10.795 104.88 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 103.96 8.075 104.88 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 103.96 5.355 104.88 5.525 ; + RECT 0 5.355 1.84 5.525 ; + RECT 103.04 2.635 104.88 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 104.88 0.085 ; + LAYER met2 ; + RECT 89.1 75.975 89.38 76.345 ; + RECT 59.66 75.975 59.94 76.345 ; + RECT 30.22 75.975 30.5 76.345 ; + RECT 0.78 75.975 1.06 76.345 ; + RECT 35.29 74.3 35.55 74.62 ; + RECT 89.1 -0.185 89.38 0.185 ; + RECT 59.66 -0.185 59.94 0.185 ; + RECT 30.22 -0.185 30.5 0.185 ; + RECT 0.78 -0.185 1.06 0.185 ; + POLYGON 104.6 75.88 104.6 0.28 102.93 0.28 102.93 1.64 102.23 1.64 102.23 0.28 97.87 0.28 97.87 1.64 97.17 1.64 97.17 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 12.07 75.88 12.07 74.52 12.77 74.52 12.77 75.88 12.99 75.88 12.99 74.52 13.69 74.52 13.69 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 34.61 75.88 34.61 74.52 35.31 74.52 35.31 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 73.25 75.88 73.25 74.52 73.95 74.52 73.95 75.88 74.17 75.88 74.17 74.52 74.87 74.52 74.87 75.88 75.09 75.88 75.09 74.52 75.79 74.52 75.79 75.88 76.01 75.88 76.01 74.52 76.71 74.52 76.71 75.88 90.27 75.88 90.27 74.52 90.97 74.52 90.97 75.88 100.39 75.88 100.39 74.52 101.09 74.52 101.09 75.88 101.31 75.88 101.31 74.52 102.01 74.52 102.01 75.88 102.23 75.88 102.23 74.52 102.93 74.52 102.93 75.88 ; + LAYER met3 ; + POLYGON 89.405 76.325 89.405 76.32 89.62 76.32 89.62 76 89.405 76 89.405 75.995 89.075 75.995 89.075 76 88.86 76 88.86 76.32 89.075 76.32 89.075 76.325 ; + POLYGON 59.965 76.325 59.965 76.32 60.18 76.32 60.18 76 59.965 76 59.965 75.995 59.635 75.995 59.635 76 59.42 76 59.42 76.32 59.635 76.32 59.635 76.325 ; + POLYGON 30.525 76.325 30.525 76.32 30.74 76.32 30.74 76 30.525 76 30.525 75.995 30.195 75.995 30.195 76 29.98 76 29.98 76.32 30.195 76.32 30.195 76.325 ; + POLYGON 1.085 76.325 1.085 76.32 1.3 76.32 1.3 76 1.085 76 1.085 75.995 0.755 75.995 0.755 76 0.54 76 0.54 76.32 0.755 76.32 0.755 76.325 ; + POLYGON 4.29 59.31 4.29 59.01 1.78 59.01 1.78 59.03 0.31 59.03 0.31 59.31 ; + POLYGON 103.65 26.67 103.65 26.39 103.1 26.39 103.1 26.37 58.27 26.37 58.27 26.67 ; + POLYGON 89.405 0.165 89.405 0.16 89.62 0.16 89.62 -0.16 89.405 -0.16 89.405 -0.165 89.075 -0.165 89.075 -0.16 88.86 -0.16 88.86 0.16 89.075 0.16 89.075 0.165 ; + POLYGON 59.965 0.165 59.965 0.16 60.18 0.16 60.18 -0.16 59.965 -0.16 59.965 -0.165 59.635 -0.165 59.635 -0.16 59.42 -0.16 59.42 0.16 59.635 0.16 59.635 0.165 ; + POLYGON 30.525 0.165 30.525 0.16 30.74 0.16 30.74 -0.16 30.525 -0.16 30.525 -0.165 30.195 -0.165 30.195 -0.16 29.98 -0.16 29.98 0.16 30.195 0.16 30.195 0.165 ; + POLYGON 1.085 0.165 1.085 0.16 1.3 0.16 1.3 -0.16 1.085 -0.16 1.085 -0.165 0.755 -0.165 0.755 -0.16 0.54 -0.16 0.54 0.16 0.755 0.16 0.755 0.165 ; + POLYGON 104.48 75.76 104.48 72.63 103.1 72.63 103.1 71.53 104.48 71.53 104.48 71.27 103.1 71.27 103.1 70.17 104.48 70.17 104.48 69.91 103.1 69.91 103.1 68.81 104.48 68.81 104.48 66.51 103.1 66.51 103.1 65.41 104.48 65.41 104.48 65.15 103.1 65.15 103.1 64.05 104.48 64.05 104.48 61.75 103.1 61.75 103.1 60.65 104.48 60.65 104.48 60.39 103.1 60.39 103.1 59.29 104.48 59.29 104.48 59.03 103.1 59.03 103.1 57.93 104.48 57.93 104.48 56.31 103.1 56.31 103.1 55.21 104.48 55.21 104.48 54.95 103.1 54.95 103.1 53.85 104.48 53.85 104.48 53.59 103.1 53.59 103.1 52.49 104.48 52.49 104.48 50.87 103.1 50.87 103.1 49.77 104.48 49.77 104.48 49.51 103.1 49.51 103.1 48.41 104.48 48.41 104.48 48.15 103.1 48.15 103.1 47.05 104.48 47.05 104.48 45.43 103.1 45.43 103.1 44.33 104.48 44.33 104.48 44.07 103.1 44.07 103.1 42.97 104.48 42.97 104.48 42.71 103.1 42.71 103.1 41.61 104.48 41.61 104.48 39.99 103.1 39.99 103.1 38.89 104.48 38.89 104.48 38.63 103.1 38.63 103.1 37.53 104.48 37.53 104.48 37.27 103.1 37.27 103.1 36.17 104.48 36.17 104.48 34.55 103.1 34.55 103.1 33.45 104.48 33.45 104.48 33.19 103.1 33.19 103.1 32.09 104.48 32.09 104.48 31.83 103.1 31.83 103.1 30.73 104.48 30.73 104.48 29.11 103.1 29.11 103.1 28.01 104.48 28.01 104.48 27.75 103.1 27.75 103.1 26.65 104.48 26.65 104.48 26.39 103.1 26.39 103.1 25.29 104.48 25.29 104.48 23.67 103.1 23.67 103.1 22.57 104.48 22.57 104.48 22.31 103.1 22.31 103.1 21.21 104.48 21.21 104.48 20.95 103.1 20.95 103.1 19.85 104.48 19.85 104.48 18.23 103.1 18.23 103.1 17.13 104.48 17.13 104.48 16.19 103.1 16.19 103.1 15.09 104.48 15.09 104.48 12.11 103.1 12.11 103.1 11.01 104.48 11.01 104.48 10.75 103.1 10.75 103.1 9.65 104.48 9.65 104.48 7.35 103.1 7.35 103.1 6.25 104.48 6.25 104.48 5.99 103.1 5.99 103.1 4.89 104.48 4.89 104.48 4.63 103.1 4.63 103.1 3.53 104.48 3.53 104.48 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 75.76 ; + LAYER met4 ; + POLYGON 104.26 75.16 104.26 59.87 104.55 59.87 104.55 57.09 104.26 57.09 104.26 19.07 104.55 19.07 104.55 16.29 104.26 16.29 104.26 1 103.66 1 103.66 16.29 103.37 16.29 103.37 19.07 103.66 19.07 103.66 57.09 103.37 57.09 103.37 59.87 103.66 59.87 103.66 75.16 ; + POLYGON 1.22 75.16 1.22 39.47 1.51 39.47 1.51 36.69 1.22 36.69 1.22 1 0.62 1 0.62 36.69 0.33 36.69 0.33 39.47 0.62 39.47 0.62 75.16 ; + POLYGON 103.26 75.76 103.26 75.16 104.48 75.16 104.48 1 103.26 1 103.26 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 31.06 0.4 31.06 1 29.66 1 29.66 0.4 16.34 0.4 16.34 1 14.94 1 14.94 0.4 1.62 0.4 1.62 1 0.4 1 0.4 75.16 1.62 75.16 1.62 75.76 14.94 75.76 14.94 75.16 16.34 75.16 16.34 75.76 29.66 75.76 29.66 75.16 31.06 75.16 31.06 75.76 44.38 75.76 44.38 75.16 45.78 75.16 45.78 75.76 59.1 75.76 59.1 75.16 60.5 75.16 60.5 75.76 73.82 75.76 73.82 75.16 75.22 75.16 75.22 75.76 88.54 75.76 88.54 75.16 89.94 75.16 89.94 75.76 99.73 75.76 99.73 74.4 100.83 74.4 100.83 75.76 ; + LAYER met1 ; + POLYGON 104.6 75.64 104.6 73.96 104.12 73.96 104.12 72.92 104.6 72.92 104.6 71.24 104.12 71.24 104.12 70.2 104.6 70.2 104.6 68.52 104.12 68.52 104.12 67.48 104.6 67.48 104.6 65.8 104.12 65.8 104.12 64.76 104.6 64.76 104.6 63.08 104.12 63.08 104.12 62.04 104.6 62.04 104.6 60.36 104.12 60.36 104.12 59.32 104.6 59.32 104.6 57.64 104.12 57.64 104.12 56.6 104.6 56.6 104.6 54.92 104.12 54.92 104.12 53.88 104.6 53.88 104.6 52.2 104.12 52.2 104.12 51.16 104.6 51.16 104.6 49.48 104.12 49.48 104.12 48.44 104.6 48.44 104.6 46.76 104.12 46.76 104.12 45.72 104.6 45.72 104.6 44.04 104.12 44.04 104.12 43 104.6 43 104.6 41.32 104.12 41.32 104.12 40.28 104.6 40.28 104.6 38.6 104.12 38.6 104.12 37.56 104.6 37.56 104.6 35.88 104.12 35.88 104.12 34.84 104.6 34.84 104.6 33.16 104.12 33.16 104.12 32.12 104.6 32.12 104.6 30.44 104.12 30.44 104.12 29.4 104.6 29.4 104.6 27.72 104.12 27.72 104.12 26.68 104.6 26.68 104.6 25 104.12 25 104.12 23.96 104.6 23.96 104.6 22.28 104.12 22.28 104.12 21.24 104.6 21.24 104.6 19.56 104.12 19.56 104.12 18.52 104.6 18.52 104.6 16.84 104.12 16.84 104.12 15.8 104.6 15.8 104.6 14.12 104.12 14.12 104.12 13.08 104.6 13.08 104.6 11.4 104.12 11.4 104.12 10.36 104.6 10.36 104.6 8.68 104.12 8.68 104.12 7.64 104.6 7.64 104.6 5.96 104.12 5.96 104.12 4.92 104.6 4.92 104.6 3.24 104.12 3.24 104.12 2.2 104.6 2.2 104.6 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER met5 ; + POLYGON 101.68 72.96 101.68 63.28 98.48 63.28 98.48 53.68 101.68 53.68 101.68 42.88 98.48 42.88 98.48 33.28 101.68 33.28 101.68 22.48 98.48 22.48 98.48 12.88 101.68 12.88 101.68 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 ; + LAYER li1 ; + RECT 0.34 0.34 104.54 75.82 ; + LAYER mcon ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 104.565 73.355 104.735 73.525 ; + RECT 104.105 73.355 104.275 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 104.565 70.635 104.735 70.805 ; + RECT 104.105 70.635 104.275 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 104.565 67.915 104.735 68.085 ; + RECT 104.105 67.915 104.275 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 104.565 65.195 104.735 65.365 ; + RECT 104.105 65.195 104.275 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 104.565 62.475 104.735 62.645 ; + RECT 104.105 62.475 104.275 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 104.565 59.755 104.735 59.925 ; + RECT 104.105 59.755 104.275 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 104.565 57.035 104.735 57.205 ; + RECT 104.105 57.035 104.275 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 104.565 54.315 104.735 54.485 ; + RECT 104.105 54.315 104.275 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 104.565 51.595 104.735 51.765 ; + RECT 104.105 51.595 104.275 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 104.565 48.875 104.735 49.045 ; + RECT 104.105 48.875 104.275 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 104.565 46.155 104.735 46.325 ; + RECT 104.105 46.155 104.275 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 104.565 43.435 104.735 43.605 ; + RECT 104.105 43.435 104.275 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 104.565 40.715 104.735 40.885 ; + RECT 104.105 40.715 104.275 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 104.565 37.995 104.735 38.165 ; + RECT 104.105 37.995 104.275 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 104.565 35.275 104.735 35.445 ; + RECT 104.105 35.275 104.275 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 104.565 32.555 104.735 32.725 ; + RECT 104.105 32.555 104.275 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 104.565 29.835 104.735 30.005 ; + RECT 104.105 29.835 104.275 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 104.565 24.395 104.735 24.565 ; + RECT 104.105 24.395 104.275 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 104.565 21.675 104.735 21.845 ; + RECT 104.105 21.675 104.275 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 104.565 18.955 104.735 19.125 ; + RECT 104.105 18.955 104.275 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 104.565 16.235 104.735 16.405 ; + RECT 104.105 16.235 104.275 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 104.565 13.515 104.735 13.685 ; + RECT 104.105 13.515 104.275 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 104.565 10.795 104.735 10.965 ; + RECT 104.105 10.795 104.275 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 104.565 8.075 104.735 8.245 ; + RECT 104.105 8.075 104.275 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 104.565 5.355 104.735 5.525 ; + RECT 104.105 5.355 104.275 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 104.565 2.635 104.735 2.805 ; + RECT 104.105 2.635 104.275 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 89.165 76.085 89.315 76.235 ; + RECT 59.725 76.085 59.875 76.235 ; + RECT 30.285 76.085 30.435 76.235 ; + RECT 0.845 76.085 0.995 76.235 ; + RECT 102.505 1.625 102.655 1.775 ; + RECT 57.425 1.625 57.575 1.775 ; + RECT 89.165 -0.075 89.315 0.075 ; + RECT 59.725 -0.075 59.875 0.075 ; + RECT 30.285 -0.075 30.435 0.075 ; + RECT 0.845 -0.075 0.995 0.075 ; + LAYER via2 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 103.4 47.5 103.6 47.7 ; + RECT 1.28 47.5 1.48 47.7 ; + RECT 1.28 42.06 1.48 42.26 ; + RECT 1.28 31.18 1.48 31.38 ; + RECT 1.28 18.94 1.48 19.14 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via3 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 1.74 44.78 1.94 44.98 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via4 ; + RECT 103.56 58.88 104.36 59.68 ; + RECT 103.56 57.28 104.36 58.08 ; + RECT 0.52 38.48 1.32 39.28 ; + RECT 0.52 36.88 1.32 37.68 ; + RECT 103.56 18.08 104.36 18.88 ; + RECT 103.56 16.48 104.36 17.28 ; + LAYER fieldpoly ; + RECT 0.14 0.14 104.74 76.02 ; + LAYER diff ; + RECT 0 0 104.88 76.16 ; + LAYER nwell ; + POLYGON 105.07 74.855 105.07 72.025 103.77 72.025 103.77 73.25 102.85 73.25 102.85 74.855 ; + POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; + RECT 103.77 66.585 105.07 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + RECT 103.77 61.145 105.07 63.975 ; + RECT -0.19 61.145 2.03 63.975 ; + RECT 103.77 55.705 105.07 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 103.77 50.265 105.07 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + RECT 103.77 44.825 105.07 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 103.77 39.385 105.07 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + RECT 103.77 33.945 105.07 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + RECT 103.77 28.505 105.07 31.335 ; + RECT -0.19 28.505 2.03 31.335 ; + POLYGON 105.07 25.895 105.07 23.065 102.85 23.065 102.85 24.29 101.01 24.29 101.01 25.895 ; + RECT -0.19 23.065 2.03 25.895 ; + RECT 104.23 17.625 105.07 20.455 ; + RECT -0.19 17.625 2.03 20.455 ; + POLYGON 105.07 15.015 105.07 12.185 103.77 12.185 103.77 13.41 101.01 13.41 101.01 15.015 ; + RECT -0.19 12.185 2.03 15.015 ; + RECT 103.77 6.745 105.07 9.575 ; + RECT -0.19 6.745 2.03 9.575 ; + POLYGON 105.07 4.135 105.07 1.305 102.85 1.305 102.85 2.91 103.77 2.91 103.77 4.135 ; + POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; + RECT 0 0 104.88 76.16 ; + LAYER pwell ; + RECT 99.49 76.11 99.71 76.28 ; + RECT 95.81 76.11 96.03 76.28 ; + RECT 92.13 76.11 92.35 76.28 ; + RECT 88.45 76.11 88.67 76.28 ; + RECT 84.77 76.11 84.99 76.28 ; + RECT 81.09 76.11 81.31 76.28 ; + RECT 77.41 76.11 77.63 76.28 ; + RECT 73.73 76.11 73.95 76.28 ; + RECT 70.05 76.11 70.27 76.28 ; + RECT 66.37 76.11 66.59 76.28 ; + RECT 62.69 76.11 62.91 76.28 ; + RECT 59.01 76.11 59.23 76.28 ; + RECT 55.33 76.11 55.55 76.28 ; + RECT 51.65 76.11 51.87 76.28 ; + RECT 47.97 76.11 48.19 76.28 ; + RECT 44.29 76.11 44.51 76.28 ; + RECT 40.61 76.11 40.83 76.28 ; + RECT 36.93 76.11 37.15 76.28 ; + RECT 33.25 76.11 33.47 76.28 ; + RECT 29.57 76.11 29.79 76.28 ; + RECT 25.89 76.11 26.11 76.28 ; + RECT 22.21 76.11 22.43 76.28 ; + RECT 18.53 76.11 18.75 76.28 ; + RECT 14.85 76.11 15.07 76.28 ; + RECT 11.17 76.11 11.39 76.28 ; + RECT 7.49 76.11 7.71 76.28 ; + RECT 3.81 76.11 4.03 76.28 ; + RECT 0.13 76.11 0.35 76.28 ; + RECT 103.215 76.1 103.325 76.22 ; + RECT 103.215 -0.06 103.325 0.06 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + RECT 0 0 104.88 76.16 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 104.88 76.16 104.88 0 ; + END +END cbx_1__0_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef new file mode 100644 index 0000000..2b184ad --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -0,0 +1,2060 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 104.88 BY 76.16 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 0 3.29 1.36 ; + END + END prog_clk[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.77 1.38 47.07 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 8.01 1.38 8.31 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.81 1.38 15.11 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.01 1.38 25.31 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END chanx_left_in[19] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 33.85 104.88 34.15 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 54.25 104.88 54.55 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 55.61 104.88 55.91 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 47.45 104.88 47.75 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 52.89 104.88 53.19 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 20.25 104.88 20.55 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 22.97 104.88 23.27 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 38.61 104.88 38.91 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 21.61 104.88 21.91 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 42.01 104.88 42.31 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 25.69 104.88 25.99 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 69.21 104.88 69.51 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 17.53 104.88 17.83 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 71.93 104.88 72.23 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 27.05 104.88 27.35 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 0 102.65 1.36 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 4.61 104.88 4.91 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 61.05 104.88 61.35 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 43.37 104.88 43.67 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 63.77 104.88 64.07 ; + END + END chanx_right_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 37.25 104.88 37.55 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 4.45 0 4.75 1.36 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.41 1.38 28.71 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 0 4.67 1.36 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.65 1.38 23.95 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 9.37 1.38 9.67 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.45 0 5.59 1.36 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.37 0 6.51 1.36 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 63.77 1.38 64.07 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.77 1.38 30.07 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 12.09 1.38 12.39 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 74.8 3.29 76.16 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 3.93 1.38 4.23 ; + END + END chanx_left_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 48.81 104.88 49.11 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 10.73 104.88 11.03 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.67 0 100.81 1.36 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 12.09 104.88 12.39 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 58.33 104.88 58.63 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 59.69 104.88 59.99 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 6.65 104.88 6.95 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 14.81 104.88 15.11 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 16.17 104.88 16.47 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 44.73 104.88 45.03 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 31.81 104.88 32.11 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 9.37 104.88 9.67 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 70.57 104.88 70.87 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 66.49 104.88 66.79 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 65.13 104.88 65.43 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 50.17 104.88 50.47 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.59 0 101.73 1.36 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 28.41 104.88 28.71 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 74.8 102.65 76.16 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 100.13 0 100.43 1.36 ; + END + END chanx_right_out[19] + PIN top_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.97 74.8 34.11 76.16 ; + END + END top_grid_pin_16_[0] + PIN top_grid_pin_17_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 74.8 35.95 76.16 ; + END + END top_grid_pin_17_[0] + PIN top_grid_pin_18_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.89 74.8 35.03 76.16 ; + END + END top_grid_pin_18_[0] + PIN top_grid_pin_19_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.73 74.8 36.87 76.16 ; + END + END top_grid_pin_19_[0] + PIN top_grid_pin_20_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 74.8 57.57 76.16 ; + END + END top_grid_pin_20_[0] + PIN top_grid_pin_21_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.03 74.8 16.17 76.16 ; + END + END top_grid_pin_21_[0] + PIN top_grid_pin_22_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.05 74.8 33.19 76.16 ; + END + END top_grid_pin_22_[0] + PIN top_grid_pin_23_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.11 74.8 15.25 76.16 ; + END + END top_grid_pin_23_[0] + PIN top_grid_pin_24_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 74.8 2.37 76.16 ; + END + END top_grid_pin_24_[0] + PIN top_grid_pin_25_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.35 74.8 12.49 76.16 ; + END + END top_grid_pin_25_[0] + PIN top_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.27 74.8 13.41 76.16 ; + END + END top_grid_pin_26_[0] + PIN top_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.19 74.8 14.33 76.16 ; + END + END top_grid_pin_27_[0] + PIN top_grid_pin_28_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.53 74.8 73.67 76.16 ; + END + END top_grid_pin_28_[0] + PIN top_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.45 74.8 74.59 76.16 ; + END + END top_grid_pin_29_[0] + PIN top_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.29 74.8 76.43 76.16 ; + END + END top_grid_pin_30_[0] + PIN top_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.37 74.8 75.51 76.16 ; + END + END top_grid_pin_31_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 15.34 0 15.94 0.6 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 103.66 0 104.26 0.6 ; + RECT 15.34 75.56 15.94 76.16 ; + RECT 44.78 75.56 45.38 76.16 ; + RECT 74.22 75.56 74.82 76.16 ; + RECT 103.66 75.56 104.26 76.16 ; + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 101.68 16.08 104.88 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 101.68 56.88 104.88 60.08 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 104.4 2.48 104.88 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 104.4 7.92 104.88 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 104.4 13.36 104.88 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 104.4 18.8 104.88 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 104.4 24.24 104.88 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 104.4 29.68 104.88 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 104.4 35.12 104.88 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 104.4 40.56 104.88 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 104.4 46 104.88 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 104.4 51.44 104.88 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 104.4 56.88 104.88 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 104.4 62.32 104.88 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 104.4 67.76 104.88 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 104.4 73.2 104.88 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 0.62 0 1.22 0.6 ; + RECT 30.06 0 30.66 0.6 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 0.62 75.56 1.22 76.16 ; + RECT 30.06 75.56 30.66 76.16 ; + RECT 59.5 75.56 60.1 76.16 ; + RECT 88.94 75.56 89.54 76.16 ; + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 101.68 36.48 104.88 39.68 ; + LAYER met1 ; + RECT 0 0 104.88 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 104.4 5.2 104.88 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 104.4 10.64 104.88 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 104.4 16.08 104.88 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 104.4 21.52 104.88 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 104.4 26.96 104.88 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 104.4 32.4 104.88 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 104.4 37.84 104.88 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 104.4 43.28 104.88 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 104.4 48.72 104.88 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 104.4 54.16 104.88 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 104.4 59.6 104.88 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 104.4 65.04 104.88 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 104.4 70.48 104.88 70.96 ; + RECT 0 75.92 104.88 76.16 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 76.075 104.88 76.245 ; + RECT 103.04 73.355 104.88 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.96 70.635 104.88 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 103.96 67.915 104.88 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 103.96 65.195 104.88 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 103.96 62.475 104.88 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 103.96 59.755 104.88 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 103.96 57.035 104.88 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 103.96 54.315 104.88 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 103.96 51.595 104.88 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 103.96 48.875 104.88 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 103.96 46.155 104.88 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 103.96 43.435 104.88 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 103.96 40.715 104.88 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 103.96 37.995 104.88 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 103.96 35.275 104.88 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 104.42 32.555 104.88 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 103.96 29.835 104.88 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 103.96 27.115 104.88 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 103.04 24.395 104.88 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.04 21.675 104.88 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 103.96 18.955 104.88 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 103.96 16.235 104.88 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 103.96 13.515 104.88 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 103.96 10.795 104.88 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 103.96 8.075 104.88 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 103.96 5.355 104.88 5.525 ; + RECT 0 5.355 1.84 5.525 ; + RECT 103.04 2.635 104.88 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 104.88 0.085 ; + LAYER met2 ; + RECT 89.1 75.975 89.38 76.345 ; + RECT 59.66 75.975 59.94 76.345 ; + RECT 30.22 75.975 30.5 76.345 ; + RECT 0.78 75.975 1.06 76.345 ; + RECT 89.1 -0.185 89.38 0.185 ; + RECT 59.66 -0.185 59.94 0.185 ; + RECT 30.22 -0.185 30.5 0.185 ; + RECT 0.78 -0.185 1.06 0.185 ; + POLYGON 104.6 75.88 104.6 0.28 102.93 0.28 102.93 1.64 102.23 1.64 102.23 0.28 102.01 0.28 102.01 1.64 101.31 1.64 101.31 0.28 101.09 0.28 101.09 1.64 100.39 1.64 100.39 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 12.07 75.88 12.07 74.52 12.77 74.52 12.77 75.88 12.99 75.88 12.99 74.52 13.69 74.52 13.69 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 34.61 75.88 34.61 74.52 35.31 74.52 35.31 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 73.25 75.88 73.25 74.52 73.95 74.52 73.95 75.88 74.17 75.88 74.17 74.52 74.87 74.52 74.87 75.88 75.09 75.88 75.09 74.52 75.79 74.52 75.79 75.88 76.01 75.88 76.01 74.52 76.71 74.52 76.71 75.88 102.23 75.88 102.23 74.52 102.93 74.52 102.93 75.88 ; + LAYER met3 ; + POLYGON 89.405 76.325 89.405 76.32 89.62 76.32 89.62 76 89.405 76 89.405 75.995 89.075 75.995 89.075 76 88.86 76 88.86 76.32 89.075 76.32 89.075 76.325 ; + POLYGON 59.965 76.325 59.965 76.32 60.18 76.32 60.18 76 59.965 76 59.965 75.995 59.635 75.995 59.635 76 59.42 76 59.42 76.32 59.635 76.32 59.635 76.325 ; + POLYGON 30.525 76.325 30.525 76.32 30.74 76.32 30.74 76 30.525 76 30.525 75.995 30.195 75.995 30.195 76 29.98 76 29.98 76.32 30.195 76.32 30.195 76.325 ; + POLYGON 1.085 76.325 1.085 76.32 1.3 76.32 1.3 76 1.085 76 1.085 75.995 0.755 75.995 0.755 76 0.54 76 0.54 76.32 0.755 76.32 0.755 76.325 ; + POLYGON 2.91 68.83 2.91 68.53 1.23 68.53 1.23 68.81 1.78 68.81 1.78 68.83 ; + POLYGON 103.1 66.79 103.1 66.09 103.19 66.09 103.19 65.81 100.13 65.81 100.13 66.11 102.89 66.11 102.89 66.79 ; + POLYGON 8.89 7.63 8.89 7.33 1.99 7.33 1.99 6.65 1.78 6.65 1.78 7.35 1.69 7.35 1.69 7.63 ; + POLYGON 89.405 0.165 89.405 0.16 89.62 0.16 89.62 -0.16 89.405 -0.16 89.405 -0.165 89.075 -0.165 89.075 -0.16 88.86 -0.16 88.86 0.16 89.075 0.16 89.075 0.165 ; + POLYGON 59.965 0.165 59.965 0.16 60.18 0.16 60.18 -0.16 59.965 -0.16 59.965 -0.165 59.635 -0.165 59.635 -0.16 59.42 -0.16 59.42 0.16 59.635 0.16 59.635 0.165 ; + POLYGON 30.525 0.165 30.525 0.16 30.74 0.16 30.74 -0.16 30.525 -0.16 30.525 -0.165 30.195 -0.165 30.195 -0.16 29.98 -0.16 29.98 0.16 30.195 0.16 30.195 0.165 ; + POLYGON 1.085 0.165 1.085 0.16 1.3 0.16 1.3 -0.16 1.085 -0.16 1.085 -0.165 0.755 -0.165 0.755 -0.16 0.54 -0.16 0.54 0.16 0.755 0.16 0.755 0.165 ; + POLYGON 104.48 75.76 104.48 72.63 103.1 72.63 103.1 71.53 104.48 71.53 104.48 71.27 103.1 71.27 103.1 70.17 104.48 70.17 104.48 69.91 103.1 69.91 103.1 68.81 104.48 68.81 104.48 67.19 103.1 67.19 103.1 66.09 104.48 66.09 104.48 65.83 103.1 65.83 103.1 64.73 104.48 64.73 104.48 64.47 103.1 64.47 103.1 63.37 104.48 63.37 104.48 61.75 103.1 61.75 103.1 60.65 104.48 60.65 104.48 60.39 103.1 60.39 103.1 59.29 104.48 59.29 104.48 59.03 103.1 59.03 103.1 57.93 104.48 57.93 104.48 56.31 103.1 56.31 103.1 55.21 104.48 55.21 104.48 54.95 103.1 54.95 103.1 53.85 104.48 53.85 104.48 53.59 103.1 53.59 103.1 52.49 104.48 52.49 104.48 50.87 103.1 50.87 103.1 49.77 104.48 49.77 104.48 49.51 103.1 49.51 103.1 48.41 104.48 48.41 104.48 48.15 103.1 48.15 103.1 47.05 104.48 47.05 104.48 45.43 103.1 45.43 103.1 44.33 104.48 44.33 104.48 44.07 103.1 44.07 103.1 42.97 104.48 42.97 104.48 42.71 103.1 42.71 103.1 41.61 104.48 41.61 104.48 39.31 103.1 39.31 103.1 38.21 104.48 38.21 104.48 37.95 103.1 37.95 103.1 36.85 104.48 36.85 104.48 34.55 103.1 34.55 103.1 33.45 104.48 33.45 104.48 32.51 103.1 32.51 103.1 31.41 104.48 31.41 104.48 29.11 103.1 29.11 103.1 28.01 104.48 28.01 104.48 27.75 103.1 27.75 103.1 26.65 104.48 26.65 104.48 26.39 103.1 26.39 103.1 25.29 104.48 25.29 104.48 23.67 103.1 23.67 103.1 22.57 104.48 22.57 104.48 22.31 103.1 22.31 103.1 21.21 104.48 21.21 104.48 20.95 103.1 20.95 103.1 19.85 104.48 19.85 104.48 18.23 103.1 18.23 103.1 17.13 104.48 17.13 104.48 16.87 103.1 16.87 103.1 15.77 104.48 15.77 104.48 15.51 103.1 15.51 103.1 14.41 104.48 14.41 104.48 12.79 103.1 12.79 103.1 11.69 104.48 11.69 104.48 11.43 103.1 11.43 103.1 10.33 104.48 10.33 104.48 10.07 103.1 10.07 103.1 8.97 104.48 8.97 104.48 7.35 103.1 7.35 103.1 6.25 104.48 6.25 104.48 5.31 103.1 5.31 103.1 4.21 104.48 4.21 104.48 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 75.76 ; + LAYER met4 ; + POLYGON 104.26 75.16 104.26 59.87 104.55 59.87 104.55 57.09 104.26 57.09 104.26 19.07 104.55 19.07 104.55 16.29 104.26 16.29 104.26 1 103.66 1 103.66 16.29 103.37 16.29 103.37 19.07 103.66 19.07 103.66 57.09 103.37 57.09 103.37 59.87 103.66 59.87 103.66 75.16 ; + POLYGON 1.22 75.16 1.22 39.47 1.51 39.47 1.51 36.69 1.22 36.69 1.22 1 0.62 1 0.62 36.69 0.33 36.69 0.33 39.47 0.62 39.47 0.62 75.16 ; + POLYGON 103.26 75.76 103.26 75.16 104.48 75.16 104.48 1 103.26 1 103.26 0.4 100.83 0.4 100.83 1.76 99.73 1.76 99.73 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 31.06 0.4 31.06 1 29.66 1 29.66 0.4 16.34 0.4 16.34 1 14.94 1 14.94 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 1.62 0.4 1.62 1 0.4 1 0.4 75.16 1.62 75.16 1.62 75.76 14.94 75.76 14.94 75.16 16.34 75.16 16.34 75.76 29.66 75.76 29.66 75.16 31.06 75.16 31.06 75.76 44.38 75.76 44.38 75.16 45.78 75.16 45.78 75.76 59.1 75.76 59.1 75.16 60.5 75.16 60.5 75.76 73.82 75.76 73.82 75.16 75.22 75.16 75.22 75.76 88.54 75.76 88.54 75.16 89.94 75.16 89.94 75.76 ; + LAYER met1 ; + POLYGON 104.6 75.64 104.6 73.96 104.12 73.96 104.12 72.92 104.6 72.92 104.6 71.24 104.12 71.24 104.12 70.2 104.6 70.2 104.6 68.52 104.12 68.52 104.12 67.48 104.6 67.48 104.6 65.8 104.12 65.8 104.12 64.76 104.6 64.76 104.6 63.08 104.12 63.08 104.12 62.04 104.6 62.04 104.6 60.36 104.12 60.36 104.12 59.32 104.6 59.32 104.6 57.64 104.12 57.64 104.12 56.6 104.6 56.6 104.6 54.92 104.12 54.92 104.12 53.88 104.6 53.88 104.6 52.2 104.12 52.2 104.12 51.16 104.6 51.16 104.6 49.48 104.12 49.48 104.12 48.44 104.6 48.44 104.6 46.76 104.12 46.76 104.12 45.72 104.6 45.72 104.6 44.04 104.12 44.04 104.12 43 104.6 43 104.6 41.32 104.12 41.32 104.12 40.28 104.6 40.28 104.6 38.6 104.12 38.6 104.12 37.56 104.6 37.56 104.6 35.88 104.12 35.88 104.12 34.84 104.6 34.84 104.6 33.16 104.12 33.16 104.12 32.12 104.6 32.12 104.6 30.44 104.12 30.44 104.12 29.4 104.6 29.4 104.6 27.72 104.12 27.72 104.12 26.68 104.6 26.68 104.6 25 104.12 25 104.12 23.96 104.6 23.96 104.6 22.28 104.12 22.28 104.12 21.24 104.6 21.24 104.6 19.56 104.12 19.56 104.12 18.52 104.6 18.52 104.6 16.84 104.12 16.84 104.12 15.8 104.6 15.8 104.6 14.12 104.12 14.12 104.12 13.08 104.6 13.08 104.6 11.4 104.12 11.4 104.12 10.36 104.6 10.36 104.6 8.68 104.12 8.68 104.12 7.64 104.6 7.64 104.6 5.96 104.12 5.96 104.12 4.92 104.6 4.92 104.6 3.24 104.12 3.24 104.12 2.2 104.6 2.2 104.6 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER met5 ; + POLYGON 101.68 72.96 101.68 63.28 98.48 63.28 98.48 53.68 101.68 53.68 101.68 42.88 98.48 42.88 98.48 33.28 101.68 33.28 101.68 22.48 98.48 22.48 98.48 12.88 101.68 12.88 101.68 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 ; + LAYER li1 ; + RECT 0.34 0.34 104.54 75.82 ; + LAYER mcon ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 104.565 73.355 104.735 73.525 ; + RECT 104.105 73.355 104.275 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 104.565 70.635 104.735 70.805 ; + RECT 104.105 70.635 104.275 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 104.565 67.915 104.735 68.085 ; + RECT 104.105 67.915 104.275 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 104.565 65.195 104.735 65.365 ; + RECT 104.105 65.195 104.275 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 104.565 62.475 104.735 62.645 ; + RECT 104.105 62.475 104.275 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 104.565 59.755 104.735 59.925 ; + RECT 104.105 59.755 104.275 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 104.565 57.035 104.735 57.205 ; + RECT 104.105 57.035 104.275 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 104.565 54.315 104.735 54.485 ; + RECT 104.105 54.315 104.275 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 104.565 51.595 104.735 51.765 ; + RECT 104.105 51.595 104.275 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 104.565 48.875 104.735 49.045 ; + RECT 104.105 48.875 104.275 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 104.565 46.155 104.735 46.325 ; + RECT 104.105 46.155 104.275 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 104.565 43.435 104.735 43.605 ; + RECT 104.105 43.435 104.275 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 104.565 40.715 104.735 40.885 ; + RECT 104.105 40.715 104.275 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 104.565 37.995 104.735 38.165 ; + RECT 104.105 37.995 104.275 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 104.565 35.275 104.735 35.445 ; + RECT 104.105 35.275 104.275 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 104.565 32.555 104.735 32.725 ; + RECT 104.105 32.555 104.275 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 104.565 29.835 104.735 30.005 ; + RECT 104.105 29.835 104.275 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 104.565 24.395 104.735 24.565 ; + RECT 104.105 24.395 104.275 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 104.565 21.675 104.735 21.845 ; + RECT 104.105 21.675 104.275 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 104.565 18.955 104.735 19.125 ; + RECT 104.105 18.955 104.275 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 104.565 16.235 104.735 16.405 ; + RECT 104.105 16.235 104.275 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 104.565 13.515 104.735 13.685 ; + RECT 104.105 13.515 104.275 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 104.565 10.795 104.735 10.965 ; + RECT 104.105 10.795 104.275 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 104.565 8.075 104.735 8.245 ; + RECT 104.105 8.075 104.275 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 104.565 5.355 104.735 5.525 ; + RECT 104.105 5.355 104.275 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 104.565 2.635 104.735 2.805 ; + RECT 104.105 2.635 104.275 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 89.165 76.085 89.315 76.235 ; + RECT 59.725 76.085 59.875 76.235 ; + RECT 30.285 76.085 30.435 76.235 ; + RECT 0.845 76.085 0.995 76.235 ; + RECT 16.025 74.385 16.175 74.535 ; + RECT 100.665 1.625 100.815 1.775 ; + RECT 89.165 -0.075 89.315 0.075 ; + RECT 59.725 -0.075 59.875 0.075 ; + RECT 30.285 -0.075 30.435 0.075 ; + RECT 0.845 -0.075 0.995 0.075 ; + LAYER via2 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 1.28 61.1 1.48 61.3 ; + RECT 103.4 59.74 103.6 59.94 ; + RECT 103.4 50.22 103.6 50.42 ; + RECT 1.28 17.58 1.48 17.78 ; + RECT 102.94 16.22 103.14 16.42 ; + RECT 1.74 12.14 1.94 12.34 ; + RECT 102.94 9.42 103.14 9.62 ; + RECT 103.4 6.7 103.6 6.9 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via3 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via4 ; + RECT 103.56 58.88 104.36 59.68 ; + RECT 103.56 57.28 104.36 58.08 ; + RECT 0.52 38.48 1.32 39.28 ; + RECT 0.52 36.88 1.32 37.68 ; + RECT 103.56 18.08 104.36 18.88 ; + RECT 103.56 16.48 104.36 17.28 ; + LAYER fieldpoly ; + RECT 0.14 0.14 104.74 76.02 ; + LAYER diff ; + RECT 0 0 104.88 76.16 ; + LAYER nwell ; + POLYGON 105.07 74.855 105.07 72.025 103.77 72.025 103.77 73.25 102.85 73.25 102.85 74.855 ; + POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; + RECT 103.77 66.585 105.07 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + RECT 103.77 61.145 105.07 63.975 ; + RECT -0.19 61.145 2.03 63.975 ; + RECT 103.77 55.705 105.07 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 103.77 50.265 105.07 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + RECT 103.77 44.825 105.07 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 103.77 39.385 105.07 42.215 ; + POLYGON 2.03 42.215 2.03 40.99 3.87 40.99 3.87 39.385 -0.19 39.385 -0.19 42.215 ; + POLYGON 105.07 36.775 105.07 33.945 104.23 33.945 104.23 35.17 103.77 35.17 103.77 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + POLYGON 105.07 31.335 105.07 28.505 103.77 28.505 103.77 30.11 104.23 30.11 104.23 31.335 ; + RECT -0.19 28.505 2.03 31.335 ; + POLYGON 105.07 25.895 105.07 23.065 102.85 23.065 102.85 24.67 103.77 24.67 103.77 25.895 ; + RECT -0.19 23.065 2.03 25.895 ; + RECT 103.77 17.625 105.07 20.455 ; + RECT -0.19 17.625 2.03 20.455 ; + RECT 103.77 12.185 105.07 15.015 ; + RECT -0.19 12.185 2.03 15.015 ; + RECT 103.77 6.745 105.07 9.575 ; + RECT -0.19 6.745 2.03 9.575 ; + POLYGON 105.07 4.135 105.07 1.305 102.85 1.305 102.85 2.91 103.77 2.91 103.77 4.135 ; + POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; + RECT 0 0 104.88 76.16 ; + LAYER pwell ; + RECT 99.49 76.11 99.71 76.28 ; + RECT 95.81 76.11 96.03 76.28 ; + RECT 92.13 76.11 92.35 76.28 ; + RECT 88.45 76.11 88.67 76.28 ; + RECT 84.77 76.11 84.99 76.28 ; + RECT 81.09 76.11 81.31 76.28 ; + RECT 77.41 76.11 77.63 76.28 ; + RECT 73.73 76.11 73.95 76.28 ; + RECT 70.05 76.11 70.27 76.28 ; + RECT 66.37 76.11 66.59 76.28 ; + RECT 62.69 76.11 62.91 76.28 ; + RECT 59.01 76.11 59.23 76.28 ; + RECT 55.33 76.11 55.55 76.28 ; + RECT 51.65 76.11 51.87 76.28 ; + RECT 47.97 76.11 48.19 76.28 ; + RECT 44.29 76.11 44.51 76.28 ; + RECT 40.61 76.11 40.83 76.28 ; + RECT 36.93 76.11 37.15 76.28 ; + RECT 33.25 76.11 33.47 76.28 ; + RECT 29.57 76.11 29.79 76.28 ; + RECT 25.89 76.11 26.11 76.28 ; + RECT 22.21 76.11 22.43 76.28 ; + RECT 18.53 76.11 18.75 76.28 ; + RECT 14.85 76.11 15.07 76.28 ; + RECT 11.17 76.11 11.39 76.28 ; + RECT 7.49 76.11 7.71 76.28 ; + RECT 3.81 76.11 4.03 76.28 ; + RECT 0.13 76.11 0.35 76.28 ; + RECT 103.215 76.1 103.325 76.22 ; + RECT 103.215 -0.06 103.325 0.06 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + RECT 0 0 104.88 76.16 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 104.88 76.16 104.88 0 ; + END +END cbx_1__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef new file mode 100644 index 0000000..8c9d439 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -0,0 +1,1930 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 104.88 BY 76.16 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 0 3.29 1.36 ; + END + END prog_clk[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.69 1.38 25.99 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.33 1.38 24.63 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.81 1.38 15.11 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 63.77 1.38 64.07 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END chanx_left_in[19] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 52.89 104.88 53.19 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 66.49 104.88 66.79 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 6.65 104.88 6.95 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 21.61 104.88 21.91 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 31.13 104.88 31.43 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 43.37 104.88 43.67 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 16.17 104.88 16.47 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 20.25 104.88 20.55 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 58.33 104.88 58.63 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 37.93 104.88 38.23 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 70.57 104.88 70.87 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 65.13 104.88 65.43 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 55.61 104.88 55.91 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 59.69 104.88 59.99 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 42.01 104.88 42.31 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 17.53 104.88 17.83 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 27.05 104.88 27.35 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 63.77 104.88 64.07 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 39.29 104.88 39.59 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 61.05 104.88 61.35 ; + END + END chanx_right_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 50.17 104.88 50.47 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 74.8 2.37 76.16 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.77 1.38 30.07 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 3.93 1.38 4.23 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 8.01 1.38 8.31 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 9.37 1.38 9.67 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.53 0 4.67 1.36 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.41 1.38 28.71 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 12.09 1.38 12.39 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 12.09 104.88 12.39 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 14.81 104.88 15.11 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 74.8 102.65 76.16 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 33.85 104.88 34.15 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 22.97 104.88 23.27 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 102.51 0 102.65 1.36 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 3.93 104.88 4.23 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 44.73 104.88 45.03 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 48.81 104.88 49.11 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 71.93 104.88 72.23 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 9.37 104.88 9.67 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 36.57 104.88 36.87 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 5.29 104.88 5.59 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 47.45 104.88 47.75 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 32.49 104.88 32.79 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 69.21 104.88 69.51 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 28.41 104.88 28.71 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 25.69 104.88 25.99 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 10.73 104.88 11.03 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.5 54.25 104.88 54.55 ; + END + END chanx_right_out[19] + PIN top_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.05 74.8 79.19 76.16 ; + END + END top_grid_pin_0_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 74.8 57.57 76.16 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 15.34 0 15.94 0.6 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 103.66 0 104.26 0.6 ; + RECT 15.34 75.56 15.94 76.16 ; + RECT 44.78 75.56 45.38 76.16 ; + RECT 74.22 75.56 74.82 76.16 ; + RECT 103.66 75.56 104.26 76.16 ; + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 101.68 16.08 104.88 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 101.68 56.88 104.88 60.08 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 104.4 2.48 104.88 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 104.4 7.92 104.88 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 104.4 13.36 104.88 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 104.4 18.8 104.88 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 104.4 24.24 104.88 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 104.4 29.68 104.88 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 104.4 35.12 104.88 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 104.4 40.56 104.88 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 104.4 46 104.88 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 104.4 51.44 104.88 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 104.4 56.88 104.88 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 104.4 62.32 104.88 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 104.4 67.76 104.88 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 104.4 73.2 104.88 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 0.62 0 1.22 0.6 ; + RECT 30.06 0 30.66 0.6 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 0.62 75.56 1.22 76.16 ; + RECT 30.06 75.56 30.66 76.16 ; + RECT 59.5 75.56 60.1 76.16 ; + RECT 88.94 75.56 89.54 76.16 ; + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 101.68 36.48 104.88 39.68 ; + LAYER met1 ; + RECT 0 0 104.88 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 104.4 5.2 104.88 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 104.4 10.64 104.88 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 104.4 16.08 104.88 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 104.4 21.52 104.88 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 104.4 26.96 104.88 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 104.4 32.4 104.88 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 104.4 37.84 104.88 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 104.4 43.28 104.88 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 104.4 48.72 104.88 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 104.4 54.16 104.88 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 104.4 59.6 104.88 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 104.4 65.04 104.88 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 104.4 70.48 104.88 70.96 ; + RECT 0 75.92 104.88 76.16 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 76.075 104.88 76.245 ; + RECT 103.04 73.355 104.88 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.96 70.635 104.88 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 103.96 67.915 104.88 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.96 65.195 104.88 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 104.42 62.475 104.88 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 103.96 59.755 104.88 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.96 57.035 104.88 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 103.96 54.315 104.88 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 103.96 51.595 104.88 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 103.96 48.875 104.88 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 103.96 46.155 104.88 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 103.96 43.435 104.88 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 103.96 40.715 104.88 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 103.96 37.995 104.88 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 103.96 35.275 104.88 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 103.96 32.555 104.88 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 103.96 29.835 104.88 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 103.96 27.115 104.88 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 103.96 24.395 104.88 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.96 21.675 104.88 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 103.96 18.955 104.88 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 103.96 16.235 104.88 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 103.96 13.515 104.88 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 103.96 10.795 104.88 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 103.96 8.075 104.88 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 103.96 5.355 104.88 5.525 ; + RECT 0 5.355 1.84 5.525 ; + RECT 103.04 2.635 104.88 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 104.88 0.085 ; + LAYER met2 ; + RECT 89.1 75.975 89.38 76.345 ; + RECT 59.66 75.975 59.94 76.345 ; + RECT 30.22 75.975 30.5 76.345 ; + RECT 0.78 75.975 1.06 76.345 ; + RECT 89.1 -0.185 89.38 0.185 ; + RECT 59.66 -0.185 59.94 0.185 ; + RECT 30.22 -0.185 30.5 0.185 ; + RECT 0.78 -0.185 1.06 0.185 ; + POLYGON 104.6 75.88 104.6 0.28 102.93 0.28 102.93 1.64 102.23 1.64 102.23 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 78.77 75.88 78.77 74.52 79.47 74.52 79.47 75.88 102.23 75.88 102.23 74.52 102.93 74.52 102.93 75.88 ; + LAYER met3 ; + POLYGON 89.405 76.325 89.405 76.32 89.62 76.32 89.62 76 89.405 76 89.405 75.995 89.075 75.995 89.075 76 88.86 76 88.86 76.32 89.075 76.32 89.075 76.325 ; + POLYGON 59.965 76.325 59.965 76.32 60.18 76.32 60.18 76 59.965 76 59.965 75.995 59.635 75.995 59.635 76 59.42 76 59.42 76.32 59.635 76.32 59.635 76.325 ; + POLYGON 30.525 76.325 30.525 76.32 30.74 76.32 30.74 76 30.525 76 30.525 75.995 30.195 75.995 30.195 76 29.98 76 29.98 76.32 30.195 76.32 30.195 76.325 ; + POLYGON 1.085 76.325 1.085 76.32 1.3 76.32 1.3 76 1.085 76 1.085 75.995 0.755 75.995 0.755 76 0.54 76 0.54 76.32 0.755 76.32 0.755 76.325 ; + POLYGON 89.405 0.165 89.405 0.16 89.62 0.16 89.62 -0.16 89.405 -0.16 89.405 -0.165 89.075 -0.165 89.075 -0.16 88.86 -0.16 88.86 0.16 89.075 0.16 89.075 0.165 ; + POLYGON 59.965 0.165 59.965 0.16 60.18 0.16 60.18 -0.16 59.965 -0.16 59.965 -0.165 59.635 -0.165 59.635 -0.16 59.42 -0.16 59.42 0.16 59.635 0.16 59.635 0.165 ; + POLYGON 30.525 0.165 30.525 0.16 30.74 0.16 30.74 -0.16 30.525 -0.16 30.525 -0.165 30.195 -0.165 30.195 -0.16 29.98 -0.16 29.98 0.16 30.195 0.16 30.195 0.165 ; + POLYGON 1.085 0.165 1.085 0.16 1.3 0.16 1.3 -0.16 1.085 -0.16 1.085 -0.165 0.755 -0.165 0.755 -0.16 0.54 -0.16 0.54 0.16 0.755 0.16 0.755 0.165 ; + POLYGON 104.48 75.76 104.48 72.63 103.1 72.63 103.1 71.53 104.48 71.53 104.48 71.27 103.1 71.27 103.1 70.17 104.48 70.17 104.48 69.91 103.1 69.91 103.1 68.81 104.48 68.81 104.48 67.19 103.1 67.19 103.1 66.09 104.48 66.09 104.48 65.83 103.1 65.83 103.1 64.73 104.48 64.73 104.48 64.47 103.1 64.47 103.1 63.37 104.48 63.37 104.48 61.75 103.1 61.75 103.1 60.65 104.48 60.65 104.48 60.39 103.1 60.39 103.1 59.29 104.48 59.29 104.48 59.03 103.1 59.03 103.1 57.93 104.48 57.93 104.48 56.31 103.1 56.31 103.1 55.21 104.48 55.21 104.48 54.95 103.1 54.95 103.1 53.85 104.48 53.85 104.48 53.59 103.1 53.59 103.1 52.49 104.48 52.49 104.48 50.87 103.1 50.87 103.1 49.77 104.48 49.77 104.48 49.51 103.1 49.51 103.1 48.41 104.48 48.41 104.48 48.15 103.1 48.15 103.1 47.05 104.48 47.05 104.48 45.43 103.1 45.43 103.1 44.33 104.48 44.33 104.48 44.07 103.1 44.07 103.1 42.97 104.48 42.97 104.48 42.71 103.1 42.71 103.1 41.61 104.48 41.61 104.48 39.99 103.1 39.99 103.1 38.89 104.48 38.89 104.48 38.63 103.1 38.63 103.1 37.53 104.48 37.53 104.48 37.27 103.1 37.27 103.1 36.17 104.48 36.17 104.48 34.55 103.1 34.55 103.1 33.45 104.48 33.45 104.48 33.19 103.1 33.19 103.1 32.09 104.48 32.09 104.48 31.83 103.1 31.83 103.1 30.73 104.48 30.73 104.48 29.11 103.1 29.11 103.1 28.01 104.48 28.01 104.48 27.75 103.1 27.75 103.1 26.65 104.48 26.65 104.48 26.39 103.1 26.39 103.1 25.29 104.48 25.29 104.48 23.67 103.1 23.67 103.1 22.57 104.48 22.57 104.48 22.31 103.1 22.31 103.1 21.21 104.48 21.21 104.48 20.95 103.1 20.95 103.1 19.85 104.48 19.85 104.48 18.23 103.1 18.23 103.1 17.13 104.48 17.13 104.48 16.87 103.1 16.87 103.1 15.77 104.48 15.77 104.48 15.51 103.1 15.51 103.1 14.41 104.48 14.41 104.48 12.79 103.1 12.79 103.1 11.69 104.48 11.69 104.48 11.43 103.1 11.43 103.1 10.33 104.48 10.33 104.48 10.07 103.1 10.07 103.1 8.97 104.48 8.97 104.48 7.35 103.1 7.35 103.1 6.25 104.48 6.25 104.48 5.99 103.1 5.99 103.1 4.89 104.48 4.89 104.48 4.63 103.1 4.63 103.1 3.53 104.48 3.53 104.48 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 75.76 ; + LAYER met1 ; + POLYGON 104.6 75.64 104.6 73.96 104.12 73.96 104.12 72.92 104.6 72.92 104.6 71.24 104.12 71.24 104.12 70.2 104.6 70.2 104.6 68.52 104.12 68.52 104.12 67.48 104.6 67.48 104.6 65.8 104.12 65.8 104.12 64.76 104.6 64.76 104.6 63.08 104.12 63.08 104.12 62.04 104.6 62.04 104.6 60.36 104.12 60.36 104.12 59.32 104.6 59.32 104.6 57.64 104.12 57.64 104.12 56.6 104.6 56.6 104.6 54.92 104.12 54.92 104.12 53.88 104.6 53.88 104.6 52.2 104.12 52.2 104.12 51.16 104.6 51.16 104.6 49.48 104.12 49.48 104.12 48.44 104.6 48.44 104.6 46.76 104.12 46.76 104.12 45.72 104.6 45.72 104.6 44.04 104.12 44.04 104.12 43 104.6 43 104.6 41.32 104.12 41.32 104.12 40.28 104.6 40.28 104.6 38.6 104.12 38.6 104.12 37.56 104.6 37.56 104.6 35.88 104.12 35.88 104.12 34.84 104.6 34.84 104.6 33.16 104.12 33.16 104.12 32.12 104.6 32.12 104.6 30.44 104.12 30.44 104.12 29.4 104.6 29.4 104.6 27.72 104.12 27.72 104.12 26.68 104.6 26.68 104.6 25 104.12 25 104.12 23.96 104.6 23.96 104.6 22.28 104.12 22.28 104.12 21.24 104.6 21.24 104.6 19.56 104.12 19.56 104.12 18.52 104.6 18.52 104.6 16.84 104.12 16.84 104.12 15.8 104.6 15.8 104.6 14.12 104.12 14.12 104.12 13.08 104.6 13.08 104.6 11.4 104.12 11.4 104.12 10.36 104.6 10.36 104.6 8.68 104.12 8.68 104.12 7.64 104.6 7.64 104.6 5.96 104.12 5.96 104.12 4.92 104.6 4.92 104.6 3.24 104.12 3.24 104.12 2.2 104.6 2.2 104.6 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER met5 ; + POLYGON 101.68 72.96 101.68 63.28 98.48 63.28 98.48 53.68 101.68 53.68 101.68 42.88 98.48 42.88 98.48 33.28 101.68 33.28 101.68 22.48 98.48 22.48 98.48 12.88 101.68 12.88 101.68 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 ; + LAYER met4 ; + POLYGON 104.26 75.16 104.26 59.87 104.55 59.87 104.55 57.09 104.26 57.09 104.26 19.07 104.55 19.07 104.55 16.29 104.26 16.29 104.26 1 103.66 1 103.66 16.29 103.37 16.29 103.37 19.07 103.66 19.07 103.66 57.09 103.37 57.09 103.37 59.87 103.66 59.87 103.66 75.16 ; + POLYGON 1.22 75.16 1.22 39.47 1.51 39.47 1.51 36.69 1.22 36.69 1.22 1 0.62 1 0.62 36.69 0.33 36.69 0.33 39.47 0.62 39.47 0.62 75.16 ; + POLYGON 103.26 75.76 103.26 75.16 104.48 75.16 104.48 1 103.26 1 103.26 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 31.06 0.4 31.06 1 29.66 1 29.66 0.4 16.34 0.4 16.34 1 14.94 1 14.94 0.4 1.62 0.4 1.62 1 0.4 1 0.4 75.16 1.62 75.16 1.62 75.76 14.94 75.76 14.94 75.16 16.34 75.16 16.34 75.76 29.66 75.76 29.66 75.16 31.06 75.16 31.06 75.76 44.38 75.76 44.38 75.16 45.78 75.16 45.78 75.76 59.1 75.76 59.1 75.16 60.5 75.16 60.5 75.76 73.82 75.76 73.82 75.16 75.22 75.16 75.22 75.76 88.54 75.76 88.54 75.16 89.94 75.16 89.94 75.76 ; + LAYER li1 ; + RECT 0.34 0.34 104.54 75.82 ; + LAYER mcon ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 104.565 73.355 104.735 73.525 ; + RECT 104.105 73.355 104.275 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 104.565 70.635 104.735 70.805 ; + RECT 104.105 70.635 104.275 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 104.565 67.915 104.735 68.085 ; + RECT 104.105 67.915 104.275 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 104.565 65.195 104.735 65.365 ; + RECT 104.105 65.195 104.275 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 104.565 62.475 104.735 62.645 ; + RECT 104.105 62.475 104.275 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 104.565 59.755 104.735 59.925 ; + RECT 104.105 59.755 104.275 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 104.565 57.035 104.735 57.205 ; + RECT 104.105 57.035 104.275 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 104.565 54.315 104.735 54.485 ; + RECT 104.105 54.315 104.275 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 104.565 51.595 104.735 51.765 ; + RECT 104.105 51.595 104.275 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 104.565 48.875 104.735 49.045 ; + RECT 104.105 48.875 104.275 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 104.565 46.155 104.735 46.325 ; + RECT 104.105 46.155 104.275 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 104.565 43.435 104.735 43.605 ; + RECT 104.105 43.435 104.275 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 104.565 40.715 104.735 40.885 ; + RECT 104.105 40.715 104.275 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 104.565 37.995 104.735 38.165 ; + RECT 104.105 37.995 104.275 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 104.565 35.275 104.735 35.445 ; + RECT 104.105 35.275 104.275 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 104.565 32.555 104.735 32.725 ; + RECT 104.105 32.555 104.275 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 104.565 29.835 104.735 30.005 ; + RECT 104.105 29.835 104.275 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 104.565 24.395 104.735 24.565 ; + RECT 104.105 24.395 104.275 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 104.565 21.675 104.735 21.845 ; + RECT 104.105 21.675 104.275 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 104.565 18.955 104.735 19.125 ; + RECT 104.105 18.955 104.275 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 104.565 16.235 104.735 16.405 ; + RECT 104.105 16.235 104.275 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 104.565 13.515 104.735 13.685 ; + RECT 104.105 13.515 104.275 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 104.565 10.795 104.735 10.965 ; + RECT 104.105 10.795 104.275 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 104.565 8.075 104.735 8.245 ; + RECT 104.105 8.075 104.275 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 104.565 5.355 104.735 5.525 ; + RECT 104.105 5.355 104.275 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 104.565 2.635 104.735 2.805 ; + RECT 104.105 2.635 104.275 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 89.165 76.085 89.315 76.235 ; + RECT 59.725 76.085 59.875 76.235 ; + RECT 30.285 76.085 30.435 76.235 ; + RECT 0.845 76.085 0.995 76.235 ; + RECT 57.425 74.385 57.575 74.535 ; + RECT 89.165 -0.075 89.315 0.075 ; + RECT 59.725 -0.075 59.875 0.075 ; + RECT 30.285 -0.075 30.435 0.075 ; + RECT 0.845 -0.075 0.995 0.075 ; + LAYER via2 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 1.28 18.94 1.48 19.14 ; + RECT 1.74 8.06 1.94 8.26 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via3 ; + RECT 89.14 76.06 89.34 76.26 ; + RECT 59.7 76.06 59.9 76.26 ; + RECT 30.26 76.06 30.46 76.26 ; + RECT 0.82 76.06 1.02 76.26 ; + RECT 89.14 -0.1 89.34 0.1 ; + RECT 59.7 -0.1 59.9 0.1 ; + RECT 30.26 -0.1 30.46 0.1 ; + RECT 0.82 -0.1 1.02 0.1 ; + LAYER via4 ; + RECT 103.56 58.88 104.36 59.68 ; + RECT 103.56 57.28 104.36 58.08 ; + RECT 0.52 38.48 1.32 39.28 ; + RECT 0.52 36.88 1.32 37.68 ; + RECT 103.56 18.08 104.36 18.88 ; + RECT 103.56 16.48 104.36 17.28 ; + LAYER fieldpoly ; + RECT 0.14 0.14 104.74 76.02 ; + LAYER diff ; + RECT 0 0 104.88 76.16 ; + LAYER nwell ; + POLYGON 105.07 74.855 105.07 72.025 103.77 72.025 103.77 73.25 102.85 73.25 102.85 74.855 ; + POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; + RECT 103.77 66.585 105.07 69.415 ; + POLYGON 2.03 69.415 2.03 68.19 3.87 68.19 3.87 66.585 -0.19 66.585 -0.19 69.415 ; + RECT 104.23 61.145 105.07 63.975 ; + RECT -0.19 61.145 3.87 63.975 ; + RECT 103.77 55.705 105.07 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 103.77 50.265 105.07 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + RECT 103.77 44.825 105.07 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + POLYGON 105.07 42.215 105.07 39.385 103.77 39.385 103.77 40.99 104.23 40.99 104.23 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + RECT 103.77 33.945 105.07 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + RECT 103.77 28.505 105.07 31.335 ; + RECT -0.19 28.505 2.03 31.335 ; + RECT 103.77 23.065 105.07 25.895 ; + RECT -0.19 23.065 2.03 25.895 ; + POLYGON 105.07 20.455 105.07 17.625 103.77 17.625 103.77 19.23 104.23 19.23 104.23 20.455 ; + POLYGON 3.87 20.455 3.87 18.85 2.03 18.85 2.03 17.625 -0.19 17.625 -0.19 20.455 ; + RECT 103.77 12.185 105.07 15.015 ; + RECT -0.19 12.185 2.03 15.015 ; + RECT 103.77 6.745 105.07 9.575 ; + RECT -0.19 6.745 2.03 9.575 ; + POLYGON 105.07 4.135 105.07 1.305 102.85 1.305 102.85 2.91 103.77 2.91 103.77 4.135 ; + POLYGON 2.03 4.135 2.03 2.91 3.87 2.91 3.87 1.305 -0.19 1.305 -0.19 4.135 ; + RECT 0 0 104.88 76.16 ; + LAYER pwell ; + RECT 99.49 76.11 99.71 76.28 ; + RECT 95.81 76.11 96.03 76.28 ; + RECT 92.13 76.11 92.35 76.28 ; + RECT 88.45 76.11 88.67 76.28 ; + RECT 84.77 76.11 84.99 76.28 ; + RECT 81.09 76.11 81.31 76.28 ; + RECT 77.41 76.11 77.63 76.28 ; + RECT 73.73 76.11 73.95 76.28 ; + RECT 70.05 76.11 70.27 76.28 ; + RECT 66.37 76.11 66.59 76.28 ; + RECT 62.69 76.11 62.91 76.28 ; + RECT 59.01 76.11 59.23 76.28 ; + RECT 55.33 76.11 55.55 76.28 ; + RECT 51.65 76.11 51.87 76.28 ; + RECT 47.97 76.11 48.19 76.28 ; + RECT 44.29 76.11 44.51 76.28 ; + RECT 40.61 76.11 40.83 76.28 ; + RECT 36.93 76.11 37.15 76.28 ; + RECT 33.25 76.11 33.47 76.28 ; + RECT 29.57 76.11 29.79 76.28 ; + RECT 25.89 76.11 26.11 76.28 ; + RECT 22.21 76.11 22.43 76.28 ; + RECT 18.53 76.11 18.75 76.28 ; + RECT 14.85 76.11 15.07 76.28 ; + RECT 11.17 76.11 11.39 76.28 ; + RECT 7.49 76.11 7.71 76.28 ; + RECT 3.81 76.11 4.03 76.28 ; + RECT 0.13 76.11 0.35 76.28 ; + RECT 103.215 76.1 103.325 76.22 ; + RECT 103.215 -0.06 103.325 0.06 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + RECT 0 0 104.88 76.16 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 104.88 76.16 104.88 0 ; + END +END cbx_1__2_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef new file mode 100644 index 0000000..28a5ba0 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -0,0 +1,1930 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_0__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 84.64 BY 108.8 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 3.25 1.38 3.55 ; + END + END prog_clk[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 0 42.85 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 0 25.83 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 0 71.37 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 0 49.29 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.27 0 36.41 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.85 0 69.15 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.93 0 22.23 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 9.05 0 9.35 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 0 46.53 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 0 51.13 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 0 7.43 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 0 46.15 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 0 52.97 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 0 47.99 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 0 25.91 1.36 ; + END + END chany_bottom_in[19] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 107.44 50.21 108.8 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.43 107.44 34.57 108.8 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 107.44 66.77 108.8 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 107.44 44.69 108.8 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 107.44 51.13 108.8 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 107.44 45.61 108.8 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 107.44 70.45 108.8 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 107.44 68.61 108.8 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 107.44 69.53 108.8 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 107.44 25.83 108.8 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 107.44 42.85 108.8 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 107.44 48.37 108.8 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 107.44 67.69 108.8 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 107.44 49.83 108.8 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 107.44 46.15 108.8 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 107.44 47.99 108.8 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.45 107.44 28.59 108.8 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 107.44 47.45 108.8 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 107.44 24.07 108.8 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 107.44 25.91 108.8 ; + END + END chany_top_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 107.44 54.35 108.8 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 0 67.69 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 0 62.17 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 0 43.77 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 0 29.05 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 0 69.53 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 0 68.61 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.95 0 63.09 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 0 50.21 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 0 72.29 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 20.09 0 20.39 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 29.29 0 29.59 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 0 49.83 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.73 0 59.03 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 14.57 0 14.87 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 44.01 0 44.31 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 0 47.45 1.36 ; + END + END chany_bottom_out[19] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.71 107.44 65.85 108.8 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.65 107.44 14.79 108.8 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 107.44 71.37 108.8 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.73 107.44 13.87 108.8 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 107.44 73.21 108.8 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 107.44 49.29 108.8 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 107.44 52.97 108.8 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 107.44 22.15 108.8 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 107.44 23.99 108.8 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 107.44 23.07 108.8 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 107.44 52.05 108.8 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 107.44 30.89 108.8 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.87 107.44 64.01 108.8 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 107.44 72.29 108.8 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 107.44 43.77 108.8 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 107.44 46.53 108.8 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 107.44 41.93 108.8 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 107.44 29.97 108.8 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.61 107.44 26.75 108.8 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 107.44 24.91 108.8 ; + END + END chany_top_out[19] + PIN right_grid_pin_52_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 78.73 84.64 79.03 ; + END + END right_grid_pin_52_[0] + PIN left_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END left_grid_pin_0_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 78.73 1.38 79.03 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 22.2 3.2 25.4 ; + RECT 81.44 22.2 84.64 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 81.44 63 84.64 66.2 ; + RECT 0 103.8 3.2 107 ; + RECT 81.44 103.8 84.64 107 ; + LAYER met4 ; + RECT 12.58 0 13.18 0.6 ; + RECT 42.02 0 42.62 0.6 ; + RECT 71.46 0 72.06 0.6 ; + RECT 12.58 108.2 13.18 108.8 ; + RECT 42.02 108.2 42.62 108.8 ; + RECT 71.46 108.2 72.06 108.8 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 84.16 2.48 84.64 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 84.16 7.92 84.64 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 84.16 13.36 84.64 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 84.16 18.8 84.64 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 84.16 24.24 84.64 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 84.16 29.68 84.64 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 84.16 35.12 84.64 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 84.16 40.56 84.64 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 84.16 46 84.64 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 84.16 51.44 84.64 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 84.16 56.88 84.64 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 84.16 62.32 84.64 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 84.16 67.76 84.64 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 84.16 73.2 84.64 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 84.16 78.64 84.64 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 84.16 84.08 84.64 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 84.16 89.52 84.64 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 84.16 94.96 84.64 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 84.16 100.4 84.64 100.88 ; + RECT 0 105.84 0.48 106.32 ; + RECT 84.16 105.84 84.64 106.32 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 1.8 3.2 5 ; + RECT 81.44 1.8 84.64 5 ; + RECT 0 42.6 3.2 45.8 ; + RECT 81.44 42.6 84.64 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 81.44 83.4 84.64 86.6 ; + LAYER met4 ; + RECT 27.3 0 27.9 0.6 ; + RECT 56.74 0 57.34 0.6 ; + RECT 27.3 108.2 27.9 108.8 ; + RECT 56.74 108.2 57.34 108.8 ; + LAYER met1 ; + RECT 0 0 84.64 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 84.16 5.2 84.64 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 84.16 10.64 84.64 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 84.16 16.08 84.64 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 84.16 21.52 84.64 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 84.16 26.96 84.64 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 84.16 32.4 84.64 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 84.16 37.84 84.64 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 84.16 43.28 84.64 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 84.16 48.72 84.64 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 84.16 54.16 84.64 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 84.16 59.6 84.64 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 84.16 65.04 84.64 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 84.16 70.48 84.64 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 84.16 75.92 84.64 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 84.16 81.36 84.64 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 84.16 86.8 84.64 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 84.16 92.24 84.64 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 84.16 97.68 84.64 98.16 ; + RECT 0 103.12 0.48 103.6 ; + RECT 84.16 103.12 84.64 103.6 ; + RECT 0 108.56 84.64 108.8 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 108.715 84.64 108.885 ; + RECT 80.96 105.995 84.64 106.165 ; + RECT 0 105.995 3.68 106.165 ; + RECT 83.72 103.275 84.64 103.445 ; + RECT 0 103.275 3.68 103.445 ; + RECT 83.72 100.555 84.64 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 84.18 97.835 84.64 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 84.18 95.115 84.64 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 84.18 92.395 84.64 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 84.18 89.675 84.64 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 84.18 86.955 84.64 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 83.72 84.235 84.64 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 83.72 81.515 84.64 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 83.72 78.795 84.64 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 80.96 76.075 84.64 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 80.96 73.355 84.64 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 82.8 70.635 84.64 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 82.8 67.915 84.64 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 83.72 65.195 84.64 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 83.72 62.475 84.64 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 83.72 59.755 84.64 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 80.96 57.035 84.64 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 80.96 54.315 84.64 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 80.96 51.595 84.64 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 80.96 48.875 84.64 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 80.96 46.155 84.64 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 80.96 43.435 84.64 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 80.96 40.715 84.64 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 80.96 37.995 84.64 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 80.96 35.275 84.64 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 80.96 32.555 84.64 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 80.96 29.835 84.64 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 80.96 27.115 84.64 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 82.8 24.395 84.64 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 82.8 21.675 84.64 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 82.8 18.955 84.64 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 82.8 16.235 84.64 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 84.18 13.515 84.64 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 84.18 10.795 84.64 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 83.72 8.075 84.64 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 80.96 5.355 84.64 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 80.96 2.635 84.64 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 84.64 0.085 ; + LAYER met3 ; + POLYGON 57.205 108.965 57.205 108.96 57.42 108.96 57.42 108.64 57.205 108.64 57.205 108.635 56.875 108.635 56.875 108.64 56.66 108.64 56.66 108.96 56.875 108.96 56.875 108.965 ; + POLYGON 27.765 108.965 27.765 108.96 27.98 108.96 27.98 108.64 27.765 108.64 27.765 108.635 27.435 108.635 27.435 108.64 27.22 108.64 27.22 108.96 27.435 108.96 27.435 108.965 ; + POLYGON 57.205 0.165 57.205 0.16 57.42 0.16 57.42 -0.16 57.205 -0.16 57.205 -0.165 56.875 -0.165 56.875 -0.16 56.66 -0.16 56.66 0.16 56.875 0.16 56.875 0.165 ; + POLYGON 27.765 0.165 27.765 0.16 27.98 0.16 27.98 -0.16 27.765 -0.16 27.765 -0.165 27.435 -0.165 27.435 -0.16 27.22 -0.16 27.22 0.16 27.435 0.16 27.435 0.165 ; + POLYGON 84.24 108.4 84.24 79.43 82.86 79.43 82.86 78.33 84.24 78.33 84.24 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 108.4 ; + LAYER met2 ; + RECT 56.9 108.615 57.18 108.985 ; + RECT 27.46 108.615 27.74 108.985 ; + RECT 51.39 106.94 51.65 107.26 ; + RECT 41.27 106.94 41.53 107.26 ; + RECT 56.9 -0.185 57.18 0.185 ; + RECT 27.46 -0.185 27.74 0.185 ; + POLYGON 84.36 108.52 84.36 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 108.52 13.45 108.52 13.45 107.16 14.15 107.16 14.15 108.52 14.37 108.52 14.37 107.16 15.07 107.16 15.07 108.52 21.73 108.52 21.73 107.16 22.43 107.16 22.43 108.52 22.65 108.52 22.65 107.16 23.35 107.16 23.35 108.52 23.57 108.52 23.57 107.16 24.27 107.16 24.27 108.52 24.49 108.52 24.49 107.16 25.19 107.16 25.19 108.52 25.41 108.52 25.41 107.16 26.11 107.16 26.11 108.52 26.33 108.52 26.33 107.16 27.03 107.16 27.03 108.52 28.17 108.52 28.17 107.16 28.87 107.16 28.87 108.52 29.55 108.52 29.55 107.16 30.25 107.16 30.25 108.52 30.47 108.52 30.47 107.16 31.17 107.16 31.17 108.52 34.15 108.52 34.15 107.16 34.85 107.16 34.85 108.52 41.51 108.52 41.51 107.16 42.21 107.16 42.21 108.52 42.43 108.52 42.43 107.16 43.13 107.16 43.13 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 52.55 108.52 52.55 107.16 53.25 107.16 53.25 108.52 53.93 108.52 53.93 107.16 54.63 107.16 54.63 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 66.35 108.52 66.35 107.16 67.05 107.16 67.05 108.52 67.27 108.52 67.27 107.16 67.97 107.16 67.97 108.52 68.19 108.52 68.19 107.16 68.89 107.16 68.89 108.52 69.11 108.52 69.11 107.16 69.81 107.16 69.81 108.52 70.03 108.52 70.03 107.16 70.73 107.16 70.73 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 71.87 108.52 71.87 107.16 72.57 107.16 72.57 108.52 72.79 108.52 72.79 107.16 73.49 107.16 73.49 108.52 ; + LAYER met4 ; + POLYGON 84.24 108.4 84.24 0.4 72.46 0.4 72.46 1 71.06 1 71.06 0.4 69.55 0.4 69.55 1.76 68.45 1.76 68.45 0.4 59.43 0.4 59.43 1.76 58.33 1.76 58.33 0.4 57.74 0.4 57.74 1 56.34 1 56.34 0.4 50.23 0.4 50.23 1.76 49.13 1.76 49.13 0.4 48.39 0.4 48.39 1.76 47.29 1.76 47.29 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 44.71 0.4 44.71 1.76 43.61 1.76 43.61 0.4 43.02 0.4 43.02 1 41.62 1 41.62 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.3 0.4 28.3 1 26.9 1 26.9 0.4 26.31 0.4 26.31 1.76 25.21 1.76 25.21 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 20.79 0.4 20.79 1.76 19.69 1.76 19.69 0.4 15.27 0.4 15.27 1.76 14.17 1.76 14.17 0.4 13.58 0.4 13.58 1 12.18 1 12.18 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 108.4 12.18 108.4 12.18 107.8 13.58 107.8 13.58 108.4 23.37 108.4 23.37 107.04 24.47 107.04 24.47 108.4 25.21 108.4 25.21 107.04 26.31 107.04 26.31 108.4 26.9 108.4 26.9 107.8 28.3 107.8 28.3 108.4 41.62 108.4 41.62 107.8 43.02 107.8 43.02 108.4 45.45 108.4 45.45 107.04 46.55 107.04 46.55 108.4 47.29 108.4 47.29 107.04 48.39 107.04 48.39 108.4 49.13 108.4 49.13 107.04 50.23 107.04 50.23 108.4 56.34 108.4 56.34 107.8 57.74 107.8 57.74 108.4 71.06 108.4 71.06 107.8 72.46 107.8 72.46 108.4 ; + LAYER met1 ; + POLYGON 84.36 108.28 84.36 106.6 83.88 106.6 83.88 105.56 84.36 105.56 84.36 103.88 83.88 103.88 83.88 102.84 84.36 102.84 84.36 101.16 83.88 101.16 83.88 100.12 84.36 100.12 84.36 98.44 83.88 98.44 83.88 97.4 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 83.88 82.12 83.88 81.08 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; + LAYER met5 ; + RECT 6.4 103.8 78.24 107 ; + RECT 6.4 1.8 78.24 5 ; + POLYGON 78.24 105.6 78.24 100.6 81.44 100.6 81.44 89.8 78.24 89.8 78.24 80.2 81.44 80.2 81.44 69.4 78.24 69.4 78.24 59.8 81.44 59.8 81.44 49 78.24 49 78.24 39.4 81.44 39.4 81.44 28.6 78.24 28.6 78.24 19 81.44 19 81.44 8.2 78.24 8.2 78.24 3.2 6.4 3.2 6.4 8.2 3.2 8.2 3.2 19 6.4 19 6.4 28.6 3.2 28.6 3.2 39.4 6.4 39.4 6.4 49 3.2 49 3.2 59.8 6.4 59.8 6.4 69.4 3.2 69.4 3.2 80.2 6.4 80.2 6.4 89.8 3.2 89.8 3.2 100.6 6.4 100.6 6.4 105.6 ; + LAYER li1 ; + RECT 0.34 0.34 84.3 108.46 ; + LAYER mcon ; + RECT 84.325 108.715 84.495 108.885 ; + RECT 83.865 108.715 84.035 108.885 ; + RECT 83.405 108.715 83.575 108.885 ; + RECT 82.945 108.715 83.115 108.885 ; + RECT 82.485 108.715 82.655 108.885 ; + RECT 82.025 108.715 82.195 108.885 ; + RECT 81.565 108.715 81.735 108.885 ; + RECT 81.105 108.715 81.275 108.885 ; + RECT 80.645 108.715 80.815 108.885 ; + RECT 80.185 108.715 80.355 108.885 ; + RECT 79.725 108.715 79.895 108.885 ; + RECT 79.265 108.715 79.435 108.885 ; + RECT 78.805 108.715 78.975 108.885 ; + RECT 78.345 108.715 78.515 108.885 ; + RECT 77.885 108.715 78.055 108.885 ; + RECT 77.425 108.715 77.595 108.885 ; + RECT 76.965 108.715 77.135 108.885 ; + RECT 76.505 108.715 76.675 108.885 ; + RECT 76.045 108.715 76.215 108.885 ; + RECT 75.585 108.715 75.755 108.885 ; + RECT 75.125 108.715 75.295 108.885 ; + RECT 74.665 108.715 74.835 108.885 ; + RECT 74.205 108.715 74.375 108.885 ; + RECT 73.745 108.715 73.915 108.885 ; + RECT 73.285 108.715 73.455 108.885 ; + RECT 72.825 108.715 72.995 108.885 ; + RECT 72.365 108.715 72.535 108.885 ; + RECT 71.905 108.715 72.075 108.885 ; + RECT 71.445 108.715 71.615 108.885 ; + RECT 70.985 108.715 71.155 108.885 ; + RECT 70.525 108.715 70.695 108.885 ; + RECT 70.065 108.715 70.235 108.885 ; + RECT 69.605 108.715 69.775 108.885 ; + RECT 69.145 108.715 69.315 108.885 ; + RECT 68.685 108.715 68.855 108.885 ; + RECT 68.225 108.715 68.395 108.885 ; + RECT 67.765 108.715 67.935 108.885 ; + RECT 67.305 108.715 67.475 108.885 ; + RECT 66.845 108.715 67.015 108.885 ; + RECT 66.385 108.715 66.555 108.885 ; + RECT 65.925 108.715 66.095 108.885 ; + RECT 65.465 108.715 65.635 108.885 ; + RECT 65.005 108.715 65.175 108.885 ; + RECT 64.545 108.715 64.715 108.885 ; + RECT 64.085 108.715 64.255 108.885 ; + RECT 63.625 108.715 63.795 108.885 ; + RECT 63.165 108.715 63.335 108.885 ; + RECT 62.705 108.715 62.875 108.885 ; + RECT 62.245 108.715 62.415 108.885 ; + RECT 61.785 108.715 61.955 108.885 ; + RECT 61.325 108.715 61.495 108.885 ; + RECT 60.865 108.715 61.035 108.885 ; + RECT 60.405 108.715 60.575 108.885 ; + RECT 59.945 108.715 60.115 108.885 ; + RECT 59.485 108.715 59.655 108.885 ; + RECT 59.025 108.715 59.195 108.885 ; + RECT 58.565 108.715 58.735 108.885 ; + RECT 58.105 108.715 58.275 108.885 ; + RECT 57.645 108.715 57.815 108.885 ; + RECT 57.185 108.715 57.355 108.885 ; + RECT 56.725 108.715 56.895 108.885 ; + RECT 56.265 108.715 56.435 108.885 ; + RECT 55.805 108.715 55.975 108.885 ; + RECT 55.345 108.715 55.515 108.885 ; + RECT 54.885 108.715 55.055 108.885 ; + RECT 54.425 108.715 54.595 108.885 ; + RECT 53.965 108.715 54.135 108.885 ; + RECT 53.505 108.715 53.675 108.885 ; + RECT 53.045 108.715 53.215 108.885 ; + RECT 52.585 108.715 52.755 108.885 ; + RECT 52.125 108.715 52.295 108.885 ; + RECT 51.665 108.715 51.835 108.885 ; + RECT 51.205 108.715 51.375 108.885 ; + RECT 50.745 108.715 50.915 108.885 ; + RECT 50.285 108.715 50.455 108.885 ; + RECT 49.825 108.715 49.995 108.885 ; + RECT 49.365 108.715 49.535 108.885 ; + RECT 48.905 108.715 49.075 108.885 ; + RECT 48.445 108.715 48.615 108.885 ; + RECT 47.985 108.715 48.155 108.885 ; + RECT 47.525 108.715 47.695 108.885 ; + RECT 47.065 108.715 47.235 108.885 ; + RECT 46.605 108.715 46.775 108.885 ; + RECT 46.145 108.715 46.315 108.885 ; + RECT 45.685 108.715 45.855 108.885 ; + RECT 45.225 108.715 45.395 108.885 ; + RECT 44.765 108.715 44.935 108.885 ; + RECT 44.305 108.715 44.475 108.885 ; + RECT 43.845 108.715 44.015 108.885 ; + RECT 43.385 108.715 43.555 108.885 ; + RECT 42.925 108.715 43.095 108.885 ; + RECT 42.465 108.715 42.635 108.885 ; + RECT 42.005 108.715 42.175 108.885 ; + RECT 41.545 108.715 41.715 108.885 ; + RECT 41.085 108.715 41.255 108.885 ; + RECT 40.625 108.715 40.795 108.885 ; + RECT 40.165 108.715 40.335 108.885 ; + RECT 39.705 108.715 39.875 108.885 ; + RECT 39.245 108.715 39.415 108.885 ; + RECT 38.785 108.715 38.955 108.885 ; + RECT 38.325 108.715 38.495 108.885 ; + RECT 37.865 108.715 38.035 108.885 ; + RECT 37.405 108.715 37.575 108.885 ; + RECT 36.945 108.715 37.115 108.885 ; + RECT 36.485 108.715 36.655 108.885 ; + RECT 36.025 108.715 36.195 108.885 ; + RECT 35.565 108.715 35.735 108.885 ; + RECT 35.105 108.715 35.275 108.885 ; + RECT 34.645 108.715 34.815 108.885 ; + RECT 34.185 108.715 34.355 108.885 ; + RECT 33.725 108.715 33.895 108.885 ; + RECT 33.265 108.715 33.435 108.885 ; + RECT 32.805 108.715 32.975 108.885 ; + RECT 32.345 108.715 32.515 108.885 ; + RECT 31.885 108.715 32.055 108.885 ; + RECT 31.425 108.715 31.595 108.885 ; + RECT 30.965 108.715 31.135 108.885 ; + RECT 30.505 108.715 30.675 108.885 ; + RECT 30.045 108.715 30.215 108.885 ; + RECT 29.585 108.715 29.755 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 28.205 108.715 28.375 108.885 ; + RECT 27.745 108.715 27.915 108.885 ; + RECT 27.285 108.715 27.455 108.885 ; + RECT 26.825 108.715 26.995 108.885 ; + RECT 26.365 108.715 26.535 108.885 ; + RECT 25.905 108.715 26.075 108.885 ; + RECT 25.445 108.715 25.615 108.885 ; + RECT 24.985 108.715 25.155 108.885 ; + RECT 24.525 108.715 24.695 108.885 ; + RECT 24.065 108.715 24.235 108.885 ; + RECT 23.605 108.715 23.775 108.885 ; + RECT 23.145 108.715 23.315 108.885 ; + RECT 22.685 108.715 22.855 108.885 ; + RECT 22.225 108.715 22.395 108.885 ; + RECT 21.765 108.715 21.935 108.885 ; + RECT 21.305 108.715 21.475 108.885 ; + RECT 20.845 108.715 21.015 108.885 ; + RECT 20.385 108.715 20.555 108.885 ; + RECT 19.925 108.715 20.095 108.885 ; + RECT 19.465 108.715 19.635 108.885 ; + RECT 19.005 108.715 19.175 108.885 ; + RECT 18.545 108.715 18.715 108.885 ; + RECT 18.085 108.715 18.255 108.885 ; + RECT 17.625 108.715 17.795 108.885 ; + RECT 17.165 108.715 17.335 108.885 ; + RECT 16.705 108.715 16.875 108.885 ; + RECT 16.245 108.715 16.415 108.885 ; + RECT 15.785 108.715 15.955 108.885 ; + RECT 15.325 108.715 15.495 108.885 ; + RECT 14.865 108.715 15.035 108.885 ; + RECT 14.405 108.715 14.575 108.885 ; + RECT 13.945 108.715 14.115 108.885 ; + RECT 13.485 108.715 13.655 108.885 ; + RECT 13.025 108.715 13.195 108.885 ; + RECT 12.565 108.715 12.735 108.885 ; + RECT 12.105 108.715 12.275 108.885 ; + RECT 11.645 108.715 11.815 108.885 ; + RECT 11.185 108.715 11.355 108.885 ; + RECT 10.725 108.715 10.895 108.885 ; + RECT 10.265 108.715 10.435 108.885 ; + RECT 9.805 108.715 9.975 108.885 ; + RECT 9.345 108.715 9.515 108.885 ; + RECT 8.885 108.715 9.055 108.885 ; + RECT 8.425 108.715 8.595 108.885 ; + RECT 7.965 108.715 8.135 108.885 ; + RECT 7.505 108.715 7.675 108.885 ; + RECT 7.045 108.715 7.215 108.885 ; + RECT 6.585 108.715 6.755 108.885 ; + RECT 6.125 108.715 6.295 108.885 ; + RECT 5.665 108.715 5.835 108.885 ; + RECT 5.205 108.715 5.375 108.885 ; + RECT 4.745 108.715 4.915 108.885 ; + RECT 4.285 108.715 4.455 108.885 ; + RECT 3.825 108.715 3.995 108.885 ; + RECT 3.365 108.715 3.535 108.885 ; + RECT 2.905 108.715 3.075 108.885 ; + RECT 2.445 108.715 2.615 108.885 ; + RECT 1.985 108.715 2.155 108.885 ; + RECT 1.525 108.715 1.695 108.885 ; + RECT 1.065 108.715 1.235 108.885 ; + RECT 0.605 108.715 0.775 108.885 ; + RECT 0.145 108.715 0.315 108.885 ; + RECT 84.325 105.995 84.495 106.165 ; + RECT 83.865 105.995 84.035 106.165 ; + RECT 0.605 105.995 0.775 106.165 ; + RECT 0.145 105.995 0.315 106.165 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 84.325 100.555 84.495 100.725 ; + RECT 83.865 100.555 84.035 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 84.325 95.115 84.495 95.285 ; + RECT 83.865 95.115 84.035 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 84.325 92.395 84.495 92.565 ; + RECT 83.865 92.395 84.035 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 84.325 89.675 84.495 89.845 ; + RECT 83.865 89.675 84.035 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 84.325 84.235 84.495 84.405 ; + RECT 83.865 84.235 84.035 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 84.325 81.515 84.495 81.685 ; + RECT 83.865 81.515 84.035 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 84.325 78.795 84.495 78.965 ; + RECT 83.865 78.795 84.035 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 84.325 73.355 84.495 73.525 ; + RECT 83.865 73.355 84.035 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 84.325 70.635 84.495 70.805 ; + RECT 83.865 70.635 84.035 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 84.325 67.915 84.495 68.085 ; + RECT 83.865 67.915 84.035 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 84.325 65.195 84.495 65.365 ; + RECT 83.865 65.195 84.035 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 84.325 62.475 84.495 62.645 ; + RECT 83.865 62.475 84.035 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 84.325 59.755 84.495 59.925 ; + RECT 83.865 59.755 84.035 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 84.325 57.035 84.495 57.205 ; + RECT 83.865 57.035 84.035 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 84.325 54.315 84.495 54.485 ; + RECT 83.865 54.315 84.035 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 84.325 51.595 84.495 51.765 ; + RECT 83.865 51.595 84.035 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 84.325 48.875 84.495 49.045 ; + RECT 83.865 48.875 84.035 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 84.325 46.155 84.495 46.325 ; + RECT 83.865 46.155 84.035 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 84.325 43.435 84.495 43.605 ; + RECT 83.865 43.435 84.035 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 84.325 40.715 84.495 40.885 ; + RECT 83.865 40.715 84.035 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 84.325 37.995 84.495 38.165 ; + RECT 83.865 37.995 84.035 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 84.325 35.275 84.495 35.445 ; + RECT 83.865 35.275 84.035 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 84.325 32.555 84.495 32.725 ; + RECT 83.865 32.555 84.035 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 84.325 29.835 84.495 30.005 ; + RECT 83.865 29.835 84.035 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 84.325 24.395 84.495 24.565 ; + RECT 83.865 24.395 84.035 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 84.325 21.675 84.495 21.845 ; + RECT 83.865 21.675 84.035 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 84.325 18.955 84.495 19.125 ; + RECT 83.865 18.955 84.035 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 84.325 16.235 84.495 16.405 ; + RECT 83.865 16.235 84.035 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 84.325 13.515 84.495 13.685 ; + RECT 83.865 13.515 84.035 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 84.325 8.075 84.495 8.245 ; + RECT 83.865 8.075 84.035 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 84.325 5.355 84.495 5.525 ; + RECT 83.865 5.355 84.035 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 84.325 2.635 84.495 2.805 ; + RECT 83.865 2.635 84.035 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 56.965 108.725 57.115 108.875 ; + RECT 27.525 108.725 27.675 108.875 ; + RECT 30.745 107.025 30.895 107.175 ; + RECT 13.725 107.025 13.875 107.175 ; + RECT 72.145 1.625 72.295 1.775 ; + RECT 62.025 1.625 62.175 1.775 ; + RECT 51.905 1.625 52.055 1.775 ; + RECT 56.965 -0.075 57.115 0.075 ; + RECT 27.525 -0.075 27.675 0.075 ; + LAYER via2 ; + RECT 56.94 108.7 57.14 108.9 ; + RECT 27.5 108.7 27.7 108.9 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via3 ; + RECT 56.94 108.7 57.14 108.9 ; + RECT 27.5 108.7 27.7 108.9 ; + RECT 1.74 3.3 1.94 3.5 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via4 ; + RECT 71.36 105.8 72.16 106.6 ; + RECT 41.92 105.8 42.72 106.6 ; + RECT 12.48 105.8 13.28 106.6 ; + RECT 56.64 2.2 57.44 3 ; + RECT 27.2 2.2 28 3 ; + LAYER fieldpoly ; + RECT 0.14 0.14 84.5 108.66 ; + LAYER diff ; + RECT 0 0 84.64 108.8 ; + LAYER nwell ; + POLYGON 84.83 107.495 84.83 104.665 83.99 104.665 83.99 105.89 80.77 105.89 80.77 107.495 ; + RECT -0.19 104.665 3.87 107.495 ; + POLYGON 84.83 102.055 84.83 99.225 83.99 99.225 83.99 100.45 83.53 100.45 83.53 102.055 ; + RECT -0.19 99.225 3.87 102.055 ; + RECT 83.99 93.785 84.83 96.615 ; + RECT -0.19 93.785 3.87 96.615 ; + RECT 83.99 88.345 84.83 91.175 ; + RECT -0.19 88.345 3.87 91.175 ; + POLYGON 84.83 85.735 84.83 82.905 83.53 82.905 83.53 84.51 83.99 84.51 83.99 85.735 ; + RECT -0.19 82.905 2.03 85.735 ; + RECT 83.53 77.465 84.83 80.295 ; + POLYGON 2.03 80.295 2.03 79.07 3.87 79.07 3.87 77.465 -0.19 77.465 -0.19 80.295 ; + POLYGON 84.83 74.855 84.83 72.025 82.61 72.025 82.61 73.25 80.77 73.25 80.77 74.855 ; + RECT -0.19 72.025 3.87 74.855 ; + POLYGON 84.83 69.415 84.83 66.585 83.53 66.585 83.53 67.81 82.61 67.81 82.61 69.415 ; + RECT -0.19 66.585 3.87 69.415 ; + POLYGON 84.83 63.975 84.83 61.145 83.53 61.145 83.53 62.75 83.99 62.75 83.99 63.975 ; + RECT -0.19 61.145 3.87 63.975 ; + POLYGON 84.83 58.535 84.83 55.705 80.77 55.705 80.77 57.31 83.53 57.31 83.53 58.535 ; + RECT -0.19 55.705 3.87 58.535 ; + POLYGON 84.83 53.095 84.83 50.265 80.77 50.265 80.77 51.87 83.53 51.87 83.53 53.095 ; + RECT -0.19 50.265 3.87 53.095 ; + RECT 80.77 44.825 84.83 47.655 ; + RECT -0.19 44.825 3.87 47.655 ; + RECT 80.77 39.385 84.83 42.215 ; + RECT -0.19 39.385 3.87 42.215 ; + RECT 80.77 33.945 84.83 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + RECT 80.77 28.505 84.83 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + POLYGON 84.83 25.895 84.83 23.065 82.61 23.065 82.61 24.67 83.53 24.67 83.53 25.895 ; + RECT -0.19 23.065 3.87 25.895 ; + POLYGON 84.83 20.455 84.83 17.625 82.61 17.625 82.61 19.23 83.99 19.23 83.99 20.455 ; + RECT -0.19 17.625 3.87 20.455 ; + RECT 83.99 12.185 84.83 15.015 ; + RECT -0.19 12.185 3.87 15.015 ; + POLYGON 84.83 9.575 84.83 6.745 83.53 6.745 83.53 8.35 83.99 8.35 83.99 9.575 ; + RECT -0.19 6.745 3.87 9.575 ; + RECT 80.77 1.305 84.83 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + RECT 0 0 84.64 108.8 ; + LAYER pwell ; + RECT 81.09 108.75 81.31 108.92 ; + RECT 77.41 108.75 77.63 108.92 ; + RECT 73.73 108.75 73.95 108.92 ; + RECT 70.05 108.75 70.27 108.92 ; + RECT 66.37 108.75 66.59 108.92 ; + RECT 62.69 108.75 62.91 108.92 ; + RECT 59.01 108.75 59.23 108.92 ; + RECT 55.33 108.75 55.55 108.92 ; + RECT 51.65 108.75 51.87 108.92 ; + RECT 47.97 108.75 48.19 108.92 ; + RECT 44.29 108.75 44.51 108.92 ; + RECT 40.61 108.75 40.83 108.92 ; + RECT 36.93 108.75 37.15 108.92 ; + RECT 33.25 108.75 33.47 108.92 ; + RECT 29.57 108.75 29.79 108.92 ; + RECT 25.89 108.75 26.11 108.92 ; + RECT 22.21 108.75 22.43 108.92 ; + RECT 18.53 108.75 18.75 108.92 ; + RECT 14.85 108.75 15.07 108.92 ; + RECT 11.17 108.75 11.39 108.92 ; + RECT 7.49 108.75 7.71 108.92 ; + RECT 3.81 108.75 4.03 108.92 ; + RECT 0.13 108.75 0.35 108.92 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + RECT 0 0 84.64 108.8 ; + LAYER OVERLAP ; + POLYGON 0 0 0 108.8 84.64 108.8 84.64 0 ; + END +END cby_0__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef new file mode 100644 index 0000000..8d5341f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -0,0 +1,2057 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 84.64 BY 108.8 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 89.61 1.38 89.91 ; + END + END prog_clk[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 0 32.73 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 0 49.29 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 0 42.85 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.55 0 21.69 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.95 0 40.09 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 0 68.15 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 0 51.13 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 0 35.95 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 0 69.07 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.47 0 22.61 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.35 0 58.49 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.51 0 33.65 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 0 67.23 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 0 50.21 1.36 ; + END + END chany_bottom_in[19] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.67 107.44 54.81 108.8 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.21 107.44 31.35 108.8 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 107.44 23.99 108.8 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.41 107.44 40.55 108.8 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 107.44 68.15 108.8 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.17 107.44 43.31 108.8 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 107.44 46.53 108.8 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.13 107.44 32.27 108.8 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.89 107.44 35.03 108.8 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 107.44 25.83 108.8 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.79 107.44 64.93 108.8 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 107.44 45.61 108.8 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 107.44 52.05 108.8 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.05 107.44 33.19 108.8 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 107.44 69.07 108.8 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.61 107.44 26.75 108.8 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 107.44 35.95 108.8 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.29 107.44 30.43 108.8 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 107.44 44.69 108.8 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.25 107.44 42.39 108.8 ; + END + END chany_top_in[19] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 0 29.05 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 0 53.89 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.39 0 23.53 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 0 31.81 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 0 46.53 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.11 0 38.25 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 0 43.77 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.03 0 39.17 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 0 47.45 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.31 0 24.45 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.89 0 35.03 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.15 0 26.29 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.23 0 25.37 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.87 0 41.01 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 0 52.97 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.05 0 56.19 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END chany_bottom_out[19] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 107.44 53.89 108.8 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.57 107.44 38.71 108.8 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 107.44 52.97 108.8 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 107.44 59.87 108.8 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.73 107.44 36.87 108.8 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 107.44 47.45 108.8 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.71 107.44 65.85 108.8 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 107.44 58.95 108.8 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 107.44 49.29 108.8 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.59 107.44 55.73 108.8 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.97 107.44 34.11 108.8 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.89 107.44 58.03 108.8 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 107.44 51.13 108.8 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.49 107.44 39.63 108.8 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.65 107.44 37.79 108.8 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 107.44 24.91 108.8 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 107.44 48.37 108.8 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.33 107.44 41.47 108.8 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 107.44 29.05 108.8 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 107.44 50.21 108.8 ; + END + END chany_top_out[19] + PIN right_grid_pin_52_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 78.73 84.64 79.03 ; + END + END right_grid_pin_52_[0] + PIN left_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 101.85 1.38 102.15 ; + END + END left_grid_pin_0_[0] + PIN left_grid_pin_1_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 95.05 1.38 95.35 ; + END + END left_grid_pin_1_[0] + PIN left_grid_pin_2_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 97.77 1.38 98.07 ; + END + END left_grid_pin_2_[0] + PIN left_grid_pin_3_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 96.41 1.38 96.71 ; + END + END left_grid_pin_3_[0] + PIN left_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 100.49 1.38 100.79 ; + END + END left_grid_pin_4_[0] + PIN left_grid_pin_5_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 103.21 1.38 103.51 ; + END + END left_grid_pin_5_[0] + PIN left_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 80.09 1.38 80.39 ; + END + END left_grid_pin_6_[0] + PIN left_grid_pin_7_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END left_grid_pin_7_[0] + PIN left_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 76.01 1.38 76.31 ; + END + END left_grid_pin_8_[0] + PIN left_grid_pin_9_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END left_grid_pin_9_[0] + PIN left_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 78.73 1.38 79.03 ; + END + END left_grid_pin_10_[0] + PIN left_grid_pin_11_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 77.37 1.38 77.67 ; + END + END left_grid_pin_11_[0] + PIN left_grid_pin_12_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END left_grid_pin_12_[0] + PIN left_grid_pin_13_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END left_grid_pin_13_[0] + PIN left_grid_pin_14_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END left_grid_pin_14_[0] + PIN left_grid_pin_15_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END left_grid_pin_15_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 99.13 84.64 99.43 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 84.16 2.48 84.64 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 84.16 7.92 84.64 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 84.16 13.36 84.64 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 84.16 18.8 84.64 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 84.16 24.24 84.64 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 84.16 29.68 84.64 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 84.16 35.12 84.64 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 84.16 40.56 84.64 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 84.16 46 84.64 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 84.16 51.44 84.64 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 84.16 56.88 84.64 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 84.16 62.32 84.64 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 84.16 67.76 84.64 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 84.16 73.2 84.64 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 84.16 78.64 84.64 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 84.16 84.08 84.64 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 84.16 89.52 84.64 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 84.16 94.96 84.64 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 84.16 100.4 84.64 100.88 ; + RECT 0 105.84 0.48 106.32 ; + RECT 84.16 105.84 84.64 106.32 ; + LAYER met5 ; + RECT 0 22.2 3.2 25.4 ; + RECT 81.44 22.2 84.64 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 81.44 63 84.64 66.2 ; + RECT 0 103.8 3.2 107 ; + RECT 81.44 103.8 84.64 107 ; + LAYER met4 ; + RECT 12.58 0 13.18 0.6 ; + RECT 42.02 0 42.62 0.6 ; + RECT 71.46 0 72.06 0.6 ; + RECT 12.58 108.2 13.18 108.8 ; + RECT 42.02 108.2 42.62 108.8 ; + RECT 71.46 108.2 72.06 108.8 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 84.64 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 84.16 5.2 84.64 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 84.16 10.64 84.64 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 84.16 16.08 84.64 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 84.16 21.52 84.64 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 84.16 26.96 84.64 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 84.16 32.4 84.64 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 84.16 37.84 84.64 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 84.16 43.28 84.64 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 84.16 48.72 84.64 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 84.16 54.16 84.64 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 84.16 59.6 84.64 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 84.16 65.04 84.64 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 84.16 70.48 84.64 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 84.16 75.92 84.64 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 84.16 81.36 84.64 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 84.16 86.8 84.64 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 84.16 92.24 84.64 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 84.16 97.68 84.64 98.16 ; + RECT 0 103.12 0.48 103.6 ; + RECT 84.16 103.12 84.64 103.6 ; + RECT 0 108.56 84.64 108.8 ; + LAYER met5 ; + RECT 0 1.8 3.2 5 ; + RECT 81.44 1.8 84.64 5 ; + RECT 0 42.6 3.2 45.8 ; + RECT 81.44 42.6 84.64 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 81.44 83.4 84.64 86.6 ; + LAYER met4 ; + RECT 27.3 0 27.9 0.6 ; + RECT 56.74 0 57.34 0.6 ; + RECT 27.3 108.2 27.9 108.8 ; + RECT 56.74 108.2 57.34 108.8 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 108.715 84.64 108.885 ; + RECT 80.96 105.995 84.64 106.165 ; + RECT 0 105.995 3.68 106.165 ; + RECT 83.72 103.275 84.64 103.445 ; + RECT 0 103.275 3.68 103.445 ; + RECT 83.72 100.555 84.64 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 80.96 97.835 84.64 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 80.96 95.115 84.64 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 83.72 92.395 84.64 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 83.72 89.675 84.64 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 83.72 86.955 84.64 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 83.72 84.235 84.64 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 84.18 81.515 84.64 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 84.18 78.795 84.64 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 83.72 76.075 84.64 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 80.96 73.355 84.64 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 80.96 70.635 84.64 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 83.72 67.915 84.64 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 83.72 65.195 84.64 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 84.18 62.475 84.64 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 83.72 59.755 84.64 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 83.72 57.035 84.64 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 84.18 54.315 84.64 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 83.72 51.595 84.64 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 83.72 48.875 84.64 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 83.72 46.155 84.64 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 83.72 43.435 84.64 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 83.72 40.715 84.64 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 80.96 37.995 84.64 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 80.96 35.275 84.64 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 80.96 32.555 84.64 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 83.72 29.835 84.64 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 84.18 27.115 84.64 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 84.18 24.395 84.64 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 82.8 21.675 84.64 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 82.8 18.955 84.64 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 80.96 16.235 84.64 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 80.96 13.515 84.64 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 83.72 10.795 84.64 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 80.96 8.075 84.64 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 80.96 5.355 84.64 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 80.96 2.635 84.64 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 84.64 0.085 ; + LAYER met3 ; + POLYGON 57.205 108.965 57.205 108.96 57.42 108.96 57.42 108.64 57.205 108.64 57.205 108.635 56.875 108.635 56.875 108.64 56.66 108.64 56.66 108.96 56.875 108.96 56.875 108.965 ; + POLYGON 27.765 108.965 27.765 108.96 27.98 108.96 27.98 108.64 27.765 108.64 27.765 108.635 27.435 108.635 27.435 108.64 27.22 108.64 27.22 108.96 27.435 108.96 27.435 108.965 ; + POLYGON 57.205 0.165 57.205 0.16 57.42 0.16 57.42 -0.16 57.205 -0.16 57.205 -0.165 56.875 -0.165 56.875 -0.16 56.66 -0.16 56.66 0.16 56.875 0.16 56.875 0.165 ; + POLYGON 27.765 0.165 27.765 0.16 27.98 0.16 27.98 -0.16 27.765 -0.16 27.765 -0.165 27.435 -0.165 27.435 -0.16 27.22 -0.16 27.22 0.16 27.435 0.16 27.435 0.165 ; + POLYGON 84.24 108.4 84.24 99.83 82.86 99.83 82.86 98.73 84.24 98.73 84.24 79.43 82.86 79.43 82.86 78.33 84.24 78.33 84.24 0.4 0.4 0.4 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 94.65 1.78 94.65 1.78 95.75 0.4 95.75 0.4 96.01 1.78 96.01 1.78 97.11 0.4 97.11 0.4 97.37 1.78 97.37 1.78 98.47 0.4 98.47 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 100.09 1.78 100.09 1.78 101.19 0.4 101.19 0.4 101.45 1.78 101.45 1.78 102.55 0.4 102.55 0.4 102.81 1.78 102.81 1.78 103.91 0.4 103.91 0.4 108.4 ; + LAYER met2 ; + RECT 56.9 108.615 57.18 108.985 ; + RECT 27.46 108.615 27.74 108.985 ; + RECT 51.39 106.94 51.65 107.26 ; + RECT 47.71 106.94 47.97 107.26 ; + RECT 28.39 106.94 28.65 107.26 ; + RECT 52.31 1.54 52.57 1.86 ; + RECT 36.21 1.54 36.47 1.86 ; + RECT 56.9 -0.185 57.18 0.185 ; + RECT 27.46 -0.185 27.74 0.185 ; + POLYGON 84.36 108.52 84.36 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 26.57 0.28 26.57 1.64 25.87 1.64 25.87 0.28 25.65 0.28 25.65 1.64 24.95 1.64 24.95 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 0.28 0.28 0.28 108.52 23.57 108.52 23.57 107.16 24.27 107.16 24.27 108.52 24.49 108.52 24.49 107.16 25.19 107.16 25.19 108.52 25.41 108.52 25.41 107.16 26.11 107.16 26.11 108.52 26.33 108.52 26.33 107.16 27.03 107.16 27.03 108.52 28.63 108.52 28.63 107.16 29.33 107.16 29.33 108.52 30.01 108.52 30.01 107.16 30.71 107.16 30.71 108.52 30.93 108.52 30.93 107.16 31.63 107.16 31.63 108.52 31.85 108.52 31.85 107.16 32.55 107.16 32.55 108.52 32.77 108.52 32.77 107.16 33.47 107.16 33.47 108.52 33.69 108.52 33.69 107.16 34.39 107.16 34.39 108.52 34.61 108.52 34.61 107.16 35.31 107.16 35.31 108.52 35.53 108.52 35.53 107.16 36.23 107.16 36.23 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 37.37 108.52 37.37 107.16 38.07 107.16 38.07 108.52 38.29 108.52 38.29 107.16 38.99 107.16 38.99 108.52 39.21 108.52 39.21 107.16 39.91 107.16 39.91 108.52 40.13 108.52 40.13 107.16 40.83 107.16 40.83 108.52 41.05 108.52 41.05 107.16 41.75 107.16 41.75 108.52 41.97 108.52 41.97 107.16 42.67 107.16 42.67 108.52 42.89 108.52 42.89 107.16 43.59 107.16 43.59 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 52.55 108.52 52.55 107.16 53.25 107.16 53.25 108.52 53.47 108.52 53.47 107.16 54.17 107.16 54.17 108.52 54.39 108.52 54.39 107.16 55.09 107.16 55.09 108.52 55.31 108.52 55.31 107.16 56.01 107.16 56.01 108.52 57.61 108.52 57.61 107.16 58.31 107.16 58.31 108.52 58.53 108.52 58.53 107.16 59.23 107.16 59.23 108.52 59.45 108.52 59.45 107.16 60.15 107.16 60.15 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 67.73 108.52 67.73 107.16 68.43 107.16 68.43 108.52 68.65 108.52 68.65 107.16 69.35 107.16 69.35 108.52 ; + LAYER met4 ; + POLYGON 84.24 108.4 84.24 0.4 72.46 0.4 72.46 1 71.06 1 71.06 0.4 57.74 0.4 57.74 1 56.34 1 56.34 0.4 43.02 0.4 43.02 1 41.62 1 41.62 0.4 28.3 0.4 28.3 1 26.9 1 26.9 0.4 13.58 0.4 13.58 1 12.18 1 12.18 0.4 0.4 0.4 0.4 108.4 12.18 108.4 12.18 107.8 13.58 107.8 13.58 108.4 26.9 108.4 26.9 107.8 28.3 107.8 28.3 108.4 41.62 108.4 41.62 107.8 43.02 107.8 43.02 108.4 56.34 108.4 56.34 107.8 57.74 107.8 57.74 108.4 71.06 108.4 71.06 107.8 72.46 107.8 72.46 108.4 ; + LAYER met5 ; + RECT 6.4 103.8 78.24 107 ; + RECT 6.4 1.8 78.24 5 ; + POLYGON 78.24 105.6 78.24 100.6 81.44 100.6 81.44 89.8 78.24 89.8 78.24 80.2 81.44 80.2 81.44 69.4 78.24 69.4 78.24 59.8 81.44 59.8 81.44 49 78.24 49 78.24 39.4 81.44 39.4 81.44 28.6 78.24 28.6 78.24 19 81.44 19 81.44 8.2 78.24 8.2 78.24 3.2 6.4 3.2 6.4 8.2 3.2 8.2 3.2 19 6.4 19 6.4 28.6 3.2 28.6 3.2 39.4 6.4 39.4 6.4 49 3.2 49 3.2 59.8 6.4 59.8 6.4 69.4 3.2 69.4 3.2 80.2 6.4 80.2 6.4 89.8 3.2 89.8 3.2 100.6 6.4 100.6 6.4 105.6 ; + LAYER met1 ; + POLYGON 84.36 108.28 84.36 106.6 83.88 106.6 83.88 105.56 84.36 105.56 84.36 103.88 83.88 103.88 83.88 102.84 84.36 102.84 84.36 101.16 83.88 101.16 83.88 100.12 84.36 100.12 84.36 98.44 83.88 98.44 83.88 97.4 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 83.88 82.12 83.88 81.08 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; + LAYER li1 ; + RECT 0.34 0.34 84.3 108.46 ; + LAYER mcon ; + RECT 84.325 108.715 84.495 108.885 ; + RECT 83.865 108.715 84.035 108.885 ; + RECT 83.405 108.715 83.575 108.885 ; + RECT 82.945 108.715 83.115 108.885 ; + RECT 82.485 108.715 82.655 108.885 ; + RECT 82.025 108.715 82.195 108.885 ; + RECT 81.565 108.715 81.735 108.885 ; + RECT 81.105 108.715 81.275 108.885 ; + RECT 80.645 108.715 80.815 108.885 ; + RECT 80.185 108.715 80.355 108.885 ; + RECT 79.725 108.715 79.895 108.885 ; + RECT 79.265 108.715 79.435 108.885 ; + RECT 78.805 108.715 78.975 108.885 ; + RECT 78.345 108.715 78.515 108.885 ; + RECT 77.885 108.715 78.055 108.885 ; + RECT 77.425 108.715 77.595 108.885 ; + RECT 76.965 108.715 77.135 108.885 ; + RECT 76.505 108.715 76.675 108.885 ; + RECT 76.045 108.715 76.215 108.885 ; + RECT 75.585 108.715 75.755 108.885 ; + RECT 75.125 108.715 75.295 108.885 ; + RECT 74.665 108.715 74.835 108.885 ; + RECT 74.205 108.715 74.375 108.885 ; + RECT 73.745 108.715 73.915 108.885 ; + RECT 73.285 108.715 73.455 108.885 ; + RECT 72.825 108.715 72.995 108.885 ; + RECT 72.365 108.715 72.535 108.885 ; + RECT 71.905 108.715 72.075 108.885 ; + RECT 71.445 108.715 71.615 108.885 ; + RECT 70.985 108.715 71.155 108.885 ; + RECT 70.525 108.715 70.695 108.885 ; + RECT 70.065 108.715 70.235 108.885 ; + RECT 69.605 108.715 69.775 108.885 ; + RECT 69.145 108.715 69.315 108.885 ; + RECT 68.685 108.715 68.855 108.885 ; + RECT 68.225 108.715 68.395 108.885 ; + RECT 67.765 108.715 67.935 108.885 ; + RECT 67.305 108.715 67.475 108.885 ; + RECT 66.845 108.715 67.015 108.885 ; + RECT 66.385 108.715 66.555 108.885 ; + RECT 65.925 108.715 66.095 108.885 ; + RECT 65.465 108.715 65.635 108.885 ; + RECT 65.005 108.715 65.175 108.885 ; + RECT 64.545 108.715 64.715 108.885 ; + RECT 64.085 108.715 64.255 108.885 ; + RECT 63.625 108.715 63.795 108.885 ; + RECT 63.165 108.715 63.335 108.885 ; + RECT 62.705 108.715 62.875 108.885 ; + RECT 62.245 108.715 62.415 108.885 ; + RECT 61.785 108.715 61.955 108.885 ; + RECT 61.325 108.715 61.495 108.885 ; + RECT 60.865 108.715 61.035 108.885 ; + RECT 60.405 108.715 60.575 108.885 ; + RECT 59.945 108.715 60.115 108.885 ; + RECT 59.485 108.715 59.655 108.885 ; + RECT 59.025 108.715 59.195 108.885 ; + RECT 58.565 108.715 58.735 108.885 ; + RECT 58.105 108.715 58.275 108.885 ; + RECT 57.645 108.715 57.815 108.885 ; + RECT 57.185 108.715 57.355 108.885 ; + RECT 56.725 108.715 56.895 108.885 ; + RECT 56.265 108.715 56.435 108.885 ; + RECT 55.805 108.715 55.975 108.885 ; + RECT 55.345 108.715 55.515 108.885 ; + RECT 54.885 108.715 55.055 108.885 ; + RECT 54.425 108.715 54.595 108.885 ; + RECT 53.965 108.715 54.135 108.885 ; + RECT 53.505 108.715 53.675 108.885 ; + RECT 53.045 108.715 53.215 108.885 ; + RECT 52.585 108.715 52.755 108.885 ; + RECT 52.125 108.715 52.295 108.885 ; + RECT 51.665 108.715 51.835 108.885 ; + RECT 51.205 108.715 51.375 108.885 ; + RECT 50.745 108.715 50.915 108.885 ; + RECT 50.285 108.715 50.455 108.885 ; + RECT 49.825 108.715 49.995 108.885 ; + RECT 49.365 108.715 49.535 108.885 ; + RECT 48.905 108.715 49.075 108.885 ; + RECT 48.445 108.715 48.615 108.885 ; + RECT 47.985 108.715 48.155 108.885 ; + RECT 47.525 108.715 47.695 108.885 ; + RECT 47.065 108.715 47.235 108.885 ; + RECT 46.605 108.715 46.775 108.885 ; + RECT 46.145 108.715 46.315 108.885 ; + RECT 45.685 108.715 45.855 108.885 ; + RECT 45.225 108.715 45.395 108.885 ; + RECT 44.765 108.715 44.935 108.885 ; + RECT 44.305 108.715 44.475 108.885 ; + RECT 43.845 108.715 44.015 108.885 ; + RECT 43.385 108.715 43.555 108.885 ; + RECT 42.925 108.715 43.095 108.885 ; + RECT 42.465 108.715 42.635 108.885 ; + RECT 42.005 108.715 42.175 108.885 ; + RECT 41.545 108.715 41.715 108.885 ; + RECT 41.085 108.715 41.255 108.885 ; + RECT 40.625 108.715 40.795 108.885 ; + RECT 40.165 108.715 40.335 108.885 ; + RECT 39.705 108.715 39.875 108.885 ; + RECT 39.245 108.715 39.415 108.885 ; + RECT 38.785 108.715 38.955 108.885 ; + RECT 38.325 108.715 38.495 108.885 ; + RECT 37.865 108.715 38.035 108.885 ; + RECT 37.405 108.715 37.575 108.885 ; + RECT 36.945 108.715 37.115 108.885 ; + RECT 36.485 108.715 36.655 108.885 ; + RECT 36.025 108.715 36.195 108.885 ; + RECT 35.565 108.715 35.735 108.885 ; + RECT 35.105 108.715 35.275 108.885 ; + RECT 34.645 108.715 34.815 108.885 ; + RECT 34.185 108.715 34.355 108.885 ; + RECT 33.725 108.715 33.895 108.885 ; + RECT 33.265 108.715 33.435 108.885 ; + RECT 32.805 108.715 32.975 108.885 ; + RECT 32.345 108.715 32.515 108.885 ; + RECT 31.885 108.715 32.055 108.885 ; + RECT 31.425 108.715 31.595 108.885 ; + RECT 30.965 108.715 31.135 108.885 ; + RECT 30.505 108.715 30.675 108.885 ; + RECT 30.045 108.715 30.215 108.885 ; + RECT 29.585 108.715 29.755 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 28.205 108.715 28.375 108.885 ; + RECT 27.745 108.715 27.915 108.885 ; + RECT 27.285 108.715 27.455 108.885 ; + RECT 26.825 108.715 26.995 108.885 ; + RECT 26.365 108.715 26.535 108.885 ; + RECT 25.905 108.715 26.075 108.885 ; + RECT 25.445 108.715 25.615 108.885 ; + RECT 24.985 108.715 25.155 108.885 ; + RECT 24.525 108.715 24.695 108.885 ; + RECT 24.065 108.715 24.235 108.885 ; + RECT 23.605 108.715 23.775 108.885 ; + RECT 23.145 108.715 23.315 108.885 ; + RECT 22.685 108.715 22.855 108.885 ; + RECT 22.225 108.715 22.395 108.885 ; + RECT 21.765 108.715 21.935 108.885 ; + RECT 21.305 108.715 21.475 108.885 ; + RECT 20.845 108.715 21.015 108.885 ; + RECT 20.385 108.715 20.555 108.885 ; + RECT 19.925 108.715 20.095 108.885 ; + RECT 19.465 108.715 19.635 108.885 ; + RECT 19.005 108.715 19.175 108.885 ; + RECT 18.545 108.715 18.715 108.885 ; + RECT 18.085 108.715 18.255 108.885 ; + RECT 17.625 108.715 17.795 108.885 ; + RECT 17.165 108.715 17.335 108.885 ; + RECT 16.705 108.715 16.875 108.885 ; + RECT 16.245 108.715 16.415 108.885 ; + RECT 15.785 108.715 15.955 108.885 ; + RECT 15.325 108.715 15.495 108.885 ; + RECT 14.865 108.715 15.035 108.885 ; + RECT 14.405 108.715 14.575 108.885 ; + RECT 13.945 108.715 14.115 108.885 ; + RECT 13.485 108.715 13.655 108.885 ; + RECT 13.025 108.715 13.195 108.885 ; + RECT 12.565 108.715 12.735 108.885 ; + RECT 12.105 108.715 12.275 108.885 ; + RECT 11.645 108.715 11.815 108.885 ; + RECT 11.185 108.715 11.355 108.885 ; + RECT 10.725 108.715 10.895 108.885 ; + RECT 10.265 108.715 10.435 108.885 ; + RECT 9.805 108.715 9.975 108.885 ; + RECT 9.345 108.715 9.515 108.885 ; + RECT 8.885 108.715 9.055 108.885 ; + RECT 8.425 108.715 8.595 108.885 ; + RECT 7.965 108.715 8.135 108.885 ; + RECT 7.505 108.715 7.675 108.885 ; + RECT 7.045 108.715 7.215 108.885 ; + RECT 6.585 108.715 6.755 108.885 ; + RECT 6.125 108.715 6.295 108.885 ; + RECT 5.665 108.715 5.835 108.885 ; + RECT 5.205 108.715 5.375 108.885 ; + RECT 4.745 108.715 4.915 108.885 ; + RECT 4.285 108.715 4.455 108.885 ; + RECT 3.825 108.715 3.995 108.885 ; + RECT 3.365 108.715 3.535 108.885 ; + RECT 2.905 108.715 3.075 108.885 ; + RECT 2.445 108.715 2.615 108.885 ; + RECT 1.985 108.715 2.155 108.885 ; + RECT 1.525 108.715 1.695 108.885 ; + RECT 1.065 108.715 1.235 108.885 ; + RECT 0.605 108.715 0.775 108.885 ; + RECT 0.145 108.715 0.315 108.885 ; + RECT 84.325 105.995 84.495 106.165 ; + RECT 83.865 105.995 84.035 106.165 ; + RECT 0.605 105.995 0.775 106.165 ; + RECT 0.145 105.995 0.315 106.165 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 84.325 100.555 84.495 100.725 ; + RECT 83.865 100.555 84.035 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 84.325 95.115 84.495 95.285 ; + RECT 83.865 95.115 84.035 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 84.325 92.395 84.495 92.565 ; + RECT 83.865 92.395 84.035 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 84.325 89.675 84.495 89.845 ; + RECT 83.865 89.675 84.035 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 84.325 84.235 84.495 84.405 ; + RECT 83.865 84.235 84.035 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 84.325 81.515 84.495 81.685 ; + RECT 83.865 81.515 84.035 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 84.325 78.795 84.495 78.965 ; + RECT 83.865 78.795 84.035 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 84.325 73.355 84.495 73.525 ; + RECT 83.865 73.355 84.035 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 84.325 70.635 84.495 70.805 ; + RECT 83.865 70.635 84.035 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 84.325 67.915 84.495 68.085 ; + RECT 83.865 67.915 84.035 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 84.325 65.195 84.495 65.365 ; + RECT 83.865 65.195 84.035 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 84.325 62.475 84.495 62.645 ; + RECT 83.865 62.475 84.035 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 84.325 59.755 84.495 59.925 ; + RECT 83.865 59.755 84.035 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 84.325 57.035 84.495 57.205 ; + RECT 83.865 57.035 84.035 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 84.325 54.315 84.495 54.485 ; + RECT 83.865 54.315 84.035 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 84.325 51.595 84.495 51.765 ; + RECT 83.865 51.595 84.035 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 84.325 48.875 84.495 49.045 ; + RECT 83.865 48.875 84.035 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 84.325 46.155 84.495 46.325 ; + RECT 83.865 46.155 84.035 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 84.325 43.435 84.495 43.605 ; + RECT 83.865 43.435 84.035 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 84.325 40.715 84.495 40.885 ; + RECT 83.865 40.715 84.035 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 84.325 37.995 84.495 38.165 ; + RECT 83.865 37.995 84.035 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 84.325 35.275 84.495 35.445 ; + RECT 83.865 35.275 84.035 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 84.325 32.555 84.495 32.725 ; + RECT 83.865 32.555 84.035 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 84.325 29.835 84.495 30.005 ; + RECT 83.865 29.835 84.035 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 84.325 24.395 84.495 24.565 ; + RECT 83.865 24.395 84.035 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 84.325 21.675 84.495 21.845 ; + RECT 83.865 21.675 84.035 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 84.325 18.955 84.495 19.125 ; + RECT 83.865 18.955 84.035 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 84.325 16.235 84.495 16.405 ; + RECT 83.865 16.235 84.035 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 84.325 13.515 84.495 13.685 ; + RECT 83.865 13.515 84.035 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 84.325 8.075 84.495 8.245 ; + RECT 83.865 8.075 84.035 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 84.325 5.355 84.495 5.525 ; + RECT 83.865 5.355 84.035 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 84.325 2.635 84.495 2.805 ; + RECT 83.865 2.635 84.035 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 56.965 108.725 57.115 108.875 ; + RECT 27.525 108.725 27.675 108.875 ; + RECT 55.585 107.025 55.735 107.175 ; + RECT 49.145 107.025 49.295 107.175 ; + RECT 26.605 107.025 26.755 107.175 ; + RECT 25.225 1.625 25.375 1.775 ; + RECT 56.965 -0.075 57.115 0.075 ; + RECT 27.525 -0.075 27.675 0.075 ; + LAYER via2 ; + RECT 56.94 108.7 57.14 108.9 ; + RECT 27.5 108.7 27.7 108.9 ; + RECT 1.28 103.26 1.48 103.46 ; + RECT 1.28 100.54 1.48 100.74 ; + RECT 83.16 99.18 83.36 99.38 ; + RECT 1.28 80.14 1.48 80.34 ; + RECT 1.28 78.78 1.48 78.98 ; + RECT 1.28 76.06 1.48 76.26 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via3 ; + RECT 56.94 108.7 57.14 108.9 ; + RECT 27.5 108.7 27.7 108.9 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via4 ; + RECT 71.36 105.8 72.16 106.6 ; + RECT 41.92 105.8 42.72 106.6 ; + RECT 12.48 105.8 13.28 106.6 ; + RECT 56.64 2.2 57.44 3 ; + RECT 27.2 2.2 28 3 ; + LAYER fieldpoly ; + RECT 0.14 0.14 84.5 108.66 ; + LAYER diff ; + RECT 0 0 84.64 108.8 ; + LAYER nwell ; + POLYGON 84.83 107.495 84.83 104.665 83.99 104.665 83.99 105.89 80.77 105.89 80.77 107.495 ; + RECT -0.19 104.665 3.87 107.495 ; + POLYGON 84.83 102.055 84.83 99.225 83.99 99.225 83.99 100.45 83.53 100.45 83.53 102.055 ; + RECT -0.19 99.225 3.87 102.055 ; + POLYGON 84.83 96.615 84.83 93.785 83.99 93.785 83.99 95.01 80.77 95.01 80.77 96.615 ; + POLYGON 2.03 96.615 2.03 95.39 3.87 95.39 3.87 93.785 -0.19 93.785 -0.19 96.615 ; + POLYGON 84.83 91.175 84.83 88.345 83.99 88.345 83.99 89.57 83.53 89.57 83.53 91.175 ; + POLYGON 3.87 91.175 3.87 89.57 2.03 89.57 2.03 88.345 -0.19 88.345 -0.19 91.175 ; + POLYGON 84.83 85.735 84.83 82.905 83.99 82.905 83.99 84.13 83.53 84.13 83.53 85.735 ; + POLYGON 3.87 85.735 3.87 84.13 2.03 84.13 2.03 82.905 -0.19 82.905 -0.19 85.735 ; + RECT 83.99 77.465 84.83 80.295 ; + POLYGON 2.03 80.295 2.03 79.07 3.87 79.07 3.87 77.465 -0.19 77.465 -0.19 80.295 ; + POLYGON 84.83 74.855 84.83 72.025 80.77 72.025 80.77 73.63 83.53 73.63 83.53 74.855 ; + POLYGON 2.03 74.855 2.03 73.63 3.87 73.63 3.87 72.025 -0.19 72.025 -0.19 74.855 ; + POLYGON 84.83 69.415 84.83 66.585 83.53 66.585 83.53 68.19 83.99 68.19 83.99 69.415 ; + POLYGON 2.03 69.415 2.03 68.19 3.87 68.19 3.87 66.585 -0.19 66.585 -0.19 69.415 ; + RECT 83.99 61.145 84.83 63.975 ; + RECT -0.19 61.145 2.03 63.975 ; + POLYGON 84.83 58.535 84.83 55.705 83.99 55.705 83.99 56.93 83.53 56.93 83.53 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + POLYGON 84.83 53.095 84.83 50.265 83.53 50.265 83.53 51.87 83.99 51.87 83.99 53.095 ; + POLYGON 3.87 53.095 3.87 51.49 2.03 51.49 2.03 50.265 -0.19 50.265 -0.19 53.095 ; + POLYGON 84.83 47.655 84.83 44.825 83.53 44.825 83.53 46.43 83.99 46.43 83.99 47.655 ; + POLYGON 3.87 47.655 3.87 46.05 2.03 46.05 2.03 44.825 -0.19 44.825 -0.19 47.655 ; + POLYGON 84.83 42.215 84.83 39.385 83.53 39.385 83.53 40.99 83.99 40.99 83.99 42.215 ; + RECT -0.19 39.385 3.87 42.215 ; + RECT 80.77 33.945 84.83 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + POLYGON 84.83 31.335 84.83 28.505 83.99 28.505 83.99 29.73 83.53 29.73 83.53 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + RECT 83.99 23.065 84.83 25.895 ; + RECT -0.19 23.065 3.87 25.895 ; + POLYGON 84.83 20.455 84.83 17.625 83.53 17.625 83.53 18.85 82.61 18.85 82.61 20.455 ; + RECT -0.19 17.625 3.87 20.455 ; + POLYGON 84.83 15.015 84.83 12.185 83.99 12.185 83.99 13.41 80.77 13.41 80.77 15.015 ; + RECT -0.19 12.185 3.87 15.015 ; + POLYGON 84.83 9.575 84.83 6.745 80.77 6.745 80.77 8.35 83.53 8.35 83.53 9.575 ; + RECT -0.19 6.745 3.87 9.575 ; + POLYGON 84.83 4.135 84.83 1.305 80.77 1.305 80.77 2.91 83.53 2.91 83.53 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + RECT 0 0 84.64 108.8 ; + LAYER pwell ; + RECT 81.09 108.75 81.31 108.92 ; + RECT 77.41 108.75 77.63 108.92 ; + RECT 73.73 108.75 73.95 108.92 ; + RECT 70.05 108.75 70.27 108.92 ; + RECT 66.37 108.75 66.59 108.92 ; + RECT 62.69 108.75 62.91 108.92 ; + RECT 59.01 108.75 59.23 108.92 ; + RECT 55.33 108.75 55.55 108.92 ; + RECT 51.65 108.75 51.87 108.92 ; + RECT 47.97 108.75 48.19 108.92 ; + RECT 44.29 108.75 44.51 108.92 ; + RECT 40.61 108.75 40.83 108.92 ; + RECT 36.93 108.75 37.15 108.92 ; + RECT 33.25 108.75 33.47 108.92 ; + RECT 29.57 108.75 29.79 108.92 ; + RECT 25.89 108.75 26.11 108.92 ; + RECT 22.21 108.75 22.43 108.92 ; + RECT 18.53 108.75 18.75 108.92 ; + RECT 14.85 108.75 15.07 108.92 ; + RECT 11.17 108.75 11.39 108.92 ; + RECT 7.49 108.75 7.71 108.92 ; + RECT 3.81 108.75 4.03 108.92 ; + RECT 0.13 108.75 0.35 108.92 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + RECT 0 0 84.64 108.8 ; + LAYER OVERLAP ; + POLYGON 0 0 0 108.8 84.64 108.8 84.64 0 ; + END +END cby_1__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef new file mode 100644 index 0000000..cb61603 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -0,0 +1,2296 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 14.65 102 14.79 103.36 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 102 67.69 103.36 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 102 62.17 103.36 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 102 70.45 103.36 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 102 45.61 103.36 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 102 43.77 103.36 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 102 29.05 103.36 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 102 69.53 103.36 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 102 68.61 103.36 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.95 102 63.09 103.36 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 102 52.05 103.36 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 102 50.21 103.36 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 102 41.93 103.36 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 102 72.29 103.36 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 20.09 102 20.39 103.36 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 29.29 102 29.59 103.36 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 102 49.83 103.36 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.73 102 59.03 103.36 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 14.57 102 14.87 103.36 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 44.01 102 44.31 103.36 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 102 47.45 103.36 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 102 2.37 103.36 ; + END + END top_left_grid_pin_1_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 46.09 113.16 46.39 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 16.17 113.16 16.47 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 12.09 113.16 12.39 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 8.01 113.16 8.31 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 13.45 113.16 13.75 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 9.37 113.16 9.67 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 31.13 113.16 31.43 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 47.45 113.16 47.75 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 14.81 113.16 15.11 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 71.93 113.16 72.23 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 25.69 113.16 25.99 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 29.77 113.16 30.07 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 18.89 113.16 19.19 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 44.73 113.16 45.03 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 17.53 113.16 17.83 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 42.01 113.16 42.31 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 3.93 113.16 4.23 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 63.77 113.16 64.07 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 50.17 113.16 50.47 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 58.33 113.16 58.63 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 109.87 74.8 110.01 76.16 ; + END + END right_top_grid_pin_42_[0] + PIN right_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 99.13 84.64 99.43 ; + END + END right_top_grid_pin_43_[0] + PIN right_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 74.8 110.93 76.16 ; + END + END right_top_grid_pin_44_[0] + PIN right_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.95 74.8 109.09 76.16 ; + END + END right_top_grid_pin_45_[0] + PIN right_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 91.65 84.64 91.95 ; + END + END right_top_grid_pin_46_[0] + PIN right_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 90.29 84.64 90.59 ; + END + END right_top_grid_pin_47_[0] + PIN right_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 107.11 74.8 107.25 76.16 ; + END + END right_top_grid_pin_48_[0] + PIN right_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.03 74.8 108.17 76.16 ; + END + END right_top_grid_pin_49_[0] + PIN right_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 109.87 0 110.01 1.36 ; + END + END right_bottom_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 0 110.93 1.36 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 102 42.85 103.36 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 102 25.83 103.36 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 102 71.37 103.36 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 102 49.29 103.36 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.27 102 36.41 103.36 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 102 44.69 103.36 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 5.37 102 5.67 103.36 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.85 102 69.15 103.36 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.93 102 22.23 103.36 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 9.05 102 9.35 103.36 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 102 46.53 103.36 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 102 51.13 103.36 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 102 7.43 103.36 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 102 24.07 103.36 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 7.21 102 7.51 103.36 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 102 46.15 103.36 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 102 48.37 103.36 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 102 52.97 103.36 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 102 47.99 103.36 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 102 25.91 103.36 ; + END + END chany_top_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 59.69 113.16 59.99 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 66.49 113.16 66.79 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 6.65 113.16 6.95 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 67.85 113.16 68.15 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 35.21 113.16 35.51 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 56.97 113.16 57.27 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 28.41 113.16 28.71 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 51.53 113.16 51.83 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 33.85 113.16 34.15 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 40.65 113.16 40.95 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 24.33 113.16 24.63 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 55.61 113.16 55.91 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 69.21 113.16 69.51 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 61.05 113.16 61.35 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 22.97 113.16 23.27 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 39.29 113.16 39.59 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 36.57 113.16 36.87 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 62.41 113.16 62.71 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 20.25 113.16 20.55 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 52.89 113.16 53.19 ; + END + END chanx_right_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 68.53 1.38 68.83 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 84.16 78.64 84.64 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 84.16 84.08 84.64 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 84.16 89.52 84.64 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 84.16 94.96 84.64 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 84.16 100.4 84.64 100.88 ; + LAYER met4 ; + RECT 12.58 0 13.18 0.6 ; + RECT 42.02 0 42.62 0.6 ; + RECT 71.46 0 72.06 0.6 ; + RECT 106.42 0 107.02 0.6 ; + RECT 106.42 75.56 107.02 76.16 ; + RECT 12.58 102.76 13.18 103.36 ; + RECT 42.02 102.76 42.62 103.36 ; + RECT 71.46 102.76 72.06 103.36 ; + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 109.96 16.08 113.16 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 109.96 56.88 113.16 60.08 ; + RECT 0 95.64 3.2 98.84 ; + RECT 81.44 95.64 84.64 98.84 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 113.16 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 112.68 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 113.16 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 84.16 81.36 84.64 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 84.16 86.8 84.64 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 84.16 92.24 84.64 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 84.16 97.68 84.64 98.16 ; + RECT 0 103.12 84.64 103.36 ; + LAYER met4 ; + RECT 27.3 0 27.9 0.6 ; + RECT 56.74 0 57.34 0.6 ; + RECT 27.3 102.76 27.9 103.36 ; + RECT 56.74 102.76 57.34 103.36 ; + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 109.96 36.48 113.16 39.68 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 103.275 84.64 103.445 ; + RECT 80.96 100.555 84.64 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 83.72 97.835 84.64 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 80.96 95.115 84.64 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 80.96 92.395 84.64 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 84.18 89.675 84.64 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 84.18 86.955 84.64 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 84.18 84.235 84.64 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 83.72 81.515 84.64 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 80.96 78.795 84.64 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 80.96 76.075 113.16 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 111.32 73.355 113.16 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 112.24 70.635 113.16 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 112.24 67.915 113.16 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 112.24 65.195 113.16 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 112.24 62.475 113.16 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 112.24 59.755 113.16 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 112.24 57.035 113.16 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 112.24 54.315 113.16 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 112.24 51.595 113.16 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 111.32 48.875 113.16 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 111.32 46.155 113.16 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 112.24 43.435 113.16 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 112.24 40.715 113.16 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 112.24 37.995 113.16 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 111.32 35.275 113.16 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 111.32 32.555 113.16 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 112.24 29.835 113.16 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 112.24 27.115 113.16 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 112.24 24.395 113.16 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 112.24 21.675 113.16 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 112.24 18.955 113.16 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 112.24 16.235 113.16 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 112.24 13.515 113.16 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 112.24 10.795 113.16 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 112.24 8.075 113.16 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 112.24 5.355 113.16 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 112.24 2.635 113.16 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 113.16 0.085 ; + LAYER met2 ; + RECT 56.9 103.175 57.18 103.545 ; + RECT 27.46 103.175 27.74 103.545 ; + RECT 45.87 101.5 46.13 101.82 ; + RECT 56.9 -0.185 57.18 0.185 ; + RECT 27.46 -0.185 27.74 0.185 ; + POLYGON 84.36 103.08 84.36 75.88 106.83 75.88 106.83 74.52 107.53 74.52 107.53 75.88 107.75 75.88 107.75 74.52 108.45 74.52 108.45 75.88 108.67 75.88 108.67 74.52 109.37 74.52 109.37 75.88 109.59 75.88 109.59 74.52 110.29 74.52 110.29 75.88 110.51 75.88 110.51 74.52 111.21 74.52 111.21 75.88 112.88 75.88 112.88 0.28 111.21 0.28 111.21 1.64 110.51 1.64 110.51 0.28 110.29 0.28 110.29 1.64 109.59 1.64 109.59 0.28 0.28 0.28 0.28 103.08 1.95 103.08 1.95 101.72 2.65 101.72 2.65 103.08 7.01 103.08 7.01 101.72 7.71 101.72 7.71 103.08 14.37 103.08 14.37 101.72 15.07 101.72 15.07 103.08 25.41 103.08 25.41 101.72 26.11 101.72 26.11 103.08 28.63 103.08 28.63 101.72 29.33 101.72 29.33 103.08 35.99 103.08 35.99 101.72 36.69 101.72 36.69 103.08 41.51 103.08 41.51 101.72 42.21 101.72 42.21 103.08 42.43 103.08 42.43 101.72 43.13 101.72 43.13 103.08 43.35 103.08 43.35 101.72 44.05 101.72 44.05 103.08 44.27 103.08 44.27 101.72 44.97 101.72 44.97 103.08 45.19 103.08 45.19 101.72 45.89 101.72 45.89 103.08 46.11 103.08 46.11 101.72 46.81 101.72 46.81 103.08 47.03 103.08 47.03 101.72 47.73 101.72 47.73 103.08 47.95 103.08 47.95 101.72 48.65 101.72 48.65 103.08 48.87 103.08 48.87 101.72 49.57 101.72 49.57 103.08 49.79 103.08 49.79 101.72 50.49 101.72 50.49 103.08 50.71 103.08 50.71 101.72 51.41 101.72 51.41 103.08 51.63 103.08 51.63 101.72 52.33 101.72 52.33 103.08 52.55 103.08 52.55 101.72 53.25 101.72 53.25 103.08 61.75 103.08 61.75 101.72 62.45 101.72 62.45 103.08 62.67 103.08 62.67 101.72 63.37 101.72 63.37 103.08 67.27 103.08 67.27 101.72 67.97 101.72 67.97 103.08 68.19 103.08 68.19 101.72 68.89 101.72 68.89 103.08 69.11 103.08 69.11 101.72 69.81 101.72 69.81 103.08 70.03 103.08 70.03 101.72 70.73 101.72 70.73 103.08 70.95 103.08 70.95 101.72 71.65 101.72 71.65 103.08 71.87 103.08 71.87 101.72 72.57 101.72 72.57 103.08 ; + LAYER met4 ; + POLYGON 84.24 102.96 84.24 75.76 106.02 75.76 106.02 75.16 107.42 75.16 107.42 75.76 112.76 75.76 112.76 0.4 107.42 0.4 107.42 1 106.02 1 106.02 0.4 72.46 0.4 72.46 1 71.06 1 71.06 0.4 57.74 0.4 57.74 1 56.34 1 56.34 0.4 43.02 0.4 43.02 1 41.62 1 41.62 0.4 28.3 0.4 28.3 1 26.9 1 26.9 0.4 13.58 0.4 13.58 1 12.18 1 12.18 0.4 0.4 0.4 0.4 102.96 4.97 102.96 4.97 101.6 6.07 101.6 6.07 102.96 6.81 102.96 6.81 101.6 7.91 101.6 7.91 102.96 8.65 102.96 8.65 101.6 9.75 101.6 9.75 102.96 12.18 102.96 12.18 102.36 13.58 102.36 13.58 102.96 14.17 102.96 14.17 101.6 15.27 101.6 15.27 102.96 19.69 102.96 19.69 101.6 20.79 101.6 20.79 102.96 21.53 102.96 21.53 101.6 22.63 101.6 22.63 102.96 23.37 102.96 23.37 101.6 24.47 101.6 24.47 102.96 25.21 102.96 25.21 101.6 26.31 101.6 26.31 102.96 26.9 102.96 26.9 102.36 28.3 102.36 28.3 102.96 28.89 102.96 28.89 101.6 29.99 101.6 29.99 102.96 41.62 102.96 41.62 102.36 43.02 102.36 43.02 102.96 43.61 102.96 43.61 101.6 44.71 101.6 44.71 102.96 45.45 102.96 45.45 101.6 46.55 101.6 46.55 102.96 47.29 102.96 47.29 101.6 48.39 101.6 48.39 102.96 49.13 102.96 49.13 101.6 50.23 101.6 50.23 102.96 56.34 102.96 56.34 102.36 57.74 102.36 57.74 102.96 58.33 102.96 58.33 101.6 59.43 101.6 59.43 102.96 68.45 102.96 68.45 101.6 69.55 101.6 69.55 102.96 71.06 102.96 71.06 102.36 72.46 102.36 72.46 102.96 ; + LAYER met3 ; + POLYGON 57.205 103.525 57.205 103.52 57.42 103.52 57.42 103.2 57.205 103.2 57.205 103.195 56.875 103.195 56.875 103.2 56.66 103.2 56.66 103.52 56.875 103.52 56.875 103.525 ; + POLYGON 27.765 103.525 27.765 103.52 27.98 103.52 27.98 103.2 27.765 103.2 27.765 103.195 27.435 103.195 27.435 103.2 27.22 103.2 27.22 103.52 27.435 103.52 27.435 103.525 ; + POLYGON 111.485 37.565 111.485 37.235 111.155 37.235 111.155 37.25 106.11 37.25 106.11 37.55 111.155 37.55 111.155 37.565 ; + POLYGON 57.205 0.165 57.205 0.16 57.42 0.16 57.42 -0.16 57.205 -0.16 57.205 -0.165 56.875 -0.165 56.875 -0.16 56.66 -0.16 56.66 0.16 56.875 0.16 56.875 0.165 ; + POLYGON 27.765 0.165 27.765 0.16 27.98 0.16 27.98 -0.16 27.765 -0.16 27.765 -0.165 27.435 -0.165 27.435 -0.16 27.22 -0.16 27.22 0.16 27.435 0.16 27.435 0.165 ; + POLYGON 84.24 102.96 84.24 99.83 82.86 99.83 82.86 98.73 84.24 98.73 84.24 92.35 82.86 92.35 82.86 91.25 84.24 91.25 84.24 90.99 82.86 90.99 82.86 89.89 84.24 89.89 84.24 75.76 112.76 75.76 112.76 72.63 111.38 72.63 111.38 71.53 112.76 71.53 112.76 69.91 111.38 69.91 111.38 68.81 112.76 68.81 112.76 68.55 111.38 68.55 111.38 67.45 112.76 67.45 112.76 67.19 111.38 67.19 111.38 66.09 112.76 66.09 112.76 64.47 111.38 64.47 111.38 63.37 112.76 63.37 112.76 63.11 111.38 63.11 111.38 62.01 112.76 62.01 112.76 61.75 111.38 61.75 111.38 60.65 112.76 60.65 112.76 60.39 111.38 60.39 111.38 59.29 112.76 59.29 112.76 59.03 111.38 59.03 111.38 57.93 112.76 57.93 112.76 57.67 111.38 57.67 111.38 56.57 112.76 56.57 112.76 56.31 111.38 56.31 111.38 55.21 112.76 55.21 112.76 53.59 111.38 53.59 111.38 52.49 112.76 52.49 112.76 52.23 111.38 52.23 111.38 51.13 112.76 51.13 112.76 50.87 111.38 50.87 111.38 49.77 112.76 49.77 112.76 48.15 111.38 48.15 111.38 47.05 112.76 47.05 112.76 46.79 111.38 46.79 111.38 45.69 112.76 45.69 112.76 45.43 111.38 45.43 111.38 44.33 112.76 44.33 112.76 42.71 111.38 42.71 111.38 41.61 112.76 41.61 112.76 41.35 111.38 41.35 111.38 40.25 112.76 40.25 112.76 39.99 111.38 39.99 111.38 38.89 112.76 38.89 112.76 37.27 111.38 37.27 111.38 36.17 112.76 36.17 112.76 35.91 111.38 35.91 111.38 34.81 112.76 34.81 112.76 34.55 111.38 34.55 111.38 33.45 112.76 33.45 112.76 31.83 111.38 31.83 111.38 30.73 112.76 30.73 112.76 30.47 111.38 30.47 111.38 29.37 112.76 29.37 112.76 29.11 111.38 29.11 111.38 28.01 112.76 28.01 112.76 26.39 111.38 26.39 111.38 25.29 112.76 25.29 112.76 25.03 111.38 25.03 111.38 23.93 112.76 23.93 112.76 23.67 111.38 23.67 111.38 22.57 112.76 22.57 112.76 20.95 111.38 20.95 111.38 19.85 112.76 19.85 112.76 19.59 111.38 19.59 111.38 18.49 112.76 18.49 112.76 18.23 111.38 18.23 111.38 17.13 112.76 17.13 112.76 16.87 111.38 16.87 111.38 15.77 112.76 15.77 112.76 15.51 111.38 15.51 111.38 14.41 112.76 14.41 112.76 14.15 111.38 14.15 111.38 13.05 112.76 13.05 112.76 12.79 111.38 12.79 111.38 11.69 112.76 11.69 112.76 10.07 111.38 10.07 111.38 8.97 112.76 8.97 112.76 8.71 111.38 8.71 111.38 7.61 112.76 7.61 112.76 7.35 111.38 7.35 111.38 6.25 112.76 6.25 112.76 4.63 111.38 4.63 111.38 3.53 112.76 3.53 112.76 0.4 0.4 0.4 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 102.96 ; + LAYER met5 ; + POLYGON 78.24 100.16 78.24 92.44 81.44 92.44 81.44 72.96 109.96 72.96 109.96 63.28 106.76 63.28 106.76 53.68 109.96 53.68 109.96 42.88 106.76 42.88 106.76 33.28 109.96 33.28 109.96 22.48 106.76 22.48 106.76 12.88 109.96 12.88 109.96 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 92.44 6.4 92.44 6.4 100.16 ; + LAYER met1 ; + POLYGON 84.36 102.84 84.36 101.16 83.88 101.16 83.88 100.12 84.36 100.12 84.36 98.44 83.88 98.44 83.88 97.4 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 83.88 82.12 83.88 81.08 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 112.4 27.72 112.4 26.68 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER li1 ; + POLYGON 84.3 103.02 84.3 75.82 112.82 75.82 112.82 0.34 0.34 0.34 0.34 103.02 ; + LAYER mcon ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 84.325 100.555 84.495 100.725 ; + RECT 83.865 100.555 84.035 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 84.325 95.115 84.495 95.285 ; + RECT 83.865 95.115 84.035 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 84.325 92.395 84.495 92.565 ; + RECT 83.865 92.395 84.035 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 84.325 89.675 84.495 89.845 ; + RECT 83.865 89.675 84.035 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 84.325 84.235 84.495 84.405 ; + RECT 83.865 84.235 84.035 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 84.325 81.515 84.495 81.685 ; + RECT 83.865 81.515 84.035 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 84.325 78.795 84.495 78.965 ; + RECT 83.865 78.795 84.035 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 111.925 76.075 112.095 76.245 ; + RECT 111.465 76.075 111.635 76.245 ; + RECT 111.005 76.075 111.175 76.245 ; + RECT 110.545 76.075 110.715 76.245 ; + RECT 110.085 76.075 110.255 76.245 ; + RECT 109.625 76.075 109.795 76.245 ; + RECT 109.165 76.075 109.335 76.245 ; + RECT 108.705 76.075 108.875 76.245 ; + RECT 108.245 76.075 108.415 76.245 ; + RECT 107.785 76.075 107.955 76.245 ; + RECT 107.325 76.075 107.495 76.245 ; + RECT 106.865 76.075 107.035 76.245 ; + RECT 106.405 76.075 106.575 76.245 ; + RECT 105.945 76.075 106.115 76.245 ; + RECT 105.485 76.075 105.655 76.245 ; + RECT 105.025 76.075 105.195 76.245 ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 56.965 103.285 57.115 103.435 ; + RECT 27.525 103.285 27.675 103.435 ; + RECT 62.025 101.585 62.175 101.735 ; + RECT 48.225 101.585 48.375 101.735 ; + RECT 56.965 76.085 57.115 76.235 ; + RECT 27.525 76.085 27.675 76.235 ; + RECT 108.025 74.385 108.175 74.535 ; + RECT 109.865 1.625 110.015 1.775 ; + RECT 56.965 -0.075 57.115 0.075 ; + RECT 27.525 -0.075 27.675 0.075 ; + LAYER via2 ; + RECT 56.94 103.26 57.14 103.46 ; + RECT 27.5 103.26 27.7 103.46 ; + RECT 111.22 66.54 111.42 66.74 ; + RECT 111.22 40.7 111.42 40.9 ; + RECT 111.68 36.62 111.88 36.82 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via3 ; + RECT 56.94 103.26 57.14 103.46 ; + RECT 27.5 103.26 27.7 103.46 ; + RECT 82.7 91.7 82.9 91.9 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via4 ; + RECT 106.32 58.88 107.12 59.68 ; + RECT 106.32 57.28 107.12 58.08 ; + RECT 106.32 18.08 107.12 18.88 ; + RECT 106.32 16.48 107.12 17.28 ; + LAYER fieldpoly ; + POLYGON 84.5 103.22 84.5 76.02 113.02 76.02 113.02 0.14 0.14 0.14 0.14 103.22 ; + LAYER diff ; + POLYGON 84.64 103.36 84.64 76.16 113.16 76.16 113.16 0 0 0 0 103.36 ; + LAYER nwell ; + POLYGON 84.83 102.055 84.83 99.225 83.53 99.225 83.53 100.45 80.77 100.45 80.77 102.055 ; + RECT -0.19 99.225 3.87 102.055 ; + POLYGON 84.83 96.615 84.83 93.785 80.77 93.785 80.77 95.39 83.53 95.39 83.53 96.615 ; + RECT -0.19 93.785 3.87 96.615 ; + RECT 83.99 88.345 84.83 91.175 ; + RECT -0.19 88.345 3.87 91.175 ; + RECT 83.99 82.905 84.83 85.735 ; + RECT -0.19 82.905 3.87 85.735 ; + POLYGON 84.83 80.295 84.83 77.465 80.77 77.465 80.77 79.07 83.53 79.07 83.53 80.295 ; + RECT -0.19 77.465 3.87 80.295 ; + POLYGON 113.35 74.855 113.35 72.025 112.51 72.025 112.51 73.25 111.13 73.25 111.13 74.855 ; + RECT -0.19 72.025 3.87 74.855 ; + RECT 112.05 66.585 113.35 69.415 ; + POLYGON 2.03 69.415 2.03 68.19 3.87 68.19 3.87 66.585 -0.19 66.585 -0.19 69.415 ; + POLYGON 113.35 63.975 113.35 61.145 112.51 61.145 112.51 62.37 112.05 62.37 112.05 63.975 ; + RECT -0.19 61.145 3.87 63.975 ; + RECT 112.05 55.705 113.35 58.535 ; + RECT -0.19 55.705 3.87 58.535 ; + RECT 112.05 50.265 113.35 53.095 ; + RECT -0.19 50.265 3.87 53.095 ; + POLYGON 113.35 47.655 113.35 44.825 112.05 44.825 112.05 46.05 111.13 46.05 111.13 47.655 ; + RECT -0.19 44.825 3.87 47.655 ; + RECT 112.05 39.385 113.35 42.215 ; + RECT -0.19 39.385 3.87 42.215 ; + POLYGON 113.35 36.775 113.35 33.945 111.13 33.945 111.13 35.55 112.05 35.55 112.05 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + RECT 112.05 28.505 113.35 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + RECT 112.05 23.065 113.35 25.895 ; + RECT -0.19 23.065 3.87 25.895 ; + RECT 112.05 17.625 113.35 20.455 ; + RECT -0.19 17.625 3.87 20.455 ; + RECT 112.05 12.185 113.35 15.015 ; + RECT -0.19 12.185 3.87 15.015 ; + RECT 112.05 6.745 113.35 9.575 ; + RECT -0.19 6.745 3.87 9.575 ; + RECT 112.05 1.305 113.35 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + POLYGON 84.64 103.36 84.64 76.16 113.16 76.16 113.16 0 0 0 0 103.36 ; + LAYER pwell ; + RECT 81.09 103.31 81.31 103.48 ; + RECT 77.41 103.31 77.63 103.48 ; + RECT 73.73 103.31 73.95 103.48 ; + RECT 70.05 103.31 70.27 103.48 ; + RECT 66.37 103.31 66.59 103.48 ; + RECT 62.69 103.31 62.91 103.48 ; + RECT 59.01 103.31 59.23 103.48 ; + RECT 55.33 103.31 55.55 103.48 ; + RECT 51.65 103.31 51.87 103.48 ; + RECT 47.97 103.31 48.19 103.48 ; + RECT 44.29 103.31 44.51 103.48 ; + RECT 40.61 103.31 40.83 103.48 ; + RECT 36.93 103.31 37.15 103.48 ; + RECT 33.25 103.31 33.47 103.48 ; + RECT 29.57 103.31 29.79 103.48 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 107.77 76.11 107.99 76.28 ; + RECT 104.09 76.11 104.31 76.28 ; + RECT 100.41 76.11 100.63 76.28 ; + RECT 96.73 76.11 96.95 76.28 ; + RECT 93.05 76.11 93.27 76.28 ; + RECT 89.37 76.11 89.59 76.28 ; + RECT 85.69 76.11 85.91 76.28 ; + RECT 111.495 76.1 111.605 76.22 ; + RECT 112.395 -0.05 112.555 0.06 ; + RECT 110.575 -0.06 110.685 0.06 ; + RECT 106.85 -0.12 107.07 0.05 ; + RECT 103.17 -0.12 103.39 0.05 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + POLYGON 84.64 103.36 84.64 76.16 113.16 76.16 113.16 0 0 0 0 103.36 ; + LAYER OVERLAP ; + POLYGON 0 0 0 103.36 84.64 103.36 84.64 76.16 113.16 76.16 113.16 0 ; + END +END sb_0__0_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef new file mode 100644 index 0000000..0f94742 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -0,0 +1,2892 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 130.56 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 59.01 1.38 59.31 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 129.2 67.69 130.56 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 129.2 62.17 130.56 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 129.2 70.45 130.56 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 129.2 45.61 130.56 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 129.2 43.77 130.56 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.91 129.2 29.05 130.56 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 129.2 69.53 130.56 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 129.2 68.61 130.56 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.95 129.2 63.09 130.56 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 129.2 52.05 130.56 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 129.2 50.21 130.56 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 129.2 41.93 130.56 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 129.2 72.29 130.56 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 20.09 129.2 20.39 130.56 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 29.29 129.2 29.59 130.56 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 129.2 49.83 130.56 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.73 129.2 59.03 130.56 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 14.57 129.2 14.87 130.56 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 44.01 129.2 44.31 130.56 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 129.2 47.45 130.56 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 129.2 2.37 130.56 ; + END + END top_left_grid_pin_1_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 48.81 113.16 49.11 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 99.13 113.16 99.43 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 55.61 113.16 55.91 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 43.37 113.16 43.67 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 93.69 113.16 93.99 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 95.05 113.16 95.35 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 77.37 113.16 77.67 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 69.21 113.16 69.51 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 44.73 113.16 45.03 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 50.85 113.16 51.15 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 36.57 113.16 36.87 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 37.93 113.16 38.23 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 96.41 113.16 96.71 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 32.49 113.16 32.79 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 90.97 113.16 91.27 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 56.97 113.16 57.27 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 39.29 113.16 39.59 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 33.85 113.16 34.15 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 65.13 113.16 65.43 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 31.13 113.16 31.43 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 109.87 102 110.01 103.36 ; + END + END right_top_grid_pin_42_[0] + PIN right_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 126.33 84.64 126.63 ; + END + END right_top_grid_pin_43_[0] + PIN right_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 102 110.93 103.36 ; + END + END right_top_grid_pin_44_[0] + PIN right_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.95 102 109.09 103.36 ; + END + END right_top_grid_pin_45_[0] + PIN right_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 118.85 84.64 119.15 ; + END + END right_top_grid_pin_46_[0] + PIN right_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 83.26 117.49 84.64 117.79 ; + END + END right_top_grid_pin_47_[0] + PIN right_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 107.11 102 107.25 103.36 ; + END + END right_top_grid_pin_48_[0] + PIN right_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.03 102 108.17 103.36 ; + END + END right_top_grid_pin_49_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.71 0 65.85 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.65 0 14.79 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 0 71.37 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.73 0 13.87 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 0 49.29 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 0 52.97 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 0 22.15 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 0 23.99 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 0 23.07 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.87 0 64.01 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 0 72.29 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 0 43.77 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 0 46.53 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 0 24.91 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END bottom_left_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 88.25 113.16 88.55 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 129.2 42.85 130.56 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 129.2 25.83 130.56 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 129.2 71.37 130.56 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 129.2 49.29 130.56 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.27 129.2 36.41 130.56 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 129.2 44.69 130.56 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 5.37 129.2 5.67 130.56 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.85 129.2 69.15 130.56 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.93 129.2 22.23 130.56 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 9.05 129.2 9.35 130.56 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 129.2 46.53 130.56 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 129.2 51.13 130.56 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 129.2 7.43 130.56 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 129.2 24.07 130.56 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 7.21 129.2 7.51 130.56 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 129.2 46.15 130.56 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 129.2 48.37 130.56 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 129.2 52.97 130.56 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 129.2 47.99 130.56 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 129.2 25.91 130.56 ; + END + END chany_top_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 84.17 113.16 84.47 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 82.81 113.16 83.11 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 62.41 113.16 62.71 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 73.97 113.16 74.27 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 80.09 113.16 80.39 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 71.93 113.16 72.23 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 58.33 113.16 58.63 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 35.21 113.16 35.51 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 46.09 113.16 46.39 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 63.77 113.16 64.07 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 61.05 113.16 61.35 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 78.73 113.16 79.03 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 42.01 113.16 42.31 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 85.53 113.16 85.83 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 47.45 113.16 47.75 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 67.85 113.16 68.15 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 40.65 113.16 40.95 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 66.49 113.16 66.79 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 52.21 113.16 52.51 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 89.61 113.16 89.91 ; + END + END chanx_right_out[19] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 0 50.21 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.43 0 34.57 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 0 66.77 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 0 51.13 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 0 68.61 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 0 69.53 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 0 25.83 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 0 42.85 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 0 67.69 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 0 49.83 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 0 46.15 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 0 47.99 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.45 0 28.59 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 0 47.45 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 0 25.91 1.36 ; + END + END chany_bottom_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 84.16 2.48 84.64 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 84.16 7.92 84.64 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 84.16 13.36 84.64 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 84.16 18.8 84.64 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 84.16 24.24 84.64 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + RECT 0 105.84 0.48 106.32 ; + RECT 84.16 105.84 84.64 106.32 ; + RECT 0 111.28 0.48 111.76 ; + RECT 84.16 111.28 84.64 111.76 ; + RECT 0 116.72 0.48 117.2 ; + RECT 84.16 116.72 84.64 117.2 ; + RECT 0 122.16 0.48 122.64 ; + RECT 84.16 122.16 84.64 122.64 ; + RECT 0 127.6 0.48 128.08 ; + RECT 84.16 127.6 84.64 128.08 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 109.96 43.28 113.16 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 109.96 84.08 113.16 87.28 ; + RECT 0 122.84 3.2 126.04 ; + RECT 81.44 122.84 84.64 126.04 ; + LAYER met4 ; + RECT 12.58 0 13.18 0.6 ; + RECT 42.02 0 42.62 0.6 ; + RECT 71.46 0 72.06 0.6 ; + RECT 106.42 27.2 107.02 27.8 ; + RECT 106.42 102.76 107.02 103.36 ; + RECT 12.58 129.96 13.18 130.56 ; + RECT 42.02 129.96 42.62 130.56 ; + RECT 71.46 129.96 72.06 130.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 84.64 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 84.16 5.2 84.64 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 84.16 10.64 84.64 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 84.16 16.08 84.64 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 84.16 21.52 84.64 22 ; + RECT 0 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 112.68 75.92 113.16 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 0 103.12 113.16 103.6 ; + RECT 0 108.56 0.48 109.04 ; + RECT 84.16 108.56 84.64 109.04 ; + RECT 0 114 0.48 114.48 ; + RECT 84.16 114 84.64 114.48 ; + RECT 0 119.44 0.48 119.92 ; + RECT 84.16 119.44 84.64 119.92 ; + RECT 0 124.88 0.48 125.36 ; + RECT 84.16 124.88 84.64 125.36 ; + RECT 0 130.32 84.64 130.56 ; + LAYER met5 ; + RECT 0 4.52 3.2 7.72 ; + RECT 81.44 4.52 84.64 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 109.96 63.68 113.16 66.88 ; + LAYER met4 ; + RECT 27.3 0 27.9 0.6 ; + RECT 56.74 0 57.34 0.6 ; + RECT 27.3 129.96 27.9 130.56 ; + RECT 56.74 129.96 57.34 130.56 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 130.475 84.64 130.645 ; + RECT 80.96 127.755 84.64 127.925 ; + RECT 0 127.755 3.68 127.925 ; + RECT 80.96 125.035 84.64 125.205 ; + RECT 0 125.035 3.68 125.205 ; + RECT 82.8 122.315 84.64 122.485 ; + RECT 0 122.315 3.68 122.485 ; + RECT 80.96 119.595 84.64 119.765 ; + RECT 0 119.595 3.68 119.765 ; + RECT 80.96 116.875 84.64 117.045 ; + RECT 0 116.875 3.68 117.045 ; + RECT 83.72 114.155 84.64 114.325 ; + RECT 0 114.155 3.68 114.325 ; + RECT 83.72 111.435 84.64 111.605 ; + RECT 0 111.435 3.68 111.605 ; + RECT 84.18 108.715 84.64 108.885 ; + RECT 0 108.715 3.68 108.885 ; + RECT 84.18 105.995 84.64 106.165 ; + RECT 0 105.995 3.68 106.165 ; + RECT 81.42 103.275 113.16 103.445 ; + RECT 0 103.275 3.68 103.445 ; + RECT 112.7 100.555 113.16 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 112.7 97.835 113.16 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 112.24 95.115 113.16 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 112.24 92.395 113.16 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 112.24 89.675 113.16 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 112.24 86.955 113.16 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 112.7 84.235 113.16 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 112.7 81.515 113.16 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 112.7 78.795 113.16 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 112.7 76.075 113.16 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 112.24 73.355 113.16 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 112.24 70.635 113.16 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 112.24 67.915 113.16 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 112.24 65.195 113.16 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 112.24 62.475 113.16 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 112.24 59.755 113.16 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 112.24 57.035 113.16 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 112.24 54.315 113.16 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 112.24 51.595 113.16 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 112.24 48.875 113.16 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 112.24 46.155 113.16 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 112.24 43.435 113.16 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 112.24 40.715 113.16 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 112.24 37.995 113.16 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 112.24 35.275 113.16 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 111.32 32.555 113.16 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 109.48 29.835 113.16 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 83.72 27.115 113.16 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 83.72 24.395 84.64 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 80.96 21.675 84.64 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 80.96 18.955 84.64 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 84.18 16.235 84.64 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 80.96 13.515 84.64 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 80.96 10.795 84.64 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 83.72 8.075 84.64 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 82.8 5.355 84.64 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 80.96 2.635 84.64 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 84.64 0.085 ; + LAYER met3 ; + POLYGON 57.205 130.725 57.205 130.72 57.42 130.72 57.42 130.4 57.205 130.4 57.205 130.395 56.875 130.395 56.875 130.4 56.66 130.4 56.66 130.72 56.875 130.72 56.875 130.725 ; + POLYGON 27.765 130.725 27.765 130.72 27.98 130.72 27.98 130.4 27.765 130.4 27.765 130.395 27.435 130.395 27.435 130.4 27.22 130.4 27.22 130.72 27.435 130.72 27.435 130.725 ; + POLYGON 111.93 36.19 111.93 35.91 111.38 35.91 111.38 35.89 104.73 35.89 104.73 36.19 ; + POLYGON 57.205 0.165 57.205 0.16 57.42 0.16 57.42 -0.16 57.205 -0.16 57.205 -0.165 56.875 -0.165 56.875 -0.16 56.66 -0.16 56.66 0.16 56.875 0.16 56.875 0.165 ; + POLYGON 27.765 0.165 27.765 0.16 27.98 0.16 27.98 -0.16 27.765 -0.16 27.765 -0.165 27.435 -0.165 27.435 -0.16 27.22 -0.16 27.22 0.16 27.435 0.16 27.435 0.165 ; + POLYGON 84.24 130.16 84.24 127.03 82.86 127.03 82.86 125.93 84.24 125.93 84.24 119.55 82.86 119.55 82.86 118.45 84.24 118.45 84.24 118.19 82.86 118.19 82.86 117.09 84.24 117.09 84.24 102.96 112.76 102.96 112.76 99.83 111.38 99.83 111.38 98.73 112.76 98.73 112.76 97.11 111.38 97.11 111.38 96.01 112.76 96.01 112.76 95.75 111.38 95.75 111.38 94.65 112.76 94.65 112.76 94.39 111.38 94.39 111.38 93.29 112.76 93.29 112.76 91.67 111.38 91.67 111.38 90.57 112.76 90.57 112.76 90.31 111.38 90.31 111.38 89.21 112.76 89.21 112.76 88.95 111.38 88.95 111.38 87.85 112.76 87.85 112.76 86.23 111.38 86.23 111.38 85.13 112.76 85.13 112.76 84.87 111.38 84.87 111.38 83.77 112.76 83.77 112.76 83.51 111.38 83.51 111.38 82.41 112.76 82.41 112.76 80.79 111.38 80.79 111.38 79.69 112.76 79.69 112.76 79.43 111.38 79.43 111.38 78.33 112.76 78.33 112.76 78.07 111.38 78.07 111.38 76.97 112.76 76.97 112.76 74.67 111.38 74.67 111.38 73.57 112.76 73.57 112.76 72.63 111.38 72.63 111.38 71.53 112.76 71.53 112.76 69.91 111.38 69.91 111.38 68.81 112.76 68.81 112.76 68.55 111.38 68.55 111.38 67.45 112.76 67.45 112.76 67.19 111.38 67.19 111.38 66.09 112.76 66.09 112.76 65.83 111.38 65.83 111.38 64.73 112.76 64.73 112.76 64.47 111.38 64.47 111.38 63.37 112.76 63.37 112.76 63.11 111.38 63.11 111.38 62.01 112.76 62.01 112.76 61.75 111.38 61.75 111.38 60.65 112.76 60.65 112.76 59.03 111.38 59.03 111.38 57.93 112.76 57.93 112.76 57.67 111.38 57.67 111.38 56.57 112.76 56.57 112.76 56.31 111.38 56.31 111.38 55.21 112.76 55.21 112.76 52.91 111.38 52.91 111.38 51.81 112.76 51.81 112.76 51.55 111.38 51.55 111.38 50.45 112.76 50.45 112.76 49.51 111.38 49.51 111.38 48.41 112.76 48.41 112.76 48.15 111.38 48.15 111.38 47.05 112.76 47.05 112.76 46.79 111.38 46.79 111.38 45.69 112.76 45.69 112.76 45.43 111.38 45.43 111.38 44.33 112.76 44.33 112.76 44.07 111.38 44.07 111.38 42.97 112.76 42.97 112.76 42.71 111.38 42.71 111.38 41.61 112.76 41.61 112.76 41.35 111.38 41.35 111.38 40.25 112.76 40.25 112.76 39.99 111.38 39.99 111.38 38.89 112.76 38.89 112.76 38.63 111.38 38.63 111.38 37.53 112.76 37.53 112.76 37.27 111.38 37.27 111.38 36.17 112.76 36.17 112.76 35.91 111.38 35.91 111.38 34.81 112.76 34.81 112.76 34.55 111.38 34.55 111.38 33.45 112.76 33.45 112.76 33.19 111.38 33.19 111.38 32.09 112.76 32.09 112.76 31.83 111.38 31.83 111.38 30.73 112.76 30.73 112.76 27.6 84.24 27.6 84.24 0.4 0.4 0.4 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 130.16 ; + LAYER met2 ; + RECT 56.9 130.375 57.18 130.745 ; + RECT 27.46 130.375 27.74 130.745 ; + RECT 31.15 1.54 31.41 1.86 ; + RECT 27.93 1.54 28.19 1.86 ; + RECT 56.9 -0.185 57.18 0.185 ; + RECT 27.46 -0.185 27.74 0.185 ; + POLYGON 84.36 130.28 84.36 103.08 106.83 103.08 106.83 101.72 107.53 101.72 107.53 103.08 107.75 103.08 107.75 101.72 108.45 101.72 108.45 103.08 108.67 103.08 108.67 101.72 109.37 101.72 109.37 103.08 109.59 103.08 109.59 101.72 110.29 101.72 110.29 103.08 110.51 103.08 110.51 101.72 111.21 101.72 111.21 103.08 112.88 103.08 112.88 27.48 84.36 27.48 84.36 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 130.28 1.95 130.28 1.95 128.92 2.65 128.92 2.65 130.28 7.01 130.28 7.01 128.92 7.71 128.92 7.71 130.28 25.41 130.28 25.41 128.92 26.11 128.92 26.11 130.28 28.63 130.28 28.63 128.92 29.33 128.92 29.33 130.28 35.99 130.28 35.99 128.92 36.69 128.92 36.69 130.28 41.51 130.28 41.51 128.92 42.21 128.92 42.21 130.28 42.43 130.28 42.43 128.92 43.13 128.92 43.13 130.28 43.35 130.28 43.35 128.92 44.05 128.92 44.05 130.28 44.27 130.28 44.27 128.92 44.97 128.92 44.97 130.28 45.19 130.28 45.19 128.92 45.89 128.92 45.89 130.28 46.11 130.28 46.11 128.92 46.81 128.92 46.81 130.28 47.03 130.28 47.03 128.92 47.73 128.92 47.73 130.28 47.95 130.28 47.95 128.92 48.65 128.92 48.65 130.28 48.87 130.28 48.87 128.92 49.57 128.92 49.57 130.28 49.79 130.28 49.79 128.92 50.49 128.92 50.49 130.28 50.71 130.28 50.71 128.92 51.41 128.92 51.41 130.28 51.63 130.28 51.63 128.92 52.33 128.92 52.33 130.28 52.55 130.28 52.55 128.92 53.25 128.92 53.25 130.28 61.75 130.28 61.75 128.92 62.45 128.92 62.45 130.28 62.67 130.28 62.67 128.92 63.37 128.92 63.37 130.28 67.27 130.28 67.27 128.92 67.97 128.92 67.97 130.28 68.19 130.28 68.19 128.92 68.89 128.92 68.89 130.28 69.11 130.28 69.11 128.92 69.81 128.92 69.81 130.28 70.03 130.28 70.03 128.92 70.73 128.92 70.73 130.28 70.95 130.28 70.95 128.92 71.65 128.92 71.65 130.28 71.87 130.28 71.87 128.92 72.57 128.92 72.57 130.28 ; + LAYER met4 ; + POLYGON 84.24 130.16 84.24 102.96 106.02 102.96 106.02 102.36 107.42 102.36 107.42 102.96 112.76 102.96 112.76 27.6 107.42 27.6 107.42 28.2 106.02 28.2 106.02 27.6 84.24 27.6 84.24 0.4 72.46 0.4 72.46 1 71.06 1 71.06 0.4 57.74 0.4 57.74 1 56.34 1 56.34 0.4 50.23 0.4 50.23 1.76 49.13 1.76 49.13 0.4 48.39 0.4 48.39 1.76 47.29 1.76 47.29 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 43.02 0.4 43.02 1 41.62 1 41.62 0.4 28.3 0.4 28.3 1 26.9 1 26.9 0.4 26.31 0.4 26.31 1.76 25.21 1.76 25.21 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 13.58 0.4 13.58 1 12.18 1 12.18 0.4 0.4 0.4 0.4 130.16 4.97 130.16 4.97 128.8 6.07 128.8 6.07 130.16 6.81 130.16 6.81 128.8 7.91 128.8 7.91 130.16 8.65 130.16 8.65 128.8 9.75 128.8 9.75 130.16 12.18 130.16 12.18 129.56 13.58 129.56 13.58 130.16 14.17 130.16 14.17 128.8 15.27 128.8 15.27 130.16 19.69 130.16 19.69 128.8 20.79 128.8 20.79 130.16 21.53 130.16 21.53 128.8 22.63 128.8 22.63 130.16 23.37 130.16 23.37 128.8 24.47 128.8 24.47 130.16 25.21 130.16 25.21 128.8 26.31 128.8 26.31 130.16 26.9 130.16 26.9 129.56 28.3 129.56 28.3 130.16 28.89 130.16 28.89 128.8 29.99 128.8 29.99 130.16 41.62 130.16 41.62 129.56 43.02 129.56 43.02 130.16 43.61 130.16 43.61 128.8 44.71 128.8 44.71 130.16 45.45 130.16 45.45 128.8 46.55 128.8 46.55 130.16 47.29 130.16 47.29 128.8 48.39 128.8 48.39 130.16 49.13 130.16 49.13 128.8 50.23 128.8 50.23 130.16 56.34 130.16 56.34 129.56 57.74 129.56 57.74 130.16 58.33 130.16 58.33 128.8 59.43 128.8 59.43 130.16 68.45 130.16 68.45 128.8 69.55 128.8 69.55 130.16 71.06 130.16 71.06 129.56 72.46 129.56 72.46 130.16 ; + LAYER met5 ; + POLYGON 78.24 127.36 78.24 119.64 81.44 119.64 81.44 100.16 109.96 100.16 109.96 90.48 106.76 90.48 106.76 80.88 109.96 80.88 109.96 70.08 106.76 70.08 106.76 60.48 109.96 60.48 109.96 49.68 106.76 49.68 106.76 40.08 109.96 40.08 109.96 30.4 81.44 30.4 81.44 10.92 78.24 10.92 78.24 3.2 6.4 3.2 6.4 10.92 3.2 10.92 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 119.64 6.4 119.64 6.4 127.36 ; + LAYER met1 ; + POLYGON 84.36 130.04 84.36 128.36 83.88 128.36 83.88 127.32 84.36 127.32 84.36 125.64 83.88 125.64 83.88 124.6 84.36 124.6 84.36 122.92 83.88 122.92 83.88 121.88 84.36 121.88 84.36 120.2 83.88 120.2 83.88 119.16 84.36 119.16 84.36 117.48 83.88 117.48 83.88 116.44 84.36 116.44 84.36 114.76 83.88 114.76 83.88 113.72 84.36 113.72 84.36 112.04 83.88 112.04 83.88 111 84.36 111 84.36 109.32 83.88 109.32 83.88 108.28 84.36 108.28 84.36 106.6 83.88 106.6 83.88 105.56 84.36 105.56 84.36 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 0.76 108.28 0.76 109.32 0.28 109.32 0.28 111 0.76 111 0.76 112.04 0.28 112.04 0.28 113.72 0.76 113.72 0.76 114.76 0.28 114.76 0.28 116.44 0.76 116.44 0.76 117.48 0.28 117.48 0.28 119.16 0.76 119.16 0.76 120.2 0.28 120.2 0.28 121.88 0.76 121.88 0.76 122.92 0.28 122.92 0.28 124.6 0.76 124.6 0.76 125.64 0.28 125.64 0.28 127.32 0.76 127.32 0.76 128.36 0.28 128.36 0.28 130.04 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 112.4 76.68 112.4 75.64 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 ; + LAYER li1 ; + POLYGON 84.3 130.22 84.3 103.02 112.82 103.02 112.82 27.54 84.3 27.54 84.3 0.34 0.34 0.34 0.34 130.22 ; + LAYER mcon ; + RECT 84.325 130.475 84.495 130.645 ; + RECT 83.865 130.475 84.035 130.645 ; + RECT 83.405 130.475 83.575 130.645 ; + RECT 82.945 130.475 83.115 130.645 ; + RECT 82.485 130.475 82.655 130.645 ; + RECT 82.025 130.475 82.195 130.645 ; + RECT 81.565 130.475 81.735 130.645 ; + RECT 81.105 130.475 81.275 130.645 ; + RECT 80.645 130.475 80.815 130.645 ; + RECT 80.185 130.475 80.355 130.645 ; + RECT 79.725 130.475 79.895 130.645 ; + RECT 79.265 130.475 79.435 130.645 ; + RECT 78.805 130.475 78.975 130.645 ; + RECT 78.345 130.475 78.515 130.645 ; + RECT 77.885 130.475 78.055 130.645 ; + RECT 77.425 130.475 77.595 130.645 ; + RECT 76.965 130.475 77.135 130.645 ; + RECT 76.505 130.475 76.675 130.645 ; + RECT 76.045 130.475 76.215 130.645 ; + RECT 75.585 130.475 75.755 130.645 ; + RECT 75.125 130.475 75.295 130.645 ; + RECT 74.665 130.475 74.835 130.645 ; + RECT 74.205 130.475 74.375 130.645 ; + RECT 73.745 130.475 73.915 130.645 ; + RECT 73.285 130.475 73.455 130.645 ; + RECT 72.825 130.475 72.995 130.645 ; + RECT 72.365 130.475 72.535 130.645 ; + RECT 71.905 130.475 72.075 130.645 ; + RECT 71.445 130.475 71.615 130.645 ; + RECT 70.985 130.475 71.155 130.645 ; + RECT 70.525 130.475 70.695 130.645 ; + RECT 70.065 130.475 70.235 130.645 ; + RECT 69.605 130.475 69.775 130.645 ; + RECT 69.145 130.475 69.315 130.645 ; + RECT 68.685 130.475 68.855 130.645 ; + RECT 68.225 130.475 68.395 130.645 ; + RECT 67.765 130.475 67.935 130.645 ; + RECT 67.305 130.475 67.475 130.645 ; + RECT 66.845 130.475 67.015 130.645 ; + RECT 66.385 130.475 66.555 130.645 ; + RECT 65.925 130.475 66.095 130.645 ; + RECT 65.465 130.475 65.635 130.645 ; + RECT 65.005 130.475 65.175 130.645 ; + RECT 64.545 130.475 64.715 130.645 ; + RECT 64.085 130.475 64.255 130.645 ; + RECT 63.625 130.475 63.795 130.645 ; + RECT 63.165 130.475 63.335 130.645 ; + RECT 62.705 130.475 62.875 130.645 ; + RECT 62.245 130.475 62.415 130.645 ; + RECT 61.785 130.475 61.955 130.645 ; + RECT 61.325 130.475 61.495 130.645 ; + RECT 60.865 130.475 61.035 130.645 ; + RECT 60.405 130.475 60.575 130.645 ; + RECT 59.945 130.475 60.115 130.645 ; + RECT 59.485 130.475 59.655 130.645 ; + RECT 59.025 130.475 59.195 130.645 ; + RECT 58.565 130.475 58.735 130.645 ; + RECT 58.105 130.475 58.275 130.645 ; + RECT 57.645 130.475 57.815 130.645 ; + RECT 57.185 130.475 57.355 130.645 ; + RECT 56.725 130.475 56.895 130.645 ; + RECT 56.265 130.475 56.435 130.645 ; + RECT 55.805 130.475 55.975 130.645 ; + RECT 55.345 130.475 55.515 130.645 ; + RECT 54.885 130.475 55.055 130.645 ; + RECT 54.425 130.475 54.595 130.645 ; + RECT 53.965 130.475 54.135 130.645 ; + RECT 53.505 130.475 53.675 130.645 ; + RECT 53.045 130.475 53.215 130.645 ; + RECT 52.585 130.475 52.755 130.645 ; + RECT 52.125 130.475 52.295 130.645 ; + RECT 51.665 130.475 51.835 130.645 ; + RECT 51.205 130.475 51.375 130.645 ; + RECT 50.745 130.475 50.915 130.645 ; + RECT 50.285 130.475 50.455 130.645 ; + RECT 49.825 130.475 49.995 130.645 ; + RECT 49.365 130.475 49.535 130.645 ; + RECT 48.905 130.475 49.075 130.645 ; + RECT 48.445 130.475 48.615 130.645 ; + RECT 47.985 130.475 48.155 130.645 ; + RECT 47.525 130.475 47.695 130.645 ; + RECT 47.065 130.475 47.235 130.645 ; + RECT 46.605 130.475 46.775 130.645 ; + RECT 46.145 130.475 46.315 130.645 ; + RECT 45.685 130.475 45.855 130.645 ; + RECT 45.225 130.475 45.395 130.645 ; + RECT 44.765 130.475 44.935 130.645 ; + RECT 44.305 130.475 44.475 130.645 ; + RECT 43.845 130.475 44.015 130.645 ; + RECT 43.385 130.475 43.555 130.645 ; + RECT 42.925 130.475 43.095 130.645 ; + RECT 42.465 130.475 42.635 130.645 ; + RECT 42.005 130.475 42.175 130.645 ; + RECT 41.545 130.475 41.715 130.645 ; + RECT 41.085 130.475 41.255 130.645 ; + RECT 40.625 130.475 40.795 130.645 ; + RECT 40.165 130.475 40.335 130.645 ; + RECT 39.705 130.475 39.875 130.645 ; + RECT 39.245 130.475 39.415 130.645 ; + RECT 38.785 130.475 38.955 130.645 ; + RECT 38.325 130.475 38.495 130.645 ; + RECT 37.865 130.475 38.035 130.645 ; + RECT 37.405 130.475 37.575 130.645 ; + RECT 36.945 130.475 37.115 130.645 ; + RECT 36.485 130.475 36.655 130.645 ; + RECT 36.025 130.475 36.195 130.645 ; + RECT 35.565 130.475 35.735 130.645 ; + RECT 35.105 130.475 35.275 130.645 ; + RECT 34.645 130.475 34.815 130.645 ; + RECT 34.185 130.475 34.355 130.645 ; + RECT 33.725 130.475 33.895 130.645 ; + RECT 33.265 130.475 33.435 130.645 ; + RECT 32.805 130.475 32.975 130.645 ; + RECT 32.345 130.475 32.515 130.645 ; + RECT 31.885 130.475 32.055 130.645 ; + RECT 31.425 130.475 31.595 130.645 ; + RECT 30.965 130.475 31.135 130.645 ; + RECT 30.505 130.475 30.675 130.645 ; + RECT 30.045 130.475 30.215 130.645 ; + RECT 29.585 130.475 29.755 130.645 ; + RECT 29.125 130.475 29.295 130.645 ; + RECT 28.665 130.475 28.835 130.645 ; + RECT 28.205 130.475 28.375 130.645 ; + RECT 27.745 130.475 27.915 130.645 ; + RECT 27.285 130.475 27.455 130.645 ; + RECT 26.825 130.475 26.995 130.645 ; + RECT 26.365 130.475 26.535 130.645 ; + RECT 25.905 130.475 26.075 130.645 ; + RECT 25.445 130.475 25.615 130.645 ; + RECT 24.985 130.475 25.155 130.645 ; + RECT 24.525 130.475 24.695 130.645 ; + RECT 24.065 130.475 24.235 130.645 ; + RECT 23.605 130.475 23.775 130.645 ; + RECT 23.145 130.475 23.315 130.645 ; + RECT 22.685 130.475 22.855 130.645 ; + RECT 22.225 130.475 22.395 130.645 ; + RECT 21.765 130.475 21.935 130.645 ; + RECT 21.305 130.475 21.475 130.645 ; + RECT 20.845 130.475 21.015 130.645 ; + RECT 20.385 130.475 20.555 130.645 ; + RECT 19.925 130.475 20.095 130.645 ; + RECT 19.465 130.475 19.635 130.645 ; + RECT 19.005 130.475 19.175 130.645 ; + RECT 18.545 130.475 18.715 130.645 ; + RECT 18.085 130.475 18.255 130.645 ; + RECT 17.625 130.475 17.795 130.645 ; + RECT 17.165 130.475 17.335 130.645 ; + RECT 16.705 130.475 16.875 130.645 ; + RECT 16.245 130.475 16.415 130.645 ; + RECT 15.785 130.475 15.955 130.645 ; + RECT 15.325 130.475 15.495 130.645 ; + RECT 14.865 130.475 15.035 130.645 ; + RECT 14.405 130.475 14.575 130.645 ; + RECT 13.945 130.475 14.115 130.645 ; + RECT 13.485 130.475 13.655 130.645 ; + RECT 13.025 130.475 13.195 130.645 ; + RECT 12.565 130.475 12.735 130.645 ; + RECT 12.105 130.475 12.275 130.645 ; + RECT 11.645 130.475 11.815 130.645 ; + RECT 11.185 130.475 11.355 130.645 ; + RECT 10.725 130.475 10.895 130.645 ; + RECT 10.265 130.475 10.435 130.645 ; + RECT 9.805 130.475 9.975 130.645 ; + RECT 9.345 130.475 9.515 130.645 ; + RECT 8.885 130.475 9.055 130.645 ; + RECT 8.425 130.475 8.595 130.645 ; + RECT 7.965 130.475 8.135 130.645 ; + RECT 7.505 130.475 7.675 130.645 ; + RECT 7.045 130.475 7.215 130.645 ; + RECT 6.585 130.475 6.755 130.645 ; + RECT 6.125 130.475 6.295 130.645 ; + RECT 5.665 130.475 5.835 130.645 ; + RECT 5.205 130.475 5.375 130.645 ; + RECT 4.745 130.475 4.915 130.645 ; + RECT 4.285 130.475 4.455 130.645 ; + RECT 3.825 130.475 3.995 130.645 ; + RECT 3.365 130.475 3.535 130.645 ; + RECT 2.905 130.475 3.075 130.645 ; + RECT 2.445 130.475 2.615 130.645 ; + RECT 1.985 130.475 2.155 130.645 ; + RECT 1.525 130.475 1.695 130.645 ; + RECT 1.065 130.475 1.235 130.645 ; + RECT 0.605 130.475 0.775 130.645 ; + RECT 0.145 130.475 0.315 130.645 ; + RECT 84.325 127.755 84.495 127.925 ; + RECT 83.865 127.755 84.035 127.925 ; + RECT 0.605 127.755 0.775 127.925 ; + RECT 0.145 127.755 0.315 127.925 ; + RECT 84.325 125.035 84.495 125.205 ; + RECT 83.865 125.035 84.035 125.205 ; + RECT 0.605 125.035 0.775 125.205 ; + RECT 0.145 125.035 0.315 125.205 ; + RECT 84.325 122.315 84.495 122.485 ; + RECT 83.865 122.315 84.035 122.485 ; + RECT 0.605 122.315 0.775 122.485 ; + RECT 0.145 122.315 0.315 122.485 ; + RECT 84.325 119.595 84.495 119.765 ; + RECT 83.865 119.595 84.035 119.765 ; + RECT 0.605 119.595 0.775 119.765 ; + RECT 0.145 119.595 0.315 119.765 ; + RECT 84.325 116.875 84.495 117.045 ; + RECT 83.865 116.875 84.035 117.045 ; + RECT 0.605 116.875 0.775 117.045 ; + RECT 0.145 116.875 0.315 117.045 ; + RECT 84.325 114.155 84.495 114.325 ; + RECT 83.865 114.155 84.035 114.325 ; + RECT 0.605 114.155 0.775 114.325 ; + RECT 0.145 114.155 0.315 114.325 ; + RECT 84.325 111.435 84.495 111.605 ; + RECT 83.865 111.435 84.035 111.605 ; + RECT 0.605 111.435 0.775 111.605 ; + RECT 0.145 111.435 0.315 111.605 ; + RECT 84.325 108.715 84.495 108.885 ; + RECT 83.865 108.715 84.035 108.885 ; + RECT 0.605 108.715 0.775 108.885 ; + RECT 0.145 108.715 0.315 108.885 ; + RECT 84.325 105.995 84.495 106.165 ; + RECT 83.865 105.995 84.035 106.165 ; + RECT 0.605 105.995 0.775 106.165 ; + RECT 0.145 105.995 0.315 106.165 ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 84.325 24.395 84.495 24.565 ; + RECT 83.865 24.395 84.035 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 84.325 21.675 84.495 21.845 ; + RECT 83.865 21.675 84.035 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 84.325 18.955 84.495 19.125 ; + RECT 83.865 18.955 84.035 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 84.325 16.235 84.495 16.405 ; + RECT 83.865 16.235 84.035 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 84.325 13.515 84.495 13.685 ; + RECT 83.865 13.515 84.035 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 84.325 8.075 84.495 8.245 ; + RECT 83.865 8.075 84.035 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 84.325 5.355 84.495 5.525 ; + RECT 83.865 5.355 84.035 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 84.325 2.635 84.495 2.805 ; + RECT 83.865 2.635 84.035 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 56.965 130.485 57.115 130.635 ; + RECT 27.525 130.485 27.675 130.635 ; + RECT 62.945 128.785 63.095 128.935 ; + RECT 56.965 103.285 57.115 103.435 ; + RECT 27.525 103.285 27.675 103.435 ; + RECT 108.025 101.585 108.175 101.735 ; + RECT 56.965 27.125 57.115 27.275 ; + RECT 27.525 27.125 27.675 27.275 ; + RECT 65.705 1.625 65.855 1.775 ; + RECT 54.205 1.625 54.355 1.775 ; + RECT 34.425 1.625 34.575 1.775 ; + RECT 56.965 -0.075 57.115 0.075 ; + RECT 27.525 -0.075 27.675 0.075 ; + LAYER via2 ; + RECT 56.94 130.46 57.14 130.66 ; + RECT 27.5 130.46 27.7 130.66 ; + RECT 111.68 67.9 111.88 68.1 ; + RECT 111.68 63.82 111.88 64.02 ; + RECT 111.22 62.46 111.42 62.66 ; + RECT 111.68 46.14 111.88 46.34 ; + RECT 111.22 40.7 111.42 40.9 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via3 ; + RECT 56.94 130.46 57.14 130.66 ; + RECT 27.5 130.46 27.7 130.66 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via4 ; + RECT 106.32 86.08 107.12 86.88 ; + RECT 106.32 84.48 107.12 85.28 ; + RECT 106.32 45.28 107.12 46.08 ; + RECT 106.32 43.68 107.12 44.48 ; + LAYER fieldpoly ; + POLYGON 84.5 130.42 84.5 103.22 113.02 103.22 113.02 27.34 84.5 27.34 84.5 0.14 0.14 0.14 0.14 130.42 ; + LAYER diff ; + POLYGON 84.64 130.56 84.64 103.36 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 130.56 ; + LAYER nwell ; + RECT 80.77 126.425 84.83 129.255 ; + RECT -0.19 126.425 3.87 129.255 ; + POLYGON 84.83 123.815 84.83 120.985 82.61 120.985 82.61 122.59 83.99 122.59 83.99 123.815 ; + RECT -0.19 120.985 3.87 123.815 ; + POLYGON 84.83 118.375 84.83 115.545 83.99 115.545 83.99 116.77 80.77 116.77 80.77 118.375 ; + RECT -0.19 115.545 3.87 118.375 ; + POLYGON 84.83 112.935 84.83 110.105 83.99 110.105 83.99 111.33 83.53 111.33 83.53 112.935 ; + RECT -0.19 110.105 3.87 112.935 ; + RECT 83.99 104.665 84.83 107.495 ; + RECT -0.19 104.665 3.87 107.495 ; + RECT 112.51 99.225 113.35 102.055 ; + RECT -0.19 99.225 3.87 102.055 ; + POLYGON 113.35 96.615 113.35 93.785 112.05 93.785 112.05 95.39 112.51 95.39 112.51 96.615 ; + RECT -0.19 93.785 3.87 96.615 ; + POLYGON 113.35 91.175 113.35 88.345 112.05 88.345 112.05 89.95 112.51 89.95 112.51 91.175 ; + RECT -0.19 88.345 3.87 91.175 ; + RECT 112.51 82.905 113.35 85.735 ; + RECT -0.19 82.905 3.87 85.735 ; + RECT 112.51 77.465 113.35 80.295 ; + RECT -0.19 77.465 3.87 80.295 ; + POLYGON 113.35 74.855 113.35 72.025 112.05 72.025 112.05 73.63 112.51 73.63 112.51 74.855 ; + RECT -0.19 72.025 3.87 74.855 ; + RECT 112.05 66.585 113.35 69.415 ; + RECT -0.19 66.585 3.87 69.415 ; + POLYGON 113.35 63.975 113.35 61.145 112.51 61.145 112.51 62.37 112.05 62.37 112.05 63.975 ; + RECT -0.19 61.145 3.87 63.975 ; + RECT 112.05 55.705 113.35 58.535 ; + RECT -0.19 55.705 3.87 58.535 ; + RECT 112.05 50.265 113.35 53.095 ; + RECT -0.19 50.265 3.87 53.095 ; + POLYGON 113.35 47.655 113.35 44.825 112.51 44.825 112.51 46.05 112.05 46.05 112.05 47.655 ; + RECT -0.19 44.825 3.87 47.655 ; + RECT 112.05 39.385 113.35 42.215 ; + RECT -0.19 39.385 3.87 42.215 ; + POLYGON 113.35 36.775 113.35 33.945 112.05 33.945 112.05 35.55 112.51 35.55 112.51 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + POLYGON 113.35 31.335 113.35 28.505 109.29 28.505 109.29 30.11 111.13 30.11 111.13 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + RECT 83.53 23.065 84.83 25.895 ; + RECT -0.19 23.065 3.87 25.895 ; + POLYGON 84.83 20.455 84.83 17.625 83.99 17.625 83.99 18.85 80.77 18.85 80.77 20.455 ; + RECT -0.19 17.625 3.87 20.455 ; + POLYGON 84.83 15.015 84.83 12.185 80.77 12.185 80.77 13.79 83.99 13.79 83.99 15.015 ; + RECT -0.19 12.185 3.87 15.015 ; + POLYGON 84.83 9.575 84.83 6.745 83.53 6.745 83.53 8.35 83.99 8.35 83.99 9.575 ; + RECT -0.19 6.745 3.87 9.575 ; + POLYGON 84.83 4.135 84.83 1.305 80.77 1.305 80.77 2.91 82.61 2.91 82.61 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + POLYGON 84.64 130.56 84.64 103.36 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 130.56 ; + LAYER pwell ; + RECT 81.09 130.51 81.31 130.68 ; + RECT 77.41 130.51 77.63 130.68 ; + RECT 73.73 130.51 73.95 130.68 ; + RECT 70.05 130.51 70.27 130.68 ; + RECT 66.37 130.51 66.59 130.68 ; + RECT 62.69 130.51 62.91 130.68 ; + RECT 59.01 130.51 59.23 130.68 ; + RECT 55.33 130.51 55.55 130.68 ; + RECT 51.65 130.51 51.87 130.68 ; + RECT 47.97 130.51 48.19 130.68 ; + RECT 44.29 130.51 44.51 130.68 ; + RECT 40.61 130.51 40.83 130.68 ; + RECT 36.93 130.51 37.15 130.68 ; + RECT 33.25 130.51 33.47 130.68 ; + RECT 29.57 130.51 29.79 130.68 ; + RECT 25.89 130.51 26.11 130.68 ; + RECT 22.21 130.51 22.43 130.68 ; + RECT 18.53 130.51 18.75 130.68 ; + RECT 14.85 130.51 15.07 130.68 ; + RECT 11.17 130.51 11.39 130.68 ; + RECT 7.49 130.51 7.71 130.68 ; + RECT 3.81 130.51 4.03 130.68 ; + RECT 0.13 130.51 0.35 130.68 ; + RECT 107.31 103.31 107.53 103.48 ; + RECT 103.63 103.31 103.85 103.48 ; + RECT 99.95 103.31 100.17 103.48 ; + RECT 96.27 103.31 96.49 103.48 ; + RECT 92.59 103.31 92.81 103.48 ; + RECT 88.91 103.31 89.13 103.48 ; + RECT 85.23 103.31 85.45 103.48 ; + RECT 111.035 103.3 111.145 103.42 ; + RECT 112.84 103.305 112.96 103.415 ; + RECT 109.61 27.08 109.83 27.25 ; + RECT 105.93 27.08 106.15 27.25 ; + RECT 102.25 27.08 102.47 27.25 ; + RECT 98.57 27.08 98.79 27.25 ; + RECT 94.89 27.08 95.11 27.25 ; + RECT 91.21 27.08 91.43 27.25 ; + RECT 87.53 27.08 87.75 27.25 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + POLYGON 84.64 130.56 84.64 103.36 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 130.56 ; + LAYER OVERLAP ; + POLYGON 0 0 0 130.56 84.64 130.56 84.64 103.36 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 ; + END +END sb_0__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef new file mode 100644 index 0000000..bbe25ad --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -0,0 +1,2233 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 36.27 0 36.41 1.36 ; + END + END prog_clk[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 86.89 113.16 87.19 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 56.97 113.16 57.27 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 99.13 113.16 99.43 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 96.41 113.16 96.71 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 33.85 113.16 34.15 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 62.41 113.16 62.71 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 31.13 113.16 31.43 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 50.17 113.16 50.47 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 77.37 113.16 77.67 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 35.21 113.16 35.51 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 80.09 113.16 80.39 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 58.33 113.16 58.63 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 74.65 113.16 74.95 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 36.57 113.16 36.87 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 43.37 113.16 43.67 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 55.61 113.16 55.91 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 40.65 113.16 40.95 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 61.05 113.16 61.35 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 39.29 113.16 39.59 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 71.93 113.16 72.23 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 109.87 102 110.01 103.36 ; + END + END right_top_grid_pin_1_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.71 0 65.85 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.65 0 14.79 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 0 71.37 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.73 0 13.87 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.15 0 49.29 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 0 52.97 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.01 0 22.15 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.85 0 23.99 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.93 0 23.07 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 0 52.05 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.87 0 64.01 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 0 72.29 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.63 0 43.77 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.39 0 46.53 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.79 0 41.93 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.61 0 26.75 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.77 0 24.91 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END bottom_left_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 102 110.93 103.36 ; + END + END ccff_head[0] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 73.29 113.16 73.59 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 47.45 113.16 47.75 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 52.89 113.16 53.19 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 82.81 113.16 83.11 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 78.73 113.16 79.03 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 95.05 113.16 95.35 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 84.17 113.16 84.47 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 93.69 113.16 93.99 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 85.53 113.16 85.83 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 44.73 113.16 45.03 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 51.53 113.16 51.83 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 69.21 113.16 69.51 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 42.01 113.16 42.31 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 66.49 113.16 66.79 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 90.97 113.16 91.27 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 67.85 113.16 68.15 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 63.77 113.16 64.07 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 88.25 113.16 88.55 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 89.61 113.16 89.91 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 46.09 113.16 46.39 ; + END + END chanx_right_out[19] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 0 50.21 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.43 0 34.57 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 0 66.77 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.55 0 44.69 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 0 51.13 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.47 0 45.61 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 0 70.45 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 0 68.61 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 0 69.53 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.69 0 25.83 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.71 0 42.85 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 0 67.69 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.53 0 49.83 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 45.85 0 46.15 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 47.69 0 47.99 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.45 0 28.59 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.31 0 47.45 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 25.61 0 25.91 1.36 ; + END + END chany_bottom_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 84.16 2.48 84.64 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 84.16 7.92 84.64 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 84.16 13.36 84.64 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 84.16 18.8 84.64 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 84.16 24.24 84.64 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + LAYER met4 ; + RECT 12.58 0 13.18 0.6 ; + RECT 42.02 0 42.62 0.6 ; + RECT 71.46 0 72.06 0.6 ; + RECT 106.42 27.2 107.02 27.8 ; + RECT 12.58 102.76 13.18 103.36 ; + RECT 42.02 102.76 42.62 103.36 ; + RECT 71.46 102.76 72.06 103.36 ; + RECT 106.42 102.76 107.02 103.36 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 109.96 43.28 113.16 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 109.96 84.08 113.16 87.28 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 84.64 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 84.16 5.2 84.64 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 84.16 10.64 84.64 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 84.16 16.08 84.64 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 84.16 21.52 84.64 22 ; + RECT 0 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 112.68 75.92 113.16 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 0 103.12 113.16 103.36 ; + LAYER met5 ; + RECT 0 4.52 3.2 7.72 ; + RECT 81.44 4.52 84.64 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 109.96 63.68 113.16 66.88 ; + LAYER met4 ; + RECT 27.3 0 27.9 0.6 ; + RECT 56.74 0 57.34 0.6 ; + RECT 27.3 102.76 27.9 103.36 ; + RECT 56.74 102.76 57.34 103.36 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 103.275 113.16 103.445 ; + RECT 112.24 100.555 113.16 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 112.24 97.835 113.16 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 112.24 95.115 113.16 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 112.24 92.395 113.16 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 112.24 89.675 113.16 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 112.24 86.955 113.16 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 112.24 84.235 113.16 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 112.24 81.515 113.16 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 112.24 78.795 113.16 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 112.24 76.075 113.16 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 112.24 73.355 113.16 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 112.24 70.635 113.16 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 112.24 67.915 113.16 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 112.24 65.195 113.16 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 112.24 62.475 113.16 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 112.24 59.755 113.16 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 112.24 57.035 113.16 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 112.24 54.315 113.16 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 112.24 51.595 113.16 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 112.24 48.875 113.16 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 112.24 46.155 113.16 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 112.24 43.435 113.16 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 112.24 40.715 113.16 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 112.7 37.995 113.16 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 112.7 35.275 113.16 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 112.24 32.555 113.16 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 112.24 29.835 113.16 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 80.96 27.115 113.16 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 83.72 24.395 84.64 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 83.72 21.675 84.64 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 83.72 18.955 84.64 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 84.18 16.235 84.64 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 80.96 13.515 84.64 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 80.96 10.795 84.64 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 83.72 8.075 84.64 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 83.72 5.355 84.64 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 80.96 2.635 84.64 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 84.64 0.085 ; + LAYER met2 ; + RECT 56.9 103.175 57.18 103.545 ; + RECT 27.46 103.175 27.74 103.545 ; + RECT 56.9 -0.185 57.18 0.185 ; + RECT 27.46 -0.185 27.74 0.185 ; + POLYGON 112.88 103.08 112.88 27.48 84.36 27.48 84.36 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 103.08 109.59 103.08 109.59 101.72 110.29 101.72 110.29 103.08 110.51 103.08 110.51 101.72 111.21 101.72 111.21 103.08 ; + LAYER met3 ; + POLYGON 57.205 103.525 57.205 103.52 57.42 103.52 57.42 103.2 57.205 103.2 57.205 103.195 56.875 103.195 56.875 103.2 56.66 103.2 56.66 103.52 56.875 103.52 56.875 103.525 ; + POLYGON 27.765 103.525 27.765 103.52 27.98 103.52 27.98 103.2 27.765 103.2 27.765 103.195 27.435 103.195 27.435 103.2 27.22 103.2 27.22 103.52 27.435 103.52 27.435 103.525 ; + POLYGON 57.205 0.165 57.205 0.16 57.42 0.16 57.42 -0.16 57.205 -0.16 57.205 -0.165 56.875 -0.165 56.875 -0.16 56.66 -0.16 56.66 0.16 56.875 0.16 56.875 0.165 ; + POLYGON 27.765 0.165 27.765 0.16 27.98 0.16 27.98 -0.16 27.765 -0.16 27.765 -0.165 27.435 -0.165 27.435 -0.16 27.22 -0.16 27.22 0.16 27.435 0.16 27.435 0.165 ; + POLYGON 112.76 102.96 112.76 99.83 111.38 99.83 111.38 98.73 112.76 98.73 112.76 97.11 111.38 97.11 111.38 96.01 112.76 96.01 112.76 95.75 111.38 95.75 111.38 94.65 112.76 94.65 112.76 94.39 111.38 94.39 111.38 93.29 112.76 93.29 112.76 91.67 111.38 91.67 111.38 90.57 112.76 90.57 112.76 90.31 111.38 90.31 111.38 89.21 112.76 89.21 112.76 88.95 111.38 88.95 111.38 87.85 112.76 87.85 112.76 87.59 111.38 87.59 111.38 86.49 112.76 86.49 112.76 86.23 111.38 86.23 111.38 85.13 112.76 85.13 112.76 84.87 111.38 84.87 111.38 83.77 112.76 83.77 112.76 83.51 111.38 83.51 111.38 82.41 112.76 82.41 112.76 80.79 111.38 80.79 111.38 79.69 112.76 79.69 112.76 79.43 111.38 79.43 111.38 78.33 112.76 78.33 112.76 78.07 111.38 78.07 111.38 76.97 112.76 76.97 112.76 75.35 111.38 75.35 111.38 74.25 112.76 74.25 112.76 73.99 111.38 73.99 111.38 72.89 112.76 72.89 112.76 72.63 111.38 72.63 111.38 71.53 112.76 71.53 112.76 69.91 111.38 69.91 111.38 68.81 112.76 68.81 112.76 68.55 111.38 68.55 111.38 67.45 112.76 67.45 112.76 67.19 111.38 67.19 111.38 66.09 112.76 66.09 112.76 64.47 111.38 64.47 111.38 63.37 112.76 63.37 112.76 63.11 111.38 63.11 111.38 62.01 112.76 62.01 112.76 61.75 111.38 61.75 111.38 60.65 112.76 60.65 112.76 59.03 111.38 59.03 111.38 57.93 112.76 57.93 112.76 57.67 111.38 57.67 111.38 56.57 112.76 56.57 112.76 56.31 111.38 56.31 111.38 55.21 112.76 55.21 112.76 53.59 111.38 53.59 111.38 52.49 112.76 52.49 112.76 52.23 111.38 52.23 111.38 51.13 112.76 51.13 112.76 50.87 111.38 50.87 111.38 49.77 112.76 49.77 112.76 48.15 111.38 48.15 111.38 47.05 112.76 47.05 112.76 46.79 111.38 46.79 111.38 45.69 112.76 45.69 112.76 45.43 111.38 45.43 111.38 44.33 112.76 44.33 112.76 44.07 111.38 44.07 111.38 42.97 112.76 42.97 112.76 42.71 111.38 42.71 111.38 41.61 112.76 41.61 112.76 41.35 111.38 41.35 111.38 40.25 112.76 40.25 112.76 39.99 111.38 39.99 111.38 38.89 112.76 38.89 112.76 37.27 111.38 37.27 111.38 36.17 112.76 36.17 112.76 35.91 111.38 35.91 111.38 34.81 112.76 34.81 112.76 34.55 111.38 34.55 111.38 33.45 112.76 33.45 112.76 31.83 111.38 31.83 111.38 30.73 112.76 30.73 112.76 27.6 84.24 27.6 84.24 0.4 0.4 0.4 0.4 102.96 ; + LAYER met4 ; + POLYGON 112.76 102.96 112.76 27.6 107.42 27.6 107.42 28.2 106.02 28.2 106.02 27.6 84.24 27.6 84.24 0.4 72.46 0.4 72.46 1 71.06 1 71.06 0.4 57.74 0.4 57.74 1 56.34 1 56.34 0.4 50.23 0.4 50.23 1.76 49.13 1.76 49.13 0.4 48.39 0.4 48.39 1.76 47.29 1.76 47.29 0.4 46.55 0.4 46.55 1.76 45.45 1.76 45.45 0.4 43.02 0.4 43.02 1 41.62 1 41.62 0.4 28.3 0.4 28.3 1 26.9 1 26.9 0.4 26.31 0.4 26.31 1.76 25.21 1.76 25.21 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 13.58 0.4 13.58 1 12.18 1 12.18 0.4 0.4 0.4 0.4 102.96 12.18 102.96 12.18 102.36 13.58 102.36 13.58 102.96 26.9 102.96 26.9 102.36 28.3 102.36 28.3 102.96 41.62 102.96 41.62 102.36 43.02 102.36 43.02 102.96 56.34 102.96 56.34 102.36 57.74 102.36 57.74 102.96 71.06 102.96 71.06 102.36 72.46 102.36 72.46 102.96 106.02 102.96 106.02 102.36 107.42 102.36 107.42 102.96 ; + LAYER met5 ; + POLYGON 109.96 100.16 109.96 90.48 106.76 90.48 106.76 80.88 109.96 80.88 109.96 70.08 106.76 70.08 106.76 60.48 109.96 60.48 109.96 49.68 106.76 49.68 106.76 40.08 109.96 40.08 109.96 30.4 81.44 30.4 81.44 10.92 78.24 10.92 78.24 3.2 6.4 3.2 6.4 10.92 3.2 10.92 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 100.16 ; + LAYER met1 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 112.4 76.68 112.4 75.64 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 ; + LAYER li1 ; + POLYGON 112.82 103.02 112.82 27.54 84.3 27.54 84.3 0.34 0.34 0.34 0.34 103.02 ; + LAYER mcon ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 84.325 24.395 84.495 24.565 ; + RECT 83.865 24.395 84.035 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 84.325 21.675 84.495 21.845 ; + RECT 83.865 21.675 84.035 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 84.325 18.955 84.495 19.125 ; + RECT 83.865 18.955 84.035 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 84.325 16.235 84.495 16.405 ; + RECT 83.865 16.235 84.035 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 84.325 13.515 84.495 13.685 ; + RECT 83.865 13.515 84.035 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 84.325 8.075 84.495 8.245 ; + RECT 83.865 8.075 84.035 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 84.325 5.355 84.495 5.525 ; + RECT 83.865 5.355 84.035 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 84.325 2.635 84.495 2.805 ; + RECT 83.865 2.635 84.035 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 56.965 103.285 57.115 103.435 ; + RECT 27.525 103.285 27.675 103.435 ; + RECT 109.865 101.585 110.015 101.735 ; + RECT 56.965 27.125 57.115 27.275 ; + RECT 27.525 27.125 27.675 27.275 ; + RECT 54.205 1.625 54.355 1.775 ; + RECT 22.925 1.625 23.075 1.775 ; + RECT 56.965 -0.075 57.115 0.075 ; + RECT 27.525 -0.075 27.675 0.075 ; + LAYER via2 ; + RECT 56.94 103.26 57.14 103.46 ; + RECT 27.5 103.26 27.7 103.46 ; + RECT 111.68 93.74 111.88 93.94 ; + RECT 111.68 88.3 111.88 88.5 ; + RECT 111.68 82.86 111.88 83.06 ; + RECT 111.68 50.22 111.88 50.42 ; + RECT 111.22 47.5 111.42 47.7 ; + RECT 111.68 46.14 111.88 46.34 ; + RECT 111.68 42.06 111.88 42.26 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via3 ; + RECT 56.94 103.26 57.14 103.46 ; + RECT 27.5 103.26 27.7 103.46 ; + RECT 56.94 -0.1 57.14 0.1 ; + RECT 27.5 -0.1 27.7 0.1 ; + LAYER via4 ; + RECT 106.32 86.08 107.12 86.88 ; + RECT 106.32 84.48 107.12 85.28 ; + RECT 106.32 45.28 107.12 46.08 ; + RECT 106.32 43.68 107.12 44.48 ; + LAYER fieldpoly ; + POLYGON 113.02 103.22 113.02 27.34 84.5 27.34 84.5 0.14 0.14 0.14 0.14 103.22 ; + LAYER diff ; + POLYGON 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 103.36 ; + LAYER nwell ; + RECT 112.05 99.225 113.35 102.055 ; + RECT -0.19 99.225 3.87 102.055 ; + RECT 112.05 93.785 113.35 96.615 ; + RECT -0.19 93.785 3.87 96.615 ; + RECT 112.05 88.345 113.35 91.175 ; + RECT -0.19 88.345 3.87 91.175 ; + RECT 112.05 82.905 113.35 85.735 ; + RECT -0.19 82.905 3.87 85.735 ; + POLYGON 113.35 80.295 113.35 77.465 112.51 77.465 112.51 78.69 112.05 78.69 112.05 80.295 ; + RECT -0.19 77.465 3.87 80.295 ; + RECT 112.05 72.025 113.35 74.855 ; + RECT -0.19 72.025 3.87 74.855 ; + RECT 112.05 66.585 113.35 69.415 ; + RECT -0.19 66.585 3.87 69.415 ; + RECT 112.05 61.145 113.35 63.975 ; + RECT -0.19 61.145 3.87 63.975 ; + POLYGON 113.35 58.535 113.35 55.705 112.05 55.705 112.05 57.31 112.51 57.31 112.51 58.535 ; + RECT -0.19 55.705 3.87 58.535 ; + RECT 112.05 50.265 113.35 53.095 ; + RECT -0.19 50.265 3.87 53.095 ; + RECT 112.05 44.825 113.35 47.655 ; + RECT -0.19 44.825 3.87 47.655 ; + POLYGON 113.35 42.215 113.35 39.385 112.51 39.385 112.51 40.61 112.05 40.61 112.05 42.215 ; + RECT -0.19 39.385 3.87 42.215 ; + RECT 112.51 33.945 113.35 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + RECT 112.05 28.505 113.35 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + POLYGON 84.83 25.895 84.83 23.065 83.99 23.065 83.99 24.29 83.53 24.29 83.53 25.895 ; + RECT -0.19 23.065 3.87 25.895 ; + POLYGON 84.83 20.455 84.83 17.625 83.99 17.625 83.99 18.85 83.53 18.85 83.53 20.455 ; + RECT -0.19 17.625 3.87 20.455 ; + POLYGON 84.83 15.015 84.83 12.185 80.77 12.185 80.77 13.79 83.99 13.79 83.99 15.015 ; + RECT -0.19 12.185 3.87 15.015 ; + POLYGON 84.83 9.575 84.83 6.745 83.53 6.745 83.53 8.35 83.99 8.35 83.99 9.575 ; + RECT -0.19 6.745 3.87 9.575 ; + POLYGON 84.83 4.135 84.83 1.305 80.77 1.305 80.77 2.91 83.99 2.91 83.99 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + POLYGON 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 103.36 ; + LAYER pwell ; + RECT 106.85 103.31 107.07 103.48 ; + RECT 103.17 103.31 103.39 103.48 ; + RECT 99.49 103.31 99.71 103.48 ; + RECT 95.81 103.31 96.03 103.48 ; + RECT 92.13 103.31 92.35 103.48 ; + RECT 88.45 103.31 88.67 103.48 ; + RECT 84.77 103.31 84.99 103.48 ; + RECT 81.09 103.31 81.31 103.48 ; + RECT 77.41 103.31 77.63 103.48 ; + RECT 73.73 103.31 73.95 103.48 ; + RECT 70.05 103.31 70.27 103.48 ; + RECT 66.37 103.31 66.59 103.48 ; + RECT 62.69 103.31 62.91 103.48 ; + RECT 59.01 103.31 59.23 103.48 ; + RECT 55.33 103.31 55.55 103.48 ; + RECT 51.65 103.31 51.87 103.48 ; + RECT 47.97 103.31 48.19 103.48 ; + RECT 44.29 103.31 44.51 103.48 ; + RECT 40.61 103.31 40.83 103.48 ; + RECT 36.93 103.31 37.15 103.48 ; + RECT 33.25 103.31 33.47 103.48 ; + RECT 29.57 103.31 29.79 103.48 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 110.575 103.3 110.685 103.42 ; + RECT 112.395 103.3 112.555 103.41 ; + RECT 112.395 27.15 112.555 27.26 ; + RECT 110.575 27.14 110.685 27.26 ; + RECT 106.85 27.08 107.07 27.25 ; + RECT 103.17 27.08 103.39 27.25 ; + RECT 99.49 27.08 99.71 27.25 ; + RECT 95.81 27.08 96.03 27.25 ; + RECT 92.13 27.08 92.35 27.25 ; + RECT 88.45 27.08 88.67 27.25 ; + RECT 84.77 27.08 84.99 27.25 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + POLYGON 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 0 0 0 103.36 ; + LAYER OVERLAP ; + POLYGON 0 0 0 103.36 113.16 103.36 113.16 27.2 84.64 27.2 84.64 0 ; + END +END sb_0__2_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef new file mode 100644 index 0000000..d9ea027 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -0,0 +1,2918 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 141.68 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 30.75 102 30.89 103.36 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 102 80.57 103.36 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 102 57.57 103.36 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 102 82.41 103.36 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 102 74.13 103.36 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 102 52.05 103.36 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.19 102 60.33 103.36 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 102 75.05 103.36 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 102 66.77 103.36 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 102 72.29 103.36 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 102 67.69 103.36 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 102 73.21 103.36 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 102 75.97 103.36 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 102 52.97 103.36 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 102 63.55 103.36 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.67 102 54.81 103.36 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 102 53.89 103.36 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 102 69.53 103.36 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 102 81.49 103.36 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.57 102 84.71 103.36 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.27 102 59.41 103.36 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.05 102 33.19 103.36 ; + END + END top_left_grid_pin_34_[0] + PIN top_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 32.97 102 33.27 103.36 ; + END + END top_left_grid_pin_35_[0] + PIN top_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 99.81 29.9 100.11 ; + END + END top_left_grid_pin_36_[0] + PIN top_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.13 102 32.27 103.36 ; + END + END top_left_grid_pin_37_[0] + PIN top_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 97.77 29.9 98.07 ; + END + END top_left_grid_pin_38_[0] + PIN top_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 96.41 29.9 96.71 ; + END + END top_left_grid_pin_39_[0] + PIN top_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 95.05 29.9 95.35 ; + END + END top_left_grid_pin_40_[0] + PIN top_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 90.29 29.9 90.59 ; + END + END top_left_grid_pin_41_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 46.09 141.68 46.39 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 16.17 141.68 16.47 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 12.09 141.68 12.39 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 8.01 141.68 8.31 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 13.45 141.68 13.75 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 9.37 141.68 9.67 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 31.13 141.68 31.43 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 47.45 141.68 47.75 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 14.81 141.68 15.11 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 71.93 141.68 72.23 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 25.69 141.68 25.99 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 29.77 141.68 30.07 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 18.89 141.68 19.19 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 44.73 141.68 45.03 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 17.53 141.68 17.83 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 42.01 141.68 42.31 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 3.93 141.68 4.23 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 63.77 141.68 64.07 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 50.17 141.68 50.47 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 58.33 141.68 58.63 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 138.39 74.8 138.53 76.16 ; + END + END right_top_grid_pin_42_[0] + PIN right_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 99.13 113.16 99.43 ; + END + END right_top_grid_pin_43_[0] + PIN right_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.31 74.8 139.45 76.16 ; + END + END right_top_grid_pin_44_[0] + PIN right_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 137.47 74.8 137.61 76.16 ; + END + END right_top_grid_pin_45_[0] + PIN right_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 91.65 113.16 91.95 ; + END + END right_top_grid_pin_46_[0] + PIN right_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 90.29 113.16 90.59 ; + END + END right_top_grid_pin_47_[0] + PIN right_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 135.63 74.8 135.77 76.16 ; + END + END right_top_grid_pin_48_[0] + PIN right_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 136.55 74.8 136.69 76.16 ; + END + END right_top_grid_pin_49_[0] + PIN right_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.31 0 139.45 1.36 ; + END + END right_bottom_grid_pin_1_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.17 1.38 67.47 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.49 1.38 32.79 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.41 1.38 28.71 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 5.29 1.38 5.59 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 3.93 1.38 4.23 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 74.8 7.43 76.16 ; + END + END left_top_grid_pin_42_[0] + PIN left_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 91.65 29.9 91.95 ; + END + END left_top_grid_pin_43_[0] + PIN left_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.07 74.8 4.21 76.16 ; + END + END left_top_grid_pin_44_[0] + PIN left_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.99 74.8 5.13 76.16 ; + END + END left_top_grid_pin_45_[0] + PIN left_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 74.8 2.37 76.16 ; + END + END left_top_grid_pin_46_[0] + PIN left_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 74.8 3.29 76.16 ; + END + END left_top_grid_pin_47_[0] + PIN left_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.43 74.8 11.57 76.16 ; + END + END left_top_grid_pin_48_[0] + PIN left_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.51 74.8 10.65 76.16 ; + END + END left_top_grid_pin_49_[0] + PIN left_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END left_bottom_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 138.39 0 138.53 1.36 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 102 76.89 103.36 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.11 102 61.25 103.36 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 102 77.81 103.36 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 102 71.37 103.36 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 102 98.97 103.36 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.65 102 83.79 103.36 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 102 70.45 103.36 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 102 50.21 103.36 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 102 68.61 103.36 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.35 102 58.49 103.36 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 102 96.67 103.36 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.77 102 93.91 103.36 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 102 79.65 103.36 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 102 64.47 103.36 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 102 97.59 103.36 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 102 51.13 103.36 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.87 102 87.01 103.36 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 102 62.17 103.36 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.61 102 95.75 103.36 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 102 78.73 103.36 ; + END + END chany_top_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 59.69 141.68 59.99 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 66.49 141.68 66.79 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 6.65 141.68 6.95 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 67.85 141.68 68.15 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 35.21 141.68 35.51 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 56.97 141.68 57.27 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 28.41 141.68 28.71 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 51.53 141.68 51.83 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 33.85 141.68 34.15 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 40.65 141.68 40.95 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 24.33 141.68 24.63 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 55.61 141.68 55.91 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 69.21 141.68 69.51 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 61.05 141.68 61.35 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 22.97 141.68 23.27 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 39.29 141.68 39.59 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 36.57 141.68 36.87 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 62.41 141.68 62.71 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 20.25 141.68 20.55 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 52.89 141.68 53.19 ; + END + END chanx_right_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.05 1.38 27.35 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 64.45 1.38 64.75 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 15.49 1.38 15.79 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 11.41 1.38 11.71 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.69 1.38 25.99 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.61 1.38 21.91 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.81 1.38 66.11 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 10.05 1.38 10.35 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 141.2 2.48 141.68 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 141.2 7.92 141.68 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 141.2 13.36 141.68 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 141.2 18.8 141.68 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 141.2 24.24 141.68 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 141.2 29.68 141.68 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 141.2 35.12 141.68 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 141.2 40.56 141.68 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 141.2 46 141.68 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 141.2 51.44 141.68 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 141.2 56.88 141.68 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 141.2 62.32 141.68 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 141.2 67.76 141.68 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 141.2 73.2 141.68 73.68 ; + RECT 28.52 78.64 29 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 28.52 84.08 29 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 28.52 89.52 29 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 28.52 94.96 29 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 28.52 100.4 29 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 134.94 0 135.54 0.6 ; + RECT 134.94 75.56 135.54 76.16 ; + RECT 41.1 102.76 41.7 103.36 ; + RECT 70.54 102.76 71.14 103.36 ; + RECT 99.98 102.76 100.58 103.36 ; + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 138.48 16.08 141.68 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 138.48 56.88 141.68 60.08 ; + RECT 28.52 95.64 31.72 98.84 ; + RECT 109.96 95.64 113.16 98.84 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 141.68 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 141.2 5.2 141.68 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 141.2 10.64 141.68 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 141.2 16.08 141.68 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 141.2 21.52 141.68 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 141.2 26.96 141.68 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 141.2 32.4 141.68 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 141.2 37.84 141.68 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 141.2 43.28 141.68 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 141.2 48.72 141.68 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 141.2 54.16 141.68 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 141.2 59.6 141.68 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 141.2 65.04 141.68 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 141.2 70.48 141.68 70.96 ; + RECT 0 75.92 141.68 76.4 ; + RECT 28.52 81.36 29 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 28.52 86.8 29 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 28.52 92.24 29 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 28.52 97.68 29 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 28.52 103.12 113.16 103.36 ; + LAYER met4 ; + RECT 6.14 0 6.74 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 75.56 6.74 76.16 ; + RECT 55.82 102.76 56.42 103.36 ; + RECT 85.26 102.76 85.86 103.36 ; + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 138.48 36.48 141.68 39.68 ; + END + END VSS + OBS + LAYER li1 ; + RECT 28.52 103.275 113.16 103.445 ; + RECT 109.48 100.555 113.16 100.725 ; + RECT 28.52 100.555 32.2 100.725 ; + RECT 109.48 97.835 113.16 98.005 ; + RECT 28.52 97.835 32.2 98.005 ; + RECT 109.48 95.115 113.16 95.285 ; + RECT 28.52 95.115 32.2 95.285 ; + RECT 112.24 92.395 113.16 92.565 ; + RECT 28.52 92.395 32.2 92.565 ; + RECT 112.7 89.675 113.16 89.845 ; + RECT 28.52 89.675 32.2 89.845 ; + RECT 112.24 86.955 113.16 87.125 ; + RECT 28.52 86.955 32.2 87.125 ; + RECT 112.24 84.235 113.16 84.405 ; + RECT 28.52 84.235 32.2 84.405 ; + RECT 112.24 81.515 113.16 81.685 ; + RECT 28.52 81.515 32.2 81.685 ; + RECT 112.24 78.795 113.16 78.965 ; + RECT 28.52 78.795 32.2 78.965 ; + RECT 112.24 76.075 141.68 76.245 ; + RECT 0 76.075 30.36 76.245 ; + RECT 138 73.355 141.68 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 140.76 70.635 141.68 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 140.76 67.915 141.68 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 140.76 65.195 141.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 140.76 62.475 141.68 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 140.76 59.755 141.68 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 140.76 57.035 141.68 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 140.76 54.315 141.68 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 140.76 51.595 141.68 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 140.76 48.875 141.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 140.76 46.155 141.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 140.76 43.435 141.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 140.76 40.715 141.68 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 140.76 37.995 141.68 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 140.76 35.275 141.68 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 140.76 32.555 141.68 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 140.76 29.835 141.68 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 140.76 27.115 141.68 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 140.76 24.395 141.68 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 140.76 21.675 141.68 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 139.84 18.955 141.68 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 138 16.235 141.68 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 138 13.515 141.68 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 139.84 10.795 141.68 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 139.84 8.075 141.68 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 139.84 5.355 141.68 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 139.84 2.635 141.68 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 141.68 0.085 ; + LAYER met2 ; + RECT 85.42 103.175 85.7 103.545 ; + RECT 55.98 103.175 56.26 103.545 ; + RECT 84.05 101.5 84.31 101.82 ; + RECT 6.3 75.975 6.58 76.345 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 6.3 -0.185 6.58 0.185 ; + POLYGON 112.88 103.08 112.88 75.88 135.35 75.88 135.35 74.52 136.05 74.52 136.05 75.88 136.27 75.88 136.27 74.52 136.97 74.52 136.97 75.88 137.19 75.88 137.19 74.52 137.89 74.52 137.89 75.88 138.11 75.88 138.11 74.52 138.81 74.52 138.81 75.88 139.03 75.88 139.03 74.52 139.73 74.52 139.73 75.88 141.4 75.88 141.4 0.28 139.73 0.28 139.73 1.64 139.03 1.64 139.03 0.28 138.81 0.28 138.81 1.64 138.11 1.64 138.11 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 3.79 75.88 3.79 74.52 4.49 74.52 4.49 75.88 4.71 75.88 4.71 74.52 5.41 74.52 5.41 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 10.23 75.88 10.23 74.52 10.93 74.52 10.93 75.88 11.15 75.88 11.15 74.52 11.85 74.52 11.85 75.88 28.8 75.88 28.8 103.08 30.47 103.08 30.47 101.72 31.17 101.72 31.17 103.08 31.85 103.08 31.85 101.72 32.55 101.72 32.55 103.08 32.77 103.08 32.77 101.72 33.47 101.72 33.47 103.08 49.79 103.08 49.79 101.72 50.49 101.72 50.49 103.08 50.71 103.08 50.71 101.72 51.41 101.72 51.41 103.08 51.63 103.08 51.63 101.72 52.33 101.72 52.33 103.08 52.55 103.08 52.55 101.72 53.25 101.72 53.25 103.08 53.47 103.08 53.47 101.72 54.17 101.72 54.17 103.08 54.39 103.08 54.39 101.72 55.09 101.72 55.09 103.08 57.15 103.08 57.15 101.72 57.85 101.72 57.85 103.08 58.07 103.08 58.07 101.72 58.77 101.72 58.77 103.08 58.99 103.08 58.99 101.72 59.69 101.72 59.69 103.08 59.91 103.08 59.91 101.72 60.61 101.72 60.61 103.08 60.83 103.08 60.83 101.72 61.53 101.72 61.53 103.08 61.75 103.08 61.75 101.72 62.45 101.72 62.45 103.08 63.13 103.08 63.13 101.72 63.83 101.72 63.83 103.08 64.05 103.08 64.05 101.72 64.75 101.72 64.75 103.08 66.35 103.08 66.35 101.72 67.05 101.72 67.05 103.08 67.27 103.08 67.27 101.72 67.97 101.72 67.97 103.08 68.19 103.08 68.19 101.72 68.89 101.72 68.89 103.08 69.11 103.08 69.11 101.72 69.81 101.72 69.81 103.08 70.03 103.08 70.03 101.72 70.73 101.72 70.73 103.08 70.95 103.08 70.95 101.72 71.65 101.72 71.65 103.08 71.87 103.08 71.87 101.72 72.57 101.72 72.57 103.08 72.79 103.08 72.79 101.72 73.49 101.72 73.49 103.08 73.71 103.08 73.71 101.72 74.41 101.72 74.41 103.08 74.63 103.08 74.63 101.72 75.33 101.72 75.33 103.08 75.55 103.08 75.55 101.72 76.25 101.72 76.25 103.08 76.47 103.08 76.47 101.72 77.17 101.72 77.17 103.08 77.39 103.08 77.39 101.72 78.09 101.72 78.09 103.08 78.31 103.08 78.31 101.72 79.01 101.72 79.01 103.08 79.23 103.08 79.23 101.72 79.93 101.72 79.93 103.08 80.15 103.08 80.15 101.72 80.85 101.72 80.85 103.08 81.07 103.08 81.07 101.72 81.77 101.72 81.77 103.08 81.99 103.08 81.99 101.72 82.69 101.72 82.69 103.08 83.37 103.08 83.37 101.72 84.07 101.72 84.07 103.08 84.29 103.08 84.29 101.72 84.99 101.72 84.99 103.08 86.59 103.08 86.59 101.72 87.29 101.72 87.29 103.08 93.49 103.08 93.49 101.72 94.19 101.72 94.19 103.08 95.33 103.08 95.33 101.72 96.03 101.72 96.03 103.08 96.25 103.08 96.25 101.72 96.95 101.72 96.95 103.08 97.17 103.08 97.17 101.72 97.87 101.72 97.87 103.08 98.55 103.08 98.55 101.72 99.25 101.72 99.25 103.08 ; + LAYER met4 ; + POLYGON 112.76 102.96 112.76 75.76 134.54 75.76 134.54 75.16 135.94 75.16 135.94 75.76 141.28 75.76 141.28 0.4 135.94 0.4 135.94 1 134.54 1 134.54 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 7.14 0.4 7.14 1 5.74 1 5.74 0.4 0.4 0.4 0.4 75.76 5.74 75.76 5.74 75.16 7.14 75.16 7.14 75.76 28.92 75.76 28.92 102.96 32.57 102.96 32.57 101.6 33.67 101.6 33.67 102.96 40.7 102.96 40.7 102.36 42.1 102.36 42.1 102.96 55.42 102.96 55.42 102.36 56.82 102.36 56.82 102.96 70.14 102.96 70.14 102.36 71.54 102.36 71.54 102.96 84.86 102.96 84.86 102.36 86.26 102.36 86.26 102.96 99.58 102.96 99.58 102.36 100.98 102.36 100.98 102.96 ; + LAYER met3 ; + POLYGON 85.725 103.525 85.725 103.52 85.94 103.52 85.94 103.2 85.725 103.2 85.725 103.195 85.395 103.195 85.395 103.2 85.18 103.2 85.18 103.52 85.395 103.52 85.395 103.525 ; + POLYGON 56.285 103.525 56.285 103.52 56.5 103.52 56.5 103.2 56.285 103.2 56.285 103.195 55.955 103.195 55.955 103.2 55.74 103.2 55.74 103.52 55.955 103.52 55.955 103.525 ; + POLYGON 6.605 76.325 6.605 76.32 6.82 76.32 6.82 76 6.605 76 6.605 75.995 6.275 75.995 6.275 76 6.06 76 6.06 76.32 6.275 76.32 6.275 76.325 ; + POLYGON 38.79 71.55 38.79 71.25 1.78 71.25 1.78 71.27 1.23 71.27 1.23 71.55 ; + POLYGON 140.45 57.95 140.45 57.67 139.9 57.67 139.9 57.65 136.93 57.65 136.93 57.95 ; + POLYGON 24.53 55.23 24.53 54.93 1.78 54.93 1.78 54.95 1.23 54.95 1.23 55.23 ; + POLYGON 2.03 40.28 2.03 40.27 7.05 40.27 7.05 39.97 2.03 39.97 2.03 39.96 1.65 39.96 1.65 40.28 ; + POLYGON 6.13 28.03 6.13 27.73 1.78 27.73 1.78 27.75 1.23 27.75 1.23 28.03 ; + POLYGON 140.03 22.6 140.03 22.28 139.65 22.28 139.65 22.29 58.73 22.29 58.73 22.59 139.65 22.59 139.65 22.6 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 6.605 0.165 6.605 0.16 6.82 0.16 6.82 -0.16 6.605 -0.16 6.605 -0.165 6.275 -0.165 6.275 -0.16 6.06 -0.16 6.06 0.16 6.275 0.16 6.275 0.165 ; + POLYGON 112.76 102.96 112.76 99.83 111.38 99.83 111.38 98.73 112.76 98.73 112.76 92.35 111.38 92.35 111.38 91.25 112.76 91.25 112.76 90.99 111.38 90.99 111.38 89.89 112.76 89.89 112.76 75.76 141.28 75.76 141.28 72.63 139.9 72.63 139.9 71.53 141.28 71.53 141.28 69.91 139.9 69.91 139.9 68.81 141.28 68.81 141.28 68.55 139.9 68.55 139.9 67.45 141.28 67.45 141.28 67.19 139.9 67.19 139.9 66.09 141.28 66.09 141.28 64.47 139.9 64.47 139.9 63.37 141.28 63.37 141.28 63.11 139.9 63.11 139.9 62.01 141.28 62.01 141.28 61.75 139.9 61.75 139.9 60.65 141.28 60.65 141.28 60.39 139.9 60.39 139.9 59.29 141.28 59.29 141.28 59.03 139.9 59.03 139.9 57.93 141.28 57.93 141.28 57.67 139.9 57.67 139.9 56.57 141.28 56.57 141.28 56.31 139.9 56.31 139.9 55.21 141.28 55.21 141.28 53.59 139.9 53.59 139.9 52.49 141.28 52.49 141.28 52.23 139.9 52.23 139.9 51.13 141.28 51.13 141.28 50.87 139.9 50.87 139.9 49.77 141.28 49.77 141.28 48.15 139.9 48.15 139.9 47.05 141.28 47.05 141.28 46.79 139.9 46.79 139.9 45.69 141.28 45.69 141.28 45.43 139.9 45.43 139.9 44.33 141.28 44.33 141.28 42.71 139.9 42.71 139.9 41.61 141.28 41.61 141.28 41.35 139.9 41.35 139.9 40.25 141.28 40.25 141.28 39.99 139.9 39.99 139.9 38.89 141.28 38.89 141.28 37.27 139.9 37.27 139.9 36.17 141.28 36.17 141.28 35.91 139.9 35.91 139.9 34.81 141.28 34.81 141.28 34.55 139.9 34.55 139.9 33.45 141.28 33.45 141.28 31.83 139.9 31.83 139.9 30.73 141.28 30.73 141.28 30.47 139.9 30.47 139.9 29.37 141.28 29.37 141.28 29.11 139.9 29.11 139.9 28.01 141.28 28.01 141.28 26.39 139.9 26.39 139.9 25.29 141.28 25.29 141.28 25.03 139.9 25.03 139.9 23.93 141.28 23.93 141.28 23.67 139.9 23.67 139.9 22.57 141.28 22.57 141.28 20.95 139.9 20.95 139.9 19.85 141.28 19.85 141.28 19.59 139.9 19.59 139.9 18.49 141.28 18.49 141.28 18.23 139.9 18.23 139.9 17.13 141.28 17.13 141.28 16.87 139.9 16.87 139.9 15.77 141.28 15.77 141.28 15.51 139.9 15.51 139.9 14.41 141.28 14.41 141.28 14.15 139.9 14.15 139.9 13.05 141.28 13.05 141.28 12.79 139.9 12.79 139.9 11.69 141.28 11.69 141.28 10.07 139.9 10.07 139.9 8.97 141.28 8.97 141.28 8.71 139.9 8.71 139.9 7.61 141.28 7.61 141.28 7.35 139.9 7.35 139.9 6.25 141.28 6.25 141.28 4.63 139.9 4.63 139.9 3.53 141.28 3.53 141.28 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 75.76 28.92 75.76 28.92 89.89 30.3 89.89 30.3 90.99 28.92 90.99 28.92 91.25 30.3 91.25 30.3 92.35 28.92 92.35 28.92 94.65 30.3 94.65 30.3 95.75 28.92 95.75 28.92 96.01 30.3 96.01 30.3 97.11 28.92 97.11 28.92 97.37 30.3 97.37 30.3 98.47 28.92 98.47 28.92 99.41 30.3 99.41 30.3 100.51 28.92 100.51 28.92 102.96 ; + LAYER met5 ; + POLYGON 106.76 100.16 106.76 92.44 109.96 92.44 109.96 72.96 138.48 72.96 138.48 63.28 135.28 63.28 135.28 53.68 138.48 53.68 138.48 42.88 135.28 42.88 135.28 33.28 138.48 33.28 138.48 22.48 135.28 22.48 135.28 12.88 138.48 12.88 138.48 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 31.72 72.96 31.72 92.44 34.92 92.44 34.92 100.16 ; + LAYER met1 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 28.8 76.68 28.8 78.36 29.28 78.36 29.28 79.4 28.8 79.4 28.8 81.08 29.28 81.08 29.28 82.12 28.8 82.12 28.8 83.8 29.28 83.8 29.28 84.84 28.8 84.84 28.8 86.52 29.28 86.52 29.28 87.56 28.8 87.56 28.8 89.24 29.28 89.24 29.28 90.28 28.8 90.28 28.8 91.96 29.28 91.96 29.28 93 28.8 93 28.8 94.68 29.28 94.68 29.28 95.72 28.8 95.72 28.8 97.4 29.28 97.4 29.28 98.44 28.8 98.44 28.8 100.12 29.28 100.12 29.28 101.16 28.8 101.16 28.8 102.84 ; + POLYGON 141.4 75.64 141.4 73.96 140.92 73.96 140.92 72.92 141.4 72.92 141.4 71.24 140.92 71.24 140.92 70.2 141.4 70.2 141.4 68.52 140.92 68.52 140.92 67.48 141.4 67.48 141.4 65.8 140.92 65.8 140.92 64.76 141.4 64.76 141.4 63.08 140.92 63.08 140.92 62.04 141.4 62.04 141.4 60.36 140.92 60.36 140.92 59.32 141.4 59.32 141.4 57.64 140.92 57.64 140.92 56.6 141.4 56.6 141.4 54.92 140.92 54.92 140.92 53.88 141.4 53.88 141.4 52.2 140.92 52.2 140.92 51.16 141.4 51.16 141.4 49.48 140.92 49.48 140.92 48.44 141.4 48.44 141.4 46.76 140.92 46.76 140.92 45.72 141.4 45.72 141.4 44.04 140.92 44.04 140.92 43 141.4 43 141.4 41.32 140.92 41.32 140.92 40.28 141.4 40.28 141.4 38.6 140.92 38.6 140.92 37.56 141.4 37.56 141.4 35.88 140.92 35.88 140.92 34.84 141.4 34.84 141.4 33.16 140.92 33.16 140.92 32.12 141.4 32.12 141.4 30.44 140.92 30.44 140.92 29.4 141.4 29.4 141.4 27.72 140.92 27.72 140.92 26.68 141.4 26.68 141.4 25 140.92 25 140.92 23.96 141.4 23.96 141.4 22.28 140.92 22.28 140.92 21.24 141.4 21.24 141.4 19.56 140.92 19.56 140.92 18.52 141.4 18.52 141.4 16.84 140.92 16.84 140.92 15.8 141.4 15.8 141.4 14.12 140.92 14.12 140.92 13.08 141.4 13.08 141.4 11.4 140.92 11.4 140.92 10.36 141.4 10.36 141.4 8.68 140.92 8.68 140.92 7.64 141.4 7.64 141.4 5.96 140.92 5.96 140.92 4.92 141.4 4.92 141.4 3.24 140.92 3.24 140.92 2.2 141.4 2.2 141.4 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER li1 ; + POLYGON 112.82 103.02 112.82 75.82 141.34 75.82 141.34 0.34 0.34 0.34 0.34 75.82 28.86 75.82 28.86 103.02 ; + LAYER mcon ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 29.125 100.555 29.295 100.725 ; + RECT 28.665 100.555 28.835 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 29.125 95.115 29.295 95.285 ; + RECT 28.665 95.115 28.835 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 29.125 92.395 29.295 92.565 ; + RECT 28.665 92.395 28.835 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 29.125 89.675 29.295 89.845 ; + RECT 28.665 89.675 28.835 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 29.125 84.235 29.295 84.405 ; + RECT 28.665 84.235 28.835 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 29.125 81.515 29.295 81.685 ; + RECT 28.665 81.515 28.835 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 29.125 78.795 29.295 78.965 ; + RECT 28.665 78.795 28.835 78.965 ; + RECT 141.365 76.075 141.535 76.245 ; + RECT 140.905 76.075 141.075 76.245 ; + RECT 140.445 76.075 140.615 76.245 ; + RECT 139.985 76.075 140.155 76.245 ; + RECT 139.525 76.075 139.695 76.245 ; + RECT 139.065 76.075 139.235 76.245 ; + RECT 138.605 76.075 138.775 76.245 ; + RECT 138.145 76.075 138.315 76.245 ; + RECT 137.685 76.075 137.855 76.245 ; + RECT 137.225 76.075 137.395 76.245 ; + RECT 136.765 76.075 136.935 76.245 ; + RECT 136.305 76.075 136.475 76.245 ; + RECT 135.845 76.075 136.015 76.245 ; + RECT 135.385 76.075 135.555 76.245 ; + RECT 134.925 76.075 135.095 76.245 ; + RECT 134.465 76.075 134.635 76.245 ; + RECT 134.005 76.075 134.175 76.245 ; + RECT 133.545 76.075 133.715 76.245 ; + RECT 133.085 76.075 133.255 76.245 ; + RECT 132.625 76.075 132.795 76.245 ; + RECT 132.165 76.075 132.335 76.245 ; + RECT 131.705 76.075 131.875 76.245 ; + RECT 131.245 76.075 131.415 76.245 ; + RECT 130.785 76.075 130.955 76.245 ; + RECT 130.325 76.075 130.495 76.245 ; + RECT 129.865 76.075 130.035 76.245 ; + RECT 129.405 76.075 129.575 76.245 ; + RECT 128.945 76.075 129.115 76.245 ; + RECT 128.485 76.075 128.655 76.245 ; + RECT 128.025 76.075 128.195 76.245 ; + RECT 127.565 76.075 127.735 76.245 ; + RECT 127.105 76.075 127.275 76.245 ; + RECT 126.645 76.075 126.815 76.245 ; + RECT 126.185 76.075 126.355 76.245 ; + RECT 125.725 76.075 125.895 76.245 ; + RECT 125.265 76.075 125.435 76.245 ; + RECT 124.805 76.075 124.975 76.245 ; + RECT 124.345 76.075 124.515 76.245 ; + RECT 123.885 76.075 124.055 76.245 ; + RECT 123.425 76.075 123.595 76.245 ; + RECT 122.965 76.075 123.135 76.245 ; + RECT 122.505 76.075 122.675 76.245 ; + RECT 122.045 76.075 122.215 76.245 ; + RECT 121.585 76.075 121.755 76.245 ; + RECT 121.125 76.075 121.295 76.245 ; + RECT 120.665 76.075 120.835 76.245 ; + RECT 120.205 76.075 120.375 76.245 ; + RECT 119.745 76.075 119.915 76.245 ; + RECT 119.285 76.075 119.455 76.245 ; + RECT 118.825 76.075 118.995 76.245 ; + RECT 118.365 76.075 118.535 76.245 ; + RECT 117.905 76.075 118.075 76.245 ; + RECT 117.445 76.075 117.615 76.245 ; + RECT 116.985 76.075 117.155 76.245 ; + RECT 116.525 76.075 116.695 76.245 ; + RECT 116.065 76.075 116.235 76.245 ; + RECT 115.605 76.075 115.775 76.245 ; + RECT 115.145 76.075 115.315 76.245 ; + RECT 114.685 76.075 114.855 76.245 ; + RECT 114.225 76.075 114.395 76.245 ; + RECT 113.765 76.075 113.935 76.245 ; + RECT 113.305 76.075 113.475 76.245 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 111.925 76.075 112.095 76.245 ; + RECT 111.465 76.075 111.635 76.245 ; + RECT 111.005 76.075 111.175 76.245 ; + RECT 110.545 76.075 110.715 76.245 ; + RECT 110.085 76.075 110.255 76.245 ; + RECT 109.625 76.075 109.795 76.245 ; + RECT 109.165 76.075 109.335 76.245 ; + RECT 108.705 76.075 108.875 76.245 ; + RECT 108.245 76.075 108.415 76.245 ; + RECT 107.785 76.075 107.955 76.245 ; + RECT 107.325 76.075 107.495 76.245 ; + RECT 106.865 76.075 107.035 76.245 ; + RECT 106.405 76.075 106.575 76.245 ; + RECT 105.945 76.075 106.115 76.245 ; + RECT 105.485 76.075 105.655 76.245 ; + RECT 105.025 76.075 105.195 76.245 ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 141.365 73.355 141.535 73.525 ; + RECT 140.905 73.355 141.075 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 141.365 70.635 141.535 70.805 ; + RECT 140.905 70.635 141.075 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 141.365 67.915 141.535 68.085 ; + RECT 140.905 67.915 141.075 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 141.365 65.195 141.535 65.365 ; + RECT 140.905 65.195 141.075 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 141.365 62.475 141.535 62.645 ; + RECT 140.905 62.475 141.075 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 141.365 59.755 141.535 59.925 ; + RECT 140.905 59.755 141.075 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 141.365 57.035 141.535 57.205 ; + RECT 140.905 57.035 141.075 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 141.365 54.315 141.535 54.485 ; + RECT 140.905 54.315 141.075 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 141.365 51.595 141.535 51.765 ; + RECT 140.905 51.595 141.075 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 141.365 48.875 141.535 49.045 ; + RECT 140.905 48.875 141.075 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 141.365 46.155 141.535 46.325 ; + RECT 140.905 46.155 141.075 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 141.365 43.435 141.535 43.605 ; + RECT 140.905 43.435 141.075 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 141.365 40.715 141.535 40.885 ; + RECT 140.905 40.715 141.075 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 141.365 37.995 141.535 38.165 ; + RECT 140.905 37.995 141.075 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 141.365 35.275 141.535 35.445 ; + RECT 140.905 35.275 141.075 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 141.365 32.555 141.535 32.725 ; + RECT 140.905 32.555 141.075 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 141.365 29.835 141.535 30.005 ; + RECT 140.905 29.835 141.075 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 141.365 27.115 141.535 27.285 ; + RECT 140.905 27.115 141.075 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 141.365 24.395 141.535 24.565 ; + RECT 140.905 24.395 141.075 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 141.365 21.675 141.535 21.845 ; + RECT 140.905 21.675 141.075 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 141.365 18.955 141.535 19.125 ; + RECT 140.905 18.955 141.075 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 141.365 16.235 141.535 16.405 ; + RECT 140.905 16.235 141.075 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 141.365 13.515 141.535 13.685 ; + RECT 140.905 13.515 141.075 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 141.365 10.795 141.535 10.965 ; + RECT 140.905 10.795 141.075 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 141.365 8.075 141.535 8.245 ; + RECT 140.905 8.075 141.075 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 141.365 5.355 141.535 5.525 ; + RECT 140.905 5.355 141.075 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 141.365 2.635 141.535 2.805 ; + RECT 140.905 2.635 141.075 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 141.365 -0.085 141.535 0.085 ; + RECT 140.905 -0.085 141.075 0.085 ; + RECT 140.445 -0.085 140.615 0.085 ; + RECT 139.985 -0.085 140.155 0.085 ; + RECT 139.525 -0.085 139.695 0.085 ; + RECT 139.065 -0.085 139.235 0.085 ; + RECT 138.605 -0.085 138.775 0.085 ; + RECT 138.145 -0.085 138.315 0.085 ; + RECT 137.685 -0.085 137.855 0.085 ; + RECT 137.225 -0.085 137.395 0.085 ; + RECT 136.765 -0.085 136.935 0.085 ; + RECT 136.305 -0.085 136.475 0.085 ; + RECT 135.845 -0.085 136.015 0.085 ; + RECT 135.385 -0.085 135.555 0.085 ; + RECT 134.925 -0.085 135.095 0.085 ; + RECT 134.465 -0.085 134.635 0.085 ; + RECT 134.005 -0.085 134.175 0.085 ; + RECT 133.545 -0.085 133.715 0.085 ; + RECT 133.085 -0.085 133.255 0.085 ; + RECT 132.625 -0.085 132.795 0.085 ; + RECT 132.165 -0.085 132.335 0.085 ; + RECT 131.705 -0.085 131.875 0.085 ; + RECT 131.245 -0.085 131.415 0.085 ; + RECT 130.785 -0.085 130.955 0.085 ; + RECT 130.325 -0.085 130.495 0.085 ; + RECT 129.865 -0.085 130.035 0.085 ; + RECT 129.405 -0.085 129.575 0.085 ; + RECT 128.945 -0.085 129.115 0.085 ; + RECT 128.485 -0.085 128.655 0.085 ; + RECT 128.025 -0.085 128.195 0.085 ; + RECT 127.565 -0.085 127.735 0.085 ; + RECT 127.105 -0.085 127.275 0.085 ; + RECT 126.645 -0.085 126.815 0.085 ; + RECT 126.185 -0.085 126.355 0.085 ; + RECT 125.725 -0.085 125.895 0.085 ; + RECT 125.265 -0.085 125.435 0.085 ; + RECT 124.805 -0.085 124.975 0.085 ; + RECT 124.345 -0.085 124.515 0.085 ; + RECT 123.885 -0.085 124.055 0.085 ; + RECT 123.425 -0.085 123.595 0.085 ; + RECT 122.965 -0.085 123.135 0.085 ; + RECT 122.505 -0.085 122.675 0.085 ; + RECT 122.045 -0.085 122.215 0.085 ; + RECT 121.585 -0.085 121.755 0.085 ; + RECT 121.125 -0.085 121.295 0.085 ; + RECT 120.665 -0.085 120.835 0.085 ; + RECT 120.205 -0.085 120.375 0.085 ; + RECT 119.745 -0.085 119.915 0.085 ; + RECT 119.285 -0.085 119.455 0.085 ; + RECT 118.825 -0.085 118.995 0.085 ; + RECT 118.365 -0.085 118.535 0.085 ; + RECT 117.905 -0.085 118.075 0.085 ; + RECT 117.445 -0.085 117.615 0.085 ; + RECT 116.985 -0.085 117.155 0.085 ; + RECT 116.525 -0.085 116.695 0.085 ; + RECT 116.065 -0.085 116.235 0.085 ; + RECT 115.605 -0.085 115.775 0.085 ; + RECT 115.145 -0.085 115.315 0.085 ; + RECT 114.685 -0.085 114.855 0.085 ; + RECT 114.225 -0.085 114.395 0.085 ; + RECT 113.765 -0.085 113.935 0.085 ; + RECT 113.305 -0.085 113.475 0.085 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 71.225 101.585 71.375 101.735 ; + RECT 53.745 101.585 53.895 101.735 ; + RECT 85.485 76.085 85.635 76.235 ; + RECT 56.045 76.085 56.195 76.235 ; + RECT 6.365 76.085 6.515 76.235 ; + RECT 139.305 74.385 139.455 74.535 ; + RECT 135.625 74.385 135.775 74.535 ; + RECT 2.225 74.385 2.375 74.535 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 6.365 -0.075 6.515 0.075 ; + LAYER via2 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 29.8 95.1 30 95.3 ; + RECT 111.22 91.7 111.42 91.9 ; + RECT 30.26 91.7 30.46 91.9 ; + RECT 6.34 76.06 6.54 76.26 ; + RECT 1.28 71.98 1.48 72.18 ; + RECT 140.2 66.54 140.4 66.74 ; + RECT 1.74 65.86 1.94 66.06 ; + RECT 139.74 61.1 139.94 61.3 ; + RECT 1.28 61.1 1.48 61.3 ; + RECT 140.2 55.66 140.4 55.86 ; + RECT 1.28 55.66 1.48 55.86 ; + RECT 140.2 51.58 140.4 51.78 ; + RECT 1.28 39.34 1.48 39.54 ; + RECT 1.28 33.9 1.48 34.1 ; + RECT 140.2 28.46 140.4 28.66 ; + RECT 1.28 21.66 1.48 21.86 ; + RECT 139.74 20.3 139.94 20.5 ; + RECT 140.2 16.22 140.4 16.42 ; + RECT 140.2 8.06 140.4 8.26 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 6.34 -0.1 6.54 0.1 ; + LAYER via3 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 76.06 6.54 76.26 ; + RECT 1.74 37.98 1.94 38.18 ; + RECT 139.74 18.94 139.94 19.14 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 6.34 -0.1 6.54 0.1 ; + LAYER via4 ; + RECT 134.84 58.88 135.64 59.68 ; + RECT 134.84 57.28 135.64 58.08 ; + RECT 6.04 38.48 6.84 39.28 ; + RECT 6.04 36.88 6.84 37.68 ; + RECT 134.84 18.08 135.64 18.88 ; + RECT 134.84 16.48 135.64 17.28 ; + LAYER fieldpoly ; + POLYGON 113.02 103.22 113.02 76.02 141.54 76.02 141.54 0.14 0.14 0.14 0.14 76.02 28.66 76.02 28.66 103.22 ; + LAYER diff ; + POLYGON 113.16 103.36 113.16 76.16 141.68 76.16 141.68 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER nwell ; + POLYGON 113.35 102.055 113.35 99.225 111.13 99.225 111.13 100.45 109.29 100.45 109.29 102.055 ; + POLYGON 32.39 102.055 32.39 100.45 30.55 100.45 30.55 99.225 28.33 99.225 28.33 102.055 ; + POLYGON 113.35 96.615 113.35 93.785 112.05 93.785 112.05 95.01 109.29 95.01 109.29 96.615 ; + RECT 28.33 93.785 32.39 96.615 ; + RECT 112.51 88.345 113.35 91.175 ; + POLYGON 30.55 91.175 30.55 89.95 32.39 89.95 32.39 88.345 28.33 88.345 28.33 91.175 ; + RECT 112.05 82.905 113.35 85.735 ; + RECT 28.33 82.905 32.39 85.735 ; + POLYGON 113.35 80.295 113.35 77.465 112.51 77.465 112.51 78.69 112.05 78.69 112.05 80.295 ; + POLYGON 32.39 80.295 32.39 78.69 30.55 78.69 30.55 77.465 28.33 77.465 28.33 80.295 ; + POLYGON 141.87 74.855 141.87 72.025 140.57 72.025 140.57 73.25 137.81 73.25 137.81 74.855 ; + POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; + RECT 140.57 66.585 141.87 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + RECT 140.57 61.145 141.87 63.975 ; + RECT -0.19 61.145 2.03 63.975 ; + RECT 140.57 55.705 141.87 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 140.57 50.265 141.87 53.095 ; + POLYGON 3.87 53.095 3.87 51.49 2.03 51.49 2.03 50.265 -0.19 50.265 -0.19 53.095 ; + RECT 140.57 44.825 141.87 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 140.57 39.385 141.87 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + RECT 140.57 33.945 141.87 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + RECT 140.57 28.505 141.87 31.335 ; + RECT -0.19 28.505 2.03 31.335 ; + RECT 140.57 23.065 141.87 25.895 ; + RECT -0.19 23.065 2.03 25.895 ; + POLYGON 141.87 20.455 141.87 17.625 139.65 17.625 139.65 19.23 140.57 19.23 140.57 20.455 ; + RECT -0.19 17.625 2.03 20.455 ; + POLYGON 141.87 15.015 141.87 12.185 139.65 12.185 139.65 13.41 137.81 13.41 137.81 15.015 ; + POLYGON 3.87 15.015 3.87 13.41 2.03 13.41 2.03 12.185 -0.19 12.185 -0.19 15.015 ; + RECT 139.65 6.745 141.87 9.575 ; + POLYGON 2.03 9.575 2.03 8.35 3.87 8.35 3.87 6.745 -0.19 6.745 -0.19 9.575 ; + RECT 139.65 1.305 141.87 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + POLYGON 113.16 103.36 113.16 76.16 141.68 76.16 141.68 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER pwell ; + RECT 109.61 103.31 109.83 103.48 ; + RECT 105.93 103.31 106.15 103.48 ; + RECT 102.25 103.31 102.47 103.48 ; + RECT 98.57 103.31 98.79 103.48 ; + RECT 94.89 103.31 95.11 103.48 ; + RECT 91.21 103.31 91.43 103.48 ; + RECT 87.53 103.31 87.75 103.48 ; + RECT 83.85 103.31 84.07 103.48 ; + RECT 80.17 103.31 80.39 103.48 ; + RECT 76.49 103.31 76.71 103.48 ; + RECT 72.81 103.31 73.03 103.48 ; + RECT 69.13 103.31 69.35 103.48 ; + RECT 65.45 103.31 65.67 103.48 ; + RECT 61.77 103.31 61.99 103.48 ; + RECT 58.09 103.31 58.31 103.48 ; + RECT 54.41 103.31 54.63 103.48 ; + RECT 50.73 103.31 50.95 103.48 ; + RECT 47.05 103.31 47.27 103.48 ; + RECT 43.37 103.31 43.59 103.48 ; + RECT 39.69 103.31 39.91 103.48 ; + RECT 36.01 103.31 36.23 103.48 ; + RECT 32.33 103.31 32.55 103.48 ; + RECT 28.65 103.31 28.87 103.48 ; + RECT 138.13 76.11 138.35 76.28 ; + RECT 134.45 76.11 134.67 76.28 ; + RECT 130.77 76.11 130.99 76.28 ; + RECT 127.09 76.11 127.31 76.28 ; + RECT 123.41 76.11 123.63 76.28 ; + RECT 119.73 76.11 119.95 76.28 ; + RECT 116.05 76.11 116.27 76.28 ; + RECT 25.89 76.11 26.11 76.28 ; + RECT 22.21 76.11 22.43 76.28 ; + RECT 18.53 76.11 18.75 76.28 ; + RECT 14.85 76.11 15.07 76.28 ; + RECT 11.17 76.11 11.39 76.28 ; + RECT 7.49 76.11 7.71 76.28 ; + RECT 3.81 76.11 4.03 76.28 ; + RECT 0.13 76.11 0.35 76.28 ; + RECT 140.015 -0.06 140.125 0.06 ; + RECT 136.29 -0.12 136.51 0.05 ; + RECT 132.61 -0.12 132.83 0.05 ; + RECT 128.93 -0.12 129.15 0.05 ; + RECT 125.25 -0.12 125.47 0.05 ; + RECT 121.57 -0.12 121.79 0.05 ; + RECT 117.89 -0.12 118.11 0.05 ; + RECT 114.21 -0.12 114.43 0.05 ; + RECT 110.53 -0.12 110.75 0.05 ; + RECT 106.85 -0.12 107.07 0.05 ; + RECT 103.17 -0.12 103.39 0.05 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + POLYGON 113.16 103.36 113.16 76.16 141.68 76.16 141.68 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 28.52 76.16 28.52 103.36 113.16 103.36 113.16 76.16 141.68 76.16 141.68 0 ; + END +END sb_1__0_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef new file mode 100644 index 0000000..efd8de2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -0,0 +1,3560 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 141.68 BY 130.56 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 2.23 27.2 2.37 28.56 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 129.2 80.57 130.56 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 129.2 57.57 130.56 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 129.2 82.41 130.56 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 129.2 74.13 130.56 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 129.2 52.05 130.56 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.19 129.2 60.33 130.56 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 129.2 75.05 130.56 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 129.2 66.77 130.56 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 129.2 72.29 130.56 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 129.2 67.69 130.56 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 129.2 73.21 130.56 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 129.2 75.97 130.56 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 129.2 52.97 130.56 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 129.2 63.55 130.56 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.67 129.2 54.81 130.56 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 129.2 53.89 130.56 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 129.2 69.53 130.56 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 129.2 81.49 130.56 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.57 129.2 84.71 130.56 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.27 129.2 59.41 130.56 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 129.2 31.81 130.56 ; + END + END top_left_grid_pin_34_[0] + PIN top_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 129.2 32.73 130.56 ; + END + END top_left_grid_pin_35_[0] + PIN top_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 127.01 29.9 127.31 ; + END + END top_left_grid_pin_36_[0] + PIN top_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 129.2 30.89 130.56 ; + END + END top_left_grid_pin_37_[0] + PIN top_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 124.97 29.9 125.27 ; + END + END top_left_grid_pin_38_[0] + PIN top_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 123.61 29.9 123.91 ; + END + END top_left_grid_pin_39_[0] + PIN top_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 122.25 29.9 122.55 ; + END + END top_left_grid_pin_40_[0] + PIN top_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 117.49 29.9 117.79 ; + END + END top_left_grid_pin_41_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 48.81 141.68 49.11 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 99.13 141.68 99.43 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 55.61 141.68 55.91 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 37.93 141.68 38.23 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 93.69 141.68 93.99 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 95.05 141.68 95.35 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 77.37 141.68 77.67 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 69.21 141.68 69.51 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 44.73 141.68 45.03 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 50.85 141.68 51.15 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 36.57 141.68 36.87 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 43.37 141.68 43.67 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 96.41 141.68 96.71 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 32.49 141.68 32.79 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 90.97 141.68 91.27 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 56.97 141.68 57.27 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 39.29 141.68 39.59 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 33.85 141.68 34.15 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 65.13 141.68 65.43 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 31.13 141.68 31.43 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 138.39 102 138.53 103.36 ; + END + END right_top_grid_pin_42_[0] + PIN right_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 126.33 113.16 126.63 ; + END + END right_top_grid_pin_43_[0] + PIN right_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.31 102 139.45 103.36 ; + END + END right_top_grid_pin_44_[0] + PIN right_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 137.47 102 137.61 103.36 ; + END + END right_top_grid_pin_45_[0] + PIN right_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 118.85 113.16 119.15 ; + END + END right_top_grid_pin_46_[0] + PIN right_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 111.78 117.49 113.16 117.79 ; + END + END right_top_grid_pin_47_[0] + PIN right_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 135.63 102 135.77 103.36 ; + END + END right_top_grid_pin_48_[0] + PIN right_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 136.55 102 136.69 103.36 ; + END + END right_top_grid_pin_49_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 0 67.23 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 0 81.49 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.25 0 88.39 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 0 75.97 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.23 0 94.37 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.33 0 87.47 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 0 77.81 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.11 0 84.25 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.49 0 62.63 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.41 0 86.55 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 0 79.65 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 0 68.15 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.17 0 66.31 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.29 0 53.43 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 0 76.89 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.85 0 69.99 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 0 78.73 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 10.05 29.9 10.35 ; + END + END bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 8.01 29.9 8.31 ; + END + END bottom_left_grid_pin_35_[0] + PIN bottom_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 6.65 29.9 6.95 ; + END + END bottom_left_grid_pin_36_[0] + PIN bottom_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 3.25 29.9 3.55 ; + END + END bottom_left_grid_pin_37_[0] + PIN bottom_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 4.61 29.9 4.91 ; + END + END bottom_left_grid_pin_38_[0] + PIN bottom_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 11.41 29.9 11.71 ; + END + END bottom_left_grid_pin_39_[0] + PIN bottom_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 12.77 29.9 13.07 ; + END + END bottom_left_grid_pin_40_[0] + PIN bottom_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 14.13 29.9 14.43 ; + END + END bottom_left_grid_pin_41_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 76.01 1.38 76.31 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 85.53 1.38 85.83 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 86.89 1.38 87.19 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.01 1.38 59.31 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 97.77 1.38 98.07 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 93.69 1.38 93.99 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 92.33 1.38 92.63 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 77.37 1.38 77.67 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 102 7.43 103.36 ; + END + END left_top_grid_pin_42_[0] + PIN left_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 118.85 29.9 119.15 ; + END + END left_top_grid_pin_43_[0] + PIN left_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.07 102 4.21 103.36 ; + END + END left_top_grid_pin_44_[0] + PIN left_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.99 102 5.13 103.36 ; + END + END left_top_grid_pin_45_[0] + PIN left_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 102 2.37 103.36 ; + END + END left_top_grid_pin_46_[0] + PIN left_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 102 3.29 103.36 ; + END + END left_top_grid_pin_47_[0] + PIN left_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.43 102 11.57 103.36 ; + END + END left_top_grid_pin_48_[0] + PIN left_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.51 102 10.65 103.36 ; + END + END left_top_grid_pin_49_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 88.25 141.68 88.55 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 129.2 76.89 130.56 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.11 129.2 61.25 130.56 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 129.2 77.81 130.56 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 129.2 71.37 130.56 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 129.2 98.97 130.56 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.65 129.2 83.79 130.56 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 129.2 70.45 130.56 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 129.2 50.21 130.56 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 129.2 68.61 130.56 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.35 129.2 58.49 130.56 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 129.2 96.67 130.56 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.77 129.2 93.91 130.56 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 129.2 79.65 130.56 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 129.2 64.47 130.56 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 129.2 97.59 130.56 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 129.2 51.13 130.56 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.87 129.2 87.01 130.56 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 129.2 62.17 130.56 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.61 129.2 95.75 130.56 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 129.2 78.73 130.56 ; + END + END chany_top_out[19] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 84.17 141.68 84.47 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 82.81 141.68 83.11 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 62.41 141.68 62.71 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 73.97 141.68 74.27 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 80.09 141.68 80.39 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 71.93 141.68 72.23 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 58.33 141.68 58.63 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 35.21 141.68 35.51 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 46.09 141.68 46.39 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 63.77 141.68 64.07 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 61.05 141.68 61.35 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 78.73 141.68 79.03 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 42.01 141.68 42.31 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 85.53 141.68 85.83 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 47.45 141.68 47.75 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 67.85 141.68 68.15 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 40.65 141.68 40.95 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 66.49 141.68 66.79 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 52.21 141.68 52.51 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 89.61 141.68 89.91 ; + END + END chanx_right_out[19] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.19 0 83.33 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 0 59.87 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.37 0 52.51 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 0 69.07 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 0 96.67 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.69 0 71.83 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.65 0 60.79 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 0 63.55 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.31 0 93.45 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 0 74.13 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 0 80.57 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.57 0 61.71 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 0 97.59 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 0 64.47 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 0 58.95 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.77 0 70.91 1.36 ; + END + END chany_bottom_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 82.81 1.38 83.11 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 74.65 1.38 74.95 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 80.09 1.38 80.39 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.81 1.38 66.11 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 96.41 1.38 96.71 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.81 1.38 32.11 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 88.25 1.38 88.55 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 90.97 1.38 91.27 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 64.45 1.38 64.75 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 28.52 2.48 29 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 28.52 7.92 29 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 28.52 13.36 29 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 28.52 18.8 29 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 28.52 24.24 29 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 141.2 29.68 141.68 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 141.2 35.12 141.68 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 141.2 40.56 141.68 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 141.2 46 141.68 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 141.2 51.44 141.68 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 141.2 56.88 141.68 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 141.2 62.32 141.68 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 141.2 67.76 141.68 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 141.2 73.2 141.68 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 141.2 78.64 141.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 141.2 84.08 141.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 141.2 89.52 141.68 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 141.2 94.96 141.68 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 141.2 100.4 141.68 100.88 ; + RECT 28.52 105.84 29 106.32 ; + RECT 112.68 105.84 113.16 106.32 ; + RECT 28.52 111.28 29 111.76 ; + RECT 112.68 111.28 113.16 111.76 ; + RECT 28.52 116.72 29 117.2 ; + RECT 112.68 116.72 113.16 117.2 ; + RECT 28.52 122.16 29 122.64 ; + RECT 112.68 122.16 113.16 122.64 ; + RECT 28.52 127.6 29 128.08 ; + RECT 112.68 127.6 113.16 128.08 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 138.48 43.28 141.68 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 138.48 84.08 141.68 87.28 ; + RECT 28.52 122.84 31.72 126.04 ; + RECT 109.96 122.84 113.16 126.04 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 134.94 27.2 135.54 27.8 ; + RECT 134.94 102.76 135.54 103.36 ; + RECT 41.1 129.96 41.7 130.56 ; + RECT 70.54 129.96 71.14 130.56 ; + RECT 99.98 129.96 100.58 130.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 28.52 0 113.16 0.24 ; + RECT 28.52 5.2 29 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 28.52 10.64 29 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 28.52 16.08 29 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 28.52 21.52 29 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 141.68 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 141.2 32.4 141.68 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 141.2 37.84 141.68 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 141.2 43.28 141.68 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 141.2 48.72 141.68 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 141.2 54.16 141.68 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 141.2 59.6 141.68 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 141.2 65.04 141.68 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 141.2 70.48 141.68 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 141.2 75.92 141.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 141.2 81.36 141.68 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 141.2 86.8 141.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 141.2 92.24 141.68 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 141.2 97.68 141.68 98.16 ; + RECT 0 103.12 141.68 103.6 ; + RECT 28.52 108.56 29 109.04 ; + RECT 112.68 108.56 113.16 109.04 ; + RECT 28.52 114 29 114.48 ; + RECT 112.68 114 113.16 114.48 ; + RECT 28.52 119.44 29 119.92 ; + RECT 112.68 119.44 113.16 119.92 ; + RECT 28.52 124.88 29 125.36 ; + RECT 112.68 124.88 113.16 125.36 ; + RECT 28.52 130.32 113.16 130.56 ; + LAYER met5 ; + RECT 28.52 4.52 31.72 7.72 ; + RECT 109.96 4.52 113.16 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 138.48 63.68 141.68 66.88 ; + LAYER met4 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 27.2 6.74 27.8 ; + RECT 6.14 102.76 6.74 103.36 ; + RECT 55.82 129.96 56.42 130.56 ; + RECT 85.26 129.96 85.86 130.56 ; + END + END VSS + OBS + LAYER li1 ; + RECT 28.52 130.475 113.16 130.645 ; + RECT 109.48 127.755 113.16 127.925 ; + RECT 28.52 127.755 32.2 127.925 ; + RECT 112.24 125.035 113.16 125.205 ; + RECT 28.52 125.035 32.2 125.205 ; + RECT 112.24 122.315 113.16 122.485 ; + RECT 28.52 122.315 32.2 122.485 ; + RECT 112.24 119.595 113.16 119.765 ; + RECT 28.52 119.595 32.2 119.765 ; + RECT 112.24 116.875 113.16 117.045 ; + RECT 28.52 116.875 32.2 117.045 ; + RECT 112.7 114.155 113.16 114.325 ; + RECT 28.52 114.155 30.36 114.325 ; + RECT 112.24 111.435 113.16 111.605 ; + RECT 28.52 111.435 32.2 111.605 ; + RECT 112.24 108.715 113.16 108.885 ; + RECT 28.52 108.715 32.2 108.885 ; + RECT 112.24 105.995 113.16 106.165 ; + RECT 28.52 105.995 32.2 106.165 ; + RECT 110.4 103.275 141.68 103.445 ; + RECT 0 103.275 30.36 103.445 ; + RECT 139.84 100.555 141.68 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 141.22 97.835 141.68 98.005 ; + RECT 0 97.835 1.84 98.005 ; + RECT 140.76 95.115 141.68 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 140.76 92.395 141.68 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 140.76 89.675 141.68 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 140.76 86.955 141.68 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 140.76 84.235 141.68 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 140.76 81.515 141.68 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 140.76 78.795 141.68 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 140.76 76.075 141.68 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 140.76 73.355 141.68 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 140.76 70.635 141.68 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 140.76 67.915 141.68 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 140.76 65.195 141.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 140.76 62.475 141.68 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 140.76 59.755 141.68 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 140.76 57.035 141.68 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 140.76 54.315 141.68 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 140.76 51.595 141.68 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 140.76 48.875 141.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 140.76 46.155 141.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 140.76 43.435 141.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 141.22 40.715 141.68 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 140.76 37.995 141.68 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 140.76 35.275 141.68 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 140.76 32.555 141.68 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 141.22 29.835 141.68 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 110.86 27.115 141.68 27.285 ; + RECT 0 27.115 32.2 27.285 ; + RECT 112.7 24.395 113.16 24.565 ; + RECT 28.52 24.395 32.2 24.565 ; + RECT 112.24 21.675 113.16 21.845 ; + RECT 28.52 21.675 32.2 21.845 ; + RECT 112.24 18.955 113.16 19.125 ; + RECT 28.52 18.955 32.2 19.125 ; + RECT 109.48 16.235 113.16 16.405 ; + RECT 28.52 16.235 32.2 16.405 ; + RECT 109.48 13.515 113.16 13.685 ; + RECT 28.52 13.515 32.2 13.685 ; + RECT 109.48 10.795 113.16 10.965 ; + RECT 28.52 10.795 32.2 10.965 ; + RECT 109.48 8.075 113.16 8.245 ; + RECT 28.52 8.075 32.2 8.245 ; + RECT 112.24 5.355 113.16 5.525 ; + RECT 28.52 5.355 32.2 5.525 ; + RECT 109.48 2.635 113.16 2.805 ; + RECT 28.52 2.635 32.2 2.805 ; + RECT 28.52 -0.085 113.16 0.085 ; + LAYER met2 ; + RECT 85.42 130.375 85.7 130.745 ; + RECT 55.98 130.375 56.26 130.745 ; + RECT 84.97 128.7 85.23 129.02 ; + RECT 75.31 128.7 75.57 129.02 ; + RECT 6.3 103.175 6.58 103.545 ; + RECT 6.3 27.015 6.58 27.385 ; + RECT 63.81 1.54 64.07 1.86 ; + RECT 69.3 1.57 69.62 1.83 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + POLYGON 112.88 130.28 112.88 103.08 135.35 103.08 135.35 101.72 136.05 101.72 136.05 103.08 136.27 103.08 136.27 101.72 136.97 101.72 136.97 103.08 137.19 103.08 137.19 101.72 137.89 101.72 137.89 103.08 138.11 103.08 138.11 101.72 138.81 101.72 138.81 103.08 139.03 103.08 139.03 101.72 139.73 101.72 139.73 103.08 141.4 103.08 141.4 27.48 112.88 27.48 112.88 0.28 97.87 0.28 97.87 1.64 97.17 1.64 97.17 0.28 96.95 0.28 96.95 1.64 96.25 1.64 96.25 0.28 94.65 0.28 94.65 1.64 93.95 1.64 93.95 0.28 93.73 0.28 93.73 1.64 93.03 1.64 93.03 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 86.83 0.28 86.83 1.64 86.13 1.64 86.13 0.28 84.53 0.28 84.53 1.64 83.83 1.64 83.83 0.28 83.61 0.28 83.61 1.64 82.91 1.64 82.91 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 76.25 0.28 76.25 1.64 75.55 1.64 75.55 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 28.8 0.28 28.8 27.48 2.65 27.48 2.65 28.84 1.95 28.84 1.95 27.48 0.28 27.48 0.28 103.08 1.95 103.08 1.95 101.72 2.65 101.72 2.65 103.08 2.87 103.08 2.87 101.72 3.57 101.72 3.57 103.08 3.79 103.08 3.79 101.72 4.49 101.72 4.49 103.08 4.71 103.08 4.71 101.72 5.41 101.72 5.41 103.08 7.01 103.08 7.01 101.72 7.71 101.72 7.71 103.08 10.23 103.08 10.23 101.72 10.93 101.72 10.93 103.08 11.15 103.08 11.15 101.72 11.85 101.72 11.85 103.08 28.8 103.08 28.8 130.28 30.47 130.28 30.47 128.92 31.17 128.92 31.17 130.28 31.39 130.28 31.39 128.92 32.09 128.92 32.09 130.28 32.31 130.28 32.31 128.92 33.01 128.92 33.01 130.28 49.79 130.28 49.79 128.92 50.49 128.92 50.49 130.28 50.71 130.28 50.71 128.92 51.41 128.92 51.41 130.28 51.63 130.28 51.63 128.92 52.33 128.92 52.33 130.28 52.55 130.28 52.55 128.92 53.25 128.92 53.25 130.28 53.47 130.28 53.47 128.92 54.17 128.92 54.17 130.28 54.39 130.28 54.39 128.92 55.09 128.92 55.09 130.28 57.15 130.28 57.15 128.92 57.85 128.92 57.85 130.28 58.07 130.28 58.07 128.92 58.77 128.92 58.77 130.28 58.99 130.28 58.99 128.92 59.69 128.92 59.69 130.28 59.91 130.28 59.91 128.92 60.61 128.92 60.61 130.28 60.83 130.28 60.83 128.92 61.53 128.92 61.53 130.28 61.75 130.28 61.75 128.92 62.45 128.92 62.45 130.28 63.13 130.28 63.13 128.92 63.83 128.92 63.83 130.28 64.05 130.28 64.05 128.92 64.75 128.92 64.75 130.28 66.35 130.28 66.35 128.92 67.05 128.92 67.05 130.28 67.27 130.28 67.27 128.92 67.97 128.92 67.97 130.28 68.19 130.28 68.19 128.92 68.89 128.92 68.89 130.28 69.11 130.28 69.11 128.92 69.81 128.92 69.81 130.28 70.03 130.28 70.03 128.92 70.73 128.92 70.73 130.28 70.95 130.28 70.95 128.92 71.65 128.92 71.65 130.28 71.87 130.28 71.87 128.92 72.57 128.92 72.57 130.28 72.79 130.28 72.79 128.92 73.49 128.92 73.49 130.28 73.71 130.28 73.71 128.92 74.41 128.92 74.41 130.28 74.63 130.28 74.63 128.92 75.33 128.92 75.33 130.28 75.55 130.28 75.55 128.92 76.25 128.92 76.25 130.28 76.47 130.28 76.47 128.92 77.17 128.92 77.17 130.28 77.39 130.28 77.39 128.92 78.09 128.92 78.09 130.28 78.31 130.28 78.31 128.92 79.01 128.92 79.01 130.28 79.23 130.28 79.23 128.92 79.93 128.92 79.93 130.28 80.15 130.28 80.15 128.92 80.85 128.92 80.85 130.28 81.07 130.28 81.07 128.92 81.77 128.92 81.77 130.28 81.99 130.28 81.99 128.92 82.69 128.92 82.69 130.28 83.37 130.28 83.37 128.92 84.07 128.92 84.07 130.28 84.29 130.28 84.29 128.92 84.99 128.92 84.99 130.28 86.59 130.28 86.59 128.92 87.29 128.92 87.29 130.28 93.49 130.28 93.49 128.92 94.19 128.92 94.19 130.28 95.33 130.28 95.33 128.92 96.03 128.92 96.03 130.28 96.25 130.28 96.25 128.92 96.95 128.92 96.95 130.28 97.17 130.28 97.17 128.92 97.87 128.92 97.87 130.28 98.55 130.28 98.55 128.92 99.25 128.92 99.25 130.28 ; + LAYER met3 ; + POLYGON 85.725 130.725 85.725 130.72 85.94 130.72 85.94 130.4 85.725 130.4 85.725 130.395 85.395 130.395 85.395 130.4 85.18 130.4 85.18 130.72 85.395 130.72 85.395 130.725 ; + POLYGON 56.285 130.725 56.285 130.72 56.5 130.72 56.5 130.4 56.285 130.4 56.285 130.395 55.955 130.395 55.955 130.4 55.74 130.4 55.74 130.72 55.955 130.72 55.955 130.725 ; + POLYGON 6.605 103.525 6.605 103.52 6.82 103.52 6.82 103.2 6.605 103.2 6.605 103.195 6.275 103.195 6.275 103.2 6.06 103.2 6.06 103.52 6.275 103.52 6.275 103.525 ; + POLYGON 140.45 96.03 140.45 95.75 139.9 95.75 139.9 95.73 121.75 95.73 121.75 96.03 ; + POLYGON 8.43 93.31 8.43 93.01 1.78 93.01 1.78 93.03 1.23 93.03 1.23 93.31 ; + POLYGON 10.27 76.99 10.27 76.69 1.78 76.69 1.78 76.71 1.23 76.71 1.23 76.99 ; + POLYGON 2.005 68.845 2.005 68.84 2.03 68.84 2.03 68.52 2.005 68.52 2.005 68.515 1.275 68.515 1.275 68.845 ; + POLYGON 2.03 56.6 2.03 56.59 10.73 56.59 10.73 56.29 2.03 56.29 2.03 56.28 1.65 56.28 1.65 56.6 ; + POLYGON 140.45 41.63 140.45 41.35 139.9 41.35 139.9 41.33 126.81 41.33 126.81 41.63 ; + POLYGON 140.45 40.27 140.45 39.99 139.9 39.99 139.9 39.97 94.61 39.97 94.61 40.27 ; + POLYGON 99.97 36.19 99.97 35.89 1.23 35.89 1.23 36.17 1.78 36.17 1.78 36.19 ; + POLYGON 6.605 27.365 6.605 27.36 6.82 27.36 6.82 27.04 6.605 27.04 6.605 27.035 6.275 27.035 6.275 27.04 6.06 27.04 6.06 27.36 6.275 27.36 6.275 27.365 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 112.76 130.16 112.76 127.03 111.38 127.03 111.38 125.93 112.76 125.93 112.76 119.55 111.38 119.55 111.38 118.45 112.76 118.45 112.76 118.19 111.38 118.19 111.38 117.09 112.76 117.09 112.76 102.96 141.28 102.96 141.28 99.83 139.9 99.83 139.9 98.73 141.28 98.73 141.28 97.11 139.9 97.11 139.9 96.01 141.28 96.01 141.28 95.75 139.9 95.75 139.9 94.65 141.28 94.65 141.28 94.39 139.9 94.39 139.9 93.29 141.28 93.29 141.28 91.67 139.9 91.67 139.9 90.57 141.28 90.57 141.28 90.31 139.9 90.31 139.9 89.21 141.28 89.21 141.28 88.95 139.9 88.95 139.9 87.85 141.28 87.85 141.28 86.23 139.9 86.23 139.9 85.13 141.28 85.13 141.28 84.87 139.9 84.87 139.9 83.77 141.28 83.77 141.28 83.51 139.9 83.51 139.9 82.41 141.28 82.41 141.28 80.79 139.9 80.79 139.9 79.69 141.28 79.69 141.28 79.43 139.9 79.43 139.9 78.33 141.28 78.33 141.28 78.07 139.9 78.07 139.9 76.97 141.28 76.97 141.28 74.67 139.9 74.67 139.9 73.57 141.28 73.57 141.28 72.63 139.9 72.63 139.9 71.53 141.28 71.53 141.28 69.91 139.9 69.91 139.9 68.81 141.28 68.81 141.28 68.55 139.9 68.55 139.9 67.45 141.28 67.45 141.28 67.19 139.9 67.19 139.9 66.09 141.28 66.09 141.28 65.83 139.9 65.83 139.9 64.73 141.28 64.73 141.28 64.47 139.9 64.47 139.9 63.37 141.28 63.37 141.28 63.11 139.9 63.11 139.9 62.01 141.28 62.01 141.28 61.75 139.9 61.75 139.9 60.65 141.28 60.65 141.28 59.03 139.9 59.03 139.9 57.93 141.28 57.93 141.28 57.67 139.9 57.67 139.9 56.57 141.28 56.57 141.28 56.31 139.9 56.31 139.9 55.21 141.28 55.21 141.28 52.91 139.9 52.91 139.9 51.81 141.28 51.81 141.28 51.55 139.9 51.55 139.9 50.45 141.28 50.45 141.28 49.51 139.9 49.51 139.9 48.41 141.28 48.41 141.28 48.15 139.9 48.15 139.9 47.05 141.28 47.05 141.28 46.79 139.9 46.79 139.9 45.69 141.28 45.69 141.28 45.43 139.9 45.43 139.9 44.33 141.28 44.33 141.28 44.07 139.9 44.07 139.9 42.97 141.28 42.97 141.28 42.71 139.9 42.71 139.9 41.61 141.28 41.61 141.28 41.35 139.9 41.35 139.9 40.25 141.28 40.25 141.28 39.99 139.9 39.99 139.9 38.89 141.28 38.89 141.28 38.63 139.9 38.63 139.9 37.53 141.28 37.53 141.28 37.27 139.9 37.27 139.9 36.17 141.28 36.17 141.28 35.91 139.9 35.91 139.9 34.81 141.28 34.81 141.28 34.55 139.9 34.55 139.9 33.45 141.28 33.45 141.28 33.19 139.9 33.19 139.9 32.09 141.28 32.09 141.28 31.83 139.9 31.83 139.9 30.73 141.28 30.73 141.28 27.6 112.76 27.6 112.76 0.4 28.92 0.4 28.92 2.85 30.3 2.85 30.3 3.95 28.92 3.95 28.92 4.21 30.3 4.21 30.3 5.31 28.92 5.31 28.92 6.25 30.3 6.25 30.3 7.35 28.92 7.35 28.92 7.61 30.3 7.61 30.3 8.71 28.92 8.71 28.92 9.65 30.3 9.65 30.3 10.75 28.92 10.75 28.92 11.01 30.3 11.01 30.3 12.11 28.92 12.11 28.92 12.37 30.3 12.37 30.3 13.47 28.92 13.47 28.92 13.73 30.3 13.73 30.3 14.83 28.92 14.83 28.92 27.6 0.4 27.6 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 93.29 1.78 93.29 1.78 94.39 0.4 94.39 0.4 96.01 1.78 96.01 1.78 97.11 0.4 97.11 0.4 97.37 1.78 97.37 1.78 98.47 0.4 98.47 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 102.96 28.92 102.96 28.92 117.09 30.3 117.09 30.3 118.19 28.92 118.19 28.92 118.45 30.3 118.45 30.3 119.55 28.92 119.55 28.92 121.85 30.3 121.85 30.3 122.95 28.92 122.95 28.92 123.21 30.3 123.21 30.3 124.31 28.92 124.31 28.92 124.57 30.3 124.57 30.3 125.67 28.92 125.67 28.92 126.61 30.3 126.61 30.3 127.71 28.92 127.71 28.92 130.16 ; + LAYER met4 ; + POLYGON 112.76 130.16 112.76 102.96 134.54 102.96 134.54 102.36 135.94 102.36 135.94 102.96 141.28 102.96 141.28 27.6 135.94 27.6 135.94 28.2 134.54 28.2 134.54 27.6 112.76 27.6 112.76 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 28.92 0.4 28.92 27.6 7.14 27.6 7.14 28.2 5.74 28.2 5.74 27.6 0.4 27.6 0.4 102.96 5.74 102.96 5.74 102.36 7.14 102.36 7.14 102.96 28.92 102.96 28.92 130.16 40.7 130.16 40.7 129.56 42.1 129.56 42.1 130.16 55.42 130.16 55.42 129.56 56.82 129.56 56.82 130.16 70.14 130.16 70.14 129.56 71.54 129.56 71.54 130.16 84.86 130.16 84.86 129.56 86.26 129.56 86.26 130.16 99.58 130.16 99.58 129.56 100.98 129.56 100.98 130.16 ; + LAYER met5 ; + POLYGON 106.76 127.36 106.76 119.64 109.96 119.64 109.96 100.16 138.48 100.16 138.48 90.48 135.28 90.48 135.28 80.88 138.48 80.88 138.48 70.08 135.28 70.08 135.28 60.48 138.48 60.48 138.48 49.68 135.28 49.68 135.28 40.08 138.48 40.08 138.48 30.4 109.96 30.4 109.96 10.92 106.76 10.92 106.76 3.2 34.92 3.2 34.92 10.92 31.72 10.92 31.72 30.4 3.2 30.4 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 100.16 31.72 100.16 31.72 119.64 34.92 119.64 34.92 127.36 ; + LAYER met1 ; + POLYGON 112.88 130.04 112.88 128.36 112.4 128.36 112.4 127.32 112.88 127.32 112.88 125.64 112.4 125.64 112.4 124.6 112.88 124.6 112.88 122.92 112.4 122.92 112.4 121.88 112.88 121.88 112.88 120.2 112.4 120.2 112.4 119.16 112.88 119.16 112.88 117.48 112.4 117.48 112.4 116.44 112.88 116.44 112.88 114.76 112.4 114.76 112.4 113.72 112.88 113.72 112.88 112.04 112.4 112.04 112.4 111 112.88 111 112.88 109.32 112.4 109.32 112.4 108.28 112.88 108.28 112.88 106.6 112.4 106.6 112.4 105.56 112.88 105.56 112.88 103.88 28.8 103.88 28.8 105.56 29.28 105.56 29.28 106.6 28.8 106.6 28.8 108.28 29.28 108.28 29.28 109.32 28.8 109.32 28.8 111 29.28 111 29.28 112.04 28.8 112.04 28.8 113.72 29.28 113.72 29.28 114.76 28.8 114.76 28.8 116.44 29.28 116.44 29.28 117.48 28.8 117.48 28.8 119.16 29.28 119.16 29.28 120.2 28.8 120.2 28.8 121.88 29.28 121.88 29.28 122.92 28.8 122.92 28.8 124.6 29.28 124.6 29.28 125.64 28.8 125.64 28.8 127.32 29.28 127.32 29.28 128.36 28.8 128.36 28.8 130.04 ; + POLYGON 141.4 102.84 141.4 101.16 140.92 101.16 140.92 100.12 141.4 100.12 141.4 98.44 140.92 98.44 140.92 97.4 141.4 97.4 141.4 95.72 140.92 95.72 140.92 94.68 141.4 94.68 141.4 93 140.92 93 140.92 91.96 141.4 91.96 141.4 90.28 140.92 90.28 140.92 89.24 141.4 89.24 141.4 87.56 140.92 87.56 140.92 86.52 141.4 86.52 141.4 84.84 140.92 84.84 140.92 83.8 141.4 83.8 141.4 82.12 140.92 82.12 140.92 81.08 141.4 81.08 141.4 79.4 140.92 79.4 140.92 78.36 141.4 78.36 141.4 76.68 140.92 76.68 140.92 75.64 141.4 75.64 141.4 73.96 140.92 73.96 140.92 72.92 141.4 72.92 141.4 71.24 140.92 71.24 140.92 70.2 141.4 70.2 141.4 68.52 140.92 68.52 140.92 67.48 141.4 67.48 141.4 65.8 140.92 65.8 140.92 64.76 141.4 64.76 141.4 63.08 140.92 63.08 140.92 62.04 141.4 62.04 141.4 60.36 140.92 60.36 140.92 59.32 141.4 59.32 141.4 57.64 140.92 57.64 140.92 56.6 141.4 56.6 141.4 54.92 140.92 54.92 140.92 53.88 141.4 53.88 141.4 52.2 140.92 52.2 140.92 51.16 141.4 51.16 141.4 49.48 140.92 49.48 140.92 48.44 141.4 48.44 141.4 46.76 140.92 46.76 140.92 45.72 141.4 45.72 141.4 44.04 140.92 44.04 140.92 43 141.4 43 141.4 41.32 140.92 41.32 140.92 40.28 141.4 40.28 141.4 38.6 140.92 38.6 140.92 37.56 141.4 37.56 141.4 35.88 140.92 35.88 140.92 34.84 141.4 34.84 141.4 33.16 140.92 33.16 140.92 32.12 141.4 32.12 141.4 30.44 140.92 30.44 140.92 29.4 141.4 29.4 141.4 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 28.8 0.52 28.8 2.2 29.28 2.2 29.28 3.24 28.8 3.24 28.8 4.92 29.28 4.92 29.28 5.96 28.8 5.96 28.8 7.64 29.28 7.64 29.28 8.68 28.8 8.68 28.8 10.36 29.28 10.36 29.28 11.4 28.8 11.4 28.8 13.08 29.28 13.08 29.28 14.12 28.8 14.12 28.8 15.8 29.28 15.8 29.28 16.84 28.8 16.84 28.8 18.52 29.28 18.52 29.28 19.56 28.8 19.56 28.8 21.24 29.28 21.24 29.28 22.28 28.8 22.28 28.8 23.96 29.28 23.96 29.28 25 28.8 25 28.8 26.68 ; + LAYER li1 ; + POLYGON 112.82 130.22 112.82 103.02 141.34 103.02 141.34 27.54 112.82 27.54 112.82 0.34 28.86 0.34 28.86 27.54 0.34 27.54 0.34 103.02 28.86 103.02 28.86 130.22 ; + LAYER mcon ; + RECT 112.845 130.475 113.015 130.645 ; + RECT 112.385 130.475 112.555 130.645 ; + RECT 111.925 130.475 112.095 130.645 ; + RECT 111.465 130.475 111.635 130.645 ; + RECT 111.005 130.475 111.175 130.645 ; + RECT 110.545 130.475 110.715 130.645 ; + RECT 110.085 130.475 110.255 130.645 ; + RECT 109.625 130.475 109.795 130.645 ; + RECT 109.165 130.475 109.335 130.645 ; + RECT 108.705 130.475 108.875 130.645 ; + RECT 108.245 130.475 108.415 130.645 ; + RECT 107.785 130.475 107.955 130.645 ; + RECT 107.325 130.475 107.495 130.645 ; + RECT 106.865 130.475 107.035 130.645 ; + RECT 106.405 130.475 106.575 130.645 ; + RECT 105.945 130.475 106.115 130.645 ; + RECT 105.485 130.475 105.655 130.645 ; + RECT 105.025 130.475 105.195 130.645 ; + RECT 104.565 130.475 104.735 130.645 ; + RECT 104.105 130.475 104.275 130.645 ; + RECT 103.645 130.475 103.815 130.645 ; + RECT 103.185 130.475 103.355 130.645 ; + RECT 102.725 130.475 102.895 130.645 ; + RECT 102.265 130.475 102.435 130.645 ; + RECT 101.805 130.475 101.975 130.645 ; + RECT 101.345 130.475 101.515 130.645 ; + RECT 100.885 130.475 101.055 130.645 ; + RECT 100.425 130.475 100.595 130.645 ; + RECT 99.965 130.475 100.135 130.645 ; + RECT 99.505 130.475 99.675 130.645 ; + RECT 99.045 130.475 99.215 130.645 ; + RECT 98.585 130.475 98.755 130.645 ; + RECT 98.125 130.475 98.295 130.645 ; + RECT 97.665 130.475 97.835 130.645 ; + RECT 97.205 130.475 97.375 130.645 ; + RECT 96.745 130.475 96.915 130.645 ; + RECT 96.285 130.475 96.455 130.645 ; + RECT 95.825 130.475 95.995 130.645 ; + RECT 95.365 130.475 95.535 130.645 ; + RECT 94.905 130.475 95.075 130.645 ; + RECT 94.445 130.475 94.615 130.645 ; + RECT 93.985 130.475 94.155 130.645 ; + RECT 93.525 130.475 93.695 130.645 ; + RECT 93.065 130.475 93.235 130.645 ; + RECT 92.605 130.475 92.775 130.645 ; + RECT 92.145 130.475 92.315 130.645 ; + RECT 91.685 130.475 91.855 130.645 ; + RECT 91.225 130.475 91.395 130.645 ; + RECT 90.765 130.475 90.935 130.645 ; + RECT 90.305 130.475 90.475 130.645 ; + RECT 89.845 130.475 90.015 130.645 ; + RECT 89.385 130.475 89.555 130.645 ; + RECT 88.925 130.475 89.095 130.645 ; + RECT 88.465 130.475 88.635 130.645 ; + RECT 88.005 130.475 88.175 130.645 ; + RECT 87.545 130.475 87.715 130.645 ; + RECT 87.085 130.475 87.255 130.645 ; + RECT 86.625 130.475 86.795 130.645 ; + RECT 86.165 130.475 86.335 130.645 ; + RECT 85.705 130.475 85.875 130.645 ; + RECT 85.245 130.475 85.415 130.645 ; + RECT 84.785 130.475 84.955 130.645 ; + RECT 84.325 130.475 84.495 130.645 ; + RECT 83.865 130.475 84.035 130.645 ; + RECT 83.405 130.475 83.575 130.645 ; + RECT 82.945 130.475 83.115 130.645 ; + RECT 82.485 130.475 82.655 130.645 ; + RECT 82.025 130.475 82.195 130.645 ; + RECT 81.565 130.475 81.735 130.645 ; + RECT 81.105 130.475 81.275 130.645 ; + RECT 80.645 130.475 80.815 130.645 ; + RECT 80.185 130.475 80.355 130.645 ; + RECT 79.725 130.475 79.895 130.645 ; + RECT 79.265 130.475 79.435 130.645 ; + RECT 78.805 130.475 78.975 130.645 ; + RECT 78.345 130.475 78.515 130.645 ; + RECT 77.885 130.475 78.055 130.645 ; + RECT 77.425 130.475 77.595 130.645 ; + RECT 76.965 130.475 77.135 130.645 ; + RECT 76.505 130.475 76.675 130.645 ; + RECT 76.045 130.475 76.215 130.645 ; + RECT 75.585 130.475 75.755 130.645 ; + RECT 75.125 130.475 75.295 130.645 ; + RECT 74.665 130.475 74.835 130.645 ; + RECT 74.205 130.475 74.375 130.645 ; + RECT 73.745 130.475 73.915 130.645 ; + RECT 73.285 130.475 73.455 130.645 ; + RECT 72.825 130.475 72.995 130.645 ; + RECT 72.365 130.475 72.535 130.645 ; + RECT 71.905 130.475 72.075 130.645 ; + RECT 71.445 130.475 71.615 130.645 ; + RECT 70.985 130.475 71.155 130.645 ; + RECT 70.525 130.475 70.695 130.645 ; + RECT 70.065 130.475 70.235 130.645 ; + RECT 69.605 130.475 69.775 130.645 ; + RECT 69.145 130.475 69.315 130.645 ; + RECT 68.685 130.475 68.855 130.645 ; + RECT 68.225 130.475 68.395 130.645 ; + RECT 67.765 130.475 67.935 130.645 ; + RECT 67.305 130.475 67.475 130.645 ; + RECT 66.845 130.475 67.015 130.645 ; + RECT 66.385 130.475 66.555 130.645 ; + RECT 65.925 130.475 66.095 130.645 ; + RECT 65.465 130.475 65.635 130.645 ; + RECT 65.005 130.475 65.175 130.645 ; + RECT 64.545 130.475 64.715 130.645 ; + RECT 64.085 130.475 64.255 130.645 ; + RECT 63.625 130.475 63.795 130.645 ; + RECT 63.165 130.475 63.335 130.645 ; + RECT 62.705 130.475 62.875 130.645 ; + RECT 62.245 130.475 62.415 130.645 ; + RECT 61.785 130.475 61.955 130.645 ; + RECT 61.325 130.475 61.495 130.645 ; + RECT 60.865 130.475 61.035 130.645 ; + RECT 60.405 130.475 60.575 130.645 ; + RECT 59.945 130.475 60.115 130.645 ; + RECT 59.485 130.475 59.655 130.645 ; + RECT 59.025 130.475 59.195 130.645 ; + RECT 58.565 130.475 58.735 130.645 ; + RECT 58.105 130.475 58.275 130.645 ; + RECT 57.645 130.475 57.815 130.645 ; + RECT 57.185 130.475 57.355 130.645 ; + RECT 56.725 130.475 56.895 130.645 ; + RECT 56.265 130.475 56.435 130.645 ; + RECT 55.805 130.475 55.975 130.645 ; + RECT 55.345 130.475 55.515 130.645 ; + RECT 54.885 130.475 55.055 130.645 ; + RECT 54.425 130.475 54.595 130.645 ; + RECT 53.965 130.475 54.135 130.645 ; + RECT 53.505 130.475 53.675 130.645 ; + RECT 53.045 130.475 53.215 130.645 ; + RECT 52.585 130.475 52.755 130.645 ; + RECT 52.125 130.475 52.295 130.645 ; + RECT 51.665 130.475 51.835 130.645 ; + RECT 51.205 130.475 51.375 130.645 ; + RECT 50.745 130.475 50.915 130.645 ; + RECT 50.285 130.475 50.455 130.645 ; + RECT 49.825 130.475 49.995 130.645 ; + RECT 49.365 130.475 49.535 130.645 ; + RECT 48.905 130.475 49.075 130.645 ; + RECT 48.445 130.475 48.615 130.645 ; + RECT 47.985 130.475 48.155 130.645 ; + RECT 47.525 130.475 47.695 130.645 ; + RECT 47.065 130.475 47.235 130.645 ; + RECT 46.605 130.475 46.775 130.645 ; + RECT 46.145 130.475 46.315 130.645 ; + RECT 45.685 130.475 45.855 130.645 ; + RECT 45.225 130.475 45.395 130.645 ; + RECT 44.765 130.475 44.935 130.645 ; + RECT 44.305 130.475 44.475 130.645 ; + RECT 43.845 130.475 44.015 130.645 ; + RECT 43.385 130.475 43.555 130.645 ; + RECT 42.925 130.475 43.095 130.645 ; + RECT 42.465 130.475 42.635 130.645 ; + RECT 42.005 130.475 42.175 130.645 ; + RECT 41.545 130.475 41.715 130.645 ; + RECT 41.085 130.475 41.255 130.645 ; + RECT 40.625 130.475 40.795 130.645 ; + RECT 40.165 130.475 40.335 130.645 ; + RECT 39.705 130.475 39.875 130.645 ; + RECT 39.245 130.475 39.415 130.645 ; + RECT 38.785 130.475 38.955 130.645 ; + RECT 38.325 130.475 38.495 130.645 ; + RECT 37.865 130.475 38.035 130.645 ; + RECT 37.405 130.475 37.575 130.645 ; + RECT 36.945 130.475 37.115 130.645 ; + RECT 36.485 130.475 36.655 130.645 ; + RECT 36.025 130.475 36.195 130.645 ; + RECT 35.565 130.475 35.735 130.645 ; + RECT 35.105 130.475 35.275 130.645 ; + RECT 34.645 130.475 34.815 130.645 ; + RECT 34.185 130.475 34.355 130.645 ; + RECT 33.725 130.475 33.895 130.645 ; + RECT 33.265 130.475 33.435 130.645 ; + RECT 32.805 130.475 32.975 130.645 ; + RECT 32.345 130.475 32.515 130.645 ; + RECT 31.885 130.475 32.055 130.645 ; + RECT 31.425 130.475 31.595 130.645 ; + RECT 30.965 130.475 31.135 130.645 ; + RECT 30.505 130.475 30.675 130.645 ; + RECT 30.045 130.475 30.215 130.645 ; + RECT 29.585 130.475 29.755 130.645 ; + RECT 29.125 130.475 29.295 130.645 ; + RECT 28.665 130.475 28.835 130.645 ; + RECT 112.845 127.755 113.015 127.925 ; + RECT 112.385 127.755 112.555 127.925 ; + RECT 29.125 127.755 29.295 127.925 ; + RECT 28.665 127.755 28.835 127.925 ; + RECT 112.845 125.035 113.015 125.205 ; + RECT 112.385 125.035 112.555 125.205 ; + RECT 29.125 125.035 29.295 125.205 ; + RECT 28.665 125.035 28.835 125.205 ; + RECT 112.845 122.315 113.015 122.485 ; + RECT 112.385 122.315 112.555 122.485 ; + RECT 29.125 122.315 29.295 122.485 ; + RECT 28.665 122.315 28.835 122.485 ; + RECT 112.845 119.595 113.015 119.765 ; + RECT 112.385 119.595 112.555 119.765 ; + RECT 29.125 119.595 29.295 119.765 ; + RECT 28.665 119.595 28.835 119.765 ; + RECT 112.845 116.875 113.015 117.045 ; + RECT 112.385 116.875 112.555 117.045 ; + RECT 29.125 116.875 29.295 117.045 ; + RECT 28.665 116.875 28.835 117.045 ; + RECT 112.845 114.155 113.015 114.325 ; + RECT 112.385 114.155 112.555 114.325 ; + RECT 29.125 114.155 29.295 114.325 ; + RECT 28.665 114.155 28.835 114.325 ; + RECT 112.845 111.435 113.015 111.605 ; + RECT 112.385 111.435 112.555 111.605 ; + RECT 29.125 111.435 29.295 111.605 ; + RECT 28.665 111.435 28.835 111.605 ; + RECT 112.845 108.715 113.015 108.885 ; + RECT 112.385 108.715 112.555 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 112.845 105.995 113.015 106.165 ; + RECT 112.385 105.995 112.555 106.165 ; + RECT 29.125 105.995 29.295 106.165 ; + RECT 28.665 105.995 28.835 106.165 ; + RECT 141.365 103.275 141.535 103.445 ; + RECT 140.905 103.275 141.075 103.445 ; + RECT 140.445 103.275 140.615 103.445 ; + RECT 139.985 103.275 140.155 103.445 ; + RECT 139.525 103.275 139.695 103.445 ; + RECT 139.065 103.275 139.235 103.445 ; + RECT 138.605 103.275 138.775 103.445 ; + RECT 138.145 103.275 138.315 103.445 ; + RECT 137.685 103.275 137.855 103.445 ; + RECT 137.225 103.275 137.395 103.445 ; + RECT 136.765 103.275 136.935 103.445 ; + RECT 136.305 103.275 136.475 103.445 ; + RECT 135.845 103.275 136.015 103.445 ; + RECT 135.385 103.275 135.555 103.445 ; + RECT 134.925 103.275 135.095 103.445 ; + RECT 134.465 103.275 134.635 103.445 ; + RECT 134.005 103.275 134.175 103.445 ; + RECT 133.545 103.275 133.715 103.445 ; + RECT 133.085 103.275 133.255 103.445 ; + RECT 132.625 103.275 132.795 103.445 ; + RECT 132.165 103.275 132.335 103.445 ; + RECT 131.705 103.275 131.875 103.445 ; + RECT 131.245 103.275 131.415 103.445 ; + RECT 130.785 103.275 130.955 103.445 ; + RECT 130.325 103.275 130.495 103.445 ; + RECT 129.865 103.275 130.035 103.445 ; + RECT 129.405 103.275 129.575 103.445 ; + RECT 128.945 103.275 129.115 103.445 ; + RECT 128.485 103.275 128.655 103.445 ; + RECT 128.025 103.275 128.195 103.445 ; + RECT 127.565 103.275 127.735 103.445 ; + RECT 127.105 103.275 127.275 103.445 ; + RECT 126.645 103.275 126.815 103.445 ; + RECT 126.185 103.275 126.355 103.445 ; + RECT 125.725 103.275 125.895 103.445 ; + RECT 125.265 103.275 125.435 103.445 ; + RECT 124.805 103.275 124.975 103.445 ; + RECT 124.345 103.275 124.515 103.445 ; + RECT 123.885 103.275 124.055 103.445 ; + RECT 123.425 103.275 123.595 103.445 ; + RECT 122.965 103.275 123.135 103.445 ; + RECT 122.505 103.275 122.675 103.445 ; + RECT 122.045 103.275 122.215 103.445 ; + RECT 121.585 103.275 121.755 103.445 ; + RECT 121.125 103.275 121.295 103.445 ; + RECT 120.665 103.275 120.835 103.445 ; + RECT 120.205 103.275 120.375 103.445 ; + RECT 119.745 103.275 119.915 103.445 ; + RECT 119.285 103.275 119.455 103.445 ; + RECT 118.825 103.275 118.995 103.445 ; + RECT 118.365 103.275 118.535 103.445 ; + RECT 117.905 103.275 118.075 103.445 ; + RECT 117.445 103.275 117.615 103.445 ; + RECT 116.985 103.275 117.155 103.445 ; + RECT 116.525 103.275 116.695 103.445 ; + RECT 116.065 103.275 116.235 103.445 ; + RECT 115.605 103.275 115.775 103.445 ; + RECT 115.145 103.275 115.315 103.445 ; + RECT 114.685 103.275 114.855 103.445 ; + RECT 114.225 103.275 114.395 103.445 ; + RECT 113.765 103.275 113.935 103.445 ; + RECT 113.305 103.275 113.475 103.445 ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 141.365 100.555 141.535 100.725 ; + RECT 140.905 100.555 141.075 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 141.365 97.835 141.535 98.005 ; + RECT 140.905 97.835 141.075 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 141.365 95.115 141.535 95.285 ; + RECT 140.905 95.115 141.075 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 141.365 92.395 141.535 92.565 ; + RECT 140.905 92.395 141.075 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 141.365 89.675 141.535 89.845 ; + RECT 140.905 89.675 141.075 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 141.365 86.955 141.535 87.125 ; + RECT 140.905 86.955 141.075 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 141.365 84.235 141.535 84.405 ; + RECT 140.905 84.235 141.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 141.365 81.515 141.535 81.685 ; + RECT 140.905 81.515 141.075 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 141.365 78.795 141.535 78.965 ; + RECT 140.905 78.795 141.075 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 141.365 76.075 141.535 76.245 ; + RECT 140.905 76.075 141.075 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 141.365 73.355 141.535 73.525 ; + RECT 140.905 73.355 141.075 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 141.365 70.635 141.535 70.805 ; + RECT 140.905 70.635 141.075 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 141.365 67.915 141.535 68.085 ; + RECT 140.905 67.915 141.075 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 141.365 65.195 141.535 65.365 ; + RECT 140.905 65.195 141.075 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 141.365 62.475 141.535 62.645 ; + RECT 140.905 62.475 141.075 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 141.365 59.755 141.535 59.925 ; + RECT 140.905 59.755 141.075 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 141.365 57.035 141.535 57.205 ; + RECT 140.905 57.035 141.075 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 141.365 54.315 141.535 54.485 ; + RECT 140.905 54.315 141.075 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 141.365 51.595 141.535 51.765 ; + RECT 140.905 51.595 141.075 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 141.365 48.875 141.535 49.045 ; + RECT 140.905 48.875 141.075 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 141.365 46.155 141.535 46.325 ; + RECT 140.905 46.155 141.075 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 141.365 43.435 141.535 43.605 ; + RECT 140.905 43.435 141.075 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 141.365 40.715 141.535 40.885 ; + RECT 140.905 40.715 141.075 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 141.365 37.995 141.535 38.165 ; + RECT 140.905 37.995 141.075 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 141.365 35.275 141.535 35.445 ; + RECT 140.905 35.275 141.075 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 141.365 32.555 141.535 32.725 ; + RECT 140.905 32.555 141.075 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 141.365 29.835 141.535 30.005 ; + RECT 140.905 29.835 141.075 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 141.365 27.115 141.535 27.285 ; + RECT 140.905 27.115 141.075 27.285 ; + RECT 140.445 27.115 140.615 27.285 ; + RECT 139.985 27.115 140.155 27.285 ; + RECT 139.525 27.115 139.695 27.285 ; + RECT 139.065 27.115 139.235 27.285 ; + RECT 138.605 27.115 138.775 27.285 ; + RECT 138.145 27.115 138.315 27.285 ; + RECT 137.685 27.115 137.855 27.285 ; + RECT 137.225 27.115 137.395 27.285 ; + RECT 136.765 27.115 136.935 27.285 ; + RECT 136.305 27.115 136.475 27.285 ; + RECT 135.845 27.115 136.015 27.285 ; + RECT 135.385 27.115 135.555 27.285 ; + RECT 134.925 27.115 135.095 27.285 ; + RECT 134.465 27.115 134.635 27.285 ; + RECT 134.005 27.115 134.175 27.285 ; + RECT 133.545 27.115 133.715 27.285 ; + RECT 133.085 27.115 133.255 27.285 ; + RECT 132.625 27.115 132.795 27.285 ; + RECT 132.165 27.115 132.335 27.285 ; + RECT 131.705 27.115 131.875 27.285 ; + RECT 131.245 27.115 131.415 27.285 ; + RECT 130.785 27.115 130.955 27.285 ; + RECT 130.325 27.115 130.495 27.285 ; + RECT 129.865 27.115 130.035 27.285 ; + RECT 129.405 27.115 129.575 27.285 ; + RECT 128.945 27.115 129.115 27.285 ; + RECT 128.485 27.115 128.655 27.285 ; + RECT 128.025 27.115 128.195 27.285 ; + RECT 127.565 27.115 127.735 27.285 ; + RECT 127.105 27.115 127.275 27.285 ; + RECT 126.645 27.115 126.815 27.285 ; + RECT 126.185 27.115 126.355 27.285 ; + RECT 125.725 27.115 125.895 27.285 ; + RECT 125.265 27.115 125.435 27.285 ; + RECT 124.805 27.115 124.975 27.285 ; + RECT 124.345 27.115 124.515 27.285 ; + RECT 123.885 27.115 124.055 27.285 ; + RECT 123.425 27.115 123.595 27.285 ; + RECT 122.965 27.115 123.135 27.285 ; + RECT 122.505 27.115 122.675 27.285 ; + RECT 122.045 27.115 122.215 27.285 ; + RECT 121.585 27.115 121.755 27.285 ; + RECT 121.125 27.115 121.295 27.285 ; + RECT 120.665 27.115 120.835 27.285 ; + RECT 120.205 27.115 120.375 27.285 ; + RECT 119.745 27.115 119.915 27.285 ; + RECT 119.285 27.115 119.455 27.285 ; + RECT 118.825 27.115 118.995 27.285 ; + RECT 118.365 27.115 118.535 27.285 ; + RECT 117.905 27.115 118.075 27.285 ; + RECT 117.445 27.115 117.615 27.285 ; + RECT 116.985 27.115 117.155 27.285 ; + RECT 116.525 27.115 116.695 27.285 ; + RECT 116.065 27.115 116.235 27.285 ; + RECT 115.605 27.115 115.775 27.285 ; + RECT 115.145 27.115 115.315 27.285 ; + RECT 114.685 27.115 114.855 27.285 ; + RECT 114.225 27.115 114.395 27.285 ; + RECT 113.765 27.115 113.935 27.285 ; + RECT 113.305 27.115 113.475 27.285 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 29.125 24.395 29.295 24.565 ; + RECT 28.665 24.395 28.835 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 29.125 21.675 29.295 21.845 ; + RECT 28.665 21.675 28.835 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 29.125 18.955 29.295 19.125 ; + RECT 28.665 18.955 28.835 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 29.125 16.235 29.295 16.405 ; + RECT 28.665 16.235 28.835 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 29.125 13.515 29.295 13.685 ; + RECT 28.665 13.515 28.835 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 29.125 8.075 29.295 8.245 ; + RECT 28.665 8.075 28.835 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 29.125 5.355 29.295 5.525 ; + RECT 28.665 5.355 28.835 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 29.125 2.635 29.295 2.805 ; + RECT 28.665 2.635 28.835 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + LAYER via ; + RECT 85.485 130.485 85.635 130.635 ; + RECT 56.045 130.485 56.195 130.635 ; + RECT 62.025 128.785 62.175 128.935 ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 6.365 103.285 6.515 103.435 ; + RECT 139.305 101.585 139.455 101.735 ; + RECT 4.985 101.585 5.135 101.735 ; + RECT 4.065 101.585 4.215 101.735 ; + RECT 85.485 27.125 85.635 27.275 ; + RECT 56.045 27.125 56.195 27.275 ; + RECT 6.365 27.125 6.515 27.275 ; + RECT 80.425 1.625 80.575 1.775 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + LAYER via2 ; + RECT 85.46 130.46 85.66 130.66 ; + RECT 56.02 130.46 56.22 130.66 ; + RECT 29.8 125.02 30 125.22 ; + RECT 29.8 118.9 30 119.1 ; + RECT 111.68 117.54 111.88 117.74 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.28 99.18 1.48 99.38 ; + RECT 1.28 91.02 1.48 91.22 ; + RECT 1.74 64.5 1.94 64.7 ; + RECT 139.74 63.82 139.94 64.02 ; + RECT 1.74 52.94 1.94 53.14 ; + RECT 140.2 48.86 140.4 49.06 ; + RECT 1.74 47.5 1.94 47.7 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 29.8 3.3 30 3.5 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via3 ; + RECT 85.46 130.46 85.66 130.66 ; + RECT 56.02 130.46 56.22 130.66 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.74 65.86 1.94 66.06 ; + RECT 1.74 54.3 1.94 54.5 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via4 ; + RECT 134.84 86.08 135.64 86.88 ; + RECT 134.84 84.48 135.64 85.28 ; + RECT 6.04 65.68 6.84 66.48 ; + RECT 6.04 64.08 6.84 64.88 ; + RECT 134.84 45.28 135.64 46.08 ; + RECT 134.84 43.68 135.64 44.48 ; + LAYER fieldpoly ; + POLYGON 113.02 130.42 113.02 103.22 141.54 103.22 141.54 27.34 113.02 27.34 113.02 0.14 28.66 0.14 28.66 27.34 0.14 27.34 0.14 103.22 28.66 103.22 28.66 130.42 ; + LAYER diff ; + POLYGON 113.16 130.56 113.16 103.36 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER nwell ; + POLYGON 113.35 129.255 113.35 126.425 112.51 126.425 112.51 127.65 109.29 127.65 109.29 129.255 ; + RECT 28.33 126.425 32.39 129.255 ; + POLYGON 113.35 123.815 113.35 120.985 112.51 120.985 112.51 122.21 112.05 122.21 112.05 123.815 ; + POLYGON 30.55 123.815 30.55 122.59 32.39 122.59 32.39 120.985 28.33 120.985 28.33 123.815 ; + POLYGON 113.35 118.375 113.35 115.545 112.51 115.545 112.51 116.77 112.05 116.77 112.05 118.375 ; + POLYGON 32.39 118.375 32.39 116.77 30.55 116.77 30.55 115.545 28.33 115.545 28.33 118.375 ; + POLYGON 113.35 112.935 113.35 110.105 112.05 110.105 112.05 111.71 112.51 111.71 112.51 112.935 ; + POLYGON 30.55 112.935 30.55 111.71 32.39 111.71 32.39 110.105 28.33 110.105 28.33 112.935 ; + RECT 112.05 104.665 113.35 107.495 ; + POLYGON 32.39 107.495 32.39 105.89 30.55 105.89 30.55 104.665 28.33 104.665 28.33 107.495 ; + POLYGON 141.87 102.055 141.87 99.225 141.03 99.225 141.03 100.45 139.65 100.45 139.65 102.055 ; + POLYGON 3.87 102.055 3.87 100.45 2.03 100.45 2.03 99.225 -0.19 99.225 -0.19 102.055 ; + POLYGON 141.87 96.615 141.87 93.785 140.57 93.785 140.57 95.39 141.03 95.39 141.03 96.615 ; + POLYGON 2.03 96.615 2.03 95.39 3.87 95.39 3.87 93.785 -0.19 93.785 -0.19 96.615 ; + POLYGON 141.87 91.175 141.87 88.345 141.03 88.345 141.03 89.57 140.57 89.57 140.57 91.175 ; + RECT -0.19 88.345 2.03 91.175 ; + RECT 140.57 82.905 141.87 85.735 ; + RECT -0.19 82.905 2.03 85.735 ; + RECT 140.57 77.465 141.87 80.295 ; + RECT -0.19 77.465 2.03 80.295 ; + RECT 140.57 72.025 141.87 74.855 ; + RECT -0.19 72.025 2.03 74.855 ; + RECT 140.57 66.585 141.87 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + RECT 140.57 61.145 141.87 63.975 ; + POLYGON 2.03 63.975 2.03 62.75 3.87 62.75 3.87 61.145 -0.19 61.145 -0.19 63.975 ; + RECT 140.57 55.705 141.87 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 140.57 50.265 141.87 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + RECT 140.57 44.825 141.87 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 141.03 39.385 141.87 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + RECT 140.57 33.945 141.87 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + RECT 141.03 28.505 141.87 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + RECT 112.51 23.065 113.35 25.895 ; + RECT 28.33 23.065 32.39 25.895 ; + POLYGON 113.35 20.455 113.35 17.625 112.51 17.625 112.51 18.85 112.05 18.85 112.05 20.455 ; + RECT 28.33 17.625 32.39 20.455 ; + POLYGON 113.35 15.015 113.35 12.185 112.51 12.185 112.51 13.41 109.29 13.41 109.29 15.015 ; + POLYGON 30.55 15.015 30.55 13.79 32.39 13.79 32.39 12.185 28.33 12.185 28.33 15.015 ; + POLYGON 113.35 9.575 113.35 6.745 112.05 6.745 112.05 7.97 109.29 7.97 109.29 9.575 ; + RECT 28.33 6.745 32.39 9.575 ; + POLYGON 113.35 4.135 113.35 1.305 109.29 1.305 109.29 2.91 112.51 2.91 112.51 4.135 ; + RECT 28.33 1.305 32.39 4.135 ; + POLYGON 113.16 130.56 113.16 103.36 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER pwell ; + RECT 109.61 130.51 109.83 130.68 ; + RECT 105.93 130.51 106.15 130.68 ; + RECT 102.25 130.51 102.47 130.68 ; + RECT 98.57 130.51 98.79 130.68 ; + RECT 94.89 130.51 95.11 130.68 ; + RECT 91.21 130.51 91.43 130.68 ; + RECT 87.53 130.51 87.75 130.68 ; + RECT 83.85 130.51 84.07 130.68 ; + RECT 80.17 130.51 80.39 130.68 ; + RECT 76.49 130.51 76.71 130.68 ; + RECT 72.81 130.51 73.03 130.68 ; + RECT 69.13 130.51 69.35 130.68 ; + RECT 65.45 130.51 65.67 130.68 ; + RECT 61.77 130.51 61.99 130.68 ; + RECT 58.09 130.51 58.31 130.68 ; + RECT 54.41 130.51 54.63 130.68 ; + RECT 50.73 130.51 50.95 130.68 ; + RECT 47.05 130.51 47.27 130.68 ; + RECT 43.37 130.51 43.59 130.68 ; + RECT 39.69 130.51 39.91 130.68 ; + RECT 36.01 130.51 36.23 130.68 ; + RECT 32.33 130.51 32.55 130.68 ; + RECT 28.65 130.51 28.87 130.68 ; + RECT 136.29 103.31 136.51 103.48 ; + RECT 132.61 103.31 132.83 103.48 ; + RECT 128.93 103.31 129.15 103.48 ; + RECT 125.25 103.31 125.47 103.48 ; + RECT 121.57 103.31 121.79 103.48 ; + RECT 117.89 103.31 118.11 103.48 ; + RECT 114.21 103.31 114.43 103.48 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 140.015 103.3 140.125 103.42 ; + RECT 140.455 27.15 140.615 27.26 ; + RECT 141.36 27.145 141.48 27.255 ; + RECT 136.75 27.08 136.97 27.25 ; + RECT 133.07 27.08 133.29 27.25 ; + RECT 129.39 27.08 129.61 27.25 ; + RECT 125.71 27.08 125.93 27.25 ; + RECT 122.03 27.08 122.25 27.25 ; + RECT 118.35 27.08 118.57 27.25 ; + RECT 114.67 27.08 114.89 27.25 ; + RECT 25.89 27.08 26.11 27.25 ; + RECT 22.21 27.08 22.43 27.25 ; + RECT 18.53 27.08 18.75 27.25 ; + RECT 14.85 27.08 15.07 27.25 ; + RECT 11.17 27.08 11.39 27.25 ; + RECT 7.49 27.08 7.71 27.25 ; + RECT 3.81 27.08 4.03 27.25 ; + RECT 0.13 27.08 0.35 27.25 ; + RECT 109.61 -0.12 109.83 0.05 ; + RECT 105.93 -0.12 106.15 0.05 ; + RECT 102.25 -0.12 102.47 0.05 ; + RECT 98.57 -0.12 98.79 0.05 ; + RECT 94.89 -0.12 95.11 0.05 ; + RECT 91.21 -0.12 91.43 0.05 ; + RECT 87.53 -0.12 87.75 0.05 ; + RECT 83.85 -0.12 84.07 0.05 ; + RECT 80.17 -0.12 80.39 0.05 ; + RECT 76.49 -0.12 76.71 0.05 ; + RECT 72.81 -0.12 73.03 0.05 ; + RECT 69.13 -0.12 69.35 0.05 ; + RECT 65.45 -0.12 65.67 0.05 ; + RECT 61.77 -0.12 61.99 0.05 ; + RECT 58.09 -0.12 58.31 0.05 ; + RECT 54.41 -0.12 54.63 0.05 ; + RECT 50.73 -0.12 50.95 0.05 ; + RECT 47.05 -0.12 47.27 0.05 ; + RECT 43.37 -0.12 43.59 0.05 ; + RECT 39.69 -0.12 39.91 0.05 ; + RECT 36.01 -0.12 36.23 0.05 ; + RECT 32.33 -0.12 32.55 0.05 ; + RECT 28.65 -0.12 28.87 0.05 ; + POLYGON 113.16 130.56 113.16 103.36 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER OVERLAP ; + POLYGON 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 113.16 130.56 113.16 103.36 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 ; + END +END sb_1__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef new file mode 100644 index 0000000..59f4962 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -0,0 +1,2786 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 141.68 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END prog_clk[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 86.89 141.68 87.19 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 56.97 141.68 57.27 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 99.13 141.68 99.43 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 96.41 141.68 96.71 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 33.85 141.68 34.15 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 62.41 141.68 62.71 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 31.13 141.68 31.43 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 50.17 141.68 50.47 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 77.37 141.68 77.67 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 35.21 141.68 35.51 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 80.09 141.68 80.39 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 58.33 141.68 58.63 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 74.65 141.68 74.95 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 36.57 141.68 36.87 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 43.37 141.68 43.67 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 55.61 141.68 55.91 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 40.65 141.68 40.95 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 61.05 141.68 61.35 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 39.29 141.68 39.59 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 71.93 141.68 72.23 ; + END + END chanx_right_in[19] + PIN right_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 139.31 102 139.45 103.36 ; + END + END right_top_grid_pin_1_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 0 67.23 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 0 81.49 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.25 0 88.39 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 0 75.97 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.23 0 94.37 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.33 0 87.47 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 0 77.81 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.11 0 84.25 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.49 0 62.63 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.41 0 86.55 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 0 79.65 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 0 68.15 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.17 0 66.31 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.29 0 53.43 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 0 76.89 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.85 0 69.99 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 0 78.73 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 10.05 29.9 10.35 ; + END + END bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 8.01 29.9 8.31 ; + END + END bottom_left_grid_pin_35_[0] + PIN bottom_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 6.65 29.9 6.95 ; + END + END bottom_left_grid_pin_36_[0] + PIN bottom_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 3.25 29.9 3.55 ; + END + END bottom_left_grid_pin_37_[0] + PIN bottom_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 4.61 29.9 4.91 ; + END + END bottom_left_grid_pin_38_[0] + PIN bottom_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 11.41 29.9 11.71 ; + END + END bottom_left_grid_pin_39_[0] + PIN bottom_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 12.77 29.9 13.07 ; + END + END bottom_left_grid_pin_40_[0] + PIN bottom_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 14.13 29.9 14.43 ; + END + END bottom_left_grid_pin_41_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 76.01 1.38 76.31 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 63.77 1.38 64.07 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.49 1.38 32.79 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 74.65 1.38 74.95 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 96.41 1.38 96.71 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 102 2.37 103.36 ; + END + END left_top_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 138.39 102 138.53 103.36 ; + END + END ccff_head[0] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 73.29 141.68 73.59 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 47.45 141.68 47.75 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 52.89 141.68 53.19 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 82.81 141.68 83.11 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 78.73 141.68 79.03 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 95.05 141.68 95.35 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 84.17 141.68 84.47 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 93.69 141.68 93.99 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 85.53 141.68 85.83 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 44.73 141.68 45.03 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 51.53 141.68 51.83 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 69.21 141.68 69.51 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 42.01 141.68 42.31 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 66.49 141.68 66.79 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 90.97 141.68 91.27 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 67.85 141.68 68.15 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 63.77 141.68 64.07 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 88.25 141.68 88.55 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 89.61 141.68 89.91 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 140.3 46.09 141.68 46.39 ; + END + END chanx_right_out[19] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.19 0 83.33 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 0 59.87 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.37 0 52.51 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 0 69.07 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 0 96.67 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.69 0 71.83 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.65 0 60.79 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 0 63.55 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.31 0 93.45 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 0 74.13 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 0 80.57 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.57 0 61.71 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 0 97.59 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 0 64.47 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 0 58.95 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.77 0 70.91 1.36 ; + END + END chany_bottom_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 80.09 1.38 80.39 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 93.69 1.38 93.99 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 85.53 1.38 85.83 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.13 1.38 65.43 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 97.77 1.38 98.07 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 92.33 1.38 92.63 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 82.81 1.38 83.11 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 86.89 1.38 87.19 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 90.97 1.38 91.27 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 88.25 1.38 88.55 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 77.37 1.38 77.67 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 28.52 2.48 29 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 28.52 7.92 29 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 28.52 13.36 29 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 28.52 18.8 29 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 28.52 24.24 29 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 141.2 29.68 141.68 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 141.2 35.12 141.68 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 141.2 40.56 141.68 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 141.2 46 141.68 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 141.2 51.44 141.68 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 141.2 56.88 141.68 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 141.2 62.32 141.68 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 141.2 67.76 141.68 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 141.2 73.2 141.68 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 141.2 78.64 141.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 141.2 84.08 141.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 141.2 89.52 141.68 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 141.2 94.96 141.68 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 141.2 100.4 141.68 100.88 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 134.94 27.2 135.54 27.8 ; + RECT 41.1 102.76 41.7 103.36 ; + RECT 70.54 102.76 71.14 103.36 ; + RECT 99.98 102.76 100.58 103.36 ; + RECT 134.94 102.76 135.54 103.36 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 138.48 43.28 141.68 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 138.48 84.08 141.68 87.28 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 28.52 0 113.16 0.24 ; + RECT 28.52 5.2 29 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 28.52 10.64 29 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 28.52 16.08 29 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 28.52 21.52 29 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 141.68 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 141.2 32.4 141.68 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 141.2 37.84 141.68 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 141.2 43.28 141.68 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 141.2 48.72 141.68 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 141.2 54.16 141.68 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 141.2 59.6 141.68 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 141.2 65.04 141.68 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 141.2 70.48 141.68 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 141.2 75.92 141.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 141.2 81.36 141.68 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 141.2 86.8 141.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 141.2 92.24 141.68 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 141.2 97.68 141.68 98.16 ; + RECT 0 103.12 141.68 103.36 ; + LAYER met5 ; + RECT 28.52 4.52 31.72 7.72 ; + RECT 109.96 4.52 113.16 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 138.48 63.68 141.68 66.88 ; + LAYER met4 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 27.2 6.74 27.8 ; + RECT 6.14 102.76 6.74 103.36 ; + RECT 55.82 102.76 56.42 103.36 ; + RECT 85.26 102.76 85.86 103.36 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 103.275 141.68 103.445 ; + RECT 139.84 100.555 141.68 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 140.76 97.835 141.68 98.005 ; + RECT 0 97.835 1.84 98.005 ; + RECT 140.76 95.115 141.68 95.285 ; + RECT 0 95.115 1.84 95.285 ; + RECT 140.76 92.395 141.68 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 140.76 89.675 141.68 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 140.76 86.955 141.68 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 140.76 84.235 141.68 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 140.76 81.515 141.68 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 138 78.795 141.68 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 138 76.075 141.68 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 139.84 73.355 141.68 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 140.76 70.635 141.68 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 140.76 67.915 141.68 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 141.22 65.195 141.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 140.76 62.475 141.68 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 140.76 59.755 141.68 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 140.76 57.035 141.68 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 140.76 54.315 141.68 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 140.76 51.595 141.68 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 140.76 48.875 141.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 140.76 46.155 141.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 140.76 43.435 141.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 139.84 40.715 141.68 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 139.84 37.995 141.68 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 141.22 35.275 141.68 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 141.22 32.555 141.68 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 141.22 29.835 141.68 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 110.86 27.115 141.68 27.285 ; + RECT 0 27.115 32.2 27.285 ; + RECT 109.48 24.395 113.16 24.565 ; + RECT 28.52 24.395 32.2 24.565 ; + RECT 109.48 21.675 113.16 21.845 ; + RECT 28.52 21.675 32.2 21.845 ; + RECT 112.24 18.955 113.16 19.125 ; + RECT 28.52 18.955 32.2 19.125 ; + RECT 111.32 16.235 113.16 16.405 ; + RECT 28.52 16.235 32.2 16.405 ; + RECT 109.48 13.515 113.16 13.685 ; + RECT 28.52 13.515 32.2 13.685 ; + RECT 109.48 10.795 113.16 10.965 ; + RECT 28.52 10.795 32.2 10.965 ; + RECT 109.48 8.075 113.16 8.245 ; + RECT 28.52 8.075 32.2 8.245 ; + RECT 112.7 5.355 113.16 5.525 ; + RECT 28.52 5.355 32.2 5.525 ; + RECT 109.48 2.635 113.16 2.805 ; + RECT 28.52 2.635 32.2 2.805 ; + RECT 28.52 -0.085 113.16 0.085 ; + LAYER met2 ; + RECT 85.42 103.175 85.7 103.545 ; + RECT 55.98 103.175 56.26 103.545 ; + RECT 6.3 103.175 6.58 103.545 ; + RECT 6.3 27.015 6.58 27.385 ; + RECT 76.23 1.54 76.49 1.86 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + POLYGON 141.4 103.08 141.4 27.48 112.88 27.48 112.88 0.28 97.87 0.28 97.87 1.64 97.17 1.64 97.17 0.28 96.95 0.28 96.95 1.64 96.25 1.64 96.25 0.28 94.65 0.28 94.65 1.64 93.95 1.64 93.95 0.28 93.73 0.28 93.73 1.64 93.03 1.64 93.03 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 86.83 0.28 86.83 1.64 86.13 1.64 86.13 0.28 84.53 0.28 84.53 1.64 83.83 1.64 83.83 0.28 83.61 0.28 83.61 1.64 82.91 1.64 82.91 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 76.25 0.28 76.25 1.64 75.55 1.64 75.55 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 28.8 0.28 28.8 27.48 0.28 27.48 0.28 103.08 1.95 103.08 1.95 101.72 2.65 101.72 2.65 103.08 138.11 103.08 138.11 101.72 138.81 101.72 138.81 103.08 139.03 103.08 139.03 101.72 139.73 101.72 139.73 103.08 ; + LAYER met3 ; + POLYGON 85.725 103.525 85.725 103.52 85.94 103.52 85.94 103.2 85.725 103.2 85.725 103.195 85.395 103.195 85.395 103.2 85.18 103.2 85.18 103.52 85.395 103.52 85.395 103.525 ; + POLYGON 56.285 103.525 56.285 103.52 56.5 103.52 56.5 103.2 56.285 103.2 56.285 103.195 55.955 103.195 55.955 103.2 55.74 103.2 55.74 103.52 55.955 103.52 55.955 103.525 ; + POLYGON 6.605 103.525 6.605 103.52 6.82 103.52 6.82 103.2 6.605 103.2 6.605 103.195 6.275 103.195 6.275 103.2 6.06 103.2 6.06 103.52 6.275 103.52 6.275 103.525 ; + POLYGON 11.65 98.75 11.65 98.45 1.99 98.45 1.99 97.77 1.78 97.77 1.78 98.47 1.69 98.47 1.69 98.75 ; + POLYGON 11.65 93.31 11.65 93.01 1.99 93.01 1.99 92.33 1.78 92.33 1.78 93.03 1.69 93.03 1.69 93.31 ; + POLYGON 15.79 76.99 15.79 76.69 1.78 76.69 1.78 76.71 1.23 76.71 1.23 76.99 ; + POLYGON 11.65 67.47 11.65 67.17 1.78 67.17 1.78 67.19 1.23 67.19 1.23 67.47 ; + POLYGON 2.03 57.96 2.03 57.95 89.39 57.95 89.39 57.65 2.03 57.65 2.03 57.64 1.65 57.64 1.65 57.96 ; + POLYGON 6.605 27.365 6.605 27.36 6.82 27.36 6.82 27.04 6.605 27.04 6.605 27.035 6.275 27.035 6.275 27.04 6.06 27.04 6.06 27.36 6.275 27.36 6.275 27.365 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 141.28 102.96 141.28 99.83 139.9 99.83 139.9 98.73 141.28 98.73 141.28 97.11 139.9 97.11 139.9 96.01 141.28 96.01 141.28 95.75 139.9 95.75 139.9 94.65 141.28 94.65 141.28 94.39 139.9 94.39 139.9 93.29 141.28 93.29 141.28 91.67 139.9 91.67 139.9 90.57 141.28 90.57 141.28 90.31 139.9 90.31 139.9 89.21 141.28 89.21 141.28 88.95 139.9 88.95 139.9 87.85 141.28 87.85 141.28 87.59 139.9 87.59 139.9 86.49 141.28 86.49 141.28 86.23 139.9 86.23 139.9 85.13 141.28 85.13 141.28 84.87 139.9 84.87 139.9 83.77 141.28 83.77 141.28 83.51 139.9 83.51 139.9 82.41 141.28 82.41 141.28 80.79 139.9 80.79 139.9 79.69 141.28 79.69 141.28 79.43 139.9 79.43 139.9 78.33 141.28 78.33 141.28 78.07 139.9 78.07 139.9 76.97 141.28 76.97 141.28 75.35 139.9 75.35 139.9 74.25 141.28 74.25 141.28 73.99 139.9 73.99 139.9 72.89 141.28 72.89 141.28 72.63 139.9 72.63 139.9 71.53 141.28 71.53 141.28 69.91 139.9 69.91 139.9 68.81 141.28 68.81 141.28 68.55 139.9 68.55 139.9 67.45 141.28 67.45 141.28 67.19 139.9 67.19 139.9 66.09 141.28 66.09 141.28 64.47 139.9 64.47 139.9 63.37 141.28 63.37 141.28 63.11 139.9 63.11 139.9 62.01 141.28 62.01 141.28 61.75 139.9 61.75 139.9 60.65 141.28 60.65 141.28 59.03 139.9 59.03 139.9 57.93 141.28 57.93 141.28 57.67 139.9 57.67 139.9 56.57 141.28 56.57 141.28 56.31 139.9 56.31 139.9 55.21 141.28 55.21 141.28 53.59 139.9 53.59 139.9 52.49 141.28 52.49 141.28 52.23 139.9 52.23 139.9 51.13 141.28 51.13 141.28 50.87 139.9 50.87 139.9 49.77 141.28 49.77 141.28 48.15 139.9 48.15 139.9 47.05 141.28 47.05 141.28 46.79 139.9 46.79 139.9 45.69 141.28 45.69 141.28 45.43 139.9 45.43 139.9 44.33 141.28 44.33 141.28 44.07 139.9 44.07 139.9 42.97 141.28 42.97 141.28 42.71 139.9 42.71 139.9 41.61 141.28 41.61 141.28 41.35 139.9 41.35 139.9 40.25 141.28 40.25 141.28 39.99 139.9 39.99 139.9 38.89 141.28 38.89 141.28 37.27 139.9 37.27 139.9 36.17 141.28 36.17 141.28 35.91 139.9 35.91 139.9 34.81 141.28 34.81 141.28 34.55 139.9 34.55 139.9 33.45 141.28 33.45 141.28 31.83 139.9 31.83 139.9 30.73 141.28 30.73 141.28 27.6 112.76 27.6 112.76 0.4 28.92 0.4 28.92 2.85 30.3 2.85 30.3 3.95 28.92 3.95 28.92 4.21 30.3 4.21 30.3 5.31 28.92 5.31 28.92 6.25 30.3 6.25 30.3 7.35 28.92 7.35 28.92 7.61 30.3 7.61 30.3 8.71 28.92 8.71 28.92 9.65 30.3 9.65 30.3 10.75 28.92 10.75 28.92 11.01 30.3 11.01 30.3 12.11 28.92 12.11 28.92 12.37 30.3 12.37 30.3 13.47 28.92 13.47 28.92 13.73 30.3 13.73 30.3 14.83 28.92 14.83 28.92 27.6 0.4 27.6 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 93.29 1.78 93.29 1.78 94.39 0.4 94.39 0.4 96.01 1.78 96.01 1.78 97.11 0.4 97.11 0.4 97.37 1.78 97.37 1.78 98.47 0.4 98.47 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 102.96 ; + LAYER met5 ; + POLYGON 138.48 100.16 138.48 90.48 135.28 90.48 135.28 80.88 138.48 80.88 138.48 70.08 135.28 70.08 135.28 60.48 138.48 60.48 138.48 49.68 135.28 49.68 135.28 40.08 138.48 40.08 138.48 30.4 109.96 30.4 109.96 10.92 106.76 10.92 106.76 3.2 34.92 3.2 34.92 10.92 31.72 10.92 31.72 30.4 3.2 30.4 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 100.16 ; + LAYER met4 ; + POLYGON 141.28 102.96 141.28 27.6 135.94 27.6 135.94 28.2 134.54 28.2 134.54 27.6 112.76 27.6 112.76 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 28.92 0.4 28.92 27.6 7.14 27.6 7.14 28.2 5.74 28.2 5.74 27.6 0.4 27.6 0.4 102.96 5.74 102.96 5.74 102.36 7.14 102.36 7.14 102.96 40.7 102.96 40.7 102.36 42.1 102.36 42.1 102.96 55.42 102.96 55.42 102.36 56.82 102.36 56.82 102.96 70.14 102.96 70.14 102.36 71.54 102.36 71.54 102.96 84.86 102.96 84.86 102.36 86.26 102.36 86.26 102.96 99.58 102.96 99.58 102.36 100.98 102.36 100.98 102.96 134.54 102.96 134.54 102.36 135.94 102.36 135.94 102.96 ; + LAYER met1 ; + POLYGON 93.525 26.795 93.525 26.565 93.235 26.565 93.235 26.61 92.07 26.61 92.07 26.45 91.93 26.45 91.93 26.75 93.235 26.75 93.235 26.795 ; + POLYGON 141.4 102.84 141.4 101.16 140.92 101.16 140.92 100.12 141.4 100.12 141.4 98.44 140.92 98.44 140.92 97.4 141.4 97.4 141.4 95.72 140.92 95.72 140.92 94.68 141.4 94.68 141.4 93 140.92 93 140.92 91.96 141.4 91.96 141.4 90.28 140.92 90.28 140.92 89.24 141.4 89.24 141.4 87.56 140.92 87.56 140.92 86.52 141.4 86.52 141.4 84.84 140.92 84.84 140.92 83.8 141.4 83.8 141.4 82.12 140.92 82.12 140.92 81.08 141.4 81.08 141.4 79.4 140.92 79.4 140.92 78.36 141.4 78.36 141.4 76.68 140.92 76.68 140.92 75.64 141.4 75.64 141.4 73.96 140.92 73.96 140.92 72.92 141.4 72.92 141.4 71.24 140.92 71.24 140.92 70.2 141.4 70.2 141.4 68.52 140.92 68.52 140.92 67.48 141.4 67.48 141.4 65.8 140.92 65.8 140.92 64.76 141.4 64.76 141.4 63.08 140.92 63.08 140.92 62.04 141.4 62.04 141.4 60.36 140.92 60.36 140.92 59.32 141.4 59.32 141.4 57.64 140.92 57.64 140.92 56.6 141.4 56.6 141.4 54.92 140.92 54.92 140.92 53.88 141.4 53.88 141.4 52.2 140.92 52.2 140.92 51.16 141.4 51.16 141.4 49.48 140.92 49.48 140.92 48.44 141.4 48.44 141.4 46.76 140.92 46.76 140.92 45.72 141.4 45.72 141.4 44.04 140.92 44.04 140.92 43 141.4 43 141.4 41.32 140.92 41.32 140.92 40.28 141.4 40.28 141.4 38.6 140.92 38.6 140.92 37.56 141.4 37.56 141.4 35.88 140.92 35.88 140.92 34.84 141.4 34.84 141.4 33.16 140.92 33.16 140.92 32.12 141.4 32.12 141.4 30.44 140.92 30.44 140.92 29.4 141.4 29.4 141.4 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 28.8 0.52 28.8 2.2 29.28 2.2 29.28 3.24 28.8 3.24 28.8 4.92 29.28 4.92 29.28 5.96 28.8 5.96 28.8 7.64 29.28 7.64 29.28 8.68 28.8 8.68 28.8 10.36 29.28 10.36 29.28 11.4 28.8 11.4 28.8 13.08 29.28 13.08 29.28 14.12 28.8 14.12 28.8 15.8 29.28 15.8 29.28 16.84 28.8 16.84 28.8 18.52 29.28 18.52 29.28 19.56 28.8 19.56 28.8 21.24 29.28 21.24 29.28 22.28 28.8 22.28 28.8 23.96 29.28 23.96 29.28 25 28.8 25 28.8 26.68 ; + LAYER li1 ; + POLYGON 141.34 103.02 141.34 27.54 112.82 27.54 112.82 0.34 28.86 0.34 28.86 27.54 0.34 27.54 0.34 103.02 ; + LAYER mcon ; + RECT 141.365 103.275 141.535 103.445 ; + RECT 140.905 103.275 141.075 103.445 ; + RECT 140.445 103.275 140.615 103.445 ; + RECT 139.985 103.275 140.155 103.445 ; + RECT 139.525 103.275 139.695 103.445 ; + RECT 139.065 103.275 139.235 103.445 ; + RECT 138.605 103.275 138.775 103.445 ; + RECT 138.145 103.275 138.315 103.445 ; + RECT 137.685 103.275 137.855 103.445 ; + RECT 137.225 103.275 137.395 103.445 ; + RECT 136.765 103.275 136.935 103.445 ; + RECT 136.305 103.275 136.475 103.445 ; + RECT 135.845 103.275 136.015 103.445 ; + RECT 135.385 103.275 135.555 103.445 ; + RECT 134.925 103.275 135.095 103.445 ; + RECT 134.465 103.275 134.635 103.445 ; + RECT 134.005 103.275 134.175 103.445 ; + RECT 133.545 103.275 133.715 103.445 ; + RECT 133.085 103.275 133.255 103.445 ; + RECT 132.625 103.275 132.795 103.445 ; + RECT 132.165 103.275 132.335 103.445 ; + RECT 131.705 103.275 131.875 103.445 ; + RECT 131.245 103.275 131.415 103.445 ; + RECT 130.785 103.275 130.955 103.445 ; + RECT 130.325 103.275 130.495 103.445 ; + RECT 129.865 103.275 130.035 103.445 ; + RECT 129.405 103.275 129.575 103.445 ; + RECT 128.945 103.275 129.115 103.445 ; + RECT 128.485 103.275 128.655 103.445 ; + RECT 128.025 103.275 128.195 103.445 ; + RECT 127.565 103.275 127.735 103.445 ; + RECT 127.105 103.275 127.275 103.445 ; + RECT 126.645 103.275 126.815 103.445 ; + RECT 126.185 103.275 126.355 103.445 ; + RECT 125.725 103.275 125.895 103.445 ; + RECT 125.265 103.275 125.435 103.445 ; + RECT 124.805 103.275 124.975 103.445 ; + RECT 124.345 103.275 124.515 103.445 ; + RECT 123.885 103.275 124.055 103.445 ; + RECT 123.425 103.275 123.595 103.445 ; + RECT 122.965 103.275 123.135 103.445 ; + RECT 122.505 103.275 122.675 103.445 ; + RECT 122.045 103.275 122.215 103.445 ; + RECT 121.585 103.275 121.755 103.445 ; + RECT 121.125 103.275 121.295 103.445 ; + RECT 120.665 103.275 120.835 103.445 ; + RECT 120.205 103.275 120.375 103.445 ; + RECT 119.745 103.275 119.915 103.445 ; + RECT 119.285 103.275 119.455 103.445 ; + RECT 118.825 103.275 118.995 103.445 ; + RECT 118.365 103.275 118.535 103.445 ; + RECT 117.905 103.275 118.075 103.445 ; + RECT 117.445 103.275 117.615 103.445 ; + RECT 116.985 103.275 117.155 103.445 ; + RECT 116.525 103.275 116.695 103.445 ; + RECT 116.065 103.275 116.235 103.445 ; + RECT 115.605 103.275 115.775 103.445 ; + RECT 115.145 103.275 115.315 103.445 ; + RECT 114.685 103.275 114.855 103.445 ; + RECT 114.225 103.275 114.395 103.445 ; + RECT 113.765 103.275 113.935 103.445 ; + RECT 113.305 103.275 113.475 103.445 ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 141.365 100.555 141.535 100.725 ; + RECT 140.905 100.555 141.075 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 141.365 97.835 141.535 98.005 ; + RECT 140.905 97.835 141.075 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 141.365 95.115 141.535 95.285 ; + RECT 140.905 95.115 141.075 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 141.365 92.395 141.535 92.565 ; + RECT 140.905 92.395 141.075 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 141.365 89.675 141.535 89.845 ; + RECT 140.905 89.675 141.075 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 141.365 86.955 141.535 87.125 ; + RECT 140.905 86.955 141.075 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 141.365 84.235 141.535 84.405 ; + RECT 140.905 84.235 141.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 141.365 81.515 141.535 81.685 ; + RECT 140.905 81.515 141.075 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 141.365 78.795 141.535 78.965 ; + RECT 140.905 78.795 141.075 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 141.365 76.075 141.535 76.245 ; + RECT 140.905 76.075 141.075 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 141.365 73.355 141.535 73.525 ; + RECT 140.905 73.355 141.075 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 141.365 70.635 141.535 70.805 ; + RECT 140.905 70.635 141.075 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 141.365 67.915 141.535 68.085 ; + RECT 140.905 67.915 141.075 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 141.365 65.195 141.535 65.365 ; + RECT 140.905 65.195 141.075 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 141.365 62.475 141.535 62.645 ; + RECT 140.905 62.475 141.075 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 141.365 59.755 141.535 59.925 ; + RECT 140.905 59.755 141.075 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 141.365 57.035 141.535 57.205 ; + RECT 140.905 57.035 141.075 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 141.365 54.315 141.535 54.485 ; + RECT 140.905 54.315 141.075 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 141.365 51.595 141.535 51.765 ; + RECT 140.905 51.595 141.075 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 141.365 48.875 141.535 49.045 ; + RECT 140.905 48.875 141.075 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 141.365 46.155 141.535 46.325 ; + RECT 140.905 46.155 141.075 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 141.365 43.435 141.535 43.605 ; + RECT 140.905 43.435 141.075 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 141.365 40.715 141.535 40.885 ; + RECT 140.905 40.715 141.075 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 141.365 37.995 141.535 38.165 ; + RECT 140.905 37.995 141.075 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 141.365 35.275 141.535 35.445 ; + RECT 140.905 35.275 141.075 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 141.365 32.555 141.535 32.725 ; + RECT 140.905 32.555 141.075 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 141.365 29.835 141.535 30.005 ; + RECT 140.905 29.835 141.075 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 141.365 27.115 141.535 27.285 ; + RECT 140.905 27.115 141.075 27.285 ; + RECT 140.445 27.115 140.615 27.285 ; + RECT 139.985 27.115 140.155 27.285 ; + RECT 139.525 27.115 139.695 27.285 ; + RECT 139.065 27.115 139.235 27.285 ; + RECT 138.605 27.115 138.775 27.285 ; + RECT 138.145 27.115 138.315 27.285 ; + RECT 137.685 27.115 137.855 27.285 ; + RECT 137.225 27.115 137.395 27.285 ; + RECT 136.765 27.115 136.935 27.285 ; + RECT 136.305 27.115 136.475 27.285 ; + RECT 135.845 27.115 136.015 27.285 ; + RECT 135.385 27.115 135.555 27.285 ; + RECT 134.925 27.115 135.095 27.285 ; + RECT 134.465 27.115 134.635 27.285 ; + RECT 134.005 27.115 134.175 27.285 ; + RECT 133.545 27.115 133.715 27.285 ; + RECT 133.085 27.115 133.255 27.285 ; + RECT 132.625 27.115 132.795 27.285 ; + RECT 132.165 27.115 132.335 27.285 ; + RECT 131.705 27.115 131.875 27.285 ; + RECT 131.245 27.115 131.415 27.285 ; + RECT 130.785 27.115 130.955 27.285 ; + RECT 130.325 27.115 130.495 27.285 ; + RECT 129.865 27.115 130.035 27.285 ; + RECT 129.405 27.115 129.575 27.285 ; + RECT 128.945 27.115 129.115 27.285 ; + RECT 128.485 27.115 128.655 27.285 ; + RECT 128.025 27.115 128.195 27.285 ; + RECT 127.565 27.115 127.735 27.285 ; + RECT 127.105 27.115 127.275 27.285 ; + RECT 126.645 27.115 126.815 27.285 ; + RECT 126.185 27.115 126.355 27.285 ; + RECT 125.725 27.115 125.895 27.285 ; + RECT 125.265 27.115 125.435 27.285 ; + RECT 124.805 27.115 124.975 27.285 ; + RECT 124.345 27.115 124.515 27.285 ; + RECT 123.885 27.115 124.055 27.285 ; + RECT 123.425 27.115 123.595 27.285 ; + RECT 122.965 27.115 123.135 27.285 ; + RECT 122.505 27.115 122.675 27.285 ; + RECT 122.045 27.115 122.215 27.285 ; + RECT 121.585 27.115 121.755 27.285 ; + RECT 121.125 27.115 121.295 27.285 ; + RECT 120.665 27.115 120.835 27.285 ; + RECT 120.205 27.115 120.375 27.285 ; + RECT 119.745 27.115 119.915 27.285 ; + RECT 119.285 27.115 119.455 27.285 ; + RECT 118.825 27.115 118.995 27.285 ; + RECT 118.365 27.115 118.535 27.285 ; + RECT 117.905 27.115 118.075 27.285 ; + RECT 117.445 27.115 117.615 27.285 ; + RECT 116.985 27.115 117.155 27.285 ; + RECT 116.525 27.115 116.695 27.285 ; + RECT 116.065 27.115 116.235 27.285 ; + RECT 115.605 27.115 115.775 27.285 ; + RECT 115.145 27.115 115.315 27.285 ; + RECT 114.685 27.115 114.855 27.285 ; + RECT 114.225 27.115 114.395 27.285 ; + RECT 113.765 27.115 113.935 27.285 ; + RECT 113.305 27.115 113.475 27.285 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 93.295 26.595 93.465 26.765 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 29.125 24.395 29.295 24.565 ; + RECT 28.665 24.395 28.835 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 29.125 21.675 29.295 21.845 ; + RECT 28.665 21.675 28.835 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 29.125 18.955 29.295 19.125 ; + RECT 28.665 18.955 28.835 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 29.125 16.235 29.295 16.405 ; + RECT 28.665 16.235 28.835 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 29.125 13.515 29.295 13.685 ; + RECT 28.665 13.515 28.835 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 29.125 8.075 29.295 8.245 ; + RECT 28.665 8.075 28.835 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 29.125 5.355 29.295 5.525 ; + RECT 28.665 5.355 28.835 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 29.125 2.635 29.295 2.805 ; + RECT 28.665 2.635 28.835 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + LAYER via ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 6.365 103.285 6.515 103.435 ; + RECT 139.305 101.585 139.455 101.735 ; + RECT 85.485 27.125 85.635 27.275 ; + RECT 56.045 27.125 56.195 27.275 ; + RECT 6.365 27.125 6.515 27.275 ; + RECT 83.185 1.625 83.335 1.775 ; + RECT 71.685 1.625 71.835 1.775 ; + RECT 59.725 1.625 59.875 1.775 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + LAYER via2 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.28 93.74 1.48 93.94 ; + RECT 140.2 91.02 140.4 91.22 ; + RECT 1.28 85.58 1.48 85.78 ; + RECT 1.28 77.42 1.48 77.62 ; + RECT 1.28 70.62 1.48 70.82 ; + RECT 140.2 66.54 140.4 66.74 ; + RECT 140.2 62.46 140.4 62.66 ; + RECT 140.2 58.38 140.4 58.58 ; + RECT 1.28 54.3 1.48 54.5 ; + RECT 1.28 48.86 1.48 49.06 ; + RECT 1.74 43.42 1.94 43.62 ; + RECT 1.28 33.9 1.48 34.1 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via3 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.74 52.94 1.94 53.14 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 30.26 10.1 30.46 10.3 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via4 ; + RECT 134.84 86.08 135.64 86.88 ; + RECT 134.84 84.48 135.64 85.28 ; + RECT 6.04 65.68 6.84 66.48 ; + RECT 6.04 64.08 6.84 64.88 ; + RECT 134.84 45.28 135.64 46.08 ; + RECT 134.84 43.68 135.64 44.48 ; + LAYER fieldpoly ; + POLYGON 141.54 103.22 141.54 27.34 113.02 27.34 113.02 0.14 28.66 0.14 28.66 27.34 0.14 27.34 0.14 103.22 ; + LAYER diff ; + POLYGON 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER nwell ; + POLYGON 141.87 102.055 141.87 99.225 140.57 99.225 140.57 100.45 139.65 100.45 139.65 102.055 ; + POLYGON 3.87 102.055 3.87 100.45 2.03 100.45 2.03 99.225 -0.19 99.225 -0.19 102.055 ; + RECT 140.57 93.785 141.87 96.615 ; + RECT -0.19 93.785 2.03 96.615 ; + RECT 140.57 88.345 141.87 91.175 ; + RECT -0.19 88.345 2.03 91.175 ; + RECT 140.57 82.905 141.87 85.735 ; + RECT -0.19 82.905 2.03 85.735 ; + POLYGON 141.87 80.295 141.87 77.465 137.81 77.465 137.81 79.07 140.57 79.07 140.57 80.295 ; + POLYGON 2.03 80.295 2.03 79.07 3.87 79.07 3.87 77.465 -0.19 77.465 -0.19 80.295 ; + POLYGON 141.87 74.855 141.87 72.025 140.57 72.025 140.57 73.25 139.65 73.25 139.65 74.855 ; + RECT -0.19 72.025 2.03 74.855 ; + POLYGON 141.87 69.415 141.87 66.585 141.03 66.585 141.03 67.81 140.57 67.81 140.57 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + POLYGON 141.87 63.975 141.87 61.145 140.57 61.145 140.57 62.75 141.03 62.75 141.03 63.975 ; + POLYGON 2.03 63.975 2.03 62.75 3.87 62.75 3.87 61.145 -0.19 61.145 -0.19 63.975 ; + POLYGON 141.87 58.535 141.87 55.705 140.57 55.705 140.57 57.31 141.03 57.31 141.03 58.535 ; + POLYGON 3.87 58.535 3.87 56.93 2.03 56.93 2.03 55.705 -0.19 55.705 -0.19 58.535 ; + RECT 140.57 50.265 141.87 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + RECT 140.57 44.825 141.87 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + POLYGON 141.87 42.215 141.87 39.385 139.65 39.385 139.65 40.99 141.03 40.99 141.03 42.215 ; + POLYGON 2.03 42.215 2.03 40.99 3.87 40.99 3.87 39.385 -0.19 39.385 -0.19 42.215 ; + RECT 141.03 33.945 141.87 36.775 ; + RECT -0.19 33.945 3.87 36.775 ; + RECT 141.03 28.505 141.87 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + POLYGON 113.35 25.895 113.35 23.065 109.29 23.065 109.29 24.67 112.05 24.67 112.05 25.895 ; + RECT 28.33 23.065 32.39 25.895 ; + RECT 112.05 17.625 113.35 20.455 ; + RECT 28.33 17.625 32.39 20.455 ; + POLYGON 113.35 15.015 113.35 12.185 109.29 12.185 109.29 13.79 111.13 13.79 111.13 15.015 ; + POLYGON 30.55 15.015 30.55 13.79 32.39 13.79 32.39 12.185 28.33 12.185 28.33 15.015 ; + POLYGON 113.35 9.575 113.35 6.745 112.51 6.745 112.51 7.97 109.29 7.97 109.29 9.575 ; + RECT 28.33 6.745 32.39 9.575 ; + POLYGON 113.35 4.135 113.35 1.305 109.29 1.305 109.29 2.91 112.51 2.91 112.51 4.135 ; + RECT 28.33 1.305 32.39 4.135 ; + POLYGON 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER pwell ; + RECT 136.29 103.31 136.51 103.48 ; + RECT 132.61 103.31 132.83 103.48 ; + RECT 128.93 103.31 129.15 103.48 ; + RECT 125.25 103.31 125.47 103.48 ; + RECT 121.57 103.31 121.79 103.48 ; + RECT 117.89 103.31 118.11 103.48 ; + RECT 114.21 103.31 114.43 103.48 ; + RECT 110.53 103.31 110.75 103.48 ; + RECT 106.85 103.31 107.07 103.48 ; + RECT 103.17 103.31 103.39 103.48 ; + RECT 99.49 103.31 99.71 103.48 ; + RECT 95.81 103.31 96.03 103.48 ; + RECT 92.13 103.31 92.35 103.48 ; + RECT 88.45 103.31 88.67 103.48 ; + RECT 84.77 103.31 84.99 103.48 ; + RECT 81.09 103.31 81.31 103.48 ; + RECT 77.41 103.31 77.63 103.48 ; + RECT 73.73 103.31 73.95 103.48 ; + RECT 70.05 103.31 70.27 103.48 ; + RECT 66.37 103.31 66.59 103.48 ; + RECT 62.69 103.31 62.91 103.48 ; + RECT 59.01 103.31 59.23 103.48 ; + RECT 55.33 103.31 55.55 103.48 ; + RECT 51.65 103.31 51.87 103.48 ; + RECT 47.97 103.31 48.19 103.48 ; + RECT 44.29 103.31 44.51 103.48 ; + RECT 40.61 103.31 40.83 103.48 ; + RECT 36.93 103.31 37.15 103.48 ; + RECT 33.25 103.31 33.47 103.48 ; + RECT 29.57 103.31 29.79 103.48 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 140.015 103.3 140.125 103.42 ; + RECT 140.455 27.15 140.615 27.26 ; + RECT 141.36 27.145 141.48 27.255 ; + RECT 136.75 27.08 136.97 27.25 ; + RECT 133.07 27.08 133.29 27.25 ; + RECT 129.39 27.08 129.61 27.25 ; + RECT 125.71 27.08 125.93 27.25 ; + RECT 122.03 27.08 122.25 27.25 ; + RECT 118.35 27.08 118.57 27.25 ; + RECT 114.67 27.08 114.89 27.25 ; + RECT 25.89 27.08 26.11 27.25 ; + RECT 22.21 27.08 22.43 27.25 ; + RECT 18.53 27.08 18.75 27.25 ; + RECT 14.85 27.08 15.07 27.25 ; + RECT 11.17 27.08 11.39 27.25 ; + RECT 7.49 27.08 7.71 27.25 ; + RECT 3.81 27.08 4.03 27.25 ; + RECT 0.13 27.08 0.35 27.25 ; + RECT 109.61 -0.12 109.83 0.05 ; + RECT 105.93 -0.12 106.15 0.05 ; + RECT 102.25 -0.12 102.47 0.05 ; + RECT 98.57 -0.12 98.79 0.05 ; + RECT 94.89 -0.12 95.11 0.05 ; + RECT 91.21 -0.12 91.43 0.05 ; + RECT 87.53 -0.12 87.75 0.05 ; + RECT 83.85 -0.12 84.07 0.05 ; + RECT 80.17 -0.12 80.39 0.05 ; + RECT 76.49 -0.12 76.71 0.05 ; + RECT 72.81 -0.12 73.03 0.05 ; + RECT 69.13 -0.12 69.35 0.05 ; + RECT 65.45 -0.12 65.67 0.05 ; + RECT 61.77 -0.12 61.99 0.05 ; + RECT 58.09 -0.12 58.31 0.05 ; + RECT 54.41 -0.12 54.63 0.05 ; + RECT 50.73 -0.12 50.95 0.05 ; + RECT 47.05 -0.12 47.27 0.05 ; + RECT 43.37 -0.12 43.59 0.05 ; + RECT 39.69 -0.12 39.91 0.05 ; + RECT 36.01 -0.12 36.23 0.05 ; + RECT 32.33 -0.12 32.55 0.05 ; + RECT 28.65 -0.12 28.87 0.05 ; + POLYGON 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER OVERLAP ; + POLYGON 28.52 0 28.52 27.2 0 27.2 0 103.36 141.68 103.36 141.68 27.2 113.16 27.2 113.16 0 ; + END +END sb_1__2_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef new file mode 100644 index 0000000..45f28af --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -0,0 +1,2368 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 28.52 99.81 29.9 100.11 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 102 80.57 103.36 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 102 57.57 103.36 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 102 82.41 103.36 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 102 74.13 103.36 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 102 52.05 103.36 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.19 102 60.33 103.36 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 102 75.05 103.36 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 102 66.77 103.36 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 102 72.29 103.36 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 102 67.69 103.36 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 102 73.21 103.36 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 102 75.97 103.36 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 102 52.97 103.36 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 102 63.55 103.36 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.67 102 54.81 103.36 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 102 53.89 103.36 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 102 69.53 103.36 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 102 81.49 103.36 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.57 102 84.71 103.36 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.27 102 59.41 103.36 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 102 32.73 103.36 ; + END + END top_left_grid_pin_34_[0] + PIN top_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 102 30.89 103.36 ; + END + END top_left_grid_pin_35_[0] + PIN top_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 93.69 29.9 93.99 ; + END + END top_left_grid_pin_36_[0] + PIN top_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 102 31.81 103.36 ; + END + END top_left_grid_pin_37_[0] + PIN top_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 97.77 29.9 98.07 ; + END + END top_left_grid_pin_38_[0] + PIN top_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 96.41 29.9 96.71 ; + END + END top_left_grid_pin_39_[0] + PIN top_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 95.05 29.9 95.35 ; + END + END top_left_grid_pin_40_[0] + PIN top_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 90.29 29.9 90.59 ; + END + END top_left_grid_pin_41_[0] + PIN top_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 102 110.93 103.36 ; + END + END top_right_grid_pin_1_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.97 1.38 57.27 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 62.41 1.38 62.71 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.49 1.38 32.79 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.17 1.38 67.47 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.41 1.38 28.71 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 5.29 1.38 5.59 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 3.93 1.38 4.23 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 74.8 7.43 76.16 ; + END + END left_top_grid_pin_42_[0] + PIN left_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 91.65 29.9 91.95 ; + END + END left_top_grid_pin_43_[0] + PIN left_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.07 74.8 4.21 76.16 ; + END + END left_top_grid_pin_44_[0] + PIN left_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.99 74.8 5.13 76.16 ; + END + END left_top_grid_pin_45_[0] + PIN left_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 74.8 2.37 76.16 ; + END + END left_top_grid_pin_46_[0] + PIN left_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 74.8 3.29 76.16 ; + END + END left_top_grid_pin_47_[0] + PIN left_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.43 74.8 11.57 76.16 ; + END + END left_top_grid_pin_48_[0] + PIN left_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.51 74.8 10.65 76.16 ; + END + END left_top_grid_pin_49_[0] + PIN left_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 0 2.37 1.36 ; + END + END left_bottom_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.03 102 108.17 103.36 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 102 76.89 103.36 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.11 102 61.25 103.36 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 102 77.81 103.36 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 102 71.37 103.36 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 102 98.97 103.36 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.65 102 83.79 103.36 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 102 70.45 103.36 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 102 50.21 103.36 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 102 68.61 103.36 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.35 102 58.49 103.36 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 102 96.67 103.36 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.77 102 93.91 103.36 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 102 79.65 103.36 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 102 64.47 103.36 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 102 97.59 103.36 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 102 51.13 103.36 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.87 102 87.01 103.36 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 102 62.17 103.36 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.61 102 95.75 103.36 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 102 78.73 103.36 ; + END + END chany_top_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.05 1.38 27.35 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 64.45 1.38 64.75 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 15.49 1.38 15.79 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 11.41 1.38 11.71 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.69 1.38 25.99 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.61 1.38 21.91 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.97 1.38 23.27 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.81 1.38 66.11 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 10.05 1.38 10.35 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 28.52 78.64 29 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 28.52 84.08 29 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 28.52 89.52 29 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 28.52 94.96 29 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 28.52 100.4 29 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 109.96 16.08 113.16 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 109.96 56.88 113.16 60.08 ; + RECT 28.52 95.64 31.72 98.84 ; + RECT 109.96 95.64 113.16 98.84 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 41.1 102.76 41.7 103.36 ; + RECT 70.54 102.76 71.14 103.36 ; + RECT 99.98 102.76 100.58 103.36 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 0 0 113.16 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 112.68 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 113.16 76.4 ; + RECT 28.52 81.36 29 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 28.52 86.8 29 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 28.52 92.24 29 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 28.52 97.68 29 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 28.52 103.12 113.16 103.36 ; + LAYER met4 ; + RECT 6.14 0 6.74 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 75.56 6.74 76.16 ; + RECT 55.82 102.76 56.42 103.36 ; + RECT 85.26 102.76 85.86 103.36 ; + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 109.96 36.48 113.16 39.68 ; + END + END VSS + OBS + LAYER li1 ; + RECT 28.52 103.275 113.16 103.445 ; + RECT 109.48 100.555 113.16 100.725 ; + RECT 28.52 100.555 32.2 100.725 ; + RECT 112.7 97.835 113.16 98.005 ; + RECT 28.52 97.835 32.2 98.005 ; + RECT 109.48 95.115 113.16 95.285 ; + RECT 28.52 95.115 32.2 95.285 ; + RECT 109.48 92.395 113.16 92.565 ; + RECT 28.52 92.395 32.2 92.565 ; + RECT 112.24 89.675 113.16 89.845 ; + RECT 28.52 89.675 32.2 89.845 ; + RECT 112.24 86.955 113.16 87.125 ; + RECT 28.52 86.955 32.2 87.125 ; + RECT 112.24 84.235 113.16 84.405 ; + RECT 28.52 84.235 32.2 84.405 ; + RECT 111.32 81.515 113.16 81.685 ; + RECT 28.52 81.515 32.2 81.685 ; + RECT 111.32 78.795 113.16 78.965 ; + RECT 28.52 78.795 32.2 78.965 ; + RECT 112.7 76.075 113.16 76.245 ; + RECT 0 76.075 30.36 76.245 ; + RECT 112.7 73.355 113.16 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 112.7 70.635 113.16 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 112.7 67.915 113.16 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 112.7 65.195 113.16 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 111.32 62.475 113.16 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 111.32 59.755 113.16 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 112.7 57.035 113.16 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 112.7 54.315 113.16 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 112.24 51.595 113.16 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 112.24 48.875 113.16 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 112.24 46.155 113.16 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 112.7 43.435 113.16 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 112.7 40.715 113.16 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 111.32 37.995 113.16 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 111.32 35.275 113.16 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 112.24 32.555 113.16 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 109.48 29.835 113.16 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 109.48 27.115 113.16 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 111.32 24.395 113.16 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 111.32 21.675 113.16 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 111.32 18.955 113.16 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 112.24 16.235 113.16 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 112.24 13.515 113.16 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 112.24 10.795 113.16 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 112.24 8.075 113.16 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 112.24 5.355 113.16 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 112.24 2.635 113.16 2.805 ; + RECT 0 2.635 3.68 2.805 ; + RECT 0 -0.085 113.16 0.085 ; + LAYER met3 ; + POLYGON 85.725 103.525 85.725 103.52 85.94 103.52 85.94 103.2 85.725 103.2 85.725 103.195 85.395 103.195 85.395 103.2 85.18 103.2 85.18 103.52 85.395 103.52 85.395 103.525 ; + POLYGON 56.285 103.525 56.285 103.52 56.5 103.52 56.5 103.2 56.285 103.2 56.285 103.195 55.955 103.195 55.955 103.2 55.74 103.2 55.74 103.52 55.955 103.52 55.955 103.525 ; + POLYGON 6.605 76.325 6.605 76.32 6.82 76.32 6.82 76 6.605 76 6.605 75.995 6.275 75.995 6.275 76 6.06 76 6.06 76.32 6.275 76.32 6.275 76.325 ; + POLYGON 19.47 55.23 19.47 54.93 1.78 54.93 1.78 54.95 1.23 54.95 1.23 55.23 ; + POLYGON 2.91 48.43 2.91 48.13 1.78 48.13 1.78 48.15 1.23 48.15 1.23 48.43 ; + POLYGON 11.19 44.35 11.19 44.05 1.99 44.05 1.99 43.37 1.78 43.37 1.78 44.07 1.69 44.07 1.69 44.35 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 6.605 0.165 6.605 0.16 6.82 0.16 6.82 -0.16 6.605 -0.16 6.605 -0.165 6.275 -0.165 6.275 -0.16 6.06 -0.16 6.06 0.16 6.275 0.16 6.275 0.165 ; + POLYGON 112.76 102.96 112.76 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 75.76 28.92 75.76 28.92 89.89 30.3 89.89 30.3 90.99 28.92 90.99 28.92 91.25 30.3 91.25 30.3 92.35 28.92 92.35 28.92 93.29 30.3 93.29 30.3 94.39 28.92 94.39 28.92 94.65 30.3 94.65 30.3 95.75 28.92 95.75 28.92 96.01 30.3 96.01 30.3 97.11 28.92 97.11 28.92 97.37 30.3 97.37 30.3 98.47 28.92 98.47 28.92 99.41 30.3 99.41 30.3 100.51 28.92 100.51 28.92 102.96 ; + LAYER met2 ; + RECT 85.42 103.175 85.7 103.545 ; + RECT 55.98 103.175 56.26 103.545 ; + RECT 78.07 101.5 78.33 101.82 ; + RECT 6.3 75.975 6.58 76.345 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 6.3 -0.185 6.58 0.185 ; + POLYGON 112.88 103.08 112.88 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 75.88 1.95 75.88 1.95 74.52 2.65 74.52 2.65 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 3.79 75.88 3.79 74.52 4.49 74.52 4.49 75.88 4.71 75.88 4.71 74.52 5.41 74.52 5.41 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 10.23 75.88 10.23 74.52 10.93 74.52 10.93 75.88 11.15 75.88 11.15 74.52 11.85 74.52 11.85 75.88 28.8 75.88 28.8 103.08 30.47 103.08 30.47 101.72 31.17 101.72 31.17 103.08 31.39 103.08 31.39 101.72 32.09 101.72 32.09 103.08 32.31 103.08 32.31 101.72 33.01 101.72 33.01 103.08 49.79 103.08 49.79 101.72 50.49 101.72 50.49 103.08 50.71 103.08 50.71 101.72 51.41 101.72 51.41 103.08 51.63 103.08 51.63 101.72 52.33 101.72 52.33 103.08 52.55 103.08 52.55 101.72 53.25 101.72 53.25 103.08 53.47 103.08 53.47 101.72 54.17 101.72 54.17 103.08 54.39 103.08 54.39 101.72 55.09 101.72 55.09 103.08 57.15 103.08 57.15 101.72 57.85 101.72 57.85 103.08 58.07 103.08 58.07 101.72 58.77 101.72 58.77 103.08 58.99 103.08 58.99 101.72 59.69 101.72 59.69 103.08 59.91 103.08 59.91 101.72 60.61 101.72 60.61 103.08 60.83 103.08 60.83 101.72 61.53 101.72 61.53 103.08 61.75 103.08 61.75 101.72 62.45 101.72 62.45 103.08 63.13 103.08 63.13 101.72 63.83 101.72 63.83 103.08 64.05 103.08 64.05 101.72 64.75 101.72 64.75 103.08 66.35 103.08 66.35 101.72 67.05 101.72 67.05 103.08 67.27 103.08 67.27 101.72 67.97 101.72 67.97 103.08 68.19 103.08 68.19 101.72 68.89 101.72 68.89 103.08 69.11 103.08 69.11 101.72 69.81 101.72 69.81 103.08 70.03 103.08 70.03 101.72 70.73 101.72 70.73 103.08 70.95 103.08 70.95 101.72 71.65 101.72 71.65 103.08 71.87 103.08 71.87 101.72 72.57 101.72 72.57 103.08 72.79 103.08 72.79 101.72 73.49 101.72 73.49 103.08 73.71 103.08 73.71 101.72 74.41 101.72 74.41 103.08 74.63 103.08 74.63 101.72 75.33 101.72 75.33 103.08 75.55 103.08 75.55 101.72 76.25 101.72 76.25 103.08 76.47 103.08 76.47 101.72 77.17 101.72 77.17 103.08 77.39 103.08 77.39 101.72 78.09 101.72 78.09 103.08 78.31 103.08 78.31 101.72 79.01 101.72 79.01 103.08 79.23 103.08 79.23 101.72 79.93 101.72 79.93 103.08 80.15 103.08 80.15 101.72 80.85 101.72 80.85 103.08 81.07 103.08 81.07 101.72 81.77 101.72 81.77 103.08 81.99 103.08 81.99 101.72 82.69 101.72 82.69 103.08 83.37 103.08 83.37 101.72 84.07 101.72 84.07 103.08 84.29 103.08 84.29 101.72 84.99 101.72 84.99 103.08 86.59 103.08 86.59 101.72 87.29 101.72 87.29 103.08 93.49 103.08 93.49 101.72 94.19 101.72 94.19 103.08 95.33 103.08 95.33 101.72 96.03 101.72 96.03 103.08 96.25 103.08 96.25 101.72 96.95 101.72 96.95 103.08 97.17 103.08 97.17 101.72 97.87 101.72 97.87 103.08 98.55 103.08 98.55 101.72 99.25 101.72 99.25 103.08 107.75 103.08 107.75 101.72 108.45 101.72 108.45 103.08 110.51 103.08 110.51 101.72 111.21 101.72 111.21 103.08 ; + LAYER met4 ; + POLYGON 112.76 102.96 112.76 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 7.14 0.4 7.14 1 5.74 1 5.74 0.4 0.4 0.4 0.4 75.76 5.74 75.76 5.74 75.16 7.14 75.16 7.14 75.76 28.92 75.76 28.92 102.96 40.7 102.96 40.7 102.36 42.1 102.36 42.1 102.96 55.42 102.96 55.42 102.36 56.82 102.36 56.82 102.96 70.14 102.96 70.14 102.36 71.54 102.36 71.54 102.96 84.86 102.96 84.86 102.36 86.26 102.36 86.26 102.96 99.58 102.96 99.58 102.36 100.98 102.36 100.98 102.96 ; + LAYER met5 ; + POLYGON 106.76 100.16 106.76 92.44 109.96 92.44 109.96 63.28 106.76 63.28 106.76 53.68 109.96 53.68 109.96 42.88 106.76 42.88 106.76 33.28 109.96 33.28 109.96 22.48 106.76 22.48 106.76 12.88 109.96 12.88 109.96 3.2 3.2 3.2 3.2 12.88 6.4 12.88 6.4 22.48 3.2 22.48 3.2 33.28 6.4 33.28 6.4 42.88 3.2 42.88 3.2 53.68 6.4 53.68 6.4 63.28 3.2 63.28 3.2 72.96 31.72 72.96 31.72 92.44 34.92 92.44 34.92 100.16 ; + LAYER met1 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 28.8 76.68 28.8 78.36 29.28 78.36 29.28 79.4 28.8 79.4 28.8 81.08 29.28 81.08 29.28 82.12 28.8 82.12 28.8 83.8 29.28 83.8 29.28 84.84 28.8 84.84 28.8 86.52 29.28 86.52 29.28 87.56 28.8 87.56 28.8 89.24 29.28 89.24 29.28 90.28 28.8 90.28 28.8 91.96 29.28 91.96 29.28 93 28.8 93 28.8 94.68 29.28 94.68 29.28 95.72 28.8 95.72 28.8 97.4 29.28 97.4 29.28 98.44 28.8 98.44 28.8 100.12 29.28 100.12 29.28 101.16 28.8 101.16 28.8 102.84 ; + POLYGON 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 112.4 27.72 112.4 26.68 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + LAYER li1 ; + POLYGON 112.82 103.02 112.82 0.34 0.34 0.34 0.34 75.82 28.86 75.82 28.86 103.02 ; + LAYER mcon ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 29.125 100.555 29.295 100.725 ; + RECT 28.665 100.555 28.835 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 29.125 95.115 29.295 95.285 ; + RECT 28.665 95.115 28.835 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 29.125 92.395 29.295 92.565 ; + RECT 28.665 92.395 28.835 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 29.125 89.675 29.295 89.845 ; + RECT 28.665 89.675 28.835 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 29.125 84.235 29.295 84.405 ; + RECT 28.665 84.235 28.835 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 29.125 81.515 29.295 81.685 ; + RECT 28.665 81.515 28.835 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 29.125 78.795 29.295 78.965 ; + RECT 28.665 78.795 28.835 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 111.925 76.075 112.095 76.245 ; + RECT 111.465 76.075 111.635 76.245 ; + RECT 111.005 76.075 111.175 76.245 ; + RECT 110.545 76.075 110.715 76.245 ; + RECT 110.085 76.075 110.255 76.245 ; + RECT 109.625 76.075 109.795 76.245 ; + RECT 109.165 76.075 109.335 76.245 ; + RECT 108.705 76.075 108.875 76.245 ; + RECT 108.245 76.075 108.415 76.245 ; + RECT 107.785 76.075 107.955 76.245 ; + RECT 107.325 76.075 107.495 76.245 ; + RECT 106.865 76.075 107.035 76.245 ; + RECT 106.405 76.075 106.575 76.245 ; + RECT 105.945 76.075 106.115 76.245 ; + RECT 105.485 76.075 105.655 76.245 ; + RECT 105.025 76.075 105.195 76.245 ; + RECT 104.565 76.075 104.735 76.245 ; + RECT 104.105 76.075 104.275 76.245 ; + RECT 103.645 76.075 103.815 76.245 ; + RECT 103.185 76.075 103.355 76.245 ; + RECT 102.725 76.075 102.895 76.245 ; + RECT 102.265 76.075 102.435 76.245 ; + RECT 101.805 76.075 101.975 76.245 ; + RECT 101.345 76.075 101.515 76.245 ; + RECT 100.885 76.075 101.055 76.245 ; + RECT 100.425 76.075 100.595 76.245 ; + RECT 99.965 76.075 100.135 76.245 ; + RECT 99.505 76.075 99.675 76.245 ; + RECT 99.045 76.075 99.215 76.245 ; + RECT 98.585 76.075 98.755 76.245 ; + RECT 98.125 76.075 98.295 76.245 ; + RECT 97.665 76.075 97.835 76.245 ; + RECT 97.205 76.075 97.375 76.245 ; + RECT 96.745 76.075 96.915 76.245 ; + RECT 96.285 76.075 96.455 76.245 ; + RECT 95.825 76.075 95.995 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 94.445 76.075 94.615 76.245 ; + RECT 93.985 76.075 94.155 76.245 ; + RECT 93.525 76.075 93.695 76.245 ; + RECT 93.065 76.075 93.235 76.245 ; + RECT 92.605 76.075 92.775 76.245 ; + RECT 92.145 76.075 92.315 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; + RECT 90.765 76.075 90.935 76.245 ; + RECT 90.305 76.075 90.475 76.245 ; + RECT 89.845 76.075 90.015 76.245 ; + RECT 89.385 76.075 89.555 76.245 ; + RECT 88.925 76.075 89.095 76.245 ; + RECT 88.465 76.075 88.635 76.245 ; + RECT 88.005 76.075 88.175 76.245 ; + RECT 87.545 76.075 87.715 76.245 ; + RECT 87.085 76.075 87.255 76.245 ; + RECT 86.625 76.075 86.795 76.245 ; + RECT 86.165 76.075 86.335 76.245 ; + RECT 85.705 76.075 85.875 76.245 ; + RECT 85.245 76.075 85.415 76.245 ; + RECT 84.785 76.075 84.955 76.245 ; + RECT 84.325 76.075 84.495 76.245 ; + RECT 83.865 76.075 84.035 76.245 ; + RECT 83.405 76.075 83.575 76.245 ; + RECT 82.945 76.075 83.115 76.245 ; + RECT 82.485 76.075 82.655 76.245 ; + RECT 82.025 76.075 82.195 76.245 ; + RECT 81.565 76.075 81.735 76.245 ; + RECT 81.105 76.075 81.275 76.245 ; + RECT 80.645 76.075 80.815 76.245 ; + RECT 80.185 76.075 80.355 76.245 ; + RECT 79.725 76.075 79.895 76.245 ; + RECT 79.265 76.075 79.435 76.245 ; + RECT 78.805 76.075 78.975 76.245 ; + RECT 78.345 76.075 78.515 76.245 ; + RECT 77.885 76.075 78.055 76.245 ; + RECT 77.425 76.075 77.595 76.245 ; + RECT 76.965 76.075 77.135 76.245 ; + RECT 76.505 76.075 76.675 76.245 ; + RECT 76.045 76.075 76.215 76.245 ; + RECT 75.585 76.075 75.755 76.245 ; + RECT 75.125 76.075 75.295 76.245 ; + RECT 74.665 76.075 74.835 76.245 ; + RECT 74.205 76.075 74.375 76.245 ; + RECT 73.745 76.075 73.915 76.245 ; + RECT 73.285 76.075 73.455 76.245 ; + RECT 72.825 76.075 72.995 76.245 ; + RECT 72.365 76.075 72.535 76.245 ; + RECT 71.905 76.075 72.075 76.245 ; + RECT 71.445 76.075 71.615 76.245 ; + RECT 70.985 76.075 71.155 76.245 ; + RECT 70.525 76.075 70.695 76.245 ; + RECT 70.065 76.075 70.235 76.245 ; + RECT 69.605 76.075 69.775 76.245 ; + RECT 69.145 76.075 69.315 76.245 ; + RECT 68.685 76.075 68.855 76.245 ; + RECT 68.225 76.075 68.395 76.245 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; + RECT 65.005 76.075 65.175 76.245 ; + RECT 64.545 76.075 64.715 76.245 ; + RECT 64.085 76.075 64.255 76.245 ; + RECT 63.625 76.075 63.795 76.245 ; + RECT 63.165 76.075 63.335 76.245 ; + RECT 62.705 76.075 62.875 76.245 ; + RECT 62.245 76.075 62.415 76.245 ; + RECT 61.785 76.075 61.955 76.245 ; + RECT 61.325 76.075 61.495 76.245 ; + RECT 60.865 76.075 61.035 76.245 ; + RECT 60.405 76.075 60.575 76.245 ; + RECT 59.945 76.075 60.115 76.245 ; + RECT 59.485 76.075 59.655 76.245 ; + RECT 59.025 76.075 59.195 76.245 ; + RECT 58.565 76.075 58.735 76.245 ; + RECT 58.105 76.075 58.275 76.245 ; + RECT 57.645 76.075 57.815 76.245 ; + RECT 57.185 76.075 57.355 76.245 ; + RECT 56.725 76.075 56.895 76.245 ; + RECT 56.265 76.075 56.435 76.245 ; + RECT 55.805 76.075 55.975 76.245 ; + RECT 55.345 76.075 55.515 76.245 ; + RECT 54.885 76.075 55.055 76.245 ; + RECT 54.425 76.075 54.595 76.245 ; + RECT 53.965 76.075 54.135 76.245 ; + RECT 53.505 76.075 53.675 76.245 ; + RECT 53.045 76.075 53.215 76.245 ; + RECT 52.585 76.075 52.755 76.245 ; + RECT 52.125 76.075 52.295 76.245 ; + RECT 51.665 76.075 51.835 76.245 ; + RECT 51.205 76.075 51.375 76.245 ; + RECT 50.745 76.075 50.915 76.245 ; + RECT 50.285 76.075 50.455 76.245 ; + RECT 49.825 76.075 49.995 76.245 ; + RECT 49.365 76.075 49.535 76.245 ; + RECT 48.905 76.075 49.075 76.245 ; + RECT 48.445 76.075 48.615 76.245 ; + RECT 47.985 76.075 48.155 76.245 ; + RECT 47.525 76.075 47.695 76.245 ; + RECT 47.065 76.075 47.235 76.245 ; + RECT 46.605 76.075 46.775 76.245 ; + RECT 46.145 76.075 46.315 76.245 ; + RECT 45.685 76.075 45.855 76.245 ; + RECT 45.225 76.075 45.395 76.245 ; + RECT 44.765 76.075 44.935 76.245 ; + RECT 44.305 76.075 44.475 76.245 ; + RECT 43.845 76.075 44.015 76.245 ; + RECT 43.385 76.075 43.555 76.245 ; + RECT 42.925 76.075 43.095 76.245 ; + RECT 42.465 76.075 42.635 76.245 ; + RECT 42.005 76.075 42.175 76.245 ; + RECT 41.545 76.075 41.715 76.245 ; + RECT 41.085 76.075 41.255 76.245 ; + RECT 40.625 76.075 40.795 76.245 ; + RECT 40.165 76.075 40.335 76.245 ; + RECT 39.705 76.075 39.875 76.245 ; + RECT 39.245 76.075 39.415 76.245 ; + RECT 38.785 76.075 38.955 76.245 ; + RECT 38.325 76.075 38.495 76.245 ; + RECT 37.865 76.075 38.035 76.245 ; + RECT 37.405 76.075 37.575 76.245 ; + RECT 36.945 76.075 37.115 76.245 ; + RECT 36.485 76.075 36.655 76.245 ; + RECT 36.025 76.075 36.195 76.245 ; + RECT 35.565 76.075 35.735 76.245 ; + RECT 35.105 76.075 35.275 76.245 ; + RECT 34.645 76.075 34.815 76.245 ; + RECT 34.185 76.075 34.355 76.245 ; + RECT 33.725 76.075 33.895 76.245 ; + RECT 33.265 76.075 33.435 76.245 ; + RECT 32.805 76.075 32.975 76.245 ; + RECT 32.345 76.075 32.515 76.245 ; + RECT 31.885 76.075 32.055 76.245 ; + RECT 31.425 76.075 31.595 76.245 ; + RECT 30.965 76.075 31.135 76.245 ; + RECT 30.505 76.075 30.675 76.245 ; + RECT 30.045 76.075 30.215 76.245 ; + RECT 29.585 76.075 29.755 76.245 ; + RECT 29.125 76.075 29.295 76.245 ; + RECT 28.665 76.075 28.835 76.245 ; + RECT 28.205 76.075 28.375 76.245 ; + RECT 27.745 76.075 27.915 76.245 ; + RECT 27.285 76.075 27.455 76.245 ; + RECT 26.825 76.075 26.995 76.245 ; + RECT 26.365 76.075 26.535 76.245 ; + RECT 25.905 76.075 26.075 76.245 ; + RECT 25.445 76.075 25.615 76.245 ; + RECT 24.985 76.075 25.155 76.245 ; + RECT 24.525 76.075 24.695 76.245 ; + RECT 24.065 76.075 24.235 76.245 ; + RECT 23.605 76.075 23.775 76.245 ; + RECT 23.145 76.075 23.315 76.245 ; + RECT 22.685 76.075 22.855 76.245 ; + RECT 22.225 76.075 22.395 76.245 ; + RECT 21.765 76.075 21.935 76.245 ; + RECT 21.305 76.075 21.475 76.245 ; + RECT 20.845 76.075 21.015 76.245 ; + RECT 20.385 76.075 20.555 76.245 ; + RECT 19.925 76.075 20.095 76.245 ; + RECT 19.465 76.075 19.635 76.245 ; + RECT 19.005 76.075 19.175 76.245 ; + RECT 18.545 76.075 18.715 76.245 ; + RECT 18.085 76.075 18.255 76.245 ; + RECT 17.625 76.075 17.795 76.245 ; + RECT 17.165 76.075 17.335 76.245 ; + RECT 16.705 76.075 16.875 76.245 ; + RECT 16.245 76.075 16.415 76.245 ; + RECT 15.785 76.075 15.955 76.245 ; + RECT 15.325 76.075 15.495 76.245 ; + RECT 14.865 76.075 15.035 76.245 ; + RECT 14.405 76.075 14.575 76.245 ; + RECT 13.945 76.075 14.115 76.245 ; + RECT 13.485 76.075 13.655 76.245 ; + RECT 13.025 76.075 13.195 76.245 ; + RECT 12.565 76.075 12.735 76.245 ; + RECT 12.105 76.075 12.275 76.245 ; + RECT 11.645 76.075 11.815 76.245 ; + RECT 11.185 76.075 11.355 76.245 ; + RECT 10.725 76.075 10.895 76.245 ; + RECT 10.265 76.075 10.435 76.245 ; + RECT 9.805 76.075 9.975 76.245 ; + RECT 9.345 76.075 9.515 76.245 ; + RECT 8.885 76.075 9.055 76.245 ; + RECT 8.425 76.075 8.595 76.245 ; + RECT 7.965 76.075 8.135 76.245 ; + RECT 7.505 76.075 7.675 76.245 ; + RECT 7.045 76.075 7.215 76.245 ; + RECT 6.585 76.075 6.755 76.245 ; + RECT 6.125 76.075 6.295 76.245 ; + RECT 5.665 76.075 5.835 76.245 ; + RECT 5.205 76.075 5.375 76.245 ; + RECT 4.745 76.075 4.915 76.245 ; + RECT 4.285 76.075 4.455 76.245 ; + RECT 3.825 76.075 3.995 76.245 ; + RECT 3.365 76.075 3.535 76.245 ; + RECT 2.905 76.075 3.075 76.245 ; + RECT 2.445 76.075 2.615 76.245 ; + RECT 1.985 76.075 2.155 76.245 ; + RECT 1.525 76.075 1.695 76.245 ; + RECT 1.065 76.075 1.235 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 0.605 24.395 0.775 24.565 ; + RECT 0.145 24.395 0.315 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 0.605 21.675 0.775 21.845 ; + RECT 0.145 21.675 0.315 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 0.605 18.955 0.775 19.125 ; + RECT 0.145 18.955 0.315 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 0.605 16.235 0.775 16.405 ; + RECT 0.145 16.235 0.315 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 0.605 8.075 0.775 8.245 ; + RECT 0.145 8.075 0.315 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 0.605 5.355 0.775 5.525 ; + RECT 0.145 5.355 0.315 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + RECT 28.205 -0.085 28.375 0.085 ; + RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; + RECT 25.445 -0.085 25.615 0.085 ; + RECT 24.985 -0.085 25.155 0.085 ; + RECT 24.525 -0.085 24.695 0.085 ; + RECT 24.065 -0.085 24.235 0.085 ; + RECT 23.605 -0.085 23.775 0.085 ; + RECT 23.145 -0.085 23.315 0.085 ; + RECT 22.685 -0.085 22.855 0.085 ; + RECT 22.225 -0.085 22.395 0.085 ; + RECT 21.765 -0.085 21.935 0.085 ; + RECT 21.305 -0.085 21.475 0.085 ; + RECT 20.845 -0.085 21.015 0.085 ; + RECT 20.385 -0.085 20.555 0.085 ; + RECT 19.925 -0.085 20.095 0.085 ; + RECT 19.465 -0.085 19.635 0.085 ; + RECT 19.005 -0.085 19.175 0.085 ; + RECT 18.545 -0.085 18.715 0.085 ; + RECT 18.085 -0.085 18.255 0.085 ; + RECT 17.625 -0.085 17.795 0.085 ; + RECT 17.165 -0.085 17.335 0.085 ; + RECT 16.705 -0.085 16.875 0.085 ; + RECT 16.245 -0.085 16.415 0.085 ; + RECT 15.785 -0.085 15.955 0.085 ; + RECT 15.325 -0.085 15.495 0.085 ; + RECT 14.865 -0.085 15.035 0.085 ; + RECT 14.405 -0.085 14.575 0.085 ; + RECT 13.945 -0.085 14.115 0.085 ; + RECT 13.485 -0.085 13.655 0.085 ; + RECT 13.025 -0.085 13.195 0.085 ; + RECT 12.565 -0.085 12.735 0.085 ; + RECT 12.105 -0.085 12.275 0.085 ; + RECT 11.645 -0.085 11.815 0.085 ; + RECT 11.185 -0.085 11.355 0.085 ; + RECT 10.725 -0.085 10.895 0.085 ; + RECT 10.265 -0.085 10.435 0.085 ; + RECT 9.805 -0.085 9.975 0.085 ; + RECT 9.345 -0.085 9.515 0.085 ; + RECT 8.885 -0.085 9.055 0.085 ; + RECT 8.425 -0.085 8.595 0.085 ; + RECT 7.965 -0.085 8.135 0.085 ; + RECT 7.505 -0.085 7.675 0.085 ; + RECT 7.045 -0.085 7.215 0.085 ; + RECT 6.585 -0.085 6.755 0.085 ; + RECT 6.125 -0.085 6.295 0.085 ; + RECT 5.665 -0.085 5.835 0.085 ; + RECT 5.205 -0.085 5.375 0.085 ; + RECT 4.745 -0.085 4.915 0.085 ; + RECT 4.285 -0.085 4.455 0.085 ; + RECT 3.825 -0.085 3.995 0.085 ; + RECT 3.365 -0.085 3.535 0.085 ; + RECT 2.905 -0.085 3.075 0.085 ; + RECT 2.445 -0.085 2.615 0.085 ; + RECT 1.985 -0.085 2.155 0.085 ; + RECT 1.525 -0.085 1.695 0.085 ; + RECT 1.065 -0.085 1.235 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + RECT 0.145 -0.085 0.315 0.085 ; + LAYER via ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 85.485 76.085 85.635 76.235 ; + RECT 56.045 76.085 56.195 76.235 ; + RECT 6.365 76.085 6.515 76.235 ; + RECT 7.285 74.385 7.435 74.535 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 6.365 -0.075 6.515 0.075 ; + LAYER via2 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 29.8 99.86 30 100.06 ; + RECT 6.34 76.06 6.54 76.26 ; + RECT 1.28 71.98 1.48 72.18 ; + RECT 1.74 58.38 1.94 58.58 ; + RECT 1.74 23.02 1.94 23.22 ; + RECT 1.74 17.58 1.94 17.78 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 6.34 -0.1 6.54 0.1 ; + LAYER via3 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 76.06 6.54 76.26 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 6.34 -0.1 6.54 0.1 ; + LAYER via4 ; + RECT 6.04 38.48 6.84 39.28 ; + RECT 6.04 36.88 6.84 37.68 ; + LAYER fieldpoly ; + POLYGON 113.02 103.22 113.02 0.14 0.14 0.14 0.14 76.02 28.66 76.02 28.66 103.22 ; + LAYER diff ; + POLYGON 113.16 103.36 113.16 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER nwell ; + POLYGON 113.35 102.055 113.35 99.225 112.51 99.225 112.51 100.45 109.29 100.45 109.29 102.055 ; + POLYGON 32.39 102.055 32.39 100.45 30.55 100.45 30.55 99.225 28.33 99.225 28.33 102.055 ; + POLYGON 113.35 96.615 113.35 93.785 109.29 93.785 109.29 95.39 112.51 95.39 112.51 96.615 ; + RECT 28.33 93.785 32.39 96.615 ; + POLYGON 113.35 91.175 113.35 88.345 112.51 88.345 112.51 89.57 112.05 89.57 112.05 91.175 ; + RECT 28.33 88.345 32.39 91.175 ; + POLYGON 113.35 85.735 113.35 82.905 112.51 82.905 112.51 84.13 112.05 84.13 112.05 85.735 ; + RECT 28.33 82.905 32.39 85.735 ; + POLYGON 113.35 80.295 113.35 77.465 112.51 77.465 112.51 78.69 111.13 78.69 111.13 80.295 ; + POLYGON 32.39 80.295 32.39 78.69 30.55 78.69 30.55 77.465 28.33 77.465 28.33 80.295 ; + RECT 112.51 72.025 113.35 74.855 ; + RECT -0.19 72.025 3.87 74.855 ; + RECT 112.51 66.585 113.35 69.415 ; + POLYGON 2.03 69.415 2.03 68.19 3.87 68.19 3.87 66.585 -0.19 66.585 -0.19 69.415 ; + POLYGON 113.35 63.975 113.35 61.145 111.13 61.145 111.13 62.75 112.51 62.75 112.51 63.975 ; + RECT -0.19 61.145 2.03 63.975 ; + RECT 112.51 55.705 113.35 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + POLYGON 113.35 53.095 113.35 50.265 112.05 50.265 112.05 51.87 112.51 51.87 112.51 53.095 ; + POLYGON 2.03 53.095 2.03 51.87 3.87 51.87 3.87 50.265 -0.19 50.265 -0.19 53.095 ; + POLYGON 113.35 47.655 113.35 44.825 112.51 44.825 112.51 46.05 112.05 46.05 112.05 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 112.51 39.385 113.35 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + POLYGON 113.35 36.775 113.35 33.945 112.05 33.945 112.05 35.17 111.13 35.17 111.13 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + POLYGON 113.35 31.335 113.35 28.505 109.29 28.505 109.29 30.11 112.51 30.11 112.51 31.335 ; + RECT -0.19 28.505 2.03 31.335 ; + RECT 111.13 23.065 113.35 25.895 ; + RECT -0.19 23.065 2.03 25.895 ; + POLYGON 113.35 20.455 113.35 17.625 112.05 17.625 112.05 18.85 111.13 18.85 111.13 20.455 ; + RECT -0.19 17.625 2.03 20.455 ; + RECT 112.05 12.185 113.35 15.015 ; + POLYGON 3.87 15.015 3.87 13.41 2.03 13.41 2.03 12.185 -0.19 12.185 -0.19 15.015 ; + RECT 112.05 6.745 113.35 9.575 ; + POLYGON 2.03 9.575 2.03 8.35 3.87 8.35 3.87 6.745 -0.19 6.745 -0.19 9.575 ; + RECT 112.05 1.305 113.35 4.135 ; + RECT -0.19 1.305 3.87 4.135 ; + POLYGON 113.16 103.36 113.16 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER pwell ; + RECT 109.61 103.31 109.83 103.48 ; + RECT 105.93 103.31 106.15 103.48 ; + RECT 102.25 103.31 102.47 103.48 ; + RECT 98.57 103.31 98.79 103.48 ; + RECT 94.89 103.31 95.11 103.48 ; + RECT 91.21 103.31 91.43 103.48 ; + RECT 87.53 103.31 87.75 103.48 ; + RECT 83.85 103.31 84.07 103.48 ; + RECT 80.17 103.31 80.39 103.48 ; + RECT 76.49 103.31 76.71 103.48 ; + RECT 72.81 103.31 73.03 103.48 ; + RECT 69.13 103.31 69.35 103.48 ; + RECT 65.45 103.31 65.67 103.48 ; + RECT 61.77 103.31 61.99 103.48 ; + RECT 58.09 103.31 58.31 103.48 ; + RECT 54.41 103.31 54.63 103.48 ; + RECT 50.73 103.31 50.95 103.48 ; + RECT 47.05 103.31 47.27 103.48 ; + RECT 43.37 103.31 43.59 103.48 ; + RECT 39.69 103.31 39.91 103.48 ; + RECT 36.01 103.31 36.23 103.48 ; + RECT 32.33 103.31 32.55 103.48 ; + RECT 28.65 103.31 28.87 103.48 ; + RECT 25.89 76.11 26.11 76.28 ; + RECT 22.21 76.11 22.43 76.28 ; + RECT 18.53 76.11 18.75 76.28 ; + RECT 14.85 76.11 15.07 76.28 ; + RECT 11.17 76.11 11.39 76.28 ; + RECT 7.49 76.11 7.71 76.28 ; + RECT 3.81 76.11 4.03 76.28 ; + RECT 0.13 76.11 0.35 76.28 ; + RECT 112.395 -0.05 112.555 0.06 ; + RECT 110.575 -0.06 110.685 0.06 ; + RECT 106.85 -0.12 107.07 0.05 ; + RECT 103.17 -0.12 103.39 0.05 ; + RECT 99.49 -0.12 99.71 0.05 ; + RECT 95.81 -0.12 96.03 0.05 ; + RECT 92.13 -0.12 92.35 0.05 ; + RECT 88.45 -0.12 88.67 0.05 ; + RECT 84.77 -0.12 84.99 0.05 ; + RECT 81.09 -0.12 81.31 0.05 ; + RECT 77.41 -0.12 77.63 0.05 ; + RECT 73.73 -0.12 73.95 0.05 ; + RECT 70.05 -0.12 70.27 0.05 ; + RECT 66.37 -0.12 66.59 0.05 ; + RECT 62.69 -0.12 62.91 0.05 ; + RECT 59.01 -0.12 59.23 0.05 ; + RECT 55.33 -0.12 55.55 0.05 ; + RECT 51.65 -0.12 51.87 0.05 ; + RECT 47.97 -0.12 48.19 0.05 ; + RECT 44.29 -0.12 44.51 0.05 ; + RECT 40.61 -0.12 40.83 0.05 ; + RECT 36.93 -0.12 37.15 0.05 ; + RECT 33.25 -0.12 33.47 0.05 ; + RECT 29.57 -0.12 29.79 0.05 ; + RECT 25.89 -0.12 26.11 0.05 ; + RECT 22.21 -0.12 22.43 0.05 ; + RECT 18.53 -0.12 18.75 0.05 ; + RECT 14.85 -0.12 15.07 0.05 ; + RECT 11.17 -0.12 11.39 0.05 ; + RECT 7.49 -0.12 7.71 0.05 ; + RECT 3.81 -0.12 4.03 0.05 ; + RECT 0.13 -0.12 0.35 0.05 ; + POLYGON 113.16 103.36 113.16 0 0 0 0 76.16 28.52 76.16 28.52 103.36 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 28.52 76.16 28.52 103.36 113.16 103.36 113.16 0 ; + END +END sb_2__0_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef new file mode 100644 index 0000000..40ba30e --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -0,0 +1,3043 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 130.56 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 2.23 27.2 2.37 28.56 ; + END + END prog_clk[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 129.2 80.57 130.56 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 129.2 57.57 130.56 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 129.2 82.41 130.56 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 129.2 74.13 130.56 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.91 129.2 52.05 130.56 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.19 129.2 60.33 130.56 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 129.2 75.05 130.56 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.63 129.2 66.77 130.56 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.15 129.2 72.29 130.56 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.55 129.2 67.69 130.56 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 129.2 73.21 130.56 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 129.2 75.97 130.56 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.83 129.2 52.97 130.56 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 129.2 63.55 130.56 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.67 129.2 54.81 130.56 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.75 129.2 53.89 130.56 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.39 129.2 69.53 130.56 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 129.2 81.49 130.56 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.57 129.2 84.71 130.56 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.27 129.2 59.41 130.56 ; + END + END chany_top_in[19] + PIN top_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.59 129.2 32.73 130.56 ; + END + END top_left_grid_pin_34_[0] + PIN top_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.75 129.2 30.89 130.56 ; + END + END top_left_grid_pin_35_[0] + PIN top_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 127.01 29.9 127.31 ; + END + END top_left_grid_pin_36_[0] + PIN top_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.67 129.2 31.81 130.56 ; + END + END top_left_grid_pin_37_[0] + PIN top_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 124.97 29.9 125.27 ; + END + END top_left_grid_pin_38_[0] + PIN top_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 123.61 29.9 123.91 ; + END + END top_left_grid_pin_39_[0] + PIN top_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 122.25 29.9 122.55 ; + END + END top_left_grid_pin_40_[0] + PIN top_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 117.49 29.9 117.79 ; + END + END top_left_grid_pin_41_[0] + PIN top_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 108.03 129.2 108.17 130.56 ; + END + END top_right_grid_pin_1_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 0 67.23 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 0 81.49 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.25 0 88.39 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 0 75.97 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.23 0 94.37 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.33 0 87.47 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 0 77.81 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.11 0 84.25 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.49 0 62.63 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.41 0 86.55 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 0 79.65 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 0 68.15 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.17 0 66.31 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.29 0 53.43 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 0 76.89 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.85 0 69.99 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 0 78.73 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 0 110.93 1.36 ; + END + END bottom_right_grid_pin_1_[0] + PIN bottom_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 10.05 29.9 10.35 ; + END + END bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 8.01 29.9 8.31 ; + END + END bottom_left_grid_pin_35_[0] + PIN bottom_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 6.65 29.9 6.95 ; + END + END bottom_left_grid_pin_36_[0] + PIN bottom_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 3.25 29.9 3.55 ; + END + END bottom_left_grid_pin_37_[0] + PIN bottom_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 4.61 29.9 4.91 ; + END + END bottom_left_grid_pin_38_[0] + PIN bottom_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 11.41 29.9 11.71 ; + END + END bottom_left_grid_pin_39_[0] + PIN bottom_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 12.77 29.9 13.07 ; + END + END bottom_left_grid_pin_40_[0] + PIN bottom_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 14.13 29.9 14.43 ; + END + END bottom_left_grid_pin_41_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 76.01 1.38 76.31 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 85.53 1.38 85.83 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 86.89 1.38 87.19 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.01 1.38 59.31 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 97.77 1.38 98.07 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 93.69 1.38 93.99 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 92.33 1.38 92.63 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 77.37 1.38 77.67 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.53 1.38 51.83 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.29 102 7.43 103.36 ; + END + END left_top_grid_pin_42_[0] + PIN left_top_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 118.85 29.9 119.15 ; + END + END left_top_grid_pin_43_[0] + PIN left_top_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.07 102 4.21 103.36 ; + END + END left_top_grid_pin_44_[0] + PIN left_top_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.99 102 5.13 103.36 ; + END + END left_top_grid_pin_45_[0] + PIN left_top_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 102 2.37 103.36 ; + END + END left_top_grid_pin_46_[0] + PIN left_top_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.15 102 3.29 103.36 ; + END + END left_top_grid_pin_47_[0] + PIN left_top_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.43 102 11.57 103.36 ; + END + END left_top_grid_pin_48_[0] + PIN left_top_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.51 102 10.65 103.36 ; + END + END left_top_grid_pin_49_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 107.49 129.2 107.79 130.56 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 129.2 76.89 130.56 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.11 129.2 61.25 130.56 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 129.2 77.81 130.56 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.23 129.2 71.37 130.56 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.83 129.2 98.97 130.56 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.65 129.2 83.79 130.56 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.31 129.2 70.45 130.56 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.07 129.2 50.21 130.56 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.47 129.2 68.61 130.56 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.35 129.2 58.49 130.56 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 129.2 96.67 130.56 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.77 129.2 93.91 130.56 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 129.2 79.65 130.56 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 129.2 64.47 130.56 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 129.2 97.59 130.56 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.99 129.2 51.13 130.56 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.87 129.2 87.01 130.56 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.03 129.2 62.17 130.56 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.61 129.2 95.75 130.56 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 129.2 78.73 130.56 ; + END + END chany_top_out[19] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.19 0 83.33 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 0 59.87 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.37 0 52.51 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 0 69.07 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 0 96.67 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.69 0 71.83 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.65 0 60.79 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 0 63.55 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.31 0 93.45 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 0 74.13 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 0 80.57 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.57 0 61.71 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 0 97.59 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 0 64.47 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 0 58.95 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.77 0 70.91 1.36 ; + END + END chany_bottom_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 82.81 1.38 83.11 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 74.65 1.38 74.95 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 80.09 1.38 80.39 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.81 1.38 66.11 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 96.41 1.38 96.71 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.65 1.38 40.95 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.81 1.38 32.11 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 88.25 1.38 88.55 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 90.97 1.38 91.27 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 64.45 1.38 64.75 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 28.52 2.48 29 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 28.52 7.92 29 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 28.52 13.36 29 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 28.52 18.8 29 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 28.52 24.24 29 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + RECT 28.52 105.84 29 106.32 ; + RECT 112.68 105.84 113.16 106.32 ; + RECT 28.52 111.28 29 111.76 ; + RECT 112.68 111.28 113.16 111.76 ; + RECT 28.52 116.72 29 117.2 ; + RECT 112.68 116.72 113.16 117.2 ; + RECT 28.52 122.16 29 122.64 ; + RECT 112.68 122.16 113.16 122.64 ; + RECT 28.52 127.6 29 128.08 ; + RECT 112.68 127.6 113.16 128.08 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 109.96 43.28 113.16 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 109.96 84.08 113.16 87.28 ; + RECT 28.52 122.84 31.72 126.04 ; + RECT 109.96 122.84 113.16 126.04 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 41.1 129.96 41.7 130.56 ; + RECT 70.54 129.96 71.14 130.56 ; + RECT 99.98 129.96 100.58 130.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 28.52 0 113.16 0.24 ; + RECT 28.52 5.2 29 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 28.52 10.64 29 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 28.52 16.08 29 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 28.52 21.52 29 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 112.68 75.92 113.16 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 0 103.12 113.16 103.6 ; + RECT 28.52 108.56 29 109.04 ; + RECT 112.68 108.56 113.16 109.04 ; + RECT 28.52 114 29 114.48 ; + RECT 112.68 114 113.16 114.48 ; + RECT 28.52 119.44 29 119.92 ; + RECT 112.68 119.44 113.16 119.92 ; + RECT 28.52 124.88 29 125.36 ; + RECT 112.68 124.88 113.16 125.36 ; + RECT 28.52 130.32 113.16 130.56 ; + LAYER met4 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 27.2 6.74 27.8 ; + RECT 6.14 102.76 6.74 103.36 ; + RECT 55.82 129.96 56.42 130.56 ; + RECT 85.26 129.96 85.86 130.56 ; + LAYER met5 ; + RECT 28.52 4.52 31.72 7.72 ; + RECT 109.96 4.52 113.16 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 109.96 63.68 113.16 66.88 ; + END + END VSS + OBS + LAYER li1 ; + RECT 28.52 130.475 113.16 130.645 ; + RECT 109.48 127.755 113.16 127.925 ; + RECT 28.52 127.755 32.2 127.925 ; + RECT 111.32 125.035 113.16 125.205 ; + RECT 28.52 125.035 32.2 125.205 ; + RECT 109.48 122.315 113.16 122.485 ; + RECT 28.52 122.315 32.2 122.485 ; + RECT 109.48 119.595 113.16 119.765 ; + RECT 28.52 119.595 32.2 119.765 ; + RECT 112.24 116.875 113.16 117.045 ; + RECT 28.52 116.875 32.2 117.045 ; + RECT 112.7 114.155 113.16 114.325 ; + RECT 28.52 114.155 32.2 114.325 ; + RECT 112.7 111.435 113.16 111.605 ; + RECT 28.52 111.435 32.2 111.605 ; + RECT 112.24 108.715 113.16 108.885 ; + RECT 28.52 108.715 32.2 108.885 ; + RECT 109.48 105.995 113.16 106.165 ; + RECT 28.52 105.995 32.2 106.165 ; + RECT 109.48 103.275 113.16 103.445 ; + RECT 0 103.275 30.36 103.445 ; + RECT 109.48 100.555 113.16 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 109.48 97.835 113.16 98.005 ; + RECT 0 97.835 1.84 98.005 ; + RECT 111.32 95.115 113.16 95.285 ; + RECT 0 95.115 1.84 95.285 ; + RECT 109.48 92.395 113.16 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 109.48 89.675 113.16 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 109.48 86.955 113.16 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 111.32 84.235 113.16 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 111.32 81.515 113.16 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 112.24 78.795 113.16 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 112.24 76.075 113.16 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 112.7 73.355 113.16 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 112.7 70.635 113.16 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 109.48 67.915 113.16 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 109.48 65.195 113.16 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 112.24 62.475 113.16 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 109.48 59.755 113.16 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 109.48 57.035 113.16 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 109.48 54.315 113.16 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 112.7 51.595 113.16 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 112.24 48.875 113.16 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 112.24 46.155 113.16 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 109.48 43.435 113.16 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 109.48 40.715 113.16 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 111.32 37.995 113.16 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 111.32 35.275 113.16 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 112.24 32.555 113.16 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 111.32 29.835 113.16 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 111.32 27.115 113.16 27.285 ; + RECT 0 27.115 30.36 27.285 ; + RECT 112.24 24.395 113.16 24.565 ; + RECT 28.52 24.395 32.2 24.565 ; + RECT 112.24 21.675 113.16 21.845 ; + RECT 28.52 21.675 32.2 21.845 ; + RECT 112.24 18.955 113.16 19.125 ; + RECT 28.52 18.955 32.2 19.125 ; + RECT 112.7 16.235 113.16 16.405 ; + RECT 28.52 16.235 32.2 16.405 ; + RECT 112.7 13.515 113.16 13.685 ; + RECT 28.52 13.515 32.2 13.685 ; + RECT 112.7 10.795 113.16 10.965 ; + RECT 28.52 10.795 32.2 10.965 ; + RECT 112.7 8.075 113.16 8.245 ; + RECT 28.52 8.075 32.2 8.245 ; + RECT 112.7 5.355 113.16 5.525 ; + RECT 28.52 5.355 32.2 5.525 ; + RECT 109.48 2.635 113.16 2.805 ; + RECT 28.52 2.635 32.2 2.805 ; + RECT 28.52 -0.085 113.16 0.085 ; + LAYER met2 ; + RECT 85.42 130.375 85.7 130.745 ; + RECT 55.98 130.375 56.26 130.745 ; + RECT 81.75 128.7 82.01 129.02 ; + RECT 76.23 128.7 76.49 129.02 ; + RECT 68.87 128.7 69.13 129.02 ; + RECT 49.55 128.7 49.81 129.02 ; + RECT 6.3 103.175 6.58 103.545 ; + RECT 9.99 101.5 10.25 101.82 ; + RECT 6.3 27.015 6.58 27.385 ; + RECT 82.67 1.54 82.93 1.86 ; + RECT 73.47 1.54 73.73 1.86 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + POLYGON 112.88 130.28 112.88 0.28 111.21 0.28 111.21 1.64 110.51 1.64 110.51 0.28 97.87 0.28 97.87 1.64 97.17 1.64 97.17 0.28 96.95 0.28 96.95 1.64 96.25 1.64 96.25 0.28 94.65 0.28 94.65 1.64 93.95 1.64 93.95 0.28 93.73 0.28 93.73 1.64 93.03 1.64 93.03 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 86.83 0.28 86.83 1.64 86.13 1.64 86.13 0.28 84.53 0.28 84.53 1.64 83.83 1.64 83.83 0.28 83.61 0.28 83.61 1.64 82.91 1.64 82.91 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 76.25 0.28 76.25 1.64 75.55 1.64 75.55 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 28.8 0.28 28.8 27.48 2.65 27.48 2.65 28.84 1.95 28.84 1.95 27.48 0.28 27.48 0.28 103.08 1.95 103.08 1.95 101.72 2.65 101.72 2.65 103.08 2.87 103.08 2.87 101.72 3.57 101.72 3.57 103.08 3.79 103.08 3.79 101.72 4.49 101.72 4.49 103.08 4.71 103.08 4.71 101.72 5.41 101.72 5.41 103.08 7.01 103.08 7.01 101.72 7.71 101.72 7.71 103.08 10.23 103.08 10.23 101.72 10.93 101.72 10.93 103.08 11.15 103.08 11.15 101.72 11.85 101.72 11.85 103.08 28.8 103.08 28.8 130.28 30.47 130.28 30.47 128.92 31.17 128.92 31.17 130.28 31.39 130.28 31.39 128.92 32.09 128.92 32.09 130.28 32.31 130.28 32.31 128.92 33.01 128.92 33.01 130.28 49.79 130.28 49.79 128.92 50.49 128.92 50.49 130.28 50.71 130.28 50.71 128.92 51.41 128.92 51.41 130.28 51.63 130.28 51.63 128.92 52.33 128.92 52.33 130.28 52.55 130.28 52.55 128.92 53.25 128.92 53.25 130.28 53.47 130.28 53.47 128.92 54.17 128.92 54.17 130.28 54.39 130.28 54.39 128.92 55.09 128.92 55.09 130.28 57.15 130.28 57.15 128.92 57.85 128.92 57.85 130.28 58.07 130.28 58.07 128.92 58.77 128.92 58.77 130.28 58.99 130.28 58.99 128.92 59.69 128.92 59.69 130.28 59.91 130.28 59.91 128.92 60.61 128.92 60.61 130.28 60.83 130.28 60.83 128.92 61.53 128.92 61.53 130.28 61.75 130.28 61.75 128.92 62.45 128.92 62.45 130.28 63.13 130.28 63.13 128.92 63.83 128.92 63.83 130.28 64.05 130.28 64.05 128.92 64.75 128.92 64.75 130.28 66.35 130.28 66.35 128.92 67.05 128.92 67.05 130.28 67.27 130.28 67.27 128.92 67.97 128.92 67.97 130.28 68.19 130.28 68.19 128.92 68.89 128.92 68.89 130.28 69.11 130.28 69.11 128.92 69.81 128.92 69.81 130.28 70.03 130.28 70.03 128.92 70.73 128.92 70.73 130.28 70.95 130.28 70.95 128.92 71.65 128.92 71.65 130.28 71.87 130.28 71.87 128.92 72.57 128.92 72.57 130.28 72.79 130.28 72.79 128.92 73.49 128.92 73.49 130.28 73.71 130.28 73.71 128.92 74.41 128.92 74.41 130.28 74.63 130.28 74.63 128.92 75.33 128.92 75.33 130.28 75.55 130.28 75.55 128.92 76.25 128.92 76.25 130.28 76.47 130.28 76.47 128.92 77.17 128.92 77.17 130.28 77.39 130.28 77.39 128.92 78.09 128.92 78.09 130.28 78.31 130.28 78.31 128.92 79.01 128.92 79.01 130.28 79.23 130.28 79.23 128.92 79.93 128.92 79.93 130.28 80.15 130.28 80.15 128.92 80.85 128.92 80.85 130.28 81.07 130.28 81.07 128.92 81.77 128.92 81.77 130.28 81.99 130.28 81.99 128.92 82.69 128.92 82.69 130.28 83.37 130.28 83.37 128.92 84.07 128.92 84.07 130.28 84.29 130.28 84.29 128.92 84.99 128.92 84.99 130.28 86.59 130.28 86.59 128.92 87.29 128.92 87.29 130.28 93.49 130.28 93.49 128.92 94.19 128.92 94.19 130.28 95.33 130.28 95.33 128.92 96.03 128.92 96.03 130.28 96.25 130.28 96.25 128.92 96.95 128.92 96.95 130.28 97.17 130.28 97.17 128.92 97.87 128.92 97.87 130.28 98.55 130.28 98.55 128.92 99.25 128.92 99.25 130.28 107.75 130.28 107.75 128.92 108.45 128.92 108.45 130.28 ; + LAYER met3 ; + POLYGON 85.725 130.725 85.725 130.72 85.94 130.72 85.94 130.4 85.725 130.4 85.725 130.395 85.395 130.395 85.395 130.4 85.18 130.4 85.18 130.72 85.395 130.72 85.395 130.725 ; + POLYGON 56.285 130.725 56.285 130.72 56.5 130.72 56.5 130.4 56.285 130.4 56.285 130.395 55.955 130.395 55.955 130.4 55.74 130.4 55.74 130.72 55.955 130.72 55.955 130.725 ; + POLYGON 30.55 118.48 30.55 118.47 34.19 118.47 34.19 118.17 30.55 118.17 30.55 118.16 30.17 118.16 30.17 118.48 ; + POLYGON 6.605 103.525 6.605 103.52 6.82 103.52 6.82 103.2 6.605 103.2 6.605 103.195 6.275 103.195 6.275 103.2 6.06 103.2 6.06 103.52 6.275 103.52 6.275 103.525 ; + POLYGON 6.13 91.95 6.13 91.65 1.78 91.65 1.78 91.67 1.23 91.67 1.23 91.95 ; + POLYGON 12.11 76.99 12.11 76.69 1.78 76.69 1.78 76.71 1.23 76.71 1.23 76.99 ; + POLYGON 6.13 49.79 6.13 49.49 1.78 49.49 1.78 49.51 1.23 49.51 1.23 49.79 ; + POLYGON 13.95 44.35 13.95 44.05 1.78 44.05 1.78 44.07 1.23 44.07 1.23 44.35 ; + POLYGON 6.605 27.365 6.605 27.36 6.82 27.36 6.82 27.04 6.605 27.04 6.605 27.035 6.275 27.035 6.275 27.04 6.06 27.04 6.06 27.36 6.275 27.36 6.275 27.365 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 112.76 130.16 112.76 0.4 28.92 0.4 28.92 2.85 30.3 2.85 30.3 3.95 28.92 3.95 28.92 4.21 30.3 4.21 30.3 5.31 28.92 5.31 28.92 6.25 30.3 6.25 30.3 7.35 28.92 7.35 28.92 7.61 30.3 7.61 30.3 8.71 28.92 8.71 28.92 9.65 30.3 9.65 30.3 10.75 28.92 10.75 28.92 11.01 30.3 11.01 30.3 12.11 28.92 12.11 28.92 12.37 30.3 12.37 30.3 13.47 28.92 13.47 28.92 13.73 30.3 13.73 30.3 14.83 28.92 14.83 28.92 27.6 0.4 27.6 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 93.29 1.78 93.29 1.78 94.39 0.4 94.39 0.4 96.01 1.78 96.01 1.78 97.11 0.4 97.11 0.4 97.37 1.78 97.37 1.78 98.47 0.4 98.47 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 102.96 28.92 102.96 28.92 117.09 30.3 117.09 30.3 118.19 28.92 118.19 28.92 118.45 30.3 118.45 30.3 119.55 28.92 119.55 28.92 121.85 30.3 121.85 30.3 122.95 28.92 122.95 28.92 123.21 30.3 123.21 30.3 124.31 28.92 124.31 28.92 124.57 30.3 124.57 30.3 125.67 28.92 125.67 28.92 126.61 30.3 126.61 30.3 127.71 28.92 127.71 28.92 130.16 ; + LAYER met4 ; + POLYGON 112.76 130.16 112.76 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 28.92 0.4 28.92 27.6 7.14 27.6 7.14 28.2 5.74 28.2 5.74 27.6 0.4 27.6 0.4 102.96 5.74 102.96 5.74 102.36 7.14 102.36 7.14 102.96 28.92 102.96 28.92 130.16 40.7 130.16 40.7 129.56 42.1 129.56 42.1 130.16 55.42 130.16 55.42 129.56 56.82 129.56 56.82 130.16 70.14 130.16 70.14 129.56 71.54 129.56 71.54 130.16 84.86 130.16 84.86 129.56 86.26 129.56 86.26 130.16 99.58 130.16 99.58 129.56 100.98 129.56 100.98 130.16 107.09 130.16 107.09 128.8 108.19 128.8 108.19 130.16 ; + LAYER met5 ; + POLYGON 106.76 127.36 106.76 119.64 109.96 119.64 109.96 90.48 106.76 90.48 106.76 80.88 109.96 80.88 109.96 70.08 106.76 70.08 106.76 60.48 109.96 60.48 109.96 49.68 106.76 49.68 106.76 40.08 109.96 40.08 109.96 10.92 106.76 10.92 106.76 3.2 34.92 3.2 34.92 10.92 31.72 10.92 31.72 30.4 3.2 30.4 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 100.16 31.72 100.16 31.72 119.64 34.92 119.64 34.92 127.36 ; + LAYER met1 ; + POLYGON 112.88 130.04 112.88 128.36 112.4 128.36 112.4 127.32 112.88 127.32 112.88 125.64 112.4 125.64 112.4 124.6 112.88 124.6 112.88 122.92 112.4 122.92 112.4 121.88 112.88 121.88 112.88 120.2 112.4 120.2 112.4 119.16 112.88 119.16 112.88 117.48 112.4 117.48 112.4 116.44 112.88 116.44 112.88 114.76 112.4 114.76 112.4 113.72 112.88 113.72 112.88 112.04 112.4 112.04 112.4 111 112.88 111 112.88 109.32 112.4 109.32 112.4 108.28 112.88 108.28 112.88 106.6 112.4 106.6 112.4 105.56 112.88 105.56 112.88 103.88 28.8 103.88 28.8 105.56 29.28 105.56 29.28 106.6 28.8 106.6 28.8 108.28 29.28 108.28 29.28 109.32 28.8 109.32 28.8 111 29.28 111 29.28 112.04 28.8 112.04 28.8 113.72 29.28 113.72 29.28 114.76 28.8 114.76 28.8 116.44 29.28 116.44 29.28 117.48 28.8 117.48 28.8 119.16 29.28 119.16 29.28 120.2 28.8 120.2 28.8 121.88 29.28 121.88 29.28 122.92 28.8 122.92 28.8 124.6 29.28 124.6 29.28 125.64 28.8 125.64 28.8 127.32 29.28 127.32 29.28 128.36 28.8 128.36 28.8 130.04 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 112.4 76.68 112.4 75.64 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 28.8 0.52 28.8 2.2 29.28 2.2 29.28 3.24 28.8 3.24 28.8 4.92 29.28 4.92 29.28 5.96 28.8 5.96 28.8 7.64 29.28 7.64 29.28 8.68 28.8 8.68 28.8 10.36 29.28 10.36 29.28 11.4 28.8 11.4 28.8 13.08 29.28 13.08 29.28 14.12 28.8 14.12 28.8 15.8 29.28 15.8 29.28 16.84 28.8 16.84 28.8 18.52 29.28 18.52 29.28 19.56 28.8 19.56 28.8 21.24 29.28 21.24 29.28 22.28 28.8 22.28 28.8 23.96 29.28 23.96 29.28 25 28.8 25 28.8 26.68 ; + LAYER li1 ; + POLYGON 112.82 130.22 112.82 0.34 28.86 0.34 28.86 27.54 0.34 27.54 0.34 103.02 28.86 103.02 28.86 130.22 ; + LAYER mcon ; + RECT 112.845 130.475 113.015 130.645 ; + RECT 112.385 130.475 112.555 130.645 ; + RECT 111.925 130.475 112.095 130.645 ; + RECT 111.465 130.475 111.635 130.645 ; + RECT 111.005 130.475 111.175 130.645 ; + RECT 110.545 130.475 110.715 130.645 ; + RECT 110.085 130.475 110.255 130.645 ; + RECT 109.625 130.475 109.795 130.645 ; + RECT 109.165 130.475 109.335 130.645 ; + RECT 108.705 130.475 108.875 130.645 ; + RECT 108.245 130.475 108.415 130.645 ; + RECT 107.785 130.475 107.955 130.645 ; + RECT 107.325 130.475 107.495 130.645 ; + RECT 106.865 130.475 107.035 130.645 ; + RECT 106.405 130.475 106.575 130.645 ; + RECT 105.945 130.475 106.115 130.645 ; + RECT 105.485 130.475 105.655 130.645 ; + RECT 105.025 130.475 105.195 130.645 ; + RECT 104.565 130.475 104.735 130.645 ; + RECT 104.105 130.475 104.275 130.645 ; + RECT 103.645 130.475 103.815 130.645 ; + RECT 103.185 130.475 103.355 130.645 ; + RECT 102.725 130.475 102.895 130.645 ; + RECT 102.265 130.475 102.435 130.645 ; + RECT 101.805 130.475 101.975 130.645 ; + RECT 101.345 130.475 101.515 130.645 ; + RECT 100.885 130.475 101.055 130.645 ; + RECT 100.425 130.475 100.595 130.645 ; + RECT 99.965 130.475 100.135 130.645 ; + RECT 99.505 130.475 99.675 130.645 ; + RECT 99.045 130.475 99.215 130.645 ; + RECT 98.585 130.475 98.755 130.645 ; + RECT 98.125 130.475 98.295 130.645 ; + RECT 97.665 130.475 97.835 130.645 ; + RECT 97.205 130.475 97.375 130.645 ; + RECT 96.745 130.475 96.915 130.645 ; + RECT 96.285 130.475 96.455 130.645 ; + RECT 95.825 130.475 95.995 130.645 ; + RECT 95.365 130.475 95.535 130.645 ; + RECT 94.905 130.475 95.075 130.645 ; + RECT 94.445 130.475 94.615 130.645 ; + RECT 93.985 130.475 94.155 130.645 ; + RECT 93.525 130.475 93.695 130.645 ; + RECT 93.065 130.475 93.235 130.645 ; + RECT 92.605 130.475 92.775 130.645 ; + RECT 92.145 130.475 92.315 130.645 ; + RECT 91.685 130.475 91.855 130.645 ; + RECT 91.225 130.475 91.395 130.645 ; + RECT 90.765 130.475 90.935 130.645 ; + RECT 90.305 130.475 90.475 130.645 ; + RECT 89.845 130.475 90.015 130.645 ; + RECT 89.385 130.475 89.555 130.645 ; + RECT 88.925 130.475 89.095 130.645 ; + RECT 88.465 130.475 88.635 130.645 ; + RECT 88.005 130.475 88.175 130.645 ; + RECT 87.545 130.475 87.715 130.645 ; + RECT 87.085 130.475 87.255 130.645 ; + RECT 86.625 130.475 86.795 130.645 ; + RECT 86.165 130.475 86.335 130.645 ; + RECT 85.705 130.475 85.875 130.645 ; + RECT 85.245 130.475 85.415 130.645 ; + RECT 84.785 130.475 84.955 130.645 ; + RECT 84.325 130.475 84.495 130.645 ; + RECT 83.865 130.475 84.035 130.645 ; + RECT 83.405 130.475 83.575 130.645 ; + RECT 82.945 130.475 83.115 130.645 ; + RECT 82.485 130.475 82.655 130.645 ; + RECT 82.025 130.475 82.195 130.645 ; + RECT 81.565 130.475 81.735 130.645 ; + RECT 81.105 130.475 81.275 130.645 ; + RECT 80.645 130.475 80.815 130.645 ; + RECT 80.185 130.475 80.355 130.645 ; + RECT 79.725 130.475 79.895 130.645 ; + RECT 79.265 130.475 79.435 130.645 ; + RECT 78.805 130.475 78.975 130.645 ; + RECT 78.345 130.475 78.515 130.645 ; + RECT 77.885 130.475 78.055 130.645 ; + RECT 77.425 130.475 77.595 130.645 ; + RECT 76.965 130.475 77.135 130.645 ; + RECT 76.505 130.475 76.675 130.645 ; + RECT 76.045 130.475 76.215 130.645 ; + RECT 75.585 130.475 75.755 130.645 ; + RECT 75.125 130.475 75.295 130.645 ; + RECT 74.665 130.475 74.835 130.645 ; + RECT 74.205 130.475 74.375 130.645 ; + RECT 73.745 130.475 73.915 130.645 ; + RECT 73.285 130.475 73.455 130.645 ; + RECT 72.825 130.475 72.995 130.645 ; + RECT 72.365 130.475 72.535 130.645 ; + RECT 71.905 130.475 72.075 130.645 ; + RECT 71.445 130.475 71.615 130.645 ; + RECT 70.985 130.475 71.155 130.645 ; + RECT 70.525 130.475 70.695 130.645 ; + RECT 70.065 130.475 70.235 130.645 ; + RECT 69.605 130.475 69.775 130.645 ; + RECT 69.145 130.475 69.315 130.645 ; + RECT 68.685 130.475 68.855 130.645 ; + RECT 68.225 130.475 68.395 130.645 ; + RECT 67.765 130.475 67.935 130.645 ; + RECT 67.305 130.475 67.475 130.645 ; + RECT 66.845 130.475 67.015 130.645 ; + RECT 66.385 130.475 66.555 130.645 ; + RECT 65.925 130.475 66.095 130.645 ; + RECT 65.465 130.475 65.635 130.645 ; + RECT 65.005 130.475 65.175 130.645 ; + RECT 64.545 130.475 64.715 130.645 ; + RECT 64.085 130.475 64.255 130.645 ; + RECT 63.625 130.475 63.795 130.645 ; + RECT 63.165 130.475 63.335 130.645 ; + RECT 62.705 130.475 62.875 130.645 ; + RECT 62.245 130.475 62.415 130.645 ; + RECT 61.785 130.475 61.955 130.645 ; + RECT 61.325 130.475 61.495 130.645 ; + RECT 60.865 130.475 61.035 130.645 ; + RECT 60.405 130.475 60.575 130.645 ; + RECT 59.945 130.475 60.115 130.645 ; + RECT 59.485 130.475 59.655 130.645 ; + RECT 59.025 130.475 59.195 130.645 ; + RECT 58.565 130.475 58.735 130.645 ; + RECT 58.105 130.475 58.275 130.645 ; + RECT 57.645 130.475 57.815 130.645 ; + RECT 57.185 130.475 57.355 130.645 ; + RECT 56.725 130.475 56.895 130.645 ; + RECT 56.265 130.475 56.435 130.645 ; + RECT 55.805 130.475 55.975 130.645 ; + RECT 55.345 130.475 55.515 130.645 ; + RECT 54.885 130.475 55.055 130.645 ; + RECT 54.425 130.475 54.595 130.645 ; + RECT 53.965 130.475 54.135 130.645 ; + RECT 53.505 130.475 53.675 130.645 ; + RECT 53.045 130.475 53.215 130.645 ; + RECT 52.585 130.475 52.755 130.645 ; + RECT 52.125 130.475 52.295 130.645 ; + RECT 51.665 130.475 51.835 130.645 ; + RECT 51.205 130.475 51.375 130.645 ; + RECT 50.745 130.475 50.915 130.645 ; + RECT 50.285 130.475 50.455 130.645 ; + RECT 49.825 130.475 49.995 130.645 ; + RECT 49.365 130.475 49.535 130.645 ; + RECT 48.905 130.475 49.075 130.645 ; + RECT 48.445 130.475 48.615 130.645 ; + RECT 47.985 130.475 48.155 130.645 ; + RECT 47.525 130.475 47.695 130.645 ; + RECT 47.065 130.475 47.235 130.645 ; + RECT 46.605 130.475 46.775 130.645 ; + RECT 46.145 130.475 46.315 130.645 ; + RECT 45.685 130.475 45.855 130.645 ; + RECT 45.225 130.475 45.395 130.645 ; + RECT 44.765 130.475 44.935 130.645 ; + RECT 44.305 130.475 44.475 130.645 ; + RECT 43.845 130.475 44.015 130.645 ; + RECT 43.385 130.475 43.555 130.645 ; + RECT 42.925 130.475 43.095 130.645 ; + RECT 42.465 130.475 42.635 130.645 ; + RECT 42.005 130.475 42.175 130.645 ; + RECT 41.545 130.475 41.715 130.645 ; + RECT 41.085 130.475 41.255 130.645 ; + RECT 40.625 130.475 40.795 130.645 ; + RECT 40.165 130.475 40.335 130.645 ; + RECT 39.705 130.475 39.875 130.645 ; + RECT 39.245 130.475 39.415 130.645 ; + RECT 38.785 130.475 38.955 130.645 ; + RECT 38.325 130.475 38.495 130.645 ; + RECT 37.865 130.475 38.035 130.645 ; + RECT 37.405 130.475 37.575 130.645 ; + RECT 36.945 130.475 37.115 130.645 ; + RECT 36.485 130.475 36.655 130.645 ; + RECT 36.025 130.475 36.195 130.645 ; + RECT 35.565 130.475 35.735 130.645 ; + RECT 35.105 130.475 35.275 130.645 ; + RECT 34.645 130.475 34.815 130.645 ; + RECT 34.185 130.475 34.355 130.645 ; + RECT 33.725 130.475 33.895 130.645 ; + RECT 33.265 130.475 33.435 130.645 ; + RECT 32.805 130.475 32.975 130.645 ; + RECT 32.345 130.475 32.515 130.645 ; + RECT 31.885 130.475 32.055 130.645 ; + RECT 31.425 130.475 31.595 130.645 ; + RECT 30.965 130.475 31.135 130.645 ; + RECT 30.505 130.475 30.675 130.645 ; + RECT 30.045 130.475 30.215 130.645 ; + RECT 29.585 130.475 29.755 130.645 ; + RECT 29.125 130.475 29.295 130.645 ; + RECT 28.665 130.475 28.835 130.645 ; + RECT 112.845 127.755 113.015 127.925 ; + RECT 112.385 127.755 112.555 127.925 ; + RECT 29.125 127.755 29.295 127.925 ; + RECT 28.665 127.755 28.835 127.925 ; + RECT 112.845 125.035 113.015 125.205 ; + RECT 112.385 125.035 112.555 125.205 ; + RECT 29.125 125.035 29.295 125.205 ; + RECT 28.665 125.035 28.835 125.205 ; + RECT 112.845 122.315 113.015 122.485 ; + RECT 112.385 122.315 112.555 122.485 ; + RECT 29.125 122.315 29.295 122.485 ; + RECT 28.665 122.315 28.835 122.485 ; + RECT 112.845 119.595 113.015 119.765 ; + RECT 112.385 119.595 112.555 119.765 ; + RECT 29.125 119.595 29.295 119.765 ; + RECT 28.665 119.595 28.835 119.765 ; + RECT 112.845 116.875 113.015 117.045 ; + RECT 112.385 116.875 112.555 117.045 ; + RECT 29.125 116.875 29.295 117.045 ; + RECT 28.665 116.875 28.835 117.045 ; + RECT 112.845 114.155 113.015 114.325 ; + RECT 112.385 114.155 112.555 114.325 ; + RECT 29.125 114.155 29.295 114.325 ; + RECT 28.665 114.155 28.835 114.325 ; + RECT 112.845 111.435 113.015 111.605 ; + RECT 112.385 111.435 112.555 111.605 ; + RECT 29.125 111.435 29.295 111.605 ; + RECT 28.665 111.435 28.835 111.605 ; + RECT 112.845 108.715 113.015 108.885 ; + RECT 112.385 108.715 112.555 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 112.845 105.995 113.015 106.165 ; + RECT 112.385 105.995 112.555 106.165 ; + RECT 29.125 105.995 29.295 106.165 ; + RECT 28.665 105.995 28.835 106.165 ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 29.125 24.395 29.295 24.565 ; + RECT 28.665 24.395 28.835 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 29.125 21.675 29.295 21.845 ; + RECT 28.665 21.675 28.835 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 29.125 18.955 29.295 19.125 ; + RECT 28.665 18.955 28.835 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 29.125 16.235 29.295 16.405 ; + RECT 28.665 16.235 28.835 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 29.125 13.515 29.295 13.685 ; + RECT 28.665 13.515 28.835 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 29.125 8.075 29.295 8.245 ; + RECT 28.665 8.075 28.835 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 29.125 5.355 29.295 5.525 ; + RECT 28.665 5.355 28.835 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 29.125 2.635 29.295 2.805 ; + RECT 28.665 2.635 28.835 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + LAYER via ; + RECT 85.485 130.485 85.635 130.635 ; + RECT 56.045 130.485 56.195 130.635 ; + RECT 97.445 128.785 97.595 128.935 ; + RECT 79.505 128.785 79.655 128.935 ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 6.365 103.285 6.515 103.435 ; + RECT 85.485 27.125 85.635 27.275 ; + RECT 56.045 27.125 56.195 27.275 ; + RECT 6.365 27.125 6.515 27.275 ; + RECT 97.445 1.625 97.595 1.775 ; + RECT 74.905 1.625 75.055 1.775 ; + RECT 70.765 1.625 70.915 1.775 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + LAYER via2 ; + RECT 85.46 130.46 85.66 130.66 ; + RECT 56.02 130.46 56.22 130.66 ; + RECT 30.26 118.9 30.46 119.1 ; + RECT 29.8 117.54 30 117.74 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.28 96.46 1.48 96.66 ; + RECT 1.28 70.62 1.48 70.82 ; + RECT 1.28 64.5 1.48 64.7 ; + RECT 1.28 51.58 1.48 51.78 ; + RECT 1.28 46.14 1.48 46.34 ; + RECT 1.28 40.7 1.48 40.9 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 29.8 12.82 30 13.02 ; + RECT 29.8 4.66 30 4.86 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via3 ; + RECT 85.46 130.46 85.66 130.66 ; + RECT 56.02 130.46 56.22 130.66 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 30.26 14.18 30.46 14.38 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via4 ; + RECT 6.04 65.68 6.84 66.48 ; + RECT 6.04 64.08 6.84 64.88 ; + LAYER fieldpoly ; + POLYGON 113.02 130.42 113.02 0.14 28.66 0.14 28.66 27.34 0.14 27.34 0.14 103.22 28.66 103.22 28.66 130.42 ; + LAYER diff ; + POLYGON 113.16 130.56 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER nwell ; + POLYGON 113.35 129.255 113.35 126.425 112.05 126.425 112.05 127.65 109.29 127.65 109.29 129.255 ; + POLYGON 32.39 129.255 32.39 127.65 30.55 127.65 30.55 126.425 28.33 126.425 28.33 129.255 ; + POLYGON 113.35 123.815 113.35 120.985 109.29 120.985 109.29 122.59 111.13 122.59 111.13 123.815 ; + POLYGON 32.39 123.815 32.39 122.21 30.55 122.21 30.55 120.985 28.33 120.985 28.33 123.815 ; + POLYGON 113.35 118.375 113.35 115.545 112.51 115.545 112.51 116.77 112.05 116.77 112.05 118.375 ; + POLYGON 32.39 118.375 32.39 116.77 30.55 116.77 30.55 115.545 28.33 115.545 28.33 118.375 ; + RECT 112.51 110.105 113.35 112.935 ; + POLYGON 32.39 112.935 32.39 111.33 30.55 111.33 30.55 110.105 28.33 110.105 28.33 112.935 ; + POLYGON 113.35 107.495 113.35 104.665 109.29 104.665 109.29 106.27 112.05 106.27 112.05 107.495 ; + POLYGON 32.39 107.495 32.39 105.89 30.55 105.89 30.55 104.665 28.33 104.665 28.33 107.495 ; + POLYGON 113.35 102.055 113.35 99.225 109.29 99.225 109.29 100.83 112.05 100.83 112.05 102.055 ; + POLYGON 3.87 102.055 3.87 100.45 2.03 100.45 2.03 99.225 -0.19 99.225 -0.19 102.055 ; + POLYGON 113.35 96.615 113.35 93.785 112.05 93.785 112.05 95.01 111.13 95.01 111.13 96.615 ; + RECT -0.19 93.785 2.03 96.615 ; + RECT 109.29 88.345 113.35 91.175 ; + RECT -0.19 88.345 2.03 91.175 ; + POLYGON 113.35 85.735 113.35 82.905 111.13 82.905 111.13 84.51 112.51 84.51 112.51 85.735 ; + POLYGON 2.03 85.735 2.03 84.51 3.87 84.51 3.87 82.905 -0.19 82.905 -0.19 85.735 ; + RECT 112.05 77.465 113.35 80.295 ; + POLYGON 3.87 80.295 3.87 78.69 2.03 78.69 2.03 77.465 -0.19 77.465 -0.19 80.295 ; + RECT 112.51 72.025 113.35 74.855 ; + POLYGON 3.87 74.855 3.87 73.25 2.03 73.25 2.03 72.025 -0.19 72.025 -0.19 74.855 ; + POLYGON 113.35 69.415 113.35 66.585 109.29 66.585 109.29 68.19 112.51 68.19 112.51 69.415 ; + POLYGON 3.87 69.415 3.87 67.81 2.03 67.81 2.03 66.585 -0.19 66.585 -0.19 69.415 ; + POLYGON 113.35 63.975 113.35 61.145 112.05 61.145 112.05 62.75 112.51 62.75 112.51 63.975 ; + POLYGON 2.03 63.975 2.03 62.75 3.87 62.75 3.87 61.145 -0.19 61.145 -0.19 63.975 ; + RECT 109.29 55.705 113.35 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + RECT 112.51 50.265 113.35 53.095 ; + POLYGON 2.03 53.095 2.03 51.87 3.87 51.87 3.87 50.265 -0.19 50.265 -0.19 53.095 ; + RECT 112.05 44.825 113.35 47.655 ; + POLYGON 2.03 47.655 2.03 46.43 3.87 46.43 3.87 44.825 -0.19 44.825 -0.19 47.655 ; + POLYGON 113.35 42.215 113.35 39.385 112.51 39.385 112.51 40.61 109.29 40.61 109.29 42.215 ; + RECT -0.19 39.385 2.03 42.215 ; + POLYGON 113.35 36.775 113.35 33.945 112.51 33.945 112.51 35.17 111.13 35.17 111.13 36.775 ; + RECT -0.19 33.945 2.03 36.775 ; + POLYGON 113.35 31.335 113.35 28.505 111.13 28.505 111.13 30.11 112.05 30.11 112.05 31.335 ; + RECT -0.19 28.505 3.87 31.335 ; + POLYGON 113.35 25.895 113.35 23.065 112.51 23.065 112.51 24.29 112.05 24.29 112.05 25.895 ; + POLYGON 30.55 25.895 30.55 24.67 32.39 24.67 32.39 23.065 28.33 23.065 28.33 25.895 ; + POLYGON 113.35 20.455 113.35 17.625 112.51 17.625 112.51 18.85 112.05 18.85 112.05 20.455 ; + POLYGON 30.55 20.455 30.55 19.23 32.39 19.23 32.39 17.625 28.33 17.625 28.33 20.455 ; + RECT 112.51 12.185 113.35 15.015 ; + POLYGON 30.55 15.015 30.55 13.79 32.39 13.79 32.39 12.185 28.33 12.185 28.33 15.015 ; + RECT 112.51 6.745 113.35 9.575 ; + POLYGON 30.55 9.575 30.55 8.35 32.39 8.35 32.39 6.745 28.33 6.745 28.33 9.575 ; + POLYGON 113.35 4.135 113.35 1.305 109.29 1.305 109.29 2.91 112.51 2.91 112.51 4.135 ; + POLYGON 30.55 4.135 30.55 2.91 32.39 2.91 32.39 1.305 28.33 1.305 28.33 4.135 ; + POLYGON 113.16 130.56 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER pwell ; + RECT 109.61 130.51 109.83 130.68 ; + RECT 105.93 130.51 106.15 130.68 ; + RECT 102.25 130.51 102.47 130.68 ; + RECT 98.57 130.51 98.79 130.68 ; + RECT 94.89 130.51 95.11 130.68 ; + RECT 91.21 130.51 91.43 130.68 ; + RECT 87.53 130.51 87.75 130.68 ; + RECT 83.85 130.51 84.07 130.68 ; + RECT 80.17 130.51 80.39 130.68 ; + RECT 76.49 130.51 76.71 130.68 ; + RECT 72.81 130.51 73.03 130.68 ; + RECT 69.13 130.51 69.35 130.68 ; + RECT 65.45 130.51 65.67 130.68 ; + RECT 61.77 130.51 61.99 130.68 ; + RECT 58.09 130.51 58.31 130.68 ; + RECT 54.41 130.51 54.63 130.68 ; + RECT 50.73 130.51 50.95 130.68 ; + RECT 47.05 130.51 47.27 130.68 ; + RECT 43.37 130.51 43.59 130.68 ; + RECT 39.69 130.51 39.91 130.68 ; + RECT 36.01 130.51 36.23 130.68 ; + RECT 32.33 130.51 32.55 130.68 ; + RECT 28.65 130.51 28.87 130.68 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 25.89 27.08 26.11 27.25 ; + RECT 22.21 27.08 22.43 27.25 ; + RECT 18.53 27.08 18.75 27.25 ; + RECT 14.85 27.08 15.07 27.25 ; + RECT 11.17 27.08 11.39 27.25 ; + RECT 7.49 27.08 7.71 27.25 ; + RECT 3.81 27.08 4.03 27.25 ; + RECT 0.13 27.08 0.35 27.25 ; + RECT 109.61 -0.12 109.83 0.05 ; + RECT 105.93 -0.12 106.15 0.05 ; + RECT 102.25 -0.12 102.47 0.05 ; + RECT 98.57 -0.12 98.79 0.05 ; + RECT 94.89 -0.12 95.11 0.05 ; + RECT 91.21 -0.12 91.43 0.05 ; + RECT 87.53 -0.12 87.75 0.05 ; + RECT 83.85 -0.12 84.07 0.05 ; + RECT 80.17 -0.12 80.39 0.05 ; + RECT 76.49 -0.12 76.71 0.05 ; + RECT 72.81 -0.12 73.03 0.05 ; + RECT 69.13 -0.12 69.35 0.05 ; + RECT 65.45 -0.12 65.67 0.05 ; + RECT 61.77 -0.12 61.99 0.05 ; + RECT 58.09 -0.12 58.31 0.05 ; + RECT 54.41 -0.12 54.63 0.05 ; + RECT 50.73 -0.12 50.95 0.05 ; + RECT 47.05 -0.12 47.27 0.05 ; + RECT 43.37 -0.12 43.59 0.05 ; + RECT 39.69 -0.12 39.91 0.05 ; + RECT 36.01 -0.12 36.23 0.05 ; + RECT 32.33 -0.12 32.55 0.05 ; + RECT 28.65 -0.12 28.87 0.05 ; + POLYGON 113.16 130.56 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 ; + LAYER OVERLAP ; + POLYGON 28.52 0 28.52 27.2 0 27.2 0 103.36 28.52 103.36 28.52 130.56 113.16 130.56 113.16 0 ; + END +END sb_2__1_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef new file mode 100644 index 0000000..32ade24 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -0,0 +1,2313 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER fieldpoly + TYPE MASTERSLICE ; +END fieldpoly + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER diff + TYPE MASTERSLICE ; +END diff + +LAYER licon1 + TYPE MASTERSLICE ; +END licon1 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 113.16 BY 103.36 ; + SYMMETRY X Y ; + PIN prog_clk[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 30.75 0 30.89 1.36 ; + END + END prog_clk[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.27 0 82.41 1.36 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.09 0 67.23 1.36 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.35 0 81.49 1.36 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.25 0 88.39 1.36 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.25 0 65.39 1.36 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.83 0 75.97 1.36 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.23 0 94.37 1.36 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.33 0 87.47 1.36 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.67 0 77.81 1.36 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.11 0 84.25 1.36 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.49 0 62.63 1.36 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.41 0 86.55 1.36 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.51 0 79.65 1.36 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.01 0 68.15 1.36 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.17 0 66.31 1.36 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.29 0 53.43 1.36 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.75 0 76.89 1.36 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.85 0 69.99 1.36 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.59 0 78.73 1.36 ; + END + END chany_bottom_in[19] + PIN bottom_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 110.79 0 110.93 1.36 ; + END + END bottom_right_grid_pin_1_[0] + PIN bottom_left_grid_pin_34_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 10.05 29.9 10.35 ; + END + END bottom_left_grid_pin_34_[0] + PIN bottom_left_grid_pin_35_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 8.01 29.9 8.31 ; + END + END bottom_left_grid_pin_35_[0] + PIN bottom_left_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 6.65 29.9 6.95 ; + END + END bottom_left_grid_pin_36_[0] + PIN bottom_left_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 3.25 29.9 3.55 ; + END + END bottom_left_grid_pin_37_[0] + PIN bottom_left_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 4.61 29.9 4.91 ; + END + END bottom_left_grid_pin_38_[0] + PIN bottom_left_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 11.41 29.9 11.71 ; + END + END bottom_left_grid_pin_39_[0] + PIN bottom_left_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 12.77 29.9 13.07 ; + END + END bottom_left_grid_pin_40_[0] + PIN bottom_left_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 28.52 14.13 29.9 14.43 ; + END + END bottom_left_grid_pin_41_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.01 1.38 42.31 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.85 1.38 68.15 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 61.05 1.38 61.35 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.17 1.38 50.47 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.13 1.38 31.43 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 76.01 1.38 76.31 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 99.13 1.38 99.43 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 63.77 1.38 64.07 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.49 1.38 32.79 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 74.65 1.38 74.95 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 59.69 1.38 59.99 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 96.41 1.38 96.71 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.61 1.38 55.91 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END chanx_left_in[19] + PIN left_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 102 2.37 103.36 ; + END + END left_top_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.79 102 18.93 103.36 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.19 0 83.33 1.36 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.73 0 59.87 1.36 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.37 0 52.51 1.36 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.93 0 69.07 1.36 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.53 0 96.67 1.36 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.69 0 71.83 1.36 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.91 0 75.05 1.36 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.65 0 60.79 1.36 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.41 0 63.55 1.36 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.21 0 54.35 1.36 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.31 0 93.45 1.36 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.99 0 74.13 1.36 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.43 0 80.57 1.36 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.57 0 61.71 1.36 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.45 0 97.59 1.36 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.13 0 55.27 1.36 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.33 0 64.47 1.36 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.81 0 58.95 1.36 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.07 0 73.21 1.36 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.77 0 70.91 1.36 ; + END + END chany_bottom_out[19] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 80.09 1.38 80.39 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 93.69 1.38 93.99 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 58.33 1.38 58.63 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 70.57 1.38 70.87 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.37 1.38 43.67 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 85.53 1.38 85.83 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 65.13 1.38 65.43 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 97.77 1.38 98.07 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 92.33 1.38 92.63 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 82.81 1.38 83.11 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 86.89 1.38 87.19 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 69.21 1.38 69.51 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.73 1.38 45.03 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.25 1.38 54.55 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 90.97 1.38 91.27 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 88.25 1.38 88.55 ; + END + END chanx_left_out[19] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 77.37 1.38 77.67 ; + END + END ccff_tail[0] + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met1 ; + RECT 28.52 2.48 29 2.96 ; + RECT 112.68 2.48 113.16 2.96 ; + RECT 28.52 7.92 29 8.4 ; + RECT 112.68 7.92 113.16 8.4 ; + RECT 28.52 13.36 29 13.84 ; + RECT 112.68 13.36 113.16 13.84 ; + RECT 28.52 18.8 29 19.28 ; + RECT 112.68 18.8 113.16 19.28 ; + RECT 28.52 24.24 29 24.72 ; + RECT 112.68 24.24 113.16 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 112.68 29.68 113.16 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 112.68 35.12 113.16 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 112.68 40.56 113.16 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 112.68 46 113.16 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 112.68 51.44 113.16 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 112.68 56.88 113.16 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 112.68 62.32 113.16 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 112.68 67.76 113.16 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 112.68 73.2 113.16 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 112.68 78.64 113.16 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 112.68 84.08 113.16 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 112.68 89.52 113.16 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 112.68 94.96 113.16 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 112.68 100.4 113.16 100.88 ; + LAYER met4 ; + RECT 41.1 0 41.7 0.6 ; + RECT 70.54 0 71.14 0.6 ; + RECT 99.98 0 100.58 0.6 ; + RECT 41.1 102.76 41.7 103.36 ; + RECT 70.54 102.76 71.14 103.36 ; + RECT 99.98 102.76 100.58 103.36 ; + LAYER met5 ; + RECT 0 43.28 3.2 46.48 ; + RECT 109.96 43.28 113.16 46.48 ; + RECT 0 84.08 3.2 87.28 ; + RECT 109.96 84.08 113.16 87.28 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met1 ; + RECT 28.52 0 113.16 0.24 ; + RECT 28.52 5.2 29 5.68 ; + RECT 112.68 5.2 113.16 5.68 ; + RECT 28.52 10.64 29 11.12 ; + RECT 112.68 10.64 113.16 11.12 ; + RECT 28.52 16.08 29 16.56 ; + RECT 112.68 16.08 113.16 16.56 ; + RECT 28.52 21.52 29 22 ; + RECT 112.68 21.52 113.16 22 ; + RECT 0 26.96 113.16 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 112.68 32.4 113.16 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 112.68 37.84 113.16 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 112.68 43.28 113.16 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 112.68 48.72 113.16 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 112.68 54.16 113.16 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 112.68 59.6 113.16 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 112.68 65.04 113.16 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 112.68 70.48 113.16 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 112.68 75.92 113.16 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 112.68 81.36 113.16 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 112.68 86.8 113.16 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 112.68 92.24 113.16 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 112.68 97.68 113.16 98.16 ; + RECT 0 103.12 113.16 103.36 ; + LAYER met5 ; + RECT 28.52 4.52 31.72 7.72 ; + RECT 109.96 4.52 113.16 7.72 ; + RECT 0 63.68 3.2 66.88 ; + RECT 109.96 63.68 113.16 66.88 ; + LAYER met4 ; + RECT 55.82 0 56.42 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 6.14 27.2 6.74 27.8 ; + RECT 6.14 102.76 6.74 103.36 ; + RECT 55.82 102.76 56.42 103.36 ; + RECT 85.26 102.76 85.86 103.36 ; + END + END VSS + OBS + LAYER li1 ; + RECT 0 103.275 113.16 103.445 ; + RECT 111.32 100.555 113.16 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 111.32 97.835 113.16 98.005 ; + RECT 0 97.835 1.84 98.005 ; + RECT 111.32 95.115 113.16 95.285 ; + RECT 0 95.115 1.84 95.285 ; + RECT 112.24 92.395 113.16 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 111.32 89.675 113.16 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 111.32 86.955 113.16 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 112.24 84.235 113.16 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 112.24 81.515 113.16 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 112.24 78.795 113.16 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 112.24 76.075 113.16 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 112.24 73.355 113.16 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 109.48 70.635 113.16 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 109.48 67.915 113.16 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 112.24 65.195 113.16 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 112.7 62.475 113.16 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 111.32 59.755 113.16 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 111.32 57.035 113.16 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 112.24 54.315 113.16 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 109.48 51.595 113.16 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 109.48 48.875 113.16 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 112.24 46.155 113.16 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 112.24 43.435 113.16 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 112.7 40.715 113.16 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 112.7 37.995 113.16 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 112.7 35.275 113.16 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 112.7 32.555 113.16 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 112.7 29.835 113.16 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 112.24 27.115 113.16 27.285 ; + RECT 0 27.115 30.36 27.285 ; + RECT 112.24 24.395 113.16 24.565 ; + RECT 28.52 24.395 32.2 24.565 ; + RECT 112.24 21.675 113.16 21.845 ; + RECT 28.52 21.675 32.2 21.845 ; + RECT 112.7 18.955 113.16 19.125 ; + RECT 28.52 18.955 32.2 19.125 ; + RECT 112.24 16.235 113.16 16.405 ; + RECT 28.52 16.235 32.2 16.405 ; + RECT 112.24 13.515 113.16 13.685 ; + RECT 28.52 13.515 32.2 13.685 ; + RECT 112.7 10.795 113.16 10.965 ; + RECT 28.52 10.795 32.2 10.965 ; + RECT 112.24 8.075 113.16 8.245 ; + RECT 28.52 8.075 32.2 8.245 ; + RECT 112.24 5.355 113.16 5.525 ; + RECT 28.52 5.355 32.2 5.525 ; + RECT 109.48 2.635 113.16 2.805 ; + RECT 28.52 2.635 32.2 2.805 ; + RECT 28.52 -0.085 113.16 0.085 ; + LAYER met2 ; + RECT 85.42 103.175 85.7 103.545 ; + RECT 55.98 103.175 56.26 103.545 ; + RECT 6.3 103.175 6.58 103.545 ; + RECT 6.3 27.015 6.58 27.385 ; + RECT 85.42 -0.185 85.7 0.185 ; + RECT 55.98 -0.185 56.26 0.185 ; + POLYGON 112.88 103.08 112.88 0.28 111.21 0.28 111.21 1.64 110.51 1.64 110.51 0.28 97.87 0.28 97.87 1.64 97.17 1.64 97.17 0.28 96.95 0.28 96.95 1.64 96.25 1.64 96.25 0.28 94.65 0.28 94.65 1.64 93.95 1.64 93.95 0.28 93.73 0.28 93.73 1.64 93.03 1.64 93.03 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 86.83 0.28 86.83 1.64 86.13 1.64 86.13 0.28 84.53 0.28 84.53 1.64 83.83 1.64 83.83 0.28 83.61 0.28 83.61 1.64 82.91 1.64 82.91 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 76.25 0.28 76.25 1.64 75.55 1.64 75.55 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 28.8 0.28 28.8 27.48 0.28 27.48 0.28 103.08 1.95 103.08 1.95 101.72 2.65 101.72 2.65 103.08 18.51 103.08 18.51 101.72 19.21 101.72 19.21 103.08 ; + LAYER met3 ; + POLYGON 85.725 103.525 85.725 103.52 85.94 103.52 85.94 103.2 85.725 103.2 85.725 103.195 85.395 103.195 85.395 103.2 85.18 103.2 85.18 103.52 85.395 103.52 85.395 103.525 ; + POLYGON 56.285 103.525 56.285 103.52 56.5 103.52 56.5 103.2 56.285 103.2 56.285 103.195 55.955 103.195 55.955 103.2 55.74 103.2 55.74 103.52 55.955 103.52 55.955 103.525 ; + POLYGON 6.605 103.525 6.605 103.52 6.82 103.52 6.82 103.2 6.605 103.2 6.605 103.195 6.275 103.195 6.275 103.2 6.06 103.2 6.06 103.52 6.275 103.52 6.275 103.525 ; + POLYGON 11.65 98.75 11.65 98.45 1.99 98.45 1.99 97.77 1.78 97.77 1.78 98.47 1.69 98.47 1.69 98.75 ; + POLYGON 2.03 72.92 2.03 72.91 11.65 72.91 11.65 72.61 2.03 72.61 2.03 72.6 1.65 72.6 1.65 72.92 ; + POLYGON 32.35 71.55 32.35 71.25 1.23 71.25 1.23 71.53 1.78 71.53 1.78 71.55 ; + POLYGON 10.73 60.67 10.73 60.37 1.78 60.37 1.78 60.39 1.23 60.39 1.23 60.67 ; + POLYGON 1.99 45.03 1.99 44.35 6.13 44.35 6.13 44.05 1.69 44.05 1.69 44.33 1.78 44.33 1.78 45.03 ; + POLYGON 64.55 38.91 64.55 38.61 1.23 38.61 1.23 38.89 1.78 38.89 1.78 38.91 ; + POLYGON 6.605 27.365 6.605 27.36 6.82 27.36 6.82 27.04 6.605 27.04 6.605 27.035 6.275 27.035 6.275 27.04 6.06 27.04 6.06 27.36 6.275 27.36 6.275 27.365 ; + POLYGON 85.725 0.165 85.725 0.16 85.94 0.16 85.94 -0.16 85.725 -0.16 85.725 -0.165 85.395 -0.165 85.395 -0.16 85.18 -0.16 85.18 0.16 85.395 0.16 85.395 0.165 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 112.76 102.96 112.76 0.4 28.92 0.4 28.92 2.85 30.3 2.85 30.3 3.95 28.92 3.95 28.92 4.21 30.3 4.21 30.3 5.31 28.92 5.31 28.92 6.25 30.3 6.25 30.3 7.35 28.92 7.35 28.92 7.61 30.3 7.61 30.3 8.71 28.92 8.71 28.92 9.65 30.3 9.65 30.3 10.75 28.92 10.75 28.92 11.01 30.3 11.01 30.3 12.11 28.92 12.11 28.92 12.37 30.3 12.37 30.3 13.47 28.92 13.47 28.92 13.73 30.3 13.73 30.3 14.83 28.92 14.83 28.92 27.6 0.4 27.6 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 93.29 1.78 93.29 1.78 94.39 0.4 94.39 0.4 96.01 1.78 96.01 1.78 97.11 0.4 97.11 0.4 97.37 1.78 97.37 1.78 98.47 0.4 98.47 0.4 98.73 1.78 98.73 1.78 99.83 0.4 99.83 0.4 102.96 ; + LAYER met5 ; + POLYGON 109.96 100.16 109.96 90.48 106.76 90.48 106.76 80.88 109.96 80.88 109.96 70.08 106.76 70.08 106.76 60.48 109.96 60.48 109.96 49.68 106.76 49.68 106.76 40.08 109.96 40.08 109.96 10.92 106.76 10.92 106.76 3.2 34.92 3.2 34.92 10.92 31.72 10.92 31.72 30.4 3.2 30.4 3.2 40.08 6.4 40.08 6.4 49.68 3.2 49.68 3.2 60.48 6.4 60.48 6.4 70.08 3.2 70.08 3.2 80.88 6.4 80.88 6.4 90.48 3.2 90.48 3.2 100.16 ; + LAYER met4 ; + POLYGON 112.76 102.96 112.76 0.4 100.98 0.4 100.98 1 99.58 1 99.58 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 71.54 0.4 71.54 1 70.14 1 70.14 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 28.92 0.4 28.92 27.6 7.14 27.6 7.14 28.2 5.74 28.2 5.74 27.6 0.4 27.6 0.4 102.96 5.74 102.96 5.74 102.36 7.14 102.36 7.14 102.96 40.7 102.96 40.7 102.36 42.1 102.36 42.1 102.96 55.42 102.96 55.42 102.36 56.82 102.36 56.82 102.96 70.14 102.96 70.14 102.36 71.54 102.36 71.54 102.96 84.86 102.96 84.86 102.36 86.26 102.36 86.26 102.96 99.58 102.96 99.58 102.36 100.98 102.36 100.98 102.96 ; + LAYER met1 ; + POLYGON 112.88 102.84 112.88 101.16 112.4 101.16 112.4 100.12 112.88 100.12 112.88 98.44 112.4 98.44 112.4 97.4 112.88 97.4 112.88 95.72 112.4 95.72 112.4 94.68 112.88 94.68 112.88 93 112.4 93 112.4 91.96 112.88 91.96 112.88 90.28 112.4 90.28 112.4 89.24 112.88 89.24 112.88 87.56 112.4 87.56 112.4 86.52 112.88 86.52 112.88 84.84 112.4 84.84 112.4 83.8 112.88 83.8 112.88 82.12 112.4 82.12 112.4 81.08 112.88 81.08 112.88 79.4 112.4 79.4 112.4 78.36 112.88 78.36 112.88 76.68 112.4 76.68 112.4 75.64 112.88 75.64 112.88 73.96 112.4 73.96 112.4 72.92 112.88 72.92 112.88 71.24 112.4 71.24 112.4 70.2 112.88 70.2 112.88 68.52 112.4 68.52 112.4 67.48 112.88 67.48 112.88 65.8 112.4 65.8 112.4 64.76 112.88 64.76 112.88 63.08 112.4 63.08 112.4 62.04 112.88 62.04 112.88 60.36 112.4 60.36 112.4 59.32 112.88 59.32 112.88 57.64 112.4 57.64 112.4 56.6 112.88 56.6 112.88 54.92 112.4 54.92 112.4 53.88 112.88 53.88 112.88 52.2 112.4 52.2 112.4 51.16 112.88 51.16 112.88 49.48 112.4 49.48 112.4 48.44 112.88 48.44 112.88 46.76 112.4 46.76 112.4 45.72 112.88 45.72 112.88 44.04 112.4 44.04 112.4 43 112.88 43 112.88 41.32 112.4 41.32 112.4 40.28 112.88 40.28 112.88 38.6 112.4 38.6 112.4 37.56 112.88 37.56 112.88 35.88 112.4 35.88 112.4 34.84 112.88 34.84 112.88 33.16 112.4 33.16 112.4 32.12 112.88 32.12 112.88 30.44 112.4 30.44 112.4 29.4 112.88 29.4 112.88 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 ; + POLYGON 112.88 26.68 112.88 25 112.4 25 112.4 23.96 112.88 23.96 112.88 22.28 112.4 22.28 112.4 21.24 112.88 21.24 112.88 19.56 112.4 19.56 112.4 18.52 112.88 18.52 112.88 16.84 112.4 16.84 112.4 15.8 112.88 15.8 112.88 14.12 112.4 14.12 112.4 13.08 112.88 13.08 112.88 11.4 112.4 11.4 112.4 10.36 112.88 10.36 112.88 8.68 112.4 8.68 112.4 7.64 112.88 7.64 112.88 5.96 112.4 5.96 112.4 4.92 112.88 4.92 112.88 3.24 112.4 3.24 112.4 2.2 112.88 2.2 112.88 0.52 28.8 0.52 28.8 2.2 29.28 2.2 29.28 3.24 28.8 3.24 28.8 4.92 29.28 4.92 29.28 5.96 28.8 5.96 28.8 7.64 29.28 7.64 29.28 8.68 28.8 8.68 28.8 10.36 29.28 10.36 29.28 11.4 28.8 11.4 28.8 13.08 29.28 13.08 29.28 14.12 28.8 14.12 28.8 15.8 29.28 15.8 29.28 16.84 28.8 16.84 28.8 18.52 29.28 18.52 29.28 19.56 28.8 19.56 28.8 21.24 29.28 21.24 29.28 22.28 28.8 22.28 28.8 23.96 29.28 23.96 29.28 25 28.8 25 28.8 26.68 ; + LAYER li1 ; + POLYGON 112.82 103.02 112.82 0.34 28.86 0.34 28.86 27.54 0.34 27.54 0.34 103.02 ; + LAYER mcon ; + RECT 112.845 103.275 113.015 103.445 ; + RECT 112.385 103.275 112.555 103.445 ; + RECT 111.925 103.275 112.095 103.445 ; + RECT 111.465 103.275 111.635 103.445 ; + RECT 111.005 103.275 111.175 103.445 ; + RECT 110.545 103.275 110.715 103.445 ; + RECT 110.085 103.275 110.255 103.445 ; + RECT 109.625 103.275 109.795 103.445 ; + RECT 109.165 103.275 109.335 103.445 ; + RECT 108.705 103.275 108.875 103.445 ; + RECT 108.245 103.275 108.415 103.445 ; + RECT 107.785 103.275 107.955 103.445 ; + RECT 107.325 103.275 107.495 103.445 ; + RECT 106.865 103.275 107.035 103.445 ; + RECT 106.405 103.275 106.575 103.445 ; + RECT 105.945 103.275 106.115 103.445 ; + RECT 105.485 103.275 105.655 103.445 ; + RECT 105.025 103.275 105.195 103.445 ; + RECT 104.565 103.275 104.735 103.445 ; + RECT 104.105 103.275 104.275 103.445 ; + RECT 103.645 103.275 103.815 103.445 ; + RECT 103.185 103.275 103.355 103.445 ; + RECT 102.725 103.275 102.895 103.445 ; + RECT 102.265 103.275 102.435 103.445 ; + RECT 101.805 103.275 101.975 103.445 ; + RECT 101.345 103.275 101.515 103.445 ; + RECT 100.885 103.275 101.055 103.445 ; + RECT 100.425 103.275 100.595 103.445 ; + RECT 99.965 103.275 100.135 103.445 ; + RECT 99.505 103.275 99.675 103.445 ; + RECT 99.045 103.275 99.215 103.445 ; + RECT 98.585 103.275 98.755 103.445 ; + RECT 98.125 103.275 98.295 103.445 ; + RECT 97.665 103.275 97.835 103.445 ; + RECT 97.205 103.275 97.375 103.445 ; + RECT 96.745 103.275 96.915 103.445 ; + RECT 96.285 103.275 96.455 103.445 ; + RECT 95.825 103.275 95.995 103.445 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 94.445 103.275 94.615 103.445 ; + RECT 93.985 103.275 94.155 103.445 ; + RECT 93.525 103.275 93.695 103.445 ; + RECT 93.065 103.275 93.235 103.445 ; + RECT 92.605 103.275 92.775 103.445 ; + RECT 92.145 103.275 92.315 103.445 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 90.765 103.275 90.935 103.445 ; + RECT 90.305 103.275 90.475 103.445 ; + RECT 89.845 103.275 90.015 103.445 ; + RECT 89.385 103.275 89.555 103.445 ; + RECT 88.925 103.275 89.095 103.445 ; + RECT 88.465 103.275 88.635 103.445 ; + RECT 88.005 103.275 88.175 103.445 ; + RECT 87.545 103.275 87.715 103.445 ; + RECT 87.085 103.275 87.255 103.445 ; + RECT 86.625 103.275 86.795 103.445 ; + RECT 86.165 103.275 86.335 103.445 ; + RECT 85.705 103.275 85.875 103.445 ; + RECT 85.245 103.275 85.415 103.445 ; + RECT 84.785 103.275 84.955 103.445 ; + RECT 84.325 103.275 84.495 103.445 ; + RECT 83.865 103.275 84.035 103.445 ; + RECT 83.405 103.275 83.575 103.445 ; + RECT 82.945 103.275 83.115 103.445 ; + RECT 82.485 103.275 82.655 103.445 ; + RECT 82.025 103.275 82.195 103.445 ; + RECT 81.565 103.275 81.735 103.445 ; + RECT 81.105 103.275 81.275 103.445 ; + RECT 80.645 103.275 80.815 103.445 ; + RECT 80.185 103.275 80.355 103.445 ; + RECT 79.725 103.275 79.895 103.445 ; + RECT 79.265 103.275 79.435 103.445 ; + RECT 78.805 103.275 78.975 103.445 ; + RECT 78.345 103.275 78.515 103.445 ; + RECT 77.885 103.275 78.055 103.445 ; + RECT 77.425 103.275 77.595 103.445 ; + RECT 76.965 103.275 77.135 103.445 ; + RECT 76.505 103.275 76.675 103.445 ; + RECT 76.045 103.275 76.215 103.445 ; + RECT 75.585 103.275 75.755 103.445 ; + RECT 75.125 103.275 75.295 103.445 ; + RECT 74.665 103.275 74.835 103.445 ; + RECT 74.205 103.275 74.375 103.445 ; + RECT 73.745 103.275 73.915 103.445 ; + RECT 73.285 103.275 73.455 103.445 ; + RECT 72.825 103.275 72.995 103.445 ; + RECT 72.365 103.275 72.535 103.445 ; + RECT 71.905 103.275 72.075 103.445 ; + RECT 71.445 103.275 71.615 103.445 ; + RECT 70.985 103.275 71.155 103.445 ; + RECT 70.525 103.275 70.695 103.445 ; + RECT 70.065 103.275 70.235 103.445 ; + RECT 69.605 103.275 69.775 103.445 ; + RECT 69.145 103.275 69.315 103.445 ; + RECT 68.685 103.275 68.855 103.445 ; + RECT 68.225 103.275 68.395 103.445 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 66.845 103.275 67.015 103.445 ; + RECT 66.385 103.275 66.555 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; + RECT 65.005 103.275 65.175 103.445 ; + RECT 64.545 103.275 64.715 103.445 ; + RECT 64.085 103.275 64.255 103.445 ; + RECT 63.625 103.275 63.795 103.445 ; + RECT 63.165 103.275 63.335 103.445 ; + RECT 62.705 103.275 62.875 103.445 ; + RECT 62.245 103.275 62.415 103.445 ; + RECT 61.785 103.275 61.955 103.445 ; + RECT 61.325 103.275 61.495 103.445 ; + RECT 60.865 103.275 61.035 103.445 ; + RECT 60.405 103.275 60.575 103.445 ; + RECT 59.945 103.275 60.115 103.445 ; + RECT 59.485 103.275 59.655 103.445 ; + RECT 59.025 103.275 59.195 103.445 ; + RECT 58.565 103.275 58.735 103.445 ; + RECT 58.105 103.275 58.275 103.445 ; + RECT 57.645 103.275 57.815 103.445 ; + RECT 57.185 103.275 57.355 103.445 ; + RECT 56.725 103.275 56.895 103.445 ; + RECT 56.265 103.275 56.435 103.445 ; + RECT 55.805 103.275 55.975 103.445 ; + RECT 55.345 103.275 55.515 103.445 ; + RECT 54.885 103.275 55.055 103.445 ; + RECT 54.425 103.275 54.595 103.445 ; + RECT 53.965 103.275 54.135 103.445 ; + RECT 53.505 103.275 53.675 103.445 ; + RECT 53.045 103.275 53.215 103.445 ; + RECT 52.585 103.275 52.755 103.445 ; + RECT 52.125 103.275 52.295 103.445 ; + RECT 51.665 103.275 51.835 103.445 ; + RECT 51.205 103.275 51.375 103.445 ; + RECT 50.745 103.275 50.915 103.445 ; + RECT 50.285 103.275 50.455 103.445 ; + RECT 49.825 103.275 49.995 103.445 ; + RECT 49.365 103.275 49.535 103.445 ; + RECT 48.905 103.275 49.075 103.445 ; + RECT 48.445 103.275 48.615 103.445 ; + RECT 47.985 103.275 48.155 103.445 ; + RECT 47.525 103.275 47.695 103.445 ; + RECT 47.065 103.275 47.235 103.445 ; + RECT 46.605 103.275 46.775 103.445 ; + RECT 46.145 103.275 46.315 103.445 ; + RECT 45.685 103.275 45.855 103.445 ; + RECT 45.225 103.275 45.395 103.445 ; + RECT 44.765 103.275 44.935 103.445 ; + RECT 44.305 103.275 44.475 103.445 ; + RECT 43.845 103.275 44.015 103.445 ; + RECT 43.385 103.275 43.555 103.445 ; + RECT 42.925 103.275 43.095 103.445 ; + RECT 42.465 103.275 42.635 103.445 ; + RECT 42.005 103.275 42.175 103.445 ; + RECT 41.545 103.275 41.715 103.445 ; + RECT 41.085 103.275 41.255 103.445 ; + RECT 40.625 103.275 40.795 103.445 ; + RECT 40.165 103.275 40.335 103.445 ; + RECT 39.705 103.275 39.875 103.445 ; + RECT 39.245 103.275 39.415 103.445 ; + RECT 38.785 103.275 38.955 103.445 ; + RECT 38.325 103.275 38.495 103.445 ; + RECT 37.865 103.275 38.035 103.445 ; + RECT 37.405 103.275 37.575 103.445 ; + RECT 36.945 103.275 37.115 103.445 ; + RECT 36.485 103.275 36.655 103.445 ; + RECT 36.025 103.275 36.195 103.445 ; + RECT 35.565 103.275 35.735 103.445 ; + RECT 35.105 103.275 35.275 103.445 ; + RECT 34.645 103.275 34.815 103.445 ; + RECT 34.185 103.275 34.355 103.445 ; + RECT 33.725 103.275 33.895 103.445 ; + RECT 33.265 103.275 33.435 103.445 ; + RECT 32.805 103.275 32.975 103.445 ; + RECT 32.345 103.275 32.515 103.445 ; + RECT 31.885 103.275 32.055 103.445 ; + RECT 31.425 103.275 31.595 103.445 ; + RECT 30.965 103.275 31.135 103.445 ; + RECT 30.505 103.275 30.675 103.445 ; + RECT 30.045 103.275 30.215 103.445 ; + RECT 29.585 103.275 29.755 103.445 ; + RECT 29.125 103.275 29.295 103.445 ; + RECT 28.665 103.275 28.835 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 27.285 103.275 27.455 103.445 ; + RECT 26.825 103.275 26.995 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 25.445 103.275 25.615 103.445 ; + RECT 24.985 103.275 25.155 103.445 ; + RECT 24.525 103.275 24.695 103.445 ; + RECT 24.065 103.275 24.235 103.445 ; + RECT 23.605 103.275 23.775 103.445 ; + RECT 23.145 103.275 23.315 103.445 ; + RECT 22.685 103.275 22.855 103.445 ; + RECT 22.225 103.275 22.395 103.445 ; + RECT 21.765 103.275 21.935 103.445 ; + RECT 21.305 103.275 21.475 103.445 ; + RECT 20.845 103.275 21.015 103.445 ; + RECT 20.385 103.275 20.555 103.445 ; + RECT 19.925 103.275 20.095 103.445 ; + RECT 19.465 103.275 19.635 103.445 ; + RECT 19.005 103.275 19.175 103.445 ; + RECT 18.545 103.275 18.715 103.445 ; + RECT 18.085 103.275 18.255 103.445 ; + RECT 17.625 103.275 17.795 103.445 ; + RECT 17.165 103.275 17.335 103.445 ; + RECT 16.705 103.275 16.875 103.445 ; + RECT 16.245 103.275 16.415 103.445 ; + RECT 15.785 103.275 15.955 103.445 ; + RECT 15.325 103.275 15.495 103.445 ; + RECT 14.865 103.275 15.035 103.445 ; + RECT 14.405 103.275 14.575 103.445 ; + RECT 13.945 103.275 14.115 103.445 ; + RECT 13.485 103.275 13.655 103.445 ; + RECT 13.025 103.275 13.195 103.445 ; + RECT 12.565 103.275 12.735 103.445 ; + RECT 12.105 103.275 12.275 103.445 ; + RECT 11.645 103.275 11.815 103.445 ; + RECT 11.185 103.275 11.355 103.445 ; + RECT 10.725 103.275 10.895 103.445 ; + RECT 10.265 103.275 10.435 103.445 ; + RECT 9.805 103.275 9.975 103.445 ; + RECT 9.345 103.275 9.515 103.445 ; + RECT 8.885 103.275 9.055 103.445 ; + RECT 8.425 103.275 8.595 103.445 ; + RECT 7.965 103.275 8.135 103.445 ; + RECT 7.505 103.275 7.675 103.445 ; + RECT 7.045 103.275 7.215 103.445 ; + RECT 6.585 103.275 6.755 103.445 ; + RECT 6.125 103.275 6.295 103.445 ; + RECT 5.665 103.275 5.835 103.445 ; + RECT 5.205 103.275 5.375 103.445 ; + RECT 4.745 103.275 4.915 103.445 ; + RECT 4.285 103.275 4.455 103.445 ; + RECT 3.825 103.275 3.995 103.445 ; + RECT 3.365 103.275 3.535 103.445 ; + RECT 2.905 103.275 3.075 103.445 ; + RECT 2.445 103.275 2.615 103.445 ; + RECT 1.985 103.275 2.155 103.445 ; + RECT 1.525 103.275 1.695 103.445 ; + RECT 1.065 103.275 1.235 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 112.845 100.555 113.015 100.725 ; + RECT 112.385 100.555 112.555 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 112.845 95.115 113.015 95.285 ; + RECT 112.385 95.115 112.555 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 112.845 92.395 113.015 92.565 ; + RECT 112.385 92.395 112.555 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 112.845 89.675 113.015 89.845 ; + RECT 112.385 89.675 112.555 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 112.845 84.235 113.015 84.405 ; + RECT 112.385 84.235 112.555 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 112.845 81.515 113.015 81.685 ; + RECT 112.385 81.515 112.555 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 112.845 78.795 113.015 78.965 ; + RECT 112.385 78.795 112.555 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 112.845 76.075 113.015 76.245 ; + RECT 112.385 76.075 112.555 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 112.845 73.355 113.015 73.525 ; + RECT 112.385 73.355 112.555 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 112.845 70.635 113.015 70.805 ; + RECT 112.385 70.635 112.555 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 112.845 67.915 113.015 68.085 ; + RECT 112.385 67.915 112.555 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 112.845 65.195 113.015 65.365 ; + RECT 112.385 65.195 112.555 65.365 ; + RECT 0.605 65.195 0.775 65.365 ; + RECT 0.145 65.195 0.315 65.365 ; + RECT 112.845 62.475 113.015 62.645 ; + RECT 112.385 62.475 112.555 62.645 ; + RECT 0.605 62.475 0.775 62.645 ; + RECT 0.145 62.475 0.315 62.645 ; + RECT 112.845 59.755 113.015 59.925 ; + RECT 112.385 59.755 112.555 59.925 ; + RECT 0.605 59.755 0.775 59.925 ; + RECT 0.145 59.755 0.315 59.925 ; + RECT 112.845 57.035 113.015 57.205 ; + RECT 112.385 57.035 112.555 57.205 ; + RECT 0.605 57.035 0.775 57.205 ; + RECT 0.145 57.035 0.315 57.205 ; + RECT 112.845 54.315 113.015 54.485 ; + RECT 112.385 54.315 112.555 54.485 ; + RECT 0.605 54.315 0.775 54.485 ; + RECT 0.145 54.315 0.315 54.485 ; + RECT 112.845 51.595 113.015 51.765 ; + RECT 112.385 51.595 112.555 51.765 ; + RECT 0.605 51.595 0.775 51.765 ; + RECT 0.145 51.595 0.315 51.765 ; + RECT 112.845 48.875 113.015 49.045 ; + RECT 112.385 48.875 112.555 49.045 ; + RECT 0.605 48.875 0.775 49.045 ; + RECT 0.145 48.875 0.315 49.045 ; + RECT 112.845 46.155 113.015 46.325 ; + RECT 112.385 46.155 112.555 46.325 ; + RECT 0.605 46.155 0.775 46.325 ; + RECT 0.145 46.155 0.315 46.325 ; + RECT 112.845 43.435 113.015 43.605 ; + RECT 112.385 43.435 112.555 43.605 ; + RECT 0.605 43.435 0.775 43.605 ; + RECT 0.145 43.435 0.315 43.605 ; + RECT 112.845 40.715 113.015 40.885 ; + RECT 112.385 40.715 112.555 40.885 ; + RECT 0.605 40.715 0.775 40.885 ; + RECT 0.145 40.715 0.315 40.885 ; + RECT 112.845 37.995 113.015 38.165 ; + RECT 112.385 37.995 112.555 38.165 ; + RECT 0.605 37.995 0.775 38.165 ; + RECT 0.145 37.995 0.315 38.165 ; + RECT 112.845 35.275 113.015 35.445 ; + RECT 112.385 35.275 112.555 35.445 ; + RECT 0.605 35.275 0.775 35.445 ; + RECT 0.145 35.275 0.315 35.445 ; + RECT 112.845 32.555 113.015 32.725 ; + RECT 112.385 32.555 112.555 32.725 ; + RECT 0.605 32.555 0.775 32.725 ; + RECT 0.145 32.555 0.315 32.725 ; + RECT 112.845 29.835 113.015 30.005 ; + RECT 112.385 29.835 112.555 30.005 ; + RECT 0.605 29.835 0.775 30.005 ; + RECT 0.145 29.835 0.315 30.005 ; + RECT 112.845 27.115 113.015 27.285 ; + RECT 112.385 27.115 112.555 27.285 ; + RECT 111.925 27.115 112.095 27.285 ; + RECT 111.465 27.115 111.635 27.285 ; + RECT 111.005 27.115 111.175 27.285 ; + RECT 110.545 27.115 110.715 27.285 ; + RECT 110.085 27.115 110.255 27.285 ; + RECT 109.625 27.115 109.795 27.285 ; + RECT 109.165 27.115 109.335 27.285 ; + RECT 108.705 27.115 108.875 27.285 ; + RECT 108.245 27.115 108.415 27.285 ; + RECT 107.785 27.115 107.955 27.285 ; + RECT 107.325 27.115 107.495 27.285 ; + RECT 106.865 27.115 107.035 27.285 ; + RECT 106.405 27.115 106.575 27.285 ; + RECT 105.945 27.115 106.115 27.285 ; + RECT 105.485 27.115 105.655 27.285 ; + RECT 105.025 27.115 105.195 27.285 ; + RECT 104.565 27.115 104.735 27.285 ; + RECT 104.105 27.115 104.275 27.285 ; + RECT 103.645 27.115 103.815 27.285 ; + RECT 103.185 27.115 103.355 27.285 ; + RECT 102.725 27.115 102.895 27.285 ; + RECT 102.265 27.115 102.435 27.285 ; + RECT 101.805 27.115 101.975 27.285 ; + RECT 101.345 27.115 101.515 27.285 ; + RECT 100.885 27.115 101.055 27.285 ; + RECT 100.425 27.115 100.595 27.285 ; + RECT 99.965 27.115 100.135 27.285 ; + RECT 99.505 27.115 99.675 27.285 ; + RECT 99.045 27.115 99.215 27.285 ; + RECT 98.585 27.115 98.755 27.285 ; + RECT 98.125 27.115 98.295 27.285 ; + RECT 97.665 27.115 97.835 27.285 ; + RECT 97.205 27.115 97.375 27.285 ; + RECT 96.745 27.115 96.915 27.285 ; + RECT 96.285 27.115 96.455 27.285 ; + RECT 95.825 27.115 95.995 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; + RECT 94.445 27.115 94.615 27.285 ; + RECT 93.985 27.115 94.155 27.285 ; + RECT 93.525 27.115 93.695 27.285 ; + RECT 93.065 27.115 93.235 27.285 ; + RECT 92.605 27.115 92.775 27.285 ; + RECT 92.145 27.115 92.315 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; + RECT 90.765 27.115 90.935 27.285 ; + RECT 90.305 27.115 90.475 27.285 ; + RECT 89.845 27.115 90.015 27.285 ; + RECT 89.385 27.115 89.555 27.285 ; + RECT 88.925 27.115 89.095 27.285 ; + RECT 88.465 27.115 88.635 27.285 ; + RECT 88.005 27.115 88.175 27.285 ; + RECT 87.545 27.115 87.715 27.285 ; + RECT 87.085 27.115 87.255 27.285 ; + RECT 86.625 27.115 86.795 27.285 ; + RECT 86.165 27.115 86.335 27.285 ; + RECT 85.705 27.115 85.875 27.285 ; + RECT 85.245 27.115 85.415 27.285 ; + RECT 84.785 27.115 84.955 27.285 ; + RECT 84.325 27.115 84.495 27.285 ; + RECT 83.865 27.115 84.035 27.285 ; + RECT 83.405 27.115 83.575 27.285 ; + RECT 82.945 27.115 83.115 27.285 ; + RECT 82.485 27.115 82.655 27.285 ; + RECT 82.025 27.115 82.195 27.285 ; + RECT 81.565 27.115 81.735 27.285 ; + RECT 81.105 27.115 81.275 27.285 ; + RECT 80.645 27.115 80.815 27.285 ; + RECT 80.185 27.115 80.355 27.285 ; + RECT 79.725 27.115 79.895 27.285 ; + RECT 79.265 27.115 79.435 27.285 ; + RECT 78.805 27.115 78.975 27.285 ; + RECT 78.345 27.115 78.515 27.285 ; + RECT 77.885 27.115 78.055 27.285 ; + RECT 77.425 27.115 77.595 27.285 ; + RECT 76.965 27.115 77.135 27.285 ; + RECT 76.505 27.115 76.675 27.285 ; + RECT 76.045 27.115 76.215 27.285 ; + RECT 75.585 27.115 75.755 27.285 ; + RECT 75.125 27.115 75.295 27.285 ; + RECT 74.665 27.115 74.835 27.285 ; + RECT 74.205 27.115 74.375 27.285 ; + RECT 73.745 27.115 73.915 27.285 ; + RECT 73.285 27.115 73.455 27.285 ; + RECT 72.825 27.115 72.995 27.285 ; + RECT 72.365 27.115 72.535 27.285 ; + RECT 71.905 27.115 72.075 27.285 ; + RECT 71.445 27.115 71.615 27.285 ; + RECT 70.985 27.115 71.155 27.285 ; + RECT 70.525 27.115 70.695 27.285 ; + RECT 70.065 27.115 70.235 27.285 ; + RECT 69.605 27.115 69.775 27.285 ; + RECT 69.145 27.115 69.315 27.285 ; + RECT 68.685 27.115 68.855 27.285 ; + RECT 68.225 27.115 68.395 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; + RECT 66.845 27.115 67.015 27.285 ; + RECT 66.385 27.115 66.555 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; + RECT 65.005 27.115 65.175 27.285 ; + RECT 64.545 27.115 64.715 27.285 ; + RECT 64.085 27.115 64.255 27.285 ; + RECT 63.625 27.115 63.795 27.285 ; + RECT 63.165 27.115 63.335 27.285 ; + RECT 62.705 27.115 62.875 27.285 ; + RECT 62.245 27.115 62.415 27.285 ; + RECT 61.785 27.115 61.955 27.285 ; + RECT 61.325 27.115 61.495 27.285 ; + RECT 60.865 27.115 61.035 27.285 ; + RECT 60.405 27.115 60.575 27.285 ; + RECT 59.945 27.115 60.115 27.285 ; + RECT 59.485 27.115 59.655 27.285 ; + RECT 59.025 27.115 59.195 27.285 ; + RECT 58.565 27.115 58.735 27.285 ; + RECT 58.105 27.115 58.275 27.285 ; + RECT 57.645 27.115 57.815 27.285 ; + RECT 57.185 27.115 57.355 27.285 ; + RECT 56.725 27.115 56.895 27.285 ; + RECT 56.265 27.115 56.435 27.285 ; + RECT 55.805 27.115 55.975 27.285 ; + RECT 55.345 27.115 55.515 27.285 ; + RECT 54.885 27.115 55.055 27.285 ; + RECT 54.425 27.115 54.595 27.285 ; + RECT 53.965 27.115 54.135 27.285 ; + RECT 53.505 27.115 53.675 27.285 ; + RECT 53.045 27.115 53.215 27.285 ; + RECT 52.585 27.115 52.755 27.285 ; + RECT 52.125 27.115 52.295 27.285 ; + RECT 51.665 27.115 51.835 27.285 ; + RECT 51.205 27.115 51.375 27.285 ; + RECT 50.745 27.115 50.915 27.285 ; + RECT 50.285 27.115 50.455 27.285 ; + RECT 49.825 27.115 49.995 27.285 ; + RECT 49.365 27.115 49.535 27.285 ; + RECT 48.905 27.115 49.075 27.285 ; + RECT 48.445 27.115 48.615 27.285 ; + RECT 47.985 27.115 48.155 27.285 ; + RECT 47.525 27.115 47.695 27.285 ; + RECT 47.065 27.115 47.235 27.285 ; + RECT 46.605 27.115 46.775 27.285 ; + RECT 46.145 27.115 46.315 27.285 ; + RECT 45.685 27.115 45.855 27.285 ; + RECT 45.225 27.115 45.395 27.285 ; + RECT 44.765 27.115 44.935 27.285 ; + RECT 44.305 27.115 44.475 27.285 ; + RECT 43.845 27.115 44.015 27.285 ; + RECT 43.385 27.115 43.555 27.285 ; + RECT 42.925 27.115 43.095 27.285 ; + RECT 42.465 27.115 42.635 27.285 ; + RECT 42.005 27.115 42.175 27.285 ; + RECT 41.545 27.115 41.715 27.285 ; + RECT 41.085 27.115 41.255 27.285 ; + RECT 40.625 27.115 40.795 27.285 ; + RECT 40.165 27.115 40.335 27.285 ; + RECT 39.705 27.115 39.875 27.285 ; + RECT 39.245 27.115 39.415 27.285 ; + RECT 38.785 27.115 38.955 27.285 ; + RECT 38.325 27.115 38.495 27.285 ; + RECT 37.865 27.115 38.035 27.285 ; + RECT 37.405 27.115 37.575 27.285 ; + RECT 36.945 27.115 37.115 27.285 ; + RECT 36.485 27.115 36.655 27.285 ; + RECT 36.025 27.115 36.195 27.285 ; + RECT 35.565 27.115 35.735 27.285 ; + RECT 35.105 27.115 35.275 27.285 ; + RECT 34.645 27.115 34.815 27.285 ; + RECT 34.185 27.115 34.355 27.285 ; + RECT 33.725 27.115 33.895 27.285 ; + RECT 33.265 27.115 33.435 27.285 ; + RECT 32.805 27.115 32.975 27.285 ; + RECT 32.345 27.115 32.515 27.285 ; + RECT 31.885 27.115 32.055 27.285 ; + RECT 31.425 27.115 31.595 27.285 ; + RECT 30.965 27.115 31.135 27.285 ; + RECT 30.505 27.115 30.675 27.285 ; + RECT 30.045 27.115 30.215 27.285 ; + RECT 29.585 27.115 29.755 27.285 ; + RECT 29.125 27.115 29.295 27.285 ; + RECT 28.665 27.115 28.835 27.285 ; + RECT 28.205 27.115 28.375 27.285 ; + RECT 27.745 27.115 27.915 27.285 ; + RECT 27.285 27.115 27.455 27.285 ; + RECT 26.825 27.115 26.995 27.285 ; + RECT 26.365 27.115 26.535 27.285 ; + RECT 25.905 27.115 26.075 27.285 ; + RECT 25.445 27.115 25.615 27.285 ; + RECT 24.985 27.115 25.155 27.285 ; + RECT 24.525 27.115 24.695 27.285 ; + RECT 24.065 27.115 24.235 27.285 ; + RECT 23.605 27.115 23.775 27.285 ; + RECT 23.145 27.115 23.315 27.285 ; + RECT 22.685 27.115 22.855 27.285 ; + RECT 22.225 27.115 22.395 27.285 ; + RECT 21.765 27.115 21.935 27.285 ; + RECT 21.305 27.115 21.475 27.285 ; + RECT 20.845 27.115 21.015 27.285 ; + RECT 20.385 27.115 20.555 27.285 ; + RECT 19.925 27.115 20.095 27.285 ; + RECT 19.465 27.115 19.635 27.285 ; + RECT 19.005 27.115 19.175 27.285 ; + RECT 18.545 27.115 18.715 27.285 ; + RECT 18.085 27.115 18.255 27.285 ; + RECT 17.625 27.115 17.795 27.285 ; + RECT 17.165 27.115 17.335 27.285 ; + RECT 16.705 27.115 16.875 27.285 ; + RECT 16.245 27.115 16.415 27.285 ; + RECT 15.785 27.115 15.955 27.285 ; + RECT 15.325 27.115 15.495 27.285 ; + RECT 14.865 27.115 15.035 27.285 ; + RECT 14.405 27.115 14.575 27.285 ; + RECT 13.945 27.115 14.115 27.285 ; + RECT 13.485 27.115 13.655 27.285 ; + RECT 13.025 27.115 13.195 27.285 ; + RECT 12.565 27.115 12.735 27.285 ; + RECT 12.105 27.115 12.275 27.285 ; + RECT 11.645 27.115 11.815 27.285 ; + RECT 11.185 27.115 11.355 27.285 ; + RECT 10.725 27.115 10.895 27.285 ; + RECT 10.265 27.115 10.435 27.285 ; + RECT 9.805 27.115 9.975 27.285 ; + RECT 9.345 27.115 9.515 27.285 ; + RECT 8.885 27.115 9.055 27.285 ; + RECT 8.425 27.115 8.595 27.285 ; + RECT 7.965 27.115 8.135 27.285 ; + RECT 7.505 27.115 7.675 27.285 ; + RECT 7.045 27.115 7.215 27.285 ; + RECT 6.585 27.115 6.755 27.285 ; + RECT 6.125 27.115 6.295 27.285 ; + RECT 5.665 27.115 5.835 27.285 ; + RECT 5.205 27.115 5.375 27.285 ; + RECT 4.745 27.115 4.915 27.285 ; + RECT 4.285 27.115 4.455 27.285 ; + RECT 3.825 27.115 3.995 27.285 ; + RECT 3.365 27.115 3.535 27.285 ; + RECT 2.905 27.115 3.075 27.285 ; + RECT 2.445 27.115 2.615 27.285 ; + RECT 1.985 27.115 2.155 27.285 ; + RECT 1.525 27.115 1.695 27.285 ; + RECT 1.065 27.115 1.235 27.285 ; + RECT 0.605 27.115 0.775 27.285 ; + RECT 0.145 27.115 0.315 27.285 ; + RECT 112.845 24.395 113.015 24.565 ; + RECT 112.385 24.395 112.555 24.565 ; + RECT 29.125 24.395 29.295 24.565 ; + RECT 28.665 24.395 28.835 24.565 ; + RECT 112.845 21.675 113.015 21.845 ; + RECT 112.385 21.675 112.555 21.845 ; + RECT 29.125 21.675 29.295 21.845 ; + RECT 28.665 21.675 28.835 21.845 ; + RECT 112.845 18.955 113.015 19.125 ; + RECT 112.385 18.955 112.555 19.125 ; + RECT 29.125 18.955 29.295 19.125 ; + RECT 28.665 18.955 28.835 19.125 ; + RECT 112.845 16.235 113.015 16.405 ; + RECT 112.385 16.235 112.555 16.405 ; + RECT 29.125 16.235 29.295 16.405 ; + RECT 28.665 16.235 28.835 16.405 ; + RECT 112.845 13.515 113.015 13.685 ; + RECT 112.385 13.515 112.555 13.685 ; + RECT 29.125 13.515 29.295 13.685 ; + RECT 28.665 13.515 28.835 13.685 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 112.845 8.075 113.015 8.245 ; + RECT 112.385 8.075 112.555 8.245 ; + RECT 29.125 8.075 29.295 8.245 ; + RECT 28.665 8.075 28.835 8.245 ; + RECT 112.845 5.355 113.015 5.525 ; + RECT 112.385 5.355 112.555 5.525 ; + RECT 29.125 5.355 29.295 5.525 ; + RECT 28.665 5.355 28.835 5.525 ; + RECT 112.845 2.635 113.015 2.805 ; + RECT 112.385 2.635 112.555 2.805 ; + RECT 29.125 2.635 29.295 2.805 ; + RECT 28.665 2.635 28.835 2.805 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; + RECT 102.725 -0.085 102.895 0.085 ; + RECT 102.265 -0.085 102.435 0.085 ; + RECT 101.805 -0.085 101.975 0.085 ; + RECT 101.345 -0.085 101.515 0.085 ; + RECT 100.885 -0.085 101.055 0.085 ; + RECT 100.425 -0.085 100.595 0.085 ; + RECT 99.965 -0.085 100.135 0.085 ; + RECT 99.505 -0.085 99.675 0.085 ; + RECT 99.045 -0.085 99.215 0.085 ; + RECT 98.585 -0.085 98.755 0.085 ; + RECT 98.125 -0.085 98.295 0.085 ; + RECT 97.665 -0.085 97.835 0.085 ; + RECT 97.205 -0.085 97.375 0.085 ; + RECT 96.745 -0.085 96.915 0.085 ; + RECT 96.285 -0.085 96.455 0.085 ; + RECT 95.825 -0.085 95.995 0.085 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; + RECT 84.325 -0.085 84.495 0.085 ; + RECT 83.865 -0.085 84.035 0.085 ; + RECT 83.405 -0.085 83.575 0.085 ; + RECT 82.945 -0.085 83.115 0.085 ; + RECT 82.485 -0.085 82.655 0.085 ; + RECT 82.025 -0.085 82.195 0.085 ; + RECT 81.565 -0.085 81.735 0.085 ; + RECT 81.105 -0.085 81.275 0.085 ; + RECT 80.645 -0.085 80.815 0.085 ; + RECT 80.185 -0.085 80.355 0.085 ; + RECT 79.725 -0.085 79.895 0.085 ; + RECT 79.265 -0.085 79.435 0.085 ; + RECT 78.805 -0.085 78.975 0.085 ; + RECT 78.345 -0.085 78.515 0.085 ; + RECT 77.885 -0.085 78.055 0.085 ; + RECT 77.425 -0.085 77.595 0.085 ; + RECT 76.965 -0.085 77.135 0.085 ; + RECT 76.505 -0.085 76.675 0.085 ; + RECT 76.045 -0.085 76.215 0.085 ; + RECT 75.585 -0.085 75.755 0.085 ; + RECT 75.125 -0.085 75.295 0.085 ; + RECT 74.665 -0.085 74.835 0.085 ; + RECT 74.205 -0.085 74.375 0.085 ; + RECT 73.745 -0.085 73.915 0.085 ; + RECT 73.285 -0.085 73.455 0.085 ; + RECT 72.825 -0.085 72.995 0.085 ; + RECT 72.365 -0.085 72.535 0.085 ; + RECT 71.905 -0.085 72.075 0.085 ; + RECT 71.445 -0.085 71.615 0.085 ; + RECT 70.985 -0.085 71.155 0.085 ; + RECT 70.525 -0.085 70.695 0.085 ; + RECT 70.065 -0.085 70.235 0.085 ; + RECT 69.605 -0.085 69.775 0.085 ; + RECT 69.145 -0.085 69.315 0.085 ; + RECT 68.685 -0.085 68.855 0.085 ; + RECT 68.225 -0.085 68.395 0.085 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; + RECT 65.925 -0.085 66.095 0.085 ; + RECT 65.465 -0.085 65.635 0.085 ; + RECT 65.005 -0.085 65.175 0.085 ; + RECT 64.545 -0.085 64.715 0.085 ; + RECT 64.085 -0.085 64.255 0.085 ; + RECT 63.625 -0.085 63.795 0.085 ; + RECT 63.165 -0.085 63.335 0.085 ; + RECT 62.705 -0.085 62.875 0.085 ; + RECT 62.245 -0.085 62.415 0.085 ; + RECT 61.785 -0.085 61.955 0.085 ; + RECT 61.325 -0.085 61.495 0.085 ; + RECT 60.865 -0.085 61.035 0.085 ; + RECT 60.405 -0.085 60.575 0.085 ; + RECT 59.945 -0.085 60.115 0.085 ; + RECT 59.485 -0.085 59.655 0.085 ; + RECT 59.025 -0.085 59.195 0.085 ; + RECT 58.565 -0.085 58.735 0.085 ; + RECT 58.105 -0.085 58.275 0.085 ; + RECT 57.645 -0.085 57.815 0.085 ; + RECT 57.185 -0.085 57.355 0.085 ; + RECT 56.725 -0.085 56.895 0.085 ; + RECT 56.265 -0.085 56.435 0.085 ; + RECT 55.805 -0.085 55.975 0.085 ; + RECT 55.345 -0.085 55.515 0.085 ; + RECT 54.885 -0.085 55.055 0.085 ; + RECT 54.425 -0.085 54.595 0.085 ; + RECT 53.965 -0.085 54.135 0.085 ; + RECT 53.505 -0.085 53.675 0.085 ; + RECT 53.045 -0.085 53.215 0.085 ; + RECT 52.585 -0.085 52.755 0.085 ; + RECT 52.125 -0.085 52.295 0.085 ; + RECT 51.665 -0.085 51.835 0.085 ; + RECT 51.205 -0.085 51.375 0.085 ; + RECT 50.745 -0.085 50.915 0.085 ; + RECT 50.285 -0.085 50.455 0.085 ; + RECT 49.825 -0.085 49.995 0.085 ; + RECT 49.365 -0.085 49.535 0.085 ; + RECT 48.905 -0.085 49.075 0.085 ; + RECT 48.445 -0.085 48.615 0.085 ; + RECT 47.985 -0.085 48.155 0.085 ; + RECT 47.525 -0.085 47.695 0.085 ; + RECT 47.065 -0.085 47.235 0.085 ; + RECT 46.605 -0.085 46.775 0.085 ; + RECT 46.145 -0.085 46.315 0.085 ; + RECT 45.685 -0.085 45.855 0.085 ; + RECT 45.225 -0.085 45.395 0.085 ; + RECT 44.765 -0.085 44.935 0.085 ; + RECT 44.305 -0.085 44.475 0.085 ; + RECT 43.845 -0.085 44.015 0.085 ; + RECT 43.385 -0.085 43.555 0.085 ; + RECT 42.925 -0.085 43.095 0.085 ; + RECT 42.465 -0.085 42.635 0.085 ; + RECT 42.005 -0.085 42.175 0.085 ; + RECT 41.545 -0.085 41.715 0.085 ; + RECT 41.085 -0.085 41.255 0.085 ; + RECT 40.625 -0.085 40.795 0.085 ; + RECT 40.165 -0.085 40.335 0.085 ; + RECT 39.705 -0.085 39.875 0.085 ; + RECT 39.245 -0.085 39.415 0.085 ; + RECT 38.785 -0.085 38.955 0.085 ; + RECT 38.325 -0.085 38.495 0.085 ; + RECT 37.865 -0.085 38.035 0.085 ; + RECT 37.405 -0.085 37.575 0.085 ; + RECT 36.945 -0.085 37.115 0.085 ; + RECT 36.485 -0.085 36.655 0.085 ; + RECT 36.025 -0.085 36.195 0.085 ; + RECT 35.565 -0.085 35.735 0.085 ; + RECT 35.105 -0.085 35.275 0.085 ; + RECT 34.645 -0.085 34.815 0.085 ; + RECT 34.185 -0.085 34.355 0.085 ; + RECT 33.725 -0.085 33.895 0.085 ; + RECT 33.265 -0.085 33.435 0.085 ; + RECT 32.805 -0.085 32.975 0.085 ; + RECT 32.345 -0.085 32.515 0.085 ; + RECT 31.885 -0.085 32.055 0.085 ; + RECT 31.425 -0.085 31.595 0.085 ; + RECT 30.965 -0.085 31.135 0.085 ; + RECT 30.505 -0.085 30.675 0.085 ; + RECT 30.045 -0.085 30.215 0.085 ; + RECT 29.585 -0.085 29.755 0.085 ; + RECT 29.125 -0.085 29.295 0.085 ; + RECT 28.665 -0.085 28.835 0.085 ; + LAYER via ; + RECT 85.485 103.285 85.635 103.435 ; + RECT 56.045 103.285 56.195 103.435 ; + RECT 6.365 103.285 6.515 103.435 ; + RECT 2.225 101.585 2.375 101.735 ; + RECT 85.485 27.125 85.635 27.275 ; + RECT 56.045 27.125 56.195 27.275 ; + RECT 6.365 27.125 6.515 27.275 ; + RECT 67.085 1.625 67.235 1.775 ; + RECT 85.485 -0.075 85.635 0.075 ; + RECT 56.045 -0.075 56.195 0.075 ; + LAYER via2 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.74 92.38 1.94 92.58 ; + RECT 1.28 88.3 1.48 88.5 ; + RECT 1.28 82.86 1.48 83.06 ; + RECT 1.28 77.42 1.48 77.62 ; + RECT 1.28 69.26 1.48 69.46 ; + RECT 1.28 47.5 1.48 47.7 ; + RECT 1.28 31.18 1.48 31.38 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 30.26 8.06 30.46 8.26 ; + RECT 29.8 3.3 30 3.5 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via3 ; + RECT 85.46 103.26 85.66 103.46 ; + RECT 56.02 103.26 56.22 103.46 ; + RECT 6.34 103.26 6.54 103.46 ; + RECT 1.74 70.62 1.94 70.82 ; + RECT 6.34 27.1 6.54 27.3 ; + RECT 30.26 14.18 30.46 14.38 ; + RECT 85.46 -0.1 85.66 0.1 ; + RECT 56.02 -0.1 56.22 0.1 ; + LAYER via4 ; + RECT 6.04 65.68 6.84 66.48 ; + RECT 6.04 64.08 6.84 64.88 ; + LAYER fieldpoly ; + POLYGON 113.02 103.22 113.02 0.14 28.66 0.14 28.66 27.34 0.14 27.34 0.14 103.22 ; + LAYER diff ; + POLYGON 113.16 103.36 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER nwell ; + POLYGON 113.35 102.055 113.35 99.225 111.13 99.225 111.13 100.83 112.05 100.83 112.05 102.055 ; + POLYGON 3.87 102.055 3.87 100.45 2.03 100.45 2.03 99.225 -0.19 99.225 -0.19 102.055 ; + POLYGON 113.35 96.615 113.35 93.785 112.05 93.785 112.05 95.01 111.13 95.01 111.13 96.615 ; + RECT -0.19 93.785 2.03 96.615 ; + POLYGON 113.35 91.175 113.35 88.345 111.13 88.345 111.13 89.95 112.51 89.95 112.51 91.175 ; + RECT -0.19 88.345 2.03 91.175 ; + POLYGON 113.35 85.735 113.35 82.905 112.51 82.905 112.51 84.13 112.05 84.13 112.05 85.735 ; + RECT -0.19 82.905 2.03 85.735 ; + POLYGON 113.35 80.295 113.35 77.465 112.51 77.465 112.51 78.69 112.05 78.69 112.05 80.295 ; + RECT -0.19 77.465 2.03 80.295 ; + POLYGON 113.35 74.855 113.35 72.025 112.51 72.025 112.51 73.25 112.05 73.25 112.05 74.855 ; + RECT -0.19 72.025 2.03 74.855 ; + POLYGON 113.35 69.415 113.35 66.585 112.05 66.585 112.05 67.81 109.29 67.81 109.29 69.415 ; + RECT -0.19 66.585 2.03 69.415 ; + RECT 112.51 61.145 113.35 63.975 ; + POLYGON 2.03 63.975 2.03 62.75 3.87 62.75 3.87 61.145 -0.19 61.145 -0.19 63.975 ; + POLYGON 113.35 58.535 113.35 55.705 112.05 55.705 112.05 56.93 111.13 56.93 111.13 58.535 ; + RECT -0.19 55.705 2.03 58.535 ; + POLYGON 113.35 53.095 113.35 50.265 109.29 50.265 109.29 51.87 112.51 51.87 112.51 53.095 ; + RECT -0.19 50.265 2.03 53.095 ; + POLYGON 113.35 47.655 113.35 44.825 112.05 44.825 112.05 46.43 112.51 46.43 112.51 47.655 ; + RECT -0.19 44.825 2.03 47.655 ; + RECT 112.51 39.385 113.35 42.215 ; + POLYGON 3.87 42.215 3.87 40.61 2.03 40.61 2.03 39.385 -0.19 39.385 -0.19 42.215 ; + RECT 112.51 33.945 113.35 36.775 ; + POLYGON 3.87 36.775 3.87 35.17 2.03 35.17 2.03 33.945 -0.19 33.945 -0.19 36.775 ; + RECT 112.51 28.505 113.35 31.335 ; + POLYGON 2.03 31.335 2.03 30.11 3.87 30.11 3.87 28.505 -0.19 28.505 -0.19 31.335 ; + RECT 112.05 23.065 113.35 25.895 ; + POLYGON 30.55 25.895 30.55 24.67 32.39 24.67 32.39 23.065 28.33 23.065 28.33 25.895 ; + RECT 112.51 17.625 113.35 20.455 ; + RECT 28.33 17.625 32.39 20.455 ; + POLYGON 113.35 15.015 113.35 12.185 112.51 12.185 112.51 13.41 112.05 13.41 112.05 15.015 ; + POLYGON 30.55 15.015 30.55 13.79 32.39 13.79 32.39 12.185 28.33 12.185 28.33 15.015 ; + POLYGON 113.35 9.575 113.35 6.745 112.05 6.745 112.05 8.35 112.51 8.35 112.51 9.575 ; + POLYGON 30.55 9.575 30.55 8.35 32.39 8.35 32.39 6.745 28.33 6.745 28.33 9.575 ; + POLYGON 113.35 4.135 113.35 1.305 109.29 1.305 109.29 2.91 112.51 2.91 112.51 4.135 ; + POLYGON 30.55 4.135 30.55 2.91 32.39 2.91 32.39 1.305 28.33 1.305 28.33 4.135 ; + POLYGON 113.16 103.36 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER pwell ; + RECT 106.85 103.31 107.07 103.48 ; + RECT 103.17 103.31 103.39 103.48 ; + RECT 99.49 103.31 99.71 103.48 ; + RECT 95.81 103.31 96.03 103.48 ; + RECT 92.13 103.31 92.35 103.48 ; + RECT 88.45 103.31 88.67 103.48 ; + RECT 84.77 103.31 84.99 103.48 ; + RECT 81.09 103.31 81.31 103.48 ; + RECT 77.41 103.31 77.63 103.48 ; + RECT 73.73 103.31 73.95 103.48 ; + RECT 70.05 103.31 70.27 103.48 ; + RECT 66.37 103.31 66.59 103.48 ; + RECT 62.69 103.31 62.91 103.48 ; + RECT 59.01 103.31 59.23 103.48 ; + RECT 55.33 103.31 55.55 103.48 ; + RECT 51.65 103.31 51.87 103.48 ; + RECT 47.97 103.31 48.19 103.48 ; + RECT 44.29 103.31 44.51 103.48 ; + RECT 40.61 103.31 40.83 103.48 ; + RECT 36.93 103.31 37.15 103.48 ; + RECT 33.25 103.31 33.47 103.48 ; + RECT 29.57 103.31 29.79 103.48 ; + RECT 25.89 103.31 26.11 103.48 ; + RECT 22.21 103.31 22.43 103.48 ; + RECT 18.53 103.31 18.75 103.48 ; + RECT 14.85 103.31 15.07 103.48 ; + RECT 11.17 103.31 11.39 103.48 ; + RECT 7.49 103.31 7.71 103.48 ; + RECT 3.81 103.31 4.03 103.48 ; + RECT 0.13 103.31 0.35 103.48 ; + RECT 110.575 103.3 110.685 103.42 ; + RECT 112.395 103.3 112.555 103.41 ; + RECT 25.89 27.08 26.11 27.25 ; + RECT 22.21 27.08 22.43 27.25 ; + RECT 18.53 27.08 18.75 27.25 ; + RECT 14.85 27.08 15.07 27.25 ; + RECT 11.17 27.08 11.39 27.25 ; + RECT 7.49 27.08 7.71 27.25 ; + RECT 3.81 27.08 4.03 27.25 ; + RECT 0.13 27.08 0.35 27.25 ; + RECT 109.61 -0.12 109.83 0.05 ; + RECT 105.93 -0.12 106.15 0.05 ; + RECT 102.25 -0.12 102.47 0.05 ; + RECT 98.57 -0.12 98.79 0.05 ; + RECT 94.89 -0.12 95.11 0.05 ; + RECT 91.21 -0.12 91.43 0.05 ; + RECT 87.53 -0.12 87.75 0.05 ; + RECT 83.85 -0.12 84.07 0.05 ; + RECT 80.17 -0.12 80.39 0.05 ; + RECT 76.49 -0.12 76.71 0.05 ; + RECT 72.81 -0.12 73.03 0.05 ; + RECT 69.13 -0.12 69.35 0.05 ; + RECT 65.45 -0.12 65.67 0.05 ; + RECT 61.77 -0.12 61.99 0.05 ; + RECT 58.09 -0.12 58.31 0.05 ; + RECT 54.41 -0.12 54.63 0.05 ; + RECT 50.73 -0.12 50.95 0.05 ; + RECT 47.05 -0.12 47.27 0.05 ; + RECT 43.37 -0.12 43.59 0.05 ; + RECT 39.69 -0.12 39.91 0.05 ; + RECT 36.01 -0.12 36.23 0.05 ; + RECT 32.33 -0.12 32.55 0.05 ; + RECT 28.65 -0.12 28.87 0.05 ; + POLYGON 113.16 103.36 113.16 0 28.52 0 28.52 27.2 0 27.2 0 103.36 ; + LAYER OVERLAP ; + POLYGON 28.52 0 28.52 27.2 0 27.2 0 103.36 113.16 103.36 113.16 0 ; + END +END sb_2__2_ + +END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..61e5246 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -0,0 +1,24126 @@ +*SPEF "1481-1998" +*DESIGN "cbx_1__0_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 90.620 75.480 +chanx_left_in[0] I *C 3.220 75.480 +chanx_left_in[1] I *C 0.690 66.640 +chanx_left_in[2] I *C 0.690 6.800 +chanx_left_in[3] I *C 0.690 68.000 +chanx_left_in[4] I *C 0.690 35.360 +chanx_left_in[5] I *C 0.690 57.120 +chanx_left_in[6] I *C 0.690 28.560 +chanx_left_in[7] I *C 0.690 51.680 +chanx_left_in[8] I *C 0.690 34.000 +chanx_left_in[9] I *C 0.690 40.800 +chanx_left_in[10] I *C 0.690 24.480 +chanx_left_in[11] I *C 0.690 55.760 +chanx_left_in[12] I *C 0.690 69.360 +chanx_left_in[13] I *C 0.690 61.200 +chanx_left_in[14] I *C 0.690 23.120 +chanx_left_in[15] I *C 0.690 39.440 +chanx_left_in[16] I *C 0.690 36.720 +chanx_left_in[17] I *C 0.690 62.560 +chanx_left_in[18] I *C 0.690 20.400 +chanx_left_in[19] I *C 0.690 53.040 +chanx_right_in[0] I *C 104.190 27.200 +chanx_right_in[1] I *C 104.190 64.600 +chanx_right_in[2] I *C 104.190 15.640 +chanx_right_in[3] I *C 104.190 59.840 +chanx_right_in[4] I *C 104.190 11.560 +chanx_right_in[5] I *C 104.190 61.200 +chanx_right_in[6] I *C 104.190 25.840 +chanx_right_in[7] I *C 104.190 48.960 +chanx_right_in[8] I *C 104.190 21.760 +chanx_right_in[9] I *C 104.190 34.000 +chanx_right_in[10] I *C 104.190 20.400 +chanx_right_in[11] I *C 104.190 38.080 +chanx_right_in[12] I *C 104.190 23.120 +chanx_right_in[13] I *C 104.190 65.960 +chanx_right_in[14] I *C 104.190 17.680 +chanx_right_in[15] I *C 104.190 39.440 +chanx_right_in[16] I *C 104.190 31.280 +chanx_right_in[17] I *C 104.190 43.520 +chanx_right_in[18] I *C 104.190 10.200 +chanx_right_in[19] I *C 104.190 58.480 +ccff_head[0] I *C 104.190 55.760 +chanx_left_out[0] O *C 0.690 46.240 +chanx_left_out[1] O *C 2.300 0.680 +chanx_left_out[2] O *C 0.690 12.240 +chanx_left_out[3] O *C 0.690 8.160 +chanx_left_out[4] O *C 0.690 13.600 +chanx_left_out[5] O *C 0.690 9.520 +chanx_left_out[6] O *C 0.690 31.280 +chanx_left_out[7] O *C 0.690 47.600 +chanx_left_out[8] O *C 0.690 14.960 +chanx_left_out[9] O *C 0.690 72.080 +chanx_left_out[10] O *C 0.690 25.840 +chanx_left_out[11] O *C 0.690 29.920 +chanx_left_out[12] O *C 0.690 19.040 +chanx_left_out[13] O *C 0.690 44.880 +chanx_left_out[14] O *C 0.690 17.680 +chanx_left_out[15] O *C 0.690 42.160 +chanx_left_out[16] O *C 0.690 4.080 +chanx_left_out[17] O *C 0.690 63.920 +chanx_left_out[18] O *C 0.690 50.320 +chanx_left_out[19] O *C 0.690 58.480 +chanx_right_out[0] O *C 100.740 75.480 +chanx_right_out[1] O *C 104.190 54.400 +chanx_right_out[2] O *C 100.280 75.480 +chanx_right_out[3] O *C 104.190 53.040 +chanx_right_out[4] O *C 102.580 75.480 +chanx_right_out[5] O *C 104.190 50.320 +chanx_right_out[6] O *C 104.190 47.600 +chanx_right_out[7] O *C 104.190 70.720 +chanx_right_out[8] O *C 104.190 32.640 +chanx_right_out[9] O *C 104.190 72.080 +chanx_right_out[10] O *C 101.660 75.480 +chanx_right_out[11] O *C 104.190 69.360 +chanx_right_out[12] O *C 104.190 36.720 +chanx_right_out[13] O *C 104.190 44.880 +chanx_right_out[14] O *C 104.190 6.800 +chanx_right_out[15] O *C 104.190 42.160 +chanx_right_out[16] O *C 104.190 28.560 +chanx_right_out[17] O *C 102.580 0.680 +chanx_right_out[18] O *C 104.190 5.440 +chanx_right_out[19] O *C 104.190 4.080 +top_grid_pin_16_[0] O *C 34.040 75.480 +top_grid_pin_17_[0] O *C 35.880 75.480 +top_grid_pin_18_[0] O *C 34.960 75.480 +top_grid_pin_19_[0] O *C 36.800 75.480 +top_grid_pin_20_[0] O *C 57.500 75.480 +top_grid_pin_21_[0] O *C 16.100 75.480 +top_grid_pin_22_[0] O *C 33.120 75.480 +top_grid_pin_23_[0] O *C 15.180 75.480 +top_grid_pin_24_[0] O *C 2.300 75.480 +top_grid_pin_25_[0] O *C 12.420 75.480 +top_grid_pin_26_[0] O *C 13.340 75.480 +top_grid_pin_27_[0] O *C 14.260 75.480 +top_grid_pin_28_[0] O *C 73.600 75.480 +top_grid_pin_29_[0] O *C 74.520 75.480 +top_grid_pin_30_[0] O *C 76.360 75.480 +top_grid_pin_31_[0] O *C 75.440 75.480 +bottom_grid_pin_0_[0] O *C 97.520 0.680 +ccff_tail[0] O *C 57.500 0.680 +VDD I *C 52.440 38.080 +VSS I *C 52.440 38.080 + +*D_NET chanx_left_in[0] 0.02919863 //LENGTH 213.180 LUMPCC 0.008279803 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 3.220 74.835 +*I mux_bottom_ipin_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 18.400 30.940 +*I mux_bottom_ipin_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 23.825 28.900 +*I mux_bottom_ipin_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 37.260 28.900 +*I mux_bottom_ipin_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 62.200 25.500 +*I mux_bottom_ipin_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 71.400 25.500 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 90.985 28.900 +*I mux_top_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 95.220 28.900 +*I BUFT_RR_58:A I *L 0.001776 *C 80.040 72.080 +*I mux_bottom_ipin_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.645 23.460 +*I mux_bottom_ipin_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.000 28.900 +*N chanx_left_in[0]:11 *C 22.600 32.640 +*N chanx_left_in[0]:12 *C 53.038 28.900 +*N chanx_left_in[0]:13 *C 53.360 28.900 +*N chanx_left_in[0]:14 *C 54.645 23.460 +*N chanx_left_in[0]:15 *C 54.740 23.505 +*N chanx_left_in[0]:16 *C 80.002 72.080 +*N chanx_left_in[0]:17 *C 78.705 72.080 +*N chanx_left_in[0]:18 *C 78.660 72.035 +*N chanx_left_in[0]:19 *C 78.660 44.258 +*N chanx_left_in[0]:20 *C 78.653 44.200 +*N chanx_left_in[0]:21 *C 76.368 44.200 +*N chanx_left_in[0]:22 *C 76.360 44.143 +*N chanx_left_in[0]:23 *C 95.183 28.900 +*N chanx_left_in[0]:24 *C 90.985 28.900 +*N chanx_left_in[0]:25 *C 88.825 28.900 +*N chanx_left_in[0]:26 *C 88.780 28.855 +*N chanx_left_in[0]:27 *C 88.780 26.565 +*N chanx_left_in[0]:28 *C 88.735 26.520 +*N chanx_left_in[0]:29 *C 76.405 26.520 +*N chanx_left_in[0]:30 *C 76.360 26.520 +*N chanx_left_in[0]:31 *C 76.360 25.218 +*N chanx_left_in[0]:32 *C 76.353 25.160 +*N chanx_left_in[0]:33 *C 71.300 25.500 +*N chanx_left_in[0]:34 *C 71.300 25.500 +*N chanx_left_in[0]:35 *C 71.300 25.160 +*N chanx_left_in[0]:36 *C 71.300 25.160 +*N chanx_left_in[0]:37 *C 62.100 25.500 +*N chanx_left_in[0]:38 *C 62.100 25.500 +*N chanx_left_in[0]:39 *C 62.100 25.160 +*N chanx_left_in[0]:40 *C 62.100 25.160 +*N chanx_left_in[0]:41 *C 54.748 25.160 +*N chanx_left_in[0]:42 *C 54.740 25.160 +*N chanx_left_in[0]:43 *C 54.740 28.515 +*N chanx_left_in[0]:44 *C 54.695 28.560 +*N chanx_left_in[0]:45 *C 53.360 28.560 +*N chanx_left_in[0]:46 *C 51.105 28.560 +*N chanx_left_in[0]:47 *C 51.060 28.560 +*N chanx_left_in[0]:48 *C 51.053 28.560 +*N chanx_left_in[0]:49 *C 36.808 28.560 +*N chanx_left_in[0]:50 *C 36.800 28.560 +*N chanx_left_in[0]:51 *C 36.800 28.560 +*N chanx_left_in[0]:52 *C 37.223 28.900 +*N chanx_left_in[0]:53 *C 36.800 28.900 +*N chanx_left_in[0]:54 *C 23.965 28.900 +*N chanx_left_in[0]:55 *C 23.920 28.900 +*N chanx_left_in[0]:56 *C 23.000 28.900 +*N chanx_left_in[0]:57 *C 18.438 30.940 +*N chanx_left_in[0]:58 *C 18.860 30.940 +*N chanx_left_in[0]:59 *C 18.860 31.960 +*N chanx_left_in[0]:60 *C 22.955 31.960 +*N chanx_left_in[0]:61 *C 23.000 31.960 +*N chanx_left_in[0]:62 *C 23.000 32.583 +*N chanx_left_in[0]:63 *C 23.000 32.640 +*N chanx_left_in[0]:64 *C 23.000 32.648 +*N chanx_left_in[0]:65 *C 23.000 74.112 +*N chanx_left_in[0]:66 *C 23.000 74.125 +*N chanx_left_in[0]:67 *C 23.000 74.800 +*N chanx_left_in[0]:68 *C 10.580 74.800 +*N chanx_left_in[0]:69 *C 10.580 74.120 +*N chanx_left_in[0]:70 *C 3.228 74.120 +*N chanx_left_in[0]:71 *C 3.220 74.178 + +*CAP +0 chanx_left_in[0] 5.096326e-05 +1 mux_bottom_ipin_10\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_ipin_8\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_ipin_2\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_ipin_4\/mux_l1_in_0_:A1 1e-06 +5 mux_bottom_ipin_14\/mux_l1_in_0_:A1 1e-06 +6 mux_bottom_ipin_0\/mux_l1_in_0_:A1 1e-06 +7 mux_top_ipin_0\/mux_l1_in_0_:A1 1e-06 +8 BUFT_RR_58:A 1e-06 +9 mux_bottom_ipin_6\/mux_l1_in_0_:A1 1e-06 +10 mux_bottom_ipin_12\/mux_l1_in_0_:A1 1e-06 +11 chanx_left_in[0]:11 9.203509e-05 +12 chanx_left_in[0]:12 5.029135e-05 +13 chanx_left_in[0]:13 7.482899e-05 +14 chanx_left_in[0]:14 2.945022e-05 +15 chanx_left_in[0]:15 8.549642e-05 +16 chanx_left_in[0]:16 8.753609e-05 +17 chanx_left_in[0]:17 8.753609e-05 +18 chanx_left_in[0]:18 0.001397279 +19 chanx_left_in[0]:19 0.001397279 +20 chanx_left_in[0]:20 0.0001733458 +21 chanx_left_in[0]:21 0.0001733458 +22 chanx_left_in[0]:22 0.0006630715 +23 chanx_left_in[0]:23 0.0003186979 +24 chanx_left_in[0]:24 0.0004702128 +25 chanx_left_in[0]:25 0.0001219384 +26 chanx_left_in[0]:26 0.0001606872 +27 chanx_left_in[0]:27 0.0001606872 +28 chanx_left_in[0]:28 0.0007534207 +29 chanx_left_in[0]:29 0.0007534207 +30 chanx_left_in[0]:30 0.0007722782 +31 chanx_left_in[0]:31 7.475312e-05 +32 chanx_left_in[0]:32 0.0003927661 +33 chanx_left_in[0]:33 3.269818e-05 +34 chanx_left_in[0]:34 5.331514e-05 +35 chanx_left_in[0]:35 5.729255e-05 +36 chanx_left_in[0]:36 0.0005910235 +37 chanx_left_in[0]:37 3.126141e-05 +38 chanx_left_in[0]:38 5.272171e-05 +39 chanx_left_in[0]:39 5.679348e-05 +40 chanx_left_in[0]:40 0.0004168927 +41 chanx_left_in[0]:41 0.0002186355 +42 chanx_left_in[0]:42 0.0002830867 +43 chanx_left_in[0]:43 0.0001603603 +44 chanx_left_in[0]:44 8.967426e-05 +45 chanx_left_in[0]:45 0.0002553121 +46 chanx_left_in[0]:46 0.0001411002 +47 chanx_left_in[0]:47 3.953676e-05 +48 chanx_left_in[0]:48 0.0004720385 +49 chanx_left_in[0]:49 0.0004720385 +50 chanx_left_in[0]:50 4.065167e-05 +51 chanx_left_in[0]:51 5.875579e-05 +52 chanx_left_in[0]:52 3.900648e-05 +53 chanx_left_in[0]:53 0.0008853755 +54 chanx_left_in[0]:54 0.0008190294 +55 chanx_left_in[0]:55 9.162964e-05 +56 chanx_left_in[0]:56 0.0002383304 +57 chanx_left_in[0]:57 5.810047e-05 +58 chanx_left_in[0]:58 0.0001199983 +59 chanx_left_in[0]:59 0.0003647977 +60 chanx_left_in[0]:60 0.0003028998 +61 chanx_left_in[0]:61 0.000248575 +62 chanx_left_in[0]:62 3.574312e-05 +63 chanx_left_in[0]:63 9.203509e-05 +64 chanx_left_in[0]:64 0.001649938 +65 chanx_left_in[0]:65 0.001649938 +66 chanx_left_in[0]:66 4.776618e-05 +67 chanx_left_in[0]:67 0.0007497887 +68 chanx_left_in[0]:68 0.0007465749 +69 chanx_left_in[0]:69 0.0004491908 +70 chanx_left_in[0]:70 0.0004046384 +71 chanx_left_in[0]:71 5.096326e-05 +72 chanx_left_in[0]:19 chanx_left_in[7]:14 0.0003507744 +73 chanx_left_in[0]:18 chanx_left_in[7]:13 0.0003507744 +74 chanx_left_in[0]:54 chanx_left_in[12]:22 6.759408e-06 +75 chanx_left_in[0]:49 chanx_left_in[12]:22 0.0008133516 +76 chanx_left_in[0]:48 chanx_left_in[12]:21 0.0008133516 +77 chanx_left_in[0]:53 chanx_left_in[12]:21 6.759408e-06 +78 chanx_left_in[0]:54 chanx_left_in[16]:30 5.129997e-06 +79 chanx_left_in[0]:55 chanx_left_in[16]:29 6.499944e-06 +80 chanx_left_in[0]:49 chanx_left_in[16]:30 0.0001325899 +81 chanx_left_in[0]:48 chanx_left_in[16]:29 0.0001325899 +82 chanx_left_in[0]:29 chanx_left_in[16]:20 3.872662e-05 +83 chanx_left_in[0]:29 chanx_left_in[16]:18 6.994542e-05 +84 chanx_left_in[0]:29 chanx_left_in[16]:13 2.01765e-06 +85 chanx_left_in[0]:28 chanx_left_in[16]:12 2.01765e-06 +86 chanx_left_in[0]:28 chanx_left_in[16]:17 6.994542e-05 +87 chanx_left_in[0]:28 chanx_left_in[16]:19 3.872662e-05 +88 chanx_left_in[0]:53 chanx_left_in[16]:29 5.129997e-06 +89 chanx_left_in[0]:56 chanx_left_in[16]:30 6.499944e-06 +90 chanx_left_in[0]:41 chanx_right_in[4]:11 0.0001120372 +91 chanx_left_in[0]:41 chanx_right_in[4]:12 4.29697e-05 +92 chanx_left_in[0]:32 chanx_right_in[4]:18 8.605317e-05 +93 chanx_left_in[0]:40 chanx_right_in[4]:17 0.0001683224 +94 chanx_left_in[0]:40 chanx_right_in[4]:12 0.0001984902 +95 chanx_left_in[0]:36 chanx_right_in[4]:18 0.0001253527 +96 chanx_left_in[0]:36 chanx_right_in[4]:17 0.0001725062 +97 chanx_left_in[0]:41 chanx_right_in[12]:25 0.0004061351 +98 chanx_left_in[0]:32 chanx_right_in[12]:26 3.428483e-05 +99 chanx_left_in[0]:40 chanx_right_in[12]:25 0.0005127228 +100 chanx_left_in[0]:40 chanx_right_in[12]:26 0.0004061351 +101 chanx_left_in[0]:35 chanx_right_in[12]:27 1.611402e-07 +102 chanx_left_in[0]:36 chanx_right_in[12]:25 3.428483e-05 +103 chanx_left_in[0]:36 chanx_right_in[12]:26 0.0005127228 +104 chanx_left_in[0]:34 chanx_right_in[12]:28 1.611402e-07 +105 chanx_left_in[0]:42 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 3.991769e-05 +106 chanx_left_in[0]:42 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 2.052841e-05 +107 chanx_left_in[0]:43 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 3.991769e-05 +108 chanx_left_in[0]:15 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 2.052841e-05 +109 chanx_left_in[0]:22 mux_tree_tapbuf_size8_6_sram[0]:11 0.0001394194 +110 chanx_left_in[0]:30 mux_tree_tapbuf_size8_6_sram[0]:10 0.0001394194 +111 chanx_left_in[0]:30 mux_tree_tapbuf_size8_6_sram[0]:11 1.068636e-06 +112 chanx_left_in[0]:31 mux_tree_tapbuf_size8_6_sram[0]:10 1.068636e-06 +113 chanx_left_in[0]:22 mux_tree_tapbuf_size8_6_sram[3]:8 0.0001231357 +114 chanx_left_in[0]:22 mux_tree_tapbuf_size8_6_sram[3]:11 9.911638e-07 +115 chanx_left_in[0]:22 mux_tree_tapbuf_size8_6_sram[3]:10 8.346643e-07 +116 chanx_left_in[0]:30 mux_tree_tapbuf_size8_6_sram[3]:5 8.346643e-07 +117 chanx_left_in[0]:30 mux_tree_tapbuf_size8_6_sram[3]:9 0.0001231357 +118 chanx_left_in[0]:30 mux_tree_tapbuf_size8_6_sram[3]:10 9.911638e-07 +119 chanx_left_in[0]:60 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 1.355525e-05 +120 chanx_left_in[0]:61 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 9.483726e-06 +121 chanx_left_in[0]:61 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 5.481922e-06 +122 chanx_left_in[0]:62 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 9.483726e-06 +123 chanx_left_in[0]:64 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.0003538138 +124 chanx_left_in[0]:65 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.0003538138 +125 chanx_left_in[0]:59 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 1.355525e-05 +126 chanx_left_in[0]:56 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 5.481922e-06 +127 chanx_left_in[0]:25 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.226274e-05 +128 chanx_left_in[0]:23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.579938e-05 +129 chanx_left_in[0]:24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.226274e-05 +130 chanx_left_in[0]:24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.579938e-05 +131 chanx_left_in[0]:64 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0004431389 +132 chanx_left_in[0]:65 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0004431389 +133 chanx_left_in[0]:22 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.295566e-05 +134 chanx_left_in[0]:30 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.295566e-05 +135 chanx_left_in[0]:30 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.555074e-05 +136 chanx_left_in[0]:31 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.555074e-05 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:71 0.0005870535 +1 chanx_left_in[0]:57 mux_bottom_ipin_10\/mux_l1_in_0_:A1 0.152 +2 chanx_left_in[0]:60 chanx_left_in[0]:59 0.00365625 +3 chanx_left_in[0]:61 chanx_left_in[0]:60 0.0045 +4 chanx_left_in[0]:61 chanx_left_in[0]:56 0.002732143 +5 chanx_left_in[0]:54 mux_bottom_ipin_8\/mux_l1_in_0_:A1 0.152 +6 chanx_left_in[0]:54 chanx_left_in[0]:53 0.01145982 +7 chanx_left_in[0]:55 chanx_left_in[0]:54 0.0045 +8 chanx_left_in[0]:51 chanx_left_in[0]:50 0.0045 +9 chanx_left_in[0]:50 chanx_left_in[0]:49 0.00341 +10 chanx_left_in[0]:49 chanx_left_in[0]:48 0.002231717 +11 chanx_left_in[0]:47 chanx_left_in[0]:46 0.0045 +12 chanx_left_in[0]:48 chanx_left_in[0]:47 0.00341 +13 chanx_left_in[0]:46 chanx_left_in[0]:45 0.002013393 +14 chanx_left_in[0]:22 chanx_left_in[0]:21 0.00341 +15 chanx_left_in[0]:21 chanx_left_in[0]:20 0.0003579833 +16 chanx_left_in[0]:19 chanx_left_in[0]:18 0.02480134 +17 chanx_left_in[0]:20 chanx_left_in[0]:19 0.00341 +18 chanx_left_in[0]:17 chanx_left_in[0]:16 0.001158482 +19 chanx_left_in[0]:18 chanx_left_in[0]:17 0.0045 +20 chanx_left_in[0]:16 BUFT_RR_58:A 0.152 +21 chanx_left_in[0]:29 chanx_left_in[0]:28 0.01100893 +22 chanx_left_in[0]:30 chanx_left_in[0]:29 0.0045 +23 chanx_left_in[0]:30 chanx_left_in[0]:22 0.01573438 +24 chanx_left_in[0]:28 chanx_left_in[0]:27 0.0045 +25 chanx_left_in[0]:27 chanx_left_in[0]:26 0.002044643 +26 chanx_left_in[0]:25 chanx_left_in[0]:24 0.001928571 +27 chanx_left_in[0]:26 chanx_left_in[0]:25 0.0045 +28 chanx_left_in[0]:42 chanx_left_in[0]:41 0.00341 +29 chanx_left_in[0]:42 chanx_left_in[0]:15 0.001477679 +30 chanx_left_in[0]:41 chanx_left_in[0]:40 0.001151892 +31 chanx_left_in[0]:62 chanx_left_in[0]:61 0.0005558036 +32 chanx_left_in[0]:63 chanx_left_in[0]:62 0.00341 +33 chanx_left_in[0]:63 chanx_left_in[0]:11 5.69697e-05 +34 chanx_left_in[0]:64 chanx_left_in[0]:63 0.00341 +35 chanx_left_in[0]:66 chanx_left_in[0]:65 0.00341 +36 chanx_left_in[0]:65 chanx_left_in[0]:64 0.006496183 +37 chanx_left_in[0]:71 chanx_left_in[0]:70 0.00341 +38 chanx_left_in[0]:70 chanx_left_in[0]:69 0.001151892 +39 chanx_left_in[0]:44 chanx_left_in[0]:43 0.0045 +40 chanx_left_in[0]:43 chanx_left_in[0]:42 0.002995536 +41 chanx_left_in[0]:23 mux_top_ipin_0\/mux_l1_in_0_:A1 0.152 +42 chanx_left_in[0]:31 chanx_left_in[0]:30 0.001162947 +43 chanx_left_in[0]:32 chanx_left_in[0]:31 0.00341 +44 chanx_left_in[0]:14 mux_bottom_ipin_6\/mux_l1_in_0_:A1 0.152 +45 chanx_left_in[0]:15 chanx_left_in[0]:14 0.0045 +46 chanx_left_in[0]:39 chanx_left_in[0]:38 0.0001634616 +47 chanx_left_in[0]:40 chanx_left_in[0]:39 0.00341 +48 chanx_left_in[0]:40 chanx_left_in[0]:36 0.001441333 +49 chanx_left_in[0]:37 mux_bottom_ipin_4\/mux_l1_in_0_:A1 0.152 +50 chanx_left_in[0]:38 chanx_left_in[0]:37 0.0045 +51 chanx_left_in[0]:12 mux_bottom_ipin_12\/mux_l1_in_0_:A1 0.152 +52 chanx_left_in[0]:35 chanx_left_in[0]:34 0.0001634615 +53 chanx_left_in[0]:36 chanx_left_in[0]:35 0.00341 +54 chanx_left_in[0]:36 chanx_left_in[0]:32 0.0007915584 +55 chanx_left_in[0]:33 mux_bottom_ipin_14\/mux_l1_in_0_:A1 0.152 +56 chanx_left_in[0]:34 chanx_left_in[0]:33 0.0045 +57 chanx_left_in[0]:52 mux_bottom_ipin_2\/mux_l1_in_0_:A1 0.152 +58 chanx_left_in[0]:24 mux_bottom_ipin_0\/mux_l1_in_0_:A1 0.152 +59 chanx_left_in[0]:24 chanx_left_in[0]:23 0.003747768 +60 chanx_left_in[0]:58 chanx_left_in[0]:57 0.0003772322 +61 chanx_left_in[0]:59 chanx_left_in[0]:58 0.0009107143 +62 chanx_left_in[0]:53 chanx_left_in[0]:52 0.0003772322 +63 chanx_left_in[0]:53 chanx_left_in[0]:51 0.0003035715 +64 chanx_left_in[0]:45 chanx_left_in[0]:44 0.001191964 +65 chanx_left_in[0]:45 chanx_left_in[0]:13 0.0003035715 +66 chanx_left_in[0]:13 chanx_left_in[0]:12 0.0002879465 +67 chanx_left_in[0]:56 chanx_left_in[0]:55 0.0008214285 +68 chanx_left_in[0]:69 chanx_left_in[0]:68 0.0001065333 +69 chanx_left_in[0]:68 chanx_left_in[0]:67 0.0019458 +70 chanx_left_in[0]:67 chanx_left_in[0]:66 0.00010575 + +*END + +*D_NET chanx_right_in[0] 0.01958974 //LENGTH 139.690 LUMPCC 0.003596256 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 103.650 27.200 +*I mux_top_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 95.510 27.880 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 91.370 27.880 +*I mux_bottom_ipin_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 61.815 26.520 +*I mux_bottom_ipin_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 22.780 +*I mux_bottom_ipin_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.615 27.880 +*I mux_bottom_ipin_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 37.435 27.880 +*I mux_bottom_ipin_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 24.210 27.880 +*I ropt_mt_inst_721:A I *L 0.001767 *C 4.600 47.600 +*I mux_bottom_ipin_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 18.115 31.620 +*I mux_bottom_ipin_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.015 26.520 +*N chanx_right_in[0]:11 *C 70.890 26.520 +*N chanx_right_in[0]:12 *C 18.078 31.620 +*N chanx_right_in[0]:13 *C 4.562 47.600 +*N chanx_right_in[0]:14 *C 3.265 47.600 +*N chanx_right_in[0]:15 *C 3.220 47.555 +*N chanx_right_in[0]:16 *C 3.220 37.445 +*N chanx_right_in[0]:17 *C 3.265 37.400 +*N chanx_right_in[0]:18 *C 7.775 37.400 +*N chanx_right_in[0]:19 *C 7.820 37.355 +*N chanx_right_in[0]:20 *C 7.820 32.005 +*N chanx_right_in[0]:21 *C 7.865 31.960 +*N chanx_right_in[0]:22 *C 15.180 31.960 +*N chanx_right_in[0]:23 *C 15.312 31.620 +*N chanx_right_in[0]:24 *C 15.180 31.575 +*N chanx_right_in[0]:25 *C 15.180 28.265 +*N chanx_right_in[0]:26 *C 15.225 28.220 +*N chanx_right_in[0]:27 *C 24.210 28.220 +*N chanx_right_in[0]:28 *C 24.210 27.880 +*N chanx_right_in[0]:29 *C 37.435 27.880 +*N chanx_right_in[0]:30 *C 52.615 27.880 +*N chanx_right_in[0]:31 *C 53.775 27.880 +*N chanx_right_in[0]:32 *C 53.820 27.835 +*N chanx_right_in[0]:33 *C 54.992 22.780 +*N chanx_right_in[0]:34 *C 53.865 22.780 +*N chanx_right_in[0]:35 *C 53.820 22.825 +*N chanx_right_in[0]:36 *C 53.820 26.180 +*N chanx_right_in[0]:37 *C 53.865 26.180 +*N chanx_right_in[0]:38 *C 58.880 26.180 +*N chanx_right_in[0]:39 *C 58.880 26.520 +*N chanx_right_in[0]:40 *C 61.815 26.520 +*N chanx_right_in[0]:41 *C 70.795 26.520 +*N chanx_right_in[0]:42 *C 70.840 26.565 +*N chanx_right_in[0]:43 *C 70.840 28.175 +*N chanx_right_in[0]:44 *C 70.885 28.220 +*N chanx_right_in[0]:45 *C 77.740 28.220 +*N chanx_right_in[0]:46 *C 77.740 27.880 +*N chanx_right_in[0]:47 *C 91.370 27.880 +*N chanx_right_in[0]:48 *C 95.510 27.880 +*N chanx_right_in[0]:49 *C 101.155 27.880 +*N chanx_right_in[0]:50 *C 101.200 27.835 +*N chanx_right_in[0]:51 *C 101.200 27.258 +*N chanx_right_in[0]:52 *C 101.208 27.200 + +*CAP +0 chanx_right_in[0] 0.0002393441 +1 mux_top_ipin_0\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_ipin_4\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_ipin_6\/mux_l1_in_0_:A0 1e-06 +5 mux_bottom_ipin_12\/mux_l1_in_0_:A0 1e-06 +6 mux_bottom_ipin_2\/mux_l1_in_0_:A0 1e-06 +7 mux_bottom_ipin_8\/mux_l1_in_0_:A0 1e-06 +8 ropt_mt_inst_721:A 1e-06 +9 mux_bottom_ipin_10\/mux_l1_in_0_:A0 1e-06 +10 mux_bottom_ipin_14\/mux_l1_in_0_:A0 1e-06 +11 chanx_right_in[0]:11 2.24535e-05 +12 chanx_right_in[0]:12 0.0002076318 +13 chanx_right_in[0]:13 6.252779e-05 +14 chanx_right_in[0]:14 6.252779e-05 +15 chanx_right_in[0]:15 0.0002919527 +16 chanx_right_in[0]:16 0.0002919527 +17 chanx_right_in[0]:17 0.0002845023 +18 chanx_right_in[0]:18 0.0002845023 +19 chanx_right_in[0]:19 0.0002369771 +20 chanx_right_in[0]:20 0.0002369771 +21 chanx_right_in[0]:21 0.0005190293 +22 chanx_right_in[0]:22 0.0005479306 +23 chanx_right_in[0]:23 0.000236533 +24 chanx_right_in[0]:24 0.000229472 +25 chanx_right_in[0]:25 0.000229472 +26 chanx_right_in[0]:26 0.0004450169 +27 chanx_right_in[0]:27 0.0004720421 +28 chanx_right_in[0]:28 0.0008922656 +29 chanx_right_in[0]:29 0.001836345 +30 chanx_right_in[0]:30 0.001061113 +31 chanx_right_in[0]:31 8.906669e-05 +32 chanx_right_in[0]:32 0.0001046025 +33 chanx_right_in[0]:33 0.0001003766 +34 chanx_right_in[0]:34 0.0001003766 +35 chanx_right_in[0]:35 0.0002025515 +36 chanx_right_in[0]:36 0.0003399442 +37 chanx_right_in[0]:37 0.0004155666 +38 chanx_right_in[0]:38 0.0004414697 +39 chanx_right_in[0]:39 0.0002279922 +40 chanx_right_in[0]:40 0.0007918422 +41 chanx_right_in[0]:41 0.0005831718 +42 chanx_right_in[0]:42 0.0001196983 +43 chanx_right_in[0]:43 0.0001196983 +44 chanx_right_in[0]:44 0.0002868607 +45 chanx_right_in[0]:45 0.0003141949 +46 chanx_right_in[0]:46 0.0008588976 +47 chanx_right_in[0]:47 0.00109762 +48 chanx_right_in[0]:48 0.0005257318 +49 chanx_right_in[0]:49 0.000263287 +50 chanx_right_in[0]:50 3.531024e-05 +51 chanx_right_in[0]:51 3.531024e-05 +52 chanx_right_in[0]:52 0.0002393441 +53 chanx_right_in[0]:16 chanx_left_in[12]:28 0.0002806464 +54 chanx_right_in[0]:15 chanx_left_in[12]:29 0.0002806464 +55 chanx_right_in[0]:26 chanx_left_in[12]:22 5.915314e-06 +56 chanx_right_in[0]:29 chanx_left_in[12]:21 6.105272e-06 +57 chanx_right_in[0]:28 chanx_left_in[12]:22 6.105272e-06 +58 chanx_right_in[0]:27 chanx_left_in[12]:21 5.915314e-06 +59 chanx_right_in[0]:30 mux_tree_tapbuf_size8_2_sram[3]:11 0.0001595519 +60 chanx_right_in[0]:30 mux_tree_tapbuf_size8_2_sram[3]:7 4.989382e-07 +61 chanx_right_in[0]:29 mux_tree_tapbuf_size8_2_sram[3]:10 0.0001595519 +62 chanx_right_in[0]:29 mux_tree_tapbuf_size8_2_sram[3]:6 4.989382e-07 +63 chanx_right_in[0]:26 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002609261 +64 chanx_right_in[0]:27 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002609261 +65 chanx_right_in[0]:21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.133224e-05 +66 chanx_right_in[0]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.446059e-06 +67 chanx_right_in[0]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.446059e-06 +68 chanx_right_in[0]:22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.133224e-05 +69 chanx_right_in[0]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001148268 +70 chanx_right_in[0]:18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.186601e-07 +71 chanx_right_in[0]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001148268 +72 chanx_right_in[0]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.186601e-07 +73 chanx_right_in[0]:18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 7.846268e-05 +74 chanx_right_in[0]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.846268e-05 +75 chanx_right_in[0]:16 optlc_net_107:8 9.886736e-05 +76 chanx_right_in[0]:14 optlc_net_107:15 4.372474e-05 +77 chanx_right_in[0]:15 optlc_net_107:9 9.886736e-05 +78 chanx_right_in[0]:13 optlc_net_107:14 4.372474e-05 +79 chanx_right_in[0]:47 optlc_net_108:20 4.802705e-06 +80 chanx_right_in[0]:47 optlc_net_108:21 0.0001073104 +81 chanx_right_in[0]:42 optlc_net_108:40 4.039532e-08 +82 chanx_right_in[0]:44 optlc_net_108:22 5.37399e-05 +83 chanx_right_in[0]:44 optlc_net_108:41 0.00010696 +84 chanx_right_in[0]:44 optlc_net_108:24 0.0001083074 +85 chanx_right_in[0]:43 optlc_net_108:39 4.039532e-08 +86 chanx_right_in[0]:45 optlc_net_108:42 0.00010696 +87 chanx_right_in[0]:45 optlc_net_108:41 0.0001083074 +88 chanx_right_in[0]:45 optlc_net_108:21 5.37399e-05 +89 chanx_right_in[0]:46 optlc_net_108:22 0.0001073104 +90 chanx_right_in[0]:46 optlc_net_108:8 4.802705e-06 +91 chanx_right_in[0]:48 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.563282e-05 +92 chanx_right_in[0]:48 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001979019 +93 chanx_right_in[0]:47 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.563282e-05 +94 chanx_right_in[0]:49 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001979019 +95 chanx_right_in[0]:50 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.551043e-05 +96 chanx_right_in[0]:51 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.551043e-05 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:52 0.0003826583 +1 chanx_right_in[0]:37 chanx_right_in[0]:36 0.0045 +2 chanx_right_in[0]:36 chanx_right_in[0]:35 0.002995536 +3 chanx_right_in[0]:36 chanx_right_in[0]:32 0.001477679 +4 chanx_right_in[0]:31 chanx_right_in[0]:30 0.001035714 +5 chanx_right_in[0]:32 chanx_right_in[0]:31 0.0045 +6 chanx_right_in[0]:21 chanx_right_in[0]:20 0.0045 +7 chanx_right_in[0]:20 chanx_right_in[0]:19 0.004776786 +8 chanx_right_in[0]:18 chanx_right_in[0]:17 0.004026785 +9 chanx_right_in[0]:19 chanx_right_in[0]:18 0.0045 +10 chanx_right_in[0]:17 chanx_right_in[0]:16 0.0045 +11 chanx_right_in[0]:16 chanx_right_in[0]:15 0.009026786 +12 chanx_right_in[0]:14 chanx_right_in[0]:13 0.001158482 +13 chanx_right_in[0]:15 chanx_right_in[0]:14 0.0045 +14 chanx_right_in[0]:13 ropt_mt_inst_721:A 0.152 +15 chanx_right_in[0]:23 chanx_right_in[0]:22 0.0003035715 +16 chanx_right_in[0]:23 chanx_right_in[0]:12 0.00246875 +17 chanx_right_in[0]:24 chanx_right_in[0]:23 0.0045 +18 chanx_right_in[0]:26 chanx_right_in[0]:25 0.0045 +19 chanx_right_in[0]:25 chanx_right_in[0]:24 0.002955357 +20 chanx_right_in[0]:12 mux_bottom_ipin_10\/mux_l1_in_0_:A0 0.152 +21 chanx_right_in[0]:48 mux_top_ipin_0\/mux_l1_in_0_:A0 0.152 +22 chanx_right_in[0]:48 chanx_right_in[0]:47 0.003696429 +23 chanx_right_in[0]:34 chanx_right_in[0]:33 0.001006696 +24 chanx_right_in[0]:35 chanx_right_in[0]:34 0.0045 +25 chanx_right_in[0]:33 mux_bottom_ipin_6\/mux_l1_in_0_:A0 0.152 +26 chanx_right_in[0]:40 mux_bottom_ipin_4\/mux_l1_in_0_:A0 0.152 +27 chanx_right_in[0]:40 chanx_right_in[0]:39 0.002620536 +28 chanx_right_in[0]:30 mux_bottom_ipin_12\/mux_l1_in_0_:A0 0.152 +29 chanx_right_in[0]:30 chanx_right_in[0]:29 0.01355357 +30 chanx_right_in[0]:11 mux_bottom_ipin_14\/mux_l1_in_0_:A0 0.152 +31 chanx_right_in[0]:29 mux_bottom_ipin_2\/mux_l1_in_0_:A0 0.152 +32 chanx_right_in[0]:29 chanx_right_in[0]:28 0.01180804 +33 chanx_right_in[0]:47 mux_bottom_ipin_0\/mux_l1_in_0_:A0 0.152 +34 chanx_right_in[0]:47 chanx_right_in[0]:46 0.01216964 +35 chanx_right_in[0]:28 mux_bottom_ipin_8\/mux_l1_in_0_:A0 0.152 +36 chanx_right_in[0]:28 chanx_right_in[0]:27 0.0003035715 +37 chanx_right_in[0]:49 chanx_right_in[0]:48 0.005040179 +38 chanx_right_in[0]:50 chanx_right_in[0]:49 0.0045 +39 chanx_right_in[0]:51 chanx_right_in[0]:50 0.000515625 +40 chanx_right_in[0]:52 chanx_right_in[0]:51 0.00341 +41 chanx_right_in[0]:41 chanx_right_in[0]:40 0.008017858 +42 chanx_right_in[0]:41 chanx_right_in[0]:11 8.482143e-05 +43 chanx_right_in[0]:42 chanx_right_in[0]:41 0.0045 +44 chanx_right_in[0]:44 chanx_right_in[0]:43 0.0045 +45 chanx_right_in[0]:43 chanx_right_in[0]:42 0.0014375 +46 chanx_right_in[0]:22 chanx_right_in[0]:21 0.006531251 +47 chanx_right_in[0]:27 chanx_right_in[0]:26 0.008022322 +48 chanx_right_in[0]:38 chanx_right_in[0]:37 0.004477679 +49 chanx_right_in[0]:39 chanx_right_in[0]:38 0.0003035715 +50 chanx_right_in[0]:45 chanx_right_in[0]:44 0.006120536 +51 chanx_right_in[0]:46 chanx_right_in[0]:45 0.0003035715 + +*END + +*D_NET chanx_right_in[3] 0.02663361 //LENGTH 191.105 LUMPCC 0.003750508 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 103.575 59.840 +*I mux_bottom_ipin_15\/mux_l2_in_1_:A1 I *L 0.00198 *C 90.065 58.140 +*I mux_bottom_ipin_13\/mux_l1_in_1_:A0 I *L 0.001631 *C 82.170 58.820 +*I mux_bottom_ipin_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 69.290 53.380 +*I mux_bottom_ipin_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 61.010 53.380 +*I mux_bottom_ipin_11\/mux_l2_in_1_:A1 I *L 0.00198 *C 29.345 52.700 +*I mux_bottom_ipin_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 19.165 53.380 +*I FTB_24__23:A I *L 0.001776 *C 13.340 6.800 +*I mux_bottom_ipin_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 34.500 58.140 +*I mux_bottom_ipin_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 45.905 52.700 +*N chanx_right_in[3]:10 *C 34.500 58.125 +*N chanx_right_in[3]:11 *C 13.340 6.800 +*N chanx_right_in[3]:12 *C 13.340 6.845 +*N chanx_right_in[3]:13 *C 13.340 9.475 +*N chanx_right_in[3]:14 *C 13.295 9.520 +*N chanx_right_in[3]:15 *C 8.785 9.520 +*N chanx_right_in[3]:16 *C 8.740 9.565 +*N chanx_right_in[3]:17 *C 8.740 10.822 +*N chanx_right_in[3]:18 *C 8.732 10.880 +*N chanx_right_in[3]:19 *C 7.380 10.880 +*N chanx_right_in[3]:20 *C 7.360 10.888 +*N chanx_right_in[3]:21 *C 7.360 44.873 +*N chanx_right_in[3]:22 *C 7.380 44.880 +*N chanx_right_in[3]:23 *C 19.203 53.380 +*N chanx_right_in[3]:24 *C 20.195 53.380 +*N chanx_right_in[3]:25 *C 20.240 53.335 +*N chanx_right_in[3]:26 *C 20.240 44.938 +*N chanx_right_in[3]:27 *C 20.240 44.880 +*N chanx_right_in[3]:28 *C 29.893 44.880 +*N chanx_right_in[3]:29 *C 29.900 44.938 +*N chanx_right_in[3]:30 *C 29.900 51.680 +*N chanx_right_in[3]:31 *C 31.280 51.680 +*N chanx_right_in[3]:32 *C 29.383 52.700 +*N chanx_right_in[3]:33 *C 31.235 52.700 +*N chanx_right_in[3]:34 *C 31.280 52.700 +*N chanx_right_in[3]:35 *C 31.280 57.755 +*N chanx_right_in[3]:36 *C 31.325 57.800 +*N chanx_right_in[3]:37 *C 34.500 57.800 +*N chanx_right_in[3]:38 *C 43.240 57.800 +*N chanx_right_in[3]:39 *C 43.240 58.140 +*N chanx_right_in[3]:40 *C 45.955 58.140 +*N chanx_right_in[3]:41 *C 46.000 58.095 +*N chanx_right_in[3]:42 *C 46.000 52.745 +*N chanx_right_in[3]:43 *C 45.905 52.700 +*N chanx_right_in[3]:44 *C 46.000 52.360 +*N chanx_right_in[3]:45 *C 61.010 53.380 +*N chanx_right_in[3]:46 *C 61.180 53.380 +*N chanx_right_in[3]:47 *C 61.180 53.335 +*N chanx_right_in[3]:48 *C 61.180 52.405 +*N chanx_right_in[3]:49 *C 61.180 52.360 +*N chanx_right_in[3]:50 *C 68.955 52.360 +*N chanx_right_in[3]:51 *C 69.000 52.405 +*N chanx_right_in[3]:52 *C 69.290 53.380 +*N chanx_right_in[3]:53 *C 69.000 53.380 +*N chanx_right_in[3]:54 *C 69.000 53.380 +*N chanx_right_in[3]:55 *C 69.000 52.983 +*N chanx_right_in[3]:56 *C 69.008 53.040 +*N chanx_right_in[3]:57 *C 81.873 53.040 +*N chanx_right_in[3]:58 *C 81.880 53.098 +*N chanx_right_in[3]:59 *C 81.880 58.775 +*N chanx_right_in[3]:60 *C 81.880 58.820 +*N chanx_right_in[3]:61 *C 82.208 58.820 +*N chanx_right_in[3]:62 *C 83.260 58.820 +*N chanx_right_in[3]:63 *C 83.260 57.800 +*N chanx_right_in[3]:64 *C 90.620 57.800 +*N chanx_right_in[3]:65 *C 90.103 58.140 +*N chanx_right_in[3]:66 *C 90.620 58.140 +*N chanx_right_in[3]:67 *C 100.235 58.140 +*N chanx_right_in[3]:68 *C 100.280 58.185 +*N chanx_right_in[3]:69 *C 100.280 59.783 +*N chanx_right_in[3]:70 *C 100.288 59.840 + +*CAP +0 chanx_right_in[3] 0.0002550568 +1 mux_bottom_ipin_15\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_13\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_ipin_1\/mux_l1_in_1_:A0 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_1_:A0 1e-06 +5 mux_bottom_ipin_11\/mux_l2_in_1_:A1 1e-06 +6 mux_bottom_ipin_9\/mux_l1_in_1_:A0 1e-06 +7 FTB_24__23:A 1e-06 +8 mux_bottom_ipin_7\/mux_l2_in_1_:A1 1e-06 +9 mux_bottom_ipin_3\/mux_l2_in_1_:A1 1e-06 +10 chanx_right_in[3]:10 3.105308e-05 +11 chanx_right_in[3]:11 3.739507e-05 +12 chanx_right_in[3]:12 0.0001569361 +13 chanx_right_in[3]:13 0.0001569361 +14 chanx_right_in[3]:14 0.0002159111 +15 chanx_right_in[3]:15 0.0002159111 +16 chanx_right_in[3]:16 8.772555e-05 +17 chanx_right_in[3]:17 8.772555e-05 +18 chanx_right_in[3]:18 0.0001101352 +19 chanx_right_in[3]:19 0.0001101352 +20 chanx_right_in[3]:20 0.001964716 +21 chanx_right_in[3]:21 0.001964716 +22 chanx_right_in[3]:22 0.0008874852 +23 chanx_right_in[3]:23 0.0001284622 +24 chanx_right_in[3]:24 0.0001284622 +25 chanx_right_in[3]:25 0.0003975183 +26 chanx_right_in[3]:26 0.0003975183 +27 chanx_right_in[3]:27 0.001528215 +28 chanx_right_in[3]:28 0.0006407296 +29 chanx_right_in[3]:29 0.0004696788 +30 chanx_right_in[3]:30 0.0005405466 +31 chanx_right_in[3]:31 0.0001269133 +32 chanx_right_in[3]:32 0.0001730869 +33 chanx_right_in[3]:33 0.0001730869 +34 chanx_right_in[3]:34 0.0003948996 +35 chanx_right_in[3]:35 0.0003051617 +36 chanx_right_in[3]:36 0.0001852681 +37 chanx_right_in[3]:37 0.000781512 +38 chanx_right_in[3]:38 0.0005920664 +39 chanx_right_in[3]:39 0.0002500656 +40 chanx_right_in[3]:40 0.00022319 +41 chanx_right_in[3]:41 0.0003603364 +42 chanx_right_in[3]:42 0.0003603364 +43 chanx_right_in[3]:43 5.85956e-05 +44 chanx_right_in[3]:44 0.001033553 +45 chanx_right_in[3]:45 5.317751e-05 +46 chanx_right_in[3]:46 5.844462e-05 +47 chanx_right_in[3]:47 8.230655e-05 +48 chanx_right_in[3]:48 8.230655e-05 +49 chanx_right_in[3]:49 0.00155899 +50 chanx_right_in[3]:50 0.0005190577 +51 chanx_right_in[3]:51 5.727384e-05 +52 chanx_right_in[3]:52 4.110931e-05 +53 chanx_right_in[3]:53 4.507988e-05 +54 chanx_right_in[3]:54 5.396513e-05 +55 chanx_right_in[3]:55 7.791975e-05 +56 chanx_right_in[3]:56 0.0003747014 +57 chanx_right_in[3]:57 0.0003747014 +58 chanx_right_in[3]:58 0.0003557616 +59 chanx_right_in[3]:59 0.0003557616 +60 chanx_right_in[3]:60 4.665357e-05 +61 chanx_right_in[3]:61 9.430335e-05 +62 chanx_right_in[3]:62 0.0001378372 +63 chanx_right_in[3]:63 0.0005515653 +64 chanx_right_in[3]:64 0.0005152278 +65 chanx_right_in[3]:65 4.518433e-05 +66 chanx_right_in[3]:66 0.0007273545 +67 chanx_right_in[3]:67 0.0006561597 +68 chanx_right_in[3]:68 0.0001115772 +69 chanx_right_in[3]:69 0.0001115772 +70 chanx_right_in[3]:70 0.0002550568 +71 chanx_right_in[3]:26 chanx_left_in[1]:11 0.0001511705 +72 chanx_right_in[3]:26 chanx_left_in[1]:52 1.294818e-05 +73 chanx_right_in[3]:25 chanx_left_in[1]:52 0.0001511705 +74 chanx_right_in[3]:25 chanx_left_in[1]:53 1.294818e-05 +75 chanx_right_in[3]:50 chanx_left_in[1]:27 7.785238e-06 +76 chanx_right_in[3]:50 chanx_left_in[1]:29 6.249193e-05 +77 chanx_right_in[3]:50 chanx_left_in[1]:37 2.665043e-07 +78 chanx_right_in[3]:58 chanx_left_in[1]:25 3.17766e-06 +79 chanx_right_in[3]:59 chanx_left_in[1]:26 3.17766e-06 +80 chanx_right_in[3]:35 chanx_left_in[1]:48 2.25526e-08 +81 chanx_right_in[3]:49 chanx_left_in[1]:28 6.249193e-05 +82 chanx_right_in[3]:49 chanx_left_in[1]:30 7.785238e-06 +83 chanx_right_in[3]:49 chanx_left_in[1]:37 2.766132e-07 +84 chanx_right_in[3]:49 chanx_left_in[1]:38 2.665043e-07 +85 chanx_right_in[3]:53 chanx_left_in[1]:30 1.370055e-05 +86 chanx_right_in[3]:52 chanx_left_in[1]:27 1.370055e-05 +87 chanx_right_in[3]:34 chanx_left_in[1]:48 2.25526e-08 +88 chanx_right_in[3]:34 chanx_left_in[1]:49 2.25526e-08 +89 chanx_right_in[3]:44 chanx_left_in[1]:38 2.766132e-07 +90 chanx_right_in[3]:31 chanx_left_in[1]:49 2.25526e-08 +91 chanx_right_in[3]:56 chanx_left_in[7]:20 0.0001090859 +92 chanx_right_in[3]:56 chanx_left_in[7]:21 0.0004047139 +93 chanx_right_in[3]:57 chanx_left_in[7]:15 0.0001090859 +94 chanx_right_in[3]:57 chanx_left_in[7]:20 0.0004047139 +95 chanx_right_in[3]:35 chanx_left_in[7]:32 6.33052e-06 +96 chanx_right_in[3]:42 chanx_left_in[7]:22 1.702129e-06 +97 chanx_right_in[3]:41 chanx_left_in[7]:23 1.702129e-06 +98 chanx_right_in[3]:49 chanx_left_in[7]:20 5.547364e-06 +99 chanx_right_in[3]:49 chanx_left_in[7]:24 4.280742e-06 +100 chanx_right_in[3]:49 chanx_left_in[7]:25 7.101691e-07 +101 chanx_right_in[3]:33 chanx_left_in[7]:31 7.813354e-07 +102 chanx_right_in[3]:34 chanx_left_in[7]:32 3.010564e-06 +103 chanx_right_in[3]:34 chanx_left_in[7]:33 6.33052e-06 +104 chanx_right_in[3]:32 chanx_left_in[7]:30 7.813354e-07 +105 chanx_right_in[3]:44 chanx_left_in[7]:21 5.547364e-06 +106 chanx_right_in[3]:44 chanx_left_in[7]:25 4.280742e-06 +107 chanx_right_in[3]:44 chanx_left_in[7]:26 7.101691e-07 +108 chanx_right_in[3]:30 chanx_left_in[7]:35 9.904388e-06 +109 chanx_right_in[3]:31 chanx_left_in[7]:33 3.010564e-06 +110 chanx_right_in[3]:31 chanx_left_in[7]:34 9.904388e-06 +111 chanx_right_in[3]:56 chanx_left_in[13]:13 0.0003353886 +112 chanx_right_in[3]:56 chanx_left_in[13]:14 0.0003800824 +113 chanx_right_in[3]:57 chanx_left_in[13]:8 0.0003353886 +114 chanx_right_in[3]:57 chanx_left_in[13]:13 0.0003800824 +115 chanx_right_in[3]:49 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.020705e-05 +116 chanx_right_in[3]:49 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.182101e-05 +117 chanx_right_in[3]:44 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.182101e-05 +118 chanx_right_in[3]:44 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.020705e-05 +119 chanx_right_in[3]:37 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.775346e-05 +120 chanx_right_in[3]:38 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.775346e-05 +121 chanx_right_in[3]:36 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.194201e-05 +122 chanx_right_in[3]:37 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.194201e-05 +123 chanx_right_in[3]:63 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.872239e-05 +124 chanx_right_in[3]:64 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.872239e-05 +125 chanx_right_in[3]:15 ropt_net_160:4 0.0001214079 +126 chanx_right_in[3]:14 ropt_net_160:5 0.0001214079 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:70 0.0005150416 +1 chanx_right_in[3]:69 chanx_right_in[3]:68 0.001426339 +2 chanx_right_in[3]:70 chanx_right_in[3]:69 0.00341 +3 chanx_right_in[3]:67 chanx_right_in[3]:66 0.008584822 +4 chanx_right_in[3]:68 chanx_right_in[3]:67 0.0045 +5 chanx_right_in[3]:29 chanx_right_in[3]:28 0.00341 +6 chanx_right_in[3]:28 chanx_right_in[3]:27 0.001512225 +7 chanx_right_in[3]:26 chanx_right_in[3]:25 0.007497768 +8 chanx_right_in[3]:27 chanx_right_in[3]:26 0.00341 +9 chanx_right_in[3]:27 chanx_right_in[3]:22 0.002014733 +10 chanx_right_in[3]:24 chanx_right_in[3]:23 0.0008861608 +11 chanx_right_in[3]:25 chanx_right_in[3]:24 0.0045 +12 chanx_right_in[3]:23 mux_bottom_ipin_9\/mux_l1_in_1_:A0 0.152 +13 chanx_right_in[3]:50 chanx_right_in[3]:49 0.006941965 +14 chanx_right_in[3]:51 chanx_right_in[3]:50 0.0045 +15 chanx_right_in[3]:55 chanx_right_in[3]:54 0.0001911058 +16 chanx_right_in[3]:55 chanx_right_in[3]:51 0.000515625 +17 chanx_right_in[3]:56 chanx_right_in[3]:55 0.00341 +18 chanx_right_in[3]:58 chanx_right_in[3]:57 0.00341 +19 chanx_right_in[3]:57 chanx_right_in[3]:56 0.002015516 +20 chanx_right_in[3]:60 chanx_right_in[3]:59 0.0045 +21 chanx_right_in[3]:59 chanx_right_in[3]:58 0.005069197 +22 chanx_right_in[3]:36 chanx_right_in[3]:35 0.0045 +23 chanx_right_in[3]:35 chanx_right_in[3]:34 0.004513393 +24 chanx_right_in[3]:43 chanx_right_in[3]:42 0.0045 +25 chanx_right_in[3]:43 mux_bottom_ipin_3\/mux_l2_in_1_:A1 0.152 +26 chanx_right_in[3]:42 chanx_right_in[3]:41 0.004776787 +27 chanx_right_in[3]:40 chanx_right_in[3]:39 0.002424107 +28 chanx_right_in[3]:41 chanx_right_in[3]:40 0.0045 +29 chanx_right_in[3]:10 mux_bottom_ipin_7\/mux_l2_in_1_:A1 0.152 +30 chanx_right_in[3]:49 chanx_right_in[3]:48 0.0045 +31 chanx_right_in[3]:49 chanx_right_in[3]:44 0.01355357 +32 chanx_right_in[3]:48 chanx_right_in[3]:47 0.0008303572 +33 chanx_right_in[3]:46 chanx_right_in[3]:45 9.239131e-05 +34 chanx_right_in[3]:47 chanx_right_in[3]:46 0.0045 +35 chanx_right_in[3]:45 mux_bottom_ipin_5\/mux_l1_in_1_:A0 0.152 +36 chanx_right_in[3]:61 mux_bottom_ipin_13\/mux_l1_in_1_:A0 0.152 +37 chanx_right_in[3]:61 chanx_right_in[3]:60 0.0001779891 +38 chanx_right_in[3]:65 mux_bottom_ipin_15\/mux_l2_in_1_:A1 0.152 +39 chanx_right_in[3]:53 chanx_right_in[3]:52 0.0001576087 +40 chanx_right_in[3]:54 chanx_right_in[3]:53 0.0045 +41 chanx_right_in[3]:52 mux_bottom_ipin_1\/mux_l1_in_1_:A0 0.152 +42 chanx_right_in[3]:22 chanx_right_in[3]:21 0.00341 +43 chanx_right_in[3]:21 chanx_right_in[3]:20 0.005324317 +44 chanx_right_in[3]:19 chanx_right_in[3]:18 0.0002118916 +45 chanx_right_in[3]:20 chanx_right_in[3]:19 0.00341 +46 chanx_right_in[3]:17 chanx_right_in[3]:16 0.001122768 +47 chanx_right_in[3]:18 chanx_right_in[3]:17 0.00341 +48 chanx_right_in[3]:15 chanx_right_in[3]:14 0.004026785 +49 chanx_right_in[3]:16 chanx_right_in[3]:15 0.0045 +50 chanx_right_in[3]:14 chanx_right_in[3]:13 0.0045 +51 chanx_right_in[3]:13 chanx_right_in[3]:12 0.002348214 +52 chanx_right_in[3]:11 FTB_24__23:A 0.152 +53 chanx_right_in[3]:12 chanx_right_in[3]:11 0.0045 +54 chanx_right_in[3]:33 chanx_right_in[3]:32 0.001654018 +55 chanx_right_in[3]:34 chanx_right_in[3]:33 0.0045 +56 chanx_right_in[3]:34 chanx_right_in[3]:31 0.0009107143 +57 chanx_right_in[3]:32 mux_bottom_ipin_11\/mux_l2_in_1_:A1 0.152 +58 chanx_right_in[3]:37 chanx_right_in[3]:36 0.002834822 +59 chanx_right_in[3]:37 chanx_right_in[3]:10 0.0001766304 +60 chanx_right_in[3]:38 chanx_right_in[3]:37 0.007803572 +61 chanx_right_in[3]:39 chanx_right_in[3]:38 0.0003035715 +62 chanx_right_in[3]:44 chanx_right_in[3]:43 0.0003035715 +63 chanx_right_in[3]:62 chanx_right_in[3]:61 0.0009397322 +64 chanx_right_in[3]:63 chanx_right_in[3]:62 0.0009107144 +65 chanx_right_in[3]:64 chanx_right_in[3]:63 0.006571429 +66 chanx_right_in[3]:66 chanx_right_in[3]:65 0.0004620536 +67 chanx_right_in[3]:66 chanx_right_in[3]:64 0.0003035715 +68 chanx_right_in[3]:30 chanx_right_in[3]:29 0.00602009 +69 chanx_right_in[3]:31 chanx_right_in[3]:30 0.001232143 + +*END + +*D_NET chanx_right_in[7] 0.01496019 //LENGTH 112.555 LUMPCC 0.0003139147 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 103.650 48.960 +*I FTB_28__27:A I *L 0.001776 *C 10.120 44.880 +*I mux_bottom_ipin_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 39.200 50.660 +*I mux_bottom_ipin_11\/mux_l2_in_2_:A1 I *L 0.00198 *C 36.705 47.260 +*I mux_bottom_ipin_13\/mux_l1_in_2_:A0 I *L 0.001631 *C 77.110 49.980 +*N chanx_right_in[7]:5 *C 77.110 49.980 +*N chanx_right_in[7]:6 *C 36.742 47.260 +*N chanx_right_in[7]:7 *C 39.163 50.660 +*N chanx_right_in[7]:8 *C 38.180 50.660 +*N chanx_right_in[7]:9 *C 10.143 44.907 +*N chanx_right_in[7]:10 *C 10.155 45.220 +*N chanx_right_in[7]:11 *C 13.755 45.220 +*N chanx_right_in[7]:12 *C 13.800 45.265 +*N chanx_right_in[7]:13 *C 13.800 49.935 +*N chanx_right_in[7]:14 *C 13.845 49.980 +*N chanx_right_in[7]:15 *C 38.180 50.010 +*N chanx_right_in[7]:16 *C 38.180 49.935 +*N chanx_right_in[7]:17 *C 38.180 47.305 +*N chanx_right_in[7]:18 *C 38.180 47.230 +*N chanx_right_in[7]:19 *C 38.180 46.920 +*N chanx_right_in[7]:20 *C 77.235 46.920 +*N chanx_right_in[7]:21 *C 77.280 46.965 +*N chanx_right_in[7]:22 *C 77.280 49.595 +*N chanx_right_in[7]:23 *C 77.280 49.640 +*N chanx_right_in[7]:24 *C 90.575 49.640 +*N chanx_right_in[7]:25 *C 90.620 49.595 +*N chanx_right_in[7]:26 *C 90.620 49.018 +*N chanx_right_in[7]:27 *C 90.627 48.960 + +*CAP +0 chanx_right_in[7] 0.001016643 +1 FTB_28__27:A 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_11\/mux_l2_in_2_:A1 1e-06 +4 mux_bottom_ipin_13\/mux_l1_in_2_:A0 1e-06 +5 chanx_right_in[7]:5 7.074414e-05 +6 chanx_right_in[7]:6 0.0001267857 +7 chanx_right_in[7]:7 9.720295e-05 +8 chanx_right_in[7]:8 0.0001435559 +9 chanx_right_in[7]:9 3.437795e-05 +10 chanx_right_in[7]:10 0.0002252417 +11 chanx_right_in[7]:11 0.0001908637 +12 chanx_right_in[7]:12 0.0002873335 +13 chanx_right_in[7]:13 0.0002873335 +14 chanx_right_in[7]:14 0.001529108 +15 chanx_right_in[7]:15 0.001575461 +16 chanx_right_in[7]:16 0.0001972905 +17 chanx_right_in[7]:17 0.0001972905 +18 chanx_right_in[7]:18 0.0001569007 +19 chanx_right_in[7]:19 0.002604528 +20 chanx_right_in[7]:20 0.002574413 +21 chanx_right_in[7]:21 0.0001654133 +22 chanx_right_in[7]:22 0.0001654133 +23 chanx_right_in[7]:23 0.0009423703 +24 chanx_right_in[7]:24 0.0009049249 +25 chanx_right_in[7]:25 6.621795e-05 +26 chanx_right_in[7]:26 6.621795e-05 +27 chanx_right_in[7]:27 0.001016643 +28 chanx_right_in[7]:20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001061248 +29 chanx_right_in[7]:19 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001061248 +30 chanx_right_in[7]:11 ropt_net_168:2 2.786096e-05 +31 chanx_right_in[7]:11 ropt_net_168:5 2.297156e-05 +32 chanx_right_in[7]:10 ropt_net_168:3 2.786096e-05 +33 chanx_right_in[7]:10 ropt_net_168:6 2.297156e-05 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:27 0.002040192 +1 chanx_right_in[7]:14 chanx_right_in[7]:13 0.0045 +2 chanx_right_in[7]:13 chanx_right_in[7]:12 0.004169643 +3 chanx_right_in[7]:11 chanx_right_in[7]:10 0.003214286 +4 chanx_right_in[7]:12 chanx_right_in[7]:11 0.0045 +5 chanx_right_in[7]:9 FTB_28__27:A 0.152 +6 chanx_right_in[7]:18 chanx_right_in[7]:17 0.0045 +7 chanx_right_in[7]:18 chanx_right_in[7]:6 0.001283482 +8 chanx_right_in[7]:17 chanx_right_in[7]:16 0.002348214 +9 chanx_right_in[7]:15 chanx_right_in[7]:14 0.02172768 +10 chanx_right_in[7]:15 chanx_right_in[7]:8 0.0005803572 +11 chanx_right_in[7]:16 chanx_right_in[7]:15 0.0045 +12 chanx_right_in[7]:24 chanx_right_in[7]:23 0.01187054 +13 chanx_right_in[7]:25 chanx_right_in[7]:24 0.0045 +14 chanx_right_in[7]:26 chanx_right_in[7]:25 0.000515625 +15 chanx_right_in[7]:27 chanx_right_in[7]:26 0.00341 +16 chanx_right_in[7]:5 mux_bottom_ipin_13\/mux_l1_in_2_:A0 0.152 +17 chanx_right_in[7]:7 mux_bottom_ipin_3\/mux_l2_in_2_:A1 0.152 +18 chanx_right_in[7]:6 mux_bottom_ipin_11\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[7]:20 chanx_right_in[7]:19 0.03487054 +20 chanx_right_in[7]:21 chanx_right_in[7]:20 0.0045 +21 chanx_right_in[7]:23 chanx_right_in[7]:22 0.0045 +22 chanx_right_in[7]:23 chanx_right_in[7]:5 0.0001847826 +23 chanx_right_in[7]:22 chanx_right_in[7]:21 0.002348214 +24 chanx_right_in[7]:10 chanx_right_in[7]:9 0.0002111487 +25 chanx_right_in[7]:19 chanx_right_in[7]:18 0.0002767857 +26 chanx_right_in[7]:8 chanx_right_in[7]:7 0.0008772322 + +*END + +*D_NET chanx_right_in[10] 0.01746155 //LENGTH 117.870 LUMPCC 0.007441566 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 103.650 20.400 +*I mux_top_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 84.740 18.020 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 84.085 25.500 +*I mux_bottom_ipin_14\/mux_l2_in_2_:A1 I *L 0.00198 *C 75.080 18.020 +*I mux_bottom_ipin_6\/mux_l2_in_2_:A1 I *L 0.00198 *C 48.300 20.060 +*I BUFT_RR_68:A I *L 0.001767 *C 6.900 20.400 +*N chanx_right_in[10]:6 *C 6.900 20.400 +*N chanx_right_in[10]:7 *C 6.900 20.355 +*N chanx_right_in[10]:8 *C 6.900 19.777 +*N chanx_right_in[10]:9 *C 6.908 19.720 +*N chanx_right_in[10]:10 *C 48.263 20.060 +*N chanx_right_in[10]:11 *C 47.885 20.060 +*N chanx_right_in[10]:12 *C 47.840 20.060 +*N chanx_right_in[10]:13 *C 47.840 19.720 +*N chanx_right_in[10]:14 *C 47.840 19.720 +*N chanx_right_in[10]:15 *C 75.043 18.020 +*N chanx_right_in[10]:16 *C 73.185 18.020 +*N chanx_right_in[10]:17 *C 73.140 18.065 +*N chanx_right_in[10]:18 *C 73.140 19.663 +*N chanx_right_in[10]:19 *C 73.140 19.720 +*N chanx_right_in[10]:20 *C 84.047 25.500 +*N chanx_right_in[10]:21 *C 83.305 25.500 +*N chanx_right_in[10]:22 *C 83.260 25.455 +*N chanx_right_in[10]:23 *C 84.703 18.020 +*N chanx_right_in[10]:24 *C 83.305 18.020 +*N chanx_right_in[10]:25 *C 83.260 18.020 +*N chanx_right_in[10]:26 *C 83.260 18.418 +*N chanx_right_in[10]:27 *C 83.263 18.360 +*N chanx_right_in[10]:28 *C 83.705 18.360 +*N chanx_right_in[10]:29 *C 83.720 18.367 +*N chanx_right_in[10]:30 *C 83.720 19.713 +*N chanx_right_in[10]:31 *C 83.720 19.725 +*N chanx_right_in[10]:32 *C 83.720 20.400 + +*CAP +0 chanx_right_in[10] 0.0008416051 +1 mux_top_ipin_0\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_14\/mux_l2_in_2_:A1 1e-06 +4 mux_bottom_ipin_6\/mux_l2_in_2_:A1 1e-06 +5 BUFT_RR_68:A 1e-06 +6 chanx_right_in[10]:6 3.869111e-05 +7 chanx_right_in[10]:7 5.63769e-05 +8 chanx_right_in[10]:8 5.63769e-05 +9 chanx_right_in[10]:9 0.00138419 +10 chanx_right_in[10]:10 5.402468e-05 +11 chanx_right_in[10]:11 5.402468e-05 +12 chanx_right_in[10]:12 5.404038e-05 +13 chanx_right_in[10]:13 5.836986e-05 +14 chanx_right_in[10]:14 0.002267331 +15 chanx_right_in[10]:15 0.0001300177 +16 chanx_right_in[10]:16 0.0001300177 +17 chanx_right_in[10]:17 0.0001121754 +18 chanx_right_in[10]:18 0.0001121754 +19 chanx_right_in[10]:19 0.001498505 +20 chanx_right_in[10]:20 7.168385e-05 +21 chanx_right_in[10]:21 7.168385e-05 +22 chanx_right_in[10]:22 0.0004692182 +23 chanx_right_in[10]:23 0.00010075 +24 chanx_right_in[10]:24 0.00010075 +25 chanx_right_in[10]:25 5.711829e-05 +26 chanx_right_in[10]:26 0.000492865 +27 chanx_right_in[10]:27 1.293713e-05 +28 chanx_right_in[10]:28 1.293713e-05 +29 chanx_right_in[10]:29 0.0001027008 +30 chanx_right_in[10]:30 0.0001027008 +31 chanx_right_in[10]:31 0.0006727377 +32 chanx_right_in[10]:32 0.0008989799 +33 chanx_right_in[10]:12 chanx_left_in[18]:21 3.406634e-06 +34 chanx_right_in[10]:13 chanx_left_in[18]:22 3.406634e-06 +35 chanx_right_in[10]:14 chanx_left_in[18]:23 0.001396447 +36 chanx_right_in[10]:14 chanx_left_in[18]:24 1.611096e-05 +37 chanx_right_in[10]:14 chanx_left_in[18]:27 0.0001456369 +38 chanx_right_in[10]:8 chanx_left_in[18]:25 4.218525e-07 +39 chanx_right_in[10]:8 chanx_left_in[18]:26 7.803052e-08 +40 chanx_right_in[10]:9 chanx_left_in[18] 0.0001456369 +41 chanx_right_in[10]:9 chanx_left_in[18]:24 0.0008420149 +42 chanx_right_in[10]:7 chanx_left_in[18]:7 7.803052e-08 +43 chanx_right_in[10]:7 chanx_left_in[18]:26 4.218525e-07 +44 chanx_right_in[10]:31 chanx_left_in[18]:19 3.001518e-05 +45 chanx_right_in[10]:18 chanx_left_in[18]:18 5.033507e-07 +46 chanx_right_in[10]:19 chanx_left_in[18]:19 0.0005544325 +47 chanx_right_in[10]:19 chanx_left_in[18]:23 4.612614e-05 +48 chanx_right_in[10]:16 chanx_left_in[18]:15 4.15837e-06 +49 chanx_right_in[10]:17 chanx_left_in[18]:17 5.033507e-07 +50 chanx_right_in[10]:15 chanx_left_in[18]:16 4.15837e-06 +51 chanx_right_in[10] chanx_right_in[2] 1.150423e-06 +52 chanx_right_in[10] chanx_right_in[2]:49 0.0005054926 +53 chanx_right_in[10]:14 chanx_right_in[2]:39 0.0001832085 +54 chanx_right_in[10]:8 chanx_right_in[2]:22 3.829356e-06 +55 chanx_right_in[10]:7 chanx_right_in[2]:23 3.829356e-06 +56 chanx_right_in[10]:31 chanx_right_in[2]:49 3.392128e-05 +57 chanx_right_in[10]:28 chanx_right_in[2]:49 1.45258e-06 +58 chanx_right_in[10]:26 chanx_right_in[2]:45 2.232025e-06 +59 chanx_right_in[10]:26 chanx_right_in[2]:47 8.2605e-06 +60 chanx_right_in[10]:27 chanx_right_in[2]:48 1.45258e-06 +61 chanx_right_in[10]:22 chanx_right_in[2]:12 2.232025e-06 +62 chanx_right_in[10]:22 chanx_right_in[2]:46 8.2605e-06 +63 chanx_right_in[10]:19 chanx_right_in[2]:40 0.0001832085 +64 chanx_right_in[10]:19 chanx_right_in[2]:48 3.392128e-05 +65 chanx_right_in[10]:32 chanx_right_in[2]:48 0.0005054926 +66 chanx_right_in[10]:32 chanx_right_in[2]:62 1.150423e-06 +67 chanx_right_in[10]:14 chanx_right_in[6]:21 0.0005246402 +68 chanx_right_in[10]:14 chanx_right_in[6]:22 0.0004947225 +69 chanx_right_in[10]:9 chanx_right_in[6]:12 0.0003047676 +70 chanx_right_in[10]:9 chanx_right_in[6]:21 0.0004947225 +71 chanx_right_in[10]:19 chanx_right_in[6]:22 0.0002198727 +72 chanx_right_in[10] chanx_right_in[14] 0.0002035591 +73 chanx_right_in[10]:14 chanx_right_in[14]:31 2.460818e-06 +74 chanx_right_in[10]:8 chanx_right_in[14]:8 6.708814e-07 +75 chanx_right_in[10]:7 chanx_right_in[14]:7 6.708814e-07 +76 chanx_right_in[10]:31 chanx_right_in[14] 0.0001103834 +77 chanx_right_in[10]:28 chanx_right_in[14] 4.802057e-05 +78 chanx_right_in[10]:27 chanx_right_in[14]:31 4.802057e-05 +79 chanx_right_in[10]:19 chanx_right_in[14] 2.460818e-06 +80 chanx_right_in[10]:19 chanx_right_in[14]:31 0.0001103834 +81 chanx_right_in[10]:32 chanx_right_in[14]:31 0.0002035591 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:32 0.003122366 +1 chanx_right_in[10]:10 mux_bottom_ipin_6\/mux_l2_in_2_:A1 0.152 +2 chanx_right_in[10]:11 chanx_right_in[10]:10 0.0003370536 +3 chanx_right_in[10]:12 chanx_right_in[10]:11 0.0045 +4 chanx_right_in[10]:13 chanx_right_in[10]:12 0.0001634615 +5 chanx_right_in[10]:14 chanx_right_in[10]:13 0.00341 +6 chanx_right_in[10]:14 chanx_right_in[10]:9 0.006412758 +7 chanx_right_in[10]:8 chanx_right_in[10]:7 0.000515625 +8 chanx_right_in[10]:9 chanx_right_in[10]:8 0.00341 +9 chanx_right_in[10]:6 BUFT_RR_68:A 0.152 +10 chanx_right_in[10]:7 chanx_right_in[10]:6 0.0045 +11 chanx_right_in[10]:31 chanx_right_in[10]:30 0.00341 +12 chanx_right_in[10]:31 chanx_right_in[10]:19 0.001657533 +13 chanx_right_in[10]:30 chanx_right_in[10]:29 0.0002107167 +14 chanx_right_in[10]:28 chanx_right_in[10]:27 6.499219e-05 +15 chanx_right_in[10]:29 chanx_right_in[10]:28 0.00341 +16 chanx_right_in[10]:26 chanx_right_in[10]:25 0.0001911058 +17 chanx_right_in[10]:26 chanx_right_in[10]:22 0.006283483 +18 chanx_right_in[10]:27 chanx_right_in[10]:26 0.00341 +19 chanx_right_in[10]:24 chanx_right_in[10]:23 0.001247768 +20 chanx_right_in[10]:25 chanx_right_in[10]:24 0.0045 +21 chanx_right_in[10]:23 mux_top_ipin_0\/mux_l2_in_2_:A1 0.152 +22 chanx_right_in[10]:21 chanx_right_in[10]:20 0.0006629464 +23 chanx_right_in[10]:22 chanx_right_in[10]:21 0.0045 +24 chanx_right_in[10]:20 mux_bottom_ipin_0\/mux_l2_in_2_:A1 0.152 +25 chanx_right_in[10]:18 chanx_right_in[10]:17 0.001426339 +26 chanx_right_in[10]:19 chanx_right_in[10]:18 0.00341 +27 chanx_right_in[10]:19 chanx_right_in[10]:14 0.003963667 +28 chanx_right_in[10]:16 chanx_right_in[10]:15 0.001658482 +29 chanx_right_in[10]:17 chanx_right_in[10]:16 0.0045 +30 chanx_right_in[10]:15 mux_bottom_ipin_14\/mux_l2_in_2_:A1 0.152 +31 chanx_right_in[10]:32 chanx_right_in[10]:31 0.00010575 + +*END + +*D_NET chanx_right_in[16] 0.01978684 //LENGTH 155.545 LUMPCC 0.002322393 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 103.650 31.280 +*I mux_top_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 85.560 20.060 +*I ropt_mt_inst_719:A I *L 0.001767 *C 3.220 6.800 +*I mux_bottom_ipin_12\/mux_l2_in_3_:A1 I *L 0.00198 *C 67.065 28.900 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 85.100 28.900 +*N chanx_right_in[16]:5 *C 85.062 28.900 +*N chanx_right_in[16]:6 *C 81.420 28.900 +*N chanx_right_in[16]:7 *C 67.103 28.900 +*N chanx_right_in[16]:8 *C 67.620 28.900 +*N chanx_right_in[16]:9 *C 67.620 29.240 +*N chanx_right_in[16]:10 *C 3.258 6.800 +*N chanx_right_in[16]:11 *C 6.395 6.800 +*N chanx_right_in[16]:12 *C 6.440 6.755 +*N chanx_right_in[16]:13 *C 6.440 4.805 +*N chanx_right_in[16]:14 *C 6.485 4.760 +*N chanx_right_in[16]:15 *C 56.280 4.760 +*N chanx_right_in[16]:16 *C 79.995 4.760 +*N chanx_right_in[16]:17 *C 80.040 4.805 +*N chanx_right_in[16]:18 *C 85.523 20.060 +*N chanx_right_in[16]:19 *C 85.100 20.060 +*N chanx_right_in[16]:20 *C 85.100 19.720 +*N chanx_right_in[16]:21 *C 80.085 19.720 +*N chanx_right_in[16]:22 *C 80.040 19.720 +*N chanx_right_in[16]:23 *C 80.040 29.195 +*N chanx_right_in[16]:24 *C 80.040 29.240 +*N chanx_right_in[16]:25 *C 81.420 29.210 +*N chanx_right_in[16]:26 *C 81.420 29.285 +*N chanx_right_in[16]:27 *C 81.420 31.223 +*N chanx_right_in[16]:28 *C 81.428 31.280 + +*CAP +0 chanx_right_in[16] 0.001643272 +1 mux_top_ipin_0\/mux_l2_in_3_:A1 1e-06 +2 ropt_mt_inst_719:A 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_3_:A1 1e-06 +4 mux_bottom_ipin_0\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[16]:5 0.0002238681 +6 chanx_right_in[16]:6 0.0002541968 +7 chanx_right_in[16]:7 5.091092e-05 +8 chanx_right_in[16]:8 7.493031e-05 +9 chanx_right_in[16]:9 0.0007656132 +10 chanx_right_in[16]:10 0.0001431876 +11 chanx_right_in[16]:11 0.0001431876 +12 chanx_right_in[16]:12 0.0001217905 +13 chanx_right_in[16]:13 0.0001217905 +14 chanx_right_in[16]:14 0.002823895 +15 chanx_right_in[16]:15 0.004061978 +16 chanx_right_in[16]:16 0.001238083 +17 chanx_right_in[16]:17 0.0005039698 +18 chanx_right_in[16]:18 5.36221e-05 +19 chanx_right_in[16]:19 8.053921e-05 +20 chanx_right_in[16]:20 0.0003471507 +21 chanx_right_in[16]:21 0.0003202336 +22 chanx_right_in[16]:22 0.001042046 +23 chanx_right_in[16]:23 0.0005046595 +24 chanx_right_in[16]:24 0.0008843339 +25 chanx_right_in[16]:25 0.0001383666 +26 chanx_right_in[16]:26 0.0001377749 +27 chanx_right_in[16]:27 0.0001377749 +28 chanx_right_in[16]:28 0.001643272 +29 chanx_right_in[16]:22 chanx_left_in[17]:12 1.620767e-05 +30 chanx_right_in[16]:22 chanx_left_in[17]:15 3.896868e-05 +31 chanx_right_in[16]:22 chanx_left_in[17]:16 0.0001997212 +32 chanx_right_in[16]:23 chanx_left_in[17]:16 3.896868e-05 +33 chanx_right_in[16]:17 chanx_left_in[17]:11 1.620767e-05 +34 chanx_right_in[16]:17 chanx_left_in[17]:15 0.0001997212 +35 chanx_right_in[16]:16 ropt_net_128:4 8.109705e-05 +36 chanx_right_in[16]:15 ropt_net_128:3 8.109705e-05 +37 chanx_right_in[16]:22 mux_tree_tapbuf_size10_8_sram[2]:8 0.0002419567 +38 chanx_right_in[16]:17 mux_tree_tapbuf_size10_8_sram[2]:7 0.0002419567 +39 chanx_right_in[16]:7 optlc_net_108:24 3.210409e-06 +40 chanx_right_in[16]:21 optlc_net_108:16 3.657068e-05 +41 chanx_right_in[16]:18 optlc_net_108:17 1.318892e-06 +42 chanx_right_in[16]:25 optlc_net_108:21 9.61067e-06 +43 chanx_right_in[16]:24 optlc_net_108:22 9.61067e-06 +44 chanx_right_in[16]:24 optlc_net_108:41 1.774117e-05 +45 chanx_right_in[16]:24 optlc_net_108:21 6.126802e-05 +46 chanx_right_in[16]:5 optlc_net_108:21 0.0001420195 +47 chanx_right_in[16]:8 optlc_net_108:41 3.210409e-06 +48 chanx_right_in[16]:9 optlc_net_108:22 6.126802e-05 +49 chanx_right_in[16]:9 optlc_net_108:24 1.774117e-05 +50 chanx_right_in[16]:20 optlc_net_108:17 3.657068e-05 +51 chanx_right_in[16]:6 optlc_net_108:22 0.0001420195 +52 chanx_right_in[16]:19 optlc_net_108:16 1.318892e-06 +53 chanx_right_in[16]:22 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.498727e-05 +54 chanx_right_in[16]:26 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.888104e-07 +55 chanx_right_in[16]:27 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.888104e-07 +56 chanx_right_in[16]:23 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.498727e-05 +57 chanx_right_in[16]:14 ropt_net_124:3 4.673017e-05 +58 chanx_right_in[16]:15 ropt_net_124:4 4.673017e-05 +59 chanx_right_in[16]:16 mem_top_ipin_0/net_net_72:3 0.0001444723 +60 chanx_right_in[16]:15 mem_top_ipin_0/net_net_72:2 0.0001444723 +61 chanx_right_in[16]:11 ropt_net_111:6 6.442718e-05 +62 chanx_right_in[16]:10 ropt_net_111:5 6.442718e-05 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:28 0.003481525 +1 chanx_right_in[16]:7 mux_bottom_ipin_12\/mux_l2_in_3_:A1 0.152 +2 chanx_right_in[16]:21 chanx_right_in[16]:20 0.004477679 +3 chanx_right_in[16]:22 chanx_right_in[16]:21 0.0045 +4 chanx_right_in[16]:22 chanx_right_in[16]:17 0.01331696 +5 chanx_right_in[16]:18 mux_top_ipin_0\/mux_l2_in_3_:A1 0.152 +6 chanx_right_in[16]:25 chanx_right_in[16]:24 0.001232143 +7 chanx_right_in[16]:25 chanx_right_in[16]:6 0.0002767857 +8 chanx_right_in[16]:26 chanx_right_in[16]:25 0.0045 +9 chanx_right_in[16]:27 chanx_right_in[16]:26 0.001729911 +10 chanx_right_in[16]:28 chanx_right_in[16]:27 0.00341 +11 chanx_right_in[16]:24 chanx_right_in[16]:23 0.0045 +12 chanx_right_in[16]:24 chanx_right_in[16]:9 0.01108929 +13 chanx_right_in[16]:23 chanx_right_in[16]:22 0.008459821 +14 chanx_right_in[16]:16 chanx_right_in[16]:15 0.02117411 +15 chanx_right_in[16]:17 chanx_right_in[16]:16 0.0045 +16 chanx_right_in[16]:14 chanx_right_in[16]:13 0.0045 +17 chanx_right_in[16]:13 chanx_right_in[16]:12 0.001741072 +18 chanx_right_in[16]:11 chanx_right_in[16]:10 0.00280134 +19 chanx_right_in[16]:12 chanx_right_in[16]:11 0.0045 +20 chanx_right_in[16]:10 ropt_mt_inst_719:A 0.152 +21 chanx_right_in[16]:5 mux_bottom_ipin_0\/mux_l2_in_3_:A1 0.152 +22 chanx_right_in[16]:8 chanx_right_in[16]:7 0.0004620536 +23 chanx_right_in[16]:9 chanx_right_in[16]:8 0.0003035715 +24 chanx_right_in[16]:20 chanx_right_in[16]:19 0.0003035715 +25 chanx_right_in[16]:6 chanx_right_in[16]:5 0.003252232 +26 chanx_right_in[16]:19 chanx_right_in[16]:18 0.0003772322 +27 chanx_right_in[16]:15 chanx_right_in[16]:14 0.04445983 + +*END + +*D_NET ccff_head[0] 0.002863618 //LENGTH 26.190 LUMPCC 0.0001966421 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 103.650 55.760 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.935 39.100 +*N ccff_head[0]:2 *C 94.973 39.100 +*N ccff_head[0]:3 *C 98.395 39.100 +*N ccff_head[0]:4 *C 98.440 39.145 +*N ccff_head[0]:5 *C 98.440 55.703 +*N ccff_head[0]:6 *C 98.448 55.760 + +*CAP +0 ccff_head[0] 0.0003120334 +1 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 0.0002301107 +3 ccff_head[0]:3 0.0002301107 +4 ccff_head[0]:4 0.0007908437 +5 ccff_head[0]:5 0.0007908437 +6 ccff_head[0]:6 0.0003120334 +7 ccff_head[0]:4 ropt_net_169:5 9.832104e-05 +8 ccff_head[0]:5 ropt_net_169:4 9.832104e-05 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.0008150583 +1 ccff_head[0]:2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.003055804 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:5 ccff_head[0]:4 0.01478348 +5 ccff_head[0]:6 ccff_head[0]:5 0.00341 + +*END + +*D_NET top_grid_pin_17_[0] 0.001025587 //LENGTH 8.885 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 41.345 72.080 +*P top_grid_pin_17_[0] O *L 0.7423 *C 35.880 74.870 +*N top_grid_pin_17_[0]:2 *C 35.880 72.465 +*N top_grid_pin_17_[0]:3 *C 35.925 72.420 +*N top_grid_pin_17_[0]:4 *C 41.400 72.420 +*N top_grid_pin_17_[0]:5 *C 41.345 72.080 + +*CAP +0 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_17_[0] 0.0001662923 +2 top_grid_pin_17_[0]:2 0.0001662923 +3 top_grid_pin_17_[0]:3 0.000310172 +4 top_grid_pin_17_[0]:4 0.0003339273 +5 top_grid_pin_17_[0]:5 4.790309e-05 + +*RES +0 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_17_[0]:5 0.152 +1 top_grid_pin_17_[0]:5 top_grid_pin_17_[0]:4 0.0003035715 +2 top_grid_pin_17_[0]:3 top_grid_pin_17_[0]:2 0.0045 +3 top_grid_pin_17_[0]:2 top_grid_pin_17_[0] 0.002147322 +4 top_grid_pin_17_[0]:4 top_grid_pin_17_[0]:3 0.004888393 + +*END + +*D_NET top_grid_pin_20_[0] 0.0005390683 //LENGTH 5.330 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 57.560 69.700 +*P top_grid_pin_20_[0] O *L 0.7423 *C 57.500 74.870 +*N top_grid_pin_20_[0]:2 *C 57.500 69.745 +*N top_grid_pin_20_[0]:3 *C 57.500 69.700 + +*CAP +0 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_20_[0] 0.0002543235 +2 top_grid_pin_20_[0]:2 0.0002543235 +3 top_grid_pin_20_[0]:3 2.942138e-05 + +*RES +0 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_20_[0]:3 0.152 +1 top_grid_pin_20_[0]:3 top_grid_pin_20_[0]:2 0.0045 +2 top_grid_pin_20_[0]:2 top_grid_pin_20_[0] 0.004575893 + +*END + +*D_NET top_grid_pin_22_[0] 0.0006383559 //LENGTH 5.575 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 33.065 69.700 +*P top_grid_pin_22_[0] O *L 0.7423 *C 33.120 74.870 +*N top_grid_pin_22_[0]:2 *C 33.120 70.085 +*N top_grid_pin_22_[0]:3 *C 33.120 70.040 +*N top_grid_pin_22_[0]:4 *C 33.065 69.700 + +*CAP +0 mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_22_[0] 0.0002564325 +2 top_grid_pin_22_[0]:2 0.0002564325 +3 top_grid_pin_22_[0]:3 6.438805e-05 +4 top_grid_pin_22_[0]:4 6.010298e-05 + +*RES +0 mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_22_[0]:4 0.152 +1 top_grid_pin_22_[0]:4 top_grid_pin_22_[0]:3 0.00017 +2 top_grid_pin_22_[0]:3 top_grid_pin_22_[0]:2 0.0045 +3 top_grid_pin_22_[0]:2 top_grid_pin_22_[0] 0.004272321 + +*END + +*D_NET top_grid_pin_26_[0] 0.0005183303 //LENGTH 4.460 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 14.205 71.740 +*P top_grid_pin_26_[0] O *L 0.7423 *C 13.340 74.870 +*N top_grid_pin_26_[0]:2 *C 13.340 71.785 +*N top_grid_pin_26_[0]:3 *C 13.385 71.740 +*N top_grid_pin_26_[0]:4 *C 14.168 71.740 + +*CAP +0 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_26_[0] 0.0001822031 +2 top_grid_pin_26_[0]:2 0.0001822031 +3 top_grid_pin_26_[0]:3 7.646206e-05 +4 top_grid_pin_26_[0]:4 7.646206e-05 + +*RES +0 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_26_[0]:4 0.152 +1 top_grid_pin_26_[0]:4 top_grid_pin_26_[0]:3 0.0006986606 +2 top_grid_pin_26_[0]:3 top_grid_pin_26_[0]:2 0.0045 +3 top_grid_pin_26_[0]:2 top_grid_pin_26_[0] 0.002754464 + +*END + +*D_NET bottom_grid_pin_0_[0] 0.001329612 //LENGTH 11.795 LUMPCC 0 DR + +*CONN +*I mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 92.000 6.800 +*P bottom_grid_pin_0_[0] O *L 0.7423 *C 97.520 1.325 +*N bottom_grid_pin_0_[0]:2 *C 97.520 4.715 +*N bottom_grid_pin_0_[0]:3 *C 97.475 4.760 +*N bottom_grid_pin_0_[0]:4 *C 92.045 4.760 +*N bottom_grid_pin_0_[0]:5 *C 92.000 4.805 +*N bottom_grid_pin_0_[0]:6 *C 92.000 6.755 +*N bottom_grid_pin_0_[0]:7 *C 92.000 6.800 + +*CAP +0 mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 bottom_grid_pin_0_[0] 0.0001856701 +2 bottom_grid_pin_0_[0]:2 0.0001856701 +3 bottom_grid_pin_0_[0]:3 0.0003533231 +4 bottom_grid_pin_0_[0]:4 0.0003533231 +5 bottom_grid_pin_0_[0]:5 0.0001109135 +6 bottom_grid_pin_0_[0]:6 0.0001109135 +7 bottom_grid_pin_0_[0]:7 2.879852e-05 + +*RES +0 mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X bottom_grid_pin_0_[0]:7 0.152 +1 bottom_grid_pin_0_[0]:3 bottom_grid_pin_0_[0]:2 0.0045 +2 bottom_grid_pin_0_[0]:2 bottom_grid_pin_0_[0] 0.003026786 +3 bottom_grid_pin_0_[0]:4 bottom_grid_pin_0_[0]:3 0.004848214 +4 bottom_grid_pin_0_[0]:5 bottom_grid_pin_0_[0]:4 0.0045 +5 bottom_grid_pin_0_[0]:7 bottom_grid_pin_0_[0]:6 0.0045 +6 bottom_grid_pin_0_[0]:6 bottom_grid_pin_0_[0]:5 0.001741071 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.006425787 //LENGTH 47.445 LUMPCC 0.000780725 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 79.425 44.880 +*I mux_bottom_ipin_1\/mux_l1_in_0_:S I *L 0.00357 *C 65.420 57.725 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 59.965 64.260 +*I mux_bottom_ipin_1\/mux_l1_in_2_:S I *L 0.00357 *C 61.280 58.190 +*I mux_bottom_ipin_1\/mux_l1_in_1_:S I *L 0.00357 *C 68.180 53.040 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 68.080 53.040 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 68.080 52.995 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 61.280 58.190 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 60.003 64.260 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 60.675 64.260 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 60.720 64.215 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 60.720 57.845 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 60.765 57.800 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 61.280 57.800 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 65.333 57.785 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 65.320 57.755 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 65.320 47.645 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 65.365 47.600 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 68.035 47.600 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 68.080 47.600 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 68.080 45.617 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 68.088 45.560 +*N mux_tree_tapbuf_size10_1_sram[0]:22 *C 79.112 45.560 +*N mux_tree_tapbuf_size10_1_sram[0]:23 *C 79.120 45.503 +*N mux_tree_tapbuf_size10_1_sram[0]:24 *C 79.120 44.925 +*N mux_tree_tapbuf_size10_1_sram[0]:25 *C 79.120 44.880 +*N mux_tree_tapbuf_size10_1_sram[0]:26 *C 79.425 44.880 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_ipin_1\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_ipin_1\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 3.177776e-05 +6 mux_tree_tapbuf_size10_1_sram[0]:6 0.0002806827 +7 mux_tree_tapbuf_size10_1_sram[0]:7 6.031038e-05 +8 mux_tree_tapbuf_size10_1_sram[0]:8 6.97954e-05 +9 mux_tree_tapbuf_size10_1_sram[0]:9 6.97954e-05 +10 mux_tree_tapbuf_size10_1_sram[0]:10 0.0003720892 +11 mux_tree_tapbuf_size10_1_sram[0]:11 0.0003720892 +12 mux_tree_tapbuf_size10_1_sram[0]:12 4.954495e-05 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0003394205 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.0002583944 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0005602617 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0005602617 +17 mux_tree_tapbuf_size10_1_sram[0]:17 0.0001938568 +18 mux_tree_tapbuf_size10_1_sram[0]:18 0.0001938568 +19 mux_tree_tapbuf_size10_1_sram[0]:19 0.000408536 +20 mux_tree_tapbuf_size10_1_sram[0]:20 9.381548e-05 +21 mux_tree_tapbuf_size10_1_sram[0]:21 0.0007460868 +22 mux_tree_tapbuf_size10_1_sram[0]:22 0.0007460868 +23 mux_tree_tapbuf_size10_1_sram[0]:23 6.510043e-05 +24 mux_tree_tapbuf_size10_1_sram[0]:24 6.510043e-05 +25 mux_tree_tapbuf_size10_1_sram[0]:25 4.879035e-05 +26 mux_tree_tapbuf_size10_1_sram[0]:26 5.440956e-05 +27 mux_tree_tapbuf_size10_1_sram[0]:14 chanx_left_in[5]:21 3.191742e-05 +28 mux_tree_tapbuf_size10_1_sram[0]:15 chanx_left_in[5]:24 2.717679e-05 +29 mux_tree_tapbuf_size10_1_sram[0]:16 chanx_left_in[5]:19 2.717679e-05 +30 mux_tree_tapbuf_size10_1_sram[0]:11 chanx_left_in[5]:23 4.506681e-08 +31 mux_tree_tapbuf_size10_1_sram[0]:10 chanx_left_in[5]:22 4.506681e-08 +32 mux_tree_tapbuf_size10_1_sram[0]:21 chanx_left_in[5]:13 0.0002218074 +33 mux_tree_tapbuf_size10_1_sram[0]:22 chanx_left_in[5]:8 0.0002218074 +34 mux_tree_tapbuf_size10_1_sram[0]:13 chanx_left_in[5]:20 3.191742e-05 +35 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 4.93859e-06 +36 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 4.93859e-06 +37 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 5.677483e-05 +38 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 4.770244e-05 +39 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 4.770244e-05 +40 mux_tree_tapbuf_size10_1_sram[0]:6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 5.677483e-05 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:14 mux_bottom_ipin_1\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:13 0.003618304 +3 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.0045 +4 mux_tree_tapbuf_size10_1_sram[0]:17 mux_tree_tapbuf_size10_1_sram[0]:16 0.0045 +5 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:15 0.009026786 +6 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.002383929 +7 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 0.0045 +8 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:6 0.004816964 +9 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.0056875 +11 mux_tree_tapbuf_size10_1_sram[0]:9 mux_tree_tapbuf_size10_1_sram[0]:8 0.0006004464 +12 mux_tree_tapbuf_size10_1_sram[0]:10 mux_tree_tapbuf_size10_1_sram[0]:9 0.0045 +13 mux_tree_tapbuf_size10_1_sram[0]:8 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.001770089 +15 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.00341 +16 mux_tree_tapbuf_size10_1_sram[0]:23 mux_tree_tapbuf_size10_1_sram[0]:22 0.00341 +17 mux_tree_tapbuf_size10_1_sram[0]:22 mux_tree_tapbuf_size10_1_sram[0]:21 0.00172725 +18 mux_tree_tapbuf_size10_1_sram[0]:25 mux_tree_tapbuf_size10_1_sram[0]:24 0.0045 +19 mux_tree_tapbuf_size10_1_sram[0]:24 mux_tree_tapbuf_size10_1_sram[0]:23 0.000515625 +20 mux_tree_tapbuf_size10_1_sram[0]:26 mux_tree_tapbuf_size10_1_sram[0]:25 0.0001657609 +21 mux_tree_tapbuf_size10_1_sram[0]:7 mux_bottom_ipin_1\/mux_l1_in_2_:S 0.152 +22 mux_tree_tapbuf_size10_1_sram[0]:5 mux_bottom_ipin_1\/mux_l1_in_1_:S 0.152 +23 mux_tree_tapbuf_size10_1_sram[0]:6 mux_tree_tapbuf_size10_1_sram[0]:5 0.0045 +24 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.0004598215 +25 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:7 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[1] 0.005671519 //LENGTH 42.530 LUMPCC 0.0001002591 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.075 44.540 +*I mux_bottom_ipin_5\/mux_l2_in_0_:S I *L 0.00357 *C 57.600 56.055 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 51.695 58.820 +*I mux_bottom_ipin_5\/mux_l2_in_1_:S I *L 0.00357 *C 56.680 50.615 +*I mux_bottom_ipin_5\/mux_l2_in_2_:S I *L 0.00357 *C 56.680 47.600 +*I mux_bottom_ipin_5\/mux_l2_in_3_:S I *L 0.00357 *C 55.320 45.560 +*N mux_tree_tapbuf_size10_3_sram[1]:6 *C 56.680 50.690 +*N mux_tree_tapbuf_size10_3_sram[1]:7 *C 55.358 45.560 +*N mux_tree_tapbuf_size10_3_sram[1]:8 *C 56.535 45.560 +*N mux_tree_tapbuf_size10_3_sram[1]:9 *C 56.580 45.605 +*N mux_tree_tapbuf_size10_3_sram[1]:10 *C 56.580 47.600 +*N mux_tree_tapbuf_size10_3_sram[1]:11 *C 56.580 47.600 +*N mux_tree_tapbuf_size10_3_sram[1]:12 *C 56.580 50.275 +*N mux_tree_tapbuf_size10_3_sram[1]:13 *C 56.580 50.320 +*N mux_tree_tapbuf_size10_3_sram[1]:14 *C 56.680 50.615 +*N mux_tree_tapbuf_size10_3_sram[1]:15 *C 56.680 51.000 +*N mux_tree_tapbuf_size10_3_sram[1]:16 *C 51.695 58.820 +*N mux_tree_tapbuf_size10_3_sram[1]:17 *C 51.520 58.820 +*N mux_tree_tapbuf_size10_3_sram[1]:18 *C 51.520 58.775 +*N mux_tree_tapbuf_size10_3_sram[1]:19 *C 51.520 56.145 +*N mux_tree_tapbuf_size10_3_sram[1]:20 *C 51.565 56.100 +*N mux_tree_tapbuf_size10_3_sram[1]:21 *C 57.638 56.050 +*N mux_tree_tapbuf_size10_3_sram[1]:22 *C 57.658 55.760 +*N mux_tree_tapbuf_size10_3_sram[1]:23 *C 60.215 55.760 +*N mux_tree_tapbuf_size10_3_sram[1]:24 *C 60.260 55.715 +*N mux_tree_tapbuf_size10_3_sram[1]:25 *C 60.260 51.045 +*N mux_tree_tapbuf_size10_3_sram[1]:26 *C 60.260 51.000 +*N mux_tree_tapbuf_size10_3_sram[1]:27 *C 61.595 51.000 +*N mux_tree_tapbuf_size10_3_sram[1]:28 *C 61.640 50.955 +*N mux_tree_tapbuf_size10_3_sram[1]:29 *C 61.640 44.585 +*N mux_tree_tapbuf_size10_3_sram[1]:30 *C 61.685 44.540 +*N mux_tree_tapbuf_size10_3_sram[1]:31 *C 66.038 44.540 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_5\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_5\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_ipin_5\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_3_sram[1]:6 1.375674e-05 +7 mux_tree_tapbuf_size10_3_sram[1]:7 0.0001042832 +8 mux_tree_tapbuf_size10_3_sram[1]:8 0.0001042832 +9 mux_tree_tapbuf_size10_3_sram[1]:9 0.0001245551 +10 mux_tree_tapbuf_size10_3_sram[1]:10 3.160167e-05 +11 mux_tree_tapbuf_size10_3_sram[1]:11 0.0003175254 +12 mux_tree_tapbuf_size10_3_sram[1]:12 0.0001577715 +13 mux_tree_tapbuf_size10_3_sram[1]:13 5.427548e-05 +14 mux_tree_tapbuf_size10_3_sram[1]:14 8.394424e-05 +15 mux_tree_tapbuf_size10_3_sram[1]:15 0.000234213 +16 mux_tree_tapbuf_size10_3_sram[1]:16 5.534718e-05 +17 mux_tree_tapbuf_size10_3_sram[1]:17 5.908965e-05 +18 mux_tree_tapbuf_size10_3_sram[1]:18 0.0001905005 +19 mux_tree_tapbuf_size10_3_sram[1]:19 0.0001905005 +20 mux_tree_tapbuf_size10_3_sram[1]:20 0.000401507 +21 mux_tree_tapbuf_size10_3_sram[1]:21 0.0004289489 +22 mux_tree_tapbuf_size10_3_sram[1]:22 0.0002311829 +23 mux_tree_tapbuf_size10_3_sram[1]:23 0.0002037411 +24 mux_tree_tapbuf_size10_3_sram[1]:24 0.0002917611 +25 mux_tree_tapbuf_size10_3_sram[1]:25 0.0002917611 +26 mux_tree_tapbuf_size10_3_sram[1]:26 0.000348735 +27 mux_tree_tapbuf_size10_3_sram[1]:27 9.87176e-05 +28 mux_tree_tapbuf_size10_3_sram[1]:28 0.0004628298 +29 mux_tree_tapbuf_size10_3_sram[1]:29 0.0004628298 +30 mux_tree_tapbuf_size10_3_sram[1]:30 0.000310799 +31 mux_tree_tapbuf_size10_3_sram[1]:31 0.000310799 +32 mux_tree_tapbuf_size10_3_sram[1]:29 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.686789e-06 +33 mux_tree_tapbuf_size10_3_sram[1]:27 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.286949e-06 +34 mux_tree_tapbuf_size10_3_sram[1]:28 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.686789e-06 +35 mux_tree_tapbuf_size10_3_sram[1]:26 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.660369e-05 +36 mux_tree_tapbuf_size10_3_sram[1]:26 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.286949e-06 +37 mux_tree_tapbuf_size10_3_sram[1]:14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.995722e-06 +38 mux_tree_tapbuf_size10_3_sram[1]:14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.201613e-06 +39 mux_tree_tapbuf_size10_3_sram[1]:11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.547723e-07 +40 mux_tree_tapbuf_size10_3_sram[1]:13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.995722e-06 +41 mux_tree_tapbuf_size10_3_sram[1]:12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.547723e-07 +42 mux_tree_tapbuf_size10_3_sram[1]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.570058e-07 +43 mux_tree_tapbuf_size10_3_sram[1]:15 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.446076e-07 +44 mux_tree_tapbuf_size10_3_sram[1]:15 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.660369e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_3_sram[1]:31 0.152 +1 mux_tree_tapbuf_size10_3_sram[1]:31 mux_tree_tapbuf_size10_3_sram[1]:30 0.00388616 +2 mux_tree_tapbuf_size10_3_sram[1]:30 mux_tree_tapbuf_size10_3_sram[1]:29 0.0045 +3 mux_tree_tapbuf_size10_3_sram[1]:29 mux_tree_tapbuf_size10_3_sram[1]:28 0.005687501 +4 mux_tree_tapbuf_size10_3_sram[1]:27 mux_tree_tapbuf_size10_3_sram[1]:26 0.001191964 +5 mux_tree_tapbuf_size10_3_sram[1]:28 mux_tree_tapbuf_size10_3_sram[1]:27 0.0045 +6 mux_tree_tapbuf_size10_3_sram[1]:7 mux_bottom_ipin_5\/mux_l2_in_3_:S 0.152 +7 mux_tree_tapbuf_size10_3_sram[1]:8 mux_tree_tapbuf_size10_3_sram[1]:7 0.001051339 +8 mux_tree_tapbuf_size10_3_sram[1]:9 mux_tree_tapbuf_size10_3_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size10_3_sram[1]:21 mux_bottom_ipin_5\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_3_sram[1]:21 mux_tree_tapbuf_size10_3_sram[1]:20 0.005421875 +11 mux_tree_tapbuf_size10_3_sram[1]:23 mux_tree_tapbuf_size10_3_sram[1]:22 0.002283482 +12 mux_tree_tapbuf_size10_3_sram[1]:24 mux_tree_tapbuf_size10_3_sram[1]:23 0.0045 +13 mux_tree_tapbuf_size10_3_sram[1]:26 mux_tree_tapbuf_size10_3_sram[1]:25 0.0045 +14 mux_tree_tapbuf_size10_3_sram[1]:26 mux_tree_tapbuf_size10_3_sram[1]:15 0.003196429 +15 mux_tree_tapbuf_size10_3_sram[1]:25 mux_tree_tapbuf_size10_3_sram[1]:24 0.004169643 +16 mux_tree_tapbuf_size10_3_sram[1]:14 mux_bottom_ipin_5\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_3_sram[1]:14 mux_tree_tapbuf_size10_3_sram[1]:13 0.0001715116 +18 mux_tree_tapbuf_size10_3_sram[1]:14 mux_tree_tapbuf_size10_3_sram[1]:6 4.360465e-05 +19 mux_tree_tapbuf_size10_3_sram[1]:20 mux_tree_tapbuf_size10_3_sram[1]:19 0.0045 +20 mux_tree_tapbuf_size10_3_sram[1]:19 mux_tree_tapbuf_size10_3_sram[1]:18 0.002348214 +21 mux_tree_tapbuf_size10_3_sram[1]:17 mux_tree_tapbuf_size10_3_sram[1]:16 9.51087e-05 +22 mux_tree_tapbuf_size10_3_sram[1]:18 mux_tree_tapbuf_size10_3_sram[1]:17 0.0045 +23 mux_tree_tapbuf_size10_3_sram[1]:16 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +24 mux_tree_tapbuf_size10_3_sram[1]:10 mux_bottom_ipin_5\/mux_l2_in_2_:S 0.152 +25 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:10 0.0045 +26 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:9 0.00178125 +27 mux_tree_tapbuf_size10_3_sram[1]:13 mux_tree_tapbuf_size10_3_sram[1]:12 0.0045 +28 mux_tree_tapbuf_size10_3_sram[1]:12 mux_tree_tapbuf_size10_3_sram[1]:11 0.002388393 +29 mux_tree_tapbuf_size10_3_sram[1]:15 mux_tree_tapbuf_size10_3_sram[1]:14 0.00034375 +30 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:21 0.0001686047 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[0] 0.004663631 //LENGTH 33.970 LUMPCC 0.0005748887 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 47.225 36.720 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.935 31.620 +*I mux_bottom_ipin_12\/mux_l1_in_0_:S I *L 0.00357 *C 53.720 29.240 +*I mux_bottom_ipin_12\/mux_l1_in_1_:S I *L 0.00357 *C 58.520 23.120 +*I mux_bottom_ipin_12\/mux_l1_in_2_:S I *L 0.00357 *C 58.780 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:5 *C 58.742 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:6 *C 58.483 23.120 +*N mux_tree_tapbuf_size10_6_sram[0]:7 *C 57.085 23.120 +*N mux_tree_tapbuf_size10_6_sram[0]:8 *C 57.040 23.165 +*N mux_tree_tapbuf_size10_6_sram[0]:9 *C 57.040 25.795 +*N mux_tree_tapbuf_size10_6_sram[0]:10 *C 57.040 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:11 *C 48.805 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:12 *C 48.760 25.885 +*N mux_tree_tapbuf_size10_6_sram[0]:13 *C 53.683 29.240 +*N mux_tree_tapbuf_size10_6_sram[0]:14 *C 48.805 29.240 +*N mux_tree_tapbuf_size10_6_sram[0]:15 *C 48.760 29.240 +*N mux_tree_tapbuf_size10_6_sram[0]:16 *C 48.935 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:17 *C 48.760 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:18 *C 48.760 31.575 +*N mux_tree_tapbuf_size10_6_sram[0]:19 *C 48.300 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:20 *C 48.300 36.675 +*N mux_tree_tapbuf_size10_6_sram[0]:21 *C 48.255 36.720 +*N mux_tree_tapbuf_size10_6_sram[0]:22 *C 47.263 36.720 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_12\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_ipin_12\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_ipin_12\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_6_sram[0]:5 0.0001333449 +6 mux_tree_tapbuf_size10_6_sram[0]:6 0.0001330012 +7 mux_tree_tapbuf_size10_6_sram[0]:7 0.0001330012 +8 mux_tree_tapbuf_size10_6_sram[0]:8 0.0001680112 +9 mux_tree_tapbuf_size10_6_sram[0]:9 0.0001680112 +10 mux_tree_tapbuf_size10_6_sram[0]:10 0.0005706177 +11 mux_tree_tapbuf_size10_6_sram[0]:11 0.0004012425 +12 mux_tree_tapbuf_size10_6_sram[0]:12 0.0001880836 +13 mux_tree_tapbuf_size10_6_sram[0]:13 0.0003610022 +14 mux_tree_tapbuf_size10_6_sram[0]:14 0.0003610022 +15 mux_tree_tapbuf_size10_6_sram[0]:15 0.0003481271 +16 mux_tree_tapbuf_size10_6_sram[0]:16 5.4434e-05 +17 mux_tree_tapbuf_size10_6_sram[0]:17 5.611166e-05 +18 mux_tree_tapbuf_size10_6_sram[0]:18 0.0001581237 +19 mux_tree_tapbuf_size10_6_sram[0]:19 0.0003554073 +20 mux_tree_tapbuf_size10_6_sram[0]:20 0.0003238574 +21 mux_tree_tapbuf_size10_6_sram[0]:21 8.51815e-05 +22 mux_tree_tapbuf_size10_6_sram[0]:22 8.51815e-05 +23 mux_tree_tapbuf_size10_6_sram[0]:20 chanx_left_in[6]:14 6.403086e-07 +24 mux_tree_tapbuf_size10_6_sram[0]:20 chanx_left_in[6]:16 4.625477e-06 +25 mux_tree_tapbuf_size10_6_sram[0]:11 chanx_left_in[6]:18 0.0002073573 +26 mux_tree_tapbuf_size10_6_sram[0]:11 chanx_left_in[6]:26 4.782337e-05 +27 mux_tree_tapbuf_size10_6_sram[0]:12 chanx_left_in[6]:19 2.549316e-07 +28 mux_tree_tapbuf_size10_6_sram[0]:12 chanx_left_in[6]:20 2.313304e-06 +29 mux_tree_tapbuf_size10_6_sram[0]:5 chanx_left_in[6]:17 2.187338e-05 +30 mux_tree_tapbuf_size10_6_sram[0]:10 chanx_left_in[6]:17 0.0002073573 +31 mux_tree_tapbuf_size10_6_sram[0]:10 chanx_left_in[6]:18 2.187338e-05 +32 mux_tree_tapbuf_size10_6_sram[0]:10 chanx_left_in[6]:21 4.782337e-05 +33 mux_tree_tapbuf_size10_6_sram[0]:15 chanx_left_in[6]:16 2.313304e-06 +34 mux_tree_tapbuf_size10_6_sram[0]:15 chanx_left_in[6]:20 2.811262e-06 +35 mux_tree_tapbuf_size10_6_sram[0]:18 chanx_left_in[6]:16 2.556331e-06 +36 mux_tree_tapbuf_size10_6_sram[0]:19 chanx_left_in[6]:15 6.403086e-07 +37 mux_tree_tapbuf_size10_6_sram[0]:19 chanx_left_in[6]:20 4.625477e-06 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_6_sram[0]:22 0.152 +1 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:20 0.0045 +2 mux_tree_tapbuf_size10_6_sram[0]:20 mux_tree_tapbuf_size10_6_sram[0]:19 0.004513393 +3 mux_tree_tapbuf_size10_6_sram[0]:22 mux_tree_tapbuf_size10_6_sram[0]:21 0.0008861608 +4 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:10 0.007352679 +5 mux_tree_tapbuf_size10_6_sram[0]:12 mux_tree_tapbuf_size10_6_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size10_6_sram[0]:5 mux_bottom_ipin_12\/mux_l1_in_2_:S 0.152 +7 mux_tree_tapbuf_size10_6_sram[0]:10 mux_tree_tapbuf_size10_6_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size10_6_sram[0]:10 mux_tree_tapbuf_size10_6_sram[0]:5 0.001520089 +9 mux_tree_tapbuf_size10_6_sram[0]:9 mux_tree_tapbuf_size10_6_sram[0]:8 0.002348214 +10 mux_tree_tapbuf_size10_6_sram[0]:7 mux_tree_tapbuf_size10_6_sram[0]:6 0.001247768 +11 mux_tree_tapbuf_size10_6_sram[0]:8 mux_tree_tapbuf_size10_6_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size10_6_sram[0]:6 mux_bottom_ipin_12\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[0]:14 mux_tree_tapbuf_size10_6_sram[0]:13 0.004354911 +14 mux_tree_tapbuf_size10_6_sram[0]:15 mux_tree_tapbuf_size10_6_sram[0]:14 0.0045 +15 mux_tree_tapbuf_size10_6_sram[0]:15 mux_tree_tapbuf_size10_6_sram[0]:12 0.002995536 +16 mux_tree_tapbuf_size10_6_sram[0]:13 mux_bottom_ipin_12\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size10_6_sram[0]:17 mux_tree_tapbuf_size10_6_sram[0]:16 9.510871e-05 +18 mux_tree_tapbuf_size10_6_sram[0]:18 mux_tree_tapbuf_size10_6_sram[0]:17 0.0045 +19 mux_tree_tapbuf_size10_6_sram[0]:18 mux_tree_tapbuf_size10_6_sram[0]:15 0.002084821 +20 mux_tree_tapbuf_size10_6_sram[0]:16 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +21 mux_tree_tapbuf_size10_6_sram[0]:19 mux_tree_tapbuf_size10_6_sram[0]:18 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_2_ccff_tail[0] 0.002237373 //LENGTH 19.630 LUMPCC 0.0002447967 DR + +*CONN +*I mem_bottom_ipin_4\/FTB_3__42:X O *L 0 *C 54.965 21.080 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 55.835 39.100 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 *C 55.835 39.100 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 *C 55.660 39.100 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 *C 55.660 39.055 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 *C 55.660 21.125 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 *C 55.615 21.080 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 *C 55.003 21.080 + +*CAP +0 mem_bottom_ipin_4\/FTB_3__42:X 1e-06 +1 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 4.780398e-05 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 5.201843e-05 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.0008638521 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0008638521 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 8.152497e-05 +7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 8.152497e-05 +8 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 chanx_left_in[0]:15 2.052841e-05 +9 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 chanx_left_in[0]:42 3.991769e-05 +10 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 chanx_left_in[0]:42 2.052841e-05 +11 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 chanx_left_in[0]:43 3.991769e-05 +12 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size10_2_sram[0]:22 6.195228e-05 +13 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size10_2_sram[0]:23 6.195228e-05 + +*RES +0 mem_bottom_ipin_4\/FTB_3__42:X mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 0.000546875 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.01600893 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[1] 0.004971668 //LENGTH 36.825 LUMPCC 0.0004230229 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.625 15.300 +*I mux_bottom_ipin_2\/mux_l2_in_0_:S I *L 0.00357 *C 39.200 19.720 +*I mux_bottom_ipin_2\/mux_l2_in_2_:S I *L 0.00357 *C 28.420 19.720 +*I mux_bottom_ipin_2\/mux_l2_in_1_:S I *L 0.00357 *C 39.680 23.460 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.835 11.900 +*I mux_bottom_ipin_2\/mux_l2_in_3_:S I *L 0.00357 *C 31.840 14.280 +*N mux_tree_tapbuf_size8_0_sram[1]:6 *C 31.878 14.280 +*N mux_tree_tapbuf_size8_0_sram[1]:7 *C 32.835 11.900 +*N mux_tree_tapbuf_size8_0_sram[1]:8 *C 33.120 11.900 +*N mux_tree_tapbuf_size8_0_sram[1]:9 *C 33.120 11.945 +*N mux_tree_tapbuf_size8_0_sram[1]:10 *C 33.120 14.235 +*N mux_tree_tapbuf_size8_0_sram[1]:11 *C 33.120 14.280 +*N mux_tree_tapbuf_size8_0_sram[1]:12 *C 34.960 14.280 +*N mux_tree_tapbuf_size8_0_sram[1]:13 *C 34.960 15.640 +*N mux_tree_tapbuf_size8_0_sram[1]:14 *C 39.100 15.640 +*N mux_tree_tapbuf_size8_0_sram[1]:15 *C 39.643 23.460 +*N mux_tree_tapbuf_size8_0_sram[1]:16 *C 39.145 23.460 +*N mux_tree_tapbuf_size8_0_sram[1]:17 *C 39.100 23.415 +*N mux_tree_tapbuf_size8_0_sram[1]:18 *C 28.458 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:19 *C 39.113 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:20 *C 39.100 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:21 *C 39.100 15.345 +*N mux_tree_tapbuf_size8_0_sram[1]:22 *C 39.100 15.300 +*N mux_tree_tapbuf_size8_0_sram[1]:23 *C 42.587 15.300 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_ipin_2\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_ipin_2\/mux_l2_in_1_:S 1e-06 +4 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_ipin_2\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_0_sram[1]:6 9.582856e-05 +7 mux_tree_tapbuf_size8_0_sram[1]:7 4.591316e-05 +8 mux_tree_tapbuf_size8_0_sram[1]:8 4.966541e-05 +9 mux_tree_tapbuf_size8_0_sram[1]:9 0.0001445448 +10 mux_tree_tapbuf_size8_0_sram[1]:10 0.0001445448 +11 mux_tree_tapbuf_size8_0_sram[1]:11 0.0002548505 +12 mux_tree_tapbuf_size8_0_sram[1]:12 0.000215082 +13 mux_tree_tapbuf_size8_0_sram[1]:13 0.0003922645 +14 mux_tree_tapbuf_size8_0_sram[1]:14 0.0003318894 +15 mux_tree_tapbuf_size8_0_sram[1]:15 6.549383e-05 +16 mux_tree_tapbuf_size8_0_sram[1]:16 6.549383e-05 +17 mux_tree_tapbuf_size8_0_sram[1]:17 0.0002303695 +18 mux_tree_tapbuf_size8_0_sram[1]:18 0.0006242254 +19 mux_tree_tapbuf_size8_0_sram[1]:19 0.0006242254 +20 mux_tree_tapbuf_size8_0_sram[1]:20 0.0005212086 +21 mux_tree_tapbuf_size8_0_sram[1]:21 0.0002565628 +22 mux_tree_tapbuf_size8_0_sram[1]:22 0.0002535555 +23 mux_tree_tapbuf_size8_0_sram[1]:23 0.0002269268 +24 mux_tree_tapbuf_size8_0_sram[1]:18 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000104567 +25 mux_tree_tapbuf_size8_0_sram[1]:19 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000104567 +26 mux_tree_tapbuf_size8_0_sram[1]:18 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001069445 +27 mux_tree_tapbuf_size8_0_sram[1]:19 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001069445 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_0_sram[1]:23 0.152 +1 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[1]:10 0.0045 +2 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[1]:6 0.001109375 +3 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[1]:9 0.002044643 +4 mux_tree_tapbuf_size8_0_sram[1]:8 mux_tree_tapbuf_size8_0_sram[1]:7 0.0001548913 +5 mux_tree_tapbuf_size8_0_sram[1]:9 mux_tree_tapbuf_size8_0_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size8_0_sram[1]:7 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size8_0_sram[1]:22 0.00311384 +8 mux_tree_tapbuf_size8_0_sram[1]:18 mux_bottom_ipin_2\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size8_0_sram[1]:19 mux_bottom_ipin_2\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:18 0.009513393 +11 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:19 0.0045 +12 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:17 0.003299107 +13 mux_tree_tapbuf_size8_0_sram[1]:6 mux_bottom_ipin_2\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size8_0_sram[1]:15 mux_bottom_ipin_2\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size8_0_sram[1]:16 mux_tree_tapbuf_size8_0_sram[1]:15 0.0004441965 +16 mux_tree_tapbuf_size8_0_sram[1]:17 mux_tree_tapbuf_size8_0_sram[1]:16 0.0045 +17 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:21 0.0045 +18 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:14 0.0003035715 +19 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:20 0.00390625 +20 mux_tree_tapbuf_size8_0_sram[1]:12 mux_tree_tapbuf_size8_0_sram[1]:11 0.001642857 +21 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:12 0.001214286 +22 mux_tree_tapbuf_size8_0_sram[1]:14 mux_tree_tapbuf_size8_0_sram[1]:13 0.003696429 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[1] 0.005407932 //LENGTH 41.220 LUMPCC 0.0004768013 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 43.895 38.760 +*I mux_bottom_ipin_3\/mux_l2_in_3_:S I *L 0.00357 *C 39.920 44.880 +*I mux_bottom_ipin_3\/mux_l2_in_2_:S I *L 0.00357 *C 39.920 51.000 +*I mux_bottom_ipin_3\/mux_l2_in_0_:S I *L 0.00357 *C 42.220 58.190 +*I mux_bottom_ipin_3\/mux_l2_in_1_:S I *L 0.00357 *C 45.180 52.700 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 38.355 60.860 +*N mux_tree_tapbuf_size8_1_sram[1]:6 *C 38.392 60.860 +*N mux_tree_tapbuf_size8_1_sram[1]:7 *C 39.975 60.860 +*N mux_tree_tapbuf_size8_1_sram[1]:8 *C 40.020 60.815 +*N mux_tree_tapbuf_size8_1_sram[1]:9 *C 45.143 52.700 +*N mux_tree_tapbuf_size8_1_sram[1]:10 *C 44.665 52.700 +*N mux_tree_tapbuf_size8_1_sram[1]:11 *C 44.620 52.745 +*N mux_tree_tapbuf_size8_1_sram[1]:12 *C 44.620 58.435 +*N mux_tree_tapbuf_size8_1_sram[1]:13 *C 44.575 58.480 +*N mux_tree_tapbuf_size8_1_sram[1]:14 *C 42.220 58.190 +*N mux_tree_tapbuf_size8_1_sram[1]:15 *C 42.163 58.480 +*N mux_tree_tapbuf_size8_1_sram[1]:16 *C 40.065 58.480 +*N mux_tree_tapbuf_size8_1_sram[1]:17 *C 40.020 58.480 +*N mux_tree_tapbuf_size8_1_sram[1]:18 *C 39.920 51.000 +*N mux_tree_tapbuf_size8_1_sram[1]:19 *C 40.020 51.000 +*N mux_tree_tapbuf_size8_1_sram[1]:20 *C 39.920 44.880 +*N mux_tree_tapbuf_size8_1_sram[1]:21 *C 40.020 44.880 +*N mux_tree_tapbuf_size8_1_sram[1]:22 *C 40.020 38.805 +*N mux_tree_tapbuf_size8_1_sram[1]:23 *C 40.065 38.760 +*N mux_tree_tapbuf_size8_1_sram[1]:24 *C 43.858 38.760 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_ipin_3\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_3\/mux_l2_in_1_:S 1e-06 +5 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_1_sram[1]:6 0.0001246667 +7 mux_tree_tapbuf_size8_1_sram[1]:7 0.0001246667 +8 mux_tree_tapbuf_size8_1_sram[1]:8 0.0001362414 +9 mux_tree_tapbuf_size8_1_sram[1]:9 5.977388e-05 +10 mux_tree_tapbuf_size8_1_sram[1]:10 5.977388e-05 +11 mux_tree_tapbuf_size8_1_sram[1]:11 0.0003553369 +12 mux_tree_tapbuf_size8_1_sram[1]:12 0.0003553369 +13 mux_tree_tapbuf_size8_1_sram[1]:13 0.0002347444 +14 mux_tree_tapbuf_size8_1_sram[1]:14 5.887938e-05 +15 mux_tree_tapbuf_size8_1_sram[1]:15 0.0004300409 +16 mux_tree_tapbuf_size8_1_sram[1]:16 0.0001660262 +17 mux_tree_tapbuf_size8_1_sram[1]:17 0.0004947858 +18 mux_tree_tapbuf_size8_1_sram[1]:18 3.009264e-05 +19 mux_tree_tapbuf_size8_1_sram[1]:19 0.0006630607 +20 mux_tree_tapbuf_size8_1_sram[1]:20 3.040579e-05 +21 mux_tree_tapbuf_size8_1_sram[1]:21 0.0006732807 +22 mux_tree_tapbuf_size8_1_sram[1]:22 0.0003325422 +23 mux_tree_tapbuf_size8_1_sram[1]:23 0.0002977371 +24 mux_tree_tapbuf_size8_1_sram[1]:24 0.0002977371 +25 mux_tree_tapbuf_size8_1_sram[1]:19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001291429 +26 mux_tree_tapbuf_size8_1_sram[1]:16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.775346e-05 +27 mux_tree_tapbuf_size8_1_sram[1]:17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001291429 +28 mux_tree_tapbuf_size8_1_sram[1]:15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.775346e-05 +29 mux_tree_tapbuf_size8_1_sram[1]:21 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.457713e-06 +30 mux_tree_tapbuf_size8_1_sram[1]:21 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.804658e-05 +31 mux_tree_tapbuf_size8_1_sram[1]:19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.457713e-06 +32 mux_tree_tapbuf_size8_1_sram[1]:19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 5.804658e-05 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_1_sram[1]:24 0.152 +1 mux_tree_tapbuf_size8_1_sram[1]:24 mux_tree_tapbuf_size8_1_sram[1]:23 0.003386161 +2 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:22 0.0045 +3 mux_tree_tapbuf_size8_1_sram[1]:22 mux_tree_tapbuf_size8_1_sram[1]:21 0.005424107 +4 mux_tree_tapbuf_size8_1_sram[1]:9 mux_bottom_ipin_3\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size8_1_sram[1]:10 mux_tree_tapbuf_size8_1_sram[1]:9 0.0004263393 +6 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size8_1_sram[1]:13 mux_tree_tapbuf_size8_1_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size8_1_sram[1]:12 mux_tree_tapbuf_size8_1_sram[1]:11 0.005080357 +9 mux_tree_tapbuf_size8_1_sram[1]:20 mux_bottom_ipin_3\/mux_l2_in_3_:S 0.152 +10 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:20 0.0045 +11 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:19 0.005464286 +12 mux_tree_tapbuf_size8_1_sram[1]:18 mux_bottom_ipin_3\/mux_l2_in_2_:S 0.152 +13 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:18 0.0045 +14 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:17 0.006678572 +15 mux_tree_tapbuf_size8_1_sram[1]:16 mux_tree_tapbuf_size8_1_sram[1]:15 0.001872768 +16 mux_tree_tapbuf_size8_1_sram[1]:17 mux_tree_tapbuf_size8_1_sram[1]:16 0.0045 +17 mux_tree_tapbuf_size8_1_sram[1]:17 mux_tree_tapbuf_size8_1_sram[1]:8 0.002084821 +18 mux_tree_tapbuf_size8_1_sram[1]:14 mux_bottom_ipin_3\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size8_1_sram[1]:7 mux_tree_tapbuf_size8_1_sram[1]:6 0.001412946 +20 mux_tree_tapbuf_size8_1_sram[1]:8 mux_tree_tapbuf_size8_1_sram[1]:7 0.0045 +21 mux_tree_tapbuf_size8_1_sram[1]:6 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +22 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:14 0.000125 +23 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:13 0.002154018 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[2] 0.004925374 //LENGTH 37.910 LUMPCC 0.0001370493 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 30.205 9.520 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 15.815 9.860 +*I mux_bottom_ipin_10\/mux_l3_in_1_:S I *L 0.00357 *C 24.940 17.975 +*I mux_bottom_ipin_10\/mux_l3_in_0_:S I *L 0.00357 *C 21.260 19.720 +*N mux_tree_tapbuf_size8_4_sram[2]:4 *C 21.297 19.720 +*N mux_tree_tapbuf_size8_4_sram[2]:5 *C 24.335 19.720 +*N mux_tree_tapbuf_size8_4_sram[2]:6 *C 24.380 19.675 +*N mux_tree_tapbuf_size8_4_sram[2]:7 *C 24.380 18.065 +*N mux_tree_tapbuf_size8_4_sram[2]:8 *C 24.425 18.020 +*N mux_tree_tapbuf_size8_4_sram[2]:9 *C 24.978 17.970 +*N mux_tree_tapbuf_size8_4_sram[2]:10 *C 24.998 17.680 +*N mux_tree_tapbuf_size8_4_sram[2]:11 *C 30.775 17.680 +*N mux_tree_tapbuf_size8_4_sram[2]:12 *C 30.820 17.635 +*N mux_tree_tapbuf_size8_4_sram[2]:13 *C 30.820 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:14 *C 15.815 9.860 +*N mux_tree_tapbuf_size8_4_sram[2]:15 *C 15.640 9.860 +*N mux_tree_tapbuf_size8_4_sram[2]:16 *C 15.640 9.860 +*N mux_tree_tapbuf_size8_4_sram[2]:17 *C 15.640 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:18 *C 15.648 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:19 *C 30.353 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:20 *C 30.360 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:21 *C 30.360 9.520 +*N mux_tree_tapbuf_size8_4_sram[2]:22 *C 30.205 9.520 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_10\/mux_l3_in_1_:S 1e-06 +3 mux_bottom_ipin_10\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_4_sram[2]:4 0.0002388215 +5 mux_tree_tapbuf_size8_4_sram[2]:5 0.0002388215 +6 mux_tree_tapbuf_size8_4_sram[2]:6 0.0001128454 +7 mux_tree_tapbuf_size8_4_sram[2]:7 0.0001128454 +8 mux_tree_tapbuf_size8_4_sram[2]:8 7.440629e-05 +9 mux_tree_tapbuf_size8_4_sram[2]:9 0.0001061851 +10 mux_tree_tapbuf_size8_4_sram[2]:10 0.0004423568 +11 mux_tree_tapbuf_size8_4_sram[2]:11 0.000410578 +12 mux_tree_tapbuf_size8_4_sram[2]:12 0.0004481193 +13 mux_tree_tapbuf_size8_4_sram[2]:13 0.0004804863 +14 mux_tree_tapbuf_size8_4_sram[2]:14 4.834064e-05 +15 mux_tree_tapbuf_size8_4_sram[2]:15 5.25851e-05 +16 mux_tree_tapbuf_size8_4_sram[2]:16 5.398749e-05 +17 mux_tree_tapbuf_size8_4_sram[2]:17 5.758931e-05 +18 mux_tree_tapbuf_size8_4_sram[2]:18 0.0008684659 +19 mux_tree_tapbuf_size8_4_sram[2]:19 0.0008684659 +20 mux_tree_tapbuf_size8_4_sram[2]:20 6.593042e-05 +21 mux_tree_tapbuf_size8_4_sram[2]:21 5.388732e-05 +22 mux_tree_tapbuf_size8_4_sram[2]:22 4.960759e-05 +23 mux_tree_tapbuf_size8_4_sram[2]:12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.852466e-05 +24 mux_tree_tapbuf_size8_4_sram[2]:13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.852466e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_4_sram[2]:22 0.152 +1 mux_tree_tapbuf_size8_4_sram[2]:8 mux_tree_tapbuf_size8_4_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size8_4_sram[2]:7 mux_tree_tapbuf_size8_4_sram[2]:6 0.0014375 +3 mux_tree_tapbuf_size8_4_sram[2]:5 mux_tree_tapbuf_size8_4_sram[2]:4 0.002712054 +4 mux_tree_tapbuf_size8_4_sram[2]:6 mux_tree_tapbuf_size8_4_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size8_4_sram[2]:4 mux_bottom_ipin_10\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_4_sram[2]:9 mux_bottom_ipin_10\/mux_l3_in_1_:S 0.152 +7 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_4_sram[2]:8 0.0004933036 +8 mux_tree_tapbuf_size8_4_sram[2]:11 mux_tree_tapbuf_size8_4_sram[2]:10 0.005158482 +9 mux_tree_tapbuf_size8_4_sram[2]:12 mux_tree_tapbuf_size8_4_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size8_4_sram[2]:20 mux_tree_tapbuf_size8_4_sram[2]:19 0.00341 +11 mux_tree_tapbuf_size8_4_sram[2]:20 mux_tree_tapbuf_size8_4_sram[2]:13 0.0004107143 +12 mux_tree_tapbuf_size8_4_sram[2]:19 mux_tree_tapbuf_size8_4_sram[2]:18 0.002303783 +13 mux_tree_tapbuf_size8_4_sram[2]:17 mux_tree_tapbuf_size8_4_sram[2]:16 0.0001634615 +14 mux_tree_tapbuf_size8_4_sram[2]:18 mux_tree_tapbuf_size8_4_sram[2]:17 0.00341 +15 mux_tree_tapbuf_size8_4_sram[2]:15 mux_tree_tapbuf_size8_4_sram[2]:14 9.51087e-05 +16 mux_tree_tapbuf_size8_4_sram[2]:16 mux_tree_tapbuf_size8_4_sram[2]:15 0.0045 +17 mux_tree_tapbuf_size8_4_sram[2]:14 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +18 mux_tree_tapbuf_size8_4_sram[2]:21 mux_tree_tapbuf_size8_4_sram[2]:20 0.0045 +19 mux_tree_tapbuf_size8_4_sram[2]:22 mux_tree_tapbuf_size8_4_sram[2]:21 8.423914e-05 +20 mux_tree_tapbuf_size8_4_sram[2]:10 mux_tree_tapbuf_size8_4_sram[2]:9 0.0001686047 +21 mux_tree_tapbuf_size8_4_sram[2]:13 mux_tree_tapbuf_size8_4_sram[2]:12 0.007245536 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_1_ccff_tail[0] 0.001154257 //LENGTH 10.130 LUMPCC 0.0001270962 DR + +*CONN +*I mem_bottom_ipin_3\/FTB_11__50:X O *L 0 *C 52.215 44.200 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 50.315 37.060 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 *C 50.315 37.060 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 *C 50.140 37.060 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 *C 50.140 37.105 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 *C 50.140 44.155 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 *C 50.185 44.200 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 *C 52.178 44.200 + +*CAP +0 mem_bottom_ipin_3\/FTB_11__50:X 1e-06 +1 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 4.818133e-05 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 5.233672e-05 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.0003145418 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0003145418 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.0001477795 +7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.0001477795 +8 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 prog_clk[0]:318 1.00724e-09 +9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 prog_clk[0]:324 6.354707e-05 +10 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 prog_clk[0]:319 1.00724e-09 +11 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 prog_clk[0]:325 6.354707e-05 + +*RES +0 mem_bottom_ipin_3\/FTB_11__50:X mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 9.510871e-05 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.006294643 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.001779018 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005849922 //LENGTH 3.705 LUMPCC 0.0002053367 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_1_:X O *L 0 *C 93.555 31.960 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 92.290 33.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 92.328 33.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 93.335 33.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 93.380 33.615 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 93.380 32.005 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 93.380 31.960 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 93.555 31.960 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.568757e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.568757e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.900839e-05 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.900839e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.483084e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.343278e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_0_sram[0]:15 5.129307e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_0_sram[0]:13 7.666658e-07 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_0_sram[0]:14 5.129307e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_0_sram[0]:12 7.666658e-07 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_0_sram[1]:26 5.060861e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_0_sram[1]:27 5.060861e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008995536 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005360759 //LENGTH 3.850 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_0_:X O *L 0 *C 64.575 59.160 +*I mux_bottom_ipin_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 63.845 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 63.883 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 64.355 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 64.400 61.495 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 64.400 59.205 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 64.400 59.160 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 64.575 59.160 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.991322e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.991322e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001504538 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001504538 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.768951e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.565235e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008218844 //LENGTH 5.745 LUMPCC 0.0002455987 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l3_in_1_:X O *L 0 *C 45.715 61.880 +*I mux_bottom_ipin_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 46.750 65.960 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 46.713 65.960 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 46.045 65.960 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 46.000 65.915 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 46.000 61.925 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 46.000 61.880 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 45.715 61.880 + +*CAP +0 mux_bottom_ipin_1\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 7.317313e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.317313e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001532714 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001532714 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.055508e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.084151e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:7 5.258053e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:12 7.021883e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:8 5.258053e-05 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:11 7.021883e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l3_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_1\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0005959822 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0035625 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.006538025 //LENGTH 54.060 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l4_in_0_:X O *L 0 *C 56.295 18.360 +*I mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 56.035 69.550 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 55.720 20.400 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 55.720 67.320 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 56.035 69.550 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 56.120 69.360 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 56.120 69.315 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 56.120 67.377 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 56.120 67.320 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 56.120 67.312 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 56.120 20.408 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 56.120 20.400 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 56.120 20.343 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 56.120 18.405 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 56.120 18.360 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 56.295 18.360 + +*CAP +0 mux_bottom_ipin_4\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001257265 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 6.674526e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.213564e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.607005e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001161318 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001161318 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.674526e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.002716919 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.002716919 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001257265 +12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0001436426 +13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0001436426 +14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.503213e-05 +15 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.445777e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l4_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 9.51087e-05 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.001729911 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.69697e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.007348449 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.69697e-05 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001729911 +12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.619566e-05 +13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001202588 //LENGTH 7.590 LUMPCC 0.0004298704 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_1_:X O *L 0 *C 11.325 28.900 +*I mux_bottom_ipin_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 9.490 33.320 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 9.490 33.320 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 9.660 33.320 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 9.660 33.275 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 9.660 31.665 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 9.705 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 10.995 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 11.040 31.575 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 11.040 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 11.040 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 11.325 28.900 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.294954e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.76214e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.69018e-05 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.69018e-05 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.608871e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.608871e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001598664 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001949962 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.885673e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 6.04464e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[0]:19 6.446059e-06 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[0]:21 6.133224e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[0]:20 6.446059e-06 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[0]:22 6.133224e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.041562e-05 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.041562e-05 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.029741e-05 +19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.657602e-06 +20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.029741e-05 +21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.657602e-06 +22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 ropt_net_167:3 6.278626e-05 +23 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 ropt_net_167:2 6.278626e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239132e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001151786 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.002388393 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0007245658 //LENGTH 6.235 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l4_in_0_:X O *L 0 *C 8.500 66.980 +*I mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.375 71.885 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 9.338 71.790 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 8.785 71.740 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 8.740 71.695 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 8.740 67.025 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 8.740 66.980 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 8.500 66.980 + +*CAP +0 mux_bottom_ipin_9\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.084687e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.084687e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002553008 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002553008 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.68211e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.344936e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l4_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004933036 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.004169643 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001304348 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0] 0.004850746 //LENGTH 38.010 LUMPCC 0.0006552746 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l4_in_0_:X O *L 0 *C 66.415 37.400 +*I mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 66.910 71.905 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 65.840 42.160 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 65.840 68.000 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 66.873 71.800 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 66.285 71.740 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 66.240 71.695 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 66.240 68.058 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 66.240 68.000 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 66.240 67.993 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 66.240 42.168 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 66.240 42.160 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 66.240 42.102 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 66.240 37.445 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 66.240 37.400 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 66.415 37.400 + +*CAP +0 mux_bottom_ipin_12\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.008291e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.076902e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.405704e-05 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.405704e-05 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002088535 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002088535 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 5.076902e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001388536 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.001388536 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 9.008291e-05 +12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.000255403 +13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.000255403 +14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.904501e-05 +15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.902293e-05 +16 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[9]:13 1.533424e-05 +17 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[9]:14 0.0003123031 +18 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_left_in[9]:15 0.0003123031 +19 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 chanx_left_in[9]:12 1.533424e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l4_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0005245536 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.003247768 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.69697e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.69697e-05 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.004045916 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.004158482 +14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001142163 //LENGTH 9.420 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l1_in_0_:X O *L 0 *C 39.385 28.220 +*I mux_bottom_ipin_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 39.925 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 39.925 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 40.020 20.105 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 40.020 28.175 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 39.975 28.220 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 39.422 28.220 + +*CAP +0 mux_bottom_ipin_2\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.889579e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000474147 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000474147 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.148651e-05 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.148651e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l1_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_2\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.007205357 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004059615 //LENGTH 2.590 LUMPCC 0.0001882942 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_1_:X O *L 0 *C 44.335 53.380 +*I mux_bottom_ipin_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 42.035 53.380 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 42.073 53.380 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 44.297 53.380 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001078336 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001078336 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[7]:26 9.41471e-05 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[7]:25 9.41471e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_1_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001986607 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003267209 //LENGTH 2.305 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_2_:X O *L 0 *C 46.635 20.060 +*I mux_bottom_ipin_6\/mux_l3_in_1_:A1 I *L 0.00198 *C 44.620 20.060 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 44.657 20.060 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 46.598 20.060 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001623605 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001623605 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_2_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001732143 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005866863 //LENGTH 3.635 LUMPCC 9.865285e-05 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_2_:X O *L 0 *C 23.635 56.440 +*I mux_bottom_ipin_7\/mux_l3_in_1_:A1 I *L 0.00198 *C 24.940 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 24.902 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 23.965 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.920 58.095 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 23.920 56.485 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 23.920 56.440 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 23.635 56.440 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.489057e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.489057e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001318779 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001318779 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.573329e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.67633e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_right_in[19]:17 4.932642e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[19]:16 4.932642e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_2_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008370536 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001264423 //LENGTH 9.240 LUMPCC 0.0004076023 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_0_:X O *L 0 *C 26.885 53.720 +*I mux_bottom_ipin_11\/mux_l3_in_0_:A1 I *L 0.00198 *C 24.840 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 24.840 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 24.840 47.305 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 24.840 53.720 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 25.760 53.720 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 25.805 53.720 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 26.848 53.720 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.061802e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002392118 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002983728 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.231425e-05 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.715192e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.715192e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[3]:58 5.988176e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[3]:59 5.988176e-05 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[19]:32 0.0001421706 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[19]:33 1.748815e-06 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[19]:14 1.748815e-06 +13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[19]:33 0.0001421706 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0008214285 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009308036 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.005727679 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005476102 //LENGTH 3.825 LUMPCC 6.657459e-05 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_3_:X O *L 0 *C 77.565 15.640 +*I mux_bottom_ipin_14\/mux_l3_in_1_:A0 I *L 0.001631 *C 78.950 17.340 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 78.913 17.340 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 77.785 17.340 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 77.740 17.295 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 77.740 15.685 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 77.740 15.640 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 77.565 15.640 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.378486e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.378486e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001121106 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001121106 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.588702e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.135775e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.32873e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.32873e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_3_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006696 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET chanx_right_out[3] 0.001499301 //LENGTH 10.065 LUMPCC 0 DR + +*CONN +*I FTB_4__3:X O *L 0 *C 94.300 52.700 +*P chanx_right_out[3] O *L 0.7423 *C 103.575 53.040 +*N chanx_right_out[3]:2 *C 99.368 53.040 +*N chanx_right_out[3]:3 *C 99.360 53.040 +*N chanx_right_out[3]:4 *C 99.360 52.700 +*N chanx_right_out[3]:5 *C 99.315 52.700 +*N chanx_right_out[3]:6 *C 94.338 52.700 + +*CAP +0 FTB_4__3:X 1e-06 +1 chanx_right_out[3] 0.000370357 +2 chanx_right_out[3]:2 0.000370357 +3 chanx_right_out[3]:3 4.935034e-05 +4 chanx_right_out[3]:4 4.601767e-05 +5 chanx_right_out[3]:5 0.0003311095 +6 chanx_right_out[3]:6 0.0003311095 + +*RES +0 FTB_4__3:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +2 chanx_right_out[3]:2 chanx_right_out[3] 0.000659175 +3 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +4 chanx_right_out[3]:4 chanx_right_out[3]:3 0.0001634615 +5 chanx_right_out[3]:6 chanx_right_out[3]:5 0.004444197 + +*END + +*D_NET ropt_net_116 0.002341765 //LENGTH 17.820 LUMPCC 0.0005989601 DR + +*CONN +*I FTB_11__10:X O *L 0 *C 97.060 60.860 +*I ropt_mt_inst_715:A I *L 0.001766 *C 88.780 69.360 +*N ropt_net_116:2 *C 88.780 69.360 +*N ropt_net_116:3 *C 88.780 69.020 +*N ropt_net_116:4 *C 90.575 69.020 +*N ropt_net_116:5 *C 90.620 68.975 +*N ropt_net_116:6 *C 90.620 60.905 +*N ropt_net_116:7 *C 90.665 60.860 +*N ropt_net_116:8 *C 97.023 60.860 + +*CAP +0 FTB_11__10:X 1e-06 +1 ropt_mt_inst_715:A 1e-06 +2 ropt_net_116:2 5.742825e-05 +3 ropt_net_116:3 0.0001467449 +4 ropt_net_116:4 0.0001186446 +5 ropt_net_116:5 0.0003052638 +6 ropt_net_116:6 0.0003052638 +7 ropt_net_116:7 0.0004037295 +8 ropt_net_116:8 0.0004037295 +9 ropt_net_116:4 prog_clk[0]:406 7.444408e-06 +10 ropt_net_116:5 prog_clk[0]:405 0.0002237622 +11 ropt_net_116:6 prog_clk[0]:223 0.0002237622 +12 ropt_net_116:3 prog_clk[0]:405 7.444408e-06 +13 ropt_net_116:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.3964e-05 +14 ropt_net_116:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.430951e-05 +15 ropt_net_116:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.3964e-05 +16 ropt_net_116:8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.430951e-05 + +*RES +0 FTB_11__10:X ropt_net_116:8 0.152 +1 ropt_net_116:2 ropt_mt_inst_715:A 0.152 +2 ropt_net_116:4 ropt_net_116:3 0.001602679 +3 ropt_net_116:5 ropt_net_116:4 0.0045 +4 ropt_net_116:7 ropt_net_116:6 0.0045 +5 ropt_net_116:6 ropt_net_116:5 0.007205357 +6 ropt_net_116:8 ropt_net_116:7 0.00567634 +7 ropt_net_116:3 ropt_net_116:2 0.0003035715 + +*END + +*D_NET ropt_net_168 0.001165018 //LENGTH 8.600 LUMPCC 0.0002337939 DR + +*CONN +*I ropt_mt_inst_721:X O *L 0 *C 5.520 46.920 +*I ropt_mt_inst_779:A I *L 0.001766 *C 11.040 44.880 +*N ropt_net_168:2 *C 11.003 44.880 +*N ropt_net_168:3 *C 10.625 44.880 +*N ropt_net_168:4 *C 10.580 44.925 +*N ropt_net_168:5 *C 10.580 46.920 +*N ropt_net_168:6 *C 9.660 46.920 +*N ropt_net_168:7 *C 9.615 46.920 +*N ropt_net_168:8 *C 5.558 46.920 + +*CAP +0 ropt_mt_inst_721:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_168:2 2.802214e-05 +3 ropt_net_168:3 2.802214e-05 +4 ropt_net_168:4 9.096484e-05 +5 ropt_net_168:5 0.0001223254 +6 ropt_net_168:6 6.784361e-05 +7 ropt_net_168:7 0.0002960231 +8 ropt_net_168:8 0.0002960231 +9 ropt_net_168:2 chanx_right_in[7]:11 2.786096e-05 +10 ropt_net_168:3 chanx_right_in[7]:10 2.786096e-05 +11 ropt_net_168:6 chanx_right_in[7]:10 2.297156e-05 +12 ropt_net_168:5 chanx_right_in[7]:11 2.297156e-05 +13 ropt_net_168:4 prog_clk[0]:276 5.556409e-05 +14 ropt_net_168:7 prog_clk[0]:278 7.16977e-07 +15 ropt_net_168:6 prog_clk[0]:279 9.783362e-06 +16 ropt_net_168:8 prog_clk[0]:277 7.16977e-07 +17 ropt_net_168:5 prog_clk[0]:280 6.534745e-05 + +*RES +0 ropt_mt_inst_721:X ropt_net_168:8 0.152 +1 ropt_net_168:2 ropt_mt_inst_779:A 0.152 +2 ropt_net_168:3 ropt_net_168:2 0.0003370536 +3 ropt_net_168:4 ropt_net_168:3 0.0045 +4 ropt_net_168:7 ropt_net_168:6 0.0045 +5 ropt_net_168:6 ropt_net_168:5 0.0008214287 +6 ropt_net_168:8 ropt_net_168:7 0.003622768 +7 ropt_net_168:5 ropt_net_168:4 0.00178125 + +*END + +*D_NET chanx_right_out[2] 0.001272316 //LENGTH 8.700 LUMPCC 0.0002858627 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 97.255 71.400 +*P chanx_right_out[2] O *L 0.7423 *C 100.280 74.950 +*N chanx_right_out[2]:2 *C 99.880 73.440 +*N chanx_right_out[2]:3 *C 100.280 73.448 +*N chanx_right_out[2]:4 *C 100.280 73.440 +*N chanx_right_out[2]:5 *C 100.280 73.383 +*N chanx_right_out[2]:6 *C 100.280 71.445 +*N chanx_right_out[2]:7 *C 100.235 71.400 +*N chanx_right_out[2]:8 *C 97.255 71.400 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chanx_right_out[2] 9.761869e-05 +2 chanx_right_out[2]:2 6.452631e-05 +3 chanx_right_out[2]:3 9.761869e-05 +4 chanx_right_out[2]:4 6.452631e-05 +5 chanx_right_out[2]:5 0.0001458863 +6 chanx_right_out[2]:6 0.0001458863 +7 chanx_right_out[2]:7 0.0001635751 +8 chanx_right_out[2]:8 0.0002058156 +9 chanx_right_out[2]:8 ropt_net_159:4 0.0001429314 +10 chanx_right_out[2]:7 ropt_net_159:5 0.0001429314 + +*RES +0 ropt_mt_inst_761:X chanx_right_out[2]:8 0.152 +1 chanx_right_out[2]:8 chanx_right_out[2]:7 0.002660715 +2 chanx_right_out[2]:7 chanx_right_out[2]:6 0.0045 +3 chanx_right_out[2]:6 chanx_right_out[2]:5 0.001729911 +4 chanx_right_out[2]:5 chanx_right_out[2]:4 0.00341 +5 chanx_right_out[2]:4 chanx_right_out[2]:3 0.00341 +6 chanx_right_out[2]:4 chanx_right_out[2]:2 5.69697e-05 +7 chanx_right_out[2]:3 chanx_right_out[2] 0.0002353916 + +*END + +*D_NET chanx_right_out[1] 0.0005327272 //LENGTH 3.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 101.855 55.760 +*P chanx_right_out[1] O *L 0.7423 *C 103.650 54.400 +*N chanx_right_out[1]:2 *C 102.128 54.400 +*N chanx_right_out[1]:3 *C 102.120 54.458 +*N chanx_right_out[1]:4 *C 102.120 55.715 +*N chanx_right_out[1]:5 *C 102.120 55.760 +*N chanx_right_out[1]:6 *C 101.855 55.760 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 chanx_right_out[1] 0.0001297586 +2 chanx_right_out[1]:2 0.0001297586 +3 chanx_right_out[1]:3 8.479846e-05 +4 chanx_right_out[1]:4 8.479846e-05 +5 chanx_right_out[1]:5 4.536617e-05 +6 chanx_right_out[1]:6 5.724686e-05 + +*RES +0 ropt_mt_inst_737:X chanx_right_out[1]:6 0.152 +1 chanx_right_out[1]:6 chanx_right_out[1]:5 0.0001440218 +2 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +3 chanx_right_out[1]:4 chanx_right_out[1]:3 0.001122768 +4 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +5 chanx_right_out[1]:2 chanx_right_out[1] 0.000238525 + +*END + +*D_NET ropt_net_133 0.001414548 //LENGTH 12.110 LUMPCC 0.0001266356 DR + +*CONN +*I BUFT_P_90:X O *L 0 *C 5.980 67.320 +*I ropt_mt_inst_732:A I *L 0.001766 *C 3.220 72.080 +*N ropt_net_133:2 *C 3.220 72.080 +*N ropt_net_133:3 *C 3.220 71.740 +*N ropt_net_133:4 *C 1.885 71.740 +*N ropt_net_133:5 *C 1.840 71.695 +*N ropt_net_133:6 *C 1.840 67.025 +*N ropt_net_133:7 *C 1.885 66.980 +*N ropt_net_133:8 *C 5.980 66.980 +*N ropt_net_133:9 *C 5.980 67.320 + +*CAP +0 BUFT_P_90:X 1e-06 +1 ropt_mt_inst_732:A 1e-06 +2 ropt_net_133:2 5.412714e-05 +3 ropt_net_133:3 0.0001138246 +4 ropt_net_133:4 8.716953e-05 +5 ropt_net_133:5 0.0002229648 +6 ropt_net_133:6 0.0002229648 +7 ropt_net_133:7 0.0002500286 +8 ropt_net_133:8 0.0002780025 +9 ropt_net_133:9 5.683062e-05 +10 ropt_net_133:6 top_grid_pin_24_[0]:2 6.331781e-05 +11 ropt_net_133:5 top_grid_pin_24_[0] 6.331781e-05 + +*RES +0 BUFT_P_90:X ropt_net_133:9 0.152 +1 ropt_net_133:9 ropt_net_133:8 0.0003035714 +2 ropt_net_133:7 ropt_net_133:6 0.0045 +3 ropt_net_133:6 ropt_net_133:5 0.004169643 +4 ropt_net_133:4 ropt_net_133:3 0.001191964 +5 ropt_net_133:5 ropt_net_133:4 0.0045 +6 ropt_net_133:2 ropt_mt_inst_732:A 0.152 +7 ropt_net_133:8 ropt_net_133:7 0.00365625 +8 ropt_net_133:3 ropt_net_133:2 0.0003035715 + +*END + +*D_NET chanx_right_out[8] 0.0005299138 //LENGTH 3.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 101.855 34.000 +*P chanx_right_out[8] O *L 0.7423 *C 103.650 32.640 +*N chanx_right_out[8]:2 *C 102.128 32.640 +*N chanx_right_out[8]:3 *C 102.120 32.698 +*N chanx_right_out[8]:4 *C 102.120 33.955 +*N chanx_right_out[8]:5 *C 102.120 34.000 +*N chanx_right_out[8]:6 *C 101.855 34.000 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 chanx_right_out[8] 0.0001286016 +2 chanx_right_out[8]:2 0.0001286016 +3 chanx_right_out[8]:3 8.382895e-05 +4 chanx_right_out[8]:4 8.382895e-05 +5 chanx_right_out[8]:5 4.62317e-05 +6 chanx_right_out[8]:6 5.782097e-05 + +*RES +0 ropt_mt_inst_746:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:6 chanx_right_out[8]:5 0.0001440218 +2 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.001122768 +4 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +5 chanx_right_out[8]:2 chanx_right_out[8] 0.000238525 + +*END + +*D_NET chanx_left_in[1] 0.02017725 //LENGTH 135.700 LUMPCC 0.005061307 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.305 66.640 +*I mux_bottom_ipin_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 33.485 52.700 +*I mux_bottom_ipin_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 38.280 52.700 +*I mux_bottom_ipin_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 66.240 58.140 +*I mux_bottom_ipin_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 64.765 52.700 +*I mux_bottom_ipin_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 79.120 52.700 +*I mux_bottom_ipin_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 83.360 52.700 +*I FTB_2__1:A I *L 0.001767 *C 93.380 55.760 +*I mux_bottom_ipin_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 20.800 47.260 +*I mux_bottom_ipin_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 20.605 56.100 +*N chanx_left_in[1]:10 *C 20.700 47.260 +*N chanx_left_in[1]:11 *C 20.700 47.305 +*N chanx_left_in[1]:12 *C 93.418 55.760 +*N chanx_left_in[1]:13 *C 93.840 55.760 +*N chanx_left_in[1]:14 *C 93.840 55.420 +*N chanx_left_in[1]:15 *C 93.840 55.375 +*N chanx_left_in[1]:16 *C 93.840 54.060 +*N chanx_left_in[1]:17 *C 92.920 54.060 +*N chanx_left_in[1]:18 *C 92.920 53.425 +*N chanx_left_in[1]:19 *C 92.875 53.380 +*N chanx_left_in[1]:20 *C 85.100 53.380 +*N chanx_left_in[1]:21 *C 85.100 52.700 +*N chanx_left_in[1]:22 *C 83.360 52.700 +*N chanx_left_in[1]:23 *C 79.120 52.700 +*N chanx_left_in[1]:24 *C 80.500 52.700 +*N chanx_left_in[1]:25 *C 80.500 52.745 +*N chanx_left_in[1]:26 *C 80.500 53.675 +*N chanx_left_in[1]:27 *C 80.455 53.720 +*N chanx_left_in[1]:28 *C 64.803 52.700 +*N chanx_left_in[1]:29 *C 66.240 52.700 +*N chanx_left_in[1]:30 *C 66.240 53.720 +*N chanx_left_in[1]:31 *C 66.240 53.765 +*N chanx_left_in[1]:32 *C 66.203 58.140 +*N chanx_left_in[1]:33 *C 65.825 58.140 +*N chanx_left_in[1]:34 *C 65.780 58.095 +*N chanx_left_in[1]:35 *C 65.780 55.080 +*N chanx_left_in[1]:36 *C 66.240 55.035 +*N chanx_left_in[1]:37 *C 66.195 55.080 +*N chanx_left_in[1]:38 *C 40.985 55.080 +*N chanx_left_in[1]:39 *C 40.940 55.035 +*N chanx_left_in[1]:40 *C 40.940 52.745 +*N chanx_left_in[1]:41 *C 40.895 52.700 +*N chanx_left_in[1]:42 *C 38.280 52.700 +*N chanx_left_in[1]:43 *C 36.800 52.700 +*N chanx_left_in[1]:44 *C 36.800 53.040 +*N chanx_left_in[1]:45 *C 34.500 53.040 +*N chanx_left_in[1]:46 *C 34.500 52.700 +*N chanx_left_in[1]:47 *C 33.625 52.700 +*N chanx_left_in[1]:48 *C 33.580 52.700 +*N chanx_left_in[1]:49 *C 33.580 53.040 +*N chanx_left_in[1]:50 *C 33.573 53.040 +*N chanx_left_in[1]:51 *C 20.707 53.040 +*N chanx_left_in[1]:52 *C 20.700 53.040 +*N chanx_left_in[1]:53 *C 20.700 56.055 +*N chanx_left_in[1]:54 *C 20.605 56.100 +*N chanx_left_in[1]:55 *C 20.700 56.440 +*N chanx_left_in[1]:56 *C 3.265 56.440 +*N chanx_left_in[1]:57 *C 3.220 56.485 +*N chanx_left_in[1]:58 *C 3.220 66.583 +*N chanx_left_in[1]:59 *C 3.213 66.640 + +*CAP +0 chanx_left_in[1] 0.0001147789 +1 mux_bottom_ipin_7\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_ipin_3\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_ipin_1\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_0_:A1 1e-06 +5 mux_bottom_ipin_13\/mux_l1_in_0_:A1 1e-06 +6 mux_bottom_ipin_15\/mux_l1_in_0_:A1 1e-06 +7 FTB_2__1:A 1e-06 +8 mux_bottom_ipin_11\/mux_l1_in_0_:A1 1e-06 +9 mux_bottom_ipin_9\/mux_l1_in_0_:A1 1e-06 +10 chanx_left_in[1]:10 3.334458e-05 +11 chanx_left_in[1]:11 0.0001798371 +12 chanx_left_in[1]:12 5.918516e-05 +13 chanx_left_in[1]:13 8.892867e-05 +14 chanx_left_in[1]:14 6.463606e-05 +15 chanx_left_in[1]:15 8.203849e-05 +16 chanx_left_in[1]:16 0.0001397632 +17 chanx_left_in[1]:17 8.363987e-05 +18 chanx_left_in[1]:18 2.591513e-05 +19 chanx_left_in[1]:19 0.0004520353 +20 chanx_left_in[1]:20 0.0004914696 +21 chanx_left_in[1]:21 0.0001514103 +22 chanx_left_in[1]:22 0.0002709409 +23 chanx_left_in[1]:23 0.0001439681 +24 chanx_left_in[1]:24 0.0002669549 +25 chanx_left_in[1]:25 6.77772e-05 +26 chanx_left_in[1]:26 6.77772e-05 +27 chanx_left_in[1]:27 0.0008809968 +28 chanx_left_in[1]:28 6.176322e-05 +29 chanx_left_in[1]:29 0.0001250074 +30 chanx_left_in[1]:30 0.0009442409 +31 chanx_left_in[1]:31 9.81716e-05 +32 chanx_left_in[1]:32 4.624396e-05 +33 chanx_left_in[1]:33 4.624396e-05 +34 chanx_left_in[1]:34 0.0002214842 +35 chanx_left_in[1]:35 0.0002570499 +36 chanx_left_in[1]:36 0.0001337373 +37 chanx_left_in[1]:37 0.001712691 +38 chanx_left_in[1]:38 0.001712691 +39 chanx_left_in[1]:39 7.165858e-05 +40 chanx_left_in[1]:40 7.165858e-05 +41 chanx_left_in[1]:41 0.0001692805 +42 chanx_left_in[1]:42 0.0002917159 +43 chanx_left_in[1]:43 0.0001196543 +44 chanx_left_in[1]:44 0.0001990201 +45 chanx_left_in[1]:45 0.0001987806 +46 chanx_left_in[1]:46 0.0001192407 +47 chanx_left_in[1]:47 9.380475e-05 +48 chanx_left_in[1]:48 4.656723e-05 +49 chanx_left_in[1]:49 5.069045e-05 +50 chanx_left_in[1]:50 0.0004957824 +51 chanx_left_in[1]:51 0.0004957824 +52 chanx_left_in[1]:52 0.0003694458 +53 chanx_left_in[1]:53 0.000153884 +54 chanx_left_in[1]:54 6.394445e-05 +55 chanx_left_in[1]:55 0.001232842 +56 chanx_left_in[1]:56 0.001201701 +57 chanx_left_in[1]:57 0.0002609913 +58 chanx_left_in[1]:58 0.0002609913 +59 chanx_left_in[1]:59 0.0001147789 +60 chanx_left_in[1] chanx_left_in[3] 4.849479e-05 +61 chanx_left_in[1]:48 chanx_left_in[3]:54 1.018519e-05 +62 chanx_left_in[1]:49 chanx_left_in[3]:55 1.018519e-05 +63 chanx_left_in[1]:30 chanx_left_in[3]:34 3.658547e-05 +64 chanx_left_in[1]:30 chanx_left_in[3]:12 3.880444e-06 +65 chanx_left_in[1]:27 chanx_left_in[3]:33 3.658547e-05 +66 chanx_left_in[1]:27 chanx_left_in[3]:13 3.880444e-06 +67 chanx_left_in[1]:19 chanx_left_in[3]:14 2.837535e-05 +68 chanx_left_in[1]:18 chanx_left_in[3]:16 2.376353e-05 +69 chanx_left_in[1]:15 chanx_left_in[3]:17 5.63904e-06 +70 chanx_left_in[1]:56 chanx_left_in[3]:66 8.794351e-06 +71 chanx_left_in[1]:57 chanx_left_in[3]:67 4.263617e-05 +72 chanx_left_in[1]:58 chanx_left_in[3]:68 4.263617e-05 +73 chanx_left_in[1]:59 chanx_left_in[3]:69 4.849479e-05 +74 chanx_left_in[1]:39 chanx_left_in[3]:45 6.798783e-05 +75 chanx_left_in[1]:40 chanx_left_in[3]:44 6.798783e-05 +76 chanx_left_in[1]:55 chanx_left_in[3]:65 8.794351e-06 +77 chanx_left_in[1]:20 chanx_left_in[3]:15 2.837535e-05 +78 chanx_left_in[1]:17 chanx_left_in[3]:17 2.376353e-05 +79 chanx_left_in[1]:16 chanx_left_in[3]:16 5.63904e-06 +80 chanx_left_in[1]:50 chanx_left_in[7]:29 0.0002077386 +81 chanx_left_in[1]:50 chanx_left_in[7]:34 0.000497941 +82 chanx_left_in[1]:51 chanx_left_in[7]:34 0.0002077386 +83 chanx_left_in[1]:51 chanx_left_in[7]:35 0.000497941 +84 chanx_left_in[1]:42 chanx_left_in[7]:26 1.024883e-05 +85 chanx_left_in[1]:41 chanx_left_in[7]:25 1.024883e-05 +86 chanx_left_in[1]:57 chanx_left_in[12]:28 0.000281336 +87 chanx_left_in[1]:58 chanx_left_in[12]:29 0.000281336 +88 chanx_left_in[1]:50 chanx_left_in[13]:17 0.0001329488 +89 chanx_left_in[1]:51 chanx_left_in[13]:21 0.0001329488 +90 chanx_left_in[1]:30 chanx_left_in[13]:13 7.061751e-06 +91 chanx_left_in[1]:30 chanx_left_in[13]:14 5.167518e-06 +92 chanx_left_in[1]:27 chanx_left_in[13]:8 7.061751e-06 +93 chanx_left_in[1]:27 chanx_left_in[13]:13 5.167518e-06 +94 chanx_left_in[1]:18 chanx_left_in[13]:6 1.978484e-09 +95 chanx_left_in[1]:57 chanx_left_in[13]:23 0.0001252257 +96 chanx_left_in[1]:58 chanx_left_in[13]:24 0.0001252257 +97 chanx_left_in[1]:37 chanx_left_in[13]:17 1.857225e-05 +98 chanx_left_in[1]:38 chanx_left_in[13]:21 1.857225e-05 +99 chanx_left_in[1]:17 chanx_left_in[13]:7 1.978484e-09 +100 chanx_left_in[1]:53 chanx_right_in[1]:12 2.2261e-05 +101 chanx_left_in[1]:47 chanx_right_in[1]:34 8.670742e-07 +102 chanx_left_in[1]:52 chanx_right_in[1]:12 2.751362e-05 +103 chanx_left_in[1]:52 chanx_right_in[1]:29 5.332555e-05 +104 chanx_left_in[1]:30 chanx_right_in[1]:49 6.675696e-05 +105 chanx_left_in[1]:24 chanx_right_in[1]:50 5.430697e-05 +106 chanx_left_in[1]:24 chanx_right_in[1]:49 7.258161e-06 +107 chanx_left_in[1]:25 chanx_right_in[1]:51 1.474043e-05 +108 chanx_left_in[1]:27 chanx_right_in[1]:50 6.675696e-05 +109 chanx_left_in[1]:26 chanx_right_in[1]:52 1.474043e-05 +110 chanx_left_in[1]:28 chanx_right_in[1]:40 5.325205e-06 +111 chanx_left_in[1]:22 chanx_right_in[1]:50 7.258161e-06 +112 chanx_left_in[1]:22 chanx_right_in[1]:48 3.98615e-05 +113 chanx_left_in[1]:23 chanx_right_in[1]:49 1.444547e-05 +114 chanx_left_in[1]:42 chanx_right_in[1]:33 8.406348e-06 +115 chanx_left_in[1]:33 chanx_right_in[1]:43 1.004958e-05 +116 chanx_left_in[1]:34 chanx_right_in[1]:45 5.518276e-06 +117 chanx_left_in[1]:32 chanx_right_in[1]:44 1.004958e-05 +118 chanx_left_in[1]:11 chanx_right_in[1]:28 3.106456e-05 +119 chanx_left_in[1]:11 chanx_right_in[1]:29 2.751362e-05 +120 chanx_left_in[1]:46 chanx_right_in[1]:35 8.670742e-07 +121 chanx_left_in[1]:45 chanx_right_in[1]:35 1.564862e-05 +122 chanx_left_in[1]:45 chanx_right_in[1]:34 4.316238e-06 +123 chanx_left_in[1]:44 chanx_right_in[1]:35 4.316238e-06 +124 chanx_left_in[1]:44 chanx_right_in[1]:33 1.564862e-05 +125 chanx_left_in[1]:43 chanx_right_in[1]:35 8.406348e-06 +126 chanx_left_in[1]:29 chanx_right_in[1]:39 5.325205e-06 +127 chanx_left_in[1]:35 chanx_right_in[1]:46 5.518276e-06 +128 chanx_left_in[1]:53 chanx_right_in[3]:25 1.294818e-05 +129 chanx_left_in[1]:48 chanx_right_in[3]:35 2.25526e-08 +130 chanx_left_in[1]:48 chanx_right_in[3]:34 2.25526e-08 +131 chanx_left_in[1]:49 chanx_right_in[3]:34 2.25526e-08 +132 chanx_left_in[1]:49 chanx_right_in[3]:31 2.25526e-08 +133 chanx_left_in[1]:52 chanx_right_in[3]:26 1.294818e-05 +134 chanx_left_in[1]:52 chanx_right_in[3]:25 0.0001511705 +135 chanx_left_in[1]:30 chanx_right_in[3]:49 7.785238e-06 +136 chanx_left_in[1]:30 chanx_right_in[3]:53 1.370055e-05 +137 chanx_left_in[1]:25 chanx_right_in[3]:58 3.17766e-06 +138 chanx_left_in[1]:27 chanx_right_in[3]:50 7.785238e-06 +139 chanx_left_in[1]:27 chanx_right_in[3]:52 1.370055e-05 +140 chanx_left_in[1]:26 chanx_right_in[3]:59 3.17766e-06 +141 chanx_left_in[1]:28 chanx_right_in[3]:49 6.249193e-05 +142 chanx_left_in[1]:11 chanx_right_in[3]:26 0.0001511705 +143 chanx_left_in[1]:37 chanx_right_in[3]:50 2.665043e-07 +144 chanx_left_in[1]:37 chanx_right_in[3]:49 2.766132e-07 +145 chanx_left_in[1]:38 chanx_right_in[3]:49 2.665043e-07 +146 chanx_left_in[1]:38 chanx_right_in[3]:44 2.766132e-07 +147 chanx_left_in[1]:29 chanx_right_in[3]:50 6.249193e-05 +148 chanx_left_in[1]:37 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.779731e-05 +149 chanx_left_in[1]:38 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.779731e-05 +150 chanx_left_in[1]:56 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.224702e-05 +151 chanx_left_in[1]:55 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.224702e-05 +152 chanx_left_in[1]:42 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.320353e-05 +153 chanx_left_in[1]:39 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.024514e-05 +154 chanx_left_in[1]:41 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.320353e-05 +155 chanx_left_in[1]:40 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.024514e-05 +156 chanx_left_in[1]:19 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.667475e-05 +157 chanx_left_in[1]:22 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.082487e-06 +158 chanx_left_in[1]:21 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.082487e-06 +159 chanx_left_in[1]:20 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.667475e-05 +160 chanx_left_in[1]:19 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001056293 +161 chanx_left_in[1]:18 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.073029e-06 +162 chanx_left_in[1]:20 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001056293 +163 chanx_left_in[1]:17 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.073029e-06 +164 chanx_left_in[1]:56 ropt_net_142:7 4.422165e-05 +165 chanx_left_in[1]:55 ropt_net_142:6 4.422165e-05 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:59 0.0002988417 +1 chanx_left_in[1]:54 chanx_left_in[1]:53 0.0045 +2 chanx_left_in[1]:54 mux_bottom_ipin_9\/mux_l1_in_0_:A1 0.152 +3 chanx_left_in[1]:53 chanx_left_in[1]:52 0.002691965 +4 chanx_left_in[1]:47 mux_bottom_ipin_7\/mux_l1_in_0_:A1 0.152 +5 chanx_left_in[1]:47 chanx_left_in[1]:46 0.00078125 +6 chanx_left_in[1]:48 chanx_left_in[1]:47 0.0045 +7 chanx_left_in[1]:49 chanx_left_in[1]:48 0.0001634615 +8 chanx_left_in[1]:50 chanx_left_in[1]:49 0.00341 +9 chanx_left_in[1]:52 chanx_left_in[1]:51 0.00341 +10 chanx_left_in[1]:52 chanx_left_in[1]:11 0.005120536 +11 chanx_left_in[1]:51 chanx_left_in[1]:50 0.002015517 +12 chanx_left_in[1]:30 chanx_left_in[1]:29 0.0009107144 +13 chanx_left_in[1]:30 chanx_left_in[1]:27 0.01269197 +14 chanx_left_in[1]:31 chanx_left_in[1]:30 0.0045 +15 chanx_left_in[1]:24 chanx_left_in[1]:23 0.001232143 +16 chanx_left_in[1]:24 chanx_left_in[1]:22 0.002553571 +17 chanx_left_in[1]:25 chanx_left_in[1]:24 0.0045 +18 chanx_left_in[1]:27 chanx_left_in[1]:26 0.0045 +19 chanx_left_in[1]:26 chanx_left_in[1]:25 0.0008303572 +20 chanx_left_in[1]:19 chanx_left_in[1]:18 0.0045 +21 chanx_left_in[1]:18 chanx_left_in[1]:17 0.0005669644 +22 chanx_left_in[1]:14 chanx_left_in[1]:13 0.0003035715 +23 chanx_left_in[1]:15 chanx_left_in[1]:14 0.0045 +24 chanx_left_in[1]:12 FTB_2__1:A 0.152 +25 chanx_left_in[1]:28 mux_bottom_ipin_5\/mux_l1_in_0_:A1 0.152 +26 chanx_left_in[1]:22 mux_bottom_ipin_15\/mux_l1_in_0_:A1 0.152 +27 chanx_left_in[1]:22 chanx_left_in[1]:21 0.001553571 +28 chanx_left_in[1]:23 mux_bottom_ipin_13\/mux_l1_in_0_:A1 0.152 +29 chanx_left_in[1]:42 mux_bottom_ipin_3\/mux_l1_in_0_:A1 0.152 +30 chanx_left_in[1]:42 chanx_left_in[1]:41 0.002334822 +31 chanx_left_in[1]:33 chanx_left_in[1]:32 0.0003370536 +32 chanx_left_in[1]:34 chanx_left_in[1]:33 0.0045 +33 chanx_left_in[1]:32 mux_bottom_ipin_1\/mux_l1_in_0_:A1 0.152 +34 chanx_left_in[1]:10 mux_bottom_ipin_11\/mux_l1_in_0_:A1 0.152 +35 chanx_left_in[1]:11 chanx_left_in[1]:10 0.0045 +36 chanx_left_in[1]:56 chanx_left_in[1]:55 0.01556697 +37 chanx_left_in[1]:57 chanx_left_in[1]:56 0.0045 +38 chanx_left_in[1]:58 chanx_left_in[1]:57 0.009015625 +39 chanx_left_in[1]:59 chanx_left_in[1]:58 0.00341 +40 chanx_left_in[1]:37 chanx_left_in[1]:36 0.0045 +41 chanx_left_in[1]:36 chanx_left_in[1]:35 0.0004107143 +42 chanx_left_in[1]:36 chanx_left_in[1]:31 0.001133929 +43 chanx_left_in[1]:38 chanx_left_in[1]:37 0.02250893 +44 chanx_left_in[1]:39 chanx_left_in[1]:38 0.0045 +45 chanx_left_in[1]:41 chanx_left_in[1]:40 0.0045 +46 chanx_left_in[1]:40 chanx_left_in[1]:39 0.002044643 +47 chanx_left_in[1]:55 chanx_left_in[1]:54 0.0003035715 +48 chanx_left_in[1]:46 chanx_left_in[1]:45 0.0003035715 +49 chanx_left_in[1]:45 chanx_left_in[1]:44 0.002053571 +50 chanx_left_in[1]:44 chanx_left_in[1]:43 0.0003035715 +51 chanx_left_in[1]:43 chanx_left_in[1]:42 0.001321429 +52 chanx_left_in[1]:29 chanx_left_in[1]:28 0.001283482 +53 chanx_left_in[1]:21 chanx_left_in[1]:20 0.0006071429 +54 chanx_left_in[1]:20 chanx_left_in[1]:19 0.006941965 +55 chanx_left_in[1]:13 chanx_left_in[1]:12 0.0003772322 +56 chanx_left_in[1]:35 chanx_left_in[1]:34 0.002691964 +57 chanx_left_in[1]:17 chanx_left_in[1]:16 0.0008214285 +58 chanx_left_in[1]:16 chanx_left_in[1]:15 0.001174107 + +*END + +*D_NET chanx_left_in[16] 0.01851424 //LENGTH 126.790 LUMPCC 0.005117172 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_ipin_12\/mux_l2_in_2_:A0 I *L 0.001631 *C 71.590 31.620 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 84.470 26.180 +*I ropt_mt_inst_716:A I *L 0.001767 *C 97.980 28.560 +*I mux_top_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 84.345 17.000 +*N chanx_left_in[16]:5 *C 84.308 17.000 +*N chanx_left_in[16]:6 *C 83.765 17.000 +*N chanx_left_in[16]:7 *C 83.720 17.045 +*N chanx_left_in[16]:8 *C 97.943 28.560 +*N chanx_left_in[16]:9 *C 97.105 28.560 +*N chanx_left_in[16]:10 *C 97.060 28.515 +*N chanx_left_in[16]:11 *C 97.060 25.545 +*N chanx_left_in[16]:12 *C 97.015 25.500 +*N chanx_left_in[16]:13 *C 88.320 25.500 +*N chanx_left_in[16]:14 *C 88.400 25.160 +*N chanx_left_in[16]:15 *C 88.330 25.205 +*N chanx_left_in[16]:16 *C 88.320 25.795 +*N chanx_left_in[16]:17 *C 88.275 25.840 +*N chanx_left_in[16]:18 *C 84.470 25.840 +*N chanx_left_in[16]:19 *C 84.470 26.158 +*N chanx_left_in[16]:20 *C 83.765 26.180 +*N chanx_left_in[16]:21 *C 83.720 26.180 +*N chanx_left_in[16]:22 *C 83.720 30.543 +*N chanx_left_in[16]:23 *C 83.713 30.600 +*N chanx_left_in[16]:24 *C 71.590 31.620 +*N chanx_left_in[16]:25 *C 71.300 31.620 +*N chanx_left_in[16]:26 *C 71.300 31.575 +*N chanx_left_in[16]:27 *C 71.300 30.658 +*N chanx_left_in[16]:28 *C 71.300 30.600 +*N chanx_left_in[16]:29 *C 54.410 30.600 +*N chanx_left_in[16]:30 *C 4.620 30.600 +*N chanx_left_in[16]:31 *C 4.600 30.608 +*N chanx_left_in[16]:32 *C 4.600 36.712 +*N chanx_left_in[16]:33 *C 4.580 36.720 + +*CAP +0 chanx_left_in[16] 0.0002266783 +1 mux_bottom_ipin_12\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_2_:A0 1e-06 +3 ropt_mt_inst_716:A 1e-06 +4 mux_top_ipin_0\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[16]:5 5.612611e-05 +6 chanx_left_in[16]:6 5.612611e-05 +7 chanx_left_in[16]:7 0.000518933 +8 chanx_left_in[16]:8 0.0001003641 +9 chanx_left_in[16]:9 0.0001003641 +10 chanx_left_in[16]:10 0.0001912909 +11 chanx_left_in[16]:11 0.0001912909 +12 chanx_left_in[16]:12 0.0005185736 +13 chanx_left_in[16]:13 0.0005444671 +14 chanx_left_in[16]:14 5.555635e-05 +15 chanx_left_in[16]:15 5.323545e-05 +16 chanx_left_in[16]:16 5.323545e-05 +17 chanx_left_in[16]:17 0.0001967976 +18 chanx_left_in[16]:18 0.000224395 +19 chanx_left_in[16]:19 7.390775e-05 +20 chanx_left_in[16]:20 4.631033e-05 +21 chanx_left_in[16]:21 0.0008028595 +22 chanx_left_in[16]:22 0.0002518498 +23 chanx_left_in[16]:23 0.0006851877 +24 chanx_left_in[16]:24 4.693123e-05 +25 chanx_left_in[16]:25 5.114716e-05 +26 chanx_left_in[16]:26 8.023751e-05 +27 chanx_left_in[16]:27 8.023751e-05 +28 chanx_left_in[16]:28 0.001674769 +29 chanx_left_in[16]:29 0.003238596 +30 chanx_left_in[16]:30 0.002249016 +31 chanx_left_in[16]:31 0.0003989528 +32 chanx_left_in[16]:32 0.0003989528 +33 chanx_left_in[16]:33 0.0002266783 +34 chanx_left_in[16]:12 chanx_left_in[0]:28 2.01765e-06 +35 chanx_left_in[16]:17 chanx_left_in[0]:28 6.994542e-05 +36 chanx_left_in[16]:20 chanx_left_in[0]:29 3.872662e-05 +37 chanx_left_in[16]:19 chanx_left_in[0]:28 3.872662e-05 +38 chanx_left_in[16]:30 chanx_left_in[0]:49 0.0001325899 +39 chanx_left_in[16]:30 chanx_left_in[0]:54 5.129997e-06 +40 chanx_left_in[16]:30 chanx_left_in[0]:56 6.499944e-06 +41 chanx_left_in[16]:18 chanx_left_in[0]:29 6.994542e-05 +42 chanx_left_in[16]:13 chanx_left_in[0]:29 2.01765e-06 +43 chanx_left_in[16]:29 chanx_left_in[0]:48 0.0001325899 +44 chanx_left_in[16]:29 chanx_left_in[0]:53 5.129997e-06 +45 chanx_left_in[16]:29 chanx_left_in[0]:55 6.499944e-06 +46 chanx_left_in[16] chanx_left_in[4] 6.851553e-05 +47 chanx_left_in[16]:23 chanx_left_in[4]:21 0.0004297575 +48 chanx_left_in[16]:28 chanx_left_in[4]:22 0.0004297575 +49 chanx_left_in[16]:28 chanx_left_in[4]:30 3.173399e-06 +50 chanx_left_in[16]:33 chanx_left_in[4]:38 6.851553e-05 +51 chanx_left_in[16]:29 chanx_left_in[4]:31 3.173399e-06 +52 chanx_left_in[16]:23 chanx_left_in[8]:11 7.617048e-05 +53 chanx_left_in[16]:28 chanx_left_in[8]:11 9.509268e-05 +54 chanx_left_in[16]:28 chanx_left_in[8]:12 7.617048e-05 +55 chanx_left_in[16]:28 chanx_left_in[8]:15 1.014159e-05 +56 chanx_left_in[16]:28 chanx_left_in[8]:16 1.522761e-06 +57 chanx_left_in[16]:30 chanx_left_in[8] 1.922518e-07 +58 chanx_left_in[16]:30 chanx_left_in[8]:17 0.000112786 +59 chanx_left_in[16]:31 chanx_left_in[8]:26 8.811439e-06 +60 chanx_left_in[16]:32 chanx_left_in[8]:17 8.811439e-06 +61 chanx_left_in[16]:29 chanx_left_in[8]:12 9.509268e-05 +62 chanx_left_in[16]:29 chanx_left_in[8]:16 0.0001229276 +63 chanx_left_in[16]:29 chanx_left_in[8]:17 1.522761e-06 +64 chanx_left_in[16]:29 chanx_left_in[8]:26 1.922518e-07 +65 chanx_left_in[16]:30 chanx_right_in[18]:12 0.0005557578 +66 chanx_left_in[16]:29 chanx_right_in[18]:13 0.0005557578 +67 chanx_left_in[16]:30 mux_tree_tapbuf_size8_0_sram[0]:11 0.0002245211 +68 chanx_left_in[16]:29 mux_tree_tapbuf_size8_0_sram[0]:12 0.0002245211 +69 chanx_left_in[16]:22 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.779003e-05 +70 chanx_left_in[16]:21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.779003e-05 +71 chanx_left_in[16]:21 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.68792e-05 +72 chanx_left_in[16]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.68792e-05 +73 chanx_left_in[16]:30 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001972299 +74 chanx_left_in[16]:29 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001972299 +75 chanx_left_in[16]:30 chanx_left_out[11] 0.0002783287 +76 chanx_left_in[16]:30 chanx_left_out[11]:5 0.0001170062 +77 chanx_left_in[16]:29 chanx_left_out[11]:6 0.0001170062 +78 chanx_left_in[16]:29 chanx_left_out[11]:2 0.0002783287 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:33 0.0005248333 +1 chanx_left_in[16]:8 ropt_mt_inst_716:A 0.152 +2 chanx_left_in[16]:9 chanx_left_in[16]:8 0.0007477679 +3 chanx_left_in[16]:10 chanx_left_in[16]:9 0.0045 +4 chanx_left_in[16]:12 chanx_left_in[16]:11 0.0045 +5 chanx_left_in[16]:11 chanx_left_in[16]:10 0.002651786 +6 chanx_left_in[16]:14 chanx_left_in[16]:13 0.0003035715 +7 chanx_left_in[16]:15 chanx_left_in[16]:14 0.0045 +8 chanx_left_in[16]:17 chanx_left_in[16]:16 0.0045 +9 chanx_left_in[16]:16 chanx_left_in[16]:15 0.0005267857 +10 chanx_left_in[16]:22 chanx_left_in[16]:21 0.003895089 +11 chanx_left_in[16]:23 chanx_left_in[16]:22 0.00341 +12 chanx_left_in[16]:20 chanx_left_in[16]:19 0.0006294643 +13 chanx_left_in[16]:21 chanx_left_in[16]:20 0.0045 +14 chanx_left_in[16]:21 chanx_left_in[16]:7 0.00815625 +15 chanx_left_in[16]:27 chanx_left_in[16]:26 0.0008191966 +16 chanx_left_in[16]:28 chanx_left_in[16]:27 0.00341 +17 chanx_left_in[16]:28 chanx_left_in[16]:23 0.001944625 +18 chanx_left_in[16]:25 chanx_left_in[16]:24 0.0001576087 +19 chanx_left_in[16]:26 chanx_left_in[16]:25 0.0045 +20 chanx_left_in[16]:24 mux_bottom_ipin_12\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[16]:6 chanx_left_in[16]:5 0.000484375 +22 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0045 +23 chanx_left_in[16]:5 mux_top_ipin_0\/mux_l2_in_2_:A0 0.152 +24 chanx_left_in[16]:19 mux_bottom_ipin_0\/mux_l2_in_2_:A0 0.152 +25 chanx_left_in[16]:19 chanx_left_in[16]:18 0.0002834821 +26 chanx_left_in[16]:30 chanx_left_in[16]:29 0.007800432 +27 chanx_left_in[16]:31 chanx_left_in[16]:30 0.00341 +28 chanx_left_in[16]:33 chanx_left_in[16]:32 0.00341 +29 chanx_left_in[16]:32 chanx_left_in[16]:31 0.0009564499 +30 chanx_left_in[16]:18 chanx_left_in[16]:17 0.003397321 +31 chanx_left_in[16]:13 chanx_left_in[16]:12 0.007763393 +32 chanx_left_in[16]:29 chanx_left_in[16]:28 0.0026461 + +*END + +*D_NET chanx_left_in[17] 0.02376531 //LENGTH 153.625 LUMPCC 0.009339842 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 62.560 +*I BUFT_P_102:A I *L 0.001776 *C 85.560 4.080 +*I mux_bottom_ipin_13\/mux_l2_in_2_:A0 I *L 0.001631 *C 70.670 58.820 +*I mux_bottom_ipin_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 46.635 55.420 +*N chanx_left_in[17]:4 *C 46.635 55.420 +*N chanx_left_in[17]:5 *C 70.633 58.820 +*N chanx_left_in[17]:6 *C 69.965 58.820 +*N chanx_left_in[17]:7 *C 69.920 58.775 +*N chanx_left_in[17]:8 *C 69.920 55.818 +*N chanx_left_in[17]:9 *C 85.523 4.080 +*N chanx_left_in[17]:10 *C 82.845 4.080 +*N chanx_left_in[17]:11 *C 82.800 4.125 +*N chanx_left_in[17]:12 *C 82.800 12.195 +*N chanx_left_in[17]:13 *C 82.755 12.240 +*N chanx_left_in[17]:14 *C 80.500 12.240 +*N chanx_left_in[17]:15 *C 80.500 12.285 +*N chanx_left_in[17]:16 *C 80.500 21.023 +*N chanx_left_in[17]:17 *C 80.493 21.080 +*N chanx_left_in[17]:18 *C 69.940 21.080 +*N chanx_left_in[17]:19 *C 69.920 21.088 +*N chanx_left_in[17]:20 *C 69.920 55.753 +*N chanx_left_in[17]:21 *C 69.913 55.760 +*N chanx_left_in[17]:22 *C 46.468 55.760 +*N chanx_left_in[17]:23 *C 46.460 55.760 +*N chanx_left_in[17]:24 *C 46.505 55.753 +*N chanx_left_in[17]:25 *C 38.225 55.760 +*N chanx_left_in[17]:26 *C 38.180 55.805 +*N chanx_left_in[17]:27 *C 38.180 62.503 +*N chanx_left_in[17]:28 *C 38.172 62.560 +*N chanx_left_in[17]:29 *C 17.480 62.560 +*N chanx_left_in[17]:30 *C 17.480 63.240 +*N chanx_left_in[17]:31 *C 13.800 63.240 +*N chanx_left_in[17]:32 *C 13.800 62.560 + +*CAP +0 chanx_left_in[17] 0.00070522 +1 BUFT_P_102:A 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_2_:A0 1e-06 +3 mux_bottom_ipin_1\/mux_l2_in_2_:A0 1e-06 +4 chanx_left_in[17]:4 7.044696e-05 +5 chanx_left_in[17]:5 6.974253e-05 +6 chanx_left_in[17]:6 6.974253e-05 +7 chanx_left_in[17]:7 0.0001330533 +8 chanx_left_in[17]:8 0.0001330533 +9 chanx_left_in[17]:9 0.0001451884 +10 chanx_left_in[17]:10 0.0001451884 +11 chanx_left_in[17]:11 0.0003934302 +12 chanx_left_in[17]:12 0.0003934302 +13 chanx_left_in[17]:13 0.0001462368 +14 chanx_left_in[17]:14 0.0001801226 +15 chanx_left_in[17]:15 0.000334565 +16 chanx_left_in[17]:16 0.000334565 +17 chanx_left_in[17]:17 0.0008163367 +18 chanx_left_in[17]:18 0.0008163367 +19 chanx_left_in[17]:19 0.001862277 +20 chanx_left_in[17]:20 0.001862277 +21 chanx_left_in[17]:21 0.00054207 +22 chanx_left_in[17]:22 0.00054207 +23 chanx_left_in[17]:23 4.137986e-05 +24 chanx_left_in[17]:24 0.0003752706 +25 chanx_left_in[17]:25 0.0003380518 +26 chanx_left_in[17]:26 0.0003792064 +27 chanx_left_in[17]:27 0.0003792064 +28 chanx_left_in[17]:28 0.0007992733 +29 chanx_left_in[17]:29 0.0008572615 +30 chanx_left_in[17]:30 0.0003920689 +31 chanx_left_in[17]:31 0.0003971274 +32 chanx_left_in[17]:32 0.0007682666 +33 chanx_left_in[17] chanx_left_in[13] 6.021373e-05 +34 chanx_left_in[17]:21 chanx_left_in[13]:13 3.216857e-05 +35 chanx_left_in[17]:21 chanx_left_in[13]:17 0.001146893 +36 chanx_left_in[17]:20 chanx_left_in[13]:16 1.536253e-05 +37 chanx_left_in[17]:19 chanx_left_in[13]:15 1.536253e-05 +38 chanx_left_in[17]:22 chanx_left_in[13]:14 3.216857e-05 +39 chanx_left_in[17]:22 chanx_left_in[13]:21 0.001146893 +40 chanx_left_in[17]:32 chanx_left_in[13]:25 6.021373e-05 +41 chanx_left_in[17]:21 chanx_right_in[11]:30 0.001300123 +42 chanx_left_in[17]:24 chanx_right_in[11]:25 4.507524e-05 +43 chanx_left_in[17]:24 chanx_right_in[11]:23 0.0002651345 +44 chanx_left_in[17]:22 chanx_right_in[11]:29 0.001300123 +45 chanx_left_in[17]:25 chanx_right_in[11]:26 4.507524e-05 +46 chanx_left_in[17]:25 chanx_right_in[11]:22 0.0002651345 +47 chanx_left_in[17]:16 chanx_right_in[16]:22 0.0001997212 +48 chanx_left_in[17]:16 chanx_right_in[16]:23 3.896868e-05 +49 chanx_left_in[17]:15 chanx_right_in[16]:22 3.896868e-05 +50 chanx_left_in[17]:15 chanx_right_in[16]:17 0.0001997212 +51 chanx_left_in[17]:12 chanx_right_in[16]:22 1.620767e-05 +52 chanx_left_in[17]:11 chanx_right_in[16]:17 1.620767e-05 +53 chanx_left_in[17] chanx_right_in[17]:9 1.606996e-05 +54 chanx_left_in[17]:8 chanx_right_in[17]:19 7.770729e-06 +55 chanx_left_in[17]:7 chanx_right_in[17]:20 7.770729e-06 +56 chanx_left_in[17]:28 chanx_right_in[17]:10 0.0004497387 +57 chanx_left_in[17]:32 chanx_right_in[17]:10 1.606996e-05 +58 chanx_left_in[17]:31 chanx_right_in[17]:9 1.516407e-05 +59 chanx_left_in[17]:30 chanx_right_in[17]:10 1.516407e-05 +60 chanx_left_in[17]:29 chanx_right_in[17]:9 0.0004497387 +61 chanx_left_in[17]:28 chanx_right_in[19]:21 0.0005246174 +62 chanx_left_in[17]:29 chanx_right_in[19]:20 0.0005246174 +63 chanx_left_in[17] mux_tree_tapbuf_size10_5_sram[2]:18 0.0001916107 +64 chanx_left_in[17]:32 mux_tree_tapbuf_size10_5_sram[2]:19 0.0001916107 +65 chanx_left_in[17]:31 mux_tree_tapbuf_size10_5_sram[2]:18 6.809459e-06 +66 chanx_left_in[17]:30 mux_tree_tapbuf_size10_5_sram[2]:19 6.809459e-06 +67 chanx_left_in[17]:30 mux_tree_tapbuf_size10_5_sram[2]:21 6.505833e-06 +68 chanx_left_in[17]:29 mux_tree_tapbuf_size10_5_sram[2]:20 6.505833e-06 +69 chanx_left_in[17]:8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.816258e-05 +70 chanx_left_in[17]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.816258e-05 +71 chanx_left_in[17]:20 optlc_net_108:35 0.0002636022 +72 chanx_left_in[17]:19 optlc_net_108:36 0.0002636022 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:32 0.0019693 +1 chanx_left_in[17]:21 chanx_left_in[17]:20 0.00341 +2 chanx_left_in[17]:21 chanx_left_in[17]:8 0.00341 +3 chanx_left_in[17]:20 chanx_left_in[17]:19 0.00543085 +4 chanx_left_in[17]:18 chanx_left_in[17]:17 0.001653225 +5 chanx_left_in[17]:19 chanx_left_in[17]:18 0.00341 +6 chanx_left_in[17]:16 chanx_left_in[17]:15 0.00780134 +7 chanx_left_in[17]:17 chanx_left_in[17]:16 0.00341 +8 chanx_left_in[17]:14 chanx_left_in[17]:13 0.002013393 +9 chanx_left_in[17]:15 chanx_left_in[17]:14 0.0045 +10 chanx_left_in[17]:13 chanx_left_in[17]:12 0.0045 +11 chanx_left_in[17]:12 chanx_left_in[17]:11 0.007205358 +12 chanx_left_in[17]:10 chanx_left_in[17]:9 0.002390625 +13 chanx_left_in[17]:11 chanx_left_in[17]:10 0.0045 +14 chanx_left_in[17]:9 BUFT_P_102:A 0.152 +15 chanx_left_in[17]:24 chanx_left_in[17]:23 0.0045 +16 chanx_left_in[17]:24 chanx_left_in[17]:4 0.0001807065 +17 chanx_left_in[17]:23 chanx_left_in[17]:22 0.00341 +18 chanx_left_in[17]:22 chanx_left_in[17]:21 0.00367305 +19 chanx_left_in[17]:8 chanx_left_in[17]:7 0.002640625 +20 chanx_left_in[17]:6 chanx_left_in[17]:5 0.0005959822 +21 chanx_left_in[17]:7 chanx_left_in[17]:6 0.0045 +22 chanx_left_in[17]:5 mux_bottom_ipin_13\/mux_l2_in_2_:A0 0.152 +23 chanx_left_in[17]:4 mux_bottom_ipin_1\/mux_l2_in_2_:A0 0.152 +24 chanx_left_in[17]:25 chanx_left_in[17]:24 0.007392857 +25 chanx_left_in[17]:26 chanx_left_in[17]:25 0.0045 +26 chanx_left_in[17]:27 chanx_left_in[17]:26 0.005979911 +27 chanx_left_in[17]:28 chanx_left_in[17]:27 0.00341 +28 chanx_left_in[17]:32 chanx_left_in[17]:31 0.0001065333 +29 chanx_left_in[17]:31 chanx_left_in[17]:30 0.0005765333 +30 chanx_left_in[17]:30 chanx_left_in[17]:29 0.0001065333 +31 chanx_left_in[17]:29 chanx_left_in[17]:28 0.003241825 + +*END + +*D_NET chanx_left_in[18] 0.01690615 //LENGTH 116.150 LUMPCC 0.006303002 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 20.400 +*I mux_bottom_ipin_6\/mux_l2_in_2_:A0 I *L 0.001631 *C 48.640 21.080 +*I mux_bottom_ipin_14\/mux_l2_in_2_:A0 I *L 0.001631 *C 74.695 17.340 +*I FTB_19__18:A I *L 0.001767 *C 93.380 9.520 +*I mux_bottom_ipin_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 8.570 26.180 +*N chanx_left_in[18]:5 *C 8.607 26.180 +*N chanx_left_in[18]:6 *C 9.155 26.180 +*N chanx_left_in[18]:7 *C 9.200 26.135 +*N chanx_left_in[18]:8 *C 93.418 9.520 +*N chanx_left_in[18]:9 *C 93.795 9.520 +*N chanx_left_in[18]:10 *C 93.840 9.565 +*N chanx_left_in[18]:11 *C 93.840 11.515 +*N chanx_left_in[18]:12 *C 93.795 11.560 +*N chanx_left_in[18]:13 *C 75.025 11.560 +*N chanx_left_in[18]:14 *C 74.980 11.605 +*N chanx_left_in[18]:15 *C 74.695 17.340 +*N chanx_left_in[18]:16 *C 74.980 17.340 +*N chanx_left_in[18]:17 *C 74.980 17.340 +*N chanx_left_in[18]:18 *C 74.980 18.303 +*N chanx_left_in[18]:19 *C 74.972 18.360 +*N chanx_left_in[18]:20 *C 48.640 21.080 +*N chanx_left_in[18]:21 *C 48.760 21.035 +*N chanx_left_in[18]:22 *C 48.760 18.418 +*N chanx_left_in[18]:23 *C 48.760 18.360 +*N chanx_left_in[18]:24 *C 9.207 18.360 +*N chanx_left_in[18]:25 *C 9.200 18.418 +*N chanx_left_in[18]:26 *C 9.200 20.400 +*N chanx_left_in[18]:27 *C 9.193 20.400 + +*CAP +0 chanx_left_in[18] 0.0004701123 +1 mux_bottom_ipin_6\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_2_:A0 1e-06 +3 FTB_19__18:A 1e-06 +4 mux_bottom_ipin_8\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[18]:5 7.006997e-05 +6 chanx_left_in[18]:6 7.006997e-05 +7 chanx_left_in[18]:7 0.0003514772 +8 chanx_left_in[18]:8 4.777511e-05 +9 chanx_left_in[18]:9 4.777511e-05 +10 chanx_left_in[18]:10 0.0001211165 +11 chanx_left_in[18]:11 0.0001211165 +12 chanx_left_in[18]:12 0.001267922 +13 chanx_left_in[18]:13 0.001267922 +14 chanx_left_in[18]:14 0.000362138 +15 chanx_left_in[18]:15 4.642519e-05 +16 chanx_left_in[18]:16 5.123945e-05 +17 chanx_left_in[18]:17 0.0004656009 +18 chanx_left_in[18]:18 7.151259e-05 +19 chanx_left_in[18]:19 0.0007278804 +20 chanx_left_in[18]:20 3.067777e-05 +21 chanx_left_in[18]:21 0.000164376 +22 chanx_left_in[18]:22 0.000164376 +23 chanx_left_in[18]:23 0.002129339 +24 chanx_left_in[18]:24 0.001401458 +25 chanx_left_in[18]:25 0.0001438523 +26 chanx_left_in[18]:26 0.0005348064 +27 chanx_left_in[18]:27 0.0004701123 +28 chanx_left_in[18] chanx_right_in[10]:9 0.0001456369 +29 chanx_left_in[18]:7 chanx_right_in[10]:7 7.803052e-08 +30 chanx_left_in[18]:25 chanx_right_in[10]:8 4.218525e-07 +31 chanx_left_in[18]:24 chanx_right_in[10]:14 1.611096e-05 +32 chanx_left_in[18]:24 chanx_right_in[10]:9 0.0008420149 +33 chanx_left_in[18]:22 chanx_right_in[10]:13 3.406634e-06 +34 chanx_left_in[18]:23 chanx_right_in[10]:14 0.001396447 +35 chanx_left_in[18]:23 chanx_right_in[10]:19 4.612614e-05 +36 chanx_left_in[18]:21 chanx_right_in[10]:12 3.406634e-06 +37 chanx_left_in[18]:16 chanx_right_in[10]:15 4.15837e-06 +38 chanx_left_in[18]:17 chanx_right_in[10]:17 5.033507e-07 +39 chanx_left_in[18]:15 chanx_right_in[10]:16 4.15837e-06 +40 chanx_left_in[18]:18 chanx_right_in[10]:18 5.033507e-07 +41 chanx_left_in[18]:19 chanx_right_in[10]:31 3.001518e-05 +42 chanx_left_in[18]:19 chanx_right_in[10]:19 0.0005544325 +43 chanx_left_in[18]:26 chanx_right_in[10]:8 7.803052e-08 +44 chanx_left_in[18]:26 chanx_right_in[10]:7 4.218525e-07 +45 chanx_left_in[18]:27 chanx_right_in[10]:14 0.0001456369 +46 chanx_left_in[18]:24 chanx_right_in[14]:17 0.0002395945 +47 chanx_left_in[18]:24 chanx_right_in[14]:26 0.0003857401 +48 chanx_left_in[18]:24 chanx_right_in[14]:22 0.000162857 +49 chanx_left_in[18]:23 chanx_right_in[14]:30 0.0003857401 +50 chanx_left_in[18]:23 chanx_right_in[14]:26 0.0006614171 +51 chanx_left_in[18]:23 chanx_right_in[14]:22 0.0002395945 +52 chanx_left_in[18]:23 chanx_right_in[14]:31 0.0002679707 +53 chanx_left_in[18]:19 chanx_right_in[14] 0.0002679707 +54 chanx_left_in[18]:19 chanx_right_in[14]:30 0.0004985601 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:27 0.001247458 +1 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0004888393 +2 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0045 +3 chanx_left_in[18]:5 mux_bottom_ipin_8\/mux_l2_in_2_:A0 0.152 +4 chanx_left_in[18]:25 chanx_left_in[18]:24 0.00341 +5 chanx_left_in[18]:24 chanx_left_in[18]:23 0.006196558 +6 chanx_left_in[18]:22 chanx_left_in[18]:21 0.002337054 +7 chanx_left_in[18]:23 chanx_left_in[18]:22 0.00341 +8 chanx_left_in[18]:23 chanx_left_in[18]:19 0.004106625 +9 chanx_left_in[18]:20 mux_bottom_ipin_6\/mux_l2_in_2_:A0 0.152 +10 chanx_left_in[18]:21 chanx_left_in[18]:20 0.0045 +11 chanx_left_in[18]:16 chanx_left_in[18]:15 0.0001548913 +12 chanx_left_in[18]:17 chanx_left_in[18]:16 0.0045 +13 chanx_left_in[18]:17 chanx_left_in[18]:14 0.005120536 +14 chanx_left_in[18]:15 mux_bottom_ipin_14\/mux_l2_in_2_:A0 0.152 +15 chanx_left_in[18]:18 chanx_left_in[18]:17 0.0008593751 +16 chanx_left_in[18]:19 chanx_left_in[18]:18 0.00341 +17 chanx_left_in[18]:26 chanx_left_in[18]:25 0.001770089 +18 chanx_left_in[18]:26 chanx_left_in[18]:7 0.005120536 +19 chanx_left_in[18]:27 chanx_left_in[18]:26 0.00341 +20 chanx_left_in[18]:13 chanx_left_in[18]:12 0.01675893 +21 chanx_left_in[18]:14 chanx_left_in[18]:13 0.0045 +22 chanx_left_in[18]:12 chanx_left_in[18]:11 0.0045 +23 chanx_left_in[18]:11 chanx_left_in[18]:10 0.001741072 +24 chanx_left_in[18]:9 chanx_left_in[18]:8 0.0003370536 +25 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0045 +26 chanx_left_in[18]:8 FTB_19__18:A 0.152 + +*END + +*D_NET chanx_left_in[19] 0.02482597 //LENGTH 176.985 LUMPCC 0.008490849 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 53.040 +*I mux_bottom_ipin_15\/mux_l2_in_2_:A0 I *L 0.001631 *C 90.930 53.720 +*I FTB_20__19:A I *L 0.001767 *C 93.380 6.800 +*I mux_bottom_ipin_7\/mux_l2_in_2_:A0 I *L 0.001631 *C 25.590 55.080 +*I mux_bottom_ipin_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 11.330 55.080 +*N chanx_left_in[19]:5 *C 11.367 55.080 +*N chanx_left_in[19]:6 *C 12.835 55.080 +*N chanx_left_in[19]:7 *C 12.880 55.125 +*N chanx_left_in[19]:8 *C 12.880 56.383 +*N chanx_left_in[19]:9 *C 12.888 56.440 +*N chanx_left_in[19]:10 *C 24.373 56.440 +*N chanx_left_in[19]:11 *C 24.380 56.383 +*N chanx_left_in[19]:12 *C 25.553 55.080 +*N chanx_left_in[19]:13 *C 24.425 55.080 +*N chanx_left_in[19]:14 *C 24.380 55.080 +*N chanx_left_in[19]:15 *C 93.418 6.800 +*N chanx_left_in[19]:16 *C 97.038 6.800 +*N chanx_left_in[19]:17 *C 97.060 7.140 +*N chanx_left_in[19]:18 *C 97.060 7.185 +*N chanx_left_in[19]:19 *C 97.060 8.783 +*N chanx_left_in[19]:20 *C 97.058 8.840 +*N chanx_left_in[19]:21 *C 96.615 8.840 +*N chanx_left_in[19]:22 *C 96.600 8.848 +*N chanx_left_in[19]:23 *C 96.600 48.273 +*N chanx_left_in[19]:24 *C 96.580 48.280 +*N chanx_left_in[19]:25 *C 90.968 53.720 +*N chanx_left_in[19]:26 *C 91.955 53.720 +*N chanx_left_in[19]:27 *C 92.000 53.675 +*N chanx_left_in[19]:28 *C 92.000 48.338 +*N chanx_left_in[19]:29 *C 92.000 48.280 +*N chanx_left_in[19]:30 *C 74.215 48.280 +*N chanx_left_in[19]:31 *C 24.388 48.280 +*N chanx_left_in[19]:32 *C 24.380 48.338 +*N chanx_left_in[19]:33 *C 24.380 53.720 +*N chanx_left_in[19]:34 *C 24.335 53.720 +*N chanx_left_in[19]:35 *C 5.105 53.720 +*N chanx_left_in[19]:36 *C 5.060 53.675 +*N chanx_left_in[19]:37 *C 5.060 53.098 +*N chanx_left_in[19]:38 *C 5.053 53.040 + +*CAP +0 chanx_left_in[19] 0.0002808732 +1 mux_bottom_ipin_15\/mux_l2_in_2_:A0 1e-06 +2 FTB_20__19:A 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_2_:A0 1e-06 +4 mux_bottom_ipin_9\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[19]:5 8.30036e-05 +6 chanx_left_in[19]:6 8.30036e-05 +7 chanx_left_in[19]:7 9.393333e-05 +8 chanx_left_in[19]:8 9.393333e-05 +9 chanx_left_in[19]:9 0.0004784282 +10 chanx_left_in[19]:10 0.0004784282 +11 chanx_left_in[19]:11 9.526015e-05 +12 chanx_left_in[19]:12 9.79487e-05 +13 chanx_left_in[19]:13 9.79487e-05 +14 chanx_left_in[19]:14 0.0002130395 +15 chanx_left_in[19]:15 0.000143434 +16 chanx_left_in[19]:16 0.0001772836 +17 chanx_left_in[19]:17 7.408032e-05 +18 chanx_left_in[19]:18 0.0001059804 +19 chanx_left_in[19]:19 0.0001059804 +20 chanx_left_in[19]:20 4.774597e-05 +21 chanx_left_in[19]:21 4.774597e-05 +22 chanx_left_in[19]:22 0.001855644 +23 chanx_left_in[19]:23 0.001855644 +24 chanx_left_in[19]:24 0.0003969088 +25 chanx_left_in[19]:25 0.0001093576 +26 chanx_left_in[19]:26 0.0001093576 +27 chanx_left_in[19]:27 0.0002869222 +28 chanx_left_in[19]:28 0.0002869222 +29 chanx_left_in[19]:29 0.001099756 +30 chanx_left_in[19]:30 0.002523796 +31 chanx_left_in[19]:31 0.00182095 +32 chanx_left_in[19]:32 0.0001718213 +33 chanx_left_in[19]:33 0.0002870198 +34 chanx_left_in[19]:34 0.001157946 +35 chanx_left_in[19]:35 0.001157946 +36 chanx_left_in[19]:36 6.610058e-05 +37 chanx_left_in[19]:37 6.610058e-05 +38 chanx_left_in[19]:38 0.0002808732 +39 chanx_left_in[19]:27 chanx_left_in[3]:17 2.660659e-05 +40 chanx_left_in[19]:28 chanx_left_in[3]:16 2.660659e-05 +41 chanx_left_in[19]:31 chanx_left_in[3]:42 4.528887e-05 +42 chanx_left_in[19]:31 chanx_left_in[3]:43 5.45343e-06 +43 chanx_left_in[19]:8 chanx_left_in[3]:64 1.612231e-05 +44 chanx_left_in[19]:6 chanx_left_in[3]:65 6.879597e-05 +45 chanx_left_in[19]:7 chanx_left_in[3]:63 1.612231e-05 +46 chanx_left_in[19]:5 chanx_left_in[3]:66 6.879597e-05 +47 chanx_left_in[19]:34 chanx_left_in[3]:60 5.648396e-05 +48 chanx_left_in[19]:34 chanx_left_in[3]:61 6.656878e-05 +49 chanx_left_in[19]:35 chanx_left_in[3]:61 5.648396e-05 +50 chanx_left_in[19]:35 chanx_left_in[3]:62 6.656878e-05 +51 chanx_left_in[19]:30 chanx_left_in[3]:37 4.528887e-05 +52 chanx_left_in[19]:30 chanx_left_in[3]:42 5.45343e-06 +53 chanx_left_in[19]:23 chanx_left_in[4]:11 0.0002027353 +54 chanx_left_in[19]:23 chanx_left_in[4]:20 5.892307e-05 +55 chanx_left_in[19]:22 chanx_left_in[4]:19 5.892307e-05 +56 chanx_left_in[19]:22 chanx_left_in[4]:20 0.0002027353 +57 chanx_left_in[19]:29 chanx_left_in[5]:8 0.0003053373 +58 chanx_left_in[19]:29 chanx_left_in[5]:13 7.958763e-05 +59 chanx_left_in[19]:31 chanx_left_in[5]:13 0.0002188763 +60 chanx_left_in[19]:31 chanx_left_in[5]:14 1.609642e-05 +61 chanx_left_in[19]:24 chanx_left_in[5]:8 7.958763e-05 +62 chanx_left_in[19]:10 chanx_left_in[5]:24 0.000166501 +63 chanx_left_in[19]:10 chanx_left_in[5]:26 0.0001157803 +64 chanx_left_in[19]:9 chanx_left_in[5] 0.0001157803 +65 chanx_left_in[19]:9 chanx_left_in[5]:25 0.000166501 +66 chanx_left_in[19]:30 chanx_left_in[5]:8 0.0002188763 +67 chanx_left_in[19]:30 chanx_left_in[5]:13 0.0003214337 +68 chanx_left_in[19]:31 chanx_left_in[9]:16 1.61753e-05 +69 chanx_left_in[19]:31 chanx_left_in[9]:23 0.0006845057 +70 chanx_left_in[19]:30 chanx_left_in[9]:4 1.61753e-05 +71 chanx_left_in[19]:30 chanx_left_in[9]:22 0.0006845057 +72 chanx_left_in[19] chanx_left_in[13]:22 1.851132e-05 +73 chanx_left_in[19]:10 chanx_left_in[13]:17 0.0001931651 +74 chanx_left_in[19]:10 chanx_left_in[13]:21 4.937318e-05 +75 chanx_left_in[19]:9 chanx_left_in[13]:21 0.0001931651 +76 chanx_left_in[19]:9 chanx_left_in[13]:22 4.937318e-05 +77 chanx_left_in[19]:34 chanx_left_in[13]:21 1.046519e-05 +78 chanx_left_in[19]:35 chanx_left_in[13]:22 1.046519e-05 +79 chanx_left_in[19]:38 chanx_left_in[13]:21 1.851132e-05 +80 chanx_left_in[19]:31 chanx_right_in[9]:15 0.0007316846 +81 chanx_left_in[19]:36 chanx_right_in[9]:9 1.522798e-06 +82 chanx_left_in[19]:37 chanx_right_in[9]:10 1.522798e-06 +83 chanx_left_in[19]:30 chanx_right_in[9]:16 0.0007316846 +84 chanx_left_in[19]:27 prog_clk[0]:223 5.808334e-06 +85 chanx_left_in[19]:27 prog_clk[0]:405 8.854936e-06 +86 chanx_left_in[19]:28 prog_clk[0]:164 5.808334e-06 +87 chanx_left_in[19]:28 prog_clk[0]:223 8.854936e-06 +88 chanx_left_in[19]:29 prog_clk[0]:222 1.060238e-05 +89 chanx_left_in[19]:29 prog_clk[0]:211 0.000154742 +90 chanx_left_in[19]:29 prog_clk[0]:221 5.889756e-05 +91 chanx_left_in[19]:29 prog_clk[0]:216 3.489473e-05 +92 chanx_left_in[19]:31 prog_clk[0]:168 6.545495e-05 +93 chanx_left_in[19]:31 prog_clk[0]:202 5.101549e-05 +94 chanx_left_in[19]:31 prog_clk[0]:183 1.281429e-05 +95 chanx_left_in[19]:30 prog_clk[0]:198 1.281429e-05 +96 chanx_left_in[19]:30 prog_clk[0]:211 5.101549e-05 +97 chanx_left_in[19]:30 prog_clk[0]:221 1.060238e-05 +98 chanx_left_in[19]:30 prog_clk[0]:202 0.000154742 +99 chanx_left_in[19]:30 prog_clk[0]:216 5.889756e-05 +100 chanx_left_in[19]:30 prog_clk[0]:169 6.545495e-05 +101 chanx_left_in[19]:30 prog_clk[0]:212 3.489473e-05 +102 chanx_left_in[19]:29 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001990536 +103 chanx_left_in[19]:30 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001990536 +104 chanx_left_in[19]:34 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.533821e-05 +105 chanx_left_in[19]:35 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.533821e-05 +106 chanx_left_in[19]:32 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.744654e-05 +107 chanx_left_in[19]:34 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.243343e-06 +108 chanx_left_in[19]:33 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.744654e-05 +109 chanx_left_in[19]:35 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.243343e-06 +110 chanx_left_in[19]:32 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001421706 +111 chanx_left_in[19]:14 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.748815e-06 +112 chanx_left_in[19]:33 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.748815e-06 +113 chanx_left_in[19]:33 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001421706 +114 chanx_left_in[19]:32 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 7.107831e-07 +115 chanx_left_in[19]:31 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001214908 +116 chanx_left_in[19]:33 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 7.107831e-07 +117 chanx_left_in[19]:30 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001214908 +118 chanx_left_in[19]:15 ropt_net_145:7 5.494072e-05 +119 chanx_left_in[19]:16 ropt_net_145:6 5.494072e-05 +120 chanx_left_in[19]:19 ropt_net_135:4 3.172904e-06 +121 chanx_left_in[19]:17 ropt_net_135:8 6.630715e-06 +122 chanx_left_in[19]:18 ropt_net_135:5 3.172904e-06 +123 chanx_left_in[19]:15 ropt_net_135:9 5.183299e-05 +124 chanx_left_in[19]:16 ropt_net_135:8 5.183299e-05 +125 chanx_left_in[19]:16 ropt_net_135:7 6.630715e-06 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:38 0.0005988583 +1 chanx_left_in[19]:25 mux_bottom_ipin_15\/mux_l2_in_2_:A0 0.152 +2 chanx_left_in[19]:26 chanx_left_in[19]:25 0.0008816965 +3 chanx_left_in[19]:27 chanx_left_in[19]:26 0.0045 +4 chanx_left_in[19]:28 chanx_left_in[19]:27 0.004765625 +5 chanx_left_in[19]:29 chanx_left_in[19]:28 0.00341 +6 chanx_left_in[19]:29 chanx_left_in[19]:24 0.0007175333 +7 chanx_left_in[19]:32 chanx_left_in[19]:31 0.00341 +8 chanx_left_in[19]:31 chanx_left_in[19]:30 0.007806308 +9 chanx_left_in[19]:24 chanx_left_in[19]:23 0.00341 +10 chanx_left_in[19]:23 chanx_left_in[19]:22 0.006176583 +11 chanx_left_in[19]:21 chanx_left_in[19]:20 6.499219e-05 +12 chanx_left_in[19]:22 chanx_left_in[19]:21 0.00341 +13 chanx_left_in[19]:19 chanx_left_in[19]:18 0.001426339 +14 chanx_left_in[19]:20 chanx_left_in[19]:19 0.00341 +15 chanx_left_in[19]:17 chanx_left_in[19]:16 0.0001847826 +16 chanx_left_in[19]:18 chanx_left_in[19]:17 0.0045 +17 chanx_left_in[19]:15 FTB_20__19:A 0.152 +18 chanx_left_in[19]:13 chanx_left_in[19]:12 0.001006696 +19 chanx_left_in[19]:14 chanx_left_in[19]:13 0.0045 +20 chanx_left_in[19]:14 chanx_left_in[19]:11 0.001162947 +21 chanx_left_in[19]:12 mux_bottom_ipin_7\/mux_l2_in_2_:A0 0.152 +22 chanx_left_in[19]:11 chanx_left_in[19]:10 0.00341 +23 chanx_left_in[19]:10 chanx_left_in[19]:9 0.001799317 +24 chanx_left_in[19]:8 chanx_left_in[19]:7 0.001122768 +25 chanx_left_in[19]:9 chanx_left_in[19]:8 0.00341 +26 chanx_left_in[19]:6 chanx_left_in[19]:5 0.001310268 +27 chanx_left_in[19]:7 chanx_left_in[19]:6 0.0045 +28 chanx_left_in[19]:5 mux_bottom_ipin_9\/mux_l2_in_2_:A0 0.152 +29 chanx_left_in[19]:34 chanx_left_in[19]:33 0.0045 +30 chanx_left_in[19]:33 chanx_left_in[19]:32 0.004805804 +31 chanx_left_in[19]:33 chanx_left_in[19]:14 0.001214286 +32 chanx_left_in[19]:35 chanx_left_in[19]:34 0.01716964 +33 chanx_left_in[19]:36 chanx_left_in[19]:35 0.0045 +34 chanx_left_in[19]:37 chanx_left_in[19]:36 0.000515625 +35 chanx_left_in[19]:38 chanx_left_in[19]:37 0.00341 +36 chanx_left_in[19]:16 chanx_left_in[19]:15 0.003232143 +37 chanx_left_in[19]:30 chanx_left_in[19]:29 0.002786317 + +*END + +*D_NET chanx_right_in[1] 0.02469726 //LENGTH 179.018 LUMPCC 0.005750784 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 103.650 64.600 +*I mux_bottom_ipin_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 78.960 53.380 +*I mux_bottom_ipin_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.975 53.380 +*I mux_bottom_ipin_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.530 58.820 +*I mux_bottom_ipin_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 65.150 53.720 +*I mux_bottom_ipin_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 33.870 53.720 +*I mux_bottom_ipin_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 37.895 53.720 +*I mux_bottom_ipin_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 20.415 47.940 +*I FTB_22__21:A I *L 0.001776 *C 10.120 6.800 +*I mux_bottom_ipin_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 20.990 55.080 +*N chanx_right_in[1]:10 *C 21.027 55.080 +*N chanx_right_in[1]:11 *C 21.575 55.080 +*N chanx_right_in[1]:12 *C 21.620 55.035 +*N chanx_right_in[1]:13 *C 10.158 6.800 +*N chanx_right_in[1]:14 *C 11.455 6.800 +*N chanx_right_in[1]:15 *C 11.500 6.845 +*N chanx_right_in[1]:16 *C 11.500 14.223 +*N chanx_right_in[1]:17 *C 11.503 14.280 +*N chanx_right_in[1]:18 *C 11.945 14.280 +*N chanx_right_in[1]:19 *C 11.960 14.288 +*N chanx_right_in[1]:20 *C 11.960 36.712 +*N chanx_right_in[1]:21 *C 11.980 36.720 +*N chanx_right_in[1]:22 *C 17.473 36.720 +*N chanx_right_in[1]:23 *C 17.480 36.778 +*N chanx_right_in[1]:24 *C 17.480 47.895 +*N chanx_right_in[1]:25 *C 17.525 47.940 +*N chanx_right_in[1]:26 *C 20.415 47.940 +*N chanx_right_in[1]:27 *C 21.575 47.940 +*N chanx_right_in[1]:28 *C 21.620 47.985 +*N chanx_right_in[1]:29 *C 21.620 50.660 +*N chanx_right_in[1]:30 *C 21.665 50.660 +*N chanx_right_in[1]:31 *C 35.375 50.660 +*N chanx_right_in[1]:32 *C 35.420 50.705 +*N chanx_right_in[1]:33 *C 37.858 53.720 +*N chanx_right_in[1]:34 *C 33.907 53.720 +*N chanx_right_in[1]:35 *C 35.420 53.720 +*N chanx_right_in[1]:36 *C 35.420 53.720 +*N chanx_right_in[1]:37 *C 35.428 53.720 +*N chanx_right_in[1]:38 *C 63.933 53.720 +*N chanx_right_in[1]:39 *C 65.112 53.720 +*N chanx_right_in[1]:40 *C 63.985 53.720 +*N chanx_right_in[1]:41 *C 63.940 53.720 +*N chanx_right_in[1]:42 *C 63.940 58.775 +*N chanx_right_in[1]:43 *C 63.985 58.820 +*N chanx_right_in[1]:44 *C 66.530 58.820 +*N chanx_right_in[1]:45 *C 66.530 58.775 +*N chanx_right_in[1]:46 *C 66.530 57.858 +*N chanx_right_in[1]:47 *C 66.538 57.800 +*N chanx_right_in[1]:48 *C 82.938 53.380 +*N chanx_right_in[1]:49 *C 78.998 53.380 +*N chanx_right_in[1]:50 *C 80.960 53.380 +*N chanx_right_in[1]:51 *C 80.960 53.425 +*N chanx_right_in[1]:52 *C 80.960 57.742 +*N chanx_right_in[1]:53 *C 80.960 57.800 +*N chanx_right_in[1]:54 *C 86.460 57.800 +*N chanx_right_in[1]:55 *C 86.480 57.808 +*N chanx_right_in[1]:56 *C 86.480 64.593 +*N chanx_right_in[1]:57 *C 86.500 64.600 + +*CAP +0 chanx_right_in[1] 0.0008016959 +1 mux_bottom_ipin_13\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_ipin_15\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_ipin_1\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_0_:A0 1e-06 +5 mux_bottom_ipin_7\/mux_l1_in_0_:A0 1e-06 +6 mux_bottom_ipin_3\/mux_l1_in_0_:A0 1e-06 +7 mux_bottom_ipin_11\/mux_l1_in_0_:A0 1e-06 +8 FTB_22__21:A 1e-06 +9 mux_bottom_ipin_9\/mux_l1_in_0_:A0 1e-06 +10 chanx_right_in[1]:10 6.913029e-05 +11 chanx_right_in[1]:11 6.913029e-05 +12 chanx_right_in[1]:12 0.0002008775 +13 chanx_right_in[1]:13 7.826567e-05 +14 chanx_right_in[1]:14 7.826567e-05 +15 chanx_right_in[1]:15 0.000405395 +16 chanx_right_in[1]:16 0.000405395 +17 chanx_right_in[1]:17 7.77785e-05 +18 chanx_right_in[1]:18 7.77785e-05 +19 chanx_right_in[1]:19 0.001512057 +20 chanx_right_in[1]:20 0.001512057 +21 chanx_right_in[1]:21 0.0005503907 +22 chanx_right_in[1]:22 0.0005503907 +23 chanx_right_in[1]:23 0.0006347715 +24 chanx_right_in[1]:24 0.0006347715 +25 chanx_right_in[1]:25 0.0001841523 +26 chanx_right_in[1]:26 0.0002947637 +27 chanx_right_in[1]:27 8.170126e-05 +28 chanx_right_in[1]:28 0.0001276049 +29 chanx_right_in[1]:29 0.0003602776 +30 chanx_right_in[1]:30 0.0007433809 +31 chanx_right_in[1]:31 0.0007433809 +32 chanx_right_in[1]:32 0.0002042087 +33 chanx_right_in[1]:33 0.0001582706 +34 chanx_right_in[1]:34 0.0001277718 +35 chanx_right_in[1]:35 0.0003199812 +36 chanx_right_in[1]:36 0.0002414374 +37 chanx_right_in[1]:37 0.001077567 +38 chanx_right_in[1]:38 0.001077567 +39 chanx_right_in[1]:39 9.351624e-05 +40 chanx_right_in[1]:40 9.351624e-05 +41 chanx_right_in[1]:41 0.0003436041 +42 chanx_right_in[1]:42 0.0003087188 +43 chanx_right_in[1]:43 0.0001675955 +44 chanx_right_in[1]:44 0.0002049954 +45 chanx_right_in[1]:45 7.735071e-05 +46 chanx_right_in[1]:46 7.735071e-05 +47 chanx_right_in[1]:47 0.0005668327 +48 chanx_right_in[1]:48 9.36522e-05 +49 chanx_right_in[1]:49 8.334548e-05 +50 chanx_right_in[1]:50 0.0002066763 +51 chanx_right_in[1]:51 0.0002692399 +52 chanx_right_in[1]:52 0.0002692399 +53 chanx_right_in[1]:53 0.0007864988 +54 chanx_right_in[1]:54 0.000219666 +55 chanx_right_in[1]:55 0.0004368844 +56 chanx_right_in[1]:56 0.0004368844 +57 chanx_right_in[1]:57 0.0008016959 +58 chanx_right_in[1]:35 chanx_left_in[1]:43 8.406348e-06 +59 chanx_right_in[1]:35 chanx_left_in[1]:44 4.316238e-06 +60 chanx_right_in[1]:35 chanx_left_in[1]:45 1.564862e-05 +61 chanx_right_in[1]:35 chanx_left_in[1]:46 8.670742e-07 +62 chanx_right_in[1]:43 chanx_left_in[1]:33 1.004958e-05 +63 chanx_right_in[1]:50 chanx_left_in[1]:22 7.258161e-06 +64 chanx_right_in[1]:50 chanx_left_in[1]:24 5.430697e-05 +65 chanx_right_in[1]:50 chanx_left_in[1]:27 6.675696e-05 +66 chanx_right_in[1]:51 chanx_left_in[1]:25 1.474043e-05 +67 chanx_right_in[1]:52 chanx_left_in[1]:26 1.474043e-05 +68 chanx_right_in[1]:48 chanx_left_in[1]:22 3.98615e-05 +69 chanx_right_in[1]:49 chanx_left_in[1]:23 1.444547e-05 +70 chanx_right_in[1]:49 chanx_left_in[1]:24 7.258161e-06 +71 chanx_right_in[1]:49 chanx_left_in[1]:30 6.675696e-05 +72 chanx_right_in[1]:28 chanx_left_in[1]:11 3.106456e-05 +73 chanx_right_in[1]:34 chanx_left_in[1]:45 4.316238e-06 +74 chanx_right_in[1]:34 chanx_left_in[1]:47 8.670742e-07 +75 chanx_right_in[1]:40 chanx_left_in[1]:28 5.325205e-06 +76 chanx_right_in[1]:39 chanx_left_in[1]:29 5.325205e-06 +77 chanx_right_in[1]:33 chanx_left_in[1]:42 8.406348e-06 +78 chanx_right_in[1]:33 chanx_left_in[1]:44 1.564862e-05 +79 chanx_right_in[1]:44 chanx_left_in[1]:32 1.004958e-05 +80 chanx_right_in[1]:12 chanx_left_in[1]:52 2.751362e-05 +81 chanx_right_in[1]:12 chanx_left_in[1]:53 2.2261e-05 +82 chanx_right_in[1]:45 chanx_left_in[1]:34 5.518276e-06 +83 chanx_right_in[1]:46 chanx_left_in[1]:35 5.518276e-06 +84 chanx_right_in[1]:29 chanx_left_in[1]:11 2.751362e-05 +85 chanx_right_in[1]:29 chanx_left_in[1]:52 5.332555e-05 +86 chanx_right_in[1]:36 chanx_left_in[3]:54 3.310716e-06 +87 chanx_right_in[1]:38 chanx_left_in[3]:42 5.11299e-05 +88 chanx_right_in[1]:37 chanx_left_in[3]:43 5.11299e-05 +89 chanx_right_in[1]:31 chanx_left_in[3]:56 0.000305769 +90 chanx_right_in[1]:32 chanx_left_in[3]:55 3.310716e-06 +91 chanx_right_in[1]:30 chanx_left_in[3]:57 0.000305769 +92 chanx_right_in[1]:36 chanx_left_in[7]:27 2.125654e-07 +93 chanx_right_in[1]:38 chanx_left_in[7]:20 0.0003415734 +94 chanx_right_in[1]:38 chanx_left_in[7]:29 8.06013e-05 +95 chanx_right_in[1]:37 chanx_left_in[7]:21 0.0003415734 +96 chanx_right_in[1]:37 chanx_left_in[7]:34 8.06013e-05 +97 chanx_right_in[1]:32 chanx_left_in[7]:28 2.125654e-07 +98 chanx_right_in[1]:54 chanx_left_in[11]:14 0.0001194247 +99 chanx_right_in[1]:53 chanx_left_in[11]:14 0.0003055669 +100 chanx_right_in[1]:53 chanx_left_in[11]:19 0.0001194247 +101 chanx_right_in[1]:47 chanx_left_in[11]:19 0.0003055669 +102 chanx_right_in[1]:54 chanx_left_in[13]:8 5.732781e-06 +103 chanx_right_in[1]:53 chanx_left_in[13]:13 5.732781e-06 +104 chanx_right_in[1]:38 chanx_left_in[13]:17 0.0005919043 +105 chanx_right_in[1]:37 chanx_left_in[13]:21 0.0005919043 +106 chanx_right_in[1]:54 chanx_right_in[11]:30 8.07989e-05 +107 chanx_right_in[1]:53 chanx_right_in[11]:29 8.07989e-05 +108 chanx_right_in[1]:53 chanx_right_in[11]:30 0.0002781733 +109 chanx_right_in[1]:47 chanx_right_in[11]:29 0.0002781733 +110 chanx_right_in[1] chanx_right_in[13] 0.0003866835 +111 chanx_right_in[1]:57 chanx_right_in[13]:25 0.0003866835 +112 chanx_right_in[1]:16 ropt_net_147:7 2.183094e-05 +113 chanx_right_in[1]:16 ropt_net_147:3 1.418007e-07 +114 chanx_right_in[1]:14 ropt_net_147:10 2.850446e-05 +115 chanx_right_in[1]:15 ropt_net_147:8 2.183094e-05 +116 chanx_right_in[1]:15 ropt_net_147:4 1.418007e-07 +117 chanx_right_in[1]:13 ropt_net_147:9 2.850446e-05 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:57 0.002686833 +1 chanx_right_in[1]:54 chanx_right_in[1]:53 0.0008616666 +2 chanx_right_in[1]:55 chanx_right_in[1]:54 0.00341 +3 chanx_right_in[1]:57 chanx_right_in[1]:56 0.00341 +4 chanx_right_in[1]:56 chanx_right_in[1]:55 0.001062983 +5 chanx_right_in[1]:35 chanx_right_in[1]:34 0.001350446 +6 chanx_right_in[1]:35 chanx_right_in[1]:33 0.002176339 +7 chanx_right_in[1]:36 chanx_right_in[1]:35 0.0045 +8 chanx_right_in[1]:36 chanx_right_in[1]:32 0.002691965 +9 chanx_right_in[1]:43 chanx_right_in[1]:42 0.0045 +10 chanx_right_in[1]:42 chanx_right_in[1]:41 0.004513393 +11 chanx_right_in[1]:50 chanx_right_in[1]:49 0.001752232 +12 chanx_right_in[1]:50 chanx_right_in[1]:48 0.001765625 +13 chanx_right_in[1]:51 chanx_right_in[1]:50 0.0045 +14 chanx_right_in[1]:52 chanx_right_in[1]:51 0.003854911 +15 chanx_right_in[1]:53 chanx_right_in[1]:52 0.00341 +16 chanx_right_in[1]:53 chanx_right_in[1]:47 0.002259525 +17 chanx_right_in[1]:48 mux_bottom_ipin_15\/mux_l1_in_0_:A0 0.152 +18 chanx_right_in[1]:49 mux_bottom_ipin_13\/mux_l1_in_0_:A0 0.152 +19 chanx_right_in[1]:27 chanx_right_in[1]:26 0.001035714 +20 chanx_right_in[1]:28 chanx_right_in[1]:27 0.0045 +21 chanx_right_in[1]:25 chanx_right_in[1]:24 0.0045 +22 chanx_right_in[1]:24 chanx_right_in[1]:23 0.00992634 +23 chanx_right_in[1]:23 chanx_right_in[1]:22 0.00341 +24 chanx_right_in[1]:22 chanx_right_in[1]:21 0.0008604916 +25 chanx_right_in[1]:21 chanx_right_in[1]:20 0.00341 +26 chanx_right_in[1]:20 chanx_right_in[1]:19 0.00351325 +27 chanx_right_in[1]:18 chanx_right_in[1]:17 6.499219e-05 +28 chanx_right_in[1]:19 chanx_right_in[1]:18 0.00341 +29 chanx_right_in[1]:16 chanx_right_in[1]:15 0.006587055 +30 chanx_right_in[1]:17 chanx_right_in[1]:16 0.00341 +31 chanx_right_in[1]:14 chanx_right_in[1]:13 0.001158482 +32 chanx_right_in[1]:15 chanx_right_in[1]:14 0.0045 +33 chanx_right_in[1]:13 FTB_22__21:A 0.152 +34 chanx_right_in[1]:34 mux_bottom_ipin_7\/mux_l1_in_0_:A0 0.152 +35 chanx_right_in[1]:40 chanx_right_in[1]:39 0.001006696 +36 chanx_right_in[1]:41 chanx_right_in[1]:40 0.0045 +37 chanx_right_in[1]:41 chanx_right_in[1]:38 0.00341 +38 chanx_right_in[1]:39 mux_bottom_ipin_5\/mux_l1_in_0_:A0 0.152 +39 chanx_right_in[1]:38 chanx_right_in[1]:37 0.004465783 +40 chanx_right_in[1]:37 chanx_right_in[1]:36 0.00341 +41 chanx_right_in[1]:33 mux_bottom_ipin_3\/mux_l1_in_0_:A0 0.152 +42 chanx_right_in[1]:44 mux_bottom_ipin_1\/mux_l1_in_0_:A0 0.152 +43 chanx_right_in[1]:44 chanx_right_in[1]:43 0.002272322 +44 chanx_right_in[1]:11 chanx_right_in[1]:10 0.0004888393 +45 chanx_right_in[1]:12 chanx_right_in[1]:11 0.0045 +46 chanx_right_in[1]:10 mux_bottom_ipin_9\/mux_l1_in_0_:A0 0.152 +47 chanx_right_in[1]:26 mux_bottom_ipin_11\/mux_l1_in_0_:A0 0.152 +48 chanx_right_in[1]:26 chanx_right_in[1]:25 0.002580357 +49 chanx_right_in[1]:45 chanx_right_in[1]:44 0.0045 +50 chanx_right_in[1]:46 chanx_right_in[1]:45 0.0008191965 +51 chanx_right_in[1]:47 chanx_right_in[1]:46 0.00341 +52 chanx_right_in[1]:31 chanx_right_in[1]:30 0.01224107 +53 chanx_right_in[1]:32 chanx_right_in[1]:31 0.0045 +54 chanx_right_in[1]:30 chanx_right_in[1]:29 0.0045 +55 chanx_right_in[1]:29 chanx_right_in[1]:28 0.002388393 +56 chanx_right_in[1]:29 chanx_right_in[1]:12 0.00390625 + +*END + +*D_NET chanx_right_in[4] 0.01863789 //LENGTH 117.080 LUMPCC 0.009041059 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 103.650 11.560 +*I mux_bottom_ipin_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 65.955 22.780 +*I FTB_25__24:A I *L 0.001776 *C 10.120 17.680 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 92.290 22.780 +*I mux_top_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 97.350 22.780 +*N chanx_right_in[4]:5 *C 97.323 22.825 +*N chanx_right_in[4]:6 *C 92.290 22.780 +*N chanx_right_in[4]:7 *C 10.120 17.695 +*N chanx_right_in[4]:8 *C 10.120 18.020 +*N chanx_right_in[4]:9 *C 10.120 18.065 +*N chanx_right_in[4]:10 *C 10.120 23.742 +*N chanx_right_in[4]:11 *C 10.128 23.800 +*N chanx_right_in[4]:12 *C 59.955 23.800 +*N chanx_right_in[4]:13 *C 65.955 22.780 +*N chanx_right_in[4]:14 *C 65.780 22.780 +*N chanx_right_in[4]:15 *C 65.780 22.825 +*N chanx_right_in[4]:16 *C 65.780 23.742 +*N chanx_right_in[4]:17 *C 65.780 23.800 +*N chanx_right_in[4]:18 *C 92.453 23.800 +*N chanx_right_in[4]:19 *C 92.460 23.742 +*N chanx_right_in[4]:20 *C 92.460 22.825 +*N chanx_right_in[4]:21 *C 92.505 22.780 +*N chanx_right_in[4]:22 *C 97.060 22.793 +*N chanx_right_in[4]:23 *C 97.060 23.120 +*N chanx_right_in[4]:24 *C 98.395 23.120 +*N chanx_right_in[4]:25 *C 98.440 23.075 +*N chanx_right_in[4]:26 *C 98.440 11.617 +*N chanx_right_in[4]:27 *C 98.448 11.560 + +*CAP +0 chanx_right_in[4] 0.0003620995 +1 mux_bottom_ipin_4\/mux_l1_in_2_:A0 1e-06 +2 FTB_25__24:A 1e-06 +3 mux_bottom_ipin_0\/mux_l1_in_2_:A0 1e-06 +4 mux_top_ipin_0\/mux_l1_in_2_:A0 1e-06 +5 chanx_right_in[4]:5 1.567559e-05 +6 chanx_right_in[4]:6 5.443606e-05 +7 chanx_right_in[4]:7 3.610868e-05 +8 chanx_right_in[4]:8 7.080984e-05 +9 chanx_right_in[4]:9 0.0003414343 +10 chanx_right_in[4]:10 0.0003414343 +11 chanx_right_in[4]:11 0.001460403 +12 chanx_right_in[4]:12 0.001628844 +13 chanx_right_in[4]:13 5.529117e-05 +14 chanx_right_in[4]:14 5.967201e-05 +15 chanx_right_in[4]:15 7.311493e-05 +16 chanx_right_in[4]:16 7.311493e-05 +17 chanx_right_in[4]:17 0.001223773 +18 chanx_right_in[4]:18 0.001055331 +19 chanx_right_in[4]:19 8.593829e-05 +20 chanx_right_in[4]:20 8.593829e-05 +21 chanx_right_in[4]:21 0.0002619423 +22 chanx_right_in[4]:22 0.0002780901 +23 chanx_right_in[4]:23 0.0001765791 +24 chanx_right_in[4]:24 0.0001506331 +25 chanx_right_in[4]:25 0.0006700368 +26 chanx_right_in[4]:26 0.0006700368 +27 chanx_right_in[4]:27 0.0003620995 +28 chanx_right_in[4]:18 chanx_left_in[0]:32 8.605317e-05 +29 chanx_right_in[4]:18 chanx_left_in[0]:36 0.0001253527 +30 chanx_right_in[4]:11 chanx_left_in[0]:41 0.0001120372 +31 chanx_right_in[4]:17 chanx_left_in[0]:36 0.0001725062 +32 chanx_right_in[4]:17 chanx_left_in[0]:40 0.0001683224 +33 chanx_right_in[4]:12 chanx_left_in[0]:40 0.0001984902 +34 chanx_right_in[4]:12 chanx_left_in[0]:41 4.29697e-05 +35 chanx_right_in[4]:18 chanx_left_in[2]:14 1.069422e-05 +36 chanx_right_in[4]:18 chanx_left_in[2]:28 1.715413e-05 +37 chanx_right_in[4]:18 chanx_left_in[2]:30 0.00093309 +38 chanx_right_in[4]:17 chanx_left_in[2]:13 1.069422e-05 +39 chanx_right_in[4]:17 chanx_left_in[2]:29 1.715413e-05 +40 chanx_right_in[4]:17 chanx_left_in[2]:31 0.00093309 +41 chanx_right_in[4]:20 chanx_left_in[10]:8 2.201679e-07 +42 chanx_right_in[4]:19 chanx_left_in[10]:9 2.201679e-07 +43 chanx_right_in[4]:18 chanx_left_in[10]:30 0.0001718181 +44 chanx_right_in[4]:11 chanx_left_in[10] 0.0002601363 +45 chanx_right_in[4]:11 chanx_left_in[10]:31 0.0002094762 +46 chanx_right_in[4]:11 chanx_left_in[10]:37 0.0007705674 +47 chanx_right_in[4]:17 chanx_left_in[10]:30 0.0001294227 +48 chanx_right_in[4]:17 chanx_left_in[10]:31 0.0001718181 +49 chanx_right_in[4]:12 chanx_left_in[10]:30 0.0002094762 +50 chanx_right_in[4]:12 chanx_left_in[10]:31 0.0001294227 +51 chanx_right_in[4]:12 chanx_left_in[10]:36 0.0007705674 +52 chanx_right_in[4]:12 chanx_left_in[10]:38 0.0002601363 +53 chanx_right_in[4]:11 chanx_left_in[14] 0.0008770335 +54 chanx_right_in[4]:12 chanx_left_in[14]:29 0.0008770335 +55 chanx_right_in[4]:18 chanx_right_in[12] 4.341892e-05 +56 chanx_right_in[4]:10 chanx_right_in[12]:10 8.416748e-06 +57 chanx_right_in[4]:10 chanx_right_in[12]:20 4.404858e-06 +58 chanx_right_in[4]:11 chanx_right_in[12]:21 0.0004782715 +59 chanx_right_in[4]:11 chanx_right_in[12]:25 5.872844e-05 +60 chanx_right_in[4]:9 chanx_right_in[12]:19 4.404858e-06 +61 chanx_right_in[4]:9 chanx_right_in[12]:20 8.416748e-06 +62 chanx_right_in[4]:17 chanx_right_in[12]:34 4.341892e-05 +63 chanx_right_in[4]:12 chanx_right_in[12]:22 0.0004782715 +64 chanx_right_in[4]:12 chanx_right_in[12]:26 5.872844e-05 +65 chanx_right_in[4]:21 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.481009e-05 +66 chanx_right_in[4]:22 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.481009e-05 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:27 0.0008150583 +1 chanx_right_in[4]:21 chanx_right_in[4]:20 0.0045 +2 chanx_right_in[4]:21 chanx_right_in[4]:6 0.0001168478 +3 chanx_right_in[4]:20 chanx_right_in[4]:19 0.0008191965 +4 chanx_right_in[4]:19 chanx_right_in[4]:18 0.00341 +5 chanx_right_in[4]:18 chanx_right_in[4]:17 0.004178692 +6 chanx_right_in[4]:10 chanx_right_in[4]:9 0.005069197 +7 chanx_right_in[4]:11 chanx_right_in[4]:10 0.00341 +8 chanx_right_in[4]:8 chanx_right_in[4]:7 0.0001766304 +9 chanx_right_in[4]:9 chanx_right_in[4]:8 0.0045 +10 chanx_right_in[4]:7 FTB_25__24:A 0.152 +11 chanx_right_in[4]:16 chanx_right_in[4]:15 0.0008191965 +12 chanx_right_in[4]:17 chanx_right_in[4]:16 0.00341 +13 chanx_right_in[4]:17 chanx_right_in[4]:12 0.0009125833 +14 chanx_right_in[4]:14 chanx_right_in[4]:13 9.51087e-05 +15 chanx_right_in[4]:15 chanx_right_in[4]:14 0.0045 +16 chanx_right_in[4]:13 mux_bottom_ipin_4\/mux_l1_in_2_:A0 0.152 +17 chanx_right_in[4]:6 mux_bottom_ipin_0\/mux_l1_in_2_:A0 0.152 +18 chanx_right_in[4]:5 mux_top_ipin_0\/mux_l1_in_2_:A0 0.152 +19 chanx_right_in[4]:24 chanx_right_in[4]:23 0.001191964 +20 chanx_right_in[4]:25 chanx_right_in[4]:24 0.0045 +21 chanx_right_in[4]:26 chanx_right_in[4]:25 0.01022991 +22 chanx_right_in[4]:27 chanx_right_in[4]:26 0.00341 +23 chanx_right_in[4]:22 chanx_right_in[4]:21 0.004066965 +24 chanx_right_in[4]:22 chanx_right_in[4]:5 0.000234375 +25 chanx_right_in[4]:23 chanx_right_in[4]:22 0.0002924108 +26 chanx_right_in[4]:12 chanx_right_in[4]:11 0.007806308 + +*END + +*D_NET chanx_right_in[8] 0.01578812 //LENGTH 116.840 LUMPCC 0.00582487 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 103.650 21.760 +*I mux_bottom_ipin_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 64.305 12.580 +*I BUFT_P_89:A I *L 0.001776 *C 16.100 12.240 +*I mux_bottom_ipin_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 12.710 26.520 +*N chanx_right_in[8]:4 *C 12.748 26.520 +*N chanx_right_in[8]:5 *C 14.215 26.520 +*N chanx_right_in[8]:6 *C 14.260 26.475 +*N chanx_right_in[8]:7 *C 14.260 12.285 +*N chanx_right_in[8]:8 *C 14.305 12.240 +*N chanx_right_in[8]:9 *C 16.100 12.240 +*N chanx_right_in[8]:10 *C 17.675 12.240 +*N chanx_right_in[8]:11 *C 17.720 12.240 +*N chanx_right_in[8]:12 *C 17.727 12.240 +*N chanx_right_in[8]:13 *C 64.392 12.240 +*N chanx_right_in[8]:14 *C 64.400 12.240 +*N chanx_right_in[8]:15 *C 64.305 12.580 +*N chanx_right_in[8]:16 *C 64.400 12.580 +*N chanx_right_in[8]:17 *C 64.400 12.920 +*N chanx_right_in[8]:18 *C 64.407 12.920 +*N chanx_right_in[8]:19 *C 101.653 12.920 +*N chanx_right_in[8]:20 *C 101.660 12.978 +*N chanx_right_in[8]:21 *C 101.660 21.703 +*N chanx_right_in[8]:22 *C 101.668 21.760 + +*CAP +0 chanx_right_in[8] 0.0001639286 +1 mux_bottom_ipin_4\/mux_l2_in_2_:A1 1e-06 +2 BUFT_P_89:A 1e-06 +3 mux_bottom_ipin_8\/mux_l1_in_2_:A0 1e-06 +4 chanx_right_in[8]:4 0.0001424664 +5 chanx_right_in[8]:5 0.0001424664 +6 chanx_right_in[8]:6 0.0008337784 +7 chanx_right_in[8]:7 0.0008337784 +8 chanx_right_in[8]:8 0.0001090056 +9 chanx_right_in[8]:9 0.0002332043 +10 chanx_right_in[8]:10 9.701501e-05 +11 chanx_right_in[8]:11 3.326378e-05 +12 chanx_right_in[8]:12 0.001426802 +13 chanx_right_in[8]:13 0.001426802 +14 chanx_right_in[8]:14 5.174227e-05 +15 chanx_right_in[8]:15 2.833039e-05 +16 chanx_right_in[8]:16 6.716449e-05 +17 chanx_right_in[8]:17 5.261138e-05 +18 chanx_right_in[8]:18 0.001615931 +19 chanx_right_in[8]:19 0.001615932 +20 chanx_right_in[8]:20 0.0004610504 +21 chanx_right_in[8]:21 0.0004610504 +22 chanx_right_in[8]:22 0.0001639286 +23 chanx_right_in[8]:13 chanx_left_in[14]:11 3.850518e-06 +24 chanx_right_in[8]:13 chanx_left_in[14]:15 0.0003670035 +25 chanx_right_in[8]:12 chanx_left_in[14]:12 3.850518e-06 +26 chanx_right_in[8]:12 chanx_left_in[14]:16 0.0003670035 +27 chanx_right_in[8]:18 chanx_right_in[18]:27 4.889377e-05 +28 chanx_right_in[8]:18 chanx_right_in[18]:32 0.0002322574 +29 chanx_right_in[8]:19 chanx_right_in[18] 0.0002322574 +30 chanx_right_in[8]:19 chanx_right_in[18]:32 4.889377e-05 +31 chanx_right_in[8]:6 prog_clk[0]:258 2.570621e-05 +32 chanx_right_in[8]:6 prog_clk[0]:92 2.168364e-05 +33 chanx_right_in[8]:6 prog_clk[0]:96 5.853687e-05 +34 chanx_right_in[8]:7 prog_clk[0]:253 2.570621e-05 +35 chanx_right_in[8]:7 prog_clk[0]:96 2.168364e-05 +36 chanx_right_in[8]:7 prog_clk[0]:95 5.853687e-05 +37 chanx_right_in[8]:14 prog_clk[0]:135 6.121503e-07 +38 chanx_right_in[8]:13 prog_clk[0]:119 7.141571e-05 +39 chanx_right_in[8]:13 prog_clk[0]:117 8.348865e-05 +40 chanx_right_in[8]:13 prog_clk[0]:107 0.0001188372 +41 chanx_right_in[8]:13 prog_clk[0]:112 7.083491e-05 +42 chanx_right_in[8]:13 prog_clk[0]:127 4.85048e-05 +43 chanx_right_in[8]:13 prog_clk[0]:132 0.0002107151 +44 chanx_right_in[8]:13 prog_clk[0]:137 9.807269e-05 +45 chanx_right_in[8]:13 prog_clk[0]:102 8.974847e-05 +46 chanx_right_in[8]:12 prog_clk[0]:122 4.85048e-05 +47 chanx_right_in[8]:12 prog_clk[0]:97 8.974847e-05 +48 chanx_right_in[8]:12 prog_clk[0]:107 7.083491e-05 +49 chanx_right_in[8]:12 prog_clk[0]:112 8.348865e-05 +50 chanx_right_in[8]:12 prog_clk[0]:127 0.0002107151 +51 chanx_right_in[8]:12 prog_clk[0]:132 9.807269e-05 +52 chanx_right_in[8]:12 prog_clk[0]:102 0.0001188372 +53 chanx_right_in[8]:12 prog_clk[0]:118 7.141571e-05 +54 chanx_right_in[8]:17 prog_clk[0]:135 6.121503e-07 +55 chanx_right_in[8]:18 prog_clk[0]:144 4.639553e-05 +56 chanx_right_in[8]:18 prog_clk[0]:77 0.0001750536 +57 chanx_right_in[8]:18 prog_clk[0]:132 0.0001671202 +58 chanx_right_in[8]:18 prog_clk[0]:137 0.0003219246 +59 chanx_right_in[8]:18 prog_clk[0]:143 4.123528e-05 +60 chanx_right_in[8]:19 prog_clk[0]:144 4.123528e-05 +61 chanx_right_in[8]:19 prog_clk[0]:87 4.639553e-05 +62 chanx_right_in[8]:19 prog_clk[0]:76 0.0001750536 +63 chanx_right_in[8]:19 prog_clk[0]:137 0.0001671202 +64 chanx_right_in[8]:19 prog_clk[0]:142 0.0003219246 +65 chanx_right_in[8]:16 prog_clk[0]:136 1.224301e-06 +66 chanx_right_in[8]:13 mux_tree_tapbuf_size10_2_sram[2]:15 0.0006099319 +67 chanx_right_in[8]:12 mux_tree_tapbuf_size10_2_sram[2]:14 0.0006099319 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:22 0.0003105917 +1 chanx_right_in[8]:4 mux_bottom_ipin_8\/mux_l1_in_2_:A0 0.152 +2 chanx_right_in[8]:5 chanx_right_in[8]:4 0.001310268 +3 chanx_right_in[8]:6 chanx_right_in[8]:5 0.0045 +4 chanx_right_in[8]:8 chanx_right_in[8]:7 0.0045 +5 chanx_right_in[8]:7 chanx_right_in[8]:6 0.01266964 +6 chanx_right_in[8]:14 chanx_right_in[8]:13 0.00341 +7 chanx_right_in[8]:13 chanx_right_in[8]:12 0.007310849 +8 chanx_right_in[8]:11 chanx_right_in[8]:10 0.0045 +9 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00341 +10 chanx_right_in[8]:10 chanx_right_in[8]:9 0.00140625 +11 chanx_right_in[8]:17 chanx_right_in[8]:16 0.0001634615 +12 chanx_right_in[8]:18 chanx_right_in[8]:17 0.00341 +13 chanx_right_in[8]:20 chanx_right_in[8]:19 0.00341 +14 chanx_right_in[8]:19 chanx_right_in[8]:18 0.00583505 +15 chanx_right_in[8]:21 chanx_right_in[8]:20 0.007790179 +16 chanx_right_in[8]:22 chanx_right_in[8]:21 0.00341 +17 chanx_right_in[8]:15 mux_bottom_ipin_4\/mux_l2_in_2_:A1 0.152 +18 chanx_right_in[8]:16 chanx_right_in[8]:15 0.0045 +19 chanx_right_in[8]:16 chanx_right_in[8]:14 0.0001634615 +20 chanx_right_in[8]:9 BUFT_P_89:A 0.152 +21 chanx_right_in[8]:9 chanx_right_in[8]:8 0.001602679 + +*END + +*D_NET chanx_right_in[14] 0.01666074 //LENGTH 125.855 LUMPCC 0.00570697 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 103.650 17.680 +*I mux_bottom_ipin_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 70.285 14.620 +*I mux_bottom_ipin_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 32.660 14.620 +*I mux_bottom_ipin_10\/mux_l2_in_3_:A1 I *L 0.00198 *C 25.300 12.580 +*I ropt_mt_inst_718:A I *L 0.001766 *C 3.220 23.120 +*N chanx_right_in[14]:5 *C 3.258 23.120 +*N chanx_right_in[14]:6 *C 4.095 23.120 +*N chanx_right_in[14]:7 *C 4.140 23.075 +*N chanx_right_in[14]:8 *C 4.140 14.325 +*N chanx_right_in[14]:9 *C 4.185 14.280 +*N chanx_right_in[14]:10 *C 12.760 14.280 +*N chanx_right_in[14]:11 *C 12.873 14.325 +*N chanx_right_in[14]:12 *C 12.880 14.915 +*N chanx_right_in[14]:13 *C 12.925 14.960 +*N chanx_right_in[14]:14 *C 13.800 14.960 +*N chanx_right_in[14]:15 *C 13.800 15.005 +*N chanx_right_in[14]:16 *C 13.800 16.943 +*N chanx_right_in[14]:17 *C 13.808 17.000 +*N chanx_right_in[14]:18 *C 25.300 12.595 +*N chanx_right_in[14]:19 *C 25.300 12.920 +*N chanx_right_in[14]:20 *C 25.300 12.965 +*N chanx_right_in[14]:21 *C 25.300 16.943 +*N chanx_right_in[14]:22 *C 25.300 17.000 +*N chanx_right_in[14]:23 *C 32.660 14.620 +*N chanx_right_in[14]:24 *C 32.660 14.665 +*N chanx_right_in[14]:25 *C 32.660 16.943 +*N chanx_right_in[14]:26 *C 32.660 17.000 +*N chanx_right_in[14]:27 *C 70.285 14.620 +*N chanx_right_in[14]:28 *C 70.380 14.665 +*N chanx_right_in[14]:29 *C 70.380 16.943 +*N chanx_right_in[14]:30 *C 70.380 17.008 +*N chanx_right_in[14]:31 *C 70.380 17.680 + +*CAP +0 chanx_right_in[14] 0.001530904 +1 mux_bottom_ipin_4\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_2\/mux_l2_in_3_:A1 1e-06 +3 mux_bottom_ipin_10\/mux_l2_in_3_:A1 1e-06 +4 ropt_mt_inst_718:A 1e-06 +5 chanx_right_in[14]:5 4.339968e-05 +6 chanx_right_in[14]:6 4.339968e-05 +7 chanx_right_in[14]:7 0.0004300101 +8 chanx_right_in[14]:8 0.0004300101 +9 chanx_right_in[14]:9 0.0005678745 +10 chanx_right_in[14]:10 0.0005678745 +11 chanx_right_in[14]:11 5.56419e-05 +12 chanx_right_in[14]:12 5.56419e-05 +13 chanx_right_in[14]:13 8.399082e-05 +14 chanx_right_in[14]:14 0.000118997 +15 chanx_right_in[14]:15 0.0001618496 +16 chanx_right_in[14]:16 0.0001618496 +17 chanx_right_in[14]:17 0.0004528544 +18 chanx_right_in[14]:18 3.459743e-05 +19 chanx_right_in[14]:19 6.631421e-05 +20 chanx_right_in[14]:20 0.0002357109 +21 chanx_right_in[14]:21 0.0002357109 +22 chanx_right_in[14]:22 0.0007671965 +23 chanx_right_in[14]:23 3.305355e-05 +24 chanx_right_in[14]:24 0.0001541079 +25 chanx_right_in[14]:25 0.0001541079 +26 chanx_right_in[14]:26 0.001453361 +27 chanx_right_in[14]:27 2.898585e-05 +28 chanx_right_in[14]:28 0.0001560604 +29 chanx_right_in[14]:29 0.0001560604 +30 chanx_right_in[14]:30 0.001189157 +31 chanx_right_in[14]:31 0.001581043 +32 chanx_right_in[14] chanx_left_in[18]:19 0.0002679707 +33 chanx_right_in[14]:30 chanx_left_in[18]:19 0.0004985601 +34 chanx_right_in[14]:30 chanx_left_in[18]:23 0.0003857401 +35 chanx_right_in[14]:17 chanx_left_in[18]:24 0.0002395945 +36 chanx_right_in[14]:26 chanx_left_in[18]:23 0.0006614171 +37 chanx_right_in[14]:26 chanx_left_in[18]:24 0.0003857401 +38 chanx_right_in[14]:22 chanx_left_in[18]:23 0.0002395945 +39 chanx_right_in[14]:22 chanx_left_in[18]:24 0.000162857 +40 chanx_right_in[14]:31 chanx_left_in[18]:23 0.0002679707 +41 chanx_right_in[14] chanx_right_in[10] 0.0002035591 +42 chanx_right_in[14] chanx_right_in[10]:19 2.460818e-06 +43 chanx_right_in[14] chanx_right_in[10]:28 4.802057e-05 +44 chanx_right_in[14] chanx_right_in[10]:31 0.0001103834 +45 chanx_right_in[14]:8 chanx_right_in[10]:8 6.708814e-07 +46 chanx_right_in[14]:7 chanx_right_in[10]:7 6.708814e-07 +47 chanx_right_in[14]:31 chanx_right_in[10]:14 2.460818e-06 +48 chanx_right_in[14]:31 chanx_right_in[10]:19 0.0001103834 +49 chanx_right_in[14]:31 chanx_right_in[10]:27 4.802057e-05 +50 chanx_right_in[14]:31 chanx_right_in[10]:32 0.0002035591 +51 chanx_right_in[14] prog_clk[0]:144 1.928361e-05 +52 chanx_right_in[14] prog_clk[0]:87 1.400636e-05 +53 chanx_right_in[14] prog_clk[0]:76 1.619552e-05 +54 chanx_right_in[14] prog_clk[0]:142 3.342319e-06 +55 chanx_right_in[14]:30 prog_clk[0]:119 0.0001295416 +56 chanx_right_in[14]:30 prog_clk[0]:117 5.158932e-05 +57 chanx_right_in[14]:30 prog_clk[0]:112 3.245698e-05 +58 chanx_right_in[14]:30 prog_clk[0]:127 4.192224e-06 +59 chanx_right_in[14]:30 prog_clk[0]:132 5.553264e-05 +60 chanx_right_in[14]:30 prog_clk[0]:137 5.918102e-05 +61 chanx_right_in[14]:30 prog_clk[0]:142 2.955275e-05 +62 chanx_right_in[14]:17 prog_clk[0]:97 8.716025e-05 +63 chanx_right_in[14]:17 prog_clk[0]:102 2.711074e-05 +64 chanx_right_in[14]:25 prog_clk[0]:106 2.956127e-08 +65 chanx_right_in[14]:26 prog_clk[0]:122 4.192224e-06 +66 chanx_right_in[14]:26 prog_clk[0]:107 7.719224e-05 +67 chanx_right_in[14]:26 prog_clk[0]:112 6.735179e-05 +68 chanx_right_in[14]:26 prog_clk[0]:127 5.553264e-05 +69 chanx_right_in[14]:26 prog_clk[0]:132 5.918102e-05 +70 chanx_right_in[14]:26 prog_clk[0]:137 2.955275e-05 +71 chanx_right_in[14]:26 prog_clk[0]:118 0.0001295416 +72 chanx_right_in[14]:24 prog_clk[0]:105 2.956127e-08 +73 chanx_right_in[14]:21 prog_clk[0]:101 1.362812e-06 +74 chanx_right_in[14]:22 prog_clk[0]:107 4.28732e-05 +75 chanx_right_in[14]:22 prog_clk[0]:102 0.0001318955 +76 chanx_right_in[14]:20 prog_clk[0]:100 1.362812e-06 +77 chanx_right_in[14]:31 prog_clk[0]:144 1.400636e-05 +78 chanx_right_in[14]:31 prog_clk[0]:77 1.619552e-05 +79 chanx_right_in[14]:31 prog_clk[0]:137 3.342319e-06 +80 chanx_right_in[14]:31 prog_clk[0]:143 1.928361e-05 +81 chanx_right_in[14]:30 mux_tree_tapbuf_size8_2_sram[0]:8 0.000176938 +82 chanx_right_in[14]:26 mux_tree_tapbuf_size8_2_sram[0]:7 0.000176938 +83 chanx_right_in[14]:10 ropt_net_148:2 7.252533e-06 +84 chanx_right_in[14]:10 ropt_net_148:4 5.96859e-05 +85 chanx_right_in[14]:9 ropt_net_148:5 5.96859e-05 +86 chanx_right_in[14]:9 ropt_net_148:3 7.252533e-06 +87 chanx_right_in[14]:8 ropt_net_156:5 6.937195e-05 +88 chanx_right_in[14]:6 ropt_net_156:8 2.938468e-05 +89 chanx_right_in[14]:7 ropt_net_156:6 6.937195e-05 +90 chanx_right_in[14]:5 ropt_net_156:7 2.938468e-05 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:31 0.0052123 +1 chanx_right_in[14]:29 chanx_right_in[14]:28 0.002033482 +2 chanx_right_in[14]:30 chanx_right_in[14]:29 0.00341 +3 chanx_right_in[14]:30 chanx_right_in[14]:26 0.005909466 +4 chanx_right_in[14]:27 mux_bottom_ipin_4\/mux_l2_in_3_:A1 0.152 +5 chanx_right_in[14]:28 chanx_right_in[14]:27 0.0045 +6 chanx_right_in[14]:16 chanx_right_in[14]:15 0.001729911 +7 chanx_right_in[14]:17 chanx_right_in[14]:16 0.00341 +8 chanx_right_in[14]:14 chanx_right_in[14]:13 0.00078125 +9 chanx_right_in[14]:15 chanx_right_in[14]:14 0.0045 +10 chanx_right_in[14]:13 chanx_right_in[14]:12 0.0045 +11 chanx_right_in[14]:12 chanx_right_in[14]:11 0.0005267857 +12 chanx_right_in[14]:10 chanx_right_in[14]:9 0.00765625 +13 chanx_right_in[14]:11 chanx_right_in[14]:10 0.0045 +14 chanx_right_in[14]:9 chanx_right_in[14]:8 0.0045 +15 chanx_right_in[14]:8 chanx_right_in[14]:7 0.0078125 +16 chanx_right_in[14]:6 chanx_right_in[14]:5 0.0007477679 +17 chanx_right_in[14]:7 chanx_right_in[14]:6 0.0045 +18 chanx_right_in[14]:5 ropt_mt_inst_718:A 0.152 +19 chanx_right_in[14]:25 chanx_right_in[14]:24 0.002033482 +20 chanx_right_in[14]:26 chanx_right_in[14]:25 0.00341 +21 chanx_right_in[14]:26 chanx_right_in[14]:22 0.001153067 +22 chanx_right_in[14]:23 mux_bottom_ipin_2\/mux_l2_in_3_:A1 0.152 +23 chanx_right_in[14]:24 chanx_right_in[14]:23 0.0045 +24 chanx_right_in[14]:21 chanx_right_in[14]:20 0.003551339 +25 chanx_right_in[14]:22 chanx_right_in[14]:21 0.00341 +26 chanx_right_in[14]:22 chanx_right_in[14]:17 0.001800492 +27 chanx_right_in[14]:19 chanx_right_in[14]:18 0.0001766304 +28 chanx_right_in[14]:20 chanx_right_in[14]:19 0.0045 +29 chanx_right_in[14]:18 mux_bottom_ipin_10\/mux_l2_in_3_:A1 0.152 +30 chanx_right_in[14]:31 chanx_right_in[14]:30 0.0001053583 + +*END + +*D_NET ropt_net_112 0.003599514 //LENGTH 33.515 LUMPCC 0.0001717335 DR + +*CONN +*I mux_bottom_ipin_0\/BUFT_RR_57:X O *L 0 *C 59.340 72.420 +*I ropt_mt_inst_711:A I *L 0.001766 *C 35.265 69.360 +*N ropt_net_112:2 *C 35.265 69.360 +*N ropt_net_112:3 *C 35.420 69.360 +*N ropt_net_112:4 *C 35.420 69.405 +*N ropt_net_112:5 *C 35.420 74.415 +*N ropt_net_112:6 *C 35.420 74.460 +*N ropt_net_112:7 *C 35.420 74.800 +*N ropt_net_112:8 *C 54.280 74.800 +*N ropt_net_112:9 *C 54.280 74.460 +*N ropt_net_112:10 *C 54.280 74.415 +*N ropt_net_112:11 *C 54.280 72.465 +*N ropt_net_112:12 *C 54.325 72.420 +*N ropt_net_112:13 *C 59.303 72.420 + +*CAP +0 mux_bottom_ipin_0\/BUFT_RR_57:X 1e-06 +1 ropt_mt_inst_711:A 1e-06 +2 ropt_net_112:2 5.055336e-05 +3 ropt_net_112:3 5.093282e-05 +4 ropt_net_112:4 0.0002772445 +5 ropt_net_112:5 0.0002772445 +6 ropt_net_112:6 6.204705e-05 +7 ropt_net_112:7 0.0009484094 +8 ropt_net_112:8 0.0009436565 +9 ropt_net_112:9 5.089696e-05 +10 ropt_net_112:10 0.0001048632 +11 ropt_net_112:11 0.0001048632 +12 ropt_net_112:12 0.0002775344 +13 ropt_net_112:13 0.0002775344 +14 ropt_net_112:5 top_grid_pin_18_[0] 8.586673e-05 +15 ropt_net_112:4 top_grid_pin_18_[0]:2 8.586673e-05 + +*RES +0 mux_bottom_ipin_0\/BUFT_RR_57:X ropt_net_112:13 0.152 +1 ropt_net_112:13 ropt_net_112:12 0.004444197 +2 ropt_net_112:12 ropt_net_112:11 0.0045 +3 ropt_net_112:11 ropt_net_112:10 0.001741072 +4 ropt_net_112:9 ropt_net_112:8 0.0003035715 +5 ropt_net_112:10 ropt_net_112:9 0.0045 +6 ropt_net_112:6 ropt_net_112:5 0.0045 +7 ropt_net_112:5 ropt_net_112:4 0.004473215 +8 ropt_net_112:3 ropt_net_112:2 8.423914e-05 +9 ropt_net_112:4 ropt_net_112:3 0.0045 +10 ropt_net_112:2 ropt_mt_inst_711:A 0.152 +11 ropt_net_112:7 ropt_net_112:6 0.0003035715 +12 ropt_net_112:8 ropt_net_112:7 0.01683929 + +*END + +*D_NET top_grid_pin_18_[0] 0.0007297333 //LENGTH 5.400 LUMPCC 0.0002935176 DR + +*CONN +*I mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 33.120 71.740 +*P top_grid_pin_18_[0] O *L 0.7423 *C 34.960 74.835 +*N top_grid_pin_18_[0]:2 *C 34.960 71.785 +*N top_grid_pin_18_[0]:3 *C 34.915 71.740 +*N top_grid_pin_18_[0]:4 *C 33.157 71.740 + +*CAP +0 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_18_[0] 0.0001055326 +2 top_grid_pin_18_[0]:2 0.0001055326 +3 top_grid_pin_18_[0]:3 0.0001120752 +4 top_grid_pin_18_[0]:4 0.0001120752 +5 top_grid_pin_18_[0] ropt_net_112:5 8.586673e-05 +6 top_grid_pin_18_[0]:2 ropt_net_112:4 8.586673e-05 +7 top_grid_pin_18_[0] ropt_net_161:3 1.803144e-05 +8 top_grid_pin_18_[0]:3 ropt_net_161:6 4.286064e-05 +9 top_grid_pin_18_[0]:2 ropt_net_161:4 1.803144e-05 +10 top_grid_pin_18_[0]:4 ropt_net_161:5 4.286064e-05 + +*RES +0 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_18_[0]:4 0.152 +1 top_grid_pin_18_[0]:3 top_grid_pin_18_[0]:2 0.0045 +2 top_grid_pin_18_[0]:2 top_grid_pin_18_[0] 0.002723214 +3 top_grid_pin_18_[0]:4 top_grid_pin_18_[0]:3 0.001569197 + +*END + +*D_NET top_grid_pin_23_[0] 0.0009244231 //LENGTH 6.550 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 18.400 72.080 +*P top_grid_pin_23_[0] O *L 0.7423 *C 15.180 74.835 +*N top_grid_pin_23_[0]:2 *C 15.180 72.465 +*N top_grid_pin_23_[0]:3 *C 15.225 72.420 +*N top_grid_pin_23_[0]:4 *C 18.400 72.420 +*N top_grid_pin_23_[0]:5 *C 18.400 72.080 + +*CAP +0 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_23_[0] 0.0001532028 +2 top_grid_pin_23_[0]:2 0.0001532028 +3 top_grid_pin_23_[0]:3 0.0002733841 +4 top_grid_pin_23_[0]:4 0.0002967689 +5 top_grid_pin_23_[0]:5 4.686448e-05 + +*RES +0 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_23_[0]:5 0.152 +1 top_grid_pin_23_[0]:3 top_grid_pin_23_[0]:2 0.0045 +2 top_grid_pin_23_[0]:2 top_grid_pin_23_[0] 0.002116072 +3 top_grid_pin_23_[0]:5 top_grid_pin_23_[0]:4 0.0003035715 +4 top_grid_pin_23_[0]:4 top_grid_pin_23_[0]:3 0.002834822 + +*END + +*D_NET top_grid_pin_31_[0] 0.0006911801 //LENGTH 6.060 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 75.900 69.700 +*P top_grid_pin_31_[0] O *L 0.7423 *C 75.440 74.835 +*N top_grid_pin_31_[0]:2 *C 75.440 69.745 +*N top_grid_pin_31_[0]:3 *C 75.485 69.700 +*N top_grid_pin_31_[0]:4 *C 75.862 69.700 + +*CAP +0 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_31_[0] 0.000298193 +2 top_grid_pin_31_[0]:2 0.000298193 +3 top_grid_pin_31_[0]:3 4.689712e-05 +4 top_grid_pin_31_[0]:4 4.689712e-05 + +*RES +0 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_31_[0]:4 0.152 +1 top_grid_pin_31_[0]:3 top_grid_pin_31_[0]:2 0.0045 +2 top_grid_pin_31_[0]:2 top_grid_pin_31_[0] 0.004544643 +3 top_grid_pin_31_[0]:4 top_grid_pin_31_[0]:3 0.0003370536 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.003534604 //LENGTH 27.330 LUMPCC 0.0008546652 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 88.625 42.160 +*I mem_bottom_ipin_0\/FTB_1__40:A I *L 0.001746 *C 72.680 42.160 +*I mux_bottom_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 83.360 36.720 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 83.398 36.720 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 86.895 36.720 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 86.940 36.765 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 72.703 42.133 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 72.715 41.820 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 79.535 41.820 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 79.580 41.820 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 79.580 41.480 +*N mux_tree_tapbuf_size10_0_sram[3]:11 *C 79.588 41.480 +*N mux_tree_tapbuf_size10_0_sram[3]:12 *C 86.933 41.480 +*N mux_tree_tapbuf_size10_0_sram[3]:13 *C 86.940 41.480 +*N mux_tree_tapbuf_size10_0_sram[3]:14 *C 86.940 42.115 +*N mux_tree_tapbuf_size10_0_sram[3]:15 *C 86.985 42.160 +*N mux_tree_tapbuf_size10_0_sram[3]:16 *C 88.588 42.160 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_0\/FTB_1__40:A 1e-06 +2 mux_bottom_ipin_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 0.0001870468 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001870468 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0002555999 +6 mux_tree_tapbuf_size10_0_sram[3]:6 3.288992e-05 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0004533768 +8 mux_tree_tapbuf_size10_0_sram[3]:8 0.0004204868 +9 mux_tree_tapbuf_size10_0_sram[3]:9 5.123895e-05 +10 mux_tree_tapbuf_size10_0_sram[3]:10 5.515667e-05 +11 mux_tree_tapbuf_size10_0_sram[3]:11 0.0001727327 +12 mux_tree_tapbuf_size10_0_sram[3]:12 0.0001727327 +13 mux_tree_tapbuf_size10_0_sram[3]:13 0.0003376958 +14 mux_tree_tapbuf_size10_0_sram[3]:14 4.450598e-05 +15 mux_tree_tapbuf_size10_0_sram[3]:15 0.0001532146 +16 mux_tree_tapbuf_size10_0_sram[3]:16 0.0001532146 +17 mux_tree_tapbuf_size10_0_sram[3]:12 chanx_left_in[15]:13 0.0001832202 +18 mux_tree_tapbuf_size10_0_sram[3]:11 chanx_left_in[15]:14 0.0001832202 +19 mux_tree_tapbuf_size10_0_sram[3]:12 chanx_right_in[15]:30 0.0001879752 +20 mux_tree_tapbuf_size10_0_sram[3]:11 chanx_right_in[15]:29 0.0001879752 +21 mux_tree_tapbuf_size10_0_sram[3]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.846515e-06 +22 mux_tree_tapbuf_size10_0_sram[3]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.229071e-05 +23 mux_tree_tapbuf_size10_0_sram[3]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.846515e-06 +24 mux_tree_tapbuf_size10_0_sram[3]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.229071e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:16 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:13 mux_tree_tapbuf_size10_0_sram[3]:12 0.00341 +2 mux_tree_tapbuf_size10_0_sram[3]:13 mux_tree_tapbuf_size10_0_sram[3]:5 0.004209822 +3 mux_tree_tapbuf_size10_0_sram[3]:12 mux_tree_tapbuf_size10_0_sram[3]:11 0.001150717 +4 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.0001634615 +5 mux_tree_tapbuf_size10_0_sram[3]:11 mux_tree_tapbuf_size10_0_sram[3]:10 0.00341 +6 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.006089286 +7 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.0045 +8 mux_tree_tapbuf_size10_0_sram[3]:6 mem_bottom_ipin_0\/FTB_1__40:A 0.152 +9 mux_tree_tapbuf_size10_0_sram[3]:4 mux_tree_tapbuf_size10_0_sram[3]:3 0.003122768 +10 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.0045 +11 mux_tree_tapbuf_size10_0_sram[3]:3 mux_bottom_ipin_0\/mux_l4_in_0_:S 0.152 +12 mux_tree_tapbuf_size10_0_sram[3]:15 mux_tree_tapbuf_size10_0_sram[3]:14 0.0045 +13 mux_tree_tapbuf_size10_0_sram[3]:14 mux_tree_tapbuf_size10_0_sram[3]:13 0.0005669643 +14 mux_tree_tapbuf_size10_0_sram[3]:16 mux_tree_tapbuf_size10_0_sram[3]:15 0.001430804 +15 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[0] 0.005361112 //LENGTH 39.965 LUMPCC 0.0002794965 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 55.965 36.720 +*I mux_bottom_ipin_4\/mux_l1_in_0_:S I *L 0.00357 *C 62.920 25.160 +*I mux_bottom_ipin_4\/mux_l1_in_2_:S I *L 0.00357 *C 67.060 23.120 +*I mux_bottom_ipin_4\/mux_l1_in_1_:S I *L 0.00357 *C 67.260 20.400 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 68.245 11.900 +*N mux_tree_tapbuf_size10_2_sram[0]:5 *C 68.245 11.900 +*N mux_tree_tapbuf_size10_2_sram[0]:6 *C 68.080 11.900 +*N mux_tree_tapbuf_size10_2_sram[0]:7 *C 68.080 11.900 +*N mux_tree_tapbuf_size10_2_sram[0]:8 *C 67.620 11.900 +*N mux_tree_tapbuf_size10_2_sram[0]:9 *C 67.275 20.400 +*N mux_tree_tapbuf_size10_2_sram[0]:10 *C 67.597 20.400 +*N mux_tree_tapbuf_size10_2_sram[0]:11 *C 67.620 20.400 +*N mux_tree_tapbuf_size10_2_sram[0]:12 *C 67.620 23.075 +*N mux_tree_tapbuf_size10_2_sram[0]:13 *C 67.575 23.120 +*N mux_tree_tapbuf_size10_2_sram[0]:14 *C 67.060 23.120 +*N mux_tree_tapbuf_size10_2_sram[0]:15 *C 63.065 23.120 +*N mux_tree_tapbuf_size10_2_sram[0]:16 *C 63.020 23.165 +*N mux_tree_tapbuf_size10_2_sram[0]:17 *C 62.920 25.160 +*N mux_tree_tapbuf_size10_2_sram[0]:18 *C 63.020 25.160 +*N mux_tree_tapbuf_size10_2_sram[0]:19 *C 63.020 31.902 +*N mux_tree_tapbuf_size10_2_sram[0]:20 *C 63.013 31.960 +*N mux_tree_tapbuf_size10_2_sram[0]:21 *C 56.588 31.960 +*N mux_tree_tapbuf_size10_2_sram[0]:22 *C 56.580 32.017 +*N mux_tree_tapbuf_size10_2_sram[0]:23 *C 56.580 36.675 +*N mux_tree_tapbuf_size10_2_sram[0]:24 *C 56.535 36.720 +*N mux_tree_tapbuf_size10_2_sram[0]:25 *C 56.003 36.720 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_ipin_4\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_ipin_4\/mux_l1_in_1_:S 1e-06 +4 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_2_sram[0]:5 5.084633e-05 +6 mux_tree_tapbuf_size10_2_sram[0]:6 4.80746e-05 +7 mux_tree_tapbuf_size10_2_sram[0]:7 6.495761e-05 +8 mux_tree_tapbuf_size10_2_sram[0]:8 0.0005486254 +9 mux_tree_tapbuf_size10_2_sram[0]:9 5.881368e-05 +10 mux_tree_tapbuf_size10_2_sram[0]:10 5.881368e-05 +11 mux_tree_tapbuf_size10_2_sram[0]:11 0.00074018 +12 mux_tree_tapbuf_size10_2_sram[0]:12 0.0001917579 +13 mux_tree_tapbuf_size10_2_sram[0]:13 5.07522e-05 +14 mux_tree_tapbuf_size10_2_sram[0]:14 0.0004007522 +15 mux_tree_tapbuf_size10_2_sram[0]:15 0.0003208434 +16 mux_tree_tapbuf_size10_2_sram[0]:16 0.0001204982 +17 mux_tree_tapbuf_size10_2_sram[0]:17 2.932179e-05 +18 mux_tree_tapbuf_size10_2_sram[0]:18 0.0004929409 +19 mux_tree_tapbuf_size10_2_sram[0]:19 0.0003392698 +20 mux_tree_tapbuf_size10_2_sram[0]:20 0.0005254137 +21 mux_tree_tapbuf_size10_2_sram[0]:21 0.0005254137 +22 mux_tree_tapbuf_size10_2_sram[0]:22 0.0002046492 +23 mux_tree_tapbuf_size10_2_sram[0]:23 0.0002046492 +24 mux_tree_tapbuf_size10_2_sram[0]:24 5.00214e-05 +25 mux_tree_tapbuf_size10_2_sram[0]:25 5.00214e-05 +26 mux_tree_tapbuf_size10_2_sram[0]:22 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 6.195228e-05 +27 mux_tree_tapbuf_size10_2_sram[0]:23 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 6.195228e-05 +28 mux_tree_tapbuf_size10_2_sram[0]:19 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.779596e-05 +29 mux_tree_tapbuf_size10_2_sram[0]:18 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.779596e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_2_sram[0]:25 0.152 +1 mux_tree_tapbuf_size10_2_sram[0]:15 mux_tree_tapbuf_size10_2_sram[0]:14 0.003566964 +2 mux_tree_tapbuf_size10_2_sram[0]:16 mux_tree_tapbuf_size10_2_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size10_2_sram[0]:10 mux_tree_tapbuf_size10_2_sram[0]:9 0.0001752718 +4 mux_tree_tapbuf_size10_2_sram[0]:11 mux_tree_tapbuf_size10_2_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size10_2_sram[0]:11 mux_tree_tapbuf_size10_2_sram[0]:8 0.007589286 +6 mux_tree_tapbuf_size10_2_sram[0]:9 mux_bottom_ipin_4\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size10_2_sram[0]:13 mux_tree_tapbuf_size10_2_sram[0]:12 0.0045 +8 mux_tree_tapbuf_size10_2_sram[0]:12 mux_tree_tapbuf_size10_2_sram[0]:11 0.002388393 +9 mux_tree_tapbuf_size10_2_sram[0]:19 mux_tree_tapbuf_size10_2_sram[0]:18 0.006020089 +10 mux_tree_tapbuf_size10_2_sram[0]:20 mux_tree_tapbuf_size10_2_sram[0]:19 0.00341 +11 mux_tree_tapbuf_size10_2_sram[0]:22 mux_tree_tapbuf_size10_2_sram[0]:21 0.00341 +12 mux_tree_tapbuf_size10_2_sram[0]:21 mux_tree_tapbuf_size10_2_sram[0]:20 0.001006583 +13 mux_tree_tapbuf_size10_2_sram[0]:24 mux_tree_tapbuf_size10_2_sram[0]:23 0.0045 +14 mux_tree_tapbuf_size10_2_sram[0]:23 mux_tree_tapbuf_size10_2_sram[0]:22 0.004158482 +15 mux_tree_tapbuf_size10_2_sram[0]:25 mux_tree_tapbuf_size10_2_sram[0]:24 0.0004754465 +16 mux_tree_tapbuf_size10_2_sram[0]:6 mux_tree_tapbuf_size10_2_sram[0]:5 1e-05 +17 mux_tree_tapbuf_size10_2_sram[0]:7 mux_tree_tapbuf_size10_2_sram[0]:6 0.0045 +18 mux_tree_tapbuf_size10_2_sram[0]:5 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size10_2_sram[0]:14 mux_bottom_ipin_4\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size10_2_sram[0]:14 mux_tree_tapbuf_size10_2_sram[0]:13 0.0004598214 +21 mux_tree_tapbuf_size10_2_sram[0]:17 mux_bottom_ipin_4\/mux_l1_in_0_:S 0.152 +22 mux_tree_tapbuf_size10_2_sram[0]:18 mux_tree_tapbuf_size10_2_sram[0]:17 0.0045 +23 mux_tree_tapbuf_size10_2_sram[0]:18 mux_tree_tapbuf_size10_2_sram[0]:16 0.00178125 +24 mux_tree_tapbuf_size10_2_sram[0]:8 mux_tree_tapbuf_size10_2_sram[0]:7 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[2] 0.00443233 //LENGTH 30.550 LUMPCC 0.000932514 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 19.165 64.260 +*I mux_bottom_ipin_9\/mux_l3_in_1_:S I *L 0.00357 *C 8.620 63.240 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 7.995 69.700 +*I mux_bottom_ipin_9\/mux_l3_in_0_:S I *L 0.00357 *C 12.980 58.405 +*N mux_tree_tapbuf_size10_5_sram[2]:4 *C 13.018 58.465 +*N mux_tree_tapbuf_size10_5_sram[2]:5 *C 14.675 58.480 +*N mux_tree_tapbuf_size10_5_sram[2]:6 *C 14.720 58.480 +*N mux_tree_tapbuf_size10_5_sram[2]:7 *C 14.260 58.480 +*N mux_tree_tapbuf_size10_5_sram[2]:8 *C 7.995 69.700 +*N mux_tree_tapbuf_size10_5_sram[2]:9 *C 7.820 69.700 +*N mux_tree_tapbuf_size10_5_sram[2]:10 *C 7.820 69.655 +*N mux_tree_tapbuf_size10_5_sram[2]:11 *C 8.582 63.240 +*N mux_tree_tapbuf_size10_5_sram[2]:12 *C 7.865 63.240 +*N mux_tree_tapbuf_size10_5_sram[2]:13 *C 7.820 63.240 +*N mux_tree_tapbuf_size10_5_sram[2]:14 *C 7.820 61.925 +*N mux_tree_tapbuf_size10_5_sram[2]:15 *C 7.865 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:16 *C 10.535 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:17 *C 10.580 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:18 *C 10.588 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:19 *C 14.253 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:20 *C 14.260 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:21 *C 14.260 64.215 +*N mux_tree_tapbuf_size10_5_sram[2]:22 *C 14.305 64.260 +*N mux_tree_tapbuf_size10_5_sram[2]:23 *C 19.128 64.260 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_9\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_5_sram[2]:4 0.000116706 +5 mux_tree_tapbuf_size10_5_sram[2]:5 0.000116706 +6 mux_tree_tapbuf_size10_5_sram[2]:6 7.040042e-05 +7 mux_tree_tapbuf_size10_5_sram[2]:7 0.0002502368 +8 mux_tree_tapbuf_size10_5_sram[2]:8 5.666554e-05 +9 mux_tree_tapbuf_size10_5_sram[2]:9 6.127616e-05 +10 mux_tree_tapbuf_size10_5_sram[2]:10 0.0003417025 +11 mux_tree_tapbuf_size10_5_sram[2]:11 7.327906e-05 +12 mux_tree_tapbuf_size10_5_sram[2]:12 7.327906e-05 +13 mux_tree_tapbuf_size10_5_sram[2]:13 0.0004592031 +14 mux_tree_tapbuf_size10_5_sram[2]:14 8.943787e-05 +15 mux_tree_tapbuf_size10_5_sram[2]:15 0.0001531404 +16 mux_tree_tapbuf_size10_5_sram[2]:16 0.0001531404 +17 mux_tree_tapbuf_size10_5_sram[2]:17 3.884286e-05 +18 mux_tree_tapbuf_size10_5_sram[2]:18 0.0001240633 +19 mux_tree_tapbuf_size10_5_sram[2]:19 0.0001240634 +20 mux_tree_tapbuf_size10_5_sram[2]:20 0.000412532 +21 mux_tree_tapbuf_size10_5_sram[2]:21 0.0001595112 +22 mux_tree_tapbuf_size10_5_sram[2]:22 0.0003108151 +23 mux_tree_tapbuf_size10_5_sram[2]:23 0.0003108151 +24 mux_tree_tapbuf_size10_5_sram[2]:20 chanx_left_in[17]:29 6.505833e-06 +25 mux_tree_tapbuf_size10_5_sram[2]:19 chanx_left_in[17]:30 6.809459e-06 +26 mux_tree_tapbuf_size10_5_sram[2]:19 chanx_left_in[17]:32 0.0001916107 +27 mux_tree_tapbuf_size10_5_sram[2]:18 chanx_left_in[17] 0.0001916107 +28 mux_tree_tapbuf_size10_5_sram[2]:18 chanx_left_in[17]:31 6.809459e-06 +29 mux_tree_tapbuf_size10_5_sram[2]:21 chanx_left_in[17]:30 6.505833e-06 +30 mux_tree_tapbuf_size10_5_sram[2]:19 chanx_right_in[17]:10 0.0001164667 +31 mux_tree_tapbuf_size10_5_sram[2]:18 chanx_right_in[17]:9 0.0001164667 +32 mux_tree_tapbuf_size10_5_sram[2]:16 chanx_right_in[17]:6 9.610108e-05 +33 mux_tree_tapbuf_size10_5_sram[2]:15 chanx_right_in[17]:5 9.610108e-05 +34 mux_tree_tapbuf_size10_5_sram[2]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.876324e-05 +35 mux_tree_tapbuf_size10_5_sram[2]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.876324e-05 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_5_sram[2]:23 0.152 +1 mux_tree_tapbuf_size10_5_sram[2]:11 mux_bottom_ipin_9\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_5_sram[2]:12 mux_tree_tapbuf_size10_5_sram[2]:11 0.000640625 +3 mux_tree_tapbuf_size10_5_sram[2]:13 mux_tree_tapbuf_size10_5_sram[2]:12 0.0045 +4 mux_tree_tapbuf_size10_5_sram[2]:13 mux_tree_tapbuf_size10_5_sram[2]:10 0.005727679 +5 mux_tree_tapbuf_size10_5_sram[2]:20 mux_tree_tapbuf_size10_5_sram[2]:19 0.00341 +6 mux_tree_tapbuf_size10_5_sram[2]:20 mux_tree_tapbuf_size10_5_sram[2]:7 0.003035714 +7 mux_tree_tapbuf_size10_5_sram[2]:19 mux_tree_tapbuf_size10_5_sram[2]:18 0.0005741833 +8 mux_tree_tapbuf_size10_5_sram[2]:17 mux_tree_tapbuf_size10_5_sram[2]:16 0.0045 +9 mux_tree_tapbuf_size10_5_sram[2]:18 mux_tree_tapbuf_size10_5_sram[2]:17 0.00341 +10 mux_tree_tapbuf_size10_5_sram[2]:16 mux_tree_tapbuf_size10_5_sram[2]:15 0.002383929 +11 mux_tree_tapbuf_size10_5_sram[2]:15 mux_tree_tapbuf_size10_5_sram[2]:14 0.0045 +12 mux_tree_tapbuf_size10_5_sram[2]:14 mux_tree_tapbuf_size10_5_sram[2]:13 0.001174107 +13 mux_tree_tapbuf_size10_5_sram[2]:9 mux_tree_tapbuf_size10_5_sram[2]:8 9.51087e-05 +14 mux_tree_tapbuf_size10_5_sram[2]:10 mux_tree_tapbuf_size10_5_sram[2]:9 0.0045 +15 mux_tree_tapbuf_size10_5_sram[2]:8 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +16 mux_tree_tapbuf_size10_5_sram[2]:22 mux_tree_tapbuf_size10_5_sram[2]:21 0.0045 +17 mux_tree_tapbuf_size10_5_sram[2]:21 mux_tree_tapbuf_size10_5_sram[2]:20 0.002084821 +18 mux_tree_tapbuf_size10_5_sram[2]:23 mux_tree_tapbuf_size10_5_sram[2]:22 0.004305804 +19 mux_tree_tapbuf_size10_5_sram[2]:5 mux_tree_tapbuf_size10_5_sram[2]:4 0.001479911 +20 mux_tree_tapbuf_size10_5_sram[2]:6 mux_tree_tapbuf_size10_5_sram[2]:5 0.0045 +21 mux_tree_tapbuf_size10_5_sram[2]:4 mux_bottom_ipin_9\/mux_l3_in_0_:S 0.152 +22 mux_tree_tapbuf_size10_5_sram[2]:7 mux_tree_tapbuf_size10_5_sram[2]:6 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[3] 0.002472342 //LENGTH 19.070 LUMPCC 0 DR + +*CONN +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 85.405 6.460 +*I mem_top_ipin_0\/FTB_9__48:A I *L 0.001746 *C 76.360 6.800 +*I mux_top_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 88.680 8.840 +*N mux_tree_tapbuf_size10_8_sram[3]:3 *C 88.642 8.840 +*N mux_tree_tapbuf_size10_8_sram[3]:4 *C 76.360 6.800 +*N mux_tree_tapbuf_size10_8_sram[3]:5 *C 76.360 6.460 +*N mux_tree_tapbuf_size10_8_sram[3]:6 *C 77.695 6.460 +*N mux_tree_tapbuf_size10_8_sram[3]:7 *C 77.740 6.505 +*N mux_tree_tapbuf_size10_8_sram[3]:8 *C 77.740 8.795 +*N mux_tree_tapbuf_size10_8_sram[3]:9 *C 77.785 8.840 +*N mux_tree_tapbuf_size10_8_sram[3]:10 *C 85.560 8.840 +*N mux_tree_tapbuf_size10_8_sram[3]:11 *C 85.560 8.795 +*N mux_tree_tapbuf_size10_8_sram[3]:12 *C 85.560 6.505 +*N mux_tree_tapbuf_size10_8_sram[3]:13 *C 85.560 6.460 +*N mux_tree_tapbuf_size10_8_sram[3]:14 *C 85.405 6.460 + +*CAP +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_ipin_0\/FTB_9__48:A 1e-06 +2 mux_top_ipin_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_8_sram[3]:3 0.0002116206 +4 mux_tree_tapbuf_size10_8_sram[3]:4 6.065621e-05 +5 mux_tree_tapbuf_size10_8_sram[3]:5 0.0001531297 +6 mux_tree_tapbuf_size10_8_sram[3]:6 0.0001235596 +7 mux_tree_tapbuf_size10_8_sram[3]:7 0.0001541058 +8 mux_tree_tapbuf_size10_8_sram[3]:8 0.0001541058 +9 mux_tree_tapbuf_size10_8_sram[3]:9 0.0004994839 +10 mux_tree_tapbuf_size10_8_sram[3]:10 0.0007430397 +11 mux_tree_tapbuf_size10_8_sram[3]:11 0.0001322028 +12 mux_tree_tapbuf_size10_8_sram[3]:12 0.0001322028 +13 mux_tree_tapbuf_size10_8_sram[3]:13 5.384412e-05 +14 mux_tree_tapbuf_size10_8_sram[3]:14 5.139125e-05 + +*RES +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_8_sram[3]:14 0.152 +1 mux_tree_tapbuf_size10_8_sram[3]:9 mux_tree_tapbuf_size10_8_sram[3]:8 0.0045 +2 mux_tree_tapbuf_size10_8_sram[3]:8 mux_tree_tapbuf_size10_8_sram[3]:7 0.002044643 +3 mux_tree_tapbuf_size10_8_sram[3]:6 mux_tree_tapbuf_size10_8_sram[3]:5 0.001191964 +4 mux_tree_tapbuf_size10_8_sram[3]:7 mux_tree_tapbuf_size10_8_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size10_8_sram[3]:4 mem_top_ipin_0\/FTB_9__48:A 0.152 +6 mux_tree_tapbuf_size10_8_sram[3]:3 mux_top_ipin_0\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_8_sram[3]:10 mux_tree_tapbuf_size10_8_sram[3]:9 0.006941964 +8 mux_tree_tapbuf_size10_8_sram[3]:10 mux_tree_tapbuf_size10_8_sram[3]:3 0.002752232 +9 mux_tree_tapbuf_size10_8_sram[3]:11 mux_tree_tapbuf_size10_8_sram[3]:10 0.0045 +10 mux_tree_tapbuf_size10_8_sram[3]:13 mux_tree_tapbuf_size10_8_sram[3]:12 0.0045 +11 mux_tree_tapbuf_size10_8_sram[3]:12 mux_tree_tapbuf_size10_8_sram[3]:11 0.002044643 +12 mux_tree_tapbuf_size10_8_sram[3]:14 mux_tree_tapbuf_size10_8_sram[3]:13 8.423914e-05 +13 mux_tree_tapbuf_size10_8_sram[3]:5 mux_tree_tapbuf_size10_8_sram[3]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_6_ccff_tail[0] 0.0008241901 //LENGTH 5.320 LUMPCC 0.0002188317 DR + +*CONN +*I mem_bottom_ipin_12\/FTB_7__46:X O *L 0 *C 67.845 45.560 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.795 49.980 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 *C 67.795 49.980 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 *C 67.620 49.980 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 *C 67.620 49.935 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 *C 67.620 45.605 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 *C 67.620 45.560 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 *C 67.845 45.560 + +*CAP +0 mem_bottom_ipin_12\/FTB_7__46:X 1e-06 +1 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 4.722759e-05 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 5.151349e-05 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.0001968864 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0001968864 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 5.458478e-05 +7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 5.625976e-05 +8 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_1_sram[0]:16 4.93859e-06 +9 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_1_sram[0]:19 5.677483e-05 +10 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_1_sram[0]:20 4.770244e-05 +11 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_1_sram[0]:6 5.677483e-05 +12 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_1_sram[0]:15 4.93859e-06 +13 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_1_sram[0]:19 4.770244e-05 + +*RES +0 mem_bottom_ipin_12\/FTB_7__46:X mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.003866071 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[2] 0.003097845 //LENGTH 25.610 LUMPCC 0.0001808212 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 47.225 11.900 +*I mux_bottom_ipin_6\/mux_l3_in_1_:S I *L 0.00357 *C 43.340 19.720 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 42.035 28.220 +*I mux_bottom_ipin_6\/mux_l3_in_0_:S I *L 0.00357 *C 45.180 23.120 +*N mux_tree_tapbuf_size8_2_sram[2]:4 *C 45.143 23.120 +*N mux_tree_tapbuf_size8_2_sram[2]:5 *C 42.073 28.220 +*N mux_tree_tapbuf_size8_2_sram[2]:6 *C 42.735 28.220 +*N mux_tree_tapbuf_size8_2_sram[2]:7 *C 42.780 28.175 +*N mux_tree_tapbuf_size8_2_sram[2]:8 *C 42.780 23.165 +*N mux_tree_tapbuf_size8_2_sram[2]:9 *C 42.825 23.120 +*N mux_tree_tapbuf_size8_2_sram[2]:10 *C 44.160 23.120 +*N mux_tree_tapbuf_size8_2_sram[2]:11 *C 44.160 22.780 +*N mux_tree_tapbuf_size8_2_sram[2]:12 *C 44.160 22.735 +*N mux_tree_tapbuf_size8_2_sram[2]:13 *C 43.355 19.720 +*N mux_tree_tapbuf_size8_2_sram[2]:14 *C 43.678 19.720 +*N mux_tree_tapbuf_size8_2_sram[2]:15 *C 43.700 19.720 +*N mux_tree_tapbuf_size8_2_sram[2]:16 *C 44.160 19.720 +*N mux_tree_tapbuf_size8_2_sram[2]:17 *C 44.160 11.945 +*N mux_tree_tapbuf_size8_2_sram[2]:18 *C 44.205 11.900 +*N mux_tree_tapbuf_size8_2_sram[2]:19 *C 47.188 11.900 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_6\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_2_sram[2]:4 8.125967e-05 +5 mux_tree_tapbuf_size8_2_sram[2]:5 9.134234e-05 +6 mux_tree_tapbuf_size8_2_sram[2]:6 9.134234e-05 +7 mux_tree_tapbuf_size8_2_sram[2]:7 0.0002439741 +8 mux_tree_tapbuf_size8_2_sram[2]:8 0.0002439741 +9 mux_tree_tapbuf_size8_2_sram[2]:9 9.825272e-05 +10 mux_tree_tapbuf_size8_2_sram[2]:10 0.0002095316 +11 mux_tree_tapbuf_size8_2_sram[2]:11 6.550258e-05 +12 mux_tree_tapbuf_size8_2_sram[2]:12 0.0001841366 +13 mux_tree_tapbuf_size8_2_sram[2]:13 5.057399e-05 +14 mux_tree_tapbuf_size8_2_sram[2]:14 5.057399e-05 +15 mux_tree_tapbuf_size8_2_sram[2]:15 6.860495e-05 +16 mux_tree_tapbuf_size8_2_sram[2]:16 0.0006401333 +17 mux_tree_tapbuf_size8_2_sram[2]:17 0.0004208591 +18 mux_tree_tapbuf_size8_2_sram[2]:18 0.0001864814 +19 mux_tree_tapbuf_size8_2_sram[2]:19 0.0001864814 +20 mux_tree_tapbuf_size8_2_sram[2]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.872728e-05 +21 mux_tree_tapbuf_size8_2_sram[2]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.872728e-05 +22 mux_tree_tapbuf_size8_2_sram[2]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.683324e-06 +23 mux_tree_tapbuf_size8_2_sram[2]:16 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.683324e-06 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_2_sram[2]:19 0.152 +1 mux_tree_tapbuf_size8_2_sram[2]:14 mux_tree_tapbuf_size8_2_sram[2]:13 0.0001752717 +2 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:14 0.0045 +3 mux_tree_tapbuf_size8_2_sram[2]:13 mux_bottom_ipin_6\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size8_2_sram[2]:18 mux_tree_tapbuf_size8_2_sram[2]:17 0.0045 +5 mux_tree_tapbuf_size8_2_sram[2]:17 mux_tree_tapbuf_size8_2_sram[2]:16 0.006941965 +6 mux_tree_tapbuf_size8_2_sram[2]:19 mux_tree_tapbuf_size8_2_sram[2]:18 0.002662946 +7 mux_tree_tapbuf_size8_2_sram[2]:4 mux_bottom_ipin_6\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:8 0.0045 +9 mux_tree_tapbuf_size8_2_sram[2]:8 mux_tree_tapbuf_size8_2_sram[2]:7 0.004473214 +10 mux_tree_tapbuf_size8_2_sram[2]:6 mux_tree_tapbuf_size8_2_sram[2]:5 0.0005915179 +11 mux_tree_tapbuf_size8_2_sram[2]:7 mux_tree_tapbuf_size8_2_sram[2]:6 0.0045 +12 mux_tree_tapbuf_size8_2_sram[2]:5 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:10 0.0003035715 +14 mux_tree_tapbuf_size8_2_sram[2]:12 mux_tree_tapbuf_size8_2_sram[2]:11 0.0045 +15 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:9 0.001191964 +16 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:4 0.0008772322 +17 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:15 0.0004107143 +18 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:12 0.002691965 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[3] 0.002079532 //LENGTH 16.615 LUMPCC 0.0003016377 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 35.265 39.440 +*I mem_bottom_ipin_11\/FTB_15__54:A I *L 0.001746 *C 33.580 42.160 +*I mux_bottom_ipin_11\/mux_l4_in_0_:S I *L 0.00357 *C 27.700 46.920 +*N mux_tree_tapbuf_size8_5_sram[3]:3 *C 27.738 46.920 +*N mux_tree_tapbuf_size8_5_sram[3]:4 *C 30.775 46.920 +*N mux_tree_tapbuf_size8_5_sram[3]:5 *C 30.820 46.875 +*N mux_tree_tapbuf_size8_5_sram[3]:6 *C 30.820 42.205 +*N mux_tree_tapbuf_size8_5_sram[3]:7 *C 30.865 42.160 +*N mux_tree_tapbuf_size8_5_sram[3]:8 *C 33.543 42.160 +*N mux_tree_tapbuf_size8_5_sram[3]:9 *C 33.580 42.115 +*N mux_tree_tapbuf_size8_5_sram[3]:10 *C 33.580 39.485 +*N mux_tree_tapbuf_size8_5_sram[3]:11 *C 33.625 39.440 +*N mux_tree_tapbuf_size8_5_sram[3]:12 *C 35.227 39.440 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_11\/FTB_15__54:A 1e-06 +2 mux_bottom_ipin_11\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_5_sram[3]:3 0.0001792151 +4 mux_tree_tapbuf_size8_5_sram[3]:4 0.0001792151 +5 mux_tree_tapbuf_size8_5_sram[3]:5 0.0002809874 +6 mux_tree_tapbuf_size8_5_sram[3]:6 0.0002809874 +7 mux_tree_tapbuf_size8_5_sram[3]:7 0.0001388959 +8 mux_tree_tapbuf_size8_5_sram[3]:8 0.0001388959 +9 mux_tree_tapbuf_size8_5_sram[3]:9 0.0001504022 +10 mux_tree_tapbuf_size8_5_sram[3]:10 0.0001504022 +11 mux_tree_tapbuf_size8_5_sram[3]:11 0.0001379462 +12 mux_tree_tapbuf_size8_5_sram[3]:12 0.0001379462 +13 mux_tree_tapbuf_size8_5_sram[3]:7 mux_tree_tapbuf_size8_5_sram[2]:13 4.518814e-05 +14 mux_tree_tapbuf_size8_5_sram[3]:6 mux_tree_tapbuf_size8_5_sram[2]:8 5.429327e-06 +15 mux_tree_tapbuf_size8_5_sram[3]:6 mux_tree_tapbuf_size8_5_sram[2]:11 2.439859e-06 +16 mux_tree_tapbuf_size8_5_sram[3]:4 mux_tree_tapbuf_size8_5_sram[2]:6 3.44617e-05 +17 mux_tree_tapbuf_size8_5_sram[3]:5 mux_tree_tapbuf_size8_5_sram[2]:7 5.429327e-06 +18 mux_tree_tapbuf_size8_5_sram[3]:5 mux_tree_tapbuf_size8_5_sram[2]:10 2.439859e-06 +19 mux_tree_tapbuf_size8_5_sram[3]:3 mux_tree_tapbuf_size8_5_sram[2]:5 3.44617e-05 +20 mux_tree_tapbuf_size8_5_sram[3]:8 mux_tree_tapbuf_size8_5_sram[2]:12 4.518814e-05 +21 mux_tree_tapbuf_size8_5_sram[3]:9 mux_tree_tapbuf_size8_5_sram[2]:10 2.610827e-05 +22 mux_tree_tapbuf_size8_5_sram[3]:10 mux_tree_tapbuf_size8_5_sram[2]:11 2.610827e-05 +23 mux_tree_tapbuf_size8_5_sram[3]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.719154e-05 +24 mux_tree_tapbuf_size8_5_sram[3]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.719154e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_5_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_5_sram[3]:7 mux_tree_tapbuf_size8_5_sram[3]:6 0.0045 +2 mux_tree_tapbuf_size8_5_sram[3]:6 mux_tree_tapbuf_size8_5_sram[3]:5 0.004169643 +3 mux_tree_tapbuf_size8_5_sram[3]:4 mux_tree_tapbuf_size8_5_sram[3]:3 0.002712054 +4 mux_tree_tapbuf_size8_5_sram[3]:5 mux_tree_tapbuf_size8_5_sram[3]:4 0.0045 +5 mux_tree_tapbuf_size8_5_sram[3]:3 mux_bottom_ipin_11\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_5_sram[3]:8 mem_bottom_ipin_11\/FTB_15__54:A 0.152 +7 mux_tree_tapbuf_size8_5_sram[3]:8 mux_tree_tapbuf_size8_5_sram[3]:7 0.002390625 +8 mux_tree_tapbuf_size8_5_sram[3]:9 mux_tree_tapbuf_size8_5_sram[3]:8 0.0045 +9 mux_tree_tapbuf_size8_5_sram[3]:11 mux_tree_tapbuf_size8_5_sram[3]:10 0.0045 +10 mux_tree_tapbuf_size8_5_sram[3]:10 mux_tree_tapbuf_size8_5_sram[3]:9 0.002348214 +11 mux_tree_tapbuf_size8_5_sram[3]:12 mux_tree_tapbuf_size8_5_sram[3]:11 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_2_ccff_tail[0] 0.002026551 //LENGTH 14.990 LUMPCC 0.0008773848 DR + +*CONN +*I mem_bottom_ipin_6\/FTB_12__51:X O *L 0 *C 39.785 31.620 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 31.915 37.060 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 *C 31.915 37.060 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 *C 32.200 37.400 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 *C 32.200 37.355 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 *C 32.200 36.098 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 *C 32.208 36.040 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 *C 39.553 36.040 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 *C 39.560 35.983 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 *C 39.560 31.665 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:10 *C 39.560 31.620 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:11 *C 39.785 31.620 + +*CAP +0 mem_bottom_ipin_6\/FTB_12__51:X 1e-06 +1 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 5.425661e-05 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 5.824204e-05 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 7.827854e-05 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 7.827854e-05 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0001791334 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.0001791334 +8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 0.0001995566 +9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 0.0001995566 +10 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:10 6.155549e-05 +11 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:11 5.917473e-05 +12 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 chanx_left_in[4]:34 0.000184399 +13 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 chanx_left_in[4]:35 0.000184399 +14 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 chanx_left_in[8]:16 0.0001851169 +15 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 chanx_left_in[8]:17 0.0001851169 +16 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 prog_clk[0]:357 5.651472e-05 +17 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 prog_clk[0]:360 5.651472e-05 +18 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 prog_clk[0]:345 7.754394e-06 +19 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 prog_clk[0]:348 3.217591e-06 +20 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 prog_clk[0]:347 1.68982e-06 +21 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 prog_clk[0]:348 7.754394e-06 +22 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 prog_clk[0]:349 3.217591e-06 +23 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 prog_clk[0]:346 1.68982e-06 + +*RES +0 mem_bottom_ipin_6\/FTB_12__51:X mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:10 0.0001222826 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 0.003854911 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.00341 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.001150717 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.001122768 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.00341 +8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0001847826 +9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005821417 //LENGTH 3.280 LUMPCC 7.558006e-05 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_3_:X O *L 0 *C 83.435 29.240 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 83.435 31.620 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 83.435 31.620 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 83.260 31.620 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 83.260 31.575 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 83.260 29.285 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 83.260 29.240 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 83.435 29.240 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.520895e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.913956e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001392683 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001392683 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.584151e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.583515e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[16]:22 3.779003e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[16]:21 3.779003e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_3_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002044643 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008651135 //LENGTH 6.250 LUMPCC 0.0002339117 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_2_:X O *L 0 *C 67.905 22.440 +*I mux_bottom_ipin_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 66.605 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 66.605 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 66.700 18.065 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 66.700 22.395 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 66.745 22.440 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 67.868 22.440 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.701417e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001933859 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001933859 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001027079 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001027079 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[8]:6 0.0001169559 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[8]:13 0.0001169559 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_2_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.003866072 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001002232 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007358979 //LENGTH 5.360 LUMPCC 0.0001755946 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_0_:X O *L 0 *C 56.755 55.420 +*I mux_bottom_ipin_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 54.645 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 54.645 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 54.740 52.745 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 54.740 55.375 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 54.785 55.420 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 56.718 55.420 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.692575e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001710331 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001710331 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.465567e-05 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.465567e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[1]:37 8.779731e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[1]:38 8.779731e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001725447 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001387144 //LENGTH 10.615 LUMPCC 0.0003265867 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l3_in_0_:X O *L 0 *C 7.535 34.000 +*I mux_bottom_ipin_8\/mux_l4_in_0_:A1 I *L 0.00198 *C 13.340 36.380 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 13.340 36.418 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 13.340 37.060 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 10.625 37.060 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 10.580 37.015 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 10.580 34.045 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 10.535 34.000 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 7.573 34.000 + +*CAP +0 mux_bottom_ipin_8\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.007052e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001582387 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001181682 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001543664 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001543664 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002166737 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002166737 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size10_4_sram[2]:7 6.185329e-06 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_4_sram[2]:8 6.185329e-06 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:13 5.689355e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:14 3.801496e-06 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:15 7.240944e-07 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:16 2.14619e-07 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:17 6.438569e-07 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:19 2.137531e-08 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:10 6.378044e-06 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:6 6.438569e-07 +19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:9 3.801496e-06 +20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:12 5.689355e-05 +21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:14 7.240944e-07 +22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:17 2.14619e-07 +23 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:18 2.137531e-08 +24 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_4_sram[2]:17 5.622353e-06 +25 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_4_sram[2]:6 5.622353e-06 +26 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_4_sram[2]:11 6.378044e-06 +27 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 8.280861e-05 +28 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 8.280861e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l3_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.002645089 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002651786 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002424107 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_8\/mux_l4_in_0_:A1 0.152 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0005736608 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007744306 //LENGTH 4.980 LUMPCC 0.0001555919 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_1_:X O *L 0 *C 63.765 29.240 +*I mux_bottom_ipin_12\/mux_l3_in_0_:A0 I *L 0.001631 *C 63.195 33.320 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 63.195 33.320 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 63.480 33.320 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 63.480 33.275 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 63.480 29.285 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 63.480 29.240 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 63.765 29.240 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.878479e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.459603e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001916201 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001916201 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.368322e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.653438e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:19 7.779596e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_2_sram[0]:18 7.779596e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001548913 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001155088 //LENGTH 8.545 LUMPCC 0.0001896202 DR + +*CONN +*I mux_top_ipin_0\/mux_l1_in_2_:X O *L 0 *C 95.395 22.440 +*I mux_top_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 90.160 20.060 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 90.198 20.060 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.875 20.060 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.920 20.105 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.920 22.395 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.965 22.440 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 95.358 22.440 + +*CAP +0 mux_top_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_top_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.000201538 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000201538 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001516751 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001516751 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001285208 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001285208 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[4]:22 9.481009e-05 +9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[4]:21 9.481009e-05 + +*RES +0 mux_top_ipin_0\/mux_l1_in_2_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002136161 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002390625 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_ipin_0\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00784377 //LENGTH 57.030 LUMPCC 0.001124532 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l4_in_0_:X O *L 0 *C 31.455 23.460 +*I mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 31.630 71.915 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 31.630 71.915 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 31.740 71.740 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 31.740 71.695 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 31.740 70.097 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 31.733 70.040 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 28.540 70.040 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 28.520 70.032 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 28.520 31.288 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 28.540 31.280 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 31.733 31.280 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 31.740 31.223 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 31.740 23.505 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 31.740 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 *C 31.455 23.460 + +*CAP +0 mux_bottom_ipin_2\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.172176e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.561861e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001079158 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001079158 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002714922 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002714922 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.002328386 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.002328386 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 6.751582e-05 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 6.751582e-05 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.00047104 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.00047104 +14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 5.968663e-05 +15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 5.751221e-05 +16 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chanx_left_in[16]:29 0.0001972299 +17 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chanx_left_in[16]:30 0.0001972299 +18 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chanx_right_in[18]:13 0.0001972299 +19 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chanx_right_in[18]:12 0.0001972299 +20 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001678064 +21 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0001678064 + +*RES +0 mux_bottom_ipin_2\/mux_l4_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.0001548913 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0045 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.006890626 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0005001583 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.006070049 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0005001583 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001426339 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.978261e-05 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001198826 //LENGTH 11.150 LUMPCC 0.0001462284 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l4_in_0_:X O *L 0 *C 23.175 64.600 +*I mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 20.020 71.890 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 20.058 71.793 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 22.035 71.740 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 22.080 71.695 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 22.080 64.645 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 22.125 64.600 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 23.138 64.600 + +*CAP +0 mux_bottom_ipin_7\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001241286 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001241286 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000304408 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000304408 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.676228e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.676228e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_3_sram[2]:7 7.311419e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[2]:8 7.311419e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l4_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001765625 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.006294644 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004599737 //LENGTH 3.175 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l1_in_0_:X O *L 0 *C 72.965 25.160 +*I mux_bottom_ipin_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 73.700 23.460 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 73.663 23.460 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.185 23.460 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.140 23.505 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.140 25.115 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 73.140 25.160 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 72.965 25.160 + +*CAP +0 mux_bottom_ipin_14\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.805259e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.805259e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001167489 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001167489 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.564754e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.272309e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l1_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_14\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.510869e-05 + +*END + +*D_NET ropt_net_138 0.0003754754 //LENGTH 3.510 LUMPCC 0 DR + +*CONN +*I FTB_2__1:X O *L 0 *C 94.760 55.760 +*I ropt_mt_inst_737:A I *L 0.001766 *C 97.980 55.760 +*N ropt_net_138:2 *C 97.943 55.760 +*N ropt_net_138:3 *C 94.797 55.760 + +*CAP +0 FTB_2__1:X 1e-06 +1 ropt_mt_inst_737:A 1e-06 +2 ropt_net_138:2 0.0001867377 +3 ropt_net_138:3 0.0001867377 + +*RES +0 FTB_2__1:X ropt_net_138:3 0.152 +1 ropt_net_138:2 ropt_mt_inst_737:A 0.152 +2 ropt_net_138:3 ropt_net_138:2 0.002808036 + +*END + +*D_NET chanx_left_out[5] 0.001099842 //LENGTH 9.060 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_710:X O *L 0 *C 7.095 11.900 +*P chanx_left_out[5] O *L 0.7423 *C 1.230 9.520 +*N chanx_left_out[5]:2 *C 5.053 9.520 +*N chanx_left_out[5]:3 *C 5.060 9.578 +*N chanx_left_out[5]:4 *C 5.060 11.855 +*N chanx_left_out[5]:5 *C 5.105 11.900 +*N chanx_left_out[5]:6 *C 7.058 11.900 + +*CAP +0 ropt_mt_inst_710:X 1e-06 +1 chanx_left_out[5] 0.0002774733 +2 chanx_left_out[5]:2 0.0002774733 +3 chanx_left_out[5]:3 0.0001347204 +4 chanx_left_out[5]:4 0.0001347204 +5 chanx_left_out[5]:5 0.0001372275 +6 chanx_left_out[5]:6 0.0001372275 + +*RES +0 ropt_mt_inst_710:X chanx_left_out[5]:6 0.152 +1 chanx_left_out[5]:6 chanx_left_out[5]:5 0.001743304 +2 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +3 chanx_left_out[5]:4 chanx_left_out[5]:3 0.002033482 +4 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +5 chanx_left_out[5]:2 chanx_left_out[5] 0.0005988583 + +*END + +*D_NET ropt_net_147 0.001036369 //LENGTH 7.755 LUMPCC 0.0001009544 DR + +*CONN +*I FTB_24__23:X O *L 0 *C 11.040 7.140 +*I ropt_mt_inst_747:A I *L 0.001766 *C 7.820 9.520 +*N ropt_net_147:2 *C 7.820 9.520 +*N ropt_net_147:3 *C 7.820 9.475 +*N ropt_net_147:4 *C 7.820 8.885 +*N ropt_net_147:5 *C 7.820 8.840 +*N ropt_net_147:6 *C 10.535 8.840 +*N ropt_net_147:7 *C 10.580 8.795 +*N ropt_net_147:8 *C 10.580 7.185 +*N ropt_net_147:9 *C 10.625 7.140 +*N ropt_net_147:10 *C 11.003 7.140 + +*CAP +0 FTB_24__23:X 1e-06 +1 ropt_mt_inst_747:A 1e-06 +2 ropt_net_147:2 3.694859e-05 +3 ropt_net_147:3 5.131022e-05 +4 ropt_net_147:4 5.131022e-05 +5 ropt_net_147:5 0.0002943027 +6 ropt_net_147:6 0.0002565387 +7 ropt_net_147:7 8.552584e-05 +8 ropt_net_147:8 8.552584e-05 +9 ropt_net_147:9 3.597624e-05 +10 ropt_net_147:10 3.597624e-05 +11 ropt_net_147:10 chanx_right_in[1]:14 2.850446e-05 +12 ropt_net_147:9 chanx_right_in[1]:13 2.850446e-05 +13 ropt_net_147:8 chanx_right_in[1]:15 2.183094e-05 +14 ropt_net_147:7 chanx_right_in[1]:16 2.183094e-05 +15 ropt_net_147:4 chanx_right_in[1]:15 1.418007e-07 +16 ropt_net_147:3 chanx_right_in[1]:16 1.418007e-07 + +*RES +0 FTB_24__23:X ropt_net_147:10 0.152 +1 ropt_net_147:10 ropt_net_147:9 0.0003370536 +2 ropt_net_147:9 ropt_net_147:8 0.0045 +3 ropt_net_147:8 ropt_net_147:7 0.0014375 +4 ropt_net_147:6 ropt_net_147:5 0.002424107 +5 ropt_net_147:7 ropt_net_147:6 0.0045 +6 ropt_net_147:5 ropt_net_147:4 0.0045 +7 ropt_net_147:4 ropt_net_147:3 0.0005267857 +8 ropt_net_147:2 ropt_mt_inst_747:A 0.152 +9 ropt_net_147:3 ropt_net_147:2 0.0045 + +*END + +*D_NET chanx_right_out[10] 0.001061767 //LENGTH 8.335 LUMPCC 0.0001480722 DR + +*CONN +*I ropt_mt_inst_753:X O *L 0 *C 98.900 70.040 +*P chanx_right_out[10] O *L 0.7423 *C 101.660 74.870 +*N chanx_right_out[10]:2 *C 101.660 72.420 +*N chanx_right_out[10]:3 *C 101.200 72.420 +*N chanx_right_out[10]:4 *C 101.200 70.085 +*N chanx_right_out[10]:5 *C 101.155 70.040 +*N chanx_right_out[10]:6 *C 98.938 70.040 + +*CAP +0 ropt_mt_inst_753:X 1e-06 +1 chanx_right_out[10] 0.000148144 +2 chanx_right_out[10]:2 0.0001523249 +3 chanx_right_out[10]:3 0.000144003 +4 chanx_right_out[10]:4 0.000139822 +5 chanx_right_out[10]:5 0.0001642006 +6 chanx_right_out[10]:6 0.0001642006 +7 chanx_right_out[10]:4 ropt_net_159:7 4.950757e-05 +8 chanx_right_out[10]:3 ropt_net_159:6 4.950757e-05 +9 chanx_right_out[10]:3 ropt_net_159:4 2.452854e-05 +10 chanx_right_out[10]:2 ropt_net_159:5 2.452854e-05 + +*RES +0 ropt_mt_inst_753:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:6 chanx_right_out[10]:5 0.001979911 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.002084821 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.0004107143 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.0021875 + +*END + +*D_NET chanx_left_out[17] 0.0008874706 //LENGTH 6.335 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 7.095 63.920 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 63.920 +*N chanx_left_out[17]:2 *C 5.053 63.920 +*N chanx_left_out[17]:3 *C 5.060 63.920 +*N chanx_left_out[17]:4 *C 5.105 63.920 +*N chanx_left_out[17]:5 *C 7.058 63.920 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 chanx_left_out[17] 0.000293614 +2 chanx_left_out[17]:2 0.000293614 +3 chanx_left_out[17]:3 3.141656e-05 +4 chanx_left_out[17]:4 0.000133913 +5 chanx_left_out[17]:5 0.000133913 + +*RES +0 ropt_mt_inst_736:X chanx_left_out[17]:5 0.152 +1 chanx_left_out[17]:5 chanx_left_out[17]:4 0.001743304 +2 chanx_left_out[17]:4 chanx_left_out[17]:3 0.0045 +3 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +4 chanx_left_out[17]:2 chanx_left_out[17] 0.0005988583 + +*END + +*D_NET ropt_net_144 0.000613 //LENGTH 4.420 LUMPCC 0.0001236165 DR + +*CONN +*I BUFT_P_91:X O *L 0 *C 94.300 41.820 +*I ropt_mt_inst_744:A I *L 0.001766 *C 97.980 42.160 +*N ropt_net_144:2 *C 97.980 42.160 +*N ropt_net_144:3 *C 97.980 41.820 +*N ropt_net_144:4 *C 94.338 41.820 + +*CAP +0 BUFT_P_91:X 1e-06 +1 ropt_mt_inst_744:A 1e-06 +2 ropt_net_144:2 6.393673e-05 +3 ropt_net_144:3 0.0002272239 +4 ropt_net_144:4 0.0001962228 +5 ropt_net_144:4 chanx_left_in[15]:9 6.180826e-05 +6 ropt_net_144:3 chanx_left_in[15]:10 6.180826e-05 + +*RES +0 BUFT_P_91:X ropt_net_144:4 0.152 +1 ropt_net_144:4 ropt_net_144:3 0.003252232 +2 ropt_net_144:2 ropt_mt_inst_744:A 0.152 +3 ropt_net_144:3 ropt_net_144:2 0.0003035715 + +*END + +*D_NET chanx_right_out[19] 0.0003770192 //LENGTH 2.445 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 101.855 4.080 +*P chanx_right_out[19] O *L 0.7423 *C 103.650 4.080 +*N chanx_right_out[19]:2 *C 101.668 4.080 +*N chanx_right_out[19]:3 *C 101.660 4.080 +*N chanx_right_out[19]:4 *C 101.660 4.080 +*N chanx_right_out[19]:5 *C 101.855 4.080 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 chanx_right_out[19] 0.0001279048 +2 chanx_right_out[19]:2 0.0001279048 +3 chanx_right_out[19]:3 3.119672e-05 +4 chanx_right_out[19]:4 4.532189e-05 +5 chanx_right_out[19]:5 4.369106e-05 + +*RES +0 ropt_mt_inst_745:X chanx_right_out[19]:5 0.152 +1 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0001059783 +2 chanx_right_out[19]:4 chanx_right_out[19]:3 0.0045 +3 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +4 chanx_right_out[19]:2 chanx_right_out[19] 0.0003105917 + +*END + +*D_NET chanx_left_in[2] 0.02516492 //LENGTH 182.755 LUMPCC 0.004579184 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 6.800 +*I mux_bottom_ipin_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 16.925 20.060 +*I mux_bottom_ipin_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 18.575 22.780 +*I mux_bottom_ipin_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 40.310 20.740 +*I mux_bottom_ipin_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 52.730 20.740 +*I mux_bottom_ipin_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.540 20.060 +*I mux_bottom_ipin_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.315 22.780 +*I mux_top_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 95.585 20.060 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 95.125 30.940 +*I BUFT_P_96:A I *L 0.001776 *C 99.360 58.480 +*I mux_bottom_ipin_12\/mux_l1_in_1_:A1 I *L 0.00198 *C 59.800 23.460 +*N chanx_left_in[2]:11 *C 59.838 23.460 +*N chanx_left_in[2]:12 *C 65.780 23.460 +*N chanx_left_in[2]:13 *C 65.780 23.800 +*N chanx_left_in[2]:14 *C 71.255 23.800 +*N chanx_left_in[2]:15 *C 71.300 23.755 +*N chanx_left_in[2]:16 *C 99.323 58.480 +*N chanx_left_in[2]:17 *C 97.105 58.480 +*N chanx_left_in[2]:18 *C 97.060 58.435 +*N chanx_left_in[2]:19 *C 97.060 54.400 +*N chanx_left_in[2]:20 *C 94.760 54.400 +*N chanx_left_in[2]:21 *C 94.760 30.940 +*N chanx_left_in[2]:22 *C 95.163 30.940 +*N chanx_left_in[2]:23 *C 95.635 30.940 +*N chanx_left_in[2]:24 *C 95.680 30.895 +*N chanx_left_in[2]:25 *C 95.585 20.060 +*N chanx_left_in[2]:26 *C 95.680 20.105 +*N chanx_left_in[2]:27 *C 95.680 22.440 +*N chanx_left_in[2]:28 *C 95.672 22.440 +*N chanx_left_in[2]:29 *C 90.160 22.440 +*N chanx_left_in[2]:30 *C 90.160 23.120 +*N chanx_left_in[2]:31 *C 73.608 23.120 +*N chanx_left_in[2]:32 *C 73.600 23.120 +*N chanx_left_in[2]:33 *C 73.600 22.780 +*N chanx_left_in[2]:34 *C 73.600 22.780 +*N chanx_left_in[2]:35 *C 73.278 22.780 +*N chanx_left_in[2]:36 *C 71.345 22.780 +*N chanx_left_in[2]:37 *C 71.300 22.780 +*N chanx_left_in[2]:38 *C 71.300 20.105 +*N chanx_left_in[2]:39 *C 71.255 20.060 +*N chanx_left_in[2]:40 *C 68.540 20.060 +*N chanx_left_in[2]:41 *C 66.240 20.060 +*N chanx_left_in[2]:42 *C 66.240 20.400 +*N chanx_left_in[2]:43 *C 64.400 20.400 +*N chanx_left_in[2]:44 *C 64.400 20.740 +*N chanx_left_in[2]:45 *C 52.730 20.740 +*N chanx_left_in[2]:46 *C 40.310 20.740 +*N chanx_left_in[2]:47 *C 38.225 20.740 +*N chanx_left_in[2]:48 *C 38.180 20.695 +*N chanx_left_in[2]:49 *C 38.180 18.405 +*N chanx_left_in[2]:50 *C 38.135 18.360 +*N chanx_left_in[2]:51 *C 18.538 22.780 +*N chanx_left_in[2]:52 *C 17.525 22.780 +*N chanx_left_in[2]:53 *C 17.480 22.735 +*N chanx_left_in[2]:54 *C 16.963 20.060 +*N chanx_left_in[2]:55 *C 17.435 20.060 +*N chanx_left_in[2]:56 *C 17.480 20.060 +*N chanx_left_in[2]:57 *C 17.480 18.405 +*N chanx_left_in[2]:58 *C 17.480 18.360 +*N chanx_left_in[2]:59 *C 16.145 18.360 +*N chanx_left_in[2]:60 *C 16.100 18.315 +*N chanx_left_in[2]:61 *C 16.100 6.857 +*N chanx_left_in[2]:62 *C 16.093 6.800 + +*CAP +0 chanx_left_in[2] 0.0008309371 +1 mux_bottom_ipin_8\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_ipin_2\/mux_l2_in_0_:A0 1e-06 +4 mux_bottom_ipin_6\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_ipin_4\/mux_l1_in_1_:A1 1e-06 +6 mux_bottom_ipin_14\/mux_l2_in_0_:A0 1e-06 +7 mux_top_ipin_0\/mux_l1_in_1_:A1 1e-06 +8 mux_bottom_ipin_0\/mux_l1_in_1_:A1 1e-06 +9 BUFT_P_96:A 1e-06 +10 mux_bottom_ipin_12\/mux_l1_in_1_:A1 1e-06 +11 chanx_left_in[2]:11 0.0004268663 +12 chanx_left_in[2]:12 0.0004517242 +13 chanx_left_in[2]:13 0.0004369784 +14 chanx_left_in[2]:14 0.0004121205 +15 chanx_left_in[2]:15 6.733368e-05 +16 chanx_left_in[2]:16 0.0001830408 +17 chanx_left_in[2]:17 0.0001830408 +18 chanx_left_in[2]:18 0.0002192105 +19 chanx_left_in[2]:19 0.0003353376 +20 chanx_left_in[2]:20 0.001353593 +21 chanx_left_in[2]:21 0.001298978 +22 chanx_left_in[2]:22 5.120472e-05 +23 chanx_left_in[2]:23 5.120472e-05 +24 chanx_left_in[2]:24 0.0003791539 +25 chanx_left_in[2]:25 2.91373e-05 +26 chanx_left_in[2]:26 0.0001162266 +27 chanx_left_in[2]:27 0.0004683108 +28 chanx_left_in[2]:28 0.0004691562 +29 chanx_left_in[2]:29 0.0005166038 +30 chanx_left_in[2]:30 0.000444018 +31 chanx_left_in[2]:31 0.0003965705 +32 chanx_left_in[2]:32 6.283417e-05 +33 chanx_left_in[2]:33 5.843021e-05 +34 chanx_left_in[2]:34 5.170597e-05 +35 chanx_left_in[2]:35 0.0001229636 +36 chanx_left_in[2]:36 0.0001041464 +37 chanx_left_in[2]:37 0.0002497328 +38 chanx_left_in[2]:38 0.0001502598 +39 chanx_left_in[2]:39 0.000177645 +40 chanx_left_in[2]:40 0.0003609113 +41 chanx_left_in[2]:41 0.000183802 +42 chanx_left_in[2]:42 0.0001501304 +43 chanx_left_in[2]:43 0.0001474245 +44 chanx_left_in[2]:44 0.0007746757 +45 chanx_left_in[2]:45 0.001459981 +46 chanx_left_in[2]:46 0.0008538904 +47 chanx_left_in[2]:47 0.0001460707 +48 chanx_left_in[2]:48 0.0001566689 +49 chanx_left_in[2]:49 0.0001566689 +50 chanx_left_in[2]:50 0.001399413 +51 chanx_left_in[2]:51 8.484141e-05 +52 chanx_left_in[2]:52 8.484141e-05 +53 chanx_left_in[2]:53 0.0001660312 +54 chanx_left_in[2]:54 6.351242e-05 +55 chanx_left_in[2]:55 6.351242e-05 +56 chanx_left_in[2]:56 0.0003086827 +57 chanx_left_in[2]:57 0.0001076251 +58 chanx_left_in[2]:58 0.001535259 +59 chanx_left_in[2]:59 0.000101511 +60 chanx_left_in[2]:60 0.0006704379 +61 chanx_left_in[2]:61 0.0006704379 +62 chanx_left_in[2]:62 0.0008309371 +63 chanx_left_in[2]:31 chanx_left_in[10]:31 0.0004986681 +64 chanx_left_in[2]:31 chanx_left_in[10]:27 1.906128e-05 +65 chanx_left_in[2]:11 chanx_left_in[10]:31 5.777929e-06 +66 chanx_left_in[2]:18 chanx_left_in[10]:15 6.121275e-06 +67 chanx_left_in[2]:12 chanx_left_in[10]:30 5.777929e-06 +68 chanx_left_in[2]:20 chanx_left_in[10]:18 5.295342e-06 +69 chanx_left_in[2]:19 chanx_left_in[10]:16 6.121275e-06 +70 chanx_left_in[2]:19 chanx_left_in[10]:17 5.295342e-06 +71 chanx_left_in[2]:30 chanx_left_in[10]:23 1.382358e-05 +72 chanx_left_in[2]:30 chanx_left_in[10]:25 1.906128e-05 +73 chanx_left_in[2]:30 chanx_left_in[10]:30 0.0004986681 +74 chanx_left_in[2]:29 chanx_left_in[10]:24 1.382358e-05 +75 chanx_left_in[2]:52 chanx_right_in[2]:28 7.98774e-06 +76 chanx_left_in[2]:51 chanx_right_in[2]:29 7.98774e-06 +77 chanx_left_in[2]:36 chanx_right_in[2]:43 8.664191e-05 +78 chanx_left_in[2]:37 chanx_right_in[2]:42 3.464477e-06 +79 chanx_left_in[2]:39 chanx_right_in[2]:14 4.936968e-06 +80 chanx_left_in[2]:38 chanx_right_in[2]:41 3.464477e-06 +81 chanx_left_in[2]:34 chanx_right_in[2]:44 1.083831e-05 +82 chanx_left_in[2]:31 chanx_right_in[2]:48 8.308772e-05 +83 chanx_left_in[2]:27 chanx_right_in[2]:51 6.003866e-08 +84 chanx_left_in[2]:27 chanx_right_in[2]:57 0.0002175753 +85 chanx_left_in[2]:27 chanx_right_in[2]:56 4.621232e-05 +86 chanx_left_in[2]:27 chanx_right_in[2]:60 2.801009e-07 +87 chanx_left_in[2]:28 chanx_right_in[2]:49 5.769315e-05 +88 chanx_left_in[2]:55 chanx_right_in[2]:18 2.025814e-06 +89 chanx_left_in[2]:54 chanx_right_in[2]:25 2.025814e-06 +90 chanx_left_in[2]:40 chanx_right_in[2]:14 2.508298e-06 +91 chanx_left_in[2]:40 chanx_right_in[2]:13 4.936968e-06 +92 chanx_left_in[2]:11 chanx_right_in[2]:36 6.05402e-06 +93 chanx_left_in[2]:11 chanx_right_in[2]:34 5.375488e-06 +94 chanx_left_in[2]:35 chanx_right_in[2]:43 1.083831e-05 +95 chanx_left_in[2]:35 chanx_right_in[2]:44 8.664191e-05 +96 chanx_left_in[2]:23 chanx_right_in[2]:55 5.516857e-06 +97 chanx_left_in[2]:24 chanx_right_in[2]:56 0.0002175753 +98 chanx_left_in[2]:22 chanx_right_in[2]:54 5.516857e-06 +99 chanx_left_in[2]:26 chanx_right_in[2]:50 6.003866e-08 +100 chanx_left_in[2]:26 chanx_right_in[2]:57 4.621232e-05 +101 chanx_left_in[2]:26 chanx_right_in[2]:61 2.801009e-07 +102 chanx_left_in[2]:12 chanx_right_in[2]:35 5.375488e-06 +103 chanx_left_in[2]:12 chanx_right_in[2]:37 6.05402e-06 +104 chanx_left_in[2]:41 chanx_right_in[2]:13 2.508298e-06 +105 chanx_left_in[2]:21 chanx_right_in[2]:57 1.787493e-06 +106 chanx_left_in[2]:20 chanx_right_in[2]:56 1.787493e-06 +107 chanx_left_in[2]:30 chanx_right_in[2]:49 8.308772e-05 +108 chanx_left_in[2]:29 chanx_right_in[2]:48 5.769315e-05 +109 chanx_left_in[2]:31 chanx_right_in[4]:17 0.00093309 +110 chanx_left_in[2]:28 chanx_right_in[4]:18 1.715413e-05 +111 chanx_left_in[2]:14 chanx_right_in[4]:18 1.069422e-05 +112 chanx_left_in[2]:13 chanx_right_in[4]:17 1.069422e-05 +113 chanx_left_in[2]:30 chanx_right_in[4]:18 0.00093309 +114 chanx_left_in[2]:29 chanx_right_in[4]:17 1.715413e-05 +115 chanx_left_in[2]:45 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.126972e-05 +116 chanx_left_in[2]:40 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.005503e-06 +117 chanx_left_in[2]:44 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.126972e-05 +118 chanx_left_in[2]:43 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.058152e-05 +119 chanx_left_in[2]:42 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.058152e-05 +120 chanx_left_in[2]:41 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.005503e-06 +121 chanx_left_in[2]:45 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001287993 +122 chanx_left_in[2]:46 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001287993 +123 chanx_left_in[2]:45 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.620495e-05 +124 chanx_left_in[2]:46 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.620495e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:62 0.002328458 +1 chanx_left_in[2]:58 chanx_left_in[2]:57 0.0045 +2 chanx_left_in[2]:58 chanx_left_in[2]:50 0.01844197 +3 chanx_left_in[2]:57 chanx_left_in[2]:56 0.001477679 +4 chanx_left_in[2]:52 chanx_left_in[2]:51 0.0009040179 +5 chanx_left_in[2]:53 chanx_left_in[2]:52 0.0045 +6 chanx_left_in[2]:51 mux_bottom_ipin_10\/mux_l2_in_0_:A0 0.152 +7 chanx_left_in[2]:59 chanx_left_in[2]:58 0.001191964 +8 chanx_left_in[2]:60 chanx_left_in[2]:59 0.0045 +9 chanx_left_in[2]:61 chanx_left_in[2]:60 0.01022991 +10 chanx_left_in[2]:62 chanx_left_in[2]:61 0.00341 +11 chanx_left_in[2]:36 chanx_left_in[2]:35 0.001725447 +12 chanx_left_in[2]:37 chanx_left_in[2]:36 0.0045 +13 chanx_left_in[2]:37 chanx_left_in[2]:15 0.0008705358 +14 chanx_left_in[2]:39 chanx_left_in[2]:38 0.0045 +15 chanx_left_in[2]:38 chanx_left_in[2]:37 0.002388393 +16 chanx_left_in[2]:50 chanx_left_in[2]:49 0.0045 +17 chanx_left_in[2]:49 chanx_left_in[2]:48 0.002044643 +18 chanx_left_in[2]:47 chanx_left_in[2]:46 0.001861607 +19 chanx_left_in[2]:48 chanx_left_in[2]:47 0.0045 +20 chanx_left_in[2]:34 chanx_left_in[2]:33 0.0045 +21 chanx_left_in[2]:33 chanx_left_in[2]:32 0.0001634615 +22 chanx_left_in[2]:32 chanx_left_in[2]:31 0.00341 +23 chanx_left_in[2]:31 chanx_left_in[2]:30 0.002593225 +24 chanx_left_in[2]:27 chanx_left_in[2]:26 0.002084821 +25 chanx_left_in[2]:27 chanx_left_in[2]:24 0.007549108 +26 chanx_left_in[2]:28 chanx_left_in[2]:27 0.00341 +27 chanx_left_in[2]:55 chanx_left_in[2]:54 0.0004218751 +28 chanx_left_in[2]:56 chanx_left_in[2]:55 0.0045 +29 chanx_left_in[2]:56 chanx_left_in[2]:53 0.002388393 +30 chanx_left_in[2]:54 mux_bottom_ipin_8\/mux_l1_in_1_:A1 0.152 +31 chanx_left_in[2]:45 mux_bottom_ipin_6\/mux_l2_in_0_:A0 0.152 +32 chanx_left_in[2]:45 chanx_left_in[2]:44 0.01041964 +33 chanx_left_in[2]:40 mux_bottom_ipin_4\/mux_l1_in_1_:A1 0.152 +34 chanx_left_in[2]:40 chanx_left_in[2]:39 0.002424107 +35 chanx_left_in[2]:14 chanx_left_in[2]:13 0.004888393 +36 chanx_left_in[2]:15 chanx_left_in[2]:14 0.0045 +37 chanx_left_in[2]:11 mux_bottom_ipin_12\/mux_l1_in_1_:A1 0.152 +38 chanx_left_in[2]:35 mux_bottom_ipin_14\/mux_l2_in_0_:A0 0.152 +39 chanx_left_in[2]:35 chanx_left_in[2]:34 0.0001752718 +40 chanx_left_in[2]:46 mux_bottom_ipin_2\/mux_l2_in_0_:A0 0.152 +41 chanx_left_in[2]:46 chanx_left_in[2]:45 0.01108929 +42 chanx_left_in[2]:23 chanx_left_in[2]:22 0.000421875 +43 chanx_left_in[2]:24 chanx_left_in[2]:23 0.0045 +44 chanx_left_in[2]:24 chanx_left_in[2]:21 0.0008214287 +45 chanx_left_in[2]:22 mux_bottom_ipin_0\/mux_l1_in_1_:A1 0.152 +46 chanx_left_in[2]:25 mux_top_ipin_0\/mux_l1_in_1_:A1 0.152 +47 chanx_left_in[2]:26 chanx_left_in[2]:25 0.0045 +48 chanx_left_in[2]:17 chanx_left_in[2]:16 0.001979911 +49 chanx_left_in[2]:18 chanx_left_in[2]:17 0.0045 +50 chanx_left_in[2]:16 BUFT_P_96:A 0.152 +51 chanx_left_in[2]:44 chanx_left_in[2]:43 0.0003035715 +52 chanx_left_in[2]:12 chanx_left_in[2]:11 0.005305804 +53 chanx_left_in[2]:43 chanx_left_in[2]:42 0.001642857 +54 chanx_left_in[2]:42 chanx_left_in[2]:41 0.0003035715 +55 chanx_left_in[2]:13 chanx_left_in[2]:12 0.0003035715 +56 chanx_left_in[2]:41 chanx_left_in[2]:40 0.002053572 +57 chanx_left_in[2]:21 chanx_left_in[2]:20 0.02094643 +58 chanx_left_in[2]:20 chanx_left_in[2]:19 0.002053572 +59 chanx_left_in[2]:19 chanx_left_in[2]:18 0.003602679 +60 chanx_left_in[2]:30 chanx_left_in[2]:29 0.0001065333 +61 chanx_left_in[2]:29 chanx_left_in[2]:28 0.000863625 + +*END + +*D_NET chanx_right_in[2] 0.01974158 //LENGTH 140.165 LUMPCC 0.003191738 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 103.650 15.640 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 95.510 31.620 +*I mux_top_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 95.970 20.740 +*I mux_bottom_ipin_12\/mux_l1_in_1_:A0 I *L 0.001631 *C 59.630 22.780 +*I FTB_23__22:A I *L 0.001767 *C 6.900 14.960 +*I mux_bottom_ipin_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 17.310 21.080 +*I mux_bottom_ipin_10\/mux_l2_in_1_:A1 I *L 0.00198 *C 24.745 23.460 +*I mux_bottom_ipin_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 38.545 23.460 +*I mux_bottom_ipin_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 50.045 23.460 +*I mux_bottom_ipin_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.370 21.080 +*I mux_bottom_ipin_14\/mux_l2_in_1_:A1 I *L 0.00198 *C 81.325 23.460 +*N chanx_right_in[2]:11 *C 81.325 23.460 +*N chanx_right_in[2]:12 *C 81.420 23.415 +*N chanx_right_in[2]:13 *C 68.407 21.080 +*N chanx_right_in[2]:14 *C 68.955 21.080 +*N chanx_right_in[2]:15 *C 50.045 23.460 +*N chanx_right_in[2]:16 *C 38.545 23.460 +*N chanx_right_in[2]:17 *C 24.745 23.460 +*N chanx_right_in[2]:18 *C 17.273 21.080 +*N chanx_right_in[2]:19 *C 6.900 14.960 +*N chanx_right_in[2]:20 *C 6.900 15.300 +*N chanx_right_in[2]:21 *C 8.695 15.300 +*N chanx_right_in[2]:22 *C 8.740 15.345 +*N chanx_right_in[2]:23 *C 8.740 21.035 +*N chanx_right_in[2]:24 *C 8.785 21.080 +*N chanx_right_in[2]:25 *C 14.720 21.080 +*N chanx_right_in[2]:26 *C 14.720 21.125 +*N chanx_right_in[2]:27 *C 14.720 23.755 +*N chanx_right_in[2]:28 *C 14.765 23.800 +*N chanx_right_in[2]:29 *C 24.840 23.800 +*N chanx_right_in[2]:30 *C 38.640 23.800 +*N chanx_right_in[2]:31 *C 50.140 23.800 +*N chanx_right_in[2]:32 *C 59.340 23.800 +*N chanx_right_in[2]:33 *C 59.340 22.815 +*N chanx_right_in[2]:34 *C 59.603 22.803 +*N chanx_right_in[2]:35 *C 59.680 22.803 +*N chanx_right_in[2]:36 *C 59.800 22.780 +*N chanx_right_in[2]:37 *C 60.260 22.780 +*N chanx_right_in[2]:38 *C 60.260 21.137 +*N chanx_right_in[2]:39 *C 60.268 21.080 +*N chanx_right_in[2]:40 *C 68.993 21.080 +*N chanx_right_in[2]:41 *C 69.000 21.080 +*N chanx_right_in[2]:42 *C 69.000 22.395 +*N chanx_right_in[2]:43 *C 69.045 22.440 +*N chanx_right_in[2]:44 *C 81.375 22.440 +*N chanx_right_in[2]:45 *C 81.420 22.440 +*N chanx_right_in[2]:46 *C 81.880 22.440 +*N chanx_right_in[2]:47 *C 81.880 21.137 +*N chanx_right_in[2]:48 *C 81.888 21.080 +*N chanx_right_in[2]:49 *C 92.453 21.080 +*N chanx_right_in[2]:50 *C 92.460 21.080 +*N chanx_right_in[2]:51 *C 92.460 20.740 +*N chanx_right_in[2]:52 *C 92.505 20.740 +*N chanx_right_in[2]:53 *C 96.093 20.740 +*N chanx_right_in[2]:54 *C 95.547 31.620 +*N chanx_right_in[2]:55 *C 96.095 31.620 +*N chanx_right_in[2]:56 *C 96.140 31.575 +*N chanx_right_in[2]:57 *C 96.140 20.785 +*N chanx_right_in[2]:58 *C 96.185 20.740 +*N chanx_right_in[2]:59 *C 97.475 20.740 +*N chanx_right_in[2]:60 *C 97.520 20.695 +*N chanx_right_in[2]:61 *C 97.520 15.698 +*N chanx_right_in[2]:62 *C 97.528 15.640 + +*CAP +0 chanx_right_in[2] 0.0003623692 +1 mux_bottom_ipin_0\/mux_l1_in_1_:A0 1e-06 +2 mux_top_ipin_0\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_ipin_12\/mux_l1_in_1_:A0 1e-06 +4 FTB_23__22:A 1e-06 +5 mux_bottom_ipin_8\/mux_l1_in_1_:A0 1e-06 +6 mux_bottom_ipin_10\/mux_l2_in_1_:A1 1e-06 +7 mux_bottom_ipin_2\/mux_l2_in_1_:A1 1e-06 +8 mux_bottom_ipin_6\/mux_l2_in_1_:A1 1e-06 +9 mux_bottom_ipin_4\/mux_l1_in_1_:A0 1e-06 +10 mux_bottom_ipin_14\/mux_l2_in_1_:A1 1e-06 +11 chanx_right_in[2]:11 2.993383e-05 +12 chanx_right_in[2]:12 6.665504e-05 +13 chanx_right_in[2]:13 5.278369e-05 +14 chanx_right_in[2]:14 5.278369e-05 +15 chanx_right_in[2]:15 5.444171e-05 +16 chanx_right_in[2]:16 5.723339e-05 +17 chanx_right_in[2]:17 5.670675e-05 +18 chanx_right_in[2]:18 0.0001747711 +19 chanx_right_in[2]:19 6.200196e-05 +20 chanx_right_in[2]:20 0.0001216508 +21 chanx_right_in[2]:21 9.444365e-05 +22 chanx_right_in[2]:22 0.0003589714 +23 chanx_right_in[2]:23 0.0003589714 +24 chanx_right_in[2]:24 0.0003506538 +25 chanx_right_in[2]:25 0.0005598072 +26 chanx_right_in[2]:26 0.0001964045 +27 chanx_right_in[2]:27 0.0001964045 +28 chanx_right_in[2]:28 0.0007003914 +29 chanx_right_in[2]:29 0.001648267 +30 chanx_right_in[2]:30 0.001763538 +31 chanx_right_in[2]:31 0.001528854 +32 chanx_right_in[2]:32 0.0007496589 +33 chanx_right_in[2]:33 8.42633e-05 +34 chanx_right_in[2]:34 3.892225e-05 +35 chanx_right_in[2]:35 1.778546e-05 +36 chanx_right_in[2]:36 6.115431e-05 +37 chanx_right_in[2]:37 0.0001361685 +38 chanx_right_in[2]:38 0.0001077332 +39 chanx_right_in[2]:39 0.0004938402 +40 chanx_right_in[2]:40 0.0004938402 +41 chanx_right_in[2]:41 0.0001249261 +42 chanx_right_in[2]:42 8.758977e-05 +43 chanx_right_in[2]:43 0.0007552197 +44 chanx_right_in[2]:44 0.0007552197 +45 chanx_right_in[2]:45 0.0001005413 +46 chanx_right_in[2]:46 0.0001190003 +47 chanx_right_in[2]:47 8.511406e-05 +48 chanx_right_in[2]:48 0.0003498993 +49 chanx_right_in[2]:49 0.0003498993 +50 chanx_right_in[2]:50 6.007234e-05 +51 chanx_right_in[2]:51 5.591358e-05 +52 chanx_right_in[2]:52 0.0002180953 +53 chanx_right_in[2]:53 0.0002400714 +54 chanx_right_in[2]:54 5.189812e-05 +55 chanx_right_in[2]:55 5.189812e-05 +56 chanx_right_in[2]:56 0.0004513497 +57 chanx_right_in[2]:57 0.0004513497 +58 chanx_right_in[2]:58 0.0001113755 +59 chanx_right_in[2]:59 8.939936e-05 +60 chanx_right_in[2]:60 0.0003186208 +61 chanx_right_in[2]:61 0.0003186208 +62 chanx_right_in[2]:62 0.0003623692 +63 chanx_right_in[2]:51 chanx_left_in[2]:27 6.003866e-08 +64 chanx_right_in[2]:50 chanx_left_in[2]:26 6.003866e-08 +65 chanx_right_in[2]:49 chanx_left_in[2]:28 5.769315e-05 +66 chanx_right_in[2]:49 chanx_left_in[2]:30 8.308772e-05 +67 chanx_right_in[2]:48 chanx_left_in[2]:29 5.769315e-05 +68 chanx_right_in[2]:48 chanx_left_in[2]:31 8.308772e-05 +69 chanx_right_in[2]:35 chanx_left_in[2]:12 5.375488e-06 +70 chanx_right_in[2]:36 chanx_left_in[2]:11 6.05402e-06 +71 chanx_right_in[2]:41 chanx_left_in[2]:38 3.464477e-06 +72 chanx_right_in[2]:25 chanx_left_in[2]:54 2.025814e-06 +73 chanx_right_in[2]:28 chanx_left_in[2]:52 7.98774e-06 +74 chanx_right_in[2]:43 chanx_left_in[2]:35 1.083831e-05 +75 chanx_right_in[2]:43 chanx_left_in[2]:36 8.664191e-05 +76 chanx_right_in[2]:42 chanx_left_in[2]:37 3.464477e-06 +77 chanx_right_in[2]:44 chanx_left_in[2]:34 1.083831e-05 +78 chanx_right_in[2]:44 chanx_left_in[2]:35 8.664191e-05 +79 chanx_right_in[2]:14 chanx_left_in[2]:39 4.936968e-06 +80 chanx_right_in[2]:14 chanx_left_in[2]:40 2.508298e-06 +81 chanx_right_in[2]:13 chanx_left_in[2]:40 4.936968e-06 +82 chanx_right_in[2]:13 chanx_left_in[2]:41 2.508298e-06 +83 chanx_right_in[2]:34 chanx_left_in[2]:11 5.375488e-06 +84 chanx_right_in[2]:57 chanx_left_in[2]:21 1.787493e-06 +85 chanx_right_in[2]:57 chanx_left_in[2]:26 4.621232e-05 +86 chanx_right_in[2]:57 chanx_left_in[2]:27 0.0002175753 +87 chanx_right_in[2]:55 chanx_left_in[2]:23 5.516857e-06 +88 chanx_right_in[2]:56 chanx_left_in[2]:20 1.787493e-06 +89 chanx_right_in[2]:56 chanx_left_in[2]:24 0.0002175753 +90 chanx_right_in[2]:56 chanx_left_in[2]:27 4.621232e-05 +91 chanx_right_in[2]:54 chanx_left_in[2]:22 5.516857e-06 +92 chanx_right_in[2]:18 chanx_left_in[2]:55 2.025814e-06 +93 chanx_right_in[2]:60 chanx_left_in[2]:27 2.801009e-07 +94 chanx_right_in[2]:61 chanx_left_in[2]:26 2.801009e-07 +95 chanx_right_in[2]:29 chanx_left_in[2]:51 7.98774e-06 +96 chanx_right_in[2]:37 chanx_left_in[2]:12 6.05402e-06 +97 chanx_right_in[2] chanx_right_in[10] 1.150423e-06 +98 chanx_right_in[2]:49 chanx_right_in[10] 0.0005054926 +99 chanx_right_in[2]:49 chanx_right_in[10]:31 3.392128e-05 +100 chanx_right_in[2]:49 chanx_right_in[10]:28 1.45258e-06 +101 chanx_right_in[2]:47 chanx_right_in[10]:26 8.2605e-06 +102 chanx_right_in[2]:48 chanx_right_in[10]:27 1.45258e-06 +103 chanx_right_in[2]:48 chanx_right_in[10]:19 3.392128e-05 +104 chanx_right_in[2]:48 chanx_right_in[10]:32 0.0005054926 +105 chanx_right_in[2]:39 chanx_right_in[10]:14 0.0001832085 +106 chanx_right_in[2]:40 chanx_right_in[10]:19 0.0001832085 +107 chanx_right_in[2]:45 chanx_right_in[10]:26 2.232025e-06 +108 chanx_right_in[2]:23 chanx_right_in[10]:7 3.829356e-06 +109 chanx_right_in[2]:22 chanx_right_in[10]:8 3.829356e-06 +110 chanx_right_in[2]:12 chanx_right_in[10]:22 2.232025e-06 +111 chanx_right_in[2]:62 chanx_right_in[10]:32 1.150423e-06 +112 chanx_right_in[2]:46 chanx_right_in[10]:22 8.2605e-06 +113 chanx_right_in[2]:25 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.817127e-05 +114 chanx_right_in[2]:25 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.914449e-05 +115 chanx_right_in[2]:24 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.914449e-05 +116 chanx_right_in[2]:18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.817127e-05 +117 chanx_right_in[2]:29 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.582021e-05 +118 chanx_right_in[2]:30 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.582021e-05 +119 chanx_right_in[2]:43 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.292632e-05 +120 chanx_right_in[2]:44 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.292632e-05 +121 chanx_right_in[2]:21 ropt_net_148:2 2.525892e-05 +122 chanx_right_in[2]:21 ropt_net_148:4 7.879295e-06 +123 chanx_right_in[2]:19 ropt_net_148:4 5.075263e-06 +124 chanx_right_in[2]:20 ropt_net_148:5 7.879295e-06 +125 chanx_right_in[2]:20 ropt_net_148:3 3.033419e-05 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:62 0.0009591916 +1 chanx_right_in[2]:52 chanx_right_in[2]:51 0.0045 +2 chanx_right_in[2]:51 chanx_right_in[2]:50 0.0001634615 +3 chanx_right_in[2]:50 chanx_right_in[2]:49 0.00341 +4 chanx_right_in[2]:49 chanx_right_in[2]:48 0.001655183 +5 chanx_right_in[2]:47 chanx_right_in[2]:46 0.001162946 +6 chanx_right_in[2]:48 chanx_right_in[2]:47 0.00341 +7 chanx_right_in[2]:35 chanx_right_in[2]:34 5.236487e-05 +8 chanx_right_in[2]:36 chanx_right_in[2]:35 0.0045 +9 chanx_right_in[2]:38 chanx_right_in[2]:37 0.001466518 +10 chanx_right_in[2]:39 chanx_right_in[2]:38 0.00341 +11 chanx_right_in[2]:41 chanx_right_in[2]:40 0.00341 +12 chanx_right_in[2]:41 chanx_right_in[2]:14 0.0045 +13 chanx_right_in[2]:40 chanx_right_in[2]:39 0.001366917 +14 chanx_right_in[2]:25 chanx_right_in[2]:24 0.005299107 +15 chanx_right_in[2]:25 chanx_right_in[2]:18 0.002279018 +16 chanx_right_in[2]:26 chanx_right_in[2]:25 0.0045 +17 chanx_right_in[2]:28 chanx_right_in[2]:27 0.0045 +18 chanx_right_in[2]:27 chanx_right_in[2]:26 0.002348214 +19 chanx_right_in[2]:43 chanx_right_in[2]:42 0.0045 +20 chanx_right_in[2]:42 chanx_right_in[2]:41 0.001174107 +21 chanx_right_in[2]:44 chanx_right_in[2]:43 0.01100893 +22 chanx_right_in[2]:45 chanx_right_in[2]:44 0.0045 +23 chanx_right_in[2]:45 chanx_right_in[2]:12 0.0008705358 +24 chanx_right_in[2]:24 chanx_right_in[2]:23 0.0045 +25 chanx_right_in[2]:23 chanx_right_in[2]:22 0.005080357 +26 chanx_right_in[2]:21 chanx_right_in[2]:20 0.001602679 +27 chanx_right_in[2]:22 chanx_right_in[2]:21 0.0045 +28 chanx_right_in[2]:19 FTB_23__22:A 0.152 +29 chanx_right_in[2]:17 mux_bottom_ipin_10\/mux_l2_in_1_:A1 0.152 +30 chanx_right_in[2]:15 mux_bottom_ipin_6\/mux_l2_in_1_:A1 0.152 +31 chanx_right_in[2]:14 chanx_right_in[2]:13 0.0004888393 +32 chanx_right_in[2]:13 mux_bottom_ipin_4\/mux_l1_in_1_:A0 0.152 +33 chanx_right_in[2]:34 mux_bottom_ipin_12\/mux_l1_in_1_:A0 0.152 +34 chanx_right_in[2]:34 chanx_right_in[2]:33 0.0001773649 +35 chanx_right_in[2]:11 mux_bottom_ipin_14\/mux_l2_in_1_:A1 0.152 +36 chanx_right_in[2]:12 chanx_right_in[2]:11 0.0045 +37 chanx_right_in[2]:16 mux_bottom_ipin_2\/mux_l2_in_1_:A1 0.152 +38 chanx_right_in[2]:58 chanx_right_in[2]:57 0.0045 +39 chanx_right_in[2]:58 chanx_right_in[2]:53 8.258929e-05 +40 chanx_right_in[2]:57 chanx_right_in[2]:56 0.009633929 +41 chanx_right_in[2]:55 chanx_right_in[2]:54 0.0004888393 +42 chanx_right_in[2]:56 chanx_right_in[2]:55 0.0045 +43 chanx_right_in[2]:54 mux_bottom_ipin_0\/mux_l1_in_1_:A0 0.152 +44 chanx_right_in[2]:18 mux_bottom_ipin_8\/mux_l1_in_1_:A0 0.152 +45 chanx_right_in[2]:53 mux_top_ipin_0\/mux_l1_in_1_:A0 0.152 +46 chanx_right_in[2]:53 chanx_right_in[2]:52 0.003203125 +47 chanx_right_in[2]:59 chanx_right_in[2]:58 0.001151786 +48 chanx_right_in[2]:60 chanx_right_in[2]:59 0.0045 +49 chanx_right_in[2]:61 chanx_right_in[2]:60 0.004462054 +50 chanx_right_in[2]:62 chanx_right_in[2]:61 0.00341 +51 chanx_right_in[2]:20 chanx_right_in[2]:19 0.0003035715 +52 chanx_right_in[2]:29 chanx_right_in[2]:28 0.008995537 +53 chanx_right_in[2]:29 chanx_right_in[2]:17 0.0003035715 +54 chanx_right_in[2]:30 chanx_right_in[2]:29 0.01232143 +55 chanx_right_in[2]:30 chanx_right_in[2]:16 0.0003035715 +56 chanx_right_in[2]:31 chanx_right_in[2]:30 0.01026786 +57 chanx_right_in[2]:31 chanx_right_in[2]:15 0.0003035715 +58 chanx_right_in[2]:32 chanx_right_in[2]:31 0.008214287 +59 chanx_right_in[2]:33 chanx_right_in[2]:32 0.0008794643 +60 chanx_right_in[2]:37 chanx_right_in[2]:36 0.0004107143 +61 chanx_right_in[2]:46 chanx_right_in[2]:45 0.0004107143 + +*END + +*D_NET chanx_right_in[12] 0.02082923 //LENGTH 123.780 LUMPCC 0.01093184 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 103.650 23.120 +*I FTB_33__32:A I *L 0.001776 *C 14.720 20.400 +*I mux_bottom_ipin_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 8.740 25.500 +*I mux_bottom_ipin_12\/mux_l2_in_2_:A1 I *L 0.00198 *C 71.205 30.940 +*N chanx_right_in[12]:4 *C 71.243 30.940 +*N chanx_right_in[12]:5 *C 72.175 30.940 +*N chanx_right_in[12]:6 *C 72.220 30.895 +*N chanx_right_in[12]:7 *C 8.740 25.500 +*N chanx_right_in[12]:8 *C 8.740 25.160 +*N chanx_right_in[12]:9 *C 11.455 25.160 +*N chanx_right_in[12]:10 *C 11.500 25.115 +*N chanx_right_in[12]:11 *C 14.758 20.400 +*N chanx_right_in[12]:12 *C 15.180 20.400 +*N chanx_right_in[12]:13 *C 15.180 20.060 +*N chanx_right_in[12]:14 *C 13.385 20.060 +*N chanx_right_in[12]:15 *C 13.340 20.060 +*N chanx_right_in[12]:16 *C 13.340 20.400 +*N chanx_right_in[12]:17 *C 13.333 20.400 +*N chanx_right_in[12]:18 *C 11.508 20.400 +*N chanx_right_in[12]:19 *C 11.500 20.457 +*N chanx_right_in[12]:20 *C 11.500 22.440 +*N chanx_right_in[12]:21 *C 11.508 22.440 +*N chanx_right_in[12]:22 *C 46.453 22.440 +*N chanx_right_in[12]:23 *C 46.460 22.498 +*N chanx_right_in[12]:24 *C 46.460 25.783 +*N chanx_right_in[12]:25 *C 46.468 25.840 +*N chanx_right_in[12]:26 *C 71.752 25.840 +*N chanx_right_in[12]:27 *C 71.760 25.898 +*N chanx_right_in[12]:28 *C 71.760 27.880 +*N chanx_right_in[12]:29 *C 72.220 27.938 +*N chanx_right_in[12]:30 *C 72.228 27.880 +*N chanx_right_in[12]:31 *C 91.980 27.880 +*N chanx_right_in[12]:32 *C 92.000 27.873 +*N chanx_right_in[12]:33 *C 92.000 23.128 +*N chanx_right_in[12]:34 *C 92.020 23.120 + +*CAP +0 chanx_right_in[12] 0.0007543106 +1 FTB_33__32:A 1e-06 +2 mux_bottom_ipin_8\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_2_:A1 1e-06 +4 chanx_right_in[12]:4 8.404416e-05 +5 chanx_right_in[12]:5 8.404416e-05 +6 chanx_right_in[12]:6 0.0002010636 +7 chanx_right_in[12]:7 5.374977e-05 +8 chanx_right_in[12]:8 0.000268321 +9 chanx_right_in[12]:9 0.0002417532 +10 chanx_right_in[12]:10 9.585104e-05 +11 chanx_right_in[12]:11 3.562752e-05 +12 chanx_right_in[12]:12 6.205105e-05 +13 chanx_right_in[12]:13 0.0001351539 +14 chanx_right_in[12]:14 0.0001087304 +15 chanx_right_in[12]:15 5.896758e-05 +16 chanx_right_in[12]:16 6.341413e-05 +17 chanx_right_in[12]:17 0.0001748068 +18 chanx_right_in[12]:18 0.0001748068 +19 chanx_right_in[12]:19 0.000114182 +20 chanx_right_in[12]:20 0.0002466652 +21 chanx_right_in[12]:21 0.0009291227 +22 chanx_right_in[12]:22 0.0009291227 +23 chanx_right_in[12]:23 0.0002040117 +24 chanx_right_in[12]:24 0.0002040117 +25 chanx_right_in[12]:25 0.0007633511 +26 chanx_right_in[12]:26 0.0007633511 +27 chanx_right_in[12]:27 0.0001451709 +28 chanx_right_in[12]:28 0.000182741 +29 chanx_right_in[12]:29 0.0002386338 +30 chanx_right_in[12]:30 0.0006317118 +31 chanx_right_in[12]:31 0.0006317118 +32 chanx_right_in[12]:32 0.0002797975 +33 chanx_right_in[12]:33 0.0002797975 +34 chanx_right_in[12]:34 0.0007543106 +35 chanx_right_in[12]:25 chanx_left_in[0]:36 3.428483e-05 +36 chanx_right_in[12]:25 chanx_left_in[0]:40 0.0005127228 +37 chanx_right_in[12]:25 chanx_left_in[0]:41 0.0004061351 +38 chanx_right_in[12]:27 chanx_left_in[0]:35 1.611402e-07 +39 chanx_right_in[12]:26 chanx_left_in[0]:32 3.428483e-05 +40 chanx_right_in[12]:26 chanx_left_in[0]:36 0.0005127228 +41 chanx_right_in[12]:26 chanx_left_in[0]:40 0.0004061351 +42 chanx_right_in[12]:28 chanx_left_in[0]:34 1.611402e-07 +43 chanx_right_in[12] chanx_left_in[4]:12 6.828415e-06 +44 chanx_right_in[12]:30 chanx_left_in[4]:30 0.0002432753 +45 chanx_right_in[12]:31 chanx_left_in[4]:25 0.0002432753 +46 chanx_right_in[12]:32 chanx_left_in[4]:20 6.71021e-05 +47 chanx_right_in[12]:34 chanx_left_in[4]:18 6.828415e-06 +48 chanx_right_in[12]:33 chanx_left_in[4]:19 6.71021e-05 +49 chanx_right_in[12]:27 chanx_left_in[4]:28 2.149434e-07 +50 chanx_right_in[12]:28 chanx_left_in[4]:29 2.149434e-07 +51 chanx_right_in[12]:10 chanx_left_in[8]:20 4.347761e-05 +52 chanx_right_in[12]:30 chanx_left_in[8]:12 0.0003460722 +53 chanx_right_in[12]:31 chanx_left_in[8]:11 0.0003460722 +54 chanx_right_in[12]:20 chanx_left_in[8]:21 4.347761e-05 +55 chanx_right_in[12]:10 chanx_left_in[10]:37 6.610652e-06 +56 chanx_right_in[12]:20 chanx_left_in[10]:38 6.610652e-06 +57 chanx_right_in[12]:25 chanx_left_in[10]:37 0.0002483894 +58 chanx_right_in[12]:26 chanx_left_in[10]:36 0.0002483894 +59 chanx_right_in[12]:18 chanx_left_in[14] 8.696255e-06 +60 chanx_right_in[12]:17 chanx_left_in[14]:29 8.696255e-06 +61 chanx_right_in[12]:21 chanx_left_in[14] 0.0008039372 +62 chanx_right_in[12]:22 chanx_left_in[14]:29 0.0008039372 +63 chanx_right_in[12] chanx_right_in[4]:18 4.341892e-05 +64 chanx_right_in[12]:10 chanx_right_in[4]:10 8.416748e-06 +65 chanx_right_in[12]:19 chanx_right_in[4]:9 4.404858e-06 +66 chanx_right_in[12]:34 chanx_right_in[4]:17 4.341892e-05 +67 chanx_right_in[12]:20 chanx_right_in[4]:9 8.416748e-06 +68 chanx_right_in[12]:20 chanx_right_in[4]:10 4.404858e-06 +69 chanx_right_in[12]:21 chanx_right_in[4]:11 0.0004782715 +70 chanx_right_in[12]:22 chanx_right_in[4]:12 0.0004782715 +71 chanx_right_in[12]:25 chanx_right_in[4]:11 5.872844e-05 +72 chanx_right_in[12]:26 chanx_right_in[4]:12 5.872844e-05 +73 chanx_right_in[12] chanx_right_in[6]:28 8.082712e-05 +74 chanx_right_in[12]:18 chanx_right_in[6]:12 2.785684e-05 +75 chanx_right_in[12]:17 chanx_right_in[6]:21 2.785684e-05 +76 chanx_right_in[12]:30 chanx_right_in[6]:27 0.0004208529 +77 chanx_right_in[12]:31 chanx_right_in[6]:28 0.0004208529 +78 chanx_right_in[12]:34 chanx_right_in[6]:27 8.082712e-05 +79 chanx_right_in[12]:21 chanx_right_in[6]:12 0.0003415096 +80 chanx_right_in[12]:21 chanx_right_in[6]:21 0.0004420135 +81 chanx_right_in[12]:22 chanx_right_in[6]:21 0.0003415096 +82 chanx_right_in[12]:22 chanx_right_in[6]:22 0.0004420135 +83 chanx_right_in[12]:25 chanx_right_in[6]:27 0.0007529794 +84 chanx_right_in[12]:26 chanx_right_in[6]:28 0.0007529794 +85 chanx_right_in[12]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.553655e-05 +86 chanx_right_in[12]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.795641e-05 +87 chanx_right_in[12]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.410969e-05 +88 chanx_right_in[12]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.112846e-05 +89 chanx_right_in[12]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.795641e-05 +90 chanx_right_in[12]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.553655e-05 +91 chanx_right_in[12]:13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.410969e-05 +92 chanx_right_in[12]:12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.112846e-05 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:34 0.001822033 +1 chanx_right_in[12]:7 mux_bottom_ipin_8\/mux_l2_in_2_:A1 0.152 +2 chanx_right_in[12]:9 chanx_right_in[12]:8 0.002424107 +3 chanx_right_in[12]:10 chanx_right_in[12]:9 0.0045 +4 chanx_right_in[12]:19 chanx_right_in[12]:18 0.00341 +5 chanx_right_in[12]:18 chanx_right_in[12]:17 0.0002859167 +6 chanx_right_in[12]:16 chanx_right_in[12]:15 0.0001634615 +7 chanx_right_in[12]:17 chanx_right_in[12]:16 0.00341 +8 chanx_right_in[12]:14 chanx_right_in[12]:13 0.001602679 +9 chanx_right_in[12]:15 chanx_right_in[12]:14 0.0045 +10 chanx_right_in[12]:11 FTB_33__32:A 0.152 +11 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0008325893 +12 chanx_right_in[12]:6 chanx_right_in[12]:5 0.0045 +13 chanx_right_in[12]:4 mux_bottom_ipin_12\/mux_l2_in_2_:A1 0.152 +14 chanx_right_in[12]:29 chanx_right_in[12]:28 0.0004107143 +15 chanx_right_in[12]:29 chanx_right_in[12]:6 0.002640625 +16 chanx_right_in[12]:30 chanx_right_in[12]:29 0.00341 +17 chanx_right_in[12]:31 chanx_right_in[12]:30 0.003094558 +18 chanx_right_in[12]:32 chanx_right_in[12]:31 0.00341 +19 chanx_right_in[12]:34 chanx_right_in[12]:33 0.00341 +20 chanx_right_in[12]:33 chanx_right_in[12]:32 0.0007433833 +21 chanx_right_in[12]:20 chanx_right_in[12]:19 0.001770089 +22 chanx_right_in[12]:20 chanx_right_in[12]:10 0.002388393 +23 chanx_right_in[12]:21 chanx_right_in[12]:20 0.00341 +24 chanx_right_in[12]:23 chanx_right_in[12]:22 0.00341 +25 chanx_right_in[12]:22 chanx_right_in[12]:21 0.005474716 +26 chanx_right_in[12]:24 chanx_right_in[12]:23 0.002933036 +27 chanx_right_in[12]:25 chanx_right_in[12]:24 0.00341 +28 chanx_right_in[12]:27 chanx_right_in[12]:26 0.00341 +29 chanx_right_in[12]:26 chanx_right_in[12]:25 0.003961316 +30 chanx_right_in[12]:8 chanx_right_in[12]:7 0.0003035715 +31 chanx_right_in[12]:13 chanx_right_in[12]:12 0.0003035715 +32 chanx_right_in[12]:12 chanx_right_in[12]:11 0.0003772322 +33 chanx_right_in[12]:28 chanx_right_in[12]:27 0.001770089 + +*END + +*D_NET chanx_right_in[17] 0.01908996 //LENGTH 126.065 LUMPCC 0.00705667 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 103.650 43.520 +*I mux_bottom_ipin_13\/mux_l2_in_3_:A1 I *L 0.00198 *C 71.300 56.100 +*I mux_bottom_ipin_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 51.425 61.540 +*I FTB_38__37:A I *L 0.001767 *C 6.900 61.200 +*N chanx_right_in[17]:4 *C 6.923 61.228 +*N chanx_right_in[17]:5 *C 6.935 61.540 +*N chanx_right_in[17]:6 *C 12.375 61.540 +*N chanx_right_in[17]:7 *C 12.420 61.540 +*N chanx_right_in[17]:8 *C 12.420 61.200 +*N chanx_right_in[17]:9 *C 12.428 61.200 +*N chanx_right_in[17]:10 *C 53.360 61.200 +*N chanx_right_in[17]:11 *C 51.425 61.540 +*N chanx_right_in[17]:12 *C 51.520 61.200 +*N chanx_right_in[17]:13 *C 53.360 61.200 +*N chanx_right_in[17]:14 *C 53.360 60.520 +*N chanx_right_in[17]:15 *C 53.360 60.520 +*N chanx_right_in[17]:16 *C 53.360 60.520 +*N chanx_right_in[17]:17 *C 71.300 56.115 +*N chanx_right_in[17]:18 *C 71.300 56.440 +*N chanx_right_in[17]:19 *C 71.300 56.485 +*N chanx_right_in[17]:20 *C 71.300 60.463 +*N chanx_right_in[17]:21 *C 71.300 60.520 +*N chanx_right_in[17]:22 *C 81.860 60.520 +*N chanx_right_in[17]:23 *C 81.880 60.513 +*N chanx_right_in[17]:24 *C 81.880 44.208 +*N chanx_right_in[17]:25 *C 81.900 44.200 +*N chanx_right_in[17]:26 *C 91.080 44.200 +*N chanx_right_in[17]:27 *C 91.080 43.520 + +*CAP +0 chanx_right_in[17] 0.0008310396 +1 mux_bottom_ipin_13\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_3_:A1 1e-06 +3 FTB_38__37:A 1e-06 +4 chanx_right_in[17]:4 3.624861e-05 +5 chanx_right_in[17]:5 0.0003442962 +6 chanx_right_in[17]:6 0.0003080476 +7 chanx_right_in[17]:7 6.264895e-05 +8 chanx_right_in[17]:8 6.700742e-05 +9 chanx_right_in[17]:9 0.001827274 +10 chanx_right_in[17]:10 0.001881547 +11 chanx_right_in[17]:11 5.529104e-05 +12 chanx_right_in[17]:12 0.0001673089 +13 chanx_right_in[17]:13 0.0001862758 +14 chanx_right_in[17]:14 7.888293e-05 +15 chanx_right_in[17]:15 3.806463e-05 +16 chanx_right_in[17]:16 0.0006573359 +17 chanx_right_in[17]:17 3.568196e-05 +18 chanx_right_in[17]:18 6.845946e-05 +19 chanx_right_in[17]:19 0.0002415555 +20 chanx_right_in[17]:20 0.0002415555 +21 chanx_right_in[17]:21 0.0008913174 +22 chanx_right_in[17]:22 0.0002882542 +23 chanx_right_in[17]:23 0.0008649417 +24 chanx_right_in[17]:24 0.0008649417 +25 chanx_right_in[17]:25 0.0005188188 +26 chanx_right_in[17]:26 0.0005806377 +27 chanx_right_in[17]:27 0.0008928584 +28 chanx_right_in[17]:22 chanx_left_in[11]:14 0.0002317675 +29 chanx_right_in[17]:16 chanx_left_in[11]:19 0.0002602028 +30 chanx_right_in[17]:16 chanx_left_in[11]:23 0.000120196 +31 chanx_right_in[17]:21 chanx_left_in[11]:14 0.0002602028 +32 chanx_right_in[17]:21 chanx_left_in[11]:19 0.0003519634 +33 chanx_right_in[17]:9 chanx_left_in[11]:23 0.0001686951 +34 chanx_right_in[17]:9 chanx_left_in[11]:24 0.0002493129 +35 chanx_right_in[17]:10 chanx_left_in[11]:19 0.0001686951 +36 chanx_right_in[17]:10 chanx_left_in[11]:23 0.0002493129 +37 chanx_right_in[17] chanx_left_in[15]:13 0.0001088791 +38 chanx_right_in[17]:25 chanx_left_in[15]:14 0.0001700403 +39 chanx_right_in[17]:26 chanx_left_in[15]:13 0.0001700403 +40 chanx_right_in[17]:27 chanx_left_in[15]:14 0.0001088791 +41 chanx_right_in[17]:20 chanx_left_in[17]:7 7.770729e-06 +42 chanx_right_in[17]:19 chanx_left_in[17]:8 7.770729e-06 +43 chanx_right_in[17]:9 chanx_left_in[17] 1.606996e-05 +44 chanx_right_in[17]:9 chanx_left_in[17]:29 0.0004497387 +45 chanx_right_in[17]:9 chanx_left_in[17]:31 1.516407e-05 +46 chanx_right_in[17]:10 chanx_left_in[17]:28 0.0004497387 +47 chanx_right_in[17]:10 chanx_left_in[17]:30 1.516407e-05 +48 chanx_right_in[17]:10 chanx_left_in[17]:32 1.606996e-05 +49 chanx_right_in[17]:22 chanx_right_in[5] 0.0005887047 +50 chanx_right_in[17]:16 chanx_right_in[5]:26 0.0005179264 +51 chanx_right_in[17]:21 chanx_right_in[5] 0.0005179264 +52 chanx_right_in[17]:21 chanx_right_in[5]:26 0.0005887047 +53 chanx_right_in[17]:16 chanx_right_in[19]:20 7.900539e-05 +54 chanx_right_in[17]:21 chanx_right_in[19]:21 7.900539e-05 +55 chanx_right_in[17]:9 chanx_right_in[19]:20 0.0001977562 +56 chanx_right_in[17]:10 chanx_right_in[19]:21 0.0001977562 +57 chanx_right_in[17]:9 mux_tree_tapbuf_size10_5_sram[2]:18 0.0001164667 +58 chanx_right_in[17]:6 mux_tree_tapbuf_size10_5_sram[2]:16 9.610108e-05 +59 chanx_right_in[17]:5 mux_tree_tapbuf_size10_5_sram[2]:15 9.610108e-05 +60 chanx_right_in[17]:10 mux_tree_tapbuf_size10_5_sram[2]:19 0.0001164667 +61 chanx_right_in[17]:23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001345379 +62 chanx_right_in[17]:24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001345379 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:27 0.0019693 +1 chanx_right_in[17]:22 chanx_right_in[17]:21 0.0016544 +2 chanx_right_in[17]:23 chanx_right_in[17]:22 0.00341 +3 chanx_right_in[17]:25 chanx_right_in[17]:24 0.00341 +4 chanx_right_in[17]:24 chanx_right_in[17]:23 0.00255445 +5 chanx_right_in[17]:15 chanx_right_in[17]:14 0.0045 +6 chanx_right_in[17]:16 chanx_right_in[17]:15 0.00341 +7 chanx_right_in[17]:16 chanx_right_in[17]:10 0.0001065333 +8 chanx_right_in[17]:14 chanx_right_in[17]:13 0.0006071429 +9 chanx_right_in[17]:11 mux_bottom_ipin_1\/mux_l2_in_3_:A1 0.152 +10 chanx_right_in[17]:20 chanx_right_in[17]:19 0.003551339 +11 chanx_right_in[17]:21 chanx_right_in[17]:20 0.00341 +12 chanx_right_in[17]:21 chanx_right_in[17]:16 0.0028106 +13 chanx_right_in[17]:18 chanx_right_in[17]:17 0.0001766305 +14 chanx_right_in[17]:19 chanx_right_in[17]:18 0.0045 +15 chanx_right_in[17]:17 mux_bottom_ipin_13\/mux_l2_in_3_:A1 0.152 +16 chanx_right_in[17]:8 chanx_right_in[17]:7 0.0001634615 +17 chanx_right_in[17]:9 chanx_right_in[17]:8 0.00341 +18 chanx_right_in[17]:6 chanx_right_in[17]:5 0.004857143 +19 chanx_right_in[17]:7 chanx_right_in[17]:6 0.0045 +20 chanx_right_in[17]:4 FTB_38__37:A 0.152 +21 chanx_right_in[17]:5 chanx_right_in[17]:4 0.0002111487 +22 chanx_right_in[17]:12 chanx_right_in[17]:11 0.0003035715 +23 chanx_right_in[17]:13 chanx_right_in[17]:12 0.001642857 +24 chanx_right_in[17]:10 chanx_right_in[17]:9 0.006412758 +25 chanx_right_in[17]:26 chanx_right_in[17]:25 0.0014382 +26 chanx_right_in[17]:27 chanx_right_in[17]:26 0.0001065333 + +*END + +*D_NET top_grid_pin_25_[0] 0.0004967368 //LENGTH 4.575 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 11.100 72.080 +*P top_grid_pin_25_[0] O *L 0.7423 *C 12.420 74.870 +*N top_grid_pin_25_[0]:2 *C 12.420 72.125 +*N top_grid_pin_25_[0]:3 *C 12.375 72.080 +*N top_grid_pin_25_[0]:4 *C 11.138 72.080 + +*CAP +0 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_25_[0] 0.0001537546 +2 top_grid_pin_25_[0]:2 0.0001537546 +3 top_grid_pin_25_[0]:3 9.411378e-05 +4 top_grid_pin_25_[0]:4 9.411378e-05 + +*RES +0 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_25_[0]:4 0.152 +1 top_grid_pin_25_[0]:4 top_grid_pin_25_[0]:3 0.001104911 +2 top_grid_pin_25_[0]:3 top_grid_pin_25_[0]:2 0.0045 +3 top_grid_pin_25_[0]:2 top_grid_pin_25_[0] 0.002450893 + +*END + +*D_NET ropt_net_128 0.0009424256 //LENGTH 8.100 LUMPCC 0.0001621941 DR + +*CONN +*I mem_top_ipin_0\/BUFT_RR_93:X O *L 0 *C 63.940 3.740 +*I ropt_mt_inst_727:A I *L 0.001766 *C 56.580 4.080 +*N ropt_net_128:2 *C 56.580 4.080 +*N ropt_net_128:3 *C 56.580 3.740 +*N ropt_net_128:4 *C 63.903 3.740 + +*CAP +0 mem_top_ipin_0\/BUFT_RR_93:X 1e-06 +1 ropt_mt_inst_727:A 1e-06 +2 ropt_net_128:2 4.932543e-05 +3 ropt_net_128:3 0.0003766719 +4 ropt_net_128:4 0.0003522342 +5 ropt_net_128:4 chanx_right_in[16]:16 8.109705e-05 +6 ropt_net_128:3 chanx_right_in[16]:15 8.109705e-05 + +*RES +0 mem_top_ipin_0\/BUFT_RR_93:X ropt_net_128:4 0.152 +1 ropt_net_128:4 ropt_net_128:3 0.006537946 +2 ropt_net_128:2 ropt_mt_inst_727:A 0.152 +3 ropt_net_128:3 ropt_net_128:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.004843134 //LENGTH 35.845 LUMPCC 0.0003298207 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 65.625 63.920 +*I mux_bottom_ipin_1\/mux_l2_in_1_:S I *L 0.00357 *C 58.060 61.540 +*I mux_bottom_ipin_1\/mux_l2_in_2_:S I *L 0.00357 *C 47.740 55.760 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 51.695 66.300 +*I mux_bottom_ipin_1\/mux_l2_in_3_:S I *L 0.00357 *C 50.700 61.495 +*I mux_bottom_ipin_1\/mux_l2_in_0_:S I *L 0.00357 *C 63.120 61.495 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 63.120 61.495 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 50.700 61.495 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 50.700 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 51.980 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 51.695 66.300 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 51.980 66.300 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 51.980 66.255 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 47.778 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 51.935 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 51.980 55.805 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 51.980 61.540 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 51.980 61.540 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 58.060 61.562 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 58.060 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 63.120 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 65.275 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 65.320 61.925 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 65.320 63.875 +*N mux_tree_tapbuf_size10_1_sram[1]:24 *C 65.320 63.920 +*N mux_tree_tapbuf_size10_1_sram[1]:25 *C 65.625 63.920 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_2_:S 1e-06 +3 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_ipin_1\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_1\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 5.42544e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:7 4.920844e-05 +8 mux_tree_tapbuf_size10_1_sram[1]:8 0.0001324494 +9 mux_tree_tapbuf_size10_1_sram[1]:9 0.0001354918 +10 mux_tree_tapbuf_size10_1_sram[1]:10 5.056711e-05 +11 mux_tree_tapbuf_size10_1_sram[1]:11 5.458541e-05 +12 mux_tree_tapbuf_size10_1_sram[1]:12 0.0002534871 +13 mux_tree_tapbuf_size10_1_sram[1]:13 0.0003306389 +14 mux_tree_tapbuf_size10_1_sram[1]:14 0.0003306389 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0003508572 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0006381561 +17 mux_tree_tapbuf_size10_1_sram[1]:17 0.0003881436 +18 mux_tree_tapbuf_size10_1_sram[1]:18 0.0003874447 +19 mux_tree_tapbuf_size10_1_sram[1]:19 0.0003348157 +20 mux_tree_tapbuf_size10_1_sram[1]:20 0.0005019833 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.0001667637 +22 mux_tree_tapbuf_size10_1_sram[1]:22 0.0001249461 +23 mux_tree_tapbuf_size10_1_sram[1]:23 0.0001249461 +24 mux_tree_tapbuf_size10_1_sram[1]:24 5.059176e-05 +25 mux_tree_tapbuf_size10_1_sram[1]:25 4.734301e-05 +26 mux_tree_tapbuf_size10_1_sram[1]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.672295e-07 +27 mux_tree_tapbuf_size10_1_sram[1]:18 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001024466 +28 mux_tree_tapbuf_size10_1_sram[1]:15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.723516e-07 +29 mux_tree_tapbuf_size10_1_sram[1]:17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001024466 +30 mux_tree_tapbuf_size10_1_sram[1]:16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.672295e-07 +31 mux_tree_tapbuf_size10_1_sram[1]:16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.723516e-07 +32 mux_tree_tapbuf_size10_1_sram[1]:19 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.132415e-05 +33 mux_tree_tapbuf_size10_1_sram[1]:20 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.132415e-05 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:25 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:10 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size10_1_sram[1]:11 mux_tree_tapbuf_size10_1_sram[1]:10 0.0001548913 +3 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size10_1_sram[1]:18 mux_bottom_ipin_1\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[1]:17 0.005428571 +6 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[1]:13 0.003712053 +7 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size10_1_sram[1]:13 mux_bottom_ipin_1\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size10_1_sram[1]:7 mux_bottom_ipin_1\/mux_l2_in_3_:S 0.152 +10 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.001924107 +11 mux_tree_tapbuf_size10_1_sram[1]:22 mux_tree_tapbuf_size10_1_sram[1]:21 0.0045 +12 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:23 0.0045 +13 mux_tree_tapbuf_size10_1_sram[1]:23 mux_tree_tapbuf_size10_1_sram[1]:22 0.001741071 +14 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:24 0.0001657609 +15 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.0045 +16 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:9 0.0003035715 +17 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.005120536 +18 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:12 0.004209822 +19 mux_tree_tapbuf_size10_1_sram[1]:6 mux_bottom_ipin_1\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size10_1_sram[1]:8 mux_tree_tapbuf_size10_1_sram[1]:7 0.00034375 +21 mux_tree_tapbuf_size10_1_sram[1]:9 mux_tree_tapbuf_size10_1_sram[1]:8 0.001142857 +22 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.0002834822 +23 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.004517857 +24 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:6 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[0] 0.00466203 //LENGTH 33.135 LUMPCC 0.000117766 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 27.445 31.280 +*I mux_bottom_ipin_8\/mux_l1_in_0_:S I *L 0.00357 *C 23.100 28.855 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 16.275 26.180 +*I mux_bottom_ipin_8\/mux_l1_in_2_:S I *L 0.00357 *C 13.460 25.160 +*I mux_bottom_ipin_8\/mux_l1_in_1_:S I *L 0.00357 *C 16.200 19.720 +*N mux_tree_tapbuf_size10_4_sram[0]:5 *C 16.163 19.720 +*N mux_tree_tapbuf_size10_4_sram[0]:6 *C 13.845 19.720 +*N mux_tree_tapbuf_size10_4_sram[0]:7 *C 13.800 19.765 +*N mux_tree_tapbuf_size10_4_sram[0]:8 *C 13.800 23.120 +*N mux_tree_tapbuf_size10_4_sram[0]:9 *C 13.340 23.120 +*N mux_tree_tapbuf_size10_4_sram[0]:10 *C 13.340 25.160 +*N mux_tree_tapbuf_size10_4_sram[0]:11 *C 13.340 25.160 +*N mux_tree_tapbuf_size10_4_sram[0]:12 *C 13.340 26.135 +*N mux_tree_tapbuf_size10_4_sram[0]:13 *C 13.385 26.180 +*N mux_tree_tapbuf_size10_4_sram[0]:14 *C 16.275 26.180 +*N mux_tree_tapbuf_size10_4_sram[0]:15 *C 22.495 26.180 +*N mux_tree_tapbuf_size10_4_sram[0]:16 *C 22.540 26.225 +*N mux_tree_tapbuf_size10_4_sram[0]:17 *C 22.540 29.195 +*N mux_tree_tapbuf_size10_4_sram[0]:18 *C 22.585 29.240 +*N mux_tree_tapbuf_size10_4_sram[0]:19 *C 23.100 29.240 +*N mux_tree_tapbuf_size10_4_sram[0]:20 *C 23.120 28.560 +*N mux_tree_tapbuf_size10_4_sram[0]:21 *C 23.100 28.855 +*N mux_tree_tapbuf_size10_4_sram[0]:22 *C 23.175 28.560 +*N mux_tree_tapbuf_size10_4_sram[0]:23 *C 25.715 28.560 +*N mux_tree_tapbuf_size10_4_sram[0]:24 *C 25.760 28.605 +*N mux_tree_tapbuf_size10_4_sram[0]:25 *C 25.760 31.235 +*N mux_tree_tapbuf_size10_4_sram[0]:26 *C 25.805 31.280 +*N mux_tree_tapbuf_size10_4_sram[0]:27 *C 27.408 31.280 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_8\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_ipin_8\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_ipin_8\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_4_sram[0]:5 0.0002083206 +6 mux_tree_tapbuf_size10_4_sram[0]:6 0.0002083206 +7 mux_tree_tapbuf_size10_4_sram[0]:7 0.0002398093 +8 mux_tree_tapbuf_size10_4_sram[0]:8 0.0002614195 +9 mux_tree_tapbuf_size10_4_sram[0]:9 0.0001223389 +10 mux_tree_tapbuf_size10_4_sram[0]:10 3.490121e-05 +11 mux_tree_tapbuf_size10_4_sram[0]:11 0.0001914418 +12 mux_tree_tapbuf_size10_4_sram[0]:12 5.835784e-05 +13 mux_tree_tapbuf_size10_4_sram[0]:13 0.0002404483 +14 mux_tree_tapbuf_size10_4_sram[0]:14 0.0007547007 +15 mux_tree_tapbuf_size10_4_sram[0]:15 0.0004833357 +16 mux_tree_tapbuf_size10_4_sram[0]:16 0.0002000289 +17 mux_tree_tapbuf_size10_4_sram[0]:17 0.0002000289 +18 mux_tree_tapbuf_size10_4_sram[0]:18 6.27093e-05 +19 mux_tree_tapbuf_size10_4_sram[0]:19 8.682917e-05 +20 mux_tree_tapbuf_size10_4_sram[0]:20 3.064761e-05 +21 mux_tree_tapbuf_size10_4_sram[0]:21 9.811534e-05 +22 mux_tree_tapbuf_size10_4_sram[0]:22 0.0002571365 +23 mux_tree_tapbuf_size10_4_sram[0]:23 0.0002200283 +24 mux_tree_tapbuf_size10_4_sram[0]:24 0.0001714678 +25 mux_tree_tapbuf_size10_4_sram[0]:25 0.0001714678 +26 mux_tree_tapbuf_size10_4_sram[0]:26 0.0001187052 +27 mux_tree_tapbuf_size10_4_sram[0]:27 0.0001187052 +28 mux_tree_tapbuf_size10_4_sram[0]:12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.364072e-05 +29 mux_tree_tapbuf_size10_4_sram[0]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.439146e-05 +30 mux_tree_tapbuf_size10_4_sram[0]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.364072e-05 +31 mux_tree_tapbuf_size10_4_sram[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.189854e-06 +32 mux_tree_tapbuf_size10_4_sram[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.189854e-06 +33 mux_tree_tapbuf_size10_4_sram[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.135381e-06 +34 mux_tree_tapbuf_size10_4_sram[0]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.525577e-06 +35 mux_tree_tapbuf_size10_4_sram[0]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.439146e-05 +36 mux_tree_tapbuf_size10_4_sram[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.135381e-06 +37 mux_tree_tapbuf_size10_4_sram[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.525577e-06 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_4_sram[0]:27 0.152 +1 mux_tree_tapbuf_size10_4_sram[0]:13 mux_tree_tapbuf_size10_4_sram[0]:12 0.0045 +2 mux_tree_tapbuf_size10_4_sram[0]:12 mux_tree_tapbuf_size10_4_sram[0]:11 0.0008705358 +3 mux_tree_tapbuf_size10_4_sram[0]:15 mux_tree_tapbuf_size10_4_sram[0]:14 0.005553572 +4 mux_tree_tapbuf_size10_4_sram[0]:16 mux_tree_tapbuf_size10_4_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size10_4_sram[0]:18 mux_tree_tapbuf_size10_4_sram[0]:17 0.0045 +6 mux_tree_tapbuf_size10_4_sram[0]:17 mux_tree_tapbuf_size10_4_sram[0]:16 0.002651786 +7 mux_tree_tapbuf_size10_4_sram[0]:23 mux_tree_tapbuf_size10_4_sram[0]:22 0.002267857 +8 mux_tree_tapbuf_size10_4_sram[0]:24 mux_tree_tapbuf_size10_4_sram[0]:23 0.0045 +9 mux_tree_tapbuf_size10_4_sram[0]:26 mux_tree_tapbuf_size10_4_sram[0]:25 0.0045 +10 mux_tree_tapbuf_size10_4_sram[0]:25 mux_tree_tapbuf_size10_4_sram[0]:24 0.002348214 +11 mux_tree_tapbuf_size10_4_sram[0]:27 mux_tree_tapbuf_size10_4_sram[0]:26 0.001430804 +12 mux_tree_tapbuf_size10_4_sram[0]:14 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size10_4_sram[0]:14 mux_tree_tapbuf_size10_4_sram[0]:13 0.002580357 +14 mux_tree_tapbuf_size10_4_sram[0]:10 mux_bottom_ipin_8\/mux_l1_in_2_:S 0.152 +15 mux_tree_tapbuf_size10_4_sram[0]:11 mux_tree_tapbuf_size10_4_sram[0]:10 0.0045 +16 mux_tree_tapbuf_size10_4_sram[0]:11 mux_tree_tapbuf_size10_4_sram[0]:9 0.001821429 +17 mux_tree_tapbuf_size10_4_sram[0]:5 mux_bottom_ipin_8\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_4_sram[0]:6 mux_tree_tapbuf_size10_4_sram[0]:5 0.002069197 +19 mux_tree_tapbuf_size10_4_sram[0]:7 mux_tree_tapbuf_size10_4_sram[0]:6 0.0045 +20 mux_tree_tapbuf_size10_4_sram[0]:21 mux_bottom_ipin_8\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_4_sram[0]:21 mux_tree_tapbuf_size10_4_sram[0]:20 0.0002633929 +22 mux_tree_tapbuf_size10_4_sram[0]:21 mux_tree_tapbuf_size10_4_sram[0]:19 0.00034375 +23 mux_tree_tapbuf_size10_4_sram[0]:19 mux_tree_tapbuf_size10_4_sram[0]:18 0.0004598215 +24 mux_tree_tapbuf_size10_4_sram[0]:22 mux_tree_tapbuf_size10_4_sram[0]:21 0.0002633929 +25 mux_tree_tapbuf_size10_4_sram[0]:9 mux_tree_tapbuf_size10_4_sram[0]:8 0.0004107143 +26 mux_tree_tapbuf_size10_4_sram[0]:8 mux_tree_tapbuf_size10_4_sram[0]:7 0.002995536 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[1] 0.004722997 //LENGTH 34.955 LUMPCC 0.0005645122 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 83.565 61.200 +*I mux_bottom_ipin_13\/mux_l2_in_0_:S I *L 0.00357 *C 76.920 58.480 +*I mux_bottom_ipin_13\/mux_l2_in_3_:S I *L 0.00357 *C 70.480 56.440 +*I mux_bottom_ipin_13\/mux_l2_in_2_:S I *L 0.00357 *C 69.560 57.800 +*I mux_bottom_ipin_13\/mux_l2_in_1_:S I *L 0.00357 *C 74.620 56.055 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 76.075 66.300 +*N mux_tree_tapbuf_size10_7_sram[1]:6 *C 76.112 66.300 +*N mux_tree_tapbuf_size10_7_sram[1]:7 *C 77.235 66.300 +*N mux_tree_tapbuf_size10_7_sram[1]:8 *C 77.280 66.255 +*N mux_tree_tapbuf_size10_7_sram[1]:9 *C 76.820 58.385 +*N mux_tree_tapbuf_size10_7_sram[1]:10 *C 74.620 56.055 +*N mux_tree_tapbuf_size10_7_sram[1]:11 *C 74.620 56.440 +*N mux_tree_tapbuf_size10_7_sram[1]:12 *C 76.775 56.440 +*N mux_tree_tapbuf_size10_7_sram[1]:13 *C 76.820 56.485 +*N mux_tree_tapbuf_size10_7_sram[1]:14 *C 69.597 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:15 *C 70.495 56.440 +*N mux_tree_tapbuf_size10_7_sram[1]:16 *C 70.818 56.440 +*N mux_tree_tapbuf_size10_7_sram[1]:17 *C 70.840 56.485 +*N mux_tree_tapbuf_size10_7_sram[1]:18 *C 70.840 57.755 +*N mux_tree_tapbuf_size10_7_sram[1]:19 *C 70.840 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:20 *C 76.775 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:21 *C 76.820 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:22 *C 76.820 58.480 +*N mux_tree_tapbuf_size10_7_sram[1]:23 *C 76.850 58.510 +*N mux_tree_tapbuf_size10_7_sram[1]:24 *C 76.865 58.820 +*N mux_tree_tapbuf_size10_7_sram[1]:25 *C 77.280 58.820 +*N mux_tree_tapbuf_size10_7_sram[1]:26 *C 77.280 63.920 +*N mux_tree_tapbuf_size10_7_sram[1]:27 *C 77.325 63.920 +*N mux_tree_tapbuf_size10_7_sram[1]:28 *C 83.215 63.920 +*N mux_tree_tapbuf_size10_7_sram[1]:29 *C 83.260 63.875 +*N mux_tree_tapbuf_size10_7_sram[1]:30 *C 83.260 61.245 +*N mux_tree_tapbuf_size10_7_sram[1]:31 *C 83.260 61.200 +*N mux_tree_tapbuf_size10_7_sram[1]:32 *C 83.565 61.200 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_13\/mux_l2_in_2_:S 1e-06 +4 mux_bottom_ipin_13\/mux_l2_in_1_:S 1e-06 +5 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_7_sram[1]:6 9.791375e-05 +7 mux_tree_tapbuf_size10_7_sram[1]:7 9.791375e-05 +8 mux_tree_tapbuf_size10_7_sram[1]:8 0.0001438528 +9 mux_tree_tapbuf_size10_7_sram[1]:9 1.00096e-05 +10 mux_tree_tapbuf_size10_7_sram[1]:10 6.471443e-05 +11 mux_tree_tapbuf_size10_7_sram[1]:11 0.0001978078 +12 mux_tree_tapbuf_size10_7_sram[1]:12 0.0001637441 +13 mux_tree_tapbuf_size10_7_sram[1]:13 9.482557e-05 +14 mux_tree_tapbuf_size10_7_sram[1]:14 7.558715e-05 +15 mux_tree_tapbuf_size10_7_sram[1]:15 4.705328e-05 +16 mux_tree_tapbuf_size10_7_sram[1]:16 4.705328e-05 +17 mux_tree_tapbuf_size10_7_sram[1]:17 0.0001007946 +18 mux_tree_tapbuf_size10_7_sram[1]:18 0.0001007946 +19 mux_tree_tapbuf_size10_7_sram[1]:19 0.0003822507 +20 mux_tree_tapbuf_size10_7_sram[1]:20 0.0002680971 +21 mux_tree_tapbuf_size10_7_sram[1]:21 0.0001629818 +22 mux_tree_tapbuf_size10_7_sram[1]:22 3.694129e-05 +23 mux_tree_tapbuf_size10_7_sram[1]:23 6.928981e-05 +24 mux_tree_tapbuf_size10_7_sram[1]:24 5.646282e-05 +25 mux_tree_tapbuf_size10_7_sram[1]:25 0.0003404636 +26 mux_tree_tapbuf_size10_7_sram[1]:26 0.0004850197 +27 mux_tree_tapbuf_size10_7_sram[1]:27 0.0003698501 +28 mux_tree_tapbuf_size10_7_sram[1]:28 0.0003698501 +29 mux_tree_tapbuf_size10_7_sram[1]:29 0.0001322984 +30 mux_tree_tapbuf_size10_7_sram[1]:30 0.0001322984 +31 mux_tree_tapbuf_size10_7_sram[1]:31 5.312653e-05 +32 mux_tree_tapbuf_size10_7_sram[1]:32 5.148844e-05 +33 mux_tree_tapbuf_size10_7_sram[1]:14 chanx_right_in[13]:4 2.57343e-05 +34 mux_tree_tapbuf_size10_7_sram[1]:19 chanx_right_in[13]:4 0.0002234245 +35 mux_tree_tapbuf_size10_7_sram[1]:19 chanx_right_in[13]:5 2.57343e-05 +36 mux_tree_tapbuf_size10_7_sram[1]:29 chanx_right_in[13]:23 3.309734e-05 +37 mux_tree_tapbuf_size10_7_sram[1]:30 chanx_right_in[13]:8 3.309734e-05 +38 mux_tree_tapbuf_size10_7_sram[1]:20 chanx_right_in[13]:5 0.0002234245 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_7_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_7_sram[1]:14 mux_bottom_ipin_13\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[1]:12 mux_tree_tapbuf_size10_7_sram[1]:11 0.001924107 +3 mux_tree_tapbuf_size10_7_sram[1]:13 mux_tree_tapbuf_size10_7_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size10_7_sram[1]:10 mux_bottom_ipin_13\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_7_sram[1]:22 mux_bottom_ipin_13\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:22 0.0045 +7 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:21 0.0006339286 +8 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:9 0.0001116071 +9 mux_tree_tapbuf_size10_7_sram[1]:19 mux_tree_tapbuf_size10_7_sram[1]:18 0.0045 +10 mux_tree_tapbuf_size10_7_sram[1]:19 mux_tree_tapbuf_size10_7_sram[1]:14 0.001109375 +11 mux_tree_tapbuf_size10_7_sram[1]:18 mux_tree_tapbuf_size10_7_sram[1]:17 0.001133928 +12 mux_tree_tapbuf_size10_7_sram[1]:16 mux_tree_tapbuf_size10_7_sram[1]:15 0.0001752718 +13 mux_tree_tapbuf_size10_7_sram[1]:17 mux_tree_tapbuf_size10_7_sram[1]:16 0.0045 +14 mux_tree_tapbuf_size10_7_sram[1]:15 mux_bottom_ipin_13\/mux_l2_in_3_:S 0.152 +15 mux_tree_tapbuf_size10_7_sram[1]:7 mux_tree_tapbuf_size10_7_sram[1]:6 0.001002232 +16 mux_tree_tapbuf_size10_7_sram[1]:8 mux_tree_tapbuf_size10_7_sram[1]:7 0.0045 +17 mux_tree_tapbuf_size10_7_sram[1]:6 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size10_7_sram[1]:27 mux_tree_tapbuf_size10_7_sram[1]:26 0.0045 +19 mux_tree_tapbuf_size10_7_sram[1]:26 mux_tree_tapbuf_size10_7_sram[1]:25 0.004553572 +20 mux_tree_tapbuf_size10_7_sram[1]:26 mux_tree_tapbuf_size10_7_sram[1]:8 0.002084821 +21 mux_tree_tapbuf_size10_7_sram[1]:28 mux_tree_tapbuf_size10_7_sram[1]:27 0.005258929 +22 mux_tree_tapbuf_size10_7_sram[1]:29 mux_tree_tapbuf_size10_7_sram[1]:28 0.0045 +23 mux_tree_tapbuf_size10_7_sram[1]:31 mux_tree_tapbuf_size10_7_sram[1]:30 0.0045 +24 mux_tree_tapbuf_size10_7_sram[1]:30 mux_tree_tapbuf_size10_7_sram[1]:29 0.002348214 +25 mux_tree_tapbuf_size10_7_sram[1]:32 mux_tree_tapbuf_size10_7_sram[1]:31 0.0001657609 +26 mux_tree_tapbuf_size10_7_sram[1]:20 mux_tree_tapbuf_size10_7_sram[1]:19 0.005299108 +27 mux_tree_tapbuf_size10_7_sram[1]:21 mux_tree_tapbuf_size10_7_sram[1]:20 0.0045 +28 mux_tree_tapbuf_size10_7_sram[1]:21 mux_tree_tapbuf_size10_7_sram[1]:13 0.001174107 +29 mux_tree_tapbuf_size10_7_sram[1]:11 mux_tree_tapbuf_size10_7_sram[1]:10 0.00034375 +30 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:23 0.00019375 +31 mux_tree_tapbuf_size10_7_sram[1]:25 mux_tree_tapbuf_size10_7_sram[1]:24 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[0] 0.003684742 //LENGTH 29.485 LUMPCC 0.0004904551 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.745 39.100 +*I mux_bottom_ipin_6\/mux_l1_in_0_:S I *L 0.00357 *C 53.920 23.460 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 49.855 15.300 +*N mux_tree_tapbuf_size8_2_sram[0]:3 *C 49.855 15.300 +*N mux_tree_tapbuf_size8_2_sram[0]:4 *C 50.140 15.300 +*N mux_tree_tapbuf_size8_2_sram[0]:5 *C 50.140 15.345 +*N mux_tree_tapbuf_size8_2_sram[0]:6 *C 50.140 16.262 +*N mux_tree_tapbuf_size8_2_sram[0]:7 *C 50.148 16.320 +*N mux_tree_tapbuf_size8_2_sram[0]:8 *C 52.893 16.320 +*N mux_tree_tapbuf_size8_2_sram[0]:9 *C 52.900 16.378 +*N mux_tree_tapbuf_size8_2_sram[0]:10 *C 53.883 23.460 +*N mux_tree_tapbuf_size8_2_sram[0]:11 *C 52.945 23.460 +*N mux_tree_tapbuf_size8_2_sram[0]:12 *C 52.900 23.460 +*N mux_tree_tapbuf_size8_2_sram[0]:13 *C 52.900 39.055 +*N mux_tree_tapbuf_size8_2_sram[0]:14 *C 52.900 39.100 +*N mux_tree_tapbuf_size8_2_sram[0]:15 *C 52.745 39.100 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_2_sram[0]:3 4.992638e-05 +4 mux_tree_tapbuf_size8_2_sram[0]:4 5.101832e-05 +5 mux_tree_tapbuf_size8_2_sram[0]:5 7.306522e-05 +6 mux_tree_tapbuf_size8_2_sram[0]:6 7.306522e-05 +7 mux_tree_tapbuf_size8_2_sram[0]:7 0.0001025674 +8 mux_tree_tapbuf_size8_2_sram[0]:8 0.0001025674 +9 mux_tree_tapbuf_size8_2_sram[0]:9 0.0003662875 +10 mux_tree_tapbuf_size8_2_sram[0]:10 0.0001131381 +11 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001131381 +12 mux_tree_tapbuf_size8_2_sram[0]:12 0.001225081 +13 mux_tree_tapbuf_size8_2_sram[0]:13 0.0008268278 +14 mux_tree_tapbuf_size8_2_sram[0]:14 4.937988e-05 +15 mux_tree_tapbuf_size8_2_sram[0]:15 4.522449e-05 +16 mux_tree_tapbuf_size8_2_sram[0]:8 chanx_right_in[14]:30 0.000176938 +17 mux_tree_tapbuf_size8_2_sram[0]:7 chanx_right_in[14]:26 0.000176938 +18 mux_tree_tapbuf_size8_2_sram[0]:10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.18694e-06 +19 mux_tree_tapbuf_size8_2_sram[0]:11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.18694e-06 +20 mux_tree_tapbuf_size8_2_sram[0]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.710261e-05 +21 mux_tree_tapbuf_size8_2_sram[0]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.710261e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_2_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_2_sram[0]:10 mux_bottom_ipin_6\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_2_sram[0]:11 mux_tree_tapbuf_size8_2_sram[0]:10 0.0008370536 +3 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:9 0.006323661 +5 mux_tree_tapbuf_size8_2_sram[0]:9 mux_tree_tapbuf_size8_2_sram[0]:8 0.00341 +6 mux_tree_tapbuf_size8_2_sram[0]:8 mux_tree_tapbuf_size8_2_sram[0]:7 0.00043005 +7 mux_tree_tapbuf_size8_2_sram[0]:6 mux_tree_tapbuf_size8_2_sram[0]:5 0.0008191965 +8 mux_tree_tapbuf_size8_2_sram[0]:7 mux_tree_tapbuf_size8_2_sram[0]:6 0.00341 +9 mux_tree_tapbuf_size8_2_sram[0]:4 mux_tree_tapbuf_size8_2_sram[0]:3 0.0001548913 +10 mux_tree_tapbuf_size8_2_sram[0]:5 mux_tree_tapbuf_size8_2_sram[0]:4 0.0045 +11 mux_tree_tapbuf_size8_2_sram[0]:3 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size8_2_sram[0]:14 mux_tree_tapbuf_size8_2_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size8_2_sram[0]:13 mux_tree_tapbuf_size8_2_sram[0]:12 0.01392411 +14 mux_tree_tapbuf_size8_2_sram[0]:15 mux_tree_tapbuf_size8_2_sram[0]:14 8.423915e-05 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[2] 0.003345405 //LENGTH 24.795 LUMPCC 0.0008173946 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 26.525 39.100 +*I mux_bottom_ipin_11\/mux_l3_in_1_:S I *L 0.00357 *C 31.840 47.310 +*I mux_bottom_ipin_11\/mux_l3_in_0_:S I *L 0.00357 *C 25.660 47.600 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 29.615 39.100 +*N mux_tree_tapbuf_size8_5_sram[2]:4 *C 29.490 39.100 +*N mux_tree_tapbuf_size8_5_sram[2]:5 *C 25.698 47.600 +*N mux_tree_tapbuf_size8_5_sram[2]:6 *C 31.783 47.600 +*N mux_tree_tapbuf_size8_5_sram[2]:7 *C 31.840 47.310 +*N mux_tree_tapbuf_size8_5_sram[2]:8 *C 31.840 46.920 +*N mux_tree_tapbuf_size8_5_sram[2]:9 *C 33.075 46.920 +*N mux_tree_tapbuf_size8_5_sram[2]:10 *C 33.120 46.875 +*N mux_tree_tapbuf_size8_5_sram[2]:11 *C 33.120 41.525 +*N mux_tree_tapbuf_size8_5_sram[2]:12 *C 33.075 41.480 +*N mux_tree_tapbuf_size8_5_sram[2]:13 *C 29.485 41.480 +*N mux_tree_tapbuf_size8_5_sram[2]:14 *C 29.440 41.435 +*N mux_tree_tapbuf_size8_5_sram[2]:15 *C 29.440 39.145 +*N mux_tree_tapbuf_size8_5_sram[2]:16 *C 29.395 39.100 +*N mux_tree_tapbuf_size8_5_sram[2]:17 *C 26.562 39.100 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_11\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_5_sram[2]:4 2.292267e-05 +5 mux_tree_tapbuf_size8_5_sram[2]:5 0.0002260778 +6 mux_tree_tapbuf_size8_5_sram[2]:6 0.000253737 +7 mux_tree_tapbuf_size8_5_sram[2]:7 8.174121e-05 +8 mux_tree_tapbuf_size8_5_sram[2]:8 0.0001437643 +9 mux_tree_tapbuf_size8_5_sram[2]:9 0.0001185583 +10 mux_tree_tapbuf_size8_5_sram[2]:10 0.0002943362 +11 mux_tree_tapbuf_size8_5_sram[2]:11 0.0002943362 +12 mux_tree_tapbuf_size8_5_sram[2]:12 0.0002077714 +13 mux_tree_tapbuf_size8_5_sram[2]:13 0.0002077714 +14 mux_tree_tapbuf_size8_5_sram[2]:14 0.0001387513 +15 mux_tree_tapbuf_size8_5_sram[2]:15 0.0001387513 +16 mux_tree_tapbuf_size8_5_sram[2]:16 0.0002092072 +17 mux_tree_tapbuf_size8_5_sram[2]:17 0.0001862845 +18 mux_tree_tapbuf_size8_5_sram[2]:7 mux_tree_tapbuf_size8_5_sram[3]:5 5.429327e-06 +19 mux_tree_tapbuf_size8_5_sram[2]:13 mux_tree_tapbuf_size8_5_sram[3]:7 4.518814e-05 +20 mux_tree_tapbuf_size8_5_sram[2]:12 mux_tree_tapbuf_size8_5_sram[3]:8 4.518814e-05 +21 mux_tree_tapbuf_size8_5_sram[2]:11 mux_tree_tapbuf_size8_5_sram[3]:6 2.439859e-06 +22 mux_tree_tapbuf_size8_5_sram[2]:11 mux_tree_tapbuf_size8_5_sram[3]:10 2.610827e-05 +23 mux_tree_tapbuf_size8_5_sram[2]:10 mux_tree_tapbuf_size8_5_sram[3]:5 2.439859e-06 +24 mux_tree_tapbuf_size8_5_sram[2]:10 mux_tree_tapbuf_size8_5_sram[3]:9 2.610827e-05 +25 mux_tree_tapbuf_size8_5_sram[2]:5 mux_tree_tapbuf_size8_5_sram[3]:3 3.44617e-05 +26 mux_tree_tapbuf_size8_5_sram[2]:6 mux_tree_tapbuf_size8_5_sram[3]:4 3.44617e-05 +27 mux_tree_tapbuf_size8_5_sram[2]:8 mux_tree_tapbuf_size8_5_sram[3]:6 5.429327e-06 +28 mux_tree_tapbuf_size8_5_sram[2]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.340191e-05 +29 mux_tree_tapbuf_size8_5_sram[2]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.340191e-05 +30 mux_tree_tapbuf_size8_5_sram[2]:11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.162555e-05 +31 mux_tree_tapbuf_size8_5_sram[2]:9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.389996e-07 +32 mux_tree_tapbuf_size8_5_sram[2]:10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.162555e-05 +33 mux_tree_tapbuf_size8_5_sram[2]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.389996e-07 +34 mux_tree_tapbuf_size8_5_sram[2]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.881477e-05 +35 mux_tree_tapbuf_size8_5_sram[2]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.881477e-05 +36 mux_tree_tapbuf_size8_5_sram[2]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.068874e-05 +37 mux_tree_tapbuf_size8_5_sram[2]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.068874e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_5_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_5_sram[2]:7 mux_bottom_ipin_11\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_5_sram[2]:7 mux_tree_tapbuf_size8_5_sram[2]:6 0.0001686047 +3 mux_tree_tapbuf_size8_5_sram[2]:16 mux_tree_tapbuf_size8_5_sram[2]:15 0.0045 +4 mux_tree_tapbuf_size8_5_sram[2]:16 mux_tree_tapbuf_size8_5_sram[2]:4 8.482143e-05 +5 mux_tree_tapbuf_size8_5_sram[2]:15 mux_tree_tapbuf_size8_5_sram[2]:14 0.002044643 +6 mux_tree_tapbuf_size8_5_sram[2]:13 mux_tree_tapbuf_size8_5_sram[2]:12 0.003205357 +7 mux_tree_tapbuf_size8_5_sram[2]:14 mux_tree_tapbuf_size8_5_sram[2]:13 0.0045 +8 mux_tree_tapbuf_size8_5_sram[2]:12 mux_tree_tapbuf_size8_5_sram[2]:11 0.0045 +9 mux_tree_tapbuf_size8_5_sram[2]:11 mux_tree_tapbuf_size8_5_sram[2]:10 0.004776786 +10 mux_tree_tapbuf_size8_5_sram[2]:9 mux_tree_tapbuf_size8_5_sram[2]:8 0.001102679 +11 mux_tree_tapbuf_size8_5_sram[2]:10 mux_tree_tapbuf_size8_5_sram[2]:9 0.0045 +12 mux_tree_tapbuf_size8_5_sram[2]:5 mux_bottom_ipin_11\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size8_5_sram[2]:4 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +14 mux_tree_tapbuf_size8_5_sram[2]:17 mux_tree_tapbuf_size8_5_sram[2]:16 0.002529018 +15 mux_tree_tapbuf_size8_5_sram[2]:6 mux_tree_tapbuf_size8_5_sram[2]:5 0.005433036 +16 mux_tree_tapbuf_size8_5_sram[2]:8 mux_tree_tapbuf_size8_5_sram[2]:7 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_7_ccff_tail[0] 0.0009532143 //LENGTH 7.345 LUMPCC 0.0001629493 DR + +*CONN +*I mem_bottom_ipin_15\/FTB_17__56:X O *L 0 *C 88.535 52.360 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 90.330 47.940 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 *C 90.293 47.940 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 *C 88.365 47.940 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 *C 88.320 47.985 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 *C 88.320 52.315 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:6 *C 88.320 52.360 +*N mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:7 *C 88.535 52.360 + +*CAP +0 mem_bottom_ipin_15\/FTB_17__56:X 1e-06 +1 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 0.00013555 +3 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 0.00013555 +4 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 0.0002055104 +5 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 0.0002055104 +6 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:6 5.420432e-05 +7 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:7 5.193994e-05 +8 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 prog_clk[0]:220 6.517977e-05 +9 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 prog_clk[0]:223 2.483304e-06 +10 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 prog_clk[0]:218 1.381156e-05 +11 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 prog_clk[0]:164 2.483304e-06 +12 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 prog_clk[0]:219 6.517977e-05 +13 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 prog_clk[0]:217 1.381156e-05 + +*RES +0 mem_bottom_ipin_15\/FTB_17__56:X mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:6 0.0001168478 +2 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 0.003866072 +4 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 0.001720982 +5 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001366791 //LENGTH 11.500 LUMPCC 0.0003701357 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l3_in_0_:X O *L 0 *C 53.535 63.580 +*I mux_bottom_ipin_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 46.365 66.980 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 46.403 66.980 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 47.335 66.980 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 47.380 66.935 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 47.380 63.625 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 47.425 63.580 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 53.498 63.580 + +*CAP +0 mux_bottom_ipin_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.443238e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.443238e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001780295 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001780295 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002648656 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002648656 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:7 1.555695e-06 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:12 1.185025e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_1_sram[2]:13 0.0001158412 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:8 1.555695e-06 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:11 1.185025e-05 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_1_sram[2]:14 0.0001158412 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_1_sram[3]:5 4.799956e-05 +15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_1_sram[3]:6 4.799956e-05 +16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[3]:8 7.821168e-06 +17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[3]:7 7.821168e-06 + +*RES +0 mux_bottom_ipin_1\/mux_l3_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_1\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0008325893 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002955357 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.005421875 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006186874 //LENGTH 4.385 LUMPCC 7.835138e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_3_:X O *L 0 *C 52.615 45.220 +*I mux_bottom_ipin_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 53.650 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 53.613 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 52.945 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 52.900 47.895 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 52.900 45.265 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 52.900 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 52.615 45.220 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.555195e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.555195e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001746305 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001746305 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.215804e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.581318e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[15]:18 3.917569e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[15]:20 3.917569e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_3_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005959822 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005574143 //LENGTH 42.340 LUMPCC 0.0007186993 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l4_in_0_:X O *L 0 *C 11.675 36.040 +*I mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.600 69.540 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.120 65.280 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 5.600 69.540 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 5.520 69.360 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 5.520 69.315 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 5.520 65.338 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 5.520 65.280 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 5.520 65.273 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 5.520 46.928 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 5.540 46.920 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 6.433 46.920 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 6.440 46.863 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 6.440 36.098 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 6.448 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 11.492 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 *C 11.500 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:17 *C 11.500 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:18 *C 11.675 36.040 + +*CAP +0 mux_bottom_ipin_8\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.918501e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.301821e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 5.580645e-05 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002246786 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002246786 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.918501e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001048827 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001048827 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001419173 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001419173 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0005549933 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0005549933 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0002721798 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0002721798 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 3.642322e-05 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:17 5.345049e-05 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:18 5.118351e-05 +19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 chanx_left_in[4] 0.0002900074 +20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 chanx_left_in[4]:38 0.0002900074 +21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 ropt_net_163:4 6.934226e-05 +22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 ropt_net_163:5 6.934226e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l4_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:18 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.347826e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00355134 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.69697e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00287405 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.000139825 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.009611608 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.00341 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.00341 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0007903833 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 0.0045 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:17 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001138891 //LENGTH 8.020 LUMPCC 0.0003958086 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_0_:X O *L 0 *C 76.995 53.040 +*I mux_bottom_ipin_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 77.645 58.140 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 77.645 58.140 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 77.740 58.095 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 77.740 53.425 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 77.785 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.375 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 78.375 53.040 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 77.032 53.040 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.231631e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001631219 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001631219 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.205628e-05 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.888556e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001192046 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.237537e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[3]:31 6.706829e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[3]:32 6.706829e-05 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_left_in[3]:34 5.067453e-06 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[3]:33 5.067453e-06 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[7]:13 0.0001257686 +14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[7]:14 0.0001257686 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004169643 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.001198661 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003035715 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005267857 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008973372 //LENGTH 6.340 LUMPCC 0.0002674767 DR + +*CONN +*I mux_top_ipin_0\/mux_l3_in_1_:X O *L 0 *C 87.225 15.640 +*I mux_top_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 87.555 10.200 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 87.555 10.200 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 87.400 10.200 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 87.400 10.245 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 87.400 15.595 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 87.400 15.640 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 87.225 15.640 + +*CAP +0 mux_top_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_top_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.920998e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.211401e-05 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002111602 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002111602 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.435736e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 4.985884e-05 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001337383 +9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001337383 + +*RES +0 mux_top_ipin_0\/mux_l3_in_1_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004776786 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 8.423914e-05 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_ipin_0\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001018513 //LENGTH 7.000 LUMPCC 0.0001227571 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l3_in_1_:X O *L 0 *C 44.905 45.560 +*I mux_bottom_ipin_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 43.070 49.640 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 43.070 49.640 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 43.240 49.640 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 43.240 49.595 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 43.240 47.645 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 43.285 47.600 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 44.575 47.600 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 44.620 47.555 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 44.620 45.605 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 44.620 45.560 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 44.905 45.560 + +*CAP +0 mux_bottom_ipin_3\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.016057e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.489643e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.746914e-05 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.746914e-05 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001066905 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001066905 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001368725 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001368725 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.380648e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.282809e-05 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_1_sram[2]:10 5.83148e-05 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_1_sram[2]:9 5.83148e-05 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_tree_tapbuf_size8_1_sram[2]:9 2.077121e-07 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_tree_tapbuf_size8_1_sram[2]:10 2.856042e-06 +16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_tree_tapbuf_size8_1_sram[2]:6 2.077121e-07 +17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_tree_tapbuf_size8_1_sram[2]:9 2.856042e-06 + +*RES +0 mux_bottom_ipin_3\/mux_l3_in_1_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_3\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001741071 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001151786 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001741072 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004413203 //LENGTH 2.910 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_1_:X O *L 0 *C 23.175 22.440 +*I mux_bottom_ipin_10\/mux_l3_in_0_:A0 I *L 0.001631 *C 22.370 21.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 22.370 21.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.540 21.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 22.540 21.125 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 22.540 22.395 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 22.585 22.440 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 23.138 22.440 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.492118e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.60984e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.581084e-05 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.581084e-05 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.83395e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.83395e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_1_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.239132e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004869687 //LENGTH 2.590 LUMPCC 0.0003717053 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_1_:X O *L 0 *C 79.755 22.780 +*I mux_bottom_ipin_14\/mux_l3_in_0_:A0 I *L 0.001631 *C 77.455 22.780 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 77.493 22.780 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 79.718 22.780 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.663172e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.663172e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[2]:44 9.292632e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[2]:43 9.292632e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size8_6_sram[1]:20 9.292632e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size8_6_sram[1]:19 9.292632e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_1_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001986607 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00103271 //LENGTH 7.680 LUMPCC 0.0001839667 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l3_in_1_:X O *L 0 *C 90.335 61.540 +*I mux_bottom_ipin_15\/mux_l4_in_0_:A0 I *L 0.001631 *C 86.305 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 86.343 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 89.195 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 89.240 64.215 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 89.240 61.585 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 89.285 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 90.297 61.540 + +*CAP +0 mux_bottom_ipin_15\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001700244 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001700244 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001843865 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001843865 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.896064e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.896064e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[7]:5 4.423842e-05 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[7]:6 4.423842e-05 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 ropt_net_118:6 4.774492e-05 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 ropt_net_118:7 4.774492e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l3_in_1_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009040179 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002546875 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_15\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET chanx_right_out[11] 0.0006555014 //LENGTH 4.370 LUMPCC 0.0001237371 DR + +*CONN +*I ropt_mt_inst_717:X O *L 0 *C 101.855 67.320 +*P chanx_right_out[11] O *L 0.7423 *C 103.650 69.360 +*N chanx_right_out[11]:2 *C 102.128 69.360 +*N chanx_right_out[11]:3 *C 102.120 69.303 +*N chanx_right_out[11]:4 *C 102.120 67.365 +*N chanx_right_out[11]:5 *C 102.120 67.320 +*N chanx_right_out[11]:6 *C 101.855 67.320 + +*CAP +0 ropt_mt_inst_717:X 1e-06 +1 chanx_right_out[11] 0.000118909 +2 chanx_right_out[11]:2 0.000118909 +3 chanx_right_out[11]:3 8.661131e-05 +4 chanx_right_out[11]:4 8.661131e-05 +5 chanx_right_out[11]:5 5.495898e-05 +6 chanx_right_out[11]:6 6.476454e-05 +7 chanx_right_out[11]:4 ropt_net_159:7 6.186857e-05 +8 chanx_right_out[11]:3 ropt_net_159:6 6.186857e-05 + +*RES +0 ropt_mt_inst_717:X chanx_right_out[11]:6 0.152 +1 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0001440218 +2 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +3 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001729911 +4 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +5 chanx_right_out[11]:2 chanx_right_out[11] 0.000238525 + +*END + +*D_NET chanx_left_out[6] 0.0009047487 //LENGTH 6.800 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 4.140 34.340 +*P chanx_left_out[6] O *L 0.7423 *C 1.298 31.280 +*N chanx_left_out[6]:2 *C 1.380 31.280 +*N chanx_left_out[6]:3 *C 1.380 31.338 +*N chanx_left_out[6]:4 *C 1.380 34.295 +*N chanx_left_out[6]:5 *C 1.425 34.340 +*N chanx_left_out[6]:6 *C 4.103 34.340 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 chanx_left_out[6] 4.130047e-05 +2 chanx_left_out[6]:2 4.130047e-05 +3 chanx_left_out[6]:3 0.0002154501 +4 chanx_left_out[6]:4 0.0002154501 +5 chanx_left_out[6]:5 0.0001951238 +6 chanx_left_out[6]:6 0.0001951238 + +*RES +0 ropt_mt_inst_750:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +2 chanx_left_out[6]:2 chanx_left_out[6] 2.35e-05 +3 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +4 chanx_left_out[6]:4 chanx_left_out[6]:3 0.002640625 +5 chanx_left_out[6]:6 chanx_left_out[6]:5 0.002390625 + +*END + +*D_NET chanx_right_out[7] 0.001610362 //LENGTH 13.630 LUMPCC 0.0001729378 DR + +*CONN +*I ropt_mt_inst_725:X O *L 0 *C 97.220 64.260 +*P chanx_right_out[7] O *L 0.7423 *C 103.575 70.720 +*N chanx_right_out[7]:2 *C 98.907 70.720 +*N chanx_right_out[7]:3 *C 98.900 70.663 +*N chanx_right_out[7]:4 *C 98.900 64.305 +*N chanx_right_out[7]:5 *C 98.855 64.260 +*N chanx_right_out[7]:6 *C 97.258 64.260 + +*CAP +0 ropt_mt_inst_725:X 1e-06 +1 chanx_right_out[7] 0.0003222321 +2 chanx_right_out[7]:2 0.0003222321 +3 chanx_right_out[7]:3 0.0002745144 +4 chanx_right_out[7]:4 0.0002745144 +5 chanx_right_out[7]:5 0.0001214656 +6 chanx_right_out[7]:6 0.0001214656 +7 chanx_right_out[7]:3 BUF_net_58:4 8.646892e-05 +8 chanx_right_out[7]:4 BUF_net_58:3 8.646892e-05 + +*RES +0 ropt_mt_inst_725:X chanx_right_out[7]:6 0.152 +1 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +2 chanx_right_out[7]:2 chanx_right_out[7] 0.0007312417 +3 chanx_right_out[7]:5 chanx_right_out[7]:4 0.0045 +4 chanx_right_out[7]:4 chanx_right_out[7]:3 0.005676339 +5 chanx_right_out[7]:6 chanx_right_out[7]:5 0.001426339 + +*END + +*D_NET ropt_net_165 0.0001844806 //LENGTH 0.870 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_729:X O *L 0 *C 11.780 23.120 +*I ropt_mt_inst_771:A I *L 0.001767 *C 12.420 23.120 +*N ropt_net_165:2 *C 12.420 23.120 +*N ropt_net_165:3 *C 11.780 23.120 + +*CAP +0 ropt_mt_inst_729:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_165:2 9.124032e-05 +3 ropt_net_165:3 9.124032e-05 + +*RES +0 ropt_mt_inst_729:X ropt_net_165:3 0.152 +1 ropt_net_165:2 ropt_mt_inst_771:A 0.152 +2 ropt_net_165:3 ropt_net_165:2 0.0005714286 + +*END + +*D_NET ropt_net_134 0.001772114 //LENGTH 13.525 LUMPCC 0.0006362238 DR + +*CONN +*I BUFT_P_88:X O *L 0 *C 3.680 25.840 +*I ropt_mt_inst_733:A I *L 0.001766 *C 3.220 36.720 +*N ropt_net_134:2 *C 3.220 36.720 +*N ropt_net_134:3 *C 3.220 36.675 +*N ropt_net_134:4 *C 3.220 29.285 +*N ropt_net_134:5 *C 3.265 29.240 +*N ropt_net_134:6 *C 4.095 29.240 +*N ropt_net_134:7 *C 4.140 29.195 +*N ropt_net_134:8 *C 4.140 25.885 +*N ropt_net_134:9 *C 4.095 25.840 +*N ropt_net_134:10 *C 3.718 25.840 + +*CAP +0 BUFT_P_88:X 1e-06 +1 ropt_mt_inst_733:A 1e-06 +2 ropt_net_134:2 3.299777e-05 +3 ropt_net_134:3 0.0003122066 +4 ropt_net_134:4 0.0003122066 +5 ropt_net_134:5 4.277626e-05 +6 ropt_net_134:6 4.277626e-05 +7 ropt_net_134:7 0.0001556245 +8 ropt_net_134:8 0.0001556245 +9 ropt_net_134:9 3.983911e-05 +10 ropt_net_134:10 3.983911e-05 +11 ropt_net_134:8 chanx_left_in[12]:28 7.228764e-07 +12 ropt_net_134:6 chanx_left_in[12]:26 4.584894e-05 +13 ropt_net_134:7 chanx_left_in[12]:29 7.228764e-07 +14 ropt_net_134:5 chanx_left_in[12]:27 4.584894e-05 +15 ropt_net_134:4 chanx_left_in[12]:28 0.000205279 +16 ropt_net_134:3 chanx_left_in[12]:29 0.000205279 +17 ropt_net_134:8 ropt_net_136:4 4.991223e-06 +18 ropt_net_134:8 ropt_net_136:6 5.70573e-05 +19 ropt_net_134:8 ropt_net_136:8 4.212555e-06 +20 ropt_net_134:7 ropt_net_136:3 4.991223e-06 +21 ropt_net_134:7 ropt_net_136:5 5.70573e-05 +22 ropt_net_134:7 ropt_net_136:7 4.212555e-06 + +*RES +0 BUFT_P_88:X ropt_net_134:10 0.152 +1 ropt_net_134:10 ropt_net_134:9 0.0003370536 +2 ropt_net_134:9 ropt_net_134:8 0.0045 +3 ropt_net_134:8 ropt_net_134:7 0.002955357 +4 ropt_net_134:6 ropt_net_134:5 0.0007410714 +5 ropt_net_134:7 ropt_net_134:6 0.0045 +6 ropt_net_134:5 ropt_net_134:4 0.0045 +7 ropt_net_134:4 ropt_net_134:3 0.006598215 +8 ropt_net_134:2 ropt_mt_inst_733:A 0.152 +9 ropt_net_134:3 ropt_net_134:2 0.0045 + +*END + +*D_NET chanx_left_in[3] 0.02117319 //LENGTH 149.967 LUMPCC 0.005304021 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 68.000 +*I mux_bottom_ipin_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 33.870 55.080 +*I mux_bottom_ipin_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 41.115 58.820 +*I mux_bottom_ipin_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 60.720 52.700 +*I mux_bottom_ipin_13\/mux_l1_in_1_:A1 I *L 0.00198 *C 81.785 58.140 +*I mux_bottom_ipin_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.770 55.080 +*I FTB_4__3:A I *L 0.001767 *C 93.380 53.040 +*I mux_bottom_ipin_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 69.460 52.700 +*I mux_bottom_ipin_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 25.015 53.380 +*I mux_bottom_ipin_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 18.765 52.700 +*N chanx_left_in[3]:10 *C 18.765 52.700 +*N chanx_left_in[3]:11 *C 25.015 53.380 +*N chanx_left_in[3]:12 *C 69.498 52.700 +*N chanx_left_in[3]:13 *C 69.920 52.700 +*N chanx_left_in[3]:14 *C 93.343 53.040 +*N chanx_left_in[3]:15 *C 92.505 53.040 +*N chanx_left_in[3]:16 *C 92.460 53.085 +*N chanx_left_in[3]:17 *C 92.460 55.035 +*N chanx_left_in[3]:18 *C 92.415 55.080 +*N chanx_left_in[3]:19 *C 86.808 55.080 +*N chanx_left_in[3]:20 *C 86.480 55.080 +*N chanx_left_in[3]:21 *C 86.480 55.125 +*N chanx_left_in[3]:22 *C 86.480 56.395 +*N chanx_left_in[3]:23 *C 86.435 56.440 +*N chanx_left_in[3]:24 *C 81.823 58.140 +*N chanx_left_in[3]:25 *C 82.755 58.140 +*N chanx_left_in[3]:26 *C 82.800 58.095 +*N chanx_left_in[3]:27 *C 82.800 56.485 +*N chanx_left_in[3]:28 *C 82.800 56.440 +*N chanx_left_in[3]:29 *C 82.800 55.760 +*N chanx_left_in[3]:30 *C 77.325 55.760 +*N chanx_left_in[3]:31 *C 77.280 55.715 +*N chanx_left_in[3]:32 *C 77.280 52.405 +*N chanx_left_in[3]:33 *C 77.235 52.360 +*N chanx_left_in[3]:34 *C 69.920 52.360 +*N chanx_left_in[3]:35 *C 69.920 52.315 +*N chanx_left_in[3]:36 *C 69.920 51.058 +*N chanx_left_in[3]:37 *C 69.913 51.000 +*N chanx_left_in[3]:38 *C 60.683 52.700 +*N chanx_left_in[3]:39 *C 59.385 52.700 +*N chanx_left_in[3]:40 *C 59.340 52.655 +*N chanx_left_in[3]:41 *C 59.340 51.058 +*N chanx_left_in[3]:42 *C 59.340 51.000 +*N chanx_left_in[3]:43 *C 41.407 51.000 +*N chanx_left_in[3]:44 *C 41.400 51.058 +*N chanx_left_in[3]:45 *C 41.400 58.775 +*N chanx_left_in[3]:46 *C 41.400 58.820 +*N chanx_left_in[3]:47 *C 41.078 58.820 +*N chanx_left_in[3]:48 *C 36.385 58.820 +*N chanx_left_in[3]:49 *C 36.340 58.775 +*N chanx_left_in[3]:50 *C 36.340 55.125 +*N chanx_left_in[3]:51 *C 36.295 55.080 +*N chanx_left_in[3]:52 *C 33.870 55.080 +*N chanx_left_in[3]:53 *C 34.085 55.080 +*N chanx_left_in[3]:54 *C 34.040 55.035 +*N chanx_left_in[3]:55 *C 34.040 51.045 +*N chanx_left_in[3]:56 *C 33.995 51.000 +*N chanx_left_in[3]:57 *C 25.345 51.000 +*N chanx_left_in[3]:58 *C 25.300 51.045 +*N chanx_left_in[3]:59 *C 25.300 52.995 +*N chanx_left_in[3]:60 *C 25.255 53.047 +*N chanx_left_in[3]:61 *C 18.860 53.040 +*N chanx_left_in[3]:62 *C 13.385 53.040 +*N chanx_left_in[3]:63 *C 13.340 53.085 +*N chanx_left_in[3]:64 *C 13.340 55.375 +*N chanx_left_in[3]:65 *C 13.295 55.420 +*N chanx_left_in[3]:66 *C 4.645 55.420 +*N chanx_left_in[3]:67 *C 4.600 55.465 +*N chanx_left_in[3]:68 *C 4.600 67.943 +*N chanx_left_in[3]:69 *C 4.593 68.000 + +*CAP +0 chanx_left_in[3] 0.0002153698 +1 mux_bottom_ipin_7\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_ipin_5\/mux_l1_in_1_:A1 1e-06 +4 mux_bottom_ipin_13\/mux_l1_in_1_:A1 1e-06 +5 mux_bottom_ipin_15\/mux_l2_in_0_:A0 1e-06 +6 FTB_4__3:A 1e-06 +7 mux_bottom_ipin_1\/mux_l1_in_1_:A1 1e-06 +8 mux_bottom_ipin_11\/mux_l2_in_0_:A0 1e-06 +9 mux_bottom_ipin_9\/mux_l1_in_1_:A1 1e-06 +10 chanx_left_in[3]:10 5.065451e-05 +11 chanx_left_in[3]:11 5.267471e-05 +12 chanx_left_in[3]:12 4.816653e-05 +13 chanx_left_in[3]:13 7.585028e-05 +14 chanx_left_in[3]:14 6.36984e-05 +15 chanx_left_in[3]:15 6.36984e-05 +16 chanx_left_in[3]:16 8.666694e-05 +17 chanx_left_in[3]:17 8.666694e-05 +18 chanx_left_in[3]:18 0.0004700179 +19 chanx_left_in[3]:19 0.0004987216 +20 chanx_left_in[3]:20 6.227597e-05 +21 chanx_left_in[3]:21 9.730953e-05 +22 chanx_left_in[3]:22 9.730953e-05 +23 chanx_left_in[3]:23 0.0002201046 +24 chanx_left_in[3]:24 9.597802e-05 +25 chanx_left_in[3]:25 9.597802e-05 +26 chanx_left_in[3]:26 0.0001155273 +27 chanx_left_in[3]:27 0.0001155273 +28 chanx_left_in[3]:28 0.0002724692 +29 chanx_left_in[3]:29 0.0003851646 +30 chanx_left_in[3]:30 0.0003328 +31 chanx_left_in[3]:31 0.0001589335 +32 chanx_left_in[3]:32 0.0001589335 +33 chanx_left_in[3]:33 0.000439298 +34 chanx_left_in[3]:34 0.0004669818 +35 chanx_left_in[3]:35 9.167289e-05 +36 chanx_left_in[3]:36 9.167289e-05 +37 chanx_left_in[3]:37 0.0004240564 +38 chanx_left_in[3]:38 0.0001401896 +39 chanx_left_in[3]:39 0.0001401896 +40 chanx_left_in[3]:40 0.0001151796 +41 chanx_left_in[3]:41 0.0001151796 +42 chanx_left_in[3]:42 0.001098679 +43 chanx_left_in[3]:43 0.0006746227 +44 chanx_left_in[3]:44 0.0003549097 +45 chanx_left_in[3]:45 0.0003549097 +46 chanx_left_in[3]:46 5.740928e-05 +47 chanx_left_in[3]:47 0.000359189 +48 chanx_left_in[3]:48 0.000333146 +49 chanx_left_in[3]:49 0.0001529023 +50 chanx_left_in[3]:50 0.0001529023 +51 chanx_left_in[3]:51 0.0001944287 +52 chanx_left_in[3]:52 5.682147e-05 +53 chanx_left_in[3]:53 0.0002220976 +54 chanx_left_in[3]:54 0.0002123451 +55 chanx_left_in[3]:55 0.0002123451 +56 chanx_left_in[3]:56 0.0004468632 +57 chanx_left_in[3]:57 0.0004468632 +58 chanx_left_in[3]:58 9.305398e-05 +59 chanx_left_in[3]:59 9.305398e-05 +60 chanx_left_in[3]:60 0.0003694341 +61 chanx_left_in[3]:61 0.0006209916 +62 chanx_left_in[3]:62 0.0002532464 +63 chanx_left_in[3]:63 0.0001542757 +64 chanx_left_in[3]:64 0.0001542757 +65 chanx_left_in[3]:65 0.0006535272 +66 chanx_left_in[3]:66 0.0006535272 +67 chanx_left_in[3]:67 0.0006620276 +68 chanx_left_in[3]:68 0.0006620276 +69 chanx_left_in[3]:69 0.0002153698 +70 chanx_left_in[3] chanx_left_in[1] 4.849479e-05 +71 chanx_left_in[3]:17 chanx_left_in[1]:15 5.63904e-06 +72 chanx_left_in[3]:17 chanx_left_in[1]:17 2.376353e-05 +73 chanx_left_in[3]:15 chanx_left_in[1]:20 2.837535e-05 +74 chanx_left_in[3]:16 chanx_left_in[1]:16 5.63904e-06 +75 chanx_left_in[3]:16 chanx_left_in[1]:18 2.376353e-05 +76 chanx_left_in[3]:14 chanx_left_in[1]:19 2.837535e-05 +77 chanx_left_in[3]:45 chanx_left_in[1]:39 6.798783e-05 +78 chanx_left_in[3]:44 chanx_left_in[1]:40 6.798783e-05 +79 chanx_left_in[3]:33 chanx_left_in[1]:27 3.658547e-05 +80 chanx_left_in[3]:54 chanx_left_in[1]:48 1.018519e-05 +81 chanx_left_in[3]:55 chanx_left_in[1]:49 1.018519e-05 +82 chanx_left_in[3]:34 chanx_left_in[1]:30 3.658547e-05 +83 chanx_left_in[3]:12 chanx_left_in[1]:30 3.880444e-06 +84 chanx_left_in[3]:65 chanx_left_in[1]:55 8.794351e-06 +85 chanx_left_in[3]:66 chanx_left_in[1]:56 8.794351e-06 +86 chanx_left_in[3]:67 chanx_left_in[1]:57 4.263617e-05 +87 chanx_left_in[3]:68 chanx_left_in[1]:58 4.263617e-05 +88 chanx_left_in[3]:69 chanx_left_in[1]:59 4.849479e-05 +89 chanx_left_in[3]:13 chanx_left_in[1]:27 3.880444e-06 +90 chanx_left_in[3]:43 chanx_left_in[7]:21 0.0002407628 +91 chanx_left_in[3]:33 chanx_left_in[7]:20 7.061751e-06 +92 chanx_left_in[3]:33 chanx_left_in[7]:17 7.414303e-06 +93 chanx_left_in[3]:32 chanx_left_in[7]:14 1.401757e-05 +94 chanx_left_in[3]:32 chanx_left_in[7]:18 3.134484e-06 +95 chanx_left_in[3]:31 chanx_left_in[7]:13 1.401757e-05 +96 chanx_left_in[3]:31 chanx_left_in[7]:19 3.134484e-06 +97 chanx_left_in[3]:34 chanx_left_in[7]:21 7.061751e-06 +98 chanx_left_in[3]:34 chanx_left_in[7]:18 7.414303e-06 +99 chanx_left_in[3]:37 chanx_left_in[7]:20 0.0002160493 +100 chanx_left_in[3]:42 chanx_left_in[7]:21 0.0002160493 +101 chanx_left_in[3]:42 chanx_left_in[7]:20 0.0002407628 +102 chanx_left_in[3]:62 chanx_left_in[7]:35 6.216478e-06 +103 chanx_left_in[3]:61 chanx_left_in[7]:34 6.216478e-06 +104 chanx_left_in[3]:43 chanx_left_in[9]:23 0.0002853394 +105 chanx_left_in[3]:37 chanx_left_in[9]:4 1.494404e-05 +106 chanx_left_in[3]:42 chanx_left_in[9]:16 1.494404e-05 +107 chanx_left_in[3]:42 chanx_left_in[9]:22 0.0002853394 +108 chanx_left_in[3]:17 chanx_left_in[19]:27 2.660659e-05 +109 chanx_left_in[3]:16 chanx_left_in[19]:28 2.660659e-05 +110 chanx_left_in[3]:43 chanx_left_in[19]:31 5.45343e-06 +111 chanx_left_in[3]:60 chanx_left_in[19]:34 5.648396e-05 +112 chanx_left_in[3]:37 chanx_left_in[19]:30 4.528887e-05 +113 chanx_left_in[3]:42 chanx_left_in[19]:31 4.528887e-05 +114 chanx_left_in[3]:42 chanx_left_in[19]:30 5.45343e-06 +115 chanx_left_in[3]:62 chanx_left_in[19]:35 6.656878e-05 +116 chanx_left_in[3]:63 chanx_left_in[19]:7 1.612231e-05 +117 chanx_left_in[3]:65 chanx_left_in[19]:6 6.879597e-05 +118 chanx_left_in[3]:64 chanx_left_in[19]:8 1.612231e-05 +119 chanx_left_in[3]:66 chanx_left_in[19]:5 6.879597e-05 +120 chanx_left_in[3]:61 chanx_left_in[19]:34 6.656878e-05 +121 chanx_left_in[3]:61 chanx_left_in[19]:35 5.648396e-05 +122 chanx_left_in[3]:43 chanx_right_in[1]:37 5.11299e-05 +123 chanx_left_in[3]:54 chanx_right_in[1]:36 3.310716e-06 +124 chanx_left_in[3]:56 chanx_right_in[1]:31 0.000305769 +125 chanx_left_in[3]:55 chanx_right_in[1]:32 3.310716e-06 +126 chanx_left_in[3]:57 chanx_right_in[1]:30 0.000305769 +127 chanx_left_in[3]:42 chanx_right_in[1]:38 5.11299e-05 +128 chanx_left_in[3]:43 prog_clk[0]:315 5.941498e-05 +129 chanx_left_in[3]:43 prog_clk[0]:370 0.0001349838 +130 chanx_left_in[3]:37 prog_clk[0]:169 0.0001938038 +131 chanx_left_in[3]:42 prog_clk[0]:371 0.0001349838 +132 chanx_left_in[3]:42 prog_clk[0]:168 0.0001938038 +133 chanx_left_in[3]:42 prog_clk[0]:370 5.941498e-05 +134 chanx_left_in[3]:10 prog_clk[0]:283 5.595608e-06 +135 chanx_left_in[3]:61 prog_clk[0]:286 5.595608e-06 +136 chanx_left_in[3]:62 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.533821e-05 +137 chanx_left_in[3]:61 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.533821e-05 +138 chanx_left_in[3]:33 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.067453e-06 +139 chanx_left_in[3]:32 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.706829e-05 +140 chanx_left_in[3]:31 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.706829e-05 +141 chanx_left_in[3]:34 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.067453e-06 +142 chanx_left_in[3]:45 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.448858e-05 +143 chanx_left_in[3]:44 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.448858e-05 +144 chanx_left_in[3]:49 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001039751 +145 chanx_left_in[3]:50 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001039751 +146 chanx_left_in[3]:54 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.317282e-06 +147 chanx_left_in[3]:55 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.317282e-06 +148 chanx_left_in[3]:51 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.409175e-07 +149 chanx_left_in[3]:53 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.213645e-07 +150 chanx_left_in[3]:53 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.409175e-07 +151 chanx_left_in[3]:54 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.911822e-05 +152 chanx_left_in[3]:55 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.911822e-05 +153 chanx_left_in[3]:52 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.213645e-07 +154 chanx_left_in[3]:60 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.135031e-05 +155 chanx_left_in[3]:61 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.135031e-05 +156 chanx_left_in[3]:58 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.988176e-05 +157 chanx_left_in[3]:59 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.988176e-05 +158 chanx_left_in[3]:28 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.51238e-05 +159 chanx_left_in[3]:27 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.109224e-06 +160 chanx_left_in[3]:26 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.109224e-06 +161 chanx_left_in[3]:23 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.51238e-05 +162 chanx_left_in[3]:22 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.640045e-05 +163 chanx_left_in[3]:21 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.640045e-05 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:69 0.0005267916 +1 chanx_left_in[3]:18 chanx_left_in[3]:17 0.0045 +2 chanx_left_in[3]:17 chanx_left_in[3]:16 0.001741071 +3 chanx_left_in[3]:15 chanx_left_in[3]:14 0.0007477679 +4 chanx_left_in[3]:16 chanx_left_in[3]:15 0.0045 +5 chanx_left_in[3]:14 FTB_4__3:A 0.152 +6 chanx_left_in[3]:48 chanx_left_in[3]:47 0.004189732 +7 chanx_left_in[3]:49 chanx_left_in[3]:48 0.0045 +8 chanx_left_in[3]:51 chanx_left_in[3]:50 0.0045 +9 chanx_left_in[3]:50 chanx_left_in[3]:49 0.003258929 +10 chanx_left_in[3]:46 chanx_left_in[3]:45 0.0045 +11 chanx_left_in[3]:45 chanx_left_in[3]:44 0.006890625 +12 chanx_left_in[3]:44 chanx_left_in[3]:43 0.00341 +13 chanx_left_in[3]:43 chanx_left_in[3]:42 0.002809425 +14 chanx_left_in[3]:33 chanx_left_in[3]:32 0.0045 +15 chanx_left_in[3]:32 chanx_left_in[3]:31 0.002955357 +16 chanx_left_in[3]:30 chanx_left_in[3]:29 0.004888393 +17 chanx_left_in[3]:31 chanx_left_in[3]:30 0.0045 +18 chanx_left_in[3]:53 chanx_left_in[3]:52 0.0001168478 +19 chanx_left_in[3]:53 chanx_left_in[3]:51 0.001973214 +20 chanx_left_in[3]:54 chanx_left_in[3]:53 0.0045 +21 chanx_left_in[3]:56 chanx_left_in[3]:55 0.0045 +22 chanx_left_in[3]:55 chanx_left_in[3]:54 0.0035625 +23 chanx_left_in[3]:57 chanx_left_in[3]:56 0.007723215 +24 chanx_left_in[3]:58 chanx_left_in[3]:57 0.0045 +25 chanx_left_in[3]:60 chanx_left_in[3]:59 0.0045 +26 chanx_left_in[3]:60 chanx_left_in[3]:11 0.0001807065 +27 chanx_left_in[3]:59 chanx_left_in[3]:58 0.001741072 +28 chanx_left_in[3]:34 chanx_left_in[3]:33 0.00653125 +29 chanx_left_in[3]:34 chanx_left_in[3]:13 0.0003035715 +30 chanx_left_in[3]:35 chanx_left_in[3]:34 0.0045 +31 chanx_left_in[3]:36 chanx_left_in[3]:35 0.001122768 +32 chanx_left_in[3]:37 chanx_left_in[3]:36 0.00341 +33 chanx_left_in[3]:52 mux_bottom_ipin_7\/mux_l2_in_0_:A0 0.152 +34 chanx_left_in[3]:41 chanx_left_in[3]:40 0.001426339 +35 chanx_left_in[3]:42 chanx_left_in[3]:41 0.00341 +36 chanx_left_in[3]:42 chanx_left_in[3]:37 0.001656358 +37 chanx_left_in[3]:39 chanx_left_in[3]:38 0.001158482 +38 chanx_left_in[3]:40 chanx_left_in[3]:39 0.0045 +39 chanx_left_in[3]:38 mux_bottom_ipin_5\/mux_l1_in_1_:A1 0.152 +40 chanx_left_in[3]:28 chanx_left_in[3]:27 0.0045 +41 chanx_left_in[3]:28 chanx_left_in[3]:23 0.003245536 +42 chanx_left_in[3]:27 chanx_left_in[3]:26 0.0014375 +43 chanx_left_in[3]:25 chanx_left_in[3]:24 0.0008325893 +44 chanx_left_in[3]:26 chanx_left_in[3]:25 0.0045 +45 chanx_left_in[3]:24 mux_bottom_ipin_13\/mux_l1_in_1_:A1 0.152 +46 chanx_left_in[3]:19 mux_bottom_ipin_15\/mux_l2_in_0_:A0 0.152 +47 chanx_left_in[3]:19 chanx_left_in[3]:18 0.005006697 +48 chanx_left_in[3]:23 chanx_left_in[3]:22 0.0045 +49 chanx_left_in[3]:22 chanx_left_in[3]:21 0.001133929 +50 chanx_left_in[3]:20 chanx_left_in[3]:19 0.0001779891 +51 chanx_left_in[3]:21 chanx_left_in[3]:20 0.0045 +52 chanx_left_in[3]:47 mux_bottom_ipin_3\/mux_l2_in_0_:A0 0.152 +53 chanx_left_in[3]:47 chanx_left_in[3]:46 0.0001752718 +54 chanx_left_in[3]:12 mux_bottom_ipin_1\/mux_l1_in_1_:A1 0.152 +55 chanx_left_in[3]:10 mux_bottom_ipin_9\/mux_l1_in_1_:A1 0.152 +56 chanx_left_in[3]:11 mux_bottom_ipin_11\/mux_l2_in_0_:A0 0.152 +57 chanx_left_in[3]:62 chanx_left_in[3]:61 0.004888394 +58 chanx_left_in[3]:63 chanx_left_in[3]:62 0.0045 +59 chanx_left_in[3]:65 chanx_left_in[3]:64 0.0045 +60 chanx_left_in[3]:64 chanx_left_in[3]:63 0.002044643 +61 chanx_left_in[3]:66 chanx_left_in[3]:65 0.007723216 +62 chanx_left_in[3]:67 chanx_left_in[3]:66 0.0045 +63 chanx_left_in[3]:68 chanx_left_in[3]:67 0.01114062 +64 chanx_left_in[3]:69 chanx_left_in[3]:68 0.00341 +65 chanx_left_in[3]:61 chanx_left_in[3]:60 0.005709821 +66 chanx_left_in[3]:61 chanx_left_in[3]:10 0.0003035715 +67 chanx_left_in[3]:13 chanx_left_in[3]:12 0.0003772322 +68 chanx_left_in[3]:29 chanx_left_in[3]:28 0.0006071429 + +*END + +*D_NET chanx_right_in[5] 0.01946195 //LENGTH 143.240 LUMPCC 0.004451491 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 103.650 61.200 +*I mux_bottom_ipin_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 62.390 58.820 +*I mux_bottom_ipin_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 62.390 48.280 +*I BUFT_P_92:A I *L 0.001766 *C 17.940 6.800 +*N chanx_right_in[5]:4 *C 50.653 9.520 +*N chanx_right_in[5]:5 *C 17.977 6.800 +*N chanx_right_in[5]:6 *C 48.255 6.800 +*N chanx_right_in[5]:7 *C 48.300 6.845 +*N chanx_right_in[5]:8 *C 48.300 9.490 +*N chanx_right_in[5]:9 *C 48.345 9.520 +*N chanx_right_in[5]:10 *C 50.698 9.527 +*N chanx_right_in[5]:11 *C 50.600 9.520 +*N chanx_right_in[5]:12 *C 50.608 9.520 +*N chanx_right_in[5]:13 *C 61.620 9.520 +*N chanx_right_in[5]:14 *C 61.640 9.527 +*N chanx_right_in[5]:15 *C 61.640 46.913 +*N chanx_right_in[5]:16 *C 61.655 46.920 +*N chanx_right_in[5]:17 *C 62.098 46.920 +*N chanx_right_in[5]:18 *C 62.100 46.977 +*N chanx_right_in[5]:19 *C 62.390 48.280 +*N chanx_right_in[5]:20 *C 62.100 48.280 +*N chanx_right_in[5]:21 *C 62.100 48.280 +*N chanx_right_in[5]:22 *C 62.390 58.820 +*N chanx_right_in[5]:23 *C 62.100 58.820 +*N chanx_right_in[5]:24 *C 62.100 58.820 +*N chanx_right_in[5]:25 *C 62.100 61.143 +*N chanx_right_in[5]:26 *C 62.108 61.200 + +*CAP +0 chanx_right_in[5] 0.001740775 +1 mux_bottom_ipin_1\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_ipin_5\/mux_l1_in_2_:A0 1e-06 +3 BUFT_P_92:A 1e-06 +4 chanx_right_in[5]:4 1.745981e-05 +5 chanx_right_in[5]:5 0.00148867 +6 chanx_right_in[5]:6 0.00148867 +7 chanx_right_in[5]:7 0.0001483122 +8 chanx_right_in[5]:8 0.0001483122 +9 chanx_right_in[5]:9 0.0001238216 +10 chanx_right_in[5]:10 0.0001412814 +11 chanx_right_in[5]:11 3.593315e-05 +12 chanx_right_in[5]:12 0.0003800436 +13 chanx_right_in[5]:13 0.0003800436 +14 chanx_right_in[5]:14 0.002513537 +15 chanx_right_in[5]:15 0.002513537 +16 chanx_right_in[5]:16 6.05142e-05 +17 chanx_right_in[5]:17 6.05142e-05 +18 chanx_right_in[5]:18 0.0001018147 +19 chanx_right_in[5]:19 5.035563e-05 +20 chanx_right_in[5]:20 5.50507e-05 +21 chanx_right_in[5]:21 0.0007681358 +22 chanx_right_in[5]:22 5.324052e-05 +23 chanx_right_in[5]:23 5.5028e-05 +24 chanx_right_in[5]:24 0.0008028153 +25 chanx_right_in[5]:25 0.000138816 +26 chanx_right_in[5]:26 0.001740775 +27 chanx_right_in[5]:12 chanx_left_in[14]:16 0.0006398661 +28 chanx_right_in[5]:13 chanx_left_in[14]:15 0.0006398661 +29 chanx_right_in[5] chanx_right_in[17]:22 0.0005887047 +30 chanx_right_in[5] chanx_right_in[17]:21 0.0005179264 +31 chanx_right_in[5]:26 chanx_right_in[17]:16 0.0005179264 +32 chanx_right_in[5]:26 chanx_right_in[17]:21 0.0005887047 +33 chanx_right_in[5] chanx_right_in[19] 6.527948e-05 +34 chanx_right_in[5] chanx_right_in[19]:22 0.0002020139 +35 chanx_right_in[5] chanx_right_in[19]:21 0.0002119552 +36 chanx_right_in[5]:26 chanx_right_in[19]:20 0.0002119552 +37 chanx_right_in[5]:26 chanx_right_in[19]:28 6.527948e-05 +38 chanx_right_in[5]:26 chanx_right_in[19]:21 0.0002020139 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:26 0.006508325 +1 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0045 +2 chanx_right_in[5]:8 chanx_right_in[5]:7 0.002361607 +3 chanx_right_in[5]:6 chanx_right_in[5]:5 0.02703349 +4 chanx_right_in[5]:7 chanx_right_in[5]:6 0.0045 +5 chanx_right_in[5]:5 BUFT_P_92:A 0.152 +6 chanx_right_in[5]:10 chanx_right_in[5]:9 0.002100446 +7 chanx_right_in[5]:10 chanx_right_in[5]:4 4.017857e-05 +8 chanx_right_in[5]:11 chanx_right_in[5]:10 0.0045 +9 chanx_right_in[5]:12 chanx_right_in[5]:11 0.00341 +10 chanx_right_in[5]:13 chanx_right_in[5]:12 0.001725292 +11 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00341 +12 chanx_right_in[5]:16 chanx_right_in[5]:15 0.00341 +13 chanx_right_in[5]:15 chanx_right_in[5]:14 0.005856983 +14 chanx_right_in[5]:18 chanx_right_in[5]:17 0.00341 +15 chanx_right_in[5]:17 chanx_right_in[5]:16 6.499219e-05 +16 chanx_right_in[5]:20 chanx_right_in[5]:19 0.0001576087 +17 chanx_right_in[5]:21 chanx_right_in[5]:20 0.0045 +18 chanx_right_in[5]:21 chanx_right_in[5]:18 0.001162947 +19 chanx_right_in[5]:19 mux_bottom_ipin_5\/mux_l1_in_2_:A0 0.152 +20 chanx_right_in[5]:23 chanx_right_in[5]:22 0.0001576087 +21 chanx_right_in[5]:24 chanx_right_in[5]:23 0.0045 +22 chanx_right_in[5]:24 chanx_right_in[5]:21 0.009410715 +23 chanx_right_in[5]:22 mux_bottom_ipin_1\/mux_l1_in_2_:A0 0.152 +24 chanx_right_in[5]:25 chanx_right_in[5]:24 0.002073661 +25 chanx_right_in[5]:26 chanx_right_in[5]:25 0.00341 + +*END + +*D_NET chanx_right_in[9] 0.01838777 //LENGTH 132.675 LUMPCC 0.005547056 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 103.650 34.000 +*I BUFT_P_90:A I *L 0.001767 *C 6.900 66.640 +*I mux_bottom_ipin_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 14.895 49.640 +*I mux_bottom_ipin_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 57.405 47.260 +*N chanx_right_in[9]:4 *C 57.443 47.260 +*N chanx_right_in[9]:5 *C 57.915 47.260 +*N chanx_right_in[9]:6 *C 57.960 47.260 +*N chanx_right_in[9]:7 *C 14.770 49.640 +*N chanx_right_in[9]:8 *C 6.900 66.640 +*N chanx_right_in[9]:9 *C 6.900 66.595 +*N chanx_right_in[9]:10 *C 6.900 49.685 +*N chanx_right_in[9]:11 *C 6.945 49.640 +*N chanx_right_in[9]:12 *C 14.675 49.640 +*N chanx_right_in[9]:13 *C 14.720 49.595 +*N chanx_right_in[9]:14 *C 14.720 46.977 +*N chanx_right_in[9]:15 *C 14.728 46.920 +*N chanx_right_in[9]:16 *C 57.953 46.920 +*N chanx_right_in[9]:17 *C 57.960 46.920 +*N chanx_right_in[9]:18 *C 58.420 46.920 +*N chanx_right_in[9]:19 *C 58.420 34.058 +*N chanx_right_in[9]:20 *C 58.428 34.000 + +*CAP +0 chanx_right_in[9] 0.002279241 +1 BUFT_P_90:A 1e-06 +2 mux_bottom_ipin_9\/mux_l1_in_2_:A0 1e-06 +3 mux_bottom_ipin_5\/mux_l2_in_2_:A1 1e-06 +4 chanx_right_in[9]:4 6.870373e-05 +5 chanx_right_in[9]:5 6.870373e-05 +6 chanx_right_in[9]:6 6.216056e-05 +7 chanx_right_in[9]:7 3.003001e-05 +8 chanx_right_in[9]:8 3.923562e-05 +9 chanx_right_in[9]:9 0.0008002085 +10 chanx_right_in[9]:10 0.0008002085 +11 chanx_right_in[9]:11 0.000407571 +12 chanx_right_in[9]:12 0.000437601 +13 chanx_right_in[9]:13 0.000172116 +14 chanx_right_in[9]:14 0.000172116 +15 chanx_right_in[9]:15 0.001856059 +16 chanx_right_in[9]:16 0.001856059 +17 chanx_right_in[9]:17 0.0001026595 +18 chanx_right_in[9]:18 0.0007214355 +19 chanx_right_in[9]:19 0.0006843671 +20 chanx_right_in[9]:20 0.002279241 +21 chanx_right_in[9] chanx_left_in[6]:12 0.0003467275 +22 chanx_right_in[9]:20 chanx_left_in[6]:13 0.0003467275 +23 chanx_right_in[9] chanx_left_in[8]:15 0.0004931902 +24 chanx_right_in[9]:20 chanx_left_in[8]:16 0.0004931902 +25 chanx_right_in[9]:16 chanx_left_in[19]:30 0.0007316846 +26 chanx_right_in[9]:15 chanx_left_in[19]:31 0.0007316846 +27 chanx_right_in[9]:10 chanx_left_in[19]:37 1.522798e-06 +28 chanx_right_in[9]:9 chanx_left_in[19]:36 1.522798e-06 +29 chanx_right_in[9]:16 chanx_right_in[15]:9 2.583305e-06 +30 chanx_right_in[9]:16 chanx_right_in[15]:18 0.0001698211 +31 chanx_right_in[9]:16 chanx_right_in[15]:19 0.0002936063 +32 chanx_right_in[9]:15 chanx_right_in[15]:8 2.583305e-06 +33 chanx_right_in[9]:15 chanx_right_in[15]:14 0.0001698211 +34 chanx_right_in[9]:15 chanx_right_in[15]:18 0.0002936063 +35 chanx_right_in[9]:16 prog_clk[0]:282 0.0002644043 +36 chanx_right_in[9]:14 prog_clk[0]:276 2.281275e-08 +37 chanx_right_in[9]:15 prog_clk[0]:281 0.0002644043 +38 chanx_right_in[9]:12 prog_clk[0]:280 8.557694e-06 +39 chanx_right_in[9]:13 prog_clk[0]:280 2.281275e-08 +40 chanx_right_in[9]:19 prog_clk[0]:192 3.805266e-05 +41 chanx_right_in[9]:11 prog_clk[0]:279 8.557694e-06 +42 chanx_right_in[9]:18 prog_clk[0]:193 3.805266e-05 +43 chanx_right_in[9]:10 ropt_net_129:5 9.790097e-05 +44 chanx_right_in[9]:9 ropt_net_129:4 9.790097e-05 +45 chanx_right_in[9]:10 ropt_net_142:5 0.0001370444 +46 chanx_right_in[9]:9 ropt_net_142:4 0.0001370444 +47 chanx_right_in[9]:12 ropt_net_155:5 0.0001808247 +48 chanx_right_in[9]:12 ropt_net_155:2 7.584821e-06 +49 chanx_right_in[9]:11 ropt_net_155:4 0.0001808247 +50 chanx_right_in[9]:11 ropt_net_155:3 7.584821e-06 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:20 0.007084858 +1 chanx_right_in[9]:17 chanx_right_in[9]:16 0.00341 +2 chanx_right_in[9]:17 chanx_right_in[9]:6 0.0001634616 +3 chanx_right_in[9]:16 chanx_right_in[9]:15 0.006771916 +4 chanx_right_in[9]:14 chanx_right_in[9]:13 0.002337054 +5 chanx_right_in[9]:15 chanx_right_in[9]:14 0.00341 +6 chanx_right_in[9]:12 chanx_right_in[9]:11 0.006901786 +7 chanx_right_in[9]:12 chanx_right_in[9]:7 8.482143e-05 +8 chanx_right_in[9]:13 chanx_right_in[9]:12 0.0045 +9 chanx_right_in[9]:19 chanx_right_in[9]:18 0.01148438 +10 chanx_right_in[9]:20 chanx_right_in[9]:19 0.00341 +11 chanx_right_in[9]:11 chanx_right_in[9]:10 0.0045 +12 chanx_right_in[9]:10 chanx_right_in[9]:9 0.01509822 +13 chanx_right_in[9]:8 BUFT_P_90:A 0.152 +14 chanx_right_in[9]:9 chanx_right_in[9]:8 0.0045 +15 chanx_right_in[9]:7 mux_bottom_ipin_9\/mux_l1_in_2_:A0 0.152 +16 chanx_right_in[9]:5 chanx_right_in[9]:4 0.000421875 +17 chanx_right_in[9]:6 chanx_right_in[9]:5 0.0045 +18 chanx_right_in[9]:4 mux_bottom_ipin_5\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[9]:18 chanx_right_in[9]:17 0.0004107143 + +*END + +*D_NET chanx_right_in[13] 0.01850136 //LENGTH 135.545 LUMPCC 0.005865861 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 103.650 65.960 +*I FTB_34__33:A I *L 0.001776 *C 5.520 55.760 +*I mux_bottom_ipin_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 11.040 56.100 +*I mux_bottom_ipin_13\/mux_l2_in_2_:A1 I *L 0.00198 *C 70.285 58.140 +*N chanx_right_in[13]:4 *C 70.323 58.140 +*N chanx_right_in[13]:5 *C 77.280 58.140 +*N chanx_right_in[13]:6 *C 77.280 57.800 +*N chanx_right_in[13]:7 *C 82.295 57.800 +*N chanx_right_in[13]:8 *C 82.340 57.845 +*N chanx_right_in[13]:9 *C 11.003 56.100 +*N chanx_right_in[13]:10 *C 5.558 55.760 +*N chanx_right_in[13]:11 *C 7.820 55.760 +*N chanx_right_in[13]:12 *C 7.820 56.100 +*N chanx_right_in[13]:13 *C 9.660 56.100 +*N chanx_right_in[13]:14 *C 9.660 55.760 +*N chanx_right_in[13]:15 *C 9.660 55.805 +*N chanx_right_in[13]:16 *C 9.660 65.903 +*N chanx_right_in[13]:17 *C 9.668 65.960 +*N chanx_right_in[13]:18 *C 61.172 65.960 +*N chanx_right_in[13]:19 *C 61.180 65.903 +*N chanx_right_in[13]:20 *C 61.180 64.657 +*N chanx_right_in[13]:21 *C 61.188 64.600 +*N chanx_right_in[13]:22 *C 82.333 64.600 +*N chanx_right_in[13]:23 *C 82.340 64.600 +*N chanx_right_in[13]:24 *C 82.340 65.903 +*N chanx_right_in[13]:25 *C 82.348 65.960 + +*CAP +0 chanx_right_in[13] 0.0008335461 +1 FTB_34__33:A 1e-06 +2 mux_bottom_ipin_9\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_13\/mux_l2_in_2_:A1 1e-06 +4 chanx_right_in[13]:4 0.0002926593 +5 chanx_right_in[13]:5 0.0003224713 +6 chanx_right_in[13]:6 0.0004233039 +7 chanx_right_in[13]:7 0.000393492 +8 chanx_right_in[13]:8 0.0003505673 +9 chanx_right_in[13]:9 0.000128974 +10 chanx_right_in[13]:10 0.000179407 +11 chanx_right_in[13]:11 0.0002066502 +12 chanx_right_in[13]:12 0.000169512 +13 chanx_right_in[13]:13 0.0003001885 +14 chanx_right_in[13]:14 6.283854e-05 +15 chanx_right_in[13]:15 0.000451323 +16 chanx_right_in[13]:16 0.000451323 +17 chanx_right_in[13]:17 0.002316081 +18 chanx_right_in[13]:18 0.002316081 +19 chanx_right_in[13]:19 9.223211e-05 +20 chanx_right_in[13]:20 9.223211e-05 +21 chanx_right_in[13]:21 0.0009345656 +22 chanx_right_in[13]:22 0.0009345657 +23 chanx_right_in[13]:23 0.0004658137 +24 chanx_right_in[13]:24 8.112144e-05 +25 chanx_right_in[13]:25 0.0008335461 +26 chanx_right_in[13] chanx_left_in[7]:9 0.0003228667 +27 chanx_right_in[13]:21 chanx_left_in[7]:10 1.510878e-05 +28 chanx_right_in[13]:21 chanx_left_in[7]:12 4.52155e-05 +29 chanx_right_in[13]:22 chanx_left_in[7]:9 1.510878e-05 +30 chanx_right_in[13]:22 chanx_left_in[7]:11 4.52155e-05 +31 chanx_right_in[13]:25 chanx_left_in[7]:10 0.0003228667 +32 chanx_right_in[13] chanx_right_in[1] 0.0003866835 +33 chanx_right_in[13]:25 chanx_right_in[1]:57 0.0003866835 +34 chanx_right_in[13] chanx_right_in[19]:22 2.657152e-05 +35 chanx_right_in[13]:15 chanx_right_in[19]:13 2.10753e-06 +36 chanx_right_in[13]:16 chanx_right_in[19]:14 2.10753e-06 +37 chanx_right_in[13]:17 chanx_right_in[19]:20 0.0003134934 +38 chanx_right_in[13]:18 chanx_right_in[19]:21 0.0003134934 +39 chanx_right_in[13]:21 chanx_right_in[19]:20 0.0003922589 +40 chanx_right_in[13]:21 chanx_right_in[19]:21 8.403968e-05 +41 chanx_right_in[13]:22 chanx_right_in[19]:22 8.403968e-05 +42 chanx_right_in[13]:22 chanx_right_in[19]:21 0.0003922589 +43 chanx_right_in[13]:25 chanx_right_in[19]:21 2.657152e-05 +44 chanx_right_in[13]:12 chanx_right_in[19]:12 2.761597e-05 +45 chanx_right_in[13]:13 chanx_right_in[19]:11 2.761597e-05 +46 chanx_right_in[13]:17 prog_clk[0]:297 1.820996e-05 +47 chanx_right_in[13]:17 prog_clk[0]:247 1.747645e-05 +48 chanx_right_in[13]:17 prog_clk[0]:382 9.186471e-05 +49 chanx_right_in[13]:17 prog_clk[0]:236 2.944524e-05 +50 chanx_right_in[13]:17 prog_clk[0]:243 1.388261e-05 +51 chanx_right_in[13]:17 prog_clk[0]:310 6.593145e-06 +52 chanx_right_in[13]:17 prog_clk[0]:288 6.814332e-05 +53 chanx_right_in[13]:17 prog_clk[0]:388 1.907066e-05 +54 chanx_right_in[13]:19 prog_clk[0]:386 1.945921e-06 +55 chanx_right_in[13]:18 prog_clk[0]:287 1.747645e-05 +56 chanx_right_in[13]:18 prog_clk[0]:297 6.814332e-05 +57 chanx_right_in[13]:18 prog_clk[0]:247 2.944524e-05 +58 chanx_right_in[13]:18 prog_clk[0]:305 1.820996e-05 +59 chanx_right_in[13]:18 prog_clk[0]:392 1.907066e-05 +60 chanx_right_in[13]:18 prog_clk[0]:244 1.388261e-05 +61 chanx_right_in[13]:18 prog_clk[0]:387 9.186471e-05 +62 chanx_right_in[13]:18 prog_clk[0]:311 6.593145e-06 +63 chanx_right_in[13]:20 prog_clk[0]:385 1.945921e-06 +64 chanx_right_in[13]:21 prog_clk[0]:397 1.443136e-06 +65 chanx_right_in[13]:21 prog_clk[0]:392 3.203847e-06 +66 chanx_right_in[13]:21 prog_clk[0]:388 9.806612e-07 +67 chanx_right_in[13]:22 prog_clk[0]:398 1.443136e-06 +68 chanx_right_in[13]:22 prog_clk[0]:392 9.806612e-07 +69 chanx_right_in[13]:22 prog_clk[0]:393 3.203847e-06 +70 chanx_right_in[13]:23 mux_tree_tapbuf_size10_7_sram[1]:29 3.309734e-05 +71 chanx_right_in[13]:8 mux_tree_tapbuf_size10_7_sram[1]:30 3.309734e-05 +72 chanx_right_in[13]:4 mux_tree_tapbuf_size10_7_sram[1]:14 2.57343e-05 +73 chanx_right_in[13]:4 mux_tree_tapbuf_size10_7_sram[1]:19 0.0002234245 +74 chanx_right_in[13]:5 mux_tree_tapbuf_size10_7_sram[1]:19 2.57343e-05 +75 chanx_right_in[13]:5 mux_tree_tapbuf_size10_7_sram[1]:20 0.0002234245 +76 chanx_right_in[13]:17 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 0.000169664 +77 chanx_right_in[13]:18 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 0.000169664 +78 chanx_right_in[13]:17 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0003796732 +79 chanx_right_in[13]:18 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0003796732 +80 chanx_right_in[13]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.792022e-05 +81 chanx_right_in[13]:16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.792022e-05 +82 chanx_right_in[13]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000103608 +83 chanx_right_in[13]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.365876e-06 +84 chanx_right_in[13]:16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000103608 +85 chanx_right_in[13]:16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.365876e-06 +86 chanx_right_in[13]:10 ropt_net_142:7 4.422165e-05 +87 chanx_right_in[13]:11 ropt_net_142:6 4.422165e-05 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:25 0.003337392 +1 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0003035715 +2 chanx_right_in[13]:15 chanx_right_in[13]:14 0.0045 +3 chanx_right_in[13]:16 chanx_right_in[13]:15 0.009015625 +4 chanx_right_in[13]:17 chanx_right_in[13]:16 0.00341 +5 chanx_right_in[13]:19 chanx_right_in[13]:18 0.00341 +6 chanx_right_in[13]:18 chanx_right_in[13]:17 0.008069116 +7 chanx_right_in[13]:20 chanx_right_in[13]:19 0.001111607 +8 chanx_right_in[13]:21 chanx_right_in[13]:20 0.00341 +9 chanx_right_in[13]:23 chanx_right_in[13]:22 0.00341 +10 chanx_right_in[13]:23 chanx_right_in[13]:8 0.006031251 +11 chanx_right_in[13]:22 chanx_right_in[13]:21 0.003312716 +12 chanx_right_in[13]:9 mux_bottom_ipin_9\/mux_l2_in_2_:A1 0.152 +13 chanx_right_in[13]:24 chanx_right_in[13]:23 0.001162947 +14 chanx_right_in[13]:25 chanx_right_in[13]:24 0.00341 +15 chanx_right_in[13]:10 FTB_34__33:A 0.152 +16 chanx_right_in[13]:7 chanx_right_in[13]:6 0.004477679 +17 chanx_right_in[13]:8 chanx_right_in[13]:7 0.0045 +18 chanx_right_in[13]:4 mux_bottom_ipin_13\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[13]:11 chanx_right_in[13]:10 0.002020089 +20 chanx_right_in[13]:12 chanx_right_in[13]:11 0.0003035715 +21 chanx_right_in[13]:13 chanx_right_in[13]:12 0.001642857 +22 chanx_right_in[13]:13 chanx_right_in[13]:9 0.001198661 +23 chanx_right_in[13]:5 chanx_right_in[13]:4 0.006212054 +24 chanx_right_in[13]:6 chanx_right_in[13]:5 0.0003035715 + +*END + +*D_NET chanx_right_in[19] 0.01639613 //LENGTH 120.490 LUMPCC 0.004745652 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 103.650 58.480 +*I mux_bottom_ipin_15\/mux_l2_in_3_:A1 I *L 0.00198 *C 90.525 56.100 +*I FTB_40__39:A I *L 0.001776 *C 8.740 55.760 +*I mux_bottom_ipin_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 9.760 58.140 +*I mux_bottom_ipin_7\/mux_l2_in_3_:A1 I *L 0.00198 *C 29.440 56.100 +*N chanx_right_in[19]:5 *C 29.402 56.100 +*N chanx_right_in[19]:6 *C 28.980 56.100 +*N chanx_right_in[19]:7 *C 28.980 56.440 +*N chanx_right_in[19]:8 *C 28.980 56.485 +*N chanx_right_in[19]:9 *C 9.723 58.140 +*N chanx_right_in[19]:10 *C 8.740 58.140 +*N chanx_right_in[19]:11 *C 8.703 55.760 +*N chanx_right_in[19]:12 *C 8.325 55.760 +*N chanx_right_in[19]:13 *C 8.280 55.805 +*N chanx_right_in[19]:14 *C 8.280 57.755 +*N chanx_right_in[19]:15 *C 8.325 57.800 +*N chanx_right_in[19]:16 *C 8.740 57.800 +*N chanx_right_in[19]:17 *C 28.935 57.800 +*N chanx_right_in[19]:18 *C 28.980 57.800 +*N chanx_right_in[19]:19 *C 28.980 63.183 +*N chanx_right_in[19]:20 *C 28.988 63.240 +*N chanx_right_in[19]:21 *C 78.815 63.240 +*N chanx_right_in[19]:22 *C 93.833 63.240 +*N chanx_right_in[19]:23 *C 93.840 63.183 +*N chanx_right_in[19]:24 *C 90.562 56.100 +*N chanx_right_in[19]:25 *C 93.795 56.100 +*N chanx_right_in[19]:26 *C 93.840 56.145 +*N chanx_right_in[19]:27 *C 93.840 58.480 +*N chanx_right_in[19]:28 *C 93.848 58.480 + +*CAP +0 chanx_right_in[19] 0.0005438288 +1 mux_bottom_ipin_15\/mux_l2_in_3_:A1 1e-06 +2 FTB_40__39:A 1e-06 +3 mux_bottom_ipin_9\/mux_l2_in_3_:A1 1e-06 +4 mux_bottom_ipin_7\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[19]:5 5.411443e-05 +6 chanx_right_in[19]:6 8.467109e-05 +7 chanx_right_in[19]:7 6.583513e-05 +8 chanx_right_in[19]:8 9.312245e-05 +9 chanx_right_in[19]:9 9.996614e-05 +10 chanx_right_in[19]:10 0.0001275243 +11 chanx_right_in[19]:11 4.194352e-05 +12 chanx_right_in[19]:12 4.194352e-05 +13 chanx_right_in[19]:13 0.0001143122 +14 chanx_right_in[19]:14 0.0001143122 +15 chanx_right_in[19]:15 3.878285e-05 +16 chanx_right_in[19]:16 0.001321546 +17 chanx_right_in[19]:17 0.001255205 +18 chanx_right_in[19]:18 0.0004476972 +19 chanx_right_in[19]:19 0.000319201 +20 chanx_right_in[19]:20 0.001797922 +21 chanx_right_in[19]:21 0.002473282 +22 chanx_right_in[19]:22 0.0006753596 +23 chanx_right_in[19]:23 0.0002734699 +24 chanx_right_in[19]:24 0.0002626288 +25 chanx_right_in[19]:25 0.0002626288 +26 chanx_right_in[19]:26 0.0001403147 +27 chanx_right_in[19]:27 0.0004530324 +28 chanx_right_in[19]:28 0.0005438288 +29 chanx_right_in[19]:20 chanx_left_in[17]:29 0.0005246174 +30 chanx_right_in[19]:21 chanx_left_in[17]:28 0.0005246174 +31 chanx_right_in[19] chanx_right_in[5] 6.527948e-05 +32 chanx_right_in[19]:20 chanx_right_in[5]:26 0.0002119552 +33 chanx_right_in[19]:22 chanx_right_in[5] 0.0002020139 +34 chanx_right_in[19]:28 chanx_right_in[5]:26 6.527948e-05 +35 chanx_right_in[19]:21 chanx_right_in[5] 0.0002119552 +36 chanx_right_in[19]:21 chanx_right_in[5]:26 0.0002020139 +37 chanx_right_in[19]:20 chanx_right_in[13]:17 0.0003134934 +38 chanx_right_in[19]:20 chanx_right_in[13]:21 0.0003922589 +39 chanx_right_in[19]:22 chanx_right_in[13] 2.657152e-05 +40 chanx_right_in[19]:22 chanx_right_in[13]:22 8.403968e-05 +41 chanx_right_in[19]:14 chanx_right_in[13]:16 2.10753e-06 +42 chanx_right_in[19]:12 chanx_right_in[13]:12 2.761597e-05 +43 chanx_right_in[19]:13 chanx_right_in[13]:15 2.10753e-06 +44 chanx_right_in[19]:11 chanx_right_in[13]:13 2.761597e-05 +45 chanx_right_in[19]:21 chanx_right_in[13]:18 0.0003134934 +46 chanx_right_in[19]:21 chanx_right_in[13]:21 8.403968e-05 +47 chanx_right_in[19]:21 chanx_right_in[13]:22 0.0003922589 +48 chanx_right_in[19]:21 chanx_right_in[13]:25 2.657152e-05 +49 chanx_right_in[19]:20 chanx_right_in[17]:9 0.0001977562 +50 chanx_right_in[19]:20 chanx_right_in[17]:16 7.900539e-05 +51 chanx_right_in[19]:21 chanx_right_in[17]:10 0.0001977562 +52 chanx_right_in[19]:21 chanx_right_in[17]:21 7.900539e-05 +53 chanx_right_in[19]:17 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001396402 +54 chanx_right_in[19]:16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001396402 +55 chanx_right_in[19]:14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.714426e-05 +56 chanx_right_in[19]:13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.714426e-05 +57 chanx_right_in[19]:17 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.932642e-05 +58 chanx_right_in[19]:16 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.932642e-05 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:28 0.001535725 +1 chanx_right_in[19]:19 chanx_right_in[19]:18 0.004805804 +2 chanx_right_in[19]:20 chanx_right_in[19]:19 0.00341 +3 chanx_right_in[19]:23 chanx_right_in[19]:22 0.00341 +4 chanx_right_in[19]:22 chanx_right_in[19]:21 0.002352742 +5 chanx_right_in[19]:17 chanx_right_in[19]:16 0.01803125 +6 chanx_right_in[19]:18 chanx_right_in[19]:17 0.0045 +7 chanx_right_in[19]:18 chanx_right_in[19]:8 0.001174107 +8 chanx_right_in[19]:7 chanx_right_in[19]:6 0.0003035715 +9 chanx_right_in[19]:8 chanx_right_in[19]:7 0.0045 +10 chanx_right_in[19]:5 mux_bottom_ipin_7\/mux_l2_in_3_:A1 0.152 +11 chanx_right_in[19]:25 chanx_right_in[19]:24 0.002886161 +12 chanx_right_in[19]:26 chanx_right_in[19]:25 0.0045 +13 chanx_right_in[19]:24 mux_bottom_ipin_15\/mux_l2_in_3_:A1 0.152 +14 chanx_right_in[19]:9 mux_bottom_ipin_9\/mux_l2_in_3_:A1 0.152 +15 chanx_right_in[19]:15 chanx_right_in[19]:14 0.0045 +16 chanx_right_in[19]:14 chanx_right_in[19]:13 0.001741072 +17 chanx_right_in[19]:12 chanx_right_in[19]:11 0.0003370536 +18 chanx_right_in[19]:13 chanx_right_in[19]:12 0.0045 +19 chanx_right_in[19]:11 FTB_40__39:A 0.152 +20 chanx_right_in[19]:27 chanx_right_in[19]:26 0.002084821 +21 chanx_right_in[19]:27 chanx_right_in[19]:23 0.00419866 +22 chanx_right_in[19]:28 chanx_right_in[19]:27 0.00341 +23 chanx_right_in[19]:16 chanx_right_in[19]:15 0.0003705357 +24 chanx_right_in[19]:16 chanx_right_in[19]:10 0.0003035715 +25 chanx_right_in[19]:10 chanx_right_in[19]:9 0.0008772321 +26 chanx_right_in[19]:6 chanx_right_in[19]:5 0.0003772322 +27 chanx_right_in[19]:21 chanx_right_in[19]:20 0.007806308 + +*END + +*D_NET top_grid_pin_27_[0] 0.001570733 //LENGTH 12.070 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 23.000 72.080 +*P top_grid_pin_27_[0] O *L 0.7423 *C 14.260 74.835 +*N top_grid_pin_27_[0]:2 *C 14.260 72.805 +*N top_grid_pin_27_[0]:3 *C 14.305 72.760 +*N top_grid_pin_27_[0]:4 *C 23.000 72.760 +*N top_grid_pin_27_[0]:5 *C 23.000 72.080 + +*CAP +0 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_27_[0] 0.0001322878 +2 top_grid_pin_27_[0]:2 0.0001322878 +3 top_grid_pin_27_[0]:3 0.0006041277 +4 top_grid_pin_27_[0]:4 0.0006413233 +5 top_grid_pin_27_[0]:5 5.970644e-05 + +*RES +0 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_27_[0]:5 0.152 +1 top_grid_pin_27_[0]:3 top_grid_pin_27_[0]:2 0.0045 +2 top_grid_pin_27_[0]:2 top_grid_pin_27_[0] 0.0018125 +3 top_grid_pin_27_[0]:5 top_grid_pin_27_[0]:4 0.000607143 +4 top_grid_pin_27_[0]:4 top_grid_pin_27_[0]:3 0.007763393 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.003496751 //LENGTH 28.335 LUMPCC 0.0003102339 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 91.845 39.440 +*I mux_bottom_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 84.540 31.280 +*I mux_bottom_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 86.580 34.680 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 82.975 42.500 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 83.013 42.500 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 86.543 34.680 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 84.640 34.680 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 84.540 31.280 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 84.640 31.325 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 84.640 34.295 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 84.640 34.370 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 83.765 34.340 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 83.720 34.385 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 83.720 42.455 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 83.720 42.500 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 91.495 42.500 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 91.540 42.455 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 91.540 39.485 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 91.540 39.440 +*N mux_tree_tapbuf_size10_0_sram[2]:19 *C 91.845 39.440 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 6.565829e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 0.0001362651 +6 mux_tree_tapbuf_size10_0_sram[2]:6 0.0001649942 +7 mux_tree_tapbuf_size10_0_sram[2]:7 2.955517e-05 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0001365535 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.0001365535 +10 mux_tree_tapbuf_size10_0_sram[2]:10 7.667929e-05 +11 mux_tree_tapbuf_size10_0_sram[2]:11 4.795012e-05 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0003803687 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0003803687 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.0006264441 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.0005260133 +16 mux_tree_tapbuf_size10_0_sram[2]:16 0.0001811959 +17 mux_tree_tapbuf_size10_0_sram[2]:17 0.0001811959 +18 mux_tree_tapbuf_size10_0_sram[2]:18 5.861473e-05 +19 mux_tree_tapbuf_size10_0_sram[2]:19 5.410665e-05 +20 mux_tree_tapbuf_size10_0_sram[2]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.294814e-05 +21 mux_tree_tapbuf_size10_0_sram[2]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.412815e-05 +22 mux_tree_tapbuf_size10_0_sram[2]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.294814e-05 +23 mux_tree_tapbuf_size10_0_sram[2]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.270788e-06 +24 mux_tree_tapbuf_size10_0_sram[2]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.412815e-05 +25 mux_tree_tapbuf_size10_0_sram[2]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.659851e-05 +26 mux_tree_tapbuf_size10_0_sram[2]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.659851e-05 +27 mux_tree_tapbuf_size10_0_sram[2]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.270788e-06 +28 mux_tree_tapbuf_size10_0_sram[2]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.497004e-06 +29 mux_tree_tapbuf_size10_0_sram[2]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.497004e-06 +30 mux_tree_tapbuf_size10_0_sram[2]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.867435e-05 +31 mux_tree_tapbuf_size10_0_sram[2]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.867435e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +2 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:4 0.0006316964 +3 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.007205357 +4 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.00078125 +5 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.0045 +6 mux_tree_tapbuf_size10_0_sram[2]:5 mux_bottom_ipin_0\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_0_sram[2]:4 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:6 0.0002767857 +10 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.002651786 +11 mux_tree_tapbuf_size10_0_sram[2]:7 mux_bottom_ipin_0\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.0045 +13 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.006941965 +14 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.0045 +15 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:17 0.0045 +16 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.002651786 +17 mux_tree_tapbuf_size10_0_sram[2]:19 mux_tree_tapbuf_size10_0_sram[2]:18 0.0001657609 +18 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.001698661 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[3] 0.00129399 //LENGTH 10.535 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 56.885 12.240 +*I mux_bottom_ipin_4\/mux_l4_in_0_:S I *L 0.00357 *C 57.140 17.975 +*I mem_bottom_ipin_4\/FTB_3__42:A I *L 0.001746 *C 57.960 20.400 +*N mux_tree_tapbuf_size10_2_sram[3]:3 *C 57.922 20.400 +*N mux_tree_tapbuf_size10_2_sram[3]:4 *C 57.085 20.400 +*N mux_tree_tapbuf_size10_2_sram[3]:5 *C 57.040 20.355 +*N mux_tree_tapbuf_size10_2_sram[3]:6 *C 57.140 17.975 +*N mux_tree_tapbuf_size10_2_sram[3]:7 *C 57.040 17.680 +*N mux_tree_tapbuf_size10_2_sram[3]:8 *C 57.040 17.680 +*N mux_tree_tapbuf_size10_2_sram[3]:9 *C 57.040 12.285 +*N mux_tree_tapbuf_size10_2_sram[3]:10 *C 57.040 12.240 +*N mux_tree_tapbuf_size10_2_sram[3]:11 *C 56.885 12.240 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_4\/FTB_3__42:A 1e-06 +3 mux_tree_tapbuf_size10_2_sram[3]:3 8.893826e-05 +4 mux_tree_tapbuf_size10_2_sram[3]:4 8.893826e-05 +5 mux_tree_tapbuf_size10_2_sram[3]:5 0.0001586793 +6 mux_tree_tapbuf_size10_2_sram[3]:6 5.858114e-05 +7 mux_tree_tapbuf_size10_2_sram[3]:7 5.968075e-05 +8 mux_tree_tapbuf_size10_2_sram[3]:8 0.0004629272 +9 mux_tree_tapbuf_size10_2_sram[3]:9 0.0002745749 +10 mux_tree_tapbuf_size10_2_sram[3]:10 5.198385e-05 +11 mux_tree_tapbuf_size10_2_sram[3]:11 4.66858e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_2_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_2_sram[3]:3 mem_bottom_ipin_4\/FTB_3__42:A 0.152 +2 mux_tree_tapbuf_size10_2_sram[3]:4 mux_tree_tapbuf_size10_2_sram[3]:3 0.0007477679 +3 mux_tree_tapbuf_size10_2_sram[3]:5 mux_tree_tapbuf_size10_2_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size10_2_sram[3]:10 mux_tree_tapbuf_size10_2_sram[3]:9 0.0045 +5 mux_tree_tapbuf_size10_2_sram[3]:9 mux_tree_tapbuf_size10_2_sram[3]:8 0.004816964 +6 mux_tree_tapbuf_size10_2_sram[3]:11 mux_tree_tapbuf_size10_2_sram[3]:10 8.423914e-05 +7 mux_tree_tapbuf_size10_2_sram[3]:7 mux_tree_tapbuf_size10_2_sram[3]:6 0.0001715116 +8 mux_tree_tapbuf_size10_2_sram[3]:8 mux_tree_tapbuf_size10_2_sram[3]:7 0.0045 +9 mux_tree_tapbuf_size10_2_sram[3]:8 mux_tree_tapbuf_size10_2_sram[3]:5 0.002388393 +10 mux_tree_tapbuf_size10_2_sram[3]:6 mux_bottom_ipin_4\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[1] 0.004992733 //LENGTH 34.085 LUMPCC 0.0003203038 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 21.750 26.520 +*I mux_bottom_ipin_8\/mux_l2_in_0_:S I *L 0.00357 *C 14.380 29.240 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 13.055 33.660 +*I mux_bottom_ipin_8\/mux_l2_in_1_:S I *L 0.00357 *C 8.620 29.240 +*I mux_bottom_ipin_8\/mux_l2_in_2_:S I *L 0.00357 *C 9.320 25.500 +*I mux_bottom_ipin_8\/mux_l2_in_3_:S I *L 0.00357 *C 5.880 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:6 *C 5.918 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:7 *C 7.775 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:8 *C 7.820 30.555 +*N mux_tree_tapbuf_size10_4_sram[1]:9 *C 9.357 25.500 +*N mux_tree_tapbuf_size10_4_sram[1]:10 *C 10.120 25.500 +*N mux_tree_tapbuf_size10_4_sram[1]:11 *C 10.120 25.840 +*N mux_tree_tapbuf_size10_4_sram[1]:12 *C 7.820 25.840 +*N mux_tree_tapbuf_size10_4_sram[1]:13 *C 7.820 26.180 +*N mux_tree_tapbuf_size10_4_sram[1]:14 *C 7.820 26.225 +*N mux_tree_tapbuf_size10_4_sram[1]:15 *C 7.820 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:16 *C 7.865 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:17 *C 8.620 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:18 *C 13.055 33.660 +*N mux_tree_tapbuf_size10_4_sram[1]:19 *C 13.340 33.660 +*N mux_tree_tapbuf_size10_4_sram[1]:20 *C 13.340 33.615 +*N mux_tree_tapbuf_size10_4_sram[1]:21 *C 13.340 29.285 +*N mux_tree_tapbuf_size10_4_sram[1]:22 *C 13.340 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:23 *C 14.380 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:24 *C 16.975 29.240 +*N mux_tree_tapbuf_size10_4_sram[1]:25 *C 17.020 29.195 +*N mux_tree_tapbuf_size10_4_sram[1]:26 *C 17.020 26.565 +*N mux_tree_tapbuf_size10_4_sram[1]:27 *C 17.065 26.520 +*N mux_tree_tapbuf_size10_4_sram[1]:28 *C 21.713 26.520 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_8\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_8\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_ipin_8\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_4_sram[1]:6 0.0001597335 +7 mux_tree_tapbuf_size10_4_sram[1]:7 0.0001597335 +8 mux_tree_tapbuf_size10_4_sram[1]:8 6.40931e-05 +9 mux_tree_tapbuf_size10_4_sram[1]:9 4.889594e-05 +10 mux_tree_tapbuf_size10_4_sram[1]:10 7.581465e-05 +11 mux_tree_tapbuf_size10_4_sram[1]:11 0.0001973803 +12 mux_tree_tapbuf_size10_4_sram[1]:12 0.0001986725 +13 mux_tree_tapbuf_size10_4_sram[1]:13 6.151849e-05 +14 mux_tree_tapbuf_size10_4_sram[1]:14 0.0001318248 +15 mux_tree_tapbuf_size10_4_sram[1]:15 0.0002316686 +16 mux_tree_tapbuf_size10_4_sram[1]:16 7.802842e-05 +17 mux_tree_tapbuf_size10_4_sram[1]:17 0.0004515277 +18 mux_tree_tapbuf_size10_4_sram[1]:18 5.863147e-05 +19 mux_tree_tapbuf_size10_4_sram[1]:19 6.324619e-05 +20 mux_tree_tapbuf_size10_4_sram[1]:20 0.0003143568 +21 mux_tree_tapbuf_size10_4_sram[1]:21 0.0003143568 +22 mux_tree_tapbuf_size10_4_sram[1]:22 0.0004367934 +23 mux_tree_tapbuf_size10_4_sram[1]:23 0.0002457496 +24 mux_tree_tapbuf_size10_4_sram[1]:24 0.0001509125 +25 mux_tree_tapbuf_size10_4_sram[1]:25 0.0002005546 +26 mux_tree_tapbuf_size10_4_sram[1]:26 0.0002005546 +27 mux_tree_tapbuf_size10_4_sram[1]:27 0.0004111912 +28 mux_tree_tapbuf_size10_4_sram[1]:28 0.0004111912 +29 mux_tree_tapbuf_size10_4_sram[1]:24 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.251032e-05 +30 mux_tree_tapbuf_size10_4_sram[1]:22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.868468e-06 +31 mux_tree_tapbuf_size10_4_sram[1]:23 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.868468e-06 +32 mux_tree_tapbuf_size10_4_sram[1]:23 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.251032e-05 +33 mux_tree_tapbuf_size10_4_sram[1]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.089363e-05 +34 mux_tree_tapbuf_size10_4_sram[1]:15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.687948e-05 +35 mux_tree_tapbuf_size10_4_sram[1]:15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.089363e-05 +36 mux_tree_tapbuf_size10_4_sram[1]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.687948e-05 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_4_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_4_sram[1]:13 mux_tree_tapbuf_size10_4_sram[1]:12 0.0003035715 +2 mux_tree_tapbuf_size10_4_sram[1]:14 mux_tree_tapbuf_size10_4_sram[1]:13 0.0045 +3 mux_tree_tapbuf_size10_4_sram[1]:9 mux_bottom_ipin_8\/mux_l2_in_2_:S 0.152 +4 mux_tree_tapbuf_size10_4_sram[1]:16 mux_tree_tapbuf_size10_4_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size10_4_sram[1]:15 mux_tree_tapbuf_size10_4_sram[1]:14 0.002691964 +6 mux_tree_tapbuf_size10_4_sram[1]:15 mux_tree_tapbuf_size10_4_sram[1]:8 0.001174107 +7 mux_tree_tapbuf_size10_4_sram[1]:24 mux_tree_tapbuf_size10_4_sram[1]:23 0.002316964 +8 mux_tree_tapbuf_size10_4_sram[1]:25 mux_tree_tapbuf_size10_4_sram[1]:24 0.0045 +9 mux_tree_tapbuf_size10_4_sram[1]:27 mux_tree_tapbuf_size10_4_sram[1]:26 0.0045 +10 mux_tree_tapbuf_size10_4_sram[1]:26 mux_tree_tapbuf_size10_4_sram[1]:25 0.002348214 +11 mux_tree_tapbuf_size10_4_sram[1]:28 mux_tree_tapbuf_size10_4_sram[1]:27 0.004149554 +12 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:21 0.0045 +13 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:17 0.004214286 +14 mux_tree_tapbuf_size10_4_sram[1]:21 mux_tree_tapbuf_size10_4_sram[1]:20 0.003866072 +15 mux_tree_tapbuf_size10_4_sram[1]:19 mux_tree_tapbuf_size10_4_sram[1]:18 0.0001548913 +16 mux_tree_tapbuf_size10_4_sram[1]:20 mux_tree_tapbuf_size10_4_sram[1]:19 0.0045 +17 mux_tree_tapbuf_size10_4_sram[1]:18 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size10_4_sram[1]:7 mux_tree_tapbuf_size10_4_sram[1]:6 0.001658482 +19 mux_tree_tapbuf_size10_4_sram[1]:8 mux_tree_tapbuf_size10_4_sram[1]:7 0.0045 +20 mux_tree_tapbuf_size10_4_sram[1]:6 mux_bottom_ipin_8\/mux_l2_in_3_:S 0.152 +21 mux_tree_tapbuf_size10_4_sram[1]:17 mux_bottom_ipin_8\/mux_l2_in_1_:S 0.152 +22 mux_tree_tapbuf_size10_4_sram[1]:17 mux_tree_tapbuf_size10_4_sram[1]:16 0.0006741072 +23 mux_tree_tapbuf_size10_4_sram[1]:23 mux_bottom_ipin_8\/mux_l2_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:22 0.0009285715 +25 mux_tree_tapbuf_size10_4_sram[1]:12 mux_tree_tapbuf_size10_4_sram[1]:11 0.002053571 +26 mux_tree_tapbuf_size10_4_sram[1]:11 mux_tree_tapbuf_size10_4_sram[1]:10 0.0003035715 +27 mux_tree_tapbuf_size10_4_sram[1]:10 mux_tree_tapbuf_size10_4_sram[1]:9 0.0006808036 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[2] 0.00410304 //LENGTH 31.390 LUMPCC 0.0007524032 DR + +*CONN +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 95.985 11.900 +*I mux_top_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 86.380 14.670 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 79.710 6.460 +*I mux_top_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 88.420 14.670 +*N mux_tree_tapbuf_size10_8_sram[2]:4 *C 88.420 14.670 +*N mux_tree_tapbuf_size10_8_sram[2]:5 *C 79.688 6.433 +*N mux_tree_tapbuf_size10_8_sram[2]:6 *C 79.580 6.120 +*N mux_tree_tapbuf_size10_8_sram[2]:7 *C 79.580 6.165 +*N mux_tree_tapbuf_size10_8_sram[2]:8 *C 79.580 14.915 +*N mux_tree_tapbuf_size10_8_sram[2]:9 *C 79.625 14.960 +*N mux_tree_tapbuf_size10_8_sram[2]:10 *C 86.323 14.960 +*N mux_tree_tapbuf_size10_8_sram[2]:11 *C 86.380 14.628 +*N mux_tree_tapbuf_size10_8_sram[2]:12 *C 87.400 14.620 +*N mux_tree_tapbuf_size10_8_sram[2]:13 *C 87.400 14.280 +*N mux_tree_tapbuf_size10_8_sram[2]:14 *C 88.420 14.280 +*N mux_tree_tapbuf_size10_8_sram[2]:15 *C 91.955 14.280 +*N mux_tree_tapbuf_size10_8_sram[2]:16 *C 92.000 14.235 +*N mux_tree_tapbuf_size10_8_sram[2]:17 *C 92.000 11.945 +*N mux_tree_tapbuf_size10_8_sram[2]:18 *C 92.045 11.900 +*N mux_tree_tapbuf_size10_8_sram[2]:19 *C 95.948 11.900 + +*CAP +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_ipin_0\/mux_l3_in_1_:S 1e-06 +2 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_top_ipin_0\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_8_sram[2]:4 5.89951e-05 +5 mux_tree_tapbuf_size10_8_sram[2]:5 3.474377e-05 +6 mux_tree_tapbuf_size10_8_sram[2]:6 6.799803e-05 +7 mux_tree_tapbuf_size10_8_sram[2]:7 0.0003407452 +8 mux_tree_tapbuf_size10_8_sram[2]:8 0.0003407452 +9 mux_tree_tapbuf_size10_8_sram[2]:9 0.0003715328 +10 mux_tree_tapbuf_size10_8_sram[2]:10 0.0004011067 +11 mux_tree_tapbuf_size10_8_sram[2]:11 0.0001121027 +12 mux_tree_tapbuf_size10_8_sram[2]:12 0.0001008304 +13 mux_tree_tapbuf_size10_8_sram[2]:13 9.71714e-05 +14 mux_tree_tapbuf_size10_8_sram[2]:14 0.0003149878 +15 mux_tree_tapbuf_size10_8_sram[2]:15 0.0002057726 +16 mux_tree_tapbuf_size10_8_sram[2]:16 0.0001479412 +17 mux_tree_tapbuf_size10_8_sram[2]:17 0.0001479412 +18 mux_tree_tapbuf_size10_8_sram[2]:18 0.0003020116 +19 mux_tree_tapbuf_size10_8_sram[2]:19 0.0003020116 +20 mux_tree_tapbuf_size10_8_sram[2]:8 chanx_right_in[16]:22 0.0002419567 +21 mux_tree_tapbuf_size10_8_sram[2]:7 chanx_right_in[16]:17 0.0002419567 +22 mux_tree_tapbuf_size10_8_sram[2]:15 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.154415e-05 +23 mux_tree_tapbuf_size10_8_sram[2]:15 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.052519e-08 +24 mux_tree_tapbuf_size10_8_sram[2]:14 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.154415e-05 +25 mux_tree_tapbuf_size10_8_sram[2]:14 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.052519e-08 +26 mux_tree_tapbuf_size10_8_sram[2]:9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.267033e-05 +27 mux_tree_tapbuf_size10_8_sram[2]:10 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.267033e-05 + +*RES +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_8_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_8_sram[2]:19 mux_tree_tapbuf_size10_8_sram[2]:18 0.003484375 +2 mux_tree_tapbuf_size10_8_sram[2]:18 mux_tree_tapbuf_size10_8_sram[2]:17 0.0045 +3 mux_tree_tapbuf_size10_8_sram[2]:17 mux_tree_tapbuf_size10_8_sram[2]:16 0.002044643 +4 mux_tree_tapbuf_size10_8_sram[2]:15 mux_tree_tapbuf_size10_8_sram[2]:14 0.00315625 +5 mux_tree_tapbuf_size10_8_sram[2]:16 mux_tree_tapbuf_size10_8_sram[2]:15 0.0045 +6 mux_tree_tapbuf_size10_8_sram[2]:9 mux_tree_tapbuf_size10_8_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size10_8_sram[2]:8 mux_tree_tapbuf_size10_8_sram[2]:7 0.0078125 +8 mux_tree_tapbuf_size10_8_sram[2]:6 mux_tree_tapbuf_size10_8_sram[2]:5 0.0002111487 +9 mux_tree_tapbuf_size10_8_sram[2]:7 mux_tree_tapbuf_size10_8_sram[2]:6 0.0045 +10 mux_tree_tapbuf_size10_8_sram[2]:5 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size10_8_sram[2]:11 mux_top_ipin_0\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_8_sram[2]:11 mux_tree_tapbuf_size10_8_sram[2]:10 0.000193314 +13 mux_tree_tapbuf_size10_8_sram[2]:4 mux_top_ipin_0\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size10_8_sram[2]:10 mux_tree_tapbuf_size10_8_sram[2]:9 0.005979911 +15 mux_tree_tapbuf_size10_8_sram[2]:12 mux_tree_tapbuf_size10_8_sram[2]:11 0.0009107143 +16 mux_tree_tapbuf_size10_8_sram[2]:13 mux_tree_tapbuf_size10_8_sram[2]:12 0.0003035715 +17 mux_tree_tapbuf_size10_8_sram[2]:14 mux_tree_tapbuf_size10_8_sram[2]:13 0.0009107143 +18 mux_tree_tapbuf_size10_8_sram[2]:14 mux_tree_tapbuf_size10_8_sram[2]:4 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[3] 0.001981222 //LENGTH 14.460 LUMPCC 0.0004287836 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 47.685 28.220 +*I mux_bottom_ipin_6\/mux_l4_in_0_:S I *L 0.00357 *C 41.500 25.160 +*I mem_bottom_ipin_6\/FTB_12__51:A I *L 0.001746 *C 42.780 31.280 +*N mux_tree_tapbuf_size8_2_sram[3]:3 *C 42.818 31.280 +*N mux_tree_tapbuf_size8_2_sram[3]:4 *C 43.655 31.280 +*N mux_tree_tapbuf_size8_2_sram[3]:5 *C 43.700 31.235 +*N mux_tree_tapbuf_size8_2_sram[3]:6 *C 41.538 25.160 +*N mux_tree_tapbuf_size8_2_sram[3]:7 *C 43.655 25.160 +*N mux_tree_tapbuf_size8_2_sram[3]:8 *C 43.700 25.205 +*N mux_tree_tapbuf_size8_2_sram[3]:9 *C 43.700 28.220 +*N mux_tree_tapbuf_size8_2_sram[3]:10 *C 43.745 28.220 +*N mux_tree_tapbuf_size8_2_sram[3]:11 *C 47.648 28.220 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_6\/FTB_12__51:A 1e-06 +3 mux_tree_tapbuf_size8_2_sram[3]:3 7.036125e-05 +4 mux_tree_tapbuf_size8_2_sram[3]:4 7.036125e-05 +5 mux_tree_tapbuf_size8_2_sram[3]:5 0.0001831021 +6 mux_tree_tapbuf_size8_2_sram[3]:6 0.0001498231 +7 mux_tree_tapbuf_size8_2_sram[3]:7 0.0001498231 +8 mux_tree_tapbuf_size8_2_sram[3]:8 0.0001765144 +9 mux_tree_tapbuf_size8_2_sram[3]:9 0.0003954854 +10 mux_tree_tapbuf_size8_2_sram[3]:10 0.0001769841 +11 mux_tree_tapbuf_size8_2_sram[3]:11 0.0001769841 +12 mux_tree_tapbuf_size8_2_sram[3]:10 chanx_right_in[0]:29 0.0001595519 +13 mux_tree_tapbuf_size8_2_sram[3]:11 chanx_right_in[0]:30 0.0001595519 +14 mux_tree_tapbuf_size8_2_sram[3]:7 chanx_right_in[0]:30 4.989382e-07 +15 mux_tree_tapbuf_size8_2_sram[3]:6 chanx_right_in[0]:29 4.989382e-07 +16 mux_tree_tapbuf_size8_2_sram[3]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.421235e-06 +17 mux_tree_tapbuf_size8_2_sram[3]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.791976e-05 +18 mux_tree_tapbuf_size8_2_sram[3]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.421235e-06 +19 mux_tree_tapbuf_size8_2_sram[3]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.791976e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_2_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.0045 +2 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:8 0.002691964 +3 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:5 0.002691964 +4 mux_tree_tapbuf_size8_2_sram[3]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.003484375 +5 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size8_2_sram[3]:6 0.001890625 +6 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size8_2_sram[3]:7 0.0045 +7 mux_tree_tapbuf_size8_2_sram[3]:6 mux_bottom_ipin_6\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_2_sram[3]:4 mux_tree_tapbuf_size8_2_sram[3]:3 0.0007477679 +9 mux_tree_tapbuf_size8_2_sram[3]:5 mux_tree_tapbuf_size8_2_sram[3]:4 0.0045 +10 mux_tree_tapbuf_size8_2_sram[3]:3 mem_bottom_ipin_6\/FTB_12__51:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[3] 0.001220068 //LENGTH 10.820 LUMPCC 9.624717e-05 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 21.465 9.860 +*I mem_bottom_ipin_10\/FTB_14__53:A I *L 0.001746 *C 20.700 17.680 +*I mux_bottom_ipin_10\/mux_l4_in_0_:S I *L 0.00357 *C 19.320 17.855 +*N mux_tree_tapbuf_size8_4_sram[3]:3 *C 19.358 17.745 +*N mux_tree_tapbuf_size8_4_sram[3]:4 *C 20.663 17.680 +*N mux_tree_tapbuf_size8_4_sram[3]:5 *C 20.700 17.635 +*N mux_tree_tapbuf_size8_4_sram[3]:6 *C 20.700 9.905 +*N mux_tree_tapbuf_size8_4_sram[3]:7 *C 20.745 9.860 +*N mux_tree_tapbuf_size8_4_sram[3]:8 *C 21.428 9.860 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_10\/FTB_14__53:A 1e-06 +2 mux_bottom_ipin_10\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_4_sram[3]:3 8.318464e-05 +4 mux_tree_tapbuf_size8_4_sram[3]:4 8.318464e-05 +5 mux_tree_tapbuf_size8_4_sram[3]:5 0.0004183032 +6 mux_tree_tapbuf_size8_4_sram[3]:6 0.0004183032 +7 mux_tree_tapbuf_size8_4_sram[3]:7 5.892285e-05 +8 mux_tree_tapbuf_size8_4_sram[3]:8 5.892285e-05 +9 mux_tree_tapbuf_size8_4_sram[3]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.812359e-05 +10 mux_tree_tapbuf_size8_4_sram[3]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.812359e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_4_sram[3]:8 0.152 +1 mux_tree_tapbuf_size8_4_sram[3]:3 mux_bottom_ipin_10\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_4_sram[3]:4 mem_bottom_ipin_10\/FTB_14__53:A 0.152 +3 mux_tree_tapbuf_size8_4_sram[3]:4 mux_tree_tapbuf_size8_4_sram[3]:3 0.001165179 +4 mux_tree_tapbuf_size8_4_sram[3]:5 mux_tree_tapbuf_size8_4_sram[3]:4 0.0045 +5 mux_tree_tapbuf_size8_4_sram[3]:7 mux_tree_tapbuf_size8_4_sram[3]:6 0.0045 +6 mux_tree_tapbuf_size8_4_sram[3]:6 mux_tree_tapbuf_size8_4_sram[3]:5 0.006901786 +7 mux_tree_tapbuf_size8_4_sram[3]:8 mux_tree_tapbuf_size8_4_sram[3]:7 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[0] 0.001249856 //LENGTH 9.905 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 87.245 47.600 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 84.815 49.980 +*I mux_bottom_ipin_15\/mux_l1_in_0_:S I *L 0.00357 *C 84.080 52.360 +*N mux_tree_tapbuf_size8_7_sram[0]:3 *C 84.118 52.360 +*N mux_tree_tapbuf_size8_7_sram[0]:4 *C 85.515 52.360 +*N mux_tree_tapbuf_size8_7_sram[0]:5 *C 85.560 52.315 +*N mux_tree_tapbuf_size8_7_sram[0]:6 *C 84.853 49.980 +*N mux_tree_tapbuf_size8_7_sram[0]:7 *C 85.515 49.980 +*N mux_tree_tapbuf_size8_7_sram[0]:8 *C 85.560 49.980 +*N mux_tree_tapbuf_size8_7_sram[0]:9 *C 85.560 47.645 +*N mux_tree_tapbuf_size8_7_sram[0]:10 *C 85.605 47.600 +*N mux_tree_tapbuf_size8_7_sram[0]:11 *C 87.208 47.600 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_15\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_7_sram[0]:3 0.0001365611 +4 mux_tree_tapbuf_size8_7_sram[0]:4 0.0001365611 +5 mux_tree_tapbuf_size8_7_sram[0]:5 0.0001338856 +6 mux_tree_tapbuf_size8_7_sram[0]:6 8.225503e-05 +7 mux_tree_tapbuf_size8_7_sram[0]:7 8.225503e-05 +8 mux_tree_tapbuf_size8_7_sram[0]:8 0.00029935 +9 mux_tree_tapbuf_size8_7_sram[0]:9 0.0001323954 +10 mux_tree_tapbuf_size8_7_sram[0]:10 0.0001217962 +11 mux_tree_tapbuf_size8_7_sram[0]:11 0.0001217962 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_7_sram[0]:11 0.152 +1 mux_tree_tapbuf_size8_7_sram[0]:4 mux_tree_tapbuf_size8_7_sram[0]:3 0.001247768 +2 mux_tree_tapbuf_size8_7_sram[0]:5 mux_tree_tapbuf_size8_7_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size8_7_sram[0]:3 mux_bottom_ipin_15\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_7_sram[0]:7 mux_tree_tapbuf_size8_7_sram[0]:6 0.0005915179 +5 mux_tree_tapbuf_size8_7_sram[0]:8 mux_tree_tapbuf_size8_7_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size8_7_sram[0]:8 mux_tree_tapbuf_size8_7_sram[0]:5 0.002084821 +7 mux_tree_tapbuf_size8_7_sram[0]:6 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_7_sram[0]:10 mux_tree_tapbuf_size8_7_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size8_7_sram[0]:9 mux_tree_tapbuf_size8_7_sram[0]:8 0.002084821 +10 mux_tree_tapbuf_size8_7_sram[0]:11 mux_tree_tapbuf_size8_7_sram[0]:10 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_6_ccff_tail[0] 0.001126215 //LENGTH 8.080 LUMPCC 0.0003895498 DR + +*CONN +*I mem_bottom_ipin_14\/FTB_16__55:X O *L 0 *C 79.355 42.840 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 81.595 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 *C 81.595 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 *C 81.420 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 *C 81.420 47.895 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 *C 81.420 42.885 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 *C 81.375 42.840 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 *C 79.392 42.840 + +*CAP +0 mem_bottom_ipin_14\/FTB_16__55:X 1e-06 +1 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 4.747026e-05 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 5.171563e-05 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.0001570933 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0001570933 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 0.0001606462 +7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 0.0001606462 +8 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 prog_clk[0]:204 3.870658e-06 +9 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 prog_clk[0]:203 3.870658e-06 +10 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 prog_clk[0]:205 0.0001332481 +11 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 prog_clk[0]:209 4.046074e-06 +12 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 prog_clk[0]:209 0.0001332481 +13 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 prog_clk[0]:210 4.046074e-06 +14 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.361001e-05 +15 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 5.361001e-05 + +*RES +0 mem_bottom_ipin_14\/FTB_16__55:X mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 0.001770089 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.004473215 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001239889 //LENGTH 9.620 LUMPCC 0.0003298207 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_0_:X O *L 0 *C 62.275 61.200 +*I mux_bottom_ipin_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 55.660 63.580 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 55.660 63.580 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 55.660 63.535 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 55.660 61.245 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 55.705 61.200 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 62.238 61.200 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.033967e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001417779 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001417779 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002970865 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002970865 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_1_sram[1]:18 0.0001024466 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_1_sram[1]:20 6.132415e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_1_sram[1]:17 0.0001024466 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_1_sram[1]:19 6.132415e-05 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_1_sram[1]:15 1.723516e-07 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_1_sram[1]:16 9.672295e-07 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:12 9.672295e-07 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:16 1.723516e-07 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00583259 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002044643 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000388439 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_1_:X O *L 0 *C 65.035 17.340 +*I mux_bottom_ipin_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 62.390 17.340 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 62.428 17.340 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 64.998 17.340 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001932195 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001932195 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002294643 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004651608 //LENGTH 2.860 LUMPCC 0.0002122496 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_2_:X O *L 0 *C 55.835 47.260 +*I mux_bottom_ipin_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 53.265 47.260 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 53.303 47.260 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 55.797 47.260 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001254556 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001254556 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chanx_right_in[7]:19 0.0001061248 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[7]:20 0.0001061248 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_2_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001441981 //LENGTH 10.085 LUMPCC 0.0004548043 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_3_:X O *L 0 *C 6.725 31.960 +*I mux_bottom_ipin_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 9.320 37.060 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 9.320 37.060 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 6.025 37.060 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 5.980 37.015 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 5.980 32.005 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 6.025 31.960 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 6.688 31.960 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001973042 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001574292 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002362917 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002362917 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.893006e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.893006e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_right_in[0]:17 7.846268e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_right_in[0]:18 7.846268e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 ropt_net_151:8 9.735754e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 ropt_net_151:10 5.158195e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 ropt_net_151:9 9.735754e-05 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 ropt_net_151:11 5.158195e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_3_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005915179 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004473215 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002941964 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0005649815 //LENGTH 3.925 LUMPCC 0.0001594718 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l3_in_1_:X O *L 0 *C 11.325 63.920 +*I mux_bottom_ipin_9\/mux_l4_in_0_:A0 I *L 0.001631 *C 10.410 66.300 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 10.447 66.300 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 10.995 66.300 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 11.040 66.255 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 11.040 63.965 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 11.040 63.920 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 11.325 63.920 + +*CAP +0 mux_bottom_ipin_9\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.33894e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.33894e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001015007 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001015007 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.662684e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.710282e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 1.264011e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 1.264011e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.709577e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.709577e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l3_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_9\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0004888393 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002044643 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008104365 //LENGTH 6.050 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_2_:X O *L 0 *C 75.155 50.660 +*I mux_bottom_ipin_13\/mux_l2_in_1_:A1 I *L 0.00198 *C 75.345 56.100 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 75.345 56.100 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 75.440 56.055 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 75.440 50.705 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 75.440 50.660 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 75.155 50.660 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.162336e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003334263 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003334263 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.54754e-05 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.448506e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_2_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.004776786 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001548913 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004962375 //LENGTH 3.750 LUMPCC 7.753861e-05 DR + +*CONN +*I mux_top_ipin_0\/mux_l2_in_2_:X O *L 0 *C 86.305 17.000 +*I mux_top_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 85.660 14.620 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 85.560 14.620 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 85.560 14.665 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 85.560 16.955 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 85.605 17.000 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 86.267 17.000 + +*CAP +0 mux_top_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_top_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.359247e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001443002 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001443002 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.7253e-05 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 4.7253e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_8_sram[1]:24 3.87693e-05 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_8_sram[1]:25 3.87693e-05 + +*RES +0 mux_top_ipin_0\/mux_l2_in_2_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001184498 //LENGTH 8.835 LUMPCC 0.0002398003 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_2_:X O *L 0 *C 40.765 49.640 +*I mux_bottom_ipin_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 43.340 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 43.303 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 41.905 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 41.860 45.265 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 41.860 47.555 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 41.815 47.600 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 40.525 47.600 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 40.480 47.645 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 40.480 49.595 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 40.480 49.640 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 40.765 49.640 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.819855e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.819855e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001267731 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001267731 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001066905 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001066905 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.648952e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 9.648952e-05 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:10 5.44914e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:11 5.190329e-05 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:21 3.457713e-06 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:19 3.457713e-06 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size8_1_sram[1]:21 5.804658e-05 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size8_1_sram[1]:19 5.804658e-05 +16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_1_sram[2]:7 3.174563e-05 +17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_1_sram[2]:8 3.174563e-05 +18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_1_sram[2]:6 4.77519e-06 +19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_1_sram[2]:9 2.101084e-05 +20 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_1_sram[2]:9 4.77519e-06 +21 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_1_sram[2]:10 2.101084e-05 +22 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size8_1_sram[2]:9 8.641821e-07 +23 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size8_1_sram[2]:10 8.641821e-07 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_2_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001247768 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001151786 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001741071 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008332719 //LENGTH 5.625 LUMPCC 0.0002428684 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_3_:X O *L 0 *C 26.965 12.920 +*I mux_bottom_ipin_10\/mux_l3_in_1_:A0 I *L 0.001631 *C 26.050 17.000 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 26.088 17.000 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 26.635 17.000 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 26.680 16.955 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 26.680 12.965 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 26.680 12.920 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 26.965 12.920 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.796455e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.796455e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001709812 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001709812 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.596908e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.454288e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[6]:16 6.898954e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[6]:15 6.898954e-05 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.302881e-07 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.302881e-07 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.16144e-05 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.16144e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_3_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001928071 //LENGTH 15.720 LUMPCC 0.0003908389 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l3_in_1_:X O *L 0 *C 76.995 18.360 +*I mux_bottom_ipin_14\/mux_l4_in_0_:A0 I *L 0.001631 *C 78.485 31.960 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 78.448 31.960 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 77.325 31.960 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 77.280 31.915 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 77.280 18.405 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 77.280 18.360 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 76.995 18.360 + +*CAP +0 mux_bottom_ipin_14\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.655506e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.655506e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0006141165 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0006141165 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.155026e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.233854e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[0]:30 5.295566e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[0]:31 1.555074e-05 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[0]:22 5.295566e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[0]:30 1.555074e-05 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_6_sram[2]:10 6.752345e-05 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_6_sram[2]:13 5.938963e-05 +14 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_6_sram[2]:7 6.752345e-05 +15 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_6_sram[2]:10 5.938963e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l3_in_1_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0120625 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001002232 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_14\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET ropt_net_161 0.001214736 //LENGTH 8.260 LUMPCC 0.0001217842 DR + +*CONN +*I ropt_mt_inst_711:X O *L 0 *C 39.295 70.040 +*I ropt_mt_inst_764:A I *L 0.001767 *C 34.500 72.080 +*N ropt_net_161:2 *C 34.500 72.080 +*N ropt_net_161:3 *C 34.500 72.035 +*N ropt_net_161:4 *C 34.500 71.445 +*N ropt_net_161:5 *C 34.500 71.400 +*N ropt_net_161:6 *C 39.055 71.400 +*N ropt_net_161:7 *C 39.100 71.355 +*N ropt_net_161:8 *C 39.100 70.085 +*N ropt_net_161:9 *C 39.100 70.040 +*N ropt_net_161:10 *C 39.295 70.040 + +*CAP +0 ropt_mt_inst_711:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_161:2 3.540616e-05 +3 ropt_net_161:3 4.548454e-05 +4 ropt_net_161:4 4.548454e-05 +5 ropt_net_161:5 0.0003460946 +6 ropt_net_161:6 0.0003130644 +7 ropt_net_161:7 8.864286e-05 +8 ropt_net_161:8 8.864286e-05 +9 ropt_net_161:9 6.272123e-05 +10 ropt_net_161:10 6.541044e-05 +11 ropt_net_161:6 top_grid_pin_18_[0]:3 4.286064e-05 +12 ropt_net_161:5 top_grid_pin_18_[0]:4 4.286064e-05 +13 ropt_net_161:4 top_grid_pin_18_[0]:2 1.803144e-05 +14 ropt_net_161:3 top_grid_pin_18_[0] 1.803144e-05 + +*RES +0 ropt_mt_inst_711:X ropt_net_161:10 0.152 +1 ropt_net_161:10 ropt_net_161:9 0.0001059783 +2 ropt_net_161:9 ropt_net_161:8 0.0045 +3 ropt_net_161:8 ropt_net_161:7 0.001133929 +4 ropt_net_161:6 ropt_net_161:5 0.004066965 +5 ropt_net_161:7 ropt_net_161:6 0.0045 +6 ropt_net_161:5 ropt_net_161:4 0.0045 +7 ropt_net_161:4 ropt_net_161:3 0.0005267857 +8 ropt_net_161:2 ropt_mt_inst_764:A 0.152 +9 ropt_net_161:3 ropt_net_161:2 0.0045 + +*END + +*D_NET ropt_net_162 0.001355727 //LENGTH 9.780 LUMPCC 0.0004176084 DR + +*CONN +*I ropt_mt_inst_723:X O *L 0 *C 11.695 3.400 +*I ropt_mt_inst_765:A I *L 0.001767 *C 3.220 4.080 +*N ropt_net_162:2 *C 3.220 4.080 +*N ropt_net_162:3 *C 3.220 4.035 +*N ropt_net_162:4 *C 3.220 3.445 +*N ropt_net_162:5 *C 3.265 3.400 +*N ropt_net_162:6 *C 11.658 3.400 + +*CAP +0 ropt_mt_inst_723:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_162:2 2.801825e-05 +3 ropt_net_162:3 4.077857e-05 +4 ropt_net_162:4 4.077857e-05 +5 ropt_net_162:5 0.0004132718 +6 ropt_net_162:6 0.0004132718 +7 ropt_net_162:5 ropt_net_124:3 0.0001524531 +8 ropt_net_162:5 ropt_net_124:8 4.340353e-07 +9 ropt_net_162:6 ropt_net_124:4 0.0001524531 +10 ropt_net_162:6 ropt_net_124:7 4.340353e-07 +11 ropt_net_162:3 chanx_left_out[1]:2 9.333696e-06 +12 ropt_net_162:5 chanx_left_out[1]:3 4.658339e-05 +13 ropt_net_162:4 chanx_left_out[1] 9.333696e-06 +14 ropt_net_162:6 chanx_left_out[1]:4 4.658339e-05 + +*RES +0 ropt_mt_inst_723:X ropt_net_162:6 0.152 +1 ropt_net_162:2 ropt_mt_inst_765:A 0.152 +2 ropt_net_162:3 ropt_net_162:2 0.0045 +3 ropt_net_162:5 ropt_net_162:4 0.0045 +4 ropt_net_162:4 ropt_net_162:3 0.0005267857 +5 ropt_net_162:6 ropt_net_162:5 0.007493304 + +*END + +*D_NET mem_top_ipin_0/net_net_72 0.001252314 //LENGTH 11.475 LUMPCC 0.0002889447 DR + +*CONN +*I mem_top_ipin_0\/FTB_9__48:X O *L 0 *C 73.365 6.120 +*I mem_top_ipin_0\/BUFT_RR_93:A I *L 0.001767 *C 64.860 4.080 +*N mem_top_ipin_0/net_net_72:2 *C 64.898 4.080 +*N mem_top_ipin_0/net_net_72:3 *C 71.715 4.080 +*N mem_top_ipin_0/net_net_72:4 *C 71.760 4.125 +*N mem_top_ipin_0/net_net_72:5 *C 71.760 6.075 +*N mem_top_ipin_0/net_net_72:6 *C 71.805 6.120 +*N mem_top_ipin_0/net_net_72:7 *C 73.328 6.120 + +*CAP +0 mem_top_ipin_0\/FTB_9__48:X 1e-06 +1 mem_top_ipin_0\/BUFT_RR_93:A 1e-06 +2 mem_top_ipin_0/net_net_72:2 0.0002525636 +3 mem_top_ipin_0/net_net_72:3 0.0002525636 +4 mem_top_ipin_0/net_net_72:4 0.0001162427 +5 mem_top_ipin_0/net_net_72:5 0.0001162427 +6 mem_top_ipin_0/net_net_72:6 0.0001118784 +7 mem_top_ipin_0/net_net_72:7 0.0001118784 +8 mem_top_ipin_0/net_net_72:3 chanx_right_in[16]:16 0.0001444723 +9 mem_top_ipin_0/net_net_72:2 chanx_right_in[16]:15 0.0001444723 + +*RES +0 mem_top_ipin_0\/FTB_9__48:X mem_top_ipin_0/net_net_72:7 0.152 +1 mem_top_ipin_0/net_net_72:7 mem_top_ipin_0/net_net_72:6 0.001359375 +2 mem_top_ipin_0/net_net_72:6 mem_top_ipin_0/net_net_72:5 0.0045 +3 mem_top_ipin_0/net_net_72:5 mem_top_ipin_0/net_net_72:4 0.001741072 +4 mem_top_ipin_0/net_net_72:3 mem_top_ipin_0/net_net_72:2 0.006087054 +5 mem_top_ipin_0/net_net_72:4 mem_top_ipin_0/net_net_72:3 0.0045 +6 mem_top_ipin_0/net_net_72:2 mem_top_ipin_0\/BUFT_RR_93:A 0.152 + +*END + +*D_NET ropt_net_111 0.001994536 //LENGTH 16.230 LUMPCC 0.0001288544 DR + +*CONN +*I BUFT_P_92:X O *L 0 *C 14.065 7.480 +*I ropt_mt_inst_710:A I *L 0.001766 *C 3.220 12.240 +*N ropt_net_111:2 *C 3.220 12.240 +*N ropt_net_111:3 *C 3.220 12.195 +*N ropt_net_111:4 *C 3.220 7.525 +*N ropt_net_111:5 *C 3.265 7.480 +*N ropt_net_111:6 *C 14.027 7.480 + +*CAP +0 BUFT_P_92:X 1e-06 +1 ropt_mt_inst_710:A 1e-06 +2 ropt_net_111:2 2.908172e-05 +3 ropt_net_111:3 0.0002587183 +4 ropt_net_111:4 0.0002587183 +5 ropt_net_111:5 0.0006585818 +6 ropt_net_111:6 0.0006585818 +7 ropt_net_111:5 chanx_right_in[16]:10 6.442718e-05 +8 ropt_net_111:6 chanx_right_in[16]:11 6.442718e-05 + +*RES +0 BUFT_P_92:X ropt_net_111:6 0.152 +1 ropt_net_111:2 ropt_mt_inst_710:A 0.152 +2 ropt_net_111:3 ropt_net_111:2 0.0045 +3 ropt_net_111:5 ropt_net_111:4 0.0045 +4 ropt_net_111:4 ropt_net_111:3 0.004169643 +5 ropt_net_111:6 ropt_net_111:5 0.009609376 + +*END + +*D_NET ropt_net_160 0.001188324 //LENGTH 9.385 LUMPCC 0.0002428158 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 11.695 9.860 +*I ropt_mt_inst_762:A I *L 0.001767 *C 3.220 9.520 +*N ropt_net_160:2 *C 3.258 9.520 +*N ropt_net_160:3 *C 4.600 9.520 +*N ropt_net_160:4 *C 4.600 9.860 +*N ropt_net_160:5 *C 11.658 9.860 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_160:2 8.380995e-05 +3 ropt_net_160:3 0.000107417 +4 ropt_net_160:4 0.0003879442 +5 ropt_net_160:5 0.0003643372 +6 ropt_net_160:5 chanx_right_in[3]:14 0.0001214079 +7 ropt_net_160:4 chanx_right_in[3]:15 0.0001214079 + +*RES +0 ropt_mt_inst_747:X ropt_net_160:5 0.152 +1 ropt_net_160:5 ropt_net_160:4 0.00630134 +2 ropt_net_160:2 ropt_mt_inst_762:A 0.152 +3 ropt_net_160:3 ropt_net_160:2 0.001198661 +4 ropt_net_160:4 ropt_net_160:3 0.0003035715 + +*END + +*D_NET chanx_left_in[5] 0.01798128 //LENGTH 118.250 LUMPCC 0.007516881 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 57.120 +*I mux_bottom_ipin_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 62.005 58.140 +*I mux_bottom_ipin_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 62.560 47.260 +*I FTB_6__5:A I *L 0.001767 *C 93.380 50.320 +*N chanx_left_in[5]:4 *C 93.418 50.320 +*N chanx_left_in[5]:5 *C 95.635 50.320 +*N chanx_left_in[5]:6 *C 95.680 50.275 +*N chanx_left_in[5]:7 *C 95.680 46.977 +*N chanx_left_in[5]:8 *C 95.672 46.920 +*N chanx_left_in[5]:9 *C 62.598 47.260 +*N chanx_left_in[5]:10 *C 63.895 47.260 +*N chanx_left_in[5]:11 *C 63.940 47.260 +*N chanx_left_in[5]:12 *C 63.940 46.920 +*N chanx_left_in[5]:13 *C 63.948 46.920 +*N chanx_left_in[5]:14 *C 63.508 46.928 +*N chanx_left_in[5]:15 *C 63.500 47.260 +*N chanx_left_in[5]:16 *C 63.480 47.268 +*N chanx_left_in[5]:17 *C 63.480 57.113 +*N chanx_left_in[5]:18 *C 63.460 57.120 +*N chanx_left_in[5]:19 *C 62.560 57.120 +*N chanx_left_in[5]:20 *C 62.043 58.140 +*N chanx_left_in[5]:21 *C 62.515 58.140 +*N chanx_left_in[5]:22 *C 62.560 58.140 +*N chanx_left_in[5]:23 *C 62.560 57.800 +*N chanx_left_in[5]:24 *C 62.560 57.793 +*N chanx_left_in[5]:25 *C 14.720 57.800 +*N chanx_left_in[5]:26 *C 14.720 57.120 + +*CAP +0 chanx_left_in[5] 0.0005808321 +1 mux_bottom_ipin_1\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_ipin_5\/mux_l1_in_2_:A1 1e-06 +3 FTB_6__5:A 1e-06 +4 chanx_left_in[5]:4 0.0001644733 +5 chanx_left_in[5]:5 0.0001644733 +6 chanx_left_in[5]:6 0.0001720581 +7 chanx_left_in[5]:7 0.0001720581 +8 chanx_left_in[5]:8 0.001382563 +9 chanx_left_in[5]:9 0.000150778 +10 chanx_left_in[5]:10 0.000150778 +11 chanx_left_in[5]:11 5.653743e-05 +12 chanx_left_in[5]:12 6.086038e-05 +13 chanx_left_in[5]:13 0.001423203 +14 chanx_left_in[5]:14 8.41002e-05 +15 chanx_left_in[5]:15 4.346123e-05 +16 chanx_left_in[5]:16 0.0004864575 +17 chanx_left_in[5]:17 0.0004864575 +18 chanx_left_in[5]:18 5.516168e-05 +19 chanx_left_in[5]:19 8.812018e-05 +20 chanx_left_in[5]:20 2.47476e-05 +21 chanx_left_in[5]:21 2.47476e-05 +22 chanx_left_in[5]:22 6.498499e-05 +23 chanx_left_in[5]:23 6.975311e-05 +24 chanx_left_in[5]:24 0.001932421 +25 chanx_left_in[5]:25 0.001970502 +26 chanx_left_in[5]:26 0.000651872 +27 chanx_left_in[5]:16 chanx_left_in[9]:15 0.0003333473 +28 chanx_left_in[5]:17 chanx_left_in[9]:14 0.0003333473 +29 chanx_left_in[5] chanx_left_in[11] 0.0001546752 +30 chanx_left_in[5] chanx_left_in[11]:24 2.106704e-05 +31 chanx_left_in[5]:18 chanx_left_in[11]:14 6.740239e-06 +32 chanx_left_in[5]:24 chanx_left_in[11]:23 0.0004095823 +33 chanx_left_in[5]:24 chanx_left_in[11]:19 0.0005243988 +34 chanx_left_in[5]:24 chanx_left_in[11]:14 9.286767e-05 +35 chanx_left_in[5]:26 chanx_left_in[11]:23 2.106704e-05 +36 chanx_left_in[5]:26 chanx_left_in[11]:27 0.0001546752 +37 chanx_left_in[5]:25 chanx_left_in[11]:23 0.0005243988 +38 chanx_left_in[5]:25 chanx_left_in[11]:19 9.286767e-05 +39 chanx_left_in[5]:25 chanx_left_in[11]:24 0.0004095823 +40 chanx_left_in[5]:19 chanx_left_in[11]:19 6.740239e-06 +41 chanx_left_in[5] chanx_left_in[13] 8.978401e-07 +42 chanx_left_in[5] chanx_left_in[13]:22 5.79579e-05 +43 chanx_left_in[5]:7 chanx_left_in[13]:6 3.509387e-05 +44 chanx_left_in[5]:6 chanx_left_in[13]:7 3.509387e-05 +45 chanx_left_in[5]:24 chanx_left_in[13]:17 0.0001685592 +46 chanx_left_in[5]:26 chanx_left_in[13]:21 5.79579e-05 +47 chanx_left_in[5]:26 chanx_left_in[13]:25 8.978401e-07 +48 chanx_left_in[5]:25 chanx_left_in[13]:21 0.0001685592 +49 chanx_left_in[5] chanx_left_in[19]:9 0.0001157803 +50 chanx_left_in[5]:8 chanx_left_in[19]:29 0.0003053373 +51 chanx_left_in[5]:8 chanx_left_in[19]:24 7.958763e-05 +52 chanx_left_in[5]:8 chanx_left_in[19]:30 0.0002188763 +53 chanx_left_in[5]:13 chanx_left_in[19]:29 7.958763e-05 +54 chanx_left_in[5]:13 chanx_left_in[19]:31 0.0002188763 +55 chanx_left_in[5]:13 chanx_left_in[19]:30 0.0003214337 +56 chanx_left_in[5]:24 chanx_left_in[19]:10 0.000166501 +57 chanx_left_in[5]:26 chanx_left_in[19]:10 0.0001157803 +58 chanx_left_in[5]:25 chanx_left_in[19]:9 0.000166501 +59 chanx_left_in[5]:14 chanx_left_in[19]:31 1.609642e-05 +60 chanx_left_in[5]:18 chanx_right_in[11]:30 6.610426e-05 +61 chanx_left_in[5]:24 chanx_right_in[11]:30 0.0003617972 +62 chanx_left_in[5]:25 chanx_right_in[11]:29 0.0003617972 +63 chanx_left_in[5]:19 chanx_right_in[11]:29 6.610426e-05 +64 chanx_left_in[5]:8 mux_tree_tapbuf_size10_1_sram[0]:22 0.0002218074 +65 chanx_left_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:21 0.0002218074 +66 chanx_left_in[5]:23 mux_tree_tapbuf_size10_1_sram[0]:11 4.506681e-08 +67 chanx_left_in[5]:24 mux_tree_tapbuf_size10_1_sram[0]:15 2.717679e-05 +68 chanx_left_in[5]:21 mux_tree_tapbuf_size10_1_sram[0]:14 3.191742e-05 +69 chanx_left_in[5]:22 mux_tree_tapbuf_size10_1_sram[0]:10 4.506681e-08 +70 chanx_left_in[5]:20 mux_tree_tapbuf_size10_1_sram[0]:13 3.191742e-05 +71 chanx_left_in[5]:19 mux_tree_tapbuf_size10_1_sram[0]:16 2.717679e-05 +72 chanx_left_in[5]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001990536 +73 chanx_left_in[5]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001990536 +74 chanx_left_in[5] ropt_net_157:5 0.0001431723 +75 chanx_left_in[5]:26 ropt_net_157:6 0.0001431723 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:26 0.002113433 +1 chanx_left_in[5]:7 chanx_left_in[5]:6 0.002944197 +2 chanx_left_in[5]:8 chanx_left_in[5]:7 0.00341 +3 chanx_left_in[5]:5 chanx_left_in[5]:4 0.001979911 +4 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0045 +5 chanx_left_in[5]:4 FTB_6__5:A 0.152 +6 chanx_left_in[5]:15 chanx_left_in[5]:14 4.596323e-05 +7 chanx_left_in[5]:16 chanx_left_in[5]:15 0.00341 +8 chanx_left_in[5]:18 chanx_left_in[5]:17 0.00341 +9 chanx_left_in[5]:17 chanx_left_in[5]:16 0.001542383 +10 chanx_left_in[5]:12 chanx_left_in[5]:11 0.0001634615 +11 chanx_left_in[5]:13 chanx_left_in[5]:12 0.00341 +12 chanx_left_in[5]:13 chanx_left_in[5]:8 0.00497025 +13 chanx_left_in[5]:10 chanx_left_in[5]:9 0.001158482 +14 chanx_left_in[5]:11 chanx_left_in[5]:10 0.0045 +15 chanx_left_in[5]:9 mux_bottom_ipin_5\/mux_l1_in_2_:A1 0.152 +16 chanx_left_in[5]:23 chanx_left_in[5]:22 0.0001634615 +17 chanx_left_in[5]:24 chanx_left_in[5]:23 0.00341 +18 chanx_left_in[5]:24 chanx_left_in[5]:19 0.0001053583 +19 chanx_left_in[5]:21 chanx_left_in[5]:20 0.000421875 +20 chanx_left_in[5]:22 chanx_left_in[5]:21 0.0045 +21 chanx_left_in[5]:20 mux_bottom_ipin_1\/mux_l1_in_2_:A1 0.152 +22 chanx_left_in[5]:26 chanx_left_in[5]:25 0.0001065333 +23 chanx_left_in[5]:25 chanx_left_in[5]:24 0.007494933 +24 chanx_left_in[5]:19 chanx_left_in[5]:18 0.000141 +25 chanx_left_in[5]:14 chanx_left_in[5]:13 6.565078e-05 + +*END + +*D_NET chanx_right_in[15] 0.01446257 //LENGTH 109.465 LUMPCC 0.003619566 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 103.575 39.440 +*I mux_bottom_ipin_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 54.280 45.220 +*I mux_bottom_ipin_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 39.200 45.220 +*I mux_bottom_ipin_11\/mux_l2_in_3_:A1 I *L 0.00198 *C 31.840 45.220 +*I FTB_36__35:A I *L 0.001776 *C 10.120 39.440 +*N chanx_right_in[15]:5 *C 10.120 39.440 +*N chanx_right_in[15]:6 *C 10.120 39.485 +*N chanx_right_in[15]:7 *C 10.120 42.102 +*N chanx_right_in[15]:8 *C 10.128 42.160 +*N chanx_right_in[15]:9 *C 31.733 42.160 +*N chanx_right_in[15]:10 *C 31.740 42.218 +*N chanx_right_in[15]:11 *C 31.740 45.220 +*N chanx_right_in[15]:12 *C 31.740 45.175 +*N chanx_right_in[15]:13 *C 31.740 45.560 +*N chanx_right_in[15]:14 *C 31.748 45.560 +*N chanx_right_in[15]:15 *C 39.100 45.220 +*N chanx_right_in[15]:16 *C 39.100 45.220 +*N chanx_right_in[15]:17 *C 39.100 45.560 +*N chanx_right_in[15]:18 *C 39.100 45.560 +*N chanx_right_in[15]:19 *C 53.812 45.560 +*N chanx_right_in[15]:20 *C 53.820 45.560 +*N chanx_right_in[15]:21 *C 54.242 45.220 +*N chanx_right_in[15]:22 *C 53.865 45.220 +*N chanx_right_in[15]:23 *C 53.820 45.175 +*N chanx_right_in[15]:24 *C 53.820 41.865 +*N chanx_right_in[15]:25 *C 53.865 41.820 +*N chanx_right_in[15]:26 *C 68.035 41.820 +*N chanx_right_in[15]:27 *C 68.080 41.775 +*N chanx_right_in[15]:28 *C 68.080 40.178 +*N chanx_right_in[15]:29 *C 68.088 40.120 +*N chanx_right_in[15]:30 *C 103.500 40.120 + +*CAP +0 chanx_right_in[15] 5.813444e-05 +1 mux_bottom_ipin_5\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_3_:A1 1e-06 +3 mux_bottom_ipin_11\/mux_l2_in_3_:A1 1e-06 +4 FTB_36__35:A 1e-06 +5 chanx_right_in[15]:5 3.226468e-05 +6 chanx_right_in[15]:6 0.0001336139 +7 chanx_right_in[15]:7 0.0001336139 +8 chanx_right_in[15]:8 0.00123391 +9 chanx_right_in[15]:9 0.00123391 +10 chanx_right_in[15]:10 0.0001841727 +11 chanx_right_in[15]:11 3.342803e-05 +12 chanx_right_in[15]:12 0.0002054447 +13 chanx_right_in[15]:13 5.999656e-05 +14 chanx_right_in[15]:14 0.0002966019 +15 chanx_right_in[15]:15 3.456285e-05 +16 chanx_right_in[15]:16 5.753295e-05 +17 chanx_right_in[15]:17 6.20947e-05 +18 chanx_right_in[15]:18 0.0008176467 +19 chanx_right_in[15]:19 0.0005210449 +20 chanx_right_in[15]:20 6.061224e-05 +21 chanx_right_in[15]:21 4.765123e-05 +22 chanx_right_in[15]:22 4.765123e-05 +23 chanx_right_in[15]:23 0.0001994271 +24 chanx_right_in[15]:24 0.0001784751 +25 chanx_right_in[15]:25 0.0007705323 +26 chanx_right_in[15]:26 0.0007705323 +27 chanx_right_in[15]:27 0.000103834 +28 chanx_right_in[15]:28 0.000103834 +29 chanx_right_in[15]:29 0.001700171 +30 chanx_right_in[15]:30 0.001758306 +31 chanx_right_in[15]:8 chanx_left_in[15] 0.0001194432 +32 chanx_right_in[15]:9 chanx_left_in[15]:28 0.0001194432 +33 chanx_right_in[15]:25 chanx_left_in[15]:14 5.658388e-06 +34 chanx_right_in[15]:24 chanx_left_in[15]:15 3.268182e-06 +35 chanx_right_in[15]:26 chanx_left_in[15]:13 5.658388e-06 +36 chanx_right_in[15]:29 chanx_left_in[15]:14 0.0001711604 +37 chanx_right_in[15]:23 chanx_left_in[15]:16 3.268182e-06 +38 chanx_right_in[15]:30 chanx_left_in[15]:13 0.0001711604 +39 chanx_right_in[15]:8 chanx_right_in[9]:15 2.583305e-06 +40 chanx_right_in[15]:9 chanx_right_in[9]:16 2.583305e-06 +41 chanx_right_in[15]:14 chanx_right_in[9]:15 0.0001698211 +42 chanx_right_in[15]:18 chanx_right_in[9]:15 0.0002936063 +43 chanx_right_in[15]:18 chanx_right_in[9]:16 0.0001698211 +44 chanx_right_in[15]:19 chanx_right_in[9]:16 0.0002936063 +45 chanx_right_in[15]:6 prog_clk[0]:273 3.219555e-05 +46 chanx_right_in[15]:7 prog_clk[0]:276 3.219555e-05 +47 chanx_right_in[15]:8 prog_clk[0]:350 1.01489e-05 +48 chanx_right_in[15]:8 prog_clk[0]:336 1.445813e-05 +49 chanx_right_in[15]:9 prog_clk[0]:350 1.445813e-05 +50 chanx_right_in[15]:9 prog_clk[0]:354 1.01489e-05 +51 chanx_right_in[15]:27 prog_clk[0]:200 2.874467e-08 +52 chanx_right_in[15]:28 prog_clk[0]:177 2.874467e-08 +53 chanx_right_in[15]:29 prog_clk[0]:157 0.0002099101 +54 chanx_right_in[15]:29 prog_clk[0]:163 0.0001556839 +55 chanx_right_in[15]:29 prog_clk[0]:162 7.444896e-05 +56 chanx_right_in[15]:30 prog_clk[0]:163 7.444896e-05 +57 chanx_right_in[15]:30 prog_clk[0]:162 0.0002099101 +58 chanx_right_in[15]:30 prog_clk[0]:153 0.0001556839 +59 chanx_right_in[15]:29 mux_tree_tapbuf_size10_0_sram[3]:11 0.0001879752 +60 chanx_right_in[15]:30 mux_tree_tapbuf_size10_0_sram[3]:12 0.0001879752 +61 chanx_right_in[15]:10 optlc_net_106:26 1.360011e-07 +62 chanx_right_in[15]:14 optlc_net_106:19 2.382635e-05 +63 chanx_right_in[15]:18 optlc_net_106:18 8.40061e-05 +64 chanx_right_in[15]:18 optlc_net_106:19 0.0002752507 +65 chanx_right_in[15]:12 optlc_net_106:25 1.360011e-07 +66 chanx_right_in[15]:19 optlc_net_106:18 0.0002752507 +67 chanx_right_in[15]:19 optlc_net_106:10 6.017975e-05 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:30 0.0001065333 +1 chanx_right_in[15]:5 FTB_36__35:A 0.152 +2 chanx_right_in[15]:6 chanx_right_in[15]:5 0.0045 +3 chanx_right_in[15]:7 chanx_right_in[15]:6 0.002337054 +4 chanx_right_in[15]:8 chanx_right_in[15]:7 0.00341 +5 chanx_right_in[15]:10 chanx_right_in[15]:9 0.00341 +6 chanx_right_in[15]:9 chanx_right_in[15]:8 0.003384783 +7 chanx_right_in[15]:25 chanx_right_in[15]:24 0.0045 +8 chanx_right_in[15]:24 chanx_right_in[15]:23 0.002955357 +9 chanx_right_in[15]:26 chanx_right_in[15]:25 0.01265179 +10 chanx_right_in[15]:27 chanx_right_in[15]:26 0.0045 +11 chanx_right_in[15]:28 chanx_right_in[15]:27 0.001426339 +12 chanx_right_in[15]:29 chanx_right_in[15]:28 0.00341 +13 chanx_right_in[15]:13 chanx_right_in[15]:12 0.0001850962 +14 chanx_right_in[15]:14 chanx_right_in[15]:13 0.00341 +15 chanx_right_in[15]:22 chanx_right_in[15]:21 0.0003370536 +16 chanx_right_in[15]:23 chanx_right_in[15]:22 0.0045 +17 chanx_right_in[15]:23 chanx_right_in[15]:20 0.0001850962 +18 chanx_right_in[15]:21 mux_bottom_ipin_5\/mux_l2_in_3_:A1 0.152 +19 chanx_right_in[15]:17 chanx_right_in[15]:16 0.0001634615 +20 chanx_right_in[15]:18 chanx_right_in[15]:17 0.00341 +21 chanx_right_in[15]:18 chanx_right_in[15]:14 0.001151892 +22 chanx_right_in[15]:15 mux_bottom_ipin_3\/mux_l2_in_3_:A1 0.152 +23 chanx_right_in[15]:16 chanx_right_in[15]:15 0.0045 +24 chanx_right_in[15]:11 mux_bottom_ipin_11\/mux_l2_in_3_:A1 0.152 +25 chanx_right_in[15]:12 chanx_right_in[15]:11 0.0045 +26 chanx_right_in[15]:12 chanx_right_in[15]:10 0.002640625 +27 chanx_right_in[15]:20 chanx_right_in[15]:19 0.00341 +28 chanx_right_in[15]:19 chanx_right_in[15]:18 0.002304958 +29 chanx_right_in[15]:30 chanx_right_in[15]:29 0.005547958 + +*END + +*D_NET prog_clk[0] 0.08871355 //LENGTH 644.025 LUMPCC 0.0161721 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 90.620 74.870 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 84.400 72.080 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 62.365 69.360 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 58.685 63.920 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 50.405 66.640 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 50.405 58.480 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 40.285 36.720 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 40.745 28.560 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 37.065 39.440 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 30.625 36.720 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 30.625 31.280 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 26.945 25.840 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 28.325 39.440 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.805 39.440 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 42.125 42.160 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 49.025 36.720 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.645 31.280 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 45.805 50.320 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 43.505 69.360 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.525 63.920 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 37.065 61.200 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 27.865 66.640 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 28.785 63.920 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 19.585 69.360 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 9.925 47.600 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 11.305 42.160 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 10.845 39.440 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 19.585 44.880 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 19.585 39.440 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 19.585 36.720 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 11.745 34.000 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 14.985 25.840 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 20.505 31.280 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 12.225 63.920 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 14.065 61.200 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 6.705 69.360 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 74.785 66.640 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 76.625 61.200 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 83.525 66.640 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 89.045 47.600 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 83.525 50.320 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 80.305 47.600 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 81.685 42.160 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 57.765 36.720 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 54.545 39.440 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 63.285 39.440 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.145 44.880 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 72.485 44.880 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 71.105 34.000 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 72.025 39.440 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.505 50.320 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.045 36.720 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 84.905 39.440 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 93.645 39.440 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 72.945 9.520 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.965 12.240 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 58.225 9.520 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 49.945 12.240 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 40.285 12.240 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.685 14.960 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.545 12.240 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 23.265 9.520 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 14.525 9.520 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 16.825 14.960 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 48.565 14.960 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 78.465 6.800 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.865 25.840 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 92.725 14.960 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 89.135 12.240 +*N prog_clk[0]:69 *C 89.135 12.240 +*N prog_clk[0]:70 *C 89.240 12.285 +*N prog_clk[0]:71 *C 89.240 13.600 +*N prog_clk[0]:72 *C 92.725 14.960 +*N prog_clk[0]:73 *C 92.920 14.960 +*N prog_clk[0]:74 *C 92.920 14.915 +*N prog_clk[0]:75 *C 92.920 13.658 +*N prog_clk[0]:76 *C 92.913 13.600 +*N prog_clk[0]:77 *C 90.168 13.600 +*N prog_clk[0]:78 *C 90.160 13.658 +*N prog_clk[0]:79 *C 73.865 25.840 +*N prog_clk[0]:80 *C 74.060 25.840 +*N prog_clk[0]:81 *C 74.060 25.840 +*N prog_clk[0]:82 *C 74.068 25.840 +*N prog_clk[0]:83 *C 78.465 6.800 +*N prog_clk[0]:84 *C 78.200 6.800 +*N prog_clk[0]:85 *C 78.200 6.845 +*N prog_clk[0]:86 *C 78.200 14.223 +*N prog_clk[0]:87 *C 78.193 14.280 +*N prog_clk[0]:88 *C 48.565 14.960 +*N prog_clk[0]:89 *C 48.300 14.960 +*N prog_clk[0]:90 *C 16.788 14.960 +*N prog_clk[0]:91 *C 14.765 14.960 +*N prog_clk[0]:92 *C 14.720 14.915 +*N prog_clk[0]:93 *C 14.525 9.520 +*N prog_clk[0]:94 *C 14.720 9.520 +*N prog_clk[0]:95 *C 14.720 9.565 +*N prog_clk[0]:96 *C 14.720 14.280 +*N prog_clk[0]:97 *C 14.728 14.280 +*N prog_clk[0]:98 *C 23.265 9.520 +*N prog_clk[0]:99 *C 23.000 9.520 +*N prog_clk[0]:100 *C 23.000 9.565 +*N prog_clk[0]:101 *C 23.000 14.223 +*N prog_clk[0]:102 *C 23.000 14.280 +*N prog_clk[0]:103 *C 31.545 12.240 +*N prog_clk[0]:104 *C 31.280 12.240 +*N prog_clk[0]:105 *C 31.280 12.285 +*N prog_clk[0]:106 *C 31.280 14.223 +*N prog_clk[0]:107 *C 31.280 14.280 +*N prog_clk[0]:108 *C 35.685 14.960 +*N prog_clk[0]:109 *C 35.420 14.960 +*N prog_clk[0]:110 *C 35.420 14.915 +*N prog_clk[0]:111 *C 35.420 14.338 +*N prog_clk[0]:112 *C 35.420 14.280 +*N prog_clk[0]:113 *C 40.285 12.240 +*N prog_clk[0]:114 *C 40.020 12.240 +*N prog_clk[0]:115 *C 40.020 12.285 +*N prog_clk[0]:116 *C 40.020 14.223 +*N prog_clk[0]:117 *C 40.020 14.288 +*N prog_clk[0]:118 *C 40.020 14.960 +*N prog_clk[0]:119 *C 48.293 14.960 +*N prog_clk[0]:120 *C 48.300 14.960 +*N prog_clk[0]:121 *C 48.300 13.658 +*N prog_clk[0]:122 *C 48.308 13.600 +*N prog_clk[0]:123 *C 49.945 12.240 +*N prog_clk[0]:124 *C 50.140 12.240 +*N prog_clk[0]:125 *C 50.140 12.285 +*N prog_clk[0]:126 *C 50.140 13.543 +*N prog_clk[0]:127 *C 50.140 13.600 +*N prog_clk[0]:128 *C 58.225 9.520 +*N prog_clk[0]:129 *C 58.420 9.520 +*N prog_clk[0]:130 *C 58.420 9.565 +*N prog_clk[0]:131 *C 58.420 13.543 +*N prog_clk[0]:132 *C 58.420 13.600 +*N prog_clk[0]:133 *C 66.965 12.240 +*N prog_clk[0]:134 *C 67.160 12.240 +*N prog_clk[0]:135 *C 67.160 12.285 +*N prog_clk[0]:136 *C 67.160 13.543 +*N prog_clk[0]:137 *C 67.160 13.600 +*N prog_clk[0]:138 *C 72.945 9.520 +*N prog_clk[0]:139 *C 72.680 9.520 +*N prog_clk[0]:140 *C 72.680 9.565 +*N prog_clk[0]:141 *C 72.680 13.543 +*N prog_clk[0]:142 *C 72.680 13.607 +*N prog_clk[0]:143 *C 72.680 14.280 +*N prog_clk[0]:144 *C 76.360 14.280 +*N prog_clk[0]:145 *C 76.360 14.288 +*N prog_clk[0]:146 *C 76.360 25.832 +*N prog_clk[0]:147 *C 76.360 25.840 +*N prog_clk[0]:148 *C 90.153 25.840 +*N prog_clk[0]:149 *C 90.160 25.840 +*N prog_clk[0]:150 *C 93.608 39.440 +*N prog_clk[0]:151 *C 92.965 39.440 +*N prog_clk[0]:152 *C 92.920 39.440 +*N prog_clk[0]:153 *C 92.913 39.440 +*N prog_clk[0]:154 *C 84.905 39.440 +*N prog_clk[0]:155 *C 85.100 39.440 +*N prog_clk[0]:156 *C 85.100 39.440 +*N prog_clk[0]:157 *C 85.108 39.440 +*N prog_clk[0]:158 *C 89.045 36.720 +*N prog_clk[0]:159 *C 88.780 36.720 +*N prog_clk[0]:160 *C 88.780 36.765 +*N prog_clk[0]:161 *C 88.780 39.383 +*N prog_clk[0]:162 *C 88.780 39.440 +*N prog_clk[0]:163 *C 90.160 39.440 +*N prog_clk[0]:164 *C 90.160 39.440 +*N prog_clk[0]:165 *C 66.505 50.320 +*N prog_clk[0]:166 *C 66.700 50.320 +*N prog_clk[0]:167 *C 66.700 50.320 +*N prog_clk[0]:168 *C 66.708 50.320 +*N prog_clk[0]:169 *C 71.760 50.320 +*N prog_clk[0]:170 *C 72.025 39.440 +*N prog_clk[0]:171 *C 71.760 39.100 +*N prog_clk[0]:172 *C 71.730 39.130 +*N prog_clk[0]:173 *C 71.105 34.000 +*N prog_clk[0]:174 *C 71.300 34.000 +*N prog_clk[0]:175 *C 71.300 34.045 +*N prog_clk[0]:176 *C 71.300 39.440 +*N prog_clk[0]:177 *C 71.715 39.440 +*N prog_clk[0]:178 *C 72.448 44.880 +*N prog_clk[0]:179 *C 71.805 44.880 +*N prog_clk[0]:180 *C 59.145 44.880 +*N prog_clk[0]:181 *C 59.340 44.880 +*N prog_clk[0]:182 *C 59.340 44.880 +*N prog_clk[0]:183 *C 59.348 44.880 +*N prog_clk[0]:184 *C 63.285 39.440 +*N prog_clk[0]:185 *C 63.020 39.440 +*N prog_clk[0]:186 *C 54.545 39.440 +*N prog_clk[0]:187 *C 54.740 39.440 +*N prog_clk[0]:188 *C 54.740 39.440 +*N prog_clk[0]:189 *C 54.748 39.440 +*N prog_clk[0]:190 *C 57.765 36.720 +*N prog_clk[0]:191 *C 57.500 36.720 +*N prog_clk[0]:192 *C 57.500 36.765 +*N prog_clk[0]:193 *C 57.500 39.383 +*N prog_clk[0]:194 *C 57.500 39.440 +*N prog_clk[0]:195 *C 63.013 39.440 +*N prog_clk[0]:196 *C 63.020 39.440 +*N prog_clk[0]:197 *C 63.020 44.823 +*N prog_clk[0]:198 *C 63.020 44.880 +*N prog_clk[0]:199 *C 71.752 44.880 +*N prog_clk[0]:200 *C 71.760 44.880 +*N prog_clk[0]:201 *C 71.760 49.583 +*N prog_clk[0]:202 *C 71.760 49.640 +*N prog_clk[0]:203 *C 81.648 42.160 +*N prog_clk[0]:204 *C 81.005 42.160 +*N prog_clk[0]:205 *C 80.960 42.205 +*N prog_clk[0]:206 *C 80.305 47.600 +*N prog_clk[0]:207 *C 80.500 47.940 +*N prog_clk[0]:208 *C 80.915 47.940 +*N prog_clk[0]:209 *C 80.960 47.940 +*N prog_clk[0]:210 *C 80.960 49.583 +*N prog_clk[0]:211 *C 80.960 49.648 +*N prog_clk[0]:212 *C 80.960 50.320 +*N prog_clk[0]:213 *C 83.525 50.320 +*N prog_clk[0]:214 *C 83.720 50.320 +*N prog_clk[0]:215 *C 83.720 50.320 +*N prog_clk[0]:216 *C 83.720 50.320 +*N prog_clk[0]:217 *C 89.045 47.600 +*N prog_clk[0]:218 *C 88.780 47.600 +*N prog_clk[0]:219 *C 88.780 47.645 +*N prog_clk[0]:220 *C 88.780 50.263 +*N prog_clk[0]:221 *C 88.780 50.320 +*N prog_clk[0]:222 *C 90.153 50.320 +*N prog_clk[0]:223 *C 90.160 50.320 +*N prog_clk[0]:224 *C 83.487 66.640 +*N prog_clk[0]:225 *C 82.845 66.640 +*N prog_clk[0]:226 *C 82.800 66.685 +*N prog_clk[0]:227 *C 76.625 61.200 +*N prog_clk[0]:228 *C 76.360 61.200 +*N prog_clk[0]:229 *C 76.360 61.245 +*N prog_clk[0]:230 *C 74.785 66.640 +*N prog_clk[0]:231 *C 74.980 66.640 +*N prog_clk[0]:232 *C 74.980 66.685 +*N prog_clk[0]:233 *C 6.705 69.360 +*N prog_clk[0]:234 *C 6.900 69.360 +*N prog_clk[0]:235 *C 6.900 69.360 +*N prog_clk[0]:236 *C 6.908 69.360 +*N prog_clk[0]:237 *C 14.065 61.200 +*N prog_clk[0]:238 *C 13.800 61.200 +*N prog_clk[0]:239 *C 13.800 61.245 +*N prog_clk[0]:240 *C 12.225 63.920 +*N prog_clk[0]:241 *C 12.420 63.920 +*N prog_clk[0]:242 *C 12.420 63.920 +*N prog_clk[0]:243 *C 12.428 63.920 +*N prog_clk[0]:244 *C 13.793 63.920 +*N prog_clk[0]:245 *C 13.800 63.920 +*N prog_clk[0]:246 *C 13.800 69.303 +*N prog_clk[0]:247 *C 13.800 69.360 +*N prog_clk[0]:248 *C 20.468 31.280 +*N prog_clk[0]:249 *C 19.365 31.280 +*N prog_clk[0]:250 *C 19.320 31.325 +*N prog_clk[0]:251 *C 14.948 25.840 +*N prog_clk[0]:252 *C 13.845 25.840 +*N prog_clk[0]:253 *C 13.800 25.885 +*N prog_clk[0]:254 *C 11.718 33.977 +*N prog_clk[0]:255 *C 11.500 33.965 +*N prog_clk[0]:256 *C 11.500 33.320 +*N prog_clk[0]:257 *C 13.755 33.320 +*N prog_clk[0]:258 *C 13.800 33.320 +*N prog_clk[0]:259 *C 13.808 33.320 +*N prog_clk[0]:260 *C 19.312 33.320 +*N prog_clk[0]:261 *C 19.320 33.320 +*N prog_clk[0]:262 *C 19.585 36.720 +*N prog_clk[0]:263 *C 19.320 37.060 +*N prog_clk[0]:264 *C 19.320 37.060 +*N prog_clk[0]:265 *C 19.585 39.440 +*N prog_clk[0]:266 *C 19.320 39.100 +*N prog_clk[0]:267 *C 19.320 39.100 +*N prog_clk[0]:268 *C 19.585 44.880 +*N prog_clk[0]:269 *C 19.320 44.540 +*N prog_clk[0]:270 *C 19.320 44.540 +*N prog_clk[0]:271 *C 10.845 39.440 +*N prog_clk[0]:272 *C 11.040 39.440 +*N prog_clk[0]:273 *C 11.040 39.485 +*N prog_clk[0]:274 *C 11.305 42.160 +*N prog_clk[0]:275 *C 11.040 42.500 +*N prog_clk[0]:276 *C 11.040 42.500 +*N prog_clk[0]:277 *C 9.925 47.600 +*N prog_clk[0]:278 *C 10.120 47.600 +*N prog_clk[0]:279 *C 10.120 47.600 +*N prog_clk[0]:280 *C 11.040 47.543 +*N prog_clk[0]:281 *C 11.048 47.600 +*N prog_clk[0]:282 *C 19.312 47.600 +*N prog_clk[0]:283 *C 19.320 47.600 +*N prog_clk[0]:284 *C 19.585 69.360 +*N prog_clk[0]:285 *C 19.320 69.360 +*N prog_clk[0]:286 *C 19.320 69.360 +*N prog_clk[0]:287 *C 19.320 69.353 +*N prog_clk[0]:288 *C 19.320 68.680 +*N prog_clk[0]:289 *C 28.785 63.920 +*N prog_clk[0]:290 *C 28.520 63.920 +*N prog_clk[0]:291 *C 28.520 63.965 +*N prog_clk[0]:292 *C 27.865 66.640 +*N prog_clk[0]:293 *C 28.060 66.300 +*N prog_clk[0]:294 *C 28.475 66.300 +*N prog_clk[0]:295 *C 28.520 66.300 +*N prog_clk[0]:296 *C 28.520 68.623 +*N prog_clk[0]:297 *C 28.520 68.680 +*N prog_clk[0]:298 *C 37.065 61.200 +*N prog_clk[0]:299 *C 37.260 61.200 +*N prog_clk[0]:300 *C 37.260 61.245 +*N prog_clk[0]:301 *C 37.525 63.920 +*N prog_clk[0]:302 *C 37.260 64.260 +*N prog_clk[0]:303 *C 37.260 64.260 +*N prog_clk[0]:304 *C 37.260 68.623 +*N prog_clk[0]:305 *C 37.260 68.688 +*N prog_clk[0]:306 *C 37.260 69.360 +*N prog_clk[0]:307 *C 43.505 69.360 +*N prog_clk[0]:308 *C 43.700 69.360 +*N prog_clk[0]:309 *C 43.700 69.360 +*N prog_clk[0]:310 *C 43.700 69.360 +*N prog_clk[0]:311 *C 49.220 69.360 +*N prog_clk[0]:312 *C 45.805 50.320 +*N prog_clk[0]:313 *C 46.000 50.320 +*N prog_clk[0]:314 *C 46.000 50.320 +*N prog_clk[0]:315 *C 46.008 50.320 +*N prog_clk[0]:316 *C 47.645 31.280 +*N prog_clk[0]:317 *C 47.840 31.280 +*N prog_clk[0]:318 *C 47.840 31.325 +*N prog_clk[0]:319 *C 47.840 36.663 +*N prog_clk[0]:320 *C 47.848 36.720 +*N prog_clk[0]:321 *C 49.213 36.720 +*N prog_clk[0]:322 *C 49.025 36.720 +*N prog_clk[0]:323 *C 49.220 36.720 +*N prog_clk[0]:324 *C 49.220 36.720 +*N prog_clk[0]:325 *C 49.220 42.102 +*N prog_clk[0]:326 *C 49.213 42.160 +*N prog_clk[0]:327 *C 42.125 42.160 +*N prog_clk[0]:328 *C 42.320 42.160 +*N prog_clk[0]:329 *C 42.320 42.160 +*N prog_clk[0]:330 *C 42.328 42.160 +*N prog_clk[0]:331 *C 45.768 39.440 +*N prog_clk[0]:332 *C 43.745 39.440 +*N prog_clk[0]:333 *C 28.325 39.440 +*N prog_clk[0]:334 *C 28.520 39.440 +*N prog_clk[0]:335 *C 28.520 39.440 +*N prog_clk[0]:336 *C 28.527 39.440 +*N prog_clk[0]:337 *C 26.945 25.840 +*N prog_clk[0]:338 *C 27.140 25.840 +*N prog_clk[0]:339 *C 27.140 25.840 +*N prog_clk[0]:340 *C 27.148 25.840 +*N prog_clk[0]:341 *C 30.812 25.840 +*N prog_clk[0]:342 *C 30.820 25.898 +*N prog_clk[0]:343 *C 30.625 31.280 +*N prog_clk[0]:344 *C 30.820 31.620 +*N prog_clk[0]:345 *C 30.820 31.620 +*N prog_clk[0]:346 *C 30.625 36.720 +*N prog_clk[0]:347 *C 30.820 37.060 +*N prog_clk[0]:348 *C 30.820 37.060 +*N prog_clk[0]:349 *C 30.820 39.383 +*N prog_clk[0]:350 *C 30.820 39.440 +*N prog_clk[0]:351 *C 37.065 39.440 +*N prog_clk[0]:352 *C 37.260 39.440 +*N prog_clk[0]:353 *C 37.260 39.440 +*N prog_clk[0]:354 *C 37.260 39.440 +*N prog_clk[0]:355 *C 40.745 28.560 +*N prog_clk[0]:356 *C 40.480 28.560 +*N prog_clk[0]:357 *C 40.480 28.605 +*N prog_clk[0]:358 *C 40.285 36.720 +*N prog_clk[0]:359 *C 40.480 37.060 +*N prog_clk[0]:360 *C 40.480 37.060 +*N prog_clk[0]:361 *C 40.480 39.383 +*N prog_clk[0]:362 *C 40.480 39.440 +*N prog_clk[0]:363 *C 43.693 39.440 +*N prog_clk[0]:364 *C 43.700 39.440 +*N prog_clk[0]:365 *C 43.700 42.102 +*N prog_clk[0]:366 *C 43.700 42.160 +*N prog_clk[0]:367 *C 46.920 42.160 +*N prog_clk[0]:368 *C 46.920 42.168 +*N prog_clk[0]:369 *C 46.920 50.312 +*N prog_clk[0]:370 *C 46.920 50.320 +*N prog_clk[0]:371 *C 49.213 50.320 +*N prog_clk[0]:372 *C 49.220 50.378 +*N prog_clk[0]:373 *C 50.367 58.480 +*N prog_clk[0]:374 *C 49.220 58.480 +*N prog_clk[0]:375 *C 49.220 58.820 +*N prog_clk[0]:376 *C 49.220 58.820 +*N prog_clk[0]:377 *C 50.367 66.640 +*N prog_clk[0]:378 *C 49.220 66.640 +*N prog_clk[0]:379 *C 49.220 66.300 +*N prog_clk[0]:380 *C 49.220 66.300 +*N prog_clk[0]:381 *C 49.220 68.623 +*N prog_clk[0]:382 *C 49.220 68.680 +*N prog_clk[0]:383 *C 58.685 63.920 +*N prog_clk[0]:384 *C 58.420 63.920 +*N prog_clk[0]:385 *C 58.420 63.965 +*N prog_clk[0]:386 *C 58.420 68.623 +*N prog_clk[0]:387 *C 58.420 68.688 +*N prog_clk[0]:388 *C 58.420 69.360 +*N prog_clk[0]:389 *C 62.365 69.360 +*N prog_clk[0]:390 *C 62.100 69.360 +*N prog_clk[0]:391 *C 62.100 69.360 +*N prog_clk[0]:392 *C 62.100 69.360 +*N prog_clk[0]:393 *C 74.980 69.360 +*N prog_clk[0]:394 *C 74.980 68.688 +*N prog_clk[0]:395 *C 74.980 68.680 +*N prog_clk[0]:396 *C 76.360 68.623 +*N prog_clk[0]:397 *C 76.368 68.680 +*N prog_clk[0]:398 *C 82.793 68.680 +*N prog_clk[0]:399 *C 82.800 68.680 +*N prog_clk[0]:400 *C 84.362 72.080 +*N prog_clk[0]:401 *C 82.845 72.080 +*N prog_clk[0]:402 *C 82.800 72.080 +*N prog_clk[0]:403 *C 82.808 72.080 +*N prog_clk[0]:404 *C 90.153 72.080 +*N prog_clk[0]:405 *C 90.160 72.080 +*N prog_clk[0]:406 *C 90.620 72.080 + +*CAP +0 prog_clk[0] 0.0001466158 +1 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +2 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +3 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +5 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +6 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +7 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +8 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +9 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +12 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +13 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +14 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +15 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +16 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +18 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +19 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +21 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +22 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +23 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +24 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +25 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +26 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +27 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +28 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +29 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +31 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +32 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +33 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +34 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +36 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +37 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +39 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +40 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +41 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +42 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +43 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +44 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +45 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +46 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +47 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +49 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +50 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +51 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +52 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +54 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +55 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +57 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +58 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +59 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +60 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +61 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +62 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +63 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +64 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +65 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +66 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +67 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +68 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +69 prog_clk[0]:69 2.933274e-05 +70 prog_clk[0]:70 8.386699e-05 +71 prog_clk[0]:71 0.0001451233 +72 prog_clk[0]:72 5.617488e-05 +73 prog_clk[0]:73 6.156505e-05 +74 prog_clk[0]:74 9.946264e-05 +75 prog_clk[0]:75 9.946264e-05 +76 prog_clk[0]:76 9.357449e-05 +77 prog_clk[0]:77 9.357449e-05 +78 prog_clk[0]:78 0.0007004098 +79 prog_clk[0]:79 5.532528e-05 +80 prog_clk[0]:80 5.754862e-05 +81 prog_clk[0]:81 4.117546e-05 +82 prog_clk[0]:82 0.0001814002 +83 prog_clk[0]:83 6.051207e-05 +84 prog_clk[0]:84 6.033534e-05 +85 prog_clk[0]:85 0.0004764881 +86 prog_clk[0]:86 0.0004764881 +87 prog_clk[0]:87 7.163468e-05 +88 prog_clk[0]:88 5.303789e-05 +89 prog_clk[0]:89 5.143768e-05 +90 prog_clk[0]:90 0.0001607075 +91 prog_clk[0]:91 0.0001607075 +92 prog_clk[0]:92 3.195614e-05 +93 prog_clk[0]:93 5.878201e-05 +94 prog_clk[0]:94 6.021309e-05 +95 prog_clk[0]:95 0.0002195123 +96 prog_clk[0]:96 0.0002896152 +97 prog_clk[0]:97 0.000378051 +98 prog_clk[0]:98 5.719456e-05 +99 prog_clk[0]:99 6.161616e-05 +100 prog_clk[0]:100 0.0002918398 +101 prog_clk[0]:101 0.0002918398 +102 prog_clk[0]:102 0.0007223606 +103 prog_clk[0]:103 6.702241e-05 +104 prog_clk[0]:104 6.643437e-05 +105 prog_clk[0]:105 0.0001464527 +106 prog_clk[0]:106 0.0001464527 +107 prog_clk[0]:107 0.0004704945 +108 prog_clk[0]:108 6.417661e-05 +109 prog_clk[0]:109 6.350711e-05 +110 prog_clk[0]:110 6.534597e-05 +111 prog_clk[0]:111 6.534597e-05 +112 prog_clk[0]:112 0.0002579726 +113 prog_clk[0]:113 5.464095e-05 +114 prog_clk[0]:114 5.558506e-05 +115 prog_clk[0]:115 0.0001275244 +116 prog_clk[0]:116 0.0001275244 +117 prog_clk[0]:117 0.0001822657 +118 prog_clk[0]:118 0.0003909226 +119 prog_clk[0]:119 0.0003404447 +120 prog_clk[0]:120 0.0001286166 +121 prog_clk[0]:121 9.123325e-05 +122 prog_clk[0]:122 7.538009e-05 +123 prog_clk[0]:123 6.215391e-05 +124 prog_clk[0]:124 6.129096e-05 +125 prog_clk[0]:125 9.202969e-05 +126 prog_clk[0]:126 9.202969e-05 +127 prog_clk[0]:127 0.0003044569 +128 prog_clk[0]:128 6.194664e-05 +129 prog_clk[0]:129 5.811044e-05 +130 prog_clk[0]:130 0.0002533702 +131 prog_clk[0]:131 0.0002533702 +132 prog_clk[0]:132 0.0005546225 +133 prog_clk[0]:133 4.959722e-05 +134 prog_clk[0]:134 5.38607e-05 +135 prog_clk[0]:135 9.582889e-05 +136 prog_clk[0]:136 9.582889e-05 +137 prog_clk[0]:137 0.0005055533 +138 prog_clk[0]:138 6.443306e-05 +139 prog_clk[0]:139 6.341954e-05 +140 prog_clk[0]:140 0.0002308424 +141 prog_clk[0]:141 0.0002308424 +142 prog_clk[0]:142 0.0002485176 +143 prog_clk[0]:143 0.0003354157 +144 prog_clk[0]:144 0.0003385403 +145 prog_clk[0]:145 0.0007876295 +146 prog_clk[0]:146 0.0007876295 +147 prog_clk[0]:147 0.0007425694 +148 prog_clk[0]:148 0.0005611692 +149 prog_clk[0]:149 0.001315661 +150 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3.203847e-06 +558 prog_clk[0]:144 chanx_right_in[14] 1.928361e-05 +559 prog_clk[0]:144 chanx_right_in[14]:31 1.400636e-05 +560 prog_clk[0]:122 chanx_right_in[14]:26 4.192224e-06 +561 prog_clk[0]:97 chanx_right_in[14]:17 8.716025e-05 +562 prog_clk[0]:119 chanx_right_in[14]:30 0.0001295416 +563 prog_clk[0]:87 chanx_right_in[14] 1.400636e-05 +564 prog_clk[0]:77 chanx_right_in[14]:31 1.619552e-05 +565 prog_clk[0]:76 chanx_right_in[14] 1.619552e-05 +566 prog_clk[0]:117 chanx_right_in[14]:30 5.158932e-05 +567 prog_clk[0]:106 chanx_right_in[14]:25 2.956127e-08 +568 prog_clk[0]:107 chanx_right_in[14]:22 4.28732e-05 +569 prog_clk[0]:107 chanx_right_in[14]:26 7.719224e-05 +570 prog_clk[0]:105 chanx_right_in[14]:24 2.956127e-08 +571 prog_clk[0]:112 chanx_right_in[14]:26 6.735179e-05 +572 prog_clk[0]:112 chanx_right_in[14]:30 3.245698e-05 +573 prog_clk[0]:127 chanx_right_in[14]:26 5.553264e-05 +574 prog_clk[0]:127 chanx_right_in[14]:30 4.192224e-06 +575 prog_clk[0]:132 chanx_right_in[14]:26 5.918102e-05 +576 prog_clk[0]:132 chanx_right_in[14]:30 5.553264e-05 +577 prog_clk[0]:137 chanx_right_in[14]:26 2.955275e-05 +578 prog_clk[0]:137 chanx_right_in[14]:30 5.918102e-05 +579 prog_clk[0]:137 chanx_right_in[14]:31 3.342319e-06 +580 prog_clk[0]:142 chanx_right_in[14] 3.342319e-06 +581 prog_clk[0]:142 chanx_right_in[14]:30 2.955275e-05 +582 prog_clk[0]:101 chanx_right_in[14]:21 1.362812e-06 +583 prog_clk[0]:102 chanx_right_in[14]:17 2.711074e-05 +584 prog_clk[0]:102 chanx_right_in[14]:22 0.0001318955 +585 prog_clk[0]:100 chanx_right_in[14]:20 1.362812e-06 +586 prog_clk[0]:118 chanx_right_in[14]:26 0.0001295416 +587 prog_clk[0]:143 chanx_right_in[14]:31 1.928361e-05 +588 prog_clk[0]:157 chanx_right_in[15]:29 0.0002099101 +589 prog_clk[0]:200 chanx_right_in[15]:27 2.874467e-08 +590 prog_clk[0]:163 chanx_right_in[15]:29 0.0001556839 +591 prog_clk[0]:163 chanx_right_in[15]:30 7.444896e-05 +592 prog_clk[0]:350 chanx_right_in[15]:8 1.01489e-05 +593 prog_clk[0]:350 chanx_right_in[15]:9 1.445813e-05 +594 prog_clk[0]:276 chanx_right_in[15]:7 3.219555e-05 +595 prog_clk[0]:354 chanx_right_in[15]:9 1.01489e-05 +596 prog_clk[0]:273 chanx_right_in[15]:6 3.219555e-05 +597 prog_clk[0]:162 chanx_right_in[15]:29 7.444896e-05 +598 prog_clk[0]:162 chanx_right_in[15]:30 0.0002099101 +599 prog_clk[0]:336 chanx_right_in[15]:8 1.445813e-05 +600 prog_clk[0]:153 chanx_right_in[15]:30 0.0001556839 +601 prog_clk[0]:177 chanx_right_in[15]:28 2.874467e-08 +602 prog_clk[0]:280 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0001208904 +603 prog_clk[0]:276 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0001208904 +604 prog_clk[0]:200 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 2.613196e-05 +605 prog_clk[0]:200 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 4.1877e-05 +606 prog_clk[0]:201 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 2.613196e-05 +607 prog_clk[0]:202 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 1.893068e-05 +608 prog_clk[0]:175 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 1.663117e-06 +609 prog_clk[0]:172 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 4.519291e-06 +610 prog_clk[0]:176 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 1.663117e-06 +611 prog_clk[0]:177 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 4.1877e-05 +612 prog_clk[0]:177 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 4.519291e-06 +613 prog_clk[0]:169 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 1.893068e-05 +614 prog_clk[0]:325 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 6.354707e-05 +615 prog_clk[0]:324 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 6.354707e-05 +616 prog_clk[0]:319 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 1.00724e-09 +617 prog_clk[0]:318 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 1.00724e-09 +618 prog_clk[0]:357 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 5.651472e-05 +619 prog_clk[0]:349 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 3.217591e-06 +620 prog_clk[0]:347 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 1.68982e-06 +621 prog_clk[0]:348 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 3.217591e-06 +622 prog_clk[0]:348 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 7.754394e-06 +623 prog_clk[0]:346 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 1.68982e-06 +624 prog_clk[0]:345 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 7.754394e-06 +625 prog_clk[0]:360 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 5.651472e-05 +626 prog_clk[0]:204 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 3.870658e-06 +627 prog_clk[0]:205 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0001332481 +628 prog_clk[0]:203 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 3.870658e-06 +629 prog_clk[0]:210 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 4.046074e-06 +630 prog_clk[0]:209 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 4.046074e-06 +631 prog_clk[0]:209 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.0001332481 +632 prog_clk[0]:164 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 2.483304e-06 +633 prog_clk[0]:223 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 2.483304e-06 +634 prog_clk[0]:220 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:5 6.517977e-05 +635 prog_clk[0]:218 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:3 1.381156e-05 +636 prog_clk[0]:219 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:4 6.517977e-05 +637 prog_clk[0]:217 mux_tree_tapbuf_size8_mem_7_ccff_tail[0]:2 1.381156e-05 +638 prog_clk[0]:164 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.934539e-05 +639 prog_clk[0]:149 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.032203e-05 +640 prog_clk[0]:149 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.934539e-05 +641 prog_clk[0]:78 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.032203e-05 +642 prog_clk[0]:398 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 2.198703e-05 +643 prog_clk[0]:397 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 2.198703e-05 +644 prog_clk[0]:205 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 1.099978e-05 +645 prog_clk[0]:211 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 7.273912e-06 +646 prog_clk[0]:392 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001460662 +647 prog_clk[0]:392 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.554625e-06 +648 prog_clk[0]:209 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 1.099978e-05 +649 prog_clk[0]:394 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.370751e-06 +650 prog_clk[0]:388 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.554625e-06 +651 prog_clk[0]:393 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001460662 +652 prog_clk[0]:393 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.370751e-06 +653 prog_clk[0]:212 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 7.273912e-06 +654 prog_clk[0]:296 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.810555e-06 +655 prog_clk[0]:297 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001620642 +656 prog_clk[0]:305 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001620642 +657 prog_clk[0]:372 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 2.705011e-06 +658 prog_clk[0]:295 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 3.810555e-06 +659 prog_clk[0]:376 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 2.705011e-06 +660 prog_clk[0]:376 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 9.26975e-07 +661 prog_clk[0]:310 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.090553e-05 +662 prog_clk[0]:310 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 8.322529e-05 +663 prog_clk[0]:380 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 9.26975e-07 +664 prog_clk[0]:306 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.322529e-05 +665 prog_clk[0]:311 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 4.090553e-05 +666 prog_clk[0]:283 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.721596e-05 +667 prog_clk[0]:286 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.721596e-05 +668 prog_clk[0]:297 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.776232e-05 +669 prog_clk[0]:305 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.776232e-05 +670 prog_clk[0]:305 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 5.33058e-06 +671 prog_clk[0]:310 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001477014 +672 prog_clk[0]:306 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001477014 +673 prog_clk[0]:306 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 5.33058e-06 +674 prog_clk[0]:223 ropt_net_116:6 0.0002237622 +675 prog_clk[0]:405 ropt_net_116:5 0.0002237622 +676 prog_clk[0]:405 ropt_net_116:3 7.444408e-06 +677 prog_clk[0]:406 ropt_net_116:4 7.444408e-06 +678 prog_clk[0]:280 ropt_net_168:5 6.534745e-05 +679 prog_clk[0]:276 ropt_net_168:4 5.556409e-05 +680 prog_clk[0]:278 ropt_net_168:7 7.16977e-07 +681 prog_clk[0]:279 ropt_net_168:6 9.783362e-06 +682 prog_clk[0]:277 ropt_net_168:8 7.16977e-07 + +*RES +0 prog_clk[0] prog_clk[0]:406 0.002491071 +1 prog_clk[0]:156 prog_clk[0]:155 0.0045 +2 prog_clk[0]:157 prog_clk[0]:156 0.00341 +3 prog_clk[0]:155 prog_clk[0]:154 0.0001059783 +4 prog_clk[0]:154 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +5 prog_clk[0]:251 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +6 prog_clk[0]:252 prog_clk[0]:251 0.000984375 +7 prog_clk[0]:253 prog_clk[0]:252 0.0045 +8 prog_clk[0]:248 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +9 prog_clk[0]:249 prog_clk[0]:248 0.0009843751 +10 prog_clk[0]:250 prog_clk[0]:249 0.0045 +11 prog_clk[0]:258 prog_clk[0]:257 0.0045 +12 prog_clk[0]:258 prog_clk[0]:253 0.006638393 +13 prog_clk[0]:259 prog_clk[0]:258 0.00341 +14 prog_clk[0]:261 prog_clk[0]:260 0.00341 +15 prog_clk[0]:261 prog_clk[0]:250 0.00178125 +16 prog_clk[0]:260 prog_clk[0]:259 0.0008624499 +17 prog_clk[0]:200 prog_clk[0]:199 0.00341 +18 prog_clk[0]:200 prog_clk[0]:179 0.0045 +19 prog_clk[0]:200 prog_clk[0]:177 0.004857143 +20 prog_clk[0]:199 prog_clk[0]:198 0.001368092 +21 prog_clk[0]:144 prog_clk[0]:143 0.0005765333 +22 prog_clk[0]:144 prog_clk[0]:87 0.0002870917 +23 prog_clk[0]:145 prog_clk[0]:144 0.00341 +24 prog_clk[0]:147 prog_clk[0]:146 0.00341 +25 prog_clk[0]:147 prog_clk[0]:82 0.0003591583 +26 prog_clk[0]:146 prog_clk[0]:145 0.001808716 +27 prog_clk[0]:399 prog_clk[0]:398 0.00341 +28 prog_clk[0]:399 prog_clk[0]:226 0.00178125 +29 prog_clk[0]:398 prog_clk[0]:397 0.001006583 +30 prog_clk[0]:396 prog_clk[0]:395 0.001232143 +31 prog_clk[0]:396 prog_clk[0]:229 0.006587054 +32 prog_clk[0]:397 prog_clk[0]:396 0.00341 +33 prog_clk[0]:283 prog_clk[0]:282 0.00341 +34 prog_clk[0]:283 prog_clk[0]:270 0.002732143 +35 prog_clk[0]:282 prog_clk[0]:281 0.00129485 +36 prog_clk[0]:280 prog_clk[0]:279 0.0008214287 +37 prog_clk[0]:280 prog_clk[0]:276 0.004502232 +38 prog_clk[0]:281 prog_clk[0]:280 0.00341 +39 prog_clk[0]:365 prog_clk[0]:364 0.002377232 +40 prog_clk[0]:366 prog_clk[0]:365 0.00341 +41 prog_clk[0]:366 prog_clk[0]:330 0.000215025 +42 prog_clk[0]:164 prog_clk[0]:163 0.00341 +43 prog_clk[0]:164 prog_clk[0]:149 0.01214286 +44 prog_clk[0]:163 prog_clk[0]:162 0.0002162 +45 prog_clk[0]:163 prog_clk[0]:153 0.000431225 +46 prog_clk[0]:286 prog_clk[0]:285 0.0045 +47 prog_clk[0]:286 prog_clk[0]:283 0.01942857 +48 prog_clk[0]:287 prog_clk[0]:286 0.00341 +49 prog_clk[0]:287 prog_clk[0]:247 0.0008648 +50 prog_clk[0]:356 prog_clk[0]:355 0.0001440218 +51 prog_clk[0]:357 prog_clk[0]:356 0.0045 +52 prog_clk[0]:355 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +53 prog_clk[0]:197 prog_clk[0]:196 0.004805804 +54 prog_clk[0]:198 prog_clk[0]:197 0.00341 +55 prog_clk[0]:198 prog_clk[0]:183 0.0005753583 +56 prog_clk[0]:364 prog_clk[0]:363 0.00341 +57 prog_clk[0]:364 prog_clk[0]:332 0.0045 +58 prog_clk[0]:363 prog_clk[0]:362 0.0005032917 +59 prog_clk[0]:91 prog_clk[0]:90 0.001805803 +60 prog_clk[0]:92 prog_clk[0]:91 0.0045 +61 prog_clk[0]:90 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +62 prog_clk[0]:149 prog_clk[0]:148 0.00341 +63 prog_clk[0]:149 prog_clk[0]:78 0.01087723 +64 prog_clk[0]:148 prog_clk[0]:147 0.002160825 +65 prog_clk[0]:296 prog_clk[0]:295 0.002073661 +66 prog_clk[0]:297 prog_clk[0]:296 0.00341 +67 prog_clk[0]:297 prog_clk[0]:288 0.001441333 +68 prog_clk[0]:349 prog_clk[0]:348 0.00207366 +69 prog_clk[0]:350 prog_clk[0]:349 0.00341 +70 prog_clk[0]:350 prog_clk[0]:336 0.0003591583 +71 prog_clk[0]:223 prog_clk[0]:222 0.00341 +72 prog_clk[0]:223 prog_clk[0]:164 0.009714287 +73 prog_clk[0]:222 prog_clk[0]:221 0.000215025 +74 prog_clk[0]:402 prog_clk[0]:401 0.0045 +75 prog_clk[0]:402 prog_clk[0]:399 0.003035714 +76 prog_clk[0]:403 prog_clk[0]:402 0.00341 +77 prog_clk[0]:405 prog_clk[0]:404 0.00341 +78 prog_clk[0]:405 prog_clk[0]:223 0.01942857 +79 prog_clk[0]:404 prog_clk[0]:403 0.001150717 +80 prog_clk[0]:196 prog_clk[0]:195 0.00341 +81 prog_clk[0]:196 prog_clk[0]:185 0.0045 +82 prog_clk[0]:195 prog_clk[0]:194 0.000863625 +83 prog_clk[0]:325 prog_clk[0]:324 0.004805803 +84 prog_clk[0]:326 prog_clk[0]:325 0.00341 +85 prog_clk[0]:361 prog_clk[0]:360 0.002073661 +86 prog_clk[0]:362 prog_clk[0]:361 0.00341 +87 prog_clk[0]:362 prog_clk[0]:354 0.0005044666 +88 prog_clk[0]:246 prog_clk[0]:245 0.004805804 +89 prog_clk[0]:247 prog_clk[0]:246 0.00341 +90 prog_clk[0]:247 prog_clk[0]:236 0.001079825 +91 prog_clk[0]:304 prog_clk[0]:303 0.003895089 +92 prog_clk[0]:305 prog_clk[0]:304 0.00341 +93 prog_clk[0]:305 prog_clk[0]:297 0.001369267 +94 prog_clk[0]:372 prog_clk[0]:371 0.00341 +95 prog_clk[0]:371 prog_clk[0]:370 0.0003591583 +96 prog_clk[0]:121 prog_clk[0]:120 0.001162947 +97 prog_clk[0]:122 prog_clk[0]:121 0.00341 +98 prog_clk[0]:204 prog_clk[0]:203 0.0005736608 +99 prog_clk[0]:205 prog_clk[0]:204 0.0045 +100 prog_clk[0]:203 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +101 prog_clk[0]:381 prog_clk[0]:380 0.002073661 +102 prog_clk[0]:382 prog_clk[0]:381 0.00341 +103 prog_clk[0]:382 prog_clk[0]:311 0.0001065333 +104 prog_clk[0]:210 prog_clk[0]:209 0.001466518 +105 prog_clk[0]:211 prog_clk[0]:210 0.00341 +106 prog_clk[0]:211 prog_clk[0]:202 0.001441333 +107 prog_clk[0]:81 prog_clk[0]:80 0.0045 +108 prog_clk[0]:82 prog_clk[0]:81 0.00341 +109 prog_clk[0]:80 prog_clk[0]:79 0.0001059783 +110 prog_clk[0]:79 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +111 prog_clk[0]:96 prog_clk[0]:95 0.004209822 +112 prog_clk[0]:96 prog_clk[0]:92 0.0005669643 +113 prog_clk[0]:97 prog_clk[0]:96 0.00341 +114 prog_clk[0]:120 prog_clk[0]:119 0.00341 +115 prog_clk[0]:120 prog_clk[0]:89 0.0045 +116 prog_clk[0]:119 prog_clk[0]:118 0.001296025 +117 prog_clk[0]:275 prog_clk[0]:274 0.0001847826 +118 prog_clk[0]:276 prog_clk[0]:275 0.0045 +119 prog_clk[0]:276 prog_clk[0]:273 0.002691964 +120 prog_clk[0]:274 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +121 prog_clk[0]:285 prog_clk[0]:284 0.0001440218 +122 prog_clk[0]:284 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +123 prog_clk[0]:294 prog_clk[0]:293 0.0003705357 +124 prog_clk[0]:295 prog_clk[0]:294 0.0045 +125 prog_clk[0]:295 prog_clk[0]:291 0.002084821 +126 prog_clk[0]:292 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +127 prog_clk[0]:290 prog_clk[0]:289 0.0001440218 +128 prog_clk[0]:291 prog_clk[0]:290 0.0045 +129 prog_clk[0]:289 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +130 prog_clk[0]:347 prog_clk[0]:346 0.0001847826 +131 prog_clk[0]:348 prog_clk[0]:347 0.0045 +132 prog_clk[0]:348 prog_clk[0]:345 0.004857143 +133 prog_clk[0]:346 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +134 prog_clk[0]:86 prog_clk[0]:85 0.006587055 +135 prog_clk[0]:87 prog_clk[0]:86 0.00341 +136 prog_clk[0]:84 prog_clk[0]:83 0.0001440218 +137 prog_clk[0]:85 prog_clk[0]:84 0.0045 +138 prog_clk[0]:83 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +139 prog_clk[0]:78 prog_clk[0]:77 0.00341 +140 prog_clk[0]:78 prog_clk[0]:71 0.0008214286 +141 prog_clk[0]:77 prog_clk[0]:76 0.00043005 +142 prog_clk[0]:75 prog_clk[0]:74 0.001122768 +143 prog_clk[0]:76 prog_clk[0]:75 0.00341 +144 prog_clk[0]:73 prog_clk[0]:72 0.0001059783 +145 prog_clk[0]:74 prog_clk[0]:73 0.0045 +146 prog_clk[0]:72 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +147 prog_clk[0]:116 prog_clk[0]:115 0.001729911 +148 prog_clk[0]:117 prog_clk[0]:116 0.00341 +149 prog_clk[0]:117 prog_clk[0]:112 0.0007206666 +150 prog_clk[0]:114 prog_clk[0]:113 0.0001440218 +151 prog_clk[0]:115 prog_clk[0]:114 0.0045 +152 prog_clk[0]:113 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +153 prog_clk[0]:220 prog_clk[0]:219 0.002337054 +154 prog_clk[0]:221 prog_clk[0]:220 0.00341 +155 prog_clk[0]:221 prog_clk[0]:216 0.0007927333 +156 prog_clk[0]:218 prog_clk[0]:217 0.0001440218 +157 prog_clk[0]:219 prog_clk[0]:218 0.0045 +158 prog_clk[0]:217 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +159 prog_clk[0]:89 prog_clk[0]:88 0.0001440218 +160 prog_clk[0]:88 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +161 prog_clk[0]:391 prog_clk[0]:390 0.0045 +162 prog_clk[0]:392 prog_clk[0]:391 0.00341 +163 prog_clk[0]:392 prog_clk[0]:388 0.0005765333 +164 prog_clk[0]:390 prog_clk[0]:389 0.0001440218 +165 prog_clk[0]:389 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +166 prog_clk[0]:231 prog_clk[0]:230 0.0001059783 +167 prog_clk[0]:232 prog_clk[0]:231 0.0045 +168 prog_clk[0]:230 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +169 prog_clk[0]:332 prog_clk[0]:331 0.001805804 +170 prog_clk[0]:331 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +171 prog_clk[0]:329 prog_clk[0]:328 0.0045 +172 prog_clk[0]:330 prog_clk[0]:329 0.00341 +173 prog_clk[0]:328 prog_clk[0]:327 0.0001059783 +174 prog_clk[0]:327 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +175 prog_clk[0]:228 prog_clk[0]:227 0.0001440218 +176 prog_clk[0]:229 prog_clk[0]:228 0.0045 +177 prog_clk[0]:227 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +178 prog_clk[0]:299 prog_clk[0]:298 0.0001059783 +179 prog_clk[0]:300 prog_clk[0]:299 0.0045 +180 prog_clk[0]:298 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +181 prog_clk[0]:167 prog_clk[0]:166 0.0045 +182 prog_clk[0]:168 prog_clk[0]:167 0.00341 +183 prog_clk[0]:166 prog_clk[0]:165 0.0001059783 +184 prog_clk[0]:165 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +185 prog_clk[0]:185 prog_clk[0]:184 0.0001440218 +186 prog_clk[0]:184 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +187 prog_clk[0]:353 prog_clk[0]:352 0.0045 +188 prog_clk[0]:354 prog_clk[0]:353 0.00341 +189 prog_clk[0]:354 prog_clk[0]:350 0.001008933 +190 prog_clk[0]:352 prog_clk[0]:351 0.0001059783 +191 prog_clk[0]:351 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +192 prog_clk[0]:193 prog_clk[0]:192 0.002337054 +193 prog_clk[0]:194 prog_clk[0]:193 0.00341 +194 prog_clk[0]:194 prog_clk[0]:189 0.000431225 +195 prog_clk[0]:191 prog_clk[0]:190 0.0001440218 +196 prog_clk[0]:192 prog_clk[0]:191 0.0045 +197 prog_clk[0]:190 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +198 prog_clk[0]:344 prog_clk[0]:343 0.0001847826 +199 prog_clk[0]:345 prog_clk[0]:344 0.0045 +200 prog_clk[0]:345 prog_clk[0]:342 0.005109375 +201 prog_clk[0]:343 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +202 prog_clk[0]:342 prog_clk[0]:341 0.00341 +203 prog_clk[0]:341 prog_clk[0]:340 0.0005741833 +204 prog_clk[0]:339 prog_clk[0]:338 0.0045 +205 prog_clk[0]:340 prog_clk[0]:339 0.00341 +206 prog_clk[0]:338 prog_clk[0]:337 0.0001059783 +207 prog_clk[0]:337 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +208 prog_clk[0]:359 prog_clk[0]:358 0.0001847826 +209 prog_clk[0]:360 prog_clk[0]:359 0.0045 +210 prog_clk[0]:360 prog_clk[0]:357 0.007549108 +211 prog_clk[0]:358 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +212 prog_clk[0]:106 prog_clk[0]:105 0.001729911 +213 prog_clk[0]:107 prog_clk[0]:106 0.00341 +214 prog_clk[0]:107 prog_clk[0]:102 0.0012972 +215 prog_clk[0]:104 prog_clk[0]:103 0.0001005435 +216 prog_clk[0]:105 prog_clk[0]:104 0.0045 +217 prog_clk[0]:103 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +218 prog_clk[0]:235 prog_clk[0]:234 0.0045 +219 prog_clk[0]:236 prog_clk[0]:235 0.00341 +220 prog_clk[0]:234 prog_clk[0]:233 0.0001059783 +221 prog_clk[0]:233 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +222 prog_clk[0]:111 prog_clk[0]:110 0.000515625 +223 prog_clk[0]:112 prog_clk[0]:111 0.00341 +224 prog_clk[0]:112 prog_clk[0]:107 0.0006485999 +225 prog_clk[0]:109 prog_clk[0]:108 0.0001440218 +226 prog_clk[0]:110 prog_clk[0]:109 0.0045 +227 prog_clk[0]:108 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +228 prog_clk[0]:245 prog_clk[0]:244 0.00341 +229 prog_clk[0]:245 prog_clk[0]:239 0.002388393 +230 prog_clk[0]:244 prog_clk[0]:243 0.00021385 +231 prog_clk[0]:242 prog_clk[0]:241 0.0045 +232 prog_clk[0]:243 prog_clk[0]:242 0.00341 +233 prog_clk[0]:241 prog_clk[0]:240 0.0001059783 +234 prog_clk[0]:240 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +235 prog_clk[0]:302 prog_clk[0]:301 0.0001847826 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0.0001059783 +254 prog_clk[0]:175 prog_clk[0]:174 0.0045 +255 prog_clk[0]:173 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +256 prog_clk[0]:69 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +257 prog_clk[0]:70 prog_clk[0]:69 0.0045 +258 prog_clk[0]:375 prog_clk[0]:374 0.0003035715 +259 prog_clk[0]:376 prog_clk[0]:375 0.0045 +260 prog_clk[0]:376 prog_clk[0]:372 0.007537947 +261 prog_clk[0]:373 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +262 prog_clk[0]:182 prog_clk[0]:181 0.0045 +263 prog_clk[0]:183 prog_clk[0]:182 0.00341 +264 prog_clk[0]:181 prog_clk[0]:180 0.0001059783 +265 prog_clk[0]:180 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +266 prog_clk[0]:188 prog_clk[0]:187 0.0045 +267 prog_clk[0]:189 prog_clk[0]:188 0.00341 +268 prog_clk[0]:187 prog_clk[0]:186 0.0001059783 +269 prog_clk[0]:186 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +270 prog_clk[0]:126 prog_clk[0]:125 0.001122768 +271 prog_clk[0]:127 prog_clk[0]:126 0.00341 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mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +291 prog_clk[0]:323 prog_clk[0]:322 0.0001059783 +292 prog_clk[0]:324 prog_clk[0]:323 0.0045 +293 prog_clk[0]:324 prog_clk[0]:321 0.00341 +294 prog_clk[0]:322 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +295 prog_clk[0]:401 prog_clk[0]:400 0.001354911 +296 prog_clk[0]:400 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +297 prog_clk[0]:309 prog_clk[0]:308 0.0045 +298 prog_clk[0]:310 prog_clk[0]:309 0.00341 +299 prog_clk[0]:310 prog_clk[0]:306 0.001008933 +300 prog_clk[0]:308 prog_clk[0]:307 0.0001059783 +301 prog_clk[0]:307 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +302 prog_clk[0]:215 prog_clk[0]:214 0.0045 +303 prog_clk[0]:216 prog_clk[0]:215 0.00341 +304 prog_clk[0]:216 prog_clk[0]:212 0.0004324 +305 prog_clk[0]:214 prog_clk[0]:213 0.0001059783 +306 prog_clk[0]:213 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +307 prog_clk[0]:379 prog_clk[0]:378 0.0003035715 +308 prog_clk[0]:380 prog_clk[0]:379 0.0045 +309 prog_clk[0]:380 prog_clk[0]:376 0.006678571 +310 prog_clk[0]:377 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +311 prog_clk[0]:208 prog_clk[0]:207 0.0003705357 +312 prog_clk[0]:209 prog_clk[0]:208 0.0045 +313 prog_clk[0]:209 prog_clk[0]:205 0.005120536 +314 prog_clk[0]:206 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +315 prog_clk[0]:386 prog_clk[0]:385 0.004158483 +316 prog_clk[0]:387 prog_clk[0]:386 0.00341 +317 prog_clk[0]:387 prog_clk[0]:382 0.001441333 +318 prog_clk[0]:384 prog_clk[0]:383 0.0001440218 +319 prog_clk[0]:385 prog_clk[0]:384 0.0045 +320 prog_clk[0]:383 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +321 prog_clk[0]:395 prog_clk[0]:394 0.00341 +322 prog_clk[0]:395 prog_clk[0]:232 0.00178125 +323 prog_clk[0]:394 prog_clk[0]:393 0.0001053583 +324 prog_clk[0]:179 prog_clk[0]:178 0.0005736608 +325 prog_clk[0]:178 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +326 prog_clk[0]:141 prog_clk[0]:140 0.003551339 +327 prog_clk[0]:142 prog_clk[0]:141 0.00341 +328 prog_clk[0]:142 prog_clk[0]:137 0.0008648 +329 prog_clk[0]:139 prog_clk[0]:138 0.0001440218 +330 prog_clk[0]:140 prog_clk[0]:139 0.0045 +331 prog_clk[0]:138 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +332 prog_clk[0]:314 prog_clk[0]:313 0.0045 +333 prog_clk[0]:315 prog_clk[0]:314 0.00341 +334 prog_clk[0]:313 prog_clk[0]:312 0.0001059783 +335 prog_clk[0]:312 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +336 prog_clk[0]:321 prog_clk[0]:320 0.00021385 +337 prog_clk[0]:319 prog_clk[0]:318 0.004765625 +338 prog_clk[0]:320 prog_clk[0]:319 0.00341 +339 prog_clk[0]:317 prog_clk[0]:316 0.0001059783 +340 prog_clk[0]:318 prog_clk[0]:317 0.0045 +341 prog_clk[0]:316 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +342 prog_clk[0]:171 prog_clk[0]:170 0.0001847826 +343 prog_clk[0]:172 prog_clk[0]:171 0.0045 +344 prog_clk[0]:170 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 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prog_clk[0]:268 0.0001847826 +364 prog_clk[0]:270 prog_clk[0]:269 0.0045 +365 prog_clk[0]:270 prog_clk[0]:267 0.004857142 +366 prog_clk[0]:268 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +367 prog_clk[0]:263 prog_clk[0]:262 0.0001847826 +368 prog_clk[0]:264 prog_clk[0]:263 0.0045 +369 prog_clk[0]:264 prog_clk[0]:261 0.003339286 +370 prog_clk[0]:262 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +371 prog_clk[0]:94 prog_clk[0]:93 0.0001059783 +372 prog_clk[0]:95 prog_clk[0]:94 0.0045 +373 prog_clk[0]:93 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +374 prog_clk[0]:101 prog_clk[0]:100 0.004158482 +375 prog_clk[0]:102 prog_clk[0]:101 0.00341 +376 prog_clk[0]:102 prog_clk[0]:97 0.001296025 +377 prog_clk[0]:99 prog_clk[0]:98 0.0001440218 +378 prog_clk[0]:100 prog_clk[0]:99 0.0045 +379 prog_clk[0]:98 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +380 prog_clk[0]:370 prog_clk[0]:369 0.00341 +381 prog_clk[0]:370 prog_clk[0]:315 0.0001429583 +382 prog_clk[0]:369 prog_clk[0]:368 0.00127605 +383 prog_clk[0]:367 prog_clk[0]:366 0.0005044666 +384 prog_clk[0]:367 prog_clk[0]:326 0.0003591583 +385 prog_clk[0]:368 prog_clk[0]:367 0.00341 +386 prog_clk[0]:256 prog_clk[0]:255 0.0005758929 +387 prog_clk[0]:255 prog_clk[0]:254 0.0001469595 +388 prog_clk[0]:293 prog_clk[0]:292 0.0003035715 +389 prog_clk[0]:374 prog_clk[0]:373 0.001024554 +390 prog_clk[0]:378 prog_clk[0]:377 0.001024554 +391 prog_clk[0]:207 prog_clk[0]:206 0.0003035715 +392 prog_clk[0]:176 prog_clk[0]:175 0.004816964 +393 prog_clk[0]:177 prog_clk[0]:176 0.0003705357 +394 prog_clk[0]:177 prog_clk[0]:172 0.00019375 +395 prog_clk[0]:71 prog_clk[0]:70 0.001174107 +396 prog_clk[0]:406 prog_clk[0]:405 0.0004107143 +397 prog_clk[0]:288 prog_clk[0]:287 0.0001053583 +398 prog_clk[0]:306 prog_clk[0]:305 0.0001053583 +399 prog_clk[0]:311 prog_clk[0]:310 0.0008648 +400 prog_clk[0]:118 prog_clk[0]:117 0.0001053583 +401 prog_clk[0]:388 prog_clk[0]:387 0.0001053583 +402 prog_clk[0]:393 prog_clk[0]:392 0.002017867 +403 prog_clk[0]:169 prog_clk[0]:168 0.0007915584 +404 prog_clk[0]:143 prog_clk[0]:142 0.0001053583 +405 prog_clk[0]:212 prog_clk[0]:211 0.0001053583 + +*END + +*D_NET chanx_left_in[4] 0.02548965 //LENGTH 162.750 LUMPCC 0.01060857 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 35.360 +*I mux_bottom_ipin_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 66.340 23.460 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 91.905 23.460 +*I mux_top_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 96.965 23.460 +*I FTB_5__4:A I *L 0.001776 *C 96.140 58.480 +*N chanx_left_in[4]:5 *C 96.103 58.480 +*N chanx_left_in[4]:6 *C 94.805 58.480 +*N chanx_left_in[4]:7 *C 94.760 58.525 +*N chanx_left_in[4]:8 *C 94.760 59.783 +*N chanx_left_in[4]:9 *C 94.752 59.840 +*N chanx_left_in[4]:10 *C 93.860 59.840 +*N chanx_left_in[4]:11 *C 93.840 59.833 +*N chanx_left_in[4]:12 *C 93.130 24.480 +*N chanx_left_in[4]:13 *C 96.928 23.460 +*N chanx_left_in[4]:14 *C 91.943 23.460 +*N chanx_left_in[4]:15 *C 93.840 23.460 +*N chanx_left_in[4]:16 *C 93.840 23.505 +*N chanx_left_in[4]:17 *C 93.840 24.422 +*N chanx_left_in[4]:18 *C 93.838 24.480 +*N chanx_left_in[4]:19 *C 93.840 24.488 +*N chanx_left_in[4]:20 *C 93.840 29.920 +*N chanx_left_in[4]:21 *C 93.820 29.920 +*N chanx_left_in[4]:22 *C 76.380 29.920 +*N chanx_left_in[4]:23 *C 76.360 29.913 +*N chanx_left_in[4]:24 *C 76.360 28.568 +*N chanx_left_in[4]:25 *C 76.340 28.560 +*N chanx_left_in[4]:26 *C 66.377 23.460 +*N chanx_left_in[4]:27 *C 68.035 23.460 +*N chanx_left_in[4]:28 *C 68.080 23.505 +*N chanx_left_in[4]:29 *C 68.080 28.503 +*N chanx_left_in[4]:30 *C 68.080 28.560 +*N chanx_left_in[4]:31 *C 67.180 28.560 +*N chanx_left_in[4]:32 *C 67.160 28.568 +*N chanx_left_in[4]:33 *C 67.160 37.392 +*N chanx_left_in[4]:34 *C 67.140 37.400 +*N chanx_left_in[4]:35 *C 14.728 37.400 +*N chanx_left_in[4]:36 *C 14.720 37.343 +*N chanx_left_in[4]:37 *C 14.720 35.418 +*N chanx_left_in[4]:38 *C 14.713 35.360 + +*CAP +0 chanx_left_in[4] 0.000567074 +1 mux_bottom_ipin_4\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_2_:A1 1e-06 +3 mux_top_ipin_0\/mux_l1_in_2_:A1 1e-06 +4 FTB_5__4:A 1e-06 +5 chanx_left_in[4]:5 0.0001246018 +6 chanx_left_in[4]:6 0.0001246018 +7 chanx_left_in[4]:7 6.607464e-05 +8 chanx_left_in[4]:8 6.607464e-05 +9 chanx_left_in[4]:9 9.779318e-05 +10 chanx_left_in[4]:10 9.779318e-05 +11 chanx_left_in[4]:11 0.001190392 +12 chanx_left_in[4]:12 0.0001108759 +13 chanx_left_in[4]:13 0.0002568932 +14 chanx_left_in[4]:14 0.0001632342 +15 chanx_left_in[4]:15 0.0004546272 +16 chanx_left_in[4]:16 7.349365e-05 +17 chanx_left_in[4]:17 7.349365e-05 +18 chanx_left_in[4]:18 0.0001108759 +19 chanx_left_in[4]:19 0.0002473793 +20 chanx_left_in[4]:20 0.001437772 +21 chanx_left_in[4]:21 0.0006180162 +22 chanx_left_in[4]:22 0.0006180162 +23 chanx_left_in[4]:23 0.0001202187 +24 chanx_left_in[4]:24 0.0001202187 +25 chanx_left_in[4]:25 0.0002726976 +26 chanx_left_in[4]:26 0.0001652496 +27 chanx_left_in[4]:27 0.0001652496 +28 chanx_left_in[4]:28 0.0002645852 +29 chanx_left_in[4]:29 0.0002645852 +30 chanx_left_in[4]:30 0.0003095848 +31 chanx_left_in[4]:31 3.688726e-05 +32 chanx_left_in[4]:32 0.0005094489 +33 chanx_left_in[4]:33 0.0005094489 +34 chanx_left_in[4]:34 0.002409104 +35 chanx_left_in[4]:35 0.002409104 +36 chanx_left_in[4]:36 0.000127277 +37 chanx_left_in[4]:37 0.000127277 +38 chanx_left_in[4]:38 0.000567074 +39 chanx_left_in[4]:34 chanx_left_in[6]:12 0.0003451736 +40 chanx_left_in[4]:35 chanx_left_in[6]:13 0.0003451736 +41 chanx_left_in[4] chanx_left_in[8] 6.705496e-05 +42 chanx_left_in[4] chanx_left_in[8]:17 0.0004708358 +43 chanx_left_in[4]:21 chanx_left_in[8]:11 0.00098478 +44 chanx_left_in[4]:22 chanx_left_in[8]:12 0.00098478 +45 chanx_left_in[4]:25 chanx_left_in[8]:11 0.0004617556 +46 chanx_left_in[4]:29 chanx_left_in[8]:13 4.491199e-05 +47 chanx_left_in[4]:30 chanx_left_in[8]:12 0.0004617556 +48 chanx_left_in[4]:30 chanx_left_in[8]:11 5.988804e-05 +49 chanx_left_in[4]:28 chanx_left_in[8]:6 4.491199e-05 +50 chanx_left_in[4]:31 chanx_left_in[8]:12 5.988804e-05 +51 chanx_left_in[4]:34 chanx_left_in[8]:16 0.0002168449 +52 chanx_left_in[4]:35 chanx_left_in[8]:17 0.0002168449 +53 chanx_left_in[4]:38 chanx_left_in[8]:26 6.705496e-05 +54 chanx_left_in[4]:38 chanx_left_in[8]:16 0.0004708358 +55 chanx_left_in[4]:10 chanx_left_in[10]:18 3.542008e-07 +56 chanx_left_in[4]:11 chanx_left_in[10]:19 0.0004865066 +57 chanx_left_in[4]:8 chanx_left_in[10]:15 4.084402e-05 +58 chanx_left_in[4]:9 chanx_left_in[10]:17 3.542008e-07 +59 chanx_left_in[4]:7 chanx_left_in[10]:16 4.084402e-05 +60 chanx_left_in[4]:20 chanx_left_in[10]:20 0.0004865066 +61 chanx_left_in[4] chanx_left_in[16] 6.851553e-05 +62 chanx_left_in[4]:21 chanx_left_in[16]:23 0.0004297575 +63 chanx_left_in[4]:22 chanx_left_in[16]:28 0.0004297575 +64 chanx_left_in[4]:30 chanx_left_in[16]:28 3.173399e-06 +65 chanx_left_in[4]:31 chanx_left_in[16]:29 3.173399e-06 +66 chanx_left_in[4]:38 chanx_left_in[16]:33 6.851553e-05 +67 chanx_left_in[4]:11 chanx_left_in[19]:23 0.0002027353 +68 chanx_left_in[4]:20 chanx_left_in[19]:23 5.892307e-05 +69 chanx_left_in[4]:20 chanx_left_in[19]:22 0.0002027353 +70 chanx_left_in[4]:19 chanx_left_in[19]:22 5.892307e-05 +71 chanx_left_in[4]:20 chanx_right_in[12]:32 6.71021e-05 +72 chanx_left_in[4]:25 chanx_right_in[12]:31 0.0002432753 +73 chanx_left_in[4]:18 chanx_right_in[12]:34 6.828415e-06 +74 chanx_left_in[4]:19 chanx_right_in[12]:33 6.71021e-05 +75 chanx_left_in[4]:29 chanx_right_in[12]:28 2.149434e-07 +76 chanx_left_in[4]:30 chanx_right_in[12]:30 0.0002432753 +77 chanx_left_in[4]:28 chanx_right_in[12]:27 2.149434e-07 +78 chanx_left_in[4]:12 chanx_right_in[12] 6.828415e-06 +79 chanx_left_in[4]:16 prog_clk[0]:78 5.860908e-08 +80 chanx_left_in[4]:17 prog_clk[0]:149 5.860908e-08 +81 chanx_left_in[4]:34 prog_clk[0]:366 6.500673e-07 +82 chanx_left_in[4]:34 prog_clk[0]:363 4.552109e-05 +83 chanx_left_in[4]:34 prog_clk[0]:350 1.783907e-05 +84 chanx_left_in[4]:34 prog_clk[0]:195 5.049658e-05 +85 chanx_left_in[4]:34 prog_clk[0]:326 8.759825e-06 +86 chanx_left_in[4]:34 prog_clk[0]:362 4.587579e-05 +87 chanx_left_in[4]:34 prog_clk[0]:354 0.000102073 +88 chanx_left_in[4]:34 prog_clk[0]:194 4.290554e-05 +89 chanx_left_in[4]:34 prog_clk[0]:321 9.593138e-05 +90 chanx_left_in[4]:34 prog_clk[0]:367 7.831775e-06 +91 chanx_left_in[4]:35 prog_clk[0]:366 7.831775e-06 +92 chanx_left_in[4]:35 prog_clk[0]:350 0.000102073 +93 chanx_left_in[4]:35 prog_clk[0]:362 4.552109e-05 +94 chanx_left_in[4]:35 prog_clk[0]:330 6.500673e-07 +95 chanx_left_in[4]:35 prog_clk[0]:354 4.587579e-05 +96 chanx_left_in[4]:35 prog_clk[0]:194 5.049658e-05 +97 chanx_left_in[4]:35 prog_clk[0]:189 4.290554e-05 +98 chanx_left_in[4]:35 prog_clk[0]:320 9.593138e-05 +99 chanx_left_in[4]:35 prog_clk[0]:336 1.783907e-05 +100 chanx_left_in[4]:35 prog_clk[0]:367 8.759825e-06 +101 chanx_left_in[4] mux_tree_tapbuf_size10_4_sram[3]:11 2.104859e-06 +102 chanx_left_in[4] mux_tree_tapbuf_size10_4_sram[3]:7 9.250214e-06 +103 chanx_left_in[4]:34 mux_tree_tapbuf_size10_4_sram[3]:12 0.0001406482 +104 chanx_left_in[4]:36 mux_tree_tapbuf_size10_4_sram[3]:10 4.546883e-07 +105 chanx_left_in[4]:35 mux_tree_tapbuf_size10_4_sram[3]:11 0.0001406482 +106 chanx_left_in[4]:37 mux_tree_tapbuf_size10_4_sram[3]:9 4.546883e-07 +107 chanx_left_in[4]:38 mux_tree_tapbuf_size10_4_sram[3]:11 9.250214e-06 +108 chanx_left_in[4]:38 mux_tree_tapbuf_size10_4_sram[3]:12 2.104859e-06 +109 chanx_left_in[4]:34 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.000184399 +110 chanx_left_in[4]:35 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.000184399 +111 chanx_left_in[4] mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0002900074 +112 chanx_left_in[4]:38 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0002900074 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:38 0.002112258 +1 chanx_left_in[4]:10 chanx_left_in[4]:9 0.000139825 +2 chanx_left_in[4]:11 chanx_left_in[4]:10 0.00341 +3 chanx_left_in[4]:8 chanx_left_in[4]:7 0.001122768 +4 chanx_left_in[4]:9 chanx_left_in[4]:8 0.00341 +5 chanx_left_in[4]:6 chanx_left_in[4]:5 0.001158482 +6 chanx_left_in[4]:7 chanx_left_in[4]:6 0.0045 +7 chanx_left_in[4]:5 FTB_5__4:A 0.152 +8 chanx_left_in[4]:21 chanx_left_in[4]:20 0.00341 +9 chanx_left_in[4]:20 chanx_left_in[4]:19 0.0008510916 +10 chanx_left_in[4]:20 chanx_left_in[4]:11 0.004686291 +11 chanx_left_in[4]:22 chanx_left_in[4]:21 0.002732267 +12 chanx_left_in[4]:23 chanx_left_in[4]:22 0.00341 +13 chanx_left_in[4]:25 chanx_left_in[4]:24 0.00341 +14 chanx_left_in[4]:24 chanx_left_in[4]:23 0.0002107167 +15 chanx_left_in[4]:15 chanx_left_in[4]:14 0.001694196 +16 chanx_left_in[4]:15 chanx_left_in[4]:13 0.002756697 +17 chanx_left_in[4]:16 chanx_left_in[4]:15 0.0045 +18 chanx_left_in[4]:17 chanx_left_in[4]:16 0.0008191965 +19 chanx_left_in[4]:18 chanx_left_in[4]:17 0.00341 +20 chanx_left_in[4]:18 chanx_left_in[4]:12 0.0001039141 +21 chanx_left_in[4]:19 chanx_left_in[4]:18 0.00341 +22 chanx_left_in[4]:29 chanx_left_in[4]:28 0.004462054 +23 chanx_left_in[4]:30 chanx_left_in[4]:29 0.00341 +24 chanx_left_in[4]:30 chanx_left_in[4]:25 0.001294067 +25 chanx_left_in[4]:27 chanx_left_in[4]:26 0.001479911 +26 chanx_left_in[4]:28 chanx_left_in[4]:27 0.0045 +27 chanx_left_in[4]:26 mux_bottom_ipin_4\/mux_l1_in_2_:A1 0.152 +28 chanx_left_in[4]:31 chanx_left_in[4]:30 0.000141 +29 chanx_left_in[4]:32 chanx_left_in[4]:31 0.00341 +30 chanx_left_in[4]:34 chanx_left_in[4]:33 0.00341 +31 chanx_left_in[4]:33 chanx_left_in[4]:32 0.001382583 +32 chanx_left_in[4]:36 chanx_left_in[4]:35 0.00341 +33 chanx_left_in[4]:35 chanx_left_in[4]:34 0.00821129 +34 chanx_left_in[4]:37 chanx_left_in[4]:36 0.00171875 +35 chanx_left_in[4]:38 chanx_left_in[4]:37 0.00341 +36 chanx_left_in[4]:14 mux_bottom_ipin_0\/mux_l1_in_2_:A1 0.152 +37 chanx_left_in[4]:13 mux_top_ipin_0\/mux_l1_in_2_:A1 0.152 + +*END + +*D_NET chanx_right_in[6] 0.01924613 //LENGTH 122.335 LUMPCC 0.008299862 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 103.575 25.840 +*I mux_bottom_ipin_12\/mux_l1_in_2_:A0 I *L 0.001631 *C 57.675 26.520 +*I mux_bottom_ipin_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 27.700 20.060 +*I mux_bottom_ipin_10\/mux_l2_in_2_:A1 I *L 0.00198 *C 28.520 14.620 +*I BUFT_P_88:A I *L 0.001776 *C 5.980 25.840 +*N chanx_right_in[6]:5 *C 6.018 25.840 +*N chanx_right_in[6]:6 *C 6.855 25.840 +*N chanx_right_in[6]:7 *C 6.900 25.840 +*N chanx_right_in[6]:8 *C 6.908 25.840 +*N chanx_right_in[6]:9 *C 10.100 25.840 +*N chanx_right_in[6]:10 *C 10.120 25.832 +*N chanx_right_in[6]:11 *C 10.120 21.088 +*N chanx_right_in[6]:12 *C 10.140 21.080 +*N chanx_right_in[6]:13 *C 28.483 14.620 +*N chanx_right_in[6]:14 *C 27.185 14.620 +*N chanx_right_in[6]:15 *C 27.140 14.665 +*N chanx_right_in[6]:16 *C 27.140 20.060 +*N chanx_right_in[6]:17 *C 27.663 20.060 +*N chanx_right_in[6]:18 *C 26.725 20.060 +*N chanx_right_in[6]:19 *C 26.680 20.060 +*N chanx_right_in[6]:20 *C 26.680 21.023 +*N chanx_right_in[6]:21 *C 26.680 21.080 +*N chanx_right_in[6]:22 *C 58.413 21.080 +*N chanx_right_in[6]:23 *C 58.420 21.137 +*N chanx_right_in[6]:24 *C 57.713 26.520 +*N chanx_right_in[6]:25 *C 58.375 26.520 +*N chanx_right_in[6]:26 *C 58.420 26.520 +*N chanx_right_in[6]:27 *C 58.428 26.520 +*N chanx_right_in[6]:28 *C 103.500 26.520 + +*CAP +0 chanx_right_in[6] 5.96943e-05 +1 mux_bottom_ipin_12\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_ipin_2\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_10\/mux_l2_in_2_:A1 1e-06 +4 BUFT_P_88:A 1e-06 +5 chanx_right_in[6]:5 7.496024e-05 +6 chanx_right_in[6]:6 7.496024e-05 +7 chanx_right_in[6]:7 3.533988e-05 +8 chanx_right_in[6]:8 0.0002828418 +9 chanx_right_in[6]:9 0.0002828418 +10 chanx_right_in[6]:10 0.0003513643 +11 chanx_right_in[6]:11 0.0003513643 +12 chanx_right_in[6]:12 0.0006167018 +13 chanx_right_in[6]:13 0.0001091908 +14 chanx_right_in[6]:14 0.0001091908 +15 chanx_right_in[6]:15 0.0002800903 +16 chanx_right_in[6]:16 0.0003160684 +17 chanx_right_in[6]:17 9.934031e-05 +18 chanx_right_in[6]:18 9.934031e-05 +19 chanx_right_in[6]:19 0.0001131365 +20 chanx_right_in[6]:20 7.715831e-05 +21 chanx_right_in[6]:21 0.001805579 +22 chanx_right_in[6]:22 0.001188877 +23 chanx_right_in[6]:23 0.0002623589 +24 chanx_right_in[6]:24 8.1686e-05 +25 chanx_right_in[6]:25 8.1686e-05 +26 chanx_right_in[6]:26 0.0002991359 +27 chanx_right_in[6]:27 0.001914832 +28 chanx_right_in[6]:28 0.001974526 +29 chanx_right_in[6]:12 chanx_right_in[10]:9 0.0003047676 +30 chanx_right_in[6]:21 chanx_right_in[10]:14 0.0005246402 +31 chanx_right_in[6]:21 chanx_right_in[10]:9 0.0004947225 +32 chanx_right_in[6]:22 chanx_right_in[10]:14 0.0004947225 +33 chanx_right_in[6]:22 chanx_right_in[10]:19 0.0002198727 +34 chanx_right_in[6]:12 chanx_right_in[12]:18 2.785684e-05 +35 chanx_right_in[6]:12 chanx_right_in[12]:21 0.0003415096 +36 chanx_right_in[6]:21 chanx_right_in[12]:17 2.785684e-05 +37 chanx_right_in[6]:21 chanx_right_in[12]:21 0.0004420135 +38 chanx_right_in[6]:21 chanx_right_in[12]:22 0.0003415096 +39 chanx_right_in[6]:27 chanx_right_in[12]:30 0.0004208529 +40 chanx_right_in[6]:27 chanx_right_in[12]:34 8.082712e-05 +41 chanx_right_in[6]:27 chanx_right_in[12]:25 0.0007529794 +42 chanx_right_in[6]:22 chanx_right_in[12]:22 0.0004420135 +43 chanx_right_in[6]:28 chanx_right_in[12] 8.082712e-05 +44 chanx_right_in[6]:28 chanx_right_in[12]:31 0.0004208529 +45 chanx_right_in[6]:28 chanx_right_in[12]:26 0.0007529794 +46 chanx_right_in[6]:27 prog_clk[0]:147 0.0007745895 +47 chanx_right_in[6]:27 prog_clk[0]:82 0.0001342556 +48 chanx_right_in[6]:28 prog_clk[0]:147 0.0001342556 +49 chanx_right_in[6]:28 prog_clk[0]:148 0.0007745895 +50 chanx_right_in[6]:26 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.669424e-05 +51 chanx_right_in[6]:23 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.669424e-05 +52 chanx_right_in[6]:15 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.898954e-05 +53 chanx_right_in[6]:16 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.898954e-05 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:28 0.0001065333 +1 chanx_right_in[6]:12 chanx_right_in[6]:11 0.00341 +2 chanx_right_in[6]:11 chanx_right_in[6]:10 0.0007433833 +3 chanx_right_in[6]:9 chanx_right_in[6]:8 0.0005001583 +4 chanx_right_in[6]:10 chanx_right_in[6]:9 0.00341 +5 chanx_right_in[6]:7 chanx_right_in[6]:6 0.0045 +6 chanx_right_in[6]:8 chanx_right_in[6]:7 0.00341 +7 chanx_right_in[6]:6 chanx_right_in[6]:5 0.0007477679 +8 chanx_right_in[6]:5 BUFT_P_88:A 0.152 +9 chanx_right_in[6]:20 chanx_right_in[6]:19 0.0008593749 +10 chanx_right_in[6]:21 chanx_right_in[6]:20 0.00341 +11 chanx_right_in[6]:21 chanx_right_in[6]:12 0.002591267 +12 chanx_right_in[6]:14 chanx_right_in[6]:13 0.001158482 +13 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0045 +14 chanx_right_in[6]:13 mux_bottom_ipin_10\/mux_l2_in_2_:A1 0.152 +15 chanx_right_in[6]:25 chanx_right_in[6]:24 0.0005915179 +16 chanx_right_in[6]:26 chanx_right_in[6]:25 0.0045 +17 chanx_right_in[6]:26 chanx_right_in[6]:23 0.004805804 +18 chanx_right_in[6]:24 mux_bottom_ipin_12\/mux_l1_in_2_:A0 0.152 +19 chanx_right_in[6]:18 chanx_right_in[6]:17 0.0008370536 +20 chanx_right_in[6]:19 chanx_right_in[6]:18 0.0045 +21 chanx_right_in[6]:19 chanx_right_in[6]:16 0.0004107143 +22 chanx_right_in[6]:17 mux_bottom_ipin_2\/mux_l2_in_2_:A1 0.152 +23 chanx_right_in[6]:27 chanx_right_in[6]:26 0.00341 +24 chanx_right_in[6]:23 chanx_right_in[6]:22 0.00341 +25 chanx_right_in[6]:22 chanx_right_in[6]:21 0.004971425 +26 chanx_right_in[6]:16 chanx_right_in[6]:15 0.004816964 +27 chanx_right_in[6]:28 chanx_right_in[6]:27 0.007061358 + +*END + +*D_NET chanx_right_in[11] 0.02525372 //LENGTH 160.795 LUMPCC 0.009717674 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 103.650 38.080 +*I mux_bottom_ipin_15\/mux_l2_in_2_:A1 I *L 0.00198 *C 91.080 52.700 +*I mux_bottom_ipin_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 47.020 56.100 +*I ropt_mt_inst_709:A I *L 0.001767 *C 7.360 31.280 +*I mux_bottom_ipin_7\/mux_l2_in_2_:A1 I *L 0.00198 *C 25.205 56.100 +*N chanx_right_in[11]:5 *C 25.242 56.100 +*N chanx_right_in[11]:6 *C 26.635 56.100 +*N chanx_right_in[11]:7 *C 26.680 56.055 +*N chanx_right_in[11]:8 *C 7.323 31.280 +*N chanx_right_in[11]:9 *C 1.885 31.280 +*N chanx_right_in[11]:10 *C 1.840 31.325 +*N chanx_right_in[11]:11 *C 1.840 41.775 +*N chanx_right_in[11]:12 *C 1.885 41.820 +*N chanx_right_in[11]:13 *C 5.015 41.820 +*N chanx_right_in[11]:14 *C 5.060 41.865 +*N chanx_right_in[11]:15 *C 5.060 50.943 +*N chanx_right_in[11]:16 *C 5.067 51.000 +*N chanx_right_in[11]:17 *C 26.673 51.000 +*N chanx_right_in[11]:18 *C 26.680 51.058 +*N chanx_right_in[11]:19 *C 26.680 55.080 +*N chanx_right_in[11]:20 *C 26.725 55.080 +*N chanx_right_in[11]:21 *C 31.740 55.080 +*N chanx_right_in[11]:22 *C 31.740 55.420 +*N chanx_right_in[11]:23 *C 45.495 55.420 +*N chanx_right_in[11]:24 *C 45.540 55.465 +*N chanx_right_in[11]:25 *C 46.983 56.100 +*N chanx_right_in[11]:26 *C 45.585 56.100 +*N chanx_right_in[11]:27 *C 45.540 56.055 +*N chanx_right_in[11]:28 *C 45.540 56.440 +*N chanx_right_in[11]:29 *C 45.547 56.440 +*N chanx_right_in[11]:30 *C 84.620 56.440 +*N chanx_right_in[11]:31 *C 84.640 56.433 +*N chanx_right_in[11]:32 *C 84.640 53.047 +*N chanx_right_in[11]:33 *C 84.660 53.040 +*N chanx_right_in[11]:34 *C 91.080 52.700 +*N chanx_right_in[11]:35 *C 91.080 52.700 +*N chanx_right_in[11]:36 *C 91.080 53.040 +*N chanx_right_in[11]:37 *C 91.080 53.040 +*N chanx_right_in[11]:38 *C 93.380 53.040 +*N chanx_right_in[11]:39 *C 93.380 52.360 +*N chanx_right_in[11]:40 *C 102.113 52.360 +*N chanx_right_in[11]:41 *C 102.120 52.303 +*N chanx_right_in[11]:42 *C 102.120 38.138 +*N chanx_right_in[11]:43 *C 102.128 38.080 + +*CAP +0 chanx_right_in[11] 0.0001144474 +1 mux_bottom_ipin_15\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_2_:A1 1e-06 +3 ropt_mt_inst_709:A 1e-06 +4 mux_bottom_ipin_7\/mux_l2_in_2_:A1 1e-06 +5 chanx_right_in[11]:5 0.0001249626 +6 chanx_right_in[11]:6 0.0001249626 +7 chanx_right_in[11]:7 6.695509e-05 +8 chanx_right_in[11]:8 0.0003362741 +9 chanx_right_in[11]:9 0.0003362741 +10 chanx_right_in[11]:10 0.0006309479 +11 chanx_right_in[11]:11 0.0006309479 +12 chanx_right_in[11]:12 0.000230506 +13 chanx_right_in[11]:13 0.000230506 +14 chanx_right_in[11]:14 0.0002417057 +15 chanx_right_in[11]:15 0.0002417057 +16 chanx_right_in[11]:16 0.0008512707 +17 chanx_right_in[11]:17 0.0008512709 +18 chanx_right_in[11]:18 0.0002375573 +19 chanx_right_in[11]:19 0.0003400376 +20 chanx_right_in[11]:20 0.0003663891 +21 chanx_right_in[11]:21 0.0003913943 +22 chanx_right_in[11]:22 0.0008878594 +23 chanx_right_in[11]:23 0.0008628542 +24 chanx_right_in[11]:24 6.927415e-05 +25 chanx_right_in[11]:25 9.742077e-05 +26 chanx_right_in[11]:26 9.742077e-05 +27 chanx_right_in[11]:27 9.598411e-05 +28 chanx_right_in[11]:28 6.808982e-05 +29 chanx_right_in[11]:29 0.001333925 +30 chanx_right_in[11]:30 0.001333925 +31 chanx_right_in[11]:31 0.0002392704 +32 chanx_right_in[11]:32 0.0002392704 +33 chanx_right_in[11]:33 0.0002811877 +34 chanx_right_in[11]:34 3.366134e-05 +35 chanx_right_in[11]:35 5.249071e-05 +36 chanx_right_in[11]:36 5.652874e-05 +37 chanx_right_in[11]:37 0.0004091437 +38 chanx_right_in[11]:38 0.0001825649 +39 chanx_right_in[11]:39 0.0006331112 +40 chanx_right_in[11]:40 0.0005785023 +41 chanx_right_in[11]:41 0.0007584984 +42 chanx_right_in[11]:42 0.0007584984 +43 chanx_right_in[11]:43 0.0001144474 +44 chanx_right_in[11]:29 chanx_left_in[5]:19 6.610426e-05 +45 chanx_right_in[11]:29 chanx_left_in[5]:25 0.0003617972 +46 chanx_right_in[11]:30 chanx_left_in[5]:18 6.610426e-05 +47 chanx_right_in[11]:30 chanx_left_in[5]:24 0.0003617972 +48 chanx_right_in[11]:18 chanx_left_in[7]:33 2.029113e-09 +49 chanx_right_in[11]:17 chanx_left_in[7]:34 0.0002297132 +50 chanx_right_in[11]:17 chanx_left_in[7]:36 0.0004945073 +51 chanx_right_in[11]:16 chanx_left_in[7] 0.0004945073 +52 chanx_right_in[11]:16 chanx_left_in[7]:35 0.0002297132 +53 chanx_right_in[11]:19 chanx_left_in[7]:32 2.029113e-09 +54 chanx_right_in[11]:17 chanx_left_in[9]:22 0.0001614686 +55 chanx_right_in[11]:17 chanx_left_in[9]:24 0.0001143654 +56 chanx_right_in[11]:17 chanx_left_in[9]:26 1.974588e-05 +57 chanx_right_in[11]:17 chanx_left_in[9]:30 0.0001011872 +58 chanx_right_in[11]:16 chanx_left_in[9]:23 0.0001614686 +59 chanx_right_in[11]:16 chanx_left_in[9]:25 0.0001143654 +60 chanx_right_in[11]:16 chanx_left_in[9]:30 1.974588e-05 +61 chanx_right_in[11]:16 chanx_left_in[9]:31 0.0001011872 +62 chanx_right_in[11]:17 chanx_left_in[13]:17 3.633211e-07 +63 chanx_right_in[11]:17 chanx_left_in[13]:21 2.307222e-07 +64 chanx_right_in[11]:16 chanx_left_in[13]:21 3.633211e-07 +65 chanx_right_in[11]:16 chanx_left_in[13]:22 2.307222e-07 +66 chanx_right_in[11]:37 chanx_left_in[13]:8 0.0003628632 +67 chanx_right_in[11]:37 chanx_left_in[13]:13 0.0001300646 +68 chanx_right_in[11]:29 chanx_left_in[13]:14 9.226685e-06 +69 chanx_right_in[11]:29 chanx_left_in[13]:21 2.854974e-05 +70 chanx_right_in[11]:30 chanx_left_in[13]:13 9.226685e-06 +71 chanx_right_in[11]:30 chanx_left_in[13]:17 2.854974e-05 +72 chanx_right_in[11]:33 chanx_left_in[13]:13 0.0003628632 +73 chanx_right_in[11]:40 chanx_left_in[13]:8 6.262458e-05 +74 chanx_right_in[11]:38 chanx_left_in[13]:7 8.795824e-06 +75 chanx_right_in[11]:38 chanx_left_in[13]:8 0.0001300646 +76 chanx_right_in[11]:39 chanx_left_in[13]:6 8.795824e-06 +77 chanx_right_in[11]:39 chanx_left_in[13]:13 6.262458e-05 +78 chanx_right_in[11]:29 chanx_left_in[17]:22 0.001300123 +79 chanx_right_in[11]:30 chanx_left_in[17]:21 0.001300123 +80 chanx_right_in[11]:26 chanx_left_in[17]:25 4.507524e-05 +81 chanx_right_in[11]:25 chanx_left_in[17]:24 4.507524e-05 +82 chanx_right_in[11]:23 chanx_left_in[17]:24 0.0002651345 +83 chanx_right_in[11]:22 chanx_left_in[17]:25 0.0002651345 +84 chanx_right_in[11]:29 chanx_right_in[1]:47 0.0002781733 +85 chanx_right_in[11]:29 chanx_right_in[1]:53 8.07989e-05 +86 chanx_right_in[11]:30 chanx_right_in[1]:53 0.0002781733 +87 chanx_right_in[11]:30 chanx_right_in[1]:54 8.07989e-05 +88 chanx_right_in[11]:15 chanx_right_in[18]:7 0.0002285528 +89 chanx_right_in[11]:14 chanx_right_in[18]:11 0.0002285528 +90 chanx_right_in[11]:9 chanx_right_in[18]:9 3.152754e-05 +91 chanx_right_in[11]:8 chanx_right_in[18]:8 3.152754e-05 +92 chanx_right_in[11]:29 optlc_net_108:34 0.0002504172 +93 chanx_right_in[11]:29 optlc_net_108:33 2.01801e-05 +94 chanx_right_in[11]:30 optlc_net_108:29 0.0002504172 +95 chanx_right_in[11]:30 optlc_net_108:34 2.01801e-05 +96 chanx_right_in[11]:15 ropt_net_158:5 0.0002072458 +97 chanx_right_in[11]:14 ropt_net_158:6 0.0002072458 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:43 0.000238525 +1 chanx_right_in[11]:18 chanx_right_in[11]:17 0.00341 +2 chanx_right_in[11]:17 chanx_right_in[11]:16 0.003384783 +3 chanx_right_in[11]:15 chanx_right_in[11]:14 0.008104911 +4 chanx_right_in[11]:16 chanx_right_in[11]:15 0.00341 +5 chanx_right_in[11]:13 chanx_right_in[11]:12 0.002794643 +6 chanx_right_in[11]:14 chanx_right_in[11]:13 0.0045 +7 chanx_right_in[11]:12 chanx_right_in[11]:11 0.0045 +8 chanx_right_in[11]:11 chanx_right_in[11]:10 0.009330358 +9 chanx_right_in[11]:9 chanx_right_in[11]:8 0.004854911 +10 chanx_right_in[11]:10 chanx_right_in[11]:9 0.0045 +11 chanx_right_in[11]:8 ropt_mt_inst_709:A 0.152 +12 chanx_right_in[11]:36 chanx_right_in[11]:35 0.0001634615 +13 chanx_right_in[11]:37 chanx_right_in[11]:36 0.00341 +14 chanx_right_in[11]:37 chanx_right_in[11]:33 0.0010058 +15 chanx_right_in[11]:34 mux_bottom_ipin_15\/mux_l2_in_2_:A1 0.152 +16 chanx_right_in[11]:35 chanx_right_in[11]:34 0.0045 +17 chanx_right_in[11]:28 chanx_right_in[11]:27 0.0001850962 +18 chanx_right_in[11]:29 chanx_right_in[11]:28 0.00341 +19 chanx_right_in[11]:30 chanx_right_in[11]:29 0.006121358 +20 chanx_right_in[11]:31 chanx_right_in[11]:30 0.00341 +21 chanx_right_in[11]:33 chanx_right_in[11]:32 0.00341 +22 chanx_right_in[11]:32 chanx_right_in[11]:31 0.0005303166 +23 chanx_right_in[11]:42 chanx_right_in[11]:41 0.01264732 +24 chanx_right_in[11]:43 chanx_right_in[11]:42 0.00341 +25 chanx_right_in[11]:41 chanx_right_in[11]:40 0.00341 +26 chanx_right_in[11]:40 chanx_right_in[11]:39 0.001368092 +27 chanx_right_in[11]:6 chanx_right_in[11]:5 0.001243304 +28 chanx_right_in[11]:7 chanx_right_in[11]:6 0.0045 +29 chanx_right_in[11]:5 mux_bottom_ipin_7\/mux_l2_in_2_:A1 0.152 +30 chanx_right_in[11]:26 chanx_right_in[11]:25 0.001247768 +31 chanx_right_in[11]:27 chanx_right_in[11]:26 0.0045 +32 chanx_right_in[11]:27 chanx_right_in[11]:24 0.0005267857 +33 chanx_right_in[11]:25 mux_bottom_ipin_1\/mux_l2_in_2_:A1 0.152 +34 chanx_right_in[11]:23 chanx_right_in[11]:22 0.01228125 +35 chanx_right_in[11]:24 chanx_right_in[11]:23 0.0045 +36 chanx_right_in[11]:20 chanx_right_in[11]:19 0.0045 +37 chanx_right_in[11]:19 chanx_right_in[11]:18 0.003591518 +38 chanx_right_in[11]:19 chanx_right_in[11]:7 0.0008705358 +39 chanx_right_in[11]:21 chanx_right_in[11]:20 0.004477679 +40 chanx_right_in[11]:22 chanx_right_in[11]:21 0.0003035715 +41 chanx_right_in[11]:38 chanx_right_in[11]:37 0.0003603333 +42 chanx_right_in[11]:39 chanx_right_in[11]:38 0.0001065333 + +*END + +*D_NET chanx_right_in[18] 0.02036702 //LENGTH 160.780 LUMPCC 0.003931604 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 103.650 10.200 +*I mux_bottom_ipin_14\/mux_l2_in_3_:A1 I *L 0.00198 *C 75.900 14.620 +*I mux_bottom_ipin_6\/mux_l2_in_3_:A1 I *L 0.00198 *C 44.065 18.020 +*I mux_bottom_ipin_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 5.160 30.940 +*I BUFT_RR_70:A I *L 0.001767 *C 3.220 53.040 +*N chanx_right_in[18]:5 *C 3.258 53.040 +*N chanx_right_in[18]:6 *C 4.555 53.040 +*N chanx_right_in[18]:7 *C 4.600 52.995 +*N chanx_right_in[18]:8 *C 5.123 30.940 +*N chanx_right_in[18]:9 *C 4.645 30.940 +*N chanx_right_in[18]:10 *C 4.600 30.985 +*N chanx_right_in[18]:11 *C 4.600 31.960 +*N chanx_right_in[18]:12 *C 4.607 31.960 +*N chanx_right_in[18]:13 *C 34.953 31.960 +*N chanx_right_in[18]:14 *C 34.960 31.960 +*N chanx_right_in[18]:15 *C 35.005 31.960 +*N chanx_right_in[18]:16 *C 45.495 31.960 +*N chanx_right_in[18]:17 *C 45.540 31.915 +*N chanx_right_in[18]:18 *C 44.102 18.020 +*N chanx_right_in[18]:19 *C 45.540 18.020 +*N chanx_right_in[18]:20 *C 45.540 18.360 +*N chanx_right_in[18]:21 *C 45.540 18.360 +*N chanx_right_in[18]:22 *C 45.540 7.525 +*N chanx_right_in[18]:23 *C 45.585 7.480 +*N chanx_right_in[18]:24 *C 68.035 7.480 +*N chanx_right_in[18]:25 *C 68.080 7.525 +*N chanx_right_in[18]:26 *C 68.080 10.143 +*N chanx_right_in[18]:27 *C 68.088 10.200 +*N chanx_right_in[18]:28 *C 75.938 14.620 +*N chanx_right_in[18]:29 *C 76.315 14.620 +*N chanx_right_in[18]:30 *C 76.360 14.575 +*N chanx_right_in[18]:31 *C 76.360 10.258 +*N chanx_right_in[18]:32 *C 76.360 10.200 + +*CAP +0 chanx_right_in[18] 0.001317626 +1 mux_bottom_ipin_14\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_6\/mux_l2_in_3_:A1 1e-06 +3 mux_bottom_ipin_8\/mux_l2_in_3_:A1 1e-06 +4 BUFT_RR_70:A 1e-06 +5 chanx_right_in[18]:5 9.583716e-05 +6 chanx_right_in[18]:6 9.583716e-05 +7 chanx_right_in[18]:7 0.0008358699 +8 chanx_right_in[18]:8 3.927231e-05 +9 chanx_right_in[18]:9 3.927231e-05 +10 chanx_right_in[18]:10 3.671665e-05 +11 chanx_right_in[18]:11 0.0009083133 +12 chanx_right_in[18]:12 0.001367379 +13 chanx_right_in[18]:13 0.001367379 +14 chanx_right_in[18]:14 3.476968e-05 +15 chanx_right_in[18]:15 0.0007131682 +16 chanx_right_in[18]:16 0.0007131682 +17 chanx_right_in[18]:17 0.0007737915 +18 chanx_right_in[18]:18 0.0001293783 +19 chanx_right_in[18]:19 0.000157408 +20 chanx_right_in[18]:20 6.040659e-05 +21 chanx_right_in[18]:21 0.001374365 +22 chanx_right_in[18]:22 0.0005662612 +23 chanx_right_in[18]:23 0.001327294 +24 chanx_right_in[18]:24 0.001327294 +25 chanx_right_in[18]:25 0.0001584131 +26 chanx_right_in[18]:26 0.0001584131 +27 chanx_right_in[18]:27 0.0004529163 +28 chanx_right_in[18]:28 4.677754e-05 +29 chanx_right_in[18]:29 4.677754e-05 +30 chanx_right_in[18]:30 0.0002583828 +31 chanx_right_in[18]:31 0.0002583828 +32 chanx_right_in[18]:32 0.001770542 +33 chanx_right_in[18]:7 chanx_left_in[8]:25 5.413083e-05 +34 chanx_right_in[18]:11 chanx_left_in[8]:24 5.413083e-05 +35 chanx_right_in[18]:11 chanx_left_in[8]:25 2.866951e-05 +36 chanx_right_in[18]:12 chanx_left_in[8] 8.631102e-06 +37 chanx_right_in[18]:12 chanx_left_in[8]:17 0.0002162907 +38 chanx_right_in[18]:13 chanx_left_in[8]:16 0.0002162907 +39 chanx_right_in[18]:13 chanx_left_in[8]:26 8.631102e-06 +40 chanx_right_in[18]:10 chanx_left_in[8]:24 2.866951e-05 +41 chanx_right_in[18]:12 chanx_left_in[16]:30 0.0005557578 +42 chanx_right_in[18]:13 chanx_left_in[16]:29 0.0005557578 +43 chanx_right_in[18] chanx_right_in[8]:19 0.0002322574 +44 chanx_right_in[18]:27 chanx_right_in[8]:18 4.889377e-05 +45 chanx_right_in[18]:32 chanx_right_in[8]:18 0.0002322574 +46 chanx_right_in[18]:32 chanx_right_in[8]:19 4.889377e-05 +47 chanx_right_in[18]:7 chanx_right_in[11]:15 0.0002285528 +48 chanx_right_in[18]:11 chanx_right_in[11]:14 0.0002285528 +49 chanx_right_in[18]:9 chanx_right_in[11]:9 3.152754e-05 +50 chanx_right_in[18]:8 chanx_right_in[11]:8 3.152754e-05 +51 chanx_right_in[18]:7 optlc_net_107:9 0.0003429861 +52 chanx_right_in[18]:11 optlc_net_107:9 1.96782e-05 +53 chanx_right_in[18]:11 optlc_net_107:8 0.0003429861 +54 chanx_right_in[18]:9 optlc_net_107:7 1.196275e-06 +55 chanx_right_in[18]:10 optlc_net_107:8 1.96782e-05 +56 chanx_right_in[18]:8 optlc_net_107:6 1.196275e-06 +57 chanx_right_in[18]:12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001972299 +58 chanx_right_in[18]:13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001972299 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:32 0.004275433 +1 chanx_right_in[18]:23 chanx_right_in[18]:22 0.0045 +2 chanx_right_in[18]:22 chanx_right_in[18]:21 0.009674107 +3 chanx_right_in[18]:24 chanx_right_in[18]:23 0.02004464 +4 chanx_right_in[18]:25 chanx_right_in[18]:24 0.0045 +5 chanx_right_in[18]:26 chanx_right_in[18]:25 0.002337053 +6 chanx_right_in[18]:27 chanx_right_in[18]:26 0.00341 +7 chanx_right_in[18]:6 chanx_right_in[18]:5 0.001158482 +8 chanx_right_in[18]:7 chanx_right_in[18]:6 0.0045 +9 chanx_right_in[18]:5 BUFT_RR_70:A 0.152 +10 chanx_right_in[18]:11 chanx_right_in[18]:10 0.0008705357 +11 chanx_right_in[18]:11 chanx_right_in[18]:7 0.01878125 +12 chanx_right_in[18]:12 chanx_right_in[18]:11 0.00341 +13 chanx_right_in[18]:14 chanx_right_in[18]:13 0.00341 +14 chanx_right_in[18]:13 chanx_right_in[18]:12 0.00475405 +15 chanx_right_in[18]:15 chanx_right_in[18]:14 0.0045 +16 chanx_right_in[18]:16 chanx_right_in[18]:15 0.009366072 +17 chanx_right_in[18]:17 chanx_right_in[18]:16 0.0045 +18 chanx_right_in[18]:20 chanx_right_in[18]:19 0.0003035715 +19 chanx_right_in[18]:21 chanx_right_in[18]:20 0.0045 +20 chanx_right_in[18]:21 chanx_right_in[18]:17 0.01210268 +21 chanx_right_in[18]:18 mux_bottom_ipin_6\/mux_l2_in_3_:A1 0.152 +22 chanx_right_in[18]:31 chanx_right_in[18]:30 0.003854911 +23 chanx_right_in[18]:32 chanx_right_in[18]:31 0.00341 +24 chanx_right_in[18]:32 chanx_right_in[18]:27 0.001296025 +25 chanx_right_in[18]:29 chanx_right_in[18]:28 0.0003370536 +26 chanx_right_in[18]:30 chanx_right_in[18]:29 0.0045 +27 chanx_right_in[18]:28 mux_bottom_ipin_14\/mux_l2_in_3_:A1 0.152 +28 chanx_right_in[18]:9 chanx_right_in[18]:8 0.0004263393 +29 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0045 +30 chanx_right_in[18]:8 mux_bottom_ipin_8\/mux_l2_in_3_:A1 0.152 +31 chanx_right_in[18]:19 chanx_right_in[18]:18 0.001283482 + +*END + +*D_NET top_grid_pin_30_[0] 0.0004425083 //LENGTH 4.235 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 77.340 72.080 +*P top_grid_pin_30_[0] O *L 0.7423 *C 76.360 74.870 +*N top_grid_pin_30_[0]:2 *C 76.360 72.125 +*N top_grid_pin_30_[0]:3 *C 76.405 72.080 +*N top_grid_pin_30_[0]:4 *C 77.303 72.080 + +*CAP +0 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_30_[0] 0.0001539982 +2 top_grid_pin_30_[0]:2 0.0001539982 +3 top_grid_pin_30_[0]:3 6.6756e-05 +4 top_grid_pin_30_[0]:4 6.6756e-05 + +*RES +0 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_30_[0]:4 0.152 +1 top_grid_pin_30_[0]:4 top_grid_pin_30_[0]:3 0.0008013393 +2 top_grid_pin_30_[0]:3 top_grid_pin_30_[0]:2 0.0045 +3 top_grid_pin_30_[0]:2 top_grid_pin_30_[0] 0.002450893 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.003002427 //LENGTH 24.885 LUMPCC 0.000504093 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 57.345 66.300 +*I mux_bottom_ipin_1\/mux_l3_in_1_:S I *L 0.00357 *C 46.560 61.880 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 44.795 69.700 +*I mux_bottom_ipin_1\/mux_l3_in_0_:S I *L 0.00357 *C 54.380 63.920 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 54.380 63.920 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 44.833 69.700 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 45.495 69.700 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 45.540 69.655 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 45.540 64.305 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 45.585 64.260 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 46.460 61.880 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 46.460 61.925 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 46.460 64.215 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 46.460 64.260 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 54.325 64.252 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 54.280 64.305 +*N mux_tree_tapbuf_size10_1_sram[2]:16 *C 54.280 66.255 +*N mux_tree_tapbuf_size10_1_sram[2]:17 *C 54.325 66.300 +*N mux_tree_tapbuf_size10_1_sram[2]:18 *C 57.308 66.300 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_1\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 5.922625e-05 +5 mux_tree_tapbuf_size10_1_sram[2]:5 6.598139e-05 +6 mux_tree_tapbuf_size10_1_sram[2]:6 6.598139e-05 +7 mux_tree_tapbuf_size10_1_sram[2]:7 0.0002858067 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0002858067 +9 mux_tree_tapbuf_size10_1_sram[2]:9 6.376414e-05 +10 mux_tree_tapbuf_size10_1_sram[2]:10 3.575293e-05 +11 mux_tree_tapbuf_size10_1_sram[2]:11 8.739627e-05 +12 mux_tree_tapbuf_size10_1_sram[2]:12 8.739627e-05 +13 mux_tree_tapbuf_size10_1_sram[2]:13 0.0004486262 +14 mux_tree_tapbuf_size10_1_sram[2]:14 0.0003805414 +15 mux_tree_tapbuf_size10_1_sram[2]:15 0.000118533 +16 mux_tree_tapbuf_size10_1_sram[2]:16 0.000118533 +17 mux_tree_tapbuf_size10_1_sram[2]:17 0.0001954942 +18 mux_tree_tapbuf_size10_1_sram[2]:18 0.0001954942 +19 mux_tree_tapbuf_size10_1_sram[2]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.555695e-06 +20 mux_tree_tapbuf_size10_1_sram[2]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.555695e-06 +21 mux_tree_tapbuf_size10_1_sram[2]:13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001158412 +22 mux_tree_tapbuf_size10_1_sram[2]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.185025e-05 +23 mux_tree_tapbuf_size10_1_sram[2]:11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.185025e-05 +24 mux_tree_tapbuf_size10_1_sram[2]:14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001158412 +25 mux_tree_tapbuf_size10_1_sram[2]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.258053e-05 +26 mux_tree_tapbuf_size10_1_sram[2]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.258053e-05 +27 mux_tree_tapbuf_size10_1_sram[2]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.021883e-05 +28 mux_tree_tapbuf_size10_1_sram[2]:11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.021883e-05 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:18 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.0045 +2 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.004776786 +3 mux_tree_tapbuf_size10_1_sram[2]:6 mux_tree_tapbuf_size10_1_sram[2]:5 0.0005915179 +4 mux_tree_tapbuf_size10_1_sram[2]:7 mux_tree_tapbuf_size10_1_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size10_1_sram[2]:5 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size10_1_sram[2]:4 mux_bottom_ipin_1\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:12 0.0045 +8 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:9 0.00078125 +9 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.002044643 +10 mux_tree_tapbuf_size10_1_sram[2]:10 mux_bottom_ipin_1\/mux_l3_in_1_:S 0.152 +11 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:10 0.0045 +12 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.007022322 +13 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:4 0.0001807065 +14 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:14 0.0045 +15 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:16 0.0045 +16 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[2]:15 0.001741072 +17 mux_tree_tapbuf_size10_1_sram[2]:18 mux_tree_tapbuf_size10_1_sram[2]:17 0.002662947 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[2] 0.003006124 //LENGTH 24.355 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 57.345 58.820 +*I mux_bottom_ipin_5\/mux_l3_in_0_:S I *L 0.00357 *C 53.920 53.040 +*I mux_bottom_ipin_5\/mux_l3_in_1_:S I *L 0.00357 *C 52.540 47.260 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 47.095 49.980 +*N mux_tree_tapbuf_size10_3_sram[2]:4 *C 47.133 49.980 +*N mux_tree_tapbuf_size10_3_sram[2]:5 *C 52.503 47.260 +*N mux_tree_tapbuf_size10_3_sram[2]:6 *C 52.025 47.260 +*N mux_tree_tapbuf_size10_3_sram[2]:7 *C 51.980 47.305 +*N mux_tree_tapbuf_size10_3_sram[2]:8 *C 51.980 49.935 +*N mux_tree_tapbuf_size10_3_sram[2]:9 *C 51.980 50.010 +*N mux_tree_tapbuf_size10_3_sram[2]:10 *C 51.980 51.000 +*N mux_tree_tapbuf_size10_3_sram[2]:11 *C 53.775 51.000 +*N mux_tree_tapbuf_size10_3_sram[2]:12 *C 53.820 51.045 +*N mux_tree_tapbuf_size10_3_sram[2]:13 *C 53.820 53.040 +*N mux_tree_tapbuf_size10_3_sram[2]:14 *C 53.820 53.040 +*N mux_tree_tapbuf_size10_3_sram[2]:15 *C 53.820 58.775 +*N mux_tree_tapbuf_size10_3_sram[2]:16 *C 53.865 58.820 +*N mux_tree_tapbuf_size10_3_sram[2]:17 *C 57.308 58.820 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_5\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_3_sram[2]:4 0.0003435602 +5 mux_tree_tapbuf_size10_3_sram[2]:5 7.329373e-05 +6 mux_tree_tapbuf_size10_3_sram[2]:6 7.329373e-05 +7 mux_tree_tapbuf_size10_3_sram[2]:7 0.0001735591 +8 mux_tree_tapbuf_size10_3_sram[2]:8 0.0001735591 +9 mux_tree_tapbuf_size10_3_sram[2]:9 0.0004079482 +10 mux_tree_tapbuf_size10_3_sram[2]:10 0.0002204138 +11 mux_tree_tapbuf_size10_3_sram[2]:11 0.0001560257 +12 mux_tree_tapbuf_size10_3_sram[2]:12 0.0001128991 +13 mux_tree_tapbuf_size10_3_sram[2]:13 3.111842e-05 +14 mux_tree_tapbuf_size10_3_sram[2]:14 0.0004755106 +15 mux_tree_tapbuf_size10_3_sram[2]:15 0.0003308471 +16 mux_tree_tapbuf_size10_3_sram[2]:16 0.0002150478 +17 mux_tree_tapbuf_size10_3_sram[2]:17 0.0002150478 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_3_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_3_sram[2]:5 mux_bottom_ipin_5\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_3_sram[2]:6 mux_tree_tapbuf_size10_3_sram[2]:5 0.0004263393 +3 mux_tree_tapbuf_size10_3_sram[2]:7 mux_tree_tapbuf_size10_3_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size10_3_sram[2]:9 mux_tree_tapbuf_size10_3_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size10_3_sram[2]:9 mux_tree_tapbuf_size10_3_sram[2]:4 0.004328125 +6 mux_tree_tapbuf_size10_3_sram[2]:8 mux_tree_tapbuf_size10_3_sram[2]:7 0.002348214 +7 mux_tree_tapbuf_size10_3_sram[2]:11 mux_tree_tapbuf_size10_3_sram[2]:10 0.001602679 +8 mux_tree_tapbuf_size10_3_sram[2]:12 mux_tree_tapbuf_size10_3_sram[2]:11 0.0045 +9 mux_tree_tapbuf_size10_3_sram[2]:4 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size10_3_sram[2]:16 mux_tree_tapbuf_size10_3_sram[2]:15 0.0045 +11 mux_tree_tapbuf_size10_3_sram[2]:15 mux_tree_tapbuf_size10_3_sram[2]:14 0.005120536 +12 mux_tree_tapbuf_size10_3_sram[2]:17 mux_tree_tapbuf_size10_3_sram[2]:16 0.00307366 +13 mux_tree_tapbuf_size10_3_sram[2]:13 mux_bottom_ipin_5\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size10_3_sram[2]:14 mux_tree_tapbuf_size10_3_sram[2]:13 0.0045 +15 mux_tree_tapbuf_size10_3_sram[2]:14 mux_tree_tapbuf_size10_3_sram[2]:12 0.00178125 +16 mux_tree_tapbuf_size10_3_sram[2]:10 mux_tree_tapbuf_size10_3_sram[2]:9 0.0008839286 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[3] 0.001708538 //LENGTH 14.040 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 13.645 69.360 +*I mux_bottom_ipin_9\/mux_l4_in_0_:S I *L 0.00357 *C 9.300 67.320 +*I mem_bottom_ipin_9\/FTB_6__45:A I *L 0.001746 *C 17.480 66.640 +*N mux_tree_tapbuf_size10_5_sram[3]:3 *C 17.480 66.640 +*N mux_tree_tapbuf_size10_5_sram[3]:4 *C 17.480 66.980 +*N mux_tree_tapbuf_size10_5_sram[3]:5 *C 11.960 66.980 +*N mux_tree_tapbuf_size10_5_sram[3]:6 *C 9.338 67.320 +*N mux_tree_tapbuf_size10_5_sram[3]:7 *C 11.960 67.290 +*N mux_tree_tapbuf_size10_5_sram[3]:8 *C 11.960 67.365 +*N mux_tree_tapbuf_size10_5_sram[3]:9 *C 11.960 69.315 +*N mux_tree_tapbuf_size10_5_sram[3]:10 *C 12.005 69.360 +*N mux_tree_tapbuf_size10_5_sram[3]:11 *C 13.607 69.360 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_9\/FTB_6__45:A 1e-06 +3 mux_tree_tapbuf_size10_5_sram[3]:3 5.452365e-05 +4 mux_tree_tapbuf_size10_5_sram[3]:4 0.000358985 +5 mux_tree_tapbuf_size10_5_sram[3]:5 0.000361054 +6 mux_tree_tapbuf_size10_5_sram[3]:6 0.0002225211 +7 mux_tree_tapbuf_size10_5_sram[3]:7 0.0002514793 +8 mux_tree_tapbuf_size10_5_sram[3]:8 0.0001196787 +9 mux_tree_tapbuf_size10_5_sram[3]:9 0.0001196787 +10 mux_tree_tapbuf_size10_5_sram[3]:10 0.000108809 +11 mux_tree_tapbuf_size10_5_sram[3]:11 0.000108809 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_5_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_5_sram[3]:3 mem_bottom_ipin_9\/FTB_6__45:A 0.152 +2 mux_tree_tapbuf_size10_5_sram[3]:6 mux_bottom_ipin_9\/mux_l4_in_0_:S 0.152 +3 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:6 0.002341518 +4 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:5 0.0002767857 +5 mux_tree_tapbuf_size10_5_sram[3]:8 mux_tree_tapbuf_size10_5_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size10_5_sram[3]:10 mux_tree_tapbuf_size10_5_sram[3]:9 0.0045 +7 mux_tree_tapbuf_size10_5_sram[3]:9 mux_tree_tapbuf_size10_5_sram[3]:8 0.001741072 +8 mux_tree_tapbuf_size10_5_sram[3]:11 mux_tree_tapbuf_size10_5_sram[3]:10 0.001430804 +9 mux_tree_tapbuf_size10_5_sram[3]:5 mux_tree_tapbuf_size10_5_sram[3]:4 0.004928572 +10 mux_tree_tapbuf_size10_5_sram[3]:4 mux_tree_tapbuf_size10_5_sram[3]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[2] 0.004438568 //LENGTH 35.200 LUMPCC 8.815983e-05 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 81.725 66.300 +*I mux_bottom_ipin_13\/mux_l3_in_0_:S I *L 0.00357 *C 73.240 61.200 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 63.655 69.700 +*I mux_bottom_ipin_13\/mux_l3_in_1_:S I *L 0.00357 *C 70.280 63.630 +*N mux_tree_tapbuf_size10_7_sram[2]:4 *C 70.280 63.630 +*N mux_tree_tapbuf_size10_7_sram[2]:5 *C 63.693 69.700 +*N mux_tree_tapbuf_size10_7_sram[2]:6 *C 64.355 69.700 +*N mux_tree_tapbuf_size10_7_sram[2]:7 *C 64.400 69.655 +*N mux_tree_tapbuf_size10_7_sram[2]:8 *C 64.400 63.285 +*N mux_tree_tapbuf_size10_7_sram[2]:9 *C 64.445 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:10 *C 70.280 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:11 *C 73.203 61.200 +*N mux_tree_tapbuf_size10_7_sram[2]:12 *C 70.425 61.200 +*N mux_tree_tapbuf_size10_7_sram[2]:13 *C 70.380 61.245 +*N mux_tree_tapbuf_size10_7_sram[2]:14 *C 70.380 63.195 +*N mux_tree_tapbuf_size10_7_sram[2]:15 *C 70.285 63.270 +*N mux_tree_tapbuf_size10_7_sram[2]:16 *C 79.995 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:17 *C 80.040 63.285 +*N mux_tree_tapbuf_size10_7_sram[2]:18 *C 80.040 66.255 +*N mux_tree_tapbuf_size10_7_sram[2]:19 *C 80.085 66.300 +*N mux_tree_tapbuf_size10_7_sram[2]:20 *C 81.688 66.300 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_13\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_7_sram[2]:4 5.68176e-05 +5 mux_tree_tapbuf_size10_7_sram[2]:5 6.652428e-05 +6 mux_tree_tapbuf_size10_7_sram[2]:6 6.652428e-05 +7 mux_tree_tapbuf_size10_7_sram[2]:7 0.00033989 +8 mux_tree_tapbuf_size10_7_sram[2]:8 0.00033989 +9 mux_tree_tapbuf_size10_7_sram[2]:9 0.0004146463 +10 mux_tree_tapbuf_size10_7_sram[2]:10 0.0004219942 +11 mux_tree_tapbuf_size10_7_sram[2]:11 0.0001944112 +12 mux_tree_tapbuf_size10_7_sram[2]:12 0.0001944112 +13 mux_tree_tapbuf_size10_7_sram[2]:13 0.000129626 +14 mux_tree_tapbuf_size10_7_sram[2]:14 0.000129626 +15 mux_tree_tapbuf_size10_7_sram[2]:15 0.0006970786 +16 mux_tree_tapbuf_size10_7_sram[2]:16 0.0006634553 +17 mux_tree_tapbuf_size10_7_sram[2]:17 0.0001808813 +18 mux_tree_tapbuf_size10_7_sram[2]:18 0.0001808813 +19 mux_tree_tapbuf_size10_7_sram[2]:19 0.000134875 +20 mux_tree_tapbuf_size10_7_sram[2]:20 0.000134875 +21 mux_tree_tapbuf_size10_7_sram[2]:16 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.173036e-05 +22 mux_tree_tapbuf_size10_7_sram[2]:15 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.173036e-05 +23 mux_tree_tapbuf_size10_7_sram[2]:14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.405738e-06 +24 mux_tree_tapbuf_size10_7_sram[2]:12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.438174e-07 +25 mux_tree_tapbuf_size10_7_sram[2]:13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.405738e-06 +26 mux_tree_tapbuf_size10_7_sram[2]:11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.438174e-07 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_7_sram[2]:20 0.152 +1 mux_tree_tapbuf_size10_7_sram[2]:16 mux_tree_tapbuf_size10_7_sram[2]:15 0.008669644 +2 mux_tree_tapbuf_size10_7_sram[2]:17 mux_tree_tapbuf_size10_7_sram[2]:16 0.0045 +3 mux_tree_tapbuf_size10_7_sram[2]:19 mux_tree_tapbuf_size10_7_sram[2]:18 0.0045 +4 mux_tree_tapbuf_size10_7_sram[2]:18 mux_tree_tapbuf_size10_7_sram[2]:17 0.002651786 +5 mux_tree_tapbuf_size10_7_sram[2]:20 mux_tree_tapbuf_size10_7_sram[2]:19 0.001430804 +6 mux_tree_tapbuf_size10_7_sram[2]:9 mux_tree_tapbuf_size10_7_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size10_7_sram[2]:8 mux_tree_tapbuf_size10_7_sram[2]:7 0.005687499 +8 mux_tree_tapbuf_size10_7_sram[2]:6 mux_tree_tapbuf_size10_7_sram[2]:5 0.0005915179 +9 mux_tree_tapbuf_size10_7_sram[2]:7 mux_tree_tapbuf_size10_7_sram[2]:6 0.0045 +10 mux_tree_tapbuf_size10_7_sram[2]:5 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size10_7_sram[2]:4 mux_bottom_ipin_13\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_7_sram[2]:15 mux_tree_tapbuf_size10_7_sram[2]:14 0.0045 +13 mux_tree_tapbuf_size10_7_sram[2]:15 mux_tree_tapbuf_size10_7_sram[2]:10 1e-05 +14 mux_tree_tapbuf_size10_7_sram[2]:15 mux_tree_tapbuf_size10_7_sram[2]:4 0.0003214286 +15 mux_tree_tapbuf_size10_7_sram[2]:14 mux_tree_tapbuf_size10_7_sram[2]:13 0.001741071 +16 mux_tree_tapbuf_size10_7_sram[2]:12 mux_tree_tapbuf_size10_7_sram[2]:11 0.002479911 +17 mux_tree_tapbuf_size10_7_sram[2]:13 mux_tree_tapbuf_size10_7_sram[2]:12 0.0045 +18 mux_tree_tapbuf_size10_7_sram[2]:11 mux_bottom_ipin_13\/mux_l3_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_7_sram[2]:10 mux_tree_tapbuf_size10_7_sram[2]:9 0.005209822 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[0] 0.007799308 //LENGTH 59.180 LUMPCC 0.001631432 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.465 63.920 +*I mux_bottom_ipin_2\/mux_l1_in_0_:S I *L 0.00357 *C 38.540 28.560 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.975 15.300 +*N mux_tree_tapbuf_size8_0_sram[0]:3 *C 36.975 15.300 +*N mux_tree_tapbuf_size8_0_sram[0]:4 *C 37.260 15.300 +*N mux_tree_tapbuf_size8_0_sram[0]:5 *C 37.260 15.345 +*N mux_tree_tapbuf_size8_0_sram[0]:6 *C 37.260 28.560 +*N mux_tree_tapbuf_size8_0_sram[0]:7 *C 38.503 28.560 +*N mux_tree_tapbuf_size8_0_sram[0]:8 *C 37.765 28.560 +*N mux_tree_tapbuf_size8_0_sram[0]:9 *C 37.720 28.605 +*N mux_tree_tapbuf_size8_0_sram[0]:10 *C 37.720 29.863 +*N mux_tree_tapbuf_size8_0_sram[0]:11 *C 37.727 29.920 +*N mux_tree_tapbuf_size8_0_sram[0]:12 *C 41.380 29.920 +*N mux_tree_tapbuf_size8_0_sram[0]:13 *C 41.400 29.928 +*N mux_tree_tapbuf_size8_0_sram[0]:14 *C 41.400 59.833 +*N mux_tree_tapbuf_size8_0_sram[0]:15 *C 41.420 59.840 +*N mux_tree_tapbuf_size8_0_sram[0]:16 *C 44.153 59.840 +*N mux_tree_tapbuf_size8_0_sram[0]:17 *C 44.160 59.898 +*N mux_tree_tapbuf_size8_0_sram[0]:18 *C 44.160 63.875 +*N mux_tree_tapbuf_size8_0_sram[0]:19 *C 44.160 63.920 +*N mux_tree_tapbuf_size8_0_sram[0]:20 *C 44.465 63.920 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_0_sram[0]:3 5.220715e-05 +4 mux_tree_tapbuf_size8_0_sram[0]:4 5.884367e-05 +5 mux_tree_tapbuf_size8_0_sram[0]:5 0.0007449716 +6 mux_tree_tapbuf_size8_0_sram[0]:6 0.000782464 +7 mux_tree_tapbuf_size8_0_sram[0]:7 8.485607e-05 +8 mux_tree_tapbuf_size8_0_sram[0]:8 8.485607e-05 +9 mux_tree_tapbuf_size8_0_sram[0]:9 0.000128228 +10 mux_tree_tapbuf_size8_0_sram[0]:10 9.073556e-05 +11 mux_tree_tapbuf_size8_0_sram[0]:11 0.0001811778 +12 mux_tree_tapbuf_size8_0_sram[0]:12 0.0001811778 +13 mux_tree_tapbuf_size8_0_sram[0]:13 0.001279042 +14 mux_tree_tapbuf_size8_0_sram[0]:14 0.001279042 +15 mux_tree_tapbuf_size8_0_sram[0]:15 0.0003158965 +16 mux_tree_tapbuf_size8_0_sram[0]:16 0.0003158965 +17 mux_tree_tapbuf_size8_0_sram[0]:17 0.0002416284 +18 mux_tree_tapbuf_size8_0_sram[0]:18 0.0002416284 +19 mux_tree_tapbuf_size8_0_sram[0]:19 5.195411e-05 +20 mux_tree_tapbuf_size8_0_sram[0]:20 5.027041e-05 +21 mux_tree_tapbuf_size8_0_sram[0]:11 chanx_left_in[16]:30 0.0002245211 +22 mux_tree_tapbuf_size8_0_sram[0]:12 chanx_left_in[16]:29 0.0002245211 +23 mux_tree_tapbuf_size8_0_sram[0]:13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.000591195 +24 mux_tree_tapbuf_size8_0_sram[0]:14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.000591195 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_0_sram[0]:20 0.152 +1 mux_tree_tapbuf_size8_0_sram[0]:8 mux_tree_tapbuf_size8_0_sram[0]:7 0.0006584823 +2 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:6 0.0004107143 +4 mux_tree_tapbuf_size8_0_sram[0]:7 mux_bottom_ipin_2\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_0_sram[0]:4 mux_tree_tapbuf_size8_0_sram[0]:3 0.0001548913 +6 mux_tree_tapbuf_size8_0_sram[0]:5 mux_tree_tapbuf_size8_0_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size8_0_sram[0]:3 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:9 0.001122768 +9 mux_tree_tapbuf_size8_0_sram[0]:11 mux_tree_tapbuf_size8_0_sram[0]:10 0.00341 +10 mux_tree_tapbuf_size8_0_sram[0]:12 mux_tree_tapbuf_size8_0_sram[0]:11 0.000572225 +11 mux_tree_tapbuf_size8_0_sram[0]:13 mux_tree_tapbuf_size8_0_sram[0]:12 0.00341 +12 mux_tree_tapbuf_size8_0_sram[0]:15 mux_tree_tapbuf_size8_0_sram[0]:14 0.00341 +13 mux_tree_tapbuf_size8_0_sram[0]:14 mux_tree_tapbuf_size8_0_sram[0]:13 0.004685116 +14 mux_tree_tapbuf_size8_0_sram[0]:17 mux_tree_tapbuf_size8_0_sram[0]:16 0.00341 +15 mux_tree_tapbuf_size8_0_sram[0]:16 mux_tree_tapbuf_size8_0_sram[0]:15 0.0004280916 +16 mux_tree_tapbuf_size8_0_sram[0]:19 mux_tree_tapbuf_size8_0_sram[0]:18 0.0045 +17 mux_tree_tapbuf_size8_0_sram[0]:18 mux_tree_tapbuf_size8_0_sram[0]:17 0.003551339 +18 mux_tree_tapbuf_size8_0_sram[0]:20 mux_tree_tapbuf_size8_0_sram[0]:19 0.0001657609 +19 mux_tree_tapbuf_size8_0_sram[0]:6 mux_tree_tapbuf_size8_0_sram[0]:5 0.01179911 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[1] 0.004329733 //LENGTH 35.480 LUMPCC 0.0001342052 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.505 15.300 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 41.575 11.900 +*I mux_bottom_ipin_6\/mux_l2_in_3_:S I *L 0.00357 *C 43.340 17.975 +*I mux_bottom_ipin_6\/mux_l2_in_0_:S I *L 0.00357 *C 51.620 19.720 +*I mux_bottom_ipin_6\/mux_l2_in_2_:S I *L 0.00357 *C 49.340 19.720 +*I mux_bottom_ipin_6\/mux_l2_in_1_:S I *L 0.00357 *C 49.320 23.120 +*N mux_tree_tapbuf_size8_2_sram[1]:6 *C 49.358 23.120 +*N mux_tree_tapbuf_size8_2_sram[1]:7 *C 51.935 23.120 +*N mux_tree_tapbuf_size8_2_sram[1]:8 *C 51.980 23.075 +*N mux_tree_tapbuf_size8_2_sram[1]:9 *C 49.378 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:10 *C 51.658 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:11 *C 51.960 19.728 +*N mux_tree_tapbuf_size8_2_sram[1]:12 *C 51.980 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:13 *C 43.340 17.975 +*N mux_tree_tapbuf_size8_2_sram[1]:14 *C 41.575 11.900 +*N mux_tree_tapbuf_size8_2_sram[1]:15 *C 41.860 11.900 +*N mux_tree_tapbuf_size8_2_sram[1]:16 *C 41.860 11.945 +*N mux_tree_tapbuf_size8_2_sram[1]:17 *C 41.860 17.635 +*N mux_tree_tapbuf_size8_2_sram[1]:18 *C 41.905 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:19 *C 43.340 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:20 *C 51.935 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:21 *C 51.980 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:22 *C 51.980 15.345 +*N mux_tree_tapbuf_size8_2_sram[1]:23 *C 52.025 15.300 +*N mux_tree_tapbuf_size8_2_sram[1]:24 *C 55.468 15.300 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_6\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_6\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_6\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_ipin_6\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size8_2_sram[1]:6 0.0002009188 +7 mux_tree_tapbuf_size8_2_sram[1]:7 0.0002009188 +8 mux_tree_tapbuf_size8_2_sram[1]:8 0.0001514786 +9 mux_tree_tapbuf_size8_2_sram[1]:9 0.0001762973 +10 mux_tree_tapbuf_size8_2_sram[1]:10 0.0002286197 +11 mux_tree_tapbuf_size8_2_sram[1]:11 5.232247e-05 +12 mux_tree_tapbuf_size8_2_sram[1]:12 0.0003097194 +13 mux_tree_tapbuf_size8_2_sram[1]:13 5.92635e-05 +14 mux_tree_tapbuf_size8_2_sram[1]:14 4.48477e-05 +15 mux_tree_tapbuf_size8_2_sram[1]:15 4.873544e-05 +16 mux_tree_tapbuf_size8_2_sram[1]:16 0.0003082863 +17 mux_tree_tapbuf_size8_2_sram[1]:17 0.0003082863 +18 mux_tree_tapbuf_size8_2_sram[1]:18 0.0001063535 +19 mux_tree_tapbuf_size8_2_sram[1]:19 0.0006334553 +20 mux_tree_tapbuf_size8_2_sram[1]:20 0.0004973685 +21 mux_tree_tapbuf_size8_2_sram[1]:21 0.0002957801 +22 mux_tree_tapbuf_size8_2_sram[1]:22 0.0001384156 +23 mux_tree_tapbuf_size8_2_sram[1]:23 0.0002142298 +24 mux_tree_tapbuf_size8_2_sram[1]:24 0.0002142298 +25 mux_tree_tapbuf_size8_2_sram[1]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.710261e-05 +26 mux_tree_tapbuf_size8_2_sram[1]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.710261e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_2_sram[1]:24 0.152 +1 mux_tree_tapbuf_size8_2_sram[1]:10 mux_bottom_ipin_6\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_2_sram[1]:10 mux_tree_tapbuf_size8_2_sram[1]:9 0.002035714 +3 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:16 0.005080357 +5 mux_tree_tapbuf_size8_2_sram[1]:15 mux_tree_tapbuf_size8_2_sram[1]:14 0.0001548913 +6 mux_tree_tapbuf_size8_2_sram[1]:16 mux_tree_tapbuf_size8_2_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size8_2_sram[1]:14 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size8_2_sram[1]:9 mux_bottom_ipin_6\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:19 0.007674107 +10 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:20 0.0045 +11 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:12 0.001821429 +12 mux_tree_tapbuf_size8_2_sram[1]:23 mux_tree_tapbuf_size8_2_sram[1]:22 0.0045 +13 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:21 0.002084821 +14 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:23 0.003073661 +15 mux_tree_tapbuf_size8_2_sram[1]:13 mux_bottom_ipin_6\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size8_2_sram[1]:11 mux_tree_tapbuf_size8_2_sram[1]:10 0.0001543367 +17 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:11 0.0045 +18 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:8 0.002995536 +19 mux_tree_tapbuf_size8_2_sram[1]:7 mux_tree_tapbuf_size8_2_sram[1]:6 0.00230134 +20 mux_tree_tapbuf_size8_2_sram[1]:8 mux_tree_tapbuf_size8_2_sram[1]:7 0.0045 +21 mux_tree_tapbuf_size8_2_sram[1]:6 mux_bottom_ipin_6\/mux_l2_in_1_:S 0.152 +22 mux_tree_tapbuf_size8_2_sram[1]:19 mux_tree_tapbuf_size8_2_sram[1]:18 0.00128125 +23 mux_tree_tapbuf_size8_2_sram[1]:19 mux_tree_tapbuf_size8_2_sram[1]:13 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[1] 0.003602192 //LENGTH 26.415 LUMPCC 0.0003543631 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.805 25.840 +*I mux_bottom_ipin_14\/mux_l2_in_1_:S I *L 0.00357 *C 80.600 23.120 +*I mux_bottom_ipin_14\/mux_l2_in_2_:S I *L 0.00357 *C 75.800 17.680 +*I mux_bottom_ipin_14\/mux_l2_in_3_:S I *L 0.00357 *C 74.860 14.620 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 74.235 9.860 +*I mux_bottom_ipin_14\/mux_l2_in_0_:S I *L 0.00357 *C 74.420 23.120 +*N mux_tree_tapbuf_size8_6_sram[1]:6 *C 74.458 23.120 +*N mux_tree_tapbuf_size8_6_sram[1]:7 *C 75.440 14.525 +*N mux_tree_tapbuf_size8_6_sram[1]:8 *C 74.273 9.860 +*N mux_tree_tapbuf_size8_6_sram[1]:9 *C 75.395 9.860 +*N mux_tree_tapbuf_size8_6_sram[1]:10 *C 75.440 9.905 +*N mux_tree_tapbuf_size8_6_sram[1]:11 *C 74.898 14.620 +*N mux_tree_tapbuf_size8_6_sram[1]:12 *C 75.395 14.620 +*N mux_tree_tapbuf_size8_6_sram[1]:13 *C 75.470 14.650 +*N mux_tree_tapbuf_size8_6_sram[1]:14 *C 75.485 14.960 +*N mux_tree_tapbuf_size8_6_sram[1]:15 *C 75.900 14.960 +*N mux_tree_tapbuf_size8_6_sram[1]:16 *C 75.800 17.680 +*N mux_tree_tapbuf_size8_6_sram[1]:17 *C 75.900 17.680 +*N mux_tree_tapbuf_size8_6_sram[1]:18 *C 75.900 23.075 +*N mux_tree_tapbuf_size8_6_sram[1]:19 *C 75.900 23.120 +*N mux_tree_tapbuf_size8_6_sram[1]:20 *C 80.513 23.120 +*N mux_tree_tapbuf_size8_6_sram[1]:21 *C 80.500 23.165 +*N mux_tree_tapbuf_size8_6_sram[1]:22 *C 80.500 25.795 +*N mux_tree_tapbuf_size8_6_sram[1]:23 *C 80.500 25.840 +*N mux_tree_tapbuf_size8_6_sram[1]:24 *C 80.805 25.840 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_14\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_ipin_14\/mux_l2_in_3_:S 1e-06 +4 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_ipin_14\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_6_sram[1]:6 9.490832e-05 +7 mux_tree_tapbuf_size8_6_sram[1]:7 1.032453e-05 +8 mux_tree_tapbuf_size8_6_sram[1]:8 9.561345e-05 +9 mux_tree_tapbuf_size8_6_sram[1]:9 9.561345e-05 +10 mux_tree_tapbuf_size8_6_sram[1]:10 0.0002964204 +11 mux_tree_tapbuf_size8_6_sram[1]:11 5.20597e-05 +12 mux_tree_tapbuf_size8_6_sram[1]:12 5.20597e-05 +13 mux_tree_tapbuf_size8_6_sram[1]:13 0.0003331453 +14 mux_tree_tapbuf_size8_6_sram[1]:14 5.696943e-05 +15 mux_tree_tapbuf_size8_6_sram[1]:15 0.0002026979 +16 mux_tree_tapbuf_size8_6_sram[1]:16 2.988502e-05 +17 mux_tree_tapbuf_size8_6_sram[1]:17 0.0005184495 +18 mux_tree_tapbuf_size8_6_sram[1]:18 0.0003143771 +19 mux_tree_tapbuf_size8_6_sram[1]:19 0.0003527052 +20 mux_tree_tapbuf_size8_6_sram[1]:20 0.0002219298 +21 mux_tree_tapbuf_size8_6_sram[1]:21 0.0001987201 +22 mux_tree_tapbuf_size8_6_sram[1]:22 0.0001987201 +23 mux_tree_tapbuf_size8_6_sram[1]:23 6.185274e-05 +24 mux_tree_tapbuf_size8_6_sram[1]:24 5.537724e-05 +25 mux_tree_tapbuf_size8_6_sram[1]:19 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.915131e-05 +26 mux_tree_tapbuf_size8_6_sram[1]:19 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.51039e-05 +27 mux_tree_tapbuf_size8_6_sram[1]:20 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.51039e-05 +28 mux_tree_tapbuf_size8_6_sram[1]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.915131e-05 +29 mux_tree_tapbuf_size8_6_sram[1]:19 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.292632e-05 +30 mux_tree_tapbuf_size8_6_sram[1]:20 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.292632e-05 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_6_sram[1]:24 0.152 +1 mux_tree_tapbuf_size8_6_sram[1]:11 mux_bottom_ipin_14\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size8_6_sram[1]:12 mux_tree_tapbuf_size8_6_sram[1]:11 0.0004441965 +3 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:10 0.004236607 +5 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:7 0.0001116071 +6 mux_tree_tapbuf_size8_6_sram[1]:19 mux_tree_tapbuf_size8_6_sram[1]:18 0.0045 +7 mux_tree_tapbuf_size8_6_sram[1]:19 mux_tree_tapbuf_size8_6_sram[1]:6 0.001287946 +8 mux_tree_tapbuf_size8_6_sram[1]:18 mux_tree_tapbuf_size8_6_sram[1]:17 0.004816964 +9 mux_tree_tapbuf_size8_6_sram[1]:16 mux_bottom_ipin_14\/mux_l2_in_2_:S 0.152 +10 mux_tree_tapbuf_size8_6_sram[1]:17 mux_tree_tapbuf_size8_6_sram[1]:16 0.0045 +11 mux_tree_tapbuf_size8_6_sram[1]:17 mux_tree_tapbuf_size8_6_sram[1]:15 0.002428572 +12 mux_tree_tapbuf_size8_6_sram[1]:20 mux_bottom_ipin_14\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size8_6_sram[1]:20 mux_tree_tapbuf_size8_6_sram[1]:19 0.004118304 +14 mux_tree_tapbuf_size8_6_sram[1]:6 mux_bottom_ipin_14\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size8_6_sram[1]:9 mux_tree_tapbuf_size8_6_sram[1]:8 0.001002232 +16 mux_tree_tapbuf_size8_6_sram[1]:10 mux_tree_tapbuf_size8_6_sram[1]:9 0.0045 +17 mux_tree_tapbuf_size8_6_sram[1]:8 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size8_6_sram[1]:21 mux_tree_tapbuf_size8_6_sram[1]:20 0.0045 +19 mux_tree_tapbuf_size8_6_sram[1]:23 mux_tree_tapbuf_size8_6_sram[1]:22 0.0045 +20 mux_tree_tapbuf_size8_6_sram[1]:22 mux_tree_tapbuf_size8_6_sram[1]:21 0.002348214 +21 mux_tree_tapbuf_size8_6_sram[1]:24 mux_tree_tapbuf_size8_6_sram[1]:23 8.967391e-05 +22 mux_tree_tapbuf_size8_6_sram[1]:14 mux_tree_tapbuf_size8_6_sram[1]:13 0.00019375 +23 mux_tree_tapbuf_size8_6_sram[1]:15 mux_tree_tapbuf_size8_6_sram[1]:14 0.0003705357 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.007034406 //LENGTH 57.395 LUMPCC 0.001571014 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l4_in_0_:X O *L 0 *C 82.515 37.060 +*I mux_bottom_ipin_0\/BUFT_RR_57:A I *L 0.001776 *C 61.640 72.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 61.640 72.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 61.640 72.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 61.648 72.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 79.100 72.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 79.120 72.073 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 79.120 47.608 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 79.140 47.600 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 82.333 47.600 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 82.340 47.543 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 82.340 37.105 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 82.340 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 82.515 37.060 + +*CAP +0 mux_bottom_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/BUFT_RR_57:A 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.667814e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.05697e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0007417453 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0007417453 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001336584 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.001336584 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.382057e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 6.382057e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0005094042 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0005094042 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 5.146879e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 4.956535e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[5]:13 0.0001990536 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[5]:8 0.0001990536 +16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[19]:30 0.0001990536 +17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[19]:29 0.0001990536 +18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_right_in[17]:23 0.0001345379 +19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_right_in[17]:24 0.0001345379 +20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:388 4.554625e-06 +21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:392 0.0001460662 +22 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:397 2.198703e-05 +23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:392 4.554625e-06 +24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:393 0.0001460662 +25 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:398 2.198703e-05 +26 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:212 7.273912e-06 +27 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:393 8.370751e-06 +28 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:211 7.273912e-06 +29 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:394 8.370751e-06 +30 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 prog_clk[0]:209 1.099978e-05 +31 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 prog_clk[0]:205 1.099978e-05 +32 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 5.361001e-05 +33 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 5.361001e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l4_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_0\/BUFT_RR_57:A 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.00341 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.002734225 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00383285 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0005001583 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0045 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.009319197 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0005033744 //LENGTH 3.480 LUMPCC 0.0001440561 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l3_in_0_:X O *L 0 *C 53.075 53.040 +*I mux_bottom_ipin_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 50.505 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 50.543 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 51.980 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 51.980 53.040 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 53.038 53.040 + +*CAP +0 mux_bottom_ipin_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.120964e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.654265e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001074495 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.211649e-05 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 chanx_right_in[3]:44 6.182101e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_right_in[3]:49 1.020705e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chanx_right_in[3]:49 6.182101e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chanx_right_in[3]:44 1.020705e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l3_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_5\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0009441964 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001283482 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003035715 + +*END + +*D_NET optlc_net_107 0.005295765 //LENGTH 39.335 LUMPCC 0.001868004 DR + +*CONN +*I optlc_108:HI O *L 0 *C 3.680 47.940 +*I mux_bottom_ipin_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 4.775 31.620 +*I mux_bottom_ipin_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 9.375 58.820 +*N optlc_net_107:3 *C 9.338 58.820 +*N optlc_net_107:4 *C 7.865 58.820 +*N optlc_net_107:5 *C 7.820 58.775 +*N optlc_net_107:6 *C 4.737 31.620 +*N optlc_net_107:7 *C 4.185 31.620 +*N optlc_net_107:8 *C 4.140 31.620 +*N optlc_net_107:9 *C 4.140 44.495 +*N optlc_net_107:10 *C 4.185 44.540 +*N optlc_net_107:11 *C 7.775 44.540 +*N optlc_net_107:12 *C 7.820 44.585 +*N optlc_net_107:13 *C 7.820 47.940 +*N optlc_net_107:14 *C 7.775 47.940 +*N optlc_net_107:15 *C 3.718 47.940 + +*CAP +0 optlc_108:HI 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_9\/mux_l2_in_3_:A0 1e-06 +3 optlc_net_107:3 0.0001466353 +4 optlc_net_107:4 0.0001466353 +5 optlc_net_107:5 0.0005062199 +6 optlc_net_107:6 7.377594e-05 +7 optlc_net_107:7 7.377594e-05 +8 optlc_net_107:8 0.0004429998 +9 optlc_net_107:9 0.0004119164 +10 optlc_net_107:10 0.0001550437 +11 optlc_net_107:11 0.0001550437 +12 optlc_net_107:12 0.0001511581 +13 optlc_net_107:13 0.0006925385 +14 optlc_net_107:14 0.0002345093 +15 optlc_net_107:15 0.0002345093 +16 optlc_net_107:14 chanx_right_in[0]:13 4.372474e-05 +17 optlc_net_107:15 chanx_right_in[0]:14 4.372474e-05 +18 optlc_net_107:9 chanx_right_in[0]:15 9.886736e-05 +19 optlc_net_107:8 chanx_right_in[0]:16 9.886736e-05 +20 optlc_net_107:9 chanx_right_in[18]:7 0.0003429861 +21 optlc_net_107:9 chanx_right_in[18]:11 1.96782e-05 +22 optlc_net_107:7 chanx_right_in[18]:9 1.196275e-06 +23 optlc_net_107:8 chanx_right_in[18]:10 1.96782e-05 +24 optlc_net_107:8 chanx_right_in[18]:11 0.0003429861 +25 optlc_net_107:6 chanx_right_in[18]:8 1.196275e-06 +26 optlc_net_107:13 ropt_net_129:8 5.850441e-05 +27 optlc_net_107:13 ropt_net_129:5 0.0001360349 +28 optlc_net_107:13 ropt_net_129:4 1.287833e-05 +29 optlc_net_107:5 ropt_net_129:4 0.0001360349 +30 optlc_net_107:11 ropt_net_129:10 7.250787e-07 +31 optlc_net_107:12 ropt_net_129:9 5.850441e-05 +32 optlc_net_107:12 ropt_net_129:5 1.287833e-05 +33 optlc_net_107:10 ropt_net_129:11 7.250787e-07 +34 optlc_net_107:13 ropt_net_142:5 7.49867e-05 +35 optlc_net_107:5 ropt_net_142:4 7.49867e-05 +36 optlc_net_107:13 ropt_net_163:4 1.714439e-05 +37 optlc_net_107:11 ropt_net_163:3 0.0001272755 +38 optlc_net_107:12 ropt_net_163:5 1.714439e-05 +39 optlc_net_107:10 ropt_net_163:2 0.0001272755 + +*RES +0 optlc_108:HI optlc_net_107:15 0.152 +1 optlc_net_107:14 optlc_net_107:13 0.0045 +2 optlc_net_107:13 optlc_net_107:12 0.002995535 +3 optlc_net_107:13 optlc_net_107:5 0.009674107 +4 optlc_net_107:15 optlc_net_107:14 0.003622768 +5 optlc_net_107:4 optlc_net_107:3 0.001314732 +6 optlc_net_107:5 optlc_net_107:4 0.0045 +7 optlc_net_107:3 mux_bottom_ipin_9\/mux_l2_in_3_:A0 0.152 +8 optlc_net_107:11 optlc_net_107:10 0.003205357 +9 optlc_net_107:12 optlc_net_107:11 0.0045 +10 optlc_net_107:10 optlc_net_107:9 0.0045 +11 optlc_net_107:9 optlc_net_107:8 0.01149554 +12 optlc_net_107:7 optlc_net_107:6 0.0004933036 +13 optlc_net_107:8 optlc_net_107:7 0.0045 +14 optlc_net_107:6 mux_bottom_ipin_8\/mux_l2_in_3_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001137853 //LENGTH 8.720 LUMPCC 0.0002709323 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_3_:X O *L 0 *C 69.635 56.440 +*I mux_bottom_ipin_13\/mux_l3_in_1_:A0 I *L 0.001631 *C 69.175 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 69.175 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 69.460 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 69.460 64.215 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 69.460 56.485 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 69.460 56.440 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 69.635 56.440 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.206145e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.850368e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003313813 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003313813 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.744459e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.414845e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[17]:7 6.816258e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[17]:8 6.816258e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.353948e-06 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.353948e-06 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.194961e-05 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.194961e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_3_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001548913 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.006901786 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007490858 //LENGTH 5.110 LUMPCC 0.0001316404 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l3_in_0_:X O *L 0 *C 34.215 20.740 +*I mux_bottom_ipin_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 33.025 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 33.062 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 34.455 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 34.500 23.415 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 34.500 20.785 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 34.500 20.740 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 34.215 20.740 + +*CAP +0 mux_bottom_ipin_2\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.69846e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.69846e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001775411 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001775411 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.3935e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.245896e-05 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chanx_right_in[2]:29 6.582021e-05 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[2]:30 6.582021e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l3_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_2\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001243304 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348215 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009624361 //LENGTH 6.680 LUMPCC 0.0001808212 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l3_in_1_:X O *L 0 *C 42.495 20.400 +*I mux_bottom_ipin_6\/mux_l4_in_0_:A0 I *L 0.001631 *C 42.610 26.180 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 42.610 26.180 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 42.320 26.180 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 42.320 26.135 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 42.320 20.445 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 42.320 20.400 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 42.495 20.400 + +*CAP +0 mux_bottom_ipin_6\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.743467e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.985225e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002698582 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002698582 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.992509e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.268646e-05 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_2_sram[2]:7 8.872728e-05 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_2_sram[2]:12 1.683324e-06 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_2_sram[2]:8 8.872728e-05 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_2_sram[2]:16 1.683324e-06 + +*RES +0 mux_bottom_ipin_6\/mux_l3_in_1_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_6\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001576087 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005080357 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0] 0.008349933 //LENGTH 59.560 LUMPCC 0.0005171782 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l4_in_0_:X O *L 0 *C 16.275 17.680 +*I mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 15.895 71.945 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 17.080 17.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 17.080 72.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 15.895 71.945 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 17.435 72.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 17.480 72.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 17.480 72.080 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 17.480 72.073 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 17.480 17.688 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 17.480 17.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 17.480 17.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 17.435 17.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 16.312 17.680 + +*CAP +0 mux_bottom_ipin_10\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001276082 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.681895e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001725808 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001379897 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.598643e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.681895e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.003439049 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.003439049 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001276082 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 3.633029e-05 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 9.04575e-05 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 9.04575e-05 +14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.0002585891 +15 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.0002585891 + +*RES +0 mux_bottom_ipin_10\/mux_l4_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.001002232 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0045 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.00341 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.69697e-05 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.008520316 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00341 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.69697e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001375 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001342736 //LENGTH 8.935 LUMPCC 0.0003853154 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_3_:X O *L 0 *C 88.955 56.440 +*I mux_bottom_ipin_15\/mux_l3_in_1_:A0 I *L 0.001631 *C 92.290 60.520 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 92.252 60.520 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 91.125 60.520 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 91.080 60.520 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 91.080 56.485 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 91.035 56.440 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 88.993 56.440 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.719845e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.719845e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002364162 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002015809 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001915132 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001915132 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.715574e-07 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.715574e-07 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001234126 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001234126 +12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 ropt_net_116:8 5.430951e-05 +13 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 ropt_net_116:7 5.430951e-05 +14 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 ropt_net_116:5 1.3964e-05 +15 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 ropt_net_116:6 1.3964e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_3_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006696 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003602678 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001823661 + +*END + +*D_NET chanx_right_out[16] 0.0008275164 //LENGTH 5.670 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_716:X O *L 0 *C 98.900 28.900 +*P chanx_right_out[16] O *L 0.7423 *C 103.650 28.560 +*N chanx_right_out[16]:2 *C 102.128 28.560 +*N chanx_right_out[16]:3 *C 102.120 28.560 +*N chanx_right_out[16]:4 *C 102.075 28.560 +*N chanx_right_out[16]:5 *C 98.900 28.560 +*N chanx_right_out[16]:6 *C 98.900 28.900 + +*CAP +0 ropt_mt_inst_716:X 1e-06 +1 chanx_right_out[16] 0.0001180238 +2 chanx_right_out[16]:2 0.0001180238 +3 chanx_right_out[16]:3 3.85354e-05 +4 chanx_right_out[16]:4 0.0002372034 +5 chanx_right_out[16]:5 0.0002628952 +6 chanx_right_out[16]:6 5.183492e-05 + +*RES +0 ropt_mt_inst_716:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +2 chanx_right_out[16]:2 chanx_right_out[16] 0.000238525 +3 chanx_right_out[16]:4 chanx_right_out[16]:3 0.0045 +4 chanx_right_out[16]:6 chanx_right_out[16]:5 0.0003035715 +5 chanx_right_out[16]:5 chanx_right_out[16]:4 0.002834822 + +*END + +*D_NET ropt_net_130 0.00151855 //LENGTH 11.690 LUMPCC 0.0001006632 DR + +*CONN +*I FTB_33__32:X O *L 0 *C 12.420 19.720 +*I ropt_mt_inst_729:A I *L 0.001766 *C 7.820 23.120 +*N ropt_net_130:2 *C 7.783 23.120 +*N ropt_net_130:3 *C 6.485 23.120 +*N ropt_net_130:4 *C 6.440 23.075 +*N ropt_net_130:5 *C 6.440 19.765 +*N ropt_net_130:6 *C 6.485 19.720 +*N ropt_net_130:7 *C 12.383 19.720 + +*CAP +0 FTB_33__32:X 1e-06 +1 ropt_mt_inst_729:A 1e-06 +2 ropt_net_130:2 8.482969e-05 +3 ropt_net_130:3 8.482969e-05 +4 ropt_net_130:4 0.0002066475 +5 ropt_net_130:5 0.0002066475 +6 ropt_net_130:6 0.0004164662 +7 ropt_net_130:7 0.0004164662 +8 ropt_net_130:2 ropt_net_156:8 3.587876e-05 +9 ropt_net_130:3 ropt_net_156:7 3.587876e-05 +10 ropt_net_130:6 ropt_net_156:4 1.445285e-05 +11 ropt_net_130:7 ropt_net_156:3 1.445285e-05 + +*RES +0 FTB_33__32:X ropt_net_130:7 0.152 +1 ropt_net_130:2 ropt_mt_inst_729:A 0.152 +2 ropt_net_130:3 ropt_net_130:2 0.001158482 +3 ropt_net_130:4 ropt_net_130:3 0.0045 +4 ropt_net_130:6 ropt_net_130:5 0.0045 +5 ropt_net_130:5 ropt_net_130:4 0.002955357 +6 ropt_net_130:7 ropt_net_130:6 0.005265625 + +*END + +*D_NET chanx_left_out[14] 0.002150559 //LENGTH 13.660 LUMPCC 0.0004461519 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 11.695 20.060 +*P chanx_left_out[14] O *L 0.7423 *C 1.230 17.680 +*N chanx_left_out[14]:2 *C 11.033 17.680 +*N chanx_left_out[14]:3 *C 11.040 17.738 +*N chanx_left_out[14]:4 *C 11.040 20.015 +*N chanx_left_out[14]:5 *C 11.085 20.060 +*N chanx_left_out[14]:6 *C 11.658 20.060 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 chanx_left_out[14] 0.0006061137 +2 chanx_left_out[14]:2 0.0006061137 +3 chanx_left_out[14]:3 0.0001743876 +4 chanx_left_out[14]:4 0.0001743876 +5 chanx_left_out[14]:5 7.12022e-05 +6 chanx_left_out[14]:6 7.12022e-05 +7 chanx_left_out[14] ropt_net_150:6 0.000223076 +8 chanx_left_out[14]:2 ropt_net_150:7 0.000223076 + +*RES +0 ropt_mt_inst_755:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:6 chanx_left_out[14]:5 0.0005111608 +2 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +3 chanx_left_out[14]:4 chanx_left_out[14]:3 0.002033483 +4 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +5 chanx_left_out[14]:2 chanx_left_out[14] 0.001535725 + +*END + +*D_NET ropt_net_164 0.001032595 //LENGTH 8.450 LUMPCC 0.0002596824 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 101.855 8.840 +*I ropt_mt_inst_770:A I *L 0.001767 *C 97.825 6.800 +*N ropt_net_164:2 *C 97.863 6.800 +*N ropt_net_164:3 *C 102.535 6.800 +*N ropt_net_164:4 *C 102.580 6.845 +*N ropt_net_164:5 *C 102.580 8.795 +*N ropt_net_164:6 *C 102.535 8.840 +*N ropt_net_164:7 *C 101.892 8.840 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_164:2 0.0002389303 +3 ropt_net_164:3 0.0002389303 +4 ropt_net_164:4 8.197334e-05 +5 ropt_net_164:5 8.197334e-05 +6 ropt_net_164:6 6.45527e-05 +7 ropt_net_164:7 6.45527e-05 +8 ropt_net_164:4 chanx_right_out[18]:3 6.087067e-05 +9 ropt_net_164:5 chanx_right_out[18]:4 6.087067e-05 +10 ropt_net_164:2 ropt_net_135:7 6.869511e-05 +11 ropt_net_164:3 ropt_net_135:6 6.869511e-05 +12 ropt_net_164:4 ropt_net_135:5 2.754019e-07 +13 ropt_net_164:5 ropt_net_135:4 2.754019e-07 + +*RES +0 ropt_mt_inst_734:X ropt_net_164:7 0.152 +1 ropt_net_164:2 ropt_mt_inst_770:A 0.152 +2 ropt_net_164:3 ropt_net_164:2 0.004171875 +3 ropt_net_164:4 ropt_net_164:3 0.0045 +4 ropt_net_164:6 ropt_net_164:5 0.0045 +5 ropt_net_164:5 ropt_net_164:4 0.001741072 +6 ropt_net_164:7 ropt_net_164:6 0.0005736608 + +*END + +*D_NET chanx_left_out[15] 0.0009080681 //LENGTH 7.140 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 4.140 45.560 +*P chanx_left_out[15] O *L 0.7423 *C 1.298 42.160 +*N chanx_left_out[15]:2 *C 1.380 42.160 +*N chanx_left_out[15]:3 *C 1.380 42.218 +*N chanx_left_out[15]:4 *C 1.380 45.515 +*N chanx_left_out[15]:5 *C 1.425 45.560 +*N chanx_left_out[15]:6 *C 4.103 45.560 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 chanx_left_out[15] 4.121937e-05 +2 chanx_left_out[15]:2 4.121937e-05 +3 chanx_left_out[15]:3 0.0002137955 +4 chanx_left_out[15]:4 0.0002137955 +5 chanx_left_out[15]:5 0.0001985192 +6 chanx_left_out[15]:6 0.0001985192 + +*RES +0 ropt_mt_inst_769:X chanx_left_out[15]:6 0.152 +1 chanx_left_out[15]:6 chanx_left_out[15]:5 0.002390625 +2 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +3 chanx_left_out[15]:4 chanx_left_out[15]:3 0.002944197 +4 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +5 chanx_left_out[15]:2 chanx_left_out[15] 2.35e-05 + +*END + +*D_NET chanx_left_in[6] 0.0195191 //LENGTH 133.180 LUMPCC 0.006857659 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 28.560 +*I mux_bottom_ipin_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 38.895 22.780 +*I mux_bottom_ipin_12\/mux_l1_in_2_:A1 I *L 0.00198 *C 57.500 25.500 +*I ropt_mt_inst_720:A I *L 0.001767 *C 93.380 44.880 +*I mux_bottom_ipin_10\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.130 22.780 +*N chanx_left_in[6]:5 *C 25.168 22.780 +*N chanx_left_in[6]:6 *C 26.635 22.780 +*N chanx_left_in[6]:7 *C 26.680 22.825 +*N chanx_left_in[6]:8 *C 93.418 44.880 +*N chanx_left_in[6]:9 *C 93.795 44.880 +*N chanx_left_in[6]:10 *C 93.840 44.835 +*N chanx_left_in[6]:11 *C 93.840 36.098 +*N chanx_left_in[6]:12 *C 93.840 36.040 +*N chanx_left_in[6]:13 *C 51.988 36.040 +*N chanx_left_in[6]:14 *C 51.980 35.983 +*N chanx_left_in[6]:15 *C 51.980 34.340 +*N chanx_left_in[6]:16 *C 51.520 34.340 +*N chanx_left_in[6]:17 *C 57.463 25.500 +*N chanx_left_in[6]:18 *C 51.565 25.500 +*N chanx_left_in[6]:19 *C 51.520 25.545 +*N chanx_left_in[6]:20 *C 51.520 26.520 +*N chanx_left_in[6]:21 *C 51.475 26.520 +*N chanx_left_in[6]:22 *C 38.895 22.780 +*N chanx_left_in[6]:23 *C 38.640 22.780 +*N chanx_left_in[6]:24 *C 38.640 22.825 +*N chanx_left_in[6]:25 *C 38.640 26.475 +*N chanx_left_in[6]:26 *C 38.640 26.520 +*N chanx_left_in[6]:27 *C 26.725 26.520 +*N chanx_left_in[6]:28 *C 26.680 26.520 +*N chanx_left_in[6]:29 *C 26.680 28.503 +*N chanx_left_in[6]:30 *C 26.673 28.560 + +*CAP +0 chanx_left_in[6] 0.001057451 +1 mux_bottom_ipin_2\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_12\/mux_l1_in_2_:A1 1e-06 +3 ropt_mt_inst_720:A 1e-06 +4 mux_bottom_ipin_10\/mux_l2_in_1_:A0 1e-06 +5 chanx_left_in[6]:5 0.0001186539 +6 chanx_left_in[6]:6 0.0001186539 +7 chanx_left_in[6]:7 0.0002060627 +8 chanx_left_in[6]:8 4.027001e-05 +9 chanx_left_in[6]:9 4.027001e-05 +10 chanx_left_in[6]:10 0.0004957087 +11 chanx_left_in[6]:11 0.0004957087 +12 chanx_left_in[6]:12 0.001503858 +13 chanx_left_in[6]:13 0.001503858 +14 chanx_left_in[6]:14 0.0001111606 +15 chanx_left_in[6]:15 0.0001385785 +16 chanx_left_in[6]:16 0.0004487936 +17 chanx_left_in[6]:17 0.0002485124 +18 chanx_left_in[6]:18 0.0002485124 +19 chanx_left_in[6]:19 6.701001e-05 +20 chanx_left_in[6]:20 0.0005203515 +21 chanx_left_in[6]:21 0.0008012814 +22 chanx_left_in[6]:22 5.292851e-05 +23 chanx_left_in[6]:23 5.536025e-05 +24 chanx_left_in[6]:24 0.0002239469 +25 chanx_left_in[6]:25 0.0002239469 +26 chanx_left_in[6]:26 0.001613119 +27 chanx_left_in[6]:27 0.0007776973 +28 chanx_left_in[6]:28 0.0003626994 +29 chanx_left_in[6]:29 0.0001255977 +30 chanx_left_in[6]:30 0.001057451 +31 chanx_left_in[6]:13 chanx_left_in[4]:35 0.0003451736 +32 chanx_left_in[6]:12 chanx_left_in[4]:34 0.0003451736 +33 chanx_left_in[6]:13 chanx_left_in[8]:17 7.400091e-05 +34 chanx_left_in[6]:13 chanx_left_in[8]:16 0.000267021 +35 chanx_left_in[6]:12 chanx_left_in[8]:15 0.000267021 +36 chanx_left_in[6]:12 chanx_left_in[8]:16 7.400091e-05 +37 chanx_left_in[6] chanx_left_in[12]:22 0.001008167 +38 chanx_left_in[6]:27 chanx_left_in[12]:22 6.306102e-06 +39 chanx_left_in[6]:13 chanx_left_in[12]:15 5.053702e-06 +40 chanx_left_in[6]:13 chanx_left_in[12]:10 0.000834647 +41 chanx_left_in[6]:12 chanx_left_in[12]:9 0.000834647 +42 chanx_left_in[6]:12 chanx_left_in[12]:14 5.053702e-06 +43 chanx_left_in[6]:26 chanx_left_in[12]:21 6.306102e-06 +44 chanx_left_in[6]:30 chanx_left_in[12]:21 0.001008167 +45 chanx_left_in[6]:13 chanx_right_in[9]:20 0.0003467275 +46 chanx_left_in[6]:12 chanx_right_in[9] 0.0003467275 +47 chanx_left_in[6]:14 mux_tree_tapbuf_size10_6_sram[0]:20 6.403086e-07 +48 chanx_left_in[6]:18 mux_tree_tapbuf_size10_6_sram[0]:11 0.0002073573 +49 chanx_left_in[6]:18 mux_tree_tapbuf_size10_6_sram[0]:10 2.187338e-05 +50 chanx_left_in[6]:19 mux_tree_tapbuf_size10_6_sram[0]:12 2.549316e-07 +51 chanx_left_in[6]:17 mux_tree_tapbuf_size10_6_sram[0]:5 2.187338e-05 +52 chanx_left_in[6]:17 mux_tree_tapbuf_size10_6_sram[0]:10 0.0002073573 +53 chanx_left_in[6]:26 mux_tree_tapbuf_size10_6_sram[0]:11 4.782337e-05 +54 chanx_left_in[6]:21 mux_tree_tapbuf_size10_6_sram[0]:10 4.782337e-05 +55 chanx_left_in[6]:20 mux_tree_tapbuf_size10_6_sram[0]:12 2.313304e-06 +56 chanx_left_in[6]:20 mux_tree_tapbuf_size10_6_sram[0]:15 2.811262e-06 +57 chanx_left_in[6]:20 mux_tree_tapbuf_size10_6_sram[0]:19 4.625477e-06 +58 chanx_left_in[6]:16 mux_tree_tapbuf_size10_6_sram[0]:20 4.625477e-06 +59 chanx_left_in[6]:16 mux_tree_tapbuf_size10_6_sram[0]:15 2.313304e-06 +60 chanx_left_in[6]:16 mux_tree_tapbuf_size10_6_sram[0]:18 2.556331e-06 +61 chanx_left_in[6]:15 mux_tree_tapbuf_size10_6_sram[0]:19 6.403086e-07 +62 chanx_left_in[6] chanx_left_out[11] 0.0002542877 +63 chanx_left_in[6]:30 chanx_left_out[11]:2 0.0002542877 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:30 0.003985991 +1 chanx_left_in[6]:27 chanx_left_in[6]:26 0.01063839 +2 chanx_left_in[6]:28 chanx_left_in[6]:27 0.0045 +3 chanx_left_in[6]:28 chanx_left_in[6]:7 0.003299107 +4 chanx_left_in[6]:14 chanx_left_in[6]:13 0.00341 +5 chanx_left_in[6]:13 chanx_left_in[6]:12 0.006556891 +6 chanx_left_in[6]:11 chanx_left_in[6]:10 0.007801339 +7 chanx_left_in[6]:12 chanx_left_in[6]:11 0.00341 +8 chanx_left_in[6]:9 chanx_left_in[6]:8 0.0003370536 +9 chanx_left_in[6]:10 chanx_left_in[6]:9 0.0045 +10 chanx_left_in[6]:8 ropt_mt_inst_720:A 0.152 +11 chanx_left_in[6]:18 chanx_left_in[6]:17 0.005265625 +12 chanx_left_in[6]:19 chanx_left_in[6]:18 0.0045 +13 chanx_left_in[6]:17 mux_bottom_ipin_12\/mux_l1_in_2_:A1 0.152 +14 chanx_left_in[6]:26 chanx_left_in[6]:25 0.0045 +15 chanx_left_in[6]:26 chanx_left_in[6]:21 0.01145982 +16 chanx_left_in[6]:25 chanx_left_in[6]:24 0.003258929 +17 chanx_left_in[6]:23 chanx_left_in[6]:22 0.000138587 +18 chanx_left_in[6]:24 chanx_left_in[6]:23 0.0045 +19 chanx_left_in[6]:22 mux_bottom_ipin_2\/mux_l2_in_1_:A0 0.152 +20 chanx_left_in[6]:6 chanx_left_in[6]:5 0.001310268 +21 chanx_left_in[6]:7 chanx_left_in[6]:6 0.0045 +22 chanx_left_in[6]:5 mux_bottom_ipin_10\/mux_l2_in_1_:A0 0.152 +23 chanx_left_in[6]:29 chanx_left_in[6]:28 0.001770089 +24 chanx_left_in[6]:30 chanx_left_in[6]:29 0.00341 +25 chanx_left_in[6]:21 chanx_left_in[6]:20 0.0045 +26 chanx_left_in[6]:20 chanx_left_in[6]:19 0.0008705358 +27 chanx_left_in[6]:20 chanx_left_in[6]:16 0.006982143 +28 chanx_left_in[6]:16 chanx_left_in[6]:15 0.0004107143 +29 chanx_left_in[6]:15 chanx_left_in[6]:14 0.001466518 + +*END + +*D_NET top_grid_pin_24_[0] 0.0008519507 //LENGTH 7.440 LUMPCC 0.0001266356 DR + +*CONN +*I mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.140 69.700 +*P top_grid_pin_24_[0] O *L 0.7423 *C 2.300 74.835 +*N top_grid_pin_24_[0]:2 *C 2.300 69.745 +*N top_grid_pin_24_[0]:3 *C 2.345 69.700 +*N top_grid_pin_24_[0]:4 *C 4.103 69.700 + +*CAP +0 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_24_[0] 0.000245961 +2 top_grid_pin_24_[0]:2 0.000245961 +3 top_grid_pin_24_[0]:3 0.0001161966 +4 top_grid_pin_24_[0]:4 0.0001161966 +5 top_grid_pin_24_[0] ropt_net_133:5 6.331781e-05 +6 top_grid_pin_24_[0]:2 ropt_net_133:6 6.331781e-05 + +*RES +0 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_24_[0]:4 0.152 +1 top_grid_pin_24_[0]:3 top_grid_pin_24_[0]:2 0.0045 +2 top_grid_pin_24_[0]:2 top_grid_pin_24_[0] 0.004544643 +3 top_grid_pin_24_[0]:4 top_grid_pin_24_[0]:3 0.001569197 + +*END + +*D_NET top_grid_pin_28_[0] 0.001021814 //LENGTH 8.390 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 68.540 72.080 +*P top_grid_pin_28_[0] O *L 0.7423 *C 73.600 74.835 +*N top_grid_pin_28_[0]:2 *C 73.600 72.805 +*N top_grid_pin_28_[0]:3 *C 73.555 72.760 +*N top_grid_pin_28_[0]:4 *C 68.540 72.760 +*N top_grid_pin_28_[0]:5 *C 68.540 72.080 + +*CAP +0 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_28_[0] 0.0001339287 +2 top_grid_pin_28_[0]:2 0.0001339287 +3 top_grid_pin_28_[0]:3 0.0003282576 +4 top_grid_pin_28_[0]:4 0.0003652837 +5 top_grid_pin_28_[0]:5 5.94152e-05 + +*RES +0 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_28_[0]:5 0.152 +1 top_grid_pin_28_[0]:3 top_grid_pin_28_[0]:2 0.0045 +2 top_grid_pin_28_[0]:2 top_grid_pin_28_[0] 0.0018125 +3 top_grid_pin_28_[0]:5 top_grid_pin_28_[0]:4 0.0006071429 +4 top_grid_pin_28_[0]:4 top_grid_pin_28_[0]:3 0.004477679 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.004842672 //LENGTH 38.190 LUMPCC 0.0001012172 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 95.985 36.720 +*I mux_bottom_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 91.180 34.000 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 86.195 39.100 +*I mux_bottom_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 87.960 31.280 +*I mux_bottom_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 85.220 25.500 +*I mux_bottom_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 84.280 29.240 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 91.255 34.330 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 91.130 34.680 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 84.295 29.240 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 85.183 25.500 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 84.685 25.500 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 84.640 25.545 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 84.640 29.195 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 84.685 29.240 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 87.815 29.240 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 87.860 29.285 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 87.860 31.280 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 87.860 31.280 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 88.320 31.280 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 88.320 34.635 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 88.365 34.680 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 86.233 39.100 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 91.035 39.100 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 91.080 39.055 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 91.080 34.725 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 91.175 34.650 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 91.255 34.000 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 95.635 34.000 +*N mux_tree_tapbuf_size10_0_sram[1]:28 *C 95.680 34.045 +*N mux_tree_tapbuf_size10_0_sram[1]:29 *C 95.680 36.675 +*N mux_tree_tapbuf_size10_0_sram[1]:30 *C 95.680 36.720 +*N mux_tree_tapbuf_size10_0_sram[1]:31 *C 95.985 36.720 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_0\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_0\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_ipin_0\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 3.244444e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:7 2.30913e-05 +8 mux_tree_tapbuf_size10_0_sram[1]:8 6.484069e-05 +9 mux_tree_tapbuf_size10_0_sram[1]:9 5.862423e-05 +10 mux_tree_tapbuf_size10_0_sram[1]:10 5.862423e-05 +11 mux_tree_tapbuf_size10_0_sram[1]:11 0.0002347953 +12 mux_tree_tapbuf_size10_0_sram[1]:12 0.0002347953 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.0003211561 +14 mux_tree_tapbuf_size10_0_sram[1]:14 0.0002563154 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0001291666 +16 mux_tree_tapbuf_size10_0_sram[1]:16 3.260153e-05 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0001657818 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.0002370603 +19 mux_tree_tapbuf_size10_0_sram[1]:19 0.0002004451 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0001967257 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.000330016 +22 mux_tree_tapbuf_size10_0_sram[1]:22 0.000330016 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.000279177 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.000279177 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0002606949 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.0003223175 +27 mux_tree_tapbuf_size10_0_sram[1]:27 0.0002489951 +28 mux_tree_tapbuf_size10_0_sram[1]:28 0.0001645727 +29 mux_tree_tapbuf_size10_0_sram[1]:29 0.0001645727 +30 mux_tree_tapbuf_size10_0_sram[1]:30 5.684883e-05 +31 mux_tree_tapbuf_size10_0_sram[1]:31 5.259898e-05 +32 mux_tree_tapbuf_size10_0_sram[1]:26 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.060861e-05 +33 mux_tree_tapbuf_size10_0_sram[1]:27 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.060861e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:31 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:26 mux_bottom_ipin_0\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.0005803572 +3 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:6 0.0002946429 +4 mux_tree_tapbuf_size10_0_sram[1]:9 mux_bottom_ipin_0\/mux_l2_in_2_:S 0.152 +5 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.0004441965 +6 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:8 0.0002119565 +9 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.003258929 +10 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0045 +11 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:20 0.002508929 +12 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:7 4.017857e-05 +13 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.003866071 +14 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.004287947 +15 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0045 +16 mux_tree_tapbuf_size10_0_sram[1]:21 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0045 +18 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.002995535 +19 mux_tree_tapbuf_size10_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:26 0.003910715 +20 mux_tree_tapbuf_size10_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:27 0.0045 +21 mux_tree_tapbuf_size10_0_sram[1]:30 mux_tree_tapbuf_size10_0_sram[1]:29 0.0045 +22 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:28 0.002348214 +23 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:30 0.0001657609 +24 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:13 0.002794643 +25 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0045 +26 mux_tree_tapbuf_size10_0_sram[1]:8 mux_bottom_ipin_0\/mux_l2_in_3_:S 0.152 +27 mux_tree_tapbuf_size10_0_sram[1]:16 mux_bottom_ipin_0\/mux_l2_in_1_:S 0.152 +28 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +29 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:15 0.00178125 +30 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[1] 0.004896644 //LENGTH 37.640 LUMPCC 0.00013747 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.905 11.900 +*I mux_bottom_ipin_4\/mux_l2_in_2_:S I *L 0.00357 *C 63.580 12.535 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.515 9.860 +*I mux_bottom_ipin_4\/mux_l2_in_3_:S I *L 0.00357 *C 69.560 14.670 +*I mux_bottom_ipin_4\/mux_l2_in_0_:S I *L 0.00357 *C 64.520 19.720 +*I mux_bottom_ipin_4\/mux_l2_in_1_:S I *L 0.00357 *C 65.880 17.975 +*N mux_tree_tapbuf_size10_2_sram[1]:6 *C 65.880 17.975 +*N mux_tree_tapbuf_size10_2_sram[1]:7 *C 64.558 19.720 +*N mux_tree_tapbuf_size10_2_sram[1]:8 *C 65.735 19.720 +*N mux_tree_tapbuf_size10_2_sram[1]:9 *C 65.780 19.675 +*N mux_tree_tapbuf_size10_2_sram[1]:10 *C 65.780 17.725 +*N mux_tree_tapbuf_size10_2_sram[1]:11 *C 65.918 17.680 +*N mux_tree_tapbuf_size10_2_sram[1]:12 *C 69.415 17.680 +*N mux_tree_tapbuf_size10_2_sram[1]:13 *C 69.460 17.635 +*N mux_tree_tapbuf_size10_2_sram[1]:14 *C 69.460 15.005 +*N mux_tree_tapbuf_size10_2_sram[1]:15 *C 69.460 14.960 +*N mux_tree_tapbuf_size10_2_sram[1]:16 *C 69.560 14.670 +*N mux_tree_tapbuf_size10_2_sram[1]:17 *C 69.560 14.280 +*N mux_tree_tapbuf_size10_2_sram[1]:18 *C 70.795 14.280 +*N mux_tree_tapbuf_size10_2_sram[1]:19 *C 70.840 14.235 +*N mux_tree_tapbuf_size10_2_sram[1]:20 *C 59.515 9.860 +*N mux_tree_tapbuf_size10_2_sram[1]:21 *C 59.340 9.860 +*N mux_tree_tapbuf_size10_2_sram[1]:22 *C 59.340 9.905 +*N mux_tree_tapbuf_size10_2_sram[1]:23 *C 59.340 12.535 +*N mux_tree_tapbuf_size10_2_sram[1]:24 *C 59.385 12.580 +*N mux_tree_tapbuf_size10_2_sram[1]:25 *C 63.580 12.535 +*N mux_tree_tapbuf_size10_2_sram[1]:26 *C 63.940 12.580 +*N mux_tree_tapbuf_size10_2_sram[1]:27 *C 63.940 12.240 +*N mux_tree_tapbuf_size10_2_sram[1]:28 *C 66.195 12.240 +*N mux_tree_tapbuf_size10_2_sram[1]:29 *C 66.240 12.195 +*N mux_tree_tapbuf_size10_2_sram[1]:30 *C 66.240 11.617 +*N mux_tree_tapbuf_size10_2_sram[1]:31 *C 66.248 11.560 +*N mux_tree_tapbuf_size10_2_sram[1]:32 *C 70.833 11.560 +*N mux_tree_tapbuf_size10_2_sram[1]:33 *C 70.840 11.560 +*N mux_tree_tapbuf_size10_2_sram[1]:34 *C 70.840 11.945 +*N mux_tree_tapbuf_size10_2_sram[1]:35 *C 70.885 11.900 +*N mux_tree_tapbuf_size10_2_sram[1]:36 *C 73.868 11.900 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_2_:S 1e-06 +2 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_4\/mux_l2_in_3_:S 1e-06 +4 mux_bottom_ipin_4\/mux_l2_in_0_:S 1e-06 +5 mux_bottom_ipin_4\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_2_sram[1]:6 7.286674e-05 +7 mux_tree_tapbuf_size10_2_sram[1]:7 0.0001142856 +8 mux_tree_tapbuf_size10_2_sram[1]:8 0.0001142856 +9 mux_tree_tapbuf_size10_2_sram[1]:9 0.0001311071 +10 mux_tree_tapbuf_size10_2_sram[1]:10 0.0001311071 +11 mux_tree_tapbuf_size10_2_sram[1]:11 0.0002954295 +12 mux_tree_tapbuf_size10_2_sram[1]:12 0.0002580741 +13 mux_tree_tapbuf_size10_2_sram[1]:13 0.0001627048 +14 mux_tree_tapbuf_size10_2_sram[1]:14 0.0001627048 +15 mux_tree_tapbuf_size10_2_sram[1]:15 6.599611e-05 +16 mux_tree_tapbuf_size10_2_sram[1]:16 9.142311e-05 +17 mux_tree_tapbuf_size10_2_sram[1]:17 0.0001319745 +18 mux_tree_tapbuf_size10_2_sram[1]:18 0.0001011931 +19 mux_tree_tapbuf_size10_2_sram[1]:19 0.00014573 +20 mux_tree_tapbuf_size10_2_sram[1]:20 4.909791e-05 +21 mux_tree_tapbuf_size10_2_sram[1]:21 5.390724e-05 +22 mux_tree_tapbuf_size10_2_sram[1]:22 0.0001728528 +23 mux_tree_tapbuf_size10_2_sram[1]:23 0.0001728528 +24 mux_tree_tapbuf_size10_2_sram[1]:24 0.0002410441 +25 mux_tree_tapbuf_size10_2_sram[1]:25 0.0002789403 +26 mux_tree_tapbuf_size10_2_sram[1]:26 5.638127e-05 +27 mux_tree_tapbuf_size10_2_sram[1]:27 0.0001849421 +28 mux_tree_tapbuf_size10_2_sram[1]:28 0.0001611321 +29 mux_tree_tapbuf_size10_2_sram[1]:29 5.2123e-05 +30 mux_tree_tapbuf_size10_2_sram[1]:30 5.2123e-05 +31 mux_tree_tapbuf_size10_2_sram[1]:31 0.0003340204 +32 mux_tree_tapbuf_size10_2_sram[1]:32 0.0003340204 +33 mux_tree_tapbuf_size10_2_sram[1]:33 5.642447e-05 +34 mux_tree_tapbuf_size10_2_sram[1]:34 0.0001643016 +35 mux_tree_tapbuf_size10_2_sram[1]:35 0.0002050641 +36 mux_tree_tapbuf_size10_2_sram[1]:36 0.0002050641 +37 mux_tree_tapbuf_size10_2_sram[1]:25 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.873501e-05 +38 mux_tree_tapbuf_size10_2_sram[1]:24 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.873501e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_2_sram[1]:36 0.152 +1 mux_tree_tapbuf_size10_2_sram[1]:7 mux_bottom_ipin_4\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[1]:8 mux_tree_tapbuf_size10_2_sram[1]:7 0.001051339 +3 mux_tree_tapbuf_size10_2_sram[1]:9 mux_tree_tapbuf_size10_2_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size10_2_sram[1]:11 mux_tree_tapbuf_size10_2_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size10_2_sram[1]:11 mux_tree_tapbuf_size10_2_sram[1]:6 0.0001271552 +6 mux_tree_tapbuf_size10_2_sram[1]:10 mux_tree_tapbuf_size10_2_sram[1]:9 0.001741071 +7 mux_tree_tapbuf_size10_2_sram[1]:16 mux_bottom_ipin_4\/mux_l2_in_3_:S 0.152 +8 mux_tree_tapbuf_size10_2_sram[1]:16 mux_tree_tapbuf_size10_2_sram[1]:15 0.0001686047 +9 mux_tree_tapbuf_size10_2_sram[1]:28 mux_tree_tapbuf_size10_2_sram[1]:27 0.002013393 +10 mux_tree_tapbuf_size10_2_sram[1]:29 mux_tree_tapbuf_size10_2_sram[1]:28 0.0045 +11 mux_tree_tapbuf_size10_2_sram[1]:30 mux_tree_tapbuf_size10_2_sram[1]:29 0.000515625 +12 mux_tree_tapbuf_size10_2_sram[1]:31 mux_tree_tapbuf_size10_2_sram[1]:30 0.00341 +13 mux_tree_tapbuf_size10_2_sram[1]:33 mux_tree_tapbuf_size10_2_sram[1]:32 0.00341 +14 mux_tree_tapbuf_size10_2_sram[1]:32 mux_tree_tapbuf_size10_2_sram[1]:31 0.0007183166 +15 mux_tree_tapbuf_size10_2_sram[1]:18 mux_tree_tapbuf_size10_2_sram[1]:17 0.001102679 +16 mux_tree_tapbuf_size10_2_sram[1]:19 mux_tree_tapbuf_size10_2_sram[1]:18 0.0045 +17 mux_tree_tapbuf_size10_2_sram[1]:25 mux_bottom_ipin_4\/mux_l2_in_2_:S 0.152 +18 mux_tree_tapbuf_size10_2_sram[1]:25 mux_tree_tapbuf_size10_2_sram[1]:24 0.003745536 +19 mux_tree_tapbuf_size10_2_sram[1]:35 mux_tree_tapbuf_size10_2_sram[1]:34 0.0045 +20 mux_tree_tapbuf_size10_2_sram[1]:34 mux_tree_tapbuf_size10_2_sram[1]:33 0.0001850962 +21 mux_tree_tapbuf_size10_2_sram[1]:34 mux_tree_tapbuf_size10_2_sram[1]:19 0.002044643 +22 mux_tree_tapbuf_size10_2_sram[1]:36 mux_tree_tapbuf_size10_2_sram[1]:35 0.002662946 +23 mux_tree_tapbuf_size10_2_sram[1]:12 mux_tree_tapbuf_size10_2_sram[1]:11 0.003122768 +24 mux_tree_tapbuf_size10_2_sram[1]:13 mux_tree_tapbuf_size10_2_sram[1]:12 0.0045 +25 mux_tree_tapbuf_size10_2_sram[1]:15 mux_tree_tapbuf_size10_2_sram[1]:14 0.0045 +26 mux_tree_tapbuf_size10_2_sram[1]:14 mux_tree_tapbuf_size10_2_sram[1]:13 0.002348214 +27 mux_tree_tapbuf_size10_2_sram[1]:6 mux_bottom_ipin_4\/mux_l2_in_1_:S 0.152 +28 mux_tree_tapbuf_size10_2_sram[1]:20 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +29 mux_tree_tapbuf_size10_2_sram[1]:21 mux_tree_tapbuf_size10_2_sram[1]:20 9.51087e-05 +30 mux_tree_tapbuf_size10_2_sram[1]:22 mux_tree_tapbuf_size10_2_sram[1]:21 0.0045 +31 mux_tree_tapbuf_size10_2_sram[1]:24 mux_tree_tapbuf_size10_2_sram[1]:23 0.0045 +32 mux_tree_tapbuf_size10_2_sram[1]:23 mux_tree_tapbuf_size10_2_sram[1]:22 0.002348214 +33 mux_tree_tapbuf_size10_2_sram[1]:26 mux_tree_tapbuf_size10_2_sram[1]:25 0.0003214286 +34 mux_tree_tapbuf_size10_2_sram[1]:27 mux_tree_tapbuf_size10_2_sram[1]:26 0.0003035715 +35 mux_tree_tapbuf_size10_2_sram[1]:17 mux_tree_tapbuf_size10_2_sram[1]:16 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[1] 0.003712686 //LENGTH 27.675 LUMPCC 7.736096e-05 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 20.855 60.520 +*I mux_bottom_ipin_9\/mux_l2_in_2_:S I *L 0.00357 *C 12.420 55.930 +*I mux_bottom_ipin_9\/mux_l2_in_1_:S I *L 0.00357 *C 14.360 55.685 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 13.455 64.260 +*I mux_bottom_ipin_9\/mux_l2_in_3_:S I *L 0.00357 *C 10.480 58.480 +*I mux_bottom_ipin_9\/mux_l2_in_0_:S I *L 0.00357 *C 18.040 58.405 +*N mux_tree_tapbuf_size10_5_sram[1]:6 *C 18.040 58.405 +*N mux_tree_tapbuf_size10_5_sram[1]:7 *C 10.518 58.480 +*N mux_tree_tapbuf_size10_5_sram[1]:8 *C 11.500 58.480 +*N mux_tree_tapbuf_size10_5_sram[1]:9 *C 11.500 58.820 +*N mux_tree_tapbuf_size10_5_sram[1]:10 *C 11.960 58.820 +*N mux_tree_tapbuf_size10_5_sram[1]:11 *C 11.960 59.160 +*N mux_tree_tapbuf_size10_5_sram[1]:12 *C 13.418 64.260 +*N mux_tree_tapbuf_size10_5_sram[1]:13 *C 12.925 64.260 +*N mux_tree_tapbuf_size10_5_sram[1]:14 *C 12.880 64.215 +*N mux_tree_tapbuf_size10_5_sram[1]:15 *C 14.323 55.745 +*N mux_tree_tapbuf_size10_5_sram[1]:16 *C 12.420 55.930 +*N mux_tree_tapbuf_size10_5_sram[1]:17 *C 12.465 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:18 *C 12.420 55.805 +*N mux_tree_tapbuf_size10_5_sram[1]:19 *C 12.420 57.120 +*N mux_tree_tapbuf_size10_5_sram[1]:20 *C 12.880 57.120 +*N mux_tree_tapbuf_size10_5_sram[1]:21 *C 12.880 59.160 +*N mux_tree_tapbuf_size10_5_sram[1]:22 *C 12.880 59.160 +*N mux_tree_tapbuf_size10_5_sram[1]:23 *C 17.940 59.130 +*N mux_tree_tapbuf_size10_5_sram[1]:24 *C 17.940 59.205 +*N mux_tree_tapbuf_size10_5_sram[1]:25 *C 17.940 60.475 +*N mux_tree_tapbuf_size10_5_sram[1]:26 *C 17.985 60.520 +*N mux_tree_tapbuf_size10_5_sram[1]:27 *C 20.818 60.520 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_9\/mux_l2_in_1_:S 1e-06 +3 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_ipin_9\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_9\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_5_sram[1]:6 7.674083e-05 +7 mux_tree_tapbuf_size10_5_sram[1]:7 9.373816e-05 +8 mux_tree_tapbuf_size10_5_sram[1]:8 0.0001216599 +9 mux_tree_tapbuf_size10_5_sram[1]:9 7.179471e-05 +10 mux_tree_tapbuf_size10_5_sram[1]:10 7.234735e-05 +11 mux_tree_tapbuf_size10_5_sram[1]:11 0.0001003836 +12 mux_tree_tapbuf_size10_5_sram[1]:12 5.665933e-05 +13 mux_tree_tapbuf_size10_5_sram[1]:13 5.665933e-05 +14 mux_tree_tapbuf_size10_5_sram[1]:14 0.0003030976 +15 mux_tree_tapbuf_size10_5_sram[1]:15 0.0001633204 +16 mux_tree_tapbuf_size10_5_sram[1]:16 4.742303e-05 +17 mux_tree_tapbuf_size10_5_sram[1]:17 0.0001791281 +18 mux_tree_tapbuf_size10_5_sram[1]:18 9.802549e-05 +19 mux_tree_tapbuf_size10_5_sram[1]:19 0.0001313343 +20 mux_tree_tapbuf_size10_5_sram[1]:20 0.0001505378 +21 mux_tree_tapbuf_size10_5_sram[1]:21 0.000454809 +22 mux_tree_tapbuf_size10_5_sram[1]:22 0.0004583819 +23 mux_tree_tapbuf_size10_5_sram[1]:23 0.0003993367 +24 mux_tree_tapbuf_size10_5_sram[1]:24 9.279106e-05 +25 mux_tree_tapbuf_size10_5_sram[1]:25 9.279106e-05 +26 mux_tree_tapbuf_size10_5_sram[1]:26 0.0002041829 +27 mux_tree_tapbuf_size10_5_sram[1]:27 0.0002041829 +28 mux_tree_tapbuf_size10_5_sram[1]:17 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.072328e-05 +29 mux_tree_tapbuf_size10_5_sram[1]:18 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.432976e-07 +30 mux_tree_tapbuf_size10_5_sram[1]:22 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.358634e-05 +31 mux_tree_tapbuf_size10_5_sram[1]:21 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.362756e-05 +32 mux_tree_tapbuf_size10_5_sram[1]:23 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.358634e-05 +33 mux_tree_tapbuf_size10_5_sram[1]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.072328e-05 +34 mux_tree_tapbuf_size10_5_sram[1]:19 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.432976e-07 +35 mux_tree_tapbuf_size10_5_sram[1]:20 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.362756e-05 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_5_sram[1]:27 0.152 +1 mux_tree_tapbuf_size10_5_sram[1]:17 mux_tree_tapbuf_size10_5_sram[1]:16 7.327587e-05 +2 mux_tree_tapbuf_size10_5_sram[1]:17 mux_tree_tapbuf_size10_5_sram[1]:15 0.001658482 +3 mux_tree_tapbuf_size10_5_sram[1]:18 mux_tree_tapbuf_size10_5_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size10_5_sram[1]:13 mux_tree_tapbuf_size10_5_sram[1]:12 0.0004397322 +5 mux_tree_tapbuf_size10_5_sram[1]:14 mux_tree_tapbuf_size10_5_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size10_5_sram[1]:12 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size10_5_sram[1]:7 mux_bottom_ipin_9\/mux_l2_in_3_:S 0.152 +8 mux_tree_tapbuf_size10_5_sram[1]:22 mux_tree_tapbuf_size10_5_sram[1]:21 0.0045 +9 mux_tree_tapbuf_size10_5_sram[1]:22 mux_tree_tapbuf_size10_5_sram[1]:11 0.0008214285 +10 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_5_sram[1]:20 0.001821429 +11 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_5_sram[1]:14 0.004513393 +12 mux_tree_tapbuf_size10_5_sram[1]:23 mux_tree_tapbuf_size10_5_sram[1]:22 0.004517857 +13 mux_tree_tapbuf_size10_5_sram[1]:23 mux_tree_tapbuf_size10_5_sram[1]:6 0.0006473215 +14 mux_tree_tapbuf_size10_5_sram[1]:24 mux_tree_tapbuf_size10_5_sram[1]:23 0.0045 +15 mux_tree_tapbuf_size10_5_sram[1]:26 mux_tree_tapbuf_size10_5_sram[1]:25 0.0045 +16 mux_tree_tapbuf_size10_5_sram[1]:25 mux_tree_tapbuf_size10_5_sram[1]:24 0.001133929 +17 mux_tree_tapbuf_size10_5_sram[1]:27 mux_tree_tapbuf_size10_5_sram[1]:26 0.002529018 +18 mux_tree_tapbuf_size10_5_sram[1]:16 mux_bottom_ipin_9\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_5_sram[1]:15 mux_bottom_ipin_9\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_5_sram[1]:6 mux_bottom_ipin_9\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_5_sram[1]:8 mux_tree_tapbuf_size10_5_sram[1]:7 0.0008772322 +22 mux_tree_tapbuf_size10_5_sram[1]:9 mux_tree_tapbuf_size10_5_sram[1]:8 0.0003035715 +23 mux_tree_tapbuf_size10_5_sram[1]:10 mux_tree_tapbuf_size10_5_sram[1]:9 0.0004107143 +24 mux_tree_tapbuf_size10_5_sram[1]:11 mux_tree_tapbuf_size10_5_sram[1]:10 0.0003035715 +25 mux_tree_tapbuf_size10_5_sram[1]:19 mux_tree_tapbuf_size10_5_sram[1]:18 0.001174107 +26 mux_tree_tapbuf_size10_5_sram[1]:20 mux_tree_tapbuf_size10_5_sram[1]:19 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[3] 0.001362372 //LENGTH 11.485 LUMPCC 9.630084e-05 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 69.305 69.360 +*I mem_bottom_ipin_13\/FTB_8__47:A I *L 0.001746 *C 71.300 69.360 +*I mux_bottom_ipin_13\/mux_l4_in_0_:S I *L 0.00357 *C 74.420 63.920 +*N mux_tree_tapbuf_size10_7_sram[3]:3 *C 74.383 63.920 +*N mux_tree_tapbuf_size10_7_sram[3]:4 *C 71.805 63.920 +*N mux_tree_tapbuf_size10_7_sram[3]:5 *C 71.760 63.965 +*N mux_tree_tapbuf_size10_7_sram[3]:6 *C 71.760 69.315 +*N mux_tree_tapbuf_size10_7_sram[3]:7 *C 71.715 69.360 +*N mux_tree_tapbuf_size10_7_sram[3]:8 *C 71.300 69.360 +*N mux_tree_tapbuf_size10_7_sram[3]:9 *C 69.343 69.360 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_13\/FTB_8__47:A 1e-06 +2 mux_bottom_ipin_13\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_7_sram[3]:3 0.0001772292 +4 mux_tree_tapbuf_size10_7_sram[3]:4 0.0001772292 +5 mux_tree_tapbuf_size10_7_sram[3]:5 0.0002996855 +6 mux_tree_tapbuf_size10_7_sram[3]:6 0.0002996855 +7 mux_tree_tapbuf_size10_7_sram[3]:7 3.531002e-05 +8 mux_tree_tapbuf_size10_7_sram[3]:8 0.0001676964 +9 mux_tree_tapbuf_size10_7_sram[3]:9 0.0001062357 +10 mux_tree_tapbuf_size10_7_sram[3]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.815042e-05 +11 mux_tree_tapbuf_size10_7_sram[3]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.815042e-05 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_7_sram[3]:9 0.152 +1 mux_tree_tapbuf_size10_7_sram[3]:7 mux_tree_tapbuf_size10_7_sram[3]:6 0.0045 +2 mux_tree_tapbuf_size10_7_sram[3]:6 mux_tree_tapbuf_size10_7_sram[3]:5 0.004776786 +3 mux_tree_tapbuf_size10_7_sram[3]:4 mux_tree_tapbuf_size10_7_sram[3]:3 0.002301339 +4 mux_tree_tapbuf_size10_7_sram[3]:5 mux_tree_tapbuf_size10_7_sram[3]:4 0.0045 +5 mux_tree_tapbuf_size10_7_sram[3]:3 mux_bottom_ipin_13\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_7_sram[3]:8 mem_bottom_ipin_13\/FTB_8__47:A 0.152 +7 mux_tree_tapbuf_size10_7_sram[3]:8 mux_tree_tapbuf_size10_7_sram[3]:7 0.0003705357 +8 mux_tree_tapbuf_size10_7_sram[3]:9 mux_tree_tapbuf_size10_7_sram[3]:8 0.001747768 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_1_ccff_tail[0] 0.0004358213 //LENGTH 3.300 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_1\/FTB_2__41:X O *L 0 *C 39.325 65.960 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.815 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 *C 38.815 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 *C 38.640 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 *C 38.640 64.305 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 *C 38.640 65.915 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 *C 38.685 65.960 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 *C 39.288 65.960 + +*CAP +0 mem_bottom_ipin_1\/FTB_2__41:X 1e-06 +1 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 5.322499e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 5.678328e-05 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0001015335 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0001015335 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 6.037303e-05 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 6.037303e-05 + +*RES +0 mem_bottom_ipin_1\/FTB_2__41:X mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_7_ccff_tail[0] 0.003815576 //LENGTH 31.990 LUMPCC 0.001236644 DR + +*CONN +*I mem_bottom_ipin_13\/FTB_8__47:X O *L 0 *C 74.295 69.020 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 73.315 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 *C 73.315 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 *C 73.140 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 *C 73.140 39.145 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 *C 73.140 68.975 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 *C 73.185 69.020 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 *C 74.258 69.020 + +*CAP +0 mem_bottom_ipin_13\/FTB_8__47:X 1e-06 +1 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 4.798305e-05 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 5.215426e-05 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.001149622 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.001149622 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 8.877427e-05 +7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 8.877427e-05 +8 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:172 4.519291e-06 +9 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:175 1.663117e-06 +10 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:177 4.1877e-05 +11 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:200 2.613196e-05 +12 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:202 1.893068e-05 +13 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:169 1.893068e-05 +14 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:176 1.663117e-06 +15 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:177 4.519291e-06 +16 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:200 4.1877e-05 +17 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:201 2.613196e-05 +18 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001097374 +19 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001097374 +20 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.153244e-05 +21 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.153244e-05 +22 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001324372 +23 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001324372 +24 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002314931 +25 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002314931 + +*RES +0 mem_bottom_ipin_13\/FTB_8__47:X mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.02663393 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.0009575893 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[1] 0.004281271 //LENGTH 31.680 LUMPCC 0.0004035817 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 35.725 63.920 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 29.155 66.300 +*I mux_bottom_ipin_7\/mux_l2_in_0_:S I *L 0.00357 *C 32.760 56.440 +*I mux_bottom_ipin_7\/mux_l2_in_2_:S I *L 0.00357 *C 24.480 55.760 +*I mux_bottom_ipin_7\/mux_l2_in_3_:S I *L 0.00357 *C 28.620 56.055 +*I mux_bottom_ipin_7\/mux_l2_in_1_:S I *L 0.00357 *C 33.220 58.190 +*N mux_tree_tapbuf_size8_3_sram[1]:6 *C 33.075 58.410 +*N mux_tree_tapbuf_size8_3_sram[1]:7 *C 33.190 58.550 +*N mux_tree_tapbuf_size8_3_sram[1]:8 *C 33.220 58.190 +*N mux_tree_tapbuf_size8_3_sram[1]:9 *C 28.620 56.055 +*N mux_tree_tapbuf_size8_3_sram[1]:10 *C 24.518 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:11 *C 28.620 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:12 *C 33.120 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:13 *C 32.775 56.440 +*N mux_tree_tapbuf_size8_3_sram[1]:14 *C 33.120 56.410 +*N mux_tree_tapbuf_size8_3_sram[1]:15 *C 33.120 56.485 +*N mux_tree_tapbuf_size8_3_sram[1]:16 *C 33.120 58.435 +*N mux_tree_tapbuf_size8_3_sram[1]:17 *C 33.120 58.480 +*N mux_tree_tapbuf_size8_3_sram[1]:18 *C 33.120 58.820 +*N mux_tree_tapbuf_size8_3_sram[1]:19 *C 35.375 58.820 +*N mux_tree_tapbuf_size8_3_sram[1]:20 *C 35.420 58.865 +*N mux_tree_tapbuf_size8_3_sram[1]:21 *C 29.193 66.300 +*N mux_tree_tapbuf_size8_3_sram[1]:22 *C 35.375 66.300 +*N mux_tree_tapbuf_size8_3_sram[1]:23 *C 35.420 66.255 +*N mux_tree_tapbuf_size8_3_sram[1]:24 *C 35.420 63.920 +*N mux_tree_tapbuf_size8_3_sram[1]:25 *C 35.420 63.920 +*N mux_tree_tapbuf_size8_3_sram[1]:26 *C 35.725 63.920 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_7\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_2_:S 1e-06 +4 mux_bottom_ipin_7\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_7\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size8_3_sram[1]:6 1.032734e-05 +7 mux_tree_tapbuf_size8_3_sram[1]:7 1.077643e-05 +8 mux_tree_tapbuf_size8_3_sram[1]:8 4.781573e-05 +9 mux_tree_tapbuf_size8_3_sram[1]:9 6.306237e-05 +10 mux_tree_tapbuf_size8_3_sram[1]:10 0.0002876311 +11 mux_tree_tapbuf_size8_3_sram[1]:11 0.0006473481 +12 mux_tree_tapbuf_size8_3_sram[1]:12 0.000371956 +13 mux_tree_tapbuf_size8_3_sram[1]:13 5.304145e-05 +14 mux_tree_tapbuf_size8_3_sram[1]:14 9.74826e-05 +15 mux_tree_tapbuf_size8_3_sram[1]:15 0.0001302396 +16 mux_tree_tapbuf_size8_3_sram[1]:16 0.0001302396 +17 mux_tree_tapbuf_size8_3_sram[1]:17 8.190151e-05 +18 mux_tree_tapbuf_size8_3_sram[1]:18 0.0001818921 +19 mux_tree_tapbuf_size8_3_sram[1]:19 0.0001626571 +20 mux_tree_tapbuf_size8_3_sram[1]:20 0.0002012951 +21 mux_tree_tapbuf_size8_3_sram[1]:21 0.0004249635 +22 mux_tree_tapbuf_size8_3_sram[1]:22 0.0004249635 +23 mux_tree_tapbuf_size8_3_sram[1]:23 9.872043e-05 +24 mux_tree_tapbuf_size8_3_sram[1]:24 0.0003318065 +25 mux_tree_tapbuf_size8_3_sram[1]:25 5.807331e-05 +26 mux_tree_tapbuf_size8_3_sram[1]:26 5.549679e-05 +27 mux_tree_tapbuf_size8_3_sram[1]:15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.213748e-07 +28 mux_tree_tapbuf_size8_3_sram[1]:16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.213748e-07 +29 mux_tree_tapbuf_size8_3_sram[1]:23 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.598185e-05 +30 mux_tree_tapbuf_size8_3_sram[1]:20 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001353876 +31 mux_tree_tapbuf_size8_3_sram[1]:24 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001353876 +32 mux_tree_tapbuf_size8_3_sram[1]:24 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.598185e-05 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_3_sram[1]:26 0.152 +1 mux_tree_tapbuf_size8_3_sram[1]:14 mux_tree_tapbuf_size8_3_sram[1]:13 0.0001875 +2 mux_tree_tapbuf_size8_3_sram[1]:14 mux_tree_tapbuf_size8_3_sram[1]:12 0.0005803572 +3 mux_tree_tapbuf_size8_3_sram[1]:15 mux_tree_tapbuf_size8_3_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:16 0.0045 +5 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:8 0.0001686047 +6 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:7 4.069768e-05 +7 mux_tree_tapbuf_size8_3_sram[1]:16 mux_tree_tapbuf_size8_3_sram[1]:15 0.001741072 +8 mux_tree_tapbuf_size8_3_sram[1]:22 mux_tree_tapbuf_size8_3_sram[1]:21 0.005520089 +9 mux_tree_tapbuf_size8_3_sram[1]:23 mux_tree_tapbuf_size8_3_sram[1]:22 0.0045 +10 mux_tree_tapbuf_size8_3_sram[1]:21 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size8_3_sram[1]:19 mux_tree_tapbuf_size8_3_sram[1]:18 0.002013393 +12 mux_tree_tapbuf_size8_3_sram[1]:20 mux_tree_tapbuf_size8_3_sram[1]:19 0.0045 +13 mux_tree_tapbuf_size8_3_sram[1]:9 mux_bottom_ipin_7\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size8_3_sram[1]:10 mux_bottom_ipin_7\/mux_l2_in_2_:S 0.152 +15 mux_tree_tapbuf_size8_3_sram[1]:8 mux_bottom_ipin_7\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size8_3_sram[1]:13 mux_bottom_ipin_7\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size8_3_sram[1]:25 mux_tree_tapbuf_size8_3_sram[1]:24 0.0045 +18 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:23 0.002084821 +19 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:20 0.004513393 +20 mux_tree_tapbuf_size8_3_sram[1]:26 mux_tree_tapbuf_size8_3_sram[1]:25 0.0001657609 +21 mux_tree_tapbuf_size8_3_sram[1]:11 mux_tree_tapbuf_size8_3_sram[1]:10 0.003662947 +22 mux_tree_tapbuf_size8_3_sram[1]:11 mux_tree_tapbuf_size8_3_sram[1]:9 0.0001271552 +23 mux_tree_tapbuf_size8_3_sram[1]:12 mux_tree_tapbuf_size8_3_sram[1]:11 0.004017857 +24 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:17 0.0003035715 +25 mux_tree_tapbuf_size8_3_sram[1]:7 mux_tree_tapbuf_size8_3_sram[1]:6 0.0001026786 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[3] 0.002968342 //LENGTH 22.520 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 90.465 66.300 +*I mux_bottom_ipin_15\/mux_l4_in_0_:S I *L 0.00357 *C 85.200 63.240 +*I mem_bottom_ipin_15\/FTB_17__56:A I *L 0.001746 *C 85.560 53.040 +*N mux_tree_tapbuf_size8_7_sram[3]:3 *C 85.598 53.040 +*N mux_tree_tapbuf_size8_7_sram[3]:4 *C 88.275 53.040 +*N mux_tree_tapbuf_size8_7_sram[3]:5 *C 88.320 53.085 +*N mux_tree_tapbuf_size8_7_sram[3]:6 *C 85.237 63.240 +*N mux_tree_tapbuf_size8_7_sram[3]:7 *C 88.275 63.240 +*N mux_tree_tapbuf_size8_7_sram[3]:8 *C 88.320 63.240 +*N mux_tree_tapbuf_size8_7_sram[3]:9 *C 88.320 66.255 +*N mux_tree_tapbuf_size8_7_sram[3]:10 *C 88.365 66.300 +*N mux_tree_tapbuf_size8_7_sram[3]:11 *C 90.428 66.300 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_15\/FTB_17__56:A 1e-06 +3 mux_tree_tapbuf_size8_7_sram[3]:3 0.0002330989 +4 mux_tree_tapbuf_size8_7_sram[3]:4 0.0002330989 +5 mux_tree_tapbuf_size8_7_sram[3]:5 0.0005922909 +6 mux_tree_tapbuf_size8_7_sram[3]:6 0.0002469915 +7 mux_tree_tapbuf_size8_7_sram[3]:7 0.0002469915 +8 mux_tree_tapbuf_size8_7_sram[3]:8 0.0008342976 +9 mux_tree_tapbuf_size8_7_sram[3]:9 0.00020746 +10 mux_tree_tapbuf_size8_7_sram[3]:10 0.000185556 +11 mux_tree_tapbuf_size8_7_sram[3]:11 0.000185556 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_7_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_7_sram[3]:7 mux_tree_tapbuf_size8_7_sram[3]:6 0.002712054 +2 mux_tree_tapbuf_size8_7_sram[3]:8 mux_tree_tapbuf_size8_7_sram[3]:7 0.0045 +3 mux_tree_tapbuf_size8_7_sram[3]:8 mux_tree_tapbuf_size8_7_sram[3]:5 0.009066964 +4 mux_tree_tapbuf_size8_7_sram[3]:6 mux_bottom_ipin_15\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_7_sram[3]:4 mux_tree_tapbuf_size8_7_sram[3]:3 0.002390625 +6 mux_tree_tapbuf_size8_7_sram[3]:5 mux_tree_tapbuf_size8_7_sram[3]:4 0.0045 +7 mux_tree_tapbuf_size8_7_sram[3]:3 mem_bottom_ipin_15\/FTB_17__56:A 0.152 +8 mux_tree_tapbuf_size8_7_sram[3]:10 mux_tree_tapbuf_size8_7_sram[3]:9 0.0045 +9 mux_tree_tapbuf_size8_7_sram[3]:9 mux_tree_tapbuf_size8_7_sram[3]:8 0.002691964 +10 mux_tree_tapbuf_size8_7_sram[3]:11 mux_tree_tapbuf_size8_7_sram[3]:10 0.001841518 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_5_ccff_tail[0] 0.002047008 //LENGTH 16.000 LUMPCC 0.0006275598 DR + +*CONN +*I mem_bottom_ipin_11\/FTB_15__54:X O *L 0 *C 36.575 41.480 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 41.575 37.060 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 *C 41.575 37.060 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 *C 41.400 37.060 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 *C 41.400 37.015 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 *C 41.400 34.385 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 *C 41.355 34.340 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 *C 36.845 34.340 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 *C 36.800 34.385 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 *C 36.800 41.435 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 *C 36.800 41.480 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 *C 36.575 41.480 + +*CAP +0 mem_bottom_ipin_11\/FTB_15__54:X 1e-06 +1 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 4.895281e-05 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 5.336858e-05 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.0001033689 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.0001033689 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.0001782761 +7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.0001782761 +8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 0.0003165695 +9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 0.0003165695 +10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 5.346978e-05 +11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 6.522788e-05 +12 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size8_1_sram[0]:5 8.52779e-05 +13 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size8_1_sram[0]:11 0.0001487204 +14 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size8_1_sram[0]:12 8.52779e-05 +15 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size8_1_sram[0]:10 0.0001487204 +16 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_1_sram[0]:9 7.965806e-05 +17 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_1_sram[0]:12 1.234971e-07 +18 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_1_sram[0]:5 1.234971e-07 +19 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_1_sram[0]:8 7.965806e-05 + +*RES +0 mem_bottom_ipin_11\/FTB_15__54:X mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 0.0001222826 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 0.006294643 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.004026785 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.0045 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.0045 +7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.002348214 +8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 9.510871e-05 +9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009315014 //LENGTH 7.155 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_2_:X O *L 0 *C 82.515 26.180 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 83.820 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 83.782 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 82.385 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 82.340 30.895 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 82.340 26.225 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 82.340 26.180 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 82.515 26.180 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001087471 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001087471 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002959287 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002959287 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.149955e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.865035e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001247768 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008788583 //LENGTH 7.330 LUMPCC 9.180335e-05 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_2_:X O *L 0 *C 48.585 56.440 +*I mux_bottom_ipin_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 47.285 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 47.323 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 47.795 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 47.840 61.495 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 47.840 56.485 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 47.885 56.440 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 48.547 56.440 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.722438e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.722438e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002570404 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002570404 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.826272e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.826272e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 4.590167e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 4.590167e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_2_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004473215 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006762067 //LENGTH 4.615 LUMPCC 0.00013747 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_2_:X O *L 0 *C 62.735 12.920 +*I mux_bottom_ipin_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 60.720 14.620 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 60.720 14.605 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 60.720 14.280 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 60.720 14.235 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 60.720 12.965 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 60.765 12.920 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 62.698 12.920 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.504222e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.725362e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.708274e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.708274e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001201377 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001201377 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_2_sram[1]:24 6.873501e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size10_2_sram[1]:25 6.873501e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_2_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001766305 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001133929 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0009216195 //LENGTH 6.990 LUMPCC 0.0001256443 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l3_in_1_:X O *L 0 *C 51.695 47.940 +*I mux_bottom_ipin_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 50.890 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 50.890 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 51.060 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 51.060 53.335 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 51.060 47.985 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 51.105 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 51.658 47.940 + +*CAP +0 mux_bottom_ipin_5\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.099809e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.585915e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002679874 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002679874 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.557163e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.557163e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_3_sram[3]:7 5.962832e-06 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_3_sram[3]:9 2.49881e-05 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_3_sram[3]:10 3.187124e-05 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_3_sram[3]:5 2.49881e-05 +12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_3_sram[3]:8 5.962832e-06 +13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_3_sram[3]:11 3.187124e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l3_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_5\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004776786 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003939091 //LENGTH 2.575 LUMPCC 0.0001656172 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l3_in_1_:X O *L 0 *C 11.325 37.400 +*I mux_bottom_ipin_8\/mux_l4_in_0_:A0 I *L 0.001631 *C 13.610 37.400 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 13.572 37.400 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 11.363 37.400 + +*CAP +0 mux_bottom_ipin_8\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001131459 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001131459 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.280861e-05 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.280861e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l3_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_8\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001973214 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001448766 //LENGTH 11.315 LUMPCC 0.0004314572 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_2_:X O *L 0 *C 9.375 55.080 +*I mux_bottom_ipin_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 9.200 63.580 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.200 63.580 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 9.200 63.920 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 8.785 63.920 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 8.740 63.875 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 8.740 55.125 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 8.785 55.080 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 9.338 55.080 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.694522e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.02424e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.223173e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003456132 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003456132 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.733156e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 7.733156e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[13]:16 5.792022e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[13]:15 5.792022e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[19]:14 5.714426e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[19]:13 5.714426e-05 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.458536e-06 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.920559e-05 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.920559e-05 +16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.458536e-06 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_2_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003705357 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.007812501 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0004933036 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005615321 //LENGTH 4.040 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_3_:X O *L 0 *C 65.495 29.240 +*I mux_bottom_ipin_12\/mux_l3_in_1_:A0 I *L 0.001631 *C 66.415 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 66.415 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 66.240 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 66.240 31.575 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 66.240 29.285 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 66.195 29.240 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 65.532 29.240 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.55292e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.631851e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001500958 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001500958 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.374646e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.374646e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_3_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002044643 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005915179 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003261308 //LENGTH 25.815 LUMPCC 0.0005980903 DR + +*CONN +*I mux_top_ipin_0\/mux_l1_in_0_:X O *L 0 *C 93.555 28.220 +*I mux_top_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 93.380 18.020 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 93.403 18.047 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 93.415 18.360 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 100.695 18.360 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 100.740 18.405 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 100.740 28.175 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 100.695 28.220 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 93.593 28.220 + +*CAP +0 mux_top_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.262146e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005014961 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004688746 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004672095 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004672095 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003619034 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003619034 +9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[0]:51 2.551043e-05 +10 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[0]:48 7.563282e-05 +11 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[0]:49 0.0001979019 +12 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[0]:50 2.551043e-05 +13 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[0]:47 7.563282e-05 +14 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[0]:48 0.0001979019 + +*RES +0 mux_top_ipin_0\/mux_l1_in_0_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_ipin_0\/mux_l2_in_0_:A1 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006500001 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.008723214 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.006341518 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002111487 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000451899 //LENGTH 2.865 LUMPCC 0.0002138889 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_2_:X O *L 0 *C 29.265 20.060 +*I mux_bottom_ipin_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 31.840 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 31.803 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 29.303 20.060 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000118005 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000118005 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_0_sram[1]:19 0.0001069445 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_0_sram[1]:18 0.0001069445 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_2_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002232143 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005436417 //LENGTH 3.630 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l3_in_0_:X O *L 0 *C 43.985 52.360 +*I mux_bottom_ipin_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 42.685 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 42.723 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 43.655 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 43.700 50.705 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 43.700 52.315 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 43.700 52.360 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 43.985 52.360 + +*CAP +0 mux_bottom_ipin_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.571893e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.571893e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001170497 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001170497 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.172243e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.4382e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l3_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_3\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008325893 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001129719 //LENGTH 8.600 LUMPCC 0.0001312046 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_0_:X O *L 0 *C 31.915 56.440 +*I mux_bottom_ipin_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 29.345 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 29.383 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 30.775 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 30.820 61.495 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 30.820 56.485 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 30.865 56.440 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 31.878 56.440 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.801821e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.801821e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003308117 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003308117 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.942748e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.942748e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_3_sram[2]:16 6.56023e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_3_sram[2]:17 6.56023e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001243304 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006516832 //LENGTH 4.840 LUMPCC 0.0001048894 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_2_:X O *L 0 *C 26.855 15.300 +*I mux_bottom_ipin_10\/mux_l3_in_1_:A1 I *L 0.00198 *C 25.665 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 25.703 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 26.175 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 26.220 17.975 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 26.220 15.345 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 26.265 15.300 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 26.818 15.300 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.314591e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.314591e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001425811 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001425811 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.666987e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.666987e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.302881e-07 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.302881e-07 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.16144e-05 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.16144e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_2_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003843879 //LENGTH 2.475 LUMPCC 0.0001813775 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l3_in_1_:X O *L 0 *C 30.995 47.940 +*I mux_bottom_ipin_11\/mux_l4_in_0_:A0 I *L 0.001631 *C 28.810 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 28.848 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 30.958 47.940 + +*CAP +0 mux_bottom_ipin_11\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001005052 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001005052 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_5_sram[2]:5 9.068874e-05 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_5_sram[2]:6 9.068874e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l3_in_1_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_11\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007481012 //LENGTH 5.020 LUMPCC 0.0001555145 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l1_in_0_:X O *L 0 *C 84.925 53.720 +*I mux_bottom_ipin_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 86.940 56.100 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.940 56.100 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.940 56.055 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.940 53.765 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.895 53.720 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 84.963 53.720 + +*CAP +0 mux_bottom_ipin_15\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.369768e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000168317 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000168317 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001101275 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001101275 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[1]:19 7.667475e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[1]:21 1.082487e-06 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[1]:20 7.667475e-05 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[1]:22 1.082487e-06 + +*RES +0 mux_bottom_ipin_15\/mux_l1_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_15\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725447 + +*END + +*D_NET ropt_net_140 0.0007099307 //LENGTH 5.055 LUMPCC 0 DR + +*CONN +*I FTB_6__5:X O *L 0 *C 94.300 49.640 +*I ropt_mt_inst_740:A I *L 0.001766 *C 97.825 50.320 +*N ropt_net_140:2 *C 97.797 50.297 +*N ropt_net_140:3 *C 97.520 50.285 +*N ropt_net_140:4 *C 97.520 49.980 +*N ropt_net_140:5 *C 95.220 49.980 +*N ropt_net_140:6 *C 95.220 49.640 +*N ropt_net_140:7 *C 94.338 49.640 + +*CAP +0 FTB_6__5:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_140:2 3.808835e-05 +3 ropt_net_140:3 6.355056e-05 +4 ropt_net_140:4 0.0002104447 +5 ropt_net_140:5 0.0002101902 +6 ropt_net_140:6 0.0001054324 +7 ropt_net_140:7 8.022458e-05 + +*RES +0 FTB_6__5:X ropt_net_140:7 0.152 +1 ropt_net_140:2 ropt_mt_inst_740:A 0.152 +2 ropt_net_140:7 ropt_net_140:6 0.0007879465 +3 ropt_net_140:6 ropt_net_140:5 0.0003035715 +4 ropt_net_140:5 ropt_net_140:4 0.002053572 +5 ropt_net_140:4 ropt_net_140:3 0.0002723215 +6 ropt_net_140:3 ropt_net_140:2 0.0001875 + +*END + +*D_NET ropt_net_124 0.001385668 //LENGTH 10.710 LUMPCC 0.0003992346 DR + +*CONN +*I FTB_22__21:X O *L 0 *C 7.820 6.460 +*I ropt_mt_inst_723:A I *L 0.001766 *C 7.820 4.080 +*N ropt_net_124:2 *C 7.820 4.080 +*N ropt_net_124:3 *C 7.820 3.740 +*N ropt_net_124:4 *C 10.535 3.740 +*N ropt_net_124:5 *C 10.580 3.785 +*N ropt_net_124:6 *C 10.580 6.075 +*N ropt_net_124:7 *C 10.535 6.120 +*N ropt_net_124:8 *C 7.820 6.120 +*N ropt_net_124:9 *C 7.820 6.460 + +*CAP +0 FTB_22__21:X 1e-06 +1 ropt_mt_inst_723:A 1e-06 +2 ropt_net_124:2 5.600209e-05 +3 ropt_net_124:3 0.0001014742 +4 ropt_net_124:4 7.406042e-05 +5 ropt_net_124:5 0.0001359763 +6 ropt_net_124:6 0.0001359763 +7 ropt_net_124:7 0.0001938145 +8 ropt_net_124:8 0.0002242763 +9 ropt_net_124:9 6.285282e-05 +10 ropt_net_124:4 chanx_right_in[16]:15 4.673017e-05 +11 ropt_net_124:3 chanx_right_in[16]:14 4.673017e-05 +12 ropt_net_124:7 ropt_net_162:6 4.340353e-07 +13 ropt_net_124:4 ropt_net_162:6 0.0001524531 +14 ropt_net_124:3 ropt_net_162:5 0.0001524531 +15 ropt_net_124:8 ropt_net_162:5 4.340353e-07 + +*RES +0 FTB_22__21:X ropt_net_124:9 0.152 +1 ropt_net_124:9 ropt_net_124:8 0.0003035715 +2 ropt_net_124:7 ropt_net_124:6 0.0045 +3 ropt_net_124:6 ropt_net_124:5 0.002044643 +4 ropt_net_124:4 ropt_net_124:3 0.002424107 +5 ropt_net_124:5 ropt_net_124:4 0.0045 +6 ropt_net_124:2 ropt_mt_inst_723:A 0.152 +7 ropt_net_124:3 ropt_net_124:2 0.0003035715 +8 ropt_net_124:8 ropt_net_124:7 0.002424107 + +*END + +*D_NET ropt_net_137 0.001042236 //LENGTH 8.360 LUMPCC 0.0001447594 DR + +*CONN +*I FTB_38__37:X O *L 0 *C 5.980 61.880 +*I ropt_mt_inst_736:A I *L 0.001766 *C 3.220 63.920 +*N ropt_net_137:2 *C 3.183 63.920 +*N ropt_net_137:3 *C 2.345 63.920 +*N ropt_net_137:4 *C 2.300 63.875 +*N ropt_net_137:5 *C 2.300 61.585 +*N ropt_net_137:6 *C 2.345 61.540 +*N ropt_net_137:7 *C 5.980 61.540 +*N ropt_net_137:8 *C 5.980 61.880 + +*CAP +0 FTB_38__37:X 1e-06 +1 ropt_mt_inst_736:A 1e-06 +2 ropt_net_137:2 6.55687e-05 +3 ropt_net_137:3 6.55687e-05 +4 ropt_net_137:4 9.437978e-05 +5 ropt_net_137:5 9.437978e-05 +6 ropt_net_137:6 0.0002443027 +7 ropt_net_137:7 0.0002729446 +8 ropt_net_137:8 5.833228e-05 +9 ropt_net_137:5 chanx_left_in[12]:28 7.23797e-05 +10 ropt_net_137:4 chanx_left_in[12]:29 7.23797e-05 + +*RES +0 FTB_38__37:X ropt_net_137:8 0.152 +1 ropt_net_137:8 ropt_net_137:7 0.0003035715 +2 ropt_net_137:6 ropt_net_137:5 0.0045 +3 ropt_net_137:5 ropt_net_137:4 0.002044643 +4 ropt_net_137:3 ropt_net_137:2 0.0007477679 +5 ropt_net_137:4 ropt_net_137:3 0.0045 +6 ropt_net_137:2 ropt_mt_inst_736:A 0.152 +7 ropt_net_137:7 ropt_net_137:6 0.003245536 + +*END + +*D_NET ropt_net_136 0.001560295 //LENGTH 12.345 LUMPCC 0.0004266194 DR + +*CONN +*I BUFT_RR_68:X O *L 0 *C 5.980 21.080 +*I ropt_mt_inst_735:A I *L 0.001766 *C 3.220 28.560 +*N ropt_net_136:2 *C 3.220 28.560 +*N ropt_net_136:3 *C 3.250 28.530 +*N ropt_net_136:4 *C 3.265 28.220 +*N ropt_net_136:5 *C 3.680 28.220 +*N ropt_net_136:6 *C 3.680 26.180 +*N ropt_net_136:7 *C 3.220 26.180 +*N ropt_net_136:8 *C 3.220 21.125 +*N ropt_net_136:9 *C 3.265 21.080 +*N ropt_net_136:10 *C 5.942 21.080 + +*CAP +0 BUFT_RR_68:X 1e-06 +1 ropt_mt_inst_735:A 1e-06 +2 ropt_net_136:2 3.616937e-05 +3 ropt_net_136:3 3.061838e-05 +4 ropt_net_136:4 6.203192e-05 +5 ropt_net_136:5 0.0001252757 +6 ropt_net_136:6 0.0001195722 +7 ropt_net_136:7 0.0002677054 +8 ropt_net_136:8 0.0002419954 +9 ropt_net_136:9 0.0001241538 +10 ropt_net_136:10 0.0001241538 +11 ropt_net_136:9 ropt_net_156:4 9.685788e-05 +12 ropt_net_136:8 ropt_net_156:5 5.019076e-05 +13 ropt_net_136:10 ropt_net_156:3 9.685788e-05 +14 ropt_net_136:7 ropt_net_156:6 5.019076e-05 +15 ropt_net_136:3 ropt_net_134:7 4.991223e-06 +16 ropt_net_136:8 ropt_net_134:8 4.212555e-06 +17 ropt_net_136:7 ropt_net_134:7 4.212555e-06 +18 ropt_net_136:6 ropt_net_134:8 5.70573e-05 +19 ropt_net_136:4 ropt_net_134:8 4.991223e-06 +20 ropt_net_136:5 ropt_net_134:7 5.70573e-05 + +*RES +0 BUFT_RR_68:X ropt_net_136:10 0.152 +1 ropt_net_136:2 ropt_mt_inst_735:A 0.152 +2 ropt_net_136:3 ropt_net_136:2 0.0045 +3 ropt_net_136:9 ropt_net_136:8 0.0045 +4 ropt_net_136:8 ropt_net_136:7 0.004513393 +5 ropt_net_136:10 ropt_net_136:9 0.002390625 +6 ropt_net_136:7 ropt_net_136:6 0.0004107143 +7 ropt_net_136:6 ropt_net_136:5 0.001821429 +8 ropt_net_136:4 ropt_net_136:3 0.00019375 +9 ropt_net_136:5 ropt_net_136:4 0.0003705357 + +*END + +*D_NET chanx_right_out[5] 0.0003236132 //LENGTH 2.265 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 101.855 50.320 +*P chanx_right_out[5] O *L 0.7423 *C 103.650 50.320 +*N chanx_right_out[5]:2 *C 102.588 50.320 +*N chanx_right_out[5]:3 *C 102.580 50.320 +*N chanx_right_out[5]:4 *C 102.535 50.320 +*N chanx_right_out[5]:5 *C 101.892 50.320 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 chanx_right_out[5] 9.15038e-05 +2 chanx_right_out[5]:2 9.15038e-05 +3 chanx_right_out[5]:3 3.131605e-05 +4 chanx_right_out[5]:4 5.414475e-05 +5 chanx_right_out[5]:5 5.414475e-05 + +*RES +0 ropt_mt_inst_740:X chanx_right_out[5]:5 0.152 +1 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0005736608 +2 chanx_right_out[5]:4 chanx_right_out[5]:3 0.0045 +3 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +4 chanx_right_out[5]:2 chanx_right_out[5] 0.0001664583 + +*END + +*D_NET top_grid_pin_16_[0] 0.0004895078 //LENGTH 4.025 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 35.420 72.760 +*P top_grid_pin_16_[0] O *L 0.7423 *C 34.040 74.835 +*N top_grid_pin_16_[0]:2 *C 34.040 74.800 +*N top_grid_pin_16_[0]:3 *C 34.040 72.805 +*N top_grid_pin_16_[0]:4 *C 34.085 72.760 +*N top_grid_pin_16_[0]:5 *C 35.383 72.760 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 top_grid_pin_16_[0] 9.57526e-06 +2 top_grid_pin_16_[0]:2 0.0001318712 +3 top_grid_pin_16_[0]:3 0.0001222959 +4 top_grid_pin_16_[0]:4 0.0001123828 +5 top_grid_pin_16_[0]:5 0.0001123828 + +*RES +0 ropt_mt_inst_764:X top_grid_pin_16_[0]:5 0.152 +1 top_grid_pin_16_[0]:5 top_grid_pin_16_[0]:4 0.001158482 +2 top_grid_pin_16_[0]:4 top_grid_pin_16_[0]:3 0.0045 +3 top_grid_pin_16_[0]:3 top_grid_pin_16_[0]:2 0.00178125 +4 top_grid_pin_16_[0]:2 top_grid_pin_16_[0] 6.696428e-05 + +*END + +*D_NET chanx_right_out[13] 0.000327776 //LENGTH 2.265 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 101.855 44.880 +*P chanx_right_out[13] O *L 0.7423 *C 103.650 44.880 +*N chanx_right_out[13]:2 *C 102.588 44.880 +*N chanx_right_out[13]:3 *C 102.580 44.880 +*N chanx_right_out[13]:4 *C 102.535 44.880 +*N chanx_right_out[13]:5 *C 101.892 44.880 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 chanx_right_out[13] 9.108747e-05 +2 chanx_right_out[13]:2 9.108747e-05 +3 chanx_right_out[13]:3 3.550585e-05 +4 chanx_right_out[13]:4 5.454758e-05 +5 chanx_right_out[13]:5 5.454758e-05 + +*RES +0 ropt_mt_inst_743:X chanx_right_out[13]:5 0.152 +1 chanx_right_out[13]:5 chanx_right_out[13]:4 0.0005736608 +2 chanx_right_out[13]:4 chanx_right_out[13]:3 0.0045 +3 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +4 chanx_right_out[13]:2 chanx_right_out[13] 0.0001664583 + +*END + +*D_NET chanx_left_out[0] 0.002765429 //LENGTH 18.160 LUMPCC 0.0001848063 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 14.915 44.540 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 46.240 +*N chanx_left_out[0]:2 *C 9.200 46.240 +*N chanx_left_out[0]:3 *C 9.200 46.920 +*N chanx_left_out[0]:4 *C 12.873 46.920 +*N chanx_left_out[0]:5 *C 12.880 46.863 +*N chanx_left_out[0]:6 *C 12.880 44.585 +*N chanx_left_out[0]:7 *C 12.925 44.540 +*N chanx_left_out[0]:8 *C 14.878 44.540 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 chanx_left_out[0] 0.0006303259 +2 chanx_left_out[0]:2 0.0006945097 +3 chanx_left_out[0]:3 0.0004073568 +4 chanx_left_out[0]:4 0.000343173 +5 chanx_left_out[0]:5 0.0001182485 +6 chanx_left_out[0]:6 0.0001182485 +7 chanx_left_out[0]:7 0.0001338799 +8 chanx_left_out[0]:8 0.0001338799 +9 chanx_left_out[0]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 4.748402e-05 +10 chanx_left_out[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 4.748402e-05 +11 chanx_left_out[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 4.491913e-05 +12 chanx_left_out[0]:3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 4.491913e-05 + +*RES +0 ropt_mt_inst_779:X chanx_left_out[0]:8 0.152 +1 chanx_left_out[0]:8 chanx_left_out[0]:7 0.001743304 +2 chanx_left_out[0]:7 chanx_left_out[0]:6 0.0045 +3 chanx_left_out[0]:6 chanx_left_out[0]:5 0.002033482 +4 chanx_left_out[0]:5 chanx_left_out[0]:4 0.00341 +5 chanx_left_out[0]:4 chanx_left_out[0]:3 0.0005753583 +6 chanx_left_out[0]:2 chanx_left_out[0] 0.001248633 +7 chanx_left_out[0]:3 chanx_left_out[0]:2 0.0001065333 + +*END + +*D_NET chanx_left_in[7] 0.01895136 //LENGTH 116.615 LUMPCC 0.007802762 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 51.680 +*I mux_bottom_ipin_11\/mux_l2_in_1_:A0 I *L 0.001631 *C 29.730 53.720 +*I mux_bottom_ipin_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 46.290 53.720 +*I mux_bottom_ipin_13\/mux_l1_in_2_:A1 I *L 0.00198 *C 76.820 50.660 +*I BUFT_P_85:A I *L 0.001767 *C 88.780 63.920 +*N chanx_left_in[7]:5 *C 88.743 63.920 +*N chanx_left_in[7]:6 *C 87.905 63.920 +*N chanx_left_in[7]:7 *C 87.860 63.965 +*N chanx_left_in[7]:8 *C 87.860 66.583 +*N chanx_left_in[7]:9 *C 87.853 66.640 +*N chanx_left_in[7]:10 *C 80.040 66.640 +*N chanx_left_in[7]:11 *C 80.040 65.960 +*N chanx_left_in[7]:12 *C 78.208 65.960 +*N chanx_left_in[7]:13 *C 78.200 65.903 +*N chanx_left_in[7]:14 *C 78.200 52.418 +*N chanx_left_in[7]:15 *C 78.193 52.360 +*N chanx_left_in[7]:16 *C 76.820 50.660 +*N chanx_left_in[7]:17 *C 76.820 50.660 +*N chanx_left_in[7]:18 *C 76.360 50.660 +*N chanx_left_in[7]:19 *C 76.360 52.303 +*N chanx_left_in[7]:20 *C 76.360 52.360 +*N chanx_left_in[7]:21 *C 48.308 52.360 +*N chanx_left_in[7]:22 *C 48.300 52.418 +*N chanx_left_in[7]:23 *C 48.300 53.675 +*N chanx_left_in[7]:24 *C 48.255 53.720 +*N chanx_left_in[7]:25 *C 46.290 53.720 +*N chanx_left_in[7]:26 *C 39.145 53.720 +*N chanx_left_in[7]:27 *C 39.100 53.675 +*N chanx_left_in[7]:28 *C 39.100 52.418 +*N chanx_left_in[7]:29 *C 39.093 52.360 +*N chanx_left_in[7]:30 *C 29.730 53.720 +*N chanx_left_in[7]:31 *C 29.900 53.720 +*N chanx_left_in[7]:32 *C 29.900 53.675 +*N chanx_left_in[7]:33 *C 29.900 52.418 +*N chanx_left_in[7]:34 *C 29.900 52.360 +*N chanx_left_in[7]:35 *C 13.800 52.360 +*N chanx_left_in[7]:36 *C 13.800 51.680 + +*CAP +0 chanx_left_in[7] 0.0006558962 +1 mux_bottom_ipin_11\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_ipin_13\/mux_l1_in_2_:A1 1e-06 +4 BUFT_P_85:A 1e-06 +5 chanx_left_in[7]:5 5.088114e-05 +6 chanx_left_in[7]:6 5.088114e-05 +7 chanx_left_in[7]:7 0.000202847 +8 chanx_left_in[7]:8 0.000202847 +9 chanx_left_in[7]:9 0.0003492212 +10 chanx_left_in[7]:10 0.0004086241 +11 chanx_left_in[7]:11 0.0002093334 +12 chanx_left_in[7]:12 0.0001499305 +13 chanx_left_in[7]:13 0.0004730027 +14 chanx_left_in[7]:14 0.0004730027 +15 chanx_left_in[7]:15 8.349162e-05 +16 chanx_left_in[7]:16 3.669256e-05 +17 chanx_left_in[7]:17 6.000474e-05 +18 chanx_left_in[7]:18 0.0001366968 +19 chanx_left_in[7]:19 0.0001095437 +20 chanx_left_in[7]:20 0.001213101 +21 chanx_left_in[7]:21 0.001129609 +22 chanx_left_in[7]:22 9.372793e-05 +23 chanx_left_in[7]:23 9.372793e-05 +24 chanx_left_in[7]:24 0.0001564458 +25 chanx_left_in[7]:25 0.0006388025 +26 chanx_left_in[7]:26 0.0004521637 +27 chanx_left_in[7]:27 9.39515e-05 +28 chanx_left_in[7]:28 9.39515e-05 +29 chanx_left_in[7]:29 0.0004582882 +30 chanx_left_in[7]:30 5.019089e-05 +31 chanx_left_in[7]:31 5.498169e-05 +32 chanx_left_in[7]:32 9.98523e-05 +33 chanx_left_in[7]:33 9.98523e-05 +34 chanx_left_in[7]:34 0.001217576 +35 chanx_left_in[7]:35 0.0008244346 +36 chanx_left_in[7]:36 0.0007210435 +37 chanx_left_in[7]:14 chanx_left_in[0]:19 0.0003507744 +38 chanx_left_in[7]:13 chanx_left_in[0]:18 0.0003507744 +39 chanx_left_in[7]:26 chanx_left_in[1]:42 1.024883e-05 +40 chanx_left_in[7]:29 chanx_left_in[1]:50 0.0002077386 +41 chanx_left_in[7]:25 chanx_left_in[1]:41 1.024883e-05 +42 chanx_left_in[7]:34 chanx_left_in[1]:50 0.000497941 +43 chanx_left_in[7]:34 chanx_left_in[1]:51 0.0002077386 +44 chanx_left_in[7]:35 chanx_left_in[1]:51 0.000497941 +45 chanx_left_in[7]:14 chanx_left_in[3]:32 1.401757e-05 +46 chanx_left_in[7]:13 chanx_left_in[3]:31 1.401757e-05 +47 chanx_left_in[7]:21 chanx_left_in[3]:34 7.061751e-06 +48 chanx_left_in[7]:21 chanx_left_in[3]:42 0.0002160493 +49 chanx_left_in[7]:21 chanx_left_in[3]:43 0.0002407628 +50 chanx_left_in[7]:19 chanx_left_in[3]:31 3.134484e-06 +51 chanx_left_in[7]:20 chanx_left_in[3]:33 7.061751e-06 +52 chanx_left_in[7]:20 chanx_left_in[3]:37 0.0002160493 +53 chanx_left_in[7]:20 chanx_left_in[3]:42 0.0002407628 +54 chanx_left_in[7]:17 chanx_left_in[3]:33 7.414303e-06 +55 chanx_left_in[7]:34 chanx_left_in[3]:61 6.216478e-06 +56 chanx_left_in[7]:18 chanx_left_in[3]:32 3.134484e-06 +57 chanx_left_in[7]:18 chanx_left_in[3]:34 7.414303e-06 +58 chanx_left_in[7]:35 chanx_left_in[3]:62 6.216478e-06 +59 chanx_left_in[7]:27 chanx_right_in[1]:36 2.125654e-07 +60 chanx_left_in[7]:28 chanx_right_in[1]:32 2.125654e-07 +61 chanx_left_in[7]:29 chanx_right_in[1]:38 8.06013e-05 +62 chanx_left_in[7]:21 chanx_right_in[1]:37 0.0003415734 +63 chanx_left_in[7]:20 chanx_right_in[1]:38 0.0003415734 +64 chanx_left_in[7]:34 chanx_right_in[1]:37 8.06013e-05 +65 chanx_left_in[7]:15 chanx_right_in[3]:57 0.0001090859 +66 chanx_left_in[7]:26 chanx_right_in[3]:44 7.101691e-07 +67 chanx_left_in[7]:22 chanx_right_in[3]:42 1.702129e-06 +68 chanx_left_in[7]:21 chanx_right_in[3]:56 0.0004047139 +69 chanx_left_in[7]:21 chanx_right_in[3]:44 5.547364e-06 +70 chanx_left_in[7]:24 chanx_right_in[3]:49 4.280742e-06 +71 chanx_left_in[7]:23 chanx_right_in[3]:41 1.702129e-06 +72 chanx_left_in[7]:20 chanx_right_in[3]:56 0.0001090859 +73 chanx_left_in[7]:20 chanx_right_in[3]:57 0.0004047139 +74 chanx_left_in[7]:20 chanx_right_in[3]:49 5.547364e-06 +75 chanx_left_in[7]:25 chanx_right_in[3]:49 7.101691e-07 +76 chanx_left_in[7]:25 chanx_right_in[3]:44 4.280742e-06 +77 chanx_left_in[7]:33 chanx_right_in[3]:34 6.33052e-06 +78 chanx_left_in[7]:33 chanx_right_in[3]:31 3.010564e-06 +79 chanx_left_in[7]:34 chanx_right_in[3]:31 9.904388e-06 +80 chanx_left_in[7]:31 chanx_right_in[3]:33 7.813354e-07 +81 chanx_left_in[7]:32 chanx_right_in[3]:35 6.33052e-06 +82 chanx_left_in[7]:32 chanx_right_in[3]:34 3.010564e-06 +83 chanx_left_in[7]:30 chanx_right_in[3]:32 7.813354e-07 +84 chanx_left_in[7]:35 chanx_right_in[3]:30 9.904388e-06 +85 chanx_left_in[7] chanx_right_in[11]:16 0.0004945073 +86 chanx_left_in[7]:33 chanx_right_in[11]:18 2.029113e-09 +87 chanx_left_in[7]:34 chanx_right_in[11]:17 0.0002297132 +88 chanx_left_in[7]:32 chanx_right_in[11]:19 2.029113e-09 +89 chanx_left_in[7]:36 chanx_right_in[11]:17 0.0004945073 +90 chanx_left_in[7]:35 chanx_right_in[11]:16 0.0002297132 +91 chanx_left_in[7]:12 chanx_right_in[13]:21 4.52155e-05 +92 chanx_left_in[7]:9 chanx_right_in[13] 0.0003228667 +93 chanx_left_in[7]:9 chanx_right_in[13]:22 1.510878e-05 +94 chanx_left_in[7]:11 chanx_right_in[13]:22 4.52155e-05 +95 chanx_left_in[7]:10 chanx_right_in[13]:21 1.510878e-05 +96 chanx_left_in[7]:10 chanx_right_in[13]:25 0.0003228667 +97 chanx_left_in[7]:14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001257686 +98 chanx_left_in[7]:13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001257686 +99 chanx_left_in[7]:26 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.41471e-05 +100 chanx_left_in[7]:25 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.41471e-05 +101 chanx_left_in[7]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.423842e-05 +102 chanx_left_in[7]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.423842e-05 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:36 0.0019693 +1 chanx_left_in[7]:14 chanx_left_in[7]:13 0.01204018 +2 chanx_left_in[7]:15 chanx_left_in[7]:14 0.00341 +3 chanx_left_in[7]:13 chanx_left_in[7]:12 0.00341 +4 chanx_left_in[7]:12 chanx_left_in[7]:11 0.0002870917 +5 chanx_left_in[7]:8 chanx_left_in[7]:7 0.002337054 +6 chanx_left_in[7]:9 chanx_left_in[7]:8 0.00341 +7 chanx_left_in[7]:6 chanx_left_in[7]:5 0.0007477679 +8 chanx_left_in[7]:7 chanx_left_in[7]:6 0.0045 +9 chanx_left_in[7]:5 BUFT_P_85:A 0.152 +10 chanx_left_in[7]:26 chanx_left_in[7]:25 0.006379465 +11 chanx_left_in[7]:27 chanx_left_in[7]:26 0.0045 +12 chanx_left_in[7]:28 chanx_left_in[7]:27 0.001122768 +13 chanx_left_in[7]:29 chanx_left_in[7]:28 0.00341 +14 chanx_left_in[7]:22 chanx_left_in[7]:21 0.00341 +15 chanx_left_in[7]:21 chanx_left_in[7]:20 0.004394892 +16 chanx_left_in[7]:24 chanx_left_in[7]:23 0.0045 +17 chanx_left_in[7]:23 chanx_left_in[7]:22 0.001122768 +18 chanx_left_in[7]:19 chanx_left_in[7]:18 0.001466518 +19 chanx_left_in[7]:20 chanx_left_in[7]:19 0.00341 +20 chanx_left_in[7]:20 chanx_left_in[7]:15 0.0002870917 +21 chanx_left_in[7]:16 mux_bottom_ipin_13\/mux_l1_in_2_:A1 0.152 +22 chanx_left_in[7]:17 chanx_left_in[7]:16 0.0045 +23 chanx_left_in[7]:25 mux_bottom_ipin_3\/mux_l2_in_1_:A0 0.152 +24 chanx_left_in[7]:25 chanx_left_in[7]:24 0.001754464 +25 chanx_left_in[7]:33 chanx_left_in[7]:32 0.001122768 +26 chanx_left_in[7]:34 chanx_left_in[7]:33 0.00341 +27 chanx_left_in[7]:34 chanx_left_in[7]:29 0.001440158 +28 chanx_left_in[7]:31 chanx_left_in[7]:30 9.239131e-05 +29 chanx_left_in[7]:32 chanx_left_in[7]:31 0.0045 +30 chanx_left_in[7]:30 mux_bottom_ipin_11\/mux_l2_in_1_:A0 0.152 +31 chanx_left_in[7]:18 chanx_left_in[7]:17 0.0004107143 +32 chanx_left_in[7]:36 chanx_left_in[7]:35 0.0001065333 +33 chanx_left_in[7]:35 chanx_left_in[7]:34 0.002522333 +34 chanx_left_in[7]:11 chanx_left_in[7]:10 0.0001065333 +35 chanx_left_in[7]:10 chanx_left_in[7]:9 0.001223958 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[3] 0.00260331 //LENGTH 18.400 LUMPCC 0.0007085671 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 17.785 39.100 +*I mux_bottom_ipin_8\/mux_l4_in_0_:S I *L 0.00357 *C 12.520 36.720 +*I mem_bottom_ipin_8\/FTB_5__44:A I *L 0.001746 *C 7.820 42.160 +*N mux_tree_tapbuf_size10_4_sram[3]:3 *C 7.858 42.160 +*N mux_tree_tapbuf_size10_4_sram[3]:4 *C 8.235 42.160 +*N mux_tree_tapbuf_size10_4_sram[3]:5 *C 8.280 42.115 +*N mux_tree_tapbuf_size10_4_sram[3]:6 *C 8.280 38.138 +*N mux_tree_tapbuf_size10_4_sram[3]:7 *C 8.287 38.080 +*N mux_tree_tapbuf_size10_4_sram[3]:8 *C 12.420 36.720 +*N mux_tree_tapbuf_size10_4_sram[3]:9 *C 12.420 36.765 +*N mux_tree_tapbuf_size10_4_sram[3]:10 *C 12.420 38.023 +*N mux_tree_tapbuf_size10_4_sram[3]:11 *C 12.420 38.080 +*N mux_tree_tapbuf_size10_4_sram[3]:12 *C 17.012 38.080 +*N mux_tree_tapbuf_size10_4_sram[3]:13 *C 17.020 38.138 +*N mux_tree_tapbuf_size10_4_sram[3]:14 *C 17.020 39.055 +*N mux_tree_tapbuf_size10_4_sram[3]:15 *C 17.065 39.100 +*N mux_tree_tapbuf_size10_4_sram[3]:16 *C 17.748 39.100 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_8\/FTB_5__44:A 1e-06 +3 mux_tree_tapbuf_size10_4_sram[3]:3 4.784519e-05 +4 mux_tree_tapbuf_size10_4_sram[3]:4 4.784519e-05 +5 mux_tree_tapbuf_size10_4_sram[3]:5 0.0002436059 +6 mux_tree_tapbuf_size10_4_sram[3]:6 0.0002436059 +7 mux_tree_tapbuf_size10_4_sram[3]:7 0.0001792242 +8 mux_tree_tapbuf_size10_4_sram[3]:8 3.232172e-05 +9 mux_tree_tapbuf_size10_4_sram[3]:9 0.0001046908 +10 mux_tree_tapbuf_size10_4_sram[3]:10 0.0001046908 +11 mux_tree_tapbuf_size10_4_sram[3]:11 0.0003720744 +12 mux_tree_tapbuf_size10_4_sram[3]:12 0.0001928502 +13 mux_tree_tapbuf_size10_4_sram[3]:13 9.796159e-05 +14 mux_tree_tapbuf_size10_4_sram[3]:14 9.796159e-05 +15 mux_tree_tapbuf_size10_4_sram[3]:15 6.353283e-05 +16 mux_tree_tapbuf_size10_4_sram[3]:16 6.353283e-05 +17 mux_tree_tapbuf_size10_4_sram[3]:9 chanx_left_in[4]:37 4.546883e-07 +18 mux_tree_tapbuf_size10_4_sram[3]:10 chanx_left_in[4]:36 4.546883e-07 +19 mux_tree_tapbuf_size10_4_sram[3]:11 chanx_left_in[4] 2.104859e-06 +20 mux_tree_tapbuf_size10_4_sram[3]:11 chanx_left_in[4]:35 0.0001406482 +21 mux_tree_tapbuf_size10_4_sram[3]:11 chanx_left_in[4]:38 9.250214e-06 +22 mux_tree_tapbuf_size10_4_sram[3]:7 chanx_left_in[4] 9.250214e-06 +23 mux_tree_tapbuf_size10_4_sram[3]:12 chanx_left_in[4]:34 0.0001406482 +24 mux_tree_tapbuf_size10_4_sram[3]:12 chanx_left_in[4]:38 2.104859e-06 +25 mux_tree_tapbuf_size10_4_sram[3]:11 chanx_left_in[15] 9.9503e-05 +26 mux_tree_tapbuf_size10_4_sram[3]:11 chanx_left_in[15]:28 0.0001023226 +27 mux_tree_tapbuf_size10_4_sram[3]:7 chanx_left_in[15] 0.0001023226 +28 mux_tree_tapbuf_size10_4_sram[3]:12 chanx_left_in[15]:28 9.9503e-05 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_4_sram[3]:16 0.152 +1 mux_tree_tapbuf_size10_4_sram[3]:8 mux_bottom_ipin_8\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_4_sram[3]:9 mux_tree_tapbuf_size10_4_sram[3]:8 0.0045 +3 mux_tree_tapbuf_size10_4_sram[3]:10 mux_tree_tapbuf_size10_4_sram[3]:9 0.001122768 +4 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size10_4_sram[3]:10 0.00341 +5 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size10_4_sram[3]:7 0.000647425 +6 mux_tree_tapbuf_size10_4_sram[3]:6 mux_tree_tapbuf_size10_4_sram[3]:5 0.003551339 +7 mux_tree_tapbuf_size10_4_sram[3]:7 mux_tree_tapbuf_size10_4_sram[3]:6 0.00341 +8 mux_tree_tapbuf_size10_4_sram[3]:4 mux_tree_tapbuf_size10_4_sram[3]:3 0.0003370536 +9 mux_tree_tapbuf_size10_4_sram[3]:5 mux_tree_tapbuf_size10_4_sram[3]:4 0.0045 +10 mux_tree_tapbuf_size10_4_sram[3]:3 mem_bottom_ipin_8\/FTB_5__44:A 0.152 +11 mux_tree_tapbuf_size10_4_sram[3]:13 mux_tree_tapbuf_size10_4_sram[3]:12 0.00341 +12 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size10_4_sram[3]:11 0.0007194916 +13 mux_tree_tapbuf_size10_4_sram[3]:15 mux_tree_tapbuf_size10_4_sram[3]:14 0.0045 +14 mux_tree_tapbuf_size10_4_sram[3]:14 mux_tree_tapbuf_size10_4_sram[3]:13 0.0008191965 +15 mux_tree_tapbuf_size10_4_sram[3]:16 mux_tree_tapbuf_size10_4_sram[3]:15 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[0] 0.003072418 //LENGTH 24.590 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 73.445 49.980 +*I mux_bottom_ipin_13\/mux_l1_in_0_:S I *L 0.00357 *C 79.700 52.360 +*I mux_bottom_ipin_13\/mux_l1_in_1_:S I *L 0.00357 *C 81.060 58.140 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 77.915 60.860 +*I mux_bottom_ipin_13\/mux_l1_in_2_:S I *L 0.00357 *C 76.000 50.615 +*N mux_tree_tapbuf_size10_7_sram[0]:5 *C 76.000 50.615 +*N mux_tree_tapbuf_size10_7_sram[0]:6 *C 77.953 60.860 +*N mux_tree_tapbuf_size10_7_sram[0]:7 *C 80.455 60.860 +*N mux_tree_tapbuf_size10_7_sram[0]:8 *C 80.500 60.815 +*N mux_tree_tapbuf_size10_7_sram[0]:9 *C 80.500 58.575 +*N mux_tree_tapbuf_size10_7_sram[0]:10 *C 81.023 58.140 +*N mux_tree_tapbuf_size10_7_sram[0]:11 *C 80.545 58.140 +*N mux_tree_tapbuf_size10_7_sram[0]:12 *C 80.470 58.185 +*N mux_tree_tapbuf_size10_7_sram[0]:13 *C 80.040 58.140 +*N mux_tree_tapbuf_size10_7_sram[0]:14 *C 79.715 52.360 +*N mux_tree_tapbuf_size10_7_sram[0]:15 *C 80.017 52.360 +*N mux_tree_tapbuf_size10_7_sram[0]:16 *C 80.040 52.405 +*N mux_tree_tapbuf_size10_7_sram[0]:17 *C 79.170 52.360 +*N mux_tree_tapbuf_size10_7_sram[0]:18 *C 79.120 50.365 +*N mux_tree_tapbuf_size10_7_sram[0]:19 *C 79.075 50.320 +*N mux_tree_tapbuf_size10_7_sram[0]:20 *C 76.000 50.320 +*N mux_tree_tapbuf_size10_7_sram[0]:21 *C 74.520 50.320 +*N mux_tree_tapbuf_size10_7_sram[0]:22 *C 74.520 49.980 +*N mux_tree_tapbuf_size10_7_sram[0]:23 *C 73.483 49.980 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_ipin_13\/mux_l1_in_1_:S 1e-06 +3 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_ipin_13\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_7_sram[0]:5 5.858906e-05 +6 mux_tree_tapbuf_size10_7_sram[0]:6 0.0001872227 +7 mux_tree_tapbuf_size10_7_sram[0]:7 0.0001872227 +8 mux_tree_tapbuf_size10_7_sram[0]:8 0.0001313259 +9 mux_tree_tapbuf_size10_7_sram[0]:9 0.0001727467 +10 mux_tree_tapbuf_size10_7_sram[0]:10 6.52021e-05 +11 mux_tree_tapbuf_size10_7_sram[0]:11 6.52021e-05 +12 mux_tree_tapbuf_size10_7_sram[0]:12 7.800566e-05 +13 mux_tree_tapbuf_size10_7_sram[0]:13 0.0003888787 +14 mux_tree_tapbuf_size10_7_sram[0]:14 5.577417e-05 +15 mux_tree_tapbuf_size10_7_sram[0]:15 5.577417e-05 +16 mux_tree_tapbuf_size10_7_sram[0]:16 0.0004109348 +17 mux_tree_tapbuf_size10_7_sram[0]:17 0.0002021379 +18 mux_tree_tapbuf_size10_7_sram[0]:18 0.000143497 +19 mux_tree_tapbuf_size10_7_sram[0]:19 0.0002104509 +20 mux_tree_tapbuf_size10_7_sram[0]:20 0.0003437434 +21 mux_tree_tapbuf_size10_7_sram[0]:21 0.0001289417 +22 mux_tree_tapbuf_size10_7_sram[0]:22 0.0001036677 +23 mux_tree_tapbuf_size10_7_sram[0]:23 7.810067e-05 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_7_sram[0]:23 0.152 +1 mux_tree_tapbuf_size10_7_sram[0]:15 mux_tree_tapbuf_size10_7_sram[0]:14 0.0001644022 +2 mux_tree_tapbuf_size10_7_sram[0]:16 mux_tree_tapbuf_size10_7_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size10_7_sram[0]:16 mux_tree_tapbuf_size10_7_sram[0]:13 0.005120536 +4 mux_tree_tapbuf_size10_7_sram[0]:14 mux_bottom_ipin_13\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:18 0.0045 +6 mux_tree_tapbuf_size10_7_sram[0]:18 mux_tree_tapbuf_size10_7_sram[0]:17 0.00178125 +7 mux_tree_tapbuf_size10_7_sram[0]:23 mux_tree_tapbuf_size10_7_sram[0]:22 0.0009263393 +8 mux_tree_tapbuf_size10_7_sram[0]:7 mux_tree_tapbuf_size10_7_sram[0]:6 0.002234375 +9 mux_tree_tapbuf_size10_7_sram[0]:8 mux_tree_tapbuf_size10_7_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size10_7_sram[0]:6 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size10_7_sram[0]:5 mux_bottom_ipin_13\/mux_l1_in_2_:S 0.152 +12 mux_tree_tapbuf_size10_7_sram[0]:11 mux_tree_tapbuf_size10_7_sram[0]:10 0.0004263393 +13 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:11 0.0045 +14 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:9 0.00024375 +15 mux_tree_tapbuf_size10_7_sram[0]:10 mux_bottom_ipin_13\/mux_l1_in_1_:S 0.152 +16 mux_tree_tapbuf_size10_7_sram[0]:22 mux_tree_tapbuf_size10_7_sram[0]:21 0.0003035715 +17 mux_tree_tapbuf_size10_7_sram[0]:21 mux_tree_tapbuf_size10_7_sram[0]:20 0.001321429 +18 mux_tree_tapbuf_size10_7_sram[0]:20 mux_tree_tapbuf_size10_7_sram[0]:19 0.002745536 +19 mux_tree_tapbuf_size10_7_sram[0]:20 mux_tree_tapbuf_size10_7_sram[0]:5 0.0001271552 +20 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:16 0.0007767858 +21 mux_tree_tapbuf_size10_7_sram[0]:13 mux_tree_tapbuf_size10_7_sram[0]:12 0.0003839286 +22 mux_tree_tapbuf_size10_7_sram[0]:9 mux_tree_tapbuf_size10_7_sram[0]:8 0.002 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[3] 0.001058914 //LENGTH 8.605 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 33.885 25.840 +*I mux_bottom_ipin_2\/mux_l4_in_0_:S I *L 0.00357 *C 32.300 23.460 +*I mem_bottom_ipin_2\/FTB_10__49:A I *L 0.001746 *C 32.660 28.560 +*N mux_tree_tapbuf_size8_0_sram[3]:3 *C 32.698 28.560 +*N mux_tree_tapbuf_size8_0_sram[3]:4 *C 33.075 28.560 +*N mux_tree_tapbuf_size8_0_sram[3]:5 *C 33.120 28.515 +*N mux_tree_tapbuf_size8_0_sram[3]:6 *C 32.200 23.460 +*N mux_tree_tapbuf_size8_0_sram[3]:7 *C 32.200 23.505 +*N mux_tree_tapbuf_size8_0_sram[3]:8 *C 32.200 25.840 +*N mux_tree_tapbuf_size8_0_sram[3]:9 *C 33.120 25.885 +*N mux_tree_tapbuf_size8_0_sram[3]:10 *C 33.165 25.840 +*N mux_tree_tapbuf_size8_0_sram[3]:11 *C 33.848 25.840 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_2\/FTB_10__49:A 1e-06 +3 mux_tree_tapbuf_size8_0_sram[3]:3 5.863612e-05 +4 mux_tree_tapbuf_size8_0_sram[3]:4 5.863612e-05 +5 mux_tree_tapbuf_size8_0_sram[3]:5 0.000168801 +6 mux_tree_tapbuf_size8_0_sram[3]:6 3.221598e-05 +7 mux_tree_tapbuf_size8_0_sram[3]:7 0.0001632423 +8 mux_tree_tapbuf_size8_0_sram[3]:8 0.0002190256 +9 mux_tree_tapbuf_size8_0_sram[3]:9 0.0002245843 +10 mux_tree_tapbuf_size8_0_sram[3]:10 6.538609e-05 +11 mux_tree_tapbuf_size8_0_sram[3]:11 6.538609e-05 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_0_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_0_sram[3]:6 mux_bottom_ipin_2\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[3]:7 mux_tree_tapbuf_size8_0_sram[3]:6 0.0045 +3 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:9 0.0045 +4 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:8 0.0008214285 +5 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:5 0.002348214 +6 mux_tree_tapbuf_size8_0_sram[3]:11 mux_tree_tapbuf_size8_0_sram[3]:10 0.000609375 +7 mux_tree_tapbuf_size8_0_sram[3]:4 mux_tree_tapbuf_size8_0_sram[3]:3 0.0003370536 +8 mux_tree_tapbuf_size8_0_sram[3]:5 mux_tree_tapbuf_size8_0_sram[3]:4 0.0045 +9 mux_tree_tapbuf_size8_0_sram[3]:3 mem_bottom_ipin_2\/FTB_10__49:A 0.152 +10 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:7 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[2] 0.002924591 //LENGTH 23.700 LUMPCC 0.0003749334 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 44.005 60.860 +*I mux_bottom_ipin_3\/mux_l3_in_0_:S I *L 0.00357 *C 43.140 52.750 +*I mux_bottom_ipin_3\/mux_l3_in_1_:S I *L 0.00357 *C 44.060 45.560 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 43.415 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:4 *C 43.378 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:5 *C 42.825 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:6 *C 42.780 42.545 +*N mux_tree_tapbuf_size8_1_sram[2]:7 *C 44.023 45.560 +*N mux_tree_tapbuf_size8_1_sram[2]:8 *C 42.825 45.560 +*N mux_tree_tapbuf_size8_1_sram[2]:9 *C 42.780 45.560 +*N mux_tree_tapbuf_size8_1_sram[2]:10 *C 42.780 53.040 +*N mux_tree_tapbuf_size8_1_sram[2]:11 *C 43.140 52.750 +*N mux_tree_tapbuf_size8_1_sram[2]:12 *C 43.240 53.040 +*N mux_tree_tapbuf_size8_1_sram[2]:13 *C 43.240 53.085 +*N mux_tree_tapbuf_size8_1_sram[2]:14 *C 43.240 60.815 +*N mux_tree_tapbuf_size8_1_sram[2]:15 *C 43.285 60.860 +*N mux_tree_tapbuf_size8_1_sram[2]:16 *C 43.968 60.860 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_3\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_1_sram[2]:4 5.880302e-05 +5 mux_tree_tapbuf_size8_1_sram[2]:5 5.880302e-05 +6 mux_tree_tapbuf_size8_1_sram[2]:6 0.0001766376 +7 mux_tree_tapbuf_size8_1_sram[2]:7 8.20409e-05 +8 mux_tree_tapbuf_size8_1_sram[2]:8 8.20409e-05 +9 mux_tree_tapbuf_size8_1_sram[2]:9 0.0005702625 +10 mux_tree_tapbuf_size8_1_sram[2]:10 0.0003915676 +11 mux_tree_tapbuf_size8_1_sram[2]:11 6.287831e-05 +12 mux_tree_tapbuf_size8_1_sram[2]:12 6.756985e-05 +13 mux_tree_tapbuf_size8_1_sram[2]:13 0.0004530877 +14 mux_tree_tapbuf_size8_1_sram[2]:14 0.0004194489 +15 mux_tree_tapbuf_size8_1_sram[2]:15 6.12587e-05 +16 mux_tree_tapbuf_size8_1_sram[2]:16 6.12587e-05 +17 mux_tree_tapbuf_size8_1_sram[2]:14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.281978e-05 +18 mux_tree_tapbuf_size8_1_sram[2]:13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.281978e-05 +19 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.487255e-05 +20 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.487255e-05 +21 mux_tree_tapbuf_size8_1_sram[2]:8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.174563e-05 +22 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.101084e-05 +23 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.77519e-06 +24 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 8.641821e-07 +25 mux_tree_tapbuf_size8_1_sram[2]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.174563e-05 +26 mux_tree_tapbuf_size8_1_sram[2]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.77519e-06 +27 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.101084e-05 +28 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 8.641821e-07 +29 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.83148e-05 +30 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 2.077121e-07 +31 mux_tree_tapbuf_size8_1_sram[2]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 2.856042e-06 +32 mux_tree_tapbuf_size8_1_sram[2]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 2.077121e-07 +33 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.83148e-05 +34 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 2.856042e-06 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_1_sram[2]:16 0.152 +1 mux_tree_tapbuf_size8_1_sram[2]:15 mux_tree_tapbuf_size8_1_sram[2]:14 0.0045 +2 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:13 0.006901786 +3 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:15 0.000609375 +4 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:11 0.000125 +5 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:12 0.0045 +6 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:10 0.0004107143 +7 mux_tree_tapbuf_size8_1_sram[2]:11 mux_bottom_ipin_3\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_1_sram[2]:8 mux_tree_tapbuf_size8_1_sram[2]:7 0.001069196 +9 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:8 0.0045 +10 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:6 0.002691964 +11 mux_tree_tapbuf_size8_1_sram[2]:7 mux_bottom_ipin_3\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size8_1_sram[2]:5 mux_tree_tapbuf_size8_1_sram[2]:4 0.0004933036 +13 mux_tree_tapbuf_size8_1_sram[2]:6 mux_tree_tapbuf_size8_1_sram[2]:5 0.0045 +14 mux_tree_tapbuf_size8_1_sram[2]:4 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +15 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:9 0.006678571 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[1] 0.005235539 //LENGTH 41.798 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 26.525 44.880 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 20.875 39.100 +*I mux_bottom_ipin_11\/mux_l2_in_3_:S I *L 0.00357 *C 32.560 44.880 +*I mux_bottom_ipin_11\/mux_l2_in_1_:S I *L 0.00357 *C 28.620 52.750 +*I mux_bottom_ipin_11\/mux_l2_in_0_:S I *L 0.00357 *C 26.120 52.360 +*I mux_bottom_ipin_11\/mux_l2_in_2_:S I *L 0.00357 *C 35.980 47.600 +*N mux_tree_tapbuf_size8_5_sram[1]:6 *C 35.880 47.600 +*N mux_tree_tapbuf_size8_5_sram[1]:7 *C 35.880 47.555 +*N mux_tree_tapbuf_size8_5_sram[1]:8 *C 35.880 44.925 +*N mux_tree_tapbuf_size8_5_sram[1]:9 *C 35.835 44.880 +*N mux_tree_tapbuf_size8_5_sram[1]:10 *C 28.590 52.820 +*N mux_tree_tapbuf_size8_5_sram[1]:11 *C 28.550 52.645 +*N mux_tree_tapbuf_size8_5_sram[1]:12 *C 26.158 52.360 +*N mux_tree_tapbuf_size8_5_sram[1]:13 *C 28.520 52.360 +*N mux_tree_tapbuf_size8_5_sram[1]:14 *C 28.620 52.750 +*N mux_tree_tapbuf_size8_5_sram[1]:15 *C 28.678 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:16 *C 32.615 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:17 *C 32.660 52.995 +*N mux_tree_tapbuf_size8_5_sram[1]:18 *C 32.660 44.925 +*N mux_tree_tapbuf_size8_5_sram[1]:19 *C 32.560 44.880 +*N mux_tree_tapbuf_size8_5_sram[1]:20 *C 20.875 39.100 +*N mux_tree_tapbuf_size8_5_sram[1]:21 *C 21.160 39.100 +*N mux_tree_tapbuf_size8_5_sram[1]:22 *C 21.160 39.145 +*N mux_tree_tapbuf_size8_5_sram[1]:23 *C 21.160 41.435 +*N mux_tree_tapbuf_size8_5_sram[1]:24 *C 21.205 41.480 +*N mux_tree_tapbuf_size8_5_sram[1]:25 *C 25.715 41.480 +*N mux_tree_tapbuf_size8_5_sram[1]:26 *C 25.760 41.525 +*N mux_tree_tapbuf_size8_5_sram[1]:27 *C 25.760 44.835 +*N mux_tree_tapbuf_size8_5_sram[1]:28 *C 25.805 44.880 +*N mux_tree_tapbuf_size8_5_sram[1]:29 *C 26.525 44.880 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_11\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_11\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_11\/mux_l2_in_0_:S 1e-06 +5 mux_bottom_ipin_11\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size8_5_sram[1]:6 3.822119e-05 +7 mux_tree_tapbuf_size8_5_sram[1]:7 0.0001788602 +8 mux_tree_tapbuf_size8_5_sram[1]:8 0.0001788602 +9 mux_tree_tapbuf_size8_5_sram[1]:9 0.0002221314 +10 mux_tree_tapbuf_size8_5_sram[1]:10 7.981588e-06 +11 mux_tree_tapbuf_size8_5_sram[1]:11 6.55435e-06 +12 mux_tree_tapbuf_size8_5_sram[1]:12 0.000198113 +13 mux_tree_tapbuf_size8_5_sram[1]:13 0.0002217439 +14 mux_tree_tapbuf_size8_5_sram[1]:14 8.486172e-05 +15 mux_tree_tapbuf_size8_5_sram[1]:15 0.0003320191 +16 mux_tree_tapbuf_size8_5_sram[1]:16 0.0003112887 +17 mux_tree_tapbuf_size8_5_sram[1]:17 0.0004889808 +18 mux_tree_tapbuf_size8_5_sram[1]:18 0.0004889808 +19 mux_tree_tapbuf_size8_5_sram[1]:19 0.0006119534 +20 mux_tree_tapbuf_size8_5_sram[1]:20 4.700333e-05 +21 mux_tree_tapbuf_size8_5_sram[1]:21 5.107393e-05 +22 mux_tree_tapbuf_size8_5_sram[1]:22 0.0001370649 +23 mux_tree_tapbuf_size8_5_sram[1]:23 0.0001370649 +24 mux_tree_tapbuf_size8_5_sram[1]:24 0.0003001664 +25 mux_tree_tapbuf_size8_5_sram[1]:25 0.0003001664 +26 mux_tree_tapbuf_size8_5_sram[1]:26 0.0001916707 +27 mux_tree_tapbuf_size8_5_sram[1]:27 0.0001916707 +28 mux_tree_tapbuf_size8_5_sram[1]:28 5.518354e-05 +29 mux_tree_tapbuf_size8_5_sram[1]:29 0.0004479233 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_5_sram[1]:29 0.152 +1 mux_tree_tapbuf_size8_5_sram[1]:14 mux_bottom_ipin_11\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_5_sram[1]:14 mux_tree_tapbuf_size8_5_sram[1]:13 0.0003482143 +3 mux_tree_tapbuf_size8_5_sram[1]:14 mux_tree_tapbuf_size8_5_sram[1]:11 9.375e-05 +4 mux_tree_tapbuf_size8_5_sram[1]:14 mux_tree_tapbuf_size8_5_sram[1]:10 4.069768e-05 +5 mux_tree_tapbuf_size8_5_sram[1]:9 mux_tree_tapbuf_size8_5_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size8_5_sram[1]:8 mux_tree_tapbuf_size8_5_sram[1]:7 0.002348214 +7 mux_tree_tapbuf_size8_5_sram[1]:6 mux_bottom_ipin_11\/mux_l2_in_2_:S 0.152 +8 mux_tree_tapbuf_size8_5_sram[1]:7 mux_tree_tapbuf_size8_5_sram[1]:6 0.0045 +9 mux_tree_tapbuf_size8_5_sram[1]:12 mux_bottom_ipin_11\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_5_sram[1]:19 mux_bottom_ipin_11\/mux_l2_in_3_:S 0.152 +11 mux_tree_tapbuf_size8_5_sram[1]:19 mux_tree_tapbuf_size8_5_sram[1]:18 0.0045 +12 mux_tree_tapbuf_size8_5_sram[1]:19 mux_tree_tapbuf_size8_5_sram[1]:9 0.002924107 +13 mux_tree_tapbuf_size8_5_sram[1]:18 mux_tree_tapbuf_size8_5_sram[1]:17 0.007205357 +14 mux_tree_tapbuf_size8_5_sram[1]:16 mux_tree_tapbuf_size8_5_sram[1]:15 0.003515625 +15 mux_tree_tapbuf_size8_5_sram[1]:17 mux_tree_tapbuf_size8_5_sram[1]:16 0.0045 +16 mux_tree_tapbuf_size8_5_sram[1]:28 mux_tree_tapbuf_size8_5_sram[1]:27 0.0045 +17 mux_tree_tapbuf_size8_5_sram[1]:27 mux_tree_tapbuf_size8_5_sram[1]:26 0.002955357 +18 mux_tree_tapbuf_size8_5_sram[1]:25 mux_tree_tapbuf_size8_5_sram[1]:24 0.004026786 +19 mux_tree_tapbuf_size8_5_sram[1]:26 mux_tree_tapbuf_size8_5_sram[1]:25 0.0045 +20 mux_tree_tapbuf_size8_5_sram[1]:24 mux_tree_tapbuf_size8_5_sram[1]:23 0.0045 +21 mux_tree_tapbuf_size8_5_sram[1]:23 mux_tree_tapbuf_size8_5_sram[1]:22 0.002044643 +22 mux_tree_tapbuf_size8_5_sram[1]:21 mux_tree_tapbuf_size8_5_sram[1]:20 0.0001548913 +23 mux_tree_tapbuf_size8_5_sram[1]:22 mux_tree_tapbuf_size8_5_sram[1]:21 0.0045 +24 mux_tree_tapbuf_size8_5_sram[1]:20 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +25 mux_tree_tapbuf_size8_5_sram[1]:29 mux_tree_tapbuf_size8_5_sram[1]:28 0.0006428572 +26 mux_tree_tapbuf_size8_5_sram[1]:29 mux_tree_tapbuf_size8_5_sram[1]:19 0.005388393 +27 mux_tree_tapbuf_size8_5_sram[1]:13 mux_tree_tapbuf_size8_5_sram[1]:12 0.002109375 +28 mux_tree_tapbuf_size8_5_sram[1]:15 mux_tree_tapbuf_size8_5_sram[1]:14 0.0001686047 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004970329 //LENGTH 3.675 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_0_:X O *L 0 *C 90.335 34.000 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 87.305 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 87.305 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 87.400 34.000 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 90.297 34.000 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.954622e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002321172 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002033695 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002587054 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.000936269 //LENGTH 7.445 LUMPCC 0.0002006171 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_1_:X O *L 0 *C 85.385 31.620 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 84.470 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 84.508 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 85.515 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 85.560 37.015 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 85.560 31.665 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 85.560 31.620 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 85.385 31.620 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.883135e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.883135e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002647446 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002647446 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.83185e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.81815e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:9 3.867435e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:13 5.497004e-06 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:8 3.867435e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:12 5.497004e-06 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_0_sram[3]:3 5.229071e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_0_sram[3]:4 5.229071e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:13 3.846515e-06 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[3]:5 3.846515e-06 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0008995536 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004776786 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0003379387 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l3_in_0_:X O *L 0 *C 60.435 18.020 +*I mux_bottom_ipin_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 57.865 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 57.903 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 60.398 18.020 + +*CAP +0 mux_bottom_ipin_4\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001679694 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001679694 + +*RES +0 mux_bottom_ipin_4\/mux_l3_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_4\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005296789 //LENGTH 39.815 LUMPCC 0.001438425 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l4_in_0_:X O *L 0 *C 48.935 53.380 +*I mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 30.605 71.950 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 46.210 60.520 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 30.605 71.950 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 30.820 72.080 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 30.820 72.035 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 30.820 67.377 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 30.828 67.320 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 46.900 67.320 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 46.920 67.312 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 46.920 60.528 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 46.918 60.520 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 46.920 60.463 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 46.920 53.425 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 46.965 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 48.898 53.380 + +*CAP +0 mux_bottom_ipin_5\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001337952 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.29783e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.614138e-05 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00026697 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00026697 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004683289 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004683289 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004499135 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0004499135 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001337952 +12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0003937602 +13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0003937602 +14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0001708542 +15 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0001708542 +16 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_right_in[13]:17 0.0003796732 +17 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_right_in[13]:18 0.0003796732 +18 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:296 3.810555e-06 +19 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:295 3.810555e-06 +20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:297 0.0001620642 +21 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:306 8.322529e-05 +22 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:310 4.090553e-05 +23 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:305 0.0001620642 +24 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:310 8.322529e-05 +25 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:311 4.090553e-05 +26 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 prog_clk[0]:376 2.705011e-06 +27 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 prog_clk[0]:380 9.26975e-07 +28 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 prog_clk[0]:372 2.705011e-06 +29 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 prog_clk[0]:376 9.26975e-07 +30 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.590167e-05 +31 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.590167e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l4_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.065218e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.004158483 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.002518025 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001039141 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001062983 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.006283483 +14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.001725447 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008331875 //LENGTH 7.145 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_0_:X O *L 0 *C 60.085 31.620 +*I mux_bottom_ipin_12\/mux_l3_in_0_:A1 I *L 0.00198 *C 63.580 34.340 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 63.543 34.340 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.225 34.340 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 61.180 34.295 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 61.180 31.665 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 61.135 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.123 31.620 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000164434 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000164434 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001648858 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001648858 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.627402e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.627402e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002069197 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001543786 //LENGTH 10.400 LUMPCC 0.0006561356 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l4_in_0_:X O *L 0 *C 75.265 64.260 +*I mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 73.675 71.925 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 73.675 71.925 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 73.600 72.080 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 73.600 72.035 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 73.600 64.305 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 73.645 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 75.228 64.260 + +*CAP +0 mux_bottom_ipin_13\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.27043e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.304343e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002353285 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002353285 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001546228 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001546228 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0001324372 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0001324372 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001956306 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001956306 + +*RES +0 mux_bottom_ipin_13\/mux_l4_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001412947 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.006901786 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 8.423914e-05 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009235162 //LENGTH 6.340 LUMPCC 0.0001370493 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_3_:X O *L 0 *C 30.995 15.300 +*I mux_bottom_ipin_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 31.455 20.740 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 31.455 20.740 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 31.280 20.740 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 31.280 20.695 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 31.280 15.345 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 31.280 15.300 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 30.995 15.300 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.083654e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.965652e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002754336 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002754336 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.769601e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.541069e-05 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_4_sram[2]:12 6.852466e-05 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_4_sram[2]:13 6.852466e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_3_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.51087e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004776786 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008172183 //LENGTH 5.350 LUMPCC 0.000108682 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l3_in_0_:X O *L 0 *C 44.335 23.460 +*I mux_bottom_ipin_6\/mux_l4_in_0_:A1 I *L 0.00198 *C 42.225 25.500 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 42.263 25.500 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 44.575 25.500 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 44.620 25.455 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 44.620 23.505 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 44.620 23.460 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 44.335 23.460 + +*CAP +0 mux_bottom_ipin_6\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001583714 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001583714 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001308926 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001308926 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.610303e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.190541e-05 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_2_sram[3]:6 4.791976e-05 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_2_sram[3]:7 4.791976e-05 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_2_sram[3]:9 6.421235e-06 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_2_sram[3]:8 6.421235e-06 + +*RES +0 mux_bottom_ipin_6\/mux_l3_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_6\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002064732 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001741072 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006136589 //LENGTH 4.680 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l3_in_0_:X O *L 0 *C 20.415 19.985 +*I mux_bottom_ipin_10\/mux_l4_in_0_:A1 I *L 0.00198 *C 18.400 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 18.400 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 18.400 18.065 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 18.400 20.015 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 18.445 20.060 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 20.378 20.045 + +*CAP +0 mux_bottom_ipin_10\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.155308e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001303849 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001303849 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000159668 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000159668 + +*RES +0 mux_bottom_ipin_10\/mux_l3_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001725447 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.001741072 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_10\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004105437 //LENGTH 2.755 LUMPCC 6.657459e-05 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_2_:X O *L 0 *C 76.645 17.680 +*I mux_bottom_ipin_14\/mux_l3_in_1_:A1 I *L 0.00198 *C 78.660 18.020 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.660 18.020 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 78.660 17.680 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 76.683 17.680 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.848745e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001562049 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001272768 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.32873e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.32873e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_2_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001765625 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001440661 //LENGTH 13.060 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l4_in_0_:X O *L 0 *C 84.355 64.260 +*I mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 77.400 69.535 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 77.438 69.640 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 84.135 69.700 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 84.180 69.655 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 84.180 64.305 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 84.180 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 84.355 64.260 + +*CAP +0 mux_bottom_ipin_15\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003753901 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003753901 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002871874 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002871874 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.658749e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.691814e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l4_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.005979911 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004776786 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_145 0.0008757167 //LENGTH 6.635 LUMPCC 0.0001098814 DR + +*CONN +*I FTB_20__19:X O *L 0 *C 94.300 6.120 +*I ropt_mt_inst_745:A I *L 0.001766 *C 97.825 4.080 +*N ropt_net_145:2 *C 97.825 4.080 +*N ropt_net_145:3 *C 97.980 4.080 +*N ropt_net_145:4 *C 97.980 4.125 +*N ropt_net_145:5 *C 97.980 6.075 +*N ropt_net_145:6 *C 97.935 6.120 +*N ropt_net_145:7 *C 94.338 6.120 + +*CAP +0 FTB_20__19:X 1e-06 +1 ropt_mt_inst_745:A 1e-06 +2 ropt_net_145:2 4.716405e-05 +3 ropt_net_145:3 4.960055e-05 +4 ropt_net_145:4 0.0001300175 +5 ropt_net_145:5 0.0001300175 +6 ropt_net_145:6 0.0002035178 +7 ropt_net_145:7 0.0002035178 +8 ropt_net_145:6 chanx_left_in[19]:16 5.494072e-05 +9 ropt_net_145:7 chanx_left_in[19]:15 5.494072e-05 + +*RES +0 FTB_20__19:X ropt_net_145:7 0.152 +1 ropt_net_145:2 ropt_mt_inst_745:A 0.152 +2 ropt_net_145:3 ropt_net_145:2 8.423914e-05 +3 ropt_net_145:4 ropt_net_145:3 0.0045 +4 ropt_net_145:6 ropt_net_145:5 0.0045 +5 ropt_net_145:5 ropt_net_145:4 0.001741071 +6 ropt_net_145:7 ropt_net_145:6 0.003212054 + +*END + +*D_NET ropt_net_141 0.0007958381 //LENGTH 6.210 LUMPCC 0 DR + +*CONN +*I FTB_36__35:X O *L 0 *C 7.820 40.120 +*I ropt_mt_inst_741:A I *L 0.001766 *C 3.220 39.440 +*N ropt_net_141:2 *C 3.258 39.440 +*N ropt_net_141:3 *C 5.015 39.440 +*N ropt_net_141:4 *C 5.060 39.485 +*N ropt_net_141:5 *C 5.060 40.075 +*N ropt_net_141:6 *C 5.105 40.120 +*N ropt_net_141:7 *C 7.783 40.120 + +*CAP +0 FTB_36__35:X 1e-06 +1 ropt_mt_inst_741:A 1e-06 +2 ropt_net_141:2 0.0001207979 +3 ropt_net_141:3 0.0001207979 +4 ropt_net_141:4 6.590081e-05 +5 ropt_net_141:5 6.590081e-05 +6 ropt_net_141:6 0.0002102204 +7 ropt_net_141:7 0.0002102204 + +*RES +0 FTB_36__35:X ropt_net_141:7 0.152 +1 ropt_net_141:2 ropt_mt_inst_741:A 0.152 +2 ropt_net_141:3 ropt_net_141:2 0.001569196 +3 ropt_net_141:4 ropt_net_141:3 0.0045 +4 ropt_net_141:6 ropt_net_141:5 0.0045 +5 ropt_net_141:5 ropt_net_141:4 0.0005267858 +6 ropt_net_141:7 ropt_net_141:6 0.002390625 + +*END + +*D_NET chanx_left_out[19] 0.001316668 //LENGTH 8.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 7.095 59.160 +*P chanx_left_out[19] O *L 0.7423 *C 0.460 58.480 +*N chanx_left_out[19]:2 *C 0.460 59.160 +*N chanx_left_out[19]:3 *C 4.133 59.160 +*N chanx_left_out[19]:4 *C 4.140 59.160 +*N chanx_left_out[19]:5 *C 4.185 59.160 +*N chanx_left_out[19]:6 *C 7.058 59.160 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 chanx_left_out[19] 7.066748e-05 +2 chanx_left_out[19]:2 0.0004121983 +3 chanx_left_out[19]:3 0.0003415308 +4 chanx_left_out[19]:4 3.496955e-05 +5 chanx_left_out[19]:5 0.0002281511 +6 chanx_left_out[19]:6 0.0002281511 + +*RES +0 ropt_mt_inst_757:X chanx_left_out[19]:6 0.152 +1 chanx_left_out[19]:6 chanx_left_out[19]:5 0.002564732 +2 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0045 +3 chanx_left_out[19]:4 chanx_left_out[19]:3 0.00341 +4 chanx_left_out[19]:3 chanx_left_out[19]:2 0.0005753583 +5 chanx_left_out[19]:2 chanx_left_out[19] 0.0001065333 + +*END + +*D_NET chanx_left_out[10] 0.001394915 //LENGTH 9.320 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 7.095 27.880 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 25.840 +*N chanx_left_out[10]:2 *C 1.840 25.840 +*N chanx_left_out[10]:3 *C 1.840 26.520 +*N chanx_left_out[10]:4 *C 6.433 26.520 +*N chanx_left_out[10]:5 *C 6.440 26.578 +*N chanx_left_out[10]:6 *C 6.440 27.835 +*N chanx_left_out[10]:7 *C 6.485 27.880 +*N chanx_left_out[10]:8 *C 7.058 27.880 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 chanx_left_out[10] 6.696974e-05 +2 chanx_left_out[10]:2 0.0001215333 +3 chanx_left_out[10]:3 0.0004710984 +4 chanx_left_out[10]:4 0.0004165349 +5 chanx_left_out[10]:5 9.652562e-05 +6 chanx_left_out[10]:6 9.652562e-05 +7 chanx_left_out[10]:7 6.23637e-05 +8 chanx_left_out[10]:8 6.23637e-05 + +*RES +0 ropt_mt_inst_735:X chanx_left_out[10]:8 0.152 +1 chanx_left_out[10]:8 chanx_left_out[10]:7 0.0005111608 +2 chanx_left_out[10]:7 chanx_left_out[10]:6 0.0045 +3 chanx_left_out[10]:6 chanx_left_out[10]:5 0.001122768 +4 chanx_left_out[10]:5 chanx_left_out[10]:4 0.00341 +5 chanx_left_out[10]:4 chanx_left_out[10]:3 0.0007194916 +6 chanx_left_out[10]:2 chanx_left_out[10] 9.556666e-05 +7 chanx_left_out[10]:3 chanx_left_out[10]:2 0.0001065333 + +*END + +*D_NET chanx_left_out[1] 0.0005291709 //LENGTH 4.755 LUMPCC 0.0001118342 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 4.140 3.740 +*P chanx_left_out[1] O *L 0.7423 *C 2.300 1.290 +*N chanx_left_out[1]:2 *C 2.300 3.695 +*N chanx_left_out[1]:3 *C 2.345 3.740 +*N chanx_left_out[1]:4 *C 4.103 3.740 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 chanx_left_out[1] 0.0001219369 +2 chanx_left_out[1]:2 0.0001219369 +3 chanx_left_out[1]:3 8.623149e-05 +4 chanx_left_out[1]:4 8.623149e-05 +5 chanx_left_out[1] ropt_net_162:4 9.333696e-06 +6 chanx_left_out[1]:4 ropt_net_162:6 4.658339e-05 +7 chanx_left_out[1]:3 ropt_net_162:5 4.658339e-05 +8 chanx_left_out[1]:2 ropt_net_162:3 9.333696e-06 + +*RES +0 ropt_mt_inst_765:X chanx_left_out[1]:4 0.152 +1 chanx_left_out[1]:4 chanx_left_out[1]:3 0.001569197 +2 chanx_left_out[1]:3 chanx_left_out[1]:2 0.0045 +3 chanx_left_out[1]:2 chanx_left_out[1] 0.002147322 + +*END + +*D_NET chanx_left_out[2] 0.001853461 //LENGTH 13.660 LUMPCC 0.0002144624 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 11.695 14.620 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 12.240 +*N chanx_left_out[2]:2 *C 11.033 12.240 +*N chanx_left_out[2]:3 *C 11.040 12.298 +*N chanx_left_out[2]:4 *C 11.040 14.575 +*N chanx_left_out[2]:5 *C 11.085 14.620 +*N chanx_left_out[2]:6 *C 11.658 14.620 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 chanx_left_out[2] 0.0006663913 +2 chanx_left_out[2]:2 0.0006663913 +3 chanx_left_out[2]:3 0.000104789 +4 chanx_left_out[2]:4 0.000104789 +5 chanx_left_out[2]:5 4.781897e-05 +6 chanx_left_out[2]:6 4.781897e-05 +7 chanx_left_out[2]:6 ropt_net_166:2 3.58067e-05 +8 chanx_left_out[2]:5 ropt_net_166:3 3.58067e-05 +9 chanx_left_out[2]:4 ropt_net_166:4 7.142451e-05 +10 chanx_left_out[2]:3 ropt_net_166:5 7.142451e-05 + +*RES +0 ropt_mt_inst_748:X chanx_left_out[2]:6 0.152 +1 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0005111608 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.002033482 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.001535725 + +*END + +*D_NET chanx_left_in[8] 0.02159449 //LENGTH 140.825 LUMPCC 0.008993243 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 34.000 +*I mux_bottom_ipin_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 12.325 25.500 +*I FTB_9__8:A I *L 0.001767 *C 97.980 31.280 +*I mux_bottom_ipin_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 66.990 17.340 +*N chanx_left_in[8]:4 *C 66.990 17.340 +*N chanx_left_in[8]:5 *C 67.160 17.340 +*N chanx_left_in[8]:6 *C 67.160 17.385 +*N chanx_left_in[8]:7 *C 98.017 31.280 +*N chanx_left_in[8]:8 *C 98.395 31.280 +*N chanx_left_in[8]:9 *C 98.440 31.235 +*N chanx_left_in[8]:10 *C 98.440 29.298 +*N chanx_left_in[8]:11 *C 98.433 29.240 +*N chanx_left_in[8]:12 *C 67.168 29.240 +*N chanx_left_in[8]:13 *C 67.160 29.240 +*N chanx_left_in[8]:14 *C 67.160 34.623 +*N chanx_left_in[8]:15 *C 67.153 34.680 +*N chanx_left_in[8]:16 *C 54.910 34.680 +*N chanx_left_in[8]:17 *C 5.060 34.680 +*N chanx_left_in[8]:18 *C 12.310 25.500 +*N chanx_left_in[8]:19 *C 11.982 25.500 +*N chanx_left_in[8]:20 *C 11.960 25.455 +*N chanx_left_in[8]:21 *C 11.960 23.845 +*N chanx_left_in[8]:22 *C 11.960 23.800 +*N chanx_left_in[8]:23 *C 5.105 23.800 +*N chanx_left_in[8]:24 *C 5.060 23.845 +*N chanx_left_in[8]:25 *C 5.060 33.943 +*N chanx_left_in[8]:26 *C 5.060 34.008 + +*CAP +0 chanx_left_in[8] 0.0002399224 +1 mux_bottom_ipin_8\/mux_l1_in_2_:A1 1e-06 +2 FTB_9__8:A 1e-06 +3 mux_bottom_ipin_4\/mux_l2_in_1_:A0 1e-06 +4 chanx_left_in[8]:4 4.593074e-05 +5 chanx_left_in[8]:5 4.961352e-05 +6 chanx_left_in[8]:6 0.0006158094 +7 chanx_left_in[8]:7 5.141346e-05 +8 chanx_left_in[8]:8 5.141346e-05 +9 chanx_left_in[8]:9 0.0001485506 +10 chanx_left_in[8]:10 0.0001485506 +11 chanx_left_in[8]:11 0.001070841 +12 chanx_left_in[8]:12 0.001070841 +13 chanx_left_in[8]:13 0.0009563774 +14 chanx_left_in[8]:14 0.0003014558 +15 chanx_left_in[8]:15 0.0003821698 +16 chanx_left_in[8]:16 0.00258072 +17 chanx_left_in[8]:17 0.002255972 +18 chanx_left_in[8]:18 6.466815e-05 +19 chanx_left_in[8]:19 6.466815e-05 +20 chanx_left_in[8]:20 4.922123e-05 +21 chanx_left_in[8]:21 4.922123e-05 +22 chanx_left_in[8]:22 0.0005162045 +23 chanx_left_in[8]:23 0.0004808269 +24 chanx_left_in[8]:24 0.0005532574 +25 chanx_left_in[8]:25 0.0005532574 +26 chanx_left_in[8]:26 0.0002973439 +27 chanx_left_in[8] chanx_left_in[4] 6.705496e-05 +28 chanx_left_in[8]:6 chanx_left_in[4]:28 4.491199e-05 +29 chanx_left_in[8]:13 chanx_left_in[4]:29 4.491199e-05 +30 chanx_left_in[8]:12 chanx_left_in[4]:22 0.00098478 +31 chanx_left_in[8]:12 chanx_left_in[4]:30 0.0004617556 +32 chanx_left_in[8]:12 chanx_left_in[4]:31 5.988804e-05 +33 chanx_left_in[8]:11 chanx_left_in[4]:21 0.00098478 +34 chanx_left_in[8]:11 chanx_left_in[4]:25 0.0004617556 +35 chanx_left_in[8]:11 chanx_left_in[4]:30 5.988804e-05 +36 chanx_left_in[8]:26 chanx_left_in[4]:38 6.705496e-05 +37 chanx_left_in[8]:17 chanx_left_in[4] 0.0004708358 +38 chanx_left_in[8]:17 chanx_left_in[4]:35 0.0002168449 +39 chanx_left_in[8]:16 chanx_left_in[4]:34 0.0002168449 +40 chanx_left_in[8]:16 chanx_left_in[4]:38 0.0004708358 +41 chanx_left_in[8]:15 chanx_left_in[6]:12 0.000267021 +42 chanx_left_in[8]:17 chanx_left_in[6]:13 7.400091e-05 +43 chanx_left_in[8]:16 chanx_left_in[6]:12 7.400091e-05 +44 chanx_left_in[8]:16 chanx_left_in[6]:13 0.000267021 +45 chanx_left_in[8] chanx_left_in[16]:30 1.922518e-07 +46 chanx_left_in[8]:15 chanx_left_in[16]:28 1.014159e-05 +47 chanx_left_in[8]:12 chanx_left_in[16]:28 7.617048e-05 +48 chanx_left_in[8]:12 chanx_left_in[16]:29 9.509268e-05 +49 chanx_left_in[8]:11 chanx_left_in[16]:23 7.617048e-05 +50 chanx_left_in[8]:11 chanx_left_in[16]:28 9.509268e-05 +51 chanx_left_in[8]:26 chanx_left_in[16]:31 8.811439e-06 +52 chanx_left_in[8]:26 chanx_left_in[16]:29 1.922518e-07 +53 chanx_left_in[8]:17 chanx_left_in[16]:30 0.000112786 +54 chanx_left_in[8]:17 chanx_left_in[16]:32 8.811439e-06 +55 chanx_left_in[8]:17 chanx_left_in[16]:29 1.522761e-06 +56 chanx_left_in[8]:16 chanx_left_in[16]:28 1.522761e-06 +57 chanx_left_in[8]:16 chanx_left_in[16]:29 0.0001229276 +58 chanx_left_in[8]:15 chanx_right_in[9] 0.0004931902 +59 chanx_left_in[8]:16 chanx_right_in[9]:20 0.0004931902 +60 chanx_left_in[8]:12 chanx_right_in[12]:30 0.0003460722 +61 chanx_left_in[8]:11 chanx_right_in[12]:31 0.0003460722 +62 chanx_left_in[8]:20 chanx_right_in[12]:10 4.347761e-05 +63 chanx_left_in[8]:21 chanx_right_in[12]:20 4.347761e-05 +64 chanx_left_in[8] chanx_right_in[18]:12 8.631102e-06 +65 chanx_left_in[8]:24 chanx_right_in[18]:11 5.413083e-05 +66 chanx_left_in[8]:24 chanx_right_in[18]:10 2.866951e-05 +67 chanx_left_in[8]:25 chanx_right_in[18]:7 5.413083e-05 +68 chanx_left_in[8]:25 chanx_right_in[18]:11 2.866951e-05 +69 chanx_left_in[8]:26 chanx_right_in[18]:13 8.631102e-06 +70 chanx_left_in[8]:17 chanx_right_in[18]:12 0.0002162907 +71 chanx_left_in[8]:16 chanx_right_in[18]:13 0.0002162907 +72 chanx_left_in[8]:17 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0001851169 +73 chanx_left_in[8]:16 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.0001851169 +74 chanx_left_in[8]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001169559 +75 chanx_left_in[8]:13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001169559 +76 chanx_left_in[8]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.227665e-05 +77 chanx_left_in[8]:21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.227665e-05 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:26 0.0006000333 +1 chanx_left_in[8]:14 chanx_left_in[8]:13 0.004805804 +2 chanx_left_in[8]:15 chanx_left_in[8]:14 0.00341 +3 chanx_left_in[8]:5 chanx_left_in[8]:4 9.239131e-05 +4 chanx_left_in[8]:6 chanx_left_in[8]:5 0.0045 +5 chanx_left_in[8]:4 mux_bottom_ipin_4\/mux_l2_in_1_:A0 0.152 +6 chanx_left_in[8]:13 chanx_left_in[8]:12 0.00341 +7 chanx_left_in[8]:13 chanx_left_in[8]:6 0.01058482 +8 chanx_left_in[8]:12 chanx_left_in[8]:11 0.004898183 +9 chanx_left_in[8]:10 chanx_left_in[8]:9 0.001729911 +10 chanx_left_in[8]:11 chanx_left_in[8]:10 0.00341 +11 chanx_left_in[8]:8 chanx_left_in[8]:7 0.0003370536 +12 chanx_left_in[8]:9 chanx_left_in[8]:8 0.0045 +13 chanx_left_in[8]:7 FTB_9__8:A 0.152 +14 chanx_left_in[8]:18 mux_bottom_ipin_8\/mux_l1_in_2_:A1 0.152 +15 chanx_left_in[8]:19 chanx_left_in[8]:18 0.0001779891 +16 chanx_left_in[8]:20 chanx_left_in[8]:19 0.0045 +17 chanx_left_in[8]:22 chanx_left_in[8]:21 0.0045 +18 chanx_left_in[8]:21 chanx_left_in[8]:20 0.0014375 +19 chanx_left_in[8]:23 chanx_left_in[8]:22 0.006120536 +20 chanx_left_in[8]:24 chanx_left_in[8]:23 0.0045 +21 chanx_left_in[8]:25 chanx_left_in[8]:24 0.009015625 +22 chanx_left_in[8]:26 chanx_left_in[8]:25 0.00341 +23 chanx_left_in[8]:26 chanx_left_in[8]:17 0.0001053583 +24 chanx_left_in[8]:17 chanx_left_in[8]:16 0.007809833 +25 chanx_left_in[8]:16 chanx_left_in[8]:15 0.001917992 + +*END + +*D_NET top_grid_pin_19_[0] 0.00118792 //LENGTH 9.505 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 40.425 69.700 +*P top_grid_pin_19_[0] O *L 0.7423 *C 36.800 74.835 +*N top_grid_pin_19_[0]:2 *C 36.800 70.085 +*N top_grid_pin_19_[0]:3 *C 36.845 70.040 +*N top_grid_pin_19_[0]:4 *C 38.180 70.040 +*N top_grid_pin_19_[0]:5 *C 38.180 69.700 +*N top_grid_pin_19_[0]:6 *C 40.388 69.700 + +*CAP +0 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_19_[0] 0.0002714934 +2 top_grid_pin_19_[0]:2 0.0002714934 +3 top_grid_pin_19_[0]:3 0.0001232613 +4 top_grid_pin_19_[0]:4 0.0001480471 +5 top_grid_pin_19_[0]:5 0.0001987053 +6 top_grid_pin_19_[0]:6 0.0001739195 + +*RES +0 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_19_[0]:6 0.152 +1 top_grid_pin_19_[0]:6 top_grid_pin_19_[0]:5 0.001970982 +2 top_grid_pin_19_[0]:3 top_grid_pin_19_[0]:2 0.0045 +3 top_grid_pin_19_[0]:2 top_grid_pin_19_[0] 0.004241071 +4 top_grid_pin_19_[0]:4 top_grid_pin_19_[0]:3 0.001191964 +5 top_grid_pin_19_[0]:5 top_grid_pin_19_[0]:4 0.0003035715 + +*END + +*D_NET top_grid_pin_21_[0] 0.001875507 //LENGTH 16.470 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 28.925 72.080 +*P top_grid_pin_21_[0] O *L 0.7423 *C 16.100 74.870 +*N top_grid_pin_21_[0]:2 *C 16.100 74.165 +*N top_grid_pin_21_[0]:3 *C 16.145 74.120 +*N top_grid_pin_21_[0]:4 *C 28.935 74.120 +*N top_grid_pin_21_[0]:5 *C 28.980 74.075 +*N top_grid_pin_21_[0]:6 *C 28.980 72.125 +*N top_grid_pin_21_[0]:7 *C 28.925 72.080 + +*CAP +0 mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_21_[0] 5.737101e-05 +2 top_grid_pin_21_[0]:2 5.737101e-05 +3 top_grid_pin_21_[0]:3 0.0007587799 +4 top_grid_pin_21_[0]:4 0.0007587799 +5 top_grid_pin_21_[0]:5 0.0001091893 +6 top_grid_pin_21_[0]:6 0.0001091893 +7 top_grid_pin_21_[0]:7 2.382685e-05 + +*RES +0 mux_bottom_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_21_[0]:7 0.152 +1 top_grid_pin_21_[0]:7 top_grid_pin_21_[0]:6 0.0045 +2 top_grid_pin_21_[0]:6 top_grid_pin_21_[0]:5 0.001741072 +3 top_grid_pin_21_[0]:4 top_grid_pin_21_[0]:3 0.01141964 +4 top_grid_pin_21_[0]:5 top_grid_pin_21_[0]:4 0.0045 +5 top_grid_pin_21_[0]:3 top_grid_pin_21_[0]:2 0.0045 +6 top_grid_pin_21_[0]:2 top_grid_pin_21_[0] 0.0006294643 + +*END + +*D_NET top_grid_pin_29_[0] 0.0007875504 //LENGTH 5.905 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 72.220 72.080 +*P top_grid_pin_29_[0] O *L 0.7423 *C 74.520 74.835 +*N top_grid_pin_29_[0]:2 *C 74.060 74.800 +*N top_grid_pin_29_[0]:3 *C 74.060 72.465 +*N top_grid_pin_29_[0]:4 *C 74.015 72.420 +*N top_grid_pin_29_[0]:5 *C 73.140 72.420 +*N top_grid_pin_29_[0]:6 *C 73.140 72.080 +*N top_grid_pin_29_[0]:7 *C 72.258 72.080 + +*CAP +0 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_29_[0] 3.237291e-05 +2 top_grid_pin_29_[0]:2 0.0002129984 +3 top_grid_pin_29_[0]:3 0.0001806255 +4 top_grid_pin_29_[0]:4 8.418041e-05 +5 top_grid_pin_29_[0]:5 0.0001110355 +6 top_grid_pin_29_[0]:6 9.609636e-05 +7 top_grid_pin_29_[0]:7 6.924125e-05 + +*RES +0 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_29_[0]:7 0.152 +1 top_grid_pin_29_[0]:7 top_grid_pin_29_[0]:6 0.0007879465 +2 top_grid_pin_29_[0]:4 top_grid_pin_29_[0]:3 0.0045 +3 top_grid_pin_29_[0]:3 top_grid_pin_29_[0]:2 0.002084821 +4 top_grid_pin_29_[0]:6 top_grid_pin_29_[0]:5 0.0003035715 +5 top_grid_pin_29_[0]:5 top_grid_pin_29_[0]:4 0.00078125 +6 top_grid_pin_29_[0]:2 top_grid_pin_29_[0] 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.004475489 //LENGTH 33.955 LUMPCC 0.0001041195 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 100.585 39.100 +*I mux_bottom_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 94.400 30.600 +*I mux_bottom_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 90.260 29.240 +*I mux_bottom_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 91.180 23.120 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.335 37.060 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 90.373 37.060 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 91.218 23.120 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 92.875 23.120 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 92.920 23.165 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 90.297 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 92.875 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 92.920 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 94.363 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 92.965 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 92.920 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 92.920 37.015 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 92.920 37.060 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 100.235 37.060 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 100.280 37.105 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 100.280 39.055 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 100.280 39.100 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 100.585 39.100 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_ipin_0\/mux_l1_in_2_:S 1e-06 +4 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 0.0001634052 +6 mux_tree_tapbuf_size10_0_sram[0]:6 0.0001792175 +7 mux_tree_tapbuf_size10_0_sram[0]:7 0.0001792175 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.0003566399 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0002458126 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0002458126 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.000469111 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0001261463 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0001261463 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0004467387 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0003341261 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0006857231 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0004870275 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0001140783 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001140783 +20 mux_tree_tapbuf_size10_0_sram[0]:20 4.905149e-05 +21 mux_tree_tapbuf_size10_0_sram[0]:21 4.403803e-05 +22 mux_tree_tapbuf_size10_0_sram[0]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.666658e-07 +23 mux_tree_tapbuf_size10_0_sram[0]:14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.129307e-05 +24 mux_tree_tapbuf_size10_0_sram[0]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.666658e-07 +25 mux_tree_tapbuf_size10_0_sram[0]:15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.129307e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:21 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.002301339 +2 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.0045 +3 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:8 0.005424107 +4 mux_tree_tapbuf_size10_0_sram[0]:9 mux_bottom_ipin_0\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_0_sram[0]:5 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.00653125 +7 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.0045 +8 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0045 +9 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.001741072 +10 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.0001657609 +11 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.001479911 +12 mux_tree_tapbuf_size10_0_sram[0]:8 mux_tree_tapbuf_size10_0_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size10_0_sram[0]:6 mux_bottom_ipin_0\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.001247768 +15 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +16 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:11 0.001214286 +17 mux_tree_tapbuf_size10_0_sram[0]:12 mux_bottom_ipin_0\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.0045 +19 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:5 0.002274554 +20 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_0_sram[0]:14 0.005727679 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.001517741 //LENGTH 12.595 LUMPCC 0.0001116414 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 50.445 69.700 +*I mem_bottom_ipin_1\/FTB_2__41:A I *L 0.001746 *C 42.320 66.640 +*I mux_bottom_ipin_1\/mux_l4_in_0_:S I *L 0.00357 *C 45.640 66.935 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 45.640 66.935 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 42.358 66.640 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 45.640 66.640 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 48.255 66.640 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 48.300 66.685 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 48.300 69.655 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 48.345 69.700 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 50.407 69.700 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_1\/FTB_2__41:A 1e-06 +2 mux_bottom_ipin_1\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 6.689543e-05 +4 mux_tree_tapbuf_size10_1_sram[3]:4 0.000192504 +5 mux_tree_tapbuf_size10_1_sram[3]:5 0.0003741132 +6 mux_tree_tapbuf_size10_1_sram[3]:6 0.0001474498 +7 mux_tree_tapbuf_size10_1_sram[3]:7 0.0001725919 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.0001725919 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.0001384765 +10 mux_tree_tapbuf_size10_1_sram[3]:10 0.0001384765 +11 mux_tree_tapbuf_size10_1_sram[3]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.799956e-05 +12 mux_tree_tapbuf_size10_1_sram[3]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.821168e-06 +13 mux_tree_tapbuf_size10_1_sram[3]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.821168e-06 +14 mux_tree_tapbuf_size10_1_sram[3]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.799956e-05 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:4 mem_bottom_ipin_1\/FTB_2__41:A 0.152 +2 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.002334822 +3 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 0.0045 +4 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.002651786 +6 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.001841518 +7 mux_tree_tapbuf_size10_1_sram[3]:3 mux_bottom_ipin_1\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:4 0.002930804 +9 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:3 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[0] 0.003192659 //LENGTH 24.700 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.485 39.440 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.430 44.540 +*I mux_bottom_ipin_5\/mux_l1_in_2_:S I *L 0.00357 *C 61.280 47.310 +*I mux_bottom_ipin_5\/mux_l1_in_1_:S I *L 0.00357 *C 59.900 53.040 +*I mux_bottom_ipin_5\/mux_l1_in_0_:S I *L 0.00357 *C 64.040 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:5 *C 64.002 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:6 *C 63.480 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:7 *C 59.938 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:8 *C 61.640 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:9 *C 61.640 52.700 +*N mux_tree_tapbuf_size10_3_sram[0]:10 *C 63.480 52.730 +*N mux_tree_tapbuf_size10_3_sram[0]:11 *C 63.480 52.655 +*N mux_tree_tapbuf_size10_3_sram[0]:12 *C 63.480 47.645 +*N mux_tree_tapbuf_size10_3_sram[0]:13 *C 63.435 47.600 +*N mux_tree_tapbuf_size10_3_sram[0]:14 *C 61.280 47.310 +*N mux_tree_tapbuf_size10_3_sram[0]:15 *C 61.338 47.600 +*N mux_tree_tapbuf_size10_3_sram[0]:16 *C 61.180 47.555 +*N mux_tree_tapbuf_size10_3_sram[0]:17 *C 60.453 44.513 +*N mux_tree_tapbuf_size10_3_sram[0]:18 *C 60.465 44.200 +*N mux_tree_tapbuf_size10_3_sram[0]:19 *C 61.135 44.200 +*N mux_tree_tapbuf_size10_3_sram[0]:20 *C 61.180 44.200 +*N mux_tree_tapbuf_size10_3_sram[0]:21 *C 61.180 39.485 +*N mux_tree_tapbuf_size10_3_sram[0]:22 *C 61.180 39.440 +*N mux_tree_tapbuf_size10_3_sram[0]:23 *C 61.485 39.440 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_5\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_ipin_5\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_3_sram[0]:5 5.677581e-05 +6 mux_tree_tapbuf_size10_3_sram[0]:6 8.512433e-05 +7 mux_tree_tapbuf_size10_3_sram[0]:7 0.0001450605 +8 mux_tree_tapbuf_size10_3_sram[0]:8 0.000170115 +9 mux_tree_tapbuf_size10_3_sram[0]:9 0.0001786548 +10 mux_tree_tapbuf_size10_3_sram[0]:10 0.0001819489 +11 mux_tree_tapbuf_size10_3_sram[0]:11 0.0003035449 +12 mux_tree_tapbuf_size10_3_sram[0]:12 0.0003035449 +13 mux_tree_tapbuf_size10_3_sram[0]:13 0.0001729316 +14 mux_tree_tapbuf_size10_3_sram[0]:14 6.163041e-05 +15 mux_tree_tapbuf_size10_3_sram[0]:15 0.0002060695 +16 mux_tree_tapbuf_size10_3_sram[0]:16 0.0002278176 +17 mux_tree_tapbuf_size10_3_sram[0]:17 2.896386e-05 +18 mux_tree_tapbuf_size10_3_sram[0]:18 0.0001018399 +19 mux_tree_tapbuf_size10_3_sram[0]:19 7.287608e-05 +20 mux_tree_tapbuf_size10_3_sram[0]:20 0.0005245712 +21 mux_tree_tapbuf_size10_3_sram[0]:21 0.000264627 +22 mux_tree_tapbuf_size10_3_sram[0]:22 5.288848e-05 +23 mux_tree_tapbuf_size10_3_sram[0]:23 4.867436e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_3_sram[0]:23 0.152 +1 mux_tree_tapbuf_size10_3_sram[0]:17 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size10_3_sram[0]:19 mux_tree_tapbuf_size10_3_sram[0]:18 0.0005982143 +3 mux_tree_tapbuf_size10_3_sram[0]:20 mux_tree_tapbuf_size10_3_sram[0]:19 0.0045 +4 mux_tree_tapbuf_size10_3_sram[0]:20 mux_tree_tapbuf_size10_3_sram[0]:16 0.002995536 +5 mux_tree_tapbuf_size10_3_sram[0]:13 mux_tree_tapbuf_size10_3_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size10_3_sram[0]:12 mux_tree_tapbuf_size10_3_sram[0]:11 0.004473214 +7 mux_tree_tapbuf_size10_3_sram[0]:10 mux_tree_tapbuf_size10_3_sram[0]:9 0.001642857 +8 mux_tree_tapbuf_size10_3_sram[0]:10 mux_tree_tapbuf_size10_3_sram[0]:6 0.0002767857 +9 mux_tree_tapbuf_size10_3_sram[0]:11 mux_tree_tapbuf_size10_3_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size10_3_sram[0]:22 mux_tree_tapbuf_size10_3_sram[0]:21 0.0045 +11 mux_tree_tapbuf_size10_3_sram[0]:21 mux_tree_tapbuf_size10_3_sram[0]:20 0.004209822 +12 mux_tree_tapbuf_size10_3_sram[0]:23 mux_tree_tapbuf_size10_3_sram[0]:22 0.0001657609 +13 mux_tree_tapbuf_size10_3_sram[0]:15 mux_tree_tapbuf_size10_3_sram[0]:14 0.000125 +14 mux_tree_tapbuf_size10_3_sram[0]:15 mux_tree_tapbuf_size10_3_sram[0]:13 0.001872768 +15 mux_tree_tapbuf_size10_3_sram[0]:16 mux_tree_tapbuf_size10_3_sram[0]:15 0.0045 +16 mux_tree_tapbuf_size10_3_sram[0]:14 mux_bottom_ipin_5\/mux_l1_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_3_sram[0]:7 mux_bottom_ipin_5\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_3_sram[0]:5 mux_bottom_ipin_5\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_3_sram[0]:8 mux_tree_tapbuf_size10_3_sram[0]:7 0.001520089 +20 mux_tree_tapbuf_size10_3_sram[0]:18 mux_tree_tapbuf_size10_3_sram[0]:17 0.0002111487 +21 mux_tree_tapbuf_size10_3_sram[0]:9 mux_tree_tapbuf_size10_3_sram[0]:8 0.0003035715 +22 mux_tree_tapbuf_size10_3_sram[0]:6 mux_tree_tapbuf_size10_3_sram[0]:5 0.0004665179 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[0] 0.003971637 //LENGTH 30.340 LUMPCC 0.0001517222 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 16.865 47.940 +*I mux_bottom_ipin_9\/mux_l1_in_2_:S I *L 0.00357 *C 16.000 51.000 +*I mux_bottom_ipin_9\/mux_l1_in_1_:S I *L 0.00357 *C 18.040 52.360 +*I mux_bottom_ipin_9\/mux_l1_in_0_:S I *L 0.00357 *C 19.880 55.760 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 15.355 60.860 +*N mux_tree_tapbuf_size10_5_sram[0]:5 *C 15.393 60.860 +*N mux_tree_tapbuf_size10_5_sram[0]:6 *C 16.055 60.860 +*N mux_tree_tapbuf_size10_5_sram[0]:7 *C 16.100 60.815 +*N mux_tree_tapbuf_size10_5_sram[0]:8 *C 19.918 55.760 +*N mux_tree_tapbuf_size10_5_sram[0]:9 *C 20.240 55.760 +*N mux_tree_tapbuf_size10_5_sram[0]:10 *C 20.240 55.420 +*N mux_tree_tapbuf_size10_5_sram[0]:11 *C 16.145 55.420 +*N mux_tree_tapbuf_size10_5_sram[0]:12 *C 16.100 55.420 +*N mux_tree_tapbuf_size10_5_sram[0]:13 *C 16.100 52.360 +*N mux_tree_tapbuf_size10_5_sram[0]:14 *C 18.003 52.360 +*N mux_tree_tapbuf_size10_5_sram[0]:15 *C 15.963 51.000 +*N mux_tree_tapbuf_size10_5_sram[0]:16 *C 13.385 51.000 +*N mux_tree_tapbuf_size10_5_sram[0]:17 *C 13.340 51.045 +*N mux_tree_tapbuf_size10_5_sram[0]:18 *C 13.340 52.315 +*N mux_tree_tapbuf_size10_5_sram[0]:19 *C 13.385 52.360 +*N mux_tree_tapbuf_size10_5_sram[0]:20 *C 16.560 52.360 +*N mux_tree_tapbuf_size10_5_sram[0]:21 *C 16.560 52.315 +*N mux_tree_tapbuf_size10_5_sram[0]:22 *C 16.560 47.985 +*N mux_tree_tapbuf_size10_5_sram[0]:23 *C 16.560 47.940 +*N mux_tree_tapbuf_size10_5_sram[0]:24 *C 16.865 47.940 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l1_in_2_:S 1e-06 +2 mux_bottom_ipin_9\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_ipin_9\/mux_l1_in_0_:S 1e-06 +4 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_5_sram[0]:5 6.929685e-05 +6 mux_tree_tapbuf_size10_5_sram[0]:6 6.929685e-05 +7 mux_tree_tapbuf_size10_5_sram[0]:7 0.0003169157 +8 mux_tree_tapbuf_size10_5_sram[0]:8 4.336335e-05 +9 mux_tree_tapbuf_size10_5_sram[0]:9 7.017277e-05 +10 mux_tree_tapbuf_size10_5_sram[0]:10 0.0002996071 +11 mux_tree_tapbuf_size10_5_sram[0]:11 0.0002727977 +12 mux_tree_tapbuf_size10_5_sram[0]:12 0.0005291128 +13 mux_tree_tapbuf_size10_5_sram[0]:13 0.0002112973 +14 mux_tree_tapbuf_size10_5_sram[0]:14 0.0001097094 +15 mux_tree_tapbuf_size10_5_sram[0]:15 0.000216471 +16 mux_tree_tapbuf_size10_5_sram[0]:16 0.000216471 +17 mux_tree_tapbuf_size10_5_sram[0]:17 8.781913e-05 +18 mux_tree_tapbuf_size10_5_sram[0]:18 8.781913e-05 +19 mux_tree_tapbuf_size10_5_sram[0]:19 0.0002266424 +20 mux_tree_tapbuf_size10_5_sram[0]:20 0.0003711138 +21 mux_tree_tapbuf_size10_5_sram[0]:21 0.0002761385 +22 mux_tree_tapbuf_size10_5_sram[0]:22 0.0002407573 +23 mux_tree_tapbuf_size10_5_sram[0]:23 5.115998e-05 +24 mux_tree_tapbuf_size10_5_sram[0]:24 4.895249e-05 +25 mux_tree_tapbuf_size10_5_sram[0]:21 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.716828e-05 +26 mux_tree_tapbuf_size10_5_sram[0]:18 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.208905e-07 +27 mux_tree_tapbuf_size10_5_sram[0]:17 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.208905e-07 +28 mux_tree_tapbuf_size10_5_sram[0]:11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.25204e-05 +29 mux_tree_tapbuf_size10_5_sram[0]:12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.638842e-06 +30 mux_tree_tapbuf_size10_5_sram[0]:12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.80127e-05 +31 mux_tree_tapbuf_size10_5_sram[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.638842e-06 +32 mux_tree_tapbuf_size10_5_sram[0]:22 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.716828e-05 +33 mux_tree_tapbuf_size10_5_sram[0]:10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.25204e-05 +34 mux_tree_tapbuf_size10_5_sram[0]:13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.80127e-05 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_5_sram[0]:24 0.152 +1 mux_tree_tapbuf_size10_5_sram[0]:20 mux_tree_tapbuf_size10_5_sram[0]:19 0.002834822 +2 mux_tree_tapbuf_size10_5_sram[0]:20 mux_tree_tapbuf_size10_5_sram[0]:14 0.001287947 +3 mux_tree_tapbuf_size10_5_sram[0]:21 mux_tree_tapbuf_size10_5_sram[0]:20 0.0045 +4 mux_tree_tapbuf_size10_5_sram[0]:21 mux_tree_tapbuf_size10_5_sram[0]:13 0.0004107143 +5 mux_tree_tapbuf_size10_5_sram[0]:19 mux_tree_tapbuf_size10_5_sram[0]:18 0.0045 +6 mux_tree_tapbuf_size10_5_sram[0]:18 mux_tree_tapbuf_size10_5_sram[0]:17 0.001133928 +7 mux_tree_tapbuf_size10_5_sram[0]:16 mux_tree_tapbuf_size10_5_sram[0]:15 0.00230134 +8 mux_tree_tapbuf_size10_5_sram[0]:17 mux_tree_tapbuf_size10_5_sram[0]:16 0.0045 +9 mux_tree_tapbuf_size10_5_sram[0]:15 mux_bottom_ipin_9\/mux_l1_in_2_:S 0.152 +10 mux_tree_tapbuf_size10_5_sram[0]:14 mux_bottom_ipin_9\/mux_l1_in_1_:S 0.152 +11 mux_tree_tapbuf_size10_5_sram[0]:11 mux_tree_tapbuf_size10_5_sram[0]:10 0.00365625 +12 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:11 0.0045 +13 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:7 0.004816964 +14 mux_tree_tapbuf_size10_5_sram[0]:8 mux_bottom_ipin_9\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size10_5_sram[0]:6 mux_tree_tapbuf_size10_5_sram[0]:5 0.0005915179 +16 mux_tree_tapbuf_size10_5_sram[0]:7 mux_tree_tapbuf_size10_5_sram[0]:6 0.0045 +17 mux_tree_tapbuf_size10_5_sram[0]:5 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size10_5_sram[0]:23 mux_tree_tapbuf_size10_5_sram[0]:22 0.0045 +19 mux_tree_tapbuf_size10_5_sram[0]:22 mux_tree_tapbuf_size10_5_sram[0]:21 0.003866072 +20 mux_tree_tapbuf_size10_5_sram[0]:24 mux_tree_tapbuf_size10_5_sram[0]:23 0.0001657609 +21 mux_tree_tapbuf_size10_5_sram[0]:10 mux_tree_tapbuf_size10_5_sram[0]:9 0.0003035715 +22 mux_tree_tapbuf_size10_5_sram[0]:9 mux_tree_tapbuf_size10_5_sram[0]:8 0.0002879465 +23 mux_tree_tapbuf_size10_5_sram[0]:13 mux_tree_tapbuf_size10_5_sram[0]:12 0.002732143 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[3] 0.001582509 //LENGTH 13.310 LUMPCC 0.0001174411 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 70.225 39.440 +*I mux_bottom_ipin_12\/mux_l4_in_0_:S I *L 0.00357 *C 67.260 36.720 +*I mem_bottom_ipin_12\/FTB_7__46:A I *L 0.001746 *C 70.840 44.880 +*N mux_tree_tapbuf_size10_6_sram[3]:3 *C 70.803 44.880 +*N mux_tree_tapbuf_size10_6_sram[3]:4 *C 70.425 44.880 +*N mux_tree_tapbuf_size10_6_sram[3]:5 *C 70.380 44.835 +*N mux_tree_tapbuf_size10_6_sram[3]:6 *C 70.380 39.485 +*N mux_tree_tapbuf_size10_6_sram[3]:7 *C 70.258 39.440 +*N mux_tree_tapbuf_size10_6_sram[3]:8 *C 67.297 36.720 +*N mux_tree_tapbuf_size10_6_sram[3]:9 *C 69.415 36.720 +*N mux_tree_tapbuf_size10_6_sram[3]:10 *C 69.460 36.765 +*N mux_tree_tapbuf_size10_6_sram[3]:11 *C 69.460 39.395 +*N mux_tree_tapbuf_size10_6_sram[3]:12 *C 69.505 39.440 +*N mux_tree_tapbuf_size10_6_sram[3]:13 *C 70.188 39.440 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_12\/FTB_7__46:A 1e-06 +3 mux_tree_tapbuf_size10_6_sram[3]:3 2.204068e-05 +4 mux_tree_tapbuf_size10_6_sram[3]:4 2.204068e-05 +5 mux_tree_tapbuf_size10_6_sram[3]:5 0.0002709857 +6 mux_tree_tapbuf_size10_6_sram[3]:6 0.0002709857 +7 mux_tree_tapbuf_size10_6_sram[3]:7 2.433486e-05 +8 mux_tree_tapbuf_size10_6_sram[3]:8 0.0002003849 +9 mux_tree_tapbuf_size10_6_sram[3]:9 0.0002003849 +10 mux_tree_tapbuf_size10_6_sram[3]:10 0.0001520192 +11 mux_tree_tapbuf_size10_6_sram[3]:11 0.0001520192 +12 mux_tree_tapbuf_size10_6_sram[3]:12 6.126862e-05 +13 mux_tree_tapbuf_size10_6_sram[3]:13 8.560347e-05 +14 mux_tree_tapbuf_size10_6_sram[3]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 3.038442e-05 +15 mux_tree_tapbuf_size10_6_sram[3]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 2.833611e-05 +16 mux_tree_tapbuf_size10_6_sram[3]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 3.038442e-05 +17 mux_tree_tapbuf_size10_6_sram[3]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 2.833611e-05 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_6_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_6_sram[3]:12 mux_tree_tapbuf_size10_6_sram[3]:11 0.0045 +2 mux_tree_tapbuf_size10_6_sram[3]:11 mux_tree_tapbuf_size10_6_sram[3]:10 0.002348214 +3 mux_tree_tapbuf_size10_6_sram[3]:9 mux_tree_tapbuf_size10_6_sram[3]:8 0.001890625 +4 mux_tree_tapbuf_size10_6_sram[3]:10 mux_tree_tapbuf_size10_6_sram[3]:9 0.0045 +5 mux_tree_tapbuf_size10_6_sram[3]:8 mux_bottom_ipin_12\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_6_sram[3]:7 mux_tree_tapbuf_size10_6_sram[3]:6 0.0045 +7 mux_tree_tapbuf_size10_6_sram[3]:6 mux_tree_tapbuf_size10_6_sram[3]:5 0.004776786 +8 mux_tree_tapbuf_size10_6_sram[3]:4 mux_tree_tapbuf_size10_6_sram[3]:3 0.0003370536 +9 mux_tree_tapbuf_size10_6_sram[3]:5 mux_tree_tapbuf_size10_6_sram[3]:4 0.0045 +10 mux_tree_tapbuf_size10_6_sram[3]:3 mem_bottom_ipin_12\/FTB_7__46:A 0.152 +11 mux_tree_tapbuf_size10_6_sram[3]:13 mux_tree_tapbuf_size10_6_sram[3]:12 0.000609375 +12 mux_tree_tapbuf_size10_6_sram[3]:13 mux_tree_tapbuf_size10_6_sram[3]:7 6.25e-05 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[0] 0.005515927 //LENGTH 45.445 LUMPCC 0.0001390139 DR + +*CONN +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 95.985 47.940 +*I mux_top_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 96.260 29.240 +*I mux_top_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 96.240 23.800 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 94.015 15.300 +*I mux_top_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 94.860 19.720 +*N mux_tree_tapbuf_size10_8_sram[0]:5 *C 94.898 19.720 +*N mux_tree_tapbuf_size10_8_sram[0]:6 *C 94.053 15.300 +*N mux_tree_tapbuf_size10_8_sram[0]:7 *C 96.095 15.300 +*N mux_tree_tapbuf_size10_8_sram[0]:8 *C 96.140 15.345 +*N mux_tree_tapbuf_size10_8_sram[0]:9 *C 96.140 19.675 +*N mux_tree_tapbuf_size10_8_sram[0]:10 *C 96.140 19.750 +*N mux_tree_tapbuf_size10_8_sram[0]:11 *C 96.140 20.060 +*N mux_tree_tapbuf_size10_8_sram[0]:12 *C 97.935 20.060 +*N mux_tree_tapbuf_size10_8_sram[0]:13 *C 97.980 20.105 +*N mux_tree_tapbuf_size10_8_sram[0]:14 *C 96.278 23.800 +*N mux_tree_tapbuf_size10_8_sram[0]:15 *C 97.935 23.800 +*N mux_tree_tapbuf_size10_8_sram[0]:16 *C 97.980 23.800 +*N mux_tree_tapbuf_size10_8_sram[0]:17 *C 97.980 29.240 +*N mux_tree_tapbuf_size10_8_sram[0]:18 *C 96.297 29.240 +*N mux_tree_tapbuf_size10_8_sram[0]:19 *C 97.015 29.240 +*N mux_tree_tapbuf_size10_8_sram[0]:20 *C 97.060 29.240 +*N mux_tree_tapbuf_size10_8_sram[0]:21 *C 97.060 47.895 +*N mux_tree_tapbuf_size10_8_sram[0]:22 *C 97.015 47.940 +*N mux_tree_tapbuf_size10_8_sram[0]:23 *C 96.023 47.940 + +*CAP +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_ipin_0\/mux_l1_in_0_:S 1e-06 +2 mux_top_ipin_0\/mux_l1_in_2_:S 1e-06 +3 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_ipin_0\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_8_sram[0]:5 0.0001144846 +6 mux_tree_tapbuf_size10_8_sram[0]:6 0.00018477 +7 mux_tree_tapbuf_size10_8_sram[0]:7 0.00018477 +8 mux_tree_tapbuf_size10_8_sram[0]:8 0.0002670232 +9 mux_tree_tapbuf_size10_8_sram[0]:9 0.0002670232 +10 mux_tree_tapbuf_size10_8_sram[0]:10 0.0001428368 +11 mux_tree_tapbuf_size10_8_sram[0]:11 0.0001714085 +12 mux_tree_tapbuf_size10_8_sram[0]:12 0.0001430563 +13 mux_tree_tapbuf_size10_8_sram[0]:13 0.0002564133 +14 mux_tree_tapbuf_size10_8_sram[0]:14 0.000158812 +15 mux_tree_tapbuf_size10_8_sram[0]:15 0.000158812 +16 mux_tree_tapbuf_size10_8_sram[0]:16 0.0006063103 +17 mux_tree_tapbuf_size10_8_sram[0]:17 0.0003807267 +18 mux_tree_tapbuf_size10_8_sram[0]:18 7.935582e-05 +19 mux_tree_tapbuf_size10_8_sram[0]:19 7.935582e-05 +20 mux_tree_tapbuf_size10_8_sram[0]:20 0.001027493 +21 mux_tree_tapbuf_size10_8_sram[0]:21 0.000965981 +22 mux_tree_tapbuf_size10_8_sram[0]:22 9.164083e-05 +23 mux_tree_tapbuf_size10_8_sram[0]:23 9.164083e-05 +24 mux_tree_tapbuf_size10_8_sram[0]:20 ropt_net_169:5 6.950697e-05 +25 mux_tree_tapbuf_size10_8_sram[0]:21 ropt_net_169:4 6.950697e-05 + +*RES +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_8_sram[0]:23 0.152 +1 mux_tree_tapbuf_size10_8_sram[0]:12 mux_tree_tapbuf_size10_8_sram[0]:11 0.001602679 +2 mux_tree_tapbuf_size10_8_sram[0]:13 mux_tree_tapbuf_size10_8_sram[0]:12 0.0045 +3 mux_tree_tapbuf_size10_8_sram[0]:15 mux_tree_tapbuf_size10_8_sram[0]:14 0.001479911 +4 mux_tree_tapbuf_size10_8_sram[0]:16 mux_tree_tapbuf_size10_8_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size10_8_sram[0]:16 mux_tree_tapbuf_size10_8_sram[0]:13 0.003299107 +6 mux_tree_tapbuf_size10_8_sram[0]:14 mux_top_ipin_0\/mux_l1_in_2_:S 0.152 +7 mux_tree_tapbuf_size10_8_sram[0]:5 mux_top_ipin_0\/mux_l1_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_8_sram[0]:19 mux_tree_tapbuf_size10_8_sram[0]:18 0.000640625 +9 mux_tree_tapbuf_size10_8_sram[0]:20 mux_tree_tapbuf_size10_8_sram[0]:19 0.0045 +10 mux_tree_tapbuf_size10_8_sram[0]:20 mux_tree_tapbuf_size10_8_sram[0]:17 0.0008214287 +11 mux_tree_tapbuf_size10_8_sram[0]:18 mux_top_ipin_0\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size10_8_sram[0]:10 mux_tree_tapbuf_size10_8_sram[0]:9 0.0045 +13 mux_tree_tapbuf_size10_8_sram[0]:10 mux_tree_tapbuf_size10_8_sram[0]:5 0.001109375 +14 mux_tree_tapbuf_size10_8_sram[0]:9 mux_tree_tapbuf_size10_8_sram[0]:8 0.003866071 +15 mux_tree_tapbuf_size10_8_sram[0]:7 mux_tree_tapbuf_size10_8_sram[0]:6 0.001823661 +16 mux_tree_tapbuf_size10_8_sram[0]:8 mux_tree_tapbuf_size10_8_sram[0]:7 0.0045 +17 mux_tree_tapbuf_size10_8_sram[0]:6 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size10_8_sram[0]:22 mux_tree_tapbuf_size10_8_sram[0]:21 0.0045 +19 mux_tree_tapbuf_size10_8_sram[0]:21 mux_tree_tapbuf_size10_8_sram[0]:20 0.01665625 +20 mux_tree_tapbuf_size10_8_sram[0]:23 mux_tree_tapbuf_size10_8_sram[0]:22 0.0008861608 +21 mux_tree_tapbuf_size10_8_sram[0]:11 mux_tree_tapbuf_size10_8_sram[0]:10 0.0002767857 +22 mux_tree_tapbuf_size10_8_sram[0]:17 mux_tree_tapbuf_size10_8_sram[0]:16 0.004857143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_4_ccff_tail[0] 0.0009996176 //LENGTH 6.715 LUMPCC 0.0003278152 DR + +*CONN +*I mem_bottom_ipin_8\/FTB_5__44:X O *L 0 *C 10.800 42.915 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 11.215 47.940 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 *C 11.215 47.940 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 *C 11.500 47.940 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 *C 11.500 47.895 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 *C 11.500 42.885 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 *C 11.455 42.840 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 *C 10.800 42.915 + +*CAP +0 mem_bottom_ipin_8\/FTB_5__44:X 1e-06 +1 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 5.045482e-05 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 5.636377e-05 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0001812495 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0001812495 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 7.318469e-05 +7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.0001273003 +8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 prog_clk[0]:280 0.0001208904 +9 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 prog_clk[0]:276 0.0001208904 +10 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 4.30172e-05 +11 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 4.30172e-05 + +*RES +0 mem_bottom_ipin_8\/FTB_5__44:X mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.004473215 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.0005848214 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[3] 0.002365548 //LENGTH 18.530 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 49.065 42.500 +*I mux_bottom_ipin_3\/mux_l4_in_0_:S I *L 0.00357 *C 41.960 51.000 +*I mem_bottom_ipin_3\/FTB_11__50:A I *L 0.001746 *C 49.220 44.880 +*N mux_tree_tapbuf_size8_1_sram[3]:3 *C 49.220 44.880 +*N mux_tree_tapbuf_size8_1_sram[3]:4 *C 49.220 44.540 +*N mux_tree_tapbuf_size8_1_sram[3]:5 *C 41.998 51.000 +*N mux_tree_tapbuf_size8_1_sram[3]:6 *C 45.495 51.000 +*N mux_tree_tapbuf_size8_1_sram[3]:7 *C 45.540 50.955 +*N mux_tree_tapbuf_size8_1_sram[3]:8 *C 45.540 44.585 +*N mux_tree_tapbuf_size8_1_sram[3]:9 *C 45.585 44.540 +*N mux_tree_tapbuf_size8_1_sram[3]:10 *C 48.300 44.540 +*N mux_tree_tapbuf_size8_1_sram[3]:11 *C 48.300 44.495 +*N mux_tree_tapbuf_size8_1_sram[3]:12 *C 48.300 42.545 +*N mux_tree_tapbuf_size8_1_sram[3]:13 *C 48.345 42.500 +*N mux_tree_tapbuf_size8_1_sram[3]:14 *C 49.028 42.500 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_3\/FTB_11__50:A 1e-06 +3 mux_tree_tapbuf_size8_1_sram[3]:3 5.503171e-05 +4 mux_tree_tapbuf_size8_1_sram[3]:4 8.332525e-05 +5 mux_tree_tapbuf_size8_1_sram[3]:5 0.0003205521 +6 mux_tree_tapbuf_size8_1_sram[3]:6 0.0003205521 +7 mux_tree_tapbuf_size8_1_sram[3]:7 0.0003942738 +8 mux_tree_tapbuf_size8_1_sram[3]:8 0.0003942738 +9 mux_tree_tapbuf_size8_1_sram[3]:9 0.000165058 +10 mux_tree_tapbuf_size8_1_sram[3]:10 0.000251909 +11 mux_tree_tapbuf_size8_1_sram[3]:11 0.000127138 +12 mux_tree_tapbuf_size8_1_sram[3]:12 0.000127138 +13 mux_tree_tapbuf_size8_1_sram[3]:13 6.1648e-05 +14 mux_tree_tapbuf_size8_1_sram[3]:14 6.1648e-05 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_1_sram[3]:14 0.152 +1 mux_tree_tapbuf_size8_1_sram[3]:9 mux_tree_tapbuf_size8_1_sram[3]:8 0.0045 +2 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:7 0.0056875 +3 mux_tree_tapbuf_size8_1_sram[3]:6 mux_tree_tapbuf_size8_1_sram[3]:5 0.003122768 +4 mux_tree_tapbuf_size8_1_sram[3]:7 mux_tree_tapbuf_size8_1_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size8_1_sram[3]:5 mux_bottom_ipin_3\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_1_sram[3]:10 mux_tree_tapbuf_size8_1_sram[3]:9 0.002424107 +7 mux_tree_tapbuf_size8_1_sram[3]:10 mux_tree_tapbuf_size8_1_sram[3]:4 0.0008214285 +8 mux_tree_tapbuf_size8_1_sram[3]:11 mux_tree_tapbuf_size8_1_sram[3]:10 0.0045 +9 mux_tree_tapbuf_size8_1_sram[3]:13 mux_tree_tapbuf_size8_1_sram[3]:12 0.0045 +10 mux_tree_tapbuf_size8_1_sram[3]:12 mux_tree_tapbuf_size8_1_sram[3]:11 0.001741072 +11 mux_tree_tapbuf_size8_1_sram[3]:14 mux_tree_tapbuf_size8_1_sram[3]:13 0.000609375 +12 mux_tree_tapbuf_size8_1_sram[3]:3 mem_bottom_ipin_3\/FTB_11__50:A 0.152 +13 mux_tree_tapbuf_size8_1_sram[3]:4 mux_tree_tapbuf_size8_1_sram[3]:3 0.0003035714 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[2] 0.004107119 //LENGTH 32.270 LUMPCC 0.0006347496 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 34.805 66.640 +*I mux_bottom_ipin_7\/mux_l3_in_0_:S I *L 0.00357 *C 28.620 61.495 +*I mux_bottom_ipin_7\/mux_l3_in_1_:S I *L 0.00357 *C 25.660 58.480 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 20.875 69.700 +*N mux_tree_tapbuf_size8_3_sram[2]:4 *C 28.620 61.570 +*N mux_tree_tapbuf_size8_3_sram[2]:5 *C 20.875 69.700 +*N mux_tree_tapbuf_size8_3_sram[2]:6 *C 21.160 69.700 +*N mux_tree_tapbuf_size8_3_sram[2]:7 *C 21.160 69.655 +*N mux_tree_tapbuf_size8_3_sram[2]:8 *C 21.160 61.245 +*N mux_tree_tapbuf_size8_3_sram[2]:9 *C 21.205 61.200 +*N mux_tree_tapbuf_size8_3_sram[2]:10 *C 25.660 58.480 +*N mux_tree_tapbuf_size8_3_sram[2]:11 *C 25.760 58.525 +*N mux_tree_tapbuf_size8_3_sram[2]:12 *C 25.760 61.155 +*N mux_tree_tapbuf_size8_3_sram[2]:13 *C 25.760 61.200 +*N mux_tree_tapbuf_size8_3_sram[2]:14 *C 28.562 61.200 +*N mux_tree_tapbuf_size8_3_sram[2]:15 *C 28.620 61.495 +*N mux_tree_tapbuf_size8_3_sram[2]:16 *C 28.620 61.880 +*N mux_tree_tapbuf_size8_3_sram[2]:17 *C 34.455 61.880 +*N mux_tree_tapbuf_size8_3_sram[2]:18 *C 34.500 61.925 +*N mux_tree_tapbuf_size8_3_sram[2]:19 *C 34.500 66.595 +*N mux_tree_tapbuf_size8_3_sram[2]:20 *C 34.500 66.640 +*N mux_tree_tapbuf_size8_3_sram[2]:21 *C 34.805 66.640 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_7\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_3_sram[2]:4 1.401325e-05 +5 mux_tree_tapbuf_size8_3_sram[2]:5 5.330634e-05 +6 mux_tree_tapbuf_size8_3_sram[2]:6 5.651142e-05 +7 mux_tree_tapbuf_size8_3_sram[2]:7 0.0003761298 +8 mux_tree_tapbuf_size8_3_sram[2]:8 0.0003761298 +9 mux_tree_tapbuf_size8_3_sram[2]:9 0.0002765735 +10 mux_tree_tapbuf_size8_3_sram[2]:10 2.881454e-05 +11 mux_tree_tapbuf_size8_3_sram[2]:11 0.0001276535 +12 mux_tree_tapbuf_size8_3_sram[2]:12 0.0001276535 +13 mux_tree_tapbuf_size8_3_sram[2]:13 0.000432202 +14 mux_tree_tapbuf_size8_3_sram[2]:14 0.0001421578 +15 mux_tree_tapbuf_size8_3_sram[2]:15 8.350582e-05 +16 mux_tree_tapbuf_size8_3_sram[2]:16 0.0003665042 +17 mux_tree_tapbuf_size8_3_sram[2]:17 0.0003466276 +18 mux_tree_tapbuf_size8_3_sram[2]:18 0.0002735584 +19 mux_tree_tapbuf_size8_3_sram[2]:19 0.0002735584 +20 mux_tree_tapbuf_size8_3_sram[2]:20 5.877339e-05 +21 mux_tree_tapbuf_size8_3_sram[2]:21 5.469572e-05 +22 mux_tree_tapbuf_size8_3_sram[2]:17 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.56023e-05 +23 mux_tree_tapbuf_size8_3_sram[2]:16 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.56023e-05 +24 mux_tree_tapbuf_size8_3_sram[2]:11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.470008e-05 +25 mux_tree_tapbuf_size8_3_sram[2]:13 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.015444e-05 +26 mux_tree_tapbuf_size8_3_sram[2]:13 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.315312e-05 +27 mux_tree_tapbuf_size8_3_sram[2]:12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.470008e-05 +28 mux_tree_tapbuf_size8_3_sram[2]:9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.315312e-05 +29 mux_tree_tapbuf_size8_3_sram[2]:14 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.015444e-05 +30 mux_tree_tapbuf_size8_3_sram[2]:11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.065068e-05 +31 mux_tree_tapbuf_size8_3_sram[2]:12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.065068e-05 +32 mux_tree_tapbuf_size8_3_sram[2]:8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.311419e-05 +33 mux_tree_tapbuf_size8_3_sram[2]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.311419e-05 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_3_sram[2]:21 0.152 +1 mux_tree_tapbuf_size8_3_sram[2]:10 mux_bottom_ipin_7\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_3_sram[2]:11 mux_tree_tapbuf_size8_3_sram[2]:10 0.0045 +3 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:12 0.0045 +4 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:9 0.004066965 +5 mux_tree_tapbuf_size8_3_sram[2]:12 mux_tree_tapbuf_size8_3_sram[2]:11 0.002348214 +6 mux_tree_tapbuf_size8_3_sram[2]:9 mux_tree_tapbuf_size8_3_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size8_3_sram[2]:8 mux_tree_tapbuf_size8_3_sram[2]:7 0.007508929 +8 mux_tree_tapbuf_size8_3_sram[2]:6 mux_tree_tapbuf_size8_3_sram[2]:5 0.0001548913 +9 mux_tree_tapbuf_size8_3_sram[2]:7 mux_tree_tapbuf_size8_3_sram[2]:6 0.0045 +10 mux_tree_tapbuf_size8_3_sram[2]:5 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size8_3_sram[2]:15 mux_bottom_ipin_7\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size8_3_sram[2]:15 mux_tree_tapbuf_size8_3_sram[2]:14 0.0001715116 +13 mux_tree_tapbuf_size8_3_sram[2]:15 mux_tree_tapbuf_size8_3_sram[2]:4 4.360465e-05 +14 mux_tree_tapbuf_size8_3_sram[2]:17 mux_tree_tapbuf_size8_3_sram[2]:16 0.005209822 +15 mux_tree_tapbuf_size8_3_sram[2]:18 mux_tree_tapbuf_size8_3_sram[2]:17 0.0045 +16 mux_tree_tapbuf_size8_3_sram[2]:20 mux_tree_tapbuf_size8_3_sram[2]:19 0.0045 +17 mux_tree_tapbuf_size8_3_sram[2]:19 mux_tree_tapbuf_size8_3_sram[2]:18 0.004169643 +18 mux_tree_tapbuf_size8_3_sram[2]:21 mux_tree_tapbuf_size8_3_sram[2]:20 0.0001657609 +19 mux_tree_tapbuf_size8_3_sram[2]:14 mux_tree_tapbuf_size8_3_sram[2]:13 0.002502232 +20 mux_tree_tapbuf_size8_3_sram[2]:16 mux_tree_tapbuf_size8_3_sram[2]:15 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[0] 0.001920963 //LENGTH 16.760 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 26.525 37.060 +*I mux_bottom_ipin_11\/mux_l1_in_0_:S I *L 0.00357 *C 21.520 46.920 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 20.875 44.540 +*N mux_tree_tapbuf_size8_5_sram[0]:3 *C 20.913 44.540 +*N mux_tree_tapbuf_size8_5_sram[0]:4 *C 21.520 46.920 +*N mux_tree_tapbuf_size8_5_sram[0]:5 *C 21.620 46.875 +*N mux_tree_tapbuf_size8_5_sram[0]:6 *C 21.620 44.585 +*N mux_tree_tapbuf_size8_5_sram[0]:7 *C 21.620 44.540 +*N mux_tree_tapbuf_size8_5_sram[0]:8 *C 22.955 44.540 +*N mux_tree_tapbuf_size8_5_sram[0]:9 *C 23.000 44.495 +*N mux_tree_tapbuf_size8_5_sram[0]:10 *C 23.000 37.105 +*N mux_tree_tapbuf_size8_5_sram[0]:11 *C 23.045 37.060 +*N mux_tree_tapbuf_size8_5_sram[0]:12 *C 26.488 37.060 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_11\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_5_sram[0]:3 6.41771e-05 +4 mux_tree_tapbuf_size8_5_sram[0]:4 2.900547e-05 +5 mux_tree_tapbuf_size8_5_sram[0]:5 0.0001487137 +6 mux_tree_tapbuf_size8_5_sram[0]:6 0.0001487137 +7 mux_tree_tapbuf_size8_5_sram[0]:7 0.0002055093 +8 mux_tree_tapbuf_size8_5_sram[0]:8 0.0001111125 +9 mux_tree_tapbuf_size8_5_sram[0]:9 0.0003968797 +10 mux_tree_tapbuf_size8_5_sram[0]:10 0.0003968797 +11 mux_tree_tapbuf_size8_5_sram[0]:11 0.0002084859 +12 mux_tree_tapbuf_size8_5_sram[0]:12 0.0002084859 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_5_sram[0]:12 0.152 +1 mux_tree_tapbuf_size8_5_sram[0]:7 mux_tree_tapbuf_size8_5_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size8_5_sram[0]:7 mux_tree_tapbuf_size8_5_sram[0]:3 0.0006316965 +3 mux_tree_tapbuf_size8_5_sram[0]:6 mux_tree_tapbuf_size8_5_sram[0]:5 0.002044643 +4 mux_tree_tapbuf_size8_5_sram[0]:4 mux_bottom_ipin_11\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_5_sram[0]:5 mux_tree_tapbuf_size8_5_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size8_5_sram[0]:3 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size8_5_sram[0]:8 mux_tree_tapbuf_size8_5_sram[0]:7 0.001191964 +8 mux_tree_tapbuf_size8_5_sram[0]:9 mux_tree_tapbuf_size8_5_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size8_5_sram[0]:11 mux_tree_tapbuf_size8_5_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size8_5_sram[0]:10 mux_tree_tapbuf_size8_5_sram[0]:9 0.006598215 +11 mux_tree_tapbuf_size8_5_sram[0]:12 mux_tree_tapbuf_size8_5_sram[0]:11 0.003073661 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[3] 0.001828745 //LENGTH 15.570 LUMPCC 0.000249923 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 78.045 34.000 +*I mem_bottom_ipin_14\/FTB_16__55:A I *L 0.001746 *C 76.360 42.160 +*I mux_bottom_ipin_14\/mux_l4_in_0_:S I *L 0.00357 *C 77.380 31.280 +*N mux_tree_tapbuf_size8_6_sram[3]:3 *C 77.395 31.280 +*N mux_tree_tapbuf_size8_6_sram[3]:4 *C 77.718 31.280 +*N mux_tree_tapbuf_size8_6_sram[3]:5 *C 77.740 31.325 +*N mux_tree_tapbuf_size8_6_sram[3]:6 *C 76.398 42.160 +*N mux_tree_tapbuf_size8_6_sram[3]:7 *C 77.235 42.160 +*N mux_tree_tapbuf_size8_6_sram[3]:8 *C 77.280 42.115 +*N mux_tree_tapbuf_size8_6_sram[3]:9 *C 77.280 32.640 +*N mux_tree_tapbuf_size8_6_sram[3]:10 *C 77.740 32.640 +*N mux_tree_tapbuf_size8_6_sram[3]:11 *C 77.740 33.955 +*N mux_tree_tapbuf_size8_6_sram[3]:12 *C 77.740 34.000 +*N mux_tree_tapbuf_size8_6_sram[3]:13 *C 78.045 34.000 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_14\/FTB_16__55:A 1e-06 +2 mux_bottom_ipin_14\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_6_sram[3]:3 5.066113e-05 +4 mux_tree_tapbuf_size8_6_sram[3]:4 5.066113e-05 +5 mux_tree_tapbuf_size8_6_sram[3]:5 0.0001021167 +6 mux_tree_tapbuf_size8_6_sram[3]:6 8.788005e-05 +7 mux_tree_tapbuf_size8_6_sram[3]:7 8.788005e-05 +8 mux_tree_tapbuf_size8_6_sram[3]:8 0.0003655719 +9 mux_tree_tapbuf_size8_6_sram[3]:9 0.0003938789 +10 mux_tree_tapbuf_size8_6_sram[3]:10 0.0002301368 +11 mux_tree_tapbuf_size8_6_sram[3]:11 9.971309e-05 +12 mux_tree_tapbuf_size8_6_sram[3]:12 5.483823e-05 +13 mux_tree_tapbuf_size8_6_sram[3]:13 5.248348e-05 +14 mux_tree_tapbuf_size8_6_sram[3]:5 chanx_left_in[0]:30 8.346643e-07 +15 mux_tree_tapbuf_size8_6_sram[3]:8 chanx_left_in[0]:22 0.0001231357 +16 mux_tree_tapbuf_size8_6_sram[3]:11 chanx_left_in[0]:22 9.911638e-07 +17 mux_tree_tapbuf_size8_6_sram[3]:9 chanx_left_in[0]:30 0.0001231357 +18 mux_tree_tapbuf_size8_6_sram[3]:10 chanx_left_in[0]:22 8.346643e-07 +19 mux_tree_tapbuf_size8_6_sram[3]:10 chanx_left_in[0]:30 9.911638e-07 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_6_sram[3]:13 0.152 +1 mux_tree_tapbuf_size8_6_sram[3]:4 mux_tree_tapbuf_size8_6_sram[3]:3 0.0001752718 +2 mux_tree_tapbuf_size8_6_sram[3]:5 mux_tree_tapbuf_size8_6_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size8_6_sram[3]:3 mux_bottom_ipin_14\/mux_l4_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_6_sram[3]:7 mux_tree_tapbuf_size8_6_sram[3]:6 0.0007477679 +5 mux_tree_tapbuf_size8_6_sram[3]:8 mux_tree_tapbuf_size8_6_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size8_6_sram[3]:6 mem_bottom_ipin_14\/FTB_16__55:A 0.152 +7 mux_tree_tapbuf_size8_6_sram[3]:12 mux_tree_tapbuf_size8_6_sram[3]:11 0.0045 +8 mux_tree_tapbuf_size8_6_sram[3]:11 mux_tree_tapbuf_size8_6_sram[3]:10 0.001174107 +9 mux_tree_tapbuf_size8_6_sram[3]:13 mux_tree_tapbuf_size8_6_sram[3]:12 0.0001657609 +10 mux_tree_tapbuf_size8_6_sram[3]:9 mux_tree_tapbuf_size8_6_sram[3]:8 0.008459821 +11 mux_tree_tapbuf_size8_6_sram[3]:10 mux_tree_tapbuf_size8_6_sram[3]:9 0.0004107143 +12 mux_tree_tapbuf_size8_6_sram[3]:10 mux_tree_tapbuf_size8_6_sram[3]:5 0.001174107 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_0_ccff_tail[0] 0.0008224685 //LENGTH 5.880 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/FTB_10__49:X O *L 0 *C 29.665 29.240 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 31.915 31.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 *C 31.915 31.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 *C 31.740 31.960 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 *C 29.945 31.960 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 *C 29.900 31.915 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 *C 29.900 29.285 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 *C 29.900 29.240 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:8 *C 29.665 29.240 + +*CAP +0 mem_bottom_ipin_2\/FTB_10__49:X 1e-06 +1 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 5.191312e-05 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.0001608585 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0001357253 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.000171878 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.000171878 +7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 6.459883e-05 +8 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:8 6.361672e-05 + +*RES +0 mem_bottom_ipin_2\/FTB_10__49:X mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.001602678 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0045 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.0045 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.002348214 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 0.0001277174 +7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_4_ccff_tail[0] 0.002727837 //LENGTH 23.220 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_10\/FTB_14__53:X O *L 0 *C 23.695 17.680 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 20.875 37.060 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 *C 20.875 37.060 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 *C 21.160 37.060 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 *C 21.160 37.015 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 *C 21.160 25.545 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 *C 21.205 25.500 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 *C 23.415 25.500 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:8 *C 23.460 25.455 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:9 *C 23.460 17.725 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:10 *C 23.460 17.680 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:11 *C 23.695 17.680 + +*CAP +0 mem_bottom_ipin_10\/FTB_14__53:X 1e-06 +1 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 4.778959e-05 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 5.186019e-05 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.0006453783 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0006453783 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 0.0001686128 +7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 0.0001686128 +8 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:8 0.0004383548 +9 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:9 0.0004383548 +10 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:10 6.196396e-05 +11 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:11 5.95311e-05 + +*RES +0 mem_bottom_ipin_10\/FTB_14__53:X mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.01024107 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 0.001973214 +7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 0.0045 +8 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:9 0.0045 +9 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:8 0.006901786 +10 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:10 0.0001277174 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00141458 //LENGTH 11.210 LUMPCC 0.0002701591 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_2_:X O *L 0 *C 90.335 23.800 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 88.685 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 88.723 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 91.035 30.940 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 91.080 30.895 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 91.080 23.845 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 91.035 23.800 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 90.373 23.800 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001676403 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001676403 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003194222 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003194222 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.414804e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.414804e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:149 2.032203e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:164 4.934539e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:78 2.032203e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:149 4.934539e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.541215e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.541215e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002064732 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.006294644 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006424026 //LENGTH 4.900 LUMPCC 0.0002218912 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_0_:X O *L 0 *C 85.735 33.660 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 84.085 36.380 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 84.085 36.380 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 84.180 36.335 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 84.180 33.705 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 84.225 33.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 85.698 33.660 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.726557e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001027888 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001027888 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 9.283409e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.283409e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:9 2.659851e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:13 6.294814e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:6 7.270788e-06 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:11 1.412815e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:8 2.659851e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:12 6.294814e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:5 7.270788e-06 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:10 1.412815e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002348214 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003071366 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_3_:X O *L 0 *C 49.855 60.860 +*I mux_bottom_ipin_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 47.670 60.860 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 47.708 60.860 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 49.818 60.860 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001525683 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001525683 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_3_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000385898 //LENGTH 2.650 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_0_:X O *L 0 *C 61.815 20.060 +*I mux_bottom_ipin_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 62.005 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 62.005 18.020 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 62.100 18.065 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 62.100 20.015 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 62.100 20.060 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 61.815 20.060 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.709402e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001264481 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001264481 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.046106e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.34468e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001741072 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009355814 //LENGTH 8.455 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_3_:X O *L 0 *C 68.715 15.300 +*I mux_bottom_ipin_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 60.550 15.300 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 60.588 15.300 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 68.678 15.300 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004667907 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0004667907 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_3_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.007223214 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001206207 //LENGTH 8.685 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_0_:X O *L 0 *C 63.195 53.720 +*I mux_bottom_ipin_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.325 56.100 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.325 56.100 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 58.420 56.440 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 62.975 56.440 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.020 56.395 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.020 53.765 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 63.020 53.720 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 63.195 53.720 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.143981e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003497983 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003195014 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001805464 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001805464 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.674789e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.562626e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004066965 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002348214 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.51087e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001660469 //LENGTH 12.540 LUMPCC 0.0006144129 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_1_:X O *L 0 *C 15.355 20.740 +*I mux_bottom_ipin_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 13.615 28.220 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 13.578 28.220 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 12.465 28.220 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 12.420 28.175 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 12.420 20.785 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 12.465 20.740 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 15.318 20.740 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001075814 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001075814 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003276561 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003276561 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.679053e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.679052e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[8]:20 5.227665e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[8]:21 5.227665e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[2]:24 8.914449e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[2]:25 2.817127e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[2]:18 2.817127e-05 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[2]:25 8.914449e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[12]:10 1.553655e-05 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[12]:20 1.795641e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[12]:11 2.112846e-05 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[12]:14 2.410969e-05 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[12]:19 1.795641e-05 +19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[12]:20 1.553655e-05 +20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[12]:12 2.112846e-05 +21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[12]:13 2.410969e-05 +22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:8 8.135381e-06 +23 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:11 2.439146e-05 +24 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:12 1.364072e-05 +25 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_4_sram[0]:6 3.189854e-06 +26 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_4_sram[0]:9 9.525577e-06 +27 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:7 8.135381e-06 +28 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:9 2.439146e-05 +29 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:11 1.364072e-05 +30 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_4_sram[0]:5 3.189854e-06 +31 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_4_sram[0]:8 9.525577e-06 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009933036 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006598215 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002546875 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00104513 //LENGTH 7.395 LUMPCC 0.0002762162 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_2_:X O *L 0 *C 16.845 51.000 +*I mux_bottom_ipin_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 15.640 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 15.678 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 16.975 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.020 56.055 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.020 51.045 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 17.020 51.000 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 16.845 51.000 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.076678e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.076678e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002642497 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002642497 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.821948e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.866101e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[1]:55 6.224702e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[1]:56 6.224702e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[0]:12 7.638842e-06 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[0]:13 1.80127e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[0]:17 5.208905e-07 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[0]:22 3.716828e-05 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_5_sram[0]:10 1.25204e-05 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[0]:7 7.638842e-06 +16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[0]:12 1.80127e-05 +17 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[0]:18 5.208905e-07 +18 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[0]:21 3.716828e-05 +19 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_5_sram[0]:11 1.25204e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_2_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004473214 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001158482 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008518702 //LENGTH 6.585 LUMPCC 0.0001650615 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_0_:X O *L 0 *C 54.565 29.240 +*I mux_bottom_ipin_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.520 30.940 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.483 30.940 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 56.625 30.940 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 56.580 30.895 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 56.580 29.285 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 56.535 29.240 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 54.602 29.240 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.250347e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.250347e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001117894 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001117894 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001481114 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001481114 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_6_sram[1]:20 8.253076e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_6_sram[1]:21 8.253076e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0007023081 //LENGTH 5.260 LUMPCC 0.0001093431 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l3_in_0_:X O *L 0 *C 65.145 34.680 +*I mux_bottom_ipin_12\/mux_l4_in_0_:A1 I *L 0.00198 *C 68.080 36.380 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 68.080 36.380 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 68.080 36.335 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 68.080 34.725 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 68.035 34.680 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 65.183 34.680 + +*CAP +0 mux_bottom_ipin_12\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.204889e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.661406e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.661406e-05 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000212844 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000212844 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.467157e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.467157e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l3_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002546875 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0014375 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_12\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006212868 //LENGTH 3.635 LUMPCC 0.0002875256 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l3_in_0_:X O *L 0 *C 72.395 61.880 +*I mux_bottom_ipin_13\/mux_l4_in_0_:A1 I *L 0.00198 *C 73.700 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 73.663 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 72.725 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 72.680 63.535 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 72.680 61.925 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 72.680 61.880 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 72.395 61.880 + +*CAP +0 mux_bottom_ipin_13\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.767331e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.767331e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.736102e-05 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.736102e-05 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.01883e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.15043e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_7_sram[2]:16 4.173036e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_7_sram[2]:15 4.173036e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_7_sram[2]:14 1.405738e-06 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_7_sram[2]:11 9.438174e-07 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_7_sram[2]:13 1.405738e-06 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_7_sram[2]:12 9.438174e-07 +14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_7_sram[3]:3 4.815042e-05 +15 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_7_sram[3]:4 4.815042e-05 +16 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 5.153244e-05 +17 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 5.153244e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l3_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_13\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0008370536 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0014375 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.000898976 //LENGTH 6.390 LUMPCC 0.0002674767 DR + +*CONN +*I mux_top_ipin_0\/mux_l3_in_0_:X O *L 0 *C 87.575 14.960 +*I mux_top_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 87.860 9.180 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 87.860 9.180 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 87.860 9.225 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 87.860 14.915 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 87.860 14.960 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 87.575 14.960 + +*CAP +0 mux_top_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_top_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.438397e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002378122 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002378122 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.328705e-05 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.620393e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001337383 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001337383 + +*RES +0 mux_top_ipin_0\/mux_l3_in_0_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001548913 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.005080357 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_ipin_0\/mux_l4_in_0_:A1 0.152 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004233453 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l3_in_1_:X O *L 0 *C 33.405 21.080 +*I mux_bottom_ipin_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 33.410 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 33.410 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 33.580 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 33.580 22.395 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 33.580 21.125 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 33.580 21.080 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 33.405 21.080 + +*CAP +0 mux_bottom_ipin_2\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.314799e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.71051e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.660247e-05 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.660247e-05 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.041727e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.746999e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l3_in_1_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_2\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239132e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.004068457 //LENGTH 31.385 LUMPCC 0.0006141665 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l4_in_0_:X O *L 0 *C 41.115 50.660 +*I mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 41.945 69.510 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 41.945 69.510 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 41.860 69.020 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 35.925 69.020 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 35.880 68.975 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 35.880 51.045 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 35.925 51.000 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 39.560 51.000 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 39.560 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 41.078 50.660 + +*CAP +0 mux_bottom_ipin_3\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.380866e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0004089268 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003739858 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0008438618 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0008438618 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0003035119 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003291941 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001554109 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001297287 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_left_in[3]:49 0.0001039751 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_left_in[3]:54 1.317282e-06 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_left_in[3]:50 0.0001039751 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_left_in[3]:55 1.317282e-06 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:16 4.213748e-07 +16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:23 6.598185e-05 +17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:24 0.0001353876 +18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size8_3_sram[1]:15 4.213748e-07 +19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size8_3_sram[1]:20 0.0001353876 +20 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size8_3_sram[1]:24 6.598185e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l4_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.005299107 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.01600893 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.001354911 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.003245536 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004375 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008734342 //LENGTH 6.110 LUMPCC 0.000103884 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_1_:X O *L 0 *C 32.375 58.140 +*I mux_bottom_ipin_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 29.730 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 29.730 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 29.900 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 29.900 60.815 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 29.900 58.185 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 29.945 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 32.337 58.140 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.10621e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.65273e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001807894 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001807894 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001491909 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001491909 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[3]:36 5.194201e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[3]:37 5.194201e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_1_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.239132e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002136161 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000887866 //LENGTH 6.155 LUMPCC 9.624717e-05 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l3_in_1_:X O *L 0 *C 24.095 17.340 +*I mux_bottom_ipin_10\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.230 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 18.268 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 24.058 17.340 + +*CAP +0 mux_bottom_ipin_10\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003948094 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003948094 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_4_sram[3]:3 4.812359e-05 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_4_sram[3]:4 4.812359e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l3_in_1_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_10\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.005169643 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004236603 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_2_:X O *L 0 *C 35.135 47.260 +*I mux_bottom_ipin_11\/mux_l3_in_1_:A1 I *L 0.00198 *C 32.565 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 32.602 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 35.098 47.260 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002108301 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002108301 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_2_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003594976 //LENGTH 2.305 LUMPCC 0.0001685104 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_0_:X O *L 0 *C 75.265 23.460 +*I mux_bottom_ipin_14\/mux_l3_in_0_:A1 I *L 0.00198 *C 77.280 23.460 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 77.243 23.460 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 75.303 23.460 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.449359e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.449359e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_6_sram[1]:19 2.915131e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_6_sram[1]:20 5.51039e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_6_sram[1]:6 2.915131e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_6_sram[1]:19 5.51039e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001732143 + +*END + +*D_NET optlc_net_109 0.003708921 //LENGTH 29.745 LUMPCC 0 DR + +*CONN +*I optlc_112:HI O *L 0 *C 36.800 17.340 +*I mux_bottom_ipin_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 32.950 15.300 +*I mux_bottom_ipin_10\/mux_l2_in_3_:A0 I *L 0.001631 *C 25.015 11.560 +*I mux_bottom_ipin_6\/mux_l2_in_3_:A0 I *L 0.001631 *C 44.450 17.000 +*N optlc_net_109:4 *C 44.413 17.000 +*N optlc_net_109:5 *C 25.053 11.560 +*N optlc_net_109:6 *C 28.475 11.560 +*N optlc_net_109:7 *C 28.520 11.605 +*N optlc_net_109:8 *C 28.520 16.955 +*N optlc_net_109:9 *C 28.565 17.000 +*N optlc_net_109:10 *C 32.988 15.300 +*N optlc_net_109:11 *C 33.995 15.300 +*N optlc_net_109:12 *C 34.040 15.345 +*N optlc_net_109:13 *C 34.040 16.955 +*N optlc_net_109:14 *C 34.040 17.000 +*N optlc_net_109:15 *C 36.800 17.000 +*N optlc_net_109:16 *C 36.800 17.340 + +*CAP +0 optlc_112:HI 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_6\/mux_l2_in_3_:A0 1e-06 +4 optlc_net_109:4 0.0004981068 +5 optlc_net_109:5 0.0002368321 +6 optlc_net_109:6 0.0002368321 +7 optlc_net_109:7 0.000310875 +8 optlc_net_109:8 0.000310875 +9 optlc_net_109:9 0.0003724917 +10 optlc_net_109:10 9.029964e-05 +11 optlc_net_109:11 9.029964e-05 +12 optlc_net_109:12 0.0001129367 +13 optlc_net_109:13 0.0001129367 +14 optlc_net_109:14 0.0005791708 +15 optlc_net_109:15 0.000698155 +16 optlc_net_109:16 5.511004e-05 + +*RES +0 optlc_112:HI optlc_net_109:16 0.152 +1 optlc_net_109:9 optlc_net_109:8 0.0045 +2 optlc_net_109:8 optlc_net_109:7 0.004776786 +3 optlc_net_109:6 optlc_net_109:5 0.003055804 +4 optlc_net_109:7 optlc_net_109:6 0.0045 +5 optlc_net_109:5 mux_bottom_ipin_10\/mux_l2_in_3_:A0 0.152 +6 optlc_net_109:14 optlc_net_109:13 0.0045 +7 optlc_net_109:14 optlc_net_109:9 0.004888393 +8 optlc_net_109:13 optlc_net_109:12 0.0014375 +9 optlc_net_109:11 optlc_net_109:10 0.0008995536 +10 optlc_net_109:12 optlc_net_109:11 0.0045 +11 optlc_net_109:10 mux_bottom_ipin_2\/mux_l2_in_3_:A0 0.152 +12 optlc_net_109:16 optlc_net_109:15 0.0003035715 +13 optlc_net_109:4 mux_bottom_ipin_6\/mux_l2_in_3_:A0 0.152 +14 optlc_net_109:15 optlc_net_109:14 0.002464286 +15 optlc_net_109:15 optlc_net_109:4 0.006796875 + +*END + +*D_NET ropt_net_167 0.0004632864 //LENGTH 3.510 LUMPCC 0.0001255725 DR + +*CONN +*I ropt_mt_inst_709:X O *L 0 *C 8.740 31.280 +*I ropt_mt_inst_776:A I *L 0.001766 *C 11.960 31.280 +*N ropt_net_167:2 *C 11.923 31.280 +*N ropt_net_167:3 *C 8.777 31.280 + +*CAP +0 ropt_mt_inst_709:X 1e-06 +1 ropt_mt_inst_776:A 1e-06 +2 ropt_net_167:2 0.0001678569 +3 ropt_net_167:3 0.0001678569 +4 ropt_net_167:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.278626e-05 +5 ropt_net_167:2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.278626e-05 + +*RES +0 ropt_mt_inst_709:X ropt_net_167:3 0.152 +1 ropt_net_167:3 ropt_net_167:2 0.002808036 +2 ropt_net_167:2 ropt_mt_inst_776:A 0.152 + +*END + +*D_NET ropt_net_139 0.0008769758 //LENGTH 7.795 LUMPCC 0 DR + +*CONN +*I FTB_19__18:X O *L 0 *C 94.300 9.180 +*I ropt_mt_inst_738:A I *L 0.001766 *C 97.825 12.240 +*N ropt_net_139:2 *C 97.788 12.240 +*N ropt_net_139:3 *C 96.645 12.240 +*N ropt_net_139:4 *C 96.600 12.195 +*N ropt_net_139:5 *C 96.600 9.565 +*N ropt_net_139:6 *C 96.555 9.520 +*N ropt_net_139:7 *C 95.220 9.520 +*N ropt_net_139:8 *C 95.220 9.180 +*N ropt_net_139:9 *C 94.338 9.180 + +*CAP +0 FTB_19__18:X 1e-06 +1 ropt_mt_inst_738:A 1e-06 +2 ropt_net_139:2 9.555383e-05 +3 ropt_net_139:3 9.555383e-05 +4 ropt_net_139:4 0.0001506659 +5 ropt_net_139:5 0.0001506659 +6 ropt_net_139:6 9.405956e-05 +7 ropt_net_139:7 0.0001172921 +8 ropt_net_139:8 9.720866e-05 +9 ropt_net_139:9 7.397608e-05 + +*RES +0 FTB_19__18:X ropt_net_139:9 0.152 +1 ropt_net_139:9 ropt_net_139:8 0.0007879465 +2 ropt_net_139:6 ropt_net_139:5 0.0045 +3 ropt_net_139:5 ropt_net_139:4 0.002348214 +4 ropt_net_139:3 ropt_net_139:2 0.001020089 +5 ropt_net_139:4 ropt_net_139:3 0.0045 +6 ropt_net_139:2 ropt_mt_inst_738:A 0.152 +7 ropt_net_139:8 ropt_net_139:7 0.0003035715 +8 ropt_net_139:7 ropt_net_139:6 0.001191964 + +*END + +*D_NET ropt_net_169 0.0014885 //LENGTH 12.090 LUMPCC 0.0004521108 DR + +*CONN +*I ropt_mt_inst_720:X O *L 0 *C 94.300 45.560 +*I ropt_mt_inst_781:A I *L 0.001766 *C 97.980 53.040 +*N ropt_net_169:2 *C 97.943 53.040 +*N ropt_net_169:3 *C 97.565 53.040 +*N ropt_net_169:4 *C 97.520 52.995 +*N ropt_net_169:5 *C 97.520 45.605 +*N ropt_net_169:6 *C 97.475 45.560 +*N ropt_net_169:7 *C 94.338 45.560 + +*CAP +0 ropt_mt_inst_720:X 1e-06 +1 ropt_mt_inst_781:A 1e-06 +2 ropt_net_169:2 5.687941e-05 +3 ropt_net_169:3 5.687941e-05 +4 ropt_net_169:4 0.0002318986 +5 ropt_net_169:5 0.0002318986 +6 ropt_net_169:6 0.0002284167 +7 ropt_net_169:7 0.0002284167 +8 ropt_net_169:4 chanx_left_in[13]:7 5.82274e-05 +9 ropt_net_169:5 chanx_left_in[13]:6 5.82274e-05 +10 ropt_net_169:4 ccff_head[0]:5 9.832104e-05 +11 ropt_net_169:5 ccff_head[0]:4 9.832104e-05 +12 ropt_net_169:4 mux_tree_tapbuf_size10_8_sram[0]:21 6.950697e-05 +13 ropt_net_169:5 mux_tree_tapbuf_size10_8_sram[0]:20 6.950697e-05 + +*RES +0 ropt_mt_inst_720:X ropt_net_169:7 0.152 +1 ropt_net_169:2 ropt_mt_inst_781:A 0.152 +2 ropt_net_169:3 ropt_net_169:2 0.0003370536 +3 ropt_net_169:4 ropt_net_169:3 0.0045 +4 ropt_net_169:6 ropt_net_169:5 0.0045 +5 ropt_net_169:5 ropt_net_169:4 0.006598215 +6 ropt_net_169:7 ropt_net_169:6 0.00280134 + +*END + +*D_NET chanx_right_out[17] 0.001168281 //LENGTH 11.190 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 94.300 3.400 +*P chanx_right_out[17] O *L 0.7423 *C 102.580 1.290 +*N chanx_right_out[17]:2 *C 102.580 1.655 +*N chanx_right_out[17]:3 *C 102.535 1.700 +*N chanx_right_out[17]:4 *C 94.345 1.700 +*N chanx_right_out[17]:5 *C 94.300 1.745 +*N chanx_right_out[17]:6 *C 94.300 3.355 +*N chanx_right_out[17]:7 *C 94.300 3.400 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 chanx_right_out[17] 3.241225e-05 +2 chanx_right_out[17]:2 3.241225e-05 +3 chanx_right_out[17]:3 0.0004446122 +4 chanx_right_out[17]:4 0.0004446122 +5 chanx_right_out[17]:5 9.194193e-05 +6 chanx_right_out[17]:6 9.194193e-05 +7 chanx_right_out[17]:7 2.934847e-05 + +*RES +0 ropt_mt_inst_752:X chanx_right_out[17]:7 0.152 +1 chanx_right_out[17]:7 chanx_right_out[17]:6 0.0045 +2 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0014375 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.0073125 +4 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +5 chanx_right_out[17]:3 chanx_right_out[17]:2 0.0045 +6 chanx_right_out[17]:2 chanx_right_out[17] 0.0003258929 + +*END + +*D_NET chanx_left_out[13] 0.002051498 //LENGTH 14.110 LUMPCC 0.0001079471 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 7.095 50.660 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 44.880 +*N chanx_left_out[13]:2 *C 1.820 44.880 +*N chanx_left_out[13]:3 *C 1.848 44.880 +*N chanx_left_out[13]:4 *C 2.760 44.880 +*N chanx_left_out[13]:5 *C 2.760 48.273 +*N chanx_left_out[13]:6 *C 2.780 48.280 +*N chanx_left_out[13]:7 *C 4.133 48.280 +*N chanx_left_out[13]:8 *C 4.140 48.338 +*N chanx_left_out[13]:9 *C 4.140 49.595 +*N chanx_left_out[13]:10 *C 4.185 49.640 +*N chanx_left_out[13]:11 *C 6.395 49.640 +*N chanx_left_out[13]:12 *C 6.440 49.685 +*N chanx_left_out[13]:13 *C 6.440 50.615 +*N chanx_left_out[13]:14 *C 6.485 50.660 +*N chanx_left_out[13]:15 *C 7.058 50.660 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 chanx_left_out[13] 8.116739e-05 +2 chanx_left_out[13]:2 8.116739e-05 +3 chanx_left_out[13]:3 7.148828e-05 +4 chanx_left_out[13]:4 0.0003182251 +5 chanx_left_out[13]:5 0.0002467368 +6 chanx_left_out[13]:6 0.0001570166 +7 chanx_left_out[13]:7 0.0001570166 +8 chanx_left_out[13]:8 0.0001095452 +9 chanx_left_out[13]:9 0.0001095452 +10 chanx_left_out[13]:10 0.0001837088 +11 chanx_left_out[13]:11 0.0001837088 +12 chanx_left_out[13]:12 7.998085e-05 +13 chanx_left_out[13]:13 7.998085e-05 +14 chanx_left_out[13]:14 4.163145e-05 +15 chanx_left_out[13]:15 4.163145e-05 +16 chanx_left_out[13]:15 ropt_net_155:5 8.080156e-06 +17 chanx_left_out[13]:15 ropt_net_155:2 3.108245e-05 +18 chanx_left_out[13]:14 ropt_net_155:4 8.080156e-06 +19 chanx_left_out[13]:14 ropt_net_155:3 3.108245e-05 +20 chanx_left_out[13]:13 ropt_net_155:3 5.169686e-06 +21 chanx_left_out[13]:11 ropt_net_155:5 8.217198e-06 +22 chanx_left_out[13]:11 ropt_net_155:2 1.424089e-06 +23 chanx_left_out[13]:12 ropt_net_155:4 5.169686e-06 +24 chanx_left_out[13]:10 ropt_net_155:4 8.217198e-06 +25 chanx_left_out[13]:10 ropt_net_155:3 1.424089e-06 + +*RES +0 ropt_mt_inst_760:X chanx_left_out[13]:15 0.152 +1 chanx_left_out[13]:15 chanx_left_out[13]:14 0.0005111608 +2 chanx_left_out[13]:14 chanx_left_out[13]:13 0.0045 +3 chanx_left_out[13]:13 chanx_left_out[13]:12 0.0008303572 +4 chanx_left_out[13]:11 chanx_left_out[13]:10 0.001973214 +5 chanx_left_out[13]:12 chanx_left_out[13]:11 0.0045 +6 chanx_left_out[13]:10 chanx_left_out[13]:9 0.0045 +7 chanx_left_out[13]:9 chanx_left_out[13]:8 0.001122768 +8 chanx_left_out[13]:8 chanx_left_out[13]:7 0.00341 +9 chanx_left_out[13]:7 chanx_left_out[13]:6 0.0002118916 +10 chanx_left_out[13]:6 chanx_left_out[13]:5 0.00341 +11 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0005314916 +12 chanx_left_out[13]:2 chanx_left_out[13] 9.243333e-05 +13 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +14 chanx_left_out[13]:4 chanx_left_out[13]:3 0.0001429583 + +*END + +*D_NET chanx_right_out[18] 0.00105338 //LENGTH 8.450 LUMPCC 0.0001217413 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 101.855 11.560 +*P chanx_right_out[18] O *L 0.7423 *C 103.650 5.440 +*N chanx_right_out[18]:2 *C 102.128 5.440 +*N chanx_right_out[18]:3 *C 102.120 5.498 +*N chanx_right_out[18]:4 *C 102.120 11.515 +*N chanx_right_out[18]:5 *C 102.120 11.560 +*N chanx_right_out[18]:6 *C 101.855 11.560 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 chanx_right_out[18] 0.0001180417 +2 chanx_right_out[18]:2 0.0001180417 +3 chanx_right_out[18]:3 0.0002940287 +4 chanx_right_out[18]:4 0.0002940287 +5 chanx_right_out[18]:5 5.000452e-05 +6 chanx_right_out[18]:6 5.649291e-05 +7 chanx_right_out[18]:4 ropt_net_164:5 6.087067e-05 +8 chanx_right_out[18]:3 ropt_net_164:4 6.087067e-05 + +*RES +0 ropt_mt_inst_738:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0001440218 +2 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.005372768 +4 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +5 chanx_right_out[18]:2 chanx_right_out[18] 0.000238525 + +*END + +*D_NET ropt_net_163 0.001347353 //LENGTH 10.155 LUMPCC 0.0004275244 DR + +*CONN +*I ropt_mt_inst_741:X O *L 0 *C 7.095 39.780 +*I ropt_mt_inst_769:A I *L 0.001767 *C 3.220 44.880 +*N ropt_net_163:2 *C 3.258 44.880 +*N ropt_net_163:3 *C 7.315 44.880 +*N ropt_net_163:4 *C 7.360 44.835 +*N ropt_net_163:5 *C 7.360 39.825 +*N ropt_net_163:6 *C 7.360 39.780 +*N ropt_net_163:7 *C 7.095 39.780 + +*CAP +0 ropt_mt_inst_741:X 1e-06 +1 ropt_mt_inst_769:A 1e-06 +2 ropt_net_163:2 0.0001813138 +3 ropt_net_163:3 0.0001813138 +4 ropt_net_163:4 0.0002154292 +5 ropt_net_163:5 0.0002154292 +6 ropt_net_163:6 6.059914e-05 +7 ropt_net_163:7 6.374386e-05 +8 ropt_net_163:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 6.934226e-05 +9 ropt_net_163:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 6.934226e-05 +10 ropt_net_163:2 optlc_net_107:10 0.0001272755 +11 ropt_net_163:3 optlc_net_107:11 0.0001272755 +12 ropt_net_163:4 optlc_net_107:13 1.714439e-05 +13 ropt_net_163:5 optlc_net_107:12 1.714439e-05 + +*RES +0 ropt_mt_inst_741:X ropt_net_163:7 0.152 +1 ropt_net_163:2 ropt_mt_inst_769:A 0.152 +2 ropt_net_163:3 ropt_net_163:2 0.003622768 +3 ropt_net_163:4 ropt_net_163:3 0.0045 +4 ropt_net_163:6 ropt_net_163:5 0.0045 +5 ropt_net_163:5 ropt_net_163:4 0.004473215 +6 ropt_net_163:7 ropt_net_163:6 0.0001440218 + +*END + +*D_NET chanx_right_out[15] 0.0003255138 //LENGTH 2.265 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 101.855 42.160 +*P chanx_right_out[15] O *L 0.7423 *C 103.650 42.160 +*N chanx_right_out[15]:2 *C 102.588 42.160 +*N chanx_right_out[15]:3 *C 102.580 42.160 +*N chanx_right_out[15]:4 *C 102.535 42.160 +*N chanx_right_out[15]:5 *C 101.892 42.160 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 chanx_right_out[15] 9.193536e-05 +2 chanx_right_out[15]:2 9.193536e-05 +3 chanx_right_out[15]:3 3.384663e-05 +4 chanx_right_out[15]:4 5.339822e-05 +5 chanx_right_out[15]:5 5.339822e-05 + +*RES +0 ropt_mt_inst_744:X chanx_right_out[15]:5 0.152 +1 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0005736608 +2 chanx_right_out[15]:4 chanx_right_out[15]:3 0.0045 +3 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +4 chanx_right_out[15]:2 chanx_right_out[15] 0.0001664583 + +*END + +*D_NET chanx_left_in[9] 0.01922858 //LENGTH 132.925 LUMPCC 0.005348112 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 40.800 +*I mux_bottom_ipin_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 15.180 50.660 +*I mux_bottom_ipin_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 57.790 49.640 +*I ropt_mt_inst_713:A I *L 0.001767 *C 93.380 69.360 +*N chanx_left_in[9]:4 *C 64.000 49.640 +*N chanx_left_in[9]:5 *C 93.380 69.360 +*N chanx_left_in[9]:6 *C 93.380 69.405 +*N chanx_left_in[9]:7 *C 93.380 71.355 +*N chanx_left_in[9]:8 *C 93.335 71.400 +*N chanx_left_in[9]:9 *C 79.165 71.400 +*N chanx_left_in[9]:10 *C 79.120 71.355 +*N chanx_left_in[9]:11 *C 79.120 66.698 +*N chanx_left_in[9]:12 *C 79.112 66.640 +*N chanx_left_in[9]:13 *C 64.420 66.640 +*N chanx_left_in[9]:14 *C 64.400 66.633 +*N chanx_left_in[9]:15 *C 64.400 49.648 +*N chanx_left_in[9]:16 *C 64.400 49.640 +*N chanx_left_in[9]:17 *C 64.400 49.640 +*N chanx_left_in[9]:18 *C 64.355 49.640 +*N chanx_left_in[9]:19 *C 57.828 49.640 +*N chanx_left_in[9]:20 *C 58.420 49.640 +*N chanx_left_in[9]:21 *C 58.420 49.640 +*N chanx_left_in[9]:22 *C 58.413 49.640 +*N chanx_left_in[9]:23 *C 18.400 49.640 +*N chanx_left_in[9]:24 *C 18.400 50.320 +*N chanx_left_in[9]:25 *C 16.560 50.320 +*N chanx_left_in[9]:26 *C 16.560 49.640 +*N chanx_left_in[9]:27 *C 15.180 50.660 +*N chanx_left_in[9]:28 *C 15.180 50.615 +*N chanx_left_in[9]:29 *C 15.180 49.698 +*N chanx_left_in[9]:30 *C 15.180 49.640 +*N chanx_left_in[9]:31 *C 10.140 49.640 +*N chanx_left_in[9]:32 *C 10.120 49.633 +*N chanx_left_in[9]:33 *C 10.120 40.808 +*N chanx_left_in[9]:34 *C 10.100 40.800 + +*CAP +0 chanx_left_in[9] 0.0006520176 +1 mux_bottom_ipin_9\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_ipin_5\/mux_l2_in_1_:A0 1e-06 +3 ropt_mt_inst_713:A 1e-06 +4 chanx_left_in[9]:4 5.361268e-05 +5 chanx_left_in[9]:5 3.186203e-05 +6 chanx_left_in[9]:6 0.0001240043 +7 chanx_left_in[9]:7 0.0001240043 +8 chanx_left_in[9]:8 0.0009153055 +9 chanx_left_in[9]:9 0.0009153055 +10 chanx_left_in[9]:10 0.0003109416 +11 chanx_left_in[9]:11 0.0003109416 +12 chanx_left_in[9]:12 0.000833831 +13 chanx_left_in[9]:13 0.000833831 +14 chanx_left_in[9]:14 0.0006707744 +15 chanx_left_in[9]:15 0.0006707744 +16 chanx_left_in[9]:16 5.361268e-05 +17 chanx_left_in[9]:17 3.477575e-05 +18 chanx_left_in[9]:18 0.0003640909 +19 chanx_left_in[9]:19 3.574014e-05 +20 chanx_left_in[9]:20 0.000435539 +21 chanx_left_in[9]:21 3.688122e-05 +22 chanx_left_in[9]:22 0.001683874 +23 chanx_left_in[9]:23 0.001742261 +24 chanx_left_in[9]:24 0.0002120232 +25 chanx_left_in[9]:25 0.0002077868 +26 chanx_left_in[9]:26 0.0001292726 +27 chanx_left_in[9]:27 3.27636e-05 +28 chanx_left_in[9]:28 7.879133e-05 +29 chanx_left_in[9]:29 7.879133e-05 +30 chanx_left_in[9]:30 0.0003223257 +31 chanx_left_in[9]:31 0.0002472041 +32 chanx_left_in[9]:32 0.000541255 +33 chanx_left_in[9]:33 0.000541255 +34 chanx_left_in[9]:34 0.0006520176 +35 chanx_left_in[9]:16 chanx_left_in[3]:42 1.494404e-05 +36 chanx_left_in[9]:22 chanx_left_in[3]:42 0.0002853394 +37 chanx_left_in[9]:23 chanx_left_in[3]:43 0.0002853394 +38 chanx_left_in[9]:4 chanx_left_in[3]:37 1.494404e-05 +39 chanx_left_in[9]:15 chanx_left_in[5]:16 0.0003333473 +40 chanx_left_in[9]:14 chanx_left_in[5]:17 0.0003333473 +41 chanx_left_in[9]:16 chanx_left_in[19]:31 1.61753e-05 +42 chanx_left_in[9]:22 chanx_left_in[19]:30 0.0006845057 +43 chanx_left_in[9]:23 chanx_left_in[19]:31 0.0006845057 +44 chanx_left_in[9]:4 chanx_left_in[19]:30 1.61753e-05 +45 chanx_left_in[9]:31 chanx_right_in[11]:16 0.0001011872 +46 chanx_left_in[9]:22 chanx_right_in[11]:17 0.0001614686 +47 chanx_left_in[9]:30 chanx_right_in[11]:17 0.0001011872 +48 chanx_left_in[9]:30 chanx_right_in[11]:16 1.974588e-05 +49 chanx_left_in[9]:26 chanx_right_in[11]:17 1.974588e-05 +50 chanx_left_in[9]:25 chanx_right_in[11]:16 0.0001143654 +51 chanx_left_in[9]:24 chanx_right_in[11]:17 0.0001143654 +52 chanx_left_in[9]:23 chanx_right_in[11]:16 0.0001614686 +53 chanx_left_in[9]:13 prog_clk[0]:397 3.862874e-05 +54 chanx_left_in[9]:13 prog_clk[0]:392 9.43327e-05 +55 chanx_left_in[9]:11 prog_clk[0]:399 3.776144e-06 +56 chanx_left_in[9]:11 prog_clk[0]:226 1.940519e-06 +57 chanx_left_in[9]:12 prog_clk[0]:398 3.862874e-05 +58 chanx_left_in[9]:12 prog_clk[0]:393 9.43327e-05 +59 chanx_left_in[9]:9 prog_clk[0]:405 1.308489e-05 +60 chanx_left_in[9]:9 prog_clk[0]:401 3.462167e-05 +61 chanx_left_in[9]:10 prog_clk[0]:399 1.940519e-06 +62 chanx_left_in[9]:10 prog_clk[0]:402 3.776144e-06 +63 chanx_left_in[9]:8 prog_clk[0]:400 3.462167e-05 +64 chanx_left_in[9]:8 prog_clk[0]:406 1.308489e-05 +65 chanx_left_in[9]:31 prog_clk[0]:281 3.126248e-05 +66 chanx_left_in[9]:22 prog_clk[0]:282 1.616156e-05 +67 chanx_left_in[9]:22 prog_clk[0]:371 0.0001349838 +68 chanx_left_in[9]:22 prog_clk[0]:370 5.941498e-05 +69 chanx_left_in[9]:30 prog_clk[0]:282 3.126248e-05 +70 chanx_left_in[9]:30 prog_clk[0]:281 1.666611e-05 +71 chanx_left_in[9]:26 prog_clk[0]:282 1.666611e-05 +72 chanx_left_in[9]:25 prog_clk[0]:281 2.462835e-06 +73 chanx_left_in[9]:24 prog_clk[0]:282 2.462835e-06 +74 chanx_left_in[9]:23 prog_clk[0]:281 1.616156e-05 +75 chanx_left_in[9]:23 prog_clk[0]:315 5.941498e-05 +76 chanx_left_in[9]:23 prog_clk[0]:370 0.0001349838 +77 chanx_left_in[9]:18 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.298484e-05 +78 chanx_left_in[9]:20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.35286e-05 +79 chanx_left_in[9]:20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.298484e-05 +80 chanx_left_in[9]:19 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.35286e-05 +81 chanx_left_in[9]:15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0003123031 +82 chanx_left_in[9]:13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 1.533424e-05 +83 chanx_left_in[9]:14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0003123031 +84 chanx_left_in[9]:12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 1.533424e-05 +85 chanx_left_in[9]:22 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001214908 +86 chanx_left_in[9]:23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001214908 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:34 0.001389633 +1 chanx_left_in[9]:18 chanx_left_in[9]:17 0.0045 +2 chanx_left_in[9]:17 chanx_left_in[9]:16 0.00341 +3 chanx_left_in[9]:16 chanx_left_in[9]:15 0.00341 +4 chanx_left_in[9]:16 chanx_left_in[9]:4 5.69697e-05 +5 chanx_left_in[9]:15 chanx_left_in[9]:14 0.002660983 +6 chanx_left_in[9]:13 chanx_left_in[9]:12 0.002301825 +7 chanx_left_in[9]:14 chanx_left_in[9]:13 0.00341 +8 chanx_left_in[9]:11 chanx_left_in[9]:10 0.004158482 +9 chanx_left_in[9]:12 chanx_left_in[9]:11 0.00341 +10 chanx_left_in[9]:9 chanx_left_in[9]:8 0.01265179 +11 chanx_left_in[9]:10 chanx_left_in[9]:9 0.0045 +12 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0045 +13 chanx_left_in[9]:7 chanx_left_in[9]:6 0.001741072 +14 chanx_left_in[9]:5 ropt_mt_inst_713:A 0.152 +15 chanx_left_in[9]:6 chanx_left_in[9]:5 0.0045 +16 chanx_left_in[9]:31 chanx_left_in[9]:30 0.0007896 +17 chanx_left_in[9]:32 chanx_left_in[9]:31 0.00341 +18 chanx_left_in[9]:34 chanx_left_in[9]:33 0.00341 +19 chanx_left_in[9]:33 chanx_left_in[9]:32 0.001382583 +20 chanx_left_in[9]:20 chanx_left_in[9]:19 0.0005290179 +21 chanx_left_in[9]:20 chanx_left_in[9]:18 0.005299107 +22 chanx_left_in[9]:21 chanx_left_in[9]:20 0.0045 +23 chanx_left_in[9]:22 chanx_left_in[9]:21 0.00341 +24 chanx_left_in[9]:19 mux_bottom_ipin_5\/mux_l2_in_1_:A0 0.152 +25 chanx_left_in[9]:29 chanx_left_in[9]:28 0.0008191965 +26 chanx_left_in[9]:30 chanx_left_in[9]:29 0.00341 +27 chanx_left_in[9]:30 chanx_left_in[9]:26 0.0002162 +28 chanx_left_in[9]:27 mux_bottom_ipin_9\/mux_l1_in_2_:A1 0.152 +29 chanx_left_in[9]:28 chanx_left_in[9]:27 0.0045 +30 chanx_left_in[9]:26 chanx_left_in[9]:25 0.0001065333 +31 chanx_left_in[9]:25 chanx_left_in[9]:24 0.0002882667 +32 chanx_left_in[9]:24 chanx_left_in[9]:23 0.0001065333 +33 chanx_left_in[9]:23 chanx_left_in[9]:22 0.006268625 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[2] 0.002726638 //LENGTH 22.650 LUMPCC 0.0001609695 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 18.705 33.660 +*I mux_bottom_ipin_8\/mux_l3_in_1_:S I *L 0.00357 *C 10.480 36.040 +*I mux_bottom_ipin_8\/mux_l3_in_0_:S I *L 0.00357 *C 10.240 34.680 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 12.135 39.100 +*N mux_tree_tapbuf_size10_4_sram[2]:4 *C 12.173 39.100 +*N mux_tree_tapbuf_size10_4_sram[2]:5 *C 12.835 39.100 +*N mux_tree_tapbuf_size10_4_sram[2]:6 *C 12.880 39.055 +*N mux_tree_tapbuf_size10_4_sram[2]:7 *C 10.277 34.680 +*N mux_tree_tapbuf_size10_4_sram[2]:8 *C 11.455 34.680 +*N mux_tree_tapbuf_size10_4_sram[2]:9 *C 11.500 34.635 +*N mux_tree_tapbuf_size10_4_sram[2]:10 *C 10.518 36.040 +*N mux_tree_tapbuf_size10_4_sram[2]:11 *C 10.995 36.040 +*N mux_tree_tapbuf_size10_4_sram[2]:12 *C 11.040 35.995 +*N mux_tree_tapbuf_size10_4_sram[2]:13 *C 11.040 34.000 +*N mux_tree_tapbuf_size10_4_sram[2]:14 *C 11.500 34.000 +*N mux_tree_tapbuf_size10_4_sram[2]:15 *C 11.500 33.320 +*N mux_tree_tapbuf_size10_4_sram[2]:16 *C 12.880 33.320 +*N mux_tree_tapbuf_size10_4_sram[2]:17 *C 12.880 34.340 +*N mux_tree_tapbuf_size10_4_sram[2]:18 *C 14.260 34.340 +*N mux_tree_tapbuf_size10_4_sram[2]:19 *C 14.260 33.705 +*N mux_tree_tapbuf_size10_4_sram[2]:20 *C 14.305 33.660 +*N mux_tree_tapbuf_size10_4_sram[2]:21 *C 18.668 33.660 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_8\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_4_sram[2]:4 7.010026e-05 +5 mux_tree_tapbuf_size10_4_sram[2]:5 7.010026e-05 +6 mux_tree_tapbuf_size10_4_sram[2]:6 0.0002802683 +7 mux_tree_tapbuf_size10_4_sram[2]:7 0.0001125977 +8 mux_tree_tapbuf_size10_4_sram[2]:8 0.0001125977 +9 mux_tree_tapbuf_size10_4_sram[2]:9 4.245656e-05 +10 mux_tree_tapbuf_size10_4_sram[2]:10 5.022765e-05 +11 mux_tree_tapbuf_size10_4_sram[2]:11 5.022765e-05 +12 mux_tree_tapbuf_size10_4_sram[2]:12 6.502855e-05 +13 mux_tree_tapbuf_size10_4_sram[2]:13 0.0001013297 +14 mux_tree_tapbuf_size10_4_sram[2]:14 0.0001193255 +15 mux_tree_tapbuf_size10_4_sram[2]:15 0.0001210218 +16 mux_tree_tapbuf_size10_4_sram[2]:16 0.0001460496 +17 mux_tree_tapbuf_size10_4_sram[2]:17 0.0004309643 +18 mux_tree_tapbuf_size10_4_sram[2]:18 0.0001435868 +19 mux_tree_tapbuf_size10_4_sram[2]:19 5.848635e-05 +20 mux_tree_tapbuf_size10_4_sram[2]:20 0.0002936498 +21 mux_tree_tapbuf_size10_4_sram[2]:21 0.0002936498 +22 mux_tree_tapbuf_size10_4_sram[2]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.137531e-08 +23 mux_tree_tapbuf_size10_4_sram[2]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.438569e-07 +24 mux_tree_tapbuf_size10_4_sram[2]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.622353e-06 +25 mux_tree_tapbuf_size10_4_sram[2]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.378044e-06 +26 mux_tree_tapbuf_size10_4_sram[2]:12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.689355e-05 +27 mux_tree_tapbuf_size10_4_sram[2]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.378044e-06 +28 mux_tree_tapbuf_size10_4_sram[2]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.185329e-06 +29 mux_tree_tapbuf_size10_4_sram[2]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.801496e-06 +30 mux_tree_tapbuf_size10_4_sram[2]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:8 6.185329e-06 +31 mux_tree_tapbuf_size10_4_sram[2]:13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.689355e-05 +32 mux_tree_tapbuf_size10_4_sram[2]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.801496e-06 +33 mux_tree_tapbuf_size10_4_sram[2]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.240944e-07 +34 mux_tree_tapbuf_size10_4_sram[2]:15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.240944e-07 +35 mux_tree_tapbuf_size10_4_sram[2]:16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.14619e-07 +36 mux_tree_tapbuf_size10_4_sram[2]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.438569e-07 +37 mux_tree_tapbuf_size10_4_sram[2]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.14619e-07 +38 mux_tree_tapbuf_size10_4_sram[2]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.622353e-06 +39 mux_tree_tapbuf_size10_4_sram[2]:18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.137531e-08 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_4_sram[2]:21 0.152 +1 mux_tree_tapbuf_size10_4_sram[2]:21 mux_tree_tapbuf_size10_4_sram[2]:20 0.003895089 +2 mux_tree_tapbuf_size10_4_sram[2]:20 mux_tree_tapbuf_size10_4_sram[2]:19 0.0045 +3 mux_tree_tapbuf_size10_4_sram[2]:19 mux_tree_tapbuf_size10_4_sram[2]:18 0.0005669643 +4 mux_tree_tapbuf_size10_4_sram[2]:5 mux_tree_tapbuf_size10_4_sram[2]:4 0.0005915179 +5 mux_tree_tapbuf_size10_4_sram[2]:6 mux_tree_tapbuf_size10_4_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size10_4_sram[2]:4 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size10_4_sram[2]:11 mux_tree_tapbuf_size10_4_sram[2]:10 0.0004263393 +8 mux_tree_tapbuf_size10_4_sram[2]:12 mux_tree_tapbuf_size10_4_sram[2]:11 0.0045 +9 mux_tree_tapbuf_size10_4_sram[2]:10 mux_bottom_ipin_8\/mux_l3_in_1_:S 0.152 +10 mux_tree_tapbuf_size10_4_sram[2]:8 mux_tree_tapbuf_size10_4_sram[2]:7 0.001051339 +11 mux_tree_tapbuf_size10_4_sram[2]:9 mux_tree_tapbuf_size10_4_sram[2]:8 0.0045 +12 mux_tree_tapbuf_size10_4_sram[2]:7 mux_bottom_ipin_8\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_4_sram[2]:13 mux_tree_tapbuf_size10_4_sram[2]:12 0.00178125 +14 mux_tree_tapbuf_size10_4_sram[2]:14 mux_tree_tapbuf_size10_4_sram[2]:13 0.0004107143 +15 mux_tree_tapbuf_size10_4_sram[2]:14 mux_tree_tapbuf_size10_4_sram[2]:9 0.0005669644 +16 mux_tree_tapbuf_size10_4_sram[2]:15 mux_tree_tapbuf_size10_4_sram[2]:14 0.000607143 +17 mux_tree_tapbuf_size10_4_sram[2]:16 mux_tree_tapbuf_size10_4_sram[2]:15 0.001232143 +18 mux_tree_tapbuf_size10_4_sram[2]:17 mux_tree_tapbuf_size10_4_sram[2]:16 0.0009107143 +19 mux_tree_tapbuf_size10_4_sram[2]:17 mux_tree_tapbuf_size10_4_sram[2]:6 0.004209822 +20 mux_tree_tapbuf_size10_4_sram[2]:18 mux_tree_tapbuf_size10_4_sram[2]:17 0.001232143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_3_ccff_tail[0] 0.001105838 //LENGTH 9.060 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_5\/FTB_4__43:X O *L 0 *C 46.685 47.260 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.095 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 *C 47.095 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 *C 46.920 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 *C 46.920 39.145 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 *C 46.920 47.215 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 *C 46.920 47.260 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 *C 46.685 47.260 + +*CAP +0 mem_bottom_ipin_5\/FTB_4__43:X 1e-06 +1 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 4.759532e-05 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 5.171475e-05 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.0004459568 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0004459568 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 5.624545e-05 +7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 5.636838e-05 + +*RES +0 mem_bottom_ipin_5\/FTB_4__43:X mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.007205358 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[0] 0.005055817 //LENGTH 41.550 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 37.565 37.060 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 30.075 64.260 +*I mux_bottom_ipin_7\/mux_l1_in_0_:S I *L 0.00357 *C 32.760 52.360 +*N mux_tree_tapbuf_size8_3_sram[0]:3 *C 32.797 52.360 +*N mux_tree_tapbuf_size8_3_sram[0]:4 *C 34.455 52.360 +*N mux_tree_tapbuf_size8_3_sram[0]:5 *C 34.500 52.315 +*N mux_tree_tapbuf_size8_3_sram[0]:6 *C 32.410 60.520 +*N mux_tree_tapbuf_size8_3_sram[0]:7 *C 30.113 64.260 +*N mux_tree_tapbuf_size8_3_sram[0]:8 *C 33.075 64.260 +*N mux_tree_tapbuf_size8_3_sram[0]:9 *C 33.120 64.215 +*N mux_tree_tapbuf_size8_3_sram[0]:10 *C 33.120 60.578 +*N mux_tree_tapbuf_size8_3_sram[0]:11 *C 33.117 60.520 +*N mux_tree_tapbuf_size8_3_sram[0]:12 *C 33.120 60.513 +*N mux_tree_tapbuf_size8_3_sram[0]:13 *C 33.120 51.008 +*N mux_tree_tapbuf_size8_3_sram[0]:14 *C 33.140 51.000 +*N mux_tree_tapbuf_size8_3_sram[0]:15 *C 34.492 51.000 +*N mux_tree_tapbuf_size8_3_sram[0]:16 *C 34.500 51.000 +*N mux_tree_tapbuf_size8_3_sram[0]:17 *C 34.960 51.000 +*N mux_tree_tapbuf_size8_3_sram[0]:18 *C 34.960 37.105 +*N mux_tree_tapbuf_size8_3_sram[0]:19 *C 35.005 37.060 +*N mux_tree_tapbuf_size8_3_sram[0]:20 *C 37.528 37.060 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_7\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_3_sram[0]:3 0.0001518304 +4 mux_tree_tapbuf_size8_3_sram[0]:4 0.0001518304 +5 mux_tree_tapbuf_size8_3_sram[0]:5 0.0001054835 +6 mux_tree_tapbuf_size8_3_sram[0]:6 0.0001281123 +7 mux_tree_tapbuf_size8_3_sram[0]:7 0.0002132537 +8 mux_tree_tapbuf_size8_3_sram[0]:8 0.0002132537 +9 mux_tree_tapbuf_size8_3_sram[0]:9 0.000211721 +10 mux_tree_tapbuf_size8_3_sram[0]:10 0.000211721 +11 mux_tree_tapbuf_size8_3_sram[0]:11 0.0001281123 +12 mux_tree_tapbuf_size8_3_sram[0]:12 0.0005955225 +13 mux_tree_tapbuf_size8_3_sram[0]:13 0.0005955225 +14 mux_tree_tapbuf_size8_3_sram[0]:14 0.0001277061 +15 mux_tree_tapbuf_size8_3_sram[0]:15 0.0001277061 +16 mux_tree_tapbuf_size8_3_sram[0]:16 0.0001407998 +17 mux_tree_tapbuf_size8_3_sram[0]:17 0.0008238738 +18 mux_tree_tapbuf_size8_3_sram[0]:18 0.0007885575 +19 mux_tree_tapbuf_size8_3_sram[0]:19 0.000168905 +20 mux_tree_tapbuf_size8_3_sram[0]:20 0.000168905 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_3_sram[0]:20 0.152 +1 mux_tree_tapbuf_size8_3_sram[0]:16 mux_tree_tapbuf_size8_3_sram[0]:15 0.00341 +2 mux_tree_tapbuf_size8_3_sram[0]:16 mux_tree_tapbuf_size8_3_sram[0]:5 0.001174107 +3 mux_tree_tapbuf_size8_3_sram[0]:15 mux_tree_tapbuf_size8_3_sram[0]:14 0.0002118916 +4 mux_tree_tapbuf_size8_3_sram[0]:14 mux_tree_tapbuf_size8_3_sram[0]:13 0.00341 +5 mux_tree_tapbuf_size8_3_sram[0]:13 mux_tree_tapbuf_size8_3_sram[0]:12 0.001489117 +6 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_3_sram[0]:10 0.00341 +7 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_3_sram[0]:6 0.0001039141 +8 mux_tree_tapbuf_size8_3_sram[0]:12 mux_tree_tapbuf_size8_3_sram[0]:11 0.00341 +9 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:9 0.003247768 +10 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[0]:7 0.002645089 +11 mux_tree_tapbuf_size8_3_sram[0]:9 mux_tree_tapbuf_size8_3_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size8_3_sram[0]:7 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size8_3_sram[0]:4 mux_tree_tapbuf_size8_3_sram[0]:3 0.001479911 +14 mux_tree_tapbuf_size8_3_sram[0]:5 mux_tree_tapbuf_size8_3_sram[0]:4 0.0045 +15 mux_tree_tapbuf_size8_3_sram[0]:3 mux_bottom_ipin_7\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size8_3_sram[0]:19 mux_tree_tapbuf_size8_3_sram[0]:18 0.0045 +17 mux_tree_tapbuf_size8_3_sram[0]:18 mux_tree_tapbuf_size8_3_sram[0]:17 0.01240625 +18 mux_tree_tapbuf_size8_3_sram[0]:20 mux_tree_tapbuf_size8_3_sram[0]:19 0.002252232 +19 mux_tree_tapbuf_size8_3_sram[0]:17 mux_tree_tapbuf_size8_3_sram[0]:16 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[1] 0.004298527 //LENGTH 31.330 LUMPCC 0.0004549861 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 90.465 50.320 +*I mux_bottom_ipin_15\/mux_l2_in_2_:S I *L 0.00357 *C 89.800 52.360 +*I mux_bottom_ipin_15\/mux_l2_in_0_:S I *L 0.00357 *C 87.860 55.930 +*I mux_bottom_ipin_15\/mux_l2_in_3_:S I *L 0.00357 *C 89.800 55.760 +*I mux_bottom_ipin_15\/mux_l2_in_1_:S I *L 0.00357 *C 89.340 58.480 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 85.735 71.740 +*N mux_tree_tapbuf_size8_7_sram[1]:6 *C 85.735 71.740 +*N mux_tree_tapbuf_size8_7_sram[1]:7 *C 86.020 71.740 +*N mux_tree_tapbuf_size8_7_sram[1]:8 *C 86.020 71.695 +*N mux_tree_tapbuf_size8_7_sram[1]:9 *C 86.020 58.820 +*N mux_tree_tapbuf_size8_7_sram[1]:10 *C 85.560 58.820 +*N mux_tree_tapbuf_size8_7_sram[1]:11 *C 85.605 58.820 +*N mux_tree_tapbuf_size8_7_sram[1]:12 *C 89.240 58.820 +*N mux_tree_tapbuf_size8_7_sram[1]:13 *C 89.240 58.480 +*N mux_tree_tapbuf_size8_7_sram[1]:14 *C 89.340 58.480 +*N mux_tree_tapbuf_size8_7_sram[1]:15 *C 89.240 58.140 +*N mux_tree_tapbuf_size8_7_sram[1]:16 *C 89.240 58.095 +*N mux_tree_tapbuf_size8_7_sram[1]:17 *C 89.763 55.760 +*N mux_tree_tapbuf_size8_7_sram[1]:18 *C 87.898 55.823 +*N mux_tree_tapbuf_size8_7_sram[1]:19 *C 89.240 55.760 +*N mux_tree_tapbuf_size8_7_sram[1]:20 *C 89.240 55.760 +*N mux_tree_tapbuf_size8_7_sram[1]:21 *C 89.700 55.760 +*N mux_tree_tapbuf_size8_7_sram[1]:22 *C 89.700 52.360 +*N mux_tree_tapbuf_size8_7_sram[1]:23 *C 89.700 52.360 +*N mux_tree_tapbuf_size8_7_sram[1]:24 *C 89.700 50.365 +*N mux_tree_tapbuf_size8_7_sram[1]:25 *C 89.745 50.320 +*N mux_tree_tapbuf_size8_7_sram[1]:26 *C 90.428 50.320 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_15\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_ipin_15\/mux_l2_in_3_:S 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_1_:S 1e-06 +5 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_7_sram[1]:6 5.149122e-05 +7 mux_tree_tapbuf_size8_7_sram[1]:7 5.527134e-05 +8 mux_tree_tapbuf_size8_7_sram[1]:8 0.0006334272 +9 mux_tree_tapbuf_size8_7_sram[1]:9 0.0006702902 +10 mux_tree_tapbuf_size8_7_sram[1]:10 7.221443e-05 +11 mux_tree_tapbuf_size8_7_sram[1]:11 0.0002078276 +12 mux_tree_tapbuf_size8_7_sram[1]:12 0.0002294607 +13 mux_tree_tapbuf_size8_7_sram[1]:13 1.403315e-05 +14 mux_tree_tapbuf_size8_7_sram[1]:14 9.406391e-05 +15 mux_tree_tapbuf_size8_7_sram[1]:15 6.464951e-05 +16 mux_tree_tapbuf_size8_7_sram[1]:16 0.0001623863 +17 mux_tree_tapbuf_size8_7_sram[1]:17 6.069842e-05 +18 mux_tree_tapbuf_size8_7_sram[1]:18 0.0001226387 +19 mux_tree_tapbuf_size8_7_sram[1]:19 0.0002200686 +20 mux_tree_tapbuf_size8_7_sram[1]:20 0.0001984211 +21 mux_tree_tapbuf_size8_7_sram[1]:21 0.0002754349 +22 mux_tree_tapbuf_size8_7_sram[1]:22 3.327485e-05 +23 mux_tree_tapbuf_size8_7_sram[1]:23 0.0004084483 +24 mux_tree_tapbuf_size8_7_sram[1]:24 0.0001387573 +25 mux_tree_tapbuf_size8_7_sram[1]:25 6.234201e-05 +26 mux_tree_tapbuf_size8_7_sram[1]:26 6.234201e-05 +27 mux_tree_tapbuf_size8_7_sram[1]:11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.165741e-05 +28 mux_tree_tapbuf_size8_7_sram[1]:12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.165741e-05 +29 mux_tree_tapbuf_size8_7_sram[1]:11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.319903e-05 +30 mux_tree_tapbuf_size8_7_sram[1]:8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001226366 +31 mux_tree_tapbuf_size8_7_sram[1]:12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.319903e-05 +32 mux_tree_tapbuf_size8_7_sram[1]:9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001226366 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_7_sram[1]:26 0.152 +1 mux_tree_tapbuf_size8_7_sram[1]:22 mux_bottom_ipin_15\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size8_7_sram[1]:23 mux_tree_tapbuf_size8_7_sram[1]:22 0.0045 +3 mux_tree_tapbuf_size8_7_sram[1]:23 mux_tree_tapbuf_size8_7_sram[1]:21 0.003035714 +4 mux_tree_tapbuf_size8_7_sram[1]:19 mux_tree_tapbuf_size8_7_sram[1]:18 0.001198661 +5 mux_tree_tapbuf_size8_7_sram[1]:19 mux_tree_tapbuf_size8_7_sram[1]:17 0.0004665178 +6 mux_tree_tapbuf_size8_7_sram[1]:20 mux_tree_tapbuf_size8_7_sram[1]:19 0.0045 +7 mux_tree_tapbuf_size8_7_sram[1]:20 mux_tree_tapbuf_size8_7_sram[1]:16 0.002084821 +8 mux_tree_tapbuf_size8_7_sram[1]:15 mux_tree_tapbuf_size8_7_sram[1]:14 0.0001847826 +9 mux_tree_tapbuf_size8_7_sram[1]:16 mux_tree_tapbuf_size8_7_sram[1]:15 0.0045 +10 mux_tree_tapbuf_size8_7_sram[1]:17 mux_bottom_ipin_15\/mux_l2_in_3_:S 0.152 +11 mux_tree_tapbuf_size8_7_sram[1]:14 mux_bottom_ipin_15\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size8_7_sram[1]:14 mux_tree_tapbuf_size8_7_sram[1]:13 1e-05 +13 mux_tree_tapbuf_size8_7_sram[1]:14 mux_tree_tapbuf_size8_7_sram[1]:12 0.0003035715 +14 mux_tree_tapbuf_size8_7_sram[1]:18 mux_bottom_ipin_15\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size8_7_sram[1]:11 mux_tree_tapbuf_size8_7_sram[1]:10 0.0045 +16 mux_tree_tapbuf_size8_7_sram[1]:10 mux_tree_tapbuf_size8_7_sram[1]:9 0.0004107143 +17 mux_tree_tapbuf_size8_7_sram[1]:7 mux_tree_tapbuf_size8_7_sram[1]:6 0.0001548913 +18 mux_tree_tapbuf_size8_7_sram[1]:8 mux_tree_tapbuf_size8_7_sram[1]:7 0.0045 +19 mux_tree_tapbuf_size8_7_sram[1]:6 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +20 mux_tree_tapbuf_size8_7_sram[1]:25 mux_tree_tapbuf_size8_7_sram[1]:24 0.0045 +21 mux_tree_tapbuf_size8_7_sram[1]:24 mux_tree_tapbuf_size8_7_sram[1]:23 0.00178125 +22 mux_tree_tapbuf_size8_7_sram[1]:26 mux_tree_tapbuf_size8_7_sram[1]:25 0.000609375 +23 mux_tree_tapbuf_size8_7_sram[1]:12 mux_tree_tapbuf_size8_7_sram[1]:11 0.003245536 +24 mux_tree_tapbuf_size8_7_sram[1]:9 mux_tree_tapbuf_size8_7_sram[1]:8 0.01149554 +25 mux_tree_tapbuf_size8_7_sram[1]:21 mux_tree_tapbuf_size8_7_sram[1]:20 0.0004107143 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005436462 //LENGTH 4.265 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_1_:X O *L 0 *C 55.835 50.660 +*I mux_bottom_ipin_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 55.030 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 55.068 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 55.615 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 55.660 53.335 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 55.660 50.705 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 55.660 50.660 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 55.835 50.660 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.58507e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.58507e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001589577 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001589577 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.730281e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.472663e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.510871e-05 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005154653 //LENGTH 2.650 LUMPCC 0.0002270524 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_0_:X O *L 0 *C 19.035 56.100 +*I mux_bottom_ipin_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.765 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.765 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 18.860 58.095 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 18.860 56.145 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 18.860 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 19.035 56.100 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.33438e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.381739e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.381739e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.268367e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.275064e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 prog_clk[0]:286 5.721596e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:283 5.721596e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.631023e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.631023e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001741072 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004712375 //LENGTH 3.125 LUMPCC 0.0003075601 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_2_:X O *L 0 *C 69.635 30.940 +*I mux_bottom_ipin_12\/mux_l3_in_1_:A1 I *L 0.00198 *C 66.800 30.940 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 66.838 30.940 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 69.597 30.940 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.08387e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.08387e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_6_sram[1]:13 0.0001164702 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_6_sram[1]:6 0.0001164702 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_6_sram[2]:8 3.73098e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_6_sram[2]:7 3.73098e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_2_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002464286 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008186264 //LENGTH 5.230 LUMPCC 0.0003451459 DR + +*CONN +*I mux_top_ipin_0\/mux_l2_in_0_:X O *L 0 *C 91.255 17.000 +*I mux_top_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 89.145 14.620 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 89.183 14.620 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 91.035 14.620 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 91.080 14.665 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 91.080 16.955 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 91.080 17.000 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 91.255 17.000 + +*CAP +0 mux_top_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.186139e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.186139e-05 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.439324e-05 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.439324e-05 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.096681e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.800444e-05 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_8_sram[1]:11 6.948946e-05 +9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_8_sram[1]:29 8.133429e-06 +10 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_8_sram[1]:25 1.337538e-05 +11 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_8_sram[1]:12 6.948946e-05 +12 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_8_sram[1]:28 8.133429e-06 +13 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_8_sram[1]:26 1.337538e-05 +14 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_8_sram[2]:14 8.154415e-05 +15 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_8_sram[2]:15 8.154415e-05 +16 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_8_sram[2]:14 3.052519e-08 +17 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_8_sram[2]:15 3.052519e-08 + +*RES +0 mux_top_ipin_0\/mux_l2_in_0_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0] 0.006761209 //LENGTH 52.120 LUMPCC 0.001583979 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l4_in_0_:X O *L 0 *C 40.655 25.840 +*I mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 34.660 69.545 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 34.660 69.545 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 34.500 69.700 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 34.500 69.700 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 34.500 70.040 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 34.508 70.040 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 39.540 70.040 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 39.560 70.032 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 39.560 25.848 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 39.580 25.840 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 40.473 25.840 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 40.480 25.840 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 40.480 25.840 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 40.655 25.840 + +*CAP +0 mux_bottom_ipin_6\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.615153e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.147428e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.093103e-05 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.476193e-05 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002114016 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002114016 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.002077062 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.002077062 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001197828 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001197828 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 3.512839e-05 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 6.026638e-05 +14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 6.002287e-05 +15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:297 4.776232e-05 +16 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:306 0.0001477014 +17 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:305 4.776232e-05 +18 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:310 0.0001477014 +19 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 prog_clk[0]:306 5.33058e-06 +20 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 prog_clk[0]:305 5.33058e-06 +21 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size8_0_sram[0]:14 0.000591195 +22 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_tree_tapbuf_size8_0_sram[0]:13 0.000591195 + +*RES +0 mux_bottom_ipin_6\/mux_l4_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.695653e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001634615 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000788425 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.006922316 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.000139825 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0045 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004801316 //LENGTH 2.550 LUMPCC 0.0001833148 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_1_:X O *L 0 *C 88.495 59.235 +*I mux_bottom_ipin_15\/mux_l3_in_0_:A0 I *L 0.001631 *C 86.235 59.160 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 86.273 59.160 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 88.495 59.235 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001173226 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001774941 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size8_7_sram[1]:12 9.165741e-05 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size8_7_sram[1]:11 9.165741e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_1_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001984375 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET ropt_net_153 0.0001067804 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_712:X O *L 0 *C 92.655 4.080 +*I ropt_mt_inst_752:A I *L 0.001767 *C 93.380 4.080 +*N ropt_net_153:2 *C 93.343 4.080 +*N ropt_net_153:3 *C 92.693 4.080 + +*CAP +0 ropt_mt_inst_712:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_153:2 5.239019e-05 +3 ropt_net_153:3 5.239019e-05 + +*RES +0 ropt_mt_inst_712:X ropt_net_153:3 0.152 +1 ropt_net_153:2 ropt_mt_inst_752:A 0.152 +2 ropt_net_153:3 ropt_net_153:2 0.0005803572 + +*END + +*D_NET ropt_net_129 0.001605704 //LENGTH 11.455 LUMPCC 0.0006120873 DR + +*CONN +*I FTB_28__27:X O *L 0 *C 7.820 45.560 +*I ropt_mt_inst_728:A I *L 0.001766 *C 7.820 53.040 +*N ropt_net_129:2 *C 7.783 53.040 +*N ropt_net_129:3 *C 7.405 53.040 +*N ropt_net_129:4 *C 7.360 52.995 +*N ropt_net_129:5 *C 7.360 47.657 +*N ropt_net_129:6 *C 7.360 47.600 +*N ropt_net_129:7 *C 8.273 47.600 +*N ropt_net_129:8 *C 8.280 47.543 +*N ropt_net_129:9 *C 8.280 45.605 +*N ropt_net_129:10 *C 8.235 45.560 +*N ropt_net_129:11 *C 7.858 45.560 + +*CAP +0 FTB_28__27:X 1e-06 +1 ropt_mt_inst_728:A 1e-06 +2 ropt_net_129:2 4.642578e-05 +3 ropt_net_129:3 4.642578e-05 +4 ropt_net_129:4 0.00016575 +5 ropt_net_129:5 0.00016575 +6 ropt_net_129:6 0.0001344536 +7 ropt_net_129:7 0.0001344536 +8 ropt_net_129:8 9.785595e-05 +9 ropt_net_129:9 9.785595e-05 +10 ropt_net_129:10 5.132332e-05 +11 ropt_net_129:11 5.132332e-05 +12 ropt_net_129:5 chanx_right_in[9]:10 9.790097e-05 +13 ropt_net_129:4 chanx_right_in[9]:9 9.790097e-05 +14 ropt_net_129:11 optlc_net_107:10 7.250787e-07 +15 ropt_net_129:10 optlc_net_107:11 7.250787e-07 +16 ropt_net_129:9 optlc_net_107:12 5.850441e-05 +17 ropt_net_129:8 optlc_net_107:13 5.850441e-05 +18 ropt_net_129:5 optlc_net_107:12 1.287833e-05 +19 ropt_net_129:5 optlc_net_107:13 0.0001360349 +20 ropt_net_129:4 optlc_net_107:5 0.0001360349 +21 ropt_net_129:4 optlc_net_107:13 1.287833e-05 + +*RES +0 FTB_28__27:X ropt_net_129:11 0.152 +1 ropt_net_129:11 ropt_net_129:10 0.0003370536 +2 ropt_net_129:10 ropt_net_129:9 0.0045 +3 ropt_net_129:9 ropt_net_129:8 0.001729911 +4 ropt_net_129:8 ropt_net_129:7 0.00341 +5 ropt_net_129:7 ropt_net_129:6 0.0001429583 +6 ropt_net_129:5 ropt_net_129:4 0.004765625 +7 ropt_net_129:6 ropt_net_129:5 0.00341 +8 ropt_net_129:3 ropt_net_129:2 0.0003370536 +9 ropt_net_129:4 ropt_net_129:3 0.0045 +10 ropt_net_129:2 ropt_mt_inst_728:A 0.152 + +*END + +*D_NET ropt_net_126 0.000387167 //LENGTH 3.510 LUMPCC 0 DR + +*CONN +*I BUFT_P_85:X O *L 0 *C 90.160 63.920 +*I ropt_mt_inst_725:A I *L 0.001766 *C 93.380 63.920 +*N ropt_net_126:2 *C 93.343 63.920 +*N ropt_net_126:3 *C 90.198 63.920 + +*CAP +0 BUFT_P_85:X 1e-06 +1 ropt_mt_inst_725:A 1e-06 +2 ropt_net_126:2 0.0001925835 +3 ropt_net_126:3 0.0001925835 + +*RES +0 BUFT_P_85:X ropt_net_126:3 0.152 +1 ropt_net_126:3 ropt_net_126:2 0.002808036 +2 ropt_net_126:2 ropt_mt_inst_725:A 0.152 + +*END + +*D_NET chanx_right_out[14] 0.0007602935 //LENGTH 6.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 98.900 7.480 +*P chanx_right_out[14] O *L 0.7423 *C 103.650 6.800 +*N chanx_right_out[14]:2 *C 100.288 6.800 +*N chanx_right_out[14]:3 *C 100.280 6.857 +*N chanx_right_out[14]:4 *C 100.280 7.435 +*N chanx_right_out[14]:5 *C 100.235 7.480 +*N chanx_right_out[14]:6 *C 98.938 7.480 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 chanx_right_out[14] 0.0002073943 +2 chanx_right_out[14]:2 0.0002073943 +3 chanx_right_out[14]:3 5.357084e-05 +4 chanx_right_out[14]:4 5.357084e-05 +5 chanx_right_out[14]:5 0.0001186816 +6 chanx_right_out[14]:6 0.0001186816 + +*RES +0 ropt_mt_inst_770:X chanx_right_out[14]:6 0.152 +1 chanx_right_out[14]:6 chanx_right_out[14]:5 0.001158482 +2 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +3 chanx_right_out[14]:4 chanx_right_out[14]:3 0.0005156251 +4 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +5 chanx_right_out[14]:2 chanx_right_out[14] 0.0005267917 + +*END + +*D_NET chanx_left_in[10] 0.02163737 //LENGTH 145.935 LUMPCC 0.007354117 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 24.480 +*I mux_bottom_ipin_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 50.430 22.440 +*I mux_bottom_ipin_14\/mux_l2_in_1_:A0 I *L 0.001631 *C 81.755 22.855 +*I FTB_11__10:A I *L 0.001776 *C 94.760 61.200 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 89.070 31.960 +*I mux_top_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 89.990 20.740 +*N chanx_left_in[10]:6 *C 90.028 20.740 +*N chanx_left_in[10]:7 *C 90.575 20.740 +*N chanx_left_in[10]:8 *C 90.620 20.785 +*N chanx_left_in[10]:9 *C 90.620 22.735 +*N chanx_left_in[10]:10 *C 90.575 22.780 +*N chanx_left_in[10]:11 *C 89.108 31.960 +*N chanx_left_in[10]:12 *C 89.655 31.960 +*N chanx_left_in[10]:13 *C 94.797 61.200 +*N chanx_left_in[10]:14 *C 95.175 61.200 +*N chanx_left_in[10]:15 *C 95.220 61.155 +*N chanx_left_in[10]:16 *C 95.220 57.178 +*N chanx_left_in[10]:17 *C 95.213 57.120 +*N chanx_left_in[10]:18 *C 92.020 57.120 +*N chanx_left_in[10]:19 *C 92.000 57.113 +*N chanx_left_in[10]:20 *C 92.000 31.968 +*N chanx_left_in[10]:21 *C 91.980 31.960 +*N chanx_left_in[10]:22 *C 89.708 31.960 +*N chanx_left_in[10]:23 *C 89.700 31.960 +*N chanx_left_in[10]:24 *C 89.700 22.825 +*N chanx_left_in[10]:25 *C 89.700 22.780 +*N chanx_left_in[10]:26 *C 81.755 22.855 +*N chanx_left_in[10]:27 *C 82.340 22.780 +*N chanx_left_in[10]:28 *C 82.340 22.780 +*N chanx_left_in[10]:29 *C 82.340 22.440 +*N chanx_left_in[10]:30 *C 82.333 22.440 +*N chanx_left_in[10]:31 *C 50.608 22.440 +*N chanx_left_in[10]:32 *C 50.430 22.440 +*N chanx_left_in[10]:33 *C 50.600 22.440 +*N chanx_left_in[10]:34 *C 50.600 22.440 +*N chanx_left_in[10]:35 *C 50.600 25.103 +*N chanx_left_in[10]:36 *C 50.593 25.160 +*N chanx_left_in[10]:37 *C 14.720 25.160 +*N chanx_left_in[10]:38 *C 14.720 24.480 + +*CAP +0 chanx_left_in[10] 0.0008626598 +1 mux_bottom_ipin_6\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_1_:A0 1e-06 +3 FTB_11__10:A 1e-06 +4 mux_bottom_ipin_0\/mux_l2_in_1_:A0 1e-06 +5 mux_top_ipin_0\/mux_l2_in_1_:A0 1e-06 +6 chanx_left_in[10]:6 5.637204e-05 +7 chanx_left_in[10]:7 5.637204e-05 +8 chanx_left_in[10]:8 9.458025e-05 +9 chanx_left_in[10]:9 9.458025e-05 +10 chanx_left_in[10]:10 8.026965e-05 +11 chanx_left_in[10]:11 6.656677e-05 +12 chanx_left_in[10]:12 6.656677e-05 +13 chanx_left_in[10]:13 5.580123e-05 +14 chanx_left_in[10]:14 5.580123e-05 +15 chanx_left_in[10]:15 0.0002023404 +16 chanx_left_in[10]:16 0.0002023404 +17 chanx_left_in[10]:17 0.0002301326 +18 chanx_left_in[10]:18 0.0002301326 +19 chanx_left_in[10]:19 0.001156165 +20 chanx_left_in[10]:20 0.001156165 +21 chanx_left_in[10]:21 0.0002733869 +22 chanx_left_in[10]:22 0.0002733869 +23 chanx_left_in[10]:23 0.0004104696 +24 chanx_left_in[10]:24 0.0003727764 +25 chanx_left_in[10]:25 0.0005206251 +26 chanx_left_in[10]:26 8.978424e-05 +27 chanx_left_in[10]:27 0.0004859011 +28 chanx_left_in[10]:28 5.468076e-05 +29 chanx_left_in[10]:29 5.649641e-05 +30 chanx_left_in[10]:30 0.001613195 +31 chanx_left_in[10]:31 0.001613195 +32 chanx_left_in[10]:32 5.224416e-05 +33 chanx_left_in[10]:33 5.588464e-05 +34 chanx_left_in[10]:34 0.0001861881 +35 chanx_left_in[10]:35 0.0001502594 +36 chanx_left_in[10]:36 0.001210841 +37 chanx_left_in[10]:37 0.001270136 +38 chanx_left_in[10]:38 0.0009219549 +39 chanx_left_in[10]:23 chanx_left_in[2]:30 1.382358e-05 +40 chanx_left_in[10]:18 chanx_left_in[2]:20 5.295342e-06 +41 chanx_left_in[10]:16 chanx_left_in[2]:19 6.121275e-06 +42 chanx_left_in[10]:17 chanx_left_in[2]:19 5.295342e-06 +43 chanx_left_in[10]:15 chanx_left_in[2]:18 6.121275e-06 +44 chanx_left_in[10]:25 chanx_left_in[2]:30 1.906128e-05 +45 chanx_left_in[10]:24 chanx_left_in[2]:29 1.382358e-05 +46 chanx_left_in[10]:31 chanx_left_in[2]:11 5.777929e-06 +47 chanx_left_in[10]:31 chanx_left_in[2]:31 0.0004986681 +48 chanx_left_in[10]:30 chanx_left_in[2]:12 5.777929e-06 +49 chanx_left_in[10]:30 chanx_left_in[2]:30 0.0004986681 +50 chanx_left_in[10]:27 chanx_left_in[2]:31 1.906128e-05 +51 chanx_left_in[10]:20 chanx_left_in[4]:20 0.0004865066 +52 chanx_left_in[10]:18 chanx_left_in[4]:10 3.542008e-07 +53 chanx_left_in[10]:19 chanx_left_in[4]:11 0.0004865066 +54 chanx_left_in[10]:16 chanx_left_in[4]:7 4.084402e-05 +55 chanx_left_in[10]:17 chanx_left_in[4]:9 3.542008e-07 +56 chanx_left_in[10]:15 chanx_left_in[4]:8 4.084402e-05 +57 chanx_left_in[10] chanx_left_in[12]:22 1.616842e-05 +58 chanx_left_in[10]:36 chanx_left_in[12]:21 0.0002816679 +59 chanx_left_in[10]:38 chanx_left_in[12]:21 1.616842e-05 +60 chanx_left_in[10]:37 chanx_left_in[12]:22 0.0002816679 +61 chanx_left_in[10] chanx_right_in[4]:11 0.0002601363 +62 chanx_left_in[10]:31 chanx_right_in[4]:11 0.0002094762 +63 chanx_left_in[10]:31 chanx_right_in[4]:17 0.0001718181 +64 chanx_left_in[10]:31 chanx_right_in[4]:12 0.0001294227 +65 chanx_left_in[10]:30 chanx_right_in[4]:18 0.0001718181 +66 chanx_left_in[10]:30 chanx_right_in[4]:17 0.0001294227 +67 chanx_left_in[10]:30 chanx_right_in[4]:12 0.0002094762 +68 chanx_left_in[10]:9 chanx_right_in[4]:19 2.201679e-07 +69 chanx_left_in[10]:8 chanx_right_in[4]:20 2.201679e-07 +70 chanx_left_in[10]:36 chanx_right_in[4]:12 0.0007705674 +71 chanx_left_in[10]:38 chanx_right_in[4]:12 0.0002601363 +72 chanx_left_in[10]:37 chanx_right_in[4]:11 0.0007705674 +73 chanx_left_in[10]:36 chanx_right_in[12]:26 0.0002483894 +74 chanx_left_in[10]:38 chanx_right_in[12]:20 6.610652e-06 +75 chanx_left_in[10]:37 chanx_right_in[12]:10 6.610652e-06 +76 chanx_left_in[10]:37 chanx_right_in[12]:25 0.0002483894 +77 chanx_left_in[10]:23 prog_clk[0]:164 0.000147443 +78 chanx_left_in[10]:23 prog_clk[0]:149 7.781186e-05 +79 chanx_left_in[10]:24 prog_clk[0]:149 0.000147443 +80 chanx_left_in[10]:24 prog_clk[0]:78 7.781186e-05 +81 chanx_left_in[10]:9 prog_clk[0]:149 5.987852e-05 +82 chanx_left_in[10]:8 prog_clk[0]:78 5.987852e-05 +83 chanx_left_in[10]:36 prog_clk[0]:341 0.0002209953 +84 chanx_left_in[10]:37 prog_clk[0]:340 0.0002209953 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:38 0.002113433 +1 chanx_left_in[10]:23 chanx_left_in[10]:22 0.00341 +2 chanx_left_in[10]:23 chanx_left_in[10]:12 0.0045 +3 chanx_left_in[10]:22 chanx_left_in[10]:21 0.000356025 +4 chanx_left_in[10]:21 chanx_left_in[10]:20 0.00341 +5 chanx_left_in[10]:20 chanx_left_in[10]:19 0.003939383 +6 chanx_left_in[10]:18 chanx_left_in[10]:17 0.0005001583 +7 chanx_left_in[10]:19 chanx_left_in[10]:18 0.00341 +8 chanx_left_in[10]:16 chanx_left_in[10]:15 0.003551339 +9 chanx_left_in[10]:17 chanx_left_in[10]:16 0.00341 +10 chanx_left_in[10]:14 chanx_left_in[10]:13 0.0003370536 +11 chanx_left_in[10]:15 chanx_left_in[10]:14 0.0045 +12 chanx_left_in[10]:13 FTB_11__10:A 0.152 +13 chanx_left_in[10]:25 chanx_left_in[10]:24 0.0045 +14 chanx_left_in[10]:25 chanx_left_in[10]:10 0.00078125 +15 chanx_left_in[10]:24 chanx_left_in[10]:23 0.00815625 +16 chanx_left_in[10]:33 chanx_left_in[10]:32 9.239131e-05 +17 chanx_left_in[10]:34 chanx_left_in[10]:33 0.0045 +18 chanx_left_in[10]:34 chanx_left_in[10]:31 0.00341 +19 chanx_left_in[10]:32 mux_bottom_ipin_6\/mux_l2_in_1_:A0 0.152 +20 chanx_left_in[10]:31 chanx_left_in[10]:30 0.00497025 +21 chanx_left_in[10]:29 chanx_left_in[10]:28 0.0001634615 +22 chanx_left_in[10]:30 chanx_left_in[10]:29 0.00341 +23 chanx_left_in[10]:27 chanx_left_in[10]:26 0.0005223214 +24 chanx_left_in[10]:27 chanx_left_in[10]:25 0.006571429 +25 chanx_left_in[10]:28 chanx_left_in[10]:27 0.0045 +26 chanx_left_in[10]:26 mux_bottom_ipin_14\/mux_l2_in_1_:A0 0.152 +27 chanx_left_in[10]:12 chanx_left_in[10]:11 0.0004888393 +28 chanx_left_in[10]:11 mux_bottom_ipin_0\/mux_l2_in_1_:A0 0.152 +29 chanx_left_in[10]:10 chanx_left_in[10]:9 0.0045 +30 chanx_left_in[10]:9 chanx_left_in[10]:8 0.001741071 +31 chanx_left_in[10]:7 chanx_left_in[10]:6 0.0004888393 +32 chanx_left_in[10]:8 chanx_left_in[10]:7 0.0045 +33 chanx_left_in[10]:6 mux_top_ipin_0\/mux_l2_in_1_:A0 0.152 +34 chanx_left_in[10]:35 chanx_left_in[10]:34 0.002377232 +35 chanx_left_in[10]:36 chanx_left_in[10]:35 0.00341 +36 chanx_left_in[10]:38 chanx_left_in[10]:37 0.0001065333 +37 chanx_left_in[10]:37 chanx_left_in[10]:36 0.005620025 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[3] 0.001420277 //LENGTH 10.940 LUMPCC 0.0001256443 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 52.600 49.640 +*I mux_bottom_ipin_5\/mux_l4_in_0_:S I *L 0.00357 *C 49.780 52.700 +*I mem_bottom_ipin_5\/FTB_4__43:A I *L 0.001746 *C 49.680 47.600 +*N mux_tree_tapbuf_size10_3_sram[3]:3 *C 49.718 47.600 +*N mux_tree_tapbuf_size10_3_sram[3]:4 *C 50.095 47.600 +*N mux_tree_tapbuf_size10_3_sram[3]:5 *C 50.140 47.645 +*N mux_tree_tapbuf_size10_3_sram[3]:6 *C 49.680 52.700 +*N mux_tree_tapbuf_size10_3_sram[3]:7 *C 49.680 52.655 +*N mux_tree_tapbuf_size10_3_sram[3]:8 *C 49.680 50.660 +*N mux_tree_tapbuf_size10_3_sram[3]:9 *C 50.140 50.660 +*N mux_tree_tapbuf_size10_3_sram[3]:10 *C 50.600 50.660 +*N mux_tree_tapbuf_size10_3_sram[3]:11 *C 50.600 49.685 +*N mux_tree_tapbuf_size10_3_sram[3]:12 *C 50.645 49.640 +*N mux_tree_tapbuf_size10_3_sram[3]:13 *C 52.562 49.640 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_5\/FTB_4__43:A 1e-06 +3 mux_tree_tapbuf_size10_3_sram[3]:3 6.332864e-05 +4 mux_tree_tapbuf_size10_3_sram[3]:4 6.332864e-05 +5 mux_tree_tapbuf_size10_3_sram[3]:5 0.0001407255 +6 mux_tree_tapbuf_size10_3_sram[3]:6 3.307833e-05 +7 mux_tree_tapbuf_size10_3_sram[3]:7 0.0001409427 +8 mux_tree_tapbuf_size10_3_sram[3]:8 0.0001688286 +9 mux_tree_tapbuf_size10_3_sram[3]:9 0.0001964973 +10 mux_tree_tapbuf_size10_3_sram[3]:10 8.099883e-05 +11 mux_tree_tapbuf_size10_3_sram[3]:11 5.311289e-05 +12 mux_tree_tapbuf_size10_3_sram[3]:12 0.0001753954 +13 mux_tree_tapbuf_size10_3_sram[3]:13 0.0001753954 +14 mux_tree_tapbuf_size10_3_sram[3]:11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.187124e-05 +15 mux_tree_tapbuf_size10_3_sram[3]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.962832e-06 +16 mux_tree_tapbuf_size10_3_sram[3]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.49881e-05 +17 mux_tree_tapbuf_size10_3_sram[3]:8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.962832e-06 +18 mux_tree_tapbuf_size10_3_sram[3]:9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.49881e-05 +19 mux_tree_tapbuf_size10_3_sram[3]:10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.187124e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_3_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_3_sram[3]:12 mux_tree_tapbuf_size10_3_sram[3]:11 0.0045 +2 mux_tree_tapbuf_size10_3_sram[3]:11 mux_tree_tapbuf_size10_3_sram[3]:10 0.0008705357 +3 mux_tree_tapbuf_size10_3_sram[3]:13 mux_tree_tapbuf_size10_3_sram[3]:12 0.001712054 +4 mux_tree_tapbuf_size10_3_sram[3]:6 mux_bottom_ipin_5\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_3_sram[3]:7 mux_tree_tapbuf_size10_3_sram[3]:6 0.0045 +6 mux_tree_tapbuf_size10_3_sram[3]:4 mux_tree_tapbuf_size10_3_sram[3]:3 0.0003370536 +7 mux_tree_tapbuf_size10_3_sram[3]:5 mux_tree_tapbuf_size10_3_sram[3]:4 0.0045 +8 mux_tree_tapbuf_size10_3_sram[3]:3 mem_bottom_ipin_5\/FTB_4__43:A 0.152 +9 mux_tree_tapbuf_size10_3_sram[3]:8 mux_tree_tapbuf_size10_3_sram[3]:7 0.00178125 +10 mux_tree_tapbuf_size10_3_sram[3]:9 mux_tree_tapbuf_size10_3_sram[3]:8 0.0004107143 +11 mux_tree_tapbuf_size10_3_sram[3]:9 mux_tree_tapbuf_size10_3_sram[3]:5 0.002691964 +12 mux_tree_tapbuf_size10_3_sram[3]:10 mux_tree_tapbuf_size10_3_sram[3]:9 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[1] 0.004190001 //LENGTH 31.045 LUMPCC 0.000398002 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.585 31.280 +*I mux_bottom_ipin_12\/mux_l2_in_0_:S I *L 0.00357 *C 59.240 30.990 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.055 37.060 +*I mux_bottom_ipin_12\/mux_l2_in_1_:S I *L 0.00357 *C 62.920 28.560 +*I mux_bottom_ipin_12\/mux_l2_in_3_:S I *L 0.00357 *C 66.340 28.855 +*I mux_bottom_ipin_12\/mux_l2_in_2_:S I *L 0.00357 *C 70.480 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:6 *C 70.443 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:7 *C 66.340 28.855 +*N mux_tree_tapbuf_size10_6_sram[1]:8 *C 66.303 28.560 +*N mux_tree_tapbuf_size10_6_sram[1]:9 *C 62.958 28.560 +*N mux_tree_tapbuf_size10_6_sram[1]:10 *C 64.400 28.560 +*N mux_tree_tapbuf_size10_6_sram[1]:11 *C 64.400 28.605 +*N mux_tree_tapbuf_size10_6_sram[1]:12 *C 64.400 30.555 +*N mux_tree_tapbuf_size10_6_sram[1]:13 *C 64.400 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:14 *C 59.055 37.060 +*N mux_tree_tapbuf_size10_6_sram[1]:15 *C 59.340 37.060 +*N mux_tree_tapbuf_size10_6_sram[1]:16 *C 59.340 37.015 +*N mux_tree_tapbuf_size10_6_sram[1]:17 *C 59.340 30.645 +*N mux_tree_tapbuf_size10_6_sram[1]:18 *C 59.385 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:19 *C 59.240 30.990 +*N mux_tree_tapbuf_size10_6_sram[1]:20 *C 59.183 31.280 +*N mux_tree_tapbuf_size10_6_sram[1]:21 *C 54.623 31.280 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_12\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_12\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size10_6_sram[1]:6 0.0003430013 +7 mux_tree_tapbuf_size10_6_sram[1]:7 5.943187e-05 +8 mux_tree_tapbuf_size10_6_sram[1]:8 0.0001556556 +9 mux_tree_tapbuf_size10_6_sram[1]:9 9.766164e-05 +10 mux_tree_tapbuf_size10_6_sram[1]:10 0.0002671766 +11 mux_tree_tapbuf_size10_6_sram[1]:11 0.0001307842 +12 mux_tree_tapbuf_size10_6_sram[1]:12 0.0001307842 +13 mux_tree_tapbuf_size10_6_sram[1]:13 0.0007365908 +14 mux_tree_tapbuf_size10_6_sram[1]:14 4.606194e-05 +15 mux_tree_tapbuf_size10_6_sram[1]:15 5.024402e-05 +16 mux_tree_tapbuf_size10_6_sram[1]:16 0.0003749112 +17 mux_tree_tapbuf_size10_6_sram[1]:17 0.0003749112 +18 mux_tree_tapbuf_size10_6_sram[1]:18 0.0003894708 +19 mux_tree_tapbuf_size10_6_sram[1]:19 0.0001049186 +20 mux_tree_tapbuf_size10_6_sram[1]:20 0.0002786731 +21 mux_tree_tapbuf_size10_6_sram[1]:21 0.0002457216 +22 mux_tree_tapbuf_size10_6_sram[1]:21 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.253076e-05 +23 mux_tree_tapbuf_size10_6_sram[1]:20 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.253076e-05 +24 mux_tree_tapbuf_size10_6_sram[1]:13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001164702 +25 mux_tree_tapbuf_size10_6_sram[1]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001164702 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_6_sram[1]:21 0.152 +1 mux_tree_tapbuf_size10_6_sram[1]:10 mux_tree_tapbuf_size10_6_sram[1]:9 0.001287946 +2 mux_tree_tapbuf_size10_6_sram[1]:10 mux_tree_tapbuf_size10_6_sram[1]:8 0.001698661 +3 mux_tree_tapbuf_size10_6_sram[1]:11 mux_tree_tapbuf_size10_6_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size10_6_sram[1]:13 mux_tree_tapbuf_size10_6_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size10_6_sram[1]:13 mux_tree_tapbuf_size10_6_sram[1]:6 0.005395089 +6 mux_tree_tapbuf_size10_6_sram[1]:12 mux_tree_tapbuf_size10_6_sram[1]:11 0.001741072 +7 mux_tree_tapbuf_size10_6_sram[1]:9 mux_bottom_ipin_12\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_6_sram[1]:6 mux_bottom_ipin_12\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size10_6_sram[1]:19 mux_bottom_ipin_12\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_6_sram[1]:19 mux_tree_tapbuf_size10_6_sram[1]:18 0.0003482143 +11 mux_tree_tapbuf_size10_6_sram[1]:7 mux_bottom_ipin_12\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_6_sram[1]:18 mux_tree_tapbuf_size10_6_sram[1]:17 0.0045 +13 mux_tree_tapbuf_size10_6_sram[1]:18 mux_tree_tapbuf_size10_6_sram[1]:13 0.004477679 +14 mux_tree_tapbuf_size10_6_sram[1]:17 mux_tree_tapbuf_size10_6_sram[1]:16 0.0056875 +15 mux_tree_tapbuf_size10_6_sram[1]:15 mux_tree_tapbuf_size10_6_sram[1]:14 0.0001548913 +16 mux_tree_tapbuf_size10_6_sram[1]:16 mux_tree_tapbuf_size10_6_sram[1]:15 0.0045 +17 mux_tree_tapbuf_size10_6_sram[1]:14 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size10_6_sram[1]:21 mux_tree_tapbuf_size10_6_sram[1]:20 0.004071428 +19 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:19 0.0001686047 +20 mux_tree_tapbuf_size10_6_sram[1]:8 mux_tree_tapbuf_size10_6_sram[1]:7 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.0009826345 //LENGTH 7.260 LUMPCC 0.0001174411 DR + +*CONN +*I mem_bottom_ipin_0\/FTB_1__40:X O *L 0 *C 69.680 42.500 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 73.765 44.540 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 73.728 44.540 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 69.505 44.540 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 69.460 44.495 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 69.460 42.545 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 69.460 42.500 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 69.680 42.500 + +*CAP +0 mem_bottom_ipin_0\/FTB_1__40:X 1e-06 +1 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0002862194 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0002862194 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 9.3242e-05 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 9.3242e-05 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 5.37261e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 5.05444e-05 +8 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mux_tree_tapbuf_size10_6_sram[3]:3 2.833611e-05 +9 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_6_sram[3]:4 2.833611e-05 +10 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_6_sram[3]:5 3.038442e-05 +11 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_6_sram[3]:6 3.038442e-05 + +*RES +0 mem_bottom_ipin_0\/FTB_1__40:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.003770089 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0001195652 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[2] 0.003382387 //LENGTH 27.230 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.485 11.900 +*I mux_bottom_ipin_2\/mux_l3_in_1_:S I *L 0.00357 *C 32.560 20.400 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 28.235 26.180 +*I mux_bottom_ipin_2\/mux_l3_in_0_:S I *L 0.00357 *C 35.060 20.110 +*N mux_tree_tapbuf_size8_0_sram[2]:4 *C 35.060 20.110 +*N mux_tree_tapbuf_size8_0_sram[2]:5 *C 34.973 20.400 +*N mux_tree_tapbuf_size8_0_sram[2]:6 *C 28.235 26.180 +*N mux_tree_tapbuf_size8_0_sram[2]:7 *C 28.520 26.180 +*N mux_tree_tapbuf_size8_0_sram[2]:8 *C 28.520 26.135 +*N mux_tree_tapbuf_size8_0_sram[2]:9 *C 28.520 22.825 +*N mux_tree_tapbuf_size8_0_sram[2]:10 *C 28.565 22.780 +*N mux_tree_tapbuf_size8_0_sram[2]:11 *C 32.615 22.780 +*N mux_tree_tapbuf_size8_0_sram[2]:12 *C 32.660 22.735 +*N mux_tree_tapbuf_size8_0_sram[2]:13 *C 32.660 20.785 +*N mux_tree_tapbuf_size8_0_sram[2]:14 *C 32.660 20.740 +*N mux_tree_tapbuf_size8_0_sram[2]:15 *C 32.660 20.400 +*N mux_tree_tapbuf_size8_0_sram[2]:16 *C 35.017 20.370 +*N mux_tree_tapbuf_size8_0_sram[2]:17 *C 34.960 20.355 +*N mux_tree_tapbuf_size8_0_sram[2]:18 *C 34.960 11.945 +*N mux_tree_tapbuf_size8_0_sram[2]:19 *C 35.005 11.900 +*N mux_tree_tapbuf_size8_0_sram[2]:20 *C 38.448 11.900 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_2\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_0_sram[2]:4 5.999819e-05 +5 mux_tree_tapbuf_size8_0_sram[2]:5 3.080164e-05 +6 mux_tree_tapbuf_size8_0_sram[2]:6 5.55566e-05 +7 mux_tree_tapbuf_size8_0_sram[2]:7 5.966557e-05 +8 mux_tree_tapbuf_size8_0_sram[2]:8 0.0001956123 +9 mux_tree_tapbuf_size8_0_sram[2]:9 0.0001956123 +10 mux_tree_tapbuf_size8_0_sram[2]:10 0.0002575726 +11 mux_tree_tapbuf_size8_0_sram[2]:11 0.0002575726 +12 mux_tree_tapbuf_size8_0_sram[2]:12 0.0001376731 +13 mux_tree_tapbuf_size8_0_sram[2]:13 0.0001376731 +14 mux_tree_tapbuf_size8_0_sram[2]:14 6.50939e-05 +15 mux_tree_tapbuf_size8_0_sram[2]:15 0.0002272106 +16 mux_tree_tapbuf_size8_0_sram[2]:16 0.0002518363 +17 mux_tree_tapbuf_size8_0_sram[2]:17 0.0005016302 +18 mux_tree_tapbuf_size8_0_sram[2]:18 0.0005016302 +19 mux_tree_tapbuf_size8_0_sram[2]:19 0.0002216238 +20 mux_tree_tapbuf_size8_0_sram[2]:20 0.0002216238 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_0_sram[2]:20 0.152 +1 mux_tree_tapbuf_size8_0_sram[2]:20 mux_tree_tapbuf_size8_0_sram[2]:19 0.003073661 +2 mux_tree_tapbuf_size8_0_sram[2]:19 mux_tree_tapbuf_size8_0_sram[2]:18 0.0045 +3 mux_tree_tapbuf_size8_0_sram[2]:18 mux_tree_tapbuf_size8_0_sram[2]:17 0.007508928 +4 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:15 0.002104911 +5 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:5 4.017858e-05 +6 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:4 0.000112069 +7 mux_tree_tapbuf_size8_0_sram[2]:17 mux_tree_tapbuf_size8_0_sram[2]:16 0.0045 +8 mux_tree_tapbuf_size8_0_sram[2]:4 mux_bottom_ipin_2\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_0_sram[2]:15 mux_bottom_ipin_2\/mux_l3_in_1_:S 0.152 +10 mux_tree_tapbuf_size8_0_sram[2]:15 mux_tree_tapbuf_size8_0_sram[2]:14 0.0001847826 +11 mux_tree_tapbuf_size8_0_sram[2]:6 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size8_0_sram[2]:7 mux_tree_tapbuf_size8_0_sram[2]:6 0.0001548913 +13 mux_tree_tapbuf_size8_0_sram[2]:8 mux_tree_tapbuf_size8_0_sram[2]:7 0.0045 +14 mux_tree_tapbuf_size8_0_sram[2]:10 mux_tree_tapbuf_size8_0_sram[2]:9 0.0045 +15 mux_tree_tapbuf_size8_0_sram[2]:9 mux_tree_tapbuf_size8_0_sram[2]:8 0.002955357 +16 mux_tree_tapbuf_size8_0_sram[2]:11 mux_tree_tapbuf_size8_0_sram[2]:10 0.003616071 +17 mux_tree_tapbuf_size8_0_sram[2]:12 mux_tree_tapbuf_size8_0_sram[2]:11 0.0045 +18 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:13 0.0045 +19 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:12 0.001741071 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[0] 0.004514768 //LENGTH 36.625 LUMPCC 0.0006275597 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 37.565 31.620 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 38.355 39.100 +*I mux_bottom_ipin_3\/mux_l1_in_0_:S I *L 0.00357 *C 39.000 52.360 +*N mux_tree_tapbuf_size8_1_sram[0]:3 *C 38.962 52.360 +*N mux_tree_tapbuf_size8_1_sram[0]:4 *C 37.765 52.360 +*N mux_tree_tapbuf_size8_1_sram[0]:5 *C 37.720 52.315 +*N mux_tree_tapbuf_size8_1_sram[0]:6 *C 38.392 39.100 +*N mux_tree_tapbuf_size8_1_sram[0]:7 *C 41.815 39.100 +*N mux_tree_tapbuf_size8_1_sram[0]:8 *C 41.860 39.055 +*N mux_tree_tapbuf_size8_1_sram[0]:9 *C 41.860 34.045 +*N mux_tree_tapbuf_size8_1_sram[0]:10 *C 41.815 34.000 +*N mux_tree_tapbuf_size8_1_sram[0]:11 *C 37.765 34.000 +*N mux_tree_tapbuf_size8_1_sram[0]:12 *C 37.720 34.000 +*N mux_tree_tapbuf_size8_1_sram[0]:13 *C 37.720 31.665 +*N mux_tree_tapbuf_size8_1_sram[0]:14 *C 37.720 31.620 +*N mux_tree_tapbuf_size8_1_sram[0]:15 *C 37.565 31.620 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_3\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001264718 +4 mux_tree_tapbuf_size8_1_sram[0]:4 0.0001264718 +5 mux_tree_tapbuf_size8_1_sram[0]:5 0.0009704714 +6 mux_tree_tapbuf_size8_1_sram[0]:6 0.0002740402 +7 mux_tree_tapbuf_size8_1_sram[0]:7 0.0002740402 +8 mux_tree_tapbuf_size8_1_sram[0]:8 0.0002253392 +9 mux_tree_tapbuf_size8_1_sram[0]:9 0.0002253392 +10 mux_tree_tapbuf_size8_1_sram[0]:10 0.0001446131 +11 mux_tree_tapbuf_size8_1_sram[0]:11 0.0001446131 +12 mux_tree_tapbuf_size8_1_sram[0]:12 0.00113346 +13 mux_tree_tapbuf_size8_1_sram[0]:13 0.0001316379 +14 mux_tree_tapbuf_size8_1_sram[0]:14 5.595585e-05 +15 mux_tree_tapbuf_size8_1_sram[0]:15 5.175456e-05 +16 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 8.52779e-05 +17 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 1.234971e-07 +18 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.0001487204 +19 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 8.52779e-05 +20 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 1.234971e-07 +21 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.0001487204 +22 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 7.965806e-05 +23 mux_tree_tapbuf_size8_1_sram[0]:8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 7.965806e-05 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_1_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_1_sram[0]:4 mux_tree_tapbuf_size8_1_sram[0]:3 0.001069196 +2 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_1_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size8_1_sram[0]:3 mux_bottom_ipin_3\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_1_sram[0]:10 0.003616072 +5 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_1_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_1_sram[0]:5 0.01635268 +7 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:8 0.004473214 +9 mux_tree_tapbuf_size8_1_sram[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 0.003055804 +10 mux_tree_tapbuf_size8_1_sram[0]:8 mux_tree_tapbuf_size8_1_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size8_1_sram[0]:6 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size8_1_sram[0]:14 mux_tree_tapbuf_size8_1_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size8_1_sram[0]:13 mux_tree_tapbuf_size8_1_sram[0]:12 0.002084822 +14 mux_tree_tapbuf_size8_1_sram[0]:15 mux_tree_tapbuf_size8_1_sram[0]:14 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[3] 0.001082005 //LENGTH 9.435 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 26.525 69.360 +*I mux_bottom_ipin_7\/mux_l4_in_0_:S I *L 0.00357 *C 24.020 63.920 +*I mem_bottom_ipin_7\/FTB_13__52:A I *L 0.001746 *C 23.460 66.640 +*N mux_tree_tapbuf_size8_3_sram[3]:3 *C 23.498 66.640 +*N mux_tree_tapbuf_size8_3_sram[3]:4 *C 23.920 63.920 +*N mux_tree_tapbuf_size8_3_sram[3]:5 *C 23.920 63.965 +*N mux_tree_tapbuf_size8_3_sram[3]:6 *C 23.920 66.595 +*N mux_tree_tapbuf_size8_3_sram[3]:7 *C 23.920 66.640 +*N mux_tree_tapbuf_size8_3_sram[3]:8 *C 26.175 66.640 +*N mux_tree_tapbuf_size8_3_sram[3]:9 *C 26.220 66.685 +*N mux_tree_tapbuf_size8_3_sram[3]:10 *C 26.220 69.315 +*N mux_tree_tapbuf_size8_3_sram[3]:11 *C 26.220 69.360 +*N mux_tree_tapbuf_size8_3_sram[3]:12 *C 26.525 69.360 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_7\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_7\/FTB_13__52:A 1e-06 +3 mux_tree_tapbuf_size8_3_sram[3]:3 3.167211e-05 +4 mux_tree_tapbuf_size8_3_sram[3]:4 3.029649e-05 +5 mux_tree_tapbuf_size8_3_sram[3]:5 0.0001489109 +6 mux_tree_tapbuf_size8_3_sram[3]:6 0.0001489109 +7 mux_tree_tapbuf_size8_3_sram[3]:7 0.000190751 +8 mux_tree_tapbuf_size8_3_sram[3]:8 0.0001287824 +9 mux_tree_tapbuf_size8_3_sram[3]:9 0.00015145 +10 mux_tree_tapbuf_size8_3_sram[3]:10 0.00015145 +11 mux_tree_tapbuf_size8_3_sram[3]:11 4.930262e-05 +12 mux_tree_tapbuf_size8_3_sram[3]:12 4.747849e-05 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_3_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:6 0.0045 +2 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:3 0.0003772322 +3 mux_tree_tapbuf_size8_3_sram[3]:6 mux_tree_tapbuf_size8_3_sram[3]:5 0.002348214 +4 mux_tree_tapbuf_size8_3_sram[3]:4 mux_bottom_ipin_7\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_3_sram[3]:5 mux_tree_tapbuf_size8_3_sram[3]:4 0.0045 +6 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[3]:7 0.002013393 +7 mux_tree_tapbuf_size8_3_sram[3]:9 mux_tree_tapbuf_size8_3_sram[3]:8 0.0045 +8 mux_tree_tapbuf_size8_3_sram[3]:11 mux_tree_tapbuf_size8_3_sram[3]:10 0.0045 +9 mux_tree_tapbuf_size8_3_sram[3]:10 mux_tree_tapbuf_size8_3_sram[3]:9 0.002348214 +10 mux_tree_tapbuf_size8_3_sram[3]:12 mux_tree_tapbuf_size8_3_sram[3]:11 0.0001657609 +11 mux_tree_tapbuf_size8_3_sram[3]:3 mem_bottom_ipin_7\/FTB_13__52:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[0] 0.002570705 //LENGTH 21.585 LUMPCC 0.0002809761 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 78.965 39.100 +*I mux_bottom_ipin_14\/mux_l1_in_0_:S I *L 0.00357 *C 72.120 25.840 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.155 26.180 +*N mux_tree_tapbuf_size8_6_sram[0]:3 *C 75.155 26.180 +*N mux_tree_tapbuf_size8_6_sram[0]:4 *C 75.373 26.520 +*N mux_tree_tapbuf_size8_6_sram[0]:5 *C 72.120 25.840 +*N mux_tree_tapbuf_size8_6_sram[0]:6 *C 72.220 25.885 +*N mux_tree_tapbuf_size8_6_sram[0]:7 *C 72.220 26.475 +*N mux_tree_tapbuf_size8_6_sram[0]:8 *C 72.265 26.520 +*N mux_tree_tapbuf_size8_6_sram[0]:9 *C 75.395 26.513 +*N mux_tree_tapbuf_size8_6_sram[0]:10 *C 75.440 26.565 +*N mux_tree_tapbuf_size8_6_sram[0]:11 *C 75.440 39.055 +*N mux_tree_tapbuf_size8_6_sram[0]:12 *C 75.485 39.100 +*N mux_tree_tapbuf_size8_6_sram[0]:13 *C 78.928 39.100 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_14\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_6_sram[0]:3 5.012172e-05 +4 mux_tree_tapbuf_size8_6_sram[0]:4 1.642488e-05 +5 mux_tree_tapbuf_size8_6_sram[0]:5 2.801004e-05 +6 mux_tree_tapbuf_size8_6_sram[0]:6 5.988952e-05 +7 mux_tree_tapbuf_size8_6_sram[0]:7 5.988952e-05 +8 mux_tree_tapbuf_size8_6_sram[0]:8 0.0002190735 +9 mux_tree_tapbuf_size8_6_sram[0]:9 0.0002581723 +10 mux_tree_tapbuf_size8_6_sram[0]:10 0.0005796222 +11 mux_tree_tapbuf_size8_6_sram[0]:11 0.0005796222 +12 mux_tree_tapbuf_size8_6_sram[0]:12 0.0002179517 +13 mux_tree_tapbuf_size8_6_sram[0]:13 0.0002179517 +14 mux_tree_tapbuf_size8_6_sram[0]:10 chanx_left_in[0]:30 0.0001394194 +15 mux_tree_tapbuf_size8_6_sram[0]:10 chanx_left_in[0]:31 1.068636e-06 +16 mux_tree_tapbuf_size8_6_sram[0]:11 chanx_left_in[0]:22 0.0001394194 +17 mux_tree_tapbuf_size8_6_sram[0]:11 chanx_left_in[0]:30 1.068636e-06 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_6_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_6_sram[0]:8 mux_tree_tapbuf_size8_6_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size8_6_sram[0]:7 mux_tree_tapbuf_size8_6_sram[0]:6 0.0005267857 +3 mux_tree_tapbuf_size8_6_sram[0]:5 mux_bottom_ipin_14\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_6_sram[0]:6 mux_tree_tapbuf_size8_6_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:8 0.002794643 +6 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:4 2.008929e-05 +7 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:3 0.0001807065 +8 mux_tree_tapbuf_size8_6_sram[0]:10 mux_tree_tapbuf_size8_6_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size8_6_sram[0]:12 mux_tree_tapbuf_size8_6_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size8_6_sram[0]:11 mux_tree_tapbuf_size8_6_sram[0]:10 0.01115179 +11 mux_tree_tapbuf_size8_6_sram[0]:13 mux_tree_tapbuf_size8_6_sram[0]:12 0.003073661 +12 mux_tree_tapbuf_size8_6_sram[0]:3 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_3_ccff_tail[0] 0.005065972 //LENGTH 39.500 LUMPCC 0.001281847 DR + +*CONN +*I mem_bottom_ipin_7\/FTB_13__52:X O *L 0 *C 20.465 66.640 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 21.790 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 *C 19.530 66.640 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 *C 21.790 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 *C 22.080 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 *C 22.080 31.665 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 *C 22.080 35.983 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 *C 22.073 36.040 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 *C 20.260 36.040 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 *C 20.240 36.047 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 *C 20.240 66.633 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 *C 20.238 66.640 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 *C 20.240 66.640 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 *C 20.240 66.640 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 *C 20.465 66.640 + +*CAP +0 mem_bottom_ipin_7\/FTB_13__52:X 1e-06 +1 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 0.0001226926 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 4.504244e-05 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 4.94047e-05 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.0002408097 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.0002408097 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.0001619194 +8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 0.0001619194 +9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.001249906 +10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.001249906 +11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 0.0001226926 +12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 3.146434e-05 +13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 5.294539e-05 +14 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 5.261344e-05 +15 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 chanx_left_in[0]:59 1.355525e-05 +16 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 chanx_left_in[0]:60 1.355525e-05 +17 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 chanx_left_in[0]:56 5.481922e-06 +18 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 chanx_left_in[0]:61 9.483726e-06 +19 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 chanx_left_in[0]:61 5.481922e-06 +20 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 chanx_left_in[0]:62 9.483726e-06 +21 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 chanx_left_in[0]:64 0.0003538138 +22 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 chanx_left_in[0]:65 0.0003538138 +23 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0002585891 +24 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002585891 + +*RES +0 mem_bottom_ipin_7\/FTB_13__52:X mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 0.152 +1 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 0.0001576087 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.0045 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.00385491 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.00341 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.0002839583 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 0.00341 +8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.00341 +9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 0.0001039141 +10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.00479165 +11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 0.00341 +12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 0.0045 +13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 0.0001222826 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005285206 //LENGTH 4.100 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_2_:X O *L 0 *C 60.435 59.160 +*I mux_bottom_ipin_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 59.340 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 59.340 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 59.340 61.495 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 59.340 59.205 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 59.385 59.160 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 60.398 59.160 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.702661e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001513267 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001513267 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.342031e-05 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.342031e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_2_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009040179 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002044643 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_1_:A1 0.152 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0008025648 //LENGTH 6.905 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l4_in_0_:X O *L 0 *C 44.795 67.320 +*I mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 42.975 71.880 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 43.013 71.788 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 44.575 71.740 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 44.620 71.695 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 44.620 67.365 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 44.620 67.320 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 44.795 67.320 + +*CAP +0 mux_bottom_ipin_1\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.911173e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 9.911173e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002503933 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002503933 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.285446e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.870024e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l4_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.001395089 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.003866072 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004801766 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_1_:X O *L 0 *C 59.055 53.720 +*I mux_bottom_ipin_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.710 55.420 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.710 55.420 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 58.880 55.420 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.880 55.375 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.880 53.765 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.880 53.720 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 59.055 53.720 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.8601e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.469112e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001180392 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001180392 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.671515e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.209099e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001756187 //LENGTH 13.485 LUMPCC 0.000446437 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_2_:X O *L 0 *C 6.615 26.520 +*I mux_bottom_ipin_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 9.200 36.380 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.200 36.380 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 9.200 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 7.405 36.040 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 7.360 35.995 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 7.360 26.565 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 7.315 26.520 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 6.653 26.520 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.447451e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001636457 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001367467 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004041312 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004041312 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.231042e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 7.231042e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[0]:20 0.0001148268 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[0]:17 6.186601e-07 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[0]:19 0.0001148268 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[0]:18 6.186601e-07 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:14 7.089363e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:15 3.687948e-05 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_4_sram[1]:8 3.687948e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_4_sram[1]:15 7.089363e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_2_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0005915179 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.008419643 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.001602679 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_1_:A1 0.152 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001482178 //LENGTH 11.325 LUMPCC 0.0002942864 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l3_in_0_:X O *L 0 *C 12.135 58.140 +*I mux_bottom_ipin_9\/mux_l4_in_0_:A1 I *L 0.00198 *C 10.580 66.980 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 10.617 66.980 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 11.455 66.980 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 11.500 66.935 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 11.500 58.185 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 11.545 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 12.098 58.140 + +*CAP +0 mux_bottom_ipin_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.398937e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.398937e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004397271 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0004397271 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.922939e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.922939e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 6.709577e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.264011e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 6.709577e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.264011e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 ropt_net_157:9 3.865012e-08 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 ropt_net_157:10 3.865012e-08 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_157:7 6.736869e-05 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 ropt_net_157:8 6.736869e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l3_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0078125 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0007477679 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_9\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003405207 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_1_:X O *L 0 *C 80.215 58.820 +*I mux_bottom_ipin_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 78.030 58.820 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 78.068 58.820 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 80.178 58.820 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001692603 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001692603 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001883929 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005640876 //LENGTH 4.265 LUMPCC 0 DR + +*CONN +*I mux_top_ipin_0\/mux_l1_in_1_:X O *L 0 *C 94.015 20.060 +*I mux_top_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 93.210 17.340 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 93.248 17.340 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 93.795 17.340 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 93.840 17.385 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 93.840 20.015 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 93.840 20.060 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 94.015 20.060 + +*CAP +0 mux_top_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_top_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.724135e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.724135e-05 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001648705 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001648705 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.023106e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.763293e-05 + +*RES +0 mux_top_ipin_0\/mux_l1_in_1_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004385674 //LENGTH 2.910 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_1_:X O *L 0 *C 36.975 22.440 +*I mux_bottom_ipin_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 36.170 21.080 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 36.170 21.080 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 36.340 21.080 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 36.340 21.125 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 36.340 22.395 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 36.385 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 36.938 22.440 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.074307e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.246375e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.408022e-05 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.408022e-05 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.260005e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.260005e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_1_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001206677 //LENGTH 8.305 LUMPCC 0.0002575986 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_0_:X O *L 0 *C 50.775 20.400 +*I mux_bottom_ipin_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 46.460 23.460 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 46.498 23.460 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 47.335 23.460 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 47.380 23.415 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 47.380 20.445 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 47.425 20.400 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 50.738 20.400 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.967991e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.967991e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001880042 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001880042 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000185855 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000185855 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[2]:45 0.0001287993 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[2]:46 0.0001287993 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002957589 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0007477679 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009020447 //LENGTH 6.680 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_3_:X O *L 0 *C 27.775 56.100 +*I mux_bottom_ipin_7\/mux_l3_in_1_:A0 I *L 0.001631 *C 24.555 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 24.593 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 27.555 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 27.600 58.775 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 27.600 56.145 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 27.600 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 27.775 56.100 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002128555 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002128555 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001719073 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001719073 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.208479e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.843437e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_3_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002645089 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001206734 //LENGTH 9.060 LUMPCC 0.0001668038 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_1_:X O *L 0 *C 27.775 53.040 +*I mux_bottom_ipin_11\/mux_l3_in_0_:A0 I *L 0.001631 *C 24.555 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 24.593 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 27.555 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 27.600 47.985 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 27.600 52.995 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 27.600 53.040 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 27.775 53.040 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001612412 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001612412 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002990484 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002990484 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.867406e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.867722e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size8_5_sram[2]:5 8.340191e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size8_5_sram[2]:6 8.340191e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_1_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002645089 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004473214 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005702041 //LENGTH 3.870 LUMPCC 0.0001452669 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_0_:X O *L 0 *C 84.815 56.100 +*I mux_bottom_ipin_15\/mux_l3_in_0_:A1 I *L 0.00198 *C 86.020 58.140 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 86.020 58.140 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 86.020 58.095 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 86.020 56.145 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.975 56.100 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 84.853 56.100 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.39817e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001315641 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001315641 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.291358e-05 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.291358e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[3]:22 1.640045e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[3]:26 1.109224e-06 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[3]:23 5.51238e-05 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[3]:21 1.640045e-05 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[3]:27 1.109224e-06 +12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[3]:28 5.51238e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001741072 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001002232 + +*END + +*D_NET ropt_net_146 0.0006250698 //LENGTH 5.345 LUMPCC 0 DR + +*CONN +*I FTB_9__8:X O *L 0 *C 98.900 30.600 +*I ropt_mt_inst_746:A I *L 0.001766 *C 97.825 34.000 +*N ropt_net_146:2 *C 97.863 34.000 +*N ropt_net_146:3 *C 98.855 34.000 +*N ropt_net_146:4 *C 98.900 33.955 +*N ropt_net_146:5 *C 98.900 30.985 +*N ropt_net_146:6 *C 98.900 30.940 +*N ropt_net_146:7 *C 98.900 30.600 + +*CAP +0 FTB_9__8:X 1e-06 +1 ropt_mt_inst_746:A 1e-06 +2 ropt_net_146:2 7.3041e-05 +3 ropt_net_146:3 7.3041e-05 +4 ropt_net_146:4 0.0001770759 +5 ropt_net_146:5 0.0001770759 +6 ropt_net_146:6 6.344565e-05 +7 ropt_net_146:7 5.939038e-05 + +*RES +0 FTB_9__8:X ropt_net_146:7 0.152 +1 ropt_net_146:2 ropt_mt_inst_746:A 0.152 +2 ropt_net_146:3 ropt_net_146:2 0.0008861608 +3 ropt_net_146:4 ropt_net_146:3 0.0045 +4 ropt_net_146:6 ropt_net_146:5 0.0045 +5 ropt_net_146:5 ropt_net_146:4 0.002651786 +6 ropt_net_146:7 ropt_net_146:6 0.0001465518 + +*END + +*D_NET ropt_net_132 0.0006173517 //LENGTH 5.080 LUMPCC 0 DR + +*CONN +*I FTB_25__24:X O *L 0 *C 7.820 17.000 +*I ropt_mt_inst_731:A I *L 0.001766 *C 7.820 12.240 +*N ropt_net_132:2 *C 7.820 12.240 +*N ropt_net_132:3 *C 7.820 12.285 +*N ropt_net_132:4 *C 7.820 16.955 +*N ropt_net_132:5 *C 7.820 17.000 + +*CAP +0 FTB_25__24:X 1e-06 +1 ropt_mt_inst_731:A 1e-06 +2 ropt_net_132:2 3.694859e-05 +3 ropt_net_132:3 0.0002688178 +4 ropt_net_132:4 0.0002688178 +5 ropt_net_132:5 4.076754e-05 + +*RES +0 FTB_25__24:X ropt_net_132:5 0.152 +1 ropt_net_132:5 ropt_net_132:4 0.0045 +2 ropt_net_132:4 ropt_net_132:3 0.004169643 +3 ropt_net_132:2 ropt_mt_inst_731:A 0.152 +4 ropt_net_132:3 ropt_net_132:2 0.0045 + +*END + +*D_NET chanx_right_out[4] 0.000751883 //LENGTH 6.255 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 98.900 72.760 +*P chanx_right_out[4] O *L 0.7423 *C 102.580 74.870 +*N chanx_right_out[4]:2 *C 102.580 72.805 +*N chanx_right_out[4]:3 *C 102.535 72.760 +*N chanx_right_out[4]:4 *C 98.938 72.760 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 chanx_right_out[4] 0.0001231188 +2 chanx_right_out[4]:2 0.0001231188 +3 chanx_right_out[4]:3 0.0002523227 +4 chanx_right_out[4]:4 0.0002523227 + +*RES +0 ropt_mt_inst_751:X chanx_right_out[4]:4 0.152 +1 chanx_right_out[4]:4 chanx_right_out[4]:3 0.003212054 +2 chanx_right_out[4]:3 chanx_right_out[4]:2 0.0045 +3 chanx_right_out[4]:2 chanx_right_out[4] 0.00184375 + +*END + +*D_NET ropt_net_158 0.001774685 //LENGTH 13.075 LUMPCC 0.0006123543 DR + +*CONN +*I ropt_mt_inst_724:X O *L 0 *C 7.095 42.840 +*I ropt_mt_inst_760:A I *L 0.001766 *C 3.220 50.320 +*N ropt_net_158:2 *C 3.220 50.320 +*N ropt_net_158:3 *C 3.220 50.660 +*N ropt_net_158:4 *C 5.475 50.660 +*N ropt_net_158:5 *C 5.520 50.615 +*N ropt_net_158:6 *C 5.520 42.885 +*N ropt_net_158:7 *C 5.565 42.840 +*N ropt_net_158:8 *C 7.058 42.840 + +*CAP +0 ropt_mt_inst_724:X 1e-06 +1 ropt_mt_inst_760:A 1e-06 +2 ropt_net_158:2 5.834117e-05 +3 ropt_net_158:3 0.0001371649 +4 ropt_net_158:4 0.0001085829 +5 ropt_net_158:5 0.0003058502 +6 ropt_net_158:6 0.0003058502 +7 ropt_net_158:7 0.0001222711 +8 ropt_net_158:8 0.0001222711 +9 ropt_net_158:5 chanx_right_in[11]:15 0.0002072458 +10 ropt_net_158:6 chanx_right_in[11]:14 0.0002072458 +11 ropt_net_158:4 chanx_left_out[7]:6 8.852695e-05 +12 ropt_net_158:5 chanx_left_out[7]:2 1.040436e-05 +13 ropt_net_158:6 chanx_left_out[7] 1.040436e-05 +14 ropt_net_158:3 chanx_left_out[7]:5 8.852695e-05 + +*RES +0 ropt_mt_inst_724:X ropt_net_158:8 0.152 +1 ropt_net_158:2 ropt_mt_inst_760:A 0.152 +2 ropt_net_158:4 ropt_net_158:3 0.002013393 +3 ropt_net_158:5 ropt_net_158:4 0.0045 +4 ropt_net_158:7 ropt_net_158:6 0.0045 +5 ropt_net_158:6 ropt_net_158:5 0.006901786 +6 ropt_net_158:8 ropt_net_158:7 0.00133259 +7 ropt_net_158:3 ropt_net_158:2 0.0003035715 + +*END + +*D_NET ropt_net_151 0.001310902 //LENGTH 9.525 LUMPCC 0.000297879 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 7.095 36.720 +*I ropt_mt_inst_750:A I *L 0.001767 *C 3.220 34.000 +*N ropt_net_151:2 *C 3.258 34.000 +*N ropt_net_151:3 *C 3.635 34.000 +*N ropt_net_151:4 *C 3.680 33.955 +*N ropt_net_151:5 *C 3.680 33.365 +*N ropt_net_151:6 *C 3.725 33.320 +*N ropt_net_151:7 *C 5.475 33.320 +*N ropt_net_151:8 *C 5.520 33.365 +*N ropt_net_151:9 *C 5.520 36.675 +*N ropt_net_151:10 *C 5.565 36.720 +*N ropt_net_151:11 *C 7.058 36.720 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 ropt_mt_inst_750:A 1e-06 +2 ropt_net_151:2 5.575442e-05 +3 ropt_net_151:3 5.575442e-05 +4 ropt_net_151:4 7.360505e-05 +5 ropt_net_151:5 7.360505e-05 +6 ropt_net_151:6 0.0001378501 +7 ropt_net_151:7 0.0001378501 +8 ropt_net_151:8 0.0001542958 +9 ropt_net_151:9 0.0001542958 +10 ropt_net_151:10 8.400616e-05 +11 ropt_net_151:11 8.400616e-05 +12 ropt_net_151:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.735754e-05 +13 ropt_net_151:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.158195e-05 +14 ropt_net_151:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.735754e-05 +15 ropt_net_151:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.158195e-05 + +*RES +0 ropt_mt_inst_733:X ropt_net_151:11 0.152 +1 ropt_net_151:2 ropt_mt_inst_750:A 0.152 +2 ropt_net_151:3 ropt_net_151:2 0.0003370536 +3 ropt_net_151:4 ropt_net_151:3 0.0045 +4 ropt_net_151:6 ropt_net_151:5 0.0045 +5 ropt_net_151:5 ropt_net_151:4 0.0005267857 +6 ropt_net_151:7 ropt_net_151:6 0.0015625 +7 ropt_net_151:8 ropt_net_151:7 0.0045 +8 ropt_net_151:10 ropt_net_151:9 0.0045 +9 ropt_net_151:9 ropt_net_151:8 0.002955357 +10 ropt_net_151:11 ropt_net_151:10 0.001332589 + +*END + +*D_NET ropt_net_157 0.002030081 //LENGTH 12.390 LUMPCC 0.0007728355 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 11.695 60.860 +*I ropt_mt_inst_757:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_157:2 *C 3.258 58.480 +*N ropt_net_157:3 *C 5.475 58.480 +*N ropt_net_157:4 *C 5.520 58.480 +*N ropt_net_157:5 *C 5.527 58.480 +*N ropt_net_157:6 *C 11.953 58.480 +*N ropt_net_157:7 *C 11.960 58.538 +*N ropt_net_157:8 *C 11.960 60.815 +*N ropt_net_157:9 *C 11.960 60.860 +*N ropt_net_157:10 *C 11.695 60.860 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_157:2 0.0001611197 +3 ropt_net_157:3 0.0001611197 +4 ropt_net_157:4 3.556386e-05 +5 ropt_net_157:5 0.0002634645 +6 ropt_net_157:6 0.0002634645 +7 ropt_net_157:7 0.0001181905 +8 ropt_net_157:8 0.0001181905 +9 ropt_net_157:9 6.35684e-05 +10 ropt_net_157:10 7.05636e-05 +11 ropt_net_157:6 chanx_left_in[5]:26 0.0001431723 +12 ropt_net_157:5 chanx_left_in[5] 0.0001431723 +13 ropt_net_157:6 chanx_left_in[11]:23 0.0001758381 +14 ropt_net_157:5 chanx_left_in[11]:24 0.0001758381 +15 ropt_net_157:10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.865012e-08 +16 ropt_net_157:9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 3.865012e-08 +17 ropt_net_157:8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.736869e-05 +18 ropt_net_157:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.736869e-05 + +*RES +0 ropt_mt_inst_742:X ropt_net_157:10 0.152 +1 ropt_net_157:10 ropt_net_157:9 0.0001440218 +2 ropt_net_157:9 ropt_net_157:8 0.0045 +3 ropt_net_157:8 ropt_net_157:7 0.002033482 +4 ropt_net_157:7 ropt_net_157:6 0.00341 +5 ropt_net_157:6 ropt_net_157:5 0.001006583 +6 ropt_net_157:4 ropt_net_157:3 0.0045 +7 ropt_net_157:5 ropt_net_157:4 0.00341 +8 ropt_net_157:3 ropt_net_157:2 0.001979911 +9 ropt_net_157:2 ropt_mt_inst_757:A 0.152 + +*END + +*D_NET chanx_left_in[11] 0.01617517 //LENGTH 106.630 LUMPCC 0.006230899 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 55.760 +*I mux_bottom_ipin_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 34.330 59.160 +*I mux_bottom_ipin_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.170 60.520 +*I BUFT_P_86:A I *L 0.001767 *C 86.020 61.200 +*I mux_bottom_ipin_15\/mux_l2_in_1_:A0 I *L 0.001631 *C 90.460 58.820 +*N chanx_left_in[11]:5 *C 90.498 58.820 +*N chanx_left_in[11]:6 *C 91.955 58.820 +*N chanx_left_in[11]:7 *C 92.000 58.820 +*N chanx_left_in[11]:8 *C 92.000 59.160 +*N chanx_left_in[11]:9 *C 91.993 59.160 +*N chanx_left_in[11]:10 *C 86.058 61.200 +*N chanx_left_in[11]:11 *C 89.655 61.200 +*N chanx_left_in[11]:12 *C 89.700 61.155 +*N chanx_left_in[11]:13 *C 89.700 59.218 +*N chanx_left_in[11]:14 *C 89.700 59.160 +*N chanx_left_in[11]:15 *C 59.133 60.520 +*N chanx_left_in[11]:16 *C 58.465 60.520 +*N chanx_left_in[11]:17 *C 58.420 60.475 +*N chanx_left_in[11]:18 *C 58.420 59.218 +*N chanx_left_in[11]:19 *C 58.420 59.160 +*N chanx_left_in[11]:20 *C 34.330 59.160 +*N chanx_left_in[11]:21 *C 34.500 59.160 +*N chanx_left_in[11]:22 *C 34.500 59.160 +*N chanx_left_in[11]:23 *C 34.500 59.160 +*N chanx_left_in[11]:24 *C 8.300 59.160 +*N chanx_left_in[11]:25 *C 8.280 59.153 +*N chanx_left_in[11]:26 *C 8.280 55.768 +*N chanx_left_in[11]:27 *C 8.260 55.760 + +*CAP +0 chanx_left_in[11] 0.0002656696 +1 mux_bottom_ipin_7\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_1_:A0 1e-06 +3 BUFT_P_86:A 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_1_:A0 1e-06 +5 chanx_left_in[11]:5 0.0001149251 +6 chanx_left_in[11]:6 0.0001149251 +7 chanx_left_in[11]:7 6.061829e-05 +8 chanx_left_in[11]:8 6.503484e-05 +9 chanx_left_in[11]:9 0.0001738972 +10 chanx_left_in[11]:10 0.0002525795 +11 chanx_left_in[11]:11 0.0002525795 +12 chanx_left_in[11]:12 0.0001684658 +13 chanx_left_in[11]:13 0.0001684658 +14 chanx_left_in[11]:14 0.001490403 +15 chanx_left_in[11]:15 7.085293e-05 +16 chanx_left_in[11]:16 7.085293e-05 +17 chanx_left_in[11]:17 9.214004e-05 +18 chanx_left_in[11]:18 9.214004e-05 +19 chanx_left_in[11]:19 0.002294738 +20 chanx_left_in[11]:20 5.306555e-05 +21 chanx_left_in[11]:21 5.759202e-05 +22 chanx_left_in[11]:22 3.623604e-05 +23 chanx_left_in[11]:23 0.002151565 +24 chanx_left_in[11]:24 0.001173332 +25 chanx_left_in[11]:25 0.0002272612 +26 chanx_left_in[11]:26 0.0002272612 +27 chanx_left_in[11]:27 0.0002656696 +28 chanx_left_in[11] chanx_left_in[5] 0.0001546752 +29 chanx_left_in[11]:23 chanx_left_in[5]:24 0.0004095823 +30 chanx_left_in[11]:23 chanx_left_in[5]:25 0.0005243988 +31 chanx_left_in[11]:23 chanx_left_in[5]:26 2.106704e-05 +32 chanx_left_in[11]:19 chanx_left_in[5]:19 6.740239e-06 +33 chanx_left_in[11]:19 chanx_left_in[5]:24 0.0005243988 +34 chanx_left_in[11]:19 chanx_left_in[5]:25 9.286767e-05 +35 chanx_left_in[11]:14 chanx_left_in[5]:18 6.740239e-06 +36 chanx_left_in[11]:14 chanx_left_in[5]:24 9.286767e-05 +37 chanx_left_in[11]:24 chanx_left_in[5] 2.106704e-05 +38 chanx_left_in[11]:24 chanx_left_in[5]:25 0.0004095823 +39 chanx_left_in[11]:27 chanx_left_in[5]:26 0.0001546752 +40 chanx_left_in[11] chanx_left_in[13]:22 0.0002666957 +41 chanx_left_in[11]:9 chanx_left_in[13]:8 2.098538e-06 +42 chanx_left_in[11]:19 chanx_left_in[13]:13 6.320931e-06 +43 chanx_left_in[11]:14 chanx_left_in[13]:8 6.320931e-06 +44 chanx_left_in[11]:14 chanx_left_in[13]:13 2.098538e-06 +45 chanx_left_in[11]:27 chanx_left_in[13]:21 0.0002666957 +46 chanx_left_in[11]:19 chanx_right_in[1]:53 0.0001194247 +47 chanx_left_in[11]:19 chanx_right_in[1]:47 0.0003055669 +48 chanx_left_in[11]:14 chanx_right_in[1]:54 0.0001194247 +49 chanx_left_in[11]:14 chanx_right_in[1]:53 0.0003055669 +50 chanx_left_in[11]:23 chanx_right_in[17]:16 0.000120196 +51 chanx_left_in[11]:23 chanx_right_in[17]:9 0.0001686951 +52 chanx_left_in[11]:23 chanx_right_in[17]:10 0.0002493129 +53 chanx_left_in[11]:19 chanx_right_in[17]:16 0.0002602028 +54 chanx_left_in[11]:19 chanx_right_in[17]:21 0.0003519634 +55 chanx_left_in[11]:19 chanx_right_in[17]:10 0.0001686951 +56 chanx_left_in[11]:14 chanx_right_in[17]:22 0.0002317675 +57 chanx_left_in[11]:14 chanx_right_in[17]:21 0.0002602028 +58 chanx_left_in[11]:24 chanx_right_in[17]:9 0.0002493129 +59 chanx_left_in[11]:23 ropt_net_157:6 0.0001758381 +60 chanx_left_in[11]:24 ropt_net_157:5 0.0001758381 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:27 0.001101367 +1 chanx_left_in[11]:22 chanx_left_in[11]:21 0.0045 +2 chanx_left_in[11]:23 chanx_left_in[11]:22 0.00341 +3 chanx_left_in[11]:23 chanx_left_in[11]:19 0.003747466 +4 chanx_left_in[11]:21 chanx_left_in[11]:20 9.239131e-05 +5 chanx_left_in[11]:20 mux_bottom_ipin_7\/mux_l2_in_1_:A0 0.152 +6 chanx_left_in[11]:8 chanx_left_in[11]:7 0.0001634615 +7 chanx_left_in[11]:9 chanx_left_in[11]:8 0.00341 +8 chanx_left_in[11]:6 chanx_left_in[11]:5 0.001301339 +9 chanx_left_in[11]:7 chanx_left_in[11]:6 0.0045 +10 chanx_left_in[11]:5 mux_bottom_ipin_15\/mux_l2_in_1_:A0 0.152 +11 chanx_left_in[11]:18 chanx_left_in[11]:17 0.001122768 +12 chanx_left_in[11]:19 chanx_left_in[11]:18 0.00341 +13 chanx_left_in[11]:19 chanx_left_in[11]:14 0.004900533 +14 chanx_left_in[11]:16 chanx_left_in[11]:15 0.0005959822 +15 chanx_left_in[11]:17 chanx_left_in[11]:16 0.0045 +16 chanx_left_in[11]:15 mux_bottom_ipin_1\/mux_l2_in_1_:A0 0.152 +17 chanx_left_in[11]:13 chanx_left_in[11]:12 0.001729911 +18 chanx_left_in[11]:14 chanx_left_in[11]:13 0.00341 +19 chanx_left_in[11]:14 chanx_left_in[11]:9 0.0003591583 +20 chanx_left_in[11]:11 chanx_left_in[11]:10 0.003212054 +21 chanx_left_in[11]:12 chanx_left_in[11]:11 0.0045 +22 chanx_left_in[11]:10 BUFT_P_86:A 0.152 +23 chanx_left_in[11]:24 chanx_left_in[11]:23 0.004104666 +24 chanx_left_in[11]:25 chanx_left_in[11]:24 0.00341 +25 chanx_left_in[11]:27 chanx_left_in[11]:26 0.00341 +26 chanx_left_in[11]:26 chanx_left_in[11]:25 0.0005303167 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[2] 0.004037907 //LENGTH 25.270 LUMPCC 0.001708188 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 65.165 9.860 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 51.235 11.900 +*I mux_bottom_ipin_4\/mux_l3_in_1_:S I *L 0.00357 *C 61.300 14.620 +*I mux_bottom_ipin_4\/mux_l3_in_0_:S I *L 0.00357 *C 61.280 18.360 +*N mux_tree_tapbuf_size10_2_sram[2]:4 *C 61.180 18.360 +*N mux_tree_tapbuf_size10_2_sram[2]:5 *C 61.180 18.315 +*N mux_tree_tapbuf_size10_2_sram[2]:6 *C 61.180 14.665 +*N mux_tree_tapbuf_size10_2_sram[2]:7 *C 61.338 14.620 +*N mux_tree_tapbuf_size10_2_sram[2]:8 *C 62.055 14.620 +*N mux_tree_tapbuf_size10_2_sram[2]:9 *C 62.100 14.575 +*N mux_tree_tapbuf_size10_2_sram[2]:10 *C 51.235 11.900 +*N mux_tree_tapbuf_size10_2_sram[2]:11 *C 51.520 11.900 +*N mux_tree_tapbuf_size10_2_sram[2]:12 *C 51.520 11.900 +*N mux_tree_tapbuf_size10_2_sram[2]:13 *C 51.520 11.560 +*N mux_tree_tapbuf_size10_2_sram[2]:14 *C 51.528 11.560 +*N mux_tree_tapbuf_size10_2_sram[2]:15 *C 62.093 11.560 +*N mux_tree_tapbuf_size10_2_sram[2]:16 *C 62.100 11.560 +*N mux_tree_tapbuf_size10_2_sram[2]:17 *C 62.100 9.905 +*N mux_tree_tapbuf_size10_2_sram[2]:18 *C 62.145 9.860 +*N mux_tree_tapbuf_size10_2_sram[2]:19 *C 65.127 9.860 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_4\/mux_l3_in_1_:S 1e-06 +3 mux_bottom_ipin_4\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_2_sram[2]:4 3.41377e-05 +5 mux_tree_tapbuf_size10_2_sram[2]:5 0.0002210881 +6 mux_tree_tapbuf_size10_2_sram[2]:6 0.0002210881 +7 mux_tree_tapbuf_size10_2_sram[2]:7 7.357413e-05 +8 mux_tree_tapbuf_size10_2_sram[2]:8 7.357413e-05 +9 mux_tree_tapbuf_size10_2_sram[2]:9 0.0001701161 +10 mux_tree_tapbuf_size10_2_sram[2]:10 4.597306e-05 +11 mux_tree_tapbuf_size10_2_sram[2]:11 4.965471e-05 +12 mux_tree_tapbuf_size10_2_sram[2]:12 5.092449e-05 +13 mux_tree_tapbuf_size10_2_sram[2]:13 5.488157e-05 +14 mux_tree_tapbuf_size10_2_sram[2]:14 0.0002808933 +15 mux_tree_tapbuf_size10_2_sram[2]:15 0.0002808933 +16 mux_tree_tapbuf_size10_2_sram[2]:16 0.0002967806 +17 mux_tree_tapbuf_size10_2_sram[2]:17 8.918557e-05 +18 mux_tree_tapbuf_size10_2_sram[2]:18 0.0001914773 +19 mux_tree_tapbuf_size10_2_sram[2]:19 0.0001914773 +20 mux_tree_tapbuf_size10_2_sram[2]:9 chanx_left_in[14]:7 8.851515e-07 +21 mux_tree_tapbuf_size10_2_sram[2]:16 chanx_left_in[14]:7 7.523787e-06 +22 mux_tree_tapbuf_size10_2_sram[2]:16 chanx_left_in[14]:14 3.65125e-06 +23 mux_tree_tapbuf_size10_2_sram[2]:15 chanx_left_in[14]:15 0.0002329869 +24 mux_tree_tapbuf_size10_2_sram[2]:14 chanx_left_in[14]:16 0.0002329869 +25 mux_tree_tapbuf_size10_2_sram[2]:17 chanx_left_in[14]:13 2.766098e-06 +26 mux_tree_tapbuf_size10_2_sram[2]:17 chanx_left_in[14]:14 7.523787e-06 +27 mux_tree_tapbuf_size10_2_sram[2]:15 chanx_right_in[8]:13 0.0006099319 +28 mux_tree_tapbuf_size10_2_sram[2]:14 chanx_right_in[8]:12 0.0006099319 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_2_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_2_sram[2]:7 mux_bottom_ipin_4\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[2]:7 mux_tree_tapbuf_size10_2_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size10_2_sram[2]:8 mux_tree_tapbuf_size10_2_sram[2]:7 0.000640625 +4 mux_tree_tapbuf_size10_2_sram[2]:9 mux_tree_tapbuf_size10_2_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size10_2_sram[2]:16 mux_tree_tapbuf_size10_2_sram[2]:15 0.00341 +6 mux_tree_tapbuf_size10_2_sram[2]:16 mux_tree_tapbuf_size10_2_sram[2]:9 0.002691964 +7 mux_tree_tapbuf_size10_2_sram[2]:15 mux_tree_tapbuf_size10_2_sram[2]:14 0.001655183 +8 mux_tree_tapbuf_size10_2_sram[2]:13 mux_tree_tapbuf_size10_2_sram[2]:12 0.0001634615 +9 mux_tree_tapbuf_size10_2_sram[2]:14 mux_tree_tapbuf_size10_2_sram[2]:13 0.00341 +10 mux_tree_tapbuf_size10_2_sram[2]:11 mux_tree_tapbuf_size10_2_sram[2]:10 0.0001548913 +11 mux_tree_tapbuf_size10_2_sram[2]:12 mux_tree_tapbuf_size10_2_sram[2]:11 0.0045 +12 mux_tree_tapbuf_size10_2_sram[2]:10 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size10_2_sram[2]:18 mux_tree_tapbuf_size10_2_sram[2]:17 0.0045 +14 mux_tree_tapbuf_size10_2_sram[2]:17 mux_tree_tapbuf_size10_2_sram[2]:16 0.001477679 +15 mux_tree_tapbuf_size10_2_sram[2]:19 mux_tree_tapbuf_size10_2_sram[2]:18 0.002662947 +16 mux_tree_tapbuf_size10_2_sram[2]:6 mux_tree_tapbuf_size10_2_sram[2]:5 0.003258929 +17 mux_tree_tapbuf_size10_2_sram[2]:4 mux_bottom_ipin_4\/mux_l3_in_0_:S 0.152 +18 mux_tree_tapbuf_size10_2_sram[2]:5 mux_tree_tapbuf_size10_2_sram[2]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[2] 0.001589289 //LENGTH 12.145 LUMPCC 7.461959e-05 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 64.705 36.720 +*I mux_bottom_ipin_12\/mux_l3_in_0_:S I *L 0.00357 *C 64.300 34.000 +*I mux_bottom_ipin_12\/mux_l3_in_1_:S I *L 0.00357 *C 67.520 31.280 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 64.575 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:4 *C 64.575 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:5 *C 64.400 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:6 *C 64.400 39.055 +*N mux_tree_tapbuf_size10_6_sram[2]:7 *C 67.483 31.280 +*N mux_tree_tapbuf_size10_6_sram[2]:8 *C 64.445 31.280 +*N mux_tree_tapbuf_size10_6_sram[2]:9 *C 64.400 31.325 +*N mux_tree_tapbuf_size10_6_sram[2]:10 *C 64.300 34.000 +*N mux_tree_tapbuf_size10_6_sram[2]:11 *C 64.400 34.000 +*N mux_tree_tapbuf_size10_6_sram[2]:12 *C 64.400 36.720 +*N mux_tree_tapbuf_size10_6_sram[2]:13 *C 64.400 36.720 +*N mux_tree_tapbuf_size10_6_sram[2]:14 *C 64.705 36.720 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_12\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_6_sram[2]:4 4.718393e-05 +5 mux_tree_tapbuf_size10_6_sram[2]:5 5.130658e-05 +6 mux_tree_tapbuf_size10_6_sram[2]:6 0.0001267555 +7 mux_tree_tapbuf_size10_6_sram[2]:7 0.0001911094 +8 mux_tree_tapbuf_size10_6_sram[2]:8 0.0001911094 +9 mux_tree_tapbuf_size10_6_sram[2]:9 0.000149739 +10 mux_tree_tapbuf_size10_6_sram[2]:10 3.049352e-05 +11 mux_tree_tapbuf_size10_6_sram[2]:11 0.000319271 +12 mux_tree_tapbuf_size10_6_sram[2]:12 0.0002962849 +13 mux_tree_tapbuf_size10_6_sram[2]:13 5.575627e-05 +14 mux_tree_tapbuf_size10_6_sram[2]:14 5.165971e-05 +15 mux_tree_tapbuf_size10_6_sram[2]:8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.73098e-05 +16 mux_tree_tapbuf_size10_6_sram[2]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.73098e-05 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_6_sram[2]:14 0.152 +1 mux_tree_tapbuf_size10_6_sram[2]:8 mux_tree_tapbuf_size10_6_sram[2]:7 0.002712054 +2 mux_tree_tapbuf_size10_6_sram[2]:9 mux_tree_tapbuf_size10_6_sram[2]:8 0.0045 +3 mux_tree_tapbuf_size10_6_sram[2]:7 mux_bottom_ipin_12\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size10_6_sram[2]:10 mux_bottom_ipin_12\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_6_sram[2]:11 mux_tree_tapbuf_size10_6_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size10_6_sram[2]:11 mux_tree_tapbuf_size10_6_sram[2]:9 0.002388393 +7 mux_tree_tapbuf_size10_6_sram[2]:5 mux_tree_tapbuf_size10_6_sram[2]:4 9.51087e-05 +8 mux_tree_tapbuf_size10_6_sram[2]:6 mux_tree_tapbuf_size10_6_sram[2]:5 0.0045 +9 mux_tree_tapbuf_size10_6_sram[2]:4 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size10_6_sram[2]:13 mux_tree_tapbuf_size10_6_sram[2]:12 0.0045 +11 mux_tree_tapbuf_size10_6_sram[2]:12 mux_tree_tapbuf_size10_6_sram[2]:11 0.002428571 +12 mux_tree_tapbuf_size10_6_sram[2]:12 mux_tree_tapbuf_size10_6_sram[2]:6 0.002084821 +13 mux_tree_tapbuf_size10_6_sram[2]:14 mux_tree_tapbuf_size10_6_sram[2]:13 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_5_ccff_tail[0] 0.003909837 //LENGTH 28.990 LUMPCC 0.0006101688 DR + +*CONN +*I mem_bottom_ipin_9\/FTB_6__45:X O *L 0 *C 14.485 65.960 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 12.580 42.500 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 *C 12.580 42.500 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 *C 12.420 42.500 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 *C 12.420 42.545 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 *C 12.420 46.183 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 *C 12.418 46.240 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 *C 11.975 46.240 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 *C 11.960 46.248 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 *C 11.960 65.273 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 *C 11.980 65.280 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 *C 14.713 65.280 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:12 *C 14.720 65.338 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:13 *C 14.720 65.915 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:14 *C 14.720 65.960 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:15 *C 14.485 65.960 + +*CAP +0 mem_bottom_ipin_9\/FTB_6__45:X 1e-06 +1 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 5.132272e-05 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 5.588095e-05 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.0001438745 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0001438745 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 3.876121e-05 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 3.876121e-05 +8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 0.001173623 +9 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 0.001173623 +10 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 0.0001277566 +11 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 0.0001277566 +12 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:12 6.052485e-05 +13 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:13 6.052485e-05 +14 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:14 5.154865e-05 +15 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:15 4.983496e-05 +16 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 chanx_right_in[13]:17 0.000169664 +17 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 chanx_right_in[13]:18 0.000169664 +18 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 4.30172e-05 +19 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 4.30172e-05 +20 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 chanx_left_out[0]:6 4.748402e-05 +21 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 chanx_left_out[0]:5 4.748402e-05 +22 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 chanx_left_out[0]:4 4.491913e-05 +23 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 chanx_left_out[0]:3 4.491913e-05 + +*RES +0 mem_bottom_ipin_9\/FTB_6__45:X mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:15 0.152 +1 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 8.695653e-05 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.003247768 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.00341 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 6.499219e-05 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 0.00341 +8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 0.00341 +9 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 0.002980583 +10 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:12 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 0.00341 +11 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:11 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:10 0.0004280917 +12 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:14 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:13 0.0045 +13 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:13 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:12 0.000515625 +14 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:15 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:14 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[1] 0.003922823 //LENGTH 31.140 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 23.765 14.960 +*I mux_bottom_ipin_10\/mux_l2_in_2_:S I *L 0.00357 *C 27.700 14.280 +*I mux_bottom_ipin_10\/mux_l2_in_0_:S I *L 0.00357 *C 19.680 23.120 +*I mux_bottom_ipin_10\/mux_l2_in_1_:S I *L 0.00357 *C 24.020 23.460 +*I mux_bottom_ipin_10\/mux_l2_in_3_:S I *L 0.00357 *C 24.260 12.580 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 24.555 9.860 +*N mux_tree_tapbuf_size8_4_sram[1]:6 *C 24.518 9.860 +*N mux_tree_tapbuf_size8_4_sram[1]:7 *C 23.965 9.860 +*N mux_tree_tapbuf_size8_4_sram[1]:8 *C 23.920 9.905 +*N mux_tree_tapbuf_size8_4_sram[1]:9 *C 23.920 11.900 +*N mux_tree_tapbuf_size8_4_sram[1]:10 *C 23.460 11.900 +*N mux_tree_tapbuf_size8_4_sram[1]:11 *C 24.223 12.580 +*N mux_tree_tapbuf_size8_4_sram[1]:12 *C 23.983 23.460 +*N mux_tree_tapbuf_size8_4_sram[1]:13 *C 21.620 23.460 +*N mux_tree_tapbuf_size8_4_sram[1]:14 *C 19.718 23.120 +*N mux_tree_tapbuf_size8_4_sram[1]:15 *C 21.620 23.150 +*N mux_tree_tapbuf_size8_4_sram[1]:16 *C 21.620 23.075 +*N mux_tree_tapbuf_size8_4_sram[1]:17 *C 21.620 12.625 +*N mux_tree_tapbuf_size8_4_sram[1]:18 *C 21.665 12.580 +*N mux_tree_tapbuf_size8_4_sram[1]:19 *C 23.460 12.580 +*N mux_tree_tapbuf_size8_4_sram[1]:20 *C 23.460 12.580 +*N mux_tree_tapbuf_size8_4_sram[1]:21 *C 27.663 14.280 +*N mux_tree_tapbuf_size8_4_sram[1]:22 *C 23.505 14.280 +*N mux_tree_tapbuf_size8_4_sram[1]:23 *C 23.460 14.280 +*N mux_tree_tapbuf_size8_4_sram[1]:24 *C 23.460 14.915 +*N mux_tree_tapbuf_size8_4_sram[1]:25 *C 23.460 14.960 +*N mux_tree_tapbuf_size8_4_sram[1]:26 *C 23.765 14.960 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_10\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_ipin_10\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_10\/mux_l2_in_3_:S 1e-06 +5 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_4_sram[1]:6 5.931903e-05 +7 mux_tree_tapbuf_size8_4_sram[1]:7 5.931903e-05 +8 mux_tree_tapbuf_size8_4_sram[1]:8 0.0001311096 +9 mux_tree_tapbuf_size8_4_sram[1]:9 0.0001606796 +10 mux_tree_tapbuf_size8_4_sram[1]:10 7.650609e-05 +11 mux_tree_tapbuf_size8_4_sram[1]:11 6.08178e-05 +12 mux_tree_tapbuf_size8_4_sram[1]:12 0.0002046478 +13 mux_tree_tapbuf_size8_4_sram[1]:13 0.0002318094 +14 mux_tree_tapbuf_size8_4_sram[1]:14 0.0001418258 +15 mux_tree_tapbuf_size8_4_sram[1]:15 0.0001689874 +16 mux_tree_tapbuf_size8_4_sram[1]:16 0.0005949134 +17 mux_tree_tapbuf_size8_4_sram[1]:17 0.0005949134 +18 mux_tree_tapbuf_size8_4_sram[1]:18 0.0001172213 +19 mux_tree_tapbuf_size8_4_sram[1]:19 0.0002095081 +20 mux_tree_tapbuf_size8_4_sram[1]:20 0.000182451 +21 mux_tree_tapbuf_size8_4_sram[1]:21 0.0002921081 +22 mux_tree_tapbuf_size8_4_sram[1]:22 0.0002921081 +23 mux_tree_tapbuf_size8_4_sram[1]:23 0.0001832418 +24 mux_tree_tapbuf_size8_4_sram[1]:24 4.643444e-05 +25 mux_tree_tapbuf_size8_4_sram[1]:25 5.565566e-05 +26 mux_tree_tapbuf_size8_4_sram[1]:26 5.324679e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_4_sram[1]:26 0.152 +1 mux_tree_tapbuf_size8_4_sram[1]:22 mux_tree_tapbuf_size8_4_sram[1]:21 0.003712054 +2 mux_tree_tapbuf_size8_4_sram[1]:23 mux_tree_tapbuf_size8_4_sram[1]:22 0.0045 +3 mux_tree_tapbuf_size8_4_sram[1]:23 mux_tree_tapbuf_size8_4_sram[1]:20 0.001517857 +4 mux_tree_tapbuf_size8_4_sram[1]:21 mux_bottom_ipin_10\/mux_l2_in_2_:S 0.152 +5 mux_tree_tapbuf_size8_4_sram[1]:25 mux_tree_tapbuf_size8_4_sram[1]:24 0.0045 +6 mux_tree_tapbuf_size8_4_sram[1]:24 mux_tree_tapbuf_size8_4_sram[1]:23 0.0005669643 +7 mux_tree_tapbuf_size8_4_sram[1]:26 mux_tree_tapbuf_size8_4_sram[1]:25 0.0001657609 +8 mux_tree_tapbuf_size8_4_sram[1]:15 mux_tree_tapbuf_size8_4_sram[1]:14 0.001698661 +9 mux_tree_tapbuf_size8_4_sram[1]:15 mux_tree_tapbuf_size8_4_sram[1]:13 0.0002767857 +10 mux_tree_tapbuf_size8_4_sram[1]:16 mux_tree_tapbuf_size8_4_sram[1]:15 0.0045 +11 mux_tree_tapbuf_size8_4_sram[1]:18 mux_tree_tapbuf_size8_4_sram[1]:17 0.0045 +12 mux_tree_tapbuf_size8_4_sram[1]:17 mux_tree_tapbuf_size8_4_sram[1]:16 0.009330357 +13 mux_tree_tapbuf_size8_4_sram[1]:19 mux_tree_tapbuf_size8_4_sram[1]:18 0.001602679 +14 mux_tree_tapbuf_size8_4_sram[1]:19 mux_tree_tapbuf_size8_4_sram[1]:11 0.0006808035 +15 mux_tree_tapbuf_size8_4_sram[1]:20 mux_tree_tapbuf_size8_4_sram[1]:19 0.0045 +16 mux_tree_tapbuf_size8_4_sram[1]:20 mux_tree_tapbuf_size8_4_sram[1]:10 0.000607143 +17 mux_tree_tapbuf_size8_4_sram[1]:11 mux_bottom_ipin_10\/mux_l2_in_3_:S 0.152 +18 mux_tree_tapbuf_size8_4_sram[1]:12 mux_bottom_ipin_10\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size8_4_sram[1]:14 mux_bottom_ipin_10\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size8_4_sram[1]:7 mux_tree_tapbuf_size8_4_sram[1]:6 0.0004933036 +21 mux_tree_tapbuf_size8_4_sram[1]:8 mux_tree_tapbuf_size8_4_sram[1]:7 0.0045 +22 mux_tree_tapbuf_size8_4_sram[1]:6 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +23 mux_tree_tapbuf_size8_4_sram[1]:13 mux_tree_tapbuf_size8_4_sram[1]:12 0.002109375 +24 mux_tree_tapbuf_size8_4_sram[1]:10 mux_tree_tapbuf_size8_4_sram[1]:9 0.0004107143 +25 mux_tree_tapbuf_size8_4_sram[1]:9 mux_tree_tapbuf_size8_4_sram[1]:8 0.00178125 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004156172 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_1_:X O *L 0 *C 87.115 31.960 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 87.690 33.320 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 87.690 33.320 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 87.400 33.320 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 87.400 33.275 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 87.400 32.005 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 87.400 31.960 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 87.115 31.960 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.394733e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.751653e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.232302e-05 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.232302e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.890152e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.860574e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001576087 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133929 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008785709 //LENGTH 6.910 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_0_:X O *L 0 *C 63.765 25.500 +*I mux_bottom_ipin_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 63.385 20.060 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 63.423 20.060 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.895 20.060 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.940 20.105 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.940 25.455 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.940 25.500 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 63.765 25.500 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.574962e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.574962e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003150508 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003150508 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.470273e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.026731e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004776786 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001389231 //LENGTH 9.195 LUMPCC 0.0006266099 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_0_:X O *L 0 *C 22.255 28.560 +*I mux_bottom_ipin_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 13.800 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 13.800 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 13.800 28.560 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 22.218 28.560 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.803102e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003655486 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003370411 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[0]:27 0.0002609261 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[0]:26 0.0002609261 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_4_sram[1]:23 9.868468e-06 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_4_sram[1]:24 4.251032e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_4_sram[1]:22 9.868468e-06 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_4_sram[1]:23 4.251032e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.007515625 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_0_:A1 0.152 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006415027 //LENGTH 3.620 LUMPCC 7.736096e-05 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_1_:X O *L 0 *C 13.515 56.100 +*I mux_bottom_ipin_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 14.065 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 14.065 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 13.800 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 13.800 58.775 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 13.800 56.145 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 13.800 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 13.515 56.100 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.10065e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.957632e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001769404 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001769404 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.406121e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.361682e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_5_sram[1]:17 1.072328e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_5_sram[1]:15 1.072328e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_5_sram[1]:18 7.432976e-07 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_5_sram[1]:20 1.362756e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_5_sram[1]:22 1.358634e-05 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_5_sram[1]:19 7.432976e-07 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_5_sram[1]:21 1.362756e-05 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_5_sram[1]:23 1.358634e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001440218 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009091406 //LENGTH 5.745 LUMPCC 0.0004389496 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_1_:X O *L 0 *C 73.775 56.440 +*I mux_bottom_ipin_13\/mux_l3_in_0_:A0 I *L 0.001631 *C 74.350 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 74.312 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 73.645 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 73.600 60.475 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 73.600 56.485 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 73.600 56.440 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 73.775 56.440 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.885171e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.885171e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001093531 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001093531 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.63733e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.540811e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0001097374 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0001097374 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001097374 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001097374 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0005959822 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009628601 //LENGTH 7.490 LUMPCC 0.0002643618 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_0_:X O *L 0 *C 43.065 58.820 +*I mux_bottom_ipin_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 42.420 52.700 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 42.320 52.700 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 42.320 52.745 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 42.320 58.775 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 42.365 58.820 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 43.028 58.820 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.383851e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002495932 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002495932 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.17367e-05 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.17367e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[3]:44 6.448858e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[3]:45 6.448858e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_1_sram[2]:9 1.487255e-05 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_1_sram[2]:13 5.281978e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size8_1_sram[2]:10 1.487255e-05 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size8_1_sram[2]:14 5.281978e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.005383929 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006781802 //LENGTH 4.785 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_0_:X O *L 0 *C 20.525 22.440 +*I mux_bottom_ipin_10\/mux_l3_in_0_:A1 I *L 0.00198 *C 21.985 20.060 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 21.985 20.060 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.080 20.400 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 20.745 20.400 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 20.700 20.445 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 20.700 22.395 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 20.700 22.440 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 20.525 22.440 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.663444e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001370154 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001089472 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001310277 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001310277 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.601564e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.551214e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001191964 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001741072 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.51087e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0] 0.005517085 //LENGTH 46.085 LUMPCC 0.001073722 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l4_in_0_:X O *L 0 *C 76.535 30.940 +*I mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 75.690 71.880 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 75.690 71.880 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 75.690 71.400 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 74.105 71.400 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 74.060 71.355 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 74.060 30.985 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 74.105 30.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 76.498 30.940 + +*CAP +0 mux_bottom_ipin_14\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.116127e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001626192 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001231399 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001882027 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001882027 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001601947 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0001601947 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0002314931 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0002314931 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001097374 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001097374 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001956306 +14 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001956306 + +*RES +0 mux_bottom_ipin_14\/mux_l4_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.001415179 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.03604465 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.002136161 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004285715 + +*END + +*D_NET chanx_left_out[8] 0.001206182 //LENGTH 8.930 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_749:X O *L 0 *C 7.095 17.340 +*P chanx_left_out[8] O *L 0.7423 *C 1.230 14.960 +*N chanx_left_out[8]:2 *C 3.213 14.960 +*N chanx_left_out[8]:3 *C 3.220 15.018 +*N chanx_left_out[8]:4 *C 3.220 16.955 +*N chanx_left_out[8]:5 *C 3.265 17.000 +*N chanx_left_out[8]:6 *C 6.900 17.000 +*N chanx_left_out[8]:7 *C 7.095 17.340 + +*CAP +0 ropt_mt_inst_749:X 1e-06 +1 chanx_left_out[8] 0.0001692417 +2 chanx_left_out[8]:2 0.0001692417 +3 chanx_left_out[8]:3 0.00012981 +4 chanx_left_out[8]:4 0.00012981 +5 chanx_left_out[8]:5 0.0002535501 +6 chanx_left_out[8]:6 0.0002830655 +7 chanx_left_out[8]:7 7.046291e-05 + +*RES +0 ropt_mt_inst_749:X chanx_left_out[8]:7 0.152 +1 chanx_left_out[8]:7 chanx_left_out[8]:6 0.0003035715 +2 chanx_left_out[8]:5 chanx_left_out[8]:4 0.0045 +3 chanx_left_out[8]:4 chanx_left_out[8]:3 0.001729911 +4 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +5 chanx_left_out[8]:2 chanx_left_out[8] 0.0003105917 +6 chanx_left_out[8]:6 chanx_left_out[8]:5 0.003245536 + +*END + +*D_NET chanx_left_out[7] 0.001865165 //LENGTH 13.640 LUMPCC 0.0001978626 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 8.740 50.660 +*P chanx_left_out[7] O *L 0.7423 *C 1.298 47.600 +*N chanx_left_out[7]:2 *C 1.380 47.600 +*N chanx_left_out[7]:3 *C 1.380 47.657 +*N chanx_left_out[7]:4 *C 1.380 50.955 +*N chanx_left_out[7]:5 *C 1.425 51.000 +*N chanx_left_out[7]:6 *C 9.200 51.000 +*N chanx_left_out[7]:7 *C 9.200 50.660 +*N chanx_left_out[7]:8 *C 8.777 50.660 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 chanx_left_out[7] 3.440983e-05 +2 chanx_left_out[7]:2 3.440983e-05 +3 chanx_left_out[7]:3 0.0002011223 +4 chanx_left_out[7]:4 0.0002011223 +5 chanx_left_out[7]:5 0.0005252806 +6 chanx_left_out[7]:6 0.0005488595 +7 chanx_left_out[7]:7 7.233866e-05 +8 chanx_left_out[7]:8 4.875973e-05 +9 chanx_left_out[7] ropt_net_158:6 1.040436e-05 +10 chanx_left_out[7]:5 ropt_net_158:3 8.852695e-05 +11 chanx_left_out[7]:2 ropt_net_158:5 1.040436e-05 +12 chanx_left_out[7]:6 ropt_net_158:4 8.852695e-05 + +*RES +0 ropt_mt_inst_754:X chanx_left_out[7]:8 0.152 +1 chanx_left_out[7]:8 chanx_left_out[7]:7 0.0003772322 +2 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +3 chanx_left_out[7]:4 chanx_left_out[7]:3 0.002944197 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 2.35e-05 +6 chanx_left_out[7]:6 chanx_left_out[7]:5 0.006941965 +7 chanx_left_out[7]:7 chanx_left_out[7]:6 0.0003035715 + +*END + +*D_NET ropt_net_118 0.002198716 //LENGTH 16.400 LUMPCC 0.0002240739 DR + +*CONN +*I BUFT_P_86:X O *L 0 *C 87.115 61.880 +*I ropt_mt_inst_717:A I *L 0.001766 *C 97.825 66.640 +*N ropt_net_118:2 *C 97.788 66.640 +*N ropt_net_118:3 *C 96.185 66.640 +*N ropt_net_118:4 *C 96.140 66.595 +*N ropt_net_118:5 *C 96.140 61.925 +*N ropt_net_118:6 *C 96.095 61.880 +*N ropt_net_118:7 *C 87.153 61.880 + +*CAP +0 BUFT_P_86:X 1e-06 +1 ropt_mt_inst_717:A 1e-06 +2 ropt_net_118:2 6.836734e-05 +3 ropt_net_118:3 6.836734e-05 +4 ropt_net_118:4 0.0002540565 +5 ropt_net_118:5 0.0002540565 +6 ropt_net_118:6 0.0006638973 +7 ropt_net_118:7 0.0006638973 +8 ropt_net_118:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.774492e-05 +9 ropt_net_118:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 4.774492e-05 +10 ropt_net_118:2 ropt_net_123:5 6.429203e-05 +11 ropt_net_118:3 ropt_net_123:4 6.429203e-05 + +*RES +0 BUFT_P_86:X ropt_net_118:7 0.152 +1 ropt_net_118:2 ropt_mt_inst_717:A 0.152 +2 ropt_net_118:3 ropt_net_118:2 0.001430804 +3 ropt_net_118:4 ropt_net_118:3 0.0045 +4 ropt_net_118:6 ropt_net_118:5 0.0045 +5 ropt_net_118:5 ropt_net_118:4 0.004169643 +6 ropt_net_118:7 ropt_net_118:6 0.007984376 + +*END + +*D_NET chanx_right_out[6] 0.0008375009 //LENGTH 7.480 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 101.855 52.360 +*P chanx_right_out[6] O *L 0.7423 *C 103.583 47.600 +*N chanx_right_out[6]:2 *C 103.500 47.600 +*N chanx_right_out[6]:3 *C 103.500 47.600 +*N chanx_right_out[6]:4 *C 103.040 47.600 +*N chanx_right_out[6]:5 *C 103.040 52.315 +*N chanx_right_out[6]:6 *C 102.995 52.360 +*N chanx_right_out[6]:7 *C 101.892 52.360 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 chanx_right_out[6] 3.548342e-05 +2 chanx_right_out[6]:2 3.548342e-05 +3 chanx_right_out[6]:3 5.949458e-05 +4 chanx_right_out[6]:4 0.0002711504 +5 chanx_right_out[6]:5 0.0002414411 +6 chanx_right_out[6]:6 9.6724e-05 +7 chanx_right_out[6]:7 9.6724e-05 + +*RES +0 ropt_mt_inst_781:X chanx_right_out[6]:7 0.152 +1 chanx_right_out[6]:7 chanx_right_out[6]:6 0.0009843751 +2 chanx_right_out[6]:6 chanx_right_out[6]:5 0.0045 +3 chanx_right_out[6]:5 chanx_right_out[6]:4 0.004209821 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 2.35e-05 +6 chanx_right_out[6]:4 chanx_right_out[6]:3 0.0004107143 + +*END + +*D_NET chanx_left_in[12] 0.02293243 //LENGTH 155.195 LUMPCC 0.008440793 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 69.360 +*I mux_bottom_ipin_12\/mux_l2_in_1_:A0 I *L 0.001631 *C 61.865 28.220 +*I ropt_mt_inst_714:A I *L 0.001767 *C 97.825 36.720 +*I mux_bottom_ipin_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 9.375 28.220 +*N chanx_left_in[12]:4 *C 9.375 28.220 +*N chanx_left_in[12]:5 *C 9.200 28.560 +*N chanx_left_in[12]:6 *C 97.863 36.720 +*N chanx_left_in[12]:7 *C 99.275 36.720 +*N chanx_left_in[12]:8 *C 99.320 36.720 +*N chanx_left_in[12]:9 *C 99.312 36.720 +*N chanx_left_in[12]:10 *C 79.127 36.720 +*N chanx_left_in[12]:11 *C 79.120 36.720 +*N chanx_left_in[12]:12 *C 79.075 36.720 +*N chanx_left_in[12]:13 *C 78.200 36.720 +*N chanx_left_in[12]:14 *C 78.200 37.060 +*N chanx_left_in[12]:15 *C 62.145 37.060 +*N chanx_left_in[12]:16 *C 62.100 37.015 +*N chanx_left_in[12]:17 *C 61.865 28.220 +*N chanx_left_in[12]:18 *C 62.100 28.220 +*N chanx_left_in[12]:19 *C 62.100 28.265 +*N chanx_left_in[12]:20 *C 62.100 27.880 +*N chanx_left_in[12]:21 *C 62.093 27.880 +*N chanx_left_in[12]:22 *C 8.748 27.880 +*N chanx_left_in[12]:23 *C 8.740 27.938 +*N chanx_left_in[12]:24 *C 8.740 28.515 +*N chanx_left_in[12]:25 *C 8.740 28.560 +*N chanx_left_in[12]:26 *C 8.740 28.900 +*N chanx_left_in[12]:27 *C 2.805 28.900 +*N chanx_left_in[12]:28 *C 2.760 28.945 +*N chanx_left_in[12]:29 *C 2.760 69.303 +*N chanx_left_in[12]:30 *C 2.752 69.360 + +*CAP +0 chanx_left_in[12] 0.000135737 +1 mux_bottom_ipin_12\/mux_l2_in_1_:A0 1e-06 +2 ropt_mt_inst_714:A 1e-06 +3 mux_bottom_ipin_8\/mux_l2_in_1_:A0 1e-06 +4 chanx_left_in[12]:4 5.424314e-05 +5 chanx_left_in[12]:5 6.81363e-05 +6 chanx_left_in[12]:6 0.0001307904 +7 chanx_left_in[12]:7 0.0001307904 +8 chanx_left_in[12]:8 3.261968e-05 +9 chanx_left_in[12]:9 0.0009308759 +10 chanx_left_in[12]:10 0.0009308759 +11 chanx_left_in[12]:11 3.187751e-05 +12 chanx_left_in[12]:12 6.555722e-05 +13 chanx_left_in[12]:13 9.026066e-05 +14 chanx_left_in[12]:14 0.001044137 +15 chanx_left_in[12]:15 0.001019433 +16 chanx_left_in[12]:16 0.0005018238 +17 chanx_left_in[12]:17 4.575272e-05 +18 chanx_left_in[12]:18 5.002205e-05 +19 chanx_left_in[12]:19 0.000522513 +20 chanx_left_in[12]:20 5.917244e-05 +21 chanx_left_in[12]:21 0.002317186 +22 chanx_left_in[12]:22 0.002317186 +23 chanx_left_in[12]:23 6.01339e-05 +24 chanx_left_in[12]:24 6.01339e-05 +25 chanx_left_in[12]:25 6.696607e-05 +26 chanx_left_in[12]:26 0.0003904224 +27 chanx_left_in[12]:27 0.0003658918 +28 chanx_left_in[12]:28 0.001465184 +29 chanx_left_in[12]:29 0.001465184 +30 chanx_left_in[12]:30 0.000135737 +31 chanx_left_in[12]:21 chanx_left_in[0]:48 0.0008133516 +32 chanx_left_in[12]:21 chanx_left_in[0]:53 6.759408e-06 +33 chanx_left_in[12]:22 chanx_left_in[0]:49 0.0008133516 +34 chanx_left_in[12]:22 chanx_left_in[0]:54 6.759408e-06 +35 chanx_left_in[12]:28 chanx_left_in[1]:57 0.000281336 +36 chanx_left_in[12]:29 chanx_left_in[1]:58 0.000281336 +37 chanx_left_in[12]:15 chanx_left_in[6]:13 5.053702e-06 +38 chanx_left_in[12]:10 chanx_left_in[6]:13 0.000834647 +39 chanx_left_in[12]:9 chanx_left_in[6]:12 0.000834647 +40 chanx_left_in[12]:21 chanx_left_in[6]:26 6.306102e-06 +41 chanx_left_in[12]:21 chanx_left_in[6]:30 0.001008167 +42 chanx_left_in[12]:22 chanx_left_in[6] 0.001008167 +43 chanx_left_in[12]:22 chanx_left_in[6]:27 6.306102e-06 +44 chanx_left_in[12]:14 chanx_left_in[6]:12 5.053702e-06 +45 chanx_left_in[12]:21 chanx_left_in[10]:36 0.0002816679 +46 chanx_left_in[12]:21 chanx_left_in[10]:38 1.616842e-05 +47 chanx_left_in[12]:22 chanx_left_in[10] 1.616842e-05 +48 chanx_left_in[12]:22 chanx_left_in[10]:37 0.0002816679 +49 chanx_left_in[12]:21 chanx_right_in[0]:29 6.105272e-06 +50 chanx_left_in[12]:21 chanx_right_in[0]:27 5.915314e-06 +51 chanx_left_in[12]:22 chanx_right_in[0]:26 5.915314e-06 +52 chanx_left_in[12]:22 chanx_right_in[0]:28 6.105272e-06 +53 chanx_left_in[12]:28 chanx_right_in[0]:16 0.0002806464 +54 chanx_left_in[12]:29 chanx_right_in[0]:15 0.0002806464 +55 chanx_left_in[12]:28 ropt_net_125:4 0.0003500416 +56 chanx_left_in[12]:29 ropt_net_125:5 0.0003500416 +57 chanx_left_in[12]:28 ropt_net_137:5 7.23797e-05 +58 chanx_left_in[12]:29 ropt_net_137:4 7.23797e-05 +59 chanx_left_in[12]:27 ropt_net_134:5 4.584894e-05 +60 chanx_left_in[12]:28 ropt_net_134:8 7.228764e-07 +61 chanx_left_in[12]:28 ropt_net_134:4 0.000205279 +62 chanx_left_in[12]:29 ropt_net_134:7 7.228764e-07 +63 chanx_left_in[12]:29 ropt_net_134:3 0.000205279 +64 chanx_left_in[12]:26 ropt_net_134:6 4.584894e-05 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:30 0.000238525 +1 chanx_left_in[12]:15 chanx_left_in[12]:14 0.01433482 +2 chanx_left_in[12]:16 chanx_left_in[12]:15 0.0045 +3 chanx_left_in[12]:12 chanx_left_in[12]:11 0.0045 +4 chanx_left_in[12]:11 chanx_left_in[12]:10 0.00341 +5 chanx_left_in[12]:10 chanx_left_in[12]:9 0.003162317 +6 chanx_left_in[12]:8 chanx_left_in[12]:7 0.0045 +7 chanx_left_in[12]:9 chanx_left_in[12]:8 0.00341 +8 chanx_left_in[12]:7 chanx_left_in[12]:6 0.001261161 +9 chanx_left_in[12]:6 ropt_mt_inst_714:A 0.152 +10 chanx_left_in[12]:20 chanx_left_in[12]:19 0.0001850962 +11 chanx_left_in[12]:21 chanx_left_in[12]:20 0.00341 +12 chanx_left_in[12]:23 chanx_left_in[12]:22 0.00341 +13 chanx_left_in[12]:22 chanx_left_in[12]:21 0.008357382 +14 chanx_left_in[12]:25 chanx_left_in[12]:24 0.0045 +15 chanx_left_in[12]:25 chanx_left_in[12]:5 0.0004107143 +16 chanx_left_in[12]:24 chanx_left_in[12]:23 0.000515625 +17 chanx_left_in[12]:4 mux_bottom_ipin_8\/mux_l2_in_1_:A0 0.152 +18 chanx_left_in[12]:18 chanx_left_in[12]:17 0.0001277174 +19 chanx_left_in[12]:19 chanx_left_in[12]:18 0.0045 +20 chanx_left_in[12]:19 chanx_left_in[12]:16 0.0078125 +21 chanx_left_in[12]:17 mux_bottom_ipin_12\/mux_l2_in_1_:A0 0.152 +22 chanx_left_in[12]:27 chanx_left_in[12]:26 0.005299108 +23 chanx_left_in[12]:28 chanx_left_in[12]:27 0.0045 +24 chanx_left_in[12]:29 chanx_left_in[12]:28 0.03603349 +25 chanx_left_in[12]:30 chanx_left_in[12]:29 0.00341 +26 chanx_left_in[12]:26 chanx_left_in[12]:25 0.0003035715 +27 chanx_left_in[12]:5 chanx_left_in[12]:4 0.0003035715 +28 chanx_left_in[12]:14 chanx_left_in[12]:13 0.0003035715 +29 chanx_left_in[12]:13 chanx_left_in[12]:12 0.00078125 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[2] 0.003842131 //LENGTH 29.970 LUMPCC 0.0003244034 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 91.385 71.740 +*I mux_bottom_ipin_15\/mux_l3_in_0_:S I *L 0.00357 *C 87.300 58.480 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 84.815 66.300 +*I mux_bottom_ipin_15\/mux_l3_in_1_:S I *L 0.00357 *C 93.040 61.540 +*N mux_tree_tapbuf_size8_7_sram[2]:4 *C 93.002 61.540 +*N mux_tree_tapbuf_size8_7_sram[2]:5 *C 92.505 61.540 +*N mux_tree_tapbuf_size8_7_sram[2]:6 *C 92.460 61.585 +*N mux_tree_tapbuf_size8_7_sram[2]:7 *C 84.853 66.300 +*N mux_tree_tapbuf_size8_7_sram[2]:8 *C 86.940 66.300 +*N mux_tree_tapbuf_size8_7_sram[2]:9 *C 87.285 58.480 +*N mux_tree_tapbuf_size8_7_sram[2]:10 *C 86.963 58.480 +*N mux_tree_tapbuf_size8_7_sram[2]:11 *C 86.940 58.525 +*N mux_tree_tapbuf_size8_7_sram[2]:12 *C 86.940 65.915 +*N mux_tree_tapbuf_size8_7_sram[2]:13 *C 86.940 65.960 +*N mux_tree_tapbuf_size8_7_sram[2]:14 *C 92.415 65.960 +*N mux_tree_tapbuf_size8_7_sram[2]:15 *C 92.460 65.960 +*N mux_tree_tapbuf_size8_7_sram[2]:16 *C 92.460 71.695 +*N mux_tree_tapbuf_size8_7_sram[2]:17 *C 92.415 71.740 +*N mux_tree_tapbuf_size8_7_sram[2]:18 *C 91.422 71.740 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_15\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_7_sram[2]:4 7.122537e-05 +5 mux_tree_tapbuf_size8_7_sram[2]:5 7.122537e-05 +6 mux_tree_tapbuf_size8_7_sram[2]:6 0.0002385256 +7 mux_tree_tapbuf_size8_7_sram[2]:7 0.0001749643 +8 mux_tree_tapbuf_size8_7_sram[2]:8 0.0002045694 +9 mux_tree_tapbuf_size8_7_sram[2]:9 4.395103e-05 +10 mux_tree_tapbuf_size8_7_sram[2]:10 4.395103e-05 +11 mux_tree_tapbuf_size8_7_sram[2]:11 0.000363783 +12 mux_tree_tapbuf_size8_7_sram[2]:12 0.000363783 +13 mux_tree_tapbuf_size8_7_sram[2]:13 0.0004532803 +14 mux_tree_tapbuf_size8_7_sram[2]:14 0.0004236752 +15 mux_tree_tapbuf_size8_7_sram[2]:15 0.0005614415 +16 mux_tree_tapbuf_size8_7_sram[2]:16 0.0002927078 +17 mux_tree_tapbuf_size8_7_sram[2]:17 0.0001033225 +18 mux_tree_tapbuf_size8_7_sram[2]:18 0.0001033225 +19 mux_tree_tapbuf_size8_7_sram[2]:12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001331791 +20 mux_tree_tapbuf_size8_7_sram[2]:10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.902257e-05 +21 mux_tree_tapbuf_size8_7_sram[2]:11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001331791 +22 mux_tree_tapbuf_size8_7_sram[2]:9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.902257e-05 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_7_sram[2]:18 0.152 +1 mux_tree_tapbuf_size8_7_sram[2]:7 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size8_7_sram[2]:14 mux_tree_tapbuf_size8_7_sram[2]:13 0.004888393 +3 mux_tree_tapbuf_size8_7_sram[2]:15 mux_tree_tapbuf_size8_7_sram[2]:14 0.0045 +4 mux_tree_tapbuf_size8_7_sram[2]:15 mux_tree_tapbuf_size8_7_sram[2]:6 0.00390625 +5 mux_tree_tapbuf_size8_7_sram[2]:5 mux_tree_tapbuf_size8_7_sram[2]:4 0.0004441965 +6 mux_tree_tapbuf_size8_7_sram[2]:6 mux_tree_tapbuf_size8_7_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size8_7_sram[2]:4 mux_bottom_ipin_15\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size8_7_sram[2]:13 mux_tree_tapbuf_size8_7_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size8_7_sram[2]:13 mux_tree_tapbuf_size8_7_sram[2]:8 0.0003035715 +10 mux_tree_tapbuf_size8_7_sram[2]:12 mux_tree_tapbuf_size8_7_sram[2]:11 0.006598215 +11 mux_tree_tapbuf_size8_7_sram[2]:10 mux_tree_tapbuf_size8_7_sram[2]:9 0.0001752718 +12 mux_tree_tapbuf_size8_7_sram[2]:11 mux_tree_tapbuf_size8_7_sram[2]:10 0.0045 +13 mux_tree_tapbuf_size8_7_sram[2]:9 mux_bottom_ipin_15\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size8_7_sram[2]:17 mux_tree_tapbuf_size8_7_sram[2]:16 0.0045 +15 mux_tree_tapbuf_size8_7_sram[2]:16 mux_tree_tapbuf_size8_7_sram[2]:15 0.005120536 +16 mux_tree_tapbuf_size8_7_sram[2]:18 mux_tree_tapbuf_size8_7_sram[2]:17 0.0008861608 +17 mux_tree_tapbuf_size8_7_sram[2]:8 mux_tree_tapbuf_size8_7_sram[2]:7 0.001863839 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005941572 //LENGTH 5.035 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_1_:X O *L 0 *C 57.215 61.880 +*I mux_bottom_ipin_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 55.490 64.260 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 55.528 64.260 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 56.535 64.260 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 56.580 64.215 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 56.580 61.925 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 56.625 61.880 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 57.178 61.880 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.810301e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.810301e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001418608 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001418608 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.611484e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.611484e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008995536 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003983711 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l3_in_1_:X O *L 0 *C 58.595 15.640 +*I mux_bottom_ipin_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 58.250 17.000 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 58.250 17.000 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 58.420 17.000 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 58.420 16.955 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 58.420 15.685 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 58.420 15.640 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 58.595 15.640 + +*CAP +0 mux_bottom_ipin_4\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.100937e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.378787e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 8.641052e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 8.641052e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.814827e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.060457e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l3_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_4\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.001133929 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006925286 //LENGTH 4.690 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_2_:X O *L 0 *C 10.755 26.520 +*I mux_bottom_ipin_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 9.660 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 9.660 28.900 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 9.660 28.855 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 9.660 26.520 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 9.705 26.520 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 10.718 26.520 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.391867e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000213659 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002459625 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.849425e-05 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.849425e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_2_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002084821 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006320113 //LENGTH 3.780 LUMPCC 0.0003768069 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_0_:X O *L 0 *C 17.195 58.140 +*I mux_bottom_ipin_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 13.705 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 13.743 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 17.158 58.140 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001266022 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001266022 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_right_in[19]:16 0.0001396402 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[19]:17 0.0001396402 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:4 4.876324e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:5 4.876324e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003049107 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008167168 //LENGTH 6.495 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_2_:X O *L 0 *C 59.625 26.180 +*I mux_bottom_ipin_12\/mux_l2_in_1_:A1 I *L 0.00198 *C 62.200 28.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 62.163 28.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 59.385 28.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 59.340 28.855 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 59.340 26.225 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 59.340 26.180 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 59.625 26.180 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001749973 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001749973 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000170797 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000170797 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.121059e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.191761e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_2_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002479911 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET optlc_net_108 0.01379747 //LENGTH 100.145 LUMPCC 0.002966879 DR + +*CONN +*I optlc_110:HI O *L 0 *C 76.360 27.880 +*I mux_bottom_ipin_13\/mux_l2_in_3_:A0 I *L 0.001631 *C 71.590 55.080 +*I mux_bottom_ipin_15\/mux_l2_in_3_:A0 I *L 0.001631 *C 90.890 55.420 +*I mux_bottom_ipin_12\/mux_l2_in_3_:A0 I *L 0.001631 *C 67.450 27.880 +*I mux_bottom_ipin_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 70.670 15.300 +*I mux_bottom_ipin_14\/mux_l2_in_3_:A0 I *L 0.001631 *C 75.615 15.640 +*I mux_top_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 85.850 20.740 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 85.390 28.220 +*N optlc_net_108:8 *C 85.390 28.220 +*N optlc_net_108:9 *C 85.850 20.740 +*N optlc_net_108:10 *C 75.578 15.640 +*N optlc_net_108:11 *C 70.708 15.300 +*N optlc_net_108:12 *C 74.060 15.300 +*N optlc_net_108:13 *C 74.060 15.640 +*N optlc_net_108:14 *C 74.060 15.685 +*N optlc_net_108:15 *C 74.060 20.695 +*N optlc_net_108:16 *C 74.105 20.740 +*N optlc_net_108:17 *C 85.515 20.740 +*N optlc_net_108:18 *C 85.560 20.785 +*N optlc_net_108:19 *C 85.560 28.175 +*N optlc_net_108:20 *C 85.560 28.220 +*N optlc_net_108:21 *C 85.560 28.560 +*N optlc_net_108:22 *C 76.398 28.560 +*N optlc_net_108:23 *C 76.360 28.560 +*N optlc_net_108:24 *C 67.487 27.880 +*N optlc_net_108:25 *C 90.853 55.420 +*N optlc_net_108:26 *C 85.605 55.420 +*N optlc_net_108:27 *C 85.560 55.420 +*N optlc_net_108:28 *C 85.560 55.080 +*N optlc_net_108:29 *C 85.553 55.080 +*N optlc_net_108:30 *C 71.590 55.080 +*N optlc_net_108:31 *C 71.760 55.080 +*N optlc_net_108:32 *C 71.760 55.080 +*N optlc_net_108:33 *C 71.767 55.080 +*N optlc_net_108:34 *C 72.680 55.080 +*N optlc_net_108:35 *C 72.680 55.073 +*N optlc_net_108:36 *C 72.680 32.648 +*N optlc_net_108:37 *C 72.700 32.640 +*N optlc_net_108:38 *C 73.593 32.640 +*N optlc_net_108:39 *C 73.600 32.583 +*N optlc_net_108:40 *C 73.600 27.925 +*N optlc_net_108:41 *C 73.600 27.880 +*N optlc_net_108:42 *C 76.323 27.880 +*N optlc_net_108:43 *C 76.360 27.880 + +*CAP +0 optlc_110:HI 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_15\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_3_:A0 1e-06 +4 mux_bottom_ipin_4\/mux_l2_in_3_:A0 1e-06 +5 mux_bottom_ipin_14\/mux_l2_in_3_:A0 1e-06 +6 mux_top_ipin_0\/mux_l2_in_3_:A0 1e-06 +7 mux_bottom_ipin_0\/mux_l2_in_3_:A0 1e-06 +8 optlc_net_108:8 3.909606e-05 +9 optlc_net_108:9 5.2935e-05 +10 optlc_net_108:10 0.0001362715 +11 optlc_net_108:11 0.0002242018 +12 optlc_net_108:12 0.0002536981 +13 optlc_net_108:13 0.0001657679 +14 optlc_net_108:14 0.0003052023 +15 optlc_net_108:15 0.0003052023 +16 optlc_net_108:16 0.0006579636 +17 optlc_net_108:17 0.0006838087 +18 optlc_net_108:18 0.0004128236 +19 optlc_net_108:19 0.0004128236 +20 optlc_net_108:20 6.262762e-05 +21 optlc_net_108:21 0.0003362836 +22 optlc_net_108:22 0.0003169888 +23 optlc_net_108:23 1e-06 +24 optlc_net_108:24 0.0003207943 +25 optlc_net_108:25 0.0004723124 +26 optlc_net_108:26 0.0004723124 +27 optlc_net_108:27 5.857472e-05 +28 optlc_net_108:28 6.219301e-05 +29 optlc_net_108:29 0.0004765337 +30 optlc_net_108:30 5.600421e-05 +31 optlc_net_108:31 6.036656e-05 +32 optlc_net_108:32 3.914577e-05 +33 optlc_net_108:33 4.546092e-05 +34 optlc_net_108:34 0.0005219947 +35 optlc_net_108:35 0.001231548 +36 optlc_net_108:36 0.001231548 +37 optlc_net_108:37 9.393279e-05 +38 optlc_net_108:38 9.393279e-05 +39 optlc_net_108:39 0.0003048265 +40 optlc_net_108:40 0.0003048265 +41 optlc_net_108:41 0.0004823106 +42 optlc_net_108:42 0.0001262774 +43 optlc_net_108:43 1e-06 +44 optlc_net_108:29 chanx_left_in[13]:8 0.0002119931 +45 optlc_net_108:29 chanx_left_in[13]:13 6.162326e-05 +46 optlc_net_108:36 chanx_left_in[13]:15 1.69765e-06 +47 optlc_net_108:34 chanx_left_in[13]:13 0.0002330187 +48 optlc_net_108:34 chanx_left_in[13]:14 6.162326e-05 +49 optlc_net_108:35 chanx_left_in[13]:16 1.69765e-06 +50 optlc_net_108:33 chanx_left_in[13]:14 2.102564e-05 +51 optlc_net_108:36 chanx_left_in[17]:19 0.0002636022 +52 optlc_net_108:35 chanx_left_in[17]:20 0.0002636022 +53 optlc_net_108:22 chanx_right_in[0]:44 5.37399e-05 +54 optlc_net_108:22 chanx_right_in[0]:46 0.0001073104 +55 optlc_net_108:20 chanx_right_in[0]:47 4.802705e-06 +56 optlc_net_108:42 chanx_right_in[0]:45 0.00010696 +57 optlc_net_108:41 chanx_right_in[0]:44 0.00010696 +58 optlc_net_108:41 chanx_right_in[0]:45 0.0001083074 +59 optlc_net_108:40 chanx_right_in[0]:42 4.039532e-08 +60 optlc_net_108:39 chanx_right_in[0]:43 4.039532e-08 +61 optlc_net_108:24 chanx_right_in[0]:44 0.0001083074 +62 optlc_net_108:8 chanx_right_in[0]:46 4.802705e-06 +63 optlc_net_108:21 chanx_right_in[0]:45 5.37399e-05 +64 optlc_net_108:21 chanx_right_in[0]:47 0.0001073104 +65 optlc_net_108:29 chanx_right_in[11]:30 0.0002504172 +66 optlc_net_108:34 chanx_right_in[11]:29 0.0002504172 +67 optlc_net_108:34 chanx_right_in[11]:30 2.01801e-05 +68 optlc_net_108:33 chanx_right_in[11]:29 2.01801e-05 +69 optlc_net_108:16 chanx_right_in[16]:19 1.318892e-06 +70 optlc_net_108:16 chanx_right_in[16]:21 3.657068e-05 +71 optlc_net_108:22 chanx_right_in[16]:6 0.0001420195 +72 optlc_net_108:22 chanx_right_in[16]:9 6.126802e-05 +73 optlc_net_108:22 chanx_right_in[16]:24 9.61067e-06 +74 optlc_net_108:17 chanx_right_in[16]:18 1.318892e-06 +75 optlc_net_108:17 chanx_right_in[16]:20 3.657068e-05 +76 optlc_net_108:41 chanx_right_in[16]:8 3.210409e-06 +77 optlc_net_108:41 chanx_right_in[16]:24 1.774117e-05 +78 optlc_net_108:24 chanx_right_in[16]:7 3.210409e-06 +79 optlc_net_108:24 chanx_right_in[16]:9 1.774117e-05 +80 optlc_net_108:21 chanx_right_in[16]:5 0.0001420195 +81 optlc_net_108:21 chanx_right_in[16]:24 6.126802e-05 +82 optlc_net_108:21 chanx_right_in[16]:25 9.61067e-06 + +*RES +0 optlc_110:HI optlc_net_108:43 1e-05 +1 optlc_net_108:28 optlc_net_108:27 0.0001634615 +2 optlc_net_108:29 optlc_net_108:28 0.00341 +3 optlc_net_108:26 optlc_net_108:25 0.004685268 +4 optlc_net_108:27 optlc_net_108:26 0.0045 +5 optlc_net_108:25 mux_bottom_ipin_15\/mux_l2_in_3_:A0 0.152 +6 optlc_net_108:16 optlc_net_108:15 0.0045 +7 optlc_net_108:15 optlc_net_108:14 0.004473215 +8 optlc_net_108:13 optlc_net_108:12 0.0003035715 +9 optlc_net_108:13 optlc_net_108:10 0.001354911 +10 optlc_net_108:14 optlc_net_108:13 0.0045 +11 optlc_net_108:22 optlc_net_108:21 0.008180804 +12 optlc_net_108:17 optlc_net_108:16 0.0101875 +13 optlc_net_108:17 optlc_net_108:9 0.0001820652 +14 optlc_net_108:18 optlc_net_108:17 0.0045 +15 optlc_net_108:20 optlc_net_108:19 0.0045 +16 optlc_net_108:20 optlc_net_108:8 9.239131e-05 +17 optlc_net_108:19 optlc_net_108:18 0.006598215 +18 optlc_net_108:42 optlc_net_108:41 0.002430804 +19 optlc_net_108:11 mux_bottom_ipin_4\/mux_l2_in_3_:A0 0.152 +20 optlc_net_108:41 optlc_net_108:40 0.0045 +21 optlc_net_108:41 optlc_net_108:24 0.005457589 +22 optlc_net_108:40 optlc_net_108:39 0.004158482 +23 optlc_net_108:39 optlc_net_108:38 0.00341 +24 optlc_net_108:38 optlc_net_108:37 0.000139825 +25 optlc_net_108:37 optlc_net_108:36 0.00341 +26 optlc_net_108:36 optlc_net_108:35 0.00351325 +27 optlc_net_108:34 optlc_net_108:33 0.0001429583 +28 optlc_net_108:34 optlc_net_108:29 0.002016691 +29 optlc_net_108:35 optlc_net_108:34 0.00341 +30 optlc_net_108:10 mux_bottom_ipin_14\/mux_l2_in_3_:A0 0.152 +31 optlc_net_108:24 mux_bottom_ipin_12\/mux_l2_in_3_:A0 0.152 +32 optlc_net_108:9 mux_top_ipin_0\/mux_l2_in_3_:A0 0.152 +33 optlc_net_108:8 mux_bottom_ipin_0\/mux_l2_in_3_:A0 0.152 +34 optlc_net_108:32 optlc_net_108:31 0.0045 +35 optlc_net_108:33 optlc_net_108:32 0.00341 +36 optlc_net_108:31 optlc_net_108:30 9.239131e-05 +37 optlc_net_108:30 mux_bottom_ipin_13\/mux_l2_in_3_:A0 0.152 +38 optlc_net_108:12 optlc_net_108:11 0.002993304 +39 optlc_net_108:21 optlc_net_108:20 0.0003035715 +40 optlc_net_108:23 optlc_net_108:22 0.152 +41 optlc_net_108:43 optlc_net_108:42 0.152 +42 optlc_net_108:43 optlc_net_108:23 0.01596089 + +*END + +*D_NET chanx_right_out[9] 0.001456879 //LENGTH 12.920 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_713:X O *L 0 *C 94.300 69.020 +*P chanx_right_out[9] O *L 0.7423 *C 103.650 72.080 +*N chanx_right_out[9]:2 *C 94.308 72.080 +*N chanx_right_out[9]:3 *C 94.300 72.023 +*N chanx_right_out[9]:4 *C 94.300 69.065 +*N chanx_right_out[9]:5 *C 94.300 69.020 + +*CAP +0 ropt_mt_inst_713:X 1e-06 +1 chanx_right_out[9] 0.0005428378 +2 chanx_right_out[9]:2 0.0005428378 +3 chanx_right_out[9]:3 0.0001694906 +4 chanx_right_out[9]:4 0.0001694906 +5 chanx_right_out[9]:5 3.1222e-05 + +*RES +0 ropt_mt_inst_713:X chanx_right_out[9]:5 0.152 +1 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0045 +2 chanx_right_out[9]:4 chanx_right_out[9]:3 0.002640625 +3 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +4 chanx_right_out[9]:2 chanx_right_out[9] 0.001463658 + +*END + +*D_NET chanx_left_out[16] 0.0014159 //LENGTH 12.205 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_719:X O *L 0 *C 4.140 6.120 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 4.080 +*N chanx_left_out[16]:2 *C 7.353 4.080 +*N chanx_left_out[16]:3 *C 7.360 4.138 +*N chanx_left_out[16]:4 *C 7.360 6.075 +*N chanx_left_out[16]:5 *C 7.315 6.120 +*N chanx_left_out[16]:6 *C 4.178 6.120 + +*CAP +0 ropt_mt_inst_719:X 1e-06 +1 chanx_left_out[16] 0.0003528158 +2 chanx_left_out[16]:2 0.0003528158 +3 chanx_left_out[16]:3 0.000123624 +4 chanx_left_out[16]:4 0.000123624 +5 chanx_left_out[16]:5 0.0002310099 +6 chanx_left_out[16]:6 0.0002310099 + +*RES +0 ropt_mt_inst_719:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +2 chanx_left_out[16]:2 chanx_left_out[16] 0.0009591916 +3 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +4 chanx_left_out[16]:4 chanx_left_out[16]:3 0.001729911 +5 chanx_left_out[16]:6 chanx_left_out[16]:5 0.002801339 + +*END + +*D_NET BUF_net_58 0.003604999 //LENGTH 31.185 LUMPCC 0.0004471205 DR + +*CONN +*I BUFT_RR_58:X O *L 0 *C 82.340 72.760 +*I BUFT_P_95:A I *L 0.001766 *C 97.980 61.200 +*N BUF_net_58:2 *C 97.980 61.200 +*N BUF_net_58:3 *C 97.980 61.245 +*N BUF_net_58:4 *C 97.980 74.075 +*N BUF_net_58:5 *C 97.935 74.120 +*N BUF_net_58:6 *C 83.765 74.120 +*N BUF_net_58:7 *C 83.720 74.075 +*N BUF_net_58:8 *C 83.720 72.805 +*N BUF_net_58:9 *C 83.675 72.760 +*N BUF_net_58:10 *C 82.377 72.760 + +*CAP +0 BUFT_RR_58:X 1e-06 +1 BUFT_P_95:A 1e-06 +2 BUF_net_58:2 3.585229e-05 +3 BUF_net_58:3 0.0005270996 +4 BUF_net_58:4 0.0005270996 +5 BUF_net_58:5 0.0008500404 +6 BUF_net_58:6 0.0008500404 +7 BUF_net_58:7 7.891063e-05 +8 BUF_net_58:8 7.891063e-05 +9 BUF_net_58:9 0.0001039624 +10 BUF_net_58:10 0.0001039624 +11 BUF_net_58:3 ropt_net_152:5 0.0001370913 +12 BUF_net_58:4 ropt_net_152:4 0.0001370913 +13 BUF_net_58:3 chanx_right_out[7]:4 8.646892e-05 +14 BUF_net_58:4 chanx_right_out[7]:3 8.646892e-05 + +*RES +0 BUFT_RR_58:X BUF_net_58:10 0.152 +1 BUF_net_58:2 BUFT_P_95:A 0.152 +2 BUF_net_58:3 BUF_net_58:2 0.0045 +3 BUF_net_58:5 BUF_net_58:4 0.0045 +4 BUF_net_58:4 BUF_net_58:3 0.01145536 +5 BUF_net_58:6 BUF_net_58:5 0.01265179 +6 BUF_net_58:7 BUF_net_58:6 0.0045 +7 BUF_net_58:9 BUF_net_58:8 0.0045 +8 BUF_net_58:8 BUF_net_58:7 0.001133929 +9 BUF_net_58:10 BUF_net_58:9 0.001158482 + +*END + +*D_NET chanx_left_out[9] 0.0008231634 //LENGTH 6.125 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 7.095 72.080 +*P chanx_left_out[9] O *L 0.7423 *C 1.230 72.080 +*N chanx_left_out[9]:2 *C 6.893 72.080 +*N chanx_left_out[9]:3 *C 6.900 72.080 +*N chanx_left_out[9]:4 *C 6.900 72.080 +*N chanx_left_out[9]:5 *C 7.095 72.080 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 chanx_left_out[9] 0.0003446446 +2 chanx_left_out[9]:2 0.0003446446 +3 chanx_left_out[9]:3 3.206505e-05 +4 chanx_left_out[9]:4 4.972037e-05 +5 chanx_left_out[9]:5 5.108889e-05 + +*RES +0 ropt_mt_inst_732:X chanx_left_out[9]:5 0.152 +1 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0001059783 +2 chanx_left_out[9]:4 chanx_left_out[9]:3 0.0045 +3 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +4 chanx_left_out[9]:2 chanx_left_out[9] 0.0008871249 + +*END + +*D_NET ropt_net_127 0.00331356 //LENGTH 27.400 LUMPCC 0.0001283271 DR + +*CONN +*I BUFT_P_89:X O *L 0 *C 13.800 12.920 +*I ropt_mt_inst_726:A I *L 0.001766 *C 11.040 17.680 +*N ropt_net_127:2 *C 11.040 17.680 +*N ropt_net_127:3 *C 11.040 18.360 +*N ropt_net_127:4 *C 2.345 18.360 +*N ropt_net_127:5 *C 2.300 18.315 +*N ropt_net_127:6 *C 2.300 12.965 +*N ropt_net_127:7 *C 2.345 12.920 +*N ropt_net_127:8 *C 13.763 12.920 + +*CAP +0 BUFT_P_89:X 1e-06 +1 ropt_mt_inst_726:A 1e-06 +2 ropt_net_127:2 7.623082e-05 +3 ropt_net_127:3 0.0005568243 +4 ropt_net_127:4 0.0005092869 +5 ropt_net_127:5 0.0002938063 +6 ropt_net_127:6 0.0002938063 +7 ropt_net_127:7 0.0007266391 +8 ropt_net_127:8 0.0007266391 +9 ropt_net_127:6 ropt_net_150:5 4.775384e-08 +10 ropt_net_127:4 ropt_net_150:2 5.396783e-05 +11 ropt_net_127:4 ropt_net_150:9 1.014798e-05 +12 ropt_net_127:5 ropt_net_150:4 4.775384e-08 +13 ropt_net_127:3 ropt_net_150:3 5.396783e-05 +14 ropt_net_127:3 ropt_net_150:10 1.014798e-05 + +*RES +0 BUFT_P_89:X ropt_net_127:8 0.152 +1 ropt_net_127:8 ropt_net_127:7 0.0101942 +2 ropt_net_127:7 ropt_net_127:6 0.0045 +3 ropt_net_127:6 ropt_net_127:5 0.004776786 +4 ropt_net_127:4 ropt_net_127:3 0.007763393 +5 ropt_net_127:5 ropt_net_127:4 0.0045 +6 ropt_net_127:2 ropt_mt_inst_726:A 0.152 +7 ropt_net_127:3 ropt_net_127:2 0.0006071429 + +*END + +*D_NET chanx_left_out[11] 0.003220857 //LENGTH 18.170 LUMPCC 0.001299245 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 15.835 30.600 +*P chanx_left_out[11] O *L 0.7423 *C 1.230 29.920 +*N chanx_left_out[11]:2 *C 12.860 29.920 +*N chanx_left_out[11]:3 *C 12.880 29.928 +*N chanx_left_out[11]:4 *C 12.880 31.273 +*N chanx_left_out[11]:5 *C 12.900 31.280 +*N chanx_left_out[11]:6 *C 14.713 31.280 +*N chanx_left_out[11]:7 *C 14.720 31.223 +*N chanx_left_out[11]:8 *C 14.720 30.645 +*N chanx_left_out[11]:9 *C 14.765 30.600 +*N chanx_left_out[11]:10 *C 15.798 30.600 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 chanx_left_out[11] 0.0004718186 +2 chanx_left_out[11]:2 0.0004718186 +3 chanx_left_out[11]:3 0.0001492298 +4 chanx_left_out[11]:4 0.0001492298 +5 chanx_left_out[11]:5 0.0001724476 +6 chanx_left_out[11]:6 0.0001724476 +7 chanx_left_out[11]:7 6.681176e-05 +8 chanx_left_out[11]:8 6.681176e-05 +9 chanx_left_out[11]:9 9.999795e-05 +10 chanx_left_out[11]:10 9.999795e-05 +11 chanx_left_out[11] chanx_left_in[6] 0.0002542877 +12 chanx_left_out[11]:2 chanx_left_in[6]:30 0.0002542877 +13 chanx_left_out[11] chanx_left_in[16]:30 0.0002783287 +14 chanx_left_out[11]:6 chanx_left_in[16]:29 0.0001170062 +15 chanx_left_out[11]:5 chanx_left_in[16]:30 0.0001170062 +16 chanx_left_out[11]:2 chanx_left_in[16]:29 0.0002783287 + +*RES +0 ropt_mt_inst_776:X chanx_left_out[11]:10 0.152 +1 chanx_left_out[11]:10 chanx_left_out[11]:9 0.0009218751 +2 chanx_left_out[11]:9 chanx_left_out[11]:8 0.0045 +3 chanx_left_out[11]:8 chanx_left_out[11]:7 0.000515625 +4 chanx_left_out[11]:7 chanx_left_out[11]:6 0.00341 +5 chanx_left_out[11]:6 chanx_left_out[11]:5 0.0002839583 +6 chanx_left_out[11]:5 chanx_left_out[11]:4 0.00341 +7 chanx_left_out[11]:4 chanx_left_out[11]:3 0.0002107167 +8 chanx_left_out[11]:2 chanx_left_out[11] 0.001822033 +9 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 + +*END + +*D_NET chanx_left_in[13] 0.01914863 //LENGTH 114.860 LUMPCC 0.009246296 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 61.200 +*I mux_bottom_ipin_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 15.480 55.080 +*I mux_bottom_ipin_13\/mux_l2_in_1_:A0 I *L 0.001631 *C 75.730 55.080 +*I FTB_14__13:A I *L 0.001767 *C 97.980 47.600 +*N chanx_left_in[13]:4 *C 97.943 47.600 +*N chanx_left_in[13]:5 *C 96.645 47.600 +*N chanx_left_in[13]:6 *C 96.600 47.645 +*N chanx_left_in[13]:7 *C 96.600 53.663 +*N chanx_left_in[13]:8 *C 96.593 53.720 +*N chanx_left_in[13]:9 *C 75.730 55.080 +*N chanx_left_in[13]:10 *C 75.900 55.080 +*N chanx_left_in[13]:11 *C 75.900 55.035 +*N chanx_left_in[13]:12 *C 75.900 53.778 +*N chanx_left_in[13]:13 *C 75.900 53.720 +*N chanx_left_in[13]:14 *C 67.180 53.720 +*N chanx_left_in[13]:15 *C 67.160 53.727 +*N chanx_left_in[13]:16 *C 67.160 55.073 +*N chanx_left_in[13]:17 *C 67.140 55.080 +*N chanx_left_in[13]:18 *C 15.480 55.080 +*N chanx_left_in[13]:19 *C 15.180 55.080 +*N chanx_left_in[13]:20 *C 15.180 55.080 +*N chanx_left_in[13]:21 *C 15.180 55.080 +*N chanx_left_in[13]:22 *C 3.688 55.080 +*N chanx_left_in[13]:23 *C 3.680 55.138 +*N chanx_left_in[13]:24 *C 3.680 61.143 +*N chanx_left_in[13]:25 *C 3.673 61.200 + +*CAP +0 chanx_left_in[13] 0.0001448193 +1 mux_bottom_ipin_9\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_1_:A0 1e-06 +3 FTB_14__13:A 1e-06 +4 chanx_left_in[13]:4 0.0001075435 +5 chanx_left_in[13]:5 0.0001075435 +6 chanx_left_in[13]:6 0.0002546936 +7 chanx_left_in[13]:7 0.0002546936 +8 chanx_left_in[13]:8 0.0008057192 +9 chanx_left_in[13]:9 5.623943e-05 +10 chanx_left_in[13]:10 5.725455e-05 +11 chanx_left_in[13]:11 0.000106884 +12 chanx_left_in[13]:12 0.000106884 +13 chanx_left_in[13]:13 0.001136921 +14 chanx_left_in[13]:14 0.0003312024 +15 chanx_left_in[13]:15 0.0001298274 +16 chanx_left_in[13]:16 0.0001298274 +17 chanx_left_in[13]:17 0.002114116 +18 chanx_left_in[13]:18 5.606622e-05 +19 chanx_left_in[13]:19 5.758311e-05 +20 chanx_left_in[13]:20 4.093884e-05 +21 chanx_left_in[13]:21 0.002654696 +22 chanx_left_in[13]:22 0.0005405811 +23 chanx_left_in[13]:23 0.0002802428 +24 chanx_left_in[13]:24 0.0002802428 +25 chanx_left_in[13]:25 0.0001448193 +26 chanx_left_in[13]:21 chanx_left_in[1]:38 1.857225e-05 +27 chanx_left_in[13]:21 chanx_left_in[1]:51 0.0001329488 +28 chanx_left_in[13]:23 chanx_left_in[1]:57 0.0001252257 +29 chanx_left_in[13]:24 chanx_left_in[1]:58 0.0001252257 +30 chanx_left_in[13]:7 chanx_left_in[1]:17 1.978484e-09 +31 chanx_left_in[13]:8 chanx_left_in[1]:27 7.061751e-06 +32 chanx_left_in[13]:6 chanx_left_in[1]:18 1.978484e-09 +33 chanx_left_in[13]:13 chanx_left_in[1]:27 5.167518e-06 +34 chanx_left_in[13]:13 chanx_left_in[1]:30 7.061751e-06 +35 chanx_left_in[13]:17 chanx_left_in[1]:37 1.857225e-05 +36 chanx_left_in[13]:17 chanx_left_in[1]:50 0.0001329488 +37 chanx_left_in[13]:14 chanx_left_in[1]:30 5.167518e-06 +38 chanx_left_in[13] chanx_left_in[5] 8.978401e-07 +39 chanx_left_in[13]:21 chanx_left_in[5]:25 0.0001685592 +40 chanx_left_in[13]:21 chanx_left_in[5]:26 5.79579e-05 +41 chanx_left_in[13]:22 chanx_left_in[5] 5.79579e-05 +42 chanx_left_in[13]:25 chanx_left_in[5]:26 8.978401e-07 +43 chanx_left_in[13]:7 chanx_left_in[5]:6 3.509387e-05 +44 chanx_left_in[13]:6 chanx_left_in[5]:7 3.509387e-05 +45 chanx_left_in[13]:17 chanx_left_in[5]:24 0.0001685592 +46 chanx_left_in[13]:21 chanx_left_in[11]:27 0.0002666957 +47 chanx_left_in[13]:22 chanx_left_in[11] 0.0002666957 +48 chanx_left_in[13]:8 chanx_left_in[11]:9 2.098538e-06 +49 chanx_left_in[13]:8 chanx_left_in[11]:14 6.320931e-06 +50 chanx_left_in[13]:13 chanx_left_in[11]:14 2.098538e-06 +51 chanx_left_in[13]:13 chanx_left_in[11]:19 6.320931e-06 +52 chanx_left_in[13] chanx_left_in[17] 6.021373e-05 +53 chanx_left_in[13]:21 chanx_left_in[17]:22 0.001146893 +54 chanx_left_in[13]:25 chanx_left_in[17]:32 6.021373e-05 +55 chanx_left_in[13]:13 chanx_left_in[17]:21 3.216857e-05 +56 chanx_left_in[13]:17 chanx_left_in[17]:21 0.001146893 +57 chanx_left_in[13]:16 chanx_left_in[17]:20 1.536253e-05 +58 chanx_left_in[13]:14 chanx_left_in[17]:22 3.216857e-05 +59 chanx_left_in[13]:15 chanx_left_in[17]:19 1.536253e-05 +60 chanx_left_in[13]:21 chanx_left_in[19]:10 4.937318e-05 +61 chanx_left_in[13]:21 chanx_left_in[19]:9 0.0001931651 +62 chanx_left_in[13]:21 chanx_left_in[19]:34 1.046519e-05 +63 chanx_left_in[13]:21 chanx_left_in[19]:38 1.851132e-05 +64 chanx_left_in[13]:22 chanx_left_in[19] 1.851132e-05 +65 chanx_left_in[13]:22 chanx_left_in[19]:9 4.937318e-05 +66 chanx_left_in[13]:22 chanx_left_in[19]:35 1.046519e-05 +67 chanx_left_in[13]:17 chanx_left_in[19]:10 0.0001931651 +68 chanx_left_in[13]:21 chanx_right_in[1]:37 0.0005919043 +69 chanx_left_in[13]:8 chanx_right_in[1]:54 5.732781e-06 +70 chanx_left_in[13]:13 chanx_right_in[1]:53 5.732781e-06 +71 chanx_left_in[13]:17 chanx_right_in[1]:38 0.0005919043 +72 chanx_left_in[13]:8 chanx_right_in[3]:57 0.0003353886 +73 chanx_left_in[13]:13 chanx_right_in[3]:56 0.0003353886 +74 chanx_left_in[13]:13 chanx_right_in[3]:57 0.0003800824 +75 chanx_left_in[13]:14 chanx_right_in[3]:56 0.0003800824 +76 chanx_left_in[13]:21 chanx_right_in[11]:17 2.307222e-07 +77 chanx_left_in[13]:21 chanx_right_in[11]:16 3.633211e-07 +78 chanx_left_in[13]:21 chanx_right_in[11]:29 2.854974e-05 +79 chanx_left_in[13]:22 chanx_right_in[11]:16 2.307222e-07 +80 chanx_left_in[13]:7 chanx_right_in[11]:38 8.795824e-06 +81 chanx_left_in[13]:8 chanx_right_in[11]:37 0.0003628632 +82 chanx_left_in[13]:8 chanx_right_in[11]:40 6.262458e-05 +83 chanx_left_in[13]:8 chanx_right_in[11]:38 0.0001300646 +84 chanx_left_in[13]:6 chanx_right_in[11]:39 8.795824e-06 +85 chanx_left_in[13]:13 chanx_right_in[11]:37 0.0001300646 +86 chanx_left_in[13]:13 chanx_right_in[11]:30 9.226685e-06 +87 chanx_left_in[13]:13 chanx_right_in[11]:33 0.0003628632 +88 chanx_left_in[13]:13 chanx_right_in[11]:39 6.262458e-05 +89 chanx_left_in[13]:17 chanx_right_in[11]:17 3.633211e-07 +90 chanx_left_in[13]:17 chanx_right_in[11]:30 2.854974e-05 +91 chanx_left_in[13]:14 chanx_right_in[11]:29 9.226685e-06 +92 chanx_left_in[13]:8 optlc_net_108:29 0.0002119931 +93 chanx_left_in[13]:13 optlc_net_108:29 6.162326e-05 +94 chanx_left_in[13]:13 optlc_net_108:34 0.0002330187 +95 chanx_left_in[13]:16 optlc_net_108:35 1.69765e-06 +96 chanx_left_in[13]:14 optlc_net_108:34 6.162326e-05 +97 chanx_left_in[13]:14 optlc_net_108:33 2.102564e-05 +98 chanx_left_in[13]:15 optlc_net_108:36 1.69765e-06 +99 chanx_left_in[13]:7 ropt_net_169:4 5.82274e-05 +100 chanx_left_in[13]:6 ropt_net_169:5 5.82274e-05 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:25 0.0003826583 +1 chanx_left_in[13]:18 mux_bottom_ipin_9\/mux_l2_in_1_:A0 0.152 +2 chanx_left_in[13]:19 chanx_left_in[13]:18 0.0001630435 +3 chanx_left_in[13]:20 chanx_left_in[13]:19 0.0045 +4 chanx_left_in[13]:21 chanx_left_in[13]:20 0.00341 +5 chanx_left_in[13]:21 chanx_left_in[13]:17 0.008140399 +6 chanx_left_in[13]:23 chanx_left_in[13]:22 0.00341 +7 chanx_left_in[13]:22 chanx_left_in[13]:21 0.001800492 +8 chanx_left_in[13]:24 chanx_left_in[13]:23 0.005361607 +9 chanx_left_in[13]:25 chanx_left_in[13]:24 0.00341 +10 chanx_left_in[13]:7 chanx_left_in[13]:6 0.005372768 +11 chanx_left_in[13]:8 chanx_left_in[13]:7 0.00341 +12 chanx_left_in[13]:5 chanx_left_in[13]:4 0.001158482 +13 chanx_left_in[13]:6 chanx_left_in[13]:5 0.0045 +14 chanx_left_in[13]:4 FTB_14__13:A 0.152 +15 chanx_left_in[13]:12 chanx_left_in[13]:11 0.001122768 +16 chanx_left_in[13]:13 chanx_left_in[13]:12 0.00341 +17 chanx_left_in[13]:13 chanx_left_in[13]:8 0.003241825 +18 chanx_left_in[13]:10 chanx_left_in[13]:9 9.239131e-05 +19 chanx_left_in[13]:11 chanx_left_in[13]:10 0.0045 +20 chanx_left_in[13]:9 mux_bottom_ipin_13\/mux_l2_in_1_:A0 0.152 +21 chanx_left_in[13]:17 chanx_left_in[13]:16 0.00341 +22 chanx_left_in[13]:16 chanx_left_in[13]:15 0.0002107167 +23 chanx_left_in[13]:14 chanx_left_in[13]:13 0.001366133 +24 chanx_left_in[13]:15 chanx_left_in[13]:14 0.00341 + +*END + +*D_NET optlc_net_106 0.007900799 //LENGTH 57.995 LUMPCC 0.0007187857 DR + +*CONN +*I optlc_106:HI O *L 0 *C 28.980 44.200 +*I mux_bottom_ipin_7\/mux_l2_in_3_:A0 I *L 0.001631 *C 29.730 55.420 +*I mux_bottom_ipin_11\/mux_l2_in_3_:A0 I *L 0.001631 *C 31.455 44.200 +*I mux_bottom_ipin_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 51.810 60.520 +*I mux_bottom_ipin_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 54.570 44.200 +*I mux_bottom_ipin_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 38.815 44.200 +*N optlc_net_106:6 *C 38.778 44.200 +*N optlc_net_106:7 *C 54.570 44.200 +*N optlc_net_106:8 *C 54.740 44.200 +*N optlc_net_106:9 *C 54.740 44.200 +*N optlc_net_106:10 *C 54.733 44.200 +*N optlc_net_106:11 *C 51.848 60.520 +*N optlc_net_106:12 *C 52.395 60.520 +*N optlc_net_106:13 *C 52.440 60.520 +*N optlc_net_106:14 *C 52.433 60.520 +*N optlc_net_106:15 *C 51.540 60.520 +*N optlc_net_106:16 *C 51.520 60.513 +*N optlc_net_106:17 *C 51.520 44.208 +*N optlc_net_106:18 *C 51.520 44.200 +*N optlc_net_106:19 *C 38.188 44.200 +*N optlc_net_106:20 *C 38.180 44.200 +*N optlc_net_106:21 *C 38.180 44.200 +*N optlc_net_106:22 *C 31.455 44.200 +*N optlc_net_106:23 *C 29.730 55.420 +*N optlc_net_106:24 *C 29.440 55.420 +*N optlc_net_106:25 *C 29.440 55.375 +*N optlc_net_106:26 *C 29.440 44.245 +*N optlc_net_106:27 *C 29.440 44.200 +*N optlc_net_106:28 *C 29.018 44.200 + +*CAP +0 optlc_106:HI 1e-06 +1 mux_bottom_ipin_7\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_11\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_1\/mux_l2_in_3_:A0 1e-06 +4 mux_bottom_ipin_5\/mux_l2_in_3_:A0 1e-06 +5 mux_bottom_ipin_3\/mux_l2_in_3_:A0 1e-06 +6 optlc_net_106:6 4.936252e-05 +7 optlc_net_106:7 5.067485e-05 +8 optlc_net_106:8 4.8191e-05 +9 optlc_net_106:9 3.242787e-05 +10 optlc_net_106:10 0.0001384717 +11 optlc_net_106:11 6.315078e-05 +12 optlc_net_106:12 6.315078e-05 +13 optlc_net_106:13 3.806463e-05 +14 optlc_net_106:14 0.0001250286 +15 optlc_net_106:15 0.0001250286 +16 optlc_net_106:16 0.001043673 +17 optlc_net_106:17 0.001043673 +18 optlc_net_106:18 0.0007447756 +19 optlc_net_106:19 0.0006063039 +20 optlc_net_106:20 3.388559e-05 +21 optlc_net_106:21 0.000523033 +22 optlc_net_106:22 0.0006009844 +23 optlc_net_106:23 6.273467e-05 +24 optlc_net_106:24 6.795429e-05 +25 optlc_net_106:25 0.0007378383 +26 optlc_net_106:26 0.0007378383 +27 optlc_net_106:27 0.000200164 +28 optlc_net_106:28 3.96022e-05 +29 optlc_net_106:26 chanx_right_in[15]:10 1.360011e-07 +30 optlc_net_106:25 chanx_right_in[15]:12 1.360011e-07 +31 optlc_net_106:18 chanx_right_in[15]:18 8.40061e-05 +32 optlc_net_106:18 chanx_right_in[15]:19 0.0002752507 +33 optlc_net_106:19 chanx_right_in[15]:14 2.382635e-05 +34 optlc_net_106:19 chanx_right_in[15]:18 0.0002752507 +35 optlc_net_106:10 chanx_right_in[15]:19 6.017975e-05 + +*RES +0 optlc_106:HI optlc_net_106:28 0.152 +1 optlc_net_106:27 optlc_net_106:26 0.0045 +2 optlc_net_106:27 optlc_net_106:22 0.001799107 +3 optlc_net_106:26 optlc_net_106:25 0.0099375 +4 optlc_net_106:24 optlc_net_106:23 0.0001576087 +5 optlc_net_106:25 optlc_net_106:24 0.0045 +6 optlc_net_106:23 mux_bottom_ipin_7\/mux_l2_in_3_:A0 0.152 +7 optlc_net_106:18 optlc_net_106:17 0.00341 +8 optlc_net_106:18 optlc_net_106:10 0.0005032917 +9 optlc_net_106:17 optlc_net_106:16 0.00255445 +10 optlc_net_106:15 optlc_net_106:14 0.000139825 +11 optlc_net_106:16 optlc_net_106:15 0.00341 +12 optlc_net_106:13 optlc_net_106:12 0.0045 +13 optlc_net_106:14 optlc_net_106:13 0.00341 +14 optlc_net_106:12 optlc_net_106:11 0.0004888393 +15 optlc_net_106:11 mux_bottom_ipin_1\/mux_l2_in_3_:A0 0.152 +16 optlc_net_106:22 mux_bottom_ipin_11\/mux_l2_in_3_:A0 0.152 +17 optlc_net_106:22 optlc_net_106:21 0.006004464 +18 optlc_net_106:6 mux_bottom_ipin_3\/mux_l2_in_3_:A0 0.152 +19 optlc_net_106:20 optlc_net_106:19 0.00341 +20 optlc_net_106:19 optlc_net_106:18 0.002088758 +21 optlc_net_106:21 optlc_net_106:20 0.0045 +22 optlc_net_106:21 optlc_net_106:6 0.0005334822 +23 optlc_net_106:9 optlc_net_106:8 0.0045 +24 optlc_net_106:10 optlc_net_106:9 0.00341 +25 optlc_net_106:8 optlc_net_106:7 9.239131e-05 +26 optlc_net_106:7 mux_bottom_ipin_5\/mux_l2_in_3_:A0 0.152 +27 optlc_net_106:28 optlc_net_106:27 0.0003772322 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001185205 //LENGTH 8.530 LUMPCC 0.0001687413 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_0_:X O *L 0 *C 11.675 28.485 +*I mux_bottom_ipin_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 9.660 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 9.660 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 9.660 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 10.120 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 10.120 28.605 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 10.165 28.560 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 11.638 28.545 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.432863e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.417642e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000340384 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003027395 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001314177 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001314177 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:11 3.657602e-06 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:10 3.657602e-06 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.041562e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:9 3.029741e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.041562e-05 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.029741e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005120536 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004107143 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001325009 //LENGTH 8.480 LUMPCC 0.000423276 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_3_:X O *L 0 *C 11.325 59.160 +*I mux_bottom_ipin_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 9.375 64.260 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 9.375 64.260 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 9.200 64.260 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 9.200 64.215 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 9.200 60.565 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 9.245 60.520 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 10.995 60.520 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 11.040 60.475 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 11.040 59.205 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 11.040 59.160 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 11.325 59.160 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.912195e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.385722e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.475139e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.475139e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001492365 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001492365 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001054656 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001054656 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.965759e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.818949e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_right_in[13]:16 0.000103608 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_right_in[13]:15 0.000103608 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[13]:16 7.365876e-06 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chanx_right_in[13]:15 7.365876e-06 +16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.458536e-06 +17 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.458536e-06 +18 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.920559e-05 +19 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.920559e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_3_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003258929 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0015625 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001133929 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0004189837 //LENGTH 2.500 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l3_in_1_:X O *L 0 *C 71.125 64.600 +*I mux_bottom_ipin_13\/mux_l4_in_0_:A0 I *L 0.001631 *C 73.335 64.675 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 73.335 64.675 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 71.163 64.600 + +*CAP +0 mux_bottom_ipin_13\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002364076 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.000180576 + +*RES +0 mux_bottom_ipin_13\/mux_l3_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001939732 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_13\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0004665316 //LENGTH 3.990 LUMPCC 0 DR + +*CONN +*I mux_top_ipin_0\/mux_l4_in_0_:X O *L 0 *C 89.525 9.180 +*I mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 90.370 6.665 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 90.370 6.703 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 90.160 7.140 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 90.160 7.185 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 90.160 9.135 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 90.115 9.180 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 89.562 9.180 + +*CAP +0 mux_top_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.907983e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.029425e-05 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001159971 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001159971 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.158161e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.158161e-05 + +*RES +0 mux_top_ipin_0\/mux_l4_in_0_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0004933036 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001741071 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0003906251 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005631511 //LENGTH 3.640 LUMPCC 0.0002707843 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l1_in_0_:X O *L 0 *C 53.075 22.440 +*I mux_bottom_ipin_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 52.440 20.060 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 52.440 20.060 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 52.440 20.105 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 52.440 22.395 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 52.485 22.440 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 53.038 22.440 + +*CAP +0 mux_bottom_ipin_6\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.315073e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.606097e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.606097e-05 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.254709e-05 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.254709e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size8_2_sram[0]:10 1.18694e-06 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_2_sram[0]:11 1.18694e-06 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_2_sram[0]:12 6.710261e-05 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size8_2_sram[0]:9 6.710261e-05 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_2_sram[1]:8 6.710261e-05 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size8_2_sram[1]:12 6.710261e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l1_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004933036 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_6\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009241877 //LENGTH 7.105 LUMPCC 0.0001213014 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l3_in_1_:X O *L 0 *C 26.505 59.160 +*I mux_bottom_ipin_7\/mux_l4_in_0_:A0 I *L 0.001631 *C 25.130 64.260 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 25.168 64.260 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 26.175 64.260 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 26.220 64.215 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 26.220 59.205 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 26.220 59.160 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 26.505 59.160 + +*CAP +0 mux_bottom_ipin_7\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.81989e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.81989e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002512525 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002512525 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.880922e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.317429e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_3_sram[2]:12 6.065068e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_3_sram[2]:11 6.065068e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l3_in_1_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_7\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0008995536 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004473215 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0] 0.003910272 //LENGTH 27.920 LUMPCC 0.001709275 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l4_in_0_:X O *L 0 *C 26.855 48.280 +*I mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 24.665 71.880 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 24.130 71.400 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 24.665 71.880 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 24.840 71.740 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 24.840 71.740 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 24.840 71.400 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 24.838 71.400 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 24.840 71.392 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 24.840 48.968 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 24.860 48.960 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 26.673 48.960 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 26.680 48.903 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 26.680 48.325 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 26.680 48.280 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:15 *C 26.855 48.280 + +*CAP +0 mux_bottom_ipin_11\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.249069e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 3.815386e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.250489e-05 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.658975e-05 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.214725e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.249069e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0008037631 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0008037631 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 1.263598e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 1.263598e-05 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 5.606713e-05 +13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 5.606713e-05 +14 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:14 5.689063e-05 +15 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:15 5.27969e-05 +16 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 chanx_left_in[0]:64 0.0004431389 +17 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chanx_left_in[0]:65 0.0004431389 +18 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chanx_left_in[9]:22 0.0001214908 +19 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chanx_left_in[9]:23 0.0001214908 +20 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 chanx_left_in[19]:32 7.107831e-07 +21 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 chanx_left_in[19]:33 7.107831e-07 +22 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chanx_left_in[19]:30 0.0001214908 +23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chanx_left_in[19]:31 0.0001214908 +24 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001678064 +25 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0001678064 + +*RES +0 mux_bottom_ipin_11\/mux_l4_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:15 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:15 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:14 9.51087e-05 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0045 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0005156249 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0002839583 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.00351325 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00341 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001039141 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001634616 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.51087e-05 +13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +14 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chanx_right_out[12] 0.0008271979 //LENGTH 5.840 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_714:X O *L 0 *C 98.900 36.380 +*P chanx_right_out[12] O *L 0.7423 *C 103.650 36.720 +*N chanx_right_out[12]:2 *C 102.128 36.720 +*N chanx_right_out[12]:3 *C 102.120 36.720 +*N chanx_right_out[12]:4 *C 102.075 36.720 +*N chanx_right_out[12]:5 *C 99.820 36.720 +*N chanx_right_out[12]:6 *C 99.820 36.380 +*N chanx_right_out[12]:7 *C 98.938 36.380 + +*CAP +0 ropt_mt_inst_714:X 1e-06 +1 chanx_right_out[12] 0.0001106268 +2 chanx_right_out[12]:2 0.0001106268 +3 chanx_right_out[12]:3 3.261968e-05 +4 chanx_right_out[12]:4 0.0001825731 +5 chanx_right_out[12]:5 0.0002061054 +6 chanx_right_out[12]:6 0.0001035893 +7 chanx_right_out[12]:7 8.005691e-05 + +*RES +0 ropt_mt_inst_714:X chanx_right_out[12]:7 0.152 +1 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +2 chanx_right_out[12]:2 chanx_right_out[12] 0.000238525 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0045 +4 chanx_right_out[12]:7 chanx_right_out[12]:6 0.0007879465 +5 chanx_right_out[12]:6 chanx_right_out[12]:5 0.0003035715 +6 chanx_right_out[12]:5 chanx_right_out[12]:4 0.002013393 + +*END + +*D_NET ropt_net_152 0.0008327321 //LENGTH 5.660 LUMPCC 0.0002741826 DR + +*CONN +*I ropt_mt_inst_722:X O *L 0 *C 97.255 67.320 +*I ropt_mt_inst_751:A I *L 0.001767 *C 97.825 72.080 +*N ropt_net_152:2 *C 97.825 72.080 +*N ropt_net_152:3 *C 97.520 72.080 +*N ropt_net_152:4 *C 97.520 72.035 +*N ropt_net_152:5 *C 97.520 67.365 +*N ropt_net_152:6 *C 97.520 67.320 +*N ropt_net_152:7 *C 97.255 67.320 + +*CAP +0 ropt_mt_inst_722:X 1e-06 +1 ropt_mt_inst_751:A 1e-06 +2 ropt_net_152:2 5.08707e-05 +3 ropt_net_152:3 5.092788e-05 +4 ropt_net_152:4 0.0001677293 +5 ropt_net_152:5 0.0001677293 +6 ropt_net_152:6 5.508406e-05 +7 ropt_net_152:7 6.420829e-05 +8 ropt_net_152:4 BUF_net_58:4 0.0001370913 +9 ropt_net_152:5 BUF_net_58:3 0.0001370913 + +*RES +0 ropt_mt_inst_722:X ropt_net_152:7 0.152 +1 ropt_net_152:2 ropt_mt_inst_751:A 0.152 +2 ropt_net_152:3 ropt_net_152:2 0.0001657609 +3 ropt_net_152:4 ropt_net_152:3 0.0045 +4 ropt_net_152:6 ropt_net_152:5 0.0045 +5 ropt_net_152:5 ropt_net_152:4 0.004169643 +6 ropt_net_152:7 ropt_net_152:6 0.0001440218 + +*END + +*D_NET ccff_tail[0] 0.0006775155 //LENGTH 5.960 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_727:X O *L 0 *C 60.455 3.400 +*P ccff_tail[0] O *L 0.7423 *C 57.500 1.290 +*N ccff_tail[0]:2 *C 57.500 1.655 +*N ccff_tail[0]:3 *C 57.545 1.700 +*N ccff_tail[0]:4 *C 60.215 1.700 +*N ccff_tail[0]:5 *C 60.260 1.745 +*N ccff_tail[0]:6 *C 60.260 3.355 +*N ccff_tail[0]:7 *C 60.260 3.400 +*N ccff_tail[0]:8 *C 60.455 3.400 + +*CAP +0 ropt_mt_inst_727:X 1e-06 +1 ccff_tail[0] 2.984791e-05 +2 ccff_tail[0]:2 2.984791e-05 +3 ccff_tail[0]:3 0.0001566287 +4 ccff_tail[0]:4 0.0001566287 +5 ccff_tail[0]:5 9.76906e-05 +6 ccff_tail[0]:6 9.76906e-05 +7 ccff_tail[0]:7 5.600771e-05 +8 ccff_tail[0]:8 5.217319e-05 + +*RES +0 ropt_mt_inst_727:X ccff_tail[0]:8 0.152 +1 ccff_tail[0]:8 ccff_tail[0]:7 0.0001059783 +2 ccff_tail[0]:7 ccff_tail[0]:6 0.0045 +3 ccff_tail[0]:6 ccff_tail[0]:5 0.0014375 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.002383929 +5 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +6 ccff_tail[0]:3 ccff_tail[0]:2 0.0045 +7 ccff_tail[0]:2 ccff_tail[0] 0.0003258929 + +*END + +*D_NET ropt_net_159 0.002294944 //LENGTH 17.060 LUMPCC 0.0006777968 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 101.855 64.600 +*I ropt_mt_inst_761:A I *L 0.001766 *C 93.380 72.080 +*N ropt_net_159:2 *C 93.418 72.080 +*N ropt_net_159:3 *C 95.220 72.080 +*N ropt_net_159:4 *C 95.220 71.740 +*N ropt_net_159:5 *C 101.660 71.740 +*N ropt_net_159:6 *C 101.660 71.695 +*N ropt_net_159:7 *C 101.660 64.645 +*N ropt_net_159:8 *C 101.660 64.600 +*N ropt_net_159:9 *C 101.855 64.600 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_159:2 0.0001324176 +3 ropt_net_159:3 0.0001567356 +4 ropt_net_159:4 0.0003135696 +5 ropt_net_159:5 0.0003250682 +6 ropt_net_159:6 0.0002821338 +7 ropt_net_159:7 0.0002821338 +8 ropt_net_159:8 6.086403e-05 +9 ropt_net_159:9 6.222488e-05 +10 ropt_net_159:7 chanx_right_out[11]:4 6.186857e-05 +11 ropt_net_159:6 chanx_right_out[11]:3 6.186857e-05 +12 ropt_net_159:7 chanx_right_out[10]:4 4.950757e-05 +13 ropt_net_159:5 chanx_right_out[10]:2 2.452854e-05 +14 ropt_net_159:6 chanx_right_out[10]:3 4.950757e-05 +15 ropt_net_159:4 chanx_right_out[10]:3 2.452854e-05 +16 ropt_net_159:5 chanx_right_out[2]:7 0.0001429314 +17 ropt_net_159:4 chanx_right_out[2]:8 0.0001429314 +18 ropt_net_159:7 chanx_right_out[0]:2 6.006238e-05 +19 ropt_net_159:6 chanx_right_out[0] 6.006238e-05 + +*RES +0 ropt_mt_inst_730:X ropt_net_159:9 0.152 +1 ropt_net_159:9 ropt_net_159:8 0.0001059783 +2 ropt_net_159:8 ropt_net_159:7 0.0045 +3 ropt_net_159:7 ropt_net_159:6 0.006294643 +4 ropt_net_159:5 ropt_net_159:4 0.00575 +5 ropt_net_159:6 ropt_net_159:5 0.0045 +6 ropt_net_159:2 ropt_mt_inst_761:A 0.152 +7 ropt_net_159:3 ropt_net_159:2 0.001609375 +8 ropt_net_159:4 ropt_net_159:3 0.0003035715 + +*END + +*D_NET ropt_net_113 0.0001205376 //LENGTH 1.210 LUMPCC 0 DR + +*CONN +*I BUFT_P_102:X O *L 0 *C 87.860 4.080 +*I ropt_mt_inst_712:A I *L 0.001766 *C 88.780 4.080 +*N ropt_net_113:2 *C 88.743 4.080 +*N ropt_net_113:3 *C 87.898 4.080 + +*CAP +0 BUFT_P_102:X 1e-06 +1 ropt_mt_inst_712:A 1e-06 +2 ropt_net_113:2 5.926881e-05 +3 ropt_net_113:3 5.926881e-05 + +*RES +0 BUFT_P_102:X ropt_net_113:3 0.152 +1 ropt_net_113:2 ropt_mt_inst_712:A 0.152 +2 ropt_net_113:3 ropt_net_113:2 0.0007544643 + +*END + +*D_NET chanx_left_in[15] 0.01607084 //LENGTH 118.625 LUMPCC 0.002128958 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 39.440 +*I mux_bottom_ipin_11\/mux_l2_in_2_:A0 I *L 0.001631 *C 37.090 48.280 +*I BUFT_P_91:A I *L 0.001767 *C 93.380 42.160 +*I mux_bottom_ipin_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 57.790 47.940 +*I mux_bottom_ipin_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 38.800 49.640 +*N chanx_left_in[15]:5 *C 38.763 49.640 +*N chanx_left_in[15]:6 *C 37.305 49.640 +*N chanx_left_in[15]:7 *C 37.260 49.595 +*N chanx_left_in[15]:8 *C 57.790 47.940 +*N chanx_left_in[15]:9 *C 93.418 42.160 +*N chanx_left_in[15]:10 *C 95.635 42.160 +*N chanx_left_in[15]:11 *C 95.680 42.205 +*N chanx_left_in[15]:12 *C 95.680 42.782 +*N chanx_left_in[15]:13 *C 95.672 42.840 +*N chanx_left_in[15]:14 *C 57.508 42.840 +*N chanx_left_in[15]:15 *C 57.500 42.898 +*N chanx_left_in[15]:16 *C 57.500 47.895 +*N chanx_left_in[15]:17 *C 57.500 47.940 +*N chanx_left_in[15]:18 *C 57.500 48.280 +*N chanx_left_in[15]:19 *C 37.090 48.280 +*N chanx_left_in[15]:20 *C 37.305 48.280 +*N chanx_left_in[15]:21 *C 37.260 48.325 +*N chanx_left_in[15]:22 *C 36.800 48.280 +*N chanx_left_in[15]:23 *C 36.800 42.885 +*N chanx_left_in[15]:24 *C 36.755 42.840 +*N chanx_left_in[15]:25 *C 24.425 42.840 +*N chanx_left_in[15]:26 *C 24.380 42.795 +*N chanx_left_in[15]:27 *C 24.380 39.498 +*N chanx_left_in[15]:28 *C 24.373 39.440 + +*CAP +0 chanx_left_in[15] 0.001286031 +1 mux_bottom_ipin_11\/mux_l2_in_2_:A0 1e-06 +2 BUFT_P_91:A 1e-06 +3 mux_bottom_ipin_5\/mux_l2_in_2_:A0 1e-06 +4 mux_bottom_ipin_3\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[15]:5 0.0001378024 +6 chanx_left_in[15]:6 0.0001378024 +7 chanx_left_in[15]:7 0.0001172183 +8 chanx_left_in[15]:8 5.682018e-05 +9 chanx_left_in[15]:9 0.0001198044 +10 chanx_left_in[15]:10 0.0001198044 +11 chanx_left_in[15]:11 5.516081e-05 +12 chanx_left_in[15]:12 5.516081e-05 +13 chanx_left_in[15]:13 0.002138711 +14 chanx_left_in[15]:14 0.002138711 +15 chanx_left_in[15]:15 0.0003012178 +16 chanx_left_in[15]:16 0.0003012178 +17 chanx_left_in[15]:17 8.350599e-05 +18 chanx_left_in[15]:18 0.001359419 +19 chanx_left_in[15]:19 5.894963e-05 +20 chanx_left_in[15]:20 0.001355901 +21 chanx_left_in[15]:21 0.0001544371 +22 chanx_left_in[15]:22 0.0003644016 +23 chanx_left_in[15]:23 0.0003271828 +24 chanx_left_in[15]:24 0.0007978677 +25 chanx_left_in[15]:25 0.0007978677 +26 chanx_left_in[15]:26 0.0001934295 +27 chanx_left_in[15]:27 0.0001934295 +28 chanx_left_in[15]:28 0.001286031 +29 chanx_left_in[15] chanx_right_in[15]:8 0.0001194432 +30 chanx_left_in[15]:16 chanx_right_in[15]:23 3.268182e-06 +31 chanx_left_in[15]:15 chanx_right_in[15]:24 3.268182e-06 +32 chanx_left_in[15]:14 chanx_right_in[15]:25 5.658388e-06 +33 chanx_left_in[15]:14 chanx_right_in[15]:29 0.0001711604 +34 chanx_left_in[15]:13 chanx_right_in[15]:26 5.658388e-06 +35 chanx_left_in[15]:13 chanx_right_in[15]:30 0.0001711604 +36 chanx_left_in[15]:28 chanx_right_in[15]:9 0.0001194432 +37 chanx_left_in[15]:14 chanx_right_in[17]:25 0.0001700403 +38 chanx_left_in[15]:14 chanx_right_in[17]:27 0.0001088791 +39 chanx_left_in[15]:13 chanx_right_in[17] 0.0001088791 +40 chanx_left_in[15]:13 chanx_right_in[17]:26 0.0001700403 +41 chanx_left_in[15]:14 mux_tree_tapbuf_size10_0_sram[3]:11 0.0001832202 +42 chanx_left_in[15]:13 mux_tree_tapbuf_size10_0_sram[3]:12 0.0001832202 +43 chanx_left_in[15] mux_tree_tapbuf_size10_4_sram[3]:11 9.9503e-05 +44 chanx_left_in[15] mux_tree_tapbuf_size10_4_sram[3]:7 0.0001023226 +45 chanx_left_in[15]:28 mux_tree_tapbuf_size10_4_sram[3]:11 0.0001023226 +46 chanx_left_in[15]:28 mux_tree_tapbuf_size10_4_sram[3]:12 9.9503e-05 +47 chanx_left_in[15]:20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.917569e-05 +48 chanx_left_in[15]:18 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.917569e-05 +49 chanx_left_in[15]:10 ropt_net_144:3 6.180826e-05 +50 chanx_left_in[15]:9 ropt_net_144:4 6.180826e-05 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:28 0.003625658 +1 chanx_left_in[15]:17 chanx_left_in[15]:16 0.0045 +2 chanx_left_in[15]:17 chanx_left_in[15]:8 0.0001576087 +3 chanx_left_in[15]:16 chanx_left_in[15]:15 0.004462054 +4 chanx_left_in[15]:15 chanx_left_in[15]:14 0.00341 +5 chanx_left_in[15]:14 chanx_left_in[15]:13 0.005979183 +6 chanx_left_in[15]:12 chanx_left_in[15]:11 0.000515625 +7 chanx_left_in[15]:13 chanx_left_in[15]:12 0.00341 +8 chanx_left_in[15]:10 chanx_left_in[15]:9 0.001979911 +9 chanx_left_in[15]:11 chanx_left_in[15]:10 0.0045 +10 chanx_left_in[15]:9 BUFT_P_91:A 0.152 +11 chanx_left_in[15]:24 chanx_left_in[15]:23 0.0045 +12 chanx_left_in[15]:23 chanx_left_in[15]:22 0.004816965 +13 chanx_left_in[15]:25 chanx_left_in[15]:24 0.01100893 +14 chanx_left_in[15]:26 chanx_left_in[15]:25 0.0045 +15 chanx_left_in[15]:27 chanx_left_in[15]:26 0.002944197 +16 chanx_left_in[15]:28 chanx_left_in[15]:27 0.00341 +17 chanx_left_in[15]:20 chanx_left_in[15]:19 0.0001168478 +18 chanx_left_in[15]:20 chanx_left_in[15]:18 0.01803125 +19 chanx_left_in[15]:21 chanx_left_in[15]:20 0.0045 +20 chanx_left_in[15]:21 chanx_left_in[15]:7 0.001133929 +21 chanx_left_in[15]:8 mux_bottom_ipin_5\/mux_l2_in_2_:A0 0.152 +22 chanx_left_in[15]:6 chanx_left_in[15]:5 0.001301339 +23 chanx_left_in[15]:7 chanx_left_in[15]:6 0.0045 +24 chanx_left_in[15]:5 mux_bottom_ipin_3\/mux_l2_in_2_:A0 0.152 +25 chanx_left_in[15]:19 mux_bottom_ipin_11\/mux_l2_in_2_:A0 0.152 +26 chanx_left_in[15]:18 chanx_left_in[15]:17 0.0003035715 +27 chanx_left_in[15]:22 chanx_left_in[15]:21 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[1] 0.005207294 //LENGTH 38.150 LUMPCC 0.0002595351 DR + +*CONN +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 99.495 15.640 +*I mux_top_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 85.460 17.680 +*I mux_top_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 84.740 20.110 +*I mux_top_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 88.880 20.110 +*I mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 90.345 11.900 +*I mux_top_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 92.100 17.975 +*N mux_tree_tapbuf_size10_8_sram[1]:6 *C 92.100 17.975 +*N mux_tree_tapbuf_size10_8_sram[1]:7 *C 92.070 17.750 +*N mux_tree_tapbuf_size10_8_sram[1]:8 *C 91.955 17.610 +*N mux_tree_tapbuf_size10_8_sram[1]:9 *C 90.345 11.900 +*N mux_tree_tapbuf_size10_8_sram[1]:10 *C 90.620 11.900 +*N mux_tree_tapbuf_size10_8_sram[1]:11 *C 90.620 11.945 +*N mux_tree_tapbuf_size10_8_sram[1]:12 *C 90.620 19.675 +*N mux_tree_tapbuf_size10_8_sram[1]:13 *C 90.575 19.720 +*N mux_tree_tapbuf_size10_8_sram[1]:14 *C 88.880 19.720 +*N mux_tree_tapbuf_size10_8_sram[1]:15 *C 88.880 20.110 +*N mux_tree_tapbuf_size10_8_sram[1]:16 *C 88.843 20.400 +*N mux_tree_tapbuf_size10_8_sram[1]:17 *C 84.740 20.110 +*N mux_tree_tapbuf_size10_8_sram[1]:18 *C 84.778 20.400 +*N mux_tree_tapbuf_size10_8_sram[1]:19 *C 86.480 20.400 +*N mux_tree_tapbuf_size10_8_sram[1]:20 *C 86.480 20.355 +*N mux_tree_tapbuf_size10_8_sram[1]:21 *C 86.480 17.725 +*N mux_tree_tapbuf_size10_8_sram[1]:22 *C 86.480 17.680 +*N mux_tree_tapbuf_size10_8_sram[1]:23 *C 85.460 17.680 +*N mux_tree_tapbuf_size10_8_sram[1]:24 *C 85.460 17.340 +*N mux_tree_tapbuf_size10_8_sram[1]:25 *C 86.480 17.340 +*N mux_tree_tapbuf_size10_8_sram[1]:26 *C 92.000 17.340 +*N mux_tree_tapbuf_size10_8_sram[1]:27 *C 92.415 17.340 +*N mux_tree_tapbuf_size10_8_sram[1]:28 *C 92.460 17.295 +*N mux_tree_tapbuf_size10_8_sram[1]:29 *C 92.460 15.685 +*N mux_tree_tapbuf_size10_8_sram[1]:30 *C 92.505 15.640 +*N mux_tree_tapbuf_size10_8_sram[1]:31 *C 99.458 15.640 + +*CAP +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_ipin_0\/mux_l2_in_2_:S 1e-06 +2 mux_top_ipin_0\/mux_l2_in_3_:S 1e-06 +3 mux_top_ipin_0\/mux_l2_in_1_:S 1e-06 +4 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_top_ipin_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_8_sram[1]:6 5.907803e-05 +7 mux_tree_tapbuf_size10_8_sram[1]:7 3.85483e-05 +8 mux_tree_tapbuf_size10_8_sram[1]:8 3.662237e-05 +9 mux_tree_tapbuf_size10_8_sram[1]:9 5.388185e-05 +10 mux_tree_tapbuf_size10_8_sram[1]:10 5.751399e-05 +11 mux_tree_tapbuf_size10_8_sram[1]:11 0.0004604564 +12 mux_tree_tapbuf_size10_8_sram[1]:12 0.0004604564 +13 mux_tree_tapbuf_size10_8_sram[1]:13 0.0001481908 +14 mux_tree_tapbuf_size10_8_sram[1]:14 0.0001788891 +15 mux_tree_tapbuf_size10_8_sram[1]:15 9.003932e-05 +16 mux_tree_tapbuf_size10_8_sram[1]:16 0.000206488 +17 mux_tree_tapbuf_size10_8_sram[1]:17 6.127008e-05 +18 mux_tree_tapbuf_size10_8_sram[1]:18 0.0001683501 +19 mux_tree_tapbuf_size10_8_sram[1]:19 0.0003436906 +20 mux_tree_tapbuf_size10_8_sram[1]:20 0.0001624867 +21 mux_tree_tapbuf_size10_8_sram[1]:21 0.0001624867 +22 mux_tree_tapbuf_size10_8_sram[1]:22 5.950854e-05 +23 mux_tree_tapbuf_size10_8_sram[1]:23 4.907953e-05 +24 mux_tree_tapbuf_size10_8_sram[1]:24 5.667948e-05 +25 mux_tree_tapbuf_size10_8_sram[1]:25 0.0003944269 +26 mux_tree_tapbuf_size10_8_sram[1]:26 0.0003991371 +27 mux_tree_tapbuf_size10_8_sram[1]:27 3.659857e-05 +28 mux_tree_tapbuf_size10_8_sram[1]:28 0.0001134478 +29 mux_tree_tapbuf_size10_8_sram[1]:29 0.0001134478 +30 mux_tree_tapbuf_size10_8_sram[1]:30 0.0005154923 +31 mux_tree_tapbuf_size10_8_sram[1]:31 0.0005154923 +32 mux_tree_tapbuf_size10_8_sram[1]:12 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.948946e-05 +33 mux_tree_tapbuf_size10_8_sram[1]:11 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.948946e-05 +34 mux_tree_tapbuf_size10_8_sram[1]:28 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.133429e-06 +35 mux_tree_tapbuf_size10_8_sram[1]:29 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.133429e-06 +36 mux_tree_tapbuf_size10_8_sram[1]:25 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.337538e-05 +37 mux_tree_tapbuf_size10_8_sram[1]:26 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.337538e-05 +38 mux_tree_tapbuf_size10_8_sram[1]:24 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.87693e-05 +39 mux_tree_tapbuf_size10_8_sram[1]:25 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.87693e-05 + +*RES +0 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_8_sram[1]:31 0.152 +1 mux_tree_tapbuf_size10_8_sram[1]:13 mux_tree_tapbuf_size10_8_sram[1]:12 0.0045 +2 mux_tree_tapbuf_size10_8_sram[1]:12 mux_tree_tapbuf_size10_8_sram[1]:11 0.006901786 +3 mux_tree_tapbuf_size10_8_sram[1]:10 mux_tree_tapbuf_size10_8_sram[1]:9 0.0001494565 +4 mux_tree_tapbuf_size10_8_sram[1]:11 mux_tree_tapbuf_size10_8_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size10_8_sram[1]:9 mem_top_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +6 mux_tree_tapbuf_size10_8_sram[1]:17 mux_top_ipin_0\/mux_l2_in_3_:S 0.152 +7 mux_tree_tapbuf_size10_8_sram[1]:19 mux_tree_tapbuf_size10_8_sram[1]:18 0.001520089 +8 mux_tree_tapbuf_size10_8_sram[1]:19 mux_tree_tapbuf_size10_8_sram[1]:16 0.002109375 +9 mux_tree_tapbuf_size10_8_sram[1]:20 mux_tree_tapbuf_size10_8_sram[1]:19 0.0045 +10 mux_tree_tapbuf_size10_8_sram[1]:22 mux_tree_tapbuf_size10_8_sram[1]:21 0.0045 +11 mux_tree_tapbuf_size10_8_sram[1]:21 mux_tree_tapbuf_size10_8_sram[1]:20 0.002348214 +12 mux_tree_tapbuf_size10_8_sram[1]:27 mux_tree_tapbuf_size10_8_sram[1]:26 0.0003705357 +13 mux_tree_tapbuf_size10_8_sram[1]:28 mux_tree_tapbuf_size10_8_sram[1]:27 0.0045 +14 mux_tree_tapbuf_size10_8_sram[1]:30 mux_tree_tapbuf_size10_8_sram[1]:29 0.0045 +15 mux_tree_tapbuf_size10_8_sram[1]:29 mux_tree_tapbuf_size10_8_sram[1]:28 0.0014375 +16 mux_tree_tapbuf_size10_8_sram[1]:31 mux_tree_tapbuf_size10_8_sram[1]:30 0.00620759 +17 mux_tree_tapbuf_size10_8_sram[1]:23 mux_top_ipin_0\/mux_l2_in_2_:S 0.152 +18 mux_tree_tapbuf_size10_8_sram[1]:15 mux_top_ipin_0\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size10_8_sram[1]:15 mux_tree_tapbuf_size10_8_sram[1]:14 0.0003482143 +20 mux_tree_tapbuf_size10_8_sram[1]:6 mux_top_ipin_0\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_8_sram[1]:18 mux_tree_tapbuf_size10_8_sram[1]:17 0.000125 +22 mux_tree_tapbuf_size10_8_sram[1]:16 mux_tree_tapbuf_size10_8_sram[1]:15 0.000125 +23 mux_tree_tapbuf_size10_8_sram[1]:24 mux_tree_tapbuf_size10_8_sram[1]:23 0.0003035715 +24 mux_tree_tapbuf_size10_8_sram[1]:25 mux_tree_tapbuf_size10_8_sram[1]:24 0.0009107143 +25 mux_tree_tapbuf_size10_8_sram[1]:25 mux_tree_tapbuf_size10_8_sram[1]:22 0.0003035715 +26 mux_tree_tapbuf_size10_8_sram[1]:26 mux_tree_tapbuf_size10_8_sram[1]:25 0.004928571 +27 mux_tree_tapbuf_size10_8_sram[1]:26 mux_tree_tapbuf_size10_8_sram[1]:8 0.0002410715 +28 mux_tree_tapbuf_size10_8_sram[1]:14 mux_tree_tapbuf_size10_8_sram[1]:13 0.001513393 +29 mux_tree_tapbuf_size10_8_sram[1]:8 mux_tree_tapbuf_size10_8_sram[1]:7 0.0001026786 +30 mux_tree_tapbuf_size10_8_sram[1]:7 mux_tree_tapbuf_size10_8_sram[1]:6 0.000130814 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[0] 0.003842361 //LENGTH 32.365 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 18.245 42.500 +*I mux_bottom_ipin_10\/mux_l1_in_0_:S I *L 0.00357 *C 17.360 30.940 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 18.115 15.300 +*N mux_tree_tapbuf_size8_4_sram[0]:3 *C 18.115 15.300 +*N mux_tree_tapbuf_size8_4_sram[0]:4 *C 17.940 15.640 +*N mux_tree_tapbuf_size8_4_sram[0]:5 *C 16.605 15.640 +*N mux_tree_tapbuf_size8_4_sram[0]:6 *C 16.560 15.685 +*N mux_tree_tapbuf_size8_4_sram[0]:7 *C 17.323 30.940 +*N mux_tree_tapbuf_size8_4_sram[0]:8 *C 16.605 30.940 +*N mux_tree_tapbuf_size8_4_sram[0]:9 *C 16.560 30.940 +*N mux_tree_tapbuf_size8_4_sram[0]:10 *C 16.560 42.455 +*N mux_tree_tapbuf_size8_4_sram[0]:11 *C 16.605 42.500 +*N mux_tree_tapbuf_size8_4_sram[0]:12 *C 18.207 42.500 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_10\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_4_sram[0]:3 5.060605e-05 +4 mux_tree_tapbuf_size8_4_sram[0]:4 0.0001325457 +5 mux_tree_tapbuf_size8_4_sram[0]:5 0.0001086442 +6 mux_tree_tapbuf_size8_4_sram[0]:6 0.0009168227 +7 mux_tree_tapbuf_size8_4_sram[0]:7 7.399121e-05 +8 mux_tree_tapbuf_size8_4_sram[0]:8 7.399121e-05 +9 mux_tree_tapbuf_size8_4_sram[0]:9 0.001604295 +10 mux_tree_tapbuf_size8_4_sram[0]:10 0.0006513133 +11 mux_tree_tapbuf_size8_4_sram[0]:11 0.0001135758 +12 mux_tree_tapbuf_size8_4_sram[0]:12 0.0001135758 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_4_sram[0]:12 0.152 +1 mux_tree_tapbuf_size8_4_sram[0]:8 mux_tree_tapbuf_size8_4_sram[0]:7 0.000640625 +2 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size8_4_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size8_4_sram[0]:6 0.01362054 +4 mux_tree_tapbuf_size8_4_sram[0]:7 mux_bottom_ipin_10\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_4_sram[0]:5 mux_tree_tapbuf_size8_4_sram[0]:4 0.001191964 +6 mux_tree_tapbuf_size8_4_sram[0]:6 mux_tree_tapbuf_size8_4_sram[0]:5 0.0045 +7 mux_tree_tapbuf_size8_4_sram[0]:3 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_4_sram[0]:11 mux_tree_tapbuf_size8_4_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size8_4_sram[0]:10 mux_tree_tapbuf_size8_4_sram[0]:9 0.01028125 +10 mux_tree_tapbuf_size8_4_sram[0]:12 mux_tree_tapbuf_size8_4_sram[0]:11 0.001430804 +11 mux_tree_tapbuf_size8_4_sram[0]:4 mux_tree_tapbuf_size8_4_sram[0]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[2] 0.004103084 //LENGTH 33.565 LUMPCC 0.0003939905 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 79.695 10.200 +*I mux_bottom_ipin_14\/mux_l3_in_1_:S I *L 0.00357 *C 77.840 18.360 +*I mux_bottom_ipin_14\/mux_l3_in_0_:S I *L 0.00357 *C 78.560 23.800 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 72.390 33.660 +*N mux_tree_tapbuf_size8_6_sram[2]:4 *C 72.428 33.660 +*N mux_tree_tapbuf_size8_6_sram[2]:5 *C 78.200 33.660 +*N mux_tree_tapbuf_size8_6_sram[2]:6 *C 78.200 33.320 +*N mux_tree_tapbuf_size8_6_sram[2]:7 *C 78.200 33.275 +*N mux_tree_tapbuf_size8_6_sram[2]:8 *C 78.545 23.800 +*N mux_tree_tapbuf_size8_6_sram[2]:9 *C 78.223 23.800 +*N mux_tree_tapbuf_size8_6_sram[2]:10 *C 78.200 23.800 +*N mux_tree_tapbuf_size8_6_sram[2]:11 *C 77.855 18.360 +*N mux_tree_tapbuf_size8_6_sram[2]:12 *C 78.178 18.360 +*N mux_tree_tapbuf_size8_6_sram[2]:13 *C 78.200 18.360 +*N mux_tree_tapbuf_size8_6_sram[2]:14 *C 78.660 18.360 +*N mux_tree_tapbuf_size8_6_sram[2]:15 *C 78.660 10.245 +*N mux_tree_tapbuf_size8_6_sram[2]:16 *C 78.705 10.200 +*N mux_tree_tapbuf_size8_6_sram[2]:17 *C 79.657 10.200 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_14\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_6_sram[2]:4 0.000370287 +5 mux_tree_tapbuf_size8_6_sram[2]:5 0.0003994378 +6 mux_tree_tapbuf_size8_6_sram[2]:6 6.334591e-05 +7 mux_tree_tapbuf_size8_6_sram[2]:7 0.000437182 +8 mux_tree_tapbuf_size8_6_sram[2]:8 5.695241e-05 +9 mux_tree_tapbuf_size8_6_sram[2]:9 5.695241e-05 +10 mux_tree_tapbuf_size8_6_sram[2]:10 0.0007238848 +11 mux_tree_tapbuf_size8_6_sram[2]:11 5.113962e-05 +12 mux_tree_tapbuf_size8_6_sram[2]:12 5.113962e-05 +13 mux_tree_tapbuf_size8_6_sram[2]:13 0.0002872715 +14 mux_tree_tapbuf_size8_6_sram[2]:14 0.0005353216 +15 mux_tree_tapbuf_size8_6_sram[2]:15 0.0005002993 +16 mux_tree_tapbuf_size8_6_sram[2]:16 8.593957e-05 +17 mux_tree_tapbuf_size8_6_sram[2]:17 8.593957e-05 +18 mux_tree_tapbuf_size8_6_sram[2]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.847177e-05 +19 mux_tree_tapbuf_size8_6_sram[2]:13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.610432e-06 +20 mux_tree_tapbuf_size8_6_sram[2]:10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.847177e-05 +21 mux_tree_tapbuf_size8_6_sram[2]:10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.610432e-06 +22 mux_tree_tapbuf_size8_6_sram[2]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.752345e-05 +23 mux_tree_tapbuf_size8_6_sram[2]:13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.938963e-05 +24 mux_tree_tapbuf_size8_6_sram[2]:10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.752345e-05 +25 mux_tree_tapbuf_size8_6_sram[2]:10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.938963e-05 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_6_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_6_sram[2]:17 mux_tree_tapbuf_size8_6_sram[2]:16 0.0008504465 +2 mux_tree_tapbuf_size8_6_sram[2]:16 mux_tree_tapbuf_size8_6_sram[2]:15 0.0045 +3 mux_tree_tapbuf_size8_6_sram[2]:15 mux_tree_tapbuf_size8_6_sram[2]:14 0.007245536 +4 mux_tree_tapbuf_size8_6_sram[2]:4 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +5 mux_tree_tapbuf_size8_6_sram[2]:6 mux_tree_tapbuf_size8_6_sram[2]:5 0.0003035715 +6 mux_tree_tapbuf_size8_6_sram[2]:7 mux_tree_tapbuf_size8_6_sram[2]:6 0.0045 +7 mux_tree_tapbuf_size8_6_sram[2]:12 mux_tree_tapbuf_size8_6_sram[2]:11 0.0001752718 +8 mux_tree_tapbuf_size8_6_sram[2]:13 mux_tree_tapbuf_size8_6_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size8_6_sram[2]:13 mux_tree_tapbuf_size8_6_sram[2]:10 0.004857143 +10 mux_tree_tapbuf_size8_6_sram[2]:11 mux_bottom_ipin_14\/mux_l3_in_1_:S 0.152 +11 mux_tree_tapbuf_size8_6_sram[2]:8 mux_bottom_ipin_14\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size8_6_sram[2]:9 mux_tree_tapbuf_size8_6_sram[2]:8 0.0001752718 +13 mux_tree_tapbuf_size8_6_sram[2]:10 mux_tree_tapbuf_size8_6_sram[2]:9 0.0045 +14 mux_tree_tapbuf_size8_6_sram[2]:10 mux_tree_tapbuf_size8_6_sram[2]:7 0.008459822 +15 mux_tree_tapbuf_size8_6_sram[2]:5 mux_tree_tapbuf_size8_6_sram[2]:4 0.005154018 +16 mux_tree_tapbuf_size8_6_sram[2]:14 mux_tree_tapbuf_size8_6_sram[2]:13 0.0004107143 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001281475 //LENGTH 9.100 LUMPCC 0.0003069485 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_0_:X O *L 0 *C 89.415 28.560 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 92.000 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 92.000 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 92.000 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 91.540 34.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 91.540 28.605 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 91.495 28.560 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 89.453 28.560 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.504699e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.877697e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003445806 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003093613 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001073805 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001073805 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[0]:23 2.579938e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[0]:24 6.226274e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[0]:24 2.579938e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[0]:25 6.226274e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.541215e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.541215e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005120536 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001823661 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004107143 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001391102 //LENGTH 11.445 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_1_:X O *L 0 *C 67.335 53.380 +*I mux_bottom_ipin_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.230 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 64.267 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 67.575 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 67.620 60.475 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 67.620 53.425 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 67.620 53.380 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 67.335 53.380 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002283145 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002283145 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004086321 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004086321 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.84953e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.67132e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002953125 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006294644 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004249131 //LENGTH 2.935 LUMPCC 0.0001057135 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_1_:X O *L 0 *C 66.415 21.080 +*I mux_bottom_ipin_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.770 21.080 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 63.808 21.080 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.377 21.080 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001585998 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001585998 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[2]:41 1.005503e-06 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[2]:43 2.058152e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[2]:45 3.126972e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[2]:40 1.005503e-06 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[2]:42 2.058152e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[2]:44 3.126972e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002294643 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.000853217 //LENGTH 6.165 LUMPCC 0.000193286 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_2_:X O *L 0 *C 60.435 48.280 +*I mux_bottom_ipin_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 57.405 50.660 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 57.405 50.660 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 57.500 50.320 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 60.215 50.320 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 60.260 50.275 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 60.260 48.325 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 60.260 48.280 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 60.435 48.280 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.356789e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001270846 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001039641 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001282486 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001282486 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.068721e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.612997e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[9]:18 3.298484e-05 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[9]:20 1.35286e-05 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[9]:19 1.35286e-05 +12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[9]:20 3.298484e-05 +13 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:6 3.570058e-07 +14 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:14 3.995722e-06 +15 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:15 8.446076e-07 +16 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:26 3.660369e-05 +17 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:27 2.286949e-06 +18 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_3_sram[1]:12 3.547723e-07 +19 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_3_sram[1]:28 5.686789e-06 +20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_3_sram[1]:11 3.547723e-07 +21 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_3_sram[1]:29 5.686789e-06 +22 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:13 3.995722e-06 +23 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:14 1.201613e-06 +24 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:15 3.660369e-05 +25 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:26 2.286949e-06 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_2_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002424107 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001741072 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.510871e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001115494 //LENGTH 8.305 LUMPCC 0.0003339733 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_1_:X O *L 0 *C 17.195 53.380 +*I mux_bottom_ipin_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 19.130 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 19.093 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 18.445 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 18.400 58.775 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 18.400 53.425 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 18.355 53.380 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 17.233 53.380 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.178986e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.178986e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002982359 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002982359 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.973477e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.973477e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[3]:62 5.533821e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[3]:61 5.533821e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[19]:35 5.533821e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[19]:34 5.533821e-05 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.631023e-05 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.631023e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001002232 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000578125 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001230829 //LENGTH 9.060 LUMPCC 0.0001733885 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_1_:X O *L 0 *C 57.675 23.460 +*I mux_bottom_ipin_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.135 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.135 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 57.960 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 57.960 31.575 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 57.960 23.505 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 57.960 23.460 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 57.675 23.460 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.198495e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.766191e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004090104 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004090104 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.521167e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.256159e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[6]:26 8.669424e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[6]:23 8.669424e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.007205358 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006702833 //LENGTH 5.420 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_0_:X O *L 0 *C 76.075 59.160 +*I mux_bottom_ipin_13\/mux_l3_in_0_:A1 I *L 0.00198 *C 73.965 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 74.002 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 75.395 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 75.440 61.495 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 75.440 59.205 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 75.485 59.160 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 76.038 59.160 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001245442 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001245442 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000148331 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000148331 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.126639e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.126639e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001243304 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009190874 //LENGTH 6.770 LUMPCC 0.000279099 DR + +*CONN +*I mux_top_ipin_0\/mux_l2_in_3_:X O *L 0 *C 83.895 20.060 +*I mux_top_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 85.275 15.300 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 85.237 15.300 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 84.225 15.300 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 84.180 15.345 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 84.180 20.015 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 84.180 20.060 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 83.895 20.060 + +*CAP +0 mux_top_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_top_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.132175e-05 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.132175e-05 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002050849 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002050849 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.183052e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.334441e-05 +8 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[16]:7 8.68792e-05 +9 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[16]:21 8.68792e-05 +10 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_8_sram[2]:10 5.267033e-05 +11 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_8_sram[2]:9 5.267033e-05 + +*RES +0 mux_top_ipin_0\/mux_l2_in_3_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0009040179 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004169643 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003046233 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_3_:X O *L 0 *C 40.765 44.200 +*I mux_bottom_ipin_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 42.955 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 42.918 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 40.803 44.200 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001513116 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001513116 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_3_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007466571 //LENGTH 5.605 LUMPCC 0.0001124099 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_3_:X O *L 0 *C 42.495 18.360 +*I mux_bottom_ipin_6\/mux_l3_in_1_:A0 I *L 0.001631 *C 44.450 21.080 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 44.413 21.080 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 43.285 21.080 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 43.240 21.035 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 43.240 18.405 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 43.195 18.360 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 42.532 18.360 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.790554e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.790554e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001736935 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001736935 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.452463e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.452463e-05 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[2]:45 5.620495e-05 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[2]:46 5.620495e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_3_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006696 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005915178 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001079892 //LENGTH 8.970 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l1_in_0_:X O *L 0 *C 20.065 30.600 +*I mux_bottom_ipin_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.860 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.860 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 18.860 23.505 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 18.860 30.555 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 18.905 30.600 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 20.027 30.600 + +*CAP +0 mux_bottom_ipin_10\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.06195e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004150088 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004150088 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001086276 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001086276 + +*RES +0 mux_bottom_ipin_10\/mux_l1_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001002232 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006294644 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_10\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0003761205 //LENGTH 2.210 LUMPCC 0.0002320126 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l3_in_0_:X O *L 0 *C 26.505 47.260 +*I mux_bottom_ipin_11\/mux_l4_in_0_:A1 I *L 0.00198 *C 28.425 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 28.388 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 26.543 47.260 + +*CAP +0 mux_bottom_ipin_11\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.105393e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.105393e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_5_sram[2]:6 7.881477e-05 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_5_sram[2]:5 7.881477e-05 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_5_sram[3]:4 3.719154e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_5_sram[3]:3 3.719154e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l3_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_11\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001647322 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001679168 //LENGTH 12.475 LUMPCC 0.000462173 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_2_:X O *L 0 *C 88.955 53.040 +*I mux_bottom_ipin_15\/mux_l3_in_1_:A1 I *L 0.00198 *C 92.000 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 91.963 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 91.585 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 91.540 61.495 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 91.540 53.085 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 91.495 53.040 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 88.993 53.040 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.059614e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.059614e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004346089 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004346089 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001122924 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001122924 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[1]:20 0.0001056293 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[1]:19 0.0001056293 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[1]:18 1.073029e-06 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_left_in[1]:17 1.073029e-06 +12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001234126 +13 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.715574e-07 +14 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001234126 +15 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.715574e-07 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_2_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002234375 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.007508929 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003370536 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET ropt_net_143 0.0005536586 //LENGTH 4.965 LUMPCC 0 DR + +*CONN +*I FTB_14__13:X O *L 0 *C 98.900 46.920 +*I ropt_mt_inst_743:A I *L 0.001766 *C 97.825 44.880 +*N ropt_net_143:2 *C 97.863 44.880 +*N ropt_net_143:3 *C 99.315 44.880 +*N ropt_net_143:4 *C 99.360 44.925 +*N ropt_net_143:5 *C 99.360 46.875 +*N ropt_net_143:6 *C 99.315 46.920 +*N ropt_net_143:7 *C 98.938 46.920 + +*CAP +0 FTB_14__13:X 1e-06 +1 ropt_mt_inst_743:A 1e-06 +2 ropt_net_143:2 0.0001033293 +3 ropt_net_143:3 0.0001033293 +4 ropt_net_143:4 0.0001260684 +5 ropt_net_143:5 0.0001260684 +6 ropt_net_143:6 4.643166e-05 +7 ropt_net_143:7 4.643166e-05 + +*RES +0 FTB_14__13:X ropt_net_143:7 0.152 +1 ropt_net_143:2 ropt_mt_inst_743:A 0.152 +2 ropt_net_143:3 ropt_net_143:2 0.001296875 +3 ropt_net_143:4 ropt_net_143:3 0.0045 +4 ropt_net_143:6 ropt_net_143:5 0.0045 +5 ropt_net_143:5 ropt_net_143:4 0.001741072 +6 ropt_net_143:7 ropt_net_143:6 0.0003370536 + +*END + +*D_NET ropt_net_156 0.001661215 //LENGTH 11.225 LUMPCC 0.0008880751 DR + +*CONN +*I ropt_mt_inst_718:X O *L 0 *C 7.095 22.780 +*I ropt_mt_inst_755:A I *L 0.001766 *C 7.820 20.400 +*N ropt_net_156:2 *C 7.820 20.400 +*N ropt_net_156:3 *C 7.820 20.740 +*N ropt_net_156:4 *C 3.725 20.740 +*N ropt_net_156:5 *C 3.680 20.740 +*N ropt_net_156:6 *C 3.680 22.735 +*N ropt_net_156:7 *C 3.725 22.780 +*N ropt_net_156:8 *C 7.058 22.780 + +*CAP +0 ropt_mt_inst_718:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_156:2 6.42856e-05 +3 ropt_net_156:3 0.0002158309 +4 ropt_net_156:4 0.0001847133 +5 ropt_net_156:5 7.680806e-05 +6 ropt_net_156:6 4.606923e-05 +7 ropt_net_156:7 9.17163e-05 +8 ropt_net_156:8 9.17163e-05 +9 ropt_net_156:8 chanx_right_in[14]:6 2.938468e-05 +10 ropt_net_156:7 chanx_right_in[14]:5 2.938468e-05 +11 ropt_net_156:6 chanx_right_in[14]:7 6.937195e-05 +12 ropt_net_156:5 chanx_right_in[14]:8 6.937195e-05 +13 ropt_net_156:8 ropt_net_130:2 3.587876e-05 +14 ropt_net_156:7 ropt_net_130:3 3.587876e-05 +15 ropt_net_156:4 ropt_net_130:6 1.445285e-05 +16 ropt_net_156:3 ropt_net_130:7 1.445285e-05 +17 ropt_net_156:6 ropt_net_136:7 5.019076e-05 +18 ropt_net_156:4 ropt_net_136:9 9.685788e-05 +19 ropt_net_156:5 ropt_net_136:8 5.019076e-05 +20 ropt_net_156:3 ropt_net_136:10 9.685788e-05 +21 ropt_net_156:8 chanx_left_out[12]:7 0.0001393172 +22 ropt_net_156:7 chanx_left_out[12]:6 0.0001393172 +23 ropt_net_156:6 chanx_left_out[12]:5 8.583427e-06 +24 ropt_net_156:5 chanx_left_out[12]:4 8.583427e-06 + +*RES +0 ropt_mt_inst_718:X ropt_net_156:8 0.152 +1 ropt_net_156:8 ropt_net_156:7 0.002975446 +2 ropt_net_156:7 ropt_net_156:6 0.0045 +3 ropt_net_156:6 ropt_net_156:5 0.00178125 +4 ropt_net_156:4 ropt_net_156:3 0.00365625 +5 ropt_net_156:5 ropt_net_156:4 0.0045 +6 ropt_net_156:2 ropt_mt_inst_755:A 0.152 +7 ropt_net_156:3 ropt_net_156:2 0.0003035715 + +*END + +*D_NET chanx_left_out[18] 0.0007907575 //LENGTH 5.765 LUMPCC 0 DR + +*CONN +*I BUFT_RR_70:X O *L 0 *C 4.140 52.360 +*P chanx_left_out[18] O *L 0.7423 *C 1.230 50.320 +*N chanx_left_out[18]:2 *C 3.213 50.320 +*N chanx_left_out[18]:3 *C 3.220 50.378 +*N chanx_left_out[18]:4 *C 3.220 52.315 +*N chanx_left_out[18]:5 *C 3.265 52.360 +*N chanx_left_out[18]:6 *C 4.103 52.360 + +*CAP +0 BUFT_RR_70:X 1e-06 +1 chanx_left_out[18] 0.0001696452 +2 chanx_left_out[18]:2 0.0001696452 +3 chanx_left_out[18]:3 0.0001468208 +4 chanx_left_out[18]:4 0.0001468208 +5 chanx_left_out[18]:5 7.841268e-05 +6 chanx_left_out[18]:6 7.841268e-05 + +*RES +0 BUFT_RR_70:X chanx_left_out[18]:6 0.152 +1 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0007477679 +2 chanx_left_out[18]:5 chanx_left_out[18]:4 0.0045 +3 chanx_left_out[18]:4 chanx_left_out[18]:3 0.001729911 +4 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +5 chanx_left_out[18]:2 chanx_left_out[18] 0.0003105917 + +*END + +*D_NET ropt_net_166 0.0008205965 //LENGTH 6.945 LUMPCC 0.0002144624 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 11.695 11.900 +*I ropt_mt_inst_772:A I *L 0.001767 *C 12.420 14.960 +*N ropt_net_166:2 *C 12.383 14.960 +*N ropt_net_166:3 *C 10.625 14.960 +*N ropt_net_166:4 *C 10.580 14.915 +*N ropt_net_166:5 *C 10.580 11.945 +*N ropt_net_166:6 *C 10.625 11.900 +*N ropt_net_166:7 *C 11.658 11.900 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_166:2 0.0001021722 +3 ropt_net_166:3 0.0001021722 +4 ropt_net_166:4 0.0001212852 +5 ropt_net_166:5 0.0001212852 +6 ropt_net_166:6 7.860965e-05 +7 ropt_net_166:7 7.860965e-05 +8 ropt_net_166:5 chanx_left_out[2]:3 7.142451e-05 +9 ropt_net_166:3 chanx_left_out[2]:5 3.58067e-05 +10 ropt_net_166:4 chanx_left_out[2]:4 7.142451e-05 +11 ropt_net_166:2 chanx_left_out[2]:6 3.58067e-05 + +*RES +0 ropt_mt_inst_731:X ropt_net_166:7 0.152 +1 ropt_net_166:7 ropt_net_166:6 0.0009218751 +2 ropt_net_166:6 ropt_net_166:5 0.0045 +3 ropt_net_166:5 ropt_net_166:4 0.002651786 +4 ropt_net_166:3 ropt_net_166:2 0.001569197 +5 ropt_net_166:4 ropt_net_166:3 0.0045 +6 ropt_net_166:2 ropt_mt_inst_772:A 0.152 + +*END + +*D_NET ropt_net_131 0.001190235 //LENGTH 10.215 LUMPCC 0 DR + +*CONN +*I BUFT_P_96:X O *L 0 *C 101.660 59.160 +*I ropt_mt_inst_730:A I *L 0.001766 *C 97.825 63.920 +*N ropt_net_131:2 *C 97.797 63.898 +*N ropt_net_131:3 *C 97.520 63.885 +*N ropt_net_131:4 *C 97.520 63.580 +*N ropt_net_131:5 *C 101.660 63.580 +*N ropt_net_131:6 *C 101.660 63.535 +*N ropt_net_131:7 *C 101.660 59.205 +*N ropt_net_131:8 *C 101.660 59.160 + +*CAP +0 BUFT_P_96:X 1e-06 +1 ropt_mt_inst_730:A 1e-06 +2 ropt_net_131:2 3.69329e-05 +3 ropt_net_131:3 6.074284e-05 +4 ropt_net_131:4 0.0002638736 +5 ropt_net_131:5 0.0002788691 +6 ropt_net_131:6 0.0002551667 +7 ropt_net_131:7 0.0002551667 +8 ropt_net_131:8 3.748356e-05 + +*RES +0 BUFT_P_96:X ropt_net_131:8 0.152 +1 ropt_net_131:2 ropt_mt_inst_730:A 0.152 +2 ropt_net_131:5 ropt_net_131:4 0.003696429 +3 ropt_net_131:6 ropt_net_131:5 0.0045 +4 ropt_net_131:8 ropt_net_131:7 0.0045 +5 ropt_net_131:7 ropt_net_131:6 0.003866072 +6 ropt_net_131:4 ropt_net_131:3 0.0002723215 +7 ropt_net_131:3 ropt_net_131:2 0.0001875 + +*END + +*D_NET chanx_left_out[12] 0.002212526 //LENGTH 16.405 LUMPCC 0.0002958013 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 13.340 22.440 +*P chanx_left_out[12] O *L 0.7423 *C 1.298 19.040 +*N chanx_left_out[12]:2 *C 1.380 19.040 +*N chanx_left_out[12]:3 *C 1.380 19.040 +*N chanx_left_out[12]:4 *C 2.300 19.040 +*N chanx_left_out[12]:5 *C 2.300 22.395 +*N chanx_left_out[12]:6 *C 2.345 22.440 +*N chanx_left_out[12]:7 *C 13.340 22.440 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 chanx_left_out[12] 3.926725e-05 +2 chanx_left_out[12]:2 3.926725e-05 +3 chanx_left_out[12]:3 9.002788e-05 +4 chanx_left_out[12]:4 0.0002331958 +5 chanx_left_out[12]:5 0.0001775373 +6 chanx_left_out[12]:6 0.0006496534 +7 chanx_left_out[12]:7 0.0006867755 +8 chanx_left_out[12]:6 ropt_net_156:7 0.0001393172 +9 chanx_left_out[12]:5 ropt_net_156:6 8.583427e-06 +10 chanx_left_out[12]:7 ropt_net_156:8 0.0001393172 +11 chanx_left_out[12]:4 ropt_net_156:5 8.583427e-06 + +*RES +0 ropt_mt_inst_771:X chanx_left_out[12]:7 0.152 +1 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +2 chanx_left_out[12]:2 chanx_left_out[12] 2.35e-05 +3 chanx_left_out[12]:6 chanx_left_out[12]:5 0.0045 +4 chanx_left_out[12]:5 chanx_left_out[12]:4 0.002995536 +5 chanx_left_out[12]:7 chanx_left_out[12]:6 0.009816965 +6 chanx_left_out[12]:4 chanx_left_out[12]:3 0.0008214285 + +*END + +*D_NET chanx_left_in[14] 0.015832 //LENGTH 110.565 LUMPCC 0.005889098 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 23.120 +*I mux_bottom_ipin_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 27.315 20.740 +*I mux_bottom_ipin_10\/mux_l2_in_2_:A0 I *L 0.001631 *C 28.810 15.300 +*I BUFT_P_100:A I *L 0.001776 *C 87.400 6.800 +*I mux_bottom_ipin_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 64.690 11.560 +*N chanx_left_in[14]:5 *C 64.653 11.560 +*N chanx_left_in[14]:6 *C 63.525 11.560 +*N chanx_left_in[14]:7 *C 63.480 11.515 +*N chanx_left_in[14]:8 *C 87.362 6.800 +*N chanx_left_in[14]:9 *C 83.765 6.800 +*N chanx_left_in[14]:10 *C 83.720 6.800 +*N chanx_left_in[14]:11 *C 83.713 6.800 +*N chanx_left_in[14]:12 *C 63.488 6.800 +*N chanx_left_in[14]:13 *C 63.480 6.857 +*N chanx_left_in[14]:14 *C 63.480 10.200 +*N chanx_left_in[14]:15 *C 63.473 10.200 +*N chanx_left_in[14]:16 *C 29.448 10.200 +*N chanx_left_in[14]:17 *C 29.440 10.258 +*N chanx_left_in[14]:18 *C 28.848 15.300 +*N chanx_left_in[14]:19 *C 29.395 15.300 +*N chanx_left_in[14]:20 *C 29.440 15.300 +*N chanx_left_in[14]:21 *C 29.440 20.695 +*N chanx_left_in[14]:22 *C 29.395 20.740 +*N chanx_left_in[14]:23 *C 27.353 20.740 +*N chanx_left_in[14]:24 *C 28.060 20.740 +*N chanx_left_in[14]:25 *C 28.060 20.400 +*N chanx_left_in[14]:26 *C 25.805 20.400 +*N chanx_left_in[14]:27 *C 25.760 20.445 +*N chanx_left_in[14]:28 *C 25.760 23.062 +*N chanx_left_in[14]:29 *C 25.753 23.120 + +*CAP +0 chanx_left_in[14] 0.0009515998 +1 mux_bottom_ipin_2\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_2_:A0 1e-06 +3 BUFT_P_100:A 1e-06 +4 mux_bottom_ipin_4\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[14]:5 9.791098e-05 +6 chanx_left_in[14]:6 9.791098e-05 +7 chanx_left_in[14]:7 6.918242e-05 +8 chanx_left_in[14]:8 0.0002219671 +9 chanx_left_in[14]:9 0.0002219671 +10 chanx_left_in[14]:10 3.474602e-05 +11 chanx_left_in[14]:11 0.001013811 +12 chanx_left_in[14]:12 0.001013811 +13 chanx_left_in[14]:13 0.0001748216 +14 chanx_left_in[14]:14 0.0002783189 +15 chanx_left_in[14]:15 0.001234089 +16 chanx_left_in[14]:16 0.001234089 +17 chanx_left_in[14]:17 0.0002809498 +18 chanx_left_in[14]:18 5.603061e-05 +19 chanx_left_in[14]:19 5.603061e-05 +20 chanx_left_in[14]:20 0.0006252766 +21 chanx_left_in[14]:21 0.0003111303 +22 chanx_left_in[14]:22 9.702215e-05 +23 chanx_left_in[14]:23 5.607124e-05 +24 chanx_left_in[14]:24 0.0001772836 +25 chanx_left_in[14]:25 0.0001850824 +26 chanx_left_in[14]:26 0.0001608922 +27 chanx_left_in[14]:27 0.0001686539 +28 chanx_left_in[14]:28 0.0001686539 +29 chanx_left_in[14]:29 0.0009515998 +30 chanx_left_in[14] chanx_right_in[4]:11 0.0008770335 +31 chanx_left_in[14]:29 chanx_right_in[4]:12 0.0008770335 +32 chanx_left_in[14]:15 chanx_right_in[5]:13 0.0006398661 +33 chanx_left_in[14]:16 chanx_right_in[5]:12 0.0006398661 +34 chanx_left_in[14]:12 chanx_right_in[8]:12 3.850518e-06 +35 chanx_left_in[14]:11 chanx_right_in[8]:13 3.850518e-06 +36 chanx_left_in[14]:15 chanx_right_in[8]:13 0.0003670035 +37 chanx_left_in[14]:16 chanx_right_in[8]:12 0.0003670035 +38 chanx_left_in[14] chanx_right_in[12]:18 8.696255e-06 +39 chanx_left_in[14] chanx_right_in[12]:21 0.0008039372 +40 chanx_left_in[14]:29 chanx_right_in[12]:17 8.696255e-06 +41 chanx_left_in[14]:29 chanx_right_in[12]:22 0.0008039372 +42 chanx_left_in[14]:13 mux_tree_tapbuf_size10_2_sram[2]:17 2.766098e-06 +43 chanx_left_in[14]:14 mux_tree_tapbuf_size10_2_sram[2]:16 3.65125e-06 +44 chanx_left_in[14]:14 mux_tree_tapbuf_size10_2_sram[2]:17 7.523787e-06 +45 chanx_left_in[14]:15 mux_tree_tapbuf_size10_2_sram[2]:15 0.0002329869 +46 chanx_left_in[14]:16 mux_tree_tapbuf_size10_2_sram[2]:14 0.0002329869 +47 chanx_left_in[14]:7 mux_tree_tapbuf_size10_2_sram[2]:9 8.851515e-07 +48 chanx_left_in[14]:7 mux_tree_tapbuf_size10_2_sram[2]:16 7.523787e-06 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:29 0.003841858 +1 chanx_left_in[14]:13 chanx_left_in[14]:12 0.00341 +2 chanx_left_in[14]:12 chanx_left_in[14]:11 0.003168583 +3 chanx_left_in[14]:10 chanx_left_in[14]:9 0.0045 +4 chanx_left_in[14]:11 chanx_left_in[14]:10 0.00341 +5 chanx_left_in[14]:9 chanx_left_in[14]:8 0.003212054 +6 chanx_left_in[14]:8 BUFT_P_100:A 0.152 +7 chanx_left_in[14]:14 chanx_left_in[14]:13 0.002984375 +8 chanx_left_in[14]:14 chanx_left_in[14]:7 0.001174107 +9 chanx_left_in[14]:15 chanx_left_in[14]:14 0.00341 +10 chanx_left_in[14]:17 chanx_left_in[14]:16 0.00341 +11 chanx_left_in[14]:16 chanx_left_in[14]:15 0.005330583 +12 chanx_left_in[14]:22 chanx_left_in[14]:21 0.0045 +13 chanx_left_in[14]:21 chanx_left_in[14]:20 0.004816964 +14 chanx_left_in[14]:19 chanx_left_in[14]:18 0.0004888393 +15 chanx_left_in[14]:20 chanx_left_in[14]:19 0.0045 +16 chanx_left_in[14]:20 chanx_left_in[14]:17 0.004502232 +17 chanx_left_in[14]:18 mux_bottom_ipin_10\/mux_l2_in_2_:A0 0.152 +18 chanx_left_in[14]:6 chanx_left_in[14]:5 0.001006696 +19 chanx_left_in[14]:7 chanx_left_in[14]:6 0.0045 +20 chanx_left_in[14]:5 mux_bottom_ipin_4\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[14]:23 mux_bottom_ipin_2\/mux_l2_in_2_:A0 0.152 +22 chanx_left_in[14]:26 chanx_left_in[14]:25 0.002013393 +23 chanx_left_in[14]:27 chanx_left_in[14]:26 0.0045 +24 chanx_left_in[14]:28 chanx_left_in[14]:27 0.002337054 +25 chanx_left_in[14]:29 chanx_left_in[14]:28 0.00341 +26 chanx_left_in[14]:25 chanx_left_in[14]:24 0.0003035715 +27 chanx_left_in[14]:24 chanx_left_in[14]:23 0.0006316964 +28 chanx_left_in[14]:24 chanx_left_in[14]:22 0.001191964 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008755039 //LENGTH 6.680 LUMPCC 0.0001093431 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l3_in_1_:X O *L 0 *C 68.365 31.620 +*I mux_bottom_ipin_12\/mux_l4_in_0_:A0 I *L 0.001631 *C 68.370 37.400 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 68.370 37.400 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 68.540 37.400 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 68.540 37.355 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 68.540 31.665 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 68.540 31.620 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 68.365 31.620 + +*CAP +0 mux_bottom_ipin_12\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.618542e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.053131e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002704009 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002704009 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.575845e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.088384e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.467157e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.467157e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l3_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_12\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.005080357 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009107161 //LENGTH 7.035 LUMPCC 0.0001346071 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_2_:X O *L 0 *C 68.715 58.480 +*I mux_bottom_ipin_13\/mux_l3_in_1_:A1 I *L 0.00198 *C 69.560 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 69.523 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 68.585 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 68.540 63.535 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 68.540 58.525 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 68.540 58.480 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 68.715 58.480 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.5409e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.5409e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002334904 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002334904 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.944818e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.686198e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.353948e-06 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.353948e-06 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.194961e-05 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.194961e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_2_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008370536 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004473215 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008111596 //LENGTH 6.205 LUMPCC 0 DR + +*CONN +*I mux_top_ipin_0\/mux_l2_in_1_:X O *L 0 *C 88.035 19.720 +*I mux_top_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 89.530 15.640 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 89.493 15.640 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 88.365 15.640 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 88.320 15.685 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 88.320 19.675 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 88.320 19.720 +*N mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 88.035 19.720 + +*CAP +0 mux_top_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001011172 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001011172 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00024711 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00024711 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.717897e-05 +7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.552641e-05 + +*RES +0 mux_top_ipin_0\/mux_l2_in_1_:X mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006696 +3 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004348073 //LENGTH 2.860 LUMPCC 0.0002091339 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_0_:X O *L 0 *C 38.355 20.060 +*I mux_bottom_ipin_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 35.785 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 35.823 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 38.318 20.060 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001118367 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001118367 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_0_sram[1]:18 0.000104567 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_0_sram[1]:19 0.000104567 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002227678 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001092588 //LENGTH 7.345 LUMPCC 0.000576197 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l1_in_0_:X O *L 0 *C 39.845 53.380 +*I mux_bottom_ipin_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.500 58.140 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.462 58.140 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 40.525 58.140 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 40.480 58.095 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 40.480 53.425 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 40.435 53.380 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 39.883 53.380 + +*CAP +0 mux_bottom_ipin_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.089512e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.089512e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001761197 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001761197 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.018053e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.018053e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[1]:39 5.024514e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[1]:41 1.320353e-05 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[1]:40 5.024514e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[1]:42 1.320353e-05 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[3]:38 4.775346e-05 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[3]:37 4.775346e-05 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size8_1_sram[1]:15 4.775346e-05 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size8_1_sram[1]:16 4.775346e-05 +16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:17 0.0001291429 +17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:19 0.0001291429 + +*RES +0 mux_bottom_ipin_3\/mux_l1_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003167015 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_1_:X O *L 0 *C 48.475 22.780 +*I mux_bottom_ipin_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 46.290 22.780 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 46.328 22.780 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 48.438 22.780 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001573508 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001573508 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_1_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009700144 //LENGTH 6.695 LUMPCC 0.000100561 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l1_in_0_:X O *L 0 *C 31.915 53.380 +*I mux_bottom_ipin_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.040 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.078 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.455 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 34.500 56.055 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 34.500 53.425 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 34.455 53.380 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 31.953 53.380 + +*CAP +0 mux_bottom_ipin_7\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.751526e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.751526e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001361779 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001361779 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002400335 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002400335 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[3]:55 4.911822e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[3]:51 9.409175e-07 +10 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[3]:53 2.213645e-07 +11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[3]:54 4.911822e-05 +12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[3]:52 2.213645e-07 +13 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[3]:53 9.409175e-07 + +*RES +0 mux_bottom_ipin_7\/mux_l1_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002234375 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370536 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_7\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008549275 //LENGTH 6.680 LUMPCC 0.0002360153 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l3_in_0_:X O *L 0 *C 27.775 60.860 +*I mux_bottom_ipin_7\/mux_l4_in_0_:A1 I *L 0.00198 *C 24.745 63.580 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 24.783 63.580 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 25.255 63.580 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 25.300 63.535 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 25.300 60.905 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 25.345 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 27.738 60.860 + +*CAP +0 mux_bottom_ipin_7\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.098874e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.098874e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001629496 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001629496 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.451779e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.451779e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_3_sram[2]:12 1.470008e-05 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_3_sram[2]:9 2.315312e-05 +10 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_3_sram[2]:13 8.015444e-05 +11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_3_sram[2]:11 1.470008e-05 +12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size8_3_sram[2]:13 2.315312e-05 +13 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size8_3_sram[2]:14 8.015444e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l3_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_7\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.002136161 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009901003 //LENGTH 7.825 LUMPCC 0.0002240804 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l1_in_0_:X O *L 0 *C 22.365 48.280 +*I mux_bottom_ipin_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 24.840 52.700 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 24.803 52.700 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 23.505 52.700 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 23.460 52.655 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 23.460 48.325 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 23.415 48.280 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 22.402 48.280 + +*CAP +0 mux_bottom_ipin_11\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.340157e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.340157e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002136919 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002136919 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001049165 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001049165 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[3]:61 6.135031e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[3]:60 6.135031e-05 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[19]:32 4.744654e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[19]:35 3.243343e-06 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[19]:33 4.744654e-05 +13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[19]:34 3.243343e-06 + +*RES +0 mux_bottom_ipin_11\/mux_l1_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003866072 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001158482 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_11\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000565529 //LENGTH 3.925 LUMPCC 8.432909e-05 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_3_:X O *L 0 *C 33.405 45.560 +*I mux_bottom_ipin_11\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.950 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 32.988 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 33.535 47.940 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 33.580 47.895 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 33.580 45.605 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 33.580 45.560 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 33.405 45.560 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.02265e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.02265e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001236302 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001236302 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.703075e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.445575e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_5_sram[2]:8 5.389996e-07 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_5_sram[2]:9 5.389996e-07 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_5_sram[2]:10 4.162555e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_5_sram[2]:11 4.162555e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_3_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001092786 //LENGTH 8.515 LUMPCC 0.0002519166 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l3_in_0_:X O *L 0 *C 79.350 23.800 +*I mux_bottom_ipin_14\/mux_l4_in_0_:A1 I *L 0.00198 *C 78.660 30.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 78.698 30.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 79.075 30.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 79.120 30.895 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 79.120 23.845 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 79.120 23.800 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 79.350 23.800 + +*CAP +0 mux_bottom_ipin_14\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.963322e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.963322e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003114008 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003114008 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.986192e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.693906e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[16]:22 5.498727e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[16]:26 8.888104e-07 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[16]:23 5.498727e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[16]:27 8.888104e-07 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_6_sram[2]:10 6.847177e-05 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_6_sram[2]:13 1.610432e-06 +14 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_6_sram[2]:7 6.847177e-05 +15 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_6_sram[2]:10 1.610432e-06 + +*RES +0 mux_bottom_ipin_14\/mux_l3_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000125 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006294644 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003370536 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_14\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001215207 //LENGTH 7.655 LUMPCC 0.0007335194 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l3_in_0_:X O *L 0 *C 88.070 58.140 +*I mux_bottom_ipin_15\/mux_l4_in_0_:A1 I *L 0.00198 *C 86.480 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 86.480 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 86.480 63.535 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 86.480 58.185 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 86.525 58.140 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 88.032 58.140 + +*CAP +0 mux_bottom_ipin_15\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.586522e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001705117 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001705117 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.139947e-05 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.139947e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[3]:64 6.872239e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[3]:63 6.872239e-05 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_7_sram[1]:12 1.319903e-05 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_7_sram[1]:11 1.319903e-05 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_7_sram[1]:9 0.0001226366 +12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_7_sram[1]:8 0.0001226366 +13 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_7_sram[2]:9 2.902257e-05 +14 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_7_sram[2]:10 2.902257e-05 +15 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_7_sram[2]:11 0.0001331791 +16 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_7_sram[2]:12 0.0001331791 + +*RES +0 mux_bottom_ipin_15\/mux_l3_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001345982 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.004776786 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_15\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_123 0.002749688 //LENGTH 22.365 LUMPCC 0.0001285841 DR + +*CONN +*I FTB_5__4:X O *L 0 *C 98.440 59.160 +*I ropt_mt_inst_722:A I *L 0.001766 *C 93.380 66.640 +*N ropt_net_123:2 *C 93.418 66.640 +*N ropt_net_123:3 *C 95.680 66.640 +*N ropt_net_123:4 *C 95.680 66.300 +*N ropt_net_123:5 *C 102.535 66.300 +*N ropt_net_123:6 *C 102.580 66.255 +*N ropt_net_123:7 *C 102.580 61.585 +*N ropt_net_123:8 *C 102.535 61.540 +*N ropt_net_123:9 *C 98.485 61.540 +*N ropt_net_123:10 *C 98.440 61.495 +*N ropt_net_123:11 *C 98.440 59.205 +*N ropt_net_123:12 *C 98.440 59.160 + +*CAP +0 FTB_5__4:X 1e-06 +1 ropt_mt_inst_722:A 1e-06 +2 ropt_net_123:2 0.0001637894 +3 ropt_net_123:3 0.0001877792 +4 ropt_net_123:4 0.0004100213 +5 ropt_net_123:5 0.0003860316 +6 ropt_net_123:6 0.0002686613 +7 ropt_net_123:7 0.0002686613 +8 ropt_net_123:8 0.0002972864 +9 ropt_net_123:9 0.0002972864 +10 ropt_net_123:10 0.0001534881 +11 ropt_net_123:11 0.0001534881 +12 ropt_net_123:12 3.261074e-05 +13 ropt_net_123:5 ropt_net_118:2 6.429203e-05 +14 ropt_net_123:4 ropt_net_118:3 6.429203e-05 + +*RES +0 FTB_5__4:X ropt_net_123:12 0.152 +1 ropt_net_123:12 ropt_net_123:11 0.0045 +2 ropt_net_123:11 ropt_net_123:10 0.002044643 +3 ropt_net_123:9 ropt_net_123:8 0.003616072 +4 ropt_net_123:10 ropt_net_123:9 0.0045 +5 ropt_net_123:8 ropt_net_123:7 0.0045 +6 ropt_net_123:7 ropt_net_123:6 0.004169643 +7 ropt_net_123:5 ropt_net_123:4 0.006120536 +8 ropt_net_123:6 ropt_net_123:5 0.0045 +9 ropt_net_123:2 ropt_mt_inst_722:A 0.152 +10 ropt_net_123:3 ropt_net_123:2 0.002020089 +11 ropt_net_123:4 ropt_net_123:3 0.0003035715 + +*END + +*D_NET ropt_net_154 0.000872063 //LENGTH 6.385 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_715:X O *L 0 *C 92.675 68.680 +*I ropt_mt_inst_753:A I *L 0.001767 *C 97.980 69.360 +*N ropt_net_154:2 *C 97.980 69.360 +*N ropt_net_154:3 *C 97.980 68.680 +*N ropt_net_154:4 *C 92.713 68.680 + +*CAP +0 ropt_mt_inst_715:X 1e-06 +1 ropt_mt_inst_753:A 1e-06 +2 ropt_net_154:2 8.525446e-05 +3 ropt_net_154:3 0.0004182669 +4 ropt_net_154:4 0.0003665417 + +*RES +0 ropt_mt_inst_715:X ropt_net_154:4 0.152 +1 ropt_net_154:4 ropt_net_154:3 0.004703125 +2 ropt_net_154:2 ropt_mt_inst_753:A 0.152 +3 ropt_net_154:3 ropt_net_154:2 0.0006071429 + +*END + +*D_NET ropt_net_148 0.0003948189 //LENGTH 2.750 LUMPCC 0.0002103038 DR + +*CONN +*I FTB_23__22:X O *L 0 *C 5.980 14.620 +*I ropt_mt_inst_748:A I *L 0.001766 *C 7.820 14.960 +*N ropt_net_148:2 *C 7.783 14.960 +*N ropt_net_148:3 *C 7.360 14.960 +*N ropt_net_148:4 *C 7.360 14.620 +*N ropt_net_148:5 *C 6.018 14.620 + +*CAP +0 FTB_23__22:X 1e-06 +1 ropt_mt_inst_748:A 1e-06 +2 ropt_net_148:2 1.73176e-05 +3 ropt_net_148:3 3.767213e-05 +4 ropt_net_148:4 7.393995e-05 +5 ropt_net_148:5 5.358542e-05 +6 ropt_net_148:5 chanx_right_in[2]:20 7.879295e-06 +7 ropt_net_148:2 chanx_right_in[2]:21 2.525892e-05 +8 ropt_net_148:4 chanx_right_in[2]:19 5.075263e-06 +9 ropt_net_148:4 chanx_right_in[2]:21 7.879295e-06 +10 ropt_net_148:3 chanx_right_in[2]:20 3.033419e-05 +11 ropt_net_148:5 chanx_right_in[14]:9 5.96859e-05 +12 ropt_net_148:2 chanx_right_in[14]:10 7.252533e-06 +13 ropt_net_148:4 chanx_right_in[14]:10 5.96859e-05 +14 ropt_net_148:3 chanx_right_in[14]:9 7.252533e-06 + +*RES +0 FTB_23__22:X ropt_net_148:5 0.152 +1 ropt_net_148:5 ropt_net_148:4 0.001198661 +2 ropt_net_148:2 ropt_mt_inst_748:A 0.152 +3 ropt_net_148:4 ropt_net_148:3 0.0003035715 +4 ropt_net_148:3 ropt_net_148:2 0.0003772322 + +*END + +*D_NET ropt_net_125 0.002025438 //LENGTH 15.690 LUMPCC 0.0007000832 DR + +*CONN +*I FTB_34__33:X O *L 0 *C 3.220 55.080 +*I ropt_mt_inst_724:A I *L 0.001766 *C 3.220 42.160 +*N ropt_net_125:2 *C 3.183 42.160 +*N ropt_net_125:3 *C 2.345 42.160 +*N ropt_net_125:4 *C 2.300 42.205 +*N ropt_net_125:5 *C 2.300 55.035 +*N ropt_net_125:6 *C 2.345 55.080 +*N ropt_net_125:7 *C 3.183 55.080 + +*CAP +0 FTB_34__33:X 1e-06 +1 ropt_mt_inst_724:A 1e-06 +2 ropt_net_125:2 8.479349e-05 +3 ropt_net_125:3 8.479349e-05 +4 ropt_net_125:4 0.0004988635 +5 ropt_net_125:5 0.0004988635 +6 ropt_net_125:6 7.802063e-05 +7 ropt_net_125:7 7.802063e-05 +8 ropt_net_125:4 chanx_left_in[12]:28 0.0003500416 +9 ropt_net_125:5 chanx_left_in[12]:29 0.0003500416 + +*RES +0 FTB_34__33:X ropt_net_125:7 0.152 +1 ropt_net_125:2 ropt_mt_inst_724:A 0.152 +2 ropt_net_125:3 ropt_net_125:2 0.0007477679 +3 ropt_net_125:4 ropt_net_125:3 0.0045 +4 ropt_net_125:6 ropt_net_125:5 0.0045 +5 ropt_net_125:5 ropt_net_125:4 0.01145536 +6 ropt_net_125:7 ropt_net_125:6 0.0007477678 + +*END + +*D_NET ropt_net_142 0.001107455 //LENGTH 7.410 LUMPCC 0.0006009489 DR + +*CONN +*I FTB_40__39:X O *L 0 *C 6.440 56.100 +*I ropt_mt_inst_742:A I *L 0.001766 *C 7.820 61.200 +*N ropt_net_142:2 *C 7.783 61.200 +*N ropt_net_142:3 *C 7.405 61.200 +*N ropt_net_142:4 *C 7.360 61.155 +*N ropt_net_142:5 *C 7.360 56.145 +*N ropt_net_142:6 *C 7.315 56.100 +*N ropt_net_142:7 *C 6.478 56.100 + +*CAP +0 FTB_40__39:X 1e-06 +1 ropt_mt_inst_742:A 1e-06 +2 ropt_net_142:2 5.442333e-05 +3 ropt_net_142:3 5.442333e-05 +4 ropt_net_142:4 0.0001742173 +5 ropt_net_142:5 0.0001742173 +6 ropt_net_142:6 2.361231e-05 +7 ropt_net_142:7 2.361231e-05 +8 ropt_net_142:6 chanx_left_in[1]:55 4.422165e-05 +9 ropt_net_142:7 chanx_left_in[1]:56 4.422165e-05 +10 ropt_net_142:4 chanx_right_in[9]:9 0.0001370444 +11 ropt_net_142:5 chanx_right_in[9]:10 0.0001370444 +12 ropt_net_142:6 chanx_right_in[13]:11 4.422165e-05 +13 ropt_net_142:7 chanx_right_in[13]:10 4.422165e-05 +14 ropt_net_142:4 optlc_net_107:5 7.49867e-05 +15 ropt_net_142:5 optlc_net_107:13 7.49867e-05 + +*RES +0 FTB_40__39:X ropt_net_142:7 0.152 +1 ropt_net_142:2 ropt_mt_inst_742:A 0.152 +2 ropt_net_142:3 ropt_net_142:2 0.0003370536 +3 ropt_net_142:4 ropt_net_142:3 0.0045 +4 ropt_net_142:6 ropt_net_142:5 0.0045 +5 ropt_net_142:5 ropt_net_142:4 0.004473215 +6 ropt_net_142:7 ropt_net_142:6 0.0007477679 + +*END + +*D_NET ropt_net_150 0.001943857 //LENGTH 13.660 LUMPCC 0.000574479 DR + +*CONN +*I ropt_mt_inst_726:X O *L 0 *C 14.915 17.000 +*I ropt_mt_inst_749:A I *L 0.001766 *C 3.220 17.680 +*N ropt_net_150:2 *C 3.258 17.680 +*N ropt_net_150:3 *C 5.935 17.680 +*N ropt_net_150:4 *C 5.980 17.635 +*N ropt_net_150:5 *C 5.980 17.058 +*N ropt_net_150:6 *C 5.988 17.000 +*N ropt_net_150:7 *C 9.652 17.000 +*N ropt_net_150:8 *C 9.660 17.000 +*N ropt_net_150:9 *C 9.705 17.000 +*N ropt_net_150:10 *C 14.878 17.000 + +*CAP +0 ropt_mt_inst_726:X 1e-06 +1 ropt_mt_inst_749:A 1e-06 +2 ropt_net_150:2 0.0001323262 +3 ropt_net_150:3 0.0001323262 +4 ropt_net_150:4 5.378578e-05 +5 ropt_net_150:5 5.378578e-05 +6 ropt_net_150:6 0.0001395876 +7 ropt_net_150:7 0.0001395876 +8 ropt_net_150:8 3.66635e-05 +9 ropt_net_150:9 0.0003396579 +10 ropt_net_150:10 0.0003396579 +11 ropt_net_150:6 chanx_left_out[14] 0.000223076 +12 ropt_net_150:7 chanx_left_out[14]:2 0.000223076 +13 ropt_net_150:2 ropt_net_127:4 5.396783e-05 +14 ropt_net_150:3 ropt_net_127:3 5.396783e-05 +15 ropt_net_150:4 ropt_net_127:5 4.775384e-08 +16 ropt_net_150:5 ropt_net_127:6 4.775384e-08 +17 ropt_net_150:9 ropt_net_127:4 1.014798e-05 +18 ropt_net_150:10 ropt_net_127:3 1.014798e-05 + +*RES +0 ropt_mt_inst_726:X ropt_net_150:10 0.152 +1 ropt_net_150:2 ropt_mt_inst_749:A 0.152 +2 ropt_net_150:3 ropt_net_150:2 0.002390625 +3 ropt_net_150:4 ropt_net_150:3 0.0045 +4 ropt_net_150:5 ropt_net_150:4 0.000515625 +5 ropt_net_150:6 ropt_net_150:5 0.00341 +6 ropt_net_150:8 ropt_net_150:7 0.00341 +7 ropt_net_150:7 ropt_net_150:6 0.0005741833 +8 ropt_net_150:9 ropt_net_150:8 0.0045 +9 ropt_net_150:10 ropt_net_150:9 0.004618304 + +*END + +*D_NET ropt_net_155 0.001449988 //LENGTH 10.695 LUMPCC 0.0004847661 DR + +*CONN +*I ropt_mt_inst_728:X O *L 0 *C 11.695 52.700 +*I ropt_mt_inst_754:A I *L 0.001767 *C 7.820 50.320 +*N ropt_net_155:2 *C 7.783 50.320 +*N ropt_net_155:3 *C 6.440 50.320 +*N ropt_net_155:4 *C 6.440 49.980 +*N ropt_net_155:5 *C 11.455 49.980 +*N ropt_net_155:6 *C 11.500 50.025 +*N ropt_net_155:7 *C 11.500 52.655 +*N ropt_net_155:8 *C 11.500 52.700 +*N ropt_net_155:9 *C 11.695 52.700 + +*CAP +0 ropt_mt_inst_728:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_155:2 9.530671e-05 +3 ropt_net_155:3 0.0001171427 +4 ropt_net_155:4 0.0001829919 +5 ropt_net_155:5 0.0001611559 +6 ropt_net_155:6 0.0001490331 +7 ropt_net_155:7 0.0001490331 +8 ropt_net_155:8 5.434911e-05 +9 ropt_net_155:9 5.420901e-05 +10 ropt_net_155:5 chanx_right_in[9]:12 0.0001808247 +11 ropt_net_155:2 chanx_right_in[9]:12 7.584821e-06 +12 ropt_net_155:4 chanx_right_in[9]:11 0.0001808247 +13 ropt_net_155:3 chanx_right_in[9]:11 7.584821e-06 +14 ropt_net_155:5 chanx_left_out[13]:11 8.217198e-06 +15 ropt_net_155:5 chanx_left_out[13]:15 8.080156e-06 +16 ropt_net_155:2 chanx_left_out[13]:11 1.424089e-06 +17 ropt_net_155:2 chanx_left_out[13]:15 3.108245e-05 +18 ropt_net_155:4 chanx_left_out[13]:10 8.217198e-06 +19 ropt_net_155:4 chanx_left_out[13]:12 5.169686e-06 +20 ropt_net_155:4 chanx_left_out[13]:14 8.080156e-06 +21 ropt_net_155:3 chanx_left_out[13]:10 1.424089e-06 +22 ropt_net_155:3 chanx_left_out[13]:13 5.169686e-06 +23 ropt_net_155:3 chanx_left_out[13]:14 3.108245e-05 + +*RES +0 ropt_mt_inst_728:X ropt_net_155:9 0.152 +1 ropt_net_155:9 ropt_net_155:8 0.0001059783 +2 ropt_net_155:8 ropt_net_155:7 0.0045 +3 ropt_net_155:7 ropt_net_155:6 0.002348214 +4 ropt_net_155:5 ropt_net_155:4 0.004477679 +5 ropt_net_155:6 ropt_net_155:5 0.0045 +6 ropt_net_155:2 ropt_mt_inst_754:A 0.152 +7 ropt_net_155:4 ropt_net_155:3 0.0003035715 +8 ropt_net_155:3 ropt_net_155:2 0.001198661 + +*END + +*D_NET chanx_left_out[3] 0.0006039423 //LENGTH 4.405 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 4.140 8.840 +*P chanx_left_out[3] O *L 0.7423 *C 1.230 8.160 +*N chanx_left_out[3]:2 *C 2.752 8.160 +*N chanx_left_out[3]:3 *C 2.760 8.218 +*N chanx_left_out[3]:4 *C 2.760 8.795 +*N chanx_left_out[3]:5 *C 2.805 8.840 +*N chanx_left_out[3]:6 *C 4.103 8.840 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 chanx_left_out[3] 0.0001421039 +2 chanx_left_out[3]:2 0.0001421039 +3 chanx_left_out[3]:3 5.541193e-05 +4 chanx_left_out[3]:4 5.541193e-05 +5 chanx_left_out[3]:5 0.0001039553 +6 chanx_left_out[3]:6 0.0001039553 + +*RES +0 ropt_mt_inst_762:X chanx_left_out[3]:6 0.152 +1 chanx_left_out[3]:6 chanx_left_out[3]:5 0.001158482 +2 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +3 chanx_left_out[3]:4 chanx_left_out[3]:3 0.000515625 +4 chanx_left_out[3]:3 chanx_left_out[3]:2 0.00341 +5 chanx_left_out[3]:2 chanx_left_out[3] 0.000238525 + +*END + +*D_NET chanx_right_out[0] 0.001747596 //LENGTH 14.570 LUMPCC 0.0001201248 DR + +*CONN +*I BUFT_P_95:X O *L 0 *C 101.855 61.880 +*P chanx_right_out[0] O *L 0.7423 *C 100.740 74.870 +*N chanx_right_out[0]:2 *C 100.740 61.925 +*N chanx_right_out[0]:3 *C 100.785 61.880 +*N chanx_right_out[0]:4 *C 101.818 61.880 + +*CAP +0 BUFT_P_95:X 1e-06 +1 chanx_right_out[0] 0.0006937635 +2 chanx_right_out[0]:2 0.0006937635 +3 chanx_right_out[0]:3 0.0001194721 +4 chanx_right_out[0]:4 0.0001194721 +5 chanx_right_out[0] ropt_net_159:6 6.006238e-05 +6 chanx_right_out[0]:2 ropt_net_159:7 6.006238e-05 + +*RES +0 BUFT_P_95:X chanx_right_out[0]:4 0.152 +1 chanx_right_out[0]:4 chanx_right_out[0]:3 0.0009218751 +2 chanx_right_out[0]:3 chanx_right_out[0]:2 0.0045 +3 chanx_right_out[0]:2 chanx_right_out[0] 0.01155804 + +*END + +*D_NET ropt_net_135 0.00194096 //LENGTH 15.125 LUMPCC 0.0002612142 DR + +*CONN +*I BUFT_P_100:X O *L 0 *C 89.700 7.480 +*I ropt_mt_inst_734:A I *L 0.001766 *C 97.825 9.520 +*N ropt_net_135:2 *C 97.863 9.520 +*N ropt_net_135:3 *C 99.315 9.520 +*N ropt_net_135:4 *C 99.360 9.475 +*N ropt_net_135:5 *C 99.360 7.185 +*N ropt_net_135:6 *C 99.315 7.140 +*N ropt_net_135:7 *C 97.520 7.140 +*N ropt_net_135:8 *C 97.520 7.480 +*N ropt_net_135:9 *C 89.738 7.480 + +*CAP +0 BUFT_P_100:X 1e-06 +1 ropt_mt_inst_734:A 1e-06 +2 ropt_net_135:2 0.0001026714 +3 ropt_net_135:3 0.0001026714 +4 ropt_net_135:4 0.0001356563 +5 ropt_net_135:5 0.0001356563 +6 ropt_net_135:6 0.0001021853 +7 ropt_net_135:7 0.0001191659 +8 ropt_net_135:8 0.0004983602 +9 ropt_net_135:9 0.0004813796 +10 ropt_net_135:9 chanx_left_in[19]:15 5.183299e-05 +11 ropt_net_135:5 chanx_left_in[19]:18 3.172904e-06 +12 ropt_net_135:4 chanx_left_in[19]:19 3.172904e-06 +13 ropt_net_135:8 chanx_left_in[19]:16 5.183299e-05 +14 ropt_net_135:8 chanx_left_in[19]:17 6.630715e-06 +15 ropt_net_135:7 chanx_left_in[19]:16 6.630715e-06 +16 ropt_net_135:6 ropt_net_164:3 6.869511e-05 +17 ropt_net_135:5 ropt_net_164:4 2.754019e-07 +18 ropt_net_135:4 ropt_net_164:5 2.754019e-07 +19 ropt_net_135:7 ropt_net_164:2 6.869511e-05 + +*RES +0 BUFT_P_100:X ropt_net_135:9 0.152 +1 ropt_net_135:9 ropt_net_135:8 0.006948661 +2 ropt_net_135:6 ropt_net_135:5 0.0045 +3 ropt_net_135:5 ropt_net_135:4 0.002044643 +4 ropt_net_135:3 ropt_net_135:2 0.001296875 +5 ropt_net_135:4 ropt_net_135:3 0.0045 +6 ropt_net_135:2 ropt_mt_inst_734:A 0.152 +7 ropt_net_135:8 ropt_net_135:7 0.0003035715 +8 ropt_net_135:7 ropt_net_135:6 0.001602679 + +*END + +*D_NET chanx_left_out[4] 0.00194799 //LENGTH 13.640 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 13.340 14.620 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 13.600 +*N chanx_left_out[4]:2 *C 13.333 13.600 +*N chanx_left_out[4]:3 *C 13.340 13.658 +*N chanx_left_out[4]:4 *C 13.340 14.575 +*N chanx_left_out[4]:5 *C 13.340 14.620 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 chanx_left_out[4] 0.0008709945 +2 chanx_left_out[4]:2 0.0008709945 +3 chanx_left_out[4]:3 8.662621e-05 +4 chanx_left_out[4]:4 8.662621e-05 +5 chanx_left_out[4]:5 3.174887e-05 + +*RES +0 ropt_mt_inst_772:X chanx_left_out[4]:5 0.152 +1 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +2 chanx_left_out[4]:4 chanx_left_out[4]:3 0.0008191965 +3 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +4 chanx_left_out[4]:2 chanx_left_out[4] 0.001896058 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..f515697 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,22866 @@ +*SPEF "1481-1998" +*DESIGN "cbx_1__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 3.220 0.680 +chanx_left_in[0] I *C 0.690 57.120 +chanx_left_in[1] I *C 0.690 55.760 +chanx_left_in[2] I *C 0.690 35.360 +chanx_left_in[3] I *C 0.690 46.920 +chanx_left_in[4] I *C 0.690 53.040 +chanx_left_in[5] I *C 0.690 44.880 +chanx_left_in[6] I *C 0.690 31.280 +chanx_left_in[7] I *C 0.690 8.160 +chanx_left_in[8] I *C 0.690 19.040 +chanx_left_in[9] I *C 0.690 36.720 +chanx_left_in[10] I *C 0.690 34.000 +chanx_left_in[11] I *C 0.690 51.680 +chanx_left_in[12] I *C 0.690 14.960 +chanx_left_in[13] I *C 0.690 58.480 +chanx_left_in[14] I *C 0.690 20.400 +chanx_left_in[15] I *C 0.690 40.800 +chanx_left_in[16] I *C 0.690 13.600 +chanx_left_in[17] I *C 0.690 39.440 +chanx_left_in[18] I *C 0.690 25.160 +chanx_left_in[19] I *C 0.690 62.560 +chanx_right_in[0] I *C 104.190 34.000 +chanx_right_in[1] I *C 104.190 54.400 +chanx_right_in[2] I *C 104.190 55.760 +chanx_right_in[3] I *C 104.190 47.600 +chanx_right_in[4] I *C 104.190 53.040 +chanx_right_in[5] I *C 104.190 20.400 +chanx_right_in[6] I *C 104.190 23.120 +chanx_right_in[7] I *C 104.190 38.760 +chanx_right_in[8] I *C 104.190 21.760 +chanx_right_in[9] I *C 104.190 42.160 +chanx_right_in[10] I *C 104.190 25.840 +chanx_right_in[11] I *C 104.190 69.360 +chanx_right_in[12] I *C 104.190 17.680 +chanx_right_in[13] I *C 104.190 72.080 +chanx_right_in[14] I *C 104.190 27.200 +chanx_right_in[15] I *C 102.580 0.680 +chanx_right_in[16] I *C 104.190 4.760 +chanx_right_in[17] I *C 104.190 61.200 +chanx_right_in[18] I *C 104.190 43.520 +chanx_right_in[19] I *C 104.190 63.920 +ccff_head[0] I *C 104.190 37.400 +chanx_left_out[0] O *C 4.600 0.680 +chanx_left_out[1] O *C 0.690 72.080 +chanx_left_out[2] O *C 0.690 28.560 +chanx_left_out[3] O *C 4.600 0.680 +chanx_left_out[4] O *C 0.690 66.640 +chanx_left_out[5] O *C 0.690 68.000 +chanx_left_out[6] O *C 0.690 50.320 +chanx_left_out[7] O *C 0.690 42.160 +chanx_left_out[8] O *C 0.690 17.680 +chanx_left_out[9] O *C 0.690 23.800 +chanx_left_out[10] O *C 0.690 9.520 +chanx_left_out[11] O *C 5.520 0.680 +chanx_left_out[12] O *C 0.690 69.360 +chanx_left_out[13] O *C 6.440 0.680 +chanx_left_out[14] O *C 0.690 63.920 +chanx_left_out[15] O *C 0.690 29.920 +chanx_left_out[16] O *C 0.690 12.240 +chanx_left_out[17] O *C 0.690 6.800 +chanx_left_out[18] O *C 3.220 75.480 +chanx_left_out[19] O *C 0.690 4.080 +chanx_right_out[0] O *C 104.190 48.960 +chanx_right_out[1] O *C 104.190 10.880 +chanx_right_out[2] O *C 100.740 0.680 +chanx_right_out[3] O *C 104.190 12.240 +chanx_right_out[4] O *C 104.190 58.480 +chanx_right_out[5] O *C 104.190 59.840 +chanx_right_out[6] O *C 104.190 6.800 +chanx_right_out[7] O *C 104.190 14.960 +chanx_right_out[8] O *C 104.190 16.320 +chanx_right_out[9] O *C 104.190 44.880 +chanx_right_out[10] O *C 104.190 31.960 +chanx_right_out[11] O *C 104.190 9.520 +chanx_right_out[12] O *C 104.190 70.720 +chanx_right_out[13] O *C 104.190 66.640 +chanx_right_out[14] O *C 104.190 65.280 +chanx_right_out[15] O *C 104.190 50.320 +chanx_right_out[16] O *C 101.660 0.680 +chanx_right_out[17] O *C 104.190 28.560 +chanx_right_out[18] O *C 102.580 75.480 +chanx_right_out[19] O *C 100.280 0.680 +top_grid_pin_16_[0] O *C 34.040 75.480 +top_grid_pin_17_[0] O *C 35.880 75.480 +top_grid_pin_18_[0] O *C 34.960 75.480 +top_grid_pin_19_[0] O *C 36.800 75.480 +top_grid_pin_20_[0] O *C 57.500 75.480 +top_grid_pin_21_[0] O *C 16.100 75.480 +top_grid_pin_22_[0] O *C 33.120 75.480 +top_grid_pin_23_[0] O *C 15.180 75.480 +top_grid_pin_24_[0] O *C 2.300 75.480 +top_grid_pin_25_[0] O *C 12.420 75.480 +top_grid_pin_26_[0] O *C 13.340 75.480 +top_grid_pin_27_[0] O *C 14.260 75.480 +top_grid_pin_28_[0] O *C 73.600 75.480 +top_grid_pin_29_[0] O *C 74.520 75.480 +top_grid_pin_30_[0] O *C 76.360 75.480 +top_grid_pin_31_[0] O *C 75.440 75.480 +ccff_tail[0] O *C 0.690 61.200 +VDD I *C 52.440 38.080 +VSS I *C 52.440 38.080 + +*D_NET chanx_left_in[0] 0.02332642 //LENGTH 166.420 LUMPCC 0.007474943 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.230 57.120 +*I mux_bottom_ipin_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 9.660 28.900 +*I mux_bottom_ipin_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 17.940 25.500 +*I mux_bottom_ipin_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 43.145 25.500 +*I mux_bottom_ipin_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.240 28.900 +*I mux_bottom_ipin_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.705 25.500 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 86.845 28.900 +*I mux_bottom_ipin_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 94.300 34.340 +*I ropt_mt_inst_742:A I *L 0.001767 *C 97.825 47.600 +*I mux_bottom_ipin_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 47.480 28.900 +*N chanx_left_in[0]:10 *C 47.495 28.900 +*N chanx_left_in[0]:11 *C 47.818 28.900 +*N chanx_left_in[0]:12 *C 47.840 28.900 +*N chanx_left_in[0]:13 *C 97.863 47.600 +*N chanx_left_in[0]:14 *C 98.395 47.600 +*N chanx_left_in[0]:15 *C 98.440 47.555 +*N chanx_left_in[0]:16 *C 98.440 39.145 +*N chanx_left_in[0]:17 *C 98.395 39.100 +*N chanx_left_in[0]:18 *C 93.885 39.100 +*N chanx_left_in[0]:19 *C 93.840 39.055 +*N chanx_left_in[0]:20 *C 94.263 34.340 +*N chanx_left_in[0]:21 *C 93.885 34.340 +*N chanx_left_in[0]:22 *C 93.840 34.340 +*N chanx_left_in[0]:23 *C 93.840 29.298 +*N chanx_left_in[0]:24 *C 93.833 29.240 +*N chanx_left_in[0]:25 *C 86.845 28.900 +*N chanx_left_in[0]:26 *C 86.940 28.900 +*N chanx_left_in[0]:27 *C 86.940 29.240 +*N chanx_left_in[0]:28 *C 86.940 29.240 +*N chanx_left_in[0]:29 *C 86.940 28.560 +*N chanx_left_in[0]:30 *C 82.705 25.500 +*N chanx_left_in[0]:31 *C 82.800 25.545 +*N chanx_left_in[0]:32 *C 82.800 28.503 +*N chanx_left_in[0]:33 *C 82.800 28.560 +*N chanx_left_in[0]:34 *C 73.140 28.900 +*N chanx_left_in[0]:35 *C 73.140 28.900 +*N chanx_left_in[0]:36 *C 73.140 28.560 +*N chanx_left_in[0]:37 *C 73.140 28.560 +*N chanx_left_in[0]:38 *C 47.848 28.560 +*N chanx_left_in[0]:39 *C 47.840 28.503 +*N chanx_left_in[0]:40 *C 47.840 25.545 +*N chanx_left_in[0]:41 *C 47.795 25.500 +*N chanx_left_in[0]:42 *C 43.183 25.500 +*N chanx_left_in[0]:43 *C 42.803 25.500 +*N chanx_left_in[0]:44 *C 42.780 25.455 +*N chanx_left_in[0]:45 *C 42.780 24.538 +*N chanx_left_in[0]:46 *C 42.773 24.480 +*N chanx_left_in[0]:47 *C 18.408 24.480 +*N chanx_left_in[0]:48 *C 18.400 24.538 +*N chanx_left_in[0]:49 *C 17.940 25.500 +*N chanx_left_in[0]:50 *C 17.940 25.500 +*N chanx_left_in[0]:51 *C 18.400 25.500 +*N chanx_left_in[0]:52 *C 18.400 29.195 +*N chanx_left_in[0]:53 *C 18.355 29.240 +*N chanx_left_in[0]:54 *C 9.660 28.915 +*N chanx_left_in[0]:55 *C 9.683 29.240 +*N chanx_left_in[0]:56 *C 9.660 29.285 +*N chanx_left_in[0]:57 *C 9.660 31.902 +*N chanx_left_in[0]:58 *C 9.652 31.960 +*N chanx_left_in[0]:59 *C 8.300 31.960 +*N chanx_left_in[0]:60 *C 8.280 31.968 +*N chanx_left_in[0]:61 *C 8.280 57.113 +*N chanx_left_in[0]:62 *C 8.260 57.120 + +*CAP +0 chanx_left_in[0] 0.0005483266 +1 mux_bottom_ipin_10\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_ipin_8\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_ipin_2\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_ipin_12\/mux_l1_in_0_:A1 1e-06 +5 mux_bottom_ipin_6\/mux_l1_in_0_:A1 1e-06 +6 mux_bottom_ipin_0\/mux_l1_in_0_:A1 1e-06 +7 mux_bottom_ipin_14\/mux_l1_in_0_:A1 1e-06 +8 ropt_mt_inst_742:A 1e-06 +9 mux_bottom_ipin_4\/mux_l1_in_0_:A1 1e-06 +10 chanx_left_in[0]:10 3.792274e-05 +11 chanx_left_in[0]:11 3.792274e-05 +12 chanx_left_in[0]:12 5.594618e-05 +13 chanx_left_in[0]:13 5.369847e-05 +14 chanx_left_in[0]:14 5.369847e-05 +15 chanx_left_in[0]:15 0.0003833762 +16 chanx_left_in[0]:16 0.0003833762 +17 chanx_left_in[0]:17 0.000305554 +18 chanx_left_in[0]:18 0.000305554 +19 chanx_left_in[0]:19 0.0002662671 +20 chanx_left_in[0]:20 4.998934e-05 +21 chanx_left_in[0]:21 4.998934e-05 +22 chanx_left_in[0]:22 0.0005566817 +23 chanx_left_in[0]:23 0.0002592491 +24 chanx_left_in[0]:24 0.0003670999 +25 chanx_left_in[0]:25 2.884443e-05 +26 chanx_left_in[0]:26 4.869077e-05 +27 chanx_left_in[0]:27 5.326907e-05 +28 chanx_left_in[0]:28 0.0004205451 +29 chanx_left_in[0]:29 0.0003682965 +30 chanx_left_in[0]:30 2.786334e-05 +31 chanx_left_in[0]:31 0.0001509865 +32 chanx_left_in[0]:32 0.0001509865 +33 chanx_left_in[0]:33 0.0008488304 +34 chanx_left_in[0]:34 3.295821e-05 +35 chanx_left_in[0]:35 5.372623e-05 +36 chanx_left_in[0]:36 5.828012e-05 +37 chanx_left_in[0]:37 0.001667001 +38 chanx_left_in[0]:38 0.001133022 +39 chanx_left_in[0]:39 0.000144948 +40 chanx_left_in[0]:40 0.0001227231 +41 chanx_left_in[0]:41 0.0002953548 +42 chanx_left_in[0]:42 0.0003299533 +43 chanx_left_in[0]:43 3.459846e-05 +44 chanx_left_in[0]:44 6.710238e-05 +45 chanx_left_in[0]:45 6.710238e-05 +46 chanx_left_in[0]:46 0.0006323946 +47 chanx_left_in[0]:47 0.0006323946 +48 chanx_left_in[0]:48 6.640766e-05 +49 chanx_left_in[0]:49 3.741168e-05 +50 chanx_left_in[0]:50 5.699867e-05 +51 chanx_left_in[0]:51 0.000304887 +52 chanx_left_in[0]:52 0.0002143517 +53 chanx_left_in[0]:53 0.0004936312 +54 chanx_left_in[0]:54 3.565355e-05 +55 chanx_left_in[0]:55 0.0005292848 +56 chanx_left_in[0]:56 0.0001930616 +57 chanx_left_in[0]:57 0.0001930616 +58 chanx_left_in[0]:58 0.0001499175 +59 chanx_left_in[0]:59 0.0001499175 +60 chanx_left_in[0]:60 0.0008925191 +61 chanx_left_in[0]:61 0.0008925191 +62 chanx_left_in[0]:62 0.0005483266 +63 chanx_left_in[0]:44 chanx_left_in[2]:46 8.190692e-06 +64 chanx_left_in[0]:45 chanx_left_in[2]:45 8.190692e-06 +65 chanx_left_in[0]:46 chanx_left_in[2]:53 0.0006553854 +66 chanx_left_in[0]:47 chanx_left_in[2]:54 0.0006553854 +67 chanx_left_in[0]:32 chanx_left_in[2]:30 4.732764e-07 +68 chanx_left_in[0]:32 chanx_left_in[2]:21 2.510425e-07 +69 chanx_left_in[0]:31 chanx_left_in[2]:20 2.510425e-07 +70 chanx_left_in[0]:31 chanx_left_in[2]:31 4.732764e-07 +71 chanx_left_in[0]:50 chanx_left_in[2]:54 5.289467e-06 +72 chanx_left_in[0]:27 chanx_left_in[2]:20 9.15118e-06 +73 chanx_left_in[0]:26 chanx_left_in[2]:21 9.15118e-06 +74 chanx_left_in[0]:51 chanx_left_in[2]:53 5.289467e-06 +75 chanx_left_in[0]:46 chanx_left_in[8]:26 0.0005644749 +76 chanx_left_in[0]:47 chanx_left_in[8]:30 0.0005644749 +77 chanx_left_in[0]:38 chanx_left_in[12]:12 1.233308e-05 +78 chanx_left_in[0]:38 chanx_left_in[12]:9 3.469304e-05 +79 chanx_left_in[0]:38 chanx_left_in[12]:27 0.0001094526 +80 chanx_left_in[0]:38 chanx_left_in[12]:22 8.099332e-05 +81 chanx_left_in[0]:58 chanx_left_in[12]:27 3.162681e-05 +82 chanx_left_in[0]:59 chanx_left_in[12]:28 3.162681e-05 +83 chanx_left_in[0]:36 chanx_left_in[12]:6 3.701107e-06 +84 chanx_left_in[0]:37 chanx_left_in[12]:21 8.099332e-05 +85 chanx_left_in[0]:37 chanx_left_in[12]:9 5.791068e-05 +86 chanx_left_in[0]:37 chanx_left_in[12]:8 3.469304e-05 +87 chanx_left_in[0]:37 chanx_left_in[12]:11 1.233308e-05 +88 chanx_left_in[0]:37 chanx_left_in[12]:22 0.0001094526 +89 chanx_left_in[0]:35 chanx_left_in[12]:7 3.701107e-06 +90 chanx_left_in[0]:33 chanx_left_in[12]:8 5.791068e-05 +91 chanx_left_in[0]:60 chanx_left_in[17]:27 0.0003643706 +92 chanx_left_in[0]:61 chanx_left_in[17]:26 0.0003643706 +93 chanx_left_in[0]:16 chanx_left_in[17]:6 5.694887e-05 +94 chanx_left_in[0]:15 chanx_left_in[17]:7 5.694887e-05 +95 chanx_left_in[0]:41 chanx_right_in[0]:31 7.423559e-06 +96 chanx_left_in[0]:41 chanx_right_in[0]:29 2.220156e-05 +97 chanx_left_in[0]:43 chanx_right_in[0]:28 3.15242e-05 +98 chanx_left_in[0]:43 chanx_right_in[0]:30 6.434077e-07 +99 chanx_left_in[0]:46 chanx_right_in[0]:26 0.0001274689 +100 chanx_left_in[0]:47 chanx_right_in[0]:25 0.0001274689 +101 chanx_left_in[0]:23 chanx_right_in[0]:48 3.519239e-05 +102 chanx_left_in[0]:23 chanx_right_in[0]:52 3.938502e-06 +103 chanx_left_in[0]:24 chanx_right_in[0]:47 0.0001455499 +104 chanx_left_in[0]:38 chanx_right_in[0]:35 8.27483e-06 +105 chanx_left_in[0]:55 chanx_right_in[0]:12 4.061938e-07 +106 chanx_left_in[0]:55 chanx_right_in[0]:18 0.0001077824 +107 chanx_left_in[0]:53 chanx_right_in[0]:19 0.0001077824 +108 chanx_left_in[0]:53 chanx_right_in[0]:17 4.061938e-07 +109 chanx_left_in[0]:52 chanx_right_in[0]:23 4.496469e-07 +110 chanx_left_in[0]:52 chanx_right_in[0]:20 3.229221e-06 +111 chanx_left_in[0]:42 chanx_right_in[0]:28 2.220156e-05 +112 chanx_left_in[0]:42 chanx_right_in[0]:31 6.434077e-07 +113 chanx_left_in[0]:42 chanx_right_in[0]:30 7.423559e-06 +114 chanx_left_in[0]:42 chanx_right_in[0]:29 3.15242e-05 +115 chanx_left_in[0]:37 chanx_right_in[0]:36 8.27483e-06 +116 chanx_left_in[0]:11 chanx_right_in[0]:36 5.026106e-06 +117 chanx_left_in[0]:10 chanx_right_in[0]:35 5.026106e-06 +118 chanx_left_in[0]:32 chanx_right_in[0]:40 4.284873e-05 +119 chanx_left_in[0]:31 chanx_right_in[0]:39 4.284873e-05 +120 chanx_left_in[0]:22 chanx_right_in[0]:51 3.913089e-05 +121 chanx_left_in[0]:50 chanx_right_in[0]:25 5.289467e-06 +122 chanx_left_in[0]:27 chanx_right_in[0]:44 3.69616e-06 +123 chanx_left_in[0]:28 chanx_right_in[0]:45 1.396129e-05 +124 chanx_left_in[0]:28 chanx_right_in[0]:46 0.0001455499 +125 chanx_left_in[0]:26 chanx_right_in[0]:45 3.69616e-06 +126 chanx_left_in[0]:51 chanx_right_in[0]:23 3.229221e-06 +127 chanx_left_in[0]:51 chanx_right_in[0]:26 5.289467e-06 +128 chanx_left_in[0]:51 chanx_right_in[0]:24 4.496469e-07 +129 chanx_left_in[0]:29 chanx_right_in[0]:44 1.396129e-05 +130 chanx_left_in[0]:41 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 5.260362e-06 +131 chanx_left_in[0]:46 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.0001212978 +132 chanx_left_in[0]:47 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.0001212978 +133 chanx_left_in[0]:38 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.0001380763 +134 chanx_left_in[0]:42 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 5.260362e-06 +135 chanx_left_in[0]:37 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.0001380763 +136 chanx_left_in[0]:38 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.470516e-05 +137 chanx_left_in[0]:37 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001259943 +138 chanx_left_in[0]:37 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.470516e-05 +139 chanx_left_in[0]:33 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001259943 +140 chanx_left_in[0]:38 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0002764228 +141 chanx_left_in[0]:37 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0002764228 +142 chanx_left_in[0]:40 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.941508e-05 +143 chanx_left_in[0]:39 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.941508e-05 +144 chanx_left_in[0]:60 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0003042754 +145 chanx_left_in[0]:61 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003042754 +146 chanx_left_in[0]:16 ropt_net_160:5 6.18719e-05 +147 chanx_left_in[0]:15 ropt_net_160:4 6.18719e-05 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:62 0.001101367 +1 chanx_left_in[0]:41 chanx_left_in[0]:40 0.0045 +2 chanx_left_in[0]:40 chanx_left_in[0]:39 0.002640625 +3 chanx_left_in[0]:43 chanx_left_in[0]:42 0.0002065218 +4 chanx_left_in[0]:44 chanx_left_in[0]:43 0.0045 +5 chanx_left_in[0]:45 chanx_left_in[0]:44 0.0008191965 +6 chanx_left_in[0]:46 chanx_left_in[0]:45 0.00341 +7 chanx_left_in[0]:48 chanx_left_in[0]:47 0.00341 +8 chanx_left_in[0]:47 chanx_left_in[0]:46 0.003817183 +9 chanx_left_in[0]:23 chanx_left_in[0]:22 0.004502232 +10 chanx_left_in[0]:24 chanx_left_in[0]:23 0.00341 +11 chanx_left_in[0]:39 chanx_left_in[0]:38 0.00341 +12 chanx_left_in[0]:39 chanx_left_in[0]:12 0.0001911058 +13 chanx_left_in[0]:38 chanx_left_in[0]:37 0.003962492 +14 chanx_left_in[0]:55 chanx_left_in[0]:54 0.0001766304 +15 chanx_left_in[0]:55 chanx_left_in[0]:53 0.007743304 +16 chanx_left_in[0]:56 chanx_left_in[0]:55 0.0045 +17 chanx_left_in[0]:57 chanx_left_in[0]:56 0.002337053 +18 chanx_left_in[0]:58 chanx_left_in[0]:57 0.00341 +19 chanx_left_in[0]:59 chanx_left_in[0]:58 0.0002118917 +20 chanx_left_in[0]:60 chanx_left_in[0]:59 0.00341 +21 chanx_left_in[0]:62 chanx_left_in[0]:61 0.00341 +22 chanx_left_in[0]:61 chanx_left_in[0]:60 0.003939383 +23 chanx_left_in[0]:53 chanx_left_in[0]:52 0.0045 +24 chanx_left_in[0]:52 chanx_left_in[0]:51 0.003299107 +25 chanx_left_in[0]:42 mux_bottom_ipin_2\/mux_l1_in_0_:A1 0.152 +26 chanx_left_in[0]:42 chanx_left_in[0]:41 0.004118304 +27 chanx_left_in[0]:54 mux_bottom_ipin_10\/mux_l1_in_0_:A1 0.152 +28 chanx_left_in[0]:36 chanx_left_in[0]:35 0.0001634616 +29 chanx_left_in[0]:37 chanx_left_in[0]:36 0.00341 +30 chanx_left_in[0]:37 chanx_left_in[0]:33 0.0015134 +31 chanx_left_in[0]:34 mux_bottom_ipin_12\/mux_l1_in_0_:A1 0.152 +32 chanx_left_in[0]:35 chanx_left_in[0]:34 0.0045 +33 chanx_left_in[0]:11 chanx_left_in[0]:10 0.0001752717 +34 chanx_left_in[0]:12 chanx_left_in[0]:11 0.0045 +35 chanx_left_in[0]:10 mux_bottom_ipin_4\/mux_l1_in_0_:A1 0.152 +36 chanx_left_in[0]:32 chanx_left_in[0]:31 0.002640625 +37 chanx_left_in[0]:33 chanx_left_in[0]:32 0.00341 +38 chanx_left_in[0]:33 chanx_left_in[0]:29 0.0006485999 +39 chanx_left_in[0]:30 mux_bottom_ipin_6\/mux_l1_in_0_:A1 0.152 +40 chanx_left_in[0]:31 chanx_left_in[0]:30 0.0045 +41 chanx_left_in[0]:21 chanx_left_in[0]:20 0.0003370536 +42 chanx_left_in[0]:22 chanx_left_in[0]:21 0.0045 +43 chanx_left_in[0]:22 chanx_left_in[0]:19 0.004209822 +44 chanx_left_in[0]:20 mux_bottom_ipin_14\/mux_l1_in_0_:A1 0.152 +45 chanx_left_in[0]:18 chanx_left_in[0]:17 0.004026786 +46 chanx_left_in[0]:19 chanx_left_in[0]:18 0.0045 +47 chanx_left_in[0]:17 chanx_left_in[0]:16 0.0045 +48 chanx_left_in[0]:16 chanx_left_in[0]:15 0.007508929 +49 chanx_left_in[0]:14 chanx_left_in[0]:13 0.0004754465 +50 chanx_left_in[0]:15 chanx_left_in[0]:14 0.0045 +51 chanx_left_in[0]:13 ropt_mt_inst_742:A 0.152 +52 chanx_left_in[0]:49 mux_bottom_ipin_8\/mux_l1_in_0_:A1 0.152 +53 chanx_left_in[0]:50 chanx_left_in[0]:49 0.0045 +54 chanx_left_in[0]:27 chanx_left_in[0]:26 0.0001634615 +55 chanx_left_in[0]:28 chanx_left_in[0]:27 0.00341 +56 chanx_left_in[0]:28 chanx_left_in[0]:24 0.001079825 +57 chanx_left_in[0]:25 mux_bottom_ipin_0\/mux_l1_in_0_:A1 0.152 +58 chanx_left_in[0]:26 chanx_left_in[0]:25 0.0045 +59 chanx_left_in[0]:51 chanx_left_in[0]:50 0.0004107143 +60 chanx_left_in[0]:51 chanx_left_in[0]:48 0.0008593751 +61 chanx_left_in[0]:29 chanx_left_in[0]:28 0.0001065333 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001681685 //LENGTH 13.380 LUMPCC 0.0004660463 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l3_in_0_:X O *L 0 *C 13.055 33.320 +*I mux_bottom_ipin_8\/mux_l4_in_0_:A1 I *L 0.00198 *C 9.105 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 9.143 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 9.615 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 9.660 41.775 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 9.660 33.365 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 9.705 33.320 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 13.018 33.320 + +*CAP +0 mux_bottom_ipin_8\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.969875e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.969875e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003565236 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003565236 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001905969 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001905969 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[9]:11 1.840762e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[9]:13 8.468766e-06 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[9]:15 3.180332e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_right_in[9]:12 1.840762e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_right_in[9]:14 8.468766e-06 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_right_in[9]:16 3.180332e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:10 8.949054e-07 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:19 6.936525e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_4_sram[2]:8 7.507935e-07 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:9 8.949054e-07 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:20 6.936525e-05 +19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_4_sram[2]:7 7.507935e-07 +20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_4_sram[0]:8 0.0001033325 +21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_4_sram[0]:7 0.0001033325 + +*RES +0 mux_bottom_ipin_8\/mux_l3_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_8\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.000421875 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.007508928 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002957589 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001357947 //LENGTH 11.140 LUMPCC 0.0002705771 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l4_in_0_:X O *L 0 *C 80.675 64.600 +*I mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 77.915 71.950 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 77.915 71.950 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 78.170 72.050 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 78.200 72.035 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 78.200 64.645 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 78.245 64.600 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 80.638 64.600 + +*CAP +0 mux_bottom_ipin_13\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.203783e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.289507e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003195415 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0003195415 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001756769 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001756769 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001352886 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001352886 + +*RES +0 mux_bottom_ipin_13\/mux_l4_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00213616 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.006598215 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.000159375 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002663309 //LENGTH 19.255 LUMPCC 0.0004626252 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_2_:X O *L 0 *C 93.555 41.820 +*I mux_bottom_ipin_6\/mux_l3_in_1_:A1 I *L 0.00198 *C 78.660 45.220 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.660 45.220 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 78.660 45.220 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 78.660 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 78.668 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 92.453 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 92.460 44.823 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 92.460 41.865 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 92.505 41.820 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 93.517 41.820 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.091267e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.016726e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.400015e-05 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0007067358 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0007067358 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002187797 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002187797 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001062864 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001062864 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_left_in[15]:8 1.780779e-07 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[15]:7 1.780779e-07 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[15]:9 9.783704e-05 +14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[15]:14 9.783704e-05 +15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size8_6_sram[2]:20 0.0001332975 +16 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_6_sram[2]:19 0.0001332975 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_2_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0009040179 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002640625 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00215965 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001634615 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_1_:A1 0.152 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0] 0.004372309 //LENGTH 36.480 LUMPCC 0.0006896744 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l4_in_0_:X O *L 0 *C 16.735 39.780 +*I mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 18.960 71.905 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 18.960 71.905 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 18.860 72.420 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 16.605 72.420 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 16.560 72.375 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 16.560 39.825 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 16.560 39.780 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 16.735 39.780 + +*CAP +0 mux_bottom_ipin_11\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.407629e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002146884 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001784745 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001552962 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001552962 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.045771e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 5.701343e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000301393 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000301393 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.344414e-05 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.344414e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l4_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002013393 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0290625 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.51087e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004598215 + +*END + +*D_NET ropt_net_143 0.001022558 //LENGTH 8.675 LUMPCC 0 DR + +*CONN +*I FTB_8__7:X O *L 0 *C 97.980 25.500 +*I ropt_mt_inst_740:A I *L 0.001766 *C 97.825 17.680 +*N ropt_net_143:2 *C 97.825 17.680 +*N ropt_net_143:3 *C 97.980 17.680 +*N ropt_net_143:4 *C 97.980 17.725 +*N ropt_net_143:5 *C 97.980 25.115 +*N ropt_net_143:6 *C 97.980 25.160 +*N ropt_net_143:7 *C 97.980 25.500 + +*CAP +0 FTB_8__7:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_143:2 5.368127e-05 +3 ropt_net_143:3 5.339887e-05 +4 ropt_net_143:4 0.0003910685 +5 ropt_net_143:5 0.0003910685 +6 ropt_net_143:6 6.788984e-05 +7 ropt_net_143:7 6.34511e-05 + +*RES +0 FTB_8__7:X ropt_net_143:7 0.152 +1 ropt_net_143:2 ropt_mt_inst_740:A 0.152 +2 ropt_net_143:3 ropt_net_143:2 8.423914e-05 +3 ropt_net_143:4 ropt_net_143:3 0.0045 +4 ropt_net_143:6 ropt_net_143:5 0.0045 +5 ropt_net_143:5 ropt_net_143:4 0.006598214 +6 ropt_net_143:7 ropt_net_143:6 0.0001465518 + +*END + +*D_NET ropt_net_192 0.0008559149 //LENGTH 5.945 LUMPCC 0.0003080991 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 4.140 26.520 +*I ropt_mt_inst_801:A I *L 0.001766 *C 7.820 25.840 +*N ropt_net_192:2 *C 7.783 25.840 +*N ropt_net_192:3 *C 7.020 25.840 +*N ropt_net_192:4 *C 7.020 25.500 +*N ropt_net_192:5 *C 4.185 25.500 +*N ropt_net_192:6 *C 4.140 25.545 +*N ropt_net_192:7 *C 4.140 26.475 +*N ropt_net_192:8 *C 4.140 26.520 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_192:2 6.263809e-05 +3 ropt_net_192:3 9.187465e-05 +4 ropt_net_192:4 0.0001544566 +5 ropt_net_192:5 0.00012522 +6 ropt_net_192:6 3.968815e-05 +7 ropt_net_192:7 3.968815e-05 +8 ropt_net_192:8 3.225011e-05 +9 ropt_net_192:2 chanx_left_in[2]:57 6.670278e-06 +10 ropt_net_192:5 chanx_left_in[2]:58 0.0001109752 +11 ropt_net_192:6 chanx_left_in[2]:59 3.640407e-05 +12 ropt_net_192:7 chanx_left_in[2]:60 3.640407e-05 +13 ropt_net_192:4 chanx_left_in[2]:57 0.0001109752 +14 ropt_net_192:3 chanx_left_in[2]:58 6.670278e-06 + +*RES +0 ropt_mt_inst_736:X ropt_net_192:8 0.152 +1 ropt_net_192:2 ropt_mt_inst_801:A 0.152 +2 ropt_net_192:5 ropt_net_192:4 0.00253125 +3 ropt_net_192:6 ropt_net_192:5 0.0045 +4 ropt_net_192:8 ropt_net_192:7 0.0045 +5 ropt_net_192:7 ropt_net_192:6 0.0008303572 +6 ropt_net_192:4 ropt_net_192:3 0.0003035715 +7 ropt_net_192:3 ropt_net_192:2 0.0006808036 + +*END + +*D_NET ropt_net_133 0.002166074 //LENGTH 13.390 LUMPCC 0.0009600585 DR + +*CONN +*I BUFT_RR_70:X O *L 0 *C 15.350 9.180 +*I ropt_mt_inst_730:A I *L 0.001766 *C 3.220 9.520 +*N ropt_net_133:2 *C 3.258 9.520 +*N ropt_net_133:3 *C 4.075 9.520 +*N ropt_net_133:4 *C 4.120 9.520 +*N ropt_net_133:5 *C 4.128 9.520 +*N ropt_net_133:6 *C 11.033 9.520 +*N ropt_net_133:7 *C 11.040 9.520 +*N ropt_net_133:8 *C 11.040 9.180 +*N ropt_net_133:9 *C 11.085 9.180 +*N ropt_net_133:10 *C 15.312 9.180 + +*CAP +0 BUFT_RR_70:X 1e-06 +1 ropt_mt_inst_730:A 1e-06 +2 ropt_net_133:2 6.780346e-05 +3 ropt_net_133:3 6.780346e-05 +4 ropt_net_133:4 3.287198e-05 +5 ropt_net_133:5 0.0001756958 +6 ropt_net_133:6 0.0001756958 +7 ropt_net_133:7 5.483049e-05 +8 ropt_net_133:8 5.096434e-05 +9 ropt_net_133:9 0.000289175 +10 ropt_net_133:10 0.000289175 +11 ropt_net_133:6 prog_clk[0]:313 0.0003477648 +12 ropt_net_133:6 prog_clk[0]:378 6.081825e-05 +13 ropt_net_133:5 prog_clk[0]:378 0.0003477648 +14 ropt_net_133:5 prog_clk[0]:379 6.081825e-05 +15 ropt_net_133:6 chanx_left_out[17]:4 7.144621e-05 +16 ropt_net_133:5 chanx_left_out[17]:3 7.144621e-05 + +*RES +0 BUFT_RR_70:X ropt_net_133:10 0.152 +1 ropt_net_133:10 ropt_net_133:9 0.003774554 +2 ropt_net_133:9 ropt_net_133:8 0.0045 +3 ropt_net_133:8 ropt_net_133:7 0.0001634615 +4 ropt_net_133:7 ropt_net_133:6 0.00341 +5 ropt_net_133:6 ropt_net_133:5 0.001081783 +6 ropt_net_133:4 ropt_net_133:3 0.0045 +7 ropt_net_133:5 ropt_net_133:4 0.00341 +8 ropt_net_133:3 ropt_net_133:2 0.0007299107 +9 ropt_net_133:2 ropt_mt_inst_730:A 0.152 + +*END + +*D_NET ropt_net_160 0.000505847 //LENGTH 3.585 LUMPCC 0.0002715739 DR + +*CONN +*I BUFT_P_96:X O *L 0 *C 98.900 42.840 +*I ropt_mt_inst_761:A I *L 0.001766 *C 97.980 44.880 +*N ropt_net_160:2 *C 98.017 44.880 +*N ropt_net_160:3 *C 98.855 44.880 +*N ropt_net_160:4 *C 98.900 44.835 +*N ropt_net_160:5 *C 98.900 42.885 +*N ropt_net_160:6 *C 98.900 42.840 + +*CAP +0 BUFT_P_96:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_160:2 3.947979e-05 +3 ropt_net_160:3 3.947979e-05 +4 ropt_net_160:4 6.070373e-05 +5 ropt_net_160:5 6.070373e-05 +6 ropt_net_160:6 3.190607e-05 +7 ropt_net_160:4 chanx_left_in[0]:15 6.18719e-05 +8 ropt_net_160:5 chanx_left_in[0]:16 6.18719e-05 +9 ropt_net_160:2 chanx_right_in[10]:5 4.480654e-05 +10 ropt_net_160:3 chanx_right_in[10]:6 4.480654e-05 +11 ropt_net_160:4 chanx_right_in[10]:7 2.91085e-05 +12 ropt_net_160:5 chanx_right_in[10]:10 2.91085e-05 + +*RES +0 BUFT_P_96:X ropt_net_160:6 0.152 +1 ropt_net_160:2 ropt_mt_inst_761:A 0.152 +2 ropt_net_160:3 ropt_net_160:2 0.0007477679 +3 ropt_net_160:4 ropt_net_160:3 0.0045 +4 ropt_net_160:6 ropt_net_160:5 0.0045 +5 ropt_net_160:5 ropt_net_160:4 0.001741071 + +*END + +*D_NET chanx_left_in[1] 0.02142207 //LENGTH 150.885 LUMPCC 0.004564094 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 55.760 +*I mux_bottom_ipin_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 23.825 52.700 +*I mux_bottom_ipin_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 36.340 50.660 +*I BUFT_RR_59:A I *L 0.001776 *C 94.760 20.400 +*I mux_bottom_ipin_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 89.605 52.700 +*I mux_bottom_ipin_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.585 52.700 +*I mux_bottom_ipin_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 65.685 52.700 +*I mux_bottom_ipin_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.200 56.100 +*I mux_bottom_ipin_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.925 50.660 +*I mux_bottom_ipin_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 28.885 52.700 +*N chanx_left_in[1]:10 *C 28.885 52.700 +*N chanx_left_in[1]:11 *C 39.888 50.660 +*N chanx_left_in[1]:12 *C 39.560 50.660 +*N chanx_left_in[1]:13 *C 55.200 56.100 +*N chanx_left_in[1]:14 *C 55.200 56.055 +*N chanx_left_in[1]:15 *C 65.722 52.700 +*N chanx_left_in[1]:16 *C 66.700 52.700 +*N chanx_left_in[1]:17 *C 72.585 52.700 +*N chanx_left_in[1]:18 *C 89.605 52.700 +*N chanx_left_in[1]:19 *C 94.797 20.400 +*N chanx_left_in[1]:20 *C 96.555 20.400 +*N chanx_left_in[1]:21 *C 96.600 20.445 +*N chanx_left_in[1]:22 *C 96.600 52.315 +*N chanx_left_in[1]:23 *C 96.555 52.360 +*N chanx_left_in[1]:24 *C 89.700 52.360 +*N chanx_left_in[1]:25 *C 72.680 52.360 +*N chanx_left_in[1]:26 *C 66.700 52.360 +*N chanx_left_in[1]:27 *C 56.580 52.360 +*N chanx_left_in[1]:28 *C 56.580 53.040 +*N chanx_left_in[1]:29 *C 55.245 53.040 +*N chanx_left_in[1]:30 *C 55.200 53.040 +*N chanx_left_in[1]:31 *C 55.200 51.045 +*N chanx_left_in[1]:32 *C 55.155 51.000 +*N chanx_left_in[1]:33 *C 39.560 51.000 +*N chanx_left_in[1]:34 *C 36.378 50.660 +*N chanx_left_in[1]:35 *C 37.260 50.660 +*N chanx_left_in[1]:36 *C 37.260 51.000 +*N chanx_left_in[1]:37 *C 37.260 51.045 +*N chanx_left_in[1]:38 *C 37.260 52.315 +*N chanx_left_in[1]:39 *C 37.215 52.360 +*N chanx_left_in[1]:40 *C 28.980 52.360 +*N chanx_left_in[1]:41 *C 24.840 52.360 +*N chanx_left_in[1]:42 *C 23.863 52.700 +*N chanx_left_in[1]:43 *C 24.840 52.670 +*N chanx_left_in[1]:44 *C 24.840 52.745 +*N chanx_left_in[1]:45 *C 24.840 53.663 +*N chanx_left_in[1]:46 *C 24.832 53.720 +*N chanx_left_in[1]:47 *C 2.780 53.720 +*N chanx_left_in[1]:48 *C 2.760 53.727 +*N chanx_left_in[1]:49 *C 2.760 55.753 +*N chanx_left_in[1]:50 *C 2.740 55.760 + +*CAP +0 chanx_left_in[1] 0.0001377936 +1 mux_bottom_ipin_9\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_ipin_3\/mux_l1_in_0_:A1 1e-06 +3 BUFT_RR_59:A 1e-06 +4 mux_bottom_ipin_13\/mux_l1_in_0_:A1 1e-06 +5 mux_bottom_ipin_15\/mux_l1_in_0_:A1 1e-06 +6 mux_bottom_ipin_1\/mux_l1_in_0_:A1 1e-06 +7 mux_bottom_ipin_5\/mux_l1_in_0_:A1 1e-06 +8 mux_bottom_ipin_7\/mux_l1_in_0_:A1 1e-06 +9 mux_bottom_ipin_11\/mux_l1_in_0_:A1 1e-06 +10 chanx_left_in[1]:10 5.646765e-05 +11 chanx_left_in[1]:11 3.026826e-05 +12 chanx_left_in[1]:12 5.464772e-05 +13 chanx_left_in[1]:13 3.252509e-05 +14 chanx_left_in[1]:14 0.0001923171 +15 chanx_left_in[1]:15 0.0001069234 +16 chanx_left_in[1]:16 0.0001350958 +17 chanx_left_in[1]:17 5.171778e-05 +18 chanx_left_in[1]:18 5.558136e-05 +19 chanx_left_in[1]:19 9.685721e-05 +20 chanx_left_in[1]:20 9.685721e-05 +21 chanx_left_in[1]:21 0.001144376 +22 chanx_left_in[1]:22 0.001144376 +23 chanx_left_in[1]:23 0.0004833612 +24 chanx_left_in[1]:24 0.001604678 +25 chanx_left_in[1]:25 0.001512185 +26 chanx_left_in[1]:26 0.001084674 +27 chanx_left_in[1]:27 0.0007116452 +28 chanx_left_in[1]:28 0.000115295 +29 chanx_left_in[1]:29 6.753545e-05 +30 chanx_left_in[1]:30 0.0003319884 +31 chanx_left_in[1]:31 0.0001080866 +32 chanx_left_in[1]:32 0.001069051 +33 chanx_left_in[1]:33 0.001281194 +34 chanx_left_in[1]:34 8.5994e-05 +35 chanx_left_in[1]:35 0.000113138 +36 chanx_left_in[1]:36 0.0002149074 +37 chanx_left_in[1]:37 8.650418e-05 +38 chanx_left_in[1]:38 8.650418e-05 +39 chanx_left_in[1]:39 0.0005492766 +40 chanx_left_in[1]:40 0.0008422539 +41 chanx_left_in[1]:41 0.0002946263 +42 chanx_left_in[1]:42 0.0001042422 +43 chanx_left_in[1]:43 0.0001304631 +44 chanx_left_in[1]:44 6.305191e-05 +45 chanx_left_in[1]:45 6.305191e-05 +46 chanx_left_in[1]:46 0.001047279 +47 chanx_left_in[1]:47 0.001047279 +48 chanx_left_in[1]:48 0.0001385549 +49 chanx_left_in[1]:49 0.0001385549 +50 chanx_left_in[1]:50 0.0001377936 +51 chanx_left_in[1] chanx_left_in[4] 6.250455e-06 +52 chanx_left_in[1]:44 chanx_left_in[4]:32 2.698936e-06 +53 chanx_left_in[1]:45 chanx_left_in[4]:33 2.698936e-06 +54 chanx_left_in[1]:46 chanx_left_in[4]:34 0.001090896 +55 chanx_left_in[1]:47 chanx_left_in[4] 0.001090896 +56 chanx_left_in[1]:50 chanx_left_in[4]:34 6.250455e-06 +57 chanx_left_in[1]:22 chanx_left_in[17]:7 0.0004761032 +58 chanx_left_in[1]:21 chanx_left_in[17]:6 0.0004761032 +59 chanx_left_in[1]:48 chanx_left_in[17]:27 1.529909e-05 +60 chanx_left_in[1]:49 chanx_left_in[17]:26 1.529909e-05 +61 chanx_left_in[1]:22 mux_tree_tapbuf_size8_6_sram[0]:9 0.000421083 +62 chanx_left_in[1]:21 mux_tree_tapbuf_size8_6_sram[0]:10 9.779079e-06 +63 chanx_left_in[1]:21 mux_tree_tapbuf_size8_6_sram[0]:6 0.0004113039 +64 chanx_left_in[1]:29 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.162954e-05 +65 chanx_left_in[1]:28 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.162954e-05 +66 chanx_left_in[1]:31 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.407464e-05 +67 chanx_left_in[1]:29 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.616121e-06 +68 chanx_left_in[1]:30 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.407464e-05 +69 chanx_left_in[1]:28 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.616121e-06 +70 chanx_left_in[1]:25 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.068033e-05 +71 chanx_left_in[1]:24 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.068033e-05 +72 chanx_left_in[1]:10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.677974e-06 +73 chanx_left_in[1]:41 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.746472e-05 +74 chanx_left_in[1]:40 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.677974e-06 +75 chanx_left_in[1]:40 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.746472e-05 +76 chanx_left_in[1]:20 ropt_net_191:3 4.557177e-05 +77 chanx_left_in[1]:19 ropt_net_191:4 4.557177e-05 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:50 0.0002365667 +1 chanx_left_in[1]:32 chanx_left_in[1]:31 0.0045 +2 chanx_left_in[1]:31 chanx_left_in[1]:30 0.00178125 +3 chanx_left_in[1]:29 chanx_left_in[1]:28 0.001191964 +4 chanx_left_in[1]:30 chanx_left_in[1]:29 0.0045 +5 chanx_left_in[1]:30 chanx_left_in[1]:14 0.002691964 +6 chanx_left_in[1]:23 chanx_left_in[1]:22 0.0045 +7 chanx_left_in[1]:22 chanx_left_in[1]:21 0.02845536 +8 chanx_left_in[1]:20 chanx_left_in[1]:19 0.001569197 +9 chanx_left_in[1]:21 chanx_left_in[1]:20 0.0045 +10 chanx_left_in[1]:19 BUFT_RR_59:A 0.152 +11 chanx_left_in[1]:10 mux_bottom_ipin_11\/mux_l1_in_0_:A1 0.152 +12 chanx_left_in[1]:18 mux_bottom_ipin_13\/mux_l1_in_0_:A1 0.152 +13 chanx_left_in[1]:36 chanx_left_in[1]:35 0.0003035715 +14 chanx_left_in[1]:36 chanx_left_in[1]:33 0.002053572 +15 chanx_left_in[1]:37 chanx_left_in[1]:36 0.0045 +16 chanx_left_in[1]:39 chanx_left_in[1]:38 0.0045 +17 chanx_left_in[1]:38 chanx_left_in[1]:37 0.001133929 +18 chanx_left_in[1]:13 mux_bottom_ipin_5\/mux_l1_in_0_:A1 0.152 +19 chanx_left_in[1]:14 chanx_left_in[1]:13 0.0045 +20 chanx_left_in[1]:11 mux_bottom_ipin_7\/mux_l1_in_0_:A1 0.152 +21 chanx_left_in[1]:17 mux_bottom_ipin_15\/mux_l1_in_0_:A1 0.152 +22 chanx_left_in[1]:42 mux_bottom_ipin_9\/mux_l1_in_0_:A1 0.152 +23 chanx_left_in[1]:15 mux_bottom_ipin_1\/mux_l1_in_0_:A1 0.152 +24 chanx_left_in[1]:34 mux_bottom_ipin_3\/mux_l1_in_0_:A1 0.152 +25 chanx_left_in[1]:43 chanx_left_in[1]:42 0.0008727679 +26 chanx_left_in[1]:43 chanx_left_in[1]:41 0.0002767857 +27 chanx_left_in[1]:44 chanx_left_in[1]:43 0.0045 +28 chanx_left_in[1]:45 chanx_left_in[1]:44 0.0008191965 +29 chanx_left_in[1]:46 chanx_left_in[1]:45 0.00341 +30 chanx_left_in[1]:47 chanx_left_in[1]:46 0.003454891 +31 chanx_left_in[1]:48 chanx_left_in[1]:47 0.00341 +32 chanx_left_in[1]:50 chanx_left_in[1]:49 0.00341 +33 chanx_left_in[1]:49 chanx_left_in[1]:48 0.00031725 +34 chanx_left_in[1]:41 chanx_left_in[1]:40 0.003696429 +35 chanx_left_in[1]:40 chanx_left_in[1]:39 0.007352679 +36 chanx_left_in[1]:40 chanx_left_in[1]:10 0.0003035715 +37 chanx_left_in[1]:35 chanx_left_in[1]:34 0.0007879465 +38 chanx_left_in[1]:33 chanx_left_in[1]:32 0.01392411 +39 chanx_left_in[1]:33 chanx_left_in[1]:12 0.0003035715 +40 chanx_left_in[1]:12 chanx_left_in[1]:11 0.0002924107 +41 chanx_left_in[1]:28 chanx_left_in[1]:27 0.000607143 +42 chanx_left_in[1]:27 chanx_left_in[1]:26 0.009035715 +43 chanx_left_in[1]:26 chanx_left_in[1]:25 0.005339286 +44 chanx_left_in[1]:26 chanx_left_in[1]:16 0.0003035715 +45 chanx_left_in[1]:25 chanx_left_in[1]:24 0.01519643 +46 chanx_left_in[1]:25 chanx_left_in[1]:17 0.0003035715 +47 chanx_left_in[1]:24 chanx_left_in[1]:23 0.006120536 +48 chanx_left_in[1]:24 chanx_left_in[1]:18 0.0003035715 +49 chanx_left_in[1]:16 chanx_left_in[1]:15 0.0008727679 + +*END + +*D_NET chanx_left_in[16] 0.01442795 //LENGTH 104.552 LUMPCC 0.004787183 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 13.600 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 66.530 17.000 +*I mux_bottom_ipin_12\/mux_l2_in_2_:A0 I *L 0.001631 *C 79.295 15.640 +*I BUFT_P_97:A I *L 0.001767 *C 88.780 6.800 +*N chanx_left_in[16]:4 *C 88.780 6.800 +*N chanx_left_in[16]:5 *C 88.780 6.460 +*N chanx_left_in[16]:6 *C 87.445 6.460 +*N chanx_left_in[16]:7 *C 87.400 6.505 +*N chanx_left_in[16]:8 *C 87.400 15.595 +*N chanx_left_in[16]:9 *C 87.355 15.640 +*N chanx_left_in[16]:10 *C 79.333 15.640 +*N chanx_left_in[16]:11 *C 79.120 15.640 +*N chanx_left_in[16]:12 *C 79.120 15.685 +*N chanx_left_in[16]:13 *C 79.120 16.955 +*N chanx_left_in[16]:14 *C 79.075 17.000 +*N chanx_left_in[16]:15 *C 66.530 17.000 +*N chanx_left_in[16]:16 *C 64.445 17.000 +*N chanx_left_in[16]:17 *C 64.400 16.955 +*N chanx_left_in[16]:18 *C 64.400 14.338 +*N chanx_left_in[16]:19 *C 64.392 14.280 +*N chanx_left_in[16]:20 *C 14.720 14.280 +*N chanx_left_in[16]:21 *C 14.720 13.600 + +*CAP +0 chanx_left_in[16] 0.0007918512 +1 mux_bottom_ipin_0\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_12\/mux_l2_in_2_:A0 1e-06 +3 BUFT_P_97:A 1e-06 +4 chanx_left_in[16]:4 6.190941e-05 +5 chanx_left_in[16]:5 0.0001312757 +6 chanx_left_in[16]:6 0.0001011995 +7 chanx_left_in[16]:7 0.0004836897 +8 chanx_left_in[16]:8 0.0004836897 +9 chanx_left_in[16]:9 0.0004697757 +10 chanx_left_in[16]:10 0.0004979925 +11 chanx_left_in[16]:11 5.870507e-05 +12 chanx_left_in[16]:12 6.36677e-05 +13 chanx_left_in[16]:13 6.36677e-05 +14 chanx_left_in[16]:14 0.0007453621 +15 chanx_left_in[16]:15 0.0008665277 +16 chanx_left_in[16]:16 9.303247e-05 +17 chanx_left_in[16]:17 0.000169465 +18 chanx_left_in[16]:18 0.000169465 +19 chanx_left_in[16]:19 0.001742409 +20 chanx_left_in[16]:20 0.001797319 +21 chanx_left_in[16]:21 0.0008467606 +22 chanx_left_in[16] chanx_left_in[8] 7.06647e-06 +23 chanx_left_in[16]:19 chanx_left_in[8]:16 0.0002586083 +24 chanx_left_in[16]:12 chanx_left_in[8]:10 1.048949e-06 +25 chanx_left_in[16]:12 chanx_left_in[8]:15 4.238441e-05 +26 chanx_left_in[16]:14 chanx_left_in[8]:12 1.414216e-05 +27 chanx_left_in[16]:13 chanx_left_in[8]:11 1.048949e-06 +28 chanx_left_in[16]:13 chanx_left_in[8]:14 4.238441e-05 +29 chanx_left_in[16]:15 chanx_left_in[8]:13 1.414216e-05 +30 chanx_left_in[16]:21 chanx_left_in[8]:34 7.06647e-06 +31 chanx_left_in[16]:20 chanx_left_in[8]:17 0.0002586083 +32 chanx_left_in[16]:16 chanx_right_in[6]:32 8.410343e-05 +33 chanx_left_in[16]:14 chanx_right_in[6]:5 2.887031e-05 +34 chanx_left_in[16]:14 chanx_right_in[6]:33 0.0001593348 +35 chanx_left_in[16]:15 chanx_right_in[6]:33 0.0001129737 +36 chanx_left_in[16]:15 chanx_right_in[6]:32 0.0001593348 +37 chanx_left_in[16] chanx_right_in[8]:12 2.681003e-07 +38 chanx_left_in[16] chanx_right_in[8]:17 7.681189e-07 +39 chanx_left_in[16]:19 chanx_right_in[8]:18 0.0002768301 +40 chanx_left_in[16]:21 chanx_right_in[8]:13 2.681003e-07 +41 chanx_left_in[16]:21 chanx_right_in[8]:18 7.681189e-07 +42 chanx_left_in[16]:20 chanx_right_in[8]:17 0.0002768301 +43 chanx_left_in[16]:19 chanx_right_in[12]:27 0.0007237672 +44 chanx_left_in[16]:10 chanx_right_in[12]:32 7.40028e-05 +45 chanx_left_in[16]:9 chanx_right_in[12]:33 7.40028e-05 +46 chanx_left_in[16]:21 chanx_right_in[12]:25 1.600115e-05 +47 chanx_left_in[16]:20 chanx_right_in[12]:24 1.600115e-05 +48 chanx_left_in[16]:20 chanx_right_in[12]:26 0.0007237672 +49 chanx_left_in[16] prog_clk[0]:378 6.34125e-06 +50 chanx_left_in[16] prog_clk[0]:379 1.558809e-06 +51 chanx_left_in[16]:19 prog_clk[0]:313 2.04679e-06 +52 chanx_left_in[16]:19 prog_clk[0]:156 0.0002680539 +53 chanx_left_in[16]:19 prog_clk[0]:309 0.0002898598 +54 chanx_left_in[16]:19 prog_clk[0]:144 2.434743e-06 +55 chanx_left_in[16]:21 prog_clk[0]:313 6.34125e-06 +56 chanx_left_in[16]:21 prog_clk[0]:378 1.558809e-06 +57 chanx_left_in[16]:20 prog_clk[0]:313 2.434743e-06 +58 chanx_left_in[16]:20 prog_clk[0]:310 0.0002898598 +59 chanx_left_in[16]:20 prog_clk[0]:309 0.0002680539 +60 chanx_left_in[16]:20 prog_clk[0]:378 2.04679e-06 +61 chanx_left_in[16] ropt_net_129:5 0.0001360996 +62 chanx_left_in[16]:21 ropt_net_129:6 0.0001360996 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:21 0.002113433 +1 chanx_left_in[16]:16 chanx_left_in[16]:15 0.001861607 +2 chanx_left_in[16]:17 chanx_left_in[16]:16 0.0045 +3 chanx_left_in[16]:18 chanx_left_in[16]:17 0.002337054 +4 chanx_left_in[16]:19 chanx_left_in[16]:18 0.00341 +5 chanx_left_in[16]:11 chanx_left_in[16]:10 0.0001154891 +6 chanx_left_in[16]:12 chanx_left_in[16]:11 0.0045 +7 chanx_left_in[16]:14 chanx_left_in[16]:13 0.0045 +8 chanx_left_in[16]:13 chanx_left_in[16]:12 0.001133929 +9 chanx_left_in[16]:10 mux_bottom_ipin_12\/mux_l2_in_2_:A0 0.152 +10 chanx_left_in[16]:10 chanx_left_in[16]:9 0.007162946 +11 chanx_left_in[16]:15 mux_bottom_ipin_0\/mux_l2_in_2_:A0 0.152 +12 chanx_left_in[16]:15 chanx_left_in[16]:14 0.01120089 +13 chanx_left_in[16]:9 chanx_left_in[16]:8 0.0045 +14 chanx_left_in[16]:8 chanx_left_in[16]:7 0.008116071 +15 chanx_left_in[16]:6 chanx_left_in[16]:5 0.001191964 +16 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0045 +17 chanx_left_in[16]:4 BUFT_P_97:A 0.152 +18 chanx_left_in[16]:5 chanx_left_in[16]:4 0.0003035715 +19 chanx_left_in[16]:21 chanx_left_in[16]:20 0.0001065333 +20 chanx_left_in[16]:20 chanx_left_in[16]:19 0.007782024 + +*END + +*D_NET chanx_left_in[18] 0.02471549 //LENGTH 162.790 LUMPCC 0.005646174 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 25.160 +*I mux_bottom_ipin_6\/mux_l2_in_2_:A0 I *L 0.001631 *C 95.510 42.840 +*I mux_bottom_ipin_14\/mux_l2_in_2_:A0 I *L 0.001631 *C 90.910 44.540 +*I FTB_19__18:A I *L 0.001767 *C 97.980 69.360 +*I mux_bottom_ipin_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 14.090 37.400 +*N chanx_left_in[18]:5 *C 14.053 37.400 +*N chanx_left_in[18]:6 *C 13.385 37.400 +*N chanx_left_in[18]:7 *C 13.340 37.355 +*N chanx_left_in[18]:8 *C 97.943 69.360 +*N chanx_left_in[18]:9 *C 96.645 69.360 +*N chanx_left_in[18]:10 *C 96.600 69.315 +*N chanx_left_in[18]:11 *C 96.600 67.377 +*N chanx_left_in[18]:12 *C 96.593 67.320 +*N chanx_left_in[18]:13 *C 91.100 67.320 +*N chanx_left_in[18]:14 *C 91.080 67.312 +*N chanx_left_in[18]:15 *C 90.680 46.240 +*N chanx_left_in[18]:16 *C 90.910 44.540 +*N chanx_left_in[18]:17 *C 91.080 44.540 +*N chanx_left_in[18]:18 *C 91.080 44.585 +*N chanx_left_in[18]:19 *C 91.080 46.183 +*N chanx_left_in[18]:20 *C 91.080 46.240 +*N chanx_left_in[18]:21 *C 91.080 46.240 +*N chanx_left_in[18]:22 *C 90.370 42.840 +*N chanx_left_in[18]:23 *C 95.473 42.840 +*N chanx_left_in[18]:24 *C 91.125 42.840 +*N chanx_left_in[18]:25 *C 91.080 42.840 +*N chanx_left_in[18]:26 *C 91.078 42.840 +*N chanx_left_in[18]:27 *C 91.080 42.840 +*N chanx_left_in[18]:28 *C 91.080 31.968 +*N chanx_left_in[18]:29 *C 91.060 31.960 +*N chanx_left_in[18]:30 *C 57.968 31.960 +*N chanx_left_in[18]:31 *C 57.960 31.960 +*N chanx_left_in[18]:32 *C 57.915 31.960 +*N chanx_left_in[18]:33 *C 51.105 31.960 +*N chanx_left_in[18]:34 *C 51.060 31.915 +*N chanx_left_in[18]:35 *C 51.060 29.298 +*N chanx_left_in[18]:36 *C 51.053 29.240 +*N chanx_left_in[18]:37 *C 13.348 29.240 +*N chanx_left_in[18]:38 *C 13.340 29.240 +*N chanx_left_in[18]:39 *C 13.340 25.898 +*N chanx_left_in[18]:40 *C 13.333 25.840 +*N chanx_left_in[18]:41 *C 8.280 25.840 +*N chanx_left_in[18]:42 *C 8.280 25.160 + +*CAP +0 chanx_left_in[18] 0.0005392566 +1 mux_bottom_ipin_6\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_2_:A0 1e-06 +3 FTB_19__18:A 1e-06 +4 mux_bottom_ipin_8\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[18]:5 6.974987e-05 +6 chanx_left_in[18]:6 6.974987e-05 +7 chanx_left_in[18]:7 0.0005204965 +8 chanx_left_in[18]:8 0.0001175789 +9 chanx_left_in[18]:9 0.0001175789 +10 chanx_left_in[18]:10 0.0001250592 +11 chanx_left_in[18]:11 0.0001250592 +12 chanx_left_in[18]:12 0.0003737751 +13 chanx_left_in[18]:13 0.0003737751 +14 chanx_left_in[18]:14 0.001395039 +15 chanx_left_in[18]:15 9.970277e-05 +16 chanx_left_in[18]:16 5.889658e-05 +17 chanx_left_in[18]:17 5.806302e-05 +18 chanx_left_in[18]:18 0.000123946 +19 chanx_left_in[18]:19 0.000123946 +20 chanx_left_in[18]:20 9.970277e-05 +21 chanx_left_in[18]:21 0.001611746 +22 chanx_left_in[18]:22 0.0001271068 +23 chanx_left_in[18]:23 0.0003636024 +24 chanx_left_in[18]:24 0.0003636024 +25 chanx_left_in[18]:25 3.85492e-05 +26 chanx_left_in[18]:26 0.0001271068 +27 chanx_left_in[18]:27 0.0009327836 +28 chanx_left_in[18]:28 0.0007160763 +29 chanx_left_in[18]:29 0.001277875 +30 chanx_left_in[18]:30 0.001277875 +31 chanx_left_in[18]:31 3.768162e-05 +32 chanx_left_in[18]:32 0.0004658532 +33 chanx_left_in[18]:33 0.0004658532 +34 chanx_left_in[18]:34 0.0001641246 +35 chanx_left_in[18]:35 0.0001641246 +36 chanx_left_in[18]:36 0.001987402 +37 chanx_left_in[18]:37 0.001987402 +38 chanx_left_in[18]:38 0.0007611715 +39 chanx_left_in[18]:39 0.0002009885 +40 chanx_left_in[18]:40 0.0004820503 +41 chanx_left_in[18]:41 0.000531883 +42 chanx_left_in[18]:42 0.0005890894 +43 chanx_left_in[18]:30 chanx_left_in[10]:13 0.0005639209 +44 chanx_left_in[18]:29 chanx_left_in[10]:12 0.0005639209 +45 chanx_left_in[18] chanx_left_in[12]:28 1.302461e-06 +46 chanx_left_in[18]:38 chanx_left_in[12]:26 1.151411e-05 +47 chanx_left_in[18]:37 chanx_left_in[12]:27 0.0004195036 +48 chanx_left_in[18]:37 chanx_left_in[12]:28 1.726426e-05 +49 chanx_left_in[18]:36 chanx_left_in[12]:22 0.0004195036 +50 chanx_left_in[18]:36 chanx_left_in[12]:27 1.726426e-05 +51 chanx_left_in[18]:30 chanx_left_in[12]:9 8.535248e-06 +52 chanx_left_in[18]:30 chanx_left_in[12]:12 1.451744e-05 +53 chanx_left_in[18]:30 chanx_left_in[12]:22 0.0001744244 +54 chanx_left_in[18]:30 chanx_left_in[12]:27 0.000130053 +55 chanx_left_in[18]:29 chanx_left_in[12]:8 8.535248e-06 +56 chanx_left_in[18]:29 chanx_left_in[12]:11 1.451744e-05 +57 chanx_left_in[18]:29 chanx_left_in[12]:21 0.0001744244 +58 chanx_left_in[18]:29 chanx_left_in[12]:22 0.000130053 +59 chanx_left_in[18]:7 chanx_left_in[12]:25 1.151411e-05 +60 chanx_left_in[18]:40 chanx_left_in[12]:27 7.46178e-07 +61 chanx_left_in[18]:42 chanx_left_in[12]:27 1.302461e-06 +62 chanx_left_in[18]:42 chanx_left_in[12]:30 6.903501e-06 +63 chanx_left_in[18]:41 chanx_left_in[12]:28 7.46178e-07 +64 chanx_left_in[18]:41 chanx_left_in[12]:29 6.903501e-06 +65 chanx_left_in[18]:30 chanx_right_in[5]:28 0.0006139305 +66 chanx_left_in[18]:29 chanx_right_in[5]:29 0.0006139305 +67 chanx_left_in[18]:37 prog_clk[0]:299 0.0003094592 +68 chanx_left_in[18]:37 prog_clk[0]:298 9.844783e-05 +69 chanx_left_in[18]:37 prog_clk[0]:287 0.000436687 +70 chanx_left_in[18]:35 prog_clk[0]:273 1.087196e-05 +71 chanx_left_in[18]:36 prog_clk[0]:282 0.000436687 +72 chanx_left_in[18]:36 prog_clk[0]:298 0.0003094592 +73 chanx_left_in[18]:36 prog_clk[0]:287 9.844783e-05 +74 chanx_left_in[18]:34 prog_clk[0]:272 1.087196e-05 +75 chanx_left_in[18]:30 prog_clk[0]:84 5.005284e-06 +76 chanx_left_in[18]:29 prog_clk[0]:83 5.005284e-06 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:42 0.0011045 +1 chanx_left_in[18]:38 chanx_left_in[18]:37 0.00341 +2 chanx_left_in[18]:38 chanx_left_in[18]:7 0.007245536 +3 chanx_left_in[18]:37 chanx_left_in[18]:36 0.005907116 +4 chanx_left_in[18]:35 chanx_left_in[18]:34 0.002337054 +5 chanx_left_in[18]:36 chanx_left_in[18]:35 0.00341 +6 chanx_left_in[18]:33 chanx_left_in[18]:32 0.006080357 +7 chanx_left_in[18]:34 chanx_left_in[18]:33 0.0045 +8 chanx_left_in[18]:32 chanx_left_in[18]:31 0.0045 +9 chanx_left_in[18]:31 chanx_left_in[18]:30 0.00341 +10 chanx_left_in[18]:30 chanx_left_in[18]:29 0.005184491 +11 chanx_left_in[18]:29 chanx_left_in[18]:28 0.00341 +12 chanx_left_in[18]:28 chanx_left_in[18]:27 0.001703358 +13 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0005959821 +14 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0045 +15 chanx_left_in[18]:5 mux_bottom_ipin_8\/mux_l2_in_2_:A0 0.152 +16 chanx_left_in[18]:20 chanx_left_in[18]:19 0.00341 +17 chanx_left_in[18]:20 chanx_left_in[18]:15 5.69697e-05 +18 chanx_left_in[18]:21 chanx_left_in[18]:20 0.00341 +19 chanx_left_in[18]:21 chanx_left_in[18]:14 0.003301358 +20 chanx_left_in[18]:19 chanx_left_in[18]:18 0.001426339 +21 chanx_left_in[18]:17 chanx_left_in[18]:16 9.239131e-05 +22 chanx_left_in[18]:18 chanx_left_in[18]:17 0.0045 +23 chanx_left_in[18]:16 mux_bottom_ipin_14\/mux_l2_in_2_:A0 0.152 +24 chanx_left_in[18]:13 chanx_left_in[18]:12 0.0008604917 +25 chanx_left_in[18]:14 chanx_left_in[18]:13 0.00341 +26 chanx_left_in[18]:11 chanx_left_in[18]:10 0.001729911 +27 chanx_left_in[18]:12 chanx_left_in[18]:11 0.00341 +28 chanx_left_in[18]:9 chanx_left_in[18]:8 0.001158482 +29 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0045 +30 chanx_left_in[18]:8 FTB_19__18:A 0.152 +31 chanx_left_in[18]:26 chanx_left_in[18]:25 0.00341 +32 chanx_left_in[18]:26 chanx_left_in[18]:22 0.0001039141 +33 chanx_left_in[18]:27 chanx_left_in[18]:26 0.00341 +34 chanx_left_in[18]:27 chanx_left_in[18]:21 0.0005326666 +35 chanx_left_in[18]:25 chanx_left_in[18]:24 0.0045 +36 chanx_left_in[18]:24 chanx_left_in[18]:23 0.003881697 +37 chanx_left_in[18]:23 mux_bottom_ipin_6\/mux_l2_in_2_:A0 0.152 +38 chanx_left_in[18]:39 chanx_left_in[18]:38 0.002984375 +39 chanx_left_in[18]:40 chanx_left_in[18]:39 0.00341 +40 chanx_left_in[18]:42 chanx_left_in[18]:41 0.0001065333 +41 chanx_left_in[18]:41 chanx_left_in[18]:40 0.0007915583 + +*END + +*D_NET chanx_right_in[0] 0.02000532 //LENGTH 138.130 LUMPCC 0.005201663 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 103.650 34.000 +*I mux_bottom_ipin_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 94.590 33.660 +*I mux_bottom_ipin_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.090 26.520 +*I mux_bottom_ipin_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.855 27.880 +*I mux_bottom_ipin_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 47.095 27.880 +*I mux_bottom_ipin_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 43.530 26.180 +*I mux_bottom_ipin_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 18.115 26.180 +*I FTB_21__20:A I *L 0.001767 *C 11.500 6.800 +*I mux_bottom_ipin_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 9.950 28.220 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 86.770 28.220 +*N chanx_right_in[0]:10 *C 86.733 28.220 +*N chanx_right_in[0]:11 *C 86.020 28.220 +*N chanx_right_in[0]:12 *C 9.950 28.220 +*N chanx_right_in[0]:13 *C 11.463 6.800 +*N chanx_right_in[0]:14 *C 10.165 6.800 +*N chanx_right_in[0]:15 *C 10.120 6.845 +*N chanx_right_in[0]:16 *C 10.120 28.175 +*N chanx_right_in[0]:17 *C 10.120 28.220 +*N chanx_right_in[0]:18 *C 10.120 28.560 +*N chanx_right_in[0]:19 *C 16.055 28.560 +*N chanx_right_in[0]:20 *C 16.100 28.515 +*N chanx_right_in[0]:21 *C 18.078 26.180 +*N chanx_right_in[0]:22 *C 16.145 26.180 +*N chanx_right_in[0]:23 *C 16.100 26.225 +*N chanx_right_in[0]:24 *C 16.100 25.840 +*N chanx_right_in[0]:25 *C 16.108 25.840 +*N chanx_right_in[0]:26 *C 35.413 25.840 +*N chanx_right_in[0]:27 *C 35.420 25.840 +*N chanx_right_in[0]:28 *C 35.465 25.840 +*N chanx_right_in[0]:29 *C 43.530 25.840 +*N chanx_right_in[0]:30 *C 43.530 26.158 +*N chanx_right_in[0]:31 *C 44.575 26.180 +*N chanx_right_in[0]:32 *C 44.620 26.225 +*N chanx_right_in[0]:33 *C 44.620 27.835 +*N chanx_right_in[0]:34 *C 44.665 27.880 +*N chanx_right_in[0]:35 *C 47.095 27.880 +*N chanx_right_in[0]:36 *C 72.855 27.880 +*N chanx_right_in[0]:37 *C 83.090 26.520 +*N chanx_right_in[0]:38 *C 83.260 26.520 +*N chanx_right_in[0]:39 *C 83.260 26.565 +*N chanx_right_in[0]:40 *C 83.260 27.835 +*N chanx_right_in[0]:41 *C 83.260 27.880 +*N chanx_right_in[0]:42 *C 86.020 27.880 +*N chanx_right_in[0]:43 *C 87.815 27.880 +*N chanx_right_in[0]:44 *C 87.860 27.925 +*N chanx_right_in[0]:45 *C 87.860 30.543 +*N chanx_right_in[0]:46 *C 87.868 30.600 +*N chanx_right_in[0]:47 *C 94.752 30.600 +*N chanx_right_in[0]:48 *C 94.760 30.658 +*N chanx_right_in[0]:49 *C 94.590 33.660 +*N chanx_right_in[0]:50 *C 94.760 33.660 +*N chanx_right_in[0]:51 *C 94.760 33.615 +*N chanx_right_in[0]:52 *C 94.760 34.000 +*N chanx_right_in[0]:53 *C 94.767 34.000 + +*CAP +0 chanx_right_in[0] 0.0003565965 +1 mux_bottom_ipin_14\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_ipin_6\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_ipin_12\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_ipin_4\/mux_l1_in_0_:A0 1e-06 +5 mux_bottom_ipin_2\/mux_l1_in_0_:A0 1e-06 +6 mux_bottom_ipin_8\/mux_l1_in_0_:A0 1e-06 +7 FTB_21__20:A 1e-06 +8 mux_bottom_ipin_10\/mux_l1_in_0_:A0 1e-06 +9 mux_bottom_ipin_0\/mux_l1_in_0_:A0 1e-06 +10 chanx_right_in[0]:10 7.1735e-05 +11 chanx_right_in[0]:11 9.707514e-05 +12 chanx_right_in[0]:12 5.336835e-05 +13 chanx_right_in[0]:13 0.0001240939 +14 chanx_right_in[0]:14 0.0001240939 +15 chanx_right_in[0]:15 0.001248942 +16 chanx_right_in[0]:16 0.001248942 +17 chanx_right_in[0]:17 7.863108e-05 +18 chanx_right_in[0]:18 0.0003030837 +19 chanx_right_in[0]:19 0.0002822549 +20 chanx_right_in[0]:20 0.0001533007 +21 chanx_right_in[0]:21 0.0001733291 +22 chanx_right_in[0]:22 0.0001733291 +23 chanx_right_in[0]:23 0.0001737561 +24 chanx_right_in[0]:24 5.831685e-05 +25 chanx_right_in[0]:25 0.0008065701 +26 chanx_right_in[0]:26 0.0008065701 +27 chanx_right_in[0]:27 3.429066e-05 +28 chanx_right_in[0]:28 0.0003219528 +29 chanx_right_in[0]:29 0.0003488994 +30 chanx_right_in[0]:30 0.0001334278 +31 chanx_right_in[0]:31 0.0001064812 +32 chanx_right_in[0]:32 0.0001156341 +33 chanx_right_in[0]:33 0.0001156341 +34 chanx_right_in[0]:34 0.0001783837 +35 chanx_right_in[0]:35 0.001840081 +36 chanx_right_in[0]:36 0.002320688 +37 chanx_right_in[0]:37 4.965456e-05 +38 chanx_right_in[0]:38 5.4082e-05 +39 chanx_right_in[0]:39 5.928128e-05 +40 chanx_right_in[0]:40 5.928128e-05 +41 chanx_right_in[0]:41 0.0008604311 +42 chanx_right_in[0]:42 0.000293431 +43 chanx_right_in[0]:43 0.0001048661 +44 chanx_right_in[0]:44 0.0001467402 +45 chanx_right_in[0]:45 0.0001467402 +46 chanx_right_in[0]:46 0.0001664188 +47 chanx_right_in[0]:47 0.0001664188 +48 chanx_right_in[0]:48 0.0001537899 +49 chanx_right_in[0]:49 5.326629e-05 +50 chanx_right_in[0]:50 5.386088e-05 +51 chanx_right_in[0]:51 0.0001695973 +52 chanx_right_in[0]:52 5.074467e-05 +53 chanx_right_in[0]:53 0.0003565965 +54 chanx_right_in[0]:23 chanx_left_in[0]:51 3.229221e-06 +55 chanx_right_in[0]:23 chanx_left_in[0]:52 4.496469e-07 +56 chanx_right_in[0]:28 chanx_left_in[0]:42 2.220156e-05 +57 chanx_right_in[0]:28 chanx_left_in[0]:43 3.15242e-05 +58 chanx_right_in[0]:26 chanx_left_in[0]:46 0.0001274689 +59 chanx_right_in[0]:26 chanx_left_in[0]:51 5.289467e-06 +60 chanx_right_in[0]:24 chanx_left_in[0]:51 4.496469e-07 +61 chanx_right_in[0]:25 chanx_left_in[0]:47 0.0001274689 +62 chanx_right_in[0]:25 chanx_left_in[0]:50 5.289467e-06 +63 chanx_right_in[0]:31 chanx_left_in[0]:41 7.423559e-06 +64 chanx_right_in[0]:31 chanx_left_in[0]:42 6.434077e-07 +65 chanx_right_in[0]:19 chanx_left_in[0]:53 0.0001077824 +66 chanx_right_in[0]:20 chanx_left_in[0]:52 3.229221e-06 +67 chanx_right_in[0]:48 chanx_left_in[0]:23 3.519239e-05 +68 chanx_right_in[0]:47 chanx_left_in[0]:24 0.0001455499 +69 chanx_right_in[0]:45 chanx_left_in[0]:26 3.69616e-06 +70 chanx_right_in[0]:45 chanx_left_in[0]:28 1.396129e-05 +71 chanx_right_in[0]:46 chanx_left_in[0]:28 0.0001455499 +72 chanx_right_in[0]:44 chanx_left_in[0]:27 3.69616e-06 +73 chanx_right_in[0]:44 chanx_left_in[0]:29 1.396129e-05 +74 chanx_right_in[0]:30 chanx_left_in[0]:42 7.423559e-06 +75 chanx_right_in[0]:30 chanx_left_in[0]:43 6.434077e-07 +76 chanx_right_in[0]:12 chanx_left_in[0]:55 4.061938e-07 +77 chanx_right_in[0]:36 chanx_left_in[0]:11 5.026106e-06 +78 chanx_right_in[0]:36 chanx_left_in[0]:37 8.27483e-06 +79 chanx_right_in[0]:35 chanx_left_in[0]:10 5.026106e-06 +80 chanx_right_in[0]:35 chanx_left_in[0]:38 8.27483e-06 +81 chanx_right_in[0]:40 chanx_left_in[0]:32 4.284873e-05 +82 chanx_right_in[0]:39 chanx_left_in[0]:31 4.284873e-05 +83 chanx_right_in[0]:51 chanx_left_in[0]:22 3.913089e-05 +84 chanx_right_in[0]:17 chanx_left_in[0]:53 4.061938e-07 +85 chanx_right_in[0]:52 chanx_left_in[0]:23 3.938502e-06 +86 chanx_right_in[0]:18 chanx_left_in[0]:55 0.0001077824 +87 chanx_right_in[0]:29 chanx_left_in[0]:41 2.220156e-05 +88 chanx_right_in[0]:29 chanx_left_in[0]:42 3.15242e-05 +89 chanx_right_in[0]:28 chanx_left_in[2]:48 7.687404e-05 +90 chanx_right_in[0]:28 chanx_left_in[2]:50 6.318261e-05 +91 chanx_right_in[0]:26 chanx_left_in[2]:49 1.176057e-05 +92 chanx_right_in[0]:26 chanx_left_in[2]:53 0.0007777371 +93 chanx_right_in[0]:25 chanx_left_in[2]:50 1.176057e-05 +94 chanx_right_in[0]:25 chanx_left_in[2]:54 0.0007777371 +95 chanx_right_in[0]:45 chanx_left_in[2]:21 1.203226e-05 +96 chanx_right_in[0]:44 chanx_left_in[2]:20 1.203226e-05 +97 chanx_right_in[0]:15 chanx_left_in[2]:14 5.518851e-06 +98 chanx_right_in[0]:16 chanx_left_in[2]:55 5.518851e-06 +99 chanx_right_in[0]:29 chanx_left_in[2]:47 7.687404e-05 +100 chanx_right_in[0]:29 chanx_left_in[2]:49 6.318261e-05 +101 chanx_right_in[0] chanx_left_in[10]:12 1.111984e-07 +102 chanx_right_in[0]:47 chanx_left_in[10]:12 0.0004037808 +103 chanx_right_in[0]:46 chanx_left_in[10]:13 0.0004037808 +104 chanx_right_in[0]:36 chanx_left_in[10]:17 3.45021e-05 +105 chanx_right_in[0]:35 chanx_left_in[10]:18 3.45021e-05 +106 chanx_right_in[0]:53 chanx_left_in[10]:13 1.111984e-07 +107 chanx_right_in[0] chanx_right_in[5]:29 0.0003291215 +108 chanx_right_in[0]:53 chanx_right_in[5]:28 0.0003291215 +109 chanx_right_in[0]:36 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.719714e-05 +110 chanx_right_in[0]:41 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.719714e-05 +111 chanx_right_in[0]:41 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.617762e-05 +112 chanx_right_in[0]:42 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.617762e-05 +113 chanx_right_in[0]:36 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.701393e-05 +114 chanx_right_in[0]:35 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.701393e-05 +115 chanx_right_in[0]:28 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001063176 +116 chanx_right_in[0]:29 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001063176 +117 chanx_right_in[0] ropt_net_185:7 6.45984e-05 +118 chanx_right_in[0]:53 ropt_net_185:6 6.45984e-05 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:53 0.001391592 +1 chanx_right_in[0]:21 mux_bottom_ipin_8\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[0]:22 chanx_right_in[0]:21 0.001725447 +3 chanx_right_in[0]:23 chanx_right_in[0]:22 0.0045 +4 chanx_right_in[0]:23 chanx_right_in[0]:20 0.002044643 +5 chanx_right_in[0]:28 chanx_right_in[0]:27 0.0045 +6 chanx_right_in[0]:27 chanx_right_in[0]:26 0.00341 +7 chanx_right_in[0]:26 chanx_right_in[0]:25 0.00302445 +8 chanx_right_in[0]:24 chanx_right_in[0]:23 0.0001850961 +9 chanx_right_in[0]:25 chanx_right_in[0]:24 0.00341 +10 chanx_right_in[0]:31 chanx_right_in[0]:30 0.0009330358 +11 chanx_right_in[0]:32 chanx_right_in[0]:31 0.0045 +12 chanx_right_in[0]:34 chanx_right_in[0]:33 0.0045 +13 chanx_right_in[0]:33 chanx_right_in[0]:32 0.0014375 +14 chanx_right_in[0]:19 chanx_right_in[0]:18 0.005299107 +15 chanx_right_in[0]:20 chanx_right_in[0]:19 0.0045 +16 chanx_right_in[0]:48 chanx_right_in[0]:47 0.00341 +17 chanx_right_in[0]:47 chanx_right_in[0]:46 0.00107865 +18 chanx_right_in[0]:45 chanx_right_in[0]:44 0.002337054 +19 chanx_right_in[0]:46 chanx_right_in[0]:45 0.00341 +20 chanx_right_in[0]:43 chanx_right_in[0]:42 0.001602679 +21 chanx_right_in[0]:44 chanx_right_in[0]:43 0.0045 +22 chanx_right_in[0]:30 mux_bottom_ipin_2\/mux_l1_in_0_:A0 0.152 +23 chanx_right_in[0]:30 chanx_right_in[0]:29 0.0002834822 +24 chanx_right_in[0]:12 mux_bottom_ipin_10\/mux_l1_in_0_:A0 0.152 +25 chanx_right_in[0]:36 mux_bottom_ipin_12\/mux_l1_in_0_:A0 0.152 +26 chanx_right_in[0]:36 chanx_right_in[0]:35 0.023 +27 chanx_right_in[0]:35 mux_bottom_ipin_4\/mux_l1_in_0_:A0 0.152 +28 chanx_right_in[0]:35 chanx_right_in[0]:34 0.002169643 +29 chanx_right_in[0]:41 chanx_right_in[0]:40 0.0045 +30 chanx_right_in[0]:41 chanx_right_in[0]:36 0.009290179 +31 chanx_right_in[0]:40 chanx_right_in[0]:39 0.001133929 +32 chanx_right_in[0]:38 chanx_right_in[0]:37 9.239131e-05 +33 chanx_right_in[0]:39 chanx_right_in[0]:38 0.0045 +34 chanx_right_in[0]:37 mux_bottom_ipin_6\/mux_l1_in_0_:A0 0.152 +35 chanx_right_in[0]:50 chanx_right_in[0]:49 9.239132e-05 +36 chanx_right_in[0]:51 chanx_right_in[0]:50 0.0045 +37 chanx_right_in[0]:51 chanx_right_in[0]:48 0.002640625 +38 chanx_right_in[0]:49 mux_bottom_ipin_14\/mux_l1_in_0_:A0 0.152 +39 chanx_right_in[0]:13 FTB_21__20:A 0.152 +40 chanx_right_in[0]:14 chanx_right_in[0]:13 0.001158482 +41 chanx_right_in[0]:15 chanx_right_in[0]:14 0.0045 +42 chanx_right_in[0]:17 chanx_right_in[0]:16 0.0045 +43 chanx_right_in[0]:17 chanx_right_in[0]:12 9.239131e-05 +44 chanx_right_in[0]:16 chanx_right_in[0]:15 0.01904465 +45 chanx_right_in[0]:10 mux_bottom_ipin_0\/mux_l1_in_0_:A0 0.152 +46 chanx_right_in[0]:52 chanx_right_in[0]:51 0.0001850962 +47 chanx_right_in[0]:53 chanx_right_in[0]:52 0.00341 +48 chanx_right_in[0]:18 chanx_right_in[0]:17 0.0003035715 +49 chanx_right_in[0]:29 chanx_right_in[0]:28 0.007200893 +50 chanx_right_in[0]:42 chanx_right_in[0]:41 0.002464286 +51 chanx_right_in[0]:42 chanx_right_in[0]:11 0.0003035715 +52 chanx_right_in[0]:11 chanx_right_in[0]:10 0.0006361608 + +*END + +*D_NET chanx_right_in[11] 0.02157574 //LENGTH 174.175 LUMPCC 0.005715183 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 103.650 69.360 +*I mux_bottom_ipin_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 53.360 63.580 +*I ropt_mt_inst_735:A I *L 0.001767 *C 3.220 4.080 +*I mux_bottom_ipin_7\/mux_l2_in_2_:A1 I *L 0.00198 *C 36.340 58.140 +*I mux_bottom_ipin_15\/mux_l2_in_2_:A1 I *L 0.00198 *C 71.665 61.540 +*N chanx_right_in[11]:5 *C 71.665 61.540 +*N chanx_right_in[11]:6 *C 71.760 61.585 +*N chanx_right_in[11]:7 *C 36.340 58.140 +*N chanx_right_in[11]:8 *C 36.340 58.140 +*N chanx_right_in[11]:9 *C 3.258 4.080 +*N chanx_right_in[11]:10 *C 5.475 4.080 +*N chanx_right_in[11]:11 *C 5.520 4.125 +*N chanx_right_in[11]:12 *C 5.520 7.095 +*N chanx_right_in[11]:13 *C 5.565 7.140 +*N chanx_right_in[11]:14 *C 33.075 7.140 +*N chanx_right_in[11]:15 *C 33.120 7.140 +*N chanx_right_in[11]:16 *C 33.120 6.800 +*N chanx_right_in[11]:17 *C 33.128 6.800 +*N chanx_right_in[11]:18 *C 35.860 6.800 +*N chanx_right_in[11]:19 *C 35.880 6.808 +*N chanx_right_in[11]:20 *C 35.880 58.133 +*N chanx_right_in[11]:21 *C 35.900 58.140 +*N chanx_right_in[11]:22 *C 35.907 58.473 +*N chanx_right_in[11]:23 *C 36.335 58.473 +*N chanx_right_in[11]:24 *C 36.340 58.538 +*N chanx_right_in[11]:25 *C 36.340 63.863 +*N chanx_right_in[11]:26 *C 36.348 63.920 +*N chanx_right_in[11]:27 *C 53.360 63.565 +*N chanx_right_in[11]:28 *C 53.360 63.240 +*N chanx_right_in[11]:29 *C 53.360 63.285 +*N chanx_right_in[11]:30 *C 53.360 63.863 +*N chanx_right_in[11]:31 *C 53.360 63.920 +*N chanx_right_in[11]:32 *C 71.752 63.920 +*N chanx_right_in[11]:33 *C 71.760 63.920 +*N chanx_right_in[11]:34 *C 71.760 69.303 +*N chanx_right_in[11]:35 *C 71.767 69.360 + +*CAP +0 chanx_right_in[11] 0.00133682 +1 mux_bottom_ipin_1\/mux_l2_in_2_:A1 1e-06 +2 ropt_mt_inst_735:A 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_2_:A1 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_2_:A1 1e-06 +5 chanx_right_in[11]:5 2.870165e-05 +6 chanx_right_in[11]:6 0.0001005023 +7 chanx_right_in[11]:7 3.244529e-05 +8 chanx_right_in[11]:8 5.732468e-05 +9 chanx_right_in[11]:9 0.0001614301 +10 chanx_right_in[11]:10 0.0001614301 +11 chanx_right_in[11]:11 0.0001915465 +12 chanx_right_in[11]:12 0.0001915465 +13 chanx_right_in[11]:13 0.001497506 +14 chanx_right_in[11]:14 0.001497506 +15 chanx_right_in[11]:15 4.797329e-05 +16 chanx_right_in[11]:16 5.167624e-05 +17 chanx_right_in[11]:17 0.0001472196 +18 chanx_right_in[11]:18 0.0001472196 +19 chanx_right_in[11]:19 0.002440514 +20 chanx_right_in[11]:20 0.002440514 +21 chanx_right_in[11]:21 3.91452e-05 +22 chanx_right_in[11]:22 0.0001097112 +23 chanx_right_in[11]:23 7.056603e-05 +24 chanx_right_in[11]:24 0.0003524119 +25 chanx_right_in[11]:25 0.0003289597 +26 chanx_right_in[11]:26 0.0004014845 +27 chanx_right_in[11]:27 3.482991e-05 +28 chanx_right_in[11]:28 6.679606e-05 +29 chanx_right_in[11]:29 6.372771e-05 +30 chanx_right_in[11]:30 6.372771e-05 +31 chanx_right_in[11]:31 0.001123944 +32 chanx_right_in[11]:32 0.0007224597 +33 chanx_right_in[11]:33 0.0003723571 +34 chanx_right_in[11]:34 0.000237744 +35 chanx_right_in[11]:35 0.00133682 +36 chanx_right_in[11] chanx_left_in[12]:17 0.0002082478 +37 chanx_right_in[11]:33 chanx_left_in[12]:19 6.56921e-05 +38 chanx_right_in[11]:33 chanx_left_in[12]:20 9.654907e-05 +39 chanx_right_in[11]:6 chanx_left_in[12]:20 6.56921e-05 +40 chanx_right_in[11]:34 chanx_left_in[12]:19 9.654907e-05 +41 chanx_right_in[11]:35 chanx_left_in[12]:18 0.0002082478 +42 chanx_right_in[11] chanx_left_in[17]:15 2.851347e-05 +43 chanx_right_in[11]:26 chanx_left_in[17]:25 0.0007163155 +44 chanx_right_in[11]:32 chanx_left_in[17]:15 0.000191093 +45 chanx_right_in[11]:32 chanx_left_in[17]:19 7.421005e-06 +46 chanx_right_in[11]:31 chanx_left_in[17]:16 0.000191093 +47 chanx_right_in[11]:31 chanx_left_in[17]:20 7.421005e-06 +48 chanx_right_in[11]:31 chanx_left_in[17]:24 0.0007163155 +49 chanx_right_in[11]:35 chanx_left_in[17]:16 2.851347e-05 +50 chanx_right_in[11] chanx_right_in[13] 1.58857e-05 +51 chanx_right_in[11]:26 chanx_right_in[13]:17 5.006127e-05 +52 chanx_right_in[11]:23 chanx_right_in[13]:18 5.825397e-06 +53 chanx_right_in[11]:14 chanx_right_in[13]:9 9.931695e-05 +54 chanx_right_in[11]:13 chanx_right_in[13]:8 9.931695e-05 +55 chanx_right_in[11]:32 chanx_right_in[13]:18 0.0001751904 +56 chanx_right_in[11]:31 chanx_right_in[13]:17 0.0001751904 +57 chanx_right_in[11]:31 chanx_right_in[13]:18 5.006127e-05 +58 chanx_right_in[11]:35 chanx_right_in[13]:26 1.58857e-05 +59 chanx_right_in[11]:22 chanx_right_in[13]:17 5.825397e-06 +60 chanx_right_in[11]:20 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 0.000283568 +61 chanx_right_in[11]:19 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 0.000283568 +62 chanx_right_in[11]:20 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003499791 +63 chanx_right_in[11]:19 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0003499791 +64 chanx_right_in[11] chanx_right_out[12] 0.0002538614 +65 chanx_right_in[11]:35 chanx_right_out[12]:2 0.0002538614 +66 chanx_right_in[11]:26 mem_bottom_ipin_15/net_net_75:6 0.0002683882 +67 chanx_right_in[11]:32 mem_bottom_ipin_15/net_net_75:7 4.168317e-05 +68 chanx_right_in[11]:31 mem_bottom_ipin_15/net_net_75:7 0.0002683882 +69 chanx_right_in[11]:31 mem_bottom_ipin_15/net_net_75:6 4.168317e-05 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:35 0.004994925 +1 chanx_right_in[11]:25 chanx_right_in[11]:24 0.004754465 +2 chanx_right_in[11]:26 chanx_right_in[11]:25 0.00341 +3 chanx_right_in[11]:24 chanx_right_in[11]:23 0.00341 +4 chanx_right_in[11]:24 chanx_right_in[11]:8 0.0001911058 +5 chanx_right_in[11]:23 chanx_right_in[11]:22 6.378572e-05 +6 chanx_right_in[11]:21 chanx_right_in[11]:20 0.00341 +7 chanx_right_in[11]:20 chanx_right_in[11]:19 0.008040916 +8 chanx_right_in[11]:18 chanx_right_in[11]:17 0.0004280917 +9 chanx_right_in[11]:19 chanx_right_in[11]:18 0.00341 +10 chanx_right_in[11]:16 chanx_right_in[11]:15 0.0001634615 +11 chanx_right_in[11]:17 chanx_right_in[11]:16 0.00341 +12 chanx_right_in[11]:14 chanx_right_in[11]:13 0.0245625 +13 chanx_right_in[11]:15 chanx_right_in[11]:14 0.0045 +14 chanx_right_in[11]:13 chanx_right_in[11]:12 0.0045 +15 chanx_right_in[11]:12 chanx_right_in[11]:11 0.002651786 +16 chanx_right_in[11]:10 chanx_right_in[11]:9 0.001979911 +17 chanx_right_in[11]:11 chanx_right_in[11]:10 0.0045 +18 chanx_right_in[11]:9 ropt_mt_inst_735:A 0.152 +19 chanx_right_in[11]:33 chanx_right_in[11]:32 0.00341 +20 chanx_right_in[11]:33 chanx_right_in[11]:6 0.002084821 +21 chanx_right_in[11]:32 chanx_right_in[11]:31 0.002881492 +22 chanx_right_in[11]:7 mux_bottom_ipin_7\/mux_l2_in_2_:A1 0.152 +23 chanx_right_in[11]:8 chanx_right_in[11]:7 0.0045 +24 chanx_right_in[11]:5 mux_bottom_ipin_15\/mux_l2_in_2_:A1 0.152 +25 chanx_right_in[11]:6 chanx_right_in[11]:5 0.0045 +26 chanx_right_in[11]:30 chanx_right_in[11]:29 0.000515625 +27 chanx_right_in[11]:31 chanx_right_in[11]:30 0.00341 +28 chanx_right_in[11]:31 chanx_right_in[11]:26 0.002665292 +29 chanx_right_in[11]:28 chanx_right_in[11]:27 0.0001766305 +30 chanx_right_in[11]:29 chanx_right_in[11]:28 0.0045 +31 chanx_right_in[11]:27 mux_bottom_ipin_1\/mux_l2_in_2_:A1 0.152 +32 chanx_right_in[11]:34 chanx_right_in[11]:33 0.004805804 +33 chanx_right_in[11]:35 chanx_right_in[11]:34 0.00341 +34 chanx_right_in[11]:22 chanx_right_in[11]:21 4.596323e-05 + +*END + +*D_NET ccff_head[0] 0.002894006 //LENGTH 23.310 LUMPCC 0.0002722062 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 103.650 37.400 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 90.335 28.220 +*N ccff_head[0]:2 *C 90.373 28.220 +*N ccff_head[0]:3 *C 97.475 28.220 +*N ccff_head[0]:4 *C 97.520 28.265 +*N ccff_head[0]:5 *C 97.520 37.343 +*N ccff_head[0]:6 *C 97.528 37.400 + +*CAP +0 ccff_head[0] 0.0003110788 +1 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 0.0004746271 +3 ccff_head[0]:3 0.0004746271 +4 ccff_head[0]:4 0.0005246937 +5 ccff_head[0]:5 0.0005246937 +6 ccff_head[0]:6 0.0003110788 +7 ccff_head[0] ropt_net_185:7 0.0001084846 +8 ccff_head[0]:5 ropt_net_185:4 2.761855e-05 +9 ccff_head[0]:6 ropt_net_185:6 0.0001084846 +10 ccff_head[0]:4 ropt_net_185:5 2.761855e-05 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.0009591917 +1 ccff_head[0]:5 ccff_head[0]:4 0.008104911 +2 ccff_head[0]:6 ccff_head[0]:5 0.00341 +3 ccff_head[0]:3 ccff_head[0]:2 0.006341518 +4 ccff_head[0]:4 ccff_head[0]:3 0.0045 +5 ccff_head[0]:2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET top_grid_pin_20_[0] 0.0005106375 //LENGTH 4.710 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 56.120 72.080 +*P top_grid_pin_20_[0] O *L 0.7423 *C 57.500 74.835 +*N top_grid_pin_20_[0]:2 *C 57.500 72.805 +*N top_grid_pin_20_[0]:3 *C 57.455 72.760 +*N top_grid_pin_20_[0]:4 *C 56.120 72.760 +*N top_grid_pin_20_[0]:5 *C 56.120 72.080 + +*CAP +0 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_20_[0] 0.0001089025 +2 top_grid_pin_20_[0]:2 0.0001089025 +3 top_grid_pin_20_[0]:3 9.497835e-05 +4 top_grid_pin_20_[0]:4 0.0001340045 +5 top_grid_pin_20_[0]:5 6.284963e-05 + +*RES +0 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_20_[0]:5 0.152 +1 top_grid_pin_20_[0]:3 top_grid_pin_20_[0]:2 0.0045 +2 top_grid_pin_20_[0]:2 top_grid_pin_20_[0] 0.0018125 +3 top_grid_pin_20_[0]:5 top_grid_pin_20_[0]:4 0.0006071429 +4 top_grid_pin_20_[0]:4 top_grid_pin_20_[0]:3 0.001191964 + +*END + +*D_NET top_grid_pin_29_[0] 0.0007071364 //LENGTH 5.450 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 76.360 72.080 +*P top_grid_pin_29_[0] O *L 0.7423 *C 74.520 74.835 +*N top_grid_pin_29_[0]:2 *C 74.520 74.120 +*N top_grid_pin_29_[0]:3 *C 74.980 74.120 +*N top_grid_pin_29_[0]:4 *C 74.980 72.465 +*N top_grid_pin_29_[0]:5 *C 75.025 72.420 +*N top_grid_pin_29_[0]:6 *C 76.360 72.420 +*N top_grid_pin_29_[0]:7 *C 76.360 72.080 + +*CAP +0 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_29_[0] 4.765737e-05 +2 top_grid_pin_29_[0]:2 7.514434e-05 +3 top_grid_pin_29_[0]:3 0.0001602756 +4 top_grid_pin_29_[0]:4 0.0001327887 +5 top_grid_pin_29_[0]:5 0.0001082451 +6 top_grid_pin_29_[0]:6 0.0001327413 +7 top_grid_pin_29_[0]:7 4.928389e-05 + +*RES +0 mux_bottom_ipin_13\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_29_[0]:7 0.152 +1 top_grid_pin_29_[0]:5 top_grid_pin_29_[0]:4 0.0045 +2 top_grid_pin_29_[0]:4 top_grid_pin_29_[0]:3 0.001477679 +3 top_grid_pin_29_[0]:7 top_grid_pin_29_[0]:6 0.0003035715 +4 top_grid_pin_29_[0]:6 top_grid_pin_29_[0]:5 0.001191964 +5 top_grid_pin_29_[0]:2 top_grid_pin_29_[0] 0.0006383929 +6 top_grid_pin_29_[0]:3 top_grid_pin_29_[0]:2 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.001467702 //LENGTH 11.215 LUMPCC 0.0002312005 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 48.145 63.920 +*I mem_bottom_ipin_1\/FTB_2__41:A I *L 0.001746 *C 44.160 58.480 +*I mux_bottom_ipin_1\/mux_l4_in_0_:S I *L 0.00357 *C 45.180 61.495 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 45.180 61.495 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 44.198 58.480 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 45.035 58.480 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 45.080 58.525 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 45.080 61.155 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 45.238 61.200 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 47.795 61.200 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 47.840 61.245 +*N mux_tree_tapbuf_size10_1_sram[3]:11 *C 47.840 63.875 +*N mux_tree_tapbuf_size10_1_sram[3]:12 *C 47.840 63.920 +*N mux_tree_tapbuf_size10_1_sram[3]:13 *C 48.145 63.920 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_1\/FTB_2__41:A 1e-06 +2 mux_bottom_ipin_1\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 6.21108e-05 +4 mux_tree_tapbuf_size10_1_sram[3]:4 7.650444e-05 +5 mux_tree_tapbuf_size10_1_sram[3]:5 7.650444e-05 +6 mux_tree_tapbuf_size10_1_sram[3]:6 0.0001683737 +7 mux_tree_tapbuf_size10_1_sram[3]:7 0.0001683737 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.0001355724 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.0001020326 +10 mux_tree_tapbuf_size10_1_sram[3]:10 0.0001679937 +11 mux_tree_tapbuf_size10_1_sram[3]:11 0.0001679937 +12 mux_tree_tapbuf_size10_1_sram[3]:12 5.464276e-05 +13 mux_tree_tapbuf_size10_1_sram[3]:13 5.339961e-05 +14 mux_tree_tapbuf_size10_1_sram[3]:9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.316201e-05 +15 mux_tree_tapbuf_size10_1_sram[3]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.316201e-05 +16 mux_tree_tapbuf_size10_1_sram[3]:9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.243822e-05 +17 mux_tree_tapbuf_size10_1_sram[3]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.243822e-05 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:3 mux_bottom_ipin_1\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.002283482 +3 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.0045 +4 mux_tree_tapbuf_size10_1_sram[3]:12 mux_tree_tapbuf_size10_1_sram[3]:11 0.0045 +5 mux_tree_tapbuf_size10_1_sram[3]:11 mux_tree_tapbuf_size10_1_sram[3]:10 0.002348214 +6 mux_tree_tapbuf_size10_1_sram[3]:13 mux_tree_tapbuf_size10_1_sram[3]:12 0.0001657609 +7 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.0045 +8 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:3 0.0001271552 +9 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 0.002348214 +10 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:4 0.0007477679 +11 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.0045 +12 mux_tree_tapbuf_size10_1_sram[3]:4 mem_bottom_ipin_1\/FTB_2__41:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[1] 0.004099738 //LENGTH 32.250 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 23.305 49.980 +*I mux_bottom_ipin_9\/mux_l2_in_3_:S I *L 0.00357 *C 18.040 57.800 +*I mux_bottom_ipin_9\/mux_l2_in_2_:S I *L 0.00357 *C 20.340 61.200 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 16.275 66.300 +*I mux_bottom_ipin_9\/mux_l2_in_0_:S I *L 0.00357 *C 20.800 55.760 +*I mux_bottom_ipin_9\/mux_l2_in_1_:S I *L 0.00357 *C 16.200 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:6 *C 16.238 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:7 *C 20.713 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:8 *C 20.700 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:9 *C 16.312 66.300 +*N mux_tree_tapbuf_size10_5_sram[1]:10 *C 20.195 66.300 +*N mux_tree_tapbuf_size10_5_sram[1]:11 *C 20.240 66.255 +*N mux_tree_tapbuf_size10_5_sram[1]:12 *C 20.240 61.200 +*N mux_tree_tapbuf_size10_5_sram[1]:13 *C 20.240 61.200 +*N mux_tree_tapbuf_size10_5_sram[1]:14 *C 18.078 57.800 +*N mux_tree_tapbuf_size10_5_sram[1]:15 *C 20.195 57.800 +*N mux_tree_tapbuf_size10_5_sram[1]:16 *C 20.240 57.800 +*N mux_tree_tapbuf_size10_5_sram[1]:17 *C 20.240 55.760 +*N mux_tree_tapbuf_size10_5_sram[1]:18 *C 20.240 50.025 +*N mux_tree_tapbuf_size10_5_sram[1]:19 *C 20.285 49.980 +*N mux_tree_tapbuf_size10_5_sram[1]:20 *C 23.268 49.980 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_ipin_9\/mux_l2_in_2_:S 1e-06 +3 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_ipin_9\/mux_l2_in_0_:S 1e-06 +5 mux_bottom_ipin_9\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_5_sram[1]:6 0.0003727464 +7 mux_tree_tapbuf_size10_5_sram[1]:7 0.0003727464 +8 mux_tree_tapbuf_size10_5_sram[1]:8 7.017649e-05 +9 mux_tree_tapbuf_size10_5_sram[1]:9 0.0003137155 +10 mux_tree_tapbuf_size10_5_sram[1]:10 0.0003137155 +11 mux_tree_tapbuf_size10_5_sram[1]:11 0.0002767528 +12 mux_tree_tapbuf_size10_5_sram[1]:12 3.279421e-05 +13 mux_tree_tapbuf_size10_5_sram[1]:13 0.0004881383 +14 mux_tree_tapbuf_size10_5_sram[1]:14 0.0001706163 +15 mux_tree_tapbuf_size10_5_sram[1]:15 0.0001706163 +16 mux_tree_tapbuf_size10_5_sram[1]:16 0.0003309322 +17 mux_tree_tapbuf_size10_5_sram[1]:17 0.0004703432 +18 mux_tree_tapbuf_size10_5_sram[1]:18 0.0003178943 +19 mux_tree_tapbuf_size10_5_sram[1]:19 0.0001962748 +20 mux_tree_tapbuf_size10_5_sram[1]:20 0.0001962748 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_5_sram[1]:20 0.152 +1 mux_tree_tapbuf_size10_5_sram[1]:20 mux_tree_tapbuf_size10_5_sram[1]:19 0.002662946 +2 mux_tree_tapbuf_size10_5_sram[1]:19 mux_tree_tapbuf_size10_5_sram[1]:18 0.0045 +3 mux_tree_tapbuf_size10_5_sram[1]:18 mux_tree_tapbuf_size10_5_sram[1]:17 0.005120536 +4 mux_tree_tapbuf_size10_5_sram[1]:7 mux_bottom_ipin_9\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_5_sram[1]:7 mux_tree_tapbuf_size10_5_sram[1]:6 0.003995536 +6 mux_tree_tapbuf_size10_5_sram[1]:8 mux_tree_tapbuf_size10_5_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size10_5_sram[1]:10 mux_tree_tapbuf_size10_5_sram[1]:9 0.003466518 +8 mux_tree_tapbuf_size10_5_sram[1]:11 mux_tree_tapbuf_size10_5_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size10_5_sram[1]:9 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_5_sram[1]:15 mux_tree_tapbuf_size10_5_sram[1]:14 0.001890625 +11 mux_tree_tapbuf_size10_5_sram[1]:16 mux_tree_tapbuf_size10_5_sram[1]:15 0.0045 +12 mux_tree_tapbuf_size10_5_sram[1]:16 mux_tree_tapbuf_size10_5_sram[1]:13 0.003035714 +13 mux_tree_tapbuf_size10_5_sram[1]:14 mux_bottom_ipin_9\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size10_5_sram[1]:12 mux_bottom_ipin_9\/mux_l2_in_2_:S 0.152 +15 mux_tree_tapbuf_size10_5_sram[1]:13 mux_tree_tapbuf_size10_5_sram[1]:12 0.0045 +16 mux_tree_tapbuf_size10_5_sram[1]:13 mux_tree_tapbuf_size10_5_sram[1]:11 0.004513393 +17 mux_tree_tapbuf_size10_5_sram[1]:6 mux_bottom_ipin_9\/mux_l2_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_5_sram[1]:17 mux_tree_tapbuf_size10_5_sram[1]:16 0.001821429 +19 mux_tree_tapbuf_size10_5_sram[1]:17 mux_tree_tapbuf_size10_5_sram[1]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_7_ccff_tail[0] 0.0007362625 //LENGTH 5.065 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_13\/FTB_8__47:X O *L 0 *C 88.050 66.300 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 90.325 64.260 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 *C 90.325 64.260 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 *C 90.160 64.260 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 *C 90.160 64.305 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 *C 90.160 66.255 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 *C 90.115 66.300 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 *C 88.088 66.300 + +*CAP +0 mem_bottom_ipin_13\/FTB_8__47:X 1e-06 +1 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 4.643846e-05 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 5.055072e-05 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0001352497 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0001352497 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.000183387 +7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.000183387 + +*RES +0 mem_bottom_ipin_13\/FTB_8__47:X mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.001810268 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.001741072 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 8.967391e-05 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[2] 0.004018665 //LENGTH 29.270 LUMPCC 0.0005780401 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.025 63.920 +*I mux_bottom_ipin_7\/mux_l3_in_1_:S I *L 0.00357 *C 31.840 61.495 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 26.840 69.700 +*I mux_bottom_ipin_7\/mux_l3_in_0_:S I *L 0.00357 *C 29.080 58.480 +*N mux_tree_tapbuf_size8_3_sram[2]:4 *C 29.095 58.480 +*N mux_tree_tapbuf_size8_3_sram[2]:5 *C 29.418 58.480 +*N mux_tree_tapbuf_size8_3_sram[2]:6 *C 29.440 58.525 +*N mux_tree_tapbuf_size8_3_sram[2]:7 *C 26.840 69.700 +*N mux_tree_tapbuf_size8_3_sram[2]:8 *C 26.680 69.700 +*N mux_tree_tapbuf_size8_3_sram[2]:9 *C 26.680 69.655 +*N mux_tree_tapbuf_size8_3_sram[2]:10 *C 26.680 60.565 +*N mux_tree_tapbuf_size8_3_sram[2]:11 *C 26.725 60.520 +*N mux_tree_tapbuf_size8_3_sram[2]:12 *C 29.395 60.520 +*N mux_tree_tapbuf_size8_3_sram[2]:13 *C 29.440 60.520 +*N mux_tree_tapbuf_size8_3_sram[2]:14 *C 29.440 61.495 +*N mux_tree_tapbuf_size8_3_sram[2]:15 *C 29.485 61.540 +*N mux_tree_tapbuf_size8_3_sram[2]:16 *C 31.840 61.540 +*N mux_tree_tapbuf_size8_3_sram[2]:17 *C 31.840 61.880 +*N mux_tree_tapbuf_size8_3_sram[2]:18 *C 37.215 61.880 +*N mux_tree_tapbuf_size8_3_sram[2]:19 *C 37.260 61.925 +*N mux_tree_tapbuf_size8_3_sram[2]:20 *C 37.260 63.875 +*N mux_tree_tapbuf_size8_3_sram[2]:21 *C 37.305 63.920 +*N mux_tree_tapbuf_size8_3_sram[2]:22 *C 37.988 63.920 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_7\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_3_sram[2]:4 5.806456e-05 +5 mux_tree_tapbuf_size8_3_sram[2]:5 5.806456e-05 +6 mux_tree_tapbuf_size8_3_sram[2]:6 0.0001283395 +7 mux_tree_tapbuf_size8_3_sram[2]:7 5.491819e-05 +8 mux_tree_tapbuf_size8_3_sram[2]:8 5.936155e-05 +9 mux_tree_tapbuf_size8_3_sram[2]:9 0.000383028 +10 mux_tree_tapbuf_size8_3_sram[2]:10 0.000383028 +11 mux_tree_tapbuf_size8_3_sram[2]:11 0.000189887 +12 mux_tree_tapbuf_size8_3_sram[2]:12 0.000189887 +13 mux_tree_tapbuf_size8_3_sram[2]:13 0.0002332151 +14 mux_tree_tapbuf_size8_3_sram[2]:14 6.883666e-05 +15 mux_tree_tapbuf_size8_3_sram[2]:15 0.0001677406 +16 mux_tree_tapbuf_size8_3_sram[2]:16 0.0001982178 +17 mux_tree_tapbuf_size8_3_sram[2]:17 0.0004671197 +18 mux_tree_tapbuf_size8_3_sram[2]:18 0.0004366425 +19 mux_tree_tapbuf_size8_3_sram[2]:19 0.0001257694 +20 mux_tree_tapbuf_size8_3_sram[2]:20 0.0001257694 +21 mux_tree_tapbuf_size8_3_sram[2]:21 5.436773e-05 +22 mux_tree_tapbuf_size8_3_sram[2]:22 5.436773e-05 +23 mux_tree_tapbuf_size8_3_sram[2]:12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.262521e-05 +24 mux_tree_tapbuf_size8_3_sram[2]:11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.262521e-05 +25 mux_tree_tapbuf_size8_3_sram[2]:15 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.180485e-05 +26 mux_tree_tapbuf_size8_3_sram[2]:16 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.180485e-05 +27 mux_tree_tapbuf_size8_3_sram[2]:12 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.640444e-06 +28 mux_tree_tapbuf_size8_3_sram[2]:11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.640444e-06 +29 mux_tree_tapbuf_size8_3_sram[2]:10 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002199496 +30 mux_tree_tapbuf_size8_3_sram[2]:9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002199496 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_3_sram[2]:22 0.152 +1 mux_tree_tapbuf_size8_3_sram[2]:12 mux_tree_tapbuf_size8_3_sram[2]:11 0.002383929 +2 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:12 0.0045 +3 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:6 0.00178125 +4 mux_tree_tapbuf_size8_3_sram[2]:11 mux_tree_tapbuf_size8_3_sram[2]:10 0.0045 +5 mux_tree_tapbuf_size8_3_sram[2]:10 mux_tree_tapbuf_size8_3_sram[2]:9 0.008116072 +6 mux_tree_tapbuf_size8_3_sram[2]:8 mux_tree_tapbuf_size8_3_sram[2]:7 8.695653e-05 +7 mux_tree_tapbuf_size8_3_sram[2]:9 mux_tree_tapbuf_size8_3_sram[2]:8 0.0045 +8 mux_tree_tapbuf_size8_3_sram[2]:7 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +9 mux_tree_tapbuf_size8_3_sram[2]:15 mux_tree_tapbuf_size8_3_sram[2]:14 0.0045 +10 mux_tree_tapbuf_size8_3_sram[2]:14 mux_tree_tapbuf_size8_3_sram[2]:13 0.0008705358 +11 mux_tree_tapbuf_size8_3_sram[2]:16 mux_bottom_ipin_7\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size8_3_sram[2]:16 mux_tree_tapbuf_size8_3_sram[2]:15 0.002102679 +13 mux_tree_tapbuf_size8_3_sram[2]:5 mux_tree_tapbuf_size8_3_sram[2]:4 0.0001752718 +14 mux_tree_tapbuf_size8_3_sram[2]:6 mux_tree_tapbuf_size8_3_sram[2]:5 0.0045 +15 mux_tree_tapbuf_size8_3_sram[2]:4 mux_bottom_ipin_7\/mux_l3_in_0_:S 0.152 +16 mux_tree_tapbuf_size8_3_sram[2]:18 mux_tree_tapbuf_size8_3_sram[2]:17 0.004799108 +17 mux_tree_tapbuf_size8_3_sram[2]:19 mux_tree_tapbuf_size8_3_sram[2]:18 0.0045 +18 mux_tree_tapbuf_size8_3_sram[2]:21 mux_tree_tapbuf_size8_3_sram[2]:20 0.0045 +19 mux_tree_tapbuf_size8_3_sram[2]:20 mux_tree_tapbuf_size8_3_sram[2]:19 0.001741071 +20 mux_tree_tapbuf_size8_3_sram[2]:22 mux_tree_tapbuf_size8_3_sram[2]:21 0.000609375 +21 mux_tree_tapbuf_size8_3_sram[2]:17 mux_tree_tapbuf_size8_3_sram[2]:16 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[3] 0.001743119 //LENGTH 14.210 LUMPCC 0.0001346125 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 62.405 69.360 +*I mem_bottom_ipin_15\/FTB_16__55:A I *L 0.001746 *C 59.800 63.920 +*I mux_bottom_ipin_15\/mux_l4_in_0_:S I *L 0.00357 *C 66.600 67.320 +*N mux_tree_tapbuf_size8_7_sram[3]:3 *C 66.562 67.320 +*N mux_tree_tapbuf_size8_7_sram[3]:4 *C 59.838 63.920 +*N mux_tree_tapbuf_size8_7_sram[3]:5 *C 60.675 63.920 +*N mux_tree_tapbuf_size8_7_sram[3]:6 *C 60.720 63.965 +*N mux_tree_tapbuf_size8_7_sram[3]:7 *C 60.720 66.935 +*N mux_tree_tapbuf_size8_7_sram[3]:8 *C 60.765 66.980 +*N mux_tree_tapbuf_size8_7_sram[3]:9 *C 62.560 66.980 +*N mux_tree_tapbuf_size8_7_sram[3]:10 *C 62.560 67.320 +*N mux_tree_tapbuf_size8_7_sram[3]:11 *C 62.560 67.365 +*N mux_tree_tapbuf_size8_7_sram[3]:12 *C 62.560 69.315 +*N mux_tree_tapbuf_size8_7_sram[3]:13 *C 62.560 69.360 +*N mux_tree_tapbuf_size8_7_sram[3]:14 *C 62.405 69.360 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_15\/FTB_16__55:A 1e-06 +2 mux_bottom_ipin_15\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_7_sram[3]:3 0.0002356233 +4 mux_tree_tapbuf_size8_7_sram[3]:4 8.289582e-05 +5 mux_tree_tapbuf_size8_7_sram[3]:5 8.289582e-05 +6 mux_tree_tapbuf_size8_7_sram[3]:6 0.0001756607 +7 mux_tree_tapbuf_size8_7_sram[3]:7 0.0001756607 +8 mux_tree_tapbuf_size8_7_sram[3]:8 0.0001105742 +9 mux_tree_tapbuf_size8_7_sram[3]:9 0.0001388084 +10 mux_tree_tapbuf_size8_7_sram[3]:10 0.0002638575 +11 mux_tree_tapbuf_size8_7_sram[3]:11 0.0001227832 +12 mux_tree_tapbuf_size8_7_sram[3]:12 0.0001227832 +13 mux_tree_tapbuf_size8_7_sram[3]:13 4.941555e-05 +14 mux_tree_tapbuf_size8_7_sram[3]:14 4.454834e-05 +15 mux_tree_tapbuf_size8_7_sram[3]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.004743e-06 +16 mux_tree_tapbuf_size8_7_sram[3]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.004743e-06 +17 mux_tree_tapbuf_size8_7_sram[3]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.630152e-05 +18 mux_tree_tapbuf_size8_7_sram[3]:10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.630152e-05 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_7_sram[3]:14 0.152 +1 mux_tree_tapbuf_size8_7_sram[3]:8 mux_tree_tapbuf_size8_7_sram[3]:7 0.0045 +2 mux_tree_tapbuf_size8_7_sram[3]:7 mux_tree_tapbuf_size8_7_sram[3]:6 0.002651786 +3 mux_tree_tapbuf_size8_7_sram[3]:5 mux_tree_tapbuf_size8_7_sram[3]:4 0.0007477678 +4 mux_tree_tapbuf_size8_7_sram[3]:6 mux_tree_tapbuf_size8_7_sram[3]:5 0.0045 +5 mux_tree_tapbuf_size8_7_sram[3]:4 mem_bottom_ipin_15\/FTB_16__55:A 0.152 +6 mux_tree_tapbuf_size8_7_sram[3]:3 mux_bottom_ipin_15\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_7_sram[3]:10 mux_tree_tapbuf_size8_7_sram[3]:9 0.0003035714 +8 mux_tree_tapbuf_size8_7_sram[3]:10 mux_tree_tapbuf_size8_7_sram[3]:3 0.003573661 +9 mux_tree_tapbuf_size8_7_sram[3]:11 mux_tree_tapbuf_size8_7_sram[3]:10 0.0045 +10 mux_tree_tapbuf_size8_7_sram[3]:13 mux_tree_tapbuf_size8_7_sram[3]:12 0.0045 +11 mux_tree_tapbuf_size8_7_sram[3]:12 mux_tree_tapbuf_size8_7_sram[3]:11 0.001741072 +12 mux_tree_tapbuf_size8_7_sram[3]:14 mux_tree_tapbuf_size8_7_sram[3]:13 8.423914e-05 +13 mux_tree_tapbuf_size8_7_sram[3]:9 mux_tree_tapbuf_size8_7_sram[3]:8 0.001602679 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.006452979 //LENGTH 49.275 LUMPCC 0.001395042 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l4_in_0_:X O *L 0 *C 58.135 28.560 +*I mux_bottom_ipin_0\/BUFT_RR_56:A I *L 0.001776 *C 53.820 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 53.570 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 53.858 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 54.235 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 54.280 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 54.278 69.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 54.280 69.353 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 54.280 29.248 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 54.300 29.240 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 58.873 29.240 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 58.880 29.183 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 58.880 28.605 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 58.835 28.560 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 58.172 28.560 + +*CAP +0 mux_bottom_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/BUFT_RR_56:A 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 8.06844e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.767943e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.767943e-05 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.464142e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.06844e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.002019016 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.002019016 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0002238342 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0002238342 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.849517e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 5.849517e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 8.093891e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:14 8.093891e-05 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_left_in[0]:37 0.0002764228 +16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[0]:38 0.0002764228 +17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 1.028548e-06 +18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 1.028548e-06 +19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004200695 +20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004200695 + +*RES +0 mux_bottom_ipin_0\/mux_l4_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0005915179 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.000515625 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0007163583 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.006283116 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001039141 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0003370536 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_0\/BUFT_RR_56:A 0.152 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003666296 //LENGTH 2.590 LUMPCC 0.0001032591 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_1_:X O *L 0 *C 56.295 53.380 +*I mux_bottom_ipin_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 53.995 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 54.033 53.380 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 56.258 53.380 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001306853 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001306853 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[1]:28 5.162954e-05 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[1]:29 5.162954e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001986607 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001211223 //LENGTH 8.510 LUMPCC 0.0003780414 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_2_:X O *L 0 *C 15.465 23.800 +*I mux_bottom_ipin_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 14.820 30.940 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 14.720 30.940 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 14.720 30.895 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 14.720 23.845 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 14.765 23.800 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 15.428 23.800 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.330275e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003284472 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003284472 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.049222e-05 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.049222e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[2]:21 6.950391e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[2]:22 6.950391e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_4_sram[0]:10 5.663281e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_4_sram[0]:16 1.750469e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_4_sram[0]:17 3.730262e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:6 8.076672e-06 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:8 5.663281e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:10 1.750469e-05 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:16 3.730262e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_4_sram[0]:7 8.076672e-06 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_2_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.006294644 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005754044 //LENGTH 4.440 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_0_:X O *L 0 *C 77.105 22.780 +*I mux_bottom_ipin_12\/mux_l3_in_0_:A1 I *L 0.00198 *C 78.300 20.060 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.200 20.060 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 78.200 20.105 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 78.200 22.735 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 78.155 22.780 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 77.142 22.780 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.300431e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001836285 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001836285 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.657153e-05 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.657153e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0009040179 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0005870743 //LENGTH 5.080 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l3_in_0_:X O *L 0 *C 84.355 61.540 +*I mux_bottom_ipin_13\/mux_l4_in_0_:A1 I *L 0.00198 *C 82.245 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 82.282 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 83.215 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 83.260 63.535 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 83.260 61.585 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 83.305 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 84.318 61.540 + +*CAP +0 mux_bottom_ipin_13\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.752428e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.752428e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001267878 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001267878 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.822507e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.822507e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l3_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_13\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0008325893 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001741071 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000904018 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0002909263 //LENGTH 2.205 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l1_in_0_:X O *L 0 *C 34.215 50.660 +*I mux_bottom_ipin_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 32.300 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 32.337 50.660 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.178 50.660 + +*CAP +0 mux_bottom_ipin_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001444631 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001444631 + +*RES +0 mux_bottom_ipin_3\/mux_l1_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001642857 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003710022 //LENGTH 2.475 LUMPCC 0.0001552592 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l3_in_1_:X O *L 0 *C 76.535 44.540 +*I mux_bottom_ipin_6\/mux_l4_in_0_:A0 I *L 0.001631 *C 74.350 44.540 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 74.388 44.540 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 76.498 44.540 + +*CAP +0 mux_bottom_ipin_6\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001068715 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001068715 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:8 7.762961e-05 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:9 7.762961e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l3_in_1_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_6\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008656855 //LENGTH 5.890 LUMPCC 0.0003511462 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_2_:X O *L 0 *C 21.905 22.440 +*I mux_bottom_ipin_10\/mux_l3_in_1_:A1 I *L 0.00198 *C 21.065 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 21.103 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 21.575 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 21.620 18.065 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 21.620 22.395 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 21.620 22.440 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 21.905 22.440 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.586134e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.586134e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001326021 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001326021 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.99363e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.56759e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:308 0.0001214117 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:307 0.0001214117 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.416141e-05 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.416141e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_2_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003866072 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007189987 //LENGTH 5.630 LUMPCC 9.990996e-05 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_1_:X O *L 0 *C 82.055 40.120 +*I mux_bottom_ipin_14\/mux_l3_in_0_:A0 I *L 0.001631 *C 82.515 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 82.478 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 81.925 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 81.880 44.155 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 81.880 40.165 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 81.880 40.120 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 82.055 40.120 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.31155e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.31155e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00019057 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00019057 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.50417e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.467608e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.995498e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.995498e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_1_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004933036 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0035625 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.510869e-05 + +*END + +*D_NET ropt_net_172 0.001262525 //LENGTH 9.565 LUMPCC 0.0002235163 DR + +*CONN +*I ropt_mt_inst_727:X O *L 0 *C 7.095 51.000 +*I ropt_mt_inst_776:A I *L 0.001767 *C 3.220 55.760 +*N ropt_net_172:2 *C 3.258 55.760 +*N ropt_net_172:3 *C 5.475 55.760 +*N ropt_net_172:4 *C 5.520 55.715 +*N ropt_net_172:5 *C 5.520 51.045 +*N ropt_net_172:6 *C 5.565 51.000 +*N ropt_net_172:7 *C 7.058 51.000 + +*CAP +0 ropt_mt_inst_727:X 1e-06 +1 ropt_mt_inst_776:A 1e-06 +2 ropt_net_172:2 0.000165034 +3 ropt_net_172:3 0.000165034 +4 ropt_net_172:4 0.0002116807 +5 ropt_net_172:5 0.0002116807 +6 ropt_net_172:6 0.0001417895 +7 ropt_net_172:7 0.0001417895 +8 ropt_net_172:5 mux_tree_tapbuf_size10_4_sram[3]:5 6.264575e-05 +9 ropt_net_172:4 mux_tree_tapbuf_size10_4_sram[3]:4 6.264575e-05 +10 ropt_net_172:7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 4.517088e-06 +11 ropt_net_172:6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 4.517088e-06 +12 ropt_net_172:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 4.459528e-05 +13 ropt_net_172:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 4.459528e-05 + +*RES +0 ropt_mt_inst_727:X ropt_net_172:7 0.152 +1 ropt_net_172:7 ropt_net_172:6 0.001332589 +2 ropt_net_172:6 ropt_net_172:5 0.0045 +3 ropt_net_172:5 ropt_net_172:4 0.004169643 +4 ropt_net_172:3 ropt_net_172:2 0.001979911 +5 ropt_net_172:4 ropt_net_172:3 0.0045 +6 ropt_net_172:2 ropt_mt_inst_776:A 0.152 + +*END + +*D_NET chanx_left_out[1] 0.002252139 //LENGTH 17.170 LUMPCC 0.0005036081 DR + +*CONN +*I FTB_22__21:X O *L 0 *C 13.620 70.040 +*P chanx_left_out[1] O *L 0.7423 *C 1.305 72.080 +*N chanx_left_out[1]:2 *C 10.113 72.080 +*N chanx_left_out[1]:3 *C 10.120 72.023 +*N chanx_left_out[1]:4 *C 10.120 69.405 +*N chanx_left_out[1]:5 *C 10.165 69.360 +*N chanx_left_out[1]:6 *C 10.995 69.360 +*N chanx_left_out[1]:7 *C 11.040 69.405 +*N chanx_left_out[1]:8 *C 11.040 69.995 +*N chanx_left_out[1]:9 *C 11.085 70.040 +*N chanx_left_out[1]:10 *C 13.583 70.040 + +*CAP +0 FTB_22__21:X 1e-06 +1 chanx_left_out[1] 0.0003819293 +2 chanx_left_out[1]:2 0.0003819293 +3 chanx_left_out[1]:3 0.0001719552 +4 chanx_left_out[1]:4 0.0001719552 +5 chanx_left_out[1]:5 7.005436e-05 +6 chanx_left_out[1]:6 7.005436e-05 +7 chanx_left_out[1]:7 6.088637e-05 +8 chanx_left_out[1]:8 6.088637e-05 +9 chanx_left_out[1]:9 0.0001889403 +10 chanx_left_out[1]:10 0.0001889403 +11 chanx_left_out[1] chanx_left_out[12]:6 0.0002495393 +12 chanx_left_out[1] chanx_left_out[12]:2 2.264745e-06 +13 chanx_left_out[1]:2 chanx_left_out[12]:7 0.0002495393 +14 chanx_left_out[1]:2 chanx_left_out[12]:3 2.264745e-06 + +*RES +0 FTB_22__21:X chanx_left_out[1]:10 0.152 +1 chanx_left_out[1]:10 chanx_left_out[1]:9 0.002229911 +2 chanx_left_out[1]:9 chanx_left_out[1]:8 0.0045 +3 chanx_left_out[1]:8 chanx_left_out[1]:7 0.0005267857 +4 chanx_left_out[1]:6 chanx_left_out[1]:5 0.0007410714 +5 chanx_left_out[1]:7 chanx_left_out[1]:6 0.0045 +6 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +7 chanx_left_out[1]:4 chanx_left_out[1]:3 0.002337054 +8 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +9 chanx_left_out[1]:2 chanx_left_out[1] 0.001379842 + +*END + +*D_NET ropt_net_176 0.0001592276 //LENGTH 0.965 LUMPCC 7.195914e-05 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 92.705 66.640 +*I ropt_mt_inst_780:A I *L 0.001767 *C 93.380 66.640 +*N ropt_net_176:2 *C 93.343 66.640 +*N ropt_net_176:3 *C 92.743 66.640 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 ropt_mt_inst_780:A 1e-06 +2 ropt_net_176:2 4.263422e-05 +3 ropt_net_176:3 4.263422e-05 +4 ropt_net_176:3 mux_tree_tapbuf_size10_7_sram[2]:17 3.597957e-05 +5 ropt_net_176:2 mux_tree_tapbuf_size10_7_sram[2]:18 3.597957e-05 + +*RES +0 ropt_mt_inst_746:X ropt_net_176:3 0.152 +1 ropt_net_176:3 ropt_net_176:2 0.0005357143 +2 ropt_net_176:2 ropt_mt_inst_780:A 0.152 + +*END + +*D_NET mem_bottom_ipin_15/net_net_74 0.0009717285 //LENGTH 8.140 LUMPCC 0.0002322538 DR + +*CONN +*I mem_bottom_ipin_15\/BUFT_RR_75:X O *L 0 *C 3.365 69.020 +*I mem_bottom_ipin_15\/BUFT_RR_105:A I *L 0.001767 *C 3.220 61.200 +*N mem_bottom_ipin_15/net_net_74:2 *C 3.220 61.200 +*N mem_bottom_ipin_15/net_net_74:3 *C 3.220 61.245 +*N mem_bottom_ipin_15/net_net_74:4 *C 3.220 68.975 +*N mem_bottom_ipin_15/net_net_74:5 *C 3.220 69.020 + +*CAP +0 mem_bottom_ipin_15\/BUFT_RR_75:X 1e-06 +1 mem_bottom_ipin_15\/BUFT_RR_105:A 1e-06 +2 mem_bottom_ipin_15/net_net_74:2 3.211106e-05 +3 mem_bottom_ipin_15/net_net_74:3 0.0003374767 +4 mem_bottom_ipin_15/net_net_74:4 0.0003374767 +5 mem_bottom_ipin_15/net_net_74:5 3.041023e-05 +6 mem_bottom_ipin_15/net_net_74:3 top_grid_pin_24_[0]:6 5.889946e-05 +7 mem_bottom_ipin_15/net_net_74:4 top_grid_pin_24_[0]:5 5.889946e-05 +8 mem_bottom_ipin_15/net_net_74:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.722743e-05 +9 mem_bottom_ipin_15/net_net_74:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 5.722743e-05 + +*RES +0 mem_bottom_ipin_15\/BUFT_RR_75:X mem_bottom_ipin_15/net_net_74:5 0.152 +1 mem_bottom_ipin_15/net_net_74:2 mem_bottom_ipin_15\/BUFT_RR_105:A 0.152 +2 mem_bottom_ipin_15/net_net_74:3 mem_bottom_ipin_15/net_net_74:2 0.0045 +3 mem_bottom_ipin_15/net_net_74:5 mem_bottom_ipin_15/net_net_74:4 0.0045 +4 mem_bottom_ipin_15/net_net_74:4 mem_bottom_ipin_15/net_net_74:3 0.006901786 + +*END + +*D_NET chanx_right_out[10] 0.001147766 //LENGTH 9.645 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 98.900 36.040 +*P chanx_right_out[10] O *L 0.7423 *C 103.650 31.960 +*N chanx_right_out[10]:2 *C 100.748 31.960 +*N chanx_right_out[10]:3 *C 100.740 32.017 +*N chanx_right_out[10]:4 *C 100.740 35.995 +*N chanx_right_out[10]:5 *C 100.695 36.040 +*N chanx_right_out[10]:6 *C 98.938 36.040 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 chanx_right_out[10] 0.0002038091 +2 chanx_right_out[10]:2 0.0002038091 +3 chanx_right_out[10]:3 0.0002331288 +4 chanx_right_out[10]:4 0.0002331288 +5 chanx_right_out[10]:5 0.0001364449 +6 chanx_right_out[10]:6 0.0001364449 + +*RES +0 ropt_mt_inst_792:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:6 chanx_right_out[10]:5 0.001569197 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.003551339 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.000454725 + +*END + +*D_NET chanx_right_out[8] 0.0006536378 //LENGTH 6.010 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 101.855 19.720 +*P chanx_right_out[8] O *L 0.7423 *C 103.650 16.320 +*N chanx_right_out[8]:2 *C 103.047 16.320 +*N chanx_right_out[8]:3 *C 103.040 16.378 +*N chanx_right_out[8]:4 *C 103.040 19.675 +*N chanx_right_out[8]:5 *C 102.995 19.720 +*N chanx_right_out[8]:6 *C 101.892 19.720 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 chanx_right_out[8] 6.828304e-05 +2 chanx_right_out[8]:2 6.828304e-05 +3 chanx_right_out[8]:3 0.0001704439 +4 chanx_right_out[8]:4 0.0001704439 +5 chanx_right_out[8]:5 8.759197e-05 +6 chanx_right_out[8]:6 8.759197e-05 + +*RES +0 ropt_mt_inst_800:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:6 chanx_right_out[8]:5 0.000984375 +2 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.002944197 +4 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +5 chanx_right_out[8]:2 chanx_right_out[8] 9.439165e-05 + +*END + +*D_NET chanx_left_in[2] 0.02149624 //LENGTH 152.260 LUMPCC 0.003657711 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.305 35.360 +*I mux_bottom_ipin_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 39.390 26.520 +*I mux_bottom_ipin_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 81.710 31.620 +*I mux_bottom_ipin_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.310 37.060 +*I BUFT_P_95:A I *L 0.001776 *C 86.940 9.520 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 78.565 25.500 +*I mux_bottom_ipin_12\/mux_l1_in_1_:A1 I *L 0.00198 *C 71.300 23.460 +*I mux_bottom_ipin_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 45.180 23.460 +*I mux_bottom_ipin_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 9.375 22.440 +*I mux_bottom_ipin_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 13.900 25.500 +*N chanx_left_in[2]:10 *C 13.900 25.500 +*N chanx_left_in[2]:11 *C 13.800 25.160 +*N chanx_left_in[2]:12 *C 9.412 22.440 +*N chanx_left_in[2]:13 *C 11.455 22.440 +*N chanx_left_in[2]:14 *C 11.500 22.485 +*N chanx_left_in[2]:15 *C 45.218 23.460 +*N chanx_left_in[2]:16 *C 45.540 23.460 +*N chanx_left_in[2]:17 *C 79.350 25.500 +*N chanx_left_in[2]:18 *C 86.903 9.520 +*N chanx_left_in[2]:19 *C 86.525 9.520 +*N chanx_left_in[2]:20 *C 86.480 9.565 +*N chanx_left_in[2]:21 *C 86.480 31.620 +*N chanx_left_in[2]:22 *C 86.310 37.060 +*N chanx_left_in[2]:23 *C 86.020 37.060 +*N chanx_left_in[2]:24 *C 86.020 37.015 +*N chanx_left_in[2]:25 *C 86.020 31.620 +*N chanx_left_in[2]:26 *C 85.975 31.620 +*N chanx_left_in[2]:27 *C 81.880 31.620 +*N chanx_left_in[2]:28 *C 81.880 31.280 +*N chanx_left_in[2]:29 *C 80.085 31.280 +*N chanx_left_in[2]:30 *C 80.040 31.235 +*N chanx_left_in[2]:31 *C 80.040 25.545 +*N chanx_left_in[2]:32 *C 79.995 25.500 +*N chanx_left_in[2]:33 *C 79.157 25.500 +*N chanx_left_in[2]:34 *C 79.120 25.500 +*N chanx_left_in[2]:35 *C 78.565 25.500 +*N chanx_left_in[2]:36 *C 78.550 25.500 +*N chanx_left_in[2]:37 *C 78.178 25.500 +*N chanx_left_in[2]:38 *C 71.345 25.500 +*N chanx_left_in[2]:39 *C 71.300 25.455 +*N chanx_left_in[2]:40 *C 71.300 23.505 +*N chanx_left_in[2]:41 *C 71.300 23.460 +*N chanx_left_in[2]:42 *C 71.300 23.800 +*N chanx_left_in[2]:43 *C 45.540 23.800 +*N chanx_left_in[2]:44 *C 41.445 23.800 +*N chanx_left_in[2]:45 *C 41.400 23.845 +*N chanx_left_in[2]:46 *C 41.400 26.135 +*N chanx_left_in[2]:47 *C 41.355 26.180 +*N chanx_left_in[2]:48 *C 39.560 26.180 +*N chanx_left_in[2]:49 *C 39.513 26.498 +*N chanx_left_in[2]:50 *C 29.945 26.520 +*N chanx_left_in[2]:51 *C 29.900 26.475 +*N chanx_left_in[2]:52 *C 29.900 25.218 +*N chanx_left_in[2]:53 *C 29.893 25.160 +*N chanx_left_in[2]:54 *C 11.508 25.160 +*N chanx_left_in[2]:55 *C 11.500 25.160 +*N chanx_left_in[2]:56 *C 12.420 25.160 +*N chanx_left_in[2]:57 *C 12.420 25.160 +*N chanx_left_in[2]:58 *C 3.725 25.160 +*N chanx_left_in[2]:59 *C 3.680 25.205 +*N chanx_left_in[2]:60 *C 3.680 35.303 +*N chanx_left_in[2]:61 *C 3.673 35.360 + +*CAP +0 chanx_left_in[2] 0.0002168855 +1 mux_bottom_ipin_2\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_6\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_ipin_14\/mux_l2_in_0_:A0 1e-06 +4 BUFT_P_95:A 1e-06 +5 mux_bottom_ipin_0\/mux_l1_in_1_:A1 1e-06 +6 mux_bottom_ipin_12\/mux_l1_in_1_:A1 1e-06 +7 mux_bottom_ipin_4\/mux_l1_in_1_:A1 1e-06 +8 mux_bottom_ipin_10\/mux_l2_in_0_:A0 1e-06 +9 mux_bottom_ipin_8\/mux_l1_in_1_:A1 1e-06 +10 chanx_left_in[2]:10 5.749655e-05 +11 chanx_left_in[2]:11 0.0001360006 +12 chanx_left_in[2]:12 0.0002007379 +13 chanx_left_in[2]:13 0.0002007379 +14 chanx_left_in[2]:14 0.00018544 +15 chanx_left_in[2]:15 2.349527e-05 +16 chanx_left_in[2]:16 4.91493e-05 +17 chanx_left_in[2]:17 1e-06 +18 chanx_left_in[2]:18 4.039796e-05 +19 chanx_left_in[2]:19 4.039796e-05 +20 chanx_left_in[2]:20 0.001193914 +21 chanx_left_in[2]:21 0.001229537 +22 chanx_left_in[2]:22 5.45866e-05 +23 chanx_left_in[2]:23 5.896651e-05 +24 chanx_left_in[2]:24 0.0003166911 +25 chanx_left_in[2]:25 0.0003523135 +26 chanx_left_in[2]:26 0.0003497245 +27 chanx_left_in[2]:27 0.0003757696 +28 chanx_left_in[2]:28 0.0001555754 +29 chanx_left_in[2]:29 0.0001295303 +30 chanx_left_in[2]:30 0.0003430071 +31 chanx_left_in[2]:31 0.0003430071 +32 chanx_left_in[2]:32 7.844975e-05 +33 chanx_left_in[2]:33 7.844975e-05 +34 chanx_left_in[2]:34 1e-06 +35 chanx_left_in[2]:35 1e-06 +36 chanx_left_in[2]:36 4.61868e-05 +37 chanx_left_in[2]:37 0.0004762731 +38 chanx_left_in[2]:38 0.0004300863 +39 chanx_left_in[2]:39 0.0001348276 +40 chanx_left_in[2]:40 0.0001348276 +41 chanx_left_in[2]:41 5.993611e-05 +42 chanx_left_in[2]:42 0.001765618 +43 chanx_left_in[2]:43 0.002051875 +44 chanx_left_in[2]:44 0.0002884035 +45 chanx_left_in[2]:45 0.0001347639 +46 chanx_left_in[2]:46 0.0001347639 +47 chanx_left_in[2]:47 8.438557e-05 +48 chanx_left_in[2]:48 0.0001086443 +49 chanx_left_in[2]:49 0.0005838257 +50 chanx_left_in[2]:50 0.000559567 +51 chanx_left_in[2]:51 8.713785e-05 +52 chanx_left_in[2]:52 8.713785e-05 +53 chanx_left_in[2]:53 0.0007666174 +54 chanx_left_in[2]:54 0.0007666174 +55 chanx_left_in[2]:55 0.0002469507 +56 chanx_left_in[2]:56 9.38491e-05 +57 chanx_left_in[2]:57 0.0006847368 +58 chanx_left_in[2]:58 0.0005442265 +59 chanx_left_in[2]:59 0.0005640609 +60 chanx_left_in[2]:60 0.0005640609 +61 chanx_left_in[2]:61 0.0002168855 +62 chanx_left_in[2]:46 chanx_left_in[0]:44 8.190692e-06 +63 chanx_left_in[2]:45 chanx_left_in[0]:45 8.190692e-06 +64 chanx_left_in[2]:20 chanx_left_in[0]:27 9.15118e-06 +65 chanx_left_in[2]:20 chanx_left_in[0]:31 2.510425e-07 +66 chanx_left_in[2]:30 chanx_left_in[0]:32 4.732764e-07 +67 chanx_left_in[2]:31 chanx_left_in[0]:31 4.732764e-07 +68 chanx_left_in[2]:53 chanx_left_in[0]:46 0.0006553854 +69 chanx_left_in[2]:53 chanx_left_in[0]:51 5.289467e-06 +70 chanx_left_in[2]:54 chanx_left_in[0]:47 0.0006553854 +71 chanx_left_in[2]:54 chanx_left_in[0]:50 5.289467e-06 +72 chanx_left_in[2]:21 chanx_left_in[0]:26 9.15118e-06 +73 chanx_left_in[2]:21 chanx_left_in[0]:32 2.510425e-07 +74 chanx_left_in[2]:47 chanx_right_in[0]:29 7.687404e-05 +75 chanx_left_in[2]:20 chanx_right_in[0]:44 1.203226e-05 +76 chanx_left_in[2]:49 chanx_right_in[0]:26 1.176057e-05 +77 chanx_left_in[2]:49 chanx_right_in[0]:29 6.318261e-05 +78 chanx_left_in[2]:14 chanx_right_in[0]:15 5.518851e-06 +79 chanx_left_in[2]:50 chanx_right_in[0]:28 6.318261e-05 +80 chanx_left_in[2]:50 chanx_right_in[0]:25 1.176057e-05 +81 chanx_left_in[2]:53 chanx_right_in[0]:26 0.0007777371 +82 chanx_left_in[2]:55 chanx_right_in[0]:16 5.518851e-06 +83 chanx_left_in[2]:54 chanx_right_in[0]:25 0.0007777371 +84 chanx_left_in[2]:48 chanx_right_in[0]:28 7.687404e-05 +85 chanx_left_in[2]:21 chanx_right_in[0]:45 1.203226e-05 +86 chanx_left_in[2]:43 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.895957e-05 +87 chanx_left_in[2]:42 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.895957e-05 +88 chanx_left_in[2]:57 ropt_net_192:2 6.670278e-06 +89 chanx_left_in[2]:57 ropt_net_192:4 0.0001109752 +90 chanx_left_in[2]:58 ropt_net_192:5 0.0001109752 +91 chanx_left_in[2]:58 ropt_net_192:3 6.670278e-06 +92 chanx_left_in[2]:59 ropt_net_192:6 3.640407e-05 +93 chanx_left_in[2]:60 ropt_net_192:7 3.640407e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:61 0.0003709083 +1 chanx_left_in[2]:57 chanx_left_in[2]:56 0.0045 +2 chanx_left_in[2]:57 chanx_left_in[2]:11 0.001232143 +3 chanx_left_in[2]:56 chanx_left_in[2]:55 0.0008214285 +4 chanx_left_in[2]:41 chanx_left_in[2]:40 0.0045 +5 chanx_left_in[2]:41 mux_bottom_ipin_12\/mux_l1_in_1_:A1 0.152 +6 chanx_left_in[2]:40 chanx_left_in[2]:39 0.001741072 +7 chanx_left_in[2]:38 chanx_left_in[2]:37 0.006100446 +8 chanx_left_in[2]:39 chanx_left_in[2]:38 0.0045 +9 chanx_left_in[2]:36 chanx_left_in[2]:35 0.152 +10 chanx_left_in[2]:58 chanx_left_in[2]:57 0.007763393 +11 chanx_left_in[2]:59 chanx_left_in[2]:58 0.0045 +12 chanx_left_in[2]:60 chanx_left_in[2]:59 0.009015625 +13 chanx_left_in[2]:61 chanx_left_in[2]:60 0.00341 +14 chanx_left_in[2]:47 chanx_left_in[2]:46 0.0045 +15 chanx_left_in[2]:46 chanx_left_in[2]:45 0.002044643 +16 chanx_left_in[2]:44 chanx_left_in[2]:43 0.00365625 +17 chanx_left_in[2]:45 chanx_left_in[2]:44 0.0045 +18 chanx_left_in[2]:26 chanx_left_in[2]:25 0.0045 +19 chanx_left_in[2]:25 chanx_left_in[2]:24 0.004816965 +20 chanx_left_in[2]:25 chanx_left_in[2]:21 0.0004107143 +21 chanx_left_in[2]:19 chanx_left_in[2]:18 0.0003370536 +22 chanx_left_in[2]:20 chanx_left_in[2]:19 0.0045 +23 chanx_left_in[2]:18 BUFT_P_95:A 0.152 +24 chanx_left_in[2]:49 mux_bottom_ipin_2\/mux_l2_in_0_:A0 0.152 +25 chanx_left_in[2]:49 chanx_left_in[2]:48 0.0002834821 +26 chanx_left_in[2]:13 chanx_left_in[2]:12 0.001823661 +27 chanx_left_in[2]:14 chanx_left_in[2]:13 0.0045 +28 chanx_left_in[2]:12 mux_bottom_ipin_10\/mux_l2_in_0_:A0 0.152 +29 chanx_left_in[2]:15 mux_bottom_ipin_4\/mux_l1_in_1_:A1 0.152 +30 chanx_left_in[2]:27 mux_bottom_ipin_6\/mux_l2_in_0_:A0 0.152 +31 chanx_left_in[2]:27 chanx_left_in[2]:26 0.00365625 +32 chanx_left_in[2]:10 mux_bottom_ipin_8\/mux_l1_in_1_:A1 0.152 +33 chanx_left_in[2]:23 chanx_left_in[2]:22 0.0001576087 +34 chanx_left_in[2]:24 chanx_left_in[2]:23 0.0045 +35 chanx_left_in[2]:22 mux_bottom_ipin_14\/mux_l2_in_0_:A0 0.152 +36 chanx_left_in[2]:29 chanx_left_in[2]:28 0.001602679 +37 chanx_left_in[2]:30 chanx_left_in[2]:29 0.0045 +38 chanx_left_in[2]:32 chanx_left_in[2]:31 0.0045 +39 chanx_left_in[2]:31 chanx_left_in[2]:30 0.005080358 +40 chanx_left_in[2]:33 chanx_left_in[2]:32 0.0007477678 +41 chanx_left_in[2]:50 chanx_left_in[2]:49 0.008542411 +42 chanx_left_in[2]:51 chanx_left_in[2]:50 0.0045 +43 chanx_left_in[2]:52 chanx_left_in[2]:51 0.001122768 +44 chanx_left_in[2]:53 chanx_left_in[2]:52 0.00341 +45 chanx_left_in[2]:55 chanx_left_in[2]:54 0.00341 +46 chanx_left_in[2]:55 chanx_left_in[2]:14 0.002388393 +47 chanx_left_in[2]:54 chanx_left_in[2]:53 0.002880317 +48 chanx_left_in[2]:11 chanx_left_in[2]:10 0.0003035715 +49 chanx_left_in[2]:48 chanx_left_in[2]:47 0.001602679 +50 chanx_left_in[2]:43 chanx_left_in[2]:42 0.023 +51 chanx_left_in[2]:43 chanx_left_in[2]:16 0.0003035715 +52 chanx_left_in[2]:42 chanx_left_in[2]:41 0.0003035715 +53 chanx_left_in[2]:16 chanx_left_in[2]:15 0.0002879465 +54 chanx_left_in[2]:37 chanx_left_in[2]:36 0.0002024456 +55 chanx_left_in[2]:28 chanx_left_in[2]:27 0.0003035714 +56 chanx_left_in[2]:21 chanx_left_in[2]:20 0.01969197 +57 chanx_left_in[2]:34 chanx_left_in[2]:33 0.152 +58 chanx_left_in[2]:34 chanx_left_in[2]:17 0.01650588 +59 chanx_left_in[2]:35 chanx_left_in[2]:34 0.03985094 +60 chanx_left_in[2]:35 mux_bottom_ipin_0\/mux_l1_in_1_:A1 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[3] 0.001672306 //LENGTH 13.415 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 75.745 47.600 +*I mem_bottom_ipin_6\/FTB_11__50:A I *L 0.001746 *C 70.380 50.320 +*I mux_bottom_ipin_6\/mux_l4_in_0_:S I *L 0.00357 *C 73.240 45.560 +*N mux_tree_tapbuf_size8_2_sram[3]:3 *C 70.418 50.320 +*N mux_tree_tapbuf_size8_2_sram[3]:4 *C 73.095 50.320 +*N mux_tree_tapbuf_size8_2_sram[3]:5 *C 73.140 50.275 +*N mux_tree_tapbuf_size8_2_sram[3]:6 *C 73.140 45.605 +*N mux_tree_tapbuf_size8_2_sram[3]:7 *C 73.278 45.560 +*N mux_tree_tapbuf_size8_2_sram[3]:8 *C 75.395 45.560 +*N mux_tree_tapbuf_size8_2_sram[3]:9 *C 75.440 45.605 +*N mux_tree_tapbuf_size8_2_sram[3]:10 *C 75.440 47.555 +*N mux_tree_tapbuf_size8_2_sram[3]:11 *C 75.440 47.600 +*N mux_tree_tapbuf_size8_2_sram[3]:12 *C 75.745 47.600 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_6\/FTB_11__50:A 1e-06 +2 mux_bottom_ipin_6\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_2_sram[3]:3 0.0001870274 +4 mux_tree_tapbuf_size8_2_sram[3]:4 0.0001870274 +5 mux_tree_tapbuf_size8_2_sram[3]:5 0.0002782217 +6 mux_tree_tapbuf_size8_2_sram[3]:6 0.0002782217 +7 mux_tree_tapbuf_size8_2_sram[3]:7 0.0001828729 +8 mux_tree_tapbuf_size8_2_sram[3]:8 0.0001828729 +9 mux_tree_tapbuf_size8_2_sram[3]:9 0.0001330421 +10 mux_tree_tapbuf_size8_2_sram[3]:10 0.0001330421 +11 mux_tree_tapbuf_size8_2_sram[3]:11 5.540656e-05 +12 mux_tree_tapbuf_size8_2_sram[3]:12 5.157092e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_2_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size8_2_sram[3]:7 0.001890625 +2 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:8 0.0045 +3 mux_tree_tapbuf_size8_2_sram[3]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.0045 +4 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.001741072 +5 mux_tree_tapbuf_size8_2_sram[3]:12 mux_tree_tapbuf_size8_2_sram[3]:11 0.0001657609 +6 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size8_2_sram[3]:6 0.0045 +7 mux_tree_tapbuf_size8_2_sram[3]:7 mux_bottom_ipin_6\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_2_sram[3]:6 mux_tree_tapbuf_size8_2_sram[3]:5 0.004169643 +9 mux_tree_tapbuf_size8_2_sram[3]:4 mux_tree_tapbuf_size8_2_sram[3]:3 0.002390625 +10 mux_tree_tapbuf_size8_2_sram[3]:5 mux_tree_tapbuf_size8_2_sram[3]:4 0.0045 +11 mux_tree_tapbuf_size8_2_sram[3]:3 mem_bottom_ipin_6\/FTB_11__50:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[1] 0.004211415 //LENGTH 31.410 LUMPCC 0.0005981214 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 95.755 50.660 +*I mux_bottom_ipin_14\/mux_l2_in_2_:S I *L 0.00357 *C 89.800 45.175 +*I mux_bottom_ipin_14\/mux_l2_in_3_:S I *L 0.00357 *C 87.040 41.820 +*I mux_bottom_ipin_14\/mux_l2_in_0_:S I *L 0.00357 *C 85.200 36.720 +*I mux_bottom_ipin_14\/mux_l2_in_1_:S I *L 0.00357 *C 82.900 39.440 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 90.335 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:6 *C 90.335 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:7 *C 82.938 39.440 +*N mux_tree_tapbuf_size8_6_sram[1]:8 *C 83.260 39.440 +*N mux_tree_tapbuf_size8_6_sram[1]:9 *C 83.260 39.100 +*N mux_tree_tapbuf_size8_6_sram[1]:10 *C 85.100 36.720 +*N mux_tree_tapbuf_size8_6_sram[1]:11 *C 85.100 36.765 +*N mux_tree_tapbuf_size8_6_sram[1]:12 *C 85.100 39.055 +*N mux_tree_tapbuf_size8_6_sram[1]:13 *C 85.100 39.100 +*N mux_tree_tapbuf_size8_6_sram[1]:14 *C 87.355 39.100 +*N mux_tree_tapbuf_size8_6_sram[1]:15 *C 87.400 39.145 +*N mux_tree_tapbuf_size8_6_sram[1]:16 *C 87.055 41.820 +*N mux_tree_tapbuf_size8_6_sram[1]:17 *C 87.377 41.820 +*N mux_tree_tapbuf_size8_6_sram[1]:18 *C 87.400 41.820 +*N mux_tree_tapbuf_size8_6_sram[1]:19 *C 87.400 44.835 +*N mux_tree_tapbuf_size8_6_sram[1]:20 *C 87.445 44.880 +*N mux_tree_tapbuf_size8_6_sram[1]:21 *C 89.743 44.880 +*N mux_tree_tapbuf_size8_6_sram[1]:22 *C 89.800 45.175 +*N mux_tree_tapbuf_size8_6_sram[1]:23 *C 89.800 45.560 +*N mux_tree_tapbuf_size8_6_sram[1]:24 *C 90.575 45.560 +*N mux_tree_tapbuf_size8_6_sram[1]:25 *C 90.620 45.605 +*N mux_tree_tapbuf_size8_6_sram[1]:26 *C 90.620 47.895 +*N mux_tree_tapbuf_size8_6_sram[1]:27 *C 90.665 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:28 *C 94.255 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:29 *C 94.300 47.985 +*N mux_tree_tapbuf_size8_6_sram[1]:30 *C 94.300 50.615 +*N mux_tree_tapbuf_size8_6_sram[1]:31 *C 94.345 50.660 +*N mux_tree_tapbuf_size8_6_sram[1]:32 *C 95.718 50.660 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_14\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_14\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_14\/mux_l2_in_1_:S 1e-06 +5 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_6_sram[1]:6 5.036885e-05 +7 mux_tree_tapbuf_size8_6_sram[1]:7 4.175179e-05 +8 mux_tree_tapbuf_size8_6_sram[1]:8 6.701288e-05 +9 mux_tree_tapbuf_size8_6_sram[1]:9 0.0001648534 +10 mux_tree_tapbuf_size8_6_sram[1]:10 3.288121e-05 +11 mux_tree_tapbuf_size8_6_sram[1]:11 0.0001356678 +12 mux_tree_tapbuf_size8_6_sram[1]:12 0.0001356678 +13 mux_tree_tapbuf_size8_6_sram[1]:13 0.0002971522 +14 mux_tree_tapbuf_size8_6_sram[1]:14 0.0001246787 +15 mux_tree_tapbuf_size8_6_sram[1]:15 8.454754e-05 +16 mux_tree_tapbuf_size8_6_sram[1]:16 6.63182e-05 +17 mux_tree_tapbuf_size8_6_sram[1]:17 6.63182e-05 +18 mux_tree_tapbuf_size8_6_sram[1]:18 0.0002518207 +19 mux_tree_tapbuf_size8_6_sram[1]:19 0.000132785 +20 mux_tree_tapbuf_size8_6_sram[1]:20 0.0001175089 +21 mux_tree_tapbuf_size8_6_sram[1]:21 0.0001457441 +22 mux_tree_tapbuf_size8_6_sram[1]:22 8.781019e-05 +23 mux_tree_tapbuf_size8_6_sram[1]:23 0.0001128212 +24 mux_tree_tapbuf_size8_6_sram[1]:24 8.231569e-05 +25 mux_tree_tapbuf_size8_6_sram[1]:25 0.0001641494 +26 mux_tree_tapbuf_size8_6_sram[1]:26 0.0001641494 +27 mux_tree_tapbuf_size8_6_sram[1]:27 0.0002666526 +28 mux_tree_tapbuf_size8_6_sram[1]:28 0.0002467514 +29 mux_tree_tapbuf_size8_6_sram[1]:29 0.0001706233 +30 mux_tree_tapbuf_size8_6_sram[1]:30 0.0001706233 +31 mux_tree_tapbuf_size8_6_sram[1]:31 0.0001131597 +32 mux_tree_tapbuf_size8_6_sram[1]:32 0.0001131597 +33 mux_tree_tapbuf_size8_6_sram[1]:19 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.030052e-05 +34 mux_tree_tapbuf_size8_6_sram[1]:18 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.335495e-05 +35 mux_tree_tapbuf_size8_6_sram[1]:18 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.030052e-05 +36 mux_tree_tapbuf_size8_6_sram[1]:15 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.335495e-05 +37 mux_tree_tapbuf_size8_6_sram[1]:13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 4.578255e-05 +38 mux_tree_tapbuf_size8_6_sram[1]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.288691e-06 +39 mux_tree_tapbuf_size8_6_sram[1]:11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 3.288691e-06 +40 mux_tree_tapbuf_size8_6_sram[1]:18 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 2.707534e-05 +41 mux_tree_tapbuf_size8_6_sram[1]:14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 4.578255e-05 +42 mux_tree_tapbuf_size8_6_sram[1]:15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 2.707534e-05 +43 mux_tree_tapbuf_size8_6_sram[1]:20 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.925862e-05 +44 mux_tree_tapbuf_size8_6_sram[1]:21 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.925862e-05 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_6_sram[1]:32 0.152 +1 mux_tree_tapbuf_size8_6_sram[1]:27 mux_tree_tapbuf_size8_6_sram[1]:26 0.0045 +2 mux_tree_tapbuf_size8_6_sram[1]:27 mux_tree_tapbuf_size8_6_sram[1]:6 0.0001793478 +3 mux_tree_tapbuf_size8_6_sram[1]:26 mux_tree_tapbuf_size8_6_sram[1]:25 0.002044643 +4 mux_tree_tapbuf_size8_6_sram[1]:24 mux_tree_tapbuf_size8_6_sram[1]:23 0.0006919643 +5 mux_tree_tapbuf_size8_6_sram[1]:25 mux_tree_tapbuf_size8_6_sram[1]:24 0.0045 +6 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:9 0.001642857 +8 mux_tree_tapbuf_size8_6_sram[1]:12 mux_tree_tapbuf_size8_6_sram[1]:11 0.002044643 +9 mux_tree_tapbuf_size8_6_sram[1]:10 mux_bottom_ipin_14\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_6_sram[1]:11 mux_tree_tapbuf_size8_6_sram[1]:10 0.0045 +11 mux_tree_tapbuf_size8_6_sram[1]:20 mux_tree_tapbuf_size8_6_sram[1]:19 0.0045 +12 mux_tree_tapbuf_size8_6_sram[1]:19 mux_tree_tapbuf_size8_6_sram[1]:18 0.002691964 +13 mux_tree_tapbuf_size8_6_sram[1]:6 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size8_6_sram[1]:28 mux_tree_tapbuf_size8_6_sram[1]:27 0.003205357 +15 mux_tree_tapbuf_size8_6_sram[1]:29 mux_tree_tapbuf_size8_6_sram[1]:28 0.0045 +16 mux_tree_tapbuf_size8_6_sram[1]:31 mux_tree_tapbuf_size8_6_sram[1]:30 0.0045 +17 mux_tree_tapbuf_size8_6_sram[1]:30 mux_tree_tapbuf_size8_6_sram[1]:29 0.002348214 +18 mux_tree_tapbuf_size8_6_sram[1]:32 mux_tree_tapbuf_size8_6_sram[1]:31 0.001225446 +19 mux_tree_tapbuf_size8_6_sram[1]:17 mux_tree_tapbuf_size8_6_sram[1]:16 0.0001752718 +20 mux_tree_tapbuf_size8_6_sram[1]:18 mux_tree_tapbuf_size8_6_sram[1]:17 0.0045 +21 mux_tree_tapbuf_size8_6_sram[1]:18 mux_tree_tapbuf_size8_6_sram[1]:15 0.002388393 +22 mux_tree_tapbuf_size8_6_sram[1]:16 mux_bottom_ipin_14\/mux_l2_in_3_:S 0.152 +23 mux_tree_tapbuf_size8_6_sram[1]:22 mux_bottom_ipin_14\/mux_l2_in_2_:S 0.152 +24 mux_tree_tapbuf_size8_6_sram[1]:22 mux_tree_tapbuf_size8_6_sram[1]:21 0.0001715116 +25 mux_tree_tapbuf_size8_6_sram[1]:7 mux_bottom_ipin_14\/mux_l2_in_1_:S 0.152 +26 mux_tree_tapbuf_size8_6_sram[1]:14 mux_tree_tapbuf_size8_6_sram[1]:13 0.002013393 +27 mux_tree_tapbuf_size8_6_sram[1]:15 mux_tree_tapbuf_size8_6_sram[1]:14 0.0045 +28 mux_tree_tapbuf_size8_6_sram[1]:8 mux_tree_tapbuf_size8_6_sram[1]:7 0.0002879465 +29 mux_tree_tapbuf_size8_6_sram[1]:9 mux_tree_tapbuf_size8_6_sram[1]:8 0.0003035715 +30 mux_tree_tapbuf_size8_6_sram[1]:21 mux_tree_tapbuf_size8_6_sram[1]:20 0.002051339 +31 mux_tree_tapbuf_size8_6_sram[1]:23 mux_tree_tapbuf_size8_6_sram[1]:22 0.00034375 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006117587 //LENGTH 3.855 LUMPCC 0.0002902506 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_1_:X O *L 0 *C 25.475 55.420 +*I mux_bottom_ipin_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 21.910 55.420 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 21.948 55.420 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 25.438 55.420 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001597541 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001597541 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[11]:33 0.0001451253 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[11]:32 0.0001451253 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003116072 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009368614 //LENGTH 8.460 LUMPCC 0.000104761 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_3_:X O *L 0 *C 73.885 11.900 +*I mux_bottom_ipin_12\/mux_l3_in_1_:A0 I *L 0.001631 *C 82.055 11.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 82.017 11.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 73.922 11.900 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004150502 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0004150502 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_6_sram[2]:15 5.238051e-05 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_6_sram[2]:14 5.238051e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_3_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.007227679 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006449628 //LENGTH 4.550 LUMPCC 0.0001265258 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_2_:X O *L 0 *C 36.515 19.720 +*I mux_bottom_ipin_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 34.405 18.020 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 34.443 18.020 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 36.295 18.020 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 36.340 18.065 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 36.340 19.675 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 36.340 19.720 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 36.515 19.720 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.228363e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.228363e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001022819 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001022819 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.35429e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.376308e-05 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_0_sram[2]:11 4.846184e-05 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_0_sram[2]:10 4.846184e-05 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_0_sram[2]:9 1.467135e-05 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_0_sram[2]:15 1.29736e-07 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_0_sram[2]:8 1.467135e-05 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_0_sram[2]:14 1.29736e-07 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_2_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006815555 //LENGTH 5.760 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_2_:X O *L 0 *C 34.675 58.820 +*I mux_bottom_ipin_7\/mux_l3_in_1_:A1 I *L 0.00198 *C 32.565 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 32.602 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 33.075 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 33.120 61.495 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 33.120 58.865 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 33.165 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 34.638 58.820 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.466143e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.466143e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001664332 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001664332 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001086831 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001086831 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_2_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002022335 //LENGTH 11.305 LUMPCC 0.0007252585 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l1_in_0_:X O *L 0 *C 92.635 34.000 +*I mux_bottom_ipin_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.925 36.380 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.963 36.380 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.435 36.380 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.480 36.380 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.480 36.720 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 86.487 36.720 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 92.913 36.720 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 92.920 36.663 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 92.920 34.045 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 92.920 34.000 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 92.635 34.000 + +*CAP +0 mux_bottom_ipin_14\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.71579e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.71579e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.291741e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.685349e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003126806 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003126806 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001656108 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001656108 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.759911e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:11 5.680785e-05 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[4]:38 0.0003626293 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[4]:39 0.0003626293 + +*RES +0 mux_bottom_ipin_14\/mux_l1_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_14\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001634615 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001006583 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.002337054 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001548913 + +*END + +*D_NET chanx_left_out[10] 0.001007446 //LENGTH 7.360 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 7.095 8.840 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 9.520 +*N chanx_left_out[10]:2 *C 2.292 9.520 +*N chanx_left_out[10]:3 *C 2.300 9.463 +*N chanx_left_out[10]:4 *C 2.300 8.885 +*N chanx_left_out[10]:5 *C 2.345 8.840 +*N chanx_left_out[10]:6 *C 7.058 8.840 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 chanx_left_out[10] 0.0001238955 +2 chanx_left_out[10]:2 0.0001238955 +3 chanx_left_out[10]:3 5.535041e-05 +4 chanx_left_out[10]:4 5.535041e-05 +5 chanx_left_out[10]:5 0.0003239771 +6 chanx_left_out[10]:6 0.0003239771 + +*RES +0 ropt_mt_inst_730:X chanx_left_out[10]:6 0.152 +1 chanx_left_out[10]:6 chanx_left_out[10]:5 0.00420759 +2 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0045 +3 chanx_left_out[10]:4 chanx_left_out[10]:3 0.000515625 +4 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +5 chanx_left_out[10]:2 chanx_left_out[10] 0.0001664583 + +*END + +*D_NET chanx_left_out[12] 0.002291583 //LENGTH 13.160 LUMPCC 0.0006412528 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 4.140 71.400 +*P chanx_left_out[12] O *L 0.7423 *C 1.305 69.360 +*N chanx_left_out[12]:2 *C 1.380 68.680 +*N chanx_left_out[12]:3 *C 2.740 68.680 +*N chanx_left_out[12]:4 *C 2.760 68.688 +*N chanx_left_out[12]:5 *C 2.760 71.392 +*N chanx_left_out[12]:6 *C 2.780 71.400 +*N chanx_left_out[12]:7 *C 6.893 71.400 +*N chanx_left_out[12]:8 *C 6.900 71.400 +*N chanx_left_out[12]:9 *C 6.855 71.400 +*N chanx_left_out[12]:10 *C 4.178 71.400 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 chanx_left_out[12] 7.319915e-05 +2 chanx_left_out[12]:2 0.0002579542 +3 chanx_left_out[12]:3 0.0001847551 +4 chanx_left_out[12]:4 0.0001949927 +5 chanx_left_out[12]:5 0.0001949927 +6 chanx_left_out[12]:6 0.0001857439 +7 chanx_left_out[12]:7 0.0001857439 +8 chanx_left_out[12]:8 3.501039e-05 +9 chanx_left_out[12]:9 0.000168469 +10 chanx_left_out[12]:10 0.000168469 +11 chanx_left_out[12]:7 chanx_left_out[1]:2 0.0002495393 +12 chanx_left_out[12]:6 chanx_left_out[1] 0.0002495393 +13 chanx_left_out[12]:3 chanx_left_out[1]:2 2.264745e-06 +14 chanx_left_out[12]:2 chanx_left_out[1] 2.264745e-06 +15 chanx_left_out[12]:10 ropt_net_170:2 9.10767e-06 +16 chanx_left_out[12]:10 ropt_net_170:4 5.971464e-05 +17 chanx_left_out[12]:9 ropt_net_170:3 9.10767e-06 +18 chanx_left_out[12]:9 ropt_net_170:5 5.971464e-05 + +*RES +0 ropt_mt_inst_774:X chanx_left_out[12]:10 0.152 +1 chanx_left_out[12]:10 chanx_left_out[12]:9 0.002390625 +2 chanx_left_out[12]:9 chanx_left_out[12]:8 0.0045 +3 chanx_left_out[12]:8 chanx_left_out[12]:7 0.00341 +4 chanx_left_out[12]:7 chanx_left_out[12]:6 0.0006442916 +5 chanx_left_out[12]:6 chanx_left_out[12]:5 0.00341 +6 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0004237833 +7 chanx_left_out[12]:3 chanx_left_out[12]:2 0.0002130666 +8 chanx_left_out[12]:4 chanx_left_out[12]:3 0.00341 +9 chanx_left_out[12]:2 chanx_left_out[12] 0.0001065333 + +*END + +*D_NET chanx_right_out[16] 0.001527963 //LENGTH 11.995 LUMPCC 0.0001102644 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 92.655 3.740 +*P chanx_right_out[16] O *L 0.7423 *C 101.660 1.325 +*N chanx_right_out[16]:2 *C 101.660 3.740 +*N chanx_right_out[16]:3 *C 101.200 3.740 +*N chanx_right_out[16]:4 *C 101.155 3.740 +*N chanx_right_out[16]:5 *C 92.693 3.740 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 chanx_right_out[16] 0.000141261 +2 chanx_right_out[16]:2 0.0001725294 +3 chanx_right_out[16]:3 6.058968e-05 +4 chanx_right_out[16]:4 0.0005211591 +5 chanx_right_out[16]:5 0.0005211591 +6 chanx_right_out[16]:5 ropt_net_184:3 5.513222e-05 +7 chanx_right_out[16]:4 ropt_net_184:4 5.513222e-05 + +*RES +0 ropt_mt_inst_757:X chanx_right_out[16]:5 0.152 +1 chanx_right_out[16]:5 chanx_right_out[16]:4 0.007555804 +2 chanx_right_out[16]:4 chanx_right_out[16]:3 0.0045 +3 chanx_right_out[16]:3 chanx_right_out[16]:2 0.0004107143 +4 chanx_right_out[16]:2 chanx_right_out[16] 0.00215625 + +*END + +*D_NET ropt_net_158 0.000415958 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I BUFT_P_97:X O *L 0 *C 89.700 6.120 +*I ropt_mt_inst_757:A I *L 0.001766 *C 88.780 4.080 +*N ropt_net_158:2 *C 88.818 4.080 +*N ropt_net_158:3 *C 89.655 4.080 +*N ropt_net_158:4 *C 89.700 4.125 +*N ropt_net_158:5 *C 89.700 6.075 +*N ropt_net_158:6 *C 89.700 6.120 + +*CAP +0 BUFT_P_97:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_158:2 6.218592e-05 +3 ropt_net_158:3 6.218592e-05 +4 ropt_net_158:4 0.0001301726 +5 ropt_net_158:5 0.0001301726 +6 ropt_net_158:6 2.924101e-05 + +*RES +0 BUFT_P_97:X ropt_net_158:6 0.152 +1 ropt_net_158:6 ropt_net_158:5 0.0045 +2 ropt_net_158:5 ropt_net_158:4 0.001741071 +3 ropt_net_158:3 ropt_net_158:2 0.0007477679 +4 ropt_net_158:4 ropt_net_158:3 0.0045 +5 ropt_net_158:2 ropt_mt_inst_757:A 0.152 + +*END + +*D_NET ropt_net_153 0.001464491 //LENGTH 12.170 LUMPCC 0 DR + +*CONN +*I BUFT_P_119:X O *L 0 *C 12.420 10.200 +*I ropt_mt_inst_750:A I *L 0.001766 *C 3.220 12.240 +*N ropt_net_153:2 *C 3.258 12.240 +*N ropt_net_153:3 *C 4.095 12.240 +*N ropt_net_153:4 *C 4.140 12.195 +*N ropt_net_153:5 *C 4.140 10.245 +*N ropt_net_153:6 *C 4.185 10.200 +*N ropt_net_153:7 *C 12.383 10.200 + +*CAP +0 BUFT_P_119:X 1e-06 +1 ropt_mt_inst_750:A 1e-06 +2 ropt_net_153:2 6.502953e-05 +3 ropt_net_153:3 6.502953e-05 +4 ropt_net_153:4 0.0001250826 +5 ropt_net_153:5 0.0001250826 +6 ropt_net_153:6 0.0005411335 +7 ropt_net_153:7 0.0005411335 + +*RES +0 BUFT_P_119:X ropt_net_153:7 0.152 +1 ropt_net_153:7 ropt_net_153:6 0.007319197 +2 ropt_net_153:6 ropt_net_153:5 0.0045 +3 ropt_net_153:5 ropt_net_153:4 0.001741072 +4 ropt_net_153:3 ropt_net_153:2 0.0007477679 +5 ropt_net_153:4 ropt_net_153:3 0.0045 +6 ropt_net_153:2 ropt_mt_inst_750:A 0.152 + +*END + +*D_NET chanx_left_in[3] 0.0256176 //LENGTH 178.435 LUMPCC 0.007833831 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 46.920 +*I mux_bottom_ipin_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.350 48.280 +*I mux_bottom_ipin_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 31.915 49.640 +*I mux_bottom_ipin_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 27.045 56.100 +*I mux_bottom_ipin_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 36.170 55.080 +*I mux_bottom_ipin_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 58.420 52.700 +*I mux_bottom_ipin_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.770 60.520 +*I mux_bottom_ipin_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 64.765 47.260 +*I ropt_mt_inst_739:A I *L 0.001767 *C 93.380 14.960 +*I mux_bottom_ipin_13\/mux_l1_in_1_:A1 I *L 0.00198 *C 86.480 50.660 +*N chanx_left_in[3]:10 *C 86.480 50.660 +*N chanx_left_in[3]:11 *C 86.480 50.660 +*N chanx_left_in[3]:12 *C 86.480 51.000 +*N chanx_left_in[3]:13 *C 86.473 51.000 +*N chanx_left_in[3]:14 *C 93.380 14.975 +*N chanx_left_in[3]:15 *C 93.380 15.300 +*N chanx_left_in[3]:16 *C 93.380 15.345 +*N chanx_left_in[3]:17 *C 93.380 23.075 +*N chanx_left_in[3]:18 *C 93.335 23.120 +*N chanx_left_in[3]:19 *C 91.125 23.120 +*N chanx_left_in[3]:20 *C 91.080 23.165 +*N chanx_left_in[3]:21 *C 91.080 23.742 +*N chanx_left_in[3]:22 *C 91.073 23.800 +*N chanx_left_in[3]:23 *C 83.740 23.800 +*N chanx_left_in[3]:24 *C 83.720 23.808 +*N chanx_left_in[3]:25 *C 83.720 50.992 +*N chanx_left_in[3]:26 *C 83.720 51.000 +*N chanx_left_in[3]:27 *C 64.803 47.260 +*N chanx_left_in[3]:28 *C 65.275 47.260 +*N chanx_left_in[3]:29 *C 65.320 47.305 +*N chanx_left_in[3]:30 *C 65.320 50.943 +*N chanx_left_in[3]:31 *C 63.770 60.520 +*N chanx_left_in[3]:32 *C 63.940 60.520 +*N chanx_left_in[3]:33 *C 63.940 60.520 +*N chanx_left_in[3]:34 *C 63.948 60.520 +*N chanx_left_in[3]:35 *C 65.300 60.520 +*N chanx_left_in[3]:36 *C 65.320 60.513 +*N chanx_left_in[3]:37 *C 65.320 51.008 +*N chanx_left_in[3]:38 *C 65.320 51.000 +*N chanx_left_in[3]:39 *C 58.420 52.700 +*N chanx_left_in[3]:40 *C 58.420 53.040 +*N chanx_left_in[3]:41 *C 58.835 53.040 +*N chanx_left_in[3]:42 *C 58.880 52.995 +*N chanx_left_in[3]:43 *C 58.880 51.058 +*N chanx_left_in[3]:44 *C 58.880 51.000 +*N chanx_left_in[3]:45 *C 52.460 51.000 +*N chanx_left_in[3]:46 *C 52.440 51.008 +*N chanx_left_in[3]:47 *C 52.440 54.393 +*N chanx_left_in[3]:48 *C 52.420 54.400 +*N chanx_left_in[3]:49 *C 36.808 54.400 +*N chanx_left_in[3]:50 *C 36.800 54.458 +*N chanx_left_in[3]:51 *C 36.208 55.080 +*N chanx_left_in[3]:52 *C 36.755 55.080 +*N chanx_left_in[3]:53 *C 36.800 55.080 +*N chanx_left_in[3]:54 *C 36.800 56.395 +*N chanx_left_in[3]:55 *C 36.755 56.440 +*N chanx_left_in[3]:56 *C 27.140 56.440 +*N chanx_left_in[3]:57 *C 27.045 56.100 +*N chanx_left_in[3]:58 *C 27.140 56.055 +*N chanx_left_in[3]:59 *C 31.878 49.640 +*N chanx_left_in[3]:60 *C 27.185 49.640 +*N chanx_left_in[3]:61 *C 27.140 49.640 +*N chanx_left_in[3]:62 *C 28.312 48.280 +*N chanx_left_in[3]:63 *C 27.185 48.280 +*N chanx_left_in[3]:64 *C 27.140 48.280 +*N chanx_left_in[3]:65 *C 27.140 46.977 +*N chanx_left_in[3]:66 *C 27.133 46.920 + +*CAP +0 chanx_left_in[3] 0.00123722 +1 mux_bottom_ipin_11\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_ipin_9\/mux_l1_in_1_:A1 1e-06 +4 mux_bottom_ipin_7\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_ipin_5\/mux_l1_in_1_:A1 1e-06 +6 mux_bottom_ipin_15\/mux_l2_in_0_:A0 1e-06 +7 mux_bottom_ipin_1\/mux_l1_in_1_:A1 1e-06 +8 ropt_mt_inst_739:A 1e-06 +9 mux_bottom_ipin_13\/mux_l1_in_1_:A1 1e-06 +10 chanx_left_in[3]:10 3.302816e-05 +11 chanx_left_in[3]:11 5.15705e-05 +12 chanx_left_in[3]:12 5.542619e-05 +13 chanx_left_in[3]:13 0.0001026879 +14 chanx_left_in[3]:14 3.688517e-05 +15 chanx_left_in[3]:15 7.107731e-05 +16 chanx_left_in[3]:16 0.0004123846 +17 chanx_left_in[3]:17 0.0004123846 +18 chanx_left_in[3]:18 0.0001322728 +19 chanx_left_in[3]:19 0.0001322728 +20 chanx_left_in[3]:20 4.55083e-05 +21 chanx_left_in[3]:21 4.55083e-05 +22 chanx_left_in[3]:22 0.0005777089 +23 chanx_left_in[3]:23 0.0005777089 +24 chanx_left_in[3]:24 0.001101073 +25 chanx_left_in[3]:25 0.001101073 +26 chanx_left_in[3]:26 0.0007081617 +27 chanx_left_in[3]:27 5.396979e-05 +28 chanx_left_in[3]:28 5.396979e-05 +29 chanx_left_in[3]:29 0.0001582298 +30 chanx_left_in[3]:30 0.0001582298 +31 chanx_left_in[3]:31 4.878025e-05 +32 chanx_left_in[3]:32 5.295402e-05 +33 chanx_left_in[3]:33 3.851421e-05 +34 chanx_left_in[3]:34 0.0001742419 +35 chanx_left_in[3]:35 0.0001742419 +36 chanx_left_in[3]:36 0.0006218318 +37 chanx_left_in[3]:37 0.0006218318 +38 chanx_left_in[3]:38 0.0008625794 +39 chanx_left_in[3]:39 5.752353e-05 +40 chanx_left_in[3]:40 5.134739e-05 +41 chanx_left_in[3]:41 2.306473e-05 +42 chanx_left_in[3]:42 9.585751e-05 +43 chanx_left_in[3]:43 9.585751e-05 +44 chanx_left_in[3]:44 0.0006618223 +45 chanx_left_in[3]:45 0.0004047166 +46 chanx_left_in[3]:46 0.0002417116 +47 chanx_left_in[3]:47 0.0002417116 +48 chanx_left_in[3]:48 0.0004616766 +49 chanx_left_in[3]:49 0.0004616766 +50 chanx_left_in[3]:50 4.714308e-05 +51 chanx_left_in[3]:51 6.154954e-05 +52 chanx_left_in[3]:52 6.154954e-05 +53 chanx_left_in[3]:53 0.0001644573 +54 chanx_left_in[3]:54 8.333775e-05 +55 chanx_left_in[3]:55 0.0006796145 +56 chanx_left_in[3]:56 0.0007101452 +57 chanx_left_in[3]:57 6.323334e-05 +58 chanx_left_in[3]:58 0.0004120545 +59 chanx_left_in[3]:59 0.0002833803 +60 chanx_left_in[3]:60 0.0002833803 +61 chanx_left_in[3]:61 0.0005174873 +62 chanx_left_in[3]:62 0.0001205147 +63 chanx_left_in[3]:63 0.0001205147 +64 chanx_left_in[3]:64 0.0001950592 +65 chanx_left_in[3]:65 8.38378e-05 +66 chanx_left_in[3]:66 0.00123722 +67 chanx_left_in[3] chanx_left_in[5] 7.020996e-06 +68 chanx_left_in[3] chanx_left_in[5]:24 0.0005056619 +69 chanx_left_in[3] chanx_left_in[5]:28 2.465308e-05 +70 chanx_left_in[3]:26 chanx_left_in[5]:10 6.013508e-05 +71 chanx_left_in[3]:26 chanx_left_in[5]:9 0.0003786061 +72 chanx_left_in[3]:13 chanx_left_in[5]:9 6.013508e-05 +73 chanx_left_in[3]:44 chanx_left_in[5]:22 2.872433e-06 +74 chanx_left_in[3]:44 chanx_left_in[5]:10 5.087818e-05 +75 chanx_left_in[3]:44 chanx_left_in[5]:23 3.286864e-07 +76 chanx_left_in[3]:38 chanx_left_in[5]:16 2.41513e-06 +77 chanx_left_in[3]:38 chanx_left_in[5]:22 3.286864e-07 +78 chanx_left_in[3]:38 chanx_left_in[5]:10 0.0003786061 +79 chanx_left_in[3]:38 chanx_left_in[5]:9 5.087818e-05 +80 chanx_left_in[3]:45 chanx_left_in[5]:23 4.573027e-07 +81 chanx_left_in[3]:66 chanx_left_in[5]:27 2.465308e-05 +82 chanx_left_in[3]:66 chanx_left_in[5]:29 7.020996e-06 +83 chanx_left_in[3]:66 chanx_left_in[5]:23 0.0005056619 +84 chanx_left_in[3] chanx_left_in[11] 8.145189e-07 +85 chanx_left_in[3]:26 chanx_left_in[11]:18 1.520618e-06 +86 chanx_left_in[3]:25 chanx_left_in[11]:17 0.0003053746 +87 chanx_left_in[3]:24 chanx_left_in[11]:16 0.0003053746 +88 chanx_left_in[3]:43 chanx_left_in[11]:26 8.88563e-06 +89 chanx_left_in[3]:44 chanx_left_in[11]:18 4.95441e-06 +90 chanx_left_in[3]:44 chanx_left_in[11]:27 0.0001174103 +91 chanx_left_in[3]:42 chanx_left_in[11]:25 8.88563e-06 +92 chanx_left_in[3]:38 chanx_left_in[11]:18 4.346153e-05 +93 chanx_left_in[3]:38 chanx_left_in[11]:27 1.520618e-06 +94 chanx_left_in[3]:49 chanx_left_in[11]:28 0.0002641853 +95 chanx_left_in[3]:48 chanx_left_in[11]:27 0.0002641853 +96 chanx_left_in[3]:45 chanx_left_in[11]:28 7.39488e-05 +97 chanx_left_in[3]:45 chanx_left_in[11]:27 4.95441e-06 +98 chanx_left_in[3]:66 chanx_left_in[11]:36 8.145189e-07 +99 chanx_left_in[3]:25 chanx_left_in[19]:15 0.0003053746 +100 chanx_left_in[3]:24 chanx_left_in[19]:14 0.0003053746 +101 chanx_left_in[3]:60 chanx_right_in[1]:25 0.0001000932 +102 chanx_left_in[3]:59 chanx_right_in[1]:26 0.0001000932 +103 chanx_left_in[3]:49 chanx_right_in[1]:33 0.0005017954 +104 chanx_left_in[3]:48 chanx_right_in[1]:37 0.0005017954 +105 chanx_left_in[3]:55 chanx_right_in[3]:41 3.002703e-05 +106 chanx_left_in[3]:55 chanx_right_in[3]:15 1.827865e-05 +107 chanx_left_in[3]:26 chanx_right_in[3]:56 5.68817e-05 +108 chanx_left_in[3]:26 chanx_right_in[3]:60 0.0004085833 +109 chanx_left_in[3]:13 chanx_right_in[3]:60 5.68817e-05 +110 chanx_left_in[3]:13 chanx_right_in[3]:61 3.253376e-06 +111 chanx_left_in[3]:43 chanx_right_in[3]:50 6.142675e-05 +112 chanx_left_in[3]:44 chanx_right_in[3]:51 0.0001127053 +113 chanx_left_in[3]:44 chanx_right_in[3]:56 9.494509e-06 +114 chanx_left_in[3]:41 chanx_right_in[3]:48 2.50646e-05 +115 chanx_left_in[3]:42 chanx_right_in[3]:49 6.142675e-05 +116 chanx_left_in[3]:38 chanx_right_in[3]:56 0.0005180353 +117 chanx_left_in[3]:38 chanx_right_in[3]:60 9.494509e-06 +118 chanx_left_in[3]:49 chanx_right_in[3]:44 0.0001547537 +119 chanx_left_in[3]:48 chanx_right_in[3]:45 0.0001547537 +120 chanx_left_in[3]:30 chanx_right_in[3]:55 4.364934e-05 +121 chanx_left_in[3]:28 chanx_right_in[3]:52 2.350143e-06 +122 chanx_left_in[3]:29 chanx_right_in[3]:54 4.364934e-05 +123 chanx_left_in[3]:27 chanx_right_in[3]:53 2.350143e-06 +124 chanx_left_in[3]:56 chanx_right_in[3]:43 1.827865e-05 +125 chanx_left_in[3]:56 chanx_right_in[3]:40 3.002703e-05 +126 chanx_left_in[3]:40 chanx_right_in[3]:47 2.50646e-05 +127 chanx_left_in[3] prog_clk[0]:332 1.735274e-05 +128 chanx_left_in[3] prog_clk[0]:366 3.644382e-05 +129 chanx_left_in[3] prog_clk[0]:365 0.0001026419 +130 chanx_left_in[3] prog_clk[0]:327 3.258011e-05 +131 chanx_left_in[3]:54 prog_clk[0]:167 6.136087e-07 +132 chanx_left_in[3]:53 prog_clk[0]:167 6.318709e-07 +133 chanx_left_in[3]:53 prog_clk[0]:168 6.136087e-07 +134 chanx_left_in[3]:50 prog_clk[0]:168 6.318709e-07 +135 chanx_left_in[3]:49 prog_clk[0]:194 0.0001204219 +136 chanx_left_in[3]:48 prog_clk[0]:193 0.0001204219 +137 chanx_left_in[3]:30 prog_clk[0]:257 4.244976e-05 +138 chanx_left_in[3]:29 prog_clk[0]:258 4.244976e-05 +139 chanx_left_in[3]:66 prog_clk[0]:332 0.0001026419 +140 chanx_left_in[3]:66 prog_clk[0]:322 3.258011e-05 +141 chanx_left_in[3]:66 prog_clk[0]:365 3.644382e-05 +142 chanx_left_in[3]:66 prog_clk[0]:327 1.735274e-05 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:66 0.004058058 +1 chanx_left_in[3]:55 chanx_left_in[3]:54 0.0045 +2 chanx_left_in[3]:54 chanx_left_in[3]:53 0.001174107 +3 chanx_left_in[3]:26 chanx_left_in[3]:25 0.00341 +4 chanx_left_in[3]:26 chanx_left_in[3]:13 0.000431225 +5 chanx_left_in[3]:25 chanx_left_in[3]:24 0.004258983 +6 chanx_left_in[3]:23 chanx_left_in[3]:22 0.001148758 +7 chanx_left_in[3]:24 chanx_left_in[3]:23 0.00341 +8 chanx_left_in[3]:21 chanx_left_in[3]:20 0.000515625 +9 chanx_left_in[3]:22 chanx_left_in[3]:21 0.00341 +10 chanx_left_in[3]:19 chanx_left_in[3]:18 0.001973214 +11 chanx_left_in[3]:20 chanx_left_in[3]:19 0.0045 +12 chanx_left_in[3]:18 chanx_left_in[3]:17 0.0045 +13 chanx_left_in[3]:17 chanx_left_in[3]:16 0.006901786 +14 chanx_left_in[3]:15 chanx_left_in[3]:14 0.0001766305 +15 chanx_left_in[3]:16 chanx_left_in[3]:15 0.0045 +16 chanx_left_in[3]:14 ropt_mt_inst_739:A 0.152 +17 chanx_left_in[3]:12 chanx_left_in[3]:11 0.0001634615 +18 chanx_left_in[3]:13 chanx_left_in[3]:12 0.00341 +19 chanx_left_in[3]:10 mux_bottom_ipin_13\/mux_l1_in_1_:A1 0.152 +20 chanx_left_in[3]:11 chanx_left_in[3]:10 0.0045 +21 chanx_left_in[3]:57 mux_bottom_ipin_9\/mux_l1_in_1_:A1 0.152 +22 chanx_left_in[3]:57 chanx_left_in[3]:56 0.0003035715 +23 chanx_left_in[3]:58 chanx_left_in[3]:57 0.0045 +24 chanx_left_in[3]:52 chanx_left_in[3]:51 0.0004888393 +25 chanx_left_in[3]:53 chanx_left_in[3]:52 0.0045 +26 chanx_left_in[3]:53 chanx_left_in[3]:50 0.0005558036 +27 chanx_left_in[3]:51 mux_bottom_ipin_7\/mux_l2_in_0_:A0 0.152 +28 chanx_left_in[3]:43 chanx_left_in[3]:42 0.001729911 +29 chanx_left_in[3]:44 chanx_left_in[3]:43 0.00341 +30 chanx_left_in[3]:44 chanx_left_in[3]:38 0.001008933 +31 chanx_left_in[3]:41 chanx_left_in[3]:40 0.0003705357 +32 chanx_left_in[3]:42 chanx_left_in[3]:41 0.0045 +33 chanx_left_in[3]:39 mux_bottom_ipin_5\/mux_l1_in_1_:A1 0.152 +34 chanx_left_in[3]:60 chanx_left_in[3]:59 0.004189732 +35 chanx_left_in[3]:61 chanx_left_in[3]:60 0.0045 +36 chanx_left_in[3]:61 chanx_left_in[3]:58 0.005727679 +37 chanx_left_in[3]:59 mux_bottom_ipin_3\/mux_l2_in_0_:A0 0.152 +38 chanx_left_in[3]:38 chanx_left_in[3]:37 0.00341 +39 chanx_left_in[3]:38 chanx_left_in[3]:30 0.00341 +40 chanx_left_in[3]:38 chanx_left_in[3]:26 0.002882667 +41 chanx_left_in[3]:37 chanx_left_in[3]:36 0.001489117 +42 chanx_left_in[3]:35 chanx_left_in[3]:34 0.0002118916 +43 chanx_left_in[3]:36 chanx_left_in[3]:35 0.00341 +44 chanx_left_in[3]:33 chanx_left_in[3]:32 0.0045 +45 chanx_left_in[3]:34 chanx_left_in[3]:33 0.00341 +46 chanx_left_in[3]:32 chanx_left_in[3]:31 9.239131e-05 +47 chanx_left_in[3]:31 mux_bottom_ipin_15\/mux_l2_in_0_:A0 0.152 +48 chanx_left_in[3]:50 chanx_left_in[3]:49 0.00341 +49 chanx_left_in[3]:49 chanx_left_in[3]:48 0.002445958 +50 chanx_left_in[3]:48 chanx_left_in[3]:47 0.00341 +51 chanx_left_in[3]:47 chanx_left_in[3]:46 0.0005303166 +52 chanx_left_in[3]:45 chanx_left_in[3]:44 0.0010058 +53 chanx_left_in[3]:46 chanx_left_in[3]:45 0.00341 +54 chanx_left_in[3]:30 chanx_left_in[3]:29 0.003247768 +55 chanx_left_in[3]:28 chanx_left_in[3]:27 0.000421875 +56 chanx_left_in[3]:29 chanx_left_in[3]:28 0.0045 +57 chanx_left_in[3]:27 mux_bottom_ipin_1\/mux_l1_in_1_:A1 0.152 +58 chanx_left_in[3]:63 chanx_left_in[3]:62 0.001006696 +59 chanx_left_in[3]:64 chanx_left_in[3]:63 0.0045 +60 chanx_left_in[3]:64 chanx_left_in[3]:61 0.001214286 +61 chanx_left_in[3]:62 mux_bottom_ipin_11\/mux_l2_in_0_:A0 0.152 +62 chanx_left_in[3]:65 chanx_left_in[3]:64 0.001162947 +63 chanx_left_in[3]:66 chanx_left_in[3]:65 0.00341 +64 chanx_left_in[3]:56 chanx_left_in[3]:55 0.008584822 +65 chanx_left_in[3]:40 chanx_left_in[3]:39 0.0003035715 + +*END + +*D_NET chanx_right_in[4] 0.02283234 //LENGTH 161.435 LUMPCC 0.005751321 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 103.650 53.040 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 66.990 33.660 +*I mux_bottom_ipin_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 49.855 33.660 +*I ropt_mt_inst_725:A I *L 0.001766 *C 10.580 66.640 +*N chanx_right_in[4]:4 *C 10.543 66.640 +*N chanx_right_in[4]:5 *C 6.885 66.640 +*N chanx_right_in[4]:6 *C 6.840 66.640 +*N chanx_right_in[4]:7 *C 6.848 66.640 +*N chanx_right_in[4]:8 *C 12.873 66.640 +*N chanx_right_in[4]:9 *C 12.880 66.583 +*N chanx_right_in[4]:10 *C 12.880 63.625 +*N chanx_right_in[4]:11 *C 12.925 63.580 +*N chanx_right_in[4]:12 *C 22.495 63.580 +*N chanx_right_in[4]:13 *C 22.540 63.535 +*N chanx_right_in[4]:14 *C 22.540 58.185 +*N chanx_right_in[4]:15 *C 22.585 58.140 +*N chanx_right_in[4]:16 *C 26.220 58.140 +*N chanx_right_in[4]:17 *C 26.145 57.800 +*N chanx_right_in[4]:18 *C 26.213 57.845 +*N chanx_right_in[4]:19 *C 26.220 58.435 +*N chanx_right_in[4]:20 *C 26.265 58.480 +*N chanx_right_in[4]:21 *C 27.555 58.480 +*N chanx_right_in[4]:22 *C 27.600 58.435 +*N chanx_right_in[4]:23 *C 27.600 50.378 +*N chanx_right_in[4]:24 *C 27.608 50.320 +*N chanx_right_in[4]:25 *C 49.660 50.320 +*N chanx_right_in[4]:26 *C 49.680 50.312 +*N chanx_right_in[4]:27 *C 49.680 35.367 +*N chanx_right_in[4]:28 *C 49.855 33.660 +*N chanx_right_in[4]:29 *C 49.680 33.660 +*N chanx_right_in[4]:30 *C 49.680 33.705 +*N chanx_right_in[4]:31 *C 49.680 35.303 +*N chanx_right_in[4]:32 *C 49.688 35.360 +*N chanx_right_in[4]:33 *C 67.028 33.660 +*N chanx_right_in[4]:34 *C 67.575 33.660 +*N chanx_right_in[4]:35 *C 67.620 33.705 +*N chanx_right_in[4]:36 *C 67.620 35.303 +*N chanx_right_in[4]:37 *C 67.620 35.367 +*N chanx_right_in[4]:38 *C 67.620 36.040 +*N chanx_right_in[4]:39 *C 95.660 36.040 +*N chanx_right_in[4]:40 *C 95.680 36.047 +*N chanx_right_in[4]:41 *C 95.680 53.033 +*N chanx_right_in[4]:42 *C 95.700 53.040 + +*CAP +0 chanx_right_in[4] 0.0005661893 +1 mux_bottom_ipin_0\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_ipin_4\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_725:A 1e-06 +4 chanx_right_in[4]:4 0.0001699036 +5 chanx_right_in[4]:5 0.0001699036 +6 chanx_right_in[4]:6 3.616973e-05 +7 chanx_right_in[4]:7 0.0002494177 +8 chanx_right_in[4]:8 0.0002494177 +9 chanx_right_in[4]:9 0.0001748643 +10 chanx_right_in[4]:10 0.0001748643 +11 chanx_right_in[4]:11 0.0005416945 +12 chanx_right_in[4]:12 0.0005416945 +13 chanx_right_in[4]:13 0.0003343844 +14 chanx_right_in[4]:14 0.0003343844 +15 chanx_right_in[4]:15 0.0002202357 +16 chanx_right_in[4]:16 0.000248934 +17 chanx_right_in[4]:17 6.190365e-05 +18 chanx_right_in[4]:18 5.24307e-05 +19 chanx_right_in[4]:19 5.24307e-05 +20 chanx_right_in[4]:20 0.0001267555 +21 chanx_right_in[4]:21 0.0001267555 +22 chanx_right_in[4]:22 0.0004817898 +23 chanx_right_in[4]:23 0.0004817898 +24 chanx_right_in[4]:24 0.001289219 +25 chanx_right_in[4]:25 0.001289219 +26 chanx_right_in[4]:26 0.000915613 +27 chanx_right_in[4]:27 0.000915613 +28 chanx_right_in[4]:28 5.326237e-05 +29 chanx_right_in[4]:29 5.711715e-05 +30 chanx_right_in[4]:30 0.0001112057 +31 chanx_right_in[4]:31 0.0001112057 +32 chanx_right_in[4]:32 0.0007545532 +33 chanx_right_in[4]:33 6.951328e-05 +34 chanx_right_in[4]:34 6.951328e-05 +35 chanx_right_in[4]:35 0.0001030314 +36 chanx_right_in[4]:36 0.0001030314 +37 chanx_right_in[4]:37 0.0007941836 +38 chanx_right_in[4]:38 0.001339527 +39 chanx_right_in[4]:39 0.001299897 +40 chanx_right_in[4]:40 0.0009201058 +41 chanx_right_in[4]:41 0.0009201058 +42 chanx_right_in[4]:42 0.0005661893 +43 chanx_right_in[4]:32 chanx_left_in[7]:16 0.0008340328 +44 chanx_right_in[4]:37 chanx_left_in[7]:15 0.0008340328 +45 chanx_right_in[4]:39 chanx_left_in[7]:14 0.0001777615 +46 chanx_right_in[4]:39 chanx_left_in[7]:15 0.000286994 +47 chanx_right_in[4]:38 chanx_left_in[7]:15 0.0001777615 +48 chanx_right_in[4]:38 chanx_left_in[7]:16 0.000286994 +49 chanx_right_in[4]:25 chanx_right_in[5]:15 0.0003704122 +50 chanx_right_in[4]:24 chanx_right_in[5]:14 0.0003704122 +51 chanx_right_in[4]:39 chanx_right_in[5]:29 2.964545e-05 +52 chanx_right_in[4]:38 chanx_right_in[5]:28 2.964545e-05 +53 chanx_right_in[4]:31 prog_clk[0]:272 2.93725e-06 +54 chanx_right_in[4]:32 prog_clk[0]:271 0.0001449644 +55 chanx_right_in[4]:32 prog_clk[0]:270 4.039907e-05 +56 chanx_right_in[4]:30 prog_clk[0]:273 2.93725e-06 +57 chanx_right_in[4]:36 prog_clk[0]:79 4.573759e-06 +58 chanx_right_in[4]:37 prog_clk[0]:270 0.0001449644 +59 chanx_right_in[4]:37 prog_clk[0]:214 4.039907e-05 +60 chanx_right_in[4]:37 prog_clk[0]:83 8.27439e-06 +61 chanx_right_in[4]:35 prog_clk[0]:83 4.573759e-06 +62 chanx_right_in[4]:12 prog_clk[0]:346 1.066482e-05 +63 chanx_right_in[4]:12 prog_clk[0]:351 8.328015e-06 +64 chanx_right_in[4]:11 prog_clk[0]:351 1.066482e-05 +65 chanx_right_in[4]:11 prog_clk[0]:352 8.328015e-06 +66 chanx_right_in[4]:10 prog_clk[0]:350 2.536302e-05 +67 chanx_right_in[4]:9 prog_clk[0]:349 2.536302e-05 +68 chanx_right_in[4]:39 prog_clk[0]:77 7.170039e-05 +69 chanx_right_in[4]:38 prog_clk[0]:79 8.27439e-06 +70 chanx_right_in[4]:38 prog_clk[0]:78 7.170039e-05 +71 chanx_right_in[4]:23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.406293e-05 +72 chanx_right_in[4]:22 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.406293e-05 +73 chanx_right_in[4]:39 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003626293 +74 chanx_right_in[4]:38 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003626293 +75 chanx_right_in[4]:5 ropt_net_173:5 6.955155e-05 +76 chanx_right_in[4]:4 ropt_net_173:6 6.955155e-05 +77 chanx_right_in[4]:8 mem_bottom_ipin_15/net_net_75:7 0.0003533658 +78 chanx_right_in[4]:7 mem_bottom_ipin_15/net_net_75:6 0.0003533658 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:42 0.0012455 +1 chanx_right_in[4]:31 chanx_right_in[4]:30 0.001426339 +2 chanx_right_in[4]:32 chanx_right_in[4]:31 0.00341 +3 chanx_right_in[4]:32 chanx_right_in[4]:27 0.00341 +4 chanx_right_in[4]:29 chanx_right_in[4]:28 9.51087e-05 +5 chanx_right_in[4]:30 chanx_right_in[4]:29 0.0045 +6 chanx_right_in[4]:28 mux_bottom_ipin_4\/mux_l1_in_2_:A0 0.152 +7 chanx_right_in[4]:36 chanx_right_in[4]:35 0.001426339 +8 chanx_right_in[4]:37 chanx_right_in[4]:36 0.00341 +9 chanx_right_in[4]:37 chanx_right_in[4]:32 0.002809425 +10 chanx_right_in[4]:34 chanx_right_in[4]:33 0.0004888393 +11 chanx_right_in[4]:35 chanx_right_in[4]:34 0.0045 +12 chanx_right_in[4]:33 mux_bottom_ipin_0\/mux_l1_in_2_:A0 0.152 +13 chanx_right_in[4]:27 chanx_right_in[4]:26 0.002341383 +14 chanx_right_in[4]:25 chanx_right_in[4]:24 0.003454891 +15 chanx_right_in[4]:26 chanx_right_in[4]:25 0.00341 +16 chanx_right_in[4]:23 chanx_right_in[4]:22 0.007194196 +17 chanx_right_in[4]:24 chanx_right_in[4]:23 0.00341 +18 chanx_right_in[4]:21 chanx_right_in[4]:20 0.001151786 +19 chanx_right_in[4]:22 chanx_right_in[4]:21 0.0045 +20 chanx_right_in[4]:20 chanx_right_in[4]:19 0.0045 +21 chanx_right_in[4]:19 chanx_right_in[4]:18 0.0005267857 +22 chanx_right_in[4]:17 chanx_right_in[4]:16 0.0003035715 +23 chanx_right_in[4]:18 chanx_right_in[4]:17 0.0045 +24 chanx_right_in[4]:15 chanx_right_in[4]:14 0.0045 +25 chanx_right_in[4]:14 chanx_right_in[4]:13 0.004776786 +26 chanx_right_in[4]:12 chanx_right_in[4]:11 0.008544643 +27 chanx_right_in[4]:13 chanx_right_in[4]:12 0.0045 +28 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0045 +29 chanx_right_in[4]:10 chanx_right_in[4]:9 0.002640625 +30 chanx_right_in[4]:9 chanx_right_in[4]:8 0.00341 +31 chanx_right_in[4]:8 chanx_right_in[4]:7 0.0009439166 +32 chanx_right_in[4]:6 chanx_right_in[4]:5 0.0045 +33 chanx_right_in[4]:7 chanx_right_in[4]:6 0.00341 +34 chanx_right_in[4]:5 chanx_right_in[4]:4 0.003265625 +35 chanx_right_in[4]:4 ropt_mt_inst_725:A 0.152 +36 chanx_right_in[4]:39 chanx_right_in[4]:38 0.004392933 +37 chanx_right_in[4]:40 chanx_right_in[4]:39 0.00341 +38 chanx_right_in[4]:42 chanx_right_in[4]:41 0.00341 +39 chanx_right_in[4]:41 chanx_right_in[4]:40 0.002660983 +40 chanx_right_in[4]:16 chanx_right_in[4]:15 0.003245536 +41 chanx_right_in[4]:38 chanx_right_in[4]:37 0.0001053583 + +*END + +*D_NET chanx_right_in[9] 0.01893374 //LENGTH 128.625 LUMPCC 0.006637915 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 103.650 42.160 +*I mux_bottom_ipin_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 56.120 39.780 +*I ropt_mt_inst_736:A I *L 0.001767 *C 3.220 25.840 +*I mux_bottom_ipin_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 13.975 44.540 +*N chanx_right_in[9]:4 *C 13.975 44.540 +*N chanx_right_in[9]:5 *C 13.800 44.540 +*N chanx_right_in[9]:6 *C 13.800 44.495 +*N chanx_right_in[9]:7 *C 3.220 25.840 +*N chanx_right_in[9]:8 *C 1.885 25.840 +*N chanx_right_in[9]:9 *C 1.840 25.885 +*N chanx_right_in[9]:10 *C 1.840 34.295 +*N chanx_right_in[9]:11 *C 1.885 34.340 +*N chanx_right_in[9]:12 *C 11.960 34.340 +*N chanx_right_in[9]:13 *C 11.960 34.000 +*N chanx_right_in[9]:14 *C 12.430 34.000 +*N chanx_right_in[9]:15 *C 12.455 33.660 +*N chanx_right_in[9]:16 *C 13.755 33.660 +*N chanx_right_in[9]:17 *C 13.800 33.705 +*N chanx_right_in[9]:18 *C 13.800 40.120 +*N chanx_right_in[9]:19 *C 13.808 40.120 +*N chanx_right_in[9]:20 *C 56.120 39.780 +*N chanx_right_in[9]:21 *C 56.120 39.780 +*N chanx_right_in[9]:22 *C 56.120 40.120 +*N chanx_right_in[9]:23 *C 56.120 40.120 +*N chanx_right_in[9]:24 *C 102.573 40.120 +*N chanx_right_in[9]:25 *C 102.580 40.178 +*N chanx_right_in[9]:26 *C 102.580 42.102 +*N chanx_right_in[9]:27 *C 102.588 42.160 + +*CAP +0 chanx_right_in[9] 7.258486e-05 +1 mux_bottom_ipin_5\/mux_l2_in_2_:A1 1e-06 +2 ropt_mt_inst_736:A 1e-06 +3 mux_bottom_ipin_9\/mux_l1_in_2_:A0 1e-06 +4 chanx_right_in[9]:4 5.723253e-05 +5 chanx_right_in[9]:5 6.219559e-05 +6 chanx_right_in[9]:6 0.0002315885 +7 chanx_right_in[9]:7 0.0001300647 +8 chanx_right_in[9]:8 9.735517e-05 +9 chanx_right_in[9]:9 0.0005167956 +10 chanx_right_in[9]:10 0.0005167956 +11 chanx_right_in[9]:11 0.000507644 +12 chanx_right_in[9]:12 0.0005316855 +13 chanx_right_in[9]:13 5.846511e-05 +14 chanx_right_in[9]:14 6.514361e-05 +15 chanx_right_in[9]:15 0.0001056705 +16 chanx_right_in[9]:16 7.495058e-05 +17 chanx_right_in[9]:17 0.0004052115 +18 chanx_right_in[9]:18 0.0006707881 +19 chanx_right_in[9]:19 0.001643768 +20 chanx_right_in[9]:20 2.958742e-05 +21 chanx_right_in[9]:21 4.472599e-05 +22 chanx_right_in[9]:22 4.866132e-05 +23 chanx_right_in[9]:23 0.003868472 +24 chanx_right_in[9]:24 0.002224704 +25 chanx_right_in[9]:25 0.0001280772 +26 chanx_right_in[9]:26 0.0001280772 +27 chanx_right_in[9]:27 7.258486e-05 +28 chanx_right_in[9]:19 chanx_left_in[15]:29 0.0002804872 +29 chanx_right_in[9]:22 chanx_left_in[15]:12 9.620872e-06 +30 chanx_right_in[9]:23 chanx_left_in[15]:28 0.0002804872 +31 chanx_right_in[9]:21 chanx_left_in[15]:13 9.620872e-06 +32 chanx_right_in[9]:19 chanx_right_in[15]:22 0.0001480519 +33 chanx_right_in[9]:19 chanx_right_in[15]:26 3.491432e-06 +34 chanx_right_in[9]:19 chanx_right_in[15]:29 0.0004888839 +35 chanx_right_in[9]:19 chanx_right_in[15]:28 0.0003354499 +36 chanx_right_in[9]:23 chanx_right_in[15]:8 0.0004888839 +37 chanx_right_in[9]:23 chanx_right_in[15]:26 0.0001480519 +38 chanx_right_in[9]:23 chanx_right_in[15]:29 0.0003354499 +39 chanx_right_in[9]:23 chanx_right_in[15]:27 3.491432e-06 +40 chanx_right_in[9] chanx_right_in[18] 3.346724e-05 +41 chanx_right_in[9]:24 chanx_right_in[18] 4.397969e-06 +42 chanx_right_in[9]:24 chanx_right_in[18]:27 0.0005088898 +43 chanx_right_in[9]:24 chanx_right_in[18]:28 0.0002124295 +44 chanx_right_in[9]:24 chanx_right_in[18]:17 0.0002410321 +45 chanx_right_in[9]:27 chanx_right_in[18]:31 3.346724e-05 +46 chanx_right_in[9]:18 chanx_right_in[18]:16 5.960419e-06 +47 chanx_right_in[9]:19 chanx_right_in[18]:16 0.0007831259 +48 chanx_right_in[9]:6 chanx_right_in[18]:15 5.960419e-06 +49 chanx_right_in[9]:23 chanx_right_in[18]:27 0.0002124295 +50 chanx_right_in[9]:23 chanx_right_in[18]:31 4.397969e-06 +51 chanx_right_in[9]:23 chanx_right_in[18]:16 0.0002410321 +52 chanx_right_in[9]:23 chanx_right_in[18]:17 0.001292016 +53 chanx_right_in[9]:11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.840762e-05 +54 chanx_right_in[9]:16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 3.180332e-05 +55 chanx_right_in[9]:12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.840762e-05 +56 chanx_right_in[9]:13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.468766e-06 +57 chanx_right_in[9]:14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.468766e-06 +58 chanx_right_in[9]:15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.180332e-05 +59 chanx_right_in[9]:11 ropt_net_163:2 6.087399e-05 +60 chanx_right_in[9]:12 ropt_net_163:3 6.087399e-05 +61 chanx_right_in[9]:9 ropt_net_178:4 7.680424e-05 +62 chanx_right_in[9]:11 ropt_net_178:6 6.731114e-05 +63 chanx_right_in[9]:10 ropt_net_178:5 7.680424e-05 +64 chanx_right_in[9]:12 ropt_net_178:7 6.731114e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:27 0.0001664583 +1 chanx_right_in[9]:25 chanx_right_in[9]:24 0.00341 +2 chanx_right_in[9]:24 chanx_right_in[9]:23 0.007277558 +3 chanx_right_in[9]:26 chanx_right_in[9]:25 0.00171875 +4 chanx_right_in[9]:27 chanx_right_in[9]:26 0.00341 +5 chanx_right_in[9]:18 chanx_right_in[9]:17 0.005727679 +6 chanx_right_in[9]:18 chanx_right_in[9]:6 0.00390625 +7 chanx_right_in[9]:19 chanx_right_in[9]:18 0.00341 +8 chanx_right_in[9]:5 chanx_right_in[9]:4 9.510871e-05 +9 chanx_right_in[9]:6 chanx_right_in[9]:5 0.0045 +10 chanx_right_in[9]:4 mux_bottom_ipin_9\/mux_l1_in_2_:A0 0.152 +11 chanx_right_in[9]:22 chanx_right_in[9]:21 0.0001634615 +12 chanx_right_in[9]:23 chanx_right_in[9]:22 0.00341 +13 chanx_right_in[9]:23 chanx_right_in[9]:19 0.006628958 +14 chanx_right_in[9]:20 mux_bottom_ipin_5\/mux_l2_in_2_:A1 0.152 +15 chanx_right_in[9]:21 chanx_right_in[9]:20 0.0045 +16 chanx_right_in[9]:7 ropt_mt_inst_736:A 0.152 +17 chanx_right_in[9]:8 chanx_right_in[9]:7 0.001191964 +18 chanx_right_in[9]:9 chanx_right_in[9]:8 0.0045 +19 chanx_right_in[9]:11 chanx_right_in[9]:10 0.0045 +20 chanx_right_in[9]:10 chanx_right_in[9]:9 0.007508929 +21 chanx_right_in[9]:16 chanx_right_in[9]:15 0.001160714 +22 chanx_right_in[9]:17 chanx_right_in[9]:16 0.0045 +23 chanx_right_in[9]:12 chanx_right_in[9]:11 0.008995537 +24 chanx_right_in[9]:13 chanx_right_in[9]:12 0.0003035715 +25 chanx_right_in[9]:14 chanx_right_in[9]:13 0.0004196429 +26 chanx_right_in[9]:15 chanx_right_in[9]:14 0.0002297298 + +*END + +*D_NET top_grid_pin_18_[0] 0.00109023 //LENGTH 9.555 LUMPCC 0.0001648634 DR + +*CONN +*I mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 34.100 66.640 +*P top_grid_pin_18_[0] O *L 0.7423 *C 34.960 74.870 +*N top_grid_pin_18_[0]:2 *C 34.960 66.685 +*N top_grid_pin_18_[0]:3 *C 34.915 66.640 +*N top_grid_pin_18_[0]:4 *C 34.138 66.640 + +*CAP +0 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_18_[0] 0.0003911679 +2 top_grid_pin_18_[0]:2 0.0003911679 +3 top_grid_pin_18_[0]:3 7.101534e-05 +4 top_grid_pin_18_[0]:4 7.101534e-05 +5 top_grid_pin_18_[0] mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.243171e-05 +6 top_grid_pin_18_[0]:2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.243171e-05 + +*RES +0 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_18_[0]:4 0.152 +1 top_grid_pin_18_[0]:4 top_grid_pin_18_[0]:3 0.0006941965 +2 top_grid_pin_18_[0]:3 top_grid_pin_18_[0]:2 0.0045 +3 top_grid_pin_18_[0]:2 top_grid_pin_18_[0] 0.007308036 + +*END + +*D_NET top_grid_pin_25_[0] 0.001306751 //LENGTH 10.530 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 16.280 69.020 +*P top_grid_pin_25_[0] O *L 0.7423 *C 12.420 74.835 +*N top_grid_pin_25_[0]:2 *C 12.420 69.360 +*N top_grid_pin_25_[0]:3 *C 12.880 69.360 +*N top_grid_pin_25_[0]:4 *C 12.925 69.360 +*N top_grid_pin_25_[0]:5 *C 13.800 69.360 +*N top_grid_pin_25_[0]:6 *C 13.800 69.020 +*N top_grid_pin_25_[0]:7 *C 16.242 69.020 + +*CAP +0 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_25_[0] 0.0002909401 +2 top_grid_pin_25_[0]:2 0.0003248575 +3 top_grid_pin_25_[0]:3 6.611204e-05 +4 top_grid_pin_25_[0]:4 7.71237e-05 +5 top_grid_pin_25_[0]:5 0.0001021697 +6 top_grid_pin_25_[0]:6 0.0002347969 +7 top_grid_pin_25_[0]:7 0.0002097509 + +*RES +0 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_25_[0]:7 0.152 +1 top_grid_pin_25_[0]:7 top_grid_pin_25_[0]:6 0.002180804 +2 top_grid_pin_25_[0]:4 top_grid_pin_25_[0]:3 0.0045 +3 top_grid_pin_25_[0]:3 top_grid_pin_25_[0]:2 0.0004107143 +4 top_grid_pin_25_[0]:5 top_grid_pin_25_[0]:4 0.0007812501 +5 top_grid_pin_25_[0]:6 top_grid_pin_25_[0]:5 0.0003035715 +6 top_grid_pin_25_[0]:2 top_grid_pin_25_[0] 0.004888393 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.002062619 //LENGTH 15.360 LUMPCC 8.309976e-05 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 65.625 25.840 +*I mux_bottom_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 58.980 29.240 +*I mem_bottom_ipin_0\/FTB_1__40:A I *L 0.001746 *C 63.480 31.280 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 63.480 31.280 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 59.018 29.240 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 61.135 29.240 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 61.180 29.285 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 61.180 30.895 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 61.225 30.940 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 63.480 30.940 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 63.480 30.600 +*N mux_tree_tapbuf_size10_0_sram[3]:11 *C 65.275 30.600 +*N mux_tree_tapbuf_size10_0_sram[3]:12 *C 65.320 30.555 +*N mux_tree_tapbuf_size10_0_sram[3]:13 *C 65.320 25.885 +*N mux_tree_tapbuf_size10_0_sram[3]:14 *C 65.320 25.840 +*N mux_tree_tapbuf_size10_0_sram[3]:15 *C 65.625 25.840 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_0\/FTB_1__40:A 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 5.603474e-05 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001855856 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0001855856 +6 mux_tree_tapbuf_size10_0_sram[3]:6 0.0001158965 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0001158965 +8 mux_tree_tapbuf_size10_0_sram[3]:8 0.0001509956 +9 mux_tree_tapbuf_size10_0_sram[3]:9 0.0001994084 +10 mux_tree_tapbuf_size10_0_sram[3]:10 0.0001542444 +11 mux_tree_tapbuf_size10_0_sram[3]:11 0.0001312478 +12 mux_tree_tapbuf_size10_0_sram[3]:12 0.0002855342 +13 mux_tree_tapbuf_size10_0_sram[3]:13 0.0002855342 +14 mux_tree_tapbuf_size10_0_sram[3]:14 5.731708e-05 +15 mux_tree_tapbuf_size10_0_sram[3]:15 5.323909e-05 +16 mux_tree_tapbuf_size10_0_sram[3]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.674534e-08 +17 mux_tree_tapbuf_size10_0_sram[3]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.674534e-08 +18 mux_tree_tapbuf_size10_0_sram[3]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.150313e-05 +19 mux_tree_tapbuf_size10_0_sram[3]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.150313e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:15 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.0045 +2 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.0014375 +3 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.001890625 +4 mux_tree_tapbuf_size10_0_sram[3]:6 mux_tree_tapbuf_size10_0_sram[3]:5 0.0045 +5 mux_tree_tapbuf_size10_0_sram[3]:4 mux_bottom_ipin_0\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_0_sram[3]:11 mux_tree_tapbuf_size10_0_sram[3]:10 0.001602679 +7 mux_tree_tapbuf_size10_0_sram[3]:12 mux_tree_tapbuf_size10_0_sram[3]:11 0.0045 +8 mux_tree_tapbuf_size10_0_sram[3]:14 mux_tree_tapbuf_size10_0_sram[3]:13 0.0045 +9 mux_tree_tapbuf_size10_0_sram[3]:13 mux_tree_tapbuf_size10_0_sram[3]:12 0.004169643 +10 mux_tree_tapbuf_size10_0_sram[3]:15 mux_tree_tapbuf_size10_0_sram[3]:14 0.0001657609 +11 mux_tree_tapbuf_size10_0_sram[3]:3 mem_bottom_ipin_0\/FTB_1__40:A 0.152 +12 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.002013393 +13 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:3 0.0003035715 +14 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[0] 0.006221158 //LENGTH 48.465 LUMPCC 0.0003058508 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 59.185 37.060 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 44.795 37.060 +*I mux_bottom_ipin_5\/mux_l1_in_2_:S I *L 0.00357 *C 58.060 46.920 +*I mux_bottom_ipin_5\/mux_l1_in_0_:S I *L 0.00357 *C 55.780 56.440 +*I mux_bottom_ipin_5\/mux_l1_in_1_:S I *L 0.00357 *C 57.140 52.750 +*N mux_tree_tapbuf_size10_3_sram[0]:5 *C 57.140 52.750 +*N mux_tree_tapbuf_size10_3_sram[0]:6 *C 55.818 56.440 +*N mux_tree_tapbuf_size10_3_sram[0]:7 *C 56.535 56.440 +*N mux_tree_tapbuf_size10_3_sram[0]:8 *C 56.580 56.395 +*N mux_tree_tapbuf_size10_3_sram[0]:9 *C 56.580 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:10 *C 57.040 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:11 *C 57.040 53.040 +*N mux_tree_tapbuf_size10_3_sram[0]:12 *C 57.040 53.720 +*N mux_tree_tapbuf_size10_3_sram[0]:13 *C 60.215 53.720 +*N mux_tree_tapbuf_size10_3_sram[0]:14 *C 60.260 53.675 +*N mux_tree_tapbuf_size10_3_sram[0]:15 *C 58.098 46.920 +*N mux_tree_tapbuf_size10_3_sram[0]:16 *C 60.215 46.920 +*N mux_tree_tapbuf_size10_3_sram[0]:17 *C 60.260 46.920 +*N mux_tree_tapbuf_size10_3_sram[0]:18 *C 60.260 38.805 +*N mux_tree_tapbuf_size10_3_sram[0]:19 *C 60.215 38.760 +*N mux_tree_tapbuf_size10_3_sram[0]:20 *C 44.833 37.060 +*N mux_tree_tapbuf_size10_3_sram[0]:21 *C 45.495 37.060 +*N mux_tree_tapbuf_size10_3_sram[0]:22 *C 45.540 37.105 +*N mux_tree_tapbuf_size10_3_sram[0]:23 *C 45.540 38.715 +*N mux_tree_tapbuf_size10_3_sram[0]:24 *C 45.585 38.760 +*N mux_tree_tapbuf_size10_3_sram[0]:25 *C 59.340 38.760 +*N mux_tree_tapbuf_size10_3_sram[0]:26 *C 59.340 38.715 +*N mux_tree_tapbuf_size10_3_sram[0]:27 *C 59.340 37.105 +*N mux_tree_tapbuf_size10_3_sram[0]:28 *C 59.340 37.060 +*N mux_tree_tapbuf_size10_3_sram[0]:29 *C 59.185 37.060 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_5\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_ipin_5\/mux_l1_in_0_:S 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_3_sram[0]:5 6.145492e-05 +6 mux_tree_tapbuf_size10_3_sram[0]:6 7.771709e-05 +7 mux_tree_tapbuf_size10_3_sram[0]:7 7.771709e-05 +8 mux_tree_tapbuf_size10_3_sram[0]:8 0.0002015576 +9 mux_tree_tapbuf_size10_3_sram[0]:9 0.0002349773 +10 mux_tree_tapbuf_size10_3_sram[0]:10 6.500434e-05 +11 mux_tree_tapbuf_size10_3_sram[0]:11 0.0001149374 +12 mux_tree_tapbuf_size10_3_sram[0]:12 0.0003043112 +13 mux_tree_tapbuf_size10_3_sram[0]:13 0.0002562518 +14 mux_tree_tapbuf_size10_3_sram[0]:14 0.0003425853 +15 mux_tree_tapbuf_size10_3_sram[0]:15 0.0001698659 +16 mux_tree_tapbuf_size10_3_sram[0]:16 0.0001698659 +17 mux_tree_tapbuf_size10_3_sram[0]:17 0.0008574442 +18 mux_tree_tapbuf_size10_3_sram[0]:18 0.000478733 +19 mux_tree_tapbuf_size10_3_sram[0]:19 6.708064e-05 +20 mux_tree_tapbuf_size10_3_sram[0]:20 6.10735e-05 +21 mux_tree_tapbuf_size10_3_sram[0]:21 6.10735e-05 +22 mux_tree_tapbuf_size10_3_sram[0]:22 0.0001078777 +23 mux_tree_tapbuf_size10_3_sram[0]:23 0.0001078777 +24 mux_tree_tapbuf_size10_3_sram[0]:24 0.0008381788 +25 mux_tree_tapbuf_size10_3_sram[0]:25 0.0009374137 +26 mux_tree_tapbuf_size10_3_sram[0]:26 0.0001069245 +27 mux_tree_tapbuf_size10_3_sram[0]:27 0.0001069245 +28 mux_tree_tapbuf_size10_3_sram[0]:28 5.390732e-05 +29 mux_tree_tapbuf_size10_3_sram[0]:29 4.955157e-05 +30 mux_tree_tapbuf_size10_3_sram[0]:17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.698201e-05 +31 mux_tree_tapbuf_size10_3_sram[0]:14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.698201e-05 +32 mux_tree_tapbuf_size10_3_sram[0]:24 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.594337e-05 +33 mux_tree_tapbuf_size10_3_sram[0]:25 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.594337e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_3_sram[0]:29 0.152 +1 mux_tree_tapbuf_size10_3_sram[0]:5 mux_bottom_ipin_5\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_3_sram[0]:6 mux_bottom_ipin_5\/mux_l1_in_0_:S 0.152 +3 mux_tree_tapbuf_size10_3_sram[0]:7 mux_tree_tapbuf_size10_3_sram[0]:6 0.000640625 +4 mux_tree_tapbuf_size10_3_sram[0]:8 mux_tree_tapbuf_size10_3_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size10_3_sram[0]:11 mux_tree_tapbuf_size10_3_sram[0]:10 0.0045 +6 mux_tree_tapbuf_size10_3_sram[0]:11 mux_tree_tapbuf_size10_3_sram[0]:5 0.0001576087 +7 mux_tree_tapbuf_size10_3_sram[0]:10 mux_tree_tapbuf_size10_3_sram[0]:9 0.0004107143 +8 mux_tree_tapbuf_size10_3_sram[0]:24 mux_tree_tapbuf_size10_3_sram[0]:23 0.0045 +9 mux_tree_tapbuf_size10_3_sram[0]:23 mux_tree_tapbuf_size10_3_sram[0]:22 0.0014375 +10 mux_tree_tapbuf_size10_3_sram[0]:21 mux_tree_tapbuf_size10_3_sram[0]:20 0.0005915179 +11 mux_tree_tapbuf_size10_3_sram[0]:22 mux_tree_tapbuf_size10_3_sram[0]:21 0.0045 +12 mux_tree_tapbuf_size10_3_sram[0]:20 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size10_3_sram[0]:19 mux_tree_tapbuf_size10_3_sram[0]:18 0.0045 +14 mux_tree_tapbuf_size10_3_sram[0]:18 mux_tree_tapbuf_size10_3_sram[0]:17 0.007245536 +15 mux_tree_tapbuf_size10_3_sram[0]:25 mux_tree_tapbuf_size10_3_sram[0]:24 0.01228125 +16 mux_tree_tapbuf_size10_3_sram[0]:25 mux_tree_tapbuf_size10_3_sram[0]:19 0.00078125 +17 mux_tree_tapbuf_size10_3_sram[0]:26 mux_tree_tapbuf_size10_3_sram[0]:25 0.0045 +18 mux_tree_tapbuf_size10_3_sram[0]:28 mux_tree_tapbuf_size10_3_sram[0]:27 0.0045 +19 mux_tree_tapbuf_size10_3_sram[0]:27 mux_tree_tapbuf_size10_3_sram[0]:26 0.0014375 +20 mux_tree_tapbuf_size10_3_sram[0]:29 mux_tree_tapbuf_size10_3_sram[0]:28 8.423915e-05 +21 mux_tree_tapbuf_size10_3_sram[0]:16 mux_tree_tapbuf_size10_3_sram[0]:15 0.001890625 +22 mux_tree_tapbuf_size10_3_sram[0]:17 mux_tree_tapbuf_size10_3_sram[0]:16 0.0045 +23 mux_tree_tapbuf_size10_3_sram[0]:17 mux_tree_tapbuf_size10_3_sram[0]:14 0.00603125 +24 mux_tree_tapbuf_size10_3_sram[0]:15 mux_bottom_ipin_5\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size10_3_sram[0]:13 mux_tree_tapbuf_size10_3_sram[0]:12 0.002834822 +26 mux_tree_tapbuf_size10_3_sram[0]:14 mux_tree_tapbuf_size10_3_sram[0]:13 0.0045 +27 mux_tree_tapbuf_size10_3_sram[0]:12 mux_tree_tapbuf_size10_3_sram[0]:11 0.0006071428 +28 mux_tree_tapbuf_size10_3_sram[0]:9 mux_tree_tapbuf_size10_3_sram[0]:8 0.002995536 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[2] 0.004475642 //LENGTH 32.220 LUMPCC 0.0006903445 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 95.855 69.020 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 77.455 66.300 +*I mux_bottom_ipin_13\/mux_l3_in_0_:S I *L 0.00357 *C 85.200 61.200 +*I mux_bottom_ipin_13\/mux_l3_in_1_:S I *L 0.00357 *C 87.520 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:4 *C 87.535 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:5 *C 87.838 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:6 *C 87.860 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:7 *C 85.237 61.200 +*N mux_tree_tapbuf_size10_7_sram[2]:8 *C 87.355 61.200 +*N mux_tree_tapbuf_size10_7_sram[2]:9 *C 87.400 61.245 +*N mux_tree_tapbuf_size10_7_sram[2]:10 *C 87.400 63.240 +*N mux_tree_tapbuf_size10_7_sram[2]:11 *C 77.493 66.300 +*N mux_tree_tapbuf_size10_7_sram[2]:12 *C 81.420 66.300 +*N mux_tree_tapbuf_size10_7_sram[2]:13 *C 81.420 65.960 +*N mux_tree_tapbuf_size10_7_sram[2]:14 *C 87.355 65.960 +*N mux_tree_tapbuf_size10_7_sram[2]:15 *C 87.400 65.960 +*N mux_tree_tapbuf_size10_7_sram[2]:16 *C 87.400 66.935 +*N mux_tree_tapbuf_size10_7_sram[2]:17 *C 87.445 66.980 +*N mux_tree_tapbuf_size10_7_sram[2]:18 *C 94.715 66.980 +*N mux_tree_tapbuf_size10_7_sram[2]:19 *C 94.760 67.025 +*N mux_tree_tapbuf_size10_7_sram[2]:20 *C 94.760 68.975 +*N mux_tree_tapbuf_size10_7_sram[2]:21 *C 94.805 69.020 +*N mux_tree_tapbuf_size10_7_sram[2]:22 *C 95.818 69.020 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_13\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_ipin_13\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_7_sram[2]:4 6.111831e-05 +5 mux_tree_tapbuf_size10_7_sram[2]:5 6.111831e-05 +6 mux_tree_tapbuf_size10_7_sram[2]:6 6.565964e-05 +7 mux_tree_tapbuf_size10_7_sram[2]:7 0.0001152886 +8 mux_tree_tapbuf_size10_7_sram[2]:8 0.0001152886 +9 mux_tree_tapbuf_size10_7_sram[2]:9 0.0001187753 +10 mux_tree_tapbuf_size10_7_sram[2]:10 0.0002976054 +11 mux_tree_tapbuf_size10_7_sram[2]:11 0.0003184387 +12 mux_tree_tapbuf_size10_7_sram[2]:12 0.0003423136 +13 mux_tree_tapbuf_size10_7_sram[2]:13 0.000485348 +14 mux_tree_tapbuf_size10_7_sram[2]:14 0.0004614731 +15 mux_tree_tapbuf_size10_7_sram[2]:15 0.0002401877 +16 mux_tree_tapbuf_size10_7_sram[2]:16 6.298484e-05 +17 mux_tree_tapbuf_size10_7_sram[2]:17 0.0003018838 +18 mux_tree_tapbuf_size10_7_sram[2]:18 0.0003018838 +19 mux_tree_tapbuf_size10_7_sram[2]:19 0.0001252702 +20 mux_tree_tapbuf_size10_7_sram[2]:20 0.0001252702 +21 mux_tree_tapbuf_size10_7_sram[2]:21 9.069467e-05 +22 mux_tree_tapbuf_size10_7_sram[2]:22 9.069467e-05 +23 mux_tree_tapbuf_size10_7_sram[2]:8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.819049e-05 +24 mux_tree_tapbuf_size10_7_sram[2]:9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.563803e-05 +25 mux_tree_tapbuf_size10_7_sram[2]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.819049e-05 +26 mux_tree_tapbuf_size10_7_sram[2]:10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.563803e-05 +27 mux_tree_tapbuf_size10_7_sram[2]:17 ropt_net_149:6 0.0002172639 +28 mux_tree_tapbuf_size10_7_sram[2]:17 ropt_net_149:2 2.810033e-05 +29 mux_tree_tapbuf_size10_7_sram[2]:18 ropt_net_149:7 0.0002172639 +30 mux_tree_tapbuf_size10_7_sram[2]:18 ropt_net_149:3 2.810033e-05 +31 mux_tree_tapbuf_size10_7_sram[2]:17 ropt_net_176:3 3.597957e-05 +32 mux_tree_tapbuf_size10_7_sram[2]:18 ropt_net_176:2 3.597957e-05 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_7_sram[2]:22 0.152 +1 mux_tree_tapbuf_size10_7_sram[2]:14 mux_tree_tapbuf_size10_7_sram[2]:13 0.005299107 +2 mux_tree_tapbuf_size10_7_sram[2]:15 mux_tree_tapbuf_size10_7_sram[2]:14 0.0045 +3 mux_tree_tapbuf_size10_7_sram[2]:15 mux_tree_tapbuf_size10_7_sram[2]:10 0.002428571 +4 mux_tree_tapbuf_size10_7_sram[2]:11 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +5 mux_tree_tapbuf_size10_7_sram[2]:17 mux_tree_tapbuf_size10_7_sram[2]:16 0.0045 +6 mux_tree_tapbuf_size10_7_sram[2]:16 mux_tree_tapbuf_size10_7_sram[2]:15 0.0008705357 +7 mux_tree_tapbuf_size10_7_sram[2]:18 mux_tree_tapbuf_size10_7_sram[2]:17 0.006491072 +8 mux_tree_tapbuf_size10_7_sram[2]:19 mux_tree_tapbuf_size10_7_sram[2]:18 0.0045 +9 mux_tree_tapbuf_size10_7_sram[2]:21 mux_tree_tapbuf_size10_7_sram[2]:20 0.0045 +10 mux_tree_tapbuf_size10_7_sram[2]:20 mux_tree_tapbuf_size10_7_sram[2]:19 0.001741071 +11 mux_tree_tapbuf_size10_7_sram[2]:22 mux_tree_tapbuf_size10_7_sram[2]:21 0.0009040178 +12 mux_tree_tapbuf_size10_7_sram[2]:8 mux_tree_tapbuf_size10_7_sram[2]:7 0.001890625 +13 mux_tree_tapbuf_size10_7_sram[2]:9 mux_tree_tapbuf_size10_7_sram[2]:8 0.0045 +14 mux_tree_tapbuf_size10_7_sram[2]:7 mux_bottom_ipin_13\/mux_l3_in_0_:S 0.152 +15 mux_tree_tapbuf_size10_7_sram[2]:5 mux_tree_tapbuf_size10_7_sram[2]:4 0.0001644022 +16 mux_tree_tapbuf_size10_7_sram[2]:6 mux_tree_tapbuf_size10_7_sram[2]:5 0.0045 +17 mux_tree_tapbuf_size10_7_sram[2]:4 mux_bottom_ipin_13\/mux_l3_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_7_sram[2]:12 mux_tree_tapbuf_size10_7_sram[2]:11 0.003506696 +19 mux_tree_tapbuf_size10_7_sram[2]:13 mux_tree_tapbuf_size10_7_sram[2]:12 0.0003035715 +20 mux_tree_tapbuf_size10_7_sram[2]:10 mux_tree_tapbuf_size10_7_sram[2]:9 0.00178125 +21 mux_tree_tapbuf_size10_7_sram[2]:10 mux_tree_tapbuf_size10_7_sram[2]:6 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[3] 0.002009341 //LENGTH 14.130 LUMPCC 0.0006240483 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 46.765 47.600 +*I mux_bottom_ipin_3\/mux_l4_in_0_:S I *L 0.00357 *C 37.380 47.260 +*I mem_bottom_ipin_3\/FTB_10__49:A I *L 0.001746 *C 46.000 44.880 +*N mux_tree_tapbuf_size8_1_sram[3]:3 *C 46.038 44.880 +*N mux_tree_tapbuf_size8_1_sram[3]:4 *C 46.415 44.880 +*N mux_tree_tapbuf_size8_1_sram[3]:5 *C 46.460 44.925 +*N mux_tree_tapbuf_size8_1_sram[3]:6 *C 37.418 47.260 +*N mux_tree_tapbuf_size8_1_sram[3]:7 *C 39.055 47.260 +*N mux_tree_tapbuf_size8_1_sram[3]:8 *C 39.100 47.260 +*N mux_tree_tapbuf_size8_1_sram[3]:9 *C 39.100 46.920 +*N mux_tree_tapbuf_size8_1_sram[3]:10 *C 39.108 46.920 +*N mux_tree_tapbuf_size8_1_sram[3]:11 *C 46.453 46.920 +*N mux_tree_tapbuf_size8_1_sram[3]:12 *C 46.460 46.920 +*N mux_tree_tapbuf_size8_1_sram[3]:13 *C 46.460 47.555 +*N mux_tree_tapbuf_size8_1_sram[3]:14 *C 46.460 47.600 +*N mux_tree_tapbuf_size8_1_sram[3]:15 *C 46.765 47.600 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_3\/FTB_10__49:A 1e-06 +3 mux_tree_tapbuf_size8_1_sram[3]:3 3.991757e-05 +4 mux_tree_tapbuf_size8_1_sram[3]:4 3.991757e-05 +5 mux_tree_tapbuf_size8_1_sram[3]:5 0.0001083317 +6 mux_tree_tapbuf_size8_1_sram[3]:6 0.0001211265 +7 mux_tree_tapbuf_size8_1_sram[3]:7 0.0001211265 +8 mux_tree_tapbuf_size8_1_sram[3]:8 5.473967e-05 +9 mux_tree_tapbuf_size8_1_sram[3]:9 5.902862e-05 +10 mux_tree_tapbuf_size8_1_sram[3]:10 0.0002599639 +11 mux_tree_tapbuf_size8_1_sram[3]:11 0.0002599639 +12 mux_tree_tapbuf_size8_1_sram[3]:12 0.000185518 +13 mux_tree_tapbuf_size8_1_sram[3]:13 4.219421e-05 +14 mux_tree_tapbuf_size8_1_sram[3]:14 4.833829e-05 +15 mux_tree_tapbuf_size8_1_sram[3]:15 4.212681e-05 +16 mux_tree_tapbuf_size8_1_sram[3]:12 chanx_left_in[4]:29 2.319245e-06 +17 mux_tree_tapbuf_size8_1_sram[3]:11 chanx_left_in[4]:30 0.0001320439 +18 mux_tree_tapbuf_size8_1_sram[3]:10 chanx_left_in[4]:31 0.0001320439 +19 mux_tree_tapbuf_size8_1_sram[3]:5 chanx_left_in[4]:28 2.319245e-06 +20 mux_tree_tapbuf_size8_1_sram[3]:11 chanx_left_in[5]:23 0.000177661 +21 mux_tree_tapbuf_size8_1_sram[3]:10 chanx_left_in[5]:24 0.000177661 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_1_sram[3]:15 0.152 +1 mux_tree_tapbuf_size8_1_sram[3]:12 mux_tree_tapbuf_size8_1_sram[3]:11 0.00341 +2 mux_tree_tapbuf_size8_1_sram[3]:12 mux_tree_tapbuf_size8_1_sram[3]:5 0.00178125 +3 mux_tree_tapbuf_size8_1_sram[3]:11 mux_tree_tapbuf_size8_1_sram[3]:10 0.001150717 +4 mux_tree_tapbuf_size8_1_sram[3]:9 mux_tree_tapbuf_size8_1_sram[3]:8 0.0001634615 +5 mux_tree_tapbuf_size8_1_sram[3]:10 mux_tree_tapbuf_size8_1_sram[3]:9 0.00341 +6 mux_tree_tapbuf_size8_1_sram[3]:7 mux_tree_tapbuf_size8_1_sram[3]:6 0.001462054 +7 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:7 0.0045 +8 mux_tree_tapbuf_size8_1_sram[3]:6 mux_bottom_ipin_3\/mux_l4_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_1_sram[3]:4 mux_tree_tapbuf_size8_1_sram[3]:3 0.0003370536 +10 mux_tree_tapbuf_size8_1_sram[3]:5 mux_tree_tapbuf_size8_1_sram[3]:4 0.0045 +11 mux_tree_tapbuf_size8_1_sram[3]:3 mem_bottom_ipin_3\/FTB_10__49:A 0.152 +12 mux_tree_tapbuf_size8_1_sram[3]:14 mux_tree_tapbuf_size8_1_sram[3]:13 0.0045 +13 mux_tree_tapbuf_size8_1_sram[3]:13 mux_tree_tapbuf_size8_1_sram[3]:12 0.0005669643 +14 mux_tree_tapbuf_size8_1_sram[3]:15 mux_tree_tapbuf_size8_1_sram[3]:14 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[1] 0.004064283 //LENGTH 28.990 LUMPCC 0.0001166561 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.560 20.400 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 8.920 15.300 +*I mux_bottom_ipin_10\/mux_l2_in_0_:S I *L 0.00357 *C 10.480 23.415 +*I mux_bottom_ipin_10\/mux_l2_in_1_:S I *L 0.00357 *C 17.120 20.400 +*I mux_bottom_ipin_10\/mux_l2_in_3_:S I *L 0.00357 *C 23.100 23.800 +*I mux_bottom_ipin_10\/mux_l2_in_2_:S I *L 0.00357 *C 21.060 23.415 +*N mux_tree_tapbuf_size8_4_sram[1]:6 *C 21.060 23.415 +*N mux_tree_tapbuf_size8_4_sram[1]:7 *C 23.062 23.800 +*N mux_tree_tapbuf_size8_4_sram[1]:8 *C 21.060 23.800 +*N mux_tree_tapbuf_size8_4_sram[1]:9 *C 17.525 23.800 +*N mux_tree_tapbuf_size8_4_sram[1]:10 *C 17.480 23.755 +*N mux_tree_tapbuf_size8_4_sram[1]:11 *C 17.480 20.445 +*N mux_tree_tapbuf_size8_4_sram[1]:12 *C 17.457 20.400 +*N mux_tree_tapbuf_size8_4_sram[1]:13 *C 17.135 20.400 +*N mux_tree_tapbuf_size8_4_sram[1]:14 *C 10.480 23.415 +*N mux_tree_tapbuf_size8_4_sram[1]:15 *C 10.580 23.120 +*N mux_tree_tapbuf_size8_4_sram[1]:16 *C 10.580 23.075 +*N mux_tree_tapbuf_size8_4_sram[1]:17 *C 8.957 15.300 +*N mux_tree_tapbuf_size8_4_sram[1]:18 *C 10.535 15.300 +*N mux_tree_tapbuf_size8_4_sram[1]:19 *C 10.580 15.345 +*N mux_tree_tapbuf_size8_4_sram[1]:20 *C 10.580 20.740 +*N mux_tree_tapbuf_size8_4_sram[1]:21 *C 10.625 20.740 +*N mux_tree_tapbuf_size8_4_sram[1]:22 *C 12.880 20.740 +*N mux_tree_tapbuf_size8_4_sram[1]:23 *C 12.880 20.400 +*N mux_tree_tapbuf_size8_4_sram[1]:24 *C 14.560 20.400 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_ipin_10\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_10\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_10\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size8_4_sram[1]:6 5.95735e-05 +7 mux_tree_tapbuf_size8_4_sram[1]:7 0.0001632408 +8 mux_tree_tapbuf_size8_4_sram[1]:8 0.0004626859 +9 mux_tree_tapbuf_size8_4_sram[1]:9 0.0002689168 +10 mux_tree_tapbuf_size8_4_sram[1]:10 0.0002222989 +11 mux_tree_tapbuf_size8_4_sram[1]:11 0.0002222989 +12 mux_tree_tapbuf_size8_4_sram[1]:12 4.527048e-05 +13 mux_tree_tapbuf_size8_4_sram[1]:13 0.0001740584 +14 mux_tree_tapbuf_size8_4_sram[1]:14 6.296541e-05 +15 mux_tree_tapbuf_size8_4_sram[1]:15 6.753227e-05 +16 mux_tree_tapbuf_size8_4_sram[1]:16 0.0001707836 +17 mux_tree_tapbuf_size8_4_sram[1]:17 0.0001170908 +18 mux_tree_tapbuf_size8_4_sram[1]:18 0.0001170908 +19 mux_tree_tapbuf_size8_4_sram[1]:19 0.0003585184 +20 mux_tree_tapbuf_size8_4_sram[1]:20 0.0005644436 +21 mux_tree_tapbuf_size8_4_sram[1]:21 0.0002361248 +22 mux_tree_tapbuf_size8_4_sram[1]:22 0.0002616008 +23 mux_tree_tapbuf_size8_4_sram[1]:23 0.000116211 +24 mux_tree_tapbuf_size8_4_sram[1]:24 0.0002509218 +25 mux_tree_tapbuf_size8_4_sram[1]:24 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.456881e-05 +26 mux_tree_tapbuf_size8_4_sram[1]:24 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.192243e-05 +27 mux_tree_tapbuf_size8_4_sram[1]:13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.456881e-05 +28 mux_tree_tapbuf_size8_4_sram[1]:19 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.836824e-06 +29 mux_tree_tapbuf_size8_4_sram[1]:20 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.836824e-06 +30 mux_tree_tapbuf_size8_4_sram[1]:23 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.192243e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_4_sram[1]:24 0.152 +1 mux_tree_tapbuf_size8_4_sram[1]:24 mux_tree_tapbuf_size8_4_sram[1]:23 0.0015 +2 mux_tree_tapbuf_size8_4_sram[1]:24 mux_tree_tapbuf_size8_4_sram[1]:13 0.002299107 +3 mux_tree_tapbuf_size8_4_sram[1]:13 mux_bottom_ipin_10\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size8_4_sram[1]:13 mux_tree_tapbuf_size8_4_sram[1]:12 0.0001752718 +5 mux_tree_tapbuf_size8_4_sram[1]:15 mux_tree_tapbuf_size8_4_sram[1]:14 0.0001271552 +6 mux_tree_tapbuf_size8_4_sram[1]:16 mux_tree_tapbuf_size8_4_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size8_4_sram[1]:14 mux_bottom_ipin_10\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_4_sram[1]:9 mux_tree_tapbuf_size8_4_sram[1]:8 0.00315625 +9 mux_tree_tapbuf_size8_4_sram[1]:10 mux_tree_tapbuf_size8_4_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size8_4_sram[1]:12 mux_tree_tapbuf_size8_4_sram[1]:11 0.0045 +11 mux_tree_tapbuf_size8_4_sram[1]:11 mux_tree_tapbuf_size8_4_sram[1]:10 0.002955357 +12 mux_tree_tapbuf_size8_4_sram[1]:7 mux_bottom_ipin_10\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size8_4_sram[1]:6 mux_bottom_ipin_10\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size8_4_sram[1]:17 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +15 mux_tree_tapbuf_size8_4_sram[1]:18 mux_tree_tapbuf_size8_4_sram[1]:17 0.001408482 +16 mux_tree_tapbuf_size8_4_sram[1]:19 mux_tree_tapbuf_size8_4_sram[1]:18 0.0045 +17 mux_tree_tapbuf_size8_4_sram[1]:21 mux_tree_tapbuf_size8_4_sram[1]:20 0.0045 +18 mux_tree_tapbuf_size8_4_sram[1]:20 mux_tree_tapbuf_size8_4_sram[1]:19 0.004816964 +19 mux_tree_tapbuf_size8_4_sram[1]:20 mux_tree_tapbuf_size8_4_sram[1]:16 0.002084821 +20 mux_tree_tapbuf_size8_4_sram[1]:22 mux_tree_tapbuf_size8_4_sram[1]:21 0.002013393 +21 mux_tree_tapbuf_size8_4_sram[1]:23 mux_tree_tapbuf_size8_4_sram[1]:22 0.0003035715 +22 mux_tree_tapbuf_size8_4_sram[1]:8 mux_tree_tapbuf_size8_4_sram[1]:7 0.001787946 +23 mux_tree_tapbuf_size8_4_sram[1]:8 mux_tree_tapbuf_size8_4_sram[1]:6 0.0003437501 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_5_ccff_tail[0] 0.004770456 //LENGTH 34.040 LUMPCC 0.001420655 DR + +*CONN +*I mem_bottom_ipin_11\/FTB_14__53:X O *L 0 *C 37.495 27.880 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.735 20.740 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 *C 62.735 20.740 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 *C 63.020 20.740 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 *C 63.020 20.785 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 *C 63.020 25.783 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 *C 63.013 25.840 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 *C 37.727 25.840 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 *C 37.720 25.898 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 *C 37.720 27.835 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 *C 37.720 27.880 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 *C 37.495 27.880 + +*CAP +0 mem_bottom_ipin_11\/FTB_14__53:X 1e-06 +1 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 5.01879e-05 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 5.2354e-05 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.0002692098 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.0002692098 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.001174232 +7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.001174232 +8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 0.0001257289 +9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 0.0001257289 +10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 5.058931e-05 +11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 5.632932e-05 +12 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 chanx_left_in[0]:38 0.0001380763 +13 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 chanx_left_in[0]:42 5.260362e-06 +14 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 chanx_left_in[0]:47 0.0001212978 +15 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 chanx_left_in[0]:37 0.0001380763 +16 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 chanx_left_in[0]:41 5.260362e-06 +17 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 chanx_left_in[0]:46 0.0001212978 +18 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 chanx_right_in[14]:32 0.000445693 +19 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 chanx_right_in[14]:33 0.000445693 + +*RES +0 mem_bottom_ipin_11\/FTB_14__53:X mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 0.0001222826 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 0.001729911 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.00341 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.003961316 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.004462054 +7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.00341 +8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 0.0001548913 +9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001292352 //LENGTH 8.720 LUMPCC 0.0005556909 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_1_:X O *L 0 *C 63.195 47.600 +*I mux_bottom_ipin_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.310 55.420 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 63.310 55.420 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 63.480 55.420 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 63.480 55.375 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 63.480 47.645 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 63.480 47.600 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 63.195 47.600 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.589213e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.134243e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002640637 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002640637 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.494413e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.435541e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[5]:11 4.838925e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[5]:14 6.572357e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[5]:14 4.838925e-05 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[5]:15 6.572357e-05 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:12 4.523485e-06 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:16 9.530591e-05 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:13 4.523485e-06 +15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:18 9.530591e-05 +16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.263455e-06 +17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.263455e-06 +18 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.963978e-05 +19 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.963978e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901787 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006897229 //LENGTH 5.765 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l3_in_0_:X O *L 0 *C 53.185 26.180 +*I mux_bottom_ipin_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 55.300 28.900 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 55.263 28.900 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 53.865 28.900 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 53.820 28.855 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 53.820 26.225 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 53.775 26.180 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 53.223 26.180 + +*CAP +0 mux_bottom_ipin_4\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001108557 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001108557 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001717356 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001717356 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.12701e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.12701e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l3_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_4\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001247768 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002348214 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006695904 //LENGTH 5.360 LUMPCC 9.744782e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l3_in_0_:X O *L 0 *C 52.155 47.940 +*I mux_bottom_ipin_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 50.140 50.660 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 50.140 50.660 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 50.140 50.615 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 50.140 47.985 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 50.185 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 52.117 47.940 + +*CAP +0 mux_bottom_ipin_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.324532e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000134077 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000134077 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001343716 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001343716 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.872391e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.872391e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l3_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_5\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002348214 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001725447 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003502034 //LENGTH 29.330 LUMPCC 0.0007503446 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l4_in_0_:X O *L 0 *C 7.535 42.500 +*I mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.135 66.475 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.135 66.475 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 5.060 65.960 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 4.185 65.960 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 4.140 65.915 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 4.140 42.545 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 4.185 42.500 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 7.498 42.500 + +*CAP +0 mux_bottom_ipin_8\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.832542e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001123107 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 7.426263e-05 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.001059636 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001059636 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001877595 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001877595 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chanx_left_in[11]:34 0.0001015161 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_left_in[11]:35 0.0001015161 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mem_bottom_ipin_15/net_net_74:4 5.722743e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mem_bottom_ipin_15/net_net_74:3 5.722743e-05 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 ropt_net_174:5 1.395952e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 ropt_net_174:2 6.125181e-05 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 ropt_net_174:4 1.395952e-05 +16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 ropt_net_174:3 6.125181e-05 +17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 ropt_net_161:4 0.0001412175 +18 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 ropt_net_161:5 0.0001412175 + +*RES +0 mux_bottom_ipin_8\/mux_l4_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.00078125 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.02086607 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.002957589 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004598215 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005464876 //LENGTH 3.635 LUMPCC 0.0001131522 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_2_:X O *L 0 *C 81.245 14.280 +*I mux_bottom_ipin_12\/mux_l3_in_1_:A1 I *L 0.00198 *C 82.440 12.580 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 82.403 12.580 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 81.465 12.580 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 81.420 12.625 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 81.420 14.235 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 81.420 14.280 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 81.245 14.280 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.641421e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.641421e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001077879 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001077879 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.110204e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.182905e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_6_sram[2]:9 7.001689e-06 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_6_sram[2]:15 4.957441e-05 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_6_sram[2]:10 7.001689e-06 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_6_sram[2]:14 4.957441e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_2_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008370536 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003065974 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_1_:X O *L 0 *C 38.815 22.440 +*I mux_bottom_ipin_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 36.630 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 36.668 22.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 38.778 22.440 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001522987 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001522987 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_1_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007681932 //LENGTH 6.080 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_1_:X O *L 0 *C 33.865 39.780 +*I mux_bottom_ipin_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 33.295 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 33.333 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 33.995 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 34.040 44.155 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 34.040 39.825 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 34.040 39.780 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 33.865 39.780 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.615867e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.615867e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002520336 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002520336 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.546307e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.434551e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_1_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005915179 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.510869e-05 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002675312 //LENGTH 19.590 LUMPCC 0.0003966285 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_3_:X O *L 0 *C 91.255 38.760 +*I mux_bottom_ipin_6\/mux_l3_in_1_:A0 I *L 0.001631 *C 78.490 44.200 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 78.490 44.200 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 78.660 44.200 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 78.660 44.155 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 78.660 41.525 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 78.705 41.480 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 86.435 41.480 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 86.480 41.435 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 86.480 38.805 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 86.525 38.760 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 91.218 38.760 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.109504e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.508834e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001640156 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001640156 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004437887 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004437887 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.000141236 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.000141236 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0003362098 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0003362098 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[9]:7 0.0001221677 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[9]:6 0.0001221677 +14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size8_6_sram[1]:12 3.288691e-06 +15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size8_6_sram[1]:18 2.707534e-05 +16 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size8_6_sram[1]:13 4.578255e-05 +17 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size8_6_sram[1]:11 3.288691e-06 +18 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size8_6_sram[1]:15 2.707534e-05 +19 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size8_6_sram[1]:14 4.578255e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_3_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.006901786 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.002348214 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.004189732 + +*END + +*D_NET optlc_net_127 0.003986972 //LENGTH 30.425 LUMPCC 0.000404594 DR + +*CONN +*I optlc_128:HI O *L 0 *C 93.380 53.040 +*I mux_bottom_ipin_6\/mux_l2_in_3_:A0 I *L 0.001631 *C 93.210 39.100 +*I mux_bottom_ipin_14\/mux_l2_in_3_:A0 I *L 0.001631 *C 88.150 42.500 +*I mux_bottom_ipin_13\/mux_l2_in_3_:A0 I *L 0.001631 *C 92.290 58.820 +*N optlc_net_127:4 *C 92.328 58.820 +*N optlc_net_127:5 *C 93.795 58.820 +*N optlc_net_127:6 *C 93.840 58.775 +*N optlc_net_127:7 *C 88.188 42.500 +*N optlc_net_127:8 *C 92.875 42.500 +*N optlc_net_127:9 *C 92.920 42.455 +*N optlc_net_127:10 *C 93.210 39.100 +*N optlc_net_127:11 *C 92.920 39.100 +*N optlc_net_127:12 *C 92.920 39.145 +*N optlc_net_127:13 *C 92.920 41.820 +*N optlc_net_127:14 *C 93.380 41.820 +*N optlc_net_127:15 *C 93.380 53.040 +*N optlc_net_127:16 *C 93.840 53.085 +*N optlc_net_127:17 *C 93.795 53.040 +*N optlc_net_127:18 *C 93.418 53.040 + +*CAP +0 optlc_128:HI 1e-06 +1 mux_bottom_ipin_6\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_14\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_13\/mux_l2_in_3_:A0 1e-06 +4 optlc_net_127:4 0.0001389197 +5 optlc_net_127:5 0.0001389197 +6 optlc_net_127:6 0.000373004 +7 optlc_net_127:7 0.0002546436 +8 optlc_net_127:8 0.0002546436 +9 optlc_net_127:9 3.729046e-05 +10 optlc_net_127:10 5.504701e-05 +11 optlc_net_127:11 5.978887e-05 +12 optlc_net_127:12 0.0001776168 +13 optlc_net_127:13 0.0002305298 +14 optlc_net_127:14 0.0006669505 +15 optlc_net_127:15 0.0006855668 +16 optlc_net_127:16 0.0004072429 +17 optlc_net_127:17 4.910732e-05 +18 optlc_net_127:18 4.910732e-05 +19 optlc_net_127:8 chanx_left_in[9]:6 0.0001854676 +20 optlc_net_127:7 chanx_left_in[9]:7 0.0001854676 +21 optlc_net_127:13 chanx_left_in[9]:7 1.682945e-05 +22 optlc_net_127:14 chanx_left_in[9]:6 1.682945e-05 + +*RES +0 optlc_128:HI optlc_net_127:18 0.152 +1 optlc_net_127:17 optlc_net_127:16 0.0045 +2 optlc_net_127:16 optlc_net_127:15 0.0004107143 +3 optlc_net_127:16 optlc_net_127:6 0.005080357 +4 optlc_net_127:18 optlc_net_127:17 0.0003370536 +5 optlc_net_127:11 optlc_net_127:10 0.0001576087 +6 optlc_net_127:12 optlc_net_127:11 0.0045 +7 optlc_net_127:10 mux_bottom_ipin_6\/mux_l2_in_3_:A0 0.152 +8 optlc_net_127:8 optlc_net_127:7 0.004185268 +9 optlc_net_127:9 optlc_net_127:8 0.0045 +10 optlc_net_127:7 mux_bottom_ipin_14\/mux_l2_in_3_:A0 0.152 +11 optlc_net_127:5 optlc_net_127:4 0.001310268 +12 optlc_net_127:6 optlc_net_127:5 0.0045 +13 optlc_net_127:4 mux_bottom_ipin_13\/mux_l2_in_3_:A0 0.152 +14 optlc_net_127:13 optlc_net_127:12 0.002388393 +15 optlc_net_127:13 optlc_net_127:9 0.0005669643 +16 optlc_net_127:14 optlc_net_127:13 0.0004107143 +17 optlc_net_127:15 optlc_net_127:14 0.01001786 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004920338 //LENGTH 4.130 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l3_in_1_:X O *L 0 *C 67.335 64.600 +*I mux_bottom_ipin_15\/mux_l4_in_0_:A0 I *L 0.001631 *C 65.495 65.960 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 65.532 65.960 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 66.195 65.960 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 66.240 65.915 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 66.240 64.645 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 66.285 64.600 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 67.297 64.600 + +*CAP +0 mux_bottom_ipin_15\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.520504e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.520504e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.719024e-05 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.719024e-05 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.262164e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 9.262164e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l3_in_1_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_15\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005915179 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009040179 + +*END + +*D_NET ropt_net_187 0.0001191763 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 34.235 72.080 +*I ropt_mt_inst_794:A I *L 0.001767 *C 34.960 72.080 +*N ropt_net_187:2 *C 34.922 72.080 +*N ropt_net_187:3 *C 34.273 72.080 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_187:2 5.858816e-05 +3 ropt_net_187:3 5.858816e-05 + +*RES +0 ropt_mt_inst_732:X ropt_net_187:3 0.152 +1 ropt_net_187:2 ropt_mt_inst_794:A 0.152 +2 ropt_net_187:3 ropt_net_187:2 0.0005803572 + +*END + +*D_NET chanx_left_out[0] 0.001306804 //LENGTH 11.680 LUMPCC 0.0001719523 DR + +*CONN +*I FTB_21__20:X O *L 0 *C 10.580 6.120 +*P chanx_left_out[0] O *L 0.7423 *C 4.600 1.285 +*N chanx_left_out[0]:2 *C 4.600 5.433 +*N chanx_left_out[0]:3 *C 4.620 5.440 +*N chanx_left_out[0]:4 *C 10.572 5.440 +*N chanx_left_out[0]:5 *C 10.580 5.498 +*N chanx_left_out[0]:6 *C 10.580 6.075 +*N chanx_left_out[0]:7 *C 10.580 6.120 + +*CAP +0 FTB_21__20:X 1e-06 +1 chanx_left_out[0] 0.0002150396 +2 chanx_left_out[0]:2 0.0002150396 +3 chanx_left_out[0]:3 0.0002792355 +4 chanx_left_out[0]:4 0.0002792355 +5 chanx_left_out[0]:5 5.675034e-05 +6 chanx_left_out[0]:6 5.675034e-05 +7 chanx_left_out[0]:7 3.180074e-05 +8 chanx_left_out[0]:3 ropt_net_147:5 8.597617e-05 +9 chanx_left_out[0]:4 ropt_net_147:6 8.597617e-05 + +*RES +0 FTB_21__20:X chanx_left_out[0]:7 0.152 +1 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +2 chanx_left_out[0]:2 chanx_left_out[0] 0.000649775 +3 chanx_left_out[0]:5 chanx_left_out[0]:4 0.00341 +4 chanx_left_out[0]:4 chanx_left_out[0]:3 0.0009325583 +5 chanx_left_out[0]:7 chanx_left_out[0]:6 0.0045 +6 chanx_left_out[0]:6 chanx_left_out[0]:5 0.0005156251 + +*END + +*D_NET chanx_right_out[11] 0.001690754 //LENGTH 12.130 LUMPCC 0.0004810698 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 94.300 11.560 +*P chanx_right_out[11] O *L 0.7423 *C 103.575 9.520 +*N chanx_right_out[11]:2 *C 103.047 9.520 +*N chanx_right_out[11]:3 *C 103.040 9.578 +*N chanx_right_out[11]:4 *C 103.040 11.515 +*N chanx_right_out[11]:5 *C 102.995 11.560 +*N chanx_right_out[11]:6 *C 94.338 11.560 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 chanx_right_out[11] 5.788324e-05 +2 chanx_right_out[11]:2 5.788324e-05 +3 chanx_right_out[11]:3 9.877712e-05 +4 chanx_right_out[11]:4 9.877712e-05 +5 chanx_right_out[11]:5 0.0004476815 +6 chanx_right_out[11]:6 0.0004476815 +7 chanx_right_out[11]:6 ropt_net_188:7 0.0002405349 +8 chanx_right_out[11]:5 ropt_net_188:8 0.0002405349 + +*RES +0 ropt_mt_inst_743:X chanx_right_out[11]:6 0.152 +1 chanx_right_out[11]:6 chanx_right_out[11]:5 0.007729911 +2 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +3 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001729911 +4 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +5 chanx_right_out[11]:2 chanx_right_out[11] 8.264167e-05 + +*END + +*D_NET ropt_net_188 0.001603038 //LENGTH 11.815 LUMPCC 0.0005731373 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 101.775 11.900 +*I ropt_mt_inst_795:A I *L 0.001767 *C 93.380 9.520 +*N ropt_net_188:2 *C 93.380 9.520 +*N ropt_net_188:3 *C 93.380 9.860 +*N ropt_net_188:4 *C 95.635 9.860 +*N ropt_net_188:5 *C 95.680 9.905 +*N ropt_net_188:6 *C 95.680 11.855 +*N ropt_net_188:7 *C 95.725 11.900 +*N ropt_net_188:8 *C 101.738 11.900 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_188:2 5.621704e-05 +3 ropt_net_188:3 0.0001883873 +4 ropt_net_188:4 0.0001608134 +5 ropt_net_188:5 0.0001174615 +6 ropt_net_188:6 0.0001174615 +7 ropt_net_188:7 0.0001937797 +8 ropt_net_188:8 0.0001937797 +9 ropt_net_188:8 chanx_right_out[11]:5 0.0002405349 +10 ropt_net_188:7 chanx_right_out[11]:6 0.0002405349 +11 ropt_net_188:8 ropt_net_150:2 4.603374e-05 +12 ropt_net_188:7 ropt_net_150:3 4.603374e-05 + +*RES +0 ropt_mt_inst_747:X ropt_net_188:8 0.152 +1 ropt_net_188:8 ropt_net_188:7 0.005368304 +2 ropt_net_188:7 ropt_net_188:6 0.0045 +3 ropt_net_188:6 ropt_net_188:5 0.001741071 +4 ropt_net_188:4 ropt_net_188:3 0.002013393 +5 ropt_net_188:5 ropt_net_188:4 0.0045 +6 ropt_net_188:2 ropt_mt_inst_795:A 0.152 +7 ropt_net_188:3 ropt_net_188:2 0.0003035715 + +*END + +*D_NET chanx_right_out[9] 0.000384098 //LENGTH 1.985 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 101.855 44.880 +*P chanx_right_out[9] O *L 0.7423 *C 103.650 44.880 +*N chanx_right_out[9]:2 *C 102.128 44.880 +*N chanx_right_out[9]:3 *C 102.120 44.880 +*N chanx_right_out[9]:4 *C 102.120 44.880 +*N chanx_right_out[9]:5 *C 101.855 44.880 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chanx_right_out[9] 0.0001168538 +2 chanx_right_out[9]:2 0.0001168538 +3 chanx_right_out[9]:3 3.688539e-05 +4 chanx_right_out[9]:4 5.068816e-05 +5 chanx_right_out[9]:5 6.18169e-05 + +*RES +0 ropt_mt_inst_761:X chanx_right_out[9]:5 0.152 +1 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0001440218 +2 chanx_right_out[9]:4 chanx_right_out[9]:3 0.0045 +3 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +4 chanx_right_out[9]:2 chanx_right_out[9] 0.000238525 + +*END + +*D_NET chanx_right_out[6] 0.0007146492 //LENGTH 5.855 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 98.900 7.140 +*P chanx_right_out[6] O *L 0.7423 *C 103.583 6.800 +*N chanx_right_out[6]:2 *C 103.500 6.800 +*N chanx_right_out[6]:3 *C 103.500 6.800 +*N chanx_right_out[6]:4 *C 103.455 6.800 +*N chanx_right_out[6]:5 *C 99.360 6.800 +*N chanx_right_out[6]:6 *C 99.360 7.140 +*N chanx_right_out[6]:7 *C 98.938 7.140 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 chanx_right_out[6] 3.467206e-05 +2 chanx_right_out[6]:2 3.467206e-05 +3 chanx_right_out[6]:3 2.916884e-05 +4 chanx_right_out[6]:4 0.0002354793 +5 chanx_right_out[6]:5 0.0002592268 +6 chanx_right_out[6]:6 7.208879e-05 +7 chanx_right_out[6]:7 4.834128e-05 + +*RES +0 ropt_mt_inst_788:X chanx_right_out[6]:7 0.152 +1 chanx_right_out[6]:7 chanx_right_out[6]:6 0.0003772322 +2 chanx_right_out[6]:4 chanx_right_out[6]:3 0.0045 +3 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +4 chanx_right_out[6]:2 chanx_right_out[6] 2.35e-05 +5 chanx_right_out[6]:6 chanx_right_out[6]:5 0.0003035715 +6 chanx_right_out[6]:5 chanx_right_out[6]:4 0.00365625 + +*END + +*D_NET ropt_net_155 0.001746552 //LENGTH 15.645 LUMPCC 0.00013241 DR + +*CONN +*I BUFT_P_101:X O *L 0 *C 18.400 6.460 +*I ropt_mt_inst_752:A I *L 0.001766 *C 7.820 4.080 +*N ropt_net_155:2 *C 7.858 4.080 +*N ropt_net_155:3 *C 9.155 4.080 +*N ropt_net_155:4 *C 9.200 4.035 +*N ropt_net_155:5 *C 9.200 3.458 +*N ropt_net_155:6 *C 9.207 3.400 +*N ropt_net_155:7 *C 18.393 3.400 +*N ropt_net_155:8 *C 18.400 3.458 +*N ropt_net_155:9 *C 18.400 6.415 +*N ropt_net_155:10 *C 18.400 6.460 + +*CAP +0 BUFT_P_101:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_155:2 5.931867e-05 +3 ropt_net_155:3 5.931867e-05 +4 ropt_net_155:4 4.95616e-05 +5 ropt_net_155:5 4.95616e-05 +6 ropt_net_155:6 0.0005302933 +7 ropt_net_155:7 0.0005302933 +8 ropt_net_155:8 0.0001524935 +9 ropt_net_155:9 0.0001524935 +10 ropt_net_155:10 2.880796e-05 +11 ropt_net_155:9 chanx_left_out[3]:6 3.232437e-06 +12 ropt_net_155:8 chanx_left_out[3]:5 3.232437e-06 +13 ropt_net_155:3 chanx_left_out[3]:4 6.297257e-05 +14 ropt_net_155:2 chanx_left_out[3]:3 6.297257e-05 + +*RES +0 BUFT_P_101:X ropt_net_155:10 0.152 +1 ropt_net_155:10 ropt_net_155:9 0.0045 +2 ropt_net_155:9 ropt_net_155:8 0.002640625 +3 ropt_net_155:8 ropt_net_155:7 0.00341 +4 ropt_net_155:7 ropt_net_155:6 0.001438983 +5 ropt_net_155:5 ropt_net_155:4 0.000515625 +6 ropt_net_155:6 ropt_net_155:5 0.00341 +7 ropt_net_155:3 ropt_net_155:2 0.001158482 +8 ropt_net_155:4 ropt_net_155:3 0.0045 +9 ropt_net_155:2 ropt_mt_inst_752:A 0.152 + +*END + +*D_NET chanx_left_in[4] 0.01978991 //LENGTH 146.740 LUMPCC 0.004073767 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 53.040 +*I mux_bottom_ipin_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 50.240 34.340 +*I ropt_mt_inst_728:A I *L 0.001767 *C 97.825 55.760 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 66.605 34.340 +*N chanx_left_in[4]:4 *C 97.863 55.760 +*N chanx_left_in[4]:5 *C 98.855 55.760 +*N chanx_left_in[4]:6 *C 98.900 55.715 +*N chanx_left_in[4]:7 *C 98.900 55.125 +*N chanx_left_in[4]:8 *C 98.900 55.080 +*N chanx_left_in[4]:9 *C 81.005 55.080 +*N chanx_left_in[4]:10 *C 80.960 55.125 +*N chanx_left_in[4]:11 *C 80.960 55.715 +*N chanx_left_in[4]:12 *C 80.915 55.760 +*N chanx_left_in[4]:13 *C 76.865 55.760 +*N chanx_left_in[4]:14 *C 76.820 55.715 +*N chanx_left_in[4]:15 *C 76.820 42.885 +*N chanx_left_in[4]:16 *C 76.775 42.840 +*N chanx_left_in[4]:17 *C 66.745 42.840 +*N chanx_left_in[4]:18 *C 66.700 42.795 +*N chanx_left_in[4]:19 *C 66.700 34.385 +*N chanx_left_in[4]:20 *C 66.608 34.340 +*N chanx_left_in[4]:21 *C 65.320 34.340 +*N chanx_left_in[4]:22 *C 65.320 34.680 +*N chanx_left_in[4]:23 *C 58.880 34.680 +*N chanx_left_in[4]:24 *C 58.880 34.340 +*N chanx_left_in[4]:25 *C 50.278 34.340 +*N chanx_left_in[4]:26 *C 50.140 34.000 +*N chanx_left_in[4]:27 *C 44.665 34.000 +*N chanx_left_in[4]:28 *C 44.620 34.045 +*N chanx_left_in[4]:29 *C 44.620 45.503 +*N chanx_left_in[4]:30 *C 44.613 45.560 +*N chanx_left_in[4]:31 *C 22.547 45.560 +*N chanx_left_in[4]:32 *C 22.540 45.617 +*N chanx_left_in[4]:33 *C 22.540 52.983 +*N chanx_left_in[4]:34 *C 22.533 53.040 + +*CAP +0 chanx_left_in[4] 0.0009681011 +1 mux_bottom_ipin_4\/mux_l1_in_2_:A1 1e-06 +2 ropt_mt_inst_728:A 1e-06 +3 mux_bottom_ipin_0\/mux_l1_in_2_:A1 1e-06 +4 chanx_left_in[4]:4 7.85044e-05 +5 chanx_left_in[4]:5 7.85044e-05 +6 chanx_left_in[4]:6 5.320776e-05 +7 chanx_left_in[4]:7 5.320776e-05 +8 chanx_left_in[4]:8 0.001202004 +9 chanx_left_in[4]:9 0.001170809 +10 chanx_left_in[4]:10 6.258091e-05 +11 chanx_left_in[4]:11 6.258091e-05 +12 chanx_left_in[4]:12 0.0002541972 +13 chanx_left_in[4]:13 0.0002541972 +14 chanx_left_in[4]:14 0.0006556508 +15 chanx_left_in[4]:15 0.0006556508 +16 chanx_left_in[4]:16 0.0005083111 +17 chanx_left_in[4]:17 0.0005083111 +18 chanx_left_in[4]:18 0.0004407633 +19 chanx_left_in[4]:19 0.0004407633 +20 chanx_left_in[4]:20 0.0001060691 +21 chanx_left_in[4]:21 0.0001326732 +22 chanx_left_in[4]:22 0.0004743909 +23 chanx_left_in[4]:23 0.0004745087 +24 chanx_left_in[4]:24 0.0005521773 +25 chanx_left_in[4]:25 0.000552472 +26 chanx_left_in[4]:26 0.0004156617 +27 chanx_left_in[4]:27 0.000388645 +28 chanx_left_in[4]:28 0.0006340428 +29 chanx_left_in[4]:29 0.0006340428 +30 chanx_left_in[4]:30 0.001048856 +31 chanx_left_in[4]:31 0.001048856 +32 chanx_left_in[4]:32 0.0004176492 +33 chanx_left_in[4]:33 0.0004176492 +34 chanx_left_in[4]:34 0.0009681012 +35 chanx_left_in[4] chanx_left_in[1] 6.250455e-06 +36 chanx_left_in[4] chanx_left_in[1]:47 0.001090896 +37 chanx_left_in[4]:32 chanx_left_in[1]:44 2.698936e-06 +38 chanx_left_in[4]:33 chanx_left_in[1]:45 2.698936e-06 +39 chanx_left_in[4]:34 chanx_left_in[1]:46 0.001090896 +40 chanx_left_in[4]:34 chanx_left_in[1]:50 6.250455e-06 +41 chanx_left_in[4]:17 chanx_left_in[9]:9 0.0001251598 +42 chanx_left_in[4]:17 chanx_left_in[9]:7 0.0001061256 +43 chanx_left_in[4]:16 chanx_left_in[9]:6 0.0001061256 +44 chanx_left_in[4]:16 chanx_left_in[9]:8 0.0001251598 +45 chanx_left_in[4]:30 chanx_left_in[9]:17 0.0004658417 +46 chanx_left_in[4]:31 chanx_left_in[9]:18 0.0004658417 +47 chanx_left_in[4]:25 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 3.739013e-05 +48 chanx_left_in[4]:24 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 3.739013e-05 +49 chanx_left_in[4]:28 mux_tree_tapbuf_size8_1_sram[3]:5 2.319245e-06 +50 chanx_left_in[4]:29 mux_tree_tapbuf_size8_1_sram[3]:12 2.319245e-06 +51 chanx_left_in[4]:30 mux_tree_tapbuf_size8_1_sram[3]:11 0.0001320439 +52 chanx_left_in[4]:31 mux_tree_tapbuf_size8_1_sram[3]:10 0.0001320439 +53 chanx_left_in[4]:15 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 6.815747e-05 +54 chanx_left_in[4]:14 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 6.815747e-05 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:34 0.003337391 +1 chanx_left_in[4]:20 chanx_left_in[4]:19 0.0045 +2 chanx_left_in[4]:20 mux_bottom_ipin_0\/mux_l1_in_2_:A1 0.152 +3 chanx_left_in[4]:19 chanx_left_in[4]:18 0.007508929 +4 chanx_left_in[4]:17 chanx_left_in[4]:16 0.008955357 +5 chanx_left_in[4]:18 chanx_left_in[4]:17 0.0045 +6 chanx_left_in[4]:16 chanx_left_in[4]:15 0.0045 +7 chanx_left_in[4]:15 chanx_left_in[4]:14 0.01145536 +8 chanx_left_in[4]:13 chanx_left_in[4]:12 0.003616072 +9 chanx_left_in[4]:14 chanx_left_in[4]:13 0.0045 +10 chanx_left_in[4]:12 chanx_left_in[4]:11 0.0045 +11 chanx_left_in[4]:11 chanx_left_in[4]:10 0.0005267857 +12 chanx_left_in[4]:9 chanx_left_in[4]:8 0.01597768 +13 chanx_left_in[4]:10 chanx_left_in[4]:9 0.0045 +14 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0045 +15 chanx_left_in[4]:7 chanx_left_in[4]:6 0.0005267857 +16 chanx_left_in[4]:5 chanx_left_in[4]:4 0.0008861608 +17 chanx_left_in[4]:6 chanx_left_in[4]:5 0.0045 +18 chanx_left_in[4]:4 ropt_mt_inst_728:A 0.152 +19 chanx_left_in[4]:25 mux_bottom_ipin_4\/mux_l1_in_2_:A1 0.152 +20 chanx_left_in[4]:25 chanx_left_in[4]:24 0.007680804 +21 chanx_left_in[4]:27 chanx_left_in[4]:26 0.004888393 +22 chanx_left_in[4]:28 chanx_left_in[4]:27 0.0045 +23 chanx_left_in[4]:29 chanx_left_in[4]:28 0.01022991 +24 chanx_left_in[4]:30 chanx_left_in[4]:29 0.00341 +25 chanx_left_in[4]:32 chanx_left_in[4]:31 0.00341 +26 chanx_left_in[4]:31 chanx_left_in[4]:30 0.00345685 +27 chanx_left_in[4]:33 chanx_left_in[4]:32 0.006575893 +28 chanx_left_in[4]:34 chanx_left_in[4]:33 0.00341 +29 chanx_left_in[4]:26 chanx_left_in[4]:25 0.0003035715 +30 chanx_left_in[4]:24 chanx_left_in[4]:23 0.0003035715 +31 chanx_left_in[4]:23 chanx_left_in[4]:22 0.00575 +32 chanx_left_in[4]:22 chanx_left_in[4]:21 0.0003035715 +33 chanx_left_in[4]:21 chanx_left_in[4]:20 0.001149554 + +*END + +*D_NET chanx_left_in[17] 0.02207882 //LENGTH 159.260 LUMPCC 0.006985269 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 39.440 +*I mux_bottom_ipin_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 53.650 64.260 +*I mux_bottom_ipin_13\/mux_l2_in_2_:A0 I *L 0.001631 *C 90.920 60.860 +*I FTB_18__17:A I *L 0.001767 *C 97.520 34.000 +*N chanx_left_in[17]:4 *C 97.483 34.000 +*N chanx_left_in[17]:5 *C 97.105 34.000 +*N chanx_left_in[17]:6 *C 97.060 34.045 +*N chanx_left_in[17]:7 *C 97.060 51.623 +*N chanx_left_in[17]:8 *C 97.053 51.680 +*N chanx_left_in[17]:9 *C 91.547 51.680 +*N chanx_left_in[17]:10 *C 91.540 51.738 +*N chanx_left_in[17]:11 *C 90.958 60.860 +*N chanx_left_in[17]:12 *C 91.495 60.860 +*N chanx_left_in[17]:13 *C 91.540 60.860 +*N chanx_left_in[17]:14 *C 91.540 65.903 +*N chanx_left_in[17]:15 *C 91.532 65.960 +*N chanx_left_in[17]:16 *C 57.508 65.960 +*N chanx_left_in[17]:17 *C 57.500 65.903 +*N chanx_left_in[17]:18 *C 57.500 64.305 +*N chanx_left_in[17]:19 *C 57.455 64.260 +*N chanx_left_in[17]:20 *C 53.650 64.260 +*N chanx_left_in[17]:21 *C 48.805 64.260 +*N chanx_left_in[17]:22 *C 48.760 64.215 +*N chanx_left_in[17]:23 *C 48.760 63.298 +*N chanx_left_in[17]:24 *C 48.753 63.240 +*N chanx_left_in[17]:25 *C 6.460 63.240 +*N chanx_left_in[17]:26 *C 6.440 63.233 +*N chanx_left_in[17]:27 *C 6.440 39.448 +*N chanx_left_in[17]:28 *C 6.420 39.440 + +*CAP +0 chanx_left_in[17] 0.0004419446 +1 mux_bottom_ipin_1\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_2_:A0 1e-06 +3 FTB_18__17:A 1e-06 +4 chanx_left_in[17]:4 4.875323e-05 +5 chanx_left_in[17]:5 4.875323e-05 +6 chanx_left_in[17]:6 0.0006313808 +7 chanx_left_in[17]:7 0.0006313808 +8 chanx_left_in[17]:8 0.0004948796 +9 chanx_left_in[17]:9 0.0004948796 +10 chanx_left_in[17]:10 0.0005248758 +11 chanx_left_in[17]:11 5.687672e-05 +12 chanx_left_in[17]:12 5.687672e-05 +13 chanx_left_in[17]:13 0.0008387374 +14 chanx_left_in[17]:14 0.0002807415 +15 chanx_left_in[17]:15 0.001547386 +16 chanx_left_in[17]:16 0.001547386 +17 chanx_left_in[17]:17 0.0001026791 +18 chanx_left_in[17]:18 0.0001026791 +19 chanx_left_in[17]:19 0.0002254264 +20 chanx_left_in[17]:20 0.0005958873 +21 chanx_left_in[17]:21 0.0003403076 +22 chanx_left_in[17]:22 7.310882e-05 +23 chanx_left_in[17]:23 7.310882e-05 +24 chanx_left_in[17]:24 0.001708076 +25 chanx_left_in[17]:25 0.001708076 +26 chanx_left_in[17]:26 0.0010372 +27 chanx_left_in[17]:27 0.0010372 +28 chanx_left_in[17]:28 0.0004419446 +29 chanx_left_in[17]:26 chanx_left_in[0]:61 0.0003643706 +30 chanx_left_in[17]:27 chanx_left_in[0]:60 0.0003643706 +31 chanx_left_in[17]:7 chanx_left_in[0]:15 5.694887e-05 +32 chanx_left_in[17]:6 chanx_left_in[0]:16 5.694887e-05 +33 chanx_left_in[17]:26 chanx_left_in[1]:49 1.529909e-05 +34 chanx_left_in[17]:27 chanx_left_in[1]:48 1.529909e-05 +35 chanx_left_in[17]:7 chanx_left_in[1]:22 0.0004761032 +36 chanx_left_in[17]:6 chanx_left_in[1]:21 0.0004761032 +37 chanx_left_in[17]:15 chanx_left_in[12]:17 0.0003436799 +38 chanx_left_in[17]:16 chanx_left_in[12]:18 0.0003436799 +39 chanx_left_in[17]:15 chanx_right_in[11] 2.851347e-05 +40 chanx_left_in[17]:15 chanx_right_in[11]:32 0.000191093 +41 chanx_left_in[17]:16 chanx_right_in[11]:31 0.000191093 +42 chanx_left_in[17]:16 chanx_right_in[11]:35 2.851347e-05 +43 chanx_left_in[17]:19 chanx_right_in[11]:32 7.421005e-06 +44 chanx_left_in[17]:20 chanx_right_in[11]:31 7.421005e-06 +45 chanx_left_in[17]:24 chanx_right_in[11]:31 0.0007163155 +46 chanx_left_in[17]:25 chanx_right_in[11]:26 0.0007163155 +47 chanx_left_in[17]:15 chanx_right_in[19]:31 9.049049e-05 +48 chanx_left_in[17]:16 chanx_right_in[19]:30 9.049049e-05 +49 chanx_left_in[17]:24 chanx_right_in[19]:23 0.0004510916 +50 chanx_left_in[17]:24 chanx_right_in[19]:19 2.52103e-07 +51 chanx_left_in[17]:25 chanx_right_in[19]:22 0.0004510916 +52 chanx_left_in[17]:25 chanx_right_in[19]:18 2.52103e-07 +53 chanx_left_in[17] prog_clk[0]:366 2.442613e-06 +54 chanx_left_in[17] prog_clk[0]:365 2.367839e-07 +55 chanx_left_in[17]:13 prog_clk[0]:223 9.384105e-07 +56 chanx_left_in[17]:13 prog_clk[0]:220 1.011207e-06 +57 chanx_left_in[17]:15 prog_clk[0]:172 1.736545e-06 +58 chanx_left_in[17]:16 prog_clk[0]:173 1.736545e-06 +59 chanx_left_in[17]:24 prog_clk[0]:346 0.0001964125 +60 chanx_left_in[17]:24 prog_clk[0]:351 0.0001315331 +61 chanx_left_in[17]:24 prog_clk[0]:336 0.0004167451 +62 chanx_left_in[17]:25 prog_clk[0]:351 0.0001964125 +63 chanx_left_in[17]:25 prog_clk[0]:352 0.0001315331 +64 chanx_left_in[17]:25 prog_clk[0]:337 0.0004167451 +65 chanx_left_in[17]:28 prog_clk[0]:332 2.367839e-07 +66 chanx_left_in[17]:28 prog_clk[0]:365 2.442613e-06 +67 chanx_left_in[17]:10 prog_clk[0]:223 1.011207e-06 +68 chanx_left_in[17]:10 prog_clk[0]:226 9.384105e-07 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:28 0.0008131 +1 chanx_left_in[17]:11 mux_bottom_ipin_13\/mux_l2_in_2_:A0 0.152 +2 chanx_left_in[17]:12 chanx_left_in[17]:11 0.0004799107 +3 chanx_left_in[17]:13 chanx_left_in[17]:12 0.0045 +4 chanx_left_in[17]:13 chanx_left_in[17]:10 0.008145089 +5 chanx_left_in[17]:14 chanx_left_in[17]:13 0.004502233 +6 chanx_left_in[17]:15 chanx_left_in[17]:14 0.00341 +7 chanx_left_in[17]:17 chanx_left_in[17]:16 0.00341 +8 chanx_left_in[17]:16 chanx_left_in[17]:15 0.005330583 +9 chanx_left_in[17]:19 chanx_left_in[17]:18 0.0045 +10 chanx_left_in[17]:18 chanx_left_in[17]:17 0.001426339 +11 chanx_left_in[17]:20 mux_bottom_ipin_1\/mux_l2_in_2_:A0 0.152 +12 chanx_left_in[17]:20 chanx_left_in[17]:19 0.003397322 +13 chanx_left_in[17]:21 chanx_left_in[17]:20 0.004325893 +14 chanx_left_in[17]:22 chanx_left_in[17]:21 0.0045 +15 chanx_left_in[17]:23 chanx_left_in[17]:22 0.0008191965 +16 chanx_left_in[17]:24 chanx_left_in[17]:23 0.00341 +17 chanx_left_in[17]:25 chanx_left_in[17]:24 0.006625825 +18 chanx_left_in[17]:26 chanx_left_in[17]:25 0.00341 +19 chanx_left_in[17]:28 chanx_left_in[17]:27 0.00341 +20 chanx_left_in[17]:27 chanx_left_in[17]:26 0.003726316 +21 chanx_left_in[17]:10 chanx_left_in[17]:9 0.00341 +22 chanx_left_in[17]:9 chanx_left_in[17]:8 0.0008624499 +23 chanx_left_in[17]:7 chanx_left_in[17]:6 0.0156942 +24 chanx_left_in[17]:8 chanx_left_in[17]:7 0.00341 +25 chanx_left_in[17]:5 chanx_left_in[17]:4 0.0003370536 +26 chanx_left_in[17]:6 chanx_left_in[17]:5 0.0045 +27 chanx_left_in[17]:4 FTB_18__17:A 0.152 + +*END + +*D_NET chanx_right_in[2] 0.02448028 //LENGTH 152.660 LUMPCC 0.0101948 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 103.650 55.760 +*I mux_bottom_ipin_14\/mux_l2_in_1_:A1 I *L 0.00198 *C 83.625 39.780 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.950 26.180 +*I mux_bottom_ipin_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 40.385 23.460 +*I mux_bottom_ipin_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 44.795 22.780 +*I mux_bottom_ipin_10\/mux_l2_in_1_:A1 I *L 0.00198 *C 18.400 20.060 +*I mux_bottom_ipin_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 13.975 26.180 +*I BUFT_P_98:A I *L 0.001767 *C 6.900 28.560 +*I mux_bottom_ipin_12\/mux_l1_in_1_:A0 I *L 0.001631 *C 71.015 22.440 +*I mux_bottom_ipin_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 80.865 34.340 +*N chanx_right_in[2]:10 *C 80.828 34.340 +*N chanx_right_in[2]:11 *C 80.500 34.340 +*N chanx_right_in[2]:12 *C 71.015 22.440 +*N chanx_right_in[2]:13 *C 71.300 22.440 +*N chanx_right_in[2]:14 *C 6.938 28.560 +*N chanx_right_in[2]:15 *C 9.155 28.560 +*N chanx_right_in[2]:16 *C 9.200 28.515 +*N chanx_right_in[2]:17 *C 9.200 26.225 +*N chanx_right_in[2]:18 *C 9.245 26.180 +*N chanx_right_in[2]:19 *C 13.938 26.180 +*N chanx_right_in[2]:20 *C 14.260 26.180 +*N chanx_right_in[2]:21 *C 14.260 26.135 +*N chanx_right_in[2]:22 *C 14.260 22.498 +*N chanx_right_in[2]:23 *C 14.268 22.440 +*N chanx_right_in[2]:24 *C 18.400 20.060 +*N chanx_right_in[2]:25 *C 18.400 20.105 +*N chanx_right_in[2]:26 *C 18.400 22.383 +*N chanx_right_in[2]:27 *C 18.400 22.440 +*N chanx_right_in[2]:28 *C 44.670 22.780 +*N chanx_right_in[2]:29 *C 40.385 23.460 +*N chanx_right_in[2]:30 *C 40.480 23.120 +*N chanx_right_in[2]:31 *C 40.940 23.120 +*N chanx_right_in[2]:32 *C 40.940 22.780 +*N chanx_right_in[2]:33 *C 44.575 22.780 +*N chanx_right_in[2]:34 *C 44.620 22.780 +*N chanx_right_in[2]:35 *C 44.620 22.440 +*N chanx_right_in[2]:36 *C 44.620 22.433 +*N chanx_right_in[2]:37 *C 44.620 21.760 +*N chanx_right_in[2]:38 *C 54.280 21.760 +*N chanx_right_in[2]:39 *C 54.280 22.440 +*N chanx_right_in[2]:40 *C 71.293 22.440 +*N chanx_right_in[2]:41 *C 71.300 22.440 +*N chanx_right_in[2]:42 *C 71.760 22.440 +*N chanx_right_in[2]:43 *C 71.760 23.755 +*N chanx_right_in[2]:44 *C 71.805 23.800 +*N chanx_right_in[2]:45 *C 78.615 23.800 +*N chanx_right_in[2]:46 *C 78.660 23.845 +*N chanx_right_in[2]:47 *C 78.950 26.180 +*N chanx_right_in[2]:48 *C 78.660 26.180 +*N chanx_right_in[2]:49 *C 78.660 26.180 +*N chanx_right_in[2]:50 *C 78.660 34.635 +*N chanx_right_in[2]:51 *C 78.705 34.680 +*N chanx_right_in[2]:52 *C 80.500 34.680 +*N chanx_right_in[2]:53 *C 83.675 34.680 +*N chanx_right_in[2]:54 *C 83.720 34.725 +*N chanx_right_in[2]:55 *C 83.625 39.780 +*N chanx_right_in[2]:56 *C 83.720 39.780 +*N chanx_right_in[2]:57 *C 83.720 55.703 +*N chanx_right_in[2]:58 *C 83.728 55.760 + +*CAP +0 chanx_right_in[2] 0.000620297 +1 mux_bottom_ipin_14\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_ipin_2\/mux_l2_in_1_:A1 1e-06 +4 mux_bottom_ipin_4\/mux_l1_in_1_:A0 1e-06 +5 mux_bottom_ipin_10\/mux_l2_in_1_:A1 1e-06 +6 mux_bottom_ipin_8\/mux_l1_in_1_:A0 1e-06 +7 BUFT_P_98:A 1e-06 +8 mux_bottom_ipin_12\/mux_l1_in_1_:A0 1e-06 +9 mux_bottom_ipin_6\/mux_l2_in_1_:A1 1e-06 +10 chanx_right_in[2]:10 2.766862e-05 +11 chanx_right_in[2]:11 5.532355e-05 +12 chanx_right_in[2]:12 5.320093e-05 +13 chanx_right_in[2]:13 5.397698e-05 +14 chanx_right_in[2]:14 0.0001510254 +15 chanx_right_in[2]:15 0.0001510254 +16 chanx_right_in[2]:16 0.0001865711 +17 chanx_right_in[2]:17 0.0001865711 +18 chanx_right_in[2]:18 0.0003111796 +19 chanx_right_in[2]:19 0.0003369295 +20 chanx_right_in[2]:20 6.084987e-05 +21 chanx_right_in[2]:21 0.0001782435 +22 chanx_right_in[2]:22 0.0001782435 +23 chanx_right_in[2]:23 0.0001639229 +24 chanx_right_in[2]:24 3.42373e-05 +25 chanx_right_in[2]:25 0.0001527593 +26 chanx_right_in[2]:26 0.0001527593 +27 chanx_right_in[2]:27 0.0008499337 +28 chanx_right_in[2]:28 2.246535e-05 +29 chanx_right_in[2]:29 5.356143e-05 +30 chanx_right_in[2]:30 7.156248e-05 +31 chanx_right_in[2]:31 7.314088e-05 +32 chanx_right_in[2]:32 0.0002526323 +33 chanx_right_in[2]:33 0.0002490451 +34 chanx_right_in[2]:34 5.419161e-05 +35 chanx_right_in[2]:35 5.830335e-05 +36 chanx_right_in[2]:36 0.0007479489 +37 chanx_right_in[2]:37 0.0003486013 +38 chanx_right_in[2]:38 0.0003421279 +39 chanx_right_in[2]:39 0.0009526852 +40 chanx_right_in[2]:40 0.0008972206 +41 chanx_right_in[2]:41 6.539238e-05 +42 chanx_right_in[2]:42 0.0001424139 +43 chanx_right_in[2]:43 0.0001101537 +44 chanx_right_in[2]:44 0.0004940973 +45 chanx_right_in[2]:45 0.0004940973 +46 chanx_right_in[2]:46 0.0001318016 +47 chanx_right_in[2]:47 5.390615e-05 +48 chanx_right_in[2]:48 5.606139e-05 +49 chanx_right_in[2]:49 0.0006802745 +50 chanx_right_in[2]:50 0.0005181707 +51 chanx_right_in[2]:51 0.000141804 +52 chanx_right_in[2]:52 0.0004060108 +53 chanx_right_in[2]:53 0.0002365519 +54 chanx_right_in[2]:54 0.0002534149 +55 chanx_right_in[2]:55 3.472748e-05 +56 chanx_right_in[2]:56 0.001046493 +57 chanx_right_in[2]:57 0.000762613 +58 chanx_right_in[2]:58 0.000620297 +59 chanx_right_in[2]:27 chanx_left_in[8]:26 0.0002286186 +60 chanx_right_in[2]:27 chanx_left_in[8]:30 0.001465038 +61 chanx_right_in[2]:21 chanx_left_in[8]:28 1.027577e-05 +62 chanx_right_in[2]:22 chanx_left_in[8]:29 1.027577e-05 +63 chanx_right_in[2]:23 chanx_left_in[8]:30 0.0002286186 +64 chanx_right_in[2]:36 chanx_left_in[8]:26 0.001465038 +65 chanx_right_in[2]:37 chanx_left_in[8]:26 3.862565e-06 +66 chanx_right_in[2]:37 chanx_left_in[8]:30 0.000179098 +67 chanx_right_in[2]:38 chanx_left_in[8]:21 3.862565e-06 +68 chanx_right_in[2]:38 chanx_left_in[8]:26 0.000179098 +69 chanx_right_in[2] chanx_left_in[14]:9 0.0005432105 +70 chanx_right_in[2]:25 chanx_left_in[14]:26 4.178823e-06 +71 chanx_right_in[2]:26 chanx_left_in[14]:25 4.178823e-06 +72 chanx_right_in[2]:27 chanx_left_in[14] 1.132628e-05 +73 chanx_right_in[2]:27 chanx_left_in[14]:21 0.0001447042 +74 chanx_right_in[2]:27 chanx_left_in[14]:27 9.065453e-05 +75 chanx_right_in[2]:23 chanx_left_in[14] 4.221411e-05 +76 chanx_right_in[2]:40 chanx_left_in[14]:13 4.775416e-05 +77 chanx_right_in[2]:40 chanx_left_in[14]:17 9.560572e-05 +78 chanx_right_in[2]:36 chanx_left_in[14]:17 0.0001447042 +79 chanx_right_in[2]:36 chanx_left_in[14]:22 4.844042e-05 +80 chanx_right_in[2]:36 chanx_left_in[14]:27 1.132628e-05 +81 chanx_right_in[2]:58 chanx_left_in[14]:10 0.0005432105 +82 chanx_right_in[2]:37 chanx_left_in[14]:21 0.0005469696 +83 chanx_right_in[2]:38 chanx_left_in[14]:17 0.0005469696 +84 chanx_right_in[2]:39 chanx_left_in[14]:17 4.775416e-05 +85 chanx_right_in[2]:39 chanx_left_in[14]:21 9.560572e-05 +86 chanx_right_in[2] chanx_right_in[1] 0.000128179 +87 chanx_right_in[2] chanx_right_in[1]:44 0.0008010524 +88 chanx_right_in[2]:58 chanx_right_in[1]:43 0.0008010524 +89 chanx_right_in[2]:58 chanx_right_in[1]:49 0.000128179 +90 chanx_right_in[2]:25 chanx_right_in[6]:20 8.833927e-06 +91 chanx_right_in[2]:26 chanx_right_in[6]:19 8.833927e-06 +92 chanx_right_in[2]:27 chanx_right_in[6]:21 0.0003152411 +93 chanx_right_in[2]:36 chanx_right_in[6]:22 0.0003152411 +94 chanx_right_in[2]:21 chanx_right_in[8]:6 3.193836e-06 +95 chanx_right_in[2]:22 chanx_right_in[8]:11 3.193836e-06 +96 chanx_right_in[2]:40 chanx_right_in[8]:28 0.0002523658 +97 chanx_right_in[2]:39 chanx_right_in[8]:27 0.0002523658 +98 chanx_right_in[2]:21 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.950391e-05 +99 chanx_right_in[2]:22 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.950391e-05 +100 chanx_right_in[2]:54 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.419522e-05 +101 chanx_right_in[2]:57 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.286238e-05 +102 chanx_right_in[2]:56 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.419522e-05 +103 chanx_right_in[2]:56 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.286238e-05 +104 chanx_right_in[2]:57 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.067324e-05 +105 chanx_right_in[2]:56 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.067324e-05 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:58 0.003121192 +1 chanx_right_in[2]:24 mux_bottom_ipin_10\/mux_l2_in_1_:A1 0.152 +2 chanx_right_in[2]:25 chanx_right_in[2]:24 0.0045 +3 chanx_right_in[2]:26 chanx_right_in[2]:25 0.002033482 +4 chanx_right_in[2]:27 chanx_right_in[2]:26 0.00341 +5 chanx_right_in[2]:27 chanx_right_in[2]:23 0.000647425 +6 chanx_right_in[2]:20 chanx_right_in[2]:19 0.0001752718 +7 chanx_right_in[2]:21 chanx_right_in[2]:20 0.0045 +8 chanx_right_in[2]:22 chanx_right_in[2]:21 0.003247768 +9 chanx_right_in[2]:23 chanx_right_in[2]:22 0.00341 +10 chanx_right_in[2]:41 chanx_right_in[2]:40 0.00341 +11 chanx_right_in[2]:41 chanx_right_in[2]:13 0.0045 +12 chanx_right_in[2]:40 chanx_right_in[2]:39 0.002665292 +13 chanx_right_in[2]:53 chanx_right_in[2]:52 0.002834822 +14 chanx_right_in[2]:54 chanx_right_in[2]:53 0.0045 +15 chanx_right_in[2]:33 chanx_right_in[2]:32 0.003245536 +16 chanx_right_in[2]:33 chanx_right_in[2]:28 8.482143e-05 +17 chanx_right_in[2]:34 chanx_right_in[2]:33 0.0045 +18 chanx_right_in[2]:35 chanx_right_in[2]:34 0.0001634615 +19 chanx_right_in[2]:36 chanx_right_in[2]:35 0.00341 +20 chanx_right_in[2]:36 chanx_right_in[2]:27 0.0041078 +21 chanx_right_in[2]:57 chanx_right_in[2]:56 0.01421652 +22 chanx_right_in[2]:58 chanx_right_in[2]:57 0.00341 +23 chanx_right_in[2]:51 chanx_right_in[2]:50 0.0045 +24 chanx_right_in[2]:50 chanx_right_in[2]:49 0.007549107 +25 chanx_right_in[2]:18 chanx_right_in[2]:17 0.0045 +26 chanx_right_in[2]:17 chanx_right_in[2]:16 0.002044643 +27 chanx_right_in[2]:15 chanx_right_in[2]:14 0.001979911 +28 chanx_right_in[2]:16 chanx_right_in[2]:15 0.0045 +29 chanx_right_in[2]:14 BUFT_P_98:A 0.152 +30 chanx_right_in[2]:29 mux_bottom_ipin_2\/mux_l2_in_1_:A1 0.152 +31 chanx_right_in[2]:13 chanx_right_in[2]:12 0.0001548913 +32 chanx_right_in[2]:12 mux_bottom_ipin_12\/mux_l1_in_1_:A0 0.152 +33 chanx_right_in[2]:28 mux_bottom_ipin_4\/mux_l1_in_1_:A0 0.152 +34 chanx_right_in[2]:10 mux_bottom_ipin_6\/mux_l2_in_1_:A1 0.152 +35 chanx_right_in[2]:55 mux_bottom_ipin_14\/mux_l2_in_1_:A1 0.152 +36 chanx_right_in[2]:56 chanx_right_in[2]:55 0.0045 +37 chanx_right_in[2]:56 chanx_right_in[2]:54 0.004513393 +38 chanx_right_in[2]:19 mux_bottom_ipin_8\/mux_l1_in_1_:A0 0.152 +39 chanx_right_in[2]:19 chanx_right_in[2]:18 0.004189732 +40 chanx_right_in[2]:48 chanx_right_in[2]:47 0.0001576087 +41 chanx_right_in[2]:49 chanx_right_in[2]:48 0.0045 +42 chanx_right_in[2]:49 chanx_right_in[2]:46 0.002084821 +43 chanx_right_in[2]:47 mux_bottom_ipin_0\/mux_l1_in_1_:A0 0.152 +44 chanx_right_in[2]:44 chanx_right_in[2]:43 0.0045 +45 chanx_right_in[2]:43 chanx_right_in[2]:42 0.001174107 +46 chanx_right_in[2]:45 chanx_right_in[2]:44 0.006080357 +47 chanx_right_in[2]:46 chanx_right_in[2]:45 0.0045 +48 chanx_right_in[2]:30 chanx_right_in[2]:29 0.0003035714 +49 chanx_right_in[2]:31 chanx_right_in[2]:30 0.0004107143 +50 chanx_right_in[2]:32 chanx_right_in[2]:31 0.0003035714 +51 chanx_right_in[2]:52 chanx_right_in[2]:51 0.001602679 +52 chanx_right_in[2]:52 chanx_right_in[2]:11 0.0003035714 +53 chanx_right_in[2]:11 chanx_right_in[2]:10 0.0002924107 +54 chanx_right_in[2]:42 chanx_right_in[2]:41 0.0004107143 +55 chanx_right_in[2]:37 chanx_right_in[2]:36 0.0001053583 +56 chanx_right_in[2]:38 chanx_right_in[2]:37 0.0015134 +57 chanx_right_in[2]:39 chanx_right_in[2]:38 0.0001065333 + +*END + +*D_NET chanx_right_in[14] 0.02386158 //LENGTH 161.830 LUMPCC 0.008587485 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 103.650 27.200 +*I mux_bottom_ipin_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 42.225 20.060 +*I mux_bottom_ipin_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 55.300 20.060 +*I BUFT_P_102:A I *L 0.001767 *C 6.900 58.480 +*I mux_bottom_ipin_10\/mux_l2_in_3_:A1 I *L 0.00198 *C 23.825 23.460 +*N chanx_right_in[14]:5 *C 6.938 58.480 +*N chanx_right_in[14]:6 *C 9.155 58.480 +*N chanx_right_in[14]:7 *C 9.200 58.435 +*N chanx_right_in[14]:8 *C 9.200 55.818 +*N chanx_right_in[14]:9 *C 9.207 55.760 +*N chanx_right_in[14]:10 *C 22.060 55.760 +*N chanx_right_in[14]:11 *C 22.080 55.753 +*N chanx_right_in[14]:12 *C 22.080 27.888 +*N chanx_right_in[14]:13 *C 22.100 27.880 +*N chanx_right_in[14]:14 *C 23.913 27.880 +*N chanx_right_in[14]:15 *C 23.920 27.823 +*N chanx_right_in[14]:16 *C 23.920 23.505 +*N chanx_right_in[14]:17 *C 23.965 23.460 +*N chanx_right_in[14]:18 *C 27.555 23.460 +*N chanx_right_in[14]:19 *C 27.600 23.415 +*N chanx_right_in[14]:20 *C 27.600 19.777 +*N chanx_right_in[14]:21 *C 27.608 19.720 +*N chanx_right_in[14]:22 *C 55.300 20.060 +*N chanx_right_in[14]:23 *C 55.200 19.720 +*N chanx_right_in[14]:24 *C 42.263 20.060 +*N chanx_right_in[14]:25 *C 43.240 20.060 +*N chanx_right_in[14]:26 *C 43.240 19.720 +*N chanx_right_in[14]:27 *C 43.240 19.720 +*N chanx_right_in[14]:28 *C 43.240 19.720 +*N chanx_right_in[14]:29 *C 55.180 19.720 +*N chanx_right_in[14]:30 *C 55.200 19.728 +*N chanx_right_in[14]:31 *C 55.200 25.152 +*N chanx_right_in[14]:32 *C 55.220 25.160 +*N chanx_right_in[14]:33 *C 101.653 25.160 +*N chanx_right_in[14]:34 *C 101.660 25.218 +*N chanx_right_in[14]:35 *C 101.660 27.143 +*N chanx_right_in[14]:36 *C 101.668 27.200 + +*CAP +0 chanx_right_in[14] 0.0001528571 +1 mux_bottom_ipin_2\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_4\/mux_l2_in_3_:A1 1e-06 +3 BUFT_P_102:A 1e-06 +4 mux_bottom_ipin_10\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[14]:5 0.0001764973 +6 chanx_right_in[14]:6 0.0001764973 +7 chanx_right_in[14]:7 0.0001640666 +8 chanx_right_in[14]:8 0.0001640666 +9 chanx_right_in[14]:9 0.0009134401 +10 chanx_right_in[14]:10 0.0009134401 +11 chanx_right_in[14]:11 0.0008667385 +12 chanx_right_in[14]:12 0.0008667385 +13 chanx_right_in[14]:13 0.0001539189 +14 chanx_right_in[14]:14 0.0001539189 +15 chanx_right_in[14]:15 0.000264929 +16 chanx_right_in[14]:16 0.000264929 +17 chanx_right_in[14]:17 0.0002665317 +18 chanx_right_in[14]:18 0.0002665317 +19 chanx_right_in[14]:19 0.0001885745 +20 chanx_right_in[14]:20 0.0001885745 +21 chanx_right_in[14]:21 0.0004171713 +22 chanx_right_in[14]:22 6.426392e-05 +23 chanx_right_in[14]:23 0.0006865534 +24 chanx_right_in[14]:24 6.303396e-05 +25 chanx_right_in[14]:25 9.117388e-05 +26 chanx_right_in[14]:26 0.0006827742 +27 chanx_right_in[14]:27 3.815803e-05 +28 chanx_right_in[14]:28 0.0008296472 +29 chanx_right_in[14]:29 0.0004124758 +30 chanx_right_in[14]:30 0.0003496842 +31 chanx_right_in[14]:31 0.0003496842 +32 chanx_right_in[14]:32 0.002383883 +33 chanx_right_in[14]:33 0.002383883 +34 chanx_right_in[14]:34 0.0001113003 +35 chanx_right_in[14]:35 0.0001113003 +36 chanx_right_in[14]:36 0.0001528571 +37 chanx_right_in[14]:29 chanx_left_in[6]:15 0.0002451116 +38 chanx_right_in[14]:28 chanx_left_in[6]:15 6.664135e-05 +39 chanx_right_in[14]:28 chanx_left_in[6]:20 0.0005312938 +40 chanx_right_in[14]:21 chanx_left_in[6]:20 6.664135e-05 +41 chanx_right_in[14]:21 chanx_left_in[6]:21 0.0002861822 +42 chanx_right_in[14]:29 chanx_left_in[14]:17 0.000265763 +43 chanx_right_in[14]:32 chanx_left_in[14]:21 1.217404e-06 +44 chanx_right_in[14]:33 chanx_left_in[14]:17 1.217404e-06 +45 chanx_right_in[14]:28 chanx_left_in[14]:17 8.888706e-05 +46 chanx_right_in[14]:28 chanx_left_in[14]:21 0.000265763 +47 chanx_right_in[14]:28 chanx_left_in[14]:22 0.0006049639 +48 chanx_right_in[14]:21 chanx_left_in[14]:21 8.888706e-05 +49 chanx_right_in[14]:21 chanx_left_in[14]:27 0.0006049639 +50 chanx_right_in[14] chanx_right_in[6] 2.568117e-06 +51 chanx_right_in[14]:29 chanx_right_in[6]:27 1.609264e-05 +52 chanx_right_in[14]:32 chanx_right_in[6]:40 0.0001208405 +53 chanx_right_in[14]:33 chanx_right_in[6] 0.0001208405 +54 chanx_right_in[14]:36 chanx_right_in[6]:40 2.568117e-06 +55 chanx_right_in[14]:26 chanx_right_in[6]:26 0.000167586 +56 chanx_right_in[14]:28 chanx_right_in[6]:26 1.609264e-05 +57 chanx_right_in[14]:24 chanx_right_in[6]:26 4.614717e-05 +58 chanx_right_in[14]:25 chanx_right_in[6]:27 4.614717e-05 +59 chanx_right_in[14]:23 chanx_right_in[6]:27 0.000167586 +60 chanx_right_in[14]:12 chanx_right_in[19]:14 0.0003334206 +61 chanx_right_in[14]:11 chanx_right_in[19]:20 0.0003334206 +62 chanx_right_in[14]:30 prog_clk[0]:128 4.142711e-06 +63 chanx_right_in[14]:32 prog_clk[0]:99 0.0001332472 +64 chanx_right_in[14]:32 prog_clk[0]:93 0.0001814741 +65 chanx_right_in[14]:32 prog_clk[0]:98 7.440128e-05 +66 chanx_right_in[14]:31 prog_clk[0]:127 4.142711e-06 +67 chanx_right_in[14]:33 prog_clk[0]:93 7.440128e-05 +68 chanx_right_in[14]:33 prog_clk[0]:98 0.0001332472 +69 chanx_right_in[14]:33 prog_clk[0]:89 0.0001814741 +70 chanx_right_in[14]:16 prog_clk[0]:308 2.144257e-06 +71 chanx_right_in[14]:16 prog_clk[0]:307 7.554289e-07 +72 chanx_right_in[14]:15 prog_clk[0]:304 7.554289e-07 +73 chanx_right_in[14]:15 prog_clk[0]:307 2.144257e-06 +74 chanx_right_in[14]:8 prog_clk[0]:360 8.531026e-07 +75 chanx_right_in[14]:7 prog_clk[0]:356 8.531026e-07 +76 chanx_right_in[14]:16 mux_tree_tapbuf_size10_4_sram[0]:22 4.629596e-08 +77 chanx_right_in[14]:15 mux_tree_tapbuf_size10_4_sram[0]:23 4.629596e-08 +78 chanx_right_in[14]:12 mux_tree_tapbuf_size10_4_sram[0]:25 0.001030733 +79 chanx_right_in[14]:11 mux_tree_tapbuf_size10_4_sram[0]:26 0.001030733 +80 chanx_right_in[14]:14 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 7.042125e-06 +81 chanx_right_in[14]:13 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 7.042125e-06 +82 chanx_right_in[14]:20 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 4.599909e-05 +83 chanx_right_in[14]:19 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 4.599909e-05 +84 chanx_right_in[14]:32 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.000445693 +85 chanx_right_in[14]:33 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.000445693 +86 chanx_right_in[14]:32 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00012179 +87 chanx_right_in[14]:33 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00012179 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:36 0.0003105917 +1 chanx_right_in[14]:29 chanx_right_in[14]:28 0.0018706 +2 chanx_right_in[14]:30 chanx_right_in[14]:29 0.00341 +3 chanx_right_in[14]:32 chanx_right_in[14]:31 0.00341 +4 chanx_right_in[14]:31 chanx_right_in[14]:30 0.0008499166 +5 chanx_right_in[14]:34 chanx_right_in[14]:33 0.00341 +6 chanx_right_in[14]:33 chanx_right_in[14]:32 0.007274425 +7 chanx_right_in[14]:35 chanx_right_in[14]:34 0.00171875 +8 chanx_right_in[14]:36 chanx_right_in[14]:35 0.00341 +9 chanx_right_in[14]:22 mux_bottom_ipin_4\/mux_l2_in_3_:A1 0.152 +10 chanx_right_in[14]:26 chanx_right_in[14]:25 0.0003035715 +11 chanx_right_in[14]:26 chanx_right_in[14]:23 0.01067857 +12 chanx_right_in[14]:27 chanx_right_in[14]:26 0.0045 +13 chanx_right_in[14]:28 chanx_right_in[14]:27 0.00341 +14 chanx_right_in[14]:28 chanx_right_in[14]:21 0.002449092 +15 chanx_right_in[14]:17 chanx_right_in[14]:16 0.0045 +16 chanx_right_in[14]:17 mux_bottom_ipin_10\/mux_l2_in_3_:A1 0.152 +17 chanx_right_in[14]:16 chanx_right_in[14]:15 0.003854911 +18 chanx_right_in[14]:15 chanx_right_in[14]:14 0.00341 +19 chanx_right_in[14]:14 chanx_right_in[14]:13 0.0002839583 +20 chanx_right_in[14]:13 chanx_right_in[14]:12 0.00341 +21 chanx_right_in[14]:12 chanx_right_in[14]:11 0.004365516 +22 chanx_right_in[14]:10 chanx_right_in[14]:9 0.002013558 +23 chanx_right_in[14]:11 chanx_right_in[14]:10 0.00341 +24 chanx_right_in[14]:8 chanx_right_in[14]:7 0.002337054 +25 chanx_right_in[14]:9 chanx_right_in[14]:8 0.00341 +26 chanx_right_in[14]:6 chanx_right_in[14]:5 0.001979911 +27 chanx_right_in[14]:7 chanx_right_in[14]:6 0.0045 +28 chanx_right_in[14]:5 BUFT_P_102:A 0.152 +29 chanx_right_in[14]:24 mux_bottom_ipin_2\/mux_l2_in_3_:A1 0.152 +30 chanx_right_in[14]:20 chanx_right_in[14]:19 0.003247768 +31 chanx_right_in[14]:21 chanx_right_in[14]:20 0.00341 +32 chanx_right_in[14]:18 chanx_right_in[14]:17 0.003205357 +33 chanx_right_in[14]:19 chanx_right_in[14]:18 0.0045 +34 chanx_right_in[14]:25 chanx_right_in[14]:24 0.0008727679 +35 chanx_right_in[14]:23 chanx_right_in[14]:22 0.0003035715 + +*END + +*D_NET ropt_net_134 0.002544283 //LENGTH 21.645 LUMPCC 0.0004791647 DR + +*CONN +*I mux_bottom_ipin_0\/BUFT_RR_56:X O *L 0 *C 51.520 70.040 +*I ropt_mt_inst_731:A I *L 0.001766 *C 37.260 69.360 +*N ropt_net_134:2 *C 37.297 69.360 +*N ropt_net_134:3 *C 39.055 69.360 +*N ropt_net_134:4 *C 39.100 69.405 +*N ropt_net_134:5 *C 39.100 72.715 +*N ropt_net_134:6 *C 39.145 72.760 +*N ropt_net_134:7 *C 51.475 72.760 +*N ropt_net_134:8 *C 51.520 72.715 +*N ropt_net_134:9 *C 51.520 70.085 +*N ropt_net_134:10 *C 51.520 70.040 + +*CAP +0 mux_bottom_ipin_0\/BUFT_RR_56:X 1e-06 +1 ropt_mt_inst_731:A 1e-06 +2 ropt_net_134:2 0.0001057053 +3 ropt_net_134:3 0.0001057053 +4 ropt_net_134:4 0.0001385238 +5 ropt_net_134:5 0.0001385238 +6 ropt_net_134:6 0.0006819909 +7 ropt_net_134:7 0.0006819909 +8 ropt_net_134:8 8.835616e-05 +9 ropt_net_134:9 8.835616e-05 +10 ropt_net_134:10 3.396626e-05 +11 ropt_net_134:4 top_grid_pin_17_[0]:6 2.626561e-06 +12 ropt_net_134:6 top_grid_pin_17_[0]:3 6.623229e-05 +13 ropt_net_134:5 top_grid_pin_17_[0]:5 2.626561e-06 +14 ropt_net_134:7 top_grid_pin_17_[0]:4 6.623229e-05 +15 ropt_net_134:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.687388e-05 +16 ropt_net_134:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.687388e-05 +17 ropt_net_134:2 top_grid_pin_16_[0]:7 4.569483e-05 +18 ropt_net_134:3 top_grid_pin_16_[0]:8 4.569483e-05 +19 ropt_net_134:4 top_grid_pin_16_[0]:6 4.81548e-05 +20 ropt_net_134:5 top_grid_pin_16_[0]:5 4.81548e-05 + +*RES +0 mux_bottom_ipin_0\/BUFT_RR_56:X ropt_net_134:10 0.152 +1 ropt_net_134:2 ropt_mt_inst_731:A 0.152 +2 ropt_net_134:3 ropt_net_134:2 0.001569197 +3 ropt_net_134:4 ropt_net_134:3 0.0045 +4 ropt_net_134:6 ropt_net_134:5 0.0045 +5 ropt_net_134:5 ropt_net_134:4 0.002955357 +6 ropt_net_134:7 ropt_net_134:6 0.01100893 +7 ropt_net_134:8 ropt_net_134:7 0.0045 +8 ropt_net_134:10 ropt_net_134:9 0.0045 +9 ropt_net_134:9 ropt_net_134:8 0.002348214 + +*END + +*D_NET top_grid_pin_24_[0] 0.001289846 //LENGTH 10.995 LUMPCC 0.0001177989 DR + +*CONN +*I mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 66.300 +*P top_grid_pin_24_[0] O *L 0.7423 *C 2.300 74.870 +*N top_grid_pin_24_[0]:2 *C 2.300 71.785 +*N top_grid_pin_24_[0]:3 *C 2.345 71.740 +*N top_grid_pin_24_[0]:4 *C 3.635 71.740 +*N top_grid_pin_24_[0]:5 *C 3.680 71.695 +*N top_grid_pin_24_[0]:6 *C 3.680 67.025 +*N top_grid_pin_24_[0]:7 *C 3.680 66.980 +*N top_grid_pin_24_[0]:8 *C 3.625 66.300 + +*CAP +0 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_24_[0] 0.0001697072 +2 top_grid_pin_24_[0]:2 0.0001697072 +3 top_grid_pin_24_[0]:3 0.0001064319 +4 top_grid_pin_24_[0]:4 0.0001064319 +5 top_grid_pin_24_[0]:5 0.0002345784 +6 top_grid_pin_24_[0]:6 0.0002345784 +7 top_grid_pin_24_[0]:7 7.689044e-05 +8 top_grid_pin_24_[0]:8 7.272141e-05 +9 top_grid_pin_24_[0]:6 mem_bottom_ipin_15/net_net_74:3 5.889946e-05 +10 top_grid_pin_24_[0]:5 mem_bottom_ipin_15/net_net_74:4 5.889946e-05 + +*RES +0 mux_bottom_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_24_[0]:8 0.152 +1 top_grid_pin_24_[0]:8 top_grid_pin_24_[0]:7 0.0006071429 +2 top_grid_pin_24_[0]:7 top_grid_pin_24_[0]:6 0.0045 +3 top_grid_pin_24_[0]:6 top_grid_pin_24_[0]:5 0.004169643 +4 top_grid_pin_24_[0]:4 top_grid_pin_24_[0]:3 0.001151786 +5 top_grid_pin_24_[0]:5 top_grid_pin_24_[0]:4 0.0045 +6 top_grid_pin_24_[0]:3 top_grid_pin_24_[0]:2 0.0045 +7 top_grid_pin_24_[0]:2 top_grid_pin_24_[0] 0.002754465 + +*END + +*D_NET top_grid_pin_27_[0] 0.0009577946 //LENGTH 6.780 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 17.480 71.740 +*P top_grid_pin_27_[0] O *L 0.7423 *C 14.260 74.835 +*N top_grid_pin_27_[0]:2 *C 14.260 71.785 +*N top_grid_pin_27_[0]:3 *C 14.305 71.740 +*N top_grid_pin_27_[0]:4 *C 17.443 71.740 + +*CAP +0 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_27_[0] 0.0001927029 +2 top_grid_pin_27_[0]:2 0.0001927029 +3 top_grid_pin_27_[0]:3 0.0002856944 +4 top_grid_pin_27_[0]:4 0.0002856944 + +*RES +0 mux_bottom_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_27_[0]:4 0.152 +1 top_grid_pin_27_[0]:3 top_grid_pin_27_[0]:2 0.0045 +2 top_grid_pin_27_[0]:2 top_grid_pin_27_[0] 0.002723214 +3 top_grid_pin_27_[0]:4 top_grid_pin_27_[0]:3 0.00280134 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.006642362 //LENGTH 47.783 LUMPCC 0.0006564972 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 95.795 29.240 +*I mux_bottom_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 65.880 34.680 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 71.935 31.620 +*I mux_bottom_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 77.840 25.840 +*I mux_bottom_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 85.660 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 85.675 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 85.998 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 86.020 29.285 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 77.803 25.840 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 75.945 25.840 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 75.900 25.885 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 71.935 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 65.918 34.680 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 72.175 34.680 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 72.220 34.635 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 72.220 31.665 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 72.265 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 74.935 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 74.980 31.575 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 74.980 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 75.900 30.543 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 75.907 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 86.013 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 86.020 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:24 *C 86.065 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:25 *C 94.255 30.600 +*N mux_tree_tapbuf_size10_0_sram[0]:26 *C 94.300 30.555 +*N mux_tree_tapbuf_size10_0_sram[0]:27 *C 94.300 29.285 +*N mux_tree_tapbuf_size10_0_sram[0]:28 *C 94.345 29.240 +*N mux_tree_tapbuf_size10_0_sram[0]:29 *C 95.758 29.240 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_ipin_0\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_ipin_0\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 5.355812e-05 +6 mux_tree_tapbuf_size10_0_sram[0]:6 5.355812e-05 +7 mux_tree_tapbuf_size10_0_sram[0]:7 9.670967e-05 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.0001707743 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0001707743 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0003107609 +11 mux_tree_tapbuf_size10_0_sram[0]:11 4.85411e-05 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0003984046 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0003984046 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0001926003 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0001926003 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0002150365 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0001942473 +18 mux_tree_tapbuf_size10_0_sram[0]:18 7.137895e-05 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001243513 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.0003637333 +21 mux_tree_tapbuf_size10_0_sram[0]:21 0.0006143106 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.0006143106 +23 mux_tree_tapbuf_size10_0_sram[0]:23 0.0001372578 +24 mux_tree_tapbuf_size10_0_sram[0]:24 0.0005625039 +25 mux_tree_tapbuf_size10_0_sram[0]:25 0.0005625039 +26 mux_tree_tapbuf_size10_0_sram[0]:26 0.000101046 +27 mux_tree_tapbuf_size10_0_sram[0]:27 0.000101046 +28 mux_tree_tapbuf_size10_0_sram[0]:28 0.0001162259 +29 mux_tree_tapbuf_size10_0_sram[0]:29 0.0001162259 +30 mux_tree_tapbuf_size10_0_sram[0]:22 chanx_left_in[10]:12 0.0002870309 +31 mux_tree_tapbuf_size10_0_sram[0]:20 chanx_left_in[10]:16 1.089392e-05 +32 mux_tree_tapbuf_size10_0_sram[0]:21 chanx_left_in[10]:13 0.0002870309 +33 mux_tree_tapbuf_size10_0_sram[0]:13 chanx_left_in[10]:16 3.032381e-05 +34 mux_tree_tapbuf_size10_0_sram[0]:12 chanx_left_in[10]:21 3.032381e-05 +35 mux_tree_tapbuf_size10_0_sram[0]:19 chanx_left_in[10]:21 1.089392e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:29 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:29 mux_tree_tapbuf_size10_0_sram[0]:28 0.001261161 +2 mux_tree_tapbuf_size10_0_sram[0]:28 mux_tree_tapbuf_size10_0_sram[0]:27 0.0045 +3 mux_tree_tapbuf_size10_0_sram[0]:27 mux_tree_tapbuf_size10_0_sram[0]:26 0.001133929 +4 mux_tree_tapbuf_size10_0_sram[0]:25 mux_tree_tapbuf_size10_0_sram[0]:24 0.0073125 +5 mux_tree_tapbuf_size10_0_sram[0]:26 mux_tree_tapbuf_size10_0_sram[0]:25 0.0045 +6 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:23 0.0045 +7 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.00341 +8 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:7 0.001174107 +9 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.001583117 +10 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0008214285 +11 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:10 0.004158482 +12 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.00341 +13 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.002383929 +14 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.0045 +15 mux_tree_tapbuf_size10_0_sram[0]:11 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.0001752718 +17 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0045 +18 mux_tree_tapbuf_size10_0_sram[0]:5 mux_bottom_ipin_0\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.0045 +20 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:11 0.0001793478 +21 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_0_sram[0]:14 0.002651786 +22 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.005587054 +23 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +24 mux_tree_tapbuf_size10_0_sram[0]:12 mux_bottom_ipin_0\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size10_0_sram[0]:9 mux_tree_tapbuf_size10_0_sram[0]:8 0.001658482 +26 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.0045 +27 mux_tree_tapbuf_size10_0_sram[0]:8 mux_bottom_ipin_0\/mux_l1_in_1_:S 0.152 +28 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.0008705357 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[2] 0.003184228 //LENGTH 24.350 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 56.425 15.300 +*I mux_bottom_ipin_4\/mux_l3_in_1_:S I *L 0.00357 *C 56.220 23.120 +*I mux_bottom_ipin_4\/mux_l3_in_0_:S I *L 0.00357 *C 52.340 25.550 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 49.855 31.620 +*N mux_tree_tapbuf_size10_2_sram[2]:4 *C 49.855 31.620 +*N mux_tree_tapbuf_size10_2_sram[2]:5 *C 50.140 31.620 +*N mux_tree_tapbuf_size10_2_sram[2]:6 *C 50.140 31.575 +*N mux_tree_tapbuf_size10_2_sram[2]:7 *C 50.140 25.885 +*N mux_tree_tapbuf_size10_2_sram[2]:8 *C 50.185 25.840 +*N mux_tree_tapbuf_size10_2_sram[2]:9 *C 52.283 25.840 +*N mux_tree_tapbuf_size10_2_sram[2]:10 *C 52.340 25.550 +*N mux_tree_tapbuf_size10_2_sram[2]:11 *C 52.340 25.160 +*N mux_tree_tapbuf_size10_2_sram[2]:12 *C 56.075 25.160 +*N mux_tree_tapbuf_size10_2_sram[2]:13 *C 56.120 25.115 +*N mux_tree_tapbuf_size10_2_sram[2]:14 *C 56.120 23.120 +*N mux_tree_tapbuf_size10_2_sram[2]:15 *C 56.120 23.120 +*N mux_tree_tapbuf_size10_2_sram[2]:16 *C 56.120 15.345 +*N mux_tree_tapbuf_size10_2_sram[2]:17 *C 56.120 15.300 +*N mux_tree_tapbuf_size10_2_sram[2]:18 *C 56.425 15.300 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_4\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_2_sram[2]:4 5.645028e-05 +5 mux_tree_tapbuf_size10_2_sram[2]:5 5.874176e-05 +6 mux_tree_tapbuf_size10_2_sram[2]:6 0.0003449279 +7 mux_tree_tapbuf_size10_2_sram[2]:7 0.0003449279 +8 mux_tree_tapbuf_size10_2_sram[2]:8 0.000166329 +9 mux_tree_tapbuf_size10_2_sram[2]:9 0.000195546 +10 mux_tree_tapbuf_size10_2_sram[2]:10 9.13281e-05 +11 mux_tree_tapbuf_size10_2_sram[2]:11 0.0002895161 +12 mux_tree_tapbuf_size10_2_sram[2]:12 0.0002578152 +13 mux_tree_tapbuf_size10_2_sram[2]:13 0.0001128792 +14 mux_tree_tapbuf_size10_2_sram[2]:14 3.118026e-05 +15 mux_tree_tapbuf_size10_2_sram[2]:15 0.000632117 +16 mux_tree_tapbuf_size10_2_sram[2]:16 0.000489842 +17 mux_tree_tapbuf_size10_2_sram[2]:17 5.49596e-05 +18 mux_tree_tapbuf_size10_2_sram[2]:18 5.366739e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_2_sram[2]:18 0.152 +1 mux_tree_tapbuf_size10_2_sram[2]:10 mux_bottom_ipin_4\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[2]:10 mux_tree_tapbuf_size10_2_sram[2]:9 0.0001686047 +3 mux_tree_tapbuf_size10_2_sram[2]:12 mux_tree_tapbuf_size10_2_sram[2]:11 0.003334821 +4 mux_tree_tapbuf_size10_2_sram[2]:13 mux_tree_tapbuf_size10_2_sram[2]:12 0.0045 +5 mux_tree_tapbuf_size10_2_sram[2]:17 mux_tree_tapbuf_size10_2_sram[2]:16 0.0045 +6 mux_tree_tapbuf_size10_2_sram[2]:16 mux_tree_tapbuf_size10_2_sram[2]:15 0.006941964 +7 mux_tree_tapbuf_size10_2_sram[2]:18 mux_tree_tapbuf_size10_2_sram[2]:17 0.0001657609 +8 mux_tree_tapbuf_size10_2_sram[2]:14 mux_bottom_ipin_4\/mux_l3_in_1_:S 0.152 +9 mux_tree_tapbuf_size10_2_sram[2]:15 mux_tree_tapbuf_size10_2_sram[2]:14 0.0045 +10 mux_tree_tapbuf_size10_2_sram[2]:15 mux_tree_tapbuf_size10_2_sram[2]:13 0.00178125 +11 mux_tree_tapbuf_size10_2_sram[2]:4 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_2_sram[2]:5 mux_tree_tapbuf_size10_2_sram[2]:4 0.0001548913 +13 mux_tree_tapbuf_size10_2_sram[2]:6 mux_tree_tapbuf_size10_2_sram[2]:5 0.0045 +14 mux_tree_tapbuf_size10_2_sram[2]:8 mux_tree_tapbuf_size10_2_sram[2]:7 0.0045 +15 mux_tree_tapbuf_size10_2_sram[2]:7 mux_tree_tapbuf_size10_2_sram[2]:6 0.005080357 +16 mux_tree_tapbuf_size10_2_sram[2]:9 mux_tree_tapbuf_size10_2_sram[2]:8 0.001872768 +17 mux_tree_tapbuf_size10_2_sram[2]:11 mux_tree_tapbuf_size10_2_sram[2]:10 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[1] 0.0064797 //LENGTH 50.930 LUMPCC 0.0001022775 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 27.445 28.560 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 4.315 37.060 +*I mux_bottom_ipin_8\/mux_l2_in_3_:S I *L 0.00357 *C 16.660 41.820 +*I mux_bottom_ipin_8\/mux_l2_in_2_:S I *L 0.00357 *C 12.980 36.430 +*I mux_bottom_ipin_8\/mux_l2_in_1_:S I *L 0.00357 *C 15.540 30.990 +*I mux_bottom_ipin_8\/mux_l2_in_0_:S I *L 0.00357 *C 18.040 30.990 +*N mux_tree_tapbuf_size10_4_sram[1]:6 *C 18.040 30.990 +*N mux_tree_tapbuf_size10_4_sram[1]:7 *C 15.540 30.990 +*N mux_tree_tapbuf_size10_4_sram[1]:8 *C 12.980 36.430 +*N mux_tree_tapbuf_size10_4_sram[1]:9 *C 16.623 41.820 +*N mux_tree_tapbuf_size10_4_sram[1]:10 *C 15.225 41.820 +*N mux_tree_tapbuf_size10_4_sram[1]:11 *C 15.180 41.775 +*N mux_tree_tapbuf_size10_4_sram[1]:12 *C 15.180 36.765 +*N mux_tree_tapbuf_size10_4_sram[1]:13 *C 15.135 36.720 +*N mux_tree_tapbuf_size10_4_sram[1]:14 *C 12.980 36.720 +*N mux_tree_tapbuf_size10_4_sram[1]:15 *C 10.580 36.720 +*N mux_tree_tapbuf_size10_4_sram[1]:16 *C 10.580 37.060 +*N mux_tree_tapbuf_size10_4_sram[1]:17 *C 4.353 37.060 +*N mux_tree_tapbuf_size10_4_sram[1]:18 *C 6.900 37.060 +*N mux_tree_tapbuf_size10_4_sram[1]:19 *C 6.900 37.015 +*N mux_tree_tapbuf_size10_4_sram[1]:20 *C 6.900 30.645 +*N mux_tree_tapbuf_size10_4_sram[1]:21 *C 6.945 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:22 *C 15.540 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:23 *C 18.040 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:24 *C 25.715 30.600 +*N mux_tree_tapbuf_size10_4_sram[1]:25 *C 25.760 30.555 +*N mux_tree_tapbuf_size10_4_sram[1]:26 *C 25.760 28.605 +*N mux_tree_tapbuf_size10_4_sram[1]:27 *C 25.805 28.560 +*N mux_tree_tapbuf_size10_4_sram[1]:28 *C 27.408 28.560 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_8\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_8\/mux_l2_in_2_:S 1e-06 +4 mux_bottom_ipin_8\/mux_l2_in_1_:S 1e-06 +5 mux_bottom_ipin_8\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_4_sram[1]:6 5.880047e-05 +7 mux_tree_tapbuf_size10_4_sram[1]:7 6.274615e-05 +8 mux_tree_tapbuf_size10_4_sram[1]:8 5.833657e-05 +9 mux_tree_tapbuf_size10_4_sram[1]:9 0.0001044471 +10 mux_tree_tapbuf_size10_4_sram[1]:10 0.0001044471 +11 mux_tree_tapbuf_size10_4_sram[1]:11 0.0002794758 +12 mux_tree_tapbuf_size10_4_sram[1]:12 0.0002794758 +13 mux_tree_tapbuf_size10_4_sram[1]:13 0.0001526334 +14 mux_tree_tapbuf_size10_4_sram[1]:14 0.0003471467 +15 mux_tree_tapbuf_size10_4_sram[1]:15 0.0001922407 +16 mux_tree_tapbuf_size10_4_sram[1]:16 0.0002814712 +17 mux_tree_tapbuf_size10_4_sram[1]:17 0.0001621199 +18 mux_tree_tapbuf_size10_4_sram[1]:18 0.0004518355 +19 mux_tree_tapbuf_size10_4_sram[1]:19 0.0003953522 +20 mux_tree_tapbuf_size10_4_sram[1]:20 0.0003953522 +21 mux_tree_tapbuf_size10_4_sram[1]:21 0.0005380934 +22 mux_tree_tapbuf_size10_4_sram[1]:22 0.0007425703 +23 mux_tree_tapbuf_size10_4_sram[1]:23 0.0007184912 +24 mux_tree_tapbuf_size10_4_sram[1]:24 0.0005186429 +25 mux_tree_tapbuf_size10_4_sram[1]:25 0.0001381153 +26 mux_tree_tapbuf_size10_4_sram[1]:26 0.0001381153 +27 mux_tree_tapbuf_size10_4_sram[1]:27 0.0001257566 +28 mux_tree_tapbuf_size10_4_sram[1]:28 0.0001257566 +29 mux_tree_tapbuf_size10_4_sram[1]:21 ropt_net_163:8 4.478891e-05 +30 mux_tree_tapbuf_size10_4_sram[1]:20 ropt_net_163:5 6.349828e-06 +31 mux_tree_tapbuf_size10_4_sram[1]:19 ropt_net_163:4 6.349828e-06 +32 mux_tree_tapbuf_size10_4_sram[1]:22 ropt_net_163:9 4.478891e-05 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_4_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_4_sram[1]:21 mux_tree_tapbuf_size10_4_sram[1]:20 0.0045 +2 mux_tree_tapbuf_size10_4_sram[1]:20 mux_tree_tapbuf_size10_4_sram[1]:19 0.0056875 +3 mux_tree_tapbuf_size10_4_sram[1]:18 mux_tree_tapbuf_size10_4_sram[1]:17 0.002274554 +4 mux_tree_tapbuf_size10_4_sram[1]:18 mux_tree_tapbuf_size10_4_sram[1]:16 0.003285714 +5 mux_tree_tapbuf_size10_4_sram[1]:19 mux_tree_tapbuf_size10_4_sram[1]:18 0.0045 +6 mux_tree_tapbuf_size10_4_sram[1]:7 mux_bottom_ipin_8\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size10_4_sram[1]:17 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size10_4_sram[1]:24 mux_tree_tapbuf_size10_4_sram[1]:23 0.006852678 +9 mux_tree_tapbuf_size10_4_sram[1]:25 mux_tree_tapbuf_size10_4_sram[1]:24 0.0045 +10 mux_tree_tapbuf_size10_4_sram[1]:27 mux_tree_tapbuf_size10_4_sram[1]:26 0.0045 +11 mux_tree_tapbuf_size10_4_sram[1]:26 mux_tree_tapbuf_size10_4_sram[1]:25 0.001741072 +12 mux_tree_tapbuf_size10_4_sram[1]:28 mux_tree_tapbuf_size10_4_sram[1]:27 0.001430804 +13 mux_tree_tapbuf_size10_4_sram[1]:13 mux_tree_tapbuf_size10_4_sram[1]:12 0.0045 +14 mux_tree_tapbuf_size10_4_sram[1]:12 mux_tree_tapbuf_size10_4_sram[1]:11 0.004473215 +15 mux_tree_tapbuf_size10_4_sram[1]:10 mux_tree_tapbuf_size10_4_sram[1]:9 0.001247768 +16 mux_tree_tapbuf_size10_4_sram[1]:11 mux_tree_tapbuf_size10_4_sram[1]:10 0.0045 +17 mux_tree_tapbuf_size10_4_sram[1]:9 mux_bottom_ipin_8\/mux_l2_in_3_:S 0.152 +18 mux_tree_tapbuf_size10_4_sram[1]:8 mux_bottom_ipin_8\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_4_sram[1]:6 mux_bottom_ipin_8\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size10_4_sram[1]:16 mux_tree_tapbuf_size10_4_sram[1]:15 0.0003035715 +21 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:21 0.007674108 +22 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:7 0.0003482143 +23 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:22 0.002232143 +24 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:6 0.0003482143 +25 mux_tree_tapbuf_size10_4_sram[1]:15 mux_tree_tapbuf_size10_4_sram[1]:14 0.002142857 +26 mux_tree_tapbuf_size10_4_sram[1]:14 mux_tree_tapbuf_size10_4_sram[1]:13 0.001924107 +27 mux_tree_tapbuf_size10_4_sram[1]:14 mux_tree_tapbuf_size10_4_sram[1]:8 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[3] 0.0008250276 //LENGTH 5.895 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 83.105 66.300 +*I mux_bottom_ipin_13\/mux_l4_in_0_:S I *L 0.00357 *C 83.720 63.745 +*I mem_bottom_ipin_13\/FTB_8__47:A I *L 0.001746 *C 85.100 66.640 +*N mux_tree_tapbuf_size10_7_sram[3]:3 *C 85.062 66.640 +*N mux_tree_tapbuf_size10_7_sram[3]:4 *C 84.640 66.640 +*N mux_tree_tapbuf_size10_7_sram[3]:5 *C 84.640 66.300 +*N mux_tree_tapbuf_size10_7_sram[3]:6 *C 83.720 63.745 +*N mux_tree_tapbuf_size10_7_sram[3]:7 *C 83.720 63.920 +*N mux_tree_tapbuf_size10_7_sram[3]:8 *C 83.720 63.965 +*N mux_tree_tapbuf_size10_7_sram[3]:9 *C 83.720 66.255 +*N mux_tree_tapbuf_size10_7_sram[3]:10 *C 83.720 66.300 +*N mux_tree_tapbuf_size10_7_sram[3]:11 *C 83.142 66.300 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_13\/FTB_8__47:A 1e-06 +3 mux_tree_tapbuf_size10_7_sram[3]:3 4.913316e-05 +4 mux_tree_tapbuf_size10_7_sram[3]:4 7.317719e-05 +5 mux_tree_tapbuf_size10_7_sram[3]:5 9.743703e-05 +6 mux_tree_tapbuf_size10_7_sram[3]:6 4.381019e-05 +7 mux_tree_tapbuf_size10_7_sram[3]:7 4.849389e-05 +8 mux_tree_tapbuf_size10_7_sram[3]:8 0.000144357 +9 mux_tree_tapbuf_size10_7_sram[3]:9 0.000144357 +10 mux_tree_tapbuf_size10_7_sram[3]:10 0.0001614216 +11 mux_tree_tapbuf_size10_7_sram[3]:11 5.984048e-05 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_7_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_7_sram[3]:3 mem_bottom_ipin_13\/FTB_8__47:A 0.152 +2 mux_tree_tapbuf_size10_7_sram[3]:11 mux_tree_tapbuf_size10_7_sram[3]:10 0.0005156249 +3 mux_tree_tapbuf_size10_7_sram[3]:6 mux_bottom_ipin_13\/mux_l4_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_7_sram[3]:7 mux_tree_tapbuf_size10_7_sram[3]:6 7.543104e-05 +5 mux_tree_tapbuf_size10_7_sram[3]:8 mux_tree_tapbuf_size10_7_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size10_7_sram[3]:10 mux_tree_tapbuf_size10_7_sram[3]:9 0.0045 +7 mux_tree_tapbuf_size10_7_sram[3]:10 mux_tree_tapbuf_size10_7_sram[3]:5 0.0008214285 +8 mux_tree_tapbuf_size10_7_sram[3]:9 mux_tree_tapbuf_size10_7_sram[3]:8 0.002044643 +9 mux_tree_tapbuf_size10_7_sram[3]:5 mux_tree_tapbuf_size10_7_sram[3]:4 0.0003035715 +10 mux_tree_tapbuf_size10_7_sram[3]:4 mux_tree_tapbuf_size10_7_sram[3]:3 0.0003772322 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_3_ccff_tail[0] 0.0006600533 //LENGTH 4.910 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_5\/FTB_4__43:X O *L 0 *C 71.995 41.480 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 70.555 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 *C 70.555 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 *C 70.380 39.100 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 *C 70.380 39.145 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 *C 70.380 41.435 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 *C 70.425 41.480 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 *C 71.958 41.480 + +*CAP +0 mem_bottom_ipin_5\/FTB_4__43:X 1e-06 +1 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 4.989546e-05 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 5.320795e-05 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.0001529487 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0001529487 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.0001245262 +7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.0001245262 + +*RES +0 mem_bottom_ipin_5\/FTB_4__43:X mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.001368304 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[0] 0.002797828 //LENGTH 22.955 LUMPCC 0.0001039827 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 35.265 31.620 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.975 33.660 +*I mux_bottom_ipin_3\/mux_l1_in_0_:S I *L 0.00357 *C 35.060 50.320 +*N mux_tree_tapbuf_size8_1_sram[0]:3 *C 35.075 50.320 +*N mux_tree_tapbuf_size8_1_sram[0]:4 *C 35.398 50.320 +*N mux_tree_tapbuf_size8_1_sram[0]:5 *C 35.420 50.275 +*N mux_tree_tapbuf_size8_1_sram[0]:6 *C 36.975 33.660 +*N mux_tree_tapbuf_size8_1_sram[0]:7 *C 36.800 33.320 +*N mux_tree_tapbuf_size8_1_sram[0]:8 *C 35.465 33.320 +*N mux_tree_tapbuf_size8_1_sram[0]:9 *C 35.420 33.365 +*N mux_tree_tapbuf_size8_1_sram[0]:10 *C 34.960 33.320 +*N mux_tree_tapbuf_size8_1_sram[0]:11 *C 34.960 31.665 +*N mux_tree_tapbuf_size8_1_sram[0]:12 *C 34.960 31.620 +*N mux_tree_tapbuf_size8_1_sram[0]:13 *C 35.265 31.620 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_3\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_1_sram[0]:3 7.207421e-05 +4 mux_tree_tapbuf_size8_1_sram[0]:4 7.207421e-05 +5 mux_tree_tapbuf_size8_1_sram[0]:5 0.0009264037 +6 mux_tree_tapbuf_size8_1_sram[0]:6 5.154573e-05 +7 mux_tree_tapbuf_size8_1_sram[0]:7 0.0001311323 +8 mux_tree_tapbuf_size8_1_sram[0]:8 0.0001067145 +9 mux_tree_tapbuf_size8_1_sram[0]:9 0.0009593501 +10 mux_tree_tapbuf_size8_1_sram[0]:10 0.0001412467 +11 mux_tree_tapbuf_size8_1_sram[0]:11 0.0001083003 +12 mux_tree_tapbuf_size8_1_sram[0]:12 5.877965e-05 +13 mux_tree_tapbuf_size8_1_sram[0]:13 6.322343e-05 +14 mux_tree_tapbuf_size8_1_sram[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.199134e-05 +15 mux_tree_tapbuf_size8_1_sram[0]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.199134e-05 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_1_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_1_sram[0]:4 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001752718 +2 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_1_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size8_1_sram[0]:3 mux_bottom_ipin_3\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_1_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_1_sram[0]:10 0.001477679 +6 mux_tree_tapbuf_size8_1_sram[0]:13 mux_tree_tapbuf_size8_1_sram[0]:12 0.0001657609 +7 mux_tree_tapbuf_size8_1_sram[0]:8 mux_tree_tapbuf_size8_1_sram[0]:7 0.001191964 +8 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:5 0.01509821 +10 mux_tree_tapbuf_size8_1_sram[0]:6 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size8_1_sram[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 0.0003035715 +12 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:9 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[1] 0.004525943 //LENGTH 34.330 LUMPCC 0.0001135914 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 24.225 47.600 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 21.795 44.540 +*I mux_bottom_ipin_11\/mux_l2_in_1_:S I *L 0.00357 *C 20.600 34.000 +*I mux_bottom_ipin_11\/mux_l2_in_3_:S I *L 0.00357 *C 23.560 34.295 +*I mux_bottom_ipin_11\/mux_l2_in_2_:S I *L 0.00357 *C 25.400 39.735 +*I mux_bottom_ipin_11\/mux_l2_in_0_:S I *L 0.00357 *C 27.240 47.600 +*N mux_tree_tapbuf_size8_5_sram[1]:6 *C 27.203 47.600 +*N mux_tree_tapbuf_size8_5_sram[1]:7 *C 25.400 39.735 +*N mux_tree_tapbuf_size8_5_sram[1]:8 *C 23.560 34.295 +*N mux_tree_tapbuf_size8_5_sram[1]:9 *C 23.530 34.070 +*N mux_tree_tapbuf_size8_5_sram[1]:10 *C 23.415 33.930 +*N mux_tree_tapbuf_size8_5_sram[1]:11 *C 20.600 34.000 +*N mux_tree_tapbuf_size8_5_sram[1]:12 *C 20.700 33.660 +*N mux_tree_tapbuf_size8_5_sram[1]:13 *C 23.460 33.660 +*N mux_tree_tapbuf_size8_5_sram[1]:14 *C 27.555 33.660 +*N mux_tree_tapbuf_size8_5_sram[1]:15 *C 27.600 33.705 +*N mux_tree_tapbuf_size8_5_sram[1]:16 *C 27.600 39.395 +*N mux_tree_tapbuf_size8_5_sram[1]:17 *C 27.555 39.440 +*N mux_tree_tapbuf_size8_5_sram[1]:18 *C 25.400 39.440 +*N mux_tree_tapbuf_size8_5_sram[1]:19 *C 23.505 39.440 +*N mux_tree_tapbuf_size8_5_sram[1]:20 *C 23.460 39.485 +*N mux_tree_tapbuf_size8_5_sram[1]:21 *C 21.832 44.540 +*N mux_tree_tapbuf_size8_5_sram[1]:22 *C 23.415 44.540 +*N mux_tree_tapbuf_size8_5_sram[1]:23 *C 23.460 44.540 +*N mux_tree_tapbuf_size8_5_sram[1]:24 *C 23.460 47.555 +*N mux_tree_tapbuf_size8_5_sram[1]:25 *C 23.505 47.600 +*N mux_tree_tapbuf_size8_5_sram[1]:26 *C 24.225 47.600 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_11\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_11\/mux_l2_in_3_:S 1e-06 +4 mux_bottom_ipin_11\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_ipin_11\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_5_sram[1]:6 0.0002103046 +7 mux_tree_tapbuf_size8_5_sram[1]:7 7.06823e-05 +8 mux_tree_tapbuf_size8_5_sram[1]:8 5.691848e-05 +9 mux_tree_tapbuf_size8_5_sram[1]:9 3.858235e-05 +10 mux_tree_tapbuf_size8_5_sram[1]:10 3.626418e-05 +11 mux_tree_tapbuf_size8_5_sram[1]:11 5.820553e-05 +12 mux_tree_tapbuf_size8_5_sram[1]:12 0.0002006641 +13 mux_tree_tapbuf_size8_5_sram[1]:13 0.0004637829 +14 mux_tree_tapbuf_size8_5_sram[1]:14 0.0002661167 +15 mux_tree_tapbuf_size8_5_sram[1]:15 0.0003442897 +16 mux_tree_tapbuf_size8_5_sram[1]:16 0.0003442897 +17 mux_tree_tapbuf_size8_5_sram[1]:17 0.0001861451 +18 mux_tree_tapbuf_size8_5_sram[1]:18 0.000383142 +19 mux_tree_tapbuf_size8_5_sram[1]:19 0.0001609038 +20 mux_tree_tapbuf_size8_5_sram[1]:20 0.0002745388 +21 mux_tree_tapbuf_size8_5_sram[1]:21 0.0001409616 +22 mux_tree_tapbuf_size8_5_sram[1]:22 0.0001409616 +23 mux_tree_tapbuf_size8_5_sram[1]:23 0.000479749 +24 mux_tree_tapbuf_size8_5_sram[1]:24 0.0001727162 +25 mux_tree_tapbuf_size8_5_sram[1]:25 6.9446e-05 +26 mux_tree_tapbuf_size8_5_sram[1]:26 0.0003076872 +27 mux_tree_tapbuf_size8_5_sram[1]:24 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.209672e-05 +28 mux_tree_tapbuf_size8_5_sram[1]:20 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.625984e-05 +29 mux_tree_tapbuf_size8_5_sram[1]:23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.209672e-05 +30 mux_tree_tapbuf_size8_5_sram[1]:23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.625984e-05 +31 mux_tree_tapbuf_size8_5_sram[1]:26 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.843915e-05 +32 mux_tree_tapbuf_size8_5_sram[1]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.843915e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_5_sram[1]:26 0.152 +1 mux_tree_tapbuf_size8_5_sram[1]:25 mux_tree_tapbuf_size8_5_sram[1]:24 0.0045 +2 mux_tree_tapbuf_size8_5_sram[1]:24 mux_tree_tapbuf_size8_5_sram[1]:23 0.002691964 +3 mux_tree_tapbuf_size8_5_sram[1]:17 mux_tree_tapbuf_size8_5_sram[1]:16 0.0045 +4 mux_tree_tapbuf_size8_5_sram[1]:16 mux_tree_tapbuf_size8_5_sram[1]:15 0.005080358 +5 mux_tree_tapbuf_size8_5_sram[1]:14 mux_tree_tapbuf_size8_5_sram[1]:13 0.00365625 +6 mux_tree_tapbuf_size8_5_sram[1]:15 mux_tree_tapbuf_size8_5_sram[1]:14 0.0045 +7 mux_tree_tapbuf_size8_5_sram[1]:19 mux_tree_tapbuf_size8_5_sram[1]:18 0.001691964 +8 mux_tree_tapbuf_size8_5_sram[1]:20 mux_tree_tapbuf_size8_5_sram[1]:19 0.0045 +9 mux_tree_tapbuf_size8_5_sram[1]:22 mux_tree_tapbuf_size8_5_sram[1]:21 0.001412946 +10 mux_tree_tapbuf_size8_5_sram[1]:23 mux_tree_tapbuf_size8_5_sram[1]:22 0.0045 +11 mux_tree_tapbuf_size8_5_sram[1]:23 mux_tree_tapbuf_size8_5_sram[1]:20 0.004513393 +12 mux_tree_tapbuf_size8_5_sram[1]:21 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size8_5_sram[1]:26 mux_tree_tapbuf_size8_5_sram[1]:25 0.0006428572 +14 mux_tree_tapbuf_size8_5_sram[1]:26 mux_tree_tapbuf_size8_5_sram[1]:6 0.002658482 +15 mux_tree_tapbuf_size8_5_sram[1]:8 mux_bottom_ipin_11\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size8_5_sram[1]:7 mux_bottom_ipin_11\/mux_l2_in_2_:S 0.152 +17 mux_tree_tapbuf_size8_5_sram[1]:11 mux_bottom_ipin_11\/mux_l2_in_1_:S 0.152 +18 mux_tree_tapbuf_size8_5_sram[1]:6 mux_bottom_ipin_11\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size8_5_sram[1]:12 mux_tree_tapbuf_size8_5_sram[1]:11 0.0003035715 +20 mux_tree_tapbuf_size8_5_sram[1]:13 mux_tree_tapbuf_size8_5_sram[1]:12 0.002464286 +21 mux_tree_tapbuf_size8_5_sram[1]:13 mux_tree_tapbuf_size8_5_sram[1]:10 0.0002410715 +22 mux_tree_tapbuf_size8_5_sram[1]:10 mux_tree_tapbuf_size8_5_sram[1]:9 0.0001026786 +23 mux_tree_tapbuf_size8_5_sram[1]:9 mux_tree_tapbuf_size8_5_sram[1]:8 0.000130814 +24 mux_tree_tapbuf_size8_5_sram[1]:18 mux_tree_tapbuf_size8_5_sram[1]:17 0.001924107 +25 mux_tree_tapbuf_size8_5_sram[1]:18 mux_tree_tapbuf_size8_5_sram[1]:7 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_2_ccff_tail[0] 0.003653806 //LENGTH 27.540 LUMPCC 0.0004878585 DR + +*CONN +*I mem_bottom_ipin_6\/FTB_11__50:X O *L 0 *C 67.385 49.640 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 44.795 53.380 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 *C 44.833 53.380 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 *C 48.715 53.380 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 *C 48.760 53.335 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 *C 48.760 50.025 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 *C 48.805 49.980 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 *C 50.600 49.980 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 *C 50.600 49.640 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 *C 67.347 49.640 + +*CAP +0 mem_bottom_ipin_6\/FTB_11__50:X 1e-06 +1 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0001675292 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0001675292 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.0001961246 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0001961246 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0001395409 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.000165023 +8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 0.001078779 +9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 0.001053297 +10 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 chanx_right_in[5]:19 2.605757e-05 +11 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 chanx_right_in[5]:21 4.513445e-05 +12 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 chanx_right_in[5]:22 1.334963e-05 +13 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 chanx_right_in[5]:18 2.605757e-05 +14 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 chanx_right_in[5]:20 4.513445e-05 +15 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 chanx_right_in[5]:21 1.334963e-05 +16 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_3_sram[0]:12 0.0001593876 +17 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mux_tree_tapbuf_size8_3_sram[0]:11 0.0001593876 + +*RES +0 mem_bottom_ipin_6\/FTB_11__50:X mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 0.01495313 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.002955357 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.003466518 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.001602679 +8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002694618 //LENGTH 19.550 LUMPCC 0.0007813739 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_0_:X O *L 0 *C 75.155 29.240 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 68.905 25.500 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 68.943 25.500 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 70.335 25.500 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 70.380 25.545 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 70.380 27.143 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 70.388 27.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 79.112 27.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 79.120 27.258 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 79.120 29.195 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 79.075 29.240 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 75.193 29.240 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001032272 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001032272 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001118972 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001118972 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003309525 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003309525 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000160175 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.000160175 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0002493701 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0002493701 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[0]:37 0.0001259943 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[0]:38 6.470516e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[0]:33 0.0001259943 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[0]:37 6.470516e-05 +16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[14]:32 0.00012179 +17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[14]:33 0.00012179 +18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.819751e-05 +19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.819751e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001243304 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001426339 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001366917 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001729911 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.003466518 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008450876 //LENGTH 5.305 LUMPCC 0.0002913021 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_1_:X O *L 0 *C 57.215 56.440 +*I mux_bottom_ipin_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 55.490 58.820 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 55.528 58.820 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 57.455 58.820 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 57.500 58.775 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 57.500 56.485 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 57.500 56.440 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 57.215 56.440 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.558389e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.558389e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001507956 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001507956 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.331617e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.571038e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[19]:22 8.713773e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[19]:20 8.713773e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 1.335894e-06 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.713826e-05 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.335894e-06 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.713826e-05 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.918451e-08 +15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.918451e-08 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001720982 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000726489 //LENGTH 4.640 LUMPCC 0.0001091613 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_1_:X O *L 0 *C 51.235 22.440 +*I mux_bottom_ipin_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 51.235 26.180 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 51.235 26.180 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 51.060 26.180 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 51.060 26.135 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 51.060 22.485 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 51.060 22.440 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 51.235 22.440 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.236995e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.739361e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001974925 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001974925 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.758756e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.299164e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.135173e-06 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.135173e-06 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.344546e-05 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.344546e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003258929 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.51087e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001226806 //LENGTH 9.800 LUMPCC 0.000336684 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_2_:X O *L 0 *C 53.995 39.440 +*I mux_bottom_ipin_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 50.505 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 50.505 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 50.600 45.175 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 50.600 39.485 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 50.645 39.440 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 53.958 39.440 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.944008e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002804348 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002804348 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000148906 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000148906 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_3_sram[0]:24 6.594337e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_3_sram[0]:25 6.594337e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:27 6.07009e-05 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:28 6.07009e-05 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.169772e-05 +12 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.169772e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_2_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.005080358 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.002957589 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000309763 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_3_:X O *L 0 *C 15.815 42.500 +*I mux_bottom_ipin_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 13.630 42.500 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 13.668 42.500 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 15.778 42.500 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001538815 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001538815 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_3_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001148541 //LENGTH 8.020 LUMPCC 0.0001694869 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_0_:X O *L 0 *C 19.955 56.440 +*I mux_bottom_ipin_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 14.260 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 14.260 58.140 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 14.260 58.095 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 14.260 56.485 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 14.305 56.440 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 19.918 56.440 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.278443e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.335388e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.335388e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003987807 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003987807 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.453699e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.453699e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.020649e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.020649e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.005011161 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0014375 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007603214 //LENGTH 5.370 LUMPCC 0.0001040717 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_0_:X O *L 0 *C 74.805 28.220 +*I mux_bottom_ipin_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 74.980 23.460 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 74.980 23.460 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 74.980 23.505 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 74.980 28.175 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 74.980 28.220 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 74.805 28.220 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.284229e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002437664 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002437664 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.632441e-05 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.755032e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[12]:7 5.203583e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[12]:6 5.203583e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004169643 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003573051 //LENGTH 2.205 LUMPCC 0.0001613607 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_0_:X O *L 0 *C 88.035 52.700 +*I mux_bottom_ipin_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 86.120 52.700 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.157 52.700 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.998 52.700 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.697222e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.697222e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[1]:25 8.068033e-05 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[1]:24 8.068033e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001642857 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005097282 //LENGTH 2.860 LUMPCC 0.0002126352 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l1_in_0_:X O *L 0 *C 41.575 25.500 +*I mux_bottom_ipin_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 39.005 25.500 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 39.043 25.500 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.538 25.500 + +*CAP +0 mux_bottom_ipin_2\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001475465 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001475465 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[0]:28 0.0001063176 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[0]:29 0.0001063176 + +*RES +0 mux_bottom_ipin_2\/mux_l1_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_2\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001311353 //LENGTH 9.855 LUMPCC 0.0003122989 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_3_:X O *L 0 *C 40.655 20.060 +*I mux_bottom_ipin_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 34.790 17.000 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 34.828 17.000 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 39.055 17.000 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 39.100 17.045 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 39.100 20.015 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 39.145 20.060 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 40.617 20.060 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000280675 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000280675 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001849898 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001849898 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.286216e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.286216e-05 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[6]:26 6.891854e-05 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[6]:27 6.891854e-05 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_0_sram[1]:23 1.574039e-05 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_0_sram[1]:27 2.571995e-06 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_0_sram[1]:14 2.287256e-05 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_0_sram[1]:24 4.604598e-05 +14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_0_sram[1]:22 1.574039e-05 +15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_0_sram[1]:26 2.571995e-06 +16 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size8_0_sram[1]:24 2.287256e-05 +17 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size8_0_sram[1]:25 4.604598e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_3_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003774554 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002651786 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009040762 //LENGTH 6.085 LUMPCC 0.0002500392 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_1_:X O *L 0 *C 79.295 34.340 +*I mux_bottom_ipin_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 79.870 38.760 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 79.833 38.760 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 79.165 38.760 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 79.120 38.715 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 79.120 34.385 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 79.120 34.340 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 79.295 34.340 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.104164e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.104164e-05 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001850292 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001850292 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.55218e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.437341e-05 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001250196 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001250196 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_1_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005959822 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009008841 //LENGTH 6.825 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_0_:X O *L 0 *C 34.215 56.100 +*I mux_bottom_ipin_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 30.360 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 30.398 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 33.535 58.140 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 33.580 58.095 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 33.580 56.145 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.625 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 34.178 56.100 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002265929 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002265929 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001412792 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001412792 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.156997e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.156997e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741072 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002801339 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009882019 //LENGTH 6.775 LUMPCC 0.0002723254 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_1_:X O *L 0 *C 16.360 19.720 +*I mux_bottom_ipin_10\/mux_l3_in_0_:A0 I *L 0.001631 *C 12.595 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 12.595 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 12.880 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 12.880 17.385 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 12.880 19.675 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 12.925 19.720 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 16.323 19.720 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.29654e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.78962e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001025219 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001025219 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002089856 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002089856 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[8]:7 1.006633e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[8]:8 1.006633e-05 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[8]:10 4.693655e-05 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[8]:11 2.083174e-05 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[8]:6 2.083174e-05 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[8]:11 4.693655e-05 +14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_4_sram[1]:19 1.836824e-06 +15 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size8_4_sram[1]:23 2.192243e-05 +16 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size8_4_sram[1]:24 3.456881e-05 +17 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_4_sram[1]:20 1.836824e-06 +18 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size8_4_sram[1]:13 3.456881e-05 +19 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size8_4_sram[1]:24 2.192243e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_1_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001548913 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003033482 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006733371 //LENGTH 4.090 LUMPCC 0.0002390506 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l3_in_0_:X O *L 0 *C 19.955 41.480 +*I mux_bottom_ipin_11\/mux_l4_in_0_:A1 I *L 0.00198 *C 18.305 39.780 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 18.343 39.780 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 19.735 39.780 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 19.780 39.825 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 19.780 41.435 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 19.780 41.480 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 19.955 41.480 + +*CAP +0 mux_bottom_ipin_11\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.084663e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.084663e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001165493 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001165493 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.354746e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.394709e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chanx_right_in[7]:8 6.640296e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[7]:9 6.640296e-05 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_5_sram[3]:8 5.312237e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_5_sram[3]:9 5.312237e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l3_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_11\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001243304 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006009333 //LENGTH 3.565 LUMPCC 0.000235051 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l3_in_0_:X O *L 0 *C 84.465 45.635 +*I mux_bottom_ipin_14\/mux_l4_in_0_:A1 I *L 0.00198 *C 83.260 47.260 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 83.297 47.260 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 84.135 47.260 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 84.180 47.215 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 84.180 45.605 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 84.180 45.560 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 84.465 45.635 + +*CAP +0 mux_bottom_ipin_14\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.181737e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.181737e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.556997e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.556997e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.760918e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.149845e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[2]:56 5.067324e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[2]:57 5.067324e-05 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.067324e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.617903e-05 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.067324e-05 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.617903e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l3_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001370192 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0007477679 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_14\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET ropt_net_179 0.001088707 //LENGTH 8.315 LUMPCC 0.0003168239 DR + +*CONN +*I ropt_mt_inst_726:X O *L 0 *C 7.095 14.280 +*I ropt_mt_inst_786:A I *L 0.001767 *C 3.220 17.680 +*N ropt_net_179:2 *C 3.220 17.680 +*N ropt_net_179:3 *C 3.220 17.340 +*N ropt_net_179:4 *C 5.935 17.340 +*N ropt_net_179:5 *C 5.980 17.295 +*N ropt_net_179:6 *C 5.980 14.325 +*N ropt_net_179:7 *C 6.025 14.280 +*N ropt_net_179:8 *C 7.058 14.280 + +*CAP +0 ropt_mt_inst_726:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_179:2 5.852752e-05 +3 ropt_net_179:3 0.0001358686 +4 ropt_net_179:4 0.0001072177 +5 ropt_net_179:5 0.0001509145 +6 ropt_net_179:6 0.0001509145 +7 ropt_net_179:7 8.321987e-05 +8 ropt_net_179:8 8.321987e-05 +9 ropt_net_179:8 prog_clk[0]:314 1.770196e-05 +10 ropt_net_179:7 prog_clk[0]:315 1.770196e-05 +11 ropt_net_179:6 prog_clk[0]:376 2.946719e-05 +12 ropt_net_179:6 prog_clk[0]:377 9.745056e-06 +13 ropt_net_179:4 prog_clk[0]:316 9.448009e-06 +14 ropt_net_179:5 prog_clk[0]:375 2.946719e-05 +15 ropt_net_179:5 prog_clk[0]:376 9.745056e-06 +16 ropt_net_179:3 prog_clk[0]:376 9.448009e-06 +17 ropt_net_179:4 ropt_net_165:13 9.204976e-05 +18 ropt_net_179:3 ropt_net_165:12 9.204976e-05 + +*RES +0 ropt_mt_inst_726:X ropt_net_179:8 0.152 +1 ropt_net_179:8 ropt_net_179:7 0.0009218751 +2 ropt_net_179:7 ropt_net_179:6 0.0045 +3 ropt_net_179:6 ropt_net_179:5 0.002651786 +4 ropt_net_179:4 ropt_net_179:3 0.002424107 +5 ropt_net_179:5 ropt_net_179:4 0.0045 +6 ropt_net_179:2 ropt_mt_inst_786:A 0.152 +7 ropt_net_179:3 ropt_net_179:2 0.0003035715 + +*END + +*D_NET ropt_net_169 0.0001023807 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 92.655 72.080 +*I ropt_mt_inst_773:A I *L 0.001767 *C 93.380 72.080 +*N ropt_net_169:2 *C 93.343 72.080 +*N ropt_net_169:3 *C 92.693 72.080 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 ropt_mt_inst_773:A 1e-06 +2 ropt_net_169:2 5.019033e-05 +3 ropt_net_169:3 5.019033e-05 + +*RES +0 ropt_mt_inst_734:X ropt_net_169:3 0.152 +1 ropt_net_169:3 ropt_net_169:2 0.0005803572 +2 ropt_net_169:2 ropt_mt_inst_773:A 0.152 + +*END + +*D_NET ropt_net_190 0.0004168723 //LENGTH 2.920 LUMPCC 0 DR + +*CONN +*I FTB_24__23:X O *L 0 *C 15.180 3.400 +*I ropt_mt_inst_799:A I *L 0.001766 *C 17.020 4.080 +*N ropt_net_190:2 *C 17.020 4.080 +*N ropt_net_190:3 *C 17.020 3.400 +*N ropt_net_190:4 *C 15.218 3.400 + +*CAP +0 FTB_24__23:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_190:2 6.863002e-05 +3 ropt_net_190:3 0.0001943059 +4 ropt_net_190:4 0.0001519363 + +*RES +0 FTB_24__23:X ropt_net_190:4 0.152 +1 ropt_net_190:4 ropt_net_190:3 0.001609375 +2 ropt_net_190:2 ropt_mt_inst_799:A 0.152 +3 ropt_net_190:3 ropt_net_190:2 0.0006071429 + +*END + +*D_NET ropt_net_170 0.001375101 //LENGTH 10.005 LUMPCC 0.0004496471 DR + +*CONN +*I ropt_mt_inst_741:X O *L 0 *C 11.695 71.400 +*I ropt_mt_inst_774:A I *L 0.001767 *C 3.220 72.080 +*N ropt_net_170:2 *C 3.258 72.080 +*N ropt_net_170:3 *C 5.520 72.080 +*N ropt_net_170:4 *C 5.520 71.740 +*N ropt_net_170:5 *C 9.660 71.740 +*N ropt_net_170:6 *C 9.660 71.400 +*N ropt_net_170:7 *C 11.658 71.400 + +*CAP +0 ropt_mt_inst_741:X 1e-06 +1 ropt_mt_inst_774:A 1e-06 +2 ropt_net_170:2 0.0001116962 +3 ropt_net_170:3 0.0001333991 +4 ropt_net_170:4 0.0001942029 +5 ropt_net_170:5 0.0001972147 +6 ropt_net_170:6 0.0001558279 +7 ropt_net_170:7 0.000131113 +8 ropt_net_170:4 chanx_right_in[12]:8 8.231224e-05 +9 ropt_net_170:5 chanx_right_in[12]:7 8.231224e-05 +10 ropt_net_170:2 chanx_left_out[12]:10 9.10767e-06 +11 ropt_net_170:3 chanx_left_out[12]:9 9.10767e-06 +12 ropt_net_170:4 chanx_left_out[12]:10 5.971464e-05 +13 ropt_net_170:5 chanx_left_out[12]:9 5.971464e-05 +14 ropt_net_170:2 chanx_left_out[18]:3 4.698658e-05 +15 ropt_net_170:7 chanx_left_out[18]:4 1.21464e-05 +16 ropt_net_170:3 chanx_left_out[18]:4 4.698658e-05 +17 ropt_net_170:4 chanx_left_out[18]:3 1.4556e-05 +18 ropt_net_170:5 chanx_left_out[18]:4 1.4556e-05 +19 ropt_net_170:6 chanx_left_out[18]:3 1.21464e-05 + +*RES +0 ropt_mt_inst_741:X ropt_net_170:7 0.152 +1 ropt_net_170:2 ropt_mt_inst_774:A 0.152 +2 ropt_net_170:7 ropt_net_170:6 0.001783482 +3 ropt_net_170:3 ropt_net_170:2 0.002020089 +4 ropt_net_170:4 ropt_net_170:3 0.0003035715 +5 ropt_net_170:5 ropt_net_170:4 0.003696429 +6 ropt_net_170:6 ropt_net_170:5 0.0003035714 + +*END + +*D_NET chanx_left_out[7] 0.0006542521 //LENGTH 4.405 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 4.140 41.480 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 42.160 +*N chanx_left_out[7]:2 *C 3.213 42.160 +*N chanx_left_out[7]:3 *C 3.220 42.102 +*N chanx_left_out[7]:4 *C 3.220 41.525 +*N chanx_left_out[7]:5 *C 3.265 41.480 +*N chanx_left_out[7]:6 *C 4.103 41.480 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 chanx_left_out[7] 0.0001718087 +2 chanx_left_out[7]:2 0.0001718087 +3 chanx_left_out[7]:3 7.577552e-05 +4 chanx_left_out[7]:4 7.577552e-05 +5 chanx_left_out[7]:5 7.904182e-05 +6 chanx_left_out[7]:6 7.904182e-05 + +*RES +0 ropt_mt_inst_778:X chanx_left_out[7]:6 0.152 +1 chanx_left_out[7]:6 chanx_left_out[7]:5 0.0007477679 +2 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +3 chanx_left_out[7]:4 chanx_left_out[7]:3 0.000515625 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 0.0003105917 + +*END + +*D_NET chanx_left_out[14] 0.001239773 //LENGTH 6.445 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_749:X O *L 0 *C 7.095 63.580 +*P chanx_left_out[14] O *L 0.7423 *C 1.230 63.920 +*N chanx_left_out[14]:2 *C 6.893 63.920 +*N chanx_left_out[14]:3 *C 6.900 63.920 +*N chanx_left_out[14]:4 *C 6.900 63.580 +*N chanx_left_out[14]:5 *C 6.900 63.580 +*N chanx_left_out[14]:6 *C 7.095 63.580 + +*CAP +0 ropt_mt_inst_749:X 1e-06 +1 chanx_left_out[14] 0.0005014997 +2 chanx_left_out[14]:2 0.0005014997 +3 chanx_left_out[14]:3 5.813171e-05 +4 chanx_left_out[14]:4 5.414295e-05 +5 chanx_left_out[14]:5 6.202361e-05 +6 chanx_left_out[14]:6 6.147519e-05 + +*RES +0 ropt_mt_inst_749:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:6 chanx_left_out[14]:5 0.0001059783 +2 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +3 chanx_left_out[14]:4 chanx_left_out[14]:3 0.0001634615 +4 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +5 chanx_left_out[14]:2 chanx_left_out[14] 0.0008871249 + +*END + +*D_NET ropt_net_181 0.0007934317 //LENGTH 6.465 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 101.780 8.840 +*I ropt_mt_inst_788:A I *L 0.001767 *C 97.980 6.800 +*N ropt_net_181:2 *C 97.980 6.800 +*N ropt_net_181:3 *C 97.980 6.845 +*N ropt_net_181:4 *C 97.980 8.795 +*N ropt_net_181:5 *C 98.025 8.840 +*N ropt_net_181:6 *C 101.743 8.840 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_181:2 3.800363e-05 +3 ropt_net_181:3 0.0001188583 +4 ropt_net_181:4 0.0001188583 +5 ropt_net_181:5 0.0002578557 +6 ropt_net_181:6 0.0002578557 + +*RES +0 ropt_mt_inst_763:X ropt_net_181:6 0.152 +1 ropt_net_181:6 ropt_net_181:5 0.003319197 +2 ropt_net_181:5 ropt_net_181:4 0.0045 +3 ropt_net_181:4 ropt_net_181:3 0.001741072 +4 ropt_net_181:2 ropt_mt_inst_788:A 0.152 +5 ropt_net_181:3 ropt_net_181:2 0.0045 + +*END + +*D_NET chanx_right_out[5] 0.001002429 //LENGTH 7.050 LUMPCC 0.0002914969 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 98.900 60.520 +*P chanx_right_out[5] O *L 0.7423 *C 103.583 59.840 +*N chanx_right_out[5]:2 *C 103.500 59.840 +*N chanx_right_out[5]:3 *C 103.500 59.898 +*N chanx_right_out[5]:4 *C 103.500 60.815 +*N chanx_right_out[5]:5 *C 103.455 60.860 +*N chanx_right_out[5]:6 *C 98.900 60.860 +*N chanx_right_out[5]:7 *C 98.900 60.520 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 chanx_right_out[5] 3.803331e-05 +2 chanx_right_out[5]:2 3.803331e-05 +3 chanx_right_out[5]:3 5.837862e-05 +4 chanx_right_out[5]:4 5.837862e-05 +5 chanx_right_out[5]:5 0.0002175907 +6 chanx_right_out[5]:6 0.0002446615 +7 chanx_right_out[5]:7 5.485587e-05 +8 chanx_right_out[5]:5 ropt_net_183:3 5.970895e-05 +9 chanx_right_out[5]:5 ropt_net_183:7 8.010642e-05 +10 chanx_right_out[5]:4 ropt_net_183:4 5.442163e-08 +11 chanx_right_out[5]:4 ropt_net_183:8 5.878667e-06 +12 chanx_right_out[5]:3 ropt_net_183:5 5.442163e-08 +13 chanx_right_out[5]:3 ropt_net_183:9 5.878667e-06 +14 chanx_right_out[5]:6 ropt_net_183:2 5.970895e-05 +15 chanx_right_out[5]:6 ropt_net_183:6 8.010642e-05 + +*RES +0 ropt_mt_inst_790:X chanx_right_out[5]:7 0.152 +1 chanx_right_out[5]:7 chanx_right_out[5]:6 0.0003035715 +2 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0045 +3 chanx_right_out[5]:4 chanx_right_out[5]:3 0.0008191965 +4 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +5 chanx_right_out[5]:2 chanx_right_out[5] 2.35e-05 +6 chanx_right_out[5]:6 chanx_right_out[5]:5 0.004066964 + +*END + +*D_NET ropt_net_129 0.003251563 //LENGTH 24.365 LUMPCC 0.001314083 DR + +*CONN +*I BUFT_P_104:X O *L 0 *C 21.160 9.860 +*I ropt_mt_inst_726:A I *L 0.001766 *C 3.220 14.960 +*N ropt_net_129:2 *C 3.220 14.960 +*N ropt_net_129:3 *C 3.220 14.915 +*N ropt_net_129:4 *C 3.220 11.617 +*N ropt_net_129:5 *C 3.228 11.560 +*N ropt_net_129:6 *C 13.793 11.560 +*N ropt_net_129:7 *C 13.800 11.503 +*N ropt_net_129:8 *C 13.800 9.905 +*N ropt_net_129:9 *C 13.845 9.860 +*N ropt_net_129:10 *C 21.123 9.860 + +*CAP +0 BUFT_P_104:X 1e-06 +1 ropt_mt_inst_726:A 1e-06 +2 ropt_net_129:2 3.469262e-05 +3 ropt_net_129:3 0.0001867066 +4 ropt_net_129:4 0.0001867066 +5 ropt_net_129:5 0.0003437041 +6 ropt_net_129:6 0.0003437041 +7 ropt_net_129:7 7.398315e-05 +8 ropt_net_129:8 7.398315e-05 +9 ropt_net_129:9 0.0003459999 +10 ropt_net_129:10 0.0003459999 +11 ropt_net_129:6 chanx_left_in[16]:21 0.0001360996 +12 ropt_net_129:5 chanx_left_in[16] 0.0001360996 +13 ropt_net_129:8 chanx_right_in[3]:20 2.464818e-05 +14 ropt_net_129:7 chanx_right_in[3]:21 2.464818e-05 +15 ropt_net_129:6 chanx_right_in[3]:17 5.939503e-05 +16 ropt_net_129:5 chanx_right_in[3]:22 5.939503e-05 +17 ropt_net_129:10 chanx_right_in[17]:8 0.0001647166 +18 ropt_net_129:10 chanx_right_in[17]:10 1.033159e-05 +19 ropt_net_129:9 chanx_right_in[17]:7 0.0001647166 +20 ropt_net_129:9 chanx_right_in[17]:9 1.033159e-05 +21 ropt_net_129:8 prog_clk[0]:312 5.534487e-06 +22 ropt_net_129:7 prog_clk[0]:311 5.534487e-06 +23 ropt_net_129:6 prog_clk[0]:313 0.0002132947 +24 ropt_net_129:6 prog_clk[0]:378 3.456563e-05 +25 ropt_net_129:4 prog_clk[0]:376 5.689583e-07 +26 ropt_net_129:4 prog_clk[0]:377 7.886489e-06 +27 ropt_net_129:5 prog_clk[0]:378 0.0002132947 +28 ropt_net_129:5 prog_clk[0]:379 3.456563e-05 +29 ropt_net_129:3 prog_clk[0]:375 5.689583e-07 +30 ropt_net_129:3 prog_clk[0]:376 7.886489e-06 + +*RES +0 BUFT_P_104:X ropt_net_129:10 0.152 +1 ropt_net_129:10 ropt_net_129:9 0.006497768 +2 ropt_net_129:9 ropt_net_129:8 0.0045 +3 ropt_net_129:8 ropt_net_129:7 0.001426339 +4 ropt_net_129:7 ropt_net_129:6 0.00341 +5 ropt_net_129:6 ropt_net_129:5 0.001655183 +6 ropt_net_129:4 ropt_net_129:3 0.002944197 +7 ropt_net_129:5 ropt_net_129:4 0.00341 +8 ropt_net_129:2 ropt_mt_inst_726:A 0.152 +9 ropt_net_129:3 ropt_net_129:2 0.0045 + +*END + +*D_NET chanx_left_in[5] 0.01758566 //LENGTH 108.100 LUMPCC 0.006012875 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 44.880 +*I mux_bottom_ipin_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 58.785 47.260 +*I mux_bottom_ipin_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 62.005 50.660 +*I FTB_6__5:A I *L 0.001776 *C 94.760 53.040 +*N chanx_left_in[5]:4 *C 94.760 53.040 +*N chanx_left_in[5]:5 *C 94.760 53.040 +*N chanx_left_in[5]:6 *C 94.760 52.700 +*N chanx_left_in[5]:7 *C 94.752 52.700 +*N chanx_left_in[5]:8 *C 93.880 52.700 +*N chanx_left_in[5]:9 *C 93.880 52.360 +*N chanx_left_in[5]:10 *C 63.028 52.360 +*N chanx_left_in[5]:11 *C 63.020 52.303 +*N chanx_left_in[5]:12 *C 62.043 50.660 +*N chanx_left_in[5]:13 *C 62.975 50.660 +*N chanx_left_in[5]:14 *C 63.020 50.660 +*N chanx_left_in[5]:15 *C 63.020 48.338 +*N chanx_left_in[5]:16 *C 63.013 48.280 +*N chanx_left_in[5]:17 *C 58.823 47.260 +*N chanx_left_in[5]:18 *C 59.340 47.260 +*N chanx_left_in[5]:19 *C 59.340 47.600 +*N chanx_left_in[5]:20 *C 59.340 47.645 +*N chanx_left_in[5]:21 *C 59.340 48.223 +*N chanx_left_in[5]:22 *C 59.340 48.280 +*N chanx_left_in[5]:23 *C 52.570 48.280 +*N chanx_left_in[5]:24 *C 2.780 48.280 +*N chanx_left_in[5]:25 *C 2.760 48.273 +*N chanx_left_in[5]:26 *C 2.760 45.568 +*N chanx_left_in[5]:27 *C 2.740 45.560 +*N chanx_left_in[5]:28 *C 1.840 45.560 +*N chanx_left_in[5]:29 *C 1.840 44.880 + +*CAP +0 chanx_left_in[5] 5.420644e-05 +1 mux_bottom_ipin_5\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_ipin_1\/mux_l1_in_2_:A1 1e-06 +3 FTB_6__5:A 1e-06 +4 chanx_left_in[5]:4 3.173847e-05 +5 chanx_left_in[5]:5 5.244856e-05 +6 chanx_left_in[5]:6 5.629123e-05 +7 chanx_left_in[5]:7 0.0001270935 +8 chanx_left_in[5]:8 0.000165944 +9 chanx_left_in[5]:9 0.001582818 +10 chanx_left_in[5]:10 0.001543967 +11 chanx_left_in[5]:11 7.599191e-05 +12 chanx_left_in[5]:12 9.870146e-05 +13 chanx_left_in[5]:13 9.870146e-05 +14 chanx_left_in[5]:14 0.0001744172 +15 chanx_left_in[5]:15 6.153005e-05 +16 chanx_left_in[5]:16 0.0002159028 +17 chanx_left_in[5]:17 4.871546e-05 +18 chanx_left_in[5]:18 7.701264e-05 +19 chanx_left_in[5]:19 6.105523e-05 +20 chanx_left_in[5]:20 5.900944e-05 +21 chanx_left_in[5]:21 5.900944e-05 +22 chanx_left_in[5]:22 0.0005620886 +23 chanx_left_in[5]:23 0.002983575 +24 chanx_left_in[5]:24 0.002637389 +25 chanx_left_in[5]:25 0.0002034475 +26 chanx_left_in[5]:26 0.0002034475 +27 chanx_left_in[5]:27 8.622583e-05 +28 chanx_left_in[5]:28 0.0001405366 +29 chanx_left_in[5]:29 0.0001085172 +30 chanx_left_in[5] chanx_left_in[3] 7.020996e-06 +31 chanx_left_in[5]:24 chanx_left_in[3] 0.0005056619 +32 chanx_left_in[5]:27 chanx_left_in[3]:66 2.465308e-05 +33 chanx_left_in[5]:16 chanx_left_in[3]:38 2.41513e-06 +34 chanx_left_in[5]:22 chanx_left_in[3]:38 3.286864e-07 +35 chanx_left_in[5]:22 chanx_left_in[3]:44 2.872433e-06 +36 chanx_left_in[5]:10 chanx_left_in[3]:26 6.013508e-05 +37 chanx_left_in[5]:10 chanx_left_in[3]:38 0.0003786061 +38 chanx_left_in[5]:10 chanx_left_in[3]:44 5.087818e-05 +39 chanx_left_in[5]:29 chanx_left_in[3]:66 7.020996e-06 +40 chanx_left_in[5]:28 chanx_left_in[3] 2.465308e-05 +41 chanx_left_in[5]:9 chanx_left_in[3]:13 6.013508e-05 +42 chanx_left_in[5]:9 chanx_left_in[3]:26 0.0003786061 +43 chanx_left_in[5]:9 chanx_left_in[3]:38 5.087818e-05 +44 chanx_left_in[5]:23 chanx_left_in[3]:44 3.286864e-07 +45 chanx_left_in[5]:23 chanx_left_in[3]:45 4.573027e-07 +46 chanx_left_in[5]:23 chanx_left_in[3]:66 0.0005056619 +47 chanx_left_in[5]:24 chanx_left_in[11] 1.276332e-06 +48 chanx_left_in[5]:10 chanx_left_in[11]:27 0.001004987 +49 chanx_left_in[5]:9 chanx_left_in[11]:18 0.001004987 +50 chanx_left_in[5]:23 chanx_left_in[11]:36 1.276332e-06 +51 chanx_left_in[5]:24 chanx_right_in[5]:14 0.0002062798 +52 chanx_left_in[5]:15 chanx_right_in[5]:26 4.172022e-05 +53 chanx_left_in[5]:15 chanx_right_in[5]:27 4.166907e-06 +54 chanx_left_in[5]:22 chanx_right_in[5]:15 0.0001206237 +55 chanx_left_in[5]:17 chanx_right_in[5]:24 3.706307e-06 +56 chanx_left_in[5]:13 chanx_right_in[5]:22 1.601364e-06 +57 chanx_left_in[5]:13 chanx_right_in[5]:21 2.146045e-06 +58 chanx_left_in[5]:14 chanx_right_in[5]:23 4.172022e-05 +59 chanx_left_in[5]:14 chanx_right_in[5]:26 4.166907e-06 +60 chanx_left_in[5]:12 chanx_right_in[5]:21 1.601364e-06 +61 chanx_left_in[5]:12 chanx_right_in[5]:20 2.146045e-06 +62 chanx_left_in[5]:18 chanx_right_in[5]:25 3.706307e-06 +63 chanx_left_in[5]:23 chanx_right_in[5]:15 0.0002062798 +64 chanx_left_in[5]:23 chanx_right_in[5]:14 0.0001206237 +65 chanx_left_in[5]:27 prog_clk[0]:365 1.889418e-05 +66 chanx_left_in[5]:16 prog_clk[0]:259 0.0002066454 +67 chanx_left_in[5]:21 prog_clk[0]:261 3.199006e-06 +68 chanx_left_in[5]:22 prog_clk[0]:260 0.0002066454 +69 chanx_left_in[5]:22 prog_clk[0]:259 5.803486e-05 +70 chanx_left_in[5]:20 prog_clk[0]:265 3.199006e-06 +71 chanx_left_in[5]:29 prog_clk[0]:370 1.122632e-05 +72 chanx_left_in[5]:28 prog_clk[0]:367 1.122632e-05 +73 chanx_left_in[5]:28 prog_clk[0]:366 1.889418e-05 +74 chanx_left_in[5]:23 prog_clk[0]:260 5.803486e-05 +75 chanx_left_in[5]:24 mux_tree_tapbuf_size8_1_sram[3]:10 0.000177661 +76 chanx_left_in[5]:23 mux_tree_tapbuf_size8_1_sram[3]:11 0.000177661 +77 chanx_left_in[5]:15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.572357e-05 +78 chanx_left_in[5]:11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.838925e-05 +79 chanx_left_in[5]:14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.572357e-05 +80 chanx_left_in[5]:14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.838925e-05 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:29 9.556665e-05 +1 chanx_left_in[5]:24 chanx_left_in[5]:23 0.007800433 +2 chanx_left_in[5]:25 chanx_left_in[5]:24 0.00341 +3 chanx_left_in[5]:27 chanx_left_in[5]:26 0.00341 +4 chanx_left_in[5]:26 chanx_left_in[5]:25 0.0004237833 +5 chanx_left_in[5]:15 chanx_left_in[5]:14 0.002073661 +6 chanx_left_in[5]:16 chanx_left_in[5]:15 0.00341 +7 chanx_left_in[5]:21 chanx_left_in[5]:20 0.000515625 +8 chanx_left_in[5]:22 chanx_left_in[5]:21 0.00341 +9 chanx_left_in[5]:22 chanx_left_in[5]:16 0.0005753583 +10 chanx_left_in[5]:19 chanx_left_in[5]:18 0.0003035715 +11 chanx_left_in[5]:20 chanx_left_in[5]:19 0.0045 +12 chanx_left_in[5]:17 mux_bottom_ipin_5\/mux_l1_in_2_:A1 0.152 +13 chanx_left_in[5]:11 chanx_left_in[5]:10 0.00341 +14 chanx_left_in[5]:10 chanx_left_in[5]:9 0.004833558 +15 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0001634615 +16 chanx_left_in[5]:7 chanx_left_in[5]:6 0.00341 +17 chanx_left_in[5]:4 FTB_6__5:A 0.152 +18 chanx_left_in[5]:5 chanx_left_in[5]:4 0.0045 +19 chanx_left_in[5]:13 chanx_left_in[5]:12 0.0008325893 +20 chanx_left_in[5]:14 chanx_left_in[5]:13 0.0045 +21 chanx_left_in[5]:14 chanx_left_in[5]:11 0.001466518 +22 chanx_left_in[5]:12 mux_bottom_ipin_1\/mux_l1_in_2_:A1 0.152 +23 chanx_left_in[5]:18 chanx_left_in[5]:17 0.0004620535 +24 chanx_left_in[5]:29 chanx_left_in[5]:28 0.0001065333 +25 chanx_left_in[5]:28 chanx_left_in[5]:27 0.000141 +26 chanx_left_in[5]:9 chanx_left_in[5]:8 5.326666e-05 +27 chanx_left_in[5]:8 chanx_left_in[5]:7 0.0001366917 +28 chanx_left_in[5]:23 chanx_left_in[5]:22 0.001060633 + +*END + +*D_NET chanx_right_in[16] 0.009980883 //LENGTH 90.790 LUMPCC 0.001960165 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 103.650 4.760 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 62.925 9.180 +*I BUFT_P_104:A I *L 0.001776 *C 23.460 9.520 +*I mux_bottom_ipin_12\/mux_l2_in_3_:A1 I *L 0.00198 *C 72.320 12.580 +*N chanx_right_in[16]:4 *C 72.282 12.580 +*N chanx_right_in[16]:5 *C 71.805 12.580 +*N chanx_right_in[16]:6 *C 71.760 12.535 +*N chanx_right_in[16]:7 *C 27.600 9.180 +*N chanx_right_in[16]:8 *C 23.498 9.520 +*N chanx_right_in[16]:9 *C 27.600 9.520 +*N chanx_right_in[16]:10 *C 61.640 9.520 +*N chanx_right_in[16]:11 *C 61.640 9.180 +*N chanx_right_in[16]:12 *C 62.925 9.180 +*N chanx_right_in[16]:13 *C 71.715 9.180 +*N chanx_right_in[16]:14 *C 71.760 9.180 +*N chanx_right_in[16]:15 *C 71.760 4.817 +*N chanx_right_in[16]:16 *C 71.767 4.760 + +*CAP +0 chanx_right_in[16] 0.001235771 +1 mux_bottom_ipin_0\/mux_l2_in_3_:A1 1e-06 +2 BUFT_P_104:A 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_3_:A1 1e-06 +4 chanx_right_in[16]:4 6.143566e-05 +5 chanx_right_in[16]:5 6.143566e-05 +6 chanx_right_in[16]:6 0.0001791444 +7 chanx_right_in[16]:7 2.697348e-05 +8 chanx_right_in[16]:8 0.0001487226 +9 chanx_right_in[16]:9 0.001588288 +10 chanx_right_in[16]:10 0.001438222 +11 chanx_right_in[16]:11 0.0001220458 +12 chanx_right_in[16]:12 0.000692871 +13 chanx_right_in[16]:13 0.0005704001 +14 chanx_right_in[16]:14 0.0004328148 +15 chanx_right_in[16]:15 0.0002238233 +16 chanx_right_in[16]:16 0.001235771 +17 chanx_right_in[16] chanx_right_in[15]:33 0.0003334423 +18 chanx_right_in[16] chanx_right_in[15]:34 0.0001555055 +19 chanx_right_in[16]:13 chanx_right_in[15]:33 5.102063e-06 +20 chanx_right_in[16]:16 chanx_right_in[15]:32 0.0003334423 +21 chanx_right_in[16]:16 chanx_right_in[15]:33 0.0001555055 +22 chanx_right_in[16]:12 chanx_right_in[15]:32 5.102063e-06 +23 chanx_right_in[16]:9 chanx_right_in[15]:32 2.13117e-05 +24 chanx_right_in[16]:10 chanx_right_in[15]:33 2.13117e-05 +25 chanx_right_in[16]:8 chanx_right_in[17]:9 7.913889e-05 +26 chanx_right_in[16]:9 chanx_right_in[17]:10 7.913889e-05 +27 chanx_right_in[16]:9 chanx_right_in[17]:9 0.000385582 +28 chanx_right_in[16]:10 chanx_right_in[17]:10 0.000385582 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:16 0.004994925 +1 chanx_right_in[16]:13 chanx_right_in[16]:12 0.007848214 +2 chanx_right_in[16]:14 chanx_right_in[16]:13 0.0045 +3 chanx_right_in[16]:14 chanx_right_in[16]:6 0.002995536 +4 chanx_right_in[16]:15 chanx_right_in[16]:14 0.003895089 +5 chanx_right_in[16]:16 chanx_right_in[16]:15 0.00341 +6 chanx_right_in[16]:8 BUFT_P_104:A 0.152 +7 chanx_right_in[16]:5 chanx_right_in[16]:4 0.0004263393 +8 chanx_right_in[16]:6 chanx_right_in[16]:5 0.0045 +9 chanx_right_in[16]:4 mux_bottom_ipin_12\/mux_l2_in_3_:A1 0.152 +10 chanx_right_in[16]:12 mux_bottom_ipin_0\/mux_l2_in_3_:A1 0.152 +11 chanx_right_in[16]:12 chanx_right_in[16]:11 0.001147322 +12 chanx_right_in[16]:9 chanx_right_in[16]:8 0.003662947 +13 chanx_right_in[16]:9 chanx_right_in[16]:7 0.0003035715 +14 chanx_right_in[16]:10 chanx_right_in[16]:9 0.03039286 +15 chanx_right_in[16]:11 chanx_right_in[16]:10 0.0003035715 + +*END + +*D_NET top_grid_pin_17_[0] 0.001401125 //LENGTH 12.375 LUMPCC 0.0001377177 DR + +*CONN +*I mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 42.320 69.700 +*P top_grid_pin_17_[0] O *L 0.7423 *C 35.880 74.835 +*N top_grid_pin_17_[0]:2 *C 35.880 72.125 +*N top_grid_pin_17_[0]:3 *C 35.925 72.080 +*N top_grid_pin_17_[0]:4 *C 42.275 72.080 +*N top_grid_pin_17_[0]:5 *C 42.320 72.035 +*N top_grid_pin_17_[0]:6 *C 42.320 69.745 +*N top_grid_pin_17_[0]:7 *C 42.320 69.700 + +*CAP +0 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_17_[0] 0.0001832068 +2 top_grid_pin_17_[0]:2 0.0001832068 +3 top_grid_pin_17_[0]:3 0.0003035178 +4 top_grid_pin_17_[0]:4 0.0003035178 +5 top_grid_pin_17_[0]:5 0.0001284574 +6 top_grid_pin_17_[0]:6 0.0001284574 +7 top_grid_pin_17_[0]:7 3.204336e-05 +8 top_grid_pin_17_[0]:3 ropt_net_134:6 6.623229e-05 +9 top_grid_pin_17_[0]:4 ropt_net_134:7 6.623229e-05 +10 top_grid_pin_17_[0]:5 ropt_net_134:5 2.626561e-06 +11 top_grid_pin_17_[0]:6 ropt_net_134:4 2.626561e-06 + +*RES +0 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_17_[0]:7 0.152 +1 top_grid_pin_17_[0]:3 top_grid_pin_17_[0]:2 0.0045 +2 top_grid_pin_17_[0]:2 top_grid_pin_17_[0] 0.002419643 +3 top_grid_pin_17_[0]:4 top_grid_pin_17_[0]:3 0.005669643 +4 top_grid_pin_17_[0]:5 top_grid_pin_17_[0]:4 0.0045 +5 top_grid_pin_17_[0]:7 top_grid_pin_17_[0]:6 0.0045 +6 top_grid_pin_17_[0]:6 top_grid_pin_17_[0]:5 0.002044643 + +*END + +*D_NET top_grid_pin_28_[0] 0.0008559641 //LENGTH 8.340 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 76.305 69.700 +*P top_grid_pin_28_[0] O *L 0.7423 *C 73.600 74.870 +*N top_grid_pin_28_[0]:2 *C 73.600 69.745 +*N top_grid_pin_28_[0]:3 *C 73.645 69.700 +*N top_grid_pin_28_[0]:4 *C 76.267 69.700 + +*CAP +0 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_28_[0] 0.0002671558 +2 top_grid_pin_28_[0]:2 0.0002671558 +3 top_grid_pin_28_[0]:3 0.0001603263 +4 top_grid_pin_28_[0]:4 0.0001603263 + +*RES +0 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_28_[0]:4 0.152 +1 top_grid_pin_28_[0]:4 top_grid_pin_28_[0]:3 0.002341518 +2 top_grid_pin_28_[0]:3 top_grid_pin_28_[0]:2 0.0045 +3 top_grid_pin_28_[0]:2 top_grid_pin_28_[0] 0.004575893 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.006217495 //LENGTH 45.845 LUMPCC 0.000675518 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.445 55.760 +*I mux_bottom_ipin_1\/mux_l2_in_1_:S I *L 0.00357 *C 58.060 56.055 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 50.315 66.300 +*I mux_bottom_ipin_1\/mux_l2_in_2_:S I *L 0.00357 *C 52.540 63.630 +*I mux_bottom_ipin_1\/mux_l2_in_3_:S I *L 0.00357 *C 49.780 55.760 +*I mux_bottom_ipin_1\/mux_l2_in_0_:S I *L 0.00357 *C 62.200 56.055 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 62.200 56.055 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 58.060 56.130 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 49.818 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 52.540 63.630 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 52.430 63.920 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 50.315 66.300 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 50.600 66.300 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 50.600 66.255 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 50.600 63.965 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 50.645 63.920 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 52.453 63.920 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 52.870 63.890 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 52.900 63.875 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 52.900 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 53.360 61.880 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 53.360 55.805 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 53.360 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 58.003 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:24 *C 58.060 56.055 +*N mux_tree_tapbuf_size10_1_sram[1]:25 *C 58.060 56.440 +*N mux_tree_tapbuf_size10_1_sram[1]:26 *C 62.200 56.440 +*N mux_tree_tapbuf_size10_1_sram[1]:27 *C 65.735 56.440 +*N mux_tree_tapbuf_size10_1_sram[1]:28 *C 65.780 56.485 +*N mux_tree_tapbuf_size10_1_sram[1]:29 *C 65.780 57.755 +*N mux_tree_tapbuf_size10_1_sram[1]:30 *C 65.825 57.800 +*N mux_tree_tapbuf_size10_1_sram[1]:31 *C 72.175 57.800 +*N mux_tree_tapbuf_size10_1_sram[1]:32 *C 72.220 57.755 +*N mux_tree_tapbuf_size10_1_sram[1]:33 *C 72.220 55.805 +*N mux_tree_tapbuf_size10_1_sram[1]:34 *C 72.265 55.760 +*N mux_tree_tapbuf_size10_1_sram[1]:35 *C 73.407 55.760 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_1_:S 1e-06 +2 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_1\/mux_l2_in_2_:S 1e-06 +4 mux_bottom_ipin_1\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_1\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 6.252741e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:7 1.386764e-05 +8 mux_tree_tapbuf_size10_1_sram[1]:8 0.000243948 +9 mux_tree_tapbuf_size10_1_sram[1]:9 5.562219e-05 +10 mux_tree_tapbuf_size10_1_sram[1]:10 4.628642e-05 +11 mux_tree_tapbuf_size10_1_sram[1]:11 5.042612e-05 +12 mux_tree_tapbuf_size10_1_sram[1]:12 5.39102e-05 +13 mux_tree_tapbuf_size10_1_sram[1]:13 0.0001480177 +14 mux_tree_tapbuf_size10_1_sram[1]:14 0.0001480177 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0001560588 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0002257868 +17 mux_tree_tapbuf_size10_1_sram[1]:17 5.169884e-05 +18 mux_tree_tapbuf_size10_1_sram[1]:18 0.0001296467 +19 mux_tree_tapbuf_size10_1_sram[1]:19 0.0001611497 +20 mux_tree_tapbuf_size10_1_sram[1]:20 0.0003472198 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.0003157168 +22 mux_tree_tapbuf_size10_1_sram[1]:22 0.0005692886 +23 mux_tree_tapbuf_size10_1_sram[1]:23 0.0003111128 +24 mux_tree_tapbuf_size10_1_sram[1]:24 8.353387e-05 +25 mux_tree_tapbuf_size10_1_sram[1]:25 0.000258976 +26 mux_tree_tapbuf_size10_1_sram[1]:26 0.0004980974 +27 mux_tree_tapbuf_size10_1_sram[1]:27 0.0002259523 +28 mux_tree_tapbuf_size10_1_sram[1]:28 0.0001077754 +29 mux_tree_tapbuf_size10_1_sram[1]:29 0.0001077754 +30 mux_tree_tapbuf_size10_1_sram[1]:30 0.0003681376 +31 mux_tree_tapbuf_size10_1_sram[1]:31 0.0003681376 +32 mux_tree_tapbuf_size10_1_sram[1]:32 0.0001287563 +33 mux_tree_tapbuf_size10_1_sram[1]:33 0.0001287563 +34 mux_tree_tapbuf_size10_1_sram[1]:34 8.488801e-05 +35 mux_tree_tapbuf_size10_1_sram[1]:35 8.488801e-05 +36 mux_tree_tapbuf_size10_1_sram[1]:27 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.878097e-05 +37 mux_tree_tapbuf_size10_1_sram[1]:26 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.878097e-05 +38 mux_tree_tapbuf_size10_1_sram[1]:25 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.170692e-05 +39 mux_tree_tapbuf_size10_1_sram[1]:26 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.170692e-05 +40 mux_tree_tapbuf_size10_1_sram[1]:21 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.664932e-05 +41 mux_tree_tapbuf_size10_1_sram[1]:20 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.664932e-05 +42 mux_tree_tapbuf_size10_1_sram[1]:30 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001306218 +43 mux_tree_tapbuf_size10_1_sram[1]:31 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001306218 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:35 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:9 mux_bottom_ipin_1\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[1]:11 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +3 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 0.0001548913 +4 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.0045 +6 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[1]:13 0.002044643 +7 mux_tree_tapbuf_size10_1_sram[1]:24 mux_bottom_ipin_1\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:23 0.0001715116 +9 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:7 4.360465e-05 +10 mux_tree_tapbuf_size10_1_sram[1]:6 mux_bottom_ipin_1\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size10_1_sram[1]:8 mux_bottom_ipin_1\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_1_sram[1]:22 mux_tree_tapbuf_size10_1_sram[1]:21 0.0045 +13 mux_tree_tapbuf_size10_1_sram[1]:22 mux_tree_tapbuf_size10_1_sram[1]:8 0.003162947 +14 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.005424107 +15 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.0002609375 +16 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[1]:17 0.0045 +17 mux_tree_tapbuf_size10_1_sram[1]:27 mux_tree_tapbuf_size10_1_sram[1]:26 0.00315625 +18 mux_tree_tapbuf_size10_1_sram[1]:28 mux_tree_tapbuf_size10_1_sram[1]:27 0.0045 +19 mux_tree_tapbuf_size10_1_sram[1]:30 mux_tree_tapbuf_size10_1_sram[1]:29 0.0045 +20 mux_tree_tapbuf_size10_1_sram[1]:29 mux_tree_tapbuf_size10_1_sram[1]:28 0.001133929 +21 mux_tree_tapbuf_size10_1_sram[1]:31 mux_tree_tapbuf_size10_1_sram[1]:30 0.005669643 +22 mux_tree_tapbuf_size10_1_sram[1]:32 mux_tree_tapbuf_size10_1_sram[1]:31 0.0045 +23 mux_tree_tapbuf_size10_1_sram[1]:34 mux_tree_tapbuf_size10_1_sram[1]:33 0.0045 +24 mux_tree_tapbuf_size10_1_sram[1]:33 mux_tree_tapbuf_size10_1_sram[1]:32 0.001741072 +25 mux_tree_tapbuf_size10_1_sram[1]:35 mux_tree_tapbuf_size10_1_sram[1]:34 0.001020089 +26 mux_tree_tapbuf_size10_1_sram[1]:23 mux_tree_tapbuf_size10_1_sram[1]:22 0.00414509 +27 mux_tree_tapbuf_size10_1_sram[1]:10 mux_tree_tapbuf_size10_1_sram[1]:9 0.000125 +28 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.001613839 +29 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:10 2.008929e-05 +30 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:24 0.00034375 +31 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:25 0.003696429 +32 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:6 0.00034375 +33 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.00178125 +34 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_1_ccff_tail[0] 0.004190665 //LENGTH 31.585 LUMPCC 0.0008772088 DR + +*CONN +*I mem_bottom_ipin_1\/FTB_2__41:X O *L 0 *C 41.165 58.480 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.355 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 *C 38.355 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 *C 38.180 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 *C 38.180 31.665 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 *C 38.180 32.583 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 *C 38.183 32.640 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 *C 38.625 32.640 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 *C 38.640 32.648 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 *C 38.640 58.473 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 *C 38.660 58.480 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 *C 40.933 58.480 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:12 *C 40.940 58.480 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:13 *C 40.940 58.480 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:14 *C 41.165 58.480 + +*CAP +0 mem_bottom_ipin_1\/FTB_2__41:X 1e-06 +1 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 5.321042e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 5.730748e-05 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 7.390614e-05 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 7.390614e-05 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 6.118046e-05 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 6.118046e-05 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 0.001288129 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 0.001288129 +10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 0.0001062862 +11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 0.0001062862 +12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:12 3.527177e-05 +13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:13 5.691734e-05 +14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:14 4.974634e-05 +15 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 chanx_left_in[13]:13 0.0001458615 +16 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 chanx_left_in[13]:14 0.0001458615 +17 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 chanx_left_in[13]:14 9.174879e-06 +18 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 chanx_left_in[13]:15 9.174879e-06 +19 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 chanx_right_in[11]:20 0.000283568 +20 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 chanx_right_in[11]:19 0.000283568 + +*RES +0 mem_bottom_ipin_1\/FTB_2__41:X mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:14 0.152 +1 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:13 0.0001222826 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:12 0.0045 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 0.00341 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 0.000356025 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 0.00341 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 0.004045916 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 6.499219e-05 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.00341 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0008191965 +10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.00341 +11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 9.51087e-05 +12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 0.0045 +13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[1] 0.004482133 //LENGTH 33.665 LUMPCC 0.0001856757 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 45.845 55.420 +*I mux_bottom_ipin_7\/mux_l2_in_2_:S I *L 0.00357 *C 35.520 57.800 +*I mux_bottom_ipin_7\/mux_l2_in_1_:S I *L 0.00357 *C 33.120 55.935 +*I mux_bottom_ipin_7\/mux_l2_in_0_:S I *L 0.00357 *C 35.060 56.055 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.385 64.260 +*I mux_bottom_ipin_7\/mux_l2_in_3_:S I *L 0.00357 *C 38.740 61.495 +*N mux_tree_tapbuf_size8_3_sram[1]:6 *C 38.740 61.495 +*N mux_tree_tapbuf_size8_3_sram[1]:7 *C 32.422 64.260 +*N mux_tree_tapbuf_size8_3_sram[1]:8 *C 35.375 64.260 +*N mux_tree_tapbuf_size8_3_sram[1]:9 *C 35.420 64.215 +*N mux_tree_tapbuf_size8_3_sram[1]:10 *C 35.060 56.055 +*N mux_tree_tapbuf_size8_3_sram[1]:11 *C 34.950 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:12 *C 33.157 55.825 +*N mux_tree_tapbuf_size8_3_sram[1]:13 *C 34.973 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:14 *C 35.390 55.790 +*N mux_tree_tapbuf_size8_3_sram[1]:15 *C 35.420 55.805 +*N mux_tree_tapbuf_size8_3_sram[1]:16 *C 35.420 57.800 +*N mux_tree_tapbuf_size8_3_sram[1]:17 *C 35.420 57.800 +*N mux_tree_tapbuf_size8_3_sram[1]:18 *C 35.420 61.540 +*N mux_tree_tapbuf_size8_3_sram[1]:19 *C 35.465 61.540 +*N mux_tree_tapbuf_size8_3_sram[1]:20 *C 38.180 61.540 +*N mux_tree_tapbuf_size8_3_sram[1]:21 *C 38.180 61.200 +*N mux_tree_tapbuf_size8_3_sram[1]:22 *C 38.740 61.200 +*N mux_tree_tapbuf_size8_3_sram[1]:23 *C 42.735 61.200 +*N mux_tree_tapbuf_size8_3_sram[1]:24 *C 42.780 61.155 +*N mux_tree_tapbuf_size8_3_sram[1]:25 *C 42.780 55.465 +*N mux_tree_tapbuf_size8_3_sram[1]:26 *C 42.825 55.420 +*N mux_tree_tapbuf_size8_3_sram[1]:27 *C 45.808 55.420 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_7\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_7\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_0_:S 1e-06 +4 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_ipin_7\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_3_sram[1]:6 5.981612e-05 +7 mux_tree_tapbuf_size8_3_sram[1]:7 0.0002047294 +8 mux_tree_tapbuf_size8_3_sram[1]:8 0.0002047294 +9 mux_tree_tapbuf_size8_3_sram[1]:9 0.0001353893 +10 mux_tree_tapbuf_size8_3_sram[1]:10 6.012381e-05 +11 mux_tree_tapbuf_size8_3_sram[1]:11 4.754084e-05 +12 mux_tree_tapbuf_size8_3_sram[1]:12 0.0001392413 +13 mux_tree_tapbuf_size8_3_sram[1]:13 0.0002075189 +14 mux_tree_tapbuf_size8_3_sram[1]:14 5.143831e-05 +15 mux_tree_tapbuf_size8_3_sram[1]:15 9.953525e-05 +16 mux_tree_tapbuf_size8_3_sram[1]:16 3.888113e-05 +17 mux_tree_tapbuf_size8_3_sram[1]:17 0.0003072836 +18 mux_tree_tapbuf_size8_3_sram[1]:18 0.0003433894 +19 mux_tree_tapbuf_size8_3_sram[1]:19 0.0002375928 +20 mux_tree_tapbuf_size8_3_sram[1]:20 0.0002471176 +21 mux_tree_tapbuf_size8_3_sram[1]:21 5.361437e-05 +22 mux_tree_tapbuf_size8_3_sram[1]:22 0.0003521785 +23 mux_tree_tapbuf_size8_3_sram[1]:23 0.0002775444 +24 mux_tree_tapbuf_size8_3_sram[1]:24 0.0004014139 +25 mux_tree_tapbuf_size8_3_sram[1]:25 0.0004014139 +26 mux_tree_tapbuf_size8_3_sram[1]:26 0.0002099824 +27 mux_tree_tapbuf_size8_3_sram[1]:27 0.0002099824 +28 mux_tree_tapbuf_size8_3_sram[1]:18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.987135e-05 +29 mux_tree_tapbuf_size8_3_sram[1]:18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.919853e-05 +30 mux_tree_tapbuf_size8_3_sram[1]:9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.919853e-05 +31 mux_tree_tapbuf_size8_3_sram[1]:17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.3768e-05 +32 mux_tree_tapbuf_size8_3_sram[1]:17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.987135e-05 +33 mux_tree_tapbuf_size8_3_sram[1]:15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.3768e-05 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_3_sram[1]:27 0.152 +1 mux_tree_tapbuf_size8_3_sram[1]:10 mux_bottom_ipin_7\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_3_sram[1]:19 mux_tree_tapbuf_size8_3_sram[1]:18 0.0045 +3 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:17 0.003339286 +4 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:9 0.002388393 +5 mux_tree_tapbuf_size8_3_sram[1]:23 mux_tree_tapbuf_size8_3_sram[1]:22 0.003566965 +6 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:23 0.0045 +7 mux_tree_tapbuf_size8_3_sram[1]:26 mux_tree_tapbuf_size8_3_sram[1]:25 0.0045 +8 mux_tree_tapbuf_size8_3_sram[1]:25 mux_tree_tapbuf_size8_3_sram[1]:24 0.005080357 +9 mux_tree_tapbuf_size8_3_sram[1]:27 mux_tree_tapbuf_size8_3_sram[1]:26 0.002662946 +10 mux_tree_tapbuf_size8_3_sram[1]:7 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size8_3_sram[1]:8 mux_tree_tapbuf_size8_3_sram[1]:7 0.002636161 +12 mux_tree_tapbuf_size8_3_sram[1]:9 mux_tree_tapbuf_size8_3_sram[1]:8 0.0045 +13 mux_tree_tapbuf_size8_3_sram[1]:6 mux_bottom_ipin_7\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size8_3_sram[1]:16 mux_bottom_ipin_7\/mux_l2_in_2_:S 0.152 +15 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:16 0.0045 +16 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:15 0.00178125 +17 mux_tree_tapbuf_size8_3_sram[1]:12 mux_bottom_ipin_7\/mux_l2_in_1_:S 0.152 +18 mux_tree_tapbuf_size8_3_sram[1]:14 mux_tree_tapbuf_size8_3_sram[1]:13 0.0002609376 +19 mux_tree_tapbuf_size8_3_sram[1]:15 mux_tree_tapbuf_size8_3_sram[1]:14 0.0045 +20 mux_tree_tapbuf_size8_3_sram[1]:11 mux_tree_tapbuf_size8_3_sram[1]:10 0.0001271552 +21 mux_tree_tapbuf_size8_3_sram[1]:13 mux_tree_tapbuf_size8_3_sram[1]:12 0.001620536 +22 mux_tree_tapbuf_size8_3_sram[1]:13 mux_tree_tapbuf_size8_3_sram[1]:11 2.008929e-05 +23 mux_tree_tapbuf_size8_3_sram[1]:20 mux_tree_tapbuf_size8_3_sram[1]:19 0.002424107 +24 mux_tree_tapbuf_size8_3_sram[1]:21 mux_tree_tapbuf_size8_3_sram[1]:20 0.0003035715 +25 mux_tree_tapbuf_size8_3_sram[1]:22 mux_tree_tapbuf_size8_3_sram[1]:21 0.0005 +26 mux_tree_tapbuf_size8_3_sram[1]:22 mux_tree_tapbuf_size8_3_sram[1]:6 0.0001271552 + +*END + +*D_NET optlc_net_124 0.008379004 //LENGTH 60.600 LUMPCC 0.001177702 DR + +*CONN +*I optlc_122:HI O *L 0 *C 25.300 42.500 +*I mux_bottom_ipin_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 36.515 38.760 +*I mux_bottom_ipin_11\/mux_l2_in_3_:A0 I *L 0.001631 *C 24.670 33.320 +*I mux_bottom_ipin_10\/mux_l2_in_3_:A0 I *L 0.001631 *C 24.210 22.780 +*I mux_bottom_ipin_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 19.150 58.820 +*I mux_bottom_ipin_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 17.770 42.840 +*N optlc_net_124:6 *C 17.808 42.840 +*N optlc_net_124:7 *C 19.150 58.820 +*N optlc_net_124:8 *C 19.320 58.820 +*N optlc_net_124:9 *C 19.320 58.775 +*N optlc_net_124:10 *C 19.320 42.885 +*N optlc_net_124:11 *C 19.320 42.840 +*N optlc_net_124:12 *C 23.000 42.840 +*N optlc_net_124:13 *C 23.000 42.500 +*N optlc_net_124:14 *C 24.248 22.780 +*N optlc_net_124:15 *C 24.795 22.780 +*N optlc_net_124:16 *C 24.840 22.825 +*N optlc_net_124:17 *C 24.670 33.320 +*N optlc_net_124:18 *C 24.840 33.320 +*N optlc_net_124:19 *C 24.840 33.320 +*N optlc_net_124:20 *C 24.840 37.400 +*N optlc_net_124:21 *C 36.515 38.760 +*N optlc_net_124:22 *C 36.340 38.760 +*N optlc_net_124:23 *C 36.340 38.715 +*N optlc_net_124:24 *C 36.340 37.458 +*N optlc_net_124:25 *C 36.333 37.400 +*N optlc_net_124:26 *C 25.308 37.400 +*N optlc_net_124:27 *C 25.300 37.458 +*N optlc_net_124:28 *C 25.300 42.455 +*N optlc_net_124:29 *C 25.263 42.500 + +*CAP +0 optlc_122:HI 1e-06 +1 mux_bottom_ipin_3\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_11\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_10\/mux_l2_in_3_:A0 1e-06 +4 mux_bottom_ipin_9\/mux_l2_in_3_:A0 1e-06 +5 mux_bottom_ipin_8\/mux_l2_in_3_:A0 1e-06 +6 optlc_net_124:6 0.0001177203 +7 optlc_net_124:7 4.94134e-05 +8 optlc_net_124:8 5.093669e-05 +9 optlc_net_124:9 0.0009018616 +10 optlc_net_124:10 0.0009018616 +11 optlc_net_124:11 0.0004019211 +12 optlc_net_124:12 0.0002732751 +13 optlc_net_124:13 0.0001254906 +14 optlc_net_124:14 5.723445e-05 +15 optlc_net_124:15 5.723445e-05 +16 optlc_net_124:16 0.0006065919 +17 optlc_net_124:17 5.710504e-05 +18 optlc_net_124:18 6.148106e-05 +19 optlc_net_124:19 0.0008802132 +20 optlc_net_124:20 0.0002758203 +21 optlc_net_124:21 5.290721e-05 +22 optlc_net_124:22 5.718707e-05 +23 optlc_net_124:23 9.737265e-05 +24 optlc_net_124:24 9.737265e-05 +25 optlc_net_124:25 0.0006599063 +26 optlc_net_124:26 0.0006599063 +27 optlc_net_124:27 0.0003442507 +28 optlc_net_124:28 0.0003088502 +29 optlc_net_124:29 9.938738e-05 +30 optlc_net_124:26 mux_tree_tapbuf_size8_5_sram[3]:12 0.0004814526 +31 optlc_net_124:25 mux_tree_tapbuf_size8_5_sram[3]:13 0.0004814526 +32 optlc_net_124:11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.504213e-05 +33 optlc_net_124:27 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.707723e-05 +34 optlc_net_124:29 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.527899e-05 +35 optlc_net_124:28 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.707723e-05 +36 optlc_net_124:12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.504213e-05 +37 optlc_net_124:13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.527899e-05 + +*RES +0 optlc_122:HI optlc_net_124:29 0.152 +1 optlc_net_124:11 optlc_net_124:10 0.0045 +2 optlc_net_124:11 optlc_net_124:6 0.001350446 +3 optlc_net_124:10 optlc_net_124:9 0.0141875 +4 optlc_net_124:8 optlc_net_124:7 9.239131e-05 +5 optlc_net_124:9 optlc_net_124:8 0.0045 +6 optlc_net_124:7 mux_bottom_ipin_9\/mux_l2_in_3_:A0 0.152 +7 optlc_net_124:27 optlc_net_124:26 0.00341 +8 optlc_net_124:27 optlc_net_124:20 0.0004107143 +9 optlc_net_124:26 optlc_net_124:25 0.00172725 +10 optlc_net_124:24 optlc_net_124:23 0.001122768 +11 optlc_net_124:25 optlc_net_124:24 0.00341 +12 optlc_net_124:22 optlc_net_124:21 9.51087e-05 +13 optlc_net_124:23 optlc_net_124:22 0.0045 +14 optlc_net_124:21 mux_bottom_ipin_3\/mux_l2_in_3_:A0 0.152 +15 optlc_net_124:29 optlc_net_124:28 0.0045 +16 optlc_net_124:29 optlc_net_124:13 0.002020089 +17 optlc_net_124:28 optlc_net_124:27 0.004462054 +18 optlc_net_124:18 optlc_net_124:17 9.239131e-05 +19 optlc_net_124:19 optlc_net_124:18 0.0045 +20 optlc_net_124:19 optlc_net_124:16 0.009370536 +21 optlc_net_124:17 mux_bottom_ipin_11\/mux_l2_in_3_:A0 0.152 +22 optlc_net_124:15 optlc_net_124:14 0.0004888393 +23 optlc_net_124:16 optlc_net_124:15 0.0045 +24 optlc_net_124:14 mux_bottom_ipin_10\/mux_l2_in_3_:A0 0.152 +25 optlc_net_124:6 mux_bottom_ipin_8\/mux_l2_in_3_:A0 0.152 +26 optlc_net_124:12 optlc_net_124:11 0.003285714 +27 optlc_net_124:13 optlc_net_124:12 0.0003035715 +28 optlc_net_124:20 optlc_net_124:19 0.003642857 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007968956 //LENGTH 5.765 LUMPCC 0.000236749 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_0_:X O *L 0 *C 20.040 26.520 +*I mux_bottom_ipin_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 19.320 30.940 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 19.320 30.940 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 19.320 30.895 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 19.320 26.565 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 19.365 26.520 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 20.003 26.520 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.436188e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001921023 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001921023 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.979005e-05 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.979005e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001183745 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001183745 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005691964 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0004909516 //LENGTH 3.980 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l3_in_0_:X O *L 0 *C 12.135 58.820 +*I mux_bottom_ipin_9\/mux_l4_in_0_:A1 I *L 0.00198 *C 11.500 61.540 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 11.500 61.540 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 11.500 61.495 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 11.500 58.865 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 11.545 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 12.098 58.820 + +*CAP +0 mux_bottom_ipin_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.698174e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001608273 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001608273 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.515768e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.515768e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l3_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0004933036 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002348214 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_9\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006712451 //LENGTH 4.645 LUMPCC 0.0001002476 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_2_:X O *L 0 *C 88.955 61.880 +*I mux_bottom_ipin_13\/mux_l3_in_1_:A1 I *L 0.00198 *C 86.940 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 86.978 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 88.275 63.580 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 88.320 63.535 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 88.320 61.925 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 88.365 61.880 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 88.918 61.880 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001297053 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001297053 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.301214e-05 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.301214e-05 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.178126e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.178126e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 prog_clk[0]:220 5.012382e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 prog_clk[0]:223 5.012382e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_2_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001158482 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007055158 //LENGTH 5.030 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l1_in_0_:X O *L 0 *C 81.135 26.520 +*I mux_bottom_ipin_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 81.325 30.940 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 81.325 30.940 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 81.420 30.895 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 81.420 26.565 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 81.420 26.520 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 81.135 26.520 + +*CAP +0 mux_bottom_ipin_6\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.950158e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002838519 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002838519 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.390611e-05 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.240439e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l1_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_6\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009964992 //LENGTH 8.025 LUMPCC 0.0001244664 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_0_:X O *L 0 *C 11.325 23.460 +*I mux_bottom_ipin_10\/mux_l3_in_0_:A1 I *L 0.00198 *C 12.980 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 12.943 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 12.005 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 11.960 18.065 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 11.960 23.415 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 11.915 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 11.363 23.460 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.035838e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.035838e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000325555 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000325555 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.9103e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.9103e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_right_in[8]:8 4.938118e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[8]:7 4.938118e-05 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[8]:10 3.145451e-06 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[8]:11 9.706577e-06 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[8]:6 9.706577e-06 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[8]:11 3.145451e-06 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008370536 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007377889 //LENGTH 5.185 LUMPCC 0.0001337046 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l3_in_1_:X O *L 0 *C 84.815 45.220 +*I mux_bottom_ipin_14\/mux_l4_in_0_:A0 I *L 0.001631 *C 83.090 47.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 83.127 47.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 84.595 47.940 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 84.640 47.895 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 84.640 45.265 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 84.640 45.220 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 84.815 45.220 + +*CAP +0 mux_bottom_ipin_14\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001075778 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001075778 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001331128 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001331128 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.144136e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.926166e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.617903e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.617903e-05 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.067324e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.067324e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l3_in_1_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_14\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001310268 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_164 0.00172004 //LENGTH 13.425 LUMPCC 0.0005544126 DR + +*CONN +*I FTB_11__10:X O *L 0 *C 100.280 30.600 +*I ropt_mt_inst_765:A I *L 0.001766 *C 97.825 39.440 +*N ropt_net_164:2 *C 97.863 39.440 +*N ropt_net_164:3 *C 99.315 39.440 +*N ropt_net_164:4 *C 99.360 39.395 +*N ropt_net_164:5 *C 99.360 32.005 +*N ropt_net_164:6 *C 99.315 31.960 +*N ropt_net_164:7 *C 98.900 31.960 +*N ropt_net_164:8 *C 98.900 30.600 +*N ropt_net_164:9 *C 100.243 30.600 + +*CAP +0 FTB_11__10:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_164:2 0.0001209802 +3 ropt_net_164:3 0.0001209802 +4 ropt_net_164:4 0.0002434917 +5 ropt_net_164:5 0.0002434917 +6 ropt_net_164:6 4.364954e-05 +7 ropt_net_164:7 0.0001240273 +8 ropt_net_164:8 0.0001736921 +9 ropt_net_164:9 9.331435e-05 +10 ropt_net_164:4 chanx_right_in[10]:10 0.0002060586 +11 ropt_net_164:5 chanx_right_in[10]:30 0.0002060586 +12 ropt_net_164:4 ropt_net_154:5 7.114775e-05 +13 ropt_net_164:5 ropt_net_154:4 7.114775e-05 + +*RES +0 FTB_11__10:X ropt_net_164:9 0.152 +1 ropt_net_164:2 ropt_mt_inst_765:A 0.152 +2 ropt_net_164:3 ropt_net_164:2 0.001296875 +3 ropt_net_164:4 ropt_net_164:3 0.0045 +4 ropt_net_164:6 ropt_net_164:5 0.0045 +5 ropt_net_164:5 ropt_net_164:4 0.006598215 +6 ropt_net_164:9 ropt_net_164:8 0.001198661 +7 ropt_net_164:8 ropt_net_164:7 0.001214286 +8 ropt_net_164:7 ropt_net_164:6 0.0003705357 + +*END + +*D_NET ropt_net_163 0.001385797 //LENGTH 9.940 LUMPCC 0.0003457734 DR + +*CONN +*I FTB_36__35:X O *L 0 *C 7.820 30.940 +*I ropt_mt_inst_764:A I *L 0.001766 *C 3.220 34.000 +*N ropt_net_163:2 *C 3.258 34.000 +*N ropt_net_163:3 *C 4.555 34.000 +*N ropt_net_163:4 *C 4.600 33.955 +*N ropt_net_163:5 *C 4.600 30.645 +*N ropt_net_163:6 *C 4.600 30.600 +*N ropt_net_163:7 *C 6.440 30.600 +*N ropt_net_163:8 *C 6.440 30.940 +*N ropt_net_163:9 *C 7.783 30.940 + +*CAP +0 FTB_36__35:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_163:2 2.00447e-05 +3 ropt_net_163:3 2.00447e-05 +4 ropt_net_163:4 0.0002020047 +5 ropt_net_163:5 0.0002020047 +6 ropt_net_163:6 0.0002009854 +7 ropt_net_163:7 0.0001965224 +8 ropt_net_163:8 0.0001114399 +9 ropt_net_163:9 8.497725e-05 +10 ropt_net_163:2 chanx_right_in[9]:11 6.087399e-05 +11 ropt_net_163:3 chanx_right_in[9]:12 6.087399e-05 +12 ropt_net_163:4 mux_tree_tapbuf_size10_4_sram[1]:19 6.349828e-06 +13 ropt_net_163:5 mux_tree_tapbuf_size10_4_sram[1]:20 6.349828e-06 +14 ropt_net_163:9 mux_tree_tapbuf_size10_4_sram[1]:22 4.478891e-05 +15 ropt_net_163:8 mux_tree_tapbuf_size10_4_sram[1]:21 4.478891e-05 +16 ropt_net_163:2 ropt_net_178:6 6.087399e-05 +17 ropt_net_163:3 ropt_net_178:7 6.087399e-05 + +*RES +0 FTB_36__35:X ropt_net_163:9 0.152 +1 ropt_net_163:2 ropt_mt_inst_764:A 0.152 +2 ropt_net_163:3 ropt_net_163:2 0.001158482 +3 ropt_net_163:4 ropt_net_163:3 0.0045 +4 ropt_net_163:6 ropt_net_163:5 0.0045 +5 ropt_net_163:5 ropt_net_163:4 0.002955357 +6 ropt_net_163:9 ropt_net_163:8 0.001198661 +7 ropt_net_163:7 ropt_net_163:6 0.001642857 +8 ropt_net_163:8 ropt_net_163:7 0.0003035715 + +*END + +*D_NET chanx_right_out[18] 0.0003465707 //LENGTH 3.300 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 101.855 72.760 +*P chanx_right_out[18] O *L 0.7423 *C 102.580 74.870 +*N chanx_right_out[18]:2 *C 102.580 72.805 +*N chanx_right_out[18]:3 *C 102.535 72.760 +*N chanx_right_out[18]:4 *C 101.892 72.760 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 chanx_right_out[18] 0.0001105048 +2 chanx_right_out[18]:2 0.0001105048 +3 chanx_right_out[18]:3 6.228057e-05 +4 chanx_right_out[18]:4 6.228057e-05 + +*RES +0 ropt_mt_inst_759:X chanx_right_out[18]:4 0.152 +1 chanx_right_out[18]:4 chanx_right_out[18]:3 0.0005736608 +2 chanx_right_out[18]:3 chanx_right_out[18]:2 0.0045 +3 chanx_right_out[18]:2 chanx_right_out[18] 0.00184375 + +*END + +*D_NET chanx_right_out[2] 0.001012037 //LENGTH 9.350 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 94.300 3.400 +*P chanx_right_out[2] O *L 0.7423 *C 100.740 1.290 +*N chanx_right_out[2]:2 *C 100.740 1.655 +*N chanx_right_out[2]:3 *C 100.695 1.700 +*N chanx_right_out[2]:4 *C 94.345 1.700 +*N chanx_right_out[2]:5 *C 94.300 1.745 +*N chanx_right_out[2]:6 *C 94.300 3.355 +*N chanx_right_out[2]:7 *C 94.300 3.400 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 chanx_right_out[2] 4.10331e-05 +2 chanx_right_out[2]:2 4.10331e-05 +3 chanx_right_out[2]:3 0.0003534507 +4 chanx_right_out[2]:4 0.0003534507 +5 chanx_right_out[2]:5 9.684849e-05 +6 chanx_right_out[2]:6 9.684849e-05 +7 chanx_right_out[2]:7 2.837231e-05 + +*RES +0 ropt_mt_inst_791:X chanx_right_out[2]:7 0.152 +1 chanx_right_out[2]:7 chanx_right_out[2]:6 0.0045 +2 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0014375 +3 chanx_right_out[2]:4 chanx_right_out[2]:3 0.005669643 +4 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0045 +5 chanx_right_out[2]:3 chanx_right_out[2]:2 0.0045 +6 chanx_right_out[2]:2 chanx_right_out[2] 0.0003258928 + +*END + +*D_NET chanx_left_out[9] 0.00205174 //LENGTH 12.980 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 11.695 25.500 +*P chanx_left_out[9] O *L 0.7423 *C 1.230 23.800 +*N chanx_left_out[9]:2 *C 11.033 23.800 +*N chanx_left_out[9]:3 *C 11.040 23.858 +*N chanx_left_out[9]:4 *C 11.040 25.455 +*N chanx_left_out[9]:5 *C 11.085 25.500 +*N chanx_left_out[9]:6 *C 11.658 25.500 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 chanx_left_out[9] 0.0008129756 +2 chanx_left_out[9]:2 0.0008129756 +3 chanx_left_out[9]:3 0.0001354796 +4 chanx_left_out[9]:4 0.0001354796 +5 chanx_left_out[9]:5 7.691477e-05 +6 chanx_left_out[9]:6 7.691477e-05 + +*RES +0 ropt_mt_inst_801:X chanx_left_out[9]:6 0.152 +1 chanx_left_out[9]:6 chanx_left_out[9]:5 0.0005111608 +2 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +3 chanx_left_out[9]:4 chanx_left_out[9]:3 0.001426339 +4 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +5 chanx_left_out[9]:2 chanx_left_out[9] 0.001535725 + +*END + +*D_NET chanx_left_in[6] 0.01726707 //LENGTH 119.595 LUMPCC 0.004006993 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 31.280 +*I mux_bottom_ipin_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 40.770 22.440 +*I mux_bottom_ipin_12\/mux_l1_in_2_:A1 I *L 0.00198 *C 71.860 18.020 +*I BUFT_RR_61:A I *L 0.001776 *C 90.160 9.520 +*I mux_bottom_ipin_10\/mux_l2_in_1_:A0 I *L 0.001631 *C 18.230 21.080 +*N chanx_left_in[6]:5 *C 18.230 21.080 +*N chanx_left_in[6]:6 *C 90.160 9.520 +*N chanx_left_in[6]:7 *C 90.160 9.565 +*N chanx_left_in[6]:8 *C 90.160 14.223 +*N chanx_left_in[6]:9 *C 90.153 14.280 +*N chanx_left_in[6]:10 *C 71.767 14.280 +*N chanx_left_in[6]:11 *C 71.760 14.338 +*N chanx_left_in[6]:12 *C 71.860 18.020 +*N chanx_left_in[6]:13 *C 71.760 18.360 +*N chanx_left_in[6]:14 *C 71.760 18.360 +*N chanx_left_in[6]:15 *C 71.752 18.360 +*N chanx_left_in[6]:16 *C 40.733 22.440 +*N chanx_left_in[6]:17 *C 40.065 22.440 +*N chanx_left_in[6]:18 *C 40.020 22.395 +*N chanx_left_in[6]:19 *C 40.020 18.418 +*N chanx_left_in[6]:20 *C 40.020 18.360 +*N chanx_left_in[6]:21 *C 17.948 18.360 +*N chanx_left_in[6]:22 *C 17.940 18.418 +*N chanx_left_in[6]:23 *C 17.940 21.035 +*N chanx_left_in[6]:24 *C 17.895 21.080 +*N chanx_left_in[6]:25 *C 5.565 21.080 +*N chanx_left_in[6]:26 *C 5.520 21.125 +*N chanx_left_in[6]:27 *C 5.520 31.223 +*N chanx_left_in[6]:28 *C 5.513 31.280 + +*CAP +0 chanx_left_in[6] 0.0003943676 +1 mux_bottom_ipin_2\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_12\/mux_l1_in_2_:A1 1e-06 +3 BUFT_RR_61:A 1e-06 +4 mux_bottom_ipin_10\/mux_l2_in_1_:A0 1e-06 +5 chanx_left_in[6]:5 5.063416e-05 +6 chanx_left_in[6]:6 3.619103e-05 +7 chanx_left_in[6]:7 0.000258575 +8 chanx_left_in[6]:8 0.000258575 +9 chanx_left_in[6]:9 0.001376191 +10 chanx_left_in[6]:10 0.001376191 +11 chanx_left_in[6]:11 0.0002412005 +12 chanx_left_in[6]:12 6.060704e-05 +13 chanx_left_in[6]:13 6.496365e-05 +14 chanx_left_in[6]:14 0.0002778605 +15 chanx_left_in[6]:15 0.001426569 +16 chanx_left_in[6]:16 7.705788e-05 +17 chanx_left_in[6]:17 7.705788e-05 +18 chanx_left_in[6]:18 0.0002800656 +19 chanx_left_in[6]:19 0.0002800656 +20 chanx_left_in[6]:20 0.002177342 +21 chanx_left_in[6]:21 0.0007507727 +22 chanx_left_in[6]:22 0.0001988911 +23 chanx_left_in[6]:23 0.0001988911 +24 chanx_left_in[6]:24 0.0009304816 +25 chanx_left_in[6]:25 0.0009094079 +26 chanx_left_in[6]:26 0.0005798726 +27 chanx_left_in[6]:27 0.0005798726 +28 chanx_left_in[6]:28 0.0003943676 +29 chanx_left_in[6]:20 chanx_right_in[8]:27 1.632172e-06 +30 chanx_left_in[6]:20 chanx_right_in[8]:23 0.0004505846 +31 chanx_left_in[6]:20 chanx_right_in[8]:17 0.000422525 +32 chanx_left_in[6]:20 chanx_right_in[8]:18 0.0005308196 +33 chanx_left_in[6]:15 chanx_right_in[8]:24 0.0004505846 +34 chanx_left_in[6]:15 chanx_right_in[8]:18 0.000422525 +35 chanx_left_in[6]:15 chanx_right_in[8]:28 1.632172e-06 +36 chanx_left_in[6]:21 chanx_right_in[8]:17 0.0005308196 +37 chanx_left_in[6]:20 chanx_right_in[14]:28 0.0005312938 +38 chanx_left_in[6]:20 chanx_right_in[14]:21 6.664135e-05 +39 chanx_left_in[6]:15 chanx_right_in[14]:29 0.0002451116 +40 chanx_left_in[6]:15 chanx_right_in[14]:28 6.664135e-05 +41 chanx_left_in[6]:21 chanx_right_in[14]:21 0.0002861822 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:28 0.000670925 +1 chanx_left_in[6]:11 chanx_left_in[6]:10 0.00341 +2 chanx_left_in[6]:10 chanx_left_in[6]:9 0.002880316 +3 chanx_left_in[6]:8 chanx_left_in[6]:7 0.004158482 +4 chanx_left_in[6]:9 chanx_left_in[6]:8 0.00341 +5 chanx_left_in[6]:6 BUFT_RR_61:A 0.152 +6 chanx_left_in[6]:7 chanx_left_in[6]:6 0.0045 +7 chanx_left_in[6]:25 chanx_left_in[6]:24 0.01100893 +8 chanx_left_in[6]:26 chanx_left_in[6]:25 0.0045 +9 chanx_left_in[6]:27 chanx_left_in[6]:26 0.009015625 +10 chanx_left_in[6]:28 chanx_left_in[6]:27 0.00341 +11 chanx_left_in[6]:19 chanx_left_in[6]:18 0.003551339 +12 chanx_left_in[6]:20 chanx_left_in[6]:19 0.00341 +13 chanx_left_in[6]:20 chanx_left_in[6]:15 0.004971425 +14 chanx_left_in[6]:17 chanx_left_in[6]:16 0.0005959822 +15 chanx_left_in[6]:18 chanx_left_in[6]:17 0.0045 +16 chanx_left_in[6]:16 mux_bottom_ipin_2\/mux_l2_in_1_:A0 0.152 +17 chanx_left_in[6]:5 mux_bottom_ipin_10\/mux_l2_in_1_:A0 0.152 +18 chanx_left_in[6]:13 chanx_left_in[6]:12 0.0001847826 +19 chanx_left_in[6]:14 chanx_left_in[6]:13 0.0045 +20 chanx_left_in[6]:14 chanx_left_in[6]:11 0.003591518 +21 chanx_left_in[6]:12 mux_bottom_ipin_12\/mux_l1_in_2_:A1 0.152 +22 chanx_left_in[6]:15 chanx_left_in[6]:14 0.00341 +23 chanx_left_in[6]:24 chanx_left_in[6]:23 0.0045 +24 chanx_left_in[6]:24 chanx_left_in[6]:5 0.0001684783 +25 chanx_left_in[6]:23 chanx_left_in[6]:22 0.002337054 +26 chanx_left_in[6]:22 chanx_left_in[6]:21 0.00341 +27 chanx_left_in[6]:21 chanx_left_in[6]:20 0.003458025 + +*END + +*D_NET chanx_right_in[5] 0.02141857 //LENGTH 155.350 LUMPCC 0.006206242 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 103.650 20.400 +*I mux_bottom_ipin_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 59.170 48.280 +*I mux_bottom_ipin_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 62.390 49.980 +*I ropt_mt_inst_737:A I *L 0.001767 *C 6.440 69.360 +*N chanx_right_in[5]:4 *C 6.478 69.360 +*N chanx_right_in[5]:5 *C 7.820 69.360 +*N chanx_right_in[5]:6 *C 7.820 68.680 +*N chanx_right_in[5]:7 *C 23.875 68.680 +*N chanx_right_in[5]:8 *C 23.920 68.635 +*N chanx_right_in[5]:9 *C 23.920 68.058 +*N chanx_right_in[5]:10 *C 23.928 68.000 +*N chanx_right_in[5]:11 *C 43.233 68.000 +*N chanx_right_in[5]:12 *C 43.240 67.943 +*N chanx_right_in[5]:13 *C 43.240 49.698 +*N chanx_right_in[5]:14 *C 43.248 49.640 +*N chanx_right_in[5]:15 *C 58.413 49.640 +*N chanx_right_in[5]:16 *C 58.420 49.698 +*N chanx_right_in[5]:17 *C 58.420 50.275 +*N chanx_right_in[5]:18 *C 58.465 50.320 +*N chanx_right_in[5]:19 *C 61.180 50.320 +*N chanx_right_in[5]:20 *C 61.180 49.980 +*N chanx_right_in[5]:21 *C 62.353 49.980 +*N chanx_right_in[5]:22 *C 62.430 49.980 +*N chanx_right_in[5]:23 *C 62.560 49.935 +*N chanx_right_in[5]:24 *C 59.208 48.280 +*N chanx_right_in[5]:25 *C 62.515 48.280 +*N chanx_right_in[5]:26 *C 62.560 48.280 +*N chanx_right_in[5]:27 *C 62.560 33.378 +*N chanx_right_in[5]:28 *C 62.568 33.320 +*N chanx_right_in[5]:29 *C 100.260 33.320 +*N chanx_right_in[5]:30 *C 100.280 33.312 +*N chanx_right_in[5]:31 *C 100.280 20.408 +*N chanx_right_in[5]:32 *C 100.300 20.400 + +*CAP +0 chanx_right_in[5] 0.0002701085 +1 mux_bottom_ipin_5\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_737:A 1e-06 +4 chanx_right_in[5]:4 8.748894e-05 +5 chanx_right_in[5]:5 0.0001307417 +6 chanx_right_in[5]:6 0.001142766 +7 chanx_right_in[5]:7 0.001099513 +8 chanx_right_in[5]:8 5.357684e-05 +9 chanx_right_in[5]:9 5.357684e-05 +10 chanx_right_in[5]:10 0.0008802299 +11 chanx_right_in[5]:11 0.0008802299 +12 chanx_right_in[5]:12 0.00105839 +13 chanx_right_in[5]:13 0.00105839 +14 chanx_right_in[5]:14 0.0006552893 +15 chanx_right_in[5]:15 0.0006552893 +16 chanx_right_in[5]:16 6.101716e-05 +17 chanx_right_in[5]:17 6.101716e-05 +18 chanx_right_in[5]:18 0.0001996368 +19 chanx_right_in[5]:19 0.0002252941 +20 chanx_right_in[5]:20 8.338785e-05 +21 chanx_right_in[5]:21 7.534331e-05 +22 chanx_right_in[5]:22 1.761279e-05 +23 chanx_right_in[5]:23 7.29649e-05 +24 chanx_right_in[5]:24 0.0002294157 +25 chanx_right_in[5]:25 0.0002294157 +26 chanx_right_in[5]:26 0.0008943297 +27 chanx_right_in[5]:27 0.0007852387 +28 chanx_right_in[5]:28 0.001284139 +29 chanx_right_in[5]:29 0.001284139 +30 chanx_right_in[5]:30 0.0007053407 +31 chanx_right_in[5]:31 0.0007053407 +32 chanx_right_in[5]:32 0.0002701085 +33 chanx_right_in[5]:15 chanx_left_in[5]:22 0.0001206237 +34 chanx_right_in[5]:15 chanx_left_in[5]:23 0.0002062798 +35 chanx_right_in[5]:14 chanx_left_in[5]:23 0.0001206237 +36 chanx_right_in[5]:14 chanx_left_in[5]:24 0.0002062798 +37 chanx_right_in[5]:22 chanx_left_in[5]:13 1.601364e-06 +38 chanx_right_in[5]:23 chanx_left_in[5]:14 4.172022e-05 +39 chanx_right_in[5]:25 chanx_left_in[5]:18 3.706307e-06 +40 chanx_right_in[5]:26 chanx_left_in[5]:14 4.166907e-06 +41 chanx_right_in[5]:26 chanx_left_in[5]:15 4.172022e-05 +42 chanx_right_in[5]:24 chanx_left_in[5]:17 3.706307e-06 +43 chanx_right_in[5]:21 chanx_left_in[5]:12 1.601364e-06 +44 chanx_right_in[5]:21 chanx_left_in[5]:13 2.146045e-06 +45 chanx_right_in[5]:27 chanx_left_in[5]:15 4.166907e-06 +46 chanx_right_in[5]:20 chanx_left_in[5]:12 2.146045e-06 +47 chanx_right_in[5]:28 chanx_left_in[7]:15 0.0001205574 +48 chanx_right_in[5]:28 chanx_left_in[7]:16 0.0003245918 +49 chanx_right_in[5]:29 chanx_left_in[7]:14 0.0001205574 +50 chanx_right_in[5]:29 chanx_left_in[7]:15 0.0003245918 +51 chanx_right_in[5]:28 chanx_left_in[18]:30 0.0006139305 +52 chanx_right_in[5]:29 chanx_left_in[18]:29 0.0006139305 +53 chanx_right_in[5]:28 chanx_right_in[0]:53 0.0003291215 +54 chanx_right_in[5]:29 chanx_right_in[0] 0.0003291215 +55 chanx_right_in[5]:15 chanx_right_in[4]:25 0.0003704122 +56 chanx_right_in[5]:14 chanx_right_in[4]:24 0.0003704122 +57 chanx_right_in[5]:28 chanx_right_in[4]:38 2.964545e-05 +58 chanx_right_in[5]:29 chanx_right_in[4]:39 2.964545e-05 +59 chanx_right_in[5]:26 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 4.791893e-05 +60 chanx_right_in[5]:27 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 4.791893e-05 +61 chanx_right_in[5]:28 mux_tree_tapbuf_size8_2_sram[0]:11 0.0004667402 +62 chanx_right_in[5]:29 mux_tree_tapbuf_size8_2_sram[0]:10 0.0004667402 +63 chanx_right_in[5]:18 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 2.605757e-05 +64 chanx_right_in[5]:22 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 1.334963e-05 +65 chanx_right_in[5]:21 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 4.513445e-05 +66 chanx_right_in[5]:21 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 1.334963e-05 +67 chanx_right_in[5]:19 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:9 2.605757e-05 +68 chanx_right_in[5]:20 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 4.513445e-05 +69 chanx_right_in[5]:13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 8.240985e-05 +70 chanx_right_in[5]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 8.240985e-05 +71 chanx_right_in[5]:11 mem_bottom_ipin_15/net_net_75:7 0.0002530075 +72 chanx_right_in[5]:10 mem_bottom_ipin_15/net_net_75:6 0.0002530075 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:32 0.0005248333 +1 chanx_right_in[5]:18 chanx_right_in[5]:17 0.0045 +2 chanx_right_in[5]:17 chanx_right_in[5]:16 0.000515625 +3 chanx_right_in[5]:16 chanx_right_in[5]:15 0.00341 +4 chanx_right_in[5]:15 chanx_right_in[5]:14 0.00237585 +5 chanx_right_in[5]:13 chanx_right_in[5]:12 0.01629018 +6 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00341 +7 chanx_right_in[5]:12 chanx_right_in[5]:11 0.00341 +8 chanx_right_in[5]:11 chanx_right_in[5]:10 0.00302445 +9 chanx_right_in[5]:9 chanx_right_in[5]:8 0.000515625 +10 chanx_right_in[5]:10 chanx_right_in[5]:9 0.00341 +11 chanx_right_in[5]:7 chanx_right_in[5]:6 0.01433482 +12 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0045 +13 chanx_right_in[5]:4 ropt_mt_inst_737:A 0.152 +14 chanx_right_in[5]:22 chanx_right_in[5]:21 6.919643e-05 +15 chanx_right_in[5]:23 chanx_right_in[5]:22 0.0045 +16 chanx_right_in[5]:25 chanx_right_in[5]:24 0.002953125 +17 chanx_right_in[5]:26 chanx_right_in[5]:25 0.0045 +18 chanx_right_in[5]:26 chanx_right_in[5]:23 0.001477679 +19 chanx_right_in[5]:24 mux_bottom_ipin_5\/mux_l1_in_2_:A0 0.152 +20 chanx_right_in[5]:21 mux_bottom_ipin_1\/mux_l1_in_2_:A0 0.152 +21 chanx_right_in[5]:21 chanx_right_in[5]:20 0.001046875 +22 chanx_right_in[5]:27 chanx_right_in[5]:26 0.01330581 +23 chanx_right_in[5]:28 chanx_right_in[5]:27 0.00341 +24 chanx_right_in[5]:29 chanx_right_in[5]:28 0.005905158 +25 chanx_right_in[5]:30 chanx_right_in[5]:29 0.00341 +26 chanx_right_in[5]:32 chanx_right_in[5]:31 0.00341 +27 chanx_right_in[5]:31 chanx_right_in[5]:30 0.002021783 +28 chanx_right_in[5]:5 chanx_right_in[5]:4 0.001198661 +29 chanx_right_in[5]:6 chanx_right_in[5]:5 0.000607143 +30 chanx_right_in[5]:19 chanx_right_in[5]:18 0.002424107 +31 chanx_right_in[5]:20 chanx_right_in[5]:19 0.0003035715 + +*END + +*D_NET chanx_right_in[10] 0.01758087 //LENGTH 136.570 LUMPCC 0.004333912 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 103.650 25.840 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 66.145 18.020 +*I BUFT_RR_70:A I *L 0.001766 *C 19.320 9.520 +*I mux_bottom_ipin_6\/mux_l2_in_2_:A1 I *L 0.00198 *C 95.680 41.820 +*I mux_bottom_ipin_14\/mux_l2_in_2_:A1 I *L 0.00198 *C 91.080 45.220 +*N chanx_right_in[10]:5 *C 91.118 45.220 +*N chanx_right_in[10]:6 *C 99.775 45.220 +*N chanx_right_in[10]:7 *C 99.820 45.175 +*N chanx_right_in[10]:8 *C 95.718 41.820 +*N chanx_right_in[10]:9 *C 99.775 41.820 +*N chanx_right_in[10]:10 *C 99.820 41.820 +*N chanx_right_in[10]:11 *C 19.358 9.520 +*N chanx_right_in[10]:12 *C 20.195 9.520 +*N chanx_right_in[10]:13 *C 20.240 9.565 +*N chanx_right_in[10]:14 *C 20.240 12.195 +*N chanx_right_in[10]:15 *C 20.285 12.240 +*N chanx_right_in[10]:16 *C 35.880 12.240 +*N chanx_right_in[10]:17 *C 35.880 12.580 +*N chanx_right_in[10]:18 *C 58.375 12.580 +*N chanx_right_in[10]:19 *C 58.420 12.625 +*N chanx_right_in[10]:20 *C 58.420 14.235 +*N chanx_right_in[10]:21 *C 58.465 14.280 +*N chanx_right_in[10]:22 *C 66.195 14.280 +*N chanx_right_in[10]:23 *C 66.240 14.325 +*N chanx_right_in[10]:24 *C 66.145 18.020 +*N chanx_right_in[10]:25 *C 66.240 18.020 +*N chanx_right_in[10]:26 *C 66.240 21.023 +*N chanx_right_in[10]:27 *C 66.248 21.080 +*N chanx_right_in[10]:28 *C 99.812 21.080 +*N chanx_right_in[10]:29 *C 99.820 21.137 +*N chanx_right_in[10]:30 *C 99.820 25.840 +*N chanx_right_in[10]:31 *C 99.828 25.840 + +*CAP +0 chanx_right_in[10] 0.000321071 +1 mux_bottom_ipin_0\/mux_l2_in_2_:A1 1e-06 +2 BUFT_RR_70:A 1e-06 +3 mux_bottom_ipin_6\/mux_l2_in_2_:A1 1e-06 +4 mux_bottom_ipin_14\/mux_l2_in_2_:A1 1e-06 +5 chanx_right_in[10]:5 0.000469347 +6 chanx_right_in[10]:6 0.000469347 +7 chanx_right_in[10]:7 0.0001625892 +8 chanx_right_in[10]:8 0.0003170031 +9 chanx_right_in[10]:9 0.0003170031 +10 chanx_right_in[10]:10 0.0009126943 +11 chanx_right_in[10]:11 8.645422e-05 +12 chanx_right_in[10]:12 8.645422e-05 +13 chanx_right_in[10]:13 0.0001437225 +14 chanx_right_in[10]:14 0.0001437225 +15 chanx_right_in[10]:15 0.0007644889 +16 chanx_right_in[10]:16 0.0007865616 +17 chanx_right_in[10]:17 0.001172232 +18 chanx_right_in[10]:18 0.001150159 +19 chanx_right_in[10]:19 0.0001072612 +20 chanx_right_in[10]:20 0.0001072612 +21 chanx_right_in[10]:21 0.0005211474 +22 chanx_right_in[10]:22 0.0005211474 +23 chanx_right_in[10]:23 0.000234827 +24 chanx_right_in[10]:24 2.730879e-05 +25 chanx_right_in[10]:25 0.00045924 +26 chanx_right_in[10]:26 0.000191717 +27 chanx_right_in[10]:27 0.001120574 +28 chanx_right_in[10]:28 0.001120574 +29 chanx_right_in[10]:29 0.0002296721 +30 chanx_right_in[10]:30 0.0009783059 +31 chanx_right_in[10]:31 0.000321071 +32 chanx_right_in[10] chanx_right_in[6] 1.635541e-05 +33 chanx_right_in[10]:27 chanx_right_in[6]:36 0.0005449019 +34 chanx_right_in[10]:28 chanx_right_in[6]:37 0.0005449019 +35 chanx_right_in[10]:31 chanx_right_in[6]:40 1.635541e-05 +36 chanx_right_in[10] chanx_right_in[8] 1.485175e-06 +37 chanx_right_in[10]:27 chanx_right_in[8]:27 0.0003270043 +38 chanx_right_in[10]:27 chanx_right_in[8]:29 0.0003721233 +39 chanx_right_in[10]:27 chanx_right_in[8]:31 0.0004630147 +40 chanx_right_in[10]:28 chanx_right_in[8] 0.0004630147 +41 chanx_right_in[10]:28 chanx_right_in[8]:28 0.0003270043 +42 chanx_right_in[10]:28 chanx_right_in[8]:30 0.0003721233 +43 chanx_right_in[10]:31 chanx_right_in[8]:31 1.485175e-06 +44 chanx_right_in[10]:10 ropt_net_164:4 0.0002060586 +45 chanx_right_in[10]:30 ropt_net_164:5 0.0002060586 +46 chanx_right_in[10]:6 ropt_net_156:6 0.0001620976 +47 chanx_right_in[10]:5 ropt_net_156:7 0.0001620976 +48 chanx_right_in[10]:10 ropt_net_160:5 2.91085e-05 +49 chanx_right_in[10]:6 ropt_net_160:3 4.480654e-05 +50 chanx_right_in[10]:7 ropt_net_160:4 2.91085e-05 +51 chanx_right_in[10]:5 ropt_net_160:2 4.480654e-05 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:31 0.0005988584 +1 chanx_right_in[10]:22 chanx_right_in[10]:21 0.006901786 +2 chanx_right_in[10]:23 chanx_right_in[10]:22 0.0045 +3 chanx_right_in[10]:21 chanx_right_in[10]:20 0.0045 +4 chanx_right_in[10]:20 chanx_right_in[10]:19 0.0014375 +5 chanx_right_in[10]:18 chanx_right_in[10]:17 0.02008482 +6 chanx_right_in[10]:19 chanx_right_in[10]:18 0.0045 +7 chanx_right_in[10]:15 chanx_right_in[10]:14 0.0045 +8 chanx_right_in[10]:14 chanx_right_in[10]:13 0.002348214 +9 chanx_right_in[10]:12 chanx_right_in[10]:11 0.0007477679 +10 chanx_right_in[10]:13 chanx_right_in[10]:12 0.0045 +11 chanx_right_in[10]:11 BUFT_RR_70:A 0.152 +12 chanx_right_in[10]:26 chanx_right_in[10]:25 0.002680804 +13 chanx_right_in[10]:27 chanx_right_in[10]:26 0.00341 +14 chanx_right_in[10]:29 chanx_right_in[10]:28 0.00341 +15 chanx_right_in[10]:28 chanx_right_in[10]:27 0.005258516 +16 chanx_right_in[10]:9 chanx_right_in[10]:8 0.003622768 +17 chanx_right_in[10]:10 chanx_right_in[10]:9 0.0045 +18 chanx_right_in[10]:10 chanx_right_in[10]:7 0.002995536 +19 chanx_right_in[10]:8 mux_bottom_ipin_6\/mux_l2_in_2_:A1 0.152 +20 chanx_right_in[10]:6 chanx_right_in[10]:5 0.007729911 +21 chanx_right_in[10]:7 chanx_right_in[10]:6 0.0045 +22 chanx_right_in[10]:5 mux_bottom_ipin_14\/mux_l2_in_2_:A1 0.152 +23 chanx_right_in[10]:24 mux_bottom_ipin_0\/mux_l2_in_2_:A1 0.152 +24 chanx_right_in[10]:25 chanx_right_in[10]:24 0.0045 +25 chanx_right_in[10]:25 chanx_right_in[10]:23 0.003299107 +26 chanx_right_in[10]:30 chanx_right_in[10]:29 0.004198661 +27 chanx_right_in[10]:30 chanx_right_in[10]:10 0.01426786 +28 chanx_right_in[10]:31 chanx_right_in[10]:30 0.00341 +29 chanx_right_in[10]:16 chanx_right_in[10]:15 0.01392411 +30 chanx_right_in[10]:17 chanx_right_in[10]:16 0.0003035715 + +*END + +*D_NET chanx_right_in[17] 0.02161097 //LENGTH 148.035 LUMPCC 0.006801511 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 103.575 61.200 +*I mux_bottom_ipin_13\/mux_l2_in_3_:A1 I *L 0.00198 *C 92.460 58.140 +*I BUFT_P_119:A I *L 0.001776 *C 14.720 9.520 +*I mux_bottom_ipin_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 51.060 56.100 +*N chanx_right_in[17]:4 *C 51.060 56.100 +*N chanx_right_in[17]:5 *C 51.060 56.145 +*N chanx_right_in[17]:6 *C 46.210 10.880 +*N chanx_right_in[17]:7 *C 14.758 9.520 +*N chanx_right_in[17]:8 *C 18.860 9.520 +*N chanx_right_in[17]:9 *C 18.860 8.840 +*N chanx_right_in[17]:10 *C 46.875 8.840 +*N chanx_right_in[17]:11 *C 46.920 8.885 +*N chanx_right_in[17]:12 *C 46.920 10.822 +*N chanx_right_in[17]:13 *C 46.918 10.880 +*N chanx_right_in[17]:14 *C 46.920 10.888 +*N chanx_right_in[17]:15 *C 46.920 57.113 +*N chanx_right_in[17]:16 *C 46.940 57.120 +*N chanx_right_in[17]:17 *C 51.053 57.120 +*N chanx_right_in[17]:18 *C 51.060 57.120 +*N chanx_right_in[17]:19 *C 51.060 59.103 +*N chanx_right_in[17]:20 *C 51.068 59.160 +*N chanx_right_in[17]:21 *C 92.460 58.140 +*N chanx_right_in[17]:22 *C 92.460 58.185 +*N chanx_right_in[17]:23 *C 92.460 59.103 +*N chanx_right_in[17]:24 *C 92.460 59.160 +*N chanx_right_in[17]:25 *C 96.140 59.160 +*N chanx_right_in[17]:26 *C 96.140 61.200 + +*CAP +0 chanx_right_in[17] 0.0004061966 +1 mux_bottom_ipin_13\/mux_l2_in_3_:A1 1e-06 +2 BUFT_P_119:A 1e-06 +3 mux_bottom_ipin_1\/mux_l2_in_3_:A1 1e-06 +4 chanx_right_in[17]:4 3.299803e-05 +5 chanx_right_in[17]:5 6.627938e-05 +6 chanx_right_in[17]:6 7.267331e-05 +7 chanx_right_in[17]:7 0.0001825243 +8 chanx_right_in[17]:8 0.0002219969 +9 chanx_right_in[17]:9 0.001356607 +10 chanx_right_in[17]:10 0.001317135 +11 chanx_right_in[17]:11 0.0001091211 +12 chanx_right_in[17]:12 0.0001091211 +13 chanx_right_in[17]:13 7.267331e-05 +14 chanx_right_in[17]:14 0.003076567 +15 chanx_right_in[17]:15 0.003076567 +16 chanx_right_in[17]:16 0.0002124851 +17 chanx_right_in[17]:17 0.0002124851 +18 chanx_right_in[17]:18 0.0002296501 +19 chanx_right_in[17]:19 0.000123615 +20 chanx_right_in[17]:20 0.001390876 +21 chanx_right_in[17]:21 3.431394e-05 +22 chanx_right_in[17]:22 7.625932e-05 +23 chanx_right_in[17]:23 7.625932e-05 +24 chanx_right_in[17]:24 0.001556292 +25 chanx_right_in[17]:25 0.0002764919 +26 chanx_right_in[17]:26 0.000517272 +27 chanx_right_in[17] chanx_left_in[13]:8 1.209982e-06 +28 chanx_right_in[17]:22 chanx_left_in[13]:7 3.133344e-07 +29 chanx_right_in[17]:23 chanx_left_in[13]:6 3.133344e-07 +30 chanx_right_in[17]:24 chanx_left_in[13]:8 0.0001214509 +31 chanx_right_in[17]:24 chanx_left_in[13]:13 0.0007220581 +32 chanx_right_in[17]:20 chanx_left_in[13]:13 0.0001214509 +33 chanx_right_in[17]:20 chanx_left_in[13]:14 0.000634324 +34 chanx_right_in[17]:17 chanx_left_in[13]:13 0.0002475504 +35 chanx_right_in[17]:16 chanx_left_in[13]:14 0.0002475504 +36 chanx_right_in[17]:25 chanx_left_in[13]:7 5.482025e-06 +37 chanx_right_in[17]:25 chanx_left_in[13]:8 8.773404e-05 +38 chanx_right_in[17]:26 chanx_left_in[13]:6 5.482025e-06 +39 chanx_right_in[17]:26 chanx_left_in[13]:13 1.209982e-06 +40 chanx_right_in[17]:24 chanx_left_in[19]:16 0.000838614 +41 chanx_right_in[17]:20 chanx_left_in[19]:17 0.000838614 +42 chanx_right_in[17]:24 chanx_right_in[13]:18 0.0002410254 +43 chanx_right_in[17]:24 chanx_right_in[13]:22 4.67519e-05 +44 chanx_right_in[17]:24 chanx_right_in[13]:23 1.58734e-05 +45 chanx_right_in[17]:20 chanx_right_in[13]:17 0.0002410254 +46 chanx_right_in[17]:20 chanx_right_in[13]:18 3.92753e-05 +47 chanx_right_in[17]:20 chanx_right_in[13]:22 1.58734e-05 +48 chanx_right_in[17]:25 chanx_right_in[13]:23 7.476604e-06 +49 chanx_right_in[17]:25 chanx_right_in[13]:24 9.160053e-06 +50 chanx_right_in[17]:26 chanx_right_in[13]:25 9.160053e-06 +51 chanx_right_in[17]:10 chanx_right_in[16]:9 7.913889e-05 +52 chanx_right_in[17]:10 chanx_right_in[16]:10 0.000385582 +53 chanx_right_in[17]:9 chanx_right_in[16]:8 7.913889e-05 +54 chanx_right_in[17]:9 chanx_right_in[16]:9 0.000385582 +55 chanx_right_in[17]:24 prog_clk[0]:252 0.0003742167 +56 chanx_right_in[17]:20 prog_clk[0]:253 0.0003742167 +57 chanx_right_in[17]:13 prog_clk[0]:139 5.810599e-05 +58 chanx_right_in[17]:12 prog_clk[0]:132 3.412849e-06 +59 chanx_right_in[17]:12 prog_clk[0]:137 2.386006e-06 +60 chanx_right_in[17]:11 prog_clk[0]:133 3.412849e-06 +61 chanx_right_in[17]:11 prog_clk[0]:138 2.386006e-06 +62 chanx_right_in[17]:6 prog_clk[0]:134 5.810599e-05 +63 chanx_right_in[17] ropt_net_151:7 7.337549e-05 +64 chanx_right_in[17]:26 ropt_net_151:6 7.337549e-05 +65 chanx_right_in[17]:10 ropt_net_129:10 1.033159e-05 +66 chanx_right_in[17]:7 ropt_net_129:9 0.0001647166 +67 chanx_right_in[17]:8 ropt_net_129:10 0.0001647166 +68 chanx_right_in[17]:9 ropt_net_129:9 1.033159e-05 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:26 0.001164817 +1 chanx_right_in[17]:21 mux_bottom_ipin_13\/mux_l2_in_3_:A1 0.152 +2 chanx_right_in[17]:22 chanx_right_in[17]:21 0.0045 +3 chanx_right_in[17]:23 chanx_right_in[17]:22 0.0008191965 +4 chanx_right_in[17]:24 chanx_right_in[17]:23 0.00341 +5 chanx_right_in[17]:24 chanx_right_in[17]:20 0.006484825 +6 chanx_right_in[17]:19 chanx_right_in[17]:18 0.001770089 +7 chanx_right_in[17]:20 chanx_right_in[17]:19 0.00341 +8 chanx_right_in[17]:4 mux_bottom_ipin_1\/mux_l2_in_3_:A1 0.152 +9 chanx_right_in[17]:5 chanx_right_in[17]:4 0.0045 +10 chanx_right_in[17]:18 chanx_right_in[17]:17 0.00341 +11 chanx_right_in[17]:18 chanx_right_in[17]:5 0.0008705358 +12 chanx_right_in[17]:17 chanx_right_in[17]:16 0.0006442916 +13 chanx_right_in[17]:16 chanx_right_in[17]:15 0.00341 +14 chanx_right_in[17]:15 chanx_right_in[17]:14 0.007241916 +15 chanx_right_in[17]:13 chanx_right_in[17]:12 0.00341 +16 chanx_right_in[17]:13 chanx_right_in[17]:6 0.0001039141 +17 chanx_right_in[17]:14 chanx_right_in[17]:13 0.00341 +18 chanx_right_in[17]:12 chanx_right_in[17]:11 0.001729911 +19 chanx_right_in[17]:10 chanx_right_in[17]:9 0.02501339 +20 chanx_right_in[17]:11 chanx_right_in[17]:10 0.0045 +21 chanx_right_in[17]:7 BUFT_P_119:A 0.152 +22 chanx_right_in[17]:8 chanx_right_in[17]:7 0.003662947 +23 chanx_right_in[17]:9 chanx_right_in[17]:8 0.0006071429 +24 chanx_right_in[17]:25 chanx_right_in[17]:24 0.0005765333 +25 chanx_right_in[17]:26 chanx_right_in[17]:25 0.0003196 + +*END + +*D_NET top_grid_pin_23_[0] 0.00185321 //LENGTH 14.180 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 24.840 71.740 +*P top_grid_pin_23_[0] O *L 0.7423 *C 15.180 74.835 +*N top_grid_pin_23_[0]:2 *C 15.180 71.445 +*N top_grid_pin_23_[0]:3 *C 15.225 71.400 +*N top_grid_pin_23_[0]:4 *C 20.240 71.400 +*N top_grid_pin_23_[0]:5 *C 20.240 71.740 +*N top_grid_pin_23_[0]:6 *C 24.803 71.740 + +*CAP +0 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_23_[0] 0.0002094007 +2 top_grid_pin_23_[0]:2 0.0002094007 +3 top_grid_pin_23_[0]:3 0.0003967681 +4 top_grid_pin_23_[0]:4 0.0004205893 +5 top_grid_pin_23_[0]:5 0.0003199364 +6 top_grid_pin_23_[0]:6 0.0002961152 + +*RES +0 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_23_[0]:6 0.152 +1 top_grid_pin_23_[0]:3 top_grid_pin_23_[0]:2 0.0045 +2 top_grid_pin_23_[0]:2 top_grid_pin_23_[0] 0.003026786 +3 top_grid_pin_23_[0]:6 top_grid_pin_23_[0]:5 0.004073661 +4 top_grid_pin_23_[0]:4 top_grid_pin_23_[0]:3 0.004477679 +5 top_grid_pin_23_[0]:5 top_grid_pin_23_[0]:4 0.0003035715 + +*END + +*D_NET top_grid_pin_31_[0] 0.0006153741 //LENGTH 5.035 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 73.660 72.080 +*P top_grid_pin_31_[0] O *L 0.7423 *C 75.440 74.870 +*N top_grid_pin_31_[0]:2 *C 75.440 72.125 +*N top_grid_pin_31_[0]:3 *C 75.395 72.080 +*N top_grid_pin_31_[0]:4 *C 73.698 72.080 + +*CAP +0 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_31_[0] 0.0001763422 +2 top_grid_pin_31_[0]:2 0.0001763422 +3 top_grid_pin_31_[0]:3 0.0001308449 +4 top_grid_pin_31_[0]:4 0.0001308449 + +*RES +0 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_31_[0]:4 0.152 +1 top_grid_pin_31_[0]:4 top_grid_pin_31_[0]:3 0.001515625 +2 top_grid_pin_31_[0]:3 top_grid_pin_31_[0]:2 0.0045 +3 top_grid_pin_31_[0]:2 top_grid_pin_31_[0] 0.002450893 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.003977954 //LENGTH 31.940 LUMPCC 0.0001996588 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.925 37.060 +*I mux_bottom_ipin_1\/mux_l1_in_1_:S I *L 0.00357 *C 64.040 46.920 +*I mux_bottom_ipin_1\/mux_l1_in_2_:S I *L 0.00357 *C 61.280 51.000 +*I mux_bottom_ipin_1\/mux_l1_in_0_:S I *L 0.00357 *C 64.960 52.750 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.795 55.420 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 67.795 55.420 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 67.620 55.420 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 67.620 55.375 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 67.620 53.085 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 67.575 53.040 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 64.960 52.750 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 65.017 53.040 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 64.860 52.995 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 64.860 51.000 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 61.318 51.000 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 63.895 51.000 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 63.940 51.000 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 63.940 46.920 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 63.940 46.920 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 64.400 46.920 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 64.400 37.105 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 64.445 37.060 +*N mux_tree_tapbuf_size10_1_sram[0]:22 *C 67.888 37.060 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_ipin_1\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_ipin_1\/mux_l1_in_0_:S 1e-06 +4 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 5.172566e-05 +6 mux_tree_tapbuf_size10_1_sram[0]:6 5.434857e-05 +7 mux_tree_tapbuf_size10_1_sram[0]:7 0.000146644 +8 mux_tree_tapbuf_size10_1_sram[0]:8 0.000146644 +9 mux_tree_tapbuf_size10_1_sram[0]:9 0.0002325592 +10 mux_tree_tapbuf_size10_1_sram[0]:10 6.711247e-05 +11 mux_tree_tapbuf_size10_1_sram[0]:11 0.0002686448 +12 mux_tree_tapbuf_size10_1_sram[0]:12 0.0001298689 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0001882665 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.0002199304 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0002199304 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0002368785 +17 mux_tree_tapbuf_size10_1_sram[0]:17 3.330461e-05 +18 mux_tree_tapbuf_size10_1_sram[0]:18 0.0002129662 +19 mux_tree_tapbuf_size10_1_sram[0]:19 0.0005819634 +20 mux_tree_tapbuf_size10_1_sram[0]:20 0.000547478 +21 mux_tree_tapbuf_size10_1_sram[0]:21 0.0002175151 +22 mux_tree_tapbuf_size10_1_sram[0]:22 0.0002175151 +23 mux_tree_tapbuf_size10_1_sram[0]:12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.523485e-06 +24 mux_tree_tapbuf_size10_1_sram[0]:16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.530591e-05 +25 mux_tree_tapbuf_size10_1_sram[0]:18 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.530591e-05 +26 mux_tree_tapbuf_size10_1_sram[0]:13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.523485e-06 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:22 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.000125 +2 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:9 0.002283483 +3 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.0045 +5 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.008763393 +6 mux_tree_tapbuf_size10_1_sram[0]:22 mux_tree_tapbuf_size10_1_sram[0]:21 0.003073661 +7 mux_tree_tapbuf_size10_1_sram[0]:10 mux_bottom_ipin_1\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.00230134 +9 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:15 0.0045 +10 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:13 0.0008214285 +11 mux_tree_tapbuf_size10_1_sram[0]:14 mux_bottom_ipin_1\/mux_l1_in_2_:S 0.152 +12 mux_tree_tapbuf_size10_1_sram[0]:17 mux_bottom_ipin_1\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.0045 +14 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:16 0.003642857 +15 mux_tree_tapbuf_size10_1_sram[0]:5 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size10_1_sram[0]:6 mux_tree_tapbuf_size10_1_sram[0]:5 9.51087e-05 +17 mux_tree_tapbuf_size10_1_sram[0]:7 mux_tree_tapbuf_size10_1_sram[0]:6 0.0045 +18 mux_tree_tapbuf_size10_1_sram[0]:9 mux_tree_tapbuf_size10_1_sram[0]:8 0.0045 +19 mux_tree_tapbuf_size10_1_sram[0]:8 mux_tree_tapbuf_size10_1_sram[0]:7 0.002044643 +20 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 0.0004107143 +21 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.00178125 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[3] 0.002532969 //LENGTH 18.375 LUMPCC 0.0004938317 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 10.425 44.880 +*I mux_bottom_ipin_8\/mux_l4_in_0_:S I *L 0.00357 *C 8.380 42.160 +*I mem_bottom_ipin_8\/FTB_5__44:A I *L 0.001746 *C 5.980 53.040 +*N mux_tree_tapbuf_size10_4_sram[3]:3 *C 5.980 53.040 +*N mux_tree_tapbuf_size10_4_sram[3]:4 *C 5.980 52.995 +*N mux_tree_tapbuf_size10_4_sram[3]:5 *C 5.980 50.378 +*N mux_tree_tapbuf_size10_4_sram[3]:6 *C 5.988 50.320 +*N mux_tree_tapbuf_size10_4_sram[3]:7 *C 10.113 50.320 +*N mux_tree_tapbuf_size10_4_sram[3]:8 *C 10.120 50.263 +*N mux_tree_tapbuf_size10_4_sram[3]:9 *C 8.418 42.160 +*N mux_tree_tapbuf_size10_4_sram[3]:10 *C 10.075 42.160 +*N mux_tree_tapbuf_size10_4_sram[3]:11 *C 10.120 42.205 +*N mux_tree_tapbuf_size10_4_sram[3]:12 *C 10.120 44.880 +*N mux_tree_tapbuf_size10_4_sram[3]:13 *C 10.120 44.880 +*N mux_tree_tapbuf_size10_4_sram[3]:14 *C 10.425 44.880 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_8\/FTB_5__44:A 1e-06 +3 mux_tree_tapbuf_size10_4_sram[3]:3 3.41155e-05 +4 mux_tree_tapbuf_size10_4_sram[3]:4 0.0001540434 +5 mux_tree_tapbuf_size10_4_sram[3]:5 0.0001540434 +6 mux_tree_tapbuf_size10_4_sram[3]:6 0.0002959323 +7 mux_tree_tapbuf_size10_4_sram[3]:7 0.0002959323 +8 mux_tree_tapbuf_size10_4_sram[3]:8 0.0002149051 +9 mux_tree_tapbuf_size10_4_sram[3]:9 0.0001226316 +10 mux_tree_tapbuf_size10_4_sram[3]:10 0.0001226316 +11 mux_tree_tapbuf_size10_4_sram[3]:11 0.0001464225 +12 mux_tree_tapbuf_size10_4_sram[3]:12 0.0003933912 +13 mux_tree_tapbuf_size10_4_sram[3]:13 5.270079e-05 +14 mux_tree_tapbuf_size10_4_sram[3]:14 4.938776e-05 +15 mux_tree_tapbuf_size10_4_sram[3]:8 mux_tree_tapbuf_size8_4_sram[0]:10 0.0001366227 +16 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size8_4_sram[0]:10 1.695504e-06 +17 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size8_4_sram[0]:8 1.116489e-05 +18 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size8_4_sram[0]:9 0.0001366227 +19 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size8_4_sram[0]:7 1.116489e-05 +20 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size8_4_sram[0]:9 1.695504e-06 +21 mux_tree_tapbuf_size10_4_sram[3]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.478696e-05 +22 mux_tree_tapbuf_size10_4_sram[3]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.478696e-05 +23 mux_tree_tapbuf_size10_4_sram[3]:5 ropt_net_172:5 6.264575e-05 +24 mux_tree_tapbuf_size10_4_sram[3]:4 ropt_net_172:4 6.264575e-05 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_4_sram[3]:14 0.152 +1 mux_tree_tapbuf_size10_4_sram[3]:8 mux_tree_tapbuf_size10_4_sram[3]:7 0.00341 +2 mux_tree_tapbuf_size10_4_sram[3]:7 mux_tree_tapbuf_size10_4_sram[3]:6 0.00064625 +3 mux_tree_tapbuf_size10_4_sram[3]:5 mux_tree_tapbuf_size10_4_sram[3]:4 0.002337054 +4 mux_tree_tapbuf_size10_4_sram[3]:6 mux_tree_tapbuf_size10_4_sram[3]:5 0.00341 +5 mux_tree_tapbuf_size10_4_sram[3]:3 mem_bottom_ipin_8\/FTB_5__44:A 0.152 +6 mux_tree_tapbuf_size10_4_sram[3]:4 mux_tree_tapbuf_size10_4_sram[3]:3 0.0045 +7 mux_tree_tapbuf_size10_4_sram[3]:13 mux_tree_tapbuf_size10_4_sram[3]:12 0.0045 +8 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size10_4_sram[3]:11 0.002388393 +9 mux_tree_tapbuf_size10_4_sram[3]:12 mux_tree_tapbuf_size10_4_sram[3]:8 0.004805804 +10 mux_tree_tapbuf_size10_4_sram[3]:14 mux_tree_tapbuf_size10_4_sram[3]:13 0.0001657609 +11 mux_tree_tapbuf_size10_4_sram[3]:10 mux_tree_tapbuf_size10_4_sram[3]:9 0.001479911 +12 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size10_4_sram[3]:10 0.0045 +13 mux_tree_tapbuf_size10_4_sram[3]:9 mux_bottom_ipin_8\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[3] 0.00160064 //LENGTH 13.815 LUMPCC 0.0001802171 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 88.625 17.340 +*I mem_bottom_ipin_12\/FTB_7__46:A I *L 0.001746 *C 85.100 23.120 +*I mux_bottom_ipin_12\/mux_l4_in_0_:S I *L 0.00357 *C 81.520 23.120 +*N mux_tree_tapbuf_size10_6_sram[3]:3 *C 81.558 23.120 +*N mux_tree_tapbuf_size10_6_sram[3]:4 *C 85.062 23.120 +*N mux_tree_tapbuf_size10_6_sram[3]:5 *C 85.100 23.075 +*N mux_tree_tapbuf_size10_6_sram[3]:6 *C 85.100 17.385 +*N mux_tree_tapbuf_size10_6_sram[3]:7 *C 85.145 17.340 +*N mux_tree_tapbuf_size10_6_sram[3]:8 *C 88.588 17.340 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_12\/FTB_7__46:A 1e-06 +2 mux_bottom_ipin_12\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_6_sram[3]:3 0.0002000954 +4 mux_tree_tapbuf_size10_6_sram[3]:4 0.0002000954 +5 mux_tree_tapbuf_size10_6_sram[3]:5 0.0002822719 +6 mux_tree_tapbuf_size10_6_sram[3]:6 0.0002822719 +7 mux_tree_tapbuf_size10_6_sram[3]:7 0.0002263442 +8 mux_tree_tapbuf_size10_6_sram[3]:8 0.0002263442 +9 mux_tree_tapbuf_size10_6_sram[3]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.168111e-05 +10 mux_tree_tapbuf_size10_6_sram[3]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.842741e-05 +11 mux_tree_tapbuf_size10_6_sram[3]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.842741e-05 +12 mux_tree_tapbuf_size10_6_sram[3]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.168111e-05 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_6_sram[3]:8 0.152 +1 mux_tree_tapbuf_size10_6_sram[3]:4 mem_bottom_ipin_12\/FTB_7__46:A 0.152 +2 mux_tree_tapbuf_size10_6_sram[3]:4 mux_tree_tapbuf_size10_6_sram[3]:3 0.003129464 +3 mux_tree_tapbuf_size10_6_sram[3]:5 mux_tree_tapbuf_size10_6_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size10_6_sram[3]:7 mux_tree_tapbuf_size10_6_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size10_6_sram[3]:6 mux_tree_tapbuf_size10_6_sram[3]:5 0.005080357 +6 mux_tree_tapbuf_size10_6_sram[3]:8 mux_tree_tapbuf_size10_6_sram[3]:7 0.003073661 +7 mux_tree_tapbuf_size10_6_sram[3]:3 mux_bottom_ipin_12\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_4_ccff_tail[0] 0.001172638 //LENGTH 9.105 LUMPCC 0.0002079458 DR + +*CONN +*I mem_bottom_ipin_8\/FTB_5__44:X O *L 0 *C 3.030 52.360 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.825 49.980 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 *C 8.787 49.980 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 *C 5.105 49.980 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 *C 5.060 50.025 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 *C 5.060 52.315 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 *C 5.015 52.360 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 *C 3.068 52.360 + +*CAP +0 mem_bottom_ipin_8\/FTB_5__44:X 1e-06 +1 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 0.0002112738 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.0002112738 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0001197499 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0001197499 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.0001503225 +7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.0001503225 +8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 prog_clk[0]:360 9.172012e-07 +9 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 prog_clk[0]:363 2.084548e-07 +10 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 prog_clk[0]:362 5.37349e-05 +11 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 prog_clk[0]:363 9.172012e-07 +12 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 prog_clk[0]:364 2.084548e-07 +13 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 prog_clk[0]:361 5.37349e-05 +14 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 ropt_net_172:4 4.459528e-05 +15 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 ropt_net_172:6 4.517088e-06 +16 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 ropt_net_172:5 4.459528e-05 +17 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 ropt_net_172:7 4.517088e-06 + +*RES +0 mem_bottom_ipin_8\/FTB_5__44:X mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.001738839 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 0.003287947 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[0] 0.004526975 //LENGTH 26.615 LUMPCC 0.002293182 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 76.205 39.100 +*I mux_bottom_ipin_6\/mux_l1_in_0_:S I *L 0.00357 *C 81.980 25.840 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 85.190 33.660 +*N mux_tree_tapbuf_size8_2_sram[0]:3 *C 85.100 33.660 +*N mux_tree_tapbuf_size8_2_sram[0]:4 *C 85.100 33.660 +*N mux_tree_tapbuf_size8_2_sram[0]:5 *C 82.017 25.840 +*N mux_tree_tapbuf_size8_2_sram[0]:6 *C 84.595 25.840 +*N mux_tree_tapbuf_size8_2_sram[0]:7 *C 84.640 25.885 +*N mux_tree_tapbuf_size8_2_sram[0]:8 *C 84.640 33.660 +*N mux_tree_tapbuf_size8_2_sram[0]:9 *C 84.675 33.960 +*N mux_tree_tapbuf_size8_2_sram[0]:10 *C 84.633 34.000 +*N mux_tree_tapbuf_size8_2_sram[0]:11 *C 76.368 34.000 +*N mux_tree_tapbuf_size8_2_sram[0]:12 *C 76.360 34.058 +*N mux_tree_tapbuf_size8_2_sram[0]:13 *C 76.360 39.055 +*N mux_tree_tapbuf_size8_2_sram[0]:14 *C 76.360 39.100 +*N mux_tree_tapbuf_size8_2_sram[0]:15 *C 76.205 39.100 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_2_sram[0]:3 3.410207e-05 +4 mux_tree_tapbuf_size8_2_sram[0]:4 7.06487e-05 +5 mux_tree_tapbuf_size8_2_sram[0]:5 0.0001764271 +6 mux_tree_tapbuf_size8_2_sram[0]:6 0.0001764271 +7 mux_tree_tapbuf_size8_2_sram[0]:7 0.0003080747 +8 mux_tree_tapbuf_size8_2_sram[0]:8 0.0003746726 +9 mux_tree_tapbuf_size8_2_sram[0]:9 3.038289e-05 +10 mux_tree_tapbuf_size8_2_sram[0]:10 0.0001927587 +11 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001927587 +12 mux_tree_tapbuf_size8_2_sram[0]:12 0.0002815252 +13 mux_tree_tapbuf_size8_2_sram[0]:13 0.0002815252 +14 mux_tree_tapbuf_size8_2_sram[0]:14 5.799779e-05 +15 mux_tree_tapbuf_size8_2_sram[0]:15 5.349307e-05 +16 mux_tree_tapbuf_size8_2_sram[0]:11 chanx_left_in[7]:15 0.0001474309 +17 mux_tree_tapbuf_size8_2_sram[0]:11 chanx_left_in[7]:16 0.0003193094 +18 mux_tree_tapbuf_size8_2_sram[0]:10 chanx_left_in[7]:14 0.0001474309 +19 mux_tree_tapbuf_size8_2_sram[0]:10 chanx_left_in[7]:15 0.0003193094 +20 mux_tree_tapbuf_size8_2_sram[0]:11 chanx_right_in[5]:28 0.0004667402 +21 mux_tree_tapbuf_size8_2_sram[0]:10 chanx_right_in[5]:29 0.0004667402 +22 mux_tree_tapbuf_size8_2_sram[0]:7 prog_clk[0]:97 0.0002024203 +23 mux_tree_tapbuf_size8_2_sram[0]:7 prog_clk[0]:103 8.217059e-08 +24 mux_tree_tapbuf_size8_2_sram[0]:9 prog_clk[0]:96 1.06077e-05 +25 mux_tree_tapbuf_size8_2_sram[0]:8 prog_clk[0]:96 0.0002024203 +26 mux_tree_tapbuf_size8_2_sram[0]:8 prog_clk[0]:97 1.06077e-05 +27 mux_tree_tapbuf_size8_2_sram[0]:8 prog_clk[0]:100 8.217059e-08 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_2_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_2_sram[0]:3 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size8_2_sram[0]:4 mux_tree_tapbuf_size8_2_sram[0]:3 0.0045 +3 mux_tree_tapbuf_size8_2_sram[0]:6 mux_tree_tapbuf_size8_2_sram[0]:5 0.002301339 +4 mux_tree_tapbuf_size8_2_sram[0]:7 mux_tree_tapbuf_size8_2_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size8_2_sram[0]:5 mux_bottom_ipin_6\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_2_sram[0]:15 mux_tree_tapbuf_size8_2_sram[0]:14 8.423914e-05 +7 mux_tree_tapbuf_size8_2_sram[0]:14 mux_tree_tapbuf_size8_2_sram[0]:13 0.0045 +8 mux_tree_tapbuf_size8_2_sram[0]:13 mux_tree_tapbuf_size8_2_sram[0]:12 0.004462054 +9 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:11 0.00341 +10 mux_tree_tapbuf_size8_2_sram[0]:11 mux_tree_tapbuf_size8_2_sram[0]:10 0.00129485 +11 mux_tree_tapbuf_size8_2_sram[0]:9 mux_tree_tapbuf_size8_2_sram[0]:8 0.0001785714 +12 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:9 0.00341 +13 mux_tree_tapbuf_size8_2_sram[0]:8 mux_tree_tapbuf_size8_2_sram[0]:7 0.006941965 +14 mux_tree_tapbuf_size8_2_sram[0]:8 mux_tree_tapbuf_size8_2_sram[0]:4 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[0] 0.005923643 //LENGTH 43.345 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 28.365 26.180 +*I mux_bottom_ipin_11\/mux_l1_in_0_:S I *L 0.00357 *C 30.020 52.700 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 18.575 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:3 *C 27.810 27.200 +*N mux_tree_tapbuf_size8_5_sram[0]:4 *C 18.613 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:5 *C 30.315 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:6 *C 30.360 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:7 *C 29.900 52.700 +*N mux_tree_tapbuf_size8_5_sram[0]:8 *C 29.900 52.655 +*N mux_tree_tapbuf_size8_5_sram[0]:9 *C 29.900 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:10 *C 29.900 46.977 +*N mux_tree_tapbuf_size8_5_sram[0]:11 *C 29.893 46.920 +*N mux_tree_tapbuf_size8_5_sram[0]:12 *C 28.540 46.920 +*N mux_tree_tapbuf_size8_5_sram[0]:13 *C 28.520 46.913 +*N mux_tree_tapbuf_size8_5_sram[0]:14 *C 28.520 27.207 +*N mux_tree_tapbuf_size8_5_sram[0]:15 *C 28.518 27.200 +*N mux_tree_tapbuf_size8_5_sram[0]:16 *C 28.520 27.143 +*N mux_tree_tapbuf_size8_5_sram[0]:17 *C 28.520 26.225 +*N mux_tree_tapbuf_size8_5_sram[0]:18 *C 28.520 26.180 +*N mux_tree_tapbuf_size8_5_sram[0]:19 *C 28.365 26.180 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_11\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_5_sram[0]:3 0.000101831 +4 mux_tree_tapbuf_size8_5_sram[0]:4 0.0008106417 +5 mux_tree_tapbuf_size8_5_sram[0]:5 0.0008106417 +6 mux_tree_tapbuf_size8_5_sram[0]:6 6.864348e-05 +7 mux_tree_tapbuf_size8_5_sram[0]:7 3.618333e-05 +8 mux_tree_tapbuf_size8_5_sram[0]:8 0.0002965975 +9 mux_tree_tapbuf_size8_5_sram[0]:9 0.0003997978 +10 mux_tree_tapbuf_size8_5_sram[0]:10 6.80423e-05 +11 mux_tree_tapbuf_size8_5_sram[0]:11 0.0001345906 +12 mux_tree_tapbuf_size8_5_sram[0]:12 0.0001345906 +13 mux_tree_tapbuf_size8_5_sram[0]:13 0.001358298 +14 mux_tree_tapbuf_size8_5_sram[0]:14 0.001358298 +15 mux_tree_tapbuf_size8_5_sram[0]:15 0.000101831 +16 mux_tree_tapbuf_size8_5_sram[0]:16 7.111296e-05 +17 mux_tree_tapbuf_size8_5_sram[0]:17 7.111296e-05 +18 mux_tree_tapbuf_size8_5_sram[0]:18 5.129224e-05 +19 mux_tree_tapbuf_size8_5_sram[0]:19 4.713917e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_5_sram[0]:19 0.152 +1 mux_tree_tapbuf_size8_5_sram[0]:5 mux_tree_tapbuf_size8_5_sram[0]:4 0.01044866 +2 mux_tree_tapbuf_size8_5_sram[0]:6 mux_tree_tapbuf_size8_5_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size8_5_sram[0]:4 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size8_5_sram[0]:10 mux_tree_tapbuf_size8_5_sram[0]:9 0.0008593751 +5 mux_tree_tapbuf_size8_5_sram[0]:11 mux_tree_tapbuf_size8_5_sram[0]:10 0.00341 +6 mux_tree_tapbuf_size8_5_sram[0]:12 mux_tree_tapbuf_size8_5_sram[0]:11 0.0002118916 +7 mux_tree_tapbuf_size8_5_sram[0]:13 mux_tree_tapbuf_size8_5_sram[0]:12 0.00341 +8 mux_tree_tapbuf_size8_5_sram[0]:15 mux_tree_tapbuf_size8_5_sram[0]:14 0.00341 +9 mux_tree_tapbuf_size8_5_sram[0]:15 mux_tree_tapbuf_size8_5_sram[0]:3 0.0001039141 +10 mux_tree_tapbuf_size8_5_sram[0]:14 mux_tree_tapbuf_size8_5_sram[0]:13 0.003087116 +11 mux_tree_tapbuf_size8_5_sram[0]:16 mux_tree_tapbuf_size8_5_sram[0]:15 0.00341 +12 mux_tree_tapbuf_size8_5_sram[0]:18 mux_tree_tapbuf_size8_5_sram[0]:17 0.0045 +13 mux_tree_tapbuf_size8_5_sram[0]:17 mux_tree_tapbuf_size8_5_sram[0]:16 0.0008191964 +14 mux_tree_tapbuf_size8_5_sram[0]:19 mux_tree_tapbuf_size8_5_sram[0]:18 8.423914e-05 +15 mux_tree_tapbuf_size8_5_sram[0]:7 mux_bottom_ipin_11\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size8_5_sram[0]:8 mux_tree_tapbuf_size8_5_sram[0]:7 0.0045 +17 mux_tree_tapbuf_size8_5_sram[0]:9 mux_tree_tapbuf_size8_5_sram[0]:8 0.004209822 +18 mux_tree_tapbuf_size8_5_sram[0]:9 mux_tree_tapbuf_size8_5_sram[0]:6 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[1] 0.003939644 //LENGTH 30.445 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.820 63.580 +*I mux_bottom_ipin_15\/mux_l2_in_2_:S I *L 0.00357 *C 70.940 61.200 +*I mux_bottom_ipin_15\/mux_l2_in_3_:S I *L 0.00357 *C 68.900 61.200 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 65.495 69.700 +*I mux_bottom_ipin_15\/mux_l2_in_0_:S I *L 0.00357 *C 62.660 61.200 +*I mux_bottom_ipin_15\/mux_l2_in_1_:S I *L 0.00357 *C 60.620 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:6 *C 60.658 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:7 *C 62.660 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:8 *C 65.495 69.700 +*N mux_tree_tapbuf_size8_7_sram[1]:9 *C 65.320 69.700 +*N mux_tree_tapbuf_size8_7_sram[1]:10 *C 65.320 69.655 +*N mux_tree_tapbuf_size8_7_sram[1]:11 *C 65.320 61.245 +*N mux_tree_tapbuf_size8_7_sram[1]:12 *C 65.320 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:13 *C 68.900 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:14 *C 70.940 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:15 *C 78.615 61.200 +*N mux_tree_tapbuf_size8_7_sram[1]:16 *C 78.660 61.245 +*N mux_tree_tapbuf_size8_7_sram[1]:17 *C 78.660 63.535 +*N mux_tree_tapbuf_size8_7_sram[1]:18 *C 78.660 63.580 +*N mux_tree_tapbuf_size8_7_sram[1]:19 *C 78.820 63.580 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_15\/mux_l2_in_3_:S 1e-06 +3 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_0_:S 1e-06 +5 mux_bottom_ipin_15\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size8_7_sram[1]:6 0.0001501451 +7 mux_tree_tapbuf_size8_7_sram[1]:7 0.0003491532 +8 mux_tree_tapbuf_size8_7_sram[1]:8 5.072483e-05 +9 mux_tree_tapbuf_size8_7_sram[1]:9 5.476951e-05 +10 mux_tree_tapbuf_size8_7_sram[1]:10 0.0004635991 +11 mux_tree_tapbuf_size8_7_sram[1]:11 0.0004635991 +12 mux_tree_tapbuf_size8_7_sram[1]:12 0.0004456082 +13 mux_tree_tapbuf_size8_7_sram[1]:13 0.0004143891 +14 mux_tree_tapbuf_size8_7_sram[1]:14 0.0006577342 +15 mux_tree_tapbuf_size8_7_sram[1]:15 0.0004834047 +16 mux_tree_tapbuf_size8_7_sram[1]:16 0.0001491946 +17 mux_tree_tapbuf_size8_7_sram[1]:17 0.0001491946 +18 mux_tree_tapbuf_size8_7_sram[1]:18 5.323913e-05 +19 mux_tree_tapbuf_size8_7_sram[1]:19 4.888923e-05 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_7_sram[1]:19 0.152 +1 mux_tree_tapbuf_size8_7_sram[1]:19 mux_tree_tapbuf_size8_7_sram[1]:18 8.695653e-05 +2 mux_tree_tapbuf_size8_7_sram[1]:18 mux_tree_tapbuf_size8_7_sram[1]:17 0.0045 +3 mux_tree_tapbuf_size8_7_sram[1]:17 mux_tree_tapbuf_size8_7_sram[1]:16 0.002044643 +4 mux_tree_tapbuf_size8_7_sram[1]:15 mux_tree_tapbuf_size8_7_sram[1]:14 0.006852679 +5 mux_tree_tapbuf_size8_7_sram[1]:16 mux_tree_tapbuf_size8_7_sram[1]:15 0.0045 +6 mux_tree_tapbuf_size8_7_sram[1]:13 mux_bottom_ipin_15\/mux_l2_in_3_:S 0.152 +7 mux_tree_tapbuf_size8_7_sram[1]:13 mux_tree_tapbuf_size8_7_sram[1]:12 0.003196429 +8 mux_tree_tapbuf_size8_7_sram[1]:14 mux_bottom_ipin_15\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size8_7_sram[1]:14 mux_tree_tapbuf_size8_7_sram[1]:13 0.001821429 +10 mux_tree_tapbuf_size8_7_sram[1]:6 mux_bottom_ipin_15\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size8_7_sram[1]:12 mux_tree_tapbuf_size8_7_sram[1]:11 0.0045 +12 mux_tree_tapbuf_size8_7_sram[1]:12 mux_tree_tapbuf_size8_7_sram[1]:7 0.002375 +13 mux_tree_tapbuf_size8_7_sram[1]:11 mux_tree_tapbuf_size8_7_sram[1]:10 0.007508929 +14 mux_tree_tapbuf_size8_7_sram[1]:9 mux_tree_tapbuf_size8_7_sram[1]:8 9.51087e-05 +15 mux_tree_tapbuf_size8_7_sram[1]:10 mux_tree_tapbuf_size8_7_sram[1]:9 0.0045 +16 mux_tree_tapbuf_size8_7_sram[1]:8 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size8_7_sram[1]:7 mux_bottom_ipin_15\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size8_7_sram[1]:7 mux_tree_tapbuf_size8_7_sram[1]:6 0.001787947 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006823447 //LENGTH 4.650 LUMPCC 0.0002253684 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_0_:X O *L 0 *C 64.115 53.380 +*I mux_bottom_ipin_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 62.925 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 62.963 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.895 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.940 56.055 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.940 53.425 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.940 53.380 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 64.115 53.380 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.258211e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.258211e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001268318 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001268318 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.994886e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.61996e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:26 4.878097e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:27 4.878097e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.263455e-06 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.263455e-06 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.963978e-05 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.963978e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325893 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009379439 //LENGTH 7.455 LUMPCC 0.0002567493 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_0_:X O *L 0 *C 49.045 28.220 +*I mux_bottom_ipin_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 49.320 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 49.282 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 48.345 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 48.300 23.505 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 48.300 28.175 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 48.345 28.220 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 49.008 28.220 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.464862e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.464862e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000205678 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000205678 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.927071e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.927071e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[0]:40 7.941508e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[0]:39 7.941508e-05 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[2]:42 4.895957e-05 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[2]:43 4.895957e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005210569 //LENGTH 3.280 LUMPCC 6.207998e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_1_:X O *L 0 *C 53.535 45.560 +*I mux_bottom_ipin_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 54.110 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 54.110 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 53.820 47.940 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 53.820 47.895 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 53.820 45.605 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 53.820 45.560 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 53.535 45.560 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.734754e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.334336e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001208046 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001208046 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.76398e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.7037e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:17 3.103999e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_3_sram[1]:20 3.103999e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001576087 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001222826 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005507341 //LENGTH 3.850 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_0_:X O *L 0 *C 22.255 53.720 +*I mux_bottom_ipin_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 21.525 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 21.562 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 22.035 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 22.080 56.055 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 22.080 53.765 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 22.080 53.720 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 22.255 53.720 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.994753e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.994753e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000151634 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000151634 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.427257e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.129851e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005597911 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l2_in_1_:X O *L 0 *C 77.565 18.020 +*I mux_bottom_ipin_12\/mux_l3_in_0_:A0 I *L 0.001631 *C 77.915 20.740 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 77.915 20.740 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 77.740 20.740 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 77.740 20.695 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 77.740 18.065 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 77.740 18.020 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 77.565 18.020 + +*CAP +0 mux_bottom_ipin_12\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.914789e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.97123e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001772409 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001772409 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.378475e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.066444e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l2_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.51087e-05 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_12\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004573448 //LENGTH 3.420 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l2_in_0_:X O *L 0 *C 37.435 25.160 +*I mux_bottom_ipin_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 36.245 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 36.245 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 36.340 23.505 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 36.340 25.115 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 36.385 25.160 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 37.398 25.160 + +*CAP +0 mux_bottom_ipin_2\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.680151e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001057121 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001057121 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001085595 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001085595 + +*RES +0 mux_bottom_ipin_2\/mux_l2_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_2\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0014375 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0009040179 + +*END + +*D_NET optlc_net_126 0.005975086 //LENGTH 46.280 LUMPCC 0.0005200633 DR + +*CONN +*I optlc_126:HI O *L 0 *C 59.800 15.300 +*I mux_bottom_ipin_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 42.610 21.080 +*I mux_bottom_ipin_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 54.915 20.740 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 63.310 9.860 +*I mux_bottom_ipin_12\/mux_l2_in_3_:A0 I *L 0.001631 *C 71.935 11.900 +*N optlc_net_126:5 *C 71.898 11.900 +*N optlc_net_126:6 *C 70.885 11.900 +*N optlc_net_126:7 *C 70.840 11.855 +*N optlc_net_126:8 *C 70.840 9.905 +*N optlc_net_126:9 *C 70.795 9.860 +*N optlc_net_126:10 *C 63.310 9.860 +*N optlc_net_126:11 *C 60.765 9.860 +*N optlc_net_126:12 *C 60.720 9.905 +*N optlc_net_126:13 *C 60.720 15.255 +*N optlc_net_126:14 *C 60.675 15.300 +*N optlc_net_126:15 *C 54.915 20.740 +*N optlc_net_126:16 *C 42.648 21.080 +*N optlc_net_126:17 *C 54.915 21.080 +*N optlc_net_126:18 *C 55.615 21.080 +*N optlc_net_126:19 *C 55.660 21.035 +*N optlc_net_126:20 *C 55.660 15.005 +*N optlc_net_126:21 *C 55.705 14.960 +*N optlc_net_126:22 *C 59.340 14.960 +*N optlc_net_126:23 *C 59.340 15.300 +*N optlc_net_126:24 *C 59.800 15.300 + +*CAP +0 optlc_126:HI 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_4\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_0\/mux_l2_in_3_:A0 1e-06 +4 mux_bottom_ipin_12\/mux_l2_in_3_:A0 1e-06 +5 optlc_net_126:5 7.577345e-05 +6 optlc_net_126:6 7.577345e-05 +7 optlc_net_126:7 0.0001217292 +8 optlc_net_126:8 0.0001217292 +9 optlc_net_126:9 0.0004905802 +10 optlc_net_126:10 0.0006933 +11 optlc_net_126:11 0.0001767749 +12 optlc_net_126:12 0.0003222666 +13 optlc_net_126:13 0.0003222666 +14 optlc_net_126:14 6.65564e-05 +15 optlc_net_126:15 6.373823e-05 +16 optlc_net_126:16 0.0006330006 +17 optlc_net_126:17 0.0007274881 +18 optlc_net_126:18 6.299864e-05 +19 optlc_net_126:19 0.0003961662 +20 optlc_net_126:20 0.0003961662 +21 optlc_net_126:21 0.0002469832 +22 optlc_net_126:22 0.0002699396 +23 optlc_net_126:23 5.561832e-05 +24 optlc_net_126:24 0.0001311739 +25 optlc_net_126:16 chanx_right_in[6]:26 0.0001931616 +26 optlc_net_126:20 chanx_right_in[6]:29 2.306257e-06 +27 optlc_net_126:19 chanx_right_in[6]:28 2.306257e-06 +28 optlc_net_126:17 chanx_right_in[6]:27 0.0001931616 +29 optlc_net_126:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.882516e-05 +30 optlc_net_126:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.573858e-05 +31 optlc_net_126:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.573858e-05 +32 optlc_net_126:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 3.882516e-05 + +*RES +0 optlc_126:HI optlc_net_126:24 0.152 +1 optlc_net_126:16 mux_bottom_ipin_2\/mux_l2_in_3_:A0 0.152 +2 optlc_net_126:11 optlc_net_126:10 0.002272321 +3 optlc_net_126:12 optlc_net_126:11 0.0045 +4 optlc_net_126:14 optlc_net_126:13 0.0045 +5 optlc_net_126:13 optlc_net_126:12 0.004776786 +6 optlc_net_126:9 optlc_net_126:8 0.0045 +7 optlc_net_126:8 optlc_net_126:7 0.001741072 +8 optlc_net_126:6 optlc_net_126:5 0.0009040178 +9 optlc_net_126:7 optlc_net_126:6 0.0045 +10 optlc_net_126:5 mux_bottom_ipin_12\/mux_l2_in_3_:A0 0.152 +11 optlc_net_126:15 mux_bottom_ipin_4\/mux_l2_in_3_:A0 0.152 +12 optlc_net_126:21 optlc_net_126:20 0.0045 +13 optlc_net_126:20 optlc_net_126:19 0.005383929 +14 optlc_net_126:18 optlc_net_126:17 0.000625 +15 optlc_net_126:19 optlc_net_126:18 0.0045 +16 optlc_net_126:24 optlc_net_126:23 0.0004107143 +17 optlc_net_126:24 optlc_net_126:14 0.0007812501 +18 optlc_net_126:10 mux_bottom_ipin_0\/mux_l2_in_3_:A0 0.152 +19 optlc_net_126:10 optlc_net_126:9 0.006683036 +20 optlc_net_126:17 optlc_net_126:16 0.01095312 +21 optlc_net_126:17 optlc_net_126:15 0.0003035715 +22 optlc_net_126:22 optlc_net_126:21 0.003245536 +23 optlc_net_126:23 optlc_net_126:22 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0] 0.008693491 //LENGTH 66.425 LUMPCC 0.001740758 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l4_in_0_:X O *L 0 *C 15.355 18.360 +*I mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 20.420 69.500 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 20.383 69.407 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 19.825 69.360 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 19.780 69.315 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 19.780 68.737 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 19.773 68.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 11.060 68.680 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 11.040 68.672 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 11.040 18.367 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 11.060 18.360 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 15.173 18.360 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 15.180 18.360 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 15.180 18.360 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 15.355 18.360 + +*CAP +0 mux_bottom_ipin_10\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.147327e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.147327e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.309633e-05 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.309633e-05 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004975463 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0004975463 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.002404673 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.002404673 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0003792712 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0003792712 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 3.822968e-05 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 6.125448e-05 +14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:14 5.913049e-05 +15 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 chanx_left_in[0]:60 0.0003042754 +16 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chanx_left_in[0]:61 0.0003042754 +17 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_right_in[1]:13 0.0002963186 +18 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[1]:14 0.0002963186 +19 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 chanx_right_in[3]:23 0.0002697848 +20 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chanx_right_in[3]:24 0.0002697848 + +*RES +0 mux_bottom_ipin_10\/mux_l4_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 9.51087e-05 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0045 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0006442916 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.007881116 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001364958 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000515625 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004977679 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chanx_right_out[12] 0.001592655 //LENGTH 11.765 LUMPCC 0.001015445 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 94.300 71.400 +*P chanx_right_out[12] O *L 0.7423 *C 103.650 70.720 +*N chanx_right_out[12]:2 *C 93.848 70.720 +*N chanx_right_out[12]:3 *C 93.840 70.778 +*N chanx_right_out[12]:4 *C 93.840 71.355 +*N chanx_right_out[12]:5 *C 93.885 71.400 +*N chanx_right_out[12]:6 *C 94.263 71.400 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 chanx_right_out[12] 0.0001858128 +2 chanx_right_out[12]:2 0.0001858128 +3 chanx_right_out[12]:3 5.545976e-05 +4 chanx_right_out[12]:4 5.545976e-05 +5 chanx_right_out[12]:5 4.683225e-05 +6 chanx_right_out[12]:6 4.683225e-05 +7 chanx_right_out[12] chanx_right_in[11] 0.0002538614 +8 chanx_right_out[12]:2 chanx_right_in[11]:35 0.0002538614 +9 chanx_right_out[12] chanx_right_in[13] 0.0002538614 +10 chanx_right_out[12]:2 chanx_right_in[13]:26 0.0002538614 + +*RES +0 ropt_mt_inst_773:X chanx_right_out[12]:6 0.152 +1 chanx_right_out[12]:6 chanx_right_out[12]:5 0.0003370536 +2 chanx_right_out[12]:5 chanx_right_out[12]:4 0.0045 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0005156249 +4 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +5 chanx_right_out[12]:2 chanx_right_out[12] 0.001535725 + +*END + +*D_NET ropt_net_157 0.002410284 //LENGTH 17.715 LUMPCC 0.0003334031 DR + +*CONN +*I FTB_14__13:X O *L 0 *C 95.680 61.540 +*I ropt_mt_inst_755:A I *L 0.001766 *C 97.825 63.920 +*N ropt_net_157:2 *C 97.825 63.920 +*N ropt_net_157:3 *C 97.520 63.920 +*N ropt_net_157:4 *C 97.520 63.965 +*N ropt_net_157:5 *C 97.520 66.583 +*N ropt_net_157:6 *C 97.528 66.640 +*N ropt_net_157:7 *C 100.733 66.640 +*N ropt_net_157:8 *C 100.740 66.583 +*N ropt_net_157:9 *C 100.740 61.585 +*N ropt_net_157:10 *C 100.695 61.540 +*N ropt_net_157:11 *C 95.718 61.540 + +*CAP +0 FTB_14__13:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_157:2 6.091219e-05 +3 ropt_net_157:3 5.520867e-05 +4 ropt_net_157:4 0.000138095 +5 ropt_net_157:5 0.000138095 +6 ropt_net_157:6 0.0002470819 +7 ropt_net_157:7 0.0002470819 +8 ropt_net_157:8 0.0003039601 +9 ropt_net_157:9 0.0003039601 +10 ropt_net_157:10 0.0002902429 +11 ropt_net_157:11 0.0002902429 +12 ropt_net_157:11 ropt_net_183:2 0.0001023661 +13 ropt_net_157:11 ropt_net_183:6 4.993096e-07 +14 ropt_net_157:10 ropt_net_183:3 0.0001023661 +15 ropt_net_157:10 ropt_net_183:7 4.993096e-07 +16 ropt_net_157:7 chanx_right_out[14] 3.645915e-05 +17 ropt_net_157:5 chanx_right_out[14]:4 2.737699e-05 +18 ropt_net_157:6 chanx_right_out[14]:2 3.645915e-05 +19 ropt_net_157:4 chanx_right_out[14]:3 2.737699e-05 + +*RES +0 FTB_14__13:X ropt_net_157:11 0.152 +1 ropt_net_157:11 ropt_net_157:10 0.004444197 +2 ropt_net_157:10 ropt_net_157:9 0.0045 +3 ropt_net_157:9 ropt_net_157:8 0.004462054 +4 ropt_net_157:8 ropt_net_157:7 0.00341 +5 ropt_net_157:7 ropt_net_157:6 0.0005021166 +6 ropt_net_157:5 ropt_net_157:4 0.002337053 +7 ropt_net_157:6 ropt_net_157:5 0.00341 +8 ropt_net_157:3 ropt_net_157:2 0.0001657609 +9 ropt_net_157:4 ropt_net_157:3 0.0045 +10 ropt_net_157:2 ropt_mt_inst_755:A 0.152 + +*END + +*D_NET chanx_left_out[4] 0.001094782 //LENGTH 7.165 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 6.900 65.960 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 66.640 +*N chanx_left_out[4]:2 *C 5.513 66.640 +*N chanx_left_out[4]:3 *C 5.520 66.583 +*N chanx_left_out[4]:4 *C 5.520 66.005 +*N chanx_left_out[4]:5 *C 5.565 65.960 +*N chanx_left_out[4]:6 *C 6.863 65.960 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 chanx_left_out[4] 0.0003668776 +2 chanx_left_out[4]:2 0.0003668776 +3 chanx_left_out[4]:3 6.859734e-05 +4 chanx_left_out[4]:4 6.859734e-05 +5 chanx_left_out[4]:5 0.0001114159 +6 chanx_left_out[4]:6 0.0001114159 + +*RES +0 ropt_mt_inst_777:X chanx_left_out[4]:6 0.152 +1 chanx_left_out[4]:6 chanx_left_out[4]:5 0.001158482 +2 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +3 chanx_left_out[4]:4 chanx_left_out[4]:3 0.000515625 +4 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.000670925 + +*END + +*D_NET chanx_right_out[15] 0.0007121961 //LENGTH 5.555 LUMPCC 0.0001461547 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 98.900 50.660 +*P chanx_right_out[15] O *L 0.7423 *C 103.583 50.320 +*N chanx_right_out[15]:2 *C 103.500 50.320 +*N chanx_right_out[15]:3 *C 103.500 50.320 +*N chanx_right_out[15]:4 *C 103.500 50.660 +*N chanx_right_out[15]:5 *C 103.455 50.660 +*N chanx_right_out[15]:6 *C 98.938 50.660 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 chanx_right_out[15] 2.54875e-05 +2 chanx_right_out[15]:2 2.54875e-05 +3 chanx_right_out[15]:3 4.003993e-05 +4 chanx_right_out[15]:4 3.731206e-05 +5 chanx_right_out[15]:5 0.0002183572 +6 chanx_right_out[15]:6 0.0002183572 +7 chanx_right_out[15] ropt_net_177:7 8.123909e-06 +8 chanx_right_out[15]:6 ropt_net_177:4 6.224122e-05 +9 chanx_right_out[15]:5 ropt_net_177:5 6.224122e-05 +10 chanx_right_out[15]:4 ropt_net_177:7 2.712223e-06 +11 chanx_right_out[15]:3 ropt_net_177:6 2.712223e-06 +12 chanx_right_out[15]:2 ropt_net_177:6 8.123909e-06 + +*RES +0 ropt_mt_inst_782:X chanx_right_out[15]:6 0.152 +1 chanx_right_out[15]:6 chanx_right_out[15]:5 0.004033482 +2 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +3 chanx_right_out[15]:4 chanx_right_out[15]:3 0.0001634616 +4 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +5 chanx_right_out[15]:2 chanx_right_out[15] 2.35e-05 + +*END + +*D_NET ropt_net_174 0.001178132 //LENGTH 9.565 LUMPCC 0.0002950446 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 7.095 46.920 +*I ropt_mt_inst_778:A I *L 0.001767 *C 3.220 42.160 +*N ropt_net_174:2 *C 3.258 42.160 +*N ropt_net_174:3 *C 5.475 42.160 +*N ropt_net_174:4 *C 5.520 42.205 +*N ropt_net_174:5 *C 5.520 46.875 +*N ropt_net_174:6 *C 5.565 46.920 +*N ropt_net_174:7 *C 7.058 46.920 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 ropt_mt_inst_778:A 1e-06 +2 ropt_net_174:2 0.0001066484 +3 ropt_net_174:3 0.0001066484 +4 ropt_net_174:4 0.0002179072 +5 ropt_net_174:5 0.0002179072 +6 ropt_net_174:6 0.0001159883 +7 ropt_net_174:7 0.0001159883 +8 ropt_net_174:4 mux_tree_tapbuf_size10_4_sram[2]:15 7.2311e-05 +9 ropt_net_174:5 mux_tree_tapbuf_size10_4_sram[2]:14 7.2311e-05 +10 ropt_net_174:2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.125181e-05 +11 ropt_net_174:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.125181e-05 +12 ropt_net_174:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 1.395952e-05 +13 ropt_net_174:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.395952e-05 + +*RES +0 ropt_mt_inst_762:X ropt_net_174:7 0.152 +1 ropt_net_174:2 ropt_mt_inst_778:A 0.152 +2 ropt_net_174:3 ropt_net_174:2 0.001979911 +3 ropt_net_174:4 ropt_net_174:3 0.0045 +4 ropt_net_174:6 ropt_net_174:5 0.0045 +5 ropt_net_174:5 ropt_net_174:4 0.004169643 +6 ropt_net_174:7 ropt_net_174:6 0.001332589 + +*END + +*D_NET chanx_right_out[7] 0.0009296877 //LENGTH 6.195 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_793:X O *L 0 *C 98.900 14.280 +*P chanx_right_out[7] O *L 0.7423 *C 103.650 14.960 +*N chanx_right_out[7]:2 *C 103.650 14.960 +*N chanx_right_out[7]:3 *C 103.650 14.280 +*N chanx_right_out[7]:4 *C 98.907 14.280 +*N chanx_right_out[7]:5 *C 98.900 14.280 +*N chanx_right_out[7]:6 *C 98.900 14.280 + +*CAP +0 ropt_mt_inst_793:X 1e-06 +1 chanx_right_out[7] 2.921873e-05 +2 chanx_right_out[7]:2 7.941831e-05 +3 chanx_right_out[7]:3 0.0004017914 +4 chanx_right_out[7]:4 0.0003515918 +5 chanx_right_out[7]:5 3.584968e-05 +6 chanx_right_out[7]:6 3.081781e-05 + +*RES +0 ropt_mt_inst_793:X chanx_right_out[7]:6 0.152 +1 chanx_right_out[7]:6 chanx_right_out[7]:5 0.0045 +2 chanx_right_out[7]:5 chanx_right_out[7]:4 0.00341 +3 chanx_right_out[7]:4 chanx_right_out[7]:3 0.0007429916 +4 chanx_right_out[7]:3 chanx_right_out[7]:2 0.0001065333 +5 chanx_right_out[7]:2 chanx_right_out[7] 2.428333e-05 + +*END + +*D_NET chanx_left_out[3] 0.002667495 //LENGTH 20.870 LUMPCC 0.00013241 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 20.895 4.760 +*P chanx_left_out[3] O *L 0.7423 *C 4.600 1.290 +*N chanx_left_out[3]:2 *C 4.600 3.695 +*N chanx_left_out[3]:3 *C 4.645 3.740 +*N chanx_left_out[3]:4 *C 15.595 3.740 +*N chanx_left_out[3]:5 *C 15.640 3.785 +*N chanx_left_out[3]:6 *C 15.640 4.715 +*N chanx_left_out[3]:7 *C 15.685 4.760 +*N chanx_left_out[3]:8 *C 20.858 4.760 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 chanx_left_out[3] 0.0001504579 +2 chanx_left_out[3]:2 0.0001504579 +3 chanx_left_out[3]:3 0.0007162886 +4 chanx_left_out[3]:4 0.0007162886 +5 chanx_left_out[3]:5 6.302822e-05 +6 chanx_left_out[3]:6 6.302822e-05 +7 chanx_left_out[3]:7 0.0003372675 +8 chanx_left_out[3]:8 0.0003372675 +9 chanx_left_out[3]:6 ropt_net_155:9 3.232437e-06 +10 chanx_left_out[3]:4 ropt_net_155:3 6.297257e-05 +11 chanx_left_out[3]:5 ropt_net_155:8 3.232437e-06 +12 chanx_left_out[3]:3 ropt_net_155:2 6.297257e-05 + +*RES +0 ropt_mt_inst_799:X chanx_left_out[3]:8 0.152 +1 chanx_left_out[3]:8 chanx_left_out[3]:7 0.004618304 +2 chanx_left_out[3]:7 chanx_left_out[3]:6 0.0045 +3 chanx_left_out[3]:6 chanx_left_out[3]:5 0.0008303572 +4 chanx_left_out[3]:4 chanx_left_out[3]:3 0.009776786 +5 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +6 chanx_left_out[3]:3 chanx_left_out[3]:2 0.0045 +7 chanx_left_out[3]:2 chanx_left_out[3] 0.002147322 + +*END + +*D_NET chanx_left_in[7] 0.02391247 //LENGTH 140.360 LUMPCC 0.01031523 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 8.160 +*I mux_bottom_ipin_11\/mux_l2_in_1_:A0 I *L 0.001631 *C 19.495 33.660 +*I mux_bottom_ipin_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 31.915 38.760 +*I FTB_8__7:A I *L 0.001776 *C 95.680 25.840 +*I mux_bottom_ipin_13\/mux_l1_in_2_:A1 I *L 0.00198 *C 90.525 36.380 +*N chanx_left_in[7]:5 *C 90.525 36.380 +*N chanx_left_in[7]:6 *C 90.620 36.335 +*N chanx_left_in[7]:7 *C 95.680 25.840 +*N chanx_left_in[7]:8 *C 95.680 25.885 +*N chanx_left_in[7]:9 *C 95.680 31.575 +*N chanx_left_in[7]:10 *C 95.635 31.620 +*N chanx_left_in[7]:11 *C 90.665 31.620 +*N chanx_left_in[7]:12 *C 90.620 31.665 +*N chanx_left_in[7]:13 *C 90.620 34.680 +*N chanx_left_in[7]:14 *C 90.613 34.680 +*N chanx_left_in[7]:15 *C 82.050 34.680 +*N chanx_left_in[7]:16 *C 32.200 34.680 +*N chanx_left_in[7]:17 *C 31.915 38.760 +*N chanx_left_in[7]:18 *C 32.200 38.760 +*N chanx_left_in[7]:19 *C 32.200 38.715 +*N chanx_left_in[7]:20 *C 32.200 35.418 +*N chanx_left_in[7]:21 *C 32.200 35.352 +*N chanx_left_in[7]:22 *C 19.328 35.360 +*N chanx_left_in[7]:23 *C 19.320 35.303 +*N chanx_left_in[7]:24 *C 19.495 33.660 +*N chanx_left_in[7]:25 *C 19.320 33.660 +*N chanx_left_in[7]:26 *C 19.320 33.660 +*N chanx_left_in[7]:27 *C 19.320 32.698 +*N chanx_left_in[7]:28 *C 19.312 32.640 +*N chanx_left_in[7]:29 *C 2.780 32.640 +*N chanx_left_in[7]:30 *C 2.760 32.633 +*N chanx_left_in[7]:31 *C 2.760 8.168 +*N chanx_left_in[7]:32 *C 2.740 8.160 + +*CAP +0 chanx_left_in[7] 0.0001753849 +1 mux_bottom_ipin_11\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_1_:A0 1e-06 +3 FTB_8__7:A 1e-06 +4 mux_bottom_ipin_13\/mux_l1_in_2_:A1 1e-06 +5 chanx_left_in[7]:5 3.314855e-05 +6 chanx_left_in[7]:6 0.0001035272 +7 chanx_left_in[7]:7 3.173172e-05 +8 chanx_left_in[7]:8 0.0003243124 +9 chanx_left_in[7]:9 0.0003243124 +10 chanx_left_in[7]:10 0.0003550564 +11 chanx_left_in[7]:11 0.0003550564 +12 chanx_left_in[7]:12 0.0001788576 +13 chanx_left_in[7]:13 0.0003173826 +14 chanx_left_in[7]:14 0.0003052051 +15 chanx_left_in[7]:15 0.002110464 +16 chanx_left_in[7]:16 0.001854559 +17 chanx_left_in[7]:17 5.622526e-05 +18 chanx_left_in[7]:18 6.06004e-05 +19 chanx_left_in[7]:19 0.0001950015 +20 chanx_left_in[7]:20 0.0001950015 +21 chanx_left_in[7]:21 0.0005975181 +22 chanx_left_in[7]:22 0.0005482197 +23 chanx_left_in[7]:23 0.0001060346 +24 chanx_left_in[7]:24 5.285041e-05 +25 chanx_left_in[7]:25 5.524786e-05 +26 chanx_left_in[7]:26 0.0002075675 +27 chanx_left_in[7]:27 6.778338e-05 +28 chanx_left_in[7]:28 0.000883494 +29 chanx_left_in[7]:29 0.000883494 +30 chanx_left_in[7]:30 0.001519909 +31 chanx_left_in[7]:31 0.001519909 +32 chanx_left_in[7]:32 0.0001753849 +33 chanx_left_in[7]:22 chanx_left_in[10] 0.0002480958 +34 chanx_left_in[7]:21 chanx_left_in[10]:26 0.0002480958 +35 chanx_left_in[7]:28 chanx_left_in[10]:26 9.670912e-05 +36 chanx_left_in[7]:29 chanx_left_in[10] 9.670912e-05 +37 chanx_left_in[7]:16 chanx_left_in[10] 0.001052718 +38 chanx_left_in[7]:16 chanx_left_in[10]:26 0.0003303195 +39 chanx_left_in[7]:15 chanx_left_in[10]:25 0.0003303195 +40 chanx_left_in[7]:15 chanx_left_in[10]:26 0.001052718 +41 chanx_left_in[7]:14 chanx_right_in[4]:39 0.0001777615 +42 chanx_left_in[7]:16 chanx_right_in[4]:32 0.0008340328 +43 chanx_left_in[7]:16 chanx_right_in[4]:38 0.000286994 +44 chanx_left_in[7]:15 chanx_right_in[4]:37 0.0008340328 +45 chanx_left_in[7]:15 chanx_right_in[4]:39 0.000286994 +46 chanx_left_in[7]:15 chanx_right_in[4]:38 0.0001777615 +47 chanx_left_in[7]:14 chanx_right_in[5]:29 0.0001205574 +48 chanx_left_in[7]:16 chanx_right_in[5]:28 0.0003245918 +49 chanx_left_in[7]:15 chanx_right_in[5]:28 0.0001205574 +50 chanx_left_in[7]:15 chanx_right_in[5]:29 0.0003245918 +51 chanx_left_in[7]:28 chanx_right_in[15]:15 0.0006669954 +52 chanx_left_in[7]:29 chanx_right_in[15]:14 0.0006669954 +53 chanx_left_in[7]:16 chanx_right_in[15]:29 1.99256e-05 +54 chanx_left_in[7]:16 chanx_right_in[15]:28 1.055983e-05 +55 chanx_left_in[7]:15 chanx_right_in[15]:8 1.99256e-05 +56 chanx_left_in[7]:15 chanx_right_in[15]:29 1.055983e-05 +57 chanx_left_in[7]:14 mux_tree_tapbuf_size8_2_sram[0]:10 0.0001474309 +58 chanx_left_in[7]:16 mux_tree_tapbuf_size8_2_sram[0]:11 0.0003193094 +59 chanx_left_in[7]:15 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001474309 +60 chanx_left_in[7]:15 mux_tree_tapbuf_size8_2_sram[0]:10 0.0003193094 +61 chanx_left_in[7]:22 mux_tree_tapbuf_size8_5_sram[3]:12 0.0002381049 +62 chanx_left_in[7]:20 mux_tree_tapbuf_size8_5_sram[3]:5 1.821059e-06 +63 chanx_left_in[7]:20 mux_tree_tapbuf_size8_5_sram[3]:7 4.006208e-06 +64 chanx_left_in[7]:21 mux_tree_tapbuf_size8_5_sram[3]:13 0.0002381049 +65 chanx_left_in[7]:21 mux_tree_tapbuf_size8_5_sram[3]:6 9.937158e-06 +66 chanx_left_in[7]:19 mux_tree_tapbuf_size8_5_sram[3]:14 4.006208e-06 +67 chanx_left_in[7]:19 mux_tree_tapbuf_size8_5_sram[3]:6 1.821059e-06 +68 chanx_left_in[7]:16 mux_tree_tapbuf_size8_5_sram[3]:5 9.937158e-06 +69 chanx_left_in[7]:16 mux_tree_tapbuf_size8_5_sram[3]:12 2.186807e-05 +70 chanx_left_in[7]:15 mux_tree_tapbuf_size8_5_sram[3]:13 2.186807e-05 +71 chanx_left_in[7]:30 ropt_net_165:8 0.0002458743 +72 chanx_left_in[7]:31 ropt_net_165:9 0.0002458743 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:32 0.0002365667 +1 chanx_left_in[7]:23 chanx_left_in[7]:22 0.00341 +2 chanx_left_in[7]:22 chanx_left_in[7]:21 0.002016692 +3 chanx_left_in[7]:5 mux_bottom_ipin_13\/mux_l1_in_2_:A1 0.152 +4 chanx_left_in[7]:6 chanx_left_in[7]:5 0.0045 +5 chanx_left_in[7]:20 chanx_left_in[7]:19 0.002944197 +6 chanx_left_in[7]:21 chanx_left_in[7]:20 0.00341 +7 chanx_left_in[7]:21 chanx_left_in[7]:16 0.0001053583 +8 chanx_left_in[7]:18 chanx_left_in[7]:17 0.0001548913 +9 chanx_left_in[7]:19 chanx_left_in[7]:18 0.0045 +10 chanx_left_in[7]:17 mux_bottom_ipin_3\/mux_l2_in_1_:A0 0.152 +11 chanx_left_in[7]:25 chanx_left_in[7]:24 9.51087e-05 +12 chanx_left_in[7]:26 chanx_left_in[7]:25 0.0045 +13 chanx_left_in[7]:26 chanx_left_in[7]:23 0.001466518 +14 chanx_left_in[7]:24 mux_bottom_ipin_11\/mux_l2_in_1_:A0 0.152 +15 chanx_left_in[7]:13 chanx_left_in[7]:12 0.002691964 +16 chanx_left_in[7]:13 chanx_left_in[7]:6 0.001477679 +17 chanx_left_in[7]:14 chanx_left_in[7]:13 0.00341 +18 chanx_left_in[7]:7 FTB_8__7:A 0.152 +19 chanx_left_in[7]:8 chanx_left_in[7]:7 0.0045 +20 chanx_left_in[7]:10 chanx_left_in[7]:9 0.0045 +21 chanx_left_in[7]:9 chanx_left_in[7]:8 0.005080357 +22 chanx_left_in[7]:11 chanx_left_in[7]:10 0.0044375 +23 chanx_left_in[7]:12 chanx_left_in[7]:11 0.0045 +24 chanx_left_in[7]:27 chanx_left_in[7]:26 0.0008593751 +25 chanx_left_in[7]:28 chanx_left_in[7]:27 0.00341 +26 chanx_left_in[7]:29 chanx_left_in[7]:28 0.002590092 +27 chanx_left_in[7]:30 chanx_left_in[7]:29 0.00341 +28 chanx_left_in[7]:32 chanx_left_in[7]:31 0.00341 +29 chanx_left_in[7]:31 chanx_left_in[7]:30 0.00383285 +30 chanx_left_in[7]:16 chanx_left_in[7]:15 0.007809833 +31 chanx_left_in[7]:15 chanx_left_in[7]:14 0.001341458 + +*END + +*D_NET chanx_right_in[6] 0.02104504 //LENGTH 150.165 LUMPCC 0.007433396 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 103.650 23.120 +*I ropt_mt_inst_727:A I *L 0.001766 *C 3.220 50.320 +*I mux_bottom_ipin_10\/mux_l2_in_2_:A1 I *L 0.00198 *C 20.340 23.460 +*I mux_bottom_ipin_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 38.180 20.060 +*I mux_bottom_ipin_12\/mux_l1_in_2_:A0 I *L 0.001631 *C 71.475 17.340 +*N chanx_right_in[6]:5 *C 71.438 17.340 +*N chanx_right_in[6]:6 *C 38.180 20.060 +*N chanx_right_in[6]:7 *C 20.303 23.460 +*N chanx_right_in[6]:8 *C 3.183 50.320 +*N chanx_right_in[6]:9 *C 2.345 50.320 +*N chanx_right_in[6]:10 *C 2.300 50.275 +*N chanx_right_in[6]:11 *C 2.300 23.505 +*N chanx_right_in[6]:12 *C 2.345 23.460 +*N chanx_right_in[6]:13 *C 5.980 23.460 +*N chanx_right_in[6]:14 *C 5.980 23.120 +*N chanx_right_in[6]:15 *C 6.900 23.120 +*N chanx_right_in[6]:16 *C 6.900 22.780 +*N chanx_right_in[6]:17 *C 19.780 22.780 +*N chanx_right_in[6]:18 *C 19.780 23.460 +*N chanx_right_in[6]:19 *C 19.780 23.415 +*N chanx_right_in[6]:20 *C 19.780 21.137 +*N chanx_right_in[6]:21 *C 19.788 21.080 +*N chanx_right_in[6]:22 *C 34.492 21.080 +*N chanx_right_in[6]:23 *C 34.500 21.023 +*N chanx_right_in[6]:24 *C 34.500 20.445 +*N chanx_right_in[6]:25 *C 34.545 20.400 +*N chanx_right_in[6]:26 *C 38.180 20.400 +*N chanx_right_in[6]:27 *C 52.855 20.400 +*N chanx_right_in[6]:28 *C 52.900 20.355 +*N chanx_right_in[6]:29 *C 52.900 17.045 +*N chanx_right_in[6]:30 *C 52.945 17.000 +*N chanx_right_in[6]:31 *C 63.940 17.000 +*N chanx_right_in[6]:32 *C 63.940 17.340 +*N chanx_right_in[6]:33 *C 70.840 17.340 +*N chanx_right_in[6]:34 *C 70.840 17.385 +*N chanx_right_in[6]:35 *C 70.840 19.663 +*N chanx_right_in[6]:36 *C 70.847 19.720 +*N chanx_right_in[6]:37 *C 94.293 19.720 +*N chanx_right_in[6]:38 *C 94.300 19.777 +*N chanx_right_in[6]:39 *C 94.300 23.062 +*N chanx_right_in[6]:40 *C 94.308 23.120 + +*CAP +0 chanx_right_in[6] 0.0002438172 +1 ropt_mt_inst_727:A 1e-06 +2 mux_bottom_ipin_10\/mux_l2_in_2_:A1 1e-06 +3 mux_bottom_ipin_2\/mux_l2_in_2_:A1 1e-06 +4 mux_bottom_ipin_12\/mux_l1_in_2_:A0 1e-06 +5 chanx_right_in[6]:5 3.817775e-05 +6 chanx_right_in[6]:6 5.76872e-05 +7 chanx_right_in[6]:7 6.664059e-05 +8 chanx_right_in[6]:8 6.534971e-05 +9 chanx_right_in[6]:9 6.534971e-05 +10 chanx_right_in[6]:10 0.001175478 +11 chanx_right_in[6]:11 0.001175478 +12 chanx_right_in[6]:12 0.0002195273 +13 chanx_right_in[6]:13 0.0002437879 +14 chanx_right_in[6]:14 9.27177e-05 +15 chanx_right_in[6]:15 9.627551e-05 +16 chanx_right_in[6]:16 0.0009179827 +17 chanx_right_in[6]:17 0.000939374 +18 chanx_right_in[6]:18 0.0001158503 +19 chanx_right_in[6]:19 9.677182e-05 +20 chanx_right_in[6]:20 9.677182e-05 +21 chanx_right_in[6]:21 0.0004097839 +22 chanx_right_in[6]:22 0.0004097839 +23 chanx_right_in[6]:23 5.514517e-05 +24 chanx_right_in[6]:24 5.514517e-05 +25 chanx_right_in[6]:25 0.0002833306 +26 chanx_right_in[6]:26 0.0007527372 +27 chanx_right_in[6]:27 0.0004410808 +28 chanx_right_in[6]:28 0.0002013847 +29 chanx_right_in[6]:29 0.0002013847 +30 chanx_right_in[6]:30 0.0007299072 +31 chanx_right_in[6]:31 0.0007563587 +32 chanx_right_in[6]:32 0.0003605434 +33 chanx_right_in[6]:33 0.0004043076 +34 chanx_right_in[6]:34 0.0001578217 +35 chanx_right_in[6]:35 0.0001578217 +36 chanx_right_in[6]:36 0.0009544899 +37 chanx_right_in[6]:37 0.0009544899 +38 chanx_right_in[6]:38 0.0001856334 +39 chanx_right_in[6]:39 0.0001856334 +40 chanx_right_in[6]:40 0.0002438172 +41 chanx_right_in[6]:27 chanx_left_in[14]:17 1.609264e-05 +42 chanx_right_in[6]:27 chanx_left_in[14]:18 5.405198e-06 +43 chanx_right_in[6]:7 chanx_left_in[14]:24 1.737713e-06 +44 chanx_right_in[6]:18 chanx_left_in[14]:23 1.737713e-06 +45 chanx_right_in[6]:19 chanx_left_in[14]:25 4.397908e-05 +46 chanx_right_in[6]:20 chanx_left_in[14]:26 4.397908e-05 +47 chanx_right_in[6]:21 chanx_left_in[14] 3.513008e-05 +48 chanx_right_in[6]:21 chanx_left_in[14]:27 0.0008003549 +49 chanx_right_in[6]:23 chanx_left_in[14]:21 5.988435e-06 +50 chanx_right_in[6]:22 chanx_left_in[14]:22 0.0008003549 +51 chanx_right_in[6]:22 chanx_left_in[14]:27 3.513008e-05 +52 chanx_right_in[6]:24 chanx_left_in[14]:22 5.988435e-06 +53 chanx_right_in[6]:16 chanx_left_in[14]:23 2.336528e-07 +54 chanx_right_in[6]:17 chanx_left_in[14]:24 2.336528e-07 +55 chanx_right_in[6]:26 chanx_left_in[14]:19 5.405198e-06 +56 chanx_right_in[6]:26 chanx_left_in[14]:21 1.609264e-05 +57 chanx_right_in[6]:5 chanx_left_in[16]:14 2.887031e-05 +58 chanx_right_in[6]:33 chanx_left_in[16]:14 0.0001593348 +59 chanx_right_in[6]:33 chanx_left_in[16]:15 0.0001129737 +60 chanx_right_in[6]:32 chanx_left_in[16]:15 0.0001593348 +61 chanx_right_in[6]:32 chanx_left_in[16]:16 8.410343e-05 +62 chanx_right_in[6]:19 chanx_right_in[2]:26 8.833927e-06 +63 chanx_right_in[6]:20 chanx_right_in[2]:25 8.833927e-06 +64 chanx_right_in[6]:21 chanx_right_in[2]:27 0.0003152411 +65 chanx_right_in[6]:22 chanx_right_in[2]:36 0.0003152411 +66 chanx_right_in[6] chanx_right_in[8] 0.0002360587 +67 chanx_right_in[6]:30 chanx_right_in[8]:17 8.283982e-06 +68 chanx_right_in[6]:38 chanx_right_in[8]:31 9.579406e-06 +69 chanx_right_in[6]:39 chanx_right_in[8]:30 9.579406e-06 +70 chanx_right_in[6]:40 chanx_right_in[8]:31 0.0002360587 +71 chanx_right_in[6]:16 chanx_right_in[8]:5 1.341284e-05 +72 chanx_right_in[6]:17 chanx_right_in[8]:4 1.341284e-05 +73 chanx_right_in[6]:31 chanx_right_in[8]:18 8.283982e-06 +74 chanx_right_in[6] chanx_right_in[10] 1.635541e-05 +75 chanx_right_in[6]:36 chanx_right_in[10]:27 0.0005449019 +76 chanx_right_in[6]:37 chanx_right_in[10]:28 0.0005449019 +77 chanx_right_in[6]:40 chanx_right_in[10]:31 1.635541e-05 +78 chanx_right_in[6] chanx_right_in[14] 2.568117e-06 +79 chanx_right_in[6] chanx_right_in[14]:33 0.0001208405 +80 chanx_right_in[6]:27 chanx_right_in[14]:29 1.609264e-05 +81 chanx_right_in[6]:27 chanx_right_in[14]:25 4.614717e-05 +82 chanx_right_in[6]:27 chanx_right_in[14]:23 0.000167586 +83 chanx_right_in[6]:40 chanx_right_in[14]:32 0.0001208405 +84 chanx_right_in[6]:40 chanx_right_in[14]:36 2.568117e-06 +85 chanx_right_in[6]:26 chanx_right_in[14]:26 0.000167586 +86 chanx_right_in[6]:26 chanx_right_in[14]:28 1.609264e-05 +87 chanx_right_in[6]:26 chanx_right_in[14]:24 4.614717e-05 +88 chanx_right_in[6]:11 prog_clk[0]:370 0.0002076947 +89 chanx_right_in[6]:11 prog_clk[0]:371 0.000363176 +90 chanx_right_in[6]:10 prog_clk[0]:367 0.0002076947 +91 chanx_right_in[6]:10 prog_clk[0]:370 0.000363176 +92 chanx_right_in[6]:19 prog_clk[0]:307 9.902294e-06 +93 chanx_right_in[6]:20 prog_clk[0]:308 9.902294e-06 +94 chanx_right_in[6]:34 prog_clk[0]:106 2.767178e-06 +95 chanx_right_in[6]:35 prog_clk[0]:84 2.767178e-06 +96 chanx_right_in[6]:36 prog_clk[0]:105 0.0001336128 +97 chanx_right_in[6]:37 prog_clk[0]:104 0.0001336128 +98 chanx_right_in[6]:27 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.891854e-05 +99 chanx_right_in[6]:26 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.891854e-05 +100 chanx_right_in[6]:29 optlc_net_126:20 2.306257e-06 +101 chanx_right_in[6]:27 optlc_net_126:17 0.0001931616 +102 chanx_right_in[6]:28 optlc_net_126:19 2.306257e-06 +103 chanx_right_in[6]:26 optlc_net_126:16 0.0001931616 +104 chanx_right_in[6]:12 ropt_net_171:6 2.381591e-05 +105 chanx_right_in[6]:13 ropt_net_171:7 2.381591e-05 +106 chanx_right_in[6]:14 ropt_net_171:6 9.288006e-06 +107 chanx_right_in[6]:15 ropt_net_171:7 9.288006e-06 +108 chanx_right_in[6]:16 ropt_net_171:6 1.492334e-05 +109 chanx_right_in[6]:17 ropt_net_171:7 1.492334e-05 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:40 0.001463658 +1 chanx_right_in[6]:12 chanx_right_in[6]:11 0.0045 +2 chanx_right_in[6]:11 chanx_right_in[6]:10 0.02390179 +3 chanx_right_in[6]:9 chanx_right_in[6]:8 0.0007477679 +4 chanx_right_in[6]:10 chanx_right_in[6]:9 0.0045 +5 chanx_right_in[6]:8 ropt_mt_inst_727:A 0.152 +6 chanx_right_in[6]:30 chanx_right_in[6]:29 0.0045 +7 chanx_right_in[6]:29 chanx_right_in[6]:28 0.002955357 +8 chanx_right_in[6]:27 chanx_right_in[6]:26 0.01310268 +9 chanx_right_in[6]:28 chanx_right_in[6]:27 0.0045 +10 chanx_right_in[6]:6 mux_bottom_ipin_2\/mux_l2_in_2_:A1 0.152 +11 chanx_right_in[6]:7 mux_bottom_ipin_10\/mux_l2_in_2_:A1 0.152 +12 chanx_right_in[6]:5 mux_bottom_ipin_12\/mux_l1_in_2_:A0 0.152 +13 chanx_right_in[6]:18 chanx_right_in[6]:17 0.0006071429 +14 chanx_right_in[6]:18 chanx_right_in[6]:7 0.0004665179 +15 chanx_right_in[6]:19 chanx_right_in[6]:18 0.0045 +16 chanx_right_in[6]:20 chanx_right_in[6]:19 0.002033482 +17 chanx_right_in[6]:21 chanx_right_in[6]:20 0.00341 +18 chanx_right_in[6]:23 chanx_right_in[6]:22 0.00341 +19 chanx_right_in[6]:22 chanx_right_in[6]:21 0.002303783 +20 chanx_right_in[6]:25 chanx_right_in[6]:24 0.0045 +21 chanx_right_in[6]:24 chanx_right_in[6]:23 0.000515625 +22 chanx_right_in[6]:33 chanx_right_in[6]:32 0.006160715 +23 chanx_right_in[6]:33 chanx_right_in[6]:5 0.0005334822 +24 chanx_right_in[6]:34 chanx_right_in[6]:33 0.0045 +25 chanx_right_in[6]:35 chanx_right_in[6]:34 0.002033482 +26 chanx_right_in[6]:36 chanx_right_in[6]:35 0.00341 +27 chanx_right_in[6]:38 chanx_right_in[6]:37 0.00341 +28 chanx_right_in[6]:37 chanx_right_in[6]:36 0.00367305 +29 chanx_right_in[6]:39 chanx_right_in[6]:38 0.002933036 +30 chanx_right_in[6]:40 chanx_right_in[6]:39 0.00341 +31 chanx_right_in[6]:13 chanx_right_in[6]:12 0.003245536 +32 chanx_right_in[6]:14 chanx_right_in[6]:13 0.0003035715 +33 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0008214285 +34 chanx_right_in[6]:16 chanx_right_in[6]:15 0.0003035715 +35 chanx_right_in[6]:17 chanx_right_in[6]:16 0.0115 +36 chanx_right_in[6]:26 chanx_right_in[6]:25 0.003245536 +37 chanx_right_in[6]:26 chanx_right_in[6]:6 0.0003035715 +38 chanx_right_in[6]:31 chanx_right_in[6]:30 0.009816965 +39 chanx_right_in[6]:32 chanx_right_in[6]:31 0.0003035715 + +*END + +*D_NET prog_clk[0] 0.09307794 //LENGTH 641.415 LUMPCC 0.02424063 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 3.220 1.290 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.570 20.400 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 3.025 36.720 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.625 50.320 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.625 53.040 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 7.625 63.920 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 14.985 66.640 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 23.725 66.640 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 25.565 69.360 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.085 63.920 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 16.410 50.320 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 17.285 47.600 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 20.505 44.880 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 3.485 44.880 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 7.625 14.960 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 21.425 25.840 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 20.505 28.560 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 26.945 36.720 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 29.245 42.160 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 28.325 31.280 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 48.565 31.280 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 58.685 42.160 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 59.605 44.880 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.505 55.760 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 74.325 58.480 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.995 63.920 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 76.220 66.640 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 68.805 47.600 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 74.325 50.320 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 89.045 47.600 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.045 50.320 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.045 55.760 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 89.045 63.920 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 89.045 69.360 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.985 36.720 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 52.245 36.720 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.065 31.280 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.685 34.000 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 39.825 47.600 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 43.505 53.040 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 41.205 63.920 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 49.025 66.640 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 55.465 69.360 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 64.205 69.360 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 38.905 55.760 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 43.505 36.720 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 42.125 39.440 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 26.945 14.960 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 25.565 20.400 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 16.410 14.960 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 36.145 14.960 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 44.425 17.680 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 49.485 14.960 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 58.685 25.840 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 61.445 20.400 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 60.065 12.240 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 68.805 14.960 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 81.685 17.680 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 83.985 34.000 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 85.365 25.840 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 88.980 28.560 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 70.645 31.280 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 71.105 36.720 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 69.265 39.440 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 73.865 9.520 +*N prog_clk[0]:65 *C 73.865 9.520 +*N prog_clk[0]:66 *C 73.600 9.520 +*N prog_clk[0]:67 *C 73.600 9.520 +*N prog_clk[0]:68 *C 73.593 9.520 +*N prog_clk[0]:69 *C 69.000 9.520 +*N prog_clk[0]:70 *C 69.265 39.440 +*N prog_clk[0]:71 *C 69.460 39.440 +*N prog_clk[0]:72 *C 69.460 39.395 +*N prog_clk[0]:73 *C 69.460 36.720 +*N prog_clk[0]:74 *C 71.105 36.720 +*N prog_clk[0]:75 *C 70.840 36.720 +*N prog_clk[0]:76 *C 70.840 36.720 +*N prog_clk[0]:77 *C 70.833 36.720 +*N prog_clk[0]:78 *C 69.928 36.720 +*N prog_clk[0]:79 *C 69.920 36.663 +*N prog_clk[0]:80 *C 70.608 31.280 +*N prog_clk[0]:81 *C 69.920 31.280 +*N prog_clk[0]:82 *C 69.920 31.620 +*N prog_clk[0]:83 *C 69.920 31.665 +*N prog_clk[0]:84 *C 69.460 31.620 +*N prog_clk[0]:85 *C 88.980 28.560 +*N prog_clk[0]:86 *C 88.780 28.560 +*N prog_clk[0]:87 *C 88.780 28.515 +*N prog_clk[0]:88 *C 88.780 25.898 +*N prog_clk[0]:89 *C 88.773 25.840 +*N prog_clk[0]:90 *C 85.365 25.840 +*N prog_clk[0]:91 *C 85.560 25.840 +*N prog_clk[0]:92 *C 85.560 25.840 +*N prog_clk[0]:93 *C 85.560 25.840 +*N prog_clk[0]:94 *C 83.985 34.000 +*N prog_clk[0]:95 *C 84.180 34.000 +*N prog_clk[0]:96 *C 84.180 33.955 +*N prog_clk[0]:97 *C 84.180 25.898 +*N prog_clk[0]:98 *C 84.180 25.840 +*N prog_clk[0]:99 *C 81.888 25.840 +*N prog_clk[0]:100 *C 81.880 25.783 +*N prog_clk[0]:101 *C 81.685 17.680 +*N prog_clk[0]:102 *C 81.880 17.680 +*N prog_clk[0]:103 *C 81.880 17.680 +*N prog_clk[0]:104 *C 81.873 17.680 +*N prog_clk[0]:105 *C 69.468 17.680 +*N prog_clk[0]:106 *C 69.460 17.738 +*N prog_clk[0]:107 *C 69.000 17.680 +*N prog_clk[0]:108 *C 68.805 14.960 +*N prog_clk[0]:109 *C 69.000 15.300 +*N prog_clk[0]:110 *C 69.000 15.300 +*N prog_clk[0]:111 *C 69.000 10.258 +*N prog_clk[0]:112 *C 69.000 10.193 +*N prog_clk[0]:113 *C 60.065 12.240 +*N prog_clk[0]:114 *C 60.260 12.240 +*N prog_clk[0]:115 *C 60.260 12.195 +*N prog_clk[0]:116 *C 60.260 10.258 +*N prog_clk[0]:117 *C 60.260 10.200 +*N prog_clk[0]:118 *C 61.445 20.400 +*N prog_clk[0]:119 *C 61.180 20.400 +*N prog_clk[0]:120 *C 61.180 20.400 +*N prog_clk[0]:121 *C 61.172 20.400 +*N prog_clk[0]:122 *C 58.685 25.840 +*N prog_clk[0]:123 *C 58.880 25.840 +*N prog_clk[0]:124 *C 58.880 25.795 +*N prog_clk[0]:125 *C 58.880 20.457 +*N prog_clk[0]:126 *C 58.888 20.400 +*N prog_clk[0]:127 *C 58.880 20.393 +*N prog_clk[0]:128 *C 58.880 10.208 +*N prog_clk[0]:129 *C 58.880 10.200 +*N prog_clk[0]:130 *C 49.485 14.960 +*N prog_clk[0]:131 *C 49.220 14.960 +*N prog_clk[0]:132 *C 49.220 14.915 +*N prog_clk[0]:133 *C 49.220 10.258 +*N prog_clk[0]:134 *C 49.220 10.200 +*N prog_clk[0]:135 *C 44.425 17.680 +*N prog_clk[0]:136 *C 44.160 17.680 +*N prog_clk[0]:137 *C 44.160 17.635 +*N prog_clk[0]:138 *C 44.160 10.258 +*N prog_clk[0]:139 *C 44.160 10.200 +*N prog_clk[0]:140 *C 36.145 14.960 +*N prog_clk[0]:141 *C 36.340 14.960 +*N prog_clk[0]:142 *C 36.340 14.915 +*N prog_clk[0]:143 *C 36.340 10.258 +*N prog_clk[0]:144 *C 36.340 10.200 +*N prog_clk[0]:145 *C 16.373 14.960 +*N prog_clk[0]:146 *C 15.685 14.960 +*N prog_clk[0]:147 *C 15.640 14.960 +*N prog_clk[0]:148 *C 25.565 20.400 +*N prog_clk[0]:149 *C 25.760 20.400 +*N prog_clk[0]:150 *C 25.760 20.355 +*N prog_clk[0]:151 *C 26.908 14.960 +*N prog_clk[0]:152 *C 25.760 14.960 +*N prog_clk[0]:153 *C 25.760 15.300 +*N prog_clk[0]:154 *C 25.760 15.345 +*N prog_clk[0]:155 *C 25.760 14.960 +*N prog_clk[0]:156 *C 25.753 14.960 +*N prog_clk[0]:157 *C 42.125 39.440 +*N prog_clk[0]:158 *C 41.860 39.440 +*N prog_clk[0]:159 *C 41.860 39.395 +*N prog_clk[0]:160 *C 43.468 36.720 +*N prog_clk[0]:161 *C 41.905 36.720 +*N prog_clk[0]:162 *C 41.860 36.720 +*N prog_clk[0]:163 *C 41.860 35.418 +*N prog_clk[0]:164 *C 41.852 35.360 +*N prog_clk[0]:165 *C 38.905 55.760 +*N prog_clk[0]:166 *C 39.100 55.760 +*N prog_clk[0]:167 *C 39.100 55.715 +*N prog_clk[0]:168 *C 39.100 53.720 +*N prog_clk[0]:169 *C 64.168 69.360 +*N prog_clk[0]:170 *C 63.525 69.360 +*N prog_clk[0]:171 *C 63.480 69.360 +*N prog_clk[0]:172 *C 63.473 69.360 +*N prog_clk[0]:173 *C 55.668 69.360 +*N prog_clk[0]:174 *C 55.465 69.360 +*N prog_clk[0]:175 *C 55.660 69.360 +*N prog_clk[0]:176 *C 55.660 69.360 +*N prog_clk[0]:177 *C 55.660 66.698 +*N prog_clk[0]:178 *C 55.653 66.640 +*N prog_clk[0]:179 *C 49.025 66.640 +*N prog_clk[0]:180 *C 49.220 66.640 +*N prog_clk[0]:181 *C 49.220 66.640 +*N prog_clk[0]:182 *C 49.220 66.640 +*N prog_clk[0]:183 *C 41.867 66.640 +*N prog_clk[0]:184 *C 41.860 66.583 +*N prog_clk[0]:185 *C 41.205 63.920 +*N prog_clk[0]:186 *C 41.400 64.260 +*N prog_clk[0]:187 *C 41.815 64.260 +*N prog_clk[0]:188 *C 41.860 64.260 +*N prog_clk[0]:189 *C 43.468 53.040 +*N prog_clk[0]:190 *C 41.905 53.040 +*N prog_clk[0]:191 *C 41.860 53.085 +*N prog_clk[0]:192 *C 41.860 53.720 +*N prog_clk[0]:193 *C 41.852 53.720 +*N prog_clk[0]:194 *C 40.028 53.720 +*N prog_clk[0]:195 *C 40.020 53.663 +*N prog_clk[0]:196 *C 39.825 47.600 +*N prog_clk[0]:197 *C 40.020 47.940 +*N prog_clk[0]:198 *C 40.020 47.940 +*N prog_clk[0]:199 *C 40.020 35.418 +*N prog_clk[0]:200 *C 40.020 35.360 +*N prog_clk[0]:201 *C 36.348 35.360 +*N prog_clk[0]:202 *C 36.340 35.303 +*N prog_clk[0]:203 *C 35.685 34.000 +*N prog_clk[0]:204 *C 35.880 33.660 +*N prog_clk[0]:205 *C 36.295 33.660 +*N prog_clk[0]:206 *C 36.340 33.660 +*N prog_clk[0]:207 *C 37.028 31.280 +*N prog_clk[0]:208 *C 36.385 31.280 +*N prog_clk[0]:209 *C 52.245 36.720 +*N prog_clk[0]:210 *C 51.980 36.720 +*N prog_clk[0]:211 *C 60.948 36.720 +*N prog_clk[0]:212 *C 60.305 36.720 +*N prog_clk[0]:213 *C 60.260 36.720 +*N prog_clk[0]:214 *C 60.253 36.720 +*N prog_clk[0]:215 *C 89.045 69.360 +*N prog_clk[0]:216 *C 88.780 69.360 +*N prog_clk[0]:217 *C 88.780 69.315 +*N prog_clk[0]:218 *C 89.045 63.920 +*N prog_clk[0]:219 *C 88.780 63.920 +*N prog_clk[0]:220 *C 88.780 63.920 +*N prog_clk[0]:221 *C 89.045 55.760 +*N prog_clk[0]:222 *C 88.780 55.420 +*N prog_clk[0]:223 *C 88.780 55.420 +*N prog_clk[0]:224 *C 89.045 50.320 +*N prog_clk[0]:225 *C 88.780 50.320 +*N prog_clk[0]:226 *C 88.780 50.320 +*N prog_clk[0]:227 *C 89.045 47.600 +*N prog_clk[0]:228 *C 88.780 47.940 +*N prog_clk[0]:229 *C 88.780 47.985 +*N prog_clk[0]:230 *C 88.780 47.600 +*N prog_clk[0]:231 *C 88.773 47.600 +*N prog_clk[0]:232 *C 74.325 50.320 +*N prog_clk[0]:233 *C 74.520 50.320 +*N prog_clk[0]:234 *C 74.520 50.275 +*N prog_clk[0]:235 *C 74.520 47.657 +*N prog_clk[0]:236 *C 74.520 47.600 +*N prog_clk[0]:237 *C 68.805 47.600 +*N prog_clk[0]:238 *C 69.000 47.600 +*N prog_clk[0]:239 *C 69.000 47.600 +*N prog_clk[0]:240 *C 69.000 47.600 +*N prog_clk[0]:241 *C 76.183 66.640 +*N prog_clk[0]:242 *C 72.725 66.640 +*N prog_clk[0]:243 *C 72.680 66.595 +*N prog_clk[0]:244 *C 71.995 63.920 +*N prog_clk[0]:245 *C 72.220 63.920 +*N prog_clk[0]:246 *C 72.220 63.920 +*N prog_clk[0]:247 *C 72.680 63.920 +*N prog_clk[0]:248 *C 74.288 58.480 +*N prog_clk[0]:249 *C 73.645 58.480 +*N prog_clk[0]:250 *C 73.600 58.480 +*N prog_clk[0]:251 *C 72.680 58.480 +*N prog_clk[0]:252 *C 72.672 58.480 +*N prog_clk[0]:253 *C 66.248 58.480 +*N prog_clk[0]:254 *C 66.240 58.422 +*N prog_clk[0]:255 *C 66.505 55.760 +*N prog_clk[0]:256 *C 66.240 55.420 +*N prog_clk[0]:257 *C 66.240 55.420 +*N prog_clk[0]:258 *C 66.240 47.657 +*N prog_clk[0]:259 *C 66.240 47.600 +*N prog_clk[0]:260 *C 58.428 47.600 +*N prog_clk[0]:261 *C 58.420 47.543 +*N prog_clk[0]:262 *C 59.568 44.880 +*N prog_clk[0]:263 *C 58.420 44.880 +*N prog_clk[0]:264 *C 58.420 44.540 +*N prog_clk[0]:265 *C 58.420 44.540 +*N prog_clk[0]:266 *C 58.685 42.160 +*N prog_clk[0]:267 *C 58.420 42.500 +*N prog_clk[0]:268 *C 58.420 42.500 +*N prog_clk[0]:269 *C 58.420 36.778 +*N prog_clk[0]:270 *C 58.420 36.720 +*N prog_clk[0]:271 *C 51.988 36.720 +*N prog_clk[0]:272 *C 51.980 36.720 +*N prog_clk[0]:273 *C 51.980 31.338 +*N prog_clk[0]:274 *C 51.973 31.280 +*N prog_clk[0]:275 *C 48.565 31.280 +*N prog_clk[0]:276 *C 48.300 31.280 +*N prog_clk[0]:277 *C 48.300 31.280 +*N prog_clk[0]:278 *C 48.300 31.280 +*N prog_clk[0]:279 *C 36.348 31.280 +*N prog_clk[0]:280 *C 36.340 31.280 +*N prog_clk[0]:281 *C 36.340 29.978 +*N prog_clk[0]:282 *C 36.333 29.920 +*N prog_clk[0]:283 *C 28.325 31.280 +*N prog_clk[0]:284 *C 28.520 31.280 +*N prog_clk[0]:285 *C 28.520 31.235 +*N prog_clk[0]:286 *C 28.520 29.978 +*N prog_clk[0]:287 *C 28.520 29.920 +*N prog_clk[0]:288 *C 29.208 42.160 +*N prog_clk[0]:289 *C 28.565 42.160 +*N prog_clk[0]:290 *C 28.520 42.160 +*N prog_clk[0]:291 *C 28.513 42.160 +*N prog_clk[0]:292 *C 26.688 42.160 +*N prog_clk[0]:293 *C 26.680 42.102 +*N prog_clk[0]:294 *C 26.945 36.720 +*N prog_clk[0]:295 *C 26.680 37.060 +*N prog_clk[0]:296 *C 26.680 37.060 +*N prog_clk[0]:297 *C 26.680 29.978 +*N prog_clk[0]:298 *C 26.680 29.920 +*N prog_clk[0]:299 *C 21.168 29.920 +*N prog_clk[0]:300 *C 21.160 29.863 +*N prog_clk[0]:301 *C 20.505 28.560 +*N prog_clk[0]:302 *C 20.700 28.220 +*N prog_clk[0]:303 *C 21.115 28.220 +*N prog_clk[0]:304 *C 21.160 28.220 +*N prog_clk[0]:305 *C 21.425 25.840 +*N prog_clk[0]:306 *C 21.160 26.180 +*N prog_clk[0]:307 *C 21.160 26.180 +*N prog_clk[0]:308 *C 21.160 15.018 +*N prog_clk[0]:309 *C 21.160 14.960 +*N prog_clk[0]:310 *C 16.108 14.960 +*N prog_clk[0]:311 *C 16.100 14.902 +*N prog_clk[0]:312 *C 16.100 10.258 +*N prog_clk[0]:313 *C 16.100 10.200 +*N prog_clk[0]:314 *C 7.588 14.960 +*N prog_clk[0]:315 *C 5.565 14.960 +*N prog_clk[0]:316 *C 5.520 14.960 +*N prog_clk[0]:317 *C 3.448 44.880 +*N prog_clk[0]:318 *C 2.805 44.880 +*N prog_clk[0]:319 *C 20.505 44.880 +*N prog_clk[0]:320 *C 20.240 44.880 +*N prog_clk[0]:321 *C 20.240 44.880 +*N prog_clk[0]:322 *C 20.233 44.880 +*N prog_clk[0]:323 *C 17.285 47.600 +*N prog_clk[0]:324 *C 17.480 47.600 +*N prog_clk[0]:325 *C 17.480 47.555 +*N prog_clk[0]:326 *C 17.480 44.938 +*N prog_clk[0]:327 *C 17.480 44.880 +*N prog_clk[0]:328 *C 16.373 50.320 +*N prog_clk[0]:329 *C 15.328 50.320 +*N prog_clk[0]:330 *C 15.180 50.275 +*N prog_clk[0]:331 *C 15.180 44.938 +*N prog_clk[0]:332 *C 15.180 44.880 +*N prog_clk[0]:333 *C 31.048 63.920 +*N prog_clk[0]:334 *C 30.405 63.920 +*N prog_clk[0]:335 *C 30.360 63.920 +*N prog_clk[0]:336 *C 30.353 63.920 +*N prog_clk[0]:337 *C 23.000 63.920 +*N prog_clk[0]:338 *C 25.527 69.360 +*N prog_clk[0]:339 *C 23.045 69.360 +*N prog_clk[0]:340 *C 23.000 69.315 +*N prog_clk[0]:341 *C 23.688 66.640 +*N prog_clk[0]:342 *C 22.978 66.640 +*N prog_clk[0]:343 *C 23.000 66.300 +*N prog_clk[0]:344 *C 23.000 66.300 +*N prog_clk[0]:345 *C 23.000 64.657 +*N prog_clk[0]:346 *C 23.000 64.593 +*N prog_clk[0]:347 *C 14.948 66.640 +*N prog_clk[0]:348 *C 13.845 66.640 +*N prog_clk[0]:349 *C 13.800 66.595 +*N prog_clk[0]:350 *C 13.800 64.657 +*N prog_clk[0]:351 *C 13.800 64.600 +*N prog_clk[0]:352 *C 6.448 64.600 +*N prog_clk[0]:353 *C 6.440 64.543 +*N prog_clk[0]:354 *C 7.588 63.920 +*N prog_clk[0]:355 *C 6.485 63.920 +*N prog_clk[0]:356 *C 6.440 63.920 +*N prog_clk[0]:357 *C 7.588 53.040 +*N prog_clk[0]:358 *C 6.440 53.040 +*N prog_clk[0]:359 *C 6.440 53.380 +*N prog_clk[0]:360 *C 6.440 53.380 +*N prog_clk[0]:361 *C 7.588 50.320 +*N prog_clk[0]:362 *C 6.585 50.320 +*N prog_clk[0]:363 *C 6.440 50.320 +*N prog_clk[0]:364 *C 6.440 44.938 +*N prog_clk[0]:365 *C 6.440 44.880 +*N prog_clk[0]:366 *C 2.768 44.880 +*N prog_clk[0]:367 *C 2.760 44.880 +*N prog_clk[0]:368 *C 3.025 36.720 +*N prog_clk[0]:369 *C 2.760 37.060 +*N prog_clk[0]:370 *C 2.760 37.060 +*N prog_clk[0]:371 *C 2.760 20.755 +*N prog_clk[0]:372 *C 2.805 20.400 +*N prog_clk[0]:373 *C 7.533 20.400 +*N prog_clk[0]:374 *C 5.105 20.400 +*N prog_clk[0]:375 *C 5.060 20.355 +*N prog_clk[0]:376 *C 5.060 14.960 +*N prog_clk[0]:377 *C 5.060 10.258 +*N prog_clk[0]:378 *C 5.060 10.200 +*N prog_clk[0]:379 *C 3.228 10.200 +*N prog_clk[0]:380 *C 3.220 10.143 + +*CAP +0 prog_clk[0] 0.0004771529 +1 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +2 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +3 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +4 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +6 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +7 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +8 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +9 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +10 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +11 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +12 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +13 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +14 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +15 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +16 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +18 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +19 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +21 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +22 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +23 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +24 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +25 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +27 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +28 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +29 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +30 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +32 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +33 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +34 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +35 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +37 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +39 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +40 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +41 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +42 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +43 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +44 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +46 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +47 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +48 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +49 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +50 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +51 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +52 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +54 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +55 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +56 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +57 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +58 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +59 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +60 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +61 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +63 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +64 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +65 prog_clk[0]:65 6.297472e-05 +66 prog_clk[0]:66 6.236747e-05 +67 prog_clk[0]:67 3.522721e-05 +68 prog_clk[0]:68 0.0002157444 +69 prog_clk[0]:69 0.000263215 +70 prog_clk[0]:70 6.128844e-05 +71 prog_clk[0]:71 6.194298e-05 +72 prog_clk[0]:72 0.0001368601 +73 prog_clk[0]:73 0.0001692992 +74 prog_clk[0]:74 5.128233e-05 +75 prog_clk[0]:75 5.522513e-05 +76 prog_clk[0]:76 3.335686e-05 +77 prog_clk[0]:77 3.721807e-05 +78 prog_clk[0]:78 3.721807e-05 +79 prog_clk[0]:79 0.0002757674 +80 prog_clk[0]:80 5.294716e-05 +81 prog_clk[0]:81 8.418727e-05 +82 prog_clk[0]:82 7.203651e-05 +83 prog_clk[0]:83 0.0002691159 +84 prog_clk[0]:84 0.000783888 +85 prog_clk[0]:85 5.748155e-05 +86 prog_clk[0]:86 5.808719e-05 +87 prog_clk[0]:87 0.0001799132 +88 prog_clk[0]:88 0.0001799132 +89 prog_clk[0]:89 0.0001544477 +90 prog_clk[0]:90 6.153977e-05 +91 prog_clk[0]:91 6.337198e-05 +92 prog_clk[0]:92 3.678923e-05 +93 prog_clk[0]:93 0.0002150576 +94 prog_clk[0]:94 6.480201e-05 +95 prog_clk[0]:95 6.207919e-05 +96 prog_clk[0]:96 0.0003307667 +97 prog_clk[0]:97 0.0003307667 +98 prog_clk[0]:98 0.000166904 +99 prog_clk[0]:99 0.0001062941 +100 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prog_clk[0]:277 3.985411e-05 +278 prog_clk[0]:278 0.0006342643 +279 prog_clk[0]:279 0.0004915342 +280 prog_clk[0]:280 0.0002640738 +281 prog_clk[0]:281 8.647672e-05 +282 prog_clk[0]:282 0.0001693065 +283 prog_clk[0]:283 5.015445e-05 +284 prog_clk[0]:284 5.654054e-05 +285 prog_clk[0]:285 9.95751e-05 +286 prog_clk[0]:286 9.95751e-05 +287 prog_clk[0]:287 0.0002150144 +288 prog_clk[0]:288 6.619448e-05 +289 prog_clk[0]:289 6.619448e-05 +290 prog_clk[0]:290 3.737096e-05 +291 prog_clk[0]:291 0.000219767 +292 prog_clk[0]:292 0.000219767 +293 prog_clk[0]:293 0.0003367784 +294 prog_clk[0]:294 6.488142e-05 +295 prog_clk[0]:295 7.187157e-05 +296 prog_clk[0]:296 0.0008000295 +297 prog_clk[0]:297 0.000426219 +298 prog_clk[0]:298 0.0001692893 +299 prog_clk[0]:299 0.0001235815 +300 prog_clk[0]:300 0.00010885 +301 prog_clk[0]:301 7.500053e-05 +302 prog_clk[0]:302 8.538436e-05 +303 prog_clk[0]:303 5.436458e-05 +304 prog_clk[0]:304 0.000259989 +305 prog_clk[0]:305 7.115174e-05 +306 prog_clk[0]:306 6.86195e-05 +307 prog_clk[0]:307 0.0006886668 +308 prog_clk[0]:308 0.000538742 +309 prog_clk[0]:309 0.0003789261 +310 prog_clk[0]:310 0.0001970302 +311 prog_clk[0]:311 0.0002773257 +312 prog_clk[0]:312 0.0002370807 +313 prog_clk[0]:313 0.001210158 +314 prog_clk[0]:314 0.0001309918 +315 prog_clk[0]:315 0.0001309918 +316 prog_clk[0]:316 5.710117e-05 +317 prog_clk[0]:317 5.808951e-05 +318 prog_clk[0]:318 5.808951e-05 +319 prog_clk[0]:319 5.37814e-05 +320 prog_clk[0]:320 5.599537e-05 +321 prog_clk[0]:321 4.181468e-05 +322 prog_clk[0]:322 0.0001936997 +323 prog_clk[0]:323 5.368417e-05 +324 prog_clk[0]:324 5.384567e-05 +325 prog_clk[0]:325 0.0001177105 +326 prog_clk[0]:326 0.0001177105 +327 prog_clk[0]:327 0.0003379547 +328 prog_clk[0]:328 0.0001277168 +329 prog_clk[0]:329 0.0001277168 +330 prog_clk[0]:330 0.0003111137 +331 prog_clk[0]:331 0.0003111137 +332 prog_clk[0]:332 0.0006198221 +333 prog_clk[0]:333 5.746505e-05 +334 prog_clk[0]:334 5.746505e-05 +335 prog_clk[0]:335 3.69319e-05 +336 prog_clk[0]:336 0.0003371258 +337 prog_clk[0]:337 0.0003936905 +338 prog_clk[0]:338 0.0001879473 +339 prog_clk[0]:339 0.0001879473 +340 prog_clk[0]:340 0.0001830193 +341 prog_clk[0]:341 7.58963e-05 +342 prog_clk[0]:342 0.0001095716 +343 prog_clk[0]:343 7.155031e-05 +344 prog_clk[0]:344 0.0003206661 +345 prog_clk[0]:345 0.0001036342 +346 prog_clk[0]:346 0.0003767368 +347 prog_clk[0]:347 0.0001043147 +348 prog_clk[0]:348 0.0001043147 +349 prog_clk[0]:349 0.0001074835 +350 prog_clk[0]:350 0.0001074835 +351 prog_clk[0]:351 0.0006004085 +352 prog_clk[0]:352 0.0002802365 +353 prog_clk[0]:353 4.909174e-05 +354 prog_clk[0]:354 0.000101051 +355 prog_clk[0]:355 0.000101051 +356 prog_clk[0]:356 0.0005739277 +357 prog_clk[0]:357 9.133665e-05 +358 prog_clk[0]:358 0.0001226107 +359 prog_clk[0]:359 6.788574e-05 +360 prog_clk[0]:360 0.0006755285 +361 prog_clk[0]:361 7.027754e-05 +362 prog_clk[0]:362 7.027754e-05 +363 prog_clk[0]:363 0.0004592248 +364 prog_clk[0]:364 0.0002751932 +365 prog_clk[0]:365 0.0007055279 +366 prog_clk[0]:366 0.0002299609 +367 prog_clk[0]:367 0.0003200184 +368 prog_clk[0]:368 6.202565e-05 +369 prog_clk[0]:369 6.217192e-05 +370 prog_clk[0]:370 0.0009663823 +371 prog_clk[0]:371 0.0006824819 +372 prog_clk[0]:372 0.0001263969 +373 prog_clk[0]:373 0.0001853774 +374 prog_clk[0]:374 0.0001853774 +375 prog_clk[0]:375 0.0003642092 +376 prog_clk[0]:376 0.0005417032 +377 prog_clk[0]:377 0.000251478 +378 prog_clk[0]:378 0.0004360688 +379 prog_clk[0]:379 0.00010789 +380 prog_clk[0]:380 0.0004771529 +381 prog_clk[0]:332 chanx_left_in[3] 1.735274e-05 +382 prog_clk[0]:332 chanx_left_in[3]:66 0.0001026419 +383 prog_clk[0]:194 chanx_left_in[3]:49 0.0001204219 +384 prog_clk[0]:193 chanx_left_in[3]:48 0.0001204219 +385 prog_clk[0]:366 chanx_left_in[3] 3.644382e-05 +386 prog_clk[0]:258 chanx_left_in[3]:29 4.244976e-05 +387 prog_clk[0]:167 chanx_left_in[3]:53 6.318709e-07 +388 prog_clk[0]:167 chanx_left_in[3]:54 6.136087e-07 +389 prog_clk[0]:257 chanx_left_in[3]:30 4.244976e-05 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chanx_left_in[12]:27 0.0003094592 +409 prog_clk[0]:298 chanx_left_in[12]:22 0.0003094592 +410 prog_clk[0]:298 chanx_left_in[12]:27 9.844783e-05 +411 prog_clk[0]:251 chanx_left_in[12]:20 1.574219e-06 +412 prog_clk[0]:106 chanx_left_in[12]:20 2.268103e-06 +413 prog_clk[0]:274 chanx_left_in[12]:22 0.0002150278 +414 prog_clk[0]:217 chanx_left_in[12]:15 4.17916e-06 +415 prog_clk[0]:279 chanx_left_in[12]:27 0.0006700828 +416 prog_clk[0]:79 chanx_left_in[12]:19 3.11381e-05 +417 prog_clk[0]:72 chanx_left_in[12]:19 7.039464e-06 +418 prog_clk[0]:287 chanx_left_in[12]:22 9.844783e-05 +419 prog_clk[0]:287 chanx_left_in[12]:27 0.000436687 +420 prog_clk[0]:278 chanx_left_in[12]:22 0.0006700828 +421 prog_clk[0]:278 chanx_left_in[12]:27 0.0002150278 +422 prog_clk[0]:235 chanx_left_in[12]:20 4.64312e-07 +423 prog_clk[0]:234 chanx_left_in[12]:19 4.64312e-07 +424 prog_clk[0]:220 chanx_left_in[12]:16 4.17916e-06 +425 prog_clk[0]:83 chanx_left_in[12]:20 3.11381e-05 +426 prog_clk[0]:83 chanx_left_in[12]:21 5.005284e-06 +427 prog_clk[0]:84 chanx_left_in[12]:19 2.268103e-06 +428 prog_clk[0]:84 chanx_left_in[12]:22 5.005284e-06 +429 prog_clk[0]:73 chanx_left_in[12]:20 7.039464e-06 +430 prog_clk[0]:247 chanx_left_in[12]:19 1.574219e-06 +431 prog_clk[0]:252 chanx_left_in[13]:13 0.0003724089 +432 prog_clk[0]:253 chanx_left_in[13]:14 0.0003724089 +433 prog_clk[0]:313 chanx_left_in[16]:19 2.04679e-06 +434 prog_clk[0]:313 chanx_left_in[16]:20 2.434743e-06 +435 prog_clk[0]:313 chanx_left_in[16]:21 6.34125e-06 +436 prog_clk[0]:310 chanx_left_in[16]:20 0.0002898598 +437 prog_clk[0]:156 chanx_left_in[16]:19 0.0002680539 +438 prog_clk[0]:309 chanx_left_in[16]:19 0.0002898598 +439 prog_clk[0]:309 chanx_left_in[16]:20 0.0002680539 +440 prog_clk[0]:378 chanx_left_in[16] 6.34125e-06 +441 prog_clk[0]:378 chanx_left_in[16]:20 2.04679e-06 +442 prog_clk[0]:378 chanx_left_in[16]:21 1.558809e-06 +443 prog_clk[0]:144 chanx_left_in[16]:19 2.434743e-06 +444 prog_clk[0]:379 chanx_left_in[16] 1.558809e-06 +445 prog_clk[0]:332 chanx_left_in[17]:28 2.367839e-07 +446 prog_clk[0]:346 chanx_left_in[17]:24 0.0001964125 +447 prog_clk[0]:351 chanx_left_in[17]:24 0.0001315331 +448 prog_clk[0]:351 chanx_left_in[17]:25 0.0001964125 +449 prog_clk[0]:366 chanx_left_in[17] 2.442613e-06 +450 prog_clk[0]:352 chanx_left_in[17]:25 0.0001315331 +451 prog_clk[0]:223 chanx_left_in[17]:10 1.011207e-06 +452 prog_clk[0]:223 chanx_left_in[17]:13 9.384105e-07 +453 prog_clk[0]:336 chanx_left_in[17]:24 0.0004167451 +454 prog_clk[0]:173 chanx_left_in[17]:16 1.736545e-06 +455 prog_clk[0]:172 chanx_left_in[17]:15 1.736545e-06 +456 prog_clk[0]:226 chanx_left_in[17]:10 9.384105e-07 +457 prog_clk[0]:220 chanx_left_in[17]:13 1.011207e-06 +458 prog_clk[0]:365 chanx_left_in[17] 2.367839e-07 +459 prog_clk[0]:365 chanx_left_in[17]:28 2.442613e-06 +460 prog_clk[0]:337 chanx_left_in[17]:25 0.0004167451 +461 prog_clk[0]:272 chanx_left_in[18]:34 1.087196e-05 +462 prog_clk[0]:282 chanx_left_in[18]:36 0.000436687 +463 prog_clk[0]:299 chanx_left_in[18]:37 0.0003094592 +464 prog_clk[0]:298 chanx_left_in[18]:36 0.0003094592 +465 prog_clk[0]:298 chanx_left_in[18]:37 9.844783e-05 +466 prog_clk[0]:273 chanx_left_in[18]:35 1.087196e-05 +467 prog_clk[0]:287 chanx_left_in[18]:36 9.844783e-05 +468 prog_clk[0]:287 chanx_left_in[18]:37 0.000436687 +469 prog_clk[0]:83 chanx_left_in[18]:29 5.005284e-06 +470 prog_clk[0]:84 chanx_left_in[18]:30 5.005284e-06 +471 prog_clk[0]:312 chanx_right_in[3]:20 1.359118e-06 +472 prog_clk[0]:194 chanx_right_in[3]:44 1.166558e-06 +473 prog_clk[0]:193 chanx_right_in[3]:45 1.166558e-06 +474 prog_clk[0]:311 chanx_right_in[3]:21 1.359118e-06 +475 prog_clk[0]:231 chanx_right_in[3]:60 0.0001470093 +476 prog_clk[0]:231 chanx_right_in[3]:61 2.334094e-05 +477 prog_clk[0]:260 chanx_right_in[3]:51 2.688166e-05 +478 prog_clk[0]:260 chanx_right_in[3]:56 1.733491e-05 +479 prog_clk[0]:258 chanx_right_in[3]:54 5.116514e-06 +480 prog_clk[0]:259 chanx_right_in[3]:56 6.421005e-05 +481 prog_clk[0]:259 chanx_right_in[3]:60 1.733491e-05 +482 prog_clk[0]:240 chanx_right_in[3]:56 7.524237e-05 +483 prog_clk[0]:240 chanx_right_in[3]:60 3.732838e-05 +484 prog_clk[0]:236 chanx_right_in[3]:56 0.0001470093 +485 prog_clk[0]:236 chanx_right_in[3]:60 9.85833e-05 +486 prog_clk[0]:257 chanx_right_in[3]:55 5.116514e-06 +487 prog_clk[0]:272 chanx_right_in[4]:31 2.93725e-06 +488 prog_clk[0]:271 chanx_right_in[4]:32 0.0001449644 +489 prog_clk[0]:346 chanx_right_in[4]:12 1.066482e-05 +490 prog_clk[0]:349 chanx_right_in[4]:9 2.536302e-05 +491 prog_clk[0]:350 chanx_right_in[4]:10 2.536302e-05 +492 prog_clk[0]:351 chanx_right_in[4]:11 1.066482e-05 +493 prog_clk[0]:351 chanx_right_in[4]:12 8.328015e-06 +494 prog_clk[0]:352 chanx_right_in[4]:11 8.328015e-06 +495 prog_clk[0]:270 chanx_right_in[4]:32 4.039907e-05 +496 prog_clk[0]:270 chanx_right_in[4]:37 0.0001449644 +497 prog_clk[0]:273 chanx_right_in[4]:30 2.93725e-06 +498 prog_clk[0]:79 chanx_right_in[4]:36 4.573759e-06 +499 prog_clk[0]:79 chanx_right_in[4]:38 8.27439e-06 +500 prog_clk[0]:78 chanx_right_in[4]:38 7.170039e-05 +501 prog_clk[0]:77 chanx_right_in[4]:39 7.170039e-05 +502 prog_clk[0]:214 chanx_right_in[4]:37 4.039907e-05 +503 prog_clk[0]:83 chanx_right_in[4]:35 4.573759e-06 +504 prog_clk[0]:83 chanx_right_in[4]:37 8.27439e-06 +505 prog_clk[0]:367 chanx_right_in[6]:10 0.0002076947 +506 prog_clk[0]:104 chanx_right_in[6]:37 0.0001336128 +507 prog_clk[0]:106 chanx_right_in[6]:34 2.767178e-06 +508 prog_clk[0]:105 chanx_right_in[6]:36 0.0001336128 +509 prog_clk[0]:308 chanx_right_in[6]:20 9.902294e-06 +510 prog_clk[0]:370 chanx_right_in[6]:10 0.000363176 +511 prog_clk[0]:370 chanx_right_in[6]:11 0.0002076947 +512 prog_clk[0]:307 chanx_right_in[6]:19 9.902294e-06 +513 prog_clk[0]:371 chanx_right_in[6]:11 0.000363176 +514 prog_clk[0]:84 chanx_right_in[6]:35 2.767178e-06 +515 prog_clk[0]:312 chanx_right_in[12]:25 5.860457e-06 +516 prog_clk[0]:313 chanx_right_in[12]:26 0.0002904114 +517 prog_clk[0]:129 chanx_right_in[12]:26 1.119951e-05 +518 prog_clk[0]:129 chanx_right_in[12]:27 0.0001699482 +519 prog_clk[0]:311 chanx_right_in[12]:24 5.860457e-06 +520 prog_clk[0]:310 chanx_right_in[12]:26 5.994539e-07 +521 prog_clk[0]:363 chanx_right_in[12]:15 6.261284e-05 +522 prog_clk[0]:363 chanx_right_in[12]:16 3.832972e-05 +523 prog_clk[0]:112 chanx_right_in[12]:27 9.776556e-05 +524 prog_clk[0]:112 chanx_right_in[12]:28 3.146056e-05 +525 prog_clk[0]:353 chanx_right_in[12]:11 2.298219e-06 +526 prog_clk[0]:309 chanx_right_in[12]:27 5.994539e-07 +527 prog_clk[0]:68 chanx_right_in[12]:28 3.842334e-05 +528 prog_clk[0]:360 chanx_right_in[12]:12 3.775899e-05 +529 prog_clk[0]:360 chanx_right_in[12]:15 3.832972e-05 +530 prog_clk[0]:360 chanx_right_in[12]:16 5.936205e-05 +531 prog_clk[0]:356 chanx_right_in[12]:11 3.775899e-05 +532 prog_clk[0]:356 chanx_right_in[12]:12 2.298219e-06 +533 prog_clk[0]:356 chanx_right_in[12]:15 5.936205e-05 +534 prog_clk[0]:144 chanx_right_in[12]:26 0.0001202402 +535 prog_clk[0]:144 chanx_right_in[12]:27 0.0002904114 +536 prog_clk[0]:134 chanx_right_in[12]:26 0.0001699482 +537 prog_clk[0]:134 chanx_right_in[12]:27 5.356827e-05 +538 prog_clk[0]:139 chanx_right_in[12]:26 5.356827e-05 +539 prog_clk[0]:139 chanx_right_in[12]:27 0.0001202402 +540 prog_clk[0]:117 chanx_right_in[12]:26 9.776556e-05 +541 prog_clk[0]:117 chanx_right_in[12]:27 4.266006e-05 +542 prog_clk[0]:364 chanx_right_in[12]:16 6.261284e-05 +543 prog_clk[0]:69 chanx_right_in[12]:27 3.842334e-05 +544 prog_clk[0]:127 chanx_right_in[14]:31 4.142711e-06 +545 prog_clk[0]:128 chanx_right_in[14]:30 4.142711e-06 +546 prog_clk[0]:99 chanx_right_in[14]:32 0.0001332472 +547 prog_clk[0]:308 chanx_right_in[14]:16 2.144257e-06 +548 prog_clk[0]:93 chanx_right_in[14]:32 0.0001814741 +549 prog_clk[0]:93 chanx_right_in[14]:33 7.440128e-05 +550 prog_clk[0]:360 chanx_right_in[14]:8 8.531026e-07 +551 prog_clk[0]:356 chanx_right_in[14]:7 8.531026e-07 +552 prog_clk[0]:98 chanx_right_in[14]:32 7.440128e-05 +553 prog_clk[0]:98 chanx_right_in[14]:33 0.0001332472 +554 prog_clk[0]:304 chanx_right_in[14]:15 7.554289e-07 +555 prog_clk[0]:307 chanx_right_in[14]:15 2.144257e-06 +556 prog_clk[0]:307 chanx_right_in[14]:16 7.554289e-07 +557 prog_clk[0]:89 chanx_right_in[14]:33 0.0001814741 +558 prog_clk[0]:129 chanx_right_in[15]:32 1.058539e-05 +559 prog_clk[0]:129 chanx_right_in[15]:33 0.0001021963 +560 prog_clk[0]:271 chanx_right_in[15]:29 3.58316e-06 +561 prog_clk[0]:199 chanx_right_in[15]:25 8.508198e-07 +562 prog_clk[0]:199 chanx_right_in[15]:27 7.354752e-06 +563 prog_clk[0]:200 chanx_right_in[15]:26 3.635365e-06 +564 prog_clk[0]:200 chanx_right_in[15]:27 3.548116e-06 +565 prog_clk[0]:200 chanx_right_in[15]:28 9.339372e-06 +566 prog_clk[0]:200 chanx_right_in[15]:29 4.231213e-06 +567 prog_clk[0]:112 chanx_right_in[15]:33 7.512081e-05 +568 prog_clk[0]:297 chanx_right_in[15]:20 1.591472e-06 +569 prog_clk[0]:270 chanx_right_in[15]:8 3.58316e-06 +570 prog_clk[0]:164 chanx_right_in[15]:29 9.339372e-06 +571 prog_clk[0]:201 chanx_right_in[15]:22 3.635365e-06 +572 prog_clk[0]:201 chanx_right_in[15]:26 3.548116e-06 +573 prog_clk[0]:201 chanx_right_in[15]:28 4.231213e-06 +574 prog_clk[0]:68 chanx_right_in[15]:33 5.382533e-05 +575 prog_clk[0]:198 chanx_right_in[15]:24 8.508198e-07 +576 prog_clk[0]:198 chanx_right_in[15]:28 7.354752e-06 +577 prog_clk[0]:293 chanx_right_in[15]:21 4.35575e-07 +578 prog_clk[0]:144 chanx_right_in[15]:32 8.874273e-06 +579 prog_clk[0]:134 chanx_right_in[15]:32 0.0001021963 +580 prog_clk[0]:134 chanx_right_in[15]:33 3.499179e-05 +581 prog_clk[0]:139 chanx_right_in[15]:32 3.499179e-05 +582 prog_clk[0]:139 chanx_right_in[15]:33 8.874273e-06 +583 prog_clk[0]:296 chanx_right_in[15]:20 4.35575e-07 +584 prog_clk[0]:296 chanx_right_in[15]:21 1.591472e-06 +585 prog_clk[0]:117 chanx_right_in[15]:32 7.512081e-05 +586 prog_clk[0]:117 chanx_right_in[15]:33 1.058539e-05 +587 prog_clk[0]:69 chanx_right_in[15]:32 5.382533e-05 +588 prog_clk[0]:252 chanx_right_in[17]:24 0.0003742167 +589 prog_clk[0]:253 chanx_right_in[17]:20 0.0003742167 +590 prog_clk[0]:133 chanx_right_in[17]:11 3.412849e-06 +591 prog_clk[0]:134 chanx_right_in[17]:6 5.810599e-05 +592 prog_clk[0]:132 chanx_right_in[17]:12 3.412849e-06 +593 prog_clk[0]:138 chanx_right_in[17]:11 2.386006e-06 +594 prog_clk[0]:139 chanx_right_in[17]:13 5.810599e-05 +595 prog_clk[0]:137 chanx_right_in[17]:12 2.386006e-06 +596 prog_clk[0]:362 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 5.37349e-05 +597 prog_clk[0]:363 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 2.084548e-07 +598 prog_clk[0]:363 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 9.172012e-07 +599 prog_clk[0]:361 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 5.37349e-05 +600 prog_clk[0]:360 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 9.172012e-07 +601 prog_clk[0]:364 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 2.084548e-07 +602 prog_clk[0]:100 mux_tree_tapbuf_size8_2_sram[0]:8 8.217059e-08 +603 prog_clk[0]:103 mux_tree_tapbuf_size8_2_sram[0]:7 8.217059e-08 +604 prog_clk[0]:97 mux_tree_tapbuf_size8_2_sram[0]:7 0.0002024203 +605 prog_clk[0]:97 mux_tree_tapbuf_size8_2_sram[0]:8 1.06077e-05 +606 prog_clk[0]:96 mux_tree_tapbuf_size8_2_sram[0]:9 1.06077e-05 +607 prog_clk[0]:96 mux_tree_tapbuf_size8_2_sram[0]:8 0.0002024203 +608 prog_clk[0]:231 mux_tree_tapbuf_size8_6_sram[2]:20 0.0004374493 +609 prog_clk[0]:236 mux_tree_tapbuf_size8_6_sram[2]:19 0.0004374493 +610 prog_clk[0]:177 mux_tree_tapbuf_size8_7_sram[2]:13 1.075369e-06 +611 prog_clk[0]:177 mux_tree_tapbuf_size8_7_sram[2]:7 7.748968e-06 +612 prog_clk[0]:176 mux_tree_tapbuf_size8_7_sram[2]:14 1.075369e-06 +613 prog_clk[0]:176 mux_tree_tapbuf_size8_7_sram[2]:6 7.748968e-06 +614 prog_clk[0]:173 mux_tree_tapbuf_size8_7_sram[2]:15 0.0002397102 +615 prog_clk[0]:173 mux_tree_tapbuf_size8_7_sram[2]:8 0.0001353528 +616 prog_clk[0]:172 mux_tree_tapbuf_size8_7_sram[2]:15 0.0001353528 +617 prog_clk[0]:172 mux_tree_tapbuf_size8_7_sram[2]:16 0.0002397102 +618 prog_clk[0]:106 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.074604e-05 +619 prog_clk[0]:84 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.074604e-05 +620 prog_clk[0]:326 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.62776e-05 +621 prog_clk[0]:325 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.62776e-05 +622 prog_clk[0]:230 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.932161e-06 +623 prog_clk[0]:223 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.481535e-05 +624 prog_clk[0]:223 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.66541e-05 +625 prog_clk[0]:229 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.932161e-06 +626 prog_clk[0]:229 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.565902e-05 +627 prog_clk[0]:226 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.565902e-05 +628 prog_clk[0]:226 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.481535e-05 +629 prog_clk[0]:220 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.66541e-05 +630 prog_clk[0]:223 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.012382e-05 +631 prog_clk[0]:220 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.012382e-05 +632 prog_clk[0]:217 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.542415e-06 +633 prog_clk[0]:223 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.034639e-05 +634 prog_clk[0]:219 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.355058e-05 +635 prog_clk[0]:220 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.034639e-05 +636 prog_clk[0]:220 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.542415e-06 +637 prog_clk[0]:218 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.355058e-05 +638 prog_clk[0]:199 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.325087e-05 +639 prog_clk[0]:198 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.325087e-05 +640 prog_clk[0]:308 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001214117 +641 prog_clk[0]:307 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001214117 +642 prog_clk[0]:375 ropt_net_179:5 2.946719e-05 +643 prog_clk[0]:377 ropt_net_179:6 9.745056e-06 +644 prog_clk[0]:315 ropt_net_179:7 1.770196e-05 +645 prog_clk[0]:316 ropt_net_179:4 9.448009e-06 +646 prog_clk[0]:314 ropt_net_179:8 1.770196e-05 +647 prog_clk[0]:376 ropt_net_179:6 2.946719e-05 +648 prog_clk[0]:376 ropt_net_179:5 9.745056e-06 +649 prog_clk[0]:376 ropt_net_179:3 9.448009e-06 +650 prog_clk[0]:313 ropt_net_133:6 0.0003477648 +651 prog_clk[0]:378 ropt_net_133:6 6.081825e-05 +652 prog_clk[0]:378 ropt_net_133:5 0.0003477648 +653 prog_clk[0]:379 ropt_net_133:5 6.081825e-05 +654 prog_clk[0]:346 mem_bottom_ipin_15/net_net_75:7 0.0001952722 +655 prog_clk[0]:351 mem_bottom_ipin_15/net_net_75:7 0.000169803 +656 prog_clk[0]:351 mem_bottom_ipin_15/net_net_75:6 0.0001952722 +657 prog_clk[0]:352 mem_bottom_ipin_15/net_net_75:6 0.000169803 +658 prog_clk[0]:183 mem_bottom_ipin_15/net_net_75:6 0.0004177893 +659 prog_clk[0]:178 mem_bottom_ipin_15/net_net_75:7 0.000369801 +660 prog_clk[0]:336 mem_bottom_ipin_15/net_net_75:7 2.977531e-05 +661 prog_clk[0]:173 mem_bottom_ipin_15/net_net_75:6 2.398543e-06 +662 prog_clk[0]:172 mem_bottom_ipin_15/net_net_75:7 2.398543e-06 +663 prog_clk[0]:182 mem_bottom_ipin_15/net_net_75:7 0.0004177893 +664 prog_clk[0]:182 mem_bottom_ipin_15/net_net_75:6 0.000369801 +665 prog_clk[0]:337 mem_bottom_ipin_15/net_net_75:6 2.977531e-05 +666 prog_clk[0]:375 ropt_net_171:7 2.681225e-05 +667 prog_clk[0]:375 ropt_net_171:5 2.645193e-08 +668 prog_clk[0]:375 ropt_net_171:2 7.819813e-06 +669 prog_clk[0]:370 ropt_net_171:5 1.107159e-05 +670 prog_clk[0]:371 ropt_net_171:5 3.312384e-06 +671 prog_clk[0]:371 ropt_net_171:4 1.107159e-05 +672 prog_clk[0]:372 ropt_net_171:6 2.681225e-05 +673 prog_clk[0]:372 ropt_net_171:3 7.819813e-06 +674 prog_clk[0]:372 ropt_net_171:4 3.312384e-06 +675 prog_clk[0]:376 ropt_net_171:4 2.645193e-08 +676 prog_clk[0]:375 ropt_net_129:3 5.689583e-07 +677 prog_clk[0]:312 ropt_net_129:8 5.534487e-06 +678 prog_clk[0]:313 ropt_net_129:6 0.0002132947 +679 prog_clk[0]:311 ropt_net_129:7 5.534487e-06 +680 prog_clk[0]:377 ropt_net_129:4 7.886489e-06 +681 prog_clk[0]:378 ropt_net_129:6 3.456563e-05 +682 prog_clk[0]:378 ropt_net_129:5 0.0002132947 +683 prog_clk[0]:379 ropt_net_129:5 3.456563e-05 +684 prog_clk[0]:376 ropt_net_129:4 5.689583e-07 +685 prog_clk[0]:376 ropt_net_129:3 7.886489e-06 + +*RES +0 prog_clk[0] prog_clk[0]:380 0.007904018 +1 prog_clk[0]:374 prog_clk[0]:373 0.002167411 +2 prog_clk[0]:375 prog_clk[0]:374 0.0045 +3 prog_clk[0]:375 prog_clk[0]:372 0.002013393 +4 prog_clk[0]:373 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +5 prog_clk[0]:331 prog_clk[0]:330 0.004765625 +6 prog_clk[0]:332 prog_clk[0]:331 0.00341 +7 prog_clk[0]:332 prog_clk[0]:327 0.0003603333 +8 prog_clk[0]:329 prog_clk[0]:328 0.0009330358 +9 prog_clk[0]:330 prog_clk[0]:329 0.0045 +10 prog_clk[0]:328 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +11 prog_clk[0]:312 prog_clk[0]:311 0.004147322 +12 prog_clk[0]:313 prog_clk[0]:312 0.00341 +13 prog_clk[0]:313 prog_clk[0]:144 0.003170933 +14 prog_clk[0]:126 prog_clk[0]:125 0.00341 +15 prog_clk[0]:126 prog_clk[0]:121 0.0003579833 +16 prog_clk[0]:127 prog_clk[0]:126 0.00341 +17 prog_clk[0]:129 prog_clk[0]:128 0.00341 +18 prog_clk[0]:129 prog_clk[0]:117 0.0002162 +19 prog_clk[0]:128 prog_clk[0]:127 0.00159565 +20 prog_clk[0]:195 prog_clk[0]:194 0.00341 +21 prog_clk[0]:195 prog_clk[0]:168 0.0008214285 +22 prog_clk[0]:194 prog_clk[0]:193 0.0002859166 +23 prog_clk[0]:192 prog_clk[0]:191 0.0005669643 +24 prog_clk[0]:192 prog_clk[0]:188 0.009410715 +25 prog_clk[0]:193 prog_clk[0]:192 0.00341 +26 prog_clk[0]:272 prog_clk[0]:271 0.00341 +27 prog_clk[0]:272 prog_clk[0]:210 0.0045 +28 prog_clk[0]:271 prog_clk[0]:270 0.001007758 +29 prog_clk[0]:311 prog_clk[0]:310 0.00341 +30 prog_clk[0]:311 prog_clk[0]:147 0.0004107143 +31 prog_clk[0]:310 prog_clk[0]:309 0.0007915583 +32 prog_clk[0]:155 prog_clk[0]:154 0.0001850962 +33 prog_clk[0]:156 prog_clk[0]:155 0.00341 +34 prog_clk[0]:345 prog_clk[0]:344 0.001466518 +35 prog_clk[0]:346 prog_clk[0]:345 0.00341 +36 prog_clk[0]:346 prog_clk[0]:337 0.0001053583 +37 prog_clk[0]:199 prog_clk[0]:198 0.0111808 +38 prog_clk[0]:200 prog_clk[0]:199 0.00341 +39 prog_clk[0]:200 prog_clk[0]:164 0.0002870917 +40 prog_clk[0]:347 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +41 prog_clk[0]:348 prog_clk[0]:347 0.000984375 +42 prog_clk[0]:349 prog_clk[0]:348 0.0045 +43 prog_clk[0]:350 prog_clk[0]:349 0.001729911 +44 prog_clk[0]:351 prog_clk[0]:350 0.00341 +45 prog_clk[0]:351 prog_clk[0]:346 0.001441333 +46 prog_clk[0]:367 prog_clk[0]:366 0.00341 +47 prog_clk[0]:367 prog_clk[0]:318 0.0045 +48 prog_clk[0]:366 prog_clk[0]:365 0.0005753583 +49 prog_clk[0]:281 prog_clk[0]:280 0.001162947 +50 prog_clk[0]:282 prog_clk[0]:281 0.00341 +51 prog_clk[0]:362 prog_clk[0]:361 0.0008950894 +52 prog_clk[0]:363 prog_clk[0]:362 0.0045 +53 prog_clk[0]:363 prog_clk[0]:360 0.002732143 +54 prog_clk[0]:361 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +55 prog_clk[0]:111 prog_clk[0]:110 0.004502232 +56 prog_clk[0]:112 prog_clk[0]:111 0.00341 +57 prog_clk[0]:112 prog_clk[0]:69 0.0001053583 +58 prog_clk[0]:353 prog_clk[0]:352 0.00341 +59 prog_clk[0]:352 prog_clk[0]:351 0.001151892 +60 prog_clk[0]:100 prog_clk[0]:99 0.00341 +61 prog_clk[0]:99 prog_clk[0]:98 0.0003591583 +62 prog_clk[0]:300 prog_clk[0]:299 0.00341 +63 prog_clk[0]:299 prog_clk[0]:298 0.0008636249 +64 prog_clk[0]:230 prog_clk[0]:229 0.0001850962 +65 prog_clk[0]:231 prog_clk[0]:230 0.00341 +66 prog_clk[0]:297 prog_clk[0]:296 0.006323661 +67 prog_clk[0]:298 prog_clk[0]:297 0.00341 +68 prog_clk[0]:298 prog_clk[0]:287 0.0002882667 +69 prog_clk[0]:343 prog_clk[0]:342 0.0001847826 +70 prog_clk[0]:344 prog_clk[0]:343 0.0045 +71 prog_clk[0]:344 prog_clk[0]:340 0.002691964 +72 prog_clk[0]:341 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +73 prog_clk[0]:269 prog_clk[0]:268 0.005109375 +74 prog_clk[0]:270 prog_clk[0]:269 0.00341 +75 prog_clk[0]:270 prog_clk[0]:214 0.0002870917 +76 prog_clk[0]:184 prog_clk[0]:183 0.00341 +77 prog_clk[0]:183 prog_clk[0]:182 0.001151892 +78 prog_clk[0]:163 prog_clk[0]:162 0.001162946 +79 prog_clk[0]:164 prog_clk[0]:163 0.00341 +80 prog_clk[0]:261 prog_clk[0]:260 0.00341 +81 prog_clk[0]:260 prog_clk[0]:259 0.001223958 +82 prog_clk[0]:249 prog_clk[0]:248 0.0005736608 +83 prog_clk[0]:250 prog_clk[0]:249 0.0045 +84 prog_clk[0]:248 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +85 prog_clk[0]:202 prog_clk[0]:201 0.00341 +86 prog_clk[0]:201 prog_clk[0]:200 0.0005753583 +87 prog_clk[0]:177 prog_clk[0]:176 0.002377232 +88 prog_clk[0]:178 prog_clk[0]:177 0.00341 +89 prog_clk[0]:258 prog_clk[0]:257 0.006930804 +90 prog_clk[0]:259 prog_clk[0]:258 0.00341 +91 prog_clk[0]:259 prog_clk[0]:240 0.0004324 +92 prog_clk[0]:251 prog_clk[0]:250 0.0008214285 +93 prog_clk[0]:251 prog_clk[0]:247 0.004857143 +94 prog_clk[0]:252 prog_clk[0]:251 0.00341 +95 prog_clk[0]:254 prog_clk[0]:253 0.00341 +96 prog_clk[0]:253 prog_clk[0]:252 0.001006583 +97 prog_clk[0]:103 prog_clk[0]:102 0.0045 +98 prog_clk[0]:103 prog_clk[0]:100 0.007234375 +99 prog_clk[0]:104 prog_clk[0]:103 0.00341 +100 prog_clk[0]:106 prog_clk[0]:105 0.00341 +101 prog_clk[0]:106 prog_clk[0]:84 0.01239509 +102 prog_clk[0]:105 prog_clk[0]:104 0.00194345 +103 prog_clk[0]:241 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +104 prog_clk[0]:242 prog_clk[0]:241 0.003087054 +105 prog_clk[0]:243 prog_clk[0]:242 0.0045 +106 prog_clk[0]:308 prog_clk[0]:307 0.009966519 +107 prog_clk[0]:309 prog_clk[0]:308 0.00341 +108 prog_clk[0]:309 prog_clk[0]:156 0.0007194917 +109 prog_clk[0]:377 prog_clk[0]:376 0.004198661 +110 prog_clk[0]:378 prog_clk[0]:377 0.00341 +111 prog_clk[0]:378 prog_clk[0]:313 0.0017296 +112 prog_clk[0]:273 prog_clk[0]:272 0.004805804 +113 prog_clk[0]:274 prog_clk[0]:273 0.00341 +114 prog_clk[0]:216 prog_clk[0]:215 0.0001440218 +115 prog_clk[0]:217 prog_clk[0]:216 0.0045 +116 prog_clk[0]:215 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +117 prog_clk[0]:222 prog_clk[0]:221 0.0001847826 +118 prog_clk[0]:223 prog_clk[0]:222 0.0045 +119 prog_clk[0]:223 prog_clk[0]:220 0.007589286 +120 prog_clk[0]:221 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +121 prog_clk[0]:92 prog_clk[0]:91 0.0045 +122 prog_clk[0]:93 prog_clk[0]:92 0.00341 +123 prog_clk[0]:93 prog_clk[0]:89 0.0005032916 +124 prog_clk[0]:91 prog_clk[0]:90 0.0001059783 +125 prog_clk[0]:90 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +126 prog_clk[0]:102 prog_clk[0]:101 0.0001059783 +127 prog_clk[0]:101 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +128 prog_clk[0]:67 prog_clk[0]:66 0.0045 +129 prog_clk[0]:68 prog_clk[0]:67 0.00341 +130 prog_clk[0]:66 prog_clk[0]:65 0.0001440218 +131 prog_clk[0]:65 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +132 prog_clk[0]:109 prog_clk[0]:108 0.0001847826 +133 prog_clk[0]:110 prog_clk[0]:109 0.0045 +134 prog_clk[0]:110 prog_clk[0]:107 0.002125 +135 prog_clk[0]:108 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +136 prog_clk[0]:359 prog_clk[0]:358 0.0003035715 +137 prog_clk[0]:360 prog_clk[0]:359 0.0045 +138 prog_clk[0]:360 prog_clk[0]:356 0.009410716 +139 prog_clk[0]:357 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +140 prog_clk[0]:120 prog_clk[0]:119 0.0045 +141 prog_clk[0]:121 prog_clk[0]:120 0.00341 +142 prog_clk[0]:119 prog_clk[0]:118 0.0001440218 +143 prog_clk[0]:118 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +144 prog_clk[0]:338 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +145 prog_clk[0]:339 prog_clk[0]:338 0.002216518 +146 prog_clk[0]:340 prog_clk[0]:339 0.0045 +147 prog_clk[0]:335 prog_clk[0]:334 0.0045 +148 prog_clk[0]:336 prog_clk[0]:335 0.00341 +149 prog_clk[0]:334 prog_clk[0]:333 0.0005736608 +150 prog_clk[0]:333 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +151 prog_clk[0]:355 prog_clk[0]:354 0.000984375 +152 prog_clk[0]:356 prog_clk[0]:355 0.0045 +153 prog_clk[0]:356 prog_clk[0]:353 0.0005558036 +154 prog_clk[0]:354 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +155 prog_clk[0]:166 prog_clk[0]:165 0.0001059783 +156 prog_clk[0]:167 prog_clk[0]:166 0.0045 +157 prog_clk[0]:165 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +158 prog_clk[0]:190 prog_clk[0]:189 0.00139509 +159 prog_clk[0]:191 prog_clk[0]:190 0.0045 +160 prog_clk[0]:189 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +161 prog_clk[0]:280 prog_clk[0]:279 0.00341 +162 prog_clk[0]:280 prog_clk[0]:208 0.0045 +163 prog_clk[0]:280 prog_clk[0]:206 0.002125 +164 prog_clk[0]:279 prog_clk[0]:278 0.001872558 +165 prog_clk[0]:239 prog_clk[0]:238 0.0045 +166 prog_clk[0]:240 prog_clk[0]:239 0.00341 +167 prog_clk[0]:240 prog_clk[0]:236 0.0008647999 +168 prog_clk[0]:238 prog_clk[0]:237 0.0001059783 +169 prog_clk[0]:237 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +170 prog_clk[0]:79 prog_clk[0]:78 0.00341 +171 prog_clk[0]:79 prog_clk[0]:73 0.0004107143 +172 prog_clk[0]:78 prog_clk[0]:77 0.0001417833 +173 prog_clk[0]:76 prog_clk[0]:75 0.0045 +174 prog_clk[0]:77 prog_clk[0]:76 0.00341 +175 prog_clk[0]:75 prog_clk[0]:74 0.0001440218 +176 prog_clk[0]:74 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +177 prog_clk[0]:97 prog_clk[0]:96 0.007194197 +178 prog_clk[0]:98 prog_clk[0]:97 0.00341 +179 prog_clk[0]:98 prog_clk[0]:93 0.0002162 +180 prog_clk[0]:95 prog_clk[0]:94 0.0001059783 +181 prog_clk[0]:96 prog_clk[0]:95 0.0045 +182 prog_clk[0]:94 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +183 prog_clk[0]:318 prog_clk[0]:317 0.0005736608 +184 prog_clk[0]:317 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +185 prog_clk[0]:71 prog_clk[0]:70 0.0001059783 +186 prog_clk[0]:72 prog_clk[0]:71 0.0045 +187 prog_clk[0]:70 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +188 prog_clk[0]:369 prog_clk[0]:368 0.0001847826 +189 prog_clk[0]:370 prog_clk[0]:369 0.0045 +190 prog_clk[0]:370 prog_clk[0]:367 0.006982144 +191 prog_clk[0]:368 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +192 prog_clk[0]:197 prog_clk[0]:196 0.0001847826 +193 prog_clk[0]:198 prog_clk[0]:197 0.0045 +194 prog_clk[0]:198 prog_clk[0]:195 0.005109375 +195 prog_clk[0]:196 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +196 prog_clk[0]:293 prog_clk[0]:292 0.00341 +197 prog_clk[0]:292 prog_clk[0]:291 0.0002859167 +198 prog_clk[0]:290 prog_clk[0]:289 0.0045 +199 prog_clk[0]:291 prog_clk[0]:290 0.00341 +200 prog_clk[0]:289 prog_clk[0]:288 0.0005736608 +201 prog_clk[0]:288 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +202 prog_clk[0]:303 prog_clk[0]:302 0.0003705357 +203 prog_clk[0]:304 prog_clk[0]:303 0.0045 +204 prog_clk[0]:304 prog_clk[0]:300 0.001466518 +205 prog_clk[0]:301 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +206 prog_clk[0]:205 prog_clk[0]:204 0.0003705357 +207 prog_clk[0]:206 prog_clk[0]:205 0.0045 +208 prog_clk[0]:206 prog_clk[0]:202 0.001466518 +209 prog_clk[0]:203 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +210 prog_clk[0]:286 prog_clk[0]:285 0.001122768 +211 prog_clk[0]:287 prog_clk[0]:286 0.00341 +212 prog_clk[0]:287 prog_clk[0]:282 0.001223958 +213 prog_clk[0]:284 prog_clk[0]:283 0.0001059783 +214 prog_clk[0]:285 prog_clk[0]:284 0.0045 +215 prog_clk[0]:283 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +216 prog_clk[0]:244 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +217 prog_clk[0]:245 prog_clk[0]:244 0.0001222826 +218 prog_clk[0]:246 prog_clk[0]:245 0.0045 +219 prog_clk[0]:149 prog_clk[0]:148 0.0001059783 +220 prog_clk[0]:150 prog_clk[0]:149 0.0045 +221 prog_clk[0]:148 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +222 prog_clk[0]:264 prog_clk[0]:263 0.0003035715 +223 prog_clk[0]:265 prog_clk[0]:264 0.0045 +224 prog_clk[0]:265 prog_clk[0]:261 0.002680804 +225 prog_clk[0]:262 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +226 prog_clk[0]:153 prog_clk[0]:152 0.0003035715 +227 prog_clk[0]:154 prog_clk[0]:153 0.0045 +228 prog_clk[0]:154 prog_clk[0]:150 0.004473214 +229 prog_clk[0]:151 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +230 prog_clk[0]:267 prog_clk[0]:266 0.0001847826 +231 prog_clk[0]:268 prog_clk[0]:267 0.0045 +232 prog_clk[0]:268 prog_clk[0]:265 0.001821429 +233 prog_clk[0]:266 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +234 prog_clk[0]:143 prog_clk[0]:142 0.004158482 +235 prog_clk[0]:144 prog_clk[0]:143 0.00341 +236 prog_clk[0]:144 prog_clk[0]:139 0.001225133 +237 prog_clk[0]:141 prog_clk[0]:140 0.0001059783 +238 prog_clk[0]:142 prog_clk[0]:141 0.0045 +239 prog_clk[0]:140 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +240 prog_clk[0]:208 prog_clk[0]:207 0.0005736608 +241 prog_clk[0]:207 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +242 prog_clk[0]:161 prog_clk[0]:160 0.001395089 +243 prog_clk[0]:162 prog_clk[0]:161 0.0045 +244 prog_clk[0]:162 prog_clk[0]:159 0.002388393 +245 prog_clk[0]:160 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +246 prog_clk[0]:210 prog_clk[0]:209 0.0001440218 +247 prog_clk[0]:209 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +248 prog_clk[0]:175 prog_clk[0]:174 0.0001059783 +249 prog_clk[0]:176 prog_clk[0]:175 0.0045 +250 prog_clk[0]:176 prog_clk[0]:173 0.00341 +251 prog_clk[0]:174 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +252 prog_clk[0]:277 prog_clk[0]:276 0.0045 +253 prog_clk[0]:278 prog_clk[0]:277 0.00341 +254 prog_clk[0]:278 prog_clk[0]:274 0.0005753583 +255 prog_clk[0]:276 prog_clk[0]:275 0.0001440218 +256 prog_clk[0]:275 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +257 prog_clk[0]:173 prog_clk[0]:172 0.001222783 +258 prog_clk[0]:171 prog_clk[0]:170 0.0045 +259 prog_clk[0]:172 prog_clk[0]:171 0.00341 +260 prog_clk[0]:170 prog_clk[0]:169 0.0005736608 +261 prog_clk[0]:169 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +262 prog_clk[0]:133 prog_clk[0]:132 0.004158482 +263 prog_clk[0]:134 prog_clk[0]:133 0.00341 +264 prog_clk[0]:134 prog_clk[0]:129 0.0015134 +265 prog_clk[0]:131 prog_clk[0]:130 0.0001114131 +266 prog_clk[0]:132 prog_clk[0]:131 0.0045 +267 prog_clk[0]:130 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +268 prog_clk[0]:138 prog_clk[0]:137 0.006587054 +269 prog_clk[0]:139 prog_clk[0]:138 0.00341 +270 prog_clk[0]:139 prog_clk[0]:134 0.0007927333 +271 prog_clk[0]:136 prog_clk[0]:135 0.0001440218 +272 prog_clk[0]:137 prog_clk[0]:136 0.0045 +273 prog_clk[0]:135 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +274 prog_clk[0]:158 prog_clk[0]:157 0.0001440218 +275 prog_clk[0]:159 prog_clk[0]:158 0.0045 +276 prog_clk[0]:157 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +277 prog_clk[0]:235 prog_clk[0]:234 0.002337054 +278 prog_clk[0]:236 prog_clk[0]:235 0.00341 +279 prog_clk[0]:236 prog_clk[0]:231 0.002232892 +280 prog_clk[0]:233 prog_clk[0]:232 0.0001059783 +281 prog_clk[0]:234 prog_clk[0]:233 0.0045 +282 prog_clk[0]:232 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +283 prog_clk[0]:187 prog_clk[0]:186 0.0003705357 +284 prog_clk[0]:188 prog_clk[0]:187 0.0045 +285 prog_clk[0]:188 prog_clk[0]:184 0.002073661 +286 prog_clk[0]:185 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +287 prog_clk[0]:228 prog_clk[0]:227 0.0001847826 +288 prog_clk[0]:229 prog_clk[0]:228 0.0045 +289 prog_clk[0]:229 prog_clk[0]:226 0.002084821 +290 prog_clk[0]:227 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +291 prog_clk[0]:181 prog_clk[0]:180 0.0045 +292 prog_clk[0]:182 prog_clk[0]:181 0.00341 +293 prog_clk[0]:182 prog_clk[0]:178 0.001007758 +294 prog_clk[0]:180 prog_clk[0]:179 0.0001059783 +295 prog_clk[0]:179 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +296 prog_clk[0]:225 prog_clk[0]:224 0.0001440218 +297 prog_clk[0]:226 prog_clk[0]:225 0.0045 +298 prog_clk[0]:226 prog_clk[0]:223 0.004553571 +299 prog_clk[0]:224 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +300 prog_clk[0]:256 prog_clk[0]:255 0.0001847826 +301 prog_clk[0]:257 prog_clk[0]:256 0.0045 +302 prog_clk[0]:257 prog_clk[0]:254 0.002680804 +303 prog_clk[0]:255 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +304 prog_clk[0]:219 prog_clk[0]:218 0.0001440218 +305 prog_clk[0]:220 prog_clk[0]:219 0.0045 +306 prog_clk[0]:220 prog_clk[0]:217 0.004816965 +307 prog_clk[0]:218 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +308 prog_clk[0]:213 prog_clk[0]:212 0.0045 +309 prog_clk[0]:214 prog_clk[0]:213 0.00341 +310 prog_clk[0]:212 prog_clk[0]:211 0.0005736608 +311 prog_clk[0]:211 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +312 prog_clk[0]:295 prog_clk[0]:294 0.0001847826 +313 prog_clk[0]:296 prog_clk[0]:295 0.0045 +314 prog_clk[0]:296 prog_clk[0]:293 0.004502232 +315 prog_clk[0]:294 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +316 prog_clk[0]:125 prog_clk[0]:124 0.004765625 +317 prog_clk[0]:123 prog_clk[0]:122 0.0001059783 +318 prog_clk[0]:124 prog_clk[0]:123 0.0045 +319 prog_clk[0]:122 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +320 prog_clk[0]:321 prog_clk[0]:320 0.0045 +321 prog_clk[0]:322 prog_clk[0]:321 0.00341 +322 prog_clk[0]:320 prog_clk[0]:319 0.0001440218 +323 prog_clk[0]:319 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +324 prog_clk[0]:116 prog_clk[0]:115 0.001729911 +325 prog_clk[0]:117 prog_clk[0]:116 0.00341 +326 prog_clk[0]:117 prog_clk[0]:112 0.001369267 +327 prog_clk[0]:114 prog_clk[0]:113 0.0001059783 +328 prog_clk[0]:115 prog_clk[0]:114 0.0045 +329 prog_clk[0]:113 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +330 prog_clk[0]:82 prog_clk[0]:81 0.0003035714 +331 prog_clk[0]:83 prog_clk[0]:82 0.0045 +332 prog_clk[0]:83 prog_clk[0]:79 0.004462054 +333 prog_clk[0]:80 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +334 prog_clk[0]:306 prog_clk[0]:305 0.0001847826 +335 prog_clk[0]:307 prog_clk[0]:306 0.0045 +336 prog_clk[0]:307 prog_clk[0]:304 0.001821429 +337 prog_clk[0]:305 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +338 prog_clk[0]:88 prog_clk[0]:87 0.002337053 +339 prog_clk[0]:89 prog_clk[0]:88 0.00341 +340 prog_clk[0]:86 prog_clk[0]:85 0.0001086957 +341 prog_clk[0]:87 prog_clk[0]:86 0.0045 +342 prog_clk[0]:85 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +343 prog_clk[0]:146 prog_clk[0]:145 0.0006138393 +344 prog_clk[0]:147 prog_clk[0]:146 0.0045 +345 prog_clk[0]:145 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +346 prog_clk[0]:315 prog_clk[0]:314 0.001805804 +347 prog_clk[0]:316 prog_clk[0]:315 0.0045 +348 prog_clk[0]:314 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +349 prog_clk[0]:380 prog_clk[0]:379 0.00341 +350 prog_clk[0]:379 prog_clk[0]:378 0.0002870917 +351 prog_clk[0]:364 prog_clk[0]:363 0.004805804 +352 prog_clk[0]:365 prog_clk[0]:364 0.00341 +353 prog_clk[0]:365 prog_clk[0]:332 0.001369267 +354 prog_clk[0]:326 prog_clk[0]:325 0.002337054 +355 prog_clk[0]:327 prog_clk[0]:326 0.00341 +356 prog_clk[0]:327 prog_clk[0]:322 0.000431225 +357 prog_clk[0]:324 prog_clk[0]:323 0.0001059783 +358 prog_clk[0]:325 prog_clk[0]:324 0.0045 +359 prog_clk[0]:323 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +360 prog_clk[0]:358 prog_clk[0]:357 0.001024554 +361 prog_clk[0]:302 prog_clk[0]:301 0.0003035715 +362 prog_clk[0]:342 prog_clk[0]:341 0.0006339286 +363 prog_clk[0]:152 prog_clk[0]:151 0.001024554 +364 prog_clk[0]:204 prog_clk[0]:203 0.0003035715 +365 prog_clk[0]:186 prog_clk[0]:185 0.0003035715 +366 prog_clk[0]:263 prog_clk[0]:262 0.001024554 +367 prog_clk[0]:81 prog_clk[0]:80 0.0006138394 +368 prog_clk[0]:371 prog_clk[0]:370 0.01455804 +369 prog_clk[0]:372 prog_clk[0]:371 0.000221875 +370 prog_clk[0]:376 prog_clk[0]:375 0.004816965 +371 prog_clk[0]:376 prog_clk[0]:316 0.0004107143 +372 prog_clk[0]:168 prog_clk[0]:167 0.00178125 +373 prog_clk[0]:107 prog_clk[0]:106 0.0004107143 +374 prog_clk[0]:84 prog_clk[0]:83 0.0004107143 +375 prog_clk[0]:73 prog_clk[0]:72 0.002388393 +376 prog_clk[0]:247 prog_clk[0]:246 0.0004107143 +377 prog_clk[0]:247 prog_clk[0]:243 0.002388393 +378 prog_clk[0]:337 prog_clk[0]:336 0.001151892 +379 prog_clk[0]:69 prog_clk[0]:68 0.0007194916 + +*END + +*D_NET chanx_left_in[8] 0.01753081 //LENGTH 111.912 LUMPCC 0.005549237 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 19.040 +*I mux_bottom_ipin_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 13.900 23.460 +*I mux_bottom_ipin_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 53.195 22.780 +*I ropt_mt_inst_733:A I *L 0.001767 *C 93.380 17.680 +*N chanx_left_in[8]:4 *C 93.343 17.680 +*N chanx_left_in[8]:5 *C 91.585 17.680 +*N chanx_left_in[8]:6 *C 91.540 17.635 +*N chanx_left_in[8]:7 *C 91.540 17.058 +*N chanx_left_in[8]:8 *C 91.532 17.000 +*N chanx_left_in[8]:9 *C 80.968 17.000 +*N chanx_left_in[8]:10 *C 80.960 17.058 +*N chanx_left_in[8]:11 *C 80.960 17.635 +*N chanx_left_in[8]:12 *C 80.915 17.680 +*N chanx_left_in[8]:13 *C 78.660 17.680 +*N chanx_left_in[8]:14 *C 78.660 17.635 +*N chanx_left_in[8]:15 *C 78.660 15.698 +*N chanx_left_in[8]:16 *C 78.653 15.640 +*N chanx_left_in[8]:17 *C 53.380 15.640 +*N chanx_left_in[8]:18 *C 53.360 15.648 +*N chanx_left_in[8]:19 *C 53.360 22.773 +*N chanx_left_in[8]:20 *C 53.348 22.780 +*N chanx_left_in[8]:21 *C 53.333 23.120 +*N chanx_left_in[8]:22 *C 53.195 22.780 +*N chanx_left_in[8]:23 *C 53.360 22.780 +*N chanx_left_in[8]:24 *C 53.360 22.780 +*N chanx_left_in[8]:25 *C 53.360 23.120 +*N chanx_left_in[8]:26 *C 53.360 23.113 +*N chanx_left_in[8]:27 *C 13.800 23.460 +*N chanx_left_in[8]:28 *C 13.800 23.460 +*N chanx_left_in[8]:29 *C 13.800 23.120 +*N chanx_left_in[8]:30 *C 13.800 23.120 +*N chanx_left_in[8]:31 *C 9.220 23.120 +*N chanx_left_in[8]:32 *C 9.200 23.113 +*N chanx_left_in[8]:33 *C 9.200 19.047 +*N chanx_left_in[8]:34 *C 9.180 19.040 + +*CAP +0 chanx_left_in[8] 0.0006150554 +1 mux_bottom_ipin_8\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_ipin_4\/mux_l2_in_1_:A0 1e-06 +3 ropt_mt_inst_733:A 1e-06 +4 chanx_left_in[8]:4 0.0001129568 +5 chanx_left_in[8]:5 0.0001129568 +6 chanx_left_in[8]:6 5.380582e-05 +7 chanx_left_in[8]:7 5.380582e-05 +8 chanx_left_in[8]:8 0.0007866717 +9 chanx_left_in[8]:9 0.0007866717 +10 chanx_left_in[8]:10 5.561199e-05 +11 chanx_left_in[8]:11 5.561199e-05 +12 chanx_left_in[8]:12 0.000151376 +13 chanx_left_in[8]:13 0.000182422 +14 chanx_left_in[8]:14 9.4674e-05 +15 chanx_left_in[8]:15 9.4674e-05 +16 chanx_left_in[8]:16 0.001471891 +17 chanx_left_in[8]:17 0.001471891 +18 chanx_left_in[8]:18 0.0004746668 +19 chanx_left_in[8]:19 0.0004746668 +20 chanx_left_in[8]:20 2.600016e-05 +21 chanx_left_in[8]:21 2.26315e-05 +22 chanx_left_in[8]:22 5.493877e-05 +23 chanx_left_in[8]:23 5.518767e-05 +24 chanx_left_in[8]:24 5.611172e-05 +25 chanx_left_in[8]:25 5.999862e-05 +26 chanx_left_in[8]:26 0.001292836 +27 chanx_left_in[8]:27 3.384276e-05 +28 chanx_left_in[8]:28 4.874376e-05 +29 chanx_left_in[8]:29 5.280035e-05 +30 chanx_left_in[8]:30 0.001649783 +31 chanx_left_in[8]:31 0.0004055791 +32 chanx_left_in[8]:32 0.0002778264 +33 chanx_left_in[8]:33 0.0002778264 +34 chanx_left_in[8]:34 0.0006150554 +35 chanx_left_in[8]:26 chanx_left_in[0]:46 0.0005644749 +36 chanx_left_in[8]:30 chanx_left_in[0]:47 0.0005644749 +37 chanx_left_in[8] chanx_left_in[16] 7.06647e-06 +38 chanx_left_in[8]:10 chanx_left_in[16]:12 1.048949e-06 +39 chanx_left_in[8]:12 chanx_left_in[16]:14 1.414216e-05 +40 chanx_left_in[8]:11 chanx_left_in[16]:13 1.048949e-06 +41 chanx_left_in[8]:13 chanx_left_in[16]:15 1.414216e-05 +42 chanx_left_in[8]:14 chanx_left_in[16]:13 4.238441e-05 +43 chanx_left_in[8]:15 chanx_left_in[16]:12 4.238441e-05 +44 chanx_left_in[8]:16 chanx_left_in[16]:19 0.0002586083 +45 chanx_left_in[8]:17 chanx_left_in[16]:20 0.0002586083 +46 chanx_left_in[8]:34 chanx_left_in[16]:21 7.06647e-06 +47 chanx_left_in[8]:26 chanx_right_in[2]:27 0.0002286186 +48 chanx_left_in[8]:26 chanx_right_in[2]:36 0.001465038 +49 chanx_left_in[8]:26 chanx_right_in[2]:37 3.862565e-06 +50 chanx_left_in[8]:26 chanx_right_in[2]:38 0.000179098 +51 chanx_left_in[8]:29 chanx_right_in[2]:22 1.027577e-05 +52 chanx_left_in[8]:30 chanx_right_in[2]:27 0.001465038 +53 chanx_left_in[8]:30 chanx_right_in[2]:23 0.0002286186 +54 chanx_left_in[8]:30 chanx_right_in[2]:37 0.000179098 +55 chanx_left_in[8]:28 chanx_right_in[2]:21 1.027577e-05 +56 chanx_left_in[8]:21 chanx_right_in[2]:38 3.862565e-06 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:34 0.0012455 +1 chanx_left_in[8]:25 chanx_left_in[8]:24 0.0001634616 +2 chanx_left_in[8]:26 chanx_left_in[8]:25 0.00341 +3 chanx_left_in[8]:26 chanx_left_in[8]:21 1e-05 +4 chanx_left_in[8]:26 chanx_left_in[8]:20 4.402113e-05 +5 chanx_left_in[8]:23 chanx_left_in[8]:22 8.967391e-05 +6 chanx_left_in[8]:24 chanx_left_in[8]:23 0.0045 +7 chanx_left_in[8]:22 mux_bottom_ipin_4\/mux_l2_in_1_:A0 0.152 +8 chanx_left_in[8]:29 chanx_left_in[8]:28 0.0001634615 +9 chanx_left_in[8]:30 chanx_left_in[8]:29 0.00341 +10 chanx_left_in[8]:30 chanx_left_in[8]:26 0.006197732 +11 chanx_left_in[8]:27 mux_bottom_ipin_8\/mux_l1_in_2_:A1 0.152 +12 chanx_left_in[8]:28 chanx_left_in[8]:27 0.0045 +13 chanx_left_in[8]:4 ropt_mt_inst_733:A 0.152 +14 chanx_left_in[8]:5 chanx_left_in[8]:4 0.001569197 +15 chanx_left_in[8]:6 chanx_left_in[8]:5 0.0045 +16 chanx_left_in[8]:7 chanx_left_in[8]:6 0.0005156251 +17 chanx_left_in[8]:8 chanx_left_in[8]:7 0.00341 +18 chanx_left_in[8]:10 chanx_left_in[8]:9 0.00341 +19 chanx_left_in[8]:9 chanx_left_in[8]:8 0.001655183 +20 chanx_left_in[8]:12 chanx_left_in[8]:11 0.0045 +21 chanx_left_in[8]:11 chanx_left_in[8]:10 0.000515625 +22 chanx_left_in[8]:13 chanx_left_in[8]:12 0.002013393 +23 chanx_left_in[8]:14 chanx_left_in[8]:13 0.0045 +24 chanx_left_in[8]:15 chanx_left_in[8]:14 0.001729911 +25 chanx_left_in[8]:16 chanx_left_in[8]:15 0.00341 +26 chanx_left_in[8]:17 chanx_left_in[8]:16 0.003959358 +27 chanx_left_in[8]:18 chanx_left_in[8]:17 0.00341 +28 chanx_left_in[8]:20 chanx_left_in[8]:19 0.00341 +29 chanx_left_in[8]:19 chanx_left_in[8]:18 0.00111625 +30 chanx_left_in[8]:31 chanx_left_in[8]:30 0.0007175333 +31 chanx_left_in[8]:32 chanx_left_in[8]:31 0.00341 +32 chanx_left_in[8]:34 chanx_left_in[8]:33 0.00341 +33 chanx_left_in[8]:33 chanx_left_in[8]:32 0.00063685 + +*END + +*D_NET top_grid_pin_19_[0] 0.0008093852 //LENGTH 6.495 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 35.940 69.700 +*P top_grid_pin_19_[0] O *L 0.7423 *C 36.800 74.870 +*N top_grid_pin_19_[0]:2 *C 36.800 69.745 +*N top_grid_pin_19_[0]:3 *C 36.755 69.700 +*N top_grid_pin_19_[0]:4 *C 35.977 69.700 + +*CAP +0 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_19_[0] 0.0003254163 +2 top_grid_pin_19_[0]:2 0.0003254163 +3 top_grid_pin_19_[0]:3 7.877628e-05 +4 top_grid_pin_19_[0]:4 7.877628e-05 + +*RES +0 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_19_[0]:4 0.152 +1 top_grid_pin_19_[0]:4 top_grid_pin_19_[0]:3 0.0006941964 +2 top_grid_pin_19_[0]:3 top_grid_pin_19_[0]:2 0.0045 +3 top_grid_pin_19_[0]:2 top_grid_pin_19_[0] 0.004575893 + +*END + +*D_NET top_grid_pin_26_[0] 0.001509843 //LENGTH 11.510 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 18.860 69.700 +*P top_grid_pin_26_[0] O *L 0.7423 *C 13.340 74.835 +*N top_grid_pin_26_[0]:2 *C 13.340 70.040 +*N top_grid_pin_26_[0]:3 *C 14.260 70.040 +*N top_grid_pin_26_[0]:4 *C 14.305 70.040 +*N top_grid_pin_26_[0]:5 *C 16.100 70.040 +*N top_grid_pin_26_[0]:6 *C 16.100 69.700 +*N top_grid_pin_26_[0]:7 *C 18.823 69.700 + +*CAP +0 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_26_[0] 0.0002784219 +2 top_grid_pin_26_[0]:2 0.0003414923 +3 top_grid_pin_26_[0]:3 9.934335e-05 +4 top_grid_pin_26_[0]:4 0.0001472843 +5 top_grid_pin_26_[0]:5 0.0001738354 +6 top_grid_pin_26_[0]:6 0.0002475086 +7 top_grid_pin_26_[0]:7 0.0002209575 + +*RES +0 mux_bottom_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_26_[0]:7 0.152 +1 top_grid_pin_26_[0]:7 top_grid_pin_26_[0]:6 0.002430804 +2 top_grid_pin_26_[0]:4 top_grid_pin_26_[0]:3 0.0045 +3 top_grid_pin_26_[0]:3 top_grid_pin_26_[0]:2 0.0008214286 +4 top_grid_pin_26_[0]:5 top_grid_pin_26_[0]:4 0.001602679 +5 top_grid_pin_26_[0]:6 top_grid_pin_26_[0]:5 0.0003035715 +6 top_grid_pin_26_[0]:2 top_grid_pin_26_[0] 0.00428125 + +*END + +*D_NET ccff_tail[0] 0.0006377738 //LENGTH 4.185 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_15\/BUFT_RR_105:X O *L 0 *C 4.140 61.880 +*P ccff_tail[0] O *L 0.7423 *C 1.298 61.200 +*N ccff_tail[0]:2 *C 1.380 61.200 +*N ccff_tail[0]:3 *C 1.380 61.200 +*N ccff_tail[0]:4 *C 1.380 61.200 +*N ccff_tail[0]:5 *C 1.380 61.880 +*N ccff_tail[0]:6 *C 4.103 61.880 + +*CAP +0 mem_bottom_ipin_15\/BUFT_RR_105:X 1e-06 +1 ccff_tail[0] 4.177598e-05 +2 ccff_tail[0]:2 4.177598e-05 +3 ccff_tail[0]:3 3.497703e-05 +4 ccff_tail[0]:4 9.08268e-05 +5 ccff_tail[0]:5 0.0002398177 +6 ccff_tail[0]:6 0.0001876003 + +*RES +0 mem_bottom_ipin_15\/BUFT_RR_105:X ccff_tail[0]:6 0.152 +1 ccff_tail[0]:6 ccff_tail[0]:5 0.002430804 +2 ccff_tail[0]:4 ccff_tail[0]:3 0.0045 +3 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +4 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 +5 ccff_tail[0]:5 ccff_tail[0]:4 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.004194407 //LENGTH 34.070 LUMPCC 0.0004213724 DR + +*CONN +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 55.965 66.300 +*I mux_bottom_ipin_1\/mux_l3_in_1_:S I *L 0.00357 *C 51.180 61.540 +*I mux_bottom_ipin_1\/mux_l3_in_0_:S I *L 0.00357 *C 54.380 58.480 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 42.490 64.260 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 42.528 64.260 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 44.575 64.260 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 44.620 64.305 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 44.620 68.975 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 44.665 69.020 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 52.855 69.020 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 52.900 68.975 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 52.900 66.345 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 52.945 66.300 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 54.280 58.480 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 54.280 58.525 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 51.218 61.540 +*N mux_tree_tapbuf_size10_1_sram[2]:16 *C 54.235 61.540 +*N mux_tree_tapbuf_size10_1_sram[2]:17 *C 54.280 61.540 +*N mux_tree_tapbuf_size10_1_sram[2]:18 *C 54.280 66.255 +*N mux_tree_tapbuf_size10_1_sram[2]:19 *C 54.280 66.300 +*N mux_tree_tapbuf_size10_1_sram[2]:20 *C 55.928 66.300 + +*CAP +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_1\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 0.0001582475 +5 mux_tree_tapbuf_size10_1_sram[2]:5 0.0001582475 +6 mux_tree_tapbuf_size10_1_sram[2]:6 0.0001788806 +7 mux_tree_tapbuf_size10_1_sram[2]:7 0.0001788806 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0005010228 +9 mux_tree_tapbuf_size10_1_sram[2]:9 0.0005010228 +10 mux_tree_tapbuf_size10_1_sram[2]:10 0.0001566625 +11 mux_tree_tapbuf_size10_1_sram[2]:11 0.0001566625 +12 mux_tree_tapbuf_size10_1_sram[2]:12 9.767064e-05 +13 mux_tree_tapbuf_size10_1_sram[2]:13 3.083083e-05 +14 mux_tree_tapbuf_size10_1_sram[2]:14 0.0001724547 +15 mux_tree_tapbuf_size10_1_sram[2]:15 0.0002198096 +16 mux_tree_tapbuf_size10_1_sram[2]:16 0.0002198096 +17 mux_tree_tapbuf_size10_1_sram[2]:17 0.0004575664 +18 mux_tree_tapbuf_size10_1_sram[2]:18 0.0002519345 +19 mux_tree_tapbuf_size10_1_sram[2]:19 0.0002294331 +20 mux_tree_tapbuf_size10_1_sram[2]:20 9.989832e-05 +21 mux_tree_tapbuf_size10_1_sram[2]:15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.444899e-05 +22 mux_tree_tapbuf_size10_1_sram[2]:16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.444899e-05 +23 mux_tree_tapbuf_size10_1_sram[2]:17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.633948e-06 +24 mux_tree_tapbuf_size10_1_sram[2]:14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 3.633948e-06 +25 mux_tree_tapbuf_size10_1_sram[2]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001326032 +26 mux_tree_tapbuf_size10_1_sram[2]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001326032 + +*RES +0 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:20 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:15 mux_bottom_ipin_1\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[2]:15 0.002694196 +3 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:16 0.0045 +4 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:14 0.002691964 +5 mux_tree_tapbuf_size10_1_sram[2]:13 mux_bottom_ipin_1\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.0045 +7 mux_tree_tapbuf_size10_1_sram[2]:20 mux_tree_tapbuf_size10_1_sram[2]:19 0.001470982 +8 mux_tree_tapbuf_size10_1_sram[2]:19 mux_tree_tapbuf_size10_1_sram[2]:18 0.0045 +9 mux_tree_tapbuf_size10_1_sram[2]:19 mux_tree_tapbuf_size10_1_sram[2]:12 0.001191964 +10 mux_tree_tapbuf_size10_1_sram[2]:18 mux_tree_tapbuf_size10_1_sram[2]:17 0.004209822 +11 mux_tree_tapbuf_size10_1_sram[2]:4 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_1_sram[2]:5 mux_tree_tapbuf_size10_1_sram[2]:4 0.001828125 +13 mux_tree_tapbuf_size10_1_sram[2]:6 mux_tree_tapbuf_size10_1_sram[2]:5 0.0045 +14 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.0045 +15 mux_tree_tapbuf_size10_1_sram[2]:7 mux_tree_tapbuf_size10_1_sram[2]:6 0.004169643 +16 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.0073125 +17 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[2]:9 0.0045 +18 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.0045 +19 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:10 0.002348214 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[2] 0.003619816 //LENGTH 28.080 LUMPCC 0.0004733038 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 9.965 36.720 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 4.775 44.540 +*I mux_bottom_ipin_8\/mux_l3_in_0_:S I *L 0.00357 *C 13.900 34.680 +*I mux_bottom_ipin_8\/mux_l3_in_1_:S I *L 0.00357 *C 12.520 41.480 +*N mux_tree_tapbuf_size10_4_sram[2]:4 *C 12.535 41.480 +*N mux_tree_tapbuf_size10_4_sram[2]:5 *C 12.857 41.480 +*N mux_tree_tapbuf_size10_4_sram[2]:6 *C 12.880 41.435 +*N mux_tree_tapbuf_size10_4_sram[2]:7 *C 13.863 34.680 +*N mux_tree_tapbuf_size10_4_sram[2]:8 *C 12.925 34.680 +*N mux_tree_tapbuf_size10_4_sram[2]:9 *C 12.880 34.725 +*N mux_tree_tapbuf_size10_4_sram[2]:10 *C 12.880 39.440 +*N mux_tree_tapbuf_size10_4_sram[2]:11 *C 12.835 39.440 +*N mux_tree_tapbuf_size10_4_sram[2]:12 *C 4.775 44.540 +*N mux_tree_tapbuf_size10_4_sram[2]:13 *C 5.060 44.540 +*N mux_tree_tapbuf_size10_4_sram[2]:14 *C 5.060 44.495 +*N mux_tree_tapbuf_size10_4_sram[2]:15 *C 5.060 38.805 +*N mux_tree_tapbuf_size10_4_sram[2]:16 *C 5.105 38.760 +*N mux_tree_tapbuf_size10_4_sram[2]:17 *C 10.120 38.760 +*N mux_tree_tapbuf_size10_4_sram[2]:18 *C 10.120 39.440 +*N mux_tree_tapbuf_size10_4_sram[2]:19 *C 10.120 39.395 +*N mux_tree_tapbuf_size10_4_sram[2]:20 *C 10.120 36.765 +*N mux_tree_tapbuf_size10_4_sram[2]:21 *C 10.120 36.720 +*N mux_tree_tapbuf_size10_4_sram[2]:22 *C 9.965 36.720 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_8\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_ipin_8\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_4_sram[2]:4 2.883475e-05 +5 mux_tree_tapbuf_size10_4_sram[2]:5 2.883475e-05 +6 mux_tree_tapbuf_size10_4_sram[2]:6 9.60339e-05 +7 mux_tree_tapbuf_size10_4_sram[2]:7 9.826195e-05 +8 mux_tree_tapbuf_size10_4_sram[2]:8 9.826195e-05 +9 mux_tree_tapbuf_size10_4_sram[2]:9 0.0002664049 +10 mux_tree_tapbuf_size10_4_sram[2]:10 0.0003930535 +11 mux_tree_tapbuf_size10_4_sram[2]:11 0.0001848087 +12 mux_tree_tapbuf_size10_4_sram[2]:12 5.487111e-05 +13 mux_tree_tapbuf_size10_4_sram[2]:13 5.960702e-05 +14 mux_tree_tapbuf_size10_4_sram[2]:14 0.0002800486 +15 mux_tree_tapbuf_size10_4_sram[2]:15 0.0002800486 +16 mux_tree_tapbuf_size10_4_sram[2]:16 0.0003359639 +17 mux_tree_tapbuf_size10_4_sram[2]:17 0.000383802 +18 mux_tree_tapbuf_size10_4_sram[2]:18 0.0002326468 +19 mux_tree_tapbuf_size10_4_sram[2]:19 0.0001060045 +20 mux_tree_tapbuf_size10_4_sram[2]:20 0.0001060045 +21 mux_tree_tapbuf_size10_4_sram[2]:21 5.720178e-05 +22 mux_tree_tapbuf_size10_4_sram[2]:22 5.181897e-05 +23 mux_tree_tapbuf_size10_4_sram[2]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.141911e-05 +24 mux_tree_tapbuf_size10_4_sram[2]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.591525e-05 +25 mux_tree_tapbuf_size10_4_sram[2]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.141911e-05 +26 mux_tree_tapbuf_size10_4_sram[2]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.524812e-05 +27 mux_tree_tapbuf_size10_4_sram[2]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.591525e-05 +28 mux_tree_tapbuf_size10_4_sram[2]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.524812e-05 +29 mux_tree_tapbuf_size10_4_sram[2]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.074748e-05 +30 mux_tree_tapbuf_size10_4_sram[2]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.074748e-05 +31 mux_tree_tapbuf_size10_4_sram[2]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.507935e-07 +32 mux_tree_tapbuf_size10_4_sram[2]:9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.949054e-07 +33 mux_tree_tapbuf_size10_4_sram[2]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.507935e-07 +34 mux_tree_tapbuf_size10_4_sram[2]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.949054e-07 +35 mux_tree_tapbuf_size10_4_sram[2]:19 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.936525e-05 +36 mux_tree_tapbuf_size10_4_sram[2]:20 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.936525e-05 +37 mux_tree_tapbuf_size10_4_sram[2]:14 ropt_net_174:5 7.2311e-05 +38 mux_tree_tapbuf_size10_4_sram[2]:15 ropt_net_174:4 7.2311e-05 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_4_sram[2]:22 0.152 +1 mux_tree_tapbuf_size10_4_sram[2]:5 mux_tree_tapbuf_size10_4_sram[2]:4 0.0001752718 +2 mux_tree_tapbuf_size10_4_sram[2]:6 mux_tree_tapbuf_size10_4_sram[2]:5 0.0045 +3 mux_tree_tapbuf_size10_4_sram[2]:4 mux_bottom_ipin_8\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size10_4_sram[2]:8 mux_tree_tapbuf_size10_4_sram[2]:7 0.0008370536 +5 mux_tree_tapbuf_size10_4_sram[2]:9 mux_tree_tapbuf_size10_4_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size10_4_sram[2]:7 mux_bottom_ipin_8\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_4_sram[2]:11 mux_tree_tapbuf_size10_4_sram[2]:10 0.0045 +8 mux_tree_tapbuf_size10_4_sram[2]:10 mux_tree_tapbuf_size10_4_sram[2]:9 0.004209822 +9 mux_tree_tapbuf_size10_4_sram[2]:10 mux_tree_tapbuf_size10_4_sram[2]:6 0.00178125 +10 mux_tree_tapbuf_size10_4_sram[2]:12 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size10_4_sram[2]:13 mux_tree_tapbuf_size10_4_sram[2]:12 0.0001548913 +12 mux_tree_tapbuf_size10_4_sram[2]:14 mux_tree_tapbuf_size10_4_sram[2]:13 0.0045 +13 mux_tree_tapbuf_size10_4_sram[2]:16 mux_tree_tapbuf_size10_4_sram[2]:15 0.0045 +14 mux_tree_tapbuf_size10_4_sram[2]:15 mux_tree_tapbuf_size10_4_sram[2]:14 0.005080358 +15 mux_tree_tapbuf_size10_4_sram[2]:18 mux_tree_tapbuf_size10_4_sram[2]:17 0.0006071429 +16 mux_tree_tapbuf_size10_4_sram[2]:18 mux_tree_tapbuf_size10_4_sram[2]:11 0.002424107 +17 mux_tree_tapbuf_size10_4_sram[2]:19 mux_tree_tapbuf_size10_4_sram[2]:18 0.0045 +18 mux_tree_tapbuf_size10_4_sram[2]:21 mux_tree_tapbuf_size10_4_sram[2]:20 0.0045 +19 mux_tree_tapbuf_size10_4_sram[2]:20 mux_tree_tapbuf_size10_4_sram[2]:19 0.002348214 +20 mux_tree_tapbuf_size10_4_sram[2]:22 mux_tree_tapbuf_size10_4_sram[2]:21 8.423914e-05 +21 mux_tree_tapbuf_size10_4_sram[2]:17 mux_tree_tapbuf_size10_4_sram[2]:16 0.004477679 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[1] 0.005447331 //LENGTH 42.265 LUMPCC 7.347146e-05 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 95.985 55.760 +*I mux_bottom_ipin_13\/mux_l2_in_3_:S I *L 0.00357 *C 93.040 57.800 +*I mux_bottom_ipin_13\/mux_l2_in_0_:S I *L 0.00357 *C 84.980 52.700 +*I mux_bottom_ipin_13\/mux_l2_in_1_:S I *L 0.00357 *C 85.660 58.190 +*I mux_bottom_ipin_13\/mux_l2_in_2_:S I *L 0.00357 *C 91.660 61.880 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 90.330 69.700 +*N mux_tree_tapbuf_size10_7_sram[1]:6 *C 90.368 69.700 +*N mux_tree_tapbuf_size10_7_sram[1]:7 *C 95.635 69.700 +*N mux_tree_tapbuf_size10_7_sram[1]:8 *C 95.680 69.655 +*N mux_tree_tapbuf_size10_7_sram[1]:9 *C 91.698 61.880 +*N mux_tree_tapbuf_size10_7_sram[1]:10 *C 95.175 61.880 +*N mux_tree_tapbuf_size10_7_sram[1]:11 *C 95.220 61.880 +*N mux_tree_tapbuf_size10_7_sram[1]:12 *C 95.680 61.880 +*N mux_tree_tapbuf_size10_7_sram[1]:13 *C 85.017 52.700 +*N mux_tree_tapbuf_size10_7_sram[1]:14 *C 85.515 52.700 +*N mux_tree_tapbuf_size10_7_sram[1]:15 *C 85.560 52.745 +*N mux_tree_tapbuf_size10_7_sram[1]:16 *C 85.560 58.095 +*N mux_tree_tapbuf_size10_7_sram[1]:17 *C 85.560 58.140 +*N mux_tree_tapbuf_size10_7_sram[1]:18 *C 85.660 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:19 *C 93.040 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:20 *C 95.635 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:21 *C 95.680 57.800 +*N mux_tree_tapbuf_size10_7_sram[1]:22 *C 95.680 55.805 +*N mux_tree_tapbuf_size10_7_sram[1]:23 *C 95.680 55.760 +*N mux_tree_tapbuf_size10_7_sram[1]:24 *C 95.985 55.760 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_ipin_13\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_13\/mux_l2_in_2_:S 1e-06 +5 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_7_sram[1]:6 0.0003560408 +7 mux_tree_tapbuf_size10_7_sram[1]:7 0.0003560408 +8 mux_tree_tapbuf_size10_7_sram[1]:8 0.0004161442 +9 mux_tree_tapbuf_size10_7_sram[1]:9 0.0002797403 +10 mux_tree_tapbuf_size10_7_sram[1]:10 0.0002797403 +11 mux_tree_tapbuf_size10_7_sram[1]:11 6.459304e-05 +12 mux_tree_tapbuf_size10_7_sram[1]:12 0.0006916698 +13 mux_tree_tapbuf_size10_7_sram[1]:13 6.100702e-05 +14 mux_tree_tapbuf_size10_7_sram[1]:14 6.100702e-05 +15 mux_tree_tapbuf_size10_7_sram[1]:15 0.0002996456 +16 mux_tree_tapbuf_size10_7_sram[1]:16 0.0002996456 +17 mux_tree_tapbuf_size10_7_sram[1]:17 7.16385e-05 +18 mux_tree_tapbuf_size10_7_sram[1]:18 0.0005843622 +19 mux_tree_tapbuf_size10_7_sram[1]:19 0.0007595248 +20 mux_tree_tapbuf_size10_7_sram[1]:20 0.0001819537 +21 mux_tree_tapbuf_size10_7_sram[1]:21 0.0003931257 +22 mux_tree_tapbuf_size10_7_sram[1]:22 0.0001186436 +23 mux_tree_tapbuf_size10_7_sram[1]:23 4.860243e-05 +24 mux_tree_tapbuf_size10_7_sram[1]:24 4.473377e-05 +25 mux_tree_tapbuf_size10_7_sram[1]:16 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.709017e-05 +26 mux_tree_tapbuf_size10_7_sram[1]:14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.645559e-06 +27 mux_tree_tapbuf_size10_7_sram[1]:15 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.709017e-05 +28 mux_tree_tapbuf_size10_7_sram[1]:13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.645559e-06 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_7_sram[1]:24 0.152 +1 mux_tree_tapbuf_size10_7_sram[1]:20 mux_tree_tapbuf_size10_7_sram[1]:19 0.002316964 +2 mux_tree_tapbuf_size10_7_sram[1]:21 mux_tree_tapbuf_size10_7_sram[1]:20 0.0045 +3 mux_tree_tapbuf_size10_7_sram[1]:21 mux_tree_tapbuf_size10_7_sram[1]:12 0.003642857 +4 mux_tree_tapbuf_size10_7_sram[1]:17 mux_tree_tapbuf_size10_7_sram[1]:16 0.0045 +5 mux_tree_tapbuf_size10_7_sram[1]:17 mux_bottom_ipin_13\/mux_l2_in_1_:S 0.152 +6 mux_tree_tapbuf_size10_7_sram[1]:16 mux_tree_tapbuf_size10_7_sram[1]:15 0.004776786 +7 mux_tree_tapbuf_size10_7_sram[1]:14 mux_tree_tapbuf_size10_7_sram[1]:13 0.0004441965 +8 mux_tree_tapbuf_size10_7_sram[1]:15 mux_tree_tapbuf_size10_7_sram[1]:14 0.0045 +9 mux_tree_tapbuf_size10_7_sram[1]:13 mux_bottom_ipin_13\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_7_sram[1]:7 mux_tree_tapbuf_size10_7_sram[1]:6 0.004703125 +11 mux_tree_tapbuf_size10_7_sram[1]:8 mux_tree_tapbuf_size10_7_sram[1]:7 0.0045 +12 mux_tree_tapbuf_size10_7_sram[1]:6 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:22 0.0045 +14 mux_tree_tapbuf_size10_7_sram[1]:22 mux_tree_tapbuf_size10_7_sram[1]:21 0.00178125 +15 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:23 0.0001657609 +16 mux_tree_tapbuf_size10_7_sram[1]:19 mux_bottom_ipin_13\/mux_l2_in_3_:S 0.152 +17 mux_tree_tapbuf_size10_7_sram[1]:19 mux_tree_tapbuf_size10_7_sram[1]:18 0.006589286 +18 mux_tree_tapbuf_size10_7_sram[1]:9 mux_bottom_ipin_13\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_7_sram[1]:10 mux_tree_tapbuf_size10_7_sram[1]:9 0.003104911 +20 mux_tree_tapbuf_size10_7_sram[1]:11 mux_tree_tapbuf_size10_7_sram[1]:10 0.0045 +21 mux_tree_tapbuf_size10_7_sram[1]:18 mux_tree_tapbuf_size10_7_sram[1]:17 0.0001770833 +22 mux_tree_tapbuf_size10_7_sram[1]:12 mux_tree_tapbuf_size10_7_sram[1]:11 0.0004107143 +23 mux_tree_tapbuf_size10_7_sram[1]:12 mux_tree_tapbuf_size10_7_sram[1]:8 0.006941965 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[2] 0.002716378 //LENGTH 21.620 LUMPCC 0.0001552592 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 78.045 37.060 +*I mux_bottom_ipin_6\/mux_l3_in_0_:S I *L 0.00357 *C 78.760 39.440 +*I mux_bottom_ipin_6\/mux_l3_in_1_:S I *L 0.00357 *C 77.380 44.880 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 70.100 47.940 +*N mux_tree_tapbuf_size8_2_sram[2]:4 *C 70.100 47.940 +*N mux_tree_tapbuf_size8_2_sram[2]:5 *C 70.380 47.940 +*N mux_tree_tapbuf_size8_2_sram[2]:6 *C 70.380 47.895 +*N mux_tree_tapbuf_size8_2_sram[2]:7 *C 70.380 44.925 +*N mux_tree_tapbuf_size8_2_sram[2]:8 *C 70.425 44.880 +*N mux_tree_tapbuf_size8_2_sram[2]:9 *C 77.395 44.880 +*N mux_tree_tapbuf_size8_2_sram[2]:10 *C 77.718 44.880 +*N mux_tree_tapbuf_size8_2_sram[2]:11 *C 77.740 44.835 +*N mux_tree_tapbuf_size8_2_sram[2]:12 *C 77.740 39.440 +*N mux_tree_tapbuf_size8_2_sram[2]:13 *C 78.723 39.440 +*N mux_tree_tapbuf_size8_2_sram[2]:14 *C 78.245 39.440 +*N mux_tree_tapbuf_size8_2_sram[2]:15 *C 78.200 39.395 +*N mux_tree_tapbuf_size8_2_sram[2]:16 *C 78.200 37.105 +*N mux_tree_tapbuf_size8_2_sram[2]:17 *C 78.200 37.060 +*N mux_tree_tapbuf_size8_2_sram[2]:18 *C 78.045 37.060 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_6\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_2_sram[2]:4 4.70199e-05 +5 mux_tree_tapbuf_size8_2_sram[2]:5 5.116957e-05 +6 mux_tree_tapbuf_size8_2_sram[2]:6 0.0001870305 +7 mux_tree_tapbuf_size8_2_sram[2]:7 0.0001870305 +8 mux_tree_tapbuf_size8_2_sram[2]:8 0.0004030028 +9 mux_tree_tapbuf_size8_2_sram[2]:9 0.0004478916 +10 mux_tree_tapbuf_size8_2_sram[2]:10 4.488877e-05 +11 mux_tree_tapbuf_size8_2_sram[2]:11 0.0003131834 +12 mux_tree_tapbuf_size8_2_sram[2]:12 0.0003445153 +13 mux_tree_tapbuf_size8_2_sram[2]:13 5.868388e-05 +14 mux_tree_tapbuf_size8_2_sram[2]:14 5.868388e-05 +15 mux_tree_tapbuf_size8_2_sram[2]:15 0.0001642204 +16 mux_tree_tapbuf_size8_2_sram[2]:16 0.0001328885 +17 mux_tree_tapbuf_size8_2_sram[2]:17 5.996212e-05 +18 mux_tree_tapbuf_size8_2_sram[2]:18 5.694814e-05 +19 mux_tree_tapbuf_size8_2_sram[2]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.762961e-05 +20 mux_tree_tapbuf_size8_2_sram[2]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 7.762961e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_2_sram[2]:18 0.152 +1 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:9 0.0001752717 +2 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:10 0.0045 +3 mux_tree_tapbuf_size8_2_sram[2]:9 mux_bottom_ipin_6\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:8 0.006223215 +5 mux_tree_tapbuf_size8_2_sram[2]:14 mux_tree_tapbuf_size8_2_sram[2]:13 0.0004263393 +6 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:14 0.0045 +7 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:12 0.0004107143 +8 mux_tree_tapbuf_size8_2_sram[2]:13 mux_bottom_ipin_6\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_2_sram[2]:4 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size8_2_sram[2]:5 mux_tree_tapbuf_size8_2_sram[2]:4 0.0001521739 +11 mux_tree_tapbuf_size8_2_sram[2]:6 mux_tree_tapbuf_size8_2_sram[2]:5 0.0045 +12 mux_tree_tapbuf_size8_2_sram[2]:8 mux_tree_tapbuf_size8_2_sram[2]:7 0.0045 +13 mux_tree_tapbuf_size8_2_sram[2]:7 mux_tree_tapbuf_size8_2_sram[2]:6 0.002651786 +14 mux_tree_tapbuf_size8_2_sram[2]:17 mux_tree_tapbuf_size8_2_sram[2]:16 0.0045 +15 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:15 0.002044643 +16 mux_tree_tapbuf_size8_2_sram[2]:18 mux_tree_tapbuf_size8_2_sram[2]:17 8.423914e-05 +17 mux_tree_tapbuf_size8_2_sram[2]:12 mux_tree_tapbuf_size8_2_sram[2]:11 0.004816965 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[2] 0.002621433 //LENGTH 19.590 LUMPCC 0.0001272907 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 27.445 44.540 +*I mux_bottom_ipin_11\/mux_l3_in_0_:S I *L 0.00357 *C 20.800 41.480 +*I mux_bottom_ipin_11\/mux_l3_in_1_:S I *L 0.00357 *C 24.840 36.550 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 28.235 37.060 +*N mux_tree_tapbuf_size8_5_sram[2]:4 *C 28.235 37.060 +*N mux_tree_tapbuf_size8_5_sram[2]:5 *C 28.060 37.400 +*N mux_tree_tapbuf_size8_5_sram[2]:6 *C 24.840 36.550 +*N mux_tree_tapbuf_size8_5_sram[2]:7 *C 24.840 37.400 +*N mux_tree_tapbuf_size8_5_sram[2]:8 *C 26.220 37.400 +*N mux_tree_tapbuf_size8_5_sram[2]:9 *C 26.220 37.445 +*N mux_tree_tapbuf_size8_5_sram[2]:10 *C 20.838 41.480 +*N mux_tree_tapbuf_size8_5_sram[2]:11 *C 26.175 41.480 +*N mux_tree_tapbuf_size8_5_sram[2]:12 *C 26.220 41.480 +*N mux_tree_tapbuf_size8_5_sram[2]:13 *C 26.220 44.495 +*N mux_tree_tapbuf_size8_5_sram[2]:14 *C 26.265 44.540 +*N mux_tree_tapbuf_size8_5_sram[2]:15 *C 27.408 44.540 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_11\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_5_sram[2]:4 5.585793e-05 +5 mux_tree_tapbuf_size8_5_sram[2]:5 0.0001563139 +6 mux_tree_tapbuf_size8_5_sram[2]:6 9.094205e-05 +7 mux_tree_tapbuf_size8_5_sram[2]:7 0.0001638068 +8 mux_tree_tapbuf_size8_5_sram[2]:8 0.0002760901 +9 mux_tree_tapbuf_size8_5_sram[2]:9 0.0002688077 +10 mux_tree_tapbuf_size8_5_sram[2]:10 0.0003166852 +11 mux_tree_tapbuf_size8_5_sram[2]:11 0.0003166852 +12 mux_tree_tapbuf_size8_5_sram[2]:12 0.0004833334 +13 mux_tree_tapbuf_size8_5_sram[2]:13 0.0001820317 +14 mux_tree_tapbuf_size8_5_sram[2]:14 8.979393e-05 +15 mux_tree_tapbuf_size8_5_sram[2]:15 8.979393e-05 +16 mux_tree_tapbuf_size8_5_sram[2]:13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.913633e-06 +17 mux_tree_tapbuf_size8_5_sram[2]:11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.673172e-05 +18 mux_tree_tapbuf_size8_5_sram[2]:12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.913633e-06 +19 mux_tree_tapbuf_size8_5_sram[2]:10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.673172e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_5_sram[2]:15 0.152 +1 mux_tree_tapbuf_size8_5_sram[2]:6 mux_bottom_ipin_11\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_5_sram[2]:8 mux_tree_tapbuf_size8_5_sram[2]:7 0.001232143 +3 mux_tree_tapbuf_size8_5_sram[2]:8 mux_tree_tapbuf_size8_5_sram[2]:5 0.001642857 +4 mux_tree_tapbuf_size8_5_sram[2]:9 mux_tree_tapbuf_size8_5_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size8_5_sram[2]:4 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size8_5_sram[2]:14 mux_tree_tapbuf_size8_5_sram[2]:13 0.0045 +7 mux_tree_tapbuf_size8_5_sram[2]:13 mux_tree_tapbuf_size8_5_sram[2]:12 0.002691964 +8 mux_tree_tapbuf_size8_5_sram[2]:15 mux_tree_tapbuf_size8_5_sram[2]:14 0.001020089 +9 mux_tree_tapbuf_size8_5_sram[2]:11 mux_tree_tapbuf_size8_5_sram[2]:10 0.004765625 +10 mux_tree_tapbuf_size8_5_sram[2]:12 mux_tree_tapbuf_size8_5_sram[2]:11 0.0045 +11 mux_tree_tapbuf_size8_5_sram[2]:12 mux_tree_tapbuf_size8_5_sram[2]:9 0.003602679 +12 mux_tree_tapbuf_size8_5_sram[2]:10 mux_bottom_ipin_11\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size8_5_sram[2]:7 mux_tree_tapbuf_size8_5_sram[2]:6 0.0007589286 +14 mux_tree_tapbuf_size8_5_sram[2]:5 mux_tree_tapbuf_size8_5_sram[2]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_3_ccff_tail[0] 0.0004712235 //LENGTH 3.875 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_7\/FTB_12__51:X O *L 0 *C 23.700 64.600 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 24.945 66.300 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 *C 24.908 66.300 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 *C 24.425 66.300 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 *C 24.380 66.255 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 *C 24.380 64.645 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 *C 24.335 64.600 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 *C 23.738 64.600 + +*CAP +0 mem_bottom_ipin_7\/FTB_12__51:X 1e-06 +1 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 6.632252e-05 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 6.632252e-05 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.0001057741 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.0001057741 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 6.251509e-05 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 6.251509e-05 + +*RES +0 mem_bottom_ipin_7\/FTB_12__51:X mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.0005334822 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 0.0004308036 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008810155 //LENGTH 5.615 LUMPCC 0.0003230725 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_2_:X O *L 0 *C 65.035 33.660 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 64.860 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 64.860 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 64.860 29.240 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 64.860 29.285 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 64.860 33.615 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 64.860 33.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 65.035 33.660 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.354979e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.794192e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001610744 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001610744 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.985961e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.244285e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[10]:16 1.087943e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_left_in[10]:21 1.087943e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_left_in[10]:20 0.000109107 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[10]:19 0.000109107 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_0_sram[3]:7 4.674534e-08 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_0_sram[3]:12 4.150313e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:6 4.674534e-08 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:13 4.150313e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001465518 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007950187 //LENGTH 6.200 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_3_:X O *L 0 *C 48.935 56.440 +*I mux_bottom_ipin_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 50.430 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 50.430 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 50.140 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 50.140 60.475 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 50.140 56.485 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 50.095 56.440 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 48.973 56.440 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.044481e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.564025e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002421415 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002421415 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001013253 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001013253 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_3_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001576087 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0035625 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001002232 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004869818 //LENGTH 3.300 LUMPCC 0.0001091613 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_0_:X O *L 0 *C 50.885 23.460 +*I mux_bottom_ipin_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 51.620 25.500 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 51.520 25.500 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 51.520 25.455 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 51.520 23.505 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 51.475 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 50.922 23.460 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.685801e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.515401e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.515401e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.432723e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.432723e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.344546e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.135173e-06 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.344546e-05 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.135173e-06 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001741072 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000501144 //LENGTH 3.020 LUMPCC 8.339545e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_3_:X O *L 0 *C 50.315 42.840 +*I mux_bottom_ipin_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 50.890 44.200 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 50.890 44.200 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 51.060 44.200 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 51.060 44.155 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 51.060 42.885 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 51.015 42.840 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 50.352 42.840 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.941269e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.70898e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.96285e-05 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.96285e-05 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.999456e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.999456e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.169772e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.169772e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_3_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003153482 //LENGTH 2.475 LUMPCC 6.957391e-05 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l3_in_1_:X O *L 0 *C 11.675 42.500 +*I mux_bottom_ipin_8\/mux_l4_in_0_:A0 I *L 0.001631 *C 9.490 42.500 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 9.527 42.500 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 11.638 42.500 + +*CAP +0 mux_bottom_ipin_8\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001218872 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001218872 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_4_sram[3]:9 3.478696e-05 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_4_sram[3]:10 3.478696e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l3_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_8\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001883928 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004615991 //LENGTH 2.905 LUMPCC 8.688828e-05 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_3_:X O *L 0 *C 17.195 59.160 +*I mux_bottom_ipin_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 16.390 60.520 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 16.428 60.520 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 16.975 60.520 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 17.020 60.475 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 17.020 59.205 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 17.020 59.160 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 17.195 59.160 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.648741e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.648741e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.608439e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.608439e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.514296e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.242429e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.344414e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.344414e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_3_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.510869e-05 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0] 0.006507034 //LENGTH 50.965 LUMPCC 0.001269503 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l4_in_0_:X O *L 0 *C 80.675 23.120 +*I mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 77.875 69.505 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 77.875 69.505 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 77.740 69.360 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 77.740 69.315 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 77.740 62.617 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 77.743 62.560 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 78.185 62.560 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 78.200 62.553 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 78.200 23.128 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 78.220 23.120 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 80.493 23.120 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 80.500 23.120 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 80.500 23.120 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 80.675 23.120 + +*CAP +0 mux_bottom_ipin_12\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.534097e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.641987e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002815919 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002815919 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.409824e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.409824e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.002047079 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.002047079 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001084726 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001084726 +12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 3.399868e-05 +13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 5.299973e-05 +14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.42887e-05 +15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[11]:17 0.0003528617 +16 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[11]:16 0.0003528617 +17 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_right_in[8]:29 0.0001466015 +18 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 chanx_right_in[8]:30 0.0001466015 +19 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001352886 +20 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001352886 + +*RES +0 mux_bottom_ipin_12\/mux_l4_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.336957e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.005979911 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.499219e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.006176583 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.000356025 +12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0045 +13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:13 9.510871e-05 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001852705 //LENGTH 12.665 LUMPCC 0.0008405365 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_2_:X O *L 0 *C 38.815 42.160 +*I mux_bottom_ipin_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 39.925 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 39.925 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 40.020 44.880 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 43.655 44.880 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 43.700 44.835 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 43.700 42.205 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 43.655 42.160 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 38.852 42.160 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.157835e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002510493 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002218386 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001456966 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001456966 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.215449e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.215449e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_left_in[15]:19 0.0001138386 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_left_in[15]:20 7.61498e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[15]:18 0.0001138386 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[15]:19 7.61498e-05 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[7]:13 6.196603e-05 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[7]:14 0.0001280223 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[7]:14 6.196603e-05 +16 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[7]:15 0.0001280223 +17 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 2.670443e-05 +18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 1.358707e-05 +19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 2.670443e-05 +20 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 1.358707e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_2_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.004287947 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002348214 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.003245536 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_1_:A1 0.152 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0] 0.006306771 //LENGTH 57.480 LUMPCC 0.0001537478 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l4_in_0_:X O *L 0 *C 72.395 44.540 +*I mux_bottom_ipin_6\/BUFT_RR_58:A I *L 0.001746 *C 49.680 69.360 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 49.718 69.360 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 51.015 69.360 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 51.060 69.405 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 51.060 73.383 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 51.068 73.440 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 69.900 73.440 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 69.920 73.433 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 69.920 44.888 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 69.940 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 72.213 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 72.220 44.880 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 72.220 44.540 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 72.220 44.540 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:15 *C 72.395 44.540 + +*CAP +0 mux_bottom_ipin_6\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/BUFT_RR_58:A 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001177656 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001177656 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001572303 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001572303 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0009029249 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0009029249 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.001615412 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.001615412 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001657479 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001657479 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 5.973826e-05 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 5.478473e-05 +14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 5.89929e-05 +15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:15 5.934497e-05 +16 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_134:8 7.687388e-05 +17 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 ropt_net_134:9 7.687388e-05 + +*RES +0 mux_bottom_ipin_6\/mux_l4_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:15 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:15 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 9.51087e-05 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.000125 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.000356025 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.00447205 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002950425 +9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +10 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.003551339 +11 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +12 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001158482 +13 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_6\/BUFT_RR_58:A 0.152 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003480844 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l3_in_1_:X O *L 0 *C 19.495 17.000 +*I mux_bottom_ipin_10\/mux_l4_in_0_:A0 I *L 0.001631 *C 17.310 17.000 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 17.348 17.000 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 19.457 17.000 + +*CAP +0 mux_bottom_ipin_10\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001730422 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001730422 + +*RES +0 mux_bottom_ipin_10\/mux_l3_in_1_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_10\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001133306 //LENGTH 9.060 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_1_:X O *L 0 *C 21.445 34.340 +*I mux_bottom_ipin_11\/mux_l3_in_0_:A0 I *L 0.001631 *C 21.910 42.500 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 21.910 42.500 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 21.620 42.500 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 21.620 42.455 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 21.620 34.385 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 21.620 34.340 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 21.445 34.340 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.529566e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.720253e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004495443 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004495443 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.825352e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.146591e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_1_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001576087 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.007205357 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004148415 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_3_:X O *L 0 *C 86.195 42.840 +*I mux_bottom_ipin_14\/mux_l3_in_1_:A0 I *L 0.001631 *C 86.770 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 86.770 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 86.480 44.200 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 86.480 44.155 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 86.480 42.885 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 86.480 42.840 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 86.195 42.840 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.105321e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.551049e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.459471e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.459471e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.766525e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.942313e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_3_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001576087 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133929 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004791301 //LENGTH 3.300 LUMPCC 0.0001216874 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_2_:X O *L 0 *C 70.095 61.540 +*I mux_bottom_ipin_15\/mux_l3_in_1_:A1 I *L 0.00198 *C 69.460 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 69.460 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 69.460 63.535 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 69.460 61.585 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 69.505 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 70.058 61.540 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.265329e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.436721e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.436721e-05 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.702749e-05 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.702749e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.084368e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.084368e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_2_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004933036 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001741071 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_1_:A1 0.152 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_151 0.002094744 //LENGTH 16.555 LUMPCC 0.000376191 DR + +*CONN +*I FTB_6__5:X O *L 0 *C 97.060 52.700 +*I ropt_mt_inst_748:A I *L 0.001766 *C 97.825 58.480 +*N ropt_net_151:2 *C 97.825 58.480 +*N ropt_net_151:3 *C 97.980 58.480 +*N ropt_net_151:4 *C 97.980 58.525 +*N ropt_net_151:5 *C 97.980 59.783 +*N ropt_net_151:6 *C 97.988 59.840 +*N ropt_net_151:7 *C 100.733 59.840 +*N ropt_net_151:8 *C 100.740 59.783 +*N ropt_net_151:9 *C 100.740 52.745 +*N ropt_net_151:10 *C 100.695 52.700 +*N ropt_net_151:11 *C 97.098 52.700 + +*CAP +0 FTB_6__5:X 1e-06 +1 ropt_mt_inst_748:A 1e-06 +2 ropt_net_151:2 5.674377e-05 +3 ropt_net_151:3 5.676705e-05 +4 ropt_net_151:4 8.664164e-05 +5 ropt_net_151:5 8.664164e-05 +6 ropt_net_151:6 0.0001372934 +7 ropt_net_151:7 0.0001372934 +8 ropt_net_151:8 0.0003952337 +9 ropt_net_151:9 0.0003952337 +10 ropt_net_151:10 0.0001823522 +11 ropt_net_151:11 0.0001823522 +12 ropt_net_151:6 chanx_right_in[17]:26 7.337549e-05 +13 ropt_net_151:7 chanx_right_in[17] 7.337549e-05 +14 ropt_net_151:8 ropt_net_156:4 1.776935e-05 +15 ropt_net_151:10 ropt_net_156:3 9.695065e-05 +16 ropt_net_151:9 ropt_net_156:5 1.776935e-05 +17 ropt_net_151:11 ropt_net_156:2 9.695065e-05 + +*RES +0 FTB_6__5:X ropt_net_151:11 0.152 +1 ropt_net_151:2 ropt_mt_inst_748:A 0.152 +2 ropt_net_151:3 ropt_net_151:2 8.423914e-05 +3 ropt_net_151:4 ropt_net_151:3 0.0045 +4 ropt_net_151:5 ropt_net_151:4 0.001122768 +5 ropt_net_151:6 ropt_net_151:5 0.00341 +6 ropt_net_151:8 ropt_net_151:7 0.00341 +7 ropt_net_151:7 ropt_net_151:6 0.00043005 +8 ropt_net_151:10 ropt_net_151:9 0.0045 +9 ropt_net_151:9 ropt_net_151:8 0.006283482 +10 ropt_net_151:11 ropt_net_151:10 0.003212054 + +*END + +*D_NET ropt_net_154 0.001070755 //LENGTH 8.540 LUMPCC 0.0001422955 DR + +*CONN +*I FTB_18__17:X O *L 0 *C 98.440 34.680 +*I ropt_mt_inst_751:A I *L 0.001766 *C 97.980 28.560 +*N ropt_net_154:2 *C 98.017 28.560 +*N ropt_net_154:3 *C 98.855 28.560 +*N ropt_net_154:4 *C 98.900 28.605 +*N ropt_net_154:5 *C 98.900 34.295 +*N ropt_net_154:6 *C 98.855 34.340 +*N ropt_net_154:7 *C 98.440 34.340 +*N ropt_net_154:8 *C 98.440 34.680 + +*CAP +0 FTB_18__17:X 1e-06 +1 ropt_mt_inst_751:A 1e-06 +2 ropt_net_154:2 8.067393e-05 +3 ropt_net_154:3 8.067393e-05 +4 ropt_net_154:4 0.000295926 +5 ropt_net_154:5 0.000295926 +6 ropt_net_154:6 4.211914e-05 +7 ropt_net_154:7 7.13623e-05 +8 ropt_net_154:8 5.977783e-05 +9 ropt_net_154:4 ropt_net_164:5 7.114775e-05 +10 ropt_net_154:5 ropt_net_164:4 7.114775e-05 + +*RES +0 FTB_18__17:X ropt_net_154:8 0.152 +1 ropt_net_154:2 ropt_mt_inst_751:A 0.152 +2 ropt_net_154:3 ropt_net_154:2 0.0007477679 +3 ropt_net_154:4 ropt_net_154:3 0.0045 +4 ropt_net_154:6 ropt_net_154:5 0.0045 +5 ropt_net_154:5 ropt_net_154:4 0.005080357 +6 ropt_net_154:8 ropt_net_154:7 0.0003035715 +7 ropt_net_154:7 ropt_net_154:6 0.0003705357 + +*END + +*D_NET ropt_net_186 0.0008518574 //LENGTH 7.250 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 101.855 17.000 +*I ropt_mt_inst_793:A I *L 0.001767 *C 97.825 14.960 +*N ropt_net_186:2 *C 97.863 14.960 +*N ropt_net_186:3 *C 102.075 14.960 +*N ropt_net_186:4 *C 102.120 15.005 +*N ropt_net_186:5 *C 102.120 16.955 +*N ropt_net_186:6 *C 102.120 17.000 +*N ropt_net_186:7 *C 101.855 17.000 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 ropt_mt_inst_793:A 1e-06 +2 ropt_net_186:2 0.0002466426 +3 ropt_net_186:3 0.0002466426 +4 ropt_net_186:4 0.0001239582 +5 ropt_net_186:5 0.0001239582 +6 ropt_net_186:6 5.023181e-05 +7 ropt_net_186:7 5.842403e-05 + +*RES +0 ropt_mt_inst_740:X ropt_net_186:7 0.152 +1 ropt_net_186:2 ropt_mt_inst_793:A 0.152 +2 ropt_net_186:3 ropt_net_186:2 0.003761161 +3 ropt_net_186:4 ropt_net_186:3 0.0045 +4 ropt_net_186:6 ropt_net_186:5 0.0045 +5 ropt_net_186:5 ropt_net_186:4 0.001741072 +6 ropt_net_186:7 ropt_net_186:6 0.0001440218 + +*END + +*D_NET ropt_net_184 0.0008687002 //LENGTH 6.745 LUMPCC 0.0001102644 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 97.255 6.120 +*I ropt_mt_inst_791:A I *L 0.001767 *C 93.380 4.080 +*N ropt_net_184:2 *C 93.380 4.080 +*N ropt_net_184:3 *C 93.380 4.420 +*N ropt_net_184:4 *C 97.015 4.420 +*N ropt_net_184:5 *C 97.060 4.465 +*N ropt_net_184:6 *C 97.060 6.075 +*N ropt_net_184:7 *C 97.060 6.120 +*N ropt_net_184:8 *C 97.255 6.120 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_184:2 4.90405e-05 +3 ropt_net_184:3 0.0002054613 +4 ropt_net_184:4 0.0001810672 +5 ropt_net_184:5 0.0001010159 +6 ropt_net_184:6 0.0001010159 +7 ropt_net_184:7 5.771197e-05 +8 ropt_net_184:8 6.112298e-05 +9 ropt_net_184:4 chanx_right_out[16]:4 5.513222e-05 +10 ropt_net_184:3 chanx_right_out[16]:5 5.513222e-05 + +*RES +0 ropt_mt_inst_745:X ropt_net_184:8 0.152 +1 ropt_net_184:2 ropt_mt_inst_791:A 0.152 +2 ropt_net_184:4 ropt_net_184:3 0.003245536 +3 ropt_net_184:5 ropt_net_184:4 0.0045 +4 ropt_net_184:7 ropt_net_184:6 0.0045 +5 ropt_net_184:6 ropt_net_184:5 0.0014375 +6 ropt_net_184:8 ropt_net_184:7 0.0001059783 +7 ropt_net_184:3 ropt_net_184:2 0.0003035715 + +*END + +*D_NET chanx_left_out[17] 0.001852016 //LENGTH 10.660 LUMPCC 0.0006313804 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 8.740 8.840 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 6.800 +*N chanx_left_out[17]:2 *C 1.840 6.800 +*N chanx_left_out[17]:3 *C 1.840 7.480 +*N chanx_left_out[17]:4 *C 8.732 7.480 +*N chanx_left_out[17]:5 *C 8.740 7.538 +*N chanx_left_out[17]:6 *C 8.740 8.795 +*N chanx_left_out[17]:7 *C 8.740 8.840 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 chanx_left_out[17] 6.688519e-05 +2 chanx_left_out[17]:2 0.0001262615 +3 chanx_left_out[17]:3 0.0004557943 +4 chanx_left_out[17]:4 0.0003964179 +5 chanx_left_out[17]:5 7.115708e-05 +6 chanx_left_out[17]:6 7.115708e-05 +7 chanx_left_out[17]:7 3.196303e-05 +8 chanx_left_out[17]:6 ropt_net_147:8 1.86481e-05 +9 chanx_left_out[17]:5 ropt_net_147:7 1.86481e-05 +10 chanx_left_out[17]:4 ropt_net_147:6 0.0002255958 +11 chanx_left_out[17]:3 ropt_net_147:5 0.0002255958 +12 chanx_left_out[17]:4 ropt_net_133:6 7.144621e-05 +13 chanx_left_out[17]:3 ropt_net_133:5 7.144621e-05 + +*RES +0 ropt_mt_inst_779:X chanx_left_out[17]:7 0.152 +1 chanx_left_out[17]:7 chanx_left_out[17]:6 0.0045 +2 chanx_left_out[17]:6 chanx_left_out[17]:5 0.001122768 +3 chanx_left_out[17]:5 chanx_left_out[17]:4 0.00341 +4 chanx_left_out[17]:4 chanx_left_out[17]:3 0.001079825 +5 chanx_left_out[17]:2 chanx_left_out[17] 9.556665e-05 +6 chanx_left_out[17]:3 chanx_left_out[17]:2 0.0001065333 + +*END + +*D_NET mem_bottom_ipin_15/net_net_75 0.009256682 //LENGTH 59.275 LUMPCC 0.004708729 DR + +*CONN +*I mem_bottom_ipin_15\/FTB_16__55:X O *L 0 *C 56.805 64.600 +*I mem_bottom_ipin_15\/BUFT_RR_75:A I *L 0.001743 *C 5.520 69.360 +*N mem_bottom_ipin_15/net_net_75:2 *C 5.482 69.360 +*N mem_bottom_ipin_15/net_net_75:3 *C 4.645 69.360 +*N mem_bottom_ipin_15/net_net_75:4 *C 4.600 69.315 +*N mem_bottom_ipin_15/net_net_75:5 *C 4.600 66.017 +*N mem_bottom_ipin_15/net_net_75:6 *C 4.607 65.960 +*N mem_bottom_ipin_15/net_net_75:7 *C 56.573 65.960 +*N mem_bottom_ipin_15/net_net_75:8 *C 56.580 65.903 +*N mem_bottom_ipin_15/net_net_75:9 *C 56.580 64.645 +*N mem_bottom_ipin_15/net_net_75:10 *C 56.580 64.600 +*N mem_bottom_ipin_15/net_net_75:11 *C 56.805 64.600 + +*CAP +0 mem_bottom_ipin_15\/FTB_16__55:X 1e-06 +1 mem_bottom_ipin_15\/BUFT_RR_75:A 1e-06 +2 mem_bottom_ipin_15/net_net_75:2 6.723625e-05 +3 mem_bottom_ipin_15/net_net_75:3 6.723625e-05 +4 mem_bottom_ipin_15/net_net_75:4 0.0002393038 +5 mem_bottom_ipin_15/net_net_75:5 0.0002393038 +6 mem_bottom_ipin_15/net_net_75:6 0.001817331 +7 mem_bottom_ipin_15/net_net_75:7 0.001817331 +8 mem_bottom_ipin_15/net_net_75:8 8.678401e-05 +9 mem_bottom_ipin_15/net_net_75:9 8.678401e-05 +10 mem_bottom_ipin_15/net_net_75:10 6.269805e-05 +11 mem_bottom_ipin_15/net_net_75:11 6.194499e-05 +12 mem_bottom_ipin_15/net_net_75:7 chanx_right_in[4]:8 0.0003533658 +13 mem_bottom_ipin_15/net_net_75:6 chanx_right_in[4]:7 0.0003533658 +14 mem_bottom_ipin_15/net_net_75:7 chanx_right_in[5]:11 0.0002530075 +15 mem_bottom_ipin_15/net_net_75:6 chanx_right_in[5]:10 0.0002530075 +16 mem_bottom_ipin_15/net_net_75:7 chanx_right_in[11]:31 0.0002683882 +17 mem_bottom_ipin_15/net_net_75:7 chanx_right_in[11]:32 4.168317e-05 +18 mem_bottom_ipin_15/net_net_75:6 chanx_right_in[11]:26 0.0002683882 +19 mem_bottom_ipin_15/net_net_75:6 chanx_right_in[11]:31 4.168317e-05 +20 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:172 2.398543e-06 +21 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:178 0.000369801 +22 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:182 0.0004177893 +23 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:336 2.977531e-05 +24 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:346 0.0001952722 +25 mem_bottom_ipin_15/net_net_75:7 prog_clk[0]:351 0.000169803 +26 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:173 2.398543e-06 +27 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:182 0.000369801 +28 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:183 0.0004177893 +29 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:337 2.977531e-05 +30 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:351 0.0001952722 +31 mem_bottom_ipin_15/net_net_75:6 prog_clk[0]:352 0.000169803 +32 mem_bottom_ipin_15/net_net_75:7 mux_tree_tapbuf_size10_4_sram[0]:28 0.0002474861 +33 mem_bottom_ipin_15/net_net_75:7 mux_tree_tapbuf_size10_4_sram[0]:32 5.594386e-06 +34 mem_bottom_ipin_15/net_net_75:6 mux_tree_tapbuf_size10_4_sram[0]:27 0.0002474861 +35 mem_bottom_ipin_15/net_net_75:6 mux_tree_tapbuf_size10_4_sram[0]:31 5.594386e-06 + +*RES +0 mem_bottom_ipin_15\/FTB_16__55:X mem_bottom_ipin_15/net_net_75:11 0.152 +1 mem_bottom_ipin_15/net_net_75:11 mem_bottom_ipin_15/net_net_75:10 0.0001222826 +2 mem_bottom_ipin_15/net_net_75:10 mem_bottom_ipin_15/net_net_75:9 0.0045 +3 mem_bottom_ipin_15/net_net_75:9 mem_bottom_ipin_15/net_net_75:8 0.001122768 +4 mem_bottom_ipin_15/net_net_75:8 mem_bottom_ipin_15/net_net_75:7 0.00341 +5 mem_bottom_ipin_15/net_net_75:7 mem_bottom_ipin_15/net_net_75:6 0.008141182 +6 mem_bottom_ipin_15/net_net_75:5 mem_bottom_ipin_15/net_net_75:4 0.002944197 +7 mem_bottom_ipin_15/net_net_75:6 mem_bottom_ipin_15/net_net_75:5 0.00341 +8 mem_bottom_ipin_15/net_net_75:3 mem_bottom_ipin_15/net_net_75:2 0.0007477679 +9 mem_bottom_ipin_15/net_net_75:4 mem_bottom_ipin_15/net_net_75:3 0.0045 +10 mem_bottom_ipin_15/net_net_75:2 mem_bottom_ipin_15\/BUFT_RR_75:A 0.152 + +*END + +*D_NET chanx_left_out[13] 0.001557991 //LENGTH 13.670 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 13.800 6.800 +*P chanx_left_out[13] O *L 0.7423 *C 6.440 1.290 +*N chanx_left_out[13]:2 *C 6.440 1.995 +*N chanx_left_out[13]:3 *C 6.485 2.040 +*N chanx_left_out[13]:4 *C 13.755 2.040 +*N chanx_left_out[13]:5 *C 13.800 2.085 +*N chanx_left_out[13]:6 *C 13.800 6.755 +*N chanx_left_out[13]:7 *C 13.800 6.800 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 chanx_left_out[13] 5.293436e-05 +2 chanx_left_out[13]:2 5.293436e-05 +3 chanx_left_out[13]:3 0.0004520762 +4 chanx_left_out[13]:4 0.0004520762 +5 chanx_left_out[13]:5 0.0002589179 +6 chanx_left_out[13]:6 0.0002589179 +7 chanx_left_out[13]:7 2.913438e-05 + +*RES +0 ropt_mt_inst_796:X chanx_left_out[13]:7 0.152 +1 chanx_left_out[13]:7 chanx_left_out[13]:6 0.0045 +2 chanx_left_out[13]:6 chanx_left_out[13]:5 0.004169643 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.006491072 +4 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +5 chanx_left_out[13]:3 chanx_left_out[13]:2 0.0045 +6 chanx_left_out[13]:2 chanx_left_out[13] 0.0006294643 + +*END + +*D_NET chanx_left_in[9] 0.01615582 //LENGTH 112.830 LUMPCC 0.003828846 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_ipin_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 55.490 44.540 +*I BUFT_P_96:A I *L 0.001767 *C 97.980 42.160 +*I mux_bottom_ipin_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 13.800 45.220 +*N chanx_left_in[9]:4 *C 13.763 45.220 +*N chanx_left_in[9]:5 *C 13.340 45.220 +*N chanx_left_in[9]:6 *C 97.943 42.160 +*N chanx_left_in[9]:7 *C 69.920 42.160 +*N chanx_left_in[9]:8 *C 69.920 42.500 +*N chanx_left_in[9]:9 *C 63.525 42.500 +*N chanx_left_in[9]:10 *C 63.480 42.545 +*N chanx_left_in[9]:11 *C 63.480 44.143 +*N chanx_left_in[9]:12 *C 63.473 44.200 +*N chanx_left_in[9]:13 *C 55.528 44.540 +*N chanx_left_in[9]:14 *C 57.455 44.540 +*N chanx_left_in[9]:15 *C 57.500 44.540 +*N chanx_left_in[9]:16 *C 57.500 44.200 +*N chanx_left_in[9]:17 *C 57.500 44.200 +*N chanx_left_in[9]:18 *C 21.168 44.200 +*N chanx_left_in[9]:19 *C 21.160 44.200 +*N chanx_left_in[9]:20 *C 21.115 44.200 +*N chanx_left_in[9]:21 *C 13.340 44.200 +*N chanx_left_in[9]:22 *C 7.865 44.200 +*N chanx_left_in[9]:23 *C 7.820 44.155 +*N chanx_left_in[9]:24 *C 7.820 36.778 +*N chanx_left_in[9]:25 *C 7.812 36.720 + +*CAP +0 chanx_left_in[9] 0.000531009 +1 mux_bottom_ipin_5\/mux_l2_in_1_:A0 1e-06 +2 BUFT_P_96:A 1e-06 +3 mux_bottom_ipin_9\/mux_l1_in_2_:A1 1e-06 +4 chanx_left_in[9]:4 4.804852e-05 +5 chanx_left_in[9]:5 0.0001070834 +6 chanx_left_in[9]:6 0.001373567 +7 chanx_left_in[9]:7 0.001398144 +8 chanx_left_in[9]:8 0.0003988007 +9 chanx_left_in[9]:9 0.000374224 +10 chanx_left_in[9]:10 0.0001161277 +11 chanx_left_in[9]:11 0.0001161277 +12 chanx_left_in[9]:12 0.0002802207 +13 chanx_left_in[9]:13 0.0001864933 +14 chanx_left_in[9]:14 0.0001864933 +15 chanx_left_in[9]:15 5.479671e-05 +16 chanx_left_in[9]:16 5.909844e-05 +17 chanx_left_in[9]:17 0.001964088 +18 chanx_left_in[9]:18 0.001683867 +19 chanx_left_in[9]:19 3.625883e-05 +20 chanx_left_in[9]:20 0.0005409592 +21 chanx_left_in[9]:21 0.000961035 +22 chanx_left_in[9]:22 0.0003610409 +23 chanx_left_in[9]:23 0.000507741 +24 chanx_left_in[9]:24 0.000507741 +25 chanx_left_in[9]:25 0.000531009 +26 chanx_left_in[9]:9 chanx_left_in[4]:17 0.0001251598 +27 chanx_left_in[9]:6 chanx_left_in[4]:16 0.0001061256 +28 chanx_left_in[9]:18 chanx_left_in[4]:31 0.0004658417 +29 chanx_left_in[9]:17 chanx_left_in[4]:30 0.0004658417 +30 chanx_left_in[9]:8 chanx_left_in[4]:16 0.0001251598 +31 chanx_left_in[9]:7 chanx_left_in[4]:17 0.0001061256 +32 chanx_left_in[9]:12 chanx_right_in[7]:19 0.0001013504 +33 chanx_left_in[9]:18 chanx_right_in[7]:18 0.0002404814 +34 chanx_left_in[9]:17 chanx_right_in[7]:19 0.0002404814 +35 chanx_left_in[9]:17 chanx_right_in[7]:18 0.0001013504 +36 chanx_left_in[9]:6 chanx_right_in[18]:24 0.0001456496 +37 chanx_left_in[9]:18 chanx_right_in[18]:16 0.0001391047 +38 chanx_left_in[9]:17 chanx_right_in[18]:17 0.0001391047 +39 chanx_left_in[9]:7 chanx_right_in[18]:23 0.0001456496 +40 chanx_left_in[9]:12 mux_tree_tapbuf_size10_3_sram[3]:12 0.0001247602 +41 chanx_left_in[9]:18 mux_tree_tapbuf_size10_3_sram[3]:11 0.0001414849 +42 chanx_left_in[9]:17 mux_tree_tapbuf_size10_3_sram[3]:11 0.0001247602 +43 chanx_left_in[9]:17 mux_tree_tapbuf_size10_3_sram[3]:12 0.0001414849 +44 chanx_left_in[9]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001221677 +45 chanx_left_in[9]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001221677 +46 chanx_left_in[9]:6 optlc_net_127:8 0.0001854676 +47 chanx_left_in[9]:6 optlc_net_127:14 1.682945e-05 +48 chanx_left_in[9]:7 optlc_net_127:7 0.0001854676 +49 chanx_left_in[9]:7 optlc_net_127:13 1.682945e-05 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:25 0.001031258 +1 chanx_left_in[9]:11 chanx_left_in[9]:10 0.001426339 +2 chanx_left_in[9]:12 chanx_left_in[9]:11 0.00341 +3 chanx_left_in[9]:9 chanx_left_in[9]:8 0.005709821 +4 chanx_left_in[9]:10 chanx_left_in[9]:9 0.0045 +5 chanx_left_in[9]:6 BUFT_P_96:A 0.152 +6 chanx_left_in[9]:19 chanx_left_in[9]:18 0.00341 +7 chanx_left_in[9]:18 chanx_left_in[9]:17 0.005692091 +8 chanx_left_in[9]:20 chanx_left_in[9]:19 0.0045 +9 chanx_left_in[9]:16 chanx_left_in[9]:15 0.0001634615 +10 chanx_left_in[9]:17 chanx_left_in[9]:16 0.00341 +11 chanx_left_in[9]:17 chanx_left_in[9]:12 0.0009356916 +12 chanx_left_in[9]:14 chanx_left_in[9]:13 0.001720982 +13 chanx_left_in[9]:15 chanx_left_in[9]:14 0.0045 +14 chanx_left_in[9]:13 mux_bottom_ipin_5\/mux_l2_in_1_:A0 0.152 +15 chanx_left_in[9]:4 mux_bottom_ipin_9\/mux_l1_in_2_:A1 0.152 +16 chanx_left_in[9]:22 chanx_left_in[9]:21 0.004888393 +17 chanx_left_in[9]:23 chanx_left_in[9]:22 0.0045 +18 chanx_left_in[9]:24 chanx_left_in[9]:23 0.006587054 +19 chanx_left_in[9]:25 chanx_left_in[9]:24 0.00341 +20 chanx_left_in[9]:21 chanx_left_in[9]:20 0.006941964 +21 chanx_left_in[9]:21 chanx_left_in[9]:5 0.0009107143 +22 chanx_left_in[9]:5 chanx_left_in[9]:4 0.0003772322 +23 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0003035715 +24 chanx_left_in[9]:7 chanx_left_in[9]:6 0.02502009 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[0] 0.003743768 //LENGTH 29.905 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.065 39.100 +*I mux_bottom_ipin_4\/mux_l1_in_0_:S I *L 0.00357 *C 46.340 28.900 +*I mux_bottom_ipin_4\/mux_l1_in_1_:S I *L 0.00357 *C 45.900 23.120 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 45.715 17.340 +*I mux_bottom_ipin_4\/mux_l1_in_2_:S I *L 0.00357 *C 50.960 34.680 +*N mux_tree_tapbuf_size10_2_sram[0]:5 *C 50.922 34.680 +*N mux_tree_tapbuf_size10_2_sram[0]:6 *C 45.715 17.340 +*N mux_tree_tapbuf_size10_2_sram[0]:7 *C 46.000 17.340 +*N mux_tree_tapbuf_size10_2_sram[0]:8 *C 46.000 17.385 +*N mux_tree_tapbuf_size10_2_sram[0]:9 *C 45.900 23.120 +*N mux_tree_tapbuf_size10_2_sram[0]:10 *C 46.000 22.780 +*N mux_tree_tapbuf_size10_2_sram[0]:11 *C 46.000 22.780 +*N mux_tree_tapbuf_size10_2_sram[0]:12 *C 46.325 28.900 +*N mux_tree_tapbuf_size10_2_sram[0]:13 *C 46.023 28.900 +*N mux_tree_tapbuf_size10_2_sram[0]:14 *C 46.000 28.900 +*N mux_tree_tapbuf_size10_2_sram[0]:15 *C 46.000 34.295 +*N mux_tree_tapbuf_size10_2_sram[0]:16 *C 46.045 34.340 +*N mux_tree_tapbuf_size10_2_sram[0]:17 *C 48.760 34.340 +*N mux_tree_tapbuf_size10_2_sram[0]:18 *C 48.760 34.680 +*N mux_tree_tapbuf_size10_2_sram[0]:19 *C 48.760 34.725 +*N mux_tree_tapbuf_size10_2_sram[0]:20 *C 48.760 39.055 +*N mux_tree_tapbuf_size10_2_sram[0]:21 *C 48.760 39.100 +*N mux_tree_tapbuf_size10_2_sram[0]:22 *C 49.065 39.100 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_ipin_4\/mux_l1_in_1_:S 1e-06 +3 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_ipin_4\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_2_sram[0]:5 0.0001971669 +6 mux_tree_tapbuf_size10_2_sram[0]:6 4.593472e-05 +7 mux_tree_tapbuf_size10_2_sram[0]:7 4.984998e-05 +8 mux_tree_tapbuf_size10_2_sram[0]:8 0.0003148266 +9 mux_tree_tapbuf_size10_2_sram[0]:9 7.116815e-05 +10 mux_tree_tapbuf_size10_2_sram[0]:10 7.393481e-05 +11 mux_tree_tapbuf_size10_2_sram[0]:11 0.0006572325 +12 mux_tree_tapbuf_size10_2_sram[0]:12 4.165716e-05 +13 mux_tree_tapbuf_size10_2_sram[0]:13 4.165716e-05 +14 mux_tree_tapbuf_size10_2_sram[0]:14 0.000644111 +15 mux_tree_tapbuf_size10_2_sram[0]:15 0.0002979158 +16 mux_tree_tapbuf_size10_2_sram[0]:16 0.0002238993 +17 mux_tree_tapbuf_size10_2_sram[0]:17 0.0002520985 +18 mux_tree_tapbuf_size10_2_sram[0]:18 0.000225366 +19 mux_tree_tapbuf_size10_2_sram[0]:19 0.0002471473 +20 mux_tree_tapbuf_size10_2_sram[0]:20 0.0002471473 +21 mux_tree_tapbuf_size10_2_sram[0]:21 5.583242e-05 +22 mux_tree_tapbuf_size10_2_sram[0]:22 5.182222e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_2_sram[0]:22 0.152 +1 mux_tree_tapbuf_size10_2_sram[0]:12 mux_bottom_ipin_4\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[0]:13 mux_tree_tapbuf_size10_2_sram[0]:12 0.0001644022 +3 mux_tree_tapbuf_size10_2_sram[0]:14 mux_tree_tapbuf_size10_2_sram[0]:13 0.0045 +4 mux_tree_tapbuf_size10_2_sram[0]:14 mux_tree_tapbuf_size10_2_sram[0]:11 0.005464286 +5 mux_tree_tapbuf_size10_2_sram[0]:16 mux_tree_tapbuf_size10_2_sram[0]:15 0.0045 +6 mux_tree_tapbuf_size10_2_sram[0]:15 mux_tree_tapbuf_size10_2_sram[0]:14 0.004816964 +7 mux_tree_tapbuf_size10_2_sram[0]:18 mux_tree_tapbuf_size10_2_sram[0]:17 0.0003035715 +8 mux_tree_tapbuf_size10_2_sram[0]:18 mux_tree_tapbuf_size10_2_sram[0]:5 0.001930804 +9 mux_tree_tapbuf_size10_2_sram[0]:19 mux_tree_tapbuf_size10_2_sram[0]:18 0.0045 +10 mux_tree_tapbuf_size10_2_sram[0]:21 mux_tree_tapbuf_size10_2_sram[0]:20 0.0045 +11 mux_tree_tapbuf_size10_2_sram[0]:20 mux_tree_tapbuf_size10_2_sram[0]:19 0.003866071 +12 mux_tree_tapbuf_size10_2_sram[0]:22 mux_tree_tapbuf_size10_2_sram[0]:21 0.0001657609 +13 mux_tree_tapbuf_size10_2_sram[0]:7 mux_tree_tapbuf_size10_2_sram[0]:6 0.0001548913 +14 mux_tree_tapbuf_size10_2_sram[0]:8 mux_tree_tapbuf_size10_2_sram[0]:7 0.0045 +15 mux_tree_tapbuf_size10_2_sram[0]:6 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size10_2_sram[0]:5 mux_bottom_ipin_4\/mux_l1_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_2_sram[0]:9 mux_bottom_ipin_4\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_2_sram[0]:10 mux_tree_tapbuf_size10_2_sram[0]:9 0.0001847826 +19 mux_tree_tapbuf_size10_2_sram[0]:11 mux_tree_tapbuf_size10_2_sram[0]:10 0.0045 +20 mux_tree_tapbuf_size10_2_sram[0]:11 mux_tree_tapbuf_size10_2_sram[0]:8 0.004816964 +21 mux_tree_tapbuf_size10_2_sram[0]:17 mux_tree_tapbuf_size10_2_sram[0]:16 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[1] 0.003210573 //LENGTH 24.910 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 75.745 15.300 +*I mux_bottom_ipin_12\/mux_l2_in_3_:S I *L 0.00357 *C 73.040 12.920 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 75.155 9.860 +*I mux_bottom_ipin_12\/mux_l2_in_1_:S I *L 0.00357 *C 74.860 18.360 +*I mux_bottom_ipin_12\/mux_l2_in_0_:S I *L 0.00357 *C 76.260 23.120 +*I mux_bottom_ipin_12\/mux_l2_in_2_:S I *L 0.00357 *C 80.400 14.960 +*N mux_tree_tapbuf_size10_6_sram[1]:6 *C 80.400 14.960 +*N mux_tree_tapbuf_size10_6_sram[1]:7 *C 80.500 15.300 +*N mux_tree_tapbuf_size10_6_sram[1]:8 *C 76.245 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:9 *C 75.922 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:10 *C 75.900 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:11 *C 75.440 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:12 *C 74.898 18.360 +*N mux_tree_tapbuf_size10_6_sram[1]:13 *C 75.395 18.360 +*N mux_tree_tapbuf_size10_6_sram[1]:14 *C 75.440 18.360 +*N mux_tree_tapbuf_size10_6_sram[1]:15 *C 75.155 9.860 +*N mux_tree_tapbuf_size10_6_sram[1]:16 *C 74.980 9.860 +*N mux_tree_tapbuf_size10_6_sram[1]:17 *C 74.980 9.905 +*N mux_tree_tapbuf_size10_6_sram[1]:18 *C 73.078 12.920 +*N mux_tree_tapbuf_size10_6_sram[1]:19 *C 74.935 12.920 +*N mux_tree_tapbuf_size10_6_sram[1]:20 *C 74.980 12.920 +*N mux_tree_tapbuf_size10_6_sram[1]:21 *C 74.980 15.300 +*N mux_tree_tapbuf_size10_6_sram[1]:22 *C 75.440 15.345 +*N mux_tree_tapbuf_size10_6_sram[1]:23 *C 75.440 15.300 +*N mux_tree_tapbuf_size10_6_sram[1]:24 *C 75.782 15.300 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_3_:S 1e-06 +2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_12\/mux_l2_in_0_:S 1e-06 +5 mux_bottom_ipin_12\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size10_6_sram[1]:6 5.306356e-05 +7 mux_tree_tapbuf_size10_6_sram[1]:7 0.0003519168 +8 mux_tree_tapbuf_size10_6_sram[1]:8 5.535921e-05 +9 mux_tree_tapbuf_size10_6_sram[1]:9 5.535921e-05 +10 mux_tree_tapbuf_size10_6_sram[1]:10 6.316224e-05 +11 mux_tree_tapbuf_size10_6_sram[1]:11 0.000299108 +12 mux_tree_tapbuf_size10_6_sram[1]:12 6.922455e-05 +13 mux_tree_tapbuf_size10_6_sram[1]:13 6.922455e-05 +14 mux_tree_tapbuf_size10_6_sram[1]:14 0.0004838129 +15 mux_tree_tapbuf_size10_6_sram[1]:15 4.731624e-05 +16 mux_tree_tapbuf_size10_6_sram[1]:16 5.180424e-05 +17 mux_tree_tapbuf_size10_6_sram[1]:17 0.0001595394 +18 mux_tree_tapbuf_size10_6_sram[1]:18 0.0001628996 +19 mux_tree_tapbuf_size10_6_sram[1]:19 0.0001628996 +20 mux_tree_tapbuf_size10_6_sram[1]:20 0.0003289515 +21 mux_tree_tapbuf_size10_6_sram[1]:21 0.0001765108 +22 mux_tree_tapbuf_size10_6_sram[1]:22 0.0002199551 +23 mux_tree_tapbuf_size10_6_sram[1]:23 5.00672e-05 +24 mux_tree_tapbuf_size10_6_sram[1]:24 0.0003443983 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_6_sram[1]:24 0.152 +1 mux_tree_tapbuf_size10_6_sram[1]:12 mux_bottom_ipin_12\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_6_sram[1]:13 mux_tree_tapbuf_size10_6_sram[1]:12 0.0004441965 +3 mux_tree_tapbuf_size10_6_sram[1]:14 mux_tree_tapbuf_size10_6_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size10_6_sram[1]:14 mux_tree_tapbuf_size10_6_sram[1]:11 0.00425 +5 mux_tree_tapbuf_size10_6_sram[1]:23 mux_tree_tapbuf_size10_6_sram[1]:22 0.0045 +6 mux_tree_tapbuf_size10_6_sram[1]:22 mux_tree_tapbuf_size10_6_sram[1]:21 0.0004107143 +7 mux_tree_tapbuf_size10_6_sram[1]:22 mux_tree_tapbuf_size10_6_sram[1]:14 0.002691965 +8 mux_tree_tapbuf_size10_6_sram[1]:6 mux_bottom_ipin_12\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size10_6_sram[1]:8 mux_bottom_ipin_12\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_6_sram[1]:9 mux_tree_tapbuf_size10_6_sram[1]:8 0.0001752718 +11 mux_tree_tapbuf_size10_6_sram[1]:10 mux_tree_tapbuf_size10_6_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size10_6_sram[1]:19 mux_tree_tapbuf_size10_6_sram[1]:18 0.001658482 +13 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:19 0.0045 +14 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:17 0.002691965 +15 mux_tree_tapbuf_size10_6_sram[1]:18 mux_bottom_ipin_12\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size10_6_sram[1]:16 mux_tree_tapbuf_size10_6_sram[1]:15 9.51087e-05 +17 mux_tree_tapbuf_size10_6_sram[1]:17 mux_tree_tapbuf_size10_6_sram[1]:16 0.0045 +18 mux_tree_tapbuf_size10_6_sram[1]:15 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +19 mux_tree_tapbuf_size10_6_sram[1]:24 mux_tree_tapbuf_size10_6_sram[1]:23 0.0001861413 +20 mux_tree_tapbuf_size10_6_sram[1]:24 mux_tree_tapbuf_size10_6_sram[1]:7 0.004212054 +21 mux_tree_tapbuf_size10_6_sram[1]:7 mux_tree_tapbuf_size10_6_sram[1]:6 0.0003035715 +22 mux_tree_tapbuf_size10_6_sram[1]:21 mux_tree_tapbuf_size10_6_sram[1]:20 0.002125 +23 mux_tree_tapbuf_size10_6_sram[1]:11 mux_tree_tapbuf_size10_6_sram[1]:10 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[2] 0.003028352 //LENGTH 20.875 LUMPCC 0.0005249523 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 33.885 15.300 +*I mux_bottom_ipin_2\/mux_l3_in_1_:S I *L 0.00357 *C 33.680 17.975 +*I mux_bottom_ipin_2\/mux_l3_in_0_:S I *L 0.00357 *C 35.520 23.120 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 26.855 20.740 +*N mux_tree_tapbuf_size8_0_sram[2]:4 *C 26.893 20.740 +*N mux_tree_tapbuf_size8_0_sram[2]:5 *C 33.535 20.740 +*N mux_tree_tapbuf_size8_0_sram[2]:6 *C 33.580 20.695 +*N mux_tree_tapbuf_size8_0_sram[2]:7 *C 35.420 23.120 +*N mux_tree_tapbuf_size8_0_sram[2]:8 *C 35.420 23.075 +*N mux_tree_tapbuf_size8_0_sram[2]:9 *C 35.420 18.405 +*N mux_tree_tapbuf_size8_0_sram[2]:10 *C 35.375 18.360 +*N mux_tree_tapbuf_size8_0_sram[2]:11 *C 33.680 18.360 +*N mux_tree_tapbuf_size8_0_sram[2]:12 *C 33.680 17.963 +*N mux_tree_tapbuf_size8_0_sram[2]:13 *C 33.580 18.020 +*N mux_tree_tapbuf_size8_0_sram[2]:14 *C 33.580 18.020 +*N mux_tree_tapbuf_size8_0_sram[2]:15 *C 33.580 15.345 +*N mux_tree_tapbuf_size8_0_sram[2]:16 *C 33.580 15.300 +*N mux_tree_tapbuf_size8_0_sram[2]:17 *C 33.885 15.300 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_2\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_0_sram[2]:4 0.0004132881 +5 mux_tree_tapbuf_size8_0_sram[2]:5 0.0004132881 +6 mux_tree_tapbuf_size8_0_sram[2]:6 0.0001664719 +7 mux_tree_tapbuf_size8_0_sram[2]:7 2.994366e-05 +8 mux_tree_tapbuf_size8_0_sram[2]:8 0.0002747235 +9 mux_tree_tapbuf_size8_0_sram[2]:9 0.0002747235 +10 mux_tree_tapbuf_size8_0_sram[2]:10 9.590563e-05 +11 mux_tree_tapbuf_size8_0_sram[2]:11 0.000121653 +12 mux_tree_tapbuf_size8_0_sram[2]:12 2.863465e-05 +13 mux_tree_tapbuf_size8_0_sram[2]:13 9.463957e-05 +14 mux_tree_tapbuf_size8_0_sram[2]:14 0.0003485982 +15 mux_tree_tapbuf_size8_0_sram[2]:15 0.0001456511 +16 mux_tree_tapbuf_size8_0_sram[2]:16 4.860372e-05 +17 mux_tree_tapbuf_size8_0_sram[2]:17 4.327467e-05 +18 mux_tree_tapbuf_size8_0_sram[2]:5 mux_tree_tapbuf_size8_0_sram[1]:11 0.0001992132 +19 mux_tree_tapbuf_size8_0_sram[2]:4 mux_tree_tapbuf_size8_0_sram[1]:10 0.0001992132 +20 mux_tree_tapbuf_size8_0_sram[2]:10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.846184e-05 +21 mux_tree_tapbuf_size8_0_sram[2]:9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.467135e-05 +22 mux_tree_tapbuf_size8_0_sram[2]:8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.467135e-05 +23 mux_tree_tapbuf_size8_0_sram[2]:14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.29736e-07 +24 mux_tree_tapbuf_size8_0_sram[2]:15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.29736e-07 +25 mux_tree_tapbuf_size8_0_sram[2]:11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.846184e-05 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_0_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_0_sram[2]:10 mux_tree_tapbuf_size8_0_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size8_0_sram[2]:9 mux_tree_tapbuf_size8_0_sram[2]:8 0.004169642 +3 mux_tree_tapbuf_size8_0_sram[2]:7 mux_bottom_ipin_2\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_0_sram[2]:8 mux_tree_tapbuf_size8_0_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size8_0_sram[2]:13 mux_bottom_ipin_2\/mux_l3_in_1_:S 0.152 +6 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:12 2.994792e-05 +7 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:11 0.0003035715 +8 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:13 0.0045 +9 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:6 0.002388393 +10 mux_tree_tapbuf_size8_0_sram[2]:5 mux_tree_tapbuf_size8_0_sram[2]:4 0.005930804 +11 mux_tree_tapbuf_size8_0_sram[2]:6 mux_tree_tapbuf_size8_0_sram[2]:5 0.0045 +12 mux_tree_tapbuf_size8_0_sram[2]:4 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:15 0.0045 +14 mux_tree_tapbuf_size8_0_sram[2]:15 mux_tree_tapbuf_size8_0_sram[2]:14 0.002388393 +15 mux_tree_tapbuf_size8_0_sram[2]:17 mux_tree_tapbuf_size8_0_sram[2]:16 0.0001657609 +16 mux_tree_tapbuf_size8_0_sram[2]:11 mux_tree_tapbuf_size8_0_sram[2]:10 0.001513393 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[0] 0.004651887 //LENGTH 39.655 LUMPCC 0.0006229419 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.560 53.380 +*I mux_bottom_ipin_10\/mux_l1_in_0_:S I *L 0.00357 *C 8.840 29.240 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.910 20.740 +*N mux_tree_tapbuf_size8_4_sram[0]:3 *C 8.910 20.740 +*N mux_tree_tapbuf_size8_4_sram[0]:4 *C 8.740 20.740 +*N mux_tree_tapbuf_size8_4_sram[0]:5 *C 8.740 20.785 +*N mux_tree_tapbuf_size8_4_sram[0]:6 *C 8.740 29.240 +*N mux_tree_tapbuf_size8_4_sram[0]:7 *C 8.740 29.240 +*N mux_tree_tapbuf_size8_4_sram[0]:8 *C 8.740 44.880 +*N mux_tree_tapbuf_size8_4_sram[0]:9 *C 9.660 44.880 +*N mux_tree_tapbuf_size8_4_sram[0]:10 *C 9.660 53.335 +*N mux_tree_tapbuf_size8_4_sram[0]:11 *C 9.705 53.380 +*N mux_tree_tapbuf_size8_4_sram[0]:12 *C 14.523 53.380 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_10\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_4_sram[0]:3 6.037876e-05 +4 mux_tree_tapbuf_size8_4_sram[0]:4 6.490786e-05 +5 mux_tree_tapbuf_size8_4_sram[0]:5 0.0004278558 +6 mux_tree_tapbuf_size8_4_sram[0]:6 3.318745e-05 +7 mux_tree_tapbuf_size8_4_sram[0]:7 0.001216091 +8 mux_tree_tapbuf_size8_4_sram[0]:8 0.0008100601 +9 mux_tree_tapbuf_size8_4_sram[0]:9 0.0004345222 +10 mux_tree_tapbuf_size8_4_sram[0]:10 0.000379437 +11 mux_tree_tapbuf_size8_4_sram[0]:11 0.0002997528 +12 mux_tree_tapbuf_size8_4_sram[0]:12 0.0002997528 +13 mux_tree_tapbuf_size8_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[3]:8 0.0001366227 +14 mux_tree_tapbuf_size8_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[3]:12 1.695504e-06 +15 mux_tree_tapbuf_size8_4_sram[0]:7 mux_tree_tapbuf_size10_4_sram[3]:11 1.116489e-05 +16 mux_tree_tapbuf_size8_4_sram[0]:8 mux_tree_tapbuf_size10_4_sram[3]:12 1.116489e-05 +17 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size10_4_sram[3]:11 1.695504e-06 +18 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size10_4_sram[3]:12 0.0001366227 +19 mux_tree_tapbuf_size8_4_sram[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001033325 +20 mux_tree_tapbuf_size8_4_sram[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001033325 +21 mux_tree_tapbuf_size8_4_sram[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.865531e-05 +22 mux_tree_tapbuf_size8_4_sram[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.865531e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_4_sram[0]:12 0.152 +1 mux_tree_tapbuf_size8_4_sram[0]:3 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size8_4_sram[0]:4 mux_tree_tapbuf_size8_4_sram[0]:3 9.239131e-05 +3 mux_tree_tapbuf_size8_4_sram[0]:5 mux_tree_tapbuf_size8_4_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size8_4_sram[0]:11 mux_tree_tapbuf_size8_4_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size8_4_sram[0]:10 mux_tree_tapbuf_size8_4_sram[0]:9 0.007549107 +6 mux_tree_tapbuf_size8_4_sram[0]:12 mux_tree_tapbuf_size8_4_sram[0]:11 0.004301339 +7 mux_tree_tapbuf_size8_4_sram[0]:6 mux_bottom_ipin_10\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_4_sram[0]:7 mux_tree_tapbuf_size8_4_sram[0]:6 0.0045 +9 mux_tree_tapbuf_size8_4_sram[0]:7 mux_tree_tapbuf_size8_4_sram[0]:5 0.007549108 +10 mux_tree_tapbuf_size8_4_sram[0]:8 mux_tree_tapbuf_size8_4_sram[0]:7 0.01396429 +11 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size8_4_sram[0]:8 0.0008214286 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[0] 0.003033569 //LENGTH 25.285 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 81.265 58.480 +*I mux_bottom_ipin_15\/mux_l1_in_0_:S I *L 0.00357 *C 71.860 53.040 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 73.315 64.260 +*N mux_tree_tapbuf_size8_7_sram[0]:3 *C 73.353 64.260 +*N mux_tree_tapbuf_size8_7_sram[0]:4 *C 74.015 64.260 +*N mux_tree_tapbuf_size8_7_sram[0]:5 *C 74.060 64.215 +*N mux_tree_tapbuf_size8_7_sram[0]:6 *C 71.898 53.040 +*N mux_tree_tapbuf_size8_7_sram[0]:7 *C 74.015 53.040 +*N mux_tree_tapbuf_size8_7_sram[0]:8 *C 74.060 53.085 +*N mux_tree_tapbuf_size8_7_sram[0]:9 *C 74.060 56.440 +*N mux_tree_tapbuf_size8_7_sram[0]:10 *C 74.105 56.440 +*N mux_tree_tapbuf_size8_7_sram[0]:11 *C 79.535 56.440 +*N mux_tree_tapbuf_size8_7_sram[0]:12 *C 79.580 56.485 +*N mux_tree_tapbuf_size8_7_sram[0]:13 *C 79.580 58.435 +*N mux_tree_tapbuf_size8_7_sram[0]:14 *C 79.625 58.480 +*N mux_tree_tapbuf_size8_7_sram[0]:15 *C 81.228 58.480 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_7_sram[0]:3 6.970926e-05 +4 mux_tree_tapbuf_size8_7_sram[0]:4 6.970926e-05 +5 mux_tree_tapbuf_size8_7_sram[0]:5 0.0004362535 +6 mux_tree_tapbuf_size8_7_sram[0]:6 0.0001651858 +7 mux_tree_tapbuf_size8_7_sram[0]:7 0.0001651858 +8 mux_tree_tapbuf_size8_7_sram[0]:8 0.0001976678 +9 mux_tree_tapbuf_size8_7_sram[0]:9 0.0006666311 +10 mux_tree_tapbuf_size8_7_sram[0]:10 0.0003802967 +11 mux_tree_tapbuf_size8_7_sram[0]:11 0.0003802967 +12 mux_tree_tapbuf_size8_7_sram[0]:12 0.0001310519 +13 mux_tree_tapbuf_size8_7_sram[0]:13 0.0001310519 +14 mux_tree_tapbuf_size8_7_sram[0]:14 0.0001187644 +15 mux_tree_tapbuf_size8_7_sram[0]:15 0.0001187644 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_7_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_7_sram[0]:7 mux_tree_tapbuf_size8_7_sram[0]:6 0.001890625 +2 mux_tree_tapbuf_size8_7_sram[0]:8 mux_tree_tapbuf_size8_7_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size8_7_sram[0]:6 mux_bottom_ipin_15\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_7_sram[0]:10 mux_tree_tapbuf_size8_7_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size8_7_sram[0]:9 mux_tree_tapbuf_size8_7_sram[0]:8 0.002995536 +6 mux_tree_tapbuf_size8_7_sram[0]:9 mux_tree_tapbuf_size8_7_sram[0]:5 0.006941965 +7 mux_tree_tapbuf_size8_7_sram[0]:11 mux_tree_tapbuf_size8_7_sram[0]:10 0.004848215 +8 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size8_7_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size8_7_sram[0]:14 mux_tree_tapbuf_size8_7_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size8_7_sram[0]:12 0.001741071 +11 mux_tree_tapbuf_size8_7_sram[0]:15 mux_tree_tapbuf_size8_7_sram[0]:14 0.001430804 +12 mux_tree_tapbuf_size8_7_sram[0]:3 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size8_7_sram[0]:4 mux_tree_tapbuf_size8_7_sram[0]:3 0.0005915179 +14 mux_tree_tapbuf_size8_7_sram[0]:5 mux_tree_tapbuf_size8_7_sram[0]:4 0.0045 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007948744 //LENGTH 4.630 LUMPCC 0.0004455556 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_1_:X O *L 0 *C 66.985 28.220 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 69.250 26.520 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 69.250 26.520 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 69.000 26.520 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 69.000 26.565 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 69.000 28.175 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 68.955 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 67.023 28.220 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.409007e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.525188e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.620302e-05 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.620302e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.27854e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.27854e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[0]:35 8.701393e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[0]:36 8.701393e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:84 5.074604e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:106 5.074604e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_0_sram[1]:20 8.258585e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_0_sram[1]:21 8.258585e-05 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:18 2.431982e-06 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:17 2.431982e-06 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725446 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001358696 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001229946 //LENGTH 9.060 LUMPCC 0.0004300261 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l4_in_0_:X O *L 0 *C 44.335 61.200 +*I mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 43.985 69.490 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 43.985 69.490 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 44.160 69.360 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 44.160 69.315 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 44.160 61.245 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 44.160 61.200 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 44.335 61.200 + +*CAP +0 mux_bottom_ipin_1\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.838383e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.261365e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002869237 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002869237 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.532737e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.774711e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chanx_right_in[5]:12 8.240985e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chanx_right_in[5]:13 8.240985e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:7 0.0001326032 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:6 0.0001326032 + +*RES +0 mux_bottom_ipin_1\/mux_l4_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.065218e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.007205357 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005664258 //LENGTH 3.995 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_2_:X O *L 0 *C 57.215 46.920 +*I mux_bottom_ipin_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 55.660 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 55.698 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 56.995 45.220 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 57.040 45.265 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 57.040 46.875 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 57.040 46.920 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 57.215 46.920 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001120669 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001120669 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001075151 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001075151 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.014899e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.511287e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_2_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001158482 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008466021 //LENGTH 6.715 LUMPCC 0.0001866599 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_2_:X O *L 0 *C 12.135 37.400 +*I mux_bottom_ipin_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 13.340 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 13.303 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 12.005 41.820 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 11.960 41.775 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 11.960 37.445 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 11.960 37.400 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 12.135 37.400 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.505814e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.505814e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001854926 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001854926 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.909696e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.77437e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:9 2.524812e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:10 2.591525e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_4_sram[2]:20 1.074748e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_4_sram[2]:4 3.141911e-05 +12 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:6 2.591525e-05 +13 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:10 2.524812e-05 +14 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:19 1.074748e-05 +15 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_4_sram[2]:5 3.141911e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_2_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003866071 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001158482 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0] 0.00231236 //LENGTH 16.195 LUMPCC 0.0003383597 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l4_in_0_:X O *L 0 *C 9.440 61.880 +*I mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 15.440 69.525 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 15.440 69.525 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 15.180 69.360 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 15.180 69.405 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 15.180 69.983 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 15.173 70.040 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 10.588 70.040 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 10.580 69.983 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 10.580 61.925 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 10.535 61.880 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 9.478 61.880 + +*CAP +0 mux_bottom_ipin_9\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.784079e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.385447e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.247249e-05 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 6.247249e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0003225185 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0003225185 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004385901 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004385901 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001065715 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001065715 +12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_right_in[18]:12 9.154232e-05 +13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_right_in[18]:11 9.154232e-05 +14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size10_5_sram[3]:9 7.763754e-05 +15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size10_5_sram[3]:8 7.763754e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l4_in_0_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 8.967393e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.000515625 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0007183166 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0045 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.007194196 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0009441965 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0002980822 //LENGTH 2.465 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l3_in_1_:X O *L 0 *C 84.815 64.260 +*I mux_bottom_ipin_13\/mux_l4_in_0_:A0 I *L 0.001631 *C 82.640 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 82.678 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 84.778 64.260 + +*CAP +0 mux_bottom_ipin_13\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001480411 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001480411 + +*RES +0 mux_bottom_ipin_13\/mux_l3_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001875 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_13\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004411176 //LENGTH 3.215 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l3_in_0_:X O *L 0 *C 34.675 23.800 +*I mux_bottom_ipin_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 32.105 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 32.105 23.460 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 32.200 23.800 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 34.638 23.800 + +*CAP +0 mux_bottom_ipin_2\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.256067e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002062459 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000180311 + +*RES +0 mux_bottom_ipin_2\/mux_l3_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_2\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.00217634 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002627169 //LENGTH 22.320 LUMPCC 0.0003505392 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l4_in_0_:X O *L 0 *C 34.675 47.940 +*I mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 34.425 69.490 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 34.425 69.490 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 34.500 69.360 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 34.500 69.315 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 34.500 47.985 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 34.500 47.940 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 34.675 47.940 + +*CAP +0 mux_bottom_ipin_3\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.247931e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.645553e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001026162 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001026162 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.896766e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.440437e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 top_grid_pin_18_[0] 8.243171e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 top_grid_pin_18_[0]:2 8.243171e-05 +10 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_3_sram[1]:9 2.919853e-05 +11 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_3_sram[1]:17 2.3768e-05 +12 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_3_sram[1]:18 3.987135e-05 +13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:15 2.3768e-05 +14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:17 3.987135e-05 +15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:18 2.919853e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l4_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.076087e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.01904465 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009341318 //LENGTH 7.275 LUMPCC 0.0002200672 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l1_in_0_:X O *L 0 *C 7.995 27.880 +*I mux_bottom_ipin_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 9.760 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 9.723 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 7.865 23.460 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 7.820 23.505 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 7.820 27.835 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 7.820 27.880 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 7.995 27.880 + +*CAP +0 mux_bottom_ipin_10\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001421031 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001421031 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001517373 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001517373 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.696658e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.741728e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[19]:10 5.137828e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[19]:11 5.137828e-05 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_4_sram[0]:5 5.865531e-05 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_4_sram[0]:7 5.865531e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l1_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_10\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003866072 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007640678 //LENGTH 6.570 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l3_in_1_:X O *L 0 *C 21.795 36.380 +*I mux_bottom_ipin_11\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.690 39.100 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 18.690 39.100 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 18.860 39.100 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 18.860 39.055 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 18.860 36.425 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 18.905 36.380 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 21.758 36.380 + +*CAP +0 mux_bottom_ipin_11\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.082721e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.520255e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001522445 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001522445 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001757745 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001757745 + +*RES +0 mux_bottom_ipin_11\/mux_l3_in_1_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_11\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239132e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002546875 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002790405 //LENGTH 25.010 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l4_in_0_:X O *L 0 *C 81.135 48.280 +*I mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.605 71.895 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 80.605 71.895 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 80.500 71.740 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 80.500 71.695 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 80.500 48.325 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 80.545 48.280 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 81.098 48.280 + +*CAP +0 mux_bottom_ipin_14\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.077151e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.536319e-05 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001285651 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001285651 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.548441e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.548441e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l4_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.706522e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.02086607 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 + +*END + +*D_NET chanx_right_out[4] 0.0009303486 //LENGTH 7.605 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_728:X O *L 0 *C 98.900 56.440 +*P chanx_right_out[4] O *L 0.7423 *C 103.650 58.480 +*N chanx_right_out[4]:2 *C 102.128 58.480 +*N chanx_right_out[4]:3 *C 102.120 58.422 +*N chanx_right_out[4]:4 *C 102.120 56.485 +*N chanx_right_out[4]:5 *C 102.075 56.440 +*N chanx_right_out[4]:6 *C 98.938 56.440 + +*CAP +0 ropt_mt_inst_728:X 1e-06 +1 chanx_right_out[4] 0.0001221125 +2 chanx_right_out[4]:2 0.0001221125 +3 chanx_right_out[4]:3 0.0001264132 +4 chanx_right_out[4]:4 0.0001264132 +5 chanx_right_out[4]:5 0.0002161487 +6 chanx_right_out[4]:6 0.0002161487 + +*RES +0 ropt_mt_inst_728:X chanx_right_out[4]:6 0.152 +1 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +2 chanx_right_out[4]:2 chanx_right_out[4] 0.000238525 +3 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +4 chanx_right_out[4]:4 chanx_right_out[4]:3 0.001729911 +5 chanx_right_out[4]:6 chanx_right_out[4]:5 0.002801339 + +*END + +*D_NET ropt_net_149 0.003172152 //LENGTH 24.210 LUMPCC 0.0004907284 DR + +*CONN +*I FTB_15__14:X O *L 0 *C 97.060 59.160 +*I ropt_mt_inst_746:A I *L 0.001766 *C 88.780 66.640 +*N ropt_net_149:2 *C 88.818 66.640 +*N ropt_net_149:3 *C 89.195 66.640 +*N ropt_net_149:4 *C 89.240 66.685 +*N ropt_net_149:5 *C 89.240 67.275 +*N ropt_net_149:6 *C 89.285 67.320 +*N ropt_net_149:7 *C 99.775 67.320 +*N ropt_net_149:8 *C 99.820 67.275 +*N ropt_net_149:9 *C 99.820 59.205 +*N ropt_net_149:10 *C 99.775 59.160 +*N ropt_net_149:11 *C 97.098 59.160 + +*CAP +0 FTB_15__14:X 1e-06 +1 ropt_mt_inst_746:A 1e-06 +2 ropt_net_149:2 2.735903e-05 +3 ropt_net_149:3 2.735903e-05 +4 ropt_net_149:4 6.43985e-05 +5 ropt_net_149:5 6.43985e-05 +6 ropt_net_149:6 0.0005761799 +7 ropt_net_149:7 0.0005761799 +8 ropt_net_149:8 0.0004786688 +9 ropt_net_149:9 0.0004786688 +10 ropt_net_149:10 0.0001931055 +11 ropt_net_149:11 0.0001931055 +12 ropt_net_149:7 mux_tree_tapbuf_size10_7_sram[2]:18 0.0002172639 +13 ropt_net_149:6 mux_tree_tapbuf_size10_7_sram[2]:17 0.0002172639 +14 ropt_net_149:3 mux_tree_tapbuf_size10_7_sram[2]:18 2.810033e-05 +15 ropt_net_149:2 mux_tree_tapbuf_size10_7_sram[2]:17 2.810033e-05 + +*RES +0 FTB_15__14:X ropt_net_149:11 0.152 +1 ropt_net_149:11 ropt_net_149:10 0.002390625 +2 ropt_net_149:10 ropt_net_149:9 0.0045 +3 ropt_net_149:9 ropt_net_149:8 0.007205358 +4 ropt_net_149:7 ropt_net_149:6 0.009366072 +5 ropt_net_149:8 ropt_net_149:7 0.0045 +6 ropt_net_149:6 ropt_net_149:5 0.0045 +7 ropt_net_149:5 ropt_net_149:4 0.0005267857 +8 ropt_net_149:3 ropt_net_149:2 0.0003370536 +9 ropt_net_149:4 ropt_net_149:3 0.0045 +10 ropt_net_149:2 ropt_mt_inst_746:A 0.152 + +*END + +*D_NET chanx_left_out[19] 0.001155115 //LENGTH 9.060 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 7.095 6.460 +*P chanx_left_out[19] O *L 0.7423 *C 1.230 4.080 +*N chanx_left_out[19]:2 *C 5.053 4.080 +*N chanx_left_out[19]:3 *C 5.060 4.138 +*N chanx_left_out[19]:4 *C 5.060 6.415 +*N chanx_left_out[19]:5 *C 5.105 6.460 +*N chanx_left_out[19]:6 *C 7.058 6.460 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 chanx_left_out[19] 0.0002698831 +2 chanx_left_out[19]:2 0.0002698831 +3 chanx_left_out[19]:3 0.0001692144 +4 chanx_left_out[19]:4 0.0001692144 +5 chanx_left_out[19]:5 0.0001379598 +6 chanx_left_out[19]:6 0.0001379598 + +*RES +0 ropt_mt_inst_744:X chanx_left_out[19]:6 0.152 +1 chanx_left_out[19]:6 chanx_left_out[19]:5 0.001743304 +2 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0045 +3 chanx_left_out[19]:4 chanx_left_out[19]:3 0.002033482 +4 chanx_left_out[19]:3 chanx_left_out[19]:2 0.00341 +5 chanx_left_out[19]:2 chanx_left_out[19] 0.0005988583 + +*END + +*D_NET ropt_net_162 0.0007819022 //LENGTH 6.100 LUMPCC 0 DR + +*CONN +*I BUFT_RR_61:X O *L 0 *C 92.635 9.180 +*I ropt_mt_inst_763:A I *L 0.001766 *C 97.825 9.520 +*N ropt_net_162:2 *C 97.788 9.520 +*N ropt_net_162:3 *C 97.060 9.520 +*N ropt_net_162:4 *C 97.060 9.180 +*N ropt_net_162:5 *C 92.672 9.180 + +*CAP +0 BUFT_RR_61:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_162:2 7.364004e-05 +3 ropt_net_162:3 0.0001006601 +4 ropt_net_162:4 0.0003163111 +5 ropt_net_162:5 0.000289291 + +*RES +0 BUFT_RR_61:X ropt_net_162:5 0.152 +1 ropt_net_162:2 ropt_mt_inst_763:A 0.152 +2 ropt_net_162:5 ropt_net_162:4 0.003917411 +3 ropt_net_162:4 ropt_net_162:3 0.0003035715 +4 ropt_net_162:3 ropt_net_162:2 0.0006495535 + +*END + +*D_NET ropt_net_175 0.0005518531 //LENGTH 4.215 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 7.095 11.900 +*I ropt_mt_inst_779:A I *L 0.001767 *C 7.820 9.520 +*N ropt_net_175:2 *C 7.783 9.520 +*N ropt_net_175:3 *C 6.945 9.520 +*N ropt_net_175:4 *C 6.900 9.565 +*N ropt_net_175:5 *C 6.900 11.855 +*N ropt_net_175:6 *C 6.900 11.900 +*N ropt_net_175:7 *C 7.095 11.900 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_175:2 7.513857e-05 +3 ropt_net_175:3 7.513857e-05 +4 ropt_net_175:4 0.0001399376 +5 ropt_net_175:5 0.0001399376 +6 ropt_net_175:6 5.907415e-05 +7 ropt_net_175:7 6.062657e-05 + +*RES +0 ropt_mt_inst_750:X ropt_net_175:7 0.152 +1 ropt_net_175:2 ropt_mt_inst_779:A 0.152 +2 ropt_net_175:3 ropt_net_175:2 0.0007477679 +3 ropt_net_175:4 ropt_net_175:3 0.0045 +4 ropt_net_175:6 ropt_net_175:5 0.0045 +5 ropt_net_175:5 ropt_net_175:4 0.002044643 +6 ropt_net_175:7 ropt_net_175:6 0.0001059783 + +*END + +*D_NET ropt_net_178 0.001445289 //LENGTH 11.115 LUMPCC 0.0004099787 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 7.095 33.660 +*I ropt_mt_inst_785:A I *L 0.001767 *C 3.220 31.280 +*N ropt_net_178:2 *C 3.183 31.280 +*N ropt_net_178:3 *C 1.425 31.280 +*N ropt_net_178:4 *C 1.380 31.280 +*N ropt_net_178:5 *C 1.380 33.615 +*N ropt_net_178:6 *C 1.425 33.660 +*N ropt_net_178:7 *C 7.058 33.660 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_178:2 0.0001301726 +3 ropt_net_178:3 0.0001301726 +4 ropt_net_178:4 0.0001399431 +5 ropt_net_178:5 0.000107581 +6 ropt_net_178:6 0.0002627202 +7 ropt_net_178:7 0.0002627202 +8 ropt_net_178:7 chanx_right_in[9]:12 6.731114e-05 +9 ropt_net_178:6 chanx_right_in[9]:11 6.731114e-05 +10 ropt_net_178:5 chanx_right_in[9]:10 7.680424e-05 +11 ropt_net_178:4 chanx_right_in[9]:9 7.680424e-05 +12 ropt_net_178:7 ropt_net_163:3 6.087399e-05 +13 ropt_net_178:6 ropt_net_163:2 6.087399e-05 + +*RES +0 ropt_mt_inst_764:X ropt_net_178:7 0.152 +1 ropt_net_178:7 ropt_net_178:6 0.005029018 +2 ropt_net_178:6 ropt_net_178:5 0.0045 +3 ropt_net_178:5 ropt_net_178:4 0.002084821 +4 ropt_net_178:3 ropt_net_178:2 0.001569197 +5 ropt_net_178:4 ropt_net_178:3 0.0045 +6 ropt_net_178:2 ropt_mt_inst_785:A 0.152 + +*END + +*D_NET top_grid_pin_22_[0] 0.0007764309 //LENGTH 6.695 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 35.880 71.400 +*P top_grid_pin_22_[0] O *L 0.7423 *C 33.120 74.870 +*N top_grid_pin_22_[0]:2 *C 33.120 71.445 +*N top_grid_pin_22_[0]:3 *C 33.165 71.400 +*N top_grid_pin_22_[0]:4 *C 35.843 71.400 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 top_grid_pin_22_[0] 0.0001915695 +2 top_grid_pin_22_[0]:2 0.0001915695 +3 top_grid_pin_22_[0]:3 0.000196146 +4 top_grid_pin_22_[0]:4 0.000196146 + +*RES +0 ropt_mt_inst_794:X top_grid_pin_22_[0]:4 0.152 +1 top_grid_pin_22_[0]:4 top_grid_pin_22_[0]:3 0.002390625 +2 top_grid_pin_22_[0]:3 top_grid_pin_22_[0]:2 0.0045 +3 top_grid_pin_22_[0]:2 top_grid_pin_22_[0] 0.003058036 + +*END + +*D_NET chanx_left_in[10] 0.01979263 //LENGTH 117.990 LUMPCC 0.008234805 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 34.000 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 65.030 28.220 +*I FTB_11__10:A I *L 0.001776 *C 97.980 31.280 +*I mux_bottom_ipin_14\/mux_l2_in_1_:A0 I *L 0.001631 *C 84.010 38.760 +*I mux_bottom_ipin_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 81.295 33.320 +*N chanx_left_in[10]:5 *C 81.280 33.320 +*N chanx_left_in[10]:6 *C 83.973 38.760 +*N chanx_left_in[10]:7 *C 81.005 38.760 +*N chanx_left_in[10]:8 *C 80.960 38.715 +*N chanx_left_in[10]:9 *C 98.017 31.280 +*N chanx_left_in[10]:10 *C 98.395 31.280 +*N chanx_left_in[10]:11 *C 98.440 31.280 +*N chanx_left_in[10]:12 *C 98.433 31.280 +*N chanx_left_in[10]:13 *C 80.968 31.280 +*N chanx_left_in[10]:14 *C 80.960 31.338 +*N chanx_left_in[10]:15 *C 80.960 33.320 +*N chanx_left_in[10]:16 *C 80.983 33.320 +*N chanx_left_in[10]:17 *C 64.993 28.220 +*N chanx_left_in[10]:18 *C 64.445 28.220 +*N chanx_left_in[10]:19 *C 64.400 28.265 +*N chanx_left_in[10]:20 *C 64.400 33.275 +*N chanx_left_in[10]:21 *C 64.400 33.320 +*N chanx_left_in[10]:22 *C 57.085 33.320 +*N chanx_left_in[10]:23 *C 57.040 33.365 +*N chanx_left_in[10]:24 *C 57.040 33.943 +*N chanx_left_in[10]:25 *C 57.033 34.000 +*N chanx_left_in[10]:26 *C 51.230 34.000 + +*CAP +0 chanx_left_in[10] 0.002238908 +1 mux_bottom_ipin_0\/mux_l2_in_1_:A0 1e-06 +2 FTB_11__10:A 1e-06 +3 mux_bottom_ipin_14\/mux_l2_in_1_:A0 1e-06 +4 mux_bottom_ipin_6\/mux_l2_in_1_:A0 1e-06 +5 chanx_left_in[10]:5 5.136458e-05 +6 chanx_left_in[10]:6 0.0002460438 +7 chanx_left_in[10]:7 0.0002460438 +8 chanx_left_in[10]:8 0.0002985723 +9 chanx_left_in[10]:9 4.893619e-05 +10 chanx_left_in[10]:10 4.893619e-05 +11 chanx_left_in[10]:11 3.478884e-05 +12 chanx_left_in[10]:12 0.0006184053 +13 chanx_left_in[10]:13 0.0006184053 +14 chanx_left_in[10]:14 0.0001280367 +15 chanx_left_in[10]:15 0.0004633928 +16 chanx_left_in[10]:16 0.001105824 +17 chanx_left_in[10]:17 4.818699e-05 +18 chanx_left_in[10]:18 4.818699e-05 +19 chanx_left_in[10]:19 0.0002202078 +20 chanx_left_in[10]:20 0.0002202078 +21 chanx_left_in[10]:21 0.00156843 +22 chanx_left_in[10]:22 0.0004758692 +23 chanx_left_in[10]:23 5.723492e-05 +24 chanx_left_in[10]:24 5.723492e-05 +25 chanx_left_in[10]:25 0.0002358528 +26 chanx_left_in[10]:26 0.002474761 +27 chanx_left_in[10] chanx_left_in[7]:16 0.001052718 +28 chanx_left_in[10] chanx_left_in[7]:22 0.0002480958 +29 chanx_left_in[10] chanx_left_in[7]:29 9.670912e-05 +30 chanx_left_in[10]:25 chanx_left_in[7]:15 0.0003303195 +31 chanx_left_in[10]:26 chanx_left_in[7]:15 0.001052718 +32 chanx_left_in[10]:26 chanx_left_in[7]:16 0.0003303195 +33 chanx_left_in[10]:26 chanx_left_in[7]:21 0.0002480958 +34 chanx_left_in[10]:26 chanx_left_in[7]:28 9.670912e-05 +35 chanx_left_in[10]:13 chanx_left_in[18]:30 0.0005639209 +36 chanx_left_in[10]:12 chanx_left_in[18]:29 0.0005639209 +37 chanx_left_in[10]:17 chanx_right_in[0]:36 3.45021e-05 +38 chanx_left_in[10]:18 chanx_right_in[0]:35 3.45021e-05 +39 chanx_left_in[10]:13 chanx_right_in[0]:46 0.0004037808 +40 chanx_left_in[10]:13 chanx_right_in[0]:53 1.111984e-07 +41 chanx_left_in[10]:12 chanx_right_in[0] 1.111984e-07 +42 chanx_left_in[10]:12 chanx_right_in[0]:47 0.0004037808 +43 chanx_left_in[10] chanx_right_in[15]:14 0.0009390088 +44 chanx_left_in[10]:26 chanx_right_in[15]:15 0.0009390088 +45 chanx_left_in[10]:21 mux_tree_tapbuf_size10_0_sram[0]:12 3.032381e-05 +46 chanx_left_in[10]:21 mux_tree_tapbuf_size10_0_sram[0]:19 1.089392e-05 +47 chanx_left_in[10]:16 mux_tree_tapbuf_size10_0_sram[0]:20 1.089392e-05 +48 chanx_left_in[10]:16 mux_tree_tapbuf_size10_0_sram[0]:13 3.032381e-05 +49 chanx_left_in[10]:13 mux_tree_tapbuf_size10_0_sram[0]:21 0.0002870309 +50 chanx_left_in[10]:12 mux_tree_tapbuf_size10_0_sram[0]:22 0.0002870309 +51 chanx_left_in[10]:19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000109107 +52 chanx_left_in[10]:21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.087943e-05 +53 chanx_left_in[10]:20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000109107 +54 chanx_left_in[10]:16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.087943e-05 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:26 0.007833333 +1 chanx_left_in[10]:17 mux_bottom_ipin_0\/mux_l2_in_1_:A0 0.152 +2 chanx_left_in[10]:18 chanx_left_in[10]:17 0.0004888392 +3 chanx_left_in[10]:19 chanx_left_in[10]:18 0.0045 +4 chanx_left_in[10]:21 chanx_left_in[10]:20 0.0045 +5 chanx_left_in[10]:21 chanx_left_in[10]:16 0.0148058 +6 chanx_left_in[10]:20 chanx_left_in[10]:19 0.004473215 +7 chanx_left_in[10]:5 mux_bottom_ipin_6\/mux_l2_in_1_:A0 0.152 +8 chanx_left_in[10]:22 chanx_left_in[10]:21 0.006531251 +9 chanx_left_in[10]:23 chanx_left_in[10]:22 0.0045 +10 chanx_left_in[10]:24 chanx_left_in[10]:23 0.000515625 +11 chanx_left_in[10]:25 chanx_left_in[10]:24 0.00341 +12 chanx_left_in[10]:16 chanx_left_in[10]:15 0.0045 +13 chanx_left_in[10]:16 chanx_left_in[10]:5 0.0001616848 +14 chanx_left_in[10]:15 chanx_left_in[10]:14 0.00177009 +15 chanx_left_in[10]:15 chanx_left_in[10]:8 0.004816965 +16 chanx_left_in[10]:7 chanx_left_in[10]:6 0.002649554 +17 chanx_left_in[10]:8 chanx_left_in[10]:7 0.0045 +18 chanx_left_in[10]:6 mux_bottom_ipin_14\/mux_l2_in_1_:A0 0.152 +19 chanx_left_in[10]:14 chanx_left_in[10]:13 0.00341 +20 chanx_left_in[10]:13 chanx_left_in[10]:12 0.002736183 +21 chanx_left_in[10]:11 chanx_left_in[10]:10 0.0045 +22 chanx_left_in[10]:12 chanx_left_in[10]:11 0.00341 +23 chanx_left_in[10]:10 chanx_left_in[10]:9 0.0003370536 +24 chanx_left_in[10]:9 FTB_11__10:A 0.152 +25 chanx_left_in[10]:26 chanx_left_in[10]:25 0.0009090582 + +*END + +*D_NET chanx_right_in[8] 0.01809661 //LENGTH 115.910 LUMPCC 0.007313238 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 103.650 21.760 +*I mux_bottom_ipin_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 58.785 20.060 +*I FTB_29__28:A I *L 0.001776 *C 10.120 17.680 +*I mux_bottom_ipin_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 13.515 22.440 +*N chanx_right_in[8]:4 *C 13.515 22.440 +*N chanx_right_in[8]:5 *C 13.340 22.440 +*N chanx_right_in[8]:6 *C 13.340 22.395 +*N chanx_right_in[8]:7 *C 10.120 17.680 +*N chanx_right_in[8]:8 *C 13.340 17.680 +*N chanx_right_in[8]:9 *C 13.340 17.340 +*N chanx_right_in[8]:10 *C 13.340 17.385 +*N chanx_right_in[8]:11 *C 13.340 19.040 +*N chanx_right_in[8]:12 *C 13.343 19.040 +*N chanx_right_in[8]:13 *C 13.785 19.040 +*N chanx_right_in[8]:14 *C 13.800 19.033 +*N chanx_right_in[8]:15 *C 13.800 17.688 +*N chanx_right_in[8]:16 *C 13.800 17.675 +*N chanx_right_in[8]:17 *C 13.800 17.000 +*N chanx_right_in[8]:18 *C 59.340 17.000 +*N chanx_right_in[8]:19 *C 58.823 20.060 +*N chanx_right_in[8]:20 *C 59.295 20.060 +*N chanx_right_in[8]:21 *C 59.340 20.015 +*N chanx_right_in[8]:22 *C 59.340 17.738 +*N chanx_right_in[8]:23 *C 59.340 17.680 +*N chanx_right_in[8]:24 *C 67.140 17.680 +*N chanx_right_in[8]:25 *C 67.160 17.688 +*N chanx_right_in[8]:26 *C 67.160 21.753 +*N chanx_right_in[8]:27 *C 67.180 21.760 +*N chanx_right_in[8]:28 *C 72.680 21.760 +*N chanx_right_in[8]:29 *C 72.680 22.440 +*N chanx_right_in[8]:30 *C 92.000 22.440 +*N chanx_right_in[8]:31 *C 92.000 21.760 + +*CAP +0 chanx_right_in[8] 0.0003861998 +1 mux_bottom_ipin_4\/mux_l2_in_2_:A1 1e-06 +2 FTB_29__28:A 1e-06 +3 mux_bottom_ipin_8\/mux_l1_in_2_:A0 1e-06 +4 chanx_right_in[8]:4 4.53035e-05 +5 chanx_right_in[8]:5 5.044497e-05 +6 chanx_right_in[8]:6 0.0001872402 +7 chanx_right_in[8]:7 0.0002320291 +8 chanx_right_in[8]:8 0.0002324848 +9 chanx_right_in[8]:9 5.781397e-05 +10 chanx_right_in[8]:10 6.512431e-05 +11 chanx_right_in[8]:11 0.0002917731 +12 chanx_right_in[8]:12 7.66208e-05 +13 chanx_right_in[8]:13 7.66208e-05 +14 chanx_right_in[8]:14 0.0001510845 +15 chanx_right_in[8]:15 0.0001510845 +16 chanx_right_in[8]:16 7.039562e-05 +17 chanx_right_in[8]:17 0.001981949 +18 chanx_right_in[8]:18 0.001980743 +19 chanx_right_in[8]:19 5.96658e-05 +20 chanx_right_in[8]:20 5.96658e-05 +21 chanx_right_in[8]:21 0.000167897 +22 chanx_right_in[8]:22 0.000167897 +23 chanx_right_in[8]:23 0.0004425316 +24 chanx_right_in[8]:24 0.0003733415 +25 chanx_right_in[8]:25 0.0002411841 +26 chanx_right_in[8]:26 0.0002411841 +27 chanx_right_in[8]:27 0.000135546 +28 chanx_right_in[8]:28 0.0001968337 +29 chanx_right_in[8]:29 0.001129335 +30 chanx_right_in[8]:30 0.001105115 +31 chanx_right_in[8]:31 0.000423268 +32 chanx_right_in[8]:24 chanx_left_in[6]:15 0.0004505846 +33 chanx_right_in[8]:27 chanx_left_in[6]:20 1.632172e-06 +34 chanx_right_in[8]:23 chanx_left_in[6]:20 0.0004505846 +35 chanx_right_in[8]:17 chanx_left_in[6]:20 0.000422525 +36 chanx_right_in[8]:17 chanx_left_in[6]:21 0.0005308196 +37 chanx_right_in[8]:18 chanx_left_in[6]:15 0.000422525 +38 chanx_right_in[8]:18 chanx_left_in[6]:20 0.0005308196 +39 chanx_right_in[8]:28 chanx_left_in[6]:15 1.632172e-06 +40 chanx_right_in[8]:12 chanx_left_in[16] 2.681003e-07 +41 chanx_right_in[8]:13 chanx_left_in[16]:21 2.681003e-07 +42 chanx_right_in[8]:17 chanx_left_in[16] 7.681189e-07 +43 chanx_right_in[8]:17 chanx_left_in[16]:20 0.0002768301 +44 chanx_right_in[8]:18 chanx_left_in[16]:19 0.0002768301 +45 chanx_right_in[8]:18 chanx_left_in[16]:21 7.681189e-07 +46 chanx_right_in[8]:11 chanx_right_in[2]:22 3.193836e-06 +47 chanx_right_in[8]:27 chanx_right_in[2]:39 0.0002523658 +48 chanx_right_in[8]:6 chanx_right_in[2]:21 3.193836e-06 +49 chanx_right_in[8]:28 chanx_right_in[2]:40 0.0002523658 +50 chanx_right_in[8] chanx_right_in[6] 0.0002360587 +51 chanx_right_in[8]:5 chanx_right_in[6]:16 1.341284e-05 +52 chanx_right_in[8]:4 chanx_right_in[6]:17 1.341284e-05 +53 chanx_right_in[8]:17 chanx_right_in[6]:30 8.283982e-06 +54 chanx_right_in[8]:18 chanx_right_in[6]:31 8.283982e-06 +55 chanx_right_in[8]:30 chanx_right_in[6]:39 9.579406e-06 +56 chanx_right_in[8]:31 chanx_right_in[6]:38 9.579406e-06 +57 chanx_right_in[8]:31 chanx_right_in[6]:40 0.0002360587 +58 chanx_right_in[8] chanx_right_in[10] 1.485175e-06 +59 chanx_right_in[8] chanx_right_in[10]:28 0.0004630147 +60 chanx_right_in[8]:27 chanx_right_in[10]:27 0.0003270043 +61 chanx_right_in[8]:28 chanx_right_in[10]:28 0.0003270043 +62 chanx_right_in[8]:29 chanx_right_in[10]:27 0.0003721233 +63 chanx_right_in[8]:30 chanx_right_in[10]:28 0.0003721233 +64 chanx_right_in[8]:31 chanx_right_in[10]:27 0.0004630147 +65 chanx_right_in[8]:31 chanx_right_in[10]:31 1.485175e-06 +66 chanx_right_in[8]:29 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001466015 +67 chanx_right_in[8]:30 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001466015 +68 chanx_right_in[8]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.706577e-06 +69 chanx_right_in[8]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.145451e-06 +70 chanx_right_in[8]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.706577e-06 +71 chanx_right_in[8]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.145451e-06 +72 chanx_right_in[8]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.938118e-05 +73 chanx_right_in[8]:8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.938118e-05 +74 chanx_right_in[8]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.083174e-05 +75 chanx_right_in[8]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.693655e-05 +76 chanx_right_in[8]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.083174e-05 +77 chanx_right_in[8]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.693655e-05 +78 chanx_right_in[8]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.006633e-05 +79 chanx_right_in[8]:8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.006633e-05 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:31 0.001825167 +1 chanx_right_in[8]:11 chanx_right_in[8]:10 0.001477679 +2 chanx_right_in[8]:11 chanx_right_in[8]:6 0.002995536 +3 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00341 +4 chanx_right_in[8]:13 chanx_right_in[8]:12 6.499218e-05 +5 chanx_right_in[8]:14 chanx_right_in[8]:13 0.00341 +6 chanx_right_in[8]:16 chanx_right_in[8]:15 0.00341 +7 chanx_right_in[8]:15 chanx_right_in[8]:14 0.0002107167 +8 chanx_right_in[8]:24 chanx_right_in[8]:23 0.001222 +9 chanx_right_in[8]:25 chanx_right_in[8]:24 0.00341 +10 chanx_right_in[8]:27 chanx_right_in[8]:26 0.00341 +11 chanx_right_in[8]:26 chanx_right_in[8]:25 0.00063685 +12 chanx_right_in[8]:22 chanx_right_in[8]:21 0.002033482 +13 chanx_right_in[8]:23 chanx_right_in[8]:22 0.00341 +14 chanx_right_in[8]:23 chanx_right_in[8]:18 0.0001065333 +15 chanx_right_in[8]:20 chanx_right_in[8]:19 0.000421875 +16 chanx_right_in[8]:21 chanx_right_in[8]:20 0.0045 +17 chanx_right_in[8]:19 mux_bottom_ipin_4\/mux_l2_in_2_:A1 0.152 +18 chanx_right_in[8]:5 chanx_right_in[8]:4 9.51087e-05 +19 chanx_right_in[8]:6 chanx_right_in[8]:5 0.0045 +20 chanx_right_in[8]:4 mux_bottom_ipin_8\/mux_l1_in_2_:A0 0.152 +21 chanx_right_in[8]:9 chanx_right_in[8]:8 0.0003035715 +22 chanx_right_in[8]:10 chanx_right_in[8]:9 0.0045 +23 chanx_right_in[8]:7 FTB_29__28:A 0.152 +24 chanx_right_in[8]:8 chanx_right_in[8]:7 0.002875 +25 chanx_right_in[8]:17 chanx_right_in[8]:16 0.00010575 +26 chanx_right_in[8]:18 chanx_right_in[8]:17 0.007134599 +27 chanx_right_in[8]:28 chanx_right_in[8]:27 0.0008616666 +28 chanx_right_in[8]:29 chanx_right_in[8]:28 0.0001065333 +29 chanx_right_in[8]:30 chanx_right_in[8]:29 0.0030268 +30 chanx_right_in[8]:31 chanx_right_in[8]:30 0.0001065333 + +*END + +*D_NET ropt_net_135 0.002888699 //LENGTH 24.650 LUMPCC 0.0003598137 DR + +*CONN +*I mux_bottom_ipin_6\/BUFT_RR_58:X O *L 0 *C 46.640 70.040 +*I ropt_mt_inst_732:A I *L 0.001766 *C 30.360 72.080 +*N ropt_net_135:2 *C 30.398 72.080 +*N ropt_net_135:3 *C 31.695 72.080 +*N ropt_net_135:4 *C 31.740 72.125 +*N ropt_net_135:5 *C 31.740 74.415 +*N ropt_net_135:6 *C 31.785 74.460 +*N ropt_net_135:7 *C 40.895 74.460 +*N ropt_net_135:8 *C 40.940 74.415 +*N ropt_net_135:9 *C 40.940 70.085 +*N ropt_net_135:10 *C 40.985 70.040 +*N ropt_net_135:11 *C 46.602 70.040 + +*CAP +0 mux_bottom_ipin_6\/BUFT_RR_58:X 1e-06 +1 ropt_mt_inst_732:A 1e-06 +2 ropt_net_135:2 8.601513e-05 +3 ropt_net_135:3 8.601513e-05 +4 ropt_net_135:4 0.0001333888 +5 ropt_net_135:5 0.0001333888 +6 ropt_net_135:6 0.0004298834 +7 ropt_net_135:7 0.0004298834 +8 ropt_net_135:8 0.0002222778 +9 ropt_net_135:9 0.0002222778 +10 ropt_net_135:10 0.0003918772 +11 ropt_net_135:11 0.0003918772 +12 ropt_net_135:6 ropt_net_132:7 0.0001799068 +13 ropt_net_135:7 ropt_net_132:8 0.0001799068 + +*RES +0 mux_bottom_ipin_6\/BUFT_RR_58:X ropt_net_135:11 0.152 +1 ropt_net_135:2 ropt_mt_inst_732:A 0.152 +2 ropt_net_135:3 ropt_net_135:2 0.001158482 +3 ropt_net_135:4 ropt_net_135:3 0.0045 +4 ropt_net_135:6 ropt_net_135:5 0.0045 +5 ropt_net_135:5 ropt_net_135:4 0.002044643 +6 ropt_net_135:7 ropt_net_135:6 0.008133928 +7 ropt_net_135:8 ropt_net_135:7 0.0045 +8 ropt_net_135:10 ropt_net_135:9 0.0045 +9 ropt_net_135:9 ropt_net_135:8 0.003866072 +10 ropt_net_135:11 ropt_net_135:10 0.005015625 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[3] 0.00141304 //LENGTH 10.925 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 55.505 31.280 +*I mux_bottom_ipin_4\/mux_l4_in_0_:S I *L 0.00357 *C 56.020 29.240 +*I mem_bottom_ipin_4\/FTB_3__42:A I *L 0.001746 *C 59.340 34.000 +*N mux_tree_tapbuf_size10_2_sram[3]:3 *C 59.340 34.015 +*N mux_tree_tapbuf_size10_2_sram[3]:4 *C 59.340 34.340 +*N mux_tree_tapbuf_size10_2_sram[3]:5 *C 59.340 34.295 +*N mux_tree_tapbuf_size10_2_sram[3]:6 *C 59.340 30.985 +*N mux_tree_tapbuf_size10_2_sram[3]:7 *C 59.295 30.940 +*N mux_tree_tapbuf_size10_2_sram[3]:8 *C 56.020 29.240 +*N mux_tree_tapbuf_size10_2_sram[3]:9 *C 56.120 29.285 +*N mux_tree_tapbuf_size10_2_sram[3]:10 *C 56.120 30.895 +*N mux_tree_tapbuf_size10_2_sram[3]:11 *C 56.120 30.940 +*N mux_tree_tapbuf_size10_2_sram[3]:12 *C 55.660 30.940 +*N mux_tree_tapbuf_size10_2_sram[3]:13 *C 55.505 31.280 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_4\/FTB_3__42:A 1e-06 +3 mux_tree_tapbuf_size10_2_sram[3]:3 4.457384e-05 +4 mux_tree_tapbuf_size10_2_sram[3]:4 8.683168e-05 +5 mux_tree_tapbuf_size10_2_sram[3]:5 0.0002077151 +6 mux_tree_tapbuf_size10_2_sram[3]:6 0.0002077151 +7 mux_tree_tapbuf_size10_2_sram[3]:7 0.0001928335 +8 mux_tree_tapbuf_size10_2_sram[3]:8 2.992392e-05 +9 mux_tree_tapbuf_size10_2_sram[3]:9 0.0001268835 +10 mux_tree_tapbuf_size10_2_sram[3]:10 0.0001268835 +11 mux_tree_tapbuf_size10_2_sram[3]:11 0.0002625977 +12 mux_tree_tapbuf_size10_2_sram[3]:12 6.588741e-05 +13 mux_tree_tapbuf_size10_2_sram[3]:13 5.819525e-05 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_2_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_2_sram[3]:11 mux_tree_tapbuf_size10_2_sram[3]:10 0.0045 +2 mux_tree_tapbuf_size10_2_sram[3]:11 mux_tree_tapbuf_size10_2_sram[3]:7 0.002834822 +3 mux_tree_tapbuf_size10_2_sram[3]:10 mux_tree_tapbuf_size10_2_sram[3]:9 0.0014375 +4 mux_tree_tapbuf_size10_2_sram[3]:8 mux_bottom_ipin_4\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_2_sram[3]:9 mux_tree_tapbuf_size10_2_sram[3]:8 0.0045 +6 mux_tree_tapbuf_size10_2_sram[3]:13 mux_tree_tapbuf_size10_2_sram[3]:12 0.0001847826 +7 mux_tree_tapbuf_size10_2_sram[3]:7 mux_tree_tapbuf_size10_2_sram[3]:6 0.0045 +8 mux_tree_tapbuf_size10_2_sram[3]:6 mux_tree_tapbuf_size10_2_sram[3]:5 0.002955357 +9 mux_tree_tapbuf_size10_2_sram[3]:4 mux_tree_tapbuf_size10_2_sram[3]:3 0.0001766304 +10 mux_tree_tapbuf_size10_2_sram[3]:5 mux_tree_tapbuf_size10_2_sram[3]:4 0.0045 +11 mux_tree_tapbuf_size10_2_sram[3]:3 mem_bottom_ipin_4\/FTB_3__42:A 0.152 +12 mux_tree_tapbuf_size10_2_sram[3]:12 mux_tree_tapbuf_size10_2_sram[3]:11 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[3] 0.002041887 //LENGTH 15.475 LUMPCC 0.0001552751 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 14.365 64.600 +*I mux_bottom_ipin_9\/mux_l4_in_0_:S I *L 0.00357 *C 10.220 61.495 +*I mem_bottom_ipin_9\/FTB_6__45:A I *L 0.001746 *C 11.040 55.760 +*N mux_tree_tapbuf_size10_5_sram[3]:3 *C 11.003 55.760 +*N mux_tree_tapbuf_size10_5_sram[3]:4 *C 10.165 55.760 +*N mux_tree_tapbuf_size10_5_sram[3]:5 *C 10.120 55.805 +*N mux_tree_tapbuf_size10_5_sram[3]:6 *C 10.220 61.495 +*N mux_tree_tapbuf_size10_5_sram[3]:7 *C 10.120 61.200 +*N mux_tree_tapbuf_size10_5_sram[3]:8 *C 10.120 61.200 +*N mux_tree_tapbuf_size10_5_sram[3]:9 *C 10.120 64.555 +*N mux_tree_tapbuf_size10_5_sram[3]:10 *C 10.165 64.600 +*N mux_tree_tapbuf_size10_5_sram[3]:11 *C 14.328 64.600 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_9\/FTB_6__45:A 1e-06 +3 mux_tree_tapbuf_size10_5_sram[3]:3 7.788592e-05 +4 mux_tree_tapbuf_size10_5_sram[3]:4 7.788592e-05 +5 mux_tree_tapbuf_size10_5_sram[3]:5 0.0002994565 +6 mux_tree_tapbuf_size10_5_sram[3]:6 6.280034e-05 +7 mux_tree_tapbuf_size10_5_sram[3]:7 6.72085e-05 +8 mux_tree_tapbuf_size10_5_sram[3]:8 0.0004665187 +9 mux_tree_tapbuf_size10_5_sram[3]:9 0.0001353535 +10 mux_tree_tapbuf_size10_5_sram[3]:10 0.000348251 +11 mux_tree_tapbuf_size10_5_sram[3]:11 0.000348251 +12 mux_tree_tapbuf_size10_5_sram[3]:9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 7.763754e-05 +13 mux_tree_tapbuf_size10_5_sram[3]:8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 7.763754e-05 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_5_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_5_sram[3]:11 mux_tree_tapbuf_size10_5_sram[3]:10 0.003716518 +2 mux_tree_tapbuf_size10_5_sram[3]:10 mux_tree_tapbuf_size10_5_sram[3]:9 0.0045 +3 mux_tree_tapbuf_size10_5_sram[3]:9 mux_tree_tapbuf_size10_5_sram[3]:8 0.002995536 +4 mux_tree_tapbuf_size10_5_sram[3]:4 mux_tree_tapbuf_size10_5_sram[3]:3 0.0007477679 +5 mux_tree_tapbuf_size10_5_sram[3]:5 mux_tree_tapbuf_size10_5_sram[3]:4 0.0045 +6 mux_tree_tapbuf_size10_5_sram[3]:3 mem_bottom_ipin_9\/FTB_6__45:A 0.152 +7 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:6 0.0001271552 +8 mux_tree_tapbuf_size10_5_sram[3]:8 mux_tree_tapbuf_size10_5_sram[3]:7 0.0045 +9 mux_tree_tapbuf_size10_5_sram[3]:8 mux_tree_tapbuf_size10_5_sram[3]:5 0.004816964 +10 mux_tree_tapbuf_size10_5_sram[3]:6 mux_bottom_ipin_9\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.0009145334 //LENGTH 8.160 LUMPCC 9.583785e-05 DR + +*CONN +*I mem_bottom_ipin_0\/FTB_1__40:X O *L 0 *C 60.485 31.620 +*I mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.275 37.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 62.238 37.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 61.685 37.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 61.640 37.015 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 61.640 31.665 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 61.595 31.620 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 60.523 31.620 + +*CAP +0 mem_bottom_ipin_0\/FTB_1__40:X 1e-06 +1 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 6.118925e-05 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 6.118925e-05 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0002614799 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0002614799 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 8.567858e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 8.567858e-05 +8 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 chanx_right_in[5]:26 4.791893e-05 +9 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 chanx_right_in[5]:27 4.791893e-05 + +*RES +0 mem_bottom_ipin_0\/FTB_1__40:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_bottom_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0009575893 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[1] 0.005567007 //LENGTH 40.310 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.625 33.660 +*I mux_bottom_ipin_3\/mux_l2_in_2_:S I *L 0.00357 *C 39.660 41.480 +*I mux_bottom_ipin_3\/mux_l2_in_3_:S I *L 0.00357 *C 37.620 39.735 +*I mux_bottom_ipin_3\/mux_l2_in_1_:S I *L 0.00357 *C 33.020 39.440 +*I mux_bottom_ipin_3\/mux_l2_in_0_:S I *L 0.00357 *C 31.160 50.660 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 30.530 42.500 +*N mux_tree_tapbuf_size8_1_sram[1]:6 *C 30.568 42.500 +*N mux_tree_tapbuf_size8_1_sram[1]:7 *C 32.155 42.500 +*N mux_tree_tapbuf_size8_1_sram[1]:8 *C 32.200 42.500 +*N mux_tree_tapbuf_size8_1_sram[1]:9 *C 31.198 50.660 +*N mux_tree_tapbuf_size8_1_sram[1]:10 *C 31.695 50.660 +*N mux_tree_tapbuf_size8_1_sram[1]:11 *C 31.740 50.615 +*N mux_tree_tapbuf_size8_1_sram[1]:12 *C 31.740 42.840 +*N mux_tree_tapbuf_size8_1_sram[1]:13 *C 32.200 42.840 +*N mux_tree_tapbuf_size8_1_sram[1]:14 *C 32.208 42.840 +*N mux_tree_tapbuf_size8_1_sram[1]:15 *C 37.712 42.840 +*N mux_tree_tapbuf_size8_1_sram[1]:16 *C 37.720 42.782 +*N mux_tree_tapbuf_size8_1_sram[1]:17 *C 37.620 39.810 +*N mux_tree_tapbuf_size8_1_sram[1]:18 *C 33.058 39.440 +*N mux_tree_tapbuf_size8_1_sram[1]:19 *C 37.562 39.440 +*N mux_tree_tapbuf_size8_1_sram[1]:20 *C 37.620 39.735 +*N mux_tree_tapbuf_size8_1_sram[1]:21 *C 37.720 40.120 +*N mux_tree_tapbuf_size8_1_sram[1]:22 *C 37.720 40.165 +*N mux_tree_tapbuf_size8_1_sram[1]:23 *C 37.720 41.480 +*N mux_tree_tapbuf_size8_1_sram[1]:24 *C 37.765 41.480 +*N mux_tree_tapbuf_size8_1_sram[1]:25 *C 39.660 41.480 +*N mux_tree_tapbuf_size8_1_sram[1]:26 *C 40.895 41.480 +*N mux_tree_tapbuf_size8_1_sram[1]:27 *C 40.940 41.435 +*N mux_tree_tapbuf_size8_1_sram[1]:28 *C 40.940 33.705 +*N mux_tree_tapbuf_size8_1_sram[1]:29 *C 40.985 33.660 +*N mux_tree_tapbuf_size8_1_sram[1]:30 *C 42.587 33.660 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_ipin_3\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_3\/mux_l2_in_0_:S 1e-06 +5 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_1_sram[1]:6 0.0001220558 +7 mux_tree_tapbuf_size8_1_sram[1]:7 0.0001220558 +8 mux_tree_tapbuf_size8_1_sram[1]:8 3.133186e-05 +9 mux_tree_tapbuf_size8_1_sram[1]:9 5.642141e-05 +10 mux_tree_tapbuf_size8_1_sram[1]:10 5.642141e-05 +11 mux_tree_tapbuf_size8_1_sram[1]:11 0.0005117953 +12 mux_tree_tapbuf_size8_1_sram[1]:12 0.0005471452 +13 mux_tree_tapbuf_size8_1_sram[1]:13 9.47618e-05 +14 mux_tree_tapbuf_size8_1_sram[1]:14 0.0004456047 +15 mux_tree_tapbuf_size8_1_sram[1]:15 0.0004456047 +16 mux_tree_tapbuf_size8_1_sram[1]:16 9.510742e-05 +17 mux_tree_tapbuf_size8_1_sram[1]:17 1.328827e-05 +18 mux_tree_tapbuf_size8_1_sram[1]:18 0.0004171591 +19 mux_tree_tapbuf_size8_1_sram[1]:19 0.0004366414 +20 mux_tree_tapbuf_size8_1_sram[1]:20 8.113062e-05 +21 mux_tree_tapbuf_size8_1_sram[1]:21 5.250948e-05 +22 mux_tree_tapbuf_size8_1_sram[1]:22 9.12407e-05 +23 mux_tree_tapbuf_size8_1_sram[1]:23 0.0002195956 +24 mux_tree_tapbuf_size8_1_sram[1]:24 0.0001740062 +25 mux_tree_tapbuf_size8_1_sram[1]:25 0.0003225593 +26 mux_tree_tapbuf_size8_1_sram[1]:26 0.0001186744 +27 mux_tree_tapbuf_size8_1_sram[1]:27 0.0004373088 +28 mux_tree_tapbuf_size8_1_sram[1]:28 0.0004373088 +29 mux_tree_tapbuf_size8_1_sram[1]:29 0.0001156389 +30 mux_tree_tapbuf_size8_1_sram[1]:30 0.0001156389 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_1_sram[1]:30 0.152 +1 mux_tree_tapbuf_size8_1_sram[1]:26 mux_tree_tapbuf_size8_1_sram[1]:25 0.001102679 +2 mux_tree_tapbuf_size8_1_sram[1]:27 mux_tree_tapbuf_size8_1_sram[1]:26 0.0045 +3 mux_tree_tapbuf_size8_1_sram[1]:29 mux_tree_tapbuf_size8_1_sram[1]:28 0.0045 +4 mux_tree_tapbuf_size8_1_sram[1]:28 mux_tree_tapbuf_size8_1_sram[1]:27 0.006901786 +5 mux_tree_tapbuf_size8_1_sram[1]:30 mux_tree_tapbuf_size8_1_sram[1]:29 0.001430804 +6 mux_tree_tapbuf_size8_1_sram[1]:25 mux_bottom_ipin_3\/mux_l2_in_2_:S 0.152 +7 mux_tree_tapbuf_size8_1_sram[1]:25 mux_tree_tapbuf_size8_1_sram[1]:24 0.001691964 +8 mux_tree_tapbuf_size8_1_sram[1]:6 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size8_1_sram[1]:7 mux_tree_tapbuf_size8_1_sram[1]:6 0.001417411 +10 mux_tree_tapbuf_size8_1_sram[1]:8 mux_tree_tapbuf_size8_1_sram[1]:7 0.0045 +11 mux_tree_tapbuf_size8_1_sram[1]:20 mux_bottom_ipin_3\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size8_1_sram[1]:20 mux_tree_tapbuf_size8_1_sram[1]:19 0.0001715117 +13 mux_tree_tapbuf_size8_1_sram[1]:20 mux_tree_tapbuf_size8_1_sram[1]:17 4.360466e-05 +14 mux_tree_tapbuf_size8_1_sram[1]:24 mux_tree_tapbuf_size8_1_sram[1]:23 0.0045 +15 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:22 0.001174107 +16 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:16 0.001162947 +17 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:20 0.0003437501 +18 mux_tree_tapbuf_size8_1_sram[1]:22 mux_tree_tapbuf_size8_1_sram[1]:21 0.0045 +19 mux_tree_tapbuf_size8_1_sram[1]:16 mux_tree_tapbuf_size8_1_sram[1]:15 0.00341 +20 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:14 0.00086245 +21 mux_tree_tapbuf_size8_1_sram[1]:13 mux_tree_tapbuf_size8_1_sram[1]:12 0.0004107143 +22 mux_tree_tapbuf_size8_1_sram[1]:13 mux_tree_tapbuf_size8_1_sram[1]:8 0.0001634615 +23 mux_tree_tapbuf_size8_1_sram[1]:14 mux_tree_tapbuf_size8_1_sram[1]:13 0.00341 +24 mux_tree_tapbuf_size8_1_sram[1]:9 mux_bottom_ipin_3\/mux_l2_in_0_:S 0.152 +25 mux_tree_tapbuf_size8_1_sram[1]:10 mux_tree_tapbuf_size8_1_sram[1]:9 0.0004441965 +26 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:10 0.0045 +27 mux_tree_tapbuf_size8_1_sram[1]:18 mux_bottom_ipin_3\/mux_l2_in_1_:S 0.152 +28 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:18 0.004022322 +29 mux_tree_tapbuf_size8_1_sram[1]:12 mux_tree_tapbuf_size8_1_sram[1]:11 0.006941965 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_1_ccff_tail[0] 0.000859301 //LENGTH 6.990 LUMPCC 8.058301e-05 DR + +*CONN +*I mem_bottom_ipin_3\/FTB_10__49:X O *L 0 *C 43.005 44.540 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 43.415 39.100 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 *C 43.378 39.100 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 *C 42.825 39.100 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 *C 42.780 39.145 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 *C 42.780 44.495 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 *C 42.780 44.540 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 *C 43.005 44.540 + +*CAP +0 mem_bottom_ipin_3\/FTB_10__49:X 1e-06 +1 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 5.957565e-05 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 5.957565e-05 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.0002813447 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0002813447 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 4.717012e-05 +7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 4.770714e-05 +8 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.670443e-05 +9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.358707e-05 +10 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.670443e-05 +11 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.358707e-05 + +*RES +0 mem_bottom_ipin_3\/FTB_10__49:X mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001511032 //LENGTH 10.385 LUMPCC 0.0004124955 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_0_:X O *L 0 *C 67.335 26.520 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 60.260 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 60.297 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 62.055 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 62.100 28.855 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 62.100 26.565 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 62.145 26.520 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 67.297 26.520 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001582444 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001582444 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001513532 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001513532 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002386705 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002386705 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_0_sram[2]:7 0.0002062478 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:9 0.0002062478 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.004600447 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002044643 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001569197 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001349665 //LENGTH 11.580 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_2_:X O *L 0 *C 51.805 33.320 +*I mux_bottom_ipin_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 52.805 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 52.805 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 52.900 23.505 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 52.900 33.275 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 52.855 33.320 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 51.843 33.320 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.217993e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0005640585 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005640585 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.368372e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.368372e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_2_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.008723215 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009040178 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.000759838 //LENGTH 5.740 LUMPCC 9.744782e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l3_in_1_:X O *L 0 *C 48.935 45.560 +*I mux_bottom_ipin_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 49.915 49.640 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 49.915 49.640 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 49.680 49.640 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 49.680 49.595 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 49.680 45.605 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 49.635 45.560 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 48.973 45.560 + +*CAP +0 mux_bottom_ipin_5\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.206227e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.579654e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002069915 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002069915 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.927417e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.927417e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.872391e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.872391e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l3_in_1_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0005915179 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0035625 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001277174 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_5\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005811117 //LENGTH 4.135 LUMPCC 0.0001074151 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_2_:X O *L 0 *C 19.495 61.880 +*I mux_bottom_ipin_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 16.005 61.540 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 16.005 61.540 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 16.100 61.880 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 19.457 61.880 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.949511e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002222247 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001999769 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:14 9.452992e-07 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:15 3.280937e-06 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_5_sram[2]:16 4.948129e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:4 3.280937e-06 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:13 9.452992e-07 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:15 4.948129e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_2_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002997768 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004579753 //LENGTH 3.785 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_1_:X O *L 0 *C 84.815 59.160 +*I mux_bottom_ipin_13\/mux_l3_in_0_:A0 I *L 0.001631 *C 86.310 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 86.273 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 85.605 60.520 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 85.560 60.475 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 85.560 59.205 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 85.515 59.160 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 84.853 59.160 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.977185e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.977185e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.016785e-05 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.016785e-05 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.804797e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.804797e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0005959822 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133929 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006734331 //LENGTH 5.030 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_0_:X O *L 0 *C 33.865 49.640 +*I mux_bottom_ipin_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 33.680 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 33.580 45.220 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 33.580 45.265 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 33.580 49.595 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 33.580 49.640 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.865 49.640 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.962067e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002550805 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002550805 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.198382e-05 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.966764e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003866072 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005794612 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_1_:X O *L 0 *C 30.075 56.100 +*I mux_bottom_ipin_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 30.190 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 30.190 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 30.360 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 30.360 58.775 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 30.360 56.145 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 30.360 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 30.075 56.100 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.309618e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.747581e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001738778 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001738778 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.962732e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.950632e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_1_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.23913e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007136253 //LENGTH 5.520 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_2_:X O *L 0 *C 24.555 39.780 +*I mux_bottom_ipin_11\/mux_l3_in_1_:A1 I *L 0.00198 *C 23.365 36.380 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 23.402 36.380 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 23.875 36.380 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.920 36.425 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 23.920 39.735 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 23.965 39.780 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 24.518 39.780 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.13807e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.13807e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002152657 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002152657 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.916623e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.916623e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_2_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002955357 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006703034 //LENGTH 4.950 LUMPCC 0.0001197295 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_1_:X O *L 0 *C 61.465 60.860 +*I mux_bottom_ipin_15\/mux_l3_in_0_:A0 I *L 0.001631 *C 62.275 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 62.238 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 61.685 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 61.640 64.215 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 61.640 60.905 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 61.640 60.860 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 61.465 60.860 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.045158e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.045158e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001533058 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001533058 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.098324e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.007584e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.986473e-05 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.986473e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_1_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004933036 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002955358 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET chanx_left_out[11] 0.0005208111 //LENGTH 3.955 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 4.140 3.400 +*P chanx_left_out[11] O *L 0.7423 *C 5.520 1.290 +*N chanx_left_out[11]:2 *C 5.520 3.355 +*N chanx_left_out[11]:3 *C 5.475 3.400 +*N chanx_left_out[11]:4 *C 4.178 3.400 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 chanx_left_out[11] 0.0001317334 +2 chanx_left_out[11]:2 0.0001317334 +3 chanx_left_out[11]:3 0.0001281721 +4 chanx_left_out[11]:4 0.0001281721 + +*RES +0 ropt_mt_inst_735:X chanx_left_out[11]:4 0.152 +1 chanx_left_out[11]:4 chanx_left_out[11]:3 0.001158482 +2 chanx_left_out[11]:3 chanx_left_out[11]:2 0.0045 +3 chanx_left_out[11]:2 chanx_left_out[11] 0.00184375 + +*END + +*D_NET chanx_left_out[8] 0.0007943534 //LENGTH 5.875 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 4.140 19.720 +*P chanx_left_out[8] O *L 0.7423 *C 1.298 17.680 +*N chanx_left_out[8]:2 *C 1.380 17.680 +*N chanx_left_out[8]:3 *C 1.380 17.680 +*N chanx_left_out[8]:4 *C 2.300 17.680 +*N chanx_left_out[8]:5 *C 2.300 19.675 +*N chanx_left_out[8]:6 *C 2.345 19.720 +*N chanx_left_out[8]:7 *C 4.103 19.720 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 chanx_left_out[8] 4.32741e-05 +2 chanx_left_out[8]:2 4.32741e-05 +3 chanx_left_out[8]:3 9.175613e-05 +4 chanx_left_out[8]:4 0.0002004877 +5 chanx_left_out[8]:5 0.0001438133 +6 chanx_left_out[8]:6 0.000135374 +7 chanx_left_out[8]:7 0.000135374 + +*RES +0 ropt_mt_inst_775:X chanx_left_out[8]:7 0.152 +1 chanx_left_out[8]:7 chanx_left_out[8]:6 0.001569197 +2 chanx_left_out[8]:6 chanx_left_out[8]:5 0.0045 +3 chanx_left_out[8]:5 chanx_left_out[8]:4 0.00178125 +4 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +5 chanx_left_out[8]:2 chanx_left_out[8] 2.35e-05 +6 chanx_left_out[8]:4 chanx_left_out[8]:3 0.0008214285 + +*END + +*D_NET ropt_net_156 0.001938611 //LENGTH 15.310 LUMPCC 0.0005536351 DR + +*CONN +*I BUFT_RR_65:X O *L 0 *C 95.680 45.560 +*I ropt_mt_inst_754:A I *L 0.001766 *C 97.980 53.040 +*N ropt_net_156:2 *C 98.017 53.040 +*N ropt_net_156:3 *C 100.235 53.040 +*N ropt_net_156:4 *C 100.280 52.995 +*N ropt_net_156:5 *C 100.280 45.605 +*N ropt_net_156:6 *C 100.235 45.560 +*N ropt_net_156:7 *C 95.718 45.560 + +*CAP +0 BUFT_RR_65:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_156:2 7.370242e-05 +3 ropt_net_156:3 7.370242e-05 +4 ropt_net_156:4 0.0004013148 +5 ropt_net_156:5 0.0004013148 +6 ropt_net_156:6 0.0002164709 +7 ropt_net_156:7 0.0002164709 +8 ropt_net_156:7 chanx_right_in[10]:5 0.0001620976 +9 ropt_net_156:6 chanx_right_in[10]:6 0.0001620976 +10 ropt_net_156:5 ropt_net_151:9 1.776935e-05 +11 ropt_net_156:3 ropt_net_151:10 9.695065e-05 +12 ropt_net_156:4 ropt_net_151:8 1.776935e-05 +13 ropt_net_156:2 ropt_net_151:11 9.695065e-05 + +*RES +0 BUFT_RR_65:X ropt_net_156:7 0.152 +1 ropt_net_156:7 ropt_net_156:6 0.004033483 +2 ropt_net_156:6 ropt_net_156:5 0.0045 +3 ropt_net_156:5 ropt_net_156:4 0.006598215 +4 ropt_net_156:3 ropt_net_156:2 0.001979911 +5 ropt_net_156:4 ropt_net_156:3 0.0045 +6 ropt_net_156:2 ropt_mt_inst_754:A 0.152 + +*END + +*D_NET ropt_net_171 0.001218724 //LENGTH 9.605 LUMPCC 0.0001941395 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 7.095 22.440 +*I ropt_mt_inst_775:A I *L 0.001767 *C 3.220 20.400 +*N ropt_net_171:2 *C 3.183 20.400 +*N ropt_net_171:3 *C 1.885 20.400 +*N ropt_net_171:4 *C 1.840 20.445 +*N ropt_net_171:5 *C 1.840 22.395 +*N ropt_net_171:6 *C 1.885 22.440 +*N ropt_net_171:7 *C 7.058 22.440 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 ropt_mt_inst_775:A 1e-06 +2 ropt_net_171:2 8.543232e-05 +3 ropt_net_171:3 8.543232e-05 +4 ropt_net_171:4 0.0001204659 +5 ropt_net_171:5 0.0001204659 +6 ropt_net_171:6 0.000305394 +7 ropt_net_171:7 0.000305394 +8 ropt_net_171:7 chanx_right_in[6]:13 2.381591e-05 +9 ropt_net_171:7 chanx_right_in[6]:15 9.288006e-06 +10 ropt_net_171:7 chanx_right_in[6]:17 1.492334e-05 +11 ropt_net_171:6 chanx_right_in[6]:12 2.381591e-05 +12 ropt_net_171:6 chanx_right_in[6]:14 9.288006e-06 +13 ropt_net_171:6 chanx_right_in[6]:16 1.492334e-05 +14 ropt_net_171:7 prog_clk[0]:375 2.681225e-05 +15 ropt_net_171:6 prog_clk[0]:372 2.681225e-05 +16 ropt_net_171:5 prog_clk[0]:370 1.107159e-05 +17 ropt_net_171:5 prog_clk[0]:371 3.312384e-06 +18 ropt_net_171:5 prog_clk[0]:375 2.645193e-08 +19 ropt_net_171:3 prog_clk[0]:372 7.819813e-06 +20 ropt_net_171:4 prog_clk[0]:371 1.107159e-05 +21 ropt_net_171:4 prog_clk[0]:372 3.312384e-06 +22 ropt_net_171:4 prog_clk[0]:376 2.645193e-08 +23 ropt_net_171:2 prog_clk[0]:375 7.819813e-06 + +*RES +0 ropt_mt_inst_766:X ropt_net_171:7 0.152 +1 ropt_net_171:7 ropt_net_171:6 0.004618304 +2 ropt_net_171:6 ropt_net_171:5 0.0045 +3 ropt_net_171:5 ropt_net_171:4 0.001741072 +4 ropt_net_171:3 ropt_net_171:2 0.001158482 +5 ropt_net_171:4 ropt_net_171:3 0.0045 +6 ropt_net_171:2 ropt_mt_inst_775:A 0.152 + +*END + +*D_NET chanx_left_in[11] 0.0214965 //LENGTH 154.295 LUMPCC 0.006000552 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 51.680 +*I mux_bottom_ipin_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 32.030 55.080 +*I mux_bottom_ipin_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.170 55.080 +*I mux_bottom_ipin_15\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.515 60.520 +*I ropt_mt_inst_743:A I *L 0.001767 *C 93.380 12.240 +*N chanx_left_in[11]:5 *C 93.380 12.240 +*N chanx_left_in[11]:6 *C 93.380 11.900 +*N chanx_left_in[11]:7 *C 89.700 11.900 +*N chanx_left_in[11]:8 *C 89.780 12.920 +*N chanx_left_in[11]:9 *C 89.710 12.875 +*N chanx_left_in[11]:10 *C 89.700 12.285 +*N chanx_left_in[11]:11 *C 89.700 12.240 +*N chanx_left_in[11]:12 *C 88.780 12.240 +*N chanx_left_in[11]:13 *C 88.780 12.240 +*N chanx_left_in[11]:14 *C 88.773 12.240 +*N chanx_left_in[11]:15 *C 80.980 12.240 +*N chanx_left_in[11]:16 *C 80.960 12.248 +*N chanx_left_in[11]:17 *C 80.960 53.033 +*N chanx_left_in[11]:18 *C 80.940 53.040 +*N chanx_left_in[11]:19 *C 59.478 60.520 +*N chanx_left_in[11]:20 *C 58.925 60.520 +*N chanx_left_in[11]:21 *C 58.880 60.475 +*N chanx_left_in[11]:22 *C 59.170 55.080 +*N chanx_left_in[11]:23 *C 58.880 55.080 +*N chanx_left_in[11]:24 *C 58.880 55.125 +*N chanx_left_in[11]:25 *C 58.420 55.080 +*N chanx_left_in[11]:26 *C 58.420 53.098 +*N chanx_left_in[11]:27 *C 58.420 53.040 +*N chanx_left_in[11]:28 *C 33.128 53.040 +*N chanx_left_in[11]:29 *C 33.120 53.098 +*N chanx_left_in[11]:30 *C 33.120 55.035 +*N chanx_left_in[11]:31 *C 33.075 55.080 +*N chanx_left_in[11]:32 *C 32.030 55.080 +*N chanx_left_in[11]:33 *C 3.725 55.080 +*N chanx_left_in[11]:34 *C 3.680 55.035 +*N chanx_left_in[11]:35 *C 3.680 51.738 +*N chanx_left_in[11]:36 *C 3.673 51.680 + +*CAP +0 chanx_left_in[11] 0.0002059735 +1 mux_bottom_ipin_7\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_ipin_15\/mux_l2_in_1_:A0 1e-06 +4 ropt_mt_inst_743:A 1e-06 +5 chanx_left_in[11]:5 5.621704e-05 +6 chanx_left_in[11]:6 0.0002664725 +7 chanx_left_in[11]:7 0.0002585355 +8 chanx_left_in[11]:8 6.826135e-05 +9 chanx_left_in[11]:9 6.271931e-05 +10 chanx_left_in[11]:10 6.271931e-05 +11 chanx_left_in[11]:11 0.0001303297 +12 chanx_left_in[11]:12 9.476609e-05 +13 chanx_left_in[11]:13 3.113085e-05 +14 chanx_left_in[11]:14 0.0004606682 +15 chanx_left_in[11]:15 0.0004606682 +16 chanx_left_in[11]:16 0.001831782 +17 chanx_left_in[11]:17 0.001831782 +18 chanx_left_in[11]:18 0.0007349213 +19 chanx_left_in[11]:19 6.275976e-05 +20 chanx_left_in[11]:20 6.275976e-05 +21 chanx_left_in[11]:21 0.000237094 +22 chanx_left_in[11]:22 5.281686e-05 +23 chanx_left_in[11]:23 5.602392e-05 +24 chanx_left_in[11]:24 0.0002725565 +25 chanx_left_in[11]:25 0.0001557114 +26 chanx_left_in[11]:26 0.0001202488 +27 chanx_left_in[11]:27 0.002055485 +28 chanx_left_in[11]:28 0.001320564 +29 chanx_left_in[11]:29 0.0001292903 +30 chanx_left_in[11]:30 0.0001292903 +31 chanx_left_in[11]:31 8.475301e-05 +32 chanx_left_in[11]:32 0.00191914 +33 chanx_left_in[11]:33 0.001803571 +34 chanx_left_in[11]:34 0.0001334809 +35 chanx_left_in[11]:35 0.0001334809 +36 chanx_left_in[11]:36 0.0002059735 +37 chanx_left_in[11] chanx_left_in[3] 8.145189e-07 +38 chanx_left_in[11]:28 chanx_left_in[3]:45 7.39488e-05 +39 chanx_left_in[11]:28 chanx_left_in[3]:49 0.0002641853 +40 chanx_left_in[11]:16 chanx_left_in[3]:24 0.0003053746 +41 chanx_left_in[11]:18 chanx_left_in[3]:26 1.520618e-06 +42 chanx_left_in[11]:18 chanx_left_in[3]:38 4.346153e-05 +43 chanx_left_in[11]:18 chanx_left_in[3]:44 4.95441e-06 +44 chanx_left_in[11]:17 chanx_left_in[3]:25 0.0003053746 +45 chanx_left_in[11]:26 chanx_left_in[3]:43 8.88563e-06 +46 chanx_left_in[11]:27 chanx_left_in[3]:38 1.520618e-06 +47 chanx_left_in[11]:27 chanx_left_in[3]:44 0.0001174103 +48 chanx_left_in[11]:27 chanx_left_in[3]:45 4.95441e-06 +49 chanx_left_in[11]:27 chanx_left_in[3]:48 0.0002641853 +50 chanx_left_in[11]:36 chanx_left_in[3]:66 8.145189e-07 +51 chanx_left_in[11]:25 chanx_left_in[3]:42 8.88563e-06 +52 chanx_left_in[11] chanx_left_in[5]:24 1.276332e-06 +53 chanx_left_in[11]:18 chanx_left_in[5]:9 0.001004987 +54 chanx_left_in[11]:27 chanx_left_in[5]:10 0.001004987 +55 chanx_left_in[11]:36 chanx_left_in[5]:23 1.276332e-06 +56 chanx_left_in[11]:29 chanx_right_in[1]:23 8.123877e-08 +57 chanx_left_in[11]:28 chanx_right_in[1]:33 2.566566e-05 +58 chanx_left_in[11]:28 chanx_right_in[1]:37 4.153451e-05 +59 chanx_left_in[11]:30 chanx_right_in[1]:19 8.123877e-08 +60 chanx_left_in[11]:18 chanx_right_in[1]:43 0.0001271614 +61 chanx_left_in[11]:18 chanx_right_in[1]:44 0.0001551572 +62 chanx_left_in[11]:27 chanx_right_in[1]:43 0.0001966917 +63 chanx_left_in[11]:27 chanx_right_in[1]:37 0.0001528271 +64 chanx_left_in[11]:29 chanx_right_in[3]:39 6.73148e-06 +65 chanx_left_in[11]:28 chanx_right_in[3]:44 3.162096e-05 +66 chanx_left_in[11]:30 chanx_right_in[3]:42 6.73148e-06 +67 chanx_left_in[11]:26 chanx_right_in[3]:50 2.396695e-06 +68 chanx_left_in[11]:26 chanx_right_in[3]:49 4.699221e-06 +69 chanx_left_in[11]:27 chanx_right_in[3]:45 3.162096e-05 +70 chanx_left_in[11]:32 chanx_right_in[3]:41 0.0001516148 +71 chanx_left_in[11]:20 chanx_right_in[3]:11 1.479867e-06 +72 chanx_left_in[11]:21 chanx_right_in[3]:46 2.113467e-05 +73 chanx_left_in[11]:21 chanx_right_in[3]:12 0.0001220862 +74 chanx_left_in[11]:19 chanx_right_in[3]:10 1.479867e-06 +75 chanx_left_in[11]:24 chanx_right_in[3]:46 0.0001220862 +76 chanx_left_in[11]:24 chanx_right_in[3]:49 2.113467e-05 +77 chanx_left_in[11]:33 chanx_right_in[3]:40 0.0001516148 +78 chanx_left_in[11]:25 chanx_right_in[3]:46 4.699221e-06 +79 chanx_left_in[11]:25 chanx_right_in[3]:49 2.396695e-06 +80 chanx_left_in[11]:34 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001015161 +81 chanx_left_in[11]:35 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001015161 +82 chanx_left_in[11]:32 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001451253 +83 chanx_left_in[11]:33 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001451253 +84 chanx_left_in[11]:16 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0003528617 +85 chanx_left_in[11]:17 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0003528617 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:36 0.0003826583 +1 chanx_left_in[11]:11 chanx_left_in[11]:10 0.0045 +2 chanx_left_in[11]:11 chanx_left_in[11]:7 0.0003035715 +3 chanx_left_in[11]:10 chanx_left_in[11]:9 0.0005267857 +4 chanx_left_in[11]:9 chanx_left_in[11]:8 0.0045 +5 chanx_left_in[11]:29 chanx_left_in[11]:28 0.00341 +6 chanx_left_in[11]:28 chanx_left_in[11]:27 0.003962492 +7 chanx_left_in[11]:31 chanx_left_in[11]:30 0.0045 +8 chanx_left_in[11]:30 chanx_left_in[11]:29 0.001729911 +9 chanx_left_in[11]:12 chanx_left_in[11]:11 0.0008214286 +10 chanx_left_in[11]:13 chanx_left_in[11]:12 0.0045 +11 chanx_left_in[11]:14 chanx_left_in[11]:13 0.00341 +12 chanx_left_in[11]:15 chanx_left_in[11]:14 0.001220825 +13 chanx_left_in[11]:16 chanx_left_in[11]:15 0.00341 +14 chanx_left_in[11]:18 chanx_left_in[11]:17 0.00341 +15 chanx_left_in[11]:17 chanx_left_in[11]:16 0.00638965 +16 chanx_left_in[11]:26 chanx_left_in[11]:25 0.001770089 +17 chanx_left_in[11]:27 chanx_left_in[11]:26 0.00341 +18 chanx_left_in[11]:27 chanx_left_in[11]:18 0.003528133 +19 chanx_left_in[11]:32 mux_bottom_ipin_7\/mux_l2_in_1_:A0 0.152 +20 chanx_left_in[11]:32 chanx_left_in[11]:31 0.0009330358 +21 chanx_left_in[11]:20 chanx_left_in[11]:19 0.0004933036 +22 chanx_left_in[11]:21 chanx_left_in[11]:20 0.0045 +23 chanx_left_in[11]:19 mux_bottom_ipin_15\/mux_l2_in_1_:A0 0.152 +24 chanx_left_in[11]:23 chanx_left_in[11]:22 0.0001576087 +25 chanx_left_in[11]:24 chanx_left_in[11]:23 0.0045 +26 chanx_left_in[11]:24 chanx_left_in[11]:21 0.004776786 +27 chanx_left_in[11]:22 mux_bottom_ipin_1\/mux_l2_in_1_:A0 0.152 +28 chanx_left_in[11]:5 ropt_mt_inst_743:A 0.152 +29 chanx_left_in[11]:33 chanx_left_in[11]:32 0.02527232 +30 chanx_left_in[11]:34 chanx_left_in[11]:33 0.0045 +31 chanx_left_in[11]:35 chanx_left_in[11]:34 0.002944197 +32 chanx_left_in[11]:36 chanx_left_in[11]:35 0.00341 +33 chanx_left_in[11]:7 chanx_left_in[11]:6 0.003285714 +34 chanx_left_in[11]:6 chanx_left_in[11]:5 0.0003035715 +35 chanx_left_in[11]:25 chanx_left_in[11]:24 0.0004107143 + +*END + +*D_NET chanx_right_in[1] 0.02196871 //LENGTH 142.350 LUMPCC 0.00728164 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 103.650 54.400 +*I mux_bottom_ipin_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 89.990 53.720 +*I mux_bottom_ipin_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.070 53.380 +*I mux_bottom_ipin_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.970 53.380 +*I mux_bottom_ipin_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 55.080 +*I mux_bottom_ipin_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 40.310 49.640 +*I mux_bottom_ipin_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 36.170 49.640 +*I mux_bottom_ipin_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 29.270 53.380 +*I mux_bottom_ipin_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 24.210 53.380 +*I FTB_22__21:A I *L 0.001767 *C 14.720 69.360 +*N chanx_right_in[1]:10 *C 36.135 49.640 +*N chanx_right_in[1]:11 *C 14.720 69.360 +*N chanx_right_in[1]:12 *C 14.720 69.360 +*N chanx_right_in[1]:13 *C 14.728 69.360 +*N chanx_right_in[1]:14 *C 27.580 69.360 +*N chanx_right_in[1]:15 *C 27.600 69.353 +*N chanx_right_in[1]:16 *C 27.600 55.768 +*N chanx_right_in[1]:17 *C 27.620 55.760 +*N chanx_right_in[1]:18 *C 29.433 55.760 +*N chanx_right_in[1]:19 *C 29.440 55.703 +*N chanx_right_in[1]:20 *C 24.248 53.380 +*N chanx_right_in[1]:21 *C 29.233 53.380 +*N chanx_right_in[1]:22 *C 29.310 53.380 +*N chanx_right_in[1]:23 *C 29.440 53.380 +*N chanx_right_in[1]:24 *C 29.440 50.025 +*N chanx_right_in[1]:25 *C 29.485 49.980 +*N chanx_right_in[1]:26 *C 35.880 49.980 +*N chanx_right_in[1]:27 *C 35.880 49.675 +*N chanx_right_in[1]:28 *C 36.208 49.640 +*N chanx_right_in[1]:29 *C 40.310 49.640 +*N chanx_right_in[1]:30 *C 43.655 49.640 +*N chanx_right_in[1]:31 *C 43.700 49.685 +*N chanx_right_in[1]:32 *C 43.700 55.023 +*N chanx_right_in[1]:33 *C 43.708 55.080 +*N chanx_right_in[1]:34 *C 55.030 55.080 +*N chanx_right_in[1]:35 *C 54.740 55.080 +*N chanx_right_in[1]:36 *C 54.740 55.080 +*N chanx_right_in[1]:37 *C 54.740 55.080 +*N chanx_right_in[1]:38 *C 72.933 53.380 +*N chanx_right_in[1]:39 *C 66.108 53.380 +*N chanx_right_in[1]:40 *C 69.920 53.380 +*N chanx_right_in[1]:41 *C 69.920 53.425 +*N chanx_right_in[1]:42 *C 69.920 55.023 +*N chanx_right_in[1]:43 *C 69.920 55.080 +*N chanx_right_in[1]:44 *C 97.980 55.080 +*N chanx_right_in[1]:45 *C 90.028 53.720 +*N chanx_right_in[1]:46 *C 97.935 53.720 +*N chanx_right_in[1]:47 *C 97.980 53.765 +*N chanx_right_in[1]:48 *C 97.980 54.343 +*N chanx_right_in[1]:49 *C 97.980 54.400 + +*CAP +0 chanx_right_in[1] 0.0002995202 +1 mux_bottom_ipin_13\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_ipin_15\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_ipin_5\/mux_l1_in_0_:A0 1e-06 +5 mux_bottom_ipin_7\/mux_l1_in_0_:A0 1e-06 +6 mux_bottom_ipin_3\/mux_l1_in_0_:A0 1e-06 +7 mux_bottom_ipin_11\/mux_l1_in_0_:A0 1e-06 +8 mux_bottom_ipin_9\/mux_l1_in_0_:A0 1e-06 +9 FTB_22__21:A 1e-06 +10 chanx_right_in[1]:10 1.286873e-05 +11 chanx_right_in[1]:11 3.408929e-05 +12 chanx_right_in[1]:12 4.162667e-05 +13 chanx_right_in[1]:13 0.0007028676 +14 chanx_right_in[1]:14 0.0007028676 +15 chanx_right_in[1]:15 0.0008539437 +16 chanx_right_in[1]:16 0.0008539437 +17 chanx_right_in[1]:17 0.0001615004 +18 chanx_right_in[1]:18 0.0001615004 +19 chanx_right_in[1]:19 0.0001408978 +20 chanx_right_in[1]:20 0.0003421318 +21 chanx_right_in[1]:21 0.0003645468 +22 chanx_right_in[1]:22 2.241503e-05 +23 chanx_right_in[1]:23 0.00038139 +24 chanx_right_in[1]:24 0.0002110274 +25 chanx_right_in[1]:25 0.0003931262 +26 chanx_right_in[1]:26 0.0004175873 +27 chanx_right_in[1]:27 3.876455e-05 +28 chanx_right_in[1]:28 0.0002956205 +29 chanx_right_in[1]:29 0.0005202397 +30 chanx_right_in[1]:30 0.0002240824 +31 chanx_right_in[1]:31 0.0003599013 +32 chanx_right_in[1]:32 0.0003599013 +33 chanx_right_in[1]:33 0.0002483396 +34 chanx_right_in[1]:34 4.953496e-05 +35 chanx_right_in[1]:35 5.358718e-05 +36 chanx_right_in[1]:36 3.92091e-05 +37 chanx_right_in[1]:37 0.0008914907 +38 chanx_right_in[1]:38 0.0001753005 +39 chanx_right_in[1]:39 0.0002417663 +40 chanx_right_in[1]:40 0.000447899 +41 chanx_right_in[1]:41 9.24768e-05 +42 chanx_right_in[1]:42 9.24768e-05 +43 chanx_right_in[1]:43 0.001755521 +44 chanx_right_in[1]:44 0.001163695 +45 chanx_right_in[1]:45 0.0005362105 +46 chanx_right_in[1]:46 0.0005362105 +47 chanx_right_in[1]:47 5.357062e-05 +48 chanx_right_in[1]:48 5.357062e-05 +49 chanx_right_in[1]:49 0.0003508451 +50 chanx_right_in[1]:25 chanx_left_in[3]:60 0.0001000932 +51 chanx_right_in[1]:33 chanx_left_in[3]:49 0.0005017954 +52 chanx_right_in[1]:37 chanx_left_in[3]:48 0.0005017954 +53 chanx_right_in[1]:26 chanx_left_in[3]:59 0.0001000932 +54 chanx_right_in[1]:23 chanx_left_in[11]:29 8.123877e-08 +55 chanx_right_in[1]:43 chanx_left_in[11]:18 0.0001271614 +56 chanx_right_in[1]:43 chanx_left_in[11]:27 0.0001966917 +57 chanx_right_in[1]:19 chanx_left_in[11]:30 8.123877e-08 +58 chanx_right_in[1]:33 chanx_left_in[11]:28 2.566566e-05 +59 chanx_right_in[1]:37 chanx_left_in[11]:27 0.0001528271 +60 chanx_right_in[1]:37 chanx_left_in[11]:28 4.153451e-05 +61 chanx_right_in[1]:44 chanx_left_in[11]:18 0.0001551572 +62 chanx_right_in[1]:43 chanx_left_in[14]:9 0.0001630638 +63 chanx_right_in[1]:43 chanx_left_in[14]:10 0.0003115681 +64 chanx_right_in[1]:37 chanx_left_in[14]:10 0.0001630638 +65 chanx_right_in[1]:44 chanx_left_in[14]:9 0.0003115681 +66 chanx_right_in[1] chanx_right_in[2] 0.000128179 +67 chanx_right_in[1]:43 chanx_right_in[2]:58 0.0008010524 +68 chanx_right_in[1]:49 chanx_right_in[2]:58 0.000128179 +69 chanx_right_in[1]:44 chanx_right_in[2] 0.0008010524 +70 chanx_right_in[1]:23 chanx_right_in[3]:43 3.411395e-07 +71 chanx_right_in[1]:23 chanx_right_in[3]:39 2.215009e-06 +72 chanx_right_in[1]:23 chanx_right_in[3]:42 2.574242e-06 +73 chanx_right_in[1]:23 chanx_right_in[3]:15 8.256724e-08 +74 chanx_right_in[1]:43 chanx_right_in[3]:45 0.0002568698 +75 chanx_right_in[1]:19 chanx_right_in[3]:14 8.256724e-08 +76 chanx_right_in[1]:19 chanx_right_in[3]:42 2.556149e-06 +77 chanx_right_in[1]:24 chanx_right_in[3]:39 2.574242e-06 +78 chanx_right_in[1]:33 chanx_right_in[3]:44 0.0006186683 +79 chanx_right_in[1]:37 chanx_right_in[3]:44 0.0002568698 +80 chanx_right_in[1]:37 chanx_right_in[3]:45 0.0006186683 +81 chanx_right_in[1]:14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002963186 +82 chanx_right_in[1]:13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002963186 +83 chanx_right_in[1]:42 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.141168e-05 +84 chanx_right_in[1]:40 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 4.049376e-05 +85 chanx_right_in[1]:40 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 4.649283e-05 +86 chanx_right_in[1]:41 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 2.141168e-05 +87 chanx_right_in[1]:38 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 4.649283e-05 +88 chanx_right_in[1]:39 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 4.049376e-05 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:49 0.0008883 +1 chanx_right_in[1]:22 chanx_right_in[1]:21 6.919643e-05 +2 chanx_right_in[1]:23 chanx_right_in[1]:22 0.0045 +3 chanx_right_in[1]:23 chanx_right_in[1]:19 0.002073661 +4 chanx_right_in[1]:42 chanx_right_in[1]:41 0.001426339 +5 chanx_right_in[1]:43 chanx_right_in[1]:42 0.00341 +6 chanx_right_in[1]:43 chanx_right_in[1]:37 0.0023782 +7 chanx_right_in[1]:40 chanx_right_in[1]:39 0.003404018 +8 chanx_right_in[1]:40 chanx_right_in[1]:38 0.002689732 +9 chanx_right_in[1]:41 chanx_right_in[1]:40 0.0045 +10 chanx_right_in[1]:19 chanx_right_in[1]:18 0.00341 +11 chanx_right_in[1]:18 chanx_right_in[1]:17 0.0002839583 +12 chanx_right_in[1]:17 chanx_right_in[1]:16 0.00341 +13 chanx_right_in[1]:16 chanx_right_in[1]:15 0.002128317 +14 chanx_right_in[1]:14 chanx_right_in[1]:13 0.002013558 +15 chanx_right_in[1]:15 chanx_right_in[1]:14 0.00341 +16 chanx_right_in[1]:12 chanx_right_in[1]:11 0.0045 +17 chanx_right_in[1]:13 chanx_right_in[1]:12 0.00341 +18 chanx_right_in[1]:11 FTB_22__21:A 0.152 +19 chanx_right_in[1]:25 chanx_right_in[1]:24 0.0045 +20 chanx_right_in[1]:24 chanx_right_in[1]:23 0.002995536 +21 chanx_right_in[1]:21 mux_bottom_ipin_11\/mux_l1_in_0_:A0 0.152 +22 chanx_right_in[1]:21 chanx_right_in[1]:20 0.004450893 +23 chanx_right_in[1]:32 chanx_right_in[1]:31 0.004765625 +24 chanx_right_in[1]:33 chanx_right_in[1]:32 0.00341 +25 chanx_right_in[1]:30 chanx_right_in[1]:29 0.002986607 +26 chanx_right_in[1]:31 chanx_right_in[1]:30 0.0045 +27 chanx_right_in[1]:48 chanx_right_in[1]:47 0.000515625 +28 chanx_right_in[1]:49 chanx_right_in[1]:48 0.00341 +29 chanx_right_in[1]:49 chanx_right_in[1]:44 0.0001065333 +30 chanx_right_in[1]:46 chanx_right_in[1]:45 0.007060268 +31 chanx_right_in[1]:47 chanx_right_in[1]:46 0.0045 +32 chanx_right_in[1]:45 mux_bottom_ipin_13\/mux_l1_in_0_:A0 0.152 +33 chanx_right_in[1]:36 chanx_right_in[1]:35 0.0045 +34 chanx_right_in[1]:37 chanx_right_in[1]:36 0.00341 +35 chanx_right_in[1]:37 chanx_right_in[1]:33 0.001728425 +36 chanx_right_in[1]:35 chanx_right_in[1]:34 0.0001576087 +37 chanx_right_in[1]:34 mux_bottom_ipin_5\/mux_l1_in_0_:A0 0.152 +38 chanx_right_in[1]:29 mux_bottom_ipin_7\/mux_l1_in_0_:A0 0.152 +39 chanx_right_in[1]:29 chanx_right_in[1]:28 0.003662947 +40 chanx_right_in[1]:38 mux_bottom_ipin_15\/mux_l1_in_0_:A0 0.152 +41 chanx_right_in[1]:20 mux_bottom_ipin_9\/mux_l1_in_0_:A0 0.152 +42 chanx_right_in[1]:39 mux_bottom_ipin_1\/mux_l1_in_0_:A0 0.152 +43 chanx_right_in[1]:28 mux_bottom_ipin_3\/mux_l1_in_0_:A0 0.152 +44 chanx_right_in[1]:28 chanx_right_in[1]:27 0.0002212838 +45 chanx_right_in[1]:28 chanx_right_in[1]:10 4.898649e-05 +46 chanx_right_in[1]:26 chanx_right_in[1]:25 0.005709822 +47 chanx_right_in[1]:27 chanx_right_in[1]:26 0.0002723215 +48 chanx_right_in[1]:44 chanx_right_in[1]:43 0.004396066 + +*END + +*D_NET chanx_right_in[15] 0.02236321 //LENGTH 161.250 LUMPCC 0.006895784 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 102.580 1.325 +*I mux_bottom_ipin_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 36.800 39.780 +*I FTB_36__35:A I *L 0.001776 *C 10.120 31.280 +*I mux_bottom_ipin_11\/mux_l2_in_3_:A1 I *L 0.00198 *C 24.285 34.340 +*I mux_bottom_ipin_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 51.885 41.820 +*N chanx_right_in[15]:5 *C 51.885 41.820 +*N chanx_right_in[15]:6 *C 51.980 41.775 +*N chanx_right_in[15]:7 *C 51.980 39.498 +*N chanx_right_in[15]:8 *C 51.973 39.440 +*N chanx_right_in[15]:9 *C 10.083 31.280 +*N chanx_right_in[15]:10 *C 7.383 31.280 +*N chanx_right_in[15]:11 *C 7.360 31.620 +*N chanx_right_in[15]:12 *C 7.360 31.665 +*N chanx_right_in[15]:13 *C 7.360 33.263 +*N chanx_right_in[15]:14 *C 7.368 33.320 +*N chanx_right_in[15]:15 *C 24.373 33.320 +*N chanx_right_in[15]:16 *C 24.380 33.378 +*N chanx_right_in[15]:17 *C 24.380 34.295 +*N chanx_right_in[15]:18 *C 24.425 34.340 +*N chanx_right_in[15]:19 *C 28.935 34.340 +*N chanx_right_in[15]:20 *C 28.980 34.385 +*N chanx_right_in[15]:21 *C 28.980 38.703 +*N chanx_right_in[15]:22 *C 28.988 38.760 +*N chanx_right_in[15]:23 *C 36.800 39.780 +*N chanx_right_in[15]:24 *C 36.800 39.735 +*N chanx_right_in[15]:25 *C 36.800 38.818 +*N chanx_right_in[15]:26 *C 36.805 38.775 +*N chanx_right_in[15]:27 *C 37.260 38.765 +*N chanx_right_in[15]:28 *C 37.260 39.440 +*N chanx_right_in[15]:29 *C 43.240 39.440 +*N chanx_right_in[15]:30 *C 43.240 39.433 +*N chanx_right_in[15]:31 *C 43.240 6.808 +*N chanx_right_in[15]:32 *C 43.260 6.800 +*N chanx_right_in[15]:33 *C 93.050 6.800 +*N chanx_right_in[15]:34 *C 102.113 6.800 +*N chanx_right_in[15]:35 *C 102.120 6.800 +*N chanx_right_in[15]:36 *C 102.580 6.800 + +*CAP +0 chanx_right_in[15] 0.000292308 +1 mux_bottom_ipin_3\/mux_l2_in_3_:A1 1e-06 +2 FTB_36__35:A 1e-06 +3 mux_bottom_ipin_11\/mux_l2_in_3_:A1 1e-06 +4 mux_bottom_ipin_5\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[15]:5 3.078506e-05 +6 chanx_right_in[15]:6 0.0001467943 +7 chanx_right_in[15]:7 0.0001467943 +8 chanx_right_in[15]:8 0.0003373784 +9 chanx_right_in[15]:9 0.0001910997 +10 chanx_right_in[15]:10 0.0002253985 +11 chanx_right_in[15]:11 6.663513e-05 +12 chanx_right_in[15]:12 0.0001296969 +13 chanx_right_in[15]:13 0.0001296969 +14 chanx_right_in[15]:14 0.0005139561 +15 chanx_right_in[15]:15 0.0005139561 +16 chanx_right_in[15]:16 8.746585e-05 +17 chanx_right_in[15]:17 8.746585e-05 +18 chanx_right_in[15]:18 0.0003774579 +19 chanx_right_in[15]:19 0.0003774579 +20 chanx_right_in[15]:20 0.0002584119 +21 chanx_right_in[15]:21 0.0002584119 +22 chanx_right_in[15]:22 0.0004997937 +23 chanx_right_in[15]:23 3.231483e-05 +24 chanx_right_in[15]:24 7.985246e-05 +25 chanx_right_in[15]:25 7.985246e-05 +26 chanx_right_in[15]:26 0.0005312734 +27 chanx_right_in[15]:27 8.738698e-05 +28 chanx_right_in[15]:28 0.000357232 +29 chanx_right_in[15]:29 0.0006387031 +30 chanx_right_in[15]:30 0.002088089 +31 chanx_right_in[15]:31 0.002088089 +32 chanx_right_in[15]:32 0.001887389 +33 chanx_right_in[15]:33 0.002206636 +34 chanx_right_in[15]:34 0.000319247 +35 chanx_right_in[15]:35 6.99499e-05 +36 chanx_right_in[15]:36 0.0003264504 +37 chanx_right_in[15]:8 chanx_left_in[7]:15 1.99256e-05 +38 chanx_right_in[15]:15 chanx_left_in[7]:28 0.0006669954 +39 chanx_right_in[15]:14 chanx_left_in[7]:29 0.0006669954 +40 chanx_right_in[15]:29 chanx_left_in[7]:15 1.055983e-05 +41 chanx_right_in[15]:29 chanx_left_in[7]:16 1.99256e-05 +42 chanx_right_in[15]:28 chanx_left_in[7]:16 1.055983e-05 +43 chanx_right_in[15]:15 chanx_left_in[10]:26 0.0009390088 +44 chanx_right_in[15]:14 chanx_left_in[10] 0.0009390088 +45 chanx_right_in[15]:8 chanx_right_in[9]:23 0.0004888839 +46 chanx_right_in[15]:22 chanx_right_in[9]:19 0.0001480519 +47 chanx_right_in[15]:26 chanx_right_in[9]:19 3.491432e-06 +48 chanx_right_in[15]:26 chanx_right_in[9]:23 0.0001480519 +49 chanx_right_in[15]:29 chanx_right_in[9]:19 0.0004888839 +50 chanx_right_in[15]:29 chanx_right_in[9]:23 0.0003354499 +51 chanx_right_in[15]:27 chanx_right_in[9]:23 3.491432e-06 +52 chanx_right_in[15]:28 chanx_right_in[9]:19 0.0003354499 +53 chanx_right_in[15]:32 chanx_right_in[16]:16 0.0003334423 +54 chanx_right_in[15]:32 chanx_right_in[16]:12 5.102063e-06 +55 chanx_right_in[15]:32 chanx_right_in[16]:9 2.13117e-05 +56 chanx_right_in[15]:34 chanx_right_in[16] 0.0001555055 +57 chanx_right_in[15]:33 chanx_right_in[16] 0.0003334423 +58 chanx_right_in[15]:33 chanx_right_in[16]:13 5.102063e-06 +59 chanx_right_in[15]:33 chanx_right_in[16]:16 0.0001555055 +60 chanx_right_in[15]:33 chanx_right_in[16]:10 2.13117e-05 +61 chanx_right_in[15]:8 prog_clk[0]:270 3.58316e-06 +62 chanx_right_in[15]:20 prog_clk[0]:297 1.591472e-06 +63 chanx_right_in[15]:20 prog_clk[0]:296 4.35575e-07 +64 chanx_right_in[15]:21 prog_clk[0]:293 4.35575e-07 +65 chanx_right_in[15]:21 prog_clk[0]:296 1.591472e-06 +66 chanx_right_in[15]:22 prog_clk[0]:201 3.635365e-06 +67 chanx_right_in[15]:25 prog_clk[0]:199 8.508198e-07 +68 chanx_right_in[15]:26 prog_clk[0]:200 3.635365e-06 +69 chanx_right_in[15]:26 prog_clk[0]:201 3.548116e-06 +70 chanx_right_in[15]:24 prog_clk[0]:198 8.508198e-07 +71 chanx_right_in[15]:29 prog_clk[0]:271 3.58316e-06 +72 chanx_right_in[15]:29 prog_clk[0]:200 4.231213e-06 +73 chanx_right_in[15]:29 prog_clk[0]:164 9.339372e-06 +74 chanx_right_in[15]:32 prog_clk[0]:129 1.058539e-05 +75 chanx_right_in[15]:32 prog_clk[0]:144 8.874273e-06 +76 chanx_right_in[15]:32 prog_clk[0]:134 0.0001021963 +77 chanx_right_in[15]:32 prog_clk[0]:139 3.499179e-05 +78 chanx_right_in[15]:32 prog_clk[0]:117 7.512081e-05 +79 chanx_right_in[15]:32 prog_clk[0]:69 5.382533e-05 +80 chanx_right_in[15]:27 prog_clk[0]:199 7.354752e-06 +81 chanx_right_in[15]:27 prog_clk[0]:200 3.548116e-06 +82 chanx_right_in[15]:28 prog_clk[0]:200 9.339372e-06 +83 chanx_right_in[15]:28 prog_clk[0]:201 4.231213e-06 +84 chanx_right_in[15]:28 prog_clk[0]:198 7.354752e-06 +85 chanx_right_in[15]:33 prog_clk[0]:129 0.0001021963 +86 chanx_right_in[15]:33 prog_clk[0]:112 7.512081e-05 +87 chanx_right_in[15]:33 prog_clk[0]:68 5.382533e-05 +88 chanx_right_in[15]:33 prog_clk[0]:134 3.499179e-05 +89 chanx_right_in[15]:33 prog_clk[0]:139 8.874273e-06 +90 chanx_right_in[15]:33 prog_clk[0]:117 1.058539e-05 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:36 0.004888393 +1 chanx_right_in[15]:7 chanx_right_in[15]:6 0.002033482 +2 chanx_right_in[15]:8 chanx_right_in[15]:7 0.00341 +3 chanx_right_in[15]:5 mux_bottom_ipin_5\/mux_l2_in_3_:A1 0.152 +4 chanx_right_in[15]:6 chanx_right_in[15]:5 0.0045 +5 chanx_right_in[15]:19 chanx_right_in[15]:18 0.004026786 +6 chanx_right_in[15]:20 chanx_right_in[15]:19 0.0045 +7 chanx_right_in[15]:21 chanx_right_in[15]:20 0.00385491 +8 chanx_right_in[15]:22 chanx_right_in[15]:21 0.00341 +9 chanx_right_in[15]:25 chanx_right_in[15]:24 0.0008191965 +10 chanx_right_in[15]:26 chanx_right_in[15]:25 0.00341 +11 chanx_right_in[15]:26 chanx_right_in[15]:22 0.001224742 +12 chanx_right_in[15]:23 mux_bottom_ipin_3\/mux_l2_in_3_:A1 0.152 +13 chanx_right_in[15]:24 chanx_right_in[15]:23 0.0045 +14 chanx_right_in[15]:18 chanx_right_in[15]:17 0.0045 +15 chanx_right_in[15]:18 mux_bottom_ipin_11\/mux_l2_in_3_:A1 0.152 +16 chanx_right_in[15]:17 chanx_right_in[15]:16 0.0008191965 +17 chanx_right_in[15]:16 chanx_right_in[15]:15 0.00341 +18 chanx_right_in[15]:15 chanx_right_in[15]:14 0.002664116 +19 chanx_right_in[15]:13 chanx_right_in[15]:12 0.001426339 +20 chanx_right_in[15]:14 chanx_right_in[15]:13 0.00341 +21 chanx_right_in[15]:11 chanx_right_in[15]:10 0.0001847826 +22 chanx_right_in[15]:12 chanx_right_in[15]:11 0.0045 +23 chanx_right_in[15]:9 FTB_36__35:A 0.152 +24 chanx_right_in[15]:29 chanx_right_in[15]:28 0.0009368666 +25 chanx_right_in[15]:29 chanx_right_in[15]:8 0.001368092 +26 chanx_right_in[15]:30 chanx_right_in[15]:29 0.00341 +27 chanx_right_in[15]:32 chanx_right_in[15]:31 0.00341 +28 chanx_right_in[15]:31 chanx_right_in[15]:30 0.00511125 +29 chanx_right_in[15]:35 chanx_right_in[15]:34 0.00341 +30 chanx_right_in[15]:34 chanx_right_in[15]:33 0.001419792 +31 chanx_right_in[15]:10 chanx_right_in[15]:9 0.002410714 +32 chanx_right_in[15]:36 chanx_right_in[15]:35 0.0004107143 +33 chanx_right_in[15]:27 chanx_right_in[15]:26 7.128333e-05 +34 chanx_right_in[15]:28 chanx_right_in[15]:27 0.00010575 +35 chanx_right_in[15]:33 chanx_right_in[15]:32 0.007800433 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[1] 0.003032933 //LENGTH 23.705 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 51.360 17.680 +*I mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 50.775 15.300 +*I mux_bottom_ipin_4\/mux_l2_in_1_:S I *L 0.00357 *C 52.080 23.120 +*I mux_bottom_ipin_4\/mux_l2_in_0_:S I *L 0.00357 *C 50.040 23.120 +*I mux_bottom_ipin_4\/mux_l2_in_3_:S I *L 0.00357 *C 56.020 20.110 +*I mux_bottom_ipin_4\/mux_l2_in_2_:S I *L 0.00357 *C 58.060 20.400 +*N mux_tree_tapbuf_size10_2_sram[1]:6 *C 58.060 20.400 +*N mux_tree_tapbuf_size10_2_sram[1]:7 *C 57.960 20.060 +*N mux_tree_tapbuf_size10_2_sram[1]:8 *C 56.020 20.068 +*N mux_tree_tapbuf_size10_2_sram[1]:9 *C 55.963 20.400 +*N mux_tree_tapbuf_size10_2_sram[1]:10 *C 53.865 20.400 +*N mux_tree_tapbuf_size10_2_sram[1]:11 *C 53.820 20.355 +*N mux_tree_tapbuf_size10_2_sram[1]:12 *C 53.820 17.725 +*N mux_tree_tapbuf_size10_2_sram[1]:13 *C 53.775 17.680 +*N mux_tree_tapbuf_size10_2_sram[1]:14 *C 50.078 23.120 +*N mux_tree_tapbuf_size10_2_sram[1]:15 *C 50.600 23.120 +*N mux_tree_tapbuf_size10_2_sram[1]:16 *C 52.080 23.120 +*N mux_tree_tapbuf_size10_2_sram[1]:17 *C 51.980 22.780 +*N mux_tree_tapbuf_size10_2_sram[1]:18 *C 50.600 22.780 +*N mux_tree_tapbuf_size10_2_sram[1]:19 *C 50.600 22.735 +*N mux_tree_tapbuf_size10_2_sram[1]:20 *C 50.775 15.300 +*N mux_tree_tapbuf_size10_2_sram[1]:21 *C 50.600 15.300 +*N mux_tree_tapbuf_size10_2_sram[1]:22 *C 50.600 15.345 +*N mux_tree_tapbuf_size10_2_sram[1]:23 *C 50.600 17.680 +*N mux_tree_tapbuf_size10_2_sram[1]:24 *C 50.645 17.680 +*N mux_tree_tapbuf_size10_2_sram[1]:25 *C 51.360 17.680 + +*CAP +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_ipin_4\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_4\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_4\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_4\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size10_2_sram[1]:6 5.657927e-05 +7 mux_tree_tapbuf_size10_2_sram[1]:7 0.0001830831 +8 mux_tree_tapbuf_size10_2_sram[1]:8 0.0001830254 +9 mux_tree_tapbuf_size10_2_sram[1]:9 0.0002182679 +10 mux_tree_tapbuf_size10_2_sram[1]:10 0.0001903989 +11 mux_tree_tapbuf_size10_2_sram[1]:11 0.0001673 +12 mux_tree_tapbuf_size10_2_sram[1]:12 0.0001673 +13 mux_tree_tapbuf_size10_2_sram[1]:13 0.0001399772 +14 mux_tree_tapbuf_size10_2_sram[1]:14 6.062483e-05 +15 mux_tree_tapbuf_size10_2_sram[1]:15 8.743029e-05 +16 mux_tree_tapbuf_size10_2_sram[1]:16 5.947881e-05 +17 mux_tree_tapbuf_size10_2_sram[1]:17 0.0001298563 +18 mux_tree_tapbuf_size10_2_sram[1]:18 0.0001257239 +19 mux_tree_tapbuf_size10_2_sram[1]:19 0.0002973822 +20 mux_tree_tapbuf_size10_2_sram[1]:20 4.648221e-05 +21 mux_tree_tapbuf_size10_2_sram[1]:21 5.047581e-05 +22 mux_tree_tapbuf_size10_2_sram[1]:22 0.0001346239 +23 mux_tree_tapbuf_size10_2_sram[1]:23 0.0004651336 +24 mux_tree_tapbuf_size10_2_sram[1]:24 4.886399e-05 +25 mux_tree_tapbuf_size10_2_sram[1]:25 0.0002149254 + +*RES +0 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_2_sram[1]:25 0.152 +1 mux_tree_tapbuf_size10_2_sram[1]:25 mux_tree_tapbuf_size10_2_sram[1]:24 0.000638393 +2 mux_tree_tapbuf_size10_2_sram[1]:25 mux_tree_tapbuf_size10_2_sram[1]:13 0.00215625 +3 mux_tree_tapbuf_size10_2_sram[1]:24 mux_tree_tapbuf_size10_2_sram[1]:23 0.0045 +4 mux_tree_tapbuf_size10_2_sram[1]:23 mux_tree_tapbuf_size10_2_sram[1]:22 0.002084821 +5 mux_tree_tapbuf_size10_2_sram[1]:23 mux_tree_tapbuf_size10_2_sram[1]:19 0.004513394 +6 mux_tree_tapbuf_size10_2_sram[1]:18 mux_tree_tapbuf_size10_2_sram[1]:17 0.001232143 +7 mux_tree_tapbuf_size10_2_sram[1]:18 mux_tree_tapbuf_size10_2_sram[1]:15 0.0003035715 +8 mux_tree_tapbuf_size10_2_sram[1]:19 mux_tree_tapbuf_size10_2_sram[1]:18 0.0045 +9 mux_tree_tapbuf_size10_2_sram[1]:13 mux_tree_tapbuf_size10_2_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size10_2_sram[1]:12 mux_tree_tapbuf_size10_2_sram[1]:11 0.002348214 +11 mux_tree_tapbuf_size10_2_sram[1]:10 mux_tree_tapbuf_size10_2_sram[1]:9 0.001872768 +12 mux_tree_tapbuf_size10_2_sram[1]:11 mux_tree_tapbuf_size10_2_sram[1]:10 0.0045 +13 mux_tree_tapbuf_size10_2_sram[1]:21 mux_tree_tapbuf_size10_2_sram[1]:20 9.510871e-05 +14 mux_tree_tapbuf_size10_2_sram[1]:22 mux_tree_tapbuf_size10_2_sram[1]:21 0.0045 +15 mux_tree_tapbuf_size10_2_sram[1]:20 mem_bottom_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size10_2_sram[1]:8 mux_bottom_ipin_4\/mux_l2_in_3_:S 0.152 +17 mux_tree_tapbuf_size10_2_sram[1]:8 mux_tree_tapbuf_size10_2_sram[1]:7 0.001732143 +18 mux_tree_tapbuf_size10_2_sram[1]:6 mux_bottom_ipin_4\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_2_sram[1]:16 mux_bottom_ipin_4\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_2_sram[1]:14 mux_bottom_ipin_4\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_2_sram[1]:15 mux_tree_tapbuf_size10_2_sram[1]:14 0.0004665179 +22 mux_tree_tapbuf_size10_2_sram[1]:17 mux_tree_tapbuf_size10_2_sram[1]:16 0.0003035715 +23 mux_tree_tapbuf_size10_2_sram[1]:9 mux_tree_tapbuf_size10_2_sram[1]:8 0.000193314 +24 mux_tree_tapbuf_size10_2_sram[1]:7 mux_tree_tapbuf_size10_2_sram[1]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[2] 0.003409745 //LENGTH 26.620 LUMPCC 0.00017903 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 21.750 65.960 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 8.905 64.260 +*I mux_bottom_ipin_9\/mux_l3_in_0_:S I *L 0.00357 *C 12.980 58.480 +*I mux_bottom_ipin_9\/mux_l3_in_1_:S I *L 0.00357 *C 15.280 61.495 +*N mux_tree_tapbuf_size10_5_sram[2]:4 *C 15.280 61.495 +*N mux_tree_tapbuf_size10_5_sram[2]:5 *C 12.880 58.480 +*N mux_tree_tapbuf_size10_5_sram[2]:6 *C 12.880 58.525 +*N mux_tree_tapbuf_size10_5_sram[2]:7 *C 8.943 64.260 +*N mux_tree_tapbuf_size10_5_sram[2]:8 *C 12.375 64.260 +*N mux_tree_tapbuf_size10_5_sram[2]:9 *C 12.420 64.215 +*N mux_tree_tapbuf_size10_5_sram[2]:10 *C 12.420 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:11 *C 12.880 61.835 +*N mux_tree_tapbuf_size10_5_sram[2]:12 *C 12.925 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:13 *C 13.800 61.880 +*N mux_tree_tapbuf_size10_5_sram[2]:14 *C 13.800 61.200 +*N mux_tree_tapbuf_size10_5_sram[2]:15 *C 15.280 61.200 +*N mux_tree_tapbuf_size10_5_sram[2]:16 *C 19.275 61.200 +*N mux_tree_tapbuf_size10_5_sram[2]:17 *C 19.320 61.245 +*N mux_tree_tapbuf_size10_5_sram[2]:18 *C 19.320 65.915 +*N mux_tree_tapbuf_size10_5_sram[2]:19 *C 19.365 65.960 +*N mux_tree_tapbuf_size10_5_sram[2]:20 *C 21.713 65.960 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_9\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_ipin_9\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_5_sram[2]:4 5.399437e-05 +5 mux_tree_tapbuf_size10_5_sram[2]:5 3.65915e-05 +6 mux_tree_tapbuf_size10_5_sram[2]:6 0.0001867307 +7 mux_tree_tapbuf_size10_5_sram[2]:7 0.0002848833 +8 mux_tree_tapbuf_size10_5_sram[2]:8 0.0002848833 +9 mux_tree_tapbuf_size10_5_sram[2]:9 0.0001652273 +10 mux_tree_tapbuf_size10_5_sram[2]:10 0.0001981996 +11 mux_tree_tapbuf_size10_5_sram[2]:11 0.000219703 +12 mux_tree_tapbuf_size10_5_sram[2]:12 7.815604e-05 +13 mux_tree_tapbuf_size10_5_sram[2]:13 0.0001192361 +14 mux_tree_tapbuf_size10_5_sram[2]:14 0.0001106476 +15 mux_tree_tapbuf_size10_5_sram[2]:15 0.0003207932 +16 mux_tree_tapbuf_size10_5_sram[2]:16 0.0002252595 +17 mux_tree_tapbuf_size10_5_sram[2]:17 0.0002704628 +18 mux_tree_tapbuf_size10_5_sram[2]:18 0.0002704628 +19 mux_tree_tapbuf_size10_5_sram[2]:19 0.0002007419 +20 mux_tree_tapbuf_size10_5_sram[2]:20 0.0002007419 +21 mux_tree_tapbuf_size10_5_sram[2]:16 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.948129e-05 +22 mux_tree_tapbuf_size10_5_sram[2]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.280937e-06 +23 mux_tree_tapbuf_size10_5_sram[2]:13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.452992e-07 +24 mux_tree_tapbuf_size10_5_sram[2]:14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.452992e-07 +25 mux_tree_tapbuf_size10_5_sram[2]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.280937e-06 +26 mux_tree_tapbuf_size10_5_sram[2]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.948129e-05 +27 mux_tree_tapbuf_size10_5_sram[2]:12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.177759e-06 +28 mux_tree_tapbuf_size10_5_sram[2]:13 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.177759e-06 +29 mux_tree_tapbuf_size10_5_sram[2]:14 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.162973e-05 +30 mux_tree_tapbuf_size10_5_sram[2]:15 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.162973e-05 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_5_sram[2]:20 0.152 +1 mux_tree_tapbuf_size10_5_sram[2]:12 mux_tree_tapbuf_size10_5_sram[2]:11 0.0045 +2 mux_tree_tapbuf_size10_5_sram[2]:11 mux_tree_tapbuf_size10_5_sram[2]:10 0.0004107143 +3 mux_tree_tapbuf_size10_5_sram[2]:11 mux_tree_tapbuf_size10_5_sram[2]:6 0.002955357 +4 mux_tree_tapbuf_size10_5_sram[2]:16 mux_tree_tapbuf_size10_5_sram[2]:15 0.003566965 +5 mux_tree_tapbuf_size10_5_sram[2]:17 mux_tree_tapbuf_size10_5_sram[2]:16 0.0045 +6 mux_tree_tapbuf_size10_5_sram[2]:19 mux_tree_tapbuf_size10_5_sram[2]:18 0.0045 +7 mux_tree_tapbuf_size10_5_sram[2]:18 mux_tree_tapbuf_size10_5_sram[2]:17 0.004169643 +8 mux_tree_tapbuf_size10_5_sram[2]:20 mux_tree_tapbuf_size10_5_sram[2]:19 0.002095982 +9 mux_tree_tapbuf_size10_5_sram[2]:8 mux_tree_tapbuf_size10_5_sram[2]:7 0.003064732 +10 mux_tree_tapbuf_size10_5_sram[2]:9 mux_tree_tapbuf_size10_5_sram[2]:8 0.0045 +11 mux_tree_tapbuf_size10_5_sram[2]:7 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_5_sram[2]:4 mux_bottom_ipin_9\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_5_sram[2]:5 mux_bottom_ipin_9\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size10_5_sram[2]:6 mux_tree_tapbuf_size10_5_sram[2]:5 0.0045 +15 mux_tree_tapbuf_size10_5_sram[2]:13 mux_tree_tapbuf_size10_5_sram[2]:12 0.0007812501 +16 mux_tree_tapbuf_size10_5_sram[2]:14 mux_tree_tapbuf_size10_5_sram[2]:13 0.0006071429 +17 mux_tree_tapbuf_size10_5_sram[2]:15 mux_tree_tapbuf_size10_5_sram[2]:14 0.001321429 +18 mux_tree_tapbuf_size10_5_sram[2]:15 mux_tree_tapbuf_size10_5_sram[2]:4 0.0001271552 +19 mux_tree_tapbuf_size10_5_sram[2]:10 mux_tree_tapbuf_size10_5_sram[2]:9 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_2_ccff_tail[0] 0.0007267749 //LENGTH 6.120 LUMPCC 7.478027e-05 DR + +*CONN +*I mem_bottom_ipin_4\/FTB_3__42:X O *L 0 *C 56.345 34.680 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 53.535 37.060 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 *C 53.573 37.060 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 *C 55.615 37.060 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 *C 55.660 37.015 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 *C 55.660 34.725 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 *C 55.705 34.680 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 *C 56.308 34.680 + +*CAP +0 mem_bottom_ipin_4\/FTB_3__42:X 1e-06 +1 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 0.0001380194 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 0.0001380194 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.0001440377 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0001440377 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 4.29402e-05 +7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 4.29402e-05 +8 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 chanx_left_in[4]:25 3.739013e-05 +9 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 chanx_left_in[4]:24 3.739013e-05 + +*RES +0 mem_bottom_ipin_4\/FTB_3__42:X mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 0.001823661 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[1] 0.005072092 //LENGTH 37.075 LUMPCC 0.0005728882 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 43.085 15.300 +*I mux_bottom_ipin_2\/mux_l2_in_3_:S I *L 0.00357 *C 41.500 19.720 +*I mux_bottom_ipin_2\/mux_l2_in_1_:S I *L 0.00357 *C 39.660 23.415 +*I mux_bottom_ipin_2\/mux_l2_in_0_:S I *L 0.00357 *C 40.140 25.160 +*I mux_bottom_ipin_2\/mux_l2_in_2_:S I *L 0.00357 *C 37.360 19.720 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 28.235 15.300 +*N mux_tree_tapbuf_size8_0_sram[1]:6 *C 28.235 15.300 +*N mux_tree_tapbuf_size8_0_sram[1]:7 *C 28.520 15.300 +*N mux_tree_tapbuf_size8_0_sram[1]:8 *C 28.520 15.345 +*N mux_tree_tapbuf_size8_0_sram[1]:9 *C 28.520 21.035 +*N mux_tree_tapbuf_size8_0_sram[1]:10 *C 28.565 21.080 +*N mux_tree_tapbuf_size8_0_sram[1]:11 *C 34.040 21.080 +*N mux_tree_tapbuf_size8_0_sram[1]:12 *C 34.040 20.060 +*N mux_tree_tapbuf_size8_0_sram[1]:13 *C 37.285 20.060 +*N mux_tree_tapbuf_size8_0_sram[1]:14 *C 37.398 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:15 *C 40.102 25.160 +*N mux_tree_tapbuf_size8_0_sram[1]:16 *C 39.605 25.160 +*N mux_tree_tapbuf_size8_0_sram[1]:17 *C 39.560 25.115 +*N mux_tree_tapbuf_size8_0_sram[1]:18 *C 39.660 23.415 +*N mux_tree_tapbuf_size8_0_sram[1]:19 *C 39.660 23.800 +*N mux_tree_tapbuf_size8_0_sram[1]:20 *C 39.145 23.800 +*N mux_tree_tapbuf_size8_0_sram[1]:21 *C 39.100 23.800 +*N mux_tree_tapbuf_size8_0_sram[1]:22 *C 39.560 23.800 +*N mux_tree_tapbuf_size8_0_sram[1]:23 *C 39.560 19.765 +*N mux_tree_tapbuf_size8_0_sram[1]:24 *C 39.560 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:25 *C 41.413 19.720 +*N mux_tree_tapbuf_size8_0_sram[1]:26 *C 41.400 19.675 +*N mux_tree_tapbuf_size8_0_sram[1]:27 *C 41.400 15.345 +*N mux_tree_tapbuf_size8_0_sram[1]:28 *C 41.445 15.300 +*N mux_tree_tapbuf_size8_0_sram[1]:29 *C 43.047 15.300 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_ipin_2\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_2\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_2\/mux_l2_in_2_:S 1e-06 +5 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size8_0_sram[1]:6 4.727757e-05 +7 mux_tree_tapbuf_size8_0_sram[1]:7 5.068916e-05 +8 mux_tree_tapbuf_size8_0_sram[1]:8 0.0003374574 +9 mux_tree_tapbuf_size8_0_sram[1]:9 0.0003374574 +10 mux_tree_tapbuf_size8_0_sram[1]:10 0.0002557157 +11 mux_tree_tapbuf_size8_0_sram[1]:11 0.0003225997 +12 mux_tree_tapbuf_size8_0_sram[1]:12 0.0003502124 +13 mux_tree_tapbuf_size8_0_sram[1]:13 0.0003188747 +14 mux_tree_tapbuf_size8_0_sram[1]:14 0.000187949 +15 mux_tree_tapbuf_size8_0_sram[1]:15 6.86251e-05 +16 mux_tree_tapbuf_size8_0_sram[1]:16 6.86251e-05 +17 mux_tree_tapbuf_size8_0_sram[1]:17 8.184638e-05 +18 mux_tree_tapbuf_size8_0_sram[1]:18 5.614862e-05 +19 mux_tree_tapbuf_size8_0_sram[1]:19 8.531892e-05 +20 mux_tree_tapbuf_size8_0_sram[1]:20 5.641978e-05 +21 mux_tree_tapbuf_size8_0_sram[1]:21 6.574434e-05 +22 mux_tree_tapbuf_size8_0_sram[1]:22 0.0003775062 +23 mux_tree_tapbuf_size8_0_sram[1]:23 0.0002618911 +24 mux_tree_tapbuf_size8_0_sram[1]:24 0.0002903242 +25 mux_tree_tapbuf_size8_0_sram[1]:25 0.0001041946 +26 mux_tree_tapbuf_size8_0_sram[1]:26 0.0002416809 +27 mux_tree_tapbuf_size8_0_sram[1]:27 0.0002416809 +28 mux_tree_tapbuf_size8_0_sram[1]:28 0.0001424827 +29 mux_tree_tapbuf_size8_0_sram[1]:29 0.0001424827 +30 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[2]:4 0.0001992132 +31 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[2]:5 0.0001992132 +32 mux_tree_tapbuf_size8_0_sram[1]:14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.287256e-05 +33 mux_tree_tapbuf_size8_0_sram[1]:25 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.604598e-05 +34 mux_tree_tapbuf_size8_0_sram[1]:26 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.571995e-06 +35 mux_tree_tapbuf_size8_0_sram[1]:27 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.571995e-06 +36 mux_tree_tapbuf_size8_0_sram[1]:24 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.604598e-05 +37 mux_tree_tapbuf_size8_0_sram[1]:24 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.287256e-05 +38 mux_tree_tapbuf_size8_0_sram[1]:23 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.574039e-05 +39 mux_tree_tapbuf_size8_0_sram[1]:22 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.574039e-05 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_0_sram[1]:29 0.152 +1 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:19 0.0004598215 +2 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:20 0.0045 +3 mux_tree_tapbuf_size8_0_sram[1]:18 mux_bottom_ipin_2\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size8_0_sram[1]:14 mux_bottom_ipin_2\/mux_l2_in_2_:S 0.152 +5 mux_tree_tapbuf_size8_0_sram[1]:14 mux_tree_tapbuf_size8_0_sram[1]:13 0.0001770834 +6 mux_tree_tapbuf_size8_0_sram[1]:25 mux_bottom_ipin_2\/mux_l2_in_3_:S 0.152 +7 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:24 0.001654018 +8 mux_tree_tapbuf_size8_0_sram[1]:26 mux_tree_tapbuf_size8_0_sram[1]:25 0.0045 +9 mux_tree_tapbuf_size8_0_sram[1]:28 mux_tree_tapbuf_size8_0_sram[1]:27 0.0045 +10 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size8_0_sram[1]:26 0.003866071 +11 mux_tree_tapbuf_size8_0_sram[1]:29 mux_tree_tapbuf_size8_0_sram[1]:28 0.001430804 +12 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size8_0_sram[1]:23 0.0045 +13 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size8_0_sram[1]:14 0.001930804 +14 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size8_0_sram[1]:22 0.003602679 +15 mux_tree_tapbuf_size8_0_sram[1]:6 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size8_0_sram[1]:7 mux_tree_tapbuf_size8_0_sram[1]:6 0.0001548913 +17 mux_tree_tapbuf_size8_0_sram[1]:8 mux_tree_tapbuf_size8_0_sram[1]:7 0.0045 +18 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[1]:9 0.0045 +19 mux_tree_tapbuf_size8_0_sram[1]:9 mux_tree_tapbuf_size8_0_sram[1]:8 0.005080357 +20 mux_tree_tapbuf_size8_0_sram[1]:15 mux_bottom_ipin_2\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size8_0_sram[1]:16 mux_tree_tapbuf_size8_0_sram[1]:15 0.0004441965 +22 mux_tree_tapbuf_size8_0_sram[1]:17 mux_tree_tapbuf_size8_0_sram[1]:16 0.0045 +23 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[1]:10 0.004888393 +24 mux_tree_tapbuf_size8_0_sram[1]:12 mux_tree_tapbuf_size8_0_sram[1]:11 0.0009107143 +25 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:12 0.002897321 +26 mux_tree_tapbuf_size8_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:18 0.00034375 +27 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:21 0.0004107143 +28 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:17 0.001174107 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[3] 0.00175362 //LENGTH 12.700 LUMPCC 0.0002008673 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 23.305 15.300 +*I mux_bottom_ipin_10\/mux_l4_in_0_:S I *L 0.00357 *C 16.200 17.680 +*I mem_bottom_ipin_10\/FTB_13__52:A I *L 0.001746 *C 24.380 17.680 +*N mux_tree_tapbuf_size8_4_sram[3]:3 *C 24.343 17.680 +*N mux_tree_tapbuf_size8_4_sram[3]:4 *C 16.238 17.680 +*N mux_tree_tapbuf_size8_4_sram[3]:5 *C 22.080 17.680 +*N mux_tree_tapbuf_size8_4_sram[3]:6 *C 22.080 17.635 +*N mux_tree_tapbuf_size8_4_sram[3]:7 *C 22.080 15.345 +*N mux_tree_tapbuf_size8_4_sram[3]:8 *C 22.125 15.300 +*N mux_tree_tapbuf_size8_4_sram[3]:9 *C 23.268 15.300 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_10\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_10\/FTB_13__52:A 1e-06 +3 mux_tree_tapbuf_size8_4_sram[3]:3 0.0001298806 +4 mux_tree_tapbuf_size8_4_sram[3]:4 0.0003961872 +5 mux_tree_tapbuf_size8_4_sram[3]:5 0.0005573581 +6 mux_tree_tapbuf_size8_4_sram[3]:6 0.0001420156 +7 mux_tree_tapbuf_size8_4_sram[3]:7 0.0001420156 +8 mux_tree_tapbuf_size8_4_sram[3]:8 9.114794e-05 +9 mux_tree_tapbuf_size8_4_sram[3]:9 9.114794e-05 +10 mux_tree_tapbuf_size8_4_sram[3]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.626452e-05 +11 mux_tree_tapbuf_size8_4_sram[3]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.939723e-05 +12 mux_tree_tapbuf_size8_4_sram[3]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.311787e-05 +13 mux_tree_tapbuf_size8_4_sram[3]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.626452e-05 +14 mux_tree_tapbuf_size8_4_sram[3]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.939723e-05 +15 mux_tree_tapbuf_size8_4_sram[3]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.311787e-05 +16 mux_tree_tapbuf_size8_4_sram[3]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.165406e-05 +17 mux_tree_tapbuf_size8_4_sram[3]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.165406e-05 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_4_sram[3]:9 0.152 +1 mux_tree_tapbuf_size8_4_sram[3]:9 mux_tree_tapbuf_size8_4_sram[3]:8 0.001020089 +2 mux_tree_tapbuf_size8_4_sram[3]:8 mux_tree_tapbuf_size8_4_sram[3]:7 0.0045 +3 mux_tree_tapbuf_size8_4_sram[3]:7 mux_tree_tapbuf_size8_4_sram[3]:6 0.002044643 +4 mux_tree_tapbuf_size8_4_sram[3]:5 mux_tree_tapbuf_size8_4_sram[3]:4 0.005216518 +5 mux_tree_tapbuf_size8_4_sram[3]:5 mux_tree_tapbuf_size8_4_sram[3]:3 0.002020089 +6 mux_tree_tapbuf_size8_4_sram[3]:6 mux_tree_tapbuf_size8_4_sram[3]:5 0.0045 +7 mux_tree_tapbuf_size8_4_sram[3]:3 mem_bottom_ipin_10\/FTB_13__52:A 0.152 +8 mux_tree_tapbuf_size8_4_sram[3]:4 mux_bottom_ipin_10\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[3] 0.001105288 //LENGTH 9.085 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 81.265 49.980 +*I mux_bottom_ipin_14\/mux_l4_in_0_:S I *L 0.00357 *C 81.980 47.600 +*I mem_bottom_ipin_14\/FTB_15__54:A I *L 0.001746 *C 79.580 53.040 +*N mux_tree_tapbuf_size8_6_sram[3]:3 *C 79.618 53.040 +*N mux_tree_tapbuf_size8_6_sram[3]:4 *C 81.375 53.040 +*N mux_tree_tapbuf_size8_6_sram[3]:5 *C 81.420 52.995 +*N mux_tree_tapbuf_size8_6_sram[3]:6 *C 81.880 47.600 +*N mux_tree_tapbuf_size8_6_sram[3]:7 *C 81.880 47.645 +*N mux_tree_tapbuf_size8_6_sram[3]:8 *C 81.880 49.980 +*N mux_tree_tapbuf_size8_6_sram[3]:9 *C 81.420 49.980 +*N mux_tree_tapbuf_size8_6_sram[3]:10 *C 81.420 49.980 +*N mux_tree_tapbuf_size8_6_sram[3]:11 *C 81.265 49.980 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_14\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_14\/FTB_15__54:A 1e-06 +3 mux_tree_tapbuf_size8_6_sram[3]:3 0.0001330287 +4 mux_tree_tapbuf_size8_6_sram[3]:4 0.0001330287 +5 mux_tree_tapbuf_size8_6_sram[3]:5 0.0001741859 +6 mux_tree_tapbuf_size8_6_sram[3]:6 3.360431e-05 +7 mux_tree_tapbuf_size8_6_sram[3]:7 0.0001482833 +8 mux_tree_tapbuf_size8_6_sram[3]:8 0.0001795652 +9 mux_tree_tapbuf_size8_6_sram[3]:9 0.0002054677 +10 mux_tree_tapbuf_size8_6_sram[3]:10 4.972407e-05 +11 mux_tree_tapbuf_size8_6_sram[3]:11 4.54e-05 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_6_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_6_sram[3]:10 mux_tree_tapbuf_size8_6_sram[3]:9 0.0045 +2 mux_tree_tapbuf_size8_6_sram[3]:9 mux_tree_tapbuf_size8_6_sram[3]:8 0.0004107143 +3 mux_tree_tapbuf_size8_6_sram[3]:9 mux_tree_tapbuf_size8_6_sram[3]:5 0.002691964 +4 mux_tree_tapbuf_size8_6_sram[3]:11 mux_tree_tapbuf_size8_6_sram[3]:10 8.423914e-05 +5 mux_tree_tapbuf_size8_6_sram[3]:6 mux_bottom_ipin_14\/mux_l4_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_6_sram[3]:7 mux_tree_tapbuf_size8_6_sram[3]:6 0.0045 +7 mux_tree_tapbuf_size8_6_sram[3]:4 mux_tree_tapbuf_size8_6_sram[3]:3 0.001569197 +8 mux_tree_tapbuf_size8_6_sram[3]:5 mux_tree_tapbuf_size8_6_sram[3]:4 0.0045 +9 mux_tree_tapbuf_size8_6_sram[3]:3 mem_bottom_ipin_14\/FTB_15__54:A 0.152 +10 mux_tree_tapbuf_size8_6_sram[3]:8 mux_tree_tapbuf_size8_6_sram[3]:7 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_0_ccff_tail[0] 0.0005950257 //LENGTH 4.660 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/FTB_9__48:X O *L 0 *C 30.125 28.560 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 29.615 31.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 *C 29.615 31.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 *C 29.440 31.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 *C 29.440 31.575 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 *C 29.440 28.605 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 *C 29.485 28.560 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 *C 30.088 28.560 + +*CAP +0 mem_bottom_ipin_2\/FTB_9__48:X 1e-06 +1 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 5.210691e-05 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 5.573953e-05 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0001898406 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0001898406 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 5.274899e-05 +7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 5.274899e-05 + +*RES +0 mem_bottom_ipin_2\/FTB_9__48:X mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001028855 //LENGTH 7.825 LUMPCC 0.0002831445 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_0_:X O *L 0 *C 84.815 28.900 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 77.280 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 77.318 28.900 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.778 28.900 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003718554 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003718554 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[0]:41 4.719714e-05 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[0]:42 1.617762e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[0]:36 4.719714e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[0]:41 1.617762e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:10 7.819751e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:11 7.819751e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.006660715 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001624569 //LENGTH 11.440 LUMPCC 0.0004372066 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_1_:X O *L 0 *C 60.435 17.680 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 60.090 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 60.090 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 60.260 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 60.260 28.175 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 60.260 17.725 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 60.260 17.680 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 60.435 17.680 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.222902e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.255928e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004728255 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004728255 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.841406e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.650874e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:10 0.0002163771 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:12 2.226172e-06 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:11 0.0002163771 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:13 2.226172e-06 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.009330357 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003307953 //LENGTH 2.475 LUMPCC 6.487644e-05 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l3_in_1_:X O *L 0 *C 48.475 60.520 +*I mux_bottom_ipin_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 46.290 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 46.328 60.520 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 48.438 60.520 + +*CAP +0 mux_bottom_ipin_1\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001319594 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001319594 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_1_sram[3]:8 3.243822e-05 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_1_sram[3]:9 3.243822e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l3_in_1_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_1\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001883929 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004208131 //LENGTH 2.260 LUMPCC 8.453365e-05 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_3_:X O *L 0 *C 56.865 21.080 +*I mux_bottom_ipin_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 57.330 22.440 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 57.330 22.440 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 57.040 22.440 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 57.040 22.395 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 57.040 21.125 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 57.040 21.080 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 56.865 21.080 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.305462e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.243799e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.869209e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.869209e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.742059e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.39821e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.226682e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.226682e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_3_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001576087 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133928 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET optlc_net_125 0.007321125 //LENGTH 56.232 LUMPCC 0.0005937825 DR + +*CONN +*I optlc_124:HI O *L 0 *C 61.180 58.820 +*I mux_bottom_ipin_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 52.270 42.840 +*I mux_bottom_ipin_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 50.890 55.420 +*I mux_bottom_ipin_7\/mux_l2_in_3_:A0 I *L 0.001631 *C 39.850 60.520 +*I mux_bottom_ipin_15\/mux_l2_in_3_:A0 I *L 0.001631 *C 67.795 60.520 +*N optlc_net_125:5 *C 67.758 60.520 +*N optlc_net_125:6 *C 67.205 60.520 +*N optlc_net_125:7 *C 67.160 60.475 +*N optlc_net_125:8 *C 67.160 58.525 +*N optlc_net_125:9 *C 67.115 58.480 +*N optlc_net_125:10 *C 39.850 60.520 +*N optlc_net_125:11 *C 40.020 60.520 +*N optlc_net_125:12 *C 40.020 60.475 +*N optlc_net_125:13 *C 40.020 57.845 +*N optlc_net_125:14 *C 40.065 57.800 +*N optlc_net_125:15 *C 50.890 55.420 +*N optlc_net_125:16 *C 52.270 42.840 +*N optlc_net_125:17 *C 51.980 42.840 +*N optlc_net_125:18 *C 51.980 42.885 +*N optlc_net_125:19 *C 51.980 52.655 +*N optlc_net_125:20 *C 51.935 52.700 +*N optlc_net_125:21 *C 51.105 52.700 +*N optlc_net_125:22 *C 51.060 52.745 +*N optlc_net_125:23 *C 51.060 55.035 +*N optlc_net_125:24 *C 51.015 55.088 +*N optlc_net_125:25 *C 48.805 55.080 +*N optlc_net_125:26 *C 48.760 55.125 +*N optlc_net_125:27 *C 48.760 57.755 +*N optlc_net_125:28 *C 48.760 57.800 +*N optlc_net_125:29 *C 56.580 57.800 +*N optlc_net_125:30 *C 56.580 58.140 +*N optlc_net_125:31 *C 61.180 58.140 +*N optlc_net_125:32 *C 61.180 58.480 +*N optlc_net_125:33 *C 61.180 58.820 + +*CAP +0 optlc_124:HI 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_3_:A0 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_3_:A0 1e-06 +5 optlc_net_125:5 6.49569e-05 +6 optlc_net_125:6 6.49569e-05 +7 optlc_net_125:7 0.0001269625 +8 optlc_net_125:8 0.0001269625 +9 optlc_net_125:9 0.0003370267 +10 optlc_net_125:10 5.813794e-05 +11 optlc_net_125:11 6.290394e-05 +12 optlc_net_125:12 0.0001732295 +13 optlc_net_125:13 0.0001732295 +14 optlc_net_125:14 0.0005668622 +15 optlc_net_125:15 5.435123e-05 +16 optlc_net_125:16 5.880625e-05 +17 optlc_net_125:17 6.127165e-05 +18 optlc_net_125:18 0.0005549553 +19 optlc_net_125:19 0.0005549553 +20 optlc_net_125:20 7.038403e-05 +21 optlc_net_125:21 7.038403e-05 +22 optlc_net_125:22 0.0001436087 +23 optlc_net_125:23 0.0001436087 +24 optlc_net_125:24 0.0002049243 +25 optlc_net_125:25 0.0001788771 +26 optlc_net_125:26 0.0001663431 +27 optlc_net_125:27 0.0001663431 +28 optlc_net_125:28 0.00109807 +29 optlc_net_125:29 0.0005213106 +30 optlc_net_125:30 0.0002425951 +31 optlc_net_125:31 0.0002371433 +32 optlc_net_125:32 0.0003843317 +33 optlc_net_125:33 5.485061e-05 +34 optlc_net_125:28 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.873436e-05 +35 optlc_net_125:28 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.523274e-06 +36 optlc_net_125:29 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.002617e-05 +37 optlc_net_125:29 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.523274e-06 +38 optlc_net_125:30 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001453692 +39 optlc_net_125:31 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001440774 +40 optlc_net_125:9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00011381 +41 optlc_net_125:8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.454388e-06 +42 optlc_net_125:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.454388e-06 +43 optlc_net_125:32 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00011381 + +*RES +0 optlc_124:HI optlc_net_125:33 0.152 +1 optlc_net_125:24 optlc_net_125:23 0.0045 +2 optlc_net_125:24 optlc_net_125:15 0.0001807065 +3 optlc_net_125:23 optlc_net_125:22 0.002044643 +4 optlc_net_125:21 optlc_net_125:20 0.0007410714 +5 optlc_net_125:22 optlc_net_125:21 0.0045 +6 optlc_net_125:20 optlc_net_125:19 0.0045 +7 optlc_net_125:19 optlc_net_125:18 0.008723215 +8 optlc_net_125:17 optlc_net_125:16 0.0001576087 +9 optlc_net_125:18 optlc_net_125:17 0.0045 +10 optlc_net_125:16 mux_bottom_ipin_5\/mux_l2_in_3_:A0 0.152 +11 optlc_net_125:28 optlc_net_125:27 0.0045 +12 optlc_net_125:28 optlc_net_125:14 0.007763393 +13 optlc_net_125:27 optlc_net_125:26 0.002348214 +14 optlc_net_125:25 optlc_net_125:24 0.001973214 +15 optlc_net_125:26 optlc_net_125:25 0.0045 +16 optlc_net_125:33 optlc_net_125:32 0.0003035715 +17 optlc_net_125:15 mux_bottom_ipin_1\/mux_l2_in_3_:A0 0.152 +18 optlc_net_125:9 optlc_net_125:8 0.0045 +19 optlc_net_125:8 optlc_net_125:7 0.001741072 +20 optlc_net_125:6 optlc_net_125:5 0.0004933036 +21 optlc_net_125:7 optlc_net_125:6 0.0045 +22 optlc_net_125:5 mux_bottom_ipin_15\/mux_l2_in_3_:A0 0.152 +23 optlc_net_125:14 optlc_net_125:13 0.0045 +24 optlc_net_125:13 optlc_net_125:12 0.002348214 +25 optlc_net_125:11 optlc_net_125:10 9.23913e-05 +26 optlc_net_125:12 optlc_net_125:11 0.0045 +27 optlc_net_125:10 mux_bottom_ipin_7\/mux_l2_in_3_:A0 0.152 +28 optlc_net_125:29 optlc_net_125:28 0.006982143 +29 optlc_net_125:30 optlc_net_125:29 0.0003035715 +30 optlc_net_125:31 optlc_net_125:30 0.004107143 +31 optlc_net_125:32 optlc_net_125:31 0.0003035715 +32 optlc_net_125:32 optlc_net_125:9 0.005299107 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002967519 //LENGTH 24.580 LUMPCC 0.0006301499 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_2_:X O *L 0 *C 88.955 37.060 +*I mux_bottom_ipin_13\/mux_l2_in_1_:A1 I *L 0.00198 *C 86.385 58.140 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 86.422 58.140 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 87.815 58.140 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 87.860 58.095 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 87.860 37.105 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 87.905 37.060 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 88.918 37.060 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001340765 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001340765 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0009241529 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009241529 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001094551 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001094551 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:220 2.66541e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:223 5.481535e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:226 2.565902e-05 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:229 2.932161e-06 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:223 2.66541e-05 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:226 5.481535e-05 +14 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:229 2.565902e-05 +15 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:230 2.932161e-06 +16 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_6_sram[1]:18 7.335495e-05 +17 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_6_sram[1]:19 8.030052e-05 +18 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_6_sram[1]:15 7.335495e-05 +19 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_6_sram[1]:18 8.030052e-05 +20 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.135884e-05 +21 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.135884e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_2_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243304 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01874107 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.005948741 //LENGTH 47.570 LUMPCC 0.0006999582 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l4_in_0_:X O *L 0 *C 30.535 23.800 +*I mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 32.570 66.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 32.570 66.440 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 32.660 66.300 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 32.660 66.255 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 32.660 64.657 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 32.663 64.600 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 33.105 64.600 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 33.120 64.593 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 33.120 27.888 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 33.100 27.880 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 30.828 27.880 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 30.820 27.823 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 30.820 23.845 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 30.820 23.800 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 *C 30.535 23.800 + +*CAP +0 mux_bottom_ipin_2\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.721633e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.141483e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001040065 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001040065 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.87569e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.87569e-05 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.001915887 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.001915887 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001981242 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0001981242 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0002397489 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0002397489 +14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 5.895906e-05 +15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 5.614541e-05 +16 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chanx_right_in[11]:20 0.0003499791 +17 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 chanx_right_in[11]:19 0.0003499791 + +*RES +0 mux_bottom_ipin_2\/mux_l4_in_0_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.891305e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001426339 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.499219e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +8 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.005750449 +10 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.000356025 +12 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0045 +13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.00355134 +14 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:15 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001055933 //LENGTH 8.535 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l1_in_0_:X O *L 0 *C 38.355 50.320 +*I mux_bottom_ipin_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 36.340 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 36.378 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 38.135 56.100 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 38.180 56.055 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 38.180 50.365 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 38.180 50.320 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 38.355 50.320 + +*CAP +0 mux_bottom_ipin_7\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001513173 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001513173 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003202535 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003202535 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.710743e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.368412e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l1_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_7\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001569197 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005080357 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001005437 //LENGTH 7.785 LUMPCC 0.000225882 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l2_in_3_:X O *L 0 *C 22.255 23.120 +*I mux_bottom_ipin_10\/mux_l3_in_1_:A0 I *L 0.001631 *C 21.450 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 21.488 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 22.495 17.340 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 22.540 17.385 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 22.540 23.075 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 22.540 23.120 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 22.255 23.120 + +*CAP +0 mux_bottom_ipin_10\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.042248e-05 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.042248e-05 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000262025 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000262025 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.719849e-05 +7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.546114e-05 +8 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_4_sram[3]:4 2.311787e-05 +9 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_4_sram[3]:5 1.939723e-05 +10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_4_sram[3]:3 1.939723e-05 +11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_4_sram[3]:5 2.311787e-05 +12 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_4_sram[3]:7 1.626452e-05 +13 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_4_sram[3]:6 1.626452e-05 +14 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.416141e-05 +15 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.416141e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l2_in_3_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_10\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008995536 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.005080357 +6 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.880435e-05 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001257308 //LENGTH 10.340 LUMPCC 0.0004305999 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_0_:X O *L 0 *C 84.355 37.060 +*I mux_bottom_ipin_14\/mux_l3_in_0_:A1 I *L 0.00198 *C 82.900 45.220 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 82.800 45.220 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 82.800 45.175 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 82.800 37.105 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 82.845 37.060 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 84.318 37.060 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.391695e-05 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003213543 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003213543 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.404134e-05 +6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.404134e-05 +7 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[2]:56 3.419522e-05 +8 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[2]:57 6.286238e-05 +9 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[2]:54 3.419522e-05 +10 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[2]:56 6.286238e-05 +11 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[7]:22 6.828738e-05 +12 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[7]:23 6.828738e-05 +13 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.995498e-05 +14 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.995498e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_0_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.007205358 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006771452 //LENGTH 5.115 LUMPCC 0.0001346125 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l3_in_0_:X O *L 0 *C 64.225 64.260 +*I mux_bottom_ipin_15\/mux_l4_in_0_:A1 I *L 0.00198 *C 65.880 66.980 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 65.843 66.980 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 64.445 66.980 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 64.400 66.935 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 64.400 64.305 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 64.400 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 64.225 64.260 + +*CAP +0 mux_bottom_ipin_15\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.107974e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.107974e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001571924 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001571924 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.242324e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.156513e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_7_sram[3]:3 6.630152e-05 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_7_sram[3]:10 6.630152e-05 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_7_sram[3]:7 1.004743e-06 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_7_sram[3]:6 1.004743e-06 + +*RES +0 mux_bottom_ipin_15\/mux_l3_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_15\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001247768 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.510869e-05 + +*END + +*D_NET top_grid_pin_16_[0] 0.001540784 //LENGTH 14.110 LUMPCC 0.0001876992 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 41.135 69.020 +*P top_grid_pin_16_[0] O *L 0.7423 *C 34.040 74.870 +*N top_grid_pin_16_[0]:2 *C 34.040 73.498 +*N top_grid_pin_16_[0]:3 *C 34.047 73.440 +*N top_grid_pin_16_[0]:4 *C 38.172 73.440 +*N top_grid_pin_16_[0]:5 *C 38.180 73.383 +*N top_grid_pin_16_[0]:6 *C 38.180 69.065 +*N top_grid_pin_16_[0]:7 *C 38.225 69.020 +*N top_grid_pin_16_[0]:8 *C 41.098 69.020 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 top_grid_pin_16_[0] 9.46756e-05 +2 top_grid_pin_16_[0]:2 9.46756e-05 +3 top_grid_pin_16_[0]:3 0.0002195761 +4 top_grid_pin_16_[0]:4 0.0002195761 +5 top_grid_pin_16_[0]:5 0.0001958844 +6 top_grid_pin_16_[0]:6 0.0001958844 +7 top_grid_pin_16_[0]:7 0.0001659062 +8 top_grid_pin_16_[0]:8 0.0001659062 +9 top_grid_pin_16_[0]:8 ropt_net_134:3 4.569483e-05 +10 top_grid_pin_16_[0]:7 ropt_net_134:2 4.569483e-05 +11 top_grid_pin_16_[0]:6 ropt_net_134:4 4.81548e-05 +12 top_grid_pin_16_[0]:5 ropt_net_134:5 4.81548e-05 + +*RES +0 ropt_mt_inst_731:X top_grid_pin_16_[0]:8 0.152 +1 top_grid_pin_16_[0]:8 top_grid_pin_16_[0]:7 0.002564732 +2 top_grid_pin_16_[0]:7 top_grid_pin_16_[0]:6 0.0045 +3 top_grid_pin_16_[0]:6 top_grid_pin_16_[0]:5 0.003854911 +4 top_grid_pin_16_[0]:5 top_grid_pin_16_[0]:4 0.00341 +5 top_grid_pin_16_[0]:4 top_grid_pin_16_[0]:3 0.00064625 +6 top_grid_pin_16_[0]:2 top_grid_pin_16_[0] 0.001225446 +7 top_grid_pin_16_[0]:3 top_grid_pin_16_[0]:2 0.00341 + +*END + +*D_NET chanx_right_out[3] 0.001512758 //LENGTH 12.205 LUMPCC 0.0001247414 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 94.300 14.280 +*P chanx_right_out[3] O *L 0.7423 *C 103.650 12.240 +*N chanx_right_out[3]:2 *C 97.528 12.240 +*N chanx_right_out[3]:3 *C 97.520 12.298 +*N chanx_right_out[3]:4 *C 97.520 14.235 +*N chanx_right_out[3]:5 *C 97.475 14.280 +*N chanx_right_out[3]:6 *C 94.338 14.280 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 chanx_right_out[3] 0.0004000489 +2 chanx_right_out[3]:2 0.0004000489 +3 chanx_right_out[3]:3 7.647792e-05 +4 chanx_right_out[3]:4 7.647792e-05 +5 chanx_right_out[3]:5 0.0002169816 +6 chanx_right_out[3]:6 0.0002169816 +7 chanx_right_out[3]:3 ropt_net_150:4 6.237071e-05 +8 chanx_right_out[3]:4 ropt_net_150:5 6.237071e-05 + +*RES +0 ropt_mt_inst_739:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +2 chanx_right_out[3]:2 chanx_right_out[3] 0.0009591916 +3 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +4 chanx_right_out[3]:4 chanx_right_out[3]:3 0.001729911 +5 chanx_right_out[3]:6 chanx_right_out[3]:5 0.00280134 + +*END + +*D_NET chanx_left_out[18] 0.00181065 //LENGTH 14.500 LUMPCC 0.000147378 DR + +*CONN +*I FTB_39__38:X O *L 0 *C 15.180 72.760 +*P chanx_left_out[18] O *L 0.7423 *C 3.220 74.835 +*N chanx_left_out[18]:2 *C 3.220 72.805 +*N chanx_left_out[18]:3 *C 3.265 72.760 +*N chanx_left_out[18]:4 *C 15.143 72.760 + +*CAP +0 FTB_39__38:X 1e-06 +1 chanx_left_out[18] 0.0001244795 +2 chanx_left_out[18]:2 0.0001244795 +3 chanx_left_out[18]:3 0.0007066563 +4 chanx_left_out[18]:4 0.0007066563 +5 chanx_left_out[18]:4 ropt_net_170:3 4.698658e-05 +6 chanx_left_out[18]:4 ropt_net_170:5 1.4556e-05 +7 chanx_left_out[18]:4 ropt_net_170:7 1.21464e-05 +8 chanx_left_out[18]:3 ropt_net_170:2 4.698658e-05 +9 chanx_left_out[18]:3 ropt_net_170:4 1.4556e-05 +10 chanx_left_out[18]:3 ropt_net_170:6 1.21464e-05 + +*RES +0 FTB_39__38:X chanx_left_out[18]:4 0.152 +1 chanx_left_out[18]:4 chanx_left_out[18]:3 0.01060491 +2 chanx_left_out[18]:3 chanx_left_out[18]:2 0.0045 +3 chanx_left_out[18]:2 chanx_left_out[18] 0.0018125 + +*END + +*D_NET chanx_right_out[14] 0.001571249 //LENGTH 10.845 LUMPCC 0.0001276723 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 94.300 65.960 +*P chanx_right_out[14] O *L 0.7423 *C 103.650 65.280 +*N chanx_right_out[14]:2 *C 97.988 65.280 +*N chanx_right_out[14]:3 *C 97.980 65.338 +*N chanx_right_out[14]:4 *C 97.980 65.915 +*N chanx_right_out[14]:5 *C 97.935 65.960 +*N chanx_right_out[14]:6 *C 94.338 65.960 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 chanx_right_out[14] 0.0004326697 +2 chanx_right_out[14]:2 0.0004326697 +3 chanx_right_out[14]:3 3.53135e-05 +4 chanx_right_out[14]:4 3.53135e-05 +5 chanx_right_out[14]:5 0.000253305 +6 chanx_right_out[14]:6 0.000253305 +7 chanx_right_out[14] ropt_net_157:7 3.645915e-05 +8 chanx_right_out[14]:4 ropt_net_157:5 2.737699e-05 +9 chanx_right_out[14]:3 ropt_net_157:4 2.737699e-05 +10 chanx_right_out[14]:2 ropt_net_157:6 3.645915e-05 + +*RES +0 ropt_mt_inst_780:X chanx_right_out[14]:6 0.152 +1 chanx_right_out[14]:6 chanx_right_out[14]:5 0.003212053 +2 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +3 chanx_right_out[14]:4 chanx_right_out[14]:3 0.000515625 +4 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +5 chanx_right_out[14]:2 chanx_right_out[14] 0.0008871249 + +*END + +*D_NET ropt_net_189 0.0004487382 //LENGTH 3.295 LUMPCC 0.000127161 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 11.790 4.760 +*I ropt_mt_inst_796:A I *L 0.001767 *C 12.420 6.800 +*N ropt_net_189:2 *C 12.420 6.800 +*N ropt_net_189:3 *C 12.420 6.755 +*N ropt_net_189:4 *C 12.420 4.805 +*N ropt_net_189:5 *C 12.375 4.760 +*N ropt_net_189:6 *C 11.828 4.760 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_189:2 3.913056e-05 +3 ropt_net_189:3 8.033661e-05 +4 ropt_net_189:4 8.033661e-05 +5 ropt_net_189:5 5.988675e-05 +6 ropt_net_189:6 5.988675e-05 +7 ropt_net_189:4 chanx_right_in[3]:20 6.358048e-05 +8 ropt_net_189:3 chanx_right_in[3]:21 6.358048e-05 + +*RES +0 ropt_mt_inst_752:X ropt_net_189:6 0.152 +1 ropt_net_189:6 ropt_net_189:5 0.0004888393 +2 ropt_net_189:5 ropt_net_189:4 0.0045 +3 ropt_net_189:4 ropt_net_189:3 0.001741072 +4 ropt_net_189:2 ropt_mt_inst_796:A 0.152 +5 ropt_net_189:3 ropt_net_189:2 0.0045 + +*END + +*D_NET top_grid_pin_21_[0] 0.0009679252 //LENGTH 8.870 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_787:X O *L 0 *C 20.700 71.400 +*P top_grid_pin_21_[0] O *L 0.7423 *C 16.100 74.870 +*N top_grid_pin_21_[0]:2 *C 16.100 74.505 +*N top_grid_pin_21_[0]:3 *C 16.145 74.460 +*N top_grid_pin_21_[0]:4 *C 20.655 74.460 +*N top_grid_pin_21_[0]:5 *C 20.700 74.415 +*N top_grid_pin_21_[0]:6 *C 20.700 71.445 +*N top_grid_pin_21_[0]:7 *C 20.700 71.400 + +*CAP +0 ropt_mt_inst_787:X 1e-06 +1 top_grid_pin_21_[0] 3.982039e-05 +2 top_grid_pin_21_[0]:2 3.982039e-05 +3 top_grid_pin_21_[0]:3 0.0002664201 +4 top_grid_pin_21_[0]:4 0.0002664201 +5 top_grid_pin_21_[0]:5 0.0001604063 +6 top_grid_pin_21_[0]:6 0.0001604063 +7 top_grid_pin_21_[0]:7 3.363183e-05 + +*RES +0 ropt_mt_inst_787:X top_grid_pin_21_[0]:7 0.152 +1 top_grid_pin_21_[0]:7 top_grid_pin_21_[0]:6 0.0045 +2 top_grid_pin_21_[0]:6 top_grid_pin_21_[0]:5 0.002651786 +3 top_grid_pin_21_[0]:4 top_grid_pin_21_[0]:3 0.004026786 +4 top_grid_pin_21_[0]:5 top_grid_pin_21_[0]:4 0.0045 +5 top_grid_pin_21_[0]:3 top_grid_pin_21_[0]:2 0.0045 +6 top_grid_pin_21_[0]:2 top_grid_pin_21_[0] 0.0003258929 + +*END + +*D_NET ropt_net_161 0.001298209 //LENGTH 10.240 LUMPCC 0.000282435 DR + +*CONN +*I BUFT_P_99:X O *L 0 *C 4.600 39.780 +*I ropt_mt_inst_762:A I *L 0.001766 *C 3.220 47.600 +*N ropt_net_161:2 *C 3.258 47.600 +*N ropt_net_161:3 *C 3.635 47.600 +*N ropt_net_161:4 *C 3.680 47.555 +*N ropt_net_161:5 *C 3.680 40.165 +*N ropt_net_161:6 *C 3.725 40.120 +*N ropt_net_161:7 *C 4.600 40.120 +*N ropt_net_161:8 *C 4.600 39.780 + +*CAP +0 BUFT_P_99:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_161:2 4.14466e-05 +3 ropt_net_161:3 4.14466e-05 +4 ropt_net_161:4 0.0003498784 +5 ropt_net_161:5 0.0003498784 +6 ropt_net_161:6 7.157095e-05 +7 ropt_net_161:7 0.0001005091 +8 ropt_net_161:8 5.904402e-05 +9 ropt_net_161:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001412175 +10 ropt_net_161:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001412175 + +*RES +0 BUFT_P_99:X ropt_net_161:8 0.152 +1 ropt_net_161:8 ropt_net_161:7 0.0003035715 +2 ropt_net_161:6 ropt_net_161:5 0.0045 +3 ropt_net_161:5 ropt_net_161:4 0.006598214 +4 ropt_net_161:3 ropt_net_161:2 0.0003370536 +5 ropt_net_161:4 ropt_net_161:3 0.0045 +6 ropt_net_161:2 ropt_mt_inst_762:A 0.152 +7 ropt_net_161:7 ropt_net_161:6 0.00078125 + +*END + +*D_NET ropt_net_137 0.0001660204 //LENGTH 1.670 LUMPCC 0 DR + +*CONN +*I BUFT_P_113:X O *L 0 *C 87.400 72.080 +*I ropt_mt_inst_734:A I *L 0.001766 *C 88.780 72.080 +*N ropt_net_137:2 *C 88.743 72.080 +*N ropt_net_137:3 *C 87.438 72.080 + +*CAP +0 BUFT_P_113:X 1e-06 +1 ropt_mt_inst_734:A 1e-06 +2 ropt_net_137:2 8.20102e-05 +3 ropt_net_137:3 8.20102e-05 + +*RES +0 BUFT_P_113:X ropt_net_137:3 0.152 +1 ropt_net_137:3 ropt_net_137:2 0.001165179 +2 ropt_net_137:2 ropt_mt_inst_734:A 0.152 + +*END + +*D_NET chanx_left_in[12] 0.02301918 //LENGTH 165.025 LUMPCC 0.007456927 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 14.960 +*I mux_bottom_ipin_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 14.435 31.620 +*I BUFT_P_113:A I *L 0.001776 *C 85.100 72.080 +*I mux_bottom_ipin_12\/mux_l2_in_1_:A0 I *L 0.001631 *C 75.615 17.340 +*N chanx_left_in[12]:4 *C 75.578 17.340 +*N chanx_left_in[12]:5 *C 74.105 17.340 +*N chanx_left_in[12]:6 *C 74.060 17.385 +*N chanx_left_in[12]:7 *C 74.060 29.183 +*N chanx_left_in[12]:8 *C 74.053 29.240 +*N chanx_left_in[12]:9 *C 72.700 29.240 +*N chanx_left_in[12]:10 *C 72.680 29.248 +*N chanx_left_in[12]:11 *C 72.680 30.600 +*N chanx_left_in[12]:12 *C 71.308 30.600 +*N chanx_left_in[12]:13 *C 85.138 72.080 +*N chanx_left_in[12]:14 *C 85.515 72.080 +*N chanx_left_in[12]:15 *C 85.560 72.035 +*N chanx_left_in[12]:16 *C 85.560 67.377 +*N chanx_left_in[12]:17 *C 85.553 67.320 +*N chanx_left_in[12]:18 *C 71.308 67.320 +*N chanx_left_in[12]:19 *C 71.300 67.263 +*N chanx_left_in[12]:20 *C 71.300 30.658 +*N chanx_left_in[12]:21 *C 71.293 30.600 +*N chanx_left_in[12]:22 *C 64.260 30.600 +*N chanx_left_in[12]:23 *C 14.435 31.620 +*N chanx_left_in[12]:24 *C 14.260 31.620 +*N chanx_left_in[12]:25 *C 14.260 31.575 +*N chanx_left_in[12]:26 *C 14.260 30.658 +*N chanx_left_in[12]:27 *C 14.260 30.600 +*N chanx_left_in[12]:28 *C 6.460 30.600 +*N chanx_left_in[12]:29 *C 6.440 30.593 +*N chanx_left_in[12]:30 *C 6.440 14.968 +*N chanx_left_in[12]:31 *C 6.420 14.960 + +*CAP +0 chanx_left_in[12] 0.0003960349 +1 mux_bottom_ipin_8\/mux_l2_in_1_:A0 1e-06 +2 BUFT_P_113:A 1e-06 +3 mux_bottom_ipin_12\/mux_l2_in_1_:A0 1e-06 +4 chanx_left_in[12]:4 0.0001566129 +5 chanx_left_in[12]:5 0.0001566129 +6 chanx_left_in[12]:6 0.0006220326 +7 chanx_left_in[12]:7 0.0006220326 +8 chanx_left_in[12]:8 8.769189e-05 +9 chanx_left_in[12]:9 8.769189e-05 +10 chanx_left_in[12]:10 0.0001118661 +11 chanx_left_in[12]:11 0.0001851653 +12 chanx_left_in[12]:12 7.32992e-05 +13 chanx_left_in[12]:13 3.720057e-05 +14 chanx_left_in[12]:14 3.720057e-05 +15 chanx_left_in[12]:15 0.0002392449 +16 chanx_left_in[12]:16 0.0002392449 +17 chanx_left_in[12]:17 0.0004223723 +18 chanx_left_in[12]:18 0.0004223723 +19 chanx_left_in[12]:19 0.001872354 +20 chanx_left_in[12]:20 0.001872354 +21 chanx_left_in[12]:21 0.0002049074 +22 chanx_left_in[12]:22 0.002288435 +23 chanx_left_in[12]:23 5.377103e-05 +24 chanx_left_in[12]:24 5.808208e-05 +25 chanx_left_in[12]:25 7.808128e-05 +26 chanx_left_in[12]:26 7.808128e-05 +27 chanx_left_in[12]:27 0.002602177 +28 chanx_left_in[12]:28 0.0005186485 +29 chanx_left_in[12]:29 0.0008198242 +30 chanx_left_in[12]:30 0.0008198242 +31 chanx_left_in[12]:31 0.0003960349 +32 chanx_left_in[12]:21 chanx_left_in[0]:37 8.099332e-05 +33 chanx_left_in[12]:12 chanx_left_in[0]:38 1.233308e-05 +34 chanx_left_in[12]:9 chanx_left_in[0]:37 5.791068e-05 +35 chanx_left_in[12]:9 chanx_left_in[0]:38 3.469304e-05 +36 chanx_left_in[12]:7 chanx_left_in[0]:35 3.701107e-06 +37 chanx_left_in[12]:8 chanx_left_in[0]:33 5.791068e-05 +38 chanx_left_in[12]:8 chanx_left_in[0]:37 3.469304e-05 +39 chanx_left_in[12]:6 chanx_left_in[0]:36 3.701107e-06 +40 chanx_left_in[12]:27 chanx_left_in[0]:38 0.0001094526 +41 chanx_left_in[12]:27 chanx_left_in[0]:58 3.162681e-05 +42 chanx_left_in[12]:28 chanx_left_in[0]:59 3.162681e-05 +43 chanx_left_in[12]:11 chanx_left_in[0]:37 1.233308e-05 +44 chanx_left_in[12]:22 chanx_left_in[0]:37 0.0001094526 +45 chanx_left_in[12]:22 chanx_left_in[0]:38 8.099332e-05 +46 chanx_left_in[12]:18 chanx_left_in[17]:16 0.0003436799 +47 chanx_left_in[12]:17 chanx_left_in[17]:15 0.0003436799 +48 chanx_left_in[12]:21 chanx_left_in[18]:29 0.0001744244 +49 chanx_left_in[12]:12 chanx_left_in[18]:30 1.451744e-05 +50 chanx_left_in[12]:9 chanx_left_in[18]:30 8.535248e-06 +51 chanx_left_in[12]:8 chanx_left_in[18]:29 8.535248e-06 +52 chanx_left_in[12]:26 chanx_left_in[18]:38 1.151411e-05 +53 chanx_left_in[12]:27 chanx_left_in[18]:37 0.0004195036 +54 chanx_left_in[12]:27 chanx_left_in[18]:36 1.726426e-05 +55 chanx_left_in[12]:27 chanx_left_in[18]:30 0.000130053 +56 chanx_left_in[12]:27 chanx_left_in[18]:40 7.46178e-07 +57 chanx_left_in[12]:27 chanx_left_in[18]:42 1.302461e-06 +58 chanx_left_in[12]:25 chanx_left_in[18]:7 1.151411e-05 +59 chanx_left_in[12]:28 chanx_left_in[18] 1.302461e-06 +60 chanx_left_in[12]:28 chanx_left_in[18]:37 1.726426e-05 +61 chanx_left_in[12]:28 chanx_left_in[18]:41 7.46178e-07 +62 chanx_left_in[12]:29 chanx_left_in[18]:41 6.903501e-06 +63 chanx_left_in[12]:30 chanx_left_in[18]:42 6.903501e-06 +64 chanx_left_in[12]:11 chanx_left_in[18]:29 1.451744e-05 +65 chanx_left_in[12]:22 chanx_left_in[18]:36 0.0004195036 +66 chanx_left_in[12]:22 chanx_left_in[18]:30 0.0001744244 +67 chanx_left_in[12]:22 chanx_left_in[18]:29 0.000130053 +68 chanx_left_in[12]:20 chanx_right_in[11]:33 9.654907e-05 +69 chanx_left_in[12]:20 chanx_right_in[11]:6 6.56921e-05 +70 chanx_left_in[12]:19 chanx_right_in[11]:33 6.56921e-05 +71 chanx_left_in[12]:19 chanx_right_in[11]:34 9.654907e-05 +72 chanx_left_in[12]:18 chanx_right_in[11]:35 0.0002082478 +73 chanx_left_in[12]:17 chanx_right_in[11] 0.0002082478 +74 chanx_left_in[12]:20 prog_clk[0]:251 1.574219e-06 +75 chanx_left_in[12]:20 prog_clk[0]:106 2.268103e-06 +76 chanx_left_in[12]:20 prog_clk[0]:235 4.64312e-07 +77 chanx_left_in[12]:20 prog_clk[0]:83 3.11381e-05 +78 chanx_left_in[12]:20 prog_clk[0]:73 7.039464e-06 +79 chanx_left_in[12]:21 prog_clk[0]:83 5.005284e-06 +80 chanx_left_in[12]:19 prog_clk[0]:79 3.11381e-05 +81 chanx_left_in[12]:19 prog_clk[0]:72 7.039464e-06 +82 chanx_left_in[12]:19 prog_clk[0]:234 4.64312e-07 +83 chanx_left_in[12]:19 prog_clk[0]:84 2.268103e-06 +84 chanx_left_in[12]:19 prog_clk[0]:247 1.574219e-06 +85 chanx_left_in[12]:16 prog_clk[0]:220 4.17916e-06 +86 chanx_left_in[12]:15 prog_clk[0]:217 4.17916e-06 +87 chanx_left_in[12]:27 prog_clk[0]:299 0.0003094592 +88 chanx_left_in[12]:27 prog_clk[0]:298 9.844783e-05 +89 chanx_left_in[12]:27 prog_clk[0]:279 0.0006700828 +90 chanx_left_in[12]:27 prog_clk[0]:287 0.000436687 +91 chanx_left_in[12]:27 prog_clk[0]:278 0.0002150278 +92 chanx_left_in[12]:22 prog_clk[0]:282 0.000436687 +93 chanx_left_in[12]:22 prog_clk[0]:298 0.0003094592 +94 chanx_left_in[12]:22 prog_clk[0]:274 0.0002150278 +95 chanx_left_in[12]:22 prog_clk[0]:287 9.844783e-05 +96 chanx_left_in[12]:22 prog_clk[0]:278 0.0006700828 +97 chanx_left_in[12]:22 prog_clk[0]:84 5.005284e-06 +98 chanx_left_in[12]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.203583e-05 +99 chanx_left_in[12]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.203583e-05 +100 chanx_left_in[12] ropt_net_165:10 5.682662e-06 +101 chanx_left_in[12]:29 ropt_net_165:8 5.972841e-05 +102 chanx_left_in[12]:31 ropt_net_165:2 5.682662e-06 +103 chanx_left_in[12]:30 ropt_net_165:9 5.972841e-05 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:31 0.0008131 +1 chanx_left_in[12]:20 chanx_left_in[12]:19 0.03268304 +2 chanx_left_in[12]:21 chanx_left_in[12]:20 0.00341 +3 chanx_left_in[12]:21 chanx_left_in[12]:12 0.00341 +4 chanx_left_in[12]:19 chanx_left_in[12]:18 0.00341 +5 chanx_left_in[12]:18 chanx_left_in[12]:17 0.002231717 +6 chanx_left_in[12]:16 chanx_left_in[12]:15 0.004158482 +7 chanx_left_in[12]:17 chanx_left_in[12]:16 0.00341 +8 chanx_left_in[12]:14 chanx_left_in[12]:13 0.0003370536 +9 chanx_left_in[12]:15 chanx_left_in[12]:14 0.0045 +10 chanx_left_in[12]:13 BUFT_P_113:A 0.152 +11 chanx_left_in[12]:12 chanx_left_in[12]:11 0.000215025 +12 chanx_left_in[12]:9 chanx_left_in[12]:8 0.0002118916 +13 chanx_left_in[12]:10 chanx_left_in[12]:9 0.00341 +14 chanx_left_in[12]:7 chanx_left_in[12]:6 0.01053348 +15 chanx_left_in[12]:8 chanx_left_in[12]:7 0.00341 +16 chanx_left_in[12]:5 chanx_left_in[12]:4 0.001314732 +17 chanx_left_in[12]:6 chanx_left_in[12]:5 0.0045 +18 chanx_left_in[12]:4 mux_bottom_ipin_12\/mux_l2_in_1_:A0 0.152 +19 chanx_left_in[12]:26 chanx_left_in[12]:25 0.0008191965 +20 chanx_left_in[12]:27 chanx_left_in[12]:26 0.00341 +21 chanx_left_in[12]:27 chanx_left_in[12]:22 0.007833333 +22 chanx_left_in[12]:24 chanx_left_in[12]:23 9.510871e-05 +23 chanx_left_in[12]:25 chanx_left_in[12]:24 0.0045 +24 chanx_left_in[12]:23 mux_bottom_ipin_8\/mux_l2_in_1_:A0 0.152 +25 chanx_left_in[12]:28 chanx_left_in[12]:27 0.001222 +26 chanx_left_in[12]:29 chanx_left_in[12]:28 0.00341 +27 chanx_left_in[12]:31 chanx_left_in[12]:30 0.00341 +28 chanx_left_in[12]:30 chanx_left_in[12]:29 0.002447917 +29 chanx_left_in[12]:11 chanx_left_in[12]:10 0.0002118916 +30 chanx_left_in[12]:22 chanx_left_in[12]:21 0.001101758 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[2] 0.003152772 //LENGTH 22.945 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 65.625 42.160 +*I mux_bottom_ipin_5\/mux_l3_in_0_:S I *L 0.00357 *C 53.000 46.920 +*I mux_bottom_ipin_5\/mux_l3_in_1_:S I *L 0.00357 *C 49.780 44.880 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 60.895 44.540 +*N mux_tree_tapbuf_size10_3_sram[2]:4 *C 60.922 44.518 +*N mux_tree_tapbuf_size10_3_sram[2]:5 *C 61.180 44.505 +*N mux_tree_tapbuf_size10_3_sram[2]:6 *C 49.818 44.880 +*N mux_tree_tapbuf_size10_3_sram[2]:7 *C 52.900 46.920 +*N mux_tree_tapbuf_size10_3_sram[2]:8 *C 52.900 46.875 +*N mux_tree_tapbuf_size10_3_sram[2]:9 *C 52.900 44.925 +*N mux_tree_tapbuf_size10_3_sram[2]:10 *C 52.900 44.850 +*N mux_tree_tapbuf_size10_3_sram[2]:11 *C 52.900 44.200 +*N mux_tree_tapbuf_size10_3_sram[2]:12 *C 61.180 44.200 +*N mux_tree_tapbuf_size10_3_sram[2]:13 *C 65.275 44.200 +*N mux_tree_tapbuf_size10_3_sram[2]:14 *C 65.320 44.155 +*N mux_tree_tapbuf_size10_3_sram[2]:15 *C 65.320 42.205 +*N mux_tree_tapbuf_size10_3_sram[2]:16 *C 65.320 42.160 +*N mux_tree_tapbuf_size10_3_sram[2]:17 *C 65.625 42.160 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_5\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_3_sram[2]:4 5.195552e-05 +5 mux_tree_tapbuf_size10_3_sram[2]:5 7.880916e-05 +6 mux_tree_tapbuf_size10_3_sram[2]:6 0.0002129484 +7 mux_tree_tapbuf_size10_3_sram[2]:7 3.685841e-05 +8 mux_tree_tapbuf_size10_3_sram[2]:8 0.0001332628 +9 mux_tree_tapbuf_size10_3_sram[2]:9 0.0001332628 +10 mux_tree_tapbuf_size10_3_sram[2]:10 0.0002649665 +11 mux_tree_tapbuf_size10_3_sram[2]:11 0.0006499869 +12 mux_tree_tapbuf_size10_3_sram[2]:12 0.0009178458 +13 mux_tree_tapbuf_size10_3_sram[2]:13 0.0002930233 +14 mux_tree_tapbuf_size10_3_sram[2]:14 0.0001298156 +15 mux_tree_tapbuf_size10_3_sram[2]:15 0.0001298156 +16 mux_tree_tapbuf_size10_3_sram[2]:16 5.858777e-05 +17 mux_tree_tapbuf_size10_3_sram[2]:17 5.763285e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_3_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_3_sram[2]:10 mux_tree_tapbuf_size10_3_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size10_3_sram[2]:10 mux_tree_tapbuf_size10_3_sram[2]:6 0.002752233 +3 mux_tree_tapbuf_size10_3_sram[2]:9 mux_tree_tapbuf_size10_3_sram[2]:8 0.001741072 +4 mux_tree_tapbuf_size10_3_sram[2]:7 mux_bottom_ipin_5\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_3_sram[2]:8 mux_tree_tapbuf_size10_3_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size10_3_sram[2]:4 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size10_3_sram[2]:6 mux_bottom_ipin_5\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_3_sram[2]:13 mux_tree_tapbuf_size10_3_sram[2]:12 0.00365625 +9 mux_tree_tapbuf_size10_3_sram[2]:14 mux_tree_tapbuf_size10_3_sram[2]:13 0.0045 +10 mux_tree_tapbuf_size10_3_sram[2]:16 mux_tree_tapbuf_size10_3_sram[2]:15 0.0045 +11 mux_tree_tapbuf_size10_3_sram[2]:15 mux_tree_tapbuf_size10_3_sram[2]:14 0.001741072 +12 mux_tree_tapbuf_size10_3_sram[2]:17 mux_tree_tapbuf_size10_3_sram[2]:16 0.0001657609 +13 mux_tree_tapbuf_size10_3_sram[2]:11 mux_tree_tapbuf_size10_3_sram[2]:10 0.0005803573 +14 mux_tree_tapbuf_size10_3_sram[2]:12 mux_tree_tapbuf_size10_3_sram[2]:11 0.007392858 +15 mux_tree_tapbuf_size10_3_sram[2]:12 mux_tree_tapbuf_size10_3_sram[2]:5 0.0002723215 +16 mux_tree_tapbuf_size10_3_sram[2]:5 mux_tree_tapbuf_size10_3_sram[2]:4 0.0001739865 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[2] 0.002386215 //LENGTH 18.725 LUMPCC 0.0004905601 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 80.805 9.860 +*I mux_bottom_ipin_12\/mux_l3_in_1_:S I *L 0.00357 *C 83.160 12.535 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 82.975 17.340 +*I mux_bottom_ipin_12\/mux_l3_in_0_:S I *L 0.00357 *C 79.020 20.060 +*N mux_tree_tapbuf_size10_6_sram[2]:4 *C 79.058 20.060 +*N mux_tree_tapbuf_size10_6_sram[2]:5 *C 83.215 20.060 +*N mux_tree_tapbuf_size10_6_sram[2]:6 *C 83.260 20.015 +*N mux_tree_tapbuf_size10_6_sram[2]:7 *C 82.975 17.340 +*N mux_tree_tapbuf_size10_6_sram[2]:8 *C 83.260 17.340 +*N mux_tree_tapbuf_size10_6_sram[2]:9 *C 83.260 17.340 +*N mux_tree_tapbuf_size10_6_sram[2]:10 *C 83.260 12.965 +*N mux_tree_tapbuf_size10_6_sram[2]:11 *C 83.260 12.920 +*N mux_tree_tapbuf_size10_6_sram[2]:12 *C 83.160 12.610 +*N mux_tree_tapbuf_size10_6_sram[2]:13 *C 83.160 12.535 +*N mux_tree_tapbuf_size10_6_sram[2]:14 *C 83.103 12.240 +*N mux_tree_tapbuf_size10_6_sram[2]:15 *C 81.005 12.240 +*N mux_tree_tapbuf_size10_6_sram[2]:16 *C 80.960 12.195 +*N mux_tree_tapbuf_size10_6_sram[2]:17 *C 80.960 9.905 +*N mux_tree_tapbuf_size10_6_sram[2]:18 *C 80.960 9.860 +*N mux_tree_tapbuf_size10_6_sram[2]:19 *C 80.805 9.860 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_12\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_6_sram[2]:4 0.0002119809 +5 mux_tree_tapbuf_size10_6_sram[2]:5 0.0002119809 +6 mux_tree_tapbuf_size10_6_sram[2]:6 0.0001392536 +7 mux_tree_tapbuf_size10_6_sram[2]:7 5.434928e-05 +8 mux_tree_tapbuf_size10_6_sram[2]:8 5.885059e-05 +9 mux_tree_tapbuf_size10_6_sram[2]:9 0.0003560847 +10 mux_tree_tapbuf_size10_6_sram[2]:10 0.000184445 +11 mux_tree_tapbuf_size10_6_sram[2]:11 5.216417e-05 +12 mux_tree_tapbuf_size10_6_sram[2]:12 1.294425e-05 +13 mux_tree_tapbuf_size10_6_sram[2]:13 8.006628e-05 +14 mux_tree_tapbuf_size10_6_sram[2]:14 9.390747e-05 +15 mux_tree_tapbuf_size10_6_sram[2]:15 7.465572e-05 +16 mux_tree_tapbuf_size10_6_sram[2]:16 0.0001354463 +17 mux_tree_tapbuf_size10_6_sram[2]:17 0.0001354463 +18 mux_tree_tapbuf_size10_6_sram[2]:18 4.704182e-05 +19 mux_tree_tapbuf_size10_6_sram[2]:19 4.303701e-05 +20 mux_tree_tapbuf_size10_6_sram[2]:9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.001689e-06 +21 mux_tree_tapbuf_size10_6_sram[2]:10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.001689e-06 +22 mux_tree_tapbuf_size10_6_sram[2]:15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.957441e-05 +23 mux_tree_tapbuf_size10_6_sram[2]:14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.957441e-05 +24 mux_tree_tapbuf_size10_6_sram[2]:15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.238051e-05 +25 mux_tree_tapbuf_size10_6_sram[2]:14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.238051e-05 +26 mux_tree_tapbuf_size10_6_sram[2]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.021723e-05 +27 mux_tree_tapbuf_size10_6_sram[2]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.021723e-05 +28 mux_tree_tapbuf_size10_6_sram[2]:9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.376182e-05 +29 mux_tree_tapbuf_size10_6_sram[2]:9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.141259e-05 +30 mux_tree_tapbuf_size10_6_sram[2]:10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.376182e-05 +31 mux_tree_tapbuf_size10_6_sram[2]:16 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 9.318325e-07 +32 mux_tree_tapbuf_size10_6_sram[2]:17 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 9.318325e-07 +33 mux_tree_tapbuf_size10_6_sram[2]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.141259e-05 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_6_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_6_sram[2]:13 mux_bottom_ipin_12\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_6_sram[2]:13 mux_tree_tapbuf_size10_6_sram[2]:12 4.360465e-05 +3 mux_tree_tapbuf_size10_6_sram[2]:13 mux_tree_tapbuf_size10_6_sram[2]:11 0.00034375 +4 mux_tree_tapbuf_size10_6_sram[2]:8 mux_tree_tapbuf_size10_6_sram[2]:7 0.0001548913 +5 mux_tree_tapbuf_size10_6_sram[2]:9 mux_tree_tapbuf_size10_6_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size10_6_sram[2]:9 mux_tree_tapbuf_size10_6_sram[2]:6 0.002388393 +7 mux_tree_tapbuf_size10_6_sram[2]:7 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_6_sram[2]:11 mux_tree_tapbuf_size10_6_sram[2]:10 0.0045 +9 mux_tree_tapbuf_size10_6_sram[2]:10 mux_tree_tapbuf_size10_6_sram[2]:9 0.00390625 +10 mux_tree_tapbuf_size10_6_sram[2]:15 mux_tree_tapbuf_size10_6_sram[2]:14 0.001872768 +11 mux_tree_tapbuf_size10_6_sram[2]:16 mux_tree_tapbuf_size10_6_sram[2]:15 0.0045 +12 mux_tree_tapbuf_size10_6_sram[2]:18 mux_tree_tapbuf_size10_6_sram[2]:17 0.0045 +13 mux_tree_tapbuf_size10_6_sram[2]:17 mux_tree_tapbuf_size10_6_sram[2]:16 0.002044643 +14 mux_tree_tapbuf_size10_6_sram[2]:19 mux_tree_tapbuf_size10_6_sram[2]:18 8.423914e-05 +15 mux_tree_tapbuf_size10_6_sram[2]:5 mux_tree_tapbuf_size10_6_sram[2]:4 0.003712054 +16 mux_tree_tapbuf_size10_6_sram[2]:6 mux_tree_tapbuf_size10_6_sram[2]:5 0.0045 +17 mux_tree_tapbuf_size10_6_sram[2]:4 mux_bottom_ipin_12\/mux_l3_in_0_:S 0.152 +18 mux_tree_tapbuf_size10_6_sram[2]:14 mux_tree_tapbuf_size10_6_sram[2]:13 0.0001715116 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[3] 0.001615534 //LENGTH 13.030 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 32.505 20.400 +*I mux_bottom_ipin_2\/mux_l4_in_0_:S I *L 0.00357 *C 31.380 23.415 +*I mem_bottom_ipin_2\/FTB_9__48:A I *L 0.001746 *C 33.120 28.560 +*N mux_tree_tapbuf_size8_0_sram[3]:3 *C 33.120 28.560 +*N mux_tree_tapbuf_size8_0_sram[3]:4 *C 33.120 28.515 +*N mux_tree_tapbuf_size8_0_sram[3]:5 *C 33.120 23.165 +*N mux_tree_tapbuf_size8_0_sram[3]:6 *C 33.075 23.120 +*N mux_tree_tapbuf_size8_0_sram[3]:7 *C 31.380 23.415 +*N mux_tree_tapbuf_size8_0_sram[3]:8 *C 31.438 23.120 +*N mux_tree_tapbuf_size8_0_sram[3]:9 *C 31.280 23.075 +*N mux_tree_tapbuf_size8_0_sram[3]:10 *C 31.280 20.445 +*N mux_tree_tapbuf_size8_0_sram[3]:11 *C 31.325 20.400 +*N mux_tree_tapbuf_size8_0_sram[3]:12 *C 32.468 20.400 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_2\/FTB_9__48:A 1e-06 +3 mux_tree_tapbuf_size8_0_sram[3]:3 3.011068e-05 +4 mux_tree_tapbuf_size8_0_sram[3]:4 0.0003162702 +5 mux_tree_tapbuf_size8_0_sram[3]:5 0.0003162702 +6 mux_tree_tapbuf_size8_0_sram[3]:6 0.0001330778 +7 mux_tree_tapbuf_size8_0_sram[3]:7 5.814031e-05 +8 mux_tree_tapbuf_size8_0_sram[3]:8 0.0001644736 +9 mux_tree_tapbuf_size8_0_sram[3]:9 0.0001754724 +10 mux_tree_tapbuf_size8_0_sram[3]:10 0.0001754724 +11 mux_tree_tapbuf_size8_0_sram[3]:11 0.0001216232 +12 mux_tree_tapbuf_size8_0_sram[3]:12 0.0001216232 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_0_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_0_sram[3]:7 mux_bottom_ipin_2\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[3]:6 mux_tree_tapbuf_size8_0_sram[3]:5 0.0045 +3 mux_tree_tapbuf_size8_0_sram[3]:5 mux_tree_tapbuf_size8_0_sram[3]:4 0.004776786 +4 mux_tree_tapbuf_size8_0_sram[3]:3 mem_bottom_ipin_2\/FTB_9__48:A 0.152 +5 mux_tree_tapbuf_size8_0_sram[3]:4 mux_tree_tapbuf_size8_0_sram[3]:3 0.0045 +6 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:7 0.0001271552 +7 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:6 0.001462053 +8 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:8 0.0045 +9 mux_tree_tapbuf_size8_0_sram[3]:11 mux_tree_tapbuf_size8_0_sram[3]:10 0.0045 +10 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:9 0.002348214 +11 mux_tree_tapbuf_size8_0_sram[3]:12 mux_tree_tapbuf_size8_0_sram[3]:11 0.001020089 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[0] 0.002579812 //LENGTH 18.870 LUMPCC 0.0003187752 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 50.445 53.380 +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 40.195 55.420 +*I mux_bottom_ipin_7\/mux_l1_in_0_:S I *L 0.00357 *C 39.200 50.320 +*N mux_tree_tapbuf_size8_3_sram[0]:3 *C 39.238 50.320 +*N mux_tree_tapbuf_size8_3_sram[0]:4 *C 40.895 50.320 +*N mux_tree_tapbuf_size8_3_sram[0]:5 *C 40.940 50.365 +*N mux_tree_tapbuf_size8_3_sram[0]:6 *C 40.195 55.420 +*N mux_tree_tapbuf_size8_3_sram[0]:7 *C 40.480 55.420 +*N mux_tree_tapbuf_size8_3_sram[0]:8 *C 40.480 55.375 +*N mux_tree_tapbuf_size8_3_sram[0]:9 *C 40.480 53.720 +*N mux_tree_tapbuf_size8_3_sram[0]:10 *C 40.940 53.675 +*N mux_tree_tapbuf_size8_3_sram[0]:11 *C 40.985 53.720 +*N mux_tree_tapbuf_size8_3_sram[0]:12 *C 50.140 53.720 +*N mux_tree_tapbuf_size8_3_sram[0]:13 *C 50.140 53.415 +*N mux_tree_tapbuf_size8_3_sram[0]:14 *C 50.418 53.403 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_7\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_3_sram[0]:3 0.0001385093 +4 mux_tree_tapbuf_size8_3_sram[0]:4 0.0001385093 +5 mux_tree_tapbuf_size8_3_sram[0]:5 0.0001892725 +6 mux_tree_tapbuf_size8_3_sram[0]:6 5.522509e-05 +7 mux_tree_tapbuf_size8_3_sram[0]:7 5.7775e-05 +8 mux_tree_tapbuf_size8_3_sram[0]:8 0.0001191617 +9 mux_tree_tapbuf_size8_3_sram[0]:9 0.0001513523 +10 mux_tree_tapbuf_size8_3_sram[0]:10 0.0002214631 +11 mux_tree_tapbuf_size8_3_sram[0]:11 0.0005398466 +12 mux_tree_tapbuf_size8_3_sram[0]:12 0.0005651726 +13 mux_tree_tapbuf_size8_3_sram[0]:13 5.353773e-05 +14 mux_tree_tapbuf_size8_3_sram[0]:14 2.821167e-05 +15 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0001593876 +16 mux_tree_tapbuf_size8_3_sram[0]:12 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0001593876 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_3_sram[0]:14 0.152 +1 mux_tree_tapbuf_size8_3_sram[0]:14 mux_tree_tapbuf_size8_3_sram[0]:13 0.0001875 +2 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_3_sram[0]:10 0.0045 +3 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:9 0.0004107143 +4 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:5 0.002955357 +5 mux_tree_tapbuf_size8_3_sram[0]:7 mux_tree_tapbuf_size8_3_sram[0]:6 0.0001548913 +6 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[0]:7 0.0045 +7 mux_tree_tapbuf_size8_3_sram[0]:6 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_3_sram[0]:4 mux_tree_tapbuf_size8_3_sram[0]:3 0.001479911 +9 mux_tree_tapbuf_size8_3_sram[0]:5 mux_tree_tapbuf_size8_3_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size8_3_sram[0]:3 mux_bottom_ipin_7\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size8_3_sram[0]:12 mux_tree_tapbuf_size8_3_sram[0]:11 0.008174107 +12 mux_tree_tapbuf_size8_3_sram[0]:13 mux_tree_tapbuf_size8_3_sram[0]:12 0.0002723215 +13 mux_tree_tapbuf_size8_3_sram[0]:9 mux_tree_tapbuf_size8_3_sram[0]:8 0.001477679 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[3] 0.004657295 //LENGTH 30.920 LUMPCC 0.001620625 DR + +*CONN +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 33.885 36.720 +*I mux_bottom_ipin_11\/mux_l4_in_0_:S I *L 0.00357 *C 17.580 39.440 +*I mem_bottom_ipin_11\/FTB_14__53:A I *L 0.001746 *C 34.500 28.560 +*N mux_tree_tapbuf_size8_5_sram[3]:3 *C 34.462 28.560 +*N mux_tree_tapbuf_size8_5_sram[3]:4 *C 33.625 28.560 +*N mux_tree_tapbuf_size8_5_sram[3]:5 *C 33.580 28.605 +*N mux_tree_tapbuf_size8_5_sram[3]:6 *C 33.580 35.360 +*N mux_tree_tapbuf_size8_5_sram[3]:7 *C 34.040 35.360 +*N mux_tree_tapbuf_size8_5_sram[3]:8 *C 17.617 39.440 +*N mux_tree_tapbuf_size8_5_sram[3]:9 *C 20.655 39.440 +*N mux_tree_tapbuf_size8_5_sram[3]:10 *C 20.700 39.395 +*N mux_tree_tapbuf_size8_5_sram[3]:11 *C 20.700 36.778 +*N mux_tree_tapbuf_size8_5_sram[3]:12 *C 20.707 36.720 +*N mux_tree_tapbuf_size8_5_sram[3]:13 *C 34.032 36.720 +*N mux_tree_tapbuf_size8_5_sram[3]:14 *C 34.040 36.720 +*N mux_tree_tapbuf_size8_5_sram[3]:15 *C 34.040 36.720 +*N mux_tree_tapbuf_size8_5_sram[3]:16 *C 33.885 36.720 + +*CAP +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_11\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_11\/FTB_14__53:A 1e-06 +3 mux_tree_tapbuf_size8_5_sram[3]:3 6.372767e-05 +4 mux_tree_tapbuf_size8_5_sram[3]:4 6.372767e-05 +5 mux_tree_tapbuf_size8_5_sram[3]:5 0.0003708717 +6 mux_tree_tapbuf_size8_5_sram[3]:6 0.0004006553 +7 mux_tree_tapbuf_size8_5_sram[3]:7 0.0001160622 +8 mux_tree_tapbuf_size8_5_sram[3]:8 0.0001867211 +9 mux_tree_tapbuf_size8_5_sram[3]:9 0.0001867211 +10 mux_tree_tapbuf_size8_5_sram[3]:10 0.0001621112 +11 mux_tree_tapbuf_size8_5_sram[3]:11 0.0001621112 +12 mux_tree_tapbuf_size8_5_sram[3]:12 0.0005467393 +13 mux_tree_tapbuf_size8_5_sram[3]:13 0.0005467393 +14 mux_tree_tapbuf_size8_5_sram[3]:14 0.0001226759 +15 mux_tree_tapbuf_size8_5_sram[3]:15 5.294953e-05 +16 mux_tree_tapbuf_size8_5_sram[3]:16 5.185716e-05 +17 mux_tree_tapbuf_size8_5_sram[3]:5 chanx_left_in[7]:16 9.937158e-06 +18 mux_tree_tapbuf_size8_5_sram[3]:5 chanx_left_in[7]:20 1.821059e-06 +19 mux_tree_tapbuf_size8_5_sram[3]:14 chanx_left_in[7]:19 4.006208e-06 +20 mux_tree_tapbuf_size8_5_sram[3]:13 chanx_left_in[7]:15 2.186807e-05 +21 mux_tree_tapbuf_size8_5_sram[3]:13 chanx_left_in[7]:21 0.0002381049 +22 mux_tree_tapbuf_size8_5_sram[3]:12 chanx_left_in[7]:16 2.186807e-05 +23 mux_tree_tapbuf_size8_5_sram[3]:12 chanx_left_in[7]:22 0.0002381049 +24 mux_tree_tapbuf_size8_5_sram[3]:6 chanx_left_in[7]:19 1.821059e-06 +25 mux_tree_tapbuf_size8_5_sram[3]:6 chanx_left_in[7]:21 9.937158e-06 +26 mux_tree_tapbuf_size8_5_sram[3]:7 chanx_left_in[7]:20 4.006208e-06 +27 mux_tree_tapbuf_size8_5_sram[3]:13 optlc_net_124:25 0.0004814526 +28 mux_tree_tapbuf_size8_5_sram[3]:12 optlc_net_124:26 0.0004814526 +29 mux_tree_tapbuf_size8_5_sram[3]:9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.312237e-05 +30 mux_tree_tapbuf_size8_5_sram[3]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.312237e-05 + +*RES +0 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_5_sram[3]:16 0.152 +1 mux_tree_tapbuf_size8_5_sram[3]:4 mux_tree_tapbuf_size8_5_sram[3]:3 0.0007477679 +2 mux_tree_tapbuf_size8_5_sram[3]:5 mux_tree_tapbuf_size8_5_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size8_5_sram[3]:3 mem_bottom_ipin_11\/FTB_14__53:A 0.152 +4 mux_tree_tapbuf_size8_5_sram[3]:15 mux_tree_tapbuf_size8_5_sram[3]:14 0.0045 +5 mux_tree_tapbuf_size8_5_sram[3]:14 mux_tree_tapbuf_size8_5_sram[3]:13 0.00341 +6 mux_tree_tapbuf_size8_5_sram[3]:14 mux_tree_tapbuf_size8_5_sram[3]:7 0.001214286 +7 mux_tree_tapbuf_size8_5_sram[3]:16 mux_tree_tapbuf_size8_5_sram[3]:15 8.423915e-05 +8 mux_tree_tapbuf_size8_5_sram[3]:13 mux_tree_tapbuf_size8_5_sram[3]:12 0.002087583 +9 mux_tree_tapbuf_size8_5_sram[3]:11 mux_tree_tapbuf_size8_5_sram[3]:10 0.002337054 +10 mux_tree_tapbuf_size8_5_sram[3]:12 mux_tree_tapbuf_size8_5_sram[3]:11 0.00341 +11 mux_tree_tapbuf_size8_5_sram[3]:9 mux_tree_tapbuf_size8_5_sram[3]:8 0.002712054 +12 mux_tree_tapbuf_size8_5_sram[3]:10 mux_tree_tapbuf_size8_5_sram[3]:9 0.0045 +13 mux_tree_tapbuf_size8_5_sram[3]:8 mux_bottom_ipin_11\/mux_l4_in_0_:S 0.152 +14 mux_tree_tapbuf_size8_5_sram[3]:6 mux_tree_tapbuf_size8_5_sram[3]:5 0.006031251 +15 mux_tree_tapbuf_size8_5_sram[3]:7 mux_tree_tapbuf_size8_5_sram[3]:6 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_6_ccff_tail[0] 0.0009427404 //LENGTH 7.100 LUMPCC 0.0001363149 DR + +*CONN +*I mem_bottom_ipin_14\/FTB_15__54:X O *L 0 *C 76.585 53.380 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 75.615 58.820 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 *C 75.653 58.820 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 *C 76.315 58.820 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 *C 76.360 58.775 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 *C 76.360 53.425 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 *C 76.360 53.380 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 *C 76.585 53.380 + +*CAP +0 mem_bottom_ipin_14\/FTB_15__54:X 1e-06 +1 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 7.959742e-05 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 7.959742e-05 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.0002698007 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0002698007 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 5.330324e-05 +7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 5.232598e-05 +8 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 chanx_left_in[4]:14 6.815747e-05 +9 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 chanx_left_in[4]:15 6.815747e-05 + +*RES +0 mem_bottom_ipin_14\/FTB_15__54:X mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 0.0005915179 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0003645292 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_2_:X O *L 0 *C 64.575 18.020 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 62.005 18.020 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 62.043 18.020 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 64.538 18.020 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001812646 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001812646 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001510542 //LENGTH 10.520 LUMPCC 0.0004802804 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_0_:X O *L 0 *C 61.355 55.760 +*I mux_bottom_ipin_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 55.105 58.140 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 55.143 58.140 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 55.660 58.140 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 55.660 58.480 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 60.215 58.480 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 60.260 58.435 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.260 55.805 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 60.305 55.760 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 61.318 55.760 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.803272e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.22785e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001968108 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000172565 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001914271 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001914271 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.786021e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 9.786021e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.335894e-06 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.713826e-05 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.918451e-08 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.918451e-08 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.335894e-06 +15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.713826e-05 +16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 optlc_net_125:28 2.873436e-05 +17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_125:29 7.523274e-06 +18 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_125:31 0.0001440774 +19 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 optlc_net_125:29 3.002617e-05 +20 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_125:28 7.523274e-06 +21 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_125:30 0.0001453692 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004066965 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002348214 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000904018 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004620536 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005076926 //LENGTH 3.755 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l1_in_0_:X O *L 0 *C 53.075 55.080 +*I mux_bottom_ipin_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 53.820 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 53.783 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.405 52.700 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 53.360 52.745 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 53.360 55.035 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 53.360 55.080 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 53.075 55.080 + +*CAP +0 mux_bottom_ipin_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.935958e-05 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.935958e-05 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001442093 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001442093 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.793487e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.061998e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l1_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_5\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370536 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001595086 //LENGTH 11.830 LUMPCC 0.000236749 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l1_in_1_:X O *L 0 *C 15.925 25.160 +*I mux_bottom_ipin_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 19.195 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 19.233 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 19.735 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 19.780 31.575 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 19.780 25.205 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 19.735 25.160 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 15.963 25.160 + +*CAP +0 mux_bottom_ipin_8\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.805503e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.805503e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000305366 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000305366 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003147473 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003147473 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001183745 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001183745 + +*RES +0 mux_bottom_ipin_8\/mux_l1_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003368304 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0056875 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004486607 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_8\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0004610659 //LENGTH 3.395 LUMPCC 7.161499e-05 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l3_in_1_:X O *L 0 *C 14.435 60.860 +*I mux_bottom_ipin_9\/mux_l4_in_0_:A0 I *L 0.001631 *C 11.330 60.860 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 11.367 60.860 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 14.398 60.860 + +*CAP +0 mux_bottom_ipin_9\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001937254 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001937254 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:12 4.177759e-06 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:14 3.162973e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:13 4.177759e-06 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:15 3.162973e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l3_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_9\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002705358 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005425821 //LENGTH 4.270 LUMPCC 7.347145e-05 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l1_in_1_:X O *L 0 *C 84.815 50.660 +*I mux_bottom_ipin_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 85.735 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 85.698 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 85.145 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 85.100 53.335 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.100 50.705 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 85.100 50.660 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 84.815 50.660 + +*CAP +0 mux_bottom_ipin_13\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.051431e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.051431e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00013456 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00013456 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.166846e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.529359e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_7_sram[1]:14 9.645559e-06 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_7_sram[1]:13 9.645559e-06 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:16 2.709017e-05 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:15 2.709017e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l1_in_1_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_13\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007377844 //LENGTH 6.055 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l3_in_1_:X O *L 0 *C 38.355 44.540 +*I mux_bottom_ipin_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 36.630 47.940 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 36.668 47.940 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 37.215 47.940 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 37.260 47.895 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 37.260 44.585 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 37.305 44.540 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 38.318 44.540 + +*CAP +0 mux_bottom_ipin_3\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.690933e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.690933e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002065322 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002065322 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001044507 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001044507 + +*RES +0 mux_bottom_ipin_3\/mux_l3_in_1_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_3\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002955357 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000904018 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003485124 //LENGTH 2.425 LUMPCC 0.0001288601 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l3_in_1_:X O *L 0 *C 30.995 60.860 +*I mux_bottom_ipin_7\/mux_l4_in_0_:A0 I *L 0.001631 *C 28.860 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 28.898 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 30.958 60.860 + +*CAP +0 mux_bottom_ipin_7\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001088261 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001088261 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_3_sram[2]:12 3.262521e-05 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_3_sram[2]:16 3.180485e-05 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_3_sram[2]:11 3.262521e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_3_sram[2]:15 3.180485e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l3_in_1_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001839286 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_7\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006228055 //LENGTH 4.400 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_3_:X O *L 0 *C 22.715 34.340 +*I mux_bottom_ipin_11\/mux_l3_in_1_:A0 I *L 0.001631 *C 23.765 37.060 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 23.728 37.060 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.045 37.060 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 23.000 37.015 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 23.000 34.385 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 23.000 34.340 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 22.715 34.340 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.671784e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.671784e-05 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001682575 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001682575 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.690277e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.395206e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_3_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000609375 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006541899 //LENGTH 4.945 LUMPCC 0.0001216874 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_3_:X O *L 0 *C 69.745 60.860 +*I mux_bottom_ipin_15\/mux_l3_in_1_:A0 I *L 0.001631 *C 69.290 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 69.328 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 69.875 64.260 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 69.920 64.215 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 69.920 60.905 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 69.920 60.860 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 69.745 60.860 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.469162e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.469162e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000151196 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000151196 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.103015e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.769712e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.084368e-05 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.084368e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_3_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002955357 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_191 0.000845263 //LENGTH 7.010 LUMPCC 9.114355e-05 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 94.760 17.680 +*I ropt_mt_inst_800:A I *L 0.001766 *C 97.980 20.400 +*N ropt_net_191:2 *C 97.958 20.373 +*N ropt_net_191:3 *C 97.945 20.060 +*N ropt_net_191:4 *C 95.725 20.060 +*N ropt_net_191:5 *C 95.680 20.015 +*N ropt_net_191:6 *C 95.680 17.725 +*N ropt_net_191:7 *C 95.635 17.680 +*N ropt_net_191:8 *C 94.797 17.680 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_191:2 3.541505e-05 +3 ropt_net_191:3 0.0001700585 +4 ropt_net_191:4 0.0001346434 +5 ropt_net_191:5 0.0001421613 +6 ropt_net_191:6 0.0001421613 +7 ropt_net_191:7 6.383991e-05 +8 ropt_net_191:8 6.383991e-05 +9 ropt_net_191:4 chanx_left_in[1]:19 4.557177e-05 +10 ropt_net_191:3 chanx_left_in[1]:20 4.557177e-05 + +*RES +0 ropt_mt_inst_733:X ropt_net_191:8 0.152 +1 ropt_net_191:2 ropt_mt_inst_800:A 0.152 +2 ropt_net_191:4 ropt_net_191:3 0.001982143 +3 ropt_net_191:5 ropt_net_191:4 0.0045 +4 ropt_net_191:7 ropt_net_191:6 0.0045 +5 ropt_net_191:6 ropt_net_191:5 0.002044643 +6 ropt_net_191:8 ropt_net_191:7 0.0007477679 +7 ropt_net_191:3 ropt_net_191:2 0.0002111487 + +*END + +*D_NET ropt_net_150 0.001063616 //LENGTH 9.025 LUMPCC 0.0002168089 DR + +*CONN +*I BUFT_RR_59:X O *L 0 *C 97.060 19.720 +*I ropt_mt_inst_747:A I *L 0.001766 *C 97.980 12.240 +*N ropt_net_150:2 *C 97.943 12.240 +*N ropt_net_150:3 *C 97.105 12.240 +*N ropt_net_150:4 *C 97.060 12.285 +*N ropt_net_150:5 *C 97.060 19.675 +*N ropt_net_150:6 *C 97.060 19.720 + +*CAP +0 BUFT_RR_59:X 1e-06 +1 ropt_mt_inst_747:A 1e-06 +2 ropt_net_150:2 3.685407e-05 +3 ropt_net_150:3 3.685407e-05 +4 ropt_net_150:4 0.0003661396 +5 ropt_net_150:5 0.0003661396 +6 ropt_net_150:6 3.881988e-05 +7 ropt_net_150:5 chanx_right_out[3]:4 6.237071e-05 +8 ropt_net_150:4 chanx_right_out[3]:3 6.237071e-05 +9 ropt_net_150:3 ropt_net_188:7 4.603374e-05 +10 ropt_net_150:2 ropt_net_188:8 4.603374e-05 + +*RES +0 BUFT_RR_59:X ropt_net_150:6 0.152 +1 ropt_net_150:6 ropt_net_150:5 0.0045 +2 ropt_net_150:5 ropt_net_150:4 0.006598214 +3 ropt_net_150:3 ropt_net_150:2 0.0007477679 +4 ropt_net_150:4 ropt_net_150:3 0.0045 +5 ropt_net_150:2 ropt_mt_inst_747:A 0.152 + +*END + +*D_NET chanx_right_out[17] 0.0003770894 //LENGTH 1.985 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 101.855 28.560 +*P chanx_right_out[17] O *L 0.7423 *C 103.650 28.560 +*N chanx_right_out[17]:2 *C 102.128 28.560 +*N chanx_right_out[17]:3 *C 102.120 28.560 +*N chanx_right_out[17]:4 *C 102.120 28.560 +*N chanx_right_out[17]:5 *C 101.855 28.560 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 chanx_right_out[17] 0.0001185344 +2 chanx_right_out[17]:2 0.0001185344 +3 chanx_right_out[17]:3 3.548336e-05 +4 chanx_right_out[17]:4 4.774196e-05 +5 chanx_right_out[17]:5 5.579528e-05 + +*RES +0 ropt_mt_inst_751:X chanx_right_out[17]:5 0.152 +1 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0001440218 +2 chanx_right_out[17]:4 chanx_right_out[17]:3 0.0045 +3 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +4 chanx_right_out[17]:2 chanx_right_out[17] 0.000238525 + +*END + +*D_NET chanx_right_out[13] 0.001169112 //LENGTH 6.500 LUMPCC 8.828768e-05 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 98.900 65.960 +*P chanx_right_out[13] O *L 0.7423 *C 103.650 66.640 +*N chanx_right_out[13]:2 *C 103.040 66.640 +*N chanx_right_out[13]:3 *C 103.040 65.960 +*N chanx_right_out[13]:4 *C 100.288 65.960 +*N chanx_right_out[13]:5 *C 100.280 65.960 +*N chanx_right_out[13]:6 *C 100.235 65.960 +*N chanx_right_out[13]:7 *C 98.938 65.960 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 chanx_right_out[13] 6.624369e-05 +2 chanx_right_out[13]:2 0.0001101675 +3 chanx_right_out[13]:3 0.0003712444 +4 chanx_right_out[13]:4 0.0003273206 +5 chanx_right_out[13]:5 3.502454e-05 +6 chanx_right_out[13]:6 8.491187e-05 +7 chanx_right_out[13]:7 8.491187e-05 +8 chanx_right_out[13]:7 ropt_net_182:2 2.698345e-05 +9 chanx_right_out[13]:6 ropt_net_182:3 2.698345e-05 +10 chanx_right_out[13]:3 ropt_net_182:5 1.716038e-05 +11 chanx_right_out[13]:2 ropt_net_182:4 1.716038e-05 + +*RES +0 ropt_mt_inst_789:X chanx_right_out[13]:7 0.152 +1 chanx_right_out[13]:7 chanx_right_out[13]:6 0.001158482 +2 chanx_right_out[13]:6 chanx_right_out[13]:5 0.0045 +3 chanx_right_out[13]:5 chanx_right_out[13]:4 0.00341 +4 chanx_right_out[13]:4 chanx_right_out[13]:3 0.000431225 +5 chanx_right_out[13]:3 chanx_right_out[13]:2 0.0001065333 +6 chanx_right_out[13]:2 chanx_right_out[13] 9.556666e-05 + +*END + +*D_NET chanx_left_in[13] 0.01743549 //LENGTH 114.410 LUMPCC 0.005883589 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 58.480 +*I mux_bottom_ipin_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 17.310 55.420 +*I mux_bottom_ipin_13\/mux_l2_in_1_:A0 I *L 0.001631 *C 86.770 58.820 +*I FTB_14__13:A I *L 0.001776 *C 93.380 61.200 +*N chanx_left_in[13]:4 *C 93.418 61.200 +*N chanx_left_in[13]:5 *C 96.095 61.200 +*N chanx_left_in[13]:6 *C 96.140 61.155 +*N chanx_left_in[13]:7 *C 96.140 57.858 +*N chanx_left_in[13]:8 *C 96.133 57.800 +*N chanx_left_in[13]:9 *C 86.770 58.820 +*N chanx_left_in[13]:10 *C 86.480 58.820 +*N chanx_left_in[13]:11 *C 86.480 58.775 +*N chanx_left_in[13]:12 *C 86.480 57.858 +*N chanx_left_in[13]:13 *C 86.480 57.800 +*N chanx_left_in[13]:14 *C 36.800 57.800 +*N chanx_left_in[13]:15 *C 36.800 57.120 +*N chanx_left_in[13]:16 *C 16.560 57.120 +*N chanx_left_in[13]:17 *C 16.560 57.800 +*N chanx_left_in[13]:18 *C 17.273 55.420 +*N chanx_left_in[13]:19 *C 13.385 55.420 +*N chanx_left_in[13]:20 *C 13.340 55.465 +*N chanx_left_in[13]:21 *C 13.340 57.742 +*N chanx_left_in[13]:22 *C 13.340 57.800 +*N chanx_left_in[13]:23 *C 13.340 58.480 + +*CAP +0 chanx_left_in[13] 0.0007064948 +1 mux_bottom_ipin_9\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_ipin_13\/mux_l2_in_1_:A0 1e-06 +3 FTB_14__13:A 1e-06 +4 chanx_left_in[13]:4 0.0002076498 +5 chanx_left_in[13]:5 0.0002076498 +6 chanx_left_in[13]:6 0.0002257538 +7 chanx_left_in[13]:7 0.0002257538 +8 chanx_left_in[13]:8 0.0003614612 +9 chanx_left_in[13]:9 5.121273e-05 +10 chanx_left_in[13]:10 5.572416e-05 +11 chanx_left_in[13]:11 8.807934e-05 +12 chanx_left_in[13]:12 8.807934e-05 +13 chanx_left_in[13]:13 0.002273617 +14 chanx_left_in[13]:14 0.001963365 +15 chanx_left_in[13]:15 0.00129402 +16 chanx_left_in[13]:16 0.001311196 +17 chanx_left_in[13]:17 0.0003586318 +18 chanx_left_in[13]:18 0.0003705378 +19 chanx_left_in[13]:19 0.0003705378 +20 chanx_left_in[13]:20 0.0001424183 +21 chanx_left_in[13]:21 0.0001424183 +22 chanx_left_in[13]:22 0.0003440236 +23 chanx_left_in[13]:23 0.0007602721 +24 chanx_left_in[13]:8 chanx_left_in[14]:9 0.0001447252 +25 chanx_left_in[13]:13 chanx_left_in[14]:10 0.0001447252 +26 chanx_left_in[13]:13 chanx_left_in[14]:9 0.0005154698 +27 chanx_left_in[13]:14 chanx_left_in[14]:10 0.0005154698 +28 chanx_left_in[13] chanx_left_in[19] 1.767507e-06 +29 chanx_left_in[13] chanx_left_in[19]:33 0.0001447063 +30 chanx_left_in[13]:22 chanx_left_in[19]:33 1.914472e-05 +31 chanx_left_in[13]:13 chanx_left_in[19]:24 1.792674e-06 +32 chanx_left_in[13]:23 chanx_left_in[19]:32 0.0001447063 +33 chanx_left_in[13]:23 chanx_left_in[19]:36 1.767507e-06 +34 chanx_left_in[13]:17 chanx_left_in[19]:32 1.914472e-05 +35 chanx_left_in[13]:16 chanx_left_in[19]:25 0.0001473489 +36 chanx_left_in[13]:16 chanx_left_in[19]:33 1.317042e-06 +37 chanx_left_in[13]:15 chanx_left_in[19]:24 0.0001473489 +38 chanx_left_in[13]:15 chanx_left_in[19]:32 1.317042e-06 +39 chanx_left_in[13]:14 chanx_left_in[19]:25 1.792674e-06 +40 chanx_left_in[13]:13 chanx_right_in[3]:45 0.0002172409 +41 chanx_left_in[13]:16 chanx_right_in[3]:44 0.0001227721 +42 chanx_left_in[13]:15 chanx_right_in[3]:45 0.0001227721 +43 chanx_left_in[13]:14 chanx_right_in[3]:44 0.0002172409 +44 chanx_left_in[13]:7 chanx_right_in[17]:22 3.133344e-07 +45 chanx_left_in[13]:7 chanx_right_in[17]:25 5.482025e-06 +46 chanx_left_in[13]:8 chanx_right_in[17] 1.209982e-06 +47 chanx_left_in[13]:8 chanx_right_in[17]:24 0.0001214509 +48 chanx_left_in[13]:8 chanx_right_in[17]:25 8.773404e-05 +49 chanx_left_in[13]:6 chanx_right_in[17]:23 3.133344e-07 +50 chanx_left_in[13]:6 chanx_right_in[17]:26 5.482025e-06 +51 chanx_left_in[13]:13 chanx_right_in[17]:24 0.0007220581 +52 chanx_left_in[13]:13 chanx_right_in[17]:20 0.0001214509 +53 chanx_left_in[13]:13 chanx_right_in[17]:17 0.0002475504 +54 chanx_left_in[13]:13 chanx_right_in[17]:26 1.209982e-06 +55 chanx_left_in[13]:14 chanx_right_in[17]:20 0.000634324 +56 chanx_left_in[13]:14 chanx_right_in[17]:16 0.0002475504 +57 chanx_left_in[13]:13 prog_clk[0]:252 0.0003724089 +58 chanx_left_in[13]:14 prog_clk[0]:253 0.0003724089 +59 chanx_left_in[13]:13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 0.0001458615 +60 chanx_left_in[13]:15 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 9.174879e-06 +61 chanx_left_in[13]:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 0.0001458615 +62 chanx_left_in[13]:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 9.174879e-06 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:23 0.001897233 +1 chanx_left_in[13]:21 chanx_left_in[13]:20 0.002033482 +2 chanx_left_in[13]:22 chanx_left_in[13]:21 0.00341 +3 chanx_left_in[13]:22 chanx_left_in[13]:17 0.0005044666 +4 chanx_left_in[13]:19 chanx_left_in[13]:18 0.003470982 +5 chanx_left_in[13]:20 chanx_left_in[13]:19 0.0045 +6 chanx_left_in[13]:18 mux_bottom_ipin_9\/mux_l2_in_1_:A0 0.152 +7 chanx_left_in[13]:7 chanx_left_in[13]:6 0.002944197 +8 chanx_left_in[13]:8 chanx_left_in[13]:7 0.00341 +9 chanx_left_in[13]:5 chanx_left_in[13]:4 0.002390625 +10 chanx_left_in[13]:6 chanx_left_in[13]:5 0.0045 +11 chanx_left_in[13]:4 FTB_14__13:A 0.152 +12 chanx_left_in[13]:12 chanx_left_in[13]:11 0.0008191965 +13 chanx_left_in[13]:13 chanx_left_in[13]:12 0.00341 +14 chanx_left_in[13]:13 chanx_left_in[13]:8 0.001512225 +15 chanx_left_in[13]:10 chanx_left_in[13]:9 0.0001576087 +16 chanx_left_in[13]:11 chanx_left_in[13]:10 0.0045 +17 chanx_left_in[13]:9 mux_bottom_ipin_13\/mux_l2_in_1_:A0 0.152 +18 chanx_left_in[13]:23 chanx_left_in[13]:22 0.0001065333 +19 chanx_left_in[13]:17 chanx_left_in[13]:16 0.0001065333 +20 chanx_left_in[13]:16 chanx_left_in[13]:15 0.003170933 +21 chanx_left_in[13]:15 chanx_left_in[13]:14 0.0001065333 +22 chanx_left_in[13]:14 chanx_left_in[13]:13 0.007783199 + +*END + +*D_NET chanx_left_in[19] 0.02313307 //LENGTH 166.600 LUMPCC 0.004119184 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 62.560 +*I mux_bottom_ipin_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 21.450 60.520 +*I mux_bottom_ipin_7\/mux_l2_in_2_:A0 I *L 0.001631 *C 36.630 59.160 +*I ropt_mt_inst_738:A I *L 0.001767 *C 97.825 4.080 +*I mux_bottom_ipin_15\/mux_l2_in_2_:A0 I *L 0.001631 *C 72.050 60.520 +*N chanx_left_in[19]:5 *C 72.050 60.520 +*N chanx_left_in[19]:6 *C 71.760 60.520 +*N chanx_left_in[19]:7 *C 71.760 60.475 +*N chanx_left_in[19]:8 *C 97.863 4.080 +*N chanx_left_in[19]:9 *C 100.235 4.080 +*N chanx_left_in[19]:10 *C 100.280 4.125 +*N chanx_left_in[19]:11 *C 100.280 14.902 +*N chanx_left_in[19]:12 *C 100.273 14.960 +*N chanx_left_in[19]:13 *C 86.500 14.960 +*N chanx_left_in[19]:14 *C 86.480 14.968 +*N chanx_left_in[19]:15 *C 86.480 59.833 +*N chanx_left_in[19]:16 *C 86.460 59.840 +*N chanx_left_in[19]:17 *C 71.767 59.840 +*N chanx_left_in[19]:18 *C 71.760 59.840 +*N chanx_left_in[19]:19 *C 71.760 59.205 +*N chanx_left_in[19]:20 *C 71.715 59.160 +*N chanx_left_in[19]:21 *C 36.630 59.160 +*N chanx_left_in[19]:22 *C 36.845 59.160 +*N chanx_left_in[19]:23 *C 36.800 59.160 +*N chanx_left_in[19]:24 *C 36.793 59.160 +*N chanx_left_in[19]:25 *C 23.008 59.160 +*N chanx_left_in[19]:26 *C 23.000 59.218 +*N chanx_left_in[19]:27 *C 23.000 60.475 +*N chanx_left_in[19]:28 *C 22.955 60.520 +*N chanx_left_in[19]:29 *C 21.450 60.520 +*N chanx_left_in[19]:30 *C 17.525 60.520 +*N chanx_left_in[19]:31 *C 17.480 60.520 +*N chanx_left_in[19]:32 *C 17.473 60.520 +*N chanx_left_in[19]:33 *C 2.780 60.520 +*N chanx_left_in[19]:34 *C 2.760 60.528 +*N chanx_left_in[19]:35 *C 2.760 62.553 +*N chanx_left_in[19]:36 *C 2.740 62.560 + +*CAP +0 chanx_left_in[19] 0.0001442658 +1 mux_bottom_ipin_9\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_7\/mux_l2_in_2_:A0 1e-06 +3 ropt_mt_inst_738:A 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[19]:5 5.290527e-05 +6 chanx_left_in[19]:6 5.625926e-05 +7 chanx_left_in[19]:7 5.515798e-05 +8 chanx_left_in[19]:8 0.0002018884 +9 chanx_left_in[19]:9 0.0002018884 +10 chanx_left_in[19]:10 0.0005651585 +11 chanx_left_in[19]:11 0.0005651585 +12 chanx_left_in[19]:12 0.00098648 +13 chanx_left_in[19]:13 0.00098648 +14 chanx_left_in[19]:14 0.002575984 +15 chanx_left_in[19]:15 0.002575984 +16 chanx_left_in[19]:16 0.0003453862 +17 chanx_left_in[19]:17 0.000345386 +18 chanx_left_in[19]:18 0.0001479646 +19 chanx_left_in[19]:19 5.515798e-05 +20 chanx_left_in[19]:20 0.002224702 +21 chanx_left_in[19]:21 5.366212e-05 +22 chanx_left_in[19]:22 0.002244909 +23 chanx_left_in[19]:23 3.830583e-05 +24 chanx_left_in[19]:24 0.0007096909 +25 chanx_left_in[19]:25 0.0007096909 +26 chanx_left_in[19]:26 0.0001056653 +27 chanx_left_in[19]:27 0.0001056653 +28 chanx_left_in[19]:28 0.0001068169 +29 chanx_left_in[19]:29 0.0004055622 +30 chanx_left_in[19]:30 0.0002680864 +31 chanx_left_in[19]:31 3.676939e-05 +32 chanx_left_in[19]:32 0.000842344 +33 chanx_left_in[19]:33 0.000842344 +34 chanx_left_in[19]:34 0.0001549494 +35 chanx_left_in[19]:35 0.0001549494 +36 chanx_left_in[19]:36 0.0001442658 +37 chanx_left_in[19]:15 chanx_left_in[3]:25 0.0003053746 +38 chanx_left_in[19]:14 chanx_left_in[3]:24 0.0003053746 +39 chanx_left_in[19] chanx_left_in[13] 1.767507e-06 +40 chanx_left_in[19]:24 chanx_left_in[13]:13 1.792674e-06 +41 chanx_left_in[19]:24 chanx_left_in[13]:15 0.0001473489 +42 chanx_left_in[19]:25 chanx_left_in[13]:14 1.792674e-06 +43 chanx_left_in[19]:25 chanx_left_in[13]:16 0.0001473489 +44 chanx_left_in[19]:32 chanx_left_in[13]:15 1.317042e-06 +45 chanx_left_in[19]:32 chanx_left_in[13]:17 1.914472e-05 +46 chanx_left_in[19]:32 chanx_left_in[13]:23 0.0001447063 +47 chanx_left_in[19]:33 chanx_left_in[13] 0.0001447063 +48 chanx_left_in[19]:33 chanx_left_in[13]:16 1.317042e-06 +49 chanx_left_in[19]:33 chanx_left_in[13]:22 1.914472e-05 +50 chanx_left_in[19]:36 chanx_left_in[13]:23 1.767507e-06 +51 chanx_left_in[19]:24 chanx_right_in[13]:17 2.54252e-05 +52 chanx_left_in[19]:24 chanx_right_in[13]:18 0.0001423899 +53 chanx_left_in[19]:25 chanx_right_in[13]:17 0.0001423899 +54 chanx_left_in[19]:25 chanx_right_in[13]:7 2.54252e-05 +55 chanx_left_in[19]:17 chanx_right_in[13]:17 6.707787e-05 +56 chanx_left_in[19]:17 chanx_right_in[13]:18 0.0002774954 +57 chanx_left_in[19]:16 chanx_right_in[13]:22 0.0002774954 +58 chanx_left_in[19]:16 chanx_right_in[13]:18 6.707787e-05 +59 chanx_left_in[19]:17 chanx_right_in[17]:20 0.000838614 +60 chanx_left_in[19]:16 chanx_right_in[17]:24 0.000838614 +61 chanx_left_in[19]:22 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.713773e-05 +62 chanx_left_in[19]:20 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.713773e-05 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:36 0.0002365666 +1 chanx_left_in[19]:22 chanx_left_in[19]:21 0.0001168478 +2 chanx_left_in[19]:22 chanx_left_in[19]:20 0.03113393 +3 chanx_left_in[19]:23 chanx_left_in[19]:22 0.0045 +4 chanx_left_in[19]:24 chanx_left_in[19]:23 0.00341 +5 chanx_left_in[19]:26 chanx_left_in[19]:25 0.00341 +6 chanx_left_in[19]:25 chanx_left_in[19]:24 0.00215965 +7 chanx_left_in[19]:28 chanx_left_in[19]:27 0.0045 +8 chanx_left_in[19]:27 chanx_left_in[19]:26 0.001122768 +9 chanx_left_in[19]:20 chanx_left_in[19]:19 0.0045 +10 chanx_left_in[19]:19 chanx_left_in[19]:18 0.0005669643 +11 chanx_left_in[19]:18 chanx_left_in[19]:17 0.00341 +12 chanx_left_in[19]:18 chanx_left_in[19]:7 0.0005669643 +13 chanx_left_in[19]:17 chanx_left_in[19]:16 0.002301825 +14 chanx_left_in[19]:16 chanx_left_in[19]:15 0.00341 +15 chanx_left_in[19]:15 chanx_left_in[19]:14 0.007028849 +16 chanx_left_in[19]:13 chanx_left_in[19]:12 0.002157692 +17 chanx_left_in[19]:14 chanx_left_in[19]:13 0.00341 +18 chanx_left_in[19]:11 chanx_left_in[19]:10 0.009622768 +19 chanx_left_in[19]:12 chanx_left_in[19]:11 0.00341 +20 chanx_left_in[19]:9 chanx_left_in[19]:8 0.002118304 +21 chanx_left_in[19]:10 chanx_left_in[19]:9 0.0045 +22 chanx_left_in[19]:8 ropt_mt_inst_738:A 0.152 +23 chanx_left_in[19]:21 mux_bottom_ipin_7\/mux_l2_in_2_:A0 0.152 +24 chanx_left_in[19]:6 chanx_left_in[19]:5 0.0001576087 +25 chanx_left_in[19]:7 chanx_left_in[19]:6 0.0045 +26 chanx_left_in[19]:5 mux_bottom_ipin_15\/mux_l2_in_2_:A0 0.152 +27 chanx_left_in[19]:29 mux_bottom_ipin_9\/mux_l2_in_2_:A0 0.152 +28 chanx_left_in[19]:29 chanx_left_in[19]:28 0.00134375 +29 chanx_left_in[19]:30 chanx_left_in[19]:29 0.003504464 +30 chanx_left_in[19]:31 chanx_left_in[19]:30 0.0045 +31 chanx_left_in[19]:32 chanx_left_in[19]:31 0.00341 +32 chanx_left_in[19]:33 chanx_left_in[19]:32 0.002301825 +33 chanx_left_in[19]:34 chanx_left_in[19]:33 0.00341 +34 chanx_left_in[19]:36 chanx_left_in[19]:35 0.00341 +35 chanx_left_in[19]:35 chanx_left_in[19]:34 0.00031725 + +*END + +*D_NET chanx_right_in[3] 0.02516769 //LENGTH 176.818 LUMPCC 0.006475862 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 103.650 47.600 +*I mux_bottom_ipin_13\/mux_l1_in_1_:A0 I *L 0.001631 *C 86.770 49.640 +*I mux_bottom_ipin_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 65.150 48.280 +*I mux_bottom_ipin_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 58.250 53.380 +*I mux_bottom_ipin_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 27.400 55.420 +*I mux_bottom_ipin_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 32.300 39.780 +*I mux_bottom_ipin_11\/mux_l2_in_1_:A1 I *L 0.00198 *C 19.880 34.340 +*I FTB_24__23:A I *L 0.001767 *C 16.100 4.080 +*I mux_bottom_ipin_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 31.645 56.100 +*I mux_bottom_ipin_15\/mux_l2_in_1_:A1 I *L 0.00198 *C 59.900 61.540 +*N chanx_right_in[3]:10 *C 59.863 61.540 +*N chanx_right_in[3]:11 *C 59.385 61.540 +*N chanx_right_in[3]:12 *C 59.340 61.495 +*N chanx_right_in[3]:13 *C 31.645 56.100 +*N chanx_right_in[3]:14 *C 31.710 56.070 +*N chanx_right_in[3]:15 *C 31.695 55.760 +*N chanx_right_in[3]:16 *C 12.480 31.960 +*N chanx_right_in[3]:17 *C 12.170 12.240 +*N chanx_right_in[3]:18 *C 16.062 4.080 +*N chanx_right_in[3]:19 *C 12.925 4.080 +*N chanx_right_in[3]:20 *C 12.880 4.125 +*N chanx_right_in[3]:21 *C 12.880 12.183 +*N chanx_right_in[3]:22 *C 12.878 12.240 +*N chanx_right_in[3]:23 *C 12.880 12.248 +*N chanx_right_in[3]:24 *C 12.880 31.953 +*N chanx_right_in[3]:25 *C 12.880 31.960 +*N chanx_right_in[3]:26 *C 12.880 31.960 +*N chanx_right_in[3]:27 *C 12.925 31.960 +*N chanx_right_in[3]:28 *C 18.355 31.960 +*N chanx_right_in[3]:29 *C 18.400 32.005 +*N chanx_right_in[3]:30 *C 18.400 34.295 +*N chanx_right_in[3]:31 *C 18.445 34.340 +*N chanx_right_in[3]:32 *C 19.780 34.340 +*N chanx_right_in[3]:33 *C 19.793 34.363 +*N chanx_right_in[3]:34 *C 19.780 34.680 +*N chanx_right_in[3]:35 *C 31.235 34.680 +*N chanx_right_in[3]:36 *C 31.280 34.725 +*N chanx_right_in[3]:37 *C 32.263 39.780 +*N chanx_right_in[3]:38 *C 31.325 39.780 +*N chanx_right_in[3]:39 *C 31.280 39.780 +*N chanx_right_in[3]:40 *C 27.438 55.420 +*N chanx_right_in[3]:41 *C 31.235 55.420 +*N chanx_right_in[3]:42 *C 31.280 55.375 +*N chanx_right_in[3]:43 *C 31.280 55.760 +*N chanx_right_in[3]:44 *C 31.288 55.760 +*N chanx_right_in[3]:45 *C 59.333 55.760 +*N chanx_right_in[3]:46 *C 59.340 55.760 +*N chanx_right_in[3]:47 *C 58.288 53.380 +*N chanx_right_in[3]:48 *C 59.295 53.380 +*N chanx_right_in[3]:49 *C 59.340 53.380 +*N chanx_right_in[3]:50 *C 59.340 49.698 +*N chanx_right_in[3]:51 *C 59.348 49.640 +*N chanx_right_in[3]:52 *C 65.150 48.280 +*N chanx_right_in[3]:53 *C 64.860 48.280 +*N chanx_right_in[3]:54 *C 64.860 48.325 +*N chanx_right_in[3]:55 *C 64.860 49.583 +*N chanx_right_in[3]:56 *C 64.860 49.640 +*N chanx_right_in[3]:57 *C 86.770 49.640 +*N chanx_right_in[3]:58 *C 86.480 49.640 +*N chanx_right_in[3]:59 *C 86.480 49.640 +*N chanx_right_in[3]:60 *C 86.480 49.640 +*N chanx_right_in[3]:61 *C 101.180 49.640 +*N chanx_right_in[3]:62 *C 101.200 49.633 +*N chanx_right_in[3]:63 *C 101.200 47.608 +*N chanx_right_in[3]:64 *C 101.220 47.600 + +*CAP +0 chanx_right_in[3] 0.0001626543 +1 mux_bottom_ipin_13\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_ipin_1\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_ipin_5\/mux_l1_in_1_:A0 1e-06 +4 mux_bottom_ipin_9\/mux_l1_in_1_:A0 1e-06 +5 mux_bottom_ipin_3\/mux_l2_in_1_:A1 1e-06 +6 mux_bottom_ipin_11\/mux_l2_in_1_:A1 1e-06 +7 FTB_24__23:A 1e-06 +8 mux_bottom_ipin_7\/mux_l2_in_1_:A1 1e-06 +9 mux_bottom_ipin_15\/mux_l2_in_1_:A1 1e-06 +10 chanx_right_in[3]:10 7.317465e-05 +11 chanx_right_in[3]:11 7.317465e-05 +12 chanx_right_in[3]:12 0.0002601742 +13 chanx_right_in[3]:13 3.062019e-05 +14 chanx_right_in[3]:14 3.740744e-05 +15 chanx_right_in[3]:15 5.504393e-05 +16 chanx_right_in[3]:16 0.0001002658 +17 chanx_right_in[3]:17 6.699244e-05 +18 chanx_right_in[3]:18 0.0002410248 +19 chanx_right_in[3]:19 0.0002410248 +20 chanx_right_in[3]:20 0.0003761457 +21 chanx_right_in[3]:21 0.0003761457 +22 chanx_right_in[3]:22 6.699244e-05 +23 chanx_right_in[3]:23 0.0009644755 +24 chanx_right_in[3]:24 0.0009644755 +25 chanx_right_in[3]:25 0.0001002658 +26 chanx_right_in[3]:26 3.682816e-05 +27 chanx_right_in[3]:27 0.0004232676 +28 chanx_right_in[3]:28 0.0004232676 +29 chanx_right_in[3]:29 0.0001508314 +30 chanx_right_in[3]:30 0.0001508314 +31 chanx_right_in[3]:31 0.0001043943 +32 chanx_right_in[3]:32 0.0001123077 +33 chanx_right_in[3]:33 2.780698e-05 +34 chanx_right_in[3]:34 0.0009074526 +35 chanx_right_in[3]:35 0.000887559 +36 chanx_right_in[3]:36 0.000288209 +37 chanx_right_in[3]:37 0.0001201964 +38 chanx_right_in[3]:38 0.0001201964 +39 chanx_right_in[3]:39 0.001231788 +40 chanx_right_in[3]:40 0.0001352454 +41 chanx_right_in[3]:41 0.0001352454 +42 chanx_right_in[3]:42 0.0009313588 +43 chanx_right_in[3]:43 7.706115e-05 +44 chanx_right_in[3]:44 0.001050054 +45 chanx_right_in[3]:45 0.001050054 +46 chanx_right_in[3]:46 0.0004274297 +47 chanx_right_in[3]:47 7.391394e-05 +48 chanx_right_in[3]:48 7.391394e-05 +49 chanx_right_in[3]:49 0.0003384255 +50 chanx_right_in[3]:50 0.0001772788 +51 chanx_right_in[3]:51 0.0003166773 +52 chanx_right_in[3]:52 4.780653e-05 +53 chanx_right_in[3]:53 5.226942e-05 +54 chanx_right_in[3]:54 5.809035e-05 +55 chanx_right_in[3]:55 5.809035e-05 +56 chanx_right_in[3]:56 0.00105859 +57 chanx_right_in[3]:57 5.321889e-05 +58 chanx_right_in[3]:58 5.757072e-05 +59 chanx_right_in[3]:59 3.518268e-05 +60 chanx_right_in[3]:60 0.001817238 +61 chanx_right_in[3]:61 0.001075326 +62 chanx_right_in[3]:62 0.0001225648 +63 chanx_right_in[3]:63 0.0001225648 +64 chanx_right_in[3]:64 0.0001626543 +65 chanx_right_in[3]:43 chanx_left_in[3]:56 1.827865e-05 +66 chanx_right_in[3]:44 chanx_left_in[3]:49 0.0001547537 +67 chanx_right_in[3]:45 chanx_left_in[3]:48 0.0001547537 +68 chanx_right_in[3]:50 chanx_left_in[3]:43 6.142675e-05 +69 chanx_right_in[3]:51 chanx_left_in[3]:44 0.0001127053 +70 chanx_right_in[3]:48 chanx_left_in[3]:41 2.50646e-05 +71 chanx_right_in[3]:49 chanx_left_in[3]:42 6.142675e-05 +72 chanx_right_in[3]:47 chanx_left_in[3]:40 2.50646e-05 +73 chanx_right_in[3]:41 chanx_left_in[3]:55 3.002703e-05 +74 chanx_right_in[3]:40 chanx_left_in[3]:56 3.002703e-05 +75 chanx_right_in[3]:55 chanx_left_in[3]:30 4.364934e-05 +76 chanx_right_in[3]:56 chanx_left_in[3]:26 5.68817e-05 +77 chanx_right_in[3]:56 chanx_left_in[3]:38 0.0005180353 +78 chanx_right_in[3]:56 chanx_left_in[3]:44 9.494509e-06 +79 chanx_right_in[3]:53 chanx_left_in[3]:27 2.350143e-06 +80 chanx_right_in[3]:54 chanx_left_in[3]:29 4.364934e-05 +81 chanx_right_in[3]:52 chanx_left_in[3]:28 2.350143e-06 +82 chanx_right_in[3]:60 chanx_left_in[3]:13 5.68817e-05 +83 chanx_right_in[3]:60 chanx_left_in[3]:26 0.0004085833 +84 chanx_right_in[3]:60 chanx_left_in[3]:38 9.494509e-06 +85 chanx_right_in[3]:61 chanx_left_in[3]:13 3.253376e-06 +86 chanx_right_in[3]:15 chanx_left_in[3]:55 1.827865e-05 +87 chanx_right_in[3]:44 chanx_left_in[11]:28 3.162096e-05 +88 chanx_right_in[3]:46 chanx_left_in[11]:21 2.113467e-05 +89 chanx_right_in[3]:46 chanx_left_in[11]:24 0.0001220862 +90 chanx_right_in[3]:46 chanx_left_in[11]:25 4.699221e-06 +91 chanx_right_in[3]:45 chanx_left_in[11]:27 3.162096e-05 +92 chanx_right_in[3]:50 chanx_left_in[11]:26 2.396695e-06 +93 chanx_right_in[3]:49 chanx_left_in[11]:24 2.113467e-05 +94 chanx_right_in[3]:49 chanx_left_in[11]:25 2.396695e-06 +95 chanx_right_in[3]:49 chanx_left_in[11]:26 4.699221e-06 +96 chanx_right_in[3]:39 chanx_left_in[11]:29 6.73148e-06 +97 chanx_right_in[3]:11 chanx_left_in[11]:20 1.479867e-06 +98 chanx_right_in[3]:12 chanx_left_in[11]:21 0.0001220862 +99 chanx_right_in[3]:10 chanx_left_in[11]:19 1.479867e-06 +100 chanx_right_in[3]:41 chanx_left_in[11]:32 0.0001516148 +101 chanx_right_in[3]:42 chanx_left_in[11]:30 6.73148e-06 +102 chanx_right_in[3]:40 chanx_left_in[11]:33 0.0001516148 +103 chanx_right_in[3]:44 chanx_left_in[13]:14 0.0002172409 +104 chanx_right_in[3]:44 chanx_left_in[13]:16 0.0001227721 +105 chanx_right_in[3]:45 chanx_left_in[13]:13 0.0002172409 +106 chanx_right_in[3]:45 chanx_left_in[13]:15 0.0001227721 +107 chanx_right_in[3]:43 chanx_right_in[1]:23 3.411395e-07 +108 chanx_right_in[3]:44 chanx_right_in[1]:33 0.0006186683 +109 chanx_right_in[3]:44 chanx_right_in[1]:37 0.0002568698 +110 chanx_right_in[3]:45 chanx_right_in[1]:37 0.0006186683 +111 chanx_right_in[3]:45 chanx_right_in[1]:43 0.0002568698 +112 chanx_right_in[3]:14 chanx_right_in[1]:19 8.256724e-08 +113 chanx_right_in[3]:39 chanx_right_in[1]:23 2.215009e-06 +114 chanx_right_in[3]:39 chanx_right_in[1]:24 2.574242e-06 +115 chanx_right_in[3]:42 chanx_right_in[1]:19 2.556149e-06 +116 chanx_right_in[3]:42 chanx_right_in[1]:23 2.574242e-06 +117 chanx_right_in[3]:15 chanx_right_in[1]:23 8.256724e-08 +118 chanx_right_in[3]:20 prog_clk[0]:312 1.359118e-06 +119 chanx_right_in[3]:21 prog_clk[0]:311 1.359118e-06 +120 chanx_right_in[3]:44 prog_clk[0]:194 1.166558e-06 +121 chanx_right_in[3]:45 prog_clk[0]:193 1.166558e-06 +122 chanx_right_in[3]:51 prog_clk[0]:260 2.688166e-05 +123 chanx_right_in[3]:55 prog_clk[0]:257 5.116514e-06 +124 chanx_right_in[3]:56 prog_clk[0]:260 1.733491e-05 +125 chanx_right_in[3]:56 prog_clk[0]:259 6.421005e-05 +126 chanx_right_in[3]:56 prog_clk[0]:240 7.524237e-05 +127 chanx_right_in[3]:56 prog_clk[0]:236 0.0001470093 +128 chanx_right_in[3]:54 prog_clk[0]:258 5.116514e-06 +129 chanx_right_in[3]:60 prog_clk[0]:231 0.0001470093 +130 chanx_right_in[3]:60 prog_clk[0]:259 1.733491e-05 +131 chanx_right_in[3]:60 prog_clk[0]:240 3.732838e-05 +132 chanx_right_in[3]:60 prog_clk[0]:236 9.85833e-05 +133 chanx_right_in[3]:61 prog_clk[0]:231 2.334094e-05 +134 chanx_right_in[3]:23 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0002697848 +135 chanx_right_in[3]:24 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002697848 +136 chanx_right_in[3]:20 ropt_net_189:4 6.358048e-05 +137 chanx_right_in[3]:21 ropt_net_189:3 6.358048e-05 +138 chanx_right_in[3]:20 ropt_net_129:8 2.464818e-05 +139 chanx_right_in[3]:21 ropt_net_129:7 2.464818e-05 +140 chanx_right_in[3]:22 ropt_net_129:5 5.939503e-05 +141 chanx_right_in[3]:17 ropt_net_129:6 5.939503e-05 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:64 0.0003807 +1 chanx_right_in[3]:18 FTB_24__23:A 0.152 +2 chanx_right_in[3]:19 chanx_right_in[3]:18 0.002801339 +3 chanx_right_in[3]:20 chanx_right_in[3]:19 0.0045 +4 chanx_right_in[3]:21 chanx_right_in[3]:20 0.007194197 +5 chanx_right_in[3]:22 chanx_right_in[3]:21 0.00341 +6 chanx_right_in[3]:22 chanx_right_in[3]:17 0.0001039141 +7 chanx_right_in[3]:23 chanx_right_in[3]:22 0.00341 +8 chanx_right_in[3]:25 chanx_right_in[3]:24 0.00341 +9 chanx_right_in[3]:25 chanx_right_in[3]:16 5.69697e-05 +10 chanx_right_in[3]:24 chanx_right_in[3]:23 0.003087116 +11 chanx_right_in[3]:26 chanx_right_in[3]:25 0.00341 +12 chanx_right_in[3]:27 chanx_right_in[3]:26 0.0045 +13 chanx_right_in[3]:28 chanx_right_in[3]:27 0.004848215 +14 chanx_right_in[3]:29 chanx_right_in[3]:28 0.0045 +15 chanx_right_in[3]:31 chanx_right_in[3]:30 0.0045 +16 chanx_right_in[3]:30 chanx_right_in[3]:29 0.002044643 +17 chanx_right_in[3]:35 chanx_right_in[3]:34 0.01022768 +18 chanx_right_in[3]:36 chanx_right_in[3]:35 0.0045 +19 chanx_right_in[3]:43 chanx_right_in[3]:42 0.0001850962 +20 chanx_right_in[3]:43 chanx_right_in[3]:15 0.0003705357 +21 chanx_right_in[3]:44 chanx_right_in[3]:43 0.00341 +22 chanx_right_in[3]:46 chanx_right_in[3]:45 0.00341 +23 chanx_right_in[3]:46 chanx_right_in[3]:12 0.005120536 +24 chanx_right_in[3]:45 chanx_right_in[3]:44 0.004393716 +25 chanx_right_in[3]:50 chanx_right_in[3]:49 0.003287947 +26 chanx_right_in[3]:51 chanx_right_in[3]:50 0.00341 +27 chanx_right_in[3]:13 mux_bottom_ipin_7\/mux_l2_in_1_:A1 0.152 +28 chanx_right_in[3]:14 chanx_right_in[3]:13 0.0045 +29 chanx_right_in[3]:48 chanx_right_in[3]:47 0.0008995536 +30 chanx_right_in[3]:49 chanx_right_in[3]:48 0.0045 +31 chanx_right_in[3]:49 chanx_right_in[3]:46 0.002125 +32 chanx_right_in[3]:47 mux_bottom_ipin_5\/mux_l1_in_1_:A0 0.152 +33 chanx_right_in[3]:38 chanx_right_in[3]:37 0.0008370535 +34 chanx_right_in[3]:39 chanx_right_in[3]:38 0.0045 +35 chanx_right_in[3]:39 chanx_right_in[3]:36 0.004513393 +36 chanx_right_in[3]:37 mux_bottom_ipin_3\/mux_l2_in_1_:A1 0.152 +37 chanx_right_in[3]:11 chanx_right_in[3]:10 0.0004263393 +38 chanx_right_in[3]:12 chanx_right_in[3]:11 0.0045 +39 chanx_right_in[3]:10 mux_bottom_ipin_15\/mux_l2_in_1_:A1 0.152 +40 chanx_right_in[3]:41 chanx_right_in[3]:40 0.003390625 +41 chanx_right_in[3]:42 chanx_right_in[3]:41 0.0045 +42 chanx_right_in[3]:42 chanx_right_in[3]:39 0.01392411 +43 chanx_right_in[3]:40 mux_bottom_ipin_9\/mux_l1_in_1_:A0 0.152 +44 chanx_right_in[3]:33 mux_bottom_ipin_11\/mux_l2_in_1_:A1 0.152 +45 chanx_right_in[3]:33 chanx_right_in[3]:32 1.116072e-05 +46 chanx_right_in[3]:55 chanx_right_in[3]:54 0.001122768 +47 chanx_right_in[3]:56 chanx_right_in[3]:55 0.00341 +48 chanx_right_in[3]:56 chanx_right_in[3]:51 0.000863625 +49 chanx_right_in[3]:53 chanx_right_in[3]:52 0.0001576087 +50 chanx_right_in[3]:54 chanx_right_in[3]:53 0.0045 +51 chanx_right_in[3]:52 mux_bottom_ipin_1\/mux_l1_in_1_:A0 0.152 +52 chanx_right_in[3]:59 chanx_right_in[3]:58 0.0045 +53 chanx_right_in[3]:60 chanx_right_in[3]:59 0.00341 +54 chanx_right_in[3]:60 chanx_right_in[3]:56 0.003387133 +55 chanx_right_in[3]:58 chanx_right_in[3]:57 0.0001576087 +56 chanx_right_in[3]:57 mux_bottom_ipin_13\/mux_l1_in_1_:A0 0.152 +57 chanx_right_in[3]:61 chanx_right_in[3]:60 0.002303 +58 chanx_right_in[3]:62 chanx_right_in[3]:61 0.00341 +59 chanx_right_in[3]:64 chanx_right_in[3]:63 0.00341 +60 chanx_right_in[3]:63 chanx_right_in[3]:62 0.00031725 +61 chanx_right_in[3]:32 chanx_right_in[3]:31 0.001191964 +62 chanx_right_in[3]:34 chanx_right_in[3]:33 0.0002834821 +63 chanx_right_in[3]:15 chanx_right_in[3]:14 0.00019375 + +*END + +*D_NET chanx_right_in[7] 0.01681858 //LENGTH 112.025 LUMPCC 0.004442067 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 103.650 38.760 +*I mux_bottom_ipin_13\/mux_l1_in_2_:A0 I *L 0.001631 *C 90.910 37.060 +*I mux_bottom_ipin_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 40.385 41.820 +*I BUFT_P_99:A I *L 0.001776 *C 6.900 39.440 +*I mux_bottom_ipin_11\/mux_l2_in_2_:A1 I *L 0.00198 *C 26.125 39.780 +*N chanx_right_in[7]:5 *C 26.088 39.780 +*N chanx_right_in[7]:6 *C 25.760 39.780 +*N chanx_right_in[7]:7 *C 6.900 39.477 +*N chanx_right_in[7]:8 *C 6.900 40.120 +*N chanx_right_in[7]:9 *C 25.760 40.120 +*N chanx_right_in[7]:10 *C 36.295 40.120 +*N chanx_right_in[7]:11 *C 36.340 40.165 +*N chanx_right_in[7]:12 *C 36.340 41.775 +*N chanx_right_in[7]:13 *C 36.385 41.820 +*N chanx_right_in[7]:14 *C 40.385 41.820 +*N chanx_right_in[7]:15 *C 46.415 41.820 +*N chanx_right_in[7]:16 *C 46.460 41.865 +*N chanx_right_in[7]:17 *C 46.460 42.782 +*N chanx_right_in[7]:18 *C 46.468 42.840 +*N chanx_right_in[7]:19 *C 75.433 42.840 +*N chanx_right_in[7]:20 *C 75.440 42.782 +*N chanx_right_in[7]:21 *C 75.440 37.445 +*N chanx_right_in[7]:22 *C 75.485 37.400 +*N chanx_right_in[7]:23 *C 90.910 37.400 +*N chanx_right_in[7]:24 *C 90.910 37.060 +*N chanx_right_in[7]:25 *C 100.695 37.060 +*N chanx_right_in[7]:26 *C 100.740 37.105 +*N chanx_right_in[7]:27 *C 100.740 38.703 +*N chanx_right_in[7]:28 *C 100.748 38.760 + +*CAP +0 chanx_right_in[7] 0.0002222413 +1 mux_bottom_ipin_13\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_2_:A1 1e-06 +3 BUFT_P_99:A 1e-06 +4 mux_bottom_ipin_11\/mux_l2_in_2_:A1 1e-06 +5 chanx_right_in[7]:5 3.409591e-05 +6 chanx_right_in[7]:6 6.266526e-05 +7 chanx_right_in[7]:7 4.338787e-05 +8 chanx_right_in[7]:8 0.001297968 +9 chanx_right_in[7]:9 0.002017317 +10 chanx_right_in[7]:10 0.0007341683 +11 chanx_right_in[7]:11 0.0001112288 +12 chanx_right_in[7]:12 0.0001112288 +13 chanx_right_in[7]:13 0.0002480696 +14 chanx_right_in[7]:14 0.0005467563 +15 chanx_right_in[7]:15 0.0002710175 +16 chanx_right_in[7]:16 7.068204e-05 +17 chanx_right_in[7]:17 7.068204e-05 +18 chanx_right_in[7]:18 0.00104515 +19 chanx_right_in[7]:19 0.00104515 +20 chanx_right_in[7]:20 0.0003125147 +21 chanx_right_in[7]:21 0.0003125147 +22 chanx_right_in[7]:22 0.001050912 +23 chanx_right_in[7]:23 0.001085629 +24 chanx_right_in[7]:24 0.000637775 +25 chanx_right_in[7]:25 0.000603058 +26 chanx_right_in[7]:26 0.0001080298 +27 chanx_right_in[7]:27 0.0001080298 +28 chanx_right_in[7]:28 0.0002222413 +29 chanx_right_in[7]:19 chanx_left_in[9]:12 0.0001013504 +30 chanx_right_in[7]:19 chanx_left_in[9]:17 0.0002404814 +31 chanx_right_in[7]:18 chanx_left_in[9]:17 0.0001013504 +32 chanx_right_in[7]:18 chanx_left_in[9]:18 0.0002404814 +33 chanx_right_in[7]:7 chanx_left_in[15]:30 6.647532e-06 +34 chanx_right_in[7]:10 chanx_left_in[15]:23 3.04734e-05 +35 chanx_right_in[7]:10 chanx_left_in[15]:25 1.679049e-06 +36 chanx_right_in[7]:11 chanx_left_in[15]:22 2.052141e-06 +37 chanx_right_in[7]:13 chanx_left_in[15]:20 2.224817e-05 +38 chanx_right_in[7]:13 chanx_left_in[15]:25 4.239812e-07 +39 chanx_right_in[7]:12 chanx_left_in[15]:21 2.052141e-06 +40 chanx_right_in[7]:19 chanx_left_in[15]:9 0.001100358 +41 chanx_right_in[7]:19 chanx_left_in[15]:14 0.0003372226 +42 chanx_right_in[7]:19 chanx_left_in[15]:18 8.287328e-06 +43 chanx_right_in[7]:17 chanx_left_in[15]:17 3.113651e-07 +44 chanx_right_in[7]:18 chanx_left_in[15]:14 0.001100358 +45 chanx_right_in[7]:18 chanx_left_in[15]:15 0.0003372226 +46 chanx_right_in[7]:18 chanx_left_in[15]:19 8.287328e-06 +47 chanx_right_in[7]:15 chanx_left_in[15]:18 4.394343e-05 +48 chanx_right_in[7]:15 chanx_left_in[15]:19 8.76108e-07 +49 chanx_right_in[7]:16 chanx_left_in[15]:16 3.113651e-07 +50 chanx_right_in[7]:14 chanx_left_in[15]:19 6.61916e-05 +51 chanx_right_in[7]:14 chanx_left_in[15]:20 8.76108e-07 +52 chanx_right_in[7]:14 chanx_left_in[15]:23 4.239812e-07 +53 chanx_right_in[7]:8 chanx_left_in[15]:31 6.647532e-06 +54 chanx_right_in[7]:9 chanx_left_in[15]:24 1.679049e-06 +55 chanx_right_in[7]:9 chanx_left_in[15]:25 3.04734e-05 +56 chanx_right_in[7]:13 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 6.196603e-05 +57 chanx_right_in[7]:15 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001280223 +58 chanx_right_in[7]:14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001280223 +59 chanx_right_in[7]:14 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.196603e-05 +60 chanx_right_in[7]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.640296e-05 +61 chanx_right_in[7]:9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.640296e-05 +62 chanx_right_in[7]:22 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.828738e-05 +63 chanx_right_in[7]:23 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.828738e-05 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:28 0.0004547249 +1 chanx_right_in[7]:7 BUFT_P_99:A 0.152 +2 chanx_right_in[7]:10 chanx_right_in[7]:9 0.009406251 +3 chanx_right_in[7]:11 chanx_right_in[7]:10 0.0045 +4 chanx_right_in[7]:13 chanx_right_in[7]:12 0.0045 +5 chanx_right_in[7]:12 chanx_right_in[7]:11 0.0014375 +6 chanx_right_in[7]:22 chanx_right_in[7]:21 0.0045 +7 chanx_right_in[7]:21 chanx_right_in[7]:20 0.004765625 +8 chanx_right_in[7]:20 chanx_right_in[7]:19 0.00341 +9 chanx_right_in[7]:19 chanx_right_in[7]:18 0.00453785 +10 chanx_right_in[7]:17 chanx_right_in[7]:16 0.0008191965 +11 chanx_right_in[7]:18 chanx_right_in[7]:17 0.00341 +12 chanx_right_in[7]:15 chanx_right_in[7]:14 0.005383929 +13 chanx_right_in[7]:16 chanx_right_in[7]:15 0.0045 +14 chanx_right_in[7]:25 chanx_right_in[7]:24 0.008736608 +15 chanx_right_in[7]:26 chanx_right_in[7]:25 0.0045 +16 chanx_right_in[7]:27 chanx_right_in[7]:26 0.001426339 +17 chanx_right_in[7]:28 chanx_right_in[7]:27 0.00341 +18 chanx_right_in[7]:14 mux_bottom_ipin_3\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[7]:14 chanx_right_in[7]:13 0.003571429 +20 chanx_right_in[7]:5 mux_bottom_ipin_11\/mux_l2_in_2_:A1 0.152 +21 chanx_right_in[7]:24 mux_bottom_ipin_13\/mux_l1_in_2_:A0 0.152 +22 chanx_right_in[7]:24 chanx_right_in[7]:23 0.0003035715 +23 chanx_right_in[7]:8 chanx_right_in[7]:7 0.0005736608 +24 chanx_right_in[7]:9 chanx_right_in[7]:8 0.01683929 +25 chanx_right_in[7]:9 chanx_right_in[7]:6 0.0003035714 +26 chanx_right_in[7]:6 chanx_right_in[7]:5 0.0002924107 +27 chanx_right_in[7]:23 chanx_right_in[7]:22 0.01377232 + +*END + +*D_NET chanx_right_in[13] 0.02074586 //LENGTH 156.120 LUMPCC 0.006362601 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 103.650 72.080 +*I mux_bottom_ipin_13\/mux_l2_in_2_:A1 I *L 0.00198 *C 90.985 61.540 +*I BUFT_P_101:A I *L 0.001776 *C 20.700 6.800 +*I mux_bottom_ipin_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 21.065 61.540 +*N chanx_right_in[13]:4 *C 21.065 61.540 +*N chanx_right_in[13]:5 *C 21.160 61.540 +*N chanx_right_in[13]:6 *C 21.160 61.200 +*N chanx_right_in[13]:7 *C 21.168 61.200 +*N chanx_right_in[13]:8 *C 20.738 6.800 +*N chanx_right_in[13]:9 *C 22.955 6.800 +*N chanx_right_in[13]:10 *C 23.000 6.755 +*N chanx_right_in[13]:11 *C 23.000 6.178 +*N chanx_right_in[13]:12 *C 23.008 6.120 +*N chanx_right_in[13]:13 *C 24.820 6.120 +*N chanx_right_in[13]:14 *C 24.840 6.128 +*N chanx_right_in[13]:15 *C 24.840 55.955 +*N chanx_right_in[13]:16 *C 24.840 61.193 +*N chanx_right_in[13]:17 *C 24.840 61.200 +*N chanx_right_in[13]:18 *C 74.840 61.200 +*N chanx_right_in[13]:19 *C 90.985 61.540 +*N chanx_right_in[13]:20 *C 91.080 61.540 +*N chanx_right_in[13]:21 *C 91.080 61.200 +*N chanx_right_in[13]:22 *C 91.080 61.200 +*N chanx_right_in[13]:23 *C 92.900 61.200 +*N chanx_right_in[13]:24 *C 92.920 61.208 +*N chanx_right_in[13]:25 *C 92.920 72.073 +*N chanx_right_in[13]:26 *C 92.940 72.080 + +*CAP +0 chanx_right_in[13] 0.0003453895 +1 mux_bottom_ipin_13\/mux_l2_in_2_:A1 1e-06 +2 BUFT_P_101:A 1e-06 +3 mux_bottom_ipin_9\/mux_l2_in_2_:A1 1e-06 +4 chanx_right_in[13]:4 2.679689e-05 +5 chanx_right_in[13]:5 5.099926e-05 +6 chanx_right_in[13]:6 5.483382e-05 +7 chanx_right_in[13]:7 0.0001258283 +8 chanx_right_in[13]:8 9.162886e-05 +9 chanx_right_in[13]:9 9.162886e-05 +10 chanx_right_in[13]:10 4.934899e-05 +11 chanx_right_in[13]:11 4.934899e-05 +12 chanx_right_in[13]:12 0.0001114673 +13 chanx_right_in[13]:13 0.0001114673 +14 chanx_right_in[13]:14 0.002550419 +15 chanx_right_in[13]:15 0.002792602 +16 chanx_right_in[13]:16 0.0002421834 +17 chanx_right_in[13]:17 0.002334169 +18 chanx_right_in[13]:18 0.002833944 +19 chanx_right_in[13]:19 2.750951e-05 +20 chanx_right_in[13]:20 5.76235e-05 +21 chanx_right_in[13]:21 6.176549e-05 +22 chanx_right_in[13]:22 0.0007143128 +23 chanx_right_in[13]:23 8.870866e-05 +24 chanx_right_in[13]:24 0.0006114496 +25 chanx_right_in[13]:25 0.0006114496 +26 chanx_right_in[13]:26 0.0003453895 +27 chanx_right_in[13]:17 chanx_left_in[19]:17 6.707787e-05 +28 chanx_right_in[13]:17 chanx_left_in[19]:24 2.54252e-05 +29 chanx_right_in[13]:17 chanx_left_in[19]:25 0.0001423899 +30 chanx_right_in[13]:22 chanx_left_in[19]:16 0.0002774954 +31 chanx_right_in[13]:7 chanx_left_in[19]:25 2.54252e-05 +32 chanx_right_in[13]:18 chanx_left_in[19]:16 6.707787e-05 +33 chanx_right_in[13]:18 chanx_left_in[19]:17 0.0002774954 +34 chanx_right_in[13]:18 chanx_left_in[19]:24 0.0001423899 +35 chanx_right_in[13] chanx_right_in[11] 1.58857e-05 +36 chanx_right_in[13]:17 chanx_right_in[11]:22 5.825397e-06 +37 chanx_right_in[13]:17 chanx_right_in[11]:26 5.006127e-05 +38 chanx_right_in[13]:17 chanx_right_in[11]:31 0.0001751904 +39 chanx_right_in[13]:9 chanx_right_in[11]:14 9.931695e-05 +40 chanx_right_in[13]:8 chanx_right_in[11]:13 9.931695e-05 +41 chanx_right_in[13]:26 chanx_right_in[11]:35 1.58857e-05 +42 chanx_right_in[13]:18 chanx_right_in[11]:23 5.825397e-06 +43 chanx_right_in[13]:18 chanx_right_in[11]:31 5.006127e-05 +44 chanx_right_in[13]:18 chanx_right_in[11]:32 0.0001751904 +45 chanx_right_in[13]:17 chanx_right_in[17]:20 0.0002410254 +46 chanx_right_in[13]:22 chanx_right_in[17]:24 4.67519e-05 +47 chanx_right_in[13]:22 chanx_right_in[17]:20 1.58734e-05 +48 chanx_right_in[13]:23 chanx_right_in[17]:24 1.58734e-05 +49 chanx_right_in[13]:23 chanx_right_in[17]:25 7.476604e-06 +50 chanx_right_in[13]:24 chanx_right_in[17]:25 9.160053e-06 +51 chanx_right_in[13]:25 chanx_right_in[17]:26 9.160053e-06 +52 chanx_right_in[13]:18 chanx_right_in[17]:24 0.0002410254 +53 chanx_right_in[13]:18 chanx_right_in[17]:20 3.92753e-05 +54 chanx_right_in[13]:17 chanx_right_in[19]:25 6.670839e-06 +55 chanx_right_in[13]:17 chanx_right_in[19]:23 0.0002106541 +56 chanx_right_in[13]:17 chanx_right_in[19]:22 0.0008174659 +57 chanx_right_in[13]:14 chanx_right_in[19]:14 2.251505e-06 +58 chanx_right_in[13]:22 chanx_right_in[19]:30 2.501787e-05 +59 chanx_right_in[13]:22 chanx_right_in[19]:31 0.0001347619 +60 chanx_right_in[13]:7 chanx_right_in[19]:22 0.0002106541 +61 chanx_right_in[13]:23 chanx_right_in[19]:31 2.501787e-05 +62 chanx_right_in[13]:18 chanx_right_in[19]:30 0.0001347619 +63 chanx_right_in[13]:18 chanx_right_in[19]:23 0.0008174659 +64 chanx_right_in[13]:18 chanx_right_in[19]:26 6.670839e-06 +65 chanx_right_in[13]:15 chanx_right_in[19]:20 2.251505e-06 +66 chanx_right_in[13]:16 mux_tree_tapbuf_size10_4_sram[0]:26 9.859447e-05 +67 chanx_right_in[13]:14 mux_tree_tapbuf_size10_4_sram[0]:25 0.0004605436 +68 chanx_right_in[13]:15 mux_tree_tapbuf_size10_4_sram[0]:25 9.859447e-05 +69 chanx_right_in[13]:15 mux_tree_tapbuf_size10_4_sram[0]:26 0.0004605436 +70 chanx_right_in[13] chanx_right_out[12] 0.0002538614 +71 chanx_right_in[13]:26 chanx_right_out[12]:2 0.0002538614 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:26 0.0016779 +1 chanx_right_in[13]:17 chanx_right_in[13]:16 0.00341 +2 chanx_right_in[13]:17 chanx_right_in[13]:7 0.0005753583 +3 chanx_right_in[13]:16 chanx_right_in[13]:15 0.0008205416 +4 chanx_right_in[13]:13 chanx_right_in[13]:12 0.0002839583 +5 chanx_right_in[13]:14 chanx_right_in[13]:13 0.00341 +6 chanx_right_in[13]:11 chanx_right_in[13]:10 0.000515625 +7 chanx_right_in[13]:12 chanx_right_in[13]:11 0.00341 +8 chanx_right_in[13]:9 chanx_right_in[13]:8 0.001979911 +9 chanx_right_in[13]:10 chanx_right_in[13]:9 0.0045 +10 chanx_right_in[13]:8 BUFT_P_101:A 0.152 +11 chanx_right_in[13]:21 chanx_right_in[13]:20 0.0001634615 +12 chanx_right_in[13]:22 chanx_right_in[13]:21 0.00341 +13 chanx_right_in[13]:22 chanx_right_in[13]:18 0.002544267 +14 chanx_right_in[13]:19 mux_bottom_ipin_13\/mux_l2_in_2_:A1 0.152 +15 chanx_right_in[13]:20 chanx_right_in[13]:19 0.0045 +16 chanx_right_in[13]:6 chanx_right_in[13]:5 0.0001634615 +17 chanx_right_in[13]:7 chanx_right_in[13]:6 0.00341 +18 chanx_right_in[13]:4 mux_bottom_ipin_9\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[13]:5 chanx_right_in[13]:4 0.0045 +20 chanx_right_in[13]:23 chanx_right_in[13]:22 0.0002851333 +21 chanx_right_in[13]:24 chanx_right_in[13]:23 0.00341 +22 chanx_right_in[13]:26 chanx_right_in[13]:25 0.00341 +23 chanx_right_in[13]:25 chanx_right_in[13]:24 0.001702183 +24 chanx_right_in[13]:18 chanx_right_in[13]:17 0.007833333 +25 chanx_right_in[13]:15 chanx_right_in[13]:14 0.007806308 + +*END + +*D_NET chanx_right_in[18] 0.02254058 //LENGTH 136.510 LUMPCC 0.01019364 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 103.650 43.520 +*I mux_bottom_ipin_14\/mux_l2_in_3_:A1 I *L 0.00198 *C 88.320 41.820 +*I mux_bottom_ipin_6\/mux_l2_in_3_:A1 I *L 0.00198 *C 92.920 39.780 +*I FTB_39__38:A I *L 0.001767 *C 16.100 72.080 +*I mux_bottom_ipin_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 17.385 41.820 +*N chanx_right_in[18]:5 *C 17.385 41.820 +*N chanx_right_in[18]:6 *C 17.480 41.820 +*N chanx_right_in[18]:7 *C 16.062 72.080 +*N chanx_right_in[18]:8 *C 13.845 72.080 +*N chanx_right_in[18]:9 *C 13.800 72.035 +*N chanx_right_in[18]:10 *C 13.800 70.778 +*N chanx_right_in[18]:11 *C 13.808 70.720 +*N chanx_right_in[18]:12 *C 17.460 70.720 +*N chanx_right_in[18]:13 *C 17.480 70.713 +*N chanx_right_in[18]:14 *C 17.480 41.828 +*N chanx_right_in[18]:15 *C 17.488 41.818 +*N chanx_right_in[18]:16 *C 17.510 41.480 +*N chanx_right_in[18]:17 *C 67.330 41.480 +*N chanx_right_in[18]:18 *C 92.883 39.780 +*N chanx_right_in[18]:19 *C 92.460 39.780 +*N chanx_right_in[18]:20 *C 92.460 39.100 +*N chanx_right_in[18]:21 *C 92.045 39.100 +*N chanx_right_in[18]:22 *C 92.000 39.145 +*N chanx_right_in[18]:23 *C 88.358 41.820 +*N chanx_right_in[18]:24 *C 91.955 41.820 +*N chanx_right_in[18]:25 *C 92.000 41.820 +*N chanx_right_in[18]:26 *C 92.000 41.422 +*N chanx_right_in[18]:27 *C 92.000 41.480 +*N chanx_right_in[18]:28 *C 101.180 41.480 +*N chanx_right_in[18]:29 *C 101.200 41.488 +*N chanx_right_in[18]:30 *C 101.200 43.513 +*N chanx_right_in[18]:31 *C 101.220 43.520 + +*CAP +0 chanx_right_in[18] 0.0001374847 +1 mux_bottom_ipin_14\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_ipin_6\/mux_l2_in_3_:A1 1e-06 +3 FTB_39__38:A 1e-06 +4 mux_bottom_ipin_8\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[18]:5 2.75581e-05 +6 chanx_right_in[18]:6 3.495627e-05 +7 chanx_right_in[18]:7 0.000208692 +8 chanx_right_in[18]:8 0.000208692 +9 chanx_right_in[18]:9 0.0001132134 +10 chanx_right_in[18]:10 0.0001132134 +11 chanx_right_in[18]:11 0.0002391427 +12 chanx_right_in[18]:12 0.0002391427 +13 chanx_right_in[18]:13 0.0015942 +14 chanx_right_in[18]:14 0.0015942 +15 chanx_right_in[18]:15 3.661292e-05 +16 chanx_right_in[18]:16 0.002137217 +17 chanx_right_in[18]:17 0.002805172 +18 chanx_right_in[18]:18 5.043993e-05 +19 chanx_right_in[18]:19 0.0001008528 +20 chanx_right_in[18]:20 9.731462e-05 +21 chanx_right_in[18]:21 4.69018e-05 +22 chanx_right_in[18]:22 0.0001722061 +23 chanx_right_in[18]:23 0.0001664603 +24 chanx_right_in[18]:24 0.0001664603 +25 chanx_right_in[18]:25 5.821311e-05 +26 chanx_right_in[18]:26 0.0001963403 +27 chanx_right_in[18]:27 0.001053204 +28 chanx_right_in[18]:28 0.0003486363 +29 chanx_right_in[18]:29 0.0001294651 +30 chanx_right_in[18]:30 0.0001294651 +31 chanx_right_in[18]:31 0.0001374847 +32 chanx_right_in[18]:24 chanx_left_in[9]:6 0.0001456496 +33 chanx_right_in[18]:23 chanx_left_in[9]:7 0.0001456496 +34 chanx_right_in[18]:16 chanx_left_in[9]:18 0.0001391047 +35 chanx_right_in[18]:17 chanx_left_in[9]:17 0.0001391047 +36 chanx_right_in[18]:27 chanx_left_in[15]:9 0.001350688 +37 chanx_right_in[18]:27 chanx_left_in[15]:14 0.0002083775 +38 chanx_right_in[18]:28 chanx_left_in[15]:9 0.0002083775 +39 chanx_right_in[18]:16 chanx_left_in[15]:14 0.0006364746 +40 chanx_right_in[18]:16 chanx_left_in[15]:15 0.0003372226 +41 chanx_right_in[18]:16 chanx_left_in[15]:19 7.394042e-06 +42 chanx_right_in[18]:16 chanx_left_in[15]:29 2.667205e-07 +43 chanx_right_in[18]:17 chanx_left_in[15]:9 0.0006364746 +44 chanx_right_in[18]:17 chanx_left_in[15]:14 0.00168791 +45 chanx_right_in[18]:17 chanx_left_in[15]:18 7.394042e-06 +46 chanx_right_in[18]:17 chanx_left_in[15]:28 2.667205e-07 +47 chanx_right_in[18] chanx_right_in[9] 3.346724e-05 +48 chanx_right_in[18] chanx_right_in[9]:24 4.397969e-06 +49 chanx_right_in[18]:15 chanx_right_in[9]:6 5.960419e-06 +50 chanx_right_in[18]:27 chanx_right_in[9]:23 0.0002124295 +51 chanx_right_in[18]:27 chanx_right_in[9]:24 0.0005088898 +52 chanx_right_in[18]:28 chanx_right_in[9]:24 0.0002124295 +53 chanx_right_in[18]:31 chanx_right_in[9]:23 4.397969e-06 +54 chanx_right_in[18]:31 chanx_right_in[9]:27 3.346724e-05 +55 chanx_right_in[18]:16 chanx_right_in[9]:18 5.960419e-06 +56 chanx_right_in[18]:16 chanx_right_in[9]:19 0.0007831259 +57 chanx_right_in[18]:16 chanx_right_in[9]:23 0.0002410321 +58 chanx_right_in[18]:17 chanx_right_in[9]:23 0.001292016 +59 chanx_right_in[18]:17 chanx_right_in[9]:24 0.0002410321 +60 chanx_right_in[18]:14 chanx_right_in[19]:14 0.0003123385 +61 chanx_right_in[18]:14 chanx_right_in[19]:20 7.845973e-05 +62 chanx_right_in[18]:13 chanx_right_in[19]:21 7.845973e-05 +63 chanx_right_in[18]:13 chanx_right_in[19]:20 0.0003123385 +64 chanx_right_in[18]:12 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.154232e-05 +65 chanx_right_in[18]:11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 9.154232e-05 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:31 0.0003807 +1 chanx_right_in[18]:15 chanx_right_in[18]:14 0.00341 +2 chanx_right_in[18]:15 chanx_right_in[18]:6 0.00341 +3 chanx_right_in[18]:14 chanx_right_in[18]:13 0.004525316 +4 chanx_right_in[18]:12 chanx_right_in[18]:11 0.000572225 +5 chanx_right_in[18]:13 chanx_right_in[18]:12 0.00341 +6 chanx_right_in[18]:10 chanx_right_in[18]:9 0.001122768 +7 chanx_right_in[18]:11 chanx_right_in[18]:10 0.00341 +8 chanx_right_in[18]:8 chanx_right_in[18]:7 0.001979911 +9 chanx_right_in[18]:9 chanx_right_in[18]:8 0.0045 +10 chanx_right_in[18]:7 FTB_39__38:A 0.152 +11 chanx_right_in[18]:26 chanx_right_in[18]:25 0.0001911058 +12 chanx_right_in[18]:26 chanx_right_in[18]:22 0.002033482 +13 chanx_right_in[18]:27 chanx_right_in[18]:26 0.00341 +14 chanx_right_in[18]:27 chanx_right_in[18]:17 0.003864967 +15 chanx_right_in[18]:21 chanx_right_in[18]:20 0.0003705357 +16 chanx_right_in[18]:22 chanx_right_in[18]:21 0.0045 +17 chanx_right_in[18]:18 mux_bottom_ipin_6\/mux_l2_in_3_:A1 0.152 +18 chanx_right_in[18]:24 chanx_right_in[18]:23 0.003212054 +19 chanx_right_in[18]:25 chanx_right_in[18]:24 0.0045 +20 chanx_right_in[18]:23 mux_bottom_ipin_14\/mux_l2_in_3_:A1 0.152 +21 chanx_right_in[18]:6 chanx_right_in[18]:5 0.0045 +22 chanx_right_in[18]:5 mux_bottom_ipin_8\/mux_l2_in_3_:A1 0.152 +23 chanx_right_in[18]:28 chanx_right_in[18]:27 0.0014382 +24 chanx_right_in[18]:29 chanx_right_in[18]:28 0.00341 +25 chanx_right_in[18]:31 chanx_right_in[18]:30 0.00341 +26 chanx_right_in[18]:30 chanx_right_in[18]:29 0.00031725 +27 chanx_right_in[18]:20 chanx_right_in[18]:19 0.000607143 +28 chanx_right_in[18]:19 chanx_right_in[18]:18 0.0003772322 +29 chanx_right_in[18]:16 chanx_right_in[18]:15 4.66544e-05 +30 chanx_right_in[18]:17 chanx_right_in[18]:16 0.007805133 + +*END + +*D_NET ropt_net_132 0.00673258 //LENGTH 57.425 LUMPCC 0.0004627533 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l4_in_0_:X O *L 0 *C 48.015 50.660 +*I ropt_mt_inst_729:A I *L 0.001766 *C 21.160 69.360 +*N ropt_net_132:2 *C 21.183 69.388 +*N ropt_net_132:3 *C 21.195 69.700 +*N ropt_net_132:4 *C 22.495 69.700 +*N ropt_net_132:5 *C 22.540 69.745 +*N ropt_net_132:6 *C 22.540 74.075 +*N ropt_net_132:7 *C 22.585 74.120 +*N ropt_net_132:8 *C 36.295 74.120 +*N ropt_net_132:9 *C 36.340 74.075 +*N ropt_net_132:10 *C 36.340 66.685 +*N ropt_net_132:11 *C 36.385 66.640 +*N ropt_net_132:12 *C 46.875 66.640 +*N ropt_net_132:13 *C 46.920 66.595 +*N ropt_net_132:14 *C 46.920 50.705 +*N ropt_net_132:15 *C 46.965 50.660 +*N ropt_net_132:16 *C 47.977 50.660 + +*CAP +0 mux_bottom_ipin_5\/mux_l4_in_0_:X 1e-06 +1 ropt_mt_inst_729:A 1e-06 +2 ropt_net_132:2 2.936582e-05 +3 ropt_net_132:3 0.0001060571 +4 ropt_net_132:4 7.669123e-05 +5 ropt_net_132:5 0.0002392343 +6 ropt_net_132:6 0.0002392343 +7 ropt_net_132:7 0.0007552715 +8 ropt_net_132:8 0.0007552715 +9 ropt_net_132:9 0.0004814434 +10 ropt_net_132:10 0.0004814434 +11 ropt_net_132:11 0.0005788991 +12 ropt_net_132:12 0.0005788991 +13 ropt_net_132:13 0.0008708631 +14 ropt_net_132:14 0.0008708631 +15 ropt_net_132:15 0.0001021453 +16 ropt_net_132:16 0.0001021453 +17 ropt_net_132:7 ropt_net_135:6 0.0001799068 +18 ropt_net_132:8 ropt_net_135:7 0.0001799068 +19 ropt_net_132:4 ropt_net_180:6 4.766947e-05 +20 ropt_net_132:5 ropt_net_180:4 3.800309e-06 +21 ropt_net_132:6 ropt_net_180:3 3.800309e-06 +22 ropt_net_132:3 ropt_net_180:5 4.766947e-05 + +*RES +0 mux_bottom_ipin_5\/mux_l4_in_0_:X ropt_net_132:16 0.152 +1 ropt_net_132:2 ropt_mt_inst_729:A 0.152 +2 ropt_net_132:4 ropt_net_132:3 0.001160714 +3 ropt_net_132:5 ropt_net_132:4 0.0045 +4 ropt_net_132:7 ropt_net_132:6 0.0045 +5 ropt_net_132:6 ropt_net_132:5 0.003866071 +6 ropt_net_132:8 ropt_net_132:7 0.01224107 +7 ropt_net_132:9 ropt_net_132:8 0.0045 +8 ropt_net_132:11 ropt_net_132:10 0.0045 +9 ropt_net_132:10 ropt_net_132:9 0.006598215 +10 ropt_net_132:12 ropt_net_132:11 0.009366072 +11 ropt_net_132:13 ropt_net_132:12 0.0045 +12 ropt_net_132:15 ropt_net_132:14 0.0045 +13 ropt_net_132:14 ropt_net_132:13 0.0141875 +14 ropt_net_132:16 ropt_net_132:15 0.0009040179 +15 ropt_net_132:3 ropt_net_132:2 0.0002111487 + +*END + +*D_NET top_grid_pin_30_[0] 0.0007172813 //LENGTH 6.090 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 79.120 72.080 +*P top_grid_pin_30_[0] O *L 0.7423 *C 76.360 74.835 +*N top_grid_pin_30_[0]:2 *C 76.360 72.805 +*N top_grid_pin_30_[0]:3 *C 76.405 72.760 +*N top_grid_pin_30_[0]:4 *C 79.120 72.760 +*N top_grid_pin_30_[0]:5 *C 79.120 72.080 + +*CAP +0 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 top_grid_pin_30_[0] 0.0001193087 +2 top_grid_pin_30_[0]:2 0.0001193087 +3 top_grid_pin_30_[0]:3 0.0001859445 +4 top_grid_pin_30_[0]:4 0.0002264028 +5 top_grid_pin_30_[0]:5 6.531669e-05 + +*RES +0 mux_bottom_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X top_grid_pin_30_[0]:5 0.152 +1 top_grid_pin_30_[0]:3 top_grid_pin_30_[0]:2 0.0045 +2 top_grid_pin_30_[0]:2 top_grid_pin_30_[0] 0.0018125 +3 top_grid_pin_30_[0]:5 top_grid_pin_30_[0]:4 0.0006071429 +4 top_grid_pin_30_[0]:4 top_grid_pin_30_[0]:3 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.004159077 //LENGTH 30.865 LUMPCC 0.0008497022 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 67.005 12.240 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 59.975 26.180 +*I mux_bottom_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 68.180 25.840 +*I mux_bottom_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 61.280 18.360 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 61.180 18.360 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 61.150 18.330 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 68.180 25.840 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 68.080 26.180 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 60.013 26.180 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 60.720 26.180 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 60.720 26.135 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 60.720 18.020 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 61.135 18.020 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 61.180 15.345 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 61.225 15.300 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 66.655 15.300 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 66.700 15.255 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 66.700 12.285 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 66.700 12.240 +*N mux_tree_tapbuf_size10_0_sram[2]:19 *C 67.005 12.240 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_0\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_ipin_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 3.379449e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 4.101334e-05 +6 mux_tree_tapbuf_size10_0_sram[2]:6 5.673626e-05 +7 mux_tree_tapbuf_size10_0_sram[2]:7 0.0003745967 +8 mux_tree_tapbuf_size10_0_sram[2]:8 6.190706e-05 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.0004411583 +10 mux_tree_tapbuf_size10_0_sram[2]:10 0.0003205821 +11 mux_tree_tapbuf_size10_0_sram[2]:11 0.0003526259 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0002523317 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0001792745 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.00034089 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.00034089 +16 mux_tree_tapbuf_size10_0_sram[2]:16 0.0001986457 +17 mux_tree_tapbuf_size10_0_sram[2]:17 0.0001986457 +18 mux_tree_tapbuf_size10_0_sram[2]:18 5.819535e-05 +19 mux_tree_tapbuf_size10_0_sram[2]:19 5.408714e-05 +20 mux_tree_tapbuf_size10_0_sram[2]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002062478 +21 mux_tree_tapbuf_size10_0_sram[2]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002062478 +22 mux_tree_tapbuf_size10_0_sram[2]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.226172e-06 +23 mux_tree_tapbuf_size10_0_sram[2]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002163771 +24 mux_tree_tapbuf_size10_0_sram[2]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002163771 +25 mux_tree_tapbuf_size10_0_sram[2]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.226172e-06 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +2 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.002388393 +3 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.004848215 +4 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.0045 +5 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:17 0.0045 +6 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.002651786 +7 mux_tree_tapbuf_size10_0_sram[2]:19 mux_tree_tapbuf_size10_0_sram[2]:18 0.0001657609 +8 mux_tree_tapbuf_size10_0_sram[2]:6 mux_bottom_ipin_0\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size10_0_sram[2]:8 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.0006316964 +11 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:7 0.006571429 +12 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.0045 +13 mux_tree_tapbuf_size10_0_sram[2]:4 mux_bottom_ipin_0\/mux_l3_in_1_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.0045 +15 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.0003035715 +16 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.007245536 +17 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.0003705357 +18 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:5 0.00019375 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[0] 0.01059624 //LENGTH 69.535 LUMPCC 0.003925029 DR + +*CONN +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 30.665 66.300 +*I mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 21.795 28.220 +*I mux_bottom_ipin_8\/mux_l1_in_0_:S I *L 0.00357 *C 17.360 25.500 +*I mux_bottom_ipin_8\/mux_l1_in_1_:S I *L 0.00357 *C 15.080 25.840 +*I mux_bottom_ipin_8\/mux_l1_in_2_:S I *L 0.00357 *C 14.620 23.120 +*N mux_tree_tapbuf_size10_4_sram[0]:5 *C 22.600 32.640 +*N mux_tree_tapbuf_size10_4_sram[0]:6 *C 14.658 23.120 +*N mux_tree_tapbuf_size10_4_sram[0]:7 *C 15.135 23.120 +*N mux_tree_tapbuf_size10_4_sram[0]:8 *C 15.180 23.165 +*N mux_tree_tapbuf_size10_4_sram[0]:9 *C 15.080 25.840 +*N mux_tree_tapbuf_size10_4_sram[0]:10 *C 15.180 25.840 +*N mux_tree_tapbuf_size10_4_sram[0]:11 *C 17.360 25.500 +*N mux_tree_tapbuf_size10_4_sram[0]:12 *C 17.480 25.840 +*N mux_tree_tapbuf_size10_4_sram[0]:13 *C 18.860 25.840 +*N mux_tree_tapbuf_size10_4_sram[0]:14 *C 18.860 26.520 +*N mux_tree_tapbuf_size10_4_sram[0]:15 *C 15.225 26.520 +*N mux_tree_tapbuf_size10_4_sram[0]:16 *C 15.180 26.520 +*N mux_tree_tapbuf_size10_4_sram[0]:17 *C 15.180 27.835 +*N mux_tree_tapbuf_size10_4_sram[0]:18 *C 15.225 27.880 +*N mux_tree_tapbuf_size10_4_sram[0]:19 *C 21.620 27.880 +*N mux_tree_tapbuf_size10_4_sram[0]:20 *C 21.832 28.220 +*N mux_tree_tapbuf_size10_4_sram[0]:21 *C 22.955 28.220 +*N mux_tree_tapbuf_size10_4_sram[0]:22 *C 23.000 28.265 +*N mux_tree_tapbuf_size10_4_sram[0]:23 *C 23.000 32.583 +*N mux_tree_tapbuf_size10_4_sram[0]:24 *C 23.000 32.640 +*N mux_tree_tapbuf_size10_4_sram[0]:25 *C 23.000 32.648 +*N mux_tree_tapbuf_size10_4_sram[0]:26 *C 23.000 65.273 +*N mux_tree_tapbuf_size10_4_sram[0]:27 *C 23.020 65.280 +*N mux_tree_tapbuf_size10_4_sram[0]:28 *C 27.133 65.280 +*N mux_tree_tapbuf_size10_4_sram[0]:29 *C 27.140 65.338 +*N mux_tree_tapbuf_size10_4_sram[0]:30 *C 27.140 66.255 +*N mux_tree_tapbuf_size10_4_sram[0]:31 *C 27.185 66.300 +*N mux_tree_tapbuf_size10_4_sram[0]:32 *C 30.628 66.300 + +*CAP +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_8\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_ipin_8\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_ipin_8\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_4_sram[0]:5 8.577433e-05 +6 mux_tree_tapbuf_size10_4_sram[0]:6 6.171123e-05 +7 mux_tree_tapbuf_size10_4_sram[0]:7 6.171123e-05 +8 mux_tree_tapbuf_size10_4_sram[0]:8 0.0001276814 +9 mux_tree_tapbuf_size10_4_sram[0]:9 2.896292e-05 +10 mux_tree_tapbuf_size10_4_sram[0]:10 0.0001871693 +11 mux_tree_tapbuf_size10_4_sram[0]:11 5.822969e-05 +12 mux_tree_tapbuf_size10_4_sram[0]:12 0.0001240973 +13 mux_tree_tapbuf_size10_4_sram[0]:13 0.0001395251 +14 mux_tree_tapbuf_size10_4_sram[0]:14 0.0003385304 +15 mux_tree_tapbuf_size10_4_sram[0]:15 0.0002947689 +16 mux_tree_tapbuf_size10_4_sram[0]:16 0.000123754 +17 mux_tree_tapbuf_size10_4_sram[0]:17 6.501275e-05 +18 mux_tree_tapbuf_size10_4_sram[0]:18 0.0004586001 +19 mux_tree_tapbuf_size10_4_sram[0]:19 0.0004863432 +20 mux_tree_tapbuf_size10_4_sram[0]:20 0.0001452523 +21 mux_tree_tapbuf_size10_4_sram[0]:21 0.0001175091 +22 mux_tree_tapbuf_size10_4_sram[0]:22 0.0002661195 +23 mux_tree_tapbuf_size10_4_sram[0]:23 0.0002661195 +24 mux_tree_tapbuf_size10_4_sram[0]:24 8.577433e-05 +25 mux_tree_tapbuf_size10_4_sram[0]:25 0.001033434 +26 mux_tree_tapbuf_size10_4_sram[0]:26 0.001033434 +27 mux_tree_tapbuf_size10_4_sram[0]:27 0.0002284022 +28 mux_tree_tapbuf_size10_4_sram[0]:28 0.0002284022 +29 mux_tree_tapbuf_size10_4_sram[0]:29 8.979991e-05 +30 mux_tree_tapbuf_size10_4_sram[0]:30 8.979991e-05 +31 mux_tree_tapbuf_size10_4_sram[0]:31 0.000220148 +32 mux_tree_tapbuf_size10_4_sram[0]:32 0.000220148 +33 mux_tree_tapbuf_size10_4_sram[0]:25 chanx_right_in[13]:14 0.0004605436 +34 mux_tree_tapbuf_size10_4_sram[0]:25 chanx_right_in[13]:15 9.859447e-05 +35 mux_tree_tapbuf_size10_4_sram[0]:26 chanx_right_in[13]:15 0.0004605436 +36 mux_tree_tapbuf_size10_4_sram[0]:26 chanx_right_in[13]:16 9.859447e-05 +37 mux_tree_tapbuf_size10_4_sram[0]:22 chanx_right_in[14]:16 4.629596e-08 +38 mux_tree_tapbuf_size10_4_sram[0]:23 chanx_right_in[14]:15 4.629596e-08 +39 mux_tree_tapbuf_size10_4_sram[0]:25 chanx_right_in[14]:12 0.001030733 +40 mux_tree_tapbuf_size10_4_sram[0]:26 chanx_right_in[14]:11 0.001030733 +41 mux_tree_tapbuf_size10_4_sram[0]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.663281e-05 +42 mux_tree_tapbuf_size10_4_sram[0]:10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.750469e-05 +43 mux_tree_tapbuf_size10_4_sram[0]:17 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.730262e-05 +44 mux_tree_tapbuf_size10_4_sram[0]:16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.750469e-05 +45 mux_tree_tapbuf_size10_4_sram[0]:16 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.730262e-05 +46 mux_tree_tapbuf_size10_4_sram[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.076672e-06 +47 mux_tree_tapbuf_size10_4_sram[0]:8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.663281e-05 +48 mux_tree_tapbuf_size10_4_sram[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.076672e-06 +49 mux_tree_tapbuf_size10_4_sram[0]:27 mem_bottom_ipin_15/net_net_75:6 0.0002474861 +50 mux_tree_tapbuf_size10_4_sram[0]:28 mem_bottom_ipin_15/net_net_75:7 0.0002474861 +51 mux_tree_tapbuf_size10_4_sram[0]:31 mem_bottom_ipin_15/net_net_75:6 5.594386e-06 +52 mux_tree_tapbuf_size10_4_sram[0]:32 mem_bottom_ipin_15/net_net_75:7 5.594386e-06 + +*RES +0 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_4_sram[0]:32 0.152 +1 mux_tree_tapbuf_size10_4_sram[0]:9 mux_bottom_ipin_8\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[0]:9 0.0045 +3 mux_tree_tapbuf_size10_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[0]:8 0.002388393 +4 mux_tree_tapbuf_size10_4_sram[0]:18 mux_tree_tapbuf_size10_4_sram[0]:17 0.0045 +5 mux_tree_tapbuf_size10_4_sram[0]:17 mux_tree_tapbuf_size10_4_sram[0]:16 0.001174107 +6 mux_tree_tapbuf_size10_4_sram[0]:11 mux_bottom_ipin_8\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_4_sram[0]:15 mux_tree_tapbuf_size10_4_sram[0]:14 0.003245536 +8 mux_tree_tapbuf_size10_4_sram[0]:16 mux_tree_tapbuf_size10_4_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size10_4_sram[0]:16 mux_tree_tapbuf_size10_4_sram[0]:10 0.0006071429 +10 mux_tree_tapbuf_size10_4_sram[0]:20 mem_bottom_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size10_4_sram[0]:20 mux_tree_tapbuf_size10_4_sram[0]:19 0.0003035715 +12 mux_tree_tapbuf_size10_4_sram[0]:21 mux_tree_tapbuf_size10_4_sram[0]:20 0.001002232 +13 mux_tree_tapbuf_size10_4_sram[0]:22 mux_tree_tapbuf_size10_4_sram[0]:21 0.0045 +14 mux_tree_tapbuf_size10_4_sram[0]:23 mux_tree_tapbuf_size10_4_sram[0]:22 0.003854911 +15 mux_tree_tapbuf_size10_4_sram[0]:24 mux_tree_tapbuf_size10_4_sram[0]:23 0.00341 +16 mux_tree_tapbuf_size10_4_sram[0]:24 mux_tree_tapbuf_size10_4_sram[0]:5 5.696969e-05 +17 mux_tree_tapbuf_size10_4_sram[0]:25 mux_tree_tapbuf_size10_4_sram[0]:24 0.00341 +18 mux_tree_tapbuf_size10_4_sram[0]:27 mux_tree_tapbuf_size10_4_sram[0]:26 0.00341 +19 mux_tree_tapbuf_size10_4_sram[0]:26 mux_tree_tapbuf_size10_4_sram[0]:25 0.00511125 +20 mux_tree_tapbuf_size10_4_sram[0]:29 mux_tree_tapbuf_size10_4_sram[0]:28 0.00341 +21 mux_tree_tapbuf_size10_4_sram[0]:28 mux_tree_tapbuf_size10_4_sram[0]:27 0.0006442916 +22 mux_tree_tapbuf_size10_4_sram[0]:31 mux_tree_tapbuf_size10_4_sram[0]:30 0.0045 +23 mux_tree_tapbuf_size10_4_sram[0]:30 mux_tree_tapbuf_size10_4_sram[0]:29 0.0008191965 +24 mux_tree_tapbuf_size10_4_sram[0]:32 mux_tree_tapbuf_size10_4_sram[0]:31 0.003073661 +25 mux_tree_tapbuf_size10_4_sram[0]:7 mux_tree_tapbuf_size10_4_sram[0]:6 0.0004263393 +26 mux_tree_tapbuf_size10_4_sram[0]:8 mux_tree_tapbuf_size10_4_sram[0]:7 0.0045 +27 mux_tree_tapbuf_size10_4_sram[0]:6 mux_bottom_ipin_8\/mux_l1_in_2_:S 0.152 +28 mux_tree_tapbuf_size10_4_sram[0]:14 mux_tree_tapbuf_size10_4_sram[0]:13 0.0006071429 +29 mux_tree_tapbuf_size10_4_sram[0]:19 mux_tree_tapbuf_size10_4_sram[0]:18 0.005709822 +30 mux_tree_tapbuf_size10_4_sram[0]:12 mux_tree_tapbuf_size10_4_sram[0]:11 0.0003035715 +31 mux_tree_tapbuf_size10_4_sram[0]:13 mux_tree_tapbuf_size10_4_sram[0]:12 0.001232143 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[0] 0.004639975 //LENGTH 38.755 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 92.305 26.180 +*I mux_bottom_ipin_13\/mux_l1_in_2_:S I *L 0.00357 *C 89.800 36.040 +*I mux_bottom_ipin_13\/mux_l1_in_1_:S I *L 0.00357 *C 87.860 50.490 +*I mux_bottom_ipin_13\/mux_l1_in_0_:S I *L 0.00357 *C 88.880 53.040 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.335 55.420 +*N mux_tree_tapbuf_size10_7_sram[0]:5 *C 90.335 55.420 +*N mux_tree_tapbuf_size10_7_sram[0]:6 *C 90.620 55.420 +*N mux_tree_tapbuf_size10_7_sram[0]:7 *C 90.620 55.375 +*N mux_tree_tapbuf_size10_7_sram[0]:8 *C 88.918 53.040 +*N mux_tree_tapbuf_size10_7_sram[0]:9 *C 90.575 53.040 +*N mux_tree_tapbuf_size10_7_sram[0]:10 *C 90.620 53.040 +*N mux_tree_tapbuf_size10_7_sram[0]:11 *C 90.620 50.320 +*N mux_tree_tapbuf_size10_7_sram[0]:12 *C 89.745 50.320 +*N mux_tree_tapbuf_size10_7_sram[0]:13 *C 89.700 49.885 +*N mux_tree_tapbuf_size10_7_sram[0]:14 *C 87.860 50.490 +*N mux_tree_tapbuf_size10_7_sram[0]:15 *C 87.860 49.980 +*N mux_tree_tapbuf_size10_7_sram[0]:16 *C 89.655 49.980 +*N mux_tree_tapbuf_size10_7_sram[0]:17 *C 89.730 50.010 +*N mux_tree_tapbuf_size10_7_sram[0]:18 *C 89.700 36.040 +*N mux_tree_tapbuf_size10_7_sram[0]:19 *C 89.700 36.040 +*N mux_tree_tapbuf_size10_7_sram[0]:20 *C 89.700 26.225 +*N mux_tree_tapbuf_size10_7_sram[0]:21 *C 89.745 26.180 +*N mux_tree_tapbuf_size10_7_sram[0]:22 *C 92.267 26.180 + +*CAP +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_13\/mux_l1_in_2_:S 1e-06 +2 mux_bottom_ipin_13\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_ipin_13\/mux_l1_in_0_:S 1e-06 +4 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_7_sram[0]:5 5.972685e-05 +6 mux_tree_tapbuf_size10_7_sram[0]:6 6.133242e-05 +7 mux_tree_tapbuf_size10_7_sram[0]:7 0.0001449689 +8 mux_tree_tapbuf_size10_7_sram[0]:8 0.0001486957 +9 mux_tree_tapbuf_size10_7_sram[0]:9 0.0001486957 +10 mux_tree_tapbuf_size10_7_sram[0]:10 0.0003282066 +11 mux_tree_tapbuf_size10_7_sram[0]:11 0.0002054075 +12 mux_tree_tapbuf_size10_7_sram[0]:12 7.598323e-05 +13 mux_tree_tapbuf_size10_7_sram[0]:13 8.762056e-06 +14 mux_tree_tapbuf_size10_7_sram[0]:14 6.46963e-05 +15 mux_tree_tapbuf_size10_7_sram[0]:15 0.0001701439 +16 mux_tree_tapbuf_size10_7_sram[0]:16 0.0001337472 +17 mux_tree_tapbuf_size10_7_sram[0]:17 0.0008087546 +18 mux_tree_tapbuf_size10_7_sram[0]:18 3.375308e-05 +19 mux_tree_tapbuf_size10_7_sram[0]:19 0.001367893 +20 mux_tree_tapbuf_size10_7_sram[0]:20 0.0005573161 +21 mux_tree_tapbuf_size10_7_sram[0]:21 0.000158446 +22 mux_tree_tapbuf_size10_7_sram[0]:22 0.000158446 + +*RES +0 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_7_sram[0]:22 0.152 +1 mux_tree_tapbuf_size10_7_sram[0]:21 mux_tree_tapbuf_size10_7_sram[0]:20 0.0045 +2 mux_tree_tapbuf_size10_7_sram[0]:20 mux_tree_tapbuf_size10_7_sram[0]:19 0.008763393 +3 mux_tree_tapbuf_size10_7_sram[0]:22 mux_tree_tapbuf_size10_7_sram[0]:21 0.002252232 +4 mux_tree_tapbuf_size10_7_sram[0]:18 mux_bottom_ipin_13\/mux_l1_in_2_:S 0.152 +5 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:18 0.0045 +6 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:17 0.01247322 +7 mux_tree_tapbuf_size10_7_sram[0]:14 mux_bottom_ipin_13\/mux_l1_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_7_sram[0]:16 mux_tree_tapbuf_size10_7_sram[0]:15 0.001602679 +9 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:16 0.0045 +10 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:13 0.0001116071 +11 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:12 0.00019375 +12 mux_tree_tapbuf_size10_7_sram[0]:6 mux_tree_tapbuf_size10_7_sram[0]:5 0.0001548913 +13 mux_tree_tapbuf_size10_7_sram[0]:7 mux_tree_tapbuf_size10_7_sram[0]:6 0.0045 +14 mux_tree_tapbuf_size10_7_sram[0]:5 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size10_7_sram[0]:9 mux_tree_tapbuf_size10_7_sram[0]:8 0.001479911 +16 mux_tree_tapbuf_size10_7_sram[0]:10 mux_tree_tapbuf_size10_7_sram[0]:9 0.0045 +17 mux_tree_tapbuf_size10_7_sram[0]:10 mux_tree_tapbuf_size10_7_sram[0]:7 0.002084821 +18 mux_tree_tapbuf_size10_7_sram[0]:8 mux_bottom_ipin_13\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_7_sram[0]:15 mux_tree_tapbuf_size10_7_sram[0]:14 0.0004553572 +20 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:11 0.00078125 +21 mux_tree_tapbuf_size10_7_sram[0]:11 mux_tree_tapbuf_size10_7_sram[0]:10 0.002428572 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_5_ccff_tail[0] 0.0005406607 //LENGTH 3.515 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_9\/FTB_6__45:X O *L 0 *C 8.095 55.420 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.870 53.380 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 *C 8.870 53.380 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 *C 8.325 53.380 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 *C 8.280 53.425 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 *C 8.280 55.375 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 *C 8.280 55.420 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 *C 8.095 55.420 + +*CAP +0 mem_bottom_ipin_9\/FTB_6__45:X 1e-06 +1 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 9.732177e-05 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 5.86991e-05 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.0001292129 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0001292129 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 6.14431e-05 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 6.277087e-05 + +*RES +0 mem_bottom_ipin_9\/FTB_6__45:X mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 0.0001005435 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 0.0004866072 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[1] 0.005880614 //LENGTH 45.505 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 90.925 33.660 +*I mux_bottom_ipin_6\/mux_l2_in_0_:S I *L 0.00357 *C 80.600 30.600 +*I mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 72.395 37.060 +*I mux_bottom_ipin_6\/mux_l2_in_1_:S I *L 0.00357 *C 80.140 34.295 +*I mux_bottom_ipin_6\/mux_l2_in_3_:S I *L 0.00357 *C 92.100 39.735 +*I mux_bottom_ipin_6\/mux_l2_in_2_:S I *L 0.00357 *C 94.400 41.480 +*N mux_tree_tapbuf_size8_2_sram[1]:6 *C 94.300 41.480 +*N mux_tree_tapbuf_size8_2_sram[1]:7 *C 94.300 41.480 +*N mux_tree_tapbuf_size8_2_sram[1]:8 *C 94.300 40.165 +*N mux_tree_tapbuf_size8_2_sram[1]:9 *C 94.255 40.120 +*N mux_tree_tapbuf_size8_2_sram[1]:10 *C 92.100 40.120 +*N mux_tree_tapbuf_size8_2_sram[1]:11 *C 92.100 39.735 +*N mux_tree_tapbuf_size8_2_sram[1]:12 *C 92.043 39.440 +*N mux_tree_tapbuf_size8_2_sram[1]:13 *C 91.585 39.440 +*N mux_tree_tapbuf_size8_2_sram[1]:14 *C 91.540 39.395 +*N mux_tree_tapbuf_size8_2_sram[1]:15 *C 80.140 34.295 +*N mux_tree_tapbuf_size8_2_sram[1]:16 *C 72.433 37.060 +*N mux_tree_tapbuf_size8_2_sram[1]:17 *C 73.095 37.060 +*N mux_tree_tapbuf_size8_2_sram[1]:18 *C 73.140 37.015 +*N mux_tree_tapbuf_size8_2_sram[1]:19 *C 73.140 34.045 +*N mux_tree_tapbuf_size8_2_sram[1]:20 *C 73.185 34.000 +*N mux_tree_tapbuf_size8_2_sram[1]:21 *C 80.140 34.000 +*N mux_tree_tapbuf_size8_2_sram[1]:22 *C 81.880 34.000 +*N mux_tree_tapbuf_size8_2_sram[1]:23 *C 81.880 33.660 +*N mux_tree_tapbuf_size8_2_sram[1]:24 *C 81.880 33.615 +*N mux_tree_tapbuf_size8_2_sram[1]:25 *C 80.638 30.600 +*N mux_tree_tapbuf_size8_2_sram[1]:26 *C 81.835 30.600 +*N mux_tree_tapbuf_size8_2_sram[1]:27 *C 81.880 30.645 +*N mux_tree_tapbuf_size8_2_sram[1]:28 *C 81.880 31.280 +*N mux_tree_tapbuf_size8_2_sram[1]:29 *C 82.340 31.280 +*N mux_tree_tapbuf_size8_2_sram[1]:30 *C 82.385 31.280 +*N mux_tree_tapbuf_size8_2_sram[1]:31 *C 91.495 31.280 +*N mux_tree_tapbuf_size8_2_sram[1]:32 *C 91.540 31.325 +*N mux_tree_tapbuf_size8_2_sram[1]:33 *C 91.540 33.660 +*N mux_tree_tapbuf_size8_2_sram[1]:34 *C 91.495 33.660 +*N mux_tree_tapbuf_size8_2_sram[1]:35 *C 90.963 33.660 + +*CAP +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_6\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_ipin_6\/mux_l2_in_1_:S 1e-06 +4 mux_bottom_ipin_6\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_6\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size8_2_sram[1]:6 3.54034e-05 +7 mux_tree_tapbuf_size8_2_sram[1]:7 0.000154253 +8 mux_tree_tapbuf_size8_2_sram[1]:8 0.0001227774 +9 mux_tree_tapbuf_size8_2_sram[1]:9 0.0001674669 +10 mux_tree_tapbuf_size8_2_sram[1]:10 0.0002002309 +11 mux_tree_tapbuf_size8_2_sram[1]:11 9.497154e-05 +12 mux_tree_tapbuf_size8_2_sram[1]:12 8.866005e-05 +13 mux_tree_tapbuf_size8_2_sram[1]:13 5.851866e-05 +14 mux_tree_tapbuf_size8_2_sram[1]:14 0.0003266236 +15 mux_tree_tapbuf_size8_2_sram[1]:15 6.379643e-05 +16 mux_tree_tapbuf_size8_2_sram[1]:16 6.524179e-05 +17 mux_tree_tapbuf_size8_2_sram[1]:17 6.524179e-05 +18 mux_tree_tapbuf_size8_2_sram[1]:18 0.0001841331 +19 mux_tree_tapbuf_size8_2_sram[1]:19 0.0001841331 +20 mux_tree_tapbuf_size8_2_sram[1]:20 0.0004433771 +21 mux_tree_tapbuf_size8_2_sram[1]:21 0.0006000804 +22 mux_tree_tapbuf_size8_2_sram[1]:22 0.0001536877 +23 mux_tree_tapbuf_size8_2_sram[1]:23 6.33053e-05 +24 mux_tree_tapbuf_size8_2_sram[1]:24 0.0001466159 +25 mux_tree_tapbuf_size8_2_sram[1]:25 0.0001112035 +26 mux_tree_tapbuf_size8_2_sram[1]:26 0.0001112035 +27 mux_tree_tapbuf_size8_2_sram[1]:27 5.595467e-05 +28 mux_tree_tapbuf_size8_2_sram[1]:28 0.0002385101 +29 mux_tree_tapbuf_size8_2_sram[1]:29 7.028685e-05 +30 mux_tree_tapbuf_size8_2_sram[1]:30 0.0006633336 +31 mux_tree_tapbuf_size8_2_sram[1]:31 0.0006633336 +32 mux_tree_tapbuf_size8_2_sram[1]:32 0.0001359308 +33 mux_tree_tapbuf_size8_2_sram[1]:33 0.0004937199 +34 mux_tree_tapbuf_size8_2_sram[1]:34 5.630964e-05 +35 mux_tree_tapbuf_size8_2_sram[1]:35 5.630964e-05 + +*RES +0 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_2_sram[1]:35 0.152 +1 mux_tree_tapbuf_size8_2_sram[1]:31 mux_tree_tapbuf_size8_2_sram[1]:30 0.008133929 +2 mux_tree_tapbuf_size8_2_sram[1]:32 mux_tree_tapbuf_size8_2_sram[1]:31 0.0045 +3 mux_tree_tapbuf_size8_2_sram[1]:30 mux_tree_tapbuf_size8_2_sram[1]:29 0.0045 +4 mux_tree_tapbuf_size8_2_sram[1]:29 mux_tree_tapbuf_size8_2_sram[1]:28 0.0004107143 +5 mux_tree_tapbuf_size8_2_sram[1]:13 mux_tree_tapbuf_size8_2_sram[1]:12 0.0004084822 +6 mux_tree_tapbuf_size8_2_sram[1]:14 mux_tree_tapbuf_size8_2_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size8_2_sram[1]:23 mux_tree_tapbuf_size8_2_sram[1]:22 0.0003035715 +8 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:23 0.0045 +9 mux_tree_tapbuf_size8_2_sram[1]:11 mux_bottom_ipin_6\/mux_l2_in_3_:S 0.152 +10 mux_tree_tapbuf_size8_2_sram[1]:11 mux_tree_tapbuf_size8_2_sram[1]:10 0.0003437501 +11 mux_tree_tapbuf_size8_2_sram[1]:9 mux_tree_tapbuf_size8_2_sram[1]:8 0.0045 +12 mux_tree_tapbuf_size8_2_sram[1]:8 mux_tree_tapbuf_size8_2_sram[1]:7 0.001174107 +13 mux_tree_tapbuf_size8_2_sram[1]:6 mux_bottom_ipin_6\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size8_2_sram[1]:7 mux_tree_tapbuf_size8_2_sram[1]:6 0.0045 +15 mux_tree_tapbuf_size8_2_sram[1]:15 mux_bottom_ipin_6\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size8_2_sram[1]:26 mux_tree_tapbuf_size8_2_sram[1]:25 0.001069196 +17 mux_tree_tapbuf_size8_2_sram[1]:27 mux_tree_tapbuf_size8_2_sram[1]:26 0.0045 +18 mux_tree_tapbuf_size8_2_sram[1]:25 mux_bottom_ipin_6\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:19 0.0045 +20 mux_tree_tapbuf_size8_2_sram[1]:19 mux_tree_tapbuf_size8_2_sram[1]:18 0.002651786 +21 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:16 0.0005915179 +22 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:17 0.0045 +23 mux_tree_tapbuf_size8_2_sram[1]:16 mem_bottom_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +24 mux_tree_tapbuf_size8_2_sram[1]:34 mux_tree_tapbuf_size8_2_sram[1]:33 0.0045 +25 mux_tree_tapbuf_size8_2_sram[1]:33 mux_tree_tapbuf_size8_2_sram[1]:32 0.002084821 +26 mux_tree_tapbuf_size8_2_sram[1]:33 mux_tree_tapbuf_size8_2_sram[1]:14 0.005120536 +27 mux_tree_tapbuf_size8_2_sram[1]:35 mux_tree_tapbuf_size8_2_sram[1]:34 0.0004754465 +28 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:20 0.006209821 +29 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:15 0.0001271552 +30 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:21 0.001553571 +31 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:11 0.0001715117 +32 mux_tree_tapbuf_size8_2_sram[1]:10 mux_tree_tapbuf_size8_2_sram[1]:9 0.001924107 +33 mux_tree_tapbuf_size8_2_sram[1]:28 mux_tree_tapbuf_size8_2_sram[1]:27 0.0005669643 +34 mux_tree_tapbuf_size8_2_sram[1]:28 mux_tree_tapbuf_size8_2_sram[1]:24 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[0] 0.005851534 //LENGTH 43.975 LUMPCC 0.000842166 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 95.985 64.260 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.340 49.980 +*I mux_bottom_ipin_14\/mux_l1_in_0_:S I *L 0.00357 *C 95.340 34.680 +*N mux_tree_tapbuf_size8_6_sram[0]:3 *C 97.730 63.920 +*N mux_tree_tapbuf_size8_6_sram[0]:4 *C 95.377 34.680 +*N mux_tree_tapbuf_size8_6_sram[0]:5 *C 96.095 34.680 +*N mux_tree_tapbuf_size8_6_sram[0]:6 *C 96.140 34.725 +*N mux_tree_tapbuf_size8_6_sram[0]:7 *C 90.377 49.980 +*N mux_tree_tapbuf_size8_6_sram[0]:8 *C 96.095 49.980 +*N mux_tree_tapbuf_size8_6_sram[0]:9 *C 96.140 49.935 +*N mux_tree_tapbuf_size8_6_sram[0]:10 *C 96.140 50.320 +*N mux_tree_tapbuf_size8_6_sram[0]:11 *C 96.148 50.320 +*N mux_tree_tapbuf_size8_6_sram[0]:12 *C 98.420 50.320 +*N mux_tree_tapbuf_size8_6_sram[0]:13 *C 98.440 50.328 +*N mux_tree_tapbuf_size8_6_sram[0]:14 *C 98.440 63.913 +*N mux_tree_tapbuf_size8_6_sram[0]:15 *C 98.438 63.920 +*N mux_tree_tapbuf_size8_6_sram[0]:16 *C 98.440 63.920 +*N mux_tree_tapbuf_size8_6_sram[0]:17 *C 98.440 63.920 +*N mux_tree_tapbuf_size8_6_sram[0]:18 *C 98.440 64.260 +*N mux_tree_tapbuf_size8_6_sram[0]:19 *C 96.023 64.260 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_ipin_14\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_6_sram[0]:3 0.0001171096 +4 mux_tree_tapbuf_size8_6_sram[0]:4 7.495023e-05 +5 mux_tree_tapbuf_size8_6_sram[0]:5 7.495023e-05 +6 mux_tree_tapbuf_size8_6_sram[0]:6 0.000603151 +7 mux_tree_tapbuf_size8_6_sram[0]:7 0.0003778817 +8 mux_tree_tapbuf_size8_6_sram[0]:8 0.0003778817 +9 mux_tree_tapbuf_size8_6_sram[0]:9 0.0006162642 +10 mux_tree_tapbuf_size8_6_sram[0]:10 4.822958e-05 +11 mux_tree_tapbuf_size8_6_sram[0]:11 0.0002656724 +12 mux_tree_tapbuf_size8_6_sram[0]:12 0.0002656724 +13 mux_tree_tapbuf_size8_6_sram[0]:13 0.0008117845 +14 mux_tree_tapbuf_size8_6_sram[0]:14 0.0008117845 +15 mux_tree_tapbuf_size8_6_sram[0]:15 0.0001171096 +16 mux_tree_tapbuf_size8_6_sram[0]:16 3.403109e-05 +17 mux_tree_tapbuf_size8_6_sram[0]:17 6.109728e-05 +18 mux_tree_tapbuf_size8_6_sram[0]:18 0.0001885399 +19 mux_tree_tapbuf_size8_6_sram[0]:19 0.0001602594 +20 mux_tree_tapbuf_size8_6_sram[0]:10 chanx_left_in[1]:21 9.779079e-06 +21 mux_tree_tapbuf_size8_6_sram[0]:9 chanx_left_in[1]:22 0.000421083 +22 mux_tree_tapbuf_size8_6_sram[0]:6 chanx_left_in[1]:21 0.0004113039 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_6_sram[0]:19 0.152 +1 mux_tree_tapbuf_size8_6_sram[0]:10 mux_tree_tapbuf_size8_6_sram[0]:9 0.0001850962 +2 mux_tree_tapbuf_size8_6_sram[0]:11 mux_tree_tapbuf_size8_6_sram[0]:10 0.00341 +3 mux_tree_tapbuf_size8_6_sram[0]:12 mux_tree_tapbuf_size8_6_sram[0]:11 0.000356025 +4 mux_tree_tapbuf_size8_6_sram[0]:13 mux_tree_tapbuf_size8_6_sram[0]:12 0.00341 +5 mux_tree_tapbuf_size8_6_sram[0]:15 mux_tree_tapbuf_size8_6_sram[0]:14 0.00341 +6 mux_tree_tapbuf_size8_6_sram[0]:15 mux_tree_tapbuf_size8_6_sram[0]:3 0.0001039141 +7 mux_tree_tapbuf_size8_6_sram[0]:14 mux_tree_tapbuf_size8_6_sram[0]:13 0.002128317 +8 mux_tree_tapbuf_size8_6_sram[0]:16 mux_tree_tapbuf_size8_6_sram[0]:15 0.00341 +9 mux_tree_tapbuf_size8_6_sram[0]:17 mux_tree_tapbuf_size8_6_sram[0]:16 0.0045 +10 mux_tree_tapbuf_size8_6_sram[0]:19 mux_tree_tapbuf_size8_6_sram[0]:18 0.002158482 +11 mux_tree_tapbuf_size8_6_sram[0]:8 mux_tree_tapbuf_size8_6_sram[0]:7 0.005104911 +12 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:8 0.0045 +13 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:6 0.01358036 +14 mux_tree_tapbuf_size8_6_sram[0]:7 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size8_6_sram[0]:5 mux_tree_tapbuf_size8_6_sram[0]:4 0.000640625 +16 mux_tree_tapbuf_size8_6_sram[0]:6 mux_tree_tapbuf_size8_6_sram[0]:5 0.0045 +17 mux_tree_tapbuf_size8_6_sram[0]:4 mux_bottom_ipin_14\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size8_6_sram[0]:18 mux_tree_tapbuf_size8_6_sram[0]:17 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_4_ccff_tail[0] 0.001542603 //LENGTH 13.410 LUMPCC 0.0001060824 DR + +*CONN +*I mem_bottom_ipin_10\/FTB_13__52:X O *L 0 *C 27.375 18.360 +*I mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 22.715 26.180 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 *C 22.753 26.180 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 *C 26.635 26.180 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 *C 26.680 26.135 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 *C 26.680 18.405 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 *C 26.725 18.360 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 *C 27.338 18.360 + +*CAP +0 mem_bottom_ipin_10\/FTB_13__52:X 1e-06 +1 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 0.0002584214 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 0.0002584214 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.0003964281 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0003964281 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 6.241085e-05 +7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 6.241085e-05 +8 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 chanx_right_in[14]:13 7.042125e-06 +9 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 chanx_right_in[14]:14 7.042125e-06 +10 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 chanx_right_in[14]:19 4.599909e-05 +11 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 chanx_right_in[14]:20 4.599909e-05 + +*RES +0 mem_bottom_ipin_10\/FTB_13__52:X mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 mem_bottom_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 0.003466518 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.006901787 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 0.000546875 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004570513 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_1_:X O *L 0 *C 76.995 26.520 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 77.110 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 77.110 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 77.280 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 77.280 28.175 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 77.280 26.565 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 77.280 26.520 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 76.995 26.520 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.104584e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.379392e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001122071 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001122071 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.503054e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.076671e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001078857 //LENGTH 8.800 LUMPCC 0.0001291275 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_3_:X O *L 0 *C 61.355 10.200 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 62.380 17.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 62.380 17.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 62.100 17.340 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 62.100 17.295 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 62.100 10.245 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 62.055 10.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 61.393 10.200 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.552149e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.981622e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003764791 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003764791 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 3.971699e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.971699e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 optlc_net_126:11 3.882516e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 optlc_net_126:10 3.882516e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 optlc_net_126:12 2.573858e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_126:13 2.573858e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_3_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005915179 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.006294643 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001521739 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00170253 //LENGTH 11.900 LUMPCC 0.0007075191 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l3_in_0_:X O *L 0 *C 53.535 58.480 +*I mux_bottom_ipin_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 45.905 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 45.943 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 48.300 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 48.300 61.200 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 52.855 61.200 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 52.900 61.155 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 52.900 58.525 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 52.945 58.480 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 53.498 58.480 + +*CAP +0 mux_bottom_ipin_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.133295e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.549882e-05 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000269575 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002454091 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001066872 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001066872 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 5.891043e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:9 5.891043e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 chanx_right_in[19]:25 9.689859e-05 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_right_in[19]:26 1.89667e-05 +12 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chanx_right_in[19]:26 9.689859e-05 +13 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chanx_right_in[19]:25 1.89667e-05 +14 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_1_sram[1]:20 7.664932e-05 +15 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_1_sram[1]:21 7.664932e-05 +16 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:16 7.444899e-05 +17 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_1_sram[2]:17 3.633948e-06 +18 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_1_sram[2]:14 3.633948e-06 +19 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:15 7.444899e-05 +20 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_1_sram[3]:8 8.316201e-05 +21 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_1_sram[3]:9 8.316201e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l3_in_0_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_1\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004066964 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002348214 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0004933036 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002104911 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005053444 //LENGTH 3.330 LUMPCC 8.453365e-05 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l2_in_2_:X O *L 0 *C 57.215 20.665 +*I mux_bottom_ipin_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 57.500 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 57.500 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 57.500 23.415 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 57.500 20.785 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 57.500 20.740 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 57.215 20.665 + +*CAP +0 mux_bottom_ipin_4\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.283419e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001283919 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001283919 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.52783e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.391441e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.226682e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.226682e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l2_in_2_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001548913 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002348214 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_4\/mux_l3_in_1_:A1 0.152 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.00102322 //LENGTH 7.950 LUMPCC 9.738152e-05 DR + +*CONN +*I mux_bottom_ipin_5\/mux_l2_in_0_:X O *L 0 *C 55.945 52.360 +*I mux_bottom_ipin_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 53.725 47.260 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 53.763 47.260 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 55.615 47.260 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 55.660 47.305 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 55.660 52.315 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 55.660 52.360 +*N mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 55.945 52.360 + +*CAP +0 mux_bottom_ipin_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001362884 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001362884 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002728185 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002728185 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.281534e-05 +7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.280896e-05 +8 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_left_in[1]:31 4.407464e-05 +9 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[1]:29 4.616121e-06 +10 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[1]:30 4.407464e-05 +11 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[1]:28 4.616121e-06 + +*RES +0 mux_bottom_ipin_5\/mux_l2_in_0_:X mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_5\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004473215 +6 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005586855 //LENGTH 4.045 LUMPCC 9.062619e-05 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_1_:X O *L 0 *C 16.385 31.620 +*I mux_bottom_ipin_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 15.010 33.660 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 15.048 33.660 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 16.055 33.660 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 16.100 33.615 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 16.100 31.665 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 16.100 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 16.385 31.620 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.013335e-05 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.013335e-05 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001124683 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001124683 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.977519e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.10807e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.114001e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 2.114001e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.417308e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.417308e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_1_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008995536 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001741072 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006296844 //LENGTH 4.915 LUMPCC 0.0001694869 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l2_in_1_:X O *L 0 *C 15.355 56.100 +*I mux_bottom_ipin_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 14.090 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 14.128 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 14.675 58.820 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 14.720 58.775 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 14.720 56.145 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 14.765 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 15.318 56.100 + +*CAP +0 mux_bottom_ipin_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.448727e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.448727e-05 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001314391 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001314391 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.317238e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.317238e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.020649e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.453699e-05 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.020649e-05 +11 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.453699e-05 + +*RES +0 mux_bottom_ipin_9\/mux_l2_in_1_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_9\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000339262 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_1_:X O *L 0 *C 72.965 22.780 +*I mux_bottom_ipin_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 75.155 22.780 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 75.118 22.780 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 73.002 22.780 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000168631 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000168631 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0007659742 //LENGTH 6.280 LUMPCC 0.0001004345 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l3_in_0_:X O *L 0 *C 79.865 20.740 +*I mux_bottom_ipin_12\/mux_l4_in_0_:A1 I *L 0.00198 *C 82.800 23.460 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 82.800 23.460 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 82.800 23.415 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 82.800 20.785 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 82.755 20.740 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 79.903 20.740 + +*CAP +0 mux_bottom_ipin_12\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.223958e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001770434 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001770434 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001386067 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001386067 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_6_sram[2]:4 5.021723e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_6_sram[2]:5 5.021723e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l3_in_0_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002546875 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002348214 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_12\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001411651 //LENGTH 11.025 LUMPCC 0.0001348788 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_3_:X O *L 0 *C 90.335 58.480 +*I mux_bottom_ipin_13\/mux_l3_in_1_:A0 I *L 0.001631 *C 86.770 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 86.808 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 89.655 64.260 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 89.700 64.215 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 89.700 58.525 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 89.745 58.480 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 90.335 58.480 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001863919 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001863919 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003068869 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003068869 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001289542 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.000159261 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 prog_clk[0]:219 1.355058e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 prog_clk[0]:218 1.355058e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:217 3.542415e-06 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:220 5.034639e-05 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:220 3.542415e-06 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:223 5.034639e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_3_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002542411 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005080357 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005267857 + +*END + +*D_NET mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008756883 //LENGTH 6.340 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_2\/mux_l3_in_1_:X O *L 0 *C 32.835 17.340 +*I mux_bottom_ipin_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 32.490 22.780 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 32.490 22.780 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 32.660 22.780 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 32.660 22.735 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 32.660 17.385 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 32.660 17.340 +*N mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 32.835 17.340 + +*CAP +0 mux_bottom_ipin_2\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_2\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.117387e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.451603e-05 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000332851 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000332851 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.136395e-05 +7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.093255e-05 + +*RES +0 mux_bottom_ipin_2\/mux_l3_in_1_:X mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_2\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004776786 +6 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000582172 //LENGTH 3.900 LUMPCC 0.0001039827 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l3_in_0_:X O *L 0 *C 35.245 45.560 +*I mux_bottom_ipin_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 36.245 47.260 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 36.208 47.260 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 35.005 47.260 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 34.960 47.215 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 34.960 45.605 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 34.960 45.560 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 35.245 45.560 + +*CAP +0 mux_bottom_ipin_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.311036e-05 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.311036e-05 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.555481e-05 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.555481e-05 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.076373e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.809523e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_1_sram[0]:5 5.199134e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_1_sram[0]:9 5.199134e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l3_in_0_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_3\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001073661 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001329754 //LENGTH 10.940 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l3_in_0_:X O *L 0 *C 77.915 38.760 +*I mux_bottom_ipin_6\/mux_l4_in_0_:A1 I *L 0.00198 *C 73.965 45.220 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 73.965 45.220 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 74.060 45.175 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 74.060 38.805 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 74.105 38.760 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 77.877 38.760 + +*CAP +0 mux_bottom_ipin_6\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.863667e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003780462 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003780462 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002715126 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002715126 + +*RES +0 mux_bottom_ipin_6\/mux_l3_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_6\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0056875 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.003368304 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005007541 //LENGTH 3.330 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l3_in_0_:X O *L 0 *C 28.235 58.820 +*I mux_bottom_ipin_7\/mux_l4_in_0_:A1 I *L 0.00198 *C 28.425 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 28.425 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 28.520 61.495 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 28.520 58.865 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 28.520 58.820 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 28.235 58.820 + +*CAP +0 mux_bottom_ipin_7\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.794667e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001779968 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001779968 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.747581e-05 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.733802e-05 + +*RES +0 mux_bottom_ipin_7\/mux_l3_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_7\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002348214 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0003972818 //LENGTH 2.765 LUMPCC 8.330811e-05 DR + +*CONN +*I mux_bottom_ipin_10\/mux_l3_in_0_:X O *L 0 *C 14.545 18.020 +*I mux_bottom_ipin_10\/mux_l4_in_0_:A1 I *L 0.00198 *C 17.020 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 16.983 18.020 +*N mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 14.583 18.020 + +*CAP +0 mux_bottom_ipin_10\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_10\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001559869 +3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001559869 +4 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_4_sram[3]:4 4.165406e-05 +5 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_4_sram[3]:5 4.165406e-05 + +*RES +0 mux_bottom_ipin_10\/mux_l3_in_0_:X mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002142857 +2 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_10\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001400556 //LENGTH 10.915 LUMPCC 0.0004556788 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l2_in_0_:X O *L 0 *C 26.395 46.920 +*I mux_bottom_ipin_11\/mux_l3_in_0_:A1 I *L 0.00198 *C 21.525 41.820 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 21.525 41.820 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 21.620 42.160 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 24.795 42.160 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 24.840 42.205 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 24.840 46.875 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 24.885 46.920 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 26.358 46.920 + +*CAP +0 mux_bottom_ipin_11\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.226345e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001204899 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.458973e-05 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002429777 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002429777 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.478928e-05 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.478928e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_5_sram[1]:20 1.625984e-05 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_5_sram[1]:23 1.209672e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size8_5_sram[1]:26 2.843915e-05 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_5_sram[1]:23 1.625984e-05 +13 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_5_sram[1]:24 1.209672e-05 +14 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size8_5_sram[1]:6 2.843915e-05 +15 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size8_5_sram[2]:11 5.673172e-05 +16 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_5_sram[2]:12 6.913633e-06 +17 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_5_sram[2]:13 6.913633e-06 +18 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_5_sram[2]:10 5.673172e-05 +19 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_124:12 1.504213e-05 +20 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_124:29 7.527899e-05 +21 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_124:27 1.707723e-05 +22 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_124:28 1.707723e-05 +23 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 optlc_net_124:11 1.504213e-05 +24 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 optlc_net_124:13 7.527899e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l2_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_11\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.002834821 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.004169643 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001314732 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000438143 //LENGTH 2.650 LUMPCC 0.0001197295 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l2_in_0_:X O *L 0 *C 61.895 61.540 +*I mux_bottom_ipin_15\/mux_l3_in_0_:A1 I *L 0.00198 *C 62.100 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 62.100 63.580 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 62.100 63.535 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.100 61.585 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.100 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 61.895 61.540 + +*CAP +0 mux_bottom_ipin_15\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.302265e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.785346e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.785346e-05 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.414032e-05 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.354364e-05 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.986473e-05 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.986473e-05 + +*RES +0 mux_bottom_ipin_15\/mux_l2_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001114131 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001741071 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_15\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_173 0.001342819 //LENGTH 9.780 LUMPCC 0.0001391031 DR + +*CONN +*I ropt_mt_inst_725:X O *L 0 *C 14.455 67.320 +*I ropt_mt_inst_777:A I *L 0.001767 *C 5.980 66.640 +*N ropt_net_173:2 *C 5.980 66.640 +*N ropt_net_173:3 *C 5.980 66.685 +*N ropt_net_173:4 *C 5.980 67.275 +*N ropt_net_173:5 *C 6.025 67.320 +*N ropt_net_173:6 *C 14.418 67.320 + +*CAP +0 ropt_mt_inst_725:X 1e-06 +1 ropt_mt_inst_777:A 1e-06 +2 ropt_net_173:2 3.476967e-05 +3 ropt_net_173:3 6.135588e-05 +4 ropt_net_173:4 6.135588e-05 +5 ropt_net_173:5 0.0005221174 +6 ropt_net_173:6 0.0005221174 +7 ropt_net_173:5 chanx_right_in[4]:5 6.955155e-05 +8 ropt_net_173:6 chanx_right_in[4]:4 6.955155e-05 + +*RES +0 ropt_mt_inst_725:X ropt_net_173:6 0.152 +1 ropt_net_173:2 ropt_mt_inst_777:A 0.152 +2 ropt_net_173:3 ropt_net_173:2 0.0045 +3 ropt_net_173:5 ropt_net_173:4 0.0045 +4 ropt_net_173:4 ropt_net_173:3 0.0005267857 +5 ropt_net_173:6 ropt_net_173:5 0.007493304 + +*END + +*D_NET ropt_net_180 0.001136562 //LENGTH 7.990 LUMPCC 0.0001029396 DR + +*CONN +*I ropt_mt_inst_729:X O *L 0 *C 25.105 70.040 +*I ropt_mt_inst_787:A I *L 0.001767 *C 19.780 72.080 +*N ropt_net_180:2 *C 19.780 72.080 +*N ropt_net_180:3 *C 19.780 72.035 +*N ropt_net_180:4 *C 19.780 70.085 +*N ropt_net_180:5 *C 19.825 70.040 +*N ropt_net_180:6 *C 25.068 70.040 + +*CAP +0 ropt_mt_inst_729:X 1e-06 +1 ropt_mt_inst_787:A 1e-06 +2 ropt_net_180:2 2.865023e-05 +3 ropt_net_180:3 0.0001164648 +4 ropt_net_180:4 0.0001164648 +5 ropt_net_180:5 0.0003850213 +6 ropt_net_180:6 0.0003850213 +7 ropt_net_180:6 ropt_net_132:4 4.766947e-05 +8 ropt_net_180:5 ropt_net_132:3 4.766947e-05 +9 ropt_net_180:4 ropt_net_132:5 3.800309e-06 +10 ropt_net_180:3 ropt_net_132:6 3.800309e-06 + +*RES +0 ropt_mt_inst_729:X ropt_net_180:6 0.152 +1 ropt_net_180:6 ropt_net_180:5 0.004680804 +2 ropt_net_180:5 ropt_net_180:4 0.0045 +3 ropt_net_180:4 ropt_net_180:3 0.001741071 +4 ropt_net_180:2 ropt_mt_inst_787:A 0.152 +5 ropt_net_180:3 ropt_net_180:2 0.0045 + +*END + +*D_NET ropt_net_159 0.0007477021 //LENGTH 7.245 LUMPCC 0 DR + +*CONN +*I FTB_19__18:X O *L 0 *C 98.900 68.680 +*I ropt_mt_inst_759:A I *L 0.001766 *C 97.825 72.080 +*N ropt_net_159:2 *C 97.863 72.080 +*N ropt_net_159:3 *C 99.775 72.080 +*N ropt_net_159:4 *C 99.820 72.035 +*N ropt_net_159:5 *C 99.820 68.725 +*N ropt_net_159:6 *C 99.775 68.680 +*N ropt_net_159:7 *C 98.938 68.680 + +*CAP +0 FTB_19__18:X 1e-06 +1 ropt_mt_inst_759:A 1e-06 +2 ropt_net_159:2 0.0001171341 +3 ropt_net_159:3 0.0001171341 +4 ropt_net_159:4 0.0001832813 +5 ropt_net_159:5 0.0001832813 +6 ropt_net_159:6 7.243565e-05 +7 ropt_net_159:7 7.243565e-05 + +*RES +0 FTB_19__18:X ropt_net_159:7 0.152 +1 ropt_net_159:2 ropt_mt_inst_759:A 0.152 +2 ropt_net_159:3 ropt_net_159:2 0.001707589 +3 ropt_net_159:4 ropt_net_159:3 0.0045 +4 ropt_net_159:6 ropt_net_159:5 0.0045 +5 ropt_net_159:5 ropt_net_159:4 0.002955357 +6 ropt_net_159:7 ropt_net_159:6 0.0007477679 + +*END + +*D_NET chanx_right_out[19] 0.0006693581 //LENGTH 5.115 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 98.900 3.400 +*P chanx_right_out[19] O *L 0.7423 *C 100.280 1.210 +*N chanx_right_out[19]:2 *C 99.880 2.040 +*N chanx_right_out[19]:3 *C 100.280 2.033 +*N chanx_right_out[19]:4 *C 100.280 2.040 +*N chanx_right_out[19]:5 *C 100.280 2.098 +*N chanx_right_out[19]:6 *C 100.280 3.355 +*N chanx_right_out[19]:7 *C 100.235 3.400 +*N chanx_right_out[19]:8 *C 98.938 3.400 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 chanx_right_out[19] 5.591188e-05 +2 chanx_right_out[19]:2 5.685977e-05 +3 chanx_right_out[19]:3 5.591188e-05 +4 chanx_right_out[19]:4 5.685977e-05 +5 chanx_right_out[19]:5 9.371413e-05 +6 chanx_right_out[19]:6 9.371413e-05 +7 chanx_right_out[19]:7 0.0001276933 +8 chanx_right_out[19]:8 0.0001276933 + +*RES +0 ropt_mt_inst_738:X chanx_right_out[19]:8 0.152 +1 chanx_right_out[19]:8 chanx_right_out[19]:7 0.001158482 +2 chanx_right_out[19]:7 chanx_right_out[19]:6 0.0045 +3 chanx_right_out[19]:6 chanx_right_out[19]:5 0.001122768 +4 chanx_right_out[19]:5 chanx_right_out[19]:4 0.00341 +5 chanx_right_out[19]:4 chanx_right_out[19]:3 0.00341 +6 chanx_right_out[19]:4 chanx_right_out[19]:2 5.69697e-05 +7 chanx_right_out[19]:3 chanx_right_out[19] 0.0001288583 + +*END + +*D_NET chanx_right_out[0] 0.0007760337 //LENGTH 6.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 98.900 48.280 +*P chanx_right_out[0] O *L 0.7423 *C 103.650 48.960 +*N chanx_right_out[0]:2 *C 102.128 48.960 +*N chanx_right_out[0]:3 *C 102.120 48.903 +*N chanx_right_out[0]:4 *C 102.120 48.325 +*N chanx_right_out[0]:5 *C 102.075 48.280 +*N chanx_right_out[0]:6 *C 98.938 48.280 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 chanx_right_out[0] 0.0001197934 +2 chanx_right_out[0]:2 0.0001197934 +3 chanx_right_out[0]:3 5.390767e-05 +4 chanx_right_out[0]:4 5.390767e-05 +5 chanx_right_out[0]:5 0.0002138158 +6 chanx_right_out[0]:6 0.0002138158 + +*RES +0 ropt_mt_inst_742:X chanx_right_out[0]:6 0.152 +1 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +2 chanx_right_out[0]:2 chanx_right_out[0] 0.000238525 +3 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +4 chanx_right_out[0]:4 chanx_right_out[0]:3 0.000515625 +5 chanx_right_out[0]:6 chanx_right_out[0]:5 0.002801339 + +*END + +*D_NET ropt_net_147 0.001872083 //LENGTH 13.405 LUMPCC 0.0006604402 DR + +*CONN +*I FTB_40__39:X O *L 0 *C 10.580 11.560 +*I ropt_mt_inst_744:A I *L 0.001766 *C 3.220 6.800 +*N ropt_net_147:2 *C 3.258 6.800 +*N ropt_net_147:3 *C 4.095 6.800 +*N ropt_net_147:4 *C 4.140 6.800 +*N ropt_net_147:5 *C 4.147 6.800 +*N ropt_net_147:6 *C 7.812 6.800 +*N ropt_net_147:7 *C 7.820 6.857 +*N ropt_net_147:8 *C 7.820 11.515 +*N ropt_net_147:9 *C 7.865 11.560 +*N ropt_net_147:10 *C 10.543 11.560 + +*CAP +0 FTB_40__39:X 1e-06 +1 ropt_mt_inst_744:A 1e-06 +2 ropt_net_147:2 6.40479e-05 +3 ropt_net_147:3 6.40479e-05 +4 ropt_net_147:4 3.418525e-05 +5 ropt_net_147:5 7.947933e-05 +6 ropt_net_147:6 7.947933e-05 +7 ropt_net_147:7 0.0002487719 +8 ropt_net_147:8 0.0002487719 +9 ropt_net_147:9 0.0001954295 +10 ropt_net_147:10 0.0001954295 +11 ropt_net_147:6 chanx_left_out[0]:4 8.597617e-05 +12 ropt_net_147:5 chanx_left_out[0]:3 8.597617e-05 +13 ropt_net_147:8 chanx_left_out[17]:6 1.86481e-05 +14 ropt_net_147:7 chanx_left_out[17]:5 1.86481e-05 +15 ropt_net_147:6 chanx_left_out[17]:4 0.0002255958 +16 ropt_net_147:5 chanx_left_out[17]:3 0.0002255958 + +*RES +0 FTB_40__39:X ropt_net_147:10 0.152 +1 ropt_net_147:10 ropt_net_147:9 0.002390625 +2 ropt_net_147:9 ropt_net_147:8 0.0045 +3 ropt_net_147:8 ropt_net_147:7 0.004158482 +4 ropt_net_147:7 ropt_net_147:6 0.00341 +5 ropt_net_147:6 ropt_net_147:5 0.0005741833 +6 ropt_net_147:4 ropt_net_147:3 0.0045 +7 ropt_net_147:5 ropt_net_147:4 0.00341 +8 ropt_net_147:3 ropt_net_147:2 0.0007477679 +9 ropt_net_147:2 ropt_mt_inst_744:A 0.152 + +*END + +*D_NET chanx_left_out[15] 0.0007506267 //LENGTH 4.440 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 4.140 30.940 +*P chanx_left_out[15] O *L 0.7423 *C 1.230 29.920 +*N chanx_left_out[15]:2 *C 4.133 29.920 +*N chanx_left_out[15]:3 *C 4.140 29.978 +*N chanx_left_out[15]:4 *C 4.140 30.895 +*N chanx_left_out[15]:5 *C 4.140 30.940 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 chanx_left_out[15] 0.0002668919 +2 chanx_left_out[15]:2 0.0002668919 +3 chanx_left_out[15]:3 9.05705e-05 +4 chanx_left_out[15]:4 9.05705e-05 +5 chanx_left_out[15]:5 3.470189e-05 + +*RES +0 ropt_mt_inst_785:X chanx_left_out[15]:5 0.152 +1 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +2 chanx_left_out[15]:4 chanx_left_out[15]:3 0.0008191965 +3 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +4 chanx_left_out[15]:2 chanx_left_out[15] 0.000454725 + +*END + +*D_NET chanx_left_out[16] 0.001068325 //LENGTH 8.485 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 4.140 17.000 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 12.240 +*N chanx_left_out[16]:2 *C 1.833 12.240 +*N chanx_left_out[16]:3 *C 1.840 12.298 +*N chanx_left_out[16]:4 *C 1.840 16.955 +*N chanx_left_out[16]:5 *C 1.885 17.000 +*N chanx_left_out[16]:6 *C 4.103 17.000 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 chanx_left_out[16] 8.63832e-05 +2 chanx_left_out[16]:2 8.63832e-05 +3 chanx_left_out[16]:3 0.0002694757 +4 chanx_left_out[16]:4 0.0002694757 +5 chanx_left_out[16]:5 0.0001778034 +6 chanx_left_out[16]:6 0.0001778034 + +*RES +0 ropt_mt_inst_786:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:6 chanx_left_out[16]:5 0.001979911 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.004158483 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 9.439165e-05 + +*END + +*D_NET ropt_net_182 0.0009003334 //LENGTH 7.250 LUMPCC 8.828768e-05 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 101.855 64.600 +*I ropt_mt_inst_789:A I *L 0.001767 *C 97.825 66.640 +*N ropt_net_182:2 *C 97.863 66.640 +*N ropt_net_182:3 *C 102.075 66.640 +*N ropt_net_182:4 *C 102.120 66.595 +*N ropt_net_182:5 *C 102.120 64.645 +*N ropt_net_182:6 *C 102.120 64.600 +*N ropt_net_182:7 *C 101.855 64.600 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_182:2 0.0002453366 +3 ropt_net_182:3 0.0002453366 +4 ropt_net_182:4 0.0001030893 +5 ropt_net_182:5 0.0001030893 +6 ropt_net_182:6 5.288391e-05 +7 ropt_net_182:7 6.030993e-05 +8 ropt_net_182:2 chanx_right_out[13]:7 2.698345e-05 +9 ropt_net_182:3 chanx_right_out[13]:6 2.698345e-05 +10 ropt_net_182:4 chanx_right_out[13]:2 1.716038e-05 +11 ropt_net_182:5 chanx_right_out[13]:3 1.716038e-05 + +*RES +0 ropt_mt_inst_755:X ropt_net_182:7 0.152 +1 ropt_net_182:2 ropt_mt_inst_789:A 0.152 +2 ropt_net_182:3 ropt_net_182:2 0.003761161 +3 ropt_net_182:4 ropt_net_182:3 0.0045 +4 ropt_net_182:6 ropt_net_182:5 0.0045 +5 ropt_net_182:5 ropt_net_182:4 0.001741072 +6 ropt_net_182:7 ropt_net_182:6 0.0001440218 + +*END + +*D_NET ropt_net_185 0.001246599 //LENGTH 9.140 LUMPCC 0.000401403 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 101.855 38.760 +*I ropt_mt_inst_792:A I *L 0.001767 *C 97.825 36.720 +*N ropt_net_185:2 *C 97.825 36.720 +*N ropt_net_185:3 *C 97.980 36.720 +*N ropt_net_185:4 *C 97.980 36.675 +*N ropt_net_185:5 *C 97.980 36.098 +*N ropt_net_185:6 *C 97.988 36.040 +*N ropt_net_185:7 *C 102.113 36.040 +*N ropt_net_185:8 *C 102.120 36.098 +*N ropt_net_185:9 *C 102.120 38.715 +*N ropt_net_185:10 *C 102.120 38.760 +*N ropt_net_185:11 *C 101.855 38.760 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_185:2 6.066314e-05 +3 ropt_net_185:3 6.213803e-05 +4 ropt_net_185:4 3.328733e-05 +5 ropt_net_185:5 3.328733e-05 +6 ropt_net_185:6 0.0001124612 +7 ropt_net_185:7 0.0001124612 +8 ropt_net_185:8 0.0001578913 +9 ropt_net_185:9 0.0001578913 +10 ropt_net_185:10 5.495322e-05 +11 ropt_net_185:11 5.816225e-05 +12 ropt_net_185:6 chanx_right_in[0]:53 6.45984e-05 +13 ropt_net_185:7 chanx_right_in[0] 6.45984e-05 +14 ropt_net_185:4 ccff_head[0]:5 2.761855e-05 +15 ropt_net_185:5 ccff_head[0]:4 2.761855e-05 +16 ropt_net_185:6 ccff_head[0]:6 0.0001084846 +17 ropt_net_185:7 ccff_head[0] 0.0001084846 + +*RES +0 ropt_mt_inst_765:X ropt_net_185:11 0.152 +1 ropt_net_185:2 ropt_mt_inst_792:A 0.152 +2 ropt_net_185:3 ropt_net_185:2 8.423914e-05 +3 ropt_net_185:4 ropt_net_185:3 0.0045 +4 ropt_net_185:5 ropt_net_185:4 0.000515625 +5 ropt_net_185:6 ropt_net_185:5 0.00341 +6 ropt_net_185:8 ropt_net_185:7 0.00341 +7 ropt_net_185:7 ropt_net_185:6 0.00064625 +8 ropt_net_185:10 ropt_net_185:9 0.0045 +9 ropt_net_185:9 ropt_net_185:8 0.002337054 +10 ropt_net_185:11 ropt_net_185:10 0.0001440218 + +*END + +*D_NET chanx_left_out[2] 0.0009125811 //LENGTH 5.940 LUMPCC 0 DR + +*CONN +*I BUFT_P_98:X O *L 0 *C 5.980 29.240 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 28.560 +*N chanx_left_out[2]:2 *C 5.973 28.560 +*N chanx_left_out[2]:3 *C 5.980 28.617 +*N chanx_left_out[2]:4 *C 5.980 29.195 +*N chanx_left_out[2]:5 *C 5.980 29.240 + +*CAP +0 BUFT_P_98:X 1e-06 +1 chanx_left_out[2] 0.0003722367 +2 chanx_left_out[2]:2 0.0003722367 +3 chanx_left_out[2]:3 6.624332e-05 +4 chanx_left_out[2]:4 6.624332e-05 +5 chanx_left_out[2]:5 3.462098e-05 + +*RES +0 BUFT_P_98:X chanx_left_out[2]:5 0.152 +1 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +2 chanx_left_out[2]:4 chanx_left_out[2]:3 0.000515625 +3 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +4 chanx_left_out[2]:2 chanx_left_out[2] 0.0007429916 + +*END + +*D_NET chanx_right_out[1] 0.001319486 //LENGTH 11.765 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 94.300 10.200 +*P chanx_right_out[1] O *L 0.7423 *C 103.650 10.880 +*N chanx_right_out[1]:2 *C 93.848 10.880 +*N chanx_right_out[1]:3 *C 93.840 10.822 +*N chanx_right_out[1]:4 *C 93.840 10.245 +*N chanx_right_out[1]:5 *C 93.885 10.200 +*N chanx_right_out[1]:6 *C 94.263 10.200 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 chanx_right_out[1] 0.0005601419 +2 chanx_right_out[1]:2 0.0005601419 +3 chanx_right_out[1]:3 4.695044e-05 +4 chanx_right_out[1]:4 4.695044e-05 +5 chanx_right_out[1]:5 5.215083e-05 +6 chanx_right_out[1]:6 5.215083e-05 + +*RES +0 ropt_mt_inst_795:X chanx_right_out[1]:6 0.152 +1 chanx_right_out[1]:6 chanx_right_out[1]:5 0.0003370536 +2 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +3 chanx_right_out[1]:4 chanx_right_out[1]:3 0.000515625 +4 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +5 chanx_right_out[1]:2 chanx_right_out[1] 0.001535725 + +*END + +*D_NET chanx_left_in[14] 0.0223602 //LENGTH 137.020 LUMPCC 0.008977968 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 20.400 +*I mux_bottom_ipin_10\/mux_l2_in_2_:A0 I *L 0.001631 *C 19.990 22.440 +*I mux_bottom_ipin_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 38.470 21.080 +*I mux_bottom_ipin_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 59.170 21.080 +*I FTB_15__14:A I *L 0.001776 *C 94.760 58.480 +*N chanx_left_in[14]:5 *C 94.723 58.480 +*N chanx_left_in[14]:6 *C 93.425 58.480 +*N chanx_left_in[14]:7 *C 93.380 58.435 +*N chanx_left_in[14]:8 *C 93.380 56.498 +*N chanx_left_in[14]:9 *C 93.373 56.440 +*N chanx_left_in[14]:10 *C 62.580 56.440 +*N chanx_left_in[14]:11 *C 62.560 56.433 +*N chanx_left_in[14]:12 *C 62.560 21.088 +*N chanx_left_in[14]:13 *C 62.540 21.080 +*N chanx_left_in[14]:14 *C 59.170 21.080 +*N chanx_left_in[14]:15 *C 59.340 21.080 +*N chanx_left_in[14]:16 *C 59.340 21.080 +*N chanx_left_in[14]:17 *C 59.340 21.080 +*N chanx_left_in[14]:18 *C 38.470 21.080 +*N chanx_left_in[14]:19 *C 38.180 21.080 +*N chanx_left_in[14]:20 *C 38.180 21.080 +*N chanx_left_in[14]:21 *C 38.180 21.080 +*N chanx_left_in[14]:22 *C 38.180 20.400 +*N chanx_left_in[14]:23 *C 19.990 22.440 +*N chanx_left_in[14]:24 *C 20.240 22.440 +*N chanx_left_in[14]:25 *C 20.240 22.395 +*N chanx_left_in[14]:26 *C 20.240 20.457 +*N chanx_left_in[14]:27 *C 20.240 20.400 + +*CAP +0 chanx_left_in[14] 0.001334501 +1 mux_bottom_ipin_10\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_2\/mux_l2_in_2_:A0 1e-06 +3 mux_bottom_ipin_4\/mux_l2_in_2_:A0 1e-06 +4 FTB_15__14:A 1e-06 +5 chanx_left_in[14]:5 0.0001129267 +6 chanx_left_in[14]:6 0.0001129267 +7 chanx_left_in[14]:7 0.000154429 +8 chanx_left_in[14]:8 0.000154429 +9 chanx_left_in[14]:9 0.0009534263 +10 chanx_left_in[14]:10 0.0009534263 +11 chanx_left_in[14]:11 0.002226846 +12 chanx_left_in[14]:12 0.002226846 +13 chanx_left_in[14]:13 0.0003020904 +14 chanx_left_in[14]:14 5.317165e-05 +15 chanx_left_in[14]:15 5.583785e-05 +16 chanx_left_in[14]:16 3.776207e-05 +17 chanx_left_in[14]:17 0.001049269 +18 chanx_left_in[14]:18 4.911351e-05 +19 chanx_left_in[14]:19 5.087873e-05 +20 chanx_left_in[14]:20 4.085986e-05 +21 chanx_left_in[14]:21 0.0007954754 +22 chanx_left_in[14]:22 0.0005644434 +23 chanx_left_in[14]:23 5.649297e-05 +24 chanx_left_in[14]:24 5.782013e-05 +25 chanx_left_in[14]:25 9.230481e-05 +26 chanx_left_in[14]:26 9.230481e-05 +27 chanx_left_in[14]:27 0.001850648 +28 chanx_left_in[14]:10 chanx_left_in[13]:13 0.0001447252 +29 chanx_left_in[14]:10 chanx_left_in[13]:14 0.0005154698 +30 chanx_left_in[14]:9 chanx_left_in[13]:8 0.0001447252 +31 chanx_left_in[14]:9 chanx_left_in[13]:13 0.0005154698 +32 chanx_left_in[14]:10 chanx_right_in[1]:43 0.0003115681 +33 chanx_left_in[14]:10 chanx_right_in[1]:37 0.0001630638 +34 chanx_left_in[14]:9 chanx_right_in[1]:43 0.0001630638 +35 chanx_left_in[14]:9 chanx_right_in[1]:44 0.0003115681 +36 chanx_left_in[14] chanx_right_in[2]:27 1.132628e-05 +37 chanx_left_in[14] chanx_right_in[2]:23 4.221411e-05 +38 chanx_left_in[14]:13 chanx_right_in[2]:40 4.775416e-05 +39 chanx_left_in[14]:10 chanx_right_in[2]:58 0.0005432105 +40 chanx_left_in[14]:9 chanx_right_in[2] 0.0005432105 +41 chanx_left_in[14]:21 chanx_right_in[2]:27 0.0001447042 +42 chanx_left_in[14]:21 chanx_right_in[2]:37 0.0005469696 +43 chanx_left_in[14]:21 chanx_right_in[2]:39 9.560572e-05 +44 chanx_left_in[14]:26 chanx_right_in[2]:25 4.178823e-06 +45 chanx_left_in[14]:27 chanx_right_in[2]:27 9.065453e-05 +46 chanx_left_in[14]:27 chanx_right_in[2]:36 1.132628e-05 +47 chanx_left_in[14]:25 chanx_right_in[2]:26 4.178823e-06 +48 chanx_left_in[14]:17 chanx_right_in[2]:40 9.560572e-05 +49 chanx_left_in[14]:17 chanx_right_in[2]:36 0.0001447042 +50 chanx_left_in[14]:17 chanx_right_in[2]:38 0.0005469696 +51 chanx_left_in[14]:17 chanx_right_in[2]:39 4.775416e-05 +52 chanx_left_in[14]:22 chanx_right_in[2]:36 4.844042e-05 +53 chanx_left_in[14] chanx_right_in[6]:21 3.513008e-05 +54 chanx_left_in[14]:21 chanx_right_in[6]:23 5.988435e-06 +55 chanx_left_in[14]:21 chanx_right_in[6]:26 1.609264e-05 +56 chanx_left_in[14]:19 chanx_right_in[6]:26 5.405198e-06 +57 chanx_left_in[14]:18 chanx_right_in[6]:27 5.405198e-06 +58 chanx_left_in[14]:26 chanx_right_in[6]:20 4.397908e-05 +59 chanx_left_in[14]:27 chanx_right_in[6]:21 0.0008003549 +60 chanx_left_in[14]:27 chanx_right_in[6]:22 3.513008e-05 +61 chanx_left_in[14]:24 chanx_right_in[6]:7 1.737713e-06 +62 chanx_left_in[14]:24 chanx_right_in[6]:17 2.336528e-07 +63 chanx_left_in[14]:25 chanx_right_in[6]:19 4.397908e-05 +64 chanx_left_in[14]:23 chanx_right_in[6]:18 1.737713e-06 +65 chanx_left_in[14]:23 chanx_right_in[6]:16 2.336528e-07 +66 chanx_left_in[14]:17 chanx_right_in[6]:27 1.609264e-05 +67 chanx_left_in[14]:22 chanx_right_in[6]:22 0.0008003549 +68 chanx_left_in[14]:22 chanx_right_in[6]:24 5.988435e-06 +69 chanx_left_in[14]:21 chanx_right_in[14]:32 1.217404e-06 +70 chanx_left_in[14]:21 chanx_right_in[14]:28 0.000265763 +71 chanx_left_in[14]:21 chanx_right_in[14]:21 8.888706e-05 +72 chanx_left_in[14]:27 chanx_right_in[14]:21 0.0006049639 +73 chanx_left_in[14]:17 chanx_right_in[14]:29 0.000265763 +74 chanx_left_in[14]:17 chanx_right_in[14]:33 1.217404e-06 +75 chanx_left_in[14]:17 chanx_right_in[14]:28 8.888706e-05 +76 chanx_left_in[14]:22 chanx_right_in[14]:28 0.0006049639 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:27 0.002978233 +1 chanx_left_in[14]:13 chanx_left_in[14]:12 0.00341 +2 chanx_left_in[14]:12 chanx_left_in[14]:11 0.005537383 +3 chanx_left_in[14]:10 chanx_left_in[14]:9 0.004824158 +4 chanx_left_in[14]:11 chanx_left_in[14]:10 0.00341 +5 chanx_left_in[14]:8 chanx_left_in[14]:7 0.001729911 +6 chanx_left_in[14]:9 chanx_left_in[14]:8 0.00341 +7 chanx_left_in[14]:6 chanx_left_in[14]:5 0.001158482 +8 chanx_left_in[14]:7 chanx_left_in[14]:6 0.0045 +9 chanx_left_in[14]:5 FTB_15__14:A 0.152 +10 chanx_left_in[14]:20 chanx_left_in[14]:19 0.0045 +11 chanx_left_in[14]:21 chanx_left_in[14]:20 0.00341 +12 chanx_left_in[14]:21 chanx_left_in[14]:17 0.003315066 +13 chanx_left_in[14]:19 chanx_left_in[14]:18 0.0001576087 +14 chanx_left_in[14]:18 mux_bottom_ipin_2\/mux_l2_in_2_:A0 0.152 +15 chanx_left_in[14]:26 chanx_left_in[14]:25 0.001729911 +16 chanx_left_in[14]:27 chanx_left_in[14]:26 0.00341 +17 chanx_left_in[14]:27 chanx_left_in[14]:22 0.0028106 +18 chanx_left_in[14]:24 chanx_left_in[14]:23 0.0001358696 +19 chanx_left_in[14]:25 chanx_left_in[14]:24 0.0045 +20 chanx_left_in[14]:23 mux_bottom_ipin_10\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[14]:16 chanx_left_in[14]:15 0.0045 +22 chanx_left_in[14]:17 chanx_left_in[14]:16 0.00341 +23 chanx_left_in[14]:17 chanx_left_in[14]:13 0.0005013334 +24 chanx_left_in[14]:15 chanx_left_in[14]:14 9.239131e-05 +25 chanx_left_in[14]:14 mux_bottom_ipin_4\/mux_l2_in_2_:A0 0.152 +26 chanx_left_in[14]:22 chanx_left_in[14]:21 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[3] 0.003762695 //LENGTH 28.605 LUMPCC 0.0005324903 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 66.545 44.880 +*I mux_bottom_ipin_5\/mux_l4_in_0_:S I *L 0.00357 *C 51.060 50.505 +*I mem_bottom_ipin_5\/FTB_4__43:A I *L 0.001746 *C 69.000 42.160 +*N mux_tree_tapbuf_size10_3_sram[3]:3 *C 69.000 42.160 +*N mux_tree_tapbuf_size10_3_sram[3]:4 *C 69.000 42.205 +*N mux_tree_tapbuf_size10_3_sram[3]:5 *C 69.000 44.835 +*N mux_tree_tapbuf_size10_3_sram[3]:6 *C 68.955 44.880 +*N mux_tree_tapbuf_size10_3_sram[3]:7 *C 51.060 50.505 +*N mux_tree_tapbuf_size10_3_sram[3]:8 *C 51.060 50.660 +*N mux_tree_tapbuf_size10_3_sram[3]:9 *C 51.060 50.615 +*N mux_tree_tapbuf_size10_3_sram[3]:10 *C 51.060 45.617 +*N mux_tree_tapbuf_size10_3_sram[3]:11 *C 51.068 45.560 +*N mux_tree_tapbuf_size10_3_sram[3]:12 *C 66.538 45.560 +*N mux_tree_tapbuf_size10_3_sram[3]:13 *C 66.545 45.503 +*N mux_tree_tapbuf_size10_3_sram[3]:14 *C 66.545 44.925 +*N mux_tree_tapbuf_size10_3_sram[3]:15 *C 66.545 44.880 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_ipin_5\/FTB_4__43:A 1e-06 +3 mux_tree_tapbuf_size10_3_sram[3]:3 3.407503e-05 +4 mux_tree_tapbuf_size10_3_sram[3]:4 0.0001639998 +5 mux_tree_tapbuf_size10_3_sram[3]:5 0.0001639998 +6 mux_tree_tapbuf_size10_3_sram[3]:6 0.0001665513 +7 mux_tree_tapbuf_size10_3_sram[3]:7 5.568033e-05 +8 mux_tree_tapbuf_size10_3_sram[3]:8 5.144527e-05 +9 mux_tree_tapbuf_size10_3_sram[3]:9 0.0003084052 +10 mux_tree_tapbuf_size10_3_sram[3]:10 0.0003084052 +11 mux_tree_tapbuf_size10_3_sram[3]:11 0.0008205023 +12 mux_tree_tapbuf_size10_3_sram[3]:12 0.0008205023 +13 mux_tree_tapbuf_size10_3_sram[3]:13 6.52234e-05 +14 mux_tree_tapbuf_size10_3_sram[3]:14 6.52234e-05 +15 mux_tree_tapbuf_size10_3_sram[3]:15 0.000203191 +16 mux_tree_tapbuf_size10_3_sram[3]:11 chanx_left_in[9]:17 0.0001247602 +17 mux_tree_tapbuf_size10_3_sram[3]:11 chanx_left_in[9]:18 0.0001414849 +18 mux_tree_tapbuf_size10_3_sram[3]:12 chanx_left_in[9]:12 0.0001247602 +19 mux_tree_tapbuf_size10_3_sram[3]:12 chanx_left_in[9]:17 0.0001414849 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_3_sram[3]:15 0.152 +1 mux_tree_tapbuf_size10_3_sram[3]:15 mux_tree_tapbuf_size10_3_sram[3]:14 0.0045 +2 mux_tree_tapbuf_size10_3_sram[3]:15 mux_tree_tapbuf_size10_3_sram[3]:6 0.002151786 +3 mux_tree_tapbuf_size10_3_sram[3]:6 mux_tree_tapbuf_size10_3_sram[3]:5 0.0045 +4 mux_tree_tapbuf_size10_3_sram[3]:5 mux_tree_tapbuf_size10_3_sram[3]:4 0.002348214 +5 mux_tree_tapbuf_size10_3_sram[3]:3 mem_bottom_ipin_5\/FTB_4__43:A 0.152 +6 mux_tree_tapbuf_size10_3_sram[3]:4 mux_tree_tapbuf_size10_3_sram[3]:3 0.0045 +7 mux_tree_tapbuf_size10_3_sram[3]:7 mux_bottom_ipin_5\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_3_sram[3]:8 mux_tree_tapbuf_size10_3_sram[3]:7 8.423914e-05 +9 mux_tree_tapbuf_size10_3_sram[3]:9 mux_tree_tapbuf_size10_3_sram[3]:8 0.0045 +10 mux_tree_tapbuf_size10_3_sram[3]:10 mux_tree_tapbuf_size10_3_sram[3]:9 0.004462054 +11 mux_tree_tapbuf_size10_3_sram[3]:11 mux_tree_tapbuf_size10_3_sram[3]:10 0.00341 +12 mux_tree_tapbuf_size10_3_sram[3]:13 mux_tree_tapbuf_size10_3_sram[3]:12 0.00341 +13 mux_tree_tapbuf_size10_3_sram[3]:12 mux_tree_tapbuf_size10_3_sram[3]:11 0.002423633 +14 mux_tree_tapbuf_size10_3_sram[3]:14 mux_tree_tapbuf_size10_3_sram[3]:13 0.000515625 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[0] 0.00328093 //LENGTH 25.035 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 68.385 20.400 +*I mux_bottom_ipin_12\/mux_l1_in_2_:S I *L 0.00357 *C 72.580 17.680 +*I mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 70.095 15.300 +*I mux_bottom_ipin_12\/mux_l1_in_0_:S I *L 0.00357 *C 73.960 29.240 +*I mux_bottom_ipin_12\/mux_l1_in_1_:S I *L 0.00357 *C 72.120 23.415 +*N mux_tree_tapbuf_size10_6_sram[0]:5 *C 72.120 23.415 +*N mux_tree_tapbuf_size10_6_sram[0]:6 *C 72.062 23.120 +*N mux_tree_tapbuf_size10_6_sram[0]:7 *C 73.922 29.240 +*N mux_tree_tapbuf_size10_6_sram[0]:8 *C 72.265 29.240 +*N mux_tree_tapbuf_size10_6_sram[0]:9 *C 72.220 29.195 +*N mux_tree_tapbuf_size10_6_sram[0]:10 *C 72.220 23.165 +*N mux_tree_tapbuf_size10_6_sram[0]:11 *C 72.163 23.150 +*N mux_tree_tapbuf_size10_6_sram[0]:12 *C 70.425 23.120 +*N mux_tree_tapbuf_size10_6_sram[0]:13 *C 70.380 23.075 +*N mux_tree_tapbuf_size10_6_sram[0]:14 *C 70.380 20.400 +*N mux_tree_tapbuf_size10_6_sram[0]:15 *C 70.095 15.300 +*N mux_tree_tapbuf_size10_6_sram[0]:16 *C 69.920 15.300 +*N mux_tree_tapbuf_size10_6_sram[0]:17 *C 69.920 15.345 +*N mux_tree_tapbuf_size10_6_sram[0]:18 *C 72.543 17.680 +*N mux_tree_tapbuf_size10_6_sram[0]:19 *C 69.965 17.680 +*N mux_tree_tapbuf_size10_6_sram[0]:20 *C 69.920 17.680 +*N mux_tree_tapbuf_size10_6_sram[0]:21 *C 69.920 20.400 +*N mux_tree_tapbuf_size10_6_sram[0]:22 *C 69.875 20.400 +*N mux_tree_tapbuf_size10_6_sram[0]:23 *C 68.422 20.400 + +*CAP +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_12\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_ipin_12\/mux_l1_in_0_:S 1e-06 +4 mux_bottom_ipin_12\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_6_sram[0]:5 5.336003e-05 +6 mux_tree_tapbuf_size10_6_sram[0]:6 2.058757e-05 +7 mux_tree_tapbuf_size10_6_sram[0]:7 0.0001457998 +8 mux_tree_tapbuf_size10_6_sram[0]:8 0.0001457998 +9 mux_tree_tapbuf_size10_6_sram[0]:9 0.0003618568 +10 mux_tree_tapbuf_size10_6_sram[0]:10 0.0003618568 +11 mux_tree_tapbuf_size10_6_sram[0]:11 0.0001674597 +12 mux_tree_tapbuf_size10_6_sram[0]:12 0.0001227331 +13 mux_tree_tapbuf_size10_6_sram[0]:13 0.0001831275 +14 mux_tree_tapbuf_size10_6_sram[0]:14 0.0002168449 +15 mux_tree_tapbuf_size10_6_sram[0]:15 5.051841e-05 +16 mux_tree_tapbuf_size10_6_sram[0]:16 5.39815e-05 +17 mux_tree_tapbuf_size10_6_sram[0]:17 0.0001430074 +18 mux_tree_tapbuf_size10_6_sram[0]:18 0.0002319316 +19 mux_tree_tapbuf_size10_6_sram[0]:19 0.0002319316 +20 mux_tree_tapbuf_size10_6_sram[0]:20 0.0003624455 +21 mux_tree_tapbuf_size10_6_sram[0]:21 0.0002219882 +22 mux_tree_tapbuf_size10_6_sram[0]:22 0.0001003501 +23 mux_tree_tapbuf_size10_6_sram[0]:23 0.0001003501 + +*RES +0 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_6_sram[0]:23 0.152 +1 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:6 8.928572e-05 +3 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:5 0.0001142241 +4 mux_tree_tapbuf_size10_6_sram[0]:10 mux_tree_tapbuf_size10_6_sram[0]:9 0.005383929 +5 mux_tree_tapbuf_size10_6_sram[0]:8 mux_tree_tapbuf_size10_6_sram[0]:7 0.001479911 +6 mux_tree_tapbuf_size10_6_sram[0]:9 mux_tree_tapbuf_size10_6_sram[0]:8 0.0045 +7 mux_tree_tapbuf_size10_6_sram[0]:7 mux_bottom_ipin_12\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_6_sram[0]:5 mux_bottom_ipin_12\/mux_l1_in_1_:S 0.152 +9 mux_tree_tapbuf_size10_6_sram[0]:19 mux_tree_tapbuf_size10_6_sram[0]:18 0.00230134 +10 mux_tree_tapbuf_size10_6_sram[0]:20 mux_tree_tapbuf_size10_6_sram[0]:19 0.0045 +11 mux_tree_tapbuf_size10_6_sram[0]:20 mux_tree_tapbuf_size10_6_sram[0]:17 0.002084821 +12 mux_tree_tapbuf_size10_6_sram[0]:18 mux_bottom_ipin_12\/mux_l1_in_2_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[0]:12 mux_tree_tapbuf_size10_6_sram[0]:11 0.001551339 +14 mux_tree_tapbuf_size10_6_sram[0]:13 mux_tree_tapbuf_size10_6_sram[0]:12 0.0045 +15 mux_tree_tapbuf_size10_6_sram[0]:16 mux_tree_tapbuf_size10_6_sram[0]:15 9.51087e-05 +16 mux_tree_tapbuf_size10_6_sram[0]:17 mux_tree_tapbuf_size10_6_sram[0]:16 0.0045 +17 mux_tree_tapbuf_size10_6_sram[0]:15 mem_bottom_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size10_6_sram[0]:22 mux_tree_tapbuf_size10_6_sram[0]:21 0.0045 +19 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:20 0.002428571 +20 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:14 0.0004107143 +21 mux_tree_tapbuf_size10_6_sram[0]:23 mux_tree_tapbuf_size10_6_sram[0]:22 0.001296875 +22 mux_tree_tapbuf_size10_6_sram[0]:14 mux_tree_tapbuf_size10_6_sram[0]:13 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_6_ccff_tail[0] 0.0006555294 //LENGTH 5.180 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_12\/FTB_7__46:X O *L 0 *C 88.095 23.120 +*I mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 86.655 26.180 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 *C 86.693 26.180 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 *C 87.815 26.180 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 *C 87.860 26.135 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 *C 87.860 23.165 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 *C 87.860 23.120 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 *C 88.095 23.120 + +*CAP +0 mem_bottom_ipin_12\/FTB_7__46:X 1e-06 +1 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.0001008462 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0001008462 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.0001757591 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0001757591 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 5.134539e-05 +7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 4.897342e-05 + +*RES +0 mem_bottom_ipin_12\/FTB_7__46:X mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.001002232 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 mem_bottom_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[2] 0.001872762 //LENGTH 13.950 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 36.185 42.500 +*I mux_bottom_ipin_3\/mux_l3_in_0_:S I *L 0.00357 *C 34.400 45.220 +*I mux_bottom_ipin_3\/mux_l3_in_1_:S I *L 0.00357 *C 39.200 45.175 +*I mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 41.115 47.940 +*N mux_tree_tapbuf_size8_1_sram[2]:4 *C 41.115 47.940 +*N mux_tree_tapbuf_size8_1_sram[2]:5 *C 40.940 47.940 +*N mux_tree_tapbuf_size8_1_sram[2]:6 *C 40.940 47.895 +*N mux_tree_tapbuf_size8_1_sram[2]:7 *C 40.940 45.605 +*N mux_tree_tapbuf_size8_1_sram[2]:8 *C 40.895 45.560 +*N mux_tree_tapbuf_size8_1_sram[2]:9 *C 39.200 45.560 +*N mux_tree_tapbuf_size8_1_sram[2]:10 *C 39.200 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:11 *C 34.438 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:12 *C 36.340 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:13 *C 36.340 45.175 +*N mux_tree_tapbuf_size8_1_sram[2]:14 *C 36.340 42.545 +*N mux_tree_tapbuf_size8_1_sram[2]:15 *C 36.340 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:16 *C 36.185 42.500 + +*CAP +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_ipin_3\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_1_sram[2]:4 4.551287e-05 +5 mux_tree_tapbuf_size8_1_sram[2]:5 4.991978e-05 +6 mux_tree_tapbuf_size8_1_sram[2]:6 0.0001555406 +7 mux_tree_tapbuf_size8_1_sram[2]:7 0.0001555406 +8 mux_tree_tapbuf_size8_1_sram[2]:8 0.0001477241 +9 mux_tree_tapbuf_size8_1_sram[2]:9 0.0001810668 +10 mux_tree_tapbuf_size8_1_sram[2]:10 0.0002139591 +11 mux_tree_tapbuf_size8_1_sram[2]:11 0.0001282986 +12 mux_tree_tapbuf_size8_1_sram[2]:12 0.0003398315 +13 mux_tree_tapbuf_size8_1_sram[2]:13 0.0001707782 +14 mux_tree_tapbuf_size8_1_sram[2]:14 0.0001707782 +15 mux_tree_tapbuf_size8_1_sram[2]:15 5.716812e-05 +16 mux_tree_tapbuf_size8_1_sram[2]:16 5.264304e-05 + +*RES +0 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_1_sram[2]:16 0.152 +1 mux_tree_tapbuf_size8_1_sram[2]:8 mux_tree_tapbuf_size8_1_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size8_1_sram[2]:7 mux_tree_tapbuf_size8_1_sram[2]:6 0.002044643 +3 mux_tree_tapbuf_size8_1_sram[2]:5 mux_tree_tapbuf_size8_1_sram[2]:4 9.51087e-05 +4 mux_tree_tapbuf_size8_1_sram[2]:6 mux_tree_tapbuf_size8_1_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size8_1_sram[2]:4 mem_bottom_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size8_1_sram[2]:11 mux_bottom_ipin_3\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_1_sram[2]:10 mux_bottom_ipin_3\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:9 0.0003035715 +9 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:11 0.001698661 +10 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:10 0.002553571 +11 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:12 0.0045 +12 mux_tree_tapbuf_size8_1_sram[2]:15 mux_tree_tapbuf_size8_1_sram[2]:14 0.0045 +13 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:13 0.002348214 +14 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:15 8.423914e-05 +15 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:8 0.001513393 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[2] 0.001732848 //LENGTH 13.585 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 14.565 15.300 +*I mux_bottom_ipin_10\/mux_l3_in_0_:S I *L 0.00357 *C 13.700 18.360 +*I mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 17.655 15.300 +*I mux_bottom_ipin_10\/mux_l3_in_1_:S I *L 0.00357 *C 20.340 18.020 +*N mux_tree_tapbuf_size8_4_sram[2]:4 *C 20.303 18.020 +*N mux_tree_tapbuf_size8_4_sram[2]:5 *C 19.365 18.020 +*N mux_tree_tapbuf_size8_4_sram[2]:6 *C 19.320 17.975 +*N mux_tree_tapbuf_size8_4_sram[2]:7 *C 19.320 15.345 +*N mux_tree_tapbuf_size8_4_sram[2]:8 *C 19.275 15.300 +*N mux_tree_tapbuf_size8_4_sram[2]:9 *C 17.655 15.300 +*N mux_tree_tapbuf_size8_4_sram[2]:10 *C 13.700 18.360 +*N mux_tree_tapbuf_size8_4_sram[2]:11 *C 13.800 18.315 +*N mux_tree_tapbuf_size8_4_sram[2]:12 *C 13.800 15.345 +*N mux_tree_tapbuf_size8_4_sram[2]:13 *C 13.845 15.300 +*N mux_tree_tapbuf_size8_4_sram[2]:14 *C 14.565 15.300 + +*CAP +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_10\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_ipin_10\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_4_sram[2]:4 0.0001014724 +5 mux_tree_tapbuf_size8_4_sram[2]:5 0.0001014724 +6 mux_tree_tapbuf_size8_4_sram[2]:6 0.0001665512 +7 mux_tree_tapbuf_size8_4_sram[2]:7 0.0001665512 +8 mux_tree_tapbuf_size8_4_sram[2]:8 0.0001085474 +9 mux_tree_tapbuf_size8_4_sram[2]:9 0.0003297684 +10 mux_tree_tapbuf_size8_4_sram[2]:10 2.741499e-05 +11 mux_tree_tapbuf_size8_4_sram[2]:11 0.000192495 +12 mux_tree_tapbuf_size8_4_sram[2]:12 0.000192495 +13 mux_tree_tapbuf_size8_4_sram[2]:13 5.824378e-05 +14 mux_tree_tapbuf_size8_4_sram[2]:14 0.0002838362 + +*RES +0 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_4_sram[2]:14 0.152 +1 mux_tree_tapbuf_size8_4_sram[2]:4 mux_bottom_ipin_10\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_4_sram[2]:5 mux_tree_tapbuf_size8_4_sram[2]:4 0.0008370536 +3 mux_tree_tapbuf_size8_4_sram[2]:6 mux_tree_tapbuf_size8_4_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size8_4_sram[2]:8 mux_tree_tapbuf_size8_4_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size8_4_sram[2]:7 mux_tree_tapbuf_size8_4_sram[2]:6 0.002348214 +6 mux_tree_tapbuf_size8_4_sram[2]:9 mem_bottom_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_4_sram[2]:8 0.001446429 +8 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_4_sram[2]:13 0.0006428572 +9 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_4_sram[2]:9 0.002758929 +10 mux_tree_tapbuf_size8_4_sram[2]:13 mux_tree_tapbuf_size8_4_sram[2]:12 0.0045 +11 mux_tree_tapbuf_size8_4_sram[2]:12 mux_tree_tapbuf_size8_4_sram[2]:11 0.002651786 +12 mux_tree_tapbuf_size8_4_sram[2]:10 mux_bottom_ipin_10\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size8_4_sram[2]:11 mux_tree_tapbuf_size8_4_sram[2]:10 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[2] 0.004532882 //LENGTH 32.860 LUMPCC 0.0007677746 DR + +*CONN +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 71.145 69.360 +*I mux_bottom_ipin_15\/mux_l3_in_1_:S I *L 0.00357 *C 68.180 63.240 +*I mux_bottom_ipin_15\/mux_l3_in_0_:S I *L 0.00357 *C 63.380 63.630 +*I mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 56.755 69.700 +*N mux_tree_tapbuf_size8_7_sram[2]:4 *C 56.755 69.700 +*N mux_tree_tapbuf_size8_7_sram[2]:5 *C 57.040 69.700 +*N mux_tree_tapbuf_size8_7_sram[2]:6 *C 57.040 69.655 +*N mux_tree_tapbuf_size8_7_sram[2]:7 *C 57.040 68.737 +*N mux_tree_tapbuf_size8_7_sram[2]:8 *C 57.047 68.680 +*N mux_tree_tapbuf_size8_7_sram[2]:9 *C 63.380 63.630 +*N mux_tree_tapbuf_size8_7_sram[2]:10 *C 68.142 63.240 +*N mux_tree_tapbuf_size8_7_sram[2]:11 *C 63.380 63.240 +*N mux_tree_tapbuf_size8_7_sram[2]:12 *C 59.385 63.240 +*N mux_tree_tapbuf_size8_7_sram[2]:13 *C 59.340 63.285 +*N mux_tree_tapbuf_size8_7_sram[2]:14 *C 59.340 68.623 +*N mux_tree_tapbuf_size8_7_sram[2]:15 *C 59.340 68.680 +*N mux_tree_tapbuf_size8_7_sram[2]:16 *C 68.080 68.680 +*N mux_tree_tapbuf_size8_7_sram[2]:17 *C 68.080 69.360 +*N mux_tree_tapbuf_size8_7_sram[2]:18 *C 70.833 69.360 +*N mux_tree_tapbuf_size8_7_sram[2]:19 *C 70.840 69.360 +*N mux_tree_tapbuf_size8_7_sram[2]:20 *C 70.840 69.360 +*N mux_tree_tapbuf_size8_7_sram[2]:21 *C 71.145 69.360 + +*CAP +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_15\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_15\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_7_sram[2]:4 5.227583e-05 +5 mux_tree_tapbuf_size8_7_sram[2]:5 5.78992e-05 +6 mux_tree_tapbuf_size8_7_sram[2]:6 6.279418e-05 +7 mux_tree_tapbuf_size8_7_sram[2]:7 6.279418e-05 +8 mux_tree_tapbuf_size8_7_sram[2]:8 9.18786e-05 +9 mux_tree_tapbuf_size8_7_sram[2]:9 5.832805e-05 +10 mux_tree_tapbuf_size8_7_sram[2]:10 0.0003156693 +11 mux_tree_tapbuf_size8_7_sram[2]:11 0.0006328702 +12 mux_tree_tapbuf_size8_7_sram[2]:12 0.0002871987 +13 mux_tree_tapbuf_size8_7_sram[2]:13 0.0003052121 +14 mux_tree_tapbuf_size8_7_sram[2]:14 0.0003052121 +15 mux_tree_tapbuf_size8_7_sram[2]:15 0.0004993178 +16 mux_tree_tapbuf_size8_7_sram[2]:16 0.000460406 +17 mux_tree_tapbuf_size8_7_sram[2]:17 0.0002455823 +18 mux_tree_tapbuf_size8_7_sram[2]:18 0.0001926156 +19 mux_tree_tapbuf_size8_7_sram[2]:19 3.367792e-05 +20 mux_tree_tapbuf_size8_7_sram[2]:20 5.053217e-05 +21 mux_tree_tapbuf_size8_7_sram[2]:21 4.684322e-05 +22 mux_tree_tapbuf_size8_7_sram[2]:14 prog_clk[0]:176 1.075369e-06 +23 mux_tree_tapbuf_size8_7_sram[2]:15 prog_clk[0]:172 0.0001353528 +24 mux_tree_tapbuf_size8_7_sram[2]:15 prog_clk[0]:173 0.0002397102 +25 mux_tree_tapbuf_size8_7_sram[2]:13 prog_clk[0]:177 1.075369e-06 +26 mux_tree_tapbuf_size8_7_sram[2]:7 prog_clk[0]:177 7.748968e-06 +27 mux_tree_tapbuf_size8_7_sram[2]:8 prog_clk[0]:173 0.0001353528 +28 mux_tree_tapbuf_size8_7_sram[2]:6 prog_clk[0]:176 7.748968e-06 +29 mux_tree_tapbuf_size8_7_sram[2]:16 prog_clk[0]:172 0.0002397102 + +*RES +0 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_7_sram[2]:21 0.152 +1 mux_tree_tapbuf_size8_7_sram[2]:14 mux_tree_tapbuf_size8_7_sram[2]:13 0.004765625 +2 mux_tree_tapbuf_size8_7_sram[2]:15 mux_tree_tapbuf_size8_7_sram[2]:14 0.00341 +3 mux_tree_tapbuf_size8_7_sram[2]:15 mux_tree_tapbuf_size8_7_sram[2]:8 0.0003591583 +4 mux_tree_tapbuf_size8_7_sram[2]:12 mux_tree_tapbuf_size8_7_sram[2]:11 0.003566965 +5 mux_tree_tapbuf_size8_7_sram[2]:13 mux_tree_tapbuf_size8_7_sram[2]:12 0.0045 +6 mux_tree_tapbuf_size8_7_sram[2]:10 mux_bottom_ipin_15\/mux_l3_in_1_:S 0.152 +7 mux_tree_tapbuf_size8_7_sram[2]:9 mux_bottom_ipin_15\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_7_sram[2]:7 mux_tree_tapbuf_size8_7_sram[2]:6 0.0008191965 +9 mux_tree_tapbuf_size8_7_sram[2]:8 mux_tree_tapbuf_size8_7_sram[2]:7 0.00341 +10 mux_tree_tapbuf_size8_7_sram[2]:5 mux_tree_tapbuf_size8_7_sram[2]:4 0.0001548913 +11 mux_tree_tapbuf_size8_7_sram[2]:6 mux_tree_tapbuf_size8_7_sram[2]:5 0.0045 +12 mux_tree_tapbuf_size8_7_sram[2]:4 mem_bottom_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size8_7_sram[2]:19 mux_tree_tapbuf_size8_7_sram[2]:18 0.00341 +14 mux_tree_tapbuf_size8_7_sram[2]:18 mux_tree_tapbuf_size8_7_sram[2]:17 0.000431225 +15 mux_tree_tapbuf_size8_7_sram[2]:20 mux_tree_tapbuf_size8_7_sram[2]:19 0.0045 +16 mux_tree_tapbuf_size8_7_sram[2]:21 mux_tree_tapbuf_size8_7_sram[2]:20 0.0001657609 +17 mux_tree_tapbuf_size8_7_sram[2]:11 mux_tree_tapbuf_size8_7_sram[2]:10 0.004252233 +18 mux_tree_tapbuf_size8_7_sram[2]:11 mux_tree_tapbuf_size8_7_sram[2]:9 0.0003482143 +19 mux_tree_tapbuf_size8_7_sram[2]:16 mux_tree_tapbuf_size8_7_sram[2]:15 0.001369267 +20 mux_tree_tapbuf_size8_7_sram[2]:17 mux_tree_tapbuf_size8_7_sram[2]:16 0.0001065333 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001214449 //LENGTH 8.290 LUMPCC 0.0003373779 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l1_in_2_:X O *L 0 *C 60.435 50.660 +*I mux_bottom_ipin_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 58.785 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 58.823 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 60.675 56.100 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 60.720 56.055 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 60.720 50.705 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 60.720 50.660 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 60.435 50.660 + +*CAP +0 mux_bottom_ipin_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001009441 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001009441 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002739584 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002739584 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.345927e-05 +7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.180727e-05 +8 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:25 8.170692e-05 +9 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:26 8.170692e-05 +10 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_3_sram[0]:14 8.698201e-05 +11 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_3_sram[0]:17 8.698201e-05 + +*RES +0 mux_bottom_ipin_1\/mux_l1_in_2_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_1\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001654018 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0002926829 //LENGTH 2.425 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l1_in_1_:X O *L 0 *C 46.745 22.780 +*I mux_bottom_ipin_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 48.880 22.780 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 48.843 22.780 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 46.782 22.780 + +*CAP +0 mux_bottom_ipin_4\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001453414 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001453414 + +*RES +0 mux_bottom_ipin_4\/mux_l1_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001839286 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_4\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005807085 //LENGTH 45.705 LUMPCC 0.0008421962 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l4_in_0_:X O *L 0 *C 56.865 28.900 +*I mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 57.575 71.895 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 57.575 71.895 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 57.500 71.740 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 57.500 71.740 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 57.500 71.400 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 57.498 71.400 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 57.055 71.400 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 57.040 71.392 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 57.040 31.968 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 57.025 31.960 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 56.583 31.960 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 56.580 31.902 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 56.580 28.945 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 56.580 28.900 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 56.865 28.900 + +*CAP +0 mux_bottom_ipin_4\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.046366e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.506788e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.604852e-05 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 5.241593e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.294899e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.294899e-05 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.002019839 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.002019839 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 5.87194e-05 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.87194e-05 +12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0002043835 +13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0002043835 +14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.974792e-05 +15 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 4.73628e-05 +16 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:12 1.028548e-06 +17 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:11 1.028548e-06 +18 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004200695 +19 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004200695 + +*RES +0 mux_bottom_ipin_4\/mux_l4_in_0_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0001548913 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.002640625 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 6.499219e-05 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.006176583 +8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.499219e-05 +9 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +10 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001634616 +11 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +12 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.076087e-05 +13 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +14 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_ipin_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001759479 //LENGTH 12.940 LUMPCC 0.0007553413 DR + +*CONN +*I mux_bottom_ipin_9\/mux_l1_in_2_:X O *L 0 *C 15.925 44.880 +*I mux_bottom_ipin_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 16.925 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 16.925 56.100 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.020 56.055 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.020 44.925 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 16.975 44.880 +*N mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 15.963 44.880 + +*CAP +0 mux_bottom_ipin_9\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_9\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.911716e-05 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003932851 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003932851 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.322504e-05 +6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.322504e-05 +7 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:325 7.62776e-05 +8 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:326 7.62776e-05 +9 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000301393 +10 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000301393 + +*RES +0 mux_bottom_ipin_9\/mux_l1_in_2_:X mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_9\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.009937501 +5 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0015334 //LENGTH 13.005 LUMPCC 0.0003524295 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l3_in_1_:X O *L 0 *C 84.005 11.900 +*I mux_bottom_ipin_12\/mux_l4_in_0_:A0 I *L 0.001631 *C 82.630 22.440 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 82.668 22.440 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 84.135 22.440 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 84.180 22.395 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 84.180 11.945 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 84.180 11.900 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 84.005 11.900 + +*CAP +0 mux_bottom_ipin_12\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.246585e-05 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 9.246585e-05 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004459027 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004459027 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.303031e-05 +7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 4.920324e-05 +8 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[2]:6 3.141259e-05 +9 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[2]:9 5.376182e-05 +10 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[2]:16 9.318325e-07 +11 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[2]:9 3.141259e-05 +12 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[2]:10 5.376182e-05 +13 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[2]:17 9.318325e-07 +14 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_6_sram[3]:3 3.168111e-05 +15 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_6_sram[3]:4 3.168111e-05 +16 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[3]:5 5.842741e-05 +17 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[3]:6 5.842741e-05 + +*RES +0 mux_bottom_ipin_12\/mux_l3_in_1_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_12\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001310268 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.009330357 +6 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008962277 //LENGTH 7.195 LUMPCC 0.0001065017 DR + +*CONN +*I mux_bottom_ipin_3\/mux_l2_in_3_:X O *L 0 *C 38.465 39.780 +*I mux_bottom_ipin_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 40.310 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 40.273 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 39.145 44.200 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 39.100 44.155 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 39.100 39.825 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 39.055 39.780 +*N mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 38.503 39.780 + +*CAP +0 mux_bottom_ipin_3\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_3\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001165719 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001165719 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002123044 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002123044 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.498667e-05 +7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.498667e-05 +8 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:198 5.325087e-05 +9 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:199 5.325087e-05 + +*RES +0 mux_bottom_ipin_3\/mux_l2_in_3_:X mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_3\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006697 +3 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006718411 //LENGTH 5.235 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l2_in_3_:X O *L 0 *C 37.895 60.860 +*I mux_bottom_ipin_7\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.950 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 32.988 60.860 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 37.858 60.860 + +*CAP +0 mux_bottom_ipin_7\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_7\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003349205 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003349205 + +*RES +0 mux_bottom_ipin_7\/mux_l2_in_3_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_7\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.004348214 + +*END + +*D_NET mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008656607 //LENGTH 6.810 LUMPCC 0.0002344112 DR + +*CONN +*I mux_bottom_ipin_11\/mux_l1_in_0_:X O *L 0 *C 27.315 52.700 +*I mux_bottom_ipin_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.965 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 27.965 47.260 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.060 47.305 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.060 52.655 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.015 52.700 +*N mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 27.353 52.700 + +*CAP +0 mux_bottom_ipin_11\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_11\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.807479e-05 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002564849 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002564849 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.410241e-05 +6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.410241e-05 +7 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[1]:40 5.677974e-06 +8 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[1]:40 3.746472e-05 +9 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[1]:10 5.677974e-06 +10 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[1]:41 3.746472e-05 +11 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[4]:23 7.406293e-05 +12 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:22 7.406293e-05 + +*RES +0 mux_bottom_ipin_11\/mux_l1_in_0_:X mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_11\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004776786 +5 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002410463 //LENGTH 17.700 LUMPCC 0.0007085689 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l1_in_0_:X O *L 0 *C 71.015 53.040 +*I mux_bottom_ipin_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 63.385 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 63.423 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 64.355 61.540 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 64.400 61.495 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 64.400 58.185 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 64.445 58.140 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 68.955 58.140 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 69.000 58.095 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 69.000 53.085 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 69.045 53.040 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 70.978 53.040 + +*CAP +0 mux_bottom_ipin_15\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001219636 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001219636 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002105402 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002105402 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001495297 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001495297 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002764736 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002764736 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.143994e-05 +11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 9.143994e-05 +12 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chanx_right_in[1]:38 4.649283e-05 +13 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chanx_right_in[1]:40 4.049376e-05 +14 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chanx_right_in[1]:39 4.049376e-05 +15 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chanx_right_in[1]:40 4.649283e-05 +16 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chanx_right_in[1]:41 2.141168e-05 +17 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[1]:42 2.141168e-05 +18 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_1_sram[1]:31 0.0001306218 +19 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_1_sram[1]:30 0.0001306218 +20 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_125:9 0.00011381 +21 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_125:32 0.00011381 +22 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_125:8 1.454388e-06 +23 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_125:7 1.454388e-06 + +*RES +0 mux_bottom_ipin_15\/mux_l1_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.001725447 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004473215 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.004026786 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002955357 +8 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325893 +9 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +10 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_15\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET ropt_net_165 0.002202208 //LENGTH 13.700 LUMPCC 0.0008066702 DR + +*CONN +*I FTB_29__28:X O *L 0 *C 7.820 18.360 +*I ropt_mt_inst_766:A I *L 0.001766 *C 3.220 23.120 +*N ropt_net_165:2 *C 2.970 17.680 +*N ropt_net_165:3 *C 3.280 23.120 +*N ropt_net_165:4 *C 3.258 23.120 +*N ropt_net_165:5 *C 3.635 23.120 +*N ropt_net_165:6 *C 3.680 23.120 +*N ropt_net_165:7 *C 3.680 23.120 +*N ropt_net_165:8 *C 3.680 23.113 +*N ropt_net_165:9 *C 3.680 17.688 +*N ropt_net_165:10 *C 3.678 17.680 +*N ropt_net_165:11 *C 3.680 17.680 +*N ropt_net_165:12 *C 3.725 17.680 +*N ropt_net_165:13 *C 6.440 17.680 +*N ropt_net_165:14 *C 6.440 18.360 +*N ropt_net_165:15 *C 7.783 18.360 + +*CAP +0 FTB_29__28:X 1e-06 +1 ropt_mt_inst_766:A 1e-06 +2 ropt_net_165:2 9.217511e-05 +3 ropt_net_165:3 0.0001020996 +4 ropt_net_165:4 5.235931e-05 +5 ropt_net_165:5 5.235931e-05 +6 ropt_net_165:6 3.28401e-05 +7 ropt_net_165:7 0.0001020996 +8 ropt_net_165:8 0.000174257 +9 ropt_net_165:9 0.000174257 +10 ropt_net_165:10 9.217511e-05 +11 ropt_net_165:11 3.508167e-05 +12 ropt_net_165:12 9.576509e-05 +13 ropt_net_165:13 0.0001393909 +14 ropt_net_165:14 0.0001461519 +15 ropt_net_165:15 0.0001025261 +16 ropt_net_165:8 chanx_left_in[7]:30 0.0002458743 +17 ropt_net_165:9 chanx_left_in[7]:31 0.0002458743 +18 ropt_net_165:8 chanx_left_in[12]:29 5.972841e-05 +19 ropt_net_165:10 chanx_left_in[12] 5.682662e-06 +20 ropt_net_165:9 chanx_left_in[12]:30 5.972841e-05 +21 ropt_net_165:2 chanx_left_in[12]:31 5.682662e-06 +22 ropt_net_165:12 ropt_net_179:3 9.204976e-05 +23 ropt_net_165:13 ropt_net_179:4 9.204976e-05 + +*RES +0 FTB_29__28:X ropt_net_165:15 0.152 +1 ropt_net_165:4 ropt_mt_inst_766:A 0.152 +2 ropt_net_165:5 ropt_net_165:4 0.0003370536 +3 ropt_net_165:6 ropt_net_165:5 0.0045 +4 ropt_net_165:7 ropt_net_165:6 0.00341 +5 ropt_net_165:7 ropt_net_165:3 5.69697e-05 +6 ropt_net_165:8 ropt_net_165:7 0.00341 +7 ropt_net_165:10 ropt_net_165:9 0.00341 +8 ropt_net_165:10 ropt_net_165:2 0.0001039141 +9 ropt_net_165:9 ropt_net_165:8 0.0008499167 +10 ropt_net_165:11 ropt_net_165:10 0.00341 +11 ropt_net_165:12 ropt_net_165:11 0.0045 +12 ropt_net_165:15 ropt_net_165:14 0.001198661 +13 ropt_net_165:13 ropt_net_165:12 0.002424107 +14 ropt_net_165:14 ropt_net_165:13 0.0006071429 + +*END + +*D_NET ropt_net_177 0.001065442 //LENGTH 8.820 LUMPCC 0.0001461547 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 101.855 52.360 +*I ropt_mt_inst_782:A I *L 0.001767 *C 97.825 50.320 +*N ropt_net_177:2 *C 97.797 50.297 +*N ropt_net_177:3 *C 97.520 50.285 +*N ropt_net_177:4 *C 97.520 49.980 +*N ropt_net_177:5 *C 102.075 49.980 +*N ropt_net_177:6 *C 102.120 50.025 +*N ropt_net_177:7 *C 102.120 52.315 +*N ropt_net_177:8 *C 102.120 52.360 +*N ropt_net_177:9 *C 101.855 52.360 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_177:2 4.540531e-05 +3 ropt_net_177:3 6.988847e-05 +4 ropt_net_177:4 0.0002332049 +5 ropt_net_177:5 0.0002087218 +6 ropt_net_177:6 0.0001219583 +7 ropt_net_177:7 0.0001219583 +8 ropt_net_177:8 5.606948e-05 +9 ropt_net_177:9 6.008061e-05 +10 ropt_net_177:5 chanx_right_out[15]:5 6.224122e-05 +11 ropt_net_177:6 chanx_right_out[15]:2 8.123909e-06 +12 ropt_net_177:6 chanx_right_out[15]:3 2.712223e-06 +13 ropt_net_177:7 chanx_right_out[15] 8.123909e-06 +14 ropt_net_177:7 chanx_right_out[15]:4 2.712223e-06 +15 ropt_net_177:4 chanx_right_out[15]:6 6.224122e-05 + +*RES +0 ropt_mt_inst_754:X ropt_net_177:9 0.152 +1 ropt_net_177:2 ropt_mt_inst_782:A 0.152 +2 ropt_net_177:5 ropt_net_177:4 0.004066965 +3 ropt_net_177:6 ropt_net_177:5 0.0045 +4 ropt_net_177:8 ropt_net_177:7 0.0045 +5 ropt_net_177:7 ropt_net_177:6 0.002044643 +6 ropt_net_177:9 ropt_net_177:8 0.0001440218 +7 ropt_net_177:4 ropt_net_177:3 0.0002723215 +8 ropt_net_177:3 ropt_net_177:2 0.0001875 + +*END + +*D_NET ropt_net_152 0.001248145 //LENGTH 10.880 LUMPCC 0 DR + +*CONN +*I BUFT_P_102:X O *L 0 *C 5.980 59.160 +*I ropt_mt_inst_749:A I *L 0.001766 *C 3.220 63.920 +*N ropt_net_152:2 *C 3.183 63.920 +*N ropt_net_152:3 *C 2.345 63.920 +*N ropt_net_152:4 *C 2.300 63.875 +*N ropt_net_152:5 *C 2.300 59.160 +*N ropt_net_152:6 *C 2.345 59.160 +*N ropt_net_152:7 *C 5.942 59.160 + +*CAP +0 BUFT_P_102:X 1e-06 +1 ropt_mt_inst_749:A 1e-06 +2 ropt_net_152:2 6.47569e-05 +3 ropt_net_152:3 6.47569e-05 +4 ropt_net_152:4 0.0002922669 +5 ropt_net_152:5 0.0003234179 +6 ropt_net_152:6 0.000250473 +7 ropt_net_152:7 0.000250473 + +*RES +0 BUFT_P_102:X ropt_net_152:7 0.152 +1 ropt_net_152:7 ropt_net_152:6 0.003212054 +2 ropt_net_152:6 ropt_net_152:5 0.0045 +3 ropt_net_152:5 ropt_net_152:4 0.004209822 +4 ropt_net_152:3 ropt_net_152:2 0.0007477679 +5 ropt_net_152:4 ropt_net_152:3 0.0045 +6 ropt_net_152:2 ropt_mt_inst_749:A 0.152 + +*END + +*D_NET chanx_left_in[15] 0.02008354 //LENGTH 112.665 LUMPCC 0.009346114 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 40.800 +*I mux_bottom_ipin_11\/mux_l2_in_2_:A0 I *L 0.001631 *C 26.510 39.100 +*I mux_bottom_ipin_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 40.770 42.500 +*I mux_bottom_ipin_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 55.950 39.100 +*I BUFT_RR_65:A I *L 0.001776 *C 93.380 44.880 +*N chanx_left_in[15]:5 *C 93.418 44.880 +*N chanx_left_in[15]:6 *C 95.635 44.880 +*N chanx_left_in[15]:7 *C 95.680 44.835 +*N chanx_left_in[15]:8 *C 95.680 42.218 +*N chanx_left_in[15]:9 *C 95.672 42.160 +*N chanx_left_in[15]:10 *C 55.950 39.100 +*N chanx_left_in[15]:11 *C 55.660 39.100 +*N chanx_left_in[15]:12 *C 55.660 39.145 +*N chanx_left_in[15]:13 *C 55.660 42.102 +*N chanx_left_in[15]:14 *C 55.660 42.160 +*N chanx_left_in[15]:15 *C 49.688 42.160 +*N chanx_left_in[15]:16 *C 49.680 42.160 +*N chanx_left_in[15]:17 *C 49.680 42.500 +*N chanx_left_in[15]:18 *C 49.635 42.500 +*N chanx_left_in[15]:19 *C 40.770 42.500 +*N chanx_left_in[15]:20 *C 38.225 42.500 +*N chanx_left_in[15]:21 *C 38.180 42.455 +*N chanx_left_in[15]:22 *C 38.180 39.145 +*N chanx_left_in[15]:23 *C 38.135 39.100 +*N chanx_left_in[15]:24 *C 26.548 39.100 +*N chanx_left_in[15]:25 *C 27.140 39.100 +*N chanx_left_in[15]:26 *C 27.140 39.100 +*N chanx_left_in[15]:27 *C 27.140 38.760 +*N chanx_left_in[15]:28 *C 27.133 38.760 +*N chanx_left_in[15]:29 *C 6.448 38.760 +*N chanx_left_in[15]:30 *C 6.440 38.818 +*N chanx_left_in[15]:31 *C 6.440 40.742 +*N chanx_left_in[15]:32 *C 6.433 40.800 + +*CAP +0 chanx_left_in[15] 0.000411596 +1 mux_bottom_ipin_11\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_ipin_3\/mux_l2_in_2_:A0 1e-06 +3 mux_bottom_ipin_5\/mux_l2_in_2_:A0 1e-06 +4 BUFT_RR_65:A 1e-06 +5 chanx_left_in[15]:5 0.0001935879 +6 chanx_left_in[15]:6 0.0001935879 +7 chanx_left_in[15]:7 0.0001930929 +8 chanx_left_in[15]:8 0.0001930929 +9 chanx_left_in[15]:9 0.00120634 +10 chanx_left_in[15]:10 5.187319e-05 +11 chanx_left_in[15]:11 5.582992e-05 +12 chanx_left_in[15]:12 0.0001753402 +13 chanx_left_in[15]:13 0.0001753402 +14 chanx_left_in[15]:14 0.001331611 +15 chanx_left_in[15]:15 0.000125271 +16 chanx_left_in[15]:16 5.916137e-05 +17 chanx_left_in[15]:17 5.482044e-05 +18 chanx_left_in[15]:18 0.0004123207 +19 chanx_left_in[15]:19 0.0005331759 +20 chanx_left_in[15]:20 8.932147e-05 +21 chanx_left_in[15]:21 0.0002172482 +22 chanx_left_in[15]:22 0.0002172482 +23 chanx_left_in[15]:23 0.0007377847 +24 chanx_left_in[15]:24 5.304112e-05 +25 chanx_left_in[15]:25 0.0008304409 +26 chanx_left_in[15]:26 6.235597e-05 +27 chanx_left_in[15]:27 6.65995e-05 +28 chanx_left_in[15]:28 0.001210872 +29 chanx_left_in[15]:29 0.001210872 +30 chanx_left_in[15]:30 0.0001300041 +31 chanx_left_in[15]:31 0.0001300041 +32 chanx_left_in[15]:32 0.000411596 +33 chanx_left_in[15]:9 chanx_right_in[7]:19 0.001100358 +34 chanx_left_in[15]:20 chanx_right_in[7]:13 2.224817e-05 +35 chanx_left_in[15]:20 chanx_right_in[7]:14 8.76108e-07 +36 chanx_left_in[15]:21 chanx_right_in[7]:12 2.052141e-06 +37 chanx_left_in[15]:23 chanx_right_in[7]:10 3.04734e-05 +38 chanx_left_in[15]:23 chanx_right_in[7]:14 4.239812e-07 +39 chanx_left_in[15]:22 chanx_right_in[7]:11 2.052141e-06 +40 chanx_left_in[15]:19 chanx_right_in[7]:18 8.287328e-06 +41 chanx_left_in[15]:19 chanx_right_in[7]:15 8.76108e-07 +42 chanx_left_in[15]:19 chanx_right_in[7]:14 6.61916e-05 +43 chanx_left_in[15]:24 chanx_right_in[7]:9 1.679049e-06 +44 chanx_left_in[15]:18 chanx_right_in[7]:19 8.287328e-06 +45 chanx_left_in[15]:18 chanx_right_in[7]:15 4.394343e-05 +46 chanx_left_in[15]:17 chanx_right_in[7]:17 3.113651e-07 +47 chanx_left_in[15]:16 chanx_right_in[7]:16 3.113651e-07 +48 chanx_left_in[15]:15 chanx_right_in[7]:18 0.0003372226 +49 chanx_left_in[15]:14 chanx_right_in[7]:19 0.0003372226 +50 chanx_left_in[15]:14 chanx_right_in[7]:18 0.001100358 +51 chanx_left_in[15]:25 chanx_right_in[7]:10 1.679049e-06 +52 chanx_left_in[15]:25 chanx_right_in[7]:13 4.239812e-07 +53 chanx_left_in[15]:25 chanx_right_in[7]:9 3.04734e-05 +54 chanx_left_in[15]:30 chanx_right_in[7]:7 6.647532e-06 +55 chanx_left_in[15]:31 chanx_right_in[7]:8 6.647532e-06 +56 chanx_left_in[15]:13 chanx_right_in[9]:21 9.620872e-06 +57 chanx_left_in[15]:12 chanx_right_in[9]:22 9.620872e-06 +58 chanx_left_in[15]:28 chanx_right_in[9]:23 0.0002804872 +59 chanx_left_in[15]:29 chanx_right_in[9]:19 0.0002804872 +60 chanx_left_in[15]:9 chanx_right_in[18]:27 0.001350688 +61 chanx_left_in[15]:9 chanx_right_in[18]:28 0.0002083775 +62 chanx_left_in[15]:9 chanx_right_in[18]:17 0.0006364746 +63 chanx_left_in[15]:19 chanx_right_in[18]:16 7.394042e-06 +64 chanx_left_in[15]:18 chanx_right_in[18]:17 7.394042e-06 +65 chanx_left_in[15]:15 chanx_right_in[18]:16 0.0003372226 +66 chanx_left_in[15]:14 chanx_right_in[18]:27 0.0002083775 +67 chanx_left_in[15]:14 chanx_right_in[18]:16 0.0006364746 +68 chanx_left_in[15]:14 chanx_right_in[18]:17 0.00168791 +69 chanx_left_in[15]:28 chanx_right_in[18]:17 2.667205e-07 +70 chanx_left_in[15]:29 chanx_right_in[18]:16 2.667205e-07 +71 chanx_left_in[15]:20 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 7.61498e-05 +72 chanx_left_in[15]:19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001138386 +73 chanx_left_in[15]:19 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.61498e-05 +74 chanx_left_in[15]:18 mux_bottom_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001138386 +75 chanx_left_in[15]:8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.780779e-07 +76 chanx_left_in[15]:9 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.783704e-05 +77 chanx_left_in[15]:7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.780779e-07 +78 chanx_left_in[15]:14 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.783704e-05 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:32 0.0008150582 +1 chanx_left_in[15]:8 chanx_left_in[15]:7 0.002337054 +2 chanx_left_in[15]:9 chanx_left_in[15]:8 0.00341 +3 chanx_left_in[15]:6 chanx_left_in[15]:5 0.001979911 +4 chanx_left_in[15]:7 chanx_left_in[15]:6 0.0045 +5 chanx_left_in[15]:5 BUFT_RR_65:A 0.152 +6 chanx_left_in[15]:20 chanx_left_in[15]:19 0.002272321 +7 chanx_left_in[15]:21 chanx_left_in[15]:20 0.0045 +8 chanx_left_in[15]:23 chanx_left_in[15]:22 0.0045 +9 chanx_left_in[15]:22 chanx_left_in[15]:21 0.002955357 +10 chanx_left_in[15]:19 mux_bottom_ipin_3\/mux_l2_in_2_:A0 0.152 +11 chanx_left_in[15]:19 chanx_left_in[15]:18 0.007915179 +12 chanx_left_in[15]:24 mux_bottom_ipin_11\/mux_l2_in_2_:A0 0.152 +13 chanx_left_in[15]:18 chanx_left_in[15]:17 0.0045 +14 chanx_left_in[15]:17 chanx_left_in[15]:16 0.0001634615 +15 chanx_left_in[15]:16 chanx_left_in[15]:15 0.00341 +16 chanx_left_in[15]:15 chanx_left_in[15]:14 0.0009356916 +17 chanx_left_in[15]:13 chanx_left_in[15]:12 0.002640625 +18 chanx_left_in[15]:14 chanx_left_in[15]:13 0.00341 +19 chanx_left_in[15]:14 chanx_left_in[15]:9 0.006268624 +20 chanx_left_in[15]:11 chanx_left_in[15]:10 0.0001576087 +21 chanx_left_in[15]:12 chanx_left_in[15]:11 0.0045 +22 chanx_left_in[15]:10 mux_bottom_ipin_5\/mux_l2_in_2_:A0 0.152 +23 chanx_left_in[15]:25 chanx_left_in[15]:24 0.0005290179 +24 chanx_left_in[15]:25 chanx_left_in[15]:23 0.009816965 +25 chanx_left_in[15]:26 chanx_left_in[15]:25 0.0045 +26 chanx_left_in[15]:27 chanx_left_in[15]:26 0.0001634615 +27 chanx_left_in[15]:28 chanx_left_in[15]:27 0.00341 +28 chanx_left_in[15]:30 chanx_left_in[15]:29 0.00341 +29 chanx_left_in[15]:29 chanx_left_in[15]:28 0.00324065 +30 chanx_left_in[15]:31 chanx_left_in[15]:30 0.00171875 +31 chanx_left_in[15]:32 chanx_left_in[15]:31 0.00341 + +*END + +*D_NET chanx_right_in[12] 0.02097567 //LENGTH 172.750 LUMPCC 0.003831845 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 103.650 17.680 +*I mux_bottom_ipin_12\/mux_l2_in_2_:A1 I *L 0.00198 *C 79.680 14.620 +*I ropt_mt_inst_741:A I *L 0.001766 *C 7.820 72.080 +*I mux_bottom_ipin_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 13.705 36.380 +*N chanx_right_in[12]:4 *C 17.080 36.040 +*N chanx_right_in[12]:5 *C 13.743 36.380 +*N chanx_right_in[12]:6 *C 14.260 36.380 +*N chanx_right_in[12]:7 *C 7.783 72.080 +*N chanx_right_in[12]:8 *C 6.025 72.080 +*N chanx_right_in[12]:9 *C 5.980 72.035 +*N chanx_right_in[12]:10 *C 5.980 69.360 +*N chanx_right_in[12]:11 *C 5.060 69.360 +*N chanx_right_in[12]:12 *C 5.060 58.185 +*N chanx_right_in[12]:13 *C 5.105 58.140 +*N chanx_right_in[12]:14 *C 7.315 58.140 +*N chanx_right_in[12]:15 *C 7.360 58.095 +*N chanx_right_in[12]:16 *C 7.360 36.098 +*N chanx_right_in[12]:17 *C 7.368 36.040 +*N chanx_right_in[12]:18 *C 14.253 36.040 +*N chanx_right_in[12]:19 *C 14.260 36.040 +*N chanx_right_in[12]:20 *C 14.260 36.040 +*N chanx_right_in[12]:21 *C 17.435 36.040 +*N chanx_right_in[12]:22 *C 17.480 36.040 +*N chanx_right_in[12]:23 *C 17.480 36.040 +*N chanx_right_in[12]:24 *C 17.480 36.032 +*N chanx_right_in[12]:25 *C 17.480 12.248 +*N chanx_right_in[12]:26 *C 17.500 12.240 +*N chanx_right_in[12]:27 *C 67.290 12.240 +*N chanx_right_in[12]:28 *C 78.653 12.240 +*N chanx_right_in[12]:29 *C 78.660 12.298 +*N chanx_right_in[12]:30 *C 78.660 14.575 +*N chanx_right_in[12]:31 *C 78.705 14.620 +*N chanx_right_in[12]:32 *C 79.680 14.620 +*N chanx_right_in[12]:33 *C 92.415 14.620 +*N chanx_right_in[12]:34 *C 92.460 14.665 +*N chanx_right_in[12]:35 *C 92.460 17.623 +*N chanx_right_in[12]:36 *C 92.468 17.680 + +*CAP +0 chanx_right_in[12] 0.0006516338 +1 mux_bottom_ipin_12\/mux_l2_in_2_:A1 1e-06 +2 ropt_mt_inst_741:A 1e-06 +3 mux_bottom_ipin_8\/mux_l2_in_2_:A1 1e-06 +4 chanx_right_in[12]:4 7.296467e-05 +5 chanx_right_in[12]:5 6.315131e-05 +6 chanx_right_in[12]:6 9.159146e-05 +7 chanx_right_in[12]:7 7.151406e-05 +8 chanx_right_in[12]:8 7.151406e-05 +9 chanx_right_in[12]:9 0.000152326 +10 chanx_right_in[12]:10 0.0002052081 +11 chanx_right_in[12]:11 0.0006682596 +12 chanx_right_in[12]:12 0.0006153774 +13 chanx_right_in[12]:13 0.0001744384 +14 chanx_right_in[12]:14 0.0001744384 +15 chanx_right_in[12]:15 0.001146988 +16 chanx_right_in[12]:16 0.001146988 +17 chanx_right_in[12]:17 0.0005154089 +18 chanx_right_in[12]:18 0.0005154089 +19 chanx_right_in[12]:19 3.398806e-05 +20 chanx_right_in[12]:20 0.0002583788 +21 chanx_right_in[12]:21 0.0002299386 +22 chanx_right_in[12]:22 3.398806e-05 +23 chanx_right_in[12]:23 7.296467e-05 +24 chanx_right_in[12]:24 0.001634615 +25 chanx_right_in[12]:25 0.001634615 +26 chanx_right_in[12]:26 0.00149267 +27 chanx_right_in[12]:27 0.002055192 +28 chanx_right_in[12]:28 0.0005625226 +29 chanx_right_in[12]:29 0.0001412297 +30 chanx_right_in[12]:30 0.0001412297 +31 chanx_right_in[12]:31 7.10805e-05 +32 chanx_right_in[12]:32 0.0007640442 +33 chanx_right_in[12]:33 0.0006657421 +34 chanx_right_in[12]:34 0.0001798903 +35 chanx_right_in[12]:35 0.0001798903 +36 chanx_right_in[12]:36 0.0006516338 +37 chanx_right_in[12]:33 chanx_left_in[16]:9 7.40028e-05 +38 chanx_right_in[12]:24 chanx_left_in[16]:20 1.600115e-05 +39 chanx_right_in[12]:26 chanx_left_in[16]:20 0.0007237672 +40 chanx_right_in[12]:25 chanx_left_in[16]:21 1.600115e-05 +41 chanx_right_in[12]:32 chanx_left_in[16]:10 7.40028e-05 +42 chanx_right_in[12]:27 chanx_left_in[16]:19 0.0007237672 +43 chanx_right_in[12]:24 prog_clk[0]:311 5.860457e-06 +44 chanx_right_in[12]:26 prog_clk[0]:313 0.0002904114 +45 chanx_right_in[12]:26 prog_clk[0]:129 1.119951e-05 +46 chanx_right_in[12]:26 prog_clk[0]:310 5.994539e-07 +47 chanx_right_in[12]:26 prog_clk[0]:144 0.0001202402 +48 chanx_right_in[12]:26 prog_clk[0]:134 0.0001699482 +49 chanx_right_in[12]:26 prog_clk[0]:139 5.356827e-05 +50 chanx_right_in[12]:26 prog_clk[0]:117 9.776556e-05 +51 chanx_right_in[12]:25 prog_clk[0]:312 5.860457e-06 +52 chanx_right_in[12]:28 prog_clk[0]:112 3.146056e-05 +53 chanx_right_in[12]:28 prog_clk[0]:68 3.842334e-05 +54 chanx_right_in[12]:16 prog_clk[0]:363 3.832972e-05 +55 chanx_right_in[12]:16 prog_clk[0]:360 5.936205e-05 +56 chanx_right_in[12]:16 prog_clk[0]:364 6.261284e-05 +57 chanx_right_in[12]:15 prog_clk[0]:363 6.261284e-05 +58 chanx_right_in[12]:15 prog_clk[0]:360 3.832972e-05 +59 chanx_right_in[12]:15 prog_clk[0]:356 5.936205e-05 +60 chanx_right_in[12]:12 prog_clk[0]:360 3.775899e-05 +61 chanx_right_in[12]:12 prog_clk[0]:356 2.298219e-06 +62 chanx_right_in[12]:11 prog_clk[0]:353 2.298219e-06 +63 chanx_right_in[12]:11 prog_clk[0]:356 3.775899e-05 +64 chanx_right_in[12]:27 prog_clk[0]:129 0.0001699482 +65 chanx_right_in[12]:27 prog_clk[0]:112 9.776556e-05 +66 chanx_right_in[12]:27 prog_clk[0]:309 5.994539e-07 +67 chanx_right_in[12]:27 prog_clk[0]:144 0.0002904114 +68 chanx_right_in[12]:27 prog_clk[0]:134 5.356827e-05 +69 chanx_right_in[12]:27 prog_clk[0]:139 0.0001202402 +70 chanx_right_in[12]:27 prog_clk[0]:117 4.266006e-05 +71 chanx_right_in[12]:27 prog_clk[0]:69 3.842334e-05 +72 chanx_right_in[12]:8 ropt_net_170:4 8.231224e-05 +73 chanx_right_in[12]:7 ropt_net_170:5 8.231224e-05 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:36 0.001751925 +1 chanx_right_in[12]:33 chanx_right_in[12]:32 0.01137054 +2 chanx_right_in[12]:34 chanx_right_in[12]:33 0.0045 +3 chanx_right_in[12]:35 chanx_right_in[12]:34 0.002640625 +4 chanx_right_in[12]:36 chanx_right_in[12]:35 0.00341 +5 chanx_right_in[12]:21 chanx_right_in[12]:20 0.002834822 +6 chanx_right_in[12]:22 chanx_right_in[12]:21 0.0045 +7 chanx_right_in[12]:23 chanx_right_in[12]:22 0.00341 +8 chanx_right_in[12]:23 chanx_right_in[12]:4 5.69697e-05 +9 chanx_right_in[12]:24 chanx_right_in[12]:23 0.00341 +10 chanx_right_in[12]:26 chanx_right_in[12]:25 0.00341 +11 chanx_right_in[12]:25 chanx_right_in[12]:24 0.003726316 +12 chanx_right_in[12]:29 chanx_right_in[12]:28 0.00341 +13 chanx_right_in[12]:28 chanx_right_in[12]:27 0.001780125 +14 chanx_right_in[12]:31 chanx_right_in[12]:30 0.0045 +15 chanx_right_in[12]:30 chanx_right_in[12]:29 0.002033482 +16 chanx_right_in[12]:32 mux_bottom_ipin_12\/mux_l2_in_2_:A1 0.152 +17 chanx_right_in[12]:32 chanx_right_in[12]:31 0.0008705358 +18 chanx_right_in[12]:5 mux_bottom_ipin_8\/mux_l2_in_2_:A1 0.152 +19 chanx_right_in[12]:20 chanx_right_in[12]:19 0.0045 +20 chanx_right_in[12]:20 chanx_right_in[12]:6 0.0003035715 +21 chanx_right_in[12]:19 chanx_right_in[12]:18 0.00341 +22 chanx_right_in[12]:18 chanx_right_in[12]:17 0.00107865 +23 chanx_right_in[12]:16 chanx_right_in[12]:15 0.01964063 +24 chanx_right_in[12]:17 chanx_right_in[12]:16 0.00341 +25 chanx_right_in[12]:14 chanx_right_in[12]:13 0.001973214 +26 chanx_right_in[12]:15 chanx_right_in[12]:14 0.0045 +27 chanx_right_in[12]:13 chanx_right_in[12]:12 0.0045 +28 chanx_right_in[12]:12 chanx_right_in[12]:11 0.00997768 +29 chanx_right_in[12]:8 chanx_right_in[12]:7 0.001569197 +30 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0045 +31 chanx_right_in[12]:7 ropt_mt_inst_741:A 0.152 +32 chanx_right_in[12]:6 chanx_right_in[12]:5 0.0004620536 +33 chanx_right_in[12]:11 chanx_right_in[12]:10 0.0008214285 +34 chanx_right_in[12]:10 chanx_right_in[12]:9 0.002388393 +35 chanx_right_in[12]:27 chanx_right_in[12]:26 0.007800433 + +*END + +*D_NET chanx_right_in[19] 0.02216795 //LENGTH 158.085 LUMPCC 0.005260237 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 103.575 63.920 +*I mux_bottom_ipin_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 18.860 58.140 +*I FTB_40__39:A I *L 0.001767 *C 11.500 12.240 +*I mux_bottom_ipin_7\/mux_l2_in_3_:A1 I *L 0.00198 *C 39.465 61.540 +*I mux_bottom_ipin_15\/mux_l2_in_3_:A1 I *L 0.00198 *C 68.180 61.540 +*N chanx_right_in[19]:5 *C 68.180 61.540 +*N chanx_right_in[19]:6 *C 39.465 61.540 +*N chanx_right_in[19]:7 *C 11.478 12.268 +*N chanx_right_in[19]:8 *C 11.465 12.580 +*N chanx_right_in[19]:9 *C 6.945 12.580 +*N chanx_right_in[19]:10 *C 6.900 12.625 +*N chanx_right_in[19]:11 *C 6.900 27.143 +*N chanx_right_in[19]:12 *C 6.908 27.200 +*N chanx_right_in[19]:13 *C 19.300 27.200 +*N chanx_right_in[19]:14 *C 19.320 27.207 +*N chanx_right_in[19]:15 *C 18.860 58.140 +*N chanx_right_in[19]:16 *C 18.860 58.140 +*N chanx_right_in[19]:17 *C 18.860 57.800 +*N chanx_right_in[19]:18 *C 18.863 57.800 +*N chanx_right_in[19]:19 *C 19.305 57.800 +*N chanx_right_in[19]:20 *C 19.320 57.800 +*N chanx_right_in[19]:21 *C 19.320 61.873 +*N chanx_right_in[19]:22 *C 19.340 61.880 +*N chanx_right_in[19]:23 *C 39.553 61.880 +*N chanx_right_in[19]:24 *C 39.560 61.880 +*N chanx_right_in[19]:25 *C 39.605 61.880 +*N chanx_right_in[19]:26 *C 68.080 61.880 +*N chanx_right_in[19]:27 *C 81.835 61.880 +*N chanx_right_in[19]:28 *C 81.880 61.925 +*N chanx_right_in[19]:29 *C 81.880 63.183 +*N chanx_right_in[19]:30 *C 81.888 63.240 +*N chanx_right_in[19]:31 *C 103.500 63.240 + +*CAP +0 chanx_right_in[19] 6.989954e-05 +1 mux_bottom_ipin_9\/mux_l2_in_3_:A1 1e-06 +2 FTB_40__39:A 1e-06 +3 mux_bottom_ipin_7\/mux_l2_in_3_:A1 1e-06 +4 mux_bottom_ipin_15\/mux_l2_in_3_:A1 1e-06 +5 chanx_right_in[19]:5 5.402161e-05 +6 chanx_right_in[19]:6 6.365645e-05 +7 chanx_right_in[19]:7 3.301479e-05 +8 chanx_right_in[19]:8 0.0003015841 +9 chanx_right_in[19]:9 0.0002685693 +10 chanx_right_in[19]:10 0.0007335977 +11 chanx_right_in[19]:11 0.0007335977 +12 chanx_right_in[19]:12 0.0009129755 +13 chanx_right_in[19]:13 0.0009129755 +14 chanx_right_in[19]:14 0.001285149 +15 chanx_right_in[19]:15 3.259642e-05 +16 chanx_right_in[19]:16 5.853375e-05 +17 chanx_right_in[19]:17 6.287339e-05 +18 chanx_right_in[19]:18 7.948499e-05 +19 chanx_right_in[19]:19 7.948499e-05 +20 chanx_right_in[19]:20 0.001451503 +21 chanx_right_in[19]:21 0.0001663544 +22 chanx_right_in[19]:22 0.0005531754 +23 chanx_right_in[19]:23 0.0005531754 +24 chanx_right_in[19]:24 3.830583e-05 +25 chanx_right_in[19]:25 0.002003984 +26 chanx_right_in[19]:26 0.002979713 +27 chanx_right_in[19]:27 0.0009836318 +28 chanx_right_in[19]:28 8.69373e-05 +29 chanx_right_in[19]:29 8.69373e-05 +30 chanx_right_in[19]:30 0.001124039 +31 chanx_right_in[19]:31 0.001193938 +32 chanx_right_in[19]:30 chanx_left_in[17]:16 9.049049e-05 +33 chanx_right_in[19]:23 chanx_left_in[17]:24 0.0004510916 +34 chanx_right_in[19]:22 chanx_left_in[17]:25 0.0004510916 +35 chanx_right_in[19]:19 chanx_left_in[17]:24 2.52103e-07 +36 chanx_right_in[19]:18 chanx_left_in[17]:25 2.52103e-07 +37 chanx_right_in[19]:31 chanx_left_in[17]:15 9.049049e-05 +38 chanx_right_in[19]:14 chanx_right_in[13]:14 2.251505e-06 +39 chanx_right_in[19]:30 chanx_right_in[13]:18 0.0001347619 +40 chanx_right_in[19]:30 chanx_right_in[13]:22 2.501787e-05 +41 chanx_right_in[19]:25 chanx_right_in[13]:17 6.670839e-06 +42 chanx_right_in[19]:23 chanx_right_in[13]:17 0.0002106541 +43 chanx_right_in[19]:23 chanx_right_in[13]:18 0.0008174659 +44 chanx_right_in[19]:22 chanx_right_in[13]:7 0.0002106541 +45 chanx_right_in[19]:22 chanx_right_in[13]:17 0.0008174659 +46 chanx_right_in[19]:20 chanx_right_in[13]:15 2.251505e-06 +47 chanx_right_in[19]:26 chanx_right_in[13]:18 6.670839e-06 +48 chanx_right_in[19]:31 chanx_right_in[13]:22 0.0001347619 +49 chanx_right_in[19]:31 chanx_right_in[13]:23 2.501787e-05 +50 chanx_right_in[19]:14 chanx_right_in[14]:12 0.0003334206 +51 chanx_right_in[19]:20 chanx_right_in[14]:11 0.0003334206 +52 chanx_right_in[19]:14 chanx_right_in[18]:14 0.0003123385 +53 chanx_right_in[19]:21 chanx_right_in[18]:13 7.845973e-05 +54 chanx_right_in[19]:20 chanx_right_in[18]:13 0.0003123385 +55 chanx_right_in[19]:20 chanx_right_in[18]:14 7.845973e-05 +56 chanx_right_in[19]:25 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 9.689859e-05 +57 chanx_right_in[19]:25 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.89667e-05 +58 chanx_right_in[19]:26 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.89667e-05 +59 chanx_right_in[19]:26 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.689859e-05 +60 chanx_right_in[19]:11 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.137828e-05 +61 chanx_right_in[19]:10 mux_bottom_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.137828e-05 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:31 0.0001065333 +1 chanx_right_in[19]:13 chanx_right_in[19]:12 0.001941492 +2 chanx_right_in[19]:14 chanx_right_in[19]:13 0.00341 +3 chanx_right_in[19]:11 chanx_right_in[19]:10 0.01296205 +4 chanx_right_in[19]:12 chanx_right_in[19]:11 0.00341 +5 chanx_right_in[19]:9 chanx_right_in[19]:8 0.004035715 +6 chanx_right_in[19]:10 chanx_right_in[19]:9 0.0045 +7 chanx_right_in[19]:7 FTB_40__39:A 0.152 +8 chanx_right_in[19]:27 chanx_right_in[19]:26 0.01228125 +9 chanx_right_in[19]:28 chanx_right_in[19]:27 0.0045 +10 chanx_right_in[19]:29 chanx_right_in[19]:28 0.001122768 +11 chanx_right_in[19]:30 chanx_right_in[19]:29 0.00341 +12 chanx_right_in[19]:25 chanx_right_in[19]:24 0.0045 +13 chanx_right_in[19]:25 chanx_right_in[19]:6 0.0001847826 +14 chanx_right_in[19]:24 chanx_right_in[19]:23 0.00341 +15 chanx_right_in[19]:23 chanx_right_in[19]:22 0.003166625 +16 chanx_right_in[19]:22 chanx_right_in[19]:21 0.00341 +17 chanx_right_in[19]:21 chanx_right_in[19]:20 0.000638025 +18 chanx_right_in[19]:6 mux_bottom_ipin_7\/mux_l2_in_3_:A1 0.152 +19 chanx_right_in[19]:5 mux_bottom_ipin_15\/mux_l2_in_3_:A1 0.152 +20 chanx_right_in[19]:19 chanx_right_in[19]:18 6.499218e-05 +21 chanx_right_in[19]:20 chanx_right_in[19]:19 0.00341 +22 chanx_right_in[19]:20 chanx_right_in[19]:14 0.004792825 +23 chanx_right_in[19]:17 chanx_right_in[19]:16 0.0001634615 +24 chanx_right_in[19]:18 chanx_right_in[19]:17 0.00341 +25 chanx_right_in[19]:15 mux_bottom_ipin_9\/mux_l2_in_3_:A1 0.152 +26 chanx_right_in[19]:16 chanx_right_in[19]:15 0.0045 +27 chanx_right_in[19]:8 chanx_right_in[19]:7 0.0002111487 +28 chanx_right_in[19]:26 chanx_right_in[19]:25 0.02542411 +29 chanx_right_in[19]:26 chanx_right_in[19]:5 0.0003035715 +30 chanx_right_in[19]:31 chanx_right_in[19]:30 0.003385958 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.005682558 //LENGTH 43.390 LUMPCC 0.0001700357 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 77.375 30.600 +*I mux_bottom_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 66.140 28.560 +*I mux_bottom_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 65.420 17.680 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 61.355 11.900 +*I mux_bottom_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 62.200 9.520 +*I mux_bottom_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 76.000 28.855 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 76.000 28.855 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 75.890 28.560 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 62.238 9.520 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 65.275 9.520 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 65.320 9.565 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 61.393 11.900 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 65.275 11.900 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 65.320 11.900 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 65.320 17.680 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 65.320 17.680 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 65.320 19.720 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 65.780 19.720 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 65.780 28.515 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 65.803 28.560 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 66.178 28.560 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 75.913 28.560 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 76.330 28.590 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 76.360 28.605 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 76.360 30.555 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 76.405 30.600 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 77.338 30.600 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_2_:S 1e-06 +3 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_ipin_0\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_ipin_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 5.90271e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:7 4.679834e-05 +8 mux_tree_tapbuf_size10_0_sram[1]:8 0.0003006676 +9 mux_tree_tapbuf_size10_0_sram[1]:9 0.0003006676 +10 mux_tree_tapbuf_size10_0_sram[1]:10 0.0001307623 +11 mux_tree_tapbuf_size10_0_sram[1]:11 0.0002620603 +12 mux_tree_tapbuf_size10_0_sram[1]:12 0.0002620603 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.0004831291 +14 mux_tree_tapbuf_size10_0_sram[1]:14 3.254968e-05 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0004740714 +16 mux_tree_tapbuf_size10_0_sram[1]:16 0.0001530416 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0005607745 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.0005295188 +19 mux_tree_tapbuf_size10_0_sram[1]:19 5.492279e-05 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0006544994 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0006700701 +22 mux_tree_tapbuf_size10_0_sram[1]:22 5.383662e-05 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0001548784 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0001548784 +25 mux_tree_tapbuf_size10_0_sram[1]:25 8.415434e-05 +26 mux_tree_tapbuf_size10_0_sram[1]:26 8.415434e-05 +27 mux_tree_tapbuf_size10_0_sram[1]:18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.431982e-06 +28 mux_tree_tapbuf_size10_0_sram[1]:20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.258585e-05 +29 mux_tree_tapbuf_size10_0_sram[1]:21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.258585e-05 +30 mux_tree_tapbuf_size10_0_sram[1]:17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.431982e-06 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:26 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.0045 +2 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.007852679 +3 mux_tree_tapbuf_size10_0_sram[1]:20 mux_bottom_ipin_0\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0002038044 +5 mux_tree_tapbuf_size10_0_sram[1]:6 mux_bottom_ipin_0\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.003466518 +7 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:10 0.002084822 +9 mux_tree_tapbuf_size10_0_sram[1]:11 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_0_sram[1]:9 mux_tree_tapbuf_size10_0_sram[1]:8 0.002712054 +11 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size10_0_sram[1]:8 mux_bottom_ipin_0\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size10_0_sram[1]:14 mux_bottom_ipin_0\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0045 +15 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:13 0.005160714 +16 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.0008325893 +17 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0045 +18 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.001741072 +19 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.0002609375 +20 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0045 +21 mux_tree_tapbuf_size10_0_sram[1]:7 mux_tree_tapbuf_size10_0_sram[1]:6 0.0001271552 +22 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.008691965 +23 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:7 2.008929e-05 +24 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.001821429 +25 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[1] 0.004869781 //LENGTH 38.960 LUMPCC 0.0001834818 DR + +*CONN +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 50.445 37.060 +*I mux_bottom_ipin_5\/mux_l2_in_3_:S I *L 0.00357 *C 51.160 41.870 +*I mux_bottom_ipin_5\/mux_l2_in_1_:S I *L 0.00357 *C 54.380 44.880 +*I mux_bottom_ipin_5\/mux_l2_in_0_:S I *L 0.00357 *C 55.100 52.360 +*I mux_bottom_ipin_5\/mux_l2_in_2_:S I *L 0.00357 *C 54.840 40.120 +*I mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.975 42.500 +*N mux_tree_tapbuf_size10_3_sram[1]:6 *C 60.013 42.500 +*N mux_tree_tapbuf_size10_3_sram[1]:7 *C 60.720 42.500 +*N mux_tree_tapbuf_size10_3_sram[1]:8 *C 60.720 42.840 +*N mux_tree_tapbuf_size10_3_sram[1]:9 *C 54.878 40.120 +*N mux_tree_tapbuf_size10_3_sram[1]:10 *C 59.295 40.120 +*N mux_tree_tapbuf_size10_3_sram[1]:11 *C 59.340 40.165 +*N mux_tree_tapbuf_size10_3_sram[1]:12 *C 59.340 42.795 +*N mux_tree_tapbuf_size10_3_sram[1]:13 *C 59.340 42.840 +*N mux_tree_tapbuf_size10_3_sram[1]:14 *C 54.740 42.840 +*N mux_tree_tapbuf_size10_3_sram[1]:15 *C 55.085 52.360 +*N mux_tree_tapbuf_size10_3_sram[1]:16 *C 54.763 52.360 +*N mux_tree_tapbuf_size10_3_sram[1]:17 *C 54.740 52.315 +*N mux_tree_tapbuf_size10_3_sram[1]:18 *C 54.395 44.880 +*N mux_tree_tapbuf_size10_3_sram[1]:19 *C 54.718 44.880 +*N mux_tree_tapbuf_size10_3_sram[1]:20 *C 54.740 44.880 +*N mux_tree_tapbuf_size10_3_sram[1]:21 *C 54.740 42.205 +*N mux_tree_tapbuf_size10_3_sram[1]:22 *C 54.740 42.190 +*N mux_tree_tapbuf_size10_3_sram[1]:23 *C 51.235 42.160 +*N mux_tree_tapbuf_size10_3_sram[1]:24 *C 51.180 42.160 +*N mux_tree_tapbuf_size10_3_sram[1]:25 *C 51.160 41.870 +*N mux_tree_tapbuf_size10_3_sram[1]:26 *C 51.060 41.480 +*N mux_tree_tapbuf_size10_3_sram[1]:27 *C 51.060 41.435 +*N mux_tree_tapbuf_size10_3_sram[1]:28 *C 51.060 37.105 +*N mux_tree_tapbuf_size10_3_sram[1]:29 *C 51.015 37.060 +*N mux_tree_tapbuf_size10_3_sram[1]:30 *C 50.483 37.060 + +*CAP +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_5\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_ipin_5\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_5\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_ipin_5\/mux_l2_in_2_:S 1e-06 +5 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_3_sram[1]:6 4.386602e-05 +7 mux_tree_tapbuf_size10_3_sram[1]:7 7.02704e-05 +8 mux_tree_tapbuf_size10_3_sram[1]:8 0.0001329526 +9 mux_tree_tapbuf_size10_3_sram[1]:9 0.0003088544 +10 mux_tree_tapbuf_size10_3_sram[1]:10 0.0003088544 +11 mux_tree_tapbuf_size10_3_sram[1]:11 0.0001820128 +12 mux_tree_tapbuf_size10_3_sram[1]:12 0.0001820128 +13 mux_tree_tapbuf_size10_3_sram[1]:13 0.0004415562 +14 mux_tree_tapbuf_size10_3_sram[1]:14 0.0003489149 +15 mux_tree_tapbuf_size10_3_sram[1]:15 5.239834e-05 +16 mux_tree_tapbuf_size10_3_sram[1]:16 5.239834e-05 +17 mux_tree_tapbuf_size10_3_sram[1]:17 0.0004099194 +18 mux_tree_tapbuf_size10_3_sram[1]:18 6.055751e-05 +19 mux_tree_tapbuf_size10_3_sram[1]:19 6.055751e-05 +20 mux_tree_tapbuf_size10_3_sram[1]:20 0.0006005685 +21 mux_tree_tapbuf_size10_3_sram[1]:21 0.0001578275 +22 mux_tree_tapbuf_size10_3_sram[1]:22 0.0002743703 +23 mux_tree_tapbuf_size10_3_sram[1]:23 0.0002635284 +24 mux_tree_tapbuf_size10_3_sram[1]:24 2.927928e-05 +25 mux_tree_tapbuf_size10_3_sram[1]:25 0.000103248 +26 mux_tree_tapbuf_size10_3_sram[1]:26 6.336001e-05 +27 mux_tree_tapbuf_size10_3_sram[1]:27 0.0002094423 +28 mux_tree_tapbuf_size10_3_sram[1]:28 0.0002094423 +29 mux_tree_tapbuf_size10_3_sram[1]:29 5.705324e-05 +30 mux_tree_tapbuf_size10_3_sram[1]:30 5.705324e-05 +31 mux_tree_tapbuf_size10_3_sram[1]:20 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.103999e-05 +32 mux_tree_tapbuf_size10_3_sram[1]:17 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.103999e-05 +33 mux_tree_tapbuf_size10_3_sram[1]:27 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.07009e-05 +34 mux_tree_tapbuf_size10_3_sram[1]:28 mux_bottom_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.07009e-05 + +*RES +0 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_3_sram[1]:30 0.152 +1 mux_tree_tapbuf_size10_3_sram[1]:19 mux_tree_tapbuf_size10_3_sram[1]:18 0.0001752718 +2 mux_tree_tapbuf_size10_3_sram[1]:20 mux_tree_tapbuf_size10_3_sram[1]:19 0.0045 +3 mux_tree_tapbuf_size10_3_sram[1]:20 mux_tree_tapbuf_size10_3_sram[1]:17 0.006638394 +4 mux_tree_tapbuf_size10_3_sram[1]:18 mux_bottom_ipin_5\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_3_sram[1]:25 mux_bottom_ipin_5\/mux_l2_in_3_:S 0.152 +6 mux_tree_tapbuf_size10_3_sram[1]:25 mux_tree_tapbuf_size10_3_sram[1]:24 0.0002589286 +7 mux_tree_tapbuf_size10_3_sram[1]:25 mux_tree_tapbuf_size10_3_sram[1]:23 0.0002589286 +8 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:21 0.0045 +9 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:14 0.0005803572 +10 mux_tree_tapbuf_size10_3_sram[1]:21 mux_tree_tapbuf_size10_3_sram[1]:20 0.002388393 +11 mux_tree_tapbuf_size10_3_sram[1]:6 mem_bottom_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size10_3_sram[1]:26 mux_tree_tapbuf_size10_3_sram[1]:25 0.0003482143 +13 mux_tree_tapbuf_size10_3_sram[1]:27 mux_tree_tapbuf_size10_3_sram[1]:26 0.0045 +14 mux_tree_tapbuf_size10_3_sram[1]:29 mux_tree_tapbuf_size10_3_sram[1]:28 0.0045 +15 mux_tree_tapbuf_size10_3_sram[1]:28 mux_tree_tapbuf_size10_3_sram[1]:27 0.003866071 +16 mux_tree_tapbuf_size10_3_sram[1]:30 mux_tree_tapbuf_size10_3_sram[1]:29 0.0004754465 +17 mux_tree_tapbuf_size10_3_sram[1]:13 mux_tree_tapbuf_size10_3_sram[1]:12 0.0045 +18 mux_tree_tapbuf_size10_3_sram[1]:13 mux_tree_tapbuf_size10_3_sram[1]:8 0.001232143 +19 mux_tree_tapbuf_size10_3_sram[1]:12 mux_tree_tapbuf_size10_3_sram[1]:11 0.002348214 +20 mux_tree_tapbuf_size10_3_sram[1]:10 mux_tree_tapbuf_size10_3_sram[1]:9 0.003944196 +21 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:10 0.0045 +22 mux_tree_tapbuf_size10_3_sram[1]:9 mux_bottom_ipin_5\/mux_l2_in_2_:S 0.152 +23 mux_tree_tapbuf_size10_3_sram[1]:15 mux_bottom_ipin_5\/mux_l2_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_3_sram[1]:16 mux_tree_tapbuf_size10_3_sram[1]:15 0.0001752717 +25 mux_tree_tapbuf_size10_3_sram[1]:17 mux_tree_tapbuf_size10_3_sram[1]:16 0.0045 +26 mux_tree_tapbuf_size10_3_sram[1]:23 mux_tree_tapbuf_size10_3_sram[1]:22 0.003129464 +27 mux_tree_tapbuf_size10_3_sram[1]:14 mux_tree_tapbuf_size10_3_sram[1]:13 0.004107143 +28 mux_tree_tapbuf_size10_3_sram[1]:8 mux_tree_tapbuf_size10_3_sram[1]:7 0.0003035715 +29 mux_tree_tapbuf_size10_3_sram[1]:7 mux_tree_tapbuf_size10_3_sram[1]:6 0.0006316964 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[0] 0.003460445 //LENGTH 27.948 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.565 49.980 +*I mux_bottom_ipin_9\/mux_l1_in_2_:S I *L 0.00357 *C 15.080 45.560 +*I mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 17.655 49.980 +*I mux_bottom_ipin_9\/mux_l1_in_0_:S I *L 0.00357 *C 23.100 52.750 +*I mux_bottom_ipin_9\/mux_l1_in_1_:S I *L 0.00357 *C 26.320 55.760 +*N mux_tree_tapbuf_size10_5_sram[0]:5 *C 26.220 55.760 +*N mux_tree_tapbuf_size10_5_sram[0]:6 *C 26.220 55.715 +*N mux_tree_tapbuf_size10_5_sram[0]:7 *C 26.220 53.085 +*N mux_tree_tapbuf_size10_5_sram[0]:8 *C 26.175 53.040 +*N mux_tree_tapbuf_size10_5_sram[0]:9 *C 23.138 53.040 +*N mux_tree_tapbuf_size10_5_sram[0]:10 *C 23.000 52.725 +*N mux_tree_tapbuf_size10_5_sram[0]:11 *C 23.100 52.773 +*N mux_tree_tapbuf_size10_5_sram[0]:12 *C 17.985 52.700 +*N mux_tree_tapbuf_size10_5_sram[0]:13 *C 17.940 52.655 +*N mux_tree_tapbuf_size10_5_sram[0]:14 *C 17.940 50.025 +*N mux_tree_tapbuf_size10_5_sram[0]:15 *C 17.940 49.980 +*N mux_tree_tapbuf_size10_5_sram[0]:16 *C 17.617 49.980 +*N mux_tree_tapbuf_size10_5_sram[0]:17 *C 15.043 45.560 +*N mux_tree_tapbuf_size10_5_sram[0]:18 *C 12.925 45.560 +*N mux_tree_tapbuf_size10_5_sram[0]:19 *C 12.880 45.605 +*N mux_tree_tapbuf_size10_5_sram[0]:20 *C 12.880 49.935 +*N mux_tree_tapbuf_size10_5_sram[0]:21 *C 12.925 49.980 +*N mux_tree_tapbuf_size10_5_sram[0]:22 *C 14.565 49.980 + +*CAP +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_9\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_ipin_9\/mux_l1_in_0_:S 1e-06 +4 mux_bottom_ipin_9\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_5_sram[0]:5 3.359086e-05 +6 mux_tree_tapbuf_size10_5_sram[0]:6 0.0001602724 +7 mux_tree_tapbuf_size10_5_sram[0]:7 0.0001602724 +8 mux_tree_tapbuf_size10_5_sram[0]:8 0.0002695065 +9 mux_tree_tapbuf_size10_5_sram[0]:9 0.0002887999 +10 mux_tree_tapbuf_size10_5_sram[0]:10 1.449665e-05 +11 mux_tree_tapbuf_size10_5_sram[0]:11 0.0003351316 +12 mux_tree_tapbuf_size10_5_sram[0]:12 0.0003013415 +13 mux_tree_tapbuf_size10_5_sram[0]:13 0.00015989 +14 mux_tree_tapbuf_size10_5_sram[0]:14 0.00015989 +15 mux_tree_tapbuf_size10_5_sram[0]:15 5.355574e-05 +16 mux_tree_tapbuf_size10_5_sram[0]:16 0.0002306958 +17 mux_tree_tapbuf_size10_5_sram[0]:17 0.0001675064 +18 mux_tree_tapbuf_size10_5_sram[0]:18 0.0001675064 +19 mux_tree_tapbuf_size10_5_sram[0]:19 0.0002424775 +20 mux_tree_tapbuf_size10_5_sram[0]:20 0.0002424775 +21 mux_tree_tapbuf_size10_5_sram[0]:21 0.0001155113 +22 mux_tree_tapbuf_size10_5_sram[0]:22 0.0003525223 + +*RES +0 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_5_sram[0]:22 0.152 +1 mux_tree_tapbuf_size10_5_sram[0]:16 mem_bottom_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size10_5_sram[0]:16 mux_tree_tapbuf_size10_5_sram[0]:15 0.0001644022 +3 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:11 0.004566964 +4 mux_tree_tapbuf_size10_5_sram[0]:13 mux_tree_tapbuf_size10_5_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size10_5_sram[0]:15 mux_tree_tapbuf_size10_5_sram[0]:14 0.0045 +6 mux_tree_tapbuf_size10_5_sram[0]:14 mux_tree_tapbuf_size10_5_sram[0]:13 0.002348214 +7 mux_tree_tapbuf_size10_5_sram[0]:22 mux_tree_tapbuf_size10_5_sram[0]:21 0.001464286 +8 mux_tree_tapbuf_size10_5_sram[0]:22 mux_tree_tapbuf_size10_5_sram[0]:16 0.002725447 +9 mux_tree_tapbuf_size10_5_sram[0]:21 mux_tree_tapbuf_size10_5_sram[0]:20 0.0045 +10 mux_tree_tapbuf_size10_5_sram[0]:20 mux_tree_tapbuf_size10_5_sram[0]:19 0.003866072 +11 mux_tree_tapbuf_size10_5_sram[0]:18 mux_tree_tapbuf_size10_5_sram[0]:17 0.001890625 +12 mux_tree_tapbuf_size10_5_sram[0]:19 mux_tree_tapbuf_size10_5_sram[0]:18 0.0045 +13 mux_tree_tapbuf_size10_5_sram[0]:17 mux_bottom_ipin_9\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_5_sram[0]:8 mux_tree_tapbuf_size10_5_sram[0]:7 0.0045 +15 mux_tree_tapbuf_size10_5_sram[0]:7 mux_tree_tapbuf_size10_5_sram[0]:6 0.002348214 +16 mux_tree_tapbuf_size10_5_sram[0]:5 mux_bottom_ipin_9\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_5_sram[0]:6 mux_tree_tapbuf_size10_5_sram[0]:5 0.0045 +18 mux_tree_tapbuf_size10_5_sram[0]:11 mux_bottom_ipin_9\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_5_sram[0]:11 mux_tree_tapbuf_size10_5_sram[0]:10 8.928572e-05 +20 mux_tree_tapbuf_size10_5_sram[0]:11 mux_tree_tapbuf_size10_5_sram[0]:9 0.0001061508 +21 mux_tree_tapbuf_size10_5_sram[0]:9 mux_tree_tapbuf_size10_5_sram[0]:8 0.002712053 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[0] 0.003034276 //LENGTH 24.325 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.005 31.280 +*I mux_bottom_ipin_2\/mux_l1_in_0_:S I *L 0.00357 *C 44.280 25.160 +*I mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 37.435 15.300 +*N mux_tree_tapbuf_size8_0_sram[0]:3 *C 37.462 15.323 +*N mux_tree_tapbuf_size8_0_sram[0]:4 *C 37.720 15.335 +*N mux_tree_tapbuf_size8_0_sram[0]:5 *C 37.720 15.640 +*N mux_tree_tapbuf_size8_0_sram[0]:6 *C 43.655 15.640 +*N mux_tree_tapbuf_size8_0_sram[0]:7 *C 43.700 15.685 +*N mux_tree_tapbuf_size8_0_sram[0]:8 *C 44.242 25.160 +*N mux_tree_tapbuf_size8_0_sram[0]:9 *C 43.745 25.160 +*N mux_tree_tapbuf_size8_0_sram[0]:10 *C 43.700 25.160 +*N mux_tree_tapbuf_size8_0_sram[0]:11 *C 43.700 31.235 +*N mux_tree_tapbuf_size8_0_sram[0]:12 *C 43.700 31.280 +*N mux_tree_tapbuf_size8_0_sram[0]:13 *C 44.005 31.280 + +*CAP +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_2\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_0_sram[0]:3 3.42832e-05 +4 mux_tree_tapbuf_size8_0_sram[0]:4 5.73696e-05 +5 mux_tree_tapbuf_size8_0_sram[0]:5 0.0004548987 +6 mux_tree_tapbuf_size8_0_sram[0]:6 0.0004318123 +7 mux_tree_tapbuf_size8_0_sram[0]:7 0.0005511304 +8 mux_tree_tapbuf_size8_0_sram[0]:8 7.511146e-05 +9 mux_tree_tapbuf_size8_0_sram[0]:9 7.511146e-05 +10 mux_tree_tapbuf_size8_0_sram[0]:10 0.0009213864 +11 mux_tree_tapbuf_size8_0_sram[0]:11 0.0003373141 +12 mux_tree_tapbuf_size8_0_sram[0]:12 4.903747e-05 +13 mux_tree_tapbuf_size8_0_sram[0]:13 4.382146e-05 + +*RES +0 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_0_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_0_sram[0]:8 mux_bottom_ipin_2\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:8 0.0004441965 +3 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:7 0.008459822 +5 mux_tree_tapbuf_size8_0_sram[0]:6 mux_tree_tapbuf_size8_0_sram[0]:5 0.005299107 +6 mux_tree_tapbuf_size8_0_sram[0]:7 mux_tree_tapbuf_size8_0_sram[0]:6 0.0045 +7 mux_tree_tapbuf_size8_0_sram[0]:3 mem_bottom_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_0_sram[0]:12 mux_tree_tapbuf_size8_0_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size8_0_sram[0]:11 mux_tree_tapbuf_size8_0_sram[0]:10 0.005424107 +10 mux_tree_tapbuf_size8_0_sram[0]:13 mux_tree_tapbuf_size8_0_sram[0]:12 0.0001657609 +11 mux_tree_tapbuf_size8_0_sram[0]:4 mux_tree_tapbuf_size8_0_sram[0]:3 0.0001739865 +12 mux_tree_tapbuf_size8_0_sram[0]:5 mux_tree_tapbuf_size8_0_sram[0]:4 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[3] 0.002217496 //LENGTH 17.885 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 32.505 69.700 +*I mem_bottom_ipin_7\/FTB_12__51:A I *L 0.001746 *C 26.680 63.920 +*I mux_bottom_ipin_7\/mux_l4_in_0_:S I *L 0.00357 *C 27.700 61.495 +*N mux_tree_tapbuf_size8_3_sram[3]:3 *C 27.700 61.495 +*N mux_tree_tapbuf_size8_3_sram[3]:4 *C 26.718 63.920 +*N mux_tree_tapbuf_size8_3_sram[3]:5 *C 27.555 63.920 +*N mux_tree_tapbuf_size8_3_sram[3]:6 *C 27.600 63.875 +*N mux_tree_tapbuf_size8_3_sram[3]:7 *C 27.600 61.925 +*N mux_tree_tapbuf_size8_3_sram[3]:8 *C 27.700 61.880 +*N mux_tree_tapbuf_size8_3_sram[3]:9 *C 30.775 61.880 +*N mux_tree_tapbuf_size8_3_sram[3]:10 *C 30.820 61.925 +*N mux_tree_tapbuf_size8_3_sram[3]:11 *C 30.820 69.655 +*N mux_tree_tapbuf_size8_3_sram[3]:12 *C 30.865 69.700 +*N mux_tree_tapbuf_size8_3_sram[3]:13 *C 32.468 69.700 + +*CAP +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_7\/FTB_12__51:A 1e-06 +2 mux_bottom_ipin_7\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_3_sram[3]:3 6.493874e-05 +4 mux_tree_tapbuf_size8_3_sram[3]:4 6.714226e-05 +5 mux_tree_tapbuf_size8_3_sram[3]:5 6.714226e-05 +6 mux_tree_tapbuf_size8_3_sram[3]:6 0.000136086 +7 mux_tree_tapbuf_size8_3_sram[3]:7 0.000136086 +8 mux_tree_tapbuf_size8_3_sram[3]:8 0.000327629 +9 mux_tree_tapbuf_size8_3_sram[3]:9 0.0002928901 +10 mux_tree_tapbuf_size8_3_sram[3]:10 0.0004466365 +11 mux_tree_tapbuf_size8_3_sram[3]:11 0.0004466365 +12 mux_tree_tapbuf_size8_3_sram[3]:12 0.0001146544 +13 mux_tree_tapbuf_size8_3_sram[3]:13 0.0001146544 + +*RES +0 mem_bottom_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_3_sram[3]:13 0.152 +1 mux_tree_tapbuf_size8_3_sram[3]:9 mux_tree_tapbuf_size8_3_sram[3]:8 0.002745536 +2 mux_tree_tapbuf_size8_3_sram[3]:10 mux_tree_tapbuf_size8_3_sram[3]:9 0.0045 +3 mux_tree_tapbuf_size8_3_sram[3]:12 mux_tree_tapbuf_size8_3_sram[3]:11 0.0045 +4 mux_tree_tapbuf_size8_3_sram[3]:11 mux_tree_tapbuf_size8_3_sram[3]:10 0.006901786 +5 mux_tree_tapbuf_size8_3_sram[3]:13 mux_tree_tapbuf_size8_3_sram[3]:12 0.001430804 +6 mux_tree_tapbuf_size8_3_sram[3]:3 mux_bottom_ipin_7\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[3]:7 0.0045 +8 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[3]:3 0.00034375 +9 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:6 0.001741071 +10 mux_tree_tapbuf_size8_3_sram[3]:5 mux_tree_tapbuf_size8_3_sram[3]:4 0.0007477679 +11 mux_tree_tapbuf_size8_3_sram[3]:6 mux_tree_tapbuf_size8_3_sram[3]:5 0.0045 +12 mux_tree_tapbuf_size8_3_sram[3]:4 mem_bottom_ipin_7\/FTB_12__51:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[2] 0.005123837 //LENGTH 35.635 LUMPCC 0.001141494 DR + +*CONN +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 95.985 47.600 +*I mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 75.615 49.980 +*I mux_bottom_ipin_14\/mux_l3_in_0_:S I *L 0.00357 *C 83.620 45.175 +*I mux_bottom_ipin_14\/mux_l3_in_1_:S I *L 0.00357 *C 85.660 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:4 *C 85.660 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:5 *C 85.560 44.540 +*N mux_tree_tapbuf_size8_6_sram[2]:6 *C 84.180 44.540 +*N mux_tree_tapbuf_size8_6_sram[2]:7 *C 84.180 44.880 +*N mux_tree_tapbuf_size8_6_sram[2]:8 *C 83.695 44.880 +*N mux_tree_tapbuf_size8_6_sram[2]:9 *C 83.640 44.880 +*N mux_tree_tapbuf_size8_6_sram[2]:10 *C 83.620 45.175 +*N mux_tree_tapbuf_size8_6_sram[2]:11 *C 83.620 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:12 *C 81.005 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:13 *C 80.960 45.605 +*N mux_tree_tapbuf_size8_6_sram[2]:14 *C 75.653 49.980 +*N mux_tree_tapbuf_size8_6_sram[2]:15 *C 79.995 49.980 +*N mux_tree_tapbuf_size8_6_sram[2]:16 *C 80.040 49.935 +*N mux_tree_tapbuf_size8_6_sram[2]:17 *C 80.040 46.920 +*N mux_tree_tapbuf_size8_6_sram[2]:18 *C 80.960 46.863 +*N mux_tree_tapbuf_size8_6_sram[2]:19 *C 80.968 46.920 +*N mux_tree_tapbuf_size8_6_sram[2]:20 *C 95.213 46.920 +*N mux_tree_tapbuf_size8_6_sram[2]:21 *C 95.220 46.977 +*N mux_tree_tapbuf_size8_6_sram[2]:22 *C 95.220 47.555 +*N mux_tree_tapbuf_size8_6_sram[2]:23 *C 95.265 47.600 +*N mux_tree_tapbuf_size8_6_sram[2]:24 *C 95.948 47.600 + +*CAP +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_ipin_14\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_ipin_14\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_6_sram[2]:4 9.51011e-05 +5 mux_tree_tapbuf_size8_6_sram[2]:5 0.0001682154 +6 mux_tree_tapbuf_size8_6_sram[2]:6 0.0001282509 +7 mux_tree_tapbuf_size8_6_sram[2]:7 6.636351e-05 +8 mux_tree_tapbuf_size8_6_sram[2]:8 7.186994e-05 +9 mux_tree_tapbuf_size8_6_sram[2]:9 2.60335e-05 +10 mux_tree_tapbuf_size8_6_sram[2]:10 9.545671e-05 +11 mux_tree_tapbuf_size8_6_sram[2]:11 0.0002356757 +12 mux_tree_tapbuf_size8_6_sram[2]:12 0.0002106018 +13 mux_tree_tapbuf_size8_6_sram[2]:13 0.0001008125 +14 mux_tree_tapbuf_size8_6_sram[2]:14 0.0002881345 +15 mux_tree_tapbuf_size8_6_sram[2]:15 0.0002881345 +16 mux_tree_tapbuf_size8_6_sram[2]:16 0.0001865883 +17 mux_tree_tapbuf_size8_6_sram[2]:17 0.0002451166 +18 mux_tree_tapbuf_size8_6_sram[2]:18 0.0001593409 +19 mux_tree_tapbuf_size8_6_sram[2]:19 0.000686094 +20 mux_tree_tapbuf_size8_6_sram[2]:20 0.000686094 +21 mux_tree_tapbuf_size8_6_sram[2]:21 5.767222e-05 +22 mux_tree_tapbuf_size8_6_sram[2]:22 5.767222e-05 +23 mux_tree_tapbuf_size8_6_sram[2]:23 6.255804e-05 +24 mux_tree_tapbuf_size8_6_sram[2]:24 6.255804e-05 +25 mux_tree_tapbuf_size8_6_sram[2]:19 prog_clk[0]:236 0.0004374493 +26 mux_tree_tapbuf_size8_6_sram[2]:20 prog_clk[0]:231 0.0004374493 +27 mux_tree_tapbuf_size8_6_sram[2]:19 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001332975 +28 mux_tree_tapbuf_size8_6_sram[2]:20 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001332975 + +*RES +0 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_6_sram[2]:24 0.152 +1 mux_tree_tapbuf_size8_6_sram[2]:18 mux_tree_tapbuf_size8_6_sram[2]:17 0.0008214285 +2 mux_tree_tapbuf_size8_6_sram[2]:18 mux_tree_tapbuf_size8_6_sram[2]:13 0.001122768 +3 mux_tree_tapbuf_size8_6_sram[2]:19 mux_tree_tapbuf_size8_6_sram[2]:18 0.00341 +4 mux_tree_tapbuf_size8_6_sram[2]:21 mux_tree_tapbuf_size8_6_sram[2]:20 0.00341 +5 mux_tree_tapbuf_size8_6_sram[2]:20 mux_tree_tapbuf_size8_6_sram[2]:19 0.002231717 +6 mux_tree_tapbuf_size8_6_sram[2]:23 mux_tree_tapbuf_size8_6_sram[2]:22 0.0045 +7 mux_tree_tapbuf_size8_6_sram[2]:22 mux_tree_tapbuf_size8_6_sram[2]:21 0.000515625 +8 mux_tree_tapbuf_size8_6_sram[2]:24 mux_tree_tapbuf_size8_6_sram[2]:23 0.000609375 +9 mux_tree_tapbuf_size8_6_sram[2]:10 mux_bottom_ipin_14\/mux_l3_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_6_sram[2]:10 mux_tree_tapbuf_size8_6_sram[2]:9 0.0002633929 +11 mux_tree_tapbuf_size8_6_sram[2]:10 mux_tree_tapbuf_size8_6_sram[2]:8 0.0002633929 +12 mux_tree_tapbuf_size8_6_sram[2]:14 mem_bottom_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size8_6_sram[2]:15 mux_tree_tapbuf_size8_6_sram[2]:14 0.003877232 +14 mux_tree_tapbuf_size8_6_sram[2]:16 mux_tree_tapbuf_size8_6_sram[2]:15 0.0045 +15 mux_tree_tapbuf_size8_6_sram[2]:12 mux_tree_tapbuf_size8_6_sram[2]:11 0.002334821 +16 mux_tree_tapbuf_size8_6_sram[2]:13 mux_tree_tapbuf_size8_6_sram[2]:12 0.0045 +17 mux_tree_tapbuf_size8_6_sram[2]:4 mux_bottom_ipin_14\/mux_l3_in_1_:S 0.152 +18 mux_tree_tapbuf_size8_6_sram[2]:11 mux_tree_tapbuf_size8_6_sram[2]:10 0.00034375 +19 mux_tree_tapbuf_size8_6_sram[2]:8 mux_tree_tapbuf_size8_6_sram[2]:7 0.0004330357 +20 mux_tree_tapbuf_size8_6_sram[2]:7 mux_tree_tapbuf_size8_6_sram[2]:6 0.0003035714 +21 mux_tree_tapbuf_size8_6_sram[2]:6 mux_tree_tapbuf_size8_6_sram[2]:5 0.001232143 +22 mux_tree_tapbuf_size8_6_sram[2]:5 mux_tree_tapbuf_size8_6_sram[2]:4 0.0009107144 +23 mux_tree_tapbuf_size8_6_sram[2]:17 mux_tree_tapbuf_size8_6_sram[2]:16 0.002691964 + +*END + +*D_NET mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005020652 //LENGTH 3.880 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_1\/mux_l2_in_2_:X O *L 0 *C 51.695 63.240 +*I mux_bottom_ipin_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 50.045 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 50.045 61.540 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 50.140 61.585 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 50.140 63.195 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 50.185 63.240 +*N mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 51.658 63.240 + +*CAP +0 mux_bottom_ipin_1\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_1\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.938781e-05 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000112422 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000112422 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001229167 +6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001229167 + +*RES +0 mux_bottom_ipin_1\/mux_l2_in_2_:X mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_1\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0014375 +5 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0007647414 //LENGTH 5.660 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_4\/mux_l3_in_1_:X O *L 0 *C 55.375 23.460 +*I mux_bottom_ipin_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 54.915 28.220 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 54.915 28.220 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 55.200 28.220 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 55.200 28.175 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 55.200 23.505 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 55.200 23.460 +*N mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 55.375 23.460 + +*CAP +0 mux_bottom_ipin_4\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_4\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.522602e-05 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.123196e-05 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002673932 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002673932 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.679496e-05 +7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.470198e-05 + +*RES +0 mux_bottom_ipin_4\/mux_l3_in_1_:X mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_4\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001548913 +3 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004169643 +6 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007369456 //LENGTH 5.475 LUMPCC 9.06262e-05 DR + +*CONN +*I mux_bottom_ipin_8\/mux_l2_in_0_:X O *L 0 *C 17.195 31.620 +*I mux_bottom_ipin_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 15.180 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 15.218 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 16.975 34.340 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 17.020 34.295 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 17.020 31.665 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 17.020 31.620 +*N mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 17.195 31.620 + +*CAP +0 mux_bottom_ipin_8\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_8\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001103944 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001103944 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001459584 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001459584 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.353545e-05 +7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.807827e-05 +8 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.417308e-05 +9 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.114001e-05 +10 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.417308e-05 +11 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.114001e-05 + +*RES +0 mux_bottom_ipin_8\/mux_l2_in_0_:X mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.510871e-05 +2 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001569197 +5 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_8\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003971361 //LENGTH 2.865 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_12\/mux_l1_in_2_:X O *L 0 *C 73.425 18.020 +*I mux_bottom_ipin_12\/mux_l2_in_1_:A1 I *L 0.00198 *C 76.000 18.020 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 75.963 18.020 +*N mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 73.463 18.020 + +*CAP +0 mux_bottom_ipin_12\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_12\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001975681 +3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001975681 + +*RES +0 mux_bottom_ipin_12\/mux_l1_in_2_:X mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_12\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002232143 + +*END + +*D_NET mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001364884 //LENGTH 10.850 LUMPCC 0.0002303747 DR + +*CONN +*I mux_bottom_ipin_13\/mux_l2_in_0_:X O *L 0 *C 87.685 53.380 +*I mux_bottom_ipin_13\/mux_l3_in_0_:A1 I *L 0.00198 *C 85.925 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 85.963 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 86.895 61.540 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 86.940 61.495 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 86.940 53.425 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 86.985 53.380 +*N mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 87.648 53.380 + +*CAP +0 mux_bottom_ipin_13\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_13\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.587678e-05 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.587678e-05 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004426064 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004426064 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.777135e-05 +7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.777135e-05 +8 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_7_sram[2]:7 4.819049e-05 +9 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_7_sram[2]:8 4.819049e-05 +10 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_7_sram[2]:10 1.563803e-05 +11 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_7_sram[2]:9 1.563803e-05 +12 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.135884e-05 +13 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.135884e-05 + +*RES +0 mux_bottom_ipin_13\/mux_l2_in_0_:X mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_13\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.007205358 +6 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001109732 //LENGTH 8.430 LUMPCC 0.0002500392 DR + +*CONN +*I mux_bottom_ipin_6\/mux_l2_in_0_:X O *L 0 *C 79.755 31.960 +*I mux_bottom_ipin_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 79.485 39.780 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 79.485 39.780 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 79.580 39.735 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 79.580 32.005 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 79.580 31.960 +*N mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 79.755 31.960 + +*CAP +0 mux_bottom_ipin_6\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_6\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.837514e-05 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003559366 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003559366 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.057496e-05 +6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.686947e-05 +7 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001250196 +8 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001250196 + +*RES +0 mux_bottom_ipin_6\/mux_l2_in_0_:X mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_6\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.006901786 +5 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001499923 //LENGTH 12.090 LUMPCC 0.00044918 DR + +*CONN +*I mux_bottom_ipin_7\/mux_l4_in_0_:X O *L 0 *C 26.855 61.540 +*I mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 26.325 71.950 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 26.325 71.950 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 26.220 72.080 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 26.220 72.035 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 26.220 61.585 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 26.265 61.540 +*N mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 26.818 61.540 + +*CAP +0 mux_bottom_ipin_7\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.861826e-05 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.166348e-05 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004251825 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0004251825 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.904802e-05 +7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.904802e-05 +8 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size8_3_sram[2]:12 4.640444e-06 +9 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size8_3_sram[2]:11 4.640444e-06 +10 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size8_3_sram[2]:10 0.0002199496 +11 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size8_3_sram[2]:9 0.0002199496 + +*RES +0 mux_bottom_ipin_7\/mux_l4_in_0_:X mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 +2 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.009330357 +4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.706522e-05 +5 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_bottom_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003943089 //LENGTH 2.860 LUMPCC 0.0001385172 DR + +*CONN +*I mux_bottom_ipin_14\/mux_l2_in_2_:X O *L 0 *C 88.955 45.220 +*I mux_bottom_ipin_14\/mux_l3_in_1_:A1 I *L 0.00198 *C 86.385 45.220 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 86.422 45.220 +*N mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 88.918 45.220 + +*CAP +0 mux_bottom_ipin_14\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_14\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001268958 +3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001268958 +4 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_6_sram[1]:20 6.925862e-05 +5 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_6_sram[1]:21 6.925862e-05 + +*RES +0 mux_bottom_ipin_14\/mux_l2_in_2_:X mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_14\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002227678 + +*END + +*D_NET mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001143659 //LENGTH 10.790 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_15\/mux_l4_in_0_:X O *L 0 *C 67.445 66.300 +*I mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 71.940 71.895 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 71.903 71.795 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 70.425 71.740 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 70.380 71.695 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 70.380 66.345 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 70.335 66.300 +*N mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 67.483 66.300 + +*CAP +0 mux_bottom_ipin_15\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 9.285694e-05 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.285694e-05 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003007172 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003007172 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001772553 +7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001772553 + +*RES +0 mux_bottom_ipin_15\/mux_l4_in_0_:X mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002546875 +2 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004776786 +4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001319197 +5 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_bottom_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chanx_left_out[5] 0.001012348 //LENGTH 7.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 7.360 68.680 +*P chanx_left_out[5] O *L 0.7423 *C 1.305 68.000 +*N chanx_left_out[5]:2 *C 7.353 68.000 +*N chanx_left_out[5]:3 *C 7.360 68.058 +*N chanx_left_out[5]:4 *C 7.360 68.635 +*N chanx_left_out[5]:5 *C 7.360 68.680 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 chanx_left_out[5] 0.0004348251 +2 chanx_left_out[5]:2 0.0004348251 +3 chanx_left_out[5]:3 5.40885e-05 +4 chanx_left_out[5]:4 5.40885e-05 +5 chanx_left_out[5]:5 3.352107e-05 + +*RES +0 ropt_mt_inst_737:X chanx_left_out[5]:5 0.152 +1 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +2 chanx_left_out[5]:2 chanx_left_out[5] 0.0009474416 +3 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +4 chanx_left_out[5]:4 chanx_left_out[5]:3 0.0005156251 + +*END + +*D_NET chanx_left_out[6] 0.001108924 //LENGTH 9.430 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 4.140 56.100 +*P chanx_left_out[6] O *L 0.7423 *C 1.305 50.320 +*N chanx_left_out[6]:2 *C 2.752 50.320 +*N chanx_left_out[6]:3 *C 2.760 50.378 +*N chanx_left_out[6]:4 *C 2.760 56.055 +*N chanx_left_out[6]:5 *C 2.805 56.100 +*N chanx_left_out[6]:6 *C 4.103 56.100 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 chanx_left_out[6] 0.0001302528 +2 chanx_left_out[6]:2 0.0001302528 +3 chanx_left_out[6]:3 0.0003205762 +4 chanx_left_out[6]:4 0.0003205762 +5 chanx_left_out[6]:5 0.0001031332 +6 chanx_left_out[6]:6 0.0001031332 + +*RES +0 ropt_mt_inst_776:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +2 chanx_left_out[6]:2 chanx_left_out[6] 0.000226775 +3 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +4 chanx_left_out[6]:4 chanx_left_out[6]:3 0.005069197 +5 chanx_left_out[6]:6 chanx_left_out[6]:5 0.001158482 + +*END + +*D_NET ropt_net_183 0.001219537 //LENGTH 7.890 LUMPCC 0.0004972278 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 101.855 59.160 +*I ropt_mt_inst_790:A I *L 0.001767 *C 97.825 61.200 +*N ropt_net_183:2 *C 97.863 61.200 +*N ropt_net_183:3 *C 100.235 61.200 +*N ropt_net_183:4 *C 100.280 61.155 +*N ropt_net_183:5 *C 100.280 60.565 +*N ropt_net_183:6 *C 100.325 60.520 +*N ropt_net_183:7 *C 102.075 60.520 +*N ropt_net_183:8 *C 102.120 60.475 +*N ropt_net_183:9 *C 102.120 59.205 +*N ropt_net_183:10 *C 102.120 59.160 +*N ropt_net_183:11 *C 101.855 59.160 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 ropt_mt_inst_790:A 1e-06 +2 ropt_net_183:2 5.563836e-05 +3 ropt_net_183:3 5.563836e-05 +4 ropt_net_183:4 7.070768e-05 +5 ropt_net_183:5 7.070768e-05 +6 ropt_net_183:6 9.343373e-05 +7 ropt_net_183:7 9.343373e-05 +8 ropt_net_183:8 8.454823e-05 +9 ropt_net_183:9 8.454823e-05 +10 ropt_net_183:10 5.199743e-05 +11 ropt_net_183:11 5.96556e-05 +12 ropt_net_183:2 ropt_net_157:11 0.0001023661 +13 ropt_net_183:3 ropt_net_157:10 0.0001023661 +14 ropt_net_183:6 ropt_net_157:11 4.993096e-07 +15 ropt_net_183:7 ropt_net_157:10 4.993096e-07 +16 ropt_net_183:2 chanx_right_out[5]:6 5.970895e-05 +17 ropt_net_183:3 chanx_right_out[5]:5 5.970895e-05 +18 ropt_net_183:4 chanx_right_out[5]:4 5.442163e-08 +19 ropt_net_183:6 chanx_right_out[5]:6 8.010642e-05 +20 ropt_net_183:5 chanx_right_out[5]:3 5.442163e-08 +21 ropt_net_183:7 chanx_right_out[5]:5 8.010642e-05 +22 ropt_net_183:8 chanx_right_out[5]:4 5.878667e-06 +23 ropt_net_183:9 chanx_right_out[5]:3 5.878667e-06 + +*RES +0 ropt_mt_inst_748:X ropt_net_183:11 0.152 +1 ropt_net_183:2 ropt_mt_inst_790:A 0.152 +2 ropt_net_183:3 ropt_net_183:2 0.002118304 +3 ropt_net_183:4 ropt_net_183:3 0.0045 +4 ropt_net_183:6 ropt_net_183:5 0.0045 +5 ropt_net_183:5 ropt_net_183:4 0.0005267857 +6 ropt_net_183:7 ropt_net_183:6 0.0015625 +7 ropt_net_183:8 ropt_net_183:7 0.0045 +8 ropt_net_183:10 ropt_net_183:9 0.0045 +9 ropt_net_183:9 ropt_net_183:8 0.001133929 +10 ropt_net_183:11 ropt_net_183:10 0.0001440218 + +*END + +*D_NET ropt_net_148 0.000759484 //LENGTH 6.805 LUMPCC 0 DR + +*CONN +*I BUFT_P_95:X O *L 0 *C 89.240 8.840 +*I ropt_mt_inst_745:A I *L 0.001766 *C 93.380 6.800 +*N ropt_net_148:2 *C 93.343 6.800 +*N ropt_net_148:3 *C 89.285 6.800 +*N ropt_net_148:4 *C 89.240 6.845 +*N ropt_net_148:5 *C 89.240 8.795 +*N ropt_net_148:6 *C 89.240 8.840 + +*CAP +0 BUFT_P_95:X 1e-06 +1 ropt_mt_inst_745:A 1e-06 +2 ropt_net_148:2 0.0002319318 +3 ropt_net_148:3 0.0002319318 +4 ropt_net_148:4 0.0001292962 +5 ropt_net_148:5 0.0001292962 +6 ropt_net_148:6 3.502803e-05 + +*RES +0 BUFT_P_95:X ropt_net_148:6 0.152 +1 ropt_net_148:2 ropt_mt_inst_745:A 0.152 +2 ropt_net_148:3 ropt_net_148:2 0.003622768 +3 ropt_net_148:4 ropt_net_148:3 0.0045 +4 ropt_net_148:6 ropt_net_148:5 0.0045 +5 ropt_net_148:5 ropt_net_148:4 0.001741072 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..1e9b062 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef @@ -0,0 +1,7042 @@ +*SPEF "1481-1998" +*DESIGN "cbx_1__2_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 3.220 0.680 +chanx_left_in[0] I *C 0.690 46.240 +chanx_left_in[1] I *C 0.690 20.400 +chanx_left_in[2] I *C 0.690 25.840 +chanx_left_in[3] I *C 0.690 55.760 +chanx_left_in[4] I *C 0.690 51.680 +chanx_left_in[5] I *C 0.690 68.000 +chanx_left_in[6] I *C 0.690 57.120 +chanx_left_in[7] I *C 0.690 66.640 +chanx_left_in[8] I *C 0.690 58.480 +chanx_left_in[9] I *C 0.690 17.680 +chanx_left_in[10] I *C 0.690 24.480 +chanx_left_in[11] I *C 0.690 42.160 +chanx_left_in[12] I *C 0.690 14.960 +chanx_left_in[13] I *C 0.690 39.440 +chanx_left_in[14] I *C 0.690 63.920 +chanx_left_in[15] I *C 0.690 40.800 +chanx_left_in[16] I *C 0.690 36.720 +chanx_left_in[17] I *C 0.690 61.200 +chanx_left_in[18] I *C 0.690 62.560 +chanx_left_in[19] I *C 0.690 19.040 +chanx_right_in[0] I *C 104.190 53.040 +chanx_right_in[1] I *C 104.190 66.640 +chanx_right_in[2] I *C 104.190 6.800 +chanx_right_in[3] I *C 104.190 21.760 +chanx_right_in[4] I *C 104.190 31.280 +chanx_right_in[5] I *C 104.190 43.520 +chanx_right_in[6] I *C 104.190 16.320 +chanx_right_in[7] I *C 104.190 20.400 +chanx_right_in[8] I *C 104.190 58.480 +chanx_right_in[9] I *C 104.190 38.080 +chanx_right_in[10] I *C 104.190 70.720 +chanx_right_in[11] I *C 104.190 65.280 +chanx_right_in[12] I *C 104.190 55.760 +chanx_right_in[13] I *C 104.190 59.840 +chanx_right_in[14] I *C 104.190 42.160 +chanx_right_in[15] I *C 104.190 17.680 +chanx_right_in[16] I *C 104.190 27.200 +chanx_right_in[17] I *C 104.190 63.920 +chanx_right_in[18] I *C 104.190 39.440 +chanx_right_in[19] I *C 104.190 61.200 +ccff_head[0] I *C 104.190 50.320 +chanx_left_out[0] O *C 2.300 75.480 +chanx_left_out[1] O *C 0.690 29.920 +chanx_left_out[2] O *C 0.690 72.080 +chanx_left_out[3] O *C 0.690 69.360 +chanx_left_out[4] O *C 0.690 6.800 +chanx_left_out[5] O *C 0.690 35.360 +chanx_left_out[6] O *C 0.690 4.080 +chanx_left_out[7] O *C 0.690 23.120 +chanx_left_out[8] O *C 0.690 50.320 +chanx_left_out[9] O *C 0.690 8.160 +chanx_left_out[10] O *C 0.690 53.040 +chanx_left_out[11] O *C 0.690 31.280 +chanx_left_out[12] O *C 0.690 47.600 +chanx_left_out[13] O *C 0.690 9.520 +chanx_left_out[14] O *C 4.600 0.680 +chanx_left_out[15] O *C 0.690 28.560 +chanx_left_out[16] O *C 0.690 13.600 +chanx_left_out[17] O *C 0.690 34.000 +chanx_left_out[18] O *C 0.690 12.240 +chanx_left_out[19] O *C 0.690 44.880 +chanx_right_out[0] O *C 104.190 12.240 +chanx_right_out[1] O *C 104.190 14.960 +chanx_right_out[2] O *C 102.580 75.480 +chanx_right_out[3] O *C 104.190 34.000 +chanx_right_out[4] O *C 104.190 23.120 +chanx_right_out[5] O *C 102.580 0.680 +chanx_right_out[6] O *C 104.190 4.080 +chanx_right_out[7] O *C 104.190 44.880 +chanx_right_out[8] O *C 104.190 48.960 +chanx_right_out[9] O *C 104.190 72.080 +chanx_right_out[10] O *C 104.190 9.520 +chanx_right_out[11] O *C 104.190 36.720 +chanx_right_out[12] O *C 104.190 5.440 +chanx_right_out[13] O *C 104.190 47.600 +chanx_right_out[14] O *C 104.190 32.640 +chanx_right_out[15] O *C 104.190 69.360 +chanx_right_out[16] O *C 104.190 28.560 +chanx_right_out[17] O *C 104.190 25.840 +chanx_right_out[18] O *C 104.190 10.880 +chanx_right_out[19] O *C 104.190 54.400 +top_grid_pin_0_[0] O *C 79.120 75.480 +ccff_tail[0] O *C 57.500 75.480 +VDD I *C 52.440 38.080 +VSS I *C 52.440 38.080 + +*D_NET chanx_left_in[0] 0.01601104 //LENGTH 141.895 LUMPCC 0.002133131 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.230 46.240 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 83.720 56.100 +*I BUFT_P_127:A I *L 0.001767 *C 97.980 17.680 +*N chanx_left_in[0]:3 *C 97.943 17.680 +*N chanx_left_in[0]:4 *C 93.885 17.680 +*N chanx_left_in[0]:5 *C 93.840 17.725 +*N chanx_left_in[0]:6 *C 93.840 46.875 +*N chanx_left_in[0]:7 *C 93.795 46.920 +*N chanx_left_in[0]:8 *C 83.720 46.920 +*N chanx_left_in[0]:9 *C 83.720 56.100 +*N chanx_left_in[0]:10 *C 83.720 56.055 +*N chanx_left_in[0]:11 *C 83.720 47.645 +*N chanx_left_in[0]:12 *C 83.720 47.570 +*N chanx_left_in[0]:13 *C 75.945 47.600 +*N chanx_left_in[0]:14 *C 75.900 47.555 +*N chanx_left_in[0]:15 *C 75.900 46.977 +*N chanx_left_in[0]:16 *C 75.892 46.920 +*N chanx_left_in[0]:17 *C 43.700 46.920 +*N chanx_left_in[0]:18 *C 43.700 46.240 +*N chanx_left_in[0]:19 *C 23.920 46.240 +*N chanx_left_in[0]:20 *C 23.920 46.920 +*N chanx_left_in[0]:21 *C 14.720 46.920 +*N chanx_left_in[0]:22 *C 14.720 46.240 + +*CAP +0 chanx_left_in[0] 0.0008677986 +1 mux_bottom_ipin_0\/mux_l1_in_0_:A1 1e-06 +2 BUFT_P_127:A 1e-06 +3 chanx_left_in[0]:3 0.0002283317 +4 chanx_left_in[0]:4 0.0002283317 +5 chanx_left_in[0]:5 0.001171654 +6 chanx_left_in[0]:6 0.001171654 +7 chanx_left_in[0]:7 0.0006159884 +8 chanx_left_in[0]:8 0.0006616273 +9 chanx_left_in[0]:9 3.582121e-05 +10 chanx_left_in[0]:10 0.000431737 +11 chanx_left_in[0]:11 0.000431737 +12 chanx_left_in[0]:12 0.0004586014 +13 chanx_left_in[0]:13 0.0004129626 +14 chanx_left_in[0]:14 5.185365e-05 +15 chanx_left_in[0]:15 5.185365e-05 +16 chanx_left_in[0]:16 0.001583987 +17 chanx_left_in[0]:17 0.001632724 +18 chanx_left_in[0]:18 0.0008284239 +19 chanx_left_in[0]:19 0.0008248067 +20 chanx_left_in[0]:20 0.0006239844 +21 chanx_left_in[0]:21 0.0006365478 +22 chanx_left_in[0]:22 0.0009254818 +23 chanx_left_in[0]:6 chanx_left_in[19]:4 0.0003119061 +24 chanx_left_in[0]:5 chanx_left_in[19]:5 0.0003119061 +25 chanx_left_in[0]:16 chanx_right_in[5]:15 0.0001725555 +26 chanx_left_in[0]:16 chanx_right_in[5]:17 5.365254e-05 +27 chanx_left_in[0]:16 chanx_right_in[5]:19 8.587097e-05 +28 chanx_left_in[0]:6 chanx_right_in[5]:19 1.490829e-05 +29 chanx_left_in[0]:5 chanx_right_in[5]:20 1.490829e-05 +30 chanx_left_in[0]:21 chanx_right_in[5]:14 2.477718e-05 +31 chanx_left_in[0]:20 chanx_right_in[5]:15 2.477718e-05 +32 chanx_left_in[0]:19 chanx_right_in[5]:14 0.0003384625 +33 chanx_left_in[0]:18 chanx_right_in[5]:15 0.0003384625 +34 chanx_left_in[0]:17 chanx_right_in[5]:14 0.0001725555 +35 chanx_left_in[0]:17 chanx_right_in[5]:16 5.365254e-05 +36 chanx_left_in[0]:17 chanx_right_in[5]:18 8.587097e-05 +37 chanx_left_in[0]:6 ropt_net_191:5 6.443253e-05 +38 chanx_left_in[0]:5 ropt_net_191:4 6.443253e-05 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:22 0.002113433 +1 chanx_left_in[0]:13 chanx_left_in[0]:12 0.006941965 +2 chanx_left_in[0]:14 chanx_left_in[0]:13 0.0045 +3 chanx_left_in[0]:15 chanx_left_in[0]:14 0.000515625 +4 chanx_left_in[0]:16 chanx_left_in[0]:15 0.00341 +5 chanx_left_in[0]:7 chanx_left_in[0]:6 0.0045 +6 chanx_left_in[0]:6 chanx_left_in[0]:5 0.02602679 +7 chanx_left_in[0]:4 chanx_left_in[0]:3 0.003622768 +8 chanx_left_in[0]:5 chanx_left_in[0]:4 0.0045 +9 chanx_left_in[0]:3 BUFT_P_127:A 0.152 +10 chanx_left_in[0]:12 chanx_left_in[0]:11 0.0045 +11 chanx_left_in[0]:12 chanx_left_in[0]:8 0.0005803572 +12 chanx_left_in[0]:11 chanx_left_in[0]:10 0.007508929 +13 chanx_left_in[0]:9 mux_bottom_ipin_0\/mux_l1_in_0_:A1 0.152 +14 chanx_left_in[0]:10 chanx_left_in[0]:9 0.0045 +15 chanx_left_in[0]:8 chanx_left_in[0]:7 0.008995537 +16 chanx_left_in[0]:22 chanx_left_in[0]:21 0.0001065333 +17 chanx_left_in[0]:21 chanx_left_in[0]:20 0.001441333 +18 chanx_left_in[0]:20 chanx_left_in[0]:19 0.0001065333 +19 chanx_left_in[0]:19 chanx_left_in[0]:18 0.003098866 +20 chanx_left_in[0]:18 chanx_left_in[0]:17 0.0001065333 +21 chanx_left_in[0]:17 chanx_left_in[0]:16 0.005043492 + +*END + +*D_NET chanx_left_in[11] 0.01064693 //LENGTH 94.020 LUMPCC 0.0009585019 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 42.160 +*I BUFT_RR_53:A I *L 0.001767 *C 93.840 42.160 +*N chanx_left_in[11]:2 *C 93.803 42.160 +*N chanx_left_in[11]:3 *C 93.380 42.160 +*N chanx_left_in[11]:4 *C 93.380 42.500 +*N chanx_left_in[11]:5 *C 54.440 42.500 +*N chanx_left_in[11]:6 *C 4.645 42.500 +*N chanx_left_in[11]:7 *C 4.600 42.500 +*N chanx_left_in[11]:8 *C 4.600 42.160 +*N chanx_left_in[11]:9 *C 4.593 42.160 + +*CAP +0 chanx_left_in[11] 0.0001729252 +1 BUFT_RR_53:A 1e-06 +2 chanx_left_in[11]:2 4.739605e-05 +3 chanx_left_in[11]:3 7.328165e-05 +4 chanx_left_in[11]:4 0.001993022 +5 chanx_left_in[11]:5 0.004543948 +6 chanx_left_in[11]:6 0.002576811 +7 chanx_left_in[11]:7 5.173113e-05 +8 chanx_left_in[11]:8 5.538455e-05 +9 chanx_left_in[11]:9 0.0001729252 +10 chanx_left_in[11] chanx_left_in[15] 8.385065e-05 +11 chanx_left_in[11]:6 chanx_left_in[15]:19 6.04579e-05 +12 chanx_left_in[11]:9 chanx_left_in[15]:20 8.385065e-05 +13 chanx_left_in[11]:4 chanx_left_in[15]:13 0.0002833297 +14 chanx_left_in[11]:5 chanx_left_in[15]:14 0.0002833297 +15 chanx_left_in[11]:5 chanx_left_in[15]:18 6.04579e-05 +16 chanx_left_in[11]:6 ropt_net_215:7 5.161266e-05 +17 chanx_left_in[11]:5 ropt_net_215:6 5.161266e-05 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:9 0.0005267917 +1 chanx_left_in[11]:2 BUFT_RR_53:A 0.152 +2 chanx_left_in[11]:6 chanx_left_in[11]:5 0.04445983 +3 chanx_left_in[11]:7 chanx_left_in[11]:6 0.0045 +4 chanx_left_in[11]:8 chanx_left_in[11]:7 0.0001634615 +5 chanx_left_in[11]:9 chanx_left_in[11]:8 0.00341 +6 chanx_left_in[11]:4 chanx_left_in[11]:3 0.0003035715 +7 chanx_left_in[11]:3 chanx_left_in[11]:2 0.0003772322 +8 chanx_left_in[11]:5 chanx_left_in[11]:4 0.03476786 + +*END + +*D_NET chanx_left_in[12] 0.01052138 //LENGTH 96.145 LUMPCC 0.001628611 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 14.960 +*I BUFT_P_139:A I *L 0.001776 *C 90.160 9.520 +*N chanx_left_in[12]:2 *C 90.123 9.520 +*N chanx_left_in[12]:3 *C 88.780 9.520 +*N chanx_left_in[12]:4 *C 88.780 9.180 +*N chanx_left_in[12]:5 *C 74.220 9.180 +*N chanx_left_in[12]:6 *C 24.425 9.180 +*N chanx_left_in[12]:7 *C 24.380 9.225 +*N chanx_left_in[12]:8 *C 24.380 14.902 +*N chanx_left_in[12]:9 *C 24.373 14.960 + +*CAP +0 chanx_left_in[12] 0.001370031 +1 BUFT_P_139:A 1e-06 +2 chanx_left_in[12]:2 9.554208e-05 +3 chanx_left_in[12]:3 0.0001231996 +4 chanx_left_in[12]:4 0.0005956105 +5 chanx_left_in[12]:5 0.002673961 +6 chanx_left_in[12]:6 0.002106007 +7 chanx_left_in[12]:7 0.0002786923 +8 chanx_left_in[12]:8 0.0002786923 +9 chanx_left_in[12]:9 0.001370031 +10 chanx_left_in[12]:6 chanx_left_in[5]:9 0.0005226589 +11 chanx_left_in[12]:4 chanx_left_in[5]:6 9.268976e-05 +12 chanx_left_in[12]:4 chanx_left_in[5]:8 0.0001989571 +13 chanx_left_in[12]:5 chanx_left_in[5]:7 9.268976e-05 +14 chanx_left_in[12]:5 chanx_left_in[5]:8 0.0005226589 +15 chanx_left_in[12]:5 chanx_left_in[5]:9 0.0001989571 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:9 0.003625658 +1 chanx_left_in[12]:2 BUFT_P_139:A 0.152 +2 chanx_left_in[12]:6 chanx_left_in[12]:5 0.04445982 +3 chanx_left_in[12]:7 chanx_left_in[12]:6 0.0045 +4 chanx_left_in[12]:8 chanx_left_in[12]:7 0.005069197 +5 chanx_left_in[12]:9 chanx_left_in[12]:8 0.00341 +6 chanx_left_in[12]:4 chanx_left_in[12]:3 0.0003035715 +7 chanx_left_in[12]:3 chanx_left_in[12]:2 0.001198661 +8 chanx_left_in[12]:5 chanx_left_in[12]:4 0.013 + +*END + +*D_NET chanx_left_in[13] 0.01427985 //LENGTH 119.810 LUMPCC 0.004566592 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 39.440 +*I BUFT_P_140:A I *L 0.001776 *C 97.825 61.200 +*N chanx_left_in[13]:2 *C 97.788 61.200 +*N chanx_left_in[13]:3 *C 96.185 61.200 +*N chanx_left_in[13]:4 *C 96.140 61.155 +*N chanx_left_in[13]:5 *C 96.140 40.165 +*N chanx_left_in[13]:6 *C 96.095 40.120 +*N chanx_left_in[13]:7 *C 89.400 40.120 +*N chanx_left_in[13]:8 *C 39.605 40.120 +*N chanx_left_in[13]:9 *C 39.560 40.075 +*N chanx_left_in[13]:10 *C 39.560 39.498 +*N chanx_left_in[13]:11 *C 39.553 39.440 + +*CAP +0 chanx_left_in[13] 0.001093629 +1 BUFT_P_140:A 1e-06 +2 chanx_left_in[13]:2 0.0001031172 +3 chanx_left_in[13]:3 0.0001031172 +4 chanx_left_in[13]:4 0.0008573252 +5 chanx_left_in[13]:5 0.0008573252 +6 chanx_left_in[13]:6 0.0003530019 +7 chanx_left_in[13]:7 0.002750682 +8 chanx_left_in[13]:8 0.00239768 +9 chanx_left_in[13]:9 5.137328e-05 +10 chanx_left_in[13]:10 5.137328e-05 +11 chanx_left_in[13]:11 0.001093629 +12 chanx_left_in[13]:4 chanx_left_in[7]:6 0.000364898 +13 chanx_left_in[13]:5 chanx_left_in[7]:5 0.000364898 +14 chanx_left_in[13] chanx_left_in[15] 0.0003120771 +15 chanx_left_in[13] chanx_left_in[15]:19 0.0004156366 +16 chanx_left_in[13]:11 chanx_left_in[15]:20 0.0003120771 +17 chanx_left_in[13]:11 chanx_left_in[15]:18 0.0004156366 +18 chanx_left_in[13] chanx_left_in[16] 0.0004559864 +19 chanx_left_in[13]:11 chanx_left_in[16]:10 0.0004559864 +20 chanx_left_in[13] chanx_right_in[9]:14 1.562118e-05 +21 chanx_left_in[13]:6 chanx_right_in[9]:16 7.347155e-05 +22 chanx_left_in[13]:8 chanx_right_in[9]:14 0.0005365132 +23 chanx_left_in[13]:8 chanx_right_in[9]:15 0.0001090921 +24 chanx_left_in[13]:11 chanx_right_in[9]:15 1.562118e-05 +25 chanx_left_in[13]:7 chanx_right_in[9]:16 0.0001090921 +26 chanx_left_in[13]:7 chanx_right_in[9]:15 0.0006099847 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:11 0.006003858 +1 chanx_left_in[13]:2 BUFT_P_140:A 0.152 +2 chanx_left_in[13]:3 chanx_left_in[13]:2 0.001430804 +3 chanx_left_in[13]:4 chanx_left_in[13]:3 0.0045 +4 chanx_left_in[13]:6 chanx_left_in[13]:5 0.0045 +5 chanx_left_in[13]:5 chanx_left_in[13]:4 0.01874107 +6 chanx_left_in[13]:8 chanx_left_in[13]:7 0.04445983 +7 chanx_left_in[13]:9 chanx_left_in[13]:8 0.0045 +8 chanx_left_in[13]:10 chanx_left_in[13]:9 0.000515625 +9 chanx_left_in[13]:11 chanx_left_in[13]:10 0.00341 +10 chanx_left_in[13]:7 chanx_left_in[13]:6 0.005977679 + +*END + +*D_NET chanx_left_in[14] 0.01937084 //LENGTH 133.165 LUMPCC 0.01058933 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 63.920 +*I BUFT_P_141:A I *L 0.001776 *C 94.760 28.560 +*N chanx_left_in[14]:2 *C 94.797 28.560 +*N chanx_left_in[14]:3 *C 96.095 28.560 +*N chanx_left_in[14]:4 *C 96.140 28.605 +*N chanx_left_in[14]:5 *C 96.140 30.543 +*N chanx_left_in[14]:6 *C 96.133 30.600 +*N chanx_left_in[14]:7 *C 86.175 30.600 +*N chanx_left_in[14]:8 *C 36.348 30.600 +*N chanx_left_in[14]:9 *C 36.340 30.658 +*N chanx_left_in[14]:10 *C 36.340 63.863 +*N chanx_left_in[14]:11 *C 36.333 63.920 + +*CAP +0 chanx_left_in[14] 0.0008355 +1 BUFT_P_141:A 1e-06 +2 chanx_left_in[14]:2 0.0001042739 +3 chanx_left_in[14]:3 0.0001042739 +4 chanx_left_in[14]:4 0.0001165252 +5 chanx_left_in[14]:5 0.0001165252 +6 chanx_left_in[14]:6 0.0002319055 +7 chanx_left_in[14]:7 0.001694511 +8 chanx_left_in[14]:8 0.001462605 +9 chanx_left_in[14]:9 0.001639445 +10 chanx_left_in[14]:10 0.001639445 +11 chanx_left_in[14]:11 0.0008354998 +12 chanx_left_in[14] chanx_left_in[7] 0.0004176234 +13 chanx_left_in[14]:11 chanx_left_in[7]:8 0.0004176234 +14 chanx_left_in[14]:6 chanx_left_in[17]:5 0.0001270016 +15 chanx_left_in[14]:8 chanx_left_in[17]:7 0.0006241128 +16 chanx_left_in[14]:8 chanx_left_in[17]:6 0.0005423567 +17 chanx_left_in[14]:7 chanx_left_in[17]:5 0.0005423567 +18 chanx_left_in[14]:7 chanx_left_in[17]:6 0.0007511143 +19 chanx_left_in[14] chanx_left_in[18] 0.0003160884 +20 chanx_left_in[14] chanx_left_in[18]:15 0.001253014 +21 chanx_left_in[14]:11 chanx_left_in[18]:14 0.001253014 +22 chanx_left_in[14]:11 chanx_left_in[18]:16 0.0003160884 +23 chanx_left_in[14]:6 chanx_right_in[4] 0.0004843555 +24 chanx_left_in[14]:7 chanx_right_in[4]:21 0.0004843555 +25 chanx_left_in[14]:8 prog_clk[0]:24 0.001056499 +26 chanx_left_in[14]:8 prog_clk[0]:23 0.0004016801 +27 chanx_left_in[14]:7 prog_clk[0]:23 0.001056499 +28 chanx_left_in[14]:7 prog_clk[0]:18 0.0004016801 +29 chanx_left_in[14]:4 ropt_net_184:5 8.763665e-06 +30 chanx_left_in[14]:5 ropt_net_184:4 8.763665e-06 +31 chanx_left_in[14]:6 ropt_net_184:6 6.316776e-05 +32 chanx_left_in[14]:7 ropt_net_184:7 6.316776e-05 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:11 0.005499391 +1 chanx_left_in[14]:2 BUFT_P_141:A 0.152 +2 chanx_left_in[14]:3 chanx_left_in[14]:2 0.001158482 +3 chanx_left_in[14]:4 chanx_left_in[14]:3 0.0045 +4 chanx_left_in[14]:5 chanx_left_in[14]:4 0.001729911 +5 chanx_left_in[14]:6 chanx_left_in[14]:5 0.00341 +6 chanx_left_in[14]:9 chanx_left_in[14]:8 0.00341 +7 chanx_left_in[14]:8 chanx_left_in[14]:7 0.007806308 +8 chanx_left_in[14]:10 chanx_left_in[14]:9 0.02964732 +9 chanx_left_in[14]:11 chanx_left_in[14]:10 0.00341 +10 chanx_left_in[14]:7 chanx_left_in[14]:6 0.001560008 + +*END + +*D_NET chanx_left_in[15] 0.01817899 //LENGTH 139.070 LUMPCC 0.007384352 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 40.800 +*I ropt_mt_inst_783:A I *L 0.001767 *C 93.380 69.360 +*N chanx_left_in[15]:2 *C 93.380 69.360 +*N chanx_left_in[15]:3 *C 93.380 69.020 +*N chanx_left_in[15]:4 *C 101.155 69.020 +*N chanx_left_in[15]:5 *C 101.200 68.975 +*N chanx_left_in[15]:6 *C 101.200 64.305 +*N chanx_left_in[15]:7 *C 101.155 64.260 +*N chanx_left_in[15]:8 *C 92.460 64.260 +*N chanx_left_in[15]:9 *C 92.460 63.920 +*N chanx_left_in[15]:10 *C 91.125 63.920 +*N chanx_left_in[15]:11 *C 91.080 63.875 +*N chanx_left_in[15]:12 *C 91.080 41.865 +*N chanx_left_in[15]:13 *C 91.035 41.820 +*N chanx_left_in[15]:14 *C 75.945 41.820 +*N chanx_left_in[15]:15 *C 75.900 41.820 +*N chanx_left_in[15]:16 *C 75.900 41.480 +*N chanx_left_in[15]:17 *C 75.892 41.480 +*N chanx_left_in[15]:18 *C 63.650 41.480 +*N chanx_left_in[15]:19 *C 13.800 41.480 +*N chanx_left_in[15]:20 *C 13.800 40.800 + +*CAP +0 chanx_left_in[15] 0.0004125339 +1 ropt_mt_inst_783:A 1e-06 +2 chanx_left_in[15]:2 5.53547e-05 +3 chanx_left_in[15]:3 0.0004267143 +4 chanx_left_in[15]:4 0.000399524 +5 chanx_left_in[15]:5 0.0002812571 +6 chanx_left_in[15]:6 0.0002812571 +7 chanx_left_in[15]:7 0.0005285072 +8 chanx_left_in[15]:8 0.0005519533 +9 chanx_left_in[15]:9 0.0001444871 +10 chanx_left_in[15]:10 0.0001210409 +11 chanx_left_in[15]:11 0.00111897 +12 chanx_left_in[15]:12 0.00111897 +13 chanx_left_in[15]:13 0.0006100899 +14 chanx_left_in[15]:14 0.0006100899 +15 chanx_left_in[15]:15 5.139439e-05 +16 chanx_left_in[15]:16 5.542883e-05 +17 chanx_left_in[15]:17 0.0003096818 +18 chanx_left_in[15]:18 0.001751867 +19 chanx_left_in[15]:19 0.001497086 +20 chanx_left_in[15]:20 0.0004674348 +21 chanx_left_in[15] chanx_left_in[11] 8.385065e-05 +22 chanx_left_in[15]:13 chanx_left_in[11]:4 0.0002833297 +23 chanx_left_in[15]:14 chanx_left_in[11]:5 0.0002833297 +24 chanx_left_in[15]:20 chanx_left_in[11]:9 8.385065e-05 +25 chanx_left_in[15]:19 chanx_left_in[11]:6 6.04579e-05 +26 chanx_left_in[15]:18 chanx_left_in[11]:5 6.04579e-05 +27 chanx_left_in[15] chanx_left_in[13] 0.0003120771 +28 chanx_left_in[15]:20 chanx_left_in[13]:11 0.0003120771 +29 chanx_left_in[15]:19 chanx_left_in[13] 0.0004156366 +30 chanx_left_in[15]:18 chanx_left_in[13]:11 0.0004156366 +31 chanx_left_in[15]:11 chanx_right_in[5]:19 1.308295e-05 +32 chanx_left_in[15]:12 chanx_right_in[5]:20 1.308295e-05 +33 chanx_left_in[15]:19 chanx_right_in[5]:14 0.0003349706 +34 chanx_left_in[15]:18 chanx_right_in[5]:15 0.0003349706 +35 chanx_left_in[15]:13 chanx_right_in[14] 5.634257e-06 +36 chanx_left_in[15]:14 chanx_right_in[14]:20 5.634257e-06 +37 chanx_left_in[15]:17 chanx_right_in[14] 0.0007021212 +38 chanx_left_in[15]:19 chanx_right_in[14]:20 0.0008013808 +39 chanx_left_in[15]:18 chanx_right_in[14] 0.0008013808 +40 chanx_left_in[15]:18 chanx_right_in[14]:20 0.0007021212 +41 chanx_left_in[15]:13 chanx_right_in[18]:29 5.703497e-06 +42 chanx_left_in[15]:14 chanx_right_in[18]:28 5.703497e-06 +43 chanx_left_in[15]:17 chanx_right_in[18]:29 0.0001891331 +44 chanx_left_in[15]:19 chanx_right_in[18]:28 0.0003519382 +45 chanx_left_in[15]:18 chanx_right_in[18]:28 0.0001891331 +46 chanx_left_in[15]:18 chanx_right_in[18]:29 0.0003519382 +47 chanx_left_in[15]:4 ropt_net_217:2 0.0001328598 +48 chanx_left_in[15]:3 ropt_net_217:3 0.0001328598 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:20 0.0019693 +1 chanx_left_in[15]:2 ropt_mt_inst_783:A 0.152 +2 chanx_left_in[15]:4 chanx_left_in[15]:3 0.006941965 +3 chanx_left_in[15]:5 chanx_left_in[15]:4 0.0045 +4 chanx_left_in[15]:7 chanx_left_in[15]:6 0.0045 +5 chanx_left_in[15]:6 chanx_left_in[15]:5 0.004169643 +6 chanx_left_in[15]:10 chanx_left_in[15]:9 0.001191964 +7 chanx_left_in[15]:11 chanx_left_in[15]:10 0.0045 +8 chanx_left_in[15]:13 chanx_left_in[15]:12 0.0045 +9 chanx_left_in[15]:12 chanx_left_in[15]:11 0.01965179 +10 chanx_left_in[15]:14 chanx_left_in[15]:13 0.01347321 +11 chanx_left_in[15]:15 chanx_left_in[15]:14 0.0045 +12 chanx_left_in[15]:16 chanx_left_in[15]:15 0.0001634615 +13 chanx_left_in[15]:17 chanx_left_in[15]:16 0.00341 +14 chanx_left_in[15]:9 chanx_left_in[15]:8 0.0003035715 +15 chanx_left_in[15]:8 chanx_left_in[15]:7 0.007763393 +16 chanx_left_in[15]:3 chanx_left_in[15]:2 0.0003035715 +17 chanx_left_in[15]:20 chanx_left_in[15]:19 0.0001065333 +18 chanx_left_in[15]:19 chanx_left_in[15]:18 0.007809832 +19 chanx_left_in[15]:18 chanx_left_in[15]:17 0.001917992 + +*END + +*D_NET chanx_left_in[16] 0.01089088 //LENGTH 95.460 LUMPCC 0.002194746 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 67.450 28.220 +*I BUFT_P_143:A I *L 0.001776 *C 86.940 28.560 +*N chanx_left_in[16]:3 *C 86.940 28.560 +*N chanx_left_in[16]:4 *C 86.940 28.220 +*N chanx_left_in[16]:5 *C 67.487 28.220 +*N chanx_left_in[16]:6 *C 67.160 28.220 +*N chanx_left_in[16]:7 *C 67.160 28.265 +*N chanx_left_in[16]:8 *C 67.160 36.663 +*N chanx_left_in[16]:9 *C 67.153 36.720 +*N chanx_left_in[16]:10 *C 51.230 36.720 + +*CAP +0 chanx_left_in[16] 0.001967824 +1 mux_bottom_ipin_0\/mux_l2_in_2_:A0 1e-06 +2 BUFT_P_143:A 1e-06 +3 chanx_left_in[16]:3 5.686838e-05 +4 chanx_left_in[16]:4 0.00111071 +5 chanx_left_in[16]:5 0.001102054 +6 chanx_left_in[16]:6 5.199009e-05 +7 chanx_left_in[16]:7 0.0005497248 +8 chanx_left_in[16]:8 0.0005497248 +9 chanx_left_in[16]:9 0.0006687051 +10 chanx_left_in[16]:10 0.002636529 +11 chanx_left_in[16] chanx_left_in[13] 0.0004559864 +12 chanx_left_in[16]:10 chanx_left_in[13]:11 0.0004559864 +13 chanx_left_in[16] chanx_right_in[1]:11 0.0002793965 +14 chanx_left_in[16]:9 chanx_right_in[1]:12 5.787588e-05 +15 chanx_left_in[16]:10 chanx_right_in[1]:11 5.787588e-05 +16 chanx_left_in[16]:10 chanx_right_in[1]:12 0.0002793965 +17 chanx_left_in[16] chanx_right_in[18]:28 0.0001308236 +18 chanx_left_in[16]:9 chanx_right_in[18]:29 0.0001732905 +19 chanx_left_in[16]:10 chanx_right_in[18]:28 0.0001732905 +20 chanx_left_in[16]:10 chanx_right_in[18]:29 0.0001308236 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:10 0.007833333 +1 chanx_left_in[16]:3 BUFT_P_143:A 0.152 +2 chanx_left_in[16]:5 mux_bottom_ipin_0\/mux_l2_in_2_:A0 0.152 +3 chanx_left_in[16]:5 chanx_left_in[16]:4 0.0173683 +4 chanx_left_in[16]:6 chanx_left_in[16]:5 0.00015625 +5 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0045 +6 chanx_left_in[16]:8 chanx_left_in[16]:7 0.007497768 +7 chanx_left_in[16]:9 chanx_left_in[16]:8 0.00341 +8 chanx_left_in[16]:4 chanx_left_in[16]:3 0.0003035715 +9 chanx_left_in[16]:10 chanx_left_in[16]:9 0.002494525 + +*END + +*D_NET chanx_left_in[17] 0.01515606 //LENGTH 124.160 LUMPCC 0.005732895 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 61.200 +*I BUFT_P_144:A I *L 0.001776 *C 91.540 28.560 +*N chanx_left_in[17]:2 *C 91.540 28.560 +*N chanx_left_in[17]:3 *C 91.540 28.605 +*N chanx_left_in[17]:4 *C 91.540 29.183 +*N chanx_left_in[17]:5 *C 91.532 29.240 +*N chanx_left_in[17]:6 *C 62.715 29.240 +*N chanx_left_in[17]:7 *C 12.888 29.240 +*N chanx_left_in[17]:8 *C 12.880 29.298 +*N chanx_left_in[17]:9 *C 12.880 61.143 +*N chanx_left_in[17]:10 *C 12.873 61.200 + +*CAP +0 chanx_left_in[17] 0.0004473215 +1 BUFT_P_144:A 1e-06 +2 chanx_left_in[17]:2 3.664948e-05 +3 chanx_left_in[17]:3 3.414786e-05 +4 chanx_left_in[17]:4 3.414786e-05 +5 chanx_left_in[17]:5 0.0008210884 +6 chanx_left_in[17]:6 0.002580686 +7 chanx_left_in[17]:7 0.001759596 +8 chanx_left_in[17]:8 0.001630602 +9 chanx_left_in[17]:9 0.001630602 +10 chanx_left_in[17]:10 0.0004473215 +11 chanx_left_in[17]:5 chanx_left_in[10]:12 3.612313e-05 +12 chanx_left_in[17]:5 chanx_left_in[10]:13 7.231431e-06 +13 chanx_left_in[17]:7 chanx_left_in[10] 4.846344e-06 +14 chanx_left_in[17]:7 chanx_left_in[10]:14 0.0003316326 +15 chanx_left_in[17]:6 chanx_left_in[10]:13 0.0003677557 +16 chanx_left_in[17]:6 chanx_left_in[10]:14 7.231431e-06 +17 chanx_left_in[17]:6 chanx_left_in[10]:15 4.846344e-06 +18 chanx_left_in[17]:5 chanx_left_in[14]:6 0.0001270016 +19 chanx_left_in[17]:5 chanx_left_in[14]:7 0.0005423567 +20 chanx_left_in[17]:7 chanx_left_in[14]:8 0.0006241128 +21 chanx_left_in[17]:6 chanx_left_in[14]:7 0.0007511143 +22 chanx_left_in[17]:6 chanx_left_in[14]:8 0.0005423567 +23 chanx_left_in[17] chanx_left_in[18] 0.0002977766 +24 chanx_left_in[17]:10 chanx_left_in[18]:16 0.0002977766 +25 chanx_left_in[17]:5 chanx_right_in[16] 6.033061e-06 +26 chanx_left_in[17]:5 chanx_right_in[16]:22 0.0004594341 +27 chanx_left_in[17]:6 chanx_right_in[16]:21 0.0004594341 +28 chanx_left_in[17]:6 chanx_right_in[16]:23 6.033061e-06 +29 chanx_left_in[17]:7 prog_clk[0]:24 0.0003604833 +30 chanx_left_in[17]:6 prog_clk[0]:23 0.0003604833 +31 chanx_left_in[17]:3 ropt_net_184:8 2.501133e-05 +32 chanx_left_in[17]:4 ropt_net_184:9 2.501133e-05 +33 chanx_left_in[17]:5 ropt_net_184:6 4.440486e-05 +34 chanx_left_in[17]:6 ropt_net_184:7 4.440486e-05 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:10 0.001823992 +1 chanx_left_in[17]:2 BUFT_P_144:A 0.152 +2 chanx_left_in[17]:3 chanx_left_in[17]:2 0.0045 +3 chanx_left_in[17]:4 chanx_left_in[17]:3 0.0005156249 +4 chanx_left_in[17]:5 chanx_left_in[17]:4 0.00341 +5 chanx_left_in[17]:8 chanx_left_in[17]:7 0.00341 +6 chanx_left_in[17]:7 chanx_left_in[17]:6 0.007806308 +7 chanx_left_in[17]:9 chanx_left_in[17]:8 0.02843304 +8 chanx_left_in[17]:10 chanx_left_in[17]:9 0.00341 +9 chanx_left_in[17]:6 chanx_left_in[17]:5 0.004514742 + +*END + +*D_NET chanx_left_in[18] 0.01820246 //LENGTH 153.565 LUMPCC 0.004881831 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 62.560 +*I ropt_mt_inst_767:A I *L 0.001767 *C 93.380 12.240 +*N chanx_left_in[18]:2 *C 93.418 12.240 +*N chanx_left_in[18]:3 *C 96.555 12.240 +*N chanx_left_in[18]:4 *C 96.600 12.285 +*N chanx_left_in[18]:5 *C 96.600 14.915 +*N chanx_left_in[18]:6 *C 96.555 14.960 +*N chanx_left_in[18]:7 *C 94.760 14.960 +*N chanx_left_in[18]:8 *C 94.760 15.300 +*N chanx_left_in[18]:9 *C 88.320 15.300 +*N chanx_left_in[18]:10 *C 88.320 14.960 +*N chanx_left_in[18]:11 *C 46.045 14.960 +*N chanx_left_in[18]:12 *C 46.000 15.005 +*N chanx_left_in[18]:13 *C 46.000 63.183 +*N chanx_left_in[18]:14 *C 45.992 63.240 +*N chanx_left_in[18]:15 *C 14.720 63.240 +*N chanx_left_in[18]:16 *C 14.720 62.560 + +*CAP +0 chanx_left_in[18] 0.000364285 +1 ropt_mt_inst_767:A 1e-06 +2 chanx_left_in[18]:2 0.0001418142 +3 chanx_left_in[18]:3 0.0001418142 +4 chanx_left_in[18]:4 0.0001580164 +5 chanx_left_in[18]:5 0.0001580164 +6 chanx_left_in[18]:6 0.0001094403 +7 chanx_left_in[18]:7 0.0001323534 +8 chanx_left_in[18]:8 0.0004474539 +9 chanx_left_in[18]:9 0.0004474695 +10 chanx_left_in[18]:10 0.002116551 +11 chanx_left_in[18]:11 0.002093622 +12 chanx_left_in[18]:12 0.00238848 +13 chanx_left_in[18]:13 0.00238848 +14 chanx_left_in[18]:14 0.0008785975 +15 chanx_left_in[18]:15 0.0009337725 +16 chanx_left_in[18]:16 0.0004194601 +17 chanx_left_in[18] chanx_left_in[14] 0.0003160884 +18 chanx_left_in[18]:14 chanx_left_in[14]:11 0.001253014 +19 chanx_left_in[18]:16 chanx_left_in[14]:11 0.0003160884 +20 chanx_left_in[18]:15 chanx_left_in[14] 0.001253014 +21 chanx_left_in[18] chanx_left_in[17] 0.0002977766 +22 chanx_left_in[18]:16 chanx_left_in[17]:10 0.0002977766 +23 chanx_left_in[18]:14 chanx_right_in[19]:15 0.0004754361 +24 chanx_left_in[18]:15 chanx_right_in[19]:14 0.0004754361 +25 chanx_left_in[18]:2 ropt_net_226:5 9.860038e-05 +26 chanx_left_in[18]:3 ropt_net_226:4 9.860038e-05 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:16 0.002113433 +1 chanx_left_in[18]:2 ropt_mt_inst_767:A 0.152 +2 chanx_left_in[18]:3 chanx_left_in[18]:2 0.002801339 +3 chanx_left_in[18]:4 chanx_left_in[18]:3 0.0045 +4 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0045 +5 chanx_left_in[18]:5 chanx_left_in[18]:4 0.002348214 +6 chanx_left_in[18]:11 chanx_left_in[18]:10 0.03774554 +7 chanx_left_in[18]:12 chanx_left_in[18]:11 0.0045 +8 chanx_left_in[18]:13 chanx_left_in[18]:12 0.04301563 +9 chanx_left_in[18]:14 chanx_left_in[18]:13 0.00341 +10 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0003035715 +11 chanx_left_in[18]:9 chanx_left_in[18]:8 0.00575 +12 chanx_left_in[18]:8 chanx_left_in[18]:7 0.0003035715 +13 chanx_left_in[18]:7 chanx_left_in[18]:6 0.001602679 +14 chanx_left_in[18]:16 chanx_left_in[18]:15 0.0001065333 +15 chanx_left_in[18]:15 chanx_left_in[18]:14 0.004899358 + +*END + +*D_NET chanx_left_in[19] 0.01598576 //LENGTH 134.785 LUMPCC 0.001937917 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.298 19.040 +*I ropt_mt_inst_784:A I *L 0.001767 *C 97.825 55.760 +*N chanx_left_in[19]:2 *C 97.788 55.760 +*N chanx_left_in[19]:3 *C 92.965 55.760 +*N chanx_left_in[19]:4 *C 92.920 55.715 +*N chanx_left_in[19]:5 *C 92.920 21.125 +*N chanx_left_in[19]:6 *C 92.875 21.080 +*N chanx_left_in[19]:7 *C 51.220 21.080 +*N chanx_left_in[19]:8 *C 1.425 21.080 +*N chanx_left_in[19]:9 *C 1.380 21.035 +*N chanx_left_in[19]:10 *C 1.380 19.098 +*N chanx_left_in[19]:11 *C 1.380 19.040 + +*CAP +0 chanx_left_in[19] 3.926969e-05 +1 ropt_mt_inst_784:A 1e-06 +2 chanx_left_in[19]:2 0.000283164 +3 chanx_left_in[19]:3 0.000283164 +4 chanx_left_in[19]:4 0.001468373 +5 chanx_left_in[19]:5 0.001468373 +6 chanx_left_in[19]:6 0.002371755 +7 chanx_left_in[19]:7 0.005109584 +8 chanx_left_in[19]:8 0.002737829 +9 chanx_left_in[19]:9 0.0001230269 +10 chanx_left_in[19]:10 0.0001230269 +11 chanx_left_in[19]:11 3.926969e-05 +12 chanx_left_in[19]:4 chanx_left_in[0]:6 0.0003119061 +13 chanx_left_in[19]:5 chanx_left_in[0]:5 0.0003119061 +14 chanx_left_in[19]:6 chanx_left_in[10]:7 0.0002668239 +15 chanx_left_in[19]:6 chanx_left_in[10]:9 1.378253e-05 +16 chanx_left_in[19]:7 chanx_left_in[10]:8 1.378253e-05 +17 chanx_left_in[19]:7 chanx_left_in[10]:9 0.0002668239 +18 chanx_left_in[19]:8 chanx_right_in[15]:5 0.0003141089 +19 chanx_left_in[19]:7 chanx_right_in[15]:6 0.0003141089 +20 chanx_left_in[19]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.233707e-05 +21 chanx_left_in[19]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.233707e-05 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:11 2.35e-05 +1 chanx_left_in[19]:2 ropt_mt_inst_784:A 0.152 +2 chanx_left_in[19]:3 chanx_left_in[19]:2 0.004305804 +3 chanx_left_in[19]:4 chanx_left_in[19]:3 0.0045 +4 chanx_left_in[19]:6 chanx_left_in[19]:5 0.0045 +5 chanx_left_in[19]:5 chanx_left_in[19]:4 0.03088393 +6 chanx_left_in[19]:8 chanx_left_in[19]:7 0.04445983 +7 chanx_left_in[19]:9 chanx_left_in[19]:8 0.0045 +8 chanx_left_in[19]:10 chanx_left_in[19]:9 0.001729911 +9 chanx_left_in[19]:11 chanx_left_in[19]:10 0.00341 +10 chanx_left_in[19]:7 chanx_left_in[19]:6 0.03719197 + +*END + +*D_NET chanx_right_in[0] 0.009771336 //LENGTH 84.305 LUMPCC 0 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 103.650 53.040 +*I BUFT_RR_62:A I *L 0.001776 *C 27.600 58.480 +*I mux_bottom_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.550 55.420 +*N chanx_right_in[0]:3 *C 83.523 55.443 +*N chanx_right_in[0]:4 *C 83.260 55.455 +*N chanx_right_in[0]:5 *C 27.600 58.480 +*N chanx_right_in[0]:6 *C 27.600 58.435 +*N chanx_right_in[0]:7 *C 27.600 56.485 +*N chanx_right_in[0]:8 *C 27.645 56.440 +*N chanx_right_in[0]:9 *C 77.440 56.440 +*N chanx_right_in[0]:10 *C 83.260 56.440 +*N chanx_right_in[0]:11 *C 93.795 56.440 +*N chanx_right_in[0]:12 *C 93.840 56.395 +*N chanx_right_in[0]:13 *C 93.840 53.098 +*N chanx_right_in[0]:14 *C 93.848 53.040 + +*CAP +0 chanx_right_in[0] 0.0005476287 +1 BUFT_RR_62:A 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[0]:3 3.211492e-05 +4 chanx_right_in[0]:4 8.980147e-05 +5 chanx_right_in[0]:5 2.714536e-05 +6 chanx_right_in[0]:6 0.0001187327 +7 chanx_right_in[0]:7 0.0001187327 +8 chanx_right_in[0]:8 0.002913275 +9 chanx_right_in[0]:9 0.003265355 +10 chanx_right_in[0]:10 0.001066255 +11 chanx_right_in[0]:11 0.0006564879 +12 chanx_right_in[0]:12 0.0001930894 +13 chanx_right_in[0]:13 0.0001930894 +14 chanx_right_in[0]:14 0.0005476287 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:14 0.001535725 +1 chanx_right_in[0]:8 chanx_right_in[0]:7 0.0045 +2 chanx_right_in[0]:7 chanx_right_in[0]:6 0.001741071 +3 chanx_right_in[0]:5 BUFT_RR_62:A 0.152 +4 chanx_right_in[0]:6 chanx_right_in[0]:5 0.0045 +5 chanx_right_in[0]:11 chanx_right_in[0]:10 0.00940625 +6 chanx_right_in[0]:12 chanx_right_in[0]:11 0.0045 +7 chanx_right_in[0]:13 chanx_right_in[0]:12 0.002944197 +8 chanx_right_in[0]:14 chanx_right_in[0]:13 0.00341 +9 chanx_right_in[0]:3 mux_bottom_ipin_0\/mux_l1_in_0_:A0 0.152 +10 chanx_right_in[0]:10 chanx_right_in[0]:9 0.005196429 +11 chanx_right_in[0]:10 chanx_right_in[0]:4 0.0008794643 +12 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0001773649 +13 chanx_right_in[0]:9 chanx_right_in[0]:8 0.04445982 + +*END + +*D_NET chanx_right_in[1] 0.0166512 //LENGTH 141.270 LUMPCC 0.00596644 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 103.650 66.640 +*I ropt_mt_inst_777:A I *L 0.001767 *C 3.220 28.560 +*N chanx_right_in[1]:2 *C 3.243 28.588 +*N chanx_right_in[1]:3 *C 3.255 28.900 +*N chanx_right_in[1]:4 *C 3.635 28.900 +*N chanx_right_in[1]:5 *C 3.680 28.945 +*N chanx_right_in[1]:6 *C 3.680 33.615 +*N chanx_right_in[1]:7 *C 3.725 33.660 +*N chanx_right_in[1]:8 *C 26.680 33.660 +*N chanx_right_in[1]:9 *C 26.680 34.000 +*N chanx_right_in[1]:10 *C 26.680 34.000 +*N chanx_right_in[1]:11 *C 26.688 34.000 +*N chanx_right_in[1]:12 *C 55.653 34.000 +*N chanx_right_in[1]:13 *C 55.660 34.058 +*N chanx_right_in[1]:14 *C 55.660 64.543 +*N chanx_right_in[1]:15 *C 55.668 64.600 +*N chanx_right_in[1]:16 *C 98.892 64.600 +*N chanx_right_in[1]:17 *C 98.900 64.657 +*N chanx_right_in[1]:18 *C 98.900 66.583 +*N chanx_right_in[1]:19 *C 98.907 66.640 + +*CAP +0 chanx_right_in[1] 0.0002492735 +1 ropt_mt_inst_777:A 1e-06 +2 chanx_right_in[1]:2 3.31306e-05 +3 chanx_right_in[1]:3 7.282195e-05 +4 chanx_right_in[1]:4 3.969135e-05 +5 chanx_right_in[1]:5 0.0002380402 +6 chanx_right_in[1]:6 0.0002380402 +7 chanx_right_in[1]:7 0.0009288801 +8 chanx_right_in[1]:8 0.0009539886 +9 chanx_right_in[1]:9 5.386578e-05 +10 chanx_right_in[1]:10 3.103059e-05 +11 chanx_right_in[1]:11 0.000925206 +12 chanx_right_in[1]:12 0.000925206 +13 chanx_right_in[1]:13 0.001458363 +14 chanx_right_in[1]:14 0.001458363 +15 chanx_right_in[1]:15 0.001300233 +16 chanx_right_in[1]:16 0.001300233 +17 chanx_right_in[1]:17 0.0001140576 +18 chanx_right_in[1]:18 0.0001140576 +19 chanx_right_in[1]:19 0.0002492735 +20 chanx_right_in[1]:15 chanx_left_in[7]:8 0.0006377213 +21 chanx_right_in[1]:17 chanx_left_in[7]:5 3.727538e-06 +22 chanx_right_in[1]:16 chanx_left_in[7]:7 0.0006377213 +23 chanx_right_in[1]:18 chanx_left_in[7]:6 3.727538e-06 +24 chanx_right_in[1]:11 chanx_left_in[16] 0.0002793965 +25 chanx_right_in[1]:11 chanx_left_in[16]:10 5.787588e-05 +26 chanx_right_in[1]:12 chanx_left_in[16]:9 5.787588e-05 +27 chanx_right_in[1]:12 chanx_left_in[16]:10 0.0002793965 +28 chanx_right_in[1] chanx_right_in[17] 2.662046e-05 +29 chanx_right_in[1]:15 chanx_right_in[17]:21 0.0005202991 +30 chanx_right_in[1]:16 chanx_right_in[17] 0.0005202991 +31 chanx_right_in[1]:19 chanx_right_in[17]:21 2.662046e-05 +32 chanx_right_in[1] chanx_right_in[19] 4.272947e-07 +33 chanx_right_in[1]:15 chanx_right_in[19]:14 9.629126e-05 +34 chanx_right_in[1]:15 chanx_right_in[19]:15 0.0002000191 +35 chanx_right_in[1]:16 chanx_right_in[19] 0.0002000191 +36 chanx_right_in[1]:16 chanx_right_in[19]:15 9.629126e-05 +37 chanx_right_in[1]:19 chanx_right_in[19]:15 4.272947e-07 +38 chanx_right_in[1]:5 prog_clk[0] 6.559725e-05 +39 chanx_right_in[1]:6 prog_clk[0]:25 6.559725e-05 +40 chanx_right_in[1]:11 prog_clk[0]:24 0.0003262241 +41 chanx_right_in[1]:11 prog_clk[0]:23 1.503629e-05 +42 chanx_right_in[1]:13 prog_clk[0]:22 3.887866e-05 +43 chanx_right_in[1]:12 prog_clk[0]:23 0.0003262241 +44 chanx_right_in[1]:12 prog_clk[0]:18 1.503629e-05 +45 chanx_right_in[1]:14 prog_clk[0]:21 3.887866e-05 +46 chanx_right_in[1]:5 ropt_net_209:4 1.6213e-05 +47 chanx_right_in[1]:7 ropt_net_209:5 0.0003132617 +48 chanx_right_in[1]:6 ropt_net_209:3 1.6213e-05 +49 chanx_right_in[1]:8 ropt_net_209:6 0.0003132617 +50 chanx_right_in[1] ropt_net_230:6 2.031838e-05 +51 chanx_right_in[1]:15 ropt_net_230:7 2.146058e-05 +52 chanx_right_in[1]:17 ropt_net_230:4 4.218045e-06 +53 chanx_right_in[1]:16 ropt_net_230:6 2.146058e-05 +54 chanx_right_in[1]:18 ropt_net_230:5 4.218045e-06 +55 chanx_right_in[1]:19 ropt_net_230:7 2.031838e-05 +56 chanx_right_in[1]:7 ropt_net_169:2 0.0003396341 +57 chanx_right_in[1]:8 ropt_net_169:3 0.0003396341 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:19 0.0007429916 +1 chanx_right_in[1]:2 ropt_mt_inst_777:A 0.152 +2 chanx_right_in[1]:4 chanx_right_in[1]:3 0.0003392857 +3 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0045 +4 chanx_right_in[1]:7 chanx_right_in[1]:6 0.0045 +5 chanx_right_in[1]:6 chanx_right_in[1]:5 0.004169643 +6 chanx_right_in[1]:9 chanx_right_in[1]:8 0.0003035715 +7 chanx_right_in[1]:10 chanx_right_in[1]:9 0.0045 +8 chanx_right_in[1]:11 chanx_right_in[1]:10 0.00341 +9 chanx_right_in[1]:13 chanx_right_in[1]:12 0.00341 +10 chanx_right_in[1]:12 chanx_right_in[1]:11 0.00453785 +11 chanx_right_in[1]:14 chanx_right_in[1]:13 0.02721875 +12 chanx_right_in[1]:15 chanx_right_in[1]:14 0.00341 +13 chanx_right_in[1]:17 chanx_right_in[1]:16 0.00341 +14 chanx_right_in[1]:16 chanx_right_in[1]:15 0.006771916 +15 chanx_right_in[1]:18 chanx_right_in[1]:17 0.00171875 +16 chanx_right_in[1]:19 chanx_right_in[1]:18 0.00341 +17 chanx_right_in[1]:3 chanx_right_in[1]:2 0.0002111487 +18 chanx_right_in[1]:8 chanx_right_in[1]:7 0.02049554 + +*END + +*D_NET chanx_right_in[2] 0.01651905 //LENGTH 152.815 LUMPCC 0 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 103.650 6.800 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 84.470 33.320 +*I BUFT_P_148:A I *L 0.001776 *C 12.880 66.640 +*N chanx_right_in[2]:3 *C 12.918 66.640 +*N chanx_right_in[2]:4 *C 21.575 66.640 +*N chanx_right_in[2]:5 *C 21.620 66.595 +*N chanx_right_in[2]:6 *C 21.620 61.540 +*N chanx_right_in[2]:7 *C 22.080 61.540 +*N chanx_right_in[2]:8 *C 22.137 61.540 +*N chanx_right_in[2]:9 *C 25.715 61.540 +*N chanx_right_in[2]:10 *C 25.760 61.495 +*N chanx_right_in[2]:11 *C 25.760 33.365 +*N chanx_right_in[2]:12 *C 25.805 33.320 +*N chanx_right_in[2]:13 *C 75.600 33.320 +*N chanx_right_in[2]:14 *C 84.433 33.320 +*N chanx_right_in[2]:15 *C 84.510 33.320 +*N chanx_right_in[2]:16 *C 84.640 33.275 +*N chanx_right_in[2]:17 *C 84.640 6.857 +*N chanx_right_in[2]:18 *C 84.648 6.800 + +*CAP +0 chanx_right_in[2] 0.001034351 +1 mux_bottom_ipin_0\/mux_l1_in_1_:A0 1e-06 +2 BUFT_P_148:A 1e-06 +3 chanx_right_in[2]:3 0.0004381179 +4 chanx_right_in[2]:4 0.0004381179 +5 chanx_right_in[2]:5 0.0002536643 +6 chanx_right_in[2]:6 0.0002838488 +7 chanx_right_in[2]:7 5.834929e-05 +8 chanx_right_in[2]:8 0.0002835836 +9 chanx_right_in[2]:9 0.0002835836 +10 chanx_right_in[2]:10 0.00138947 +11 chanx_right_in[2]:11 0.00138947 +12 chanx_right_in[2]:12 0.002958533 +13 chanx_right_in[2]:13 0.00348685 +14 chanx_right_in[2]:14 0.0005516191 +15 chanx_right_in[2]:15 2.33024e-05 +16 chanx_right_in[2]:16 0.001304919 +17 chanx_right_in[2]:17 0.001304919 +18 chanx_right_in[2]:18 0.001034351 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:18 0.002977058 +1 chanx_right_in[2]:3 BUFT_P_148:A 0.152 +2 chanx_right_in[2]:4 chanx_right_in[2]:3 0.007729911 +3 chanx_right_in[2]:5 chanx_right_in[2]:4 0.0045 +4 chanx_right_in[2]:8 chanx_right_in[2]:7 0.0045 +5 chanx_right_in[2]:7 chanx_right_in[2]:6 0.0004107143 +6 chanx_right_in[2]:9 chanx_right_in[2]:8 0.003194197 +7 chanx_right_in[2]:10 chanx_right_in[2]:9 0.0045 +8 chanx_right_in[2]:12 chanx_right_in[2]:11 0.0045 +9 chanx_right_in[2]:11 chanx_right_in[2]:10 0.02511607 +10 chanx_right_in[2]:15 chanx_right_in[2]:14 6.919643e-05 +11 chanx_right_in[2]:16 chanx_right_in[2]:15 0.0045 +12 chanx_right_in[2]:17 chanx_right_in[2]:16 0.02358706 +13 chanx_right_in[2]:18 chanx_right_in[2]:17 0.00341 +14 chanx_right_in[2]:14 mux_bottom_ipin_0\/mux_l1_in_1_:A0 0.152 +15 chanx_right_in[2]:14 chanx_right_in[2]:13 0.007886161 +16 chanx_right_in[2]:6 chanx_right_in[2]:5 0.004513393 +17 chanx_right_in[2]:13 chanx_right_in[2]:12 0.04445983 + +*END + +*D_NET chanx_right_in[3] 0.01647696 //LENGTH 149.765 LUMPCC 0.0007392965 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 103.650 21.760 +*I ropt_mt_inst_782:A I *L 0.001767 *C 7.820 69.360 +*N chanx_right_in[3]:2 *C 7.820 69.360 +*N chanx_right_in[3]:3 *C 7.405 69.360 +*N chanx_right_in[3]:4 *C 7.360 69.315 +*N chanx_right_in[3]:5 *C 7.360 61.585 +*N chanx_right_in[3]:6 *C 7.405 61.540 +*N chanx_right_in[3]:7 *C 11.960 61.540 +*N chanx_right_in[3]:8 *C 11.885 61.880 +*N chanx_right_in[3]:9 *C 11.953 61.835 +*N chanx_right_in[3]:10 *C 11.960 61.245 +*N chanx_right_in[3]:11 *C 12.005 61.200 +*N chanx_right_in[3]:12 *C 21.620 61.200 +*N chanx_right_in[3]:13 *C 21.620 61.880 +*N chanx_right_in[3]:14 *C 33.120 61.880 +*N chanx_right_in[3]:15 *C 33.120 61.200 +*N chanx_right_in[3]:16 *C 52.855 61.200 +*N chanx_right_in[3]:17 *C 52.900 61.155 +*N chanx_right_in[3]:18 *C 52.900 23.845 +*N chanx_right_in[3]:19 *C 52.945 23.800 +*N chanx_right_in[3]:20 *C 90.575 23.800 +*N chanx_right_in[3]:21 *C 90.620 23.755 +*N chanx_right_in[3]:22 *C 90.620 21.818 +*N chanx_right_in[3]:23 *C 90.627 21.760 + +*CAP +0 chanx_right_in[3] 0.0005480651 +1 ropt_mt_inst_782:A 1e-06 +2 chanx_right_in[3]:2 7.075206e-05 +3 chanx_right_in[3]:3 4.057e-05 +4 chanx_right_in[3]:4 0.0004452241 +5 chanx_right_in[3]:5 0.0004452241 +6 chanx_right_in[3]:6 0.00028604 +7 chanx_right_in[3]:7 0.0003128624 +8 chanx_right_in[3]:8 5.806395e-05 +9 chanx_right_in[3]:9 6.334679e-05 +10 chanx_right_in[3]:10 6.334679e-05 +11 chanx_right_in[3]:11 0.0005136488 +12 chanx_right_in[3]:12 0.0005529764 +13 chanx_right_in[3]:13 0.0008147929 +14 chanx_right_in[3]:14 0.0008127097 +15 chanx_right_in[3]:15 0.001034878 +16 chanx_right_in[3]:16 0.0009976341 +17 chanx_right_in[3]:17 0.00180857 +18 chanx_right_in[3]:18 0.00180857 +19 chanx_right_in[3]:19 0.00214406 +20 chanx_right_in[3]:20 0.00214406 +21 chanx_right_in[3]:21 0.0001116036 +22 chanx_right_in[3]:22 0.0001116036 +23 chanx_right_in[3]:23 0.0005480651 +24 chanx_right_in[3] chanx_right_in[7] 0.0002534422 +25 chanx_right_in[3]:23 chanx_right_in[7]:10 0.0002534422 +26 chanx_right_in[3]:19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001162061 +27 chanx_right_in[3]:20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001162061 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:23 0.002040192 +1 chanx_right_in[3]:2 ropt_mt_inst_782:A 0.152 +2 chanx_right_in[3]:3 chanx_right_in[3]:2 0.0003705358 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0045 +4 chanx_right_in[3]:6 chanx_right_in[3]:5 0.0045 +5 chanx_right_in[3]:5 chanx_right_in[3]:4 0.006901786 +6 chanx_right_in[3]:8 chanx_right_in[3]:7 0.0003035715 +7 chanx_right_in[3]:9 chanx_right_in[3]:8 0.0045 +8 chanx_right_in[3]:11 chanx_right_in[3]:10 0.0045 +9 chanx_right_in[3]:10 chanx_right_in[3]:9 0.0005267857 +10 chanx_right_in[3]:16 chanx_right_in[3]:15 0.01762054 +11 chanx_right_in[3]:17 chanx_right_in[3]:16 0.0045 +12 chanx_right_in[3]:19 chanx_right_in[3]:18 0.0045 +13 chanx_right_in[3]:18 chanx_right_in[3]:17 0.0333125 +14 chanx_right_in[3]:20 chanx_right_in[3]:19 0.03359822 +15 chanx_right_in[3]:21 chanx_right_in[3]:20 0.0045 +16 chanx_right_in[3]:22 chanx_right_in[3]:21 0.001729911 +17 chanx_right_in[3]:23 chanx_right_in[3]:22 0.00341 +18 chanx_right_in[3]:7 chanx_right_in[3]:6 0.004066965 +19 chanx_right_in[3]:12 chanx_right_in[3]:11 0.008584822 +20 chanx_right_in[3]:13 chanx_right_in[3]:12 0.000607143 +21 chanx_right_in[3]:14 chanx_right_in[3]:13 0.01026786 +22 chanx_right_in[3]:15 chanx_right_in[3]:14 0.0006071429 + +*END + +*D_NET chanx_right_in[4] 0.01218128 //LENGTH 106.550 LUMPCC 0.000968711 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 103.650 31.280 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 82.170 26.180 +*I BUFT_P_150:A I *L 0.001776 *C 11.040 20.400 +*N chanx_right_in[4]:3 *C 11.078 20.400 +*N chanx_right_in[4]:4 *C 12.835 20.400 +*N chanx_right_in[4]:5 *C 12.880 20.445 +*N chanx_right_in[4]:6 *C 12.880 22.395 +*N chanx_right_in[4]:7 *C 12.925 22.440 +*N chanx_right_in[4]:8 *C 32.820 22.440 +*N chanx_right_in[4]:9 *C 32.865 22.440 +*N chanx_right_in[4]:10 *C 33.120 22.508 +*N chanx_right_in[4]:11 *C 33.120 23.075 +*N chanx_right_in[4]:12 *C 33.120 23.120 +*N chanx_right_in[4]:13 *C 34.960 23.120 +*N chanx_right_in[4]:14 *C 34.960 23.165 +*N chanx_right_in[4]:15 *C 34.960 26.135 +*N chanx_right_in[4]:16 *C 35.005 26.180 +*N chanx_right_in[4]:17 *C 82.170 26.180 +*N chanx_right_in[4]:18 *C 87.815 26.180 +*N chanx_right_in[4]:19 *C 87.860 26.225 +*N chanx_right_in[4]:20 *C 87.860 31.223 +*N chanx_right_in[4]:21 *C 87.868 31.280 + +*CAP +0 chanx_right_in[4] 0.0007172937 +1 mux_bottom_ipin_0\/mux_l1_in_2_:A0 1e-06 +2 BUFT_P_150:A 1e-06 +3 chanx_right_in[4]:3 0.0001238191 +4 chanx_right_in[4]:4 0.0001238191 +5 chanx_right_in[4]:5 0.0001459019 +6 chanx_right_in[4]:6 0.0001459019 +7 chanx_right_in[4]:7 0.00120584 +8 chanx_right_in[4]:8 0.00120584 +9 chanx_right_in[4]:9 4.673567e-05 +10 chanx_right_in[4]:10 6.085306e-05 +11 chanx_right_in[4]:11 3.986579e-05 +12 chanx_right_in[4]:12 0.000145079 +13 chanx_right_in[4]:13 0.0001475974 +14 chanx_right_in[4]:14 0.0001441988 +15 chanx_right_in[4]:15 0.0001441988 +16 chanx_right_in[4]:16 0.002441457 +17 chanx_right_in[4]:17 0.002779526 +18 chanx_right_in[4]:18 0.0003105762 +19 chanx_right_in[4]:19 0.0002823848 +20 chanx_right_in[4]:20 0.0002823848 +21 chanx_right_in[4]:21 0.0007172937 +22 chanx_right_in[4] chanx_left_in[14]:6 0.0004843555 +23 chanx_right_in[4]:21 chanx_left_in[14]:7 0.0004843555 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:21 0.002472592 +1 chanx_right_in[4]:18 chanx_right_in[4]:17 0.005040179 +2 chanx_right_in[4]:19 chanx_right_in[4]:18 0.0045 +3 chanx_right_in[4]:20 chanx_right_in[4]:19 0.004462054 +4 chanx_right_in[4]:21 chanx_right_in[4]:20 0.00341 +5 chanx_right_in[4]:16 chanx_right_in[4]:15 0.0045 +6 chanx_right_in[4]:15 chanx_right_in[4]:14 0.002651786 +7 chanx_right_in[4]:13 chanx_right_in[4]:12 0.001642857 +8 chanx_right_in[4]:14 chanx_right_in[4]:13 0.0045 +9 chanx_right_in[4]:12 chanx_right_in[4]:11 0.0045 +10 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0005066964 +11 chanx_right_in[4]:8 chanx_right_in[4]:7 0.01776339 +12 chanx_right_in[4]:9 chanx_right_in[4]:8 0.0045 +13 chanx_right_in[4]:7 chanx_right_in[4]:6 0.0045 +14 chanx_right_in[4]:6 chanx_right_in[4]:5 0.001741072 +15 chanx_right_in[4]:4 chanx_right_in[4]:3 0.001569197 +16 chanx_right_in[4]:5 chanx_right_in[4]:4 0.0045 +17 chanx_right_in[4]:3 BUFT_P_150:A 0.152 +18 chanx_right_in[4]:17 mux_bottom_ipin_0\/mux_l1_in_2_:A0 0.152 +19 chanx_right_in[4]:17 chanx_right_in[4]:16 0.04211161 +20 chanx_right_in[4]:10 chanx_right_in[4]:9 0.000138587 + +*END + +*D_NET chanx_right_in[5] 0.01342626 //LENGTH 114.450 LUMPCC 0.003834979 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 103.575 43.520 +*I ropt_mt_inst_776:A I *L 0.001767 *C 3.220 42.160 +*N chanx_right_in[5]:2 *C 3.258 42.160 +*N chanx_right_in[5]:3 *C 5.015 42.160 +*N chanx_right_in[5]:4 *C 5.060 42.115 +*N chanx_right_in[5]:5 *C 5.060 39.145 +*N chanx_right_in[5]:6 *C 5.105 39.100 +*N chanx_right_in[5]:7 *C 18.355 39.100 +*N chanx_right_in[5]:8 *C 18.400 39.145 +*N chanx_right_in[5]:9 *C 18.400 42.115 +*N chanx_right_in[5]:10 *C 18.445 42.160 +*N chanx_right_in[5]:11 *C 21.115 42.160 +*N chanx_right_in[5]:12 *C 21.160 42.205 +*N chanx_right_in[5]:13 *C 21.160 44.143 +*N chanx_right_in[5]:14 *C 21.168 44.200 +*N chanx_right_in[5]:15 *C 61.180 44.200 +*N chanx_right_in[5]:16 *C 61.180 44.880 +*N chanx_right_in[5]:17 *C 67.160 44.880 +*N chanx_right_in[5]:18 *C 67.160 44.200 +*N chanx_right_in[5]:19 *C 90.160 44.200 +*N chanx_right_in[5]:20 *C 90.160 43.520 + +*CAP +0 chanx_right_in[5] 0.0005760896 +1 ropt_mt_inst_776:A 1e-06 +2 chanx_right_in[5]:2 9.817813e-05 +3 chanx_right_in[5]:3 9.817813e-05 +4 chanx_right_in[5]:4 0.0001675212 +5 chanx_right_in[5]:5 0.0001675212 +6 chanx_right_in[5]:6 0.0007465975 +7 chanx_right_in[5]:7 0.0007465975 +8 chanx_right_in[5]:8 0.0001563452 +9 chanx_right_in[5]:9 0.0001563452 +10 chanx_right_in[5]:10 0.0002202451 +11 chanx_right_in[5]:11 0.0002202451 +12 chanx_right_in[5]:12 0.0001212221 +13 chanx_right_in[5]:13 0.0001212221 +14 chanx_right_in[5]:14 0.00126753 +15 chanx_right_in[5]:15 0.00132067 +16 chanx_right_in[5]:16 0.0004583986 +17 chanx_right_in[5]:17 0.0004537556 +18 chanx_right_in[5]:18 0.0009597601 +19 chanx_right_in[5]:19 0.0009345167 +20 chanx_right_in[5]:20 0.0005993435 +21 chanx_right_in[5]:14 chanx_left_in[0]:17 0.0001725555 +22 chanx_right_in[5]:14 chanx_left_in[0]:19 0.0003384625 +23 chanx_right_in[5]:14 chanx_left_in[0]:21 2.477718e-05 +24 chanx_right_in[5]:15 chanx_left_in[0]:16 0.0001725555 +25 chanx_right_in[5]:15 chanx_left_in[0]:18 0.0003384625 +26 chanx_right_in[5]:15 chanx_left_in[0]:20 2.477718e-05 +27 chanx_right_in[5]:16 chanx_left_in[0]:17 5.365254e-05 +28 chanx_right_in[5]:17 chanx_left_in[0]:16 5.365254e-05 +29 chanx_right_in[5]:18 chanx_left_in[0]:17 8.587097e-05 +30 chanx_right_in[5]:19 chanx_left_in[0]:6 1.490829e-05 +31 chanx_right_in[5]:19 chanx_left_in[0]:16 8.587097e-05 +32 chanx_right_in[5]:20 chanx_left_in[0]:5 1.490829e-05 +33 chanx_right_in[5]:14 chanx_left_in[15]:19 0.0003349706 +34 chanx_right_in[5]:15 chanx_left_in[15]:18 0.0003349706 +35 chanx_right_in[5]:19 chanx_left_in[15]:11 1.308295e-05 +36 chanx_right_in[5]:20 chanx_left_in[15]:12 1.308295e-05 +37 chanx_right_in[5] chanx_right_in[14] 0.000243884 +38 chanx_right_in[5]:14 chanx_right_in[14]:20 0.0001825824 +39 chanx_right_in[5]:15 chanx_right_in[14] 0.0001825824 +40 chanx_right_in[5]:16 chanx_right_in[14]:20 5.357856e-05 +41 chanx_right_in[5]:17 chanx_right_in[14] 5.357856e-05 +42 chanx_right_in[5]:18 chanx_right_in[14]:20 0.0003478693 +43 chanx_right_in[5]:19 chanx_right_in[14] 0.0003478693 +44 chanx_right_in[5]:20 chanx_right_in[14]:20 0.000243884 +45 chanx_right_in[5]:2 ropt_net_215:7 4.622387e-05 +46 chanx_right_in[5]:3 ropt_net_215:6 4.622387e-05 +47 chanx_right_in[5]:4 ropt_net_215:5 5.070724e-06 +48 chanx_right_in[5]:5 ropt_net_215:4 5.070724e-06 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:20 0.002101683 +1 chanx_right_in[5]:2 ropt_mt_inst_776:A 0.152 +2 chanx_right_in[5]:3 chanx_right_in[5]:2 0.001569196 +3 chanx_right_in[5]:4 chanx_right_in[5]:3 0.0045 +4 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +5 chanx_right_in[5]:5 chanx_right_in[5]:4 0.002651786 +6 chanx_right_in[5]:7 chanx_right_in[5]:6 0.01183036 +7 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0045 +8 chanx_right_in[5]:10 chanx_right_in[5]:9 0.0045 +9 chanx_right_in[5]:9 chanx_right_in[5]:8 0.002651786 +10 chanx_right_in[5]:11 chanx_right_in[5]:10 0.002383929 +11 chanx_right_in[5]:12 chanx_right_in[5]:11 0.0045 +12 chanx_right_in[5]:13 chanx_right_in[5]:12 0.001729911 +13 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00341 +14 chanx_right_in[5]:15 chanx_right_in[5]:14 0.006268625 +15 chanx_right_in[5]:16 chanx_right_in[5]:15 0.0001065333 +16 chanx_right_in[5]:17 chanx_right_in[5]:16 0.0009368667 +17 chanx_right_in[5]:18 chanx_right_in[5]:17 0.0001065333 +18 chanx_right_in[5]:19 chanx_right_in[5]:18 0.003603333 +19 chanx_right_in[5]:20 chanx_right_in[5]:19 0.0001065333 + +*END + +*D_NET chanx_right_in[8] 0.009956088 //LENGTH 91.545 LUMPCC 0.003387147 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 103.650 58.480 +*I BUFT_P_153:A I *L 0.001776 *C 15.640 55.760 +*N chanx_right_in[8]:2 *C 15.678 55.760 +*N chanx_right_in[8]:3 *C 30.315 55.760 +*N chanx_right_in[8]:4 *C 30.360 55.805 +*N chanx_right_in[8]:5 *C 30.360 58.422 +*N chanx_right_in[8]:6 *C 30.367 58.480 +*N chanx_right_in[8]:7 *C 80.195 58.480 + +*CAP +0 chanx_right_in[8] 0.0007890483 +1 BUFT_P_153:A 1e-06 +2 chanx_right_in[8]:2 0.0007682107 +3 chanx_right_in[8]:3 0.0007682107 +4 chanx_right_in[8]:4 0.0001528508 +5 chanx_right_in[8]:5 0.0001528508 +6 chanx_right_in[8]:6 0.001573861 +7 chanx_right_in[8]:7 0.002362909 +8 chanx_right_in[8] chanx_right_in[12] 0.0002754554 +9 chanx_right_in[8]:6 chanx_right_in[12]:16 0.0005154171 +10 chanx_right_in[8]:6 chanx_right_in[12]:17 6.611618e-05 +11 chanx_right_in[8]:7 chanx_right_in[12] 6.611618e-05 +12 chanx_right_in[8]:7 chanx_right_in[12]:17 0.0007908725 +13 chanx_right_in[8] chanx_right_in[19] 0.0002445939 +14 chanx_right_in[8]:6 chanx_right_in[19]:14 0.0004300709 +15 chanx_right_in[8]:6 chanx_right_in[19]:15 0.00016192 +16 chanx_right_in[8]:7 chanx_right_in[19] 0.00016192 +17 chanx_right_in[8]:7 chanx_right_in[19]:15 0.0006746647 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:7 0.003674616 +1 chanx_right_in[8]:5 chanx_right_in[8]:4 0.002337054 +2 chanx_right_in[8]:6 chanx_right_in[8]:5 0.00341 +3 chanx_right_in[8]:3 chanx_right_in[8]:2 0.0130692 +4 chanx_right_in[8]:4 chanx_right_in[8]:3 0.0045 +5 chanx_right_in[8]:2 BUFT_P_153:A 0.152 +6 chanx_right_in[8]:7 chanx_right_in[8]:6 0.007806308 + +*END + +*D_NET chanx_right_in[9] 0.01347777 //LENGTH 121.450 LUMPCC 0.001755552 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 103.575 38.080 +*I BUFT_P_154:A I *L 0.001776 *C 14.720 14.960 +*N chanx_right_in[9]:2 *C 14.683 14.960 +*N chanx_right_in[9]:3 *C 12.465 14.960 +*N chanx_right_in[9]:4 *C 12.420 15.005 +*N chanx_right_in[9]:5 *C 12.420 25.115 +*N chanx_right_in[9]:6 *C 12.465 25.160 +*N chanx_right_in[9]:7 *C 28.665 25.160 +*N chanx_right_in[9]:8 *C 28.585 25.205 +*N chanx_right_in[9]:9 *C 28.520 25.795 +*N chanx_right_in[9]:10 *C 28.565 25.840 +*N chanx_right_in[9]:11 *C 30.775 25.840 +*N chanx_right_in[9]:12 *C 30.820 25.885 +*N chanx_right_in[9]:13 *C 30.820 39.055 +*N chanx_right_in[9]:14 *C 30.865 39.100 +*N chanx_right_in[9]:15 *C 80.660 39.100 +*N chanx_right_in[9]:16 *C 95.635 39.100 +*N chanx_right_in[9]:17 *C 95.680 39.055 +*N chanx_right_in[9]:18 *C 95.680 38.138 +*N chanx_right_in[9]:19 *C 95.688 38.080 + +*CAP +0 chanx_right_in[9] 0.0005456434 +1 BUFT_P_154:A 1e-06 +2 chanx_right_in[9]:2 0.0001241062 +3 chanx_right_in[9]:3 0.0001241062 +4 chanx_right_in[9]:4 0.0005809662 +5 chanx_right_in[9]:5 0.0005809662 +6 chanx_right_in[9]:6 0.0009267357 +7 chanx_right_in[9]:7 0.0009267357 +8 chanx_right_in[9]:8 4.293981e-05 +9 chanx_right_in[9]:9 4.293981e-05 +10 chanx_right_in[9]:10 0.0001371522 +11 chanx_right_in[9]:11 0.0001371522 +12 chanx_right_in[9]:12 0.0006959329 +13 chanx_right_in[9]:13 0.0006959329 +14 chanx_right_in[9]:14 0.002089139 +15 chanx_right_in[9]:15 0.002736239 +16 chanx_right_in[9]:16 0.0006470994 +17 chanx_right_in[9]:17 7.089115e-05 +18 chanx_right_in[9]:18 7.089115e-05 +19 chanx_right_in[9]:19 0.0005456434 +20 chanx_right_in[9]:14 chanx_left_in[13] 1.562118e-05 +21 chanx_right_in[9]:14 chanx_left_in[13]:8 0.0005365132 +22 chanx_right_in[9]:16 chanx_left_in[13]:6 7.347155e-05 +23 chanx_right_in[9]:16 chanx_left_in[13]:7 0.0001090921 +24 chanx_right_in[9]:15 chanx_left_in[13]:7 0.0006099847 +25 chanx_right_in[9]:15 chanx_left_in[13]:8 0.0001090921 +26 chanx_right_in[9]:15 chanx_left_in[13]:11 1.562118e-05 +27 chanx_right_in[9]:6 ropt_net_175:7 6.597977e-05 +28 chanx_right_in[9]:7 ropt_net_175:8 6.597977e-05 +29 chanx_right_in[9]:2 ropt_net_165:4 6.365719e-05 +30 chanx_right_in[9]:3 ropt_net_165:3 6.365719e-05 +31 chanx_right_in[9]:4 ropt_net_165:5 1.344084e-05 +32 chanx_right_in[9]:5 ropt_net_165:6 1.344084e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:19 0.001235708 +1 chanx_right_in[9]:2 BUFT_P_154:A 0.152 +2 chanx_right_in[9]:3 chanx_right_in[9]:2 0.001979911 +3 chanx_right_in[9]:4 chanx_right_in[9]:3 0.0045 +4 chanx_right_in[9]:6 chanx_right_in[9]:5 0.0045 +5 chanx_right_in[9]:5 chanx_right_in[9]:4 0.009026786 +6 chanx_right_in[9]:7 chanx_right_in[9]:6 0.01446429 +7 chanx_right_in[9]:8 chanx_right_in[9]:7 0.0045 +8 chanx_right_in[9]:10 chanx_right_in[9]:9 0.0045 +9 chanx_right_in[9]:9 chanx_right_in[9]:8 0.0005267857 +10 chanx_right_in[9]:11 chanx_right_in[9]:10 0.001973214 +11 chanx_right_in[9]:12 chanx_right_in[9]:11 0.0045 +12 chanx_right_in[9]:14 chanx_right_in[9]:13 0.0045 +13 chanx_right_in[9]:13 chanx_right_in[9]:12 0.01175893 +14 chanx_right_in[9]:16 chanx_right_in[9]:15 0.01337054 +15 chanx_right_in[9]:17 chanx_right_in[9]:16 0.0045 +16 chanx_right_in[9]:18 chanx_right_in[9]:17 0.0008191963 +17 chanx_right_in[9]:19 chanx_right_in[9]:18 0.00341 +18 chanx_right_in[9]:15 chanx_right_in[9]:14 0.04445982 + +*END + +*D_NET chanx_right_in[11] 0.01210583 //LENGTH 115.170 LUMPCC 0.0001542957 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 103.650 65.280 +*I BUFT_RR_73:A I *L 0.001776 *C 22.080 36.720 +*N chanx_right_in[11]:2 *C 22.080 36.720 +*N chanx_right_in[11]:3 *C 22.080 36.765 +*N chanx_right_in[11]:4 *C 22.080 44.155 +*N chanx_right_in[11]:5 *C 22.125 44.200 +*N chanx_right_in[11]:6 *C 32.820 44.200 +*N chanx_right_in[11]:7 *C 32.865 44.200 +*N chanx_right_in[11]:8 *C 33.120 44.268 +*N chanx_right_in[11]:9 *C 33.120 44.835 +*N chanx_right_in[11]:10 *C 33.120 44.880 +*N chanx_right_in[11]:11 *C 34.960 44.880 +*N chanx_right_in[11]:12 *C 34.960 45.220 +*N chanx_right_in[11]:13 *C 34.960 45.265 +*N chanx_right_in[11]:14 *C 34.960 66.255 +*N chanx_right_in[11]:15 *C 35.005 66.300 +*N chanx_right_in[11]:16 *C 84.800 66.300 +*N chanx_right_in[11]:17 *C 100.695 66.300 +*N chanx_right_in[11]:18 *C 100.740 66.255 +*N chanx_right_in[11]:19 *C 100.740 65.338 +*N chanx_right_in[11]:20 *C 100.748 65.280 + +*CAP +0 chanx_right_in[11] 0.0002315831 +1 BUFT_RR_73:A 1e-06 +2 chanx_right_in[11]:2 3.067276e-05 +3 chanx_right_in[11]:3 0.0003679557 +4 chanx_right_in[11]:4 0.0003679557 +5 chanx_right_in[11]:5 0.0006425569 +6 chanx_right_in[11]:6 0.0006425569 +7 chanx_right_in[11]:7 5.552048e-05 +8 chanx_right_in[11]:8 7.143813e-05 +9 chanx_right_in[11]:9 4.664507e-05 +10 chanx_right_in[11]:10 0.0001525986 +11 chanx_right_in[11]:11 0.0001593544 +12 chanx_right_in[11]:12 5.999868e-05 +13 chanx_right_in[11]:13 0.001039629 +14 chanx_right_in[11]:14 0.001039629 +15 chanx_right_in[11]:15 0.0024852 +16 chanx_right_in[11]:16 0.003324293 +17 chanx_right_in[11]:17 0.0008390928 +18 chanx_right_in[11]:18 8.113559e-05 +19 chanx_right_in[11]:19 8.113559e-05 +20 chanx_right_in[11]:20 0.0002315831 +21 chanx_right_in[11]:17 ropt_net_230:3 7.714784e-05 +22 chanx_right_in[11]:16 ropt_net_230:2 7.714784e-05 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:20 0.000454725 +1 chanx_right_in[11]:2 BUFT_RR_73:A 0.152 +2 chanx_right_in[11]:3 chanx_right_in[11]:2 0.0045 +3 chanx_right_in[11]:5 chanx_right_in[11]:4 0.0045 +4 chanx_right_in[11]:4 chanx_right_in[11]:3 0.006598215 +5 chanx_right_in[11]:6 chanx_right_in[11]:5 0.009549107 +6 chanx_right_in[11]:7 chanx_right_in[11]:6 0.0045 +7 chanx_right_in[11]:10 chanx_right_in[11]:9 0.0045 +8 chanx_right_in[11]:9 chanx_right_in[11]:8 0.0005066965 +9 chanx_right_in[11]:12 chanx_right_in[11]:11 0.0001465518 +10 chanx_right_in[11]:13 chanx_right_in[11]:12 0.0045 +11 chanx_right_in[11]:15 chanx_right_in[11]:14 0.0045 +12 chanx_right_in[11]:14 chanx_right_in[11]:13 0.01874107 +13 chanx_right_in[11]:17 chanx_right_in[11]:16 0.01419196 +14 chanx_right_in[11]:18 chanx_right_in[11]:17 0.0045 +15 chanx_right_in[11]:19 chanx_right_in[11]:18 0.0008191965 +16 chanx_right_in[11]:20 chanx_right_in[11]:19 0.00341 +17 chanx_right_in[11]:11 chanx_right_in[11]:10 0.001642857 +18 chanx_right_in[11]:8 chanx_right_in[11]:7 0.000138587 +19 chanx_right_in[11]:16 chanx_right_in[11]:15 0.04445983 + +*END + +*D_NET chanx_right_in[13] 0.01493316 //LENGTH 136.605 LUMPCC 0 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 103.650 59.840 +*I BUFT_P_121:A I *L 0.001776 *C 17.020 12.240 +*N chanx_right_in[13]:2 *C 17.058 12.240 +*N chanx_right_in[13]:3 *C 18.860 12.240 +*N chanx_right_in[13]:4 *C 18.860 12.580 +*N chanx_right_in[13]:5 *C 27.555 12.580 +*N chanx_right_in[13]:6 *C 27.600 12.625 +*N chanx_right_in[13]:7 *C 27.600 36.675 +*N chanx_right_in[13]:8 *C 27.645 36.720 +*N chanx_right_in[13]:9 *C 38.495 36.720 +*N chanx_right_in[13]:10 *C 41.045 36.720 +*N chanx_right_in[13]:11 *C 41.815 36.720 +*N chanx_right_in[13]:12 *C 41.860 36.765 +*N chanx_right_in[13]:13 *C 41.860 59.115 +*N chanx_right_in[13]:14 *C 41.905 59.160 +*N chanx_right_in[13]:15 *C 91.700 59.160 +*N chanx_right_in[13]:16 *C 100.695 59.160 +*N chanx_right_in[13]:17 *C 100.740 59.205 +*N chanx_right_in[13]:18 *C 100.740 59.783 +*N chanx_right_in[13]:19 *C 100.748 59.840 + +*CAP +0 chanx_right_in[13] 0.0002277375 +1 BUFT_P_121:A 1e-06 +2 chanx_right_in[13]:2 0.0001188178 +3 chanx_right_in[13]:3 0.000143494 +4 chanx_right_in[13]:4 0.0005562988 +5 chanx_right_in[13]:5 0.0005316226 +6 chanx_right_in[13]:6 0.001213811 +7 chanx_right_in[13]:7 0.001213811 +8 chanx_right_in[13]:8 0.0005349979 +9 chanx_right_in[13]:9 0.0006611698 +10 chanx_right_in[13]:10 0.0001744448 +11 chanx_right_in[13]:11 4.827285e-05 +12 chanx_right_in[13]:12 0.001126976 +13 chanx_right_in[13]:13 0.001126976 +14 chanx_right_in[13]:14 0.00290501 +15 chanx_right_in[13]:15 0.003460061 +16 chanx_right_in[13]:16 0.0005550506 +17 chanx_right_in[13]:17 5.293646e-05 +18 chanx_right_in[13]:18 5.293646e-05 +19 chanx_right_in[13]:19 0.0002277375 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:19 0.000454725 +1 chanx_right_in[13]:2 BUFT_P_121:A 0.152 +2 chanx_right_in[13]:5 chanx_right_in[13]:4 0.007763393 +3 chanx_right_in[13]:6 chanx_right_in[13]:5 0.0045 +4 chanx_right_in[13]:8 chanx_right_in[13]:7 0.0045 +5 chanx_right_in[13]:7 chanx_right_in[13]:6 0.02147322 +6 chanx_right_in[13]:11 chanx_right_in[13]:10 0.0006875001 +7 chanx_right_in[13]:12 chanx_right_in[13]:11 0.0045 +8 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0045 +9 chanx_right_in[13]:13 chanx_right_in[13]:12 0.01995536 +10 chanx_right_in[13]:16 chanx_right_in[13]:15 0.008031251 +11 chanx_right_in[13]:17 chanx_right_in[13]:16 0.0045 +12 chanx_right_in[13]:18 chanx_right_in[13]:17 0.000515625 +13 chanx_right_in[13]:19 chanx_right_in[13]:18 0.00341 +14 chanx_right_in[13]:3 chanx_right_in[13]:2 0.001609375 +15 chanx_right_in[13]:4 chanx_right_in[13]:3 0.0003035715 +16 chanx_right_in[13]:9 chanx_right_in[13]:8 0.0096875 +17 chanx_right_in[13]:10 chanx_right_in[13]:9 0.002276786 +18 chanx_right_in[13]:15 chanx_right_in[13]:14 0.04445983 + +*END + +*D_NET chanx_right_in[16] 0.01475571 //LENGTH 125.540 LUMPCC 0.002653822 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 103.650 27.200 +*I ropt_mt_inst_775:A I *L 0.001767 *C 3.220 17.680 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 65.780 18.020 +*N chanx_right_in[16]:3 *C 65.803 17.860 +*N chanx_right_in[16]:4 *C 3.183 17.680 +*N chanx_right_in[16]:5 *C 1.885 17.680 +*N chanx_right_in[16]:6 *C 1.840 17.635 +*N chanx_right_in[16]:7 *C 1.840 14.325 +*N chanx_right_in[16]:8 *C 1.885 14.280 +*N chanx_right_in[16]:9 *C 20.195 14.280 +*N chanx_right_in[16]:10 *C 20.240 14.325 +*N chanx_right_in[16]:11 *C 20.240 16.955 +*N chanx_right_in[16]:12 *C 20.240 17.000 +*N chanx_right_in[16]:13 *C 20.240 17.680 +*N chanx_right_in[16]:14 *C 21.160 17.680 +*N chanx_right_in[16]:15 *C 21.160 17.340 +*N chanx_right_in[16]:16 *C 65.780 17.340 +*N chanx_right_in[16]:17 *C 65.793 17.680 +*N chanx_right_in[16]:18 *C 70.795 17.680 +*N chanx_right_in[16]:19 *C 70.840 17.725 +*N chanx_right_in[16]:20 *C 70.840 27.823 +*N chanx_right_in[16]:21 *C 70.847 27.880 +*N chanx_right_in[16]:22 *C 90.160 27.880 +*N chanx_right_in[16]:23 *C 90.160 27.200 + +*CAP +0 chanx_right_in[16] 0.0006837676 +1 ropt_mt_inst_775:A 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_3_:A1 1e-06 +3 chanx_right_in[16]:3 2.489155e-05 +4 chanx_right_in[16]:4 9.404431e-05 +5 chanx_right_in[16]:5 9.404431e-05 +6 chanx_right_in[16]:6 0.0001932655 +7 chanx_right_in[16]:7 0.0001932655 +8 chanx_right_in[16]:8 0.0009958184 +9 chanx_right_in[16]:9 0.0009958184 +10 chanx_right_in[16]:10 0.0001493194 +11 chanx_right_in[16]:11 0.0001493194 +12 chanx_right_in[16]:12 6.428175e-05 +13 chanx_right_in[16]:13 0.0001052728 +14 chanx_right_in[16]:14 9.267069e-05 +15 chanx_right_in[16]:15 0.002109548 +16 chanx_right_in[16]:16 0.002104882 +17 chanx_right_in[16]:17 0.0003198097 +18 chanx_right_in[16]:18 0.0002769187 +19 chanx_right_in[16]:19 0.0005195729 +20 chanx_right_in[16]:20 0.0005195729 +21 chanx_right_in[16]:21 0.0008117859 +22 chanx_right_in[16]:22 0.0008650168 +23 chanx_right_in[16]:23 0.0007369985 +24 chanx_right_in[16] chanx_left_in[17]:5 6.033061e-06 +25 chanx_right_in[16]:21 chanx_left_in[17]:6 0.0004594341 +26 chanx_right_in[16]:22 chanx_left_in[17]:5 0.0004594341 +27 chanx_right_in[16]:23 chanx_left_in[17]:6 6.033061e-06 +28 chanx_right_in[16]:15 chanx_right_in[14]:8 0.0003079346 +29 chanx_right_in[16]:16 chanx_right_in[14]:9 0.0003079346 +30 chanx_right_in[16]:18 optlc_net_161:3 3.604686e-05 +31 chanx_right_in[16]:17 optlc_net_161:2 3.604686e-05 +32 chanx_right_in[16]:9 ropt_net_203:5 0.0003089091 +33 chanx_right_in[16]:9 ropt_net_203:3 9.344079e-06 +34 chanx_right_in[16]:8 ropt_net_203:2 9.344079e-06 +35 chanx_right_in[16]:8 ropt_net_203:4 0.0003089091 +36 chanx_right_in[16] ropt_net_184:6 0.0001992092 +37 chanx_right_in[16]:23 ropt_net_184:7 0.0001992092 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:23 0.002113433 +1 chanx_right_in[16]:12 chanx_right_in[16]:11 0.0045 +2 chanx_right_in[16]:11 chanx_right_in[16]:10 0.002348214 +3 chanx_right_in[16]:9 chanx_right_in[16]:8 0.01634821 +4 chanx_right_in[16]:10 chanx_right_in[16]:9 0.0045 +5 chanx_right_in[16]:8 chanx_right_in[16]:7 0.0045 +6 chanx_right_in[16]:7 chanx_right_in[16]:6 0.002955357 +7 chanx_right_in[16]:5 chanx_right_in[16]:4 0.001158482 +8 chanx_right_in[16]:6 chanx_right_in[16]:5 0.0045 +9 chanx_right_in[16]:4 ropt_mt_inst_775:A 0.152 +10 chanx_right_in[16]:3 mux_bottom_ipin_0\/mux_l2_in_3_:A1 0.152 +11 chanx_right_in[16]:18 chanx_right_in[16]:17 0.004466518 +12 chanx_right_in[16]:19 chanx_right_in[16]:18 0.0045 +13 chanx_right_in[16]:20 chanx_right_in[16]:19 0.009015625 +14 chanx_right_in[16]:21 chanx_right_in[16]:20 0.00341 +15 chanx_right_in[16]:13 chanx_right_in[16]:12 0.000607143 +16 chanx_right_in[16]:14 chanx_right_in[16]:13 0.0008214285 +17 chanx_right_in[16]:15 chanx_right_in[16]:14 0.0003035715 +18 chanx_right_in[16]:16 chanx_right_in[16]:15 0.03983929 +19 chanx_right_in[16]:17 chanx_right_in[16]:16 0.0003035715 +20 chanx_right_in[16]:17 chanx_right_in[16]:3 0.0001607143 +21 chanx_right_in[16]:22 chanx_right_in[16]:21 0.003025625 +22 chanx_right_in[16]:23 chanx_right_in[16]:22 0.0001065333 + +*END + +*D_NET chanx_right_in[19] 0.01300618 //LENGTH 118.330 LUMPCC 0.003348696 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 103.650 61.200 +*I ropt_mt_inst_781:A I *L 0.001767 *C 3.220 47.600 +*N chanx_right_in[19]:2 *C 3.183 47.600 +*N chanx_right_in[19]:3 *C 2.805 47.600 +*N chanx_right_in[19]:4 *C 2.760 47.645 +*N chanx_right_in[19]:5 *C 2.760 50.955 +*N chanx_right_in[19]:6 *C 2.805 51.000 +*N chanx_right_in[19]:7 *C 13.680 51.000 +*N chanx_right_in[19]:8 *C 13.793 50.955 +*N chanx_right_in[19]:9 *C 13.800 50.365 +*N chanx_right_in[19]:10 *C 13.845 50.320 +*N chanx_right_in[19]:11 *C 16.975 50.320 +*N chanx_right_in[19]:12 *C 17.020 50.365 +*N chanx_right_in[19]:13 *C 17.020 61.143 +*N chanx_right_in[19]:14 *C 17.027 61.200 +*N chanx_right_in[19]:15 *C 66.855 61.200 + +*CAP +0 chanx_right_in[19] 0.001411989 +1 ropt_mt_inst_781:A 1e-06 +2 chanx_right_in[19]:2 4.199824e-05 +3 chanx_right_in[19]:3 4.199824e-05 +4 chanx_right_in[19]:4 0.0002132402 +5 chanx_right_in[19]:5 0.0002132402 +6 chanx_right_in[19]:6 0.0006400661 +7 chanx_right_in[19]:7 0.0006400661 +8 chanx_right_in[19]:8 5.272401e-05 +9 chanx_right_in[19]:9 5.272401e-05 +10 chanx_right_in[19]:10 0.0001842678 +11 chanx_right_in[19]:11 0.0001842678 +12 chanx_right_in[19]:12 0.0005560777 +13 chanx_right_in[19]:13 0.0005560777 +14 chanx_right_in[19]:14 0.001727878 +15 chanx_right_in[19]:15 0.003139867 +16 chanx_right_in[19]:14 chanx_left_in[18]:15 0.0004754361 +17 chanx_right_in[19]:15 chanx_left_in[18]:14 0.0004754361 +18 chanx_right_in[19] chanx_right_in[1] 4.272947e-07 +19 chanx_right_in[19] chanx_right_in[1]:16 0.0002000191 +20 chanx_right_in[19]:14 chanx_right_in[1]:15 9.629126e-05 +21 chanx_right_in[19]:15 chanx_right_in[1]:15 0.0002000191 +22 chanx_right_in[19]:15 chanx_right_in[1]:16 9.629126e-05 +23 chanx_right_in[19]:15 chanx_right_in[1]:19 4.272947e-07 +24 chanx_right_in[19] chanx_right_in[8] 0.0002445939 +25 chanx_right_in[19] chanx_right_in[8]:7 0.00016192 +26 chanx_right_in[19]:14 chanx_right_in[8]:6 0.0004300709 +27 chanx_right_in[19]:15 chanx_right_in[8]:6 0.00016192 +28 chanx_right_in[19]:15 chanx_right_in[8]:7 0.0006746647 +29 chanx_right_in[19]:6 ropt_net_223:3 6.558941e-05 +30 chanx_right_in[19]:7 ropt_net_223:2 6.558941e-05 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:15 0.00576455 +1 chanx_right_in[19]:2 ropt_mt_inst_781:A 0.152 +2 chanx_right_in[19]:3 chanx_right_in[19]:2 0.0003370536 +3 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +4 chanx_right_in[19]:6 chanx_right_in[19]:5 0.0045 +5 chanx_right_in[19]:5 chanx_right_in[19]:4 0.002955357 +6 chanx_right_in[19]:7 chanx_right_in[19]:6 0.009709822 +7 chanx_right_in[19]:8 chanx_right_in[19]:7 0.0045 +8 chanx_right_in[19]:10 chanx_right_in[19]:9 0.0045 +9 chanx_right_in[19]:9 chanx_right_in[19]:8 0.0005267857 +10 chanx_right_in[19]:11 chanx_right_in[19]:10 0.002794643 +11 chanx_right_in[19]:12 chanx_right_in[19]:11 0.0045 +12 chanx_right_in[19]:13 chanx_right_in[19]:12 0.009622768 +13 chanx_right_in[19]:14 chanx_right_in[19]:13 0.00341 +14 chanx_right_in[19]:15 chanx_right_in[19]:14 0.007806308 + +*END + +*D_NET top_grid_pin_0_[0] 0.002337747 //LENGTH 24.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l4_in_0_:X O *L 0 *C 68.780 61.200 +*P top_grid_pin_0_[0] O *L 0.7423 *C 79.120 74.870 +*N top_grid_pin_0_[0]:2 *C 79.120 61.245 +*N top_grid_pin_0_[0]:3 *C 79.075 61.200 +*N top_grid_pin_0_[0]:4 *C 68.818 61.200 + +*CAP +0 mux_bottom_ipin_0\/mux_l4_in_0_:X 1e-06 +1 top_grid_pin_0_[0] 0.0006450043 +2 top_grid_pin_0_[0]:2 0.0006450043 +3 top_grid_pin_0_[0]:3 0.0005233692 +4 top_grid_pin_0_[0]:4 0.0005233692 + +*RES +0 mux_bottom_ipin_0\/mux_l4_in_0_:X top_grid_pin_0_[0]:4 0.152 +1 top_grid_pin_0_[0]:4 top_grid_pin_0_[0]:3 0.009158483 +2 top_grid_pin_0_[0]:3 top_grid_pin_0_[0]:2 0.0045 +3 top_grid_pin_0_[0]:2 top_grid_pin_0_[0] 0.01216518 + +*END + +*D_NET ropt_net_196 0.0005929631 //LENGTH 5.270 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_0\/BUFT_RR_125:X O *L 0 *C 59.340 70.040 +*I ropt_mt_inst_791:A I *L 0.001766 *C 57.960 72.080 +*N ropt_net_196:2 *C 57.922 72.080 +*N ropt_net_196:3 *C 57.545 72.080 +*N ropt_net_196:4 *C 57.500 72.035 +*N ropt_net_196:5 *C 57.500 70.085 +*N ropt_net_196:6 *C 57.545 70.040 +*N ropt_net_196:7 *C 59.303 70.040 + +*CAP +0 mem_bottom_ipin_0\/BUFT_RR_125:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_196:2 3.684194e-05 +3 ropt_net_196:3 3.684194e-05 +4 ropt_net_196:4 0.0001076396 +5 ropt_net_196:5 0.0001076396 +6 ropt_net_196:6 0.000151 +7 ropt_net_196:7 0.000151 + +*RES +0 mem_bottom_ipin_0\/BUFT_RR_125:X ropt_net_196:7 0.152 +1 ropt_net_196:7 ropt_net_196:6 0.001569197 +2 ropt_net_196:6 ropt_net_196:5 0.0045 +3 ropt_net_196:5 ropt_net_196:4 0.001741071 +4 ropt_net_196:3 ropt_net_196:2 0.0003370536 +5 ropt_net_196:4 ropt_net_196:3 0.0045 +6 ropt_net_196:2 ropt_mt_inst_791:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.005772651 //LENGTH 52.030 LUMPCC 0.0005072794 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 82.185 53.040 +*I mux_bottom_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 83.360 34.000 +*I mux_bottom_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 81.060 25.840 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 63.655 31.620 +*I mux_bottom_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 82.440 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 82.403 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 81.925 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 81.880 55.715 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 63.693 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 80.960 25.840 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 80.960 25.885 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 80.960 31.575 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 80.960 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 81.835 31.620 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 81.880 31.665 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 83.323 34.000 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 81.925 34.000 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 81.880 34.000 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 81.880 53.040 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 81.880 53.040 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 82.185 53.040 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_2_:S 1e-06 +3 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_ipin_0\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 6.178029e-05 +6 mux_tree_tapbuf_size10_0_sram[0]:6 6.178029e-05 +7 mux_tree_tapbuf_size10_0_sram[0]:7 0.0001211206 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.000974071 +9 mux_tree_tapbuf_size10_0_sram[0]:9 2.95411e-05 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0003176928 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.0003176928 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.001066301 +13 mux_tree_tapbuf_size10_0_sram[0]:13 5.806293e-05 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0001258096 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0001152575 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0001152575 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0009044512 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0008962356 +19 mux_tree_tapbuf_size10_0_sram[0]:19 4.793213e-05 +20 mux_tree_tapbuf_size10_0_sram[0]:20 4.738574e-05 +21 mux_tree_tapbuf_size10_0_sram[0]:18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001884518 +22 mux_tree_tapbuf_size10_0_sram[0]:18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.766672e-05 +23 mux_tree_tapbuf_size10_0_sram[0]:18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 3.732655e-05 +24 mux_tree_tapbuf_size10_0_sram[0]:17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001884518 +25 mux_tree_tapbuf_size10_0_sram[0]:17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 3.732655e-05 +26 mux_tree_tapbuf_size10_0_sram[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 1.946395e-07 +27 mux_tree_tapbuf_size10_0_sram[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.766672e-05 +28 mux_tree_tapbuf_size10_0_sram[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 1.946395e-07 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:20 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:9 mux_bottom_ipin_0\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.0045 +3 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:8 0.01541741 +5 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.005080357 +6 mux_tree_tapbuf_size10_0_sram[0]:8 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.00078125 +8 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +9 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.0045 +10 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.017 +11 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:7 0.002388393 +12 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001657609 +13 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.001247768 +14 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:14 0.002084821 +16 mux_tree_tapbuf_size10_0_sram[0]:15 mux_bottom_ipin_0\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.0004263393 +18 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0045 +19 mux_tree_tapbuf_size10_0_sram[0]:5 mux_bottom_ipin_0\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET optlc_net_161 0.0003764355 //LENGTH 2.760 LUMPCC 7.209372e-05 DR + +*CONN +*I optlc_161:HI O *L 0 *C 68.540 17.000 +*I mux_bottom_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 66.070 17.000 +*N optlc_net_161:2 *C 66.108 17.000 +*N optlc_net_161:3 *C 68.502 17.000 + +*CAP +0 optlc_161:HI 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_3_:A0 1e-06 +2 optlc_net_161:2 0.0001511709 +3 optlc_net_161:3 0.0001511709 +4 optlc_net_161:2 chanx_right_in[16]:17 3.604686e-05 +5 optlc_net_161:3 chanx_right_in[16]:18 3.604686e-05 + +*RES +0 optlc_161:HI optlc_net_161:3 0.152 +1 optlc_net_161:2 mux_bottom_ipin_0\/mux_l2_in_3_:A0 0.152 +2 optlc_net_161:3 optlc_net_161:2 0.002138393 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002063702 //LENGTH 18.410 LUMPCC 0.0003749382 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_2_:X O *L 0 *C 80.215 25.500 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 67.985 20.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 68.023 20.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 79.995 20.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.040 20.105 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 80.040 25.455 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 80.040 25.500 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 80.215 25.500 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005145051 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0005145051 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002793406 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002793406 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.031998e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.87523e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[10]:8 5.617466e-06 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[10]:9 0.0001195145 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[10]:7 0.0001195145 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[10]:9 5.617466e-06 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[19]:7 6.233707e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[19]:6 6.233707e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.01068973 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00361048 //LENGTH 30.705 LUMPCC 0.0008280656 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_1_:X O *L 0 *C 66.415 20.740 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 66.530 44.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 66.568 44.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 69.415 44.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 69.460 44.155 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 69.460 23.505 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 69.415 23.460 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 66.745 23.460 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 66.700 23.415 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 66.700 20.785 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 66.700 20.740 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 66.415 20.740 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000139348 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000139348 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0009815129 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0009815129 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001009054 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001009054 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001049282 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001049282 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 6.262815e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 6.439774e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[3]:4 0.0001217004 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[3]:3 0.0001217004 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[3]:20 0.0001162061 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[3]:19 0.0001162061 +16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:13 7.063361e-05 +17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:20 5.354285e-06 +18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:23 7.255734e-06 +19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:24 1.243115e-05 +20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:19 5.354285e-06 +21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:21 7.255734e-06 +22 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:23 1.243115e-05 +23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:25 7.063361e-05 +24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size10_0_sram[1]:20 8.045144e-05 +25 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size10_0_sram[1]:19 8.045144e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002542411 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0184375 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002383929 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.002348214 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.003383866 //LENGTH 28.840 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_1_:X O *L 0 *C 63.195 41.480 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A0 I *L 0.005103 *C 63.940 60.365 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 63.978 60.365 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 68.035 60.365 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 68.080 60.320 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 68.080 41.525 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 68.035 41.480 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 63.233 41.480 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0003616495 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0003616495 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.00095834 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.00095834 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0003709433 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0003709433 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.004287947 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.01678125 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.003622768 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET ropt_net_202 0.001218022 //LENGTH 10.085 LUMPCC 0.0001114133 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 11.695 52.360 +*I ropt_mt_inst_797:A I *L 0.001767 *C 3.220 53.040 +*N ropt_net_202:2 *C 3.258 53.040 +*N ropt_net_202:3 *C 5.015 53.040 +*N ropt_net_202:4 *C 5.060 52.995 +*N ropt_net_202:5 *C 5.060 52.405 +*N ropt_net_202:6 *C 5.105 52.360 +*N ropt_net_202:7 *C 11.658 52.360 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_202:2 0.0001141168 +3 ropt_net_202:3 0.0001141168 +4 ropt_net_202:4 4.973578e-05 +5 ropt_net_202:5 4.973578e-05 +6 ropt_net_202:6 0.0003884518 +7 ropt_net_202:7 0.0003884518 +8 ropt_net_202:6 ropt_net_167:2 5.570667e-05 +9 ropt_net_202:7 ropt_net_167:3 5.570667e-05 + +*RES +0 ropt_mt_inst_762:X ropt_net_202:7 0.152 +1 ropt_net_202:2 ropt_mt_inst_797:A 0.152 +2 ropt_net_202:3 ropt_net_202:2 0.001569196 +3 ropt_net_202:4 ropt_net_202:3 0.0045 +4 ropt_net_202:6 ropt_net_202:5 0.0045 +5 ropt_net_202:5 ropt_net_202:4 0.0005267857 +6 ropt_net_202:7 ropt_net_202:6 0.005850446 + +*END + +*D_NET ropt_net_204 0.001323391 //LENGTH 11.445 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 11.695 8.840 +*I ropt_mt_inst_799:A I *L 0.001767 *C 3.220 6.800 +*N ropt_net_204:2 *C 3.258 6.800 +*N ropt_net_204:3 *C 5.015 6.800 +*N ropt_net_204:4 *C 5.060 6.845 +*N ropt_net_204:5 *C 5.060 8.795 +*N ropt_net_204:6 *C 5.105 8.840 +*N ropt_net_204:7 *C 11.658 8.840 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_204:2 0.0001177482 +3 ropt_net_204:3 0.0001177482 +4 ropt_net_204:4 0.0001206127 +5 ropt_net_204:5 0.0001206127 +6 ropt_net_204:6 0.0004223343 +7 ropt_net_204:7 0.0004223343 + +*RES +0 ropt_mt_inst_765:X ropt_net_204:7 0.152 +1 ropt_net_204:2 ropt_mt_inst_799:A 0.152 +2 ropt_net_204:3 ropt_net_204:2 0.001569196 +3 ropt_net_204:4 ropt_net_204:3 0.0045 +4 ropt_net_204:6 ropt_net_204:5 0.0045 +5 ropt_net_204:5 ropt_net_204:4 0.001741072 +6 ropt_net_204:7 ropt_net_204:6 0.005850446 + +*END + +*D_NET ropt_net_207 0.001058193 //LENGTH 9.165 LUMPCC 8.386877e-05 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 11.645 31.620 +*I ropt_mt_inst_802:A I *L 0.001767 *C 3.220 31.280 +*N ropt_net_207:2 *C 3.220 31.280 +*N ropt_net_207:3 *C 3.220 31.620 +*N ropt_net_207:4 *C 11.607 31.620 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 ropt_mt_inst_802:A 1e-06 +2 ropt_net_207:2 6.049542e-05 +3 ropt_net_207:3 0.0004705795 +4 ropt_net_207:4 0.0004412498 +5 ropt_net_207:4 ropt_net_175:3 4.193439e-05 +6 ropt_net_207:3 ropt_net_175:4 4.193439e-05 + +*RES +0 ropt_mt_inst_770:X ropt_net_207:4 0.152 +1 ropt_net_207:4 ropt_net_207:3 0.007488839 +2 ropt_net_207:2 ropt_mt_inst_802:A 0.152 +3 ropt_net_207:3 ropt_net_207:2 0.0003035714 + +*END + +*D_NET ropt_net_217 0.0008796669 //LENGTH 6.565 LUMPCC 0.0003951665 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 94.760 72.080 +*I ropt_mt_inst_812:A I *L 0.001766 *C 97.980 69.360 +*N ropt_net_217:2 *C 97.943 69.360 +*N ropt_net_217:3 *C 94.805 69.360 +*N ropt_net_217:4 *C 94.760 69.405 +*N ropt_net_217:5 *C 94.760 72.035 +*N ropt_net_217:6 *C 94.760 72.080 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 ropt_mt_inst_812:A 1e-06 +2 ropt_net_217:2 7.555839e-05 +3 ropt_net_217:3 7.555839e-05 +4 ropt_net_217:4 0.0001517259 +5 ropt_net_217:5 0.0001517259 +6 ropt_net_217:6 2.793195e-05 +7 ropt_net_217:2 chanx_left_in[15]:4 0.0001328598 +8 ropt_net_217:3 chanx_left_in[15]:3 0.0001328598 +9 ropt_net_217:2 ropt_net_194:5 6.010846e-05 +10 ropt_net_217:3 ropt_net_194:6 6.010846e-05 +11 ropt_net_217:4 ropt_net_194:4 4.61501e-06 +12 ropt_net_217:5 ropt_net_194:3 4.61501e-06 + +*RES +0 ropt_mt_inst_772:X ropt_net_217:6 0.152 +1 ropt_net_217:2 ropt_mt_inst_812:A 0.152 +2 ropt_net_217:3 ropt_net_217:2 0.002801339 +3 ropt_net_217:4 ropt_net_217:3 0.0045 +4 ropt_net_217:6 ropt_net_217:5 0.0045 +5 ropt_net_217:5 ropt_net_217:4 0.002348214 + +*END + +*D_NET ropt_net_221 0.0006301426 //LENGTH 5.290 LUMPCC 0.0001568283 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 4.140 27.880 +*I ropt_mt_inst_816:A I *L 0.001766 *C 7.820 28.560 +*N ropt_net_221:2 *C 7.783 28.560 +*N ropt_net_221:3 *C 4.645 28.560 +*N ropt_net_221:4 *C 4.600 28.515 +*N ropt_net_221:5 *C 4.600 27.925 +*N ropt_net_221:6 *C 4.555 27.880 +*N ropt_net_221:7 *C 4.178 27.880 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 ropt_mt_inst_816:A 1e-06 +2 ropt_net_221:2 0.0001473252 +3 ropt_net_221:3 0.0001473252 +4 ropt_net_221:4 4.439735e-05 +5 ropt_net_221:5 4.439735e-05 +6 ropt_net_221:6 4.393461e-05 +7 ropt_net_221:7 4.393461e-05 +8 ropt_net_221:2 chanx_left_in[2]:15 5.443065e-05 +9 ropt_net_221:3 chanx_left_in[2]:16 5.443065e-05 +10 ropt_net_221:4 chanx_left_in[2]:17 2.398349e-05 +11 ropt_net_221:5 chanx_left_in[2]:18 2.398349e-05 + +*RES +0 ropt_mt_inst_777:X ropt_net_221:7 0.152 +1 ropt_net_221:2 ropt_mt_inst_816:A 0.152 +2 ropt_net_221:3 ropt_net_221:2 0.002801339 +3 ropt_net_221:4 ropt_net_221:3 0.0045 +4 ropt_net_221:6 ropt_net_221:5 0.0045 +5 ropt_net_221:5 ropt_net_221:4 0.0005267857 +6 ropt_net_221:7 ropt_net_221:6 0.0003370536 + +*END + +*D_NET ropt_net_228 0.0005315335 //LENGTH 4.435 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 94.300 7.140 +*I ropt_mt_inst_823:A I *L 0.001766 *C 97.825 6.800 +*N ropt_net_228:2 *C 97.788 6.800 +*N ropt_net_228:3 *C 96.140 6.800 +*N ropt_net_228:4 *C 96.140 7.140 +*N ropt_net_228:5 *C 94.338 7.140 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 ropt_mt_inst_823:A 1e-06 +2 ropt_net_228:2 0.000112809 +3 ropt_net_228:3 0.0001362401 +4 ropt_net_228:4 0.0001519578 +5 ropt_net_228:5 0.0001285267 + +*RES +0 ropt_mt_inst_780:X ropt_net_228:5 0.152 +1 ropt_net_228:2 ropt_mt_inst_823:A 0.152 +2 ropt_net_228:5 ropt_net_228:4 0.001609375 +3 ropt_net_228:4 ropt_net_228:3 0.0003035715 +4 ropt_net_228:3 ropt_net_228:2 0.001470982 + +*END + +*D_NET aps_rename_1_ 0.002738337 //LENGTH 27.770 LUMPCC 0 DR + +*CONN +*I FTB_27__26:X O *L 0 *C 35.420 11.560 +*I BUFT_RR_68:A I *L 0.001766 *C 13.340 6.800 +*N aps_rename_1_:2 *C 13.378 6.800 +*N aps_rename_1_:3 *C 33.075 6.800 +*N aps_rename_1_:4 *C 33.120 6.845 +*N aps_rename_1_:5 *C 33.120 11.515 +*N aps_rename_1_:6 *C 33.165 11.560 +*N aps_rename_1_:7 *C 35.383 11.560 + +*CAP +0 FTB_27__26:X 1e-06 +1 BUFT_RR_68:A 1e-06 +2 aps_rename_1_:2 0.000967521 +3 aps_rename_1_:3 0.000967521 +4 aps_rename_1_:4 0.0002352745 +5 aps_rename_1_:5 0.0002352745 +6 aps_rename_1_:6 0.0001653728 +7 aps_rename_1_:7 0.0001653728 + +*RES +0 FTB_27__26:X aps_rename_1_:7 0.152 +1 aps_rename_1_:7 aps_rename_1_:6 0.001979911 +2 aps_rename_1_:6 aps_rename_1_:5 0.0045 +3 aps_rename_1_:5 aps_rename_1_:4 0.004169643 +4 aps_rename_1_:3 aps_rename_1_:2 0.01758706 +5 aps_rename_1_:4 aps_rename_1_:3 0.0045 +6 aps_rename_1_:2 BUFT_RR_68:A 0.152 + +*END + +*D_NET chanx_right_out[1] 0.0008600934 //LENGTH 6.560 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_787:X O *L 0 *C 97.255 14.960 +*P chanx_right_out[1] O *L 0.7423 *C 103.650 14.960 +*N chanx_right_out[1]:2 *C 97.263 14.960 +*N chanx_right_out[1]:3 *C 97.255 14.960 +*N chanx_right_out[1]:4 *C 97.255 14.960 + +*CAP +0 ropt_mt_inst_787:X 1e-06 +1 chanx_right_out[1] 0.0003903004 +2 chanx_right_out[1]:2 0.0003903004 +3 chanx_right_out[1]:3 3.466998e-05 +4 chanx_right_out[1]:4 4.382257e-05 + +*RES +0 ropt_mt_inst_787:X chanx_right_out[1]:4 0.152 +1 chanx_right_out[1]:4 chanx_right_out[1]:3 0.0045 +2 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +3 chanx_right_out[1]:2 chanx_right_out[1] 0.001000708 + +*END + +*D_NET chanx_left_out[4] 0.0007149283 //LENGTH 4.660 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 4.140 6.120 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 6.800 +*N chanx_left_out[4]:2 *C 1.840 6.800 +*N chanx_left_out[4]:3 *C 1.840 6.120 +*N chanx_left_out[4]:4 *C 2.752 6.120 +*N chanx_left_out[4]:5 *C 2.760 6.120 +*N chanx_left_out[4]:6 *C 2.805 6.120 +*N chanx_left_out[4]:7 *C 4.103 6.120 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 chanx_left_out[4] 7.708268e-05 +2 chanx_left_out[4]:2 0.0001372809 +3 chanx_left_out[4]:3 0.0001560432 +4 chanx_left_out[4]:4 9.584495e-05 +5 chanx_left_out[4]:5 3.396907e-05 +6 chanx_left_out[4]:6 0.0001068538 +7 chanx_left_out[4]:7 0.0001068538 + +*RES +0 ropt_mt_inst_799:X chanx_left_out[4]:7 0.152 +1 chanx_left_out[4]:7 chanx_left_out[4]:6 0.001158482 +2 chanx_left_out[4]:6 chanx_left_out[4]:5 0.0045 +3 chanx_left_out[4]:5 chanx_left_out[4]:4 0.00341 +4 chanx_left_out[4]:4 chanx_left_out[4]:3 0.0001429583 +5 chanx_left_out[4]:2 chanx_left_out[4] 9.556666e-05 +6 chanx_left_out[4]:3 chanx_left_out[4]:2 0.0001065333 + +*END + +*D_NET ropt_net_212 0.001437372 //LENGTH 11.555 LUMPCC 0.000198791 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 101.855 23.800 +*I ropt_mt_inst_807:A I *L 0.001767 *C 93.380 25.840 +*N ropt_net_212:2 *C 93.380 25.840 +*N ropt_net_212:3 *C 93.380 25.500 +*N ropt_net_212:4 *C 98.855 25.500 +*N ropt_net_212:5 *C 98.900 25.455 +*N ropt_net_212:6 *C 98.900 23.845 +*N ropt_net_212:7 *C 98.945 23.800 +*N ropt_net_212:8 *C 101.818 23.800 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 ropt_mt_inst_807:A 1e-06 +2 ropt_net_212:2 5.270447e-05 +3 ropt_net_212:3 0.0003152523 +4 ropt_net_212:4 0.0002892401 +5 ropt_net_212:5 9.588897e-05 +6 ropt_net_212:6 9.588897e-05 +7 ropt_net_212:7 0.0001938032 +8 ropt_net_212:8 0.0001938032 +9 ropt_net_212:4 ropt_net_197:6 9.762953e-05 +10 ropt_net_212:5 ropt_net_197:5 1.765967e-06 +11 ropt_net_212:6 ropt_net_197:4 1.765967e-06 +12 ropt_net_212:3 ropt_net_197:7 9.762953e-05 + +*RES +0 ropt_mt_inst_792:X ropt_net_212:8 0.152 +1 ropt_net_212:2 ropt_mt_inst_807:A 0.152 +2 ropt_net_212:4 ropt_net_212:3 0.004888393 +3 ropt_net_212:5 ropt_net_212:4 0.0045 +4 ropt_net_212:7 ropt_net_212:6 0.0045 +5 ropt_net_212:6 ropt_net_212:5 0.0014375 +6 ropt_net_212:8 ropt_net_212:7 0.002564732 +7 ropt_net_212:3 ropt_net_212:2 0.0003035715 + +*END + +*D_NET chanx_right_out[0] 0.0005677005 //LENGTH 4.370 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 101.855 14.280 +*P chanx_right_out[0] O *L 0.7423 *C 103.650 12.240 +*N chanx_right_out[0]:2 *C 102.128 12.240 +*N chanx_right_out[0]:3 *C 102.120 12.298 +*N chanx_right_out[0]:4 *C 102.120 14.235 +*N chanx_right_out[0]:5 *C 102.120 14.280 +*N chanx_right_out[0]:6 *C 101.855 14.280 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 chanx_right_out[0] 0.000108225 +2 chanx_right_out[0]:2 0.000108225 +3 chanx_right_out[0]:3 0.0001209557 +4 chanx_right_out[0]:4 0.0001209557 +5 chanx_right_out[0]:5 4.999527e-05 +6 chanx_right_out[0]:6 5.834375e-05 + +*RES +0 ropt_mt_inst_795:X chanx_right_out[0]:6 0.152 +1 chanx_right_out[0]:6 chanx_right_out[0]:5 0.0001440218 +2 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +3 chanx_right_out[0]:4 chanx_right_out[0]:3 0.001729911 +4 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +5 chanx_right_out[0]:2 chanx_right_out[0] 0.000238525 + +*END + +*D_NET chanx_right_out[12] 0.001573651 //LENGTH 13.565 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_806:X O *L 0 *C 94.300 8.840 +*P chanx_right_out[12] O *L 0.7423 *C 103.650 5.440 +*N chanx_right_out[12]:2 *C 95.688 5.440 +*N chanx_right_out[12]:3 *C 95.680 5.498 +*N chanx_right_out[12]:4 *C 95.680 8.795 +*N chanx_right_out[12]:5 *C 95.635 8.840 +*N chanx_right_out[12]:6 *C 94.338 8.840 + +*CAP +0 ropt_mt_inst_806:X 1e-06 +1 chanx_right_out[12] 0.0004908956 +2 chanx_right_out[12]:2 0.0004908956 +3 chanx_right_out[12]:3 0.0001865388 +4 chanx_right_out[12]:4 0.0001865388 +5 chanx_right_out[12]:5 0.0001088908 +6 chanx_right_out[12]:6 0.0001088908 + +*RES +0 ropt_mt_inst_806:X chanx_right_out[12]:6 0.152 +1 chanx_right_out[12]:6 chanx_right_out[12]:5 0.001158482 +2 chanx_right_out[12]:5 chanx_right_out[12]:4 0.0045 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.002944197 +4 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +5 chanx_right_out[12]:2 chanx_right_out[12] 0.001247458 + +*END + +*D_NET chanx_right_out[13] 0.0007925438 //LENGTH 6.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_809:X O *L 0 *C 98.900 48.280 +*P chanx_right_out[13] O *L 0.7423 *C 103.650 47.600 +*N chanx_right_out[13]:2 *C 99.828 47.600 +*N chanx_right_out[13]:3 *C 99.820 47.657 +*N chanx_right_out[13]:4 *C 99.820 48.235 +*N chanx_right_out[13]:5 *C 99.775 48.280 +*N chanx_right_out[13]:6 *C 98.938 48.280 + +*CAP +0 ropt_mt_inst_809:X 1e-06 +1 chanx_right_out[13] 0.000258197 +2 chanx_right_out[13]:2 0.000258197 +3 chanx_right_out[13]:3 5.634622e-05 +4 chanx_right_out[13]:4 5.634622e-05 +5 chanx_right_out[13]:5 8.122865e-05 +6 chanx_right_out[13]:6 8.122865e-05 + +*RES +0 ropt_mt_inst_809:X chanx_right_out[13]:6 0.152 +1 chanx_right_out[13]:6 chanx_right_out[13]:5 0.0007477679 +2 chanx_right_out[13]:5 chanx_right_out[13]:4 0.0045 +3 chanx_right_out[13]:4 chanx_right_out[13]:3 0.000515625 +4 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +5 chanx_right_out[13]:2 chanx_right_out[13] 0.0005988583 + +*END + +*D_NET chanx_left_out[19] 0.0009240729 //LENGTH 6.050 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_813:X O *L 0 *C 7.125 44.880 +*P chanx_left_out[19] O *L 0.7423 *C 1.305 44.880 +*N chanx_left_out[19]:2 *C 6.893 44.880 +*N chanx_left_out[19]:3 *C 6.900 44.880 +*N chanx_left_out[19]:4 *C 6.900 44.880 +*N chanx_left_out[19]:5 *C 7.125 44.880 + +*CAP +0 ropt_mt_inst_813:X 1e-06 +1 chanx_left_out[19] 0.00038589 +2 chanx_left_out[19]:2 0.00038589 +3 chanx_left_out[19]:3 3.703442e-05 +4 chanx_left_out[19]:4 5.537175e-05 +5 chanx_left_out[19]:5 5.888677e-05 + +*RES +0 ropt_mt_inst_813:X chanx_left_out[19]:5 0.152 +1 chanx_left_out[19]:3 chanx_left_out[19]:2 0.00341 +2 chanx_left_out[19]:2 chanx_left_out[19] 0.000875375 +3 chanx_left_out[19]:4 chanx_left_out[19]:3 0.0045 +4 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0001222826 + +*END + +*D_NET chanx_left_out[17] 0.001412414 //LENGTH 11.440 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 7.095 38.760 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 34.000 +*N chanx_left_out[17]:2 *C 5.973 34.000 +*N chanx_left_out[17]:3 *C 5.980 34.058 +*N chanx_left_out[17]:4 *C 5.980 38.715 +*N chanx_left_out[17]:5 *C 6.025 38.760 +*N chanx_left_out[17]:6 *C 7.058 38.760 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 chanx_left_out[17] 0.0003414227 +2 chanx_left_out[17]:2 0.0003414227 +3 chanx_left_out[17]:3 0.0002505369 +4 chanx_left_out[17]:4 0.0002505369 +5 chanx_left_out[17]:5 0.0001137475 +6 chanx_left_out[17]:6 0.0001137475 + +*RES +0 ropt_mt_inst_815:X chanx_left_out[17]:6 0.152 +1 chanx_left_out[17]:6 chanx_left_out[17]:5 0.0009218751 +2 chanx_left_out[17]:5 chanx_left_out[17]:4 0.0045 +3 chanx_left_out[17]:4 chanx_left_out[17]:3 0.004158482 +4 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +5 chanx_left_out[17]:2 chanx_left_out[17] 0.0007429917 + +*END + +*D_NET chanx_left_out[3] 0.001621132 //LENGTH 13.320 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_820:X O *L 0 *C 11.695 71.400 +*P chanx_left_out[3] O *L 0.7423 *C 1.230 69.360 +*N chanx_left_out[3]:2 *C 11.033 69.360 +*N chanx_left_out[3]:3 *C 11.040 69.418 +*N chanx_left_out[3]:4 *C 11.040 71.355 +*N chanx_left_out[3]:5 *C 11.085 71.400 +*N chanx_left_out[3]:6 *C 11.658 71.400 + +*CAP +0 ropt_mt_inst_820:X 1e-06 +1 chanx_left_out[3] 0.000620523 +2 chanx_left_out[3]:2 0.000620523 +3 chanx_left_out[3]:3 0.0001307855 +4 chanx_left_out[3]:4 0.0001307855 +5 chanx_left_out[3]:5 5.875753e-05 +6 chanx_left_out[3]:6 5.875753e-05 + +*RES +0 ropt_mt_inst_820:X chanx_left_out[3]:6 0.152 +1 chanx_left_out[3]:6 chanx_left_out[3]:5 0.0005111608 +2 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +3 chanx_left_out[3]:4 chanx_left_out[3]:3 0.001729911 +4 chanx_left_out[3]:3 chanx_left_out[3]:2 0.00341 +5 chanx_left_out[3]:2 chanx_left_out[3] 0.001535725 + +*END + +*D_NET chanx_right_out[19] 0.0007953255 //LENGTH 6.010 LUMPCC 0.0001947899 DR + +*CONN +*I ropt_mt_inst_824:X O *L 0 *C 101.855 57.800 +*P chanx_right_out[19] O *L 0.7423 *C 103.650 54.400 +*N chanx_right_out[19]:2 *C 102.588 54.400 +*N chanx_right_out[19]:3 *C 102.580 54.458 +*N chanx_right_out[19]:4 *C 102.580 57.755 +*N chanx_right_out[19]:5 *C 102.535 57.800 +*N chanx_right_out[19]:6 *C 101.892 57.800 + +*CAP +0 ropt_mt_inst_824:X 1e-06 +1 chanx_right_out[19] 0.0001008014 +2 chanx_right_out[19]:2 0.0001008014 +3 chanx_right_out[19]:3 0.0001349944 +4 chanx_right_out[19]:4 0.0001349944 +5 chanx_right_out[19]:5 6.397189e-05 +6 chanx_right_out[19]:6 6.397189e-05 +7 chanx_right_out[19]:4 ropt_net_176:5 9.739496e-05 +8 chanx_right_out[19]:3 ropt_net_176:4 9.739496e-05 + +*RES +0 ropt_mt_inst_824:X chanx_right_out[19]:6 0.152 +1 chanx_right_out[19]:6 chanx_right_out[19]:5 0.0005736608 +2 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0045 +3 chanx_right_out[19]:4 chanx_right_out[19]:3 0.002944197 +4 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +5 chanx_right_out[19]:2 chanx_right_out[19] 0.0001664583 + +*END + +*D_NET ropt_net_173 0.00148384 //LENGTH 12.750 LUMPCC 0 DR + +*CONN +*I BUFT_P_121:X O *L 0 *C 14.720 12.920 +*I ropt_mt_inst_768:A I *L 0.001766 *C 3.220 12.240 +*N ropt_net_173:2 *C 3.258 12.240 +*N ropt_net_173:3 *C 6.440 12.240 +*N ropt_net_173:4 *C 6.440 12.920 +*N ropt_net_173:5 *C 14.683 12.920 + +*CAP +0 BUFT_P_121:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_173:2 0.0001836958 +3 ropt_net_173:3 0.0002250771 +4 ropt_net_173:4 0.0005572241 +5 ropt_net_173:5 0.0005158427 + +*RES +0 BUFT_P_121:X ropt_net_173:5 0.152 +1 ropt_net_173:2 ropt_mt_inst_768:A 0.152 +2 ropt_net_173:5 ropt_net_173:4 0.007359376 +3 ropt_net_173:3 ropt_net_173:2 0.002841518 +4 ropt_net_173:4 ropt_net_173:3 0.0006071429 + +*END + +*D_NET ropt_net_192 0.000614968 //LENGTH 4.830 LUMPCC 0 DR + +*CONN +*I BUFT_P_128:X O *L 0 *C 89.855 14.280 +*I ropt_mt_inst_787:A I *L 0.001766 *C 93.380 14.960 +*N ropt_net_192:2 *C 93.380 14.960 +*N ropt_net_192:3 *C 93.380 14.915 +*N ropt_net_192:4 *C 93.380 14.325 +*N ropt_net_192:5 *C 93.335 14.280 +*N ropt_net_192:6 *C 89.892 14.280 + +*CAP +0 BUFT_P_128:X 1e-06 +1 ropt_mt_inst_787:A 1e-06 +2 ropt_net_192:2 2.920939e-05 +3 ropt_net_192:3 5.146131e-05 +4 ropt_net_192:4 5.146131e-05 +5 ropt_net_192:5 0.000240418 +6 ropt_net_192:6 0.000240418 + +*RES +0 BUFT_P_128:X ropt_net_192:6 0.152 +1 ropt_net_192:2 ropt_mt_inst_787:A 0.152 +2 ropt_net_192:3 ropt_net_192:2 0.0045 +3 ropt_net_192:5 ropt_net_192:4 0.0045 +4 ropt_net_192:4 ropt_net_192:3 0.0005267857 +5 ropt_net_192:6 ropt_net_192:5 0.003073661 + +*END + +*D_NET ropt_net_190 0.0008506111 //LENGTH 6.600 LUMPCC 0.0001507595 DR + +*CONN +*I BUFT_P_139:X O *L 0 *C 92.460 10.200 +*I ropt_mt_inst_785:A I *L 0.001766 *C 97.980 9.520 +*N ropt_net_190:2 *C 97.980 9.520 +*N ropt_net_190:3 *C 97.980 10.200 +*N ropt_net_190:4 *C 92.498 10.200 + +*CAP +0 BUFT_P_139:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_190:2 7.78316e-05 +3 ropt_net_190:3 0.0003337558 +4 ropt_net_190:4 0.0002862642 +5 ropt_net_190:4 ropt_net_211:2 7.356168e-05 +6 ropt_net_190:4 ropt_net_211:6 1.818071e-06 +7 ropt_net_190:3 ropt_net_211:3 7.356168e-05 +8 ropt_net_190:3 ropt_net_211:7 1.818071e-06 + +*RES +0 BUFT_P_139:X ropt_net_190:4 0.152 +1 ropt_net_190:2 ropt_mt_inst_785:A 0.152 +2 ropt_net_190:4 ropt_net_190:3 0.00489509 +3 ropt_net_190:3 ropt_net_190:2 0.0006071429 + +*END + +*D_NET ropt_net_168 0.001359971 //LENGTH 13.770 LUMPCC 0 DR + +*CONN +*I BUFT_P_148:X O *L 0 *C 10.580 66.640 +*I ropt_mt_inst_763:A I *L 0.001766 *C 3.220 69.360 +*N ropt_net_168:2 *C 3.183 69.360 +*N ropt_net_168:3 *C 1.885 69.360 +*N ropt_net_168:4 *C 1.840 69.315 +*N ropt_net_168:5 *C 1.840 66.685 +*N ropt_net_168:6 *C 1.885 66.640 +*N ropt_net_168:7 *C 10.543 66.640 + +*CAP +0 BUFT_P_148:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_168:2 8.604805e-05 +3 ropt_net_168:3 8.604805e-05 +4 ropt_net_168:4 0.0001484797 +5 ropt_net_168:5 0.0001484797 +6 ropt_net_168:6 0.000444458 +7 ropt_net_168:7 0.000444458 + +*RES +0 BUFT_P_148:X ropt_net_168:7 0.152 +1 ropt_net_168:7 ropt_net_168:6 0.007729911 +2 ropt_net_168:6 ropt_net_168:5 0.0045 +3 ropt_net_168:5 ropt_net_168:4 0.002348214 +4 ropt_net_168:3 ropt_net_168:2 0.001158482 +5 ropt_net_168:4 ropt_net_168:3 0.0045 +6 ropt_net_168:2 ropt_mt_inst_763:A 0.152 + +*END + +*D_NET chanx_left_in[1] 0.01563154 //LENGTH 97.165 LUMPCC 0.009405073 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 20.400 +*I BUFT_P_128:A I *L 0.001767 *C 88.780 14.960 +*N chanx_left_in[1]:2 *C 88.818 14.960 +*N chanx_left_in[1]:3 *C 90.115 14.960 +*N chanx_left_in[1]:4 *C 90.160 15.005 +*N chanx_left_in[1]:5 *C 90.160 19.663 +*N chanx_left_in[1]:6 *C 90.153 19.720 +*N chanx_left_in[1]:7 *C 77.450 19.720 +*N chanx_left_in[1]:8 *C 27.600 19.720 +*N chanx_left_in[1]:9 *C 27.600 20.400 + +*CAP +0 chanx_left_in[1] 0.00126014 +1 BUFT_P_128:A 1e-06 +2 chanx_left_in[1]:2 0.0001087143 +3 chanx_left_in[1]:3 0.0001087143 +4 chanx_left_in[1]:4 0.0002613833 +5 chanx_left_in[1]:5 0.0002613833 +6 chanx_left_in[1]:6 0.0002394027 +7 chanx_left_in[1]:7 0.001428479 +8 chanx_left_in[1]:8 0.001243094 +9 chanx_left_in[1]:9 0.001314158 +10 chanx_left_in[1] chanx_right_in[7]:7 0.0002368138 +11 chanx_left_in[1]:6 chanx_right_in[7] 0.0006819558 +12 chanx_left_in[1]:6 chanx_right_in[7]:10 5.31479e-05 +13 chanx_left_in[1]:9 chanx_right_in[7]:8 0.0002478151 +14 chanx_left_in[1]:8 chanx_right_in[7]:7 8.145457e-07 +15 chanx_left_in[1]:8 chanx_right_in[7]:9 0.002801601 +16 chanx_left_in[1]:7 chanx_right_in[7]:8 8.145457e-07 +17 chanx_left_in[1]:7 chanx_right_in[7]:9 5.31479e-05 +18 chanx_left_in[1]:7 chanx_right_in[7]:10 0.003472555 +19 chanx_left_in[1]:6 chanx_right_in[15] 0.0001123947 +20 chanx_left_in[1]:6 chanx_right_in[15]:10 0.0001063116 +21 chanx_left_in[1]:8 chanx_right_in[15]:9 0.0007094973 +22 chanx_left_in[1]:7 chanx_right_in[15]:9 0.0001063116 +23 chanx_left_in[1]:7 chanx_right_in[15]:10 0.0008218919 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:9 0.004131299 +1 chanx_left_in[1]:2 BUFT_P_128:A 0.152 +2 chanx_left_in[1]:3 chanx_left_in[1]:2 0.001158482 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.0045 +4 chanx_left_in[1]:5 chanx_left_in[1]:4 0.004158482 +5 chanx_left_in[1]:6 chanx_left_in[1]:5 0.00341 +6 chanx_left_in[1]:9 chanx_left_in[1]:8 0.0001065333 +7 chanx_left_in[1]:8 chanx_left_in[1]:7 0.007809832 +8 chanx_left_in[1]:7 chanx_left_in[1]:6 0.001990058 + +*END + +*D_NET chanx_left_out[1] 0.001650831 //LENGTH 12.640 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 11.695 28.560 +*P chanx_left_out[1] O *L 0.7423 *C 1.230 29.920 +*N chanx_left_out[1]:2 *C 11.033 29.920 +*N chanx_left_out[1]:3 *C 11.040 29.863 +*N chanx_left_out[1]:4 *C 11.040 28.605 +*N chanx_left_out[1]:5 *C 11.085 28.560 +*N chanx_left_out[1]:6 *C 11.658 28.560 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 chanx_left_out[1] 0.0006639827 +2 chanx_left_out[1]:2 0.0006639827 +3 chanx_left_out[1]:3 0.0001060014 +4 chanx_left_out[1]:4 0.0001060014 +5 chanx_left_out[1]:5 5.49316e-05 +6 chanx_left_out[1]:6 5.49316e-05 + +*RES +0 ropt_mt_inst_816:X chanx_left_out[1]:6 0.152 +1 chanx_left_out[1]:6 chanx_left_out[1]:5 0.0005111608 +2 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +3 chanx_left_out[1]:4 chanx_left_out[1]:3 0.001122768 +4 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +5 chanx_left_out[1]:2 chanx_left_out[1] 0.001535725 + +*END + +*D_NET chanx_right_out[6] 0.0005837894 //LENGTH 4.370 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 101.855 6.120 +*P chanx_right_out[6] O *L 0.7423 *C 103.650 4.080 +*N chanx_right_out[6]:2 *C 102.128 4.080 +*N chanx_right_out[6]:3 *C 102.120 4.138 +*N chanx_right_out[6]:4 *C 102.120 6.075 +*N chanx_right_out[6]:5 *C 102.120 6.120 +*N chanx_right_out[6]:6 *C 101.855 6.120 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 chanx_right_out[6] 0.0001137831 +2 chanx_right_out[6]:2 0.0001137831 +3 chanx_right_out[6]:3 0.0001236095 +4 chanx_right_out[6]:4 0.0001236095 +5 chanx_right_out[6]:5 4.798234e-05 +6 chanx_right_out[6]:6 6.002184e-05 + +*RES +0 ropt_mt_inst_823:X chanx_right_out[6]:6 0.152 +1 chanx_right_out[6]:6 chanx_right_out[6]:5 0.0001440218 +2 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +3 chanx_right_out[6]:4 chanx_right_out[6]:3 0.001729911 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 0.000238525 + +*END + +*D_NET ropt_net_165 0.001419742 //LENGTH 9.860 LUMPCC 0.0005421976 DR + +*CONN +*I BUFT_P_124:X O *L 0 *C 14.260 17.340 +*I ropt_mt_inst_760:A I *L 0.001766 *C 7.820 14.960 +*N ropt_net_165:2 *C 7.820 14.960 +*N ropt_net_165:3 *C 7.820 15.300 +*N ropt_net_165:4 *C 13.755 15.300 +*N ropt_net_165:5 *C 13.800 15.345 +*N ropt_net_165:6 *C 13.800 17.295 +*N ropt_net_165:7 *C 13.845 17.340 +*N ropt_net_165:8 *C 14.223 17.340 + +*CAP +0 BUFT_P_124:X 1e-06 +1 ropt_mt_inst_760:A 1e-06 +2 ropt_net_165:2 5.422892e-05 +3 ropt_net_165:3 0.0002570465 +4 ropt_net_165:4 0.000237899 +5 ropt_net_165:5 0.0001128388 +6 ropt_net_165:6 0.0001128388 +7 ropt_net_165:7 5.034619e-05 +8 ropt_net_165:8 5.034619e-05 +9 ropt_net_165:4 chanx_right_in[9]:2 6.365719e-05 +10 ropt_net_165:5 chanx_right_in[9]:4 1.344084e-05 +11 ropt_net_165:6 chanx_right_in[9]:5 1.344084e-05 +12 ropt_net_165:3 chanx_right_in[9]:3 6.365719e-05 +13 ropt_net_165:2 ropt_net_171:7 1.333155e-05 +14 ropt_net_165:4 ropt_net_171:9 0.0001806692 +15 ropt_net_165:3 ropt_net_171:8 0.0001940007 + +*RES +0 BUFT_P_124:X ropt_net_165:8 0.152 +1 ropt_net_165:2 ropt_mt_inst_760:A 0.152 +2 ropt_net_165:4 ropt_net_165:3 0.005299107 +3 ropt_net_165:5 ropt_net_165:4 0.0045 +4 ropt_net_165:7 ropt_net_165:6 0.0045 +5 ropt_net_165:6 ropt_net_165:5 0.001741072 +6 ropt_net_165:8 ropt_net_165:7 0.0003370536 +7 ropt_net_165:3 ropt_net_165:2 0.0003035715 + +*END + +*D_NET ropt_net_195 0.002014846 //LENGTH 19.025 LUMPCC 9.48159e-05 DR + +*CONN +*I BUFT_P_140:X O *L 0 *C 100.280 60.520 +*I ropt_mt_inst_790:A I *L 0.001766 *C 97.825 44.880 +*N ropt_net_195:2 *C 97.863 44.880 +*N ropt_net_195:3 *C 98.855 44.880 +*N ropt_net_195:4 *C 98.900 44.925 +*N ropt_net_195:5 *C 98.900 60.475 +*N ropt_net_195:6 *C 98.945 60.520 +*N ropt_net_195:7 *C 100.243 60.520 + +*CAP +0 BUFT_P_140:X 1e-06 +1 ropt_mt_inst_790:A 1e-06 +2 ropt_net_195:2 7.813337e-05 +3 ropt_net_195:3 7.813337e-05 +4 ropt_net_195:4 0.0007786503 +5 ropt_net_195:5 0.0007786503 +6 ropt_net_195:6 0.0001022315 +7 ropt_net_195:7 0.0001022315 +8 ropt_net_195:5 ropt_net_222:4 4.740795e-05 +9 ropt_net_195:4 ropt_net_222:5 4.740795e-05 + +*RES +0 BUFT_P_140:X ropt_net_195:7 0.152 +1 ropt_net_195:7 ropt_net_195:6 0.001158482 +2 ropt_net_195:6 ropt_net_195:5 0.0045 +3 ropt_net_195:5 ropt_net_195:4 0.01388393 +4 ropt_net_195:3 ropt_net_195:2 0.0008861608 +5 ropt_net_195:4 ropt_net_195:3 0.0045 +6 ropt_net_195:2 ropt_mt_inst_790:A 0.152 + +*END + +*D_NET ropt_net_170 0.001503488 //LENGTH 14.480 LUMPCC 0 DR + +*CONN +*I BUFT_P_150:X O *L 0 *C 8.740 20.060 +*I ropt_mt_inst_765:A I *L 0.001766 *C 7.820 9.520 +*N ropt_net_170:2 *C 7.783 9.520 +*N ropt_net_170:3 *C 6.945 9.520 +*N ropt_net_170:4 *C 6.900 9.520 +*N ropt_net_170:5 *C 6.900 20.015 +*N ropt_net_170:6 *C 6.945 20.060 +*N ropt_net_170:7 *C 8.703 20.060 + +*CAP +0 BUFT_P_150:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_170:2 6.847752e-05 +3 ropt_net_170:3 6.847752e-05 +4 ropt_net_170:4 0.000581422 +5 ropt_net_170:5 0.0005528233 +6 ropt_net_170:6 0.000115144 +7 ropt_net_170:7 0.000115144 + +*RES +0 BUFT_P_150:X ropt_net_170:7 0.152 +1 ropt_net_170:2 ropt_mt_inst_765:A 0.152 +2 ropt_net_170:3 ropt_net_170:2 0.0007477679 +3 ropt_net_170:4 ropt_net_170:3 0.0045 +4 ropt_net_170:6 ropt_net_170:5 0.0045 +5 ropt_net_170:5 ropt_net_170:4 0.009370536 +6 ropt_net_170:7 ropt_net_170:6 0.001569197 + +*END + +*D_NET chanx_left_in[2] 0.01626358 //LENGTH 142.725 LUMPCC 0.000351748 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 25.840 +*I mux_bottom_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 84.085 34.340 +*I ropt_mt_inst_772:A I *L 0.001767 *C 93.380 72.080 +*N chanx_left_in[2]:3 *C 93.343 72.080 +*N chanx_left_in[2]:4 *C 90.665 72.080 +*N chanx_left_in[2]:5 *C 90.620 72.035 +*N chanx_left_in[2]:6 *C 90.620 67.025 +*N chanx_left_in[2]:7 *C 90.575 66.980 +*N chanx_left_in[2]:8 *C 86.065 66.980 +*N chanx_left_in[2]:9 *C 86.020 66.935 +*N chanx_left_in[2]:10 *C 84.123 34.340 +*N chanx_left_in[2]:11 *C 85.975 34.340 +*N chanx_left_in[2]:12 *C 86.020 34.340 +*N chanx_left_in[2]:13 *C 86.020 29.285 +*N chanx_left_in[2]:14 *C 85.975 29.240 +*N chanx_left_in[2]:15 *C 54.900 29.240 +*N chanx_left_in[2]:16 *C 5.105 29.240 +*N chanx_left_in[2]:17 *C 5.060 29.195 +*N chanx_left_in[2]:18 *C 5.060 25.898 +*N chanx_left_in[2]:19 *C 5.053 25.840 + +*CAP +0 chanx_left_in[2] 0.0002802036 +1 mux_bottom_ipin_0\/mux_l1_in_1_:A1 1e-06 +2 ropt_mt_inst_772:A 1e-06 +3 chanx_left_in[2]:3 0.0001458345 +4 chanx_left_in[2]:4 0.0001458345 +5 chanx_left_in[2]:5 0.000264588 +6 chanx_left_in[2]:6 0.000264588 +7 chanx_left_in[2]:7 0.0002800139 +8 chanx_left_in[2]:8 0.0002800139 +9 chanx_left_in[2]:9 0.001573391 +10 chanx_left_in[2]:10 0.0001376692 +11 chanx_left_in[2]:11 0.0001376692 +12 chanx_left_in[2]:12 0.001866402 +13 chanx_left_in[2]:13 0.0002644935 +14 chanx_left_in[2]:14 0.001928582 +15 chanx_left_in[2]:15 0.004878961 +16 chanx_left_in[2]:16 0.002950379 +17 chanx_left_in[2]:17 0.0001155033 +18 chanx_left_in[2]:18 0.0001155033 +19 chanx_left_in[2]:19 0.0002802036 +20 chanx_left_in[2]:16 ropt_net_221:3 5.443065e-05 +21 chanx_left_in[2]:17 ropt_net_221:4 2.398349e-05 +22 chanx_left_in[2]:18 ropt_net_221:5 2.398349e-05 +23 chanx_left_in[2]:15 ropt_net_221:2 5.443065e-05 +24 chanx_left_in[2]:17 ropt_net_175:5 9.74599e-05 +25 chanx_left_in[2]:18 ropt_net_175:6 9.74599e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:19 0.0005988583 +1 chanx_left_in[2]:8 chanx_left_in[2]:7 0.004026786 +2 chanx_left_in[2]:9 chanx_left_in[2]:8 0.0045 +3 chanx_left_in[2]:7 chanx_left_in[2]:6 0.0045 +4 chanx_left_in[2]:6 chanx_left_in[2]:5 0.004473215 +5 chanx_left_in[2]:4 chanx_left_in[2]:3 0.002390625 +6 chanx_left_in[2]:5 chanx_left_in[2]:4 0.0045 +7 chanx_left_in[2]:3 ropt_mt_inst_772:A 0.152 +8 chanx_left_in[2]:14 chanx_left_in[2]:13 0.0045 +9 chanx_left_in[2]:13 chanx_left_in[2]:12 0.004513393 +10 chanx_left_in[2]:16 chanx_left_in[2]:15 0.04445983 +11 chanx_left_in[2]:17 chanx_left_in[2]:16 0.0045 +12 chanx_left_in[2]:18 chanx_left_in[2]:17 0.002944197 +13 chanx_left_in[2]:19 chanx_left_in[2]:18 0.00341 +14 chanx_left_in[2]:11 chanx_left_in[2]:10 0.001654018 +15 chanx_left_in[2]:12 chanx_left_in[2]:11 0.0045 +16 chanx_left_in[2]:12 chanx_left_in[2]:9 0.02910268 +17 chanx_left_in[2]:10 mux_bottom_ipin_0\/mux_l1_in_1_:A1 0.152 +18 chanx_left_in[2]:15 chanx_left_in[2]:14 0.02774554 + +*END + +*D_NET chanx_right_in[15] 0.01022853 //LENGTH 95.020 LUMPCC 0.003053137 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 103.650 17.680 +*I BUFT_RR_77:A I *L 0.001776 *C 17.940 25.840 +*N chanx_right_in[15]:2 *C 17.940 25.840 +*N chanx_right_in[15]:3 *C 17.940 25.795 +*N chanx_right_in[15]:4 *C 17.940 20.445 +*N chanx_right_in[15]:5 *C 17.985 20.400 +*N chanx_right_in[15]:6 *C 33.535 20.400 +*N chanx_right_in[15]:7 *C 33.580 20.355 +*N chanx_right_in[15]:8 *C 33.580 17.738 +*N chanx_right_in[15]:9 *C 33.587 17.680 +*N chanx_right_in[15]:10 *C 83.415 17.680 + +*CAP +0 chanx_right_in[15] 0.0009909321 +1 BUFT_RR_77:A 1e-06 +2 chanx_right_in[15]:2 3.178395e-05 +3 chanx_right_in[15]:3 0.0002764839 +4 chanx_right_in[15]:4 0.0002764839 +5 chanx_right_in[15]:5 0.000552475 +6 chanx_right_in[15]:6 0.000552475 +7 chanx_right_in[15]:7 0.000156914 +8 chanx_right_in[15]:8 0.000156914 +9 chanx_right_in[15]:9 0.001594497 +10 chanx_right_in[15]:10 0.00258543 +11 chanx_right_in[15] chanx_left_in[1]:6 0.0001123947 +12 chanx_right_in[15]:9 chanx_left_in[1]:7 0.0001063116 +13 chanx_right_in[15]:9 chanx_left_in[1]:8 0.0007094973 +14 chanx_right_in[15]:10 chanx_left_in[1]:6 0.0001063116 +15 chanx_right_in[15]:10 chanx_left_in[1]:7 0.0008218919 +16 chanx_right_in[15] chanx_left_in[6]:7 3.070008e-05 +17 chanx_right_in[15]:9 chanx_left_in[6]:8 9.40965e-05 +18 chanx_right_in[15]:9 chanx_left_in[6]:9 0.000152055 +19 chanx_right_in[15]:4 chanx_left_in[6]:10 7.404753e-06 +20 chanx_right_in[15]:3 chanx_left_in[6]:11 7.404753e-06 +21 chanx_right_in[15]:10 chanx_left_in[6]:7 9.40965e-05 +22 chanx_right_in[15]:10 chanx_left_in[6]:8 0.0001827551 +23 chanx_right_in[15]:6 chanx_left_in[19]:7 0.0003141089 +24 chanx_right_in[15]:5 chanx_left_in[19]:8 0.0003141089 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:10 0.00317015 +1 chanx_right_in[15]:8 chanx_right_in[15]:7 0.002337054 +2 chanx_right_in[15]:9 chanx_right_in[15]:8 0.00341 +3 chanx_right_in[15]:6 chanx_right_in[15]:5 0.01388393 +4 chanx_right_in[15]:7 chanx_right_in[15]:6 0.0045 +5 chanx_right_in[15]:5 chanx_right_in[15]:4 0.0045 +6 chanx_right_in[15]:4 chanx_right_in[15]:3 0.004776786 +7 chanx_right_in[15]:2 BUFT_RR_77:A 0.152 +8 chanx_right_in[15]:3 chanx_right_in[15]:2 0.0045 +9 chanx_right_in[15]:10 chanx_right_in[15]:9 0.007806308 + +*END + +*D_NET chanx_right_in[18] 0.01295211 //LENGTH 115.100 LUMPCC 0.002372914 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 103.650 39.440 +*I BUFT_P_124:A I *L 0.001776 *C 16.560 17.680 +*N chanx_right_in[18]:2 *C 16.598 17.680 +*N chanx_right_in[18]:3 *C 18.815 17.680 +*N chanx_right_in[18]:4 *C 18.860 17.725 +*N chanx_right_in[18]:5 *C 18.860 23.415 +*N chanx_right_in[18]:6 *C 18.905 23.460 +*N chanx_right_in[18]:7 *C 21.160 23.460 +*N chanx_right_in[18]:8 *C 21.085 23.800 +*N chanx_right_in[18]:9 *C 21.152 23.755 +*N chanx_right_in[18]:10 *C 21.160 23.165 +*N chanx_right_in[18]:11 *C 21.205 23.120 +*N chanx_right_in[18]:12 *C 23.875 23.120 +*N chanx_right_in[18]:13 *C 23.920 23.165 +*N chanx_right_in[18]:14 *C 23.920 28.175 +*N chanx_right_in[18]:15 *C 23.965 28.220 +*N chanx_right_in[18]:16 *C 33.580 28.220 +*N chanx_right_in[18]:17 *C 33.580 27.880 +*N chanx_right_in[18]:18 *C 34.455 27.880 +*N chanx_right_in[18]:19 *C 34.500 27.925 +*N chanx_right_in[18]:20 *C 34.490 28.495 +*N chanx_right_in[18]:21 *C 34.418 28.560 +*N chanx_right_in[18]:22 *C 36.898 28.560 +*N chanx_right_in[18]:23 *C 36.905 28.560 +*N chanx_right_in[18]:24 *C 36.950 28.560 +*N chanx_right_in[18]:25 *C 40.435 28.560 +*N chanx_right_in[18]:26 *C 40.480 28.605 +*N chanx_right_in[18]:27 *C 40.480 39.383 +*N chanx_right_in[18]:28 *C 40.488 39.440 +*N chanx_right_in[18]:29 *C 90.315 39.440 + +*CAP +0 chanx_right_in[18] 0.0006159677 +1 BUFT_P_124:A 1e-06 +2 chanx_right_in[18]:2 0.0001548485 +3 chanx_right_in[18]:3 0.0001548485 +4 chanx_right_in[18]:4 0.0003090157 +5 chanx_right_in[18]:5 0.0003090157 +6 chanx_right_in[18]:6 0.0001596774 +7 chanx_right_in[18]:7 0.0001834724 +8 chanx_right_in[18]:8 5.054106e-05 +9 chanx_right_in[18]:9 4.269664e-05 +10 chanx_right_in[18]:10 4.269664e-05 +11 chanx_right_in[18]:11 0.0001756529 +12 chanx_right_in[18]:12 0.0001756529 +13 chanx_right_in[18]:13 0.0002551245 +14 chanx_right_in[18]:14 0.0002551245 +15 chanx_right_in[18]:15 0.0005413354 +16 chanx_right_in[18]:16 0.0005684154 +17 chanx_right_in[18]:17 0.0001020131 +18 chanx_right_in[18]:18 7.493304e-05 +19 chanx_right_in[18]:19 5.356067e-05 +20 chanx_right_in[18]:20 5.356067e-05 +21 chanx_right_in[18]:21 0.0002478293 +22 chanx_right_in[18]:22 0.0002478293 +23 chanx_right_in[18]:23 3.757094e-05 +24 chanx_right_in[18]:24 0.0002118968 +25 chanx_right_in[18]:25 0.0002118968 +26 chanx_right_in[18]:26 0.0005542932 +27 chanx_right_in[18]:27 0.0005542932 +28 chanx_right_in[18]:28 0.001809234 +29 chanx_right_in[18]:29 0.002425201 +30 chanx_right_in[18]:28 chanx_left_in[15]:14 5.703497e-06 +31 chanx_right_in[18]:28 chanx_left_in[15]:18 0.0001891331 +32 chanx_right_in[18]:28 chanx_left_in[15]:19 0.0003519382 +33 chanx_right_in[18]:29 chanx_left_in[15]:13 5.703497e-06 +34 chanx_right_in[18]:29 chanx_left_in[15]:17 0.0001891331 +35 chanx_right_in[18]:29 chanx_left_in[15]:18 0.0003519382 +36 chanx_right_in[18]:28 chanx_left_in[16] 0.0001308236 +37 chanx_right_in[18]:28 chanx_left_in[16]:10 0.0001732905 +38 chanx_right_in[18]:29 chanx_left_in[16]:9 0.0001732905 +39 chanx_right_in[18]:29 chanx_left_in[16]:10 0.0001308236 +40 chanx_right_in[18] chanx_right_in[14] 0.0001682756 +41 chanx_right_in[18]:28 chanx_right_in[14]:20 0.0001672925 +42 chanx_right_in[18]:29 chanx_right_in[14] 0.0001672925 +43 chanx_right_in[18]:29 chanx_right_in[14]:20 0.0001682756 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:29 0.00208915 +1 chanx_right_in[18]:20 chanx_right_in[18]:19 0.0005089286 +2 chanx_right_in[18]:21 chanx_right_in[18]:20 0.00341 +3 chanx_right_in[18]:23 chanx_right_in[18]:22 0.00341 +4 chanx_right_in[18]:22 chanx_right_in[18]:21 0.0003885333 +5 chanx_right_in[18]:24 chanx_right_in[18]:23 0.0045 +6 chanx_right_in[18]:25 chanx_right_in[18]:24 0.003111607 +7 chanx_right_in[18]:26 chanx_right_in[18]:25 0.0045 +8 chanx_right_in[18]:27 chanx_right_in[18]:26 0.009622768 +9 chanx_right_in[18]:28 chanx_right_in[18]:27 0.00341 +10 chanx_right_in[18]:18 chanx_right_in[18]:17 0.00078125 +11 chanx_right_in[18]:19 chanx_right_in[18]:18 0.0045 +12 chanx_right_in[18]:15 chanx_right_in[18]:14 0.0045 +13 chanx_right_in[18]:14 chanx_right_in[18]:13 0.004473214 +14 chanx_right_in[18]:12 chanx_right_in[18]:11 0.002383929 +15 chanx_right_in[18]:13 chanx_right_in[18]:12 0.0045 +16 chanx_right_in[18]:11 chanx_right_in[18]:10 0.0045 +17 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0005267857 +18 chanx_right_in[18]:8 chanx_right_in[18]:7 0.0003035715 +19 chanx_right_in[18]:9 chanx_right_in[18]:8 0.0045 +20 chanx_right_in[18]:6 chanx_right_in[18]:5 0.0045 +21 chanx_right_in[18]:5 chanx_right_in[18]:4 0.005080357 +22 chanx_right_in[18]:3 chanx_right_in[18]:2 0.001979911 +23 chanx_right_in[18]:4 chanx_right_in[18]:3 0.0045 +24 chanx_right_in[18]:2 BUFT_P_124:A 0.152 +25 chanx_right_in[18]:7 chanx_right_in[18]:6 0.002013393 +26 chanx_right_in[18]:16 chanx_right_in[18]:15 0.008584822 +27 chanx_right_in[18]:17 chanx_right_in[18]:16 0.0003035715 +28 chanx_right_in[18]:29 chanx_right_in[18]:28 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.002781678 //LENGTH 25.233 LUMPCC 0.0004076903 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 68.385 47.940 +*I mem_bottom_ipin_0\/FTB_1__40:A I *L 0.001746 *C 65.780 63.920 +*I mux_bottom_ipin_0\/mux_l4_in_0_:S I *L 0.008363 *C 63.728 61.478 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 64.815 61.540 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 64.860 61.585 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 64.860 64.215 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 64.905 64.260 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 65.780 64.260 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 65.780 63.920 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 65.780 63.875 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 65.780 47.985 +*N mux_tree_tapbuf_size10_0_sram[3]:11 *C 65.825 47.940 +*N mux_tree_tapbuf_size10_0_sram[3]:12 *C 68.347 47.940 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_ipin_0\/FTB_1__40:A 1e-06 +2 mux_bottom_ipin_0\/mux_l4_in_0_:S 9.172053e-05 +3 mux_tree_tapbuf_size10_0_sram[3]:3 9.172053e-05 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001316007 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0001316007 +6 mux_tree_tapbuf_size10_0_sram[3]:6 7.216739e-05 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0001008221 +8 mux_tree_tapbuf_size10_0_sram[3]:8 6.230437e-05 +9 mux_tree_tapbuf_size10_0_sram[3]:9 0.0006786555 +10 mux_tree_tapbuf_size10_0_sram[3]:10 0.0006786555 +11 mux_tree_tapbuf_size10_0_sram[3]:11 0.0001663697 +12 mux_tree_tapbuf_size10_0_sram[3]:12 0.0001663697 +13 mux_tree_tapbuf_size10_0_sram[3]:5 chanx_right_in[10]:16 5.676864e-06 +14 mux_tree_tapbuf_size10_0_sram[3]:4 chanx_right_in[10]:15 5.676864e-06 +15 mux_tree_tapbuf_size10_0_sram[3]:9 chanx_right_in[10]:15 6.689149e-05 +16 mux_tree_tapbuf_size10_0_sram[3]:9 chanx_right_in[10]:16 0.0001312768 +17 mux_tree_tapbuf_size10_0_sram[3]:10 chanx_right_in[10]:6 6.689149e-05 +18 mux_tree_tapbuf_size10_0_sram[3]:10 chanx_right_in[10]:15 0.0001312768 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:12 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:6 mux_tree_tapbuf_size10_0_sram[3]:5 0.0045 +2 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.002348214 +3 mux_tree_tapbuf_size10_0_sram[3]:3 mux_bottom_ipin_0\/mux_l4_in_0_:S 0.0009709822 +4 mux_tree_tapbuf_size10_0_sram[3]:4 mux_tree_tapbuf_size10_0_sram[3]:3 0.0045 +5 mux_tree_tapbuf_size10_0_sram[3]:8 mem_bottom_ipin_0\/FTB_1__40:A 0.152 +6 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.0003035715 +7 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.0045 +8 mux_tree_tapbuf_size10_0_sram[3]:11 mux_tree_tapbuf_size10_0_sram[3]:10 0.0045 +9 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.0141875 +10 mux_tree_tapbuf_size10_0_sram[3]:12 mux_tree_tapbuf_size10_0_sram[3]:11 0.002252232 +11 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.0007812501 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000540566 //LENGTH 4.040 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_1_:X O *L 0 *C 82.515 34.680 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 83.065 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.065 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 83.260 37.060 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 83.260 37.015 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 83.260 34.725 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 83.215 34.680 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 82.553 34.680 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.621899e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.036344e-05 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001481215 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001481215 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.287032e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.287032e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_1_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001059783 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001656542 //LENGTH 14.860 LUMPCC 0.0004522806 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_2_:X O *L 0 *C 65.495 28.220 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 64.765 41.820 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 64.765 41.820 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 64.860 41.775 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 64.860 28.265 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 64.905 28.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 65.458 28.220 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.770238e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0005256088 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0005256088 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.167051e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.167051e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[10]:15 5.968077e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[10]:6 5.968077e-05 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001664595 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001664595 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_2_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0120625 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004933036 + +*END + +*D_NET ropt_net_222 0.001012036 //LENGTH 7.995 LUMPCC 9.48159e-05 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 94.300 46.920 +*I ropt_mt_inst_817:A I *L 0.001766 *C 97.825 50.320 +*N ropt_net_222:2 *C 97.825 50.320 +*N ropt_net_222:3 *C 97.980 50.320 +*N ropt_net_222:4 *C 97.980 50.275 +*N ropt_net_222:5 *C 97.980 46.965 +*N ropt_net_222:6 *C 97.935 46.920 +*N ropt_net_222:7 *C 94.338 46.920 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 ropt_mt_inst_817:A 1e-06 +2 ropt_net_222:2 5.756428e-05 +3 ropt_net_222:3 5.893005e-05 +4 ropt_net_222:4 0.0001483798 +5 ropt_net_222:5 0.0001483798 +6 ropt_net_222:6 0.0002509833 +7 ropt_net_222:7 0.0002509833 +8 ropt_net_222:4 ropt_net_195:5 4.740795e-05 +9 ropt_net_222:5 ropt_net_195:4 4.740795e-05 + +*RES +0 ropt_mt_inst_759:X ropt_net_222:7 0.152 +1 ropt_net_222:2 ropt_mt_inst_817:A 0.152 +2 ropt_net_222:3 ropt_net_222:2 8.423914e-05 +3 ropt_net_222:4 ropt_net_222:3 0.0045 +4 ropt_net_222:6 ropt_net_222:5 0.0045 +5 ropt_net_222:5 ropt_net_222:4 0.002955357 +6 ropt_net_222:7 ropt_net_222:6 0.003212054 + +*END + +*D_NET ropt_net_226 0.0007291913 //LENGTH 4.435 LUMPCC 0.0004007543 DR + +*CONN +*I ropt_mt_inst_767:X O *L 0 *C 94.300 12.580 +*I ropt_mt_inst_821:A I *L 0.001766 *C 97.825 12.240 +*N ropt_net_226:2 *C 97.788 12.240 +*N ropt_net_226:3 *C 97.060 12.240 +*N ropt_net_226:4 *C 97.060 12.580 +*N ropt_net_226:5 *C 94.338 12.580 + +*CAP +0 ropt_mt_inst_767:X 1e-06 +1 ropt_mt_inst_821:A 1e-06 +2 ropt_net_226:2 6.070807e-05 +3 ropt_net_226:3 8.708588e-05 +4 ropt_net_226:4 0.0001025105 +5 ropt_net_226:5 7.613264e-05 +6 ropt_net_226:5 chanx_left_in[18]:2 9.860038e-05 +7 ropt_net_226:4 chanx_left_in[18]:3 9.860038e-05 +8 ropt_net_226:2 chanx_right_in[6]:7 4.185758e-06 +9 ropt_net_226:5 chanx_right_in[6]:6 9.759104e-05 +10 ropt_net_226:4 chanx_right_in[6]:7 9.759104e-05 +11 ropt_net_226:3 chanx_right_in[6]:6 4.185758e-06 + +*RES +0 ropt_mt_inst_767:X ropt_net_226:5 0.152 +1 ropt_net_226:2 ropt_mt_inst_821:A 0.152 +2 ropt_net_226:5 ropt_net_226:4 0.002430804 +3 ropt_net_226:4 ropt_net_226:3 0.0003035715 +4 ropt_net_226:3 ropt_net_226:2 0.0006495535 + +*END + +*D_NET ropt_net_216 0.0004930867 //LENGTH 4.420 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 4.140 18.020 +*I ropt_mt_inst_811:A I *L 0.001766 *C 7.820 17.680 +*N ropt_net_216:2 *C 7.783 17.680 +*N ropt_net_216:3 *C 4.140 17.680 +*N ropt_net_216:4 *C 4.140 18.020 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 ropt_mt_inst_811:A 1e-06 +2 ropt_net_216:2 0.0002045855 +3 ropt_net_216:3 0.0002318589 +4 ropt_net_216:4 5.464227e-05 + +*RES +0 ropt_mt_inst_775:X ropt_net_216:4 0.152 +1 ropt_net_216:2 ropt_mt_inst_811:A 0.152 +2 ropt_net_216:4 ropt_net_216:3 0.0003035715 +3 ropt_net_216:3 ropt_net_216:2 0.003252232 + +*END + +*D_NET ropt_net_219 0.0003844519 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 4.140 56.440 +*I ropt_mt_inst_814:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_219:2 *C 3.258 58.480 +*N ropt_net_219:3 *C 4.095 58.480 +*N ropt_net_219:4 *C 4.140 58.435 +*N ropt_net_219:5 *C 4.140 56.485 +*N ropt_net_219:6 *C 4.140 56.440 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 ropt_mt_inst_814:A 1e-06 +2 ropt_net_219:2 6.059797e-05 +3 ropt_net_219:3 6.059797e-05 +4 ropt_net_219:4 0.0001156867 +5 ropt_net_219:5 0.0001156867 +6 ropt_net_219:6 2.988258e-05 + +*RES +0 ropt_mt_inst_778:X ropt_net_219:6 0.152 +1 ropt_net_219:2 ropt_mt_inst_814:A 0.152 +2 ropt_net_219:3 ropt_net_219:2 0.0007477679 +3 ropt_net_219:4 ropt_net_219:3 0.0045 +4 ropt_net_219:6 ropt_net_219:5 0.0045 +5 ropt_net_219:5 ropt_net_219:4 0.001741071 + +*END + +*D_NET ropt_net_230 0.001286746 //LENGTH 10.535 LUMPCC 0.0004330058 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 94.300 68.680 +*I ropt_mt_inst_825:A I *L 0.001766 *C 97.825 66.640 +*N ropt_net_230:2 *C 97.863 66.640 +*N ropt_net_230:3 *C 99.775 66.640 +*N ropt_net_230:4 *C 99.820 66.685 +*N ropt_net_230:5 *C 99.820 68.623 +*N ropt_net_230:6 *C 99.812 68.680 +*N ropt_net_230:7 *C 94.308 68.680 +*N ropt_net_230:8 *C 94.300 68.680 +*N ropt_net_230:9 *C 94.300 68.680 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 ropt_mt_inst_825:A 1e-06 +2 ropt_net_230:2 8.196315e-05 +3 ropt_net_230:3 8.196315e-05 +4 ropt_net_230:4 0.000118843 +5 ropt_net_230:5 0.000118843 +6 ropt_net_230:6 0.0001919808 +7 ropt_net_230:7 0.0001919808 +8 ropt_net_230:8 3.591844e-05 +9 ropt_net_230:9 3.024803e-05 +10 ropt_net_230:4 chanx_right_in[1]:17 4.218045e-06 +11 ropt_net_230:5 chanx_right_in[1]:18 4.218045e-06 +12 ropt_net_230:6 chanx_right_in[1] 2.031838e-05 +13 ropt_net_230:6 chanx_right_in[1]:16 2.146058e-05 +14 ropt_net_230:7 chanx_right_in[1]:15 2.146058e-05 +15 ropt_net_230:7 chanx_right_in[1]:19 2.031838e-05 +16 ropt_net_230:6 chanx_right_in[10] 9.335806e-05 +17 ropt_net_230:7 chanx_right_in[10]:19 9.335806e-05 +18 ropt_net_230:2 chanx_right_in[11]:16 7.714784e-05 +19 ropt_net_230:3 chanx_right_in[11]:17 7.714784e-05 + +*RES +0 ropt_mt_inst_783:X ropt_net_230:9 0.152 +1 ropt_net_230:2 ropt_mt_inst_825:A 0.152 +2 ropt_net_230:3 ropt_net_230:2 0.001707589 +3 ropt_net_230:4 ropt_net_230:3 0.0045 +4 ropt_net_230:5 ropt_net_230:4 0.001729911 +5 ropt_net_230:6 ropt_net_230:5 0.00341 +6 ropt_net_230:8 ropt_net_230:7 0.00341 +7 ropt_net_230:7 ropt_net_230:6 0.00086245 +8 ropt_net_230:9 ropt_net_230:8 0.0045 + +*END + +*D_NET ropt_net_214 0.0009519945 //LENGTH 7.250 LUMPCC 0.0001198798 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 101.855 45.560 +*I ropt_mt_inst_809:A I *L 0.001767 *C 97.825 47.600 +*N ropt_net_214:2 *C 97.863 47.600 +*N ropt_net_214:3 *C 102.075 47.600 +*N ropt_net_214:4 *C 102.120 47.555 +*N ropt_net_214:5 *C 102.120 45.605 +*N ropt_net_214:6 *C 102.120 45.560 +*N ropt_net_214:7 *C 101.855 45.560 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 ropt_mt_inst_809:A 1e-06 +2 ropt_net_214:2 0.0002667771 +3 ropt_net_214:3 0.0002667771 +4 ropt_net_214:4 9.006493e-05 +5 ropt_net_214:5 9.006493e-05 +6 ropt_net_214:6 5.303352e-05 +7 ropt_net_214:7 6.339713e-05 +8 ropt_net_214:5 chanx_right_out[7]:3 5.993992e-05 +9 ropt_net_214:4 chanx_right_out[7]:4 5.993992e-05 + +*RES +0 ropt_mt_inst_790:X ropt_net_214:7 0.152 +1 ropt_net_214:7 ropt_net_214:6 0.0001440218 +2 ropt_net_214:6 ropt_net_214:5 0.0045 +3 ropt_net_214:5 ropt_net_214:4 0.001741072 +4 ropt_net_214:3 ropt_net_214:2 0.003761161 +5 ropt_net_214:4 ropt_net_214:3 0.0045 +6 ropt_net_214:2 ropt_mt_inst_809:A 0.152 + +*END + +*D_NET chanx_left_out[9] 0.0006358143 //LENGTH 4.745 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_803:X O *L 0 *C 4.140 9.180 +*P chanx_left_out[9] O *L 0.7423 *C 1.230 8.160 +*N chanx_left_out[9]:2 *C 1.833 8.160 +*N chanx_left_out[9]:3 *C 1.840 8.218 +*N chanx_left_out[9]:4 *C 1.840 9.135 +*N chanx_left_out[9]:5 *C 1.885 9.180 +*N chanx_left_out[9]:6 *C 4.103 9.180 + +*CAP +0 ropt_mt_inst_803:X 1e-06 +1 chanx_left_out[9] 8.030651e-05 +2 chanx_left_out[9]:2 8.030651e-05 +3 chanx_left_out[9]:3 6.858981e-05 +4 chanx_left_out[9]:4 6.858981e-05 +5 chanx_left_out[9]:5 0.0001685108 +6 chanx_left_out[9]:6 0.0001685108 + +*RES +0 ropt_mt_inst_803:X chanx_left_out[9]:6 0.152 +1 chanx_left_out[9]:6 chanx_left_out[9]:5 0.001979911 +2 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +3 chanx_left_out[9]:4 chanx_left_out[9]:3 0.0008191965 +4 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +5 chanx_left_out[9]:2 chanx_left_out[9] 9.439166e-05 + +*END + +*D_NET chanx_left_out[5] 0.001575952 //LENGTH 11.960 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 11.695 36.040 +*P chanx_left_out[5] O *L 0.7423 *C 1.230 35.360 +*N chanx_left_out[5]:2 *C 11.033 35.360 +*N chanx_left_out[5]:3 *C 11.040 35.418 +*N chanx_left_out[5]:4 *C 11.040 35.995 +*N chanx_left_out[5]:5 *C 11.085 36.040 +*N chanx_left_out[5]:6 *C 11.658 36.040 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chanx_left_out[5] 0.0006674884 +2 chanx_left_out[5]:2 0.0006674884 +3 chanx_left_out[5]:3 6.252615e-05 +4 chanx_left_out[5]:4 6.252615e-05 +5 chanx_left_out[5]:5 5.746134e-05 +6 chanx_left_out[5]:6 5.746134e-05 + +*RES +0 ropt_mt_inst_810:X chanx_left_out[5]:6 0.152 +1 chanx_left_out[5]:6 chanx_left_out[5]:5 0.0005111608 +2 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +3 chanx_left_out[5]:4 chanx_left_out[5]:3 0.000515625 +4 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +5 chanx_left_out[5]:2 chanx_left_out[5] 0.001535725 + +*END + +*D_NET chanx_left_out[7] 0.001305591 //LENGTH 7.405 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 7.095 22.440 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 23.120 +*N chanx_left_out[7]:2 *C 1.840 23.120 +*N chanx_left_out[7]:3 *C 1.840 22.440 +*N chanx_left_out[7]:4 *C 6.893 22.440 +*N chanx_left_out[7]:5 *C 6.900 22.440 +*N chanx_left_out[7]:6 *C 6.900 22.440 +*N chanx_left_out[7]:7 *C 7.095 22.440 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 chanx_left_out[7] 8.682503e-05 +2 chanx_left_out[7]:2 0.0001405698 +3 chanx_left_out[7]:3 0.0004915654 +4 chanx_left_out[7]:4 0.0004378207 +5 chanx_left_out[7]:5 3.249462e-05 +6 chanx_left_out[7]:6 5.719678e-05 +7 chanx_left_out[7]:7 5.811871e-05 + +*RES +0 ropt_mt_inst_819:X chanx_left_out[7]:7 0.152 +1 chanx_left_out[7]:7 chanx_left_out[7]:6 0.0001059783 +2 chanx_left_out[7]:6 chanx_left_out[7]:5 0.0045 +3 chanx_left_out[7]:5 chanx_left_out[7]:4 0.00341 +4 chanx_left_out[7]:4 chanx_left_out[7]:3 0.0007915584 +5 chanx_left_out[7]:2 chanx_left_out[7] 9.556666e-05 +6 chanx_left_out[7]:3 chanx_left_out[7]:2 0.0001065333 + +*END + +*D_NET ropt_net_175 0.002225584 //LENGTH 18.900 LUMPCC 0.0004107481 DR + +*CONN +*I BUFT_RR_77:X O *L 0 *C 15.640 25.840 +*I ropt_mt_inst_770:A I *L 0.001766 *C 7.820 31.280 +*N ropt_net_175:2 *C 7.820 31.280 +*N ropt_net_175:3 *C 7.820 30.940 +*N ropt_net_175:4 *C 5.565 30.940 +*N ropt_net_175:5 *C 5.520 30.895 +*N ropt_net_175:6 *C 5.520 25.885 +*N ropt_net_175:7 *C 5.565 25.840 +*N ropt_net_175:8 *C 15.603 25.840 + +*CAP +0 BUFT_RR_77:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_175:2 6.388412e-05 +3 ropt_net_175:3 0.0001419875 +4 ropt_net_175:4 0.0001110141 +5 ropt_net_175:5 0.0002239392 +6 ropt_net_175:6 0.0002239392 +7 ropt_net_175:7 0.0005240362 +8 ropt_net_175:8 0.0005240362 +9 ropt_net_175:6 chanx_left_in[2]:18 9.74599e-05 +10 ropt_net_175:5 chanx_left_in[2]:17 9.74599e-05 +11 ropt_net_175:8 chanx_right_in[9]:7 6.597977e-05 +12 ropt_net_175:7 chanx_right_in[9]:6 6.597977e-05 +13 ropt_net_175:4 ropt_net_207:3 4.193439e-05 +14 ropt_net_175:3 ropt_net_207:4 4.193439e-05 + +*RES +0 BUFT_RR_77:X ropt_net_175:8 0.152 +1 ropt_net_175:8 ropt_net_175:7 0.008962054 +2 ropt_net_175:7 ropt_net_175:6 0.0045 +3 ropt_net_175:6 ropt_net_175:5 0.004473215 +4 ropt_net_175:4 ropt_net_175:3 0.002013393 +5 ropt_net_175:5 ropt_net_175:4 0.0045 +6 ropt_net_175:2 ropt_mt_inst_770:A 0.152 +7 ropt_net_175:3 ropt_net_175:2 0.0003035715 + +*END + +*D_NET ropt_net_198 0.001813399 //LENGTH 16.225 LUMPCC 0.000180213 DR + +*CONN +*I BUFT_P_141:X O *L 0 *C 97.060 28.900 +*I ropt_mt_inst_793:A I *L 0.001766 *C 97.825 39.440 +*N ropt_net_198:2 *C 97.863 39.440 +*N ropt_net_198:3 *C 99.775 39.440 +*N ropt_net_198:4 *C 99.820 39.395 +*N ropt_net_198:5 *C 99.820 28.945 +*N ropt_net_198:6 *C 99.775 28.900 +*N ropt_net_198:7 *C 97.098 28.900 + +*CAP +0 BUFT_P_141:X 1e-06 +1 ropt_mt_inst_793:A 1e-06 +2 ropt_net_198:2 0.0001333157 +3 ropt_net_198:3 0.0001333157 +4 ropt_net_198:4 0.0005526507 +5 ropt_net_198:5 0.0005526507 +6 ropt_net_198:6 0.0001296266 +7 ropt_net_198:7 0.0001296266 +8 ropt_net_198:7 ropt_net_205:2 8.611302e-05 +9 ropt_net_198:6 ropt_net_205:3 8.611302e-05 +10 ropt_net_198:5 ropt_net_205:4 3.993491e-06 +11 ropt_net_198:4 ropt_net_205:5 3.993491e-06 + +*RES +0 BUFT_P_141:X ropt_net_198:7 0.152 +1 ropt_net_198:7 ropt_net_198:6 0.002390625 +2 ropt_net_198:6 ropt_net_198:5 0.0045 +3 ropt_net_198:5 ropt_net_198:4 0.009330357 +4 ropt_net_198:3 ropt_net_198:2 0.001707589 +5 ropt_net_198:4 ropt_net_198:3 0.0045 +6 ropt_net_198:2 ropt_mt_inst_793:A 0.152 + +*END + +*D_NET chanx_left_in[3] 0.01218373 //LENGTH 106.055 LUMPCC 0.002133425 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 55.760 +*I BUFT_RR_45:A I *L 0.001767 *C 93.380 44.880 +*N chanx_left_in[3]:2 *C 93.380 44.880 +*N chanx_left_in[3]:3 *C 93.380 44.540 +*N chanx_left_in[3]:4 *C 63.480 44.540 +*N chanx_left_in[3]:5 *C 63.480 44.880 +*N chanx_left_in[3]:6 *C 42.365 44.880 +*N chanx_left_in[3]:7 *C 42.320 44.925 +*N chanx_left_in[3]:8 *C 42.320 47.215 +*N chanx_left_in[3]:9 *C 42.275 47.260 +*N chanx_left_in[3]:10 *C 16.145 47.260 +*N chanx_left_in[3]:11 *C 16.100 47.305 +*N chanx_left_in[3]:12 *C 16.100 55.703 +*N chanx_left_in[3]:13 *C 16.093 55.760 + +*CAP +0 chanx_left_in[3] 0.0006243191 +1 BUFT_RR_45:A 1e-06 +2 chanx_left_in[3]:2 5.846423e-05 +3 chanx_left_in[3]:3 0.001436241 +4 chanx_left_in[3]:4 0.001434778 +5 chanx_left_in[3]:5 0.001125051 +6 chanx_left_in[3]:6 0.001098054 +7 chanx_left_in[3]:7 0.000164905 +8 chanx_left_in[3]:8 0.000164905 +9 chanx_left_in[3]:9 0.001244648 +10 chanx_left_in[3]:10 0.001244648 +11 chanx_left_in[3]:11 0.0004144862 +12 chanx_left_in[3]:12 0.0004144862 +13 chanx_left_in[3]:13 0.0006243191 +14 chanx_left_in[3] chanx_left_in[6] 0.0003347809 +15 chanx_left_in[3]:11 chanx_left_in[6]:10 5.970903e-05 +16 chanx_left_in[3]:12 chanx_left_in[6]:11 5.970903e-05 +17 chanx_left_in[3]:13 chanx_left_in[6]:12 0.0003347809 +18 chanx_left_in[3]:9 chanx_right_in[12]:9 0.0002897068 +19 chanx_left_in[3]:10 chanx_right_in[12]:8 0.0002897068 +20 chanx_left_in[3]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002608155 +21 chanx_left_in[3]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002608155 +22 chanx_left_in[3]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001217004 +23 chanx_left_in[3]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001217004 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:13 0.002328458 +1 chanx_left_in[3]:2 BUFT_RR_45:A 0.152 +2 chanx_left_in[3]:6 chanx_left_in[3]:5 0.01885268 +3 chanx_left_in[3]:7 chanx_left_in[3]:6 0.0045 +4 chanx_left_in[3]:9 chanx_left_in[3]:8 0.0045 +5 chanx_left_in[3]:8 chanx_left_in[3]:7 0.002044643 +6 chanx_left_in[3]:10 chanx_left_in[3]:9 0.02333036 +7 chanx_left_in[3]:11 chanx_left_in[3]:10 0.0045 +8 chanx_left_in[3]:12 chanx_left_in[3]:11 0.007497768 +9 chanx_left_in[3]:13 chanx_left_in[3]:12 0.00341 +10 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0003035714 +11 chanx_left_in[3]:4 chanx_left_in[3]:3 0.02669643 +12 chanx_left_in[3]:3 chanx_left_in[3]:2 0.0003035715 + +*END + +*D_NET chanx_right_in[6] 0.008097298 //LENGTH 71.465 LUMPCC 0.001089386 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 103.650 16.320 +*I FTB_27__26:A I *L 0.001776 *C 37.720 12.240 +*N chanx_right_in[6]:2 *C 37.758 12.240 +*N chanx_right_in[6]:3 *C 83.675 12.240 +*N chanx_right_in[6]:4 *C 83.720 12.285 +*N chanx_right_in[6]:5 *C 83.720 12.875 +*N chanx_right_in[6]:6 *C 83.765 12.920 +*N chanx_right_in[6]:7 *C 98.395 12.920 +*N chanx_right_in[6]:8 *C 98.440 12.965 +*N chanx_right_in[6]:9 *C 98.440 16.262 +*N chanx_right_in[6]:10 *C 98.448 16.320 + +*CAP +0 chanx_right_in[6] 0.0003814972 +1 FTB_27__26:A 1e-06 +2 chanx_right_in[6]:2 0.002102383 +3 chanx_right_in[6]:3 0.002102383 +4 chanx_right_in[6]:4 5.214848e-05 +5 chanx_right_in[6]:5 5.214848e-05 +6 chanx_right_in[6]:6 0.0007948691 +7 chanx_right_in[6]:7 0.0007948691 +8 chanx_right_in[6]:8 0.0001725589 +9 chanx_right_in[6]:9 0.0001725589 +10 chanx_right_in[6]:10 0.0003814972 +11 chanx_right_in[6]:6 ropt_net_226:5 9.759104e-05 +12 chanx_right_in[6]:6 ropt_net_226:3 4.185758e-06 +13 chanx_right_in[6]:7 ropt_net_226:2 4.185758e-06 +14 chanx_right_in[6]:7 ropt_net_226:4 9.759104e-05 +15 chanx_right_in[6]:2 BUF_net_52:5 0.0002083964 +16 chanx_right_in[6]:3 BUF_net_52:4 0.0002083964 +17 chanx_right_in[6]:6 BUF_net_52:5 0.0001872432 +18 chanx_right_in[6]:6 BUF_net_52:3 2.661443e-06 +19 chanx_right_in[6]:7 BUF_net_52:2 2.661443e-06 +20 chanx_right_in[6]:7 BUF_net_52:4 0.0001872432 +21 chanx_right_in[6]:8 ropt_net_200:4 4.461499e-05 +22 chanx_right_in[6]:9 ropt_net_200:5 4.461499e-05 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:10 0.0008150583 +1 chanx_right_in[6]:2 FTB_27__26:A 0.152 +2 chanx_right_in[6]:3 chanx_right_in[6]:2 0.04099777 +3 chanx_right_in[6]:4 chanx_right_in[6]:3 0.0045 +4 chanx_right_in[6]:6 chanx_right_in[6]:5 0.0045 +5 chanx_right_in[6]:5 chanx_right_in[6]:4 0.0005267857 +6 chanx_right_in[6]:7 chanx_right_in[6]:6 0.0130625 +7 chanx_right_in[6]:8 chanx_right_in[6]:7 0.0045 +8 chanx_right_in[6]:9 chanx_right_in[6]:8 0.002944197 +9 chanx_right_in[6]:10 chanx_right_in[6]:9 0.00341 + +*END + +*D_NET chanx_right_in[7] 0.01664264 //LENGTH 107.425 LUMPCC 0.009514028 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 103.650 20.400 +*I ropt_mt_inst_773:A I *L 0.001767 *C 3.220 25.840 +*N chanx_right_in[7]:2 *C 3.243 25.812 +*N chanx_right_in[7]:3 *C 3.255 25.500 +*N chanx_right_in[7]:4 *C 5.935 25.500 +*N chanx_right_in[7]:5 *C 5.980 25.455 +*N chanx_right_in[7]:6 *C 5.980 23.178 +*N chanx_right_in[7]:7 *C 5.988 23.120 +*N chanx_right_in[7]:8 *C 28.520 23.120 +*N chanx_right_in[7]:9 *C 28.520 20.400 +*N chanx_right_in[7]:10 *C 78.370 20.400 + +*CAP +0 chanx_right_in[7] 0.0009505773 +1 ropt_mt_inst_773:A 1e-06 +2 chanx_right_in[7]:2 2.933503e-05 +3 chanx_right_in[7]:3 0.0001728333 +4 chanx_right_in[7]:4 0.0001434983 +5 chanx_right_in[7]:5 0.000116964 +6 chanx_right_in[7]:6 0.000116964 +7 chanx_right_in[7]:7 0.0007325222 +8 chanx_right_in[7]:8 0.0009012683 +9 chanx_right_in[7]:9 0.001590909 +10 chanx_right_in[7]:10 0.00237274 +11 chanx_right_in[7] chanx_left_in[1]:6 0.0006819558 +12 chanx_right_in[7]:7 chanx_left_in[1] 0.0002368138 +13 chanx_right_in[7]:7 chanx_left_in[1]:8 8.145457e-07 +14 chanx_right_in[7]:8 chanx_left_in[1]:7 8.145457e-07 +15 chanx_right_in[7]:8 chanx_left_in[1]:9 0.0002478151 +16 chanx_right_in[7]:9 chanx_left_in[1]:7 5.31479e-05 +17 chanx_right_in[7]:9 chanx_left_in[1]:8 0.002801601 +18 chanx_right_in[7]:10 chanx_left_in[1]:6 5.31479e-05 +19 chanx_right_in[7]:10 chanx_left_in[1]:7 0.003472555 +20 chanx_right_in[7]:7 chanx_left_in[10] 0.0002019991 +21 chanx_right_in[7]:7 chanx_left_in[10]:14 0.000218558 +22 chanx_right_in[7]:8 chanx_left_in[10]:13 0.000218558 +23 chanx_right_in[7]:8 chanx_left_in[10]:15 0.0002019991 +24 chanx_right_in[7]:9 chanx_left_in[10]:9 5.569883e-06 +25 chanx_right_in[7]:9 chanx_left_in[10]:13 2.72582e-05 +26 chanx_right_in[7]:9 chanx_left_in[10]:14 0.0001718976 +27 chanx_right_in[7]:10 chanx_left_in[10]:7 5.569883e-06 +28 chanx_right_in[7]:10 chanx_left_in[10]:12 2.72582e-05 +29 chanx_right_in[7]:10 chanx_left_in[10]:13 0.0001718976 +30 chanx_right_in[7] chanx_right_in[3] 0.0002534422 +31 chanx_right_in[7]:10 chanx_right_in[3]:23 0.0002534422 +32 chanx_right_in[7]:4 ropt_net_224:6 7.19902e-05 +33 chanx_right_in[7]:5 ropt_net_224:5 3.196619e-05 +34 chanx_right_in[7]:6 ropt_net_224:4 3.196619e-05 +35 chanx_right_in[7]:3 ropt_net_224:7 7.19902e-05 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:10 0.003960533 +1 chanx_right_in[7]:2 ropt_mt_inst_773:A 0.152 +2 chanx_right_in[7]:4 chanx_right_in[7]:3 0.002392857 +3 chanx_right_in[7]:5 chanx_right_in[7]:4 0.0045 +4 chanx_right_in[7]:6 chanx_right_in[7]:5 0.002033482 +5 chanx_right_in[7]:7 chanx_right_in[7]:6 0.00341 +6 chanx_right_in[7]:3 chanx_right_in[7]:2 0.0002111487 +7 chanx_right_in[7]:8 chanx_right_in[7]:7 0.003530091 +8 chanx_right_in[7]:9 chanx_right_in[7]:8 0.0004261333 +9 chanx_right_in[7]:10 chanx_right_in[7]:9 0.007809832 + +*END + +*D_NET chanx_right_in[10] 0.01571207 //LENGTH 150.080 LUMPCC 0.0008666368 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 103.650 70.720 +*I ropt_mt_inst_778:A I *L 0.001767 *C 3.220 55.760 +*I mux_bottom_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 67.160 28.900 +*N chanx_right_in[10]:3 *C 67.160 28.900 +*N chanx_right_in[10]:4 *C 67.160 28.560 +*N chanx_right_in[10]:5 *C 66.745 28.560 +*N chanx_right_in[10]:6 *C 66.700 28.605 +*N chanx_right_in[10]:7 *C 3.243 55.733 +*N chanx_right_in[10]:8 *C 3.255 55.420 +*N chanx_right_in[10]:9 *C 10.535 55.420 +*N chanx_right_in[10]:10 *C 10.580 55.375 +*N chanx_right_in[10]:11 *C 10.580 53.085 +*N chanx_right_in[10]:12 *C 10.625 53.040 +*N chanx_right_in[10]:13 *C 60.420 53.040 +*N chanx_right_in[10]:14 *C 66.655 53.040 +*N chanx_right_in[10]:15 *C 66.700 53.040 +*N chanx_right_in[10]:16 *C 66.700 71.343 +*N chanx_right_in[10]:17 *C 66.708 71.400 +*N chanx_right_in[10]:18 *C 92.000 71.400 +*N chanx_right_in[10]:19 *C 92.000 70.720 + +*CAP +0 chanx_right_in[10] 0.0005746555 +1 ropt_mt_inst_778:A 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_2_:A1 1e-06 +3 chanx_right_in[10]:3 5.573397e-05 +4 chanx_right_in[10]:4 7.727934e-05 +5 chanx_right_in[10]:5 4.982232e-05 +6 chanx_right_in[10]:6 0.001258577 +7 chanx_right_in[10]:7 3.080053e-05 +8 chanx_right_in[10]:8 0.0004176615 +9 chanx_right_in[10]:9 0.0003868609 +10 chanx_right_in[10]:10 0.0001133487 +11 chanx_right_in[10]:11 0.0001133487 +12 chanx_right_in[10]:12 0.002465711 +13 chanx_right_in[10]:13 0.002788853 +14 chanx_right_in[10]:14 0.0003231423 +15 chanx_right_in[10]:15 0.0020946 +16 chanx_right_in[10]:16 0.0008091026 +17 chanx_right_in[10]:17 0.001307772 +18 chanx_right_in[10]:18 0.001354641 +19 chanx_right_in[10]:19 0.0006215243 +20 chanx_right_in[10]:16 mux_tree_tapbuf_size10_0_sram[3]:5 5.676864e-06 +21 chanx_right_in[10]:16 mux_tree_tapbuf_size10_0_sram[3]:9 0.0001312768 +22 chanx_right_in[10]:6 mux_tree_tapbuf_size10_0_sram[3]:10 6.689149e-05 +23 chanx_right_in[10]:15 mux_tree_tapbuf_size10_0_sram[3]:4 5.676864e-06 +24 chanx_right_in[10]:15 mux_tree_tapbuf_size10_0_sram[3]:9 6.689149e-05 +25 chanx_right_in[10]:15 mux_tree_tapbuf_size10_0_sram[3]:10 0.0001312768 +26 chanx_right_in[10]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.968077e-05 +27 chanx_right_in[10]:15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.968077e-05 +28 chanx_right_in[10] ropt_net_230:6 9.335806e-05 +29 chanx_right_in[10]:19 ropt_net_230:7 9.335806e-05 +30 chanx_right_in[10]:11 ropt_net_167:4 3.01324e-05 +31 chanx_right_in[10]:9 ropt_net_167:7 4.630196e-05 +32 chanx_right_in[10]:10 ropt_net_167:5 3.01324e-05 +33 chanx_right_in[10]:8 ropt_net_167:6 4.630196e-05 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:19 0.001825167 +1 chanx_right_in[10]:16 chanx_right_in[10]:15 0.01634152 +2 chanx_right_in[10]:17 chanx_right_in[10]:16 0.00341 +3 chanx_right_in[10]:5 chanx_right_in[10]:4 0.0003705357 +4 chanx_right_in[10]:6 chanx_right_in[10]:5 0.0045 +5 chanx_right_in[10]:3 mux_bottom_ipin_0\/mux_l2_in_2_:A1 0.152 +6 chanx_right_in[10]:14 chanx_right_in[10]:13 0.005566965 +7 chanx_right_in[10]:15 chanx_right_in[10]:14 0.0045 +8 chanx_right_in[10]:15 chanx_right_in[10]:6 0.02181697 +9 chanx_right_in[10]:12 chanx_right_in[10]:11 0.0045 +10 chanx_right_in[10]:11 chanx_right_in[10]:10 0.002044643 +11 chanx_right_in[10]:9 chanx_right_in[10]:8 0.0065 +12 chanx_right_in[10]:10 chanx_right_in[10]:9 0.0045 +13 chanx_right_in[10]:7 ropt_mt_inst_778:A 0.152 +14 chanx_right_in[10]:8 chanx_right_in[10]:7 0.0002111487 +15 chanx_right_in[10]:4 chanx_right_in[10]:3 0.0003035715 +16 chanx_right_in[10]:18 chanx_right_in[10]:17 0.003962491 +17 chanx_right_in[10]:19 chanx_right_in[10]:18 0.0001065333 +18 chanx_right_in[10]:13 chanx_right_in[10]:12 0.04445982 + +*END + +*D_NET chanx_right_in[14] 0.0148745 //LENGTH 115.280 LUMPCC 0.006489587 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 103.650 42.160 +*I BUFT_P_122:A I *L 0.001766 *C 22.540 12.240 +*N chanx_right_in[14]:2 *C 22.578 12.240 +*N chanx_right_in[14]:3 *C 23.920 12.240 +*N chanx_right_in[14]:4 *C 23.920 11.900 +*N chanx_right_in[14]:5 *C 32.155 11.900 +*N chanx_right_in[14]:6 *C 32.200 11.945 +*N chanx_right_in[14]:7 *C 32.200 17.975 +*N chanx_right_in[14]:8 *C 32.245 18.020 +*N chanx_right_in[14]:9 *C 47.335 18.020 +*N chanx_right_in[14]:10 *C 47.380 18.065 +*N chanx_right_in[14]:11 *C 47.380 25.455 +*N chanx_right_in[14]:12 *C 47.380 25.500 +*N chanx_right_in[14]:13 *C 47.380 25.840 +*N chanx_right_in[14]:14 *C 47.840 25.840 +*N chanx_right_in[14]:15 *C 47.840 25.500 +*N chanx_right_in[14]:16 *C 49.680 25.500 +*N chanx_right_in[14]:17 *C 49.680 25.840 +*N chanx_right_in[14]:18 *C 49.680 25.885 +*N chanx_right_in[14]:19 *C 49.680 42.102 +*N chanx_right_in[14]:20 *C 49.688 42.160 + +*CAP +0 chanx_right_in[14] 0.001441163 +1 BUFT_P_122:A 1e-06 +2 chanx_right_in[14]:2 0.0001341443 +3 chanx_right_in[14]:3 0.0001550274 +4 chanx_right_in[14]:4 0.0004982349 +5 chanx_right_in[14]:5 0.0004773519 +6 chanx_right_in[14]:6 0.0003026939 +7 chanx_right_in[14]:7 0.0003026939 +8 chanx_right_in[14]:8 0.0005728718 +9 chanx_right_in[14]:9 0.0005728718 +10 chanx_right_in[14]:10 0.0003425469 +11 chanx_right_in[14]:11 0.0003425469 +12 chanx_right_in[14]:12 3.502362e-05 +13 chanx_right_in[14]:13 6.393802e-05 +14 chanx_right_in[14]:14 6.817534e-05 +15 chanx_right_in[14]:15 0.0001376057 +16 chanx_right_in[14]:16 0.0001406214 +17 chanx_right_in[14]:17 4.921483e-05 +18 chanx_right_in[14]:18 0.0006530117 +19 chanx_right_in[14]:19 0.0006530117 +20 chanx_right_in[14]:20 0.001441163 +21 chanx_right_in[14]:11 chanx_left_in[5]:11 5.676325e-05 +22 chanx_right_in[14]:10 chanx_left_in[5]:10 5.676325e-05 +23 chanx_right_in[14]:18 chanx_left_in[5]:10 0.0002074766 +24 chanx_right_in[14]:19 chanx_left_in[5]:11 0.0002074766 +25 chanx_right_in[14] chanx_left_in[15]:13 5.634257e-06 +26 chanx_right_in[14] chanx_left_in[15]:17 0.0007021212 +27 chanx_right_in[14] chanx_left_in[15]:18 0.0008013808 +28 chanx_right_in[14]:20 chanx_left_in[15]:14 5.634257e-06 +29 chanx_right_in[14]:20 chanx_left_in[15]:18 0.0007021212 +30 chanx_right_in[14]:20 chanx_left_in[15]:19 0.0008013808 +31 chanx_right_in[14] chanx_right_in[5] 0.000243884 +32 chanx_right_in[14] chanx_right_in[5]:15 0.0001825824 +33 chanx_right_in[14] chanx_right_in[5]:17 5.357856e-05 +34 chanx_right_in[14] chanx_right_in[5]:19 0.0003478693 +35 chanx_right_in[14]:20 chanx_right_in[5]:14 0.0001825824 +36 chanx_right_in[14]:20 chanx_right_in[5]:16 5.357856e-05 +37 chanx_right_in[14]:20 chanx_right_in[5]:18 0.0003478693 +38 chanx_right_in[14]:20 chanx_right_in[5]:20 0.000243884 +39 chanx_right_in[14]:9 chanx_right_in[16]:16 0.0003079346 +40 chanx_right_in[14]:8 chanx_right_in[16]:15 0.0003079346 +41 chanx_right_in[14] chanx_right_in[18] 0.0001682756 +42 chanx_right_in[14] chanx_right_in[18]:29 0.0001672925 +43 chanx_right_in[14]:20 chanx_right_in[18]:28 0.0001672925 +44 chanx_right_in[14]:20 chanx_right_in[18]:29 0.0001682756 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:20 0.008454124 +1 chanx_right_in[14]:12 chanx_right_in[14]:11 0.0045 +2 chanx_right_in[14]:11 chanx_right_in[14]:10 0.006598215 +3 chanx_right_in[14]:9 chanx_right_in[14]:8 0.01347321 +4 chanx_right_in[14]:10 chanx_right_in[14]:9 0.0045 +5 chanx_right_in[14]:8 chanx_right_in[14]:7 0.0045 +6 chanx_right_in[14]:7 chanx_right_in[14]:6 0.005383929 +7 chanx_right_in[14]:5 chanx_right_in[14]:4 0.007352679 +8 chanx_right_in[14]:6 chanx_right_in[14]:5 0.0045 +9 chanx_right_in[14]:2 BUFT_P_122:A 0.152 +10 chanx_right_in[14]:17 chanx_right_in[14]:16 0.0003035715 +11 chanx_right_in[14]:18 chanx_right_in[14]:17 0.0045 +12 chanx_right_in[14]:19 chanx_right_in[14]:18 0.01447991 +13 chanx_right_in[14]:20 chanx_right_in[14]:19 0.00341 +14 chanx_right_in[14]:3 chanx_right_in[14]:2 0.001198661 +15 chanx_right_in[14]:4 chanx_right_in[14]:3 0.0003035715 +16 chanx_right_in[14]:13 chanx_right_in[14]:12 0.0003035715 +17 chanx_right_in[14]:14 chanx_right_in[14]:13 0.0004107143 +18 chanx_right_in[14]:15 chanx_right_in[14]:14 0.0003035715 +19 chanx_right_in[14]:16 chanx_right_in[14]:15 0.001642857 + +*END + +*D_NET chanx_right_in[17] 0.01569574 //LENGTH 132.080 LUMPCC 0.00142697 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 103.650 63.920 +*I ropt_mt_inst_758:A I *L 0.001767 *C 3.220 36.720 +*N chanx_right_in[17]:2 *C 3.243 36.748 +*N chanx_right_in[17]:3 *C 3.255 37.060 +*N chanx_right_in[17]:4 *C 3.635 37.060 +*N chanx_right_in[17]:5 *C 3.680 37.105 +*N chanx_right_in[17]:6 *C 3.680 45.515 +*N chanx_right_in[17]:7 *C 3.725 45.560 +*N chanx_right_in[17]:8 *C 19.660 45.560 +*N chanx_right_in[17]:9 *C 19.773 45.515 +*N chanx_right_in[17]:10 *C 19.780 44.925 +*N chanx_right_in[17]:11 *C 19.825 44.880 +*N chanx_right_in[17]:12 *C 20.700 44.880 +*N chanx_right_in[17]:13 *C 20.700 45.220 +*N chanx_right_in[17]:14 *C 20.700 45.265 +*N chanx_right_in[17]:15 *C 20.700 50.955 +*N chanx_right_in[17]:16 *C 20.745 51.000 +*N chanx_right_in[17]:17 *C 70.540 51.000 +*N chanx_right_in[17]:18 *C 90.115 51.000 +*N chanx_right_in[17]:19 *C 90.160 51.045 +*N chanx_right_in[17]:20 *C 90.160 63.863 +*N chanx_right_in[17]:21 *C 90.168 63.920 + +*CAP +0 chanx_right_in[17] 0.0005477739 +1 ropt_mt_inst_758:A 1e-06 +2 chanx_right_in[17]:2 2.967882e-05 +3 chanx_right_in[17]:3 4.496299e-05 +4 chanx_right_in[17]:4 1.528418e-05 +5 chanx_right_in[17]:5 0.0004073933 +6 chanx_right_in[17]:6 0.0004073933 +7 chanx_right_in[17]:7 0.000979543 +8 chanx_right_in[17]:8 0.000979543 +9 chanx_right_in[17]:9 4.551453e-05 +10 chanx_right_in[17]:10 4.551453e-05 +11 chanx_right_in[17]:11 6.631538e-05 +12 chanx_right_in[17]:12 9.660724e-05 +13 chanx_right_in[17]:13 5.765883e-05 +14 chanx_right_in[17]:14 0.000299828 +15 chanx_right_in[17]:15 0.000299828 +16 chanx_right_in[17]:16 0.002867037 +17 chanx_right_in[17]:17 0.004016551 +18 chanx_right_in[17]:18 0.001149513 +19 chanx_right_in[17]:19 0.0006820274 +20 chanx_right_in[17]:20 0.0006820274 +21 chanx_right_in[17]:21 0.0005477739 +22 chanx_right_in[17] chanx_right_in[1] 2.662046e-05 +23 chanx_right_in[17] chanx_right_in[1]:16 0.0005202991 +24 chanx_right_in[17]:21 chanx_right_in[1]:15 0.0005202991 +25 chanx_right_in[17]:21 chanx_right_in[1]:19 2.662046e-05 +26 chanx_right_in[17]:18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.003791e-05 +27 chanx_right_in[17]:17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.003791e-05 +28 chanx_right_in[17]:4 ropt_net_220:6 2.611323e-05 +29 chanx_right_in[17]:5 ropt_net_220:4 6.041428e-05 +30 chanx_right_in[17]:6 ropt_net_220:3 6.041428e-05 +31 chanx_right_in[17]:3 ropt_net_220:5 2.611323e-05 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:21 0.002112258 +1 chanx_right_in[17]:2 ropt_mt_inst_758:A 0.152 +2 chanx_right_in[17]:4 chanx_right_in[17]:3 0.0003392857 +3 chanx_right_in[17]:5 chanx_right_in[17]:4 0.0045 +4 chanx_right_in[17]:7 chanx_right_in[17]:6 0.0045 +5 chanx_right_in[17]:6 chanx_right_in[17]:5 0.007508929 +6 chanx_right_in[17]:8 chanx_right_in[17]:7 0.01422768 +7 chanx_right_in[17]:9 chanx_right_in[17]:8 0.0045 +8 chanx_right_in[17]:11 chanx_right_in[17]:10 0.0045 +9 chanx_right_in[17]:10 chanx_right_in[17]:9 0.0005267857 +10 chanx_right_in[17]:13 chanx_right_in[17]:12 0.0001465517 +11 chanx_right_in[17]:14 chanx_right_in[17]:13 0.0045 +12 chanx_right_in[17]:16 chanx_right_in[17]:15 0.0045 +13 chanx_right_in[17]:15 chanx_right_in[17]:14 0.005080358 +14 chanx_right_in[17]:18 chanx_right_in[17]:17 0.01747768 +15 chanx_right_in[17]:19 chanx_right_in[17]:18 0.0045 +16 chanx_right_in[17]:20 chanx_right_in[17]:19 0.0114442 +17 chanx_right_in[17]:21 chanx_right_in[17]:20 0.00341 +18 chanx_right_in[17]:3 chanx_right_in[17]:2 0.0002111487 +19 chanx_right_in[17]:12 chanx_right_in[17]:11 0.0007812501 +20 chanx_right_in[17]:17 chanx_right_in[17]:16 0.04445983 + +*END + +*D_NET prog_clk[0] 0.01676785 //LENGTH 132.762 LUMPCC 0.004852465 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 3.220 1.290 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 54.545 36.720 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 62.365 31.280 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 61.445 47.600 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 75.245 53.040 +*N prog_clk[0]:5 *C 75.245 53.040 +*N prog_clk[0]:6 *C 74.980 53.040 +*N prog_clk[0]:7 *C 74.980 52.995 +*N prog_clk[0]:8 *C 74.980 49.698 +*N prog_clk[0]:9 *C 74.972 49.640 +*N prog_clk[0]:10 *C 61.648 49.640 +*N prog_clk[0]:11 *C 61.640 49.583 +*N prog_clk[0]:12 *C 61.445 47.600 +*N prog_clk[0]:13 *C 61.640 47.940 +*N prog_clk[0]:14 *C 61.640 47.940 +*N prog_clk[0]:15 *C 62.328 31.280 +*N prog_clk[0]:16 *C 61.685 31.280 +*N prog_clk[0]:17 *C 61.640 31.280 +*N prog_clk[0]:18 *C 61.633 31.280 +*N prog_clk[0]:19 *C 54.545 36.720 +*N prog_clk[0]:20 *C 54.740 36.720 +*N prog_clk[0]:21 *C 54.740 36.675 +*N prog_clk[0]:22 *C 54.740 31.338 +*N prog_clk[0]:23 *C 54.740 31.280 +*N prog_clk[0]:24 *C 3.228 31.280 +*N prog_clk[0]:25 *C 3.220 31.223 + +*CAP +0 prog_clk[0] 0.00140623 +1 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +3 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +4 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 prog_clk[0]:5 4.527391e-05 +6 prog_clk[0]:6 4.85099e-05 +7 prog_clk[0]:7 0.0001816342 +8 prog_clk[0]:8 0.0001816342 +9 prog_clk[0]:9 0.0007825472 +10 prog_clk[0]:10 0.0007825472 +11 prog_clk[0]:11 9.761673e-05 +12 prog_clk[0]:12 6.910074e-05 +13 prog_clk[0]:13 6.921952e-05 +14 prog_clk[0]:14 0.001019008 +15 prog_clk[0]:15 5.203729e-05 +16 prog_clk[0]:16 5.203729e-05 +17 prog_clk[0]:17 0.0009269713 +18 prog_clk[0]:18 0.0002260366 +19 prog_clk[0]:19 5.88527e-05 +20 prog_clk[0]:20 6.025054e-05 +21 prog_clk[0]:21 0.0002664379 +22 prog_clk[0]:22 0.0002664379 +23 prog_clk[0]:23 0.002069404 +24 prog_clk[0]:24 0.001843367 +25 prog_clk[0]:25 0.00140623 +26 prog_clk[0]:24 chanx_left_in[14]:8 0.001056499 +27 prog_clk[0]:23 chanx_left_in[14]:7 0.001056499 +28 prog_clk[0]:23 chanx_left_in[14]:8 0.0004016801 +29 prog_clk[0]:18 chanx_left_in[14]:7 0.0004016801 +30 prog_clk[0]:24 chanx_left_in[17]:7 0.0003604833 +31 prog_clk[0]:23 chanx_left_in[17]:6 0.0003604833 +32 prog_clk[0] chanx_right_in[1]:5 6.559725e-05 +33 prog_clk[0]:25 chanx_right_in[1]:6 6.559725e-05 +34 prog_clk[0]:24 chanx_right_in[1]:11 0.0003262241 +35 prog_clk[0]:22 chanx_right_in[1]:13 3.887866e-05 +36 prog_clk[0]:23 chanx_right_in[1]:11 1.503629e-05 +37 prog_clk[0]:23 chanx_right_in[1]:12 0.0003262241 +38 prog_clk[0]:21 chanx_right_in[1]:14 3.887866e-05 +39 prog_clk[0]:18 chanx_right_in[1]:12 1.503629e-05 +40 prog_clk[0] ropt_net_208:5 2.450902e-05 +41 prog_clk[0] ropt_net_208:8 2.528149e-05 +42 prog_clk[0]:25 ropt_net_208:4 2.450902e-05 +43 prog_clk[0]:25 ropt_net_208:7 2.528149e-05 +44 prog_clk[0] ropt_net_171:4 0.0001120439 +45 prog_clk[0]:25 ropt_net_171:5 0.0001120439 + +*RES +0 prog_clk[0] prog_clk[0]:25 0.02672545 +1 prog_clk[0]:25 prog_clk[0]:24 0.00341 +2 prog_clk[0]:24 prog_clk[0]:23 0.008070291 +3 prog_clk[0]:22 prog_clk[0]:21 0.004765625 +4 prog_clk[0]:23 prog_clk[0]:22 0.00341 +5 prog_clk[0]:23 prog_clk[0]:18 0.001079825 +6 prog_clk[0]:20 prog_clk[0]:19 0.0001059783 +7 prog_clk[0]:21 prog_clk[0]:20 0.0045 +8 prog_clk[0]:19 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +9 prog_clk[0]:17 prog_clk[0]:16 0.0045 +10 prog_clk[0]:17 prog_clk[0]:14 0.014875 +11 prog_clk[0]:18 prog_clk[0]:17 0.00341 +12 prog_clk[0]:13 prog_clk[0]:12 0.0001847826 +13 prog_clk[0]:14 prog_clk[0]:13 0.0045 +14 prog_clk[0]:14 prog_clk[0]:11 0.001466518 +15 prog_clk[0]:12 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +16 prog_clk[0]:11 prog_clk[0]:10 0.00341 +17 prog_clk[0]:10 prog_clk[0]:9 0.002087583 +18 prog_clk[0]:8 prog_clk[0]:7 0.002944197 +19 prog_clk[0]:9 prog_clk[0]:8 0.00341 +20 prog_clk[0]:6 prog_clk[0]:5 0.0001440218 +21 prog_clk[0]:7 prog_clk[0]:6 0.0045 +22 prog_clk[0]:5 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +23 prog_clk[0]:16 prog_clk[0]:15 0.0005736608 +24 prog_clk[0]:15 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.002904797 //LENGTH 19.960 LUMPCC 0 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 61.485 36.720 +*I mux_bottom_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 64.040 41.870 +*I mux_bottom_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 65.420 44.880 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 62.735 47.940 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 62.735 47.940 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 63.020 47.940 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 63.020 47.895 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 63.020 45.617 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 63.028 45.560 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 65.312 45.560 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 65.320 45.503 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 65.320 44.880 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 65.320 44.880 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 65.320 42.205 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 65.275 42.160 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 64.097 42.160 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 64.078 41.875 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 62.605 41.820 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 62.560 41.775 +*N mux_tree_tapbuf_size10_0_sram[2]:19 *C 62.560 36.765 +*N mux_tree_tapbuf_size10_0_sram[2]:20 *C 62.515 36.720 +*N mux_tree_tapbuf_size10_0_sram[2]:21 *C 61.523 36.720 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l3_in_0_:S 1e-06 +3 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 5.255424e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 5.738864e-05 +6 mux_tree_tapbuf_size10_0_sram[2]:6 0.0001525151 +7 mux_tree_tapbuf_size10_0_sram[2]:7 0.0001525151 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0002605853 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.0002605853 +10 mux_tree_tapbuf_size10_0_sram[2]:10 5.28273e-05 +11 mux_tree_tapbuf_size10_0_sram[2]:11 3.256403e-05 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0002602928 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0001724992 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.000129273 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.0001578426 +16 mux_tree_tapbuf_size10_0_sram[2]:16 0.0001616113 +17 mux_tree_tapbuf_size10_0_sram[2]:17 0.0001330417 +18 mux_tree_tapbuf_size10_0_sram[2]:18 0.0003085308 +19 mux_tree_tapbuf_size10_0_sram[2]:19 0.0003085308 +20 mux_tree_tapbuf_size10_0_sram[2]:20 0.0001238198 +21 mux_tree_tapbuf_size10_0_sram[2]:21 0.0001238198 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:21 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.00341 +2 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.0003579833 +3 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.002033482 +4 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.00341 +5 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.0001548913 +6 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size10_0_sram[2]:4 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.001314732 +9 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:17 0.0045 +10 mux_tree_tapbuf_size10_0_sram[2]:20 mux_tree_tapbuf_size10_0_sram[2]:19 0.0045 +11 mux_tree_tapbuf_size10_0_sram[2]:19 mux_tree_tapbuf_size10_0_sram[2]:18 0.004473215 +12 mux_tree_tapbuf_size10_0_sram[2]:21 mux_tree_tapbuf_size10_0_sram[2]:20 0.0008861606 +13 mux_tree_tapbuf_size10_0_sram[2]:16 mux_bottom_ipin_0\/mux_l3_in_1_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.0001656977 +15 mux_tree_tapbuf_size10_0_sram[2]:11 mux_bottom_ipin_0\/mux_l3_in_0_:S 0.152 +16 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.0045 +17 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:10 0.0005558036 +18 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +19 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.002388393 +20 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.001051339 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002502969 //LENGTH 22.440 LUMPCC 0.0006673551 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l1_in_0_:X O *L 0 *C 81.595 55.080 +*I mux_bottom_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 82.705 36.380 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 82.705 36.380 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 82.800 36.425 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 82.800 50.615 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 82.755 50.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 81.005 50.660 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 80.960 50.705 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 80.960 55.035 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 81.005 55.080 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 81.558 55.080 + +*CAP +0 mux_bottom_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.610876e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005925632 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005925632 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.553581e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.553581e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001705348 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001705348 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 6.51188e-05 +10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 6.51188e-05 +11 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[17]:18 8.003791e-05 +12 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[17]:17 8.003791e-05 +13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_0_sram[0]:17 0.0001884518 +14 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_0_sram[0]:18 0.0001884518 +15 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_0_sram[0]:17 3.732655e-05 +16 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_0_sram[0]:18 2.766672e-05 +17 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size10_0_sram[0]:6 1.946395e-07 +18 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size10_0_sram[0]:7 2.766672e-05 +19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size10_0_sram[0]:18 3.732655e-05 +20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size10_0_sram[0]:5 1.946395e-07 + +*RES +0 mux_bottom_ipin_0\/mux_l1_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_ipin_0\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.01266964 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0015625 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.003866072 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004933036 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002661509 //LENGTH 23.740 LUMPCC 0.000521631 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_0_:X O *L 0 *C 81.135 37.400 +*I mux_bottom_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 66.145 45.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 66.183 45.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 79.995 45.220 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 80.040 45.175 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 80.040 37.445 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 80.085 37.400 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 81.098 37.400 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005644822 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0005644822 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004169258 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004169258 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.75314e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.75314e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_left_in[3]:4 0.0002608155 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_left_in[3]:3 0.0002608155 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.01233259 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002909037 //LENGTH 26.605 LUMPCC 0.000332919 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l2_in_3_:X O *L 0 *C 64.115 18.360 +*I mux_bottom_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 65.150 42.840 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 65.112 42.840 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 63.985 42.840 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 63.940 42.795 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 63.940 18.405 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 63.940 18.360 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 64.115 18.360 + +*CAP +0 mux_bottom_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001242144 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001242144 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.00111009 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00111009 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.460055e-05 +7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.090968e-05 +8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001664595 +9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001664595 + +*RES +0 mux_bottom_ipin_0\/mux_l2_in_3_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001006696 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.02177679 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_220 0.0004597923 //LENGTH 3.585 LUMPCC 0.000173055 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 4.140 37.400 +*I ropt_mt_inst_815:A I *L 0.001766 *C 3.220 39.440 +*N ropt_net_220:2 *C 3.220 39.440 +*N ropt_net_220:3 *C 3.220 39.395 +*N ropt_net_220:4 *C 3.220 37.445 +*N ropt_net_220:5 *C 3.265 37.400 +*N ropt_net_220:6 *C 4.103 37.400 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_220:2 3.19373e-05 +3 ropt_net_220:3 7.44049e-05 +4 ropt_net_220:4 7.44049e-05 +5 ropt_net_220:5 5.199511e-05 +6 ropt_net_220:6 5.199511e-05 +7 ropt_net_220:3 chanx_right_in[17]:6 6.041428e-05 +8 ropt_net_220:5 chanx_right_in[17]:3 2.611323e-05 +9 ropt_net_220:4 chanx_right_in[17]:5 6.041428e-05 +10 ropt_net_220:6 chanx_right_in[17]:4 2.611323e-05 + +*RES +0 ropt_mt_inst_758:X ropt_net_220:6 0.152 +1 ropt_net_220:2 ropt_mt_inst_815:A 0.152 +2 ropt_net_220:3 ropt_net_220:2 0.0045 +3 ropt_net_220:5 ropt_net_220:4 0.0045 +4 ropt_net_220:4 ropt_net_220:3 0.001741072 +5 ropt_net_220:6 ropt_net_220:5 0.0007477679 + +*END + +*D_NET ropt_net_206 0.0009131351 //LENGTH 6.635 LUMPCC 0.0003046093 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 7.095 70.040 +*I ropt_mt_inst_801:A I *L 0.001767 *C 3.220 72.080 +*N ropt_net_206:2 *C 3.258 72.080 +*N ropt_net_206:3 *C 6.855 72.080 +*N ropt_net_206:4 *C 6.900 72.035 +*N ropt_net_206:5 *C 6.900 70.085 +*N ropt_net_206:6 *C 6.900 70.040 +*N ropt_net_206:7 *C 7.095 70.040 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_206:2 0.0001172996 +3 ropt_net_206:3 0.0001172996 +4 ropt_net_206:4 0.0001259498 +5 ropt_net_206:5 0.0001259498 +6 ropt_net_206:6 5.83573e-05 +7 ropt_net_206:7 6.166977e-05 +8 ropt_net_206:2 chanx_left_out[0]:3 0.0001523046 +9 ropt_net_206:3 chanx_left_out[0]:4 0.0001523046 + +*RES +0 ropt_mt_inst_763:X ropt_net_206:7 0.152 +1 ropt_net_206:2 ropt_mt_inst_801:A 0.152 +2 ropt_net_206:3 ropt_net_206:2 0.003212054 +3 ropt_net_206:4 ropt_net_206:3 0.0045 +4 ropt_net_206:6 ropt_net_206:5 0.0045 +5 ropt_net_206:5 ropt_net_206:4 0.001741071 +6 ropt_net_206:7 ropt_net_206:6 0.0001059783 + +*END + +*D_NET ropt_net_208 0.00138828 //LENGTH 10.655 LUMPCC 0.0004938146 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 7.095 4.760 +*I ropt_mt_inst_803:A I *L 0.001767 *C 3.220 9.520 +*N ropt_net_208:2 *C 3.258 9.520 +*N ropt_net_208:3 *C 3.635 9.520 +*N ropt_net_208:4 *C 3.680 9.475 +*N ropt_net_208:5 *C 3.680 8.898 +*N ropt_net_208:6 *C 3.685 8.832 +*N ropt_net_208:7 *C 4.120 8.828 +*N ropt_net_208:8 *C 4.120 8.160 +*N ropt_net_208:9 *C 6.893 8.160 +*N ropt_net_208:10 *C 6.900 8.103 +*N ropt_net_208:11 *C 6.900 4.805 +*N ropt_net_208:12 *C 6.900 4.760 +*N ropt_net_208:13 *C 7.095 4.760 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 ropt_mt_inst_803:A 1e-06 +2 ropt_net_208:2 5.309099e-05 +3 ropt_net_208:3 5.309099e-05 +4 ropt_net_208:4 2.268713e-05 +5 ropt_net_208:5 2.268713e-05 +6 ropt_net_208:6 4.999639e-05 +7 ropt_net_208:7 3.32502e-05 +8 ropt_net_208:8 8.487219e-05 +9 ropt_net_208:9 0.0001016184 +10 ropt_net_208:10 0.0001746818 +11 ropt_net_208:11 0.0001746818 +12 ropt_net_208:12 5.924575e-05 +13 ropt_net_208:13 6.256312e-05 +14 ropt_net_208:5 prog_clk[0] 2.450902e-05 +15 ropt_net_208:4 prog_clk[0]:25 2.450902e-05 +16 ropt_net_208:7 prog_clk[0]:25 2.528149e-05 +17 ropt_net_208:8 prog_clk[0] 2.528149e-05 +18 ropt_net_208:9 chanx_left_out[13]:2 7.24141e-05 +19 ropt_net_208:6 chanx_left_out[13] 4.124313e-05 +20 ropt_net_208:7 chanx_left_out[13]:2 4.124313e-05 +21 ropt_net_208:8 chanx_left_out[13] 7.24141e-05 +22 ropt_net_208:11 ropt_net_171:4 2.970168e-06 +23 ropt_net_208:10 ropt_net_171:5 2.970168e-06 +24 ropt_net_208:5 ropt_net_171:4 2.765129e-05 +25 ropt_net_208:4 ropt_net_171:5 2.765129e-05 +26 ropt_net_208:7 ropt_net_171:5 5.28381e-05 +27 ropt_net_208:8 ropt_net_171:4 5.28381e-05 + +*RES +0 ropt_mt_inst_766:X ropt_net_208:13 0.152 +1 ropt_net_208:13 ropt_net_208:12 0.0001059783 +2 ropt_net_208:12 ropt_net_208:11 0.0045 +3 ropt_net_208:11 ropt_net_208:10 0.002944197 +4 ropt_net_208:10 ropt_net_208:9 0.00341 +5 ropt_net_208:9 ropt_net_208:8 0.0004343583 +6 ropt_net_208:5 ropt_net_208:4 0.0005156251 +7 ropt_net_208:6 ropt_net_208:5 0.00341 +8 ropt_net_208:3 ropt_net_208:2 0.0003370536 +9 ropt_net_208:4 ropt_net_208:3 0.0045 +10 ropt_net_208:2 ropt_mt_inst_803:A 0.152 +11 ropt_net_208:7 ropt_net_208:6 6.490476e-05 +12 ropt_net_208:8 ropt_net_208:7 0.000104575 + +*END + +*D_NET ropt_net_223 0.0003902654 //LENGTH 3.510 LUMPCC 0.0001311788 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 4.600 50.320 +*I ropt_mt_inst_818:A I *L 0.001766 *C 7.820 50.320 +*N ropt_net_223:2 *C 7.783 50.320 +*N ropt_net_223:3 *C 4.638 50.320 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 ropt_mt_inst_818:A 1e-06 +2 ropt_net_223:2 0.0001285433 +3 ropt_net_223:3 0.0001285433 +4 ropt_net_223:3 chanx_right_in[19]:6 6.558941e-05 +5 ropt_net_223:2 chanx_right_in[19]:7 6.558941e-05 + +*RES +0 ropt_mt_inst_774:X ropt_net_223:3 0.152 +1 ropt_net_223:3 ropt_net_223:2 0.002808036 +2 ropt_net_223:2 ropt_mt_inst_818:A 0.152 + +*END + +*D_NET ropt_net_215 0.001080442 //LENGTH 9.680 LUMPCC 0.0002058145 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 4.140 41.820 +*I ropt_mt_inst_810:A I *L 0.001766 *C 7.820 36.720 +*N ropt_net_215:2 *C 7.820 36.735 +*N ropt_net_215:3 *C 7.820 37.060 +*N ropt_net_215:4 *C 7.820 37.105 +*N ropt_net_215:5 *C 7.820 41.775 +*N ropt_net_215:6 *C 7.775 41.820 +*N ropt_net_215:7 *C 4.178 41.820 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 ropt_mt_inst_810:A 1e-06 +2 ropt_net_215:2 3.762203e-05 +3 ropt_net_215:3 7.259881e-05 +4 ropt_net_215:4 0.0002354305 +5 ropt_net_215:5 0.0002354305 +6 ropt_net_215:6 0.0001457727 +7 ropt_net_215:7 0.0001457727 +8 ropt_net_215:7 chanx_left_in[11]:6 5.161266e-05 +9 ropt_net_215:6 chanx_left_in[11]:5 5.161266e-05 +10 ropt_net_215:7 chanx_right_in[5]:2 4.622387e-05 +11 ropt_net_215:6 chanx_right_in[5]:3 4.622387e-05 +12 ropt_net_215:5 chanx_right_in[5]:4 5.070724e-06 +13 ropt_net_215:4 chanx_right_in[5]:5 5.070724e-06 + +*RES +0 ropt_mt_inst_776:X ropt_net_215:7 0.152 +1 ropt_net_215:7 ropt_net_215:6 0.003212054 +2 ropt_net_215:6 ropt_net_215:5 0.0045 +3 ropt_net_215:5 ropt_net_215:4 0.004169643 +4 ropt_net_215:3 ropt_net_215:2 0.0001766304 +5 ropt_net_215:4 ropt_net_215:3 0.0045 +6 ropt_net_215:2 ropt_mt_inst_810:A 0.152 + +*END + +*D_NET ropt_net_218 0.0005195914 //LENGTH 3.860 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 4.140 46.920 +*I ropt_mt_inst_813:A I *L 0.001766 *C 3.220 44.880 +*N ropt_net_218:2 *C 3.220 44.895 +*N ropt_net_218:3 *C 3.220 45.220 +*N ropt_net_218:4 *C 3.220 45.265 +*N ropt_net_218:5 *C 3.220 46.875 +*N ropt_net_218:6 *C 3.265 46.920 +*N ropt_net_218:7 *C 4.103 46.920 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 ropt_mt_inst_813:A 1e-06 +2 ropt_net_218:2 3.826948e-05 +3 ropt_net_218:3 7.398121e-05 +4 ropt_net_218:4 0.0001254692 +5 ropt_net_218:5 0.0001254692 +6 ropt_net_218:6 7.720121e-05 +7 ropt_net_218:7 7.720121e-05 + +*RES +0 ropt_mt_inst_781:X ropt_net_218:7 0.152 +1 ropt_net_218:7 ropt_net_218:6 0.0007477679 +2 ropt_net_218:6 ropt_net_218:5 0.0045 +3 ropt_net_218:5 ropt_net_218:4 0.0014375 +4 ropt_net_218:3 ropt_net_218:2 0.0001766304 +5 ropt_net_218:4 ropt_net_218:3 0.0045 +6 ropt_net_218:2 ropt_mt_inst_813:A 0.152 + +*END + +*D_NET ropt_net_229 0.0005125616 //LENGTH 3.875 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 98.900 56.440 +*I ropt_mt_inst_824:A I *L 0.001766 *C 97.825 58.480 +*N ropt_net_229:2 *C 97.825 58.480 +*N ropt_net_229:3 *C 97.980 58.480 +*N ropt_net_229:4 *C 97.980 58.435 +*N ropt_net_229:5 *C 97.980 56.485 +*N ropt_net_229:6 *C 98.025 56.440 +*N ropt_net_229:7 *C 98.863 56.440 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 ropt_mt_inst_824:A 1e-06 +2 ropt_net_229:2 5.541943e-05 +3 ropt_net_229:3 5.501552e-05 +4 ropt_net_229:4 0.0001215606 +5 ropt_net_229:5 0.0001215606 +6 ropt_net_229:6 7.850272e-05 +7 ropt_net_229:7 7.850272e-05 + +*RES +0 ropt_mt_inst_784:X ropt_net_229:7 0.152 +1 ropt_net_229:2 ropt_mt_inst_824:A 0.152 +2 ropt_net_229:3 ropt_net_229:2 8.423914e-05 +3 ropt_net_229:4 ropt_net_229:3 0.0045 +4 ropt_net_229:6 ropt_net_229:5 0.0045 +5 ropt_net_229:5 ropt_net_229:4 0.001741071 +6 ropt_net_229:7 ropt_net_229:6 0.0007477679 + +*END + +*D_NET chanx_left_out[13] 0.001833115 //LENGTH 15.885 LUMPCC 0.0002273144 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 8.740 11.560 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 9.520 +*N chanx_left_out[13]:2 *C 11.492 9.520 +*N chanx_left_out[13]:3 *C 11.500 9.578 +*N chanx_left_out[13]:4 *C 11.500 11.515 +*N chanx_left_out[13]:5 *C 11.455 11.560 +*N chanx_left_out[13]:6 *C 8.777 11.560 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 chanx_left_out[13] 0.0005067634 +2 chanx_left_out[13]:2 0.0005067634 +3 chanx_left_out[13]:3 0.0001117501 +4 chanx_left_out[13]:4 0.0001117501 +5 chanx_left_out[13]:5 0.0001838869 +6 chanx_left_out[13]:6 0.0001838869 +7 chanx_left_out[13] ropt_net_208:6 4.124313e-05 +8 chanx_left_out[13] ropt_net_208:8 7.24141e-05 +9 chanx_left_out[13]:2 ropt_net_208:7 4.124313e-05 +10 chanx_left_out[13]:2 ropt_net_208:9 7.24141e-05 + +*RES +0 ropt_mt_inst_796:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:6 chanx_left_out[13]:5 0.002390625 +2 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.001729911 +4 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +5 chanx_left_out[13]:2 chanx_left_out[13] 0.001607792 + +*END + +*D_NET chanx_right_out[9] 0.0003462523 //LENGTH 1.985 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 101.855 72.080 +*P chanx_right_out[9] O *L 0.7423 *C 103.650 72.080 +*N chanx_right_out[9]:2 *C 102.128 72.080 +*N chanx_right_out[9]:3 *C 102.120 72.080 +*N chanx_right_out[9]:4 *C 102.120 72.080 +*N chanx_right_out[9]:5 *C 101.855 72.080 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 chanx_right_out[9] 0.0001134288 +2 chanx_right_out[9]:2 0.0001134288 +3 chanx_right_out[9]:3 2.99081e-05 +4 chanx_right_out[9]:4 4.390535e-05 +5 chanx_right_out[9]:5 4.458119e-05 + +*RES +0 ropt_mt_inst_789:X chanx_right_out[9]:5 0.152 +1 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0001440218 +2 chanx_right_out[9]:4 chanx_right_out[9]:3 0.0045 +3 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +4 chanx_right_out[9]:2 chanx_right_out[9] 0.000238525 + +*END + +*D_NET ropt_net_210 0.0011262 //LENGTH 9.970 LUMPCC 0.0001243069 DR + +*CONN +*I ropt_mt_inst_793:X O *L 0 *C 101.855 38.760 +*I ropt_mt_inst_805:A I *L 0.001767 *C 97.825 34.000 +*N ropt_net_210:2 *C 97.863 34.000 +*N ropt_net_210:3 *C 102.075 34.000 +*N ropt_net_210:4 *C 102.120 34.045 +*N ropt_net_210:5 *C 102.120 38.715 +*N ropt_net_210:6 *C 102.120 38.760 +*N ropt_net_210:7 *C 101.855 38.760 + +*CAP +0 ropt_mt_inst_793:X 1e-06 +1 ropt_mt_inst_805:A 1e-06 +2 ropt_net_210:2 0.0002438898 +3 ropt_net_210:3 0.0002438898 +4 ropt_net_210:4 0.0002023327 +5 ropt_net_210:5 0.0002023327 +6 ropt_net_210:6 5.177896e-05 +7 ropt_net_210:7 5.566952e-05 +8 ropt_net_210:4 chanx_right_out[3]:3 6.215347e-05 +9 ropt_net_210:5 chanx_right_out[3]:4 6.215347e-05 + +*RES +0 ropt_mt_inst_793:X ropt_net_210:7 0.152 +1 ropt_net_210:2 ropt_mt_inst_805:A 0.152 +2 ropt_net_210:3 ropt_net_210:2 0.003761161 +3 ropt_net_210:4 ropt_net_210:3 0.0045 +4 ropt_net_210:6 ropt_net_210:5 0.0045 +5 ropt_net_210:5 ropt_net_210:4 0.004169643 +6 ropt_net_210:7 ropt_net_210:6 0.0001440218 + +*END + +*D_NET chanx_left_out[15] 0.0007981265 //LENGTH 5.385 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 4.140 30.600 +*P chanx_left_out[15] O *L 0.7423 *C 1.305 28.560 +*N chanx_left_out[15]:2 *C 4.133 28.560 +*N chanx_left_out[15]:3 *C 4.140 28.617 +*N chanx_left_out[15]:4 *C 4.140 30.555 +*N chanx_left_out[15]:5 *C 4.140 30.600 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 chanx_left_out[15] 0.0002285799 +2 chanx_left_out[15]:2 0.0002285799 +3 chanx_left_out[15]:3 0.0001534574 +4 chanx_left_out[15]:4 0.0001534574 +5 chanx_left_out[15]:5 3.305171e-05 + +*RES +0 ropt_mt_inst_802:X chanx_left_out[15]:5 0.152 +1 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +2 chanx_left_out[15]:4 chanx_left_out[15]:3 0.001729911 +3 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +4 chanx_left_out[15]:2 chanx_left_out[15] 0.000442975 + +*END + +*D_NET BUF_net_52 0.002126047 //LENGTH 16.245 LUMPCC 0.000796602 DR + +*CONN +*I BUFT_RR_52:X O *L 0 *C 78.660 17.340 +*I BUFT_P_137:A I *L 0.001766 *C 88.780 12.240 +*N BUF_net_52:2 *C 88.743 12.240 +*N BUF_net_52:3 *C 88.320 12.240 +*N BUF_net_52:4 *C 88.320 12.580 +*N BUF_net_52:5 *C 78.705 12.580 +*N BUF_net_52:6 *C 78.660 12.625 +*N BUF_net_52:7 *C 78.660 17.295 +*N BUF_net_52:8 *C 78.660 17.340 + +*CAP +0 BUFT_RR_52:X 1e-06 +1 BUFT_P_137:A 1e-06 +2 BUF_net_52:2 3.218593e-05 +3 BUF_net_52:3 5.6068e-05 +4 BUF_net_52:4 0.0003749352 +5 BUF_net_52:5 0.0003510531 +6 BUF_net_52:6 0.0002409252 +7 BUF_net_52:7 0.0002409252 +8 BUF_net_52:8 3.135245e-05 +9 BUF_net_52:5 chanx_right_in[6]:2 0.0002083964 +10 BUF_net_52:5 chanx_right_in[6]:6 0.0001872432 +11 BUF_net_52:2 chanx_right_in[6]:7 2.661443e-06 +12 BUF_net_52:4 chanx_right_in[6]:3 0.0002083964 +13 BUF_net_52:4 chanx_right_in[6]:7 0.0001872432 +14 BUF_net_52:3 chanx_right_in[6]:6 2.661443e-06 + +*RES +0 BUFT_RR_52:X BUF_net_52:8 0.152 +1 BUF_net_52:8 BUF_net_52:7 0.0045 +2 BUF_net_52:7 BUF_net_52:6 0.004169643 +3 BUF_net_52:5 BUF_net_52:4 0.008584822 +4 BUF_net_52:6 BUF_net_52:5 0.0045 +5 BUF_net_52:2 BUFT_P_137:A 0.152 +6 BUF_net_52:4 BUF_net_52:3 0.0003035715 +7 BUF_net_52:3 BUF_net_52:2 0.0003772322 + +*END + +*D_NET chanx_right_out[2] 0.0006437458 //LENGTH 6.020 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 101.855 70.040 +*P chanx_right_out[2] O *L 0.7423 *C 102.580 74.870 +*N chanx_right_out[2]:2 *C 102.580 70.085 +*N chanx_right_out[2]:3 *C 102.535 70.040 +*N chanx_right_out[2]:4 *C 101.892 70.040 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 chanx_right_out[2] 0.0002576637 +2 chanx_right_out[2]:2 0.0002576637 +3 chanx_right_out[2]:3 6.370918e-05 +4 chanx_right_out[2]:4 6.370918e-05 + +*RES +0 ropt_mt_inst_812:X chanx_right_out[2]:4 0.152 +1 chanx_right_out[2]:4 chanx_right_out[2]:3 0.0005736608 +2 chanx_right_out[2]:3 chanx_right_out[2]:2 0.0045 +3 chanx_right_out[2]:2 chanx_right_out[2] 0.004272322 + +*END + +*D_NET BUF_net_62 0.002240777 //LENGTH 23.390 LUMPCC 0 DR + +*CONN +*I BUFT_RR_62:X O *L 0 *C 25.300 58.820 +*I BUFT_P_147:A I *L 0.001766 *C 16.100 72.080 +*N BUF_net_62:2 *C 16.137 72.080 +*N BUF_net_62:3 *C 24.795 72.080 +*N BUF_net_62:4 *C 24.840 72.035 +*N BUF_net_62:5 *C 24.840 58.865 +*N BUF_net_62:6 *C 24.885 58.820 +*N BUF_net_62:7 *C 25.263 58.820 + +*CAP +0 BUFT_RR_62:X 1e-06 +1 BUFT_P_147:A 1e-06 +2 BUF_net_62:2 0.0004264613 +3 BUF_net_62:3 0.0004264613 +4 BUF_net_62:4 0.0006527622 +5 BUF_net_62:5 0.0006527622 +6 BUF_net_62:6 4.016522e-05 +7 BUF_net_62:7 4.016522e-05 + +*RES +0 BUFT_RR_62:X BUF_net_62:7 0.152 +1 BUF_net_62:2 BUFT_P_147:A 0.152 +2 BUF_net_62:3 BUF_net_62:2 0.007729911 +3 BUF_net_62:4 BUF_net_62:3 0.0045 +4 BUF_net_62:6 BUF_net_62:5 0.0045 +5 BUF_net_62:5 BUF_net_62:4 0.01175893 +6 BUF_net_62:7 BUF_net_62:6 0.0003370536 + +*END + +*D_NET chanx_left_out[6] 0.001215609 //LENGTH 11.075 LUMPCC 0 DR + +*CONN +*I BUFT_RR_68:X O *L 0 *C 9.370 6.460 +*P chanx_left_out[6] O *L 0.7423 *C 1.305 4.080 +*N chanx_left_out[6]:2 *C 9.193 4.080 +*N chanx_left_out[6]:3 *C 9.200 4.138 +*N chanx_left_out[6]:4 *C 9.200 6.415 +*N chanx_left_out[6]:5 *C 9.200 6.460 +*N chanx_left_out[6]:6 *C 9.370 6.460 + +*CAP +0 BUFT_RR_68:X 1e-06 +1 chanx_left_out[6] 0.0004339243 +2 chanx_left_out[6]:2 0.0004339243 +3 chanx_left_out[6]:3 0.0001273434 +4 chanx_left_out[6]:4 0.0001273434 +5 chanx_left_out[6]:5 4.579188e-05 +6 chanx_left_out[6]:6 4.628224e-05 + +*RES +0 BUFT_RR_68:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +2 chanx_left_out[6]:2 chanx_left_out[6] 0.001235708 +3 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +4 chanx_left_out[6]:4 chanx_left_out[6]:3 0.002033482 +5 chanx_left_out[6]:6 chanx_left_out[6]:5 9.239131e-05 + +*END + +*D_NET chanx_right_out[5] 0.0003461367 //LENGTH 3.300 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_822:X O *L 0 *C 101.855 3.400 +*P chanx_right_out[5] O *L 0.7423 *C 102.580 1.290 +*N chanx_right_out[5]:2 *C 102.580 3.355 +*N chanx_right_out[5]:3 *C 102.535 3.400 +*N chanx_right_out[5]:4 *C 101.892 3.400 + +*CAP +0 ropt_mt_inst_822:X 1e-06 +1 chanx_right_out[5] 0.0001126905 +2 chanx_right_out[5]:2 0.0001126905 +3 chanx_right_out[5]:3 5.987786e-05 +4 chanx_right_out[5]:4 5.987786e-05 + +*RES +0 ropt_mt_inst_822:X chanx_right_out[5]:4 0.152 +1 chanx_right_out[5]:4 chanx_right_out[5]:3 0.0005736608 +2 chanx_right_out[5]:3 chanx_right_out[5]:2 0.0045 +3 chanx_right_out[5]:2 chanx_right_out[5] 0.00184375 + +*END + +*D_NET ropt_net_200 0.0006616895 //LENGTH 5.345 LUMPCC 8.922998e-05 DR + +*CONN +*I BUFT_P_127:X O *L 0 *C 98.900 18.360 +*I ropt_mt_inst_795:A I *L 0.001766 *C 97.825 14.960 +*N ropt_net_200:2 *C 97.863 14.960 +*N ropt_net_200:3 *C 98.855 14.960 +*N ropt_net_200:4 *C 98.900 15.005 +*N ropt_net_200:5 *C 98.900 17.975 +*N ropt_net_200:6 *C 98.900 18.020 +*N ropt_net_200:7 *C 98.900 18.360 + +*CAP +0 BUFT_P_127:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_200:2 7.508239e-05 +3 ropt_net_200:3 7.508239e-05 +4 ropt_net_200:4 0.0001528225 +5 ropt_net_200:5 0.0001528225 +6 ropt_net_200:6 5.932329e-05 +7 ropt_net_200:7 5.532653e-05 +8 ropt_net_200:5 chanx_right_in[6]:9 4.461499e-05 +9 ropt_net_200:4 chanx_right_in[6]:8 4.461499e-05 + +*RES +0 BUFT_P_127:X ropt_net_200:7 0.152 +1 ropt_net_200:7 ropt_net_200:6 0.0001465517 +2 ropt_net_200:6 ropt_net_200:5 0.0045 +3 ropt_net_200:5 ropt_net_200:4 0.002651786 +4 ropt_net_200:3 ropt_net_200:2 0.0008861608 +5 ropt_net_200:4 ropt_net_200:3 0.0045 +6 ropt_net_200:2 ropt_mt_inst_795:A 0.152 + +*END + +*D_NET ropt_net_199 0.001077116 //LENGTH 9.020 LUMPCC 8.932089e-05 DR + +*CONN +*I BUFT_P_131:X O *L 0 *C 95.680 20.060 +*I ropt_mt_inst_794:A I *L 0.001766 *C 97.825 25.840 +*N ropt_net_199:2 *C 97.825 25.840 +*N ropt_net_199:3 *C 97.980 25.840 +*N ropt_net_199:4 *C 97.980 25.795 +*N ropt_net_199:5 *C 97.980 20.105 +*N ropt_net_199:6 *C 97.980 20.060 +*N ropt_net_199:7 *C 95.718 20.060 + +*CAP +0 BUFT_P_131:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_199:2 5.863726e-05 +3 ropt_net_199:3 5.984255e-05 +4 ropt_net_199:4 0.000263792 +5 ropt_net_199:5 0.000263792 +6 ropt_net_199:6 0.0001875198 +7 ropt_net_199:7 0.0001522111 +8 ropt_net_199:4 ropt_net_197:9 2.139509e-07 +9 ropt_net_199:4 ropt_net_197:5 4.444649e-05 +10 ropt_net_199:5 ropt_net_197:8 2.139509e-07 +11 ropt_net_199:5 ropt_net_197:4 4.444649e-05 + +*RES +0 BUFT_P_131:X ropt_net_199:7 0.152 +1 ropt_net_199:2 ropt_mt_inst_794:A 0.152 +2 ropt_net_199:3 ropt_net_199:2 8.423914e-05 +3 ropt_net_199:4 ropt_net_199:3 0.0045 +4 ropt_net_199:6 ropt_net_199:5 0.0045 +5 ropt_net_199:5 ropt_net_199:4 0.005080357 +6 ropt_net_199:7 ropt_net_199:6 0.002020089 + +*END + +*D_NET ropt_net_184 0.002017051 //LENGTH 15.080 LUMPCC 0.0006811137 DR + +*CONN +*I BUFT_P_143:X O *L 0 *C 89.240 29.240 +*I ropt_mt_inst_779:A I *L 0.001766 *C 97.825 31.280 +*N ropt_net_184:2 *C 97.825 31.280 +*N ropt_net_184:3 *C 97.980 31.280 +*N ropt_net_184:4 *C 97.980 31.235 +*N ropt_net_184:5 *C 97.980 28.617 +*N ropt_net_184:6 *C 97.980 28.560 +*N ropt_net_184:7 *C 91.088 28.560 +*N ropt_net_184:8 *C 91.080 28.617 +*N ropt_net_184:9 *C 91.080 29.195 +*N ropt_net_184:10 *C 91.035 29.240 +*N ropt_net_184:11 *C 89.278 29.240 + +*CAP +0 BUFT_P_143:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_184:2 5.672469e-05 +3 ropt_net_184:3 5.526385e-05 +4 ropt_net_184:4 0.0001513467 +5 ropt_net_184:5 0.0001513467 +6 ropt_net_184:6 0.0002919247 +7 ropt_net_184:7 0.0002919247 +8 ropt_net_184:8 3.366227e-05 +9 ropt_net_184:9 3.366227e-05 +10 ropt_net_184:10 0.000134041 +11 ropt_net_184:11 0.000134041 +12 ropt_net_184:7 chanx_left_in[14]:7 6.316776e-05 +13 ropt_net_184:5 chanx_left_in[14]:4 8.763665e-06 +14 ropt_net_184:6 chanx_left_in[14]:6 6.316776e-05 +15 ropt_net_184:4 chanx_left_in[14]:5 8.763665e-06 +16 ropt_net_184:9 chanx_left_in[17]:4 2.501133e-05 +17 ropt_net_184:8 chanx_left_in[17]:3 2.501133e-05 +18 ropt_net_184:7 chanx_left_in[17]:6 4.440486e-05 +19 ropt_net_184:6 chanx_left_in[17]:5 4.440486e-05 +20 ropt_net_184:7 chanx_right_in[16]:23 0.0001992092 +21 ropt_net_184:6 chanx_right_in[16] 0.0001992092 + +*RES +0 BUFT_P_143:X ropt_net_184:11 0.152 +1 ropt_net_184:11 ropt_net_184:10 0.001569196 +2 ropt_net_184:10 ropt_net_184:9 0.0045 +3 ropt_net_184:9 ropt_net_184:8 0.000515625 +4 ropt_net_184:8 ropt_net_184:7 0.00341 +5 ropt_net_184:7 ropt_net_184:6 0.001079825 +6 ropt_net_184:5 ropt_net_184:4 0.002337054 +7 ropt_net_184:6 ropt_net_184:5 0.00341 +8 ropt_net_184:3 ropt_net_184:2 8.423914e-05 +9 ropt_net_184:4 ropt_net_184:3 0.0045 +10 ropt_net_184:2 ropt_mt_inst_779:A 0.152 + +*END + +*D_NET chanx_left_in[4] 0.01415776 //LENGTH 131.310 LUMPCC 0.0008917961 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 51.680 +*I BUFT_P_131:A I *L 0.001767 *C 94.760 20.400 +*I mux_bottom_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 81.785 25.500 +*N chanx_left_in[4]:3 *C 81.785 25.500 +*N chanx_left_in[4]:4 *C 94.723 20.400 +*N chanx_left_in[4]:5 *C 82.385 20.400 +*N chanx_left_in[4]:6 *C 82.340 20.445 +*N chanx_left_in[4]:7 *C 82.340 25.115 +*N chanx_left_in[4]:8 *C 82.295 25.160 +*N chanx_left_in[4]:9 *C 81.880 25.160 +*N chanx_left_in[4]:10 *C 78.705 25.160 +*N chanx_left_in[4]:11 *C 78.660 25.205 +*N chanx_left_in[4]:12 *C 78.660 52.303 +*N chanx_left_in[4]:13 *C 78.653 52.360 +*N chanx_left_in[4]:14 *C 43.700 52.360 +*N chanx_left_in[4]:15 *C 43.700 51.680 +*N chanx_left_in[4]:16 *C 23.920 51.680 +*N chanx_left_in[4]:17 *C 23.920 52.360 +*N chanx_left_in[4]:18 *C 14.720 52.360 +*N chanx_left_in[4]:19 *C 14.720 51.680 + +*CAP +0 chanx_left_in[4] 0.0008175198 +1 BUFT_P_131:A 1e-06 +2 mux_bottom_ipin_0\/mux_l1_in_2_:A1 1e-06 +3 chanx_left_in[4]:3 5.024735e-05 +4 chanx_left_in[4]:4 0.0007049049 +5 chanx_left_in[4]:5 0.0007049049 +6 chanx_left_in[4]:6 0.0002402238 +7 chanx_left_in[4]:7 0.0002402238 +8 chanx_left_in[4]:8 4.074383e-05 +9 chanx_left_in[4]:9 0.0002867669 +10 chanx_left_in[4]:10 0.0002210831 +11 chanx_left_in[4]:11 0.001354569 +12 chanx_left_in[4]:12 0.001354569 +13 chanx_left_in[4]:13 0.001611668 +14 chanx_left_in[4]:14 0.001657953 +15 chanx_left_in[4]:15 0.0009283364 +16 chanx_left_in[4]:16 0.0009191056 +17 chanx_left_in[4]:17 0.0006172986 +18 chanx_left_in[4]:18 0.0006382858 +19 chanx_left_in[4]:19 0.0008755613 +20 chanx_left_in[4]:13 chanx_right_in[12] 3.645236e-05 +21 chanx_left_in[4]:13 chanx_right_in[12]:17 0.0002768426 +22 chanx_left_in[4]:17 chanx_right_in[12]:15 7.196902e-06 +23 chanx_left_in[4]:16 chanx_right_in[12]:14 7.196902e-06 +24 chanx_left_in[4]:16 chanx_right_in[12]:16 0.0001254062 +25 chanx_left_in[4]:15 chanx_right_in[12]:17 0.0001254062 +26 chanx_left_in[4]:14 chanx_right_in[12]:16 0.0002768426 +27 chanx_left_in[4]:14 chanx_right_in[12]:17 3.645236e-05 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:19 0.002113433 +1 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0045 +2 chanx_left_in[4]:7 chanx_left_in[4]:6 0.004169643 +3 chanx_left_in[4]:5 chanx_left_in[4]:4 0.01101563 +4 chanx_left_in[4]:6 chanx_left_in[4]:5 0.0045 +5 chanx_left_in[4]:4 BUFT_P_131:A 0.152 +6 chanx_left_in[4]:10 chanx_left_in[4]:9 0.002834822 +7 chanx_left_in[4]:11 chanx_left_in[4]:10 0.0045 +8 chanx_left_in[4]:12 chanx_left_in[4]:11 0.0241942 +9 chanx_left_in[4]:13 chanx_left_in[4]:12 0.00341 +10 chanx_left_in[4]:3 mux_bottom_ipin_0\/mux_l1_in_2_:A1 0.152 +11 chanx_left_in[4]:9 chanx_left_in[4]:8 0.0003705357 +12 chanx_left_in[4]:9 chanx_left_in[4]:3 0.0003035715 +13 chanx_left_in[4]:19 chanx_left_in[4]:18 0.0001065333 +14 chanx_left_in[4]:18 chanx_left_in[4]:17 0.001441333 +15 chanx_left_in[4]:17 chanx_left_in[4]:16 0.0001065333 +16 chanx_left_in[4]:16 chanx_left_in[4]:15 0.003098866 +17 chanx_left_in[4]:15 chanx_left_in[4]:14 0.0001065333 +18 chanx_left_in[4]:14 chanx_left_in[4]:13 0.005475891 + +*END + +*D_NET chanx_right_out[11] 0.0008704708 //LENGTH 6.560 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 97.255 36.720 +*P chanx_right_out[11] O *L 0.7423 *C 103.650 36.720 +*N chanx_right_out[11]:2 *C 97.263 36.720 +*N chanx_right_out[11]:3 *C 97.255 36.720 +*N chanx_right_out[11]:4 *C 97.255 36.720 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 chanx_right_out[11] 0.00039823 +2 chanx_right_out[11]:2 0.00039823 +3 chanx_right_out[11]:3 3.238536e-05 +4 chanx_right_out[11]:4 4.062536e-05 + +*RES +0 ropt_mt_inst_786:X chanx_right_out[11]:4 0.152 +1 chanx_right_out[11]:4 chanx_right_out[11]:3 0.0045 +2 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +3 chanx_right_out[11]:2 chanx_right_out[11] 0.001000708 + +*END + +*D_NET chanx_left_out[18] 0.001068152 //LENGTH 8.045 LUMPCC 0.0001867889 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 4.140 15.640 +*P chanx_left_out[18] O *L 0.7423 *C 1.230 12.240 +*N chanx_left_out[18]:2 *C 4.593 12.240 +*N chanx_left_out[18]:3 *C 4.600 12.298 +*N chanx_left_out[18]:4 *C 4.600 15.595 +*N chanx_left_out[18]:5 *C 4.555 15.640 +*N chanx_left_out[18]:6 *C 4.178 15.640 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 chanx_left_out[18] 0.0002612443 +2 chanx_left_out[18]:2 0.0002612443 +3 chanx_left_out[18]:3 0.0001407527 +4 chanx_left_out[18]:4 0.0001407527 +5 chanx_left_out[18]:5 3.818454e-05 +6 chanx_left_out[18]:6 3.818454e-05 +7 chanx_left_out[18]:6 ropt_net_171:6 1.215019e-05 +8 chanx_left_out[18]:5 ropt_net_171:7 1.215019e-05 +9 chanx_left_out[18]:4 ropt_net_171:5 8.124426e-05 +10 chanx_left_out[18]:3 ropt_net_171:4 8.124426e-05 + +*RES +0 ropt_mt_inst_798:X chanx_left_out[18]:6 0.152 +1 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0003370536 +2 chanx_left_out[18]:5 chanx_left_out[18]:4 0.0045 +3 chanx_left_out[18]:4 chanx_left_out[18]:3 0.002944197 +4 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +5 chanx_left_out[18]:2 chanx_left_out[18] 0.0005267917 + +*END + +*D_NET ccff_tail[0] 0.0007898698 //LENGTH 7.340 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 61.835 72.760 +*P ccff_tail[0] O *L 0.7423 *C 57.500 74.870 +*N ccff_tail[0]:2 *C 57.500 74.505 +*N ccff_tail[0]:3 *C 57.545 74.460 +*N ccff_tail[0]:4 *C 61.595 74.460 +*N ccff_tail[0]:5 *C 61.640 74.415 +*N ccff_tail[0]:6 *C 61.640 72.805 +*N ccff_tail[0]:7 *C 61.640 72.760 +*N ccff_tail[0]:8 *C 61.835 72.760 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 ccff_tail[0] 3.112814e-05 +2 ccff_tail[0]:2 3.112814e-05 +3 ccff_tail[0]:3 0.0002263907 +4 ccff_tail[0]:4 0.0002263907 +5 ccff_tail[0]:5 9.23138e-05 +6 ccff_tail[0]:6 9.23138e-05 +7 ccff_tail[0]:7 4.643006e-05 +8 ccff_tail[0]:8 4.277447e-05 + +*RES +0 ropt_mt_inst_791:X ccff_tail[0]:8 0.152 +1 ccff_tail[0]:8 ccff_tail[0]:7 0.0001059783 +2 ccff_tail[0]:7 ccff_tail[0]:6 0.0045 +3 ccff_tail[0]:6 ccff_tail[0]:5 0.0014375 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.003616072 +5 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +6 ccff_tail[0]:3 ccff_tail[0]:2 0.0045 +7 ccff_tail[0]:2 ccff_tail[0] 0.0003258929 + +*END + +*D_NET ropt_net_193 0.001426441 //LENGTH 13.165 LUMPCC 0 DR + +*CONN +*I BUFT_RR_45:X O *L 0 *C 94.300 44.200 +*I ropt_mt_inst_788:A I *L 0.001766 *C 97.825 36.720 +*N ropt_net_193:2 *C 97.863 36.720 +*N ropt_net_193:3 *C 98.395 36.720 +*N ropt_net_193:4 *C 98.440 36.765 +*N ropt_net_193:5 *C 98.440 44.155 +*N ropt_net_193:6 *C 98.395 44.200 +*N ropt_net_193:7 *C 94.338 44.200 + +*CAP +0 BUFT_RR_45:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_193:2 4.913769e-05 +3 ropt_net_193:3 4.913769e-05 +4 ropt_net_193:4 0.0003868837 +5 ropt_net_193:5 0.0003868837 +6 ropt_net_193:6 0.0002761992 +7 ropt_net_193:7 0.0002761992 + +*RES +0 BUFT_RR_45:X ropt_net_193:7 0.152 +1 ropt_net_193:7 ropt_net_193:6 0.003622768 +2 ropt_net_193:6 ropt_net_193:5 0.0045 +3 ropt_net_193:5 ropt_net_193:4 0.006598214 +4 ropt_net_193:3 ropt_net_193:2 0.0004754465 +5 ropt_net_193:4 ropt_net_193:3 0.0045 +6 ropt_net_193:2 ropt_mt_inst_788:A 0.152 + +*END + +*D_NET chanx_right_out[14] 0.0007724077 //LENGTH 5.940 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_805:X O *L 0 *C 98.900 33.320 +*P chanx_right_out[14] O *L 0.7423 *C 103.650 32.640 +*N chanx_right_out[14]:2 *C 98.907 32.640 +*N chanx_right_out[14]:3 *C 98.900 32.698 +*N chanx_right_out[14]:4 *C 98.900 33.275 +*N chanx_right_out[14]:5 *C 98.900 33.320 + +*CAP +0 ropt_mt_inst_805:X 1e-06 +1 chanx_right_out[14] 0.0003154066 +2 chanx_right_out[14]:2 0.0003154066 +3 chanx_right_out[14]:3 5.438512e-05 +4 chanx_right_out[14]:4 5.438512e-05 +5 chanx_right_out[14]:5 3.182438e-05 + +*RES +0 ropt_mt_inst_805:X chanx_right_out[14]:5 0.152 +1 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +2 chanx_right_out[14]:4 chanx_right_out[14]:3 0.000515625 +3 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +4 chanx_right_out[14]:2 chanx_right_out[14] 0.0007429916 + +*END + +*D_NET chanx_right_out[8] 0.001841955 //LENGTH 13.800 LUMPCC 0.0001772636 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 97.255 49.640 +*P chanx_right_out[8] O *L 0.7423 *C 104.420 48.960 +*N chanx_right_out[8]:2 *C 94.308 48.960 +*N chanx_right_out[8]:3 *C 94.300 49.018 +*N chanx_right_out[8]:4 *C 94.300 49.595 +*N chanx_right_out[8]:5 *C 94.345 49.640 +*N chanx_right_out[8]:6 *C 97.218 49.640 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 chanx_right_out[8] 0.0006134856 +2 chanx_right_out[8]:2 0.0006134856 +3 chanx_right_out[8]:3 5.639523e-05 +4 chanx_right_out[8]:4 5.639523e-05 +5 chanx_right_out[8]:5 0.0001619651 +6 chanx_right_out[8]:6 0.0001619651 +7 chanx_right_out[8]:6 ropt_net_213:3 5.315225e-06 +8 chanx_right_out[8]:6 ropt_net_213:5 8.331659e-05 +9 chanx_right_out[8]:5 ropt_net_213:2 5.315225e-06 +10 chanx_right_out[8]:5 ropt_net_213:4 8.331659e-05 + +*RES +0 ropt_mt_inst_808:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:6 chanx_right_out[8]:5 0.002564732 +2 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.0005156251 +4 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +5 chanx_right_out[8]:2 chanx_right_out[8] 0.001463658 + +*END + +*D_NET chanx_right_out[7] 0.0009563065 //LENGTH 7.370 LUMPCC 0.0001198798 DR + +*CONN +*I ropt_mt_inst_817:X O *L 0 *C 101.855 49.640 +*P chanx_right_out[7] O *L 0.7423 *C 103.650 44.880 +*N chanx_right_out[7]:2 *C 102.588 44.880 +*N chanx_right_out[7]:3 *C 102.580 44.938 +*N chanx_right_out[7]:4 *C 102.580 49.595 +*N chanx_right_out[7]:5 *C 102.535 49.640 +*N chanx_right_out[7]:6 *C 101.892 49.640 + +*CAP +0 ropt_mt_inst_817:X 1e-06 +1 chanx_right_out[7] 9.1469e-05 +2 chanx_right_out[7]:2 9.1469e-05 +3 chanx_right_out[7]:3 0.0002423772 +4 chanx_right_out[7]:4 0.0002423772 +5 chanx_right_out[7]:5 8.386708e-05 +6 chanx_right_out[7]:6 8.386708e-05 +7 chanx_right_out[7]:4 ropt_net_214:4 5.993992e-05 +8 chanx_right_out[7]:3 ropt_net_214:5 5.993992e-05 + +*RES +0 ropt_mt_inst_817:X chanx_right_out[7]:6 0.152 +1 chanx_right_out[7]:6 chanx_right_out[7]:5 0.0005736608 +2 chanx_right_out[7]:5 chanx_right_out[7]:4 0.0045 +3 chanx_right_out[7]:4 chanx_right_out[7]:3 0.004158482 +4 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +5 chanx_right_out[7]:2 chanx_right_out[7] 0.0001664583 + +*END + +*D_NET chanx_right_out[18] 0.0004066094 //LENGTH 3.290 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 101.855 11.560 +*P chanx_right_out[18] O *L 0.7423 *C 103.650 10.880 +*N chanx_right_out[18]:2 *C 102.588 10.880 +*N chanx_right_out[18]:3 *C 102.580 10.938 +*N chanx_right_out[18]:4 *C 102.580 11.515 +*N chanx_right_out[18]:5 *C 102.535 11.560 +*N chanx_right_out[18]:6 *C 101.892 11.560 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 chanx_right_out[18] 8.931293e-05 +2 chanx_right_out[18]:2 8.931293e-05 +3 chanx_right_out[18]:3 5.194884e-05 +4 chanx_right_out[18]:4 5.194884e-05 +5 chanx_right_out[18]:5 6.15429e-05 +6 chanx_right_out[18]:6 6.15429e-05 + +*RES +0 ropt_mt_inst_821:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0005736608 +2 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.000515625 +4 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +5 chanx_right_out[18]:2 chanx_right_out[18] 0.0001664583 + +*END + +*D_NET mem_bottom_ipin_0/net_net_83 0.001349044 //LENGTH 11.185 LUMPCC 0.0002330186 DR + +*CONN +*I mem_bottom_ipin_0\/FTB_1__40:X O *L 0 *C 62.730 63.920 +*I mem_bottom_ipin_0\/BUFT_RR_125:A I *L 0.001767 *C 60.260 69.360 +*N mem_bottom_ipin_0/net_net_83:2 *C 60.297 69.360 +*N mem_bottom_ipin_0/net_net_83:3 *C 60.675 69.360 +*N mem_bottom_ipin_0/net_net_83:4 *C 60.720 69.315 +*N mem_bottom_ipin_0/net_net_83:5 *C 60.720 64.645 +*N mem_bottom_ipin_0/net_net_83:6 *C 60.675 64.600 +*N mem_bottom_ipin_0/net_net_83:7 *C 60.050 64.600 +*N mem_bottom_ipin_0/net_net_83:8 *C 60.005 64.600 +*N mem_bottom_ipin_0/net_net_83:9 *C 60.260 64.532 +*N mem_bottom_ipin_0/net_net_83:10 *C 60.260 63.965 +*N mem_bottom_ipin_0/net_net_83:11 *C 60.260 63.920 +*N mem_bottom_ipin_0/net_net_83:12 *C 62.693 63.920 + +*CAP +0 mem_bottom_ipin_0\/FTB_1__40:X 1e-06 +1 mem_bottom_ipin_0\/BUFT_RR_125:A 1e-06 +2 mem_bottom_ipin_0/net_net_83:2 4.966461e-05 +3 mem_bottom_ipin_0/net_net_83:3 4.966461e-05 +4 mem_bottom_ipin_0/net_net_83:4 0.0002588881 +5 mem_bottom_ipin_0/net_net_83:5 0.0002588881 +6 mem_bottom_ipin_0/net_net_83:6 6.200291e-05 +7 mem_bottom_ipin_0/net_net_83:7 6.200291e-05 +8 mem_bottom_ipin_0/net_net_83:8 5.520341e-05 +9 mem_bottom_ipin_0/net_net_83:9 7.430853e-05 +10 mem_bottom_ipin_0/net_net_83:10 4.96498e-05 +11 mem_bottom_ipin_0/net_net_83:11 0.0001117431 +12 mem_bottom_ipin_0/net_net_83:12 8.200973e-05 +13 mem_bottom_ipin_0/net_net_83:12 chanx_left_in[8]:3 0.000112894 +14 mem_bottom_ipin_0/net_net_83:11 chanx_left_in[8]:4 0.000112894 +15 mem_bottom_ipin_0/net_net_83:7 chanx_left_in[8]:4 3.615304e-06 +16 mem_bottom_ipin_0/net_net_83:6 chanx_left_in[8]:3 3.615304e-06 + +*RES +0 mem_bottom_ipin_0\/FTB_1__40:X mem_bottom_ipin_0/net_net_83:12 0.152 +1 mem_bottom_ipin_0/net_net_83:12 mem_bottom_ipin_0/net_net_83:11 0.002171875 +2 mem_bottom_ipin_0/net_net_83:11 mem_bottom_ipin_0/net_net_83:10 0.0045 +3 mem_bottom_ipin_0/net_net_83:10 mem_bottom_ipin_0/net_net_83:9 0.0005066965 +4 mem_bottom_ipin_0/net_net_83:7 mem_bottom_ipin_0/net_net_83:6 0.0005580357 +5 mem_bottom_ipin_0/net_net_83:8 mem_bottom_ipin_0/net_net_83:7 0.0045 +6 mem_bottom_ipin_0/net_net_83:6 mem_bottom_ipin_0/net_net_83:5 0.0045 +7 mem_bottom_ipin_0/net_net_83:5 mem_bottom_ipin_0/net_net_83:4 0.004169643 +8 mem_bottom_ipin_0/net_net_83:3 mem_bottom_ipin_0/net_net_83:2 0.0003370536 +9 mem_bottom_ipin_0/net_net_83:4 mem_bottom_ipin_0/net_net_83:3 0.0045 +10 mem_bottom_ipin_0/net_net_83:2 mem_bottom_ipin_0\/BUFT_RR_125:A 0.152 +11 mem_bottom_ipin_0/net_net_83:9 mem_bottom_ipin_0/net_net_83:8 0.000138587 + +*END + +*D_NET chanx_right_out[10] 0.001616665 //LENGTH 13.850 LUMPCC 0 DR + +*CONN +*I BUFT_P_137:X O *L 0 *C 92.655 11.560 +*P chanx_right_out[10] O *L 0.7423 *C 103.650 9.520 +*N chanx_right_out[10]:2 *C 100.288 9.520 +*N chanx_right_out[10]:3 *C 100.280 9.578 +*N chanx_right_out[10]:4 *C 100.280 11.515 +*N chanx_right_out[10]:5 *C 100.235 11.560 +*N chanx_right_out[10]:6 *C 92.693 11.560 + +*CAP +0 BUFT_P_137:X 1e-06 +1 chanx_right_out[10] 0.0001997945 +2 chanx_right_out[10]:2 0.0001997945 +3 chanx_right_out[10]:3 0.0001108316 +4 chanx_right_out[10]:4 0.0001108316 +5 chanx_right_out[10]:5 0.0004972065 +6 chanx_right_out[10]:6 0.0004972065 + +*RES +0 BUFT_P_137:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:6 chanx_right_out[10]:5 0.006734375 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.001729911 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.0005267917 + +*END + +*D_NET ropt_net_197 0.001191892 //LENGTH 10.315 LUMPCC 0.0002881119 DR + +*CONN +*I BUFT_P_144:X O *L 0 *C 93.840 27.880 +*I ropt_mt_inst_792:A I *L 0.001766 *C 97.825 23.120 +*N ropt_net_197:2 *C 97.788 23.120 +*N ropt_net_197:3 *C 97.105 23.120 +*N ropt_net_197:4 *C 97.060 23.165 +*N ropt_net_197:5 *C 97.060 25.795 +*N ropt_net_197:6 *C 97.015 25.840 +*N ropt_net_197:7 *C 94.805 25.840 +*N ropt_net_197:8 *C 94.760 25.885 +*N ropt_net_197:9 *C 94.760 27.835 +*N ropt_net_197:10 *C 94.715 27.880 +*N ropt_net_197:11 *C 93.877 27.880 + +*CAP +0 BUFT_P_144:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_197:2 5.616798e-05 +3 ropt_net_197:3 5.616798e-05 +4 ropt_net_197:4 0.0001012545 +5 ropt_net_197:5 0.0001012545 +6 ropt_net_197:6 9.353739e-05 +7 ropt_net_197:7 9.353739e-05 +8 ropt_net_197:8 0.0001208413 +9 ropt_net_197:9 0.0001208413 +10 ropt_net_197:10 7.908899e-05 +11 ropt_net_197:11 7.908899e-05 +12 ropt_net_197:7 ropt_net_212:3 9.762953e-05 +13 ropt_net_197:6 ropt_net_212:4 9.762953e-05 +14 ropt_net_197:5 ropt_net_212:5 1.765967e-06 +15 ropt_net_197:4 ropt_net_212:6 1.765967e-06 +16 ropt_net_197:9 ropt_net_199:4 2.139509e-07 +17 ropt_net_197:8 ropt_net_199:5 2.139509e-07 +18 ropt_net_197:5 ropt_net_199:4 4.444649e-05 +19 ropt_net_197:4 ropt_net_199:5 4.444649e-05 + +*RES +0 BUFT_P_144:X ropt_net_197:11 0.152 +1 ropt_net_197:11 ropt_net_197:10 0.0007477679 +2 ropt_net_197:10 ropt_net_197:9 0.0045 +3 ropt_net_197:9 ropt_net_197:8 0.001741071 +4 ropt_net_197:7 ropt_net_197:6 0.001973214 +5 ropt_net_197:8 ropt_net_197:7 0.0045 +6 ropt_net_197:6 ropt_net_197:5 0.0045 +7 ropt_net_197:5 ropt_net_197:4 0.002348214 +8 ropt_net_197:3 ropt_net_197:2 0.000609375 +9 ropt_net_197:4 ropt_net_197:3 0.0045 +10 ropt_net_197:2 ropt_mt_inst_792:A 0.152 + +*END + +*D_NET chanx_left_in[5] 0.01726355 //LENGTH 160.190 LUMPCC 0.003901643 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 68.000 +*I ropt_mt_inst_769:A I *L 0.001767 *C 93.380 4.080 +*N chanx_left_in[5]:2 *C 93.380 4.080 +*N chanx_left_in[5]:3 *C 86.985 4.080 +*N chanx_left_in[5]:4 *C 86.940 4.125 +*N chanx_left_in[5]:5 *C 86.940 9.475 +*N chanx_left_in[5]:6 *C 86.895 9.520 +*N chanx_left_in[5]:7 *C 84.640 9.520 +*N chanx_left_in[5]:8 *C 84.640 9.860 +*N chanx_left_in[5]:9 *C 48.805 9.860 +*N chanx_left_in[5]:10 *C 48.760 9.905 +*N chanx_left_in[5]:11 *C 48.760 59.700 +*N chanx_left_in[5]:12 *C 48.760 68.623 +*N chanx_left_in[5]:13 *C 48.753 68.680 +*N chanx_left_in[5]:14 *C 14.720 68.680 +*N chanx_left_in[5]:15 *C 14.720 68.000 + +*CAP +0 chanx_left_in[5] 0.0006094065 +1 ropt_mt_inst_769:A 1e-06 +2 chanx_left_in[5]:2 0.0003612785 +3 chanx_left_in[5]:3 0.0003395082 +4 chanx_left_in[5]:4 0.0002651907 +5 chanx_left_in[5]:5 0.0002651907 +6 chanx_left_in[5]:6 8.100949e-05 +7 chanx_left_in[5]:7 0.0001029394 +8 chanx_left_in[5]:8 0.001314642 +9 chanx_left_in[5]:9 0.001292712 +10 chanx_left_in[5]:10 0.002208433 +11 chanx_left_in[5]:11 0.002647905 +12 chanx_left_in[5]:12 0.0004394724 +13 chanx_left_in[5]:13 0.0013579 +14 chanx_left_in[5]:14 0.001411908 +15 chanx_left_in[5]:15 0.0006634144 +16 chanx_left_in[5] chanx_left_in[7] 0.0003424412 +17 chanx_left_in[5]:13 chanx_left_in[7]:8 0.0005298348 +18 chanx_left_in[5]:15 chanx_left_in[7]:8 0.0003424412 +19 chanx_left_in[5]:14 chanx_left_in[7] 0.0005298348 +20 chanx_left_in[5]:6 chanx_left_in[12]:4 9.268976e-05 +21 chanx_left_in[5]:9 chanx_left_in[12]:6 0.0005226589 +22 chanx_left_in[5]:9 chanx_left_in[12]:5 0.0001989571 +23 chanx_left_in[5]:8 chanx_left_in[12]:4 0.0001989571 +24 chanx_left_in[5]:8 chanx_left_in[12]:5 0.0005226589 +25 chanx_left_in[5]:7 chanx_left_in[12]:5 9.268976e-05 +26 chanx_left_in[5]:10 chanx_right_in[14]:10 5.676325e-05 +27 chanx_left_in[5]:10 chanx_right_in[14]:18 0.0002074766 +28 chanx_left_in[5]:11 chanx_right_in[14]:11 5.676325e-05 +29 chanx_left_in[5]:11 chanx_right_in[14]:19 0.0002074766 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:15 0.002113433 +1 chanx_left_in[5]:2 ropt_mt_inst_769:A 0.152 +2 chanx_left_in[5]:3 chanx_left_in[5]:2 0.005709821 +3 chanx_left_in[5]:4 chanx_left_in[5]:3 0.0045 +4 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0045 +5 chanx_left_in[5]:5 chanx_left_in[5]:4 0.004776786 +6 chanx_left_in[5]:9 chanx_left_in[5]:8 0.03199554 +7 chanx_left_in[5]:10 chanx_left_in[5]:9 0.0045 +8 chanx_left_in[5]:12 chanx_left_in[5]:11 0.007966518 +9 chanx_left_in[5]:13 chanx_left_in[5]:12 0.00341 +10 chanx_left_in[5]:8 chanx_left_in[5]:7 0.0003035715 +11 chanx_left_in[5]:7 chanx_left_in[5]:6 0.002013393 +12 chanx_left_in[5]:15 chanx_left_in[5]:14 0.0001065333 +13 chanx_left_in[5]:14 chanx_left_in[5]:13 0.005331758 +14 chanx_left_in[5]:11 chanx_left_in[5]:10 0.04445983 + +*END + +*D_NET mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001810777 //LENGTH 16.570 LUMPCC 0 DR + +*CONN +*I mux_bottom_ipin_0\/mux_l3_in_0_:X O *L 0 *C 64.575 45.560 +*I mux_bottom_ipin_0\/mux_l4_in_0_:A1 I *L 0.005458 *C 64.400 61.085 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 64.400 61.200 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 64.400 61.155 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 64.400 45.605 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 64.400 45.560 +*N mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 64.575 45.560 + +*CAP +0 mux_bottom_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_ipin_0\/mux_l4_in_0_:A1 2.572814e-05 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.572814e-05 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0008234472 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0008234472 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.713345e-05 +6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.429241e-05 + +*RES +0 mux_bottom_ipin_0\/mux_l3_in_0_:X mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_ipin_0\/mux_l4_in_0_:A1 5.078125e-05 +2 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.01388393 +5 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 9.51087e-05 + +*END + +*D_NET ropt_net_203 0.001505487 //LENGTH 9.385 LUMPCC 0.0009035274 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 11.695 14.620 +*I ropt_mt_inst_798:A I *L 0.001767 *C 3.220 14.960 +*N ropt_net_203:2 *C 3.258 14.960 +*N ropt_net_203:3 *C 3.680 14.960 +*N ropt_net_203:4 *C 3.680 14.620 +*N ropt_net_203:5 *C 11.658 14.620 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 ropt_mt_inst_798:A 1e-06 +2 ropt_net_203:2 3.1826e-05 +3 ropt_net_203:3 5.687803e-05 +4 ropt_net_203:4 0.0002681538 +5 ropt_net_203:5 0.0002431017 +6 ropt_net_203:2 chanx_right_in[16]:8 9.344079e-06 +7 ropt_net_203:5 chanx_right_in[16]:9 0.0003089091 +8 ropt_net_203:3 chanx_right_in[16]:9 9.344079e-06 +9 ropt_net_203:4 chanx_right_in[16]:8 0.0003089091 +10 ropt_net_203:5 ropt_net_171:9 3.852314e-06 +11 ropt_net_203:5 ropt_net_171:7 0.0001296583 +12 ropt_net_203:4 ropt_net_171:6 0.0001296583 +13 ropt_net_203:4 ropt_net_171:8 3.852314e-06 + +*RES +0 ropt_mt_inst_760:X ropt_net_203:5 0.152 +1 ropt_net_203:2 ropt_mt_inst_798:A 0.152 +2 ropt_net_203:5 ropt_net_203:4 0.007122769 +3 ropt_net_203:3 ropt_net_203:2 0.0003772322 +4 ropt_net_203:4 ropt_net_203:3 0.0003035715 + +*END + +*D_NET ropt_net_209 0.001541827 //LENGTH 9.780 LUMPCC 0.0006589494 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 11.695 33.320 +*I ropt_mt_inst_804:A I *L 0.001767 *C 3.220 34.000 +*N ropt_net_209:2 *C 3.220 34.000 +*N ropt_net_209:3 *C 3.220 33.955 +*N ropt_net_209:4 *C 3.220 33.365 +*N ropt_net_209:5 *C 3.265 33.320 +*N ropt_net_209:6 *C 11.658 33.320 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 ropt_mt_inst_804:A 1e-06 +2 ropt_net_209:2 3.540406e-05 +3 ropt_net_209:3 4.371643e-05 +4 ropt_net_209:4 4.371643e-05 +5 ropt_net_209:5 0.0003790205 +6 ropt_net_209:6 0.0003790205 +7 ropt_net_209:3 chanx_right_in[1]:6 1.6213e-05 +8 ropt_net_209:5 chanx_right_in[1]:7 0.0003132617 +9 ropt_net_209:4 chanx_right_in[1]:5 1.6213e-05 +10 ropt_net_209:6 chanx_right_in[1]:8 0.0003132617 + +*RES +0 ropt_mt_inst_764:X ropt_net_209:6 0.152 +1 ropt_net_209:2 ropt_mt_inst_804:A 0.152 +2 ropt_net_209:3 ropt_net_209:2 0.0045 +3 ropt_net_209:5 ropt_net_209:4 0.0045 +4 ropt_net_209:4 ropt_net_209:3 0.0005267857 +5 ropt_net_209:6 ropt_net_209:5 0.007493304 + +*END + +*D_NET ropt_net_227 0.0004989749 //LENGTH 4.435 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 94.300 3.740 +*I ropt_mt_inst_822:A I *L 0.001766 *C 97.825 4.080 +*N ropt_net_227:2 *C 97.788 4.080 +*N ropt_net_227:3 *C 95.220 4.080 +*N ropt_net_227:4 *C 95.220 3.740 +*N ropt_net_227:5 *C 94.338 3.740 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 ropt_mt_inst_822:A 1e-06 +2 ropt_net_227:2 0.0001569187 +3 ropt_net_227:3 0.0001801602 +4 ropt_net_227:4 9.156877e-05 +5 ropt_net_227:5 6.83272e-05 + +*RES +0 ropt_mt_inst_769:X ropt_net_227:5 0.152 +1 ropt_net_227:2 ropt_mt_inst_822:A 0.152 +2 ropt_net_227:5 ropt_net_227:4 0.0007879465 +3 ropt_net_227:4 ropt_net_227:3 0.0003035715 +4 ropt_net_227:3 ropt_net_227:2 0.002292411 + +*END + +*D_NET ropt_net_213 0.001802263 //LENGTH 14.775 LUMPCC 0.0001772636 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 101.855 52.360 +*I ropt_mt_inst_808:A I *L 0.001766 *C 93.380 50.320 +*N ropt_net_213:2 *C 93.418 50.320 +*N ropt_net_213:3 *C 95.220 50.320 +*N ropt_net_213:4 *C 95.220 49.980 +*N ropt_net_213:5 *C 102.995 49.980 +*N ropt_net_213:6 *C 103.040 50.025 +*N ropt_net_213:7 *C 103.040 52.315 +*N ropt_net_213:8 *C 102.995 52.360 +*N ropt_net_213:9 *C 101.892 52.360 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_213:2 0.000123046 +3 ropt_net_213:3 0.000148509 +4 ropt_net_213:4 0.0004746729 +5 ropt_net_213:5 0.0004492099 +6 ropt_net_213:6 0.0001180708 +7 ropt_net_213:7 0.0001180708 +8 ropt_net_213:8 9.570998e-05 +9 ropt_net_213:9 9.570998e-05 +10 ropt_net_213:2 chanx_right_out[8]:5 5.315225e-06 +11 ropt_net_213:5 chanx_right_out[8]:6 8.331659e-05 +12 ropt_net_213:3 chanx_right_out[8]:6 5.315225e-06 +13 ropt_net_213:4 chanx_right_out[8]:5 8.331659e-05 + +*RES +0 ropt_mt_inst_771:X ropt_net_213:9 0.152 +1 ropt_net_213:2 ropt_mt_inst_808:A 0.152 +2 ropt_net_213:5 ropt_net_213:4 0.006941965 +3 ropt_net_213:6 ropt_net_213:5 0.0045 +4 ropt_net_213:8 ropt_net_213:7 0.0045 +5 ropt_net_213:7 ropt_net_213:6 0.002044643 +6 ropt_net_213:9 ropt_net_213:8 0.000984375 +7 ropt_net_213:3 ropt_net_213:2 0.001609375 +8 ropt_net_213:4 ropt_net_213:3 0.0003035715 + +*END + +*D_NET ropt_net_205 0.0009684476 //LENGTH 7.250 LUMPCC 0.000315348 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 101.855 30.600 +*I ropt_mt_inst_800:A I *L 0.001767 *C 97.825 28.560 +*N ropt_net_205:2 *C 97.863 28.560 +*N ropt_net_205:3 *C 102.075 28.560 +*N ropt_net_205:4 *C 102.120 28.605 +*N ropt_net_205:5 *C 102.120 30.555 +*N ropt_net_205:6 *C 102.120 30.600 +*N ropt_net_205:7 *C 101.855 30.600 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_205:2 0.0001449916 +3 ropt_net_205:3 0.0001449916 +4 ropt_net_205:4 0.0001247599 +5 ropt_net_205:5 0.0001247599 +6 ropt_net_205:6 5.015973e-05 +7 ropt_net_205:7 6.143683e-05 +8 ropt_net_205:2 chanx_right_out[16]:6 5.904587e-05 +9 ropt_net_205:3 chanx_right_out[16]:5 5.904587e-05 +10 ropt_net_205:4 chanx_right_out[16]:4 8.521639e-06 +11 ropt_net_205:5 chanx_right_out[16]:3 8.521639e-06 +12 ropt_net_205:2 ropt_net_198:7 8.611302e-05 +13 ropt_net_205:3 ropt_net_198:6 8.611302e-05 +14 ropt_net_205:4 ropt_net_198:5 3.993491e-06 +15 ropt_net_205:5 ropt_net_198:4 3.993491e-06 + +*RES +0 ropt_mt_inst_779:X ropt_net_205:7 0.152 +1 ropt_net_205:2 ropt_mt_inst_800:A 0.152 +2 ropt_net_205:3 ropt_net_205:2 0.003761161 +3 ropt_net_205:4 ropt_net_205:3 0.0045 +4 ropt_net_205:6 ropt_net_205:5 0.0045 +5 ropt_net_205:5 ropt_net_205:4 0.001741072 +6 ropt_net_205:7 ropt_net_205:6 0.0001440218 + +*END + +*D_NET ropt_net_211 0.001173582 //LENGTH 10.085 LUMPCC 0.0001507595 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 101.855 8.840 +*I ropt_mt_inst_806:A I *L 0.001767 *C 93.380 9.520 +*N ropt_net_211:2 *C 93.418 9.520 +*N ropt_net_211:3 *C 97.015 9.520 +*N ropt_net_211:4 *C 97.060 9.475 +*N ropt_net_211:5 *C 97.060 8.885 +*N ropt_net_211:6 *C 97.105 8.840 +*N ropt_net_211:7 *C 101.818 8.840 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 ropt_mt_inst_806:A 1e-06 +2 ropt_net_211:2 0.0001553627 +3 ropt_net_211:3 0.0001553627 +4 ropt_net_211:4 5.307524e-05 +5 ropt_net_211:5 5.307524e-05 +6 ropt_net_211:6 0.0003019734 +7 ropt_net_211:7 0.0003019734 +8 ropt_net_211:2 ropt_net_190:4 7.356168e-05 +9 ropt_net_211:3 ropt_net_190:3 7.356168e-05 +10 ropt_net_211:6 ropt_net_190:4 1.818071e-06 +11 ropt_net_211:7 ropt_net_190:3 1.818071e-06 + +*RES +0 ropt_mt_inst_785:X ropt_net_211:7 0.152 +1 ropt_net_211:2 ropt_mt_inst_806:A 0.152 +2 ropt_net_211:3 ropt_net_211:2 0.003212054 +3 ropt_net_211:4 ropt_net_211:3 0.0045 +4 ropt_net_211:6 ropt_net_211:5 0.0045 +5 ropt_net_211:5 ropt_net_211:4 0.0005267857 +6 ropt_net_211:7 ropt_net_211:6 0.004207589 + +*END + +*D_NET chanx_right_out[3] 0.0005762761 //LENGTH 4.650 LUMPCC 0.0001243069 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 101.855 36.040 +*P chanx_right_out[3] O *L 0.7423 *C 103.650 34.000 +*N chanx_right_out[3]:2 *C 102.588 34.000 +*N chanx_right_out[3]:3 *C 102.580 34.058 +*N chanx_right_out[3]:4 *C 102.580 35.995 +*N chanx_right_out[3]:5 *C 102.535 36.040 +*N chanx_right_out[3]:6 *C 101.892 36.040 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 chanx_right_out[3] 9.117853e-05 +2 chanx_right_out[3]:2 9.117853e-05 +3 chanx_right_out[3]:3 7.120609e-05 +4 chanx_right_out[3]:4 7.120609e-05 +5 chanx_right_out[3]:5 6.309996e-05 +6 chanx_right_out[3]:6 6.309996e-05 +7 chanx_right_out[3]:4 ropt_net_210:5 6.215347e-05 +8 chanx_right_out[3]:3 ropt_net_210:4 6.215347e-05 + +*RES +0 ropt_mt_inst_788:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:6 chanx_right_out[3]:5 0.0005736608 +2 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +3 chanx_right_out[3]:4 chanx_right_out[3]:3 0.001729911 +4 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +5 chanx_right_out[3]:2 chanx_right_out[3] 0.0001664583 + +*END + +*D_NET chanx_right_out[16] 0.0008290907 //LENGTH 6.245 LUMPCC 0.000135135 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 98.900 27.880 +*P chanx_right_out[16] O *L 0.7423 *C 103.650 28.560 +*N chanx_right_out[16]:2 *C 102.588 28.560 +*N chanx_right_out[16]:3 *C 102.580 28.503 +*N chanx_right_out[16]:4 *C 102.580 27.925 +*N chanx_right_out[16]:5 *C 102.535 27.880 +*N chanx_right_out[16]:6 *C 98.938 27.880 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 chanx_right_out[16] 9.14985e-05 +2 chanx_right_out[16]:2 9.14985e-05 +3 chanx_right_out[16]:3 5.392896e-05 +4 chanx_right_out[16]:4 5.392896e-05 +5 chanx_right_out[16]:5 0.0002010504 +6 chanx_right_out[16]:6 0.0002010504 +7 chanx_right_out[16]:6 ropt_net_205:2 5.904587e-05 +8 chanx_right_out[16]:5 ropt_net_205:3 5.904587e-05 +9 chanx_right_out[16]:4 ropt_net_205:4 8.521639e-06 +10 chanx_right_out[16]:3 ropt_net_205:5 8.521639e-06 + +*RES +0 ropt_mt_inst_800:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:6 chanx_right_out[16]:5 0.003212054 +2 chanx_right_out[16]:5 chanx_right_out[16]:4 0.0045 +3 chanx_right_out[16]:4 chanx_right_out[16]:3 0.0005156251 +4 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +5 chanx_right_out[16]:2 chanx_right_out[16] 0.0001664583 + +*END + +*D_NET chanx_left_out[2] 0.0007631594 //LENGTH 4.355 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 4.140 71.400 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 72.080 +*N chanx_left_out[2]:2 *C 1.840 72.080 +*N chanx_left_out[2]:3 *C 1.840 71.400 +*N chanx_left_out[2]:4 *C 4.133 71.400 +*N chanx_left_out[2]:5 *C 4.140 71.400 +*N chanx_left_out[2]:6 *C 4.140 71.400 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 chanx_left_out[2] 8.017512e-05 +2 chanx_left_out[2]:2 0.0001359119 +3 chanx_left_out[2]:3 0.0002692655 +4 chanx_left_out[2]:4 0.0002135287 +5 chanx_left_out[2]:5 3.418821e-05 +6 chanx_left_out[2]:6 2.908991e-05 + +*RES +0 ropt_mt_inst_801:X chanx_left_out[2]:6 0.152 +1 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0045 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.00341 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.0003591583 +4 chanx_left_out[2]:2 chanx_left_out[2] 9.556665e-05 +5 chanx_left_out[2]:3 chanx_left_out[2]:2 0.0001065333 + +*END + +*D_NET chanx_left_out[11] 0.0008068393 //LENGTH 6.710 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 4.140 34.340 +*P chanx_left_out[11] O *L 0.7423 *C 1.305 31.280 +*N chanx_left_out[11]:2 *C 2.292 31.280 +*N chanx_left_out[11]:3 *C 2.300 31.338 +*N chanx_left_out[11]:4 *C 2.300 34.295 +*N chanx_left_out[11]:5 *C 2.345 34.340 +*N chanx_left_out[11]:6 *C 4.103 34.340 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chanx_left_out[11] 9.915811e-05 +2 chanx_left_out[11]:2 9.915811e-05 +3 chanx_left_out[11]:3 0.0001768722 +4 chanx_left_out[11]:4 0.0001768722 +5 chanx_left_out[11]:5 0.0001268894 +6 chanx_left_out[11]:6 0.0001268894 + +*RES +0 ropt_mt_inst_804:X chanx_left_out[11]:6 0.152 +1 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 +2 chanx_left_out[11]:2 chanx_left_out[11] 0.0001547083 +3 chanx_left_out[11]:5 chanx_left_out[11]:4 0.0045 +4 chanx_left_out[11]:4 chanx_left_out[11]:3 0.002640625 +5 chanx_left_out[11]:6 chanx_left_out[11]:5 0.001569197 + +*END + +*D_NET ropt_net_191 0.0007404405 //LENGTH 6.765 LUMPCC 0.0001288651 DR + +*CONN +*I BUFT_RR_53:X O *L 0 *C 94.760 41.480 +*I ropt_mt_inst_786:A I *L 0.001766 *C 93.380 36.720 +*N ropt_net_191:2 *C 93.418 36.720 +*N ropt_net_191:3 *C 94.715 36.720 +*N ropt_net_191:4 *C 94.760 36.765 +*N ropt_net_191:5 *C 94.760 41.435 +*N ropt_net_191:6 *C 94.760 41.480 + +*CAP +0 BUFT_RR_53:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_191:2 8.757701e-05 +3 ropt_net_191:3 8.757701e-05 +4 ropt_net_191:4 0.0002012305 +5 ropt_net_191:5 0.0002012305 +6 ropt_net_191:6 3.196033e-05 +7 ropt_net_191:5 chanx_left_in[0]:6 6.443253e-05 +8 ropt_net_191:4 chanx_left_in[0]:5 6.443253e-05 + +*RES +0 BUFT_RR_53:X ropt_net_191:6 0.152 +1 ropt_net_191:6 ropt_net_191:5 0.0045 +2 ropt_net_191:5 ropt_net_191:4 0.004169643 +3 ropt_net_191:3 ropt_net_191:2 0.001158482 +4 ropt_net_191:4 ropt_net_191:3 0.0045 +5 ropt_net_191:2 ropt_mt_inst_786:A 0.152 + +*END + +*D_NET chanx_left_out[16] 0.001858021 //LENGTH 14.680 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_811:X O *L 0 *C 11.695 17.000 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 13.600 +*N chanx_left_out[16]:2 *C 11.033 13.600 +*N chanx_left_out[16]:3 *C 11.040 13.658 +*N chanx_left_out[16]:4 *C 11.040 16.955 +*N chanx_left_out[16]:5 *C 11.085 17.000 +*N chanx_left_out[16]:6 *C 11.658 17.000 + +*CAP +0 ropt_mt_inst_811:X 1e-06 +1 chanx_left_out[16] 0.0006614117 +2 chanx_left_out[16]:2 0.0006614117 +3 chanx_left_out[16]:3 0.0002090738 +4 chanx_left_out[16]:4 0.0002090738 +5 chanx_left_out[16]:5 5.802521e-05 +6 chanx_left_out[16]:6 5.802521e-05 + +*RES +0 ropt_mt_inst_811:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:6 chanx_left_out[16]:5 0.0005111608 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.002944197 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 0.001535725 + +*END + +*D_NET chanx_left_out[12] 0.002178861 //LENGTH 13.920 LUMPCC 0.0006805525 DR + +*CONN +*I ropt_mt_inst_818:X O *L 0 *C 11.695 49.640 +*P chanx_left_out[12] O *L 0.7423 *C 1.230 47.600 +*N chanx_left_out[12]:2 *C 1.840 47.600 +*N chanx_left_out[12]:3 *C 1.840 48.280 +*N chanx_left_out[12]:4 *C 11.033 48.280 +*N chanx_left_out[12]:5 *C 11.040 48.338 +*N chanx_left_out[12]:6 *C 11.040 49.595 +*N chanx_left_out[12]:7 *C 11.085 49.640 +*N chanx_left_out[12]:8 *C 11.658 49.640 + +*CAP +0 ropt_mt_inst_818:X 1e-06 +1 chanx_left_out[12] 6.774426e-05 +2 chanx_left_out[12]:2 0.0001197117 +3 chanx_left_out[12]:3 0.0005137554 +4 chanx_left_out[12]:4 0.000461788 +5 chanx_left_out[12]:5 0.0001077365 +6 chanx_left_out[12]:6 0.0001077365 +7 chanx_left_out[12]:7 5.941793e-05 +8 chanx_left_out[12]:8 5.941793e-05 +9 chanx_left_out[12]:4 chanx_right_in[12]:6 0.0003340098 +10 chanx_left_out[12]:2 chanx_right_in[12]:4 6.266429e-06 +11 chanx_left_out[12]:3 chanx_right_in[12]:3 6.266429e-06 +12 chanx_left_out[12]:3 chanx_right_in[12]:5 0.0003340098 + +*RES +0 ropt_mt_inst_818:X chanx_left_out[12]:8 0.152 +1 chanx_left_out[12]:8 chanx_left_out[12]:7 0.0005111608 +2 chanx_left_out[12]:7 chanx_left_out[12]:6 0.0045 +3 chanx_left_out[12]:6 chanx_left_out[12]:5 0.001122768 +4 chanx_left_out[12]:5 chanx_left_out[12]:4 0.00341 +5 chanx_left_out[12]:4 chanx_left_out[12]:3 0.001440158 +6 chanx_left_out[12]:2 chanx_left_out[12] 9.556666e-05 +7 chanx_left_out[12]:3 chanx_left_out[12]:2 0.0001065333 + +*END + +*D_NET chanx_right_out[15] 0.0006529265 //LENGTH 4.370 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_825:X O *L 0 *C 101.855 67.320 +*P chanx_right_out[15] O *L 0.7423 *C 103.650 69.360 +*N chanx_right_out[15]:2 *C 102.128 69.360 +*N chanx_right_out[15]:3 *C 102.120 69.303 +*N chanx_right_out[15]:4 *C 102.120 67.365 +*N chanx_right_out[15]:5 *C 102.120 67.320 +*N chanx_right_out[15]:6 *C 101.855 67.320 + +*CAP +0 ropt_mt_inst_825:X 1e-06 +1 chanx_right_out[15] 0.0001326532 +2 chanx_right_out[15]:2 0.0001326532 +3 chanx_right_out[15]:3 0.0001359229 +4 chanx_right_out[15]:4 0.0001359229 +5 chanx_right_out[15]:5 5.188422e-05 +6 chanx_right_out[15]:6 6.289001e-05 + +*RES +0 ropt_mt_inst_825:X chanx_right_out[15]:6 0.152 +1 chanx_right_out[15]:6 chanx_right_out[15]:5 0.0001440218 +2 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +3 chanx_right_out[15]:4 chanx_right_out[15]:3 0.001729911 +4 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +5 chanx_right_out[15]:2 chanx_right_out[15] 0.000238525 + +*END + +*D_NET ropt_net_166 0.002958602 //LENGTH 29.235 LUMPCC 0 DR + +*CONN +*I BUFT_P_122:X O *L 0 *C 18.665 11.560 +*I ropt_mt_inst_761:A I *L 0.001766 *C 7.820 4.080 +*N ropt_net_166:2 *C 7.783 4.080 +*N ropt_net_166:3 *C 6.025 4.080 +*N ropt_net_166:4 *C 5.980 4.035 +*N ropt_net_166:5 *C 5.980 1.745 +*N ropt_net_166:6 *C 5.980 1.700 +*N ropt_net_166:7 *C 5.980 1.360 +*N ropt_net_166:8 *C 17.480 1.360 +*N ropt_net_166:9 *C 17.480 1.700 +*N ropt_net_166:10 *C 17.480 1.745 +*N ropt_net_166:11 *C 17.480 11.515 +*N ropt_net_166:12 *C 17.525 11.560 +*N ropt_net_166:13 *C 18.628 11.560 + +*CAP +0 BUFT_P_122:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_166:2 0.000121683 +3 ropt_net_166:3 0.000121683 +4 ropt_net_166:4 0.000135978 +5 ropt_net_166:5 0.000135978 +6 ropt_net_166:6 5.63008e-05 +7 ropt_net_166:7 0.0006141676 +8 ropt_net_166:8 0.0006120485 +9 ropt_net_166:9 5.140259e-05 +10 ropt_net_166:10 0.0004631483 +11 ropt_net_166:11 0.0004631483 +12 ropt_net_166:12 9.053222e-05 +13 ropt_net_166:13 9.053222e-05 + +*RES +0 BUFT_P_122:X ropt_net_166:13 0.152 +1 ropt_net_166:13 ropt_net_166:12 0.0009843751 +2 ropt_net_166:12 ropt_net_166:11 0.0045 +3 ropt_net_166:11 ropt_net_166:10 0.008723214 +4 ropt_net_166:9 ropt_net_166:8 0.0003035715 +5 ropt_net_166:10 ropt_net_166:9 0.0045 +6 ropt_net_166:6 ropt_net_166:5 0.0045 +7 ropt_net_166:5 ropt_net_166:4 0.002044643 +8 ropt_net_166:3 ropt_net_166:2 0.001569197 +9 ropt_net_166:4 ropt_net_166:3 0.0045 +10 ropt_net_166:2 ropt_mt_inst_761:A 0.152 +11 ropt_net_166:7 ropt_net_166:6 0.0003035715 +12 ropt_net_166:8 ropt_net_166:7 0.01026786 + +*END + +*D_NET ropt_net_176 0.001950695 //LENGTH 17.605 LUMPCC 0.0001947899 DR + +*CONN +*I BUFT_P_135:X O *L 0 *C 100.280 63.580 +*I ropt_mt_inst_771:A I *L 0.001766 *C 97.825 53.040 +*N ropt_net_176:2 *C 97.863 53.040 +*N ropt_net_176:3 *C 102.075 53.040 +*N ropt_net_176:4 *C 102.120 53.085 +*N ropt_net_176:5 *C 102.120 63.535 +*N ropt_net_176:6 *C 102.075 63.580 +*N ropt_net_176:7 *C 100.318 63.580 + +*CAP +0 BUFT_P_135:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_176:2 0.0002491441 +3 ropt_net_176:3 0.0002491441 +4 ropt_net_176:4 0.0005032744 +5 ropt_net_176:5 0.0005032744 +6 ropt_net_176:6 0.0001245344 +7 ropt_net_176:7 0.0001245344 +8 ropt_net_176:5 chanx_right_out[19]:4 9.739496e-05 +9 ropt_net_176:4 chanx_right_out[19]:3 9.739496e-05 + +*RES +0 BUFT_P_135:X ropt_net_176:7 0.152 +1 ropt_net_176:7 ropt_net_176:6 0.001569197 +2 ropt_net_176:6 ropt_net_176:5 0.0045 +3 ropt_net_176:5 ropt_net_176:4 0.009330357 +4 ropt_net_176:3 ropt_net_176:2 0.003761161 +5 ropt_net_176:4 ropt_net_176:3 0.0045 +6 ropt_net_176:2 ropt_mt_inst_771:A 0.152 + +*END + +*D_NET chanx_left_out[0] 0.001471468 //LENGTH 12.850 LUMPCC 0.0003046093 DR + +*CONN +*I BUFT_P_147:X O *L 0 *C 12.235 72.420 +*P chanx_left_out[0] O *L 0.7423 *C 2.300 74.870 +*N chanx_left_out[0]:2 *C 2.300 72.465 +*N chanx_left_out[0]:3 *C 2.345 72.420 +*N chanx_left_out[0]:4 *C 12.197 72.420 + +*CAP +0 BUFT_P_147:X 1e-06 +1 chanx_left_out[0] 0.0001257862 +2 chanx_left_out[0]:2 0.0001257862 +3 chanx_left_out[0]:3 0.000457143 +4 chanx_left_out[0]:4 0.000457143 +5 chanx_left_out[0]:3 ropt_net_206:2 0.0001523046 +6 chanx_left_out[0]:4 ropt_net_206:3 0.0001523046 + +*RES +0 BUFT_P_147:X chanx_left_out[0]:4 0.152 +1 chanx_left_out[0]:3 chanx_left_out[0]:2 0.0045 +2 chanx_left_out[0]:2 chanx_left_out[0] 0.002147322 +3 chanx_left_out[0]:4 chanx_left_out[0]:3 0.008796875 + +*END + +*D_NET ropt_net_171 0.002826997 //LENGTH 21.970 LUMPCC 0.001232818 DR + +*CONN +*I BUFT_P_154:X O *L 0 *C 12.420 15.640 +*I ropt_mt_inst_766:A I *L 0.001766 *C 3.220 4.080 +*N ropt_net_171:2 *C 3.258 4.080 +*N ropt_net_171:3 *C 4.095 4.080 +*N ropt_net_171:4 *C 4.140 4.125 +*N ropt_net_171:5 *C 4.140 14.915 +*N ropt_net_171:6 *C 4.185 14.960 +*N ropt_net_171:7 *C 7.360 14.960 +*N ropt_net_171:8 *C 7.360 15.640 +*N ropt_net_171:9 *C 12.383 15.640 + +*CAP +0 BUFT_P_154:X 1e-06 +1 ropt_mt_inst_766:A 1e-06 +2 ropt_net_171:2 6.165445e-05 +3 ropt_net_171:3 6.165445e-05 +4 ropt_net_171:4 0.0003611086 +5 ropt_net_171:5 0.0003611086 +6 ropt_net_171:6 0.0001205465 +7 ropt_net_171:7 0.0001486812 +8 ropt_net_171:8 0.0002527798 +9 ropt_net_171:9 0.0002246451 +10 ropt_net_171:4 prog_clk[0] 0.0001120439 +11 ropt_net_171:5 prog_clk[0]:25 0.0001120439 +12 ropt_net_171:6 ropt_net_203:4 0.0001296583 +13 ropt_net_171:9 ropt_net_203:5 3.852314e-06 +14 ropt_net_171:7 ropt_net_203:5 0.0001296583 +15 ropt_net_171:8 ropt_net_203:4 3.852314e-06 +16 ropt_net_171:4 ropt_net_208:5 2.765129e-05 +17 ropt_net_171:4 ropt_net_208:8 5.28381e-05 +18 ropt_net_171:4 ropt_net_208:11 2.970168e-06 +19 ropt_net_171:5 ropt_net_208:4 2.765129e-05 +20 ropt_net_171:5 ropt_net_208:7 5.28381e-05 +21 ropt_net_171:5 ropt_net_208:10 2.970168e-06 +22 ropt_net_171:4 chanx_left_out[18]:3 8.124426e-05 +23 ropt_net_171:6 chanx_left_out[18]:6 1.215019e-05 +24 ropt_net_171:5 chanx_left_out[18]:4 8.124426e-05 +25 ropt_net_171:7 chanx_left_out[18]:5 1.215019e-05 +26 ropt_net_171:9 ropt_net_165:4 0.0001806692 +27 ropt_net_171:7 ropt_net_165:2 1.333155e-05 +28 ropt_net_171:8 ropt_net_165:3 0.0001940007 + +*RES +0 BUFT_P_154:X ropt_net_171:9 0.152 +1 ropt_net_171:2 ropt_mt_inst_766:A 0.152 +2 ropt_net_171:3 ropt_net_171:2 0.0007477679 +3 ropt_net_171:4 ropt_net_171:3 0.0045 +4 ropt_net_171:6 ropt_net_171:5 0.0045 +5 ropt_net_171:5 ropt_net_171:4 0.00963393 +6 ropt_net_171:9 ropt_net_171:8 0.004484375 +7 ropt_net_171:7 ropt_net_171:6 0.002834822 +8 ropt_net_171:8 ropt_net_171:7 0.0006071429 + +*END + +*D_NET chanx_left_in[6] 0.01470407 //LENGTH 145.275 LUMPCC 0.001357493 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 57.120 +*I ropt_mt_inst_780:A I *L 0.001767 *C 93.380 6.800 +*N chanx_left_in[6]:2 *C 93.380 6.800 +*N chanx_left_in[6]:3 *C 93.380 6.460 +*N chanx_left_in[6]:4 *C 91.125 6.460 +*N chanx_left_in[6]:5 *C 91.080 6.505 +*N chanx_left_in[6]:6 *C 91.080 12.183 +*N chanx_left_in[6]:7 *C 91.073 12.240 +*N chanx_left_in[6]:8 *C 64.555 12.240 +*N chanx_left_in[6]:9 *C 14.728 12.240 +*N chanx_left_in[6]:10 *C 14.720 12.298 +*N chanx_left_in[6]:11 *C 14.720 57.062 +*N chanx_left_in[6]:12 *C 14.713 57.120 + +*CAP +0 chanx_left_in[6] 0.0005807197 +1 ropt_mt_inst_780:A 1e-06 +2 chanx_left_in[6]:2 5.604277e-05 +3 chanx_left_in[6]:3 0.0001901586 +4 chanx_left_in[6]:4 0.0001626853 +5 chanx_left_in[6]:5 0.0002823349 +6 chanx_left_in[6]:6 0.0002823349 +7 chanx_left_in[6]:7 0.00115205 +8 chanx_left_in[6]:8 0.003407483 +9 chanx_left_in[6]:9 0.002255433 +10 chanx_left_in[6]:10 0.002197808 +11 chanx_left_in[6]:11 0.002197808 +12 chanx_left_in[6]:12 0.0005807197 +13 chanx_left_in[6] chanx_left_in[3] 0.0003347809 +14 chanx_left_in[6]:10 chanx_left_in[3]:11 5.970903e-05 +15 chanx_left_in[6]:11 chanx_left_in[3]:12 5.970903e-05 +16 chanx_left_in[6]:12 chanx_left_in[3]:13 0.0003347809 +17 chanx_left_in[6]:7 chanx_right_in[15] 3.070008e-05 +18 chanx_left_in[6]:7 chanx_right_in[15]:10 9.40965e-05 +19 chanx_left_in[6]:10 chanx_right_in[15]:4 7.404753e-06 +20 chanx_left_in[6]:9 chanx_right_in[15]:9 0.000152055 +21 chanx_left_in[6]:11 chanx_right_in[15]:3 7.404753e-06 +22 chanx_left_in[6]:8 chanx_right_in[15]:9 9.40965e-05 +23 chanx_left_in[6]:8 chanx_right_in[15]:10 0.0001827551 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:12 0.002112258 +1 chanx_left_in[6]:2 ropt_mt_inst_780:A 0.152 +2 chanx_left_in[6]:4 chanx_left_in[6]:3 0.002013393 +3 chanx_left_in[6]:5 chanx_left_in[6]:4 0.0045 +4 chanx_left_in[6]:6 chanx_left_in[6]:5 0.005069196 +5 chanx_left_in[6]:7 chanx_left_in[6]:6 0.00341 +6 chanx_left_in[6]:10 chanx_left_in[6]:9 0.00341 +7 chanx_left_in[6]:9 chanx_left_in[6]:8 0.007806308 +8 chanx_left_in[6]:11 chanx_left_in[6]:10 0.03996876 +9 chanx_left_in[6]:12 chanx_left_in[6]:11 0.00341 +10 chanx_left_in[6]:3 chanx_left_in[6]:2 0.0003035715 +11 chanx_left_in[6]:8 chanx_left_in[6]:7 0.004154408 + +*END + +*D_NET chanx_left_in[7] 0.01284537 //LENGTH 116.745 LUMPCC 0.004592493 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 66.640 +*I ropt_mt_inst_759:A I *L 0.001767 *C 93.380 47.600 +*N chanx_left_in[7]:2 *C 93.403 47.628 +*N chanx_left_in[7]:3 *C 93.415 47.940 +*N chanx_left_in[7]:4 *C 95.635 47.940 +*N chanx_left_in[7]:5 *C 95.680 47.985 +*N chanx_left_in[7]:6 *C 95.680 66.583 +*N chanx_left_in[7]:7 *C 95.672 66.640 +*N chanx_left_in[7]:8 *C 51.230 66.640 + +*CAP +0 chanx_left_in[7] 0.001529313 +1 ropt_mt_inst_759:A 1e-06 +2 chanx_left_in[7]:2 3.190438e-05 +3 chanx_left_in[7]:3 0.0001812904 +4 chanx_left_in[7]:4 0.000149386 +5 chanx_left_in[7]:5 0.0007242301 +6 chanx_left_in[7]:6 0.0007242301 +7 chanx_left_in[7]:7 0.001691106 +8 chanx_left_in[7]:8 0.003220418 +9 chanx_left_in[7] chanx_left_in[5] 0.0003424412 +10 chanx_left_in[7] chanx_left_in[5]:14 0.0005298348 +11 chanx_left_in[7]:8 chanx_left_in[5]:13 0.0005298348 +12 chanx_left_in[7]:8 chanx_left_in[5]:15 0.0003424412 +13 chanx_left_in[7]:5 chanx_left_in[13]:5 0.000364898 +14 chanx_left_in[7]:6 chanx_left_in[13]:4 0.000364898 +15 chanx_left_in[7] chanx_left_in[14] 0.0004176234 +16 chanx_left_in[7]:8 chanx_left_in[14]:11 0.0004176234 +17 chanx_left_in[7]:5 chanx_right_in[1]:17 3.727538e-06 +18 chanx_left_in[7]:6 chanx_right_in[1]:18 3.727538e-06 +19 chanx_left_in[7]:7 chanx_right_in[1]:16 0.0006377213 +20 chanx_left_in[7]:8 chanx_right_in[1]:15 0.0006377213 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:8 0.007833333 +1 chanx_left_in[7]:2 ropt_mt_inst_759:A 0.152 +2 chanx_left_in[7]:4 chanx_left_in[7]:3 0.001982143 +3 chanx_left_in[7]:5 chanx_left_in[7]:4 0.0045 +4 chanx_left_in[7]:6 chanx_left_in[7]:5 0.01660491 +5 chanx_left_in[7]:7 chanx_left_in[7]:6 0.00341 +6 chanx_left_in[7]:3 chanx_left_in[7]:2 0.0002111487 +7 chanx_left_in[7]:8 chanx_left_in[7]:7 0.006962658 + +*END + +*D_NET chanx_left_in[8] 0.01097488 //LENGTH 103.115 LUMPCC 0.0002330186 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 58.480 +*I BUFT_P_135:A I *L 0.001776 *C 97.980 63.920 +*N chanx_left_in[8]:2 *C 97.980 63.920 +*N chanx_left_in[8]:3 *C 97.980 63.580 +*N chanx_left_in[8]:4 *C 57.660 63.580 +*N chanx_left_in[8]:5 *C 7.865 63.580 +*N chanx_left_in[8]:6 *C 7.820 63.535 +*N chanx_left_in[8]:7 *C 7.820 58.538 +*N chanx_left_in[8]:8 *C 7.812 58.480 + +*CAP +0 chanx_left_in[8] 0.0004475537 +1 BUFT_P_135:A 1e-06 +2 chanx_left_in[8]:2 5.910965e-05 +3 chanx_left_in[8]:3 0.002124273 +4 chanx_left_in[8]:4 0.004586153 +5 chanx_left_in[8]:5 0.002490674 +6 chanx_left_in[8]:6 0.0002927711 +7 chanx_left_in[8]:7 0.0002927711 +8 chanx_left_in[8]:8 0.0004475537 +9 chanx_left_in[8]:3 mem_bottom_ipin_0/net_net_83:12 0.000112894 +10 chanx_left_in[8]:3 mem_bottom_ipin_0/net_net_83:6 3.615304e-06 +11 chanx_left_in[8]:4 mem_bottom_ipin_0/net_net_83:11 0.000112894 +12 chanx_left_in[8]:4 mem_bottom_ipin_0/net_net_83:7 3.615304e-06 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:8 0.001031258 +1 chanx_left_in[8]:2 BUFT_P_135:A 0.152 +2 chanx_left_in[8]:5 chanx_left_in[8]:4 0.04445983 +3 chanx_left_in[8]:6 chanx_left_in[8]:5 0.0045 +4 chanx_left_in[8]:7 chanx_left_in[8]:6 0.004462054 +5 chanx_left_in[8]:8 chanx_left_in[8]:7 0.00341 +6 chanx_left_in[8]:3 chanx_left_in[8]:2 0.0003035715 +7 chanx_left_in[8]:4 chanx_left_in[8]:3 0.03600001 + +*END + +*D_NET chanx_left_in[9] 0.01454035 //LENGTH 141.285 LUMPCC 0 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 17.680 +*I BUFT_P_136:A I *L 0.001767 *C 88.780 69.360 +*N chanx_left_in[9]:2 *C 88.743 69.360 +*N chanx_left_in[9]:3 *C 68.540 69.360 +*N chanx_left_in[9]:4 *C 68.540 69.700 +*N chanx_left_in[9]:5 *C 59.800 69.700 +*N chanx_left_in[9]:6 *C 59.800 69.360 +*N chanx_left_in[9]:7 *C 11.545 69.360 +*N chanx_left_in[9]:8 *C 11.500 69.315 +*N chanx_left_in[9]:9 *C 11.500 17.738 +*N chanx_left_in[9]:10 *C 11.492 17.680 + +*CAP +0 chanx_left_in[9] 0.0006124227 +1 BUFT_P_136:A 1e-06 +2 chanx_left_in[9]:2 0.001007025 +3 chanx_left_in[9]:3 0.00102887 +4 chanx_left_in[9]:4 0.0005567497 +5 chanx_left_in[9]:5 0.0005573552 +6 chanx_left_in[9]:6 0.002403272 +7 chanx_left_in[9]:7 0.002380821 +8 chanx_left_in[9]:8 0.002690206 +9 chanx_left_in[9]:9 0.002690206 +10 chanx_left_in[9]:10 0.0006124227 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:10 0.001607792 +1 chanx_left_in[9]:2 BUFT_P_136:A 0.152 +2 chanx_left_in[9]:7 chanx_left_in[9]:6 0.04308483 +3 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0045 +4 chanx_left_in[9]:9 chanx_left_in[9]:8 0.04605135 +5 chanx_left_in[9]:10 chanx_left_in[9]:9 0.00341 +6 chanx_left_in[9]:6 chanx_left_in[9]:5 0.0003035715 +7 chanx_left_in[9]:5 chanx_left_in[9]:4 0.007803572 +8 chanx_left_in[9]:4 chanx_left_in[9]:3 0.0003035715 +9 chanx_left_in[9]:3 chanx_left_in[9]:2 0.01803795 + +*END + +*D_NET chanx_right_in[12] 0.01302444 //LENGTH 113.455 LUMPCC 0.003865739 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 103.650 55.760 +*I ropt_mt_inst_774:A I *L 0.001767 *C 3.220 50.320 +*N chanx_right_in[12]:2 *C 3.220 50.320 +*N chanx_right_in[12]:3 *C 3.220 50.275 +*N chanx_right_in[12]:4 *C 3.220 47.657 +*N chanx_right_in[12]:5 *C 3.228 47.600 +*N chanx_right_in[12]:6 *C 8.732 47.600 +*N chanx_right_in[12]:7 *C 8.740 47.600 +*N chanx_right_in[12]:8 *C 8.785 47.600 +*N chanx_right_in[12]:9 *C 23.415 47.600 +*N chanx_right_in[12]:10 *C 23.460 47.645 +*N chanx_right_in[12]:11 *C 23.460 50.275 +*N chanx_right_in[12]:12 *C 23.505 50.320 +*N chanx_right_in[12]:13 *C 24.795 50.320 +*N chanx_right_in[12]:14 *C 24.840 50.365 +*N chanx_right_in[12]:15 *C 24.840 55.703 +*N chanx_right_in[12]:16 *C 24.848 55.760 +*N chanx_right_in[12]:17 *C 74.675 55.760 + +*CAP +0 chanx_right_in[12] 0.001204666 +1 ropt_mt_inst_774:A 1e-06 +2 chanx_right_in[12]:2 2.943621e-05 +3 chanx_right_in[12]:3 0.0001758407 +4 chanx_right_in[12]:4 0.0001758407 +5 chanx_right_in[12]:5 0.0002238147 +6 chanx_right_in[12]:6 0.0002238147 +7 chanx_right_in[12]:7 3.703442e-05 +8 chanx_right_in[12]:8 0.0006401431 +9 chanx_right_in[12]:9 0.0006401431 +10 chanx_right_in[12]:10 0.0001448762 +11 chanx_right_in[12]:11 0.0001448762 +12 chanx_right_in[12]:12 9.376651e-05 +13 chanx_right_in[12]:13 9.376651e-05 +14 chanx_right_in[12]:14 0.0002807905 +15 chanx_right_in[12]:15 0.0002807905 +16 chanx_right_in[12]:16 0.001781719 +17 chanx_right_in[12]:17 0.002986384 +18 chanx_right_in[12]:8 chanx_left_in[3]:10 0.0002897068 +19 chanx_right_in[12]:9 chanx_left_in[3]:9 0.0002897068 +20 chanx_right_in[12] chanx_left_in[4]:13 3.645236e-05 +21 chanx_right_in[12]:14 chanx_left_in[4]:16 7.196902e-06 +22 chanx_right_in[12]:15 chanx_left_in[4]:17 7.196902e-06 +23 chanx_right_in[12]:16 chanx_left_in[4]:14 0.0002768426 +24 chanx_right_in[12]:16 chanx_left_in[4]:16 0.0001254062 +25 chanx_right_in[12]:17 chanx_left_in[4]:13 0.0002768426 +26 chanx_right_in[12]:17 chanx_left_in[4]:14 3.645236e-05 +27 chanx_right_in[12]:17 chanx_left_in[4]:15 0.0001254062 +28 chanx_right_in[12] chanx_right_in[8] 0.0002754554 +29 chanx_right_in[12] chanx_right_in[8]:7 6.611618e-05 +30 chanx_right_in[12]:16 chanx_right_in[8]:6 0.0005154171 +31 chanx_right_in[12]:17 chanx_right_in[8]:6 6.611618e-05 +32 chanx_right_in[12]:17 chanx_right_in[8]:7 0.0007908725 +33 chanx_right_in[12]:3 chanx_left_out[12]:3 6.266429e-06 +34 chanx_right_in[12]:4 chanx_left_out[12]:2 6.266429e-06 +35 chanx_right_in[12]:5 chanx_left_out[12]:3 0.0003340098 +36 chanx_right_in[12]:6 chanx_left_out[12]:4 0.0003340098 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:17 0.004539417 +1 chanx_right_in[12]:2 ropt_mt_inst_774:A 0.152 +2 chanx_right_in[12]:3 chanx_right_in[12]:2 0.0045 +3 chanx_right_in[12]:4 chanx_right_in[12]:3 0.002337054 +4 chanx_right_in[12]:5 chanx_right_in[12]:4 0.00341 +5 chanx_right_in[12]:7 chanx_right_in[12]:6 0.00341 +6 chanx_right_in[12]:6 chanx_right_in[12]:5 0.00086245 +7 chanx_right_in[12]:8 chanx_right_in[12]:7 0.0045 +8 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0130625 +9 chanx_right_in[12]:10 chanx_right_in[12]:9 0.0045 +10 chanx_right_in[12]:12 chanx_right_in[12]:11 0.0045 +11 chanx_right_in[12]:11 chanx_right_in[12]:10 0.002348214 +12 chanx_right_in[12]:13 chanx_right_in[12]:12 0.001151786 +13 chanx_right_in[12]:14 chanx_right_in[12]:13 0.0045 +14 chanx_right_in[12]:15 chanx_right_in[12]:14 0.004765625 +15 chanx_right_in[12]:16 chanx_right_in[12]:15 0.00341 +16 chanx_right_in[12]:17 chanx_right_in[12]:16 0.007806308 + +*END + +*D_NET ccff_head[0] 0.003347664 //LENGTH 30.690 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 103.650 50.320 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.535 53.380 +*N ccff_head[0]:2 *C 76.535 53.380 +*N ccff_head[0]:3 *C 76.820 53.380 +*N ccff_head[0]:4 *C 76.820 53.335 +*N ccff_head[0]:5 *C 76.820 50.378 +*N ccff_head[0]:6 *C 76.828 50.320 + +*CAP +0 ccff_head[0] 0.001463174 +1 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 4.465717e-05 +3 ccff_head[0]:3 4.871615e-05 +4 ccff_head[0]:4 0.0001634706 +5 ccff_head[0]:5 0.0001634706 +6 ccff_head[0]:6 0.001463174 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.004202191 +1 ccff_head[0]:2 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001548913 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:5 ccff_head[0]:4 0.002640625 +5 ccff_head[0]:6 ccff_head[0]:5 0.00341 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.005860515 //LENGTH 50.875 LUMPCC 0.0003522524 DR + +*CONN +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 69.305 31.280 +*I mux_bottom_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 68.200 28.900 +*I mux_bottom_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 67.260 20.110 +*I mux_bottom_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 66.820 18.020 +*I mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 55.835 37.060 +*I mux_bottom_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 81.980 36.380 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 81.943 36.380 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 55.873 37.060 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 62.055 37.060 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 62.100 37.015 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 62.100 36.425 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 62.145 36.380 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 68.540 36.380 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 68.540 36.335 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 66.835 18.020 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 67.138 18.020 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 67.160 18.065 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 67.260 20.110 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 67.160 19.720 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 67.160 19.720 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 67.160 27.540 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 68.080 27.540 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 68.080 28.900 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 68.080 28.900 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 68.080 31.280 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 68.540 31.325 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 68.585 31.280 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 69.267 31.280 + +*CAP +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_ipin_0\/mux_l2_in_2_:S 1e-06 +2 mux_bottom_ipin_0\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_ipin_0\/mux_l2_in_3_:S 1e-06 +4 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_ipin_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 0.0006853618 +7 mux_tree_tapbuf_size10_0_sram[1]:7 0.0004285036 +8 mux_tree_tapbuf_size10_0_sram[1]:8 0.0004285036 +9 mux_tree_tapbuf_size10_0_sram[1]:9 7.239859e-05 +10 mux_tree_tapbuf_size10_0_sram[1]:10 7.239859e-05 +11 mux_tree_tapbuf_size10_0_sram[1]:11 0.0003633794 +12 mux_tree_tapbuf_size10_0_sram[1]:12 0.001075582 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.0002168003 +14 mux_tree_tapbuf_size10_0_sram[1]:14 5.019181e-05 +15 mux_tree_tapbuf_size10_0_sram[1]:15 5.019181e-05 +16 mux_tree_tapbuf_size10_0_sram[1]:16 0.0001049634 +17 mux_tree_tapbuf_size10_0_sram[1]:17 6.013878e-05 +18 mux_tree_tapbuf_size10_0_sram[1]:18 6.462014e-05 +19 mux_tree_tapbuf_size10_0_sram[1]:19 0.0004755445 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0003947258 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0001308605 +22 mux_tree_tapbuf_size10_0_sram[1]:22 3.258593e-05 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0002289838 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0001570742 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0002518993 +26 mux_tree_tapbuf_size10_0_sram[1]:26 7.877748e-05 +27 mux_tree_tapbuf_size10_0_sram[1]:27 7.877748e-05 +28 mux_tree_tapbuf_size10_0_sram[1]:23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.255734e-06 +29 mux_tree_tapbuf_size10_0_sram[1]:23 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.243115e-05 +30 mux_tree_tapbuf_size10_0_sram[1]:19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.354285e-06 +31 mux_tree_tapbuf_size10_0_sram[1]:19 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 8.045144e-05 +32 mux_tree_tapbuf_size10_0_sram[1]:13 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.063361e-05 +33 mux_tree_tapbuf_size10_0_sram[1]:25 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.063361e-05 +34 mux_tree_tapbuf_size10_0_sram[1]:20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.354285e-06 +35 mux_tree_tapbuf_size10_0_sram[1]:20 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 8.045144e-05 +36 mux_tree_tapbuf_size10_0_sram[1]:21 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.255734e-06 +37 mux_tree_tapbuf_size10_0_sram[1]:24 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.243115e-05 + +*RES +0 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:27 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:6 mux_bottom_ipin_0\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[1]:22 mux_bottom_ipin_0\/mux_l2_in_2_:S 0.152 +3 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0045 +4 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:21 0.001214286 +5 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0001644022 +6 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size10_0_sram[1]:14 mux_bottom_ipin_0\/mux_l2_in_3_:S 0.152 +8 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.0003482143 +9 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.0045 +10 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:16 0.001477679 +11 mux_tree_tapbuf_size10_0_sram[1]:17 mux_bottom_ipin_0\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.005709822 +13 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:6 0.01196652 +14 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +15 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.0045 +16 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.0005267857 +17 mux_tree_tapbuf_size10_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:7 0.00552009 +18 mux_tree_tapbuf_size10_0_sram[1]:9 mux_tree_tapbuf_size10_0_sram[1]:8 0.0045 +19 mux_tree_tapbuf_size10_0_sram[1]:7 mem_bottom_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +20 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.0045 +21 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0004107143 +22 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:13 0.004473215 +23 mux_tree_tapbuf_size10_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:26 0.000609375 +24 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.006982143 +25 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.0008214286 +26 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.002125 + +*END + +*D_NET chanx_left_out[14] 0.001198461 //LENGTH 10.080 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 11.695 3.400 +*P chanx_left_out[14] O *L 0.7423 *C 4.600 1.325 +*N chanx_left_out[14]:2 *C 5.060 1.020 +*N chanx_left_out[14]:3 *C 5.060 3.355 +*N chanx_left_out[14]:4 *C 5.105 3.400 +*N chanx_left_out[14]:5 *C 11.658 3.400 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chanx_left_out[14] 3.199305e-05 +2 chanx_left_out[14]:2 0.000178654 +3 chanx_left_out[14]:3 0.000146661 +4 chanx_left_out[14]:4 0.0004200766 +5 chanx_left_out[14]:5 0.0004200766 + +*RES +0 ropt_mt_inst_761:X chanx_left_out[14]:5 0.152 +1 chanx_left_out[14]:5 chanx_left_out[14]:4 0.005850446 +2 chanx_left_out[14]:4 chanx_left_out[14]:3 0.0045 +3 chanx_left_out[14]:3 chanx_left_out[14]:2 0.002084822 +4 chanx_left_out[14]:2 chanx_left_out[14] 0.0004107143 + +*END + +*D_NET ropt_net_201 0.0001566616 //LENGTH 0.860 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 7.190 12.240 +*I ropt_mt_inst_796:A I *L 0.001767 *C 7.820 12.240 +*N ropt_net_201:2 *C 7.820 12.240 +*N ropt_net_201:3 *C 7.190 12.240 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_201:2 7.733082e-05 +3 ropt_net_201:3 7.733082e-05 + +*RES +0 ropt_mt_inst_768:X ropt_net_201:3 0.152 +1 ropt_net_201:3 ropt_net_201:2 0.0005625 +2 ropt_net_201:2 ropt_mt_inst_796:A 0.152 + +*END + +*D_NET ropt_net_224 0.001103693 //LENGTH 9.410 LUMPCC 0.0002079128 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 4.140 25.160 +*I ropt_mt_inst_819:A I *L 0.001766 *C 3.220 23.120 +*N ropt_net_224:2 *C 3.258 23.120 +*N ropt_net_224:3 *C 6.855 23.120 +*N ropt_net_224:4 *C 6.900 23.165 +*N ropt_net_224:5 *C 6.900 25.115 +*N ropt_net_224:6 *C 6.855 25.160 +*N ropt_net_224:7 *C 4.178 25.160 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 ropt_mt_inst_819:A 1e-06 +2 ropt_net_224:2 0.0002103504 +3 ropt_net_224:3 0.0002103504 +4 ropt_net_224:4 8.480997e-05 +5 ropt_net_224:5 8.480997e-05 +6 ropt_net_224:6 0.0001517297 +7 ropt_net_224:7 0.0001517297 +8 ropt_net_224:4 chanx_right_in[7]:6 3.196619e-05 +9 ropt_net_224:6 chanx_right_in[7]:4 7.19902e-05 +10 ropt_net_224:5 chanx_right_in[7]:5 3.196619e-05 +11 ropt_net_224:7 chanx_right_in[7]:3 7.19902e-05 + +*RES +0 ropt_mt_inst_773:X ropt_net_224:7 0.152 +1 ropt_net_224:2 ropt_mt_inst_819:A 0.152 +2 ropt_net_224:3 ropt_net_224:2 0.003212054 +3 ropt_net_224:4 ropt_net_224:3 0.0045 +4 ropt_net_224:6 ropt_net_224:5 0.0045 +5 ropt_net_224:5 ropt_net_224:4 0.001741072 +6 ropt_net_224:7 ropt_net_224:6 0.002390625 + +*END + +*D_NET ropt_net_225 0.0004366037 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 8.740 70.040 +*I ropt_mt_inst_820:A I *L 0.001766 *C 7.820 72.080 +*N ropt_net_225:2 *C 7.820 72.080 +*N ropt_net_225:3 *C 7.820 72.035 +*N ropt_net_225:4 *C 7.820 70.085 +*N ropt_net_225:5 *C 7.865 70.040 +*N ropt_net_225:6 *C 8.703 70.040 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 ropt_mt_inst_820:A 1e-06 +2 ropt_net_225:2 3.312002e-05 +3 ropt_net_225:3 0.0001259478 +4 ropt_net_225:4 0.0001259478 +5 ropt_net_225:5 7.479402e-05 +6 ropt_net_225:6 7.479402e-05 + +*RES +0 ropt_mt_inst_782:X ropt_net_225:6 0.152 +1 ropt_net_225:6 ropt_net_225:5 0.0007477679 +2 ropt_net_225:5 ropt_net_225:4 0.0045 +3 ropt_net_225:4 ropt_net_225:3 0.001741071 +4 ropt_net_225:2 ropt_mt_inst_820:A 0.152 +5 ropt_net_225:3 ropt_net_225:2 0.0045 + +*END + +*D_NET chanx_left_out[8] 0.0007228669 //LENGTH 5.460 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 4.140 52.360 +*P chanx_left_out[8] O *L 0.7423 *C 1.230 50.320 +*N chanx_left_out[8]:2 *C 4.133 50.320 +*N chanx_left_out[8]:3 *C 4.140 50.378 +*N chanx_left_out[8]:4 *C 4.140 52.315 +*N chanx_left_out[8]:5 *C 4.140 52.360 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chanx_left_out[8] 0.0002284676 +2 chanx_left_out[8]:2 0.0002284676 +3 chanx_left_out[8]:3 0.0001177477 +4 chanx_left_out[8]:4 0.0001177477 +5 chanx_left_out[8]:5 2.943621e-05 + +*RES +0 ropt_mt_inst_797:X chanx_left_out[8]:5 0.152 +1 chanx_left_out[8]:5 chanx_left_out[8]:4 0.0045 +2 chanx_left_out[8]:4 chanx_left_out[8]:3 0.001729911 +3 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +4 chanx_left_out[8]:2 chanx_left_out[8] 0.000454725 + +*END + +*D_NET chanx_right_out[4] 0.0005560855 //LENGTH 4.370 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 101.855 25.160 +*P chanx_right_out[4] O *L 0.7423 *C 103.650 23.120 +*N chanx_right_out[4]:2 *C 102.128 23.120 +*N chanx_right_out[4]:3 *C 102.120 23.178 +*N chanx_right_out[4]:4 *C 102.120 25.115 +*N chanx_right_out[4]:5 *C 102.120 25.160 +*N chanx_right_out[4]:6 *C 101.855 25.160 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 chanx_right_out[4] 0.0001167647 +2 chanx_right_out[4]:2 0.0001167647 +3 chanx_right_out[4]:3 0.0001067027 +4 chanx_right_out[4]:4 0.0001067027 +5 chanx_right_out[4]:5 5.187437e-05 +6 chanx_right_out[4]:6 5.627635e-05 + +*RES +0 ropt_mt_inst_794:X chanx_right_out[4]:6 0.152 +1 chanx_right_out[4]:6 chanx_right_out[4]:5 0.0001440218 +2 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +3 chanx_right_out[4]:4 chanx_right_out[4]:3 0.001729911 +4 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +5 chanx_right_out[4]:2 chanx_right_out[4] 0.000238525 + +*END + +*D_NET chanx_right_out[17] 0.001543622 //LENGTH 12.685 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_807:X O *L 0 *C 94.300 26.520 +*P chanx_right_out[17] O *L 0.7423 *C 103.650 25.840 +*N chanx_right_out[17]:2 *C 93.388 25.840 +*N chanx_right_out[17]:3 *C 93.380 25.898 +*N chanx_right_out[17]:4 *C 93.380 26.475 +*N chanx_right_out[17]:5 *C 93.425 26.520 +*N chanx_right_out[17]:6 *C 94.263 26.520 + +*CAP +0 ropt_mt_inst_807:X 1e-06 +1 chanx_right_out[17] 0.0006223191 +2 chanx_right_out[17]:2 0.0006223191 +3 chanx_right_out[17]:3 7.325024e-05 +4 chanx_right_out[17]:4 7.325024e-05 +5 chanx_right_out[17]:5 7.574147e-05 +6 chanx_right_out[17]:6 7.574147e-05 + +*RES +0 ropt_mt_inst_807:X chanx_right_out[17]:6 0.152 +1 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0007477679 +2 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.000515625 +4 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +5 chanx_right_out[17]:2 chanx_right_out[17] 0.001607792 + +*END + +*D_NET chanx_left_out[10] 0.001400992 //LENGTH 11.230 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 7.095 57.800 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 53.040 +*N chanx_left_out[10]:2 *C 6.893 53.040 +*N chanx_left_out[10]:3 *C 6.900 53.098 +*N chanx_left_out[10]:4 *C 6.900 57.755 +*N chanx_left_out[10]:5 *C 6.900 57.800 +*N chanx_left_out[10]:6 *C 7.095 57.800 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 chanx_left_out[10] 0.0003903937 +2 chanx_left_out[10]:2 0.0003903937 +3 chanx_left_out[10]:3 0.0002505613 +4 chanx_left_out[10]:4 0.0002505613 +5 chanx_left_out[10]:5 5.733176e-05 +6 chanx_left_out[10]:6 6.075074e-05 + +*RES +0 ropt_mt_inst_814:X chanx_left_out[10]:6 0.152 +1 chanx_left_out[10]:6 chanx_left_out[10]:5 0.0001059783 +2 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0045 +3 chanx_left_out[10]:4 chanx_left_out[10]:3 0.004158482 +4 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +5 chanx_left_out[10]:2 chanx_left_out[10] 0.000887125 + +*END + +*D_NET ropt_net_169 0.001947009 //LENGTH 15.610 LUMPCC 0.0006792682 DR + +*CONN +*I BUFT_RR_73:X O *L 0 *C 19.780 36.720 +*I ropt_mt_inst_764:A I *L 0.001766 *C 7.820 34.000 +*N ropt_net_169:2 *C 7.858 34.000 +*N ropt_net_169:3 *C 16.515 34.000 +*N ropt_net_169:4 *C 16.560 34.045 +*N ropt_net_169:5 *C 16.560 36.675 +*N ropt_net_169:6 *C 16.605 36.720 +*N ropt_net_169:7 *C 19.742 36.720 + +*CAP +0 BUFT_RR_73:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_169:2 0.0003105439 +3 ropt_net_169:3 0.0003105439 +4 ropt_net_169:4 0.0001462484 +5 ropt_net_169:5 0.0001462484 +6 ropt_net_169:6 0.0001760784 +7 ropt_net_169:7 0.0001760784 +8 ropt_net_169:2 chanx_right_in[1]:7 0.0003396341 +9 ropt_net_169:3 chanx_right_in[1]:8 0.0003396341 + +*RES +0 BUFT_RR_73:X ropt_net_169:7 0.152 +1 ropt_net_169:2 ropt_mt_inst_764:A 0.152 +2 ropt_net_169:3 ropt_net_169:2 0.007729911 +3 ropt_net_169:4 ropt_net_169:3 0.0045 +4 ropt_net_169:6 ropt_net_169:5 0.0045 +5 ropt_net_169:5 ropt_net_169:4 0.002348214 +6 ropt_net_169:7 ropt_net_169:6 0.002801339 + +*END + +*D_NET ropt_net_194 0.001317028 //LENGTH 10.790 LUMPCC 0.0001294469 DR + +*CONN +*I BUFT_P_136:X O *L 0 *C 89.855 70.040 +*I ropt_mt_inst_789:A I *L 0.001766 *C 97.980 72.080 +*N ropt_net_194:2 *C 97.980 72.080 +*N ropt_net_194:3 *C 97.980 72.035 +*N ropt_net_194:4 *C 97.980 70.085 +*N ropt_net_194:5 *C 97.935 70.040 +*N ropt_net_194:6 *C 89.892 70.040 + +*CAP +0 BUFT_P_136:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_194:2 2.942397e-05 +3 ropt_net_194:3 0.0001121105 +4 ropt_net_194:4 0.0001121105 +5 ropt_net_194:5 0.0004659682 +6 ropt_net_194:6 0.0004659682 +7 ropt_net_194:6 ropt_net_217:3 6.010846e-05 +8 ropt_net_194:5 ropt_net_217:2 6.010846e-05 +9 ropt_net_194:4 ropt_net_217:4 4.61501e-06 +10 ropt_net_194:3 ropt_net_217:5 4.61501e-06 + +*RES +0 BUFT_P_136:X ropt_net_194:6 0.152 +1 ropt_net_194:6 ropt_net_194:5 0.007180803 +2 ropt_net_194:5 ropt_net_194:4 0.0045 +3 ropt_net_194:4 ropt_net_194:3 0.001741071 +4 ropt_net_194:2 ropt_mt_inst_789:A 0.152 +5 ropt_net_194:3 ropt_net_194:2 0.0045 + +*END + +*D_NET ropt_net_167 0.001164648 //LENGTH 9.395 LUMPCC 0.000264282 DR + +*CONN +*I BUFT_P_153:X O *L 0 *C 13.340 55.080 +*I ropt_mt_inst_762:A I *L 0.001766 *C 7.820 53.040 +*N ropt_net_167:2 *C 7.820 53.040 +*N ropt_net_167:3 *C 9.615 53.040 +*N ropt_net_167:4 *C 9.660 53.085 +*N ropt_net_167:5 *C 9.660 55.035 +*N ropt_net_167:6 *C 9.705 55.080 +*N ropt_net_167:7 *C 13.303 55.080 + +*CAP +0 BUFT_P_153:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_167:2 0.0001418124 +3 ropt_net_167:3 0.0001132226 +4 ropt_net_167:4 8.762831e-05 +5 ropt_net_167:5 8.762831e-05 +6 ropt_net_167:6 0.0002340371 +7 ropt_net_167:7 0.0002340371 +8 ropt_net_167:7 chanx_right_in[10]:9 4.630196e-05 +9 ropt_net_167:6 chanx_right_in[10]:8 4.630196e-05 +10 ropt_net_167:5 chanx_right_in[10]:10 3.01324e-05 +11 ropt_net_167:4 chanx_right_in[10]:11 3.01324e-05 +12 ropt_net_167:3 ropt_net_202:7 5.570667e-05 +13 ropt_net_167:2 ropt_net_202:6 5.570667e-05 + +*RES +0 BUFT_P_153:X ropt_net_167:7 0.152 +1 ropt_net_167:7 ropt_net_167:6 0.003212054 +2 ropt_net_167:6 ropt_net_167:5 0.0045 +3 ropt_net_167:5 ropt_net_167:4 0.001741071 +4 ropt_net_167:3 ropt_net_167:2 0.001602679 +5 ropt_net_167:4 ropt_net_167:3 0.0045 +6 ropt_net_167:2 ropt_mt_inst_762:A 0.152 + +*END + +*D_NET chanx_left_in[10] 0.009460487 //LENGTH 85.430 LUMPCC 0.00282171 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 24.480 +*I mux_bottom_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 68.370 20.740 +*I BUFT_RR_52:A I *L 0.001776 *C 76.360 17.680 +*N chanx_left_in[10]:3 *C 76.323 17.680 +*N chanx_left_in[10]:4 *C 75.485 17.680 +*N chanx_left_in[10]:5 *C 75.440 17.725 +*N chanx_left_in[10]:6 *C 75.440 20.695 +*N chanx_left_in[10]:7 *C 75.395 20.740 +*N chanx_left_in[10]:8 *C 68.370 20.740 +*N chanx_left_in[10]:9 *C 68.585 20.740 +*N chanx_left_in[10]:10 *C 68.540 20.785 +*N chanx_left_in[10]:11 *C 68.540 25.103 +*N chanx_left_in[10]:12 *C 68.532 25.160 +*N chanx_left_in[10]:13 *C 63.650 25.160 +*N chanx_left_in[10]:14 *C 13.800 25.160 +*N chanx_left_in[10]:15 *C 13.800 24.480 + +*CAP +0 chanx_left_in[10] 0.000575419 +1 mux_bottom_ipin_0\/mux_l2_in_1_:A0 1e-06 +2 BUFT_RR_52:A 1e-06 +3 chanx_left_in[10]:3 6.184795e-05 +4 chanx_left_in[10]:4 6.184795e-05 +5 chanx_left_in[10]:5 0.0001781282 +6 chanx_left_in[10]:6 0.0001781282 +7 chanx_left_in[10]:7 0.0001423688 +8 chanx_left_in[10]:8 3.36799e-05 +9 chanx_left_in[10]:9 0.0001495164 +10 chanx_left_in[10]:10 0.0002425437 +11 chanx_left_in[10]:11 0.0002425437 +12 chanx_left_in[10]:12 0.0001769091 +13 chanx_left_in[10]:13 0.00204284 +14 chanx_left_in[10]:14 0.001920758 +15 chanx_left_in[10]:15 0.0006302455 +16 chanx_left_in[10] chanx_left_in[17]:7 4.846344e-06 +17 chanx_left_in[10]:12 chanx_left_in[17]:5 3.612313e-05 +18 chanx_left_in[10]:15 chanx_left_in[17]:6 4.846344e-06 +19 chanx_left_in[10]:14 chanx_left_in[17]:7 0.0003316326 +20 chanx_left_in[10]:14 chanx_left_in[17]:6 7.231431e-06 +21 chanx_left_in[10]:13 chanx_left_in[17]:5 7.231431e-06 +22 chanx_left_in[10]:13 chanx_left_in[17]:6 0.0003677557 +23 chanx_left_in[10]:7 chanx_left_in[19]:6 0.0002668239 +24 chanx_left_in[10]:8 chanx_left_in[19]:7 1.378253e-05 +25 chanx_left_in[10]:9 chanx_left_in[19]:6 1.378253e-05 +26 chanx_left_in[10]:9 chanx_left_in[19]:7 0.0002668239 +27 chanx_left_in[10] chanx_right_in[7]:7 0.0002019991 +28 chanx_left_in[10]:7 chanx_right_in[7]:10 5.569883e-06 +29 chanx_left_in[10]:9 chanx_right_in[7]:9 5.569883e-06 +30 chanx_left_in[10]:12 chanx_right_in[7]:10 2.72582e-05 +31 chanx_left_in[10]:15 chanx_right_in[7]:8 0.0002019991 +32 chanx_left_in[10]:14 chanx_right_in[7]:7 0.000218558 +33 chanx_left_in[10]:14 chanx_right_in[7]:9 0.0001718976 +34 chanx_left_in[10]:13 chanx_right_in[7]:8 0.000218558 +35 chanx_left_in[10]:13 chanx_right_in[7]:9 2.72582e-05 +36 chanx_left_in[10]:13 chanx_right_in[7]:10 0.0001718976 +37 chanx_left_in[10]:7 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001195145 +38 chanx_left_in[10]:8 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.617466e-06 +39 chanx_left_in[10]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001195145 +40 chanx_left_in[10]:9 mux_bottom_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.617466e-06 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:15 0.0019693 +1 chanx_left_in[10]:7 chanx_left_in[10]:6 0.0045 +2 chanx_left_in[10]:6 chanx_left_in[10]:5 0.002651786 +3 chanx_left_in[10]:4 chanx_left_in[10]:3 0.0007477679 +4 chanx_left_in[10]:5 chanx_left_in[10]:4 0.0045 +5 chanx_left_in[10]:3 BUFT_RR_52:A 0.152 +6 chanx_left_in[10]:8 mux_bottom_ipin_0\/mux_l2_in_1_:A0 0.152 +7 chanx_left_in[10]:9 chanx_left_in[10]:8 0.0001168478 +8 chanx_left_in[10]:9 chanx_left_in[10]:7 0.006080357 +9 chanx_left_in[10]:10 chanx_left_in[10]:9 0.0045 +10 chanx_left_in[10]:11 chanx_left_in[10]:10 0.003854911 +11 chanx_left_in[10]:12 chanx_left_in[10]:11 0.00341 +12 chanx_left_in[10]:15 chanx_left_in[10]:14 0.0001065333 +13 chanx_left_in[10]:14 chanx_left_in[10]:13 0.007809833 +14 chanx_left_in[10]:13 chanx_left_in[10]:12 0.000764925 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..127f53c --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef @@ -0,0 +1,8631 @@ +*SPEF "1481-1998" +*DESIGN "cby_0__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 0.690 3.400 +chany_bottom_in[0] I *C 42.780 0.680 +chany_bottom_in[1] I *C 25.760 0.680 +chany_bottom_in[2] I *C 71.300 0.680 +chany_bottom_in[3] I *C 49.220 0.680 +chany_bottom_in[4] I *C 36.340 0.680 +chany_bottom_in[5] I *C 44.620 0.680 +chany_bottom_in[6] I *C 5.520 0.680 +chany_bottom_in[7] I *C 69.000 0.680 +chany_bottom_in[8] I *C 22.080 0.680 +chany_bottom_in[9] I *C 9.200 0.680 +chany_bottom_in[10] I *C 46.460 0.680 +chany_bottom_in[11] I *C 51.060 0.680 +chany_bottom_in[12] I *C 7.360 0.680 +chany_bottom_in[13] I *C 23.920 0.680 +chany_bottom_in[14] I *C 7.360 0.680 +chany_bottom_in[15] I *C 46.000 0.680 +chany_bottom_in[16] I *C 48.300 0.680 +chany_bottom_in[17] I *C 52.900 0.680 +chany_bottom_in[18] I *C 47.840 0.680 +chany_bottom_in[19] I *C 25.760 0.680 +chany_top_in[0] I *C 50.140 108.120 +chany_top_in[1] I *C 34.500 108.120 +chany_top_in[2] I *C 66.700 108.120 +chany_top_in[3] I *C 44.620 108.120 +chany_top_in[4] I *C 51.060 108.120 +chany_top_in[5] I *C 45.540 108.120 +chany_top_in[6] I *C 70.380 108.120 +chany_top_in[7] I *C 68.540 108.120 +chany_top_in[8] I *C 69.460 108.120 +chany_top_in[9] I *C 25.760 108.120 +chany_top_in[10] I *C 42.780 108.120 +chany_top_in[11] I *C 48.300 108.120 +chany_top_in[12] I *C 67.620 108.120 +chany_top_in[13] I *C 49.680 108.120 +chany_top_in[14] I *C 46.000 108.120 +chany_top_in[15] I *C 47.840 108.120 +chany_top_in[16] I *C 28.520 108.120 +chany_top_in[17] I *C 47.380 108.120 +chany_top_in[18] I *C 23.920 108.120 +chany_top_in[19] I *C 25.760 108.120 +ccff_head[0] I *C 54.280 108.120 +chany_bottom_out[0] O *C 67.620 0.680 +chany_bottom_out[1] O *C 62.100 0.680 +chany_bottom_out[2] O *C 70.380 0.680 +chany_bottom_out[3] O *C 45.540 0.680 +chany_bottom_out[4] O *C 43.700 0.680 +chany_bottom_out[5] O *C 28.980 0.680 +chany_bottom_out[6] O *C 69.460 0.680 +chany_bottom_out[7] O *C 68.540 0.680 +chany_bottom_out[8] O *C 63.020 0.680 +chany_bottom_out[9] O *C 51.980 0.680 +chany_bottom_out[10] O *C 50.140 0.680 +chany_bottom_out[11] O *C 41.860 0.680 +chany_bottom_out[12] O *C 72.220 0.680 +chany_bottom_out[13] O *C 20.240 0.680 +chany_bottom_out[14] O *C 29.440 0.680 +chany_bottom_out[15] O *C 49.680 0.680 +chany_bottom_out[16] O *C 58.880 0.680 +chany_bottom_out[17] O *C 14.720 0.680 +chany_bottom_out[18] O *C 44.160 0.680 +chany_bottom_out[19] O *C 47.380 0.680 +chany_top_out[0] O *C 65.780 108.120 +chany_top_out[1] O *C 14.720 108.120 +chany_top_out[2] O *C 71.300 108.120 +chany_top_out[3] O *C 13.800 108.120 +chany_top_out[4] O *C 73.140 108.120 +chany_top_out[5] O *C 49.220 108.120 +chany_top_out[6] O *C 52.900 108.120 +chany_top_out[7] O *C 22.080 108.120 +chany_top_out[8] O *C 23.920 108.120 +chany_top_out[9] O *C 23.000 108.120 +chany_top_out[10] O *C 51.980 108.120 +chany_top_out[11] O *C 30.820 108.120 +chany_top_out[12] O *C 63.940 108.120 +chany_top_out[13] O *C 72.220 108.120 +chany_top_out[14] O *C 43.700 108.120 +chany_top_out[15] O *C 46.460 108.120 +chany_top_out[16] O *C 41.860 108.120 +chany_top_out[17] O *C 29.900 108.120 +chany_top_out[18] O *C 26.680 108.120 +chany_top_out[19] O *C 24.840 108.120 +right_grid_pin_52_[0] O *C 83.950 78.880 +left_grid_pin_0_[0] O *C 0.690 99.280 +ccff_tail[0] O *C 0.690 78.880 +VDD I *C 42.320 54.400 +VSS I *C 42.320 54.400 + +*D_NET chany_bottom_in[0] 0.01449549 //LENGTH 133.365 LUMPCC 0.002843307 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 42.780 1.290 +*I FTB_1__0:A I *L 0.001776 *C 64.400 99.280 +*I mux_left_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 69.825 79.900 +*N chany_bottom_in[0]:3 *C 69.788 79.900 +*N chany_bottom_in[0]:4 *C 69.460 79.900 +*N chany_bottom_in[0]:5 *C 69.460 80.240 +*N chany_bottom_in[0]:6 *C 64.362 99.280 +*N chany_bottom_in[0]:7 *C 58.465 99.280 +*N chany_bottom_in[0]:8 *C 58.420 99.235 +*N chany_bottom_in[0]:9 *C 58.420 80.285 +*N chany_bottom_in[0]:10 *C 58.420 80.240 +*N chany_bottom_in[0]:11 *C 52.025 80.240 +*N chany_bottom_in[0]:12 *C 51.980 80.195 +*N chany_bottom_in[0]:13 *C 51.980 69.560 +*N chany_bottom_in[0]:14 *C 51.980 19.765 +*N chany_bottom_in[0]:15 *C 51.935 19.720 +*N chany_bottom_in[0]:16 *C 42.825 19.720 +*N chany_bottom_in[0]:17 *C 42.780 19.675 + +*CAP +0 chany_bottom_in[0] 0.0009039387 +1 FTB_1__0:A 1e-06 +2 mux_left_ipin_0\/mux_l1_in_0_:A1 1e-06 +3 chany_bottom_in[0]:3 3.97468e-05 +4 chany_bottom_in[0]:4 6.150243e-05 +5 chany_bottom_in[0]:5 0.0004010938 +6 chany_bottom_in[0]:6 0.0003087905 +7 chany_bottom_in[0]:7 0.0003087905 +8 chany_bottom_in[0]:8 0.0008434844 +9 chany_bottom_in[0]:9 0.0008434844 +10 chany_bottom_in[0]:10 0.0005935546 +11 chany_bottom_in[0]:11 0.0001841928 +12 chany_bottom_in[0]:12 0.0005932193 +13 chany_bottom_in[0]:13 0.002538797 +14 chany_bottom_in[0]:14 0.001945577 +15 chany_bottom_in[0]:15 0.0005900338 +16 chany_bottom_in[0]:16 0.0005900338 +17 chany_bottom_in[0]:17 0.0009039387 +18 chany_bottom_in[0]:10 chany_bottom_in[6]:6 0.0002514174 +19 chany_bottom_in[0]:10 chany_bottom_in[6]:7 5.77896e-05 +20 chany_bottom_in[0]:9 chany_bottom_in[6]:5 2.738933e-05 +21 chany_bottom_in[0]:8 chany_bottom_in[6]:4 2.738933e-05 +22 chany_bottom_in[0]:11 chany_bottom_in[6]:7 0.0002514174 +23 chany_bottom_in[0]:5 chany_bottom_in[6]:6 5.77896e-05 +24 chany_bottom_in[0]:10 chany_top_in[0]:16 4.402488e-05 +25 chany_bottom_in[0]:10 chany_top_in[0]:17 0.0001909004 +26 chany_bottom_in[0]:9 chany_top_in[0]:18 5.994789e-05 +27 chany_bottom_in[0]:8 chany_top_in[0]:19 5.994789e-05 +28 chany_bottom_in[0]:3 chany_top_in[0]:16 1.863092e-06 +29 chany_bottom_in[0]:11 chany_top_in[0]:17 4.402488e-05 +30 chany_bottom_in[0]:5 chany_top_in[0]:16 0.0001909004 +31 chany_bottom_in[0]:5 chany_top_in[0]:15 5.84729e-06 +32 chany_bottom_in[0]:4 chany_top_in[0]:14 5.84729e-06 +33 chany_bottom_in[0]:4 chany_top_in[0]:17 1.863092e-06 +34 chany_bottom_in[0]:14 chany_top_in[10]:12 0.0004361238 +35 chany_bottom_in[0]:14 chany_top_in[10]:6 3.897219e-05 +36 chany_bottom_in[0]:14 chany_top_in[10]:8 7.443227e-06 +37 chany_bottom_in[0]:13 chany_top_in[10]:13 0.0004361238 +38 chany_bottom_in[0]:13 chany_top_in[10]:9 7.443227e-06 +39 chany_bottom_in[0]:13 chany_top_in[10]:7 3.897219e-05 +40 chany_bottom_in[0]:10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001022356 +41 chany_bottom_in[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001022356 +42 chany_bottom_in[0]:7 ropt_net_177:4 9.689208e-05 +43 chany_bottom_in[0]:6 ropt_net_177:3 9.689208e-05 +44 chany_bottom_in[0] ropt_net_163:8 0.0001008069 +45 chany_bottom_in[0]:17 ropt_net_163:9 0.0001008069 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:17 0.01641518 +1 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.0045 +2 chany_bottom_in[0]:10 chany_bottom_in[0]:5 0.009857143 +3 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.01691965 +4 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.005265625 +5 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.0045 +6 chany_bottom_in[0]:6 FTB_1__0:A 0.152 +7 chany_bottom_in[0]:3 mux_left_ipin_0\/mux_l1_in_0_:A1 0.152 +8 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.005709821 +9 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.0045 +10 chany_bottom_in[0]:15 chany_bottom_in[0]:14 0.0045 +11 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.04445983 +12 chany_bottom_in[0]:16 chany_bottom_in[0]:15 0.008133928 +13 chany_bottom_in[0]:17 chany_bottom_in[0]:16 0.0045 +14 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.0003035715 +15 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.0002924107 +16 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.009495536 + +*END + +*D_NET ropt_net_167 0.001244204 //LENGTH 11.620 LUMPCC 0.0002221075 DR + +*CONN +*I BUFT_RR_64:X O *L 0 *C 64.860 20.060 +*I ropt_mt_inst_771:A I *L 0.001766 *C 62.100 12.240 +*N ropt_net_167:2 *C 62.138 12.240 +*N ropt_net_167:3 *C 62.975 12.240 +*N ropt_net_167:4 *C 63.020 12.285 +*N ropt_net_167:5 *C 63.020 19.675 +*N ropt_net_167:6 *C 63.065 19.720 +*N ropt_net_167:7 *C 64.860 19.720 +*N ropt_net_167:8 *C 64.860 20.060 + +*CAP +0 BUFT_RR_64:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_167:2 6.502365e-05 +3 ropt_net_167:3 6.502365e-05 +4 ropt_net_167:4 0.000274132 +5 ropt_net_167:5 0.000274132 +6 ropt_net_167:6 0.0001295785 +7 ropt_net_167:7 0.0001568138 +8 ropt_net_167:8 5.539253e-05 +9 ropt_net_167:5 chany_bottom_in[7]:7 0.0001110537 +10 ropt_net_167:4 chany_bottom_in[7]:8 0.0001110537 + +*RES +0 BUFT_RR_64:X ropt_net_167:8 0.152 +1 ropt_net_167:8 ropt_net_167:7 0.0003035715 +2 ropt_net_167:6 ropt_net_167:5 0.0045 +3 ropt_net_167:5 ropt_net_167:4 0.006598215 +4 ropt_net_167:3 ropt_net_167:2 0.0007477679 +5 ropt_net_167:4 ropt_net_167:3 0.0045 +6 ropt_net_167:2 ropt_mt_inst_771:A 0.152 +7 ropt_net_167:7 ropt_net_167:6 0.001602679 + +*END + +*D_NET chany_top_out[2] 0.0007854449 //LENGTH 5.595 LUMPCC 0.0001124834 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 71.760 104.040 +*P chany_top_out[2] O *L 0.7423 *C 71.300 107.510 +*N chany_top_out[2]:2 *C 71.300 106.760 +*N chany_top_out[2]:3 *C 70.840 106.760 +*N chany_top_out[2]:4 *C 70.840 104.085 +*N chany_top_out[2]:5 *C 70.885 104.040 +*N chany_top_out[2]:6 *C 71.722 104.040 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chany_top_out[2] 5.990083e-05 +2 chany_top_out[2]:2 8.423437e-05 +3 chany_top_out[2]:3 0.0001907263 +4 chany_top_out[2]:4 0.0001663928 +5 chany_top_out[2]:5 8.535363e-05 +6 chany_top_out[2]:6 8.535363e-05 +7 chany_top_out[2]:6 ropt_net_207:3 3.022021e-06 +8 chany_top_out[2]:6 ropt_net_207:5 2.810356e-06 +9 chany_top_out[2]:6 ropt_net_207:6 7.070533e-07 +10 chany_top_out[2]:5 ropt_net_207:2 3.022021e-06 +11 chany_top_out[2]:5 ropt_net_207:4 2.810356e-06 +12 chany_top_out[2]:5 ropt_net_207:7 7.070533e-07 +13 chany_top_out[2]:4 ropt_net_207:9 4.381548e-05 +14 chany_top_out[2]:3 ropt_net_207:2 5.886763e-06 +15 chany_top_out[2]:3 ropt_net_207:8 4.381548e-05 +16 chany_top_out[2]:2 ropt_net_207:3 5.886763e-06 + +*RES +0 ropt_mt_inst_810:X chany_top_out[2]:6 0.152 +1 chany_top_out[2]:6 chany_top_out[2]:5 0.0007477679 +2 chany_top_out[2]:5 chany_top_out[2]:4 0.0045 +3 chany_top_out[2]:4 chany_top_out[2]:3 0.002388393 +4 chany_top_out[2]:3 chany_top_out[2]:2 0.0004107143 +5 chany_top_out[2]:2 chany_top_out[2] 0.0006696429 + +*END + +*D_NET chany_bottom_out[1] 0.0008851824 //LENGTH 8.350 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_822:X O *L 0 *C 66.895 3.740 +*P chany_bottom_out[1] O *L 0.7423 *C 62.100 1.290 +*N chany_bottom_out[1]:2 *C 62.100 1.655 +*N chany_bottom_out[1]:3 *C 62.145 1.700 +*N chany_bottom_out[1]:4 *C 66.195 1.700 +*N chany_bottom_out[1]:5 *C 66.240 1.745 +*N chany_bottom_out[1]:6 *C 66.240 3.695 +*N chany_bottom_out[1]:7 *C 66.285 3.740 +*N chany_bottom_out[1]:8 *C 66.858 3.740 + +*CAP +0 ropt_mt_inst_822:X 1e-06 +1 chany_bottom_out[1] 3.449145e-05 +2 chany_bottom_out[1]:2 3.449145e-05 +3 chany_bottom_out[1]:3 0.000236368 +4 chany_bottom_out[1]:4 0.000236368 +5 chany_bottom_out[1]:5 0.0001171378 +6 chany_bottom_out[1]:6 0.0001171378 +7 chany_bottom_out[1]:7 5.409398e-05 +8 chany_bottom_out[1]:8 5.409398e-05 + +*RES +0 ropt_mt_inst_822:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0005111608 +2 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +3 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.001741072 +4 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.003616072 +5 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0045 +6 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +7 chany_bottom_out[1]:2 chany_bottom_out[1] 0.0003258929 + +*END + +*D_NET chany_bottom_in[1] 0.01122471 //LENGTH 112.425 LUMPCC 0.001083668 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 25.760 1.290 +*I BUFT_P_116:A I *L 0.001776 *C 17.940 96.560 +*I mux_right_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 31.645 58.140 +*N chany_bottom_in[1]:3 *C 31.608 58.140 +*N chany_bottom_in[1]:4 *C 17.977 96.560 +*N chany_bottom_in[1]:5 *C 19.735 96.560 +*N chany_bottom_in[1]:6 *C 19.780 96.515 +*N chany_bottom_in[1]:7 *C 19.780 58.185 +*N chany_bottom_in[1]:8 *C 19.825 58.140 +*N chany_bottom_in[1]:9 *C 27.140 58.140 +*N chany_bottom_in[1]:10 *C 27.140 58.095 +*N chany_bottom_in[1]:11 *C 27.140 44.880 +*N chany_bottom_in[1]:12 *C 26.680 44.880 +*N chany_bottom_in[1]:13 *C 26.680 2.778 +*N chany_bottom_in[1]:14 *C 26.673 2.720 +*N chany_bottom_in[1]:15 *C 25.768 2.720 +*N chany_bottom_in[1]:16 *C 25.760 2.663 + +*CAP +0 chany_bottom_in[1] 8.104764e-05 +1 BUFT_P_116:A 1e-06 +2 mux_right_ipin_0\/mux_l1_in_0_:A1 1e-06 +3 chany_bottom_in[1]:3 0.0003027257 +4 chany_bottom_in[1]:4 0.0001244611 +5 chany_bottom_in[1]:5 0.0001244611 +6 chany_bottom_in[1]:6 0.001664385 +7 chany_bottom_in[1]:7 0.001664385 +8 chany_bottom_in[1]:8 0.0003889584 +9 chany_bottom_in[1]:9 0.0007212278 +10 chany_bottom_in[1]:10 0.0006417294 +11 chany_bottom_in[1]:11 0.0006709353 +12 chany_bottom_in[1]:12 0.001747727 +13 chany_bottom_in[1]:13 0.001718521 +14 chany_bottom_in[1]:14 0.0001037136 +15 chany_bottom_in[1]:15 0.0001037136 +16 chany_bottom_in[1]:16 8.104764e-05 +17 chany_bottom_in[1]:10 chany_bottom_in[19]:7 2.560991e-05 +18 chany_bottom_in[1]:13 chany_bottom_in[19] 6.510356e-06 +19 chany_bottom_in[1]:13 chany_bottom_in[19]:8 0.0002554356 +20 chany_bottom_in[1]:14 chany_bottom_in[19]:10 1.702142e-06 +21 chany_bottom_in[1]:15 chany_bottom_in[19]:9 1.702142e-06 +22 chany_bottom_in[1]:12 chany_bottom_in[19]:11 6.510356e-06 +23 chany_bottom_in[1]:12 chany_bottom_in[19]:7 0.0002554356 +24 chany_bottom_in[1]:11 chany_bottom_in[19]:8 2.560991e-05 +25 chany_bottom_in[1]:7 mux_tree_tapbuf_size10_1_sram[1]:16 6.771629e-05 +26 chany_bottom_in[1]:7 mux_tree_tapbuf_size10_1_sram[1]:13 0.0001620508 +27 chany_bottom_in[1]:7 mux_tree_tapbuf_size10_1_sram[1]:8 2.280901e-05 +28 chany_bottom_in[1]:6 mux_tree_tapbuf_size10_1_sram[1]:16 0.0001620508 +29 chany_bottom_in[1]:6 mux_tree_tapbuf_size10_1_sram[1]:17 6.771629e-05 +30 chany_bottom_in[1]:6 mux_tree_tapbuf_size10_1_sram[1]:9 2.280901e-05 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:16 0.001225446 +1 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.00653125 +2 chany_bottom_in[1]:9 chany_bottom_in[1]:3 0.00398884 +3 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.0045 +4 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.03759152 +5 chany_bottom_in[1]:14 chany_bottom_in[1]:13 0.00341 +6 chany_bottom_in[1]:16 chany_bottom_in[1]:15 0.00341 +7 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.0001417833 +8 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.0045 +9 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.03422322 +10 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.001569197 +11 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.0045 +12 chany_bottom_in[1]:4 BUFT_P_116:A 0.152 +13 chany_bottom_in[1]:3 mux_right_ipin_0\/mux_l1_in_0_:A1 0.152 +14 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.0004107143 +15 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.01179911 + +*END + +*D_NET chany_bottom_in[2] 0.01180927 //LENGTH 110.645 LUMPCC 0.003053969 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 71.300 1.290 +*I mux_left_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 67.985 85.340 +*I BUFT_P_107:A I *L 0.001776 *C 75.440 99.280 +*N chany_bottom_in[2]:3 *C 75.403 99.280 +*N chany_bottom_in[2]:4 *C 73.645 99.280 +*N chany_bottom_in[2]:5 *C 73.600 99.235 +*N chany_bottom_in[2]:6 *C 73.600 85.045 +*N chany_bottom_in[2]:7 *C 73.555 85.000 +*N chany_bottom_in[2]:8 *C 67.948 85.340 +*N chany_bottom_in[2]:9 *C 66.240 85.340 +*N chany_bottom_in[2]:10 *C 66.240 85.000 +*N chany_bottom_in[2]:11 *C 71.300 85.000 +*N chany_bottom_in[2]:12 *C 71.300 84.955 +*N chany_bottom_in[2]:13 *C 71.300 51.290 + +*CAP +0 chany_bottom_in[2] 0.001882199 +1 mux_left_ipin_0\/mux_l1_in_1_:A1 1e-06 +2 BUFT_P_107:A 1e-06 +3 chany_bottom_in[2]:3 0.0001318713 +4 chany_bottom_in[2]:4 0.0001318713 +5 chany_bottom_in[2]:5 0.0006492546 +6 chany_bottom_in[2]:6 0.0006492546 +7 chany_bottom_in[2]:7 0.0001378908 +8 chany_bottom_in[2]:8 0.0001025681 +9 chany_bottom_in[2]:9 0.0001263038 +10 chany_bottom_in[2]:10 0.0002730759 +11 chany_bottom_in[2]:11 0.000421986 +12 chany_bottom_in[2]:12 0.001182416 +13 chany_bottom_in[2]:13 0.003064615 +14 chany_bottom_in[2] chany_top_in[6]:4 0.0004070714 +15 chany_bottom_in[2]:6 chany_top_in[6]:5 1.72111e-05 +16 chany_bottom_in[2]:5 chany_top_in[6] 1.72111e-05 +17 chany_bottom_in[2]:12 chany_top_in[6] 0.0001602861 +18 chany_bottom_in[2]:12 chany_top_in[6]:5 0.0003115369 +19 chany_bottom_in[2]:13 chany_top_in[6]:4 0.0003115369 +20 chany_bottom_in[2]:13 chany_top_in[6]:5 0.0005673575 +21 chany_bottom_in[2] chany_top_in[12]:6 0.0002684109 +22 chany_bottom_in[2]:13 chany_top_in[12]:7 0.0002684109 +23 chany_bottom_in[2]:7 mux_tree_tapbuf_size10_0_sram[0]:12 1.613165e-05 +24 chany_bottom_in[2]:6 mux_tree_tapbuf_size10_0_sram[0]:10 9.670461e-06 +25 chany_bottom_in[2]:5 mux_tree_tapbuf_size10_0_sram[0]:11 9.670461e-06 +26 chany_bottom_in[2]:11 mux_tree_tapbuf_size10_0_sram[0]:12 4.359376e-05 +27 chany_bottom_in[2]:11 mux_tree_tapbuf_size10_0_sram[0]:13 2.420568e-05 +28 chany_bottom_in[2]:12 mux_tree_tapbuf_size10_0_sram[0]:11 6.385954e-05 +29 chany_bottom_in[2]:12 mux_tree_tapbuf_size10_0_sram[0]:10 8.703356e-05 +30 chany_bottom_in[2]:8 mux_tree_tapbuf_size10_0_sram[0]:12 2.97311e-05 +31 chany_bottom_in[2]:8 mux_tree_tapbuf_size10_0_sram[0]:13 3.554147e-05 +32 chany_bottom_in[2]:10 mux_tree_tapbuf_size10_0_sram[0]:14 8.074028e-06 +33 chany_bottom_in[2]:10 mux_tree_tapbuf_size10_0_sram[0]:13 4.359376e-05 +34 chany_bottom_in[2]:9 mux_tree_tapbuf_size10_0_sram[0]:14 3.554147e-05 +35 chany_bottom_in[2]:9 mux_tree_tapbuf_size10_0_sram[0]:13 2.97311e-05 +36 chany_bottom_in[2]:13 mux_tree_tapbuf_size10_0_sram[0]:7 8.703356e-05 +37 chany_bottom_in[2]:13 mux_tree_tapbuf_size10_0_sram[0]:10 6.385954e-05 +38 chany_bottom_in[2] ropt_net_164:4 6.883237e-05 +39 chany_bottom_in[2]:13 ropt_net_164:5 6.883237e-05 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:13 0.04464286 +1 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.0045 +2 chany_bottom_in[2]:6 chany_bottom_in[2]:5 0.01266964 +3 chany_bottom_in[2]:4 chany_bottom_in[2]:3 0.001569197 +4 chany_bottom_in[2]:5 chany_bottom_in[2]:4 0.0045 +5 chany_bottom_in[2]:3 BUFT_P_107:A 0.152 +6 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.004517857 +7 chany_bottom_in[2]:11 chany_bottom_in[2]:7 0.002013393 +8 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.0045 +9 chany_bottom_in[2]:8 mux_left_ipin_0\/mux_l1_in_1_:A1 0.152 +10 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.0003035714 +11 chany_bottom_in[2]:9 chany_bottom_in[2]:8 0.001524554 +12 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.03005804 + +*END + +*D_NET chany_bottom_in[17] 0.01416919 //LENGTH 133.025 LUMPCC 0.002531999 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 52.900 1.325 +*I mux_right_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 28.350 80.580 +*I FTB_18__17:A I *L 0.001776 *C 34.040 99.280 +*N chany_bottom_in[17]:3 *C 34.040 99.280 +*N chany_bottom_in[17]:4 *C 34.040 99.960 +*N chany_bottom_in[17]:5 *C 28.105 99.960 +*N chany_bottom_in[17]:6 *C 28.060 99.915 +*N chany_bottom_in[17]:7 *C 28.060 80.625 +*N chany_bottom_in[17]:8 *C 28.060 80.580 +*N chany_bottom_in[17]:9 *C 28.388 80.580 +*N chany_bottom_in[17]:10 *C 28.935 80.580 +*N chany_bottom_in[17]:11 *C 28.980 80.535 +*N chany_bottom_in[17]:12 *C 28.980 77.578 +*N chany_bottom_in[17]:13 *C 28.988 77.520 +*N chany_bottom_in[17]:14 *C 38.620 77.520 +*N chany_bottom_in[17]:15 *C 38.640 77.513 +*N chany_bottom_in[17]:16 *C 38.640 53.915 +*N chany_bottom_in[17]:17 *C 38.640 4.088 +*N chany_bottom_in[17]:18 *C 38.660 4.080 +*N chany_bottom_in[17]:19 *C 51.973 4.080 +*N chany_bottom_in[17]:20 *C 51.980 4.022 +*N chany_bottom_in[17]:21 *C 51.980 3.400 +*N chany_bottom_in[17]:22 *C 52.900 3.400 + +*CAP +0 chany_bottom_in[17] 0.0001162239 +1 mux_right_ipin_0\/mux_l2_in_2_:A0 1e-06 +2 FTB_18__17:A 1e-06 +3 chany_bottom_in[17]:3 7.20316e-05 +4 chany_bottom_in[17]:4 0.000335442 +5 chany_bottom_in[17]:5 0.0002911099 +6 chany_bottom_in[17]:6 0.001088152 +7 chany_bottom_in[17]:7 0.001088152 +8 chany_bottom_in[17]:8 5.458801e-05 +9 chany_bottom_in[17]:9 7.749935e-05 +10 chany_bottom_in[17]:10 5.749194e-05 +11 chany_bottom_in[17]:11 0.0002102341 +12 chany_bottom_in[17]:12 0.0002102341 +13 chany_bottom_in[17]:13 0.0005077779 +14 chany_bottom_in[17]:14 0.0005077779 +15 chany_bottom_in[17]:15 0.0008074864 +16 chany_bottom_in[17]:16 0.002376532 +17 chany_bottom_in[17]:17 0.001569046 +18 chany_bottom_in[17]:18 0.000973835 +19 chany_bottom_in[17]:19 0.000973835 +20 chany_bottom_in[17]:20 4.942229e-05 +21 chany_bottom_in[17]:21 0.0001007613 +22 chany_bottom_in[17]:22 0.0001675629 +23 chany_bottom_in[17]:13 chany_bottom_in[4]:19 1.078086e-05 +24 chany_bottom_in[17]:14 chany_bottom_in[4]:18 1.078086e-05 +25 chany_bottom_in[17]:15 chany_bottom_in[4]:20 0.000289448 +26 chany_bottom_in[17]:17 chany_bottom_in[4]:21 1.148697e-05 +27 chany_bottom_in[17]:17 chany_bottom_in[4]:22 0.0007610692 +28 chany_bottom_in[17]:16 chany_bottom_in[4]:20 1.148697e-05 +29 chany_bottom_in[17]:16 chany_bottom_in[4]:21 0.001050517 +30 chany_bottom_in[17]:5 ropt_net_200:3 0.0001932144 +31 chany_bottom_in[17]:4 ropt_net_200:4 0.0001932144 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:22 0.001852679 +1 chany_bottom_in[17]:3 FTB_18__17:A 0.152 +2 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.005299107 +3 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.0045 +4 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.0045 +5 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.01722322 +6 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.0004888393 +7 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.0045 +8 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.002640625 +9 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.00341 +10 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.001509092 +11 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.00341 +12 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.00341 +13 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.007806308 +14 chany_bottom_in[17]:20 chany_bottom_in[17]:19 0.00341 +15 chany_bottom_in[17]:19 chany_bottom_in[17]:18 0.002085625 +16 chany_bottom_in[17]:9 mux_right_ipin_0\/mux_l2_in_2_:A0 0.152 +17 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.0001779891 +18 chany_bottom_in[17]:4 chany_bottom_in[17]:3 0.0006071429 +19 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.0005558036 +20 chany_bottom_in[17]:22 chany_bottom_in[17]:21 0.0008214285 +21 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.003696942 + +*END + +*D_NET chany_bottom_in[19] 0.01095336 //LENGTH 108.910 LUMPCC 0.001295027 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 25.760 1.210 +*I BUFT_RR_55:A I *L 0.001776 *C 18.860 102.000 +*N chany_bottom_in[19]:2 *C 18.860 102.000 +*N chany_bottom_in[19]:3 *C 18.860 102.000 +*N chany_bottom_in[19]:4 *C 18.867 102.000 +*N chany_bottom_in[19]:5 *C 24.832 102.000 +*N chany_bottom_in[19]:6 *C 24.840 101.943 +*N chany_bottom_in[19]:7 *C 24.840 54.575 +*N chany_bottom_in[19]:8 *C 24.840 4.817 +*N chany_bottom_in[19]:9 *C 24.848 4.760 +*N chany_bottom_in[19]:10 *C 25.740 4.760 +*N chany_bottom_in[19]:11 *C 25.760 4.753 + +*CAP +0 chany_bottom_in[19] 0.0002449867 +1 BUFT_RR_55:A 1e-06 +2 chany_bottom_in[19]:2 3.617771e-05 +3 chany_bottom_in[19]:3 2.999749e-05 +4 chany_bottom_in[19]:4 0.0003777122 +5 chany_bottom_in[19]:5 0.0003777122 +6 chany_bottom_in[19]:6 0.002092398 +7 chany_bottom_in[19]:7 0.004094506 +8 chany_bottom_in[19]:8 0.002002107 +9 chany_bottom_in[19]:9 7.8374e-05 +10 chany_bottom_in[19]:10 7.8374e-05 +11 chany_bottom_in[19]:11 0.0002449867 +12 chany_bottom_in[19] chany_bottom_in[1]:13 6.510356e-06 +13 chany_bottom_in[19]:8 chany_bottom_in[1]:11 2.560991e-05 +14 chany_bottom_in[19]:8 chany_bottom_in[1]:13 0.0002554356 +15 chany_bottom_in[19]:9 chany_bottom_in[1]:15 1.702142e-06 +16 chany_bottom_in[19]:10 chany_bottom_in[1]:14 1.702142e-06 +17 chany_bottom_in[19]:11 chany_bottom_in[1]:12 6.510356e-06 +18 chany_bottom_in[19]:7 chany_bottom_in[1]:10 2.560991e-05 +19 chany_bottom_in[19]:7 chany_bottom_in[1]:12 0.0002554356 +20 chany_bottom_in[19]:6 chany_bottom_in[6]:12 0.0002339852 +21 chany_bottom_in[19]:8 chany_bottom_in[6]:13 1.063694e-05 +22 chany_bottom_in[19]:8 chany_bottom_in[6]:17 2.752913e-05 +23 chany_bottom_in[19]:7 chany_bottom_in[6]:12 1.063694e-05 +24 chany_bottom_in[19]:7 chany_bottom_in[6]:13 0.0002339852 +25 chany_bottom_in[19]:7 chany_bottom_in[6]:16 2.752913e-05 +26 chany_bottom_in[19]:6 ropt_net_173:4 8.610429e-05 +27 chany_bottom_in[19]:7 ropt_net_173:5 8.610429e-05 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:11 0.0005549916 +1 chany_bottom_in[19]:2 BUFT_RR_55:A 0.152 +2 chany_bottom_in[19]:3 chany_bottom_in[19]:2 0.0045 +3 chany_bottom_in[19]:4 chany_bottom_in[19]:3 0.00341 +4 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.00341 +5 chany_bottom_in[19]:5 chany_bottom_in[19]:4 0.0009345166 +6 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.04442634 +7 chany_bottom_in[19]:9 chany_bottom_in[19]:8 0.00341 +8 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.000139825 +9 chany_bottom_in[19]:11 chany_bottom_in[19]:10 0.00341 +10 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.04229242 + +*END + +*D_NET chany_top_in[1] 0.01485111 //LENGTH 133.190 LUMPCC 0.003069019 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 34.500 107.510 +*I mux_right_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 32.030 58.820 +*I ropt_mt_inst_760:A I *L 0.001767 *C 59.340 6.800 +*N chany_top_in[1]:3 *C 59.303 6.800 +*N chany_top_in[1]:4 *C 57.040 6.800 +*N chany_top_in[1]:5 *C 57.040 7.140 +*N chany_top_in[1]:6 *C 53.865 7.140 +*N chany_top_in[1]:7 *C 53.820 7.185 +*N chany_top_in[1]:8 *C 53.820 11.515 +*N chany_top_in[1]:9 *C 53.775 11.560 +*N chany_top_in[1]:10 *C 47.840 11.560 +*N chany_top_in[1]:11 *C 47.840 12.240 +*N chany_top_in[1]:12 *C 46.505 12.240 +*N chany_top_in[1]:13 *C 46.460 12.285 +*N chany_top_in[1]:14 *C 46.460 44.155 +*N chany_top_in[1]:15 *C 46.415 44.200 +*N chany_top_in[1]:16 *C 43.285 44.200 +*N chany_top_in[1]:17 *C 43.240 44.200 +*N chany_top_in[1]:18 *C 43.240 44.820 +*N chany_top_in[1]:19 *C 43.240 44.865 +*N chany_top_in[1]:20 *C 40.835 44.880 +*N chany_top_in[1]:21 *C 38.225 44.880 +*N chany_top_in[1]:22 *C 38.180 44.925 +*N chany_top_in[1]:23 *C 38.180 58.775 +*N chany_top_in[1]:24 *C 38.135 58.820 +*N chany_top_in[1]:25 *C 32.068 58.820 +*N chany_top_in[1]:26 *C 35.420 58.820 +*N chany_top_in[1]:27 *C 35.420 58.865 +*N chany_top_in[1]:28 *C 35.420 98.895 +*N chany_top_in[1]:29 *C 35.375 98.940 +*N chany_top_in[1]:30 *C 34.545 98.940 +*N chany_top_in[1]:31 *C 34.500 98.985 + +*CAP +0 chany_top_in[1] 0.0004183496 +1 mux_right_ipin_0\/mux_l1_in_0_:A0 1e-06 +2 ropt_mt_inst_760:A 1e-06 +3 chany_top_in[1]:3 0.0001207017 +4 chany_top_in[1]:4 0.0001445938 +5 chany_top_in[1]:5 0.0001915752 +6 chany_top_in[1]:6 0.0001676832 +7 chany_top_in[1]:7 0.0002438628 +8 chany_top_in[1]:8 0.0002438628 +9 chany_top_in[1]:9 0.0003859414 +10 chany_top_in[1]:10 0.0004209031 +11 chany_top_in[1]:11 0.0001261436 +12 chany_top_in[1]:12 9.118186e-05 +13 chany_top_in[1]:13 0.00100859 +14 chany_top_in[1]:14 0.00100859 +15 chany_top_in[1]:15 0.0002187051 +16 chany_top_in[1]:16 0.0002187051 +17 chany_top_in[1]:17 8.960445e-05 +18 chany_top_in[1]:18 6.23336e-05 +19 chany_top_in[1]:19 0.0001773484 +20 chany_top_in[1]:20 0.0002953968 +21 chany_top_in[1]:21 0.0001516637 +22 chany_top_in[1]:22 0.0006983125 +23 chany_top_in[1]:23 0.0006983125 +24 chany_top_in[1]:24 0.0001676177 +25 chany_top_in[1]:25 0.0001813741 +26 chany_top_in[1]:26 0.000381768 +27 chany_top_in[1]:27 0.001678051 +28 chany_top_in[1]:28 0.001678051 +29 chany_top_in[1]:29 4.626043e-05 +30 chany_top_in[1]:30 4.626043e-05 +31 chany_top_in[1]:31 0.0004183496 +32 chany_top_in[1]:13 chany_top_in[4]:7 0.0003612386 +33 chany_top_in[1]:14 chany_top_in[4]:8 0.0003612386 +34 chany_top_in[1]:11 chany_top_in[4]:8 8.223255e-06 +35 chany_top_in[1]:10 chany_top_in[4]:7 8.223255e-06 +36 chany_top_in[1]:13 chany_top_in[15]:8 0.0002739003 +37 chany_top_in[1]:14 chany_top_in[15]:9 0.0002739003 +38 chany_top_in[1]:26 mux_tree_tapbuf_size10_1_sram[0]:7 8.118644e-05 +39 chany_top_in[1]:27 mux_tree_tapbuf_size10_1_sram[0]:15 0.0001135641 +40 chany_top_in[1]:27 mux_tree_tapbuf_size10_1_sram[0]:18 7.38688e-05 +41 chany_top_in[1]:27 mux_tree_tapbuf_size10_1_sram[0]:11 0.0001782233 +42 chany_top_in[1]:27 mux_tree_tapbuf_size10_1_sram[0]:8 3.78624e-05 +43 chany_top_in[1]:28 mux_tree_tapbuf_size10_1_sram[0]:19 7.38688e-05 +44 chany_top_in[1]:28 mux_tree_tapbuf_size10_1_sram[0]:12 0.0001782233 +45 chany_top_in[1]:28 mux_tree_tapbuf_size10_1_sram[0]:18 0.0001135641 +46 chany_top_in[1]:28 mux_tree_tapbuf_size10_1_sram[0]:11 3.78624e-05 +47 chany_top_in[1]:25 mux_tree_tapbuf_size10_1_sram[0]:6 8.118644e-05 +48 chany_top_in[1]:27 ropt_net_183:4 6.514995e-07 +49 chany_top_in[1]:29 ropt_net_183:7 4.588169e-05 +50 chany_top_in[1]:28 ropt_net_183:5 6.514995e-07 +51 chany_top_in[1]:30 ropt_net_183:6 4.588169e-05 +52 chany_top_in[1]:3 ropt_net_191:9 3.604051e-05 +53 chany_top_in[1]:6 ropt_net_191:8 1.226267e-06 +54 chany_top_in[1]:6 ropt_net_191:4 7.961701e-05 +55 chany_top_in[1]:5 ropt_net_191:9 1.226267e-06 +56 chany_top_in[1]:5 ropt_net_191:5 7.961701e-05 +57 chany_top_in[1]:4 ropt_net_191:8 3.604051e-05 +58 chany_top_in[1] ropt_net_202:4 9.093643e-05 +59 chany_top_in[1]:27 ropt_net_202:5 1.082265e-05 +60 chany_top_in[1]:28 ropt_net_202:4 1.082265e-05 +61 chany_top_in[1]:31 ropt_net_202:5 9.093643e-05 +62 chany_top_in[1]:13 ropt_net_165:4 0.0001412666 +63 chany_top_in[1]:14 ropt_net_165:5 0.0001412666 + +*RES +0 chany_top_in[1] chany_top_in[1]:31 0.007611607 +1 chany_top_in[1]:3 ropt_mt_inst_760:A 0.152 +2 chany_top_in[1]:6 chany_top_in[1]:5 0.002834822 +3 chany_top_in[1]:7 chany_top_in[1]:6 0.0045 +4 chany_top_in[1]:9 chany_top_in[1]:8 0.0045 +5 chany_top_in[1]:8 chany_top_in[1]:7 0.003866072 +6 chany_top_in[1]:12 chany_top_in[1]:11 0.001191964 +7 chany_top_in[1]:13 chany_top_in[1]:12 0.0045 +8 chany_top_in[1]:15 chany_top_in[1]:14 0.0045 +9 chany_top_in[1]:14 chany_top_in[1]:13 0.02845536 +10 chany_top_in[1]:16 chany_top_in[1]:15 0.002794643 +11 chany_top_in[1]:17 chany_top_in[1]:16 0.0045 +12 chany_top_in[1]:26 chany_top_in[1]:25 0.002993304 +13 chany_top_in[1]:26 chany_top_in[1]:24 0.002424107 +14 chany_top_in[1]:27 chany_top_in[1]:26 0.0045 +15 chany_top_in[1]:29 chany_top_in[1]:28 0.0045 +16 chany_top_in[1]:28 chany_top_in[1]:27 0.03574108 +17 chany_top_in[1]:30 chany_top_in[1]:29 0.0007410715 +18 chany_top_in[1]:31 chany_top_in[1]:30 0.0045 +19 chany_top_in[1]:19 chany_top_in[1]:18 0.0045 +20 chany_top_in[1]:18 chany_top_in[1]:17 0.0005535714 +21 chany_top_in[1]:21 chany_top_in[1]:20 0.002330357 +22 chany_top_in[1]:22 chany_top_in[1]:21 0.0045 +23 chany_top_in[1]:24 chany_top_in[1]:23 0.0045 +24 chany_top_in[1]:23 chany_top_in[1]:22 0.01236607 +25 chany_top_in[1]:25 mux_right_ipin_0\/mux_l1_in_0_:A0 0.152 +26 chany_top_in[1]:20 chany_top_in[1]:19 0.002147322 +27 chany_top_in[1]:11 chany_top_in[1]:10 0.0006071429 +28 chany_top_in[1]:10 chany_top_in[1]:9 0.005299108 +29 chany_top_in[1]:5 chany_top_in[1]:4 0.0003035715 +30 chany_top_in[1]:4 chany_top_in[1]:3 0.002020089 + +*END + +*D_NET chany_top_in[4] 0.01488812 //LENGTH 136.600 LUMPCC 0.00252238 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 51.060 107.510 +*I ropt_mt_inst_754:A I *L 0.001767 *C 36.340 6.800 +*I mux_left_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 69.750 71.740 +*N chany_top_in[4]:3 *C 69.713 71.740 +*N chany_top_in[4]:4 *C 36.363 6.828 +*N chany_top_in[4]:5 *C 36.375 7.140 +*N chany_top_in[4]:6 *C 46.875 7.140 +*N chany_top_in[4]:7 *C 46.920 7.185 +*N chany_top_in[4]:8 *C 46.920 25.115 +*N chany_top_in[4]:9 *C 46.965 25.160 +*N chany_top_in[4]:10 *C 49.100 25.160 +*N chany_top_in[4]:11 *C 49.213 25.205 +*N chany_top_in[4]:12 *C 49.220 25.795 +*N chany_top_in[4]:13 *C 49.265 25.840 +*N chany_top_in[4]:14 *C 50.140 25.840 +*N chany_top_in[4]:15 *C 50.140 25.885 +*N chany_top_in[4]:16 *C 50.140 71.695 +*N chany_top_in[4]:17 *C 50.185 71.740 +*N chany_top_in[4]:18 *C 51.060 71.740 +*N chany_top_in[4]:19 *C 51.060 71.785 + +*CAP +0 chany_top_in[4] 0.001792639 +1 ropt_mt_inst_754:A 1e-06 +2 mux_left_ipin_0\/mux_l1_in_2_:A0 1e-06 +3 chany_top_in[4]:3 0.001064716 +4 chany_top_in[4]:4 3.207829e-05 +5 chany_top_in[4]:5 0.0006448819 +6 chany_top_in[4]:6 0.0006128036 +7 chany_top_in[4]:7 0.0005964264 +8 chany_top_in[4]:8 0.0005964264 +9 chany_top_in[4]:9 0.0001549155 +10 chany_top_in[4]:10 0.0001549155 +11 chany_top_in[4]:11 4.235893e-05 +12 chany_top_in[4]:12 4.235893e-05 +13 chany_top_in[4]:13 6.770629e-05 +14 chany_top_in[4]:14 9.891242e-05 +15 chany_top_in[4]:15 0.001727117 +16 chany_top_in[4]:16 0.001727117 +17 chany_top_in[4]:17 5.835773e-05 +18 chany_top_in[4]:18 0.001157374 +19 chany_top_in[4]:19 0.001792639 +20 chany_top_in[4]:8 chany_top_in[1]:11 8.223255e-06 +21 chany_top_in[4]:8 chany_top_in[1]:14 0.0003612386 +22 chany_top_in[4]:7 chany_top_in[1]:10 8.223255e-06 +23 chany_top_in[4]:7 chany_top_in[1]:13 0.0003612386 +24 chany_top_in[4]:16 chany_top_in[10]:13 0.0003973661 +25 chany_top_in[4]:15 chany_top_in[10]:12 0.0003973661 +26 chany_top_in[4]:12 chany_top_in[10]:13 3.704242e-06 +27 chany_top_in[4]:11 chany_top_in[10]:12 3.704242e-06 +28 chany_top_in[4]:16 chany_top_in[15]:9 4.694312e-05 +29 chany_top_in[4]:15 chany_top_in[15]:8 4.694312e-05 +30 chany_top_in[4]:8 chany_top_in[15]:9 0.0002104246 +31 chany_top_in[4]:7 chany_top_in[15]:8 0.0002104246 +32 chany_top_in[4] mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.25568e-07 +33 chany_top_in[4]:19 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.25568e-07 +34 chany_top_in[4]:16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.653642e-05 +35 chany_top_in[4]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.653642e-05 +36 chany_top_in[4]:6 ropt_net_216:3 6.15336e-05 +37 chany_top_in[4]:5 ropt_net_216:2 6.15336e-05 +38 chany_top_in[4] ropt_net_147:4 9.44948e-05 +39 chany_top_in[4]:19 ropt_net_147:5 9.44948e-05 + +*RES +0 chany_top_in[4] chany_top_in[4]:19 0.03189733 +1 chany_top_in[4]:18 chany_top_in[4]:17 0.00078125 +2 chany_top_in[4]:18 chany_top_in[4]:3 0.01665402 +3 chany_top_in[4]:19 chany_top_in[4]:18 0.0045 +4 chany_top_in[4]:17 chany_top_in[4]:16 0.0045 +5 chany_top_in[4]:16 chany_top_in[4]:15 0.04090179 +6 chany_top_in[4]:14 chany_top_in[4]:13 0.0007812501 +7 chany_top_in[4]:15 chany_top_in[4]:14 0.0045 +8 chany_top_in[4]:13 chany_top_in[4]:12 0.0045 +9 chany_top_in[4]:12 chany_top_in[4]:11 0.0005267857 +10 chany_top_in[4]:10 chany_top_in[4]:9 0.00190625 +11 chany_top_in[4]:11 chany_top_in[4]:10 0.0045 +12 chany_top_in[4]:9 chany_top_in[4]:8 0.0045 +13 chany_top_in[4]:8 chany_top_in[4]:7 0.01600893 +14 chany_top_in[4]:6 chany_top_in[4]:5 0.009375 +15 chany_top_in[4]:7 chany_top_in[4]:6 0.0045 +16 chany_top_in[4]:4 ropt_mt_inst_754:A 0.152 +17 chany_top_in[4]:3 mux_left_ipin_0\/mux_l1_in_2_:A0 0.152 +18 chany_top_in[4]:5 chany_top_in[4]:4 0.0002111487 + +*END + +*D_NET chany_top_in[7] 0.01130443 //LENGTH 93.450 LUMPCC 0.006251041 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 68.540 107.510 +*I BUFT_RR_63:A I *L 0.001776 *C 69.000 14.960 +*N chany_top_in[7]:2 *C 69.000 14.960 +*N chany_top_in[7]:3 *C 68.970 14.990 +*N chany_top_in[7]:4 *C 68.955 15.300 +*N chany_top_in[7]:5 *C 68.540 15.300 +*N chany_top_in[7]:6 *C 68.540 65.230 + +*CAP +0 chany_top_in[7] 0.001203238 +1 BUFT_RR_63:A 1e-06 +2 chany_top_in[7]:2 3.223086e-05 +3 chany_top_in[7]:3 4.238585e-05 +4 chany_top_in[7]:4 7.033463e-05 +5 chany_top_in[7]:5 0.001264456 +6 chany_top_in[7]:6 0.002439745 +7 chany_top_in[7] chany_top_in[2]:5 6.481398e-05 +8 chany_top_in[7] chany_top_in[2]:8 0.000505155 +9 chany_top_in[7] chany_top_in[2]:10 0.0001314831 +10 chany_top_in[7]:5 chany_top_in[2]:4 0.001319734 +11 chany_top_in[7]:6 chany_top_in[2]:4 6.481398e-05 +12 chany_top_in[7]:6 chany_top_in[2]:5 0.001824889 +13 chany_top_in[7]:6 chany_top_in[2]:9 0.0001314831 +14 chany_top_in[7] chany_top_in[12] 0.000396928 +15 chany_top_in[7] chany_top_in[12]:17 0.0001762375 +16 chany_top_in[7]:5 chany_top_in[12]:16 0.0005311688 +17 chany_top_in[7]:6 chany_top_in[12]:16 0.0001762375 +18 chany_top_in[7]:6 chany_top_in[12]:17 0.0009280967 + +*RES +0 chany_top_in[7] chany_top_in[7]:6 0.03775 +1 chany_top_in[7]:2 BUFT_RR_63:A 0.152 +2 chany_top_in[7]:3 chany_top_in[7]:2 0.0045 +3 chany_top_in[7]:5 chany_top_in[7]:4 0.0003705357 +4 chany_top_in[7]:4 chany_top_in[7]:3 0.00019375 +5 chany_top_in[7]:6 chany_top_in[7]:5 0.04458036 + +*END + +*D_NET chany_top_in[10] 0.01313489 //LENGTH 120.770 LUMPCC 0.004333829 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 42.780 107.510 +*I ropt_mt_inst_762:A I *L 0.001767 *C 53.820 4.080 +*I mux_left_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 54.380 52.700 +*N chany_top_in[10]:3 *C 54.343 52.700 +*N chany_top_in[10]:4 *C 53.783 4.080 +*N chany_top_in[10]:5 *C 52.945 4.080 +*N chany_top_in[10]:6 *C 52.900 4.125 +*N chany_top_in[10]:7 *C 52.900 22.440 +*N chany_top_in[10]:8 *C 53.360 22.440 +*N chany_top_in[10]:9 *C 53.360 23.075 +*N chany_top_in[10]:10 *C 53.315 23.120 +*N chany_top_in[10]:11 *C 51.060 23.120 +*N chany_top_in[10]:12 *C 51.060 23.165 +*N chany_top_in[10]:13 *C 51.060 52.655 +*N chany_top_in[10]:14 *C 51.060 52.700 +*N chany_top_in[10]:15 *C 42.825 52.700 +*N chany_top_in[10]:16 *C 42.780 52.745 + +*CAP +0 chany_top_in[10] 0.001824643 +1 ropt_mt_inst_762:A 1e-06 +2 mux_left_ipin_0\/mux_l2_in_2_:A1 1e-06 +3 chany_top_in[10]:3 0.000174942 +4 chany_top_in[10]:4 7.591389e-05 +5 chany_top_in[10]:5 7.591389e-05 +6 chany_top_in[10]:6 0.0009180285 +7 chany_top_in[10]:7 0.0009442061 +8 chany_top_in[10]:8 6.228181e-05 +9 chany_top_in[10]:9 3.610428e-05 +10 chany_top_in[10]:10 0.0001369623 +11 chany_top_in[10]:11 0.0001684069 +12 chany_top_in[10]:12 0.0007270873 +13 chany_top_in[10]:13 0.0007270873 +14 chany_top_in[10]:14 0.0006544073 +15 chany_top_in[10]:15 0.0004484332 +16 chany_top_in[10]:16 0.001824643 +17 chany_top_in[10]:13 chany_bottom_in[0]:13 0.0004361238 +18 chany_top_in[10]:12 chany_bottom_in[0]:14 0.0004361238 +19 chany_top_in[10]:9 chany_bottom_in[0]:13 7.443227e-06 +20 chany_top_in[10]:6 chany_bottom_in[0]:14 3.897219e-05 +21 chany_top_in[10]:7 chany_bottom_in[0]:13 3.897219e-05 +22 chany_top_in[10]:8 chany_bottom_in[0]:14 7.443227e-06 +23 chany_top_in[10] chany_bottom_in[15]:5 0.0004188505 +24 chany_top_in[10] chany_bottom_in[15]:6 0.0002165916 +25 chany_top_in[10]:16 chany_bottom_in[15]:6 0.0004188505 +26 chany_top_in[10]:16 chany_bottom_in[15]:7 0.0002165916 +27 chany_top_in[10] chany_bottom_in[16]:10 0.000619227 +28 chany_top_in[10]:14 chany_bottom_in[16]:4 2.447824e-05 +29 chany_top_in[10]:13 chany_bottom_in[16]:20 4.157621e-06 +30 chany_top_in[10]:12 chany_bottom_in[16] 4.157621e-06 +31 chany_top_in[10]:3 chany_bottom_in[16]:3 2.447824e-05 +32 chany_top_in[10]:16 chany_bottom_in[16]:11 0.000619227 +33 chany_top_in[10]:13 chany_top_in[4]:12 3.704242e-06 +34 chany_top_in[10]:13 chany_top_in[4]:16 0.0003973661 +35 chany_top_in[10]:12 chany_top_in[4]:11 3.704242e-06 +36 chany_top_in[10]:12 chany_top_in[4]:15 0.0003973661 + +*RES +0 chany_top_in[10] chany_top_in[10]:16 0.04889733 +1 chany_top_in[10]:14 chany_top_in[10]:13 0.0045 +2 chany_top_in[10]:14 chany_top_in[10]:3 0.002930804 +3 chany_top_in[10]:13 chany_top_in[10]:12 0.02633036 +4 chany_top_in[10]:11 chany_top_in[10]:10 0.002013393 +5 chany_top_in[10]:12 chany_top_in[10]:11 0.0045 +6 chany_top_in[10]:10 chany_top_in[10]:9 0.0045 +7 chany_top_in[10]:9 chany_top_in[10]:8 0.0005669643 +8 chany_top_in[10]:5 chany_top_in[10]:4 0.0007477679 +9 chany_top_in[10]:6 chany_top_in[10]:5 0.0045 +10 chany_top_in[10]:4 ropt_mt_inst_762:A 0.152 +11 chany_top_in[10]:3 mux_left_ipin_0\/mux_l2_in_2_:A1 0.152 +12 chany_top_in[10]:15 chany_top_in[10]:14 0.007352679 +13 chany_top_in[10]:16 chany_top_in[10]:15 0.0045 +14 chany_top_in[10]:7 chany_top_in[10]:6 0.01635268 +15 chany_top_in[10]:8 chany_top_in[10]:7 0.0004107143 + +*END + +*D_NET chany_top_in[13] 0.01463246 //LENGTH 135.440 LUMPCC 0.006555942 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 49.680 107.590 +*I ropt_mt_inst_766:A I *L 0.001767 *C 20.700 4.080 +*N chany_top_in[13]:2 *C 20.663 4.080 +*N chany_top_in[13]:3 *C 20.285 4.080 +*N chany_top_in[13]:4 *C 20.240 4.125 +*N chany_top_in[13]:5 *C 20.240 8.795 +*N chany_top_in[13]:6 *C 20.285 8.840 +*N chany_top_in[13]:7 *C 34.380 8.840 +*N chany_top_in[13]:8 *C 34.492 8.885 +*N chany_top_in[13]:9 *C 34.500 9.475 +*N chany_top_in[13]:10 *C 34.545 9.520 +*N chany_top_in[13]:11 *C 35.375 9.520 +*N chany_top_in[13]:12 *C 35.420 9.520 +*N chany_top_in[13]:13 *C 35.428 9.520 +*N chany_top_in[13]:14 *C 49.660 9.520 +*N chany_top_in[13]:15 *C 49.680 9.527 +*N chany_top_in[13]:16 *C 49.680 59.355 + +*CAP +0 chany_top_in[13] 0.0012247 +1 ropt_mt_inst_766:A 1e-06 +2 chany_top_in[13]:2 3.788043e-05 +3 chany_top_in[13]:3 3.788043e-05 +4 chany_top_in[13]:4 0.0002215441 +5 chany_top_in[13]:5 0.0002215441 +6 chany_top_in[13]:6 0.0008872983 +7 chany_top_in[13]:7 0.0008872983 +8 chany_top_in[13]:8 4.559399e-05 +9 chany_top_in[13]:9 4.559399e-05 +10 chany_top_in[13]:10 7.534718e-05 +11 chany_top_in[13]:11 7.534718e-05 +12 chany_top_in[13]:12 2.876183e-05 +13 chany_top_in[13]:13 0.0008933578 +14 chany_top_in[13]:14 0.0008933578 +15 chany_top_in[13]:15 0.0006376549 +16 chany_top_in[13]:16 0.001862355 +17 chany_top_in[13] chany_bottom_in[10]:27 4.439447e-06 +18 chany_top_in[13] chany_bottom_in[10]:34 0.0001986212 +19 chany_top_in[13]:15 chany_bottom_in[10]:35 0.0001150246 +20 chany_top_in[13]:15 chany_bottom_in[10]:36 0.0006810453 +21 chany_top_in[13]:16 chany_bottom_in[10]:34 0.000119464 +22 chany_top_in[13]:16 chany_bottom_in[10]:35 0.0008796664 +23 chany_top_in[13] chany_bottom_in[18]:11 5.98971e-05 +24 chany_top_in[13] chany_bottom_in[18]:15 0.0001385058 +25 chany_top_in[13]:15 chany_bottom_in[18] 0.0009634899 +26 chany_top_in[13]:15 chany_bottom_in[18]:16 0.0002040746 +27 chany_top_in[13]:16 chany_bottom_in[18]:12 5.98971e-05 +28 chany_top_in[13]:16 chany_bottom_in[18]:15 0.0002040746 +29 chany_top_in[13]:16 chany_bottom_in[18]:16 0.001101996 +30 chany_top_in[13] chany_top_in[15] 0.0008938809 +31 chany_top_in[13]:15 chany_top_in[15]:4 1.899211e-05 +32 chany_top_in[13]:16 chany_top_in[15]:5 1.899211e-05 +33 chany_top_in[13]:16 chany_top_in[15]:12 0.0008938809 + +*RES +0 chany_top_in[13] chany_top_in[13]:16 0.007556816 +1 chany_top_in[13]:2 ropt_mt_inst_766:A 0.152 +2 chany_top_in[13]:3 chany_top_in[13]:2 0.0003370536 +3 chany_top_in[13]:4 chany_top_in[13]:3 0.0045 +4 chany_top_in[13]:6 chany_top_in[13]:5 0.0045 +5 chany_top_in[13]:5 chany_top_in[13]:4 0.004169643 +6 chany_top_in[13]:7 chany_top_in[13]:6 0.01258482 +7 chany_top_in[13]:8 chany_top_in[13]:7 0.0045 +8 chany_top_in[13]:10 chany_top_in[13]:9 0.0045 +9 chany_top_in[13]:9 chany_top_in[13]:8 0.0005267857 +10 chany_top_in[13]:11 chany_top_in[13]:10 0.0007410714 +11 chany_top_in[13]:12 chany_top_in[13]:11 0.0045 +12 chany_top_in[13]:13 chany_top_in[13]:12 0.00341 +13 chany_top_in[13]:14 chany_top_in[13]:13 0.002229758 +14 chany_top_in[13]:15 chany_top_in[13]:14 0.00341 +15 chany_top_in[13]:16 chany_top_in[13]:15 0.007806308 + +*END + +*D_NET chany_top_in[16] 0.01466298 //LENGTH 140.590 LUMPCC 0.0008654012 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 28.520 107.475 +*I ropt_mt_inst_773:A I *L 0.001767 *C 58.420 4.080 +*I mux_left_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 56.120 63.580 +*N chany_top_in[16]:3 *C 56.120 63.595 +*N chany_top_in[16]:4 *C 56.120 63.920 +*N chany_top_in[16]:5 *C 56.120 63.920 +*N chany_top_in[16]:6 *C 58.420 4.080 +*N chany_top_in[16]:7 *C 58.420 4.125 +*N chany_top_in[16]:8 *C 58.420 16.660 +*N chany_top_in[16]:9 *C 58.880 16.660 +*N chany_top_in[16]:10 *C 58.880 19.675 +*N chany_top_in[16]:11 *C 58.835 19.720 +*N chany_top_in[16]:12 *C 56.245 19.720 +*N chany_top_in[16]:13 *C 56.130 19.765 +*N chany_top_in[16]:14 *C 56.120 20.355 +*N chany_top_in[16]:15 *C 56.075 20.400 +*N chany_top_in[16]:16 *C 55.200 20.400 +*N chany_top_in[16]:17 *C 55.200 20.445 +*N chany_top_in[16]:18 *C 55.200 63.920 +*N chany_top_in[16]:19 *C 55.200 106.703 +*N chany_top_in[16]:20 *C 55.200 106.767 +*N chany_top_in[16]:21 *C 55.200 107.440 +*N chany_top_in[16]:22 *C 35.880 107.440 +*N chany_top_in[16]:23 *C 35.880 106.760 +*N chany_top_in[16]:24 *C 28.527 106.760 +*N chany_top_in[16]:25 *C 28.520 106.818 + +*CAP +0 chany_top_in[16] 6.733733e-05 +1 ropt_mt_inst_773:A 1e-06 +2 mux_left_ipin_0\/mux_l2_in_3_:A1 1e-06 +3 chany_top_in[16]:3 3.119903e-05 +4 chany_top_in[16]:4 6.608816e-05 +5 chany_top_in[16]:5 5.86348e-05 +6 chany_top_in[16]:6 3.182168e-05 +7 chany_top_in[16]:7 0.0006089151 +8 chany_top_in[16]:8 0.0006338174 +9 chany_top_in[16]:9 0.0001835586 +10 chany_top_in[16]:10 0.0001586563 +11 chany_top_in[16]:11 0.0001738444 +12 chany_top_in[16]:12 0.0001738444 +13 chany_top_in[16]:13 4.939862e-05 +14 chany_top_in[16]:14 4.939862e-05 +15 chany_top_in[16]:15 6.644766e-05 +16 chany_top_in[16]:16 9.47344e-05 +17 chany_top_in[16]:17 0.001955527 +18 chany_top_in[16]:18 0.003877619 +19 chany_top_in[16]:19 0.001892737 +20 chany_top_in[16]:20 6.011311e-05 +21 chany_top_in[16]:21 0.001299331 +22 chany_top_in[16]:22 0.001285337 +23 chany_top_in[16]:23 0.0004780017 +24 chany_top_in[16]:24 0.0004318822 +25 chany_top_in[16]:25 6.733733e-05 +26 chany_top_in[16]:19 chany_top_in[0]:19 0.0003064907 +27 chany_top_in[16]:18 chany_top_in[0]:18 0.0003064907 +28 chany_top_in[16]:17 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.087894e-05 +29 chany_top_in[16]:17 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 1.5185e-05 +30 chany_top_in[16]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.529181e-06 +31 chany_top_in[16]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.368889e-05 +32 chany_top_in[16]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.529181e-06 +33 chany_top_in[16]:18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.368889e-05 +34 chany_top_in[16]:18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.087894e-05 +35 chany_top_in[16]:18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.5185e-05 +36 chany_top_in[16]:19 ropt_net_186:4 5.992796e-05 +37 chany_top_in[16]:18 ropt_net_186:5 5.992796e-05 + +*RES +0 chany_top_in[16] chany_top_in[16]:25 0.0005870535 +1 chany_top_in[16]:16 chany_top_in[16]:15 0.00078125 +2 chany_top_in[16]:17 chany_top_in[16]:16 0.0045 +3 chany_top_in[16]:15 chany_top_in[16]:14 0.0045 +4 chany_top_in[16]:14 chany_top_in[16]:13 0.0005267857 +5 chany_top_in[16]:12 chany_top_in[16]:11 0.0023125 +6 chany_top_in[16]:13 chany_top_in[16]:12 0.0045 +7 chany_top_in[16]:11 chany_top_in[16]:10 0.0045 +8 chany_top_in[16]:10 chany_top_in[16]:9 0.002691964 +9 chany_top_in[16]:6 ropt_mt_inst_773:A 0.152 +10 chany_top_in[16]:7 chany_top_in[16]:6 0.0045 +11 chany_top_in[16]:19 chany_top_in[16]:18 0.03819866 +12 chany_top_in[16]:20 chany_top_in[16]:19 0.00341 +13 chany_top_in[16]:25 chany_top_in[16]:24 0.00341 +14 chany_top_in[16]:24 chany_top_in[16]:23 0.001151892 +15 chany_top_in[16]:4 chany_top_in[16]:3 0.0001766304 +16 chany_top_in[16]:5 chany_top_in[16]:4 0.0045 +17 chany_top_in[16]:3 mux_left_ipin_0\/mux_l2_in_3_:A1 0.152 +18 chany_top_in[16]:18 chany_top_in[16]:17 0.03881697 +19 chany_top_in[16]:18 chany_top_in[16]:5 0.0008214285 +20 chany_top_in[16]:8 chany_top_in[16]:7 0.01119197 +21 chany_top_in[16]:9 chany_top_in[16]:8 0.0004107143 +22 chany_top_in[16]:23 chany_top_in[16]:22 0.0001065333 +23 chany_top_in[16]:22 chany_top_in[16]:21 0.0030268 +24 chany_top_in[16]:21 chany_top_in[16]:20 0.0001053583 + +*END + +*D_NET prog_clk[0] 0.01783423 //LENGTH 159.935 LUMPCC 0.002452296 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 1.230 3.400 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 6.245 72.080 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 18.665 77.520 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 23.725 82.960 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 29.705 88.400 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 34.305 96.560 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 53.625 96.560 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 53.255 99.280 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 32.925 93.840 +*N prog_clk[0]:9 *C 32.925 93.840 +*N prog_clk[0]:10 *C 53.783 96.900 +*N prog_clk[0]:11 *C 53.255 99.280 +*N prog_clk[0]:12 *C 53.360 99.235 +*N prog_clk[0]:13 *C 53.360 96.900 +*N prog_clk[0]:14 *C 53.625 96.560 +*N prog_clk[0]:15 *C 53.820 96.900 +*N prog_clk[0]:16 *C 53.820 96.900 +*N prog_clk[0]:17 *C 53.820 96.560 +*N prog_clk[0]:18 *C 53.812 96.560 +*N prog_clk[0]:19 *C 33.128 96.560 +*N prog_clk[0]:20 *C 34.267 96.560 +*N prog_clk[0]:21 *C 33.165 96.560 +*N prog_clk[0]:22 *C 33.120 96.560 +*N prog_clk[0]:23 *C 33.120 93.545 +*N prog_clk[0]:24 *C 33.075 93.508 +*N prog_clk[0]:25 *C 29.025 93.500 +*N prog_clk[0]:26 *C 28.980 93.455 +*N prog_clk[0]:27 *C 29.668 88.400 +*N prog_clk[0]:28 *C 28.980 88.400 +*N prog_clk[0]:29 *C 28.980 88.060 +*N prog_clk[0]:30 *C 28.980 88.105 +*N prog_clk[0]:31 *C 28.520 88.060 +*N prog_clk[0]:32 *C 28.520 85.045 +*N prog_clk[0]:33 *C 28.475 85.000 +*N prog_clk[0]:34 *C 22.585 85.000 +*N prog_clk[0]:35 *C 22.540 84.955 +*N prog_clk[0]:36 *C 23.688 82.960 +*N prog_clk[0]:37 *C 23.000 82.960 +*N prog_clk[0]:38 *C 23.000 82.620 +*N prog_clk[0]:39 *C 22.585 82.620 +*N prog_clk[0]:40 *C 22.540 82.620 +*N prog_clk[0]:41 *C 22.540 77.578 +*N prog_clk[0]:42 *C 22.533 77.520 +*N prog_clk[0]:43 *C 18.665 77.520 +*N prog_clk[0]:44 *C 18.400 77.520 +*N prog_clk[0]:45 *C 18.400 77.520 +*N prog_clk[0]:46 *C 18.400 77.520 +*N prog_clk[0]:47 *C 6.448 77.520 +*N prog_clk[0]:48 *C 6.440 77.463 +*N prog_clk[0]:49 *C 6.245 72.080 +*N prog_clk[0]:50 *C 6.440 71.740 +*N prog_clk[0]:51 *C 6.440 71.740 +*N prog_clk[0]:52 *C 6.440 70.778 +*N prog_clk[0]:53 *C 6.433 70.720 +*N prog_clk[0]:54 *C 1.860 70.720 +*N prog_clk[0]:55 *C 1.840 70.713 +*N prog_clk[0]:56 *C 1.840 53.235 +*N prog_clk[0]:57 *C 1.840 3.408 +*N prog_clk[0]:58 *C 1.820 3.400 + +*CAP +0 prog_clk[0] 5.122882e-05 +1 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +3 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +6 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +7 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +8 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +9 prog_clk[0]:9 6.252308e-05 +10 prog_clk[0]:10 1.724176e-05 +11 prog_clk[0]:11 2.964565e-05 +12 prog_clk[0]:12 0.0001668372 +13 prog_clk[0]:13 0.0001929005 +14 prog_clk[0]:14 7.273541e-05 +15 prog_clk[0]:15 7.284333e-05 +16 prog_clk[0]:16 0.0001011298 +17 prog_clk[0]:17 3.636442e-05 +18 prog_clk[0]:18 0.0008897056 +19 prog_clk[0]:19 0.0008897056 +20 prog_clk[0]:20 9.87033e-05 +21 prog_clk[0]:21 9.87033e-05 +22 prog_clk[0]:22 0.0002107438 +23 prog_clk[0]:23 0.0001739052 +24 prog_clk[0]:24 0.000299412 +25 prog_clk[0]:25 0.0002769001 +26 prog_clk[0]:26 0.0003797588 +27 prog_clk[0]:27 6.499561e-05 +28 prog_clk[0]:28 9.603081e-05 +29 prog_clk[0]:29 6.967595e-05 +30 prog_clk[0]:30 0.000413047 +31 prog_clk[0]:31 0.0002494623 +32 prog_clk[0]:32 0.0002161741 +33 prog_clk[0]:33 0.0004042045 +34 prog_clk[0]:34 0.0004042045 +35 prog_clk[0]:35 0.0001356759 +36 prog_clk[0]:36 6.732507e-05 +37 prog_clk[0]:37 9.239529e-05 +38 prog_clk[0]:38 6.998853e-05 +39 prog_clk[0]:39 4.491831e-05 +40 prog_clk[0]:40 0.0004473606 +41 prog_clk[0]:41 0.0002784678 +42 prog_clk[0]:42 0.0002489273 +43 prog_clk[0]:43 6.989285e-05 +44 prog_clk[0]:44 6.68228e-05 +45 prog_clk[0]:45 3.799616e-05 +46 prog_clk[0]:46 0.0009213734 +47 prog_clk[0]:47 0.0006724461 +48 prog_clk[0]:48 0.0002992375 +49 prog_clk[0]:49 6.536936e-05 +50 prog_clk[0]:50 6.768187e-05 +51 prog_clk[0]:51 0.0003880178 +52 prog_clk[0]:52 5.831137e-05 +53 prog_clk[0]:53 0.0002506231 +54 prog_clk[0]:54 0.0002506231 +55 prog_clk[0]:55 0.0006180426 +56 prog_clk[0]:56 0.002375234 +57 prog_clk[0]:57 0.001757192 +58 prog_clk[0]:58 5.122882e-05 +59 prog_clk[0]:55 chany_bottom_in[9]:17 8.432921e-05 +60 prog_clk[0]:57 chany_bottom_in[9] 0.0001860019 +61 prog_clk[0]:57 chany_bottom_in[9]:18 1.293434e-05 +62 prog_clk[0]:56 chany_bottom_in[9]:17 1.293434e-05 +63 prog_clk[0]:56 chany_bottom_in[9]:18 0.0002703311 +64 prog_clk[0]:18 mux_tree_tapbuf_size10_0_sram[1]:32 0.0009428824 +65 prog_clk[0]:19 mux_tree_tapbuf_size10_0_sram[1]:31 0.0009428824 + +*RES +0 prog_clk[0] prog_clk[0]:58 9.243333e-05 +1 prog_clk[0]:11 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +2 prog_clk[0]:12 prog_clk[0]:11 0.0045 +3 prog_clk[0]:24 prog_clk[0]:23 0.0045 +4 prog_clk[0]:24 prog_clk[0]:9 0.0001807065 +5 prog_clk[0]:23 prog_clk[0]:22 0.002691964 +6 prog_clk[0]:21 prog_clk[0]:20 0.000984375 +7 prog_clk[0]:22 prog_clk[0]:21 0.0045 +8 prog_clk[0]:22 prog_clk[0]:19 0.00341 +9 prog_clk[0]:20 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +10 prog_clk[0]:41 prog_clk[0]:40 0.004502232 +11 prog_clk[0]:42 prog_clk[0]:41 0.00341 +12 prog_clk[0]:48 prog_clk[0]:47 0.00341 +13 prog_clk[0]:47 prog_clk[0]:46 0.001872558 +14 prog_clk[0]:25 prog_clk[0]:24 0.003616072 +15 prog_clk[0]:26 prog_clk[0]:25 0.0045 +16 prog_clk[0]:50 prog_clk[0]:49 0.0001847826 +17 prog_clk[0]:51 prog_clk[0]:50 0.0045 +18 prog_clk[0]:51 prog_clk[0]:48 0.005109376 +19 prog_clk[0]:49 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +20 prog_clk[0]:45 prog_clk[0]:44 0.0045 +21 prog_clk[0]:46 prog_clk[0]:45 0.00341 +22 prog_clk[0]:46 prog_clk[0]:42 0.000647425 +23 prog_clk[0]:44 prog_clk[0]:43 0.0001440218 +24 prog_clk[0]:43 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +25 prog_clk[0]:39 prog_clk[0]:38 0.0003705357 +26 prog_clk[0]:40 prog_clk[0]:39 0.0045 +27 prog_clk[0]:40 prog_clk[0]:35 0.002084821 +28 prog_clk[0]:36 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +29 prog_clk[0]:29 prog_clk[0]:28 0.0003035715 +30 prog_clk[0]:30 prog_clk[0]:29 0.0045 +31 prog_clk[0]:30 prog_clk[0]:26 0.004776786 +32 prog_clk[0]:27 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +33 prog_clk[0]:9 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +34 prog_clk[0]:15 prog_clk[0]:14 0.0001847826 +35 prog_clk[0]:16 prog_clk[0]:15 0.0045 +36 prog_clk[0]:16 prog_clk[0]:13 0.0004107143 +37 prog_clk[0]:16 prog_clk[0]:10 3.348214e-05 +38 prog_clk[0]:14 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +39 prog_clk[0]:34 prog_clk[0]:33 0.005258929 +40 prog_clk[0]:35 prog_clk[0]:34 0.0045 +41 prog_clk[0]:33 prog_clk[0]:32 0.0045 +42 prog_clk[0]:32 prog_clk[0]:31 0.002691964 +43 prog_clk[0]:52 prog_clk[0]:51 0.000859375 +44 prog_clk[0]:53 prog_clk[0]:52 0.00341 +45 prog_clk[0]:54 prog_clk[0]:53 0.0007163583 +46 prog_clk[0]:55 prog_clk[0]:54 0.00341 +47 prog_clk[0]:58 prog_clk[0]:57 0.00341 +48 prog_clk[0]:57 prog_clk[0]:56 0.007806308 +49 prog_clk[0]:17 prog_clk[0]:16 0.0001634615 +50 prog_clk[0]:18 prog_clk[0]:17 0.00341 +51 prog_clk[0]:19 prog_clk[0]:18 0.00324065 +52 prog_clk[0]:38 prog_clk[0]:37 0.0003035715 +53 prog_clk[0]:37 prog_clk[0]:36 0.0006138394 +54 prog_clk[0]:28 prog_clk[0]:27 0.0006138393 +55 prog_clk[0]:31 prog_clk[0]:30 0.0004107143 +56 prog_clk[0]:13 prog_clk[0]:12 0.002084821 +57 prog_clk[0]:56 prog_clk[0]:55 0.002738141 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.006213788 //LENGTH 52.600 LUMPCC 0.0005705171 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 41.040 95.880 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 34.215 93.500 +*I mux_left_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 53.000 67.320 +*I mux_left_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 45.180 77.815 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 45.180 77.815 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 52.900 67.320 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 52.900 67.365 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 52.900 78.155 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 52.855 78.200 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 45.180 78.200 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 38.685 78.200 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 38.640 78.245 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 34.215 93.500 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 34.500 93.500 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 34.500 93.500 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 34.500 93.840 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 34.508 93.840 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 38.633 93.840 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 38.640 93.840 +*N mux_tree_tapbuf_size10_0_sram[2]:19 *C 39.100 93.840 +*N mux_tree_tapbuf_size10_0_sram[2]:20 *C 39.100 95.835 +*N mux_tree_tapbuf_size10_0_sram[2]:21 *C 39.145 95.880 +*N mux_tree_tapbuf_size10_0_sram[2]:22 *C 41.003 95.880 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_left_ipin_0\/mux_l3_in_1_:S 1e-06 +3 mux_left_ipin_0\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 6.215961e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 3.584114e-05 +6 mux_tree_tapbuf_size10_0_sram[2]:6 0.0005838872 +7 mux_tree_tapbuf_size10_0_sram[2]:7 0.0005838872 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0004750492 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.0009319468 +10 mux_tree_tapbuf_size10_0_sram[2]:10 0.0004240152 +11 mux_tree_tapbuf_size10_0_sram[2]:11 0.0006258738 +12 mux_tree_tapbuf_size10_0_sram[2]:12 4.720467e-05 +13 mux_tree_tapbuf_size10_0_sram[2]:13 5.076652e-05 +14 mux_tree_tapbuf_size10_0_sram[2]:14 4.886469e-05 +15 mux_tree_tapbuf_size10_0_sram[2]:15 5.25025e-05 +16 mux_tree_tapbuf_size10_0_sram[2]:16 0.0002266241 +17 mux_tree_tapbuf_size10_0_sram[2]:17 0.0002266241 +18 mux_tree_tapbuf_size10_0_sram[2]:18 0.0006577387 +19 mux_tree_tapbuf_size10_0_sram[2]:19 0.0001458332 +20 mux_tree_tapbuf_size10_0_sram[2]:20 0.0001139683 +21 mux_tree_tapbuf_size10_0_sram[2]:21 0.0001732416 +22 mux_tree_tapbuf_size10_0_sram[2]:22 0.0001732416 +23 mux_tree_tapbuf_size10_0_sram[2]:20 chany_bottom_in[3]:11 1.19335e-05 +24 mux_tree_tapbuf_size10_0_sram[2]:18 chany_bottom_in[3]:11 0.0002171187 +25 mux_tree_tapbuf_size10_0_sram[2]:11 chany_bottom_in[3]:12 0.0002171187 +26 mux_tree_tapbuf_size10_0_sram[2]:19 chany_bottom_in[3]:12 1.19335e-05 +27 mux_tree_tapbuf_size10_0_sram[2]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.620639e-05 +28 mux_tree_tapbuf_size10_0_sram[2]:9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.620639e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:22 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:22 mux_tree_tapbuf_size10_0_sram[2]:21 0.001658482 +2 mux_tree_tapbuf_size10_0_sram[2]:21 mux_tree_tapbuf_size10_0_sram[2]:20 0.0045 +3 mux_tree_tapbuf_size10_0_sram[2]:20 mux_tree_tapbuf_size10_0_sram[2]:19 0.00178125 +4 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:17 0.00341 +5 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:11 0.01392411 +6 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.00064625 +7 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.0001634615 +8 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.00341 +9 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.0001548913 +10 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +11 mux_tree_tapbuf_size10_0_sram[2]:12 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.0045 +13 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.009633929 +14 mux_tree_tapbuf_size10_0_sram[2]:5 mux_left_ipin_0\/mux_l3_in_1_:S 0.152 +15 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.0045 +16 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.005799107 +17 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.0045 +18 mux_tree_tapbuf_size10_0_sram[2]:4 mux_left_ipin_0\/mux_l3_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.006852678 +20 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:4 0.00034375 +21 mux_tree_tapbuf_size10_0_sram[2]:19 mux_tree_tapbuf_size10_0_sram[2]:18 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.003818235 //LENGTH 27.460 LUMPCC 0.0004386269 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 25.400 76.840 +*I mux_right_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 19.880 74.510 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 7.535 71.740 +*I mux_right_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 11.600 74.120 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 11.638 74.120 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 7.573 71.740 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 14.215 71.740 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 14.260 71.785 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 14.260 74.075 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 14.260 74.120 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 18.860 74.120 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 18.860 74.460 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 19.880 74.510 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 20.655 74.460 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 20.700 74.505 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 20.700 76.795 +*N mux_tree_tapbuf_size10_1_sram[2]:16 *C 20.745 76.840 +*N mux_tree_tapbuf_size10_1_sram[2]:17 *C 25.363 76.840 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:S 1e-06 +2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 0.0002001886 +5 mux_tree_tapbuf_size10_1_sram[2]:5 0.0004396596 +6 mux_tree_tapbuf_size10_1_sram[2]:6 0.0004396596 +7 mux_tree_tapbuf_size10_1_sram[2]:7 0.0001347504 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0001347504 +9 mux_tree_tapbuf_size10_1_sram[2]:9 0.0005659783 +10 mux_tree_tapbuf_size10_1_sram[2]:10 0.0003557981 +11 mux_tree_tapbuf_size10_1_sram[2]:11 9.578725e-05 +12 mux_tree_tapbuf_size10_1_sram[2]:12 0.0001750588 +13 mux_tree_tapbuf_size10_1_sram[2]:13 7.635247e-05 +14 mux_tree_tapbuf_size10_1_sram[2]:14 0.0001617898 +15 mux_tree_tapbuf_size10_1_sram[2]:15 0.0001617898 +16 mux_tree_tapbuf_size10_1_sram[2]:16 0.0002170225 +17 mux_tree_tapbuf_size10_1_sram[2]:17 0.0002170225 +18 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[1]:20 0.0001860114 +19 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[1]:19 0.0001860114 +20 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[1]:19 1.149274e-08 +21 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[1]:20 1.38679e-07 +22 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[1]:14 1.652299e-05 +23 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[1]:15 1.651855e-05 +24 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[1]:18 1.149274e-08 +25 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[1]:19 2.490093e-07 +26 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[1]:15 1.652299e-05 +27 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[1]:14 1.651855e-05 +28 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[1]:18 1.103303e-07 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:16 0.004122768 +2 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[2]:15 0.0045 +3 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:14 0.002044643 +4 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:12 0.0006919643 +5 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.0045 +6 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:4 0.002341518 +8 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.002044643 +9 mux_tree_tapbuf_size10_1_sram[2]:6 mux_tree_tapbuf_size10_1_sram[2]:5 0.005930804 +10 mux_tree_tapbuf_size10_1_sram[2]:7 mux_tree_tapbuf_size10_1_sram[2]:6 0.0045 +11 mux_tree_tapbuf_size10_1_sram[2]:5 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_1_sram[2]:12 mux_right_ipin_0\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.0009107143 +14 mux_tree_tapbuf_size10_1_sram[2]:4 mux_right_ipin_0\/mux_l3_in_1_:S 0.152 +15 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[2]:9 0.004107143 +16 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:10 0.0003035715 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001971177 //LENGTH 17.135 LUMPCC 0.000610179 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_0_:X O *L 0 *C 68.255 79.900 +*I mux_left_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 67.160 90.780 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 67.160 90.780 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 67.160 91.460 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 65.825 91.460 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 65.780 91.415 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 65.780 79.945 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 65.825 79.900 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 68.218 79.900 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.332762e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001406698 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.562539e-05 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004141103 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004141103 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001105774 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001105774 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[0]:5 0.0001022356 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[0]:10 0.0001022356 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[5]:14 0.0001030462 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[5]:13 0.0001030462 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.425603e-05 +14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.555177e-05 +15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.425603e-05 +16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.555177e-05 + +*RES +0 mux_left_ipin_0\/mux_l1_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.002136161 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.01024107 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001191964 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_ipin_0\/mux_l2_in_0_:A1 0.152 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006071428 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.003806896 //LENGTH 33.100 LUMPCC 0.0006248488 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_0_:X O *L 0 *C 65.495 90.440 +*I mux_left_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 45.905 77.860 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 45.943 77.860 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 46.875 77.860 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 46.920 77.905 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 46.920 90.395 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 46.965 90.440 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 65.458 90.440 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001018493 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001018493 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000427641 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000427641 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001060533 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.001060533 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[5]:12 0.0001080786 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[5] 0.0001080786 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[11]:11 9.943192e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[11] 9.943192e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_0_sram[1]:23 2.084441e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_0_sram[1]:25 8.406951e-05 +14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_0_sram[1]:24 8.406951e-05 +15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_0_sram[1]:26 2.084441e-05 + +*RES +0 mux_left_ipin_0\/mux_l2_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.01115179 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.01651116 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0008751333 //LENGTH 6.525 LUMPCC 0.0001933214 DR + +*CONN +*I mux_left_ipin_0\/mux_l3_in_0_:X O *L 0 *C 44.335 76.840 +*I mux_left_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 45.540 72.420 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 45.540 72.435 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 45.540 72.760 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 45.540 72.805 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 45.540 76.795 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 45.495 76.840 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 44.373 76.840 + +*CAP +0 mux_left_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.716568e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.151895e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001766607 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001766607 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001089029 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001089029 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[5]:19 4.378192e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_bottom_in[5]:20 4.378192e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_top_in[5]:11 5.287876e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_top_in[5]:10 5.287876e-05 + +*RES +0 mux_left_ipin_0\/mux_l3_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001002232 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0035625 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001766304 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_ipin_0\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET optlc_net_145 0.001214283 //LENGTH 11.830 LUMPCC 0.0001951842 DR + +*CONN +*I optlc_145:HI O *L 0 *C 16.560 64.260 +*I mux_right_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 16.850 75.480 +*N optlc_net_145:2 *C 16.850 75.480 +*N optlc_net_145:3 *C 16.560 75.480 +*N optlc_net_145:4 *C 16.560 75.435 +*N optlc_net_145:5 *C 16.560 64.305 +*N optlc_net_145:6 *C 16.560 64.260 + +*CAP +0 optlc_145:HI 1e-06 +1 mux_right_ipin_0\/mux_l2_in_3_:A0 1e-06 +2 optlc_net_145:2 5.066306e-05 +3 optlc_net_145:3 5.486575e-05 +4 optlc_net_145:4 0.0004423448 +5 optlc_net_145:5 0.0004423448 +6 optlc_net_145:6 2.688063e-05 +7 optlc_net_145:2 chany_top_in[17]:7 5.286673e-07 +8 optlc_net_145:3 chany_top_in[17]:6 5.286673e-07 +9 optlc_net_145:4 chany_top_in[17]:8 9.022513e-05 +10 optlc_net_145:4 chany_top_in[17]:9 6.838299e-06 +11 optlc_net_145:5 chany_top_in[17]:5 9.022513e-05 +12 optlc_net_145:5 chany_top_in[17]:8 6.838299e-06 + +*RES +0 optlc_145:HI optlc_net_145:6 0.152 +1 optlc_net_145:2 mux_right_ipin_0\/mux_l2_in_3_:A0 0.152 +2 optlc_net_145:3 optlc_net_145:2 0.0001576087 +3 optlc_net_145:4 optlc_net_145:3 0.0045 +4 optlc_net_145:6 optlc_net_145:5 0.0045 +5 optlc_net_145:5 optlc_net_145:4 0.009937501 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001967798 //LENGTH 17.395 LUMPCC 0.0002996628 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_2_:X O *L 0 *C 31.915 74.800 +*I mux_right_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 21.525 69.020 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 21.525 69.020 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 21.620 69.360 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 28.015 69.360 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 28.060 69.405 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 28.060 74.415 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 28.105 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 31.280 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 31.280 74.800 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 31.878 74.800 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.772421e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003044097 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002759652 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002333754 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002333754 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001876385 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002142321 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 9.300412e-05 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:10 6.641054e-05 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[11]:8 0.0001100394 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[11]:7 3.979199e-05 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[11]:6 3.979199e-05 +14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[11]:3 0.0001100394 + +*RES +0 mux_right_ipin_0\/mux_l1_in_2_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_0\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.005709821 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.004473215 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0005334822 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.002834822 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0003035715 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002288335 //LENGTH 21.080 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_2_:X O *L 0 *C 26.395 79.900 +*I mux_right_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 12.325 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 12.363 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 13.295 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 13.340 74.505 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 13.340 77.135 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 13.385 77.180 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 14.675 77.180 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 14.720 77.225 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 14.720 79.855 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 14.765 79.900 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 26.358 79.900 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.47494e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.47494e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001677287 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001677287 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.961428e-05 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.961428e-05 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001435826 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001435826 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0006474928 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0006474928 + +*RES +0 mux_right_ipin_0\/mux_l2_in_2_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008325892 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348215 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001151786 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002348214 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.01035045 + +*END + +*D_NET ropt_net_177 0.0006569611 //LENGTH 4.880 LUMPCC 0.0001937842 DR + +*CONN +*I FTB_1__0:X O *L 0 *C 62.100 99.620 +*I ropt_mt_inst_781:A I *L 0.001766 *C 66.240 99.280 +*N ropt_net_177:2 *C 66.240 99.280 +*N ropt_net_177:3 *C 66.240 99.620 +*N ropt_net_177:4 *C 62.138 99.620 + +*CAP +0 FTB_1__0:X 1e-06 +1 ropt_mt_inst_781:A 1e-06 +2 ropt_net_177:2 5.318569e-05 +3 ropt_net_177:3 0.0002171263 +4 ropt_net_177:4 0.000190865 +5 ropt_net_177:4 chany_bottom_in[0]:7 9.689208e-05 +6 ropt_net_177:3 chany_bottom_in[0]:6 9.689208e-05 + +*RES +0 FTB_1__0:X ropt_net_177:4 0.152 +1 ropt_net_177:2 ropt_mt_inst_781:A 0.152 +2 ropt_net_177:4 ropt_net_177:3 0.003662947 +3 ropt_net_177:3 ropt_net_177:2 0.0003035715 + +*END + +*D_NET ropt_net_193 0.001725453 //LENGTH 11.480 LUMPCC 0.0005130648 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 48.930 102.340 +*I ropt_mt_inst_796:A I *L 0.001766 *C 43.240 104.720 +*N ropt_net_193:2 *C 43.203 104.720 +*N ropt_net_193:3 *C 42.365 104.720 +*N ropt_net_193:4 *C 42.320 104.675 +*N ropt_net_193:5 *C 42.320 104.085 +*N ropt_net_193:6 *C 42.365 104.040 +*N ropt_net_193:7 *C 47.795 104.040 +*N ropt_net_193:8 *C 47.840 103.995 +*N ropt_net_193:9 *C 47.840 102.385 +*N ropt_net_193:10 *C 47.885 102.340 +*N ropt_net_193:11 *C 48.893 102.340 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_193:2 5.361229e-05 +3 ropt_net_193:3 5.361229e-05 +4 ropt_net_193:4 7.190176e-05 +5 ropt_net_193:5 7.190176e-05 +6 ropt_net_193:6 0.000287595 +7 ropt_net_193:7 0.000287595 +8 ropt_net_193:8 0.0001334759 +9 ropt_net_193:9 0.0001334759 +10 ropt_net_193:10 5.860939e-05 +11 ropt_net_193:11 5.860939e-05 +12 ropt_net_193:2 chany_bottom_in[18]:8 4.355253e-05 +13 ropt_net_193:3 chany_bottom_in[18]:7 4.355253e-05 +14 ropt_net_193:6 chany_bottom_in[18]:7 1.959618e-06 +15 ropt_net_193:6 chany_bottom_in[18]:9 0.0001552417 +16 ropt_net_193:7 chany_bottom_in[18]:8 1.959618e-06 +17 ropt_net_193:7 chany_bottom_in[18]:10 0.0001552417 +18 ropt_net_193:8 ropt_net_204:7 5.750457e-06 +19 ropt_net_193:10 ropt_net_204:6 5.002812e-05 +20 ropt_net_193:9 ropt_net_204:8 5.750457e-06 +21 ropt_net_193:11 ropt_net_204:5 5.002812e-05 + +*RES +0 ropt_mt_inst_752:X ropt_net_193:11 0.152 +1 ropt_net_193:2 ropt_mt_inst_796:A 0.152 +2 ropt_net_193:3 ropt_net_193:2 0.0007477679 +3 ropt_net_193:4 ropt_net_193:3 0.0045 +4 ropt_net_193:6 ropt_net_193:5 0.0045 +5 ropt_net_193:5 ropt_net_193:4 0.0005267857 +6 ropt_net_193:7 ropt_net_193:6 0.004848215 +7 ropt_net_193:8 ropt_net_193:7 0.0045 +8 ropt_net_193:10 ropt_net_193:9 0.0045 +9 ropt_net_193:9 ropt_net_193:8 0.0014375 +10 ropt_net_193:11 ropt_net_193:10 0.0008995536 + +*END + +*D_NET chany_top_out[18] 0.001080601 //LENGTH 9.165 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 27.600 102.680 +*P chany_top_out[18] O *L 0.7423 *C 26.680 107.475 +*N chany_top_out[18]:2 *C 28.060 107.440 +*N chany_top_out[18]:3 *C 28.060 102.385 +*N chany_top_out[18]:4 *C 28.105 102.340 +*N chany_top_out[18]:5 *C 28.520 102.340 +*N chany_top_out[18]:6 *C 28.520 102.680 +*N chany_top_out[18]:7 *C 27.638 102.680 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 chany_top_out[18] 8.69122e-05 +2 chany_top_out[18]:2 0.000404357 +3 chany_top_out[18]:3 0.0003174448 +4 chany_top_out[18]:4 3.056626e-05 +5 chany_top_out[18]:5 5.674698e-05 +6 chany_top_out[18]:6 0.0001048771 +7 chany_top_out[18]:7 7.869639e-05 + +*RES +0 ropt_mt_inst_790:X chany_top_out[18]:7 0.152 +1 chany_top_out[18]:7 chany_top_out[18]:6 0.0007879465 +2 chany_top_out[18]:4 chany_top_out[18]:3 0.0045 +3 chany_top_out[18]:3 chany_top_out[18]:2 0.004513393 +4 chany_top_out[18]:6 chany_top_out[18]:5 0.0003035715 +5 chany_top_out[18]:5 chany_top_out[18]:4 0.0003705357 +6 chany_top_out[18]:2 chany_top_out[18] 0.001232143 + +*END + +*D_NET ropt_net_187 0.001315546 //LENGTH 9.505 LUMPCC 0.0002189025 DR + +*CONN +*I ropt_mt_inst_756:X O *L 0 *C 33.245 104.040 +*I ropt_mt_inst_790:A I *L 0.001767 *C 26.680 102.000 +*N ropt_net_187:2 *C 26.718 102.000 +*N ropt_net_187:3 *C 27.095 102.000 +*N ropt_net_187:4 *C 27.140 102.045 +*N ropt_net_187:5 *C 27.140 103.995 +*N ropt_net_187:6 *C 27.185 104.040 +*N ropt_net_187:7 *C 33.245 104.040 + +*CAP +0 ropt_mt_inst_756:X 1e-06 +1 ropt_mt_inst_790:A 1e-06 +2 ropt_net_187:2 5.899711e-05 +3 ropt_net_187:3 5.899711e-05 +4 ropt_net_187:4 8.494454e-05 +5 ropt_net_187:5 8.494454e-05 +6 ropt_net_187:6 0.0003819076 +7 ropt_net_187:7 0.0004248527 +8 ropt_net_187:6 chany_bottom_in[3]:7 4.698801e-05 +9 ropt_net_187:7 chany_bottom_in[3]:8 4.698801e-05 +10 ropt_net_187:4 chany_bottom_in[14]:8 6.246322e-05 +11 ropt_net_187:5 chany_bottom_in[14]:7 6.246322e-05 + +*RES +0 ropt_mt_inst_756:X ropt_net_187:7 0.152 +1 ropt_net_187:2 ropt_mt_inst_790:A 0.152 +2 ropt_net_187:3 ropt_net_187:2 0.0003370536 +3 ropt_net_187:4 ropt_net_187:3 0.0045 +4 ropt_net_187:6 ropt_net_187:5 0.0045 +5 ropt_net_187:5 ropt_net_187:4 0.001741071 +6 ropt_net_187:7 ropt_net_187:6 0.005410715 + +*END + +*D_NET chany_top_out[5] 0.0006867452 //LENGTH 5.025 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 51.670 105.400 +*P chany_top_out[5] O *L 0.7423 *C 49.220 107.510 +*N chany_top_out[5]:2 *C 49.220 105.445 +*N chany_top_out[5]:3 *C 49.265 105.400 +*N chany_top_out[5]:4 *C 51.633 105.400 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 chany_top_out[5] 0.0001484791 +2 chany_top_out[5]:2 0.0001484791 +3 chany_top_out[5]:3 0.0001943935 +4 chany_top_out[5]:4 0.0001943935 + +*RES +0 ropt_mt_inst_792:X chany_top_out[5]:4 0.152 +1 chany_top_out[5]:4 chany_top_out[5]:3 0.00211384 +2 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +3 chany_top_out[5]:2 chany_top_out[5] 0.00184375 + +*END + +*D_NET ropt_net_206 0.0007124476 //LENGTH 6.635 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 81.580 82.280 +*I ropt_mt_inst_809:A I *L 0.001767 *C 77.740 80.240 +*N ropt_net_206:2 *C 77.778 80.240 +*N ropt_net_206:3 *C 81.375 80.240 +*N ropt_net_206:4 *C 81.420 80.285 +*N ropt_net_206:5 *C 81.420 82.235 +*N ropt_net_206:6 *C 81.420 82.280 +*N ropt_net_206:7 *C 81.580 82.280 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 ropt_mt_inst_809:A 1e-06 +2 ropt_net_206:2 0.0002001886 +3 ropt_net_206:3 0.0002001886 +4 ropt_net_206:4 0.000100359 +5 ropt_net_206:5 0.000100359 +6 ropt_net_206:6 5.298425e-05 +7 ropt_net_206:7 5.636824e-05 + +*RES +0 ropt_mt_inst_758:X ropt_net_206:7 0.152 +1 ropt_net_206:2 ropt_mt_inst_809:A 0.152 +2 ropt_net_206:3 ropt_net_206:2 0.003212054 +3 ropt_net_206:4 ropt_net_206:3 0.0045 +4 ropt_net_206:6 ropt_net_206:5 0.0045 +5 ropt_net_206:5 ropt_net_206:4 0.001741071 +6 ropt_net_206:7 ropt_net_206:6 8.695653e-05 + +*END + +*D_NET ropt_net_183 0.001191022 //LENGTH 9.410 LUMPCC 9.306637e-05 DR + +*CONN +*I FTB_18__17:X O *L 0 *C 36.340 98.600 +*I ropt_mt_inst_787:A I *L 0.001766 *C 29.900 96.560 +*N ropt_net_183:2 *C 29.938 96.560 +*N ropt_net_183:3 *C 32.155 96.560 +*N ropt_net_183:4 *C 32.200 96.605 +*N ropt_net_183:5 *C 32.200 98.555 +*N ropt_net_183:6 *C 32.245 98.600 +*N ropt_net_183:7 *C 36.303 98.600 + +*CAP +0 FTB_18__17:X 1e-06 +1 ropt_mt_inst_787:A 1e-06 +2 ropt_net_183:2 0.0001576706 +3 ropt_net_183:3 0.0001576706 +4 ropt_net_183:4 0.0001286957 +5 ropt_net_183:5 0.0001286957 +6 ropt_net_183:6 0.0002616117 +7 ropt_net_183:7 0.0002616117 +8 ropt_net_183:4 chany_top_in[1]:27 6.514995e-07 +9 ropt_net_183:6 chany_top_in[1]:30 4.588169e-05 +10 ropt_net_183:5 chany_top_in[1]:28 6.514995e-07 +11 ropt_net_183:7 chany_top_in[1]:29 4.588169e-05 + +*RES +0 FTB_18__17:X ropt_net_183:7 0.152 +1 ropt_net_183:2 ropt_mt_inst_787:A 0.152 +2 ropt_net_183:3 ropt_net_183:2 0.001979911 +3 ropt_net_183:4 ropt_net_183:3 0.0045 +4 ropt_net_183:6 ropt_net_183:5 0.0045 +5 ropt_net_183:5 ropt_net_183:4 0.001741072 +6 ropt_net_183:7 ropt_net_183:6 0.003622768 + +*END + +*D_NET ropt_net_215 0.0009576268 //LENGTH 7.570 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 54.740 4.760 +*I ropt_mt_inst_818:A I *L 0.001766 *C 50.140 6.800 +*N ropt_net_215:2 *C 50.178 6.800 +*N ropt_net_215:3 *C 51.475 6.800 +*N ropt_net_215:4 *C 51.520 6.755 +*N ropt_net_215:5 *C 51.520 4.805 +*N ropt_net_215:6 *C 51.565 4.760 +*N ropt_net_215:7 *C 54.703 4.760 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 ropt_mt_inst_818:A 1e-06 +2 ropt_net_215:2 0.000104392 +3 ropt_net_215:3 0.000104392 +4 ropt_net_215:4 0.0001288547 +5 ropt_net_215:5 0.0001288547 +6 ropt_net_215:6 0.0002445667 +7 ropt_net_215:7 0.0002445667 + +*RES +0 ropt_mt_inst_762:X ropt_net_215:7 0.152 +1 ropt_net_215:7 ropt_net_215:6 0.002801339 +2 ropt_net_215:6 ropt_net_215:5 0.0045 +3 ropt_net_215:5 ropt_net_215:4 0.001741072 +4 ropt_net_215:3 ropt_net_215:2 0.001158482 +5 ropt_net_215:4 ropt_net_215:3 0.0045 +6 ropt_net_215:2 ropt_mt_inst_818:A 0.152 + +*END + +*D_NET ropt_net_218 0.0008463713 //LENGTH 6.580 LUMPCC 0.0004476405 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 21.160 104.040 +*I ropt_mt_inst_821:A I *L 0.001766 *C 20.240 99.280 +*N ropt_net_218:2 *C 20.240 99.295 +*N ropt_net_218:3 *C 20.240 99.620 +*N ropt_net_218:4 *C 20.240 99.665 +*N ropt_net_218:5 *C 20.240 103.995 +*N ropt_net_218:6 *C 20.285 104.040 +*N ropt_net_218:7 *C 21.123 104.040 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 ropt_mt_inst_821:A 1e-06 +2 ropt_net_218:2 3.849597e-05 +3 ropt_net_218:3 7.421523e-05 +4 ropt_net_218:4 8.852618e-05 +5 ropt_net_218:5 8.852618e-05 +6 ropt_net_218:6 5.348365e-05 +7 ropt_net_218:7 5.348365e-05 +8 ropt_net_218:7 chany_bottom_in[3]:8 6.965702e-06 +9 ropt_net_218:6 chany_bottom_in[3]:7 6.965702e-06 +10 ropt_net_218:5 chany_bottom_in[3]:6 0.000130981 +11 ropt_net_218:4 chany_bottom_in[3]:5 0.000130981 +12 ropt_net_218:7 chany_bottom_in[9]:3 1.847492e-05 +13 ropt_net_218:6 chany_bottom_in[9]:2 1.847492e-05 +14 ropt_net_218:5 chany_bottom_in[9]:4 6.739856e-05 +15 ropt_net_218:4 chany_bottom_in[9]:5 6.739856e-05 + +*RES +0 ropt_mt_inst_765:X ropt_net_218:7 0.152 +1 ropt_net_218:7 ropt_net_218:6 0.0007477679 +2 ropt_net_218:6 ropt_net_218:5 0.0045 +3 ropt_net_218:5 ropt_net_218:4 0.003866072 +4 ropt_net_218:3 ropt_net_218:2 0.0001766304 +5 ropt_net_218:4 ropt_net_218:3 0.0045 +6 ropt_net_218:2 ropt_mt_inst_821:A 0.152 + +*END + +*D_NET ropt_net_197 0.00073815 //LENGTH 5.665 LUMPCC 7.513784e-05 DR + +*CONN +*I ropt_mt_inst_767:X O *L 0 *C 39.265 3.740 +*I ropt_mt_inst_800:A I *L 0.001767 *C 40.940 6.800 +*N ropt_net_197:2 *C 40.903 6.800 +*N ropt_net_197:3 *C 40.525 6.800 +*N ropt_net_197:4 *C 40.480 6.755 +*N ropt_net_197:5 *C 40.480 3.785 +*N ropt_net_197:6 *C 40.435 3.740 +*N ropt_net_197:7 *C 39.303 3.740 + +*CAP +0 ropt_mt_inst_767:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_197:2 4.774242e-05 +3 ropt_net_197:3 4.774242e-05 +4 ropt_net_197:4 0.000171062 +5 ropt_net_197:5 0.000171062 +6 ropt_net_197:6 0.0001117016 +7 ropt_net_197:7 0.0001117016 +8 ropt_net_197:5 ropt_net_214:5 2.5958e-05 +9 ropt_net_197:3 ropt_net_214:7 1.161091e-05 +10 ropt_net_197:4 ropt_net_214:4 2.5958e-05 +11 ropt_net_197:2 ropt_net_214:6 1.161091e-05 + +*RES +0 ropt_mt_inst_767:X ropt_net_197:7 0.152 +1 ropt_net_197:7 ropt_net_197:6 0.001011161 +2 ropt_net_197:6 ropt_net_197:5 0.0045 +3 ropt_net_197:5 ropt_net_197:4 0.002651786 +4 ropt_net_197:3 ropt_net_197:2 0.0003370536 +5 ropt_net_197:4 ropt_net_197:3 0.0045 +6 ropt_net_197:2 ropt_mt_inst_800:A 0.152 + +*END + +*D_NET ropt_net_196 0.0009818997 //LENGTH 8.975 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 33.315 9.180 +*I ropt_mt_inst_799:A I *L 0.001767 *C 29.440 6.800 +*N ropt_net_196:2 *C 29.478 6.800 +*N ropt_net_196:3 *C 32.155 6.800 +*N ropt_net_196:4 *C 32.200 6.755 +*N ropt_net_196:5 *C 32.200 6.165 +*N ropt_net_196:6 *C 32.245 6.120 +*N ropt_net_196:7 *C 33.075 6.120 +*N ropt_net_196:8 *C 33.120 6.165 +*N ropt_net_196:9 *C 33.120 9.135 +*N ropt_net_196:10 *C 33.120 9.180 +*N ropt_net_196:11 *C 33.315 9.180 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_196:2 0.000165918 +3 ropt_net_196:3 0.000165918 +4 ropt_net_196:4 3.878335e-05 +5 ropt_net_196:5 3.878335e-05 +6 ropt_net_196:6 6.995934e-05 +7 ropt_net_196:7 6.995934e-05 +8 ropt_net_196:8 0.0001620583 +9 ropt_net_196:9 0.0001620583 +10 ropt_net_196:10 5.450921e-05 +11 ropt_net_196:11 5.195243e-05 + +*RES +0 ropt_mt_inst_770:X ropt_net_196:11 0.152 +1 ropt_net_196:11 ropt_net_196:10 0.0001059783 +2 ropt_net_196:10 ropt_net_196:9 0.0045 +3 ropt_net_196:9 ropt_net_196:8 0.002651786 +4 ropt_net_196:7 ropt_net_196:6 0.0007410715 +5 ropt_net_196:8 ropt_net_196:7 0.0045 +6 ropt_net_196:6 ropt_net_196:5 0.0045 +7 ropt_net_196:5 ropt_net_196:4 0.0005267857 +8 ropt_net_196:3 ropt_net_196:2 0.002390625 +9 ropt_net_196:4 ropt_net_196:3 0.0045 +10 ropt_net_196:2 ropt_mt_inst_799:A 0.152 + +*END + +*D_NET ropt_net_195 0.001743905 //LENGTH 15.265 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 79.315 8.840 +*I ropt_mt_inst_798:A I *L 0.001766 *C 72.220 4.080 +*N ropt_net_195:2 *C 72.220 4.080 +*N ropt_net_195:3 *C 72.220 4.035 +*N ropt_net_195:4 *C 72.220 3.458 +*N ropt_net_195:5 *C 72.220 3.400 +*N ropt_net_195:6 *C 75.892 3.400 +*N ropt_net_195:7 *C 75.900 3.458 +*N ropt_net_195:8 *C 75.900 6.075 +*N ropt_net_195:9 *C 75.945 6.120 +*N ropt_net_195:10 *C 77.235 6.120 +*N ropt_net_195:11 *C 77.280 6.165 +*N ropt_net_195:12 *C 77.280 8.795 +*N ropt_net_195:13 *C 77.325 8.840 +*N ropt_net_195:14 *C 79.278 8.840 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 ropt_mt_inst_798:A 1e-06 +2 ropt_net_195:2 3.144726e-05 +3 ropt_net_195:3 5.472633e-05 +4 ropt_net_195:4 5.472633e-05 +5 ropt_net_195:5 0.000251352 +6 ropt_net_195:6 0.000251352 +7 ropt_net_195:7 0.0001530826 +8 ropt_net_195:8 0.0001530826 +9 ropt_net_195:9 0.0001124906 +10 ropt_net_195:10 0.0001124906 +11 ropt_net_195:11 0.0001466549 +12 ropt_net_195:12 0.0001466549 +13 ropt_net_195:13 0.0001369225 +14 ropt_net_195:14 0.0001369225 + +*RES +0 ropt_mt_inst_774:X ropt_net_195:14 0.152 +1 ropt_net_195:14 ropt_net_195:13 0.001743304 +2 ropt_net_195:13 ropt_net_195:12 0.0045 +3 ropt_net_195:12 ropt_net_195:11 0.002348214 +4 ropt_net_195:10 ropt_net_195:9 0.001151786 +5 ropt_net_195:11 ropt_net_195:10 0.0045 +6 ropt_net_195:9 ropt_net_195:8 0.0045 +7 ropt_net_195:8 ropt_net_195:7 0.002337054 +8 ropt_net_195:7 ropt_net_195:6 0.00341 +9 ropt_net_195:6 ropt_net_195:5 0.0005753583 +10 ropt_net_195:4 ropt_net_195:3 0.0005156251 +11 ropt_net_195:5 ropt_net_195:4 0.00341 +12 ropt_net_195:2 ropt_mt_inst_798:A 0.152 +13 ropt_net_195:3 ropt_net_195:2 0.0045 + +*END + +*D_NET ropt_net_199 0.0007224249 //LENGTH 4.335 LUMPCC 0.0003686792 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 25.955 102.680 +*I ropt_mt_inst_802:A I *L 0.001767 *C 24.840 104.720 +*N ropt_net_199:2 *C 24.878 104.720 +*N ropt_net_199:3 *C 26.175 104.720 +*N ropt_net_199:4 *C 26.220 104.675 +*N ropt_net_199:5 *C 26.220 102.725 +*N ropt_net_199:6 *C 26.220 102.680 +*N ropt_net_199:7 *C 25.955 102.680 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 ropt_mt_inst_802:A 1e-06 +2 ropt_net_199:2 7.088351e-05 +3 ropt_net_199:3 7.088351e-05 +4 ropt_net_199:4 4.734736e-05 +5 ropt_net_199:5 4.734736e-05 +6 ropt_net_199:6 5.713424e-05 +7 ropt_net_199:7 5.814964e-05 +8 ropt_net_199:2 chany_bottom_in[3]:7 6.008434e-05 +9 ropt_net_199:3 chany_bottom_in[3]:8 6.008434e-05 +10 ropt_net_199:4 chany_bottom_in[14]:7 6.163606e-05 +11 ropt_net_199:5 chany_bottom_in[14]:8 6.163606e-05 +12 ropt_net_199:4 chany_top_in[9] 6.261922e-05 +13 ropt_net_199:5 chany_top_in[9]:17 6.261922e-05 + +*RES +0 ropt_mt_inst_777:X ropt_net_199:7 0.152 +1 ropt_net_199:2 ropt_mt_inst_802:A 0.152 +2 ropt_net_199:3 ropt_net_199:2 0.001158482 +3 ropt_net_199:4 ropt_net_199:3 0.0045 +4 ropt_net_199:6 ropt_net_199:5 0.0045 +5 ropt_net_199:5 ropt_net_199:4 0.001741071 +6 ropt_net_199:7 ropt_net_199:6 0.0001440218 + +*END + +*D_NET chany_top_out[11] 0.00112256 //LENGTH 8.155 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 35.420 104.720 +*P chany_top_out[11] O *L 0.7423 *C 30.820 107.475 +*N chany_top_out[11]:2 *C 30.820 107.145 +*N chany_top_out[11]:3 *C 30.865 107.100 +*N chany_top_out[11]:4 *C 35.375 107.100 +*N chany_top_out[11]:5 *C 35.420 107.055 +*N chany_top_out[11]:6 *C 35.420 104.765 +*N chany_top_out[11]:7 *C 35.420 104.720 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 chany_top_out[11] 3.794546e-05 +2 chany_top_out[11]:2 3.794546e-05 +3 chany_top_out[11]:3 0.000353421 +4 chany_top_out[11]:4 0.000353421 +5 chany_top_out[11]:5 0.0001539822 +6 chany_top_out[11]:6 0.0001539822 +7 chany_top_out[11]:7 3.08631e-05 + +*RES +0 ropt_mt_inst_795:X chany_top_out[11]:7 0.152 +1 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +2 chany_top_out[11]:2 chany_top_out[11] 0.0002946429 +3 chany_top_out[11]:4 chany_top_out[11]:3 0.004026786 +4 chany_top_out[11]:5 chany_top_out[11]:4 0.0045 +5 chany_top_out[11]:7 chany_top_out[11]:6 0.0045 +6 chany_top_out[11]:6 chany_top_out[11]:5 0.002044643 + +*END + +*D_NET ropt_net_205 0.001048827 //LENGTH 8.225 LUMPCC 0.0002191265 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 19.515 104.040 +*I ropt_mt_inst_808:A I *L 0.001767 *C 14.260 102.000 +*N ropt_net_205:2 *C 14.298 102.000 +*N ropt_net_205:3 *C 15.135 102.000 +*N ropt_net_205:4 *C 15.180 102.045 +*N ropt_net_205:5 *C 15.180 103.995 +*N ropt_net_205:6 *C 15.225 104.040 +*N ropt_net_205:7 *C 19.478 104.040 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_205:2 4.421352e-05 +3 ropt_net_205:3 4.421352e-05 +4 ropt_net_205:4 7.732165e-05 +5 ropt_net_205:5 7.732165e-05 +6 ropt_net_205:6 0.0002923149 +7 ropt_net_205:7 0.0002923149 +8 ropt_net_205:3 ropt_net_180:5 4.527909e-05 +9 ropt_net_205:2 ropt_net_180:4 4.527909e-05 +10 ropt_net_205:5 ropt_net_178:3 6.428415e-05 +11 ropt_net_205:4 ropt_net_178:4 6.428415e-05 + +*RES +0 ropt_mt_inst_782:X ropt_net_205:7 0.152 +1 ropt_net_205:7 ropt_net_205:6 0.003796875 +2 ropt_net_205:6 ropt_net_205:5 0.0045 +3 ropt_net_205:5 ropt_net_205:4 0.001741072 +4 ropt_net_205:3 ropt_net_205:2 0.0007477679 +5 ropt_net_205:4 ropt_net_205:3 0.0045 +6 ropt_net_205:2 ropt_mt_inst_808:A 0.152 + +*END + +*D_NET ropt_net_173 0.001703958 //LENGTH 13.950 LUMPCC 0.0003258738 DR + +*CONN +*I BUFT_RR_48:X O *L 0 *C 18.860 95.880 +*I ropt_mt_inst_777:A I *L 0.001766 *C 22.080 102.000 +*N ropt_net_173:2 *C 22.117 102.000 +*N ropt_net_173:3 *C 23.875 102.000 +*N ropt_net_173:4 *C 23.920 101.955 +*N ropt_net_173:5 *C 23.920 95.925 +*N ropt_net_173:6 *C 23.875 95.880 +*N ropt_net_173:7 *C 18.898 95.880 + +*CAP +0 BUFT_RR_48:X 1e-06 +1 ropt_mt_inst_777:A 1e-06 +2 ropt_net_173:2 8.083793e-05 +3 ropt_net_173:3 8.083793e-05 +4 ropt_net_173:4 0.0002564973 +5 ropt_net_173:5 0.0002564973 +6 ropt_net_173:6 0.0003507069 +7 ropt_net_173:7 0.0003507069 +8 ropt_net_173:5 chany_bottom_in[19]:7 8.610429e-05 +9 ropt_net_173:4 chany_bottom_in[19]:6 8.610429e-05 +10 ropt_net_173:3 ropt_net_184:5 7.68326e-05 +11 ropt_net_173:2 ropt_net_184:6 7.68326e-05 + +*RES +0 BUFT_RR_48:X ropt_net_173:7 0.152 +1 ropt_net_173:7 ropt_net_173:6 0.004444196 +2 ropt_net_173:6 ropt_net_173:5 0.0045 +3 ropt_net_173:5 ropt_net_173:4 0.005383929 +4 ropt_net_173:3 ropt_net_173:2 0.001569196 +5 ropt_net_173:4 ropt_net_173:3 0.0045 +6 ropt_net_173:2 ropt_mt_inst_777:A 0.152 + +*END + +*D_NET ropt_net_192 0.001332192 //LENGTH 10.495 LUMPCC 0.0004021323 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 39.755 101.660 +*I ropt_mt_inst_795:A I *L 0.001767 *C 34.040 104.720 +*N ropt_net_192:2 *C 34.040 104.720 +*N ropt_net_192:3 *C 34.040 105.060 +*N ropt_net_192:4 *C 36.755 105.060 +*N ropt_net_192:5 *C 36.800 105.015 +*N ropt_net_192:6 *C 36.800 101.705 +*N ropt_net_192:7 *C 36.845 101.660 +*N ropt_net_192:8 *C 39.718 101.660 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_192:2 4.628396e-05 +3 ropt_net_192:3 0.0001033627 +4 ropt_net_192:4 8.829214e-05 +5 ropt_net_192:5 0.0001620032 +6 ropt_net_192:6 0.0001620032 +7 ropt_net_192:7 0.0001830576 +8 ropt_net_192:8 0.0001830576 +9 ropt_net_192:6 chany_bottom_in[3]:12 3.670062e-05 +10 ropt_net_192:4 chany_bottom_in[3]:10 3.696209e-05 +11 ropt_net_192:5 chany_bottom_in[3]:11 3.670062e-05 +12 ropt_net_192:2 chany_bottom_in[3]:9 1.45205e-05 +13 ropt_net_192:3 chany_bottom_in[3]:8 1.45205e-05 +14 ropt_net_192:3 chany_bottom_in[3]:9 3.696209e-05 +15 ropt_net_192:4 chany_bottom_in[18]:6 0.000112883 +16 ropt_net_192:3 chany_bottom_in[18]:5 0.000112883 + +*RES +0 ropt_mt_inst_785:X ropt_net_192:8 0.152 +1 ropt_net_192:8 ropt_net_192:7 0.002564732 +2 ropt_net_192:7 ropt_net_192:6 0.0045 +3 ropt_net_192:6 ropt_net_192:5 0.002955357 +4 ropt_net_192:4 ropt_net_192:3 0.002424107 +5 ropt_net_192:5 ropt_net_192:4 0.0045 +6 ropt_net_192:2 ropt_mt_inst_795:A 0.152 +7 ropt_net_192:3 ropt_net_192:2 0.0003035714 + +*END + +*D_NET chany_bottom_out[2] 0.001165836 //LENGTH 8.910 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 76.095 3.740 +*P chany_bottom_out[2] O *L 0.7423 *C 70.380 1.290 +*N chany_bottom_out[2]:2 *C 70.380 3.355 +*N chany_bottom_out[2]:3 *C 70.425 3.400 +*N chany_bottom_out[2]:4 *C 74.520 3.400 +*N chany_bottom_out[2]:5 *C 74.520 3.740 +*N chany_bottom_out[2]:6 *C 76.058 3.740 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 chany_bottom_out[2] 0.0001437865 +2 chany_bottom_out[2]:2 0.0001437865 +3 chany_bottom_out[2]:3 0.0002925208 +4 chany_bottom_out[2]:4 0.0003153333 +5 chany_bottom_out[2]:5 0.0001461106 +6 chany_bottom_out[2]:6 0.000123298 + +*RES +0 ropt_mt_inst_798:X chany_bottom_out[2]:6 0.152 +1 chany_bottom_out[2]:6 chany_bottom_out[2]:5 0.001372768 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +3 chany_bottom_out[2]:2 chany_bottom_out[2] 0.00184375 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.00365625 +5 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.0003035715 + +*END + +*D_NET chany_bottom_out[5] 0.0007136155 //LENGTH 6.675 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 30.360 6.120 +*P chany_bottom_out[5] O *L 0.7423 *C 28.980 1.290 +*N chany_bottom_out[5]:2 *C 28.980 6.075 +*N chany_bottom_out[5]:3 *C 29.025 6.120 +*N chany_bottom_out[5]:4 *C 30.323 6.120 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 chany_bottom_out[5] 0.0002505494 +2 chany_bottom_out[5]:2 0.0002505494 +3 chany_bottom_out[5]:3 0.0001057583 +4 chany_bottom_out[5]:4 0.0001057583 + +*RES +0 ropt_mt_inst_799:X chany_bottom_out[5]:4 0.152 +1 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.001158482 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +3 chany_bottom_out[5]:2 chany_bottom_out[5] 0.004272321 + +*END + +*D_NET chany_bottom_out[11] 0.0006652391 //LENGTH 4.990 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 41.860 6.120 +*P chany_bottom_out[11] O *L 0.7423 *C 41.860 1.290 +*N chany_bottom_out[11]:2 *C 41.860 6.075 +*N chany_bottom_out[11]:3 *C 41.860 6.120 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 chany_bottom_out[11] 0.000314422 +2 chany_bottom_out[11]:2 0.000314422 +3 chany_bottom_out[11]:3 3.539509e-05 + +*RES +0 ropt_mt_inst_800:X chany_bottom_out[11]:3 0.152 +1 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +2 chany_bottom_out[11]:2 chany_bottom_out[11] 0.004272321 + +*END + +*D_NET ropt_net_163 0.00350303 //LENGTH 30.920 LUMPCC 0.0004686876 DR + +*CONN +*I BUFT_RR_67:X O *L 0 *C 40.480 25.500 +*I ropt_mt_inst_767:A I *L 0.001766 *C 35.420 4.080 +*N ropt_net_163:2 *C 35.458 4.080 +*N ropt_net_163:3 *C 38.595 4.080 +*N ropt_net_163:4 *C 38.640 4.125 +*N ropt_net_163:5 *C 38.640 11.855 +*N ropt_net_163:6 *C 38.685 11.900 +*N ropt_net_163:7 *C 41.815 11.900 +*N ropt_net_163:8 *C 41.860 11.945 +*N ropt_net_163:9 *C 41.860 25.115 +*N ropt_net_163:10 *C 41.815 25.160 +*N ropt_net_163:11 *C 40.480 25.160 +*N ropt_net_163:12 *C 40.480 25.500 + +*CAP +0 BUFT_RR_67:X 1e-06 +1 ropt_mt_inst_767:A 1e-06 +2 ropt_net_163:2 0.000134381 +3 ropt_net_163:3 0.000134381 +4 ropt_net_163:4 0.000418149 +5 ropt_net_163:5 0.000418149 +6 ropt_net_163:6 0.0001907055 +7 ropt_net_163:7 0.0001907055 +8 ropt_net_163:8 0.0006200531 +9 ropt_net_163:9 0.0006200531 +10 ropt_net_163:10 0.0001095718 +11 ropt_net_163:11 0.0001380775 +12 ropt_net_163:12 5.811585e-05 +13 ropt_net_163:8 chany_bottom_in[0] 0.0001008069 +14 ropt_net_163:9 chany_bottom_in[0]:17 0.0001008069 +15 ropt_net_163:2 chany_top_in[18]:5 0.0001335369 +16 ropt_net_163:3 chany_top_in[18]:4 0.0001335369 + +*RES +0 BUFT_RR_67:X ropt_net_163:12 0.152 +1 ropt_net_163:2 ropt_mt_inst_767:A 0.152 +2 ropt_net_163:3 ropt_net_163:2 0.002801339 +3 ropt_net_163:4 ropt_net_163:3 0.0045 +4 ropt_net_163:6 ropt_net_163:5 0.0045 +5 ropt_net_163:5 ropt_net_163:4 0.006901786 +6 ropt_net_163:7 ropt_net_163:6 0.002794643 +7 ropt_net_163:8 ropt_net_163:7 0.0045 +8 ropt_net_163:10 ropt_net_163:9 0.0045 +9 ropt_net_163:9 ropt_net_163:8 0.01175893 +10 ropt_net_163:12 ropt_net_163:11 0.0003035715 +11 ropt_net_163:11 ropt_net_163:10 0.001191964 + +*END + +*D_NET chany_top_out[0] 0.0004689181 //LENGTH 3.955 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_806:X O *L 0 *C 67.160 105.400 +*P chany_top_out[0] O *L 0.7423 *C 65.780 107.510 +*N chany_top_out[0]:2 *C 65.780 105.445 +*N chany_top_out[0]:3 *C 65.825 105.400 +*N chany_top_out[0]:4 *C 67.123 105.400 + +*CAP +0 ropt_mt_inst_806:X 1e-06 +1 chany_top_out[0] 0.0001266387 +2 chany_top_out[0]:2 0.0001266387 +3 chany_top_out[0]:3 0.0001073203 +4 chany_top_out[0]:4 0.0001073203 + +*RES +0 ropt_mt_inst_806:X chany_top_out[0]:4 0.152 +1 chany_top_out[0]:4 chany_top_out[0]:3 0.001158482 +2 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +3 chany_top_out[0]:2 chany_top_out[0] 0.00184375 + +*END + +*D_NET mem_right_ipin_0/net_net_76 0.0001440343 //LENGTH 1.355 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_0\/FTB_2__41:X O *L 0 *C 7.965 74.800 +*I mem_right_ipin_0\/BUFT_RR_142:A I *L 0.001746 *C 6.900 74.800 +*N mem_right_ipin_0/net_net_76:2 *C 6.938 74.800 +*N mem_right_ipin_0/net_net_76:3 *C 7.928 74.800 + +*CAP +0 mem_right_ipin_0\/FTB_2__41:X 1e-06 +1 mem_right_ipin_0\/BUFT_RR_142:A 1e-06 +2 mem_right_ipin_0/net_net_76:2 7.101715e-05 +3 mem_right_ipin_0/net_net_76:3 7.101715e-05 + +*RES +0 mem_right_ipin_0\/FTB_2__41:X mem_right_ipin_0/net_net_76:3 0.152 +1 mem_right_ipin_0/net_net_76:2 mem_right_ipin_0\/BUFT_RR_142:A 0.152 +2 mem_right_ipin_0/net_net_76:3 mem_right_ipin_0/net_net_76:2 0.0008839286 + +*END + +*D_NET chany_bottom_out[7] 0.0008907648 //LENGTH 7.575 LUMPCC 7.65337e-05 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 69.460 7.480 +*P chany_bottom_out[7] O *L 0.7423 *C 68.540 1.290 +*N chany_bottom_out[7]:2 *C 68.540 7.435 +*N chany_bottom_out[7]:3 *C 68.585 7.480 +*N chany_bottom_out[7]:4 *C 69.422 7.480 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 chany_bottom_out[7] 0.0003347633 +2 chany_bottom_out[7]:2 0.0003347633 +3 chany_bottom_out[7]:3 7.185228e-05 +4 chany_bottom_out[7]:4 7.185228e-05 +5 chany_bottom_out[7] ropt_net_209:4 2.632179e-05 +6 chany_bottom_out[7]:4 ropt_net_209:3 1.194506e-05 +7 chany_bottom_out[7]:3 ropt_net_209:2 1.194506e-05 +8 chany_bottom_out[7]:2 ropt_net_209:5 2.632179e-05 + +*RES +0 ropt_mt_inst_812:X chany_bottom_out[7]:4 0.152 +1 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.0007477679 +2 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0045 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.005486608 + +*END + +*D_NET chany_bottom_out[0] 0.0007268273 //LENGTH 6.055 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 68.540 4.760 +*P chany_bottom_out[0] O *L 0.7423 *C 67.620 1.290 +*N chany_bottom_out[0]:2 *C 67.620 1.700 +*N chany_bottom_out[0]:3 *C 67.160 1.700 +*N chany_bottom_out[0]:4 *C 67.160 4.715 +*N chany_bottom_out[0]:5 *C 67.205 4.760 +*N chany_bottom_out[0]:6 *C 68.502 4.760 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 chany_bottom_out[0] 3.515355e-05 +2 chany_bottom_out[0]:2 6.452399e-05 +3 chany_bottom_out[0]:3 0.0002189777 +4 chany_bottom_out[0]:4 0.0001896073 +5 chany_bottom_out[0]:5 0.0001087824 +6 chany_bottom_out[0]:6 0.0001087824 + +*RES +0 ropt_mt_inst_816:X chany_bottom_out[0]:6 0.152 +1 chany_bottom_out[0]:6 chany_bottom_out[0]:5 0.001158482 +2 chany_bottom_out[0]:5 chany_bottom_out[0]:4 0.0045 +3 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002691964 +4 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0004107143 +5 chany_bottom_out[0]:2 chany_bottom_out[0] 0.0003660714 + +*END + +*D_NET chany_top_out[12] 0.001239868 //LENGTH 10.810 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_820:X O *L 0 *C 67.815 101.320 +*P chany_top_out[12] O *L 0.7423 *C 63.940 107.510 +*N chany_top_out[12]:2 *C 63.940 106.080 +*N chany_top_out[12]:3 *C 64.400 106.080 +*N chany_top_out[12]:4 *C 64.400 101.365 +*N chany_top_out[12]:5 *C 64.445 101.320 +*N chany_top_out[12]:6 *C 67.778 101.320 + +*CAP +0 ropt_mt_inst_820:X 1e-06 +1 chany_top_out[12] 9.103628e-05 +2 chany_top_out[12]:2 0.0001202588 +3 chany_top_out[12]:3 0.0002855169 +4 chany_top_out[12]:4 0.0002562944 +5 chany_top_out[12]:5 0.0002428807 +6 chany_top_out[12]:6 0.0002428807 + +*RES +0 ropt_mt_inst_820:X chany_top_out[12]:6 0.152 +1 chany_top_out[12]:6 chany_top_out[12]:5 0.002975447 +2 chany_top_out[12]:5 chany_top_out[12]:4 0.0045 +3 chany_top_out[12]:4 chany_top_out[12]:3 0.004209822 +4 chany_top_out[12]:2 chany_top_out[12] 0.001276786 +5 chany_top_out[12]:3 chany_top_out[12]:2 0.0004107143 + +*END + +*D_NET ropt_net_174 0.001730493 //LENGTH 12.900 LUMPCC 0 DR + +*CONN +*I BUFT_P_107:X O *L 0 *C 77.740 99.620 +*I ropt_mt_inst_778:A I *L 0.001766 *C 68.540 102.000 +*N ropt_net_174:2 *C 68.578 102.000 +*N ropt_net_174:3 *C 69.460 102.000 +*N ropt_net_174:4 *C 69.460 101.660 +*N ropt_net_174:5 *C 71.255 101.660 +*N ropt_net_174:6 *C 71.300 101.615 +*N ropt_net_174:7 *C 71.300 100.005 +*N ropt_net_174:8 *C 71.345 99.960 +*N ropt_net_174:9 *C 77.740 99.960 +*N ropt_net_174:10 *C 77.740 99.620 + +*CAP +0 BUFT_P_107:X 1e-06 +1 ropt_mt_inst_778:A 1e-06 +2 ropt_net_174:2 8.000503e-05 +3 ropt_net_174:3 0.0001061292 +4 ropt_net_174:4 0.0001667235 +5 ropt_net_174:5 0.0001405993 +6 ropt_net_174:6 0.0001073765 +7 ropt_net_174:7 0.0001073765 +8 ropt_net_174:8 0.0004686843 +9 ropt_net_174:9 0.0004959847 +10 ropt_net_174:10 5.56138e-05 + +*RES +0 BUFT_P_107:X ropt_net_174:10 0.152 +1 ropt_net_174:2 ropt_mt_inst_778:A 0.152 +2 ropt_net_174:5 ropt_net_174:4 0.001602679 +3 ropt_net_174:6 ropt_net_174:5 0.0045 +4 ropt_net_174:8 ropt_net_174:7 0.0045 +5 ropt_net_174:7 ropt_net_174:6 0.0014375 +6 ropt_net_174:10 ropt_net_174:9 0.0003035715 +7 ropt_net_174:3 ropt_net_174:2 0.0007879465 +8 ropt_net_174:4 ropt_net_174:3 0.0003035715 +9 ropt_net_174:9 ropt_net_174:8 0.005709822 + +*END + +*D_NET ropt_net_178 0.0008983668 //LENGTH 8.140 LUMPCC 0.0001285683 DR + +*CONN +*I BUFT_P_116:X O *L 0 *C 15.640 96.900 +*I ropt_mt_inst_782:A I *L 0.001766 *C 15.640 104.720 +*N ropt_net_178:2 *C 15.640 104.720 +*N ropt_net_178:3 *C 15.640 104.675 +*N ropt_net_178:4 *C 15.640 96.945 +*N ropt_net_178:5 *C 15.640 96.900 + +*CAP +0 BUFT_P_116:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_178:2 3.092616e-05 +3 ropt_net_178:3 0.0003505754 +4 ropt_net_178:4 0.0003505754 +5 ropt_net_178:5 3.572153e-05 +6 ropt_net_178:4 ropt_net_205:4 6.428415e-05 +7 ropt_net_178:3 ropt_net_205:5 6.428415e-05 + +*RES +0 BUFT_P_116:X ropt_net_178:5 0.152 +1 ropt_net_178:5 ropt_net_178:4 0.0045 +2 ropt_net_178:4 ropt_net_178:3 0.006901786 +3 ropt_net_178:2 ropt_mt_inst_782:A 0.152 +4 ropt_net_178:3 ropt_net_178:2 0.0045 + +*END + +*D_NET chany_bottom_in[3] 0.01650874 //LENGTH 146.395 LUMPCC 0.003324279 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 49.220 1.290 +*I mux_right_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.325 61.540 +*I BUFT_P_109:A I *L 0.001776 *C 19.320 99.280 +*N chany_bottom_in[3]:3 *C 19.358 99.280 +*N chany_bottom_in[3]:4 *C 19.735 99.280 +*N chany_bottom_in[3]:5 *C 19.780 99.325 +*N chany_bottom_in[3]:6 *C 19.780 105.015 +*N chany_bottom_in[3]:7 *C 19.825 105.060 +*N chany_bottom_in[3]:8 *C 33.580 105.060 +*N chany_bottom_in[3]:9 *C 33.580 104.380 +*N chany_bottom_in[3]:10 *C 37.675 104.380 +*N chany_bottom_in[3]:11 *C 37.720 104.335 +*N chany_bottom_in[3]:12 *C 37.720 61.585 +*N chany_bottom_in[3]:13 *C 37.675 61.540 +*N chany_bottom_in[3]:14 *C 35.363 61.540 +*N chany_bottom_in[3]:15 *C 35.880 61.540 +*N chany_bottom_in[3]:16 *C 35.880 61.495 +*N chany_bottom_in[3]:17 *C 35.880 22.498 +*N chany_bottom_in[3]:18 *C 35.888 22.440 +*N chany_bottom_in[3]:19 *C 49.213 22.440 +*N chany_bottom_in[3]:20 *C 49.220 22.383 + +*CAP +0 chany_bottom_in[3] 0.0008925314 +1 mux_right_ipin_0\/mux_l1_in_1_:A1 1e-06 +2 BUFT_P_109:A 1e-06 +3 chany_bottom_in[3]:3 4.435132e-05 +4 chany_bottom_in[3]:4 4.435132e-05 +5 chany_bottom_in[3]:5 0.0002142151 +6 chany_bottom_in[3]:6 0.0002142151 +7 chany_bottom_in[3]:7 0.0008606086 +8 chany_bottom_in[3]:8 0.000895781 +9 chany_bottom_in[3]:9 0.0003078102 +10 chany_bottom_in[3]:10 0.0002726379 +11 chany_bottom_in[3]:11 0.001774432 +12 chany_bottom_in[3]:12 0.001774432 +13 chany_bottom_in[3]:13 0.0001121749 +14 chany_bottom_in[3]:14 4.191779e-05 +15 chany_bottom_in[3]:15 0.0001865839 +16 chany_bottom_in[3]:16 0.001437711 +17 chany_bottom_in[3]:17 0.001437711 +18 chany_bottom_in[3]:18 0.0008892328 +19 chany_bottom_in[3]:19 0.0008892328 +20 chany_bottom_in[3]:20 0.0008925314 +21 chany_bottom_in[3]:16 chany_bottom_in[11]:10 9.71392e-05 +22 chany_bottom_in[3]:16 chany_bottom_in[11]:11 0.0004640842 +23 chany_bottom_in[3]:17 chany_bottom_in[11]:12 0.0004640842 +24 chany_bottom_in[3]:17 chany_bottom_in[11]:11 9.71392e-05 +25 chany_bottom_in[3]:12 chany_bottom_in[11]:11 0.0001292781 +26 chany_bottom_in[3]:11 chany_bottom_in[11]:10 0.0001292781 +27 chany_bottom_in[3] chany_bottom_in[16] 0.0002784226 +28 chany_bottom_in[3]:20 chany_bottom_in[16]:20 0.0002784226 +29 chany_bottom_in[3]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.0002171187 +30 chany_bottom_in[3]:12 mux_tree_tapbuf_size10_0_sram[2]:19 1.19335e-05 +31 chany_bottom_in[3]:11 mux_tree_tapbuf_size10_0_sram[2]:20 1.19335e-05 +32 chany_bottom_in[3]:11 mux_tree_tapbuf_size10_0_sram[2]:18 0.0002171187 +33 chany_bottom_in[3]:7 ropt_net_187:6 4.698801e-05 +34 chany_bottom_in[3]:8 ropt_net_187:7 4.698801e-05 +35 chany_bottom_in[3]:7 ropt_net_218:6 6.965702e-06 +36 chany_bottom_in[3]:6 ropt_net_218:5 0.000130981 +37 chany_bottom_in[3]:5 ropt_net_218:4 0.000130981 +38 chany_bottom_in[3]:8 ropt_net_218:7 6.965702e-06 +39 chany_bottom_in[3] ropt_net_190:6 0.0001309609 +40 chany_bottom_in[3]:20 ropt_net_190:7 0.0001309609 +41 chany_bottom_in[3]:7 ropt_net_199:2 6.008434e-05 +42 chany_bottom_in[3]:8 ropt_net_199:3 6.008434e-05 +43 chany_bottom_in[3]:12 ropt_net_192:6 3.670062e-05 +44 chany_bottom_in[3]:10 ropt_net_192:4 3.696209e-05 +45 chany_bottom_in[3]:11 ropt_net_192:5 3.670062e-05 +46 chany_bottom_in[3]:8 ropt_net_192:3 1.45205e-05 +47 chany_bottom_in[3]:9 ropt_net_192:2 1.45205e-05 +48 chany_bottom_in[3]:9 ropt_net_192:3 3.696209e-05 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:20 0.01883259 +1 chany_bottom_in[3]:15 chany_bottom_in[3]:14 0.0004620536 +2 chany_bottom_in[3]:15 chany_bottom_in[3]:13 0.001602679 +3 chany_bottom_in[3]:16 chany_bottom_in[3]:15 0.0045 +4 chany_bottom_in[3]:17 chany_bottom_in[3]:16 0.0348192 +5 chany_bottom_in[3]:18 chany_bottom_in[3]:17 0.00341 +6 chany_bottom_in[3]:20 chany_bottom_in[3]:19 0.00341 +7 chany_bottom_in[3]:19 chany_bottom_in[3]:18 0.002087583 +8 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.0045 +9 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.03816964 +10 chany_bottom_in[3]:10 chany_bottom_in[3]:9 0.00365625 +11 chany_bottom_in[3]:11 chany_bottom_in[3]:10 0.0045 +12 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.0045 +13 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.005080357 +14 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.0003370536 +15 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.0045 +16 chany_bottom_in[3]:3 BUFT_P_109:A 0.152 +17 chany_bottom_in[3]:14 mux_right_ipin_0\/mux_l1_in_1_:A1 0.152 +18 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.01228125 +19 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.0006071429 + +*END + +*D_NET chany_bottom_in[4] 0.01527382 //LENGTH 151.880 LUMPCC 0.002299244 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 36.340 1.325 +*I mux_left_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 69.365 72.420 +*I BUFT_P_108:A I *L 0.001776 *C 78.660 99.280 +*N chany_bottom_in[4]:3 *C 35.170 3.400 +*N chany_bottom_in[4]:4 *C 78.623 99.280 +*N chany_bottom_in[4]:5 *C 76.405 99.280 +*N chany_bottom_in[4]:6 *C 76.360 99.325 +*N chany_bottom_in[4]:7 *C 76.360 101.955 +*N chany_bottom_in[4]:8 *C 76.315 102.000 +*N chany_bottom_in[4]:9 *C 75.945 102.000 +*N chany_bottom_in[4]:10 *C 75.900 101.955 +*N chany_bottom_in[4]:11 *C 75.900 72.805 +*N chany_bottom_in[4]:12 *C 75.855 72.760 +*N chany_bottom_in[4]:13 *C 69.403 72.420 +*N chany_bottom_in[4]:14 *C 69.920 72.420 +*N chany_bottom_in[4]:15 *C 69.920 72.760 +*N chany_bottom_in[4]:16 *C 69.920 72.715 +*N chany_bottom_in[4]:17 *C 69.920 72.138 +*N chany_bottom_in[4]:18 *C 69.913 72.080 +*N chany_bottom_in[4]:19 *C 35.900 72.080 +*N chany_bottom_in[4]:20 *C 35.880 72.073 +*N chany_bottom_in[4]:21 *C 35.880 53.235 +*N chany_bottom_in[4]:22 *C 35.880 3.408 +*N chany_bottom_in[4]:23 *C 35.878 3.400 +*N chany_bottom_in[4]:24 *C 35.880 3.343 +*N chany_bottom_in[4]:25 *C 35.880 1.360 + +*CAP +0 chany_bottom_in[4] 3.22128e-05 +1 mux_left_ipin_0\/mux_l1_in_2_:A1 1e-06 +2 BUFT_P_108:A 1e-06 +3 chany_bottom_in[4]:3 7.62427e-05 +4 chany_bottom_in[4]:4 0.0001584323 +5 chany_bottom_in[4]:5 0.0001584323 +6 chany_bottom_in[4]:6 0.0001720305 +7 chany_bottom_in[4]:7 0.0001720305 +8 chany_bottom_in[4]:8 4.958258e-05 +9 chany_bottom_in[4]:9 4.958258e-05 +10 chany_bottom_in[4]:10 0.00124721 +11 chany_bottom_in[4]:11 0.00124721 +12 chany_bottom_in[4]:12 0.0004032661 +13 chany_bottom_in[4]:13 5.370762e-05 +14 chany_bottom_in[4]:14 8.338473e-05 +15 chany_bottom_in[4]:15 0.0004329432 +16 chany_bottom_in[4]:16 6.586968e-05 +17 chany_bottom_in[4]:17 6.586968e-05 +18 chany_bottom_in[4]:18 0.002059733 +19 chany_bottom_in[4]:19 0.002059733 +20 chany_bottom_in[4]:20 0.0005208543 +21 chany_bottom_in[4]:21 0.002000406 +22 chany_bottom_in[4]:22 0.001479552 +23 chany_bottom_in[4]:23 7.62427e-05 +24 chany_bottom_in[4]:24 0.0001379172 +25 chany_bottom_in[4]:25 0.00017013 +26 chany_bottom_in[4]:18 chany_bottom_in[17]:14 1.078086e-05 +27 chany_bottom_in[4]:19 chany_bottom_in[17]:13 1.078086e-05 +28 chany_bottom_in[4]:20 chany_bottom_in[17]:15 0.000289448 +29 chany_bottom_in[4]:20 chany_bottom_in[17]:16 1.148697e-05 +30 chany_bottom_in[4]:22 chany_bottom_in[17]:17 0.0007610692 +31 chany_bottom_in[4]:21 chany_bottom_in[17]:17 1.148697e-05 +32 chany_bottom_in[4]:21 chany_bottom_in[17]:16 0.001050517 +33 chany_bottom_in[4]:11 ropt_net_154:5 7.683696e-05 +34 chany_bottom_in[4]:10 ropt_net_154:4 7.683696e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:25 0.0004107143 +1 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.0045 +2 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.02602679 +3 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.0003303572 +4 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.0045 +5 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.0045 +6 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.002348214 +7 chany_bottom_in[4]:5 chany_bottom_in[4]:4 0.001979911 +8 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.0045 +9 chany_bottom_in[4]:4 BUFT_P_108:A 0.152 +10 chany_bottom_in[4]:13 mux_left_ipin_0\/mux_l1_in_2_:A1 0.152 +11 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.0003035715 +12 chany_bottom_in[4]:15 chany_bottom_in[4]:12 0.005299108 +13 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.0045 +14 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.000515625 +15 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.00341 +16 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.005328625 +17 chany_bottom_in[4]:20 chany_bottom_in[4]:19 0.00341 +18 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.00341 +19 chany_bottom_in[4]:23 chany_bottom_in[4]:3 0.0001039141 +20 chany_bottom_in[4]:22 chany_bottom_in[4]:21 0.007806308 +21 chany_bottom_in[4]:24 chany_bottom_in[4]:23 0.00341 +22 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.0004620536 +23 chany_bottom_in[4]:25 chany_bottom_in[4]:24 0.001770089 +24 chany_bottom_in[4]:21 chany_bottom_in[4]:20 0.002951208 + +*END + +*D_NET chany_top_in[12] 0.01206976 //LENGTH 115.095 LUMPCC 0.003074618 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 67.620 107.510 +*I ropt_mt_inst_764:A I *L 0.001766 *C 77.740 6.800 +*N chany_top_in[12]:2 *C 77.703 6.800 +*N chany_top_in[12]:3 *C 75.440 6.800 +*N chany_top_in[12]:4 *C 75.440 6.460 +*N chany_top_in[12]:5 *C 72.265 6.460 +*N chany_top_in[12]:6 *C 72.220 6.505 +*N chany_top_in[12]:7 *C 72.220 27.835 +*N chany_top_in[12]:8 *C 72.175 27.880 +*N chany_top_in[12]:9 *C 70.380 27.880 +*N chany_top_in[12]:10 *C 70.380 29.240 +*N chany_top_in[12]:11 *C 69.585 29.240 +*N chany_top_in[12]:12 *C 69.470 29.195 +*N chany_top_in[12]:13 *C 69.460 28.605 +*N chany_top_in[12]:14 *C 69.415 28.560 +*N chany_top_in[12]:15 *C 67.665 28.560 +*N chany_top_in[12]:16 *C 67.620 28.605 +*N chany_top_in[12]:17 *C 67.620 78.400 + +*CAP +0 chany_top_in[12] 0.001079074 +1 ropt_mt_inst_764:A 1e-06 +2 chany_top_in[12]:2 9.35637e-05 +3 chany_top_in[12]:3 0.0001178311 +4 chany_top_in[12]:4 0.0002612189 +5 chany_top_in[12]:5 0.0002369515 +6 chany_top_in[12]:6 0.0008141114 +7 chany_top_in[12]:7 0.0008141114 +8 chany_top_in[12]:8 0.0001301807 +9 chany_top_in[12]:9 0.0002202568 +10 chany_top_in[12]:10 0.0001605504 +11 chany_top_in[12]:11 7.047431e-05 +12 chany_top_in[12]:12 6.487201e-05 +13 chany_top_in[12]:13 6.487201e-05 +14 chany_top_in[12]:14 0.0001212654 +15 chany_top_in[12]:15 0.0001212654 +16 chany_top_in[12]:16 0.001772235 +17 chany_top_in[12]:17 0.002851309 +18 chany_top_in[12]:6 chany_bottom_in[2] 0.0002684109 +19 chany_top_in[12]:7 chany_bottom_in[2]:13 0.0002684109 +20 chany_top_in[12] chany_top_in[7] 0.000396928 +21 chany_top_in[12]:16 chany_top_in[7]:5 0.0005311688 +22 chany_top_in[12]:16 chany_top_in[7]:6 0.0001762375 +23 chany_top_in[12]:17 chany_top_in[7] 0.0001762375 +24 chany_top_in[12]:17 chany_top_in[7]:6 0.0009280967 +25 chany_top_in[12] mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.864656e-05 +26 chany_top_in[12]:17 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.864656e-05 +27 chany_top_in[12]:2 ropt_net_188:7 6.749518e-05 +28 chany_top_in[12]:5 ropt_net_188:6 8.211826e-06 +29 chany_top_in[12]:6 ropt_net_188:5 1.021013e-05 +30 chany_top_in[12]:7 ropt_net_188:4 1.021013e-05 +31 chany_top_in[12]:4 ropt_net_188:7 8.211826e-06 +32 chany_top_in[12]:3 ropt_net_188:6 6.749518e-05 + +*RES +0 chany_top_in[12] chany_top_in[12]:17 0.02599107 +1 chany_top_in[12]:2 ropt_mt_inst_764:A 0.152 +2 chany_top_in[12]:5 chany_top_in[12]:4 0.002834822 +3 chany_top_in[12]:6 chany_top_in[12]:5 0.0045 +4 chany_top_in[12]:8 chany_top_in[12]:7 0.0045 +5 chany_top_in[12]:7 chany_top_in[12]:6 0.01904464 +6 chany_top_in[12]:11 chany_top_in[12]:10 0.0007098214 +7 chany_top_in[12]:12 chany_top_in[12]:11 0.0045 +8 chany_top_in[12]:14 chany_top_in[12]:13 0.0045 +9 chany_top_in[12]:13 chany_top_in[12]:12 0.0005267857 +10 chany_top_in[12]:15 chany_top_in[12]:14 0.0015625 +11 chany_top_in[12]:16 chany_top_in[12]:15 0.0045 +12 chany_top_in[12]:10 chany_top_in[12]:9 0.001214286 +13 chany_top_in[12]:9 chany_top_in[12]:8 0.001602679 +14 chany_top_in[12]:4 chany_top_in[12]:3 0.0003035715 +15 chany_top_in[12]:3 chany_top_in[12]:2 0.002020089 +16 chany_top_in[12]:17 chany_top_in[12]:16 0.04445983 + +*END + +*D_NET chany_top_in[15] 0.01173588 //LENGTH 104.480 LUMPCC 0.005729156 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 47.840 107.590 +*I ropt_mt_inst_772:A I *L 0.001767 *C 51.520 9.520 +*N chany_top_in[15]:2 *C 51.483 9.520 +*N chany_top_in[15]:3 *C 49.725 9.520 +*N chany_top_in[15]:4 *C 49.680 9.565 +*N chany_top_in[15]:5 *C 49.680 17.635 +*N chany_top_in[15]:6 *C 49.635 17.680 +*N chany_top_in[15]:7 *C 47.425 17.680 +*N chany_top_in[15]:8 *C 47.380 17.725 +*N chany_top_in[15]:9 *C 47.380 67.943 +*N chany_top_in[15]:10 *C 47.383 68.000 +*N chany_top_in[15]:11 *C 47.825 68.000 +*N chany_top_in[15]:12 *C 47.840 68.008 + +*CAP +0 chany_top_in[15] 0.0006242 +1 ropt_mt_inst_772:A 1e-06 +2 chany_top_in[15]:2 0.0001240537 +3 chany_top_in[15]:3 0.0001240537 +4 chany_top_in[15]:4 0.0004841686 +5 chany_top_in[15]:5 0.0004841686 +6 chany_top_in[15]:6 0.0001533828 +7 chany_top_in[15]:7 0.0001533828 +8 chany_top_in[15]:8 0.001563836 +9 chany_top_in[15]:9 0.001563836 +10 chany_top_in[15]:10 5.322058e-05 +11 chany_top_in[15]:11 5.322058e-05 +12 chany_top_in[15]:12 0.0006242 +13 chany_top_in[15]:8 chany_bottom_in[16] 0.0004564476 +14 chany_top_in[15]:9 chany_bottom_in[16]:20 0.0004564476 +15 chany_top_in[15]:8 chany_top_in[1]:13 0.0002739003 +16 chany_top_in[15]:9 chany_top_in[1]:14 0.0002739003 +17 chany_top_in[15]:8 chany_top_in[4]:7 0.0002104246 +18 chany_top_in[15]:8 chany_top_in[4]:15 4.694312e-05 +19 chany_top_in[15]:9 chany_top_in[4]:8 0.0002104246 +20 chany_top_in[15]:9 chany_top_in[4]:16 4.694312e-05 +21 chany_top_in[15] chany_top_in[13] 0.0008938809 +22 chany_top_in[15]:4 chany_top_in[13]:15 1.899211e-05 +23 chany_top_in[15]:5 chany_top_in[13]:16 1.899211e-05 +24 chany_top_in[15]:12 chany_top_in[13]:16 0.0008938809 +25 chany_top_in[15] chany_top_in[14] 0.000836655 +26 chany_top_in[15] chany_top_in[14]:19 5.722596e-05 +27 chany_top_in[15]:8 chany_top_in[14]:18 7.01084e-05 +28 chany_top_in[15]:9 chany_top_in[14]:19 7.01084e-05 +29 chany_top_in[15]:12 chany_top_in[14]:18 5.722596e-05 +30 chany_top_in[15]:12 chany_top_in[14]:19 0.000836655 + +*RES +0 chany_top_in[15] chany_top_in[15]:12 0.006201258 +1 chany_top_in[15]:2 ropt_mt_inst_772:A 0.152 +2 chany_top_in[15]:3 chany_top_in[15]:2 0.001569197 +3 chany_top_in[15]:4 chany_top_in[15]:3 0.0045 +4 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +5 chany_top_in[15]:5 chany_top_in[15]:4 0.007205358 +6 chany_top_in[15]:7 chany_top_in[15]:6 0.001973214 +7 chany_top_in[15]:8 chany_top_in[15]:7 0.0045 +8 chany_top_in[15]:9 chany_top_in[15]:8 0.04483706 +9 chany_top_in[15]:10 chany_top_in[15]:9 0.00341 +10 chany_top_in[15]:11 chany_top_in[15]:10 6.499218e-05 +11 chany_top_in[15]:12 chany_top_in[15]:11 0.00341 + +*END + +*D_NET chany_top_in[19] 0.01490637 //LENGTH 131.275 LUMPCC 0.00355236 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 25.760 107.590 +*I ropt_mt_inst_759:A I *L 0.001767 *C 49.220 4.080 +*N chany_top_in[19]:2 *C 49.183 4.080 +*N chany_top_in[19]:3 *C 45.540 4.080 +*N chany_top_in[19]:4 *C 45.540 3.740 +*N chany_top_in[19]:5 *C 41.445 3.740 +*N chany_top_in[19]:6 *C 41.400 3.785 +*N chany_top_in[19]:7 *C 41.400 8.795 +*N chany_top_in[19]:8 *C 41.355 8.840 +*N chany_top_in[19]:9 *C 37.765 8.840 +*N chany_top_in[19]:10 *C 37.720 8.885 +*N chany_top_in[19]:11 *C 37.720 14.915 +*N chany_top_in[19]:12 *C 37.675 14.960 +*N chany_top_in[19]:13 *C 32.245 14.960 +*N chany_top_in[19]:14 *C 32.200 15.005 +*N chany_top_in[19]:15 *C 32.200 39.055 +*N chany_top_in[19]:16 *C 32.200 39.100 +*N chany_top_in[19]:17 *C 32.245 39.440 +*N chany_top_in[19]:18 *C 29.025 39.440 +*N chany_top_in[19]:19 *C 28.980 39.485 +*N chany_top_in[19]:20 *C 28.980 46.183 +*N chany_top_in[19]:21 *C 28.973 46.240 +*N chany_top_in[19]:22 *C 25.780 46.240 +*N chany_top_in[19]:23 *C 25.760 46.248 +*N chany_top_in[19]:24 *C 25.760 96.075 + +*CAP +0 chany_top_in[19] 0.0004602706 +1 ropt_mt_inst_759:A 1e-06 +2 chany_top_in[19]:2 0.0001970506 +3 chany_top_in[19]:3 0.0002203254 +4 chany_top_in[19]:4 0.0003352391 +5 chany_top_in[19]:5 0.0003119643 +6 chany_top_in[19]:6 0.0002763364 +7 chany_top_in[19]:7 0.0002763364 +8 chany_top_in[19]:8 0.0002436318 +9 chany_top_in[19]:9 0.0002436318 +10 chany_top_in[19]:10 0.000331365 +11 chany_top_in[19]:11 0.000331365 +12 chany_top_in[19]:12 0.0002913091 +13 chany_top_in[19]:13 0.0002913091 +14 chany_top_in[19]:14 0.001063411 +15 chany_top_in[19]:15 0.001063411 +16 chany_top_in[19]:16 5.690259e-05 +17 chany_top_in[19]:17 0.0002035278 +18 chany_top_in[19]:18 0.0001755561 +19 chany_top_in[19]:19 0.0003314847 +20 chany_top_in[19]:20 0.0003314847 +21 chany_top_in[19]:21 0.0002158636 +22 chany_top_in[19]:22 0.0002158636 +23 chany_top_in[19]:23 0.001712551 +24 chany_top_in[19]:24 0.002172822 +25 chany_top_in[19] chany_top_in[18] 0.0002592525 +26 chany_top_in[19]:23 chany_top_in[18]:14 0.0009339849 +27 chany_top_in[19]:23 chany_top_in[18]:15 0.0002603225 +28 chany_top_in[19]:15 chany_top_in[18]:7 4.180669e-06 +29 chany_top_in[19]:15 chany_top_in[18]:11 6.068667e-05 +30 chany_top_in[19]:14 chany_top_in[18]:6 4.180669e-06 +31 chany_top_in[19]:14 chany_top_in[18]:10 6.068667e-05 +32 chany_top_in[19]:24 chany_top_in[18] 0.0002603225 +33 chany_top_in[19]:24 chany_top_in[18]:15 0.001193237 +34 chany_top_in[19]:11 ropt_net_214:4 4.750762e-07 +35 chany_top_in[19]:9 ropt_net_214:3 1.02601e-05 +36 chany_top_in[19]:10 ropt_net_214:5 4.750762e-07 +37 chany_top_in[19]:8 ropt_net_214:2 1.02601e-05 +38 chany_top_in[19]:7 ropt_net_214:4 7.841554e-05 +39 chany_top_in[19]:6 ropt_net_214:5 7.841554e-05 +40 chany_top_in[19]:5 ropt_net_190:2 2.438549e-05 +41 chany_top_in[19]:2 ropt_net_190:5 0.0001406068 +42 chany_top_in[19]:4 ropt_net_190:3 2.799532e-05 +43 chany_top_in[19]:3 ropt_net_190:4 0.0001442167 + +*RES +0 chany_top_in[19] chany_top_in[19]:24 0.001804017 +1 chany_top_in[19]:18 chany_top_in[19]:17 0.002875 +2 chany_top_in[19]:19 chany_top_in[19]:18 0.0045 +3 chany_top_in[19]:20 chany_top_in[19]:19 0.005979911 +4 chany_top_in[19]:21 chany_top_in[19]:20 0.00341 +5 chany_top_in[19]:22 chany_top_in[19]:21 0.0005001583 +6 chany_top_in[19]:23 chany_top_in[19]:22 0.00341 +7 chany_top_in[19]:16 chany_top_in[19]:15 0.0045 +8 chany_top_in[19]:15 chany_top_in[19]:14 0.02147322 +9 chany_top_in[19]:13 chany_top_in[19]:12 0.004848215 +10 chany_top_in[19]:14 chany_top_in[19]:13 0.0045 +11 chany_top_in[19]:12 chany_top_in[19]:11 0.0045 +12 chany_top_in[19]:11 chany_top_in[19]:10 0.005383929 +13 chany_top_in[19]:9 chany_top_in[19]:8 0.003205357 +14 chany_top_in[19]:10 chany_top_in[19]:9 0.0045 +15 chany_top_in[19]:8 chany_top_in[19]:7 0.0045 +16 chany_top_in[19]:7 chany_top_in[19]:6 0.004473215 +17 chany_top_in[19]:5 chany_top_in[19]:4 0.00365625 +18 chany_top_in[19]:6 chany_top_in[19]:5 0.0045 +19 chany_top_in[19]:2 ropt_mt_inst_759:A 0.152 +20 chany_top_in[19]:17 chany_top_in[19]:16 0.0001847826 +21 chany_top_in[19]:4 chany_top_in[19]:3 0.0003035715 +22 chany_top_in[19]:3 chany_top_in[19]:2 0.003252232 +23 chany_top_in[19]:24 chany_top_in[19]:23 0.007806308 + +*END + +*D_NET left_grid_pin_0_[0] 0.002125094 //LENGTH 21.610 LUMPCC 0.000265257 DR + +*CONN +*I mux_right_ipin_0\/mux_l4_in_0_:X O *L 0 *C 3.900 80.920 +*P left_grid_pin_0_[0] O *L 0.7423 *C 1.230 99.280 +*N left_grid_pin_0_[0]:2 *C 3.673 99.280 +*N left_grid_pin_0_[0]:3 *C 3.680 99.223 +*N left_grid_pin_0_[0]:4 *C 3.680 80.965 +*N left_grid_pin_0_[0]:5 *C 3.680 80.920 +*N left_grid_pin_0_[0]:6 *C 3.900 80.920 + +*CAP +0 mux_right_ipin_0\/mux_l4_in_0_:X 1e-06 +1 left_grid_pin_0_[0] 0.0001149996 +2 left_grid_pin_0_[0]:2 0.0001149996 +3 left_grid_pin_0_[0]:3 0.000763963 +4 left_grid_pin_0_[0]:4 0.000763963 +5 left_grid_pin_0_[0]:5 5.339237e-05 +6 left_grid_pin_0_[0]:6 4.751994e-05 +7 left_grid_pin_0_[0]:4 ropt_net_176:4 0.0001326285 +8 left_grid_pin_0_[0]:3 ropt_net_176:3 0.0001326285 + +*RES +0 mux_right_ipin_0\/mux_l4_in_0_:X left_grid_pin_0_[0]:6 0.152 +1 left_grid_pin_0_[0]:6 left_grid_pin_0_[0]:5 0.0001195652 +2 left_grid_pin_0_[0]:5 left_grid_pin_0_[0]:4 0.0045 +3 left_grid_pin_0_[0]:4 left_grid_pin_0_[0]:3 0.01630134 +4 left_grid_pin_0_[0]:3 left_grid_pin_0_[0]:2 0.00341 +5 left_grid_pin_0_[0]:2 left_grid_pin_0_[0] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.006810229 //LENGTH 54.740 LUMPCC 0.0005872712 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 60.105 98.940 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 54.915 96.900 +*I mux_left_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 67.260 85.680 +*I mux_left_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 69.100 79.560 +*I mux_left_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 68.640 72.080 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 68.678 72.080 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 72.175 72.080 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 72.220 72.125 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 69.138 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 72.175 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 72.220 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 72.220 85.635 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 72.175 85.680 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 67.260 85.680 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 61.225 85.680 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 61.180 85.725 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 54.953 96.900 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 56.580 96.900 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 56.580 97.240 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 61.135 97.240 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 61.180 97.240 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 61.180 98.895 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 61.058 98.940 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 60.143 98.940 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_ipin_0\/mux_l1_in_1_:S 1e-06 +3 mux_left_ipin_0\/mux_l1_in_0_:S 1e-06 +4 mux_left_ipin_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 0.0002857405 +6 mux_tree_tapbuf_size10_0_sram[0]:6 0.0002857405 +7 mux_tree_tapbuf_size10_0_sram[0]:7 0.0003007183 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.0002482817 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0002482817 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0005722411 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.0002441666 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0002528446 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0006657899 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.000380763 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0006710448 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0001295089 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0001550751 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0003467218 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0003211556 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.0008041706 +21 mux_tree_tapbuf_size10_0_sram[0]:21 0.0001026244 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.0001015451 +23 mux_tree_tapbuf_size10_0_sram[0]:23 0.0001015451 +24 mux_tree_tapbuf_size10_0_sram[0]:14 chany_bottom_in[2]:9 3.554147e-05 +25 mux_tree_tapbuf_size10_0_sram[0]:14 chany_bottom_in[2]:10 8.074028e-06 +26 mux_tree_tapbuf_size10_0_sram[0]:7 chany_bottom_in[2]:13 8.703356e-05 +27 mux_tree_tapbuf_size10_0_sram[0]:12 chany_bottom_in[2]:7 1.613165e-05 +28 mux_tree_tapbuf_size10_0_sram[0]:12 chany_bottom_in[2]:8 2.97311e-05 +29 mux_tree_tapbuf_size10_0_sram[0]:12 chany_bottom_in[2]:11 4.359376e-05 +30 mux_tree_tapbuf_size10_0_sram[0]:11 chany_bottom_in[2]:5 9.670461e-06 +31 mux_tree_tapbuf_size10_0_sram[0]:11 chany_bottom_in[2]:12 6.385954e-05 +32 mux_tree_tapbuf_size10_0_sram[0]:13 chany_bottom_in[2]:8 3.554147e-05 +33 mux_tree_tapbuf_size10_0_sram[0]:13 chany_bottom_in[2]:9 2.97311e-05 +34 mux_tree_tapbuf_size10_0_sram[0]:13 chany_bottom_in[2]:10 4.359376e-05 +35 mux_tree_tapbuf_size10_0_sram[0]:13 chany_bottom_in[2]:11 2.420568e-05 +36 mux_tree_tapbuf_size10_0_sram[0]:10 chany_bottom_in[2]:6 9.670461e-06 +37 mux_tree_tapbuf_size10_0_sram[0]:10 chany_bottom_in[2]:12 8.703356e-05 +38 mux_tree_tapbuf_size10_0_sram[0]:10 chany_bottom_in[2]:13 6.385954e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:23 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.0045 +2 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.001477679 +3 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.0008169643 +4 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.005388393 +5 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_0_sram[0]:14 0.0045 +6 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.003122768 +7 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0045 +8 mux_tree_tapbuf_size10_0_sram[0]:5 mux_left_ipin_0\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.004066965 +10 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0045 +11 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:15 0.01028125 +12 mux_tree_tapbuf_size10_0_sram[0]:16 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:11 0.0045 +14 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.005424107 +15 mux_tree_tapbuf_size10_0_sram[0]:13 mux_left_ipin_0\/mux_l1_in_1_:S 0.152 +16 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.004388393 +17 mux_tree_tapbuf_size10_0_sram[0]:9 mux_tree_tapbuf_size10_0_sram[0]:8 0.002712053 +18 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.0045 +19 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:7 0.006638393 +20 mux_tree_tapbuf_size10_0_sram[0]:8 mux_left_ipin_0\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.001453125 +22 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.003671733 //LENGTH 32.010 LUMPCC 0.0009344775 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 39.865 93.500 +*I mem_left_ipin_0\/FTB_1__40:A I *L 0.001746 *C 35.420 85.680 +*I mux_left_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 44.500 72.420 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 44.462 72.420 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 40.525 72.420 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 40.480 72.465 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 35.458 85.680 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 40.435 85.680 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 40.480 85.680 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 40.480 93.455 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 40.435 93.500 +*N mux_tree_tapbuf_size10_0_sram[3]:11 *C 39.903 93.500 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_ipin_0\/FTB_1__40:A 1e-06 +2 mux_left_ipin_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 0.0002495272 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0002495272 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0005397035 +6 mux_tree_tapbuf_size10_0_sram[3]:6 0.0002000711 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0002000711 +8 mux_tree_tapbuf_size10_0_sram[3]:8 0.0008767403 +9 mux_tree_tapbuf_size10_0_sram[3]:9 0.0003101637 +10 mux_tree_tapbuf_size10_0_sram[3]:10 5.42257e-05 +11 mux_tree_tapbuf_size10_0_sram[3]:11 5.42257e-05 +12 mux_tree_tapbuf_size10_0_sram[3]:7 chany_bottom_in[7]:5 0.0001955251 +13 mux_tree_tapbuf_size10_0_sram[3]:6 chany_bottom_in[7]:4 0.0001955251 +14 mux_tree_tapbuf_size10_0_sram[3]:5 chany_top_in[9]:13 0.0001834853 +15 mux_tree_tapbuf_size10_0_sram[3]:8 chany_top_in[9]:13 8.822833e-05 +16 mux_tree_tapbuf_size10_0_sram[3]:8 chany_top_in[9]:14 0.0001834853 +17 mux_tree_tapbuf_size10_0_sram[3]:9 chany_top_in[9]:14 8.822833e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:4 mux_tree_tapbuf_size10_0_sram[3]:3 0.003515625 +2 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size10_0_sram[3]:3 mux_left_ipin_0\/mux_l4_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.004444197 +5 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:5 0.01179911 +7 mux_tree_tapbuf_size10_0_sram[3]:6 mem_left_ipin_0\/FTB_1__40:A 0.152 +8 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.0045 +9 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.006941964 +10 mux_tree_tapbuf_size10_0_sram[3]:11 mux_tree_tapbuf_size10_0_sram[3]:10 0.0004754464 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.00488149 //LENGTH 35.290 LUMPCC 0.0009437789 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 30.510 82.280 +*I mux_right_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 27.240 79.950 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 19.955 77.180 +*I mux_right_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 15.740 74.800 +*I mux_right_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 20.800 68.680 +*I mux_right_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 21.720 67.320 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 21.683 67.320 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 20.745 67.320 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 20.700 67.365 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 20.700 68.635 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 20.700 68.680 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 20.700 69.020 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 19.365 69.020 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 19.320 69.065 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 15.778 74.800 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 19.275 74.800 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 19.320 74.800 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 19.320 77.135 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 19.365 77.180 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 19.955 77.180 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 27.095 77.180 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 27.140 77.225 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 27.240 79.950 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 27.140 80.240 +*N mux_tree_tapbuf_size10_1_sram[1]:24 *C 27.140 80.240 +*N mux_tree_tapbuf_size10_1_sram[1]:25 *C 27.140 82.235 +*N mux_tree_tapbuf_size10_1_sram[1]:26 *C 27.185 82.280 +*N mux_tree_tapbuf_size10_1_sram[1]:27 *C 30.473 82.280 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_0\/mux_l2_in_2_:S 1e-06 +2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_ipin_0\/mux_l2_in_3_:S 1e-06 +4 mux_right_ipin_0\/mux_l2_in_1_:S 1e-06 +5 mux_right_ipin_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 8.864426e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:7 8.864426e-05 +8 mux_tree_tapbuf_size10_1_sram[1]:8 7.541948e-05 +9 mux_tree_tapbuf_size10_1_sram[1]:9 7.541948e-05 +10 mux_tree_tapbuf_size10_1_sram[1]:10 6.680361e-05 +11 mux_tree_tapbuf_size10_1_sram[1]:11 0.0001343259 +12 mux_tree_tapbuf_size10_1_sram[1]:12 0.0001037402 +13 mux_tree_tapbuf_size10_1_sram[1]:13 0.0002041243 +14 mux_tree_tapbuf_size10_1_sram[1]:14 0.0002734994 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0002734994 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0003248816 +17 mux_tree_tapbuf_size10_1_sram[1]:17 9.160093e-05 +18 mux_tree_tapbuf_size10_1_sram[1]:18 5.679397e-05 +19 mux_tree_tapbuf_size10_1_sram[1]:19 0.0004097376 +20 mux_tree_tapbuf_size10_1_sram[1]:20 0.0003216489 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.0001647064 +22 mux_tree_tapbuf_size10_1_sram[1]:22 6.534871e-05 +23 mux_tree_tapbuf_size10_1_sram[1]:23 7.0493e-05 +24 mux_tree_tapbuf_size10_1_sram[1]:24 0.0003154091 +25 mux_tree_tapbuf_size10_1_sram[1]:25 0.0001211704 +26 mux_tree_tapbuf_size10_1_sram[1]:26 0.0003028999 +27 mux_tree_tapbuf_size10_1_sram[1]:27 0.0003028999 +28 mux_tree_tapbuf_size10_1_sram[1]:16 chany_bottom_in[1]:6 0.0001620508 +29 mux_tree_tapbuf_size10_1_sram[1]:16 chany_bottom_in[1]:7 6.771629e-05 +30 mux_tree_tapbuf_size10_1_sram[1]:17 chany_bottom_in[1]:6 6.771629e-05 +31 mux_tree_tapbuf_size10_1_sram[1]:13 chany_bottom_in[1]:7 0.0001620508 +32 mux_tree_tapbuf_size10_1_sram[1]:9 chany_bottom_in[1]:6 2.280901e-05 +33 mux_tree_tapbuf_size10_1_sram[1]:8 chany_bottom_in[1]:7 2.280901e-05 +34 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[2]:9 1.652299e-05 +35 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[2]:11 1.651855e-05 +36 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[2]:12 1.651855e-05 +37 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[2]:10 1.652299e-05 +38 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[2]:12 1.149274e-08 +39 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[2]:11 1.103303e-07 +40 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[2]:16 0.0001860114 +41 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[2]:13 1.149274e-08 +42 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[2]:12 2.490093e-07 +43 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[2]:17 0.0001860114 +44 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[2]:13 1.38679e-07 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:27 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:25 0.0045 +2 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:24 0.00178125 +3 mux_tree_tapbuf_size10_1_sram[1]:27 mux_tree_tapbuf_size10_1_sram[1]:26 0.002935268 +4 mux_tree_tapbuf_size10_1_sram[1]:14 mux_right_ipin_0\/mux_l2_in_3_:S 0.152 +5 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.003122768 +6 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:13 0.005120536 +8 mux_tree_tapbuf_size10_1_sram[1]:23 mux_tree_tapbuf_size10_1_sram[1]:22 0.000125 +9 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:23 0.0045 +10 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:21 0.002691964 +11 mux_tree_tapbuf_size10_1_sram[1]:22 mux_right_ipin_0\/mux_l2_in_2_:S 0.152 +12 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[1]:17 0.0045 +13 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.002084822 +14 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 0.001191964 +15 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:12 0.0045 +16 mux_tree_tapbuf_size10_1_sram[1]:19 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.0005267857 +18 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.006375 +19 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.0045 +20 mux_tree_tapbuf_size10_1_sram[1]:10 mux_right_ipin_0\/mux_l2_in_1_:S 0.152 +21 mux_tree_tapbuf_size10_1_sram[1]:10 mux_tree_tapbuf_size10_1_sram[1]:9 0.0045 +22 mux_tree_tapbuf_size10_1_sram[1]:9 mux_tree_tapbuf_size10_1_sram[1]:8 0.001133929 +23 mux_tree_tapbuf_size10_1_sram[1]:7 mux_tree_tapbuf_size10_1_sram[1]:6 0.0008370536 +24 mux_tree_tapbuf_size10_1_sram[1]:8 mux_tree_tapbuf_size10_1_sram[1]:7 0.0045 +25 mux_tree_tapbuf_size10_1_sram[1]:6 mux_right_ipin_0\/mux_l2_in_0_:S 0.152 +26 mux_tree_tapbuf_size10_1_sram[1]:11 mux_tree_tapbuf_size10_1_sram[1]:10 0.0003035715 + +*END + +*D_NET optlc_net_144 0.0004095235 //LENGTH 2.735 LUMPCC 0 DR + +*CONN +*I optlc_144:HI O *L 0 *C 57.040 65.960 +*I mux_left_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 56.410 64.600 +*N optlc_net_144:2 *C 56.410 64.600 +*N optlc_net_144:3 *C 56.580 64.600 +*N optlc_net_144:4 *C 56.580 64.645 +*N optlc_net_144:5 *C 56.580 65.915 +*N optlc_net_144:6 *C 56.625 65.960 +*N optlc_net_144:7 *C 57.003 65.960 + +*CAP +0 optlc_144:HI 1e-06 +1 mux_left_ipin_0\/mux_l2_in_3_:A0 1e-06 +2 optlc_net_144:2 6.109593e-05 +3 optlc_net_144:3 6.250718e-05 +4 optlc_net_144:4 9.233703e-05 +5 optlc_net_144:5 9.233703e-05 +6 optlc_net_144:6 4.962318e-05 +7 optlc_net_144:7 4.962318e-05 + +*RES +0 optlc_144:HI optlc_net_144:7 0.152 +1 optlc_net_144:2 mux_left_ipin_0\/mux_l2_in_3_:A0 0.152 +2 optlc_net_144:3 optlc_net_144:2 9.23913e-05 +3 optlc_net_144:4 optlc_net_144:3 0.0045 +4 optlc_net_144:6 optlc_net_144:5 0.0045 +5 optlc_net_144:5 optlc_net_144:4 0.001133929 +6 optlc_net_144:7 optlc_net_144:6 0.0003370536 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008659203 //LENGTH 7.105 LUMPCC 0.0003569087 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_1_:X O *L 0 *C 66.415 86.360 +*I mux_left_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 67.450 91.800 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 67.413 91.800 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.745 91.800 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 66.700 91.755 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 66.700 86.405 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 66.700 86.360 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 66.415 86.360 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.71101e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.71101e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001541277 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001541277 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.623415e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.830174e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[12] 7.864656e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[12]:17 7.864656e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.555177e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.555177e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.425603e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.425603e-05 + +*RES +0 mux_left_ipin_0\/mux_l1_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005959822 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002439355 //LENGTH 20.160 LUMPCC 0.0007819615 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_2_:X O *L 0 *C 55.945 53.720 +*I mux_left_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 53.725 66.980 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 53.763 66.980 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 57.455 66.980 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 57.500 66.935 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 57.500 55.465 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 57.455 55.420 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 56.625 55.420 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 56.580 55.375 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 56.580 53.765 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 56.535 53.720 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 55.983 53.720 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000212888 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000212888 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004096284 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004096284 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.739105e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.739105e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 8.197541e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 8.197541e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 5.581382e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 5.581382e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_top_in[16]:18 2.368889e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_top_in[16]:5 2.368889e-05 +14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[16]:4 6.529181e-06 +15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[16]:18 2.087894e-05 +16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[16]:3 6.529181e-06 +17 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[16]:17 2.087894e-05 +18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[16]:18 1.5185e-05 +19 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[16]:17 1.5185e-05 +20 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:15 0.0002261434 +21 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:16 8.995016e-05 +22 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:12 0.0002261434 +23 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:15 8.995016e-05 +24 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size10_0_sram[1]:15 5.467394e-06 +25 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_tree_tapbuf_size10_0_sram[1]:9 3.137834e-06 +26 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size10_0_sram[1]:12 5.467394e-06 +27 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_tree_tapbuf_size10_0_sram[1]:8 3.137834e-06 + +*RES +0 mux_left_ipin_0\/mux_l2_in_2_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003296875 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01024107 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0007410714 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0014375 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0004933036 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001544701 //LENGTH 13.270 LUMPCC 0.0004722984 DR + +*CONN +*I mux_left_ipin_0\/mux_l3_in_1_:X O *L 0 *C 52.155 66.300 +*I mux_left_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 45.255 71.740 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 45.293 71.740 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 49.175 71.740 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 49.220 71.695 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 49.220 66.345 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 49.265 66.300 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 52.117 66.300 + +*CAP +0 mux_left_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002415151 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002415151 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001207554 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001207554 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001729307 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001729307 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_bottom_in[18]:11 0.0001588873 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_bottom_in[18]:12 0.0001588873 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_top_in[4] 7.25568e-07 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_top_in[4]:16 7.653642e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_top_in[4]:15 7.653642e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_top_in[4]:19 7.25568e-07 + +*RES +0 mux_left_ipin_0\/mux_l3_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_ipin_0\/mux_l4_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.003466518 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004776786 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.002546875 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001866814 //LENGTH 17.230 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_1_:X O *L 0 *C 33.755 60.860 +*I mux_right_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 22.830 65.960 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 22.830 65.960 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.540 65.960 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 22.540 65.915 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 22.540 60.905 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 22.585 60.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 33.718 60.860 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.61797e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.016737e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002527019 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002527019 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006315315 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006315315 + +*RES +0 mux_right_ipin_0\/mux_l1_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001576087 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.009939733 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00102919 //LENGTH 7.220 LUMPCC 0.0002810821 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_1_:X O *L 0 *C 19.955 70.040 +*I mux_right_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 20.990 75.140 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 20.990 75.140 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 21.160 75.140 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 21.160 75.095 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 21.160 70.085 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 21.115 70.040 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 19.992 70.040 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.36634e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.829396e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002197883 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002197883 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.728684e-05 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.728684e-05 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.947031e-06 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.947031e-06 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000138594 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000138594 + +*RES +0 mux_right_ipin_0\/mux_l2_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473215 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001002232 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001558292 //LENGTH 12.500 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/mux_l3_in_1_:X O *L 0 *C 10.755 75.480 +*I mux_right_ipin_0\/mux_l4_in_0_:A0 I *L 0.005103 *C 8.740 81.075 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 8.703 81.075 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 6.900 81.075 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 6.900 79.560 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 9.155 79.560 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 9.200 79.515 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 9.200 75.525 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 9.245 75.480 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 10.718 75.480 + +*CAP +0 mux_right_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001557542 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002462515 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002550492 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.000164552 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0002419083 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0002419083 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0001254342 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0001254342 + +*RES +0 mux_right_ipin_0\/mux_l3_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.001314732 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0045 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0035625 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002013393 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_0\/mux_l4_in_0_:A0 0.152 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.001352679 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001609375 + +*END + +*D_NET ropt_net_210 0.000695045 //LENGTH 5.015 LUMPCC 0.0002635998 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 58.245 102.000 +*I ropt_mt_inst_813:A I *L 0.001767 *C 57.040 104.720 +*N ropt_net_210:2 *C 57.078 104.720 +*N ropt_net_210:3 *C 58.375 104.720 +*N ropt_net_210:4 *C 58.420 104.675 +*N ropt_net_210:5 *C 58.420 102.045 +*N ropt_net_210:6 *C 58.420 102.000 +*N ropt_net_210:7 *C 58.245 102.000 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 ropt_mt_inst_813:A 1e-06 +2 ropt_net_210:2 8.951374e-05 +3 ropt_net_210:3 8.951374e-05 +4 ropt_net_210:4 7.965382e-05 +5 ropt_net_210:5 7.965382e-05 +6 ropt_net_210:6 4.788785e-05 +7 ropt_net_210:7 4.322223e-05 +8 ropt_net_210:4 chany_bottom_in[12]:4 8.232506e-05 +9 ropt_net_210:6 chany_bottom_in[12]:6 5.257777e-06 +10 ropt_net_210:5 chany_bottom_in[12]:5 8.232506e-05 +11 ropt_net_210:7 chany_bottom_in[12]:7 5.257777e-06 +12 ropt_net_210:2 chany_top_out[6]:3 4.421708e-05 +13 ropt_net_210:3 chany_top_out[6]:4 4.421708e-05 + +*RES +0 ropt_mt_inst_751:X ropt_net_210:7 0.152 +1 ropt_net_210:2 ropt_mt_inst_813:A 0.152 +2 ropt_net_210:3 ropt_net_210:2 0.001158482 +3 ropt_net_210:4 ropt_net_210:3 0.0045 +4 ropt_net_210:6 ropt_net_210:5 0.0045 +5 ropt_net_210:5 ropt_net_210:4 0.002348214 +6 ropt_net_210:7 ropt_net_210:6 9.51087e-05 + +*END + +*D_NET chany_top_out[10] 0.001130348 //LENGTH 7.930 LUMPCC 0.0002149249 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 56.315 104.380 +*P chany_top_out[10] O *L 0.7423 *C 51.980 107.510 +*N chany_top_out[10]:2 *C 51.980 104.425 +*N chany_top_out[10]:3 *C 52.025 104.380 +*N chany_top_out[10]:4 *C 56.278 104.380 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 chany_top_out[10] 0.0002240708 +2 chany_top_out[10]:2 0.0002240708 +3 chany_top_out[10]:3 0.0002331407 +4 chany_top_out[10]:4 0.0002331407 +5 chany_top_out[10]:4 ropt_net_186:3 0.0001074625 +6 chany_top_out[10]:3 ropt_net_186:2 0.0001074625 + +*RES +0 ropt_mt_inst_789:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.003796875 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.002754464 + +*END + +*D_NET ropt_net_214 0.001185964 //LENGTH 9.390 LUMPCC 0.0002534393 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 37.260 6.120 +*I ropt_mt_inst_817:A I *L 0.001766 *C 42.320 9.520 +*N ropt_net_214:2 *C 42.282 9.520 +*N ropt_net_214:3 *C 40.985 9.520 +*N ropt_net_214:4 *C 40.940 9.475 +*N ropt_net_214:5 *C 40.940 6.165 +*N ropt_net_214:6 *C 40.895 6.120 +*N ropt_net_214:7 *C 37.297 6.120 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 ropt_mt_inst_817:A 1e-06 +2 ropt_net_214:2 8.285552e-05 +3 ropt_net_214:3 8.285552e-05 +4 ropt_net_214:4 0.0001390287 +5 ropt_net_214:5 0.0001390287 +6 ropt_net_214:6 0.0002433783 +7 ropt_net_214:7 0.0002433783 +8 ropt_net_214:2 chany_top_in[19]:8 1.02601e-05 +9 ropt_net_214:3 chany_top_in[19]:9 1.02601e-05 +10 ropt_net_214:4 chany_top_in[19]:7 7.841554e-05 +11 ropt_net_214:4 chany_top_in[19]:11 4.750762e-07 +12 ropt_net_214:5 chany_top_in[19]:6 7.841554e-05 +13 ropt_net_214:5 chany_top_in[19]:10 4.750762e-07 +14 ropt_net_214:4 ropt_net_197:4 2.5958e-05 +15 ropt_net_214:6 ropt_net_197:2 1.161091e-05 +16 ropt_net_214:5 ropt_net_197:5 2.5958e-05 +17 ropt_net_214:7 ropt_net_197:3 1.161091e-05 + +*RES +0 ropt_mt_inst_754:X ropt_net_214:7 0.152 +1 ropt_net_214:2 ropt_mt_inst_817:A 0.152 +2 ropt_net_214:3 ropt_net_214:2 0.001158482 +3 ropt_net_214:4 ropt_net_214:3 0.0045 +4 ropt_net_214:6 ropt_net_214:5 0.0045 +5 ropt_net_214:5 ropt_net_214:4 0.002955357 +6 ropt_net_214:7 ropt_net_214:6 0.003212054 + +*END + +*D_NET ropt_net_181 0.002276763 //LENGTH 16.410 LUMPCC 0.0007109002 DR + +*CONN +*I FTB_12__11:X O *L 0 *C 26.680 95.880 +*I ropt_mt_inst_785:A I *L 0.001766 *C 35.880 102.000 +*N ropt_net_181:2 *C 35.880 102.000 +*N ropt_net_181:3 *C 35.880 101.660 +*N ropt_net_181:4 *C 30.865 101.660 +*N ropt_net_181:5 *C 30.820 101.615 +*N ropt_net_181:6 *C 30.820 95.938 +*N ropt_net_181:7 *C 30.812 95.880 +*N ropt_net_181:8 *C 26.688 95.880 +*N ropt_net_181:9 *C 26.680 95.880 +*N ropt_net_181:10 *C 26.680 95.880 + +*CAP +0 FTB_12__11:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_181:2 5.467673e-05 +3 ropt_net_181:3 0.000247258 +4 ropt_net_181:4 0.0002203576 +5 ropt_net_181:5 0.0002101311 +6 ropt_net_181:6 0.0002101311 +7 ropt_net_181:7 0.0002747229 +8 ropt_net_181:8 0.0002747229 +9 ropt_net_181:9 3.377999e-05 +10 ropt_net_181:10 3.808167e-05 +11 ropt_net_181:6 chany_bottom_in[12]:11 0.0001650745 +12 ropt_net_181:4 chany_bottom_in[12]:9 1.173052e-05 +13 ropt_net_181:5 chany_bottom_in[12]:10 0.0001650745 +14 ropt_net_181:3 chany_bottom_in[12]:8 1.173052e-05 +15 ropt_net_181:4 ropt_net_202:2 0.0001132738 +16 ropt_net_181:3 ropt_net_202:3 0.0001132738 +17 ropt_net_181:6 chany_top_out[17]:2 8.541182e-06 +18 ropt_net_181:4 chany_top_out[17]:3 5.683014e-05 +19 ropt_net_181:5 chany_top_out[17] 8.541182e-06 +20 ropt_net_181:3 chany_top_out[17]:4 5.683014e-05 + +*RES +0 FTB_12__11:X ropt_net_181:10 0.152 +1 ropt_net_181:10 ropt_net_181:9 0.0045 +2 ropt_net_181:9 ropt_net_181:8 0.00341 +3 ropt_net_181:8 ropt_net_181:7 0.00064625 +4 ropt_net_181:6 ropt_net_181:5 0.005069197 +5 ropt_net_181:7 ropt_net_181:6 0.00341 +6 ropt_net_181:4 ropt_net_181:3 0.004477679 +7 ropt_net_181:5 ropt_net_181:4 0.0045 +8 ropt_net_181:2 ropt_mt_inst_785:A 0.152 +9 ropt_net_181:3 ropt_net_181:2 0.0003035715 + +*END + +*D_NET ropt_net_216 0.001260806 //LENGTH 8.930 LUMPCC 0.000503021 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 50.140 3.400 +*I ropt_mt_inst_819:A I *L 0.001766 *C 45.540 6.800 +*N ropt_net_216:2 *C 45.578 6.800 +*N ropt_net_216:3 *C 47.795 6.800 +*N ropt_net_216:4 *C 47.840 6.755 +*N ropt_net_216:5 *C 47.840 3.445 +*N ropt_net_216:6 *C 47.885 3.400 +*N ropt_net_216:7 *C 50.102 3.400 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 ropt_mt_inst_819:A 1e-06 +2 ropt_net_216:2 0.0001015857 +3 ropt_net_216:3 0.0001015857 +4 ropt_net_216:4 8.552558e-05 +5 ropt_net_216:5 8.552558e-05 +6 ropt_net_216:6 0.0001907812 +7 ropt_net_216:7 0.0001907812 +8 ropt_net_216:5 chany_bottom_in[16] 9.696596e-05 +9 ropt_net_216:4 chany_bottom_in[16]:20 9.696596e-05 +10 ropt_net_216:3 chany_top_in[4]:6 6.15336e-05 +11 ropt_net_216:2 chany_top_in[4]:5 6.15336e-05 +12 ropt_net_216:5 chany_bottom_out[19] 8.007647e-05 +13 ropt_net_216:3 chany_bottom_out[19]:4 1.293449e-05 +14 ropt_net_216:4 chany_bottom_out[19]:2 8.007647e-05 +15 ropt_net_216:2 chany_bottom_out[19]:3 1.293449e-05 + +*RES +0 ropt_mt_inst_759:X ropt_net_216:7 0.152 +1 ropt_net_216:7 ropt_net_216:6 0.001979911 +2 ropt_net_216:6 ropt_net_216:5 0.0045 +3 ropt_net_216:5 ropt_net_216:4 0.002955357 +4 ropt_net_216:3 ropt_net_216:2 0.001979911 +5 ropt_net_216:4 ropt_net_216:3 0.0045 +6 ropt_net_216:2 ropt_mt_inst_819:A 0.152 + +*END + +*D_NET chany_bottom_out[18] 0.001180657 //LENGTH 6.610 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 40.940 3.400 +*P chany_bottom_out[18] O *L 0.7423 *C 44.160 1.210 +*N chany_bottom_out[18]:2 *C 43.760 3.400 +*N chany_bottom_out[18]:3 *C 44.160 3.393 +*N chany_bottom_out[18]:4 *C 44.160 3.400 +*N chany_bottom_out[18]:5 *C 44.160 3.400 +*N chany_bottom_out[18]:6 *C 44.115 3.400 +*N chany_bottom_out[18]:7 *C 40.977 3.400 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chany_bottom_out[18] 0.0001712887 +2 chany_bottom_out[18]:2 0.0001094364 +3 chany_bottom_out[18]:3 0.0001712887 +4 chany_bottom_out[18]:4 0.0001094364 +5 chany_bottom_out[18]:5 3.460102e-05 +6 chany_bottom_out[18]:6 0.0002918031 +7 chany_bottom_out[18]:7 0.0002918031 + +*RES +0 ropt_mt_inst_761:X chany_bottom_out[18]:7 0.152 +1 chany_bottom_out[18]:7 chany_bottom_out[18]:6 0.002801339 +2 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.0045 +3 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.00341 +4 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.00341 +5 chany_bottom_out[18]:4 chany_bottom_out[18]:2 5.69697e-05 +6 chany_bottom_out[18]:3 chany_bottom_out[18] 0.000341925 + +*END + +*D_NET ropt_net_191 0.001586872 //LENGTH 11.995 LUMPCC 0.0002337676 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 59.995 8.840 +*I ropt_mt_inst_794:A I *L 0.001767 *C 54.740 6.800 +*N ropt_net_191:2 *C 58.480 8.840 +*N ropt_net_191:3 *C 58.170 6.120 +*N ropt_net_191:4 *C 54.778 6.800 +*N ropt_net_191:5 *C 56.535 6.800 +*N ropt_net_191:6 *C 56.580 6.755 +*N ropt_net_191:7 *C 56.580 6.165 +*N ropt_net_191:8 *C 56.625 6.120 +*N ropt_net_191:9 *C 58.835 6.120 +*N ropt_net_191:10 *C 58.880 6.120 +*N ropt_net_191:11 *C 58.878 6.120 +*N ropt_net_191:12 *C 58.880 6.128 +*N ropt_net_191:13 *C 58.880 8.832 +*N ropt_net_191:14 *C 58.880 8.840 +*N ropt_net_191:15 *C 58.880 8.840 +*N ropt_net_191:16 *C 58.925 8.840 +*N ropt_net_191:17 *C 59.958 8.840 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_191:2 5.660056e-05 +3 ropt_net_191:3 7.231696e-05 +4 ropt_net_191:4 7.610289e-05 +5 ropt_net_191:5 7.610289e-05 +6 ropt_net_191:6 5.518452e-05 +7 ropt_net_191:7 5.518452e-05 +8 ropt_net_191:8 0.0001291314 +9 ropt_net_191:9 0.0001291314 +10 ropt_net_191:10 3.326368e-05 +11 ropt_net_191:11 7.231696e-05 +12 ropt_net_191:12 0.0001647381 +13 ropt_net_191:13 0.0001647381 +14 ropt_net_191:14 5.660056e-05 +15 ropt_net_191:15 3.412434e-05 +16 ropt_net_191:16 8.778372e-05 +17 ropt_net_191:17 8.778372e-05 +18 ropt_net_191:9 chany_top_in[1]:3 3.604051e-05 +19 ropt_net_191:9 chany_top_in[1]:5 1.226267e-06 +20 ropt_net_191:8 chany_top_in[1]:4 3.604051e-05 +21 ropt_net_191:8 chany_top_in[1]:6 1.226267e-06 +22 ropt_net_191:5 chany_top_in[1]:5 7.961701e-05 +23 ropt_net_191:4 chany_top_in[1]:6 7.961701e-05 + +*RES +0 ropt_mt_inst_763:X ropt_net_191:17 0.152 +1 ropt_net_191:17 ropt_net_191:16 0.0009218751 +2 ropt_net_191:16 ropt_net_191:15 0.0045 +3 ropt_net_191:15 ropt_net_191:14 0.00341 +4 ropt_net_191:14 ropt_net_191:13 0.00341 +5 ropt_net_191:14 ropt_net_191:2 5.69697e-05 +6 ropt_net_191:13 ropt_net_191:12 0.0004237833 +7 ropt_net_191:11 ropt_net_191:10 0.00341 +8 ropt_net_191:11 ropt_net_191:3 0.0001039141 +9 ropt_net_191:12 ropt_net_191:11 0.00341 +10 ropt_net_191:10 ropt_net_191:9 0.0045 +11 ropt_net_191:9 ropt_net_191:8 0.001973214 +12 ropt_net_191:8 ropt_net_191:7 0.0045 +13 ropt_net_191:7 ropt_net_191:6 0.0005267857 +14 ropt_net_191:5 ropt_net_191:4 0.001569197 +15 ropt_net_191:6 ropt_net_191:5 0.0045 +16 ropt_net_191:4 ropt_mt_inst_794:A 0.152 + +*END + +*D_NET ropt_net_188 0.001117958 //LENGTH 9.670 LUMPCC 0.0001718343 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 77.015 7.140 +*I ropt_mt_inst_791:A I *L 0.001767 *C 70.655 9.520 +*N ropt_net_188:2 *C 70.693 9.520 +*N ropt_net_188:3 *C 74.475 9.520 +*N ropt_net_188:4 *C 74.520 9.475 +*N ropt_net_188:5 *C 74.520 7.185 +*N ropt_net_188:6 *C 74.565 7.140 +*N ropt_net_188:7 *C 76.978 7.140 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_188:2 0.0002408785 +3 ropt_net_188:3 0.0002408785 +4 ropt_net_188:4 0.0001230678 +5 ropt_net_188:5 0.0001230678 +6 ropt_net_188:6 0.0001081153 +7 ropt_net_188:7 0.0001081153 +8 ropt_net_188:7 chany_top_in[12]:2 6.749518e-05 +9 ropt_net_188:7 chany_top_in[12]:4 8.211826e-06 +10 ropt_net_188:6 chany_top_in[12]:3 6.749518e-05 +11 ropt_net_188:6 chany_top_in[12]:5 8.211826e-06 +12 ropt_net_188:5 chany_top_in[12]:6 1.021013e-05 +13 ropt_net_188:4 chany_top_in[12]:7 1.021013e-05 + +*RES +0 ropt_mt_inst_768:X ropt_net_188:7 0.152 +1 ropt_net_188:7 ropt_net_188:6 0.002154018 +2 ropt_net_188:6 ropt_net_188:5 0.0045 +3 ropt_net_188:5 ropt_net_188:4 0.002044643 +4 ropt_net_188:3 ropt_net_188:2 0.003377232 +5 ropt_net_188:4 ropt_net_188:3 0.0045 +6 ropt_net_188:2 ropt_mt_inst_791:A 0.152 + +*END + +*D_NET ropt_net_198 0.001693214 //LENGTH 14.230 LUMPCC 0.0001779989 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 65.975 11.560 +*I ropt_mt_inst_801:A I *L 0.001766 *C 61.640 9.520 +*N ropt_net_198:2 *C 61.640 9.520 +*N ropt_net_198:3 *C 61.640 9.475 +*N ropt_net_198:4 *C 61.640 6.165 +*N ropt_net_198:5 *C 61.685 6.120 +*N ropt_net_198:6 *C 65.735 6.120 +*N ropt_net_198:7 *C 65.780 6.165 +*N ropt_net_198:8 *C 65.780 11.515 +*N ropt_net_198:9 *C 65.780 11.560 +*N ropt_net_198:10 *C 65.975 11.560 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_198:2 3.125959e-05 +3 ropt_net_198:3 0.0001746757 +4 ropt_net_198:4 0.0001746757 +5 ropt_net_198:5 0.0002403321 +6 ropt_net_198:6 0.0002403321 +7 ropt_net_198:7 0.0002679369 +8 ropt_net_198:8 0.0002679369 +9 ropt_net_198:9 5.715074e-05 +10 ropt_net_198:10 5.891566e-05 +11 ropt_net_198:3 ropt_net_219:5 2.661105e-05 +12 ropt_net_198:5 ropt_net_219:7 1.353028e-05 +13 ropt_net_198:4 ropt_net_219:4 2.661105e-05 +14 ropt_net_198:6 ropt_net_219:6 1.353028e-05 +15 ropt_net_198:5 ropt_net_182:2 3.742678e-05 +16 ropt_net_198:6 ropt_net_182:3 3.742678e-05 +17 ropt_net_198:7 ropt_net_182:4 1.143134e-05 +18 ropt_net_198:8 ropt_net_182:5 1.143134e-05 + +*RES +0 ropt_mt_inst_771:X ropt_net_198:10 0.152 +1 ropt_net_198:2 ropt_mt_inst_801:A 0.152 +2 ropt_net_198:3 ropt_net_198:2 0.0045 +3 ropt_net_198:5 ropt_net_198:4 0.0045 +4 ropt_net_198:4 ropt_net_198:3 0.002955357 +5 ropt_net_198:6 ropt_net_198:5 0.003616072 +6 ropt_net_198:7 ropt_net_198:6 0.0045 +7 ropt_net_198:9 ropt_net_198:8 0.0045 +8 ropt_net_198:8 ropt_net_198:7 0.004776786 +9 ropt_net_198:10 ropt_net_198:9 0.0001059783 + +*END + +*D_NET ropt_net_204 0.001230064 //LENGTH 9.460 LUMPCC 0.0001115572 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 48.035 99.960 +*I ropt_mt_inst_807:A I *L 0.001767 *C 49.680 102.000 +*N ropt_net_204:2 *C 49.680 102.000 +*N ropt_net_204:3 *C 49.680 102.045 +*N ropt_net_204:4 *C 49.680 102.635 +*N ropt_net_204:5 *C 49.635 102.680 +*N ropt_net_204:6 *C 46.505 102.680 +*N ropt_net_204:7 *C 46.460 102.635 +*N ropt_net_204:8 *C 46.460 100.005 +*N ropt_net_204:9 *C 46.505 99.960 +*N ropt_net_204:10 *C 47.998 99.960 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 ropt_mt_inst_807:A 1e-06 +2 ropt_net_204:2 3.267208e-05 +3 ropt_net_204:3 6.288298e-05 +4 ropt_net_204:4 6.288298e-05 +5 ropt_net_204:5 0.0002071215 +6 ropt_net_204:6 0.0002071215 +7 ropt_net_204:7 0.0001504936 +8 ropt_net_204:8 0.0001504936 +9 ropt_net_204:9 0.0001214195 +10 ropt_net_204:10 0.0001214195 +11 ropt_net_204:8 ropt_net_193:9 5.750457e-06 +12 ropt_net_204:6 ropt_net_193:10 5.002812e-05 +13 ropt_net_204:7 ropt_net_193:8 5.750457e-06 +14 ropt_net_204:5 ropt_net_193:11 5.002812e-05 + +*RES +0 ropt_mt_inst_775:X ropt_net_204:10 0.152 +1 ropt_net_204:10 ropt_net_204:9 0.001332589 +2 ropt_net_204:9 ropt_net_204:8 0.0045 +3 ropt_net_204:8 ropt_net_204:7 0.002348215 +4 ropt_net_204:6 ropt_net_204:5 0.002794643 +5 ropt_net_204:7 ropt_net_204:6 0.0045 +6 ropt_net_204:5 ropt_net_204:4 0.0045 +7 ropt_net_204:4 ropt_net_204:3 0.0005267857 +8 ropt_net_204:2 ropt_mt_inst_807:A 0.152 +9 ropt_net_204:3 ropt_net_204:2 0.0045 + +*END + +*D_NET ropt_net_207 0.001016971 //LENGTH 8.270 LUMPCC 0.0001999702 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 72.415 102.340 +*I ropt_mt_inst_810:A I *L 0.001767 *C 70.655 104.720 +*N ropt_net_207:2 *C 70.693 104.720 +*N ropt_net_207:3 *C 71.300 104.720 +*N ropt_net_207:4 *C 71.300 105.060 +*N ropt_net_207:5 *C 71.760 105.060 +*N ropt_net_207:6 *C 71.760 105.400 +*N ropt_net_207:7 *C 71.345 105.400 +*N ropt_net_207:8 *C 71.300 105.355 +*N ropt_net_207:9 *C 71.300 102.385 +*N ropt_net_207:10 *C 71.345 102.340 +*N ropt_net_207:11 *C 72.377 102.340 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 ropt_mt_inst_810:A 1e-06 +2 ropt_net_207:2 4.822083e-05 +3 ropt_net_207:3 7.286781e-05 +4 ropt_net_207:4 6.348414e-05 +5 ropt_net_207:5 6.446969e-05 +6 ropt_net_207:6 7.20832e-05 +7 ropt_net_207:7 4.645068e-05 +8 ropt_net_207:8 0.0001262723 +9 ropt_net_207:9 0.0001262723 +10 ropt_net_207:10 9.744005e-05 +11 ropt_net_207:11 9.744005e-05 +12 ropt_net_207:9 chany_top_out[2]:4 4.381548e-05 +13 ropt_net_207:7 chany_top_out[2]:5 7.070533e-07 +14 ropt_net_207:8 chany_top_out[2]:3 4.381548e-05 +15 ropt_net_207:2 chany_top_out[2]:5 3.022021e-06 +16 ropt_net_207:2 chany_top_out[2]:3 5.886763e-06 +17 ropt_net_207:3 chany_top_out[2]:6 3.022021e-06 +18 ropt_net_207:3 chany_top_out[2]:2 5.886763e-06 +19 ropt_net_207:4 chany_top_out[2]:5 2.810356e-06 +20 ropt_net_207:5 chany_top_out[2]:6 2.810356e-06 +21 ropt_net_207:6 chany_top_out[2]:6 7.070533e-07 +22 ropt_net_207:11 chany_top_out[13]:4 6.166365e-06 +23 ropt_net_207:10 chany_top_out[13]:3 6.166365e-06 +24 ropt_net_207:9 chany_top_out[13]:2 3.757706e-05 +25 ropt_net_207:8 chany_top_out[13] 3.757706e-05 + +*RES +0 ropt_mt_inst_778:X ropt_net_207:11 0.152 +1 ropt_net_207:11 ropt_net_207:10 0.0009218751 +2 ropt_net_207:10 ropt_net_207:9 0.0045 +3 ropt_net_207:9 ropt_net_207:8 0.002651786 +4 ropt_net_207:7 ropt_net_207:6 0.0003705357 +5 ropt_net_207:8 ropt_net_207:7 0.0045 +6 ropt_net_207:2 ropt_mt_inst_810:A 0.152 +7 ropt_net_207:3 ropt_net_207:2 0.0005424108 +8 ropt_net_207:4 ropt_net_207:3 0.0003035715 +9 ropt_net_207:5 ropt_net_207:4 0.0004107143 +10 ropt_net_207:6 ropt_net_207:5 0.0003035715 + +*END + +*D_NET ropt_net_203 0.001348553 //LENGTH 9.465 LUMPCC 0.0002615622 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 70.115 99.960 +*I ropt_mt_inst_806:A I *L 0.001767 *C 66.240 104.720 +*N ropt_net_203:2 *C 66.240 104.720 +*N ropt_net_203:3 *C 66.240 104.380 +*N ropt_net_203:4 *C 69.875 104.380 +*N ropt_net_203:5 *C 69.920 104.335 +*N ropt_net_203:6 *C 69.920 100.005 +*N ropt_net_203:7 *C 69.920 99.960 +*N ropt_net_203:8 *C 70.115 99.960 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 ropt_mt_inst_806:A 1e-06 +2 ropt_net_203:2 5.772966e-05 +3 ropt_net_203:3 0.0002999496 +4 ropt_net_203:4 0.0002716521 +5 ropt_net_203:5 0.0001709441 +6 ropt_net_203:6 0.0001709441 +7 ropt_net_203:7 5.864284e-05 +8 ropt_net_203:8 5.512898e-05 +9 ropt_net_203:6 chany_top_in[6]:5 0.0001307811 +10 ropt_net_203:5 chany_top_in[6] 0.0001307811 + +*RES +0 ropt_mt_inst_781:X ropt_net_203:8 0.152 +1 ropt_net_203:8 ropt_net_203:7 0.0001059783 +2 ropt_net_203:7 ropt_net_203:6 0.0045 +3 ropt_net_203:6 ropt_net_203:5 0.003866072 +4 ropt_net_203:4 ropt_net_203:3 0.003245536 +5 ropt_net_203:5 ropt_net_203:4 0.0045 +6 ropt_net_203:2 ropt_mt_inst_806:A 0.152 +7 ropt_net_203:3 ropt_net_203:2 0.0003035715 + +*END + +*D_NET BUF_net_47 0.002289545 //LENGTH 18.310 LUMPCC 0.0007845308 DR + +*CONN +*I BUFT_RR_47:X O *L 0 *C 27.140 86.360 +*I BUFT_P_117:A I *L 0.001766 *C 25.760 96.560 +*N BUF_net_47:2 *C 25.798 96.560 +*N BUF_net_47:3 *C 28.520 96.560 +*N BUF_net_47:4 *C 28.520 95.880 +*N BUF_net_47:5 *C 29.855 95.880 +*N BUF_net_47:6 *C 29.900 95.835 +*N BUF_net_47:7 *C 29.900 86.405 +*N BUF_net_47:8 *C 29.855 86.360 +*N BUF_net_47:9 *C 27.178 86.360 + +*CAP +0 BUFT_RR_47:X 1e-06 +1 BUFT_P_117:A 1e-06 +2 BUF_net_47:2 0.0001683372 +3 BUF_net_47:3 0.0002141623 +4 BUF_net_47:4 0.000139821 +5 BUF_net_47:5 9.399584e-05 +6 BUF_net_47:6 0.0002419448 +7 BUF_net_47:7 0.0002419448 +8 BUF_net_47:8 0.000201404 +9 BUF_net_47:9 0.000201404 +10 BUF_net_47:5 chany_bottom_in[11]:5 1.248703e-05 +11 BUF_net_47:6 chany_bottom_in[11]:6 0.000265544 +12 BUF_net_47:7 chany_bottom_in[11]:7 0.000265544 +13 BUF_net_47:4 chany_bottom_in[11]:4 1.248703e-05 +14 BUF_net_47:6 chany_bottom_in[12]:10 2.326398e-06 +15 BUF_net_47:6 chany_bottom_in[12]:12 0.000111908 +16 BUF_net_47:7 chany_bottom_in[12]:11 2.326398e-06 +17 BUF_net_47:7 chany_bottom_in[12]:13 0.000111908 + +*RES +0 BUFT_RR_47:X BUF_net_47:9 0.152 +1 BUF_net_47:2 BUFT_P_117:A 0.152 +2 BUF_net_47:5 BUF_net_47:4 0.001191964 +3 BUF_net_47:6 BUF_net_47:5 0.0045 +4 BUF_net_47:8 BUF_net_47:7 0.0045 +5 BUF_net_47:7 BUF_net_47:6 0.008419643 +6 BUF_net_47:9 BUF_net_47:8 0.002390625 +7 BUF_net_47:3 BUF_net_47:2 0.002430804 +8 BUF_net_47:4 BUF_net_47:3 0.0006071429 + +*END + +*D_NET ropt_net_171 0.001064707 //LENGTH 8.150 LUMPCC 0.0003077768 DR + +*CONN +*I BUFT_RR_53:X O *L 0 *C 37.260 99.960 +*I ropt_mt_inst_775:A I *L 0.001766 *C 44.160 99.280 +*N ropt_net_171:2 *C 44.123 99.280 +*N ropt_net_171:3 *C 40.020 99.280 +*N ropt_net_171:4 *C 40.020 99.960 +*N ropt_net_171:5 *C 37.297 99.960 + +*CAP +0 BUFT_RR_53:X 1e-06 +1 ropt_mt_inst_775:A 1e-06 +2 ropt_net_171:2 0.0001672844 +3 ropt_net_171:3 0.0002038302 +4 ropt_net_171:4 0.0002101805 +5 ropt_net_171:5 0.0001736346 +6 ropt_net_171:2 chany_bottom_in[15]:4 0.0001411595 +7 ropt_net_171:5 chany_bottom_in[15]:3 5.855726e-06 +8 ropt_net_171:4 chany_bottom_in[15]:2 6.873157e-06 +9 ropt_net_171:4 chany_bottom_in[15]:4 5.855726e-06 +10 ropt_net_171:3 chany_bottom_in[15]:3 0.0001480327 + +*RES +0 BUFT_RR_53:X ropt_net_171:5 0.152 +1 ropt_net_171:2 ropt_mt_inst_775:A 0.152 +2 ropt_net_171:5 ropt_net_171:4 0.002430804 +3 ropt_net_171:4 ropt_net_171:3 0.0006071429 +4 ropt_net_171:3 ropt_net_171:2 0.003662947 + +*END + +*D_NET ropt_net_202 0.00118843 //LENGTH 8.435 LUMPCC 0.000551859 DR + +*CONN +*I ropt_mt_inst_787:X O *L 0 *C 33.775 97.240 +*I ropt_mt_inst_805:A I *L 0.001767 *C 31.280 102.000 +*N ropt_net_202:2 *C 31.318 102.000 +*N ropt_net_202:3 *C 33.995 102.000 +*N ropt_net_202:4 *C 34.040 101.955 +*N ropt_net_202:5 *C 34.040 97.285 +*N ropt_net_202:6 *C 34.040 97.240 +*N ropt_net_202:7 *C 33.775 97.240 + +*CAP +0 ropt_mt_inst_787:X 1e-06 +1 ropt_mt_inst_805:A 1e-06 +2 ropt_net_202:2 7.137671e-05 +3 ropt_net_202:3 7.137671e-05 +4 ropt_net_202:4 0.0001874453 +5 ropt_net_202:5 0.0001874453 +6 ropt_net_202:6 5.605951e-05 +7 ropt_net_202:7 6.086763e-05 +8 ropt_net_202:2 chany_bottom_in[12]:9 5.180682e-05 +9 ropt_net_202:3 chany_bottom_in[12]:8 5.180682e-05 +10 ropt_net_202:4 chany_bottom_in[12]:10 9.089818e-06 +11 ropt_net_202:5 chany_bottom_in[12]:11 9.089818e-06 +12 ropt_net_202:4 chany_top_in[1] 9.093643e-05 +13 ropt_net_202:4 chany_top_in[1]:28 1.082265e-05 +14 ropt_net_202:5 chany_top_in[1]:27 1.082265e-05 +15 ropt_net_202:5 chany_top_in[1]:31 9.093643e-05 +16 ropt_net_202:2 ropt_net_181:4 0.0001132738 +17 ropt_net_202:3 ropt_net_181:3 0.0001132738 + +*RES +0 ropt_mt_inst_787:X ropt_net_202:7 0.152 +1 ropt_net_202:2 ropt_mt_inst_805:A 0.152 +2 ropt_net_202:3 ropt_net_202:2 0.002390625 +3 ropt_net_202:4 ropt_net_202:3 0.0045 +4 ropt_net_202:6 ropt_net_202:5 0.0045 +5 ropt_net_202:5 ropt_net_202:4 0.004169643 +6 ropt_net_202:7 ropt_net_202:6 0.0001440218 + +*END + +*D_NET ropt_net_175 0.0008020503 //LENGTH 7.410 LUMPCC 0.0001536394 DR + +*CONN +*I BUFT_RR_63:X O *L 0 *C 66.700 14.620 +*I ropt_mt_inst_779:A I *L 0.001766 *C 66.240 9.520 +*N ropt_net_175:2 *C 66.278 9.520 +*N ropt_net_175:3 *C 67.115 9.520 +*N ropt_net_175:4 *C 67.160 9.565 +*N ropt_net_175:5 *C 67.160 14.575 +*N ropt_net_175:6 *C 67.115 14.620 +*N ropt_net_175:7 *C 66.737 14.620 + +*CAP +0 BUFT_RR_63:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_175:2 7.074806e-05 +3 ropt_net_175:3 7.074806e-05 +4 ropt_net_175:4 0.0002112154 +5 ropt_net_175:5 0.0002112154 +6 ropt_net_175:6 4.124203e-05 +7 ropt_net_175:7 4.124203e-05 +8 ropt_net_175:5 ropt_net_182:5 7.681968e-05 +9 ropt_net_175:4 ropt_net_182:4 7.681968e-05 + +*RES +0 BUFT_RR_63:X ropt_net_175:7 0.152 +1 ropt_net_175:7 ropt_net_175:6 0.0003370536 +2 ropt_net_175:6 ropt_net_175:5 0.0045 +3 ropt_net_175:5 ropt_net_175:4 0.004473215 +4 ropt_net_175:3 ropt_net_175:2 0.0007477679 +5 ropt_net_175:4 ropt_net_175:3 0.0045 +6 ropt_net_175:2 ropt_mt_inst_779:A 0.152 + +*END + +*D_NET chany_top_out[8] 0.0007062254 //LENGTH 5.775 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 25.760 104.040 +*P chany_top_out[8] O *L 0.7423 *C 23.920 107.510 +*N chany_top_out[8]:2 *C 23.920 104.085 +*N chany_top_out[8]:3 *C 23.965 104.040 +*N chany_top_out[8]:4 *C 25.723 104.040 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 chany_top_out[8] 0.0002079608 +2 chany_top_out[8]:2 0.0002079608 +3 chany_top_out[8]:3 0.0001446519 +4 chany_top_out[8]:4 0.0001446519 + +*RES +0 ropt_mt_inst_802:X chany_top_out[8]:4 0.152 +1 chany_top_out[8]:4 chany_top_out[8]:3 0.001569197 +2 chany_top_out[8]:3 chany_top_out[8]:2 0.0045 +3 chany_top_out[8]:2 chany_top_out[8] 0.003058036 + +*END + +*D_NET chany_top_out[3] 0.0005533469 //LENGTH 4.750 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 11.960 105.400 +*P chany_top_out[3] O *L 0.7423 *C 13.800 107.510 +*N chany_top_out[3]:2 *C 13.800 107.145 +*N chany_top_out[3]:3 *C 13.755 107.100 +*N chany_top_out[3]:4 *C 12.005 107.100 +*N chany_top_out[3]:5 *C 11.960 107.055 +*N chany_top_out[3]:6 *C 11.960 105.445 +*N chany_top_out[3]:7 *C 11.960 105.400 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chany_top_out[3] 4.341395e-05 +2 chany_top_out[3]:2 4.341395e-05 +3 chany_top_out[3]:3 0.0001144761 +4 chany_top_out[3]:4 0.0001144761 +5 chany_top_out[3]:5 0.0001032648 +6 chany_top_out[3]:6 0.0001032648 +7 chany_top_out[3]:7 3.003719e-05 + +*RES +0 ropt_mt_inst_804:X chany_top_out[3]:7 0.152 +1 chany_top_out[3]:7 chany_top_out[3]:6 0.0045 +2 chany_top_out[3]:6 chany_top_out[3]:5 0.0014375 +3 chany_top_out[3]:4 chany_top_out[3]:3 0.0015625 +4 chany_top_out[3]:5 chany_top_out[3]:4 0.0045 +5 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +6 chany_top_out[3]:2 chany_top_out[3] 0.0003258929 + +*END + +*D_NET chany_top_out[15] 0.001381041 //LENGTH 10.435 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_807:X O *L 0 *C 50.600 102.680 +*P chany_top_out[15] O *L 0.7423 *C 46.460 107.510 +*N chany_top_out[15]:2 *C 46.460 106.138 +*N chany_top_out[15]:3 *C 46.460 106.073 +*N chany_top_out[15]:4 *C 46.460 105.400 +*N chany_top_out[15]:5 *C 50.133 105.400 +*N chany_top_out[15]:6 *C 50.140 105.343 +*N chany_top_out[15]:7 *C 50.140 102.725 +*N chany_top_out[15]:8 *C 50.185 102.680 +*N chany_top_out[15]:9 *C 50.562 102.680 + +*CAP +0 ropt_mt_inst_807:X 1e-06 +1 chany_top_out[15] 0.000102265 +2 chany_top_out[15]:2 0.000102265 +3 chany_top_out[15]:3 6.949669e-05 +4 chany_top_out[15]:4 0.0003524902 +5 chany_top_out[15]:5 0.0002829935 +6 chany_top_out[15]:6 0.0001774646 +7 chany_top_out[15]:7 0.0001774646 +8 chany_top_out[15]:8 5.780058e-05 +9 chany_top_out[15]:9 5.780058e-05 + +*RES +0 ropt_mt_inst_807:X chany_top_out[15]:9 0.152 +1 chany_top_out[15]:9 chany_top_out[15]:8 0.0003370536 +2 chany_top_out[15]:8 chany_top_out[15]:7 0.0045 +3 chany_top_out[15]:7 chany_top_out[15]:6 0.002337054 +4 chany_top_out[15]:6 chany_top_out[15]:5 0.00341 +5 chany_top_out[15]:5 chany_top_out[15]:4 0.0005753583 +6 chany_top_out[15]:2 chany_top_out[15] 0.001225446 +7 chany_top_out[15]:3 chany_top_out[15]:2 0.00341 +8 chany_top_out[15]:4 chany_top_out[15]:3 0.0001053583 + +*END + +*D_NET right_grid_pin_52_[0] 0.000566841 //LENGTH 5.940 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_809:X O *L 0 *C 78.660 79.560 +*P right_grid_pin_52_[0] O *L 0.7423 *C 83.410 78.880 +*N right_grid_pin_52_[0]:2 *C 78.668 78.880 +*N right_grid_pin_52_[0]:3 *C 78.660 78.938 +*N right_grid_pin_52_[0]:4 *C 78.660 79.515 +*N right_grid_pin_52_[0]:5 *C 78.660 79.560 + +*CAP +0 ropt_mt_inst_809:X 1e-06 +1 right_grid_pin_52_[0] 0.0002189614 +2 right_grid_pin_52_[0]:2 0.0002189614 +3 right_grid_pin_52_[0]:3 4.816343e-05 +4 right_grid_pin_52_[0]:4 4.816343e-05 +5 right_grid_pin_52_[0]:5 3.159137e-05 + +*RES +0 ropt_mt_inst_809:X right_grid_pin_52_[0]:5 0.152 +1 right_grid_pin_52_[0]:3 right_grid_pin_52_[0]:2 0.00341 +2 right_grid_pin_52_[0]:2 right_grid_pin_52_[0] 0.0007429916 +3 right_grid_pin_52_[0]:5 right_grid_pin_52_[0]:4 0.0045 +4 right_grid_pin_52_[0]:4 right_grid_pin_52_[0]:3 0.000515625 + +*END + +*D_NET chany_top_out[6] 0.001108447 //LENGTH 7.940 LUMPCC 0.0003124819 DR + +*CONN +*I ropt_mt_inst_813:X O *L 0 *C 57.960 105.060 +*P chany_top_out[6] O *L 0.7423 *C 52.900 107.475 +*N chany_top_out[6]:2 *C 52.900 105.105 +*N chany_top_out[6]:3 *C 52.945 105.060 +*N chany_top_out[6]:4 *C 57.922 105.060 + +*CAP +0 ropt_mt_inst_813:X 1e-06 +1 chany_top_out[6] 0.0001522167 +2 chany_top_out[6]:2 0.0001522167 +3 chany_top_out[6]:3 0.0002452658 +4 chany_top_out[6]:4 0.0002452658 +5 chany_top_out[6]:3 ropt_net_210:2 4.421708e-05 +6 chany_top_out[6]:4 ropt_net_210:3 4.421708e-05 +7 chany_top_out[6]:3 ropt_net_186:2 0.0001120239 +8 chany_top_out[6]:4 ropt_net_186:3 0.0001120239 + +*RES +0 ropt_mt_inst_813:X chany_top_out[6]:4 0.152 +1 chany_top_out[6]:3 chany_top_out[6]:2 0.0045 +2 chany_top_out[6]:2 chany_top_out[6] 0.002116072 +3 chany_top_out[6]:4 chany_top_out[6]:3 0.004444197 + +*END + +*D_NET chany_bottom_out[10] 0.001142637 //LENGTH 9.080 LUMPCC 0.0001118766 DR + +*CONN +*I ropt_mt_inst_818:X O *L 0 *C 53.960 6.120 +*P chany_bottom_out[10] O *L 0.7423 *C 50.140 1.325 +*N chany_bottom_out[10]:2 *C 50.140 6.075 +*N chany_bottom_out[10]:3 *C 50.185 6.120 +*N chany_bottom_out[10]:4 *C 53.922 6.120 + +*CAP +0 ropt_mt_inst_818:X 1e-06 +1 chany_bottom_out[10] 0.0002462037 +2 chany_bottom_out[10]:2 0.0002462037 +3 chany_bottom_out[10]:3 0.0002686763 +4 chany_bottom_out[10]:4 0.0002686763 +5 chany_bottom_out[10] ropt_net_190:6 5.59383e-05 +6 chany_bottom_out[10]:2 ropt_net_190:7 5.59383e-05 + +*RES +0 ropt_mt_inst_818:X chany_bottom_out[10]:4 0.152 +1 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0045 +2 chany_bottom_out[10]:2 chany_bottom_out[10] 0.004241072 +3 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.003337053 + +*END + +*D_NET chany_top_out[9] 0.001080544 //LENGTH 9.130 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 24.115 99.960 +*P chany_top_out[9] O *L 0.7423 *C 23.000 107.510 +*N chany_top_out[9]:2 *C 23.000 100.005 +*N chany_top_out[9]:3 *C 23.045 99.960 +*N chany_top_out[9]:4 *C 24.078 99.960 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 chany_top_out[9] 0.0004357662 +2 chany_top_out[9]:2 0.0004357662 +3 chany_top_out[9]:3 0.0001040059 +4 chany_top_out[9]:4 0.0001040059 + +*RES +0 ropt_mt_inst_821:X chany_top_out[9]:4 0.152 +1 chany_top_out[9]:4 chany_top_out[9]:3 0.0009218751 +2 chany_top_out[9]:3 chany_top_out[9]:2 0.0045 +3 chany_top_out[9]:2 chany_top_out[9] 0.006700893 + +*END + +*D_NET ropt_net_179 0.0006940181 //LENGTH 6.530 LUMPCC 0 DR + +*CONN +*I BUFT_P_108:X O *L 0 *C 80.960 99.620 +*I ropt_mt_inst_783:A I *L 0.001766 *C 77.740 102.000 +*N ropt_net_179:2 *C 77.778 102.000 +*N ropt_net_179:3 *C 79.535 102.000 +*N ropt_net_179:4 *C 79.580 101.955 +*N ropt_net_179:5 *C 79.580 99.665 +*N ropt_net_179:6 *C 79.625 99.620 +*N ropt_net_179:7 *C 80.922 99.620 + +*CAP +0 BUFT_P_108:X 1e-06 +1 ropt_mt_inst_783:A 1e-06 +2 ropt_net_179:2 0.0001140586 +3 ropt_net_179:3 0.0001140586 +4 ropt_net_179:4 0.00011875 +5 ropt_net_179:5 0.00011875 +6 ropt_net_179:6 0.0001132004 +7 ropt_net_179:7 0.0001132004 + +*RES +0 BUFT_P_108:X ropt_net_179:7 0.152 +1 ropt_net_179:7 ropt_net_179:6 0.001158482 +2 ropt_net_179:6 ropt_net_179:5 0.0045 +3 ropt_net_179:5 ropt_net_179:4 0.002044643 +4 ropt_net_179:3 ropt_net_179:2 0.001569197 +5 ropt_net_179:4 ropt_net_179:3 0.0045 +6 ropt_net_179:2 ropt_mt_inst_783:A 0.152 + +*END + +*D_NET chany_top_out[7] 0.001222642 //LENGTH 10.685 LUMPCC 0 DR + +*CONN +*I BUFT_P_117:X O *L 0 *C 21.890 97.240 +*P chany_top_out[7] O *L 0.7423 *C 22.080 107.475 +*N chany_top_out[7]:2 *C 22.080 97.285 +*N chany_top_out[7]:3 *C 22.080 97.240 +*N chany_top_out[7]:4 *C 21.890 97.240 + +*CAP +0 BUFT_P_117:X 1e-06 +1 chany_top_out[7] 0.000555155 +2 chany_top_out[7]:2 0.000555155 +3 chany_top_out[7]:3 5.581198e-05 +4 chany_top_out[7]:4 5.551967e-05 + +*RES +0 BUFT_P_117:X chany_top_out[7]:4 0.152 +1 chany_top_out[7]:4 chany_top_out[7]:3 0.0001032609 +2 chany_top_out[7]:3 chany_top_out[7]:2 0.0045 +3 chany_top_out[7]:2 chany_top_out[7] 0.009098215 + +*END + +*D_NET chany_bottom_in[5] 0.01751135 //LENGTH 153.025 LUMPCC 0.003582448 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 44.620 1.290 +*I mux_right_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 33.485 74.460 +*I ropt_mt_inst_753:A I *L 0.001766 *C 48.760 99.280 +*N chany_bottom_in[5]:3 *C 48.797 99.280 +*N chany_bottom_in[5]:4 *C 50.095 99.280 +*N chany_bottom_in[5]:5 *C 50.140 99.235 +*N chany_bottom_in[5]:6 *C 50.140 94.565 +*N chany_bottom_in[5]:7 *C 50.185 94.520 +*N chany_bottom_in[5]:8 *C 66.655 94.520 +*N chany_bottom_in[5]:9 *C 66.700 94.475 +*N chany_bottom_in[5]:10 *C 66.700 93.545 +*N chany_bottom_in[5]:11 *C 66.655 93.500 +*N chany_bottom_in[5]:12 *C 64.445 93.500 +*N chany_bottom_in[5]:13 *C 64.400 93.455 +*N chany_bottom_in[5]:14 *C 64.400 74.165 +*N chany_bottom_in[5]:15 *C 64.355 74.120 +*N chany_bottom_in[5]:16 *C 33.523 74.460 +*N chany_bottom_in[5]:17 *C 45.080 74.460 +*N chany_bottom_in[5]:18 *C 45.080 74.120 +*N chany_bottom_in[5]:19 *C 45.080 74.075 +*N chany_bottom_in[5]:20 *C 45.080 59.840 +*N chany_bottom_in[5]:21 *C 44.620 59.840 +*N chany_bottom_in[5]:22 *C 44.620 51.290 + +*CAP +0 chany_bottom_in[5] 0.001901633 +1 mux_right_ipin_0\/mux_l1_in_2_:A1 1e-06 +2 ropt_mt_inst_753:A 1e-06 +3 chany_bottom_in[5]:3 9.705183e-05 +4 chany_bottom_in[5]:4 9.705183e-05 +5 chany_bottom_in[5]:5 0.0002754155 +6 chany_bottom_in[5]:6 0.0002754155 +7 chany_bottom_in[5]:7 0.001045252 +8 chany_bottom_in[5]:8 0.001045252 +9 chany_bottom_in[5]:9 7.01618e-05 +10 chany_bottom_in[5]:10 7.01618e-05 +11 chany_bottom_in[5]:11 0.0001771018 +12 chany_bottom_in[5]:12 0.0001771018 +13 chany_bottom_in[5]:13 0.0006792536 +14 chany_bottom_in[5]:14 0.0006792536 +15 chany_bottom_in[5]:15 0.001136119 +16 chany_bottom_in[5]:16 0.0007799781 +17 chany_bottom_in[5]:17 0.0008100483 +18 chany_bottom_in[5]:18 0.001166189 +19 chany_bottom_in[5]:19 0.0004667797 +20 chany_bottom_in[5]:20 0.0004626562 +21 chany_bottom_in[5]:21 0.0003046318 +22 chany_bottom_in[5]:22 0.002210388 +23 chany_bottom_in[5]:14 chany_bottom_in[7]:7 0.0003094156 +24 chany_bottom_in[5]:13 chany_bottom_in[7]:6 0.0003094156 +25 chany_bottom_in[5] chany_bottom_in[15]:7 0.0004669708 +26 chany_bottom_in[5]:19 chany_bottom_in[15]:6 3.255575e-06 +27 chany_bottom_in[5]:21 chany_bottom_in[15]:6 0.0001243274 +28 chany_bottom_in[5]:20 chany_bottom_in[15]:7 3.255575e-06 +29 chany_bottom_in[5]:22 chany_bottom_in[15]:7 0.0001243274 +30 chany_bottom_in[5]:22 chany_bottom_in[15]:6 0.0004669708 +31 chany_bottom_in[5]:19 chany_top_in[3] 0.0003702442 +32 chany_bottom_in[5]:21 chany_top_in[3]:9 3.11943e-05 +33 chany_bottom_in[5]:20 chany_top_in[3]:10 3.11943e-05 +34 chany_bottom_in[5]:20 chany_top_in[3]:11 0.0003702442 +35 chany_bottom_in[5]:14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001030462 +36 chany_bottom_in[5]:13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001030462 +37 chany_bottom_in[5]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001495369 +38 chany_bottom_in[5]:14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.413667e-06 +39 chany_bottom_in[5]:13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.413667e-06 +40 chany_bottom_in[5]:18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001495369 +41 chany_bottom_in[5]:19 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.378192e-05 +42 chany_bottom_in[5]:20 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.378192e-05 +43 chany_bottom_in[5] ropt_net_165:4 0.000181038 +44 chany_bottom_in[5]:22 ropt_net_165:5 0.000181038 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:22 0.04464286 +1 chany_bottom_in[5]:16 mux_right_ipin_0\/mux_l1_in_2_:A1 0.152 +2 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.0045 +3 chany_bottom_in[5]:14 chany_bottom_in[5]:13 0.01722322 +4 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.001973214 +5 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.0045 +6 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.0045 +7 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.0008303572 +8 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.01470536 +9 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.0045 +10 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.0045 +11 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.004169643 +12 chany_bottom_in[5]:4 chany_bottom_in[5]:3 0.001158482 +13 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.0045 +14 chany_bottom_in[5]:3 ropt_mt_inst_753:A 0.152 +15 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.0003035715 +16 chany_bottom_in[5]:18 chany_bottom_in[5]:15 0.01720982 +17 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.0045 +18 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.0103192 +19 chany_bottom_in[5]:21 chany_bottom_in[5]:20 0.0004107143 +20 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.01270982 +21 chany_bottom_in[5]:22 chany_bottom_in[5]:21 0.007633929 + +*END + +*D_NET chany_top_out[14] 0.0008167085 //LENGTH 5.990 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 47.115 105.400 +*P chany_top_out[14] O *L 0.7423 *C 43.700 107.780 +*N chany_top_out[14]:2 *C 43.700 105.445 +*N chany_top_out[14]:3 *C 43.745 105.400 +*N chany_top_out[14]:4 *C 47.078 105.400 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 chany_top_out[14] 0.0001405183 +2 chany_top_out[14]:2 0.0001405183 +3 chany_top_out[14]:3 0.000267336 +4 chany_top_out[14]:4 0.000267336 + +*RES +0 ropt_mt_inst_796:X chany_top_out[14]:4 0.152 +1 chany_top_out[14]:4 chany_top_out[14]:3 0.002975446 +2 chany_top_out[14]:3 chany_top_out[14]:2 0.0045 +3 chany_top_out[14]:2 chany_top_out[14] 0.00184375 + +*END + +*D_NET chany_bottom_out[12] 0.0009435833 //LENGTH 8.770 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 77.740 3.740 +*P chany_bottom_out[12] O *L 0.7423 *C 72.220 1.290 +*N chany_bottom_out[12]:2 *C 72.220 1.655 +*N chany_bottom_out[12]:3 *C 72.265 1.700 +*N chany_bottom_out[12]:4 *C 77.695 1.700 +*N chany_bottom_out[12]:5 *C 77.740 1.745 +*N chany_bottom_out[12]:6 *C 77.740 3.695 +*N chany_bottom_out[12]:7 *C 77.740 3.740 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chany_bottom_out[12] 3.785219e-05 +2 chany_bottom_out[12]:2 3.785219e-05 +3 chany_bottom_out[12]:3 0.0003052096 +4 chany_bottom_out[12]:4 0.0003052096 +5 chany_bottom_out[12]:5 0.0001142635 +6 chany_bottom_out[12]:6 0.0001142635 +7 chany_bottom_out[12]:7 2.793276e-05 + +*RES +0 ropt_mt_inst_797:X chany_bottom_out[12]:7 0.152 +1 chany_bottom_out[12]:7 chany_bottom_out[12]:6 0.0045 +2 chany_bottom_out[12]:6 chany_bottom_out[12]:5 0.001741072 +3 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.004848214 +4 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0045 +5 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +6 chany_bottom_out[12]:2 chany_bottom_out[12] 0.0003258929 + +*END + +*D_NET ropt_net_213 0.0004149691 //LENGTH 2.650 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 67.815 6.120 +*I ropt_mt_inst_816:A I *L 0.001767 *C 67.620 4.080 +*N ropt_net_213:2 *C 67.620 4.080 +*N ropt_net_213:3 *C 67.620 4.125 +*N ropt_net_213:4 *C 67.620 6.075 +*N ropt_net_213:5 *C 67.620 6.120 +*N ropt_net_213:6 *C 67.815 6.120 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 ropt_mt_inst_816:A 1e-06 +2 ropt_net_213:2 3.415732e-05 +3 ropt_net_213:3 0.0001325777 +4 ropt_net_213:4 0.0001325777 +5 ropt_net_213:5 5.729404e-05 +6 ropt_net_213:6 5.636229e-05 + +*RES +0 ropt_mt_inst_786:X ropt_net_213:6 0.152 +1 ropt_net_213:2 ropt_mt_inst_816:A 0.152 +2 ropt_net_213:3 ropt_net_213:2 0.0045 +3 ropt_net_213:5 ropt_net_213:4 0.0045 +4 ropt_net_213:4 ropt_net_213:3 0.001741071 +5 ropt_net_213:6 ropt_net_213:5 0.0001059783 + +*END + +*D_NET ropt_net_170 0.001279474 //LENGTH 13.265 LUMPCC 0 DR + +*CONN +*I BUFT_RR_58:X O *L 0 *C 71.300 18.020 +*I ropt_mt_inst_774:A I *L 0.001766 *C 75.440 9.520 +*N ropt_net_170:2 *C 75.440 9.520 +*N ropt_net_170:3 *C 75.440 9.565 +*N ropt_net_170:4 *C 75.440 17.975 +*N ropt_net_170:5 *C 75.395 18.020 +*N ropt_net_170:6 *C 71.338 18.020 + +*CAP +0 BUFT_RR_58:X 1e-06 +1 ropt_mt_inst_774:A 1e-06 +2 ropt_net_170:2 3.040004e-05 +3 ropt_net_170:3 0.0003922083 +4 ropt_net_170:4 0.0003922083 +5 ropt_net_170:5 0.0002313286 +6 ropt_net_170:6 0.0002313286 + +*RES +0 BUFT_RR_58:X ropt_net_170:6 0.152 +1 ropt_net_170:2 ropt_mt_inst_774:A 0.152 +2 ropt_net_170:3 ropt_net_170:2 0.0045 +3 ropt_net_170:5 ropt_net_170:4 0.0045 +4 ropt_net_170:4 ropt_net_170:3 0.007508929 +5 ropt_net_170:6 ropt_net_170:5 0.003622768 + +*END + +*D_NET ropt_net_164 0.0026606 //LENGTH 22.090 LUMPCC 0.0007152513 DR + +*CONN +*I BUFT_RR_62:X O *L 0 *C 71.300 22.440 +*I ropt_mt_inst_768:A I *L 0.001766 *C 73.140 6.800 +*N ropt_net_164:2 *C 73.103 6.800 +*N ropt_net_164:3 *C 69.505 6.800 +*N ropt_net_164:4 *C 69.460 6.845 +*N ropt_net_164:5 *C 69.460 22.395 +*N ropt_net_164:6 *C 69.505 22.440 +*N ropt_net_164:7 *C 71.263 22.440 + +*CAP +0 BUFT_RR_62:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_164:2 0.0002651903 +3 ropt_net_164:3 0.0002651903 +4 ropt_net_164:4 0.0005677303 +5 ropt_net_164:5 0.0005677303 +6 ropt_net_164:6 0.0001387536 +7 ropt_net_164:7 0.0001387536 +8 ropt_net_164:5 chany_bottom_in[2]:13 6.883237e-05 +9 ropt_net_164:4 chany_bottom_in[2] 6.883237e-05 +10 ropt_net_164:5 chany_top_in[2]:5 0.0001307957 +11 ropt_net_164:4 chany_top_in[2]:4 0.0001307957 +12 ropt_net_164:5 chany_bottom_out[6]:3 9.046357e-05 +13 ropt_net_164:4 chany_bottom_out[6]:2 9.046357e-05 +14 ropt_net_164:5 ropt_net_209:5 6.753401e-05 +15 ropt_net_164:4 ropt_net_209:4 6.753401e-05 + +*RES +0 BUFT_RR_62:X ropt_net_164:7 0.152 +1 ropt_net_164:7 ropt_net_164:6 0.001569197 +2 ropt_net_164:6 ropt_net_164:5 0.0045 +3 ropt_net_164:5 ropt_net_164:4 0.01388393 +4 ropt_net_164:3 ropt_net_164:2 0.003212054 +5 ropt_net_164:4 ropt_net_164:3 0.0045 +6 ropt_net_164:2 ropt_mt_inst_768:A 0.152 + +*END + +*D_NET chany_bottom_out[17] 0.002389741 //LENGTH 22.470 LUMPCC 0 DR + +*CONN +*I BUFT_RR_73:X O *L 0 *C 17.480 19.720 +*P chany_bottom_out[17] O *L 0.7423 *C 14.720 1.210 +*N chany_bottom_out[17]:2 *C 14.320 19.720 +*N chany_bottom_out[17]:3 *C 14.720 19.713 +*N chany_bottom_out[17]:4 *C 14.720 19.720 +*N chany_bottom_out[17]:5 *C 14.720 19.720 +*N chany_bottom_out[17]:6 *C 14.765 19.720 +*N chany_bottom_out[17]:7 *C 17.443 19.720 + +*CAP +0 BUFT_RR_73:X 1e-06 +1 chany_bottom_out[17] 0.0009452786 +2 chany_bottom_out[17]:2 5.095226e-05 +3 chany_bottom_out[17]:3 0.0009452786 +4 chany_bottom_out[17]:4 5.095226e-05 +5 chany_bottom_out[17]:5 3.399634e-05 +6 chany_bottom_out[17]:6 0.0001811414 +7 chany_bottom_out[17]:7 0.0001811414 + +*RES +0 BUFT_RR_73:X chany_bottom_out[17]:7 0.152 +1 chany_bottom_out[17]:7 chany_bottom_out[17]:6 0.002390625 +2 chany_bottom_out[17]:6 chany_bottom_out[17]:5 0.0045 +3 chany_bottom_out[17]:5 chany_bottom_out[17]:4 0.00341 +4 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.00341 +5 chany_bottom_out[17]:4 chany_bottom_out[17]:2 5.69697e-05 +6 chany_bottom_out[17]:3 chany_bottom_out[17] 0.002898725 + +*END + +*D_NET ropt_net_200 0.001308039 //LENGTH 9.190 LUMPCC 0.0003864287 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 33.260 99.620 +*I ropt_mt_inst_803:A I *L 0.001767 *C 24.840 99.280 +*N ropt_net_200:2 *C 24.863 99.308 +*N ropt_net_200:3 *C 24.875 99.620 +*N ropt_net_200:4 *C 33.223 99.620 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 ropt_mt_inst_803:A 1e-06 +2 ropt_net_200:2 3.306667e-05 +3 ropt_net_200:3 0.000459805 +4 ropt_net_200:4 0.0004267383 +5 ropt_net_200:4 chany_bottom_in[17]:4 0.0001932144 +6 ropt_net_200:3 chany_bottom_in[17]:5 0.0001932144 + +*RES +0 ropt_mt_inst_788:X ropt_net_200:4 0.152 +1 ropt_net_200:4 ropt_net_200:3 0.007453125 +2 ropt_net_200:2 ropt_mt_inst_803:A 0.152 +3 ropt_net_200:3 ropt_net_200:2 0.0002111487 + +*END + +*D_NET ccff_tail[0] 0.0008268071 //LENGTH 7.885 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 4.600 82.960 +*P ccff_tail[0] O *L 0.7423 *C 1.305 78.880 +*N ccff_tail[0]:2 *C 4.593 78.880 +*N ccff_tail[0]:3 *C 4.600 78.938 +*N ccff_tail[0]:4 *C 4.600 82.915 +*N ccff_tail[0]:5 *C 4.600 82.960 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 ccff_tail[0] 0.0001657688 +2 ccff_tail[0]:2 0.0001657688 +3 ccff_tail[0]:3 0.0002316698 +4 ccff_tail[0]:4 0.0002316698 +5 ccff_tail[0]:5 3.092986e-05 + +*RES +0 ropt_mt_inst_814:X ccff_tail[0]:5 0.152 +1 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +2 ccff_tail[0]:2 ccff_tail[0] 0.0005150416 +3 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.003551339 + +*END + +*D_NET ropt_net_182 0.001233169 //LENGTH 10.630 LUMPCC 0.0002513556 DR + +*CONN +*I BUFT_RR_88:X O *L 0 *C 66.700 11.900 +*I ropt_mt_inst_786:A I *L 0.001766 *C 63.940 6.800 +*N ropt_net_182:2 *C 63.978 6.800 +*N ropt_net_182:3 *C 67.575 6.800 +*N ropt_net_182:4 *C 67.620 6.845 +*N ropt_net_182:5 *C 67.620 11.855 +*N ropt_net_182:6 *C 67.575 11.900 +*N ropt_net_182:7 *C 66.737 11.900 + +*CAP +0 BUFT_RR_88:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_182:2 0.0001893924 +3 ropt_net_182:3 0.0001893924 +4 ropt_net_182:4 0.000224414 +5 ropt_net_182:5 0.000224414 +6 ropt_net_182:6 7.61004e-05 +7 ropt_net_182:7 7.61004e-05 +8 ropt_net_182:5 ropt_net_198:8 1.143134e-05 +9 ropt_net_182:3 ropt_net_198:6 3.742678e-05 +10 ropt_net_182:4 ropt_net_198:7 1.143134e-05 +11 ropt_net_182:2 ropt_net_198:5 3.742678e-05 +12 ropt_net_182:5 ropt_net_175:5 7.681968e-05 +13 ropt_net_182:4 ropt_net_175:4 7.681968e-05 + +*RES +0 BUFT_RR_88:X ropt_net_182:7 0.152 +1 ropt_net_182:7 ropt_net_182:6 0.0007477679 +2 ropt_net_182:6 ropt_net_182:5 0.0045 +3 ropt_net_182:5 ropt_net_182:4 0.004473215 +4 ropt_net_182:3 ropt_net_182:2 0.003212054 +5 ropt_net_182:4 ropt_net_182:3 0.0045 +6 ropt_net_182:2 ropt_mt_inst_786:A 0.152 + +*END + +*D_NET ropt_net_147 0.003348667 //LENGTH 29.870 LUMPCC 0.0003281762 DR + +*CONN +*I BUFT_P_110:X O *L 0 *C 62.100 83.640 +*I ropt_mt_inst_751:A I *L 0.001766 *C 54.280 102.000 +*N ropt_net_147:2 *C 54.242 102.000 +*N ropt_net_147:3 *C 52.945 102.000 +*N ropt_net_147:4 *C 52.900 101.955 +*N ropt_net_147:5 *C 52.900 83.685 +*N ropt_net_147:6 *C 52.945 83.640 +*N ropt_net_147:7 *C 62.062 83.640 + +*CAP +0 BUFT_P_110:X 1e-06 +1 ropt_mt_inst_751:A 1e-06 +2 ropt_net_147:2 0.0001246781 +3 ropt_net_147:3 0.0001246781 +4 ropt_net_147:4 0.0008027832 +5 ropt_net_147:5 0.0008027832 +6 ropt_net_147:6 0.0005817839 +7 ropt_net_147:7 0.0005817839 +8 ropt_net_147:5 chany_top_in[4]:19 9.44948e-05 +9 ropt_net_147:4 chany_top_in[4] 9.44948e-05 +10 ropt_net_147:5 ropt_net_189:9 5.468625e-05 +11 ropt_net_147:3 ropt_net_189:6 1.490706e-05 +12 ropt_net_147:4 ropt_net_189:8 5.468625e-05 +13 ropt_net_147:2 ropt_net_189:7 1.490706e-05 + +*RES +0 BUFT_P_110:X ropt_net_147:7 0.152 +1 ropt_net_147:7 ropt_net_147:6 0.008140625 +2 ropt_net_147:6 ropt_net_147:5 0.0045 +3 ropt_net_147:5 ropt_net_147:4 0.0163125 +4 ropt_net_147:3 ropt_net_147:2 0.001158482 +5 ropt_net_147:4 ropt_net_147:3 0.0045 +6 ropt_net_147:2 ropt_mt_inst_751:A 0.152 + +*END + +*D_NET chany_bottom_in[6] 0.01528811 //LENGTH 140.765 LUMPCC 0.0025653 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 5.520 1.210 +*I BUFT_P_110:A I *L 0.001776 *C 59.800 82.960 +*N chany_bottom_in[6]:2 *C 59.800 82.975 +*N chany_bottom_in[6]:3 *C 59.800 83.300 +*N chany_bottom_in[6]:4 *C 59.800 83.255 +*N chany_bottom_in[6]:5 *C 59.800 79.945 +*N chany_bottom_in[6]:6 *C 59.755 79.900 +*N chany_bottom_in[6]:7 *C 30.405 79.900 +*N chany_bottom_in[6]:8 *C 30.360 79.855 +*N chany_bottom_in[6]:9 *C 30.360 72.125 +*N chany_bottom_in[6]:10 *C 30.315 72.080 +*N chany_bottom_in[6]:11 *C 25.805 72.080 +*N chany_bottom_in[6]:12 *C 25.760 72.035 +*N chany_bottom_in[6]:13 *C 25.760 53.765 +*N chany_bottom_in[6]:14 *C 25.715 53.720 +*N chany_bottom_in[6]:15 *C 25.300 53.720 +*N chany_bottom_in[6]:16 *C 25.300 53.675 +*N chany_bottom_in[6]:17 *C 25.300 53.100 +*N chany_bottom_in[6]:18 *C 25.258 53.055 +*N chany_bottom_in[6]:19 *C 25.120 53.047 +*N chany_bottom_in[6]:20 *C 22.435 53.040 +*N chany_bottom_in[6]:21 *C 19.825 53.040 +*N chany_bottom_in[6]:22 *C 19.780 52.995 +*N chany_bottom_in[6]:23 *C 19.780 12.298 +*N chany_bottom_in[6]:24 *C 19.773 12.240 +*N chany_bottom_in[6]:25 *C 5.540 12.240 +*N chany_bottom_in[6]:26 *C 5.520 12.232 + +*CAP +0 chany_bottom_in[6] 0.0005399709 +1 BUFT_P_110:A 1e-06 +2 chany_bottom_in[6]:2 3.780955e-05 +3 chany_bottom_in[6]:3 7.286756e-05 +4 chany_bottom_in[6]:4 0.0001944708 +5 chany_bottom_in[6]:5 0.0001944708 +6 chany_bottom_in[6]:6 0.001121533 +7 chany_bottom_in[6]:7 0.001121533 +8 chany_bottom_in[6]:8 0.0005186388 +9 chany_bottom_in[6]:9 0.0005186388 +10 chany_bottom_in[6]:10 0.0002570984 +11 chany_bottom_in[6]:11 0.0002570984 +12 chany_bottom_in[6]:12 0.000716979 +13 chany_bottom_in[6]:13 0.000716979 +14 chany_bottom_in[6]:14 7.370688e-05 +15 chany_bottom_in[6]:15 0.0001009178 +16 chany_bottom_in[6]:16 2.673684e-05 +17 chany_bottom_in[6]:17 2.673684e-05 +18 chany_bottom_in[6]:18 1.087956e-05 +19 chany_bottom_in[6]:19 0.000141413 +20 chany_bottom_in[6]:20 0.0002681421 +21 chany_bottom_in[6]:21 0.0001376086 +22 chany_bottom_in[6]:22 0.001780441 +23 chany_bottom_in[6]:23 0.001780441 +24 chany_bottom_in[6]:24 0.0007833614 +25 chany_bottom_in[6]:25 0.0007833614 +26 chany_bottom_in[6]:26 0.0005399709 +27 chany_bottom_in[6]:4 chany_bottom_in[0]:8 2.738933e-05 +28 chany_bottom_in[6]:6 chany_bottom_in[0]:5 5.77896e-05 +29 chany_bottom_in[6]:6 chany_bottom_in[0]:10 0.0002514174 +30 chany_bottom_in[6]:5 chany_bottom_in[0]:9 2.738933e-05 +31 chany_bottom_in[6]:7 chany_bottom_in[0]:10 5.77896e-05 +32 chany_bottom_in[6]:7 chany_bottom_in[0]:11 0.0002514174 +33 chany_bottom_in[6]:12 chany_bottom_in[19]:6 0.0002339852 +34 chany_bottom_in[6]:12 chany_bottom_in[19]:7 1.063694e-05 +35 chany_bottom_in[6]:13 chany_bottom_in[19]:8 1.063694e-05 +36 chany_bottom_in[6]:13 chany_bottom_in[19]:7 0.0002339852 +37 chany_bottom_in[6]:16 chany_bottom_in[19]:7 2.752913e-05 +38 chany_bottom_in[6]:17 chany_bottom_in[19]:8 2.752913e-05 +39 chany_bottom_in[6]:6 chany_top_in[11]:10 0.0002548567 +40 chany_bottom_in[6]:6 chany_top_in[11]:9 0.0004190456 +41 chany_bottom_in[6]:7 chany_top_in[11]:9 0.0002548567 +42 chany_bottom_in[6]:7 chany_top_in[11]:4 0.0004190456 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:26 0.001726858 +1 chany_bottom_in[6]:2 BUFT_P_110:A 0.152 +2 chany_bottom_in[6]:3 chany_bottom_in[6]:2 0.0001766305 +3 chany_bottom_in[6]:4 chany_bottom_in[6]:3 0.0045 +4 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.0045 +5 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.002955357 +6 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.02620536 +7 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.0045 +8 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.0045 +9 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.006901786 +10 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.004026785 +11 chany_bottom_in[6]:12 chany_bottom_in[6]:11 0.0045 +12 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.0045 +13 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.0163125 +14 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.0003705357 +15 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.0045 +16 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.0045 +17 chany_bottom_in[6]:17 chany_bottom_in[6]:16 0.0005133929 +18 chany_bottom_in[6]:21 chany_bottom_in[6]:20 0.002330357 +19 chany_bottom_in[6]:22 chany_bottom_in[6]:21 0.0045 +20 chany_bottom_in[6]:23 chany_bottom_in[6]:22 0.03633706 +21 chany_bottom_in[6]:24 chany_bottom_in[6]:23 0.00341 +22 chany_bottom_in[6]:25 chany_bottom_in[6]:24 0.002229758 +23 chany_bottom_in[6]:26 chany_bottom_in[6]:25 0.00341 +24 chany_bottom_in[6]:20 chany_bottom_in[6]:19 0.002397322 +25 chany_bottom_in[6]:19 chany_bottom_in[6]:18 0.0001227679 + +*END + +*D_NET chany_bottom_in[7] 0.01310211 //LENGTH 126.400 LUMPCC 0.002048906 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 69.000 1.210 +*I BUFT_RR_47:A I *L 0.001776 *C 29.440 85.680 +*N chany_bottom_in[7]:2 *C 29.402 85.680 +*N chany_bottom_in[7]:3 *C 28.980 85.680 +*N chany_bottom_in[7]:4 *C 28.980 85.340 +*N chany_bottom_in[7]:5 *C 63.895 85.340 +*N chany_bottom_in[7]:6 *C 63.940 85.295 +*N chany_bottom_in[7]:7 *C 63.940 56.615 +*N chany_bottom_in[7]:8 *C 63.940 6.857 +*N chany_bottom_in[7]:9 *C 63.948 6.800 +*N chany_bottom_in[7]:10 *C 68.980 6.800 +*N chany_bottom_in[7]:11 *C 69.000 6.793 + +*CAP +0 chany_bottom_in[7] 0.0002860233 +1 BUFT_RR_47:A 1e-06 +2 chany_bottom_in[7]:2 4.76222e-05 +3 chany_bottom_in[7]:3 7.520904e-05 +4 chany_bottom_in[7]:4 0.001960658 +5 chany_bottom_in[7]:5 0.001933071 +6 chany_bottom_in[7]:6 0.0009930178 +7 chany_bottom_in[7]:7 0.002942955 +8 chany_bottom_in[7]:8 0.001949937 +9 chany_bottom_in[7]:9 0.0002888432 +10 chany_bottom_in[7]:10 0.0002888432 +11 chany_bottom_in[7]:11 0.0002860233 +12 chany_bottom_in[7]:6 chany_bottom_in[5]:13 0.0003094156 +13 chany_bottom_in[7]:7 chany_bottom_in[5]:14 0.0003094156 +14 chany_bottom_in[7]:6 chany_bottom_in[13]:4 5.497188e-05 +15 chany_bottom_in[7]:6 chany_bottom_in[13]:5 0.0001250161 +16 chany_bottom_in[7]:8 chany_bottom_in[13]:6 0.0002284707 +17 chany_bottom_in[7]:7 chany_bottom_in[13]:6 0.0001250161 +18 chany_bottom_in[7]:7 chany_bottom_in[13]:5 0.0002834426 +19 chany_bottom_in[7]:5 mux_tree_tapbuf_size10_0_sram[3]:7 0.0001955251 +20 chany_bottom_in[7]:4 mux_tree_tapbuf_size10_0_sram[3]:6 0.0001955251 +21 chany_bottom_in[7]:8 ropt_net_167:4 0.0001110537 +22 chany_bottom_in[7]:7 ropt_net_167:5 0.0001110537 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:11 0.0008745916 +1 chany_bottom_in[7]:2 BUFT_RR_47:A 0.152 +2 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.03117411 +3 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.0045 +4 chany_bottom_in[7]:8 chany_bottom_in[7]:7 0.04442634 +5 chany_bottom_in[7]:9 chany_bottom_in[7]:8 0.00341 +6 chany_bottom_in[7]:10 chany_bottom_in[7]:9 0.000788425 +7 chany_bottom_in[7]:11 chany_bottom_in[7]:10 0.00341 +8 chany_bottom_in[7]:4 chany_bottom_in[7]:3 0.0003035715 +9 chany_bottom_in[7]:3 chany_bottom_in[7]:2 0.0003772322 +10 chany_bottom_in[7]:7 chany_bottom_in[7]:6 0.02560715 + +*END + +*D_NET chany_bottom_in[8] 0.009412405 //LENGTH 98.115 LUMPCC 0.004064529 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 22.080 1.210 +*I BUFT_RR_48:A I *L 0.001776 *C 21.160 96.560 +*N chany_bottom_in[8]:2 *C 21.370 95.880 +*N chany_bottom_in[8]:3 *C 21.198 96.560 +*N chany_bottom_in[8]:4 *C 22.035 96.560 +*N chany_bottom_in[8]:5 *C 22.080 96.515 +*N chany_bottom_in[8]:6 *C 22.080 95.938 +*N chany_bottom_in[8]:7 *C 22.078 95.880 +*N chany_bottom_in[8]:8 *C 22.080 95.873 +*N chany_bottom_in[8]:9 *C 22.080 51.210 + +*CAP +0 chany_bottom_in[8] 0.001377068 +1 BUFT_RR_48:A 1e-06 +2 chany_bottom_in[8]:2 6.824243e-05 +3 chany_bottom_in[8]:3 7.121389e-05 +4 chany_bottom_in[8]:4 7.121389e-05 +5 chany_bottom_in[8]:5 5.276546e-05 +6 chany_bottom_in[8]:6 5.276546e-05 +7 chany_bottom_in[8]:7 6.824243e-05 +8 chany_bottom_in[8]:8 0.001104148 +9 chany_bottom_in[8]:9 0.002481216 +10 chany_bottom_in[8] chany_bottom_in[13] 0.0005852226 +11 chany_bottom_in[8]:9 chany_bottom_in[13]:9 0.0005852226 +12 chany_bottom_in[8] chany_top_in[18]:14 0.0003825247 +13 chany_bottom_in[8]:8 chany_top_in[18] 0.0002601113 +14 chany_bottom_in[8]:8 chany_top_in[18]:15 0.0008044058 +15 chany_bottom_in[8]:9 chany_top_in[18]:14 0.0008044058 +16 chany_bottom_in[8]:9 chany_top_in[18]:15 0.000642636 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:9 0.007833333 +1 chany_bottom_in[8]:3 BUFT_RR_48:A 0.152 +2 chany_bottom_in[8]:4 chany_bottom_in[8]:3 0.0007477679 +3 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.0045 +4 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.000515625 +5 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.00341 +6 chany_bottom_in[8]:7 chany_bottom_in[8]:2 0.0001039141 +7 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.00341 +8 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.006997124 + +*END + +*D_NET chany_bottom_in[16] 0.0143636 //LENGTH 124.760 LUMPCC 0.004547332 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 48.300 1.290 +*I ropt_mt_inst_750:A I *L 0.001767 *C 38.640 104.720 +*I mux_left_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 53.995 53.380 +*N chany_bottom_in[16]:3 *C 53.958 53.380 +*N chany_bottom_in[16]:4 *C 52.945 53.380 +*N chany_bottom_in[16]:5 *C 52.900 53.335 +*N chany_bottom_in[16]:6 *C 52.900 50.025 +*N chany_bottom_in[16]:7 *C 52.855 49.980 +*N chany_bottom_in[16]:8 *C 38.678 104.720 +*N chany_bottom_in[16]:9 *C 41.815 104.720 +*N chany_bottom_in[16]:10 *C 41.860 104.675 +*N chany_bottom_in[16]:11 *C 41.860 51.045 +*N chany_bottom_in[16]:12 *C 41.905 51.000 +*N chany_bottom_in[16]:13 *C 43.120 51.000 +*N chany_bottom_in[16]:14 *C 43.233 50.955 +*N chany_bottom_in[16]:15 *C 43.240 50.365 +*N chany_bottom_in[16]:16 *C 43.285 50.320 +*N chany_bottom_in[16]:17 *C 45.540 50.320 +*N chany_bottom_in[16]:18 *C 45.540 49.980 +*N chany_bottom_in[16]:19 *C 48.300 49.980 +*N chany_bottom_in[16]:20 *C 48.300 49.935 + +*CAP +0 chany_bottom_in[16] 0.001748939 +1 ropt_mt_inst_750:A 1e-06 +2 mux_left_ipin_0\/mux_l2_in_2_:A0 1e-06 +3 chany_bottom_in[16]:3 5.99082e-05 +4 chany_bottom_in[16]:4 5.99082e-05 +5 chany_bottom_in[16]:5 0.0001791228 +6 chany_bottom_in[16]:6 0.0001791228 +7 chany_bottom_in[16]:7 0.0002606804 +8 chany_bottom_in[16]:8 0.0002748696 +9 chany_bottom_in[16]:9 0.0002748696 +10 chany_bottom_in[16]:10 0.001878215 +11 chany_bottom_in[16]:11 0.001878215 +12 chany_bottom_in[16]:12 0.0001044855 +13 chany_bottom_in[16]:13 0.0001044855 +14 chany_bottom_in[16]:14 6.457959e-05 +15 chany_bottom_in[16]:15 6.457959e-05 +16 chany_bottom_in[16]:16 0.0001518087 +17 chany_bottom_in[16]:17 0.0001727501 +18 chany_bottom_in[16]:18 0.000171214 +19 chany_bottom_in[16]:19 0.0004375759 +20 chany_bottom_in[16]:20 0.001748939 +21 chany_bottom_in[16] chany_bottom_in[3] 0.0002784226 +22 chany_bottom_in[16]:20 chany_bottom_in[3]:20 0.0002784226 +23 chany_bottom_in[16] chany_top_in[10]:12 4.157621e-06 +24 chany_bottom_in[16]:20 chany_top_in[10]:13 4.157621e-06 +25 chany_bottom_in[16]:4 chany_top_in[10]:14 2.447824e-05 +26 chany_bottom_in[16]:3 chany_top_in[10]:3 2.447824e-05 +27 chany_bottom_in[16]:11 chany_top_in[10]:16 0.000619227 +28 chany_bottom_in[16]:10 chany_top_in[10] 0.000619227 +29 chany_bottom_in[16]:11 chany_top_in[11]:7 0.000793967 +30 chany_bottom_in[16]:10 chany_top_in[11]:8 0.000793967 +31 chany_bottom_in[16] chany_top_in[15]:8 0.0004564476 +32 chany_bottom_in[16]:20 chany_top_in[15]:9 0.0004564476 +33 chany_bottom_in[16] ropt_net_216:5 9.696596e-05 +34 chany_bottom_in[16]:20 ropt_net_216:4 9.696596e-05 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:20 0.04343304 +1 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.002464286 +2 chany_bottom_in[16]:19 chany_bottom_in[16]:7 0.004066964 +3 chany_bottom_in[16]:20 chany_bottom_in[16]:19 0.0045 +4 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.0045 +5 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.002955357 +6 chany_bottom_in[16]:4 chany_bottom_in[16]:3 0.0009040179 +7 chany_bottom_in[16]:5 chany_bottom_in[16]:4 0.0045 +8 chany_bottom_in[16]:3 mux_left_ipin_0\/mux_l2_in_2_:A0 0.152 +9 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.0045 +10 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.0005267857 +11 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.001084822 +12 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.0045 +13 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.0045 +14 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.04788394 +15 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.00280134 +16 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.0045 +17 chany_bottom_in[16]:8 ropt_mt_inst_750:A 0.152 +18 chany_bottom_in[16]:17 chany_bottom_in[16]:16 0.002013393 +19 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.0003035715 + +*END + +*D_NET chany_bottom_in[18] 0.01585999 //LENGTH 127.175 LUMPCC 0.008177137 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 47.840 1.210 +*I ropt_mt_inst_756:A I *L 0.001766 *C 29.440 104.720 +*N chany_bottom_in[18]:2 *C 29.440 104.720 +*N chany_bottom_in[18]:3 *C 29.440 104.765 +*N chany_bottom_in[18]:4 *C 29.440 105.355 +*N chany_bottom_in[18]:5 *C 29.485 105.400 +*N chany_bottom_in[18]:6 *C 39.560 105.400 +*N chany_bottom_in[18]:7 *C 39.560 105.060 +*N chany_bottom_in[18]:8 *C 43.700 105.060 +*N chany_bottom_in[18]:9 *C 43.700 104.380 +*N chany_bottom_in[18]:10 *C 48.715 104.380 +*N chany_bottom_in[18]:11 *C 48.760 104.335 +*N chany_bottom_in[18]:12 *C 48.760 65.338 +*N chany_bottom_in[18]:13 *C 48.753 65.280 +*N chany_bottom_in[18]:14 *C 47.860 65.280 +*N chany_bottom_in[18]:15 *C 47.840 65.273 +*N chany_bottom_in[18]:16 *C 47.840 51.210 + +*CAP +0 chany_bottom_in[18] 0.0008776809 +1 ropt_mt_inst_756:A 1e-06 +2 chany_bottom_in[18]:2 3.691652e-05 +3 chany_bottom_in[18]:3 6.615982e-05 +4 chany_bottom_in[18]:4 6.615982e-05 +5 chany_bottom_in[18]:5 0.0006875094 +6 chany_bottom_in[18]:6 0.0007116232 +7 chany_bottom_in[18]:7 0.0003139387 +8 chany_bottom_in[18]:8 0.0003380015 +9 chany_bottom_in[18]:9 0.000305004 +10 chany_bottom_in[18]:10 0.0002568275 +11 chany_bottom_in[18]:11 0.001366337 +12 chany_bottom_in[18]:12 0.001366337 +13 chany_bottom_in[18]:13 7.87881e-05 +14 chany_bottom_in[18]:14 7.87881e-05 +15 chany_bottom_in[18]:15 0.0001270524 +16 chany_bottom_in[18]:16 0.001004733 +17 chany_bottom_in[18] chany_bottom_in[15] 0.0003915049 +18 chany_bottom_in[18]:16 chany_bottom_in[15]:10 0.0003915049 +19 chany_bottom_in[18]:11 chany_top_in[11] 0.0006876033 +20 chany_bottom_in[18]:12 chany_top_in[11]:11 0.0006876033 +21 chany_bottom_in[18] chany_top_in[13]:15 0.0009634899 +22 chany_bottom_in[18]:11 chany_top_in[13] 5.98971e-05 +23 chany_bottom_in[18]:12 chany_top_in[13]:16 5.98971e-05 +24 chany_bottom_in[18]:15 chany_top_in[13] 0.0001385058 +25 chany_bottom_in[18]:15 chany_top_in[13]:16 0.0002040746 +26 chany_bottom_in[18]:16 chany_top_in[13]:15 0.0002040746 +27 chany_bottom_in[18]:16 chany_top_in[13]:16 0.001101996 +28 chany_bottom_in[18] chany_top_in[14]:18 0.0007138705 +29 chany_bottom_in[18]:15 chany_top_in[14]:19 0.0003425804 +30 chany_bottom_in[18]:16 chany_top_in[14]:18 0.0003425804 +31 chany_bottom_in[18]:16 chany_top_in[14]:19 0.0007138705 +32 chany_bottom_in[18]:11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001588873 +33 chany_bottom_in[18]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001588873 +34 chany_bottom_in[18]:10 ropt_net_193:7 0.0001552417 +35 chany_bottom_in[18]:7 ropt_net_193:3 4.355253e-05 +36 chany_bottom_in[18]:7 ropt_net_193:6 1.959618e-06 +37 chany_bottom_in[18]:8 ropt_net_193:2 4.355253e-05 +38 chany_bottom_in[18]:8 ropt_net_193:7 1.959618e-06 +39 chany_bottom_in[18]:9 ropt_net_193:6 0.0001552417 +40 chany_bottom_in[18]:10 ropt_net_189:3 3.480366e-05 +41 chany_bottom_in[18]:11 ropt_net_189:4 7.919499e-05 +42 chany_bottom_in[18]:11 ropt_net_189:8 5.193722e-07 +43 chany_bottom_in[18]:12 ropt_net_189:5 7.919499e-05 +44 chany_bottom_in[18]:12 ropt_net_189:9 5.193722e-07 +45 chany_bottom_in[18]:9 ropt_net_189:2 3.480366e-05 +46 chany_bottom_in[18]:5 ropt_net_192:3 0.000112883 +47 chany_bottom_in[18]:6 ropt_net_192:4 0.000112883 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:16 0.007833333 +1 chany_bottom_in[18]:2 ropt_mt_inst_756:A 0.152 +2 chany_bottom_in[18]:3 chany_bottom_in[18]:2 0.0045 +3 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.0045 +4 chany_bottom_in[18]:4 chany_bottom_in[18]:3 0.0005267857 +5 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.004477679 +6 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.0045 +7 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.0348192 +8 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.00341 +9 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.000139825 +10 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.00341 +11 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.008995536 +12 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.0003035715 +13 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.003696429 +14 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.000607143 +15 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.002203125 + +*END + +*D_NET chany_top_in[0] 0.01386062 //LENGTH 120.085 LUMPCC 0.003066668 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 50.140 107.475 +*I BUFT_RR_88:A I *L 0.001776 *C 69.000 12.240 +*I mux_left_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 70.210 80.920 +*N chany_top_in[0]:3 *C 70.210 80.920 +*N chany_top_in[0]:4 *C 69.520 77.520 +*N chany_top_in[0]:5 *C 69.210 12.240 +*N chany_top_in[0]:6 *C 69.038 12.240 +*N chany_top_in[0]:7 *C 69.875 12.240 +*N chany_top_in[0]:8 *C 69.920 12.240 +*N chany_top_in[0]:9 *C 69.918 12.240 +*N chany_top_in[0]:10 *C 69.920 12.248 +*N chany_top_in[0]:11 *C 69.920 62.075 +*N chany_top_in[0]:12 *C 69.920 77.513 +*N chany_top_in[0]:13 *C 69.920 77.520 +*N chany_top_in[0]:14 *C 69.920 77.578 +*N chany_top_in[0]:15 *C 69.920 80.875 +*N chany_top_in[0]:16 *C 69.875 80.920 +*N chany_top_in[0]:17 *C 56.165 80.920 +*N chany_top_in[0]:18 *C 56.120 80.965 +*N chany_top_in[0]:19 *C 56.120 106.715 +*N chany_top_in[0]:20 *C 56.075 106.760 +*N chany_top_in[0]:21 *C 50.185 106.760 +*N chany_top_in[0]:22 *C 50.140 106.805 + +*CAP +0 chany_top_in[0] 5.789742e-05 +1 BUFT_RR_88:A 1e-06 +2 mux_left_ipin_0\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[0]:3 6.28316e-05 +4 chany_top_in[0]:4 6.689557e-05 +5 chany_top_in[0]:5 7.666265e-05 +6 chany_top_in[0]:6 7.212808e-05 +7 chany_top_in[0]:7 7.212808e-05 +8 chany_top_in[0]:8 3.144872e-05 +9 chany_top_in[0]:9 7.666265e-05 +10 chany_top_in[0]:10 0.002067161 +11 chany_top_in[0]:11 0.002708797 +12 chany_top_in[0]:12 0.0006416362 +13 chany_top_in[0]:13 6.689557e-05 +14 chany_top_in[0]:14 0.0002340366 +15 chany_top_in[0]:15 0.0002340366 +16 chany_top_in[0]:16 0.0007236666 +17 chany_top_in[0]:17 0.0007015819 +18 chany_top_in[0]:18 0.0009781453 +19 chany_top_in[0]:19 0.0009781453 +20 chany_top_in[0]:20 0.0004416479 +21 chany_top_in[0]:21 0.0004416479 +22 chany_top_in[0]:22 5.789742e-05 +23 chany_top_in[0]:16 chany_bottom_in[0]:3 1.863092e-06 +24 chany_top_in[0]:16 chany_bottom_in[0]:5 0.0001909004 +25 chany_top_in[0]:16 chany_bottom_in[0]:10 4.402488e-05 +26 chany_top_in[0]:15 chany_bottom_in[0]:5 5.84729e-06 +27 chany_top_in[0]:14 chany_bottom_in[0]:4 5.84729e-06 +28 chany_top_in[0]:17 chany_bottom_in[0]:4 1.863092e-06 +29 chany_top_in[0]:17 chany_bottom_in[0]:10 0.0001909004 +30 chany_top_in[0]:17 chany_bottom_in[0]:11 4.402488e-05 +31 chany_top_in[0]:18 chany_bottom_in[0]:9 5.994789e-05 +32 chany_top_in[0]:19 chany_bottom_in[0]:8 5.994789e-05 +33 chany_top_in[0]:12 chany_top_in[8]:9 5.093136e-05 +34 chany_top_in[0]:12 chany_top_in[8]:8 0.0001892026 +35 chany_top_in[0]:10 chany_top_in[8]:7 0.000624198 +36 chany_top_in[0]:11 chany_top_in[8]:7 0.0001892026 +37 chany_top_in[0]:11 chany_top_in[8]:8 0.0006751294 +38 chany_top_in[0]:18 chany_top_in[16]:18 0.0003064907 +39 chany_top_in[0]:19 chany_top_in[16]:19 0.0003064907 +40 chany_top_in[0]:18 ropt_net_186:5 5.992796e-05 +41 chany_top_in[0]:19 ropt_net_186:4 5.992796e-05 + +*RES +0 chany_top_in[0] chany_top_in[0]:22 0.0005982143 +1 chany_top_in[0]:16 chany_top_in[0]:15 0.0045 +2 chany_top_in[0]:16 chany_top_in[0]:3 0.0001820652 +3 chany_top_in[0]:15 chany_top_in[0]:14 0.002944197 +4 chany_top_in[0]:14 chany_top_in[0]:13 0.00341 +5 chany_top_in[0]:13 chany_top_in[0]:12 0.00341 +6 chany_top_in[0]:13 chany_top_in[0]:4 5.69697e-05 +7 chany_top_in[0]:12 chany_top_in[0]:11 0.002418542 +8 chany_top_in[0]:9 chany_top_in[0]:8 0.00341 +9 chany_top_in[0]:9 chany_top_in[0]:5 0.0001039141 +10 chany_top_in[0]:10 chany_top_in[0]:9 0.00341 +11 chany_top_in[0]:8 chany_top_in[0]:7 0.0045 +12 chany_top_in[0]:7 chany_top_in[0]:6 0.0007477679 +13 chany_top_in[0]:6 BUFT_RR_88:A 0.152 +14 chany_top_in[0]:17 chany_top_in[0]:16 0.01224107 +15 chany_top_in[0]:18 chany_top_in[0]:17 0.0045 +16 chany_top_in[0]:20 chany_top_in[0]:19 0.0045 +17 chany_top_in[0]:19 chany_top_in[0]:18 0.02299107 +18 chany_top_in[0]:21 chany_top_in[0]:20 0.005258929 +19 chany_top_in[0]:22 chany_top_in[0]:21 0.0045 +20 chany_top_in[0]:3 mux_left_ipin_0\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[0]:11 chany_top_in[0]:10 0.007806308 + +*END + +*D_NET chany_top_in[2] 0.01145391 //LENGTH 95.215 LUMPCC 0.005578705 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 66.700 107.510 +*I mux_left_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.370 86.020 +*I BUFT_RR_58:A I *L 0.001776 *C 69.000 17.680 +*N chany_top_in[2]:3 *C 69.000 17.680 +*N chany_top_in[2]:4 *C 69.000 17.725 +*N chany_top_in[2]:5 *C 69.000 67.520 +*N chany_top_in[2]:6 *C 68.407 86.020 +*N chany_top_in[2]:7 *C 68.955 86.020 +*N chany_top_in[2]:8 *C 69.000 86.020 +*N chany_top_in[2]:9 *C 69.460 86.020 +*N chany_top_in[2]:10 *C 69.460 96.175 +*N chany_top_in[2]:11 *C 69.415 96.220 +*N chany_top_in[2]:12 *C 66.745 96.220 +*N chany_top_in[2]:13 *C 66.700 96.265 + +*CAP +0 chany_top_in[2] 0.0005923891 +1 mux_left_ipin_0\/mux_l1_in_1_:A0 1e-06 +2 BUFT_RR_58:A 1e-06 +3 chany_top_in[2]:3 3.223086e-05 +4 chany_top_in[2]:4 0.001208107 +5 chany_top_in[2]:5 0.001773623 +6 chany_top_in[2]:6 7.071471e-05 +7 chany_top_in[2]:7 7.071471e-05 +8 chany_top_in[2]:8 0.0005945616 +9 chany_top_in[2]:9 0.0003171148 +10 chany_top_in[2]:10 0.0002880695 +11 chany_top_in[2]:11 0.0001666485 +12 chany_top_in[2]:12 0.0001666485 +13 chany_top_in[2]:13 0.0005923891 +14 chany_top_in[2]:4 chany_top_in[6]:4 0.0003903603 +15 chany_top_in[2]:8 chany_top_in[6] 5.696461e-05 +16 chany_top_in[2]:8 chany_top_in[6]:5 4.231965e-05 +17 chany_top_in[2]:10 chany_top_in[6] 0.0001477254 +18 chany_top_in[2]:9 chany_top_in[6]:5 0.0001477254 +19 chany_top_in[2]:5 chany_top_in[6]:4 4.231965e-05 +20 chany_top_in[2]:5 chany_top_in[6]:5 0.0004473249 +21 chany_top_in[2]:4 chany_top_in[7]:5 0.001319734 +22 chany_top_in[2]:4 chany_top_in[7]:6 6.481398e-05 +23 chany_top_in[2]:8 chany_top_in[7] 0.000505155 +24 chany_top_in[2]:10 chany_top_in[7] 0.0001314831 +25 chany_top_in[2]:9 chany_top_in[7]:6 0.0001314831 +26 chany_top_in[2]:5 chany_top_in[7] 6.481398e-05 +27 chany_top_in[2]:5 chany_top_in[7]:6 0.001824889 +28 chany_top_in[2]:4 ropt_net_164:4 0.0001307957 +29 chany_top_in[2]:5 ropt_net_164:5 0.0001307957 + +*RES +0 chany_top_in[2] chany_top_in[2]:13 0.01004018 +1 chany_top_in[2]:3 BUFT_RR_58:A 0.152 +2 chany_top_in[2]:4 chany_top_in[2]:3 0.0045 +3 chany_top_in[2]:7 chany_top_in[2]:6 0.0004888393 +4 chany_top_in[2]:8 chany_top_in[2]:7 0.0045 +5 chany_top_in[2]:8 chany_top_in[2]:5 0.01651786 +6 chany_top_in[2]:6 mux_left_ipin_0\/mux_l1_in_1_:A0 0.152 +7 chany_top_in[2]:11 chany_top_in[2]:10 0.0045 +8 chany_top_in[2]:10 chany_top_in[2]:9 0.009066965 +9 chany_top_in[2]:12 chany_top_in[2]:11 0.002383929 +10 chany_top_in[2]:13 chany_top_in[2]:12 0.0045 +11 chany_top_in[2]:9 chany_top_in[2]:8 0.0004107143 +12 chany_top_in[2]:5 chany_top_in[2]:4 0.04445983 + +*END + +*D_NET chany_top_in[3] 0.01151061 //LENGTH 97.580 LUMPCC 0.005165036 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 44.620 107.510 +*I BUFT_RR_59:A I *L 0.001776 *C 43.700 23.120 +*I mux_right_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 35.710 60.520 +*N chany_top_in[3]:3 *C 35.748 60.520 +*N chany_top_in[3]:4 *C 43.663 23.120 +*N chany_top_in[3]:5 *C 40.985 23.120 +*N chany_top_in[3]:6 *C 40.940 23.165 +*N chany_top_in[3]:7 *C 40.940 60.475 +*N chany_top_in[3]:8 *C 40.940 60.550 +*N chany_top_in[3]:9 *C 40.940 60.860 +*N chany_top_in[3]:10 *C 44.575 60.860 +*N chany_top_in[3]:11 *C 44.620 60.905 + +*CAP +0 chany_top_in[3] 0.001489623 +1 BUFT_RR_59:A 1e-06 +2 mux_right_ipin_0\/mux_l1_in_1_:A0 1e-06 +3 chany_top_in[3]:3 0.0003546256 +4 chany_top_in[3]:4 0.0001693295 +5 chany_top_in[3]:5 0.0001693295 +6 chany_top_in[3]:6 0.0009224146 +7 chany_top_in[3]:7 0.0009224146 +8 chany_top_in[3]:8 0.0003850347 +9 chany_top_in[3]:9 0.0002357925 +10 chany_top_in[3]:10 0.0002053834 +11 chany_top_in[3]:11 0.001489623 +12 chany_top_in[3] chany_bottom_in[5]:19 0.0003702442 +13 chany_top_in[3]:10 chany_bottom_in[5]:20 3.11943e-05 +14 chany_top_in[3]:11 chany_bottom_in[5]:20 0.0003702442 +15 chany_top_in[3]:9 chany_bottom_in[5]:21 3.11943e-05 +16 chany_top_in[3] chany_bottom_in[15]:5 0.0004193259 +17 chany_top_in[3] chany_bottom_in[15]:6 0.000108925 +18 chany_top_in[3]:7 chany_bottom_in[15]:6 1.890753e-06 +19 chany_top_in[3]:6 chany_bottom_in[15]:7 1.890753e-06 +20 chany_top_in[3]:11 chany_bottom_in[15]:6 0.0004193259 +21 chany_top_in[3]:11 chany_bottom_in[15]:7 0.000108925 +22 chany_top_in[3] chany_top_in[5] 0.0003304562 +23 chany_top_in[3] chany_top_in[5]:11 4.018026e-07 +24 chany_top_in[3]:11 chany_top_in[5]:10 4.018026e-07 +25 chany_top_in[3]:11 chany_top_in[5]:12 0.0003304562 +26 chany_top_in[3]:7 chany_top_in[9]:13 0.0003434323 +27 chany_top_in[3]:6 chany_top_in[9]:12 0.0003434323 +28 chany_top_in[3]:7 chany_top_in[11]:8 0.0009766475 +29 chany_top_in[3]:6 chany_top_in[11]:7 0.0009766475 + +*RES +0 chany_top_in[3] chany_top_in[3]:11 0.04161161 +1 chany_top_in[3]:8 chany_top_in[3]:7 0.0045 +2 chany_top_in[3]:8 chany_top_in[3]:3 0.004636161 +3 chany_top_in[3]:7 chany_top_in[3]:6 0.0333125 +4 chany_top_in[3]:5 chany_top_in[3]:4 0.002390625 +5 chany_top_in[3]:6 chany_top_in[3]:5 0.0045 +6 chany_top_in[3]:4 BUFT_RR_59:A 0.152 +7 chany_top_in[3]:3 mux_right_ipin_0\/mux_l1_in_1_:A0 0.152 +8 chany_top_in[3]:10 chany_top_in[3]:9 0.003245536 +9 chany_top_in[3]:11 chany_top_in[3]:10 0.0045 +10 chany_top_in[3]:9 chany_top_in[3]:8 0.0002767857 + +*END + +*D_NET chany_top_in[5] 0.01045512 //LENGTH 101.055 LUMPCC 0.0009836307 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 45.540 107.510 +*I mux_right_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 33.870 75.140 +*I BUFT_RR_61:A I *L 0.001776 *C 33.580 20.400 +*N chany_top_in[5]:3 *C 33.580 20.400 +*N chany_top_in[5]:4 *C 33.580 20.445 +*N chany_top_in[5]:5 *C 33.580 70.240 +*N chany_top_in[5]:6 *C 33.580 75.095 +*N chany_top_in[5]:7 *C 33.580 75.140 +*N chany_top_in[5]:8 *C 33.907 75.140 +*N chany_top_in[5]:9 *C 45.955 75.140 +*N chany_top_in[5]:10 *C 46.000 75.185 +*N chany_top_in[5]:11 *C 46.000 77.520 +*N chany_top_in[5]:12 *C 45.540 77.520 + +*CAP +0 chany_top_in[5] 0.001201664 +1 mux_right_ipin_0\/mux_l1_in_2_:A0 1e-06 +2 BUFT_RR_61:A 1e-06 +3 chany_top_in[5]:3 3.860941e-05 +4 chany_top_in[5]:4 0.002315813 +5 chany_top_in[5]:5 0.002571099 +6 chany_top_in[5]:6 0.0002552861 +7 chany_top_in[5]:7 5.346839e-05 +8 chany_top_in[5]:8 0.0007832291 +9 chany_top_in[5]:9 0.0007629023 +10 chany_top_in[5]:10 0.0001122453 +11 chany_top_in[5]:11 0.0001428766 +12 chany_top_in[5]:12 0.001232295 +13 chany_top_in[5] chany_top_in[3] 0.0003304562 +14 chany_top_in[5]:10 chany_top_in[3]:11 4.018026e-07 +15 chany_top_in[5]:12 chany_top_in[3]:11 0.0003304562 +16 chany_top_in[5]:11 chany_top_in[3] 4.018026e-07 +17 chany_top_in[5] mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001080786 +18 chany_top_in[5]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001080786 +19 chany_top_in[5]:10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.287876e-05 +20 chany_top_in[5]:11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.287876e-05 + +*RES +0 chany_top_in[5] chany_top_in[5]:12 0.02677679 +1 chany_top_in[5]:9 chany_top_in[5]:8 0.0107567 +2 chany_top_in[5]:10 chany_top_in[5]:9 0.0045 +3 chany_top_in[5]:8 mux_right_ipin_0\/mux_l1_in_2_:A0 0.152 +4 chany_top_in[5]:8 chany_top_in[5]:7 0.0001779891 +5 chany_top_in[5]:7 chany_top_in[5]:6 0.0045 +6 chany_top_in[5]:6 chany_top_in[5]:5 0.004334821 +7 chany_top_in[5]:3 BUFT_RR_61:A 0.152 +8 chany_top_in[5]:4 chany_top_in[5]:3 0.0045 +9 chany_top_in[5]:12 chany_top_in[5]:11 0.0004107143 +10 chany_top_in[5]:11 chany_top_in[5]:10 0.002084822 +11 chany_top_in[5]:5 chany_top_in[5]:4 0.04445983 + +*END + +*D_NET chany_top_in[6] 0.00917616 //LENGTH 86.235 LUMPCC 0.003328514 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 70.380 107.510 +*I BUFT_RR_62:A I *L 0.001776 *C 69.000 23.120 +*N chany_top_in[6]:2 *C 69.038 23.120 +*N chany_top_in[6]:3 *C 70.335 23.120 +*N chany_top_in[6]:4 *C 70.380 23.165 +*N chany_top_in[6]:5 *C 70.380 72.960 + +*CAP +0 chany_top_in[6] 0.001423398 +1 BUFT_RR_62:A 1e-06 +2 chany_top_in[6]:2 9.667737e-05 +3 chany_top_in[6]:3 9.667737e-05 +4 chany_top_in[6]:4 0.001403248 +5 chany_top_in[6]:5 0.002826646 +6 chany_top_in[6] chany_bottom_in[2]:5 1.72111e-05 +7 chany_top_in[6] chany_bottom_in[2]:12 0.0001602861 +8 chany_top_in[6]:4 chany_bottom_in[2] 0.0004070714 +9 chany_top_in[6]:4 chany_bottom_in[2]:13 0.0003115369 +10 chany_top_in[6]:5 chany_bottom_in[2]:6 1.72111e-05 +11 chany_top_in[6]:5 chany_bottom_in[2]:12 0.0003115369 +12 chany_top_in[6]:5 chany_bottom_in[2]:13 0.0005673575 +13 chany_top_in[6] chany_top_in[2]:8 5.696461e-05 +14 chany_top_in[6] chany_top_in[2]:10 0.0001477254 +15 chany_top_in[6]:4 chany_top_in[2]:4 0.0003903603 +16 chany_top_in[6]:4 chany_top_in[2]:5 4.231965e-05 +17 chany_top_in[6]:5 chany_top_in[2]:5 0.0004473249 +18 chany_top_in[6]:5 chany_top_in[2]:8 4.231965e-05 +19 chany_top_in[6]:5 chany_top_in[2]:9 0.0001477254 +20 chany_top_in[6] ropt_net_203:5 0.0001307811 +21 chany_top_in[6]:5 ropt_net_203:6 0.0001307811 + +*RES +0 chany_top_in[6] chany_top_in[6]:5 0.03084822 +1 chany_top_in[6]:2 BUFT_RR_62:A 0.152 +2 chany_top_in[6]:3 chany_top_in[6]:2 0.001158482 +3 chany_top_in[6]:4 chany_top_in[6]:3 0.0045 +4 chany_top_in[6]:5 chany_top_in[6]:4 0.04445982 + +*END + +*D_NET chany_top_in[8] 0.008019485 //LENGTH 91.355 LUMPCC 0.001728664 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 69.460 107.510 +*I BUFT_RR_64:A I *L 0.001776 *C 67.160 20.400 +*N chany_top_in[8]:2 *C 66.760 24.480 +*N chany_top_in[8]:3 *C 67.160 20.400 +*N chany_top_in[8]:4 *C 67.160 20.445 +*N chany_top_in[8]:5 *C 67.160 24.422 +*N chany_top_in[8]:6 *C 67.160 24.480 +*N chany_top_in[8]:7 *C 67.160 24.488 +*N chany_top_in[8]:8 *C 67.160 74.315 +*N chany_top_in[8]:9 *C 67.160 104.713 +*N chany_top_in[8]:10 *C 67.180 104.720 +*N chany_top_in[8]:11 *C 69.453 104.720 +*N chany_top_in[8]:12 *C 69.460 104.778 + +*CAP +0 chany_top_in[8] 0.0001840419 +1 BUFT_RR_64:A 1e-06 +2 chany_top_in[8]:2 5.018564e-05 +3 chany_top_in[8]:3 3.517047e-05 +4 chany_top_in[8]:4 0.0002006089 +5 chany_top_in[8]:5 0.0002006089 +6 chany_top_in[8]:6 5.018564e-05 +7 chany_top_in[8]:7 0.001302841 +8 chany_top_in[8]:8 0.00252747 +9 chany_top_in[8]:9 0.001224629 +10 chany_top_in[8]:10 0.0001650187 +11 chany_top_in[8]:11 0.0001650187 +12 chany_top_in[8]:12 0.0001840419 +13 chany_top_in[8]:7 chany_top_in[0]:10 0.000624198 +14 chany_top_in[8]:7 chany_top_in[0]:11 0.0001892026 +15 chany_top_in[8]:9 chany_top_in[0]:12 5.093136e-05 +16 chany_top_in[8]:8 chany_top_in[0]:11 0.0006751294 +17 chany_top_in[8]:8 chany_top_in[0]:12 0.0001892026 + +*RES +0 chany_top_in[8] chany_top_in[8]:12 0.002439732 +1 chany_top_in[8]:3 BUFT_RR_64:A 0.152 +2 chany_top_in[8]:4 chany_top_in[8]:3 0.0045 +3 chany_top_in[8]:5 chany_top_in[8]:4 0.003551339 +4 chany_top_in[8]:6 chany_top_in[8]:5 0.00341 +5 chany_top_in[8]:6 chany_top_in[8]:2 5.69697e-05 +6 chany_top_in[8]:7 chany_top_in[8]:6 0.00341 +7 chany_top_in[8]:10 chany_top_in[8]:9 0.00341 +8 chany_top_in[8]:9 chany_top_in[8]:8 0.004762275 +9 chany_top_in[8]:12 chany_top_in[8]:11 0.00341 +10 chany_top_in[8]:11 chany_top_in[8]:10 0.000356025 +11 chany_top_in[8]:8 chany_top_in[8]:7 0.007806308 + +*END + +*D_NET chany_top_in[9] 0.01405972 //LENGTH 132.265 LUMPCC 0.00135553 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 25.760 107.510 +*I ropt_mt_inst_763:A I *L 0.001766 *C 56.120 9.520 +*N chany_top_in[9]:2 *C 56.083 9.520 +*N chany_top_in[9]:3 *C 52.025 9.520 +*N chany_top_in[9]:4 *C 51.980 9.520 +*N chany_top_in[9]:5 *C 51.980 18.315 +*N chany_top_in[9]:6 *C 51.935 18.360 +*N chany_top_in[9]:7 *C 40.605 18.360 +*N chany_top_in[9]:8 *C 40.490 18.315 +*N chany_top_in[9]:9 *C 40.480 17.725 +*N chany_top_in[9]:10 *C 40.435 17.680 +*N chany_top_in[9]:11 *C 39.605 17.680 +*N chany_top_in[9]:12 *C 39.560 17.725 +*N chany_top_in[9]:13 *C 39.560 67.520 +*N chany_top_in[9]:14 *C 39.560 91.755 +*N chany_top_in[9]:15 *C 39.515 91.800 +*N chany_top_in[9]:16 *C 25.805 91.800 +*N chany_top_in[9]:17 *C 25.760 91.845 + +*CAP +0 chany_top_in[9] 0.000895243 +1 ropt_mt_inst_763:A 1e-06 +2 chany_top_in[9]:2 0.0002419621 +3 chany_top_in[9]:3 0.0002419621 +4 chany_top_in[9]:4 0.0004964981 +5 chany_top_in[9]:5 0.0004684465 +6 chany_top_in[9]:6 0.0007428615 +7 chany_top_in[9]:7 0.0007428615 +8 chany_top_in[9]:8 5.112516e-05 +9 chany_top_in[9]:9 5.112516e-05 +10 chany_top_in[9]:10 6.163072e-05 +11 chany_top_in[9]:11 6.163072e-05 +12 chany_top_in[9]:12 0.002025641 +13 chany_top_in[9]:13 0.003017726 +14 chany_top_in[9]:14 0.0009920856 +15 chany_top_in[9]:15 0.0008585725 +16 chany_top_in[9]:16 0.0008585725 +17 chany_top_in[9]:17 0.000895243 +18 chany_top_in[9]:12 chany_top_in[3]:6 0.0003434323 +19 chany_top_in[9]:13 chany_top_in[3]:7 0.0003434323 +20 chany_top_in[9]:14 mux_tree_tapbuf_size10_0_sram[3]:8 0.0001834853 +21 chany_top_in[9]:14 mux_tree_tapbuf_size10_0_sram[3]:9 8.822833e-05 +22 chany_top_in[9]:13 mux_tree_tapbuf_size10_0_sram[3]:5 0.0001834853 +23 chany_top_in[9]:13 mux_tree_tapbuf_size10_0_sram[3]:8 8.822833e-05 +24 chany_top_in[9] ropt_net_199:4 6.261922e-05 +25 chany_top_in[9]:17 ropt_net_199:5 6.261922e-05 + +*RES +0 chany_top_in[9] chany_top_in[9]:17 0.01398661 +1 chany_top_in[9]:2 ropt_mt_inst_763:A 0.152 +2 chany_top_in[9]:3 chany_top_in[9]:2 0.003622768 +3 chany_top_in[9]:4 chany_top_in[9]:3 0.0045 +4 chany_top_in[9]:6 chany_top_in[9]:5 0.0045 +5 chany_top_in[9]:5 chany_top_in[9]:4 0.007852679 +6 chany_top_in[9]:7 chany_top_in[9]:6 0.01011607 +7 chany_top_in[9]:8 chany_top_in[9]:7 0.0045 +8 chany_top_in[9]:10 chany_top_in[9]:9 0.0045 +9 chany_top_in[9]:9 chany_top_in[9]:8 0.0005267857 +10 chany_top_in[9]:11 chany_top_in[9]:10 0.0007410714 +11 chany_top_in[9]:12 chany_top_in[9]:11 0.0045 +12 chany_top_in[9]:15 chany_top_in[9]:14 0.0045 +13 chany_top_in[9]:14 chany_top_in[9]:13 0.02163839 +14 chany_top_in[9]:16 chany_top_in[9]:15 0.01224107 +15 chany_top_in[9]:17 chany_top_in[9]:16 0.0045 +16 chany_top_in[9]:13 chany_top_in[9]:12 0.04445983 + +*END + +*D_NET chany_top_in[11] 0.01389778 //LENGTH 104.830 LUMPCC 0.006463103 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 48.300 107.510 +*I BUFT_RR_67:A I *L 0.001776 *C 42.780 25.840 +*I mux_right_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 27.965 79.900 +*N chany_top_in[11]:3 *C 27.965 79.900 +*N chany_top_in[11]:4 *C 28.060 79.560 +*N chany_top_in[11]:5 *C 42.742 25.840 +*N chany_top_in[11]:6 *C 41.445 25.840 +*N chany_top_in[11]:7 *C 41.400 25.885 +*N chany_top_in[11]:8 *C 41.400 79.515 +*N chany_top_in[11]:9 *C 41.400 79.560 +*N chany_top_in[11]:10 *C 48.255 79.560 +*N chany_top_in[11]:11 *C 48.300 79.605 + +*CAP +0 chany_top_in[11] 0.0009676163 +1 BUFT_RR_67:A 1e-06 +2 mux_right_ipin_0\/mux_l2_in_2_:A1 1e-06 +3 chany_top_in[11]:3 5.979533e-05 +4 chany_top_in[11]:4 0.0006709201 +5 chany_top_in[11]:5 9.91366e-05 +6 chany_top_in[11]:6 9.91366e-05 +7 chany_top_in[11]:7 0.001615756 +8 chany_top_in[11]:8 0.001615756 +9 chany_top_in[11]:9 0.001007747 +10 chany_top_in[11]:10 0.0003291943 +11 chany_top_in[11]:11 0.0009676163 +12 chany_top_in[11]:10 chany_bottom_in[6]:6 0.0002548567 +13 chany_top_in[11]:9 chany_bottom_in[6]:6 0.0004190456 +14 chany_top_in[11]:9 chany_bottom_in[6]:7 0.0002548567 +15 chany_top_in[11]:4 chany_bottom_in[6]:7 0.0004190456 +16 chany_top_in[11]:8 chany_bottom_in[16]:10 0.000793967 +17 chany_top_in[11]:7 chany_bottom_in[16]:11 0.000793967 +18 chany_top_in[11] chany_bottom_in[18]:11 0.0006876033 +19 chany_top_in[11]:11 chany_bottom_in[18]:12 0.0006876033 +20 chany_top_in[11]:8 chany_top_in[3]:7 0.0009766475 +21 chany_top_in[11]:7 chany_top_in[3]:6 0.0009766475 +22 chany_top_in[11] mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.943192e-05 +23 chany_top_in[11]:11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.943192e-05 + +*RES +0 chany_top_in[11] chany_top_in[11]:11 0.02491518 +1 chany_top_in[11]:3 mux_right_ipin_0\/mux_l2_in_2_:A1 0.152 +2 chany_top_in[11]:10 chany_top_in[11]:9 0.006120536 +3 chany_top_in[11]:11 chany_top_in[11]:10 0.0045 +4 chany_top_in[11]:9 chany_top_in[11]:8 0.0045 +5 chany_top_in[11]:9 chany_top_in[11]:4 0.01191071 +6 chany_top_in[11]:8 chany_top_in[11]:7 0.04788394 +7 chany_top_in[11]:6 chany_top_in[11]:5 0.001158482 +8 chany_top_in[11]:7 chany_top_in[11]:6 0.0045 +9 chany_top_in[11]:5 BUFT_RR_67:A 0.152 +10 chany_top_in[11]:4 chany_top_in[11]:3 0.0003035715 + +*END + +*D_NET chany_top_in[14] 0.0140004 //LENGTH 126.475 LUMPCC 0.004873293 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 46.000 107.590 +*I ropt_mt_inst_755:A I *L 0.001767 *C 29.900 4.080 +*N chany_top_in[14]:2 *C 29.900 4.080 +*N chany_top_in[14]:3 *C 29.900 4.035 +*N chany_top_in[14]:4 *C 29.900 2.098 +*N chany_top_in[14]:5 *C 29.900 2.040 +*N chany_top_in[14]:6 *C 36.333 2.040 +*N chany_top_in[14]:7 *C 36.340 2.098 +*N chany_top_in[14]:8 *C 36.340 19.675 +*N chany_top_in[14]:9 *C 36.385 19.720 +*N chany_top_in[14]:10 *C 38.520 19.720 +*N chany_top_in[14]:11 *C 38.633 19.765 +*N chany_top_in[14]:12 *C 38.640 20.355 +*N chany_top_in[14]:13 *C 38.685 20.400 +*N chany_top_in[14]:14 *C 40.435 20.400 +*N chany_top_in[14]:15 *C 40.480 20.400 +*N chany_top_in[14]:16 *C 40.488 20.400 +*N chany_top_in[14]:17 *C 45.980 20.400 +*N chany_top_in[14]:18 *C 46.000 20.408 +*N chany_top_in[14]:19 *C 46.000 70.235 + +*CAP +0 chany_top_in[14] 0.001212318 +1 ropt_mt_inst_755:A 1e-06 +2 chany_top_in[14]:2 2.920496e-05 +3 chany_top_in[14]:3 0.0001202361 +4 chany_top_in[14]:4 0.0001202361 +5 chany_top_in[14]:5 0.0004271924 +6 chany_top_in[14]:6 0.0004271924 +7 chany_top_in[14]:7 0.0006745687 +8 chany_top_in[14]:8 0.0006745687 +9 chany_top_in[14]:9 0.0001550199 +10 chany_top_in[14]:10 0.0001550199 +11 chany_top_in[14]:11 4.805889e-05 +12 chany_top_in[14]:12 4.805889e-05 +13 chany_top_in[14]:13 0.0001193741 +14 chany_top_in[14]:14 0.0001193741 +15 chany_top_in[14]:15 3.582121e-05 +16 chany_top_in[14]:16 0.0003899536 +17 chany_top_in[14]:17 0.0003899536 +18 chany_top_in[14]:18 0.001383819 +19 chany_top_in[14]:19 0.002596136 +20 chany_top_in[14]:7 chany_bottom_in[11]:12 0.0004118219 +21 chany_top_in[14]:8 chany_bottom_in[11]:11 0.0004118219 +22 chany_top_in[14]:11 chany_bottom_in[11]:12 4.384046e-06 +23 chany_top_in[14]:12 chany_bottom_in[11]:11 4.384046e-06 +24 chany_top_in[14]:18 chany_bottom_in[18] 0.0007138705 +25 chany_top_in[14]:18 chany_bottom_in[18]:16 0.0003425804 +26 chany_top_in[14]:19 chany_bottom_in[18]:15 0.0003425804 +27 chany_top_in[14]:19 chany_bottom_in[18]:16 0.0007138705 +28 chany_top_in[14] chany_top_in[15] 0.000836655 +29 chany_top_in[14]:18 chany_top_in[15]:8 7.01084e-05 +30 chany_top_in[14]:18 chany_top_in[15]:12 5.722596e-05 +31 chany_top_in[14]:19 chany_top_in[15] 5.722596e-05 +32 chany_top_in[14]:19 chany_top_in[15]:9 7.01084e-05 +33 chany_top_in[14]:19 chany_top_in[15]:12 0.000836655 + +*RES +0 chany_top_in[14] chany_top_in[14]:19 0.005852283 +1 chany_top_in[14]:2 ropt_mt_inst_755:A 0.152 +2 chany_top_in[14]:3 chany_top_in[14]:2 0.0045 +3 chany_top_in[14]:4 chany_top_in[14]:3 0.001729911 +4 chany_top_in[14]:5 chany_top_in[14]:4 0.00341 +5 chany_top_in[14]:7 chany_top_in[14]:6 0.00341 +6 chany_top_in[14]:6 chany_top_in[14]:5 0.001007758 +7 chany_top_in[14]:9 chany_top_in[14]:8 0.0045 +8 chany_top_in[14]:8 chany_top_in[14]:7 0.0156942 +9 chany_top_in[14]:10 chany_top_in[14]:9 0.00190625 +10 chany_top_in[14]:11 chany_top_in[14]:10 0.0045 +11 chany_top_in[14]:13 chany_top_in[14]:12 0.0045 +12 chany_top_in[14]:12 chany_top_in[14]:11 0.0005267857 +13 chany_top_in[14]:14 chany_top_in[14]:13 0.0015625 +14 chany_top_in[14]:15 chany_top_in[14]:14 0.0045 +15 chany_top_in[14]:16 chany_top_in[14]:15 0.00341 +16 chany_top_in[14]:17 chany_top_in[14]:16 0.0008604917 +17 chany_top_in[14]:18 chany_top_in[14]:17 0.00341 +18 chany_top_in[14]:19 chany_top_in[14]:18 0.007806308 + +*END + +*D_NET chany_top_in[17] 0.01230766 //LENGTH 119.955 LUMPCC 0.000507838 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 47.380 107.510 +*I mux_right_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 16.465 74.460 +*I BUFT_RR_73:A I *L 0.001767 *C 18.400 20.400 +*N chany_top_in[17]:3 *C 18.363 20.400 +*N chany_top_in[17]:4 *C 17.985 20.400 +*N chany_top_in[17]:5 *C 17.940 20.445 +*N chany_top_in[17]:6 *C 16.503 74.460 +*N chany_top_in[17]:7 *C 17.895 74.460 +*N chany_top_in[17]:8 *C 17.940 74.460 +*N chany_top_in[17]:9 *C 17.940 103.983 +*N chany_top_in[17]:10 *C 17.948 104.040 +*N chany_top_in[17]:11 *C 47.373 104.040 +*N chany_top_in[17]:12 *C 47.380 104.098 + +*CAP +0 chany_top_in[17] 0.000229854 +1 mux_right_ipin_0\/mux_l2_in_3_:A1 1e-06 +2 BUFT_RR_73:A 1e-06 +3 chany_top_in[17]:3 3.885171e-05 +4 chany_top_in[17]:4 3.885171e-05 +5 chany_top_in[17]:5 0.002327922 +6 chany_top_in[17]:6 0.0001539606 +7 chany_top_in[17]:7 0.0001539606 +8 chany_top_in[17]:8 0.003660413 +9 chany_top_in[17]:9 0.001303214 +10 chany_top_in[17]:10 0.001830469 +11 chany_top_in[17]:11 0.001830469 +12 chany_top_in[17]:12 0.000229854 +13 chany_top_in[17]:7 optlc_net_145:2 5.286673e-07 +14 chany_top_in[17]:8 optlc_net_145:4 9.022513e-05 +15 chany_top_in[17]:8 optlc_net_145:5 6.838299e-06 +16 chany_top_in[17]:6 optlc_net_145:3 5.286673e-07 +17 chany_top_in[17]:9 optlc_net_145:4 6.838299e-06 +18 chany_top_in[17]:5 optlc_net_145:5 9.022513e-05 +19 chany_top_in[17]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 1.457744e-06 +20 chany_top_in[17]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001548691 +21 chany_top_in[17]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.457744e-06 +22 chany_top_in[17]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001548691 + +*RES +0 chany_top_in[17] chany_top_in[17]:12 0.003046875 +1 chany_top_in[17]:7 chany_top_in[17]:6 0.001243304 +2 chany_top_in[17]:8 chany_top_in[17]:7 0.0045 +3 chany_top_in[17]:8 chany_top_in[17]:5 0.04822768 +4 chany_top_in[17]:6 mux_right_ipin_0\/mux_l2_in_3_:A1 0.152 +5 chany_top_in[17]:9 chany_top_in[17]:8 0.02635938 +6 chany_top_in[17]:10 chany_top_in[17]:9 0.00341 +7 chany_top_in[17]:12 chany_top_in[17]:11 0.00341 +8 chany_top_in[17]:11 chany_top_in[17]:10 0.004609916 +9 chany_top_in[17]:4 chany_top_in[17]:3 0.0003370536 +10 chany_top_in[17]:5 chany_top_in[17]:4 0.0045 +11 chany_top_in[17]:3 BUFT_RR_73:A 0.152 + +*END + +*D_NET chany_top_in[18] 0.01329236 //LENGTH 121.700 LUMPCC 0.00650881 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 23.920 107.590 +*I ropt_mt_inst_761:A I *L 0.001767 *C 40.020 4.080 +*N chany_top_in[18]:2 *C 39.983 4.080 +*N chany_top_in[18]:3 *C 39.560 4.080 +*N chany_top_in[18]:4 *C 39.560 4.420 +*N chany_top_in[18]:5 *C 31.325 4.420 +*N chany_top_in[18]:6 *C 31.280 4.465 +*N chany_top_in[18]:7 *C 31.280 14.915 +*N chany_top_in[18]:8 *C 31.235 14.960 +*N chany_top_in[18]:9 *C 29.485 14.960 +*N chany_top_in[18]:10 *C 29.440 15.005 +*N chany_top_in[18]:11 *C 29.440 35.303 +*N chany_top_in[18]:12 *C 29.433 35.360 +*N chany_top_in[18]:13 *C 23.940 35.360 +*N chany_top_in[18]:14 *C 23.920 35.367 +*N chany_top_in[18]:15 *C 23.920 85.195 + +*CAP +0 chany_top_in[18] 0.0004575925 +1 ropt_mt_inst_761:A 1e-06 +2 chany_top_in[18]:2 4.633595e-05 +3 chany_top_in[18]:3 6.986509e-05 +4 chany_top_in[18]:4 0.0004937171 +5 chany_top_in[18]:5 0.000470188 +6 chany_top_in[18]:6 0.0004855915 +7 chany_top_in[18]:7 0.0004855915 +8 chany_top_in[18]:8 0.000110996 +9 chany_top_in[18]:9 0.000110996 +10 chany_top_in[18]:10 0.0008300799 +11 chany_top_in[18]:11 0.0008300799 +12 chany_top_in[18]:12 0.0003092896 +13 chany_top_in[18]:13 0.0003092896 +14 chany_top_in[18]:14 0.0006576717 +15 chany_top_in[18]:15 0.001115264 +16 chany_top_in[18] chany_bottom_in[8]:8 0.0002601113 +17 chany_top_in[18]:14 chany_bottom_in[8] 0.0003825247 +18 chany_top_in[18]:14 chany_bottom_in[8]:9 0.0008044058 +19 chany_top_in[18]:15 chany_bottom_in[8]:8 0.0008044058 +20 chany_top_in[18]:15 chany_bottom_in[8]:9 0.000642636 +21 chany_top_in[18] chany_top_in[19] 0.0002592525 +22 chany_top_in[18] chany_top_in[19]:24 0.0002603225 +23 chany_top_in[18]:6 chany_top_in[19]:14 4.180669e-06 +24 chany_top_in[18]:7 chany_top_in[19]:15 4.180669e-06 +25 chany_top_in[18]:10 chany_top_in[19]:14 6.068667e-05 +26 chany_top_in[18]:11 chany_top_in[19]:15 6.068667e-05 +27 chany_top_in[18]:14 chany_top_in[19]:23 0.0009339849 +28 chany_top_in[18]:15 chany_top_in[19]:23 0.0002603225 +29 chany_top_in[18]:15 chany_top_in[19]:24 0.001193237 +30 chany_top_in[18]:6 ropt_net_166:4 2.247613e-05 +31 chany_top_in[18]:7 ropt_net_166:5 2.247613e-05 +32 chany_top_in[18]:10 ropt_net_166:4 0.0001329235 +33 chany_top_in[18]:11 ropt_net_166:5 0.0001329235 +34 chany_top_in[18]:5 ropt_net_163:2 0.0001335369 +35 chany_top_in[18]:4 ropt_net_163:3 0.0001335369 + +*RES +0 chany_top_in[18] chany_top_in[18]:15 0.00350855 +1 chany_top_in[18]:2 ropt_mt_inst_761:A 0.152 +2 chany_top_in[18]:5 chany_top_in[18]:4 0.007352679 +3 chany_top_in[18]:6 chany_top_in[18]:5 0.0045 +4 chany_top_in[18]:8 chany_top_in[18]:7 0.0045 +5 chany_top_in[18]:7 chany_top_in[18]:6 0.009330358 +6 chany_top_in[18]:9 chany_top_in[18]:8 0.0015625 +7 chany_top_in[18]:10 chany_top_in[18]:9 0.0045 +8 chany_top_in[18]:11 chany_top_in[18]:10 0.01812277 +9 chany_top_in[18]:12 chany_top_in[18]:11 0.00341 +10 chany_top_in[18]:13 chany_top_in[18]:12 0.0008604917 +11 chany_top_in[18]:14 chany_top_in[18]:13 0.00341 +12 chany_top_in[18]:4 chany_top_in[18]:3 0.0003035715 +13 chany_top_in[18]:3 chany_top_in[18]:2 0.0003772322 +14 chany_top_in[18]:15 chany_top_in[18]:14 0.007806308 + +*END + +*D_NET ccff_head[0] 0.001228743 //LENGTH 9.760 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 54.280 107.510 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 54.440 98.940 +*N ccff_head[0]:2 *C 54.440 98.940 +*N ccff_head[0]:3 *C 54.740 98.940 +*N ccff_head[0]:4 *C 54.740 98.985 +*N ccff_head[0]:5 *C 54.740 101.320 +*N ccff_head[0]:6 *C 54.280 101.320 + +*CAP +0 ccff_head[0] 0.0003610758 +1 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 4.793075e-05 +3 ccff_head[0]:3 5.231271e-05 +4 ccff_head[0]:4 0.0001734937 +5 ccff_head[0]:5 0.0002026739 +6 ccff_head[0]:6 0.000390256 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.005526786 +1 ccff_head[0]:2 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001630435 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:6 ccff_head[0]:5 0.0004107143 +5 ccff_head[0]:5 ccff_head[0]:4 0.002084822 + +*END + +*D_NET ropt_net_154 0.001403816 //LENGTH 13.390 LUMPCC 0.0001536739 DR + +*CONN +*I mux_left_ipin_0\/BUFT_RR_42:X O *L 0 *C 70.380 77.860 +*I ropt_mt_inst_758:A I *L 0.001766 *C 77.740 82.960 +*N ropt_net_154:2 *C 77.703 82.960 +*N ropt_net_154:3 *C 76.865 82.960 +*N ropt_net_154:4 *C 76.820 82.915 +*N ropt_net_154:5 *C 76.820 77.905 +*N ropt_net_154:6 *C 76.775 77.860 +*N ropt_net_154:7 *C 70.418 77.860 + +*CAP +0 mux_left_ipin_0\/BUFT_RR_42:X 1e-06 +1 ropt_mt_inst_758:A 1e-06 +2 ropt_net_154:2 6.138472e-05 +3 ropt_net_154:3 6.138472e-05 +4 ropt_net_154:4 0.0001941986 +5 ropt_net_154:5 0.0001941986 +6 ropt_net_154:6 0.0003684877 +7 ropt_net_154:7 0.0003684877 +8 ropt_net_154:5 chany_bottom_in[4]:11 7.683696e-05 +9 ropt_net_154:4 chany_bottom_in[4]:10 7.683696e-05 + +*RES +0 mux_left_ipin_0\/BUFT_RR_42:X ropt_net_154:7 0.152 +1 ropt_net_154:7 ropt_net_154:6 0.00567634 +2 ropt_net_154:6 ropt_net_154:5 0.0045 +3 ropt_net_154:5 ropt_net_154:4 0.004473215 +4 ropt_net_154:3 ropt_net_154:2 0.0007477679 +5 ropt_net_154:4 ropt_net_154:3 0.0045 +6 ropt_net_154:2 ropt_mt_inst_758:A 0.152 + +*END + +*D_NET ropt_net_176 0.001302594 //LENGTH 11.550 LUMPCC 0.000265257 DR + +*CONN +*I mem_right_ipin_0\/BUFT_RR_142:X O *L 0 *C 3.905 75.480 +*I ropt_mt_inst_780:A I *L 0.001766 *C 3.220 85.680 +*N ropt_net_176:2 *C 3.220 85.680 +*N ropt_net_176:3 *C 3.220 85.635 +*N ropt_net_176:4 *C 3.220 77.180 +*N ropt_net_176:5 *C 3.680 77.180 +*N ropt_net_176:6 *C 3.680 75.525 +*N ropt_net_176:7 *C 3.680 75.480 +*N ropt_net_176:8 *C 3.905 75.480 + +*CAP +0 mem_right_ipin_0\/BUFT_RR_142:X 1e-06 +1 ropt_mt_inst_780:A 1e-06 +2 ropt_net_176:2 2.686179e-05 +3 ropt_net_176:3 0.0003351844 +4 ropt_net_176:4 0.0003611015 +5 ropt_net_176:5 0.0001234953 +6 ropt_net_176:6 9.757829e-05 +7 ropt_net_176:7 4.370404e-05 +8 ropt_net_176:8 4.741176e-05 +9 ropt_net_176:3 left_grid_pin_0_[0]:3 0.0001326285 +10 ropt_net_176:4 left_grid_pin_0_[0]:4 0.0001326285 + +*RES +0 mem_right_ipin_0\/BUFT_RR_142:X ropt_net_176:8 0.152 +1 ropt_net_176:8 ropt_net_176:7 0.0001222826 +2 ropt_net_176:7 ropt_net_176:6 0.0045 +3 ropt_net_176:6 ropt_net_176:5 0.001477679 +4 ropt_net_176:2 ropt_mt_inst_780:A 0.152 +5 ropt_net_176:3 ropt_net_176:2 0.0045 +6 ropt_net_176:4 ropt_net_176:3 0.007549108 +7 ropt_net_176:5 ropt_net_176:4 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.01152884 //LENGTH 87.035 LUMPCC 0.00274499 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 60.565 96.560 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 35.595 96.900 +*I mux_left_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 66.340 91.120 +*I mux_left_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 57.160 63.580 +*I mux_left_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 55.100 52.360 +*I mux_left_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 59.440 74.510 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 59.440 74.510 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 59.330 74.800 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 55.138 52.360 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 57.040 52.360 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 57.040 52.700 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 57.915 52.700 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 57.960 52.745 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 57.198 63.580 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 57.915 63.580 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 57.960 63.580 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 57.960 74.755 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 58.005 74.800 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 59.353 74.800 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 59.770 74.770 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 59.800 74.845 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 59.800 79.220 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 60.260 79.220 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 60.260 91.120 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 66.303 91.120 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 60.765 91.120 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 60.720 91.165 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 35.633 96.900 +*N mux_tree_tapbuf_size10_0_sram[1]:28 *C 36.755 96.900 +*N mux_tree_tapbuf_size10_0_sram[1]:29 *C 36.800 96.855 +*N mux_tree_tapbuf_size10_0_sram[1]:30 *C 36.800 95.938 +*N mux_tree_tapbuf_size10_0_sram[1]:31 *C 36.808 95.880 +*N mux_tree_tapbuf_size10_0_sram[1]:32 *C 60.713 95.880 +*N mux_tree_tapbuf_size10_0_sram[1]:33 *C 60.720 95.880 +*N mux_tree_tapbuf_size10_0_sram[1]:34 *C 60.720 96.515 +*N mux_tree_tapbuf_size10_0_sram[1]:35 *C 60.720 96.560 +*N mux_tree_tapbuf_size10_0_sram[1]:36 *C 60.565 96.560 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_ipin_0\/mux_l2_in_0_:S 1e-06 +3 mux_left_ipin_0\/mux_l2_in_3_:S 1e-06 +4 mux_left_ipin_0\/mux_l2_in_2_:S 1e-06 +5 mux_left_ipin_0\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 5.571142e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:7 4.566111e-05 +8 mux_tree_tapbuf_size10_0_sram[1]:8 0.0001435949 +9 mux_tree_tapbuf_size10_0_sram[1]:9 0.0001660658 +10 mux_tree_tapbuf_size10_0_sram[1]:10 9.46359e-05 +11 mux_tree_tapbuf_size10_0_sram[1]:11 7.216498e-05 +12 mux_tree_tapbuf_size10_0_sram[1]:12 0.0003934322 +13 mux_tree_tapbuf_size10_0_sram[1]:13 6.591435e-05 +14 mux_tree_tapbuf_size10_0_sram[1]:14 6.591435e-05 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0009397384 +16 mux_tree_tapbuf_size10_0_sram[1]:16 0.000512395 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0001075413 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.0001713227 +19 mux_tree_tapbuf_size10_0_sram[1]:19 4.642289e-05 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0002379102 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.000265917 +22 mux_tree_tapbuf_size10_0_sram[1]:22 0.0006828427 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0006639303 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0002895488 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0002895488 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.0003067325 +27 mux_tree_tapbuf_size10_0_sram[1]:27 9.813606e-05 +28 mux_tree_tapbuf_size10_0_sram[1]:28 9.813606e-05 +29 mux_tree_tapbuf_size10_0_sram[1]:29 7.597775e-05 +30 mux_tree_tapbuf_size10_0_sram[1]:30 7.597775e-05 +31 mux_tree_tapbuf_size10_0_sram[1]:31 0.001140575 +32 mux_tree_tapbuf_size10_0_sram[1]:32 0.001140575 +33 mux_tree_tapbuf_size10_0_sram[1]:33 0.0003836734 +34 mux_tree_tapbuf_size10_0_sram[1]:34 5.179675e-05 +35 mux_tree_tapbuf_size10_0_sram[1]:35 5.00629e-05 +36 mux_tree_tapbuf_size10_0_sram[1]:36 4.598987e-05 +37 mux_tree_tapbuf_size10_0_sram[1]:32 prog_clk[0]:18 0.0009428824 +38 mux_tree_tapbuf_size10_0_sram[1]:31 prog_clk[0]:19 0.0009428824 +39 mux_tree_tapbuf_size10_0_sram[1]:25 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.406951e-05 +40 mux_tree_tapbuf_size10_0_sram[1]:26 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.084441e-05 +41 mux_tree_tapbuf_size10_0_sram[1]:24 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.406951e-05 +42 mux_tree_tapbuf_size10_0_sram[1]:23 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.084441e-05 +43 mux_tree_tapbuf_size10_0_sram[1]:16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.995016e-05 +44 mux_tree_tapbuf_size10_0_sram[1]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002261434 +45 mux_tree_tapbuf_size10_0_sram[1]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.995016e-05 +46 mux_tree_tapbuf_size10_0_sram[1]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.467394e-06 +47 mux_tree_tapbuf_size10_0_sram[1]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002261434 +48 mux_tree_tapbuf_size10_0_sram[1]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.467394e-06 +49 mux_tree_tapbuf_size10_0_sram[1]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 3.137834e-06 +50 mux_tree_tapbuf_size10_0_sram[1]:9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 3.137834e-06 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:36 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:33 mux_tree_tapbuf_size10_0_sram[1]:32 0.00341 +2 mux_tree_tapbuf_size10_0_sram[1]:33 mux_tree_tapbuf_size10_0_sram[1]:26 0.004209822 +3 mux_tree_tapbuf_size10_0_sram[1]:32 mux_tree_tapbuf_size10_0_sram[1]:31 0.003745116 +4 mux_tree_tapbuf_size10_0_sram[1]:30 mux_tree_tapbuf_size10_0_sram[1]:29 0.0008191965 +5 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:30 0.00341 +6 mux_tree_tapbuf_size10_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:27 0.001002232 +7 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:28 0.0045 +8 mux_tree_tapbuf_size10_0_sram[1]:27 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +10 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.00997768 +11 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.0002609375 +12 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0045 +13 mux_tree_tapbuf_size10_0_sram[1]:35 mux_tree_tapbuf_size10_0_sram[1]:34 0.0045 +14 mux_tree_tapbuf_size10_0_sram[1]:34 mux_tree_tapbuf_size10_0_sram[1]:33 0.0005669643 +15 mux_tree_tapbuf_size10_0_sram[1]:36 mux_tree_tapbuf_size10_0_sram[1]:35 8.423914e-05 +16 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:13 0.000640625 +17 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0045 +18 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:12 0.009674108 +19 mux_tree_tapbuf_size10_0_sram[1]:13 mux_left_ipin_0\/mux_l2_in_3_:S 0.152 +20 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.00078125 +21 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.0045 +22 mux_tree_tapbuf_size10_0_sram[1]:8 mux_left_ipin_0\/mux_l2_in_2_:S 0.152 +23 mux_tree_tapbuf_size10_0_sram[1]:6 mux_left_ipin_0\/mux_l2_in_1_:S 0.152 +24 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.004944196 +25 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.0045 +26 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:23 0.0004107143 +27 mux_tree_tapbuf_size10_0_sram[1]:24 mux_left_ipin_0\/mux_l2_in_0_:S 0.152 +28 mux_tree_tapbuf_size10_0_sram[1]:9 mux_tree_tapbuf_size10_0_sram[1]:8 0.001698661 +29 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.0003035715 +30 mux_tree_tapbuf_size10_0_sram[1]:7 mux_tree_tapbuf_size10_0_sram[1]:6 0.000125 +31 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.001203125 +32 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:7 2.008929e-05 +33 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.00390625 +34 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.0004107143 +35 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.010625 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.006191199 //LENGTH 50.495 LUMPCC 0.0009694103 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 36.645 88.060 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 25.015 82.620 +*I mux_right_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 34.600 61.200 +*I mux_right_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 30.920 58.480 +*I mux_right_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 32.760 74.120 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 32.797 74.120 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 30.958 58.480 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 34.455 58.480 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 34.500 58.525 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 34.600 61.200 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 34.500 61.540 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 34.500 61.540 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 34.500 74.075 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 34.500 74.120 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 36.295 74.120 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 36.340 74.165 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 25.053 82.620 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 36.295 82.620 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 36.340 82.620 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 36.340 88.015 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 36.340 88.060 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 36.645 88.060 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_0\/mux_l1_in_1_:S 1e-06 +3 mux_right_ipin_0\/mux_l1_in_0_:S 1e-06 +4 mux_right_ipin_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 0.0001400768 +6 mux_tree_tapbuf_size10_1_sram[0]:6 0.0002164206 +7 mux_tree_tapbuf_size10_1_sram[0]:7 0.0002164206 +8 mux_tree_tapbuf_size10_1_sram[0]:8 0.0001386428 +9 mux_tree_tapbuf_size10_1_sram[0]:9 6.493145e-05 +10 mux_tree_tapbuf_size10_1_sram[0]:10 7.029586e-05 +11 mux_tree_tapbuf_size10_1_sram[0]:11 0.0006676412 +12 mux_tree_tapbuf_size10_1_sram[0]:12 0.0004990767 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0003242907 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.000153164 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0003347555 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0007605211 +17 mux_tree_tapbuf_size10_1_sram[0]:17 0.0007605211 +18 mux_tree_tapbuf_size10_1_sram[0]:18 0.0005661909 +19 mux_tree_tapbuf_size10_1_sram[0]:19 0.0002054932 +20 mux_tree_tapbuf_size10_1_sram[0]:20 5.081353e-05 +21 mux_tree_tapbuf_size10_1_sram[0]:21 4.753292e-05 +22 mux_tree_tapbuf_size10_1_sram[0]:19 chany_top_in[1]:28 7.38688e-05 +23 mux_tree_tapbuf_size10_1_sram[0]:12 chany_top_in[1]:28 0.0001782233 +24 mux_tree_tapbuf_size10_1_sram[0]:15 chany_top_in[1]:27 0.0001135641 +25 mux_tree_tapbuf_size10_1_sram[0]:18 chany_top_in[1]:27 7.38688e-05 +26 mux_tree_tapbuf_size10_1_sram[0]:18 chany_top_in[1]:28 0.0001135641 +27 mux_tree_tapbuf_size10_1_sram[0]:11 chany_top_in[1]:27 0.0001782233 +28 mux_tree_tapbuf_size10_1_sram[0]:11 chany_top_in[1]:28 3.78624e-05 +29 mux_tree_tapbuf_size10_1_sram[0]:7 chany_top_in[1]:26 8.118644e-05 +30 mux_tree_tapbuf_size10_1_sram[0]:8 chany_top_in[1]:27 3.78624e-05 +31 mux_tree_tapbuf_size10_1_sram[0]:6 chany_top_in[1]:25 8.118644e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:21 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.0045 +2 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 0.004816964 +3 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.0001657609 +4 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:5 0.001520089 +6 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.01119196 +7 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:13 0.001602679 +8 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.0045 +9 mux_tree_tapbuf_size10_1_sram[0]:17 mux_tree_tapbuf_size10_1_sram[0]:16 0.01003795 +10 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.0045 +11 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:15 0.007549107 +12 mux_tree_tapbuf_size10_1_sram[0]:16 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size10_1_sram[0]:5 mux_right_ipin_0\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_1_sram[0]:10 mux_tree_tapbuf_size10_1_sram[0]:9 0.0001847826 +15 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.0045 +16 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:8 0.002691964 +17 mux_tree_tapbuf_size10_1_sram[0]:9 mux_right_ipin_0\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_1_sram[0]:7 mux_tree_tapbuf_size10_1_sram[0]:6 0.003122768 +19 mux_tree_tapbuf_size10_1_sram[0]:8 mux_tree_tapbuf_size10_1_sram[0]:7 0.0045 +20 mux_tree_tapbuf_size10_1_sram[0]:6 mux_right_ipin_0\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.001665248 //LENGTH 15.120 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 13.185 72.080 +*I mem_right_ipin_0\/FTB_2__41:A I *L 0.001743 *C 10.120 74.800 +*I mux_right_ipin_0\/mux_l4_in_0_:S I *L 0.008363 *C 12.540 79.978 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 10.120 74.800 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 10.120 74.845 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 10.120 80.025 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 12.540 79.977 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 12.420 79.900 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 12.420 79.855 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 12.420 72.125 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 12.465 72.080 +*N mux_tree_tapbuf_size10_1_sram[3]:11 *C 13.148 72.080 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_0\/FTB_2__41:A 1e-06 +2 mux_right_ipin_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 3.071493e-05 +4 mux_tree_tapbuf_size10_1_sram[3]:4 0.0002741607 +5 mux_tree_tapbuf_size10_1_sram[3]:5 0.0002741607 +6 mux_tree_tapbuf_size10_1_sram[3]:6 1.588539e-05 +7 mux_tree_tapbuf_size10_1_sram[3]:7 1.588539e-05 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.000433407 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.000433407 +10 mux_tree_tapbuf_size10_1_sram[3]:10 9.23136e-05 +11 mux_tree_tapbuf_size10_1_sram[3]:11 9.23136e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 3.015625e-05 +2 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.0045 +3 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.0045 +4 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.006901786 +5 mux_tree_tapbuf_size10_1_sram[3]:11 mux_tree_tapbuf_size10_1_sram[3]:10 0.000609375 +6 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:4 0.004625 +7 mux_tree_tapbuf_size10_1_sram[3]:3 mem_right_ipin_0\/FTB_2__41:A 0.152 +8 mux_tree_tapbuf_size10_1_sram[3]:4 mux_tree_tapbuf_size10_1_sram[3]:3 0.0045 +9 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.0045 +10 mux_tree_tapbuf_size10_1_sram[3]:6 mux_right_ipin_0\/mux_l4_in_0_:S 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.0005518487 //LENGTH 4.130 LUMPCC 0 DR + +*CONN +*I mem_left_ipin_0\/FTB_1__40:X O *L 0 *C 32.400 86.020 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 30.995 88.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 30.995 88.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 32.155 88.060 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 32.200 88.015 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 32.200 86.065 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 32.200 86.020 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 32.400 86.020 + +*CAP +0 mem_left_ipin_0\/FTB_1__40:X 1e-06 +1 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0001267475 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 8.999874e-05 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0001155575 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0001155575 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 5.259181e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 4.93956e-05 + +*RES +0 mem_left_ipin_0\/FTB_1__40:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.001035714 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0001086957 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001312196 //LENGTH 10.045 LUMPCC 0.0003159012 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_2_:X O *L 0 *C 67.795 72.420 +*I mux_left_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 60.720 74.460 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 60.758 74.460 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 65.275 74.460 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 65.320 74.415 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 65.320 72.465 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 65.365 72.420 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 67.758 72.420 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002070653 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002070653 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001122218 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001122218 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001778603 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001778603 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[5]:14 8.413667e-06 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[5]:15 0.0001495369 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[5]:13 8.413667e-06 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_bottom_in[5]:18 0.0001495369 + +*RES +0 mux_left_ipin_0\/mux_l1_in_2_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002136161 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004033483 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_ipin_0\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001715565 //LENGTH 14.745 LUMPCC 0.0001124128 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_1_:X O *L 0 *C 58.595 75.480 +*I mux_left_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 46.290 77.180 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 46.328 77.180 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 58.375 77.180 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 58.420 77.135 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 58.420 75.525 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 58.420 75.480 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 58.595 75.480 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0006362966 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0006362966 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000107403 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000107403 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.447827e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.927441e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_0_sram[2]:9 5.620639e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:8 5.620639e-05 + +*RES +0 mux_left_ipin_0\/mux_l2_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0107567 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.510869e-05 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003988397 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_3_:X O *L 0 *C 54.455 64.600 +*I mux_left_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 54.110 65.960 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 54.110 65.960 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 54.280 65.960 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 54.280 65.915 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 54.280 64.645 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 54.280 64.600 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 54.455 64.600 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.652821e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.700909e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.619609e-05 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.619609e-05 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.680063e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.410958e-05 + +*RES +0 mux_left_ipin_0\/mux_l2_in_3_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.510869e-05 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003037989 //LENGTH 26.615 LUMPCC 0 DR + +*CONN +*I mux_left_ipin_0\/mux_l4_in_0_:X O *L 0 *C 47.205 72.760 +*I mux_left_ipin_0\/BUFT_RR_42:A I *L 0.001776 *C 68.080 77.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 68.080 77.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 68.080 77.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 68.073 77.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 47.848 77.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 47.840 77.463 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 47.840 72.805 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 47.795 72.760 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 47.242 72.760 + +*CAP +0 mux_left_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_left_ipin_0\/BUFT_RR_42:A 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.868778e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.36079e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001137449 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.001137449 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002842699 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002842699 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.012778e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 6.012778e-05 + +*RES +0 mux_left_ipin_0\/mux_l4_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_ipin_0\/BUFT_RR_42:A 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.00341 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.003168583 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0045 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.004158482 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004933036 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001845771 //LENGTH 17.740 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_0_:X O *L 0 *C 30.075 57.800 +*I mux_right_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 22.445 66.980 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 22.483 66.980 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.935 66.980 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.980 66.935 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.980 57.845 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 29.025 57.800 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 30.038 57.800 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003640558 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003640558 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004440622 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004440622 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001137673 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001137673 + +*RES +0 mux_right_ipin_0\/mux_l1_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005761161 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.008116072 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001234281 //LENGTH 10.775 LUMPCC 0.000281082 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_0_:X O *L 0 *C 20.875 66.640 +*I mux_right_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 21.160 74.460 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 21.183 74.487 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 21.195 74.800 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 21.575 74.800 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 21.620 74.755 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 21.620 66.685 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 21.575 66.640 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 20.913 66.640 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.172955e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.44101e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.268056e-05 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003329407 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003329407 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.824869e-05 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.824869e-05 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000138594 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.947031e-06 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000138594 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.947031e-06 + +*RES +0 mux_right_ipin_0\/mux_l2_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0005915179 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.007205357 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003392857 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_0\/mux_l3_in_0_:A1 0.152 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002111487 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000361736 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_3_:X O *L 0 *C 14.895 75.140 +*I mux_right_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 12.710 75.140 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 12.748 75.140 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 14.857 75.140 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000179868 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.000179868 + +*RES +0 mux_right_ipin_0\/mux_l2_in_3_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001888812 //LENGTH 14.685 LUMPCC 0.0003126538 DR + +*CONN +*I mux_right_ipin_0\/mux_l3_in_0_:X O *L 0 *C 19.035 75.480 +*I mux_right_ipin_0\/mux_l4_in_0_:A1 I *L 0.005458 *C 11.365 80.502 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 11.500 80.445 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 11.500 80.920 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 17.435 80.920 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 17.480 80.875 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 17.480 75.525 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 17.525 75.480 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 18.998 75.480 + +*CAP +0 mux_right_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l4_in_0_:A1 2.620804e-05 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.114798e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0004398226 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004048827 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001922766 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001922766 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.000129272 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.000129272 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chany_top_in[17]:7 1.457744e-06 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_top_in[17]:6 1.457744e-06 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_top_in[17]:8 0.0001548691 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_top_in[17]:9 0.0001548691 + +*RES +0 mux_right_ipin_0\/mux_l3_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.001314732 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.004776786 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.005299107 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_0\/mux_l4_in_0_:A1 9.121623e-05 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004241072 + +*END + +*D_NET ropt_net_220 0.0004953012 //LENGTH 3.585 LUMPCC 0.0001035507 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 39.560 104.040 +*I ropt_mt_inst_823:A I *L 0.001766 *C 40.480 102.000 +*N ropt_net_220:2 *C 40.480 102.000 +*N ropt_net_220:3 *C 40.480 102.045 +*N ropt_net_220:4 *C 40.480 103.995 +*N ropt_net_220:5 *C 40.435 104.040 +*N ropt_net_220:6 *C 39.598 104.040 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 ropt_mt_inst_823:A 1e-06 +2 ropt_net_220:2 3.406136e-05 +3 ropt_net_220:3 8.897093e-05 +4 ropt_net_220:4 8.897093e-05 +5 ropt_net_220:5 8.887367e-05 +6 ropt_net_220:6 8.887367e-05 +7 ropt_net_220:4 chany_top_out[16]:2 5.177534e-05 +8 ropt_net_220:3 chany_top_out[16]:3 5.177534e-05 + +*RES +0 ropt_mt_inst_750:X ropt_net_220:6 0.152 +1 ropt_net_220:6 ropt_net_220:5 0.0007477679 +2 ropt_net_220:5 ropt_net_220:4 0.0045 +3 ropt_net_220:4 ropt_net_220:3 0.001741071 +4 ropt_net_220:2 ropt_mt_inst_823:A 0.152 +5 ropt_net_220:3 ropt_net_220:2 0.0045 + +*END + +*D_NET ropt_net_189 0.00175944 //LENGTH 11.465 LUMPCC 0.0006268442 DR + +*CONN +*I ropt_mt_inst_753:X O *L 0 *C 52.635 99.960 +*I ropt_mt_inst_792:A I *L 0.001766 *C 47.840 104.720 +*N ropt_net_189:2 *C 47.878 104.720 +*N ropt_net_189:3 *C 49.175 104.720 +*N ropt_net_189:4 *C 49.220 104.675 +*N ropt_net_189:5 *C 49.220 101.705 +*N ropt_net_189:6 *C 49.265 101.660 +*N ropt_net_189:7 *C 52.440 101.660 +*N ropt_net_189:8 *C 52.440 101.615 +*N ropt_net_189:9 *C 52.440 100.005 +*N ropt_net_189:10 *C 52.440 99.960 +*N ropt_net_189:11 *C 52.635 99.960 + +*CAP +0 ropt_mt_inst_753:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_189:2 9.879879e-05 +3 ropt_net_189:3 9.879879e-05 +4 ropt_net_189:4 0.000136356 +5 ropt_net_189:5 0.000136356 +6 ropt_net_189:6 0.0001940848 +7 ropt_net_189:7 0.0002267569 +8 ropt_net_189:8 6.799234e-05 +9 ropt_net_189:9 6.799234e-05 +10 ropt_net_189:10 5.39492e-05 +11 ropt_net_189:11 4.951108e-05 +12 ropt_net_189:6 chany_bottom_in[12]:7 0.0001293108 +13 ropt_net_189:7 chany_bottom_in[12]:6 0.0001293108 +14 ropt_net_189:2 chany_bottom_in[18]:9 3.480366e-05 +15 ropt_net_189:3 chany_bottom_in[18]:10 3.480366e-05 +16 ropt_net_189:4 chany_bottom_in[18]:11 7.919499e-05 +17 ropt_net_189:5 chany_bottom_in[18]:12 7.919499e-05 +18 ropt_net_189:8 chany_bottom_in[18]:11 5.193722e-07 +19 ropt_net_189:9 chany_bottom_in[18]:12 5.193722e-07 +20 ropt_net_189:6 ropt_net_147:3 1.490706e-05 +21 ropt_net_189:7 ropt_net_147:2 1.490706e-05 +22 ropt_net_189:8 ropt_net_147:4 5.468625e-05 +23 ropt_net_189:9 ropt_net_147:5 5.468625e-05 + +*RES +0 ropt_mt_inst_753:X ropt_net_189:11 0.152 +1 ropt_net_189:2 ropt_mt_inst_792:A 0.152 +2 ropt_net_189:3 ropt_net_189:2 0.001158482 +3 ropt_net_189:4 ropt_net_189:3 0.0045 +4 ropt_net_189:6 ropt_net_189:5 0.0045 +5 ropt_net_189:5 ropt_net_189:4 0.002651786 +6 ropt_net_189:7 ropt_net_189:6 0.002834822 +7 ropt_net_189:8 ropt_net_189:7 0.0045 +8 ropt_net_189:10 ropt_net_189:9 0.0045 +9 ropt_net_189:9 ropt_net_189:8 0.0014375 +10 ropt_net_189:11 ropt_net_189:10 0.0001059783 + +*END + +*D_NET chany_bottom_out[14] 0.00129486 //LENGTH 9.915 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 30.820 3.400 +*P chany_bottom_out[14] O *L 0.7423 *C 29.440 1.210 +*N chany_bottom_out[14]:2 *C 29.440 3.393 +*N chany_bottom_out[14]:3 *C 29.460 3.400 +*N chany_bottom_out[14]:4 *C 33.573 3.400 +*N chany_bottom_out[14]:5 *C 33.580 3.400 +*N chany_bottom_out[14]:6 *C 33.535 3.400 +*N chany_bottom_out[14]:7 *C 30.858 3.400 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 chany_bottom_out[14] 0.0001527554 +2 chany_bottom_out[14]:2 0.0001527554 +3 chany_bottom_out[14]:3 0.0002902667 +4 chany_bottom_out[14]:4 0.0002902667 +5 chany_bottom_out[14]:5 3.359911e-05 +6 chany_bottom_out[14]:6 0.0001871084 +7 chany_bottom_out[14]:7 0.0001871084 + +*RES +0 ropt_mt_inst_755:X chany_bottom_out[14]:7 0.152 +1 chany_bottom_out[14]:7 chany_bottom_out[14]:6 0.002390625 +2 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.0045 +3 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.00341 +4 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.0006442916 +5 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.00341 +6 chany_bottom_out[14]:2 chany_bottom_out[14] 0.000341925 + +*END + +*D_NET chany_bottom_out[6] 0.001502198 //LENGTH 11.855 LUMPCC 0.0001809271 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 71.760 10.200 +*P chany_bottom_out[6] O *L 0.7423 *C 69.460 1.325 +*N chany_bottom_out[6]:2 *C 69.920 1.360 +*N chany_bottom_out[6]:3 *C 69.920 9.815 +*N chany_bottom_out[6]:4 *C 69.920 9.860 +*N chany_bottom_out[6]:5 *C 69.920 10.200 +*N chany_bottom_out[6]:6 *C 71.722 10.200 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 chany_bottom_out[6] 3.275485e-05 +2 chany_bottom_out[6]:2 0.0004737939 +3 chany_bottom_out[6]:3 0.000441039 +4 chany_bottom_out[6]:4 6.765242e-05 +5 chany_bottom_out[6]:5 0.0001679484 +6 chany_bottom_out[6]:6 0.0001370824 +7 chany_bottom_out[6]:3 ropt_net_164:5 9.046357e-05 +8 chany_bottom_out[6]:2 ropt_net_164:4 9.046357e-05 + +*RES +0 ropt_mt_inst_791:X chany_bottom_out[6]:6 0.152 +1 chany_bottom_out[6]:6 chany_bottom_out[6]:5 0.001609375 +2 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.0045 +3 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.007549108 +4 chany_bottom_out[6]:5 chany_bottom_out[6]:4 0.0003035715 +5 chany_bottom_out[6]:2 chany_bottom_out[6] 0.0004107143 + +*END + +*D_NET ropt_net_217 0.0004706969 //LENGTH 4.265 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 63.020 104.720 +*I ropt_mt_inst_820:A I *L 0.001766 *C 63.940 102.000 +*N ropt_net_217:2 *C 63.903 102.000 +*N ropt_net_217:3 *C 63.065 102.000 +*N ropt_net_217:4 *C 63.020 102.045 +*N ropt_net_217:5 *C 63.020 104.675 +*N ropt_net_217:6 *C 63.020 104.720 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 ropt_mt_inst_820:A 1e-06 +2 ropt_net_217:2 6.877119e-05 +3 ropt_net_217:3 6.877119e-05 +4 ropt_net_217:4 0.0001474179 +5 ropt_net_217:5 0.0001474179 +6 ropt_net_217:6 3.631869e-05 + +*RES +0 ropt_mt_inst_757:X ropt_net_217:6 0.152 +1 ropt_net_217:2 ropt_mt_inst_820:A 0.152 +2 ropt_net_217:3 ropt_net_217:2 0.0007477678 +3 ropt_net_217:4 ropt_net_217:3 0.0045 +4 ropt_net_217:6 ropt_net_217:5 0.0045 +5 ropt_net_217:5 ropt_net_217:4 0.002348214 + +*END + +*D_NET chany_bottom_out[3] 0.0008845453 //LENGTH 6.150 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_793:X O *L 0 *C 48.495 3.740 +*P chany_bottom_out[3] O *L 0.7423 *C 45.540 1.290 +*N chany_bottom_out[3]:2 *C 45.540 3.355 +*N chany_bottom_out[3]:3 *C 45.585 3.400 +*N chany_bottom_out[3]:4 *C 46.920 3.400 +*N chany_bottom_out[3]:5 *C 46.920 3.740 +*N chany_bottom_out[3]:6 *C 48.458 3.740 + +*CAP +0 ropt_mt_inst_793:X 1e-06 +1 chany_bottom_out[3] 0.0001342927 +2 chany_bottom_out[3]:2 0.0001342927 +3 chany_bottom_out[3]:3 0.0001204123 +4 chany_bottom_out[3]:4 0.0001463974 +5 chany_bottom_out[3]:5 0.0001870677 +6 chany_bottom_out[3]:6 0.0001610825 + +*RES +0 ropt_mt_inst_793:X chany_bottom_out[3]:6 0.152 +1 chany_bottom_out[3]:6 chany_bottom_out[3]:5 0.001372768 +2 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0045 +3 chany_bottom_out[3]:2 chany_bottom_out[3] 0.00184375 +4 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.001191964 +5 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.0003035715 + +*END + +*D_NET ropt_net_219 0.0006869878 //LENGTH 5.950 LUMPCC 0.000154936 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 60.720 6.800 +*I ropt_mt_inst_822:A I *L 0.001766 *C 63.020 4.080 +*N ropt_net_219:2 *C 62.983 4.080 +*N ropt_net_219:3 *C 62.145 4.080 +*N ropt_net_219:4 *C 62.100 4.125 +*N ropt_net_219:5 *C 62.100 6.755 +*N ropt_net_219:6 *C 62.055 6.800 +*N ropt_net_219:7 *C 60.758 6.800 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 ropt_mt_inst_822:A 1e-06 +2 ropt_net_219:2 6.868381e-05 +3 ropt_net_219:3 6.868381e-05 +4 ropt_net_219:4 0.0001154841 +5 ropt_net_219:5 0.0001154841 +6 ropt_net_219:6 8.085796e-05 +7 ropt_net_219:7 8.085796e-05 +8 ropt_net_219:4 ropt_net_198:4 2.661105e-05 +9 ropt_net_219:6 ropt_net_198:6 1.353028e-05 +10 ropt_net_219:5 ropt_net_198:3 2.661105e-05 +11 ropt_net_219:7 ropt_net_198:5 1.353028e-05 +12 ropt_net_219:4 chany_bottom_out[8] 3.732668e-05 +13 ropt_net_219:5 chany_bottom_out[8]:2 3.732668e-05 + +*RES +0 ropt_mt_inst_760:X ropt_net_219:7 0.152 +1 ropt_net_219:2 ropt_mt_inst_822:A 0.152 +2 ropt_net_219:3 ropt_net_219:2 0.0007477679 +3 ropt_net_219:4 ropt_net_219:3 0.0045 +4 ropt_net_219:6 ropt_net_219:5 0.0045 +5 ropt_net_219:5 ropt_net_219:4 0.002348214 +6 ropt_net_219:7 ropt_net_219:6 0.001158482 + +*END + +*D_NET chany_bottom_out[9] 0.001015824 //LENGTH 9.310 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 55.660 6.120 +*P chany_bottom_out[9] O *L 0.7423 *C 51.980 1.290 +*N chany_bottom_out[9]:2 *C 51.980 1.655 +*N chany_bottom_out[9]:3 *C 52.025 1.700 +*N chany_bottom_out[9]:4 *C 55.615 1.700 +*N chany_bottom_out[9]:5 *C 55.660 1.745 +*N chany_bottom_out[9]:6 *C 55.660 6.075 +*N chany_bottom_out[9]:7 *C 55.660 6.120 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 chany_bottom_out[9] 3.763087e-05 +2 chany_bottom_out[9]:2 3.763087e-05 +3 chany_bottom_out[9]:3 0.0002172763 +4 chany_bottom_out[9]:4 0.0002172763 +5 chany_bottom_out[9]:5 0.000237031 +6 chany_bottom_out[9]:6 0.000237031 +7 chany_bottom_out[9]:7 3.094743e-05 + +*RES +0 ropt_mt_inst_794:X chany_bottom_out[9]:7 0.152 +1 chany_bottom_out[9]:7 chany_bottom_out[9]:6 0.0045 +2 chany_bottom_out[9]:6 chany_bottom_out[9]:5 0.003866071 +3 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.003205357 +4 chany_bottom_out[9]:5 chany_bottom_out[9]:4 0.0045 +5 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +6 chany_bottom_out[9]:2 chany_bottom_out[9] 0.0003258929 + +*END + +*D_NET ropt_net_194 0.001113093 //LENGTH 9.250 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 81.580 6.120 +*I ropt_mt_inst_797:A I *L 0.001767 *C 76.820 4.080 +*N ropt_net_194:2 *C 76.820 4.080 +*N ropt_net_194:3 *C 76.820 4.035 +*N ropt_net_194:4 *C 76.820 3.445 +*N ropt_net_194:5 *C 76.865 3.400 +*N ropt_net_194:6 *C 81.375 3.400 +*N ropt_net_194:7 *C 81.420 3.445 +*N ropt_net_194:8 *C 81.420 6.075 +*N ropt_net_194:9 *C 81.420 6.120 +*N ropt_net_194:10 *C 81.580 6.120 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_194:2 3.037605e-05 +3 ropt_net_194:3 5.042494e-05 +4 ropt_net_194:4 5.042494e-05 +5 ropt_net_194:5 0.000311181 +6 ropt_net_194:6 0.000311181 +7 ropt_net_194:7 0.0001286222 +8 ropt_net_194:8 0.0001286222 +9 ropt_net_194:9 5.031986e-05 +10 ropt_net_194:10 4.994067e-05 + +*RES +0 ropt_mt_inst_764:X ropt_net_194:10 0.152 +1 ropt_net_194:2 ropt_mt_inst_797:A 0.152 +2 ropt_net_194:3 ropt_net_194:2 0.0045 +3 ropt_net_194:5 ropt_net_194:4 0.0045 +4 ropt_net_194:4 ropt_net_194:3 0.0005267857 +5 ropt_net_194:6 ropt_net_194:5 0.004026786 +6 ropt_net_194:7 ropt_net_194:6 0.0045 +7 ropt_net_194:9 ropt_net_194:8 0.0045 +8 ropt_net_194:8 ropt_net_194:7 0.002348214 +9 ropt_net_194:10 ropt_net_194:9 8.695653e-05 + +*END + +*D_NET chany_bottom_out[13] 0.001353903 //LENGTH 10.640 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 21.815 3.400 +*P chany_bottom_out[13] O *L 0.7423 *C 20.240 1.210 +*N chany_bottom_out[13]:2 *C 20.240 3.393 +*N chany_bottom_out[13]:3 *C 20.260 3.400 +*N chany_bottom_out[13]:4 *C 24.832 3.400 +*N chany_bottom_out[13]:5 *C 24.840 3.400 +*N chany_bottom_out[13]:6 *C 24.795 3.400 +*N chany_bottom_out[13]:7 *C 21.853 3.400 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 chany_bottom_out[13] 0.0001345312 +2 chany_bottom_out[13]:2 0.0001345312 +3 chany_bottom_out[13]:3 0.0003299408 +4 chany_bottom_out[13]:4 0.0003299408 +5 chany_bottom_out[13]:5 3.271456e-05 +6 chany_bottom_out[13]:6 0.0001956222 +7 chany_bottom_out[13]:7 0.0001956222 + +*RES +0 ropt_mt_inst_766:X chany_bottom_out[13]:7 0.152 +1 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.00341 +2 chany_bottom_out[13]:2 chany_bottom_out[13] 0.000341925 +3 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.00341 +4 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.0007163583 +5 chany_bottom_out[13]:6 chany_bottom_out[13]:5 0.0045 +6 chany_bottom_out[13]:7 chany_bottom_out[13]:6 0.002627232 + +*END + +*D_NET ropt_net_190 0.001965456 //LENGTH 12.395 LUMPCC 0.001065826 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 50.795 8.840 +*I ropt_mt_inst_793:A I *L 0.001766 *C 44.620 4.080 +*N ropt_net_190:2 *C 44.657 4.080 +*N ropt_net_190:3 *C 45.080 4.080 +*N ropt_net_190:4 *C 45.080 4.420 +*N ropt_net_190:5 *C 49.635 4.420 +*N ropt_net_190:6 *C 49.680 4.420 +*N ropt_net_190:7 *C 49.680 8.795 +*N ropt_net_190:8 *C 49.725 8.840 +*N ropt_net_190:9 *C 50.758 8.840 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 ropt_mt_inst_793:A 1e-06 +2 ropt_net_190:2 2.097932e-05 +3 ropt_net_190:3 4.457681e-05 +4 ropt_net_190:4 0.0001588633 +5 ropt_net_190:5 0.0001352658 +6 ropt_net_190:6 0.0001880881 +7 ropt_net_190:7 0.0001575464 +8 ropt_net_190:8 9.615512e-05 +9 ropt_net_190:9 9.615512e-05 +10 ropt_net_190:6 chany_bottom_in[3] 0.0001309609 +11 ropt_net_190:7 chany_bottom_in[3]:20 0.0001309609 +12 ropt_net_190:2 chany_bottom_in[11]:13 5.608892e-06 +13 ropt_net_190:5 chany_bottom_in[11]:14 0.0001703668 +14 ropt_net_190:6 chany_bottom_in[11] 1.43589e-06 +15 ropt_net_190:7 chany_bottom_in[11]:15 1.43589e-06 +16 ropt_net_190:3 chany_bottom_in[11]:14 5.608892e-06 +17 ropt_net_190:4 chany_bottom_in[11]:13 0.0001703668 +18 ropt_net_190:2 chany_top_in[19]:5 2.438549e-05 +19 ropt_net_190:5 chany_top_in[19]:2 0.0001406068 +20 ropt_net_190:3 chany_top_in[19]:4 2.799532e-05 +21 ropt_net_190:4 chany_top_in[19]:3 0.0001442167 +22 ropt_net_190:6 chany_bottom_out[10] 5.59383e-05 +23 ropt_net_190:7 chany_bottom_out[10]:2 5.59383e-05 + +*RES +0 ropt_mt_inst_769:X ropt_net_190:9 0.152 +1 ropt_net_190:2 ropt_mt_inst_793:A 0.152 +2 ropt_net_190:5 ropt_net_190:4 0.004066965 +3 ropt_net_190:6 ropt_net_190:5 0.0045 +4 ropt_net_190:8 ropt_net_190:7 0.0045 +5 ropt_net_190:7 ropt_net_190:6 0.00390625 +6 ropt_net_190:9 ropt_net_190:8 0.0009218751 +7 ropt_net_190:3 ropt_net_190:2 0.0003772322 +8 ropt_net_190:4 ropt_net_190:3 0.0003035715 + +*END + +*D_NET chany_bottom_out[15] 0.001995326 //LENGTH 16.160 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 52.440 8.840 +*P chany_bottom_out[15] O *L 0.7423 *C 49.680 1.210 +*N chany_bottom_out[15]:2 *C 49.680 6.113 +*N chany_bottom_out[15]:3 *C 49.700 6.120 +*N chany_bottom_out[15]:4 *C 54.733 6.120 +*N chany_bottom_out[15]:5 *C 54.740 6.178 +*N chany_bottom_out[15]:6 *C 54.740 8.795 +*N chany_bottom_out[15]:7 *C 54.695 8.840 +*N chany_bottom_out[15]:8 *C 52.477 8.840 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 chany_bottom_out[15] 0.0003099672 +2 chany_bottom_out[15]:2 0.0003099672 +3 chany_bottom_out[15]:3 0.0003493748 +4 chany_bottom_out[15]:4 0.0003493748 +5 chany_bottom_out[15]:5 0.0001653609 +6 chany_bottom_out[15]:6 0.0001653609 +7 chany_bottom_out[15]:7 0.0001724598 +8 chany_bottom_out[15]:8 0.0001724598 + +*RES +0 ropt_mt_inst_772:X chany_bottom_out[15]:8 0.152 +1 chany_bottom_out[15]:8 chany_bottom_out[15]:7 0.001979911 +2 chany_bottom_out[15]:7 chany_bottom_out[15]:6 0.0045 +3 chany_bottom_out[15]:6 chany_bottom_out[15]:5 0.002337053 +4 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.00341 +5 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.0007884249 +6 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.00341 +7 chany_bottom_out[15]:2 chany_bottom_out[15] 0.0007680582 + +*END + +*D_NET chany_bottom_out[16] 0.0004871045 //LENGTH 3.415 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 59.340 3.740 +*P chany_bottom_out[16] O *L 0.7423 *C 58.880 1.285 +*N chany_bottom_out[16]:2 *C 58.880 3.393 +*N chany_bottom_out[16]:3 *C 58.895 3.400 +*N chany_bottom_out[16]:4 *C 59.338 3.400 +*N chany_bottom_out[16]:5 *C 59.340 3.400 +*N chany_bottom_out[16]:6 *C 59.340 3.740 +*N chany_bottom_out[16]:7 *C 59.340 3.740 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 chany_bottom_out[16] 0.0001364846 +2 chany_bottom_out[16]:2 0.0001364846 +3 chany_bottom_out[16]:3 4.385521e-05 +4 chany_bottom_out[16]:4 4.385521e-05 +5 chany_bottom_out[16]:5 4.848673e-05 +6 chany_bottom_out[16]:6 4.511647e-05 +7 chany_bottom_out[16]:7 3.182168e-05 + +*RES +0 ropt_mt_inst_773:X chany_bottom_out[16]:7 0.152 +1 chany_bottom_out[16]:7 chany_bottom_out[16]:6 0.0045 +2 chany_bottom_out[16]:6 chany_bottom_out[16]:5 0.0001634615 +3 chany_bottom_out[16]:5 chany_bottom_out[16]:4 0.00341 +4 chany_bottom_out[16]:4 chany_bottom_out[16]:3 6.499219e-05 +5 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.00341 +6 chany_bottom_out[16]:2 chany_bottom_out[16] 0.000330175 + +*END + +*D_NET ropt_net_186 0.00195463 //LENGTH 13.205 LUMPCC 0.0009320843 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 62.675 102.680 +*I ropt_mt_inst_789:A I *L 0.001766 *C 52.440 104.720 +*N ropt_net_186:2 *C 52.477 104.720 +*N ropt_net_186:3 *C 55.615 104.720 +*N ropt_net_186:4 *C 55.660 104.675 +*N ropt_net_186:5 *C 55.660 102.725 +*N ropt_net_186:6 *C 55.705 102.680 +*N ropt_net_186:7 *C 62.638 102.680 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_186:2 6.987591e-05 +3 ropt_net_186:3 6.987591e-05 +4 ropt_net_186:4 5.366077e-05 +5 ropt_net_186:5 5.366077e-05 +6 ropt_net_186:6 0.0003867359 +7 ropt_net_186:7 0.0003867359 +8 ropt_net_186:6 chany_bottom_in[10]:7 0.0001266999 +9 ropt_net_186:7 chany_bottom_in[10]:6 0.0001266999 +10 ropt_net_186:4 chany_top_in[0]:19 5.992796e-05 +11 ropt_net_186:5 chany_top_in[0]:18 5.992796e-05 +12 ropt_net_186:4 chany_top_in[16]:19 5.992796e-05 +13 ropt_net_186:5 chany_top_in[16]:18 5.992796e-05 +14 ropt_net_186:2 chany_top_out[10]:3 0.0001074625 +15 ropt_net_186:3 chany_top_out[10]:4 0.0001074625 +16 ropt_net_186:2 chany_top_out[6]:3 0.0001120239 +17 ropt_net_186:3 chany_top_out[6]:4 0.0001120239 + +*RES +0 ropt_mt_inst_776:X ropt_net_186:7 0.152 +1 ropt_net_186:2 ropt_mt_inst_789:A 0.152 +2 ropt_net_186:3 ropt_net_186:2 0.002801339 +3 ropt_net_186:4 ropt_net_186:3 0.0045 +4 ropt_net_186:6 ropt_net_186:5 0.0045 +5 ropt_net_186:5 ropt_net_186:4 0.001741071 +6 ropt_net_186:7 ropt_net_186:6 0.006189733 + +*END + +*D_NET ropt_net_209 0.0006381796 //LENGTH 4.800 LUMPCC 0.0002116017 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 70.030 9.180 +*I ropt_mt_inst_812:A I *L 0.001767 *C 68.540 6.800 +*N ropt_net_209:2 *C 68.578 6.800 +*N ropt_net_209:3 *C 68.955 6.800 +*N ropt_net_209:4 *C 69.000 6.845 +*N ropt_net_209:5 *C 69.000 9.135 +*N ropt_net_209:6 *C 69.045 9.180 +*N ropt_net_209:7 *C 69.993 9.180 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 ropt_mt_inst_812:A 1e-06 +2 ropt_net_209:2 3.321524e-05 +3 ropt_net_209:3 3.321524e-05 +4 ropt_net_209:4 8.620178e-05 +5 ropt_net_209:5 8.620178e-05 +6 ropt_net_209:6 9.287195e-05 +7 ropt_net_209:7 9.287195e-05 +8 ropt_net_209:4 ropt_net_164:4 6.753401e-05 +9 ropt_net_209:5 ropt_net_164:5 6.753401e-05 +10 ropt_net_209:2 chany_bottom_out[7]:3 1.194506e-05 +11 ropt_net_209:3 chany_bottom_out[7]:4 1.194506e-05 +12 ropt_net_209:4 chany_bottom_out[7] 2.632179e-05 +13 ropt_net_209:5 chany_bottom_out[7]:2 2.632179e-05 + +*RES +0 ropt_mt_inst_779:X ropt_net_209:7 0.152 +1 ropt_net_209:2 ropt_mt_inst_812:A 0.152 +2 ropt_net_209:3 ropt_net_209:2 0.0003370536 +3 ropt_net_209:4 ropt_net_209:3 0.0045 +4 ropt_net_209:6 ropt_net_209:5 0.0045 +5 ropt_net_209:5 ropt_net_209:4 0.002044643 +6 ropt_net_209:7 ropt_net_209:6 0.0008459822 + +*END + +*D_NET ropt_net_211 0.001044328 //LENGTH 8.635 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 7.095 85.000 +*I ropt_mt_inst_814:A I *L 0.001767 *C 3.220 82.960 +*N ropt_net_211:2 *C 3.258 82.960 +*N ropt_net_211:3 *C 4.095 82.960 +*N ropt_net_211:4 *C 4.140 82.915 +*N ropt_net_211:5 *C 4.140 82.325 +*N ropt_net_211:6 *C 4.185 82.280 +*N ropt_net_211:7 *C 6.855 82.280 +*N ropt_net_211:8 *C 6.900 82.325 +*N ropt_net_211:9 *C 6.900 84.955 +*N ropt_net_211:10 *C 6.900 85.000 +*N ropt_net_211:11 *C 7.095 85.000 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 ropt_mt_inst_814:A 1e-06 +2 ropt_net_211:2 6.570002e-05 +3 ropt_net_211:3 6.570002e-05 +4 ropt_net_211:4 6.548707e-05 +5 ropt_net_211:5 6.548707e-05 +6 ropt_net_211:6 0.0001845595 +7 ropt_net_211:7 0.0001845595 +8 ropt_net_211:8 0.0001475971 +9 ropt_net_211:9 0.0001475971 +10 ropt_net_211:10 5.691372e-05 +11 ropt_net_211:11 5.872689e-05 + +*RES +0 ropt_mt_inst_780:X ropt_net_211:11 0.152 +1 ropt_net_211:11 ropt_net_211:10 0.0001059783 +2 ropt_net_211:10 ropt_net_211:9 0.0045 +3 ropt_net_211:9 ropt_net_211:8 0.002348214 +4 ropt_net_211:7 ropt_net_211:6 0.002383929 +5 ropt_net_211:8 ropt_net_211:7 0.0045 +6 ropt_net_211:6 ropt_net_211:5 0.0045 +7 ropt_net_211:5 ropt_net_211:4 0.0005267857 +8 ropt_net_211:3 ropt_net_211:2 0.0007477679 +9 ropt_net_211:4 ropt_net_211:3 0.0045 +10 ropt_net_211:2 ropt_mt_inst_814:A 0.152 + +*END + +*D_NET ropt_net_212 0.001567192 //LENGTH 14.490 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 81.580 102.680 +*I ropt_mt_inst_815:A I *L 0.001767 *C 75.440 104.720 +*N ropt_net_212:2 *C 75.440 104.720 +*N ropt_net_212:3 *C 75.440 104.765 +*N ropt_net_212:4 *C 75.440 107.055 +*N ropt_net_212:5 *C 75.440 107.100 +*N ropt_net_212:6 *C 79.535 107.100 +*N ropt_net_212:7 *C 79.580 107.055 +*N ropt_net_212:8 *C 79.580 102.725 +*N ropt_net_212:9 *C 79.625 102.680 +*N ropt_net_212:10 *C 81.543 102.680 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_212:2 3.146576e-05 +3 ropt_net_212:3 0.0001355219 +4 ropt_net_212:4 0.0001355219 +5 ropt_net_212:5 0.0002820046 +6 ropt_net_212:6 0.0002505388 +7 ropt_net_212:7 0.0002264795 +8 ropt_net_212:8 0.0002264795 +9 ropt_net_212:9 0.00013859 +10 ropt_net_212:10 0.00013859 + +*RES +0 ropt_mt_inst_783:X ropt_net_212:10 0.152 +1 ropt_net_212:10 ropt_net_212:9 0.001712054 +2 ropt_net_212:9 ropt_net_212:8 0.0045 +3 ropt_net_212:8 ropt_net_212:7 0.003866072 +4 ropt_net_212:6 ropt_net_212:5 0.00365625 +5 ropt_net_212:7 ropt_net_212:6 0.0045 +6 ropt_net_212:5 ropt_net_212:4 0.0045 +7 ropt_net_212:4 ropt_net_212:3 0.002044643 +8 ropt_net_212:2 ropt_mt_inst_815:A 0.152 +9 ropt_net_212:3 ropt_net_212:2 0.0045 + +*END + +*D_NET ropt_net_201 0.0006626218 //LENGTH 5.460 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 13.535 102.680 +*I ropt_mt_inst_804:A I *L 0.001767 *C 10.835 104.720 +*N ropt_net_201:2 *C 10.873 104.720 +*N ropt_net_201:3 *C 13.295 104.720 +*N ropt_net_201:4 *C 13.340 104.675 +*N ropt_net_201:5 *C 13.340 102.725 +*N ropt_net_201:6 *C 13.340 102.680 +*N ropt_net_201:7 *C 13.535 102.680 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 ropt_mt_inst_804:A 1e-06 +2 ropt_net_201:2 0.0001462428 +3 ropt_net_201:3 0.0001462428 +4 ropt_net_201:4 0.0001311256 +5 ropt_net_201:5 0.0001311256 +6 ropt_net_201:6 5.316944e-05 +7 ropt_net_201:7 5.271565e-05 + +*RES +0 ropt_mt_inst_784:X ropt_net_201:7 0.152 +1 ropt_net_201:7 ropt_net_201:6 0.0001059783 +2 ropt_net_201:6 ropt_net_201:5 0.0045 +3 ropt_net_201:5 ropt_net_201:4 0.001741072 +4 ropt_net_201:3 ropt_net_201:2 0.002162947 +5 ropt_net_201:4 ropt_net_201:3 0.0045 +6 ropt_net_201:2 ropt_mt_inst_804:A 0.152 + +*END + +*D_NET BUF_net_51 0.00154382 //LENGTH 13.915 LUMPCC 0 DR + +*CONN +*I BUFT_RR_51:X O *L 0 *C 66.240 93.840 +*I BUFT_P_120:A I *L 0.001766 *C 70.655 99.280 +*N BUF_net_51:2 *C 70.693 99.280 +*N BUF_net_51:3 *C 72.175 99.280 +*N BUF_net_51:4 *C 72.220 99.235 +*N BUF_net_51:5 *C 72.220 93.885 +*N BUF_net_51:6 *C 72.175 93.840 +*N BUF_net_51:7 *C 66.278 93.840 + +*CAP +0 BUFT_RR_51:X 1e-06 +1 BUFT_P_120:A 1e-06 +2 BUF_net_51:2 0.0001111734 +3 BUF_net_51:3 0.0001111734 +4 BUF_net_51:4 0.0002949965 +5 BUF_net_51:5 0.0002949965 +6 BUF_net_51:6 0.0003647402 +7 BUF_net_51:7 0.0003647402 + +*RES +0 BUFT_RR_51:X BUF_net_51:7 0.152 +1 BUF_net_51:7 BUF_net_51:6 0.005265625 +2 BUF_net_51:6 BUF_net_51:5 0.0045 +3 BUF_net_51:5 BUF_net_51:4 0.004776786 +4 BUF_net_51:3 BUF_net_51:2 0.001323661 +5 BUF_net_51:4 BUF_net_51:3 0.0045 +6 BUF_net_51:2 BUFT_P_120:A 0.152 + +*END + +*D_NET ropt_net_184 0.001717623 //LENGTH 11.285 LUMPCC 0.0005650119 DR + +*CONN +*I BUFT_RR_55:X O *L 0 *C 21.160 101.660 +*I ropt_mt_inst_788:A I *L 0.001766 *C 29.440 99.280 +*N ropt_net_184:2 *C 29.440 99.280 +*N ropt_net_184:3 *C 29.440 99.325 +*N ropt_net_184:4 *C 29.440 101.615 +*N ropt_net_184:5 *C 29.395 101.660 +*N ropt_net_184:6 *C 21.198 101.660 + +*CAP +0 BUFT_RR_55:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_184:2 3.477091e-05 +3 ropt_net_184:3 0.0001479069 +4 ropt_net_184:4 0.0001479069 +5 ropt_net_184:5 0.0004100133 +6 ropt_net_184:6 0.0004100133 +7 ropt_net_184:6 chany_bottom_in[14]:10 0.0002053575 +8 ropt_net_184:5 chany_bottom_in[14]:9 0.0002053575 +9 ropt_net_184:4 chany_bottom_in[14]:7 3.158269e-07 +10 ropt_net_184:3 chany_bottom_in[14]:8 3.158269e-07 +11 ropt_net_184:6 ropt_net_173:2 7.68326e-05 +12 ropt_net_184:5 ropt_net_173:3 7.68326e-05 + +*RES +0 BUFT_RR_55:X ropt_net_184:6 0.152 +1 ropt_net_184:6 ropt_net_184:5 0.007319197 +2 ropt_net_184:5 ropt_net_184:4 0.0045 +3 ropt_net_184:4 ropt_net_184:3 0.002044643 +4 ropt_net_184:2 ropt_mt_inst_788:A 0.152 +5 ropt_net_184:3 ropt_net_184:2 0.0045 + +*END + +*D_NET ropt_net_165 0.001712283 //LENGTH 15.690 LUMPCC 0.0006446092 DR + +*CONN +*I BUFT_RR_59:X O *L 0 *C 46.000 22.440 +*I ropt_mt_inst_769:A I *L 0.001766 *C 46.920 9.520 +*N ropt_net_165:2 *C 46.883 9.520 +*N ropt_net_165:3 *C 45.585 9.520 +*N ropt_net_165:4 *C 45.540 9.565 +*N ropt_net_165:5 *C 45.540 22.395 +*N ropt_net_165:6 *C 45.585 22.440 +*N ropt_net_165:7 *C 45.963 22.440 + +*CAP +0 BUFT_RR_59:X 1e-06 +1 ropt_mt_inst_769:A 1e-06 +2 ropt_net_165:2 9.587017e-05 +3 ropt_net_165:3 9.587017e-05 +4 ropt_net_165:4 0.0003896693 +5 ropt_net_165:5 0.0003896693 +6 ropt_net_165:6 4.729769e-05 +7 ropt_net_165:7 4.729769e-05 +8 ropt_net_165:4 chany_bottom_in[5] 0.000181038 +9 ropt_net_165:5 chany_bottom_in[5]:22 0.000181038 +10 ropt_net_165:4 chany_top_in[1]:13 0.0001412666 +11 ropt_net_165:5 chany_top_in[1]:14 0.0001412666 + +*RES +0 BUFT_RR_59:X ropt_net_165:7 0.152 +1 ropt_net_165:2 ropt_mt_inst_769:A 0.152 +2 ropt_net_165:3 ropt_net_165:2 0.001158482 +3 ropt_net_165:4 ropt_net_165:3 0.0045 +4 ropt_net_165:6 ropt_net_165:5 0.0045 +5 ropt_net_165:5 ropt_net_165:4 0.01145536 +6 ropt_net_165:7 ropt_net_165:6 0.0003370536 + +*END + +*D_NET ropt_net_166 0.00150776 //LENGTH 13.890 LUMPCC 0.0003107992 DR + +*CONN +*I BUFT_RR_61:X O *L 0 *C 31.280 19.720 +*I ropt_mt_inst_770:A I *L 0.001766 *C 29.440 9.520 +*N ropt_net_166:2 *C 29.402 9.520 +*N ropt_net_166:3 *C 29.025 9.520 +*N ropt_net_166:4 *C 28.980 9.565 +*N ropt_net_166:5 *C 28.980 19.675 +*N ropt_net_166:6 *C 29.025 19.720 +*N ropt_net_166:7 *C 31.243 19.720 + +*CAP +0 BUFT_RR_61:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_166:2 4.272623e-05 +3 ropt_net_166:3 4.272623e-05 +4 ropt_net_166:4 0.0004013247 +5 ropt_net_166:5 0.0004013247 +6 ropt_net_166:6 0.0001534296 +7 ropt_net_166:7 0.0001534296 +8 ropt_net_166:5 chany_top_in[18]:7 2.247613e-05 +9 ropt_net_166:5 chany_top_in[18]:11 0.0001329235 +10 ropt_net_166:4 chany_top_in[18]:6 2.247613e-05 +11 ropt_net_166:4 chany_top_in[18]:10 0.0001329235 + +*RES +0 BUFT_RR_61:X ropt_net_166:7 0.152 +1 ropt_net_166:7 ropt_net_166:6 0.001979911 +2 ropt_net_166:6 ropt_net_166:5 0.0045 +3 ropt_net_166:5 ropt_net_166:4 0.009026786 +4 ropt_net_166:3 ropt_net_166:2 0.0003370536 +5 ropt_net_166:4 ropt_net_166:3 0.0045 +6 ropt_net_166:2 ropt_mt_inst_770:A 0.152 + +*END + +*D_NET chany_bottom_out[8] 0.001169493 //LENGTH 10.510 LUMPCC 7.465336e-05 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 65.515 8.840 +*P chany_bottom_out[8] O *L 0.7423 *C 63.020 1.290 +*N chany_bottom_out[8]:2 *C 63.020 8.795 +*N chany_bottom_out[8]:3 *C 63.065 8.840 +*N chany_bottom_out[8]:4 *C 65.478 8.840 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 chany_bottom_out[8] 0.0003694052 +2 chany_bottom_out[8]:2 0.0003694052 +3 chany_bottom_out[8]:3 0.0001775145 +4 chany_bottom_out[8]:4 0.0001775145 +5 chany_bottom_out[8] ropt_net_219:4 3.732668e-05 +6 chany_bottom_out[8]:2 ropt_net_219:5 3.732668e-05 + +*RES +0 ropt_mt_inst_801:X chany_bottom_out[8]:4 0.152 +1 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.002154018 +2 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0045 +3 chany_bottom_out[8]:2 chany_bottom_out[8] 0.006700893 + +*END + +*D_NET chany_top_out[19] 0.001534876 //LENGTH 11.845 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_803:X O *L 0 *C 25.760 98.600 +*P chany_top_out[19] O *L 0.7423 *C 24.840 107.475 +*N chany_top_out[19]:2 *C 24.840 107.440 +*N chany_top_out[19]:3 *C 24.840 106.760 +*N chany_top_out[19]:4 *C 25.300 106.760 +*N chany_top_out[19]:5 *C 25.300 98.985 +*N chany_top_out[19]:6 *C 25.345 98.940 +*N chany_top_out[19]:7 *C 26.220 98.940 +*N chany_top_out[19]:8 *C 26.220 98.600 +*N chany_top_out[19]:9 *C 25.798 98.600 + +*CAP +0 ropt_mt_inst_803:X 1e-06 +1 chany_top_out[19] 9.512957e-06 +2 chany_top_out[19]:2 5.400327e-05 +3 chany_top_out[19]:3 7.596534e-05 +4 chany_top_out[19]:4 0.000589585 +5 chany_top_out[19]:5 0.00055811 +6 chany_top_out[19]:6 7.320989e-05 +7 chany_top_out[19]:7 9.963709e-05 +8 chany_top_out[19]:8 5.013965e-05 +9 chany_top_out[19]:9 2.371245e-05 + +*RES +0 ropt_mt_inst_803:X chany_top_out[19]:9 0.152 +1 chany_top_out[19]:9 chany_top_out[19]:8 0.0003772322 +2 chany_top_out[19]:6 chany_top_out[19]:5 0.0045 +3 chany_top_out[19]:5 chany_top_out[19]:4 0.006941965 +4 chany_top_out[19]:7 chany_top_out[19]:6 0.00078125 +5 chany_top_out[19]:8 chany_top_out[19]:7 0.0003035715 +6 chany_top_out[19]:3 chany_top_out[19]:2 0.0006071429 +7 chany_top_out[19]:4 chany_top_out[19]:3 0.0004107143 +8 chany_top_out[19]:2 chany_top_out[19] 3.125e-05 + +*END + +*D_NET chany_top_out[17] 0.001196074 //LENGTH 8.955 LUMPCC 0.0001307426 DR + +*CONN +*I ropt_mt_inst_805:X O *L 0 *C 32.200 101.320 +*P chany_top_out[17] O *L 0.7423 *C 29.900 107.510 +*N chany_top_out[17]:2 *C 29.900 101.365 +*N chany_top_out[17]:3 *C 29.945 101.320 +*N chany_top_out[17]:4 *C 32.163 101.320 + +*CAP +0 ropt_mt_inst_805:X 1e-06 +1 chany_top_out[17] 0.0003754804 +2 chany_top_out[17]:2 0.0003754804 +3 chany_top_out[17]:3 0.0001566854 +4 chany_top_out[17]:4 0.0001566854 +5 chany_top_out[17] ropt_net_181:5 8.541182e-06 +6 chany_top_out[17]:4 ropt_net_181:3 5.683014e-05 +7 chany_top_out[17]:3 ropt_net_181:4 5.683014e-05 +8 chany_top_out[17]:2 ropt_net_181:6 8.541182e-06 + +*RES +0 ropt_mt_inst_805:X chany_top_out[17]:4 0.152 +1 chany_top_out[17]:4 chany_top_out[17]:3 0.001979911 +2 chany_top_out[17]:3 chany_top_out[17]:2 0.0045 +3 chany_top_out[17]:2 chany_top_out[17] 0.005486608 + +*END + +*D_NET chany_top_out[1] 0.0008258212 //LENGTH 6.955 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 15.180 102.680 +*P chany_top_out[1] O *L 0.7423 *C 14.720 107.510 +*N chany_top_out[1]:2 *C 14.720 106.080 +*N chany_top_out[1]:3 *C 14.260 106.080 +*N chany_top_out[1]:4 *C 14.260 102.725 +*N chany_top_out[1]:5 *C 14.305 102.680 +*N chany_top_out[1]:6 *C 15.143 102.680 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 chany_top_out[1] 0.0001006802 +2 chany_top_out[1]:2 0.0001296365 +3 chany_top_out[1]:3 0.0002332304 +4 chany_top_out[1]:4 0.0002042741 +5 chany_top_out[1]:5 7.850008e-05 +6 chany_top_out[1]:6 7.850008e-05 + +*RES +0 ropt_mt_inst_808:X chany_top_out[1]:6 0.152 +1 chany_top_out[1]:6 chany_top_out[1]:5 0.0007477679 +2 chany_top_out[1]:5 chany_top_out[1]:4 0.0045 +3 chany_top_out[1]:4 chany_top_out[1]:3 0.002995536 +4 chany_top_out[1]:3 chany_top_out[1]:2 0.0004107143 +5 chany_top_out[1]:2 chany_top_out[1] 0.001276786 + +*END + +*D_NET chany_top_out[13] 0.001041483 //LENGTH 8.605 LUMPCC 8.748686e-05 DR + +*CONN +*I ropt_mt_inst_811:X O *L 0 *C 74.060 101.320 +*P chany_top_out[13] O *L 0.7423 *C 72.220 107.510 +*N chany_top_out[13]:2 *C 72.220 101.705 +*N chany_top_out[13]:3 *C 72.265 101.660 +*N chany_top_out[13]:4 *C 74.060 101.660 +*N chany_top_out[13]:5 *C 74.060 101.320 + +*CAP +0 ropt_mt_inst_811:X 1e-06 +1 chany_top_out[13] 0.0003066489 +2 chany_top_out[13]:2 0.0003066489 +3 chany_top_out[13]:3 0.0001291196 +4 chany_top_out[13]:4 0.0001560347 +5 chany_top_out[13]:5 5.454394e-05 +6 chany_top_out[13] ropt_net_207:8 3.757706e-05 +7 chany_top_out[13]:3 ropt_net_207:10 6.166365e-06 +8 chany_top_out[13]:2 ropt_net_207:9 3.757706e-05 +9 chany_top_out[13]:4 ropt_net_207:11 6.166365e-06 + +*RES +0 ropt_mt_inst_811:X chany_top_out[13]:5 0.152 +1 chany_top_out[13]:5 chany_top_out[13]:4 0.0003035715 +2 chany_top_out[13]:3 chany_top_out[13]:2 0.0045 +3 chany_top_out[13]:2 chany_top_out[13] 0.005183036 +4 chany_top_out[13]:4 chany_top_out[13]:3 0.001602679 + +*END + +*D_NET chany_top_out[4] 0.0008374673 //LENGTH 7.155 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 76.360 104.040 +*P chany_top_out[4] O *L 0.7423 *C 73.140 107.510 +*N chany_top_out[4]:2 *C 73.140 104.085 +*N chany_top_out[4]:3 *C 73.185 104.040 +*N chany_top_out[4]:4 *C 76.323 104.040 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 chany_top_out[4] 0.0001992153 +2 chany_top_out[4]:2 0.0001992153 +3 chany_top_out[4]:3 0.0002190183 +4 chany_top_out[4]:4 0.0002190183 + +*RES +0 ropt_mt_inst_815:X chany_top_out[4]:4 0.152 +1 chany_top_out[4]:4 chany_top_out[4]:3 0.002801339 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0045 +3 chany_top_out[4]:2 chany_top_out[4] 0.003058036 + +*END + +*D_NET chany_bottom_out[4] 0.001258296 //LENGTH 10.505 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_817:X O *L 0 *C 46.190 8.840 +*P chany_bottom_out[4] O *L 0.7423 *C 43.700 1.290 +*N chany_bottom_out[4]:2 *C 43.700 8.795 +*N chany_bottom_out[4]:3 *C 43.745 8.840 +*N chany_bottom_out[4]:4 *C 46.153 8.840 + +*CAP +0 ropt_mt_inst_817:X 1e-06 +1 chany_bottom_out[4] 0.0004445532 +2 chany_bottom_out[4]:2 0.0004445532 +3 chany_bottom_out[4]:3 0.000184095 +4 chany_bottom_out[4]:4 0.000184095 + +*RES +0 ropt_mt_inst_817:X chany_bottom_out[4]:4 0.152 +1 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.002149554 +2 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +3 chany_bottom_out[4]:2 chany_bottom_out[4] 0.006700893 + +*END + +*D_NET chany_bottom_out[19] 0.0009322037 //LENGTH 7.330 LUMPCC 0.0001860219 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 49.415 6.120 +*P chany_bottom_out[19] O *L 0.7423 *C 47.380 1.290 +*N chany_bottom_out[19]:2 *C 47.380 6.075 +*N chany_bottom_out[19]:3 *C 47.425 6.120 +*N chany_bottom_out[19]:4 *C 49.378 6.120 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 chany_bottom_out[19] 0.0002319433 +2 chany_bottom_out[19]:2 0.0002319433 +3 chany_bottom_out[19]:3 0.0001406476 +4 chany_bottom_out[19]:4 0.0001406476 +5 chany_bottom_out[19] ropt_net_216:5 8.007647e-05 +6 chany_bottom_out[19]:4 ropt_net_216:3 1.293449e-05 +7 chany_bottom_out[19]:3 ropt_net_216:2 1.293449e-05 +8 chany_bottom_out[19]:2 ropt_net_216:4 8.007647e-05 + +*RES +0 ropt_mt_inst_819:X chany_bottom_out[19]:4 0.152 +1 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.001743304 +2 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.0045 +3 chany_bottom_out[19]:2 chany_bottom_out[19] 0.004272321 + +*END + +*D_NET chany_top_out[16] 0.001426338 //LENGTH 10.440 LUMPCC 0.0001035507 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 44.415 102.340 +*P chany_top_out[16] O *L 0.7423 *C 41.860 107.510 +*N chany_top_out[16]:2 *C 40.940 107.780 +*N chany_top_out[16]:3 *C 40.940 102.385 +*N chany_top_out[16]:4 *C 40.985 102.340 +*N chany_top_out[16]:5 *C 44.378 102.340 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 chany_top_out[16] 4.278668e-05 +2 chany_top_out[16]:2 0.0003670946 +3 chany_top_out[16]:3 0.0003243079 +4 chany_top_out[16]:4 0.0002937992 +5 chany_top_out[16]:5 0.0002937992 +6 chany_top_out[16]:3 ropt_net_220:3 5.177534e-05 +7 chany_top_out[16]:2 ropt_net_220:4 5.177534e-05 + +*RES +0 ropt_mt_inst_823:X chany_top_out[16]:5 0.152 +1 chany_top_out[16]:4 chany_top_out[16]:3 0.0045 +2 chany_top_out[16]:3 chany_top_out[16]:2 0.004816965 +3 chany_top_out[16]:5 chany_top_out[16]:4 0.003029018 +4 chany_top_out[16]:2 chany_top_out[16] 0.0008214285 + +*END + +*D_NET ropt_net_180 0.001381201 //LENGTH 10.305 LUMPCC 0.000507745 DR + +*CONN +*I BUFT_P_109:X O *L 0 *C 17.020 99.960 +*I ropt_mt_inst_784:A I *L 0.001766 *C 9.660 102.000 +*N ropt_net_180:2 *C 9.697 102.000 +*N ropt_net_180:3 *C 12.880 102.000 +*N ropt_net_180:4 *C 12.880 101.660 +*N ropt_net_180:5 *C 16.975 101.660 +*N ropt_net_180:6 *C 17.020 101.615 +*N ropt_net_180:7 *C 17.020 100.005 +*N ropt_net_180:8 *C 17.020 99.960 + +*CAP +0 BUFT_P_109:X 1e-06 +1 ropt_mt_inst_784:A 1e-06 +2 ropt_net_180:2 0.0001427766 +3 ropt_net_180:3 0.0001652438 +4 ropt_net_180:4 0.0001754803 +5 ropt_net_180:5 0.0001530131 +6 ropt_net_180:6 0.0001019429 +7 ropt_net_180:7 0.0001019429 +8 ropt_net_180:8 3.105587e-05 +9 ropt_net_180:2 chany_bottom_in[14]:10 5.562467e-05 +10 ropt_net_180:5 chany_bottom_in[14]:9 0.0001529687 +11 ropt_net_180:3 chany_bottom_in[14]:9 5.562467e-05 +12 ropt_net_180:4 chany_bottom_in[14]:10 0.0001529687 +13 ropt_net_180:5 ropt_net_205:3 4.527909e-05 +14 ropt_net_180:4 ropt_net_205:2 4.527909e-05 + +*RES +0 BUFT_P_109:X ropt_net_180:8 0.152 +1 ropt_net_180:2 ropt_mt_inst_784:A 0.152 +2 ropt_net_180:5 ropt_net_180:4 0.00365625 +3 ropt_net_180:6 ropt_net_180:5 0.0045 +4 ropt_net_180:8 ropt_net_180:7 0.0045 +5 ropt_net_180:7 ropt_net_180:6 0.0014375 +6 ropt_net_180:3 ropt_net_180:2 0.002841518 +7 ropt_net_180:4 ropt_net_180:3 0.0003035715 + +*END + +*D_NET ropt_net_208 0.001046513 //LENGTH 7.660 LUMPCC 0 DR + +*CONN +*I BUFT_P_120:X O *L 0 *C 74.715 99.620 +*I ropt_mt_inst_811:A I *L 0.001767 *C 73.140 102.000 +*N ropt_net_208:2 *C 73.140 102.000 +*N ropt_net_208:3 *C 73.140 102.045 +*N ropt_net_208:4 *C 73.140 102.635 +*N ropt_net_208:5 *C 73.140 102.680 +*N ropt_net_208:6 *C 74.935 102.680 +*N ropt_net_208:7 *C 74.980 102.635 +*N ropt_net_208:8 *C 74.980 99.665 +*N ropt_net_208:9 *C 74.980 99.620 +*N ropt_net_208:10 *C 74.715 99.620 + +*CAP +0 BUFT_P_120:X 1e-06 +1 ropt_mt_inst_811:A 1e-06 +2 ropt_net_208:2 3.416552e-05 +3 ropt_net_208:3 4.945275e-05 +4 ropt_net_208:4 4.945275e-05 +5 ropt_net_208:5 0.0002389865 +6 ropt_net_208:6 0.000204821 +7 ropt_net_208:7 0.0001722893 +8 ropt_net_208:8 0.0001722893 +9 ropt_net_208:9 6.354527e-05 +10 ropt_net_208:10 5.951081e-05 + +*RES +0 BUFT_P_120:X ropt_net_208:10 0.152 +1 ropt_net_208:10 ropt_net_208:9 0.0001440218 +2 ropt_net_208:9 ropt_net_208:8 0.0045 +3 ropt_net_208:8 ropt_net_208:7 0.002651786 +4 ropt_net_208:6 ropt_net_208:5 0.001602679 +5 ropt_net_208:7 ropt_net_208:6 0.0045 +6 ropt_net_208:5 ropt_net_208:4 0.0045 +7 ropt_net_208:4 ropt_net_208:3 0.0005267857 +8 ropt_net_208:2 ropt_mt_inst_811:A 0.152 +9 ropt_net_208:3 ropt_net_208:2 0.0045 + +*END + +*D_NET chany_bottom_in[9] 0.01138852 //LENGTH 121.670 LUMPCC 0.0007382779 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 9.200 1.210 +*I ropt_mt_inst_765:A I *L 0.001767 *C 20.240 104.720 +*N chany_bottom_in[9]:2 *C 20.277 104.720 +*N chany_bottom_in[9]:3 *C 21.115 104.720 +*N chany_bottom_in[9]:4 *C 21.160 104.675 +*N chany_bottom_in[9]:5 *C 21.160 93.205 +*N chany_bottom_in[9]:6 *C 21.115 93.160 +*N chany_bottom_in[9]:7 *C 15.180 93.160 +*N chany_bottom_in[9]:8 *C 15.260 94.520 +*N chany_bottom_in[9]:9 *C 15.190 94.475 +*N chany_bottom_in[9]:10 *C 15.180 93.885 +*N chany_bottom_in[9]:11 *C 15.180 93.840 +*N chany_bottom_in[9]:12 *C 13.385 93.840 +*N chany_bottom_in[9]:13 *C 13.340 93.795 +*N chany_bottom_in[9]:14 *C 13.340 88.458 +*N chany_bottom_in[9]:15 *C 13.333 88.400 +*N chany_bottom_in[9]:16 *C 9.220 88.400 +*N chany_bottom_in[9]:17 *C 9.200 88.392 +*N chany_bottom_in[9]:18 *C 9.200 51.210 + +*CAP +0 chany_bottom_in[9] 0.002020586 +1 ropt_mt_inst_765:A 1e-06 +2 chany_bottom_in[9]:2 6.746987e-05 +3 chany_bottom_in[9]:3 6.746987e-05 +4 chany_bottom_in[9]:4 0.0005434683 +5 chany_bottom_in[9]:5 0.0005434683 +6 chany_bottom_in[9]:6 0.0003677066 +7 chany_bottom_in[9]:7 0.0004075837 +8 chany_bottom_in[9]:8 8.092928e-05 +9 chany_bottom_in[9]:9 5.022384e-05 +10 chany_bottom_in[9]:10 5.022384e-05 +11 chany_bottom_in[9]:11 0.0001978215 +12 chany_bottom_in[9]:12 0.0001123419 +13 chany_bottom_in[9]:13 0.0002685693 +14 chany_bottom_in[9]:14 0.0002685693 +15 chany_bottom_in[9]:15 0.0002656878 +16 chany_bottom_in[9]:16 0.0002656878 +17 chany_bottom_in[9]:17 0.001525426 +18 chany_bottom_in[9]:18 0.003546012 +19 chany_bottom_in[9] prog_clk[0]:57 0.0001860019 +20 chany_bottom_in[9]:17 prog_clk[0]:55 8.432921e-05 +21 chany_bottom_in[9]:17 prog_clk[0]:56 1.293434e-05 +22 chany_bottom_in[9]:18 prog_clk[0]:57 1.293434e-05 +23 chany_bottom_in[9]:18 prog_clk[0]:56 0.0002703311 +24 chany_bottom_in[9]:2 ropt_net_218:6 1.847492e-05 +25 chany_bottom_in[9]:3 ropt_net_218:7 1.847492e-05 +26 chany_bottom_in[9]:4 ropt_net_218:5 6.739856e-05 +27 chany_bottom_in[9]:5 ropt_net_218:4 6.739856e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:18 0.007833333 +1 chany_bottom_in[9]:2 ropt_mt_inst_765:A 0.152 +2 chany_bottom_in[9]:3 chany_bottom_in[9]:2 0.000747768 +3 chany_bottom_in[9]:4 chany_bottom_in[9]:3 0.0045 +4 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.0045 +5 chany_bottom_in[9]:5 chany_bottom_in[9]:4 0.01024107 +6 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.001602679 +7 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.0045 +8 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.004765625 +9 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.00341 +10 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.0006442917 +11 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.00341 +12 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.0045 +13 chany_bottom_in[9]:11 chany_bottom_in[9]:7 0.0006071429 +14 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.0005267857 +15 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.0045 +16 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.005299107 +17 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.005825258 + +*END + +*D_NET chany_bottom_in[10] 0.01962102 //LENGTH 161.805 LUMPCC 0.002251661 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 46.460 1.290 +*I mux_left_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 60.550 75.140 +*I ropt_mt_inst_776:A I *L 0.001766 *C 58.880 102.000 +*N chany_bottom_in[10]:3 *C 51.730 75.480 +*N chany_bottom_in[10]:4 *C 41.000 99.280 +*N chany_bottom_in[10]:5 *C 58.880 102.000 +*N chany_bottom_in[10]:6 *C 58.880 102.340 +*N chany_bottom_in[10]:7 *C 51.565 102.340 +*N chany_bottom_in[10]:8 *C 51.520 102.385 +*N chany_bottom_in[10]:9 *C 51.520 107.055 +*N chany_bottom_in[10]:10 *C 51.475 107.100 +*N chany_bottom_in[10]:11 *C 44.620 107.100 +*N chany_bottom_in[10]:12 *C 44.620 107.440 +*N chany_bottom_in[10]:13 *C 41.400 107.440 +*N chany_bottom_in[10]:14 *C 41.400 107.100 +*N chany_bottom_in[10]:15 *C 41.400 107.055 +*N chany_bottom_in[10]:16 *C 41.400 99.338 +*N chany_bottom_in[10]:17 *C 41.400 99.280 +*N chany_bottom_in[10]:18 *C 41.400 99.273 +*N chany_bottom_in[10]:19 *C 41.400 75.487 +*N chany_bottom_in[10]:20 *C 41.420 75.480 +*N chany_bottom_in[10]:21 *C 46.913 75.480 +*N chany_bottom_in[10]:22 *C 46.920 75.480 +*N chany_bottom_in[10]:23 *C 46.965 75.480 +*N chany_bottom_in[10]:24 *C 52.395 75.480 +*N chany_bottom_in[10]:25 *C 52.440 75.480 +*N chany_bottom_in[10]:26 *C 52.438 75.480 +*N chany_bottom_in[10]:27 *C 52.440 75.472 +*N chany_bottom_in[10]:28 *C 60.550 75.140 +*N chany_bottom_in[10]:29 *C 60.720 75.140 +*N chany_bottom_in[10]:30 *C 60.720 75.095 +*N chany_bottom_in[10]:31 *C 60.720 74.178 +*N chany_bottom_in[10]:32 *C 60.713 74.120 +*N chany_bottom_in[10]:33 *C 52.460 74.120 +*N chany_bottom_in[10]:34 *C 52.440 74.120 +*N chany_bottom_in[10]:35 *C 52.440 52.555 +*N chany_bottom_in[10]:36 *C 52.440 2.728 +*N chany_bottom_in[10]:37 *C 52.420 2.720 +*N chany_bottom_in[10]:38 *C 46.468 2.720 +*N chany_bottom_in[10]:39 *C 46.460 2.663 + +*CAP +0 chany_bottom_in[10] 9.818281e-05 +1 mux_left_ipin_0\/mux_l2_in_1_:A0 1e-06 +2 ropt_mt_inst_776:A 1e-06 +3 chany_bottom_in[10]:3 9.063746e-05 +4 chany_bottom_in[10]:4 6.792897e-05 +5 chany_bottom_in[10]:5 5.282785e-05 +6 chany_bottom_in[10]:6 0.0004625912 +7 chany_bottom_in[10]:7 0.0004365278 +8 chany_bottom_in[10]:8 0.0003644577 +9 chany_bottom_in[10]:9 0.0003644577 +10 chany_bottom_in[10]:10 0.000465332 +11 chany_bottom_in[10]:11 0.0004933983 +12 chany_bottom_in[10]:12 0.0002408112 +13 chany_bottom_in[10]:13 0.0002433058 +14 chany_bottom_in[10]:14 6.647993e-05 +15 chany_bottom_in[10]:15 0.0005592499 +16 chany_bottom_in[10]:16 0.0005592499 +17 chany_bottom_in[10]:17 6.792897e-05 +18 chany_bottom_in[10]:18 0.00204117 +19 chany_bottom_in[10]:19 0.00204117 +20 chany_bottom_in[10]:20 0.0003883667 +21 chany_bottom_in[10]:21 0.0003883667 +22 chany_bottom_in[10]:22 3.611861e-05 +23 chany_bottom_in[10]:23 0.0003785036 +24 chany_bottom_in[10]:24 0.0003785036 +25 chany_bottom_in[10]:25 3.496294e-05 +26 chany_bottom_in[10]:26 9.063746e-05 +27 chany_bottom_in[10]:27 7.949176e-05 +28 chany_bottom_in[10]:28 5.019588e-05 +29 chany_bottom_in[10]:29 5.423934e-05 +30 chany_bottom_in[10]:30 7.078533e-05 +31 chany_bottom_in[10]:31 7.078533e-05 +32 chany_bottom_in[10]:32 0.00051313 +33 chany_bottom_in[10]:33 0.00051313 +34 chany_bottom_in[10]:34 0.0007404226 +35 chany_bottom_in[10]:35 0.0022676 +36 chany_bottom_in[10]:36 0.001606669 +37 chany_bottom_in[10]:37 0.0004457809 +38 chany_bottom_in[10]:38 0.0004457809 +39 chany_bottom_in[10]:39 9.818281e-05 +40 chany_bottom_in[10]:27 chany_top_in[13] 4.439447e-06 +41 chany_bottom_in[10]:34 chany_top_in[13] 0.0001986212 +42 chany_bottom_in[10]:34 chany_top_in[13]:16 0.000119464 +43 chany_bottom_in[10]:36 chany_top_in[13]:15 0.0006810453 +44 chany_bottom_in[10]:35 chany_top_in[13]:15 0.0001150246 +45 chany_bottom_in[10]:35 chany_top_in[13]:16 0.0008796664 +46 chany_bottom_in[10]:7 ropt_net_186:6 0.0001266999 +47 chany_bottom_in[10]:6 ropt_net_186:7 0.0001266999 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:39 0.001225446 +1 chany_bottom_in[10]:26 chany_bottom_in[10]:25 0.00341 +2 chany_bottom_in[10]:26 chany_bottom_in[10]:3 0.0001039141 +3 chany_bottom_in[10]:27 chany_bottom_in[10]:26 0.00341 +4 chany_bottom_in[10]:25 chany_bottom_in[10]:24 0.0045 +5 chany_bottom_in[10]:24 chany_bottom_in[10]:23 0.004848214 +6 chany_bottom_in[10]:23 chany_bottom_in[10]:22 0.0045 +7 chany_bottom_in[10]:22 chany_bottom_in[10]:21 0.00341 +8 chany_bottom_in[10]:21 chany_bottom_in[10]:20 0.0008604916 +9 chany_bottom_in[10]:20 chany_bottom_in[10]:19 0.00341 +10 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.003726316 +11 chany_bottom_in[10]:17 chany_bottom_in[10]:16 0.00341 +12 chany_bottom_in[10]:17 chany_bottom_in[10]:4 5.69697e-05 +13 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.00341 +14 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.006890626 +15 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.0003035715 +16 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.0045 +17 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.0045 +18 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.004169643 +19 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.006531251 +20 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.0045 +21 chany_bottom_in[10]:5 ropt_mt_inst_776:A 0.152 +22 chany_bottom_in[10]:33 chany_bottom_in[10]:32 0.001292892 +23 chany_bottom_in[10]:34 chany_bottom_in[10]:33 0.00341 +24 chany_bottom_in[10]:34 chany_bottom_in[10]:27 0.0002118916 +25 chany_bottom_in[10]:31 chany_bottom_in[10]:30 0.0008191965 +26 chany_bottom_in[10]:32 chany_bottom_in[10]:31 0.00341 +27 chany_bottom_in[10]:29 chany_bottom_in[10]:28 9.239131e-05 +28 chany_bottom_in[10]:30 chany_bottom_in[10]:29 0.0045 +29 chany_bottom_in[10]:28 mux_left_ipin_0\/mux_l2_in_1_:A0 0.152 +30 chany_bottom_in[10]:37 chany_bottom_in[10]:36 0.00341 +31 chany_bottom_in[10]:36 chany_bottom_in[10]:35 0.007806308 +32 chany_bottom_in[10]:39 chany_bottom_in[10]:38 0.00341 +33 chany_bottom_in[10]:38 chany_bottom_in[10]:37 0.0009325583 +34 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.002875 +35 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.0003035715 +36 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.006120536 +37 chany_bottom_in[10]:6 chany_bottom_in[10]:5 0.0003035715 +38 chany_bottom_in[10]:35 chany_bottom_in[10]:34 0.003378517 + +*END + +*D_NET chany_bottom_in[11] 0.01478444 //LENGTH 126.610 LUMPCC 0.003423963 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 51.060 1.290 +*I FTB_12__11:A I *L 0.001776 *C 28.980 96.560 +*I mux_right_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 21.910 70.040 +*N chany_bottom_in[11]:3 *C 21.948 70.040 +*N chany_bottom_in[11]:4 *C 29.018 96.560 +*N chany_bottom_in[11]:5 *C 29.395 96.560 +*N chany_bottom_in[11]:6 *C 29.440 96.515 +*N chany_bottom_in[11]:7 *C 29.440 70.085 +*N chany_bottom_in[11]:8 *C 29.440 70.040 +*N chany_bottom_in[11]:9 *C 36.755 70.040 +*N chany_bottom_in[11]:10 *C 36.800 69.995 +*N chany_bottom_in[11]:11 *C 36.800 54.600 +*N chany_bottom_in[11]:12 *C 36.800 4.805 +*N chany_bottom_in[11]:13 *C 36.845 4.760 +*N chany_bottom_in[11]:14 *C 51.015 4.760 +*N chany_bottom_in[11]:15 *C 51.060 4.715 + +*CAP +0 chany_bottom_in[11] 0.0002050014 +1 FTB_12__11:A 1e-06 +2 mux_right_ipin_0\/mux_l2_in_1_:A0 1e-06 +3 chany_bottom_in[11]:3 0.0003822174 +4 chany_bottom_in[11]:4 3.109021e-05 +5 chany_bottom_in[11]:5 3.109021e-05 +6 chany_bottom_in[11]:6 0.00130473 +7 chany_bottom_in[11]:7 0.00130473 +8 chany_bottom_in[11]:8 0.0008652917 +9 chany_bottom_in[11]:9 0.0004540175 +10 chany_bottom_in[11]:10 0.0005671419 +11 chany_bottom_in[11]:11 0.002366269 +12 chany_bottom_in[11]:12 0.001799127 +13 chany_bottom_in[11]:13 0.0009213826 +14 chany_bottom_in[11]:14 0.0009213826 +15 chany_bottom_in[11]:15 0.0002050014 +16 chany_bottom_in[11]:10 chany_bottom_in[3]:11 0.0001292781 +17 chany_bottom_in[11]:10 chany_bottom_in[3]:16 9.71392e-05 +18 chany_bottom_in[11]:12 chany_bottom_in[3]:17 0.0004640842 +19 chany_bottom_in[11]:11 chany_bottom_in[3]:12 0.0001292781 +20 chany_bottom_in[11]:11 chany_bottom_in[3]:16 0.0004640842 +21 chany_bottom_in[11]:11 chany_bottom_in[3]:17 9.71392e-05 +22 chany_bottom_in[11]:12 chany_top_in[14]:7 0.0004118219 +23 chany_bottom_in[11]:12 chany_top_in[14]:11 4.384046e-06 +24 chany_bottom_in[11]:11 chany_top_in[14]:8 0.0004118219 +25 chany_bottom_in[11]:11 chany_top_in[14]:12 4.384046e-06 +26 chany_bottom_in[11]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001100394 +27 chany_bottom_in[11]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.979199e-05 +28 chany_bottom_in[11]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.979199e-05 +29 chany_bottom_in[11]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001100394 +30 chany_bottom_in[11] ropt_net_190:6 1.43589e-06 +31 chany_bottom_in[11]:13 ropt_net_190:2 5.608892e-06 +32 chany_bottom_in[11]:13 ropt_net_190:4 0.0001703668 +33 chany_bottom_in[11]:14 ropt_net_190:5 0.0001703668 +34 chany_bottom_in[11]:14 ropt_net_190:3 5.608892e-06 +35 chany_bottom_in[11]:15 ropt_net_190:7 1.43589e-06 +36 chany_bottom_in[11]:7 BUF_net_47:7 0.000265544 +37 chany_bottom_in[11]:5 BUF_net_47:5 1.248703e-05 +38 chany_bottom_in[11]:6 BUF_net_47:6 0.000265544 +39 chany_bottom_in[11]:4 BUF_net_47:4 1.248703e-05 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:15 0.003058036 +1 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.0045 +2 chany_bottom_in[11]:8 chany_bottom_in[11]:3 0.006689732 +3 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.02359822 +4 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.0003370536 +5 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.0045 +6 chany_bottom_in[11]:4 FTB_12__11:A 0.152 +7 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.006531251 +8 chany_bottom_in[11]:10 chany_bottom_in[11]:9 0.0045 +9 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.0045 +10 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.04445983 +11 chany_bottom_in[11]:14 chany_bottom_in[11]:13 0.01265179 +12 chany_bottom_in[11]:15 chany_bottom_in[11]:14 0.0045 +13 chany_bottom_in[11]:3 mux_right_ipin_0\/mux_l2_in_1_:A0 0.152 +14 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.01374554 + +*END + +*D_NET chany_bottom_in[12] 0.01761361 //LENGTH 163.630 LUMPCC 0.002445463 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 7.360 1.290 +*I ropt_mt_inst_757:A I *L 0.001767 *C 61.640 104.720 +*N chany_bottom_in[12]:2 *C 61.603 104.720 +*N chany_bottom_in[12]:3 *C 58.925 104.720 +*N chany_bottom_in[12]:4 *C 58.880 104.675 +*N chany_bottom_in[12]:5 *C 58.880 101.365 +*N chany_bottom_in[12]:6 *C 58.835 101.320 +*N chany_bottom_in[12]:7 *C 45.540 101.320 +*N chany_bottom_in[12]:8 *C 45.540 102.680 +*N chany_bottom_in[12]:9 *C 31.325 102.680 +*N chany_bottom_in[12]:10 *C 31.280 102.635 +*N chany_bottom_in[12]:11 *C 31.280 94.520 +*N chany_bottom_in[12]:12 *C 30.820 94.520 +*N chany_bottom_in[12]:13 *C 30.820 53.425 +*N chany_bottom_in[12]:14 *C 30.820 53.380 +*N chany_bottom_in[12]:15 *C 30.865 53.040 +*N chany_bottom_in[12]:16 *C 28.565 53.040 +*N chany_bottom_in[12]:17 *C 28.520 52.995 +*N chany_bottom_in[12]:18 *C 28.520 50.025 +*N chany_bottom_in[12]:19 *C 28.475 49.980 +*N chany_bottom_in[12]:20 *C 7.405 49.980 +*N chany_bottom_in[12]:21 *C 7.360 49.935 + +*CAP +0 chany_bottom_in[12] 0.001672975 +1 ropt_mt_inst_757:A 1e-06 +2 chany_bottom_in[12]:2 0.0001550468 +3 chany_bottom_in[12]:3 0.0001550468 +4 chany_bottom_in[12]:4 0.0001169769 +5 chany_bottom_in[12]:5 0.0001169769 +6 chany_bottom_in[12]:6 0.0008405867 +7 chany_bottom_in[12]:7 0.0009227074 +8 chany_bottom_in[12]:8 0.001029132 +9 chany_bottom_in[12]:9 0.0009470118 +10 chany_bottom_in[12]:10 0.000327408 +11 chany_bottom_in[12]:11 0.0003573839 +12 chany_bottom_in[12]:12 0.002047249 +13 chany_bottom_in[12]:13 0.002017274 +14 chany_bottom_in[12]:14 5.420229e-05 +15 chany_bottom_in[12]:15 0.0001656917 +16 chany_bottom_in[12]:16 0.0001390483 +17 chany_bottom_in[12]:17 0.0001475546 +18 chany_bottom_in[12]:18 0.0001475546 +19 chany_bottom_in[12]:19 0.001067174 +20 chany_bottom_in[12]:20 0.001067174 +21 chany_bottom_in[12]:21 0.001672975 +22 chany_bottom_in[12] chany_bottom_in[14] 5.175357e-05 +23 chany_bottom_in[12] chany_bottom_in[14]:13 0.0006021482 +24 chany_bottom_in[12]:21 chany_bottom_in[14]:16 5.175357e-05 +25 chany_bottom_in[12]:21 chany_bottom_in[14]:12 0.0006021482 +26 chany_bottom_in[12]:6 ropt_net_210:6 5.257777e-06 +27 chany_bottom_in[12]:5 ropt_net_210:5 8.232506e-05 +28 chany_bottom_in[12]:4 ropt_net_210:4 8.232506e-05 +29 chany_bottom_in[12]:7 ropt_net_210:7 5.257777e-06 +30 chany_bottom_in[12]:6 ropt_net_189:7 0.0001293108 +31 chany_bottom_in[12]:7 ropt_net_189:6 0.0001293108 +32 chany_bottom_in[12]:9 ropt_net_181:4 1.173052e-05 +33 chany_bottom_in[12]:10 ropt_net_181:5 0.0001650745 +34 chany_bottom_in[12]:8 ropt_net_181:3 1.173052e-05 +35 chany_bottom_in[12]:11 ropt_net_181:6 0.0001650745 +36 chany_bottom_in[12]:13 BUF_net_47:7 0.000111908 +37 chany_bottom_in[12]:10 BUF_net_47:6 2.326398e-06 +38 chany_bottom_in[12]:12 BUF_net_47:6 0.000111908 +39 chany_bottom_in[12]:11 BUF_net_47:7 2.326398e-06 +40 chany_bottom_in[12]:9 ropt_net_202:2 5.180682e-05 +41 chany_bottom_in[12]:10 ropt_net_202:4 9.089818e-06 +42 chany_bottom_in[12]:8 ropt_net_202:3 5.180682e-05 +43 chany_bottom_in[12]:11 ropt_net_202:5 9.089818e-06 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:21 0.04343304 +1 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.0045 +2 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.03669197 +3 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.01269197 +4 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.0045 +5 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.0045 +6 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.002955357 +7 chany_bottom_in[12]:3 chany_bottom_in[12]:2 0.002390625 +8 chany_bottom_in[12]:4 chany_bottom_in[12]:3 0.0045 +9 chany_bottom_in[12]:2 ropt_mt_inst_757:A 0.152 +10 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.002053572 +11 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.0045 +12 chany_bottom_in[12]:19 chany_bottom_in[12]:18 0.0045 +13 chany_bottom_in[12]:18 chany_bottom_in[12]:17 0.002651786 +14 chany_bottom_in[12]:20 chany_bottom_in[12]:19 0.0188125 +15 chany_bottom_in[12]:21 chany_bottom_in[12]:20 0.0045 +16 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.0001847826 +17 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.001214286 +18 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.01187054 +19 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0004107143 +20 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.007245537 + +*END + +*D_NET chany_bottom_in[13] 0.01353735 //LENGTH 133.820 LUMPCC 0.001987363 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 23.920 1.210 +*I BUFT_RR_51:A I *L 0.001776 *C 63.940 93.840 +*N chany_bottom_in[13]:2 *C 63.903 93.840 +*N chany_bottom_in[13]:3 *C 62.145 93.840 +*N chany_bottom_in[13]:4 *C 62.100 93.795 +*N chany_bottom_in[13]:5 *C 62.100 75.655 +*N chany_bottom_in[13]:6 *C 62.100 25.898 +*N chany_bottom_in[13]:7 *C 62.093 25.840 +*N chany_bottom_in[13]:8 *C 23.940 25.840 +*N chany_bottom_in[13]:9 *C 23.920 25.832 + +*CAP +0 chany_bottom_in[13] 0.0007339751 +1 BUFT_RR_51:A 1e-06 +2 chany_bottom_in[13]:2 0.0001470852 +3 chany_bottom_in[13]:3 0.0001470852 +4 chany_bottom_in[13]:4 0.0008431357 +5 chany_bottom_in[13]:5 0.002680725 +6 chany_bottom_in[13]:6 0.001837589 +7 chany_bottom_in[13]:7 0.002212706 +8 chany_bottom_in[13]:8 0.002212706 +9 chany_bottom_in[13]:9 0.0007339751 +10 chany_bottom_in[13]:4 chany_bottom_in[7]:6 5.497188e-05 +11 chany_bottom_in[13]:6 chany_bottom_in[7]:7 0.0001250161 +12 chany_bottom_in[13]:6 chany_bottom_in[7]:8 0.0002284707 +13 chany_bottom_in[13]:5 chany_bottom_in[7]:6 0.0001250161 +14 chany_bottom_in[13]:5 chany_bottom_in[7]:7 0.0002834426 +15 chany_bottom_in[13] chany_bottom_in[8] 0.0005852226 +16 chany_bottom_in[13]:9 chany_bottom_in[8]:9 0.0005852226 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:9 0.003857525 +1 chany_bottom_in[13]:2 BUFT_RR_51:A 0.152 +2 chany_bottom_in[13]:3 chany_bottom_in[13]:2 0.001569197 +3 chany_bottom_in[13]:4 chany_bottom_in[13]:3 0.0045 +4 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.04442634 +5 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.00341 +6 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.005977225 +7 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.00341 +8 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.01619643 + +*END + +*D_NET chany_bottom_in[14] 0.01649621 //LENGTH 150.100 LUMPCC 0.002384536 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 7.360 1.285 +*I ropt_mt_inst_752:A I *L 0.001766 *C 45.080 102.000 +*N chany_bottom_in[14]:2 *C 45.080 102.000 +*N chany_bottom_in[14]:3 *C 45.080 102.045 +*N chany_bottom_in[14]:4 *C 45.080 106.715 +*N chany_bottom_in[14]:5 *C 45.035 106.760 +*N chany_bottom_in[14]:6 *C 26.725 106.760 +*N chany_bottom_in[14]:7 *C 26.680 106.715 +*N chany_bottom_in[14]:8 *C 26.680 101.365 +*N chany_bottom_in[14]:9 *C 26.635 101.320 +*N chany_bottom_in[14]:10 *C 8.325 101.320 +*N chany_bottom_in[14]:11 *C 8.280 101.275 +*N chany_bottom_in[14]:12 *C 8.280 58.655 +*N chany_bottom_in[14]:13 *C 8.280 8.898 +*N chany_bottom_in[14]:14 *C 8.273 8.840 +*N chany_bottom_in[14]:15 *C 7.380 8.840 +*N chany_bottom_in[14]:16 *C 7.360 8.832 + +*CAP +0 chany_bottom_in[14] 0.0004056905 +1 ropt_mt_inst_752:A 1e-06 +2 chany_bottom_in[14]:2 3.927798e-05 +3 chany_bottom_in[14]:3 0.0003795838 +4 chany_bottom_in[14]:4 0.0003795838 +5 chany_bottom_in[14]:5 0.001301481 +6 chany_bottom_in[14]:6 0.001301481 +7 chany_bottom_in[14]:7 0.0002273293 +8 chany_bottom_in[14]:8 0.0002273293 +9 chany_bottom_in[14]:9 0.0009761857 +10 chany_bottom_in[14]:10 0.0009761857 +11 chany_bottom_in[14]:11 0.001915895 +12 chany_bottom_in[14]:12 0.003664581 +13 chany_bottom_in[14]:13 0.001748686 +14 chany_bottom_in[14]:14 8.084865e-05 +15 chany_bottom_in[14]:15 8.084865e-05 +16 chany_bottom_in[14]:16 0.0004056905 +17 chany_bottom_in[14] chany_bottom_in[12] 5.175357e-05 +18 chany_bottom_in[14]:13 chany_bottom_in[12] 0.0006021482 +19 chany_bottom_in[14]:16 chany_bottom_in[12]:21 5.175357e-05 +20 chany_bottom_in[14]:12 chany_bottom_in[12]:21 0.0006021482 +21 chany_bottom_in[14]:7 ropt_net_187:5 6.246322e-05 +22 chany_bottom_in[14]:8 ropt_net_187:4 6.246322e-05 +23 chany_bottom_in[14]:7 ropt_net_199:4 6.163606e-05 +24 chany_bottom_in[14]:8 ropt_net_199:5 6.163606e-05 +25 chany_bottom_in[14]:7 ropt_net_184:4 3.158269e-07 +26 chany_bottom_in[14]:9 ropt_net_184:5 0.0002053575 +27 chany_bottom_in[14]:8 ropt_net_184:3 3.158269e-07 +28 chany_bottom_in[14]:10 ropt_net_184:6 0.0002053575 +29 chany_bottom_in[14]:9 ropt_net_180:5 0.0001529687 +30 chany_bottom_in[14]:9 ropt_net_180:3 5.562467e-05 +31 chany_bottom_in[14]:10 ropt_net_180:2 5.562467e-05 +32 chany_bottom_in[14]:10 ropt_net_180:4 0.0001529687 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:16 0.001182442 +1 chany_bottom_in[14]:2 ropt_mt_inst_752:A 0.152 +2 chany_bottom_in[14]:3 chany_bottom_in[14]:2 0.0045 +3 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.0045 +4 chany_bottom_in[14]:4 chany_bottom_in[14]:3 0.004169643 +5 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.01634821 +6 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.0045 +7 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.0045 +8 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.004776786 +9 chany_bottom_in[14]:10 chany_bottom_in[14]:9 0.01634821 +10 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.0045 +11 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.04442634 +12 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.00341 +13 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.000139825 +14 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.00341 +15 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.03805357 + +*END + +*D_NET chany_bottom_in[15] 0.01155312 //LENGTH 105.820 LUMPCC 0.004611062 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 46.000 1.210 +*I BUFT_RR_53:A I *L 0.001776 *C 39.560 99.280 +*N chany_bottom_in[15]:2 *C 39.583 99.252 +*N chany_bottom_in[15]:3 *C 39.595 98.940 +*N chany_bottom_in[15]:4 *C 43.655 98.940 +*N chany_bottom_in[15]:5 *C 43.700 98.895 +*N chany_bottom_in[15]:6 *C 43.700 68.175 +*N chany_bottom_in[15]:7 *C 43.700 18.418 +*N chany_bottom_in[15]:8 *C 43.708 18.360 +*N chany_bottom_in[15]:9 *C 45.980 18.360 +*N chany_bottom_in[15]:10 *C 46.000 18.352 + +*CAP +0 chany_bottom_in[15] 0.0005737895 +1 BUFT_RR_53:A 1e-06 +2 chany_bottom_in[15]:2 2.623895e-05 +3 chany_bottom_in[15]:3 0.0001946536 +4 chany_bottom_in[15]:4 0.0001684147 +5 chany_bottom_in[15]:5 0.0008368737 +6 chany_bottom_in[15]:6 0.002517433 +7 chany_bottom_in[15]:7 0.00168056 +8 chany_bottom_in[15]:8 0.0001846536 +9 chany_bottom_in[15]:9 0.0001846536 +10 chany_bottom_in[15]:10 0.0005737895 +11 chany_bottom_in[15]:7 chany_bottom_in[5] 0.0004669708 +12 chany_bottom_in[15]:7 chany_bottom_in[5]:20 3.255575e-06 +13 chany_bottom_in[15]:7 chany_bottom_in[5]:22 0.0001243274 +14 chany_bottom_in[15]:6 chany_bottom_in[5]:19 3.255575e-06 +15 chany_bottom_in[15]:6 chany_bottom_in[5]:21 0.0001243274 +16 chany_bottom_in[15]:6 chany_bottom_in[5]:22 0.0004669708 +17 chany_bottom_in[15] chany_bottom_in[18] 0.0003915049 +18 chany_bottom_in[15]:10 chany_bottom_in[18]:16 0.0003915049 +19 chany_bottom_in[15]:5 chany_top_in[3] 0.0004193259 +20 chany_bottom_in[15]:7 chany_top_in[3]:6 1.890753e-06 +21 chany_bottom_in[15]:7 chany_top_in[3]:11 0.000108925 +22 chany_bottom_in[15]:6 chany_top_in[3] 0.000108925 +23 chany_bottom_in[15]:6 chany_top_in[3]:7 1.890753e-06 +24 chany_bottom_in[15]:6 chany_top_in[3]:11 0.0004193259 +25 chany_bottom_in[15]:5 chany_top_in[10] 0.0004188505 +26 chany_bottom_in[15]:7 chany_top_in[10]:16 0.0002165916 +27 chany_bottom_in[15]:6 chany_top_in[10] 0.0002165916 +28 chany_bottom_in[15]:6 chany_top_in[10]:16 0.0004188505 +29 chany_bottom_in[15]:2 ropt_net_171:4 6.873157e-06 +30 chany_bottom_in[15]:4 ropt_net_171:2 0.0001411595 +31 chany_bottom_in[15]:4 ropt_net_171:4 5.855726e-06 +32 chany_bottom_in[15]:3 ropt_net_171:5 5.855726e-06 +33 chany_bottom_in[15]:3 ropt_net_171:3 0.0001480327 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:10 0.002685658 +1 chany_bottom_in[15]:2 BUFT_RR_53:A 0.152 +2 chany_bottom_in[15]:4 chany_bottom_in[15]:3 0.003625 +3 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.0045 +4 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.04442634 +5 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.00341 +6 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.000356025 +7 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.00341 +8 chany_bottom_in[15]:3 chany_bottom_in[15]:2 0.0002111487 +9 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.02742857 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..68389be --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,23491 @@ +*SPEF "1481-1998" +*DESIGN "cby_1__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 0.690 89.760 +chany_bottom_in[0] I *C 48.300 0.680 +chany_bottom_in[1] I *C 32.660 0.680 +chany_bottom_in[2] I *C 49.220 0.680 +chany_bottom_in[3] I *C 42.780 0.680 +chany_bottom_in[4] I *C 70.380 0.680 +chany_bottom_in[5] I *C 55.200 0.680 +chany_bottom_in[6] I *C 41.860 0.680 +chany_bottom_in[7] I *C 21.620 0.680 +chany_bottom_in[8] I *C 40.020 0.680 +chany_bottom_in[9] I *C 29.900 0.680 +chany_bottom_in[10] I *C 68.080 0.680 +chany_bottom_in[11] I *C 65.320 0.680 +chany_bottom_in[12] I *C 51.060 0.680 +chany_bottom_in[13] I *C 35.880 0.680 +chany_bottom_in[14] I *C 69.000 0.680 +chany_bottom_in[15] I *C 22.540 0.680 +chany_bottom_in[16] I *C 58.420 0.680 +chany_bottom_in[17] I *C 33.580 0.680 +chany_bottom_in[18] I *C 67.160 0.680 +chany_bottom_in[19] I *C 50.140 0.680 +chany_top_in[0] I *C 54.740 108.120 +chany_top_in[1] I *C 31.280 108.120 +chany_top_in[2] I *C 23.920 108.120 +chany_top_in[3] I *C 40.480 108.120 +chany_top_in[4] I *C 68.080 108.120 +chany_top_in[5] I *C 43.240 108.120 +chany_top_in[6] I *C 46.460 108.120 +chany_top_in[7] I *C 32.200 108.120 +chany_top_in[8] I *C 34.960 108.120 +chany_top_in[9] I *C 25.760 108.120 +chany_top_in[10] I *C 64.860 108.120 +chany_top_in[11] I *C 45.540 108.120 +chany_top_in[12] I *C 51.980 108.120 +chany_top_in[13] I *C 33.120 108.120 +chany_top_in[14] I *C 69.000 108.120 +chany_top_in[15] I *C 26.680 108.120 +chany_top_in[16] I *C 35.880 108.120 +chany_top_in[17] I *C 30.360 108.120 +chany_top_in[18] I *C 44.620 108.120 +chany_top_in[19] I *C 42.320 108.120 +ccff_head[0] I *C 0.690 13.600 +chany_bottom_out[0] O *C 51.980 0.680 +chany_bottom_out[1] O *C 28.980 0.680 +chany_bottom_out[2] O *C 53.820 0.680 +chany_bottom_out[3] O *C 45.540 0.680 +chany_bottom_out[4] O *C 23.460 0.680 +chany_bottom_out[5] O *C 31.740 0.680 +chany_bottom_out[6] O *C 46.460 0.680 +chany_bottom_out[7] O *C 38.180 0.680 +chany_bottom_out[8] O *C 43.700 0.680 +chany_bottom_out[9] O *C 39.100 0.680 +chany_bottom_out[10] O *C 44.620 0.680 +chany_bottom_out[11] O *C 47.380 0.680 +chany_bottom_out[12] O *C 24.380 0.680 +chany_bottom_out[13] O *C 34.960 0.680 +chany_bottom_out[14] O *C 26.220 0.680 +chany_bottom_out[15] O *C 25.300 0.680 +chany_bottom_out[16] O *C 40.940 0.680 +chany_bottom_out[17] O *C 52.900 0.680 +chany_bottom_out[18] O *C 56.120 0.680 +chany_bottom_out[19] O *C 30.820 0.680 +chany_top_out[0] O *C 53.820 108.120 +chany_top_out[1] O *C 38.640 108.120 +chany_top_out[2] O *C 52.900 108.120 +chany_top_out[3] O *C 59.800 108.120 +chany_top_out[4] O *C 36.800 108.120 +chany_top_out[5] O *C 47.380 108.120 +chany_top_out[6] O *C 65.780 108.120 +chany_top_out[7] O *C 58.880 108.120 +chany_top_out[8] O *C 49.220 108.120 +chany_top_out[9] O *C 55.660 108.120 +chany_top_out[10] O *C 34.040 108.120 +chany_top_out[11] O *C 57.960 108.120 +chany_top_out[12] O *C 51.060 108.120 +chany_top_out[13] O *C 39.560 108.120 +chany_top_out[14] O *C 37.720 108.120 +chany_top_out[15] O *C 24.840 108.120 +chany_top_out[16] O *C 48.300 108.120 +chany_top_out[17] O *C 41.400 108.120 +chany_top_out[18] O *C 28.980 108.120 +chany_top_out[19] O *C 50.140 108.120 +right_grid_pin_52_[0] O *C 83.950 78.880 +left_grid_pin_0_[0] O *C 0.690 102.000 +left_grid_pin_1_[0] O *C 0.690 95.200 +left_grid_pin_2_[0] O *C 0.690 97.920 +left_grid_pin_3_[0] O *C 0.690 96.560 +left_grid_pin_4_[0] O *C 0.690 100.640 +left_grid_pin_5_[0] O *C 0.690 103.360 +left_grid_pin_6_[0] O *C 0.690 80.240 +left_grid_pin_7_[0] O *C 0.690 99.280 +left_grid_pin_8_[0] O *C 0.690 76.160 +left_grid_pin_9_[0] O *C 0.690 81.600 +left_grid_pin_10_[0] O *C 0.690 78.880 +left_grid_pin_11_[0] O *C 0.690 77.520 +left_grid_pin_12_[0] O *C 0.690 35.360 +left_grid_pin_13_[0] O *C 0.690 57.120 +left_grid_pin_14_[0] O *C 0.690 55.760 +left_grid_pin_15_[0] O *C 0.690 34.000 +ccff_tail[0] O *C 83.950 99.280 +VDD I *C 42.320 54.400 +VSS I *C 42.320 54.400 + +*D_NET chany_bottom_in[0] 0.02180639 //LENGTH 169.080 LUMPCC 0.004935066 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 48.300 1.290 +*I mux_right_ipin_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 58.785 12.580 +*I mux_right_ipin_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.760 23.460 +*I mux_left_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 57.500 41.820 +*I mux_right_ipin_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 15.180 58.140 +*I mux_right_ipin_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 19.225 56.100 +*I mux_right_ipin_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 56.945 56.100 +*I mux_right_ipin_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 58.060 72.420 +*I mux_right_ipin_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 58.520 77.860 +*I mux_right_ipin_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 58.420 90.780 +*I BUFT_RR_63:A I *L 0.001776 *C 59.800 99.280 +*N chany_bottom_in[0]:11 *C 59.800 99.280 +*N chany_bottom_in[0]:12 *C 59.800 99.620 +*N chany_bottom_in[0]:13 *C 58.005 99.620 +*N chany_bottom_in[0]:14 *C 57.960 99.575 +*N chany_bottom_in[0]:15 *C 58.383 90.780 +*N chany_bottom_in[0]:16 *C 58.005 90.780 +*N chany_bottom_in[0]:17 *C 57.960 90.780 +*N chany_bottom_in[0]:18 *C 57.960 77.860 +*N chany_bottom_in[0]:19 *C 57.545 77.860 +*N chany_bottom_in[0]:20 *C 58.483 77.860 +*N chany_bottom_in[0]:21 *C 57.500 77.860 +*N chany_bottom_in[0]:22 *C 57.500 77.520 +*N chany_bottom_in[0]:23 *C 57.500 77.505 +*N chany_bottom_in[0]:24 *C 58.023 72.420 +*N chany_bottom_in[0]:25 *C 57.545 72.420 +*N chany_bottom_in[0]:26 *C 57.500 72.420 +*N chany_bottom_in[0]:27 *C 56.983 56.100 +*N chany_bottom_in[0]:28 *C 57.455 56.100 +*N chany_bottom_in[0]:29 *C 57.500 56.100 +*N chany_bottom_in[0]:30 *C 19.225 56.100 +*N chany_bottom_in[0]:31 *C 19.320 56.100 +*N chany_bottom_in[0]:32 *C 15.218 58.140 +*N chany_bottom_in[0]:33 *C 18.815 58.140 +*N chany_bottom_in[0]:34 *C 18.860 58.095 +*N chany_bottom_in[0]:35 *C 18.860 56.100 +*N chany_bottom_in[0]:36 *C 18.860 55.138 +*N chany_bottom_in[0]:37 *C 18.867 55.080 +*N chany_bottom_in[0]:38 *C 57.492 55.080 +*N chany_bottom_in[0]:39 *C 57.500 55.080 +*N chany_bottom_in[0]:40 *C 57.500 41.835 +*N chany_bottom_in[0]:41 *C 57.500 42.160 +*N chany_bottom_in[0]:42 *C 57.500 42.160 +*N chany_bottom_in[0]:43 *C 57.500 23.120 +*N chany_bottom_in[0]:44 *C 55.797 23.460 +*N chany_bottom_in[0]:45 *C 56.580 23.460 +*N chany_bottom_in[0]:46 *C 56.580 23.120 +*N chany_bottom_in[0]:47 *C 56.580 23.120 +*N chany_bottom_in[0]:48 *C 58.748 12.580 +*N chany_bottom_in[0]:49 *C 58.420 12.580 +*N chany_bottom_in[0]:50 *C 58.420 12.920 +*N chany_bottom_in[0]:51 *C 56.625 12.920 +*N chany_bottom_in[0]:52 *C 56.580 12.920 +*N chany_bottom_in[0]:53 *C 56.580 10.258 +*N chany_bottom_in[0]:54 *C 56.573 10.200 +*N chany_bottom_in[0]:55 *C 48.308 10.200 +*N chany_bottom_in[0]:56 *C 48.300 10.143 + +*CAP +0 chany_bottom_in[0] 0.0005056849 +1 mux_right_ipin_13\/mux_l1_in_0_:A1 1e-06 +2 mux_right_ipin_9\/mux_l1_in_0_:A1 1e-06 +3 mux_left_ipin_0\/mux_l1_in_0_:A1 1e-06 +4 mux_right_ipin_3\/mux_l1_in_0_:A1 1e-06 +5 mux_right_ipin_11\/mux_l1_in_0_:A1 1e-06 +6 mux_right_ipin_5\/mux_l1_in_0_:A1 1e-06 +7 mux_right_ipin_15\/mux_l1_in_0_:A1 1e-06 +8 mux_right_ipin_7\/mux_l1_in_0_:A1 1e-06 +9 mux_right_ipin_1\/mux_l1_in_0_:A1 1e-06 +10 BUFT_RR_63:A 1e-06 +11 chany_bottom_in[0]:11 6.330099e-05 +12 chany_bottom_in[0]:12 0.0001863141 +13 chany_bottom_in[0]:13 0.0001555564 +14 chany_bottom_in[0]:14 0.0004174374 +15 chany_bottom_in[0]:15 5.301773e-05 +16 chany_bottom_in[0]:16 5.301773e-05 +17 chany_bottom_in[0]:17 0.0008681499 +18 chany_bottom_in[0]:18 0.0004462298 +19 chany_bottom_in[0]:19 5.444251e-05 +20 chany_bottom_in[0]:20 7.811671e-05 +21 chany_bottom_in[0]:21 0.0001068788 +22 chany_bottom_in[0]:22 6.2245e-05 +23 chany_bottom_in[0]:23 0.0002176436 +24 chany_bottom_in[0]:24 5.426933e-05 +25 chany_bottom_in[0]:25 5.426933e-05 +26 chany_bottom_in[0]:26 0.001005101 +27 chany_bottom_in[0]:27 2.917548e-05 +28 chany_bottom_in[0]:28 2.917548e-05 +29 chany_bottom_in[0]:29 0.0008674806 +30 chany_bottom_in[0]:30 3.08915e-05 +31 chany_bottom_in[0]:31 6.787021e-05 +32 chany_bottom_in[0]:32 0.0002743417 +33 chany_bottom_in[0]:33 0.0002743417 +34 chany_bottom_in[0]:34 0.0001460777 +35 chany_bottom_in[0]:35 0.0002611853 +36 chany_bottom_in[0]:36 8.032801e-05 +37 chany_bottom_in[0]:37 0.002022219 +38 chany_bottom_in[0]:38 0.002022219 +39 chany_bottom_in[0]:39 0.0006229813 +40 chany_bottom_in[0]:40 3.498832e-05 +41 chany_bottom_in[0]:41 6.716205e-05 +42 chany_bottom_in[0]:42 0.001390687 +43 chany_bottom_in[0]:43 0.0008704148 +44 chany_bottom_in[0]:44 7.937862e-05 +45 chany_bottom_in[0]:45 0.0001079104 +46 chany_bottom_in[0]:46 6.169767e-05 +47 chany_bottom_in[0]:47 0.000562122 +48 chany_bottom_in[0]:48 2.959454e-05 +49 chany_bottom_in[0]:49 5.458789e-05 +50 chany_bottom_in[0]:50 0.0001599376 +51 chany_bottom_in[0]:51 0.0001349442 +52 chany_bottom_in[0]:52 0.0007000229 +53 chany_bottom_in[0]:53 0.0001534636 +54 chany_bottom_in[0]:54 0.0004193801 +55 chany_bottom_in[0]:55 0.0004193801 +56 chany_bottom_in[0]:56 0.0005056849 +57 chany_bottom_in[0]:14 chany_bottom_in[6]:19 1.678286e-05 +58 chany_bottom_in[0]:14 chany_bottom_in[6]:11 2.585415e-05 +59 chany_bottom_in[0]:14 chany_bottom_in[6]:15 5.691382e-05 +60 chany_bottom_in[0]:38 chany_bottom_in[6]:28 6.456706e-06 +61 chany_bottom_in[0]:37 chany_bottom_in[6]:29 6.456706e-06 +62 chany_bottom_in[0]:23 chany_bottom_in[6]:19 6.134575e-05 +63 chany_bottom_in[0]:23 chany_bottom_in[6]:20 6.606098e-06 +64 chany_bottom_in[0]:26 chany_bottom_in[6]:19 9.565434e-05 +65 chany_bottom_in[0]:26 chany_bottom_in[6]:20 6.134575e-05 +66 chany_bottom_in[0]:17 chany_bottom_in[6]:14 2.585415e-05 +67 chany_bottom_in[0]:17 chany_bottom_in[6]:16 5.691382e-05 +68 chany_bottom_in[0]:17 chany_bottom_in[6]:19 7.12439e-05 +69 chany_bottom_in[0]:17 chany_bottom_in[6]:20 1.678286e-05 +70 chany_bottom_in[0]:29 chany_bottom_in[6]:20 9.565434e-05 +71 chany_bottom_in[0]:19 chany_bottom_in[6]:19 6.606098e-06 +72 chany_bottom_in[0]:18 chany_bottom_in[6]:20 7.12439e-05 +73 chany_bottom_in[0]:39 chany_bottom_in[16]:43 8.759161e-07 +74 chany_bottom_in[0]:38 chany_bottom_in[16]:38 0.0004278847 +75 chany_bottom_in[0]:38 chany_bottom_in[16]:37 0.0001524968 +76 chany_bottom_in[0]:37 chany_bottom_in[16]:32 0.0001524968 +77 chany_bottom_in[0]:37 chany_bottom_in[16]:37 0.0004278847 +78 chany_bottom_in[0]:52 chany_bottom_in[16]:43 7.904934e-07 +79 chany_bottom_in[0]:42 chany_bottom_in[16]:43 6.10487e-07 +80 chany_bottom_in[0]:42 chany_bottom_in[16]:44 8.759161e-07 +81 chany_bottom_in[0]:53 chany_bottom_in[16]:44 7.904934e-07 +82 chany_bottom_in[0]:43 chany_bottom_in[16]:44 6.10487e-07 +83 chany_bottom_in[0]:14 chany_top_in[0]:66 8.143297e-06 +84 chany_bottom_in[0]:14 chany_top_in[0]:67 1.33601e-05 +85 chany_bottom_in[0]:39 chany_top_in[0]:41 0.0001580365 +86 chany_bottom_in[0]:39 chany_top_in[0]:40 5.78238e-06 +87 chany_bottom_in[0]:39 chany_top_in[0]:37 2.359442e-06 +88 chany_bottom_in[0]:23 chany_top_in[0]:63 5.456297e-05 +89 chany_bottom_in[0]:23 chany_top_in[0]:67 2.228778e-06 +90 chany_bottom_in[0]:20 chany_top_in[0]:62 5.15751e-06 +91 chany_bottom_in[0]:25 chany_top_in[0]:55 1.925506e-06 +92 chany_bottom_in[0]:25 chany_top_in[0]:56 1.335052e-06 +93 chany_bottom_in[0]:26 chany_top_in[0]:54 2.263207e-06 +94 chany_bottom_in[0]:26 chany_top_in[0]:63 1.163435e-05 +95 chany_bottom_in[0]:26 chany_top_in[0]:59 1.388917e-05 +96 chany_bottom_in[0]:26 chany_top_in[0]:60 5.164e-05 +97 chany_bottom_in[0]:24 chany_top_in[0]:57 1.335052e-06 +98 chany_bottom_in[0]:24 chany_top_in[0]:56 1.925506e-06 +99 chany_bottom_in[0]:33 chany_top_in[0]:45 4.790003e-06 +100 chany_bottom_in[0]:34 chany_top_in[0]:46 1.460624e-07 +101 chany_bottom_in[0]:32 chany_top_in[0]:44 4.790003e-06 +102 chany_bottom_in[0]:47 chany_top_in[0]:34 5.174831e-06 +103 chany_bottom_in[0]:17 chany_top_in[0]:63 1.33601e-05 +104 chany_bottom_in[0]:17 chany_top_in[0]:67 0.0003557163 +105 chany_bottom_in[0]:28 chany_top_in[0]:42 6.433571e-06 +106 chany_bottom_in[0]:28 chany_top_in[0]:43 3.161418e-05 +107 chany_bottom_in[0]:29 chany_top_in[0]:41 5.78238e-06 +108 chany_bottom_in[0]:29 chany_top_in[0]:53 2.263207e-06 +109 chany_bottom_in[0]:29 chany_top_in[0]:58 1.388917e-05 +110 chany_bottom_in[0]:29 chany_top_in[0]:60 9.405568e-06 +111 chany_bottom_in[0]:27 chany_top_in[0]:52 3.161418e-05 +112 chany_bottom_in[0]:27 chany_top_in[0]:11 6.433571e-06 +113 chany_bottom_in[0]:42 chany_top_in[0]:36 2.359442e-06 +114 chany_bottom_in[0]:42 chany_top_in[0]:40 0.0001580365 +115 chany_bottom_in[0]:42 chany_top_in[0]:37 7.741567e-05 +116 chany_bottom_in[0]:21 chany_top_in[0]:61 5.15751e-06 +117 chany_bottom_in[0]:35 chany_top_in[0]:50 1.460624e-07 +118 chany_bottom_in[0]:43 chany_top_in[0]:36 7.741567e-05 +119 chany_bottom_in[0]:43 chany_top_in[0]:35 5.174831e-06 +120 chany_bottom_in[0]:19 chany_top_in[0]:67 2.92297e-06 +121 chany_bottom_in[0]:18 chany_top_in[0]:63 0.000347573 +122 chany_bottom_in[0]:47 chany_top_in[14]:21 2.372772e-05 +123 chany_bottom_in[0]:47 chany_top_in[14]:20 2.805253e-05 +124 chany_bottom_in[0]:52 chany_top_in[14]:17 2.805253e-05 +125 chany_bottom_in[0]:52 chany_top_in[14]:20 3.183783e-05 +126 chany_bottom_in[0]:42 chany_top_in[14]:21 0.0002011271 +127 chany_bottom_in[0]:53 chany_top_in[14]:17 8.110117e-06 +128 chany_bottom_in[0]:54 chany_top_in[14]:16 0.000171337 +129 chany_bottom_in[0]:55 chany_top_in[14]:15 0.000171337 +130 chany_bottom_in[0]:43 chany_top_in[14]:20 0.0002011271 +131 chany_bottom_in[0]:38 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002664655 +132 chany_bottom_in[0]:37 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002664655 +133 chany_bottom_in[0] ropt_net_177:7 9.360015e-05 +134 chany_bottom_in[0]:56 ropt_net_177:8 9.360015e-05 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:56 0.007904017 +1 chany_bottom_in[0]:11 BUFT_RR_63:A 0.152 +2 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.001602679 +3 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.0045 +4 chany_bottom_in[0]:39 chany_bottom_in[0]:38 0.00341 +5 chany_bottom_in[0]:39 chany_bottom_in[0]:29 0.0009107143 +6 chany_bottom_in[0]:38 chany_bottom_in[0]:37 0.006051249 +7 chany_bottom_in[0]:36 chany_bottom_in[0]:35 0.0008593751 +8 chany_bottom_in[0]:37 chany_bottom_in[0]:36 0.00341 +9 chany_bottom_in[0]:22 chany_bottom_in[0]:21 0.0003035715 +10 chany_bottom_in[0]:23 chany_bottom_in[0]:22 0.0045 +11 chany_bottom_in[0]:23 chany_bottom_in[0]:19 0.000221875 +12 chany_bottom_in[0]:20 mux_right_ipin_7\/mux_l1_in_0_:A1 0.152 +13 chany_bottom_in[0]:25 chany_bottom_in[0]:24 0.0004263393 +14 chany_bottom_in[0]:26 chany_bottom_in[0]:25 0.0045 +15 chany_bottom_in[0]:26 chany_bottom_in[0]:23 0.004540179 +16 chany_bottom_in[0]:24 mux_right_ipin_15\/mux_l1_in_0_:A1 0.152 +17 chany_bottom_in[0]:33 chany_bottom_in[0]:32 0.003212054 +18 chany_bottom_in[0]:34 chany_bottom_in[0]:33 0.0045 +19 chany_bottom_in[0]:32 mux_right_ipin_3\/mux_l1_in_0_:A1 0.152 +20 chany_bottom_in[0]:46 chany_bottom_in[0]:45 0.0003035715 +21 chany_bottom_in[0]:47 chany_bottom_in[0]:46 0.0045 +22 chany_bottom_in[0]:47 chany_bottom_in[0]:43 0.0008214285 +23 chany_bottom_in[0]:44 mux_right_ipin_9\/mux_l1_in_0_:A1 0.152 +24 chany_bottom_in[0]:16 chany_bottom_in[0]:15 0.0003370536 +25 chany_bottom_in[0]:17 chany_bottom_in[0]:16 0.0045 +26 chany_bottom_in[0]:17 chany_bottom_in[0]:14 0.007852679 +27 chany_bottom_in[0]:15 mux_right_ipin_1\/mux_l1_in_0_:A1 0.152 +28 chany_bottom_in[0]:30 mux_right_ipin_11\/mux_l1_in_0_:A1 0.152 +29 chany_bottom_in[0]:31 chany_bottom_in[0]:30 0.0045 +30 chany_bottom_in[0]:51 chany_bottom_in[0]:50 0.001602679 +31 chany_bottom_in[0]:52 chany_bottom_in[0]:51 0.0045 +32 chany_bottom_in[0]:52 chany_bottom_in[0]:47 0.009107144 +33 chany_bottom_in[0]:48 mux_right_ipin_13\/mux_l1_in_0_:A1 0.152 +34 chany_bottom_in[0]:28 chany_bottom_in[0]:27 0.000421875 +35 chany_bottom_in[0]:29 chany_bottom_in[0]:28 0.0045 +36 chany_bottom_in[0]:29 chany_bottom_in[0]:26 0.01457143 +37 chany_bottom_in[0]:27 mux_right_ipin_5\/mux_l1_in_0_:A1 0.152 +38 chany_bottom_in[0]:41 chany_bottom_in[0]:40 0.0001766305 +39 chany_bottom_in[0]:42 chany_bottom_in[0]:41 0.0045 +40 chany_bottom_in[0]:42 chany_bottom_in[0]:39 0.01153572 +41 chany_bottom_in[0]:40 mux_left_ipin_0\/mux_l1_in_0_:A1 0.152 +42 chany_bottom_in[0]:53 chany_bottom_in[0]:52 0.002377232 +43 chany_bottom_in[0]:54 chany_bottom_in[0]:53 0.00341 +44 chany_bottom_in[0]:56 chany_bottom_in[0]:55 0.00341 +45 chany_bottom_in[0]:55 chany_bottom_in[0]:54 0.00129485 +46 chany_bottom_in[0]:45 chany_bottom_in[0]:44 0.0006986608 +47 chany_bottom_in[0]:50 chany_bottom_in[0]:49 0.0003035715 +48 chany_bottom_in[0]:21 chany_bottom_in[0]:20 0.0008772322 +49 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.0003035715 +50 chany_bottom_in[0]:49 chany_bottom_in[0]:48 0.0002924107 +51 chany_bottom_in[0]:35 chany_bottom_in[0]:34 0.00178125 +52 chany_bottom_in[0]:35 chany_bottom_in[0]:31 0.0004107143 +53 chany_bottom_in[0]:43 chany_bottom_in[0]:42 0.017 +54 chany_bottom_in[0]:19 chany_bottom_in[0]:18 0.0003705357 +55 chany_bottom_in[0]:18 chany_bottom_in[0]:17 0.01153572 + +*END + +*D_NET chany_bottom_in[15] 0.01330207 //LENGTH 118.335 LUMPCC 0.003748492 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 22.540 1.290 +*I mux_right_ipin_10\/mux_l2_in_2_:A0 I *L 0.001631 *C 15.470 38.760 +*I mux_right_ipin_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 20.070 77.180 +*I mux_right_ipin_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 20.070 93.500 +*I FTB_16__15:A I *L 0.001776 *C 16.560 104.720 +*N chany_bottom_in[15]:5 *C 20.590 77.180 +*N chany_bottom_in[15]:6 *C 16.598 104.720 +*N chany_bottom_in[15]:7 *C 19.735 104.720 +*N chany_bottom_in[15]:8 *C 19.780 104.675 +*N chany_bottom_in[15]:9 *C 19.780 99.620 +*N chany_bottom_in[15]:10 *C 20.240 99.620 +*N chany_bottom_in[15]:11 *C 20.070 93.500 +*N chany_bottom_in[15]:12 *C 20.240 93.500 +*N chany_bottom_in[15]:13 *C 20.240 93.500 +*N chany_bottom_in[15]:14 *C 20.070 77.180 +*N chany_bottom_in[15]:15 *C 20.240 77.180 +*N chany_bottom_in[15]:16 *C 20.240 77.180 +*N chany_bottom_in[15]:17 *C 20.242 77.180 +*N chany_bottom_in[15]:18 *C 20.240 77.172 +*N chany_bottom_in[15]:19 *C 15.470 38.760 +*N chany_bottom_in[15]:20 *C 15.640 38.760 +*N chany_bottom_in[15]:21 *C 15.640 38.760 +*N chany_bottom_in[15]:22 *C 15.648 38.760 +*N chany_bottom_in[15]:23 *C 20.220 38.760 +*N chany_bottom_in[15]:24 *C 20.240 38.760 +*N chany_bottom_in[15]:25 *C 21.160 38.760 +*N chany_bottom_in[15]:26 *C 21.160 5.448 +*N chany_bottom_in[15]:27 *C 21.180 5.440 +*N chany_bottom_in[15]:28 *C 22.533 5.440 +*N chany_bottom_in[15]:29 *C 22.540 5.383 + +*CAP +0 chany_bottom_in[15] 0.0002550919 +1 mux_right_ipin_10\/mux_l2_in_2_:A0 1e-06 +2 mux_right_ipin_4\/mux_l2_in_2_:A0 1e-06 +3 mux_right_ipin_2\/mux_l2_in_2_:A0 1e-06 +4 FTB_16__15:A 1e-06 +5 chany_bottom_in[15]:5 6.976276e-05 +6 chany_bottom_in[15]:6 9.973046e-05 +7 chany_bottom_in[15]:7 9.973046e-05 +8 chany_bottom_in[15]:8 0.0002776676 +9 chany_bottom_in[15]:9 0.0003062039 +10 chany_bottom_in[15]:10 0.0003255224 +11 chany_bottom_in[15]:11 6.976423e-05 +12 chany_bottom_in[15]:12 6.600979e-05 +13 chany_bottom_in[15]:13 0.001150595 +14 chany_bottom_in[15]:14 5.739582e-05 +15 chany_bottom_in[15]:15 5.859761e-05 +16 chany_bottom_in[15]:16 0.0008577109 +17 chany_bottom_in[15]:17 6.976276e-05 +18 chany_bottom_in[15]:18 0.001053238 +19 chany_bottom_in[15]:19 4.825641e-05 +20 chany_bottom_in[15]:20 5.259007e-05 +21 chany_bottom_in[15]:21 3.489892e-05 +22 chany_bottom_in[15]:22 0.00028726 +23 chany_bottom_in[15]:23 0.00028726 +24 chany_bottom_in[15]:24 0.001115878 +25 chany_bottom_in[15]:25 0.001257562 +26 chany_bottom_in[15]:26 0.001194922 +27 chany_bottom_in[15]:27 9.95353e-05 +28 chany_bottom_in[15]:28 9.95353e-05 +29 chany_bottom_in[15]:29 0.0002550919 +30 chany_bottom_in[15]:26 chany_bottom_in[9]:31 0.000181751 +31 chany_bottom_in[15]:16 chany_bottom_in[9]:23 6.993553e-07 +32 chany_bottom_in[15]:13 chany_bottom_in[9]:22 6.993553e-07 +33 chany_bottom_in[15]:24 chany_bottom_in[9]:31 0.0004908026 +34 chany_bottom_in[15]:18 chany_bottom_in[9]:30 0.0004908026 +35 chany_bottom_in[15]:25 chany_bottom_in[9]:30 0.000181751 +36 chany_bottom_in[15]:27 chany_bottom_in[13]:27 6.626737e-06 +37 chany_bottom_in[15]:26 chany_bottom_in[13]:29 0.0002877676 +38 chany_bottom_in[15]:26 chany_bottom_in[13]:30 4.361999e-05 +39 chany_bottom_in[15]:28 chany_bottom_in[13]:28 6.626737e-06 +40 chany_bottom_in[15]:25 chany_bottom_in[13]:23 0.0002877676 +41 chany_bottom_in[15]:25 chany_bottom_in[13]:29 4.361999e-05 +42 chany_bottom_in[15]:26 chany_top_in[7]:32 1.058222e-05 +43 chany_bottom_in[15]:13 chany_top_in[7]:39 6.331564e-06 +44 chany_bottom_in[15]:23 chany_top_in[7]:31 4.464831e-05 +45 chany_bottom_in[15]:24 chany_top_in[7]:32 0.0005316976 +46 chany_bottom_in[15]:22 chany_top_in[7]:30 4.464831e-05 +47 chany_bottom_in[15]:18 chany_top_in[7]:33 0.0005316976 +48 chany_bottom_in[15]:10 chany_top_in[7]:40 6.331564e-06 +49 chany_bottom_in[15]:25 chany_top_in[7]:33 1.058222e-05 +50 chany_bottom_in[15]:13 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 5.335233e-05 +51 chany_bottom_in[15]:10 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 5.335233e-05 +52 chany_bottom_in[15]:16 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.246173e-05 +53 chany_bottom_in[15]:13 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.246173e-05 +54 chany_bottom_in[15]:6 ropt_net_160:5 0.0001339053 +55 chany_bottom_in[15]:7 ropt_net_160:4 0.0001339053 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:29 0.003654018 +1 chany_bottom_in[15]:6 FTB_16__15:A 0.152 +2 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.00280134 +3 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.0045 +4 chany_bottom_in[15]:27 chany_bottom_in[15]:26 0.00341 +5 chany_bottom_in[15]:26 chany_bottom_in[15]:25 0.005218958 +6 chany_bottom_in[15]:29 chany_bottom_in[15]:28 0.00341 +7 chany_bottom_in[15]:28 chany_bottom_in[15]:27 0.0002118917 +8 chany_bottom_in[15]:15 chany_bottom_in[15]:14 9.239131e-05 +9 chany_bottom_in[15]:16 chany_bottom_in[15]:15 0.0045 +10 chany_bottom_in[15]:16 chany_bottom_in[15]:13 0.01457143 +11 chany_bottom_in[15]:14 mux_right_ipin_4\/mux_l2_in_2_:A0 0.152 +12 chany_bottom_in[15]:12 chany_bottom_in[15]:11 9.239132e-05 +13 chany_bottom_in[15]:13 chany_bottom_in[15]:12 0.0045 +14 chany_bottom_in[15]:13 chany_bottom_in[15]:10 0.005464286 +15 chany_bottom_in[15]:11 mux_right_ipin_2\/mux_l2_in_2_:A0 0.152 +16 chany_bottom_in[15]:23 chany_bottom_in[15]:22 0.0007163583 +17 chany_bottom_in[15]:24 chany_bottom_in[15]:23 0.00341 +18 chany_bottom_in[15]:24 chany_bottom_in[15]:18 0.006017958 +19 chany_bottom_in[15]:21 chany_bottom_in[15]:20 0.0045 +20 chany_bottom_in[15]:22 chany_bottom_in[15]:21 0.00341 +21 chany_bottom_in[15]:20 chany_bottom_in[15]:19 9.239131e-05 +22 chany_bottom_in[15]:19 mux_right_ipin_10\/mux_l2_in_2_:A0 0.152 +23 chany_bottom_in[15]:17 chany_bottom_in[15]:16 0.00341 +24 chany_bottom_in[15]:17 chany_bottom_in[15]:5 5.103906e-05 +25 chany_bottom_in[15]:18 chany_bottom_in[15]:17 0.00341 +26 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.004513393 +27 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.0004107143 +28 chany_bottom_in[15]:25 chany_bottom_in[15]:24 0.0001441333 + +*END + +*D_NET chany_bottom_in[16] 0.02578479 //LENGTH 205.538 LUMPCC 0.003223494 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 58.420 1.325 +*I mux_right_ipin_11\/mux_l2_in_2_:A0 I *L 0.001631 *C 30.650 55.420 +*I mux_right_ipin_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 23.175 60.520 +*I mux_right_ipin_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 65.035 53.380 +*I mux_left_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 66.415 58.820 +*I ropt_mt_inst_734:A I *L 0.001767 *C 44.620 102.000 +*N chany_bottom_in[16]:6 *C 44.657 102.000 +*N chany_bottom_in[16]:7 *C 46.875 102.000 +*N chany_bottom_in[16]:8 *C 46.920 102.045 +*N chany_bottom_in[16]:9 *C 46.920 106.715 +*N chany_bottom_in[16]:10 *C 46.965 106.760 +*N chany_bottom_in[16]:11 *C 66.655 106.760 +*N chany_bottom_in[16]:12 *C 66.700 106.760 +*N chany_bottom_in[16]:13 *C 66.708 106.760 +*N chany_bottom_in[16]:14 *C 73.580 106.760 +*N chany_bottom_in[16]:15 *C 73.600 106.753 +*N chany_bottom_in[16]:16 *C 73.600 61.208 +*N chany_bottom_in[16]:17 *C 73.580 61.200 +*N chany_bottom_in[16]:18 *C 66.708 61.200 +*N chany_bottom_in[16]:19 *C 66.700 61.143 +*N chany_bottom_in[16]:20 *C 66.415 58.820 +*N chany_bottom_in[16]:21 *C 66.700 58.820 +*N chany_bottom_in[16]:22 *C 66.700 58.820 +*N chany_bottom_in[16]:23 *C 66.700 53.765 +*N chany_bottom_in[16]:24 *C 66.655 53.720 +*N chany_bottom_in[16]:25 *C 64.860 53.720 +*N chany_bottom_in[16]:26 *C 64.910 53.403 +*N chany_bottom_in[16]:27 *C 64.860 53.380 +*N chany_bottom_in[16]:28 *C 23.175 60.520 +*N chany_bottom_in[16]:29 *C 23.000 60.520 +*N chany_bottom_in[16]:30 *C 23.000 60.475 +*N chany_bottom_in[16]:31 *C 23.000 56.498 +*N chany_bottom_in[16]:32 *C 23.008 56.440 +*N chany_bottom_in[16]:33 *C 30.650 55.420 +*N chany_bottom_in[16]:34 *C 30.820 55.420 +*N chany_bottom_in[16]:35 *C 30.820 55.465 +*N chany_bottom_in[16]:36 *C 30.820 56.383 +*N chany_bottom_in[16]:37 *C 30.820 56.440 +*N chany_bottom_in[16]:38 *C 52.433 56.440 +*N chany_bottom_in[16]:39 *C 52.440 56.383 +*N chany_bottom_in[16]:40 *C 52.440 53.425 +*N chany_bottom_in[16]:41 *C 52.485 53.380 +*N chany_bottom_in[16]:42 *C 60.260 53.380 +*N chany_bottom_in[16]:43 *C 60.260 53.335 +*N chany_bottom_in[16]:44 *C 60.260 6.120 +*N chany_bottom_in[16]:45 *C 58.420 6.120 + +*CAP +0 chany_bottom_in[16] 0.0002961284 +1 mux_right_ipin_11\/mux_l2_in_2_:A0 1e-06 +2 mux_right_ipin_3\/mux_l2_in_2_:A0 1e-06 +3 mux_right_ipin_5\/mux_l2_in_2_:A0 1e-06 +4 mux_left_ipin_0\/mux_l2_in_2_:A0 1e-06 +5 ropt_mt_inst_734:A 1e-06 +6 chany_bottom_in[16]:6 0.00022721 +7 chany_bottom_in[16]:7 0.00022721 +8 chany_bottom_in[16]:8 0.0003023693 +9 chany_bottom_in[16]:9 0.0003023693 +10 chany_bottom_in[16]:10 0.001491 +11 chany_bottom_in[16]:11 0.001491 +12 chany_bottom_in[16]:12 3.841261e-05 +13 chany_bottom_in[16]:13 0.0005195056 +14 chany_bottom_in[16]:14 0.0005195056 +15 chany_bottom_in[16]:15 0.002441583 +16 chany_bottom_in[16]:16 0.002441583 +17 chany_bottom_in[16]:17 0.0004619361 +18 chany_bottom_in[16]:18 0.0004619361 +19 chany_bottom_in[16]:19 8.826407e-05 +20 chany_bottom_in[16]:20 4.906071e-05 +21 chany_bottom_in[16]:21 5.327319e-05 +22 chany_bottom_in[16]:22 0.0003637842 +23 chany_bottom_in[16]:23 0.0002458129 +24 chany_bottom_in[16]:24 0.0001492733 +25 chany_bottom_in[16]:25 0.0001682386 +26 chany_bottom_in[16]:26 2.892872e-05 +27 chany_bottom_in[16]:27 0.0002968123 +28 chany_bottom_in[16]:28 5.276094e-05 +29 chany_bottom_in[16]:29 5.64546e-05 +30 chany_bottom_in[16]:30 0.0001961493 +31 chany_bottom_in[16]:31 0.0001961493 +32 chany_bottom_in[16]:32 0.0003368286 +33 chany_bottom_in[16]:33 5.823866e-05 +34 chany_bottom_in[16]:34 6.314852e-05 +35 chany_bottom_in[16]:35 0.0001019907 +36 chany_bottom_in[16]:36 0.0001019907 +37 chany_bottom_in[16]:37 0.00149277 +38 chany_bottom_in[16]:38 0.001155941 +39 chany_bottom_in[16]:39 0.0001900377 +40 chany_bottom_in[16]:40 0.0001900377 +41 chany_bottom_in[16]:41 0.0004343784 +42 chany_bottom_in[16]:42 0.000754194 +43 chany_bottom_in[16]:43 0.002006852 +44 chany_bottom_in[16]:44 0.002106949 +45 chany_bottom_in[16]:45 0.0003962254 +46 chany_bottom_in[16]:43 chany_bottom_in[0]:39 8.759161e-07 +47 chany_bottom_in[16]:43 chany_bottom_in[0]:42 6.10487e-07 +48 chany_bottom_in[16]:43 chany_bottom_in[0]:52 7.904934e-07 +49 chany_bottom_in[16]:38 chany_bottom_in[0]:38 0.0004278847 +50 chany_bottom_in[16]:32 chany_bottom_in[0]:37 0.0001524968 +51 chany_bottom_in[16]:37 chany_bottom_in[0]:37 0.0004278847 +52 chany_bottom_in[16]:37 chany_bottom_in[0]:38 0.0001524968 +53 chany_bottom_in[16]:44 chany_bottom_in[0]:42 8.759161e-07 +54 chany_bottom_in[16]:44 chany_bottom_in[0]:43 6.10487e-07 +55 chany_bottom_in[16]:44 chany_bottom_in[0]:53 7.904934e-07 +56 chany_bottom_in[16] chany_top_in[0]:24 1.170477e-06 +57 chany_bottom_in[16]:43 chany_top_in[0]:41 4.808248e-05 +58 chany_bottom_in[16]:43 chany_top_in[0]:36 9.272501e-07 +59 chany_bottom_in[16]:43 chany_top_in[0]:25 8.215302e-05 +60 chany_bottom_in[16]:43 chany_top_in[0]:37 0.0001675494 +61 chany_bottom_in[16]:43 chany_top_in[0]:30 0.000129886 +62 chany_bottom_in[16]:39 chany_top_in[0]:54 3.045263e-07 +63 chany_bottom_in[16]:40 chany_top_in[0]:53 3.045263e-07 +64 chany_bottom_in[16]:31 chany_top_in[0]:50 5.303367e-06 +65 chany_bottom_in[16]:31 chany_top_in[0]:49 2.575582e-07 +66 chany_bottom_in[16]:30 chany_top_in[0]:50 2.575582e-07 +67 chany_bottom_in[16]:30 chany_top_in[0]:46 5.303367e-06 +68 chany_bottom_in[16]:34 chany_top_in[0]:52 3.586354e-07 +69 chany_bottom_in[16]:33 chany_top_in[0]:51 3.586354e-07 +70 chany_bottom_in[16]:45 chany_top_in[0]:25 1.170477e-06 +71 chany_bottom_in[16]:44 chany_top_in[0]:29 0.000129886 +72 chany_bottom_in[16]:44 chany_top_in[0]:36 0.0001675494 +73 chany_bottom_in[16]:44 chany_top_in[0]:24 8.215302e-05 +74 chany_bottom_in[16]:44 chany_top_in[0]:40 4.808248e-05 +75 chany_bottom_in[16]:44 chany_top_in[0]:31 9.272501e-07 +76 chany_bottom_in[16]:38 chany_top_in[8]:15 5.750371e-05 +77 chany_bottom_in[16]:38 chany_top_in[8]:25 1.630031e-05 +78 chany_bottom_in[16]:38 chany_top_in[8]:26 5.635593e-05 +79 chany_bottom_in[16]:31 chany_top_in[8]:19 3.70874e-05 +80 chany_bottom_in[16]:32 chany_top_in[8]:20 0.0001338261 +81 chany_bottom_in[16]:30 chany_top_in[8]:18 3.70874e-05 +82 chany_bottom_in[16]:37 chany_top_in[8]:20 1.630031e-05 +83 chany_bottom_in[16]:37 chany_top_in[8]:25 0.000190182 +84 chany_bottom_in[16]:37 chany_top_in[8]:26 5.750371e-05 +85 chany_bottom_in[16]:34 chany_top_in[8]:22 1.007333e-06 +86 chany_bottom_in[16]:33 chany_top_in[8]:21 1.007333e-06 +87 chany_bottom_in[16]:23 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.483782e-05 +88 chany_bottom_in[16]:22 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.483782e-05 +89 chany_bottom_in[16]:22 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.929342e-05 +90 chany_bottom_in[16]:19 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.929342e-05 +91 chany_bottom_in[16]:43 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.084155e-05 +92 chany_bottom_in[16]:44 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.084155e-05 +93 chany_bottom_in[16]:9 ropt_net_172:4 7.604252e-05 +94 chany_bottom_in[16]:8 ropt_net_172:5 7.604252e-05 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:45 0.00428125 +1 chany_bottom_in[16]:42 chany_bottom_in[16]:41 0.006941965 +2 chany_bottom_in[16]:42 chany_bottom_in[16]:27 0.004107143 +3 chany_bottom_in[16]:43 chany_bottom_in[16]:42 0.0045 +4 chany_bottom_in[16]:24 chany_bottom_in[16]:23 0.0045 +5 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.004513393 +6 chany_bottom_in[16]:39 chany_bottom_in[16]:38 0.00341 +7 chany_bottom_in[16]:38 chany_bottom_in[16]:37 0.003385958 +8 chany_bottom_in[16]:41 chany_bottom_in[16]:40 0.0045 +9 chany_bottom_in[16]:40 chany_bottom_in[16]:39 0.002640625 +10 chany_bottom_in[16]:31 chany_bottom_in[16]:30 0.003551339 +11 chany_bottom_in[16]:32 chany_bottom_in[16]:31 0.00341 +12 chany_bottom_in[16]:29 chany_bottom_in[16]:28 9.51087e-05 +13 chany_bottom_in[16]:30 chany_bottom_in[16]:29 0.0045 +14 chany_bottom_in[16]:28 mux_right_ipin_3\/mux_l2_in_2_:A0 0.152 +15 chany_bottom_in[16]:36 chany_bottom_in[16]:35 0.0008191965 +16 chany_bottom_in[16]:37 chany_bottom_in[16]:36 0.00341 +17 chany_bottom_in[16]:37 chany_bottom_in[16]:32 0.001223958 +18 chany_bottom_in[16]:34 chany_bottom_in[16]:33 9.23913e-05 +19 chany_bottom_in[16]:35 chany_bottom_in[16]:34 0.0045 +20 chany_bottom_in[16]:33 mux_right_ipin_11\/mux_l2_in_2_:A0 0.152 +21 chany_bottom_in[16]:26 mux_right_ipin_5\/mux_l2_in_2_:A0 0.152 +22 chany_bottom_in[16]:26 chany_bottom_in[16]:25 0.0002834821 +23 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.0001548913 +24 chany_bottom_in[16]:22 chany_bottom_in[16]:21 0.0045 +25 chany_bottom_in[16]:22 chany_bottom_in[16]:19 0.002073661 +26 chany_bottom_in[16]:20 mux_left_ipin_0\/mux_l2_in_2_:A0 0.152 +27 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.00341 +28 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.001076692 +29 chany_bottom_in[16]:17 chany_bottom_in[16]:16 0.00341 +30 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.007135383 +31 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.001076692 +32 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.00341 +33 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.0045 +34 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.00341 +35 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.01758036 +36 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.0045 +37 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.004169643 +38 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.001979911 +39 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.0045 +40 chany_bottom_in[16]:6 ropt_mt_inst_734:A 0.152 +41 chany_bottom_in[16]:27 chany_bottom_in[16]:26 4.464286e-05 +42 chany_bottom_in[16]:25 chany_bottom_in[16]:24 0.001602679 +43 chany_bottom_in[16]:45 chany_bottom_in[16]:44 0.001642857 +44 chany_bottom_in[16]:44 chany_bottom_in[16]:43 0.04215625 + +*END + +*D_NET chany_bottom_in[17] 0.01608792 //LENGTH 125.050 LUMPCC 0.004622092 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 33.580 1.290 +*I mux_right_ipin_12\/mux_l2_in_2_:A0 I *L 0.001631 *C 29.730 17.340 +*I mux_right_ipin_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 43.065 86.020 +*I FTB_18__17:A I *L 0.001767 *C 41.860 104.720 +*N chany_bottom_in[17]:4 *C 41.860 104.720 +*N chany_bottom_in[17]:5 *C 41.860 104.675 +*N chany_bottom_in[17]:6 *C 43.028 86.020 +*N chany_bottom_in[17]:7 *C 41.905 86.020 +*N chany_bottom_in[17]:8 *C 41.860 86.020 +*N chany_bottom_in[17]:9 *C 41.860 80.625 +*N chany_bottom_in[17]:10 *C 41.815 80.580 +*N chany_bottom_in[17]:11 *C 29.485 80.580 +*N chany_bottom_in[17]:12 *C 29.440 80.535 +*N chany_bottom_in[17]:13 *C 29.440 39.780 +*N chany_bottom_in[17]:14 *C 29.900 39.780 +*N chany_bottom_in[17]:15 *C 29.900 34.680 +*N chany_bottom_in[17]:16 *C 29.440 34.680 +*N chany_bottom_in[17]:17 *C 29.440 30.940 +*N chany_bottom_in[17]:18 *C 29.900 30.940 +*N chany_bottom_in[17]:19 *C 29.730 17.340 +*N chany_bottom_in[17]:20 *C 29.900 17.340 +*N chany_bottom_in[17]:21 *C 29.900 17.340 +*N chany_bottom_in[17]:22 *C 29.900 10.258 +*N chany_bottom_in[17]:23 *C 29.908 10.200 +*N chany_bottom_in[17]:24 *C 33.573 10.200 +*N chany_bottom_in[17]:25 *C 33.580 10.143 + +*CAP +0 chany_bottom_in[17] 0.0005929342 +1 mux_right_ipin_12\/mux_l2_in_2_:A0 1e-06 +2 mux_right_ipin_0\/mux_l2_in_2_:A0 1e-06 +3 FTB_18__17:A 1e-06 +4 chany_bottom_in[17]:4 3.697637e-05 +5 chany_bottom_in[17]:5 0.0008534173 +6 chany_bottom_in[17]:6 9.480368e-05 +7 chany_bottom_in[17]:7 9.480368e-05 +8 chany_bottom_in[17]:8 0.001097764 +9 chany_bottom_in[17]:9 0.0002141738 +10 chany_bottom_in[17]:10 0.0006415957 +11 chany_bottom_in[17]:11 0.0006415957 +12 chany_bottom_in[17]:12 0.001771356 +13 chany_bottom_in[17]:13 0.001802052 +14 chany_bottom_in[17]:14 0.0002596833 +15 chany_bottom_in[17]:15 0.000261611 +16 chany_bottom_in[17]:16 0.0002596054 +17 chany_bottom_in[17]:17 0.0002578413 +18 chany_bottom_in[17]:18 0.0004441351 +19 chany_bottom_in[17]:19 5.931081e-05 +20 chany_bottom_in[17]:20 6.525889e-05 +21 chany_bottom_in[17]:21 0.0006842302 +22 chany_bottom_in[17]:22 0.0002385303 +23 chany_bottom_in[17]:23 0.0002491071 +24 chany_bottom_in[17]:24 0.0002491071 +25 chany_bottom_in[17]:25 0.0005929342 +26 chany_bottom_in[17]:12 chany_bottom_in[3]:29 2.545535e-06 +27 chany_bottom_in[17]:12 chany_bottom_in[3]:32 0.0002822949 +28 chany_bottom_in[17]:13 chany_bottom_in[3]:31 2.545535e-06 +29 chany_bottom_in[17]:13 chany_bottom_in[3]:33 0.0002822949 +30 chany_bottom_in[17]:5 chany_bottom_in[19]:12 1.827673e-06 +31 chany_bottom_in[17]:5 chany_bottom_in[19]:15 0.0004131483 +32 chany_bottom_in[17]:5 chany_bottom_in[19]:13 1.631851e-06 +33 chany_bottom_in[17]:8 chany_bottom_in[19]:16 0.0004131483 +34 chany_bottom_in[17]:8 chany_bottom_in[19]:14 1.631851e-06 +35 chany_bottom_in[17]:8 chany_bottom_in[19]:15 0.000150002 +36 chany_bottom_in[17]:8 chany_bottom_in[19]:13 1.827673e-06 +37 chany_bottom_in[17]:12 chany_bottom_in[19]:28 4.107517e-05 +38 chany_bottom_in[17]:9 chany_bottom_in[19]:16 0.000150002 +39 chany_bottom_in[17]:15 chany_bottom_in[19]:27 5.278783e-06 +40 chany_bottom_in[17]:13 chany_bottom_in[19]:27 4.107517e-05 +41 chany_bottom_in[17]:14 chany_bottom_in[19]:28 5.278783e-06 +42 chany_bottom_in[17]:21 chany_top_in[1]:21 1.288309e-05 +43 chany_bottom_in[17]:21 chany_top_in[1]:29 7.596664e-05 +44 chany_bottom_in[17]:21 chany_top_in[1]:26 0.000159939 +45 chany_bottom_in[17]:22 chany_top_in[1]:22 1.288309e-05 +46 chany_bottom_in[17]:22 chany_top_in[1]:26 7.596664e-05 +47 chany_bottom_in[17]:12 chany_top_in[1]:47 6.696039e-07 +48 chany_bottom_in[17]:12 chany_top_in[1]:43 0.0003718603 +49 chany_bottom_in[17]:12 chany_top_in[1]:37 2.859012e-05 +50 chany_bottom_in[17]:12 chany_top_in[1]:46 3.116524e-06 +51 chany_bottom_in[17]:17 chany_top_in[1]:29 5.259828e-06 +52 chany_bottom_in[17]:17 chany_top_in[1]:26 7.426146e-06 +53 chany_bottom_in[17]:18 chany_top_in[1]:29 0.000159939 +54 chany_bottom_in[17]:16 chany_top_in[1]:29 7.426146e-06 +55 chany_bottom_in[17]:16 chany_top_in[1]:30 5.259828e-06 +56 chany_bottom_in[17]:15 chany_top_in[1]:34 6.824781e-05 +57 chany_bottom_in[17]:15 chany_top_in[1]:29 1.412038e-05 +58 chany_bottom_in[17]:15 chany_top_in[1]:31 1.49047e-05 +59 chany_bottom_in[17]:13 chany_top_in[1]:43 3.116524e-06 +60 chany_bottom_in[17]:13 chany_top_in[1]:37 0.0003718603 +61 chany_bottom_in[17]:13 chany_top_in[1]:34 2.859012e-05 +62 chany_bottom_in[17]:13 chany_top_in[1]:46 6.696039e-07 +63 chany_bottom_in[17]:14 chany_top_in[1]:37 6.824781e-05 +64 chany_bottom_in[17]:14 chany_top_in[1]:34 1.49047e-05 +65 chany_bottom_in[17]:14 chany_top_in[1]:30 1.412038e-05 +66 chany_bottom_in[17]:21 chany_top_in[9]:6 0.0002868014 +67 chany_bottom_in[17]:21 chany_top_in[9]:9 0.0001688766 +68 chany_bottom_in[17]:22 chany_top_in[9]:6 0.0001375234 +69 chany_bottom_in[17]:18 chany_top_in[9]:10 3.135321e-05 +70 chany_bottom_in[17]:18 chany_top_in[9]:9 0.0002868014 +71 chany_bottom_in[17]:11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001507449 +72 chany_bottom_in[17]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001507449 +73 chany_bottom_in[17]:12 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.383522e-05 +74 chany_bottom_in[17]:13 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.383522e-05 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:25 0.007904017 +1 chany_bottom_in[17]:4 FTB_18__17:A 0.152 +2 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.0045 +3 chany_bottom_in[17]:20 chany_bottom_in[17]:19 9.239132e-05 +4 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.0045 +5 chany_bottom_in[17]:21 chany_bottom_in[17]:18 0.01214286 +6 chany_bottom_in[17]:19 mux_right_ipin_12\/mux_l2_in_2_:A0 0.152 +7 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.001002232 +8 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.0045 +9 chany_bottom_in[17]:8 chany_bottom_in[17]:5 0.01665625 +10 chany_bottom_in[17]:6 mux_right_ipin_0\/mux_l2_in_2_:A0 0.152 +11 chany_bottom_in[17]:22 chany_bottom_in[17]:21 0.006323661 +12 chany_bottom_in[17]:23 chany_bottom_in[17]:22 0.00341 +13 chany_bottom_in[17]:25 chany_bottom_in[17]:24 0.00341 +14 chany_bottom_in[17]:24 chany_bottom_in[17]:23 0.0005741833 +15 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.01100893 +16 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.0045 +17 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.0045 +18 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.004816964 +19 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.003339286 +20 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.0004107143 +21 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.0004107143 +22 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.004553572 +23 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.0363884 +24 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.0004107143 + +*END + +*D_NET chany_bottom_in[18] 0.01881956 //LENGTH 156.400 LUMPCC 0.004586784 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 67.160 1.325 +*I mux_right_ipin_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 45.830 91.800 +*I FTB_19__18:A I *L 0.001767 *C 25.300 102.000 +*I mux_right_ipin_13\/mux_l2_in_2_:A0 I *L 0.001631 *C 58.710 17.340 +*N chany_bottom_in[18]:4 *C 58.748 17.340 +*N chany_bottom_in[18]:5 *C 63.690 51.000 +*N chany_bottom_in[18]:6 *C 25.263 102.000 +*N chany_bottom_in[18]:7 *C 23.920 102.000 +*N chany_bottom_in[18]:8 *C 23.920 101.320 +*N chany_bottom_in[18]:9 *C 40.480 101.320 +*N chany_bottom_in[18]:10 *C 40.480 101.660 +*N chany_bottom_in[18]:11 *C 42.780 101.660 +*N chany_bottom_in[18]:12 *C 42.780 101.320 +*N chany_bottom_in[18]:13 *C 45.955 101.320 +*N chany_bottom_in[18]:14 *C 46.000 101.275 +*N chany_bottom_in[18]:15 *C 45.830 91.800 +*N chany_bottom_in[18]:16 *C 46.000 91.800 +*N chany_bottom_in[18]:17 *C 46.000 91.800 +*N chany_bottom_in[18]:18 *C 46.008 91.800 +*N chany_bottom_in[18]:19 *C 64.380 91.800 +*N chany_bottom_in[18]:20 *C 64.400 91.793 +*N chany_bottom_in[18]:21 *C 64.400 51.008 +*N chany_bottom_in[18]:22 *C 64.398 51.000 +*N chany_bottom_in[18]:23 *C 64.400 50.943 +*N chany_bottom_in[18]:24 *C 64.400 17.385 +*N chany_bottom_in[18]:25 *C 64.400 17.310 +*N chany_bottom_in[18]:26 *C 64.400 17.000 +*N chany_bottom_in[18]:27 *C 67.115 17.000 +*N chany_bottom_in[18]:28 *C 67.160 16.955 + +*CAP +0 chany_bottom_in[18] 0.0005853163 +1 mux_right_ipin_1\/mux_l2_in_2_:A0 1e-06 +2 FTB_19__18:A 1e-06 +3 mux_right_ipin_13\/mux_l2_in_2_:A0 1e-06 +4 chany_bottom_in[18]:4 0.0002571959 +5 chany_bottom_in[18]:5 6.055943e-05 +6 chany_bottom_in[18]:6 7.78912e-05 +7 chany_bottom_in[18]:7 0.0001190086 +8 chany_bottom_in[18]:8 0.00111884 +9 chany_bottom_in[18]:9 0.001105525 +10 chany_bottom_in[18]:10 0.0002063884 +11 chany_bottom_in[18]:11 0.0002056258 +12 chany_bottom_in[18]:12 0.0002900045 +13 chany_bottom_in[18]:13 0.0002629647 +14 chany_bottom_in[18]:14 0.000410156 +15 chany_bottom_in[18]:15 5.213609e-05 +16 chany_bottom_in[18]:16 5.680074e-05 +17 chany_bottom_in[18]:17 0.0004465631 +18 chany_bottom_in[18]:18 0.001417231 +19 chany_bottom_in[18]:19 0.001417231 +20 chany_bottom_in[18]:20 0.001024968 +21 chany_bottom_in[18]:21 0.001024968 +22 chany_bottom_in[18]:22 6.055943e-05 +23 chany_bottom_in[18]:23 0.001371205 +24 chany_bottom_in[18]:24 0.001371205 +25 chany_bottom_in[18]:25 0.0002810726 +26 chany_bottom_in[18]:26 0.0002224625 +27 chany_bottom_in[18]:27 0.0001985858 +28 chany_bottom_in[18]:28 0.0005853163 +29 chany_bottom_in[18] chany_bottom_in[10] 0.0002144036 +30 chany_bottom_in[18]:20 chany_bottom_in[10]:14 0.0003223514 +31 chany_bottom_in[18]:20 chany_bottom_in[10]:21 6.532486e-05 +32 chany_bottom_in[18]:22 chany_bottom_in[10]:23 1.701659e-05 +33 chany_bottom_in[18]:21 chany_bottom_in[10]:21 0.0003223514 +34 chany_bottom_in[18]:21 chany_bottom_in[10]:22 6.532486e-05 +35 chany_bottom_in[18]:28 chany_bottom_in[10]:37 0.0002144036 +36 chany_bottom_in[18]:5 chany_bottom_in[10]:24 1.701659e-05 +37 chany_bottom_in[18]:17 chany_top_in[11]:20 0.0002526092 +38 chany_bottom_in[18]:14 chany_top_in[11] 0.0002526092 +39 chany_bottom_in[18]:23 chany_top_in[14]:26 0.000350178 +40 chany_bottom_in[18]:24 chany_top_in[14]:25 0.000350178 +41 chany_bottom_in[18]:20 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.0006049675 +42 chany_bottom_in[18]:21 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.0006049675 +43 chany_bottom_in[18]:23 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 2.377631e-07 +44 chany_bottom_in[18]:24 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 2.377631e-07 +45 chany_bottom_in[18]:23 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.488308e-05 +46 chany_bottom_in[18]:25 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.717111e-06 +47 chany_bottom_in[18]:24 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.488308e-05 +48 chany_bottom_in[18]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.717111e-06 +49 chany_bottom_in[18]:27 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.074444e-06 +50 chany_bottom_in[18]:26 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.074444e-06 +51 chany_bottom_in[18]:25 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002108175 +52 chany_bottom_in[18]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002084759 +53 chany_bottom_in[18]:27 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.414239e-06 +54 chany_bottom_in[18]:26 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.341624e-06 +55 chany_bottom_in[18]:26 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.414239e-06 +56 chany_bottom_in[18]:23 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.077545e-05 +57 chany_bottom_in[18]:24 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.077545e-05 +58 chany_bottom_in[18]:6 ropt_net_163:3 4.490802e-05 +59 chany_bottom_in[18]:8 ropt_net_163:4 7.118478e-05 +60 chany_bottom_in[18]:8 ropt_net_163:3 5.283466e-07 +61 chany_bottom_in[18]:7 ropt_net_163:2 5.283466e-07 +62 chany_bottom_in[18]:7 ropt_net_163:4 4.490802e-05 +63 chany_bottom_in[18]:9 ropt_net_163:3 7.118478e-05 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:28 0.01395536 +1 chany_bottom_in[18]:17 chany_bottom_in[18]:16 0.0045 +2 chany_bottom_in[18]:17 chany_bottom_in[18]:14 0.008459821 +3 chany_bottom_in[18]:18 chany_bottom_in[18]:17 0.00341 +4 chany_bottom_in[18]:19 chany_bottom_in[18]:18 0.002878358 +5 chany_bottom_in[18]:20 chany_bottom_in[18]:19 0.00341 +6 chany_bottom_in[18]:22 chany_bottom_in[18]:21 0.00341 +7 chany_bottom_in[18]:22 chany_bottom_in[18]:5 0.000103914 +8 chany_bottom_in[18]:21 chany_bottom_in[18]:20 0.00638965 +9 chany_bottom_in[18]:23 chany_bottom_in[18]:22 0.00341 +10 chany_bottom_in[18]:25 chany_bottom_in[18]:24 0.0045 +11 chany_bottom_in[18]:25 chany_bottom_in[18]:4 0.005046875 +12 chany_bottom_in[18]:24 chany_bottom_in[18]:23 0.02996206 +13 chany_bottom_in[18]:6 FTB_19__18:A 0.152 +14 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.002834822 +15 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.0045 +16 chany_bottom_in[18]:16 chany_bottom_in[18]:15 9.239131e-05 +17 chany_bottom_in[18]:15 mux_right_ipin_1\/mux_l2_in_2_:A0 0.152 +18 chany_bottom_in[18]:4 mux_right_ipin_13\/mux_l2_in_2_:A0 0.152 +19 chany_bottom_in[18]:27 chany_bottom_in[18]:26 0.002424107 +20 chany_bottom_in[18]:28 chany_bottom_in[18]:27 0.0045 +21 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.000607143 +22 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.001198661 +23 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.01478572 +24 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.0003035715 +25 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.002053572 +26 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.0003035715 +27 chany_bottom_in[18]:26 chany_bottom_in[18]:25 0.0002767858 + +*END + +*D_NET chany_bottom_in[19] 0.01961864 //LENGTH 152.705 LUMPCC 0.003910676 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 50.140 1.290 +*I mux_right_ipin_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 26.970 39.100 +*I mux_right_ipin_6\/mux_l2_in_2_:A0 I *L 0.001631 *C 43.070 59.160 +*I ropt_mt_inst_749:A I *L 0.001766 *C 52.900 99.280 +*I mux_right_ipin_14\/mux_l2_in_2_:A0 I *L 0.001631 *C 43.070 42.500 +*N chany_bottom_in[19]:5 *C 43.070 42.500 +*N chany_bottom_in[19]:6 *C 52.863 99.280 +*N chany_bottom_in[19]:7 *C 50.185 99.280 +*N chany_bottom_in[19]:8 *C 50.140 99.325 +*N chany_bottom_in[19]:9 *C 50.140 102.635 +*N chany_bottom_in[19]:10 *C 50.095 102.680 +*N chany_bottom_in[19]:11 *C 40.985 102.680 +*N chany_bottom_in[19]:12 *C 40.940 102.635 +*N chany_bottom_in[19]:13 *C 40.940 102.000 +*N chany_bottom_in[19]:14 *C 40.940 101.320 +*N chany_bottom_in[19]:15 *C 41.400 101.320 +*N chany_bottom_in[19]:16 *C 41.400 66.685 +*N chany_bottom_in[19]:17 *C 41.445 66.640 +*N chany_bottom_in[19]:18 *C 42.735 66.640 +*N chany_bottom_in[19]:19 *C 42.780 66.595 +*N chany_bottom_in[19]:20 *C 43.070 59.160 +*N chany_bottom_in[19]:21 *C 42.780 59.160 +*N chany_bottom_in[19]:22 *C 42.780 59.160 +*N chany_bottom_in[19]:23 *C 42.780 42.885 +*N chany_bottom_in[19]:24 *C 42.825 42.833 +*N chany_bottom_in[19]:25 *C 27.008 39.100 +*N chany_bottom_in[19]:26 *C 28.475 39.100 +*N chany_bottom_in[19]:27 *C 28.520 39.145 +*N chany_bottom_in[19]:28 *C 28.520 42.795 +*N chany_bottom_in[19]:29 *C 28.565 42.840 +*N chany_bottom_in[19]:30 *C 41.860 42.840 +*N chany_bottom_in[19]:31 *C 41.860 42.795 +*N chany_bottom_in[19]:32 *C 41.860 31.338 +*N chany_bottom_in[19]:33 *C 41.867 31.280 +*N chany_bottom_in[19]:34 *C 46.900 31.280 +*N chany_bottom_in[19]:35 *C 46.920 31.273 +*N chany_bottom_in[19]:36 *C 46.920 6.808 +*N chany_bottom_in[19]:37 *C 46.940 6.800 +*N chany_bottom_in[19]:38 *C 50.133 6.800 +*N chany_bottom_in[19]:39 *C 50.140 6.743 + +*CAP +0 chany_bottom_in[19] 0.0003200239 +1 mux_right_ipin_8\/mux_l2_in_2_:A0 1e-06 +2 mux_right_ipin_6\/mux_l2_in_2_:A0 1e-06 +3 ropt_mt_inst_749:A 1e-06 +4 mux_right_ipin_14\/mux_l2_in_2_:A0 1e-06 +5 chany_bottom_in[19]:5 6.384811e-05 +6 chany_bottom_in[19]:6 0.0001777888 +7 chany_bottom_in[19]:7 0.0001777888 +8 chany_bottom_in[19]:8 0.0001710319 +9 chany_bottom_in[19]:9 0.0001710319 +10 chany_bottom_in[19]:10 0.0007638328 +11 chany_bottom_in[19]:11 0.0007638328 +12 chany_bottom_in[19]:12 5.408588e-05 +13 chany_bottom_in[19]:13 8.495149e-05 +14 chany_bottom_in[19]:14 6.69205e-05 +15 chany_bottom_in[19]:15 0.00158311 +16 chany_bottom_in[19]:16 0.001547055 +17 chany_bottom_in[19]:17 9.507849e-05 +18 chany_bottom_in[19]:18 9.507849e-05 +19 chany_bottom_in[19]:19 0.0003016195 +20 chany_bottom_in[19]:20 5.205375e-05 +21 chany_bottom_in[19]:21 5.683534e-05 +22 chany_bottom_in[19]:22 0.001026089 +23 chany_bottom_in[19]:23 0.0006890541 +24 chany_bottom_in[19]:24 0.0001043196 +25 chany_bottom_in[19]:25 0.0001385739 +26 chany_bottom_in[19]:26 0.0001385739 +27 chany_bottom_in[19]:27 0.0001843038 +28 chany_bottom_in[19]:28 0.0001843038 +29 chany_bottom_in[19]:29 0.000956799 +30 chany_bottom_in[19]:30 0.001052508 +31 chany_bottom_in[19]:31 0.0005437777 +32 chany_bottom_in[19]:32 0.0005437777 +33 chany_bottom_in[19]:33 0.000369128 +34 chany_bottom_in[19]:34 0.000369128 +35 chany_bottom_in[19]:35 0.001031011 +36 chany_bottom_in[19]:36 0.001031011 +37 chany_bottom_in[19]:37 0.0002378066 +38 chany_bottom_in[19]:38 0.0002378066 +39 chany_bottom_in[19]:39 0.0003200239 +40 chany_bottom_in[19]:31 chany_bottom_in[6]:30 1.644257e-05 +41 chany_bottom_in[19]:32 chany_bottom_in[6]:31 1.644257e-05 +42 chany_bottom_in[19]:35 chany_bottom_in[6]:30 0.000312041 +43 chany_bottom_in[19]:36 chany_bottom_in[6]:31 0.000312041 +44 chany_bottom_in[19]:16 chany_bottom_in[17]:8 0.0004131483 +45 chany_bottom_in[19]:16 chany_bottom_in[17]:9 0.000150002 +46 chany_bottom_in[19]:12 chany_bottom_in[17]:5 1.827673e-06 +47 chany_bottom_in[19]:28 chany_bottom_in[17]:12 4.107517e-05 +48 chany_bottom_in[19]:28 chany_bottom_in[17]:14 5.278783e-06 +49 chany_bottom_in[19]:27 chany_bottom_in[17]:13 4.107517e-05 +50 chany_bottom_in[19]:27 chany_bottom_in[17]:15 5.278783e-06 +51 chany_bottom_in[19]:14 chany_bottom_in[17]:8 1.631851e-06 +52 chany_bottom_in[19]:15 chany_bottom_in[17]:5 0.0004131483 +53 chany_bottom_in[19]:15 chany_bottom_in[17]:8 0.000150002 +54 chany_bottom_in[19]:13 chany_bottom_in[17]:5 1.631851e-06 +55 chany_bottom_in[19]:13 chany_bottom_in[17]:8 1.827673e-06 +56 chany_bottom_in[19]:19 chany_top_in[11]:16 0.0001957849 +57 chany_bottom_in[19]:16 chany_top_in[11]:13 1.830579e-05 +58 chany_bottom_in[19]:30 chany_top_in[11]:8 2.415801e-06 +59 chany_bottom_in[19]:31 chany_top_in[11]:13 3.028237e-06 +60 chany_bottom_in[19]:31 chany_top_in[11]:10 6.613867e-05 +61 chany_bottom_in[19]:32 chany_top_in[11]:10 3.028237e-06 +62 chany_bottom_in[19]:32 chany_top_in[11]:7 6.613867e-05 +63 chany_bottom_in[19]:24 chany_top_in[11]:9 2.415801e-06 +64 chany_bottom_in[19]:23 chany_top_in[11]:13 2.509416e-05 +65 chany_bottom_in[19]:23 chany_top_in[11]:10 0.0003988484 +66 chany_bottom_in[19]:22 chany_top_in[11]:13 0.0005946333 +67 chany_bottom_in[19]:22 chany_top_in[11]:16 2.509416e-05 +68 chany_bottom_in[19]:15 chany_top_in[11]:16 1.830579e-05 +69 chany_bottom_in[19]:16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.488867e-05 +70 chany_bottom_in[19]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.488867e-05 +71 chany_bottom_in[19]:30 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001142638 +72 chany_bottom_in[19]:31 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.306155e-08 +73 chany_bottom_in[19]:32 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.306155e-08 +74 chany_bottom_in[19]:29 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001142638 +75 chany_bottom_in[19]:11 ropt_net_169:2 8.994408e-06 +76 chany_bottom_in[19]:10 ropt_net_169:3 8.994408e-06 +77 chany_bottom_in[19]:9 ropt_net_169:4 6.8521e-05 +78 chany_bottom_in[19]:7 ropt_net_169:6 3.758378e-05 +79 chany_bottom_in[19]:8 ropt_net_169:5 6.8521e-05 +80 chany_bottom_in[19]:6 ropt_net_169:7 3.758378e-05 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:39 0.004868303 +1 chany_bottom_in[19]:18 chany_bottom_in[19]:17 0.001151786 +2 chany_bottom_in[19]:19 chany_bottom_in[19]:18 0.0045 +3 chany_bottom_in[19]:17 chany_bottom_in[19]:16 0.0045 +4 chany_bottom_in[19]:16 chany_bottom_in[19]:15 0.03092411 +5 chany_bottom_in[19]:11 chany_bottom_in[19]:10 0.008133929 +6 chany_bottom_in[19]:12 chany_bottom_in[19]:11 0.0045 +7 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.0045 +8 chany_bottom_in[19]:9 chany_bottom_in[19]:8 0.002955357 +9 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.002390625 +10 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.0045 +11 chany_bottom_in[19]:6 ropt_mt_inst_749:A 0.152 +12 chany_bottom_in[19]:30 chany_bottom_in[19]:29 0.01187054 +13 chany_bottom_in[19]:30 chany_bottom_in[19]:24 0.0008616072 +14 chany_bottom_in[19]:31 chany_bottom_in[19]:30 0.0045 +15 chany_bottom_in[19]:32 chany_bottom_in[19]:31 0.01022991 +16 chany_bottom_in[19]:33 chany_bottom_in[19]:32 0.00341 +17 chany_bottom_in[19]:34 chany_bottom_in[19]:33 0.000788425 +18 chany_bottom_in[19]:35 chany_bottom_in[19]:34 0.00341 +19 chany_bottom_in[19]:37 chany_bottom_in[19]:36 0.00341 +20 chany_bottom_in[19]:36 chany_bottom_in[19]:35 0.00383285 +21 chany_bottom_in[19]:39 chany_bottom_in[19]:38 0.00341 +22 chany_bottom_in[19]:38 chany_bottom_in[19]:37 0.0005001583 +23 chany_bottom_in[19]:24 chany_bottom_in[19]:23 0.0045 +24 chany_bottom_in[19]:24 chany_bottom_in[19]:5 0.0001807065 +25 chany_bottom_in[19]:23 chany_bottom_in[19]:22 0.01453125 +26 chany_bottom_in[19]:21 chany_bottom_in[19]:20 0.0001576087 +27 chany_bottom_in[19]:22 chany_bottom_in[19]:21 0.0045 +28 chany_bottom_in[19]:22 chany_bottom_in[19]:19 0.006638393 +29 chany_bottom_in[19]:20 mux_right_ipin_6\/mux_l2_in_2_:A0 0.152 +30 chany_bottom_in[19]:5 mux_right_ipin_14\/mux_l2_in_2_:A0 0.152 +31 chany_bottom_in[19]:29 chany_bottom_in[19]:28 0.0045 +32 chany_bottom_in[19]:28 chany_bottom_in[19]:27 0.003258929 +33 chany_bottom_in[19]:26 chany_bottom_in[19]:25 0.001310268 +34 chany_bottom_in[19]:27 chany_bottom_in[19]:26 0.0045 +35 chany_bottom_in[19]:25 mux_right_ipin_8\/mux_l2_in_2_:A0 0.152 +36 chany_bottom_in[19]:14 chany_bottom_in[19]:13 0.0006071429 +37 chany_bottom_in[19]:15 chany_bottom_in[19]:14 0.0004107143 +38 chany_bottom_in[19]:13 chany_bottom_in[19]:12 0.0005669643 + +*END + +*D_NET chany_top_in[0] 0.02586374 //LENGTH 203.710 LUMPCC 0.003795595 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 54.740 107.510 +*I mux_right_ipin_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 58.710 91.460 +*I mux_right_ipin_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 58.135 77.180 +*I mux_right_ipin_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.675 71.400 +*I mux_right_ipin_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 19.610 55.080 +*I mux_right_ipin_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 14.895 59.160 +*I mux_left_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.215 42.840 +*I mux_right_ipin_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.375 22.440 +*I mux_right_ipin_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 59.170 11.900 +*I ropt_mt_inst_757:A I *L 0.001766 *C 51.980 9.520 +*I mux_right_ipin_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.330 55.420 +*N chany_top_in[0]:11 *C 57.367 55.420 +*N chany_top_in[0]:12 *C 52.018 9.520 +*N chany_top_in[0]:13 *C 52.395 9.520 +*N chany_top_in[0]:14 *C 52.440 9.475 +*N chany_top_in[0]:15 *C 52.440 1.745 +*N chany_top_in[0]:16 *C 52.485 1.700 +*N chany_top_in[0]:17 *C 64.355 1.700 +*N chany_top_in[0]:18 *C 64.400 1.745 +*N chany_top_in[0]:19 *C 64.400 4.035 +*N chany_top_in[0]:20 *C 64.355 4.080 +*N chany_top_in[0]:21 *C 63.480 4.080 +*N chany_top_in[0]:22 *C 63.445 4.420 +*N chany_top_in[0]:23 *C 61.225 4.420 +*N chany_top_in[0]:24 *C 61.180 4.465 +*N chany_top_in[0]:25 *C 61.180 11.855 +*N chany_top_in[0]:26 *C 61.135 11.900 +*N chany_top_in[0]:27 *C 59.170 11.900 +*N chany_top_in[0]:28 *C 59.385 11.900 +*N chany_top_in[0]:29 *C 59.340 11.945 +*N chany_top_in[0]:30 *C 59.340 21.760 +*N chany_top_in[0]:31 *C 58.880 21.760 +*N chany_top_in[0]:32 *C 55.375 22.440 +*N chany_top_in[0]:33 *C 55.375 22.440 +*N chany_top_in[0]:34 *C 55.383 22.440 +*N chany_top_in[0]:35 *C 58.873 22.440 +*N chany_top_in[0]:36 *C 58.880 22.440 +*N chany_top_in[0]:37 *C 58.880 42.840 +*N chany_top_in[0]:38 *C 57.253 42.840 +*N chany_top_in[0]:39 *C 58.375 42.840 +*N chany_top_in[0]:40 *C 58.420 42.840 +*N chany_top_in[0]:41 *C 58.420 55.375 +*N chany_top_in[0]:42 *C 58.420 55.450 +*N chany_top_in[0]:43 *C 58.420 56.440 +*N chany_top_in[0]:44 *C 14.933 59.160 +*N chany_top_in[0]:45 *C 20.655 59.160 +*N chany_top_in[0]:46 *C 20.700 59.115 +*N chany_top_in[0]:47 *C 19.648 55.080 +*N chany_top_in[0]:48 *C 20.655 55.080 +*N chany_top_in[0]:49 *C 20.700 55.125 +*N chany_top_in[0]:50 *C 20.700 56.440 +*N chany_top_in[0]:51 *C 20.745 56.440 +*N chany_top_in[0]:52 *C 54.280 56.440 +*N chany_top_in[0]:53 *C 54.280 56.485 +*N chany_top_in[0]:54 *C 54.280 71.355 +*N chany_top_in[0]:55 *C 54.325 71.400 +*N chany_top_in[0]:56 *C 57.638 71.400 +*N chany_top_in[0]:57 *C 57.960 71.400 +*N chany_top_in[0]:58 *C 57.990 71.430 +*N chany_top_in[0]:59 *C 58.005 71.740 +*N chany_top_in[0]:60 *C 58.420 71.740 +*N chany_top_in[0]:61 *C 58.135 77.180 +*N chany_top_in[0]:62 *C 58.420 77.180 +*N chany_top_in[0]:63 *C 58.420 77.180 +*N chany_top_in[0]:64 *C 58.710 91.460 +*N chany_top_in[0]:65 *C 58.420 91.460 +*N chany_top_in[0]:66 *C 58.420 91.460 +*N chany_top_in[0]:67 *C 58.420 91.062 +*N chany_top_in[0]:68 *C 58.413 91.120 +*N chany_top_in[0]:69 *C 55.220 91.120 +*N chany_top_in[0]:70 *C 55.200 91.127 +*N chany_top_in[0]:71 *C 55.200 101.993 +*N chany_top_in[0]:72 *C 55.185 102.000 +*N chany_top_in[0]:73 *C 54.742 102.000 +*N chany_top_in[0]:74 *C 54.740 102.058 + +*CAP +0 chany_top_in[0] 0.0003938578 +1 mux_right_ipin_1\/mux_l1_in_0_:A0 1e-06 +2 mux_right_ipin_7\/mux_l1_in_0_:A0 1e-06 +3 mux_right_ipin_15\/mux_l1_in_0_:A0 1e-06 +4 mux_right_ipin_11\/mux_l1_in_0_:A0 1e-06 +5 mux_right_ipin_3\/mux_l1_in_0_:A0 1e-06 +6 mux_left_ipin_0\/mux_l1_in_0_:A0 1e-06 +7 mux_right_ipin_9\/mux_l1_in_0_:A0 1e-06 +8 mux_right_ipin_13\/mux_l1_in_0_:A0 1e-06 +9 ropt_mt_inst_757:A 1e-06 +10 mux_right_ipin_5\/mux_l1_in_0_:A0 1e-06 +11 chany_top_in[0]:11 7.736256e-05 +12 chany_top_in[0]:12 5.078361e-05 +13 chany_top_in[0]:13 5.078361e-05 +14 chany_top_in[0]:14 0.000501706 +15 chany_top_in[0]:15 0.000501706 +16 chany_top_in[0]:16 0.0006064803 +17 chany_top_in[0]:17 0.0006064803 +18 chany_top_in[0]:18 0.000138953 +19 chany_top_in[0]:19 0.000138953 +20 chany_top_in[0]:20 8.853795e-05 +21 chany_top_in[0]:21 0.0001152591 +22 chany_top_in[0]:22 0.0002371766 +23 chany_top_in[0]:23 0.0002104555 +24 chany_top_in[0]:24 0.0003167762 +25 chany_top_in[0]:25 0.0003167762 +26 chany_top_in[0]:26 0.0001105004 +27 chany_top_in[0]:27 4.648289e-05 +28 chany_top_in[0]:28 0.0001288197 +29 chany_top_in[0]:29 0.0004482747 +30 chany_top_in[0]:30 0.0004792412 +31 chany_top_in[0]:31 7.518497e-05 +32 chany_top_in[0]:32 3.256783e-05 +33 chany_top_in[0]:33 3.375507e-05 +34 chany_top_in[0]:34 0.0002927474 +35 chany_top_in[0]:35 0.0002927474 +36 chany_top_in[0]:36 0.0008881764 +37 chany_top_in[0]:37 0.0008446872 +38 chany_top_in[0]:38 0.0001230487 +39 chany_top_in[0]:39 0.0001230487 +40 chany_top_in[0]:40 0.0005109212 +41 chany_top_in[0]:41 0.0004765691 +42 chany_top_in[0]:42 0.0001397357 +43 chany_top_in[0]:43 0.0003154806 +44 chany_top_in[0]:44 0.0002636115 +45 chany_top_in[0]:45 0.0002636115 +46 chany_top_in[0]:46 0.0001460329 +47 chany_top_in[0]:47 6.579573e-05 +48 chany_top_in[0]:48 6.579573e-05 +49 chany_top_in[0]:49 8.270517e-05 +50 chany_top_in[0]:50 0.0002639435 +51 chany_top_in[0]:51 0.002081272 +52 chany_top_in[0]:52 0.002367411 +53 chany_top_in[0]:53 0.0007894742 +54 chany_top_in[0]:54 0.0007894742 +55 chany_top_in[0]:55 0.000244355 +56 chany_top_in[0]:56 0.0002650825 +57 chany_top_in[0]:57 5.57683e-05 +58 chany_top_in[0]:58 2.330021e-05 +59 chany_top_in[0]:59 5.143596e-05 +60 chany_top_in[0]:60 0.0002736067 +61 chany_top_in[0]:61 5.577112e-05 +62 chany_top_in[0]:62 5.290888e-05 +63 chany_top_in[0]:63 0.0007733192 +64 chany_top_in[0]:64 4.346903e-05 +65 chany_top_in[0]:65 4.754866e-05 +66 chany_top_in[0]:66 4.533382e-05 +67 chany_top_in[0]:67 0.0005136862 +68 chany_top_in[0]:68 0.000353273 +69 chany_top_in[0]:69 0.000353273 +70 chany_top_in[0]:70 0.0007240016 +71 chany_top_in[0]:71 0.0007240016 +72 chany_top_in[0]:72 8.549364e-05 +73 chany_top_in[0]:73 8.549364e-05 +74 chany_top_in[0]:74 0.0003938578 +75 chany_top_in[0]:42 chany_bottom_in[0]:28 6.433571e-06 +76 chany_top_in[0]:41 chany_bottom_in[0]:29 5.78238e-06 +77 chany_top_in[0]:41 chany_bottom_in[0]:39 0.0001580365 +78 chany_top_in[0]:50 chany_bottom_in[0]:35 1.460624e-07 +79 chany_top_in[0]:55 chany_bottom_in[0]:25 1.925506e-06 +80 chany_top_in[0]:54 chany_bottom_in[0]:26 2.263207e-06 +81 chany_top_in[0]:52 chany_bottom_in[0]:27 3.161418e-05 +82 chany_top_in[0]:53 chany_bottom_in[0]:29 2.263207e-06 +83 chany_top_in[0]:57 chany_bottom_in[0]:24 1.335052e-06 +84 chany_top_in[0]:58 chany_bottom_in[0]:29 1.388917e-05 +85 chany_top_in[0]:62 chany_bottom_in[0]:20 5.15751e-06 +86 chany_top_in[0]:63 chany_bottom_in[0]:17 1.33601e-05 +87 chany_top_in[0]:63 chany_bottom_in[0]:18 0.000347573 +88 chany_top_in[0]:63 chany_bottom_in[0]:23 5.456297e-05 +89 chany_top_in[0]:63 chany_bottom_in[0]:26 1.163435e-05 +90 chany_top_in[0]:61 chany_bottom_in[0]:21 5.15751e-06 +91 chany_top_in[0]:56 chany_bottom_in[0]:24 1.925506e-06 +92 chany_top_in[0]:56 chany_bottom_in[0]:25 1.335052e-06 +93 chany_top_in[0]:45 chany_bottom_in[0]:33 4.790003e-06 +94 chany_top_in[0]:46 chany_bottom_in[0]:34 1.460624e-07 +95 chany_top_in[0]:44 chany_bottom_in[0]:32 4.790003e-06 +96 chany_top_in[0]:36 chany_bottom_in[0]:42 2.359442e-06 +97 chany_top_in[0]:36 chany_bottom_in[0]:43 7.741567e-05 +98 chany_top_in[0]:35 chany_bottom_in[0]:43 5.174831e-06 +99 chany_top_in[0]:34 chany_bottom_in[0]:47 5.174831e-06 +100 chany_top_in[0]:66 chany_bottom_in[0]:14 8.143297e-06 +101 chany_top_in[0]:11 chany_bottom_in[0]:27 6.433571e-06 +102 chany_top_in[0]:40 chany_bottom_in[0]:39 5.78238e-06 +103 chany_top_in[0]:40 chany_bottom_in[0]:42 0.0001580365 +104 chany_top_in[0]:67 chany_bottom_in[0]:14 1.33601e-05 +105 chany_top_in[0]:67 chany_bottom_in[0]:17 0.0003557163 +106 chany_top_in[0]:67 chany_bottom_in[0]:19 2.92297e-06 +107 chany_top_in[0]:67 chany_bottom_in[0]:23 2.228778e-06 +108 chany_top_in[0]:43 chany_bottom_in[0]:28 3.161418e-05 +109 chany_top_in[0]:59 chany_bottom_in[0]:26 1.388917e-05 +110 chany_top_in[0]:60 chany_bottom_in[0]:26 5.164e-05 +111 chany_top_in[0]:60 chany_bottom_in[0]:29 9.405568e-06 +112 chany_top_in[0]:37 chany_bottom_in[0]:39 2.359442e-06 +113 chany_top_in[0]:37 chany_bottom_in[0]:42 7.741567e-05 +114 chany_top_in[0]:41 chany_bottom_in[16]:43 4.808248e-05 +115 chany_top_in[0]:51 chany_bottom_in[16]:33 3.586354e-07 +116 chany_top_in[0]:50 chany_bottom_in[16]:30 2.575582e-07 +117 chany_top_in[0]:50 chany_bottom_in[16]:31 5.303367e-06 +118 chany_top_in[0]:54 chany_bottom_in[16]:39 3.045263e-07 +119 chany_top_in[0]:52 chany_bottom_in[16]:34 3.586354e-07 +120 chany_top_in[0]:53 chany_bottom_in[16]:40 3.045263e-07 +121 chany_top_in[0]:29 chany_bottom_in[16]:44 0.000129886 +122 chany_top_in[0]:46 chany_bottom_in[16]:30 5.303367e-06 +123 chany_top_in[0]:36 chany_bottom_in[16]:43 9.272501e-07 +124 chany_top_in[0]:36 chany_bottom_in[16]:44 0.0001675494 +125 chany_top_in[0]:49 chany_bottom_in[16]:31 2.575582e-07 +126 chany_top_in[0]:25 chany_bottom_in[16]:43 8.215302e-05 +127 chany_top_in[0]:25 chany_bottom_in[16]:45 1.170477e-06 +128 chany_top_in[0]:24 chany_bottom_in[16] 1.170477e-06 +129 chany_top_in[0]:24 chany_bottom_in[16]:44 8.215302e-05 +130 chany_top_in[0]:40 chany_bottom_in[16]:44 4.808248e-05 +131 chany_top_in[0]:37 chany_bottom_in[16]:43 0.0001675494 +132 chany_top_in[0]:31 chany_bottom_in[16]:44 9.272501e-07 +133 chany_top_in[0]:30 chany_bottom_in[16]:43 0.000129886 +134 chany_top_in[0]:51 mux_tree_tapbuf_size8_6_sram[3]:3 0.0002054799 +135 chany_top_in[0]:52 mux_tree_tapbuf_size8_6_sram[3]:4 0.0002054799 +136 chany_top_in[0]:51 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.443702e-06 +137 chany_top_in[0]:54 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.429375e-05 +138 chany_top_in[0]:52 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.696673e-06 +139 chany_top_in[0]:52 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.443702e-06 +140 chany_top_in[0]:53 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.429375e-05 +141 chany_top_in[0]:43 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.696673e-06 +142 chany_top_in[0]:51 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.490533e-06 +143 chany_top_in[0]:52 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.490533e-06 +144 chany_top_in[0]:48 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.003059e-05 +145 chany_top_in[0]:47 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.003059e-05 +146 chany_top_in[0]:50 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.034992e-06 +147 chany_top_in[0]:50 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.589827e-05 +148 chany_top_in[0]:45 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001945256 +149 chany_top_in[0]:46 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.589827e-05 +150 chany_top_in[0]:44 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001945256 +151 chany_top_in[0]:49 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.034992e-06 +152 chany_top_in[0]:17 ropt_net_161:7 0.0001473138 +153 chany_top_in[0]:16 ropt_net_161:6 0.0001473138 + +*RES +0 chany_top_in[0] chany_top_in[0]:74 0.004868304 +1 chany_top_in[0]:42 chany_top_in[0]:41 0.0045 +2 chany_top_in[0]:42 chany_top_in[0]:11 0.0009397322 +3 chany_top_in[0]:41 chany_top_in[0]:40 0.01119197 +4 chany_top_in[0]:51 chany_top_in[0]:50 0.0045 +5 chany_top_in[0]:50 chany_top_in[0]:49 0.001174107 +6 chany_top_in[0]:50 chany_top_in[0]:46 0.002388393 +7 chany_top_in[0]:55 chany_top_in[0]:54 0.0045 +8 chany_top_in[0]:54 chany_top_in[0]:53 0.01327679 +9 chany_top_in[0]:52 chany_top_in[0]:51 0.02994197 +10 chany_top_in[0]:52 chany_top_in[0]:43 0.003696429 +11 chany_top_in[0]:53 chany_top_in[0]:52 0.0045 +12 chany_top_in[0]:57 chany_top_in[0]:56 0.0001752718 +13 chany_top_in[0]:58 chany_top_in[0]:57 0.0045 +14 chany_top_in[0]:28 chany_top_in[0]:27 0.0001168478 +15 chany_top_in[0]:28 chany_top_in[0]:26 0.0015625 +16 chany_top_in[0]:29 chany_top_in[0]:28 0.0045 +17 chany_top_in[0]:62 chany_top_in[0]:61 0.0001548913 +18 chany_top_in[0]:63 chany_top_in[0]:62 0.0045 +19 chany_top_in[0]:63 chany_top_in[0]:60 0.004857143 +20 chany_top_in[0]:61 mux_right_ipin_7\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[0]:56 mux_right_ipin_15\/mux_l1_in_0_:A0 0.152 +22 chany_top_in[0]:56 chany_top_in[0]:55 0.002957589 +23 chany_top_in[0]:45 chany_top_in[0]:44 0.005109375 +24 chany_top_in[0]:46 chany_top_in[0]:45 0.0045 +25 chany_top_in[0]:44 mux_right_ipin_3\/mux_l1_in_0_:A0 0.152 +26 chany_top_in[0]:36 chany_top_in[0]:35 0.00341 +27 chany_top_in[0]:36 chany_top_in[0]:31 0.0006071429 +28 chany_top_in[0]:35 chany_top_in[0]:34 0.0005467667 +29 chany_top_in[0]:33 chany_top_in[0]:32 0.0045 +30 chany_top_in[0]:34 chany_top_in[0]:33 0.00341 +31 chany_top_in[0]:32 mux_right_ipin_9\/mux_l1_in_0_:A0 0.152 +32 chany_top_in[0]:65 chany_top_in[0]:64 0.0001576087 +33 chany_top_in[0]:66 chany_top_in[0]:65 0.0045 +34 chany_top_in[0]:64 mux_right_ipin_1\/mux_l1_in_0_:A0 0.152 +35 chany_top_in[0]:48 chany_top_in[0]:47 0.0008995536 +36 chany_top_in[0]:49 chany_top_in[0]:48 0.0045 +37 chany_top_in[0]:47 mux_right_ipin_11\/mux_l1_in_0_:A0 0.152 +38 chany_top_in[0]:26 chany_top_in[0]:25 0.0045 +39 chany_top_in[0]:25 chany_top_in[0]:24 0.006598215 +40 chany_top_in[0]:23 chany_top_in[0]:22 0.001982143 +41 chany_top_in[0]:24 chany_top_in[0]:23 0.0045 +42 chany_top_in[0]:20 chany_top_in[0]:19 0.0045 +43 chany_top_in[0]:19 chany_top_in[0]:18 0.002044643 +44 chany_top_in[0]:17 chany_top_in[0]:16 0.01059821 +45 chany_top_in[0]:18 chany_top_in[0]:17 0.0045 +46 chany_top_in[0]:16 chany_top_in[0]:15 0.0045 +47 chany_top_in[0]:15 chany_top_in[0]:14 0.006901786 +48 chany_top_in[0]:13 chany_top_in[0]:12 0.0003370536 +49 chany_top_in[0]:14 chany_top_in[0]:13 0.0045 +50 chany_top_in[0]:12 ropt_mt_inst_757:A 0.152 +51 chany_top_in[0]:27 mux_right_ipin_13\/mux_l1_in_0_:A0 0.152 +52 chany_top_in[0]:11 mux_right_ipin_5\/mux_l1_in_0_:A0 0.152 +53 chany_top_in[0]:39 chany_top_in[0]:38 0.001002232 +54 chany_top_in[0]:40 chany_top_in[0]:39 0.0045 +55 chany_top_in[0]:40 chany_top_in[0]:37 0.0004107143 +56 chany_top_in[0]:38 mux_left_ipin_0\/mux_l1_in_0_:A0 0.152 +57 chany_top_in[0]:67 chany_top_in[0]:66 0.0001911058 +58 chany_top_in[0]:67 chany_top_in[0]:63 0.01239509 +59 chany_top_in[0]:68 chany_top_in[0]:67 0.00341 +60 chany_top_in[0]:69 chany_top_in[0]:68 0.0005001583 +61 chany_top_in[0]:70 chany_top_in[0]:69 0.00341 +62 chany_top_in[0]:72 chany_top_in[0]:71 0.00341 +63 chany_top_in[0]:71 chany_top_in[0]:70 0.001702183 +64 chany_top_in[0]:74 chany_top_in[0]:73 0.00341 +65 chany_top_in[0]:73 chany_top_in[0]:72 6.499219e-05 +66 chany_top_in[0]:43 chany_top_in[0]:42 0.0008839286 +67 chany_top_in[0]:22 chany_top_in[0]:21 0.0002297297 +68 chany_top_in[0]:21 chany_top_in[0]:20 0.00078125 +69 chany_top_in[0]:59 chany_top_in[0]:58 0.00019375 +70 chany_top_in[0]:60 chany_top_in[0]:59 0.0003705357 +71 chany_top_in[0]:37 chany_top_in[0]:36 0.01821429 +72 chany_top_in[0]:31 chany_top_in[0]:30 0.0004107143 +73 chany_top_in[0]:30 chany_top_in[0]:29 0.008763393 + +*END + +*D_NET chany_top_in[1] 0.01826146 //LENGTH 135.865 LUMPCC 0.004898368 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 31.280 107.510 +*I mux_right_ipin_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 30.075 77.180 +*I mux_right_ipin_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 29.615 75.480 +*I mux_right_ipin_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 31.915 42.500 +*I mux_right_ipin_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 30.190 37.400 +*I mux_right_ipin_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 31.570 33.320 +*I mux_right_ipin_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 28.850 11.560 +*I FTB_22__21:A I *L 0.001767 *C 20.700 6.800 +*I mux_right_ipin_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 26.050 82.280 +*I mux_right_ipin_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 24.690 93.500 +*N chany_top_in[1]:10 *C 24.728 93.500 +*N chany_top_in[1]:11 *C 26.050 82.280 +*N chany_top_in[1]:12 *C 26.220 82.280 +*N chany_top_in[1]:13 *C 20.738 6.800 +*N chany_top_in[1]:14 *C 21.160 6.800 +*N chany_top_in[1]:15 *C 21.160 6.460 +*N chany_top_in[1]:16 *C 24.795 6.460 +*N chany_top_in[1]:17 *C 24.840 6.505 +*N chany_top_in[1]:18 *C 24.840 10.155 +*N chany_top_in[1]:19 *C 24.885 10.200 +*N chany_top_in[1]:20 *C 28.850 11.560 +*N chany_top_in[1]:21 *C 28.980 11.515 +*N chany_top_in[1]:22 *C 28.980 10.245 +*N chany_top_in[1]:23 *C 28.980 10.200 +*N chany_top_in[1]:24 *C 30.315 10.200 +*N chany_top_in[1]:25 *C 30.360 10.200 +*N chany_top_in[1]:26 *C 30.820 10.200 +*N chany_top_in[1]:27 *C 31.533 33.320 +*N chany_top_in[1]:28 *C 30.865 33.320 +*N chany_top_in[1]:29 *C 30.820 33.320 +*N chany_top_in[1]:30 *C 30.820 37.060 +*N chany_top_in[1]:31 *C 30.405 37.060 +*N chany_top_in[1]:32 *C 30.190 37.400 +*N chany_top_in[1]:33 *C 30.360 37.400 +*N chany_top_in[1]:34 *C 30.360 37.415 +*N chany_top_in[1]:35 *C 31.878 42.500 +*N chany_top_in[1]:36 *C 30.405 42.500 +*N chany_top_in[1]:37 *C 30.360 42.500 +*N chany_top_in[1]:38 *C 29.578 75.480 +*N chany_top_in[1]:39 *C 28.565 75.480 +*N chany_top_in[1]:40 *C 28.520 75.480 +*N chany_top_in[1]:41 *C 28.527 75.480 +*N chany_top_in[1]:42 *C 30.353 75.480 +*N chany_top_in[1]:43 *C 30.360 75.480 +*N chany_top_in[1]:44 *C 30.075 77.180 +*N chany_top_in[1]:45 *C 30.360 77.180 +*N chany_top_in[1]:46 *C 30.360 77.180 +*N chany_top_in[1]:47 *C 30.360 82.223 +*N chany_top_in[1]:48 *C 30.353 82.280 +*N chany_top_in[1]:49 *C 26.228 82.280 +*N chany_top_in[1]:50 *C 26.220 82.280 +*N chany_top_in[1]:51 *C 26.220 93.455 +*N chany_top_in[1]:52 *C 26.220 93.530 +*N chany_top_in[1]:53 *C 26.220 93.840 +*N chany_top_in[1]:54 *C 30.775 93.840 +*N chany_top_in[1]:55 *C 30.820 93.885 +*N chany_top_in[1]:56 *C 30.820 97.240 +*N chany_top_in[1]:57 *C 31.280 97.240 + +*CAP +0 chany_top_in[1] 0.0005579997 +1 mux_right_ipin_0\/mux_l1_in_0_:A0 1e-06 +2 mux_right_ipin_6\/mux_l1_in_0_:A0 1e-06 +3 mux_right_ipin_14\/mux_l1_in_0_:A0 1e-06 +4 mux_right_ipin_8\/mux_l1_in_0_:A0 1e-06 +5 mux_right_ipin_10\/mux_l1_in_0_:A0 1e-06 +6 mux_right_ipin_12\/mux_l1_in_0_:A0 1e-06 +7 FTB_22__21:A 1e-06 +8 mux_right_ipin_4\/mux_l1_in_0_:A0 1e-06 +9 mux_right_ipin_2\/mux_l1_in_0_:A0 1e-06 +10 chany_top_in[1]:10 0.0001325927 +11 chany_top_in[1]:11 6.085111e-05 +12 chany_top_in[1]:12 6.325656e-05 +13 chany_top_in[1]:13 2.859427e-05 +14 chany_top_in[1]:14 5.189215e-05 +15 chany_top_in[1]:15 0.0002120436 +16 chany_top_in[1]:16 0.0001887457 +17 chany_top_in[1]:17 0.000149788 +18 chany_top_in[1]:18 0.000149788 +19 chany_top_in[1]:19 0.0003088274 +20 chany_top_in[1]:20 2.985702e-05 +21 chany_top_in[1]:21 9.476851e-05 +22 chany_top_in[1]:22 9.476851e-05 +23 chany_top_in[1]:23 0.0004411772 +24 chany_top_in[1]:24 9.853721e-05 +25 chany_top_in[1]:25 6.541036e-05 +26 chany_top_in[1]:26 0.0007517923 +27 chany_top_in[1]:27 7.008777e-05 +28 chany_top_in[1]:28 7.008777e-05 +29 chany_top_in[1]:29 0.0009518166 +30 chany_top_in[1]:30 0.0002232993 +31 chany_top_in[1]:31 4.513189e-05 +32 chany_top_in[1]:32 5.520046e-05 +33 chany_top_in[1]:33 5.782691e-05 +34 chany_top_in[1]:34 0.0002276704 +35 chany_top_in[1]:35 0.0001436434 +36 chany_top_in[1]:36 0.0001436434 +37 chany_top_in[1]:37 0.001465864 +38 chany_top_in[1]:38 9.181577e-05 +39 chany_top_in[1]:39 9.181577e-05 +40 chany_top_in[1]:40 3.705775e-05 +41 chany_top_in[1]:41 0.0001737336 +42 chany_top_in[1]:42 0.0001737336 +43 chany_top_in[1]:43 0.001327663 +44 chany_top_in[1]:44 5.140996e-05 +45 chany_top_in[1]:45 5.292073e-05 +46 chany_top_in[1]:46 0.0002830474 +47 chany_top_in[1]:47 0.0001885893 +48 chany_top_in[1]:48 0.0003601462 +49 chany_top_in[1]:49 0.0003601462 +50 chany_top_in[1]:50 0.0006256774 +51 chany_top_in[1]:51 0.0005891495 +52 chany_top_in[1]:52 0.000162429 +53 chany_top_in[1]:53 0.0003775493 +54 chany_top_in[1]:54 0.000347713 +55 chany_top_in[1]:55 0.0002478863 +56 chany_top_in[1]:56 0.0002832676 +57 chany_top_in[1]:57 0.0005933811 +58 chany_top_in[1]:21 chany_bottom_in[1]:64 1.277034e-07 +59 chany_top_in[1]:22 chany_bottom_in[1] 1.277034e-07 +60 chany_top_in[1]:51 chany_bottom_in[1]:30 9.364564e-06 +61 chany_top_in[1]:51 chany_bottom_in[1]:34 6.553093e-06 +62 chany_top_in[1]:51 chany_bottom_in[1]:36 1.602123e-05 +63 chany_top_in[1]:50 chany_bottom_in[1]:31 9.364564e-06 +64 chany_top_in[1]:50 chany_bottom_in[1]:33 6.553093e-06 +65 chany_top_in[1]:50 chany_bottom_in[1]:37 1.602123e-05 +66 chany_top_in[1]:47 chany_bottom_in[1]:40 0.0001208847 +67 chany_top_in[1]:47 chany_bottom_in[1]:43 1.788625e-05 +68 chany_top_in[1]:43 chany_bottom_in[1]:43 3.036824e-05 +69 chany_top_in[1]:43 chany_bottom_in[1]:44 4.432972e-05 +70 chany_top_in[1]:43 chany_bottom_in[1]:48 0.0001237628 +71 chany_top_in[1]:39 chany_bottom_in[1]:45 1.624321e-07 +72 chany_top_in[1]:38 chany_bottom_in[1]:46 1.624321e-07 +73 chany_top_in[1]:12 chany_bottom_in[1]:35 8.235107e-07 +74 chany_top_in[1]:11 chany_bottom_in[1]:34 8.235107e-07 +75 chany_top_in[1]:36 chany_bottom_in[1]:51 1.826647e-06 +76 chany_top_in[1]:37 chany_bottom_in[1]:44 3.036824e-05 +77 chany_top_in[1]:37 chany_bottom_in[1]:48 1.373273e-05 +78 chany_top_in[1]:37 chany_bottom_in[1]:49 0.0001237628 +79 chany_top_in[1]:37 chany_bottom_in[1]:53 4.156356e-06 +80 chany_top_in[1]:35 chany_bottom_in[1]:50 1.826647e-06 +81 chany_top_in[1]:34 chany_bottom_in[1]:49 1.373273e-05 +82 chany_top_in[1]:34 chany_bottom_in[1]:53 4.254474e-07 +83 chany_top_in[1]:34 chany_bottom_in[1]:56 4.156356e-06 +84 chany_top_in[1]:45 chany_bottom_in[1]:41 3.775216e-06 +85 chany_top_in[1]:46 chany_bottom_in[1]:43 0.0001652144 +86 chany_top_in[1]:46 chany_bottom_in[1]:44 1.788625e-05 +87 chany_top_in[1]:44 chany_bottom_in[1]:42 3.775216e-06 +88 chany_top_in[1]:29 chany_bottom_in[1]:12 2.215263e-08 +89 chany_top_in[1]:29 chany_bottom_in[1]:56 3.016487e-06 +90 chany_top_in[1]:29 chany_bottom_in[1]:57 6.9716e-06 +91 chany_top_in[1]:29 chany_bottom_in[1]:59 1.703628e-05 +92 chany_top_in[1]:29 chany_bottom_in[1]:60 0.0005320096 +93 chany_top_in[1]:29 chany_bottom_in[1]:64 7.453957e-06 +94 chany_top_in[1]:26 chany_bottom_in[1] 7.453957e-06 +95 chany_top_in[1]:26 chany_bottom_in[1]:11 2.215263e-08 +96 chany_top_in[1]:26 chany_bottom_in[1]:57 1.818079e-06 +97 chany_top_in[1]:26 chany_bottom_in[1]:60 1.703628e-05 +98 chany_top_in[1]:26 chany_bottom_in[1]:61 0.0005024466 +99 chany_top_in[1]:31 chany_bottom_in[1]:54 6.612425e-06 +100 chany_top_in[1]:31 chany_bottom_in[1]:56 4.254474e-07 +101 chany_top_in[1]:30 chany_bottom_in[1]:53 1.198408e-06 +102 chany_top_in[1]:30 chany_bottom_in[1]:55 6.612425e-06 +103 chany_top_in[1]:30 chany_bottom_in[1]:56 6.9716e-06 +104 chany_top_in[1]:30 chany_bottom_in[1]:59 2.956296e-05 +105 chany_top_in[1]:21 chany_bottom_in[17]:21 1.288309e-05 +106 chany_top_in[1]:22 chany_bottom_in[17]:22 1.288309e-05 +107 chany_top_in[1]:47 chany_bottom_in[17]:12 6.696039e-07 +108 chany_top_in[1]:43 chany_bottom_in[17]:12 0.0003718603 +109 chany_top_in[1]:43 chany_bottom_in[17]:13 3.116524e-06 +110 chany_top_in[1]:37 chany_bottom_in[17]:12 2.859012e-05 +111 chany_top_in[1]:37 chany_bottom_in[17]:13 0.0003718603 +112 chany_top_in[1]:37 chany_bottom_in[17]:14 6.824781e-05 +113 chany_top_in[1]:34 chany_bottom_in[17]:13 2.859012e-05 +114 chany_top_in[1]:34 chany_bottom_in[17]:14 1.49047e-05 +115 chany_top_in[1]:34 chany_bottom_in[17]:15 6.824781e-05 +116 chany_top_in[1]:46 chany_bottom_in[17]:12 3.116524e-06 +117 chany_top_in[1]:46 chany_bottom_in[17]:13 6.696039e-07 +118 chany_top_in[1]:29 chany_bottom_in[17]:15 1.412038e-05 +119 chany_top_in[1]:29 chany_bottom_in[17]:16 7.426146e-06 +120 chany_top_in[1]:29 chany_bottom_in[17]:17 5.259828e-06 +121 chany_top_in[1]:29 chany_bottom_in[17]:18 0.000159939 +122 chany_top_in[1]:29 chany_bottom_in[17]:21 7.596664e-05 +123 chany_top_in[1]:26 chany_bottom_in[17]:17 7.426146e-06 +124 chany_top_in[1]:26 chany_bottom_in[17]:21 0.000159939 +125 chany_top_in[1]:26 chany_bottom_in[17]:22 7.596664e-05 +126 chany_top_in[1]:31 chany_bottom_in[17]:15 1.49047e-05 +127 chany_top_in[1]:30 chany_bottom_in[17]:14 1.412038e-05 +128 chany_top_in[1]:30 chany_bottom_in[17]:16 5.259828e-06 +129 chany_top_in[1]:43 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003148739 +130 chany_top_in[1]:37 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003148739 +131 chany_top_in[1]:23 ropt_net_155:3 2.643867e-06 +132 chany_top_in[1]:13 ropt_net_155:7 2.529311e-05 +133 chany_top_in[1]:16 ropt_net_155:6 1.61414e-05 +134 chany_top_in[1]:17 ropt_net_155:5 2.063469e-05 +135 chany_top_in[1]:19 ropt_net_155:2 2.643867e-06 +136 chany_top_in[1]:18 ropt_net_155:4 2.063469e-05 +137 chany_top_in[1]:14 ropt_net_155:6 2.529311e-05 +138 chany_top_in[1]:15 ropt_net_155:7 1.61414e-05 +139 chany_top_in[1] ropt_net_167:5 0.0001325682 +140 chany_top_in[1]:57 ropt_net_167:4 0.0001325682 +141 chany_top_in[1]:16 ropt_net_149:3 0.0001127532 +142 chany_top_in[1]:17 ropt_net_149:4 9.3968e-05 +143 chany_top_in[1]:18 ropt_net_149:5 9.3968e-05 +144 chany_top_in[1]:15 ropt_net_149:2 0.0001127532 + +*RES +0 chany_top_in[1] chany_top_in[1]:57 0.009169643 +1 chany_top_in[1]:20 mux_right_ipin_12\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[1]:21 chany_top_in[1]:20 0.0045 +3 chany_top_in[1]:23 chany_top_in[1]:22 0.0045 +4 chany_top_in[1]:23 chany_top_in[1]:19 0.00365625 +5 chany_top_in[1]:22 chany_top_in[1]:21 0.001133929 +6 chany_top_in[1]:52 chany_top_in[1]:51 0.0045 +7 chany_top_in[1]:52 chany_top_in[1]:10 0.001332589 +8 chany_top_in[1]:51 chany_top_in[1]:50 0.009977679 +9 chany_top_in[1]:13 FTB_22__21:A 0.152 +10 chany_top_in[1]:16 chany_top_in[1]:15 0.003245536 +11 chany_top_in[1]:17 chany_top_in[1]:16 0.0045 +12 chany_top_in[1]:19 chany_top_in[1]:18 0.0045 +13 chany_top_in[1]:18 chany_top_in[1]:17 0.003258929 +14 chany_top_in[1]:50 chany_top_in[1]:49 0.00341 +15 chany_top_in[1]:50 chany_top_in[1]:12 0.0045 +16 chany_top_in[1]:49 chany_top_in[1]:48 0.00064625 +17 chany_top_in[1]:47 chany_top_in[1]:46 0.004502232 +18 chany_top_in[1]:48 chany_top_in[1]:47 0.00341 +19 chany_top_in[1]:24 chany_top_in[1]:23 0.001191964 +20 chany_top_in[1]:25 chany_top_in[1]:24 0.0045 +21 chany_top_in[1]:54 chany_top_in[1]:53 0.004066965 +22 chany_top_in[1]:55 chany_top_in[1]:54 0.0045 +23 chany_top_in[1]:43 chany_top_in[1]:42 0.00341 +24 chany_top_in[1]:43 chany_top_in[1]:37 0.02944643 +25 chany_top_in[1]:42 chany_top_in[1]:41 0.0002859166 +26 chany_top_in[1]:40 chany_top_in[1]:39 0.0045 +27 chany_top_in[1]:41 chany_top_in[1]:40 0.00341 +28 chany_top_in[1]:39 chany_top_in[1]:38 0.0009040179 +29 chany_top_in[1]:38 mux_right_ipin_6\/mux_l1_in_0_:A0 0.152 +30 chany_top_in[1]:12 chany_top_in[1]:11 9.239131e-05 +31 chany_top_in[1]:11 mux_right_ipin_4\/mux_l1_in_0_:A0 0.152 +32 chany_top_in[1]:36 chany_top_in[1]:35 0.001314732 +33 chany_top_in[1]:37 chany_top_in[1]:36 0.0045 +34 chany_top_in[1]:37 chany_top_in[1]:34 0.004540179 +35 chany_top_in[1]:35 mux_right_ipin_14\/mux_l1_in_0_:A0 0.152 +36 chany_top_in[1]:10 mux_right_ipin_2\/mux_l1_in_0_:A0 0.152 +37 chany_top_in[1]:33 chany_top_in[1]:32 9.239131e-05 +38 chany_top_in[1]:34 chany_top_in[1]:33 0.0045 +39 chany_top_in[1]:34 chany_top_in[1]:31 0.000221875 +40 chany_top_in[1]:32 mux_right_ipin_8\/mux_l1_in_0_:A0 0.152 +41 chany_top_in[1]:45 chany_top_in[1]:44 0.0001548913 +42 chany_top_in[1]:46 chany_top_in[1]:45 0.0045 +43 chany_top_in[1]:46 chany_top_in[1]:43 0.001517857 +44 chany_top_in[1]:44 mux_right_ipin_0\/mux_l1_in_0_:A0 0.152 +45 chany_top_in[1]:28 chany_top_in[1]:27 0.0005959821 +46 chany_top_in[1]:29 chany_top_in[1]:28 0.0045 +47 chany_top_in[1]:29 chany_top_in[1]:26 0.02064286 +48 chany_top_in[1]:27 mux_right_ipin_10\/mux_l1_in_0_:A0 0.152 +49 chany_top_in[1]:14 chany_top_in[1]:13 0.0003772322 +50 chany_top_in[1]:15 chany_top_in[1]:14 0.0003035715 +51 chany_top_in[1]:53 chany_top_in[1]:52 0.0002767858 +52 chany_top_in[1]:26 chany_top_in[1]:25 0.0004107143 +53 chany_top_in[1]:31 chany_top_in[1]:30 0.0003705357 +54 chany_top_in[1]:30 chany_top_in[1]:29 0.003339286 +55 chany_top_in[1]:56 chany_top_in[1]:55 0.002995536 +56 chany_top_in[1]:57 chany_top_in[1]:56 0.0004107143 + +*END + +*D_NET chany_top_in[3] 0.02434399 //LENGTH 183.640 LUMPCC 0.004963623 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 40.480 107.510 +*I mux_right_ipin_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 18.860 88.740 +*I mux_right_ipin_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 22.830 86.360 +*I mux_right_ipin_14\/mux_l2_in_1_:A1 I *L 0.00198 *C 33.220 47.260 +*I mux_right_ipin_10\/mux_l2_in_1_:A1 I *L 0.00198 *C 16.465 34.340 +*I mux_right_ipin_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 32.030 38.760 +*I mux_right_ipin_12\/mux_l1_in_1_:A0 I *L 0.001631 *C 36.170 15.300 +*I ropt_mt_inst_750:A I *L 0.001767 *C 49.220 6.800 +*I mux_right_ipin_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 31.185 63.580 +*I mux_right_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 28.235 80.580 +*N chany_top_in[3]:10 *C 28.110 80.580 +*N chany_top_in[3]:11 *C 31.223 63.580 +*N chany_top_in[3]:12 *C 49.183 6.800 +*N chany_top_in[3]:13 *C 46.460 6.800 +*N chany_top_in[3]:14 *C 46.425 6.460 +*N chany_top_in[3]:15 *C 35.925 6.460 +*N chany_top_in[3]:16 *C 35.880 6.505 +*N chany_top_in[3]:17 *C 35.880 8.160 +*N chany_top_in[3]:18 *C 34.960 8.160 +*N chany_top_in[3]:19 *C 36.133 15.300 +*N chany_top_in[3]:20 *C 35.005 15.300 +*N chany_top_in[3]:21 *C 34.960 15.300 +*N chany_top_in[3]:22 *C 34.960 38.715 +*N chany_top_in[3]:23 *C 34.915 38.760 +*N chany_top_in[3]:24 *C 32.068 38.760 +*N chany_top_in[3]:25 *C 32.660 38.760 +*N chany_top_in[3]:26 *C 32.660 38.805 +*N chany_top_in[3]:27 *C 16.503 34.340 +*N chany_top_in[3]:28 *C 18.355 34.340 +*N chany_top_in[3]:29 *C 18.400 34.385 +*N chany_top_in[3]:30 *C 18.400 40.742 +*N chany_top_in[3]:31 *C 18.408 40.800 +*N chany_top_in[3]:32 *C 32.653 40.800 +*N chany_top_in[3]:33 *C 32.660 40.800 +*N chany_top_in[3]:34 *C 32.660 46.240 +*N chany_top_in[3]:35 *C 32.200 46.240 +*N chany_top_in[3]:36 *C 33.183 47.260 +*N chany_top_in[3]:37 *C 32.245 47.260 +*N chany_top_in[3]:38 *C 32.200 47.260 +*N chany_top_in[3]:39 *C 32.200 63.580 +*N chany_top_in[3]:40 *C 31.740 63.580 +*N chany_top_in[3]:41 *C 31.740 63.610 +*N chany_top_in[3]:42 *C 31.740 63.920 +*N chany_top_in[3]:43 *C 28.565 63.920 +*N chany_top_in[3]:44 *C 28.520 63.965 +*N chany_top_in[3]:45 *C 28.520 72.420 +*N chany_top_in[3]:46 *C 28.060 72.420 +*N chany_top_in[3]:47 *C 28.060 80.535 +*N chany_top_in[3]:48 *C 28.015 80.580 +*N chany_top_in[3]:49 *C 24.425 80.580 +*N chany_top_in[3]:50 *C 24.380 80.625 +*N chany_top_in[3]:51 *C 22.867 86.360 +*N chany_top_in[3]:52 *C 24.335 86.360 +*N chany_top_in[3]:53 *C 24.380 86.360 +*N chany_top_in[3]:54 *C 18.898 88.740 +*N chany_top_in[3]:55 *C 24.335 88.740 +*N chany_top_in[3]:56 *C 24.380 88.740 +*N chany_top_in[3]:57 *C 24.380 88.343 +*N chany_top_in[3]:58 *C 24.388 88.400 +*N chany_top_in[3]:59 *C 32.180 88.400 +*N chany_top_in[3]:60 *C 32.200 88.407 +*N chany_top_in[3]:61 *C 32.200 100.633 +*N chany_top_in[3]:62 *C 32.220 100.640 +*N chany_top_in[3]:63 *C 40.473 100.640 +*N chany_top_in[3]:64 *C 40.480 100.698 + +*CAP +0 chany_top_in[3] 0.0004593185 +1 mux_right_ipin_2\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_4\/mux_l1_in_1_:A0 1e-06 +3 mux_right_ipin_14\/mux_l2_in_1_:A1 1e-06 +4 mux_right_ipin_10\/mux_l2_in_1_:A1 1e-06 +5 mux_right_ipin_8\/mux_l1_in_1_:A0 1e-06 +6 mux_right_ipin_12\/mux_l1_in_1_:A0 1e-06 +7 ropt_mt_inst_750:A 1e-06 +8 mux_right_ipin_6\/mux_l2_in_1_:A1 1e-06 +9 mux_right_ipin_0\/mux_l1_in_1_:A0 1e-06 +10 chany_top_in[3]:10 2.45563e-05 +11 chany_top_in[3]:11 3.267076e-05 +12 chany_top_in[3]:12 0.0002460738 +13 chany_top_in[3]:13 0.0002767005 +14 chany_top_in[3]:14 0.0008782405 +15 chany_top_in[3]:15 0.0008476137 +16 chany_top_in[3]:16 0.0001262481 +17 chany_top_in[3]:17 0.0001798616 +18 chany_top_in[3]:18 0.0003680765 +19 chany_top_in[3]:19 0.0001354733 +20 chany_top_in[3]:20 0.0001354733 +21 chany_top_in[3]:21 0.001063223 +22 chany_top_in[3]:22 0.0007164149 +23 chany_top_in[3]:23 0.0001428723 +24 chany_top_in[3]:24 4.608912e-05 +25 chany_top_in[3]:25 0.0002215788 +26 chany_top_in[3]:26 7.374354e-05 +27 chany_top_in[3]:27 0.0001387157 +28 chany_top_in[3]:28 0.0001387157 +29 chany_top_in[3]:29 0.0003175575 +30 chany_top_in[3]:30 0.0003175575 +31 chany_top_in[3]:31 0.0009367176 +32 chany_top_in[3]:32 0.0009367176 +33 chany_top_in[3]:33 0.0003499041 +34 chany_top_in[3]:34 0.0002699213 +35 chany_top_in[3]:35 8.30159e-05 +36 chany_top_in[3]:36 0.0001005997 +37 chany_top_in[3]:37 0.0001005997 +38 chany_top_in[3]:38 0.0008090014 +39 chany_top_in[3]:39 0.0007595863 +40 chany_top_in[3]:40 6.885357e-05 +41 chany_top_in[3]:41 6.29578e-05 +42 chany_top_in[3]:42 0.0002357563 +43 chany_top_in[3]:43 0.0002054692 +44 chany_top_in[3]:44 0.0003936702 +45 chany_top_in[3]:45 0.0004251812 +46 chany_top_in[3]:46 0.0004348035 +47 chany_top_in[3]:47 0.0004032925 +48 chany_top_in[3]:48 0.000292748 +49 chany_top_in[3]:49 0.0002681917 +50 chany_top_in[3]:50 0.0002829774 +51 chany_top_in[3]:51 0.0001024612 +52 chany_top_in[3]:52 0.0001024612 +53 chany_top_in[3]:53 0.0004058777 +54 chany_top_in[3]:54 0.0002842648 +55 chany_top_in[3]:55 0.0002842648 +56 chany_top_in[3]:56 4.536932e-05 +57 chany_top_in[3]:57 0.0001060501 +58 chany_top_in[3]:58 0.0005937546 +59 chany_top_in[3]:59 0.0005937546 +60 chany_top_in[3]:60 0.0005853589 +61 chany_top_in[3]:61 0.0005853589 +62 chany_top_in[3]:62 0.0004581649 +63 chany_top_in[3]:63 0.0004581649 +64 chany_top_in[3]:64 0.0004593185 +65 chany_top_in[3]:33 chany_bottom_in[1]:49 1.827235e-05 +66 chany_top_in[3]:33 chany_bottom_in[1]:53 2.813688e-05 +67 chany_top_in[3]:33 chany_bottom_in[1]:56 7.358713e-06 +68 chany_top_in[3]:57 chany_bottom_in[1]:30 4.709091e-05 +69 chany_top_in[3]:57 chany_bottom_in[1]:31 9.710105e-06 +70 chany_top_in[3]:26 chany_bottom_in[1]:56 2.813688e-05 +71 chany_top_in[3]:50 chany_bottom_in[1]:31 9.094783e-05 +72 chany_top_in[3]:53 chany_bottom_in[1]:30 9.094783e-05 +73 chany_top_in[3]:53 chany_bottom_in[1]:31 4.709091e-05 +74 chany_top_in[3]:38 chany_bottom_in[1]:48 1.260691e-05 +75 chany_top_in[3]:38 chany_bottom_in[1]:49 0.0001686348 +76 chany_top_in[3]:56 chany_bottom_in[1]:30 9.710105e-06 +77 chany_top_in[3]:39 chany_bottom_in[1]:48 0.0001686348 +78 chany_top_in[3]:35 chany_bottom_in[1]:49 1.260691e-05 +79 chany_top_in[3]:34 chany_bottom_in[1]:48 1.827235e-05 +80 chany_top_in[3]:34 chany_bottom_in[1]:53 7.358713e-06 +81 chany_top_in[3]:33 chany_bottom_in[3]:42 4.387045e-05 +82 chany_top_in[3]:30 chany_bottom_in[3]:51 2.398279e-05 +83 chany_top_in[3]:29 chany_bottom_in[3]:52 2.398279e-05 +84 chany_top_in[3]:58 chany_bottom_in[3]:20 3.852241e-07 +85 chany_top_in[3]:59 chany_bottom_in[3]:19 3.852241e-07 +86 chany_top_in[3]:21 chany_bottom_in[3]:55 4.867167e-05 +87 chany_top_in[3]:21 chany_bottom_in[3]:57 0.0002646662 +88 chany_top_in[3]:25 chany_bottom_in[3]:46 1.560695e-05 +89 chany_top_in[3]:25 chany_bottom_in[3]:47 3.838295e-06 +90 chany_top_in[3]:52 chany_bottom_in[3]:28 1.687876e-05 +91 chany_top_in[3]:51 chany_bottom_in[3]:27 1.687876e-05 +92 chany_top_in[3]:38 chany_bottom_in[3]:41 1.223276e-06 +93 chany_top_in[3]:38 chany_bottom_in[3]:42 6.750582e-05 +94 chany_top_in[3]:23 chany_bottom_in[3]:47 1.560695e-05 +95 chany_top_in[3]:22 chany_bottom_in[3]:48 4.326098e-05 +96 chany_top_in[3]:22 chany_bottom_in[3]:55 0.0002488395 +97 chany_top_in[3]:24 chany_bottom_in[3]:46 3.838295e-06 +98 chany_top_in[3]:47 chany_bottom_in[3]:29 2.632639e-05 +99 chany_top_in[3]:47 chany_bottom_in[3]:32 6.337246e-05 +100 chany_top_in[3]:44 chany_bottom_in[3]:33 9.430995e-05 +101 chany_top_in[3]:46 chany_bottom_in[3]:31 2.632639e-05 +102 chany_top_in[3]:46 chany_bottom_in[3]:33 6.337246e-05 +103 chany_top_in[3]:45 chany_bottom_in[3]:32 9.430995e-05 +104 chany_top_in[3]:39 chany_bottom_in[3]:41 6.750582e-05 +105 chany_top_in[3]:35 chany_bottom_in[3]:42 1.223276e-06 +106 chany_top_in[3]:34 chany_bottom_in[3]:41 4.387045e-05 +107 chany_top_in[3]:18 chany_bottom_in[3]:57 5.41069e-06 +108 chany_top_in[3]:18 chany_bottom_in[3]:58 1.582671e-05 +109 chany_top_in[3]:28 chany_bottom_in[7]:8 5.66551e-06 +110 chany_top_in[3]:27 chany_bottom_in[7]:7 5.66551e-06 +111 chany_top_in[3]:62 chany_bottom_in[7]:14 0.0004557755 +112 chany_top_in[3]:63 chany_bottom_in[7]:13 0.0004557755 +113 chany_top_in[3]:32 chany_top_in[13]:21 7.229608e-05 +114 chany_top_in[3]:31 chany_top_in[13]:20 7.229608e-05 +115 chany_top_in[3]:60 chany_top_in[13]:22 2.167741e-05 +116 chany_top_in[3]:60 chany_top_in[13]:23 0.0002088524 +117 chany_top_in[3]:61 chany_top_in[13]:24 0.0002088524 +118 chany_top_in[3]:61 chany_top_in[13]:23 2.167741e-05 +119 chany_top_in[3]:33 chany_top_in[17]:23 1.020066e-05 +120 chany_top_in[3]:33 chany_top_in[17]:24 1.462798e-05 +121 chany_top_in[3]:15 chany_top_in[17]:18 1.127807e-05 +122 chany_top_in[3]:21 chany_top_in[17]:20 3.974042e-06 +123 chany_top_in[3]:21 chany_top_in[17]:23 0.0002862391 +124 chany_top_in[3]:26 chany_top_in[17]:23 1.462798e-05 +125 chany_top_in[3]:22 chany_top_in[17]:24 0.0002862391 +126 chany_top_in[3]:14 chany_top_in[17]:17 1.127807e-05 +127 chany_top_in[3]:34 chany_top_in[17]:24 1.020066e-05 +128 chany_top_in[3]:18 chany_top_in[17]:19 3.974042e-06 +129 chany_top_in[3]:55 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002166255 +130 chany_top_in[3]:54 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002166255 +131 chany_top_in[3]:43 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.461764e-05 +132 chany_top_in[3]:44 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.383522e-05 +133 chany_top_in[3]:42 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.461764e-05 +134 chany_top_in[3]:45 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.383522e-05 +135 chany_top_in[3]:21 ropt_net_157:7 3.643488e-06 +136 chany_top_in[3]:21 ropt_net_157:5 5.910708e-05 +137 chany_top_in[3]:18 ropt_net_157:4 5.910708e-05 +138 chany_top_in[3]:18 ropt_net_157:6 3.643488e-06 + +*RES +0 chany_top_in[3] chany_top_in[3]:64 0.00608259 +1 chany_top_in[3]:33 chany_top_in[3]:32 0.00341 +2 chany_top_in[3]:33 chany_top_in[3]:26 0.00178125 +3 chany_top_in[3]:32 chany_top_in[3]:31 0.002231717 +4 chany_top_in[3]:30 chany_top_in[3]:29 0.00567634 +5 chany_top_in[3]:31 chany_top_in[3]:30 0.00341 +6 chany_top_in[3]:28 chany_top_in[3]:27 0.001654018 +7 chany_top_in[3]:29 chany_top_in[3]:28 0.0045 +8 chany_top_in[3]:27 mux_right_ipin_10\/mux_l2_in_1_:A1 0.152 +9 chany_top_in[3]:12 ropt_mt_inst_750:A 0.152 +10 chany_top_in[3]:15 chany_top_in[3]:14 0.009375 +11 chany_top_in[3]:16 chany_top_in[3]:15 0.0045 +12 chany_top_in[3]:57 chany_top_in[3]:56 0.0001911058 +13 chany_top_in[3]:57 chany_top_in[3]:53 0.001770089 +14 chany_top_in[3]:58 chany_top_in[3]:57 0.00341 +15 chany_top_in[3]:59 chany_top_in[3]:58 0.001220825 +16 chany_top_in[3]:60 chany_top_in[3]:59 0.00341 +17 chany_top_in[3]:62 chany_top_in[3]:61 0.00341 +18 chany_top_in[3]:61 chany_top_in[3]:60 0.00191525 +19 chany_top_in[3]:64 chany_top_in[3]:63 0.00341 +20 chany_top_in[3]:63 chany_top_in[3]:62 0.001292892 +21 chany_top_in[3]:41 chany_top_in[3]:40 0.0045 +22 chany_top_in[3]:41 chany_top_in[3]:11 0.0004620536 +23 chany_top_in[3]:40 chany_top_in[3]:39 0.0004107143 +24 chany_top_in[3]:20 chany_top_in[3]:19 0.001006696 +25 chany_top_in[3]:21 chany_top_in[3]:20 0.0045 +26 chany_top_in[3]:21 chany_top_in[3]:18 0.006375 +27 chany_top_in[3]:19 mux_right_ipin_12\/mux_l1_in_1_:A0 0.152 +28 chany_top_in[3]:25 chany_top_in[3]:24 0.0005290179 +29 chany_top_in[3]:25 chany_top_in[3]:23 0.002013393 +30 chany_top_in[3]:26 chany_top_in[3]:25 0.0045 +31 chany_top_in[3]:11 mux_right_ipin_6\/mux_l2_in_1_:A1 0.152 +32 chany_top_in[3]:49 chany_top_in[3]:48 0.003205357 +33 chany_top_in[3]:50 chany_top_in[3]:49 0.0045 +34 chany_top_in[3]:52 chany_top_in[3]:51 0.001310268 +35 chany_top_in[3]:53 chany_top_in[3]:52 0.0045 +36 chany_top_in[3]:53 chany_top_in[3]:50 0.005120536 +37 chany_top_in[3]:51 mux_right_ipin_4\/mux_l1_in_1_:A0 0.152 +38 chany_top_in[3]:37 chany_top_in[3]:36 0.0008370536 +39 chany_top_in[3]:38 chany_top_in[3]:37 0.0045 +40 chany_top_in[3]:38 chany_top_in[3]:35 0.0009107143 +41 chany_top_in[3]:36 mux_right_ipin_14\/mux_l2_in_1_:A1 0.152 +42 chany_top_in[3]:55 chany_top_in[3]:54 0.004854911 +43 chany_top_in[3]:56 chany_top_in[3]:55 0.0045 +44 chany_top_in[3]:54 mux_right_ipin_2\/mux_l2_in_1_:A1 0.152 +45 chany_top_in[3]:23 chany_top_in[3]:22 0.0045 +46 chany_top_in[3]:22 chany_top_in[3]:21 0.02090625 +47 chany_top_in[3]:24 mux_right_ipin_8\/mux_l1_in_1_:A0 0.152 +48 chany_top_in[3]:10 mux_right_ipin_0\/mux_l1_in_1_:A0 0.152 +49 chany_top_in[3]:48 chany_top_in[3]:47 0.0045 +50 chany_top_in[3]:48 chany_top_in[3]:10 8.482142e-05 +51 chany_top_in[3]:47 chany_top_in[3]:46 0.007245536 +52 chany_top_in[3]:43 chany_top_in[3]:42 0.002834821 +53 chany_top_in[3]:44 chany_top_in[3]:43 0.0045 +54 chany_top_in[3]:42 chany_top_in[3]:41 0.0002767857 +55 chany_top_in[3]:14 chany_top_in[3]:13 0.0002297297 +56 chany_top_in[3]:13 chany_top_in[3]:12 0.002430804 +57 chany_top_in[3]:46 chany_top_in[3]:45 0.0004107143 +58 chany_top_in[3]:45 chany_top_in[3]:44 0.007549108 +59 chany_top_in[3]:39 chany_top_in[3]:38 0.01457143 +60 chany_top_in[3]:35 chany_top_in[3]:34 0.0004107143 +61 chany_top_in[3]:34 chany_top_in[3]:33 0.004857143 +62 chany_top_in[3]:18 chany_top_in[3]:17 0.0008214286 +63 chany_top_in[3]:17 chany_top_in[3]:16 0.001477679 + +*END + +*D_NET chany_top_in[5] 0.022054 //LENGTH 126.790 LUMPCC 0.01327037 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 43.240 107.510 +*I mux_right_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 36.515 71.400 +*I mux_right_ipin_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 24.670 76.840 +*I BUFT_RR_71:A I *L 0.001776 *C 31.280 14.960 +*N chany_top_in[5]:4 *C 31.280 14.960 +*N chany_top_in[5]:5 *C 36.755 14.960 +*N chany_top_in[5]:6 *C 36.800 15.005 +*N chany_top_in[5]:7 *C 36.800 23.742 +*N chany_top_in[5]:8 *C 36.793 23.800 +*N chany_top_in[5]:9 *C 35.900 23.800 +*N chany_top_in[5]:10 *C 35.880 23.808 +*N chany_top_in[5]:11 *C 24.707 76.840 +*N chany_top_in[5]:12 *C 25.715 76.840 +*N chany_top_in[5]:13 *C 25.760 76.795 +*N chany_top_in[5]:14 *C 25.760 71.458 +*N chany_top_in[5]:15 *C 25.768 71.400 +*N chany_top_in[5]:16 *C 36.477 71.400 +*N chany_top_in[5]:17 *C 35.925 71.400 +*N chany_top_in[5]:18 *C 35.880 71.400 +*N chany_top_in[5]:19 *C 35.873 71.400 +*N chany_top_in[5]:20 *C 35.880 71.400 +*N chany_top_in[5]:21 *C 35.880 104.713 +*N chany_top_in[5]:22 *C 35.900 104.720 +*N chany_top_in[5]:23 *C 43.233 104.720 +*N chany_top_in[5]:24 *C 43.240 104.778 + +*CAP +0 chany_top_in[5] 0.0002194794 +1 mux_right_ipin_0\/mux_l1_in_2_:A0 1e-06 +2 mux_right_ipin_4\/mux_l1_in_2_:A0 1e-06 +3 BUFT_RR_71:A 1e-06 +4 chany_top_in[5]:4 0.0004479417 +5 chany_top_in[5]:5 0.0004075926 +6 chany_top_in[5]:6 0.0004328263 +7 chany_top_in[5]:7 0.0004328263 +8 chany_top_in[5]:8 8.973577e-05 +9 chany_top_in[5]:9 8.973577e-05 +10 chany_top_in[5]:10 0.001027801 +11 chany_top_in[5]:11 8.914387e-05 +12 chany_top_in[5]:12 8.914387e-05 +13 chany_top_in[5]:13 0.0003141726 +14 chany_top_in[5]:14 0.0003141726 +15 chany_top_in[5]:15 0.0007071045 +16 chany_top_in[5]:16 7.74962e-05 +17 chany_top_in[5]:17 7.74962e-05 +18 chany_top_in[5]:18 3.749082e-05 +19 chany_top_in[5]:19 0.0007071045 +20 chany_top_in[5]:20 0.001670073 +21 chany_top_in[5]:21 0.0006422724 +22 chany_top_in[5]:22 0.0003437748 +23 chany_top_in[5]:23 0.0003437748 +24 chany_top_in[5]:24 0.0002194794 +25 chany_top_in[5]:14 chany_bottom_in[8]:27 5.340573e-06 +26 chany_top_in[5]:15 chany_bottom_in[8]:28 1.718481e-06 +27 chany_top_in[5]:13 chany_bottom_in[8]:26 5.340573e-06 +28 chany_top_in[5]:19 chany_bottom_in[8]:5 1.718481e-06 +29 chany_top_in[5]:20 chany_bottom_in[8]:39 0.001269424 +30 chany_top_in[5]:6 chany_bottom_in[8]:43 3.020743e-07 +31 chany_top_in[5]:6 chany_bottom_in[8]:47 4.183084e-07 +32 chany_top_in[5]:7 chany_bottom_in[8]:45 3.020743e-07 +33 chany_top_in[5]:7 chany_bottom_in[8]:46 4.183084e-07 +34 chany_top_in[5]:10 chany_bottom_in[8]:40 0.001269424 +35 chany_top_in[5]:22 chany_bottom_in[10]:12 0.000415281 +36 chany_top_in[5]:23 chany_bottom_in[10]:13 0.000415281 +37 chany_top_in[5]:21 chany_top_in[8]:28 0.001388412 +38 chany_top_in[5]:20 chany_top_in[8]:14 0.0007244161 +39 chany_top_in[5]:20 chany_top_in[8]:27 0.001388412 +40 chany_top_in[5]:20 chany_top_in[8]:28 0.0005901544 +41 chany_top_in[5]:6 chany_top_in[8]:8 7.783386e-05 +42 chany_top_in[5]:7 chany_top_in[8]:11 7.783386e-05 +43 chany_top_in[5]:10 chany_top_in[8]:13 0.0007244161 +44 chany_top_in[5]:10 chany_top_in[8]:27 0.0005901544 +45 chany_top_in[5]:22 chany_top_in[16]:46 4.66802e-07 +46 chany_top_in[5]:21 chany_top_in[16]:44 0.001395581 +47 chany_top_in[5]:23 chany_top_in[16]:45 4.66802e-07 +48 chany_top_in[5]:20 chany_top_in[16]:43 0.001395581 +49 chany_top_in[5]:20 chany_top_in[16]:44 0.0005326552 +50 chany_top_in[5]:10 chany_top_in[16]:43 0.0005326552 +51 chany_top_in[5]:15 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002331776 +52 chany_top_in[5]:19 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002331776 + +*RES +0 chany_top_in[5] chany_top_in[5]:24 0.002439732 +1 chany_top_in[5]:22 chany_top_in[5]:21 0.00341 +2 chany_top_in[5]:21 chany_top_in[5]:20 0.005218958 +3 chany_top_in[5]:24 chany_top_in[5]:23 0.00341 +4 chany_top_in[5]:23 chany_top_in[5]:22 0.001148758 +5 chany_top_in[5]:14 chany_top_in[5]:13 0.004765625 +6 chany_top_in[5]:15 chany_top_in[5]:14 0.00341 +7 chany_top_in[5]:12 chany_top_in[5]:11 0.0008995536 +8 chany_top_in[5]:13 chany_top_in[5]:12 0.0045 +9 chany_top_in[5]:11 mux_right_ipin_4\/mux_l1_in_2_:A0 0.152 +10 chany_top_in[5]:19 chany_top_in[5]:18 0.00341 +11 chany_top_in[5]:19 chany_top_in[5]:15 0.001583117 +12 chany_top_in[5]:20 chany_top_in[5]:19 0.00341 +13 chany_top_in[5]:20 chany_top_in[5]:10 0.007456158 +14 chany_top_in[5]:18 chany_top_in[5]:17 0.0045 +15 chany_top_in[5]:17 chany_top_in[5]:16 0.0004933036 +16 chany_top_in[5]:16 mux_right_ipin_0\/mux_l1_in_2_:A0 0.152 +17 chany_top_in[5]:4 BUFT_RR_71:A 0.152 +18 chany_top_in[5]:5 chany_top_in[5]:4 0.004888393 +19 chany_top_in[5]:6 chany_top_in[5]:5 0.0045 +20 chany_top_in[5]:7 chany_top_in[5]:6 0.00780134 +21 chany_top_in[5]:8 chany_top_in[5]:7 0.00341 +22 chany_top_in[5]:9 chany_top_in[5]:8 0.000139825 +23 chany_top_in[5]:10 chany_top_in[5]:9 0.00341 + +*END + +*D_NET chany_top_in[6] 0.01450163 //LENGTH 119.665 LUMPCC 0.003151327 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 46.460 107.510 +*I mux_right_ipin_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 51.695 58.820 +*I FTB_27__26:A I *L 0.001767 *C 50.600 4.080 +*I mux_right_ipin_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 59.595 97.240 +*N chany_top_in[6]:4 *C 59.558 97.240 +*N chany_top_in[6]:5 *C 52.025 97.240 +*N chany_top_in[6]:6 *C 51.980 97.240 +*N chany_top_in[6]:7 *C 50.638 4.080 +*N chany_top_in[6]:8 *C 51.015 4.080 +*N chany_top_in[6]:9 *C 51.060 4.125 +*N chany_top_in[6]:10 *C 51.060 8.160 +*N chany_top_in[6]:11 *C 51.520 8.160 +*N chany_top_in[6]:12 *C 51.695 58.820 +*N chany_top_in[6]:13 *C 51.520 58.820 +*N chany_top_in[6]:14 *C 51.520 58.820 +*N chany_top_in[6]:15 *C 51.520 97.240 +*N chany_top_in[6]:16 *C 51.520 99.575 +*N chany_top_in[6]:17 *C 51.475 99.620 +*N chany_top_in[6]:18 *C 46.505 99.620 +*N chany_top_in[6]:19 *C 46.460 99.665 + +*CAP +0 chany_top_in[6] 0.0005489517 +1 mux_right_ipin_5\/mux_l1_in_2_:A0 1e-06 +2 FTB_27__26:A 1e-06 +3 mux_right_ipin_1\/mux_l1_in_2_:A0 1e-06 +4 chany_top_in[6]:4 0.0003820961 +5 chany_top_in[6]:5 0.0003820962 +6 chany_top_in[6]:6 6.747688e-05 +7 chany_top_in[6]:7 4.854228e-05 +8 chany_top_in[6]:8 4.854228e-05 +9 chany_top_in[6]:9 0.0002366739 +10 chany_top_in[6]:10 0.000266525 +11 chany_top_in[6]:11 0.001992913 +12 chany_top_in[6]:12 5.453901e-05 +13 chany_top_in[6]:13 6.239286e-05 +14 chany_top_in[6]:14 0.00377999 +15 chany_top_in[6]:15 0.001983531 +16 chany_top_in[6]:16 0.0001637405 +17 chany_top_in[6]:17 0.0003901729 +18 chany_top_in[6]:18 0.0003901729 +19 chany_top_in[6]:19 0.0005489517 +20 chany_top_in[6]:14 chany_bottom_in[2]:31 2.594344e-07 +21 chany_top_in[6]:14 chany_bottom_in[2]:37 2.035224e-05 +22 chany_top_in[6]:14 chany_bottom_in[2]:38 2.690318e-05 +23 chany_top_in[6]:14 chany_bottom_in[2]:52 1.719306e-06 +24 chany_top_in[6]:14 chany_bottom_in[2]:56 0.0003284142 +25 chany_top_in[6]:14 chany_bottom_in[2]:60 0.0001082827 +26 chany_top_in[6]:9 chany_bottom_in[2] 3.978807e-06 +27 chany_top_in[6]:10 chany_bottom_in[2]:62 6.292963e-06 +28 chany_top_in[6]:11 chany_bottom_in[2]:53 1.719306e-06 +29 chany_top_in[6]:11 chany_bottom_in[2]:60 0.0003284142 +30 chany_top_in[6]:11 chany_bottom_in[2]:61 0.0001105968 +31 chany_top_in[6]:15 chany_bottom_in[2]:28 2.594344e-07 +32 chany_top_in[6]:15 chany_bottom_in[2]:34 2.035224e-05 +33 chany_top_in[6]:15 chany_bottom_in[2]:37 2.690318e-05 +34 chany_top_in[6]:14 chany_top_in[2]:22 4.483757e-05 +35 chany_top_in[6]:14 chany_top_in[2]:38 4.518768e-06 +36 chany_top_in[6]:14 chany_top_in[2]:39 5.752563e-06 +37 chany_top_in[6]:14 chany_top_in[2]:44 0.0004620464 +38 chany_top_in[6]:14 chany_top_in[2]:48 1.752763e-05 +39 chany_top_in[6]:14 chany_top_in[2]:62 2.729009e-05 +40 chany_top_in[6]:11 chany_top_in[2]:35 4.518768e-06 +41 chany_top_in[6]:11 chany_top_in[2]:38 5.752563e-06 +42 chany_top_in[6]:11 chany_top_in[2]:43 0.0004620464 +43 chany_top_in[6]:11 chany_top_in[2]:47 1.752763e-05 +44 chany_top_in[6]:15 chany_top_in[2]:21 4.483757e-05 +45 chany_top_in[6]:15 chany_top_in[2]:63 2.729009e-05 +46 chany_top_in[6]:4 mux_tree_tapbuf_size10_2_sram[1]:38 7.3735e-09 +47 chany_top_in[6]:4 mux_tree_tapbuf_size10_2_sram[1]:34 7.499059e-05 +48 chany_top_in[6]:4 mux_tree_tapbuf_size10_2_sram[1]:36 4.403713e-05 +49 chany_top_in[6]:5 mux_tree_tapbuf_size10_2_sram[1]:33 7.499059e-05 +50 chany_top_in[6]:5 mux_tree_tapbuf_size10_2_sram[1]:35 4.403713e-05 +51 chany_top_in[6]:5 mux_tree_tapbuf_size10_2_sram[1]:37 7.3735e-09 +52 chany_top_in[6]:14 mux_tree_tapbuf_size10_2_sram[1]:29 0.0001472835 +53 chany_top_in[6]:14 mux_tree_tapbuf_size10_2_sram[1]:8 4.428836e-06 +54 chany_top_in[6]:15 mux_tree_tapbuf_size10_2_sram[1]:30 0.0001472835 +55 chany_top_in[6]:15 mux_tree_tapbuf_size10_2_sram[1]:7 4.428836e-06 +56 chany_top_in[6]:14 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.000104894 +57 chany_top_in[6]:11 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.000104894 +58 chany_top_in[6]:14 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.027289e-05 +59 chany_top_in[6]:15 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.027289e-05 +60 chany_top_in[6]:4 ropt_net_186:3 9.555235e-05 +61 chany_top_in[6]:5 ropt_net_186:4 9.555235e-05 + +*RES +0 chany_top_in[6] chany_top_in[6]:19 0.007004465 +1 chany_top_in[6]:4 mux_right_ipin_1\/mux_l1_in_2_:A0 0.152 +2 chany_top_in[6]:5 chany_top_in[6]:4 0.006725446 +3 chany_top_in[6]:6 chany_top_in[6]:5 0.0045 +4 chany_top_in[6]:13 chany_top_in[6]:12 9.51087e-05 +5 chany_top_in[6]:14 chany_top_in[6]:13 0.0045 +6 chany_top_in[6]:14 chany_top_in[6]:11 0.04523215 +7 chany_top_in[6]:12 mux_right_ipin_5\/mux_l1_in_2_:A0 0.152 +8 chany_top_in[6]:17 chany_top_in[6]:16 0.0045 +9 chany_top_in[6]:16 chany_top_in[6]:15 0.002084821 +10 chany_top_in[6]:18 chany_top_in[6]:17 0.0044375 +11 chany_top_in[6]:19 chany_top_in[6]:18 0.0045 +12 chany_top_in[6]:8 chany_top_in[6]:7 0.0003370536 +13 chany_top_in[6]:9 chany_top_in[6]:8 0.0045 +14 chany_top_in[6]:7 FTB_27__26:A 0.152 +15 chany_top_in[6]:10 chany_top_in[6]:9 0.003602679 +16 chany_top_in[6]:11 chany_top_in[6]:10 0.0004107143 +17 chany_top_in[6]:15 chany_top_in[6]:14 0.03430358 +18 chany_top_in[6]:15 chany_top_in[6]:6 0.0004107143 + +*END + +*D_NET chany_top_in[9] 0.01667288 //LENGTH 112.255 LUMPCC 0.008058848 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 25.760 107.510 +*I mux_right_ipin_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 19.780 77.860 +*I mux_right_ipin_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 29.270 28.220 +*I FTB_30__29:A I *L 0.001776 *C 31.280 12.240 +*N chany_top_in[9]:4 *C 31.243 12.240 +*N chany_top_in[9]:5 *C 29.485 12.240 +*N chany_top_in[9]:6 *C 29.440 12.285 +*N chany_top_in[9]:7 *C 29.270 28.220 +*N chany_top_in[9]:8 *C 29.440 28.220 +*N chany_top_in[9]:9 *C 29.440 28.220 +*N chany_top_in[9]:10 *C 29.440 29.183 +*N chany_top_in[9]:11 *C 29.433 29.240 +*N chany_top_in[9]:12 *C 24.860 29.240 +*N chany_top_in[9]:13 *C 24.840 29.248 +*N chany_top_in[9]:14 *C 19.780 77.860 +*N chany_top_in[9]:15 *C 19.780 77.905 +*N chany_top_in[9]:16 *C 19.780 79.502 +*N chany_top_in[9]:17 *C 19.788 79.560 +*N chany_top_in[9]:18 *C 24.820 79.560 +*N chany_top_in[9]:19 *C 24.840 79.560 +*N chany_top_in[9]:20 *C 24.840 106.073 +*N chany_top_in[9]:21 *C 24.860 106.080 +*N chany_top_in[9]:22 *C 25.753 106.080 +*N chany_top_in[9]:23 *C 25.760 106.138 + +*CAP +0 chany_top_in[9] 9.380469e-05 +1 mux_right_ipin_4\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_8\/mux_l1_in_2_:A0 1e-06 +3 FTB_30__29:A 1e-06 +4 chany_top_in[9]:4 0.0001143005 +5 chany_top_in[9]:5 0.0001143005 +6 chany_top_in[9]:6 0.0005971143 +7 chany_top_in[9]:7 4.455474e-05 +8 chany_top_in[9]:8 4.93456e-05 +9 chany_top_in[9]:9 0.0006744244 +10 chany_top_in[9]:10 4.473011e-05 +11 chany_top_in[9]:11 0.0003712023 +12 chany_top_in[9]:12 0.0003712023 +13 chany_top_in[9]:13 0.001596254 +14 chany_top_in[9]:14 3.534862e-05 +15 chany_top_in[9]:15 0.0001268082 +16 chany_top_in[9]:16 0.0001268082 +17 chany_top_in[9]:17 0.0003730909 +18 chany_top_in[9]:18 0.0003730909 +19 chany_top_in[9]:19 0.002432352 +20 chany_top_in[9]:20 0.0008360982 +21 chany_top_in[9]:21 7.119965e-05 +22 chany_top_in[9]:22 7.119965e-05 +23 chany_top_in[9]:23 9.380469e-05 +24 chany_top_in[9] chany_bottom_in[8]:17 8.008969e-07 +25 chany_top_in[9]:13 chany_bottom_in[8]:27 0.0005340549 +26 chany_top_in[9]:21 chany_bottom_in[8]:25 3.32066e-07 +27 chany_top_in[9]:20 chany_bottom_in[8]:26 0.0009408362 +28 chany_top_in[9]:23 chany_bottom_in[8]:18 8.008969e-07 +29 chany_top_in[9]:22 chany_bottom_in[8]:24 3.32066e-07 +30 chany_top_in[9]:19 chany_bottom_in[8]:26 0.0005340549 +31 chany_top_in[9]:19 chany_bottom_in[8]:27 0.0009408362 +32 chany_top_in[9]:13 chany_bottom_in[9]:31 0.0008563203 +33 chany_top_in[9]:20 chany_bottom_in[9]:19 0.0002975492 +34 chany_top_in[9]:18 chany_bottom_in[9]:6 3.412832e-06 +35 chany_top_in[9]:19 chany_bottom_in[9]:20 0.0002975492 +36 chany_top_in[9]:19 chany_bottom_in[9]:30 0.0008563203 +37 chany_top_in[9]:17 chany_bottom_in[9]:21 3.412832e-06 +38 chany_top_in[9]:8 chany_bottom_in[9]:39 1.31368e-05 +39 chany_top_in[9]:7 chany_bottom_in[9]:38 1.31368e-05 +40 chany_top_in[9]:6 chany_bottom_in[17]:21 0.0002868014 +41 chany_top_in[9]:6 chany_bottom_in[17]:22 0.0001375234 +42 chany_top_in[9]:10 chany_bottom_in[17]:18 3.135321e-05 +43 chany_top_in[9]:9 chany_bottom_in[17]:18 0.0002868014 +44 chany_top_in[9]:9 chany_bottom_in[17]:21 0.0001688766 +45 chany_top_in[9]:6 chany_top_in[16]:30 7.832754e-06 +46 chany_top_in[9]:13 chany_top_in[16]:30 0.0008427404 +47 chany_top_in[9]:19 chany_top_in[16]:31 0.0008427404 +48 chany_top_in[9]:9 chany_top_in[16]:31 7.832754e-06 +49 chany_top_in[9]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.673025e-05 +50 chany_top_in[9]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.673025e-05 + +*RES +0 chany_top_in[9] chany_top_in[9]:23 0.001225446 +1 chany_top_in[9]:5 chany_top_in[9]:4 0.001569197 +2 chany_top_in[9]:6 chany_top_in[9]:5 0.0045 +3 chany_top_in[9]:4 FTB_30__29:A 0.152 +4 chany_top_in[9]:12 chany_top_in[9]:11 0.0007163583 +5 chany_top_in[9]:13 chany_top_in[9]:12 0.00341 +6 chany_top_in[9]:10 chany_top_in[9]:9 0.0008593751 +7 chany_top_in[9]:11 chany_top_in[9]:10 0.00341 +8 chany_top_in[9]:21 chany_top_in[9]:20 0.00341 +9 chany_top_in[9]:20 chany_top_in[9]:19 0.004153625 +10 chany_top_in[9]:23 chany_top_in[9]:22 0.00341 +11 chany_top_in[9]:22 chany_top_in[9]:21 0.000139825 +12 chany_top_in[9]:18 chany_top_in[9]:17 0.0007884249 +13 chany_top_in[9]:19 chany_top_in[9]:18 0.00341 +14 chany_top_in[9]:19 chany_top_in[9]:13 0.007882291 +15 chany_top_in[9]:16 chany_top_in[9]:15 0.001426339 +16 chany_top_in[9]:17 chany_top_in[9]:16 0.00341 +17 chany_top_in[9]:14 mux_right_ipin_4\/mux_l2_in_2_:A1 0.152 +18 chany_top_in[9]:15 chany_top_in[9]:14 0.0045 +19 chany_top_in[9]:8 chany_top_in[9]:7 9.239131e-05 +20 chany_top_in[9]:9 chany_top_in[9]:8 0.0045 +21 chany_top_in[9]:9 chany_top_in[9]:6 0.01422768 +22 chany_top_in[9]:7 mux_right_ipin_8\/mux_l1_in_2_:A0 0.152 + +*END + +*D_NET chany_top_in[10] 0.0176317 //LENGTH 148.495 LUMPCC 0.003057109 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 64.860 107.510 +*I mux_right_ipin_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 65.320 52.700 +*I mux_right_ipin_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 73.965 30.940 +*I ropt_mt_inst_735:A I *L 0.001767 *C 46.000 4.080 +*I mux_left_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 66.800 58.140 +*N chany_top_in[10]:5 *C 66.763 58.140 +*N chany_top_in[10]:6 *C 46.038 4.080 +*N chany_top_in[10]:7 *C 47.795 4.080 +*N chany_top_in[10]:8 *C 47.840 4.125 +*N chany_top_in[10]:9 *C 47.840 7.435 +*N chany_top_in[10]:10 *C 47.885 7.480 +*N chany_top_in[10]:11 *C 74.935 7.480 +*N chany_top_in[10]:12 *C 74.980 7.525 +*N chany_top_in[10]:13 *C 74.002 30.940 +*N chany_top_in[10]:14 *C 74.935 30.940 +*N chany_top_in[10]:15 *C 74.980 30.940 +*N chany_top_in[10]:16 *C 74.980 47.543 +*N chany_top_in[10]:17 *C 74.972 47.600 +*N chany_top_in[10]:18 *C 65.788 47.600 +*N chany_top_in[10]:19 *C 65.780 47.657 +*N chany_top_in[10]:20 *C 65.358 52.700 +*N chany_top_in[10]:21 *C 65.735 52.700 +*N chany_top_in[10]:22 *C 65.780 52.700 +*N chany_top_in[10]:23 *C 65.780 58.095 +*N chany_top_in[10]:24 *C 65.780 58.140 +*N chany_top_in[10]:25 *C 65.780 58.480 +*N chany_top_in[10]:26 *C 64.905 58.480 +*N chany_top_in[10]:27 *C 64.860 58.525 + +*CAP +0 chany_top_in[10] 0.002147087 +1 mux_right_ipin_5\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_9\/mux_l2_in_2_:A1 1e-06 +3 ropt_mt_inst_735:A 1e-06 +4 mux_left_ipin_0\/mux_l2_in_2_:A1 1e-06 +5 chany_top_in[10]:5 7.459948e-05 +6 chany_top_in[10]:6 0.0001074801 +7 chany_top_in[10]:7 0.0001074801 +8 chany_top_in[10]:8 0.00025049 +9 chany_top_in[10]:9 0.00025049 +10 chany_top_in[10]:10 0.001799432 +11 chany_top_in[10]:11 0.001799432 +12 chany_top_in[10]:12 0.0008751482 +13 chany_top_in[10]:13 9.693521e-05 +14 chany_top_in[10]:14 9.693521e-05 +15 chany_top_in[10]:15 0.001536221 +16 chany_top_in[10]:16 0.0006275552 +17 chany_top_in[10]:17 0.0005824251 +18 chany_top_in[10]:18 0.0005824251 +19 chany_top_in[10]:19 0.0002447541 +20 chany_top_in[10]:20 4.498661e-05 +21 chany_top_in[10]:21 4.498661e-05 +22 chany_top_in[10]:22 0.0005722084 +23 chany_top_in[10]:23 0.0002999912 +24 chany_top_in[10]:24 0.0001020599 +25 chany_top_in[10]:25 0.0001039226 +26 chany_top_in[10]:26 7.646217e-05 +27 chany_top_in[10]:27 0.002147087 +28 chany_top_in[10] chany_bottom_in[4]:17 0.0004585814 +29 chany_top_in[10] chany_bottom_in[4]:19 5.140884e-06 +30 chany_top_in[10] chany_bottom_in[4]:22 3.743858e-06 +31 chany_top_in[10] chany_bottom_in[4]:27 2.010698e-05 +32 chany_top_in[10]:19 chany_bottom_in[4]:28 7.833163e-06 +33 chany_top_in[10]:23 chany_bottom_in[4]:27 2.01387e-06 +34 chany_top_in[10]:22 chany_bottom_in[4]:27 7.833163e-06 +35 chany_top_in[10]:22 chany_bottom_in[4]:28 2.01387e-06 +36 chany_top_in[10]:27 chany_bottom_in[4]:18 0.0004585814 +37 chany_top_in[10]:27 chany_bottom_in[4]:22 5.140884e-06 +38 chany_top_in[10]:27 chany_bottom_in[4]:23 3.743858e-06 +39 chany_top_in[10]:27 chany_bottom_in[4]:28 2.010698e-05 +40 chany_top_in[10]:12 chany_top_in[4]:15 0.0002735421 +41 chany_top_in[10]:12 chany_top_in[4]:18 5.567375e-05 +42 chany_top_in[10]:7 chany_top_in[4]:12 7.642401e-05 +43 chany_top_in[10]:6 chany_top_in[4]:11 7.642401e-05 +44 chany_top_in[10]:16 chany_top_in[4]:19 0.0002291383 +45 chany_top_in[10]:15 chany_top_in[4]:18 0.0005026804 +46 chany_top_in[10]:15 chany_top_in[4]:19 5.567375e-05 +47 chany_top_in[10]:16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.843702e-05 +48 chany_top_in[10]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 8.843702e-05 +49 chany_top_in[10] mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.707409e-05 +50 chany_top_in[10]:27 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.707409e-05 +51 chany_top_in[10] mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.081078e-05 +52 chany_top_in[10]:27 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.081078e-05 +53 chany_top_in[10] mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001300344 +54 chany_top_in[10]:27 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001300344 + +*RES +0 chany_top_in[10] chany_top_in[10]:27 0.04373661 +1 chany_top_in[10]:11 chany_top_in[10]:10 0.02415179 +2 chany_top_in[10]:12 chany_top_in[10]:11 0.0045 +3 chany_top_in[10]:10 chany_top_in[10]:9 0.0045 +4 chany_top_in[10]:9 chany_top_in[10]:8 0.002955357 +5 chany_top_in[10]:7 chany_top_in[10]:6 0.001569197 +6 chany_top_in[10]:8 chany_top_in[10]:7 0.0045 +7 chany_top_in[10]:6 ropt_mt_inst_735:A 0.152 +8 chany_top_in[10]:19 chany_top_in[10]:18 0.00341 +9 chany_top_in[10]:18 chany_top_in[10]:17 0.001438983 +10 chany_top_in[10]:16 chany_top_in[10]:15 0.01482366 +11 chany_top_in[10]:17 chany_top_in[10]:16 0.00341 +12 chany_top_in[10]:24 chany_top_in[10]:23 0.0045 +13 chany_top_in[10]:24 chany_top_in[10]:5 0.0008772322 +14 chany_top_in[10]:23 chany_top_in[10]:22 0.004816964 +15 chany_top_in[10]:14 chany_top_in[10]:13 0.0008325893 +16 chany_top_in[10]:15 chany_top_in[10]:14 0.0045 +17 chany_top_in[10]:15 chany_top_in[10]:12 0.02090625 +18 chany_top_in[10]:13 mux_right_ipin_9\/mux_l2_in_2_:A1 0.152 +19 chany_top_in[10]:21 chany_top_in[10]:20 0.0003370536 +20 chany_top_in[10]:22 chany_top_in[10]:21 0.0045 +21 chany_top_in[10]:22 chany_top_in[10]:19 0.004502232 +22 chany_top_in[10]:20 mux_right_ipin_5\/mux_l2_in_2_:A1 0.152 +23 chany_top_in[10]:5 mux_left_ipin_0\/mux_l2_in_2_:A1 0.152 +24 chany_top_in[10]:26 chany_top_in[10]:25 0.00078125 +25 chany_top_in[10]:27 chany_top_in[10]:26 0.0045 +26 chany_top_in[10]:25 chany_top_in[10]:24 0.0003035715 + +*END + +*D_NET chany_top_in[12] 0.01938253 //LENGTH 155.135 LUMPCC 0.003448842 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 51.980 107.510 +*I mux_right_ipin_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 45.445 90.780 +*I mux_right_ipin_7\/mux_l2_in_3_:A1 I *L 0.00198 *C 72.125 88.740 +*I mux_right_ipin_15\/mux_l2_in_3_:A1 I *L 0.00198 *C 74.980 85.340 +*I BUFT_P_118:A I *L 0.001776 *C 30.360 14.960 +*N chany_top_in[12]:5 *C 30.360 14.960 +*N chany_top_in[12]:6 *C 30.360 14.280 +*N chany_top_in[12]:7 *C 32.615 14.280 +*N chany_top_in[12]:8 *C 32.660 14.325 +*N chany_top_in[12]:9 *C 32.660 28.503 +*N chany_top_in[12]:10 *C 32.668 28.560 +*N chany_top_in[12]:11 *C 48.740 28.560 +*N chany_top_in[12]:12 *C 48.760 28.568 +*N chany_top_in[12]:13 *C 48.760 80.233 +*N chany_top_in[12]:14 *C 48.775 80.240 +*N chany_top_in[12]:15 *C 49.218 80.240 +*N chany_top_in[12]:16 *C 49.220 80.297 +*N chany_top_in[12]:17 *C 74.943 85.340 +*N chany_top_in[12]:18 *C 72.265 85.340 +*N chany_top_in[12]:19 *C 72.220 85.385 +*N chany_top_in[12]:20 *C 72.220 88.695 +*N chany_top_in[12]:21 *C 72.125 88.740 +*N chany_top_in[12]:22 *C 72.220 89.080 +*N chany_top_in[12]:23 *C 45.483 90.780 +*N chany_top_in[12]:24 *C 46.000 90.780 +*N chany_top_in[12]:25 *C 46.000 90.440 +*N chany_top_in[12]:26 *C 48.255 90.440 +*N chany_top_in[12]:27 *C 48.300 90.395 +*N chany_top_in[12]:28 *C 48.300 89.125 +*N chany_top_in[12]:29 *C 48.345 89.080 +*N chany_top_in[12]:30 *C 49.220 89.080 +*N chany_top_in[12]:31 *C 49.220 89.080 +*N chany_top_in[12]:32 *C 49.220 106.023 +*N chany_top_in[12]:33 *C 49.227 106.080 +*N chany_top_in[12]:34 *C 51.973 106.080 +*N chany_top_in[12]:35 *C 51.980 106.138 + +*CAP +0 chany_top_in[12] 0.0001241747 +1 mux_right_ipin_1\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_7\/mux_l2_in_3_:A1 1e-06 +3 mux_right_ipin_15\/mux_l2_in_3_:A1 1e-06 +4 BUFT_P_118:A 1e-06 +5 chany_top_in[12]:5 8.077216e-05 +6 chany_top_in[12]:6 0.0002319653 +7 chany_top_in[12]:7 0.0001826044 +8 chany_top_in[12]:8 0.0005149378 +9 chany_top_in[12]:9 0.0005149378 +10 chany_top_in[12]:10 0.001111142 +11 chany_top_in[12]:11 0.001111142 +12 chany_top_in[12]:12 0.00189199 +13 chany_top_in[12]:13 0.00189199 +14 chany_top_in[12]:14 5.1815e-05 +15 chany_top_in[12]:15 5.1815e-05 +16 chany_top_in[12]:16 0.0004447968 +17 chany_top_in[12]:17 0.0002291563 +18 chany_top_in[12]:18 0.0002291563 +19 chany_top_in[12]:19 0.0001895657 +20 chany_top_in[12]:20 0.0001895657 +21 chany_top_in[12]:21 5.730807e-05 +22 chany_top_in[12]:22 0.001552662 +23 chany_top_in[12]:23 6.673062e-05 +24 chany_top_in[12]:24 9.276373e-05 +25 chany_top_in[12]:25 0.0002033508 +26 chany_top_in[12]:26 0.0001773177 +27 chany_top_in[12]:27 7.633674e-05 +28 chany_top_in[12]:28 7.633674e-05 +29 chany_top_in[12]:29 6.701633e-05 +30 chany_top_in[12]:30 0.001626008 +31 chany_top_in[12]:31 0.001414424 +32 chany_top_in[12]:32 0.0009410617 +33 chany_top_in[12]:33 0.0002063329 +34 chany_top_in[12]:34 0.0002063329 +35 chany_top_in[12]:35 0.0001241747 +36 chany_top_in[12]:9 chany_bottom_in[9]:40 0.0003935181 +37 chany_top_in[12]:8 chany_bottom_in[9]:41 0.0003935181 +38 chany_top_in[12]:13 chany_top_in[18]:19 0.0003535558 +39 chany_top_in[12]:13 chany_top_in[18]:18 0.0007515529 +40 chany_top_in[12]:12 chany_top_in[18]:17 0.0007515529 +41 chany_top_in[12]:12 chany_top_in[18]:18 0.0003535558 +42 chany_top_in[12]:31 ropt_net_169:5 9.54504e-05 +43 chany_top_in[12]:32 ropt_net_169:4 9.54504e-05 +44 chany_top_in[12]:31 ropt_net_173:4 8.248464e-06 +45 chany_top_in[12]:32 ropt_net_173:5 8.248464e-06 +46 chany_top_in[12]:33 ropt_net_173:6 0.0001220952 +47 chany_top_in[12]:34 ropt_net_173:7 0.0001220952 + +*RES +0 chany_top_in[12] chany_top_in[12]:35 0.001225446 +1 chany_top_in[12]:30 chany_top_in[12]:29 0.0007812501 +2 chany_top_in[12]:30 chany_top_in[12]:22 0.02053571 +3 chany_top_in[12]:31 chany_top_in[12]:30 0.0045 +4 chany_top_in[12]:31 chany_top_in[12]:16 0.007841518 +5 chany_top_in[12]:21 mux_right_ipin_7\/mux_l2_in_3_:A1 0.152 +6 chany_top_in[12]:21 chany_top_in[12]:20 0.0045 +7 chany_top_in[12]:20 chany_top_in[12]:19 0.002955357 +8 chany_top_in[12]:18 chany_top_in[12]:17 0.002390625 +9 chany_top_in[12]:19 chany_top_in[12]:18 0.0045 +10 chany_top_in[12]:17 mux_right_ipin_15\/mux_l2_in_3_:A1 0.152 +11 chany_top_in[12]:16 chany_top_in[12]:15 0.00341 +12 chany_top_in[12]:15 chany_top_in[12]:14 6.499219e-05 +13 chany_top_in[12]:14 chany_top_in[12]:13 0.00341 +14 chany_top_in[12]:13 chany_top_in[12]:12 0.008094183 +15 chany_top_in[12]:11 chany_top_in[12]:10 0.002518025 +16 chany_top_in[12]:12 chany_top_in[12]:11 0.00341 +17 chany_top_in[12]:9 chany_top_in[12]:8 0.01265848 +18 chany_top_in[12]:10 chany_top_in[12]:9 0.00341 +19 chany_top_in[12]:7 chany_top_in[12]:6 0.002013393 +20 chany_top_in[12]:8 chany_top_in[12]:7 0.0045 +21 chany_top_in[12]:5 BUFT_P_118:A 0.152 +22 chany_top_in[12]:32 chany_top_in[12]:31 0.01512723 +23 chany_top_in[12]:33 chany_top_in[12]:32 0.00341 +24 chany_top_in[12]:35 chany_top_in[12]:34 0.00341 +25 chany_top_in[12]:34 chany_top_in[12]:33 0.00043005 +26 chany_top_in[12]:29 chany_top_in[12]:28 0.0045 +27 chany_top_in[12]:28 chany_top_in[12]:27 0.001133929 +28 chany_top_in[12]:26 chany_top_in[12]:25 0.002013393 +29 chany_top_in[12]:27 chany_top_in[12]:26 0.0045 +30 chany_top_in[12]:23 mux_right_ipin_1\/mux_l2_in_2_:A1 0.152 +31 chany_top_in[12]:6 chany_top_in[12]:5 0.0006071429 +32 chany_top_in[12]:24 chany_top_in[12]:23 0.0004620536 +33 chany_top_in[12]:25 chany_top_in[12]:24 0.0003035715 +34 chany_top_in[12]:22 chany_top_in[12]:21 0.0003035715 + +*END + +*D_NET chany_top_in[17] 0.01952069 //LENGTH 155.385 LUMPCC 0.002668738 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 30.360 107.510 +*I ropt_mt_inst_751:A I *L 0.001767 *C 58.420 6.800 +*I mux_right_ipin_12\/mux_l2_in_3_:A1 I *L 0.00198 *C 25.760 18.020 +*I mux_right_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 37.260 85.340 +*N chany_top_in[17]:4 *C 37.260 85.340 +*N chany_top_in[17]:5 *C 25.798 18.020 +*N chany_top_in[17]:6 *C 28.980 18.020 +*N chany_top_in[17]:7 *C 28.980 17.680 +*N chany_top_in[17]:8 *C 34.040 17.680 +*N chany_top_in[17]:9 *C 58.383 6.800 +*N chany_top_in[17]:10 *C 56.165 6.800 +*N chany_top_in[17]:11 *C 56.120 6.755 +*N chany_top_in[17]:12 *C 56.120 5.498 +*N chany_top_in[17]:13 *C 56.113 5.440 +*N chany_top_in[17]:14 *C 39.568 5.440 +*N chany_top_in[17]:15 *C 39.560 5.498 +*N chany_top_in[17]:16 *C 39.560 7.095 +*N chany_top_in[17]:17 *C 39.515 7.140 +*N chany_top_in[17]:18 *C 38.685 7.140 +*N chany_top_in[17]:19 *C 38.640 7.185 +*N chany_top_in[17]:20 *C 38.640 17.295 +*N chany_top_in[17]:21 *C 38.595 17.340 +*N chany_top_in[17]:22 *C 34.040 17.340 +*N chany_top_in[17]:23 *C 34.040 17.385 +*N chany_top_in[17]:24 *C 34.040 52.655 +*N chany_top_in[17]:25 *C 34.085 52.700 +*N chany_top_in[17]:26 *C 38.595 52.700 +*N chany_top_in[17]:27 *C 38.640 52.745 +*N chany_top_in[17]:28 *C 38.640 85.975 +*N chany_top_in[17]:29 *C 38.640 86.020 +*N chany_top_in[17]:30 *C 38.640 85.680 +*N chany_top_in[17]:31 *C 37.260 85.680 +*N chany_top_in[17]:32 *C 30.405 85.680 +*N chany_top_in[17]:33 *C 30.360 85.725 + +*CAP +0 chany_top_in[17] 0.001189393 +1 ropt_mt_inst_751:A 1e-06 +2 mux_right_ipin_12\/mux_l2_in_3_:A1 1e-06 +3 mux_right_ipin_0\/mux_l2_in_3_:A1 1e-06 +4 chany_top_in[17]:4 5.895817e-05 +5 chany_top_in[17]:5 0.0002739181 +6 chany_top_in[17]:6 0.0003005209 +7 chany_top_in[17]:7 0.0003991458 +8 chany_top_in[17]:8 0.000402304 +9 chany_top_in[17]:9 0.0001751192 +10 chany_top_in[17]:10 0.0001751192 +11 chany_top_in[17]:11 9.37959e-05 +12 chany_top_in[17]:12 9.37959e-05 +13 chany_top_in[17]:13 0.001008956 +14 chany_top_in[17]:14 0.001008956 +15 chany_top_in[17]:15 0.0001514553 +16 chany_top_in[17]:16 0.0001514553 +17 chany_top_in[17]:17 8.691102e-05 +18 chany_top_in[17]:18 8.691102e-05 +19 chany_top_in[17]:19 0.0006188101 +20 chany_top_in[17]:20 0.0006188101 +21 chany_top_in[17]:21 0.0002999636 +22 chany_top_in[17]:22 0.0003297246 +23 chany_top_in[17]:23 0.001272497 +24 chany_top_in[17]:24 0.001272497 +25 chany_top_in[17]:25 0.0002740991 +26 chany_top_in[17]:26 0.0002740991 +27 chany_top_in[17]:27 0.001930614 +28 chany_top_in[17]:28 0.001930614 +29 chany_top_in[17]:29 6.06374e-05 +30 chany_top_in[17]:30 0.0001301143 +31 chany_top_in[17]:31 0.0005604728 +32 chany_top_in[17]:32 0.0004298895 +33 chany_top_in[17]:33 0.001189393 +34 chany_top_in[17]:23 chany_bottom_in[3]:42 0.00027752 +35 chany_top_in[17]:23 chany_bottom_in[3]:48 7.78316e-06 +36 chany_top_in[17]:23 chany_bottom_in[3]:55 4.819824e-06 +37 chany_top_in[17]:24 chany_bottom_in[3]:41 0.00027752 +38 chany_top_in[17]:24 chany_bottom_in[3]:45 7.78316e-06 +39 chany_top_in[17]:24 chany_bottom_in[3]:48 4.819824e-06 +40 chany_top_in[17]:20 chany_top_in[3]:21 3.974042e-06 +41 chany_top_in[17]:18 chany_top_in[3]:15 1.127807e-05 +42 chany_top_in[17]:19 chany_top_in[3]:18 3.974042e-06 +43 chany_top_in[17]:17 chany_top_in[3]:14 1.127807e-05 +44 chany_top_in[17]:23 chany_top_in[3]:21 0.0002862391 +45 chany_top_in[17]:23 chany_top_in[3]:26 1.462798e-05 +46 chany_top_in[17]:23 chany_top_in[3]:33 1.020066e-05 +47 chany_top_in[17]:24 chany_top_in[3]:22 0.0002862391 +48 chany_top_in[17]:24 chany_top_in[3]:33 1.462798e-05 +49 chany_top_in[17]:24 chany_top_in[3]:34 1.020066e-05 +50 chany_top_in[17]:23 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002248672 +51 chany_top_in[17]:24 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002248672 +52 chany_top_in[17]:20 ropt_net_156:7 6.328837e-05 +53 chany_top_in[17]:19 ropt_net_156:6 6.328837e-05 +54 chany_top_in[17]:14 ropt_net_177:5 0.0002448006 +55 chany_top_in[17]:13 ropt_net_177:6 0.0002448006 +56 chany_top_in[17]:14 ropt_net_176:6 3.405787e-05 +57 chany_top_in[17]:12 ropt_net_176:8 2.317109e-06 +58 chany_top_in[17]:12 ropt_net_176:4 2.428939e-05 +59 chany_top_in[17]:13 ropt_net_176:7 3.405787e-05 +60 chany_top_in[17]:11 ropt_net_176:9 2.317109e-06 +61 chany_top_in[17]:11 ropt_net_176:5 2.428939e-05 +62 chany_top_in[17] ropt_net_167:5 0.0001243059 +63 chany_top_in[17]:33 ropt_net_167:4 0.0001243059 + +*RES +0 chany_top_in[17] chany_top_in[17]:33 0.01945089 +1 chany_top_in[17]:21 chany_top_in[17]:20 0.0045 +2 chany_top_in[17]:20 chany_top_in[17]:19 0.009026785 +3 chany_top_in[17]:18 chany_top_in[17]:17 0.0007410714 +4 chany_top_in[17]:19 chany_top_in[17]:18 0.0045 +5 chany_top_in[17]:17 chany_top_in[17]:16 0.0045 +6 chany_top_in[17]:16 chany_top_in[17]:15 0.001426339 +7 chany_top_in[17]:15 chany_top_in[17]:14 0.00341 +8 chany_top_in[17]:14 chany_top_in[17]:13 0.00259205 +9 chany_top_in[17]:12 chany_top_in[17]:11 0.001122768 +10 chany_top_in[17]:13 chany_top_in[17]:12 0.00341 +11 chany_top_in[17]:10 chany_top_in[17]:9 0.001979911 +12 chany_top_in[17]:11 chany_top_in[17]:10 0.0045 +13 chany_top_in[17]:9 ropt_mt_inst_751:A 0.152 +14 chany_top_in[17]:32 chany_top_in[17]:31 0.006120536 +15 chany_top_in[17]:33 chany_top_in[17]:32 0.0045 +16 chany_top_in[17]:22 chany_top_in[17]:21 0.004066965 +17 chany_top_in[17]:22 chany_top_in[17]:8 0.0003035715 +18 chany_top_in[17]:23 chany_top_in[17]:22 0.0045 +19 chany_top_in[17]:25 chany_top_in[17]:24 0.0045 +20 chany_top_in[17]:24 chany_top_in[17]:23 0.03149107 +21 chany_top_in[17]:26 chany_top_in[17]:25 0.004026786 +22 chany_top_in[17]:27 chany_top_in[17]:26 0.0045 +23 chany_top_in[17]:29 chany_top_in[17]:28 0.0045 +24 chany_top_in[17]:28 chany_top_in[17]:27 0.02966965 +25 chany_top_in[17]:5 mux_right_ipin_12\/mux_l2_in_3_:A1 0.152 +26 chany_top_in[17]:4 mux_right_ipin_0\/mux_l2_in_3_:A1 0.152 +27 chany_top_in[17]:6 chany_top_in[17]:5 0.002841518 +28 chany_top_in[17]:7 chany_top_in[17]:6 0.0003035715 +29 chany_top_in[17]:8 chany_top_in[17]:7 0.004517857 +30 chany_top_in[17]:31 chany_top_in[17]:30 0.001232143 +31 chany_top_in[17]:31 chany_top_in[17]:4 0.0003035715 +32 chany_top_in[17]:30 chany_top_in[17]:29 0.0003035715 + +*END + +*D_NET prog_clk[0] 0.08511412 //LENGTH 631.600 LUMPCC 0.01069002 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 1.230 89.760 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 3.945 91.120 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 6.670 96.560 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 10.845 102.000 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 17.790 99.280 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 25.565 91.120 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 35.165 96.560 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 60.545 99.280 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 69.265 99.280 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 72.485 96.560 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 26.575 96.560 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 36.145 82.960 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.725 82.960 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.330 80.240 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.355 74.800 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 51.785 69.360 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 57.305 82.960 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 72.025 77.520 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 71.565 74.800 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 71.645 66.640 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 73.405 58.480 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 72.945 53.040 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 64.665 72.080 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 59.145 66.640 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.225 74.800 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 37.525 69.360 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 42.125 53.040 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.045 39.440 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 67.425 28.560 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 68.805 36.720 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.505 42.160 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 52.705 39.440 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 55.005 47.600 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 55.005 50.320 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 42.125 47.600 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 39.365 36.720 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 38.445 39.440 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 38.905 23.120 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 54.085 14.960 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 58.685 20.400 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 38.445 31.280 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 36.145 28.560 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 38.445 61.200 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 38.445 63.920 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 3.505 82.960 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 5.325 77.520 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 8.480 61.200 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 13.145 44.880 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 14.065 50.320 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 21.885 47.600 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 6.705 53.040 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 3.945 39.440 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 4.865 36.720 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.165 31.280 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 8.085 25.840 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 9.555 17.680 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 11.305 14.960 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 16.365 23.120 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.625 23.120 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 15.905 31.280 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 16.825 28.560 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 25.105 25.840 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 26.945 20.400 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 5.785 66.640 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 6.285 69.360 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 18.665 74.800 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 17.275 72.080 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 20.505 69.360 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 5.810 74.800 +*N prog_clk[0]:69 *C 5.810 74.800 +*N prog_clk[0]:70 *C 5.980 74.800 +*N prog_clk[0]:71 *C 5.980 74.800 +*N prog_clk[0]:72 *C 20.505 69.360 +*N prog_clk[0]:73 *C 20.240 69.360 +*N prog_clk[0]:74 *C 20.240 69.360 +*N prog_clk[0]:75 *C 20.233 69.360 +*N prog_clk[0]:76 *C 18.408 69.360 +*N prog_clk[0]:77 *C 18.400 69.418 +*N prog_clk[0]:78 *C 17.275 72.080 +*N prog_clk[0]:79 *C 17.480 72.080 +*N prog_clk[0]:80 *C 17.480 72.080 +*N prog_clk[0]:81 *C 18.400 72.080 +*N prog_clk[0]:82 *C 18.665 74.800 +*N prog_clk[0]:83 *C 18.400 74.800 +*N prog_clk[0]:84 *C 18.400 74.800 +*N prog_clk[0]:85 *C 18.393 74.800 +*N prog_clk[0]:86 *C 5.527 74.800 +*N prog_clk[0]:87 *C 5.520 74.800 +*N prog_clk[0]:88 *C 5.520 76.160 +*N prog_clk[0]:89 *C 6.285 69.360 +*N prog_clk[0]:90 *C 5.980 69.360 +*N prog_clk[0]:91 *C 5.980 69.360 +*N prog_clk[0]:92 *C 5.785 66.640 +*N prog_clk[0]:93 *C 5.520 66.640 +*N prog_clk[0]:94 *C 5.520 66.685 +*N prog_clk[0]:95 *C 5.520 68.000 +*N prog_clk[0]:96 *C 26.908 20.400 +*N prog_clk[0]:97 *C 24.885 20.400 +*N prog_clk[0]:98 *C 24.840 20.445 +*N prog_clk[0]:99 *C 25.105 25.840 +*N prog_clk[0]:100 *C 24.840 25.840 +*N prog_clk[0]:101 *C 24.840 25.840 +*N prog_clk[0]:102 *C 24.832 25.840 +*N prog_clk[0]:103 *C 16.568 25.840 +*N prog_clk[0]:104 *C 16.560 25.898 +*N prog_clk[0]:105 *C 16.825 28.560 +*N prog_clk[0]:106 *C 16.560 28.220 +*N prog_clk[0]:107 *C 16.560 28.220 +*N prog_clk[0]:108 *C 16.560 31.280 +*N prog_clk[0]:109 *C 15.905 31.280 +*N prog_clk[0]:110 *C 15.640 31.280 +*N prog_clk[0]:111 *C 15.640 31.280 +*N prog_clk[0]:112 *C 15.633 31.280 +*N prog_clk[0]:113 *C 7.625 23.120 +*N prog_clk[0]:114 *C 7.820 23.120 +*N prog_clk[0]:115 *C 16.365 23.120 +*N prog_clk[0]:116 *C 16.560 23.120 +*N prog_clk[0]:117 *C 16.560 23.120 +*N prog_clk[0]:118 *C 16.553 23.120 +*N prog_clk[0]:119 *C 11.305 14.960 +*N prog_clk[0]:120 *C 11.040 14.960 +*N prog_clk[0]:121 *C 11.040 14.960 +*N prog_clk[0]:122 *C 10.580 14.960 +*N prog_clk[0]:123 *C 9.555 17.680 +*N prog_clk[0]:124 *C 9.660 17.680 +*N prog_clk[0]:125 *C 10.580 17.680 +*N prog_clk[0]:126 *C 10.580 23.062 +*N prog_clk[0]:127 *C 10.580 23.120 +*N prog_clk[0]:128 *C 7.828 23.120 +*N prog_clk[0]:129 *C 7.820 23.120 +*N prog_clk[0]:130 *C 8.085 25.840 +*N prog_clk[0]:131 *C 7.820 26.180 +*N prog_clk[0]:132 *C 7.820 26.180 +*N prog_clk[0]:133 *C 7.820 31.280 +*N prog_clk[0]:134 *C 7.165 31.280 +*N prog_clk[0]:135 *C 7.360 31.280 +*N prog_clk[0]:136 *C 7.360 31.280 +*N prog_clk[0]:137 *C 7.360 31.280 +*N prog_clk[0]:138 *C 5.067 31.280 +*N prog_clk[0]:139 *C 5.060 31.338 +*N prog_clk[0]:140 *C 4.865 36.720 +*N prog_clk[0]:141 *C 5.060 37.060 +*N prog_clk[0]:142 *C 5.060 37.015 +*N prog_clk[0]:143 *C 4.600 37.060 +*N prog_clk[0]:144 *C 3.945 39.440 +*N prog_clk[0]:145 *C 4.140 39.100 +*N prog_clk[0]:146 *C 4.555 39.100 +*N prog_clk[0]:147 *C 4.600 39.100 +*N prog_clk[0]:148 *C 6.705 53.040 +*N prog_clk[0]:149 *C 6.440 53.040 +*N prog_clk[0]:150 *C 6.440 52.995 +*N prog_clk[0]:151 *C 21.885 47.600 +*N prog_clk[0]:152 *C 22.080 47.600 +*N prog_clk[0]:153 *C 22.080 47.645 +*N prog_clk[0]:154 *C 22.080 49.583 +*N prog_clk[0]:155 *C 22.073 49.640 +*N prog_clk[0]:156 *C 14.065 50.320 +*N prog_clk[0]:157 *C 13.800 50.320 +*N prog_clk[0]:158 *C 13.800 50.275 +*N prog_clk[0]:159 *C 13.145 44.880 +*N prog_clk[0]:160 *C 13.340 44.880 +*N prog_clk[0]:161 *C 13.340 44.925 +*N prog_clk[0]:162 *C 13.340 49.640 +*N prog_clk[0]:163 *C 13.800 49.698 +*N prog_clk[0]:164 *C 13.800 49.640 +*N prog_clk[0]:165 *C 6.448 49.640 +*N prog_clk[0]:166 *C 6.440 49.698 +*N prog_clk[0]:167 *C 6.440 51.680 +*N prog_clk[0]:168 *C 6.433 51.680 +*N prog_clk[0]:169 *C 4.607 51.680 +*N prog_clk[0]:170 *C 4.600 51.680 +*N prog_clk[0]:171 *C 4.600 61.200 +*N prog_clk[0]:172 *C 5.060 61.200 +*N prog_clk[0]:173 *C 8.480 61.200 +*N prog_clk[0]:174 *C 8.480 61.880 +*N prog_clk[0]:175 *C 5.105 61.880 +*N prog_clk[0]:176 *C 5.060 61.880 +*N prog_clk[0]:177 *C 5.060 68.000 +*N prog_clk[0]:178 *C 5.060 69.360 +*N prog_clk[0]:179 *C 5.060 76.160 +*N prog_clk[0]:180 *C 5.325 77.520 +*N prog_clk[0]:181 *C 5.060 77.520 +*N prog_clk[0]:182 *C 5.060 77.520 +*N prog_clk[0]:183 *C 5.060 82.620 +*N prog_clk[0]:184 *C 4.600 82.620 +*N prog_clk[0]:185 *C 3.505 82.960 +*N prog_clk[0]:186 *C 3.680 82.960 +*N prog_clk[0]:187 *C 3.680 82.960 +*N prog_clk[0]:188 *C 4.600 82.960 +*N prog_clk[0]:189 *C 4.600 89.760 +*N prog_clk[0]:190 *C 38.445 63.920 +*N prog_clk[0]:191 *C 38.180 63.920 +*N prog_clk[0]:192 *C 38.180 63.875 +*N prog_clk[0]:193 *C 38.445 61.200 +*N prog_clk[0]:194 *C 38.180 61.200 +*N prog_clk[0]:195 *C 38.180 61.245 +*N prog_clk[0]:196 *C 38.180 62.560 +*N prog_clk[0]:197 *C 36.145 28.560 +*N prog_clk[0]:198 *C 36.340 28.560 +*N prog_clk[0]:199 *C 36.340 28.605 +*N prog_clk[0]:200 *C 36.340 29.920 +*N prog_clk[0]:201 *C 38.445 31.280 +*N prog_clk[0]:202 *C 38.180 31.280 +*N prog_clk[0]:203 *C 38.180 31.235 +*N prog_clk[0]:204 *C 58.685 20.400 +*N prog_clk[0]:205 *C 58.420 20.400 +*N prog_clk[0]:206 *C 58.420 20.400 +*N prog_clk[0]:207 *C 58.413 20.400 +*N prog_clk[0]:208 *C 54.085 14.960 +*N prog_clk[0]:209 *C 53.820 14.960 +*N prog_clk[0]:210 *C 53.820 15.005 +*N prog_clk[0]:211 *C 53.820 20.343 +*N prog_clk[0]:212 *C 53.820 20.400 +*N prog_clk[0]:213 *C 39.100 20.400 +*N prog_clk[0]:214 *C 39.100 21.760 +*N prog_clk[0]:215 *C 38.188 21.760 +*N prog_clk[0]:216 *C 38.180 21.818 +*N prog_clk[0]:217 *C 38.867 23.120 +*N prog_clk[0]:218 *C 38.180 23.120 +*N prog_clk[0]:219 *C 38.180 22.780 +*N prog_clk[0]:220 *C 38.180 22.780 +*N prog_clk[0]:221 *C 38.180 29.920 +*N prog_clk[0]:222 *C 38.172 29.920 +*N prog_clk[0]:223 *C 36.808 29.920 +*N prog_clk[0]:224 *C 36.800 29.978 +*N prog_clk[0]:225 *C 36.800 38.080 +*N prog_clk[0]:226 *C 38.445 39.440 +*N prog_clk[0]:227 *C 38.640 39.440 +*N prog_clk[0]:228 *C 38.640 39.395 +*N prog_clk[0]:229 *C 39.328 36.720 +*N prog_clk[0]:230 *C 38.685 36.720 +*N prog_clk[0]:231 *C 38.640 36.765 +*N prog_clk[0]:232 *C 38.640 38.080 +*N prog_clk[0]:233 *C 38.633 38.080 +*N prog_clk[0]:234 *C 37.267 38.080 +*N prog_clk[0]:235 *C 37.260 38.138 +*N prog_clk[0]:236 *C 37.260 53.040 +*N prog_clk[0]:237 *C 42.125 47.600 +*N prog_clk[0]:238 *C 42.320 47.600 +*N prog_clk[0]:239 *C 42.320 47.645 +*N prog_clk[0]:240 *C 55.005 50.320 +*N prog_clk[0]:241 *C 54.740 50.320 +*N prog_clk[0]:242 *C 54.740 50.275 +*N prog_clk[0]:243 *C 55.005 47.600 +*N prog_clk[0]:244 *C 54.740 47.600 +*N prog_clk[0]:245 *C 54.740 47.645 +*N prog_clk[0]:246 *C 54.740 48.960 +*N prog_clk[0]:247 *C 54.733 48.960 +*N prog_clk[0]:248 *C 52.705 39.440 +*N prog_clk[0]:249 *C 52.900 39.440 +*N prog_clk[0]:250 *C 52.900 39.485 +*N prog_clk[0]:251 *C 66.505 42.160 +*N prog_clk[0]:252 *C 66.240 42.160 +*N prog_clk[0]:253 *C 66.240 42.115 +*N prog_clk[0]:254 *C 68.767 36.720 +*N prog_clk[0]:255 *C 68.125 36.720 +*N prog_clk[0]:256 *C 68.080 36.720 +*N prog_clk[0]:257 *C 67.425 28.560 +*N prog_clk[0]:258 *C 67.620 28.560 +*N prog_clk[0]:259 *C 67.620 28.605 +*N prog_clk[0]:260 *C 67.620 36.720 +*N prog_clk[0]:261 *C 67.620 38.080 +*N prog_clk[0]:262 *C 66.240 38.080 +*N prog_clk[0]:263 *C 66.045 39.440 +*N prog_clk[0]:264 *C 66.240 39.100 +*N prog_clk[0]:265 *C 66.240 39.100 +*N prog_clk[0]:266 *C 66.240 40.800 +*N prog_clk[0]:267 *C 66.233 40.800 +*N prog_clk[0]:268 *C 52.908 40.800 +*N prog_clk[0]:269 *C 52.900 40.800 +*N prog_clk[0]:270 *C 52.900 48.903 +*N prog_clk[0]:271 *C 52.900 48.960 +*N prog_clk[0]:272 *C 42.328 48.960 +*N prog_clk[0]:273 *C 42.320 48.903 +*N prog_clk[0]:274 *C 41.860 48.960 +*N prog_clk[0]:275 *C 42.125 53.040 +*N prog_clk[0]:276 *C 41.860 53.040 +*N prog_clk[0]:277 *C 41.860 53.040 +*N prog_clk[0]:278 *C 41.852 53.040 +*N prog_clk[0]:279 *C 37.727 53.040 +*N prog_clk[0]:280 *C 37.720 53.098 +*N prog_clk[0]:281 *C 37.720 62.560 +*N prog_clk[0]:282 *C 37.525 69.360 +*N prog_clk[0]:283 *C 37.720 69.360 +*N prog_clk[0]:284 *C 37.720 69.360 +*N prog_clk[0]:285 *C 37.712 69.360 +*N prog_clk[0]:286 *C 34.968 69.360 +*N prog_clk[0]:287 *C 34.960 69.418 +*N prog_clk[0]:288 *C 35.225 74.800 +*N prog_clk[0]:289 *C 34.960 75.140 +*N prog_clk[0]:290 *C 34.960 75.140 +*N prog_clk[0]:291 *C 59.145 66.640 +*N prog_clk[0]:292 *C 59.340 66.640 +*N prog_clk[0]:293 *C 59.340 66.685 +*N prog_clk[0]:294 *C 64.627 72.080 +*N prog_clk[0]:295 *C 63.525 72.080 +*N prog_clk[0]:296 *C 63.480 72.080 +*N prog_clk[0]:297 *C 63.473 72.080 +*N prog_clk[0]:298 *C 59.348 72.080 +*N prog_clk[0]:299 *C 59.340 72.080 +*N prog_clk[0]:300 *C 72.945 53.040 +*N prog_clk[0]:301 *C 73.140 53.040 +*N prog_clk[0]:302 *C 73.140 53.085 +*N prog_clk[0]:303 *C 73.405 58.480 +*N prog_clk[0]:304 *C 73.140 58.820 +*N prog_clk[0]:305 *C 73.140 58.820 +*N prog_clk[0]:306 *C 73.140 66.300 +*N prog_clk[0]:307 *C 72.733 66.300 +*N prog_clk[0]:308 *C 71.645 66.640 +*N prog_clk[0]:309 *C 71.760 66.640 +*N prog_clk[0]:310 *C 71.767 66.640 +*N prog_clk[0]:311 *C 72.672 66.640 +*N prog_clk[0]:312 *C 72.680 66.657 +*N prog_clk[0]:313 *C 72.680 75.140 +*N prog_clk[0]:314 *C 71.565 74.800 +*N prog_clk[0]:315 *C 71.760 75.140 +*N prog_clk[0]:316 *C 72.175 75.140 +*N prog_clk[0]:317 *C 72.220 75.140 +*N prog_clk[0]:318 *C 72.025 77.520 +*N prog_clk[0]:319 *C 72.220 77.520 +*N prog_clk[0]:320 *C 72.220 77.520 +*N prog_clk[0]:321 *C 72.213 77.520 +*N prog_clk[0]:322 *C 59.348 77.520 +*N prog_clk[0]:323 *C 59.340 77.520 +*N prog_clk[0]:324 *C 59.340 82.903 +*N prog_clk[0]:325 *C 59.333 82.960 +*N prog_clk[0]:326 *C 57.305 82.960 +*N prog_clk[0]:327 *C 57.500 82.620 +*N prog_clk[0]:328 *C 57.500 82.620 +*N prog_clk[0]:329 *C 57.500 82.960 +*N prog_clk[0]:330 *C 57.500 82.960 +*N prog_clk[0]:331 *C 51.785 69.360 +*N prog_clk[0]:332 *C 51.980 69.360 +*N prog_clk[0]:333 *C 51.980 69.360 +*N prog_clk[0]:334 *C 51.973 69.360 +*N prog_clk[0]:335 *C 46.468 69.360 +*N prog_clk[0]:336 *C 46.460 69.418 +*N prog_clk[0]:337 *C 46.355 74.800 +*N prog_clk[0]:338 *C 46.460 75.140 +*N prog_clk[0]:339 *C 46.460 75.140 +*N prog_clk[0]:340 *C 46.330 80.240 +*N prog_clk[0]:341 *C 46.460 80.240 +*N prog_clk[0]:342 *C 46.725 82.960 +*N prog_clk[0]:343 *C 46.460 82.960 +*N prog_clk[0]:344 *C 46.460 82.960 +*N prog_clk[0]:345 *C 46.460 82.960 +*N prog_clk[0]:346 *C 36.145 82.960 +*N prog_clk[0]:347 *C 36.340 82.960 +*N prog_clk[0]:348 *C 36.340 82.960 +*N prog_clk[0]:349 *C 36.340 82.960 +*N prog_clk[0]:350 *C 34.968 82.960 +*N prog_clk[0]:351 *C 34.960 82.960 +*N prog_clk[0]:352 *C 34.960 91.062 +*N prog_clk[0]:353 *C 34.953 91.120 +*N prog_clk[0]:354 *C 26.575 96.560 +*N prog_clk[0]:355 *C 26.680 96.560 +*N prog_clk[0]:356 *C 72.448 96.560 +*N prog_clk[0]:357 *C 71.805 96.560 +*N prog_clk[0]:358 *C 71.760 96.560 +*N prog_clk[0]:359 *C 71.752 96.560 +*N prog_clk[0]:360 *C 69.228 99.280 +*N prog_clk[0]:361 *C 67.205 99.280 +*N prog_clk[0]:362 *C 67.160 99.235 +*N prog_clk[0]:363 *C 67.160 96.618 +*N prog_clk[0]:364 *C 67.160 96.560 +*N prog_clk[0]:365 *C 60.518 99.258 +*N prog_clk[0]:366 *C 60.260 99.245 +*N prog_clk[0]:367 *C 60.260 98.940 +*N prog_clk[0]:368 *C 56.625 98.940 +*N prog_clk[0]:369 *C 56.580 98.895 +*N prog_clk[0]:370 *C 56.580 96.618 +*N prog_clk[0]:371 *C 56.580 96.560 +*N prog_clk[0]:372 *C 35.165 96.560 +*N prog_clk[0]:373 *C 34.960 96.560 +*N prog_clk[0]:374 *C 34.960 96.560 +*N prog_clk[0]:375 *C 34.960 96.560 +*N prog_clk[0]:376 *C 28.527 96.560 +*N prog_clk[0]:377 *C 28.520 96.502 +*N prog_clk[0]:378 *C 28.520 91.178 +*N prog_clk[0]:379 *C 28.520 91.120 +*N prog_clk[0]:380 *C 25.565 91.120 +*N prog_clk[0]:381 *C 25.760 91.120 +*N prog_clk[0]:382 *C 25.760 91.120 +*N prog_clk[0]:383 *C 25.760 91.120 +*N prog_clk[0]:384 *C 18.400 91.120 +*N prog_clk[0]:385 *C 18.400 91.800 +*N prog_clk[0]:386 *C 17.775 99.280 +*N prog_clk[0]:387 *C 17.503 99.280 +*N prog_clk[0]:388 *C 17.480 99.235 +*N prog_clk[0]:389 *C 17.480 91.858 +*N prog_clk[0]:390 *C 17.480 91.800 +*N prog_clk[0]:391 *C 10.808 102.000 +*N prog_clk[0]:392 *C 9.245 102.000 +*N prog_clk[0]:393 *C 9.200 102.000 +*N prog_clk[0]:394 *C 9.193 102.000 +*N prog_clk[0]:395 *C 7.368 102.000 +*N prog_clk[0]:396 *C 7.360 101.943 +*N prog_clk[0]:397 *C 6.670 96.560 +*N prog_clk[0]:398 *C 6.900 96.560 +*N prog_clk[0]:399 *C 6.900 96.560 +*N prog_clk[0]:400 *C 7.360 96.560 +*N prog_clk[0]:401 *C 7.360 91.858 +*N prog_clk[0]:402 *C 7.360 91.800 +*N prog_clk[0]:403 *C 4.147 91.800 +*N prog_clk[0]:404 *C 4.140 91.743 +*N prog_clk[0]:405 *C 3.945 91.120 +*N prog_clk[0]:406 *C 4.140 91.120 +*N prog_clk[0]:407 *C 4.140 91.120 +*N prog_clk[0]:408 *C 4.140 89.760 +*N prog_clk[0]:409 *C 4.133 89.760 + +*CAP +0 prog_clk[0] 0.0001625383 +1 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +2 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +3 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +6 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +7 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +8 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +9 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +10 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +11 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +12 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +13 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +14 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +15 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +16 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +18 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +19 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +21 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +22 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +23 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +24 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +25 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +26 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +27 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +28 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +29 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +30 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +32 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +33 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +35 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +37 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +38 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +39 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +40 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +41 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +42 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +43 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +44 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +45 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +46 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +47 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +49 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +50 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +51 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +52 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +54 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +55 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +57 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +58 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +59 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +60 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +61 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +63 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +64 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +65 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +66 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +67 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +68 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +69 prog_clk[0]:69 6.49201e-05 +70 prog_clk[0]:70 6.622321e-05 +71 prog_clk[0]:71 6.920717e-05 +72 prog_clk[0]:72 6.307451e-05 +73 prog_clk[0]:73 6.203876e-05 +74 prog_clk[0]:74 3.683123e-05 +75 prog_clk[0]:75 9.410023e-05 +76 prog_clk[0]:76 9.410023e-05 +77 prog_clk[0]:77 0.0001110558 +78 prog_clk[0]:78 4.527062e-05 +79 prog_clk[0]:79 4.650384e-05 +80 prog_clk[0]:80 9.234135e-05 +81 prog_clk[0]:81 0.0003340433 +82 prog_clk[0]:82 6.277869e-05 +83 prog_clk[0]:83 6.254762e-05 +84 prog_clk[0]:84 0.0002029842 +85 prog_clk[0]:85 0.000724794 +86 prog_clk[0]:86 0.000724794 +87 prog_clk[0]:87 0.0001377576 +88 prog_clk[0]:88 0.0001320305 +89 prog_clk[0]:89 5.837425e-05 +90 prog_clk[0]:90 6.089611e-05 +91 prog_clk[0]:91 8.884785e-05 +92 prog_clk[0]:92 6.49633e-05 +93 prog_clk[0]:93 5.974407e-05 +94 prog_clk[0]:94 0.0001009941 +95 prog_clk[0]:95 0.0001267847 +96 prog_clk[0]:96 0.0001670674 +97 prog_clk[0]:97 0.0001670674 +98 prog_clk[0]:98 0.0002825718 +99 prog_clk[0]:99 6.214466e-05 +100 prog_clk[0]:100 5.604648e-05 +101 prog_clk[0]:101 0.0003162435 +102 prog_clk[0]:102 0.0002660867 +103 prog_clk[0]:103 0.0002660867 +104 prog_clk[0]:104 0.0001541524 +105 prog_clk[0]:105 6.925215e-05 +106 prog_clk[0]:106 6.779343e-05 +107 prog_clk[0]:107 0.0003653573 +108 prog_clk[0]:108 0.0002385682 +109 prog_clk[0]:109 5.781094e-05 +110 prog_clk[0]:110 5.706307e-05 +111 prog_clk[0]:111 9.399129e-05 +112 prog_clk[0]:112 0.0003066475 +113 prog_clk[0]:113 5.934351e-05 +114 prog_clk[0]:114 5.452086e-05 +115 prog_clk[0]:115 6.279143e-05 +116 prog_clk[0]:116 6.372595e-05 +117 prog_clk[0]:117 3.298141e-05 +118 prog_clk[0]:118 0.0003249776 +119 prog_clk[0]:119 5.87953e-05 +120 prog_clk[0]:120 5.417837e-05 +121 prog_clk[0]:121 6.583223e-05 +122 prog_clk[0]:122 0.0001754396 +123 prog_clk[0]:123 2.878717e-05 +124 prog_clk[0]:124 8.990828e-05 +125 prog_clk[0]:125 0.0004927439 +126 prog_clk[0]:126 0.00029321 +127 prog_clk[0]:127 0.0004743048 +128 prog_clk[0]:128 0.0001493273 +129 prog_clk[0]:129 0.0001817293 +130 prog_clk[0]:130 6.171421e-05 +131 prog_clk[0]:131 6.469621e-05 +132 prog_clk[0]:132 0.0004558932 +133 prog_clk[0]:133 0.0003107578 +134 prog_clk[0]:134 5.75591e-05 +135 prog_clk[0]:135 5.58585e-05 +136 prog_clk[0]:136 7.068072e-05 +137 prog_clk[0]:137 0.0004487165 +138 prog_clk[0]:138 0.000142069 +139 prog_clk[0]:139 0.0003140346 +140 prog_clk[0]:140 6.693395e-05 +141 prog_clk[0]:141 6.934005e-05 +142 prog_clk[0]:142 0.0003485557 +143 prog_clk[0]:143 0.0001520927 +144 prog_clk[0]:144 5.474061e-05 +145 prog_clk[0]:145 6.687288e-05 +146 prog_clk[0]:146 4.248176e-05 +147 prog_clk[0]:147 0.0006874355 +148 prog_clk[0]:148 5.669276e-05 +149 prog_clk[0]:149 5.945711e-05 +150 prog_clk[0]:150 6.345494e-05 +151 prog_clk[0]:151 4.925628e-05 +152 prog_clk[0]:152 5.477008e-05 +153 prog_clk[0]:153 0.0001265183 +154 prog_clk[0]:154 0.0001265183 +155 prog_clk[0]:155 0.0005256409 +156 prog_clk[0]:156 6.144455e-05 +157 prog_clk[0]:157 6.319831e-05 +158 prog_clk[0]:158 6.277363e-05 +159 prog_clk[0]:159 5.647624e-05 +160 prog_clk[0]:160 5.995119e-05 +161 prog_clk[0]:161 0.0002675634 +162 prog_clk[0]:162 0.0003027912 +163 prog_clk[0]:163 9.800139e-05 +164 prog_clk[0]:164 0.0010101 +165 prog_clk[0]:165 0.000484459 +166 prog_clk[0]:166 9.288635e-05 +167 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1.722338e-05 +554 prog_clk[0]:147 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.345454e-06 +555 prog_clk[0]:174 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.243204e-06 +556 prog_clk[0]:171 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.981411e-05 +557 prog_clk[0]:235 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.009467e-05 +558 prog_clk[0]:277 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.431386e-09 +559 prog_clk[0]:236 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.009467e-05 +560 prog_clk[0]:274 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.431386e-09 +561 prog_clk[0]:168 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.295352e-05 +562 prog_clk[0]:170 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001712856 +563 prog_clk[0]:170 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.236308e-05 +564 prog_clk[0]:169 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.295352e-05 +565 prog_clk[0]:335 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 1.038954e-05 +566 prog_clk[0]:334 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 1.038954e-05 +567 prog_clk[0]:76 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 1.605151e-05 +568 prog_clk[0]:75 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 1.605151e-05 +569 prog_clk[0]:312 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 2.4216e-06 +570 prog_clk[0]:147 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001712856 +571 prog_clk[0]:171 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.236308e-05 +572 prog_clk[0]:313 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 2.4216e-06 +573 prog_clk[0]:371 ropt_net_168:7 0.000138246 +574 prog_clk[0]:375 ropt_net_168:6 0.000138246 +575 prog_clk[0]:364 chany_top_out[0]:9 0.0001897589 +576 prog_clk[0]:368 chany_top_out[0]:4 0.0001280135 +577 prog_clk[0]:371 chany_top_out[0]:8 0.0001897589 +578 prog_clk[0]:367 chany_top_out[0]:5 0.0001280135 + +*RES +0 prog_clk[0] prog_clk[0]:409 0.000454725 +1 prog_clk[0]:273 prog_clk[0]:272 0.00341 +2 prog_clk[0]:273 prog_clk[0]:239 0.001122768 +3 prog_clk[0]:272 prog_clk[0]:271 0.001656358 +4 prog_clk[0]:284 prog_clk[0]:283 0.0045 +5 prog_clk[0]:284 prog_clk[0]:281 0.006071429 +6 prog_clk[0]:285 prog_clk[0]:284 0.00341 +7 prog_clk[0]:287 prog_clk[0]:286 0.00341 +8 prog_clk[0]:286 prog_clk[0]:285 0.00043005 +9 prog_clk[0]:363 prog_clk[0]:362 0.002337054 +10 prog_clk[0]:364 prog_clk[0]:363 0.00341 +11 prog_clk[0]:364 prog_clk[0]:359 0.0007194916 +12 prog_clk[0]:361 prog_clk[0]:360 0.001805804 +13 prog_clk[0]:362 prog_clk[0]:361 0.0045 +14 prog_clk[0]:360 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +15 prog_clk[0]:84 prog_clk[0]:83 0.0045 +16 prog_clk[0]:84 prog_clk[0]:81 0.002428572 +17 prog_clk[0]:85 prog_clk[0]:84 0.00341 +18 prog_clk[0]:87 prog_clk[0]:86 0.00341 +19 prog_clk[0]:87 prog_clk[0]:71 0.0004107143 +20 prog_clk[0]:86 prog_clk[0]:85 0.002015517 +21 prog_clk[0]:139 prog_clk[0]:138 0.00341 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prog_clk[0]:222 0.00021385 +44 prog_clk[0]:167 prog_clk[0]:166 0.001770089 +45 prog_clk[0]:167 prog_clk[0]:150 0.001174107 +46 prog_clk[0]:168 prog_clk[0]:167 0.00341 +47 prog_clk[0]:170 prog_clk[0]:169 0.00341 +48 prog_clk[0]:170 prog_clk[0]:147 0.01123214 +49 prog_clk[0]:169 prog_clk[0]:168 0.0002859166 +50 prog_clk[0]:338 prog_clk[0]:337 0.0001847826 +51 prog_clk[0]:339 prog_clk[0]:338 0.0045 +52 prog_clk[0]:339 prog_clk[0]:336 0.005109375 +53 prog_clk[0]:337 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +54 prog_clk[0]:232 prog_clk[0]:231 0.001174107 +55 prog_clk[0]:232 prog_clk[0]:228 0.001174107 +56 prog_clk[0]:233 prog_clk[0]:232 0.00341 +57 prog_clk[0]:235 prog_clk[0]:234 0.00341 +58 prog_clk[0]:235 prog_clk[0]:225 0.0004107143 +59 prog_clk[0]:234 prog_clk[0]:233 0.00021385 +60 prog_clk[0]:111 prog_clk[0]:110 0.0045 +61 prog_clk[0]:111 prog_clk[0]:108 0.0008214285 +62 prog_clk[0]:112 prog_clk[0]:111 0.00341 +63 prog_clk[0]:136 prog_clk[0]:135 0.0045 +64 prog_clk[0]:136 prog_clk[0]:133 0.0004107143 +65 prog_clk[0]:137 prog_clk[0]:136 0.00341 +66 prog_clk[0]:137 prog_clk[0]:112 0.001296025 +67 prog_clk[0]:166 prog_clk[0]:165 0.00341 +68 prog_clk[0]:165 prog_clk[0]:164 0.001151892 +69 prog_clk[0]:163 prog_clk[0]:162 0.0004107143 +70 prog_clk[0]:163 prog_clk[0]:158 0.000515625 +71 prog_clk[0]:164 prog_clk[0]:163 0.00341 +72 prog_clk[0]:164 prog_clk[0]:155 0.001296025 +73 prog_clk[0]:352 prog_clk[0]:351 0.007234375 +74 prog_clk[0]:353 prog_clk[0]:352 0.00341 +75 prog_clk[0]:277 prog_clk[0]:276 0.0045 +76 prog_clk[0]:277 prog_clk[0]:274 0.003642858 +77 prog_clk[0]:278 prog_clk[0]:277 0.00341 +78 prog_clk[0]:280 prog_clk[0]:279 0.00341 +79 prog_clk[0]:280 prog_clk[0]:236 0.0004107143 +80 prog_clk[0]:279 prog_clk[0]:278 0.00064625 +81 prog_clk[0]:344 prog_clk[0]:343 0.0045 +82 prog_clk[0]:344 prog_clk[0]:341 0.002428572 +83 prog_clk[0]:345 prog_clk[0]:344 0.00341 +84 prog_clk[0]:345 prog_clk[0]:330 0.0017296 +85 prog_clk[0]:378 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0.0045 +106 prog_clk[0]:341 prog_clk[0]:339 0.004553572 +107 prog_clk[0]:372 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +108 prog_clk[0]:373 prog_clk[0]:372 0.0001114131 +109 prog_clk[0]:374 prog_clk[0]:373 0.0045 +110 prog_clk[0]:375 prog_clk[0]:374 0.00341 +111 prog_clk[0]:375 prog_clk[0]:371 0.003387133 +112 prog_clk[0]:324 prog_clk[0]:323 0.004805803 +113 prog_clk[0]:325 prog_clk[0]:324 0.00341 +114 prog_clk[0]:401 prog_clk[0]:400 0.004198661 +115 prog_clk[0]:402 prog_clk[0]:401 0.00341 +116 prog_clk[0]:402 prog_clk[0]:390 0.001585467 +117 prog_clk[0]:351 prog_clk[0]:350 0.00341 +118 prog_clk[0]:351 prog_clk[0]:290 0.006982143 +119 prog_clk[0]:350 prog_clk[0]:349 0.000215025 +120 prog_clk[0]:336 prog_clk[0]:335 0.00341 +121 prog_clk[0]:335 prog_clk[0]:334 0.0008624499 +122 prog_clk[0]:333 prog_clk[0]:332 0.0045 +123 prog_clk[0]:334 prog_clk[0]:333 0.00341 +124 prog_clk[0]:332 prog_clk[0]:331 0.0001059783 +125 prog_clk[0]:331 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +126 prog_clk[0]:126 prog_clk[0]:125 0.004805804 +127 prog_clk[0]:127 prog_clk[0]:126 0.00341 +128 prog_clk[0]:127 prog_clk[0]:118 0.0009356916 +129 prog_clk[0]:90 prog_clk[0]:89 0.0001657609 +130 prog_clk[0]:91 prog_clk[0]:90 0.0045 +131 prog_clk[0]:89 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +132 prog_clk[0]:93 prog_clk[0]:92 0.0001440217 +133 prog_clk[0]:94 prog_clk[0]:93 0.0045 +134 prog_clk[0]:92 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +135 prog_clk[0]:175 prog_clk[0]:174 0.003013393 +136 prog_clk[0]:176 prog_clk[0]:175 0.0045 +137 prog_clk[0]:176 prog_clk[0]:172 0.0006071429 +138 prog_clk[0]:173 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +139 prog_clk[0]:186 prog_clk[0]:185 9.51087e-05 +140 prog_clk[0]:187 prog_clk[0]:186 0.0045 +141 prog_clk[0]:185 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +142 prog_clk[0]:406 prog_clk[0]:405 0.0001059783 +143 prog_clk[0]:407 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prog_clk[0]:248 0.0001059783 +162 prog_clk[0]:250 prog_clk[0]:249 0.0045 +163 prog_clk[0]:248 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +164 prog_clk[0]:255 prog_clk[0]:254 0.0005736608 +165 prog_clk[0]:256 prog_clk[0]:255 0.0045 +166 prog_clk[0]:254 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +167 prog_clk[0]:202 prog_clk[0]:201 0.0001440218 +168 prog_clk[0]:203 prog_clk[0]:202 0.0045 +169 prog_clk[0]:201 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +170 prog_clk[0]:106 prog_clk[0]:105 0.0001847826 +171 prog_clk[0]:107 prog_clk[0]:106 0.0045 +172 prog_clk[0]:107 prog_clk[0]:104 0.002073661 +173 prog_clk[0]:105 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +174 prog_clk[0]:110 prog_clk[0]:109 0.0001440218 +175 prog_clk[0]:109 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +176 prog_clk[0]:100 prog_clk[0]:99 0.0001440218 +177 prog_clk[0]:99 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +178 prog_clk[0]:264 prog_clk[0]:263 0.0001847826 +179 prog_clk[0]:265 prog_clk[0]:264 0.0045 +180 prog_clk[0]:265 prog_clk[0]:262 0.0009107144 +181 prog_clk[0]:263 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +182 prog_clk[0]:292 prog_clk[0]:291 0.0001059783 +183 prog_clk[0]:293 prog_clk[0]:292 0.0045 +184 prog_clk[0]:291 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +185 prog_clk[0]:241 prog_clk[0]:240 0.0001440218 +186 prog_clk[0]:242 prog_clk[0]:241 0.0045 +187 prog_clk[0]:240 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +188 prog_clk[0]:77 prog_clk[0]:76 0.00341 +189 prog_clk[0]:76 prog_clk[0]:75 0.0002859167 +190 prog_clk[0]:74 prog_clk[0]:73 0.0045 +191 prog_clk[0]:75 prog_clk[0]:74 0.00341 +192 prog_clk[0]:73 prog_clk[0]:72 0.0001440218 +193 prog_clk[0]:72 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +194 prog_clk[0]:70 prog_clk[0]:69 9.239131e-05 +195 prog_clk[0]:71 prog_clk[0]:70 0.0045 +196 prog_clk[0]:69 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +197 prog_clk[0]:181 prog_clk[0]:180 0.0001440218 +198 prog_clk[0]:182 prog_clk[0]:181 0.0045 +199 prog_clk[0]:182 prog_clk[0]:179 0.001214286 +200 prog_clk[0]:180 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +201 prog_clk[0]:319 prog_clk[0]:318 0.0001059783 +202 prog_clk[0]:318 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +203 prog_clk[0]:83 prog_clk[0]:82 0.0001440218 +204 prog_clk[0]:82 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +205 prog_clk[0]:316 prog_clk[0]:315 0.0003705358 +206 prog_clk[0]:317 prog_clk[0]:316 0.0045 +207 prog_clk[0]:317 prog_clk[0]:313 0.0004107143 +208 prog_clk[0]:314 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +209 prog_clk[0]:79 prog_clk[0]:78 0.0001114131 +210 prog_clk[0]:80 prog_clk[0]:79 0.0045 +211 prog_clk[0]:78 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +212 prog_clk[0]:299 prog_clk[0]:298 0.00341 +213 prog_clk[0]:299 prog_clk[0]:293 0.004816964 +214 prog_clk[0]:298 prog_clk[0]:297 0.00064625 +215 prog_clk[0]:296 prog_clk[0]:295 0.0045 +216 prog_clk[0]:297 prog_clk[0]:296 0.00341 +217 prog_clk[0]:295 prog_clk[0]:294 0.000984375 +218 prog_clk[0]:294 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +219 prog_clk[0]:377 prog_clk[0]:376 0.00341 +220 prog_clk[0]:377 prog_clk[0]:355 0.001642857 +221 prog_clk[0]:376 prog_clk[0]:375 0.001007758 +222 prog_clk[0]:244 prog_clk[0]:243 0.0001440218 +223 prog_clk[0]:245 prog_clk[0]:244 0.0045 +224 prog_clk[0]:243 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +225 prog_clk[0]:386 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +226 prog_clk[0]:387 prog_clk[0]:386 0.0001480978 +227 prog_clk[0]:388 prog_clk[0]:387 0.0045 +228 prog_clk[0]:389 prog_clk[0]:388 0.006587054 +229 prog_clk[0]:390 prog_clk[0]:389 0.00341 +230 prog_clk[0]:390 prog_clk[0]:385 0.0001441333 +231 prog_clk[0]:276 prog_clk[0]:275 0.0001440218 +232 prog_clk[0]:275 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +233 prog_clk[0]:238 prog_clk[0]:237 0.0001059783 +234 prog_clk[0]:239 prog_clk[0]:238 0.0045 +235 prog_clk[0]:237 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +236 prog_clk[0]:343 prog_clk[0]:342 0.0001440218 +237 prog_clk[0]:342 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +238 prog_clk[0]:227 prog_clk[0]:226 0.0001059783 +239 prog_clk[0]:228 prog_clk[0]:227 0.0045 +240 prog_clk[0]:226 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +241 prog_clk[0]:382 prog_clk[0]:381 0.0045 +242 prog_clk[0]:383 prog_clk[0]:382 0.00341 +243 prog_clk[0]:383 prog_clk[0]:379 0.0004324 +244 prog_clk[0]:381 prog_clk[0]:380 0.0001059783 +245 prog_clk[0]:380 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +246 prog_clk[0]:198 prog_clk[0]:197 0.0001059783 +247 prog_clk[0]:199 prog_clk[0]:198 0.0045 +248 prog_clk[0]:197 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +249 prog_clk[0]:348 prog_clk[0]:347 0.0045 +250 prog_clk[0]:349 prog_clk[0]:348 0.00341 +251 prog_clk[0]:349 prog_clk[0]:345 0.001585467 +252 prog_clk[0]:347 prog_clk[0]:346 0.0001059783 +253 prog_clk[0]:346 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +254 prog_clk[0]:149 prog_clk[0]:148 0.0001440218 +255 prog_clk[0]:150 prog_clk[0]:149 0.0045 +256 prog_clk[0]:148 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +257 prog_clk[0]:312 prog_clk[0]:311 0.00341 +258 prog_clk[0]:312 prog_clk[0]:307 0.0002127976 +259 prog_clk[0]:311 prog_clk[0]:310 0.0001417833 +260 prog_clk[0]:309 prog_clk[0]:308 0.0045 +261 prog_clk[0]:310 prog_clk[0]:309 0.00341 +262 prog_clk[0]:308 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +263 prog_clk[0]:157 prog_clk[0]:156 0.0001440218 +264 prog_clk[0]:158 prog_clk[0]:157 0.0045 +265 prog_clk[0]:156 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +266 prog_clk[0]:304 prog_clk[0]:303 0.0001847826 +267 prog_clk[0]:305 prog_clk[0]:304 0.0045 +268 prog_clk[0]:305 prog_clk[0]:302 0.005120536 +269 prog_clk[0]:303 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +270 prog_clk[0]:154 prog_clk[0]:153 0.001729911 +271 prog_clk[0]:155 prog_clk[0]:154 0.00341 +272 prog_clk[0]:152 prog_clk[0]:151 0.0001059783 +273 prog_clk[0]:153 prog_clk[0]:152 0.0045 +274 prog_clk[0]:151 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +275 prog_clk[0]:270 prog_clk[0]:269 0.007234375 +276 prog_clk[0]:271 prog_clk[0]:270 0.00341 +277 prog_clk[0]:271 prog_clk[0]:247 0.0002870917 +278 prog_clk[0]:301 prog_clk[0]:300 0.0001059783 +279 prog_clk[0]:302 prog_clk[0]:301 0.0045 +280 prog_clk[0]:300 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +281 prog_clk[0]:146 prog_clk[0]:145 0.0003705358 +282 prog_clk[0]:147 prog_clk[0]:146 0.0045 +283 prog_clk[0]:147 prog_clk[0]:143 0.001821428 +284 prog_clk[0]:144 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +285 prog_clk[0]:252 prog_clk[0]:251 0.0001440218 +286 prog_clk[0]:253 prog_clk[0]:252 0.0045 +287 prog_clk[0]:251 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +288 prog_clk[0]:141 prog_clk[0]:140 0.0001847826 +289 prog_clk[0]:142 prog_clk[0]:141 0.0045 +290 prog_clk[0]:142 prog_clk[0]:139 0.005069196 +291 prog_clk[0]:140 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +292 prog_clk[0]:114 prog_clk[0]:113 0.0001059783 +293 prog_clk[0]:113 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +294 prog_clk[0]:135 prog_clk[0]:134 0.0001059783 +295 prog_clk[0]:134 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +296 prog_clk[0]:230 prog_clk[0]:229 0.0005736608 +297 prog_clk[0]:231 prog_clk[0]:230 0.0045 +298 prog_clk[0]:229 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +299 prog_clk[0]:160 prog_clk[0]:159 0.0001059783 +300 prog_clk[0]:161 prog_clk[0]:160 0.0045 +301 prog_clk[0]:159 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +302 prog_clk[0]:358 prog_clk[0]:357 0.0045 +303 prog_clk[0]:359 prog_clk[0]:358 0.00341 +304 prog_clk[0]:357 prog_clk[0]:356 0.0005736608 +305 prog_clk[0]:356 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +306 prog_clk[0]:329 prog_clk[0]:328 0.0001634615 +307 prog_clk[0]:330 prog_clk[0]:329 0.00341 +308 prog_clk[0]:330 prog_clk[0]:325 0.0002870917 +309 prog_clk[0]:327 prog_clk[0]:326 0.0001847826 +310 prog_clk[0]:328 prog_clk[0]:327 0.0045 +311 prog_clk[0]:326 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +312 prog_clk[0]:289 prog_clk[0]:288 0.0001847826 +313 prog_clk[0]:290 prog_clk[0]:289 0.0045 +314 prog_clk[0]:290 prog_clk[0]:287 0.005109375 +315 prog_clk[0]:288 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +316 prog_clk[0]:219 prog_clk[0]:218 0.0003035715 +317 prog_clk[0]:220 prog_clk[0]:219 0.0045 +318 prog_clk[0]:220 prog_clk[0]:216 0.0008593751 +319 prog_clk[0]:217 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +320 prog_clk[0]:283 prog_clk[0]:282 0.0001059783 +321 prog_clk[0]:282 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +322 prog_clk[0]:206 prog_clk[0]:205 0.0045 +323 prog_clk[0]:207 prog_clk[0]:206 0.00341 +324 prog_clk[0]:205 prog_clk[0]:204 0.0001440218 +325 prog_clk[0]:204 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +326 prog_clk[0]:194 prog_clk[0]:193 0.0001440218 +327 prog_clk[0]:195 prog_clk[0]:194 0.0045 +328 prog_clk[0]:193 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +329 prog_clk[0]:211 prog_clk[0]:210 0.004765625 +330 prog_clk[0]:212 prog_clk[0]:211 0.00341 +331 prog_clk[0]:212 prog_clk[0]:207 0.0007194917 +332 prog_clk[0]:209 prog_clk[0]:208 0.0001440218 +333 prog_clk[0]:210 prog_clk[0]:209 0.0045 +334 prog_clk[0]:208 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +335 prog_clk[0]:191 prog_clk[0]:190 0.0001440218 +336 prog_clk[0]:192 prog_clk[0]:191 0.0045 +337 prog_clk[0]:190 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +338 prog_clk[0]:97 prog_clk[0]:96 0.001805804 +339 prog_clk[0]:98 prog_clk[0]:97 0.0045 +340 prog_clk[0]:96 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +341 prog_clk[0]:258 prog_clk[0]:257 0.0001059783 +342 prog_clk[0]:259 prog_clk[0]:258 0.0045 +343 prog_clk[0]:257 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +344 prog_clk[0]:117 prog_clk[0]:116 0.0045 +345 prog_clk[0]:118 prog_clk[0]:117 0.00341 +346 prog_clk[0]:116 prog_clk[0]:115 0.0001059783 +347 prog_clk[0]:115 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +348 prog_clk[0]:120 prog_clk[0]:119 0.0001440218 +349 prog_clk[0]:121 prog_clk[0]:120 0.0045 +350 prog_clk[0]:119 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +351 prog_clk[0]:408 prog_clk[0]:407 0.001214286 +352 prog_clk[0]:408 prog_clk[0]:189 0.0004107143 +353 prog_clk[0]:409 prog_clk[0]:408 0.00341 +354 prog_clk[0]:216 prog_clk[0]:215 0.00341 +355 prog_clk[0]:215 prog_clk[0]:214 0.0001429583 +356 prog_clk[0]:354 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +357 prog_clk[0]:355 prog_clk[0]:354 0.0045 +358 prog_clk[0]:145 prog_clk[0]:144 0.0003035715 +359 prog_clk[0]:174 prog_clk[0]:173 0.000607143 +360 prog_clk[0]:218 prog_clk[0]:217 0.0006138394 +361 prog_clk[0]:367 prog_clk[0]:366 0.0002723215 +362 prog_clk[0]:366 prog_clk[0]:365 0.0001739865 +363 prog_clk[0]:315 prog_clk[0]:314 0.0003035715 +364 prog_clk[0]:188 prog_clk[0]:187 0.0008214285 +365 prog_clk[0]:188 prog_clk[0]:184 0.0003035715 +366 prog_clk[0]:189 prog_clk[0]:188 0.006071429 +367 prog_clk[0]:143 prog_clk[0]:142 0.0004107143 +368 prog_clk[0]:171 prog_clk[0]:170 0.008500001 +369 prog_clk[0]:172 prog_clk[0]:171 0.0004107143 +370 prog_clk[0]:184 prog_clk[0]:183 0.0004107143 +371 prog_clk[0]:183 prog_clk[0]:182 0.004553571 +372 prog_clk[0]:177 prog_clk[0]:176 0.005464286 +373 prog_clk[0]:177 prog_clk[0]:95 0.0004107143 +374 prog_clk[0]:178 prog_clk[0]:177 0.001214286 +375 prog_clk[0]:178 prog_clk[0]:91 0.0008214285 +376 prog_clk[0]:179 prog_clk[0]:178 0.006071429 +377 prog_clk[0]:179 prog_clk[0]:88 0.0004107143 +378 prog_clk[0]:95 prog_clk[0]:94 0.001174107 +379 prog_clk[0]:88 prog_clk[0]:87 0.001214286 +380 prog_clk[0]:400 prog_clk[0]:399 0.0004107143 +381 prog_clk[0]:400 prog_clk[0]:396 0.004805804 +382 prog_clk[0]:133 prog_clk[0]:132 0.004553571 +383 prog_clk[0]:125 prog_clk[0]:124 0.0008214285 +384 prog_clk[0]:125 prog_clk[0]:122 0.002428572 +385 prog_clk[0]:122 prog_clk[0]:121 0.0004107143 +386 prog_clk[0]:162 prog_clk[0]:161 0.004209822 +387 prog_clk[0]:108 prog_clk[0]:107 0.002732143 +388 prog_clk[0]:81 prog_clk[0]:80 0.0008214286 +389 prog_clk[0]:81 prog_clk[0]:77 0.002377232 +390 prog_clk[0]:200 prog_clk[0]:199 0.001174107 +391 prog_clk[0]:225 prog_clk[0]:224 0.007234375 +392 prog_clk[0]:236 prog_clk[0]:235 0.0133058 +393 prog_clk[0]:281 prog_clk[0]:280 0.008448661 +394 prog_clk[0]:281 prog_clk[0]:196 0.0004107143 +395 prog_clk[0]:196 prog_clk[0]:195 0.001174107 +396 prog_clk[0]:196 prog_clk[0]:192 0.001174107 +397 prog_clk[0]:274 prog_clk[0]:273 0.0004107143 +398 prog_clk[0]:262 prog_clk[0]:261 0.001232143 +399 prog_clk[0]:261 prog_clk[0]:260 0.001214286 +400 prog_clk[0]:260 prog_clk[0]:259 0.007245536 +401 prog_clk[0]:260 prog_clk[0]:256 0.0004107143 +402 prog_clk[0]:313 prog_clk[0]:312 0.00757366 +403 prog_clk[0]:307 prog_clk[0]:306 0.0003638393 +404 prog_clk[0]:306 prog_clk[0]:305 0.006678571 +405 prog_clk[0]:385 prog_clk[0]:384 0.0001065333 +406 prog_clk[0]:384 prog_clk[0]:383 0.001153067 +407 prog_clk[0]:214 prog_clk[0]:213 0.0002130667 +408 prog_clk[0]:213 prog_clk[0]:212 0.002306133 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001872961 //LENGTH 14.615 LUMPCC 0.0006517958 DR + +*CONN +*I mux_right_ipin_9\/mux_l3_in_1_:X O *L 0 *C 63.195 26.520 +*I mux_right_ipin_9\/mux_l4_in_0_:A0 I *L 0.001631 *C 54.610 31.620 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 54.648 31.620 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 61.135 31.620 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 61.180 31.575 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 61.180 26.565 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 61.225 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 63.158 26.520 + +*CAP +0 mux_right_ipin_9\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_9\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002563083 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002563083 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002127231 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002127231 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.000140551 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.000140551 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_bottom_in[16]:44 7.084155e-05 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_bottom_in[16]:43 7.084155e-05 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 optlc_net_133:36 0.0002550563 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 optlc_net_133:37 0.0002550563 + +*RES +0 mux_right_ipin_9\/mux_l3_in_1_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.001725447 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.005792411 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_9\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006086596 //LENGTH 4.265 LUMPCC 7.421224e-05 DR + +*CONN +*I mux_right_ipin_12\/mux_l2_in_3_:X O *L 0 *C 23.635 18.020 +*I mux_right_ipin_12\/mux_l3_in_1_:A0 I *L 0.001631 *C 22.830 20.740 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 22.867 20.740 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 23.415 20.740 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 23.460 20.695 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 23.460 18.065 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 23.460 18.020 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 23.635 18.020 + +*CAP +0 mux_right_ipin_12\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_12\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.564103e-05 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.564103e-05 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000142482 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000142482 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.91816e-05 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.701984e-05 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_7_sram[3]:4 1.248192e-06 +9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_7_sram[3]:5 1.248192e-06 +10 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size10_7_sram[3]:7 3.585792e-05 +11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size10_7_sram[3]:6 3.585792e-05 + +*RES +0 mux_right_ipin_12\/mux_l2_in_3_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_12\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001132881 //LENGTH 9.340 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_13\/mux_l2_in_2_:X O *L 0 *C 56.755 18.360 +*I mux_right_ipin_13\/mux_l3_in_1_:A1 I *L 0.00198 *C 50.045 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 50.083 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 55.615 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 55.660 20.015 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 55.660 18.405 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 55.705 18.360 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 56.718 18.360 + +*CAP +0 mux_right_ipin_13\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_13\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003506966 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003506966 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001175509 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001175509 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.719293e-05 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.719293e-05 + +*RES +0 mux_right_ipin_13\/mux_l2_in_2_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_13\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.004939732 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003685873 //LENGTH 2.475 LUMPCC 0.0001857735 DR + +*CONN +*I mux_right_ipin_2\/mux_l2_in_1_:X O *L 0 *C 16.735 88.060 +*I mux_right_ipin_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 14.550 88.060 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 14.588 88.060 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 16.698 88.060 + +*CAP +0 mux_right_ipin_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.040689e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.040689e-05 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.288674e-05 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 9.288674e-05 + +*RES +0 mux_right_ipin_2\/mux_l2_in_1_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_2\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001106905 //LENGTH 8.230 LUMPCC 0.0002162717 DR + +*CONN +*I mux_right_ipin_3\/mux_l2_in_2_:X O *L 0 *C 25.125 61.880 +*I mux_right_ipin_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 22.905 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.943 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 23.460 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.460 66.640 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 24.795 66.640 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 24.840 66.595 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 24.840 61.925 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 24.840 61.880 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 25.125 61.880 + +*CAP +0 mux_right_ipin_3\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_3\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.789328e-05 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.388811e-05 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.497237e-05 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.897754e-05 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002393593 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002393593 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 6.285159e-05 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.133198e-05 +10 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chany_top_in[2]:28 8.46667e-06 +11 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chany_top_in[2]:29 4.518231e-05 +12 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chany_top_in[2]:25 4.518231e-05 +13 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chany_top_in[2]:29 8.46667e-06 +14 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.360476e-06 +15 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.112637e-05 +16 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.360476e-06 +17 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.112637e-05 + +*RES +0 mux_right_ipin_3\/mux_l2_in_2_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_3\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001191964 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.004169643 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001548913 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004620536 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035714 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009922376 //LENGTH 8.615 LUMPCC 0.0001337872 DR + +*CONN +*I mux_right_ipin_7\/mux_l1_in_0_:X O *L 0 *C 60.085 78.200 +*I mux_right_ipin_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 60.820 85.340 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 60.783 85.340 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.305 85.340 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 60.260 85.295 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 60.260 78.245 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 60.260 78.200 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 60.085 78.200 + +*CAP +0 mux_right_ipin_7\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_7\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.420151e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.420151e-05 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003176803 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003176803 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.71845e-05 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.550228e-05 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:324 6.68936e-05 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:323 6.68936e-05 + +*RES +0 mux_right_ipin_7\/mux_l1_in_0_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_7\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294643 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003904931 //LENGTH 3.395 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_10\/mux_l2_in_1_:X O *L 0 *C 14.895 33.660 +*I mux_right_ipin_10\/mux_l3_in_0_:A0 I *L 0.001631 *C 11.790 33.660 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 11.828 33.660 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 14.857 33.660 + +*CAP +0 mux_right_ipin_10\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_10\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001942466 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001942466 + +*RES +0 mux_right_ipin_10\/mux_l2_in_1_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_10\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002705358 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009047516 //LENGTH 7.600 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_11\/mux_l2_in_0_:X O *L 0 *C 15.355 53.380 +*I mux_right_ipin_11\/mux_l3_in_0_:A1 I *L 0.00198 *C 11.405 56.100 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 11.443 56.100 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 14.675 56.100 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 14.720 56.055 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 14.720 53.425 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 14.765 53.380 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 15.318 53.380 + +*CAP +0 mux_right_ipin_11\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_11\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002323143 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002323143 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001522309 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001522309 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.683057e-05 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.683057e-05 + +*RES +0 mux_right_ipin_11\/mux_l2_in_0_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_11\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002886161 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008346956 //LENGTH 6.415 LUMPCC 0.0001968741 DR + +*CONN +*I mux_right_ipin_14\/mux_l2_in_1_:X O *L 0 *C 34.785 47.260 +*I mux_right_ipin_14\/mux_l3_in_0_:A0 I *L 0.001631 *C 37.550 44.540 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 37.513 44.540 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 36.385 44.540 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 36.340 44.585 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 36.340 47.215 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 36.295 47.260 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 34.823 47.260 + +*CAP +0 mux_right_ipin_14\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_14\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.190107e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.190107e-05 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001739331 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001739331 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.207653e-05 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.207653e-05 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size8_6_sram[1]:11 5.861882e-05 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size8_6_sram[1]:12 5.861882e-05 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.518187e-06 +11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.530007e-05 +12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.518187e-06 +13 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.530007e-05 + +*RES +0 mux_right_ipin_14\/mux_l2_in_1_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001006696 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_14\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000782365 //LENGTH 6.205 LUMPCC 0.0002365928 DR + +*CONN +*I mux_right_ipin_15\/mux_l2_in_3_:X O *L 0 *C 77.105 85.000 +*I mux_right_ipin_15\/mux_l3_in_1_:A0 I *L 0.001631 *C 78.490 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 78.453 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 77.325 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 77.280 80.965 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 77.280 84.955 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 77.280 85.000 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 77.105 85.000 + +*CAP +0 mux_right_ipin_15\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_15\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.906998e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.906998e-05 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001137335 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001137335 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.833042e-05 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.983473e-05 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[4]:22 5.492333e-05 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[4]:25 5.492333e-05 +10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_7_sram[3]:9 6.337307e-05 +11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_7_sram[3]:8 6.337307e-05 + +*RES +0 mux_right_ipin_15\/mux_l2_in_3_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_15\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001006696 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET chany_bottom_out[10] 0.001049164 //LENGTH 7.160 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 46.920 4.760 +*P chany_bottom_out[10] O *L 0.7423 *C 44.620 1.290 +*N chany_bottom_out[10]:2 *C 44.620 2.040 +*N chany_bottom_out[10]:3 *C 45.080 2.040 +*N chany_bottom_out[10]:4 *C 45.080 4.715 +*N chany_bottom_out[10]:5 *C 45.125 4.760 +*N chany_bottom_out[10]:6 *C 46.920 4.760 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 chany_bottom_out[10] 5.478408e-05 +2 chany_bottom_out[10]:2 8.438059e-05 +3 chany_bottom_out[10]:3 0.0002294253 +4 chany_bottom_out[10]:4 0.0001998288 +5 chany_bottom_out[10]:5 0.0002239103 +6 chany_bottom_out[10]:6 0.000255835 + +*RES +0 ropt_mt_inst_735:X chany_bottom_out[10]:6 0.152 +1 chany_bottom_out[10]:6 chany_bottom_out[10]:5 0.001602679 +2 chany_bottom_out[10]:5 chany_bottom_out[10]:4 0.0045 +3 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.002388393 +4 chany_bottom_out[10]:2 chany_bottom_out[10] 0.0006696429 +5 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0004107143 + +*END + +*D_NET chany_bottom_out[7] 0.001125769 //LENGTH 8.495 LUMPCC 0.0001501905 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 36.340 7.480 +*P chany_bottom_out[7] O *L 0.7423 *C 38.180 1.290 +*N chany_bottom_out[7]:2 *C 38.180 7.435 +*N chany_bottom_out[7]:3 *C 38.135 7.480 +*N chany_bottom_out[7]:4 *C 36.378 7.480 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 chany_bottom_out[7] 0.0003659375 +2 chany_bottom_out[7]:2 0.0003659375 +3 chany_bottom_out[7]:3 0.000121352 +4 chany_bottom_out[7]:4 0.000121352 +5 chany_bottom_out[7] ropt_net_179:6 1.708148e-05 +6 chany_bottom_out[7]:4 ropt_net_179:4 5.801375e-05 +7 chany_bottom_out[7]:3 ropt_net_179:5 5.801375e-05 +8 chany_bottom_out[7]:2 ropt_net_179:7 1.708148e-05 + +*RES +0 ropt_mt_inst_739:X chany_bottom_out[7]:4 0.152 +1 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.001569197 +2 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0045 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.005486607 + +*END + +*D_NET chany_bottom_out[15] 0.001183732 //LENGTH 8.490 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 27.140 7.140 +*P chany_bottom_out[15] O *L 0.7423 *C 25.300 1.290 +*N chany_bottom_out[15]:2 *C 25.300 1.655 +*N chany_bottom_out[15]:3 *C 25.345 1.700 +*N chany_bottom_out[15]:4 *C 27.095 1.700 +*N chany_bottom_out[15]:5 *C 27.140 1.745 +*N chany_bottom_out[15]:6 *C 27.140 7.095 +*N chany_bottom_out[15]:7 *C 27.140 7.140 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 chany_bottom_out[15] 3.725405e-05 +2 chany_bottom_out[15]:2 3.725405e-05 +3 chany_bottom_out[15]:3 0.0001689704 +4 chany_bottom_out[15]:4 0.0001689704 +5 chany_bottom_out[15]:5 0.0003686526 +6 chany_bottom_out[15]:6 0.0003686526 +7 chany_bottom_out[15]:7 3.297748e-05 + +*RES +0 ropt_mt_inst_779:X chany_bottom_out[15]:7 0.152 +1 chany_bottom_out[15]:7 chany_bottom_out[15]:6 0.0045 +2 chany_bottom_out[15]:6 chany_bottom_out[15]:5 0.004776786 +3 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.0015625 +4 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.0045 +5 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.0045 +6 chany_bottom_out[15]:2 chany_bottom_out[15] 0.0003258929 + +*END + +*D_NET chany_bottom_out[11] 0.001880942 //LENGTH 12.340 LUMPCC 0.000154551 DR + +*CONN +*I FTB_32__31:X O *L 0 *C 40.940 6.120 +*P chany_bottom_out[11] O *L 0.7423 *C 47.380 1.325 +*N chany_bottom_out[11]:2 *C 47.380 3.695 +*N chany_bottom_out[11]:3 *C 47.335 3.740 +*N chany_bottom_out[11]:4 *C 43.745 3.740 +*N chany_bottom_out[11]:5 *C 43.700 3.785 +*N chany_bottom_out[11]:6 *C 43.700 6.075 +*N chany_bottom_out[11]:7 *C 43.655 6.120 +*N chany_bottom_out[11]:8 *C 40.977 6.120 + +*CAP +0 FTB_32__31:X 1e-06 +1 chany_bottom_out[11] 0.0001618055 +2 chany_bottom_out[11]:2 0.0001618055 +3 chany_bottom_out[11]:3 0.0002703171 +4 chany_bottom_out[11]:4 0.0002703171 +5 chany_bottom_out[11]:5 0.000175319 +6 chany_bottom_out[11]:6 0.000175319 +7 chany_bottom_out[11]:7 0.0002552539 +8 chany_bottom_out[11]:8 0.0002552539 +9 chany_bottom_out[11]:3 ropt_net_171:3 7.727551e-05 +10 chany_bottom_out[11]:4 ropt_net_171:2 7.727551e-05 + +*RES +0 FTB_32__31:X chany_bottom_out[11]:8 0.152 +1 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +2 chany_bottom_out[11]:2 chany_bottom_out[11] 0.002116072 +3 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.003205357 +4 chany_bottom_out[11]:5 chany_bottom_out[11]:4 0.0045 +5 chany_bottom_out[11]:7 chany_bottom_out[11]:6 0.0045 +6 chany_bottom_out[11]:6 chany_bottom_out[11]:5 0.002044643 +7 chany_bottom_out[11]:8 chany_bottom_out[11]:7 0.002390625 + +*END + +*D_NET ropt_net_187 0.001277355 //LENGTH 8.365 LUMPCC 0.0002203225 DR + +*CONN +*I FTB_40__39:X O *L 0 *C 22.540 9.180 +*I ropt_mt_inst_808:A I *L 0.001766 *C 28.980 9.520 +*N ropt_net_187:2 *C 28.980 9.520 +*N ropt_net_187:3 *C 28.980 9.475 +*N ropt_net_187:4 *C 28.980 8.885 +*N ropt_net_187:5 *C 28.935 8.840 +*N ropt_net_187:6 *C 26.220 8.840 +*N ropt_net_187:7 *C 26.220 9.180 +*N ropt_net_187:8 *C 22.578 9.180 + +*CAP +0 FTB_40__39:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_187:2 3.381259e-05 +3 ropt_net_187:3 6.334365e-05 +4 ropt_net_187:4 6.334365e-05 +5 ropt_net_187:5 0.0002132352 +6 ropt_net_187:6 0.0002402278 +7 ropt_net_187:7 0.0002340309 +8 ropt_net_187:8 0.0002070383 +9 ropt_net_187:8 mux_tree_tapbuf_size10_7_sram[1]:11 6.149346e-05 +10 ropt_net_187:7 mux_tree_tapbuf_size10_7_sram[1]:12 6.149346e-05 +11 ropt_net_187:8 ropt_net_155:2 4.866778e-05 +12 ropt_net_187:7 ropt_net_155:3 4.866778e-05 + +*RES +0 FTB_40__39:X ropt_net_187:8 0.152 +1 ropt_net_187:2 ropt_mt_inst_808:A 0.152 +2 ropt_net_187:3 ropt_net_187:2 0.0045 +3 ropt_net_187:5 ropt_net_187:4 0.0045 +4 ropt_net_187:4 ropt_net_187:3 0.0005267857 +5 ropt_net_187:8 ropt_net_187:7 0.003252232 +6 ropt_net_187:7 ropt_net_187:6 0.0003035715 +7 ropt_net_187:6 ropt_net_187:5 0.002424107 + +*END + +*D_NET chany_top_out[5] 0.0003829198 //LENGTH 2.270 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 47.380 105.400 +*P chany_top_out[5] O *L 0.7423 *C 47.380 107.510 +*N chany_top_out[5]:2 *C 47.380 105.445 +*N chany_top_out[5]:3 *C 47.380 105.400 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 chany_top_out[5] 0.0001723899 +2 chany_top_out[5]:2 0.0001723899 +3 chany_top_out[5]:3 3.714001e-05 + +*RES +0 ropt_mt_inst_781:X chany_top_out[5]:3 0.152 +1 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +2 chany_top_out[5]:2 chany_top_out[5] 0.00184375 + +*END + +*D_NET ropt_net_157 0.0008191737 //LENGTH 6.585 LUMPCC 0.0002515435 DR + +*CONN +*I BUFT_RR_71:X O *L 0 *C 33.580 14.280 +*I ropt_mt_inst_756:A I *L 0.001766 *C 33.580 9.520 +*N ropt_net_157:2 *C 33.617 9.520 +*N ropt_net_157:3 *C 33.995 9.520 +*N ropt_net_157:4 *C 34.040 9.565 +*N ropt_net_157:5 *C 34.040 13.600 +*N ropt_net_157:6 *C 33.580 13.600 +*N ropt_net_157:7 *C 33.580 14.235 +*N ropt_net_157:8 *C 33.580 14.280 + +*CAP +0 BUFT_RR_71:X 1e-06 +1 ropt_mt_inst_756:A 1e-06 +2 ropt_net_157:2 4.925901e-05 +3 ropt_net_157:3 4.925901e-05 +4 ropt_net_157:4 0.0001508697 +5 ropt_net_157:5 0.0001818106 +6 ropt_net_157:6 6.211549e-05 +7 ropt_net_157:7 3.117458e-05 +8 ropt_net_157:8 4.114187e-05 +9 ropt_net_157:4 chany_bottom_in[9]:41 3.958297e-05 +10 ropt_net_157:7 chany_bottom_in[9]:40 2.343822e-05 +11 ropt_net_157:6 chany_bottom_in[9]:41 2.343822e-05 +12 ropt_net_157:5 chany_bottom_in[9]:40 3.958297e-05 +13 ropt_net_157:4 chany_top_in[3]:18 5.910708e-05 +14 ropt_net_157:7 chany_top_in[3]:21 3.643488e-06 +15 ropt_net_157:6 chany_top_in[3]:18 3.643488e-06 +16 ropt_net_157:5 chany_top_in[3]:21 5.910708e-05 + +*RES +0 BUFT_RR_71:X ropt_net_157:8 0.152 +1 ropt_net_157:2 ropt_mt_inst_756:A 0.152 +2 ropt_net_157:3 ropt_net_157:2 0.0003370536 +3 ropt_net_157:4 ropt_net_157:3 0.0045 +4 ropt_net_157:8 ropt_net_157:7 0.0045 +5 ropt_net_157:7 ropt_net_157:6 0.0005669643 +6 ropt_net_157:6 ropt_net_157:5 0.0004107143 +7 ropt_net_157:5 ropt_net_157:4 0.003602678 + +*END + +*D_NET chany_top_out[18] 0.0009329215 //LENGTH 7.430 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 30.095 101.660 +*P chany_top_out[18] O *L 0.7423 *C 28.980 107.510 +*N chany_top_out[18]:2 *C 28.980 101.705 +*N chany_top_out[18]:3 *C 29.025 101.660 +*N chany_top_out[18]:4 *C 30.058 101.660 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 chany_top_out[18] 0.0003558414 +2 chany_top_out[18]:2 0.0003558414 +3 chany_top_out[18]:3 0.0001101193 +4 chany_top_out[18]:4 0.0001101193 + +*RES +0 ropt_mt_inst_763:X chany_top_out[18]:4 0.152 +1 chany_top_out[18]:4 chany_top_out[18]:3 0.0009218751 +2 chany_top_out[18]:3 chany_top_out[18]:2 0.0045 +3 chany_top_out[18]:2 chany_top_out[18] 0.005183036 + +*END + +*D_NET chany_top_out[13] 0.001491313 //LENGTH 10.150 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 43.895 102.340 +*P chany_top_out[13] O *L 0.7423 *C 39.560 107.475 +*N chany_top_out[13]:2 *C 40.020 107.440 +*N chany_top_out[13]:3 *C 40.020 102.725 +*N chany_top_out[13]:4 *C 40.020 102.680 +*N chany_top_out[13]:5 *C 40.020 102.340 +*N chany_top_out[13]:6 *C 43.858 102.340 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 chany_top_out[13] 3.614896e-05 +2 chany_top_out[13]:2 0.0003676913 +3 chany_top_out[13]:3 0.0003315423 +4 chany_top_out[13]:4 7.169977e-05 +5 chany_top_out[13]:5 0.0003578637 +6 chany_top_out[13]:6 0.0003253667 + +*RES +0 ropt_mt_inst_791:X chany_top_out[13]:6 0.152 +1 chany_top_out[13]:6 chany_top_out[13]:5 0.00342634 +2 chany_top_out[13]:4 chany_top_out[13]:3 0.0045 +3 chany_top_out[13]:3 chany_top_out[13]:2 0.004209822 +4 chany_top_out[13]:5 chany_top_out[13]:4 0.0003035715 +5 chany_top_out[13]:2 chany_top_out[13] 0.0004107143 + +*END + +*D_NET chany_bottom_in[1] 0.02043837 //LENGTH 154.292 LUMPCC 0.004520238 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 32.660 1.325 +*I mux_right_ipin_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 31.280 34.340 +*I mux_right_ipin_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 29.805 36.380 +*I mux_right_ipin_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 32.300 41.820 +*I mux_right_ipin_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 30.460 77.860 +*I mux_right_ipin_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 25.760 83.300 +*I ropt_mt_inst_738:A I *L 0.001767 *C 37.260 104.720 +*I mux_right_ipin_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 24.380 94.180 +*I mux_right_ipin_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 30.000 74.460 +*I mux_right_ipin_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 28.425 12.580 +*N chany_bottom_in[1]:10 *C 28.425 12.580 +*N chany_bottom_in[1]:11 *C 28.520 12.625 +*N chany_bottom_in[1]:12 *C 28.520 13.543 +*N chany_bottom_in[1]:13 *C 28.527 13.600 +*N chany_bottom_in[1]:14 *C 24.343 94.180 +*N chany_bottom_in[1]:15 *C 23.965 94.180 +*N chany_bottom_in[1]:16 *C 37.223 104.720 +*N chany_bottom_in[1]:17 *C 35.465 104.720 +*N chany_bottom_in[1]:18 *C 35.420 104.765 +*N chany_bottom_in[1]:19 *C 35.420 106.715 +*N chany_bottom_in[1]:20 *C 35.375 106.760 +*N chany_bottom_in[1]:21 *C 21.205 106.760 +*N chany_bottom_in[1]:22 *C 21.160 106.715 +*N chany_bottom_in[1]:23 *C 21.160 104.765 +*N chany_bottom_in[1]:24 *C 21.205 104.720 +*N chany_bottom_in[1]:25 *C 22.955 104.720 +*N chany_bottom_in[1]:26 *C 23.000 104.675 +*N chany_bottom_in[1]:27 *C 23.000 94.238 +*N chany_bottom_in[1]:28 *C 23.008 94.180 +*N chany_bottom_in[1]:29 *C 23.913 94.180 +*N chany_bottom_in[1]:30 *C 23.920 94.180 +*N chany_bottom_in[1]:31 *C 23.920 82.665 +*N chany_bottom_in[1]:32 *C 23.965 82.620 +*N chany_bottom_in[1]:33 *C 25.760 82.620 +*N chany_bottom_in[1]:34 *C 25.760 83.300 +*N chany_bottom_in[1]:35 *C 27.095 83.300 +*N chany_bottom_in[1]:36 *C 27.140 83.255 +*N chany_bottom_in[1]:37 *C 27.140 82.325 +*N chany_bottom_in[1]:38 *C 27.185 82.280 +*N chany_bottom_in[1]:39 *C 29.855 82.280 +*N chany_bottom_in[1]:40 *C 29.900 82.235 +*N chany_bottom_in[1]:41 *C 30.423 77.860 +*N chany_bottom_in[1]:42 *C 29.945 77.860 +*N chany_bottom_in[1]:43 *C 29.900 77.860 +*N chany_bottom_in[1]:44 *C 29.900 74.505 +*N chany_bottom_in[1]:45 *C 30.038 74.460 +*N chany_bottom_in[1]:46 *C 31.280 74.460 +*N chany_bottom_in[1]:47 *C 31.280 74.120 +*N chany_bottom_in[1]:48 *C 31.280 74.075 +*N chany_bottom_in[1]:49 *C 31.280 41.480 +*N chany_bottom_in[1]:50 *C 32.263 41.820 +*N chany_bottom_in[1]:51 *C 31.740 41.820 +*N chany_bottom_in[1]:52 *C 31.740 41.480 +*N chany_bottom_in[1]:53 *C 31.740 41.435 +*N chany_bottom_in[1]:54 *C 29.843 36.380 +*N chany_bottom_in[1]:55 *C 31.695 36.380 +*N chany_bottom_in[1]:56 *C 31.740 36.380 +*N chany_bottom_in[1]:57 *C 31.740 32.640 +*N chany_bottom_in[1]:58 *C 31.280 34.340 +*N chany_bottom_in[1]:59 *C 31.280 34.295 +*N chany_bottom_in[1]:60 *C 31.280 32.640 +*N chany_bottom_in[1]:61 *C 31.280 13.658 +*N chany_bottom_in[1]:62 *C 31.280 13.600 +*N chany_bottom_in[1]:63 *C 32.653 13.600 +*N chany_bottom_in[1]:64 *C 32.660 13.543 + +*CAP +0 chany_bottom_in[1] 0.0004406658 +1 mux_right_ipin_10\/mux_l1_in_0_:A1 1e-06 +2 mux_right_ipin_8\/mux_l1_in_0_:A1 1e-06 +3 mux_right_ipin_14\/mux_l1_in_0_:A1 1e-06 +4 mux_right_ipin_0\/mux_l1_in_0_:A1 1e-06 +5 mux_right_ipin_4\/mux_l1_in_0_:A1 1e-06 +6 ropt_mt_inst_738:A 1e-06 +7 mux_right_ipin_2\/mux_l1_in_0_:A1 1e-06 +8 mux_right_ipin_6\/mux_l1_in_0_:A1 1e-06 +9 mux_right_ipin_12\/mux_l1_in_0_:A1 1e-06 +10 chany_bottom_in[1]:10 2.934116e-05 +11 chany_bottom_in[1]:11 8.048004e-05 +12 chany_bottom_in[1]:12 8.048004e-05 +13 chany_bottom_in[1]:13 0.0002025489 +14 chany_bottom_in[1]:14 5.06183e-05 +15 chany_bottom_in[1]:15 5.06183e-05 +16 chany_bottom_in[1]:16 0.0001643007 +17 chany_bottom_in[1]:17 0.0001643007 +18 chany_bottom_in[1]:18 0.0001773333 +19 chany_bottom_in[1]:19 0.0001773333 +20 chany_bottom_in[1]:20 0.001160401 +21 chany_bottom_in[1]:21 0.001160401 +22 chany_bottom_in[1]:22 0.0001183499 +23 chany_bottom_in[1]:23 0.0001183499 +24 chany_bottom_in[1]:24 0.0001329308 +25 chany_bottom_in[1]:25 0.0001329308 +26 chany_bottom_in[1]:26 0.0005809308 +27 chany_bottom_in[1]:27 0.0005809308 +28 chany_bottom_in[1]:28 0.0001163032 +29 chany_bottom_in[1]:29 0.0001163032 +30 chany_bottom_in[1]:30 0.000564611 +31 chany_bottom_in[1]:31 0.000527993 +32 chany_bottom_in[1]:32 0.0001446965 +33 chany_bottom_in[1]:33 0.0001874828 +34 chany_bottom_in[1]:34 0.0001557779 +35 chany_bottom_in[1]:35 0.0001129916 +36 chany_bottom_in[1]:36 5.947972e-05 +37 chany_bottom_in[1]:37 5.947972e-05 +38 chany_bottom_in[1]:38 0.0002040097 +39 chany_bottom_in[1]:39 0.0002040097 +40 chany_bottom_in[1]:40 0.0001892451 +41 chany_bottom_in[1]:41 5.248874e-05 +42 chany_bottom_in[1]:42 5.248874e-05 +43 chany_bottom_in[1]:43 0.0003925666 +44 chany_bottom_in[1]:44 0.0001714688 +45 chany_bottom_in[1]:45 0.0001029671 +46 chany_bottom_in[1]:46 0.0001351407 +47 chany_bottom_in[1]:47 7.06434e-05 +48 chany_bottom_in[1]:48 0.00126815 +49 chany_bottom_in[1]:49 0.001302226 +50 chany_bottom_in[1]:50 6.192709e-05 +51 chany_bottom_in[1]:51 9.06418e-05 +52 chany_bottom_in[1]:52 6.206084e-05 +53 chany_bottom_in[1]:53 0.0003013681 +54 chany_bottom_in[1]:54 0.0001688658 +55 chany_bottom_in[1]:55 0.0001688658 +56 chany_bottom_in[1]:56 0.000518426 +57 chany_bottom_in[1]:57 0.0002520996 +58 chany_bottom_in[1]:58 3.816718e-05 +59 chany_bottom_in[1]:59 4.339782e-05 +60 chany_bottom_in[1]:60 0.0008514287 +61 chany_bottom_in[1]:61 0.0007773924 +62 chany_bottom_in[1]:62 0.0002712995 +63 chany_bottom_in[1]:63 6.875064e-05 +64 chany_bottom_in[1]:64 0.0004406658 +65 chany_bottom_in[1] chany_bottom_in[9]:41 0.0002983291 +66 chany_bottom_in[1]:64 chany_bottom_in[9]:40 0.0002983291 +67 chany_bottom_in[1]:30 chany_bottom_in[9]:22 4.124868e-06 +68 chany_bottom_in[1]:31 chany_bottom_in[9]:23 4.124868e-06 +69 chany_bottom_in[1] chany_top_in[1]:22 1.277034e-07 +70 chany_bottom_in[1] chany_top_in[1]:26 7.453957e-06 +71 chany_bottom_in[1]:64 chany_top_in[1]:21 1.277034e-07 +72 chany_bottom_in[1]:64 chany_top_in[1]:29 7.453957e-06 +73 chany_bottom_in[1]:12 chany_top_in[1]:29 2.215263e-08 +74 chany_bottom_in[1]:11 chany_top_in[1]:26 2.215263e-08 +75 chany_bottom_in[1]:30 chany_top_in[1]:51 9.364564e-06 +76 chany_bottom_in[1]:45 chany_top_in[1]:39 1.624321e-07 +77 chany_bottom_in[1]:44 chany_top_in[1]:43 4.432972e-05 +78 chany_bottom_in[1]:44 chany_top_in[1]:37 3.036824e-05 +79 chany_bottom_in[1]:44 chany_top_in[1]:46 1.788625e-05 +80 chany_bottom_in[1]:35 chany_top_in[1]:12 8.235107e-07 +81 chany_bottom_in[1]:36 chany_top_in[1]:51 1.602123e-05 +82 chany_bottom_in[1]:37 chany_top_in[1]:50 1.602123e-05 +83 chany_bottom_in[1]:40 chany_top_in[1]:47 0.0001208847 +84 chany_bottom_in[1]:48 chany_top_in[1]:43 0.0001237628 +85 chany_bottom_in[1]:48 chany_top_in[1]:37 1.373273e-05 +86 chany_bottom_in[1]:31 chany_top_in[1]:50 9.364564e-06 +87 chany_bottom_in[1]:61 chany_top_in[1]:26 0.0005024466 +88 chany_bottom_in[1]:34 chany_top_in[1]:51 6.553093e-06 +89 chany_bottom_in[1]:34 chany_top_in[1]:11 8.235107e-07 +90 chany_bottom_in[1]:53 chany_top_in[1]:37 4.156356e-06 +91 chany_bottom_in[1]:53 chany_top_in[1]:34 4.254474e-07 +92 chany_bottom_in[1]:53 chany_top_in[1]:30 1.198408e-06 +93 chany_bottom_in[1]:50 chany_top_in[1]:35 1.826647e-06 +94 chany_bottom_in[1]:55 chany_top_in[1]:30 6.612425e-06 +95 chany_bottom_in[1]:56 chany_top_in[1]:34 4.156356e-06 +96 chany_bottom_in[1]:56 chany_top_in[1]:29 3.016487e-06 +97 chany_bottom_in[1]:56 chany_top_in[1]:31 4.254474e-07 +98 chany_bottom_in[1]:56 chany_top_in[1]:30 6.9716e-06 +99 chany_bottom_in[1]:54 chany_top_in[1]:31 6.612425e-06 +100 chany_bottom_in[1]:42 chany_top_in[1]:44 3.775216e-06 +101 chany_bottom_in[1]:43 chany_top_in[1]:47 1.788625e-05 +102 chany_bottom_in[1]:43 chany_top_in[1]:43 3.036824e-05 +103 chany_bottom_in[1]:43 chany_top_in[1]:46 0.0001652144 +104 chany_bottom_in[1]:41 chany_top_in[1]:45 3.775216e-06 +105 chany_bottom_in[1]:59 chany_top_in[1]:29 1.703628e-05 +106 chany_bottom_in[1]:59 chany_top_in[1]:30 2.956296e-05 +107 chany_bottom_in[1]:33 chany_top_in[1]:50 6.553093e-06 +108 chany_bottom_in[1]:46 chany_top_in[1]:38 1.624321e-07 +109 chany_bottom_in[1]:51 chany_top_in[1]:36 1.826647e-06 +110 chany_bottom_in[1]:60 chany_top_in[1]:29 0.0005320096 +111 chany_bottom_in[1]:60 chany_top_in[1]:26 1.703628e-05 +112 chany_bottom_in[1]:57 chany_top_in[1]:29 6.9716e-06 +113 chany_bottom_in[1]:57 chany_top_in[1]:26 1.818079e-06 +114 chany_bottom_in[1]:49 chany_top_in[1]:37 0.0001237628 +115 chany_bottom_in[1]:49 chany_top_in[1]:34 1.373273e-05 +116 chany_bottom_in[1]:30 chany_top_in[3]:57 4.709091e-05 +117 chany_bottom_in[1]:30 chany_top_in[3]:53 9.094783e-05 +118 chany_bottom_in[1]:30 chany_top_in[3]:56 9.710105e-06 +119 chany_bottom_in[1]:48 chany_top_in[3]:38 1.260691e-05 +120 chany_bottom_in[1]:48 chany_top_in[3]:39 0.0001686348 +121 chany_bottom_in[1]:48 chany_top_in[3]:34 1.827235e-05 +122 chany_bottom_in[1]:31 chany_top_in[3]:57 9.710105e-06 +123 chany_bottom_in[1]:31 chany_top_in[3]:50 9.094783e-05 +124 chany_bottom_in[1]:31 chany_top_in[3]:53 4.709091e-05 +125 chany_bottom_in[1]:53 chany_top_in[3]:33 2.813688e-05 +126 chany_bottom_in[1]:53 chany_top_in[3]:34 7.358713e-06 +127 chany_bottom_in[1]:56 chany_top_in[3]:33 7.358713e-06 +128 chany_bottom_in[1]:56 chany_top_in[3]:26 2.813688e-05 +129 chany_bottom_in[1]:49 chany_top_in[3]:33 1.827235e-05 +130 chany_bottom_in[1]:49 chany_top_in[3]:38 0.0001686348 +131 chany_bottom_in[1]:49 chany_top_in[3]:35 1.260691e-05 +132 chany_bottom_in[1] mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.53657e-05 +133 chany_bottom_in[1]:64 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.53657e-05 +134 chany_bottom_in[1]:63 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.394237e-05 +135 chany_bottom_in[1]:61 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.1731e-05 +136 chany_bottom_in[1]:62 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.394237e-05 +137 chany_bottom_in[1]:60 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.1731e-05 +138 chany_bottom_in[1]:48 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001675289 +139 chany_bottom_in[1]:49 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001675289 +140 chany_bottom_in[1]:48 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003290153 +141 chany_bottom_in[1]:49 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003290153 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:64 0.01090848 +1 chany_bottom_in[1]:64 chany_bottom_in[1]:63 0.00341 +2 chany_bottom_in[1]:63 chany_bottom_in[1]:62 0.000215025 +3 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.0008191965 +4 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.00341 +5 chany_bottom_in[1]:10 mux_right_ipin_12\/mux_l1_in_0_:A1 0.152 +6 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.0045 +7 chany_bottom_in[1]:30 chany_bottom_in[1]:29 0.00341 +8 chany_bottom_in[1]:30 chany_bottom_in[1]:15 0.0045 +9 chany_bottom_in[1]:29 chany_bottom_in[1]:28 0.0001417833 +10 chany_bottom_in[1]:27 chany_bottom_in[1]:26 0.009319197 +11 chany_bottom_in[1]:28 chany_bottom_in[1]:27 0.00341 +12 chany_bottom_in[1]:25 chany_bottom_in[1]:24 0.0015625 +13 chany_bottom_in[1]:26 chany_bottom_in[1]:25 0.0045 +14 chany_bottom_in[1]:24 chany_bottom_in[1]:23 0.0045 +15 chany_bottom_in[1]:23 chany_bottom_in[1]:22 0.001741071 +16 chany_bottom_in[1]:21 chany_bottom_in[1]:20 0.01265179 +17 chany_bottom_in[1]:22 chany_bottom_in[1]:21 0.0045 +18 chany_bottom_in[1]:20 chany_bottom_in[1]:19 0.0045 +19 chany_bottom_in[1]:19 chany_bottom_in[1]:18 0.001741072 +20 chany_bottom_in[1]:17 chany_bottom_in[1]:16 0.001569196 +21 chany_bottom_in[1]:18 chany_bottom_in[1]:17 0.0045 +22 chany_bottom_in[1]:16 ropt_mt_inst_738:A 0.152 +23 chany_bottom_in[1]:45 chany_bottom_in[1]:44 0.0045 +24 chany_bottom_in[1]:45 mux_right_ipin_6\/mux_l1_in_0_:A1 0.152 +25 chany_bottom_in[1]:44 chany_bottom_in[1]:43 0.002995536 +26 chany_bottom_in[1]:35 chany_bottom_in[1]:34 0.001191964 +27 chany_bottom_in[1]:36 chany_bottom_in[1]:35 0.0045 +28 chany_bottom_in[1]:38 chany_bottom_in[1]:37 0.0045 +29 chany_bottom_in[1]:37 chany_bottom_in[1]:36 0.0008303572 +30 chany_bottom_in[1]:39 chany_bottom_in[1]:38 0.002383929 +31 chany_bottom_in[1]:40 chany_bottom_in[1]:39 0.0045 +32 chany_bottom_in[1]:47 chany_bottom_in[1]:46 0.0003035715 +33 chany_bottom_in[1]:48 chany_bottom_in[1]:47 0.0045 +34 chany_bottom_in[1]:32 chany_bottom_in[1]:31 0.0045 +35 chany_bottom_in[1]:31 chany_bottom_in[1]:30 0.01028125 +36 chany_bottom_in[1]:61 chany_bottom_in[1]:60 0.01694866 +37 chany_bottom_in[1]:62 chany_bottom_in[1]:61 0.00341 +38 chany_bottom_in[1]:62 chany_bottom_in[1]:13 0.000431225 +39 chany_bottom_in[1]:34 mux_right_ipin_4\/mux_l1_in_0_:A1 0.152 +40 chany_bottom_in[1]:34 chany_bottom_in[1]:33 0.0006071429 +41 chany_bottom_in[1]:52 chany_bottom_in[1]:51 0.0003035715 +42 chany_bottom_in[1]:53 chany_bottom_in[1]:52 0.0045 +43 chany_bottom_in[1]:53 chany_bottom_in[1]:49 0.0004107143 +44 chany_bottom_in[1]:50 mux_right_ipin_14\/mux_l1_in_0_:A1 0.152 +45 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.0003370536 +46 chany_bottom_in[1]:14 mux_right_ipin_2\/mux_l1_in_0_:A1 0.152 +47 chany_bottom_in[1]:55 chany_bottom_in[1]:54 0.001654018 +48 chany_bottom_in[1]:56 chany_bottom_in[1]:55 0.0045 +49 chany_bottom_in[1]:56 chany_bottom_in[1]:53 0.004513393 +50 chany_bottom_in[1]:54 mux_right_ipin_8\/mux_l1_in_0_:A1 0.152 +51 chany_bottom_in[1]:42 chany_bottom_in[1]:41 0.0004263393 +52 chany_bottom_in[1]:43 chany_bottom_in[1]:42 0.0045 +53 chany_bottom_in[1]:43 chany_bottom_in[1]:40 0.00390625 +54 chany_bottom_in[1]:41 mux_right_ipin_0\/mux_l1_in_0_:A1 0.152 +55 chany_bottom_in[1]:58 mux_right_ipin_10\/mux_l1_in_0_:A1 0.152 +56 chany_bottom_in[1]:59 chany_bottom_in[1]:58 0.0045 +57 chany_bottom_in[1]:33 chany_bottom_in[1]:32 0.001602679 +58 chany_bottom_in[1]:46 chany_bottom_in[1]:45 0.001109375 +59 chany_bottom_in[1]:51 chany_bottom_in[1]:50 0.0004665179 +60 chany_bottom_in[1]:60 chany_bottom_in[1]:59 0.001477679 +61 chany_bottom_in[1]:60 chany_bottom_in[1]:57 0.0004107143 +62 chany_bottom_in[1]:57 chany_bottom_in[1]:56 0.003339286 +63 chany_bottom_in[1]:49 chany_bottom_in[1]:48 0.02910268 + +*END + +*D_NET chany_top_in[4] 0.0186875 //LENGTH 160.640 LUMPCC 0.002915879 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 68.080 107.510 +*I mux_right_ipin_7\/mux_l2_in_2_:A1 I *L 0.00198 *C 76.265 94.180 +*I mux_right_ipin_15\/mux_l2_in_2_:A1 I *L 0.00198 *C 77.840 88.740 +*I mux_right_ipin_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 73.890 26.180 +*I BUFT_P_115:A I *L 0.001766 *C 41.860 9.520 +*I mux_left_ipin_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 71.015 47.940 +*N chany_top_in[4]:6 *C 71.053 47.940 +*N chany_top_in[4]:7 *C 41.823 9.520 +*N chany_top_in[4]:8 *C 40.985 9.520 +*N chany_top_in[4]:9 *C 40.940 9.475 +*N chany_top_in[4]:10 *C 40.940 4.465 +*N chany_top_in[4]:11 *C 40.985 4.420 +*N chany_top_in[4]:12 *C 48.300 4.420 +*N chany_top_in[4]:13 *C 48.300 4.760 +*N chany_top_in[4]:14 *C 74.015 4.760 +*N chany_top_in[4]:15 *C 74.060 4.805 +*N chany_top_in[4]:16 *C 73.890 26.180 +*N chany_top_in[4]:17 *C 74.060 26.180 +*N chany_top_in[4]:18 *C 74.060 26.180 +*N chany_top_in[4]:19 *C 74.060 47.895 +*N chany_top_in[4]:20 *C 74.060 47.940 +*N chany_top_in[4]:21 *C 76.315 47.940 +*N chany_top_in[4]:22 *C 76.360 47.985 +*N chany_top_in[4]:23 *C 77.803 88.740 +*N chany_top_in[4]:24 *C 76.405 88.740 +*N chany_top_in[4]:25 *C 76.360 88.740 +*N chany_top_in[4]:26 *C 76.265 94.180 +*N chany_top_in[4]:27 *C 76.360 94.180 +*N chany_top_in[4]:28 *C 76.360 98.543 +*N chany_top_in[4]:29 *C 76.353 98.600 +*N chany_top_in[4]:30 *C 68.088 98.600 +*N chany_top_in[4]:31 *C 68.080 98.657 + +*CAP +0 chany_top_in[4] 0.0004988626 +1 mux_right_ipin_7\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_15\/mux_l2_in_2_:A1 1e-06 +3 mux_right_ipin_9\/mux_l1_in_2_:A0 1e-06 +4 BUFT_P_115:A 1e-06 +5 mux_left_ipin_0\/mux_l1_in_2_:A0 1e-06 +6 chany_top_in[4]:6 0.0002129605 +7 chany_top_in[4]:7 0.0001043674 +8 chany_top_in[4]:8 0.0001043674 +9 chany_top_in[4]:9 0.0002092461 +10 chany_top_in[4]:10 0.0002092461 +11 chany_top_in[4]:11 0.0004005536 +12 chany_top_in[4]:12 0.0004281559 +13 chany_top_in[4]:13 0.001820395 +14 chany_top_in[4]:14 0.001792793 +15 chany_top_in[4]:15 0.0006665111 +16 chany_top_in[4]:16 4.957569e-05 +17 chany_top_in[4]:17 5.418141e-05 +18 chany_top_in[4]:18 0.00151674 +19 chany_top_in[4]:19 0.0008236609 +20 chany_top_in[4]:20 0.0004026224 +21 chany_top_in[4]:21 0.0001567882 +22 chany_top_in[4]:22 0.001741266 +23 chany_top_in[4]:23 0.0001192719 +24 chany_top_in[4]:24 0.0001192719 +25 chany_top_in[4]:25 0.002039474 +26 chany_top_in[4]:26 2.640905e-05 +27 chany_top_in[4]:27 0.0005197464 +28 chany_top_in[4]:28 0.0002193747 +29 chany_top_in[4]:29 0.0005159609 +30 chany_top_in[4]:30 0.0005159609 +31 chany_top_in[4]:31 0.0004988626 +32 chany_top_in[4]:19 chany_top_in[10]:16 0.0002291383 +33 chany_top_in[4]:19 chany_top_in[10]:15 5.567375e-05 +34 chany_top_in[4]:15 chany_top_in[10]:12 0.0002735421 +35 chany_top_in[4]:11 chany_top_in[10]:6 7.642401e-05 +36 chany_top_in[4]:18 chany_top_in[10]:12 5.567375e-05 +37 chany_top_in[4]:18 chany_top_in[10]:15 0.0005026804 +38 chany_top_in[4]:12 chany_top_in[10]:7 7.642401e-05 +39 chany_top_in[4]:19 mux_tree_tapbuf_size10_6_sram[1]:29 5.784661e-05 +40 chany_top_in[4]:15 mux_tree_tapbuf_size10_6_sram[1]:28 0.000221734 +41 chany_top_in[4]:18 mux_tree_tapbuf_size10_6_sram[1]:28 5.784661e-05 +42 chany_top_in[4]:18 mux_tree_tapbuf_size10_6_sram[1]:29 0.000221734 +43 chany_top_in[4]:25 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 6.201491e-05 +44 chany_top_in[4]:22 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 6.201491e-05 +45 chany_top_in[4]:25 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.885709e-05 +46 chany_top_in[4]:22 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.885709e-05 +47 chany_top_in[4]:25 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.976965e-05 +48 chany_top_in[4]:22 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.976965e-05 +49 chany_top_in[4]:25 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.492333e-05 +50 chany_top_in[4]:22 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.492333e-05 +51 chany_top_in[4]:11 ropt_net_171:2 0.0001592626 +52 chany_top_in[4]:12 ropt_net_171:3 0.0001592626 +53 chany_top_in[4]:10 ropt_net_174:4 0.0001387532 +54 chany_top_in[4]:9 ropt_net_174:5 0.0001387532 + +*RES +0 chany_top_in[4] chany_top_in[4]:31 0.007904018 +1 chany_top_in[4]:20 chany_top_in[4]:19 0.0045 +2 chany_top_in[4]:20 chany_top_in[4]:6 0.002685268 +3 chany_top_in[4]:19 chany_top_in[4]:18 0.01938839 +4 chany_top_in[4]:14 chany_top_in[4]:13 0.02295982 +5 chany_top_in[4]:15 chany_top_in[4]:14 0.0045 +6 chany_top_in[4]:11 chany_top_in[4]:10 0.0045 +7 chany_top_in[4]:10 chany_top_in[4]:9 0.004473215 +8 chany_top_in[4]:8 chany_top_in[4]:7 0.0007477679 +9 chany_top_in[4]:9 chany_top_in[4]:8 0.0045 +10 chany_top_in[4]:7 BUFT_P_115:A 0.152 +11 chany_top_in[4]:6 mux_left_ipin_0\/mux_l1_in_2_:A0 0.152 +12 chany_top_in[4]:17 chany_top_in[4]:16 9.239131e-05 +13 chany_top_in[4]:18 chany_top_in[4]:17 0.0045 +14 chany_top_in[4]:18 chany_top_in[4]:15 0.01908482 +15 chany_top_in[4]:16 mux_right_ipin_9\/mux_l1_in_2_:A0 0.152 +16 chany_top_in[4]:26 mux_right_ipin_7\/mux_l2_in_2_:A1 0.152 +17 chany_top_in[4]:27 chany_top_in[4]:26 0.0045 +18 chany_top_in[4]:27 chany_top_in[4]:25 0.004857143 +19 chany_top_in[4]:28 chany_top_in[4]:27 0.003895089 +20 chany_top_in[4]:29 chany_top_in[4]:28 0.00341 +21 chany_top_in[4]:31 chany_top_in[4]:30 0.00341 +22 chany_top_in[4]:30 chany_top_in[4]:29 0.00129485 +23 chany_top_in[4]:24 chany_top_in[4]:23 0.001247768 +24 chany_top_in[4]:25 chany_top_in[4]:24 0.0045 +25 chany_top_in[4]:25 chany_top_in[4]:22 0.0363884 +26 chany_top_in[4]:23 mux_right_ipin_15\/mux_l2_in_2_:A1 0.152 +27 chany_top_in[4]:21 chany_top_in[4]:20 0.002013393 +28 chany_top_in[4]:22 chany_top_in[4]:21 0.0045 +29 chany_top_in[4]:12 chany_top_in[4]:11 0.00653125 +30 chany_top_in[4]:13 chany_top_in[4]:12 0.0003035714 + +*END + +*D_NET chany_top_in[7] 0.02018809 //LENGTH 162.065 LUMPCC 0.005830496 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 32.200 107.510 +*I mux_right_ipin_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 19.685 94.180 +*I mux_right_ipin_12\/mux_l1_in_2_:A0 I *L 0.001631 *C 16.735 11.560 +*I ropt_mt_inst_739:A I *L 0.001767 *C 35.265 6.800 +*I mux_right_ipin_10\/mux_l2_in_2_:A1 I *L 0.00198 *C 15.180 39.780 +*N chany_top_in[7]:5 *C 15.180 39.780 +*N chany_top_in[7]:6 *C 15.180 39.735 +*N chany_top_in[7]:7 *C 15.180 37.400 +*N chany_top_in[7]:8 *C 35.303 6.800 +*N chany_top_in[7]:9 *C 36.295 6.800 +*N chany_top_in[7]:10 *C 36.340 6.755 +*N chany_top_in[7]:11 *C 36.340 1.745 +*N chany_top_in[7]:12 *C 36.295 1.700 +*N chany_top_in[7]:13 *C 34.960 1.700 +*N chany_top_in[7]:14 *C 34.960 1.020 +*N chany_top_in[7]:15 *C 17.940 1.020 +*N chany_top_in[7]:16 *C 17.940 1.700 +*N chany_top_in[7]:17 *C 17.940 1.745 +*N chany_top_in[7]:18 *C 17.940 4.035 +*N chany_top_in[7]:19 *C 17.895 4.080 +*N chany_top_in[7]:20 *C 16.145 4.080 +*N chany_top_in[7]:21 *C 16.100 4.125 +*N chany_top_in[7]:22 *C 16.698 11.560 +*N chany_top_in[7]:23 *C 16.145 11.560 +*N chany_top_in[7]:24 *C 16.100 11.560 +*N chany_top_in[7]:25 *C 16.100 12.875 +*N chany_top_in[7]:26 *C 16.055 12.920 +*N chany_top_in[7]:27 *C 14.765 12.920 +*N chany_top_in[7]:28 *C 14.720 12.965 +*N chany_top_in[7]:29 *C 14.720 37.400 +*N chany_top_in[7]:30 *C 14.728 37.400 +*N chany_top_in[7]:31 *C 17.460 37.400 +*N chany_top_in[7]:32 *C 17.480 37.407 +*N chany_top_in[7]:33 *C 17.480 87.235 +*N chany_top_in[7]:34 *C 17.480 94.513 +*N chany_top_in[7]:35 *C 17.500 94.520 +*N chany_top_in[7]:36 *C 19.685 94.180 +*N chany_top_in[7]:37 *C 19.780 94.520 +*N chany_top_in[7]:38 *C 19.780 94.520 +*N chany_top_in[7]:39 *C 19.780 94.528 +*N chany_top_in[7]:40 *C 19.780 95.200 +*N chany_top_in[7]:41 *C 32.193 95.200 +*N chany_top_in[7]:42 *C 32.200 95.258 + +*CAP +0 chany_top_in[7] 0.0007688317 +1 mux_right_ipin_2\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_12\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_739:A 1e-06 +4 mux_right_ipin_10\/mux_l2_in_2_:A1 1e-06 +5 chany_top_in[7]:5 3.220628e-05 +6 chany_top_in[7]:6 0.0001520263 +7 chany_top_in[7]:7 0.0001853799 +8 chany_top_in[7]:8 0.0001262629 +9 chany_top_in[7]:9 0.0001262629 +10 chany_top_in[7]:10 0.0002460252 +11 chany_top_in[7]:11 0.0002460252 +12 chany_top_in[7]:12 5.696163e-05 +13 chany_top_in[7]:13 0.0001013912 +14 chany_top_in[7]:14 0.0009349425 +15 chany_top_in[7]:15 0.0009392634 +16 chany_top_in[7]:16 8.436594e-05 +17 chany_top_in[7]:17 0.0001205209 +18 chany_top_in[7]:18 0.0001205209 +19 chany_top_in[7]:19 0.0001040708 +20 chany_top_in[7]:20 0.0001040708 +21 chany_top_in[7]:21 0.0003625806 +22 chany_top_in[7]:22 4.364092e-05 +23 chany_top_in[7]:23 4.364092e-05 +24 chany_top_in[7]:24 0.0004380748 +25 chany_top_in[7]:25 4.761216e-05 +26 chany_top_in[7]:26 0.0001180544 +27 chany_top_in[7]:27 0.0001180544 +28 chany_top_in[7]:28 0.00114441 +29 chany_top_in[7]:29 0.001177764 +30 chany_top_in[7]:30 0.0002683624 +31 chany_top_in[7]:31 0.0002683624 +32 chany_top_in[7]:32 0.001195663 +33 chany_top_in[7]:33 0.001486881 +34 chany_top_in[7]:34 0.0002912178 +35 chany_top_in[7]:35 0.0001831863 +36 chany_top_in[7]:36 6.582089e-05 +37 chany_top_in[7]:37 6.975017e-05 +38 chany_top_in[7]:38 3.554642e-05 +39 chany_top_in[7]:39 0.000229017 +40 chany_top_in[7]:40 0.0007969152 +41 chany_top_in[7]:41 0.0007510846 +42 chany_top_in[7]:42 0.0007688317 +43 chany_top_in[7]:29 chany_bottom_in[7]:9 5.24995e-07 +44 chany_top_in[7]:29 chany_bottom_in[7]:28 4.632697e-06 +45 chany_top_in[7]:32 chany_bottom_in[7]:24 0.001099852 +46 chany_top_in[7]:34 chany_bottom_in[7]:15 6.771433e-05 +47 chany_top_in[7]:34 chany_bottom_in[7]:23 1.394608e-05 +48 chany_top_in[7]:18 chany_bottom_in[7]:32 1.990844e-06 +49 chany_top_in[7]:17 chany_bottom_in[7] 1.990844e-06 +50 chany_top_in[7]:23 chany_bottom_in[7]:5 1.775493e-08 +51 chany_top_in[7]:24 chany_bottom_in[7]:29 2.995718e-06 +52 chany_top_in[7]:22 chany_bottom_in[7]:6 1.775493e-08 +53 chany_top_in[7]:28 chany_bottom_in[7]:27 5.24995e-07 +54 chany_top_in[7]:28 chany_bottom_in[7]:29 4.632697e-06 +55 chany_top_in[7]:25 chany_bottom_in[7]:28 2.995718e-06 +56 chany_top_in[7]:39 chany_bottom_in[7]:16 5.7283e-06 +57 chany_top_in[7]:40 chany_bottom_in[7]:15 5.7283e-06 +58 chany_top_in[7]:33 chany_bottom_in[7]:16 6.771433e-05 +59 chany_top_in[7]:33 chany_bottom_in[7]:23 0.001099852 +60 chany_top_in[7]:33 chany_bottom_in[7]:24 1.394608e-05 +61 chany_top_in[7]:30 chany_bottom_in[15]:22 4.464831e-05 +62 chany_top_in[7]:31 chany_bottom_in[15]:23 4.464831e-05 +63 chany_top_in[7]:32 chany_bottom_in[15]:24 0.0005316976 +64 chany_top_in[7]:32 chany_bottom_in[15]:26 1.058222e-05 +65 chany_top_in[7]:39 chany_bottom_in[15]:13 6.331564e-06 +66 chany_top_in[7]:40 chany_bottom_in[15]:10 6.331564e-06 +67 chany_top_in[7]:33 chany_bottom_in[15]:18 0.0005316976 +68 chany_top_in[7]:33 chany_bottom_in[15]:25 1.058222e-05 +69 chany_top_in[7] mux_tree_tapbuf_size10_2_sram[3]:14 6.723308e-06 +70 chany_top_in[7] mux_tree_tapbuf_size10_2_sram[3]:6 2.373196e-05 +71 chany_top_in[7]:42 mux_tree_tapbuf_size10_2_sram[3]:5 2.373196e-05 +72 chany_top_in[7]:42 mux_tree_tapbuf_size10_2_sram[3]:13 6.723308e-06 +73 chany_top_in[7]:41 mux_tree_tapbuf_size10_2_sram[3]:12 0.0004523784 +74 chany_top_in[7]:40 mux_tree_tapbuf_size10_2_sram[3]:11 0.0004523784 +75 chany_top_in[7]:29 mux_tree_tapbuf_size10_7_sram[0]:23 0.0002518506 +76 chany_top_in[7]:29 mux_tree_tapbuf_size10_7_sram[0]:17 4.336619e-05 +77 chany_top_in[7]:23 mux_tree_tapbuf_size10_7_sram[0]:15 1.644251e-05 +78 chany_top_in[7]:24 mux_tree_tapbuf_size10_7_sram[0]:16 2.770258e-05 +79 chany_top_in[7]:22 mux_tree_tapbuf_size10_7_sram[0]:14 1.644251e-05 +80 chany_top_in[7]:27 mux_tree_tapbuf_size10_7_sram[0]:15 7.337324e-06 +81 chany_top_in[7]:28 mux_tree_tapbuf_size10_7_sram[0]:16 4.336619e-05 +82 chany_top_in[7]:28 mux_tree_tapbuf_size10_7_sram[0]:22 0.0002518506 +83 chany_top_in[7]:26 mux_tree_tapbuf_size10_7_sram[0]:14 7.337324e-06 +84 chany_top_in[7]:25 mux_tree_tapbuf_size10_7_sram[0]:17 2.770258e-05 +85 chany_top_in[7]:18 ropt_net_142:4 5.562164e-06 +86 chany_top_in[7]:17 ropt_net_142:5 5.562164e-06 +87 chany_top_in[7]:12 ropt_net_142:7 5.800708e-05 +88 chany_top_in[7]:11 ropt_net_142:8 0.0001326421 +89 chany_top_in[7]:10 ropt_net_142:9 0.0001326421 +90 chany_top_in[7]:15 ropt_net_142:6 9.884118e-05 +91 chany_top_in[7]:14 ropt_net_142:7 9.884118e-05 +92 chany_top_in[7]:13 ropt_net_142:6 5.800708e-05 + +*RES +0 chany_top_in[7] chany_top_in[7]:42 0.01093973 +1 chany_top_in[7]:29 chany_top_in[7]:28 0.02181697 +2 chany_top_in[7]:29 chany_top_in[7]:7 0.0004107143 +3 chany_top_in[7]:30 chany_top_in[7]:29 0.00341 +4 chany_top_in[7]:31 chany_top_in[7]:30 0.0004280916 +5 chany_top_in[7]:32 chany_top_in[7]:31 0.00341 +6 chany_top_in[7]:35 chany_top_in[7]:34 0.00341 +7 chany_top_in[7]:34 chany_top_in[7]:33 0.001140142 +8 chany_top_in[7]:20 chany_top_in[7]:19 0.0015625 +9 chany_top_in[7]:21 chany_top_in[7]:20 0.0045 +10 chany_top_in[7]:19 chany_top_in[7]:18 0.0045 +11 chany_top_in[7]:18 chany_top_in[7]:17 0.002044643 +12 chany_top_in[7]:16 chany_top_in[7]:15 0.000607143 +13 chany_top_in[7]:17 chany_top_in[7]:16 0.0045 +14 chany_top_in[7]:12 chany_top_in[7]:11 0.0045 +15 chany_top_in[7]:11 chany_top_in[7]:10 0.004473215 +16 chany_top_in[7]:9 chany_top_in[7]:8 0.0008861608 +17 chany_top_in[7]:10 chany_top_in[7]:9 0.0045 +18 chany_top_in[7]:8 ropt_mt_inst_739:A 0.152 +19 chany_top_in[7]:23 chany_top_in[7]:22 0.0004933036 +20 chany_top_in[7]:24 chany_top_in[7]:23 0.0045 +21 chany_top_in[7]:24 chany_top_in[7]:21 0.006638393 +22 chany_top_in[7]:22 mux_right_ipin_12\/mux_l1_in_2_:A0 0.152 +23 chany_top_in[7]:27 chany_top_in[7]:26 0.001151786 +24 chany_top_in[7]:28 chany_top_in[7]:27 0.0045 +25 chany_top_in[7]:26 chany_top_in[7]:25 0.0045 +26 chany_top_in[7]:25 chany_top_in[7]:24 0.001174107 +27 chany_top_in[7]:38 chany_top_in[7]:37 0.0045 +28 chany_top_in[7]:39 chany_top_in[7]:38 0.00341 +29 chany_top_in[7]:39 chany_top_in[7]:35 0.0003572 +30 chany_top_in[7]:37 chany_top_in[7]:36 0.0001847826 +31 chany_top_in[7]:36 mux_right_ipin_2\/mux_l2_in_2_:A1 0.152 +32 chany_top_in[7]:5 mux_right_ipin_10\/mux_l2_in_2_:A1 0.152 +33 chany_top_in[7]:6 chany_top_in[7]:5 0.0045 +34 chany_top_in[7]:42 chany_top_in[7]:41 0.00341 +35 chany_top_in[7]:41 chany_top_in[7]:40 0.001944625 +36 chany_top_in[7]:15 chany_top_in[7]:14 0.01519643 +37 chany_top_in[7]:14 chany_top_in[7]:13 0.0006071429 +38 chany_top_in[7]:13 chany_top_in[7]:12 0.001191964 +39 chany_top_in[7]:7 chany_top_in[7]:6 0.002084822 +40 chany_top_in[7]:40 chany_top_in[7]:39 0.0001053583 +41 chany_top_in[7]:33 chany_top_in[7]:32 0.007806308 + +*END + +*D_NET chany_top_in[13] 0.01493607 //LENGTH 120.255 LUMPCC 0.001721484 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 33.120 107.475 +*I mux_right_ipin_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 26.585 39.780 +*I mux_right_ipin_12\/mux_l2_in_2_:A1 I *L 0.00198 *C 29.345 18.020 +*I FTB_34__33:A I *L 0.001767 *C 35.880 4.080 +*N chany_top_in[13]:4 *C 35.843 4.080 +*N chany_top_in[13]:5 *C 34.085 4.080 +*N chany_top_in[13]:6 *C 34.040 4.125 +*N chany_top_in[13]:7 *C 34.040 4.703 +*N chany_top_in[13]:8 *C 34.032 4.760 +*N chany_top_in[13]:9 *C 30.380 4.760 +*N chany_top_in[13]:10 *C 30.360 4.768 +*N chany_top_in[13]:11 *C 29.650 18.020 +*N chany_top_in[13]:12 *C 29.383 18.020 +*N chany_top_in[13]:13 *C 30.315 18.020 +*N chany_top_in[13]:14 *C 30.360 18.020 +*N chany_top_in[13]:15 *C 30.358 18.020 +*N chany_top_in[13]:16 *C 30.360 18.020 +*N chany_top_in[13]:17 *C 26.585 39.780 +*N chany_top_in[13]:18 *C 26.680 39.780 +*N chany_top_in[13]:19 *C 26.680 39.440 +*N chany_top_in[13]:20 *C 26.688 39.440 +*N chany_top_in[13]:21 *C 30.340 39.440 +*N chany_top_in[13]:22 *C 30.360 39.440 +*N chany_top_in[13]:23 *C 30.360 89.440 +*N chany_top_in[13]:24 *C 30.360 106.073 +*N chany_top_in[13]:25 *C 30.380 106.080 +*N chany_top_in[13]:26 *C 33.113 106.080 +*N chany_top_in[13]:27 *C 33.120 106.138 + +*CAP +0 chany_top_in[13] 0.0001123078 +1 mux_right_ipin_8\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_12\/mux_l2_in_2_:A1 1e-06 +3 FTB_34__33:A 1e-06 +4 chany_top_in[13]:4 0.0001794547 +5 chany_top_in[13]:5 0.0001794547 +6 chany_top_in[13]:6 6.616241e-05 +7 chany_top_in[13]:7 6.616241e-05 +8 chany_top_in[13]:8 0.0002469865 +9 chany_top_in[13]:9 0.0002469865 +10 chany_top_in[13]:10 0.0006904132 +11 chany_top_in[13]:11 9.514632e-05 +12 chany_top_in[13]:12 0.000101835 +13 chany_top_in[13]:13 0.000101835 +14 chany_top_in[13]:14 3.882546e-05 +15 chany_top_in[13]:15 9.514632e-05 +16 chany_top_in[13]:16 0.001889573 +17 chany_top_in[13]:17 2.861994e-05 +18 chany_top_in[13]:18 5.471957e-05 +19 chany_top_in[13]:19 5.840584e-05 +20 chany_top_in[13]:20 0.0002398822 +21 chany_top_in[13]:21 0.0002398822 +22 chany_top_in[13]:22 0.003674616 +23 chany_top_in[13]:23 0.003337605 +24 chany_top_in[13]:24 0.0008621497 +25 chany_top_in[13]:25 0.0002465525 +26 chany_top_in[13]:26 0.0002465525 +27 chany_top_in[13]:27 0.0001123078 +28 chany_top_in[13]:22 chany_bottom_in[11]:29 0.0002393221 +29 chany_top_in[13]:22 chany_bottom_in[11]:30 0.0003185941 +30 chany_top_in[13]:23 chany_bottom_in[11]:23 0.0002393221 +31 chany_top_in[13]:23 chany_bottom_in[11]:29 0.0003185941 +32 chany_top_in[13]:24 chany_top_in[3]:61 0.0002088524 +33 chany_top_in[13]:21 chany_top_in[3]:32 7.229608e-05 +34 chany_top_in[13]:22 chany_top_in[3]:60 2.167741e-05 +35 chany_top_in[13]:20 chany_top_in[3]:31 7.229608e-05 +36 chany_top_in[13]:23 chany_top_in[3]:60 0.0002088524 +37 chany_top_in[13]:23 chany_top_in[3]:61 2.167741e-05 + +*RES +0 chany_top_in[13] chany_top_in[13]:27 0.001194197 +1 chany_top_in[13]:25 chany_top_in[13]:24 0.00341 +2 chany_top_in[13]:24 chany_top_in[13]:23 0.002605758 +3 chany_top_in[13]:27 chany_top_in[13]:26 0.00341 +4 chany_top_in[13]:26 chany_top_in[13]:25 0.0004280917 +5 chany_top_in[13]:15 chany_top_in[13]:14 0.00341 +6 chany_top_in[13]:15 chany_top_in[13]:11 0.0001039141 +7 chany_top_in[13]:16 chany_top_in[13]:15 0.00341 +8 chany_top_in[13]:16 chany_top_in[13]:10 0.002076225 +9 chany_top_in[13]:14 chany_top_in[13]:13 0.0045 +10 chany_top_in[13]:13 chany_top_in[13]:12 0.0008325893 +11 chany_top_in[13]:12 mux_right_ipin_12\/mux_l2_in_2_:A1 0.152 +12 chany_top_in[13]:21 chany_top_in[13]:20 0.000572225 +13 chany_top_in[13]:22 chany_top_in[13]:21 0.00341 +14 chany_top_in[13]:22 chany_top_in[13]:16 0.0033558 +15 chany_top_in[13]:19 chany_top_in[13]:18 0.0001634615 +16 chany_top_in[13]:20 chany_top_in[13]:19 0.00341 +17 chany_top_in[13]:17 mux_right_ipin_8\/mux_l2_in_2_:A1 0.152 +18 chany_top_in[13]:18 chany_top_in[13]:17 0.0045 +19 chany_top_in[13]:9 chany_top_in[13]:8 0.000572225 +20 chany_top_in[13]:10 chany_top_in[13]:9 0.00341 +21 chany_top_in[13]:7 chany_top_in[13]:6 0.000515625 +22 chany_top_in[13]:8 chany_top_in[13]:7 0.00341 +23 chany_top_in[13]:5 chany_top_in[13]:4 0.001569196 +24 chany_top_in[13]:6 chany_top_in[13]:5 0.0045 +25 chany_top_in[13]:4 FTB_34__33:A 0.152 +26 chany_top_in[13]:23 chany_top_in[13]:22 0.007833333 + +*END + +*D_NET chany_top_in[18] 0.01539708 //LENGTH 122.545 LUMPCC 0.005668524 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 44.620 107.510 +*I mux_right_ipin_13\/mux_l2_in_3_:A1 I *L 0.00198 *C 50.140 14.620 +*I FTB_39__38:A I *L 0.001767 *C 61.180 9.520 +*I mux_right_ipin_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 41.305 94.180 +*N chany_top_in[18]:4 *C 41.343 94.180 +*N chany_top_in[18]:5 *C 44.575 94.180 +*N chany_top_in[18]:6 *C 44.620 94.180 +*N chany_top_in[18]:7 *C 61.143 9.520 +*N chany_top_in[18]:8 *C 58.925 9.520 +*N chany_top_in[18]:9 *C 58.880 9.565 +*N chany_top_in[18]:10 *C 58.880 13.543 +*N chany_top_in[18]:11 *C 58.873 13.600 +*N chany_top_in[18]:12 *C 50.140 14.620 +*N chany_top_in[18]:13 *C 50.140 14.575 +*N chany_top_in[18]:14 *C 50.140 13.658 +*N chany_top_in[18]:15 *C 50.143 13.600 +*N chany_top_in[18]:16 *C 50.620 13.600 +*N chany_top_in[18]:17 *C 50.600 13.607 +*N chany_top_in[18]:18 *C 50.600 63.435 +*N chany_top_in[18]:19 *C 50.600 94.513 +*N chany_top_in[18]:20 *C 50.580 94.520 +*N chany_top_in[18]:21 *C 44.628 94.520 +*N chany_top_in[18]:22 *C 44.620 94.578 + +*CAP +0 chany_top_in[18] 0.0008361741 +1 mux_right_ipin_13\/mux_l2_in_3_:A1 1e-06 +2 FTB_39__38:A 1e-06 +3 mux_right_ipin_1\/mux_l2_in_3_:A1 1e-06 +4 chany_top_in[18]:4 0.0002933066 +5 chany_top_in[18]:5 0.0002933066 +6 chany_top_in[18]:6 6.196108e-05 +7 chany_top_in[18]:7 0.0001500063 +8 chany_top_in[18]:8 0.0001500063 +9 chany_top_in[18]:9 0.0002424321 +10 chany_top_in[18]:10 0.0002424321 +11 chany_top_in[18]:11 0.0006195783 +12 chany_top_in[18]:12 3.32489e-05 +13 chany_top_in[18]:13 8.031894e-05 +14 chany_top_in[18]:14 8.031894e-05 +15 chany_top_in[18]:15 6.083614e-05 +16 chany_top_in[18]:16 0.0006804145 +17 chany_top_in[18]:17 0.001190566 +18 chany_top_in[18]:18 0.002073834 +19 chany_top_in[18]:19 0.0008832684 +20 chany_top_in[18]:20 0.0004459778 +21 chany_top_in[18]:21 0.0004459778 +22 chany_top_in[18]:22 0.0008615938 +23 chany_top_in[18]:19 chany_bottom_in[12]:20 0.000647417 +24 chany_top_in[18]:17 chany_bottom_in[12]:21 0.0002295127 +25 chany_top_in[18]:17 chany_bottom_in[12]:22 0.0008522233 +26 chany_top_in[18]:18 chany_bottom_in[12]:20 0.0002295127 +27 chany_top_in[18]:18 chany_bottom_in[12]:21 0.00149964 +28 chany_top_in[18]:19 chany_top_in[12]:13 0.0003535558 +29 chany_top_in[18]:17 chany_top_in[12]:12 0.0007515529 +30 chany_top_in[18]:18 chany_top_in[12]:12 0.0003535558 +31 chany_top_in[18]:18 chany_top_in[12]:13 0.0007515529 + +*RES +0 chany_top_in[18] chany_top_in[18]:22 0.01154688 +1 chany_top_in[18]:22 chany_top_in[18]:21 0.00341 +2 chany_top_in[18]:22 chany_top_in[18]:6 0.0001911058 +3 chany_top_in[18]:21 chany_top_in[18]:20 0.0009325583 +4 chany_top_in[18]:20 chany_top_in[18]:19 0.00341 +5 chany_top_in[18]:19 chany_top_in[18]:18 0.004868808 +6 chany_top_in[18]:16 chany_top_in[18]:15 7.013281e-05 +7 chany_top_in[18]:16 chany_top_in[18]:11 0.001292892 +8 chany_top_in[18]:17 chany_top_in[18]:16 0.00341 +9 chany_top_in[18]:5 chany_top_in[18]:4 0.002886161 +10 chany_top_in[18]:6 chany_top_in[18]:5 0.0045 +11 chany_top_in[18]:4 mux_right_ipin_1\/mux_l2_in_3_:A1 0.152 +12 chany_top_in[18]:10 chany_top_in[18]:9 0.003551339 +13 chany_top_in[18]:11 chany_top_in[18]:10 0.00341 +14 chany_top_in[18]:8 chany_top_in[18]:7 0.001979911 +15 chany_top_in[18]:9 chany_top_in[18]:8 0.0045 +16 chany_top_in[18]:7 FTB_39__38:A 0.152 +17 chany_top_in[18]:14 chany_top_in[18]:13 0.0008191965 +18 chany_top_in[18]:15 chany_top_in[18]:14 0.00341 +19 chany_top_in[18]:12 mux_right_ipin_13\/mux_l2_in_3_:A1 0.152 +20 chany_top_in[18]:13 chany_top_in[18]:12 0.0045 +21 chany_top_in[18]:18 chany_top_in[18]:17 0.007806308 + +*END + +*D_NET chany_top_in[19] 0.01611681 //LENGTH 127.510 LUMPCC 0.003089491 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 42.320 107.510 +*I FTB_40__39:A I *L 0.001767 *C 23.460 9.520 +*I mux_right_ipin_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 27.045 45.220 +*I mux_right_ipin_14\/mux_l2_in_3_:A1 I *L 0.00198 *C 31.840 50.660 +*I mux_right_ipin_6\/mux_l2_in_3_:A1 I *L 0.00198 *C 37.260 58.140 +*N chany_top_in[19]:5 *C 37.260 58.140 +*N chany_top_in[19]:6 *C 37.260 58.140 +*N chany_top_in[19]:7 *C 31.803 50.660 +*N chany_top_in[19]:8 *C 27.030 45.220 +*N chany_top_in[19]:9 *C 23.460 9.520 +*N chany_top_in[19]:10 *C 23.460 9.860 +*N chany_top_in[19]:11 *C 26.175 9.860 +*N chany_top_in[19]:12 *C 26.220 9.905 +*N chany_top_in[19]:13 *C 26.220 14.960 +*N chany_top_in[19]:14 *C 27.140 14.960 +*N chany_top_in[19]:15 *C 27.140 44.200 +*N chany_top_in[19]:16 *C 26.680 44.200 +*N chany_top_in[19]:17 *C 26.680 45.175 +*N chany_top_in[19]:18 *C 26.680 45.242 +*N chany_top_in[19]:19 *C 26.680 45.560 +*N chany_top_in[19]:20 *C 30.775 45.560 +*N chany_top_in[19]:21 *C 30.820 45.605 +*N chany_top_in[19]:22 *C 30.820 50.615 +*N chany_top_in[19]:23 *C 30.820 50.660 +*N chany_top_in[19]:24 *C 30.820 51.000 +*N chany_top_in[19]:25 *C 34.915 51.000 +*N chany_top_in[19]:26 *C 34.960 51.045 +*N chany_top_in[19]:27 *C 34.960 58.140 +*N chany_top_in[19]:28 *C 34.960 58.480 +*N chany_top_in[19]:29 *C 34.500 58.480 +*N chany_top_in[19]:30 *C 34.500 64.543 +*N chany_top_in[19]:31 *C 34.508 64.600 +*N chany_top_in[19]:32 *C 38.620 64.600 +*N chany_top_in[19]:33 *C 38.640 64.608 +*N chany_top_in[19]:34 *C 38.640 106.753 +*N chany_top_in[19]:35 *C 38.660 106.760 +*N chany_top_in[19]:36 *C 42.312 106.760 +*N chany_top_in[19]:37 *C 42.320 106.818 + +*CAP +0 chany_top_in[19] 6.951681e-05 +1 FTB_40__39:A 1e-06 +2 mux_right_ipin_8\/mux_l2_in_3_:A1 1e-06 +3 mux_right_ipin_14\/mux_l2_in_3_:A1 1e-06 +4 mux_right_ipin_6\/mux_l2_in_3_:A1 1e-06 +5 chany_top_in[19]:5 3.608005e-05 +6 chany_top_in[19]:6 0.0001604091 +7 chany_top_in[19]:7 7.16752e-05 +8 chany_top_in[19]:8 2.500697e-05 +9 chany_top_in[19]:9 6.218243e-05 +10 chany_top_in[19]:10 0.0002035067 +11 chany_top_in[19]:11 0.0001732204 +12 chany_top_in[19]:12 0.0002874956 +13 chany_top_in[19]:13 0.0003413744 +14 chany_top_in[19]:14 0.001681815 +15 chany_top_in[19]:15 0.001659337 +16 chany_top_in[19]:16 0.0001071305 +17 chany_top_in[19]:17 7.572909e-05 +18 chany_top_in[19]:18 5.201111e-05 +19 chany_top_in[19]:19 0.0003243946 +20 chany_top_in[19]:20 0.0002973904 +21 chany_top_in[19]:21 0.0003989969 +22 chany_top_in[19]:22 0.0003989969 +23 chany_top_in[19]:23 0.0001024065 +24 chany_top_in[19]:24 0.0003751647 +25 chany_top_in[19]:25 0.0003444334 +26 chany_top_in[19]:26 0.0002606335 +27 chany_top_in[19]:27 0.0004127277 +28 chany_top_in[19]:28 5.881162e-05 +29 chany_top_in[19]:29 0.0003875766 +30 chany_top_in[19]:30 0.0003542327 +31 chany_top_in[19]:31 0.0003662966 +32 chany_top_in[19]:32 0.0003662966 +33 chany_top_in[19]:33 0.001461924 +34 chany_top_in[19]:34 0.001461924 +35 chany_top_in[19]:35 0.0002875524 +36 chany_top_in[19]:36 0.0002875524 +37 chany_top_in[19]:37 6.951681e-05 +38 chany_top_in[19]:33 chany_bottom_in[14]:20 0.0003432025 +39 chany_top_in[19]:33 chany_bottom_in[14]:28 0.0001811995 +40 chany_top_in[19]:34 chany_bottom_in[14]:19 0.0003432025 +41 chany_top_in[19]:34 chany_bottom_in[14]:20 0.0001811995 +42 chany_top_in[19]:33 chany_top_in[16]:43 0.0007602446 +43 chany_top_in[19]:34 chany_top_in[16]:44 0.0007602446 +44 chany_top_in[19]:26 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000141867 +45 chany_top_in[19]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.232403e-06 +46 chany_top_in[19]:27 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.232403e-06 +47 chany_top_in[19]:27 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000141867 +48 chany_top_in[19]:26 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.116457e-05 +49 chany_top_in[19]:27 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.116457e-05 +50 chany_top_in[19]:11 ropt_net_155:3 6.083472e-05 +51 chany_top_in[19]:10 ropt_net_155:2 6.083472e-05 + +*RES +0 chany_top_in[19] chany_top_in[19]:37 0.0006183035 +1 chany_top_in[19]:9 FTB_40__39:A 0.152 +2 chany_top_in[19]:11 chany_top_in[19]:10 0.002424107 +3 chany_top_in[19]:12 chany_top_in[19]:11 0.0045 +4 chany_top_in[19]:18 chany_top_in[19]:17 0.0045 +5 chany_top_in[19]:18 chany_top_in[19]:8 0.0001902174 +6 chany_top_in[19]:17 chany_top_in[19]:16 0.0008705356 +7 chany_top_in[19]:20 chany_top_in[19]:19 0.00365625 +8 chany_top_in[19]:21 chany_top_in[19]:20 0.0045 +9 chany_top_in[19]:23 chany_top_in[19]:22 0.0045 +10 chany_top_in[19]:23 chany_top_in[19]:7 0.0008772322 +11 chany_top_in[19]:22 chany_top_in[19]:21 0.004473215 +12 chany_top_in[19]:25 chany_top_in[19]:24 0.00365625 +13 chany_top_in[19]:26 chany_top_in[19]:25 0.0045 +14 chany_top_in[19]:7 mux_right_ipin_14\/mux_l2_in_3_:A1 0.152 +15 chany_top_in[19]:8 mux_right_ipin_8\/mux_l2_in_3_:A1 0.152 +16 chany_top_in[19]:30 chany_top_in[19]:29 0.005412946 +17 chany_top_in[19]:31 chany_top_in[19]:30 0.00341 +18 chany_top_in[19]:32 chany_top_in[19]:31 0.0006442916 +19 chany_top_in[19]:33 chany_top_in[19]:32 0.00341 +20 chany_top_in[19]:35 chany_top_in[19]:34 0.00341 +21 chany_top_in[19]:34 chany_top_in[19]:33 0.006602716 +22 chany_top_in[19]:37 chany_top_in[19]:36 0.00341 +23 chany_top_in[19]:36 chany_top_in[19]:35 0.000572225 +24 chany_top_in[19]:5 mux_right_ipin_6\/mux_l2_in_3_:A1 0.152 +25 chany_top_in[19]:6 chany_top_in[19]:5 0.0045 +26 chany_top_in[19]:10 chany_top_in[19]:9 0.0003035715 +27 chany_top_in[19]:19 chany_top_in[19]:18 0.0002834822 +28 chany_top_in[19]:24 chany_top_in[19]:23 0.0003035715 +29 chany_top_in[19]:13 chany_top_in[19]:12 0.004513393 +30 chany_top_in[19]:14 chany_top_in[19]:13 0.0008214286 +31 chany_top_in[19]:16 chany_top_in[19]:15 0.0004107143 +32 chany_top_in[19]:15 chany_top_in[19]:14 0.02610714 +33 chany_top_in[19]:29 chany_top_in[19]:28 0.0004107143 +34 chany_top_in[19]:28 chany_top_in[19]:27 0.0003035715 +35 chany_top_in[19]:27 chany_top_in[19]:26 0.006334822 +36 chany_top_in[19]:27 chany_top_in[19]:6 0.002053571 + +*END + +*D_NET left_grid_pin_10_[0] 0.003145948 //LENGTH 24.945 LUMPCC 0.0004878661 DR + +*CONN +*I mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.440 60.860 +*P left_grid_pin_10_[0] O *L 0.7423 *C 1.298 78.880 +*N left_grid_pin_10_[0]:2 *C 1.380 78.880 +*N left_grid_pin_10_[0]:3 *C 1.380 78.880 +*N left_grid_pin_10_[0]:4 *C 2.300 78.880 +*N left_grid_pin_10_[0]:5 *C 2.300 60.565 +*N left_grid_pin_10_[0]:6 *C 2.345 60.520 +*N left_grid_pin_10_[0]:7 *C 6.440 60.520 +*N left_grid_pin_10_[0]:8 *C 6.440 60.860 + +*CAP +0 mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_10_[0] 3.040809e-05 +2 left_grid_pin_10_[0]:2 3.040809e-05 +3 left_grid_pin_10_[0]:3 8.520321e-05 +4 left_grid_pin_10_[0]:4 0.000949875 +5 left_grid_pin_10_[0]:5 0.0008970423 +6 left_grid_pin_10_[0]:6 0.0002886575 +7 left_grid_pin_10_[0]:7 0.0003172237 +8 left_grid_pin_10_[0]:8 5.82642e-05 +9 left_grid_pin_10_[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002439331 +10 left_grid_pin_10_[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002439331 + +*RES +0 mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_10_[0]:8 0.152 +1 left_grid_pin_10_[0]:3 left_grid_pin_10_[0]:2 0.00341 +2 left_grid_pin_10_[0]:2 left_grid_pin_10_[0] 2.35e-05 +3 left_grid_pin_10_[0]:6 left_grid_pin_10_[0]:5 0.0045 +4 left_grid_pin_10_[0]:5 left_grid_pin_10_[0]:4 0.01635268 +5 left_grid_pin_10_[0]:8 left_grid_pin_10_[0]:7 0.0003035715 +6 left_grid_pin_10_[0]:7 left_grid_pin_10_[0]:6 0.003656251 +7 left_grid_pin_10_[0]:4 left_grid_pin_10_[0]:3 0.0008214285 + +*END + +*D_NET left_grid_pin_15_[0] 0.001307274 //LENGTH 13.750 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 44.540 +*P left_grid_pin_15_[0] O *L 0.7423 *C 1.230 34.000 +*N left_grid_pin_15_[0]:2 *C 3.213 34.000 +*N left_grid_pin_15_[0]:3 *C 3.220 34.058 +*N left_grid_pin_15_[0]:4 *C 3.220 44.495 +*N left_grid_pin_15_[0]:5 *C 3.243 44.540 +*N left_grid_pin_15_[0]:6 *C 3.610 44.540 + +*CAP +0 mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_15_[0] 0.0001313756 +2 left_grid_pin_15_[0]:2 0.0001313756 +3 left_grid_pin_15_[0]:3 0.0004814668 +4 left_grid_pin_15_[0]:4 0.0004814668 +5 left_grid_pin_15_[0]:5 4.02944e-05 +6 left_grid_pin_15_[0]:6 4.02944e-05 + +*RES +0 mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_15_[0]:6 0.152 +1 left_grid_pin_15_[0]:6 left_grid_pin_15_[0]:5 0.0001997283 +2 left_grid_pin_15_[0]:5 left_grid_pin_15_[0]:4 0.0045 +3 left_grid_pin_15_[0]:4 left_grid_pin_15_[0]:3 0.009319197 +4 left_grid_pin_15_[0]:3 left_grid_pin_15_[0]:2 0.00341 +5 left_grid_pin_15_[0]:2 left_grid_pin_15_[0] 0.0003105917 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.003623479 //LENGTH 26.585 LUMPCC 0.000189627 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.165 75.140 +*I mux_right_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 38.740 77.815 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 37.435 82.620 +*I mux_right_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 38.300 85.340 +*I mux_right_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 41.960 85.340 +*I mux_right_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 33.220 78.200 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 33.258 78.200 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 41.922 85.340 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 38.337 85.340 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 38.180 85.295 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 38.180 82.620 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 37.435 82.620 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 37.260 82.620 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 37.260 82.620 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 37.260 78.245 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 37.260 78.170 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 37.260 77.860 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 38.778 77.810 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 38.797 77.520 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 41.815 77.520 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 41.860 77.475 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 41.860 75.185 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 41.860 75.140 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 42.165 75.140 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_0\/mux_l2_in_1_:S 1e-06 +2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_ipin_0\/mux_l2_in_3_:S 1e-06 +4 mux_right_ipin_0\/mux_l2_in_2_:S 1e-06 +5 mux_right_ipin_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 0.0002813195 +7 mux_tree_tapbuf_size10_1_sram[1]:7 0.0002860018 +8 mux_tree_tapbuf_size10_1_sram[1]:8 0.0002860018 +9 mux_tree_tapbuf_size10_1_sram[1]:9 0.0001894572 +10 mux_tree_tapbuf_size10_1_sram[1]:10 0.0002466064 +11 mux_tree_tapbuf_size10_1_sram[1]:11 5.822968e-05 +12 mux_tree_tapbuf_size10_1_sram[1]:12 6.055878e-05 +13 mux_tree_tapbuf_size10_1_sram[1]:13 0.0002847191 +14 mux_tree_tapbuf_size10_1_sram[1]:14 0.0002275699 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0003121174 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0001382525 +17 mux_tree_tapbuf_size10_1_sram[1]:17 0.0001348985 +18 mux_tree_tapbuf_size10_1_sram[1]:18 0.0002436488 +19 mux_tree_tapbuf_size10_1_sram[1]:19 0.000216205 +20 mux_tree_tapbuf_size10_1_sram[1]:20 0.0001776407 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.0001776407 +22 mux_tree_tapbuf_size10_1_sram[1]:22 5.376023e-05 +23 mux_tree_tapbuf_size10_1_sram[1]:23 5.322468e-05 +24 mux_tree_tapbuf_size10_1_sram[1]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.067874e-05 +25 mux_tree_tapbuf_size10_1_sram[1]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.067874e-05 +26 mux_tree_tapbuf_size10_1_sram[1]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 5.180895e-06 +27 mux_tree_tapbuf_size10_1_sram[1]:14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 2.596699e-05 +28 mux_tree_tapbuf_size10_1_sram[1]:13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 2.596699e-05 +29 mux_tree_tapbuf_size10_1_sram[1]:17 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 2.298687e-05 +30 mux_tree_tapbuf_size10_1_sram[1]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.180895e-06 +31 mux_tree_tapbuf_size10_1_sram[1]:16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 2.298687e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:23 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:8 mux_right_ipin_0\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[1]:8 mux_tree_tapbuf_size10_1_sram[1]:7 0.003200893 +3 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:6 0.003573661 +5 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[1]:13 0.00390625 +6 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 9.51087e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:10 0.0008214285 +9 mux_tree_tapbuf_size10_1_sram[1]:11 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_1_sram[1]:17 mux_right_ipin_0\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.001354911 +12 mux_tree_tapbuf_size10_1_sram[1]:6 mux_right_ipin_0\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_1_sram[1]:7 mux_right_ipin_0\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.002694197 +15 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.0045 +16 mux_tree_tapbuf_size10_1_sram[1]:22 mux_tree_tapbuf_size10_1_sram[1]:21 0.0045 +17 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.002044643 +18 mux_tree_tapbuf_size10_1_sram[1]:23 mux_tree_tapbuf_size10_1_sram[1]:22 0.0001657609 +19 mux_tree_tapbuf_size10_1_sram[1]:9 mux_tree_tapbuf_size10_1_sram[1]:8 0.0045 +20 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.0002767857 +21 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[1]:17 0.0001686047 +22 mux_tree_tapbuf_size10_1_sram[1]:10 mux_tree_tapbuf_size10_1_sram[1]:9 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[2] 0.002591565 //LENGTH 18.620 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 12.265 77.520 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 7.075 75.140 +*I mux_right_ipin_4\/mux_l3_in_1_:S I *L 0.00357 *C 11.600 79.950 +*I mux_right_ipin_4\/mux_l3_in_0_:S I *L 0.00357 *C 14.820 82.960 +*N mux_tree_tapbuf_size10_3_sram[2]:4 *C 14.783 82.960 +*N mux_tree_tapbuf_size10_3_sram[2]:5 *C 11.545 82.960 +*N mux_tree_tapbuf_size10_3_sram[2]:6 *C 11.500 82.915 +*N mux_tree_tapbuf_size10_3_sram[2]:7 *C 11.600 79.950 +*N mux_tree_tapbuf_size10_3_sram[2]:8 *C 11.500 79.560 +*N mux_tree_tapbuf_size10_3_sram[2]:9 *C 11.500 79.560 +*N mux_tree_tapbuf_size10_3_sram[2]:10 *C 11.500 78.200 +*N mux_tree_tapbuf_size10_3_sram[2]:11 *C 11.960 78.200 +*N mux_tree_tapbuf_size10_3_sram[2]:12 *C 7.113 75.140 +*N mux_tree_tapbuf_size10_3_sram[2]:13 *C 11.915 75.140 +*N mux_tree_tapbuf_size10_3_sram[2]:14 *C 11.960 75.185 +*N mux_tree_tapbuf_size10_3_sram[2]:15 *C 11.960 77.520 +*N mux_tree_tapbuf_size10_3_sram[2]:16 *C 11.960 77.520 +*N mux_tree_tapbuf_size10_3_sram[2]:17 *C 12.265 77.520 + +*CAP +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_ipin_4\/mux_l3_in_1_:S 1e-06 +3 mux_right_ipin_4\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_3_sram[2]:4 0.0002385079 +5 mux_tree_tapbuf_size10_3_sram[2]:5 0.0002385079 +6 mux_tree_tapbuf_size10_3_sram[2]:6 0.0002156815 +7 mux_tree_tapbuf_size10_3_sram[2]:7 6.171483e-05 +8 mux_tree_tapbuf_size10_3_sram[2]:8 6.616999e-05 +9 mux_tree_tapbuf_size10_3_sram[2]:9 0.0003280528 +10 mux_tree_tapbuf_size10_3_sram[2]:10 0.0001109089 +11 mux_tree_tapbuf_size10_3_sram[2]:11 8.227136e-05 +12 mux_tree_tapbuf_size10_3_sram[2]:12 0.000341455 +13 mux_tree_tapbuf_size10_3_sram[2]:13 0.000341455 +14 mux_tree_tapbuf_size10_3_sram[2]:14 0.0001814227 +15 mux_tree_tapbuf_size10_3_sram[2]:15 0.0002564933 +16 mux_tree_tapbuf_size10_3_sram[2]:16 6.55339e-05 +17 mux_tree_tapbuf_size10_3_sram[2]:17 5.938995e-05 + +*RES +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_3_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_3_sram[2]:12 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size10_3_sram[2]:13 mux_tree_tapbuf_size10_3_sram[2]:12 0.004287947 +3 mux_tree_tapbuf_size10_3_sram[2]:14 mux_tree_tapbuf_size10_3_sram[2]:13 0.0045 +4 mux_tree_tapbuf_size10_3_sram[2]:8 mux_tree_tapbuf_size10_3_sram[2]:7 0.0003482143 +5 mux_tree_tapbuf_size10_3_sram[2]:9 mux_tree_tapbuf_size10_3_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size10_3_sram[2]:9 mux_tree_tapbuf_size10_3_sram[2]:6 0.002995536 +7 mux_tree_tapbuf_size10_3_sram[2]:7 mux_right_ipin_4\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_3_sram[2]:5 mux_tree_tapbuf_size10_3_sram[2]:4 0.002890625 +9 mux_tree_tapbuf_size10_3_sram[2]:6 mux_tree_tapbuf_size10_3_sram[2]:5 0.0045 +10 mux_tree_tapbuf_size10_3_sram[2]:4 mux_right_ipin_4\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size10_3_sram[2]:16 mux_tree_tapbuf_size10_3_sram[2]:15 0.0045 +12 mux_tree_tapbuf_size10_3_sram[2]:15 mux_tree_tapbuf_size10_3_sram[2]:14 0.002084822 +13 mux_tree_tapbuf_size10_3_sram[2]:15 mux_tree_tapbuf_size10_3_sram[2]:11 0.0006071429 +14 mux_tree_tapbuf_size10_3_sram[2]:17 mux_tree_tapbuf_size10_3_sram[2]:16 0.0001657609 +15 mux_tree_tapbuf_size10_3_sram[2]:10 mux_tree_tapbuf_size10_3_sram[2]:9 0.001214286 +16 mux_tree_tapbuf_size10_3_sram[2]:11 mux_tree_tapbuf_size10_3_sram[2]:10 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[0] 0.008462512 //LENGTH 63.432 LUMPCC 0.0007649624 DR + +*CONN +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.985 39.440 +*I mux_right_ipin_8\/mux_l1_in_1_:S I *L 0.00357 *C 30.920 39.440 +*I mux_right_ipin_8\/mux_l1_in_0_:S I *L 0.00357 *C 29.080 36.430 +*I mux_right_ipin_8\/mux_l1_in_2_:S I *L 0.00357 *C 28.160 29.240 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 26.395 26.180 +*N mux_tree_tapbuf_size10_5_sram[0]:5 *C 29.100 36.720 +*N mux_tree_tapbuf_size10_5_sram[0]:6 *C 26.395 26.180 +*N mux_tree_tapbuf_size10_5_sram[0]:7 *C 26.220 26.180 +*N mux_tree_tapbuf_size10_5_sram[0]:8 *C 26.220 26.225 +*N mux_tree_tapbuf_size10_5_sram[0]:9 *C 26.220 27.835 +*N mux_tree_tapbuf_size10_5_sram[0]:10 *C 26.265 27.880 +*N mux_tree_tapbuf_size10_5_sram[0]:11 *C 28.015 27.880 +*N mux_tree_tapbuf_size10_5_sram[0]:12 *C 28.060 27.925 +*N mux_tree_tapbuf_size10_5_sram[0]:13 *C 28.060 29.240 +*N mux_tree_tapbuf_size10_5_sram[0]:14 *C 28.060 29.240 +*N mux_tree_tapbuf_size10_5_sram[0]:15 *C 28.060 35.995 +*N mux_tree_tapbuf_size10_5_sram[0]:16 *C 28.105 36.040 +*N mux_tree_tapbuf_size10_5_sram[0]:17 *C 29.080 36.040 +*N mux_tree_tapbuf_size10_5_sram[0]:18 *C 29.080 36.430 +*N mux_tree_tapbuf_size10_5_sram[0]:19 *C 29.155 36.720 +*N mux_tree_tapbuf_size10_5_sram[0]:20 *C 31.235 36.720 +*N mux_tree_tapbuf_size10_5_sram[0]:21 *C 31.280 36.765 +*N mux_tree_tapbuf_size10_5_sram[0]:22 *C 30.935 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:23 *C 31.258 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:24 *C 31.280 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:25 *C 31.288 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:26 *C 72.672 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:27 *C 72.680 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:28 *C 72.680 39.440 +*N mux_tree_tapbuf_size10_5_sram[0]:29 *C 72.985 39.440 + +*CAP +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_8\/mux_l1_in_1_:S 1e-06 +2 mux_right_ipin_8\/mux_l1_in_0_:S 1e-06 +3 mux_right_ipin_8\/mux_l1_in_2_:S 1e-06 +4 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_5_sram[0]:5 3.052144e-05 +6 mux_tree_tapbuf_size10_5_sram[0]:6 4.639724e-05 +7 mux_tree_tapbuf_size10_5_sram[0]:7 5.080244e-05 +8 mux_tree_tapbuf_size10_5_sram[0]:8 0.0001090728 +9 mux_tree_tapbuf_size10_5_sram[0]:9 0.0001090728 +10 mux_tree_tapbuf_size10_5_sram[0]:10 0.0001080754 +11 mux_tree_tapbuf_size10_5_sram[0]:11 0.0001080754 +12 mux_tree_tapbuf_size10_5_sram[0]:12 8.631101e-05 +13 mux_tree_tapbuf_size10_5_sram[0]:13 3.664929e-05 +14 mux_tree_tapbuf_size10_5_sram[0]:14 0.0005251641 +15 mux_tree_tapbuf_size10_5_sram[0]:15 0.0004062395 +16 mux_tree_tapbuf_size10_5_sram[0]:16 9.359036e-05 +17 mux_tree_tapbuf_size10_5_sram[0]:17 0.0001190731 +18 mux_tree_tapbuf_size10_5_sram[0]:18 0.0001019501 +19 mux_tree_tapbuf_size10_5_sram[0]:19 0.0002027052 +20 mux_tree_tapbuf_size10_5_sram[0]:20 0.0001658131 +21 mux_tree_tapbuf_size10_5_sram[0]:21 0.000190594 +22 mux_tree_tapbuf_size10_5_sram[0]:22 5.3507e-05 +23 mux_tree_tapbuf_size10_5_sram[0]:23 5.3507e-05 +24 mux_tree_tapbuf_size10_5_sram[0]:24 0.0002278187 +25 mux_tree_tapbuf_size10_5_sram[0]:25 0.002373043 +26 mux_tree_tapbuf_size10_5_sram[0]:26 0.002373043 +27 mux_tree_tapbuf_size10_5_sram[0]:27 2.965963e-05 +28 mux_tree_tapbuf_size10_5_sram[0]:28 4.801667e-05 +29 mux_tree_tapbuf_size10_5_sram[0]:29 4.384582e-05 +30 mux_tree_tapbuf_size10_5_sram[0]:25 prog_clk[0]:234 3.369817e-05 +31 mux_tree_tapbuf_size10_5_sram[0]:25 prog_clk[0]:268 0.000297919 +32 mux_tree_tapbuf_size10_5_sram[0]:26 prog_clk[0]:233 3.369817e-05 +33 mux_tree_tapbuf_size10_5_sram[0]:26 prog_clk[0]:267 0.000297919 +34 mux_tree_tapbuf_size10_5_sram[0]:11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.086404e-05 +35 mux_tree_tapbuf_size10_5_sram[0]:10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.086404e-05 + +*RES +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_5_sram[0]:29 0.152 +1 mux_tree_tapbuf_size10_5_sram[0]:23 mux_tree_tapbuf_size10_5_sram[0]:22 0.0001752718 +2 mux_tree_tapbuf_size10_5_sram[0]:24 mux_tree_tapbuf_size10_5_sram[0]:23 0.0045 +3 mux_tree_tapbuf_size10_5_sram[0]:24 mux_tree_tapbuf_size10_5_sram[0]:21 0.002388393 +4 mux_tree_tapbuf_size10_5_sram[0]:22 mux_right_ipin_8\/mux_l1_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_5_sram[0]:16 mux_tree_tapbuf_size10_5_sram[0]:15 0.0045 +6 mux_tree_tapbuf_size10_5_sram[0]:15 mux_tree_tapbuf_size10_5_sram[0]:14 0.00603125 +7 mux_tree_tapbuf_size10_5_sram[0]:18 mux_right_ipin_8\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_5_sram[0]:18 mux_tree_tapbuf_size10_5_sram[0]:17 0.0003482143 +9 mux_tree_tapbuf_size10_5_sram[0]:18 mux_tree_tapbuf_size10_5_sram[0]:5 0.0002589286 +10 mux_tree_tapbuf_size10_5_sram[0]:13 mux_right_ipin_8\/mux_l1_in_2_:S 0.152 +11 mux_tree_tapbuf_size10_5_sram[0]:14 mux_tree_tapbuf_size10_5_sram[0]:13 0.0045 +12 mux_tree_tapbuf_size10_5_sram[0]:14 mux_tree_tapbuf_size10_5_sram[0]:12 0.001174107 +13 mux_tree_tapbuf_size10_5_sram[0]:20 mux_tree_tapbuf_size10_5_sram[0]:19 0.001857143 +14 mux_tree_tapbuf_size10_5_sram[0]:21 mux_tree_tapbuf_size10_5_sram[0]:20 0.0045 +15 mux_tree_tapbuf_size10_5_sram[0]:11 mux_tree_tapbuf_size10_5_sram[0]:10 0.0015625 +16 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:11 0.0045 +17 mux_tree_tapbuf_size10_5_sram[0]:10 mux_tree_tapbuf_size10_5_sram[0]:9 0.0045 +18 mux_tree_tapbuf_size10_5_sram[0]:9 mux_tree_tapbuf_size10_5_sram[0]:8 0.0014375 +19 mux_tree_tapbuf_size10_5_sram[0]:7 mux_tree_tapbuf_size10_5_sram[0]:6 9.51087e-05 +20 mux_tree_tapbuf_size10_5_sram[0]:8 mux_tree_tapbuf_size10_5_sram[0]:7 0.0045 +21 mux_tree_tapbuf_size10_5_sram[0]:6 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size10_5_sram[0]:25 mux_tree_tapbuf_size10_5_sram[0]:24 0.00341 +23 mux_tree_tapbuf_size10_5_sram[0]:27 mux_tree_tapbuf_size10_5_sram[0]:26 0.00341 +24 mux_tree_tapbuf_size10_5_sram[0]:26 mux_tree_tapbuf_size10_5_sram[0]:25 0.006483649 +25 mux_tree_tapbuf_size10_5_sram[0]:28 mux_tree_tapbuf_size10_5_sram[0]:27 0.0045 +26 mux_tree_tapbuf_size10_5_sram[0]:29 mux_tree_tapbuf_size10_5_sram[0]:28 0.0001657609 +27 mux_tree_tapbuf_size10_5_sram[0]:17 mux_tree_tapbuf_size10_5_sram[0]:16 0.0008705358 +28 mux_tree_tapbuf_size10_5_sram[0]:19 mux_tree_tapbuf_size10_5_sram[0]:18 0.0002589286 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[0] 0.006130298 //LENGTH 45.705 LUMPCC 0.0007553326 DR + +*CONN +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 33.885 20.400 +*I mux_right_ipin_13\/mux_l1_in_0_:S I *L 0.00357 *C 58.060 12.240 +*I mux_right_ipin_13\/mux_l1_in_1_:S I *L 0.00357 *C 53.940 12.920 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 55.375 15.300 +*I mux_right_ipin_13\/mux_l1_in_2_:S I *L 0.00357 *C 39.000 20.110 +*N mux_tree_tapbuf_size10_8_sram[0]:5 *C 39.000 20.110 +*N mux_tree_tapbuf_size10_8_sram[0]:6 *C 55.375 15.300 +*N mux_tree_tapbuf_size10_8_sram[0]:7 *C 55.660 15.300 +*N mux_tree_tapbuf_size10_8_sram[0]:8 *C 55.660 15.255 +*N mux_tree_tapbuf_size10_8_sram[0]:9 *C 53.977 12.920 +*N mux_tree_tapbuf_size10_8_sram[0]:10 *C 55.615 12.920 +*N mux_tree_tapbuf_size10_8_sram[0]:11 *C 55.660 12.920 +*N mux_tree_tapbuf_size10_8_sram[0]:12 *C 58.023 12.240 +*N mux_tree_tapbuf_size10_8_sram[0]:13 *C 57.500 12.240 +*N mux_tree_tapbuf_size10_8_sram[0]:14 *C 57.500 11.900 +*N mux_tree_tapbuf_size10_8_sram[0]:15 *C 55.705 11.900 +*N mux_tree_tapbuf_size10_8_sram[0]:16 *C 55.660 11.900 +*N mux_tree_tapbuf_size10_8_sram[0]:17 *C 55.660 10.245 +*N mux_tree_tapbuf_size10_8_sram[0]:18 *C 55.615 10.200 +*N mux_tree_tapbuf_size10_8_sram[0]:19 *C 51.520 10.200 +*N mux_tree_tapbuf_size10_8_sram[0]:20 *C 51.520 9.860 +*N mux_tree_tapbuf_size10_8_sram[0]:21 *C 49.680 9.860 +*N mux_tree_tapbuf_size10_8_sram[0]:22 *C 49.680 10.200 +*N mux_tree_tapbuf_size10_8_sram[0]:23 *C 40.525 10.200 +*N mux_tree_tapbuf_size10_8_sram[0]:24 *C 40.480 10.245 +*N mux_tree_tapbuf_size10_8_sram[0]:25 *C 40.480 19.675 +*N mux_tree_tapbuf_size10_8_sram[0]:26 *C 40.435 19.720 +*N mux_tree_tapbuf_size10_8_sram[0]:27 *C 39.000 19.720 +*N mux_tree_tapbuf_size10_8_sram[0]:28 *C 34.040 19.720 +*N mux_tree_tapbuf_size10_8_sram[0]:29 *C 33.885 20.400 + +*CAP +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_13\/mux_l1_in_0_:S 1e-06 +2 mux_right_ipin_13\/mux_l1_in_1_:S 1e-06 +3 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_ipin_13\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_8_sram[0]:5 6.357166e-05 +6 mux_tree_tapbuf_size10_8_sram[0]:6 5.352029e-05 +7 mux_tree_tapbuf_size10_8_sram[0]:7 5.569563e-05 +8 mux_tree_tapbuf_size10_8_sram[0]:8 0.0001378584 +9 mux_tree_tapbuf_size10_8_sram[0]:9 0.0001291197 +10 mux_tree_tapbuf_size10_8_sram[0]:10 0.0001291197 +11 mux_tree_tapbuf_size10_8_sram[0]:11 0.0002244135 +12 mux_tree_tapbuf_size10_8_sram[0]:12 5.75828e-05 +13 mux_tree_tapbuf_size10_8_sram[0]:13 8.49435e-05 +14 mux_tree_tapbuf_size10_8_sram[0]:14 0.0001105915 +15 mux_tree_tapbuf_size10_8_sram[0]:15 8.323076e-05 +16 mux_tree_tapbuf_size10_8_sram[0]:16 0.00018659 +17 mux_tree_tapbuf_size10_8_sram[0]:17 0.0001005284 +18 mux_tree_tapbuf_size10_8_sram[0]:18 0.000299439 +19 mux_tree_tapbuf_size10_8_sram[0]:19 0.0003280428 +20 mux_tree_tapbuf_size10_8_sram[0]:20 0.0001615573 +21 mux_tree_tapbuf_size10_8_sram[0]:21 0.0001562864 +22 mux_tree_tapbuf_size10_8_sram[0]:22 0.000501074 +23 mux_tree_tapbuf_size10_8_sram[0]:23 0.0004777411 +24 mux_tree_tapbuf_size10_8_sram[0]:24 0.0004864971 +25 mux_tree_tapbuf_size10_8_sram[0]:25 0.0004864971 +26 mux_tree_tapbuf_size10_8_sram[0]:26 0.0001106443 +27 mux_tree_tapbuf_size10_8_sram[0]:27 0.0004841082 +28 mux_tree_tapbuf_size10_8_sram[0]:28 0.0003861519 +29 mux_tree_tapbuf_size10_8_sram[0]:29 7.516053e-05 +30 mux_tree_tapbuf_size10_8_sram[0]:9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.051555e-06 +31 mux_tree_tapbuf_size10_8_sram[0]:10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.051555e-06 +32 mux_tree_tapbuf_size10_8_sram[0]:15 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.766937e-05 +33 mux_tree_tapbuf_size10_8_sram[0]:14 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.766937e-05 +34 mux_tree_tapbuf_size10_8_sram[0]:24 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.699594e-05 +35 mux_tree_tapbuf_size10_8_sram[0]:26 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.050153e-06 +36 mux_tree_tapbuf_size10_8_sram[0]:25 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.699594e-05 +37 mux_tree_tapbuf_size10_8_sram[0]:27 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.050153e-06 +38 mux_tree_tapbuf_size10_8_sram[0]:23 ropt_net_156:5 0.0001747665 +39 mux_tree_tapbuf_size10_8_sram[0]:23 ropt_net_156:3 4.213273e-05 +40 mux_tree_tapbuf_size10_8_sram[0]:22 ropt_net_156:2 4.213273e-05 +41 mux_tree_tapbuf_size10_8_sram[0]:22 ropt_net_156:4 0.0001747665 + +*RES +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_8_sram[0]:29 0.152 +1 mux_tree_tapbuf_size10_8_sram[0]:9 mux_right_ipin_13\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_8_sram[0]:10 mux_tree_tapbuf_size10_8_sram[0]:9 0.001462054 +3 mux_tree_tapbuf_size10_8_sram[0]:11 mux_tree_tapbuf_size10_8_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size10_8_sram[0]:11 mux_tree_tapbuf_size10_8_sram[0]:8 0.002084821 +5 mux_tree_tapbuf_size10_8_sram[0]:18 mux_tree_tapbuf_size10_8_sram[0]:17 0.0045 +6 mux_tree_tapbuf_size10_8_sram[0]:17 mux_tree_tapbuf_size10_8_sram[0]:16 0.001477679 +7 mux_tree_tapbuf_size10_8_sram[0]:23 mux_tree_tapbuf_size10_8_sram[0]:22 0.008174107 +8 mux_tree_tapbuf_size10_8_sram[0]:24 mux_tree_tapbuf_size10_8_sram[0]:23 0.0045 +9 mux_tree_tapbuf_size10_8_sram[0]:26 mux_tree_tapbuf_size10_8_sram[0]:25 0.0045 +10 mux_tree_tapbuf_size10_8_sram[0]:25 mux_tree_tapbuf_size10_8_sram[0]:24 0.008419644 +11 mux_tree_tapbuf_size10_8_sram[0]:15 mux_tree_tapbuf_size10_8_sram[0]:14 0.001602679 +12 mux_tree_tapbuf_size10_8_sram[0]:16 mux_tree_tapbuf_size10_8_sram[0]:15 0.0045 +13 mux_tree_tapbuf_size10_8_sram[0]:16 mux_tree_tapbuf_size10_8_sram[0]:11 0.0009107143 +14 mux_tree_tapbuf_size10_8_sram[0]:12 mux_right_ipin_13\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size10_8_sram[0]:29 mux_tree_tapbuf_size10_8_sram[0]:28 0.0006071429 +16 mux_tree_tapbuf_size10_8_sram[0]:5 mux_right_ipin_13\/mux_l1_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_8_sram[0]:7 mux_tree_tapbuf_size10_8_sram[0]:6 0.0001548913 +18 mux_tree_tapbuf_size10_8_sram[0]:8 mux_tree_tapbuf_size10_8_sram[0]:7 0.0045 +19 mux_tree_tapbuf_size10_8_sram[0]:6 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size10_8_sram[0]:28 mux_tree_tapbuf_size10_8_sram[0]:27 0.004428571 +21 mux_tree_tapbuf_size10_8_sram[0]:27 mux_tree_tapbuf_size10_8_sram[0]:26 0.00128125 +22 mux_tree_tapbuf_size10_8_sram[0]:27 mux_tree_tapbuf_size10_8_sram[0]:5 0.0003482143 +23 mux_tree_tapbuf_size10_8_sram[0]:22 mux_tree_tapbuf_size10_8_sram[0]:21 0.0003035715 +24 mux_tree_tapbuf_size10_8_sram[0]:21 mux_tree_tapbuf_size10_8_sram[0]:20 0.001642857 +25 mux_tree_tapbuf_size10_8_sram[0]:20 mux_tree_tapbuf_size10_8_sram[0]:19 0.0003035715 +26 mux_tree_tapbuf_size10_8_sram[0]:19 mux_tree_tapbuf_size10_8_sram[0]:18 0.00365625 +27 mux_tree_tapbuf_size10_8_sram[0]:14 mux_tree_tapbuf_size10_8_sram[0]:13 0.0003035715 +28 mux_tree_tapbuf_size10_8_sram[0]:13 mux_tree_tapbuf_size10_8_sram[0]:12 0.0004665179 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[3] 0.001451155 //LENGTH 11.555 LUMPCC 0.0002121387 DR + +*CONN +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 10.885 91.460 +*I mem_right_ipin_2\/FTB_10__49:A I *L 0.001746 *C 5.980 88.400 +*I mux_right_ipin_2\/mux_l4_in_0_:S I *L 0.00357 *C 10.680 93.840 +*N mux_tree_tapbuf_size8_0_sram[3]:3 *C 10.580 93.840 +*N mux_tree_tapbuf_size8_0_sram[3]:4 *C 10.580 93.795 +*N mux_tree_tapbuf_size8_0_sram[3]:5 *C 6.018 88.400 +*N mux_tree_tapbuf_size8_0_sram[3]:6 *C 8.280 88.400 +*N mux_tree_tapbuf_size8_0_sram[3]:7 *C 8.280 88.740 +*N mux_tree_tapbuf_size8_0_sram[3]:8 *C 10.535 88.740 +*N mux_tree_tapbuf_size8_0_sram[3]:9 *C 10.580 88.785 +*N mux_tree_tapbuf_size8_0_sram[3]:10 *C 10.580 91.585 +*N mux_tree_tapbuf_size8_0_sram[3]:11 *C 10.580 91.460 +*N mux_tree_tapbuf_size8_0_sram[3]:12 *C 10.885 91.460 + +*CAP +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_2\/FTB_10__49:A 1e-06 +2 mux_right_ipin_2\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_0_sram[3]:3 3.223178e-05 +4 mux_tree_tapbuf_size8_0_sram[3]:4 0.0001293899 +5 mux_tree_tapbuf_size8_0_sram[3]:5 0.0001383527 +6 mux_tree_tapbuf_size8_0_sram[3]:6 0.0001611729 +7 mux_tree_tapbuf_size8_0_sram[3]:7 0.000139375 +8 mux_tree_tapbuf_size8_0_sram[3]:8 0.0001165547 +9 mux_tree_tapbuf_size8_0_sram[3]:9 0.0001396258 +10 mux_tree_tapbuf_size8_0_sram[3]:10 0.0002690157 +11 mux_tree_tapbuf_size8_0_sram[3]:11 5.726336e-05 +12 mux_tree_tapbuf_size8_0_sram[3]:12 5.303423e-05 +13 mux_tree_tapbuf_size8_0_sram[3]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.106061e-05 +14 mux_tree_tapbuf_size8_0_sram[3]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.491888e-05 +15 mux_tree_tapbuf_size8_0_sram[3]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.008988e-05 +16 mux_tree_tapbuf_size8_0_sram[3]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.491888e-05 +17 mux_tree_tapbuf_size8_0_sram[3]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.008988e-05 +18 mux_tree_tapbuf_size8_0_sram[3]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.106061e-05 + +*RES +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_0_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_0_sram[3]:5 mem_right_ipin_2\/FTB_10__49:A 0.152 +2 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:7 0.002013393 +3 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:8 0.0045 +4 mux_tree_tapbuf_size8_0_sram[3]:3 mux_right_ipin_2\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size8_0_sram[3]:4 mux_tree_tapbuf_size8_0_sram[3]:3 0.0045 +6 mux_tree_tapbuf_size8_0_sram[3]:11 mux_tree_tapbuf_size8_0_sram[3]:10 0.0045 +7 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:9 0.0025 +8 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:4 0.001973214 +9 mux_tree_tapbuf_size8_0_sram[3]:12 mux_tree_tapbuf_size8_0_sram[3]:11 0.0001657609 +10 mux_tree_tapbuf_size8_0_sram[3]:6 mux_tree_tapbuf_size8_0_sram[3]:5 0.002020089 +11 mux_tree_tapbuf_size8_0_sram[3]:7 mux_tree_tapbuf_size8_0_sram[3]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[1] 0.005438205 //LENGTH 42.060 LUMPCC 0.000132286 DR + +*CONN +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 45.385 63.920 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 39.735 60.860 +*I mux_right_ipin_6\/mux_l2_in_1_:S I *L 0.00357 *C 30.460 63.240 +*I mux_right_ipin_6\/mux_l2_in_0_:S I *L 0.00357 *C 32.300 66.640 +*I mux_right_ipin_6\/mux_l2_in_3_:S I *L 0.00357 *C 36.440 58.480 +*I mux_right_ipin_6\/mux_l2_in_2_:S I *L 0.00357 *C 41.960 58.190 +*N mux_tree_tapbuf_size8_2_sram[1]:6 *C 41.960 58.190 +*N mux_tree_tapbuf_size8_2_sram[1]:7 *C 36.477 58.480 +*N mux_tree_tapbuf_size8_2_sram[1]:8 *C 32.337 66.640 +*N mux_tree_tapbuf_size8_2_sram[1]:9 *C 35.420 66.640 +*N mux_tree_tapbuf_size8_2_sram[1]:10 *C 30.498 63.240 +*N mux_tree_tapbuf_size8_2_sram[1]:11 *C 32.660 63.240 +*N mux_tree_tapbuf_size8_2_sram[1]:12 *C 32.660 63.580 +*N mux_tree_tapbuf_size8_2_sram[1]:13 *C 35.375 63.580 +*N mux_tree_tapbuf_size8_2_sram[1]:14 *C 35.420 63.625 +*N mux_tree_tapbuf_size8_2_sram[1]:15 *C 35.420 65.915 +*N mux_tree_tapbuf_size8_2_sram[1]:16 *C 35.420 65.960 +*N mux_tree_tapbuf_size8_2_sram[1]:17 *C 39.975 65.960 +*N mux_tree_tapbuf_size8_2_sram[1]:18 *C 40.020 65.915 +*N mux_tree_tapbuf_size8_2_sram[1]:19 *C 39.758 60.833 +*N mux_tree_tapbuf_size8_2_sram[1]:20 *C 39.758 60.555 +*N mux_tree_tapbuf_size8_2_sram[1]:21 *C 39.990 60.550 +*N mux_tree_tapbuf_size8_2_sram[1]:22 *C 40.020 60.520 +*N mux_tree_tapbuf_size8_2_sram[1]:23 *C 40.020 58.525 +*N mux_tree_tapbuf_size8_2_sram[1]:24 *C 40.020 58.480 +*N mux_tree_tapbuf_size8_2_sram[1]:25 *C 41.960 58.480 +*N mux_tree_tapbuf_size8_2_sram[1]:26 *C 45.035 58.480 +*N mux_tree_tapbuf_size8_2_sram[1]:27 *C 45.080 58.525 +*N mux_tree_tapbuf_size8_2_sram[1]:28 *C 45.080 63.875 +*N mux_tree_tapbuf_size8_2_sram[1]:29 *C 45.080 63.920 +*N mux_tree_tapbuf_size8_2_sram[1]:30 *C 45.385 63.920 + +*CAP +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_ipin_6\/mux_l2_in_1_:S 1e-06 +3 mux_right_ipin_6\/mux_l2_in_0_:S 1e-06 +4 mux_right_ipin_6\/mux_l2_in_3_:S 1e-06 +5 mux_right_ipin_6\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size8_2_sram[1]:6 5.999595e-05 +7 mux_tree_tapbuf_size8_2_sram[1]:7 0.000185579 +8 mux_tree_tapbuf_size8_2_sram[1]:8 0.0002677469 +9 mux_tree_tapbuf_size8_2_sram[1]:9 0.0003144973 +10 mux_tree_tapbuf_size8_2_sram[1]:10 0.0001842753 +11 mux_tree_tapbuf_size8_2_sram[1]:11 0.0002107552 +12 mux_tree_tapbuf_size8_2_sram[1]:12 0.0002215404 +13 mux_tree_tapbuf_size8_2_sram[1]:13 0.0001950605 +14 mux_tree_tapbuf_size8_2_sram[1]:14 0.0001482943 +15 mux_tree_tapbuf_size8_2_sram[1]:15 0.0001482943 +16 mux_tree_tapbuf_size8_2_sram[1]:16 0.0003615304 +17 mux_tree_tapbuf_size8_2_sram[1]:17 0.00031478 +18 mux_tree_tapbuf_size8_2_sram[1]:18 0.0003293887 +19 mux_tree_tapbuf_size8_2_sram[1]:19 3.245475e-05 +20 mux_tree_tapbuf_size8_2_sram[1]:20 6.847113e-05 +21 mux_tree_tapbuf_size8_2_sram[1]:21 3.601638e-05 +22 mux_tree_tapbuf_size8_2_sram[1]:22 0.000482659 +23 mux_tree_tapbuf_size8_2_sram[1]:23 0.0001207818 +24 mux_tree_tapbuf_size8_2_sram[1]:24 0.0003371924 +25 mux_tree_tapbuf_size8_2_sram[1]:25 0.0003440825 +26 mux_tree_tapbuf_size8_2_sram[1]:26 0.0002048296 +27 mux_tree_tapbuf_size8_2_sram[1]:27 0.000317377 +28 mux_tree_tapbuf_size8_2_sram[1]:28 0.000317377 +29 mux_tree_tapbuf_size8_2_sram[1]:29 5.057421e-05 +30 mux_tree_tapbuf_size8_2_sram[1]:30 4.636522e-05 +31 mux_tree_tapbuf_size8_2_sram[1]:24 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.133972e-05 +32 mux_tree_tapbuf_size8_2_sram[1]:24 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.480326e-05 +33 mux_tree_tapbuf_size8_2_sram[1]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.133972e-05 +34 mux_tree_tapbuf_size8_2_sram[1]:25 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.480326e-05 + +*RES +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_2_sram[1]:30 0.152 +1 mux_tree_tapbuf_size8_2_sram[1]:19 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:20 0.0001453125 +3 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:21 0.0045 +4 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:18 0.004816964 +5 mux_tree_tapbuf_size8_2_sram[1]:8 mux_right_ipin_6\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:23 0.0045 +7 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:7 0.003162947 +8 mux_tree_tapbuf_size8_2_sram[1]:23 mux_tree_tapbuf_size8_2_sram[1]:22 0.00178125 +9 mux_tree_tapbuf_size8_2_sram[1]:16 mux_tree_tapbuf_size8_2_sram[1]:15 0.0045 +10 mux_tree_tapbuf_size8_2_sram[1]:16 mux_tree_tapbuf_size8_2_sram[1]:9 0.0006071429 +11 mux_tree_tapbuf_size8_2_sram[1]:15 mux_tree_tapbuf_size8_2_sram[1]:14 0.002044643 +12 mux_tree_tapbuf_size8_2_sram[1]:13 mux_tree_tapbuf_size8_2_sram[1]:12 0.002424107 +13 mux_tree_tapbuf_size8_2_sram[1]:14 mux_tree_tapbuf_size8_2_sram[1]:13 0.0045 +14 mux_tree_tapbuf_size8_2_sram[1]:10 mux_right_ipin_6\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:16 0.004066964 +16 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:17 0.0045 +17 mux_tree_tapbuf_size8_2_sram[1]:26 mux_tree_tapbuf_size8_2_sram[1]:25 0.002745536 +18 mux_tree_tapbuf_size8_2_sram[1]:27 mux_tree_tapbuf_size8_2_sram[1]:26 0.0045 +19 mux_tree_tapbuf_size8_2_sram[1]:29 mux_tree_tapbuf_size8_2_sram[1]:28 0.0045 +20 mux_tree_tapbuf_size8_2_sram[1]:28 mux_tree_tapbuf_size8_2_sram[1]:27 0.004776786 +21 mux_tree_tapbuf_size8_2_sram[1]:30 mux_tree_tapbuf_size8_2_sram[1]:29 0.0001657609 +22 mux_tree_tapbuf_size8_2_sram[1]:7 mux_right_ipin_6\/mux_l2_in_3_:S 0.152 +23 mux_tree_tapbuf_size8_2_sram[1]:6 mux_right_ipin_6\/mux_l2_in_2_:S 0.152 +24 mux_tree_tapbuf_size8_2_sram[1]:11 mux_tree_tapbuf_size8_2_sram[1]:10 0.001930804 +25 mux_tree_tapbuf_size8_2_sram[1]:9 mux_tree_tapbuf_size8_2_sram[1]:8 0.002752232 +26 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:11 0.0003035714 +27 mux_tree_tapbuf_size8_2_sram[1]:25 mux_tree_tapbuf_size8_2_sram[1]:24 0.001732143 +28 mux_tree_tapbuf_size8_2_sram[1]:25 mux_tree_tapbuf_size8_2_sram[1]:6 0.000125 +29 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:19 0.0001875 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[2] 0.003318155 //LENGTH 24.995 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 21.005 49.980 +*I mux_right_ipin_11\/mux_l3_in_1_:S I *L 0.00357 *C 20.800 52.360 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 7.995 53.380 +*I mux_right_ipin_11\/mux_l3_in_0_:S I *L 0.00357 *C 12.540 56.440 +*N mux_tree_tapbuf_size8_5_sram[2]:4 *C 12.503 56.440 +*N mux_tree_tapbuf_size8_5_sram[2]:5 *C 12.005 56.440 +*N mux_tree_tapbuf_size8_5_sram[2]:6 *C 11.960 56.395 +*N mux_tree_tapbuf_size8_5_sram[2]:7 *C 8.033 53.380 +*N mux_tree_tapbuf_size8_5_sram[2]:8 *C 11.915 53.380 +*N mux_tree_tapbuf_size8_5_sram[2]:9 *C 11.960 53.380 +*N mux_tree_tapbuf_size8_5_sram[2]:10 *C 11.960 52.405 +*N mux_tree_tapbuf_size8_5_sram[2]:11 *C 12.005 52.360 +*N mux_tree_tapbuf_size8_5_sram[2]:12 *C 20.800 52.360 +*N mux_tree_tapbuf_size8_5_sram[2]:13 *C 22.495 52.360 +*N mux_tree_tapbuf_size8_5_sram[2]:14 *C 22.540 52.315 +*N mux_tree_tapbuf_size8_5_sram[2]:15 *C 22.540 50.025 +*N mux_tree_tapbuf_size8_5_sram[2]:16 *C 22.495 49.980 +*N mux_tree_tapbuf_size8_5_sram[2]:17 *C 21.043 49.980 + +*CAP +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_11\/mux_l3_in_1_:S 1e-06 +2 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_11\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_5_sram[2]:4 6.488204e-05 +5 mux_tree_tapbuf_size8_5_sram[2]:5 6.488204e-05 +6 mux_tree_tapbuf_size8_5_sram[2]:6 0.0002034856 +7 mux_tree_tapbuf_size8_5_sram[2]:7 0.0002669828 +8 mux_tree_tapbuf_size8_5_sram[2]:8 0.0002669828 +9 mux_tree_tapbuf_size8_5_sram[2]:9 0.0003079737 +10 mux_tree_tapbuf_size8_5_sram[2]:10 7.388809e-05 +11 mux_tree_tapbuf_size8_5_sram[2]:11 0.0006421058 +12 mux_tree_tapbuf_size8_5_sram[2]:12 0.0007998009 +13 mux_tree_tapbuf_size8_5_sram[2]:13 0.0001308089 +14 mux_tree_tapbuf_size8_5_sram[2]:14 0.0001440059 +15 mux_tree_tapbuf_size8_5_sram[2]:15 0.0001440059 +16 mux_tree_tapbuf_size8_5_sram[2]:16 0.0001021751 +17 mux_tree_tapbuf_size8_5_sram[2]:17 0.0001021751 + +*RES +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_5_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_5_sram[2]:4 mux_right_ipin_11\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_5_sram[2]:5 mux_tree_tapbuf_size8_5_sram[2]:4 0.0004441965 +3 mux_tree_tapbuf_size8_5_sram[2]:6 mux_tree_tapbuf_size8_5_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size8_5_sram[2]:12 mux_right_ipin_11\/mux_l3_in_1_:S 0.152 +5 mux_tree_tapbuf_size8_5_sram[2]:12 mux_tree_tapbuf_size8_5_sram[2]:11 0.007852679 +6 mux_tree_tapbuf_size8_5_sram[2]:11 mux_tree_tapbuf_size8_5_sram[2]:10 0.0045 +7 mux_tree_tapbuf_size8_5_sram[2]:10 mux_tree_tapbuf_size8_5_sram[2]:9 0.0008705358 +8 mux_tree_tapbuf_size8_5_sram[2]:8 mux_tree_tapbuf_size8_5_sram[2]:7 0.003466518 +9 mux_tree_tapbuf_size8_5_sram[2]:9 mux_tree_tapbuf_size8_5_sram[2]:8 0.0045 +10 mux_tree_tapbuf_size8_5_sram[2]:9 mux_tree_tapbuf_size8_5_sram[2]:6 0.002691964 +11 mux_tree_tapbuf_size8_5_sram[2]:7 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size8_5_sram[2]:13 mux_tree_tapbuf_size8_5_sram[2]:12 0.001513393 +13 mux_tree_tapbuf_size8_5_sram[2]:14 mux_tree_tapbuf_size8_5_sram[2]:13 0.0045 +14 mux_tree_tapbuf_size8_5_sram[2]:16 mux_tree_tapbuf_size8_5_sram[2]:15 0.0045 +15 mux_tree_tapbuf_size8_5_sram[2]:15 mux_tree_tapbuf_size8_5_sram[2]:14 0.002044643 +16 mux_tree_tapbuf_size8_5_sram[2]:17 mux_tree_tapbuf_size8_5_sram[2]:16 0.001296875 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[2] 0.002525728 //LENGTH 21.070 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 78.505 75.140 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 73.315 77.180 +*I mux_right_ipin_15\/mux_l3_in_0_:S I *L 0.00357 *C 65.680 79.560 +*I mux_right_ipin_15\/mux_l3_in_1_:S I *L 0.00357 *C 77.380 79.560 +*N mux_tree_tapbuf_size8_7_sram[2]:4 *C 77.280 79.560 +*N mux_tree_tapbuf_size8_7_sram[2]:5 *C 77.280 79.515 +*N mux_tree_tapbuf_size8_7_sram[2]:6 *C 65.680 79.560 +*N mux_tree_tapbuf_size8_7_sram[2]:7 *C 65.780 79.515 +*N mux_tree_tapbuf_size8_7_sram[2]:8 *C 65.780 77.860 +*N mux_tree_tapbuf_size8_7_sram[2]:9 *C 66.240 77.860 +*N mux_tree_tapbuf_size8_7_sram[2]:10 *C 66.240 77.225 +*N mux_tree_tapbuf_size8_7_sram[2]:11 *C 66.285 77.180 +*N mux_tree_tapbuf_size8_7_sram[2]:12 *C 73.315 77.180 +*N mux_tree_tapbuf_size8_7_sram[2]:13 *C 77.235 77.180 +*N mux_tree_tapbuf_size8_7_sram[2]:14 *C 77.280 77.180 +*N mux_tree_tapbuf_size8_7_sram[2]:15 *C 77.280 75.185 +*N mux_tree_tapbuf_size8_7_sram[2]:16 *C 77.325 75.140 +*N mux_tree_tapbuf_size8_7_sram[2]:17 *C 78.468 75.140 + +*CAP +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_ipin_15\/mux_l3_in_0_:S 1e-06 +3 mux_right_ipin_15\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_7_sram[2]:4 3.29049e-05 +5 mux_tree_tapbuf_size8_7_sram[2]:5 0.0001313826 +6 mux_tree_tapbuf_size8_7_sram[2]:6 2.720963e-05 +7 mux_tree_tapbuf_size8_7_sram[2]:7 0.0001041493 +8 mux_tree_tapbuf_size8_7_sram[2]:8 0.000133972 +9 mux_tree_tapbuf_size8_7_sram[2]:9 8.143231e-05 +10 mux_tree_tapbuf_size8_7_sram[2]:10 5.160955e-05 +11 mux_tree_tapbuf_size8_7_sram[2]:11 0.0004353113 +12 mux_tree_tapbuf_size8_7_sram[2]:12 0.0007181773 +13 mux_tree_tapbuf_size8_7_sram[2]:13 0.0002562889 +14 mux_tree_tapbuf_size8_7_sram[2]:14 0.0002709978 +15 mux_tree_tapbuf_size8_7_sram[2]:15 0.000110793 +16 mux_tree_tapbuf_size8_7_sram[2]:16 8.374971e-05 +17 mux_tree_tapbuf_size8_7_sram[2]:17 8.374971e-05 + +*RES +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_7_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_7_sram[2]:6 mux_right_ipin_15\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_7_sram[2]:7 mux_tree_tapbuf_size8_7_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size8_7_sram[2]:11 mux_tree_tapbuf_size8_7_sram[2]:10 0.0045 +4 mux_tree_tapbuf_size8_7_sram[2]:10 mux_tree_tapbuf_size8_7_sram[2]:9 0.0005669643 +5 mux_tree_tapbuf_size8_7_sram[2]:16 mux_tree_tapbuf_size8_7_sram[2]:15 0.0045 +6 mux_tree_tapbuf_size8_7_sram[2]:15 mux_tree_tapbuf_size8_7_sram[2]:14 0.00178125 +7 mux_tree_tapbuf_size8_7_sram[2]:17 mux_tree_tapbuf_size8_7_sram[2]:16 0.001020089 +8 mux_tree_tapbuf_size8_7_sram[2]:13 mux_tree_tapbuf_size8_7_sram[2]:12 0.0035 +9 mux_tree_tapbuf_size8_7_sram[2]:14 mux_tree_tapbuf_size8_7_sram[2]:13 0.0045 +10 mux_tree_tapbuf_size8_7_sram[2]:14 mux_tree_tapbuf_size8_7_sram[2]:5 0.002084821 +11 mux_tree_tapbuf_size8_7_sram[2]:4 mux_right_ipin_15\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size8_7_sram[2]:5 mux_tree_tapbuf_size8_7_sram[2]:4 0.0045 +13 mux_tree_tapbuf_size8_7_sram[2]:12 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +14 mux_tree_tapbuf_size8_7_sram[2]:12 mux_tree_tapbuf_size8_7_sram[2]:11 0.006276786 +15 mux_tree_tapbuf_size8_7_sram[2]:8 mux_tree_tapbuf_size8_7_sram[2]:7 0.001477679 +16 mux_tree_tapbuf_size8_7_sram[2]:9 mux_tree_tapbuf_size8_7_sram[2]:8 0.0004107143 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.000477448 //LENGTH 2.990 LUMPCC 0.0001452347 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_2_:X O *L 0 *C 72.965 48.280 +*I mux_left_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 72.780 50.660 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 72.680 50.660 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.680 50.615 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.680 48.325 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.680 48.280 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 72.965 48.280 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.106845e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.813818e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.813818e-05 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.155449e-05 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.131401e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_0_sram[1]:25 7.261737e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:26 7.261737e-05 + +*RES +0 mux_left_ipin_0\/mux_l1_in_2_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_ipin_0\/mux_l2_in_1_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002044643 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001548913 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001147817 //LENGTH 7.830 LUMPCC 0.0004078414 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_1_:X O *L 0 *C 30.185 80.240 +*I mux_right_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 34.330 77.180 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 34.330 77.180 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 34.040 77.180 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 34.040 77.225 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 34.040 80.195 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.995 80.240 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 30.223 80.240 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.27377e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.316531e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001851169 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001851169 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001309194 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001309194 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[17]:10 0.0001507449 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[17]:11 0.0001507449 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:16 3.578079e-06 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_1_sram[0]:10 4.959774e-05 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:15 3.578079e-06 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_1_sram[0]:9 4.959774e-05 + +*RES +0 mux_right_ipin_0\/mux_l1_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001576087 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003368304 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008008546 //LENGTH 5.515 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_1\/mux_l1_in_0_:X O *L 0 *C 56.755 90.440 +*I mux_right_ipin_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 51.885 90.780 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.885 90.780 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 51.980 90.440 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 56.718 90.440 + +*CAP +0 mux_right_ipin_1\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_1\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.198791e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003836727 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003531941 + +*RES +0 mux_right_ipin_1\/mux_l1_in_0_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_1\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004229911 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006468617 //LENGTH 4.265 LUMPCC 0.0002697895 DR + +*CONN +*I mux_right_ipin_4\/mux_l1_in_1_:X O *L 0 *C 20.875 85.340 +*I mux_right_ipin_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 20.070 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 20.108 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 20.655 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 20.700 82.665 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 20.700 85.295 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 20.700 85.340 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 20.875 85.340 + +*CAP +0 mux_right_ipin_4\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.068302e-05 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.068302e-05 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001046496 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001046496 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.220657e-05 +7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.220039e-05 +8 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[15]:16 8.246173e-05 +9 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[15]:13 8.246173e-05 +10 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:14 3.448126e-05 +11 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:15 3.448126e-05 +12 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:19 1.795175e-05 +13 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_3_sram[1]:16 1.795175e-05 + +*RES +0 mux_right_ipin_4\/mux_l1_in_1_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_4\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001294915 //LENGTH 10.355 LUMPCC 0.0005149326 DR + +*CONN +*I mux_right_ipin_5\/mux_l2_in_3_:X O *L 0 *C 66.525 56.100 +*I mux_right_ipin_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 66.530 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 66.568 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 67.115 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 67.160 64.215 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 67.160 56.145 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 67.115 56.100 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 66.562 56.100 + +*CAP +0 mux_right_ipin_5\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_5\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.126758e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.126758e-05 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002721401 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002721401 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.558363e-05 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.558363e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_bottom_in[16]:19 6.929342e-05 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_bottom_in[16]:22 7.483782e-05 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_bottom_in[16]:22 6.929342e-05 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_bottom_in[16]:23 7.483782e-05 +12 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.501773e-05 +13 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.501773e-05 +14 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.831735e-05 +15 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.831735e-05 + +*RES +0 mux_right_ipin_5\/mux_l2_in_3_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_5\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.007205357 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004933036 + +*END + +*D_NET optlc_net_132 0.01024188 //LENGTH 74.030 LUMPCC 0.001509179 DR + +*CONN +*I optlc_126:HI O *L 0 *C 28.980 93.500 +*I mux_right_ipin_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 17.310 96.900 +*I mux_right_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 37.550 86.360 +*I mux_right_ipin_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 15.930 76.840 +*I mux_right_ipin_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 41.690 93.160 +*N optlc_net_132:5 *C 41.653 93.160 +*N optlc_net_132:6 *C 15.968 76.840 +*N optlc_net_132:7 *C 16.515 76.840 +*N optlc_net_132:8 *C 16.560 76.840 +*N optlc_net_132:9 *C 16.568 76.840 +*N optlc_net_132:10 *C 19.300 76.840 +*N optlc_net_132:11 *C 19.320 76.847 +*N optlc_net_132:12 *C 19.320 85.672 +*N optlc_net_132:13 *C 19.340 85.680 +*N optlc_net_132:14 *C 37.712 85.680 +*N optlc_net_132:15 *C 37.720 85.737 +*N optlc_net_132:16 *C 37.550 86.360 +*N optlc_net_132:17 *C 37.720 86.360 +*N optlc_net_132:18 *C 37.720 86.360 +*N optlc_net_132:19 *C 37.720 93.160 +*N optlc_net_132:20 *C 38.180 93.160 +*N optlc_net_132:21 *C 38.180 93.160 +*N optlc_net_132:22 *C 36.800 93.160 +*N optlc_net_132:23 *C 36.800 93.500 +*N optlc_net_132:24 *C 17.348 96.900 +*N optlc_net_132:25 *C 22.035 96.900 +*N optlc_net_132:26 *C 22.080 96.945 +*N optlc_net_132:27 *C 22.080 98.555 +*N optlc_net_132:28 *C 22.125 98.600 +*N optlc_net_132:29 *C 28.935 98.600 +*N optlc_net_132:30 *C 28.980 98.555 +*N optlc_net_132:31 *C 28.980 93.545 +*N optlc_net_132:32 *C 29.018 93.500 + +*CAP +0 optlc_126:HI 1e-06 +1 mux_right_ipin_2\/mux_l2_in_3_:A0 1e-06 +2 mux_right_ipin_0\/mux_l2_in_3_:A0 1e-06 +3 mux_right_ipin_4\/mux_l2_in_3_:A0 1e-06 +4 mux_right_ipin_1\/mux_l2_in_3_:A0 1e-06 +5 optlc_net_132:5 0.0001762955 +6 optlc_net_132:6 6.732257e-05 +7 optlc_net_132:7 6.732257e-05 +8 optlc_net_132:8 3.670265e-05 +9 optlc_net_132:9 0.0002195538 +10 optlc_net_132:10 0.0002195538 +11 optlc_net_132:11 0.0005243867 +12 optlc_net_132:12 0.0005243867 +13 optlc_net_132:13 0.001179365 +14 optlc_net_132:14 0.001179365 +15 optlc_net_132:15 4.626913e-05 +16 optlc_net_132:16 5.100566e-05 +17 optlc_net_132:17 5.47079e-05 +18 optlc_net_132:18 0.0004099069 +19 optlc_net_132:19 0.0003669122 +20 optlc_net_132:20 6.860837e-05 +21 optlc_net_132:21 0.0002914325 +22 optlc_net_132:22 0.0001040412 +23 optlc_net_132:23 0.0003914169 +24 optlc_net_132:24 0.0003205292 +25 optlc_net_132:25 0.0003205292 +26 optlc_net_132:26 0.0001081217 +27 optlc_net_132:27 0.0001081217 +28 optlc_net_132:28 0.0004143823 +29 optlc_net_132:29 0.0004143823 +30 optlc_net_132:30 0.000348381 +31 optlc_net_132:31 0.000348381 +32 optlc_net_132:32 0.0003663179 +33 optlc_net_132:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.0001150487 +34 optlc_net_132:13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.0001150487 +35 optlc_net_132:18 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.561123e-05 +36 optlc_net_132:19 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.561123e-05 +37 optlc_net_132:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.256831e-05 +38 optlc_net_132:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.256831e-05 +39 optlc_net_132:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 2.852379e-05 +40 optlc_net_132:22 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 2.852379e-05 +41 optlc_net_132:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.845091e-06 +42 optlc_net_132:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.203663e-05 +43 optlc_net_132:32 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001250916 +44 optlc_net_132:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.845091e-06 +45 optlc_net_132:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.282889e-06 +46 optlc_net_132:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.203663e-05 +47 optlc_net_132:23 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001250916 +48 optlc_net_132:22 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 3.282889e-06 +49 optlc_net_132:32 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.316936e-05 +50 optlc_net_132:23 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 9.316936e-05 +51 optlc_net_132:32 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001019305 +52 optlc_net_132:23 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001019305 +53 optlc_net_132:29 BUF_net_67:4 9.244236e-05 +54 optlc_net_132:28 BUF_net_67:3 9.244236e-05 +55 optlc_net_132:18 BUF_net_67:6 3.928459e-08 +56 optlc_net_132:19 BUF_net_67:5 3.928459e-08 + +*RES +0 optlc_126:HI optlc_net_132:32 0.152 +1 optlc_net_132:5 mux_right_ipin_1\/mux_l2_in_3_:A0 0.152 +2 optlc_net_132:15 optlc_net_132:14 0.00341 +3 optlc_net_132:14 optlc_net_132:13 0.002878358 +4 optlc_net_132:13 optlc_net_132:12 0.00341 +5 optlc_net_132:12 optlc_net_132:11 0.001382583 +6 optlc_net_132:10 optlc_net_132:9 0.0004280916 +7 optlc_net_132:11 optlc_net_132:10 0.00341 +8 optlc_net_132:8 optlc_net_132:7 0.0045 +9 optlc_net_132:9 optlc_net_132:8 0.00341 +10 optlc_net_132:7 optlc_net_132:6 0.0004888393 +11 optlc_net_132:6 mux_right_ipin_4\/mux_l2_in_3_:A0 0.152 +12 optlc_net_132:32 optlc_net_132:31 0.0045 +13 optlc_net_132:32 optlc_net_132:23 0.006948661 +14 optlc_net_132:31 optlc_net_132:30 0.004473214 +15 optlc_net_132:29 optlc_net_132:28 0.006080357 +16 optlc_net_132:30 optlc_net_132:29 0.0045 +17 optlc_net_132:28 optlc_net_132:27 0.0045 +18 optlc_net_132:27 optlc_net_132:26 0.0014375 +19 optlc_net_132:25 optlc_net_132:24 0.004185268 +20 optlc_net_132:26 optlc_net_132:25 0.0045 +21 optlc_net_132:24 mux_right_ipin_2\/mux_l2_in_3_:A0 0.152 +22 optlc_net_132:17 optlc_net_132:16 9.239131e-05 +23 optlc_net_132:18 optlc_net_132:17 0.0045 +24 optlc_net_132:18 optlc_net_132:15 0.0005558036 +25 optlc_net_132:16 mux_right_ipin_0\/mux_l2_in_3_:A0 0.152 +26 optlc_net_132:21 optlc_net_132:20 0.0045 +27 optlc_net_132:21 optlc_net_132:5 0.003100446 +28 optlc_net_132:20 optlc_net_132:19 0.0004107143 +29 optlc_net_132:23 optlc_net_132:22 0.0003035715 +30 optlc_net_132:22 optlc_net_132:21 0.001232143 +31 optlc_net_132:19 optlc_net_132:18 0.006071429 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008725281 //LENGTH 6.565 LUMPCC 0.0001694922 DR + +*CONN +*I mux_right_ipin_3\/mux_l1_in_0_:X O *L 0 *C 16.845 58.480 +*I mux_right_ipin_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 19.420 61.540 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 19.383 61.540 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 17.525 61.540 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 17.480 61.495 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 17.480 58.525 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 17.435 58.480 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 16.883 58.480 + +*CAP +0 mux_right_ipin_3\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_3\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.352873e-05 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.352873e-05 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001769497 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001769497 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.003955e-05 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.003955e-05 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size8_1_sram[1]:14 8.409122e-05 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size8_1_sram[1]:21 8.409122e-05 +10 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:17 6.548764e-07 +11 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:18 6.548764e-07 + +*RES +0 mux_right_ipin_3\/mux_l1_in_0_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_3\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001286936 //LENGTH 9.620 LUMPCC 0.0003350577 DR + +*CONN +*I mux_right_ipin_6\/mux_l3_in_0_:X O *L 0 *C 30.185 66.300 +*I mux_right_ipin_6\/mux_l4_in_0_:A1 I *L 0.00198 *C 30.725 72.420 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 30.763 72.420 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 31.695 72.420 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 31.740 72.375 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 31.740 66.345 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 31.695 66.300 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 30.223 66.300 + +*CAP +0 mux_right_ipin_6\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_6\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001018659 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001018659 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002418407 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002418407 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001312328 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001312328 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[1]:48 0.0001675289 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[1]:49 0.0001675289 + +*RES +0 mux_right_ipin_6\/mux_l3_in_0_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_6\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008325893 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.005383929 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00195039 //LENGTH 14.840 LUMPCC 0.0001794615 DR + +*CONN +*I mux_right_ipin_10\/mux_l1_in_0_:X O *L 0 *C 29.615 33.320 +*I mux_right_ipin_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.765 36.380 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.803 36.380 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 21.115 36.380 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 21.160 36.335 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 21.160 33.365 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 21.205 33.320 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 29.578 33.320 + +*CAP +0 mux_right_ipin_10\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_10\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001685759 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001685759 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001281076 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001281076 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005877806 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0005877806 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_5_sram[2]:9 8.973077e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_5_sram[2]:10 8.973077e-05 + +*RES +0 mux_right_ipin_10\/mux_l1_in_0_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_10\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002064732 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.007475447 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004687035 //LENGTH 3.640 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_11\/mux_l3_in_0_:X O *L 0 *C 9.835 55.760 +*I mux_right_ipin_11\/mux_l4_in_0_:A1 I *L 0.00198 *C 9.105 58.140 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.105 58.140 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 9.200 58.095 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 9.200 55.805 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 9.245 55.760 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 9.798 55.760 + +*CAP +0 mux_right_ipin_11\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_11\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.960597e-05 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001462357 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001462357 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.231303e-05 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.231303e-05 + +*RES +0 mux_right_ipin_11\/mux_l3_in_0_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_11\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004933036 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006038493 //LENGTH 4.550 LUMPCC 0.0001616216 DR + +*CONN +*I mux_right_ipin_15\/mux_l2_in_0_:X O *L 0 *C 65.605 77.180 +*I mux_right_ipin_15\/mux_l3_in_0_:A1 I *L 0.00198 *C 64.400 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 64.400 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 64.400 79.855 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 64.400 77.225 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 64.445 77.180 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 65.568 77.180 + +*CAP +0 mux_right_ipin_15\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_15\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.155186e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001067686 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001067686 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.756931e-05 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.756931e-05 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[10]:27 8.081078e-05 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[10] 8.081078e-05 + +*RES +0 mux_right_ipin_15\/mux_l2_in_0_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001002232 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.002348214 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_15\/mux_l3_in_0_:A1 0.152 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET chany_top_out[4] 0.00153395 //LENGTH 11.020 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 31.740 102.680 +*P chany_top_out[4] O *L 0.7423 *C 36.800 107.475 +*N chany_top_out[4]:2 *C 36.800 106.818 +*N chany_top_out[4]:3 *C 36.793 106.760 +*N chany_top_out[4]:4 *C 32.668 106.760 +*N chany_top_out[4]:5 *C 32.660 106.703 +*N chany_top_out[4]:6 *C 32.660 102.725 +*N chany_top_out[4]:7 *C 32.615 102.680 +*N chany_top_out[4]:8 *C 31.777 102.680 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 chany_top_out[4] 6.396029e-05 +2 chany_top_out[4]:2 6.396029e-05 +3 chany_top_out[4]:3 0.0003120049 +4 chany_top_out[4]:4 0.0003120049 +5 chany_top_out[4]:5 0.0003113782 +6 chany_top_out[4]:6 0.0003113782 +7 chany_top_out[4]:7 7.913137e-05 +8 chany_top_out[4]:8 7.913137e-05 + +*RES +0 ropt_mt_inst_733:X chany_top_out[4]:8 0.152 +1 chany_top_out[4]:2 chany_top_out[4] 0.0005870535 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.00341 +3 chany_top_out[4]:5 chany_top_out[4]:4 0.00341 +4 chany_top_out[4]:4 chany_top_out[4]:3 0.00064625 +5 chany_top_out[4]:7 chany_top_out[4]:6 0.0045 +6 chany_top_out[4]:6 chany_top_out[4]:5 0.003551339 +7 chany_top_out[4]:8 chany_top_out[4]:7 0.0007477679 + +*END + +*D_NET chany_bottom_out[4] 0.0004925407 //LENGTH 3.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_741:X O *L 0 *C 22.275 3.400 +*P chany_bottom_out[4] O *L 0.7423 *C 23.460 1.290 +*N chany_bottom_out[4]:2 *C 23.460 3.355 +*N chany_bottom_out[4]:3 *C 23.415 3.400 +*N chany_bottom_out[4]:4 *C 22.312 3.400 + +*CAP +0 ropt_mt_inst_741:X 1e-06 +1 chany_bottom_out[4] 0.0001424846 +2 chany_bottom_out[4]:2 0.0001424846 +3 chany_bottom_out[4]:3 0.0001032858 +4 chany_bottom_out[4]:4 0.0001032858 + +*RES +0 ropt_mt_inst_741:X chany_bottom_out[4]:4 0.152 +1 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.000984375 +2 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +3 chany_bottom_out[4]:2 chany_bottom_out[4] 0.00184375 + +*END + +*D_NET ropt_net_171 0.001591993 //LENGTH 10.845 LUMPCC 0.0005855138 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 46.655 8.840 +*I ropt_mt_inst_780:A I *L 0.001767 *C 41.400 4.080 +*N ropt_net_171:2 *C 41.438 4.080 +*N ropt_net_171:3 *C 45.495 4.080 +*N ropt_net_171:4 *C 45.540 4.080 +*N ropt_net_171:5 *C 46.460 4.080 +*N ropt_net_171:6 *C 46.460 8.795 +*N ropt_net_171:7 *C 46.460 8.840 +*N ropt_net_171:8 *C 46.655 8.840 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 ropt_mt_inst_780:A 1e-06 +2 ropt_net_171:2 0.000129168 +3 ropt_net_171:3 0.000129168 +4 ropt_net_171:4 8.516379e-05 +5 ropt_net_171:5 0.0002981666 +6 ropt_net_171:6 0.0002434006 +7 ropt_net_171:7 5.934977e-05 +8 ropt_net_171:8 6.006247e-05 +9 ropt_net_171:3 chany_top_in[4]:12 0.0001592626 +10 ropt_net_171:2 chany_top_in[4]:11 0.0001592626 +11 ropt_net_171:3 chany_bottom_out[11]:3 7.727551e-05 +12 ropt_net_171:2 chany_bottom_out[11]:4 7.727551e-05 +13 ropt_net_171:6 chany_bottom_out[3]:6 5.621882e-05 +14 ropt_net_171:5 chany_bottom_out[3]:5 5.621882e-05 + +*RES +0 ropt_mt_inst_745:X ropt_net_171:8 0.152 +1 ropt_net_171:8 ropt_net_171:7 0.0001059783 +2 ropt_net_171:7 ropt_net_171:6 0.0045 +3 ropt_net_171:6 ropt_net_171:5 0.004209822 +4 ropt_net_171:3 ropt_net_171:2 0.003622768 +5 ropt_net_171:4 ropt_net_171:3 0.0045 +6 ropt_net_171:2 ropt_mt_inst_780:A 0.152 +7 ropt_net_171:5 ropt_net_171:4 0.0008214285 + +*END + +*D_NET chany_top_out[2] 0.001565867 //LENGTH 11.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 57.695 102.000 +*P chany_top_out[2] O *L 0.7423 *C 52.900 107.510 +*N chany_top_out[2]:2 *C 52.900 106.760 +*N chany_top_out[2]:3 *C 53.360 106.760 +*N chany_top_out[2]:4 *C 53.360 104.085 +*N chany_top_out[2]:5 *C 53.405 104.040 +*N chany_top_out[2]:6 *C 56.075 104.040 +*N chany_top_out[2]:7 *C 56.120 103.995 +*N chany_top_out[2]:8 *C 56.120 102.045 +*N chany_top_out[2]:9 *C 56.165 102.000 +*N chany_top_out[2]:10 *C 57.658 102.000 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 chany_top_out[2] 6.143493e-05 +2 chany_top_out[2]:2 9.546259e-05 +3 chany_top_out[2]:3 0.0002299141 +4 chany_top_out[2]:4 0.0001958865 +5 chany_top_out[2]:5 0.0002025925 +6 chany_top_out[2]:6 0.0002025925 +7 chany_top_out[2]:7 0.0001578444 +8 chany_top_out[2]:8 0.0001578444 +9 chany_top_out[2]:9 0.0001306475 +10 chany_top_out[2]:10 0.0001306475 + +*RES +0 ropt_mt_inst_752:X chany_top_out[2]:10 0.152 +1 chany_top_out[2]:10 chany_top_out[2]:9 0.001332589 +2 chany_top_out[2]:9 chany_top_out[2]:8 0.0045 +3 chany_top_out[2]:8 chany_top_out[2]:7 0.001741071 +4 chany_top_out[2]:6 chany_top_out[2]:5 0.002383929 +5 chany_top_out[2]:7 chany_top_out[2]:6 0.0045 +6 chany_top_out[2]:5 chany_top_out[2]:4 0.0045 +7 chany_top_out[2]:4 chany_top_out[2]:3 0.002388393 +8 chany_top_out[2]:2 chany_top_out[2] 0.0006696429 +9 chany_top_out[2]:3 chany_top_out[2]:2 0.0004107143 + +*END + +*D_NET chany_bottom_out[9] 0.0005182765 //LENGTH 4.090 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 40.650 3.400 +*P chany_bottom_out[9] O *L 0.7423 *C 39.100 1.325 +*N chany_bottom_out[9]:2 *C 39.100 3.355 +*N chany_bottom_out[9]:3 *C 39.145 3.400 +*N chany_bottom_out[9]:4 *C 40.613 3.400 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 chany_bottom_out[9] 0.0001296074 +2 chany_bottom_out[9]:2 0.0001296074 +3 chany_bottom_out[9]:3 0.0001290308 +4 chany_bottom_out[9]:4 0.0001290308 + +*RES +0 ropt_mt_inst_783:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +2 chany_bottom_out[9]:2 chany_bottom_out[9] 0.0018125 +3 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.001310268 + +*END + +*D_NET mem_right_ipin_15/net_net_75 0.000487345 //LENGTH 5.080 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_15\/FTB_17__56:X O *L 0 *C 81.275 86.360 +*I mem_right_ipin_15\/BUFT_RR_120:A I *L 0.001767 *C 81.420 91.120 +*N mem_right_ipin_15/net_net_75:2 *C 81.420 91.120 +*N mem_right_ipin_15/net_net_75:3 *C 81.420 91.075 +*N mem_right_ipin_15/net_net_75:4 *C 81.420 86.405 +*N mem_right_ipin_15/net_net_75:5 *C 81.275 86.360 + +*CAP +0 mem_right_ipin_15\/FTB_17__56:X 1e-06 +1 mem_right_ipin_15\/BUFT_RR_120:A 1e-06 +2 mem_right_ipin_15/net_net_75:2 3.047066e-05 +3 mem_right_ipin_15/net_net_75:3 0.000215223 +4 mem_right_ipin_15/net_net_75:4 0.000215223 +5 mem_right_ipin_15/net_net_75:5 2.442834e-05 + +*RES +0 mem_right_ipin_15\/FTB_17__56:X mem_right_ipin_15/net_net_75:5 0.152 +1 mem_right_ipin_15/net_net_75:2 mem_right_ipin_15\/BUFT_RR_120:A 0.152 +2 mem_right_ipin_15/net_net_75:3 mem_right_ipin_15/net_net_75:2 0.0045 +3 mem_right_ipin_15/net_net_75:5 mem_right_ipin_15/net_net_75:4 0.0045 +4 mem_right_ipin_15/net_net_75:4 mem_right_ipin_15/net_net_75:3 0.004169643 + +*END + +*D_NET chany_bottom_out[5] 0.001058015 //LENGTH 8.590 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 34.695 6.460 +*P chany_bottom_out[5] O *L 0.7423 *C 31.740 1.290 +*N chany_bottom_out[5]:2 *C 31.740 6.415 +*N chany_bottom_out[5]:3 *C 31.785 6.460 +*N chany_bottom_out[5]:4 *C 34.657 6.460 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 chany_bottom_out[5] 0.000308012 +2 chany_bottom_out[5]:2 0.000308012 +3 chany_bottom_out[5]:3 0.0002204956 +4 chany_bottom_out[5]:4 0.0002204956 + +*RES +0 ropt_mt_inst_789:X chany_bottom_out[5]:4 0.152 +1 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.002564732 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +3 chany_bottom_out[5]:2 chany_bottom_out[5] 0.004575893 + +*END + +*D_NET chany_bottom_out[19] 0.001211659 //LENGTH 10.360 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 32.825 9.180 +*P chany_bottom_out[19] O *L 0.7423 *C 30.820 1.290 +*N chany_bottom_out[19]:2 *C 30.820 9.135 +*N chany_bottom_out[19]:3 *C 30.865 9.180 +*N chany_bottom_out[19]:4 *C 32.788 9.180 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 chany_bottom_out[19] 0.0004482242 +2 chany_bottom_out[19]:2 0.0004482242 +3 chany_bottom_out[19]:3 0.0001571052 +4 chany_bottom_out[19]:4 0.0001571052 + +*RES +0 ropt_mt_inst_808:X chany_bottom_out[19]:4 0.152 +1 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.0045 +2 chany_bottom_out[19]:2 chany_bottom_out[19] 0.007004464 +3 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.001716518 + +*END + +*D_NET chany_bottom_in[11] 0.02425504 //LENGTH 172.000 LUMPCC 0.009322157 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 65.320 1.290 +*I mux_right_ipin_14\/mux_l2_in_1_:A0 I *L 0.001631 *C 32.835 48.280 +*I mux_right_ipin_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 31.570 64.600 +*I mux_right_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 39.850 76.840 +*I ropt_mt_inst_737:A I *L 0.001766 *C 63.020 102.000 +*N chany_bottom_in[11]:5 *C 62.983 102.000 +*N chany_bottom_in[11]:6 *C 59.845 102.000 +*N chany_bottom_in[11]:7 *C 59.800 101.955 +*N chany_bottom_in[11]:8 *C 59.800 100.017 +*N chany_bottom_in[11]:9 *C 59.793 99.960 +*N chany_bottom_in[11]:10 *C 46.928 99.960 +*N chany_bottom_in[11]:11 *C 46.920 99.903 +*N chany_bottom_in[11]:12 *C 46.920 96.265 +*N chany_bottom_in[11]:13 *C 46.875 96.220 +*N chany_bottom_in[11]:14 *C 45.125 96.220 +*N chany_bottom_in[11]:15 *C 45.080 96.220 +*N chany_bottom_in[11]:16 *C 45.080 76.898 +*N chany_bottom_in[11]:17 *C 45.073 76.840 +*N chany_bottom_in[11]:18 *C 39.850 76.840 +*N chany_bottom_in[11]:19 *C 40.020 76.840 +*N chany_bottom_in[11]:20 *C 40.020 76.840 +*N chany_bottom_in[11]:21 *C 40.020 76.840 +*N chany_bottom_in[11]:22 *C 32.220 76.840 +*N chany_bottom_in[11]:23 *C 32.200 76.833 +*N chany_bottom_in[11]:24 *C 31.490 64.600 +*N chany_bottom_in[11]:25 *C 31.608 64.600 +*N chany_bottom_in[11]:26 *C 32.155 64.600 +*N chany_bottom_in[11]:27 *C 32.200 64.600 +*N chany_bottom_in[11]:28 *C 32.197 64.600 +*N chany_bottom_in[11]:29 *C 32.200 64.600 +*N chany_bottom_in[11]:30 *C 32.200 48.288 +*N chany_bottom_in[11]:31 *C 32.220 48.280 +*N chany_bottom_in[11]:32 *C 32.835 48.280 +*N chany_bottom_in[11]:33 *C 33.120 48.280 +*N chany_bottom_in[11]:34 *C 33.120 48.280 +*N chany_bottom_in[11]:35 *C 33.120 48.273 +*N chany_bottom_in[11]:36 *C 33.120 47.600 +*N chany_bottom_in[11]:37 *C 60.700 47.600 +*N chany_bottom_in[11]:38 *C 60.720 47.593 +*N chany_bottom_in[11]:39 *C 60.720 2.728 +*N chany_bottom_in[11]:40 *C 60.740 2.720 +*N chany_bottom_in[11]:41 *C 65.312 2.720 +*N chany_bottom_in[11]:42 *C 65.320 2.663 + +*CAP +0 chany_bottom_in[11] 8.980777e-05 +1 mux_right_ipin_14\/mux_l2_in_1_:A0 1e-06 +2 mux_right_ipin_6\/mux_l2_in_1_:A0 1e-06 +3 mux_right_ipin_0\/mux_l2_in_1_:A0 1e-06 +4 ropt_mt_inst_737:A 1e-06 +5 chany_bottom_in[11]:5 0.0001757818 +6 chany_bottom_in[11]:6 0.0001757818 +7 chany_bottom_in[11]:7 0.0001450561 +8 chany_bottom_in[11]:8 0.0001450561 +9 chany_bottom_in[11]:9 0.0004594851 +10 chany_bottom_in[11]:10 0.0004594851 +11 chany_bottom_in[11]:11 0.000188116 +12 chany_bottom_in[11]:12 0.000188116 +13 chany_bottom_in[11]:13 7.61161e-05 +14 chany_bottom_in[11]:14 7.61161e-05 +15 chany_bottom_in[11]:15 0.001171041 +16 chany_bottom_in[11]:16 0.001137782 +17 chany_bottom_in[11]:17 0.0002812506 +18 chany_bottom_in[11]:18 4.991398e-05 +19 chany_bottom_in[11]:19 5.416849e-05 +20 chany_bottom_in[11]:20 3.661484e-05 +21 chany_bottom_in[11]:21 0.0007406233 +22 chany_bottom_in[11]:22 0.0004593727 +23 chany_bottom_in[11]:23 0.0002807508 +24 chany_bottom_in[11]:24 0.0001094089 +25 chany_bottom_in[11]:25 6.043772e-05 +26 chany_bottom_in[11]:26 6.043772e-05 +27 chany_bottom_in[11]:27 3.798247e-05 +28 chany_bottom_in[11]:28 0.0001094089 +29 chany_bottom_in[11]:29 0.0006629053 +30 chany_bottom_in[11]:30 0.0003821545 +31 chany_bottom_in[11]:31 0.0001183207 +32 chany_bottom_in[11]:32 5.672512e-05 +33 chany_bottom_in[11]:33 5.83625e-05 +34 chany_bottom_in[11]:34 3.679226e-05 +35 chany_bottom_in[11]:35 0.0001631942 +36 chany_bottom_in[11]:36 0.001696325 +37 chany_bottom_in[11]:37 0.001651452 +38 chany_bottom_in[11]:38 0.001351527 +39 chany_bottom_in[11]:39 0.001351527 +40 chany_bottom_in[11]:40 0.0002708403 +41 chany_bottom_in[11]:41 0.0002708403 +42 chany_bottom_in[11]:42 8.980777e-05 +43 chany_bottom_in[11]:38 chany_bottom_in[5]:20 0.001005071 +44 chany_bottom_in[11]:39 chany_bottom_in[5]:21 0.001005071 +45 chany_bottom_in[11]:16 chany_bottom_in[5]:16 0.0001145407 +46 chany_bottom_in[11]:15 chany_bottom_in[5]:6 0.0001145407 +47 chany_bottom_in[11]:30 chany_bottom_in[13]:14 0.0007227471 +48 chany_bottom_in[11]:29 chany_bottom_in[13]:14 0.0005461383 +49 chany_bottom_in[11]:29 chany_bottom_in[13]:13 0.0007227471 +50 chany_bottom_in[11]:23 chany_bottom_in[13]:13 0.0005461383 +51 chany_bottom_in[11]:35 chany_bottom_in[13]:13 2.65503e-05 +52 chany_bottom_in[11]:36 chany_bottom_in[13]:14 2.65503e-05 +53 chany_bottom_in[11]:30 chany_top_in[13]:22 0.0003185941 +54 chany_bottom_in[11]:29 chany_top_in[13]:22 0.0002393221 +55 chany_bottom_in[11]:29 chany_top_in[13]:23 0.0003185941 +56 chany_bottom_in[11]:23 chany_top_in[13]:23 0.0002393221 +57 chany_bottom_in[11]:37 prog_clk[0]:247 4.209582e-05 +58 chany_bottom_in[11]:37 prog_clk[0]:278 6.181574e-06 +59 chany_bottom_in[11]:37 prog_clk[0]:271 0.0002205673 +60 chany_bottom_in[11]:10 prog_clk[0]:371 8.881934e-07 +61 chany_bottom_in[11]:9 prog_clk[0]:364 8.881934e-07 +62 chany_bottom_in[11]:36 prog_clk[0]:272 0.0002205673 +63 chany_bottom_in[11]:36 prog_clk[0]:279 6.181574e-06 +64 chany_bottom_in[11]:36 prog_clk[0]:271 4.209582e-05 +65 chany_bottom_in[11]:17 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001023425 +66 chany_bottom_in[11]:22 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001478655 +67 chany_bottom_in[11]:21 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001478655 +68 chany_bottom_in[11]:21 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001023425 +69 chany_bottom_in[11]:10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0007096339 +70 chany_bottom_in[11]:9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0007096339 +71 chany_bottom_in[11]:16 ropt_net_147:8 7.353593e-06 +72 chany_bottom_in[11]:14 ropt_net_147:5 7.640427e-05 +73 chany_bottom_in[11]:15 ropt_net_147:7 7.353593e-06 +74 chany_bottom_in[11]:13 ropt_net_147:6 7.640427e-05 +75 chany_bottom_in[11]:12 ropt_net_147:8 1.450018e-05 +76 chany_bottom_in[11]:11 ropt_net_147:7 1.450018e-05 +77 chany_bottom_in[11]:6 ropt_net_175:4 0.0001278706 +78 chany_bottom_in[11]:5 ropt_net_175:5 0.0001278706 +79 chany_bottom_in[11]:12 ropt_net_172:5 7.833025e-05 +80 chany_bottom_in[11]:11 ropt_net_172:4 7.833025e-05 +81 chany_bottom_in[11]:10 ropt_net_145:7 0.0001540829 +82 chany_bottom_in[11]:9 ropt_net_145:6 0.0001540829 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:42 0.001225446 +1 chany_bottom_in[11]:37 chany_bottom_in[11]:36 0.004320866 +2 chany_bottom_in[11]:38 chany_bottom_in[11]:37 0.00341 +3 chany_bottom_in[11]:40 chany_bottom_in[11]:39 0.00341 +4 chany_bottom_in[11]:39 chany_bottom_in[11]:38 0.007028849 +5 chany_bottom_in[11]:42 chany_bottom_in[11]:41 0.00341 +6 chany_bottom_in[11]:41 chany_bottom_in[11]:40 0.0007163583 +7 chany_bottom_in[11]:16 chany_bottom_in[11]:15 0.01725223 +8 chany_bottom_in[11]:17 chany_bottom_in[11]:16 0.00341 +9 chany_bottom_in[11]:14 chany_bottom_in[11]:13 0.0015625 +10 chany_bottom_in[11]:15 chany_bottom_in[11]:14 0.0045 +11 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.0045 +12 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.003247768 +13 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.00341 +14 chany_bottom_in[11]:10 chany_bottom_in[11]:9 0.002015517 +15 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.001729911 +16 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.00341 +17 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.00280134 +18 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.0045 +19 chany_bottom_in[11]:5 ropt_mt_inst_737:A 0.152 +20 chany_bottom_in[11]:31 chany_bottom_in[11]:30 0.00341 +21 chany_bottom_in[11]:30 chany_bottom_in[11]:29 0.002555625 +22 chany_bottom_in[11]:28 chany_bottom_in[11]:27 0.00341 +23 chany_bottom_in[11]:28 chany_bottom_in[11]:24 0.0001039141 +24 chany_bottom_in[11]:29 chany_bottom_in[11]:28 0.00341 +25 chany_bottom_in[11]:29 chany_bottom_in[11]:23 0.001916425 +26 chany_bottom_in[11]:27 chany_bottom_in[11]:26 0.0045 +27 chany_bottom_in[11]:26 chany_bottom_in[11]:25 0.0004888393 +28 chany_bottom_in[11]:25 mux_right_ipin_6\/mux_l2_in_1_:A0 0.152 +29 chany_bottom_in[11]:22 chany_bottom_in[11]:21 0.001222 +30 chany_bottom_in[11]:23 chany_bottom_in[11]:22 0.00341 +31 chany_bottom_in[11]:34 chany_bottom_in[11]:33 0.0045 +32 chany_bottom_in[11]:35 chany_bottom_in[11]:34 0.00341 +33 chany_bottom_in[11]:35 chany_bottom_in[11]:31 0.000141 +34 chany_bottom_in[11]:33 chany_bottom_in[11]:32 0.0001548913 +35 chany_bottom_in[11]:32 mux_right_ipin_14\/mux_l2_in_1_:A0 0.152 +36 chany_bottom_in[11]:20 chany_bottom_in[11]:19 0.0045 +37 chany_bottom_in[11]:21 chany_bottom_in[11]:20 0.00341 +38 chany_bottom_in[11]:21 chany_bottom_in[11]:17 0.0007915583 +39 chany_bottom_in[11]:19 chany_bottom_in[11]:18 9.239131e-05 +40 chany_bottom_in[11]:18 mux_right_ipin_0\/mux_l2_in_1_:A0 0.152 +41 chany_bottom_in[11]:36 chany_bottom_in[11]:35 0.0001053583 + +*END + +*D_NET chany_top_in[16] 0.02849796 //LENGTH 187.975 LUMPCC 0.009571724 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 35.880 107.510 +*I mux_right_ipin_11\/mux_l2_in_3_:A1 I *L 0.00198 *C 26.680 52.700 +*I ropt_mt_inst_745:A I *L 0.001766 *C 42.780 9.520 +*I mux_right_ipin_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 27.505 61.540 +*I mux_right_ipin_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 64.960 56.100 +*I mux_left_ipin_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 72.320 56.100 +*N chany_top_in[16]:6 *C 72.282 56.100 +*N chany_top_in[16]:7 *C 70.840 56.100 +*N chany_top_in[16]:8 *C 70.840 56.440 +*N chany_top_in[16]:9 *C 64.960 56.100 +*N chany_top_in[16]:10 *C 64.928 56.440 +*N chany_top_in[16]:11 *C 64.860 56.440 +*N chany_top_in[16]:12 *C 64.400 56.440 +*N chany_top_in[16]:13 *C 64.400 59.103 +*N chany_top_in[16]:14 *C 64.392 59.160 +*N chany_top_in[16]:15 *C 27.543 61.540 +*N chany_top_in[16]:16 *C 28.475 61.540 +*N chany_top_in[16]:17 *C 28.520 61.495 +*N chany_top_in[16]:18 *C 42.742 9.520 +*N chany_top_in[16]:19 *C 42.320 9.520 +*N chany_top_in[16]:20 *C 42.320 9.180 +*N chany_top_in[16]:21 *C 39.145 9.180 +*N chany_top_in[16]:22 *C 39.100 9.135 +*N chany_top_in[16]:23 *C 39.100 4.465 +*N chany_top_in[16]:24 *C 39.055 4.420 +*N chany_top_in[16]:25 *C 26.725 4.420 +*N chany_top_in[16]:26 *C 26.680 4.465 +*N chany_top_in[16]:27 *C 26.680 8.783 +*N chany_top_in[16]:28 *C 26.673 8.840 +*N chany_top_in[16]:29 *C 25.780 8.840 +*N chany_top_in[16]:30 *C 25.760 8.848 +*N chany_top_in[16]:31 *C 25.760 47.593 +*N chany_top_in[16]:32 *C 25.780 47.600 +*N chany_top_in[16]:33 *C 28.053 47.600 +*N chany_top_in[16]:34 *C 28.060 47.657 +*N chany_top_in[16]:35 *C 28.060 52.360 +*N chany_top_in[16]:36 *C 28.475 52.360 +*N chany_top_in[16]:37 *C 26.718 52.700 +*N chany_top_in[16]:38 *C 28.475 52.700 +*N chany_top_in[16]:39 *C 28.520 52.745 +*N chany_top_in[16]:40 *C 28.520 59.160 +*N chany_top_in[16]:41 *C 28.527 59.160 +*N chany_top_in[16]:42 *C 36.800 59.160 +*N chany_top_in[16]:43 *C 36.800 59.168 +*N chany_top_in[16]:44 *C 36.800 102.672 +*N chany_top_in[16]:45 *C 36.780 102.680 +*N chany_top_in[16]:46 *C 35.888 102.680 +*N chany_top_in[16]:47 *C 35.880 102.738 + +*CAP +0 chany_top_in[16] 0.000284031 +1 mux_right_ipin_11\/mux_l2_in_3_:A1 1e-06 +2 ropt_mt_inst_745:A 1e-06 +3 mux_right_ipin_3\/mux_l2_in_3_:A1 1e-06 +4 mux_right_ipin_5\/mux_l2_in_3_:A1 1e-06 +5 mux_left_ipin_0\/mux_l2_in_3_:A1 1e-06 +6 chany_top_in[16]:6 0.0001203469 +7 chany_top_in[16]:7 0.0001455553 +8 chany_top_in[16]:8 0.0004623297 +9 chany_top_in[16]:9 6.269573e-05 +10 chany_top_in[16]:10 0.000471346 +11 chany_top_in[16]:11 6.84032e-05 +12 chany_top_in[16]:12 0.0002047529 +13 chany_top_in[16]:13 0.0001697113 +14 chany_top_in[16]:14 0.001962903 +15 chany_top_in[16]:15 8.056388e-05 +16 chany_top_in[16]:16 8.056388e-05 +17 chany_top_in[16]:17 0.0001364481 +18 chany_top_in[16]:18 5.307932e-05 +19 chany_top_in[16]:19 8.067743e-05 +20 chany_top_in[16]:20 0.000183445 +21 chany_top_in[16]:21 0.0001558469 +22 chany_top_in[16]:22 0.0003271474 +23 chany_top_in[16]:23 0.0003271474 +24 chany_top_in[16]:24 0.00066655 +25 chany_top_in[16]:25 0.00066655 +26 chany_top_in[16]:26 0.0002995493 +27 chany_top_in[16]:27 0.0002995493 +28 chany_top_in[16]:28 7.952275e-05 +29 chany_top_in[16]:29 7.952275e-05 +30 chany_top_in[16]:30 0.001564205 +31 chany_top_in[16]:31 0.001564205 +32 chany_top_in[16]:32 0.0001847267 +33 chany_top_in[16]:33 0.0001847267 +34 chany_top_in[16]:34 0.000290198 +35 chany_top_in[16]:35 0.0003183131 +36 chany_top_in[16]:36 7.198119e-05 +37 chany_top_in[16]:37 0.0001511137 +38 chany_top_in[16]:38 0.0001511137 +39 chany_top_in[16]:39 0.000452324 +40 chany_top_in[16]:40 0.000579865 +41 chany_top_in[16]:41 0.000656283 +42 chany_top_in[16]:42 0.002619186 +43 chany_top_in[16]:43 0.001055134 +44 chany_top_in[16]:44 0.001055134 +45 chany_top_in[16]:45 0.0001352257 +46 chany_top_in[16]:46 0.0001352257 +47 chany_top_in[16]:47 0.000284031 +48 chany_top_in[16]:41 chany_bottom_in[2]:24 0.0001348039 +49 chany_top_in[16]:14 chany_bottom_in[2]:46 0.0001849128 +50 chany_top_in[16]:42 chany_bottom_in[2]:24 0.0001849128 +51 chany_top_in[16]:42 chany_bottom_in[2]:46 0.0001348039 +52 chany_top_in[16]:31 chany_bottom_in[13]:23 0.0004040155 +53 chany_top_in[16]:31 chany_bottom_in[13]:29 3.42699e-05 +54 chany_top_in[16]:30 chany_bottom_in[13]:29 0.0004040155 +55 chany_top_in[16]:30 chany_bottom_in[13]:30 3.42699e-05 +56 chany_top_in[16]:25 chany_bottom_in[13]:36 7.214177e-05 +57 chany_top_in[16]:24 chany_bottom_in[13]:37 7.214177e-05 +58 chany_top_in[16]:43 chany_top_in[5]:10 0.0005326552 +59 chany_top_in[16]:43 chany_top_in[5]:20 0.001395581 +60 chany_top_in[16]:45 chany_top_in[5]:23 4.66802e-07 +61 chany_top_in[16]:44 chany_top_in[5]:20 0.0005326552 +62 chany_top_in[16]:44 chany_top_in[5]:21 0.001395581 +63 chany_top_in[16]:46 chany_top_in[5]:22 4.66802e-07 +64 chany_top_in[16]:31 chany_top_in[9]:9 7.832754e-06 +65 chany_top_in[16]:31 chany_top_in[9]:19 0.0008427404 +66 chany_top_in[16]:30 chany_top_in[9]:6 7.832754e-06 +67 chany_top_in[16]:30 chany_top_in[9]:13 0.0008427404 +68 chany_top_in[16]:25 chany_top_in[14]:5 0.0001257748 +69 chany_top_in[16]:25 chany_top_in[14]:7 1.210183e-05 +70 chany_top_in[16]:24 chany_top_in[14]:6 0.0001257748 +71 chany_top_in[16]:24 chany_top_in[14]:8 1.210183e-05 +72 chany_top_in[16]:21 chany_top_in[14]:11 0.0001213294 +73 chany_top_in[16]:18 chany_top_in[14]:12 4.429248e-06 +74 chany_top_in[16]:20 chany_top_in[14]:12 0.0001213294 +75 chany_top_in[16]:19 chany_top_in[14]:11 4.429248e-06 +76 chany_top_in[16]:43 chany_top_in[19]:33 0.0007602446 +77 chany_top_in[16]:44 chany_top_in[19]:34 0.0007602446 +78 chany_top_in[16]:25 ropt_net_174:2 9.374234e-05 +79 chany_top_in[16]:24 ropt_net_174:3 9.374234e-05 +80 chany_top_in[16]:23 ropt_net_174:4 7.576664e-07 +81 chany_top_in[16]:22 ropt_net_174:5 7.576664e-07 +82 chany_top_in[16] ropt_net_184:8 5.806258e-05 +83 chany_top_in[16]:47 ropt_net_184:9 5.806258e-05 + +*RES +0 chany_top_in[16] chany_top_in[16]:47 0.00426116 +1 chany_top_in[16]:40 chany_top_in[16]:39 0.005727679 +2 chany_top_in[16]:40 chany_top_in[16]:17 0.002084821 +3 chany_top_in[16]:41 chany_top_in[16]:40 0.00341 +4 chany_top_in[16]:10 chany_top_in[16]:9 0.0001847826 +5 chany_top_in[16]:10 chany_top_in[16]:8 0.005279018 +6 chany_top_in[16]:11 chany_top_in[16]:10 0.0045 +7 chany_top_in[16]:13 chany_top_in[16]:12 0.002377232 +8 chany_top_in[16]:14 chany_top_in[16]:13 0.00341 +9 chany_top_in[16]:34 chany_top_in[16]:33 0.00341 +10 chany_top_in[16]:33 chany_top_in[16]:32 0.000356025 +11 chany_top_in[16]:32 chany_top_in[16]:31 0.00341 +12 chany_top_in[16]:31 chany_top_in[16]:30 0.006070049 +13 chany_top_in[16]:29 chany_top_in[16]:28 0.000139825 +14 chany_top_in[16]:30 chany_top_in[16]:29 0.00341 +15 chany_top_in[16]:27 chany_top_in[16]:26 0.003854911 +16 chany_top_in[16]:28 chany_top_in[16]:27 0.00341 +17 chany_top_in[16]:25 chany_top_in[16]:24 0.01100893 +18 chany_top_in[16]:26 chany_top_in[16]:25 0.0045 +19 chany_top_in[16]:24 chany_top_in[16]:23 0.0045 +20 chany_top_in[16]:23 chany_top_in[16]:22 0.004169642 +21 chany_top_in[16]:21 chany_top_in[16]:20 0.002834822 +22 chany_top_in[16]:22 chany_top_in[16]:21 0.0045 +23 chany_top_in[16]:18 ropt_mt_inst_745:A 0.152 +24 chany_top_in[16]:42 chany_top_in[16]:41 0.001296025 +25 chany_top_in[16]:42 chany_top_in[16]:14 0.004322825 +26 chany_top_in[16]:43 chany_top_in[16]:42 0.00341 +27 chany_top_in[16]:45 chany_top_in[16]:44 0.00341 +28 chany_top_in[16]:44 chany_top_in[16]:43 0.006815783 +29 chany_top_in[16]:47 chany_top_in[16]:46 0.00341 +30 chany_top_in[16]:46 chany_top_in[16]:45 0.000139825 +31 chany_top_in[16]:16 chany_top_in[16]:15 0.0008325893 +32 chany_top_in[16]:17 chany_top_in[16]:16 0.0045 +33 chany_top_in[16]:15 mux_right_ipin_3\/mux_l2_in_3_:A1 0.152 +34 chany_top_in[16]:38 chany_top_in[16]:37 0.001569196 +35 chany_top_in[16]:39 chany_top_in[16]:38 0.0045 +36 chany_top_in[16]:39 chany_top_in[16]:36 0.000240625 +37 chany_top_in[16]:37 mux_right_ipin_11\/mux_l2_in_3_:A1 0.152 +38 chany_top_in[16]:9 mux_right_ipin_5\/mux_l2_in_3_:A1 0.152 +39 chany_top_in[16]:6 mux_left_ipin_0\/mux_l2_in_3_:A1 0.152 +40 chany_top_in[16]:20 chany_top_in[16]:19 0.0003035714 +41 chany_top_in[16]:19 chany_top_in[16]:18 0.0003772322 +42 chany_top_in[16]:8 chany_top_in[16]:7 0.0003035715 +43 chany_top_in[16]:7 chany_top_in[16]:6 0.001287946 +44 chany_top_in[16]:35 chany_top_in[16]:34 0.004198661 +45 chany_top_in[16]:36 chany_top_in[16]:35 0.0003705357 +46 chany_top_in[16]:12 chany_top_in[16]:11 0.0004107143 + +*END + +*D_NET left_grid_pin_0_[0] 0.0007538358 //LENGTH 6.405 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.845 102.340 +*P left_grid_pin_0_[0] O *L 0.7423 *C 1.230 102.000 +*N left_grid_pin_0_[0]:2 *C 6.433 102.000 +*N left_grid_pin_0_[0]:3 *C 6.440 102.000 +*N left_grid_pin_0_[0]:4 *C 6.440 102.340 +*N left_grid_pin_0_[0]:5 *C 6.463 102.340 +*N left_grid_pin_0_[0]:6 *C 6.830 102.340 + +*CAP +0 mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_0_[0] 0.0002851504 +2 left_grid_pin_0_[0]:2 0.0002851504 +3 left_grid_pin_0_[0]:3 4.737695e-05 +4 left_grid_pin_0_[0]:4 4.421384e-05 +5 left_grid_pin_0_[0]:5 4.547213e-05 +6 left_grid_pin_0_[0]:6 4.547213e-05 + +*RES +0 mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_0_[0]:6 0.152 +1 left_grid_pin_0_[0]:6 left_grid_pin_0_[0]:5 0.0001997283 +2 left_grid_pin_0_[0]:5 left_grid_pin_0_[0]:4 0.0045 +3 left_grid_pin_0_[0]:4 left_grid_pin_0_[0]:3 0.0001634615 +4 left_grid_pin_0_[0]:3 left_grid_pin_0_[0]:2 0.00341 +5 left_grid_pin_0_[0]:2 left_grid_pin_0_[0] 0.0008150582 + +*END + +*D_NET left_grid_pin_3_[0] 0.004150691 //LENGTH 41.230 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_3\/mux_l4_in_0_:X O *L 0 *C 8.500 63.920 +*P left_grid_pin_3_[0] O *L 0.7423 *C 1.230 96.560 +*N left_grid_pin_3_[0]:2 *C 7.880 63.920 +*N left_grid_pin_3_[0]:3 *C 8.260 96.560 +*N left_grid_pin_3_[0]:4 *C 8.280 96.553 +*N left_grid_pin_3_[0]:5 *C 8.280 63.928 +*N left_grid_pin_3_[0]:6 *C 8.280 63.920 +*N left_grid_pin_3_[0]:7 *C 8.280 63.920 +*N left_grid_pin_3_[0]:8 *C 8.280 63.920 +*N left_grid_pin_3_[0]:9 *C 8.500 63.920 + +*CAP +0 mux_right_ipin_3\/mux_l4_in_0_:X 1e-06 +1 left_grid_pin_3_[0] 0.0004637933 +2 left_grid_pin_3_[0]:2 5.977857e-05 +3 left_grid_pin_3_[0]:3 0.0004637933 +4 left_grid_pin_3_[0]:4 0.001487618 +5 left_grid_pin_3_[0]:5 0.001487618 +6 left_grid_pin_3_[0]:6 5.977857e-05 +7 left_grid_pin_3_[0]:7 3.280906e-05 +8 left_grid_pin_3_[0]:8 4.880678e-05 +9 left_grid_pin_3_[0]:9 4.569468e-05 + +*RES +0 mux_right_ipin_3\/mux_l4_in_0_:X left_grid_pin_3_[0]:9 0.152 +1 left_grid_pin_3_[0]:9 left_grid_pin_3_[0]:8 0.0001195652 +2 left_grid_pin_3_[0]:8 left_grid_pin_3_[0]:7 0.0045 +3 left_grid_pin_3_[0]:7 left_grid_pin_3_[0]:6 0.00341 +4 left_grid_pin_3_[0]:6 left_grid_pin_3_[0]:5 0.00341 +5 left_grid_pin_3_[0]:6 left_grid_pin_3_[0]:2 5.69697e-05 +6 left_grid_pin_3_[0]:5 left_grid_pin_3_[0]:4 0.00511125 +7 left_grid_pin_3_[0]:3 left_grid_pin_3_[0] 0.001101366 +8 left_grid_pin_3_[0]:4 left_grid_pin_3_[0]:3 0.00341 + +*END + +*D_NET left_grid_pin_7_[0] 0.0006499756 //LENGTH 4.565 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 5.005 98.940 +*P left_grid_pin_7_[0] O *L 0.7423 *C 1.230 99.280 +*N left_grid_pin_7_[0]:2 *C 4.593 99.280 +*N left_grid_pin_7_[0]:3 *C 4.600 99.280 +*N left_grid_pin_7_[0]:4 *C 4.600 98.940 +*N left_grid_pin_7_[0]:5 *C 4.623 98.940 +*N left_grid_pin_7_[0]:6 *C 4.990 98.940 + +*CAP +0 mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_7_[0] 0.0002260819 +2 left_grid_pin_7_[0]:2 0.0002260819 +3 left_grid_pin_7_[0]:3 4.610297e-05 +4 left_grid_pin_7_[0]:4 4.298898e-05 +5 left_grid_pin_7_[0]:5 5.385989e-05 +6 left_grid_pin_7_[0]:6 5.385989e-05 + +*RES +0 mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_7_[0]:6 0.152 +1 left_grid_pin_7_[0]:6 left_grid_pin_7_[0]:5 0.0001997283 +2 left_grid_pin_7_[0]:5 left_grid_pin_7_[0]:4 0.0045 +3 left_grid_pin_7_[0]:4 left_grid_pin_7_[0]:3 0.0001634615 +4 left_grid_pin_7_[0]:3 left_grid_pin_7_[0]:2 0.00341 +5 left_grid_pin_7_[0]:2 left_grid_pin_7_[0] 0.0005267916 + +*END + +*D_NET left_grid_pin_9_[0] 0.002771683 //LENGTH 23.610 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 61.200 +*P left_grid_pin_9_[0] O *L 0.7423 *C 1.230 81.600 +*N left_grid_pin_9_[0]:2 *C 3.213 81.600 +*N left_grid_pin_9_[0]:3 *C 3.220 81.543 +*N left_grid_pin_9_[0]:4 *C 3.220 61.245 +*N left_grid_pin_9_[0]:5 *C 3.243 61.200 +*N left_grid_pin_9_[0]:6 *C 3.610 61.200 + +*CAP +0 mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_9_[0] 0.0001245181 +2 left_grid_pin_9_[0]:2 0.0001245181 +3 left_grid_pin_9_[0]:3 0.001217264 +4 left_grid_pin_9_[0]:4 0.001217264 +5 left_grid_pin_9_[0]:5 4.355943e-05 +6 left_grid_pin_9_[0]:6 4.355943e-05 + +*RES +0 mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_9_[0]:6 0.152 +1 left_grid_pin_9_[0]:6 left_grid_pin_9_[0]:5 0.0001997283 +2 left_grid_pin_9_[0]:5 left_grid_pin_9_[0]:4 0.0045 +3 left_grid_pin_9_[0]:4 left_grid_pin_9_[0]:3 0.01812277 +4 left_grid_pin_9_[0]:3 left_grid_pin_9_[0]:2 0.00341 +5 left_grid_pin_9_[0]:2 left_grid_pin_9_[0] 0.0003105916 + +*END + +*D_NET ropt_net_141 0.001139021 //LENGTH 11.510 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_13\/BUFT_P_106:X O *L 0 *C 4.140 50.660 +*I ropt_mt_inst_740:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_141:2 *C 3.183 58.480 +*N ropt_net_141:3 *C 2.345 58.480 +*N ropt_net_141:4 *C 2.300 58.435 +*N ropt_net_141:5 *C 2.300 50.705 +*N ropt_net_141:6 *C 2.345 50.660 +*N ropt_net_141:7 *C 4.103 50.660 + +*CAP +0 mux_right_ipin_13\/BUFT_P_106:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_141:2 6.782294e-05 +3 ropt_net_141:3 6.782294e-05 +4 ropt_net_141:4 0.0003828622 +5 ropt_net_141:5 0.0003828622 +6 ropt_net_141:6 0.0001178253 +7 ropt_net_141:7 0.0001178253 + +*RES +0 mux_right_ipin_13\/BUFT_P_106:X ropt_net_141:7 0.152 +1 ropt_net_141:7 ropt_net_141:6 0.001569197 +2 ropt_net_141:6 ropt_net_141:5 0.0045 +3 ropt_net_141:5 ropt_net_141:4 0.006901786 +4 ropt_net_141:3 ropt_net_141:2 0.0007477679 +5 ropt_net_141:4 ropt_net_141:3 0.0045 +6 ropt_net_141:2 ropt_mt_inst_740:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.004630413 //LENGTH 37.290 LUMPCC 0.0004411719 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.445 42.500 +*I mux_left_ipin_0\/mux_l2_in_0_:S I *L 0.00357 *C 65.220 45.560 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 74.235 53.380 +*I mux_left_ipin_0\/mux_l2_in_2_:S I *L 0.00357 *C 67.520 57.800 +*I mux_left_ipin_0\/mux_l2_in_3_:S I *L 0.00357 *C 73.040 56.055 +*I mux_left_ipin_0\/mux_l2_in_1_:S I *L 0.00357 *C 73.500 50.615 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 73.500 50.615 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 73.040 56.055 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 72.983 55.760 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 67.558 57.800 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 69.875 57.800 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 69.920 57.755 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 69.920 55.805 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 69.965 55.760 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 72.680 55.760 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 72.680 55.420 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 74.015 55.420 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 74.060 55.375 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 74.235 53.380 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 74.060 53.380 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 74.060 53.380 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 74.060 51.045 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 74.015 51.000 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 73.500 51.000 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 72.265 51.000 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 72.220 50.955 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 72.220 45.560 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 65.258 45.560 +*N mux_tree_tapbuf_size10_0_sram[1]:28 *C 71.715 45.560 +*N mux_tree_tapbuf_size10_0_sram[1]:29 *C 71.760 45.560 +*N mux_tree_tapbuf_size10_0_sram[1]:30 *C 71.760 42.545 +*N mux_tree_tapbuf_size10_0_sram[1]:31 *C 71.805 42.500 +*N mux_tree_tapbuf_size10_0_sram[1]:32 *C 73.407 42.500 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_ipin_0\/mux_l2_in_0_:S 1e-06 +2 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_ipin_0\/mux_l2_in_2_:S 1e-06 +4 mux_left_ipin_0\/mux_l2_in_3_:S 1e-06 +5 mux_left_ipin_0\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 5.615339e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:7 6.951104e-05 +8 mux_tree_tapbuf_size10_0_sram[1]:8 6.591478e-05 +9 mux_tree_tapbuf_size10_0_sram[1]:9 0.0001684067 +10 mux_tree_tapbuf_size10_0_sram[1]:10 0.0001684067 +11 mux_tree_tapbuf_size10_0_sram[1]:11 0.0001237702 +12 mux_tree_tapbuf_size10_0_sram[1]:12 0.0001237702 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.000198976 +14 mux_tree_tapbuf_size10_0_sram[1]:14 0.0002546684 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0001137124 +16 mux_tree_tapbuf_size10_0_sram[1]:16 8.863011e-05 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0001233938 +18 mux_tree_tapbuf_size10_0_sram[1]:18 4.985977e-05 +19 mux_tree_tapbuf_size10_0_sram[1]:19 5.229506e-05 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0002735299 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0001221546 +22 mux_tree_tapbuf_size10_0_sram[1]:22 5.172746e-05 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0001840621 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0001034549 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0002573707 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.000235437 +27 mux_tree_tapbuf_size10_0_sram[1]:27 0.0003753213 +28 mux_tree_tapbuf_size10_0_sram[1]:28 0.0003753213 +29 mux_tree_tapbuf_size10_0_sram[1]:29 0.0001532895 +30 mux_tree_tapbuf_size10_0_sram[1]:30 0.0001752232 +31 mux_tree_tapbuf_size10_0_sram[1]:31 0.0001094402 +32 mux_tree_tapbuf_size10_0_sram[1]:32 0.0001094402 +33 mux_tree_tapbuf_size10_0_sram[1]:25 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.261737e-05 +34 mux_tree_tapbuf_size10_0_sram[1]:26 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.261737e-05 +35 mux_tree_tapbuf_size10_0_sram[1]:28 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.187937e-05 +36 mux_tree_tapbuf_size10_0_sram[1]:29 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.608923e-05 +37 mux_tree_tapbuf_size10_0_sram[1]:27 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.187937e-05 +38 mux_tree_tapbuf_size10_0_sram[1]:26 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.608923e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.001102679 +2 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0045 +3 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.001191964 +4 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +5 mux_tree_tapbuf_size10_0_sram[1]:6 mux_left_ipin_0\/mux_l2_in_1_:S 0.152 +6 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 9.510871e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0045 +8 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:17 0.00178125 +9 mux_tree_tapbuf_size10_0_sram[1]:18 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:30 0.0045 +11 mux_tree_tapbuf_size10_0_sram[1]:30 mux_tree_tapbuf_size10_0_sram[1]:29 0.002691964 +12 mux_tree_tapbuf_size10_0_sram[1]:32 mux_tree_tapbuf_size10_0_sram[1]:31 0.001430804 +13 mux_tree_tapbuf_size10_0_sram[1]:7 mux_left_ipin_0\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +15 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.001741072 +16 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.002069197 +17 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.0045 +18 mux_tree_tapbuf_size10_0_sram[1]:9 mux_left_ipin_0\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.0045 +20 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.002084821 +21 mux_tree_tapbuf_size10_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:27 0.005765625 +22 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:28 0.0045 +23 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:26 0.0004107143 +24 mux_tree_tapbuf_size10_0_sram[1]:27 mux_left_ipin_0\/mux_l2_in_0_:S 0.152 +25 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:13 0.002424107 +26 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:8 0.0002700893 +27 mux_tree_tapbuf_size10_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:7 0.0001715116 +28 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0004598215 +29 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:6 0.0003437501 +30 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0003035715 +31 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.004816964 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[1] 0.008322003 //LENGTH 59.475 LUMPCC 0.001059361 DR + +*CONN +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 67.325 98.600 +*I mux_right_ipin_1\/mux_l2_in_3_:S I *L 0.00357 *C 42.440 94.520 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 36.515 96.900 +*I mux_right_ipin_1\/mux_l2_in_2_:S I *L 0.00357 *C 44.720 90.830 +*I mux_right_ipin_1\/mux_l2_in_1_:S I *L 0.00357 *C 53.460 94.520 +*I mux_right_ipin_1\/mux_l2_in_0_:S I *L 0.00357 *C 53.020 90.780 +*N mux_tree_tapbuf_size10_2_sram[1]:6 *C 53.360 94.520 +*N mux_tree_tapbuf_size10_2_sram[1]:7 *C 53.360 94.475 +*N mux_tree_tapbuf_size10_2_sram[1]:8 *C 53.360 90.825 +*N mux_tree_tapbuf_size10_2_sram[1]:9 *C 53.338 90.780 +*N mux_tree_tapbuf_size10_2_sram[1]:10 *C 53.035 90.780 +*N mux_tree_tapbuf_size10_2_sram[1]:11 *C 53.020 90.780 +*N mux_tree_tapbuf_size10_2_sram[1]:12 *C 51.160 90.830 +*N mux_tree_tapbuf_size10_2_sram[1]:13 *C 51.073 91.120 +*N mux_tree_tapbuf_size10_2_sram[1]:14 *C 44.720 90.830 +*N mux_tree_tapbuf_size10_2_sram[1]:15 *C 36.515 96.900 +*N mux_tree_tapbuf_size10_2_sram[1]:16 *C 36.800 96.900 +*N mux_tree_tapbuf_size10_2_sram[1]:17 *C 36.800 96.945 +*N mux_tree_tapbuf_size10_2_sram[1]:18 *C 36.800 98.895 +*N mux_tree_tapbuf_size10_2_sram[1]:19 *C 36.845 98.940 +*N mux_tree_tapbuf_size10_2_sram[1]:20 *C 42.735 98.940 +*N mux_tree_tapbuf_size10_2_sram[1]:21 *C 42.780 98.895 +*N mux_tree_tapbuf_size10_2_sram[1]:22 *C 42.455 94.520 +*N mux_tree_tapbuf_size10_2_sram[1]:23 *C 42.758 94.520 +*N mux_tree_tapbuf_size10_2_sram[1]:24 *C 42.780 94.520 +*N mux_tree_tapbuf_size10_2_sram[1]:25 *C 42.780 91.165 +*N mux_tree_tapbuf_size10_2_sram[1]:26 *C 42.825 91.120 +*N mux_tree_tapbuf_size10_2_sram[1]:27 *C 44.610 91.120 +*N mux_tree_tapbuf_size10_2_sram[1]:28 *C 51.117 91.090 +*N mux_tree_tapbuf_size10_2_sram[1]:29 *C 51.060 91.165 +*N mux_tree_tapbuf_size10_2_sram[1]:30 *C 51.060 96.515 +*N mux_tree_tapbuf_size10_2_sram[1]:31 *C 51.105 96.560 +*N mux_tree_tapbuf_size10_2_sram[1]:32 *C 51.520 96.560 +*N mux_tree_tapbuf_size10_2_sram[1]:33 *C 51.520 96.900 +*N mux_tree_tapbuf_size10_2_sram[1]:34 *C 53.820 96.900 +*N mux_tree_tapbuf_size10_2_sram[1]:35 *C 53.820 96.560 +*N mux_tree_tapbuf_size10_2_sram[1]:36 *C 59.800 96.560 +*N mux_tree_tapbuf_size10_2_sram[1]:37 *C 59.800 96.220 +*N mux_tree_tapbuf_size10_2_sram[1]:38 *C 62.515 96.220 +*N mux_tree_tapbuf_size10_2_sram[1]:39 *C 62.560 96.265 +*N mux_tree_tapbuf_size10_2_sram[1]:40 *C 62.560 98.555 +*N mux_tree_tapbuf_size10_2_sram[1]:41 *C 62.605 98.600 +*N mux_tree_tapbuf_size10_2_sram[1]:42 *C 67.288 98.600 + +*CAP +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_1\/mux_l2_in_3_:S 1e-06 +2 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_ipin_1\/mux_l2_in_2_:S 1e-06 +4 mux_right_ipin_1\/mux_l2_in_1_:S 1e-06 +5 mux_right_ipin_1\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_2_sram[1]:6 3.529183e-05 +7 mux_tree_tapbuf_size10_2_sram[1]:7 0.0002156703 +8 mux_tree_tapbuf_size10_2_sram[1]:8 0.0002156703 +9 mux_tree_tapbuf_size10_2_sram[1]:9 5.601259e-05 +10 mux_tree_tapbuf_size10_2_sram[1]:10 5.601259e-05 +11 mux_tree_tapbuf_size10_2_sram[1]:11 1e-06 +12 mux_tree_tapbuf_size10_2_sram[1]:12 5.420334e-05 +13 mux_tree_tapbuf_size10_2_sram[1]:13 2.873185e-05 +14 mux_tree_tapbuf_size10_2_sram[1]:14 5.882952e-05 +15 mux_tree_tapbuf_size10_2_sram[1]:15 5.62203e-05 +16 mux_tree_tapbuf_size10_2_sram[1]:16 6.057267e-05 +17 mux_tree_tapbuf_size10_2_sram[1]:17 0.0001576272 +18 mux_tree_tapbuf_size10_2_sram[1]:18 0.0001576272 +19 mux_tree_tapbuf_size10_2_sram[1]:19 0.000427854 +20 mux_tree_tapbuf_size10_2_sram[1]:20 0.000427854 +21 mux_tree_tapbuf_size10_2_sram[1]:21 0.0003026139 +22 mux_tree_tapbuf_size10_2_sram[1]:22 6.35781e-05 +23 mux_tree_tapbuf_size10_2_sram[1]:23 6.35781e-05 +24 mux_tree_tapbuf_size10_2_sram[1]:24 0.0005418065 +25 mux_tree_tapbuf_size10_2_sram[1]:25 0.0002042298 +26 mux_tree_tapbuf_size10_2_sram[1]:26 0.0001349485 +27 mux_tree_tapbuf_size10_2_sram[1]:27 0.0005866438 +28 mux_tree_tapbuf_size10_2_sram[1]:28 0.0004748833 +29 mux_tree_tapbuf_size10_2_sram[1]:29 0.0002248624 +30 mux_tree_tapbuf_size10_2_sram[1]:30 0.0002248624 +31 mux_tree_tapbuf_size10_2_sram[1]:31 4.127443e-05 +32 mux_tree_tapbuf_size10_2_sram[1]:32 6.731797e-05 +33 mux_tree_tapbuf_size10_2_sram[1]:33 0.0001613297 +34 mux_tree_tapbuf_size10_2_sram[1]:34 0.0001621389 +35 mux_tree_tapbuf_size10_2_sram[1]:35 0.0002726283 +36 mux_tree_tapbuf_size10_2_sram[1]:36 0.0002722635 +37 mux_tree_tapbuf_size10_2_sram[1]:37 0.0002293102 +38 mux_tree_tapbuf_size10_2_sram[1]:38 0.0002028223 +39 mux_tree_tapbuf_size10_2_sram[1]:39 0.0001816079 +40 mux_tree_tapbuf_size10_2_sram[1]:40 0.0001816079 +41 mux_tree_tapbuf_size10_2_sram[1]:41 0.0003265782 +42 mux_tree_tapbuf_size10_2_sram[1]:42 0.0003265782 +43 mux_tree_tapbuf_size10_2_sram[1]:38 chany_top_in[6]:4 7.3735e-09 +44 mux_tree_tapbuf_size10_2_sram[1]:30 chany_top_in[6]:15 0.0001472835 +45 mux_tree_tapbuf_size10_2_sram[1]:29 chany_top_in[6]:14 0.0001472835 +46 mux_tree_tapbuf_size10_2_sram[1]:7 chany_top_in[6]:15 4.428836e-06 +47 mux_tree_tapbuf_size10_2_sram[1]:8 chany_top_in[6]:14 4.428836e-06 +48 mux_tree_tapbuf_size10_2_sram[1]:33 chany_top_in[6]:5 7.499059e-05 +49 mux_tree_tapbuf_size10_2_sram[1]:34 chany_top_in[6]:4 7.499059e-05 +50 mux_tree_tapbuf_size10_2_sram[1]:35 chany_top_in[6]:5 4.403713e-05 +51 mux_tree_tapbuf_size10_2_sram[1]:36 chany_top_in[6]:4 4.403713e-05 +52 mux_tree_tapbuf_size10_2_sram[1]:37 chany_top_in[6]:5 7.3735e-09 +53 mux_tree_tapbuf_size10_2_sram[1]:7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.597042e-06 +54 mux_tree_tapbuf_size10_2_sram[1]:8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.597042e-06 +55 mux_tree_tapbuf_size10_2_sram[1]:35 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001342318 +56 mux_tree_tapbuf_size10_2_sram[1]:36 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001342318 +57 mux_tree_tapbuf_size10_2_sram[1]:38 ropt_net_186:3 2.349019e-05 +58 mux_tree_tapbuf_size10_2_sram[1]:35 ropt_net_186:4 9.749201e-05 +59 mux_tree_tapbuf_size10_2_sram[1]:36 ropt_net_186:3 9.761402e-05 +60 mux_tree_tapbuf_size10_2_sram[1]:37 ropt_net_186:2 1.22012e-07 +61 mux_tree_tapbuf_size10_2_sram[1]:37 ropt_net_186:4 2.349019e-05 + +*RES +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_2_sram[1]:42 0.152 +1 mux_tree_tapbuf_size10_2_sram[1]:23 mux_tree_tapbuf_size10_2_sram[1]:22 0.0001644022 +2 mux_tree_tapbuf_size10_2_sram[1]:24 mux_tree_tapbuf_size10_2_sram[1]:23 0.0045 +3 mux_tree_tapbuf_size10_2_sram[1]:24 mux_tree_tapbuf_size10_2_sram[1]:21 0.00390625 +4 mux_tree_tapbuf_size10_2_sram[1]:22 mux_right_ipin_1\/mux_l2_in_3_:S 0.152 +5 mux_tree_tapbuf_size10_2_sram[1]:42 mux_tree_tapbuf_size10_2_sram[1]:41 0.004180804 +6 mux_tree_tapbuf_size10_2_sram[1]:41 mux_tree_tapbuf_size10_2_sram[1]:40 0.0045 +7 mux_tree_tapbuf_size10_2_sram[1]:40 mux_tree_tapbuf_size10_2_sram[1]:39 0.002044643 +8 mux_tree_tapbuf_size10_2_sram[1]:38 mux_tree_tapbuf_size10_2_sram[1]:37 0.002424107 +9 mux_tree_tapbuf_size10_2_sram[1]:39 mux_tree_tapbuf_size10_2_sram[1]:38 0.0045 +10 mux_tree_tapbuf_size10_2_sram[1]:31 mux_tree_tapbuf_size10_2_sram[1]:30 0.0045 +11 mux_tree_tapbuf_size10_2_sram[1]:30 mux_tree_tapbuf_size10_2_sram[1]:29 0.004776786 +12 mux_tree_tapbuf_size10_2_sram[1]:28 mux_tree_tapbuf_size10_2_sram[1]:27 0.005810268 +13 mux_tree_tapbuf_size10_2_sram[1]:28 mux_tree_tapbuf_size10_2_sram[1]:13 4.017857e-05 +14 mux_tree_tapbuf_size10_2_sram[1]:28 mux_tree_tapbuf_size10_2_sram[1]:12 0.000112069 +15 mux_tree_tapbuf_size10_2_sram[1]:29 mux_tree_tapbuf_size10_2_sram[1]:28 0.0045 +16 mux_tree_tapbuf_size10_2_sram[1]:26 mux_tree_tapbuf_size10_2_sram[1]:25 0.0045 +17 mux_tree_tapbuf_size10_2_sram[1]:25 mux_tree_tapbuf_size10_2_sram[1]:24 0.002995536 +18 mux_tree_tapbuf_size10_2_sram[1]:14 mux_right_ipin_1\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_2_sram[1]:6 mux_right_ipin_1\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_2_sram[1]:7 mux_tree_tapbuf_size10_2_sram[1]:6 0.0045 +21 mux_tree_tapbuf_size10_2_sram[1]:9 mux_tree_tapbuf_size10_2_sram[1]:8 0.0045 +22 mux_tree_tapbuf_size10_2_sram[1]:8 mux_tree_tapbuf_size10_2_sram[1]:7 0.003258929 +23 mux_tree_tapbuf_size10_2_sram[1]:10 mux_tree_tapbuf_size10_2_sram[1]:9 0.0001644022 +24 mux_tree_tapbuf_size10_2_sram[1]:12 mux_tree_tapbuf_size10_2_sram[1]:11 0.152 +25 mux_tree_tapbuf_size10_2_sram[1]:15 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +26 mux_tree_tapbuf_size10_2_sram[1]:16 mux_tree_tapbuf_size10_2_sram[1]:15 0.0001548913 +27 mux_tree_tapbuf_size10_2_sram[1]:17 mux_tree_tapbuf_size10_2_sram[1]:16 0.0045 +28 mux_tree_tapbuf_size10_2_sram[1]:19 mux_tree_tapbuf_size10_2_sram[1]:18 0.0045 +29 mux_tree_tapbuf_size10_2_sram[1]:18 mux_tree_tapbuf_size10_2_sram[1]:17 0.001741072 +30 mux_tree_tapbuf_size10_2_sram[1]:20 mux_tree_tapbuf_size10_2_sram[1]:19 0.005258929 +31 mux_tree_tapbuf_size10_2_sram[1]:21 mux_tree_tapbuf_size10_2_sram[1]:20 0.0045 +32 mux_tree_tapbuf_size10_2_sram[1]:27 mux_tree_tapbuf_size10_2_sram[1]:26 0.00159375 +33 mux_tree_tapbuf_size10_2_sram[1]:27 mux_tree_tapbuf_size10_2_sram[1]:14 0.000125 +34 mux_tree_tapbuf_size10_2_sram[1]:32 mux_tree_tapbuf_size10_2_sram[1]:31 0.0003705357 +35 mux_tree_tapbuf_size10_2_sram[1]:33 mux_tree_tapbuf_size10_2_sram[1]:32 0.0003035715 +36 mux_tree_tapbuf_size10_2_sram[1]:34 mux_tree_tapbuf_size10_2_sram[1]:33 0.002053572 +37 mux_tree_tapbuf_size10_2_sram[1]:35 mux_tree_tapbuf_size10_2_sram[1]:34 0.0003035715 +38 mux_tree_tapbuf_size10_2_sram[1]:36 mux_tree_tapbuf_size10_2_sram[1]:35 0.005339286 +39 mux_tree_tapbuf_size10_2_sram[1]:37 mux_tree_tapbuf_size10_2_sram[1]:36 0.0003035715 +40 mux_tree_tapbuf_size10_2_sram[1]:11 mux_tree_tapbuf_size10_2_sram[1]:10 0.152 +41 mux_tree_tapbuf_size10_2_sram[1]:11 mux_right_ipin_1\/mux_l2_in_0_:S 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[2] 0.004028038 //LENGTH 30.765 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 66.085 66.300 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 53.075 69.700 +*I mux_right_ipin_5\/mux_l3_in_0_:S I *L 0.00357 *C 58.980 61.880 +*I mux_right_ipin_5\/mux_l3_in_1_:S I *L 0.00357 *C 65.420 63.920 +*N mux_tree_tapbuf_size10_4_sram[2]:4 *C 65.420 63.920 +*N mux_tree_tapbuf_size10_4_sram[2]:5 *C 59.018 61.880 +*N mux_tree_tapbuf_size10_4_sram[2]:6 *C 64.355 61.880 +*N mux_tree_tapbuf_size10_4_sram[2]:7 *C 64.400 61.925 +*N mux_tree_tapbuf_size10_4_sram[2]:8 *C 53.113 69.700 +*N mux_tree_tapbuf_size10_4_sram[2]:9 *C 63.895 69.700 +*N mux_tree_tapbuf_size10_4_sram[2]:10 *C 63.940 69.655 +*N mux_tree_tapbuf_size10_4_sram[2]:11 *C 63.940 64.260 +*N mux_tree_tapbuf_size10_4_sram[2]:12 *C 64.400 64.215 +*N mux_tree_tapbuf_size10_4_sram[2]:13 *C 64.445 64.260 +*N mux_tree_tapbuf_size10_4_sram[2]:14 *C 65.365 64.252 +*N mux_tree_tapbuf_size10_4_sram[2]:15 *C 65.320 64.260 +*N mux_tree_tapbuf_size10_4_sram[2]:16 *C 65.780 64.260 +*N mux_tree_tapbuf_size10_4_sram[2]:17 *C 65.780 66.255 +*N mux_tree_tapbuf_size10_4_sram[2]:18 *C 65.780 66.300 +*N mux_tree_tapbuf_size10_4_sram[2]:19 *C 66.085 66.300 + +*CAP +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_ipin_5\/mux_l3_in_0_:S 1e-06 +3 mux_right_ipin_5\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_4_sram[2]:4 6.293981e-05 +5 mux_tree_tapbuf_size10_4_sram[2]:5 0.0003838297 +6 mux_tree_tapbuf_size10_4_sram[2]:6 0.0003838297 +7 mux_tree_tapbuf_size10_4_sram[2]:7 0.0001645654 +8 mux_tree_tapbuf_size10_4_sram[2]:8 0.0007800738 +9 mux_tree_tapbuf_size10_4_sram[2]:9 0.0007800738 +10 mux_tree_tapbuf_size10_4_sram[2]:10 0.0003082982 +11 mux_tree_tapbuf_size10_4_sram[2]:11 0.0003404081 +12 mux_tree_tapbuf_size10_4_sram[2]:12 0.0001966752 +13 mux_tree_tapbuf_size10_4_sram[2]:13 7.577572e-05 +14 mux_tree_tapbuf_size10_4_sram[2]:14 0.0001099862 +15 mux_tree_tapbuf_size10_4_sram[2]:15 6.229668e-05 +16 mux_tree_tapbuf_size10_4_sram[2]:16 0.0001528269 +17 mux_tree_tapbuf_size10_4_sram[2]:17 0.0001207171 +18 mux_tree_tapbuf_size10_4_sram[2]:18 5.418493e-05 +19 mux_tree_tapbuf_size10_4_sram[2]:19 4.755653e-05 + +*RES +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_4_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_4_sram[2]:6 mux_tree_tapbuf_size10_4_sram[2]:5 0.004765626 +2 mux_tree_tapbuf_size10_4_sram[2]:7 mux_tree_tapbuf_size10_4_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size10_4_sram[2]:5 mux_right_ipin_5\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_4_sram[2]:13 mux_tree_tapbuf_size10_4_sram[2]:12 0.0045 +5 mux_tree_tapbuf_size10_4_sram[2]:12 mux_tree_tapbuf_size10_4_sram[2]:11 0.0004107143 +6 mux_tree_tapbuf_size10_4_sram[2]:12 mux_tree_tapbuf_size10_4_sram[2]:7 0.002044643 +7 mux_tree_tapbuf_size10_4_sram[2]:14 mux_tree_tapbuf_size10_4_sram[2]:13 0.0008214285 +8 mux_tree_tapbuf_size10_4_sram[2]:14 mux_tree_tapbuf_size10_4_sram[2]:4 0.0001807065 +9 mux_tree_tapbuf_size10_4_sram[2]:15 mux_tree_tapbuf_size10_4_sram[2]:14 0.0045 +10 mux_tree_tapbuf_size10_4_sram[2]:18 mux_tree_tapbuf_size10_4_sram[2]:17 0.0045 +11 mux_tree_tapbuf_size10_4_sram[2]:17 mux_tree_tapbuf_size10_4_sram[2]:16 0.00178125 +12 mux_tree_tapbuf_size10_4_sram[2]:19 mux_tree_tapbuf_size10_4_sram[2]:18 0.0001657609 +13 mux_tree_tapbuf_size10_4_sram[2]:9 mux_tree_tapbuf_size10_4_sram[2]:8 0.009627232 +14 mux_tree_tapbuf_size10_4_sram[2]:10 mux_tree_tapbuf_size10_4_sram[2]:9 0.0045 +15 mux_tree_tapbuf_size10_4_sram[2]:8 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +16 mux_tree_tapbuf_size10_4_sram[2]:4 mux_right_ipin_5\/mux_l3_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_4_sram[2]:11 mux_tree_tapbuf_size10_4_sram[2]:10 0.004816964 +18 mux_tree_tapbuf_size10_4_sram[2]:16 mux_tree_tapbuf_size10_4_sram[2]:15 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[0] 0.005564034 //LENGTH 44.440 LUMPCC 0.0002600491 DR + +*CONN +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 45.385 31.280 +*I mux_right_ipin_9\/mux_l1_in_0_:S I *L 0.00357 *C 54.620 23.800 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 68.715 28.220 +*I mux_right_ipin_9\/mux_l1_in_2_:S I *L 0.00357 *C 72.780 25.160 +*I mux_right_ipin_9\/mux_l1_in_1_:S I *L 0.00357 *C 52.800 25.550 +*N mux_tree_tapbuf_size10_6_sram[0]:5 *C 52.800 25.550 +*N mux_tree_tapbuf_size10_6_sram[0]:6 *C 52.742 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:7 *C 72.680 25.160 +*N mux_tree_tapbuf_size10_6_sram[0]:8 *C 72.680 25.115 +*N mux_tree_tapbuf_size10_6_sram[0]:9 *C 72.680 23.505 +*N mux_tree_tapbuf_size10_6_sram[0]:10 *C 72.635 23.460 +*N mux_tree_tapbuf_size10_6_sram[0]:11 *C 69.000 23.460 +*N mux_tree_tapbuf_size10_6_sram[0]:12 *C 68.715 28.220 +*N mux_tree_tapbuf_size10_6_sram[0]:13 *C 69.000 28.220 +*N mux_tree_tapbuf_size10_6_sram[0]:14 *C 69.000 28.175 +*N mux_tree_tapbuf_size10_6_sram[0]:15 *C 69.000 23.845 +*N mux_tree_tapbuf_size10_6_sram[0]:16 *C 69.000 23.770 +*N mux_tree_tapbuf_size10_6_sram[0]:17 *C 54.620 23.800 +*N mux_tree_tapbuf_size10_6_sram[0]:18 *C 52.945 23.800 +*N mux_tree_tapbuf_size10_6_sram[0]:19 *C 52.900 23.845 +*N mux_tree_tapbuf_size10_6_sram[0]:20 *C 52.900 25.795 +*N mux_tree_tapbuf_size10_6_sram[0]:21 *C 52.843 25.810 +*N mux_tree_tapbuf_size10_6_sram[0]:22 *C 46.505 25.840 +*N mux_tree_tapbuf_size10_6_sram[0]:23 *C 46.460 25.885 +*N mux_tree_tapbuf_size10_6_sram[0]:24 *C 46.460 31.235 +*N mux_tree_tapbuf_size10_6_sram[0]:25 *C 46.415 31.280 +*N mux_tree_tapbuf_size10_6_sram[0]:26 *C 45.422 31.280 + +*CAP +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_9\/mux_l1_in_0_:S 1e-06 +2 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_ipin_9\/mux_l1_in_2_:S 1e-06 +4 mux_right_ipin_9\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_6_sram[0]:5 5.709123e-05 +6 mux_tree_tapbuf_size10_6_sram[0]:6 2.096478e-05 +7 mux_tree_tapbuf_size10_6_sram[0]:7 3.376184e-05 +8 mux_tree_tapbuf_size10_6_sram[0]:8 6.577464e-05 +9 mux_tree_tapbuf_size10_6_sram[0]:9 6.577464e-05 +10 mux_tree_tapbuf_size10_6_sram[0]:10 0.0002320179 +11 mux_tree_tapbuf_size10_6_sram[0]:11 0.0002588838 +12 mux_tree_tapbuf_size10_6_sram[0]:12 5.034211e-05 +13 mux_tree_tapbuf_size10_6_sram[0]:13 5.470237e-05 +14 mux_tree_tapbuf_size10_6_sram[0]:14 0.0002467094 +15 mux_tree_tapbuf_size10_6_sram[0]:15 0.0002467094 +16 mux_tree_tapbuf_size10_6_sram[0]:16 0.0008915731 +17 mux_tree_tapbuf_size10_6_sram[0]:17 0.001014596 +18 mux_tree_tapbuf_size10_6_sram[0]:18 0.0001219945 +19 mux_tree_tapbuf_size10_6_sram[0]:19 0.0001368414 +20 mux_tree_tapbuf_size10_6_sram[0]:20 0.0001368414 +21 mux_tree_tapbuf_size10_6_sram[0]:21 0.0004810501 +22 mux_tree_tapbuf_size10_6_sram[0]:22 0.0004344456 +23 mux_tree_tapbuf_size10_6_sram[0]:23 0.0002972451 +24 mux_tree_tapbuf_size10_6_sram[0]:24 0.0002972451 +25 mux_tree_tapbuf_size10_6_sram[0]:25 7.720985e-05 +26 mux_tree_tapbuf_size10_6_sram[0]:26 7.720985e-05 +27 mux_tree_tapbuf_size10_6_sram[0]:17 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.315329e-05 +28 mux_tree_tapbuf_size10_6_sram[0]:16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.315329e-05 +29 mux_tree_tapbuf_size10_6_sram[0]:9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.687126e-05 +30 mux_tree_tapbuf_size10_6_sram[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.687126e-05 + +*RES +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_6_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_6_sram[0]:17 mux_right_ipin_9\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_6_sram[0]:17 mux_tree_tapbuf_size10_6_sram[0]:16 0.01283929 +3 mux_tree_tapbuf_size10_6_sram[0]:22 mux_tree_tapbuf_size10_6_sram[0]:21 0.005658482 +4 mux_tree_tapbuf_size10_6_sram[0]:23 mux_tree_tapbuf_size10_6_sram[0]:22 0.0045 +5 mux_tree_tapbuf_size10_6_sram[0]:25 mux_tree_tapbuf_size10_6_sram[0]:24 0.0045 +6 mux_tree_tapbuf_size10_6_sram[0]:24 mux_tree_tapbuf_size10_6_sram[0]:23 0.004776786 +7 mux_tree_tapbuf_size10_6_sram[0]:26 mux_tree_tapbuf_size10_6_sram[0]:25 0.0008861606 +8 mux_tree_tapbuf_size10_6_sram[0]:10 mux_tree_tapbuf_size10_6_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size10_6_sram[0]:9 mux_tree_tapbuf_size10_6_sram[0]:8 0.0014375 +10 mux_tree_tapbuf_size10_6_sram[0]:7 mux_right_ipin_9\/mux_l1_in_2_:S 0.152 +11 mux_tree_tapbuf_size10_6_sram[0]:8 mux_tree_tapbuf_size10_6_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size10_6_sram[0]:5 mux_right_ipin_9\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[0]:16 mux_tree_tapbuf_size10_6_sram[0]:15 0.0045 +14 mux_tree_tapbuf_size10_6_sram[0]:16 mux_tree_tapbuf_size10_6_sram[0]:11 0.0002767857 +15 mux_tree_tapbuf_size10_6_sram[0]:15 mux_tree_tapbuf_size10_6_sram[0]:14 0.003866072 +16 mux_tree_tapbuf_size10_6_sram[0]:13 mux_tree_tapbuf_size10_6_sram[0]:12 0.0001548913 +17 mux_tree_tapbuf_size10_6_sram[0]:14 mux_tree_tapbuf_size10_6_sram[0]:13 0.0045 +18 mux_tree_tapbuf_size10_6_sram[0]:12 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:20 0.0045 +20 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:6 8.928572e-05 +21 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:5 0.000112069 +22 mux_tree_tapbuf_size10_6_sram[0]:20 mux_tree_tapbuf_size10_6_sram[0]:19 0.001741072 +23 mux_tree_tapbuf_size10_6_sram[0]:18 mux_tree_tapbuf_size10_6_sram[0]:17 0.001495536 +24 mux_tree_tapbuf_size10_6_sram[0]:19 mux_tree_tapbuf_size10_6_sram[0]:18 0.0045 +25 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:10 0.003245536 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[3] 0.001358152 //LENGTH 10.620 LUMPCC 7.421224e-05 DR + +*CONN +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 23.305 23.120 +*I mux_right_ipin_12\/mux_l4_in_0_:S I *L 0.00357 *C 19.440 19.720 +*I mem_right_ipin_12\/FTB_8__47:A I *L 0.001746 *C 25.760 23.120 +*N mux_tree_tapbuf_size10_7_sram[3]:3 *C 25.723 23.120 +*N mux_tree_tapbuf_size10_7_sram[3]:4 *C 19.478 19.720 +*N mux_tree_tapbuf_size10_7_sram[3]:5 *C 22.955 19.720 +*N mux_tree_tapbuf_size10_7_sram[3]:6 *C 23.000 19.765 +*N mux_tree_tapbuf_size10_7_sram[3]:7 *C 23.000 23.075 +*N mux_tree_tapbuf_size10_7_sram[3]:8 *C 23.000 23.120 +*N mux_tree_tapbuf_size10_7_sram[3]:9 *C 23.343 23.120 + +*CAP +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_12\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_12\/FTB_8__47:A 1e-06 +3 mux_tree_tapbuf_size10_7_sram[3]:3 0.0001432099 +4 mux_tree_tapbuf_size10_7_sram[3]:4 0.0002726252 +5 mux_tree_tapbuf_size10_7_sram[3]:5 0.0002726252 +6 mux_tree_tapbuf_size10_7_sram[3]:6 0.0001925118 +7 mux_tree_tapbuf_size10_7_sram[3]:7 0.0001925118 +8 mux_tree_tapbuf_size10_7_sram[3]:8 4.753866e-05 +9 mux_tree_tapbuf_size10_7_sram[3]:9 0.0001599168 +10 mux_tree_tapbuf_size10_7_sram[3]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.248192e-06 +11 mux_tree_tapbuf_size10_7_sram[3]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.248192e-06 +12 mux_tree_tapbuf_size10_7_sram[3]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.585792e-05 +13 mux_tree_tapbuf_size10_7_sram[3]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.585792e-05 + +*RES +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_7_sram[3]:9 0.152 +1 mux_tree_tapbuf_size10_7_sram[3]:4 mux_right_ipin_12\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[3]:5 mux_tree_tapbuf_size10_7_sram[3]:4 0.003104911 +3 mux_tree_tapbuf_size10_7_sram[3]:6 mux_tree_tapbuf_size10_7_sram[3]:5 0.0045 +4 mux_tree_tapbuf_size10_7_sram[3]:8 mux_tree_tapbuf_size10_7_sram[3]:7 0.0045 +5 mux_tree_tapbuf_size10_7_sram[3]:7 mux_tree_tapbuf_size10_7_sram[3]:6 0.002955357 +6 mux_tree_tapbuf_size10_7_sram[3]:9 mux_tree_tapbuf_size10_7_sram[3]:8 0.0001861413 +7 mux_tree_tapbuf_size10_7_sram[3]:9 mux_tree_tapbuf_size10_7_sram[3]:3 0.002125 +8 mux_tree_tapbuf_size10_7_sram[3]:3 mem_right_ipin_12\/FTB_8__47:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.001268182 //LENGTH 10.425 LUMPCC 0.0001240298 DR + +*CONN +*I mem_left_ipin_0\/FTB_1__40:X O *L 0 *C 77.970 61.880 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 72.865 66.300 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 72.865 66.300 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 77.235 66.300 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 77.280 66.255 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 77.280 61.925 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 77.325 61.880 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 77.933 61.880 + +*CAP +0 mem_left_ipin_0\/FTB_1__40:X 1e-06 +1 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0003455248 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0003078679 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0001840868 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0001840868 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 6.029298e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 6.029298e-05 +8 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 chany_top_in[4]:25 6.201491e-05 +9 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 chany_top_in[4]:22 6.201491e-05 + +*RES +0 mem_left_ipin_0\/FTB_1__40:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.003901785 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0005424108 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_4_ccff_tail[0] 0.0007877304 //LENGTH 6.765 LUMPCC 8.353129e-05 DR + +*CONN +*I mem_right_ipin_5\/FTB_5__44:X O *L 0 *C 49.850 72.420 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.555 75.140 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 *C 47.578 75.168 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 *C 47.590 75.480 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 *C 49.175 75.480 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 *C 49.220 75.435 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 *C 49.220 72.465 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 *C 49.265 72.420 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:8 *C 49.812 72.420 + +*CAP +0 mem_right_ipin_5\/FTB_5__44:X 1e-06 +1 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 3.097495e-05 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.0001567761 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0001258012 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0001369045 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.0001369045 +7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 5.741887e-05 +8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:8 5.741887e-05 +9 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 4.176564e-05 +10 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 4.176564e-05 + +*RES +0 mem_right_ipin_5\/FTB_5__44:X mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.0004888393 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.002651786 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.001415179 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_8_ccff_tail[0] 0.0009832045 //LENGTH 8.000 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_13\/FTB_9__48:X O *L 0 *C 41.625 25.500 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 37.435 28.220 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 *C 37.435 28.220 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 *C 37.260 28.220 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 *C 37.260 28.175 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 *C 37.260 25.545 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 *C 37.305 25.500 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 *C 41.587 25.500 + +*CAP +0 mem_right_ipin_13\/FTB_9__48:X 1e-06 +1 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 5.620266e-05 +3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 5.662765e-05 +4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 0.0001768052 +5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 0.0001768052 +6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 0.0002573819 +7 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 0.0002573819 + +*RES +0 mem_right_ipin_13\/FTB_9__48:X mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 9.510871e-05 +3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 0.003823661 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[1] 0.003886685 //LENGTH 29.330 LUMPCC 0.0005038916 DR + +*CONN +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 15.485 61.200 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 7.075 66.300 +*I mux_right_ipin_3\/mux_l2_in_2_:S I *L 0.00357 *C 24.280 61.125 +*I mux_right_ipin_3\/mux_l2_in_1_:S I *L 0.00357 *C 25.880 63.240 +*I mux_right_ipin_3\/mux_l2_in_3_:S I *L 0.00357 *C 26.780 61.200 +*I mux_right_ipin_3\/mux_l2_in_0_:S I *L 0.00357 *C 20.140 61.495 +*N mux_tree_tapbuf_size8_1_sram[1]:6 *C 20.140 61.495 +*N mux_tree_tapbuf_size8_1_sram[1]:7 *C 26.742 61.200 +*N mux_tree_tapbuf_size8_1_sram[1]:8 *C 25.895 63.240 +*N mux_tree_tapbuf_size8_1_sram[1]:9 *C 26.198 63.240 +*N mux_tree_tapbuf_size8_1_sram[1]:10 *C 26.220 63.195 +*N mux_tree_tapbuf_size8_1_sram[1]:11 *C 26.220 61.245 +*N mux_tree_tapbuf_size8_1_sram[1]:12 *C 26.220 61.200 +*N mux_tree_tapbuf_size8_1_sram[1]:13 *C 24.280 61.125 +*N mux_tree_tapbuf_size8_1_sram[1]:14 *C 20.140 61.200 +*N mux_tree_tapbuf_size8_1_sram[1]:15 *C 7.113 66.300 +*N mux_tree_tapbuf_size8_1_sram[1]:16 *C 14.675 66.300 +*N mux_tree_tapbuf_size8_1_sram[1]:17 *C 14.720 66.255 +*N mux_tree_tapbuf_size8_1_sram[1]:18 *C 14.720 61.585 +*N mux_tree_tapbuf_size8_1_sram[1]:19 *C 14.720 61.540 +*N mux_tree_tapbuf_size8_1_sram[1]:20 *C 14.720 61.200 +*N mux_tree_tapbuf_size8_1_sram[1]:21 *C 15.485 61.200 + +*CAP +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_ipin_3\/mux_l2_in_2_:S 1e-06 +3 mux_right_ipin_3\/mux_l2_in_1_:S 1e-06 +4 mux_right_ipin_3\/mux_l2_in_3_:S 1e-06 +5 mux_right_ipin_3\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_1_sram[1]:6 5.61873e-05 +7 mux_tree_tapbuf_size8_1_sram[1]:7 4.026242e-05 +8 mux_tree_tapbuf_size8_1_sram[1]:8 5.655658e-05 +9 mux_tree_tapbuf_size8_1_sram[1]:9 5.655658e-05 +10 mux_tree_tapbuf_size8_1_sram[1]:10 0.0001159697 +11 mux_tree_tapbuf_size8_1_sram[1]:11 0.0001159697 +12 mux_tree_tapbuf_size8_1_sram[1]:12 0.000194232 +13 mux_tree_tapbuf_size8_1_sram[1]:13 0.0004171492 +14 mux_tree_tapbuf_size8_1_sram[1]:14 0.0004950808 +15 mux_tree_tapbuf_size8_1_sram[1]:15 0.0004184541 +16 mux_tree_tapbuf_size8_1_sram[1]:16 0.0004184541 +17 mux_tree_tapbuf_size8_1_sram[1]:17 0.0002962598 +18 mux_tree_tapbuf_size8_1_sram[1]:18 0.0002962598 +19 mux_tree_tapbuf_size8_1_sram[1]:19 5.45598e-05 +20 mux_tree_tapbuf_size8_1_sram[1]:20 7.271113e-05 +21 mux_tree_tapbuf_size8_1_sram[1]:21 0.0002721299 +22 mux_tree_tapbuf_size8_1_sram[1]:18 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.548764e-07 +23 mux_tree_tapbuf_size8_1_sram[1]:17 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.548764e-07 +24 mux_tree_tapbuf_size8_1_sram[1]:21 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.409122e-05 +25 mux_tree_tapbuf_size8_1_sram[1]:14 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.409122e-05 +26 mux_tree_tapbuf_size8_1_sram[1]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.845349e-06 +27 mux_tree_tapbuf_size8_1_sram[1]:13 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.360484e-06 +28 mux_tree_tapbuf_size8_1_sram[1]:12 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.360484e-06 +29 mux_tree_tapbuf_size8_1_sram[1]:12 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.845349e-06 +30 mux_tree_tapbuf_size8_1_sram[1]:11 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.452086e-05 +31 mux_tree_tapbuf_size8_1_sram[1]:10 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.452086e-05 +32 mux_tree_tapbuf_size8_1_sram[1]:18 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.61456e-07 +33 mux_tree_tapbuf_size8_1_sram[1]:16 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001140115 +34 mux_tree_tapbuf_size8_1_sram[1]:17 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.61456e-07 +35 mux_tree_tapbuf_size8_1_sram[1]:15 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001140115 + +*RES +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_1_sram[1]:21 0.152 +1 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:18 0.0045 +2 mux_tree_tapbuf_size8_1_sram[1]:18 mux_tree_tapbuf_size8_1_sram[1]:17 0.004169643 +3 mux_tree_tapbuf_size8_1_sram[1]:16 mux_tree_tapbuf_size8_1_sram[1]:15 0.006752232 +4 mux_tree_tapbuf_size8_1_sram[1]:17 mux_tree_tapbuf_size8_1_sram[1]:16 0.0045 +5 mux_tree_tapbuf_size8_1_sram[1]:15 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +6 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:20 0.0006830358 +7 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:14 0.004156251 +8 mux_tree_tapbuf_size8_1_sram[1]:7 mux_right_ipin_3\/mux_l2_in_3_:S 0.152 +9 mux_tree_tapbuf_size8_1_sram[1]:13 mux_right_ipin_3\/mux_l2_in_2_:S 0.152 +10 mux_tree_tapbuf_size8_1_sram[1]:13 mux_tree_tapbuf_size8_1_sram[1]:12 0.001732143 +11 mux_tree_tapbuf_size8_1_sram[1]:12 mux_tree_tapbuf_size8_1_sram[1]:11 0.0045 +12 mux_tree_tapbuf_size8_1_sram[1]:12 mux_tree_tapbuf_size8_1_sram[1]:7 0.0004665179 +13 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:10 0.001741071 +14 mux_tree_tapbuf_size8_1_sram[1]:9 mux_tree_tapbuf_size8_1_sram[1]:8 0.0001644022 +15 mux_tree_tapbuf_size8_1_sram[1]:10 mux_tree_tapbuf_size8_1_sram[1]:9 0.0045 +16 mux_tree_tapbuf_size8_1_sram[1]:8 mux_right_ipin_3\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size8_1_sram[1]:6 mux_right_ipin_3\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size8_1_sram[1]:20 mux_tree_tapbuf_size8_1_sram[1]:19 0.0003035715 +19 mux_tree_tapbuf_size8_1_sram[1]:14 mux_tree_tapbuf_size8_1_sram[1]:13 0.003696429 +20 mux_tree_tapbuf_size8_1_sram[1]:14 mux_tree_tapbuf_size8_1_sram[1]:6 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[3] 0.002296168 //LENGTH 17.870 LUMPCC 0.0003002018 DR + +*CONN +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 76.200 98.940 +*I mem_right_ipin_7\/FTB_13__52:A I *L 0.001746 *C 70.380 93.840 +*I mux_right_ipin_7\/mux_l4_in_0_:S I *L 0.00357 *C 64.980 94.180 +*N mux_tree_tapbuf_size8_3_sram[3]:3 *C 65.017 94.180 +*N mux_tree_tapbuf_size8_3_sram[3]:4 *C 69.920 94.180 +*N mux_tree_tapbuf_size8_3_sram[3]:5 *C 69.920 93.840 +*N mux_tree_tapbuf_size8_3_sram[3]:6 *C 70.380 93.840 +*N mux_tree_tapbuf_size8_3_sram[3]:7 *C 72.635 93.840 +*N mux_tree_tapbuf_size8_3_sram[3]:8 *C 72.680 93.885 +*N mux_tree_tapbuf_size8_3_sram[3]:9 *C 72.680 98.895 +*N mux_tree_tapbuf_size8_3_sram[3]:10 *C 72.725 98.940 +*N mux_tree_tapbuf_size8_3_sram[3]:11 *C 76.163 98.940 + +*CAP +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_7\/FTB_13__52:A 1e-06 +2 mux_right_ipin_7\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_3_sram[3]:3 0.0003311447 +4 mux_tree_tapbuf_size8_3_sram[3]:4 0.0003508838 +5 mux_tree_tapbuf_size8_3_sram[3]:5 5.085716e-05 +6 mux_tree_tapbuf_size8_3_sram[3]:6 0.0002236028 +7 mux_tree_tapbuf_size8_3_sram[3]:7 0.0001649393 +8 mux_tree_tapbuf_size8_3_sram[3]:8 0.0002959384 +9 mux_tree_tapbuf_size8_3_sram[3]:9 0.0002959384 +10 mux_tree_tapbuf_size8_3_sram[3]:10 0.0001398309 +11 mux_tree_tapbuf_size8_3_sram[3]:11 0.0001398309 +12 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[2]:8 5.358138e-06 +13 mux_tree_tapbuf_size8_3_sram[3]:10 mux_tree_tapbuf_size8_3_sram[2]:10 0.0001447427 +14 mux_tree_tapbuf_size8_3_sram[3]:9 mux_tree_tapbuf_size8_3_sram[2]:9 5.358138e-06 +15 mux_tree_tapbuf_size8_3_sram[3]:11 mux_tree_tapbuf_size8_3_sram[2]:11 0.0001447427 + +*RES +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_3_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_3_sram[3]:6 mem_right_ipin_7\/FTB_13__52:A 0.152 +2 mux_tree_tapbuf_size8_3_sram[3]:6 mux_tree_tapbuf_size8_3_sram[3]:5 0.0004107143 +3 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:6 0.002013393 +4 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[3]:7 0.0045 +5 mux_tree_tapbuf_size8_3_sram[3]:10 mux_tree_tapbuf_size8_3_sram[3]:9 0.0045 +6 mux_tree_tapbuf_size8_3_sram[3]:9 mux_tree_tapbuf_size8_3_sram[3]:8 0.004473215 +7 mux_tree_tapbuf_size8_3_sram[3]:11 mux_tree_tapbuf_size8_3_sram[3]:10 0.003069196 +8 mux_tree_tapbuf_size8_3_sram[3]:3 mux_right_ipin_7\/mux_l4_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_3_sram[3]:4 mux_tree_tapbuf_size8_3_sram[3]:3 0.004377232 +10 mux_tree_tapbuf_size8_3_sram[3]:5 mux_tree_tapbuf_size8_3_sram[3]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[0] 0.002046884 //LENGTH 16.775 LUMPCC 0.0002667274 DR + +*CONN +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 20.085 44.880 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 23.175 47.940 +*I mux_right_ipin_11\/mux_l1_in_0_:S I *L 0.00357 *C 18.500 55.760 +*N mux_tree_tapbuf_size8_5_sram[0]:3 *C 18.538 55.760 +*N mux_tree_tapbuf_size8_5_sram[0]:4 *C 20.195 55.760 +*N mux_tree_tapbuf_size8_5_sram[0]:5 *C 20.240 55.715 +*N mux_tree_tapbuf_size8_5_sram[0]:6 *C 23.138 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:7 *C 20.285 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:8 *C 20.240 47.940 +*N mux_tree_tapbuf_size8_5_sram[0]:9 *C 20.240 44.925 +*N mux_tree_tapbuf_size8_5_sram[0]:10 *C 20.240 44.880 +*N mux_tree_tapbuf_size8_5_sram[0]:11 *C 20.085 44.880 + +*CAP +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_11\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_5_sram[0]:3 0.0001006399 +4 mux_tree_tapbuf_size8_5_sram[0]:4 0.0001006399 +5 mux_tree_tapbuf_size8_5_sram[0]:5 0.0003831318 +6 mux_tree_tapbuf_size8_5_sram[0]:6 0.0001865472 +7 mux_tree_tapbuf_size8_5_sram[0]:7 0.0001865472 +8 mux_tree_tapbuf_size8_5_sram[0]:8 0.0005714867 +9 mux_tree_tapbuf_size8_5_sram[0]:9 0.0001580726 +10 mux_tree_tapbuf_size8_5_sram[0]:10 4.698875e-05 +11 mux_tree_tapbuf_size8_5_sram[0]:11 4.310255e-05 +12 mux_tree_tapbuf_size8_5_sram[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.356336e-05 +13 mux_tree_tapbuf_size8_5_sram[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.356336e-05 +14 mux_tree_tapbuf_size8_5_sram[0]:8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.980036e-05 +15 mux_tree_tapbuf_size8_5_sram[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.980036e-05 + +*RES +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_5_sram[0]:11 0.152 +1 mux_tree_tapbuf_size8_5_sram[0]:10 mux_tree_tapbuf_size8_5_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size8_5_sram[0]:9 mux_tree_tapbuf_size8_5_sram[0]:8 0.002691964 +3 mux_tree_tapbuf_size8_5_sram[0]:11 mux_tree_tapbuf_size8_5_sram[0]:10 8.423914e-05 +4 mux_tree_tapbuf_size8_5_sram[0]:7 mux_tree_tapbuf_size8_5_sram[0]:6 0.002546875 +5 mux_tree_tapbuf_size8_5_sram[0]:8 mux_tree_tapbuf_size8_5_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size8_5_sram[0]:8 mux_tree_tapbuf_size8_5_sram[0]:5 0.006941965 +7 mux_tree_tapbuf_size8_5_sram[0]:6 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_5_sram[0]:4 mux_tree_tapbuf_size8_5_sram[0]:3 0.001479911 +9 mux_tree_tapbuf_size8_5_sram[0]:5 mux_tree_tapbuf_size8_5_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size8_5_sram[0]:3 mux_right_ipin_11\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[1] 0.005127879 //LENGTH 41.665 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.605 71.740 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 72.855 75.140 +*I mux_right_ipin_15\/mux_l2_in_0_:S I *L 0.00357 *C 64.760 77.860 +*I mux_right_ipin_15\/mux_l2_in_1_:S I *L 0.00357 *C 67.260 85.000 +*I mux_right_ipin_15\/mux_l2_in_2_:S I *L 0.00357 *C 78.560 88.400 +*I mux_right_ipin_15\/mux_l2_in_3_:S I *L 0.00357 *C 76.260 85.000 +*N mux_tree_tapbuf_size8_7_sram[1]:6 *C 76.222 85.000 +*N mux_tree_tapbuf_size8_7_sram[1]:7 *C 78.523 88.400 +*N mux_tree_tapbuf_size8_7_sram[1]:8 *C 75.485 88.400 +*N mux_tree_tapbuf_size8_7_sram[1]:9 *C 75.440 88.355 +*N mux_tree_tapbuf_size8_7_sram[1]:10 *C 75.440 85.045 +*N mux_tree_tapbuf_size8_7_sram[1]:11 *C 75.440 85.000 +*N mux_tree_tapbuf_size8_7_sram[1]:12 *C 67.297 85.000 +*N mux_tree_tapbuf_size8_7_sram[1]:13 *C 69.920 85.000 +*N mux_tree_tapbuf_size8_7_sram[1]:14 *C 69.920 84.955 +*N mux_tree_tapbuf_size8_7_sram[1]:15 *C 64.797 77.860 +*N mux_tree_tapbuf_size8_7_sram[1]:16 *C 69.875 77.860 +*N mux_tree_tapbuf_size8_7_sram[1]:17 *C 69.920 77.860 +*N mux_tree_tapbuf_size8_7_sram[1]:18 *C 69.920 75.480 +*N mux_tree_tapbuf_size8_7_sram[1]:19 *C 72.883 75.163 +*N mux_tree_tapbuf_size8_7_sram[1]:20 *C 73.140 75.175 +*N mux_tree_tapbuf_size8_7_sram[1]:21 *C 73.140 75.480 +*N mux_tree_tapbuf_size8_7_sram[1]:22 *C 70.425 75.480 +*N mux_tree_tapbuf_size8_7_sram[1]:23 *C 70.380 75.435 +*N mux_tree_tapbuf_size8_7_sram[1]:24 *C 70.380 71.785 +*N mux_tree_tapbuf_size8_7_sram[1]:25 *C 70.425 71.740 +*N mux_tree_tapbuf_size8_7_sram[1]:26 *C 71.568 71.740 + +*CAP +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_ipin_15\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_15\/mux_l2_in_1_:S 1e-06 +4 mux_right_ipin_15\/mux_l2_in_2_:S 1e-06 +5 mux_right_ipin_15\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_7_sram[1]:6 7.133221e-05 +7 mux_tree_tapbuf_size8_7_sram[1]:7 0.0002207717 +8 mux_tree_tapbuf_size8_7_sram[1]:8 0.0002207717 +9 mux_tree_tapbuf_size8_7_sram[1]:9 0.0001912252 +10 mux_tree_tapbuf_size8_7_sram[1]:10 0.0001912252 +11 mux_tree_tapbuf_size8_7_sram[1]:11 0.0005056102 +12 mux_tree_tapbuf_size8_7_sram[1]:12 0.0001824315 +13 mux_tree_tapbuf_size8_7_sram[1]:13 0.0006183548 +14 mux_tree_tapbuf_size8_7_sram[1]:14 0.0003936358 +15 mux_tree_tapbuf_size8_7_sram[1]:15 0.000323511 +16 mux_tree_tapbuf_size8_7_sram[1]:16 0.000323511 +17 mux_tree_tapbuf_size8_7_sram[1]:17 0.0005858012 +18 mux_tree_tapbuf_size8_7_sram[1]:18 0.0001917163 +19 mux_tree_tapbuf_size8_7_sram[1]:19 1.603702e-05 +20 mux_tree_tapbuf_size8_7_sram[1]:20 4.035216e-05 +21 mux_tree_tapbuf_size8_7_sram[1]:21 0.0002240967 +22 mux_tree_tapbuf_size8_7_sram[1]:22 0.0001997816 +23 mux_tree_tapbuf_size8_7_sram[1]:23 0.0002358082 +24 mux_tree_tapbuf_size8_7_sram[1]:24 0.0002048721 +25 mux_tree_tapbuf_size8_7_sram[1]:25 9.051651e-05 +26 mux_tree_tapbuf_size8_7_sram[1]:26 9.051651e-05 + +*RES +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_7_sram[1]:26 0.152 +1 mux_tree_tapbuf_size8_7_sram[1]:15 mux_right_ipin_15\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_7_sram[1]:16 mux_tree_tapbuf_size8_7_sram[1]:15 0.004533482 +3 mux_tree_tapbuf_size8_7_sram[1]:17 mux_tree_tapbuf_size8_7_sram[1]:16 0.0045 +4 mux_tree_tapbuf_size8_7_sram[1]:17 mux_tree_tapbuf_size8_7_sram[1]:14 0.006334822 +5 mux_tree_tapbuf_size8_7_sram[1]:25 mux_tree_tapbuf_size8_7_sram[1]:24 0.0045 +6 mux_tree_tapbuf_size8_7_sram[1]:24 mux_tree_tapbuf_size8_7_sram[1]:23 0.003258929 +7 mux_tree_tapbuf_size8_7_sram[1]:26 mux_tree_tapbuf_size8_7_sram[1]:25 0.001020089 +8 mux_tree_tapbuf_size8_7_sram[1]:13 mux_tree_tapbuf_size8_7_sram[1]:12 0.002341518 +9 mux_tree_tapbuf_size8_7_sram[1]:13 mux_tree_tapbuf_size8_7_sram[1]:11 0.004928572 +10 mux_tree_tapbuf_size8_7_sram[1]:14 mux_tree_tapbuf_size8_7_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size8_7_sram[1]:6 mux_right_ipin_15\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size8_7_sram[1]:11 mux_tree_tapbuf_size8_7_sram[1]:10 0.0045 +13 mux_tree_tapbuf_size8_7_sram[1]:11 mux_tree_tapbuf_size8_7_sram[1]:6 0.0006986607 +14 mux_tree_tapbuf_size8_7_sram[1]:10 mux_tree_tapbuf_size8_7_sram[1]:9 0.002955357 +15 mux_tree_tapbuf_size8_7_sram[1]:8 mux_tree_tapbuf_size8_7_sram[1]:7 0.002712054 +16 mux_tree_tapbuf_size8_7_sram[1]:9 mux_tree_tapbuf_size8_7_sram[1]:8 0.0045 +17 mux_tree_tapbuf_size8_7_sram[1]:7 mux_right_ipin_15\/mux_l2_in_2_:S 0.152 +18 mux_tree_tapbuf_size8_7_sram[1]:12 mux_right_ipin_15\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size8_7_sram[1]:22 mux_tree_tapbuf_size8_7_sram[1]:21 0.002424107 +20 mux_tree_tapbuf_size8_7_sram[1]:23 mux_tree_tapbuf_size8_7_sram[1]:22 0.0045 +21 mux_tree_tapbuf_size8_7_sram[1]:23 mux_tree_tapbuf_size8_7_sram[1]:18 0.0004107143 +22 mux_tree_tapbuf_size8_7_sram[1]:19 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +23 mux_tree_tapbuf_size8_7_sram[1]:21 mux_tree_tapbuf_size8_7_sram[1]:20 0.0002723215 +24 mux_tree_tapbuf_size8_7_sram[1]:20 mux_tree_tapbuf_size8_7_sram[1]:19 0.0001739865 +25 mux_tree_tapbuf_size8_7_sram[1]:18 mux_tree_tapbuf_size8_7_sram[1]:17 0.002125 + +*END + +*D_NET optlc_net_130 0.0008664742 //LENGTH 7.700 LUMPCC 7.312997e-05 DR + +*CONN +*I optlc_122:HI O *L 0 *C 16.100 47.600 +*I mux_right_ipin_10\/mux_l2_in_3_:A0 I *L 0.001631 *C 14.090 42.840 +*N optlc_net_130:2 *C 14.128 42.840 +*N optlc_net_130:3 *C 15.135 42.840 +*N optlc_net_130:4 *C 15.180 42.885 +*N optlc_net_130:5 *C 15.180 47.555 +*N optlc_net_130:6 *C 15.225 47.600 +*N optlc_net_130:7 *C 16.062 47.600 + +*CAP +0 optlc_122:HI 1e-06 +1 mux_right_ipin_10\/mux_l2_in_3_:A0 1e-06 +2 optlc_net_130:2 8.611136e-05 +3 optlc_net_130:3 8.611136e-05 +4 optlc_net_130:4 0.0002317765 +5 optlc_net_130:5 0.0002317765 +6 optlc_net_130:6 7.778431e-05 +7 optlc_net_130:7 7.778431e-05 +8 optlc_net_130:5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 3.656498e-05 +9 optlc_net_130:4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 3.656498e-05 + +*RES +0 optlc_122:HI optlc_net_130:7 0.152 +1 optlc_net_130:7 optlc_net_130:6 0.0007477679 +2 optlc_net_130:6 optlc_net_130:5 0.0045 +3 optlc_net_130:5 optlc_net_130:4 0.004169643 +4 optlc_net_130:3 optlc_net_130:2 0.0008995536 +5 optlc_net_130:4 optlc_net_130:3 0.0045 +6 optlc_net_130:2 mux_right_ipin_10\/mux_l2_in_3_:A0 0.152 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009837644 //LENGTH 8.985 LUMPCC 0 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_2_:X O *L 0 *C 68.365 58.820 +*I mux_left_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 73.700 61.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 73.663 61.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 69.965 61.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 69.920 61.495 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 69.920 58.865 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 69.875 58.820 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 68.403 58.820 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002366018 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002366018 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000150185 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000150185 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001040954 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001040954 + +*RES +0 mux_left_ipin_0\/mux_l2_in_2_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003301339 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001580103 //LENGTH 11.610 LUMPCC 0.0002351435 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_1_:X O *L 0 *C 37.895 77.520 +*I mux_right_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 32.490 82.280 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 32.490 82.280 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 32.660 82.280 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 32.660 82.235 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 32.660 80.297 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 32.668 80.240 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 36.333 80.240 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 36.340 80.183 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 36.340 77.565 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 36.385 77.520 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 37.858 77.520 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.95664e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.409064e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 8.849504e-05 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.849504e-05 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002850871 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002850871 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001399869 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001399869 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001060824 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0001060824 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size10_1_sram[1]:13 2.596699e-05 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size10_1_sram[1]:6 5.180895e-06 +14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size10_1_sram[1]:16 2.298687e-05 +15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size10_1_sram[1]:14 2.596699e-05 +16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size10_1_sram[1]:15 5.180895e-06 +17 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size10_1_sram[1]:17 2.298687e-05 +18 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.343699e-05 +19 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.343699e-05 + +*RES +0 mux_right_ipin_0\/mux_l2_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001729911 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005741833 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.002337054 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.001314732 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003300518 //LENGTH 2.475 LUMPCC 8.88821e-05 DR + +*CONN +*I mux_right_ipin_1\/mux_l2_in_1_:X O *L 0 *C 52.615 93.500 +*I mux_right_ipin_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 50.430 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 50.468 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 52.578 93.500 + +*CAP +0 mux_right_ipin_1\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_1\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001195848 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001195848 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chany_bottom_in[12]:15 3.388971e-05 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chany_bottom_in[12]:16 1.055134e-05 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chany_bottom_in[12]:14 3.388971e-05 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chany_bottom_in[12]:17 1.055134e-05 + +*RES +0 mux_right_ipin_1\/mux_l2_in_1_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_1\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003901193 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l2_in_0_:X O *L 0 *C 18.115 83.300 +*I mux_right_ipin_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 15.545 83.300 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 15.583 83.300 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 18.078 83.300 + +*CAP +0 mux_right_ipin_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001940597 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001940597 + +*RES +0 mux_right_ipin_4\/mux_l2_in_0_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002227679 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_4\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0004086331 //LENGTH 3.470 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l3_in_0_:X O *L 0 *C 13.975 83.640 +*I mux_right_ipin_4\/mux_l4_in_0_:A1 I *L 0.005458 *C 13.340 85.850 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 13.340 85.805 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 13.340 83.685 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 13.385 83.640 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 13.938 83.640 + +*CAP +0 mux_right_ipin_4\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_4\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001363845 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001363845 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.693207e-05 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.693207e-05 + +*RES +0 mux_right_ipin_4\/mux_l3_in_0_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004933036 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001892857 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_4\/mux_l4_in_0_:A1 0.0045 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001131477 //LENGTH 7.560 LUMPCC 0.0002344946 DR + +*CONN +*I mux_right_ipin_5\/mux_l3_in_0_:X O *L 0 *C 58.135 61.880 +*I mux_right_ipin_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 52.900 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 52.900 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 52.900 63.535 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 52.900 61.925 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 52.945 61.880 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 58.098 61.880 + +*CAP +0 mux_right_ipin_5\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_5\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.061089e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001252027 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001252027 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003069831 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0003069831 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001172473 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001172473 + +*RES +0 mux_right_ipin_5\/mux_l3_in_0_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.004600447 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0014375 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_5\/mux_l4_in_0_:A1 0.152 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004797991 //LENGTH 3.330 LUMPCC 8.301218e-05 DR + +*CONN +*I mux_right_ipin_8\/mux_l2_in_0_:X O *L 0 *C 22.715 37.060 +*I mux_right_ipin_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 22.445 39.780 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.445 39.780 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.540 39.735 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 22.540 37.105 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 22.540 37.060 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 22.715 37.060 + +*CAP +0 mux_right_ipin_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_8\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.915317e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001228058 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001228058 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.051402e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.950803e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:7 6.82666e-06 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:9 3.467943e-05 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_5_sram[2]:9 6.82666e-06 +10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_5_sram[2]:10 3.467943e-05 + +*RES +0 mux_right_ipin_8\/mux_l2_in_0_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_8\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001637305 //LENGTH 14.245 LUMPCC 0.0004450837 DR + +*CONN +*I mux_right_ipin_9\/mux_l1_in_0_:X O *L 0 *C 57.325 22.780 +*I mux_right_ipin_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 65.880 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 65.843 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.525 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.480 18.065 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.480 22.735 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.435 22.780 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 57.363 22.780 + +*CAP +0 mux_right_ipin_9\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_9\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001091217 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001091217 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001985282 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001985282 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002874607 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002874607 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[18]:25 3.717111e-06 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[18]:27 2.074444e-06 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[18]:4 3.717111e-06 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[18]:26 2.074444e-06 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[18]:24 6.488308e-05 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[18]:23 6.488308e-05 +14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_6_sram[0]:16 7.315329e-05 +15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_6_sram[0]:17 7.315329e-05 +16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.871394e-05 +17 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.871394e-05 + +*RES +0 mux_right_ipin_9\/mux_l1_in_0_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_9\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002069197 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.005421875 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008226904 //LENGTH 6.605 LUMPCC 0.0001337724 DR + +*CONN +*I mux_right_ipin_12\/mux_l1_in_2_:X O *L 0 *C 18.685 11.560 +*I mux_right_ipin_12\/mux_l2_in_1_:A1 I *L 0.00198 *C 17.580 9.180 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 17.617 9.180 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 19.735 9.180 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 19.780 9.225 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 19.780 11.515 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 19.735 11.560 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 18.723 11.560 + +*CAP +0 mux_right_ipin_12\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_12\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001138716 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001138716 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001368582 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001368582 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.272924e-05 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.272924e-05 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_7_sram[1]:11 6.688622e-05 +9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_7_sram[1]:12 6.688622e-05 + +*RES +0 mux_right_ipin_12\/mux_l1_in_2_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_12\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001890625 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001981782 //LENGTH 17.000 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_12\/mux_l4_in_0_:X O *L 0 *C 16.735 20.740 +*I mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 8.070 28.385 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 8.107 28.280 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 16.055 28.220 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 16.100 28.175 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 16.100 20.785 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 16.145 20.740 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 16.698 20.740 + +*CAP +0 mux_right_ipin_12\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004765359 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0004765359 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0004604308 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0004604308 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.29243e-05 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.29243e-05 + +*RES +0 mux_right_ipin_12\/mux_l4_in_0_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0004933036 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.006598215 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.007095983 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008207343 //LENGTH 7.235 LUMPCC 8.998576e-05 DR + +*CONN +*I mux_right_ipin_13\/mux_l3_in_1_:X O *L 0 *C 48.475 20.400 +*I mux_right_ipin_13\/mux_l4_in_0_:A0 I *L 0.001631 *C 43.070 21.080 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 43.043 21.058 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 42.780 21.045 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 42.780 20.400 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 48.438 20.400 + +*CAP +0 mux_right_ipin_13\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_13\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.460968e-05 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.858156e-05 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0003297646 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002857927 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.312258e-07 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.436166e-05 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.436166e-05 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.312258e-07 + +*RES +0 mux_right_ipin_13\/mux_l3_in_1_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_13\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.00505134 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0005758929 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001773649 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0009257069 //LENGTH 7.455 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_2\/mux_l4_in_0_:X O *L 0 *C 9.835 94.520 +*I mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.275 96.725 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.312 96.620 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 5.935 96.560 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 5.980 96.515 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 5.980 94.565 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 6.025 94.520 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 9.798 94.520 + +*CAP +0 mux_right_ipin_2\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.000508e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.000508e-05 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001309506 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001309506 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002708978 +7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002708978 + +*RES +0 mux_right_ipin_2\/mux_l4_in_0_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0005558036 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001741072 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.003368304 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004424363 //LENGTH 3.125 LUMPCC 0.0001724 DR + +*CONN +*I mux_right_ipin_6\/mux_l2_in_0_:X O *L 0 *C 31.455 66.980 +*I mux_right_ipin_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 28.620 66.980 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 28.658 66.980 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 31.418 66.980 + +*CAP +0 mux_right_ipin_6\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_6\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001340181 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001340181 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:9 8.620002e-05 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:4 8.620002e-05 + +*RES +0 mux_right_ipin_6\/mux_l2_in_0_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002464286 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_6\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0] 0.004999309 //LENGTH 36.450 LUMPCC 0.0007302218 DR + +*CONN +*I mux_right_ipin_6\/mux_l4_in_0_:X O *L 0 *C 29.155 72.080 +*I mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.215 74.965 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.215 74.965 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 1.885 75.140 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 1.840 75.095 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 1.840 72.138 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 1.848 72.080 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 29.893 72.080 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 29.900 72.080 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 29.855 72.080 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 29.193 72.080 + +*CAP +0 mux_right_ipin_6\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0002653248 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002302701 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002483183 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002483183 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001531898 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.001531898 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 3.937422e-05 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 8.584342e-05 +10 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 8.584342e-05 +11 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_top_in[5]:19 0.0002331776 +12 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_top_in[5]:15 0.0002331776 +13 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:75 2.215922e-05 +14 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:85 0.0001097741 +15 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:76 2.215922e-05 +16 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:86 0.0001097741 + +*RES +0 mux_right_ipin_6\/mux_l4_in_0_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0005915179 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0045 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.004393717 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002640625 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002973214 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004169501 //LENGTH 2.935 LUMPCC 0.0001562128 DR + +*CONN +*I mux_right_ipin_10\/mux_l2_in_3_:X O *L 0 *C 12.135 42.500 +*I mux_right_ipin_10\/mux_l3_in_1_:A0 I *L 0.001631 *C 9.490 42.500 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 9.527 42.500 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 12.098 42.500 + +*CAP +0 mux_right_ipin_10\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_10\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001293686 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001293686 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chany_top_in[15]:14 3.204104e-05 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chany_top_in[15]:13 3.204104e-05 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.606538e-05 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.606538e-05 + +*RES +0 mux_right_ipin_10\/mux_l2_in_3_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_10\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002294643 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004400873 //LENGTH 2.935 LUMPCC 0.0002208465 DR + +*CONN +*I mux_right_ipin_11\/mux_l2_in_3_:X O *L 0 *C 24.555 53.380 +*I mux_right_ipin_11\/mux_l3_in_1_:A0 I *L 0.001631 *C 21.910 53.380 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 21.948 53.380 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 24.518 53.380 + +*CAP +0 mux_right_ipin_11\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_11\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001086204 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001086204 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_5_sram[1]:16 0.0001104232 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_5_sram[1]:17 0.0001104232 + +*RES +0 mux_right_ipin_11\/mux_l2_in_3_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_11\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002294643 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005532873 //LENGTH 4.435 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_14\/mux_l2_in_3_:X O *L 0 *C 33.405 49.980 +*I mux_right_ipin_14\/mux_l3_in_1_:A0 I *L 0.001631 *C 37.550 49.980 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 37.513 49.980 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 33.443 49.980 + +*CAP +0 mux_right_ipin_14\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_14\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002756437 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002756437 + +*RES +0 mux_right_ipin_14\/mux_l2_in_3_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003633929 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_14\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001292613 //LENGTH 11.465 LUMPCC 0.0001562048 DR + +*CONN +*I mux_right_ipin_15\/mux_l1_in_0_:X O *L 0 *C 59.625 71.740 +*I mux_right_ipin_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.040 77.860 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.002 77.860 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 61.225 77.860 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.180 77.815 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 61.180 71.785 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.135 71.740 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 59.663 71.740 + +*CAP +0 mux_right_ipin_15\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_15\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001965952 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001965952 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000303143 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000303143 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.746587e-05 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.746587e-05 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_7_sram[0]:5 9.01447e-06 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size8_7_sram[0]:4 6.908794e-05 +10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_7_sram[0]:12 9.01447e-06 +11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size8_7_sram[0]:3 6.908794e-05 + +*RES +0 mux_right_ipin_15\/mux_l1_in_0_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_15\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002479911 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005383929 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET ropt_net_147 0.002174089 //LENGTH 16.655 LUMPCC 0.0003275597 DR + +*CONN +*I FTB_6__5:X O *L 0 *C 48.760 86.360 +*I ropt_mt_inst_746:A I *L 0.001766 *C 44.160 96.560 +*N ropt_net_147:2 *C 44.160 96.560 +*N ropt_net_147:3 *C 44.160 96.515 +*N ropt_net_147:4 *C 44.160 95.925 +*N ropt_net_147:5 *C 44.205 95.880 +*N ropt_net_147:6 *C 47.335 95.880 +*N ropt_net_147:7 *C 47.380 95.880 +*N ropt_net_147:8 *C 47.380 86.405 +*N ropt_net_147:9 *C 47.425 86.360 +*N ropt_net_147:10 *C 48.723 86.360 + +*CAP +0 FTB_6__5:X 1e-06 +1 ropt_mt_inst_746:A 1e-06 +2 ropt_net_147:2 3.76298e-05 +3 ropt_net_147:3 7.264642e-05 +4 ropt_net_147:4 7.264642e-05 +5 ropt_net_147:5 0.0001871204 +6 ropt_net_147:6 0.0001871204 +7 ropt_net_147:7 0.0005517976 +8 ropt_net_147:8 0.0005185388 +9 ropt_net_147:9 0.0001085146 +10 ropt_net_147:10 0.0001085146 +11 ropt_net_147:8 chany_bottom_in[11]:12 1.450018e-05 +12 ropt_net_147:8 chany_bottom_in[11]:16 7.353593e-06 +13 ropt_net_147:6 chany_bottom_in[11]:13 7.640427e-05 +14 ropt_net_147:7 chany_bottom_in[11]:11 1.450018e-05 +15 ropt_net_147:7 chany_bottom_in[11]:15 7.353593e-06 +16 ropt_net_147:5 chany_bottom_in[11]:14 7.640427e-05 +17 ropt_net_147:8 ropt_net_143:10 6.552182e-05 +18 ropt_net_147:7 ropt_net_143:9 6.552182e-05 + +*RES +0 FTB_6__5:X ropt_net_147:10 0.152 +1 ropt_net_147:10 ropt_net_147:9 0.001158482 +2 ropt_net_147:9 ropt_net_147:8 0.0045 +3 ropt_net_147:8 ropt_net_147:7 0.008459822 +4 ropt_net_147:6 ropt_net_147:5 0.002794643 +5 ropt_net_147:7 ropt_net_147:6 0.0045 +6 ropt_net_147:5 ropt_net_147:4 0.0045 +7 ropt_net_147:4 ropt_net_147:3 0.0005267857 +8 ropt_net_147:2 ropt_mt_inst_746:A 0.152 +9 ropt_net_147:3 ropt_net_147:2 0.0045 + +*END + +*D_NET chany_bottom_out[1] 0.002039762 //LENGTH 15.100 LUMPCC 0 DR + +*CONN +*I FTB_22__21:X O *L 0 *C 19.780 6.120 +*P chany_bottom_out[1] O *L 0.7423 *C 28.980 1.325 +*N chany_bottom_out[1]:2 *C 28.980 4.715 +*N chany_bottom_out[1]:3 *C 28.935 4.760 +*N chany_bottom_out[1]:4 *C 22.125 4.760 +*N chany_bottom_out[1]:5 *C 22.080 4.805 +*N chany_bottom_out[1]:6 *C 22.080 6.075 +*N chany_bottom_out[1]:7 *C 22.035 6.120 +*N chany_bottom_out[1]:8 *C 19.818 6.120 + +*CAP +0 FTB_22__21:X 1e-06 +1 chany_bottom_out[1] 0.0002051793 +2 chany_bottom_out[1]:2 0.0002051793 +3 chany_bottom_out[1]:3 0.0005260099 +4 chany_bottom_out[1]:4 0.0005260099 +5 chany_bottom_out[1]:5 0.0001102649 +6 chany_bottom_out[1]:6 0.0001102649 +7 chany_bottom_out[1]:7 0.0001779271 +8 chany_bottom_out[1]:8 0.0001779271 + +*RES +0 FTB_22__21:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.001979911 +2 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +3 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.001133929 +4 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.006080357 +5 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0045 +6 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +7 chany_bottom_out[1]:2 chany_bottom_out[1] 0.003026786 + +*END + +*D_NET ropt_net_154 0.001657187 //LENGTH 10.730 LUMPCC 0.0003630307 DR + +*CONN +*I FTB_30__29:X O *L 0 *C 33.580 11.900 +*I ropt_mt_inst_753:A I *L 0.001766 *C 42.780 12.240 +*N ropt_net_154:2 *C 42.780 12.240 +*N ropt_net_154:3 *C 42.780 11.560 +*N ropt_net_154:4 *C 33.580 11.560 +*N ropt_net_154:5 *C 33.580 11.900 + +*CAP +0 FTB_30__29:X 1e-06 +1 ropt_mt_inst_753:A 1e-06 +2 ropt_net_154:2 8.69354e-05 +3 ropt_net_154:3 0.0005794703 +4 ropt_net_154:4 0.0005590037 +5 ropt_net_154:5 6.674718e-05 +6 ropt_net_154:4 chany_bottom_in[14]:21 7.108542e-05 +7 ropt_net_154:3 chany_bottom_in[14]:22 7.108542e-05 +8 ropt_net_154:4 ropt_net_156:9 0.0001104299 +9 ropt_net_154:3 ropt_net_156:8 0.0001104299 + +*RES +0 FTB_30__29:X ropt_net_154:5 0.152 +1 ropt_net_154:2 ropt_mt_inst_753:A 0.152 +2 ropt_net_154:5 ropt_net_154:4 0.0003035715 +3 ropt_net_154:4 ropt_net_154:3 0.008214287 +4 ropt_net_154:3 ropt_net_154:2 0.000607143 + +*END + +*D_NET ropt_net_162 0.0006933014 //LENGTH 6.305 LUMPCC 0 DR + +*CONN +*I FTB_39__38:X O *L 0 *C 62.100 8.840 +*I ropt_mt_inst_762:A I *L 0.001766 *C 63.020 4.080 +*N ropt_net_162:2 *C 63.020 4.080 +*N ropt_net_162:3 *C 63.020 4.125 +*N ropt_net_162:4 *C 63.020 8.795 +*N ropt_net_162:5 *C 62.975 8.840 +*N ropt_net_162:6 *C 62.138 8.840 + +*CAP +0 FTB_39__38:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_162:2 3.864347e-05 +3 ropt_net_162:3 0.0002493894 +4 ropt_net_162:4 0.0002493894 +5 ropt_net_162:5 7.693961e-05 +6 ropt_net_162:6 7.693961e-05 + +*RES +0 FTB_39__38:X ropt_net_162:6 0.152 +1 ropt_net_162:2 ropt_mt_inst_762:A 0.152 +2 ropt_net_162:3 ropt_net_162:2 0.0045 +3 ropt_net_162:5 ropt_net_162:4 0.0045 +4 ropt_net_162:4 ropt_net_162:3 0.004169643 +5 ropt_net_162:6 ropt_net_162:5 0.0007477679 + +*END + +*D_NET ropt_net_177 0.002258681 //LENGTH 14.080 LUMPCC 0.001030711 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 51.255 8.840 +*I ropt_mt_inst_786:A I *L 0.001766 *C 44.620 6.800 +*N ropt_net_177:2 *C 44.620 6.800 +*N ropt_net_177:3 *C 44.620 6.755 +*N ropt_net_177:4 *C 44.620 4.817 +*N ropt_net_177:5 *C 44.628 4.760 +*N ropt_net_177:6 *C 48.753 4.760 +*N ropt_net_177:7 *C 48.760 4.817 +*N ropt_net_177:8 *C 48.760 8.795 +*N ropt_net_177:9 *C 48.805 8.840 +*N ropt_net_177:10 *C 51.218 8.840 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_177:2 3.912486e-05 +3 ropt_net_177:3 8.954206e-05 +4 ropt_net_177:4 8.954206e-05 +5 ropt_net_177:5 0.0001966497 +6 ropt_net_177:6 0.0001966497 +7 ropt_net_177:7 0.0001326547 +8 ropt_net_177:8 0.0001326547 +9 ropt_net_177:9 0.0001745763 +10 ropt_net_177:10 0.0001745763 +11 ropt_net_177:7 chany_bottom_in[0] 9.360015e-05 +12 ropt_net_177:8 chany_bottom_in[0]:56 9.360015e-05 +13 ropt_net_177:7 chany_bottom_in[2] 0.0001057096 +14 ropt_net_177:7 chany_bottom_in[2]:61 1.277201e-07 +15 ropt_net_177:9 chany_bottom_in[2]:62 1.01128e-05 +16 ropt_net_177:8 chany_bottom_in[2]:60 1.277201e-07 +17 ropt_net_177:8 chany_bottom_in[2]:62 0.0001057096 +18 ropt_net_177:10 chany_bottom_in[2]:61 1.01128e-05 +19 ropt_net_177:5 chany_top_in[17]:14 0.0002448006 +20 ropt_net_177:6 chany_top_in[17]:13 0.0002448006 +21 ropt_net_177:3 chany_bottom_out[8]:4 6.100453e-05 +22 ropt_net_177:4 chany_bottom_out[8]:3 6.100453e-05 + +*RES +0 ropt_mt_inst_755:X ropt_net_177:10 0.152 +1 ropt_net_177:2 ropt_mt_inst_786:A 0.152 +2 ropt_net_177:3 ropt_net_177:2 0.0045 +3 ropt_net_177:4 ropt_net_177:3 0.001729911 +4 ropt_net_177:5 ropt_net_177:4 0.00341 +5 ropt_net_177:7 ropt_net_177:6 0.00341 +6 ropt_net_177:6 ropt_net_177:5 0.00064625 +7 ropt_net_177:9 ropt_net_177:8 0.0045 +8 ropt_net_177:8 ropt_net_177:7 0.003551339 +9 ropt_net_177:10 ropt_net_177:9 0.002154018 + +*END + +*D_NET ccff_tail[0] 0.0004845736 //LENGTH 4.480 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 81.580 101.320 +*P ccff_tail[0] O *L 0.7423 *C 83.343 99.280 +*N ccff_tail[0]:2 *C 83.260 99.280 +*N ccff_tail[0]:3 *C 83.260 99.280 +*N ccff_tail[0]:4 *C 81.880 99.280 +*N ccff_tail[0]:5 *C 81.880 101.275 +*N ccff_tail[0]:6 *C 81.880 101.320 +*N ccff_tail[0]:7 *C 81.580 101.320 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 ccff_tail[0] 2.581168e-05 +2 ccff_tail[0]:2 2.581168e-05 +3 ccff_tail[0]:3 8.720912e-05 +4 ccff_tail[0]:4 0.0001551585 +5 ccff_tail[0]:5 9.3738e-05 +6 ccff_tail[0]:6 4.729489e-05 +7 ccff_tail[0]:7 4.854968e-05 + +*RES +0 ropt_mt_inst_758:X ccff_tail[0]:7 0.152 +1 ccff_tail[0]:7 ccff_tail[0]:6 0.0001630435 +2 ccff_tail[0]:6 ccff_tail[0]:5 0.0045 +3 ccff_tail[0]:5 ccff_tail[0]:4 0.00178125 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 +6 ccff_tail[0]:4 ccff_tail[0]:3 0.001232143 + +*END + +*D_NET ropt_net_186 0.0009070546 //LENGTH 5.595 LUMPCC 0.0004333131 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 57.245 96.900 +*I ropt_mt_inst_804:A I *L 0.001767 *C 62.100 96.560 +*N ropt_net_186:2 *C 62.100 96.560 +*N ropt_net_186:3 *C 62.100 96.900 +*N ropt_net_186:4 *C 57.283 96.900 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 ropt_mt_inst_804:A 1e-06 +2 ropt_net_186:2 6.792946e-05 +3 ropt_net_186:3 0.0002181634 +4 ropt_net_186:4 0.0001856486 +5 ropt_net_186:4 chany_top_in[6]:5 9.555235e-05 +6 ropt_net_186:3 chany_top_in[6]:4 9.555235e-05 +7 ropt_net_186:2 mux_tree_tapbuf_size10_2_sram[1]:37 1.22012e-07 +8 ropt_net_186:4 mux_tree_tapbuf_size10_2_sram[1]:35 9.749201e-05 +9 ropt_net_186:4 mux_tree_tapbuf_size10_2_sram[1]:37 2.349019e-05 +10 ropt_net_186:3 mux_tree_tapbuf_size10_2_sram[1]:36 9.761402e-05 +11 ropt_net_186:3 mux_tree_tapbuf_size10_2_sram[1]:38 2.349019e-05 + +*RES +0 ropt_mt_inst_770:X ropt_net_186:4 0.152 +1 ropt_net_186:2 ropt_mt_inst_804:A 0.152 +2 ropt_net_186:4 ropt_net_186:3 0.004301339 +3 ropt_net_186:3 ropt_net_186:2 0.0003035715 + +*END + +*D_NET chany_top_out[0] 0.003273812 //LENGTH 22.395 LUMPCC 0.0006355448 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 63.020 95.880 +*P chany_top_out[0] O *L 0.7423 *C 53.820 107.780 +*N chany_top_out[0]:2 *C 54.280 107.780 +*N chany_top_out[0]:3 *C 54.280 98.645 +*N chany_top_out[0]:4 *C 54.325 98.600 +*N chany_top_out[0]:5 *C 59.755 98.600 +*N chany_top_out[0]:6 *C 59.800 98.555 +*N chany_top_out[0]:7 *C 59.800 95.938 +*N chany_top_out[0]:8 *C 59.808 95.880 +*N chany_top_out[0]:9 *C 63.013 95.880 +*N chany_top_out[0]:10 *C 63.020 95.880 +*N chany_top_out[0]:11 *C 63.020 95.880 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chany_top_out[0] 2.552453e-05 +2 chany_top_out[0]:2 0.0006302692 +3 chany_top_out[0]:3 0.0006047447 +4 chany_top_out[0]:4 0.0002992099 +5 chany_top_out[0]:5 0.0002992099 +6 chany_top_out[0]:6 0.0001954451 +7 chany_top_out[0]:7 0.0001954451 +8 chany_top_out[0]:8 0.0001592991 +9 chany_top_out[0]:9 0.0001592991 +10 chany_top_out[0]:10 3.549261e-05 +11 chany_top_out[0]:11 3.332788e-05 +12 chany_top_out[0]:9 prog_clk[0]:364 0.0001897589 +13 chany_top_out[0]:8 prog_clk[0]:371 0.0001897589 +14 chany_top_out[0]:5 prog_clk[0]:367 0.0001280135 +15 chany_top_out[0]:4 prog_clk[0]:368 0.0001280135 + +*RES +0 ropt_mt_inst_804:X chany_top_out[0]:11 0.152 +1 chany_top_out[0]:11 chany_top_out[0]:10 0.0045 +2 chany_top_out[0]:10 chany_top_out[0]:9 0.00341 +3 chany_top_out[0]:9 chany_top_out[0]:8 0.0005021166 +4 chany_top_out[0]:7 chany_top_out[0]:6 0.002337054 +5 chany_top_out[0]:8 chany_top_out[0]:7 0.00341 +6 chany_top_out[0]:5 chany_top_out[0]:4 0.004848214 +7 chany_top_out[0]:6 chany_top_out[0]:5 0.0045 +8 chany_top_out[0]:4 chany_top_out[0]:3 0.0045 +9 chany_top_out[0]:3 chany_top_out[0]:2 0.008156249 +10 chany_top_out[0]:2 chany_top_out[0] 0.0004107143 + +*END + +*D_NET chany_bottom_in[3] 0.02691195 //LENGTH 198.640 LUMPCC 0.004544528 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 42.780 1.290 +*I mux_right_ipin_12\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.880 14.620 +*I mux_right_ipin_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 19.150 37.060 +*I mux_right_ipin_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 32.200 39.780 +*I mux_right_ipin_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 33.410 66.300 +*I mux_right_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 28.620 79.900 +*I mux_right_ipin_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 22.445 85.340 +*I mux_right_ipin_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 22.370 91.460 +*I FTB_4__3:A I *L 0.001767 *C 64.860 104.720 +*I mux_right_ipin_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 36.975 42.500 +*N chany_bottom_in[3]:10 *C 36.938 42.500 +*N chany_bottom_in[3]:11 *C 64.823 104.720 +*N chany_bottom_in[3]:12 *C 61.225 104.720 +*N chany_bottom_in[3]:13 *C 61.180 104.675 +*N chany_bottom_in[3]:14 *C 61.180 97.978 +*N chany_bottom_in[3]:15 *C 61.172 97.920 +*N chany_bottom_in[3]:16 *C 58.900 97.920 +*N chany_bottom_in[3]:17 *C 58.880 97.913 +*N chany_bottom_in[3]:18 *C 58.880 93.168 +*N chany_bottom_in[3]:19 *C 58.860 93.160 +*N chany_bottom_in[3]:20 *C 22.547 93.160 +*N chany_bottom_in[3]:21 *C 22.540 93.103 +*N chany_bottom_in[3]:22 *C 22.370 91.460 +*N chany_bottom_in[3]:23 *C 22.540 91.460 +*N chany_bottom_in[3]:24 *C 22.540 91.460 +*N chany_bottom_in[3]:25 *C 22.540 85.725 +*N chany_bottom_in[3]:26 *C 22.540 85.680 +*N chany_bottom_in[3]:27 *C 22.518 85.340 +*N chany_bottom_in[3]:28 *C 28.475 85.340 +*N chany_bottom_in[3]:29 *C 28.520 85.295 +*N chany_bottom_in[3]:30 *C 28.520 79.900 +*N chany_bottom_in[3]:31 *C 28.520 79.900 +*N chany_bottom_in[3]:32 *C 28.980 79.900 +*N chany_bottom_in[3]:33 *C 28.980 69.065 +*N chany_bottom_in[3]:34 *C 29.025 69.020 +*N chany_bottom_in[3]:35 *C 34.455 69.020 +*N chany_bottom_in[3]:36 *C 34.500 68.975 +*N chany_bottom_in[3]:37 *C 34.500 66.345 +*N chany_bottom_in[3]:38 *C 34.455 66.300 +*N chany_bottom_in[3]:39 *C 33.558 66.300 +*N chany_bottom_in[3]:40 *C 33.580 65.960 +*N chany_bottom_in[3]:41 *C 33.580 65.915 +*N chany_bottom_in[3]:42 *C 33.580 42.545 +*N chany_bottom_in[3]:43 *C 33.625 42.500 +*N chany_bottom_in[3]:44 *C 35.880 42.500 +*N chany_bottom_in[3]:45 *C 35.880 42.455 +*N chany_bottom_in[3]:46 *C 32.238 39.780 +*N chany_bottom_in[3]:47 *C 35.835 39.780 +*N chany_bottom_in[3]:48 *C 35.880 39.780 +*N chany_bottom_in[3]:49 *C 19.150 37.060 +*N chany_bottom_in[3]:50 *C 19.320 37.060 +*N chany_bottom_in[3]:51 *C 19.320 37.015 +*N chany_bottom_in[3]:52 *C 19.320 35.418 +*N chany_bottom_in[3]:53 *C 19.328 35.360 +*N chany_bottom_in[3]:54 *C 35.873 35.360 +*N chany_bottom_in[3]:55 *C 35.880 35.360 +*N chany_bottom_in[3]:56 *C 35.880 14.620 +*N chany_bottom_in[3]:57 *C 35.880 14.620 +*N chany_bottom_in[3]:58 *C 35.880 12.965 +*N chany_bottom_in[3]:59 *C 35.925 12.920 +*N chany_bottom_in[3]:60 *C 42.735 12.920 +*N chany_bottom_in[3]:61 *C 42.780 12.875 + +*CAP +0 chany_bottom_in[3] 0.0007395276 +1 mux_right_ipin_12\/mux_l1_in_1_:A1 1e-06 +2 mux_right_ipin_10\/mux_l2_in_0_:A0 1e-06 +3 mux_right_ipin_8\/mux_l1_in_1_:A1 1e-06 +4 mux_right_ipin_6\/mux_l2_in_0_:A0 1e-06 +5 mux_right_ipin_0\/mux_l1_in_1_:A1 1e-06 +6 mux_right_ipin_4\/mux_l1_in_1_:A1 1e-06 +7 mux_right_ipin_2\/mux_l2_in_0_:A0 1e-06 +8 FTB_4__3:A 1e-06 +9 mux_right_ipin_14\/mux_l2_in_0_:A0 1e-06 +10 chany_bottom_in[3]:10 6.840615e-05 +11 chany_bottom_in[3]:11 0.0003408741 +12 chany_bottom_in[3]:12 0.0003408741 +13 chany_bottom_in[3]:13 0.0004474908 +14 chany_bottom_in[3]:14 0.0004474908 +15 chany_bottom_in[3]:15 0.0001557171 +16 chany_bottom_in[3]:16 0.0001557171 +17 chany_bottom_in[3]:17 0.0003452953 +18 chany_bottom_in[3]:18 0.0003452953 +19 chany_bottom_in[3]:19 0.002490705 +20 chany_bottom_in[3]:20 0.002490705 +21 chany_bottom_in[3]:21 6.905631e-05 +22 chany_bottom_in[3]:22 5.357929e-05 +23 chany_bottom_in[3]:23 5.300005e-05 +24 chany_bottom_in[3]:24 0.0004057144 +25 chany_bottom_in[3]:25 0.0003047249 +26 chany_bottom_in[3]:26 6.674137e-05 +27 chany_bottom_in[3]:27 0.0004706128 +28 chany_bottom_in[3]:28 0.0004366663 +29 chany_bottom_in[3]:29 0.0002516916 +30 chany_bottom_in[3]:30 3.593977e-05 +31 chany_bottom_in[3]:31 0.0002853188 +32 chany_bottom_in[3]:32 0.0003743733 +33 chany_bottom_in[3]:33 0.0003407461 +34 chany_bottom_in[3]:34 0.0003443908 +35 chany_bottom_in[3]:35 0.0003443908 +36 chany_bottom_in[3]:36 0.00018017 +37 chany_bottom_in[3]:37 0.00018017 +38 chany_bottom_in[3]:38 0.0001103593 +39 chany_bottom_in[3]:39 0.000145198 +40 chany_bottom_in[3]:40 6.852455e-05 +41 chany_bottom_in[3]:41 0.001069006 +42 chany_bottom_in[3]:42 0.001069006 +43 chany_bottom_in[3]:43 0.0001278438 +44 chany_bottom_in[3]:44 0.0002317075 +45 chany_bottom_in[3]:45 0.000138978 +46 chany_bottom_in[3]:46 0.000237084 +47 chany_bottom_in[3]:47 0.000237084 +48 chany_bottom_in[3]:48 0.0003088358 +49 chany_bottom_in[3]:49 5.084195e-05 +50 chany_bottom_in[3]:50 5.358183e-05 +51 chany_bottom_in[3]:51 8.636326e-05 +52 chany_bottom_in[3]:52 8.636326e-05 +53 chany_bottom_in[3]:53 0.0009740571 +54 chany_bottom_in[3]:54 0.0009740571 +55 chany_bottom_in[3]:55 0.0009516879 +56 chany_bottom_in[3]:56 3.663885e-05 +57 chany_bottom_in[3]:57 0.0008964475 +58 chany_bottom_in[3]:58 8.838637e-05 +59 chany_bottom_in[3]:59 0.0005557322 +60 chany_bottom_in[3]:60 0.0005557322 +61 chany_bottom_in[3]:61 0.0007395276 +62 chany_bottom_in[3]:33 chany_bottom_in[17]:13 0.0002822949 +63 chany_bottom_in[3]:29 chany_bottom_in[17]:12 2.545535e-06 +64 chany_bottom_in[3]:31 chany_bottom_in[17]:13 2.545535e-06 +65 chany_bottom_in[3]:32 chany_bottom_in[17]:12 0.0002822949 +66 chany_bottom_in[3]:47 chany_top_in[3]:25 3.838295e-06 +67 chany_bottom_in[3]:47 chany_top_in[3]:23 1.560695e-05 +68 chany_bottom_in[3]:48 chany_top_in[3]:22 4.326098e-05 +69 chany_bottom_in[3]:46 chany_top_in[3]:25 1.560695e-05 +70 chany_bottom_in[3]:46 chany_top_in[3]:24 3.838295e-06 +71 chany_bottom_in[3]:57 chany_top_in[3]:21 0.0002646662 +72 chany_bottom_in[3]:57 chany_top_in[3]:18 5.41069e-06 +73 chany_bottom_in[3]:33 chany_top_in[3]:44 9.430995e-05 +74 chany_bottom_in[3]:33 chany_top_in[3]:46 6.337246e-05 +75 chany_bottom_in[3]:55 chany_top_in[3]:21 4.867167e-05 +76 chany_bottom_in[3]:55 chany_top_in[3]:22 0.0002488395 +77 chany_bottom_in[3]:52 chany_top_in[3]:29 2.398279e-05 +78 chany_bottom_in[3]:51 chany_top_in[3]:30 2.398279e-05 +79 chany_bottom_in[3]:42 chany_top_in[3]:33 4.387045e-05 +80 chany_bottom_in[3]:42 chany_top_in[3]:38 6.750582e-05 +81 chany_bottom_in[3]:42 chany_top_in[3]:35 1.223276e-06 +82 chany_bottom_in[3]:41 chany_top_in[3]:38 1.223276e-06 +83 chany_bottom_in[3]:41 chany_top_in[3]:39 6.750582e-05 +84 chany_bottom_in[3]:41 chany_top_in[3]:34 4.387045e-05 +85 chany_bottom_in[3]:20 chany_top_in[3]:58 3.852241e-07 +86 chany_bottom_in[3]:19 chany_top_in[3]:59 3.852241e-07 +87 chany_bottom_in[3]:27 chany_top_in[3]:51 1.687876e-05 +88 chany_bottom_in[3]:28 chany_top_in[3]:52 1.687876e-05 +89 chany_bottom_in[3]:29 chany_top_in[3]:47 2.632639e-05 +90 chany_bottom_in[3]:31 chany_top_in[3]:46 2.632639e-05 +91 chany_bottom_in[3]:58 chany_top_in[3]:18 1.582671e-05 +92 chany_bottom_in[3]:32 chany_top_in[3]:47 6.337246e-05 +93 chany_bottom_in[3]:32 chany_top_in[3]:45 9.430995e-05 +94 chany_bottom_in[3]:48 chany_top_in[17]:23 7.78316e-06 +95 chany_bottom_in[3]:48 chany_top_in[17]:24 4.819824e-06 +96 chany_bottom_in[3]:45 chany_top_in[17]:24 7.78316e-06 +97 chany_bottom_in[3]:55 chany_top_in[17]:23 4.819824e-06 +98 chany_bottom_in[3]:42 chany_top_in[17]:23 0.00027752 +99 chany_bottom_in[3]:41 chany_top_in[17]:24 0.00027752 +100 chany_bottom_in[3]:48 prog_clk[0]:235 1.311891e-05 +101 chany_bottom_in[3]:48 prog_clk[0]:225 3.68878e-05 +102 chany_bottom_in[3]:48 prog_clk[0]:236 6.437373e-06 +103 chany_bottom_in[3]:57 prog_clk[0]:224 6.512422e-05 +104 chany_bottom_in[3]:57 prog_clk[0]:199 4.051271e-05 +105 chany_bottom_in[3]:57 prog_clk[0]:220 5.071676e-06 +106 chany_bottom_in[3]:57 prog_clk[0]:216 4.700578e-07 +107 chany_bottom_in[3]:57 prog_clk[0]:213 1.595621e-05 +108 chany_bottom_in[3]:37 prog_clk[0]:287 1.287109e-07 +109 chany_bottom_in[3]:37 prog_clk[0]:281 7.117382e-07 +110 chany_bottom_in[3]:36 prog_clk[0]:284 7.117382e-07 +111 chany_bottom_in[3]:36 prog_clk[0]:290 1.287109e-07 +112 chany_bottom_in[3]:45 prog_clk[0]:236 1.311891e-05 +113 chany_bottom_in[3]:55 prog_clk[0]:221 5.071676e-06 +114 chany_bottom_in[3]:55 prog_clk[0]:224 3.68878e-05 +115 chany_bottom_in[3]:55 prog_clk[0]:235 6.437373e-06 +116 chany_bottom_in[3]:55 prog_clk[0]:220 4.700578e-07 +117 chany_bottom_in[3]:55 prog_clk[0]:200 4.051271e-05 +118 chany_bottom_in[3]:55 prog_clk[0]:225 6.512422e-05 +119 chany_bottom_in[3]:55 prog_clk[0]:214 1.595621e-05 +120 chany_bottom_in[3]:20 prog_clk[0]:379 6.419727e-05 +121 chany_bottom_in[3]:20 prog_clk[0]:371 9.229625e-06 +122 chany_bottom_in[3]:20 prog_clk[0]:375 5.815217e-05 +123 chany_bottom_in[3]:20 prog_clk[0]:376 8.253059e-06 +124 chany_bottom_in[3]:20 prog_clk[0]:383 2.318911e-05 +125 chany_bottom_in[3]:20 prog_clk[0]:384 3.195537e-05 +126 chany_bottom_in[3]:19 prog_clk[0]:364 9.229625e-06 +127 chany_bottom_in[3]:19 prog_clk[0]:353 6.419727e-05 +128 chany_bottom_in[3]:19 prog_clk[0]:379 2.318911e-05 +129 chany_bottom_in[3]:19 prog_clk[0]:371 5.815217e-05 +130 chany_bottom_in[3]:19 prog_clk[0]:375 8.253059e-06 +131 chany_bottom_in[3]:19 prog_clk[0]:383 3.195537e-05 +132 chany_bottom_in[3]:16 prog_clk[0]:371 5.132294e-05 +133 chany_bottom_in[3]:15 prog_clk[0]:364 5.132294e-05 +134 chany_bottom_in[3]:48 mux_tree_tapbuf_size8_6_sram[0]:6 7.393221e-08 +135 chany_bottom_in[3]:48 mux_tree_tapbuf_size8_6_sram[0]:5 1.150057e-07 +136 chany_bottom_in[3]:44 mux_tree_tapbuf_size8_6_sram[0]:4 8.949036e-05 +137 chany_bottom_in[3]:44 mux_tree_tapbuf_size8_6_sram[0]:3 4.535968e-05 +138 chany_bottom_in[3]:45 mux_tree_tapbuf_size8_6_sram[0]:5 7.393221e-08 +139 chany_bottom_in[3]:55 mux_tree_tapbuf_size8_6_sram[0]:6 1.150057e-07 +140 chany_bottom_in[3]:43 mux_tree_tapbuf_size8_6_sram[0]:3 8.949036e-05 +141 chany_bottom_in[3]:10 mux_tree_tapbuf_size8_6_sram[0]:4 4.535968e-05 +142 chany_bottom_in[3]:29 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.148513e-05 +143 chany_bottom_in[3]:31 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.148513e-05 +144 chany_bottom_in[3]:54 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0003181813 +145 chany_bottom_in[3]:53 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0003181813 +146 chany_bottom_in[3]:25 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.195966e-05 +147 chany_bottom_in[3]:21 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.927853e-05 +148 chany_bottom_in[3]:24 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.927853e-05 +149 chany_bottom_in[3]:24 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.195966e-05 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:61 0.01034375 +1 chany_bottom_in[3]:47 chany_bottom_in[3]:46 0.003212054 +2 chany_bottom_in[3]:48 chany_bottom_in[3]:47 0.0045 +3 chany_bottom_in[3]:48 chany_bottom_in[3]:45 0.002388393 +4 chany_bottom_in[3]:46 mux_right_ipin_8\/mux_l1_in_1_:A1 0.152 +5 chany_bottom_in[3]:56 mux_right_ipin_12\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[3]:57 chany_bottom_in[3]:56 0.0045 +7 chany_bottom_in[3]:57 chany_bottom_in[3]:55 0.01851786 +8 chany_bottom_in[3]:38 chany_bottom_in[3]:37 0.0045 +9 chany_bottom_in[3]:37 chany_bottom_in[3]:36 0.002348214 +10 chany_bottom_in[3]:35 chany_bottom_in[3]:34 0.004848215 +11 chany_bottom_in[3]:36 chany_bottom_in[3]:35 0.0045 +12 chany_bottom_in[3]:34 chany_bottom_in[3]:33 0.0045 +13 chany_bottom_in[3]:33 chany_bottom_in[3]:32 0.009674108 +14 chany_bottom_in[3]:26 chany_bottom_in[3]:25 0.0045 +15 chany_bottom_in[3]:25 chany_bottom_in[3]:24 0.005120536 +16 chany_bottom_in[3]:44 chany_bottom_in[3]:43 0.002013393 +17 chany_bottom_in[3]:44 chany_bottom_in[3]:10 0.0009441964 +18 chany_bottom_in[3]:45 chany_bottom_in[3]:44 0.0045 +19 chany_bottom_in[3]:55 chany_bottom_in[3]:54 0.00341 +20 chany_bottom_in[3]:55 chany_bottom_in[3]:48 0.003946429 +21 chany_bottom_in[3]:54 chany_bottom_in[3]:53 0.00259205 +22 chany_bottom_in[3]:52 chany_bottom_in[3]:51 0.001426339 +23 chany_bottom_in[3]:53 chany_bottom_in[3]:52 0.00341 +24 chany_bottom_in[3]:50 chany_bottom_in[3]:49 9.239131e-05 +25 chany_bottom_in[3]:51 chany_bottom_in[3]:50 0.0045 +26 chany_bottom_in[3]:49 mux_right_ipin_10\/mux_l2_in_0_:A0 0.152 +27 chany_bottom_in[3]:43 chany_bottom_in[3]:42 0.0045 +28 chany_bottom_in[3]:42 chany_bottom_in[3]:41 0.02086607 +29 chany_bottom_in[3]:40 chany_bottom_in[3]:39 0.0001847826 +30 chany_bottom_in[3]:41 chany_bottom_in[3]:40 0.0045 +31 chany_bottom_in[3]:39 mux_right_ipin_6\/mux_l2_in_0_:A0 0.152 +32 chany_bottom_in[3]:39 chany_bottom_in[3]:38 0.0008013393 +33 chany_bottom_in[3]:21 chany_bottom_in[3]:20 0.00341 +34 chany_bottom_in[3]:20 chany_bottom_in[3]:19 0.005688958 +35 chany_bottom_in[3]:19 chany_bottom_in[3]:18 0.00341 +36 chany_bottom_in[3]:18 chany_bottom_in[3]:17 0.0007433833 +37 chany_bottom_in[3]:16 chany_bottom_in[3]:15 0.000356025 +38 chany_bottom_in[3]:17 chany_bottom_in[3]:16 0.00341 +39 chany_bottom_in[3]:14 chany_bottom_in[3]:13 0.005979911 +40 chany_bottom_in[3]:15 chany_bottom_in[3]:14 0.00341 +41 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.003212054 +42 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.0045 +43 chany_bottom_in[3]:11 FTB_4__3:A 0.152 +44 chany_bottom_in[3]:27 mux_right_ipin_4\/mux_l1_in_1_:A1 0.152 +45 chany_bottom_in[3]:27 chany_bottom_in[3]:26 0.0001847826 +46 chany_bottom_in[3]:10 mux_right_ipin_14\/mux_l2_in_0_:A0 0.152 +47 chany_bottom_in[3]:23 chany_bottom_in[3]:22 9.239132e-05 +48 chany_bottom_in[3]:24 chany_bottom_in[3]:23 0.0045 +49 chany_bottom_in[3]:24 chany_bottom_in[3]:21 0.001466518 +50 chany_bottom_in[3]:22 mux_right_ipin_2\/mux_l2_in_0_:A0 0.152 +51 chany_bottom_in[3]:28 chany_bottom_in[3]:27 0.005319196 +52 chany_bottom_in[3]:29 chany_bottom_in[3]:28 0.0045 +53 chany_bottom_in[3]:30 mux_right_ipin_0\/mux_l1_in_1_:A1 0.152 +54 chany_bottom_in[3]:31 chany_bottom_in[3]:30 0.0045 +55 chany_bottom_in[3]:31 chany_bottom_in[3]:29 0.004816964 +56 chany_bottom_in[3]:59 chany_bottom_in[3]:58 0.0045 +57 chany_bottom_in[3]:58 chany_bottom_in[3]:57 0.001477679 +58 chany_bottom_in[3]:60 chany_bottom_in[3]:59 0.006080358 +59 chany_bottom_in[3]:61 chany_bottom_in[3]:60 0.0045 +60 chany_bottom_in[3]:32 chany_bottom_in[3]:31 0.0004107143 + +*END + +*D_NET left_grid_pin_6_[0] 0.001200482 //LENGTH 8.760 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 74.800 +*P left_grid_pin_6_[0] O *L 0.7423 *C 1.298 80.240 +*N left_grid_pin_6_[0]:2 *C 1.380 80.240 +*N left_grid_pin_6_[0]:3 *C 1.380 80.240 +*N left_grid_pin_6_[0]:4 *C 2.760 80.240 +*N left_grid_pin_6_[0]:5 *C 2.760 74.845 +*N left_grid_pin_6_[0]:6 *C 2.805 74.800 +*N left_grid_pin_6_[0]:7 *C 3.588 74.800 + +*CAP +0 mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_6_[0] 3.040809e-05 +2 left_grid_pin_6_[0]:2 3.040809e-05 +3 left_grid_pin_6_[0]:3 0.000110983 +4 left_grid_pin_6_[0]:4 0.0004723535 +5 left_grid_pin_6_[0]:5 0.0003949369 +6 left_grid_pin_6_[0]:6 8.019646e-05 +7 left_grid_pin_6_[0]:7 8.019646e-05 + +*RES +0 mux_right_ipin_6\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_6_[0]:7 0.152 +1 left_grid_pin_6_[0]:7 left_grid_pin_6_[0]:6 0.0006986608 +2 left_grid_pin_6_[0]:6 left_grid_pin_6_[0]:5 0.0045 +3 left_grid_pin_6_[0]:5 left_grid_pin_6_[0]:4 0.004816964 +4 left_grid_pin_6_[0]:3 left_grid_pin_6_[0]:2 0.00341 +5 left_grid_pin_6_[0]:2 left_grid_pin_6_[0] 2.35e-05 +6 left_grid_pin_6_[0]:4 left_grid_pin_6_[0]:3 0.001232143 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.0008307179 //LENGTH 7.445 LUMPCC 0 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 80.345 58.820 +*I mem_left_ipin_0\/FTB_1__40:A I *L 0.001746 *C 80.960 61.200 +*I mux_left_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 79.480 63.240 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 79.517 63.240 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 80.915 63.240 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 80.960 63.195 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 80.960 61.200 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 80.960 61.200 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 80.960 58.865 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 80.915 58.820 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 80.383 58.820 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_ipin_0\/FTB_1__40:A 1e-06 +2 mux_left_ipin_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 0.000121282 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.000121282 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0001030249 +6 mux_tree_tapbuf_size10_0_sram[3]:6 2.846287e-05 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0002418508 +8 mux_tree_tapbuf_size10_0_sram[3]:8 0.0001121551 +9 mux_tree_tapbuf_size10_0_sram[3]:9 4.983007e-05 +10 mux_tree_tapbuf_size10_0_sram[3]:10 4.983007e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:6 mem_left_ipin_0\/FTB_1__40:A 0.152 +2 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.0045 +3 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:5 0.00178125 +4 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.002084821 +6 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.0004754465 +7 mux_tree_tapbuf_size10_0_sram[3]:4 mux_tree_tapbuf_size10_0_sram[3]:3 0.001247768 +8 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.0045 +9 mux_tree_tapbuf_size10_0_sram[3]:3 mux_left_ipin_0\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[2] 0.004442233 //LENGTH 30.465 LUMPCC 0.0005227937 DR + +*CONN +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 42.165 96.560 +*I mux_right_ipin_1\/mux_l3_in_1_:S I *L 0.00357 *C 38.300 94.520 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 27.775 96.900 +*I mux_right_ipin_1\/mux_l3_in_0_:S I *L 0.00357 *C 49.320 94.520 +*N mux_tree_tapbuf_size10_2_sram[2]:4 *C 49.282 94.520 +*N mux_tree_tapbuf_size10_2_sram[2]:5 *C 43.285 94.520 +*N mux_tree_tapbuf_size10_2_sram[2]:6 *C 43.240 94.565 +*N mux_tree_tapbuf_size10_2_sram[2]:7 *C 43.240 96.515 +*N mux_tree_tapbuf_size10_2_sram[2]:8 *C 43.195 96.560 +*N mux_tree_tapbuf_size10_2_sram[2]:9 *C 27.812 96.900 +*N mux_tree_tapbuf_size10_2_sram[2]:10 *C 29.440 96.900 +*N mux_tree_tapbuf_size10_2_sram[2]:11 *C 29.440 97.240 +*N mux_tree_tapbuf_size10_2_sram[2]:12 *C 38.263 94.520 +*N mux_tree_tapbuf_size10_2_sram[2]:13 *C 37.765 94.520 +*N mux_tree_tapbuf_size10_2_sram[2]:14 *C 37.720 94.565 +*N mux_tree_tapbuf_size10_2_sram[2]:15 *C 37.720 97.195 +*N mux_tree_tapbuf_size10_2_sram[2]:16 *C 37.720 97.240 +*N mux_tree_tapbuf_size10_2_sram[2]:17 *C 42.275 97.240 +*N mux_tree_tapbuf_size10_2_sram[2]:18 *C 42.320 97.195 +*N mux_tree_tapbuf_size10_2_sram[2]:19 *C 42.320 96.605 +*N mux_tree_tapbuf_size10_2_sram[2]:20 *C 42.365 96.560 +*N mux_tree_tapbuf_size10_2_sram[2]:21 *C 42.165 96.560 + +*CAP +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_1\/mux_l3_in_1_:S 1e-06 +2 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_1\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_2_sram[2]:4 0.0004669366 +5 mux_tree_tapbuf_size10_2_sram[2]:5 0.0004669366 +6 mux_tree_tapbuf_size10_2_sram[2]:6 0.0001175468 +7 mux_tree_tapbuf_size10_2_sram[2]:7 0.0001175468 +8 mux_tree_tapbuf_size10_2_sram[2]:8 5.982653e-05 +9 mux_tree_tapbuf_size10_2_sram[2]:9 0.0001268036 +10 mux_tree_tapbuf_size10_2_sram[2]:10 0.0001528802 +11 mux_tree_tapbuf_size10_2_sram[2]:11 0.0006018808 +12 mux_tree_tapbuf_size10_2_sram[2]:12 6.222491e-05 +13 mux_tree_tapbuf_size10_2_sram[2]:13 6.222491e-05 +14 mux_tree_tapbuf_size10_2_sram[2]:14 0.0001827294 +15 mux_tree_tapbuf_size10_2_sram[2]:15 0.0001827294 +16 mux_tree_tapbuf_size10_2_sram[2]:16 0.0008236674 +17 mux_tree_tapbuf_size10_2_sram[2]:17 0.0002146627 +18 mux_tree_tapbuf_size10_2_sram[2]:18 7.502024e-05 +19 mux_tree_tapbuf_size10_2_sram[2]:19 7.502024e-05 +20 mux_tree_tapbuf_size10_2_sram[2]:20 7.784132e-05 +21 mux_tree_tapbuf_size10_2_sram[2]:21 4.896017e-05 +22 mux_tree_tapbuf_size10_2_sram[2]:6 chany_bottom_in[9]:9 5.507719e-05 +23 mux_tree_tapbuf_size10_2_sram[2]:8 chany_bottom_in[9]:11 2.196595e-05 +24 mux_tree_tapbuf_size10_2_sram[2]:7 chany_bottom_in[9]:10 5.507719e-05 +25 mux_tree_tapbuf_size10_2_sram[2]:21 chany_bottom_in[9]:12 7.854548e-06 +26 mux_tree_tapbuf_size10_2_sram[2]:17 chany_bottom_in[9]:11 0.0001602353 +27 mux_tree_tapbuf_size10_2_sram[2]:20 chany_bottom_in[9]:11 7.854548e-06 +28 mux_tree_tapbuf_size10_2_sram[2]:20 chany_bottom_in[9]:12 2.196595e-05 +29 mux_tree_tapbuf_size10_2_sram[2]:14 chany_bottom_in[9]:13 1.62639e-05 +30 mux_tree_tapbuf_size10_2_sram[2]:16 chany_bottom_in[9]:12 0.0001602353 +31 mux_tree_tapbuf_size10_2_sram[2]:15 chany_bottom_in[9]:14 1.62639e-05 + +*RES +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_2_sram[2]:21 0.152 +1 mux_tree_tapbuf_size10_2_sram[2]:4 mux_right_ipin_1\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[2]:5 mux_tree_tapbuf_size10_2_sram[2]:4 0.005354911 +3 mux_tree_tapbuf_size10_2_sram[2]:6 mux_tree_tapbuf_size10_2_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size10_2_sram[2]:8 mux_tree_tapbuf_size10_2_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size10_2_sram[2]:7 mux_tree_tapbuf_size10_2_sram[2]:6 0.001741072 +6 mux_tree_tapbuf_size10_2_sram[2]:21 mux_tree_tapbuf_size10_2_sram[2]:20 0.0001086957 +7 mux_tree_tapbuf_size10_2_sram[2]:9 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_2_sram[2]:17 mux_tree_tapbuf_size10_2_sram[2]:16 0.004066965 +9 mux_tree_tapbuf_size10_2_sram[2]:18 mux_tree_tapbuf_size10_2_sram[2]:17 0.0045 +10 mux_tree_tapbuf_size10_2_sram[2]:20 mux_tree_tapbuf_size10_2_sram[2]:19 0.0045 +11 mux_tree_tapbuf_size10_2_sram[2]:20 mux_tree_tapbuf_size10_2_sram[2]:8 0.0007410714 +12 mux_tree_tapbuf_size10_2_sram[2]:19 mux_tree_tapbuf_size10_2_sram[2]:18 0.0005267857 +13 mux_tree_tapbuf_size10_2_sram[2]:12 mux_right_ipin_1\/mux_l3_in_1_:S 0.152 +14 mux_tree_tapbuf_size10_2_sram[2]:13 mux_tree_tapbuf_size10_2_sram[2]:12 0.0004441965 +15 mux_tree_tapbuf_size10_2_sram[2]:14 mux_tree_tapbuf_size10_2_sram[2]:13 0.0045 +16 mux_tree_tapbuf_size10_2_sram[2]:16 mux_tree_tapbuf_size10_2_sram[2]:15 0.0045 +17 mux_tree_tapbuf_size10_2_sram[2]:16 mux_tree_tapbuf_size10_2_sram[2]:11 0.007392858 +18 mux_tree_tapbuf_size10_2_sram[2]:15 mux_tree_tapbuf_size10_2_sram[2]:14 0.002348214 +19 mux_tree_tapbuf_size10_2_sram[2]:10 mux_tree_tapbuf_size10_2_sram[2]:9 0.001453125 +20 mux_tree_tapbuf_size10_2_sram[2]:11 mux_tree_tapbuf_size10_2_sram[2]:10 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[0] 0.006235821 //LENGTH 44.295 LUMPCC 0.00105118 DR + +*CONN +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 15.025 25.840 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 10.765 17.340 +*I mux_right_ipin_12\/mux_l1_in_0_:S I *L 0.00357 *C 27.700 12.240 +*I mux_right_ipin_12\/mux_l1_in_1_:S I *L 0.00357 *C 35.060 14.280 +*I mux_right_ipin_12\/mux_l1_in_2_:S I *L 0.00357 *C 17.840 12.535 +*N mux_tree_tapbuf_size10_7_sram[0]:5 *C 17.840 12.535 +*N mux_tree_tapbuf_size10_7_sram[0]:6 *C 35.075 14.280 +*N mux_tree_tapbuf_size10_7_sram[0]:7 *C 35.398 14.280 +*N mux_tree_tapbuf_size10_7_sram[0]:8 *C 35.420 14.235 +*N mux_tree_tapbuf_size10_7_sram[0]:9 *C 35.420 12.625 +*N mux_tree_tapbuf_size10_7_sram[0]:10 *C 35.375 12.580 +*N mux_tree_tapbuf_size10_7_sram[0]:11 *C 28.980 12.580 +*N mux_tree_tapbuf_size10_7_sram[0]:12 *C 28.980 12.240 +*N mux_tree_tapbuf_size10_7_sram[0]:13 *C 27.700 12.240 +*N mux_tree_tapbuf_size10_7_sram[0]:14 *C 17.840 12.240 +*N mux_tree_tapbuf_size10_7_sram[0]:15 *C 15.685 12.240 +*N mux_tree_tapbuf_size10_7_sram[0]:16 *C 15.640 12.285 +*N mux_tree_tapbuf_size10_7_sram[0]:17 *C 15.640 17.000 +*N mux_tree_tapbuf_size10_7_sram[0]:18 *C 10.765 17.340 +*N mux_tree_tapbuf_size10_7_sram[0]:19 *C 11.960 17.340 +*N mux_tree_tapbuf_size10_7_sram[0]:20 *C 11.960 17.000 +*N mux_tree_tapbuf_size10_7_sram[0]:21 *C 15.135 17.000 +*N mux_tree_tapbuf_size10_7_sram[0]:22 *C 15.180 17.000 +*N mux_tree_tapbuf_size10_7_sram[0]:23 *C 15.180 25.795 +*N mux_tree_tapbuf_size10_7_sram[0]:24 *C 15.180 25.840 +*N mux_tree_tapbuf_size10_7_sram[0]:25 *C 15.025 25.840 + +*CAP +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_12\/mux_l1_in_0_:S 1e-06 +3 mux_right_ipin_12\/mux_l1_in_1_:S 1e-06 +4 mux_right_ipin_12\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_7_sram[0]:5 5.877154e-05 +6 mux_tree_tapbuf_size10_7_sram[0]:6 5.442344e-05 +7 mux_tree_tapbuf_size10_7_sram[0]:7 5.442344e-05 +8 mux_tree_tapbuf_size10_7_sram[0]:8 0.0001394552 +9 mux_tree_tapbuf_size10_7_sram[0]:9 0.0001394552 +10 mux_tree_tapbuf_size10_7_sram[0]:10 0.0004567857 +11 mux_tree_tapbuf_size10_7_sram[0]:11 0.0004825323 +12 mux_tree_tapbuf_size10_7_sram[0]:12 9.181532e-05 +13 mux_tree_tapbuf_size10_7_sram[0]:13 0.0007208613 +14 mux_tree_tapbuf_size10_7_sram[0]:14 0.0007789952 +15 mux_tree_tapbuf_size10_7_sram[0]:15 0.0001224503 +16 mux_tree_tapbuf_size10_7_sram[0]:16 0.0002166719 +17 mux_tree_tapbuf_size10_7_sram[0]:17 0.0002493817 +18 mux_tree_tapbuf_size10_7_sram[0]:18 0.0001447982 +19 mux_tree_tapbuf_size10_7_sram[0]:19 0.0001271746 +20 mux_tree_tapbuf_size10_7_sram[0]:20 0.0002862499 +21 mux_tree_tapbuf_size10_7_sram[0]:21 0.0002613962 +22 mux_tree_tapbuf_size10_7_sram[0]:22 0.0003625611 +23 mux_tree_tapbuf_size10_7_sram[0]:23 0.0003298513 +24 mux_tree_tapbuf_size10_7_sram[0]:24 5.324489e-05 +25 mux_tree_tapbuf_size10_7_sram[0]:25 4.834164e-05 +26 mux_tree_tapbuf_size10_7_sram[0]:15 chany_top_in[7]:23 1.644251e-05 +27 mux_tree_tapbuf_size10_7_sram[0]:15 chany_top_in[7]:27 7.337324e-06 +28 mux_tree_tapbuf_size10_7_sram[0]:16 chany_top_in[7]:24 2.770258e-05 +29 mux_tree_tapbuf_size10_7_sram[0]:16 chany_top_in[7]:28 4.336619e-05 +30 mux_tree_tapbuf_size10_7_sram[0]:22 chany_top_in[7]:28 0.0002518506 +31 mux_tree_tapbuf_size10_7_sram[0]:23 chany_top_in[7]:29 0.0002518506 +32 mux_tree_tapbuf_size10_7_sram[0]:14 chany_top_in[7]:22 1.644251e-05 +33 mux_tree_tapbuf_size10_7_sram[0]:14 chany_top_in[7]:26 7.337324e-06 +34 mux_tree_tapbuf_size10_7_sram[0]:17 chany_top_in[7]:25 2.770258e-05 +35 mux_tree_tapbuf_size10_7_sram[0]:17 chany_top_in[7]:29 4.336619e-05 +36 mux_tree_tapbuf_size10_7_sram[0]:13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001161663 +37 mux_tree_tapbuf_size10_7_sram[0]:13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.919021e-05 +38 mux_tree_tapbuf_size10_7_sram[0]:10 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.353432e-05 +39 mux_tree_tapbuf_size10_7_sram[0]:14 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001161663 +40 mux_tree_tapbuf_size10_7_sram[0]:12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.919021e-05 +41 mux_tree_tapbuf_size10_7_sram[0]:11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.353432e-05 + +*RES +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_7_sram[0]:25 0.152 +1 mux_tree_tapbuf_size10_7_sram[0]:13 mux_right_ipin_12\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[0]:13 mux_tree_tapbuf_size10_7_sram[0]:12 0.001142857 +3 mux_tree_tapbuf_size10_7_sram[0]:15 mux_tree_tapbuf_size10_7_sram[0]:14 0.001924107 +4 mux_tree_tapbuf_size10_7_sram[0]:16 mux_tree_tapbuf_size10_7_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size10_7_sram[0]:10 mux_tree_tapbuf_size10_7_sram[0]:9 0.0045 +6 mux_tree_tapbuf_size10_7_sram[0]:9 mux_tree_tapbuf_size10_7_sram[0]:8 0.0014375 +7 mux_tree_tapbuf_size10_7_sram[0]:7 mux_tree_tapbuf_size10_7_sram[0]:6 0.0001752718 +8 mux_tree_tapbuf_size10_7_sram[0]:8 mux_tree_tapbuf_size10_7_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size10_7_sram[0]:6 mux_right_ipin_12\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size10_7_sram[0]:21 mux_tree_tapbuf_size10_7_sram[0]:20 0.002834822 +11 mux_tree_tapbuf_size10_7_sram[0]:22 mux_tree_tapbuf_size10_7_sram[0]:21 0.0045 +12 mux_tree_tapbuf_size10_7_sram[0]:22 mux_tree_tapbuf_size10_7_sram[0]:17 0.0004107143 +13 mux_tree_tapbuf_size10_7_sram[0]:18 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size10_7_sram[0]:24 mux_tree_tapbuf_size10_7_sram[0]:23 0.0045 +15 mux_tree_tapbuf_size10_7_sram[0]:23 mux_tree_tapbuf_size10_7_sram[0]:22 0.007852679 +16 mux_tree_tapbuf_size10_7_sram[0]:25 mux_tree_tapbuf_size10_7_sram[0]:24 8.423914e-05 +17 mux_tree_tapbuf_size10_7_sram[0]:5 mux_right_ipin_12\/mux_l1_in_2_:S 0.152 +18 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:18 0.001066964 +19 mux_tree_tapbuf_size10_7_sram[0]:20 mux_tree_tapbuf_size10_7_sram[0]:19 0.0003035715 +20 mux_tree_tapbuf_size10_7_sram[0]:14 mux_tree_tapbuf_size10_7_sram[0]:13 0.008803573 +21 mux_tree_tapbuf_size10_7_sram[0]:14 mux_tree_tapbuf_size10_7_sram[0]:5 0.0001271552 +22 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:11 0.0003035715 +23 mux_tree_tapbuf_size10_7_sram[0]:11 mux_tree_tapbuf_size10_7_sram[0]:10 0.005709822 +24 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:16 0.004209822 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[1] 0.004562154 //LENGTH 32.420 LUMPCC 0.0002208465 DR + +*CONN +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 28.825 47.940 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 15.355 49.980 +*I mux_right_ipin_11\/mux_l2_in_0_:S I *L 0.00357 *C 16.200 52.750 +*I mux_right_ipin_11\/mux_l2_in_3_:S I *L 0.00357 *C 25.400 52.750 +*I mux_right_ipin_11\/mux_l2_in_1_:S I *L 0.00357 *C 24.480 55.760 +*I mux_right_ipin_11\/mux_l2_in_2_:S I *L 0.00357 *C 29.540 55.760 +*N mux_tree_tapbuf_size8_5_sram[1]:6 *C 29.503 55.760 +*N mux_tree_tapbuf_size8_5_sram[1]:7 *C 24.518 55.760 +*N mux_tree_tapbuf_size8_5_sram[1]:8 *C 28.980 55.760 +*N mux_tree_tapbuf_size8_5_sram[1]:9 *C 28.980 55.715 +*N mux_tree_tapbuf_size8_5_sram[1]:10 *C 25.400 52.750 +*N mux_tree_tapbuf_size8_5_sram[1]:11 *C 16.200 52.750 +*N mux_tree_tapbuf_size8_5_sram[1]:12 *C 15.393 49.980 +*N mux_tree_tapbuf_size8_5_sram[1]:13 *C 16.055 49.980 +*N mux_tree_tapbuf_size8_5_sram[1]:14 *C 16.100 50.025 +*N mux_tree_tapbuf_size8_5_sram[1]:15 *C 16.100 52.995 +*N mux_tree_tapbuf_size8_5_sram[1]:16 *C 16.258 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:17 *C 25.400 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:18 *C 28.935 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:19 *C 28.980 53.040 +*N mux_tree_tapbuf_size8_5_sram[1]:20 *C 28.980 47.985 +*N mux_tree_tapbuf_size8_5_sram[1]:21 *C 28.980 47.940 +*N mux_tree_tapbuf_size8_5_sram[1]:22 *C 28.825 47.940 + +*CAP +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_ipin_11\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_11\/mux_l2_in_3_:S 1e-06 +4 mux_right_ipin_11\/mux_l2_in_1_:S 1e-06 +5 mux_right_ipin_11\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size8_5_sram[1]:6 5.210317e-05 +7 mux_tree_tapbuf_size8_5_sram[1]:7 0.0003514776 +8 mux_tree_tapbuf_size8_5_sram[1]:8 0.0004393239 +9 mux_tree_tapbuf_size8_5_sram[1]:9 0.0002102698 +10 mux_tree_tapbuf_size8_5_sram[1]:10 5.23071e-05 +11 mux_tree_tapbuf_size8_5_sram[1]:11 5.775361e-05 +12 mux_tree_tapbuf_size8_5_sram[1]:12 6.795842e-05 +13 mux_tree_tapbuf_size8_5_sram[1]:13 6.795842e-05 +14 mux_tree_tapbuf_size8_5_sram[1]:14 0.0001720823 +15 mux_tree_tapbuf_size8_5_sram[1]:15 0.0001720823 +16 mux_tree_tapbuf_size8_5_sram[1]:16 0.0005667271 +17 mux_tree_tapbuf_size8_5_sram[1]:17 0.0008207407 +18 mux_tree_tapbuf_size8_5_sram[1]:18 0.0002584939 +19 mux_tree_tapbuf_size8_5_sram[1]:19 0.0005907866 +20 mux_tree_tapbuf_size8_5_sram[1]:20 0.0003509494 +21 mux_tree_tapbuf_size8_5_sram[1]:21 5.456043e-05 +22 mux_tree_tapbuf_size8_5_sram[1]:22 4.973263e-05 +23 mux_tree_tapbuf_size8_5_sram[1]:16 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001104232 +24 mux_tree_tapbuf_size8_5_sram[1]:17 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001104232 + +*RES +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_5_sram[1]:22 0.152 +1 mux_tree_tapbuf_size8_5_sram[1]:8 mux_tree_tapbuf_size8_5_sram[1]:7 0.003984375 +2 mux_tree_tapbuf_size8_5_sram[1]:8 mux_tree_tapbuf_size8_5_sram[1]:6 0.0004665179 +3 mux_tree_tapbuf_size8_5_sram[1]:9 mux_tree_tapbuf_size8_5_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size8_5_sram[1]:16 mux_tree_tapbuf_size8_5_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size8_5_sram[1]:16 mux_tree_tapbuf_size8_5_sram[1]:11 0.000125 +6 mux_tree_tapbuf_size8_5_sram[1]:15 mux_tree_tapbuf_size8_5_sram[1]:14 0.002651786 +7 mux_tree_tapbuf_size8_5_sram[1]:13 mux_tree_tapbuf_size8_5_sram[1]:12 0.0005915179 +8 mux_tree_tapbuf_size8_5_sram[1]:14 mux_tree_tapbuf_size8_5_sram[1]:13 0.0045 +9 mux_tree_tapbuf_size8_5_sram[1]:12 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size8_5_sram[1]:18 mux_tree_tapbuf_size8_5_sram[1]:17 0.00315625 +11 mux_tree_tapbuf_size8_5_sram[1]:19 mux_tree_tapbuf_size8_5_sram[1]:18 0.0045 +12 mux_tree_tapbuf_size8_5_sram[1]:19 mux_tree_tapbuf_size8_5_sram[1]:9 0.002388393 +13 mux_tree_tapbuf_size8_5_sram[1]:21 mux_tree_tapbuf_size8_5_sram[1]:20 0.0045 +14 mux_tree_tapbuf_size8_5_sram[1]:20 mux_tree_tapbuf_size8_5_sram[1]:19 0.004513393 +15 mux_tree_tapbuf_size8_5_sram[1]:22 mux_tree_tapbuf_size8_5_sram[1]:21 8.423914e-05 +16 mux_tree_tapbuf_size8_5_sram[1]:10 mux_right_ipin_11\/mux_l2_in_3_:S 0.152 +17 mux_tree_tapbuf_size8_5_sram[1]:6 mux_right_ipin_11\/mux_l2_in_2_:S 0.152 +18 mux_tree_tapbuf_size8_5_sram[1]:7 mux_right_ipin_11\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size8_5_sram[1]:11 mux_right_ipin_11\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size8_5_sram[1]:17 mux_tree_tapbuf_size8_5_sram[1]:16 0.008162946 +21 mux_tree_tapbuf_size8_5_sram[1]:17 mux_tree_tapbuf_size8_5_sram[1]:10 0.000125 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006400232 //LENGTH 4.700 LUMPCC 0.0001312869 DR + +*CONN +*I mux_right_ipin_4\/mux_l1_in_0_:X O *L 0 *C 24.095 83.300 +*I mux_right_ipin_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 19.685 83.300 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 19.723 83.300 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 24.058 83.300 + +*CAP +0 mux_right_ipin_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002533681 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002533681 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:14 6.564346e-05 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:15 6.564346e-05 + +*RES +0 mux_right_ipin_4\/mux_l1_in_0_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_4\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003870536 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001053957 //LENGTH 7.695 LUMPCC 0.0001105119 DR + +*CONN +*I mux_right_ipin_8\/mux_l1_in_1_:X O *L 0 *C 30.075 38.760 +*I mux_right_ipin_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 24.670 37.400 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 24.707 37.400 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 28.015 37.400 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.060 37.445 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.060 38.715 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 28.105 38.760 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 30.038 38.760 + +*CAP +0 mux_right_ipin_8\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_8\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001968728 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001968728 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.97178e-05 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.97178e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000174132 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000174132 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.525594e-05 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.525594e-05 + +*RES +0 mux_right_ipin_8\/mux_l1_in_1_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_8\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002953125 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001133929 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003059052 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_12\/mux_l3_in_1_:X O *L 0 *C 20.875 21.080 +*I mux_right_ipin_12\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.690 21.080 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 18.727 21.080 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 20.838 21.080 + +*CAP +0 mux_right_ipin_12\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_12\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001519526 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001519526 + +*RES +0 mux_right_ipin_12\/mux_l3_in_1_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_12\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001883929 + +*END + +*D_NET optlc_net_133 0.01699182 //LENGTH 133.615 LUMPCC 0.001044959 DR + +*CONN +*I optlc_128:HI O *L 0 *C 27.140 49.980 +*I mux_right_ipin_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 65.150 31.960 +*I mux_right_ipin_13\/mux_l2_in_3_:A0 I *L 0.001631 *C 49.855 15.300 +*I mux_right_ipin_12\/mux_l2_in_3_:A0 I *L 0.001631 *C 25.590 17.340 +*I mux_right_ipin_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 27.430 44.540 +*I mux_right_ipin_11\/mux_l2_in_3_:A0 I *L 0.001631 *C 26.510 53.380 +*I mux_right_ipin_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 27.890 60.520 +*I mux_right_ipin_6\/mux_l2_in_3_:A0 I *L 0.001631 *C 37.550 59.160 +*I mux_right_ipin_14\/mux_l2_in_3_:A0 I *L 0.001631 *C 31.455 49.980 +*N optlc_net_133:9 *C 31.483 50.003 +*N optlc_net_133:10 *C 31.740 50.015 +*N optlc_net_133:11 *C 31.740 50.320 +*N optlc_net_133:12 *C 27.600 50.320 +*N optlc_net_133:13 *C 27.600 49.980 +*N optlc_net_133:14 *C 37.550 59.160 +*N optlc_net_133:15 *C 37.260 59.160 +*N optlc_net_133:16 *C 37.260 59.205 +*N optlc_net_133:17 *C 37.260 60.475 +*N optlc_net_133:18 *C 37.215 60.520 +*N optlc_net_133:19 *C 28.013 60.520 +*N optlc_net_133:20 *C 27.185 60.520 +*N optlc_net_133:21 *C 27.140 60.475 +*N optlc_net_133:22 *C 26.548 53.380 +*N optlc_net_133:23 *C 27.095 53.380 +*N optlc_net_133:24 *C 27.140 53.380 +*N optlc_net_133:25 *C 27.468 44.540 +*N optlc_net_133:26 *C 28.015 44.540 +*N optlc_net_133:27 *C 25.628 17.340 +*N optlc_net_133:28 *C 26.175 17.340 +*N optlc_net_133:29 *C 26.220 17.295 +*N optlc_net_133:30 *C 26.220 15.685 +*N optlc_net_133:31 *C 26.265 15.640 +*N optlc_net_133:32 *C 48.300 15.640 +*N optlc_net_133:33 *C 49.818 15.300 +*N optlc_net_133:34 *C 48.300 15.300 +*N optlc_net_133:35 *C 48.300 15.345 +*N optlc_net_133:36 *C 65.112 31.960 +*N optlc_net_133:37 *C 48.345 31.960 +*N optlc_net_133:38 *C 48.300 31.960 +*N optlc_net_133:39 *C 48.300 44.143 +*N optlc_net_133:40 *C 48.293 44.200 +*N optlc_net_133:41 *C 28.073 44.200 +*N optlc_net_133:42 *C 28.068 44.535 +*N optlc_net_133:43 *C 28.060 44.540 +*N optlc_net_133:44 *C 27.140 44.540 +*N optlc_net_133:45 *C 27.140 49.980 +*N optlc_net_133:46 *C 27.178 49.980 + +*CAP +0 optlc_128:HI 1e-06 +1 mux_right_ipin_9\/mux_l2_in_3_:A0 1e-06 +2 mux_right_ipin_13\/mux_l2_in_3_:A0 1e-06 +3 mux_right_ipin_12\/mux_l2_in_3_:A0 1e-06 +4 mux_right_ipin_8\/mux_l2_in_3_:A0 1e-06 +5 mux_right_ipin_11\/mux_l2_in_3_:A0 1e-06 +6 mux_right_ipin_3\/mux_l2_in_3_:A0 1e-06 +7 mux_right_ipin_6\/mux_l2_in_3_:A0 1e-06 +8 mux_right_ipin_14\/mux_l2_in_3_:A0 1e-06 +9 optlc_net_133:9 1.22327e-05 +10 optlc_net_133:10 3.920855e-05 +11 optlc_net_133:11 0.0003245224 +12 optlc_net_133:12 0.0003247904 +13 optlc_net_133:13 7.426226e-05 +14 optlc_net_133:14 5.362812e-05 +15 optlc_net_133:15 5.745716e-05 +16 optlc_net_133:16 0.000105698 +17 optlc_net_133:17 0.000105698 +18 optlc_net_133:18 0.0006173477 +19 optlc_net_133:19 0.0006861403 +20 optlc_net_133:20 6.879258e-05 +21 optlc_net_133:21 0.000412631 +22 optlc_net_133:22 6.732813e-05 +23 optlc_net_133:23 6.732813e-05 +24 optlc_net_133:24 0.0006132536 +25 optlc_net_133:25 5.565914e-05 +26 optlc_net_133:26 5.565914e-05 +27 optlc_net_133:27 8.667517e-05 +28 optlc_net_133:28 8.667517e-05 +29 optlc_net_133:29 0.0001062945 +30 optlc_net_133:30 0.0001062945 +31 optlc_net_133:31 0.001490235 +32 optlc_net_133:32 0.001517663 +33 optlc_net_133:33 0.0001172249 +34 optlc_net_133:34 0.0001446522 +35 optlc_net_133:35 0.0007602418 +36 optlc_net_133:36 0.001010761 +37 optlc_net_133:37 0.001010761 +38 optlc_net_133:38 0.001305142 +39 optlc_net_133:39 0.0005165344 +40 optlc_net_133:40 0.001413504 +41 optlc_net_133:41 0.001463102 +42 optlc_net_133:42 4.959821e-05 +43 optlc_net_133:43 9.32242e-05 +44 optlc_net_133:44 0.0003638591 +45 optlc_net_133:45 0.0005067606 +46 optlc_net_133:46 4.701844e-05 +47 optlc_net_133:39 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001351144 +48 optlc_net_133:35 mux_tree_tapbuf_size10_0_sram[0]:20 0.0001323088 +49 optlc_net_133:38 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001323088 +50 optlc_net_133:38 mux_tree_tapbuf_size10_0_sram[0]:20 0.0001351144 +51 optlc_net_133:37 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002550563 +52 optlc_net_133:36 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002550563 + +*RES +0 optlc_128:HI optlc_net_133:46 0.152 +1 optlc_net_133:23 optlc_net_133:22 0.0004888393 +2 optlc_net_133:24 optlc_net_133:23 0.0045 +3 optlc_net_133:24 optlc_net_133:21 0.006334822 +4 optlc_net_133:22 mux_right_ipin_11\/mux_l2_in_3_:A0 0.152 +5 optlc_net_133:43 optlc_net_133:42 0.00341 +6 optlc_net_133:43 optlc_net_133:26 0.0045 +7 optlc_net_133:42 optlc_net_133:41 4.998412e-05 +8 optlc_net_133:39 optlc_net_133:38 0.01087723 +9 optlc_net_133:40 optlc_net_133:39 0.00341 +10 optlc_net_133:31 optlc_net_133:30 0.0045 +11 optlc_net_133:30 optlc_net_133:29 0.0014375 +12 optlc_net_133:28 optlc_net_133:27 0.0004888393 +13 optlc_net_133:29 optlc_net_133:28 0.0045 +14 optlc_net_133:27 mux_right_ipin_12\/mux_l2_in_3_:A0 0.152 +15 optlc_net_133:20 optlc_net_133:19 0.0007388393 +16 optlc_net_133:21 optlc_net_133:20 0.0045 +17 optlc_net_133:46 optlc_net_133:45 0.0045 +18 optlc_net_133:46 optlc_net_133:13 0.0003772322 +19 optlc_net_133:45 optlc_net_133:44 0.004857143 +20 optlc_net_133:45 optlc_net_133:24 0.003035714 +21 optlc_net_133:34 optlc_net_133:33 0.001354911 +22 optlc_net_133:34 optlc_net_133:32 0.0003035714 +23 optlc_net_133:35 optlc_net_133:34 0.0045 +24 optlc_net_133:19 mux_right_ipin_3\/mux_l2_in_3_:A0 0.152 +25 optlc_net_133:19 optlc_net_133:18 0.008216518 +26 optlc_net_133:9 mux_right_ipin_14\/mux_l2_in_3_:A0 0.152 +27 optlc_net_133:37 optlc_net_133:36 0.01497098 +28 optlc_net_133:38 optlc_net_133:37 0.0045 +29 optlc_net_133:38 optlc_net_133:35 0.01483482 +30 optlc_net_133:36 mux_right_ipin_9\/mux_l2_in_3_:A0 0.152 +31 optlc_net_133:26 optlc_net_133:25 0.0004888393 +32 optlc_net_133:25 mux_right_ipin_8\/mux_l2_in_3_:A0 0.152 +33 optlc_net_133:33 mux_right_ipin_13\/mux_l2_in_3_:A0 0.152 +34 optlc_net_133:18 optlc_net_133:17 0.0045 +35 optlc_net_133:17 optlc_net_133:16 0.001133929 +36 optlc_net_133:15 optlc_net_133:14 0.0001576087 +37 optlc_net_133:16 optlc_net_133:15 0.0045 +38 optlc_net_133:14 mux_right_ipin_6\/mux_l2_in_3_:A0 0.152 +39 optlc_net_133:32 optlc_net_133:31 0.01967411 +40 optlc_net_133:13 optlc_net_133:12 0.0003035715 +41 optlc_net_133:12 optlc_net_133:11 0.003696429 +42 optlc_net_133:11 optlc_net_133:10 0.0002723215 +43 optlc_net_133:10 optlc_net_133:9 0.0001739865 +44 optlc_net_133:44 optlc_net_133:43 0.0008214285 +45 optlc_net_133:41 optlc_net_133:40 0.0031678 + +*END + +*D_NET chany_bottom_in[6] 0.01798978 //LENGTH 142.105 LUMPCC 0.001971309 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 41.860 1.290 +*I mux_right_ipin_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 51.980 58.140 +*I mux_right_ipin_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 59.340 96.220 +*I FTB_7__6:A I *L 0.001776 *C 74.060 104.720 +*N chany_bottom_in[6]:4 *C 74.060 104.720 +*N chany_bottom_in[6]:5 *C 74.060 104.380 +*N chany_bottom_in[6]:6 *C 61.685 104.380 +*N chany_bottom_in[6]:7 *C 61.640 104.335 +*N chany_bottom_in[6]:8 *C 61.640 101.705 +*N chany_bottom_in[6]:9 *C 61.595 101.660 +*N chany_bottom_in[6]:10 *C 58.925 101.660 +*N chany_bottom_in[6]:11 *C 58.880 101.615 +*N chany_bottom_in[6]:12 *C 59.303 96.220 +*N chany_bottom_in[6]:13 *C 58.925 96.220 +*N chany_bottom_in[6]:14 *C 58.880 96.265 +*N chany_bottom_in[6]:15 *C 58.420 96.220 +*N chany_bottom_in[6]:16 *C 58.420 94.225 +*N chany_bottom_in[6]:17 *C 58.375 94.180 +*N chany_bottom_in[6]:18 *C 56.625 94.180 +*N chany_bottom_in[6]:19 *C 56.580 94.135 +*N chany_bottom_in[6]:20 *C 56.580 63.298 +*N chany_bottom_in[6]:21 *C 56.573 63.240 +*N chany_bottom_in[6]:22 *C 52.448 63.240 +*N chany_bottom_in[6]:23 *C 52.440 63.183 +*N chany_bottom_in[6]:24 *C 51.980 58.140 +*N chany_bottom_in[6]:25 *C 51.980 57.800 +*N chany_bottom_in[6]:26 *C 51.980 57.800 +*N chany_bottom_in[6]:27 *C 52.440 57.858 +*N chany_bottom_in[6]:28 *C 52.433 57.800 +*N chany_bottom_in[6]:29 *C 44.180 57.800 +*N chany_bottom_in[6]:30 *C 44.160 57.793 +*N chany_bottom_in[6]:31 *C 44.160 4.088 +*N chany_bottom_in[6]:32 *C 44.140 4.080 +*N chany_bottom_in[6]:33 *C 41.867 4.080 +*N chany_bottom_in[6]:34 *C 41.860 4.022 + +*CAP +0 chany_bottom_in[6] 0.0001785993 +1 mux_right_ipin_5\/mux_l1_in_2_:A1 1e-06 +2 mux_right_ipin_1\/mux_l1_in_2_:A1 1e-06 +3 FTB_7__6:A 1e-06 +4 chany_bottom_in[6]:4 5.435464e-05 +5 chany_bottom_in[6]:5 0.0007589618 +6 chany_bottom_in[6]:6 0.0007322187 +7 chany_bottom_in[6]:7 0.0002030762 +8 chany_bottom_in[6]:8 0.0002030762 +9 chany_bottom_in[6]:9 0.0002543628 +10 chany_bottom_in[6]:10 0.0002543628 +11 chany_bottom_in[6]:11 0.0003223553 +12 chany_bottom_in[6]:12 5.919873e-05 +13 chany_bottom_in[6]:13 5.919873e-05 +14 chany_bottom_in[6]:14 0.0003592852 +15 chany_bottom_in[6]:15 0.000136022 +16 chany_bottom_in[6]:16 9.909207e-05 +17 chany_bottom_in[6]:17 0.0001141112 +18 chany_bottom_in[6]:18 0.0001141112 +19 chany_bottom_in[6]:19 0.001420922 +20 chany_bottom_in[6]:20 0.001420922 +21 chany_bottom_in[6]:21 0.0002840775 +22 chany_bottom_in[6]:22 0.0002840775 +23 chany_bottom_in[6]:23 0.0003344072 +24 chany_bottom_in[6]:24 6.888276e-05 +25 chany_bottom_in[6]:25 7.385132e-05 +26 chany_bottom_in[6]:26 7.258401e-05 +27 chany_bottom_in[6]:27 0.000373399 +28 chany_bottom_in[6]:28 0.0006517981 +29 chany_bottom_in[6]:29 0.0006517981 +30 chany_bottom_in[6]:30 0.002949663 +31 chany_bottom_in[6]:31 0.002949663 +32 chany_bottom_in[6]:32 0.0001992209 +33 chany_bottom_in[6]:33 0.0001992209 +34 chany_bottom_in[6]:34 0.0001785993 +35 chany_bottom_in[6]:14 chany_bottom_in[0]:17 2.585415e-05 +36 chany_bottom_in[6]:16 chany_bottom_in[0]:17 5.691382e-05 +37 chany_bottom_in[6]:19 chany_bottom_in[0]:14 1.678286e-05 +38 chany_bottom_in[6]:19 chany_bottom_in[0]:17 7.12439e-05 +39 chany_bottom_in[6]:19 chany_bottom_in[0]:19 6.606098e-06 +40 chany_bottom_in[6]:19 chany_bottom_in[0]:23 6.134575e-05 +41 chany_bottom_in[6]:19 chany_bottom_in[0]:26 9.565434e-05 +42 chany_bottom_in[6]:20 chany_bottom_in[0]:17 1.678286e-05 +43 chany_bottom_in[6]:20 chany_bottom_in[0]:18 7.12439e-05 +44 chany_bottom_in[6]:20 chany_bottom_in[0]:23 6.606098e-06 +45 chany_bottom_in[6]:20 chany_bottom_in[0]:26 6.134575e-05 +46 chany_bottom_in[6]:20 chany_bottom_in[0]:29 9.565434e-05 +47 chany_bottom_in[6]:11 chany_bottom_in[0]:14 2.585415e-05 +48 chany_bottom_in[6]:28 chany_bottom_in[0]:38 6.456706e-06 +49 chany_bottom_in[6]:29 chany_bottom_in[0]:37 6.456706e-06 +50 chany_bottom_in[6]:15 chany_bottom_in[0]:14 5.691382e-05 +51 chany_bottom_in[6]:30 chany_bottom_in[19]:31 1.644257e-05 +52 chany_bottom_in[6]:30 chany_bottom_in[19]:35 0.000312041 +53 chany_bottom_in[6]:31 chany_bottom_in[19]:32 1.644257e-05 +54 chany_bottom_in[6]:31 chany_bottom_in[19]:36 0.000312041 +55 chany_bottom_in[6]:19 mux_tree_tapbuf_size8_3_sram[0]:6 5.914425e-05 +56 chany_bottom_in[6]:19 mux_tree_tapbuf_size8_3_sram[0]:10 5.949922e-05 +57 chany_bottom_in[6]:20 mux_tree_tapbuf_size8_3_sram[0]:10 5.914425e-05 +58 chany_bottom_in[6]:20 mux_tree_tapbuf_size8_3_sram[0]:9 5.949922e-05 +59 chany_bottom_in[6]:14 ropt_net_153:5 8.06029e-08 +60 chany_bottom_in[6]:17 ropt_net_153:7 6.112989e-05 +61 chany_bottom_in[6]:18 ropt_net_153:6 6.112989e-05 +62 chany_bottom_in[6]:11 ropt_net_153:4 8.06029e-08 +63 chany_bottom_in[6]:6 ropt_net_164:3 8.245882e-05 +64 chany_bottom_in[6]:5 ropt_net_164:4 8.245882e-05 +65 chany_bottom_in[6]:6 ropt_net_185:5 5.400044e-05 +66 chany_bottom_in[6]:5 ropt_net_185:6 5.400044e-05 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:34 0.002439732 +1 chany_bottom_in[6]:12 mux_right_ipin_1\/mux_l1_in_2_:A1 0.152 +2 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.0003370536 +3 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.0045 +4 chany_bottom_in[6]:14 chany_bottom_in[6]:11 0.004776786 +5 chany_bottom_in[6]:17 chany_bottom_in[6]:16 0.0045 +6 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.00178125 +7 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.0015625 +8 chany_bottom_in[6]:19 chany_bottom_in[6]:18 0.0045 +9 chany_bottom_in[6]:20 chany_bottom_in[6]:19 0.02753348 +10 chany_bottom_in[6]:21 chany_bottom_in[6]:20 0.00341 +11 chany_bottom_in[6]:23 chany_bottom_in[6]:22 0.00341 +12 chany_bottom_in[6]:22 chany_bottom_in[6]:21 0.00064625 +13 chany_bottom_in[6]:25 chany_bottom_in[6]:24 0.0001465518 +14 chany_bottom_in[6]:26 chany_bottom_in[6]:25 0.0045 +15 chany_bottom_in[6]:24 mux_right_ipin_5\/mux_l1_in_2_:A1 0.152 +16 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.002383929 +17 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.0045 +18 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.0045 +19 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.002348214 +20 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.01104911 +21 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.0045 +22 chany_bottom_in[6]:4 FTB_7__6:A 0.152 +23 chany_bottom_in[6]:27 chany_bottom_in[6]:26 0.0004107143 +24 chany_bottom_in[6]:27 chany_bottom_in[6]:23 0.004754465 +25 chany_bottom_in[6]:28 chany_bottom_in[6]:27 0.00341 +26 chany_bottom_in[6]:29 chany_bottom_in[6]:28 0.001292892 +27 chany_bottom_in[6]:30 chany_bottom_in[6]:29 0.00341 +28 chany_bottom_in[6]:32 chany_bottom_in[6]:31 0.00341 +29 chany_bottom_in[6]:31 chany_bottom_in[6]:30 0.008413782 +30 chany_bottom_in[6]:34 chany_bottom_in[6]:33 0.00341 +31 chany_bottom_in[6]:33 chany_bottom_in[6]:32 0.0003560249 +32 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.0003035715 +33 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.0004107143 + +*END + +*D_NET chany_top_in[2] 0.02789679 //LENGTH 214.915 LUMPCC 0.002848687 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 23.920 107.510 +*I mux_right_ipin_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 45.715 66.300 +*I mux_left_ipin_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 50.315 42.840 +*I mux_right_ipin_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 51.695 26.180 +*I mux_right_ipin_13\/mux_l1_in_1_:A0 I *L 0.001631 *C 53.190 11.900 +*I BUFT_P_101:A I *L 0.001776 *C 59.800 4.080 +*I mux_right_ipin_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 24.745 63.580 +*I mux_right_ipin_11\/mux_l2_in_1_:A1 I *L 0.00198 *C 25.205 56.100 +*I mux_right_ipin_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 53.650 86.360 +*I mux_right_ipin_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 65.225 88.740 +*I mux_right_ipin_15\/mux_l2_in_1_:A1 I *L 0.00198 *C 68.080 85.340 +*N chany_top_in[2]:11 *C 68.080 85.340 +*N chany_top_in[2]:12 *C 68.050 85.370 +*N chany_top_in[2]:13 *C 68.035 85.680 +*N chany_top_in[2]:14 *C 65.263 88.740 +*N chany_top_in[2]:15 *C 66.195 88.740 +*N chany_top_in[2]:16 *C 66.240 88.695 +*N chany_top_in[2]:17 *C 66.240 85.680 +*N chany_top_in[2]:18 *C 66.233 85.680 +*N chany_top_in[2]:19 *C 53.613 86.360 +*N chany_top_in[2]:20 *C 52.025 86.360 +*N chany_top_in[2]:21 *C 51.980 86.315 +*N chany_top_in[2]:22 *C 51.980 85.045 +*N chany_top_in[2]:23 *C 51.935 85.000 +*N chany_top_in[2]:24 *C 25.205 56.100 +*N chany_top_in[2]:25 *C 25.300 56.145 +*N chany_top_in[2]:26 *C 24.783 63.580 +*N chany_top_in[2]:27 *C 25.255 63.580 +*N chany_top_in[2]:28 *C 25.300 63.580 +*N chany_top_in[2]:29 *C 25.300 63.183 +*N chany_top_in[2]:30 *C 25.308 63.240 +*N chany_top_in[2]:31 *C 59.763 4.080 +*N chany_top_in[2]:32 *C 57.040 4.080 +*N chany_top_in[2]:33 *C 57.040 4.420 +*N chany_top_in[2]:34 *C 54.325 4.420 +*N chany_top_in[2]:35 *C 54.280 4.465 +*N chany_top_in[2]:36 *C 53.227 11.900 +*N chany_top_in[2]:37 *C 54.235 11.900 +*N chany_top_in[2]:38 *C 54.280 11.900 +*N chany_top_in[2]:39 *C 54.280 26.135 +*N chany_top_in[2]:40 *C 54.235 26.180 +*N chany_top_in[2]:41 *C 51.695 26.180 +*N chany_top_in[2]:42 *C 51.105 26.180 +*N chany_top_in[2]:43 *C 51.060 26.225 +*N chany_top_in[2]:44 *C 51.060 42.840 +*N chany_top_in[2]:45 *C 50.315 42.840 +*N chany_top_in[2]:46 *C 50.600 42.840 +*N chany_top_in[2]:47 *C 50.600 42.840 +*N chany_top_in[2]:48 *C 50.600 45.175 +*N chany_top_in[2]:49 *C 50.555 45.220 +*N chany_top_in[2]:50 *C 44.205 45.220 +*N chany_top_in[2]:51 *C 44.160 45.265 +*N chany_top_in[2]:52 *C 44.160 63.183 +*N chany_top_in[2]:53 *C 44.160 63.240 +*N chany_top_in[2]:54 *C 45.532 63.240 +*N chany_top_in[2]:55 *C 45.540 63.298 +*N chany_top_in[2]:56 *C 45.715 66.300 +*N chany_top_in[2]:57 *C 45.540 66.300 +*N chany_top_in[2]:58 *C 45.540 66.300 +*N chany_top_in[2]:59 *C 45.540 84.955 +*N chany_top_in[2]:60 *C 45.585 85.000 +*N chany_top_in[2]:61 *C 51.060 85.000 +*N chany_top_in[2]:62 *C 51.060 85.045 +*N chany_top_in[2]:63 *C 51.060 85.623 +*N chany_top_in[2]:64 *C 51.060 85.680 +*N chany_top_in[2]:65 *C 46.940 85.680 +*N chany_top_in[2]:66 *C 46.920 85.688 +*N chany_top_in[2]:67 *C 46.920 101.993 +*N chany_top_in[2]:68 *C 46.900 102.000 +*N chany_top_in[2]:69 *C 23.928 102.000 +*N chany_top_in[2]:70 *C 23.920 102.058 + +*CAP +0 chany_top_in[2] 0.0003182386 +1 mux_right_ipin_5\/mux_l1_in_1_:A0 1e-06 +2 mux_left_ipin_0\/mux_l1_in_1_:A0 1e-06 +3 mux_right_ipin_9\/mux_l1_in_1_:A0 1e-06 +4 mux_right_ipin_13\/mux_l1_in_1_:A0 1e-06 +5 BUFT_P_101:A 1e-06 +6 mux_right_ipin_3\/mux_l2_in_1_:A1 1e-06 +7 mux_right_ipin_11\/mux_l2_in_1_:A1 1e-06 +8 mux_right_ipin_1\/mux_l1_in_1_:A0 1e-06 +9 mux_right_ipin_7\/mux_l2_in_1_:A1 1e-06 +10 mux_right_ipin_15\/mux_l2_in_1_:A1 1e-06 +11 chany_top_in[2]:11 3.274445e-05 +12 chany_top_in[2]:12 3.131042e-05 +13 chany_top_in[2]:13 0.0001311993 +14 chany_top_in[2]:14 0.0001182 +15 chany_top_in[2]:15 0.0001182 +16 chany_top_in[2]:16 0.0002015703 +17 chany_top_in[2]:17 0.0003014592 +18 chany_top_in[2]:18 0.0008874834 +19 chany_top_in[2]:19 0.0001092736 +20 chany_top_in[2]:20 0.0001092736 +21 chany_top_in[2]:21 5.581427e-05 +22 chany_top_in[2]:22 5.581427e-05 +23 chany_top_in[2]:23 7.205325e-05 +24 chany_top_in[2]:24 2.739755e-05 +25 chany_top_in[2]:25 0.0004503194 +26 chany_top_in[2]:26 5.685908e-05 +27 chany_top_in[2]:27 5.685908e-05 +28 chany_top_in[2]:28 5.10461e-05 +29 chany_top_in[2]:29 0.0004704201 +30 chany_top_in[2]:30 0.001441341 +31 chany_top_in[2]:31 0.000240075 +32 chany_top_in[2]:32 0.0002655152 +33 chany_top_in[2]:33 0.0002286841 +34 chany_top_in[2]:34 0.0002032439 +35 chany_top_in[2]:35 0.0003618149 +36 chany_top_in[2]:36 5.409163e-05 +37 chany_top_in[2]:37 5.409163e-05 +38 chany_top_in[2]:38 0.001052502 +39 chany_top_in[2]:39 0.0006592609 +40 chany_top_in[2]:40 0.0001896202 +41 chany_top_in[2]:41 0.0002779287 +42 chany_top_in[2]:42 5.838604e-05 +43 chany_top_in[2]:43 0.0005885231 +44 chany_top_in[2]:44 0.0006212231 +45 chany_top_in[2]:45 6.226149e-05 +46 chany_top_in[2]:46 5.96112e-05 +47 chany_top_in[2]:47 0.0001646415 +48 chany_top_in[2]:48 0.0001319415 +49 chany_top_in[2]:49 0.0003727854 +50 chany_top_in[2]:50 0.0003727854 +51 chany_top_in[2]:51 0.00102934 +52 chany_top_in[2]:52 0.00102934 +53 chany_top_in[2]:53 0.001557487 +54 chany_top_in[2]:54 0.000116146 +55 chany_top_in[2]:55 0.0001781927 +56 chany_top_in[2]:56 5.039799e-05 +57 chany_top_in[2]:57 5.446458e-05 +58 chany_top_in[2]:58 0.001101299 +59 chany_top_in[2]:59 0.0008941572 +60 chany_top_in[2]:60 0.0003772273 +61 chany_top_in[2]:61 0.0004816441 +62 chany_top_in[2]:62 3.602735e-05 +63 chany_top_in[2]:63 3.602735e-05 +64 chany_top_in[2]:64 0.001126545 +65 chany_top_in[2]:65 0.0002390621 +66 chany_top_in[2]:66 0.0009157243 +67 chany_top_in[2]:67 0.0009157243 +68 chany_top_in[2]:68 0.001732596 +69 chany_top_in[2]:69 0.001732596 +70 chany_top_in[2]:70 0.0003182386 +71 chany_top_in[2]:35 chany_top_in[6]:11 4.518768e-06 +72 chany_top_in[2]:22 chany_top_in[6]:14 4.483757e-05 +73 chany_top_in[2]:21 chany_top_in[6]:15 4.483757e-05 +74 chany_top_in[2]:39 chany_top_in[6]:14 5.752563e-06 +75 chany_top_in[2]:63 chany_top_in[6]:15 2.729009e-05 +76 chany_top_in[2]:62 chany_top_in[6]:14 2.729009e-05 +77 chany_top_in[2]:48 chany_top_in[6]:14 1.752763e-05 +78 chany_top_in[2]:43 chany_top_in[6]:11 0.0004620464 +79 chany_top_in[2]:38 chany_top_in[6]:14 4.518768e-06 +80 chany_top_in[2]:38 chany_top_in[6]:11 5.752563e-06 +81 chany_top_in[2]:47 chany_top_in[6]:11 1.752763e-05 +82 chany_top_in[2]:44 chany_top_in[6]:14 0.0004620464 +83 chany_top_in[2]:65 prog_clk[0]:345 4.284642e-05 +84 chany_top_in[2]:18 prog_clk[0]:325 1.836438e-05 +85 chany_top_in[2]:18 prog_clk[0]:330 5.0402e-05 +86 chany_top_in[2]:59 prog_clk[0]:339 3.352031e-05 +87 chany_top_in[2]:59 prog_clk[0]:344 2.415534e-05 +88 chany_top_in[2]:59 prog_clk[0]:341 1.680511e-06 +89 chany_top_in[2]:39 prog_clk[0]:211 0.000150441 +90 chany_top_in[2]:64 prog_clk[0]:345 5.0402e-05 +91 chany_top_in[2]:64 prog_clk[0]:330 6.12108e-05 +92 chany_top_in[2]:38 prog_clk[0]:210 0.000150441 +93 chany_top_in[2]:58 prog_clk[0]:339 1.680511e-06 +94 chany_top_in[2]:58 prog_clk[0]:341 2.415534e-05 +95 chany_top_in[2]:58 prog_clk[0]:336 3.352031e-05 +96 chany_top_in[2]:59 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0002268559 +97 chany_top_in[2]:58 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0002268559 +98 chany_top_in[2]:23 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.759237e-06 +99 chany_top_in[2]:22 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.768143e-05 +100 chany_top_in[2]:20 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.897156e-05 +101 chany_top_in[2]:21 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.768143e-05 +102 chany_top_in[2]:19 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.897156e-05 +103 chany_top_in[2]:61 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.759237e-06 +104 chany_top_in[2]:37 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.123283e-05 +105 chany_top_in[2]:36 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.123283e-05 +106 chany_top_in[2]:29 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.518231e-05 +107 chany_top_in[2]:29 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.46667e-06 +108 chany_top_in[2]:28 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.46667e-06 +109 chany_top_in[2]:25 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.518231e-05 +110 chany_top_in[2]:35 ropt_net_181:4 2.478509e-05 +111 chany_top_in[2]:35 ropt_net_181:7 7.461484e-05 +112 chany_top_in[2]:38 ropt_net_181:3 2.478509e-05 +113 chany_top_in[2]:38 ropt_net_181:8 7.461484e-05 +114 chany_top_in[2]:34 ropt_net_176:2 6.141046e-05 +115 chany_top_in[2]:33 ropt_net_176:3 6.141046e-05 + +*RES +0 chany_top_in[2] chany_top_in[2]:70 0.004868304 +1 chany_top_in[2]:29 chany_top_in[2]:28 0.0001911058 +2 chany_top_in[2]:29 chany_top_in[2]:25 0.006283483 +3 chany_top_in[2]:30 chany_top_in[2]:29 0.00341 +4 chany_top_in[2]:31 BUFT_P_101:A 0.152 +5 chany_top_in[2]:34 chany_top_in[2]:33 0.002424107 +6 chany_top_in[2]:35 chany_top_in[2]:34 0.0045 +7 chany_top_in[2]:23 chany_top_in[2]:22 0.0045 +8 chany_top_in[2]:22 chany_top_in[2]:21 0.001133929 +9 chany_top_in[2]:20 chany_top_in[2]:19 0.001417411 +10 chany_top_in[2]:21 chany_top_in[2]:20 0.0045 +11 chany_top_in[2]:19 mux_right_ipin_1\/mux_l1_in_1_:A0 0.152 +12 chany_top_in[2]:65 chany_top_in[2]:64 0.0006454666 +13 chany_top_in[2]:66 chany_top_in[2]:65 0.00341 +14 chany_top_in[2]:68 chany_top_in[2]:67 0.00341 +15 chany_top_in[2]:67 chany_top_in[2]:66 0.00255445 +16 chany_top_in[2]:70 chany_top_in[2]:69 0.00341 +17 chany_top_in[2]:69 chany_top_in[2]:68 0.003599025 +18 chany_top_in[2]:17 chany_top_in[2]:16 0.002691965 +19 chany_top_in[2]:17 chany_top_in[2]:13 0.001602679 +20 chany_top_in[2]:18 chany_top_in[2]:17 0.00341 +21 chany_top_in[2]:60 chany_top_in[2]:59 0.0045 +22 chany_top_in[2]:59 chany_top_in[2]:58 0.01665625 +23 chany_top_in[2]:40 chany_top_in[2]:39 0.0045 +24 chany_top_in[2]:39 chany_top_in[2]:38 0.01270982 +25 chany_top_in[2]:55 chany_top_in[2]:54 0.00341 +26 chany_top_in[2]:54 chany_top_in[2]:53 0.000215025 +27 chany_top_in[2]:63 chany_top_in[2]:62 0.000515625 +28 chany_top_in[2]:64 chany_top_in[2]:63 0.00341 +29 chany_top_in[2]:64 chany_top_in[2]:18 0.002377025 +30 chany_top_in[2]:61 chany_top_in[2]:60 0.004888393 +31 chany_top_in[2]:61 chany_top_in[2]:23 0.00078125 +32 chany_top_in[2]:62 chany_top_in[2]:61 0.0045 +33 chany_top_in[2]:52 chany_top_in[2]:51 0.01599777 +34 chany_top_in[2]:53 chany_top_in[2]:52 0.00341 +35 chany_top_in[2]:53 chany_top_in[2]:30 0.002953558 +36 chany_top_in[2]:50 chany_top_in[2]:49 0.005669643 +37 chany_top_in[2]:51 chany_top_in[2]:50 0.0045 +38 chany_top_in[2]:49 chany_top_in[2]:48 0.0045 +39 chany_top_in[2]:48 chany_top_in[2]:47 0.002084821 +40 chany_top_in[2]:15 chany_top_in[2]:14 0.0008325893 +41 chany_top_in[2]:16 chany_top_in[2]:15 0.0045 +42 chany_top_in[2]:14 mux_right_ipin_7\/mux_l2_in_1_:A1 0.152 +43 chany_top_in[2]:42 chany_top_in[2]:41 0.0005267857 +44 chany_top_in[2]:43 chany_top_in[2]:42 0.0045 +45 chany_top_in[2]:11 mux_right_ipin_15\/mux_l2_in_1_:A1 0.152 +46 chany_top_in[2]:12 chany_top_in[2]:11 0.0045 +47 chany_top_in[2]:27 chany_top_in[2]:26 0.0004218751 +48 chany_top_in[2]:28 chany_top_in[2]:27 0.0045 +49 chany_top_in[2]:26 mux_right_ipin_3\/mux_l2_in_1_:A1 0.152 +50 chany_top_in[2]:41 mux_right_ipin_9\/mux_l1_in_1_:A0 0.152 +51 chany_top_in[2]:41 chany_top_in[2]:40 0.002267857 +52 chany_top_in[2]:24 mux_right_ipin_11\/mux_l2_in_1_:A1 0.152 +53 chany_top_in[2]:25 chany_top_in[2]:24 0.0045 +54 chany_top_in[2]:37 chany_top_in[2]:36 0.0008995536 +55 chany_top_in[2]:38 chany_top_in[2]:37 0.0045 +56 chany_top_in[2]:38 chany_top_in[2]:35 0.006638393 +57 chany_top_in[2]:36 mux_right_ipin_13\/mux_l1_in_1_:A0 0.152 +58 chany_top_in[2]:57 chany_top_in[2]:56 9.51087e-05 +59 chany_top_in[2]:58 chany_top_in[2]:57 0.0045 +60 chany_top_in[2]:58 chany_top_in[2]:55 0.002680804 +61 chany_top_in[2]:56 mux_right_ipin_5\/mux_l1_in_1_:A0 0.152 +62 chany_top_in[2]:46 chany_top_in[2]:45 0.0001548913 +63 chany_top_in[2]:47 chany_top_in[2]:46 0.0045 +64 chany_top_in[2]:47 chany_top_in[2]:44 0.0004107143 +65 chany_top_in[2]:45 mux_left_ipin_0\/mux_l1_in_1_:A0 0.152 +66 chany_top_in[2]:33 chany_top_in[2]:32 0.0003035715 +67 chany_top_in[2]:32 chany_top_in[2]:31 0.002430804 +68 chany_top_in[2]:44 chany_top_in[2]:43 0.01483482 +69 chany_top_in[2]:13 chany_top_in[2]:12 0.00019375 + +*END + +*D_NET chany_top_in[8] 0.01791517 //LENGTH 120.762 LUMPCC 0.00816175 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 34.960 107.475 +*I mux_right_ipin_11\/mux_l2_in_2_:A1 I *L 0.00198 *C 30.265 56.100 +*I mux_right_ipin_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 23.460 61.540 +*I mux_right_ipin_13\/mux_l1_in_2_:A0 I *L 0.001631 *C 37.895 21.080 +*I FTB_29__28:A I *L 0.001776 *C 37.720 12.240 +*N chany_top_in[8]:5 *C 34.560 102.680 +*N chany_top_in[8]:6 *C 37.320 21.080 +*N chany_top_in[8]:7 *C 37.720 12.240 +*N chany_top_in[8]:8 *C 37.720 12.285 +*N chany_top_in[8]:9 *C 37.895 21.080 +*N chany_top_in[8]:10 *C 37.720 21.080 +*N chany_top_in[8]:11 *C 37.720 21.080 +*N chany_top_in[8]:12 *C 37.720 21.080 +*N chany_top_in[8]:13 *C 37.720 21.088 +*N chany_top_in[8]:14 *C 37.720 57.793 +*N chany_top_in[8]:15 *C 37.700 57.800 +*N chany_top_in[8]:16 *C 23.498 61.540 +*N chany_top_in[8]:17 *C 23.875 61.540 +*N chany_top_in[8]:18 *C 23.920 61.495 +*N chany_top_in[8]:19 *C 23.920 57.858 +*N chany_top_in[8]:20 *C 23.928 57.800 +*N chany_top_in[8]:21 *C 30.303 56.100 +*N chany_top_in[8]:22 *C 31.695 56.100 +*N chany_top_in[8]:23 *C 31.740 56.145 +*N chany_top_in[8]:24 *C 31.740 57.742 +*N chany_top_in[8]:25 *C 31.740 57.800 +*N chany_top_in[8]:26 *C 34.960 57.800 +*N chany_top_in[8]:27 *C 34.960 57.808 +*N chany_top_in[8]:28 *C 34.960 102.672 +*N chany_top_in[8]:29 *C 34.960 102.680 +*N chany_top_in[8]:30 *C 34.960 102.738 + +*CAP +0 chany_top_in[8] 0.0003228073 +1 mux_right_ipin_11\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_3\/mux_l2_in_2_:A1 1e-06 +3 mux_right_ipin_13\/mux_l1_in_2_:A0 1e-06 +4 FTB_29__28:A 1e-06 +5 chany_top_in[8]:5 0.0001018947 +6 chany_top_in[8]:6 0.0001026912 +7 chany_top_in[8]:7 3.736086e-05 +8 chany_top_in[8]:8 0.0004328353 +9 chany_top_in[8]:9 5.519135e-05 +10 chany_top_in[8]:10 5.781951e-05 +11 chany_top_in[8]:11 0.0004692418 +12 chany_top_in[8]:12 0.0001026912 +13 chany_top_in[8]:13 0.0009697726 +14 chany_top_in[8]:14 0.0009697725 +15 chany_top_in[8]:15 0.0002410297 +16 chany_top_in[8]:16 6.834425e-05 +17 chany_top_in[8]:17 6.834425e-05 +18 chany_top_in[8]:18 0.0001818665 +19 chany_top_in[8]:19 0.0001818665 +20 chany_top_in[8]:20 0.0004631018 +21 chany_top_in[8]:21 0.0001507324 +22 chany_top_in[8]:22 0.0001507324 +23 chany_top_in[8]:23 0.0001532677 +24 chany_top_in[8]:24 0.0001532677 +25 chany_top_in[8]:25 0.0007088223 +26 chany_top_in[8]:26 0.0004867502 +27 chany_top_in[8]:27 0.001347259 +28 chany_top_in[8]:28 0.001347259 +29 chany_top_in[8]:29 0.0001018947 +30 chany_top_in[8]:30 0.0003228073 +31 chany_top_in[8]:27 chany_bottom_in[13]:14 0.0005090503 +32 chany_top_in[8]:28 chany_bottom_in[13]:13 0.0005090503 +33 chany_top_in[8]:13 chany_bottom_in[14]:27 3.171069e-05 +34 chany_top_in[8]:13 chany_bottom_in[14]:28 0.0004572163 +35 chany_top_in[8]:14 chany_bottom_in[14]:20 0.0004572163 +36 chany_top_in[8]:14 chany_bottom_in[14]:28 3.171069e-05 +37 chany_top_in[8]:15 chany_bottom_in[16]:38 5.750371e-05 +38 chany_top_in[8]:19 chany_bottom_in[16]:31 3.70874e-05 +39 chany_top_in[8]:20 chany_bottom_in[16]:32 0.0001338261 +40 chany_top_in[8]:20 chany_bottom_in[16]:37 1.630031e-05 +41 chany_top_in[8]:18 chany_bottom_in[16]:30 3.70874e-05 +42 chany_top_in[8]:25 chany_bottom_in[16]:37 0.000190182 +43 chany_top_in[8]:25 chany_bottom_in[16]:38 1.630031e-05 +44 chany_top_in[8]:22 chany_bottom_in[16]:34 1.007333e-06 +45 chany_top_in[8]:21 chany_bottom_in[16]:33 1.007333e-06 +46 chany_top_in[8]:26 chany_bottom_in[16]:37 5.750371e-05 +47 chany_top_in[8]:26 chany_bottom_in[16]:38 5.635593e-05 +48 chany_top_in[8]:11 chany_top_in[5]:7 7.783386e-05 +49 chany_top_in[8]:13 chany_top_in[5]:10 0.0007244161 +50 chany_top_in[8]:14 chany_top_in[5]:20 0.0007244161 +51 chany_top_in[8]:8 chany_top_in[5]:6 7.783386e-05 +52 chany_top_in[8]:27 chany_top_in[5]:10 0.0005901544 +53 chany_top_in[8]:27 chany_top_in[5]:20 0.001388412 +54 chany_top_in[8]:28 chany_top_in[5]:20 0.0005901544 +55 chany_top_in[8]:28 chany_top_in[5]:21 0.001388412 + +*RES +0 chany_top_in[8] chany_top_in[8]:30 0.004229911 +1 chany_top_in[8]:11 chany_top_in[8]:10 0.0045 +2 chany_top_in[8]:11 chany_top_in[8]:8 0.007852679 +3 chany_top_in[8]:12 chany_top_in[8]:11 0.00341 +4 chany_top_in[8]:12 chany_top_in[8]:6 5.696969e-05 +5 chany_top_in[8]:13 chany_top_in[8]:12 0.00341 +6 chany_top_in[8]:15 chany_top_in[8]:14 0.00341 +7 chany_top_in[8]:14 chany_top_in[8]:13 0.00575045 +8 chany_top_in[8]:19 chany_top_in[8]:18 0.003247768 +9 chany_top_in[8]:20 chany_top_in[8]:19 0.00341 +10 chany_top_in[8]:17 chany_top_in[8]:16 0.0003370536 +11 chany_top_in[8]:18 chany_top_in[8]:17 0.0045 +12 chany_top_in[8]:16 mux_right_ipin_3\/mux_l2_in_2_:A1 0.152 +13 chany_top_in[8]:24 chany_top_in[8]:23 0.001426339 +14 chany_top_in[8]:25 chany_top_in[8]:24 0.00341 +15 chany_top_in[8]:25 chany_top_in[8]:20 0.001223958 +16 chany_top_in[8]:22 chany_top_in[8]:21 0.001243304 +17 chany_top_in[8]:23 chany_top_in[8]:22 0.0045 +18 chany_top_in[8]:21 mux_right_ipin_11\/mux_l2_in_2_:A1 0.152 +19 chany_top_in[8]:7 FTB_29__28:A 0.152 +20 chany_top_in[8]:8 chany_top_in[8]:7 0.0045 +21 chany_top_in[8]:10 chany_top_in[8]:9 9.51087e-05 +22 chany_top_in[8]:9 mux_right_ipin_13\/mux_l1_in_2_:A0 0.152 +23 chany_top_in[8]:26 chany_top_in[8]:25 0.0005044666 +24 chany_top_in[8]:26 chany_top_in[8]:15 0.0004292666 +25 chany_top_in[8]:27 chany_top_in[8]:26 0.00341 +26 chany_top_in[8]:29 chany_top_in[8]:28 0.00341 +27 chany_top_in[8]:29 chany_top_in[8]:5 5.69697e-05 +28 chany_top_in[8]:28 chany_top_in[8]:27 0.007028849 +29 chany_top_in[8]:30 chany_top_in[8]:29 0.00341 + +*END + +*D_NET chany_top_in[14] 0.01870793 //LENGTH 151.860 LUMPCC 0.00485331 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 69.000 107.510 +*I mux_right_ipin_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 64.765 30.940 +*I mux_right_ipin_13\/mux_l2_in_2_:A1 I *L 0.00198 *C 58.420 18.020 +*I ropt_mt_inst_743:A I *L 0.001767 *C 27.600 4.080 +*N chany_top_in[14]:4 *C 68.290 106.080 +*N chany_top_in[14]:5 *C 27.638 4.080 +*N chany_top_in[14]:6 *C 30.820 4.080 +*N chany_top_in[14]:7 *C 30.820 3.400 +*N chany_top_in[14]:8 *C 37.215 3.400 +*N chany_top_in[14]:9 *C 37.260 3.445 +*N chany_top_in[14]:10 *C 37.260 8.795 +*N chany_top_in[14]:11 *C 37.305 8.840 +*N chany_top_in[14]:12 *C 43.655 8.840 +*N chany_top_in[14]:13 *C 43.700 8.885 +*N chany_top_in[14]:14 *C 43.700 11.503 +*N chany_top_in[14]:15 *C 43.708 11.560 +*N chany_top_in[14]:16 *C 57.953 11.560 +*N chany_top_in[14]:17 *C 57.960 11.617 +*N chany_top_in[14]:18 *C 58.383 18.020 +*N chany_top_in[14]:19 *C 58.005 18.020 +*N chany_top_in[14]:20 *C 57.960 18.020 +*N chany_top_in[14]:21 *C 57.960 30.555 +*N chany_top_in[14]:22 *C 58.005 30.600 +*N chany_top_in[14]:23 *C 64.860 30.600 +*N chany_top_in[14]:24 *C 64.765 30.940 +*N chany_top_in[14]:25 *C 64.860 30.985 +*N chany_top_in[14]:26 *C 64.860 43.462 +*N chany_top_in[14]:27 *C 64.868 43.520 +*N chany_top_in[14]:28 *C 68.980 43.520 +*N chany_top_in[14]:29 *C 69.000 43.528 +*N chany_top_in[14]:30 *C 69.000 93.355 +*N chany_top_in[14]:31 *C 69.000 106.073 +*N chany_top_in[14]:32 *C 68.998 106.080 +*N chany_top_in[14]:33 *C 69.000 106.138 + +*CAP +0 chany_top_in[14] 9.489644e-05 +1 mux_right_ipin_9\/mux_l2_in_3_:A1 1e-06 +2 mux_right_ipin_13\/mux_l2_in_2_:A1 1e-06 +3 ropt_mt_inst_743:A 1e-06 +4 chany_top_in[14]:4 0.0001239532 +5 chany_top_in[14]:5 0.0001591835 +6 chany_top_in[14]:6 0.0002021223 +7 chany_top_in[14]:7 0.0005104003 +8 chany_top_in[14]:8 0.0004674616 +9 chany_top_in[14]:9 0.0001948838 +10 chany_top_in[14]:10 0.0001948838 +11 chany_top_in[14]:11 0.0003622969 +12 chany_top_in[14]:12 0.0003622969 +13 chany_top_in[14]:13 0.0001974326 +14 chany_top_in[14]:14 0.0001974326 +15 chany_top_in[14]:15 0.0008430628 +16 chany_top_in[14]:16 0.0008430628 +17 chany_top_in[14]:17 0.0003212923 +18 chany_top_in[14]:18 6.357887e-05 +19 chany_top_in[14]:19 6.357887e-05 +20 chany_top_in[14]:20 0.0008967388 +21 chany_top_in[14]:21 0.000543462 +22 chany_top_in[14]:22 0.0004634712 +23 chany_top_in[14]:23 0.0004894139 +24 chany_top_in[14]:24 5.247515e-05 +25 chany_top_in[14]:25 0.0004300051 +26 chany_top_in[14]:26 0.0004300051 +27 chany_top_in[14]:27 0.000246328 +28 chany_top_in[14]:28 0.000246328 +29 chany_top_in[14]:29 0.001666426 +30 chany_top_in[14]:30 0.002316363 +31 chany_top_in[14]:31 0.0006499377 +32 chany_top_in[14]:32 0.0001239532 +33 chany_top_in[14]:33 9.489644e-05 +34 chany_top_in[14]:17 chany_bottom_in[0]:52 2.805253e-05 +35 chany_top_in[14]:17 chany_bottom_in[0]:53 8.110117e-06 +36 chany_top_in[14]:16 chany_bottom_in[0]:54 0.000171337 +37 chany_top_in[14]:15 chany_bottom_in[0]:55 0.000171337 +38 chany_top_in[14]:21 chany_bottom_in[0]:42 0.0002011271 +39 chany_top_in[14]:21 chany_bottom_in[0]:47 2.372772e-05 +40 chany_top_in[14]:20 chany_bottom_in[0]:43 0.0002011271 +41 chany_top_in[14]:20 chany_bottom_in[0]:47 2.805253e-05 +42 chany_top_in[14]:20 chany_bottom_in[0]:52 3.183783e-05 +43 chany_top_in[14]:25 chany_bottom_in[18]:24 0.000350178 +44 chany_top_in[14]:26 chany_bottom_in[18]:23 0.000350178 +45 chany_top_in[14]:12 chany_top_in[16]:18 4.429248e-06 +46 chany_top_in[14]:12 chany_top_in[16]:20 0.0001213294 +47 chany_top_in[14]:11 chany_top_in[16]:21 0.0001213294 +48 chany_top_in[14]:11 chany_top_in[16]:19 4.429248e-06 +49 chany_top_in[14]:8 chany_top_in[16]:24 1.210183e-05 +50 chany_top_in[14]:5 chany_top_in[16]:25 0.0001257748 +51 chany_top_in[14]:6 chany_top_in[16]:24 0.0001257748 +52 chany_top_in[14]:7 chany_top_in[16]:25 1.210183e-05 +53 chany_top_in[14]:25 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 5.249433e-06 +54 chany_top_in[14]:26 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 5.249433e-06 +55 chany_top_in[14]:27 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 1.437937e-05 +56 chany_top_in[14]:28 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 1.437937e-05 +57 chany_top_in[14]:29 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.001118587 +58 chany_top_in[14]:31 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 1.480691e-05 +59 chany_top_in[14]:30 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.001118587 +60 chany_top_in[14]:30 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 1.480691e-05 +61 chany_top_in[14]:12 ropt_net_179:8 5.044957e-07 +62 chany_top_in[14]:11 ropt_net_179:9 5.044957e-07 +63 chany_top_in[14]:10 ropt_net_179:7 5.231713e-05 +64 chany_top_in[14]:9 ropt_net_179:6 5.231713e-05 +65 chany_top_in[14]:12 ropt_net_142:11 3.546241e-05 +66 chany_top_in[14]:11 ropt_net_142:10 3.546241e-05 +67 chany_top_in[14]:10 ropt_net_142:9 0.0001391803 +68 chany_top_in[14]:9 ropt_net_142:8 0.0001391803 + +*RES +0 chany_top_in[14] chany_top_in[14]:33 0.001225446 +1 chany_top_in[14]:17 chany_top_in[14]:16 0.00341 +2 chany_top_in[14]:16 chany_top_in[14]:15 0.002231717 +3 chany_top_in[14]:14 chany_top_in[14]:13 0.002337053 +4 chany_top_in[14]:15 chany_top_in[14]:14 0.00341 +5 chany_top_in[14]:12 chany_top_in[14]:11 0.005669643 +6 chany_top_in[14]:13 chany_top_in[14]:12 0.0045 +7 chany_top_in[14]:11 chany_top_in[14]:10 0.0045 +8 chany_top_in[14]:10 chany_top_in[14]:9 0.004776786 +9 chany_top_in[14]:8 chany_top_in[14]:7 0.005709822 +10 chany_top_in[14]:9 chany_top_in[14]:8 0.0045 +11 chany_top_in[14]:5 ropt_mt_inst_743:A 0.152 +12 chany_top_in[14]:22 chany_top_in[14]:21 0.0045 +13 chany_top_in[14]:21 chany_top_in[14]:20 0.01119196 +14 chany_top_in[14]:24 mux_right_ipin_9\/mux_l2_in_3_:A1 0.152 +15 chany_top_in[14]:24 chany_top_in[14]:23 0.0003035715 +16 chany_top_in[14]:19 chany_top_in[14]:18 0.0003370536 +17 chany_top_in[14]:20 chany_top_in[14]:19 0.0045 +18 chany_top_in[14]:20 chany_top_in[14]:17 0.005716518 +19 chany_top_in[14]:18 mux_right_ipin_13\/mux_l2_in_2_:A1 0.152 +20 chany_top_in[14]:25 chany_top_in[14]:24 0.0045 +21 chany_top_in[14]:26 chany_top_in[14]:25 0.01114062 +22 chany_top_in[14]:27 chany_top_in[14]:26 0.00341 +23 chany_top_in[14]:28 chany_top_in[14]:27 0.0006442916 +24 chany_top_in[14]:29 chany_top_in[14]:28 0.00341 +25 chany_top_in[14]:32 chany_top_in[14]:31 0.00341 +26 chany_top_in[14]:32 chany_top_in[14]:4 0.0001039141 +27 chany_top_in[14]:31 chany_top_in[14]:30 0.001992408 +28 chany_top_in[14]:33 chany_top_in[14]:32 0.00341 +29 chany_top_in[14]:6 chany_top_in[14]:5 0.002841518 +30 chany_top_in[14]:7 chany_top_in[14]:6 0.000607143 +31 chany_top_in[14]:23 chany_top_in[14]:22 0.006120536 +32 chany_top_in[14]:30 chany_top_in[14]:29 0.007806308 + +*END + +*D_NET right_grid_pin_52_[0] 0.001193899 //LENGTH 11.960 LUMPCC 0 DR + +*CONN +*I mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 79.065 72.080 +*P right_grid_pin_52_[0] O *L 0.7423 *C 83.410 78.880 +*N right_grid_pin_52_[0]:2 *C 80.047 78.880 +*N right_grid_pin_52_[0]:3 *C 80.040 78.823 +*N right_grid_pin_52_[0]:4 *C 80.040 72.125 +*N right_grid_pin_52_[0]:5 *C 79.995 72.080 +*N right_grid_pin_52_[0]:6 *C 79.103 72.080 + +*CAP +0 mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 right_grid_pin_52_[0] 0.0001858426 +2 right_grid_pin_52_[0]:2 0.0001858426 +3 right_grid_pin_52_[0]:3 0.0003381925 +4 right_grid_pin_52_[0]:4 0.0003381925 +5 right_grid_pin_52_[0]:5 7.241422e-05 +6 right_grid_pin_52_[0]:6 7.241422e-05 + +*RES +0 mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:X right_grid_pin_52_[0]:6 0.152 +1 right_grid_pin_52_[0]:6 right_grid_pin_52_[0]:5 0.000796875 +2 right_grid_pin_52_[0]:5 right_grid_pin_52_[0]:4 0.0045 +3 right_grid_pin_52_[0]:4 right_grid_pin_52_[0]:3 0.005979911 +4 right_grid_pin_52_[0]:3 right_grid_pin_52_[0]:2 0.00341 +5 right_grid_pin_52_[0]:2 right_grid_pin_52_[0] 0.0005267917 + +*END + +*D_NET left_grid_pin_5_[0] 0.00302738 //LENGTH 26.500 LUMPCC 0.0008614815 DR + +*CONN +*I mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.085 80.580 +*P left_grid_pin_5_[0] O *L 0.7423 *C 1.298 103.360 +*N left_grid_pin_5_[0]:2 *C 1.380 103.360 +*N left_grid_pin_5_[0]:3 *C 1.380 103.360 +*N left_grid_pin_5_[0]:4 *C 2.300 103.360 +*N left_grid_pin_5_[0]:5 *C 2.300 80.580 +*N left_grid_pin_5_[0]:6 *C 2.300 80.580 +*N left_grid_pin_5_[0]:7 *C 4.048 80.580 + +*CAP +0 mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_5_[0] 2.747417e-05 +2 left_grid_pin_5_[0]:2 2.747417e-05 +3 left_grid_pin_5_[0]:3 8.268574e-05 +4 left_grid_pin_5_[0]:4 0.0008891786 +5 left_grid_pin_5_[0]:5 0.000875722 +6 left_grid_pin_5_[0]:6 0.000148677 +7 left_grid_pin_5_[0]:7 0.0001136863 +8 left_grid_pin_5_[0]:5 left_grid_pin_4_[0] 1.471442e-05 +9 left_grid_pin_5_[0]:5 left_grid_pin_4_[0]:5 0.0004146107 +10 left_grid_pin_5_[0]:3 left_grid_pin_4_[0]:3 1.415645e-06 +11 left_grid_pin_5_[0]:4 left_grid_pin_4_[0]:2 1.471442e-05 +12 left_grid_pin_5_[0]:4 left_grid_pin_4_[0]:4 0.0004160263 + +*RES +0 mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_5_[0]:7 0.152 +1 left_grid_pin_5_[0]:7 left_grid_pin_5_[0]:6 0.001560268 +2 left_grid_pin_5_[0]:6 left_grid_pin_5_[0]:5 0.0045 +3 left_grid_pin_5_[0]:5 left_grid_pin_5_[0]:4 0.02033929 +4 left_grid_pin_5_[0]:3 left_grid_pin_5_[0]:2 0.00341 +5 left_grid_pin_5_[0]:2 left_grid_pin_5_[0] 2.35e-05 +6 left_grid_pin_5_[0]:4 left_grid_pin_5_[0]:3 0.0008214285 + +*END + +*D_NET left_grid_pin_11_[0] 0.001348027 //LENGTH 10.780 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 69.700 +*P left_grid_pin_11_[0] O *L 0.7423 *C 1.230 77.520 +*N left_grid_pin_11_[0]:2 *C 3.673 77.520 +*N left_grid_pin_11_[0]:3 *C 3.680 77.463 +*N left_grid_pin_11_[0]:4 *C 3.680 69.745 +*N left_grid_pin_11_[0]:5 *C 3.625 69.700 + +*CAP +0 mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_11_[0] 0.0001634378 +2 left_grid_pin_11_[0]:2 0.0001634378 +3 left_grid_pin_11_[0]:3 0.0004960332 +4 left_grid_pin_11_[0]:4 0.0004960332 +5 left_grid_pin_11_[0]:5 2.808491e-05 + +*RES +0 mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_11_[0]:5 0.152 +1 left_grid_pin_11_[0]:5 left_grid_pin_11_[0]:4 0.0045 +2 left_grid_pin_11_[0]:4 left_grid_pin_11_[0]:3 0.006890625 +3 left_grid_pin_11_[0]:3 left_grid_pin_11_[0]:2 0.00341 +4 left_grid_pin_11_[0]:2 left_grid_pin_11_[0] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.01130064 //LENGTH 87.745 LUMPCC 0.001236402 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.565 22.780 +*I mux_left_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 51.420 41.870 +*I mux_left_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 72.120 47.600 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.795 42.500 +*I mux_left_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 58.320 41.870 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 58.320 41.870 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 58.378 42.160 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 59.340 42.160 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 67.670 42.500 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 72.083 47.600 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 67.665 47.600 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 67.620 47.555 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 67.620 42.545 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 67.575 42.500 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 59.340 42.500 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 51.520 42.500 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 51.420 41.870 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 51.420 41.480 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 47.425 41.480 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 47.380 41.435 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 47.380 22.498 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 47.373 22.440 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 15.648 22.440 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 15.640 22.440 +*N mux_tree_tapbuf_size10_0_sram[0]:24 *C 15.640 22.780 +*N mux_tree_tapbuf_size10_0_sram[0]:25 *C 15.595 22.780 +*N mux_tree_tapbuf_size10_0_sram[0]:26 *C 14.603 22.780 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_ipin_0\/mux_l1_in_1_:S 1e-06 +2 mux_left_ipin_0\/mux_l1_in_2_:S 1e-06 +3 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_ipin_0\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 5.599828e-05 +6 mux_tree_tapbuf_size10_0_sram[0]:6 8.32439e-05 +7 mux_tree_tapbuf_size10_0_sram[0]:7 8.149542e-05 +8 mux_tree_tapbuf_size10_0_sram[0]:8 2.193556e-05 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0003691164 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0003691164 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.0003045922 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0003045922 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0005184957 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.001011927 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0005357971 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0001110058 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0003396501 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0003038868 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0007269598 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.0007269598 +21 mux_tree_tapbuf_size10_0_sram[0]:21 0.001952999 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.001952999 +23 mux_tree_tapbuf_size10_0_sram[0]:23 5.914507e-05 +24 mux_tree_tapbuf_size10_0_sram[0]:24 5.580396e-05 +25 mux_tree_tapbuf_size10_0_sram[0]:25 8.676043e-05 +26 mux_tree_tapbuf_size10_0_sram[0]:26 8.676043e-05 +27 mux_tree_tapbuf_size10_0_sram[0]:21 prog_clk[0]:102 5.667094e-05 +28 mux_tree_tapbuf_size10_0_sram[0]:21 prog_clk[0]:118 7.047364e-05 +29 mux_tree_tapbuf_size10_0_sram[0]:21 prog_clk[0]:212 9.122976e-05 +30 mux_tree_tapbuf_size10_0_sram[0]:21 prog_clk[0]:214 6.78058e-05 +31 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:103 5.667094e-05 +32 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:127 7.047364e-05 +33 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:213 9.122976e-05 +34 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:215 6.78058e-05 +35 mux_tree_tapbuf_size10_0_sram[0]:13 prog_clk[0]:251 1.368649e-05 +36 mux_tree_tapbuf_size10_0_sram[0]:14 prog_clk[0]:252 1.368649e-05 +37 mux_tree_tapbuf_size10_0_sram[0]:15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.091104e-05 +38 mux_tree_tapbuf_size10_0_sram[0]:14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.091104e-05 +39 mux_tree_tapbuf_size10_0_sram[0]:19 optlc_net_133:39 0.0001351144 +40 mux_tree_tapbuf_size10_0_sram[0]:19 optlc_net_133:38 0.0001323088 +41 mux_tree_tapbuf_size10_0_sram[0]:20 optlc_net_133:35 0.0001323088 +42 mux_tree_tapbuf_size10_0_sram[0]:20 optlc_net_133:38 0.0001351144 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.003566965 +2 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.0045 +3 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.01690848 +4 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.00341 +5 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.00341 +6 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.00497025 +7 mux_tree_tapbuf_size10_0_sram[0]:25 mux_tree_tapbuf_size10_0_sram[0]:24 0.0045 +8 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:23 0.0001634615 +9 mux_tree_tapbuf_size10_0_sram[0]:26 mux_tree_tapbuf_size10_0_sram[0]:25 0.0008861608 +10 mux_tree_tapbuf_size10_0_sram[0]:8 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.0045 +12 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:8 8.482143e-05 +13 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:11 0.004473215 +14 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.003944197 +15 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.0045 +16 mux_tree_tapbuf_size10_0_sram[0]:9 mux_left_ipin_0\/mux_l1_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_0_sram[0]:16 mux_left_ipin_0\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.0005625 +19 mux_tree_tapbuf_size10_0_sram[0]:5 mux_left_ipin_0\/mux_l1_in_0_:S 0.152 +20 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.000203125 +21 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_0_sram[0]:14 0.006982143 +22 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.007352679 +23 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:7 0.0003035715 +24 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.0001686047 +25 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0008593751 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[0] 0.007501962 //LENGTH 53.960 LUMPCC 0.0007504232 DR + +*CONN +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 27.445 69.360 +*I mux_right_ipin_5\/mux_l1_in_2_:S I *L 0.00357 *C 52.800 58.190 +*I mux_right_ipin_5\/mux_l1_in_0_:S I *L 0.00357 *C 56.220 55.760 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 56.295 49.980 +*I mux_right_ipin_5\/mux_l1_in_1_:S I *L 0.00357 *C 46.820 66.640 +*N mux_tree_tapbuf_size10_4_sram[0]:5 *C 46.820 66.640 +*N mux_tree_tapbuf_size10_4_sram[0]:6 *C 46.920 66.595 +*N mux_tree_tapbuf_size10_4_sram[0]:7 *C 56.295 49.980 +*N mux_tree_tapbuf_size10_4_sram[0]:8 *C 56.120 49.980 +*N mux_tree_tapbuf_size10_4_sram[0]:9 *C 56.120 50.025 +*N mux_tree_tapbuf_size10_4_sram[0]:10 *C 56.220 55.760 +*N mux_tree_tapbuf_size10_4_sram[0]:11 *C 56.120 56.100 +*N mux_tree_tapbuf_size10_4_sram[0]:12 *C 56.120 56.100 +*N mux_tree_tapbuf_size10_4_sram[0]:13 *C 56.120 57.755 +*N mux_tree_tapbuf_size10_4_sram[0]:14 *C 56.075 57.800 +*N mux_tree_tapbuf_size10_4_sram[0]:15 *C 52.800 57.800 +*N mux_tree_tapbuf_size10_4_sram[0]:16 *C 52.800 58.190 +*N mux_tree_tapbuf_size10_4_sram[0]:17 *C 52.742 58.480 +*N mux_tree_tapbuf_size10_4_sram[0]:18 *C 46.965 58.480 +*N mux_tree_tapbuf_size10_4_sram[0]:19 *C 46.920 58.525 +*N mux_tree_tapbuf_size10_4_sram[0]:20 *C 46.920 64.600 +*N mux_tree_tapbuf_size10_4_sram[0]:21 *C 46.913 64.600 +*N mux_tree_tapbuf_size10_4_sram[0]:22 *C 44.180 64.600 +*N mux_tree_tapbuf_size10_4_sram[0]:23 *C 44.160 64.608 +*N mux_tree_tapbuf_size10_4_sram[0]:24 *C 44.160 68.672 +*N mux_tree_tapbuf_size10_4_sram[0]:25 *C 44.140 68.680 +*N mux_tree_tapbuf_size10_4_sram[0]:26 *C 27.608 68.680 +*N mux_tree_tapbuf_size10_4_sram[0]:27 *C 27.600 68.737 +*N mux_tree_tapbuf_size10_4_sram[0]:28 *C 27.600 69.315 +*N mux_tree_tapbuf_size10_4_sram[0]:29 *C 27.600 69.360 +*N mux_tree_tapbuf_size10_4_sram[0]:30 *C 27.445 69.360 + +*CAP +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_5\/mux_l1_in_2_:S 1e-06 +2 mux_right_ipin_5\/mux_l1_in_0_:S 1e-06 +3 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_ipin_5\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_4_sram[0]:5 2.843303e-05 +6 mux_tree_tapbuf_size10_4_sram[0]:6 9.419518e-05 +7 mux_tree_tapbuf_size10_4_sram[0]:7 4.627934e-05 +8 mux_tree_tapbuf_size10_4_sram[0]:8 5.041831e-05 +9 mux_tree_tapbuf_size10_4_sram[0]:9 0.000308551 +10 mux_tree_tapbuf_size10_4_sram[0]:10 6.589736e-05 +11 mux_tree_tapbuf_size10_4_sram[0]:11 7.050185e-05 +12 mux_tree_tapbuf_size10_4_sram[0]:12 0.000440645 +13 mux_tree_tapbuf_size10_4_sram[0]:13 9.931847e-05 +14 mux_tree_tapbuf_size10_4_sram[0]:14 0.0001753786 +15 mux_tree_tapbuf_size10_4_sram[0]:15 0.0002057956 +16 mux_tree_tapbuf_size10_4_sram[0]:16 8.620678e-05 +17 mux_tree_tapbuf_size10_4_sram[0]:17 0.0003922489 +18 mux_tree_tapbuf_size10_4_sram[0]:18 0.0003650147 +19 mux_tree_tapbuf_size10_4_sram[0]:19 0.0002842729 +20 mux_tree_tapbuf_size10_4_sram[0]:20 0.000410897 +21 mux_tree_tapbuf_size10_4_sram[0]:21 0.0002344227 +22 mux_tree_tapbuf_size10_4_sram[0]:22 0.0002344227 +23 mux_tree_tapbuf_size10_4_sram[0]:23 0.0002837979 +24 mux_tree_tapbuf_size10_4_sram[0]:24 0.0002837979 +25 mux_tree_tapbuf_size10_4_sram[0]:25 0.001181494 +26 mux_tree_tapbuf_size10_4_sram[0]:26 0.001181494 +27 mux_tree_tapbuf_size10_4_sram[0]:27 5.485943e-05 +28 mux_tree_tapbuf_size10_4_sram[0]:28 5.485943e-05 +29 mux_tree_tapbuf_size10_4_sram[0]:29 5.911628e-05 +30 mux_tree_tapbuf_size10_4_sram[0]:30 5.42212e-05 +31 mux_tree_tapbuf_size10_4_sram[0]:25 mux_tree_tapbuf_size8_2_sram[3]:10 0.0002255146 +32 mux_tree_tapbuf_size10_4_sram[0]:27 mux_tree_tapbuf_size8_2_sram[3]:8 5.878347e-07 +33 mux_tree_tapbuf_size10_4_sram[0]:26 mux_tree_tapbuf_size8_2_sram[3]:9 0.0002255146 +34 mux_tree_tapbuf_size10_4_sram[0]:28 mux_tree_tapbuf_size8_2_sram[3]:7 5.878347e-07 +35 mux_tree_tapbuf_size10_4_sram[0]:20 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.527518e-05 +36 mux_tree_tapbuf_size10_4_sram[0]:20 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.166618e-05 +37 mux_tree_tapbuf_size10_4_sram[0]:19 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.166618e-05 +38 mux_tree_tapbuf_size10_4_sram[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.527518e-05 +39 mux_tree_tapbuf_size10_4_sram[0]:14 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001021678 +40 mux_tree_tapbuf_size10_4_sram[0]:15 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001021678 + +*RES +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_4_sram[0]:30 0.152 +1 mux_tree_tapbuf_size10_4_sram[0]:20 mux_tree_tapbuf_size10_4_sram[0]:19 0.005424107 +2 mux_tree_tapbuf_size10_4_sram[0]:20 mux_tree_tapbuf_size10_4_sram[0]:6 0.00178125 +3 mux_tree_tapbuf_size10_4_sram[0]:21 mux_tree_tapbuf_size10_4_sram[0]:20 0.00341 +4 mux_tree_tapbuf_size10_4_sram[0]:22 mux_tree_tapbuf_size10_4_sram[0]:21 0.0004280916 +5 mux_tree_tapbuf_size10_4_sram[0]:23 mux_tree_tapbuf_size10_4_sram[0]:22 0.00341 +6 mux_tree_tapbuf_size10_4_sram[0]:25 mux_tree_tapbuf_size10_4_sram[0]:24 0.00341 +7 mux_tree_tapbuf_size10_4_sram[0]:24 mux_tree_tapbuf_size10_4_sram[0]:23 0.0006368499 +8 mux_tree_tapbuf_size10_4_sram[0]:27 mux_tree_tapbuf_size10_4_sram[0]:26 0.00341 +9 mux_tree_tapbuf_size10_4_sram[0]:26 mux_tree_tapbuf_size10_4_sram[0]:25 0.002590092 +10 mux_tree_tapbuf_size10_4_sram[0]:29 mux_tree_tapbuf_size10_4_sram[0]:28 0.0045 +11 mux_tree_tapbuf_size10_4_sram[0]:28 mux_tree_tapbuf_size10_4_sram[0]:27 0.000515625 +12 mux_tree_tapbuf_size10_4_sram[0]:30 mux_tree_tapbuf_size10_4_sram[0]:29 8.423914e-05 +13 mux_tree_tapbuf_size10_4_sram[0]:18 mux_tree_tapbuf_size10_4_sram[0]:17 0.005158483 +14 mux_tree_tapbuf_size10_4_sram[0]:19 mux_tree_tapbuf_size10_4_sram[0]:18 0.0045 +15 mux_tree_tapbuf_size10_4_sram[0]:16 mux_right_ipin_5\/mux_l1_in_2_:S 0.152 +16 mux_tree_tapbuf_size10_4_sram[0]:16 mux_tree_tapbuf_size10_4_sram[0]:15 0.0003482143 +17 mux_tree_tapbuf_size10_4_sram[0]:14 mux_tree_tapbuf_size10_4_sram[0]:13 0.0045 +18 mux_tree_tapbuf_size10_4_sram[0]:13 mux_tree_tapbuf_size10_4_sram[0]:12 0.001477679 +19 mux_tree_tapbuf_size10_4_sram[0]:8 mux_tree_tapbuf_size10_4_sram[0]:7 9.51087e-05 +20 mux_tree_tapbuf_size10_4_sram[0]:9 mux_tree_tapbuf_size10_4_sram[0]:8 0.0045 +21 mux_tree_tapbuf_size10_4_sram[0]:7 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size10_4_sram[0]:5 mux_right_ipin_5\/mux_l1_in_1_:S 0.152 +23 mux_tree_tapbuf_size10_4_sram[0]:6 mux_tree_tapbuf_size10_4_sram[0]:5 0.0045 +24 mux_tree_tapbuf_size10_4_sram[0]:11 mux_tree_tapbuf_size10_4_sram[0]:10 0.0001847826 +25 mux_tree_tapbuf_size10_4_sram[0]:12 mux_tree_tapbuf_size10_4_sram[0]:11 0.0045 +26 mux_tree_tapbuf_size10_4_sram[0]:12 mux_tree_tapbuf_size10_4_sram[0]:9 0.005424107 +27 mux_tree_tapbuf_size10_4_sram[0]:10 mux_right_ipin_5\/mux_l1_in_0_:S 0.152 +28 mux_tree_tapbuf_size10_4_sram[0]:17 mux_tree_tapbuf_size10_4_sram[0]:16 0.0001686047 +29 mux_tree_tapbuf_size10_4_sram[0]:15 mux_tree_tapbuf_size10_4_sram[0]:14 0.002924107 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[3] 0.001376251 //LENGTH 10.935 LUMPCC 0.0001216157 DR + +*CONN +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 45.845 22.780 +*I mux_right_ipin_13\/mux_l4_in_0_:S I *L 0.00357 *C 41.960 19.720 +*I mem_right_ipin_13\/FTB_9__48:A I *L 0.001746 *C 44.620 25.840 +*N mux_tree_tapbuf_size10_8_sram[3]:3 *C 44.620 25.840 +*N mux_tree_tapbuf_size10_8_sram[3]:4 *C 44.620 25.795 +*N mux_tree_tapbuf_size10_8_sram[3]:5 *C 41.998 19.720 +*N mux_tree_tapbuf_size10_8_sram[3]:6 *C 44.575 19.720 +*N mux_tree_tapbuf_size10_8_sram[3]:7 *C 44.620 19.765 +*N mux_tree_tapbuf_size10_8_sram[3]:8 *C 44.620 22.780 +*N mux_tree_tapbuf_size10_8_sram[3]:9 *C 44.665 22.780 +*N mux_tree_tapbuf_size10_8_sram[3]:10 *C 45.808 22.780 + +*CAP +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_13\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_13\/FTB_9__48:A 1e-06 +3 mux_tree_tapbuf_size10_8_sram[3]:3 3.270859e-05 +4 mux_tree_tapbuf_size10_8_sram[3]:4 0.0001634693 +5 mux_tree_tapbuf_size10_8_sram[3]:5 0.0001701556 +6 mux_tree_tapbuf_size10_8_sram[3]:6 0.0001701556 +7 mux_tree_tapbuf_size10_8_sram[3]:7 0.0001754633 +8 mux_tree_tapbuf_size10_8_sram[3]:8 0.0003698931 +9 mux_tree_tapbuf_size10_8_sram[3]:9 8.489511e-05 +10 mux_tree_tapbuf_size10_8_sram[3]:10 8.489511e-05 +11 mux_tree_tapbuf_size10_8_sram[3]:8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.644621e-05 +12 mux_tree_tapbuf_size10_8_sram[3]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.436166e-05 +13 mux_tree_tapbuf_size10_8_sram[3]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.644621e-05 +14 mux_tree_tapbuf_size10_8_sram[3]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.436166e-05 + +*RES +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_8_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_8_sram[3]:9 mux_tree_tapbuf_size10_8_sram[3]:8 0.0045 +2 mux_tree_tapbuf_size10_8_sram[3]:8 mux_tree_tapbuf_size10_8_sram[3]:7 0.002691964 +3 mux_tree_tapbuf_size10_8_sram[3]:8 mux_tree_tapbuf_size10_8_sram[3]:4 0.002691964 +4 mux_tree_tapbuf_size10_8_sram[3]:10 mux_tree_tapbuf_size10_8_sram[3]:9 0.001020089 +5 mux_tree_tapbuf_size10_8_sram[3]:3 mem_right_ipin_13\/FTB_9__48:A 0.152 +6 mux_tree_tapbuf_size10_8_sram[3]:4 mux_tree_tapbuf_size10_8_sram[3]:3 0.0045 +7 mux_tree_tapbuf_size10_8_sram[3]:6 mux_tree_tapbuf_size10_8_sram[3]:5 0.00230134 +8 mux_tree_tapbuf_size10_8_sram[3]:7 mux_tree_tapbuf_size10_8_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size10_8_sram[3]:5 mux_right_ipin_13\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_6_ccff_tail[0] 0.001741651 //LENGTH 15.080 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_9\/FTB_7__46:X O *L 0 *C 51.745 34.000 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 40.655 37.060 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 *C 40.693 37.060 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 *C 50.095 37.060 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 *C 50.140 37.015 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 *C 50.140 34.045 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 *C 50.185 34.000 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 *C 51.708 34.000 + +*CAP +0 mem_right_ipin_9\/FTB_7__46:X 1e-06 +1 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.0005828831 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0005828831 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.0001811351 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0001811351 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 0.0001058074 +7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 0.0001058074 + +*RES +0 mem_right_ipin_9\/FTB_7__46:X mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.00839509 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 0.001359375 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[2] 0.002680944 //LENGTH 19.550 LUMPCC 0.0001346994 DR + +*CONN +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 12.725 66.640 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 7.535 69.700 +*I mux_right_ipin_3\/mux_l3_in_1_:S I *L 0.00357 *C 22.180 67.320 +*I mux_right_ipin_3\/mux_l3_in_0_:S I *L 0.00357 *C 18.040 66.935 +*N mux_tree_tapbuf_size8_1_sram[2]:4 *C 18.040 66.935 +*N mux_tree_tapbuf_size8_1_sram[2]:5 *C 22.143 67.320 +*N mux_tree_tapbuf_size8_1_sram[2]:6 *C 18.040 67.320 +*N mux_tree_tapbuf_size8_1_sram[2]:7 *C 7.535 69.700 +*N mux_tree_tapbuf_size8_1_sram[2]:8 *C 7.820 69.700 +*N mux_tree_tapbuf_size8_1_sram[2]:9 *C 7.820 69.700 +*N mux_tree_tapbuf_size8_1_sram[2]:10 *C 7.820 69.360 +*N mux_tree_tapbuf_size8_1_sram[2]:11 *C 7.828 69.360 +*N mux_tree_tapbuf_size8_1_sram[2]:12 *C 12.413 69.360 +*N mux_tree_tapbuf_size8_1_sram[2]:13 *C 12.420 69.303 +*N mux_tree_tapbuf_size8_1_sram[2]:14 *C 12.420 67.320 +*N mux_tree_tapbuf_size8_1_sram[2]:15 *C 12.880 67.320 +*N mux_tree_tapbuf_size8_1_sram[2]:16 *C 12.880 67.320 +*N mux_tree_tapbuf_size8_1_sram[2]:17 *C 12.725 66.640 + +*CAP +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_ipin_3\/mux_l3_in_1_:S 1e-06 +3 mux_right_ipin_3\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_1_sram[2]:4 5.640522e-05 +5 mux_tree_tapbuf_size8_1_sram[2]:5 0.0002403777 +6 mux_tree_tapbuf_size8_1_sram[2]:6 0.0006134495 +7 mux_tree_tapbuf_size8_1_sram[2]:7 5.074171e-05 +8 mux_tree_tapbuf_size8_1_sram[2]:8 5.684796e-05 +9 mux_tree_tapbuf_size8_1_sram[2]:9 5.248075e-05 +10 mux_tree_tapbuf_size8_1_sram[2]:10 5.169118e-05 +11 mux_tree_tapbuf_size8_1_sram[2]:11 0.0003034872 +12 mux_tree_tapbuf_size8_1_sram[2]:12 0.0003034872 +13 mux_tree_tapbuf_size8_1_sram[2]:13 0.0001280102 +14 mux_tree_tapbuf_size8_1_sram[2]:14 0.0001607087 +15 mux_tree_tapbuf_size8_1_sram[2]:15 6.353424e-05 +16 mux_tree_tapbuf_size8_1_sram[2]:16 0.0003889989 +17 mux_tree_tapbuf_size8_1_sram[2]:17 7.202428e-05 +18 mux_tree_tapbuf_size8_1_sram[2]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.73497e-05 +19 mux_tree_tapbuf_size8_1_sram[2]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.73497e-05 + +*RES +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_1_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_1_sram[2]:5 mux_right_ipin_3\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[2]:4 mux_right_ipin_3\/mux_l3_in_0_:S 0.152 +3 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:15 0.0045 +4 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:6 0.004607143 +5 mux_tree_tapbuf_size8_1_sram[2]:15 mux_tree_tapbuf_size8_1_sram[2]:14 0.0004107143 +6 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:12 0.00341 +7 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:11 0.0007183166 +8 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:9 0.0001634615 +9 mux_tree_tapbuf_size8_1_sram[2]:11 mux_tree_tapbuf_size8_1_sram[2]:10 0.00341 +10 mux_tree_tapbuf_size8_1_sram[2]:8 mux_tree_tapbuf_size8_1_sram[2]:7 0.0001548913 +11 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:8 0.0045 +12 mux_tree_tapbuf_size8_1_sram[2]:7 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size8_1_sram[2]:17 mux_tree_tapbuf_size8_1_sram[2]:16 0.0006071429 +14 mux_tree_tapbuf_size8_1_sram[2]:6 mux_tree_tapbuf_size8_1_sram[2]:5 0.003662947 +15 mux_tree_tapbuf_size8_1_sram[2]:6 mux_tree_tapbuf_size8_1_sram[2]:4 0.00034375 +16 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:13 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[1] 0.003547257 //LENGTH 25.800 LUMPCC 0.0001007912 DR + +*CONN +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.105 31.620 +*I mux_right_ipin_10\/mux_l2_in_1_:S I *L 0.00357 *C 15.740 34.680 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 6.155 37.060 +*I mux_right_ipin_10\/mux_l2_in_0_:S I *L 0.00357 *C 18.040 36.720 +*I mux_right_ipin_10\/mux_l2_in_2_:S I *L 0.00357 *C 14.360 40.120 +*I mux_right_ipin_10\/mux_l2_in_3_:S I *L 0.00357 *C 14.840 41.480 +*N mux_tree_tapbuf_size8_4_sram[1]:6 *C 14.803 41.480 +*N mux_tree_tapbuf_size8_4_sram[1]:7 *C 14.305 41.480 +*N mux_tree_tapbuf_size8_4_sram[1]:8 *C 14.260 41.435 +*N mux_tree_tapbuf_size8_4_sram[1]:9 *C 14.260 40.120 +*N mux_tree_tapbuf_size8_4_sram[1]:10 *C 14.260 40.120 +*N mux_tree_tapbuf_size8_4_sram[1]:11 *C 18.040 36.720 +*N mux_tree_tapbuf_size8_4_sram[1]:12 *C 17.940 37.060 +*N mux_tree_tapbuf_size8_4_sram[1]:13 *C 6.192 37.060 +*N mux_tree_tapbuf_size8_4_sram[1]:14 *C 14.260 37.060 +*N mux_tree_tapbuf_size8_4_sram[1]:15 *C 14.260 37.060 +*N mux_tree_tapbuf_size8_4_sram[1]:16 *C 15.703 34.680 +*N mux_tree_tapbuf_size8_4_sram[1]:17 *C 14.305 34.680 +*N mux_tree_tapbuf_size8_4_sram[1]:18 *C 14.260 34.680 +*N mux_tree_tapbuf_size8_4_sram[1]:19 *C 14.260 31.665 +*N mux_tree_tapbuf_size8_4_sram[1]:20 *C 14.260 31.620 +*N mux_tree_tapbuf_size8_4_sram[1]:21 *C 14.105 31.620 + +*CAP +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_10\/mux_l2_in_1_:S 1e-06 +2 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_ipin_10\/mux_l2_in_0_:S 1e-06 +4 mux_right_ipin_10\/mux_l2_in_2_:S 1e-06 +5 mux_right_ipin_10\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_4_sram[1]:6 5.888446e-05 +7 mux_tree_tapbuf_size8_4_sram[1]:7 5.888446e-05 +8 mux_tree_tapbuf_size8_4_sram[1]:8 8.053084e-05 +9 mux_tree_tapbuf_size8_4_sram[1]:9 3.301067e-05 +10 mux_tree_tapbuf_size8_4_sram[1]:10 0.000290104 +11 mux_tree_tapbuf_size8_4_sram[1]:11 6.42829e-05 +12 mux_tree_tapbuf_size8_4_sram[1]:12 0.0002294755 +13 mux_tree_tapbuf_size8_4_sram[1]:13 0.0005351902 +14 mux_tree_tapbuf_size8_4_sram[1]:14 0.0007629797 +15 mux_tree_tapbuf_size8_4_sram[1]:15 0.0003581077 +16 mux_tree_tapbuf_size8_4_sram[1]:16 0.0001260319 +17 mux_tree_tapbuf_size8_4_sram[1]:17 0.0001260319 +18 mux_tree_tapbuf_size8_4_sram[1]:18 0.0003847392 +19 mux_tree_tapbuf_size8_4_sram[1]:19 0.0002085332 +20 mux_tree_tapbuf_size8_4_sram[1]:20 6.365536e-05 +21 mux_tree_tapbuf_size8_4_sram[1]:21 6.002401e-05 +22 mux_tree_tapbuf_size8_4_sram[1]:14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.96776e-05 +23 mux_tree_tapbuf_size8_4_sram[1]:14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.071799e-05 +24 mux_tree_tapbuf_size8_4_sram[1]:13 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.071799e-05 +25 mux_tree_tapbuf_size8_4_sram[1]:12 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.96776e-05 + +*RES +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_4_sram[1]:21 0.152 +1 mux_tree_tapbuf_size8_4_sram[1]:9 mux_right_ipin_10\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size8_4_sram[1]:10 mux_tree_tapbuf_size8_4_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size8_4_sram[1]:10 mux_tree_tapbuf_size8_4_sram[1]:8 0.001174107 +4 mux_tree_tapbuf_size8_4_sram[1]:6 mux_right_ipin_10\/mux_l2_in_3_:S 0.152 +5 mux_tree_tapbuf_size8_4_sram[1]:7 mux_tree_tapbuf_size8_4_sram[1]:6 0.0004441964 +6 mux_tree_tapbuf_size8_4_sram[1]:8 mux_tree_tapbuf_size8_4_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size8_4_sram[1]:14 mux_tree_tapbuf_size8_4_sram[1]:13 0.007203126 +8 mux_tree_tapbuf_size8_4_sram[1]:14 mux_tree_tapbuf_size8_4_sram[1]:12 0.003285714 +9 mux_tree_tapbuf_size8_4_sram[1]:15 mux_tree_tapbuf_size8_4_sram[1]:14 0.0045 +10 mux_tree_tapbuf_size8_4_sram[1]:15 mux_tree_tapbuf_size8_4_sram[1]:10 0.002732143 +11 mux_tree_tapbuf_size8_4_sram[1]:13 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size8_4_sram[1]:20 mux_tree_tapbuf_size8_4_sram[1]:19 0.0045 +13 mux_tree_tapbuf_size8_4_sram[1]:19 mux_tree_tapbuf_size8_4_sram[1]:18 0.002691964 +14 mux_tree_tapbuf_size8_4_sram[1]:21 mux_tree_tapbuf_size8_4_sram[1]:20 8.423914e-05 +15 mux_tree_tapbuf_size8_4_sram[1]:17 mux_tree_tapbuf_size8_4_sram[1]:16 0.001247768 +16 mux_tree_tapbuf_size8_4_sram[1]:18 mux_tree_tapbuf_size8_4_sram[1]:17 0.0045 +17 mux_tree_tapbuf_size8_4_sram[1]:18 mux_tree_tapbuf_size8_4_sram[1]:15 0.002125 +18 mux_tree_tapbuf_size8_4_sram[1]:16 mux_right_ipin_10\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size8_4_sram[1]:11 mux_right_ipin_10\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size8_4_sram[1]:12 mux_tree_tapbuf_size8_4_sram[1]:11 0.0001847826 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_4_ccff_tail[0] 0.0005832037 //LENGTH 4.320 LUMPCC 7.312997e-05 DR + +*CONN +*I mem_right_ipin_10\/FTB_14__53:X O *L 0 *C 13.575 47.260 +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 14.435 44.540 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 *C 14.435 44.540 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 *C 14.260 44.540 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 *C 14.260 44.585 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 *C 14.260 47.215 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 *C 14.215 47.260 +*N mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 *C 13.613 47.260 + +*CAP +0 mem_right_ipin_10\/FTB_14__53:X 1e-06 +1 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 5.366669e-05 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 5.834147e-05 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.0001324148 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0001324148 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 6.561798e-05 +7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 6.561798e-05 +8 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 optlc_net_130:4 3.656498e-05 +9 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 optlc_net_130:5 3.656498e-05 + +*RES +0 mem_right_ipin_10\/FTB_14__53:X mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_4_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0007946583 //LENGTH 6.570 LUMPCC 7.953929e-05 DR + +*CONN +*I mux_left_ipin_0\/mux_l3_in_1_:X O *L 0 *C 75.265 61.540 +*I mux_left_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 78.375 64.260 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 78.338 64.260 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 75.485 64.260 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 75.440 64.215 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 75.440 61.585 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 75.440 61.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 75.265 61.540 + +*CAP +0 mux_left_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001821105 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001821105 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.00012054 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.00012054 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.348128e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.433674e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_top_in[4]:25 3.976965e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_top_in[4]:22 3.976965e-05 + +*RES +0 mux_left_ipin_0\/mux_l3_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_ipin_0\/mux_l4_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002546875 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002348214 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009931234 //LENGTH 6.335 LUMPCC 0.0004439916 DR + +*CONN +*I mux_right_ipin_1\/mux_l1_in_2_:X O *L 0 *C 57.675 96.220 +*I mux_right_ipin_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 54.280 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 54.280 94.195 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 54.280 94.520 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 54.280 94.565 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 54.280 96.175 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 54.325 96.220 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 57.638 96.220 + +*CAP +0 mux_right_ipin_1\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_1\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.743938e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.206887e-05 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001136521 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001136521 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001051597 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001051597 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_2_sram[0]:11 8.416697e-05 +9 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_2_sram[0]:12 8.416697e-05 +10 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_2_sram[1]:36 0.0001342318 +11 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_2_sram[1]:35 0.0001342318 +12 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_2_sram[1]:7 3.597042e-06 +13 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_2_sram[1]:8 3.597042e-06 + +*RES +0 mux_right_ipin_1\/mux_l1_in_2_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002957589 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001766304 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_1\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004687649 //LENGTH 3.020 LUMPCC 0.0001126448 DR + +*CONN +*I mux_right_ipin_5\/mux_l2_in_1_:X O *L 0 *C 61.005 59.160 +*I mux_right_ipin_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 60.090 60.520 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 60.090 60.520 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 60.260 60.520 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 60.260 60.475 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 60.260 59.205 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 60.305 59.160 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 60.968 59.160 + +*CAP +0 mux_right_ipin_5\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_5\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.859503e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.31136e-05 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.364995e-05 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.364995e-05 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.255576e-05 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.255577e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_4_sram[1]:9 4.375332e-05 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:16 8.462154e-06 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:19 3.621213e-07 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:20 2.022874e-06 +12 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_4_sram[1]:21 1.721926e-06 +13 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_4_sram[1]:23 4.375332e-05 +14 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_4_sram[1]:17 8.462154e-06 +15 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_4_sram[1]:18 2.384995e-06 +16 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_4_sram[1]:22 1.721926e-06 + +*RES +0 mux_right_ipin_5\/mux_l2_in_1_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_5\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239132e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133929 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005915179 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006366915 //LENGTH 4.360 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_9\/mux_l2_in_0_:X O *L 0 *C 67.445 18.360 +*I mux_right_ipin_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 69.365 20.060 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 69.328 20.060 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 67.665 20.060 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 67.620 20.015 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 67.620 18.405 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 67.620 18.360 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 67.445 18.360 + +*CAP +0 mux_right_ipin_9\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_9\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001271684 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001271684 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001266716 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001266716 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.867348e-05 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.833796e-05 + +*RES +0 mux_right_ipin_9\/mux_l2_in_0_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_9\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001484375 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0007014228 //LENGTH 6.140 LUMPCC 8.002312e-05 DR + +*CONN +*I mux_right_ipin_12\/mux_l3_in_0_:X O *L 0 *C 19.955 15.640 +*I mux_right_ipin_12\/mux_l4_in_0_:A1 I *L 0.00198 *C 18.860 20.060 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 18.860 20.060 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 18.860 20.015 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 18.860 15.685 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 18.905 15.640 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 19.918 15.640 + +*CAP +0 mux_right_ipin_12\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_12\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.001484e-05 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001978974 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001978974 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 9.679503e-05 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.679503e-05 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_bottom_in[7]:29 4.001156e-05 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chany_bottom_in[7]:28 4.001156e-05 + +*RES +0 mux_right_ipin_12\/mux_l3_in_0_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0009040179 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.003866072 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_12\/mux_l4_in_0_:A1 0.152 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005885068 //LENGTH 3.280 LUMPCC 0.0001413038 DR + +*CONN +*I mux_right_ipin_2\/mux_l2_in_3_:X O *L 0 *C 15.355 95.880 +*I mux_right_ipin_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 15.930 93.500 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 15.930 93.500 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 15.640 93.500 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 15.640 93.545 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 15.640 95.835 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 15.640 95.880 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 15.355 95.880 + +*CAP +0 mux_right_ipin_2\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_2\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.324732e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.366887e-05 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.94431e-05 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.94431e-05 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.249289e-05 +7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.690777e-05 +8 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[15]:20 7.060183e-05 +9 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chany_top_in[15]:23 5.005728e-08 +10 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[15]:25 7.060183e-05 +11 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_top_in[15]:24 5.005728e-08 + +*RES +0 mux_right_ipin_2\/mux_l2_in_3_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_2\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001576087 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005418733 //LENGTH 4.210 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_7\/mux_l3_in_0_:X O *L 0 *C 65.145 91.800 +*I mux_right_ipin_7\/mux_l4_in_0_:A1 I *L 0.00198 *C 63.845 94.180 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 63.845 94.180 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 63.940 94.135 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 63.940 91.845 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 63.985 91.800 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 65.108 91.800 + +*CAP +0 mux_right_ipin_7\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_7\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.891045e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001536594 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001536594 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000101822 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000101822 + +*RES +0 mux_right_ipin_7\/mux_l3_in_0_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_7\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001002232 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001716524 //LENGTH 12.135 LUMPCC 0.000382957 DR + +*CONN +*I mux_right_ipin_11\/mux_l2_in_1_:X O *L 0 *C 23.635 55.420 +*I mux_right_ipin_11\/mux_l3_in_0_:A0 I *L 0.001631 *C 11.790 55.420 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 11.828 55.420 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 23.598 55.420 + +*CAP +0 mux_right_ipin_11\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_11\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0006657835 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0006657835 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[0]:48 5.003059e-05 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[0]:52 9.490533e-06 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[0]:47 5.003059e-05 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[0]:51 9.490533e-06 +8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size8_5_sram[0]:4 6.356336e-05 +9 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size8_5_sram[0]:3 6.356336e-05 +10 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.839402e-05 +11 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.839402e-05 + +*RES +0 mux_right_ipin_11\/mux_l2_in_1_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.01050893 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_11\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001046543 //LENGTH 9.750 LUMPCC 0.0001746487 DR + +*CONN +*I mux_right_ipin_15\/mux_l2_in_2_:X O *L 0 *C 79.405 87.720 +*I mux_right_ipin_15\/mux_l3_in_1_:A1 I *L 0.00198 *C 78.105 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.142 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 79.075 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 79.120 79.945 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 79.120 87.675 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 79.120 87.720 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 79.405 87.720 + +*CAP +0 mux_right_ipin_15\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_15\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.951821e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.951821e-05 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000303065 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000303065 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.285239e-05 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.187526e-05 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_7_sram[3]:9 8.732437e-05 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_7_sram[3]:8 8.732437e-05 + +*RES +0 mux_right_ipin_15\/mux_l2_in_2_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_15\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET ropt_net_165 0.001228515 //LENGTH 9.155 LUMPCC 0 DR + +*CONN +*I FTB_18__17:X O *L 0 *C 42.780 105.400 +*I ropt_mt_inst_769:A I *L 0.001766 *C 40.480 99.280 +*N ropt_net_165:2 *C 40.480 99.280 +*N ropt_net_165:3 *C 40.480 99.960 +*N ropt_net_165:4 *C 42.735 99.960 +*N ropt_net_165:5 *C 42.780 100.005 +*N ropt_net_165:6 *C 42.780 105.355 +*N ropt_net_165:7 *C 42.780 105.400 + +*CAP +0 FTB_18__17:X 1e-06 +1 ropt_mt_inst_769:A 1e-06 +2 ropt_net_165:2 8.409064e-05 +3 ropt_net_165:3 0.0002176673 +4 ropt_net_165:4 0.0001664335 +5 ropt_net_165:5 0.0003613723 +6 ropt_net_165:6 0.0003613723 +7 ropt_net_165:7 3.557928e-05 + +*RES +0 FTB_18__17:X ropt_net_165:7 0.152 +1 ropt_net_165:2 ropt_mt_inst_769:A 0.152 +2 ropt_net_165:4 ropt_net_165:3 0.002013393 +3 ropt_net_165:5 ropt_net_165:4 0.0045 +4 ropt_net_165:7 ropt_net_165:6 0.0045 +5 ropt_net_165:6 ropt_net_165:5 0.004776786 +6 ropt_net_165:3 ropt_net_165:2 0.000607143 + +*END + +*D_NET ropt_net_155 0.002048736 //LENGTH 14.350 LUMPCC 0.0007421497 DR + +*CONN +*I FTB_36__35:X O *L 0 *C 16.100 7.140 +*I ropt_mt_inst_754:A I *L 0.001766 *C 24.380 9.520 +*N ropt_net_155:2 *C 24.418 9.520 +*N ropt_net_155:3 *C 25.715 9.520 +*N ropt_net_155:4 *C 25.760 9.475 +*N ropt_net_155:5 *C 25.760 7.185 +*N ropt_net_155:6 *C 25.715 7.140 +*N ropt_net_155:7 *C 16.137 7.140 + +*CAP +0 FTB_36__35:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_155:2 3.93373e-05 +3 ropt_net_155:3 3.93373e-05 +4 ropt_net_155:4 0.0001397591 +5 ropt_net_155:5 0.0001397591 +6 ropt_net_155:6 0.000473197 +7 ropt_net_155:7 0.000473197 +8 ropt_net_155:7 chany_bottom_in[13]:33 7.882214e-05 +9 ropt_net_155:6 chany_bottom_in[13]:34 7.882214e-05 +10 ropt_net_155:7 chany_top_in[1]:13 2.529311e-05 +11 ropt_net_155:7 chany_top_in[1]:15 1.61414e-05 +12 ropt_net_155:6 chany_top_in[1]:14 2.529311e-05 +13 ropt_net_155:6 chany_top_in[1]:16 1.61414e-05 +14 ropt_net_155:5 chany_top_in[1]:17 2.063469e-05 +15 ropt_net_155:3 chany_top_in[1]:23 2.643867e-06 +16 ropt_net_155:4 chany_top_in[1]:18 2.063469e-05 +17 ropt_net_155:2 chany_top_in[1]:19 2.643867e-06 +18 ropt_net_155:3 chany_top_in[19]:11 6.083472e-05 +19 ropt_net_155:2 chany_top_in[19]:10 6.083472e-05 +20 ropt_net_155:3 ropt_net_187:7 4.866778e-05 +21 ropt_net_155:2 ropt_net_187:8 4.866778e-05 +22 ropt_net_155:7 ropt_net_149:2 0.0001127532 +23 ropt_net_155:6 ropt_net_149:3 0.0001127532 +24 ropt_net_155:5 ropt_net_149:4 5.283881e-06 +25 ropt_net_155:4 ropt_net_149:5 5.283881e-06 + +*RES +0 FTB_36__35:X ropt_net_155:7 0.152 +1 ropt_net_155:7 ropt_net_155:6 0.00855134 +2 ropt_net_155:6 ropt_net_155:5 0.0045 +3 ropt_net_155:5 ropt_net_155:4 0.002044643 +4 ropt_net_155:3 ropt_net_155:2 0.001158482 +5 ropt_net_155:4 ropt_net_155:3 0.0045 +6 ropt_net_155:2 ropt_mt_inst_754:A 0.152 + +*END + +*D_NET chany_bottom_out[18] 0.00197789 //LENGTH 13.875 LUMPCC 0.0003424459 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 66.835 3.740 +*P chany_bottom_out[18] O *L 0.7423 *C 56.120 1.325 +*N chany_bottom_out[18]:2 *C 56.120 3.400 +*N chany_bottom_out[18]:3 *C 56.995 3.400 +*N chany_bottom_out[18]:4 *C 57.010 3.710 +*N chany_bottom_out[18]:5 *C 57.085 3.740 +*N chany_bottom_out[18]:6 *C 66.797 3.740 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 chany_bottom_out[18] 0.0001039953 +2 chany_bottom_out[18]:2 0.000145622 +3 chany_bottom_out[18]:3 7.718631e-05 +4 chany_bottom_out[18]:4 3.555962e-05 +5 chany_bottom_out[18]:5 0.0006360402 +6 chany_bottom_out[18]:6 0.0006360402 +7 chany_bottom_out[18] ropt_net_161:5 4.028278e-05 +8 chany_bottom_out[18]:6 ropt_net_161:11 0.0001154324 +9 chany_bottom_out[18]:5 ropt_net_161:10 0.0001154324 +10 chany_bottom_out[18]:4 ropt_net_161:4 5.337039e-07 +11 chany_bottom_out[18]:2 ropt_net_161:6 1.497406e-05 +12 chany_bottom_out[18]:2 ropt_net_161:4 4.028278e-05 +13 chany_bottom_out[18]:3 ropt_net_161:7 1.497406e-05 +14 chany_bottom_out[18]:3 ropt_net_161:5 5.337039e-07 + +*RES +0 ropt_mt_inst_762:X chany_bottom_out[18]:6 0.152 +1 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.008671876 +2 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.0045 +3 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.00019375 +4 chany_bottom_out[18]:2 chany_bottom_out[18] 0.001852678 +5 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.00078125 + +*END + +*D_NET ropt_net_142 0.004034899 //LENGTH 30.335 LUMPCC 0.0009393904 DR + +*CONN +*I BUFT_P_115:X O *L 0 *C 37.985 9.180 +*I ropt_mt_inst_741:A I *L 0.001766 *C 18.400 4.080 +*N ropt_net_142:2 *C 18.438 4.080 +*N ropt_net_142:3 *C 21.115 4.080 +*N ropt_net_142:4 *C 21.160 4.035 +*N ropt_net_142:5 *C 21.160 2.085 +*N ropt_net_142:6 *C 21.205 2.040 +*N ropt_net_142:7 *C 36.755 2.040 +*N ropt_net_142:8 *C 36.800 2.085 +*N ropt_net_142:9 *C 36.800 9.135 +*N ropt_net_142:10 *C 36.845 9.180 +*N ropt_net_142:11 *C 37.948 9.180 + +*CAP +0 BUFT_P_115:X 1e-06 +1 ropt_mt_inst_741:A 1e-06 +2 ropt_net_142:2 0.0001651154 +3 ropt_net_142:3 0.0001651154 +4 ropt_net_142:4 0.0001366828 +5 ropt_net_142:5 0.0001366828 +6 ropt_net_142:6 0.0009383868 +7 ropt_net_142:7 0.0009383868 +8 ropt_net_142:8 0.0002342105 +9 ropt_net_142:9 0.0002342105 +10 ropt_net_142:10 7.235874e-05 +11 ropt_net_142:11 7.235874e-05 +12 ropt_net_142:9 chany_top_in[7]:10 0.0001326421 +13 ropt_net_142:7 chany_top_in[7]:12 5.800708e-05 +14 ropt_net_142:7 chany_top_in[7]:14 9.884118e-05 +15 ropt_net_142:8 chany_top_in[7]:11 0.0001326421 +16 ropt_net_142:6 chany_top_in[7]:13 5.800708e-05 +17 ropt_net_142:6 chany_top_in[7]:15 9.884118e-05 +18 ropt_net_142:5 chany_top_in[7]:17 5.562164e-06 +19 ropt_net_142:4 chany_top_in[7]:18 5.562164e-06 +20 ropt_net_142:11 chany_top_in[14]:12 3.546241e-05 +21 ropt_net_142:10 chany_top_in[14]:11 3.546241e-05 +22 ropt_net_142:9 chany_top_in[14]:10 0.0001391803 +23 ropt_net_142:8 chany_top_in[14]:9 0.0001391803 + +*RES +0 BUFT_P_115:X ropt_net_142:11 0.152 +1 ropt_net_142:11 ropt_net_142:10 0.000984375 +2 ropt_net_142:10 ropt_net_142:9 0.0045 +3 ropt_net_142:9 ropt_net_142:8 0.006294644 +4 ropt_net_142:7 ropt_net_142:6 0.01388393 +5 ropt_net_142:8 ropt_net_142:7 0.0045 +6 ropt_net_142:6 ropt_net_142:5 0.0045 +7 ropt_net_142:5 ropt_net_142:4 0.001741072 +8 ropt_net_142:3 ropt_net_142:2 0.002390625 +9 ropt_net_142:4 ropt_net_142:3 0.0045 +10 ropt_net_142:2 ropt_mt_inst_741:A 0.152 + +*END + +*D_NET chany_bottom_in[4] 0.01888792 //LENGTH 156.090 LUMPCC 0.001931221 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 70.380 1.325 +*I mux_right_ipin_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 73.505 25.500 +*I mux_right_ipin_15\/mux_l2_in_1_:A0 I *L 0.001631 *C 68.370 86.020 +*I mux_right_ipin_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 65.610 87.720 +*I ropt_mt_inst_733:A I *L 0.001767 *C 30.820 102.000 +*I mux_left_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 71.400 47.260 +*N chany_bottom_in[4]:6 *C 71.362 47.260 +*N chany_bottom_in[4]:7 *C 30.858 102.000 +*N chany_bottom_in[4]:8 *C 31.695 102.000 +*N chany_bottom_in[4]:9 *C 31.740 102.045 +*N chany_bottom_in[4]:10 *C 31.740 105.355 +*N chany_bottom_in[4]:11 *C 31.785 105.400 +*N chany_bottom_in[4]:12 *C 33.120 105.400 +*N chany_bottom_in[4]:13 *C 33.120 105.060 +*N chany_bottom_in[4]:14 *C 63.940 105.060 +*N chany_bottom_in[4]:15 *C 63.940 105.400 +*N chany_bottom_in[4]:16 *C 65.275 105.400 +*N chany_bottom_in[4]:17 *C 65.320 105.355 +*N chany_bottom_in[4]:18 *C 65.320 88.060 +*N chany_bottom_in[4]:19 *C 65.735 88.060 +*N chany_bottom_in[4]:20 *C 65.610 87.720 +*N chany_bottom_in[4]:21 *C 65.780 87.720 +*N chany_bottom_in[4]:22 *C 65.780 87.705 +*N chany_bottom_in[4]:23 *C 65.780 86.065 +*N chany_bottom_in[4]:24 *C 65.825 86.020 +*N chany_bottom_in[4]:25 *C 68.333 86.020 +*N chany_bottom_in[4]:26 *C 68.410 86.020 +*N chany_bottom_in[4]:27 *C 68.540 85.975 +*N chany_bottom_in[4]:28 *C 68.540 47.305 +*N chany_bottom_in[4]:29 *C 68.585 47.260 +*N chany_bottom_in[4]:30 *C 70.840 47.260 +*N chany_bottom_in[4]:31 *C 70.840 47.215 +*N chany_bottom_in[4]:32 *C 73.468 25.500 +*N chany_bottom_in[4]:33 *C 70.885 25.500 +*N chany_bottom_in[4]:34 *C 70.840 25.500 +*N chany_bottom_in[4]:35 *C 70.840 1.360 + +*CAP +0 chany_bottom_in[4] 2.917741e-05 +1 mux_right_ipin_9\/mux_l1_in_2_:A1 1e-06 +2 mux_right_ipin_15\/mux_l2_in_1_:A0 1e-06 +3 mux_right_ipin_7\/mux_l2_in_1_:A0 1e-06 +4 ropt_mt_inst_733:A 1e-06 +5 mux_left_ipin_0\/mux_l1_in_2_:A1 1e-06 +6 chany_bottom_in[4]:6 5.447424e-05 +7 chany_bottom_in[4]:7 7.819285e-05 +8 chany_bottom_in[4]:8 7.819285e-05 +9 chany_bottom_in[4]:9 0.0002783178 +10 chany_bottom_in[4]:10 0.0002783178 +11 chany_bottom_in[4]:11 0.0001250851 +12 chany_bottom_in[4]:12 0.0001526218 +13 chany_bottom_in[4]:13 0.002202694 +14 chany_bottom_in[4]:14 0.002201747 +15 chany_bottom_in[4]:15 0.0001403041 +16 chany_bottom_in[4]:16 0.0001137142 +17 chany_bottom_in[4]:17 0.0006404513 +18 chany_bottom_in[4]:18 0.0006705093 +19 chany_bottom_in[4]:19 6.609995e-05 +20 chany_bottom_in[4]:20 5.430618e-05 +21 chany_bottom_in[4]:21 5.907624e-05 +22 chany_bottom_in[4]:22 0.0001659514 +23 chany_bottom_in[4]:23 0.0001299094 +24 chany_bottom_in[4]:24 0.0001570858 +25 chany_bottom_in[4]:25 0.0001771912 +26 chany_bottom_in[4]:26 2.010536e-05 +27 chany_bottom_in[4]:27 0.00184023 +28 chany_bottom_in[4]:28 0.00184023 +29 chany_bottom_in[4]:29 0.0001900803 +30 chany_bottom_in[4]:30 0.0002794616 +31 chany_bottom_in[4]:31 0.001155682 +32 chany_bottom_in[4]:32 0.0001852829 +33 chany_bottom_in[4]:33 0.0001852829 +34 chany_bottom_in[4]:34 0.002278093 +35 chany_bottom_in[4]:35 0.001123828 +36 chany_bottom_in[4]:27 chany_top_in[10] 2.010698e-05 +37 chany_bottom_in[4]:27 chany_top_in[10]:23 2.01387e-06 +38 chany_bottom_in[4]:27 chany_top_in[10]:22 7.833163e-06 +39 chany_bottom_in[4]:28 chany_top_in[10]:19 7.833163e-06 +40 chany_bottom_in[4]:28 chany_top_in[10]:22 2.01387e-06 +41 chany_bottom_in[4]:28 chany_top_in[10]:27 2.010698e-05 +42 chany_bottom_in[4]:17 chany_top_in[10] 0.0004585814 +43 chany_bottom_in[4]:23 chany_top_in[10]:27 3.743858e-06 +44 chany_bottom_in[4]:22 chany_top_in[10] 3.743858e-06 +45 chany_bottom_in[4]:22 chany_top_in[10]:27 5.140884e-06 +46 chany_bottom_in[4]:18 chany_top_in[10]:27 0.0004585814 +47 chany_bottom_in[4]:19 chany_top_in[10] 5.140884e-06 +48 chany_bottom_in[4]:27 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002923883 +49 chany_bottom_in[4]:28 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002923883 +50 chany_bottom_in[4]:31 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.679686e-06 +51 chany_bottom_in[4]:33 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.422319e-06 +52 chany_bottom_in[4]:34 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.679686e-06 +53 chany_bottom_in[4]:34 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.145383e-05 +54 chany_bottom_in[4]:32 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.422319e-06 +55 chany_bottom_in[4]:35 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.145383e-05 +56 chany_bottom_in[4]:34 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.811303e-05 +57 chany_bottom_in[4]:35 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.811303e-05 +58 chany_bottom_in[4]:17 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.813342e-05 +59 chany_bottom_in[4]:18 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.813342e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:35 0.0004107143 +1 chany_bottom_in[4]:30 chany_bottom_in[4]:29 0.002013393 +2 chany_bottom_in[4]:30 chany_bottom_in[4]:6 0.0004665179 +3 chany_bottom_in[4]:31 chany_bottom_in[4]:30 0.0045 +4 chany_bottom_in[4]:26 chany_bottom_in[4]:25 6.919643e-05 +5 chany_bottom_in[4]:27 chany_bottom_in[4]:26 0.0045 +6 chany_bottom_in[4]:29 chany_bottom_in[4]:28 0.0045 +7 chany_bottom_in[4]:28 chany_bottom_in[4]:27 0.03452679 +8 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.001191964 +9 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.0045 +10 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.0045 +11 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.002955357 +12 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.0007477679 +13 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.0045 +14 chany_bottom_in[4]:7 ropt_mt_inst_733:A 0.152 +15 chany_bottom_in[4]:24 chany_bottom_in[4]:23 0.0045 +16 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.001464286 +17 chany_bottom_in[4]:21 chany_bottom_in[4]:20 9.239131e-05 +18 chany_bottom_in[4]:22 chany_bottom_in[4]:21 0.0045 +19 chany_bottom_in[4]:22 chany_bottom_in[4]:19 0.000221875 +20 chany_bottom_in[4]:20 mux_right_ipin_7\/mux_l2_in_1_:A0 0.152 +21 chany_bottom_in[4]:25 mux_right_ipin_15\/mux_l2_in_1_:A0 0.152 +22 chany_bottom_in[4]:25 chany_bottom_in[4]:24 0.002238839 +23 chany_bottom_in[4]:33 chany_bottom_in[4]:32 0.002305804 +24 chany_bottom_in[4]:34 chany_bottom_in[4]:33 0.0045 +25 chany_bottom_in[4]:34 chany_bottom_in[4]:31 0.01938839 +26 chany_bottom_in[4]:32 mux_right_ipin_9\/mux_l1_in_2_:A1 0.152 +27 chany_bottom_in[4]:6 mux_left_ipin_0\/mux_l1_in_2_:A1 0.152 +28 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.001191964 +29 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.0003035715 +30 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.02751786 +31 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.0003035715 +32 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.01544197 +33 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.0003705357 +34 chany_bottom_in[4]:35 chany_bottom_in[4]:34 0.02155357 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001696426 //LENGTH 14.480 LUMPCC 0.0001967137 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_1_:X O *L 0 *C 52.265 42.840 +*I mux_left_ipin_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.115 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 64.078 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 53.865 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 53.820 44.495 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 53.820 42.885 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 53.775 42.840 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 52.303 42.840 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005507671 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0005507671 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001083652 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001083652 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.972381e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.972381e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_0_sram[0]:14 5.091104e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_0_sram[0]:15 5.091104e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.744579e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.744579e-05 + +*RES +0 mux_left_ipin_0\/mux_l1_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_ipin_0\/mux_l2_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.009118305 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET optlc_net_131 0.005718268 //LENGTH 50.685 LUMPCC 0.0005802826 DR + +*CONN +*I optlc_124:HI O *L 0 *C 72.680 69.700 +*I mux_right_ipin_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 64.575 55.080 +*I mux_left_ipin_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 71.935 55.420 +*I mux_right_ipin_7\/mux_l2_in_3_:A0 I *L 0.001631 *C 72.510 87.720 +*I mux_right_ipin_15\/mux_l2_in_3_:A0 I *L 0.001631 *C 75.155 86.020 +*N optlc_net_131:5 *C 75.118 86.020 +*N optlc_net_131:6 *C 74.105 86.020 +*N optlc_net_131:7 *C 74.060 85.975 +*N optlc_net_131:8 *C 72.547 87.720 +*N optlc_net_131:9 *C 73.095 87.720 +*N optlc_net_131:10 *C 73.140 87.675 +*N optlc_net_131:11 *C 73.140 83.005 +*N optlc_net_131:12 *C 73.185 82.960 +*N optlc_net_131:13 *C 74.015 82.960 +*N optlc_net_131:14 *C 74.060 82.960 +*N optlc_net_131:15 *C 74.060 69.745 +*N optlc_net_131:16 *C 74.015 69.700 +*N optlc_net_131:17 *C 71.935 55.420 +*N optlc_net_131:18 *C 64.612 55.080 +*N optlc_net_131:19 *C 71.935 55.080 +*N optlc_net_131:20 *C 72.220 55.080 +*N optlc_net_131:21 *C 72.220 55.125 +*N optlc_net_131:22 *C 72.220 69.655 +*N optlc_net_131:23 *C 72.265 69.700 +*N optlc_net_131:24 *C 72.680 69.700 + +*CAP +0 optlc_124:HI 1e-06 +1 mux_right_ipin_5\/mux_l2_in_3_:A0 1e-06 +2 mux_left_ipin_0\/mux_l2_in_3_:A0 1e-06 +3 mux_right_ipin_7\/mux_l2_in_3_:A0 1e-06 +4 mux_right_ipin_15\/mux_l2_in_3_:A0 1e-06 +5 optlc_net_131:5 8.361483e-05 +6 optlc_net_131:6 8.361483e-05 +7 optlc_net_131:7 0.0001668354 +8 optlc_net_131:8 6.171382e-05 +9 optlc_net_131:9 6.171382e-05 +10 optlc_net_131:10 0.0002326225 +11 optlc_net_131:11 0.0002326225 +12 optlc_net_131:12 6.42158e-05 +13 optlc_net_131:13 6.42158e-05 +14 optlc_net_131:14 0.0008257976 +15 optlc_net_131:15 0.0006292618 +16 optlc_net_131:16 8.413883e-05 +17 optlc_net_131:17 5.824911e-05 +18 optlc_net_131:18 0.0004995689 +19 optlc_net_131:19 0.0005059083 +20 optlc_net_131:20 7.277772e-05 +21 optlc_net_131:21 0.0006130834 +22 optlc_net_131:22 0.0006130834 +23 optlc_net_131:23 3.387408e-05 +24 optlc_net_131:24 0.0001460729 +25 optlc_net_131:22 prog_clk[0]:305 4.955592e-05 +26 optlc_net_131:22 prog_clk[0]:306 8.232703e-05 +27 optlc_net_131:22 prog_clk[0]:312 1.609134e-05 +28 optlc_net_131:22 prog_clk[0]:313 9.129533e-05 +29 optlc_net_131:21 prog_clk[0]:302 4.955592e-05 +30 optlc_net_131:21 prog_clk[0]:305 8.232703e-05 +31 optlc_net_131:21 prog_clk[0]:307 1.609134e-05 +32 optlc_net_131:21 prog_clk[0]:312 9.129533e-05 +33 optlc_net_131:14 prog_clk[0]:313 4.406711e-05 +34 optlc_net_131:14 prog_clk[0]:320 6.804565e-06 +35 optlc_net_131:15 prog_clk[0]:312 4.406711e-05 +36 optlc_net_131:15 prog_clk[0]:317 6.804565e-06 + +*RES +0 optlc_124:HI optlc_net_131:24 0.152 +1 optlc_net_131:23 optlc_net_131:22 0.0045 +2 optlc_net_131:22 optlc_net_131:21 0.01297322 +3 optlc_net_131:20 optlc_net_131:19 1e-05 +4 optlc_net_131:20 optlc_net_131:17 0.0001976745 +5 optlc_net_131:21 optlc_net_131:20 0.0045 +6 optlc_net_131:13 optlc_net_131:12 0.0007410714 +7 optlc_net_131:14 optlc_net_131:13 0.0045 +8 optlc_net_131:14 optlc_net_131:7 0.002691964 +9 optlc_net_131:12 optlc_net_131:11 0.0045 +10 optlc_net_131:11 optlc_net_131:10 0.004169643 +11 optlc_net_131:9 optlc_net_131:8 0.0004888393 +12 optlc_net_131:10 optlc_net_131:9 0.0045 +13 optlc_net_131:8 mux_right_ipin_7\/mux_l2_in_3_:A0 0.152 +14 optlc_net_131:18 mux_right_ipin_5\/mux_l2_in_3_:A0 0.152 +15 optlc_net_131:6 optlc_net_131:5 0.0009040179 +16 optlc_net_131:7 optlc_net_131:6 0.0045 +17 optlc_net_131:5 mux_right_ipin_15\/mux_l2_in_3_:A0 0.152 +18 optlc_net_131:17 mux_left_ipin_0\/mux_l2_in_3_:A0 0.152 +19 optlc_net_131:16 optlc_net_131:15 0.0045 +20 optlc_net_131:15 optlc_net_131:14 0.01179911 +21 optlc_net_131:24 optlc_net_131:23 0.0003705357 +22 optlc_net_131:24 optlc_net_131:16 0.001191964 +23 optlc_net_131:19 optlc_net_131:18 0.006537947 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008790885 //LENGTH 7.080 LUMPCC 0.0001215509 DR + +*CONN +*I mux_right_ipin_9\/mux_l2_in_3_:X O *L 0 *C 63.195 30.940 +*I mux_right_ipin_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 65.115 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 65.078 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 63.985 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 63.940 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 63.480 26.520 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 63.480 30.895 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 63.480 30.940 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 63.195 30.940 + +*CAP +0 mux_right_ipin_9\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_9\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.663746e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.663746e-05 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.990681e-05 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002107621 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001798045 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.407513e-05 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 5.771404e-05 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chany_bottom_in[18]:23 6.077545e-05 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_bottom_in[18]:24 6.077545e-05 + +*RES +0 mux_right_ipin_9\/mux_l2_in_3_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001548913 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0045 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00390625 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0009754464 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_9\/mux_l3_in_1_:A0 0.152 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0004107143 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001346863 //LENGTH 9.755 LUMPCC 0.0005954113 DR + +*CONN +*I mux_right_ipin_13\/mux_l1_in_2_:X O *L 0 *C 39.845 20.400 +*I mux_right_ipin_13\/mux_l2_in_1_:A1 I *L 0.00198 *C 40.580 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 40.543 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.605 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 39.560 12.625 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.560 20.355 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.560 20.400 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 39.845 20.400 + +*CAP +0 mux_right_ipin_13\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_13\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.00010697 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.00010697 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000213829 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000213829 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.404151e-05 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.381197e-05 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[8]:43 1.341029e-06 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[8]:47 0.0002053185 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[8]:45 1.341029e-06 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[8]:46 0.0002053185 +12 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_8_sram[0]:24 8.699594e-05 +13 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_8_sram[0]:27 4.050153e-06 +14 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_8_sram[0]:25 8.699594e-05 +15 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_8_sram[0]:26 4.050153e-06 + +*RES +0 mux_right_ipin_13\/mux_l1_in_2_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_13\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008370536 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.006901786 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001342564 //LENGTH 11.320 LUMPCC 0.0001269198 DR + +*CONN +*I mux_right_ipin_6\/mux_l1_in_0_:X O *L 0 *C 31.565 74.800 +*I mux_right_ipin_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 33.025 66.980 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 33.062 66.980 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 33.535 66.980 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 33.580 67.025 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 33.580 74.755 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 33.535 74.800 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 31.603 74.800 + +*CAP +0 mux_right_ipin_6\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_6\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.72788e-05 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.72788e-05 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003976164 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003976164 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001319271 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001319271 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:16 6.345988e-05 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:15 6.345988e-05 + +*RES +0 mux_right_ipin_6\/mux_l1_in_0_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_6\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0] 0.01060888 //LENGTH 61.360 LUMPCC 0.00497256 DR + +*CONN +*I mux_right_ipin_7\/mux_l4_in_0_:X O *L 0 *C 62.275 94.520 +*I mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 6.695 99.150 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 6.732 99.238 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 14.215 99.280 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 14.260 99.280 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 14.268 99.280 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 62.093 99.280 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 62.100 99.223 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 62.100 94.565 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 62.100 94.520 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 62.275 94.520 + +*CAP +0 mux_right_ipin_7\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004126397 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0004126397 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.126491e-05 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002011246 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002011246 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0003186971 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003186971 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:9 6.371467e-05 +10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:10 5.417142e-05 +11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[7]:13 0.001296752 +12 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[7]:14 0.001296752 +13 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[9]:15 0.0001875106 +14 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[9]:17 4.140982e-05 +15 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[9]:16 0.0001875106 +16 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[9]:18 4.140982e-05 +17 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[11]:9 0.0007096339 +18 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[11]:10 0.0007096339 +19 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 ropt_net_145:10 0.0002198464 +20 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 ropt_net_145:6 3.112678e-05 +21 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_145:11 0.0002198464 +22 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_145:7 3.112678e-05 + +*RES +0 mux_right_ipin_7\/mux_l4_in_0_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:9 9.51087e-05 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0045 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.004158482 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00341 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.007492582 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.00341 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.006680804 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006160758 //LENGTH 4.970 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_15\/mux_l3_in_0_:X O *L 0 *C 66.525 79.900 +*I mux_right_ipin_15\/mux_l4_in_0_:A1 I *L 0.00198 *C 71.205 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 71.168 79.900 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 66.562 79.900 + +*CAP +0 mux_right_ipin_15\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_15\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003070379 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003070379 + +*RES +0 mux_right_ipin_15\/mux_l3_in_0_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_15\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.004111607 + +*END + +*D_NET chany_top_out[12] 0.001484298 //LENGTH 11.160 LUMPCC 0 DR + +*CONN +*I FTB_13__12:X O *L 0 *C 51.520 97.240 +*P chany_top_out[12] O *L 0.7423 *C 51.060 107.475 +*N chany_top_out[12]:2 *C 51.060 97.285 +*N chany_top_out[12]:3 *C 51.105 97.240 +*N chany_top_out[12]:4 *C 51.483 97.240 + +*CAP +0 FTB_13__12:X 1e-06 +1 chany_top_out[12] 0.0006840766 +2 chany_top_out[12]:2 0.0006840766 +3 chany_top_out[12]:3 5.757251e-05 +4 chany_top_out[12]:4 5.757251e-05 + +*RES +0 FTB_13__12:X chany_top_out[12]:4 0.152 +1 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +2 chany_top_out[12]:2 chany_top_out[12] 0.009098215 +3 chany_top_out[12]:4 chany_top_out[12]:3 0.0003370536 + +*END + +*D_NET chany_bottom_out[6] 0.00105454 //LENGTH 7.600 LUMPCC 0 DR + +*CONN +*I FTB_27__26:X O *L 0 *C 51.520 3.400 +*P chany_bottom_out[6] O *L 0.7423 *C 46.460 1.325 +*N chany_bottom_out[6]:2 *C 46.460 3.355 +*N chany_bottom_out[6]:3 *C 46.505 3.400 +*N chany_bottom_out[6]:4 *C 51.483 3.400 + +*CAP +0 FTB_27__26:X 1e-06 +1 chany_bottom_out[6] 0.0001368393 +2 chany_bottom_out[6]:2 0.0001368393 +3 chany_bottom_out[6]:3 0.0003899307 +4 chany_bottom_out[6]:4 0.0003899307 + +*RES +0 FTB_27__26:X chany_bottom_out[6]:4 0.152 +1 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +2 chany_bottom_out[6]:2 chany_bottom_out[6] 0.0018125 +3 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.004444197 + +*END + +*D_NET chany_bottom_out[16] 0.0005445797 //LENGTH 4.030 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 42.320 3.400 +*P chany_bottom_out[16] O *L 0.7423 *C 40.940 1.325 +*N chany_bottom_out[16]:2 *C 40.940 3.400 +*N chany_bottom_out[16]:3 *C 41.400 3.400 +*N chany_bottom_out[16]:4 *C 41.445 3.400 +*N chany_bottom_out[16]:5 *C 42.282 3.400 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 chany_bottom_out[16] 0.0001311046 +2 chany_bottom_out[16]:2 0.0001655105 +3 chany_bottom_out[16]:3 6.738972e-05 +4 chany_bottom_out[16]:4 8.978743e-05 +5 chany_bottom_out[16]:5 8.978743e-05 + +*RES +0 ropt_mt_inst_780:X chany_bottom_out[16]:5 0.152 +1 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.0045 +2 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0004107143 +3 chany_bottom_out[16]:5 chany_bottom_out[16]:4 0.0007477679 +4 chany_bottom_out[16]:2 chany_bottom_out[16] 0.001852679 + +*END + +*D_NET ropt_net_179 0.001765534 //LENGTH 11.155 LUMPCC 0.0005623392 DR + +*CONN +*I ropt_mt_inst_756:X O *L 0 *C 37.455 9.860 +*I ropt_mt_inst_789:A I *L 0.001766 *C 30.820 6.800 +*N ropt_net_179:2 *C 30.858 6.800 +*N ropt_net_179:3 *C 32.200 6.800 +*N ropt_net_179:4 *C 32.200 7.140 +*N ropt_net_179:5 *C 37.675 7.140 +*N ropt_net_179:6 *C 37.720 7.185 +*N ropt_net_179:7 *C 37.720 9.815 +*N ropt_net_179:8 *C 37.720 9.860 +*N ropt_net_179:9 *C 37.455 9.860 + +*CAP +0 ropt_mt_inst_756:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_179:2 0.0001069686 +3 ropt_net_179:3 0.0001345583 +4 ropt_net_179:4 0.000304258 +5 ropt_net_179:5 0.0002766682 +6 ropt_net_179:6 0.0001344933 +7 ropt_net_179:7 0.0001344933 +8 ropt_net_179:8 5.67133e-05 +9 ropt_net_179:9 5.30422e-05 +10 ropt_net_179:2 chany_bottom_in[13]:33 1.271425e-05 +11 ropt_net_179:5 chany_bottom_in[13]:34 0.0001236892 +12 ropt_net_179:5 chany_bottom_in[13]:37 1.684929e-05 +13 ropt_net_179:3 chany_bottom_in[13]:34 1.271425e-05 +14 ropt_net_179:4 chany_bottom_in[13]:33 0.0001236892 +15 ropt_net_179:4 chany_bottom_in[13]:36 1.684929e-05 +16 ropt_net_179:6 chany_top_in[14]:9 5.231713e-05 +17 ropt_net_179:8 chany_top_in[14]:12 5.044957e-07 +18 ropt_net_179:7 chany_top_in[14]:10 5.231713e-05 +19 ropt_net_179:9 chany_top_in[14]:11 5.044957e-07 +20 ropt_net_179:5 chany_bottom_out[7]:3 5.801375e-05 +21 ropt_net_179:6 chany_bottom_out[7] 1.708148e-05 +22 ropt_net_179:7 chany_bottom_out[7]:2 1.708148e-05 +23 ropt_net_179:4 chany_bottom_out[7]:4 5.801375e-05 + +*RES +0 ropt_mt_inst_756:X ropt_net_179:9 0.152 +1 ropt_net_179:2 ropt_mt_inst_789:A 0.152 +2 ropt_net_179:5 ropt_net_179:4 0.004888393 +3 ropt_net_179:6 ropt_net_179:5 0.0045 +4 ropt_net_179:8 ropt_net_179:7 0.0045 +5 ropt_net_179:7 ropt_net_179:6 0.002348214 +6 ropt_net_179:9 ropt_net_179:8 0.0001440218 +7 ropt_net_179:3 ropt_net_179:2 0.001198661 +8 ropt_net_179:4 ropt_net_179:3 0.0003035715 + +*END + +*D_NET chany_top_out[7] 0.001192443 //LENGTH 9.890 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 64.135 104.040 +*P chany_top_out[7] O *L 0.7423 *C 58.880 107.510 +*N chany_top_out[7]:2 *C 58.880 106.818 +*N chany_top_out[7]:3 *C 58.888 106.760 +*N chany_top_out[7]:4 *C 63.013 106.760 +*N chany_top_out[7]:5 *C 63.020 106.703 +*N chany_top_out[7]:6 *C 63.020 104.085 +*N chany_top_out[7]:7 *C 63.065 104.040 +*N chany_top_out[7]:8 *C 64.097 104.040 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chany_top_out[7] 6.199264e-05 +2 chany_top_out[7]:2 6.199264e-05 +3 chany_top_out[7]:3 0.0002495089 +4 chany_top_out[7]:4 0.0002495089 +5 chany_top_out[7]:5 0.0001671738 +6 chany_top_out[7]:6 0.0001671738 +7 chany_top_out[7]:7 0.0001170462 +8 chany_top_out[7]:8 0.0001170462 + +*RES +0 ropt_mt_inst_797:X chany_top_out[7]:8 0.152 +1 chany_top_out[7]:8 chany_top_out[7]:7 0.0009218751 +2 chany_top_out[7]:7 chany_top_out[7]:6 0.0045 +3 chany_top_out[7]:6 chany_top_out[7]:5 0.002337054 +4 chany_top_out[7]:5 chany_top_out[7]:4 0.00341 +5 chany_top_out[7]:4 chany_top_out[7]:3 0.0006462499 +6 chany_top_out[7]:2 chany_top_out[7] 0.0006183035 +7 chany_top_out[7]:3 chany_top_out[7]:2 0.00341 + +*END + +*D_NET chany_bottom_in[2] 0.02182886 //LENGTH 175.825 LUMPCC 0.002158781 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 49.220 1.325 +*I mux_right_ipin_13\/mux_l1_in_1_:A1 I *L 0.00198 *C 52.900 12.580 +*I mux_right_ipin_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 46.100 66.980 +*I mux_right_ipin_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.655 76.840 +*I mux_right_ipin_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 53.820 85.340 +*I mux_right_ipin_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 60.435 86.020 +*I FTB_3__2:A I *L 0.001767 *C 57.040 93.840 +*I mux_right_ipin_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 17.310 53.720 +*I mux_right_ipin_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 19.035 60.860 +*I mux_left_ipin_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 50.700 41.820 +*I mux_right_ipin_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 52.080 25.500 +*N chany_bottom_in[2]:11 *C 52.117 25.500 +*N chany_bottom_in[2]:12 *C 52.440 25.500 +*N chany_bottom_in[2]:13 *C 52.440 25.160 +*N chany_bottom_in[2]:14 *C 50.663 41.820 +*N chany_bottom_in[2]:15 *C 19.035 60.860 +*N chany_bottom_in[2]:16 *C 18.910 60.520 +*N chany_bottom_in[2]:17 *C 17.348 53.720 +*N chany_bottom_in[2]:18 *C 18.355 53.720 +*N chany_bottom_in[2]:19 *C 18.400 53.765 +*N chany_bottom_in[2]:20 *C 18.400 60.475 +*N chany_bottom_in[2]:21 *C 18.445 60.520 +*N chany_bottom_in[2]:22 *C 18.955 60.550 +*N chany_bottom_in[2]:23 *C 18.860 60.520 +*N chany_bottom_in[2]:24 *C 18.867 60.520 +*N chany_bottom_in[2]:25 *C 45.290 67.320 +*N chany_bottom_in[2]:26 *C 57.003 93.840 +*N chany_bottom_in[2]:27 *C 54.785 93.840 +*N chany_bottom_in[2]:28 *C 54.740 93.795 +*N chany_bottom_in[2]:29 *C 60.398 86.020 +*N chany_bottom_in[2]:30 *C 54.785 86.020 +*N chany_bottom_in[2]:31 *C 54.740 86.020 +*N chany_bottom_in[2]:32 *C 54.740 85.340 +*N chany_bottom_in[2]:33 *C 53.820 85.340 +*N chany_bottom_in[2]:34 *C 53.820 85.340 +*N chany_bottom_in[2]:35 *C 63.617 76.840 +*N chany_bottom_in[2]:36 *C 53.865 76.840 +*N chany_bottom_in[2]:37 *C 53.820 76.840 +*N chany_bottom_in[2]:38 *C 53.820 67.365 +*N chany_bottom_in[2]:39 *C 53.775 67.320 +*N chany_bottom_in[2]:40 *C 46.100 66.980 +*N chany_bottom_in[2]:41 *C 46.068 67.320 +*N chany_bottom_in[2]:42 *C 46.000 67.320 +*N chany_bottom_in[2]:43 *C 45.998 67.320 +*N chany_bottom_in[2]:44 *C 46.000 67.312 +*N chany_bottom_in[2]:45 *C 46.000 60.528 +*N chany_bottom_in[2]:46 *C 45.992 60.520 +*N chany_bottom_in[2]:47 *C 46.000 60.463 +*N chany_bottom_in[2]:48 *C 46.000 42.545 +*N chany_bottom_in[2]:49 *C 46.045 42.500 +*N chany_bottom_in[2]:50 *C 49.220 42.500 +*N chany_bottom_in[2]:51 *C 49.220 41.820 +*N chany_bottom_in[2]:52 *C 49.220 41.775 +*N chany_bottom_in[2]:53 *C 49.220 25.205 +*N chany_bottom_in[2]:54 *C 49.265 25.160 +*N chany_bottom_in[2]:55 *C 51.060 25.160 +*N chany_bottom_in[2]:56 *C 51.060 25.115 +*N chany_bottom_in[2]:57 *C 52.878 12.607 +*N chany_bottom_in[2]:58 *C 52.865 12.920 +*N chany_bottom_in[2]:59 *C 51.105 12.920 +*N chany_bottom_in[2]:60 *C 51.060 12.920 +*N chany_bottom_in[2]:61 *C 51.060 8.840 +*N chany_bottom_in[2]:62 *C 49.220 8.840 + +*CAP +0 chany_bottom_in[2] 0.0003655617 +1 mux_right_ipin_13\/mux_l1_in_1_:A1 1e-06 +2 mux_right_ipin_5\/mux_l1_in_1_:A1 1e-06 +3 mux_right_ipin_15\/mux_l2_in_0_:A0 1e-06 +4 mux_right_ipin_1\/mux_l1_in_1_:A1 1e-06 +5 mux_right_ipin_7\/mux_l2_in_0_:A0 1e-06 +6 FTB_3__2:A 1e-06 +7 mux_right_ipin_11\/mux_l2_in_0_:A0 1e-06 +8 mux_right_ipin_3\/mux_l2_in_0_:A0 1e-06 +9 mux_left_ipin_0\/mux_l1_in_1_:A1 1e-06 +10 mux_right_ipin_9\/mux_l1_in_1_:A1 1e-06 +11 chany_bottom_in[2]:11 5.407092e-05 +12 chany_bottom_in[2]:12 8.354687e-05 +13 chany_bottom_in[2]:13 0.0001269184 +14 chany_bottom_in[2]:14 0.0001170538 +15 chany_bottom_in[2]:15 4.915808e-05 +16 chany_bottom_in[2]:16 2.674793e-05 +17 chany_bottom_in[2]:17 9.852403e-05 +18 chany_bottom_in[2]:18 9.852403e-05 +19 chany_bottom_in[2]:19 0.0004319144 +20 chany_bottom_in[2]:20 0.0004319144 +21 chany_bottom_in[2]:21 3.861867e-05 +22 chany_bottom_in[2]:22 8.811541e-05 +23 chany_bottom_in[2]:23 3.635222e-05 +24 chany_bottom_in[2]:24 0.001658818 +25 chany_bottom_in[2]:25 8.721567e-05 +26 chany_bottom_in[2]:26 0.000183583 +27 chany_bottom_in[2]:27 0.000183583 +28 chany_bottom_in[2]:28 0.0004290225 +29 chany_bottom_in[2]:29 0.0003894682 +30 chany_bottom_in[2]:30 0.0003894682 +31 chany_bottom_in[2]:31 0.0004985839 +32 chany_bottom_in[2]:32 9.198232e-05 +33 chany_bottom_in[2]:33 3.310035e-05 +34 chany_bottom_in[2]:34 0.0004609458 +35 chany_bottom_in[2]:35 0.000674557 +36 chany_bottom_in[2]:36 0.000674557 +37 chany_bottom_in[2]:37 0.0009525468 +38 chany_bottom_in[2]:38 0.0005149658 +39 chany_bottom_in[2]:39 0.0005116581 +40 chany_bottom_in[2]:40 6.343506e-05 +41 chany_bottom_in[2]:41 0.0005458951 +42 chany_bottom_in[2]:42 3.417822e-05 +43 chany_bottom_in[2]:43 8.721567e-05 +44 chany_bottom_in[2]:44 0.0004145913 +45 chany_bottom_in[2]:45 0.0004145913 +46 chany_bottom_in[2]:46 0.001658818 +47 chany_bottom_in[2]:47 0.0009490311 +48 chany_bottom_in[2]:48 0.0009490311 +49 chany_bottom_in[2]:49 0.0001946067 +50 chany_bottom_in[2]:50 0.0002407334 +51 chany_bottom_in[2]:51 0.0001631805 +52 chany_bottom_in[2]:52 0.0008745014 +53 chany_bottom_in[2]:53 0.0008745014 +54 chany_bottom_in[2]:54 0.0001510145 +55 chany_bottom_in[2]:55 0.0002784683 +56 chany_bottom_in[2]:56 0.0003623668 +57 chany_bottom_in[2]:57 3.04575e-05 +58 chany_bottom_in[2]:58 0.0001897014 +59 chany_bottom_in[2]:59 0.000159244 +60 chany_bottom_in[2]:60 0.0005445068 +61 chany_bottom_in[2]:61 0.0002418873 +62 chany_bottom_in[2]:62 0.0004570489 +63 chany_bottom_in[2] chany_top_in[6]:9 3.978807e-06 +64 chany_bottom_in[2]:60 chany_top_in[6]:14 0.0001082827 +65 chany_bottom_in[2]:60 chany_top_in[6]:11 0.0003284142 +66 chany_bottom_in[2]:53 chany_top_in[6]:11 1.719306e-06 +67 chany_bottom_in[2]:52 chany_top_in[6]:14 1.719306e-06 +68 chany_bottom_in[2]:38 chany_top_in[6]:14 2.690318e-05 +69 chany_bottom_in[2]:28 chany_top_in[6]:15 2.594344e-07 +70 chany_bottom_in[2]:56 chany_top_in[6]:14 0.0003284142 +71 chany_bottom_in[2]:31 chany_top_in[6]:14 2.594344e-07 +72 chany_bottom_in[2]:37 chany_top_in[6]:14 2.035224e-05 +73 chany_bottom_in[2]:37 chany_top_in[6]:15 2.690318e-05 +74 chany_bottom_in[2]:34 chany_top_in[6]:15 2.035224e-05 +75 chany_bottom_in[2]:62 chany_top_in[6]:10 6.292963e-06 +76 chany_bottom_in[2]:61 chany_top_in[6]:11 0.0001105968 +77 chany_bottom_in[2]:24 chany_top_in[16]:41 0.0001348039 +78 chany_bottom_in[2]:24 chany_top_in[16]:42 0.0001849128 +79 chany_bottom_in[2]:46 chany_top_in[16]:14 0.0001849128 +80 chany_bottom_in[2]:46 chany_top_in[16]:42 0.0001348039 +81 chany_bottom_in[2]:60 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001514994 +82 chany_bottom_in[2]:56 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001514994 +83 chany_bottom_in[2] ropt_net_177:7 0.0001057096 +84 chany_bottom_in[2]:60 ropt_net_177:8 1.277201e-07 +85 chany_bottom_in[2]:62 ropt_net_177:9 1.01128e-05 +86 chany_bottom_in[2]:62 ropt_net_177:8 0.0001057096 +87 chany_bottom_in[2]:61 ropt_net_177:7 1.277201e-07 +88 chany_bottom_in[2]:61 ropt_net_177:10 1.01128e-05 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:62 0.006709822 +1 chany_bottom_in[2]:59 chany_bottom_in[2]:58 0.001571429 +2 chany_bottom_in[2]:60 chany_bottom_in[2]:59 0.0045 +3 chany_bottom_in[2]:60 chany_bottom_in[2]:56 0.01088839 +4 chany_bottom_in[2]:57 mux_right_ipin_13\/mux_l1_in_1_:A1 0.152 +5 chany_bottom_in[2]:23 chany_bottom_in[2]:22 0.0045 +6 chany_bottom_in[2]:24 chany_bottom_in[2]:23 0.00341 +7 chany_bottom_in[2]:22 chany_bottom_in[2]:21 0.0004553572 +8 chany_bottom_in[2]:22 chany_bottom_in[2]:16 4.017857e-05 +9 chany_bottom_in[2]:22 chany_bottom_in[2]:15 0.0001802326 +10 chany_bottom_in[2]:46 chany_bottom_in[2]:45 0.00341 +11 chany_bottom_in[2]:46 chany_bottom_in[2]:24 0.004249583 +12 chany_bottom_in[2]:45 chany_bottom_in[2]:44 0.001062983 +13 chany_bottom_in[2]:43 chany_bottom_in[2]:42 0.00341 +14 chany_bottom_in[2]:43 chany_bottom_in[2]:25 0.0001039141 +15 chany_bottom_in[2]:44 chany_bottom_in[2]:43 0.00341 +16 chany_bottom_in[2]:42 chany_bottom_in[2]:41 0.0045 +17 chany_bottom_in[2]:41 chany_bottom_in[2]:40 0.0001847826 +18 chany_bottom_in[2]:41 chany_bottom_in[2]:39 0.006881697 +19 chany_bottom_in[2]:54 chany_bottom_in[2]:53 0.0045 +20 chany_bottom_in[2]:53 chany_bottom_in[2]:52 0.01479464 +21 chany_bottom_in[2]:51 chany_bottom_in[2]:50 0.0006071429 +22 chany_bottom_in[2]:51 chany_bottom_in[2]:14 0.001287947 +23 chany_bottom_in[2]:52 chany_bottom_in[2]:51 0.0045 +24 chany_bottom_in[2]:39 chany_bottom_in[2]:38 0.0045 +25 chany_bottom_in[2]:38 chany_bottom_in[2]:37 0.008459822 +26 chany_bottom_in[2]:27 chany_bottom_in[2]:26 0.001979911 +27 chany_bottom_in[2]:28 chany_bottom_in[2]:27 0.0045 +28 chany_bottom_in[2]:26 FTB_3__2:A 0.152 +29 chany_bottom_in[2]:55 chany_bottom_in[2]:54 0.001602679 +30 chany_bottom_in[2]:55 chany_bottom_in[2]:13 0.001232143 +31 chany_bottom_in[2]:56 chany_bottom_in[2]:55 0.0045 +32 chany_bottom_in[2]:30 chany_bottom_in[2]:29 0.005011161 +33 chany_bottom_in[2]:31 chany_bottom_in[2]:30 0.0045 +34 chany_bottom_in[2]:31 chany_bottom_in[2]:28 0.006941965 +35 chany_bottom_in[2]:29 mux_right_ipin_7\/mux_l2_in_0_:A0 0.152 +36 chany_bottom_in[2]:36 chany_bottom_in[2]:35 0.00870759 +37 chany_bottom_in[2]:37 chany_bottom_in[2]:36 0.0045 +38 chany_bottom_in[2]:37 chany_bottom_in[2]:34 0.007589286 +39 chany_bottom_in[2]:35 mux_right_ipin_15\/mux_l2_in_0_:A0 0.152 +40 chany_bottom_in[2]:15 mux_right_ipin_3\/mux_l2_in_0_:A0 0.152 +41 chany_bottom_in[2]:11 mux_right_ipin_9\/mux_l1_in_1_:A1 0.152 +42 chany_bottom_in[2]:33 mux_right_ipin_1\/mux_l1_in_1_:A1 0.152 +43 chany_bottom_in[2]:34 chany_bottom_in[2]:33 0.0045 +44 chany_bottom_in[2]:34 chany_bottom_in[2]:32 0.0008214285 +45 chany_bottom_in[2]:21 chany_bottom_in[2]:20 0.0045 +46 chany_bottom_in[2]:20 chany_bottom_in[2]:19 0.005991071 +47 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.0008995536 +48 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.0045 +49 chany_bottom_in[2]:17 mux_right_ipin_11\/mux_l2_in_0_:A0 0.152 +50 chany_bottom_in[2]:40 mux_right_ipin_5\/mux_l1_in_1_:A1 0.152 +51 chany_bottom_in[2]:14 mux_left_ipin_0\/mux_l1_in_1_:A1 0.152 +52 chany_bottom_in[2]:47 chany_bottom_in[2]:46 0.00341 +53 chany_bottom_in[2]:49 chany_bottom_in[2]:48 0.0045 +54 chany_bottom_in[2]:48 chany_bottom_in[2]:47 0.01599777 +55 chany_bottom_in[2]:50 chany_bottom_in[2]:49 0.002834822 +56 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.0003035715 +57 chany_bottom_in[2]:58 chany_bottom_in[2]:57 0.0002111487 +58 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.0002879465 +59 chany_bottom_in[2]:62 chany_bottom_in[2]:61 0.001642857 +60 chany_bottom_in[2]:61 chany_bottom_in[2]:60 0.003642857 +61 chany_bottom_in[2]:32 chany_bottom_in[2]:31 0.0006071429 + +*END + +*D_NET chany_top_in[11] 0.01380485 //LENGTH 110.190 LUMPCC 0.002152554 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 45.540 107.510 +*I mux_right_ipin_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 42.685 85.340 +*I mux_right_ipin_6\/mux_l2_in_2_:A1 I *L 0.00198 *C 42.685 58.140 +*I mux_right_ipin_14\/mux_l2_in_2_:A1 I *L 0.00198 *C 42.685 41.820 +*I FTB_32__31:A I *L 0.001767 *C 40.020 6.800 +*N chany_top_in[11]:5 *C 40.058 6.800 +*N chany_top_in[11]:6 *C 43.195 6.800 +*N chany_top_in[11]:7 *C 43.240 6.800 +*N chany_top_in[11]:8 *C 42.723 41.820 +*N chany_top_in[11]:9 *C 43.195 41.820 +*N chany_top_in[11]:10 *C 43.240 41.820 +*N chany_top_in[11]:11 *C 42.723 58.140 +*N chany_top_in[11]:12 *C 43.195 58.140 +*N chany_top_in[11]:13 *C 43.240 58.140 +*N chany_top_in[11]:14 *C 42.723 85.340 +*N chany_top_in[11]:15 *C 43.195 85.340 +*N chany_top_in[11]:16 *C 43.240 85.340 +*N chany_top_in[11]:17 *C 43.240 88.015 +*N chany_top_in[11]:18 *C 43.285 88.060 +*N chany_top_in[11]:19 *C 45.495 88.060 +*N chany_top_in[11]:20 *C 45.540 88.105 + +*CAP +0 chany_top_in[11] 0.001058456 +1 mux_right_ipin_0\/mux_l2_in_2_:A1 1e-06 +2 mux_right_ipin_6\/mux_l2_in_2_:A1 1e-06 +3 mux_right_ipin_14\/mux_l2_in_2_:A1 1e-06 +4 FTB_32__31:A 1e-06 +5 chany_top_in[11]:5 0.0002857269 +6 chany_top_in[11]:6 0.0002857269 +7 chany_top_in[11]:7 0.001919967 +8 chany_top_in[11]:8 6.183088e-05 +9 chany_top_in[11]:9 6.183088e-05 +10 chany_top_in[11]:10 0.002570408 +11 chany_top_in[11]:11 6.88463e-05 +12 chany_top_in[11]:12 6.88463e-05 +13 chany_top_in[11]:13 0.002031617 +14 chany_top_in[11]:14 5.955434e-05 +15 chany_top_in[11]:15 5.955434e-05 +16 chany_top_in[11]:16 0.001550172 +17 chany_top_in[11]:17 0.0001734975 +18 chany_top_in[11]:18 0.0001669021 +19 chany_top_in[11]:19 0.0001669021 +20 chany_top_in[11]:20 0.001058456 +21 chany_top_in[11] chany_bottom_in[18]:14 0.0002526092 +22 chany_top_in[11]:20 chany_bottom_in[18]:17 0.0002526092 +23 chany_top_in[11]:13 chany_bottom_in[19]:16 1.830579e-05 +24 chany_top_in[11]:13 chany_bottom_in[19]:22 0.0005946333 +25 chany_top_in[11]:13 chany_bottom_in[19]:23 2.509416e-05 +26 chany_top_in[11]:13 chany_bottom_in[19]:31 3.028237e-06 +27 chany_top_in[11]:9 chany_bottom_in[19]:24 2.415801e-06 +28 chany_top_in[11]:10 chany_bottom_in[19]:23 0.0003988484 +29 chany_top_in[11]:10 chany_bottom_in[19]:31 6.613867e-05 +30 chany_top_in[11]:10 chany_bottom_in[19]:32 3.028237e-06 +31 chany_top_in[11]:8 chany_bottom_in[19]:30 2.415801e-06 +32 chany_top_in[11]:16 chany_bottom_in[19]:15 1.830579e-05 +33 chany_top_in[11]:16 chany_bottom_in[19]:19 0.0001957849 +34 chany_top_in[11]:16 chany_bottom_in[19]:22 2.509416e-05 +35 chany_top_in[11]:7 chany_bottom_in[19]:32 6.613867e-05 +36 chany_top_in[11]:10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001140515 +37 chany_top_in[11]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001140515 + +*RES +0 chany_top_in[11] chany_top_in[11]:20 0.01732589 +1 chany_top_in[11]:12 chany_top_in[11]:11 0.0004218751 +2 chany_top_in[11]:13 chany_top_in[11]:12 0.0045 +3 chany_top_in[11]:13 chany_top_in[11]:10 0.01457143 +4 chany_top_in[11]:11 mux_right_ipin_6\/mux_l2_in_2_:A1 0.152 +5 chany_top_in[11]:9 chany_top_in[11]:8 0.000421875 +6 chany_top_in[11]:10 chany_top_in[11]:9 0.0045 +7 chany_top_in[11]:10 chany_top_in[11]:7 0.03126786 +8 chany_top_in[11]:8 mux_right_ipin_14\/mux_l2_in_2_:A1 0.152 +9 chany_top_in[11]:15 chany_top_in[11]:14 0.000421875 +10 chany_top_in[11]:16 chany_top_in[11]:15 0.0045 +11 chany_top_in[11]:16 chany_top_in[11]:13 0.02428572 +12 chany_top_in[11]:14 mux_right_ipin_0\/mux_l2_in_2_:A1 0.152 +13 chany_top_in[11]:6 chany_top_in[11]:5 0.002801339 +14 chany_top_in[11]:7 chany_top_in[11]:6 0.0045 +15 chany_top_in[11]:5 FTB_32__31:A 0.152 +16 chany_top_in[11]:18 chany_top_in[11]:17 0.0045 +17 chany_top_in[11]:17 chany_top_in[11]:16 0.002388393 +18 chany_top_in[11]:19 chany_top_in[11]:18 0.001973214 +19 chany_top_in[11]:20 chany_top_in[11]:19 0.0045 + +*END + +*D_NET chany_top_in[15] 0.01398714 //LENGTH 125.425 LUMPCC 0.0002053858 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 26.680 107.475 +*I mux_right_ipin_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 17.020 96.220 +*I FTB_36__35:A I *L 0.001776 *C 13.800 6.800 +*I mux_right_ipin_10\/mux_l2_in_3_:A1 I *L 0.00198 *C 13.705 41.820 +*I mux_right_ipin_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 15.640 77.860 +*N chany_top_in[15]:5 *C 15.640 77.860 +*N chany_top_in[15]:6 *C 15.640 77.860 +*N chany_top_in[15]:7 *C 13.690 41.820 +*N chany_top_in[15]:8 *C 13.763 6.800 +*N chany_top_in[15]:9 *C 13.385 6.800 +*N chany_top_in[15]:10 *C 13.340 6.845 +*N chany_top_in[15]:11 *C 13.340 41.775 +*N chany_top_in[15]:12 *C 13.340 41.843 +*N chany_top_in[15]:13 *C 13.340 42.840 +*N chany_top_in[15]:14 *C 11.545 42.840 +*N chany_top_in[15]:15 *C 11.500 42.885 +*N chany_top_in[15]:16 *C 11.500 75.435 +*N chany_top_in[15]:17 *C 11.545 75.480 +*N chany_top_in[15]:18 *C 15.135 75.480 +*N chany_top_in[15]:19 *C 15.180 75.525 +*N chany_top_in[15]:20 *C 15.180 77.860 +*N chany_top_in[15]:21 *C 16.983 96.220 +*N chany_top_in[15]:22 *C 16.560 96.220 +*N chany_top_in[15]:23 *C 16.560 97.240 +*N chany_top_in[15]:24 *C 15.225 97.240 +*N chany_top_in[15]:25 *C 15.180 97.240 +*N chany_top_in[15]:26 *C 15.180 107.055 +*N chany_top_in[15]:27 *C 15.225 107.100 +*N chany_top_in[15]:28 *C 26.635 107.100 +*N chany_top_in[15]:29 *C 26.680 107.145 + +*CAP +0 chany_top_in[15] 3.887087e-05 +1 mux_right_ipin_2\/mux_l2_in_3_:A1 1e-06 +2 FTB_36__35:A 1e-06 +3 mux_right_ipin_10\/mux_l2_in_3_:A1 1e-06 +4 mux_right_ipin_4\/mux_l2_in_3_:A1 1e-06 +5 chany_top_in[15]:5 3.402521e-05 +6 chany_top_in[15]:6 6.662743e-05 +7 chany_top_in[15]:7 4.743689e-05 +8 chany_top_in[15]:8 4.323596e-05 +9 chany_top_in[15]:9 4.323596e-05 +10 chany_top_in[15]:10 0.001843342 +11 chany_top_in[15]:11 0.001843342 +12 chany_top_in[15]:12 0.0001139763 +13 chany_top_in[15]:13 0.0001946675 +14 chany_top_in[15]:14 0.0001281281 +15 chany_top_in[15]:15 0.001815035 +16 chany_top_in[15]:16 0.001815035 +17 chany_top_in[15]:17 0.0002782909 +18 chany_top_in[15]:18 0.0002782909 +19 chany_top_in[15]:19 0.0001319361 +20 chany_top_in[15]:20 0.00110767 +21 chany_top_in[15]:21 4.787236e-05 +22 chany_top_in[15]:22 0.0001208794 +23 chany_top_in[15]:23 0.0001987433 +24 chany_top_in[15]:24 0.0001257362 +25 chany_top_in[15]:25 0.001463634 +26 chany_top_in[15]:26 0.0004905629 +27 chany_top_in[15]:27 0.0007341525 +28 chany_top_in[15]:28 0.0007341525 +29 chany_top_in[15]:29 3.887087e-05 +30 chany_top_in[15]:24 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.005728e-08 +31 chany_top_in[15]:25 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.060183e-05 +32 chany_top_in[15]:23 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.005728e-08 +33 chany_top_in[15]:20 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.060183e-05 +34 chany_top_in[15]:14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.204104e-05 +35 chany_top_in[15]:13 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.204104e-05 + +*RES +0 chany_top_in[15] chany_top_in[15]:29 0.0002946428 +1 chany_top_in[15]:14 chany_top_in[15]:13 0.001602679 +2 chany_top_in[15]:15 chany_top_in[15]:14 0.0045 +3 chany_top_in[15]:17 chany_top_in[15]:16 0.0045 +4 chany_top_in[15]:16 chany_top_in[15]:15 0.0290625 +5 chany_top_in[15]:18 chany_top_in[15]:17 0.003205357 +6 chany_top_in[15]:19 chany_top_in[15]:18 0.0045 +7 chany_top_in[15]:8 FTB_36__35:A 0.152 +8 chany_top_in[15]:9 chany_top_in[15]:8 0.0003370536 +9 chany_top_in[15]:10 chany_top_in[15]:9 0.0045 +10 chany_top_in[15]:12 chany_top_in[15]:11 0.0045 +11 chany_top_in[15]:12 chany_top_in[15]:7 0.0001902174 +12 chany_top_in[15]:11 chany_top_in[15]:10 0.0311875 +13 chany_top_in[15]:5 mux_right_ipin_4\/mux_l2_in_3_:A1 0.152 +14 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +15 chany_top_in[15]:24 chany_top_in[15]:23 0.001191964 +16 chany_top_in[15]:25 chany_top_in[15]:24 0.0045 +17 chany_top_in[15]:25 chany_top_in[15]:20 0.01730357 +18 chany_top_in[15]:21 mux_right_ipin_2\/mux_l2_in_3_:A1 0.152 +19 chany_top_in[15]:7 mux_right_ipin_10\/mux_l2_in_3_:A1 0.152 +20 chany_top_in[15]:27 chany_top_in[15]:26 0.0045 +21 chany_top_in[15]:26 chany_top_in[15]:25 0.008763393 +22 chany_top_in[15]:28 chany_top_in[15]:27 0.0101875 +23 chany_top_in[15]:29 chany_top_in[15]:28 0.0045 +24 chany_top_in[15]:13 chany_top_in[15]:12 0.0008906251 +25 chany_top_in[15]:23 chany_top_in[15]:22 0.0009107143 +26 chany_top_in[15]:22 chany_top_in[15]:21 0.0003772322 +27 chany_top_in[15]:20 chany_top_in[15]:19 0.002084821 +28 chany_top_in[15]:20 chany_top_in[15]:6 0.0004107143 + +*END + +*D_NET ccff_head[0] 0.001762053 //LENGTH 18.130 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 1.230 13.600 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.915 22.780 +*N ccff_head[0]:2 *C 8.915 22.780 +*N ccff_head[0]:3 *C 8.740 22.780 +*N ccff_head[0]:4 *C 8.740 22.735 +*N ccff_head[0]:5 *C 8.740 20.785 +*N ccff_head[0]:6 *C 8.695 20.740 +*N ccff_head[0]:7 *C 5.105 20.740 +*N ccff_head[0]:8 *C 5.060 20.695 +*N ccff_head[0]:9 *C 5.060 13.658 +*N ccff_head[0]:10 *C 5.053 13.600 + +*CAP +0 ccff_head[0] 0.0001777309 +1 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 4.394272e-05 +3 ccff_head[0]:3 4.84046e-05 +4 ccff_head[0]:4 0.000115152 +5 ccff_head[0]:5 0.000115152 +6 ccff_head[0]:6 0.0002029113 +7 ccff_head[0]:7 0.0002029113 +8 ccff_head[0]:8 0.0003385588 +9 ccff_head[0]:9 0.0003385588 +10 ccff_head[0]:10 0.0001777309 + +*RES +0 ccff_head[0] ccff_head[0]:10 0.0005988583 +1 ccff_head[0]:2 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 9.51087e-05 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:6 ccff_head[0]:5 0.0045 +5 ccff_head[0]:5 ccff_head[0]:4 0.001741071 +6 ccff_head[0]:7 ccff_head[0]:6 0.003205357 +7 ccff_head[0]:8 ccff_head[0]:7 0.0045 +8 ccff_head[0]:9 ccff_head[0]:8 0.006283483 +9 ccff_head[0]:10 ccff_head[0]:9 0.00341 + +*END + +*D_NET left_grid_pin_2_[0] 0.0005588494 //LENGTH 4.230 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 96.900 +*P left_grid_pin_2_[0] O *L 0.7423 *C 1.230 97.920 +*N left_grid_pin_2_[0]:2 *C 3.213 97.920 +*N left_grid_pin_2_[0]:3 *C 3.220 97.863 +*N left_grid_pin_2_[0]:4 *C 3.220 96.945 +*N left_grid_pin_2_[0]:5 *C 3.243 96.900 +*N left_grid_pin_2_[0]:6 *C 3.610 96.900 + +*CAP +0 mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_2_[0] 0.0001642298 +2 left_grid_pin_2_[0]:2 0.0001642298 +3 left_grid_pin_2_[0]:3 7.205266e-05 +4 left_grid_pin_2_[0]:4 7.205266e-05 +5 left_grid_pin_2_[0]:5 4.264226e-05 +6 left_grid_pin_2_[0]:6 4.264226e-05 + +*RES +0 mux_right_ipin_2\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_2_[0]:6 0.152 +1 left_grid_pin_2_[0]:6 left_grid_pin_2_[0]:5 0.0001997283 +2 left_grid_pin_2_[0]:5 left_grid_pin_2_[0]:4 0.0045 +3 left_grid_pin_2_[0]:4 left_grid_pin_2_[0]:3 0.0008191965 +4 left_grid_pin_2_[0]:3 left_grid_pin_2_[0]:2 0.00341 +5 left_grid_pin_2_[0]:2 left_grid_pin_2_[0] 0.0003105917 + +*END + +*D_NET left_grid_pin_8_[0] 0.001889188 //LENGTH 16.545 LUMPCC 0.0003014311 DR + +*CONN +*I mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.085 64.260 +*P left_grid_pin_8_[0] O *L 0.7423 *C 1.298 76.160 +*N left_grid_pin_8_[0]:2 *C 1.380 76.160 +*N left_grid_pin_8_[0]:3 *C 1.380 76.103 +*N left_grid_pin_8_[0]:4 *C 1.380 63.965 +*N left_grid_pin_8_[0]:5 *C 1.425 63.920 +*N left_grid_pin_8_[0]:6 *C 3.680 63.920 +*N left_grid_pin_8_[0]:7 *C 3.680 64.260 +*N left_grid_pin_8_[0]:8 *C 4.048 64.260 + +*CAP +0 mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_8_[0] 3.135845e-05 +2 left_grid_pin_8_[0]:2 3.135845e-05 +3 left_grid_pin_8_[0]:3 0.0005543366 +4 left_grid_pin_8_[0]:4 0.0005543366 +5 left_grid_pin_8_[0]:5 0.0001399691 +6 left_grid_pin_8_[0]:6 0.0001661908 +7 left_grid_pin_8_[0]:7 6.771414e-05 +8 left_grid_pin_8_[0]:8 4.149241e-05 +9 left_grid_pin_8_[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001507156 +10 left_grid_pin_8_[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001507156 + +*RES +0 mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_8_[0]:8 0.152 +1 left_grid_pin_8_[0]:8 left_grid_pin_8_[0]:7 0.000328125 +2 left_grid_pin_8_[0]:5 left_grid_pin_8_[0]:4 0.0045 +3 left_grid_pin_8_[0]:4 left_grid_pin_8_[0]:3 0.01083705 +4 left_grid_pin_8_[0]:3 left_grid_pin_8_[0]:2 0.00341 +5 left_grid_pin_8_[0]:2 left_grid_pin_8_[0] 2.35e-05 +6 left_grid_pin_8_[0]:6 left_grid_pin_8_[0]:5 0.002013393 +7 left_grid_pin_8_[0]:7 left_grid_pin_8_[0]:6 0.0003035715 + +*END + +*D_NET ropt_net_159 0.001318532 //LENGTH 13.585 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_15\/BUFT_RR_120:X O *L 0 *C 80.500 91.800 +*I ropt_mt_inst_758:A I *L 0.001766 *C 77.740 102.000 +*N ropt_net_159:2 *C 77.778 102.000 +*N ropt_net_159:3 *C 80.455 102.000 +*N ropt_net_159:4 *C 80.500 101.955 +*N ropt_net_159:5 *C 80.500 91.845 +*N ropt_net_159:6 *C 80.500 91.800 + +*CAP +0 mem_right_ipin_15\/BUFT_RR_120:X 1e-06 +1 ropt_mt_inst_758:A 1e-06 +2 ropt_net_159:2 0.0001544812 +3 ropt_net_159:3 0.0001544812 +4 ropt_net_159:4 0.0004884234 +5 ropt_net_159:5 0.0004884234 +6 ropt_net_159:6 3.072251e-05 + +*RES +0 mem_right_ipin_15\/BUFT_RR_120:X ropt_net_159:6 0.152 +1 ropt_net_159:6 ropt_net_159:5 0.0045 +2 ropt_net_159:5 ropt_net_159:4 0.009026786 +3 ropt_net_159:3 ropt_net_159:2 0.002390625 +4 ropt_net_159:4 ropt_net_159:3 0.0045 +5 ropt_net_159:2 ropt_mt_inst_758:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.001799708 //LENGTH 13.785 LUMPCC 0.0001801881 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 32.505 91.460 +*I mux_right_ipin_0\/mux_l4_in_0_:S I *L 0.00357 *C 25.860 89.080 +*I mem_right_ipin_0\/FTB_2__41:A I *L 0.001746 *C 28.980 85.680 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 28.980 85.680 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 28.980 85.725 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 25.898 89.080 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 28.935 89.080 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 28.980 89.080 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 29.440 89.080 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 29.440 91.415 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 29.485 91.460 +*N mux_tree_tapbuf_size10_1_sram[3]:11 *C 32.468 91.460 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_0\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_0\/FTB_2__41:A 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 3.42485e-05 +4 mux_tree_tapbuf_size10_1_sram[3]:4 0.0001726771 +5 mux_tree_tapbuf_size10_1_sram[3]:5 0.0002095275 +6 mux_tree_tapbuf_size10_1_sram[3]:6 0.0002095275 +7 mux_tree_tapbuf_size10_1_sram[3]:7 0.000206428 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.0001935183 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.0001597674 +10 mux_tree_tapbuf_size10_1_sram[3]:10 0.0002154129 +11 mux_tree_tapbuf_size10_1_sram[3]:11 0.0002154129 +12 mux_tree_tapbuf_size10_1_sram[3]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.512425e-05 +13 mux_tree_tapbuf_size10_1_sram[3]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.496981e-05 +14 mux_tree_tapbuf_size10_1_sram[3]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.512425e-05 +15 mux_tree_tapbuf_size10_1_sram[3]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.496981e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.002712054 +2 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 0.0045 +3 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:4 0.002995536 +4 mux_tree_tapbuf_size10_1_sram[3]:5 mux_right_ipin_0\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.0045 +6 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.002084821 +7 mux_tree_tapbuf_size10_1_sram[3]:11 mux_tree_tapbuf_size10_1_sram[3]:10 0.002662946 +8 mux_tree_tapbuf_size10_1_sram[3]:3 mem_right_ipin_0\/FTB_2__41:A 0.152 +9 mux_tree_tapbuf_size10_1_sram[3]:4 mux_tree_tapbuf_size10_1_sram[3]:3 0.0045 +10 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[0] 0.003850999 //LENGTH 29.480 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 24.225 72.080 +*I mux_right_ipin_4\/mux_l1_in_2_:S I *L 0.00357 *C 23.560 77.815 +*I mux_right_ipin_4\/mux_l1_in_0_:S I *L 0.00357 *C 24.940 82.960 +*I mux_right_ipin_4\/mux_l1_in_1_:S I *L 0.00357 *C 21.720 85.000 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 19.955 75.140 +*N mux_tree_tapbuf_size10_3_sram[0]:5 *C 19.955 75.140 +*N mux_tree_tapbuf_size10_3_sram[0]:6 *C 20.240 75.140 +*N mux_tree_tapbuf_size10_3_sram[0]:7 *C 20.240 75.095 +*N mux_tree_tapbuf_size10_3_sram[0]:8 *C 20.240 71.785 +*N mux_tree_tapbuf_size10_3_sram[0]:9 *C 20.285 71.740 +*N mux_tree_tapbuf_size10_3_sram[0]:10 *C 23.460 71.740 +*N mux_tree_tapbuf_size10_3_sram[0]:11 *C 21.758 85.000 +*N mux_tree_tapbuf_size10_3_sram[0]:12 *C 25.255 85.000 +*N mux_tree_tapbuf_size10_3_sram[0]:13 *C 25.300 84.955 +*N mux_tree_tapbuf_size10_3_sram[0]:14 *C 24.955 82.960 +*N mux_tree_tapbuf_size10_3_sram[0]:15 *C 25.277 82.960 +*N mux_tree_tapbuf_size10_3_sram[0]:16 *C 25.300 82.960 +*N mux_tree_tapbuf_size10_3_sram[0]:17 *C 25.300 78.245 +*N mux_tree_tapbuf_size10_3_sram[0]:18 *C 25.255 78.200 +*N mux_tree_tapbuf_size10_3_sram[0]:19 *C 23.560 78.200 +*N mux_tree_tapbuf_size10_3_sram[0]:20 *C 23.560 77.890 +*N mux_tree_tapbuf_size10_3_sram[0]:21 *C 23.560 77.815 +*N mux_tree_tapbuf_size10_3_sram[0]:22 *C 23.460 77.520 +*N mux_tree_tapbuf_size10_3_sram[0]:23 *C 23.460 77.475 +*N mux_tree_tapbuf_size10_3_sram[0]:24 *C 23.460 72.125 +*N mux_tree_tapbuf_size10_3_sram[0]:25 *C 23.460 72.080 +*N mux_tree_tapbuf_size10_3_sram[0]:26 *C 24.188 72.080 + +*CAP +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_4\/mux_l1_in_2_:S 1e-06 +2 mux_right_ipin_4\/mux_l1_in_0_:S 1e-06 +3 mux_right_ipin_4\/mux_l1_in_1_:S 1e-06 +4 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_3_sram[0]:5 4.864149e-05 +6 mux_tree_tapbuf_size10_3_sram[0]:6 5.276742e-05 +7 mux_tree_tapbuf_size10_3_sram[0]:7 0.0002002606 +8 mux_tree_tapbuf_size10_3_sram[0]:8 0.0002002606 +9 mux_tree_tapbuf_size10_3_sram[0]:9 0.0002057519 +10 mux_tree_tapbuf_size10_3_sram[0]:10 0.0002344275 +11 mux_tree_tapbuf_size10_3_sram[0]:11 0.0003092498 +12 mux_tree_tapbuf_size10_3_sram[0]:12 0.0003092498 +13 mux_tree_tapbuf_size10_3_sram[0]:13 0.0001262668 +14 mux_tree_tapbuf_size10_3_sram[0]:14 6.504241e-05 +15 mux_tree_tapbuf_size10_3_sram[0]:15 6.504241e-05 +16 mux_tree_tapbuf_size10_3_sram[0]:16 0.0004642806 +17 mux_tree_tapbuf_size10_3_sram[0]:17 0.0003055267 +18 mux_tree_tapbuf_size10_3_sram[0]:18 0.0001523426 +19 mux_tree_tapbuf_size10_3_sram[0]:19 0.0001721919 +20 mux_tree_tapbuf_size10_3_sram[0]:20 1.401084e-05 +21 mux_tree_tapbuf_size10_3_sram[0]:21 8.683812e-05 +22 mux_tree_tapbuf_size10_3_sram[0]:22 5.763457e-05 +23 mux_tree_tapbuf_size10_3_sram[0]:23 0.0003036828 +24 mux_tree_tapbuf_size10_3_sram[0]:24 0.0003036828 +25 mux_tree_tapbuf_size10_3_sram[0]:25 9.876145e-05 +26 mux_tree_tapbuf_size10_3_sram[0]:26 7.008579e-05 + +*RES +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_3_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_3_sram[0]:9 mux_tree_tapbuf_size10_3_sram[0]:8 0.0045 +2 mux_tree_tapbuf_size10_3_sram[0]:8 mux_tree_tapbuf_size10_3_sram[0]:7 0.002955357 +3 mux_tree_tapbuf_size10_3_sram[0]:6 mux_tree_tapbuf_size10_3_sram[0]:5 0.0001548913 +4 mux_tree_tapbuf_size10_3_sram[0]:7 mux_tree_tapbuf_size10_3_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size10_3_sram[0]:5 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size10_3_sram[0]:22 mux_tree_tapbuf_size10_3_sram[0]:21 0.0001715116 +7 mux_tree_tapbuf_size10_3_sram[0]:23 mux_tree_tapbuf_size10_3_sram[0]:22 0.0045 +8 mux_tree_tapbuf_size10_3_sram[0]:25 mux_tree_tapbuf_size10_3_sram[0]:24 0.0045 +9 mux_tree_tapbuf_size10_3_sram[0]:25 mux_tree_tapbuf_size10_3_sram[0]:10 0.0003035715 +10 mux_tree_tapbuf_size10_3_sram[0]:24 mux_tree_tapbuf_size10_3_sram[0]:23 0.004776785 +11 mux_tree_tapbuf_size10_3_sram[0]:21 mux_right_ipin_4\/mux_l1_in_2_:S 0.152 +12 mux_tree_tapbuf_size10_3_sram[0]:21 mux_tree_tapbuf_size10_3_sram[0]:20 4.360465e-05 +13 mux_tree_tapbuf_size10_3_sram[0]:21 mux_tree_tapbuf_size10_3_sram[0]:19 0.00034375 +14 mux_tree_tapbuf_size10_3_sram[0]:18 mux_tree_tapbuf_size10_3_sram[0]:17 0.0045 +15 mux_tree_tapbuf_size10_3_sram[0]:17 mux_tree_tapbuf_size10_3_sram[0]:16 0.004209822 +16 mux_tree_tapbuf_size10_3_sram[0]:26 mux_tree_tapbuf_size10_3_sram[0]:25 0.0006495535 +17 mux_tree_tapbuf_size10_3_sram[0]:12 mux_tree_tapbuf_size10_3_sram[0]:11 0.003122768 +18 mux_tree_tapbuf_size10_3_sram[0]:13 mux_tree_tapbuf_size10_3_sram[0]:12 0.0045 +19 mux_tree_tapbuf_size10_3_sram[0]:11 mux_right_ipin_4\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_3_sram[0]:15 mux_tree_tapbuf_size10_3_sram[0]:14 0.0001752718 +21 mux_tree_tapbuf_size10_3_sram[0]:16 mux_tree_tapbuf_size10_3_sram[0]:15 0.0045 +22 mux_tree_tapbuf_size10_3_sram[0]:16 mux_tree_tapbuf_size10_3_sram[0]:13 0.00178125 +23 mux_tree_tapbuf_size10_3_sram[0]:14 mux_right_ipin_4\/mux_l1_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_3_sram[0]:10 mux_tree_tapbuf_size10_3_sram[0]:9 0.002834821 +25 mux_tree_tapbuf_size10_3_sram[0]:19 mux_tree_tapbuf_size10_3_sram[0]:18 0.001513393 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[1] 0.005833182 //LENGTH 46.210 LUMPCC 0.0007357612 DR + +*CONN +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 74.365 28.220 +*I mux_right_ipin_9\/mux_l2_in_1_:S I *L 0.00357 *C 71.400 17.975 +*I mux_right_ipin_9\/mux_l2_in_0_:S I *L 0.00357 *C 66.600 17.680 +*I mux_right_ipin_9\/mux_l2_in_2_:S I *L 0.00357 *C 73.240 30.990 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 70.095 37.060 +*I mux_right_ipin_9\/mux_l2_in_3_:S I *L 0.00357 *C 64.040 31.280 +*N mux_tree_tapbuf_size10_6_sram[1]:6 *C 64.040 31.280 +*N mux_tree_tapbuf_size10_6_sram[1]:7 *C 63.940 31.620 +*N mux_tree_tapbuf_size10_6_sram[1]:8 *C 70.095 37.060 +*N mux_tree_tapbuf_size10_6_sram[1]:9 *C 69.920 37.060 +*N mux_tree_tapbuf_size10_6_sram[1]:10 *C 69.920 37.015 +*N mux_tree_tapbuf_size10_6_sram[1]:11 *C 69.920 31.665 +*N mux_tree_tapbuf_size10_6_sram[1]:12 *C 69.920 31.620 +*N mux_tree_tapbuf_size10_6_sram[1]:13 *C 73.140 31.620 +*N mux_tree_tapbuf_size10_6_sram[1]:14 *C 73.095 31.210 +*N mux_tree_tapbuf_size10_6_sram[1]:15 *C 73.210 31.350 +*N mux_tree_tapbuf_size10_6_sram[1]:16 *C 73.240 30.990 +*N mux_tree_tapbuf_size10_6_sram[1]:17 *C 73.240 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:18 *C 76.775 30.600 +*N mux_tree_tapbuf_size10_6_sram[1]:19 *C 76.820 30.555 +*N mux_tree_tapbuf_size10_6_sram[1]:20 *C 76.820 28.265 +*N mux_tree_tapbuf_size10_6_sram[1]:21 *C 76.775 28.220 +*N mux_tree_tapbuf_size10_6_sram[1]:22 *C 71.400 18.050 +*N mux_tree_tapbuf_size10_6_sram[1]:23 *C 66.638 17.680 +*N mux_tree_tapbuf_size10_6_sram[1]:24 *C 71.343 17.680 +*N mux_tree_tapbuf_size10_6_sram[1]:25 *C 71.400 17.975 +*N mux_tree_tapbuf_size10_6_sram[1]:26 *C 71.400 18.360 +*N mux_tree_tapbuf_size10_6_sram[1]:27 *C 73.555 18.360 +*N mux_tree_tapbuf_size10_6_sram[1]:28 *C 73.600 18.405 +*N mux_tree_tapbuf_size10_6_sram[1]:29 *C 73.600 28.175 +*N mux_tree_tapbuf_size10_6_sram[1]:30 *C 73.645 28.220 +*N mux_tree_tapbuf_size10_6_sram[1]:31 *C 74.365 28.220 + +*CAP +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_9\/mux_l2_in_1_:S 1e-06 +2 mux_right_ipin_9\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_9\/mux_l2_in_2_:S 1e-06 +4 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_right_ipin_9\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_6_sram[1]:6 5.199372e-05 +7 mux_tree_tapbuf_size10_6_sram[1]:7 0.0004032092 +8 mux_tree_tapbuf_size10_6_sram[1]:8 5.066095e-05 +9 mux_tree_tapbuf_size10_6_sram[1]:9 5.506011e-05 +10 mux_tree_tapbuf_size10_6_sram[1]:10 0.0003058873 +11 mux_tree_tapbuf_size10_6_sram[1]:11 0.0003058873 +12 mux_tree_tapbuf_size10_6_sram[1]:12 0.0005933402 +13 mux_tree_tapbuf_size10_6_sram[1]:13 0.0002094259 +14 mux_tree_tapbuf_size10_6_sram[1]:14 3.012057e-05 +15 mux_tree_tapbuf_size10_6_sram[1]:15 3.193422e-05 +16 mux_tree_tapbuf_size10_6_sram[1]:16 8.466556e-05 +17 mux_tree_tapbuf_size10_6_sram[1]:17 0.0002931925 +18 mux_tree_tapbuf_size10_6_sram[1]:18 0.0002633821 +19 mux_tree_tapbuf_size10_6_sram[1]:19 0.0001620999 +20 mux_tree_tapbuf_size10_6_sram[1]:20 0.0001620999 +21 mux_tree_tapbuf_size10_6_sram[1]:21 0.0001454306 +22 mux_tree_tapbuf_size10_6_sram[1]:22 1.506193e-05 +23 mux_tree_tapbuf_size10_6_sram[1]:23 0.0003026735 +24 mux_tree_tapbuf_size10_6_sram[1]:24 0.0003225125 +25 mux_tree_tapbuf_size10_6_sram[1]:25 8.860056e-05 +26 mux_tree_tapbuf_size10_6_sram[1]:26 0.0001853913 +27 mux_tree_tapbuf_size10_6_sram[1]:27 0.0001631413 +28 mux_tree_tapbuf_size10_6_sram[1]:28 0.0002926849 +29 mux_tree_tapbuf_size10_6_sram[1]:29 0.0002926849 +30 mux_tree_tapbuf_size10_6_sram[1]:30 5.326659e-05 +31 mux_tree_tapbuf_size10_6_sram[1]:31 0.0002270136 +32 mux_tree_tapbuf_size10_6_sram[1]:28 chany_top_in[4]:15 0.000221734 +33 mux_tree_tapbuf_size10_6_sram[1]:28 chany_top_in[4]:18 5.784661e-05 +34 mux_tree_tapbuf_size10_6_sram[1]:29 chany_top_in[4]:18 0.000221734 +35 mux_tree_tapbuf_size10_6_sram[1]:29 chany_top_in[4]:19 5.784661e-05 +36 mux_tree_tapbuf_size10_6_sram[1]:28 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.320777e-05 +37 mux_tree_tapbuf_size10_6_sram[1]:29 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.320777e-05 +38 mux_tree_tapbuf_size10_6_sram[1]:23 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.509231e-05 +39 mux_tree_tapbuf_size10_6_sram[1]:24 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.509231e-05 + +*RES +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_6_sram[1]:31 0.152 +1 mux_tree_tapbuf_size10_6_sram[1]:21 mux_tree_tapbuf_size10_6_sram[1]:20 0.0045 +2 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:19 0.002044643 +3 mux_tree_tapbuf_size10_6_sram[1]:18 mux_tree_tapbuf_size10_6_sram[1]:17 0.00315625 +4 mux_tree_tapbuf_size10_6_sram[1]:19 mux_tree_tapbuf_size10_6_sram[1]:18 0.0045 +5 mux_tree_tapbuf_size10_6_sram[1]:27 mux_tree_tapbuf_size10_6_sram[1]:26 0.001924107 +6 mux_tree_tapbuf_size10_6_sram[1]:28 mux_tree_tapbuf_size10_6_sram[1]:27 0.0045 +7 mux_tree_tapbuf_size10_6_sram[1]:30 mux_tree_tapbuf_size10_6_sram[1]:29 0.0045 +8 mux_tree_tapbuf_size10_6_sram[1]:29 mux_tree_tapbuf_size10_6_sram[1]:28 0.008723214 +9 mux_tree_tapbuf_size10_6_sram[1]:25 mux_right_ipin_9\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size10_6_sram[1]:25 mux_tree_tapbuf_size10_6_sram[1]:24 0.0001715117 +11 mux_tree_tapbuf_size10_6_sram[1]:25 mux_tree_tapbuf_size10_6_sram[1]:22 4.360466e-05 +12 mux_tree_tapbuf_size10_6_sram[1]:16 mux_right_ipin_9\/mux_l2_in_2_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[1]:16 mux_tree_tapbuf_size10_6_sram[1]:15 0.0002093024 +14 mux_tree_tapbuf_size10_6_sram[1]:6 mux_right_ipin_9\/mux_l2_in_3_:S 0.152 +15 mux_tree_tapbuf_size10_6_sram[1]:12 mux_tree_tapbuf_size10_6_sram[1]:11 0.0045 +16 mux_tree_tapbuf_size10_6_sram[1]:12 mux_tree_tapbuf_size10_6_sram[1]:7 0.005339286 +17 mux_tree_tapbuf_size10_6_sram[1]:11 mux_tree_tapbuf_size10_6_sram[1]:10 0.004776786 +18 mux_tree_tapbuf_size10_6_sram[1]:9 mux_tree_tapbuf_size10_6_sram[1]:8 9.510869e-05 +19 mux_tree_tapbuf_size10_6_sram[1]:10 mux_tree_tapbuf_size10_6_sram[1]:9 0.0045 +20 mux_tree_tapbuf_size10_6_sram[1]:8 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +21 mux_tree_tapbuf_size10_6_sram[1]:23 mux_right_ipin_9\/mux_l2_in_0_:S 0.152 +22 mux_tree_tapbuf_size10_6_sram[1]:31 mux_tree_tapbuf_size10_6_sram[1]:30 0.0006428572 +23 mux_tree_tapbuf_size10_6_sram[1]:31 mux_tree_tapbuf_size10_6_sram[1]:21 0.002151786 +24 mux_tree_tapbuf_size10_6_sram[1]:7 mux_tree_tapbuf_size10_6_sram[1]:6 0.0003035714 +25 mux_tree_tapbuf_size10_6_sram[1]:13 mux_tree_tapbuf_size10_6_sram[1]:12 0.002875 +26 mux_tree_tapbuf_size10_6_sram[1]:24 mux_tree_tapbuf_size10_6_sram[1]:23 0.004200893 +27 mux_tree_tapbuf_size10_6_sram[1]:26 mux_tree_tapbuf_size10_6_sram[1]:25 0.0003437501 +28 mux_tree_tapbuf_size10_6_sram[1]:14 mux_tree_tapbuf_size10_6_sram[1]:13 0.0003660715 +29 mux_tree_tapbuf_size10_6_sram[1]:15 mux_tree_tapbuf_size10_6_sram[1]:14 0.0001026786 +30 mux_tree_tapbuf_size10_6_sram[1]:17 mux_tree_tapbuf_size10_6_sram[1]:16 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_3_ccff_tail[0] 0.001183531 //LENGTH 9.010 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_4\/FTB_4__43:X O *L 0 *C 15.415 71.400 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 21.795 69.700 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 *C 21.758 69.700 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 *C 16.145 69.700 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 *C 16.100 69.745 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 *C 16.100 71.355 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 *C 16.055 71.400 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 *C 15.453 71.400 + +*CAP +0 mem_right_ipin_4\/FTB_4__43:X 1e-06 +1 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 0.0004316882 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 0.0004316882 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 9.930149e-05 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 9.930149e-05 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 5.977601e-05 +7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 5.977601e-05 + +*RES +0 mem_right_ipin_4\/FTB_4__43:X mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 0.005011161 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[2] 0.002482508 //LENGTH 18.865 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 13.645 96.560 +*I mux_right_ipin_2\/mux_l3_in_1_:S I *L 0.00357 *C 14.820 94.520 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 5.235 91.460 +*I mux_right_ipin_2\/mux_l3_in_0_:S I *L 0.00357 *C 13.440 89.080 +*N mux_tree_tapbuf_size8_0_sram[2]:4 *C 13.340 89.080 +*N mux_tree_tapbuf_size8_0_sram[2]:5 *C 13.340 89.125 +*N mux_tree_tapbuf_size8_0_sram[2]:6 *C 5.235 91.460 +*N mux_tree_tapbuf_size8_0_sram[2]:7 *C 5.060 91.800 +*N mux_tree_tapbuf_size8_0_sram[2]:8 *C 13.295 91.800 +*N mux_tree_tapbuf_size8_0_sram[2]:9 *C 13.340 91.800 +*N mux_tree_tapbuf_size8_0_sram[2]:10 *C 14.783 94.520 +*N mux_tree_tapbuf_size8_0_sram[2]:11 *C 13.385 94.520 +*N mux_tree_tapbuf_size8_0_sram[2]:12 *C 13.340 94.520 +*N mux_tree_tapbuf_size8_0_sram[2]:13 *C 13.340 96.515 +*N mux_tree_tapbuf_size8_0_sram[2]:14 *C 13.340 96.560 +*N mux_tree_tapbuf_size8_0_sram[2]:15 *C 13.645 96.560 + +*CAP +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_2\/mux_l3_in_1_:S 1e-06 +2 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_2\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_0_sram[2]:4 3.087634e-05 +5 mux_tree_tapbuf_size8_0_sram[2]:5 0.000154433 +6 mux_tree_tapbuf_size8_0_sram[2]:6 5.385678e-05 +7 mux_tree_tapbuf_size8_0_sram[2]:7 0.000575925 +8 mux_tree_tapbuf_size8_0_sram[2]:8 0.0005511605 +9 mux_tree_tapbuf_size8_0_sram[2]:9 0.0003332141 +10 mux_tree_tapbuf_size8_0_sram[2]:10 0.0001182996 +11 mux_tree_tapbuf_size8_0_sram[2]:11 0.0001182996 +12 mux_tree_tapbuf_size8_0_sram[2]:12 0.0003036187 +13 mux_tree_tapbuf_size8_0_sram[2]:13 0.0001223003 +14 mux_tree_tapbuf_size8_0_sram[2]:14 5.80464e-05 +15 mux_tree_tapbuf_size8_0_sram[2]:15 5.847737e-05 + +*RES +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_0_sram[2]:15 0.152 +1 mux_tree_tapbuf_size8_0_sram[2]:11 mux_tree_tapbuf_size8_0_sram[2]:10 0.001247768 +2 mux_tree_tapbuf_size8_0_sram[2]:12 mux_tree_tapbuf_size8_0_sram[2]:11 0.0045 +3 mux_tree_tapbuf_size8_0_sram[2]:12 mux_tree_tapbuf_size8_0_sram[2]:9 0.002428571 +4 mux_tree_tapbuf_size8_0_sram[2]:10 mux_right_ipin_2\/mux_l3_in_1_:S 0.152 +5 mux_tree_tapbuf_size8_0_sram[2]:4 mux_right_ipin_2\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_0_sram[2]:5 mux_tree_tapbuf_size8_0_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size8_0_sram[2]:8 mux_tree_tapbuf_size8_0_sram[2]:7 0.007352679 +8 mux_tree_tapbuf_size8_0_sram[2]:9 mux_tree_tapbuf_size8_0_sram[2]:8 0.0045 +9 mux_tree_tapbuf_size8_0_sram[2]:9 mux_tree_tapbuf_size8_0_sram[2]:5 0.002388393 +10 mux_tree_tapbuf_size8_0_sram[2]:6 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:13 0.0045 +12 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:12 0.00178125 +13 mux_tree_tapbuf_size8_0_sram[2]:15 mux_tree_tapbuf_size8_0_sram[2]:14 0.0001114131 +14 mux_tree_tapbuf_size8_0_sram[2]:7 mux_tree_tapbuf_size8_0_sram[2]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[2] 0.002475782 //LENGTH 17.860 LUMPCC 0.0003753652 DR + +*CONN +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 11.585 37.400 +*I mux_right_ipin_10\/mux_l3_in_0_:S I *L 0.00357 *C 10.680 34.295 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 5.235 39.100 +*I mux_right_ipin_10\/mux_l3_in_1_:S I *L 0.00357 *C 8.380 41.480 +*N mux_tree_tapbuf_size8_4_sram[2]:4 *C 8.280 41.480 +*N mux_tree_tapbuf_size8_4_sram[2]:5 *C 8.280 41.435 +*N mux_tree_tapbuf_size8_4_sram[2]:6 *C 5.235 39.100 +*N mux_tree_tapbuf_size8_4_sram[2]:7 *C 5.060 38.760 +*N mux_tree_tapbuf_size8_4_sram[2]:8 *C 8.235 38.760 +*N mux_tree_tapbuf_size8_4_sram[2]:9 *C 8.280 38.760 +*N mux_tree_tapbuf_size8_4_sram[2]:10 *C 10.680 34.295 +*N mux_tree_tapbuf_size8_4_sram[2]:11 *C 10.680 34.665 +*N mux_tree_tapbuf_size8_4_sram[2]:12 *C 8.325 34.680 +*N mux_tree_tapbuf_size8_4_sram[2]:13 *C 8.280 34.725 +*N mux_tree_tapbuf_size8_4_sram[2]:14 *C 8.280 37.400 +*N mux_tree_tapbuf_size8_4_sram[2]:15 *C 8.325 37.400 +*N mux_tree_tapbuf_size8_4_sram[2]:16 *C 11.548 37.400 + +*CAP +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_10\/mux_l3_in_0_:S 1e-06 +2 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_10\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_4_sram[2]:4 3.242736e-05 +5 mux_tree_tapbuf_size8_4_sram[2]:5 9.952014e-05 +6 mux_tree_tapbuf_size8_4_sram[2]:6 5.496514e-05 +7 mux_tree_tapbuf_size8_4_sram[2]:7 0.000258796 +8 mux_tree_tapbuf_size8_4_sram[2]:8 0.0002326892 +9 mux_tree_tapbuf_size8_4_sram[2]:9 0.000172617 +10 mux_tree_tapbuf_size8_4_sram[2]:10 5.682412e-05 +11 mux_tree_tapbuf_size8_4_sram[2]:11 0.0001882286 +12 mux_tree_tapbuf_size8_4_sram[2]:12 0.0001590196 +13 mux_tree_tapbuf_size8_4_sram[2]:13 9.120608e-05 +14 mux_tree_tapbuf_size8_4_sram[2]:14 0.000165756 +15 mux_tree_tapbuf_size8_4_sram[2]:15 0.0002921837 +16 mux_tree_tapbuf_size8_4_sram[2]:16 0.0002921837 +17 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 1.713769e-05 +18 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 3.369141e-05 +19 mux_tree_tapbuf_size8_4_sram[2]:13 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 3.369141e-05 +20 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 3.746311e-05 +21 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 1.713769e-05 +22 mux_tree_tapbuf_size8_4_sram[2]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 3.746311e-05 +23 mux_tree_tapbuf_size8_4_sram[2]:14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.700701e-05 +24 mux_tree_tapbuf_size8_4_sram[2]:14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.713769e-05 +25 mux_tree_tapbuf_size8_4_sram[2]:12 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.609166e-05 +26 mux_tree_tapbuf_size8_4_sram[2]:13 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.700701e-05 +27 mux_tree_tapbuf_size8_4_sram[2]:9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.713769e-05 +28 mux_tree_tapbuf_size8_4_sram[2]:9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.915403e-05 +29 mux_tree_tapbuf_size8_4_sram[2]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.915403e-05 +30 mux_tree_tapbuf_size8_4_sram[2]:11 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.609166e-05 + +*RES +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_4_sram[2]:16 0.152 +1 mux_tree_tapbuf_size8_4_sram[2]:15 mux_tree_tapbuf_size8_4_sram[2]:14 0.0045 +2 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_4_sram[2]:13 0.002388393 +3 mux_tree_tapbuf_size8_4_sram[2]:14 mux_tree_tapbuf_size8_4_sram[2]:9 0.001214286 +4 mux_tree_tapbuf_size8_4_sram[2]:16 mux_tree_tapbuf_size8_4_sram[2]:15 0.002877232 +5 mux_tree_tapbuf_size8_4_sram[2]:12 mux_tree_tapbuf_size8_4_sram[2]:11 0.002102678 +6 mux_tree_tapbuf_size8_4_sram[2]:13 mux_tree_tapbuf_size8_4_sram[2]:12 0.0045 +7 mux_tree_tapbuf_size8_4_sram[2]:10 mux_right_ipin_10\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size8_4_sram[2]:8 mux_tree_tapbuf_size8_4_sram[2]:7 0.002834822 +9 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_4_sram[2]:8 0.0045 +10 mux_tree_tapbuf_size8_4_sram[2]:9 mux_tree_tapbuf_size8_4_sram[2]:5 0.002388393 +11 mux_tree_tapbuf_size8_4_sram[2]:6 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size8_4_sram[2]:4 mux_right_ipin_10\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size8_4_sram[2]:5 mux_tree_tapbuf_size8_4_sram[2]:4 0.0045 +14 mux_tree_tapbuf_size8_4_sram[2]:7 mux_tree_tapbuf_size8_4_sram[2]:6 0.0003035715 +15 mux_tree_tapbuf_size8_4_sram[2]:11 mux_tree_tapbuf_size8_4_sram[2]:10 0.0003303571 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_1_ccff_tail[0] 0.0004744474 //LENGTH 2.865 LUMPCC 0.0001061674 DR + +*CONN +*I mem_right_ipin_3\/FTB_11__50:X O *L 0 *C 18.620 70.040 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 18.580 71.740 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 *C 18.580 71.740 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 *C 18.845 71.740 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 *C 18.860 71.695 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 *C 18.860 70.085 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 *C 18.860 70.040 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 *C 18.620 70.040 + +*CAP +0 mem_right_ipin_3\/FTB_11__50:X 1e-06 +1 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 7.438284e-05 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 3.99985e-05 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 6.459135e-05 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 6.459135e-05 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 6.012235e-05 +7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 6.259361e-05 +8 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 prog_clk[0]:77 5.308371e-05 +9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 prog_clk[0]:81 5.308371e-05 + +*RES +0 mem_right_ipin_3\/FTB_11__50:X mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.0001304348 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 0.0001274039 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008067096 //LENGTH 4.980 LUMPCC 0.0002340136 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_3_:X O *L 0 *C 73.885 56.440 +*I mux_left_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 73.335 60.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 73.335 60.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 73.600 60.520 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 73.600 60.475 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 73.600 56.485 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 73.600 56.440 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 73.885 56.440 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.196146e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.974648e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001706531 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001706531 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.904813e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.863377e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:302 6.743753e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:305 4.956925e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:305 6.743753e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:306 4.956925e-05 + +*RES +0 mux_left_ipin_0\/mux_l2_in_3_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0035625 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001440218 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_ipin_0\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009476778 //LENGTH 7.100 LUMPCC 0.0001973702 DR + +*CONN +*I mux_right_ipin_1\/mux_l1_in_1_:X O *L 0 *C 51.695 85.945 +*I mux_right_ipin_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 52.235 91.460 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 52.235 91.460 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 52.440 91.460 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 52.440 91.415 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 52.440 86.065 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 52.395 86.020 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 51.733 86.005 + +*CAP +0 mux_right_ipin_1\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_1\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.09918e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.931117e-05 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002656096 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002656096 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.839269e-05 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.839269e-05 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[2]:20 2.897156e-05 +9 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[2]:61 1.759237e-06 +10 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[2]:19 2.897156e-05 +11 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[2]:23 1.759237e-06 +12 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[2]:22 1.768143e-05 +13 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[2]:21 1.768143e-05 +14 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[6]:14 5.027289e-05 +15 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[6]:15 5.027289e-05 + +*RES +0 mux_right_ipin_1\/mux_l1_in_1_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001114131 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_1\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007697114 //LENGTH 4.970 LUMPCC 0.0002344946 DR + +*CONN +*I mux_right_ipin_5\/mux_l2_in_0_:X O *L 0 *C 55.025 61.540 +*I mux_right_ipin_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 59.705 61.540 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 59.668 61.540 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 55.062 61.540 + +*CAP +0 mux_right_ipin_5\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_5\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002666085 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002666085 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001172473 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001172473 + +*RES +0 mux_right_ipin_5\/mux_l2_in_0_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_5\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004111608 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005770581 //LENGTH 4.550 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_8\/mux_l2_in_2_:X O *L 0 *C 25.015 40.120 +*I mux_right_ipin_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 22.905 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 22.943 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 24.795 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 24.840 41.775 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 24.840 40.165 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 24.840 40.120 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 25.015 40.120 + +*CAP +0 mux_right_ipin_8\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_8\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001229622 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001229622 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001079272 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001079272 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.718568e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.609352e-05 + +*RES +0 mux_right_ipin_8\/mux_l2_in_2_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_8\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001654018 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0] 0.01032015 //LENGTH 80.045 LUMPCC 0.0009621566 DR + +*CONN +*I mux_right_ipin_9\/mux_l4_in_0_:X O *L 0 *C 52.615 31.620 +*I mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.250 61.070 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.250 61.108 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 5.250 61.540 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 7.315 61.540 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 7.360 61.495 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 7.360 56.498 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 7.368 56.440 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 10.100 56.440 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 10.120 56.433 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 10.120 36.727 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 10.140 36.720 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 52.433 36.720 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 52.440 36.663 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 52.440 31.665 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 52.440 31.620 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:16 *C 52.615 31.620 + +*CAP +0 mux_right_ipin_9\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.12384e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0002244913 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001832529 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.000285931 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.000285931 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002046067 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0002046067 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0008973688 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0008973688 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.002728223 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.002728223 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0002812382 +14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0002812382 +15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.838849e-05 +16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:16 5.388985e-05 +17 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 chany_bottom_in[3]:54 0.0003181813 +18 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 chany_bottom_in[3]:53 0.0003181813 +19 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.000162897 +20 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.000162897 + +*RES +0 mux_right_ipin_9\/mux_l4_in_0_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:16 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:15 9.51087e-05 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0045 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.004462054 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.00341 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.006625825 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.003087116 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004280917 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.004462054 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.00184375 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0003861607 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003949252 //LENGTH 2.475 LUMPCC 0.0001820621 DR + +*CONN +*I mux_right_ipin_2\/mux_l3_in_1_:X O *L 0 *C 13.975 93.160 +*I mux_right_ipin_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 11.790 93.160 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 11.828 93.160 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 13.938 93.160 + +*CAP +0 mux_right_ipin_2\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_2\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001054315 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001054315 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.103106e-05 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 9.103106e-05 + +*RES +0 mux_right_ipin_2\/mux_l3_in_1_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_2\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001477554 //LENGTH 10.380 LUMPCC 0.0004277346 DR + +*CONN +*I mux_right_ipin_6\/mux_l2_in_2_:X O *L 0 *C 41.115 57.800 +*I mux_right_ipin_6\/mux_l3_in_1_:A1 I *L 0.00198 *C 31.645 58.140 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 31.683 58.140 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 35.880 58.140 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 35.880 57.800 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 41.078 57.800 + +*CAP +0 mux_right_ipin_6\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_6\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001865973 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002125375 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003373126 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003113725 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_2_sram[1]:24 5.133972e-05 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_2_sram[1]:25 1.480326e-05 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_2_sram[1]:7 5.133972e-05 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_2_sram[1]:24 1.480326e-05 +10 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:12 9.629662e-05 +11 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:13 9.629662e-05 +12 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.142768e-05 +13 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.142768e-05 + +*RES +0 mux_right_ipin_6\/mux_l2_in_2_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_6\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004640625 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003747768 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002355366 //LENGTH 18.895 LUMPCC 0.0006068904 DR + +*CONN +*I mux_right_ipin_10\/mux_l4_in_0_:X O *L 0 *C 5.695 45.560 +*I mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.995 61.030 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 7.995 61.030 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 6.945 60.860 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 6.870 60.830 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 6.855 60.520 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 5.520 60.520 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 5.520 45.605 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 5.520 45.560 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 5.695 45.560 + +*CAP +0 mux_right_ipin_10\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001242974 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.756983e-05 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.697047e-05 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000113874 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0006756638 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0005987603 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 5.483485e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 5.450501e-05 +10 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 prog_clk[0]:174 3.243204e-06 +11 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 prog_clk[0]:175 3.243204e-06 +12 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:147 6.345454e-06 +13 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:166 2.521185e-05 +14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:167 1.722338e-05 +15 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:170 5.981411e-05 +16 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:150 1.722338e-05 +17 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:167 2.521185e-05 +18 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:170 6.345454e-06 +19 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:171 5.981411e-05 +20 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001916072 +21 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001916072 + +*RES +0 mux_right_ipin_10\/mux_l4_in_0_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0009375 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0045 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.01331696 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:8 9.510871e-05 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001191964 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.00019375 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0] 0.01390817 //LENGTH 104.150 LUMPCC 0.002897451 DR + +*CONN +*I mux_right_ipin_15\/mux_l4_in_0_:X O *L 0 *C 69.635 79.560 +*I mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.200 44.745 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.200 44.745 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 5.060 44.880 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 5.060 44.925 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 5.060 52.303 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 5.053 52.360 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 3.700 52.360 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 3.680 52.367 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 3.680 65.953 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 3.700 65.960 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 53.490 65.960 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 69.453 65.960 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 69.460 66.017 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 69.460 79.515 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:15 *C 69.460 79.560 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:16 *C 69.635 79.560 + +*CAP +0 mux_right_ipin_15\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.901137e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.254764e-05 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001849527 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001849527 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.657181e-05 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.657181e-05 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.000470638 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.000470638 +10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.003060924 +11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00389591 +12 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0008349866 +13 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0007748333 +14 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.0007748333 +15 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:15 5.968784e-05 +16 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:16 6.166256e-05 +17 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 prog_clk[0]:313 2.4216e-06 +18 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 prog_clk[0]:312 2.4216e-06 +19 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 prog_clk[0]:76 1.605151e-05 +20 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 prog_clk[0]:335 1.038954e-05 +21 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 prog_clk[0]:169 4.295352e-05 +22 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 prog_clk[0]:170 0.0001712856 +23 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 prog_clk[0]:171 2.236308e-05 +24 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 prog_clk[0]:168 4.295352e-05 +25 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 prog_clk[0]:147 0.0001712856 +26 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 prog_clk[0]:170 2.236308e-05 +27 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 prog_clk[0]:75 1.605151e-05 +28 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 prog_clk[0]:334 1.038954e-05 +29 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_tree_tapbuf_size10_1_sram[0]:28 0.0003347498 +30 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_tree_tapbuf_size10_1_sram[0]:27 8.829226e-05 +31 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_tree_tapbuf_size10_1_sram[0]:27 0.0003347498 +32 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_tree_tapbuf_size10_1_sram[0]:28 8.829226e-05 +33 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.000326019 +34 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.000326019 +35 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 3.642563e-06 +36 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0002389499 +37 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0002389499 +38 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 3.642563e-06 +39 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001916072 +40 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001916072 + +*RES +0 mux_right_ipin_15\/mux_l4_in_0_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:16 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:16 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:15 9.51087e-05 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:15 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.0045 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.01205134 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.00341 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.002500792 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.002128317 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002118916 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.006587054 +11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +12 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.608697e-05 +13 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +14 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.007800432 + +*END + +*D_NET chany_bottom_out[2] 0.001578535 //LENGTH 9.305 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 59.030 4.420 +*P chany_bottom_out[2] O *L 0.7423 *C 53.820 1.325 +*N chany_bottom_out[2]:2 *C 53.820 3.343 +*N chany_bottom_out[2]:3 *C 53.828 3.400 +*N chany_bottom_out[2]:4 *C 58.873 3.400 +*N chany_bottom_out[2]:5 *C 58.880 3.458 +*N chany_bottom_out[2]:6 *C 58.880 4.375 +*N chany_bottom_out[2]:7 *C 58.880 4.420 +*N chany_bottom_out[2]:8 *C 59.030 4.420 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 chany_bottom_out[2] 0.0001458621 +2 chany_bottom_out[2]:2 0.0001458621 +3 chany_bottom_out[2]:3 0.0004935278 +4 chany_bottom_out[2]:4 0.0004935278 +5 chany_bottom_out[2]:5 9.127101e-05 +6 chany_bottom_out[2]:6 9.127101e-05 +7 chany_bottom_out[2]:7 5.987468e-05 +8 chany_bottom_out[2]:8 5.633895e-05 + +*RES +0 ropt_mt_inst_785:X chany_bottom_out[2]:8 0.152 +1 chany_bottom_out[2]:2 chany_bottom_out[2] 0.001801339 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.00341 +3 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.00341 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.0007903833 +5 chany_bottom_out[2]:7 chany_bottom_out[2]:6 0.0045 +6 chany_bottom_out[2]:6 chany_bottom_out[2]:5 0.0008191963 +7 chany_bottom_out[2]:8 chany_bottom_out[2]:7 8.152174e-05 + +*END + +*D_NET chany_top_out[17] 0.001529389 //LENGTH 11.610 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 44.355 99.960 +*P chany_top_out[17] O *L 0.7423 *C 41.400 107.510 +*N chany_top_out[17]:2 *C 41.400 106.805 +*N chany_top_out[17]:3 *C 41.445 106.760 +*N chany_top_out[17]:4 *C 43.655 106.760 +*N chany_top_out[17]:5 *C 43.700 106.715 +*N chany_top_out[17]:6 *C 43.700 100.005 +*N chany_top_out[17]:7 *C 43.745 99.960 +*N chany_top_out[17]:8 *C 44.318 99.960 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 chany_top_out[17] 6.330552e-05 +2 chany_top_out[17]:2 6.330552e-05 +3 chany_top_out[17]:3 0.000201754 +4 chany_top_out[17]:4 0.000201754 +5 chany_top_out[17]:5 0.0004359824 +6 chany_top_out[17]:6 0.0004359824 +7 chany_top_out[17]:7 6.315263e-05 +8 chany_top_out[17]:8 6.315263e-05 + +*RES +0 ropt_mt_inst_769:X chany_top_out[17]:8 0.152 +1 chany_top_out[17]:8 chany_top_out[17]:7 0.0005111608 +2 chany_top_out[17]:7 chany_top_out[17]:6 0.0045 +3 chany_top_out[17]:6 chany_top_out[17]:5 0.005991071 +4 chany_top_out[17]:4 chany_top_out[17]:3 0.001973214 +5 chany_top_out[17]:5 chany_top_out[17]:4 0.0045 +6 chany_top_out[17]:3 chany_top_out[17]:2 0.0045 +7 chany_top_out[17]:2 chany_top_out[17] 0.0006294643 + +*END + +*D_NET chany_bottom_in[5] 0.01730467 //LENGTH 136.445 LUMPCC 0.004096791 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 55.200 1.290 +*I mux_right_ipin_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 24.285 77.860 +*I mux_right_ipin_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 36.900 72.420 +*I FTB_6__5:A I *L 0.001776 *C 46.460 85.680 +*N chany_bottom_in[5]:4 *C 46.422 85.680 +*N chany_bottom_in[5]:5 *C 44.205 85.680 +*N chany_bottom_in[5]:6 *C 44.160 85.635 +*N chany_bottom_in[5]:7 *C 36.900 72.420 +*N chany_bottom_in[5]:8 *C 24.323 77.860 +*N chany_bottom_in[5]:9 *C 26.635 77.860 +*N chany_bottom_in[5]:10 *C 26.680 77.815 +*N chany_bottom_in[5]:11 *C 26.680 71.785 +*N chany_bottom_in[5]:12 *C 26.725 71.740 +*N chany_bottom_in[5]:13 *C 36.800 71.740 +*N chany_bottom_in[5]:14 *C 44.115 71.740 +*N chany_bottom_in[5]:15 *C 44.160 71.785 +*N chany_bottom_in[5]:16 *C 44.160 73.440 +*N chany_bottom_in[5]:17 *C 44.168 73.440 +*N chany_bottom_in[5]:18 *C 58.860 73.440 +*N chany_bottom_in[5]:19 *C 58.880 73.433 +*N chany_bottom_in[5]:20 *C 58.880 52.555 +*N chany_bottom_in[5]:21 *C 58.880 2.728 +*N chany_bottom_in[5]:22 *C 58.860 2.720 +*N chany_bottom_in[5]:23 *C 55.208 2.720 +*N chany_bottom_in[5]:24 *C 55.200 2.663 + +*CAP +0 chany_bottom_in[5] 0.0001061963 +1 mux_right_ipin_4\/mux_l1_in_2_:A1 1e-06 +2 mux_right_ipin_0\/mux_l1_in_2_:A1 1e-06 +3 FTB_6__5:A 1e-06 +4 chany_bottom_in[5]:4 0.0001719264 +5 chany_bottom_in[5]:5 0.0001719264 +6 chany_bottom_in[5]:6 0.0005593928 +7 chany_bottom_in[5]:7 6.993283e-05 +8 chany_bottom_in[5]:8 0.0002005751 +9 chany_bottom_in[5]:9 0.0002005751 +10 chany_bottom_in[5]:10 0.0003480159 +11 chany_bottom_in[5]:11 0.0003480159 +12 chany_bottom_in[5]:12 0.0006464786 +13 chany_bottom_in[5]:13 0.001020314 +14 chany_bottom_in[5]:14 0.0003336633 +15 chany_bottom_in[5]:15 9.841639e-05 +16 chany_bottom_in[5]:16 0.0006915273 +17 chany_bottom_in[5]:17 0.0007996334 +18 chany_bottom_in[5]:18 0.0007996334 +19 chany_bottom_in[5]:19 0.0008441679 +20 chany_bottom_in[5]:20 0.002892367 +21 chany_bottom_in[5]:21 0.002048199 +22 chany_bottom_in[5]:22 0.00037386 +23 chany_bottom_in[5]:23 0.00037386 +24 chany_bottom_in[5]:24 0.0001061963 +25 chany_bottom_in[5]:19 chany_bottom_in[10]:14 0.0003221174 +26 chany_bottom_in[5]:19 chany_bottom_in[10]:21 0.0001357623 +27 chany_bottom_in[5]:20 chany_bottom_in[10]:22 0.0001357623 +28 chany_bottom_in[5]:20 chany_bottom_in[10]:21 0.0003221174 +29 chany_bottom_in[5]:6 chany_bottom_in[11]:15 0.0001145407 +30 chany_bottom_in[5]:16 chany_bottom_in[11]:16 0.0001145407 +31 chany_bottom_in[5]:21 chany_bottom_in[11]:39 0.001005071 +32 chany_bottom_in[5]:20 chany_bottom_in[11]:38 0.001005071 +33 chany_bottom_in[5]:14 mux_tree_tapbuf_size10_1_sram[0]:24 0.0002462037 +34 chany_bottom_in[5]:14 mux_tree_tapbuf_size10_1_sram[0]:18 3.352502e-06 +35 chany_bottom_in[5]:12 mux_tree_tapbuf_size10_1_sram[0]:17 2.687069e-05 +36 chany_bottom_in[5]:7 mux_tree_tapbuf_size10_1_sram[0]:19 4.770193e-06 +37 chany_bottom_in[5]:7 mux_tree_tapbuf_size10_1_sram[0]:18 1.795837e-06 +38 chany_bottom_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:19 1.795837e-06 +39 chany_bottom_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:17 3.352502e-06 +40 chany_bottom_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:20 4.770193e-06 +41 chany_bottom_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:23 0.0002462037 +42 chany_bottom_in[5]:13 mux_tree_tapbuf_size10_1_sram[0]:18 2.687069e-05 +43 chany_bottom_in[5]:17 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001879117 +44 chany_bottom_in[5]:18 mux_tree_tapbuf_size8_2_sram[0]:12 0.0001879117 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:24 0.001225446 +1 chany_bottom_in[5]:14 chany_bottom_in[5]:13 0.00653125 +2 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.0045 +3 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.001979911 +4 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.0045 +5 chany_bottom_in[5]:4 FTB_6__5:A 0.152 +6 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.0045 +7 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.005383929 +8 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.002064732 +9 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.0045 +10 chany_bottom_in[5]:8 mux_right_ipin_4\/mux_l1_in_2_:A1 0.152 +11 chany_bottom_in[5]:7 mux_right_ipin_0\/mux_l1_in_2_:A1 0.152 +12 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.001477679 +13 chany_bottom_in[5]:16 chany_bottom_in[5]:6 0.01088839 +14 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.00341 +15 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.002301825 +16 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.00341 +17 chany_bottom_in[5]:22 chany_bottom_in[5]:21 0.00341 +18 chany_bottom_in[5]:21 chany_bottom_in[5]:20 0.007806308 +19 chany_bottom_in[5]:24 chany_bottom_in[5]:23 0.00341 +20 chany_bottom_in[5]:23 chany_bottom_in[5]:22 0.000572225 +21 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.008995535 +22 chany_bottom_in[5]:13 chany_bottom_in[5]:7 0.0006071429 +23 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.003270808 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[1] 0.003991644 //LENGTH 31.050 LUMPCC 0.0001379063 DR + +*CONN +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 64.245 82.960 +*I mux_right_ipin_7\/mux_l2_in_0_:S I *L 0.00357 *C 61.540 85.000 +*I mux_right_ipin_7\/mux_l2_in_2_:S I *L 0.00357 *C 75.540 94.520 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 73.775 96.900 +*I mux_right_ipin_7\/mux_l2_in_3_:S I *L 0.00357 *C 71.400 88.695 +*I mux_right_ipin_7\/mux_l2_in_1_:S I *L 0.00357 *C 64.500 88.695 +*N mux_tree_tapbuf_size8_3_sram[1]:6 *C 64.500 88.695 +*N mux_tree_tapbuf_size8_3_sram[1]:7 *C 71.400 88.695 +*N mux_tree_tapbuf_size8_3_sram[1]:8 *C 73.775 96.900 +*N mux_tree_tapbuf_size8_3_sram[1]:9 *C 73.600 96.900 +*N mux_tree_tapbuf_size8_3_sram[1]:10 *C 73.600 96.855 +*N mux_tree_tapbuf_size8_3_sram[1]:11 *C 75.502 94.520 +*N mux_tree_tapbuf_size8_3_sram[1]:12 *C 73.645 94.520 +*N mux_tree_tapbuf_size8_3_sram[1]:13 *C 73.600 94.520 +*N mux_tree_tapbuf_size8_3_sram[1]:14 *C 73.600 88.445 +*N mux_tree_tapbuf_size8_3_sram[1]:15 *C 73.555 88.400 +*N mux_tree_tapbuf_size8_3_sram[1]:16 *C 71.400 88.400 +*N mux_tree_tapbuf_size8_3_sram[1]:17 *C 64.500 88.400 +*N mux_tree_tapbuf_size8_3_sram[1]:18 *C 63.985 88.400 +*N mux_tree_tapbuf_size8_3_sram[1]:19 *C 63.940 88.355 +*N mux_tree_tapbuf_size8_3_sram[1]:20 *C 61.578 85.000 +*N mux_tree_tapbuf_size8_3_sram[1]:21 *C 63.895 85.000 +*N mux_tree_tapbuf_size8_3_sram[1]:22 *C 63.940 85.000 +*N mux_tree_tapbuf_size8_3_sram[1]:23 *C 63.940 83.005 +*N mux_tree_tapbuf_size8_3_sram[1]:24 *C 63.940 82.960 +*N mux_tree_tapbuf_size8_3_sram[1]:25 *C 64.245 82.960 + +*CAP +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_7\/mux_l2_in_0_:S 1e-06 +2 mux_right_ipin_7\/mux_l2_in_2_:S 1e-06 +3 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_right_ipin_7\/mux_l2_in_3_:S 1e-06 +5 mux_right_ipin_7\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size8_3_sram[1]:6 6.096255e-05 +7 mux_tree_tapbuf_size8_3_sram[1]:7 5.48902e-05 +8 mux_tree_tapbuf_size8_3_sram[1]:8 5.263971e-05 +9 mux_tree_tapbuf_size8_3_sram[1]:9 5.678855e-05 +10 mux_tree_tapbuf_size8_3_sram[1]:10 0.0001421468 +11 mux_tree_tapbuf_size8_3_sram[1]:11 0.0001456643 +12 mux_tree_tapbuf_size8_3_sram[1]:12 0.0001456643 +13 mux_tree_tapbuf_size8_3_sram[1]:13 0.0005134578 +14 mux_tree_tapbuf_size8_3_sram[1]:14 0.0003372921 +15 mux_tree_tapbuf_size8_3_sram[1]:15 0.0001405969 +16 mux_tree_tapbuf_size8_3_sram[1]:16 0.0006043275 +17 mux_tree_tapbuf_size8_3_sram[1]:17 0.0005160074 +18 mux_tree_tapbuf_size8_3_sram[1]:18 4.917598e-05 +19 mux_tree_tapbuf_size8_3_sram[1]:19 0.0001864318 +20 mux_tree_tapbuf_size8_3_sram[1]:20 0.0001911467 +21 mux_tree_tapbuf_size8_3_sram[1]:21 0.0001911467 +22 mux_tree_tapbuf_size8_3_sram[1]:22 0.0002909491 +23 mux_tree_tapbuf_size8_3_sram[1]:23 7.49877e-05 +24 mux_tree_tapbuf_size8_3_sram[1]:24 4.895093e-05 +25 mux_tree_tapbuf_size8_3_sram[1]:25 4.451106e-05 +26 mux_tree_tapbuf_size8_3_sram[1]:19 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.24301e-05 +27 mux_tree_tapbuf_size8_3_sram[1]:23 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.652307e-05 +28 mux_tree_tapbuf_size8_3_sram[1]:22 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.24301e-05 +29 mux_tree_tapbuf_size8_3_sram[1]:22 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.652307e-05 + +*RES +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_3_sram[1]:25 0.152 +1 mux_tree_tapbuf_size8_3_sram[1]:15 mux_tree_tapbuf_size8_3_sram[1]:14 0.0045 +2 mux_tree_tapbuf_size8_3_sram[1]:14 mux_tree_tapbuf_size8_3_sram[1]:13 0.005424107 +3 mux_tree_tapbuf_size8_3_sram[1]:12 mux_tree_tapbuf_size8_3_sram[1]:11 0.001658482 +4 mux_tree_tapbuf_size8_3_sram[1]:13 mux_tree_tapbuf_size8_3_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size8_3_sram[1]:13 mux_tree_tapbuf_size8_3_sram[1]:10 0.002084821 +6 mux_tree_tapbuf_size8_3_sram[1]:11 mux_right_ipin_7\/mux_l2_in_2_:S 0.152 +7 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:17 0.0004598215 +8 mux_tree_tapbuf_size8_3_sram[1]:19 mux_tree_tapbuf_size8_3_sram[1]:18 0.0045 +9 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:23 0.0045 +10 mux_tree_tapbuf_size8_3_sram[1]:23 mux_tree_tapbuf_size8_3_sram[1]:22 0.00178125 +11 mux_tree_tapbuf_size8_3_sram[1]:25 mux_tree_tapbuf_size8_3_sram[1]:24 0.0001657609 +12 mux_tree_tapbuf_size8_3_sram[1]:7 mux_right_ipin_7\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size8_3_sram[1]:9 mux_tree_tapbuf_size8_3_sram[1]:8 9.510871e-05 +14 mux_tree_tapbuf_size8_3_sram[1]:10 mux_tree_tapbuf_size8_3_sram[1]:9 0.0045 +15 mux_tree_tapbuf_size8_3_sram[1]:8 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size8_3_sram[1]:6 mux_right_ipin_7\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size8_3_sram[1]:21 mux_tree_tapbuf_size8_3_sram[1]:20 0.002069197 +18 mux_tree_tapbuf_size8_3_sram[1]:22 mux_tree_tapbuf_size8_3_sram[1]:21 0.0045 +19 mux_tree_tapbuf_size8_3_sram[1]:22 mux_tree_tapbuf_size8_3_sram[1]:19 0.002995536 +20 mux_tree_tapbuf_size8_3_sram[1]:20 mux_right_ipin_7\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:16 0.006160715 +22 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:6 0.0001271552 +23 mux_tree_tapbuf_size8_3_sram[1]:16 mux_tree_tapbuf_size8_3_sram[1]:15 0.001924107 +24 mux_tree_tapbuf_size8_3_sram[1]:16 mux_tree_tapbuf_size8_3_sram[1]:7 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_6_ccff_tail[0] 0.001569731 //LENGTH 14.460 LUMPCC 0.000209788 DR + +*CONN +*I mem_right_ipin_14\/FTB_16__55:X O *L 0 *C 51.295 55.080 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 56.295 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 *C 56.258 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 *C 50.645 47.940 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 *C 50.600 47.985 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 *C 50.600 55.035 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 *C 50.645 55.080 +*N mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 *C 51.258 55.080 + +*CAP +0 mem_right_ipin_14\/FTB_16__55:X 1e-06 +1 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 0.0003471229 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 0.0003471229 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.0002651387 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0002651387 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 6.671003e-05 +7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 6.671003e-05 +8 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 chany_top_in[6]:14 0.000104894 +9 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 chany_top_in[6]:11 0.000104894 + +*RES +0 mem_right_ipin_14\/FTB_16__55:X mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 0.000546875 +2 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 0.006294643 +4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 0.005011161 +5 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_6_ccff_tail[0]:2 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007587342 //LENGTH 5.710 LUMPCC 0.000126874 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_0_:X O *L 0 *C 32.375 78.200 +*I mux_right_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 32.105 83.300 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 32.105 83.300 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 32.200 83.255 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 32.200 78.245 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 32.200 78.200 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 32.375 78.200 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.821839e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002426717 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002426717 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.929231e-05 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.700602e-05 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.343699e-05 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.343699e-05 + +*RES +0 mux_right_ipin_0\/mux_l2_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.004473214 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00230546 //LENGTH 16.255 LUMPCC 0.0005526966 DR + +*CONN +*I mux_right_ipin_1\/mux_l3_in_0_:X O *L 0 *C 48.475 93.500 +*I mux_right_ipin_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 33.580 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 33.580 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 33.580 93.840 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 40.480 93.840 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 40.480 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 48.438 93.500 + +*CAP +0 mux_right_ipin_1\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_1\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.63535e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003444598 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003416665 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0005168144 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004914695 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.109209e-05 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.109209e-05 +9 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 optlc_net_132:5 5.203663e-05 +10 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 optlc_net_132:32 0.0001250916 +11 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 optlc_net_132:21 4.845091e-06 +12 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 optlc_net_132:22 3.282889e-06 +13 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 optlc_net_132:5 4.845091e-06 +14 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 optlc_net_132:21 3.282889e-06 +15 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 optlc_net_132:23 0.0001250916 +16 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 optlc_net_132:21 5.203663e-05 + +*RES +0 mux_right_ipin_1\/mux_l3_in_0_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_1\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.007104912 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003035715 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.006160714 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003035715 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006441934 //LENGTH 4.595 LUMPCC 0.0001105119 DR + +*CONN +*I mux_right_ipin_8\/mux_l1_in_0_:X O *L 0 *C 28.235 36.720 +*I mux_right_ipin_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 24.285 36.380 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 24.285 36.380 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 24.380 36.720 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.198 36.720 + +*CAP +0 mux_right_ipin_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.787308e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002511843 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000222624 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.525594e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.525594e-05 + +*RES +0 mux_right_ipin_8\/mux_l1_in_0_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003408482 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002908057 //LENGTH 25.100 LUMPCC 0.0003183404 DR + +*CONN +*I mux_right_ipin_9\/mux_l3_in_0_:X O *L 0 *C 67.795 21.080 +*I mux_right_ipin_9\/mux_l4_in_0_:A1 I *L 0.00198 *C 54.185 30.940 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 54.223 30.940 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 56.535 30.940 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 56.580 30.895 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 56.580 25.898 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 56.588 25.840 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 67.153 25.840 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 67.160 25.783 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 67.160 21.125 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 67.205 21.080 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 67.758 21.080 + +*CAP +0 mux_right_ipin_9\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_9\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001732881 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001732881 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002904735 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002904735 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004999128 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0004999128 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002675657 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0002675657 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:10 6.261845e-05 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:11 6.261845e-05 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[14]:29 0.0001591702 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_bottom_in[14]:30 0.0001591702 + +*RES +0 mux_right_ipin_9\/mux_l3_in_0_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_9\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002064732 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004462054 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001655183 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0045 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.004158482 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0004933036 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006540202 //LENGTH 4.215 LUMPCC 0.0002116015 DR + +*CONN +*I mux_right_ipin_13\/mux_l3_in_0_:X O *L 0 *C 44.445 17.680 +*I mux_right_ipin_13\/mux_l4_in_0_:A1 I *L 0.00198 *C 43.240 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 43.278 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 44.115 20.060 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 44.160 20.015 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 44.160 17.725 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 44.160 17.680 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 44.445 17.680 + +*CAP +0 mux_right_ipin_13\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_13\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 9.907882e-06 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.907882e-06 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001540865 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001540865 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.739053e-05 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.503942e-05 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_8_sram[3]:7 1.644621e-05 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_8_sram[3]:6 4.436166e-05 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_8_sram[3]:8 1.644621e-05 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_8_sram[3]:5 4.436166e-05 +12 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.312258e-07 +13 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.436166e-05 +14 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.436166e-05 +15 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.312258e-07 + +*RES +0 mux_right_ipin_13\/mux_l3_in_0_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001548913 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002044643 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0007477679 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_13\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002120844 //LENGTH 13.900 LUMPCC 0.001287778 DR + +*CONN +*I mux_right_ipin_6\/mux_l3_in_1_:X O *L 0 *C 30.075 59.160 +*I mux_right_ipin_6\/mux_l4_in_0_:A0 I *L 0.001631 *C 31.090 71.400 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 31.090 71.400 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 30.820 71.400 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 30.820 71.355 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 30.820 59.205 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 30.775 59.160 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 30.113 59.160 + +*CAP +0 mux_right_ipin_6\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_6\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.05284e-05 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.845245e-05 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002833047 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002833047 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.773754e-05 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.773754e-05 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_bottom_in[1]:49 0.0003290153 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_bottom_in[1]:48 0.0003290153 +10 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[1]:37 0.0003148739 +11 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[1]:43 0.0003148739 + +*RES +0 mux_right_ipin_6\/mux_l3_in_1_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005915179 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.01084821 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001467391 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_6\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002624716 //LENGTH 20.350 LUMPCC 0.0007892972 DR + +*CONN +*I mux_right_ipin_11\/mux_l4_in_0_:X O *L 0 *C 7.535 59.160 +*I mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.165 69.525 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.090 69.487 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 5.060 69.020 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 1.885 69.020 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 1.840 68.975 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 1.840 59.205 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 1.885 59.160 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 7.498 59.160 + +*CAP +0 mux_right_ipin_11\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.116936e-05 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002582169 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002170475 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002724183 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002724183 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0003860743 +8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0003860743 +9 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 left_grid_pin_8_[0]:4 0.0001507156 +10 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 left_grid_pin_8_[0]:3 0.0001507156 +11 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 left_grid_pin_10_[0]:5 0.0002439331 +12 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 left_grid_pin_10_[0]:4 0.0002439331 + +*RES +0 mux_right_ipin_11\/mux_l4_in_0_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.005011161 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.008723215 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002834822 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004174107 + +*END + +*D_NET ropt_net_175 0.001658463 //LENGTH 9.385 LUMPCC 0.0009693175 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 66.895 102.340 +*I ropt_mt_inst_784:A I *L 0.001766 *C 58.420 102.000 +*N ropt_net_175:2 *C 58.458 102.000 +*N ropt_net_175:3 *C 59.340 102.000 +*N ropt_net_175:4 *C 59.340 102.340 +*N ropt_net_175:5 *C 66.858 102.340 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 ropt_mt_inst_784:A 1e-06 +2 ropt_net_175:2 9.354705e-05 +3 ropt_net_175:3 0.0001204508 +4 ropt_net_175:4 0.0002500259 +5 ropt_net_175:5 0.0002231222 +6 ropt_net_175:5 chany_bottom_in[11]:5 0.0001278706 +7 ropt_net_175:4 chany_bottom_in[11]:6 0.0001278706 +8 ropt_net_175:5 ropt_net_182:6 0.0002537775 +9 ropt_net_175:4 ropt_net_182:5 0.0002537775 +10 ropt_net_175:5 ropt_net_145:2 0.0001030106 +11 ropt_net_175:4 ropt_net_145:3 0.0001030106 + +*RES +0 ropt_mt_inst_737:X ropt_net_175:5 0.152 +1 ropt_net_175:5 ropt_net_175:4 0.006712054 +2 ropt_net_175:2 ropt_mt_inst_784:A 0.152 +3 ropt_net_175:3 ropt_net_175:2 0.0007879465 +4 ropt_net_175:4 ropt_net_175:3 0.0003035715 + +*END + +*D_NET chany_bottom_out[13] 0.0005053064 //LENGTH 3.670 LUMPCC 0 DR + +*CONN +*I FTB_34__33:X O *L 0 *C 34.960 3.740 +*P chany_bottom_out[13] O *L 0.7423 *C 34.960 1.290 +*N chany_bottom_out[13]:2 *C 34.040 3.740 +*N chany_bottom_out[13]:3 *C 34.960 3.695 +*N chany_bottom_out[13]:4 *C 34.922 3.740 + +*CAP +0 FTB_34__33:X 1e-06 +1 chany_bottom_out[13] 0.0001513343 +2 chany_bottom_out[13]:2 0.0001008188 +3 chany_bottom_out[13]:3 0.0001513343 +4 chany_bottom_out[13]:4 0.0001008188 + +*RES +0 FTB_34__33:X chany_bottom_out[13]:4 0.152 +1 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.0045 +2 chany_bottom_out[13]:4 chany_bottom_out[13]:2 0.0007879465 +3 chany_bottom_out[13]:3 chany_bottom_out[13] 0.002147322 + +*END + +*D_NET ropt_net_170 0.001395447 //LENGTH 9.560 LUMPCC 0.0001418582 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 28.255 9.180 +*I ropt_mt_inst_779:A I *L 0.001767 *C 26.220 6.800 +*N ropt_net_170:2 *C 26.183 6.800 +*N ropt_net_170:3 *C 25.345 6.800 +*N ropt_net_170:4 *C 25.300 6.755 +*N ropt_net_170:5 *C 25.300 6.178 +*N ropt_net_170:6 *C 25.308 6.120 +*N ropt_net_170:7 *C 28.520 6.120 +*N ropt_net_170:8 *C 28.520 6.178 +*N ropt_net_170:9 *C 28.520 9.135 +*N ropt_net_170:10 *C 28.520 9.180 +*N ropt_net_170:11 *C 28.255 9.180 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_170:2 9.550349e-05 +3 ropt_net_170:3 9.550349e-05 +4 ropt_net_170:4 6.924216e-05 +5 ropt_net_170:5 6.924216e-05 +6 ropt_net_170:6 0.0002070581 +7 ropt_net_170:7 0.0002070581 +8 ropt_net_170:8 0.0001978176 +9 ropt_net_170:9 0.0001978176 +10 ropt_net_170:10 5.895631e-05 +11 ropt_net_170:11 5.339021e-05 +12 ropt_net_170:9 ropt_net_178:9 8.915006e-06 +13 ropt_net_170:8 ropt_net_178:8 8.915006e-06 +14 ropt_net_170:7 ropt_net_178:7 5.576348e-05 +15 ropt_net_170:6 ropt_net_178:6 5.576348e-05 +16 ropt_net_170:3 ropt_net_178:11 6.250586e-06 +17 ropt_net_170:2 ropt_net_178:10 6.250586e-06 + +*RES +0 ropt_mt_inst_754:X ropt_net_170:11 0.152 +1 ropt_net_170:11 ropt_net_170:10 0.0001440218 +2 ropt_net_170:10 ropt_net_170:9 0.0045 +3 ropt_net_170:9 ropt_net_170:8 0.002640625 +4 ropt_net_170:8 ropt_net_170:7 0.00341 +5 ropt_net_170:7 ropt_net_170:6 0.0005032916 +6 ropt_net_170:5 ropt_net_170:4 0.0005156251 +7 ropt_net_170:6 ropt_net_170:5 0.00341 +8 ropt_net_170:3 ropt_net_170:2 0.0007477679 +9 ropt_net_170:4 ropt_net_170:3 0.0045 +10 ropt_net_170:2 ropt_mt_inst_779:A 0.152 + +*END + +*D_NET ropt_net_184 0.001765448 //LENGTH 13.145 LUMPCC 0.0001161252 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 35.155 98.600 +*I ropt_mt_inst_800:A I *L 0.001766 *C 32.660 104.720 +*N ropt_net_184:2 *C 32.698 104.720 +*N ropt_net_184:3 *C 33.995 104.720 +*N ropt_net_184:4 *C 34.040 104.675 +*N ropt_net_184:5 *C 34.040 104.085 +*N ropt_net_184:6 *C 34.085 104.040 +*N ropt_net_184:7 *C 36.295 104.040 +*N ropt_net_184:8 *C 36.340 104.040 +*N ropt_net_184:9 *C 36.340 98.645 +*N ropt_net_184:10 *C 36.295 98.600 +*N ropt_net_184:11 *C 35.193 98.600 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_184:2 0.000123677 +3 ropt_net_184:3 0.000123677 +4 ropt_net_184:4 5.808325e-05 +5 ropt_net_184:5 5.808325e-05 +6 ropt_net_184:6 0.0001758301 +7 ropt_net_184:7 0.0001758301 +8 ropt_net_184:8 0.0003667924 +9 ropt_net_184:9 0.0003327062 +10 ropt_net_184:10 0.0001163221 +11 ropt_net_184:11 0.0001163221 +12 ropt_net_184:8 chany_top_in[16] 5.806258e-05 +13 ropt_net_184:9 chany_top_in[16]:47 5.806258e-05 + +*RES +0 ropt_mt_inst_772:X ropt_net_184:11 0.152 +1 ropt_net_184:2 ropt_mt_inst_800:A 0.152 +2 ropt_net_184:3 ropt_net_184:2 0.001158482 +3 ropt_net_184:4 ropt_net_184:3 0.0045 +4 ropt_net_184:6 ropt_net_184:5 0.0045 +5 ropt_net_184:5 ropt_net_184:4 0.0005267857 +6 ropt_net_184:7 ropt_net_184:6 0.001973214 +7 ropt_net_184:8 ropt_net_184:7 0.0045 +8 ropt_net_184:10 ropt_net_184:9 0.0045 +9 ropt_net_184:9 ropt_net_184:8 0.004816964 +10 ropt_net_184:11 ropt_net_184:10 0.000984375 + +*END + +*D_NET ropt_net_149 0.002135575 //LENGTH 15.655 LUMPCC 0.0009639125 DR + +*CONN +*I BUFT_P_118:X O *L 0 *C 28.060 14.620 +*I ropt_mt_inst_748:A I *L 0.001766 *C 21.620 6.800 +*N ropt_net_149:2 *C 21.658 6.800 +*N ropt_net_149:3 *C 24.335 6.800 +*N ropt_net_149:4 *C 24.380 6.845 +*N ropt_net_149:5 *C 24.380 14.575 +*N ropt_net_149:6 *C 24.425 14.620 +*N ropt_net_149:7 *C 28.060 14.620 + +*CAP +0 BUFT_P_118:X 1e-06 +1 ropt_mt_inst_748:A 1e-06 +2 ropt_net_149:2 2.609738e-05 +3 ropt_net_149:3 2.609738e-05 +4 ropt_net_149:4 0.0002749427 +5 ropt_net_149:5 0.0002749427 +6 ropt_net_149:6 0.0002669659 +7 ropt_net_149:7 0.0003006165 +8 ropt_net_149:5 chany_top_in[1]:18 9.3968e-05 +9 ropt_net_149:3 chany_top_in[1]:16 0.0001127532 +10 ropt_net_149:4 chany_top_in[1]:17 9.3968e-05 +11 ropt_net_149:2 chany_top_in[1]:15 0.0001127532 +12 ropt_net_149:5 mux_tree_tapbuf_size10_7_sram[1]:16 0.0001013168 +13 ropt_net_149:5 mux_tree_tapbuf_size10_7_sram[1]:17 5.588108e-05 +14 ropt_net_149:4 mux_tree_tapbuf_size10_7_sram[1]:13 0.0001013168 +15 ropt_net_149:4 mux_tree_tapbuf_size10_7_sram[1]:16 5.588108e-05 +16 ropt_net_149:5 ropt_net_155:4 5.283881e-06 +17 ropt_net_149:3 ropt_net_155:6 0.0001127532 +18 ropt_net_149:4 ropt_net_155:5 5.283881e-06 +19 ropt_net_149:2 ropt_net_155:7 0.0001127532 + +*RES +0 BUFT_P_118:X ropt_net_149:7 0.152 +1 ropt_net_149:7 ropt_net_149:6 0.003245536 +2 ropt_net_149:6 ropt_net_149:5 0.0045 +3 ropt_net_149:5 ropt_net_149:4 0.006901786 +4 ropt_net_149:3 ropt_net_149:2 0.002390625 +5 ropt_net_149:4 ropt_net_149:3 0.0045 +6 ropt_net_149:2 ropt_mt_inst_748:A 0.152 + +*END + +*D_NET chany_bottom_in[7] 0.01889928 //LENGTH 139.900 LUMPCC 0.005991215 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 21.620 1.290 +*I mux_right_ipin_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 18.690 87.720 +*I BUFT_P_110:A I *L 0.001776 *C 45.080 99.280 +*I mux_right_ipin_10\/mux_l2_in_1_:A0 I *L 0.001631 *C 16.850 33.660 +*I mux_right_ipin_12\/mux_l1_in_2_:A1 I *L 0.00198 *C 17.020 12.580 +*N chany_bottom_in[7]:5 *C 17.058 12.580 +*N chany_bottom_in[7]:6 *C 17.480 12.580 +*N chany_bottom_in[7]:7 *C 16.850 33.660 +*N chany_bottom_in[7]:8 *C 17.020 33.660 +*N chany_bottom_in[7]:9 *C 17.020 33.660 +*N chany_bottom_in[7]:10 *C 45.080 99.280 +*N chany_bottom_in[7]:11 *C 45.080 99.325 +*N chany_bottom_in[7]:12 *C 45.080 99.903 +*N chany_bottom_in[7]:13 *C 45.073 99.960 +*N chany_bottom_in[7]:14 *C 21.180 99.960 +*N chany_bottom_in[7]:15 *C 21.160 99.953 +*N chany_bottom_in[7]:16 *C 21.160 87.728 +*N chany_bottom_in[7]:17 *C 21.140 87.720 +*N chany_bottom_in[7]:18 *C 18.690 87.720 +*N chany_bottom_in[7]:19 *C 18.400 87.720 +*N chany_bottom_in[7]:20 *C 18.400 87.720 +*N chany_bottom_in[7]:21 *C 18.400 87.720 +*N chany_bottom_in[7]:22 *C 15.660 87.720 +*N chany_bottom_in[7]:23 *C 15.640 87.713 +*N chany_bottom_in[7]:24 *C 15.640 33.328 +*N chany_bottom_in[7]:25 *C 15.660 33.320 +*N chany_bottom_in[7]:26 *C 17.012 33.320 +*N chany_bottom_in[7]:27 *C 17.020 33.320 +*N chany_bottom_in[7]:28 *C 17.480 33.320 +*N chany_bottom_in[7]:29 *C 17.480 12.965 +*N chany_bottom_in[7]:30 *C 17.480 12.920 +*N chany_bottom_in[7]:31 *C 21.575 12.920 +*N chany_bottom_in[7]:32 *C 21.620 12.875 + +*CAP +0 chany_bottom_in[7] 0.0006716472 +1 mux_right_ipin_2\/mux_l2_in_1_:A0 1e-06 +2 BUFT_P_110:A 1e-06 +3 mux_right_ipin_10\/mux_l2_in_1_:A0 1e-06 +4 mux_right_ipin_12\/mux_l1_in_2_:A1 1e-06 +5 chany_bottom_in[7]:5 5.017813e-05 +6 chany_bottom_in[7]:6 7.895492e-05 +7 chany_bottom_in[7]:7 4.31814e-05 +8 chany_bottom_in[7]:8 4.564127e-05 +9 chany_bottom_in[7]:9 5.394482e-05 +10 chany_bottom_in[7]:10 4.024831e-05 +11 chany_bottom_in[7]:11 7.609121e-05 +12 chany_bottom_in[7]:12 7.609121e-05 +13 chany_bottom_in[7]:13 0.001035611 +14 chany_bottom_in[7]:14 0.001035611 +15 chany_bottom_in[7]:15 0.0006380978 +16 chany_bottom_in[7]:16 0.0006380978 +17 chany_bottom_in[7]:17 0.0001693289 +18 chany_bottom_in[7]:18 4.824917e-05 +19 chany_bottom_in[7]:19 5.209167e-05 +20 chany_bottom_in[7]:20 3.389038e-05 +21 chany_bottom_in[7]:21 0.0003449363 +22 chany_bottom_in[7]:22 0.0001756074 +23 chany_bottom_in[7]:23 0.001985289 +24 chany_bottom_in[7]:24 0.001985289 +25 chany_bottom_in[7]:25 0.0001128374 +26 chany_bottom_in[7]:26 0.0001128374 +27 chany_bottom_in[7]:27 8.901396e-05 +28 chany_bottom_in[7]:28 0.001018253 +29 chany_bottom_in[7]:29 0.0009848684 +30 chany_bottom_in[7]:30 0.0003326514 +31 chany_bottom_in[7]:31 0.0003038746 +32 chany_bottom_in[7]:32 0.0006716472 +33 chany_bottom_in[7]:13 chany_top_in[3]:63 0.0004557755 +34 chany_bottom_in[7]:14 chany_top_in[3]:62 0.0004557755 +35 chany_bottom_in[7]:8 chany_top_in[3]:28 5.66551e-06 +36 chany_bottom_in[7]:7 chany_top_in[3]:27 5.66551e-06 +37 chany_bottom_in[7] chany_top_in[7]:17 1.990844e-06 +38 chany_bottom_in[7]:27 chany_top_in[7]:28 5.24995e-07 +39 chany_bottom_in[7]:24 chany_top_in[7]:32 0.001099852 +40 chany_bottom_in[7]:24 chany_top_in[7]:33 1.394608e-05 +41 chany_bottom_in[7]:23 chany_top_in[7]:34 1.394608e-05 +42 chany_bottom_in[7]:23 chany_top_in[7]:33 0.001099852 +43 chany_bottom_in[7]:29 chany_top_in[7]:24 2.995718e-06 +44 chany_bottom_in[7]:29 chany_top_in[7]:28 4.632697e-06 +45 chany_bottom_in[7]:15 chany_top_in[7]:34 6.771433e-05 +46 chany_bottom_in[7]:15 chany_top_in[7]:40 5.7283e-06 +47 chany_bottom_in[7]:16 chany_top_in[7]:39 5.7283e-06 +48 chany_bottom_in[7]:16 chany_top_in[7]:33 6.771433e-05 +49 chany_bottom_in[7]:5 chany_top_in[7]:23 1.775493e-08 +50 chany_bottom_in[7]:9 chany_top_in[7]:29 5.24995e-07 +51 chany_bottom_in[7]:32 chany_top_in[7]:18 1.990844e-06 +52 chany_bottom_in[7]:6 chany_top_in[7]:22 1.775493e-08 +53 chany_bottom_in[7]:28 chany_top_in[7]:29 4.632697e-06 +54 chany_bottom_in[7]:28 chany_top_in[7]:25 2.995718e-06 +55 chany_bottom_in[7]:29 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.001156e-05 +56 chany_bottom_in[7]:28 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.001156e-05 +57 chany_bottom_in[7]:13 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001296752 +58 chany_bottom_in[7]:14 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001296752 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:32 0.01034375 +1 chany_bottom_in[7]:27 chany_bottom_in[7]:26 0.00341 +2 chany_bottom_in[7]:27 chany_bottom_in[7]:9 0.0001634615 +3 chany_bottom_in[7]:26 chany_bottom_in[7]:25 0.0002118916 +4 chany_bottom_in[7]:25 chany_bottom_in[7]:24 0.00341 +5 chany_bottom_in[7]:24 chany_bottom_in[7]:23 0.008520316 +6 chany_bottom_in[7]:22 chany_bottom_in[7]:21 0.0004292666 +7 chany_bottom_in[7]:23 chany_bottom_in[7]:22 0.00341 +8 chany_bottom_in[7]:30 chany_bottom_in[7]:29 0.0045 +9 chany_bottom_in[7]:30 chany_bottom_in[7]:6 0.0003035714 +10 chany_bottom_in[7]:29 chany_bottom_in[7]:28 0.01817411 +11 chany_bottom_in[7]:10 BUFT_P_110:A 0.152 +12 chany_bottom_in[7]:11 chany_bottom_in[7]:10 0.0045 +13 chany_bottom_in[7]:12 chany_bottom_in[7]:11 0.000515625 +14 chany_bottom_in[7]:13 chany_bottom_in[7]:12 0.00341 +15 chany_bottom_in[7]:14 chany_bottom_in[7]:13 0.003743158 +16 chany_bottom_in[7]:15 chany_bottom_in[7]:14 0.00341 +17 chany_bottom_in[7]:17 chany_bottom_in[7]:16 0.00341 +18 chany_bottom_in[7]:16 chany_bottom_in[7]:15 0.00191525 +19 chany_bottom_in[7]:5 mux_right_ipin_12\/mux_l1_in_2_:A1 0.152 +20 chany_bottom_in[7]:20 chany_bottom_in[7]:19 0.0045 +21 chany_bottom_in[7]:21 chany_bottom_in[7]:20 0.00341 +22 chany_bottom_in[7]:21 chany_bottom_in[7]:17 0.0004292666 +23 chany_bottom_in[7]:19 chany_bottom_in[7]:18 0.0001576087 +24 chany_bottom_in[7]:18 mux_right_ipin_2\/mux_l2_in_1_:A0 0.152 +25 chany_bottom_in[7]:8 chany_bottom_in[7]:7 9.239132e-05 +26 chany_bottom_in[7]:9 chany_bottom_in[7]:8 0.0045 +27 chany_bottom_in[7]:7 mux_right_ipin_10\/mux_l2_in_1_:A0 0.152 +28 chany_bottom_in[7]:31 chany_bottom_in[7]:30 0.00365625 +29 chany_bottom_in[7]:32 chany_bottom_in[7]:31 0.0045 +30 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.0003772322 +31 chany_bottom_in[7]:28 chany_bottom_in[7]:27 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[3] 0.00305153 //LENGTH 16.480 LUMPCC 0.001484755 DR + +*CONN +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 33.425 96.560 +*I mem_right_ipin_1\/FTB_3__42:A I *L 0.001746 *C 22.540 96.560 +*I mux_right_ipin_1\/mux_l4_in_0_:S I *L 0.00357 *C 32.300 94.520 +*N mux_tree_tapbuf_size10_2_sram[3]:3 *C 32.315 94.520 +*N mux_tree_tapbuf_size10_2_sram[3]:4 *C 32.638 94.520 +*N mux_tree_tapbuf_size10_2_sram[3]:5 *C 32.660 94.565 +*N mux_tree_tapbuf_size10_2_sram[3]:6 *C 32.660 95.880 +*N mux_tree_tapbuf_size10_2_sram[3]:7 *C 22.578 96.560 +*N mux_tree_tapbuf_size10_2_sram[3]:8 *C 23.875 96.560 +*N mux_tree_tapbuf_size10_2_sram[3]:9 *C 23.920 96.515 +*N mux_tree_tapbuf_size10_2_sram[3]:10 *C 23.920 95.938 +*N mux_tree_tapbuf_size10_2_sram[3]:11 *C 23.928 95.880 +*N mux_tree_tapbuf_size10_2_sram[3]:12 *C 33.113 95.880 +*N mux_tree_tapbuf_size10_2_sram[3]:13 *C 33.120 95.938 +*N mux_tree_tapbuf_size10_2_sram[3]:14 *C 33.120 96.515 +*N mux_tree_tapbuf_size10_2_sram[3]:15 *C 33.120 96.560 +*N mux_tree_tapbuf_size10_2_sram[3]:16 *C 33.425 96.560 + +*CAP +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_1\/FTB_3__42:A 1e-06 +2 mux_right_ipin_1\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_2_sram[3]:3 5.090012e-05 +4 mux_tree_tapbuf_size10_2_sram[3]:4 5.090012e-05 +5 mux_tree_tapbuf_size10_2_sram[3]:5 7.430247e-05 +6 mux_tree_tapbuf_size10_2_sram[3]:6 0.0001100707 +7 mux_tree_tapbuf_size10_2_sram[3]:7 9.375153e-05 +8 mux_tree_tapbuf_size10_2_sram[3]:8 9.375153e-05 +9 mux_tree_tapbuf_size10_2_sram[3]:9 5.794838e-05 +10 mux_tree_tapbuf_size10_2_sram[3]:10 5.794838e-05 +11 mux_tree_tapbuf_size10_2_sram[3]:11 0.0003636001 +12 mux_tree_tapbuf_size10_2_sram[3]:12 0.0003636001 +13 mux_tree_tapbuf_size10_2_sram[3]:13 9.113463e-05 +14 mux_tree_tapbuf_size10_2_sram[3]:14 5.536634e-05 +15 mux_tree_tapbuf_size10_2_sram[3]:15 5.280825e-05 +16 mux_tree_tapbuf_size10_2_sram[3]:16 4.769232e-05 +17 mux_tree_tapbuf_size10_2_sram[3]:14 chany_top_in[7] 6.723308e-06 +18 mux_tree_tapbuf_size10_2_sram[3]:5 chany_top_in[7]:42 2.373196e-05 +19 mux_tree_tapbuf_size10_2_sram[3]:13 chany_top_in[7]:42 6.723308e-06 +20 mux_tree_tapbuf_size10_2_sram[3]:12 chany_top_in[7]:41 0.0004523784 +21 mux_tree_tapbuf_size10_2_sram[3]:11 chany_top_in[7]:40 0.0004523784 +22 mux_tree_tapbuf_size10_2_sram[3]:6 chany_top_in[7] 2.373196e-05 +23 mux_tree_tapbuf_size10_2_sram[3]:12 prog_clk[0]:375 0.0002595438 +24 mux_tree_tapbuf_size10_2_sram[3]:11 prog_clk[0]:376 0.0002595438 + +*RES +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_2_sram[3]:16 0.152 +1 mux_tree_tapbuf_size10_2_sram[3]:15 mux_tree_tapbuf_size10_2_sram[3]:14 0.0045 +2 mux_tree_tapbuf_size10_2_sram[3]:14 mux_tree_tapbuf_size10_2_sram[3]:13 0.000515625 +3 mux_tree_tapbuf_size10_2_sram[3]:16 mux_tree_tapbuf_size10_2_sram[3]:15 0.0001657609 +4 mux_tree_tapbuf_size10_2_sram[3]:4 mux_tree_tapbuf_size10_2_sram[3]:3 0.0001752718 +5 mux_tree_tapbuf_size10_2_sram[3]:5 mux_tree_tapbuf_size10_2_sram[3]:4 0.0045 +6 mux_tree_tapbuf_size10_2_sram[3]:3 mux_right_ipin_1\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_2_sram[3]:13 mux_tree_tapbuf_size10_2_sram[3]:12 0.00341 +8 mux_tree_tapbuf_size10_2_sram[3]:13 mux_tree_tapbuf_size10_2_sram[3]:6 0.0004107143 +9 mux_tree_tapbuf_size10_2_sram[3]:12 mux_tree_tapbuf_size10_2_sram[3]:11 0.001438983 +10 mux_tree_tapbuf_size10_2_sram[3]:10 mux_tree_tapbuf_size10_2_sram[3]:9 0.000515625 +11 mux_tree_tapbuf_size10_2_sram[3]:11 mux_tree_tapbuf_size10_2_sram[3]:10 0.00341 +12 mux_tree_tapbuf_size10_2_sram[3]:8 mux_tree_tapbuf_size10_2_sram[3]:7 0.001158482 +13 mux_tree_tapbuf_size10_2_sram[3]:9 mux_tree_tapbuf_size10_2_sram[3]:8 0.0045 +14 mux_tree_tapbuf_size10_2_sram[3]:7 mem_right_ipin_1\/FTB_3__42:A 0.152 +15 mux_tree_tapbuf_size10_2_sram[3]:6 mux_tree_tapbuf_size10_2_sram[3]:5 0.001174107 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[2] 0.0061069 //LENGTH 50.760 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 75.745 36.720 +*I mux_right_ipin_9\/mux_l3_in_1_:S I *L 0.00357 *C 64.040 25.840 +*I mux_right_ipin_9\/mux_l3_in_0_:S I *L 0.00357 *C 68.640 20.400 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 53.995 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:4 *C 53.995 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:5 *C 54.280 39.100 +*N mux_tree_tapbuf_size10_6_sram[2]:6 *C 54.280 39.055 +*N mux_tree_tapbuf_size10_6_sram[2]:7 *C 54.280 33.365 +*N mux_tree_tapbuf_size10_6_sram[2]:8 *C 54.325 33.320 +*N mux_tree_tapbuf_size10_6_sram[2]:9 *C 68.603 20.400 +*N mux_tree_tapbuf_size10_6_sram[2]:10 *C 68.125 20.400 +*N mux_tree_tapbuf_size10_6_sram[2]:11 *C 68.080 20.445 +*N mux_tree_tapbuf_size10_6_sram[2]:12 *C 64.078 25.840 +*N mux_tree_tapbuf_size10_6_sram[2]:13 *C 68.035 25.840 +*N mux_tree_tapbuf_size10_6_sram[2]:14 *C 68.080 25.840 +*N mux_tree_tapbuf_size10_6_sram[2]:15 *C 68.080 33.275 +*N mux_tree_tapbuf_size10_6_sram[2]:16 *C 68.080 33.350 +*N mux_tree_tapbuf_size10_6_sram[2]:17 *C 68.080 33.660 +*N mux_tree_tapbuf_size10_6_sram[2]:18 *C 75.395 33.660 +*N mux_tree_tapbuf_size10_6_sram[2]:19 *C 75.440 33.705 +*N mux_tree_tapbuf_size10_6_sram[2]:20 *C 75.440 36.675 +*N mux_tree_tapbuf_size10_6_sram[2]:21 *C 75.440 36.720 +*N mux_tree_tapbuf_size10_6_sram[2]:22 *C 75.745 36.720 + +*CAP +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_9\/mux_l3_in_1_:S 1e-06 +2 mux_right_ipin_9\/mux_l3_in_0_:S 1e-06 +3 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_6_sram[2]:4 4.678359e-05 +5 mux_tree_tapbuf_size10_6_sram[2]:5 5.095352e-05 +6 mux_tree_tapbuf_size10_6_sram[2]:6 0.0003205935 +7 mux_tree_tapbuf_size10_6_sram[2]:7 0.0003205935 +8 mux_tree_tapbuf_size10_6_sram[2]:8 0.0008606531 +9 mux_tree_tapbuf_size10_6_sram[2]:9 6.236492e-05 +10 mux_tree_tapbuf_size10_6_sram[2]:10 6.236492e-05 +11 mux_tree_tapbuf_size10_6_sram[2]:11 0.0003030411 +12 mux_tree_tapbuf_size10_6_sram[2]:12 0.0002612673 +13 mux_tree_tapbuf_size10_6_sram[2]:13 0.0002612673 +14 mux_tree_tapbuf_size10_6_sram[2]:14 0.0007965746 +15 mux_tree_tapbuf_size10_6_sram[2]:15 0.0004657728 +16 mux_tree_tapbuf_size10_6_sram[2]:16 0.0008885746 +17 mux_tree_tapbuf_size10_6_sram[2]:17 0.0004594357 +18 mux_tree_tapbuf_size10_6_sram[2]:18 0.0004315141 +19 mux_tree_tapbuf_size10_6_sram[2]:19 0.0002039801 +20 mux_tree_tapbuf_size10_6_sram[2]:20 0.0002039801 +21 mux_tree_tapbuf_size10_6_sram[2]:21 5.367745e-05 +22 mux_tree_tapbuf_size10_6_sram[2]:22 4.950659e-05 + +*RES +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_6_sram[2]:22 0.152 +1 mux_tree_tapbuf_size10_6_sram[2]:18 mux_tree_tapbuf_size10_6_sram[2]:17 0.006531251 +2 mux_tree_tapbuf_size10_6_sram[2]:19 mux_tree_tapbuf_size10_6_sram[2]:18 0.0045 +3 mux_tree_tapbuf_size10_6_sram[2]:21 mux_tree_tapbuf_size10_6_sram[2]:20 0.0045 +4 mux_tree_tapbuf_size10_6_sram[2]:20 mux_tree_tapbuf_size10_6_sram[2]:19 0.002651786 +5 mux_tree_tapbuf_size10_6_sram[2]:22 mux_tree_tapbuf_size10_6_sram[2]:21 0.0001657609 +6 mux_tree_tapbuf_size10_6_sram[2]:16 mux_tree_tapbuf_size10_6_sram[2]:15 0.0045 +7 mux_tree_tapbuf_size10_6_sram[2]:16 mux_tree_tapbuf_size10_6_sram[2]:8 0.01228125 +8 mux_tree_tapbuf_size10_6_sram[2]:15 mux_tree_tapbuf_size10_6_sram[2]:14 0.006638394 +9 mux_tree_tapbuf_size10_6_sram[2]:13 mux_tree_tapbuf_size10_6_sram[2]:12 0.003533482 +10 mux_tree_tapbuf_size10_6_sram[2]:14 mux_tree_tapbuf_size10_6_sram[2]:13 0.0045 +11 mux_tree_tapbuf_size10_6_sram[2]:14 mux_tree_tapbuf_size10_6_sram[2]:11 0.004816964 +12 mux_tree_tapbuf_size10_6_sram[2]:12 mux_right_ipin_9\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[2]:10 mux_tree_tapbuf_size10_6_sram[2]:9 0.0004263393 +14 mux_tree_tapbuf_size10_6_sram[2]:11 mux_tree_tapbuf_size10_6_sram[2]:10 0.0045 +15 mux_tree_tapbuf_size10_6_sram[2]:9 mux_right_ipin_9\/mux_l3_in_0_:S 0.152 +16 mux_tree_tapbuf_size10_6_sram[2]:8 mux_tree_tapbuf_size10_6_sram[2]:7 0.0045 +17 mux_tree_tapbuf_size10_6_sram[2]:7 mux_tree_tapbuf_size10_6_sram[2]:6 0.005080357 +18 mux_tree_tapbuf_size10_6_sram[2]:5 mux_tree_tapbuf_size10_6_sram[2]:4 0.0001548913 +19 mux_tree_tapbuf_size10_6_sram[2]:6 mux_tree_tapbuf_size10_6_sram[2]:5 0.0045 +20 mux_tree_tapbuf_size10_6_sram[2]:4 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +21 mux_tree_tapbuf_size10_6_sram[2]:17 mux_tree_tapbuf_size10_6_sram[2]:16 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_1_ccff_tail[0] 0.003051198 //LENGTH 22.340 LUMPCC 0.0002300973 DR + +*CONN +*I mem_right_ipin_0\/FTB_2__41:X O *L 0 *C 31.975 86.360 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 48.015 82.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 *C 48.015 82.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 *C 47.840 82.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 *C 47.840 82.665 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 *C 47.840 86.983 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 *C 47.833 87.040 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 *C 32.208 87.040 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 *C 32.200 86.983 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 *C 32.200 86.405 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 *C 32.200 86.360 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 *C 31.975 86.360 + +*CAP +0 mem_right_ipin_0\/FTB_2__41:X 1e-06 +1 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 5.371241e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 5.885145e-05 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0002640856 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0002640856 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.0009796754 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.0009796754 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 5.501826e-05 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 5.501826e-05 +10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 5.469213e-05 +11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 5.42855e-05 +12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 optlc_net_132:14 0.0001150487 +13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 optlc_net_132:13 0.0001150487 + +*RES +0 mem_right_ipin_0\/FTB_2__41:X mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 9.510871e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.003854911 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.00341 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.00341 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.002447916 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 0.0045 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:8 0.000515625 +10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:10 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[3] 0.001104363 //LENGTH 9.165 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 13.185 69.360 +*I mux_right_ipin_3\/mux_l4_in_0_:S I *L 0.008363 *C 14.260 63.695 +*I mem_right_ipin_3\/FTB_11__50:A I *L 0.001746 *C 15.640 69.360 +*N mux_tree_tapbuf_size8_1_sram[3]:3 *C 15.603 69.360 +*N mux_tree_tapbuf_size8_1_sram[3]:4 *C 14.260 63.580 +*N mux_tree_tapbuf_size8_1_sram[3]:5 *C 14.260 63.625 +*N mux_tree_tapbuf_size8_1_sram[3]:6 *C 14.260 69.315 +*N mux_tree_tapbuf_size8_1_sram[3]:7 *C 14.260 69.360 +*N mux_tree_tapbuf_size8_1_sram[3]:8 *C 13.223 69.360 + +*CAP +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_3\/mux_l4_in_0_:S 2.416033e-05 +2 mem_right_ipin_3\/FTB_11__50:A 1e-06 +3 mux_tree_tapbuf_size8_1_sram[3]:3 9.253902e-05 +4 mux_tree_tapbuf_size8_1_sram[3]:4 2.416033e-05 +5 mux_tree_tapbuf_size8_1_sram[3]:5 0.0003447722 +6 mux_tree_tapbuf_size8_1_sram[3]:6 0.0003447722 +7 mux_tree_tapbuf_size8_1_sram[3]:7 0.0001993256 +8 mux_tree_tapbuf_size8_1_sram[3]:8 7.26339e-05 + +*RES +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_1_sram[3]:8 0.152 +1 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:7 0.0009263393 +2 mux_tree_tapbuf_size8_1_sram[3]:4 mux_right_ipin_3\/mux_l4_in_0_:S 5.078125e-05 +3 mux_tree_tapbuf_size8_1_sram[3]:5 mux_tree_tapbuf_size8_1_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size8_1_sram[3]:7 mux_tree_tapbuf_size8_1_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size8_1_sram[3]:7 mux_tree_tapbuf_size8_1_sram[3]:3 0.001198661 +6 mux_tree_tapbuf_size8_1_sram[3]:6 mux_tree_tapbuf_size8_1_sram[3]:5 0.005080357 +7 mux_tree_tapbuf_size8_1_sram[3]:3 mem_right_ipin_3\/FTB_11__50:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[0] 0.001819644 //LENGTH 14.270 LUMPCC 0.000237287 DR + +*CONN +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.205 80.240 +*I mux_right_ipin_7\/mux_l1_in_0_:S I *L 0.00357 *C 59.240 78.200 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 58.560 82.620 +*N mux_tree_tapbuf_size8_3_sram[0]:3 *C 58.538 82.593 +*N mux_tree_tapbuf_size8_3_sram[0]:4 *C 58.525 82.280 +*N mux_tree_tapbuf_size8_3_sram[0]:5 *C 56.165 82.280 +*N mux_tree_tapbuf_size8_3_sram[0]:6 *C 56.120 82.235 +*N mux_tree_tapbuf_size8_3_sram[0]:7 *C 59.203 78.200 +*N mux_tree_tapbuf_size8_3_sram[0]:8 *C 56.165 78.200 +*N mux_tree_tapbuf_size8_3_sram[0]:9 *C 56.120 78.245 +*N mux_tree_tapbuf_size8_3_sram[0]:10 *C 56.120 80.240 +*N mux_tree_tapbuf_size8_3_sram[0]:11 *C 56.075 80.240 +*N mux_tree_tapbuf_size8_3_sram[0]:12 *C 53.242 80.240 + +*CAP +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_7\/mux_l1_in_0_:S 1e-06 +2 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_3_sram[0]:3 2.992418e-05 +4 mux_tree_tapbuf_size8_3_sram[0]:4 0.0002086271 +5 mux_tree_tapbuf_size8_3_sram[0]:5 0.0001787029 +6 mux_tree_tapbuf_size8_3_sram[0]:6 7.527889e-05 +7 mux_tree_tapbuf_size8_3_sram[0]:7 0.0002363593 +8 mux_tree_tapbuf_size8_3_sram[0]:8 0.0002363593 +9 mux_tree_tapbuf_size8_3_sram[0]:9 7.488234e-05 +10 mux_tree_tapbuf_size8_3_sram[0]:10 0.0001800012 +11 mux_tree_tapbuf_size8_3_sram[0]:11 0.0001796109 +12 mux_tree_tapbuf_size8_3_sram[0]:12 0.0001796109 +13 mux_tree_tapbuf_size8_3_sram[0]:6 chany_bottom_in[6]:19 5.914425e-05 +14 mux_tree_tapbuf_size8_3_sram[0]:10 chany_bottom_in[6]:19 5.949922e-05 +15 mux_tree_tapbuf_size8_3_sram[0]:10 chany_bottom_in[6]:20 5.914425e-05 +16 mux_tree_tapbuf_size8_3_sram[0]:9 chany_bottom_in[6]:20 5.949922e-05 + +*RES +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_3_sram[0]:12 0.152 +1 mux_tree_tapbuf_size8_3_sram[0]:3 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size8_3_sram[0]:5 mux_tree_tapbuf_size8_3_sram[0]:4 0.002107143 +3 mux_tree_tapbuf_size8_3_sram[0]:6 mux_tree_tapbuf_size8_3_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_3_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:9 0.00178125 +6 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:6 0.00178125 +7 mux_tree_tapbuf_size8_3_sram[0]:12 mux_tree_tapbuf_size8_3_sram[0]:11 0.002529018 +8 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[0]:7 0.002712054 +9 mux_tree_tapbuf_size8_3_sram[0]:9 mux_tree_tapbuf_size8_3_sram[0]:8 0.0045 +10 mux_tree_tapbuf_size8_3_sram[0]:7 mux_right_ipin_7\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size8_3_sram[0]:4 mux_tree_tapbuf_size8_3_sram[0]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size8_5_sram[3] 0.001907796 //LENGTH 16.510 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 13.645 53.040 +*I mem_right_ipin_11\/FTB_15__54:A I *L 0.001746 *C 11.040 50.320 +*I mux_right_ipin_11\/mux_l4_in_0_:S I *L 0.00357 *C 8.380 57.800 +*N mux_tree_tapbuf_size8_5_sram[3]:3 *C 8.280 57.800 +*N mux_tree_tapbuf_size8_5_sram[3]:4 *C 8.280 57.755 +*N mux_tree_tapbuf_size8_5_sram[3]:5 *C 8.280 50.365 +*N mux_tree_tapbuf_size8_5_sram[3]:6 *C 8.325 50.320 +*N mux_tree_tapbuf_size8_5_sram[3]:7 *C 11.040 50.320 +*N mux_tree_tapbuf_size8_5_sram[3]:8 *C 13.295 50.320 +*N mux_tree_tapbuf_size8_5_sram[3]:9 *C 13.340 50.365 +*N mux_tree_tapbuf_size8_5_sram[3]:10 *C 13.340 52.995 +*N mux_tree_tapbuf_size8_5_sram[3]:11 *C 13.340 53.040 +*N mux_tree_tapbuf_size8_5_sram[3]:12 *C 13.645 53.040 + +*CAP +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_11\/FTB_15__54:A 1e-06 +2 mux_right_ipin_11\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_5_sram[3]:3 3.391604e-05 +4 mux_tree_tapbuf_size8_5_sram[3]:4 0.000396675 +5 mux_tree_tapbuf_size8_5_sram[3]:5 0.000396675 +6 mux_tree_tapbuf_size8_5_sram[3]:6 0.0001612318 +7 mux_tree_tapbuf_size8_5_sram[3]:7 0.0003237966 +8 mux_tree_tapbuf_size8_5_sram[3]:8 0.0001352405 +9 mux_tree_tapbuf_size8_5_sram[3]:9 0.0001709982 +10 mux_tree_tapbuf_size8_5_sram[3]:10 0.0001709982 +11 mux_tree_tapbuf_size8_5_sram[3]:11 5.7278e-05 +12 mux_tree_tapbuf_size8_5_sram[3]:12 5.798665e-05 + +*RES +0 mem_right_ipin_11\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_5_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_5_sram[3]:8 mux_tree_tapbuf_size8_5_sram[3]:7 0.002013393 +2 mux_tree_tapbuf_size8_5_sram[3]:9 mux_tree_tapbuf_size8_5_sram[3]:8 0.0045 +3 mux_tree_tapbuf_size8_5_sram[3]:11 mux_tree_tapbuf_size8_5_sram[3]:10 0.0045 +4 mux_tree_tapbuf_size8_5_sram[3]:10 mux_tree_tapbuf_size8_5_sram[3]:9 0.002348214 +5 mux_tree_tapbuf_size8_5_sram[3]:12 mux_tree_tapbuf_size8_5_sram[3]:11 0.0001114131 +6 mux_tree_tapbuf_size8_5_sram[3]:6 mux_tree_tapbuf_size8_5_sram[3]:5 0.0045 +7 mux_tree_tapbuf_size8_5_sram[3]:5 mux_tree_tapbuf_size8_5_sram[3]:4 0.006598215 +8 mux_tree_tapbuf_size8_5_sram[3]:3 mux_right_ipin_11\/mux_l4_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_5_sram[3]:4 mux_tree_tapbuf_size8_5_sram[3]:3 0.0045 +10 mux_tree_tapbuf_size8_5_sram[3]:7 mem_right_ipin_11\/FTB_15__54:A 0.152 +11 mux_tree_tapbuf_size8_5_sram[3]:7 mux_tree_tapbuf_size8_5_sram[3]:6 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_0_ccff_tail[0] 0.001073385 //LENGTH 9.255 LUMPCC 0.0001468161 DR + +*CONN +*I mem_right_ipin_2\/FTB_10__49:X O *L 0 *C 3.010 87.720 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 4.775 82.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 *C 4.775 82.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 *C 5.475 82.620 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 *C 5.520 82.665 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 *C 5.520 87.675 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 *C 5.475 87.720 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 *C 3.048 87.720 + +*CAP +0 mem_right_ipin_2\/FTB_10__49:X 1e-06 +1 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 9.961585e-05 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 6.406214e-05 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0002172089 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0002172089 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.0001632364 +7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 0.0001632364 +8 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 prog_clk[0]:182 6.154416e-06 +9 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 prog_clk[0]:184 2.849031e-06 +10 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 prog_clk[0]:188 5.519523e-05 +11 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 prog_clk[0]:189 9.209368e-06 +12 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 prog_clk[0]:183 6.154416e-06 +13 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 prog_clk[0]:188 2.849031e-06 +14 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 prog_clk[0]:189 5.519523e-05 +15 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 prog_clk[0]:408 9.209368e-06 + +*RES +0 mem_right_ipin_2\/FTB_10__49:X mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 0.000625 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.004473215 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.002167411 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0009257664 //LENGTH 8.380 LUMPCC 0 DR + +*CONN +*I mux_left_ipin_0\/mux_l4_in_0_:X O *L 0 *C 80.325 64.260 +*I mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.705 71.880 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 80.705 71.880 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 80.500 71.740 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 80.500 71.695 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 80.500 64.305 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 80.500 64.260 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 80.325 64.260 + +*CAP +0 mux_left_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.34429e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.932999e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003632653 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0003632653 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.081038e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.365253e-05 + +*RES +0 mux_left_ipin_0\/mux_l4_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001114131 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.006598215 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004602481 //LENGTH 2.990 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_1\/mux_l2_in_0_:X O *L 0 *C 50.315 91.800 +*I mux_right_ipin_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 50.140 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 50.140 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 50.140 94.135 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 50.140 91.845 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 50.140 91.800 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 50.315 91.800 + +*CAP +0 mux_right_ipin_1\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_1\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.428857e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001536845 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001536845 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.007784e-05 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.651262e-05 + +*RES +0 mux_right_ipin_1\/mux_l2_in_0_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.510869e-05 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002044643 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_1\/mux_l3_in_0_:A1 0.152 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0009993274 //LENGTH 7.440 LUMPCC 0.0002653771 DR + +*CONN +*I mux_right_ipin_4\/mux_l3_in_1_:X O *L 0 *C 10.755 80.920 +*I mux_right_ipin_4\/mux_l4_in_0_:A0 I *L 0.005103 *C 11.960 86.530 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 11.960 86.530 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 11.960 86.485 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 11.960 80.965 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 11.915 80.920 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 10.793 80.920 + +*CAP +0 mux_right_ipin_4\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_4\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.410098e-05 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002459546 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002459546 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001029701 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001029701 +7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_3_sram[3]:6 0.0001326886 +8 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_3_sram[3]:3 0.0001326886 + +*RES +0 mux_right_ipin_4\/mux_l3_in_1_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.001002232 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0045 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.004928572 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_4\/mux_l4_in_0_:A0 0.152 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006424817 //LENGTH 5.200 LUMPCC 0.0001421949 DR + +*CONN +*I mux_right_ipin_8\/mux_l3_in_0_:X O *L 0 *C 20.875 40.120 +*I mux_right_ipin_8\/mux_l4_in_0_:A1 I *L 0.00198 *C 18.305 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 18.343 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 19.275 41.820 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 19.320 41.775 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 19.320 40.165 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 19.365 40.120 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 20.838 40.120 + +*CAP +0 mux_right_ipin_8\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_8\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.990127e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 3.990127e-05 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.315133e-05 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.315133e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001260908 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001260908 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_5_sram[3]:3 4.966788e-05 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_5_sram[3]:4 4.966788e-05 +10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_5_sram[3]:5 2.142956e-05 +11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_5_sram[3]:7 2.142956e-05 + +*RES +0 mux_right_ipin_8\/mux_l3_in_0_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_8\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0008325894 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0014375 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003724765 //LENGTH 2.115 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_12\/mux_l1_in_0_:X O *L 0 *C 26.855 12.580 +*I mux_right_ipin_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 25.030 12.580 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 25.068 12.580 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 26.818 12.580 + +*CAP +0 mux_right_ipin_12\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_12\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001852383 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001852383 + +*RES +0 mux_right_ipin_12\/mux_l1_in_0_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_12\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0015625 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001243923 //LENGTH 10.585 LUMPCC 0.0002872917 DR + +*CONN +*I mux_right_ipin_13\/mux_l2_in_0_:X O *L 0 *C 47.095 12.580 +*I mux_right_ipin_13\/mux_l3_in_0_:A1 I *L 0.00198 *C 42.880 18.020 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 42.918 18.020 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 46.415 18.020 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 46.460 17.975 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 46.460 12.625 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 46.505 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 47.058 12.580 + +*CAP +0 mux_right_ipin_13\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_13\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001390866 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001390866 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002810318 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002810318 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.719742e-05 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.719742e-05 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_8_sram[2]:8 3.132476e-05 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_8_sram[2]:9 0.0001123211 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_8_sram[2]:9 3.132476e-05 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_8_sram[2]:10 0.0001123211 + +*RES +0 mux_right_ipin_13\/mux_l2_in_0_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_13\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003122768 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007844733 //LENGTH 6.130 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_3\/mux_l2_in_1_:X O *L 0 *C 23.175 64.600 +*I mux_right_ipin_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 19.145 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 19.145 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 19.320 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 19.320 65.915 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 19.320 64.645 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 19.365 64.600 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 23.138 64.600 + +*CAP +0 mux_right_ipin_3\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_3\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.273039e-05 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.669051e-05 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.656525e-05 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.656525e-05 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000249961 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000249961 + +*RES +0 mux_right_ipin_3\/mux_l2_in_1_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003368304 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.51087e-05 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_3\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005446741 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_7\/mux_l2_in_3_:X O *L 0 *C 70.555 88.740 +*I mux_right_ipin_7\/mux_l3_in_1_:A0 I *L 0.001631 *C 70.670 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 70.670 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 70.380 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 70.380 91.415 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 70.380 88.785 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 70.380 88.740 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 70.555 88.740 + +*CAP +0 mux_right_ipin_7\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_7\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.313393e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.260781e-05 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001586263 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001586263 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.166483e-05 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.80149e-05 + +*RES +0 mux_right_ipin_7\/mux_l2_in_3_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_7\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001576087 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002408663 //LENGTH 16.645 LUMPCC 0.0008256224 DR + +*CONN +*I mux_right_ipin_11\/mux_l3_in_1_:X O *L 0 *C 19.955 53.380 +*I mux_right_ipin_11\/mux_l4_in_0_:A0 I *L 0.001631 *C 9.490 58.820 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 9.527 58.820 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 19.735 58.820 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 19.780 58.775 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 19.780 53.425 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 19.780 53.380 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 19.955 53.380 + +*CAP +0 mux_right_ipin_11\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_11\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004722521 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0004722521 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002598802 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002598802 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.873617e-05 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.803944e-05 +8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chany_top_in[0]:44 0.0001945256 +9 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chany_top_in[0]:45 0.0001945256 +10 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[0]:46 1.589827e-05 +11 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[0]:50 8.034992e-06 +12 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[0]:49 8.034992e-06 +13 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[0]:50 1.589827e-05 +14 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_1_sram[0]:4 0.0001245519 +15 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001245519 +16 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_5_sram[0]:5 6.980036e-05 +17 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_5_sram[0]:8 6.980036e-05 + +*RES +0 mux_right_ipin_11\/mux_l3_in_1_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_11\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.009113839 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004776786 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_164 0.0009194992 //LENGTH 7.700 LUMPCC 0.0001649176 DR + +*CONN +*I FTB_7__6:X O *L 0 *C 76.360 105.060 +*I ropt_mt_inst_768:A I *L 0.001766 *C 69.460 104.720 +*N ropt_net_164:2 *C 69.460 104.720 +*N ropt_net_164:3 *C 69.460 105.060 +*N ropt_net_164:4 *C 76.323 105.060 + +*CAP +0 FTB_7__6:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_164:2 6.151993e-05 +3 ropt_net_164:3 0.0003604856 +4 ropt_net_164:4 0.000330576 +5 ropt_net_164:4 chany_bottom_in[6]:5 8.245882e-05 +6 ropt_net_164:3 chany_bottom_in[6]:6 8.245882e-05 + +*RES +0 FTB_7__6:X ropt_net_164:4 0.152 +1 ropt_net_164:4 ropt_net_164:3 0.006127232 +2 ropt_net_164:2 ropt_mt_inst_768:A 0.152 +3 ropt_net_164:3 ropt_net_164:2 0.0003035715 + +*END + +*D_NET chany_bottom_out[14] 0.0007383974 //LENGTH 5.495 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 28.520 3.740 +*P chany_bottom_out[14] O *L 0.7423 *C 26.220 1.290 +*N chany_bottom_out[14]:2 *C 26.220 2.040 +*N chany_bottom_out[14]:3 *C 26.680 2.040 +*N chany_bottom_out[14]:4 *C 26.680 3.695 +*N chany_bottom_out[14]:5 *C 26.725 3.740 +*N chany_bottom_out[14]:6 *C 28.483 3.740 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 chany_bottom_out[14] 5.20101e-05 +2 chany_bottom_out[14]:2 8.191657e-05 +3 chany_bottom_out[14]:3 0.0001565202 +4 chany_bottom_out[14]:4 0.0001266137 +5 chany_bottom_out[14]:5 0.0001601684 +6 chany_bottom_out[14]:6 0.0001601684 + +*RES +0 ropt_mt_inst_743:X chany_bottom_out[14]:6 0.152 +1 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.001569196 +2 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.0045 +3 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.001477679 +4 chany_bottom_out[14]:2 chany_bottom_out[14] 0.0006696429 +5 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.0004107143 + +*END + +*D_NET chany_bottom_out[3] 0.001456241 //LENGTH 10.790 LUMPCC 0.0001124376 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 50.335 6.120 +*P chany_bottom_out[3] O *L 0.7423 *C 45.540 1.290 +*N chany_bottom_out[3]:2 *C 45.540 3.343 +*N chany_bottom_out[3]:3 *C 45.547 3.400 +*N chany_bottom_out[3]:4 *C 46.913 3.400 +*N chany_bottom_out[3]:5 *C 46.920 3.458 +*N chany_bottom_out[3]:6 *C 46.920 6.075 +*N chany_bottom_out[3]:7 *C 46.965 6.120 +*N chany_bottom_out[3]:8 *C 50.297 6.120 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 chany_bottom_out[3] 0.0001437169 +2 chany_bottom_out[3]:2 0.0001437169 +3 chany_bottom_out[3]:3 0.0001065059 +4 chany_bottom_out[3]:4 0.0001065059 +5 chany_bottom_out[3]:5 0.0001566824 +6 chany_bottom_out[3]:6 0.0001566824 +7 chany_bottom_out[3]:7 0.0002644968 +8 chany_bottom_out[3]:8 0.0002644968 +9 chany_bottom_out[3]:6 ropt_net_171:6 5.621882e-05 +10 chany_bottom_out[3]:5 ropt_net_171:5 5.621882e-05 + +*RES +0 ropt_mt_inst_750:X chany_bottom_out[3]:8 0.152 +1 chany_bottom_out[3]:8 chany_bottom_out[3]:7 0.002975447 +2 chany_bottom_out[3]:7 chany_bottom_out[3]:6 0.0045 +3 chany_bottom_out[3]:6 chany_bottom_out[3]:5 0.002337054 +4 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.00341 +5 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.00021385 +6 chany_bottom_out[3]:2 chany_bottom_out[3] 0.001832589 +7 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.00341 + +*END + +*D_NET chany_top_out[11] 0.001661084 //LENGTH 11.775 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 62.295 101.320 +*P chany_top_out[11] O *L 0.7423 *C 57.960 107.510 +*N chany_top_out[11]:2 *C 57.960 102.725 +*N chany_top_out[11]:3 *C 58.005 102.680 +*N chany_top_out[11]:4 *C 59.295 102.680 +*N chany_top_out[11]:5 *C 59.340 102.680 +*N chany_top_out[11]:6 *C 59.348 102.680 +*N chany_top_out[11]:7 *C 62.093 102.680 +*N chany_top_out[11]:8 *C 62.100 102.623 +*N chany_top_out[11]:9 *C 62.100 101.365 +*N chany_top_out[11]:10 *C 62.100 101.320 +*N chany_top_out[11]:11 *C 62.295 101.320 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 chany_top_out[11] 0.000284776 +2 chany_top_out[11]:2 0.000284776 +3 chany_top_out[11]:3 0.000130553 +4 chany_top_out[11]:4 0.000130553 +5 chany_top_out[11]:5 3.901242e-05 +6 chany_top_out[11]:6 0.0002248919 +7 chany_top_out[11]:7 0.0002248919 +8 chany_top_out[11]:8 0.0001042109 +9 chany_top_out[11]:9 0.0001042109 +10 chany_top_out[11]:10 6.927035e-05 +11 chany_top_out[11]:11 6.293755e-05 + +*RES +0 ropt_mt_inst_784:X chany_top_out[11]:11 0.152 +1 chany_top_out[11]:11 chany_top_out[11]:10 0.0001059783 +2 chany_top_out[11]:10 chany_top_out[11]:9 0.0045 +3 chany_top_out[11]:9 chany_top_out[11]:8 0.001122768 +4 chany_top_out[11]:8 chany_top_out[11]:7 0.00341 +5 chany_top_out[11]:7 chany_top_out[11]:6 0.00043005 +6 chany_top_out[11]:5 chany_top_out[11]:4 0.0045 +7 chany_top_out[11]:6 chany_top_out[11]:5 0.00341 +8 chany_top_out[11]:4 chany_top_out[11]:3 0.001151786 +9 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +10 chany_top_out[11]:2 chany_top_out[11] 0.004272322 + +*END + +*D_NET chany_top_out[15] 0.0004201906 //LENGTH 3.460 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 25.760 105.400 +*P chany_top_out[15] O *L 0.7423 *C 24.840 107.475 +*N chany_top_out[15]:2 *C 24.840 105.445 +*N chany_top_out[15]:3 *C 24.885 105.400 +*N chany_top_out[15]:4 *C 25.723 105.400 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 chany_top_out[15] 0.0001310318 +2 chany_top_out[15]:2 0.0001310318 +3 chany_top_out[15]:3 7.856353e-05 +4 chany_top_out[15]:4 7.856353e-05 + +*RES +0 ropt_mt_inst_799:X chany_top_out[15]:4 0.152 +1 chany_top_out[15]:3 chany_top_out[15]:2 0.0045 +2 chany_top_out[15]:2 chany_top_out[15] 0.0018125 +3 chany_top_out[15]:4 chany_top_out[15]:3 0.0007477679 + +*END + +*D_NET chany_bottom_in[9] 0.0198302 //LENGTH 146.565 LUMPCC 0.006420153 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 29.900 1.290 +*I BUFT_P_111:A I *L 0.001766 *C 44.160 93.840 +*I mux_right_ipin_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 22.830 80.920 +*I mux_right_ipin_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 28.885 28.900 +*N chany_bottom_in[9]:4 *C 28.870 28.900 +*N chany_bottom_in[9]:5 *C 22.830 80.920 +*N chany_bottom_in[9]:6 *C 22.600 82.620 +*N chany_bottom_in[9]:7 *C 44.160 93.840 +*N chany_bottom_in[9]:8 *C 44.160 93.840 +*N chany_bottom_in[9]:9 *C 43.700 93.840 +*N chany_bottom_in[9]:10 *C 43.700 96.855 +*N chany_bottom_in[9]:11 *C 43.655 96.900 +*N chany_bottom_in[9]:12 *C 38.225 96.900 +*N chany_bottom_in[9]:13 *C 38.180 96.945 +*N chany_bottom_in[9]:14 *C 38.180 97.863 +*N chany_bottom_in[9]:15 *C 38.172 97.920 +*N chany_bottom_in[9]:16 *C 28.520 97.920 +*N chany_bottom_in[9]:17 *C 28.520 97.240 +*N chany_bottom_in[9]:18 *C 23.020 97.240 +*N chany_bottom_in[9]:19 *C 23.000 97.233 +*N chany_bottom_in[9]:20 *C 23.000 82.627 +*N chany_bottom_in[9]:21 *C 23.000 82.620 +*N chany_bottom_in[9]:22 *C 23.000 82.562 +*N chany_bottom_in[9]:23 *C 23.000 80.965 +*N chany_bottom_in[9]:24 *C 23.045 80.920 +*N chany_bottom_in[9]:25 *C 24.795 80.920 +*N chany_bottom_in[9]:26 *C 24.840 80.875 +*N chany_bottom_in[9]:27 *C 24.840 74.858 +*N chany_bottom_in[9]:28 *C 24.832 74.800 +*N chany_bottom_in[9]:29 *C 23.020 74.800 +*N chany_bottom_in[9]:30 *C 23.000 74.793 +*N chany_bottom_in[9]:31 *C 23.000 30.608 +*N chany_bottom_in[9]:32 *C 23.020 30.600 +*N chany_bottom_in[9]:33 *C 24.373 30.600 +*N chany_bottom_in[9]:34 *C 24.380 30.543 +*N chany_bottom_in[9]:35 *C 24.380 28.945 +*N chany_bottom_in[9]:36 *C 24.425 28.900 +*N chany_bottom_in[9]:37 *C 28.498 28.900 +*N chany_bottom_in[9]:38 *C 28.520 28.560 +*N chany_bottom_in[9]:39 *C 33.075 28.560 +*N chany_bottom_in[9]:40 *C 33.120 28.515 +*N chany_bottom_in[9]:41 *C 33.120 2.778 +*N chany_bottom_in[9]:42 *C 33.113 2.720 +*N chany_bottom_in[9]:43 *C 29.908 2.720 +*N chany_bottom_in[9]:44 *C 29.900 2.663 + +*CAP +0 chany_bottom_in[9] 9.875265e-05 +1 BUFT_P_111:A 1e-06 +2 mux_right_ipin_4\/mux_l2_in_1_:A0 1e-06 +3 mux_right_ipin_8\/mux_l1_in_2_:A1 1e-06 +4 chany_bottom_in[9]:4 5.466782e-05 +5 chany_bottom_in[9]:5 5.664352e-05 +6 chany_bottom_in[9]:6 8.540604e-05 +7 chany_bottom_in[9]:7 3.399222e-05 +8 chany_bottom_in[9]:8 6.629828e-05 +9 chany_bottom_in[9]:9 0.0001932059 +10 chany_bottom_in[9]:10 0.0001591782 +11 chany_bottom_in[9]:11 0.0002896745 +12 chany_bottom_in[9]:12 0.0002896745 +13 chany_bottom_in[9]:13 7.08773e-05 +14 chany_bottom_in[9]:14 7.08773e-05 +15 chany_bottom_in[9]:15 0.0006125088 +16 chany_bottom_in[9]:16 0.000680588 +17 chany_bottom_in[9]:17 0.0005347534 +18 chany_bottom_in[9]:18 0.0004666742 +19 chany_bottom_in[9]:19 0.0006550374 +20 chany_bottom_in[9]:20 0.0006550374 +21 chany_bottom_in[9]:21 8.540604e-05 +22 chany_bottom_in[9]:22 0.000105485 +23 chany_bottom_in[9]:23 0.000105485 +24 chany_bottom_in[9]:24 0.0001844266 +25 chany_bottom_in[9]:25 0.0001573543 +26 chany_bottom_in[9]:26 0.0003896453 +27 chany_bottom_in[9]:27 0.0003896453 +28 chany_bottom_in[9]:28 0.0001562549 +29 chany_bottom_in[9]:29 0.0001562549 +30 chany_bottom_in[9]:30 0.001211208 +31 chany_bottom_in[9]:31 0.001211208 +32 chany_bottom_in[9]:32 0.0001355642 +33 chany_bottom_in[9]:33 0.0001355642 +34 chany_bottom_in[9]:34 8.625245e-05 +35 chany_bottom_in[9]:35 8.625245e-05 +36 chany_bottom_in[9]:36 0.0002668844 +37 chany_bottom_in[9]:37 0.000348909 +38 chany_bottom_in[9]:38 0.0003183119 +39 chany_bottom_in[9]:39 0.0002909552 +40 chany_bottom_in[9]:40 0.0009894798 +41 chany_bottom_in[9]:41 0.0009894798 +42 chany_bottom_in[9]:42 0.0002172088 +43 chany_bottom_in[9]:43 0.0002172088 +44 chany_bottom_in[9]:44 9.875265e-05 +45 chany_bottom_in[9]:22 chany_bottom_in[1]:30 4.124868e-06 +46 chany_bottom_in[9]:23 chany_bottom_in[1]:31 4.124868e-06 +47 chany_bottom_in[9]:40 chany_bottom_in[1]:64 0.0002983291 +48 chany_bottom_in[9]:41 chany_bottom_in[1] 0.0002983291 +49 chany_bottom_in[9]:22 chany_bottom_in[15]:13 6.993553e-07 +50 chany_bottom_in[9]:23 chany_bottom_in[15]:16 6.993553e-07 +51 chany_bottom_in[9]:30 chany_bottom_in[15]:18 0.0004908026 +52 chany_bottom_in[9]:30 chany_bottom_in[15]:25 0.000181751 +53 chany_bottom_in[9]:31 chany_bottom_in[15]:26 0.000181751 +54 chany_bottom_in[9]:31 chany_bottom_in[15]:24 0.0004908026 +55 chany_bottom_in[9]:19 chany_top_in[9]:20 0.0002975492 +56 chany_bottom_in[9]:21 chany_top_in[9]:17 3.412832e-06 +57 chany_bottom_in[9]:20 chany_top_in[9]:19 0.0002975492 +58 chany_bottom_in[9]:30 chany_top_in[9]:19 0.0008563203 +59 chany_bottom_in[9]:31 chany_top_in[9]:13 0.0008563203 +60 chany_bottom_in[9]:39 chany_top_in[9]:8 1.31368e-05 +61 chany_bottom_in[9]:38 chany_top_in[9]:7 1.31368e-05 +62 chany_bottom_in[9]:6 chany_top_in[9]:18 3.412832e-06 +63 chany_bottom_in[9]:40 chany_top_in[12]:9 0.0003935181 +64 chany_bottom_in[9]:41 chany_top_in[12]:8 0.0003935181 +65 chany_bottom_in[9]:11 mux_tree_tapbuf_size10_2_sram[2]:8 2.196595e-05 +66 chany_bottom_in[9]:11 mux_tree_tapbuf_size10_2_sram[2]:17 0.0001602353 +67 chany_bottom_in[9]:11 mux_tree_tapbuf_size10_2_sram[2]:20 7.854548e-06 +68 chany_bottom_in[9]:10 mux_tree_tapbuf_size10_2_sram[2]:7 5.507719e-05 +69 chany_bottom_in[9]:12 mux_tree_tapbuf_size10_2_sram[2]:21 7.854548e-06 +70 chany_bottom_in[9]:12 mux_tree_tapbuf_size10_2_sram[2]:20 2.196595e-05 +71 chany_bottom_in[9]:12 mux_tree_tapbuf_size10_2_sram[2]:16 0.0001602353 +72 chany_bottom_in[9]:13 mux_tree_tapbuf_size10_2_sram[2]:14 1.62639e-05 +73 chany_bottom_in[9]:14 mux_tree_tapbuf_size10_2_sram[2]:15 1.62639e-05 +74 chany_bottom_in[9]:9 mux_tree_tapbuf_size10_2_sram[2]:6 5.507719e-05 +75 chany_bottom_in[9]:34 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.450242e-05 +76 chany_bottom_in[9]:36 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.478805e-05 +77 chany_bottom_in[9]:35 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.450242e-05 +78 chany_bottom_in[9]:37 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.478805e-05 +79 chany_bottom_in[9]:15 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001875106 +80 chany_bottom_in[9]:18 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.140982e-05 +81 chany_bottom_in[9]:17 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.140982e-05 +82 chany_bottom_in[9]:16 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001875106 +83 chany_bottom_in[9]:13 ropt_net_168:5 2.096343e-06 +84 chany_bottom_in[9]:14 ropt_net_168:4 2.096343e-06 +85 chany_bottom_in[9]:15 ropt_net_168:7 6.570626e-05 +86 chany_bottom_in[9]:16 ropt_net_168:6 6.570626e-05 +87 chany_bottom_in[9]:40 ropt_net_157:7 2.343822e-05 +88 chany_bottom_in[9]:40 ropt_net_157:5 3.958297e-05 +89 chany_bottom_in[9]:41 ropt_net_157:4 3.958297e-05 +90 chany_bottom_in[9]:41 ropt_net_157:6 2.343822e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:44 0.001225446 +1 chany_bottom_in[9]:7 BUFT_P_111:A 0.152 +2 chany_bottom_in[9]:8 chany_bottom_in[9]:7 0.0045 +3 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.0045 +4 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.002691964 +5 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.004848215 +6 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.0045 +7 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.0008191965 +8 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.00341 +9 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.0008616666 +10 chany_bottom_in[9]:19 chany_bottom_in[9]:18 0.00341 +11 chany_bottom_in[9]:21 chany_bottom_in[9]:20 0.00341 +12 chany_bottom_in[9]:21 chany_bottom_in[9]:6 5.69697e-05 +13 chany_bottom_in[9]:20 chany_bottom_in[9]:19 0.002288117 +14 chany_bottom_in[9]:22 chany_bottom_in[9]:21 0.00341 +15 chany_bottom_in[9]:24 chany_bottom_in[9]:23 0.0045 +16 chany_bottom_in[9]:24 chany_bottom_in[9]:5 0.0001168478 +17 chany_bottom_in[9]:23 chany_bottom_in[9]:22 0.001426339 +18 chany_bottom_in[9]:25 chany_bottom_in[9]:24 0.0015625 +19 chany_bottom_in[9]:26 chany_bottom_in[9]:25 0.0045 +20 chany_bottom_in[9]:27 chany_bottom_in[9]:26 0.005372768 +21 chany_bottom_in[9]:28 chany_bottom_in[9]:27 0.00341 +22 chany_bottom_in[9]:29 chany_bottom_in[9]:28 0.0002839583 +23 chany_bottom_in[9]:30 chany_bottom_in[9]:29 0.00341 +24 chany_bottom_in[9]:32 chany_bottom_in[9]:31 0.00341 +25 chany_bottom_in[9]:31 chany_bottom_in[9]:30 0.006922316 +26 chany_bottom_in[9]:34 chany_bottom_in[9]:33 0.00341 +27 chany_bottom_in[9]:33 chany_bottom_in[9]:32 0.0002118916 +28 chany_bottom_in[9]:36 chany_bottom_in[9]:35 0.0045 +29 chany_bottom_in[9]:35 chany_bottom_in[9]:34 0.001426339 +30 chany_bottom_in[9]:5 mux_right_ipin_4\/mux_l2_in_1_:A0 0.152 +31 chany_bottom_in[9]:4 mux_right_ipin_8\/mux_l1_in_2_:A1 0.152 +32 chany_bottom_in[9]:39 chany_bottom_in[9]:38 0.004066965 +33 chany_bottom_in[9]:40 chany_bottom_in[9]:39 0.0045 +34 chany_bottom_in[9]:41 chany_bottom_in[9]:40 0.02297991 +35 chany_bottom_in[9]:42 chany_bottom_in[9]:41 0.00341 +36 chany_bottom_in[9]:44 chany_bottom_in[9]:43 0.00341 +37 chany_bottom_in[9]:43 chany_bottom_in[9]:42 0.0005021166 +38 chany_bottom_in[9]:37 chany_bottom_in[9]:36 0.003636161 +39 chany_bottom_in[9]:37 chany_bottom_in[9]:4 0.0002024457 +40 chany_bottom_in[9]:38 chany_bottom_in[9]:37 0.0003035715 +41 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.0004107143 +42 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.0001065333 +43 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.001512225 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[3] 0.002546215 //LENGTH 20.070 LUMPCC 0.0001421949 DR + +*CONN +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 23.765 28.560 +*I mem_right_ipin_8\/FTB_6__45:A I *L 0.001746 *C 20.240 34.000 +*I mux_right_ipin_8\/mux_l4_in_0_:S I *L 0.00357 *C 17.580 41.480 +*N mux_tree_tapbuf_size10_5_sram[3]:3 *C 17.617 41.480 +*N mux_tree_tapbuf_size10_5_sram[3]:4 *C 20.195 41.480 +*N mux_tree_tapbuf_size10_5_sram[3]:5 *C 20.240 41.435 +*N mux_tree_tapbuf_size10_5_sram[3]:6 *C 20.240 34.000 +*N mux_tree_tapbuf_size10_5_sram[3]:7 *C 20.240 34.000 +*N mux_tree_tapbuf_size10_5_sram[3]:8 *C 20.240 28.617 +*N mux_tree_tapbuf_size10_5_sram[3]:9 *C 20.248 28.560 +*N mux_tree_tapbuf_size10_5_sram[3]:10 *C 23.453 28.560 +*N mux_tree_tapbuf_size10_5_sram[3]:11 *C 23.460 28.560 +*N mux_tree_tapbuf_size10_5_sram[3]:12 *C 23.460 28.560 +*N mux_tree_tapbuf_size10_5_sram[3]:13 *C 23.765 28.560 + +*CAP +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_8\/FTB_6__45:A 1e-06 +2 mux_right_ipin_8\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_5_sram[3]:3 0.000167401 +4 mux_tree_tapbuf_size10_5_sram[3]:4 0.000167401 +5 mux_tree_tapbuf_size10_5_sram[3]:5 0.000370535 +6 mux_tree_tapbuf_size10_5_sram[3]:6 3.719251e-05 +7 mux_tree_tapbuf_size10_5_sram[3]:7 0.0007032079 +8 mux_tree_tapbuf_size10_5_sram[3]:8 0.0003014312 +9 mux_tree_tapbuf_size10_5_sram[3]:9 0.0002473941 +10 mux_tree_tapbuf_size10_5_sram[3]:10 0.0002473941 +11 mux_tree_tapbuf_size10_5_sram[3]:11 3.632576e-05 +12 mux_tree_tapbuf_size10_5_sram[3]:12 6.238406e-05 +13 mux_tree_tapbuf_size10_5_sram[3]:13 6.035322e-05 +14 mux_tree_tapbuf_size10_5_sram[3]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.966788e-05 +15 mux_tree_tapbuf_size10_5_sram[3]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.142956e-05 +16 mux_tree_tapbuf_size10_5_sram[3]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.966788e-05 +17 mux_tree_tapbuf_size10_5_sram[3]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.142956e-05 + +*RES +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_5_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_5_sram[3]:4 mux_tree_tapbuf_size10_5_sram[3]:3 0.00230134 +2 mux_tree_tapbuf_size10_5_sram[3]:5 mux_tree_tapbuf_size10_5_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size10_5_sram[3]:3 mux_right_ipin_8\/mux_l4_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_5_sram[3]:6 mem_right_ipin_8\/FTB_6__45:A 0.152 +5 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:6 0.0045 +6 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:5 0.006638393 +7 mux_tree_tapbuf_size10_5_sram[3]:8 mux_tree_tapbuf_size10_5_sram[3]:7 0.004805803 +8 mux_tree_tapbuf_size10_5_sram[3]:9 mux_tree_tapbuf_size10_5_sram[3]:8 0.00341 +9 mux_tree_tapbuf_size10_5_sram[3]:11 mux_tree_tapbuf_size10_5_sram[3]:10 0.00341 +10 mux_tree_tapbuf_size10_5_sram[3]:10 mux_tree_tapbuf_size10_5_sram[3]:9 0.0005021166 +11 mux_tree_tapbuf_size10_5_sram[3]:12 mux_tree_tapbuf_size10_5_sram[3]:11 0.0045 +12 mux_tree_tapbuf_size10_5_sram[3]:13 mux_tree_tapbuf_size10_5_sram[3]:12 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[1] 0.005182358 //LENGTH 37.065 LUMPCC 0.0008102502 DR + +*CONN +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 16.405 17.165 +*I mux_right_ipin_12\/mux_l2_in_3_:S I *L 0.00357 *C 24.480 17.975 +*I mux_right_ipin_12\/mux_l2_in_2_:S I *L 0.00357 *C 28.620 17.680 +*I mux_right_ipin_12\/mux_l2_in_0_:S I *L 0.00357 *C 23.560 12.580 +*I mux_right_ipin_12\/mux_l2_in_1_:S I *L 0.00357 *C 18.300 8.840 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 12.595 15.300 +*N mux_tree_tapbuf_size10_7_sram[1]:6 *C 12.595 15.300 +*N mux_tree_tapbuf_size10_7_sram[1]:7 *C 12.420 15.300 +*N mux_tree_tapbuf_size10_7_sram[1]:8 *C 12.420 15.345 +*N mux_tree_tapbuf_size10_7_sram[1]:9 *C 12.420 17.295 +*N mux_tree_tapbuf_size10_7_sram[1]:10 *C 12.465 17.340 +*N mux_tree_tapbuf_size10_7_sram[1]:11 *C 18.338 8.840 +*N mux_tree_tapbuf_size10_7_sram[1]:12 *C 23.875 8.840 +*N mux_tree_tapbuf_size10_7_sram[1]:13 *C 23.920 8.885 +*N mux_tree_tapbuf_size10_7_sram[1]:14 *C 23.575 12.580 +*N mux_tree_tapbuf_size10_7_sram[1]:15 *C 23.898 12.580 +*N mux_tree_tapbuf_size10_7_sram[1]:16 *C 23.920 12.580 +*N mux_tree_tapbuf_size10_7_sram[1]:17 *C 23.920 17.295 +*N mux_tree_tapbuf_size10_7_sram[1]:18 *C 23.920 17.340 +*N mux_tree_tapbuf_size10_7_sram[1]:19 *C 28.583 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:20 *C 24.855 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:21 *C 24.480 17.975 +*N mux_tree_tapbuf_size10_7_sram[1]:22 *C 24.370 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:23 *C 24.393 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:24 *C 23.920 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:25 *C 16.450 17.680 +*N mux_tree_tapbuf_size10_7_sram[1]:26 *C 16.405 17.635 +*N mux_tree_tapbuf_size10_7_sram[1]:27 *C 16.405 17.210 +*N mux_tree_tapbuf_size10_7_sram[1]:28 *C 16.367 17.275 + +*CAP +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_12\/mux_l2_in_3_:S 1e-06 +2 mux_right_ipin_12\/mux_l2_in_2_:S 1e-06 +3 mux_right_ipin_12\/mux_l2_in_0_:S 1e-06 +4 mux_right_ipin_12\/mux_l2_in_1_:S 1e-06 +5 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_7_sram[1]:6 4.85857e-05 +7 mux_tree_tapbuf_size10_7_sram[1]:7 5.376021e-05 +8 mux_tree_tapbuf_size10_7_sram[1]:8 0.0001285369 +9 mux_tree_tapbuf_size10_7_sram[1]:9 0.0001285369 +10 mux_tree_tapbuf_size10_7_sram[1]:10 0.000313811 +11 mux_tree_tapbuf_size10_7_sram[1]:11 0.0002966409 +12 mux_tree_tapbuf_size10_7_sram[1]:12 0.0002966409 +13 mux_tree_tapbuf_size10_7_sram[1]:13 0.0001251358 +14 mux_tree_tapbuf_size10_7_sram[1]:14 6.982899e-05 +15 mux_tree_tapbuf_size10_7_sram[1]:15 6.982899e-05 +16 mux_tree_tapbuf_size10_7_sram[1]:16 0.0003620114 +17 mux_tree_tapbuf_size10_7_sram[1]:17 0.0002049955 +18 mux_tree_tapbuf_size10_7_sram[1]:18 5.878783e-05 +19 mux_tree_tapbuf_size10_7_sram[1]:19 0.0002856124 +20 mux_tree_tapbuf_size10_7_sram[1]:20 0.0003295455 +21 mux_tree_tapbuf_size10_7_sram[1]:21 6.747089e-05 +22 mux_tree_tapbuf_size10_7_sram[1]:22 4.945516e-05 +23 mux_tree_tapbuf_size10_7_sram[1]:23 9.203055e-05 +24 mux_tree_tapbuf_size10_7_sram[1]:24 0.0005178904 +25 mux_tree_tapbuf_size10_7_sram[1]:25 0.0004604133 +26 mux_tree_tapbuf_size10_7_sram[1]:26 4.638875e-05 +27 mux_tree_tapbuf_size10_7_sram[1]:27 4.638875e-05 +28 mux_tree_tapbuf_size10_7_sram[1]:28 0.000313811 +29 mux_tree_tapbuf_size10_7_sram[1]:11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.688622e-05 +30 mux_tree_tapbuf_size10_7_sram[1]:12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.688622e-05 +31 mux_tree_tapbuf_size10_7_sram[1]:16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.045361e-05 +32 mux_tree_tapbuf_size10_7_sram[1]:16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.013856e-05 +33 mux_tree_tapbuf_size10_7_sram[1]:17 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.013856e-05 +34 mux_tree_tapbuf_size10_7_sram[1]:11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.777025e-05 +35 mux_tree_tapbuf_size10_7_sram[1]:12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.777025e-05 +36 mux_tree_tapbuf_size10_7_sram[1]:13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.045361e-05 +37 mux_tree_tapbuf_size10_7_sram[1]:16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.58435e-06 +38 mux_tree_tapbuf_size10_7_sram[1]:17 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.58435e-06 +39 mux_tree_tapbuf_size10_7_sram[1]:25 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.560232e-05 +40 mux_tree_tapbuf_size10_7_sram[1]:19 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.830589e-05 +41 mux_tree_tapbuf_size10_7_sram[1]:24 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.740899e-06 +42 mux_tree_tapbuf_size10_7_sram[1]:24 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.560232e-05 +43 mux_tree_tapbuf_size10_7_sram[1]:22 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.332823e-06 +44 mux_tree_tapbuf_size10_7_sram[1]:23 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.951667e-06 +45 mux_tree_tapbuf_size10_7_sram[1]:23 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 4.740899e-06 +46 mux_tree_tapbuf_size10_7_sram[1]:20 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.830589e-05 +47 mux_tree_tapbuf_size10_7_sram[1]:20 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.618843e-06 +48 mux_tree_tapbuf_size10_7_sram[1]:11 ropt_net_187:8 6.149346e-05 +49 mux_tree_tapbuf_size10_7_sram[1]:12 ropt_net_187:7 6.149346e-05 +50 mux_tree_tapbuf_size10_7_sram[1]:16 ropt_net_149:5 0.0001013168 +51 mux_tree_tapbuf_size10_7_sram[1]:16 ropt_net_149:4 5.588108e-05 +52 mux_tree_tapbuf_size10_7_sram[1]:17 ropt_net_149:5 5.588108e-05 +53 mux_tree_tapbuf_size10_7_sram[1]:13 ropt_net_149:4 0.0001013168 + +*RES +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_7_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_7_sram[1]:15 mux_tree_tapbuf_size10_7_sram[1]:14 0.0001752717 +2 mux_tree_tapbuf_size10_7_sram[1]:16 mux_tree_tapbuf_size10_7_sram[1]:15 0.0045 +3 mux_tree_tapbuf_size10_7_sram[1]:16 mux_tree_tapbuf_size10_7_sram[1]:13 0.003299107 +4 mux_tree_tapbuf_size10_7_sram[1]:14 mux_right_ipin_12\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_7_sram[1]:18 mux_tree_tapbuf_size10_7_sram[1]:17 0.0045 +6 mux_tree_tapbuf_size10_7_sram[1]:17 mux_tree_tapbuf_size10_7_sram[1]:16 0.004209822 +7 mux_tree_tapbuf_size10_7_sram[1]:11 mux_right_ipin_12\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_7_sram[1]:12 mux_tree_tapbuf_size10_7_sram[1]:11 0.004944196 +9 mux_tree_tapbuf_size10_7_sram[1]:13 mux_tree_tapbuf_size10_7_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size10_7_sram[1]:28 mux_tree_tapbuf_size10_7_sram[1]:27 0.0045 +11 mux_tree_tapbuf_size10_7_sram[1]:28 mux_tree_tapbuf_size10_7_sram[1]:10 0.003484376 +12 mux_tree_tapbuf_size10_7_sram[1]:27 mux_tree_tapbuf_size10_7_sram[1]:26 0.0003794643 +13 mux_tree_tapbuf_size10_7_sram[1]:25 mux_tree_tapbuf_size10_7_sram[1]:24 0.006669643 +14 mux_tree_tapbuf_size10_7_sram[1]:26 mux_tree_tapbuf_size10_7_sram[1]:25 0.0045 +15 mux_tree_tapbuf_size10_7_sram[1]:21 mux_right_ipin_12\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size10_7_sram[1]:19 mux_right_ipin_12\/mux_l2_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_7_sram[1]:10 mux_tree_tapbuf_size10_7_sram[1]:9 0.0045 +18 mux_tree_tapbuf_size10_7_sram[1]:9 mux_tree_tapbuf_size10_7_sram[1]:8 0.001741072 +19 mux_tree_tapbuf_size10_7_sram[1]:7 mux_tree_tapbuf_size10_7_sram[1]:6 9.510871e-05 +20 mux_tree_tapbuf_size10_7_sram[1]:8 mux_tree_tapbuf_size10_7_sram[1]:7 0.0045 +21 mux_tree_tapbuf_size10_7_sram[1]:6 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +22 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:23 0.000421875 +23 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:18 0.0003035715 +24 mux_tree_tapbuf_size10_7_sram[1]:22 mux_tree_tapbuf_size10_7_sram[1]:21 0.0001271552 +25 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:22 2.008929e-05 +26 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:20 0.0002890625 +27 mux_tree_tapbuf_size10_7_sram[1]:20 mux_tree_tapbuf_size10_7_sram[1]:19 0.003328125 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[2] 0.00605373 //LENGTH 40.510 LUMPCC 0.0003649933 DR + +*CONN +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 45.385 60.860 +*I mux_right_ipin_6\/mux_l3_in_1_:S I *L 0.00357 *C 30.920 57.800 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 38.815 69.700 +*I mux_right_ipin_6\/mux_l3_in_0_:S I *L 0.00357 *C 29.340 67.320 +*N mux_tree_tapbuf_size8_2_sram[2]:4 *C 29.378 67.320 +*N mux_tree_tapbuf_size8_2_sram[2]:5 *C 38.815 69.700 +*N mux_tree_tapbuf_size8_2_sram[2]:6 *C 39.100 69.700 +*N mux_tree_tapbuf_size8_2_sram[2]:7 *C 39.100 69.655 +*N mux_tree_tapbuf_size8_2_sram[2]:8 *C 39.100 67.365 +*N mux_tree_tapbuf_size8_2_sram[2]:9 *C 39.100 67.320 +*N mux_tree_tapbuf_size8_2_sram[2]:10 *C 40.895 67.320 +*N mux_tree_tapbuf_size8_2_sram[2]:11 *C 40.940 67.275 +*N mux_tree_tapbuf_size8_2_sram[2]:12 *C 30.958 57.800 +*N mux_tree_tapbuf_size8_2_sram[2]:13 *C 33.995 57.800 +*N mux_tree_tapbuf_size8_2_sram[2]:14 *C 34.040 57.845 +*N mux_tree_tapbuf_size8_2_sram[2]:15 *C 34.040 58.422 +*N mux_tree_tapbuf_size8_2_sram[2]:16 *C 34.047 58.480 +*N mux_tree_tapbuf_size8_2_sram[2]:17 *C 40.933 58.480 +*N mux_tree_tapbuf_size8_2_sram[2]:18 *C 40.940 58.538 +*N mux_tree_tapbuf_size8_2_sram[2]:19 *C 40.940 60.860 +*N mux_tree_tapbuf_size8_2_sram[2]:20 *C 40.985 60.860 +*N mux_tree_tapbuf_size8_2_sram[2]:21 *C 45.348 60.860 + +*CAP +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_6\/mux_l3_in_1_:S 1e-06 +2 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_6\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_2_sram[2]:4 0.0006165435 +5 mux_tree_tapbuf_size8_2_sram[2]:5 5.941077e-05 +6 mux_tree_tapbuf_size8_2_sram[2]:6 5.913505e-05 +7 mux_tree_tapbuf_size8_2_sram[2]:7 0.0002011833 +8 mux_tree_tapbuf_size8_2_sram[2]:8 0.0002011833 +9 mux_tree_tapbuf_size8_2_sram[2]:9 0.0007785293 +10 mux_tree_tapbuf_size8_2_sram[2]:10 0.000127766 +11 mux_tree_tapbuf_size8_2_sram[2]:11 0.0003712286 +12 mux_tree_tapbuf_size8_2_sram[2]:12 0.0001785609 +13 mux_tree_tapbuf_size8_2_sram[2]:13 0.0001785609 +14 mux_tree_tapbuf_size8_2_sram[2]:14 7.413659e-05 +15 mux_tree_tapbuf_size8_2_sram[2]:15 7.413659e-05 +16 mux_tree_tapbuf_size8_2_sram[2]:16 0.0007428381 +17 mux_tree_tapbuf_size8_2_sram[2]:17 0.0007428381 +18 mux_tree_tapbuf_size8_2_sram[2]:18 0.0001474595 +19 mux_tree_tapbuf_size8_2_sram[2]:19 0.0005541038 +20 mux_tree_tapbuf_size8_2_sram[2]:20 0.0002885609 +21 mux_tree_tapbuf_size8_2_sram[2]:21 0.0002885609 +22 mux_tree_tapbuf_size8_2_sram[2]:9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.620002e-05 +23 mux_tree_tapbuf_size8_2_sram[2]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.620002e-05 +24 mux_tree_tapbuf_size8_2_sram[2]:12 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.629662e-05 +25 mux_tree_tapbuf_size8_2_sram[2]:13 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.629662e-05 + +*RES +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_2_sram[2]:21 0.152 +1 mux_tree_tapbuf_size8_2_sram[2]:12 mux_right_ipin_6\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_2_sram[2]:13 mux_tree_tapbuf_size8_2_sram[2]:12 0.002712054 +3 mux_tree_tapbuf_size8_2_sram[2]:14 mux_tree_tapbuf_size8_2_sram[2]:13 0.0045 +4 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:14 0.000515625 +5 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:15 0.00341 +6 mux_tree_tapbuf_size8_2_sram[2]:18 mux_tree_tapbuf_size8_2_sram[2]:17 0.00341 +7 mux_tree_tapbuf_size8_2_sram[2]:17 mux_tree_tapbuf_size8_2_sram[2]:16 0.00107865 +8 mux_tree_tapbuf_size8_2_sram[2]:20 mux_tree_tapbuf_size8_2_sram[2]:19 0.0045 +9 mux_tree_tapbuf_size8_2_sram[2]:19 mux_tree_tapbuf_size8_2_sram[2]:18 0.002073661 +10 mux_tree_tapbuf_size8_2_sram[2]:19 mux_tree_tapbuf_size8_2_sram[2]:11 0.005727679 +11 mux_tree_tapbuf_size8_2_sram[2]:21 mux_tree_tapbuf_size8_2_sram[2]:20 0.003895089 +12 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:9 0.001602679 +13 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:10 0.0045 +14 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:8 0.0045 +15 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:4 0.008680805 +16 mux_tree_tapbuf_size8_2_sram[2]:8 mux_tree_tapbuf_size8_2_sram[2]:7 0.002044643 +17 mux_tree_tapbuf_size8_2_sram[2]:6 mux_tree_tapbuf_size8_2_sram[2]:5 0.0001548913 +18 mux_tree_tapbuf_size8_2_sram[2]:7 mux_tree_tapbuf_size8_2_sram[2]:6 0.0045 +19 mux_tree_tapbuf_size8_2_sram[2]:5 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +20 mux_tree_tapbuf_size8_2_sram[2]:4 mux_right_ipin_6\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[1] 0.004594169 //LENGTH 34.205 LUMPCC 0.0001172376 DR + +*CONN +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 45.385 39.440 +*I mux_right_ipin_14\/mux_l2_in_0_:S I *L 0.00357 *C 38.080 41.480 +*I mux_right_ipin_14\/mux_l2_in_2_:S I *L 0.00357 *C 41.960 41.870 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 43.415 47.940 +*I mux_right_ipin_14\/mux_l2_in_3_:S I *L 0.00357 *C 32.560 50.660 +*I mux_right_ipin_14\/mux_l2_in_1_:S I *L 0.00357 *C 33.940 47.310 +*N mux_tree_tapbuf_size8_6_sram[1]:6 *C 33.940 47.310 +*N mux_tree_tapbuf_size8_6_sram[1]:7 *C 32.560 50.660 +*N mux_tree_tapbuf_size8_6_sram[1]:8 *C 32.660 50.615 +*N mux_tree_tapbuf_size8_6_sram[1]:9 *C 32.660 47.645 +*N mux_tree_tapbuf_size8_6_sram[1]:10 *C 32.705 47.600 +*N mux_tree_tapbuf_size8_6_sram[1]:11 *C 33.940 47.600 +*N mux_tree_tapbuf_size8_6_sram[1]:12 *C 41.400 47.600 +*N mux_tree_tapbuf_size8_6_sram[1]:13 *C 41.400 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:14 *C 43.415 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:15 *C 45.035 47.940 +*N mux_tree_tapbuf_size8_6_sram[1]:16 *C 45.080 47.895 +*N mux_tree_tapbuf_size8_6_sram[1]:17 *C 41.960 41.870 +*N mux_tree_tapbuf_size8_6_sram[1]:18 *C 38.117 41.480 +*N mux_tree_tapbuf_size8_6_sram[1]:19 *C 41.960 41.480 +*N mux_tree_tapbuf_size8_6_sram[1]:20 *C 45.035 41.480 +*N mux_tree_tapbuf_size8_6_sram[1]:21 *C 45.080 41.480 +*N mux_tree_tapbuf_size8_6_sram[1]:22 *C 45.080 39.485 +*N mux_tree_tapbuf_size8_6_sram[1]:23 *C 45.080 39.440 +*N mux_tree_tapbuf_size8_6_sram[1]:24 *C 45.385 39.440 + +*CAP +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_14\/mux_l2_in_0_:S 1e-06 +2 mux_right_ipin_14\/mux_l2_in_2_:S 1e-06 +3 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_right_ipin_14\/mux_l2_in_3_:S 1e-06 +5 mux_right_ipin_14\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size8_6_sram[1]:6 6.44809e-05 +7 mux_tree_tapbuf_size8_6_sram[1]:7 2.985504e-05 +8 mux_tree_tapbuf_size8_6_sram[1]:8 0.0002195494 +9 mux_tree_tapbuf_size8_6_sram[1]:9 0.0002195494 +10 mux_tree_tapbuf_size8_6_sram[1]:10 0.0001080337 +11 mux_tree_tapbuf_size8_6_sram[1]:11 0.000591412 +12 mux_tree_tapbuf_size8_6_sram[1]:12 0.000479408 +13 mux_tree_tapbuf_size8_6_sram[1]:13 0.0001702515 +14 mux_tree_tapbuf_size8_6_sram[1]:14 0.0002983438 +15 mux_tree_tapbuf_size8_6_sram[1]:15 0.0001195574 +16 mux_tree_tapbuf_size8_6_sram[1]:16 0.000360501 +17 mux_tree_tapbuf_size8_6_sram[1]:17 5.713279e-05 +18 mux_tree_tapbuf_size8_6_sram[1]:18 0.0002844719 +19 mux_tree_tapbuf_size8_6_sram[1]:19 0.0005376304 +20 mux_tree_tapbuf_size8_6_sram[1]:20 0.000223661 +21 mux_tree_tapbuf_size8_6_sram[1]:21 0.0005007194 +22 mux_tree_tapbuf_size8_6_sram[1]:22 0.0001108001 +23 mux_tree_tapbuf_size8_6_sram[1]:23 4.996245e-05 +24 mux_tree_tapbuf_size8_6_sram[1]:24 4.561117e-05 +25 mux_tree_tapbuf_size8_6_sram[1]:11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.861882e-05 +26 mux_tree_tapbuf_size8_6_sram[1]:12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.861882e-05 + +*RES +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_6_sram[1]:24 0.152 +1 mux_tree_tapbuf_size8_6_sram[1]:15 mux_tree_tapbuf_size8_6_sram[1]:14 0.001446428 +2 mux_tree_tapbuf_size8_6_sram[1]:16 mux_tree_tapbuf_size8_6_sram[1]:15 0.0045 +3 mux_tree_tapbuf_size8_6_sram[1]:20 mux_tree_tapbuf_size8_6_sram[1]:19 0.002745535 +4 mux_tree_tapbuf_size8_6_sram[1]:21 mux_tree_tapbuf_size8_6_sram[1]:20 0.0045 +5 mux_tree_tapbuf_size8_6_sram[1]:21 mux_tree_tapbuf_size8_6_sram[1]:16 0.005727679 +6 mux_tree_tapbuf_size8_6_sram[1]:10 mux_tree_tapbuf_size8_6_sram[1]:9 0.0045 +7 mux_tree_tapbuf_size8_6_sram[1]:9 mux_tree_tapbuf_size8_6_sram[1]:8 0.002651786 +8 mux_tree_tapbuf_size8_6_sram[1]:7 mux_right_ipin_14\/mux_l2_in_3_:S 0.152 +9 mux_tree_tapbuf_size8_6_sram[1]:8 mux_tree_tapbuf_size8_6_sram[1]:7 0.0045 +10 mux_tree_tapbuf_size8_6_sram[1]:14 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size8_6_sram[1]:14 mux_tree_tapbuf_size8_6_sram[1]:13 0.001799107 +12 mux_tree_tapbuf_size8_6_sram[1]:23 mux_tree_tapbuf_size8_6_sram[1]:22 0.0045 +13 mux_tree_tapbuf_size8_6_sram[1]:22 mux_tree_tapbuf_size8_6_sram[1]:21 0.00178125 +14 mux_tree_tapbuf_size8_6_sram[1]:24 mux_tree_tapbuf_size8_6_sram[1]:23 0.0001657609 +15 mux_tree_tapbuf_size8_6_sram[1]:17 mux_right_ipin_14\/mux_l2_in_2_:S 0.152 +16 mux_tree_tapbuf_size8_6_sram[1]:6 mux_right_ipin_14\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size8_6_sram[1]:18 mux_right_ipin_14\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size8_6_sram[1]:11 mux_tree_tapbuf_size8_6_sram[1]:10 0.001102679 +19 mux_tree_tapbuf_size8_6_sram[1]:11 mux_tree_tapbuf_size8_6_sram[1]:6 0.000125 +20 mux_tree_tapbuf_size8_6_sram[1]:12 mux_tree_tapbuf_size8_6_sram[1]:11 0.006660715 +21 mux_tree_tapbuf_size8_6_sram[1]:19 mux_tree_tapbuf_size8_6_sram[1]:18 0.003430804 +22 mux_tree_tapbuf_size8_6_sram[1]:19 mux_tree_tapbuf_size8_6_sram[1]:17 0.0003482143 +23 mux_tree_tapbuf_size8_6_sram[1]:13 mux_tree_tapbuf_size8_6_sram[1]:12 0.0003035715 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002318927 //LENGTH 21.515 LUMPCC 0.0006340971 DR + +*CONN +*I mux_left_ipin_0\/mux_l3_in_0_:X O *L 0 *C 79.865 45.560 +*I mux_left_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 78.760 63.580 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 78.723 63.580 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 78.245 63.580 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 78.200 63.535 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 78.200 47.645 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 78.245 47.600 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 79.535 47.600 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 79.580 47.555 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 79.580 45.605 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 79.580 45.560 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 79.865 45.560 + +*CAP +0 mux_left_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.877189e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.877189e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0005570037 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0005570037 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.340547e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.340547e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 7.983935e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 7.983935e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 5.251579e-05 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 5.227335e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_top_in[4]:25 8.885709e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_top_in[4]:22 8.885709e-05 +14 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:10 7.699718e-05 +15 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:13 8.883255e-05 +16 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:12 8.883255e-05 +17 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:13 7.699718e-05 +18 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size10_0_sram[2]:13 6.236177e-05 +19 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_tree_tapbuf_size10_0_sram[2]:12 6.236177e-05 + +*RES +0 mux_left_ipin_0\/mux_l3_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_ipin_0\/mux_l4_in_0_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004263392 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0141875 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001151786 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0045 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0045 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.001741072 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001548913 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0004069689 //LENGTH 2.490 LUMPCC 0.0001863387 DR + +*CONN +*I mux_right_ipin_1\/mux_l3_in_1_:X O *L 0 *C 35.595 93.160 +*I mux_right_ipin_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 33.395 93.160 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 33.433 93.160 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 35.558 93.160 + +*CAP +0 mux_right_ipin_1\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_1\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001093151 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001093151 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 optlc_net_132:23 9.316936e-05 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 optlc_net_132:32 9.316936e-05 + +*RES +0 mux_right_ipin_1\/mux_l3_in_1_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001897322 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_1\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001068166 //LENGTH 8.760 LUMPCC 0.0001588683 DR + +*CONN +*I mux_right_ipin_5\/mux_l1_in_0_:X O *L 0 *C 55.375 55.420 +*I mux_right_ipin_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 53.460 61.540 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 53.360 61.540 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.360 61.495 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 53.360 55.465 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 53.405 55.420 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 55.338 55.420 + +*CAP +0 mux_right_ipin_5\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_5\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.297648e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003069692 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003069692 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001301913 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001301913 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[0]:54 6.429375e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:51 8.443702e-06 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:52 6.696673e-06 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[0]:53 6.429375e-05 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[0]:43 6.696673e-06 +12 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[0]:52 8.443702e-06 + +*RES +0 mux_right_ipin_5\/mux_l1_in_0_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_5\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005383929 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725446 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003367648 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_8\/mux_l3_in_1_:X O *L 0 *C 21.335 42.500 +*I mux_right_ipin_8\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.690 42.500 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 18.727 42.500 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 21.297 42.500 + +*CAP +0 mux_right_ipin_8\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_8\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001673824 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001673824 + +*RES +0 mux_right_ipin_8\/mux_l3_in_1_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_8\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002294643 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001727 //LENGTH 14.170 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_9\/mux_l2_in_2_:X O *L 0 *C 72.395 30.600 +*I mux_right_ipin_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 64.765 25.500 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 64.803 25.500 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 65.275 25.500 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 65.320 25.545 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 65.320 27.823 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 65.328 27.880 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 72.213 27.880 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 72.220 27.938 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 72.220 30.555 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 72.220 30.600 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 72.395 30.600 + +*CAP +0 mux_right_ipin_9\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_9\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.093415e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.093415e-05 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001420726 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001420726 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004277293 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0004277293 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001722703 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001722703 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 6.179402e-05 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 5.719302e-05 + +*RES +0 mux_right_ipin_9\/mux_l2_in_2_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_9\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002033482 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.00107865 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002337054 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003273836 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_13\/mux_l1_in_1_:X O *L 0 *C 51.235 11.560 +*I mux_right_ipin_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 49.050 11.560 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 49.088 11.560 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 51.198 11.560 + +*CAP +0 mux_right_ipin_13\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_13\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001626918 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001626918 + +*RES +0 mux_right_ipin_13\/mux_l1_in_1_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_13\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004757973 //LENGTH 3.215 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_2\/mux_l2_in_2_:X O *L 0 *C 18.115 93.840 +*I mux_right_ipin_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 15.545 94.180 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 15.545 94.180 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 15.640 93.840 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 18.078 93.840 + +*CAP +0 mux_right_ipin_2\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_2\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.286601e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002204203 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000190511 + +*RES +0 mux_right_ipin_2\/mux_l2_in_2_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_2\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002176339 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005205786 //LENGTH 3.670 LUMPCC 0.0002045762 DR + +*CONN +*I mux_right_ipin_6\/mux_l2_in_1_:X O *L 0 *C 29.615 64.600 +*I mux_right_ipin_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 28.235 65.960 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 28.273 65.960 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 28.935 65.960 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 28.980 65.915 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 28.980 64.645 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 29.025 64.600 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 29.578 64.600 + +*CAP +0 mux_right_ipin_6\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_6\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.487e-05 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.487e-05 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.325313e-05 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.325313e-05 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.887807e-05 +7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.887807e-05 +8 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[17]:12 4.383522e-05 +9 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[17]:13 4.383522e-05 +10 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[3]:45 4.383522e-05 +11 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[3]:43 1.461764e-05 +12 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[3]:44 4.383522e-05 +13 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[3]:42 1.461764e-05 + +*RES +0 mux_right_ipin_6\/mux_l2_in_1_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_6\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005915178 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +6 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008403747 //LENGTH 7.040 LUMPCC 9.213076e-05 DR + +*CONN +*I mux_right_ipin_10\/mux_l2_in_2_:X O *L 0 *C 13.515 40.120 +*I mux_right_ipin_10\/mux_l3_in_1_:A1 I *L 0.00198 *C 9.105 41.820 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 9.143 41.820 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 11.915 41.820 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 11.960 41.775 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 11.960 40.165 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 12.005 40.120 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 13.478 40.120 + +*CAP +0 mux_right_ipin_10\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_10\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001423228 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001423228 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001126021 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001126021 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000118197 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000118197 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.606538e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.606538e-05 + +*RES +0 mux_right_ipin_10\/mux_l2_in_2_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_10\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002475447 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00190125 //LENGTH 14.410 LUMPCC 0.0007459333 DR + +*CONN +*I mux_right_ipin_14\/mux_l3_in_0_:X O *L 0 *C 35.595 44.540 +*I mux_right_ipin_14\/mux_l4_in_0_:A1 I *L 0.00198 *C 35.325 56.100 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 35.288 56.100 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 34.545 56.100 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 34.500 56.055 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 34.500 44.585 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 34.545 44.540 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 35.558 44.540 + +*CAP +0 mux_right_ipin_14\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_14\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.9349e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.9349e-05 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004181307 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004181307 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.917894e-05 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.917894e-05 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[17]:24 0.0002248672 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[17]:23 0.0002248672 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_top_in[19]:6 6.232403e-06 +11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_top_in[19]:27 6.232403e-06 +12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[19]:27 0.000141867 +13 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[19]:26 0.000141867 + +*RES +0 mux_right_ipin_14\/mux_l3_in_0_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_14\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0006629464 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01024107 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET ropt_net_169 0.001052438 //LENGTH 7.285 LUMPCC 0.0004210992 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 52.175 98.600 +*I ropt_mt_inst_778:A I *L 0.001767 *C 49.220 102.000 +*N ropt_net_169:2 *C 49.258 102.000 +*N ropt_net_169:3 *C 49.635 102.000 +*N ropt_net_169:4 *C 49.680 101.955 +*N ropt_net_169:5 *C 49.680 98.645 +*N ropt_net_169:6 *C 49.725 98.600 +*N ropt_net_169:7 *C 52.138 98.600 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 ropt_mt_inst_778:A 1e-06 +2 ropt_net_169:2 5.227008e-05 +3 ropt_net_169:3 5.227008e-05 +4 ropt_net_169:4 0.0001094312 +5 ropt_net_169:5 0.0001094312 +6 ropt_net_169:6 0.0001529682 +7 ropt_net_169:7 0.0001529682 +8 ropt_net_169:7 chany_bottom_in[19]:6 3.758378e-05 +9 ropt_net_169:6 chany_bottom_in[19]:7 3.758378e-05 +10 ropt_net_169:5 chany_bottom_in[19]:8 6.8521e-05 +11 ropt_net_169:3 chany_bottom_in[19]:10 8.994408e-06 +12 ropt_net_169:4 chany_bottom_in[19]:9 6.8521e-05 +13 ropt_net_169:2 chany_bottom_in[19]:11 8.994408e-06 +14 ropt_net_169:5 chany_top_in[12]:31 9.54504e-05 +15 ropt_net_169:4 chany_top_in[12]:32 9.54504e-05 + +*RES +0 ropt_mt_inst_736:X ropt_net_169:7 0.152 +1 ropt_net_169:7 ropt_net_169:6 0.002154018 +2 ropt_net_169:6 ropt_net_169:5 0.0045 +3 ropt_net_169:5 ropt_net_169:4 0.002955357 +4 ropt_net_169:3 ropt_net_169:2 0.0003370536 +5 ropt_net_169:4 ropt_net_169:3 0.0045 +6 ropt_net_169:2 ropt_mt_inst_778:A 0.152 + +*END + +*D_NET ropt_net_168 0.002066039 //LENGTH 13.050 LUMPCC 0.000597285 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 39.755 99.620 +*I ropt_mt_inst_777:A I *L 0.001766 *C 35.265 102.000 +*N ropt_net_168:2 *C 35.303 102.000 +*N ropt_net_168:3 *C 37.215 102.000 +*N ropt_net_168:4 *C 37.260 101.955 +*N ropt_net_168:5 *C 37.260 97.297 +*N ropt_net_168:6 *C 37.267 97.240 +*N ropt_net_168:7 *C 39.553 97.240 +*N ropt_net_168:8 *C 39.560 97.297 +*N ropt_net_168:9 *C 39.560 99.575 +*N ropt_net_168:10 *C 39.560 99.620 +*N ropt_net_168:11 *C 39.755 99.620 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 ropt_mt_inst_777:A 1e-06 +2 ropt_net_168:2 0.0001572784 +3 ropt_net_168:3 0.0001572784 +4 ropt_net_168:4 0.0003042966 +5 ropt_net_168:5 0.0003042966 +6 ropt_net_168:6 0.0001081854 +7 ropt_net_168:7 0.0001081854 +8 ropt_net_168:8 0.00010397 +9 ropt_net_168:9 0.00010397 +10 ropt_net_168:10 6.153888e-05 +11 ropt_net_168:11 5.775479e-05 +12 ropt_net_168:4 chany_bottom_in[9]:14 2.096343e-06 +13 ropt_net_168:5 chany_bottom_in[9]:13 2.096343e-06 +14 ropt_net_168:6 chany_bottom_in[9]:16 6.570626e-05 +15 ropt_net_168:7 chany_bottom_in[9]:15 6.570626e-05 +16 ropt_net_168:4 chany_bottom_in[14]:11 2.274636e-05 +17 ropt_net_168:4 chany_bottom_in[14]:12 1.564366e-06 +18 ropt_net_168:5 chany_bottom_in[14]:10 2.274636e-05 +19 ropt_net_168:5 chany_bottom_in[14]:13 1.564366e-06 +20 ropt_net_168:8 chany_bottom_in[14]:10 7.014565e-07 +21 ropt_net_168:8 chany_bottom_in[14]:13 6.758175e-05 +22 ropt_net_168:9 chany_bottom_in[14]:11 7.014565e-07 +23 ropt_net_168:9 chany_bottom_in[14]:12 6.758175e-05 +24 ropt_net_168:6 prog_clk[0]:375 0.000138246 +25 ropt_net_168:7 prog_clk[0]:371 0.000138246 + +*RES +0 ropt_mt_inst_747:X ropt_net_168:11 0.152 +1 ropt_net_168:2 ropt_mt_inst_777:A 0.152 +2 ropt_net_168:3 ropt_net_168:2 0.001707589 +3 ropt_net_168:4 ropt_net_168:3 0.0045 +4 ropt_net_168:5 ropt_net_168:4 0.004158482 +5 ropt_net_168:6 ropt_net_168:5 0.00341 +6 ropt_net_168:8 ropt_net_168:7 0.00341 +7 ropt_net_168:7 ropt_net_168:6 0.0003579833 +8 ropt_net_168:10 ropt_net_168:9 0.0045 +9 ropt_net_168:9 ropt_net_168:8 0.002033482 +10 ropt_net_168:11 ropt_net_168:10 0.0001059783 + +*END + +*D_NET ropt_net_183 0.0001065776 //LENGTH 0.935 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 24.195 104.720 +*I ropt_mt_inst_799:A I *L 0.001767 *C 24.840 104.720 +*N ropt_net_183:2 *C 24.803 104.720 +*N ropt_net_183:3 *C 24.233 104.720 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_183:2 5.228878e-05 +3 ropt_net_183:3 5.228878e-05 + +*RES +0 ropt_mt_inst_760:X ropt_net_183:3 0.152 +1 ropt_net_183:3 ropt_net_183:2 0.0005089286 +2 ropt_net_183:2 ropt_mt_inst_799:A 0.152 + +*END + +*D_NET chany_bottom_out[0] 0.001284729 //LENGTH 9.075 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 54.740 7.140 +*P chany_bottom_out[0] O *L 0.7423 *C 51.980 1.290 +*N chany_bottom_out[0]:2 *C 51.980 7.095 +*N chany_bottom_out[0]:3 *C 52.025 7.140 +*N chany_bottom_out[0]:4 *C 54.703 7.140 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 chany_bottom_out[0] 0.0003885863 +2 chany_bottom_out[0]:2 0.0003885863 +3 chany_bottom_out[0]:3 0.0002532781 +4 chany_bottom_out[0]:4 0.0002532781 + +*RES +0 ropt_mt_inst_792:X chany_bottom_out[0]:4 0.152 +1 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002390625 +2 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +3 chany_bottom_out[0]:2 chany_bottom_out[0] 0.005183036 + +*END + +*D_NET chany_bottom_in[10] 0.01863659 //LENGTH 156.235 LUMPCC 0.003108996 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 68.080 1.290 +*I mux_left_ipin_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 72.380 49.980 +*I mux_right_ipin_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.055 59.160 +*I BUFT_P_98:A I *L 0.001776 *C 31.740 104.720 +*I mux_right_ipin_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 72.510 17.000 +*N chany_bottom_in[10]:5 *C 72.472 17.000 +*N chany_bottom_in[10]:6 *C 68.600 17.000 +*N chany_bottom_in[10]:7 *C 68.290 36.720 +*N chany_bottom_in[10]:8 *C 31.740 104.720 +*N chany_bottom_in[10]:9 *C 31.740 104.040 +*N chany_bottom_in[10]:10 *C 33.075 104.040 +*N chany_bottom_in[10]:11 *C 33.120 104.040 +*N chany_bottom_in[10]:12 *C 33.128 104.040 +*N chany_bottom_in[10]:13 *C 60.700 104.040 +*N chany_bottom_in[10]:14 *C 60.720 104.032 +*N chany_bottom_in[10]:15 *C 59.055 59.160 +*N chany_bottom_in[10]:16 *C 59.340 59.160 +*N chany_bottom_in[10]:17 *C 59.340 59.115 +*N chany_bottom_in[10]:18 *C 59.340 58.538 +*N chany_bottom_in[10]:19 *C 59.348 58.480 +*N chany_bottom_in[10]:20 *C 60.700 58.480 +*N chany_bottom_in[10]:21 *C 60.720 58.480 +*N chany_bottom_in[10]:22 *C 60.720 53.047 +*N chany_bottom_in[10]:23 *C 60.740 53.040 +*N chany_bottom_in[10]:24 *C 68.993 53.040 +*N chany_bottom_in[10]:25 *C 69.000 52.983 +*N chany_bottom_in[10]:26 *C 72.343 49.980 +*N chany_bottom_in[10]:27 *C 69.045 49.980 +*N chany_bottom_in[10]:28 *C 69.000 49.980 +*N chany_bottom_in[10]:29 *C 69.000 36.778 +*N chany_bottom_in[10]:30 *C 68.998 36.720 +*N chany_bottom_in[10]:31 *C 69.000 36.712 +*N chany_bottom_in[10]:32 *C 69.000 17.008 +*N chany_bottom_in[10]:33 *C 69.000 17.000 +*N chany_bottom_in[10]:34 *C 69.000 17.000 +*N chany_bottom_in[10]:35 *C 69.000 17.000 +*N chany_bottom_in[10]:36 *C 68.125 17.000 +*N chany_bottom_in[10]:37 *C 68.080 16.955 + +*CAP +0 chany_bottom_in[10] 0.0006242133 +1 mux_left_ipin_0\/mux_l2_in_1_:A0 1e-06 +2 mux_right_ipin_5\/mux_l2_in_1_:A0 1e-06 +3 BUFT_P_98:A 1e-06 +4 mux_right_ipin_9\/mux_l2_in_1_:A0 1e-06 +5 chany_bottom_in[10]:5 0.0002347769 +6 chany_bottom_in[10]:6 5.663514e-05 +7 chany_bottom_in[10]:7 7.768693e-05 +8 chany_bottom_in[10]:8 8.449135e-05 +9 chany_bottom_in[10]:9 0.0001627123 +10 chany_bottom_in[10]:10 0.0001111928 +11 chany_bottom_in[10]:11 3.92786e-05 +12 chany_bottom_in[10]:12 0.001664282 +13 chany_bottom_in[10]:13 0.001664282 +14 chany_bottom_in[10]:14 0.001844263 +15 chany_bottom_in[10]:15 5.209388e-05 +16 chany_bottom_in[10]:16 5.785006e-05 +17 chany_bottom_in[10]:17 5.470346e-05 +18 chany_bottom_in[10]:18 5.470346e-05 +19 chany_bottom_in[10]:19 0.0001702899 +20 chany_bottom_in[10]:20 0.0001702899 +21 chany_bottom_in[10]:21 0.001927376 +22 chany_bottom_in[10]:22 8.311373e-05 +23 chany_bottom_in[10]:23 0.0004861055 +24 chany_bottom_in[10]:24 0.0004861055 +25 chany_bottom_in[10]:25 0.0001877451 +26 chany_bottom_in[10]:26 0.0001973212 +27 chany_bottom_in[10]:27 0.0001973212 +28 chany_bottom_in[10]:28 0.0009538876 +29 chany_bottom_in[10]:29 0.0007396533 +30 chany_bottom_in[10]:30 7.768693e-05 +31 chany_bottom_in[10]:31 0.0009718446 +32 chany_bottom_in[10]:32 0.0009718446 +33 chany_bottom_in[10]:33 5.663514e-05 +34 chany_bottom_in[10]:34 3.285376e-05 +35 chany_bottom_in[10]:35 0.0003353625 +36 chany_bottom_in[10]:36 7.078541e-05 +37 chany_bottom_in[10]:37 0.0006242133 +38 chany_bottom_in[10]:22 chany_bottom_in[5]:20 0.0001357623 +39 chany_bottom_in[10]:14 chany_bottom_in[5]:19 0.0003221174 +40 chany_bottom_in[10]:21 chany_bottom_in[5]:19 0.0001357623 +41 chany_bottom_in[10]:21 chany_bottom_in[5]:20 0.0003221174 +42 chany_bottom_in[10] chany_bottom_in[18] 0.0002144036 +43 chany_bottom_in[10]:23 chany_bottom_in[18]:22 1.701659e-05 +44 chany_bottom_in[10]:22 chany_bottom_in[18]:21 6.532486e-05 +45 chany_bottom_in[10]:24 chany_bottom_in[18]:5 1.701659e-05 +46 chany_bottom_in[10]:14 chany_bottom_in[18]:20 0.0003223514 +47 chany_bottom_in[10]:21 chany_bottom_in[18]:20 6.532486e-05 +48 chany_bottom_in[10]:21 chany_bottom_in[18]:21 0.0003223514 +49 chany_bottom_in[10]:37 chany_bottom_in[18]:28 0.0002144036 +50 chany_bottom_in[10]:13 chany_top_in[5]:23 0.000415281 +51 chany_bottom_in[10]:12 chany_top_in[5]:22 0.000415281 +52 chany_bottom_in[10]:13 ropt_net_173:7 6.224134e-05 +53 chany_bottom_in[10]:12 ropt_net_173:6 6.224134e-05 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:37 0.01398661 +1 chany_bottom_in[10]:23 chany_bottom_in[10]:22 0.00341 +2 chany_bottom_in[10]:22 chany_bottom_in[10]:21 0.0008510916 +3 chany_bottom_in[10]:25 chany_bottom_in[10]:24 0.00341 +4 chany_bottom_in[10]:24 chany_bottom_in[10]:23 0.001292892 +5 chany_bottom_in[10]:35 chany_bottom_in[10]:34 0.0045 +6 chany_bottom_in[10]:35 chany_bottom_in[10]:5 0.003100446 +7 chany_bottom_in[10]:34 chany_bottom_in[10]:33 0.00341 +8 chany_bottom_in[10]:33 chany_bottom_in[10]:32 0.00341 +9 chany_bottom_in[10]:33 chany_bottom_in[10]:6 5.69697e-05 +10 chany_bottom_in[10]:32 chany_bottom_in[10]:31 0.003087116 +11 chany_bottom_in[10]:30 chany_bottom_in[10]:29 0.00341 +12 chany_bottom_in[10]:30 chany_bottom_in[10]:7 0.0001039141 +13 chany_bottom_in[10]:31 chany_bottom_in[10]:30 0.00341 +14 chany_bottom_in[10]:29 chany_bottom_in[10]:28 0.01178795 +15 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.004319691 +16 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.00341 +17 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.0045 +18 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.00341 +19 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.001191964 +20 chany_bottom_in[10]:8 BUFT_P_98:A 0.152 +21 chany_bottom_in[10]:5 mux_right_ipin_9\/mux_l2_in_1_:A0 0.152 +22 chany_bottom_in[10]:20 chany_bottom_in[10]:19 0.0002118916 +23 chany_bottom_in[10]:21 chany_bottom_in[10]:20 0.00341 +24 chany_bottom_in[10]:21 chany_bottom_in[10]:14 0.007136558 +25 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.000515625 +26 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.00341 +27 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.0001548913 +28 chany_bottom_in[10]:17 chany_bottom_in[10]:16 0.0045 +29 chany_bottom_in[10]:15 mux_right_ipin_5\/mux_l2_in_1_:A0 0.152 +30 chany_bottom_in[10]:27 chany_bottom_in[10]:26 0.002944197 +31 chany_bottom_in[10]:28 chany_bottom_in[10]:27 0.0045 +32 chany_bottom_in[10]:28 chany_bottom_in[10]:25 0.002680804 +33 chany_bottom_in[10]:26 mux_left_ipin_0\/mux_l2_in_1_:A0 0.152 +34 chany_bottom_in[10]:36 chany_bottom_in[10]:35 0.00078125 +35 chany_bottom_in[10]:37 chany_bottom_in[10]:36 0.0045 +36 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[2] 0.003677031 //LENGTH 30.760 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 49.065 47.940 +*I mux_right_ipin_14\/mux_l3_in_0_:S I *L 0.00357 *C 38.300 45.560 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 43.415 53.380 +*I mux_right_ipin_14\/mux_l3_in_1_:S I *L 0.00357 *C 36.440 51.000 +*N mux_tree_tapbuf_size8_6_sram[2]:4 *C 36.477 51.000 +*N mux_tree_tapbuf_size8_6_sram[2]:5 *C 39.100 51.000 +*N mux_tree_tapbuf_size8_6_sram[2]:6 *C 39.100 50.320 +*N mux_tree_tapbuf_size8_6_sram[2]:7 *C 43.378 53.380 +*N mux_tree_tapbuf_size8_6_sram[2]:8 *C 40.525 53.380 +*N mux_tree_tapbuf_size8_6_sram[2]:9 *C 40.480 53.335 +*N mux_tree_tapbuf_size8_6_sram[2]:10 *C 38.337 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:11 *C 40.435 45.560 +*N mux_tree_tapbuf_size8_6_sram[2]:12 *C 40.480 45.605 +*N mux_tree_tapbuf_size8_6_sram[2]:13 *C 40.480 50.320 +*N mux_tree_tapbuf_size8_6_sram[2]:14 *C 40.480 50.320 +*N mux_tree_tapbuf_size8_6_sram[2]:15 *C 47.335 50.320 +*N mux_tree_tapbuf_size8_6_sram[2]:16 *C 47.380 50.275 +*N mux_tree_tapbuf_size8_6_sram[2]:17 *C 47.380 47.985 +*N mux_tree_tapbuf_size8_6_sram[2]:18 *C 47.425 47.940 +*N mux_tree_tapbuf_size8_6_sram[2]:19 *C 49.028 47.940 + +*CAP +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_14\/mux_l3_in_0_:S 1e-06 +2 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_14\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_6_sram[2]:4 0.0002176737 +5 mux_tree_tapbuf_size8_6_sram[2]:5 0.0002625522 +6 mux_tree_tapbuf_size8_6_sram[2]:6 0.0001460349 +7 mux_tree_tapbuf_size8_6_sram[2]:7 0.0002123493 +8 mux_tree_tapbuf_size8_6_sram[2]:8 0.0002123493 +9 mux_tree_tapbuf_size8_6_sram[2]:9 0.0001575094 +10 mux_tree_tapbuf_size8_6_sram[2]:10 0.0001689256 +11 mux_tree_tapbuf_size8_6_sram[2]:11 0.0001689256 +12 mux_tree_tapbuf_size8_6_sram[2]:12 0.0002662514 +13 mux_tree_tapbuf_size8_6_sram[2]:13 0.0004530685 +14 mux_tree_tapbuf_size8_6_sram[2]:14 0.0005170609 +15 mux_tree_tapbuf_size8_6_sram[2]:15 0.0003815045 +16 mux_tree_tapbuf_size8_6_sram[2]:16 0.0001386883 +17 mux_tree_tapbuf_size8_6_sram[2]:17 0.0001386883 +18 mux_tree_tapbuf_size8_6_sram[2]:18 0.0001157244 +19 mux_tree_tapbuf_size8_6_sram[2]:19 0.0001157244 + +*RES +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_6_sram[2]:19 0.152 +1 mux_tree_tapbuf_size8_6_sram[2]:10 mux_right_ipin_14\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_6_sram[2]:11 mux_tree_tapbuf_size8_6_sram[2]:10 0.001872768 +3 mux_tree_tapbuf_size8_6_sram[2]:12 mux_tree_tapbuf_size8_6_sram[2]:11 0.0045 +4 mux_tree_tapbuf_size8_6_sram[2]:8 mux_tree_tapbuf_size8_6_sram[2]:7 0.002546875 +5 mux_tree_tapbuf_size8_6_sram[2]:9 mux_tree_tapbuf_size8_6_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size8_6_sram[2]:7 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size8_6_sram[2]:15 mux_tree_tapbuf_size8_6_sram[2]:14 0.006120536 +8 mux_tree_tapbuf_size8_6_sram[2]:16 mux_tree_tapbuf_size8_6_sram[2]:15 0.0045 +9 mux_tree_tapbuf_size8_6_sram[2]:18 mux_tree_tapbuf_size8_6_sram[2]:17 0.0045 +10 mux_tree_tapbuf_size8_6_sram[2]:17 mux_tree_tapbuf_size8_6_sram[2]:16 0.002044643 +11 mux_tree_tapbuf_size8_6_sram[2]:19 mux_tree_tapbuf_size8_6_sram[2]:18 0.001430804 +12 mux_tree_tapbuf_size8_6_sram[2]:4 mux_right_ipin_14\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size8_6_sram[2]:14 mux_tree_tapbuf_size8_6_sram[2]:13 0.0045 +14 mux_tree_tapbuf_size8_6_sram[2]:14 mux_tree_tapbuf_size8_6_sram[2]:6 0.001232143 +15 mux_tree_tapbuf_size8_6_sram[2]:13 mux_tree_tapbuf_size8_6_sram[2]:12 0.004209822 +16 mux_tree_tapbuf_size8_6_sram[2]:13 mux_tree_tapbuf_size8_6_sram[2]:9 0.002691964 +17 mux_tree_tapbuf_size8_6_sram[2]:5 mux_tree_tapbuf_size8_6_sram[2]:4 0.002341518 +18 mux_tree_tapbuf_size8_6_sram[2]:6 mux_tree_tapbuf_size8_6_sram[2]:5 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_3_ccff_tail[0] 0.006689141 //LENGTH 58.120 LUMPCC 0.003516456 DR + +*CONN +*I mem_right_ipin_7\/FTB_13__52:X O *L 0 *C 67.385 93.840 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.320 39.100 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 *C 66.760 93.840 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 *C 66.760 41.480 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 *C 67.297 39.073 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 *C 67.160 38.760 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 *C 67.160 38.805 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 *C 67.160 41.422 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 *C 67.160 41.480 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 *C 67.160 41.488 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 *C 67.160 93.833 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 *C 67.160 93.840 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 *C 67.160 93.840 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 *C 67.160 93.840 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 *C 67.385 93.840 + +*CAP +0 mem_right_ipin_7\/FTB_13__52:X 1e-06 +1 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 6.353494e-05 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 6.794692e-05 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 3.421631e-05 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 6.524344e-05 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.0001667488 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.0001667488 +8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 6.794692e-05 +9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.001161815 +10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.001161815 +11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 6.353494e-05 +12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 3.57859e-05 +13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 5.804311e-05 +14 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 5.73036e-05 +15 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 chany_bottom_in[18]:20 0.0006049675 +16 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 chany_bottom_in[18]:21 0.0006049675 +17 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 chany_bottom_in[18]:23 2.377631e-07 +18 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 chany_bottom_in[18]:24 2.377631e-07 +19 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 chany_top_in[14]:30 0.001118587 +20 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 chany_top_in[14]:31 1.480691e-05 +21 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 chany_top_in[14]:27 1.437937e-05 +22 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 chany_top_in[14]:29 0.001118587 +23 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 chany_top_in[14]:30 1.480691e-05 +24 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 chany_top_in[14]:26 5.249433e-06 +25 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 chany_top_in[14]:25 5.249433e-06 +26 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 chany_top_in[14]:28 1.437937e-05 + +*RES +0 mem_right_ipin_7\/FTB_13__52:X mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 0.152 +1 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:14 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 0.0001005435 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 0.0045 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 0.00341 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 0.00341 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 5.696969e-05 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 0.008200716 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.00341 +8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 5.69697e-05 +9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:9 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:8 0.00341 +10 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.002337054 +11 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.0002111487 +12 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.0045 +13 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001960765 //LENGTH 15.100 LUMPCC 0.0002997429 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_2_:X O *L 0 *C 41.115 85.000 +*I mux_right_ipin_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 31.645 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 31.683 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 32.200 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 32.200 89.080 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 39.975 89.080 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 40.020 89.035 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 40.020 85.045 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 40.065 85.000 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 41.078 85.000 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.529512e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.010472e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004557322 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004309226 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002297574 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002297574 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001087262 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001087262 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:10 2.833806e-05 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:15 1.34865e-05 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:16 0.0001079138 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:10 1.331075e-07 +14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:15 2.833806e-05 +15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:4 1.331075e-07 +16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:10 1.34865e-05 +17 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:15 0.0001079138 + +*RES +0 mux_right_ipin_0\/mux_l2_in_2_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_0\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006941964 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0035625 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0009040179 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004620536 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004491959 //LENGTH 2.475 LUMPCC 0.0003643684 DR + +*CONN +*I mux_right_ipin_1\/mux_l2_in_3_:X O *L 0 *C 39.735 93.500 +*I mux_right_ipin_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 37.550 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 37.587 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 39.698 93.500 + +*CAP +0 mux_right_ipin_1\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_1\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.141374e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.141374e-05 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 9.109209e-05 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 9.109209e-05 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_132:5 6.256831e-05 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_132:21 2.852379e-05 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 optlc_net_132:21 6.256831e-05 +9 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 optlc_net_132:22 2.852379e-05 + +*RES +0 mux_right_ipin_1\/mux_l2_in_3_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001883929 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_1\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009548096 //LENGTH 8.255 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l2_in_1_:X O *L 0 *C 20.875 80.240 +*I mux_right_ipin_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 15.930 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 15.968 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 18.355 82.620 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 18.400 82.575 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 18.400 80.285 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 18.445 80.240 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 20.838 80.240 + +*CAP +0 mux_right_ipin_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001794624 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001794624 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001320954 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001320954 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.000164847 +7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.000164847 + +*RES +0 mux_right_ipin_4\/mux_l2_in_1_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002136161 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002131697 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_4\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001796687 //LENGTH 14.500 LUMPCC 0.0008114468 DR + +*CONN +*I mux_right_ipin_5\/mux_l2_in_2_:X O *L 0 *C 66.985 53.040 +*I mux_right_ipin_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 66.145 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 66.183 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 68.035 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 68.080 63.535 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 68.080 53.085 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 68.035 53.040 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 67.023 53.040 + +*CAP +0 mux_right_ipin_5\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_5\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001129918 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001129918 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002975301 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002975301 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.109801e-05 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.109801e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[4]:27 0.0002923883 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[4]:28 0.0002923883 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.501773e-05 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.501773e-05 +12 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.831735e-05 +13 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.831735e-05 + +*RES +0 mux_right_ipin_5\/mux_l2_in_2_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_5\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001654018 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.009330357 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007229822 //LENGTH 5.625 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_8\/mux_l2_in_1_:X O *L 0 *C 23.635 34.680 +*I mux_right_ipin_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 22.830 38.760 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 22.867 38.760 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.415 38.760 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 23.460 38.715 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 23.460 34.725 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 23.460 34.680 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 23.635 34.680 + +*CAP +0 mux_right_ipin_8\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_8\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.200473e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.200473e-05 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002431004 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002431004 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.578536e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.498652e-05 + +*RES +0 mux_right_ipin_8\/mux_l2_in_1_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_8\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00058391 //LENGTH 4.270 LUMPCC 0.0001464107 DR + +*CONN +*I mux_right_ipin_9\/mux_l2_in_1_:X O *L 0 *C 70.555 18.020 +*I mux_right_ipin_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 69.750 20.740 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 69.750 20.740 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 69.920 20.740 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 69.920 20.695 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 69.920 18.065 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 69.965 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 70.517 18.020 + +*CAP +0 mux_right_ipin_9\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_9\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.293042e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.846933e-05 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001241978 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001241978 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.785203e-05 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.785203e-05 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_bottom_in[4]:34 3.811303e-05 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[4]:35 3.811303e-05 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_6_sram[1]:23 3.509231e-05 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_6_sram[1]:24 3.509231e-05 + +*RES +0 mux_right_ipin_9\/mux_l2_in_1_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_9\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004332146 //LENGTH 2.960 LUMPCC 0.0001084693 DR + +*CONN +*I mux_right_ipin_12\/mux_l2_in_0_:X O *L 0 *C 22.715 12.920 +*I mux_right_ipin_12\/mux_l3_in_0_:A1 I *L 0.00198 *C 22.080 14.620 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.080 14.620 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.080 14.575 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 22.080 12.965 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 22.125 12.920 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 22.678 12.920 + +*CAP +0 mux_right_ipin_12\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_12\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.112345e-05 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.488246e-05 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.488246e-05 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.092848e-05 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.092848e-05 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.423463e-05 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.423463e-05 + +*RES +0 mux_right_ipin_12\/mux_l2_in_0_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004933036 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0014375 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_12\/mux_l3_in_0_:A1 0.152 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001339393 //LENGTH 9.585 LUMPCC 0.0002419075 DR + +*CONN +*I mux_right_ipin_13\/mux_l1_in_0_:X O *L 0 *C 57.215 11.560 +*I mux_right_ipin_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 49.220 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 49.258 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 51.980 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 51.980 11.560 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.178 11.560 + +*CAP +0 mux_right_ipin_13\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_13\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002021473 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002676451 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003455952 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002800974 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[2]:37 5.123283e-05 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[2]:36 5.123283e-05 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_8_sram[0]:10 2.051555e-06 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_8_sram[0]:14 6.766937e-05 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_8_sram[0]:9 2.051555e-06 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_8_sram[0]:15 6.766937e-05 + +*RES +0 mux_right_ipin_13\/mux_l1_in_0_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004640625 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_13\/mux_l2_in_0_:A1 0.152 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002430804 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0009107143 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001120858 //LENGTH 8.480 LUMPCC 0.0001362596 DR + +*CONN +*I mux_right_ipin_2\/mux_l2_in_0_:X O *L 0 *C 20.415 90.440 +*I mux_right_ipin_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 14.165 88.740 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 14.165 88.740 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 14.260 88.785 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 14.260 90.395 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 14.305 90.440 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 20.378 90.440 + +*CAP +0 mux_right_ipin_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.599444e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001102522 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001102522 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003680497 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003680497 +7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_0_sram[1]:12 6.812978e-05 +8 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_0_sram[1]:11 6.812978e-05 + +*RES +0 mux_right_ipin_2\/mux_l2_in_0_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0014375 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.005421875 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009770992 //LENGTH 8.250 LUMPCC 0.0001346994 DR + +*CONN +*I mux_right_ipin_3\/mux_l2_in_0_:X O *L 0 *C 20.985 61.880 +*I mux_right_ipin_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 18.765 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 18.803 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 20.195 66.980 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 20.240 66.935 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 20.240 61.925 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 20.285 61.880 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 20.948 61.880 + +*CAP +0 mux_right_ipin_3\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_3\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.722609e-05 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.722609e-05 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000276378 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000276378 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.659578e-05 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.659578e-05 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_1_sram[2]:6 6.73497e-05 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_1_sram[2]:5 6.73497e-05 + +*RES +0 mux_right_ipin_3\/mux_l2_in_0_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_3\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001243304 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 + +*END + +*D_NET mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004702309 //LENGTH 3.855 LUMPCC 0.0001028554 DR + +*CONN +*I mux_right_ipin_6\/mux_l2_in_3_:X O *L 0 *C 35.595 58.820 +*I mux_right_ipin_6\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.030 58.820 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 32.068 58.820 +*N mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 35.558 58.820 + +*CAP +0 mux_right_ipin_6\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_6\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001826878 +3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001826878 +4 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.142768e-05 +5 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.142768e-05 + +*RES +0 mux_right_ipin_6\/mux_l2_in_3_:X mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_6\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003116072 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001995996 //LENGTH 15.470 LUMPCC 0.0005641283 DR + +*CONN +*I mux_right_ipin_7\/mux_l3_in_1_:X O *L 0 *C 68.715 90.780 +*I mux_right_ipin_7\/mux_l4_in_0_:A0 I *L 0.001631 *C 64.230 93.500 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 64.230 93.500 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 64.400 93.500 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 64.400 93.545 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 64.400 96.855 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 64.400 96.900 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 66.195 96.900 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 66.240 96.855 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 66.240 90.825 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 66.285 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 68.678 90.780 + +*CAP +0 mux_right_ipin_7\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_7\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.721122e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.193614e-05 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001461579 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001461579 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001611684 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001276518 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002677341 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0002677341 +10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 9.70582e-05 +11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 9.70582e-05 +12 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[4]:17 7.813342e-05 +13 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[4]:18 7.813342e-05 +14 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[10]:27 9.707409e-05 +15 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[10] 9.707409e-05 +16 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_tree_tapbuf_size8_3_sram[2]:9 4.26751e-06 +17 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_tree_tapbuf_size8_3_sram[2]:6 0.0001025891 +18 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_tree_tapbuf_size8_3_sram[2]:8 4.26751e-06 +19 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_tree_tapbuf_size8_3_sram[2]:7 0.0001025891 + +*RES +0 mux_right_ipin_7\/mux_l3_in_1_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_7\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002955357 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001602679 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.005383929 +10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.002136161 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001349359 //LENGTH 9.620 LUMPCC 0.000136788 DR + +*CONN +*I mux_right_ipin_11\/mux_l2_in_2_:X O *L 0 *C 28.695 55.080 +*I mux_right_ipin_11\/mux_l3_in_1_:A1 I *L 0.00198 *C 22.080 52.700 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.080 52.700 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.080 52.745 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 22.080 55.035 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 22.125 55.080 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 28.658 55.080 + +*CAP +0 mux_right_ipin_11\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_11\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.280811e-05 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001504208 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001504208 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004384604 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004384604 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.839402e-05 +8 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.839402e-05 + +*RES +0 mux_right_ipin_11\/mux_l2_in_2_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00583259 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002044643 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_11\/mux_l3_in_1_:A1 0.152 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006952612 //LENGTH 4.980 LUMPCC 0.0001023291 DR + +*CONN +*I mux_right_ipin_14\/mux_l3_in_1_:X O *L 0 *C 35.595 51.000 +*I mux_right_ipin_14\/mux_l4_in_0_:A0 I *L 0.001631 *C 35.710 55.080 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 35.710 55.080 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 35.880 55.080 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 35.880 55.035 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 35.880 51.045 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 35.880 51.000 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 35.595 51.000 + +*CAP +0 mux_right_ipin_14\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_14\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.603622e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.586773e-05 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001789864 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001789864 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.915762e-05 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.189766e-05 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[19]:27 5.116457e-05 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[19]:26 5.116457e-05 + +*RES +0 mux_right_ipin_14\/mux_l3_in_1_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_14\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.23913e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0035625 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001331522 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005832402 //LENGTH 5.235 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_15\/mux_l3_in_1_:X O *L 0 *C 76.535 80.580 +*I mux_right_ipin_15\/mux_l4_in_0_:A0 I *L 0.001631 *C 71.590 80.580 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 71.627 80.580 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 76.498 80.580 + +*CAP +0 mux_right_ipin_15\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_15\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002906201 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002906201 + +*RES +0 mux_right_ipin_15\/mux_l3_in_1_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_15\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.004348214 + +*END + +*D_NET chany_top_out[16] 0.001851411 //LENGTH 11.765 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 45.540 101.660 +*P chany_top_out[16] O *L 0.7423 *C 48.300 107.475 +*N chany_top_out[16]:2 *C 48.300 107.440 +*N chany_top_out[16]:3 *C 48.300 107.475 +*N chany_top_out[16]:4 *C 48.760 107.440 +*N chany_top_out[16]:5 *C 48.760 102.385 +*N chany_top_out[16]:6 *C 48.715 102.340 +*N chany_top_out[16]:7 *C 45.125 102.340 +*N chany_top_out[16]:8 *C 45.080 102.295 +*N chany_top_out[16]:9 *C 45.080 101.705 +*N chany_top_out[16]:10 *C 45.125 101.660 +*N chany_top_out[16]:11 *C 45.503 101.660 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 chany_top_out[16] 1e-06 +2 chany_top_out[16]:2 1.11356e-05 +3 chany_top_out[16]:3 4.033755e-05 +4 chany_top_out[16]:4 0.0004038655 +5 chany_top_out[16]:5 0.0003746636 +6 chany_top_out[16]:6 0.0003708197 +7 chany_top_out[16]:7 0.0003708197 +8 chany_top_out[16]:8 7.423532e-05 +9 chany_top_out[16]:9 7.423532e-05 +10 chany_top_out[16]:10 6.464916e-05 +11 chany_top_out[16]:11 6.464916e-05 + +*RES +0 ropt_mt_inst_734:X chany_top_out[16]:11 0.152 +1 chany_top_out[16]:11 chany_top_out[16]:10 0.0003370536 +2 chany_top_out[16]:10 chany_top_out[16]:9 0.0045 +3 chany_top_out[16]:9 chany_top_out[16]:8 0.0005267857 +4 chany_top_out[16]:7 chany_top_out[16]:6 0.003205358 +5 chany_top_out[16]:8 chany_top_out[16]:7 0.0045 +6 chany_top_out[16]:6 chany_top_out[16]:5 0.0045 +7 chany_top_out[16]:5 chany_top_out[16]:4 0.004513393 +8 chany_top_out[16]:4 chany_top_out[16]:3 0.0004109821 +9 chany_top_out[16]:3 chany_top_out[16]:2 3.098214e-05 +10 chany_top_out[16]:3 chany_top_out[16] 1e-05 + +*END + +*D_NET ropt_net_163 0.0003789223 //LENGTH 2.610 LUMPCC 0.0002332423 DR + +*CONN +*I FTB_19__18:X O *L 0 *C 24.380 101.660 +*I ropt_mt_inst_763:A I *L 0.001766 *C 26.220 102.000 +*N ropt_net_163:2 *C 26.198 101.973 +*N ropt_net_163:3 *C 26.185 101.660 +*N ropt_net_163:4 *C 24.418 101.660 + +*CAP +0 FTB_19__18:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_163:2 3.097896e-05 +3 ropt_net_163:3 7.184003e-05 +4 ropt_net_163:4 4.086106e-05 +5 ropt_net_163:2 chany_bottom_in[18]:7 5.283466e-07 +6 ropt_net_163:4 chany_bottom_in[18]:7 4.490802e-05 +7 ropt_net_163:4 chany_bottom_in[18]:8 7.118478e-05 +8 ropt_net_163:3 chany_bottom_in[18]:6 4.490802e-05 +9 ropt_net_163:3 chany_bottom_in[18]:8 5.283466e-07 +10 ropt_net_163:3 chany_bottom_in[18]:9 7.118478e-05 + +*RES +0 FTB_19__18:X ropt_net_163:4 0.152 +1 ropt_net_163:2 ropt_mt_inst_763:A 0.152 +2 ropt_net_163:4 ropt_net_163:3 0.001578125 +3 ropt_net_163:3 ropt_net_163:2 0.0002111486 + +*END + +*D_NET ropt_net_156 0.002256072 //LENGTH 15.550 LUMPCC 0.0007812351 DR + +*CONN +*I FTB_29__28:X O *L 0 *C 35.420 11.900 +*I ropt_mt_inst_755:A I *L 0.001766 *C 47.380 9.520 +*N ropt_net_156:2 *C 47.343 9.520 +*N ropt_net_156:3 *C 45.080 9.520 +*N ropt_net_156:4 *C 45.080 9.860 +*N ropt_net_156:5 *C 38.225 9.860 +*N ropt_net_156:6 *C 38.180 9.905 +*N ropt_net_156:7 *C 38.180 11.855 +*N ropt_net_156:8 *C 38.135 11.900 +*N ropt_net_156:9 *C 35.458 11.900 + +*CAP +0 FTB_29__28:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_156:2 0.0001012491 +3 ropt_net_156:3 0.0001253891 +4 ropt_net_156:4 0.0004071021 +5 ropt_net_156:5 0.0003829621 +6 ropt_net_156:6 9.869561e-05 +7 ropt_net_156:7 9.869561e-05 +8 ropt_net_156:8 0.0001293719 +9 ropt_net_156:9 0.0001293719 +10 ropt_net_156:7 chany_top_in[17]:20 6.328837e-05 +11 ropt_net_156:6 chany_top_in[17]:19 6.328837e-05 +12 ropt_net_156:5 mux_tree_tapbuf_size10_8_sram[0]:23 0.0001747665 +13 ropt_net_156:2 mux_tree_tapbuf_size10_8_sram[0]:22 4.213273e-05 +14 ropt_net_156:4 mux_tree_tapbuf_size10_8_sram[0]:22 0.0001747665 +15 ropt_net_156:3 mux_tree_tapbuf_size10_8_sram[0]:23 4.213273e-05 +16 ropt_net_156:9 ropt_net_154:4 0.0001104299 +17 ropt_net_156:8 ropt_net_154:3 0.0001104299 + +*RES +0 FTB_29__28:X ropt_net_156:9 0.152 +1 ropt_net_156:9 ropt_net_156:8 0.002390625 +2 ropt_net_156:8 ropt_net_156:7 0.0045 +3 ropt_net_156:7 ropt_net_156:6 0.001741072 +4 ropt_net_156:5 ropt_net_156:4 0.006120536 +5 ropt_net_156:6 ropt_net_156:5 0.0045 +6 ropt_net_156:2 ropt_mt_inst_755:A 0.152 +7 ropt_net_156:4 ropt_net_156:3 0.0003035715 +8 ropt_net_156:3 ropt_net_156:2 0.002020089 + +*END + +*D_NET mux_right_ipin_13/BUF_net_60 0.000421165 //LENGTH 3.810 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_13\/BUFT_RR_60:X O *L 0 *C 4.365 48.280 +*I mux_right_ipin_13\/BUFT_P_106:A I *L 0.001767 *C 3.220 50.320 +*N mux_right_ipin_13/BUF_net_60:2 *C 3.220 50.320 +*N mux_right_ipin_13/BUF_net_60:3 *C 3.220 50.275 +*N mux_right_ipin_13/BUF_net_60:4 *C 3.220 48.325 +*N mux_right_ipin_13/BUF_net_60:5 *C 3.265 48.280 +*N mux_right_ipin_13/BUF_net_60:6 *C 4.328 48.280 + +*CAP +0 mux_right_ipin_13\/BUFT_RR_60:X 1e-06 +1 mux_right_ipin_13\/BUFT_P_106:A 1e-06 +2 mux_right_ipin_13/BUF_net_60:2 2.735848e-05 +3 mux_right_ipin_13/BUF_net_60:3 0.0001127433 +4 mux_right_ipin_13/BUF_net_60:4 0.0001127433 +5 mux_right_ipin_13/BUF_net_60:5 8.315995e-05 +6 mux_right_ipin_13/BUF_net_60:6 8.315995e-05 + +*RES +0 mux_right_ipin_13\/BUFT_RR_60:X mux_right_ipin_13/BUF_net_60:6 0.152 +1 mux_right_ipin_13/BUF_net_60:2 mux_right_ipin_13\/BUFT_P_106:A 0.152 +2 mux_right_ipin_13/BUF_net_60:3 mux_right_ipin_13/BUF_net_60:2 0.0045 +3 mux_right_ipin_13/BUF_net_60:5 mux_right_ipin_13/BUF_net_60:4 0.0045 +4 mux_right_ipin_13/BUF_net_60:4 mux_right_ipin_13/BUF_net_60:3 0.001741071 +5 mux_right_ipin_13/BUF_net_60:6 mux_right_ipin_13/BUF_net_60:5 0.0009486608 + +*END + +*D_NET BUF_net_67 0.002424544 //LENGTH 19.100 LUMPCC 0.0001849633 DR + +*CONN +*I BUFT_RR_67:X O *L 0 *C 37.260 91.800 +*I BUFT_RR_84:A I *L 0.001766 *C 26.680 99.280 +*N BUF_net_67:2 *C 26.680 99.280 +*N BUF_net_67:3 *C 26.680 98.940 +*N BUF_net_67:4 *C 33.995 98.940 +*N BUF_net_67:5 *C 34.040 98.895 +*N BUF_net_67:6 *C 34.040 91.845 +*N BUF_net_67:7 *C 34.085 91.800 +*N BUF_net_67:8 *C 37.223 91.800 + +*CAP +0 BUFT_RR_67:X 1e-06 +1 BUFT_RR_84:A 1e-06 +2 BUF_net_67:2 6.314065e-05 +3 BUF_net_67:3 0.000463693 +4 BUF_net_67:4 0.0004330782 +5 BUF_net_67:5 0.0004070187 +6 BUF_net_67:6 0.0004070187 +7 BUF_net_67:7 0.0002318159 +8 BUF_net_67:8 0.0002318159 +9 BUF_net_67:6 optlc_net_132:18 3.928459e-08 +10 BUF_net_67:4 optlc_net_132:29 9.244236e-05 +11 BUF_net_67:5 optlc_net_132:19 3.928459e-08 +12 BUF_net_67:3 optlc_net_132:28 9.244236e-05 + +*RES +0 BUFT_RR_67:X BUF_net_67:8 0.152 +1 BUF_net_67:8 BUF_net_67:7 0.002801339 +2 BUF_net_67:7 BUF_net_67:6 0.0045 +3 BUF_net_67:6 BUF_net_67:5 0.006294644 +4 BUF_net_67:4 BUF_net_67:3 0.006531251 +5 BUF_net_67:5 BUF_net_67:4 0.0045 +6 BUF_net_67:2 BUFT_RR_84:A 0.152 +7 BUF_net_67:3 BUF_net_67:2 0.0003035715 + +*END + +*D_NET ropt_net_176 0.00175136 //LENGTH 12.410 LUMPCC 0.0002441497 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 60.455 8.840 +*I ropt_mt_inst_785:A I *L 0.001766 *C 55.200 4.080 +*N ropt_net_176:2 *C 55.238 4.080 +*N ropt_net_176:3 *C 56.535 4.080 +*N ropt_net_176:4 *C 56.580 4.125 +*N ropt_net_176:5 *C 56.580 6.062 +*N ropt_net_176:6 *C 56.580 6.120 +*N ropt_net_176:7 *C 57.492 6.120 +*N ropt_net_176:8 *C 57.500 6.178 +*N ropt_net_176:9 *C 57.500 8.795 +*N ropt_net_176:10 *C 57.545 8.840 +*N ropt_net_176:11 *C 60.418 8.840 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_176:2 7.193866e-05 +3 ropt_net_176:3 7.193866e-05 +4 ropt_net_176:4 0.000126236 +5 ropt_net_176:5 0.000126236 +6 ropt_net_176:6 0.0001494606 +7 ropt_net_176:7 0.0001494606 +8 ropt_net_176:8 0.0001915478 +9 ropt_net_176:9 0.0001915478 +10 ropt_net_176:10 0.0002134223 +11 ropt_net_176:11 0.0002134223 +12 ropt_net_176:3 chany_top_in[2]:33 6.141046e-05 +13 ropt_net_176:2 chany_top_in[2]:34 6.141046e-05 +14 ropt_net_176:9 chany_top_in[17]:11 2.317109e-06 +15 ropt_net_176:8 chany_top_in[17]:12 2.317109e-06 +16 ropt_net_176:7 chany_top_in[17]:13 3.405787e-05 +17 ropt_net_176:5 chany_top_in[17]:11 2.428939e-05 +18 ropt_net_176:6 chany_top_in[17]:14 3.405787e-05 +19 ropt_net_176:4 chany_top_in[17]:12 2.428939e-05 + +*RES +0 ropt_mt_inst_761:X ropt_net_176:11 0.152 +1 ropt_net_176:11 ropt_net_176:10 0.002564732 +2 ropt_net_176:10 ropt_net_176:9 0.0045 +3 ropt_net_176:9 ropt_net_176:8 0.002337054 +4 ropt_net_176:8 ropt_net_176:7 0.00341 +5 ropt_net_176:7 ropt_net_176:6 0.0001429583 +6 ropt_net_176:5 ropt_net_176:4 0.001729911 +7 ropt_net_176:6 ropt_net_176:5 0.00341 +8 ropt_net_176:3 ropt_net_176:2 0.001158482 +9 ropt_net_176:4 ropt_net_176:3 0.0045 +10 ropt_net_176:2 ropt_mt_inst_785:A 0.152 + +*END + +*D_NET chany_top_out[10] 0.0007231831 //LENGTH 5.070 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 36.535 105.400 +*P chany_top_out[10] O *L 0.7423 *C 34.040 107.510 +*N chany_top_out[10]:2 *C 34.040 105.445 +*N chany_top_out[10]:3 *C 34.085 105.400 +*N chany_top_out[10]:4 *C 36.498 105.400 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 chany_top_out[10] 0.0001391009 +2 chany_top_out[10]:2 0.0001391009 +3 chany_top_out[10]:3 0.0002219906 +4 chany_top_out[10]:4 0.0002219906 + +*RES +0 ropt_mt_inst_800:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.002154018 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.00184375 + +*END + +*D_NET ropt_net_161 0.002488323 //LENGTH 17.770 LUMPCC 0.0006370734 DR + +*CONN +*I BUFT_P_101:X O *L 0 *C 62.100 3.400 +*I ropt_mt_inst_761:A I *L 0.001766 *C 56.580 9.520 +*N ropt_net_161:2 *C 56.543 9.520 +*N ropt_net_161:3 *C 55.705 9.520 +*N ropt_net_161:4 *C 55.660 9.475 +*N ropt_net_161:5 *C 55.660 2.085 +*N ropt_net_161:6 *C 55.705 2.040 +*N ropt_net_161:7 *C 59.295 2.040 +*N ropt_net_161:8 *C 59.340 2.085 +*N ropt_net_161:9 *C 59.340 3.355 +*N ropt_net_161:10 *C 59.385 3.400 +*N ropt_net_161:11 *C 62.062 3.400 + +*CAP +0 BUFT_P_101:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_161:2 7.369394e-05 +3 ropt_net_161:3 7.369394e-05 +4 ropt_net_161:4 0.0004558515 +5 ropt_net_161:5 0.0004558515 +6 ropt_net_161:6 0.0001660994 +7 ropt_net_161:7 0.0001660994 +8 ropt_net_161:8 9.547972e-05 +9 ropt_net_161:9 9.547972e-05 +10 ropt_net_161:10 0.0001335004 +11 ropt_net_161:11 0.0001335004 +12 ropt_net_161:7 chany_top_in[0]:17 0.0001473138 +13 ropt_net_161:6 chany_top_in[0]:16 0.0001473138 +14 ropt_net_161:11 chany_bottom_out[18]:6 0.0001154324 +15 ropt_net_161:10 chany_bottom_out[18]:5 0.0001154324 +16 ropt_net_161:7 chany_bottom_out[18]:3 1.497406e-05 +17 ropt_net_161:6 chany_bottom_out[18]:2 1.497406e-05 +18 ropt_net_161:5 chany_bottom_out[18] 4.028278e-05 +19 ropt_net_161:5 chany_bottom_out[18]:3 5.337039e-07 +20 ropt_net_161:4 chany_bottom_out[18]:2 4.028278e-05 +21 ropt_net_161:4 chany_bottom_out[18]:4 5.337039e-07 + +*RES +0 BUFT_P_101:X ropt_net_161:11 0.152 +1 ropt_net_161:11 ropt_net_161:10 0.002390625 +2 ropt_net_161:10 ropt_net_161:9 0.0045 +3 ropt_net_161:9 ropt_net_161:8 0.001133929 +4 ropt_net_161:7 ropt_net_161:6 0.003205357 +5 ropt_net_161:8 ropt_net_161:7 0.0045 +6 ropt_net_161:6 ropt_net_161:5 0.0045 +7 ropt_net_161:5 ropt_net_161:4 0.006598215 +8 ropt_net_161:3 ropt_net_161:2 0.0007477679 +9 ropt_net_161:4 ropt_net_161:3 0.0045 +10 ropt_net_161:2 ropt_mt_inst_761:A 0.152 + +*END + +*D_NET chany_bottom_in[12] 0.01546885 //LENGTH 131.795 LUMPCC 0.003547188 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 51.060 1.325 +*I mux_right_ipin_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 54.570 93.160 +*I mux_right_ipin_7\/mux_l2_in_2_:A0 I *L 0.001631 *C 76.650 93.160 +*I mux_right_ipin_15\/mux_l2_in_2_:A0 I *L 0.001631 *C 77.455 88.060 +*I FTB_13__12:A I *L 0.001767 *C 52.440 96.560 +*N chany_bottom_in[12]:5 *C 52.040 94.520 +*N chany_bottom_in[12]:6 *C 52.440 96.560 +*N chany_bottom_in[12]:7 *C 52.440 96.515 +*N chany_bottom_in[12]:8 *C 77.455 88.060 +*N chany_bottom_in[12]:9 *C 77.280 88.060 +*N chany_bottom_in[12]:10 *C 77.280 88.105 +*N chany_bottom_in[12]:11 *C 77.280 93.115 +*N chany_bottom_in[12]:12 *C 77.235 93.160 +*N chany_bottom_in[12]:13 *C 76.650 93.160 +*N chany_bottom_in[12]:14 *C 54.570 93.160 +*N chany_bottom_in[12]:15 *C 52.025 93.160 +*N chany_bottom_in[12]:16 *C 51.980 93.160 +*N chany_bottom_in[12]:17 *C 52.440 93.160 +*N chany_bottom_in[12]:18 *C 52.440 94.520 +*N chany_bottom_in[12]:19 *C 52.440 94.520 +*N chany_bottom_in[12]:20 *C 52.440 94.513 +*N chany_bottom_in[12]:21 *C 52.440 52.555 +*N chany_bottom_in[12]:22 *C 52.440 2.728 +*N chany_bottom_in[12]:23 *C 52.420 2.720 +*N chany_bottom_in[12]:24 *C 51.068 2.720 +*N chany_bottom_in[12]:25 *C 51.060 2.663 + +*CAP +0 chany_bottom_in[12] 9.191372e-05 +1 mux_right_ipin_1\/mux_l2_in_1_:A0 1e-06 +2 mux_right_ipin_7\/mux_l2_in_2_:A0 1e-06 +3 mux_right_ipin_15\/mux_l2_in_2_:A0 1e-06 +4 FTB_13__12:A 1e-06 +5 chany_bottom_in[12]:5 6.604094e-05 +6 chany_bottom_in[12]:6 3.58892e-05 +7 chany_bottom_in[12]:7 0.0001259547 +8 chany_bottom_in[12]:8 5.436121e-05 +9 chany_bottom_in[12]:9 5.538313e-05 +10 chany_bottom_in[12]:10 0.0002693273 +11 chany_bottom_in[12]:11 0.0002693273 +12 chany_bottom_in[12]:12 4.797123e-05 +13 chany_bottom_in[12]:13 0.001515944 +14 chany_bottom_in[12]:14 0.001638891 +15 chany_bottom_in[12]:15 0.0001689983 +16 chany_bottom_in[12]:16 5.741344e-05 +17 chany_bottom_in[12]:17 0.000106408 +18 chany_bottom_in[12]:18 0.0002452274 +19 chany_bottom_in[12]:19 6.604094e-05 +20 chany_bottom_in[12]:20 0.001533748 +21 chany_bottom_in[12]:21 0.003400334 +22 chany_bottom_in[12]:22 0.001866587 +23 chany_bottom_in[12]:23 0.0001049922 +24 chany_bottom_in[12]:24 0.0001049922 +25 chany_bottom_in[12]:25 9.191372e-05 +26 chany_bottom_in[12]:20 chany_top_in[18]:19 0.000647417 +27 chany_bottom_in[12]:20 chany_top_in[18]:18 0.0002295127 +28 chany_bottom_in[12]:22 chany_top_in[18]:17 0.0008522233 +29 chany_bottom_in[12]:21 chany_top_in[18]:17 0.0002295127 +30 chany_bottom_in[12]:21 chany_top_in[18]:18 0.00149964 +31 chany_bottom_in[12]:15 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.388971e-05 +32 chany_bottom_in[12]:16 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.055134e-05 +33 chany_bottom_in[12]:14 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.388971e-05 +34 chany_bottom_in[12]:17 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.055134e-05 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:25 0.001194197 +1 chany_bottom_in[12]:6 FTB_13__12:A 0.152 +2 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.0045 +3 chany_bottom_in[12]:18 chany_bottom_in[12]:17 0.001214286 +4 chany_bottom_in[12]:18 chany_bottom_in[12]:7 0.00178125 +5 chany_bottom_in[12]:19 chany_bottom_in[12]:18 0.00341 +6 chany_bottom_in[12]:19 chany_bottom_in[12]:5 5.69697e-05 +7 chany_bottom_in[12]:20 chany_bottom_in[12]:19 0.00341 +8 chany_bottom_in[12]:23 chany_bottom_in[12]:22 0.00341 +9 chany_bottom_in[12]:22 chany_bottom_in[12]:21 0.007806308 +10 chany_bottom_in[12]:25 chany_bottom_in[12]:24 0.00341 +11 chany_bottom_in[12]:24 chany_bottom_in[12]:23 0.0002118916 +12 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.002272322 +13 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.0045 +14 chany_bottom_in[12]:13 mux_right_ipin_7\/mux_l2_in_2_:A0 0.152 +15 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.0005223214 +16 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0045 +17 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.004473215 +18 chany_bottom_in[12]:9 chany_bottom_in[12]:8 9.51087e-05 +19 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.0045 +20 chany_bottom_in[12]:8 mux_right_ipin_15\/mux_l2_in_2_:A0 0.152 +21 chany_bottom_in[12]:14 mux_right_ipin_1\/mux_l2_in_1_:A0 0.152 +22 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.01971429 +23 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.0004107143 +24 chany_bottom_in[12]:21 chany_bottom_in[12]:20 0.006573341 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[0] 0.004225624 //LENGTH 30.820 LUMPCC 0.0001683339 DR + +*CONN +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.550 83.300 +*I mux_right_ipin_1\/mux_l1_in_1_:S I *L 0.00357 *C 52.540 85.390 +*I mux_right_ipin_1\/mux_l1_in_0_:S I *L 0.00357 *C 57.600 91.195 +*I mux_right_ipin_1\/mux_l1_in_2_:S I *L 0.00357 *C 58.520 95.805 +*I mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 61.770 98.940 +*N mux_tree_tapbuf_size10_2_sram[0]:5 *C 61.748 98.913 +*N mux_tree_tapbuf_size10_2_sram[0]:6 *C 61.735 98.600 +*N mux_tree_tapbuf_size10_2_sram[0]:7 *C 60.305 98.600 +*N mux_tree_tapbuf_size10_2_sram[0]:8 *C 60.260 98.555 +*N mux_tree_tapbuf_size10_2_sram[0]:9 *C 60.260 95.925 +*N mux_tree_tapbuf_size10_2_sram[0]:10 *C 60.215 95.880 +*N mux_tree_tapbuf_size10_2_sram[0]:11 *C 58.520 95.805 +*N mux_tree_tapbuf_size10_2_sram[0]:12 *C 55.705 95.880 +*N mux_tree_tapbuf_size10_2_sram[0]:13 *C 55.660 95.835 +*N mux_tree_tapbuf_size10_2_sram[0]:14 *C 57.600 91.195 +*N mux_tree_tapbuf_size10_2_sram[0]:15 *C 55.705 91.120 +*N mux_tree_tapbuf_size10_2_sram[0]:16 *C 55.660 91.120 +*N mux_tree_tapbuf_size10_2_sram[0]:17 *C 55.660 85.725 +*N mux_tree_tapbuf_size10_2_sram[0]:18 *C 55.615 85.680 +*N mux_tree_tapbuf_size10_2_sram[0]:19 *C 52.540 85.390 +*N mux_tree_tapbuf_size10_2_sram[0]:20 *C 52.583 85.650 +*N mux_tree_tapbuf_size10_2_sram[0]:21 *C 52.945 85.680 +*N mux_tree_tapbuf_size10_2_sram[0]:22 *C 52.900 85.635 +*N mux_tree_tapbuf_size10_2_sram[0]:23 *C 52.900 83.345 +*N mux_tree_tapbuf_size10_2_sram[0]:24 *C 52.945 83.300 +*N mux_tree_tapbuf_size10_2_sram[0]:25 *C 53.513 83.300 + +*CAP +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_1\/mux_l1_in_1_:S 1e-06 +2 mux_right_ipin_1\/mux_l1_in_0_:S 1e-06 +3 mux_right_ipin_1\/mux_l1_in_2_:S 1e-06 +4 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_2_sram[0]:5 3.269857e-05 +6 mux_tree_tapbuf_size10_2_sram[0]:6 0.0001610558 +7 mux_tree_tapbuf_size10_2_sram[0]:7 0.0001283572 +8 mux_tree_tapbuf_size10_2_sram[0]:8 0.0001926321 +9 mux_tree_tapbuf_size10_2_sram[0]:9 0.0001926321 +10 mux_tree_tapbuf_size10_2_sram[0]:10 0.0001573348 +11 mux_tree_tapbuf_size10_2_sram[0]:11 0.0003498049 +12 mux_tree_tapbuf_size10_2_sram[0]:12 0.0001625059 +13 mux_tree_tapbuf_size10_2_sram[0]:13 0.0002994061 +14 mux_tree_tapbuf_size10_2_sram[0]:14 0.000179548 +15 mux_tree_tapbuf_size10_2_sram[0]:15 0.0001375492 +16 mux_tree_tapbuf_size10_2_sram[0]:16 0.0006418398 +17 mux_tree_tapbuf_size10_2_sram[0]:17 0.0003091025 +18 mux_tree_tapbuf_size10_2_sram[0]:18 0.0002387234 +19 mux_tree_tapbuf_size10_2_sram[0]:19 5.221621e-05 +20 mux_tree_tapbuf_size10_2_sram[0]:20 7.201853e-05 +21 mux_tree_tapbuf_size10_2_sram[0]:21 0.0002851346 +22 mux_tree_tapbuf_size10_2_sram[0]:22 0.0001516656 +23 mux_tree_tapbuf_size10_2_sram[0]:23 0.0001516656 +24 mux_tree_tapbuf_size10_2_sram[0]:24 7.819973e-05 +25 mux_tree_tapbuf_size10_2_sram[0]:25 7.819973e-05 +26 mux_tree_tapbuf_size10_2_sram[0]:12 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.416697e-05 +27 mux_tree_tapbuf_size10_2_sram[0]:11 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.416697e-05 + +*RES +0 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_2_sram[0]:25 0.152 +1 mux_tree_tapbuf_size10_2_sram[0]:21 mux_tree_tapbuf_size10_2_sram[0]:20 0.0002265625 +2 mux_tree_tapbuf_size10_2_sram[0]:21 mux_tree_tapbuf_size10_2_sram[0]:18 0.002383929 +3 mux_tree_tapbuf_size10_2_sram[0]:22 mux_tree_tapbuf_size10_2_sram[0]:21 0.0045 +4 mux_tree_tapbuf_size10_2_sram[0]:24 mux_tree_tapbuf_size10_2_sram[0]:23 0.0045 +5 mux_tree_tapbuf_size10_2_sram[0]:23 mux_tree_tapbuf_size10_2_sram[0]:22 0.002044643 +6 mux_tree_tapbuf_size10_2_sram[0]:25 mux_tree_tapbuf_size10_2_sram[0]:24 0.0005066964 +7 mux_tree_tapbuf_size10_2_sram[0]:5 mem_right_ipin_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size10_2_sram[0]:7 mux_tree_tapbuf_size10_2_sram[0]:6 0.001276786 +9 mux_tree_tapbuf_size10_2_sram[0]:8 mux_tree_tapbuf_size10_2_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size10_2_sram[0]:10 mux_tree_tapbuf_size10_2_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size10_2_sram[0]:9 mux_tree_tapbuf_size10_2_sram[0]:8 0.002348214 +12 mux_tree_tapbuf_size10_2_sram[0]:15 mux_tree_tapbuf_size10_2_sram[0]:14 0.001691964 +13 mux_tree_tapbuf_size10_2_sram[0]:16 mux_tree_tapbuf_size10_2_sram[0]:15 0.0045 +14 mux_tree_tapbuf_size10_2_sram[0]:16 mux_tree_tapbuf_size10_2_sram[0]:13 0.004209822 +15 mux_tree_tapbuf_size10_2_sram[0]:14 mux_right_ipin_1\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size10_2_sram[0]:12 mux_tree_tapbuf_size10_2_sram[0]:11 0.002513393 +17 mux_tree_tapbuf_size10_2_sram[0]:13 mux_tree_tapbuf_size10_2_sram[0]:12 0.0045 +18 mux_tree_tapbuf_size10_2_sram[0]:19 mux_right_ipin_1\/mux_l1_in_1_:S 0.152 +19 mux_tree_tapbuf_size10_2_sram[0]:11 mux_right_ipin_1\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size10_2_sram[0]:11 mux_tree_tapbuf_size10_2_sram[0]:10 0.001513393 +21 mux_tree_tapbuf_size10_2_sram[0]:18 mux_tree_tapbuf_size10_2_sram[0]:17 0.0045 +22 mux_tree_tapbuf_size10_2_sram[0]:17 mux_tree_tapbuf_size10_2_sram[0]:16 0.004816964 +23 mux_tree_tapbuf_size10_2_sram[0]:20 mux_tree_tapbuf_size10_2_sram[0]:19 0.0001511628 +24 mux_tree_tapbuf_size10_2_sram[0]:6 mux_tree_tapbuf_size10_2_sram[0]:5 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[1] 0.004686646 //LENGTH 38.420 LUMPCC 0.0006974941 DR + +*CONN +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.945 50.320 +*I mux_right_ipin_5\/mux_l2_in_2_:S I *L 0.00357 *C 64.280 52.700 +*I mux_right_ipin_5\/mux_l2_in_1_:S I *L 0.00357 *C 60.160 58.190 +*I mux_right_ipin_5\/mux_l2_in_0_:S I *L 0.00357 *C 54.180 61.200 +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 60.435 66.300 +*I mux_right_ipin_5\/mux_l2_in_3_:S I *L 0.00357 *C 65.680 55.760 +*N mux_tree_tapbuf_size10_4_sram[1]:6 *C 65.642 55.760 +*N mux_tree_tapbuf_size10_4_sram[1]:7 *C 60.435 66.300 +*N mux_tree_tapbuf_size10_4_sram[1]:8 *C 60.720 66.300 +*N mux_tree_tapbuf_size10_4_sram[1]:9 *C 60.720 66.255 +*N mux_tree_tapbuf_size10_4_sram[1]:10 *C 54.143 61.200 +*N mux_tree_tapbuf_size10_4_sram[1]:11 *C 53.820 61.200 +*N mux_tree_tapbuf_size10_4_sram[1]:12 *C 53.820 60.860 +*N mux_tree_tapbuf_size10_4_sram[1]:13 *C 55.615 60.860 +*N mux_tree_tapbuf_size10_4_sram[1]:14 *C 55.660 60.815 +*N mux_tree_tapbuf_size10_4_sram[1]:15 *C 55.660 58.865 +*N mux_tree_tapbuf_size10_4_sram[1]:16 *C 55.705 58.820 +*N mux_tree_tapbuf_size10_4_sram[1]:17 *C 60.260 58.820 +*N mux_tree_tapbuf_size10_4_sram[1]:18 *C 60.230 58.550 +*N mux_tree_tapbuf_size10_4_sram[1]:19 *C 60.190 58.410 +*N mux_tree_tapbuf_size10_4_sram[1]:20 *C 60.160 58.190 +*N mux_tree_tapbuf_size10_4_sram[1]:21 *C 60.160 57.800 +*N mux_tree_tapbuf_size10_4_sram[1]:22 *C 60.675 57.800 +*N mux_tree_tapbuf_size10_4_sram[1]:23 *C 60.720 57.800 +*N mux_tree_tapbuf_size10_4_sram[1]:24 *C 60.720 55.805 +*N mux_tree_tapbuf_size10_4_sram[1]:25 *C 60.765 55.760 +*N mux_tree_tapbuf_size10_4_sram[1]:26 *C 61.640 55.760 +*N mux_tree_tapbuf_size10_4_sram[1]:27 *C 61.640 55.715 +*N mux_tree_tapbuf_size10_4_sram[1]:28 *C 64.243 52.700 +*N mux_tree_tapbuf_size10_4_sram[1]:29 *C 61.685 52.700 +*N mux_tree_tapbuf_size10_4_sram[1]:30 *C 61.640 52.700 +*N mux_tree_tapbuf_size10_4_sram[1]:31 *C 61.640 50.365 +*N mux_tree_tapbuf_size10_4_sram[1]:32 *C 61.640 50.320 +*N mux_tree_tapbuf_size10_4_sram[1]:33 *C 61.945 50.320 + +*CAP +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_5\/mux_l2_in_2_:S 1e-06 +2 mux_right_ipin_5\/mux_l2_in_1_:S 1e-06 +3 mux_right_ipin_5\/mux_l2_in_0_:S 1e-06 +4 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_right_ipin_5\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_4_sram[1]:6 0.0002675621 +7 mux_tree_tapbuf_size10_4_sram[1]:7 4.804197e-05 +8 mux_tree_tapbuf_size10_4_sram[1]:8 5.193987e-05 +9 mux_tree_tapbuf_size10_4_sram[1]:9 0.00036267 +10 mux_tree_tapbuf_size10_4_sram[1]:10 4.621698e-05 +11 mux_tree_tapbuf_size10_4_sram[1]:11 7.053035e-05 +12 mux_tree_tapbuf_size10_4_sram[1]:12 0.00013188 +13 mux_tree_tapbuf_size10_4_sram[1]:13 0.0001075667 +14 mux_tree_tapbuf_size10_4_sram[1]:14 0.0001225543 +15 mux_tree_tapbuf_size10_4_sram[1]:15 0.0001225543 +16 mux_tree_tapbuf_size10_4_sram[1]:16 0.0002257201 +17 mux_tree_tapbuf_size10_4_sram[1]:17 0.0002506521 +18 mux_tree_tapbuf_size10_4_sram[1]:18 3.102613e-05 +19 mux_tree_tapbuf_size10_4_sram[1]:19 1.9688e-05 +20 mux_tree_tapbuf_size10_4_sram[1]:20 7.49606e-05 +21 mux_tree_tapbuf_size10_4_sram[1]:21 7.429995e-05 +22 mux_tree_tapbuf_size10_4_sram[1]:22 5.07367e-05 +23 mux_tree_tapbuf_size10_4_sram[1]:23 0.0004961665 +24 mux_tree_tapbuf_size10_4_sram[1]:24 0.000102727 +25 mux_tree_tapbuf_size10_4_sram[1]:25 6.605835e-05 +26 mux_tree_tapbuf_size10_4_sram[1]:26 0.0003743018 +27 mux_tree_tapbuf_size10_4_sram[1]:27 0.0001151963 +28 mux_tree_tapbuf_size10_4_sram[1]:28 0.0001758819 +29 mux_tree_tapbuf_size10_4_sram[1]:29 0.0001758819 +30 mux_tree_tapbuf_size10_4_sram[1]:30 0.0002269375 +31 mux_tree_tapbuf_size10_4_sram[1]:31 8.372327e-05 +32 mux_tree_tapbuf_size10_4_sram[1]:32 5.581117e-05 +33 mux_tree_tapbuf_size10_4_sram[1]:33 5.186586e-05 +34 mux_tree_tapbuf_size10_4_sram[1]:30 mux_tree_tapbuf_size8_7_sram[0]:13 8.733908e-05 +35 mux_tree_tapbuf_size10_4_sram[1]:30 mux_tree_tapbuf_size8_7_sram[0]:12 7.058181e-05 +36 mux_tree_tapbuf_size10_4_sram[1]:31 mux_tree_tapbuf_size8_7_sram[0]:13 7.058181e-05 +37 mux_tree_tapbuf_size10_4_sram[1]:24 mux_tree_tapbuf_size8_7_sram[0]:13 7.42871e-06 +38 mux_tree_tapbuf_size10_4_sram[1]:27 mux_tree_tapbuf_size8_7_sram[0]:12 8.733908e-05 +39 mux_tree_tapbuf_size10_4_sram[1]:9 mux_tree_tapbuf_size8_7_sram[0]:12 6.0568e-05 +40 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size8_7_sram[0]:13 6.0568e-05 +41 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size8_7_sram[0]:12 7.42871e-06 +42 mux_tree_tapbuf_size10_4_sram[1]:16 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.650708e-05 +43 mux_tree_tapbuf_size10_4_sram[1]:17 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.650708e-05 +44 mux_tree_tapbuf_size10_4_sram[1]:20 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.022874e-06 +45 mux_tree_tapbuf_size10_4_sram[1]:9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.375332e-05 +46 mux_tree_tapbuf_size10_4_sram[1]:22 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.721926e-06 +47 mux_tree_tapbuf_size10_4_sram[1]:23 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.375332e-05 +48 mux_tree_tapbuf_size10_4_sram[1]:16 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.462154e-06 +49 mux_tree_tapbuf_size10_4_sram[1]:17 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.462154e-06 +50 mux_tree_tapbuf_size10_4_sram[1]:21 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.721926e-06 +51 mux_tree_tapbuf_size10_4_sram[1]:19 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.621213e-07 +52 mux_tree_tapbuf_size10_4_sram[1]:18 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.384995e-06 + +*RES +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_4_sram[1]:33 0.152 +1 mux_tree_tapbuf_size10_4_sram[1]:28 mux_right_ipin_5\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_4_sram[1]:29 mux_tree_tapbuf_size10_4_sram[1]:28 0.002283482 +3 mux_tree_tapbuf_size10_4_sram[1]:30 mux_tree_tapbuf_size10_4_sram[1]:29 0.0045 +4 mux_tree_tapbuf_size10_4_sram[1]:30 mux_tree_tapbuf_size10_4_sram[1]:27 0.002691965 +5 mux_tree_tapbuf_size10_4_sram[1]:32 mux_tree_tapbuf_size10_4_sram[1]:31 0.0045 +6 mux_tree_tapbuf_size10_4_sram[1]:31 mux_tree_tapbuf_size10_4_sram[1]:30 0.002084821 +7 mux_tree_tapbuf_size10_4_sram[1]:33 mux_tree_tapbuf_size10_4_sram[1]:32 0.0001657609 +8 mux_tree_tapbuf_size10_4_sram[1]:20 mux_right_ipin_5\/mux_l2_in_1_:S 0.152 +9 mux_tree_tapbuf_size10_4_sram[1]:20 mux_tree_tapbuf_size10_4_sram[1]:19 0.0001964286 +10 mux_tree_tapbuf_size10_4_sram[1]:20 mux_tree_tapbuf_size10_4_sram[1]:18 1.881721e-05 +11 mux_tree_tapbuf_size10_4_sram[1]:25 mux_tree_tapbuf_size10_4_sram[1]:24 0.0045 +12 mux_tree_tapbuf_size10_4_sram[1]:24 mux_tree_tapbuf_size10_4_sram[1]:23 0.00178125 +13 mux_tree_tapbuf_size10_4_sram[1]:6 mux_right_ipin_5\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size10_4_sram[1]:26 mux_tree_tapbuf_size10_4_sram[1]:25 0.0007812501 +15 mux_tree_tapbuf_size10_4_sram[1]:26 mux_tree_tapbuf_size10_4_sram[1]:6 0.003573661 +16 mux_tree_tapbuf_size10_4_sram[1]:27 mux_tree_tapbuf_size10_4_sram[1]:26 0.0045 +17 mux_tree_tapbuf_size10_4_sram[1]:8 mux_tree_tapbuf_size10_4_sram[1]:7 0.0001548913 +18 mux_tree_tapbuf_size10_4_sram[1]:9 mux_tree_tapbuf_size10_4_sram[1]:8 0.0045 +19 mux_tree_tapbuf_size10_4_sram[1]:7 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +20 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:21 0.0004598215 +21 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:22 0.0045 +22 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:9 0.007549107 +23 mux_tree_tapbuf_size10_4_sram[1]:10 mux_right_ipin_5\/mux_l2_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_4_sram[1]:13 mux_tree_tapbuf_size10_4_sram[1]:12 0.001602679 +25 mux_tree_tapbuf_size10_4_sram[1]:14 mux_tree_tapbuf_size10_4_sram[1]:13 0.0045 +26 mux_tree_tapbuf_size10_4_sram[1]:16 mux_tree_tapbuf_size10_4_sram[1]:15 0.0045 +27 mux_tree_tapbuf_size10_4_sram[1]:15 mux_tree_tapbuf_size10_4_sram[1]:14 0.001741072 +28 mux_tree_tapbuf_size10_4_sram[1]:12 mux_tree_tapbuf_size10_4_sram[1]:11 0.0003035715 +29 mux_tree_tapbuf_size10_4_sram[1]:11 mux_tree_tapbuf_size10_4_sram[1]:10 0.0002879465 +30 mux_tree_tapbuf_size10_4_sram[1]:17 mux_tree_tapbuf_size10_4_sram[1]:16 0.004066965 +31 mux_tree_tapbuf_size10_4_sram[1]:21 mux_tree_tapbuf_size10_4_sram[1]:20 0.0003482143 +32 mux_tree_tapbuf_size10_4_sram[1]:18 mux_tree_tapbuf_size10_4_sram[1]:17 0.0002410715 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[2] 0.004985315 //LENGTH 33.035 LUMPCC 0.001258924 DR + +*CONN +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 65.495 19.720 +*I mux_right_ipin_13\/mux_l3_in_1_:S I *L 0.00357 *C 49.320 19.720 +*I mux_right_ipin_13\/mux_l3_in_0_:S I *L 0.00357 *C 43.600 18.360 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 40.190 22.780 +*N mux_tree_tapbuf_size10_8_sram[2]:4 *C 40.190 22.780 +*N mux_tree_tapbuf_size10_8_sram[2]:5 *C 41.815 22.780 +*N mux_tree_tapbuf_size10_8_sram[2]:6 *C 41.860 22.735 +*N mux_tree_tapbuf_size10_8_sram[2]:7 *C 41.860 18.405 +*N mux_tree_tapbuf_size10_8_sram[2]:8 *C 41.905 18.360 +*N mux_tree_tapbuf_size10_8_sram[2]:9 *C 43.600 18.360 +*N mux_tree_tapbuf_size10_8_sram[2]:10 *C 49.175 18.360 +*N mux_tree_tapbuf_size10_8_sram[2]:11 *C 49.220 18.405 +*N mux_tree_tapbuf_size10_8_sram[2]:12 *C 49.220 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:13 *C 49.220 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:14 *C 49.680 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:15 *C 49.688 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:16 *C 65.312 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:17 *C 65.320 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:18 *C 65.320 19.720 +*N mux_tree_tapbuf_size10_8_sram[2]:19 *C 65.495 19.720 + +*CAP +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_13\/mux_l3_in_1_:S 1e-06 +2 mux_right_ipin_13\/mux_l3_in_0_:S 1e-06 +3 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_8_sram[2]:4 0.0001528727 +5 mux_tree_tapbuf_size10_8_sram[2]:5 0.0001188567 +6 mux_tree_tapbuf_size10_8_sram[2]:6 0.0002745079 +7 mux_tree_tapbuf_size10_8_sram[2]:7 0.0002745079 +8 mux_tree_tapbuf_size10_8_sram[2]:8 0.0001092842 +9 mux_tree_tapbuf_size10_8_sram[2]:9 0.0004323295 +10 mux_tree_tapbuf_size10_8_sram[2]:10 0.0002932837 +11 mux_tree_tapbuf_size10_8_sram[2]:11 9.218502e-05 +12 mux_tree_tapbuf_size10_8_sram[2]:12 3.08794e-05 +13 mux_tree_tapbuf_size10_8_sram[2]:13 0.0001291204 +14 mux_tree_tapbuf_size10_8_sram[2]:14 7.25494e-05 +15 mux_tree_tapbuf_size10_8_sram[2]:15 0.0008023357 +16 mux_tree_tapbuf_size10_8_sram[2]:16 0.0008023357 +17 mux_tree_tapbuf_size10_8_sram[2]:17 3.376364e-05 +18 mux_tree_tapbuf_size10_8_sram[2]:18 5.448688e-05 +19 mux_tree_tapbuf_size10_8_sram[2]:19 4.909126e-05 +20 mux_tree_tapbuf_size10_8_sram[2]:6 prog_clk[0]:220 3.568648e-08 +21 mux_tree_tapbuf_size10_8_sram[2]:7 prog_clk[0]:216 3.568648e-08 +22 mux_tree_tapbuf_size10_8_sram[2]:15 prog_clk[0]:212 0.0002575877 +23 mux_tree_tapbuf_size10_8_sram[2]:15 prog_clk[0]:213 0.0002281929 +24 mux_tree_tapbuf_size10_8_sram[2]:16 prog_clk[0]:207 0.0002575877 +25 mux_tree_tapbuf_size10_8_sram[2]:16 prog_clk[0]:212 0.0002281929 +26 mux_tree_tapbuf_size10_8_sram[2]:8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.132476e-05 +27 mux_tree_tapbuf_size10_8_sram[2]:9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001123211 +28 mux_tree_tapbuf_size10_8_sram[2]:9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.132476e-05 +29 mux_tree_tapbuf_size10_8_sram[2]:10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001123211 + +*RES +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_8_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_8_sram[2]:4 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size10_8_sram[2]:5 mux_tree_tapbuf_size10_8_sram[2]:4 0.001450893 +3 mux_tree_tapbuf_size10_8_sram[2]:6 mux_tree_tapbuf_size10_8_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size10_8_sram[2]:8 mux_tree_tapbuf_size10_8_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size10_8_sram[2]:7 mux_tree_tapbuf_size10_8_sram[2]:6 0.003866071 +6 mux_tree_tapbuf_size10_8_sram[2]:9 mux_right_ipin_13\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_8_sram[2]:9 mux_tree_tapbuf_size10_8_sram[2]:8 0.001513393 +8 mux_tree_tapbuf_size10_8_sram[2]:10 mux_tree_tapbuf_size10_8_sram[2]:9 0.004977678 +9 mux_tree_tapbuf_size10_8_sram[2]:11 mux_tree_tapbuf_size10_8_sram[2]:10 0.0045 +10 mux_tree_tapbuf_size10_8_sram[2]:14 mux_tree_tapbuf_size10_8_sram[2]:13 0.0004107143 +11 mux_tree_tapbuf_size10_8_sram[2]:15 mux_tree_tapbuf_size10_8_sram[2]:14 0.00341 +12 mux_tree_tapbuf_size10_8_sram[2]:17 mux_tree_tapbuf_size10_8_sram[2]:16 0.00341 +13 mux_tree_tapbuf_size10_8_sram[2]:16 mux_tree_tapbuf_size10_8_sram[2]:15 0.002447917 +14 mux_tree_tapbuf_size10_8_sram[2]:18 mux_tree_tapbuf_size10_8_sram[2]:17 0.0045 +15 mux_tree_tapbuf_size10_8_sram[2]:19 mux_tree_tapbuf_size10_8_sram[2]:18 9.51087e-05 +16 mux_tree_tapbuf_size10_8_sram[2]:12 mux_right_ipin_13\/mux_l3_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_8_sram[2]:13 mux_tree_tapbuf_size10_8_sram[2]:12 0.0045 +18 mux_tree_tapbuf_size10_8_sram[2]:13 mux_tree_tapbuf_size10_8_sram[2]:11 0.001174107 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_7_ccff_tail[0] 0.0004677997 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_12\/FTB_8__47:X O *L 0 *C 28.755 22.440 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 28.235 20.740 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 *C 28.235 20.740 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 *C 28.520 20.740 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 *C 28.520 20.785 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 *C 28.520 22.395 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 *C 28.520 22.440 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 *C 28.755 22.440 + +*CAP +0 mem_right_ipin_12\/FTB_8__47:X 1e-06 +1 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 5.874382e-05 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 6.543931e-05 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0001141703 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0001141703 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 5.816413e-05 +7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 5.511195e-05 + +*RES +0 mem_right_ipin_12\/FTB_8__47:X mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[0] 0.003656699 //LENGTH 31.865 LUMPCC 0.0002491039 DR + +*CONN +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 10.425 82.620 +*I mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 9.835 60.860 +*I mux_right_ipin_3\/mux_l1_in_0_:S I *L 0.00357 *C 16.000 58.480 +*N mux_tree_tapbuf_size8_1_sram[0]:3 *C 15.963 58.480 +*N mux_tree_tapbuf_size8_1_sram[0]:4 *C 12.925 58.480 +*N mux_tree_tapbuf_size8_1_sram[0]:5 *C 12.880 58.525 +*N mux_tree_tapbuf_size8_1_sram[0]:6 *C 12.880 60.815 +*N mux_tree_tapbuf_size8_1_sram[0]:7 *C 12.835 60.860 +*N mux_tree_tapbuf_size8_1_sram[0]:8 *C 9.835 60.860 +*N mux_tree_tapbuf_size8_1_sram[0]:9 *C 10.165 60.860 +*N mux_tree_tapbuf_size8_1_sram[0]:10 *C 10.120 60.905 +*N mux_tree_tapbuf_size8_1_sram[0]:11 *C 10.120 82.575 +*N mux_tree_tapbuf_size8_1_sram[0]:12 *C 10.120 82.620 +*N mux_tree_tapbuf_size8_1_sram[0]:13 *C 10.425 82.620 + +*CAP +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_3\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001607259 +4 mux_tree_tapbuf_size8_1_sram[0]:4 0.0001607259 +5 mux_tree_tapbuf_size8_1_sram[0]:5 0.0001414201 +6 mux_tree_tapbuf_size8_1_sram[0]:6 0.0001414201 +7 mux_tree_tapbuf_size8_1_sram[0]:7 0.0001848933 +8 mux_tree_tapbuf_size8_1_sram[0]:8 4.664812e-05 +9 mux_tree_tapbuf_size8_1_sram[0]:9 0.0002045153 +10 mux_tree_tapbuf_size8_1_sram[0]:10 0.001126855 +11 mux_tree_tapbuf_size8_1_sram[0]:11 0.001126855 +12 mux_tree_tapbuf_size8_1_sram[0]:12 5.712914e-05 +13 mux_tree_tapbuf_size8_1_sram[0]:13 5.340816e-05 +14 mux_tree_tapbuf_size8_1_sram[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001245519 +15 mux_tree_tapbuf_size8_1_sram[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001245519 + +*RES +0 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_1_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_1_sram[0]:8 mem_right_ipin_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size8_1_sram[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 0.0045 +3 mux_tree_tapbuf_size8_1_sram[0]:6 mux_tree_tapbuf_size8_1_sram[0]:5 0.002044643 +4 mux_tree_tapbuf_size8_1_sram[0]:4 mux_tree_tapbuf_size8_1_sram[0]:3 0.002712054 +5 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_1_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size8_1_sram[0]:3 mux_right_ipin_3\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:8 0.0001793478 +8 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:7 0.002383929 +9 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_1_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_1_sram[0]:10 0.01934822 +12 mux_tree_tapbuf_size8_1_sram[0]:13 mux_tree_tapbuf_size8_1_sram[0]:12 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[2] 0.003551753 //LENGTH 28.085 LUMPCC 0.000513915 DR + +*CONN +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 79.425 96.900 +*I mux_right_ipin_7\/mux_l3_in_1_:S I *L 0.00357 *C 69.560 90.440 +*I mux_right_ipin_7\/mux_l3_in_0_:S I *L 0.00357 *C 64.300 90.440 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 70.555 98.940 +*N mux_tree_tapbuf_size8_3_sram[2]:4 *C 70.517 98.940 +*N mux_tree_tapbuf_size8_3_sram[2]:5 *C 69.460 98.940 +*N mux_tree_tapbuf_size8_3_sram[2]:6 *C 64.338 90.440 +*N mux_tree_tapbuf_size8_3_sram[2]:7 *C 69.472 90.440 +*N mux_tree_tapbuf_size8_3_sram[2]:8 *C 69.460 90.485 +*N mux_tree_tapbuf_size8_3_sram[2]:9 *C 69.460 98.555 +*N mux_tree_tapbuf_size8_3_sram[2]:10 *C 69.460 98.600 +*N mux_tree_tapbuf_size8_3_sram[2]:11 *C 79.075 98.600 +*N mux_tree_tapbuf_size8_3_sram[2]:12 *C 79.120 98.555 +*N mux_tree_tapbuf_size8_3_sram[2]:13 *C 79.120 96.945 +*N mux_tree_tapbuf_size8_3_sram[2]:14 *C 79.120 96.900 +*N mux_tree_tapbuf_size8_3_sram[2]:15 *C 79.425 96.900 + +*CAP +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_7\/mux_l3_in_1_:S 1e-06 +2 mux_right_ipin_7\/mux_l3_in_0_:S 1e-06 +3 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_3_sram[2]:4 0.0001057899 +5 mux_tree_tapbuf_size8_3_sram[2]:5 0.0001341333 +6 mux_tree_tapbuf_size8_3_sram[2]:6 0.0002929458 +7 mux_tree_tapbuf_size8_3_sram[2]:7 0.0002929458 +8 mux_tree_tapbuf_size8_3_sram[2]:8 0.0004248209 +9 mux_tree_tapbuf_size8_3_sram[2]:9 0.0004248209 +10 mux_tree_tapbuf_size8_3_sram[2]:10 0.0005484161 +11 mux_tree_tapbuf_size8_3_sram[2]:11 0.0005200726 +12 mux_tree_tapbuf_size8_3_sram[2]:12 9.85533e-05 +13 mux_tree_tapbuf_size8_3_sram[2]:13 9.85533e-05 +14 mux_tree_tapbuf_size8_3_sram[2]:14 4.843104e-05 +15 mux_tree_tapbuf_size8_3_sram[2]:15 4.435471e-05 +16 mux_tree_tapbuf_size8_3_sram[2]:8 mux_tree_tapbuf_size8_3_sram[3]:8 5.358138e-06 +17 mux_tree_tapbuf_size8_3_sram[2]:10 mux_tree_tapbuf_size8_3_sram[3]:10 0.0001447427 +18 mux_tree_tapbuf_size8_3_sram[2]:9 mux_tree_tapbuf_size8_3_sram[3]:9 5.358138e-06 +19 mux_tree_tapbuf_size8_3_sram[2]:11 mux_tree_tapbuf_size8_3_sram[3]:11 0.0001447427 +20 mux_tree_tapbuf_size8_3_sram[2]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0001025891 +21 mux_tree_tapbuf_size8_3_sram[2]:8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 4.26751e-06 +22 mux_tree_tapbuf_size8_3_sram[2]:9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 4.26751e-06 +23 mux_tree_tapbuf_size8_3_sram[2]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001025891 + +*RES +0 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_3_sram[2]:15 0.152 +1 mux_tree_tapbuf_size8_3_sram[2]:7 mux_right_ipin_7\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_3_sram[2]:7 mux_tree_tapbuf_size8_3_sram[2]:6 0.004584822 +3 mux_tree_tapbuf_size8_3_sram[2]:8 mux_tree_tapbuf_size8_3_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size8_3_sram[2]:10 mux_tree_tapbuf_size8_3_sram[2]:9 0.0045 +5 mux_tree_tapbuf_size8_3_sram[2]:10 mux_tree_tapbuf_size8_3_sram[2]:5 0.0003035715 +6 mux_tree_tapbuf_size8_3_sram[2]:9 mux_tree_tapbuf_size8_3_sram[2]:8 0.007205358 +7 mux_tree_tapbuf_size8_3_sram[2]:4 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size8_3_sram[2]:6 mux_right_ipin_7\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_3_sram[2]:11 mux_tree_tapbuf_size8_3_sram[2]:10 0.008584822 +10 mux_tree_tapbuf_size8_3_sram[2]:12 mux_tree_tapbuf_size8_3_sram[2]:11 0.0045 +11 mux_tree_tapbuf_size8_3_sram[2]:14 mux_tree_tapbuf_size8_3_sram[2]:13 0.0045 +12 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:12 0.0014375 +13 mux_tree_tapbuf_size8_3_sram[2]:15 mux_tree_tapbuf_size8_3_sram[2]:14 0.0001657609 +14 mux_tree_tapbuf_size8_3_sram[2]:5 mux_tree_tapbuf_size8_3_sram[2]:4 0.0009441964 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[0] 0.003201893 //LENGTH 25.375 LUMPCC 0.0005296807 DR + +*CONN +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 43.085 28.220 +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.735 39.100 +*I mux_right_ipin_14\/mux_l1_in_0_:S I *L 0.00357 *C 33.020 42.160 +*N mux_tree_tapbuf_size8_6_sram[0]:3 *C 33.058 42.160 +*N mux_tree_tapbuf_size8_6_sram[0]:4 *C 39.515 42.160 +*N mux_tree_tapbuf_size8_6_sram[0]:5 *C 39.560 42.115 +*N mux_tree_tapbuf_size8_6_sram[0]:6 *C 39.560 39.145 +*N mux_tree_tapbuf_size8_6_sram[0]:7 *C 39.560 39.100 +*N mux_tree_tapbuf_size8_6_sram[0]:8 *C 39.735 39.100 +*N mux_tree_tapbuf_size8_6_sram[0]:9 *C 40.020 39.100 +*N mux_tree_tapbuf_size8_6_sram[0]:10 *C 40.020 39.055 +*N mux_tree_tapbuf_size8_6_sram[0]:11 *C 40.020 28.265 +*N mux_tree_tapbuf_size8_6_sram[0]:12 *C 40.065 28.220 +*N mux_tree_tapbuf_size8_6_sram[0]:13 *C 43.047 28.220 + +*CAP +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_14\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_6_sram[0]:3 0.000288687 +4 mux_tree_tapbuf_size8_6_sram[0]:4 0.0002886871 +5 mux_tree_tapbuf_size8_6_sram[0]:5 0.0001866243 +6 mux_tree_tapbuf_size8_6_sram[0]:6 0.0001866243 +7 mux_tree_tapbuf_size8_6_sram[0]:7 5.458792e-05 +8 mux_tree_tapbuf_size8_6_sram[0]:8 7.027148e-05 +9 mux_tree_tapbuf_size8_6_sram[0]:9 5.348558e-05 +10 mux_tree_tapbuf_size8_6_sram[0]:10 0.0005752152 +11 mux_tree_tapbuf_size8_6_sram[0]:11 0.0005752152 +12 mux_tree_tapbuf_size8_6_sram[0]:12 0.0001949069 +13 mux_tree_tapbuf_size8_6_sram[0]:13 0.0001949069 +14 mux_tree_tapbuf_size8_6_sram[0]:6 chany_bottom_in[3]:48 7.393221e-08 +15 mux_tree_tapbuf_size8_6_sram[0]:6 chany_bottom_in[3]:55 1.150057e-07 +16 mux_tree_tapbuf_size8_6_sram[0]:4 chany_bottom_in[3]:10 4.535968e-05 +17 mux_tree_tapbuf_size8_6_sram[0]:4 chany_bottom_in[3]:44 8.949036e-05 +18 mux_tree_tapbuf_size8_6_sram[0]:5 chany_bottom_in[3]:45 7.393221e-08 +19 mux_tree_tapbuf_size8_6_sram[0]:5 chany_bottom_in[3]:48 1.150057e-07 +20 mux_tree_tapbuf_size8_6_sram[0]:3 chany_bottom_in[3]:43 8.949036e-05 +21 mux_tree_tapbuf_size8_6_sram[0]:3 chany_bottom_in[3]:44 4.535968e-05 +22 mux_tree_tapbuf_size8_6_sram[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.83498e-05 +23 mux_tree_tapbuf_size8_6_sram[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.926491e-05 +24 mux_tree_tapbuf_size8_6_sram[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.926491e-05 +25 mux_tree_tapbuf_size8_6_sram[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.83498e-05 +26 mux_tree_tapbuf_size8_6_sram[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.218666e-05 +27 mux_tree_tapbuf_size8_6_sram[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.218666e-05 + +*RES +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_6_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_6_sram[0]:7 mux_tree_tapbuf_size8_6_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size8_6_sram[0]:6 mux_tree_tapbuf_size8_6_sram[0]:5 0.002651786 +3 mux_tree_tapbuf_size8_6_sram[0]:4 mux_tree_tapbuf_size8_6_sram[0]:3 0.005765625 +4 mux_tree_tapbuf_size8_6_sram[0]:5 mux_tree_tapbuf_size8_6_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size8_6_sram[0]:3 mux_right_ipin_14\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_6_sram[0]:8 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size8_6_sram[0]:8 mux_tree_tapbuf_size8_6_sram[0]:7 9.51087e-05 +8 mux_tree_tapbuf_size8_6_sram[0]:9 mux_tree_tapbuf_size8_6_sram[0]:8 0.0001548913 +9 mux_tree_tapbuf_size8_6_sram[0]:10 mux_tree_tapbuf_size8_6_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size8_6_sram[0]:12 mux_tree_tapbuf_size8_6_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size8_6_sram[0]:11 mux_tree_tapbuf_size8_6_sram[0]:10 0.009633929 +12 mux_tree_tapbuf_size8_6_sram[0]:13 mux_tree_tapbuf_size8_6_sram[0]:12 0.002662947 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_2_ccff_tail[0] 0.001692492 //LENGTH 11.765 LUMPCC 0.0009074237 DR + +*CONN +*I mem_right_ipin_6\/FTB_12__51:X O *L 0 *C 45.315 72.760 +*I mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.540 80.580 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 *C 47.540 80.580 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 *C 47.540 80.920 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 *C 46.045 80.920 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 *C 46.000 80.875 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 *C 46.000 72.805 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 *C 45.955 72.760 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 *C 45.352 72.760 + +*CAP +0 mem_right_ipin_6\/FTB_12__51:X 1e-06 +1 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 5.627242e-05 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0001457898 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.0001180097 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0001665542 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0001665542 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 6.494412e-05 +8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 6.494412e-05 +9 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 chany_top_in[2]:58 0.0002268559 +10 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 chany_top_in[2]:59 0.0002268559 +11 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 prog_clk[0]:336 6.698239e-05 +12 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 prog_clk[0]:339 0.0001374789 +13 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 prog_clk[0]:341 2.23946e-05 +14 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 prog_clk[0]:339 6.698239e-05 +15 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 prog_clk[0]:341 0.0001374789 +16 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 prog_clk[0]:344 2.23946e-05 + +*RES +0 mem_right_ipin_6\/FTB_12__51:X mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.0005379464 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.007205357 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.001334822 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mem_right_ipin_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0003035714 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001208696 //LENGTH 9.940 LUMPCC 0.0003793658 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_1_:X O *L 0 *C 74.345 49.980 +*I mux_left_ipin_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 77.915 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 77.877 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 75.485 44.540 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 75.440 44.585 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 75.440 49.935 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 75.395 49.980 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 74.383 49.980 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_1_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_0_:A0 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.859334e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.859334e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002557067 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002557067 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.936497e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.936497e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[10]:15 8.843702e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[10]:16 8.843702e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.672083e-06 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.657381e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.672083e-06 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.657381e-05 + +*RES +0 mux_left_ipin_0\/mux_l2_in_1_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_ipin_0\/mux_l3_in_0_:A0 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002136161 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004776786 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008502158 //LENGTH 6.125 LUMPCC 0.0001416921 DR + +*CONN +*I mux_right_ipin_0\/mux_l2_in_3_:X O *L 0 *C 35.595 86.360 +*I mux_right_ipin_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.030 87.720 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 32.068 87.720 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 35.835 87.720 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 35.880 87.675 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 35.880 86.405 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 35.880 86.360 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 35.595 86.360 + +*CAP +0 mux_right_ipin_0\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_0\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002074433 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002074433 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.054865e-05 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.054865e-05 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.58882e-05 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.465158e-05 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:10 2.103009e-05 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:15 4.981597e-05 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:15 2.103009e-05 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:16 4.981597e-05 + +*RES +0 mux_right_ipin_0\/mux_l2_in_3_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_0\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.003363839 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001331522 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003570727 //LENGTH 24.705 LUMPCC 0.0003859231 DR + +*CONN +*I mux_right_ipin_1\/mux_l4_in_0_:X O *L 0 *C 31.455 93.160 +*I mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.585 93.665 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 7.623 93.560 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 14.720 93.500 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 14.720 93.160 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 31.418 93.160 + +*CAP +0 mux_right_ipin_1\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004203272 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0004450414 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001171075 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00114636 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 optlc_net_132:23 0.0001019305 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 optlc_net_132:32 0.0001019305 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.103106e-05 +9 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.103106e-05 + +*RES +0 mux_right_ipin_1\/mux_l4_in_0_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.01490848 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.006337054 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008241954 //LENGTH 6.085 LUMPCC 0.0003373498 DR + +*CONN +*I mux_right_ipin_5\/mux_l1_in_2_:X O *L 0 *C 53.645 58.140 +*I mux_right_ipin_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 59.440 58.140 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 59.403 58.140 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 53.683 58.140 + +*CAP +0 mux_right_ipin_5\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_5\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002424228 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002424228 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_4_sram[0]:14 0.0001021678 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_4_sram[0]:15 0.0001021678 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_4_sram[1]:17 6.650708e-05 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_4_sram[1]:16 6.650708e-05 + +*RES +0 mux_right_ipin_5\/mux_l1_in_2_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_5\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.005107142 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001287824 //LENGTH 9.685 LUMPCC 0.0003442239 DR + +*CONN +*I mux_right_ipin_8\/mux_l1_in_2_:X O *L 0 *C 27.315 28.220 +*I mux_right_ipin_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 25.300 34.340 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 25.300 34.340 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 25.300 34.680 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 25.300 34.635 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 25.300 28.265 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 25.345 28.220 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 27.277 28.220 + +*CAP +0 mux_right_ipin_8\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_8\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.899932e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.373547e-05 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003120889 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003120889 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.734368e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.734368e-05 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[9]:37 2.478805e-05 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[9]:36 2.478805e-05 +10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[9]:35 2.450242e-05 +11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[9]:34 2.450242e-05 +12 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_5_sram[0]:11 5.086404e-05 +13 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_5_sram[0]:10 5.086404e-05 +14 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[1]:19 3.406269e-06 +15 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_5_sram[1]:20 6.855116e-05 +16 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[1]:16 3.406269e-06 +17 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_5_sram[1]:19 6.855116e-05 + +*RES +0 mux_right_ipin_8\/mux_l1_in_2_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0056875 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001465517 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_8\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00195363 //LENGTH 12.940 LUMPCC 0.0007333203 DR + +*CONN +*I mux_right_ipin_12\/mux_l1_in_1_:X O *L 0 *C 34.215 14.280 +*I mux_right_ipin_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 24.635 11.900 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 24.672 11.900 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 32.155 11.900 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 32.200 11.945 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 32.200 14.223 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 32.208 14.280 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 34.208 14.280 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 34.215 14.280 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 34.215 14.280 + +*CAP +0 mux_right_ipin_12\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_12\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003543851 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003543851 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000104226 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000104226 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001146531 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001146531 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 3.697378e-05 +9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 3.480806e-05 +10 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[1]:63 4.394237e-05 +11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[1]:60 1.1731e-05 +12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[1]:64 5.53657e-05 +13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[1]:62 4.394237e-05 +14 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[1] 5.53657e-05 +15 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[1]:61 1.1731e-05 +16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[9]:4 7.673025e-05 +17 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_top_in[9]:5 7.673025e-05 +18 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_7_sram[0]:10 1.353432e-05 +19 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_7_sram[0]:12 4.919021e-05 +20 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_7_sram[0]:13 0.0001161663 +21 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_7_sram[0]:11 1.353432e-05 +22 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_7_sram[0]:13 4.919021e-05 +23 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_7_sram[0]:14 0.0001161663 + +*RES +0 mux_right_ipin_12\/mux_l1_in_1_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003133333 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002033482 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.006680804 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_12\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005664249 //LENGTH 3.980 LUMPCC 0.0001424764 DR + +*CONN +*I mux_right_ipin_2\/mux_l1_in_0_:X O *L 0 *C 22.715 93.500 +*I mux_right_ipin_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 21.985 90.780 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 21.985 90.780 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 22.080 90.825 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 22.080 93.455 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 22.125 93.500 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 22.678 93.500 + +*CAP +0 mux_right_ipin_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.949779e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001193346 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001193346 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.689079e-05 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.689079e-05 +7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[3]:24 4.927853e-05 +8 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[3]:25 2.195966e-05 +9 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[3]:21 4.927853e-05 +10 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[3]:24 2.195966e-05 + +*RES +0 mux_right_ipin_2\/mux_l1_in_0_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002348214 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004933036 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006382459 //LENGTH 3.953 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_3\/mux_l3_in_0_:X O *L 0 *C 17.195 65.960 +*I mux_right_ipin_3\/mux_l4_in_0_:A1 I *L 0.005458 *C 15.975 64.183 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 16.010 64.600 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 16.010 64.600 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 16.018 64.600 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 17.012 64.600 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 17.020 64.657 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 17.020 65.915 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 17.020 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 17.195 65.960 + +*CAP +0 mux_right_ipin_3\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_3\/mux_l4_in_0_:A1 3.84354e-05 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.024979e-05 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.538225e-05 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.517471e-05 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.517471e-05 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.6974e-05 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.6974e-05 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 6.377415e-05 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 6.510683e-05 + +*RES +0 mux_right_ipin_3\/mux_l3_in_0_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_3\/mux_l4_in_0_:A1 0.0004352679 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.00341 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001558833 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001122768 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 9.51087e-05 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009801057 //LENGTH 7.885 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_7\/mux_l2_in_2_:X O *L 0 *C 74.695 93.500 +*I mux_right_ipin_7\/mux_l3_in_1_:A1 I *L 0.00198 *C 70.285 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 70.285 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 70.380 91.120 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 74.475 91.120 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 74.520 91.165 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 74.520 93.455 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 74.520 93.500 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 74.695 93.500 + +*CAP +0 mux_right_ipin_7\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_7\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.442281e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002748604 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002481152 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001415183 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001415183 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.92491e-05 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.842168e-05 + +*RES +0 mux_right_ipin_7\/mux_l2_in_2_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_7\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.00365625 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002044643 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.510871e-05 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035714 + +*END + +*D_NET mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005493711 //LENGTH 3.850 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_11\/mux_l1_in_0_:X O *L 0 *C 17.655 55.080 +*I mux_right_ipin_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 16.925 52.700 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 16.963 52.700 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 17.435 52.700 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 17.480 52.745 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 17.480 55.035 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 17.480 55.080 +*N mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 17.655 55.080 + +*CAP +0 mux_right_ipin_11\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_11\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.304936e-05 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.304936e-05 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001404987 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001404987 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.826333e-05 +7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.201163e-05 + +*RES +0 mux_right_ipin_11\/mux_l1_in_0_:X mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_11\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_ipin_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001787871 //LENGTH 13.040 LUMPCC 0.0006520596 DR + +*CONN +*I mux_right_ipin_14\/mux_l2_in_2_:X O *L 0 *C 41.115 42.500 +*I mux_right_ipin_14\/mux_l3_in_1_:A1 I *L 0.00198 *C 37.165 50.660 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 37.203 50.660 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 38.135 50.660 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 38.180 50.615 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 38.180 42.545 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 38.225 42.500 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 41.078 42.500 + +*CAP +0 mux_right_ipin_14\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_14\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001031041 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001031041 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003618645 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003618645 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000101937 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000101937 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chany_bottom_in[19]:30 0.0001142638 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chany_bottom_in[19]:29 0.0001142638 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_bottom_in[19]:32 2.306155e-08 +11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_bottom_in[19]:31 2.306155e-08 +12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:235 9.009467e-05 +13 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:274 8.431386e-09 +14 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:236 9.009467e-05 +15 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:277 8.431386e-09 +16 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size8_6_sram[0]:4 6.218666e-05 +17 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size8_6_sram[0]:3 6.218666e-05 +18 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 3.755266e-07 +19 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 3.755266e-07 +20 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.907771e-05 +21 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.907771e-05 + +*RES +0 mux_right_ipin_14\/mux_l2_in_2_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002546875 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.007205358 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_ipin_14\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET ropt_net_153 0.00165627 //LENGTH 12.550 LUMPCC 0.0002778304 DR + +*CONN +*I FTB_3__2:X O *L 0 *C 57.960 94.520 +*I ropt_mt_inst_752:A I *L 0.001766 *C 53.820 102.000 +*N ropt_net_153:2 *C 53.858 102.000 +*N ropt_net_153:3 *C 55.155 102.000 +*N ropt_net_153:4 *C 55.200 101.955 +*N ropt_net_153:5 *C 55.200 94.565 +*N ropt_net_153:6 *C 55.245 94.520 +*N ropt_net_153:7 *C 57.922 94.520 + +*CAP +0 FTB_3__2:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_153:2 5.689023e-05 +3 ropt_net_153:3 5.689023e-05 +4 ropt_net_153:4 0.0004660794 +5 ropt_net_153:5 0.0004660794 +6 ropt_net_153:6 0.0001652504 +7 ropt_net_153:7 0.0001652504 +8 ropt_net_153:7 chany_bottom_in[6]:17 6.112989e-05 +9 ropt_net_153:6 chany_bottom_in[6]:18 6.112989e-05 +10 ropt_net_153:5 chany_bottom_in[6]:14 8.06029e-08 +11 ropt_net_153:4 chany_bottom_in[6]:11 8.06029e-08 +12 ropt_net_153:5 ropt_net_143:4 1.683323e-05 +13 ropt_net_153:3 ropt_net_143:5 6.087149e-05 +14 ropt_net_153:4 ropt_net_143:3 1.683323e-05 +15 ropt_net_153:2 ropt_net_143:6 6.087149e-05 + +*RES +0 FTB_3__2:X ropt_net_153:7 0.152 +1 ropt_net_153:7 ropt_net_153:6 0.002390625 +2 ropt_net_153:6 ropt_net_153:5 0.0045 +3 ropt_net_153:5 ropt_net_153:4 0.006598215 +4 ropt_net_153:3 ropt_net_153:2 0.001158482 +5 ropt_net_153:4 ropt_net_153:3 0.0045 +6 ropt_net_153:2 ropt_mt_inst_752:A 0.152 + +*END + +*D_NET chany_top_out[9] 0.001495037 //LENGTH 10.480 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 59.535 104.380 +*P chany_top_out[9] O *L 0.7423 *C 55.660 107.510 +*N chany_top_out[9]:2 *C 55.660 107.145 +*N chany_top_out[9]:3 *C 55.705 107.100 +*N chany_top_out[9]:4 *C 60.675 107.100 +*N chany_top_out[9]:5 *C 60.720 107.055 +*N chany_top_out[9]:6 *C 60.720 104.425 +*N chany_top_out[9]:7 *C 60.675 104.380 +*N chany_top_out[9]:8 *C 59.573 104.380 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 chany_top_out[9] 4.156496e-05 +2 chany_top_out[9]:2 4.156496e-05 +3 chany_top_out[9]:3 0.0003966539 +4 chany_top_out[9]:4 0.0003966539 +5 chany_top_out[9]:5 0.0002000342 +6 chany_top_out[9]:6 0.0002000342 +7 chany_top_out[9]:7 0.0001087654 +8 chany_top_out[9]:8 0.0001087654 + +*RES +0 ropt_mt_inst_742:X chany_top_out[9]:8 0.152 +1 chany_top_out[9]:3 chany_top_out[9]:2 0.0045 +2 chany_top_out[9]:2 chany_top_out[9] 0.0003258929 +3 chany_top_out[9]:4 chany_top_out[9]:3 0.0044375 +4 chany_top_out[9]:5 chany_top_out[9]:4 0.0045 +5 chany_top_out[9]:7 chany_top_out[9]:6 0.0045 +6 chany_top_out[9]:6 chany_top_out[9]:5 0.002348214 +7 chany_top_out[9]:8 chany_top_out[9]:7 0.000984375 + +*END + +*D_NET ropt_net_178 0.001525698 //LENGTH 11.295 LUMPCC 0.0001418582 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 25.495 6.120 +*I ropt_mt_inst_788:A I *L 0.001767 *C 23.000 4.080 +*N ropt_net_178:2 *C 23.038 4.080 +*N ropt_net_178:3 *C 24.335 4.080 +*N ropt_net_178:4 *C 24.380 4.125 +*N ropt_net_178:5 *C 24.380 4.703 +*N ropt_net_178:6 *C 24.388 4.760 +*N ropt_net_178:7 *C 28.053 4.760 +*N ropt_net_178:8 *C 28.060 4.817 +*N ropt_net_178:9 *C 28.060 6.075 +*N ropt_net_178:10 *C 28.015 6.120 +*N ropt_net_178:11 *C 25.533 6.120 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_178:2 0.0001140825 +3 ropt_net_178:3 0.0001140825 +4 ropt_net_178:4 6.294682e-05 +5 ropt_net_178:5 6.294682e-05 +6 ropt_net_178:6 0.0002141005 +7 ropt_net_178:7 0.0002141005 +8 ropt_net_178:8 0.0001002988 +9 ropt_net_178:9 0.0001002988 +10 ropt_net_178:10 0.0001994912 +11 ropt_net_178:11 0.0001994912 +12 ropt_net_178:6 ropt_net_170:6 5.576348e-05 +13 ropt_net_178:8 ropt_net_170:8 8.915006e-06 +14 ropt_net_178:7 ropt_net_170:7 5.576348e-05 +15 ropt_net_178:10 ropt_net_170:2 6.250586e-06 +16 ropt_net_178:9 ropt_net_170:9 8.915006e-06 +17 ropt_net_178:11 ropt_net_170:3 6.250586e-06 + +*RES +0 ropt_mt_inst_748:X ropt_net_178:11 0.152 +1 ropt_net_178:2 ropt_mt_inst_788:A 0.152 +2 ropt_net_178:3 ropt_net_178:2 0.001158482 +3 ropt_net_178:4 ropt_net_178:3 0.0045 +4 ropt_net_178:5 ropt_net_178:4 0.000515625 +5 ropt_net_178:6 ropt_net_178:5 0.00341 +6 ropt_net_178:8 ropt_net_178:7 0.00341 +7 ropt_net_178:7 ropt_net_178:6 0.0005741833 +8 ropt_net_178:10 ropt_net_178:9 0.0045 +9 ropt_net_178:9 ropt_net_178:8 0.001122768 +10 ropt_net_178:11 ropt_net_178:10 0.002216518 + +*END + +*D_NET chany_top_out[19] 0.001249586 //LENGTH 8.070 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 54.935 105.400 +*P chany_top_out[19] O *L 0.7423 *C 50.140 107.510 +*N chany_top_out[19]:2 *C 50.140 106.818 +*N chany_top_out[19]:3 *C 50.148 106.760 +*N chany_top_out[19]:4 *C 53.812 106.760 +*N chany_top_out[19]:5 *C 53.820 106.703 +*N chany_top_out[19]:6 *C 53.820 105.445 +*N chany_top_out[19]:7 *C 53.865 105.400 +*N chany_top_out[19]:8 *C 54.898 105.400 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 chany_top_out[19] 6.294135e-05 +2 chany_top_out[19]:2 6.294135e-05 +3 chany_top_out[19]:3 0.0003200433 +4 chany_top_out[19]:4 0.0003200433 +5 chany_top_out[19]:5 0.0001236137 +6 chany_top_out[19]:6 0.0001236137 +7 chany_top_out[19]:7 0.0001176945 +8 chany_top_out[19]:8 0.0001176945 + +*RES +0 ropt_mt_inst_782:X chany_top_out[19]:8 0.152 +1 chany_top_out[19]:8 chany_top_out[19]:7 0.0009218751 +2 chany_top_out[19]:7 chany_top_out[19]:6 0.0045 +3 chany_top_out[19]:6 chany_top_out[19]:5 0.001122768 +4 chany_top_out[19]:5 chany_top_out[19]:4 0.00341 +5 chany_top_out[19]:4 chany_top_out[19]:3 0.0005741833 +6 chany_top_out[19]:2 chany_top_out[19] 0.0006183035 +7 chany_top_out[19]:3 chany_top_out[19]:2 0.00341 + +*END + +*D_NET chany_bottom_in[8] 0.02350803 //LENGTH 160.545 LUMPCC 0.007246981 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 40.020 1.290 +*I mux_right_ipin_13\/mux_l1_in_2_:A1 I *L 0.00198 *C 38.280 20.060 +*I mux_right_ipin_11\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.590 55.420 +*I mux_right_ipin_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.130 64.600 +*I ropt_mt_inst_736:A I *L 0.001766 *C 48.300 99.280 +*N chany_bottom_in[8]:5 *C 25.360 68.000 +*N chany_bottom_in[8]:6 *C 48.300 99.280 +*N chany_bottom_in[8]:7 *C 48.300 99.325 +*N chany_bottom_in[8]:8 *C 48.300 104.040 +*N chany_bottom_in[8]:9 *C 47.840 104.040 +*N chany_bottom_in[8]:10 *C 47.840 107.055 +*N chany_bottom_in[8]:11 *C 47.795 107.100 +*N chany_bottom_in[8]:12 *C 41.860 107.100 +*N chany_bottom_in[8]:13 *C 41.860 108.120 +*N chany_bottom_in[8]:14 *C 34.500 108.120 +*N chany_bottom_in[8]:15 *C 34.500 107.100 +*N chany_bottom_in[8]:16 *C 28.565 107.100 +*N chany_bottom_in[8]:17 *C 28.520 107.055 +*N chany_bottom_in[8]:18 *C 28.520 105.445 +*N chany_bottom_in[8]:19 *C 28.475 105.400 +*N chany_bottom_in[8]:20 *C 27.140 105.400 +*N chany_bottom_in[8]:21 *C 27.140 105.060 +*N chany_bottom_in[8]:22 *C 27.140 105.015 +*N chany_bottom_in[8]:23 *C 27.140 100.698 +*N chany_bottom_in[8]:24 *C 27.133 100.640 +*N chany_bottom_in[8]:25 *C 25.780 100.640 +*N chany_bottom_in[8]:26 *C 25.760 100.633 +*N chany_bottom_in[8]:27 *C 25.760 68.008 +*N chany_bottom_in[8]:28 *C 25.760 68.000 +*N chany_bottom_in[8]:29 *C 25.760 67.943 +*N chany_bottom_in[8]:30 *C 25.168 64.600 +*N chany_bottom_in[8]:31 *C 25.715 64.600 +*N chany_bottom_in[8]:32 *C 25.760 64.600 +*N chany_bottom_in[8]:33 *C 25.590 55.420 +*N chany_bottom_in[8]:34 *C 25.760 55.420 +*N chany_bottom_in[8]:35 *C 25.760 55.420 +*N chany_bottom_in[8]:36 *C 25.760 51.738 +*N chany_bottom_in[8]:37 *C 25.768 51.680 +*N chany_bottom_in[8]:38 *C 34.940 51.680 +*N chany_bottom_in[8]:39 *C 34.960 51.672 +*N chany_bottom_in[8]:40 *C 34.960 20.408 +*N chany_bottom_in[8]:41 *C 34.980 20.400 +*N chany_bottom_in[8]:42 *C 38.172 20.400 +*N chany_bottom_in[8]:43 *C 38.180 20.400 +*N chany_bottom_in[8]:44 *C 38.180 20.060 +*N chany_bottom_in[8]:45 *C 38.180 20.060 +*N chany_bottom_in[8]:46 *C 39.100 20.060 +*N chany_bottom_in[8]:47 *C 39.100 11.900 +*N chany_bottom_in[8]:48 *C 40.020 11.900 + +*CAP +0 chany_bottom_in[8] 0.0005483262 +1 mux_right_ipin_13\/mux_l1_in_2_:A1 1e-06 +2 mux_right_ipin_11\/mux_l2_in_1_:A0 1e-06 +3 mux_right_ipin_3\/mux_l2_in_1_:A0 1e-06 +4 ropt_mt_inst_736:A 1e-06 +5 chany_bottom_in[8]:5 8.763636e-05 +6 chany_bottom_in[8]:6 4.00942e-05 +7 chany_bottom_in[8]:7 0.0002616705 +8 chany_bottom_in[8]:8 0.0002884042 +9 chany_bottom_in[8]:9 0.0002529208 +10 chany_bottom_in[8]:10 0.0002261871 +11 chany_bottom_in[8]:11 0.0004334059 +12 chany_bottom_in[8]:12 0.0004906196 +13 chany_bottom_in[8]:13 0.0004891485 +14 chany_bottom_in[8]:14 0.0004893989 +15 chany_bottom_in[8]:15 0.0005235113 +16 chany_bottom_in[8]:16 0.0004660473 +17 chany_bottom_in[8]:17 0.0001288036 +18 chany_bottom_in[8]:18 0.0001288036 +19 chany_bottom_in[8]:19 0.0001643514 +20 chany_bottom_in[8]:20 0.000193316 +21 chany_bottom_in[8]:21 6.266198e-05 +22 chany_bottom_in[8]:22 0.0002578764 +23 chany_bottom_in[8]:23 0.0002578764 +24 chany_bottom_in[8]:24 0.0001761073 +25 chany_bottom_in[8]:25 0.0001761073 +26 chany_bottom_in[8]:26 0.001343383 +27 chany_bottom_in[8]:27 0.001343383 +28 chany_bottom_in[8]:28 8.763636e-05 +29 chany_bottom_in[8]:29 0.0001861312 +30 chany_bottom_in[8]:30 5.877569e-05 +31 chany_bottom_in[8]:31 5.877569e-05 +32 chany_bottom_in[8]:32 0.0007747269 +33 chany_bottom_in[8]:33 5.853254e-05 +34 chany_bottom_in[8]:34 6.285978e-05 +35 chany_bottom_in[8]:35 0.0007992029 +36 chany_bottom_in[8]:36 0.0002068213 +37 chany_bottom_in[8]:37 0.0006850362 +38 chany_bottom_in[8]:38 0.0006850362 +39 chany_bottom_in[8]:39 0.0008334318 +40 chany_bottom_in[8]:40 0.0008334318 +41 chany_bottom_in[8]:41 0.0002336058 +42 chany_bottom_in[8]:42 0.0002336058 +43 chany_bottom_in[8]:43 5.958545e-05 +44 chany_bottom_in[8]:44 3.59305e-05 +45 chany_bottom_in[8]:45 0.0001079626 +46 chany_bottom_in[8]:46 0.0004161194 +47 chany_bottom_in[8]:47 0.0004102576 +48 chany_bottom_in[8]:48 0.0005995373 +49 chany_bottom_in[8]:40 chany_bottom_in[13]:14 0.0003713421 +50 chany_bottom_in[8]:39 chany_bottom_in[13]:13 0.0003713421 +51 chany_bottom_in[8]:43 chany_top_in[5]:6 3.020743e-07 +52 chany_bottom_in[8]:40 chany_top_in[5]:10 0.001269424 +53 chany_bottom_in[8]:39 chany_top_in[5]:20 0.001269424 +54 chany_bottom_in[8]:28 chany_top_in[5]:15 1.718481e-06 +55 chany_bottom_in[8]:27 chany_top_in[5]:14 5.340573e-06 +56 chany_bottom_in[8]:26 chany_top_in[5]:13 5.340573e-06 +57 chany_bottom_in[8]:45 chany_top_in[5]:7 3.020743e-07 +58 chany_bottom_in[8]:46 chany_top_in[5]:7 4.183084e-07 +59 chany_bottom_in[8]:47 chany_top_in[5]:6 4.183084e-07 +60 chany_bottom_in[8]:5 chany_top_in[5]:19 1.718481e-06 +61 chany_bottom_in[8]:27 chany_top_in[9]:13 0.0005340549 +62 chany_bottom_in[8]:27 chany_top_in[9]:19 0.0009408362 +63 chany_bottom_in[8]:25 chany_top_in[9]:21 3.32066e-07 +64 chany_bottom_in[8]:26 chany_top_in[9]:20 0.0009408362 +65 chany_bottom_in[8]:26 chany_top_in[9]:19 0.0005340549 +66 chany_bottom_in[8]:24 chany_top_in[9]:22 3.32066e-07 +67 chany_bottom_in[8]:18 chany_top_in[9]:23 8.008969e-07 +68 chany_bottom_in[8]:17 chany_top_in[9] 8.008969e-07 +69 chany_bottom_in[8]:43 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.341029e-06 +70 chany_bottom_in[8]:45 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.341029e-06 +71 chany_bottom_in[8]:46 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002053185 +72 chany_bottom_in[8]:47 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002053185 +73 chany_bottom_in[8]:29 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.853589e-05 +74 chany_bottom_in[8]:32 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.629315e-05 +75 chany_bottom_in[8]:32 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.853589e-05 +76 chany_bottom_in[8]:35 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.629315e-05 +77 chany_bottom_in[8] ropt_net_174:4 0.0001510975 +78 chany_bottom_in[8]:48 ropt_net_174:5 0.0001510975 +79 chany_bottom_in[8]:7 ropt_net_143:10 7.802475e-05 +80 chany_bottom_in[8]:7 ropt_net_143:6 1.272693e-05 +81 chany_bottom_in[8]:9 ropt_net_143:8 5.583101e-06 +82 chany_bottom_in[8]:8 ropt_net_143:9 7.802475e-05 +83 chany_bottom_in[8]:8 ropt_net_143:7 1.831003e-05 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:48 0.009473214 +1 chany_bottom_in[8]:43 chany_bottom_in[8]:42 0.00341 +2 chany_bottom_in[8]:42 chany_bottom_in[8]:41 0.0005001583 +3 chany_bottom_in[8]:41 chany_bottom_in[8]:40 0.00341 +4 chany_bottom_in[8]:40 chany_bottom_in[8]:39 0.004898183 +5 chany_bottom_in[8]:38 chany_bottom_in[8]:37 0.001437025 +6 chany_bottom_in[8]:39 chany_bottom_in[8]:38 0.00341 +7 chany_bottom_in[8]:36 chany_bottom_in[8]:35 0.003287946 +8 chany_bottom_in[8]:37 chany_bottom_in[8]:36 0.00341 +9 chany_bottom_in[8]:29 chany_bottom_in[8]:28 0.00341 +10 chany_bottom_in[8]:28 chany_bottom_in[8]:27 0.00341 +11 chany_bottom_in[8]:28 chany_bottom_in[8]:5 5.69697e-05 +12 chany_bottom_in[8]:27 chany_bottom_in[8]:26 0.00511125 +13 chany_bottom_in[8]:25 chany_bottom_in[8]:24 0.0002118917 +14 chany_bottom_in[8]:26 chany_bottom_in[8]:25 0.00341 +15 chany_bottom_in[8]:23 chany_bottom_in[8]:22 0.003854911 +16 chany_bottom_in[8]:24 chany_bottom_in[8]:23 0.00341 +17 chany_bottom_in[8]:21 chany_bottom_in[8]:20 0.0003035715 +18 chany_bottom_in[8]:22 chany_bottom_in[8]:21 0.0045 +19 chany_bottom_in[8]:19 chany_bottom_in[8]:18 0.0045 +20 chany_bottom_in[8]:18 chany_bottom_in[8]:17 0.0014375 +21 chany_bottom_in[8]:16 chany_bottom_in[8]:15 0.005299107 +22 chany_bottom_in[8]:17 chany_bottom_in[8]:16 0.0045 +23 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.0045 +24 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.002691964 +25 chany_bottom_in[8]:6 ropt_mt_inst_736:A 0.152 +26 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.0045 +27 chany_bottom_in[8]:31 chany_bottom_in[8]:30 0.0004888393 +28 chany_bottom_in[8]:32 chany_bottom_in[8]:31 0.0045 +29 chany_bottom_in[8]:32 chany_bottom_in[8]:29 0.002984375 +30 chany_bottom_in[8]:30 mux_right_ipin_3\/mux_l2_in_1_:A0 0.152 +31 chany_bottom_in[8]:34 chany_bottom_in[8]:33 9.239131e-05 +32 chany_bottom_in[8]:35 chany_bottom_in[8]:34 0.0045 +33 chany_bottom_in[8]:35 chany_bottom_in[8]:32 0.008196429 +34 chany_bottom_in[8]:33 mux_right_ipin_11\/mux_l2_in_1_:A0 0.152 +35 chany_bottom_in[8]:44 mux_right_ipin_13\/mux_l1_in_2_:A1 0.152 +36 chany_bottom_in[8]:45 chany_bottom_in[8]:44 0.0045 +37 chany_bottom_in[8]:45 chany_bottom_in[8]:43 0.0001634615 +38 chany_bottom_in[8]:20 chany_bottom_in[8]:19 0.001191964 +39 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.0009107143 +40 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.006571429 +41 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.0009107143 +42 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.005299107 +43 chany_bottom_in[8]:46 chany_bottom_in[8]:45 0.0008214285 +44 chany_bottom_in[8]:47 chany_bottom_in[8]:46 0.007285715 +45 chany_bottom_in[8]:48 chany_bottom_in[8]:47 0.0008214285 +46 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.0004107143 +47 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.004209822 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.004379368 //LENGTH 33.965 LUMPCC 0.0006519078 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 43.085 82.960 +*I mux_right_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 31.380 82.960 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 26.855 91.460 +*I mux_right_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 30.920 88.695 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 30.920 88.695 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 26.855 91.460 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 27.140 91.460 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 27.140 91.415 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 27.140 88.445 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 27.185 88.400 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 30.920 88.400 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 31.418 82.960 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 33.075 82.960 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 33.120 83.005 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 33.120 88.355 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 33.120 88.400 +*N mux_tree_tapbuf_size10_1_sram[2]:16 *C 42.735 88.400 +*N mux_tree_tapbuf_size10_1_sram[2]:17 *C 42.780 88.355 +*N mux_tree_tapbuf_size10_1_sram[2]:18 *C 42.780 83.005 +*N mux_tree_tapbuf_size10_1_sram[2]:19 *C 42.780 82.960 +*N mux_tree_tapbuf_size10_1_sram[2]:20 *C 43.085 82.960 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_0\/mux_l3_in_0_:S 1e-06 +2 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 5.841366e-05 +5 mux_tree_tapbuf_size10_1_sram[2]:5 4.912239e-05 +6 mux_tree_tapbuf_size10_1_sram[2]:6 5.702061e-05 +7 mux_tree_tapbuf_size10_1_sram[2]:7 0.0001913175 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0001913175 +9 mux_tree_tapbuf_size10_1_sram[2]:9 0.0001689078 +10 mux_tree_tapbuf_size10_1_sram[2]:10 0.0002798548 +11 mux_tree_tapbuf_size10_1_sram[2]:11 0.0001207654 +12 mux_tree_tapbuf_size10_1_sram[2]:12 0.0001207654 +13 mux_tree_tapbuf_size10_1_sram[2]:13 0.0003204815 +14 mux_tree_tapbuf_size10_1_sram[2]:14 0.0003204815 +15 mux_tree_tapbuf_size10_1_sram[2]:15 0.0005578846 +16 mux_tree_tapbuf_size10_1_sram[2]:16 0.0004423322 +17 mux_tree_tapbuf_size10_1_sram[2]:17 0.0003712443 +18 mux_tree_tapbuf_size10_1_sram[2]:18 0.0003712443 +19 mux_tree_tapbuf_size10_1_sram[2]:19 5.347131e-05 +20 mux_tree_tapbuf_size10_1_sram[2]:20 4.883534e-05 +21 mux_tree_tapbuf_size10_1_sram[2]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.34865e-05 +22 mux_tree_tapbuf_size10_1_sram[2]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.833806e-05 +23 mux_tree_tapbuf_size10_1_sram[2]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001079138 +24 mux_tree_tapbuf_size10_1_sram[2]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.331075e-07 +25 mux_tree_tapbuf_size10_1_sram[2]:16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001079138 +26 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.833806e-05 +27 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.331075e-07 +28 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.34865e-05 +29 mux_tree_tapbuf_size10_1_sram[2]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.981597e-05 +30 mux_tree_tapbuf_size10_1_sram[2]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 2.103009e-05 +31 mux_tree_tapbuf_size10_1_sram[2]:16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.981597e-05 +32 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 2.103009e-05 +33 mux_tree_tapbuf_size10_1_sram[2]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.514414e-05 +34 mux_tree_tapbuf_size10_1_sram[2]:8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.828423e-06 +35 mux_tree_tapbuf_size10_1_sram[2]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.828423e-06 +36 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.514414e-05 +37 mux_tree_tapbuf_size10_1_sram[2]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.326381e-05 +38 mux_tree_tapbuf_size10_1_sram[2]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.326381e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:20 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:14 0.0045 +2 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:10 0.001964286 +3 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.004776786 +4 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.001479911 +5 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:12 0.0045 +6 mux_tree_tapbuf_size10_1_sram[2]:11 mux_right_ipin_0\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.0045 +8 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.002651786 +9 mux_tree_tapbuf_size10_1_sram[2]:6 mux_tree_tapbuf_size10_1_sram[2]:5 0.0001548913 +10 mux_tree_tapbuf_size10_1_sram[2]:7 mux_tree_tapbuf_size10_1_sram[2]:6 0.0045 +11 mux_tree_tapbuf_size10_1_sram[2]:5 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size10_1_sram[2]:4 mux_right_ipin_0\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[2]:15 0.008584822 +14 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:16 0.0045 +15 mux_tree_tapbuf_size10_1_sram[2]:19 mux_tree_tapbuf_size10_1_sram[2]:18 0.0045 +16 mux_tree_tapbuf_size10_1_sram[2]:18 mux_tree_tapbuf_size10_1_sram[2]:17 0.004776786 +17 mux_tree_tapbuf_size10_1_sram[2]:20 mux_tree_tapbuf_size10_1_sram[2]:19 0.0001657609 +18 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[2]:9 0.003334822 +19 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[2]:4 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[1] 0.004470634 //LENGTH 34.230 LUMPCC 0.0002361529 DR + +*CONN +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 25.605 75.140 +*I mux_right_ipin_4\/mux_l2_in_1_:S I *L 0.00357 *C 21.720 79.560 +*I mux_right_ipin_4\/mux_l2_in_0_:S I *L 0.00357 *C 18.960 82.960 +*I mux_right_ipin_4\/mux_l2_in_3_:S I *L 0.00357 *C 14.820 77.815 +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 6.600 77.180 +*I mux_right_ipin_4\/mux_l2_in_2_:S I *L 0.00357 *C 18.960 77.815 +*N mux_tree_tapbuf_size10_3_sram[1]:6 *C 18.960 77.815 +*N mux_tree_tapbuf_size10_3_sram[1]:7 *C 6.638 77.180 +*N mux_tree_tapbuf_size10_3_sram[1]:8 *C 15.180 77.180 +*N mux_tree_tapbuf_size10_3_sram[1]:9 *C 14.820 77.815 +*N mux_tree_tapbuf_size10_3_sram[1]:10 *C 14.857 77.520 +*N mux_tree_tapbuf_size10_3_sram[1]:11 *C 15.180 77.520 +*N mux_tree_tapbuf_size10_3_sram[1]:12 *C 18.960 77.520 +*N mux_tree_tapbuf_size10_3_sram[1]:13 *C 21.160 77.520 +*N mux_tree_tapbuf_size10_3_sram[1]:14 *C 18.998 82.960 +*N mux_tree_tapbuf_size10_3_sram[1]:15 *C 21.115 82.960 +*N mux_tree_tapbuf_size10_3_sram[1]:16 *C 21.160 82.915 +*N mux_tree_tapbuf_size10_3_sram[1]:17 *C 21.683 79.560 +*N mux_tree_tapbuf_size10_3_sram[1]:18 *C 21.205 79.560 +*N mux_tree_tapbuf_size10_3_sram[1]:19 *C 21.160 79.560 +*N mux_tree_tapbuf_size10_3_sram[1]:20 *C 21.160 77.905 +*N mux_tree_tapbuf_size10_3_sram[1]:21 *C 21.160 77.860 +*N mux_tree_tapbuf_size10_3_sram[1]:22 *C 22.035 77.860 +*N mux_tree_tapbuf_size10_3_sram[1]:23 *C 22.080 77.815 +*N mux_tree_tapbuf_size10_3_sram[1]:24 *C 22.080 75.185 +*N mux_tree_tapbuf_size10_3_sram[1]:25 *C 22.125 75.140 +*N mux_tree_tapbuf_size10_3_sram[1]:26 *C 25.568 75.140 + +*CAP +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_4\/mux_l2_in_1_:S 1e-06 +2 mux_right_ipin_4\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_4\/mux_l2_in_3_:S 1e-06 +4 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_right_ipin_4\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size10_3_sram[1]:6 5.97001e-05 +7 mux_tree_tapbuf_size10_3_sram[1]:7 0.0005529705 +8 mux_tree_tapbuf_size10_3_sram[1]:8 0.0005809503 +9 mux_tree_tapbuf_size10_3_sram[1]:9 5.43296e-05 +10 mux_tree_tapbuf_size10_3_sram[1]:10 5.926268e-05 +11 mux_tree_tapbuf_size10_3_sram[1]:11 0.0003310751 +12 mux_tree_tapbuf_size10_3_sram[1]:12 0.0004638867 +13 mux_tree_tapbuf_size10_3_sram[1]:13 0.0001942571 +14 mux_tree_tapbuf_size10_3_sram[1]:14 9.935105e-05 +15 mux_tree_tapbuf_size10_3_sram[1]:15 9.935105e-05 +16 mux_tree_tapbuf_size10_3_sram[1]:16 0.0001848002 +17 mux_tree_tapbuf_size10_3_sram[1]:17 5.983886e-05 +18 mux_tree_tapbuf_size10_3_sram[1]:18 5.983886e-05 +19 mux_tree_tapbuf_size10_3_sram[1]:19 0.0003150541 +20 mux_tree_tapbuf_size10_3_sram[1]:20 9.831696e-05 +21 mux_tree_tapbuf_size10_3_sram[1]:21 0.0001222122 +22 mux_tree_tapbuf_size10_3_sram[1]:22 9.324393e-05 +23 mux_tree_tapbuf_size10_3_sram[1]:23 0.0001753167 +24 mux_tree_tapbuf_size10_3_sram[1]:24 0.0001753167 +25 mux_tree_tapbuf_size10_3_sram[1]:25 0.0002247042 +26 mux_tree_tapbuf_size10_3_sram[1]:26 0.0002247042 +27 mux_tree_tapbuf_size10_3_sram[1]:15 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.564346e-05 +28 mux_tree_tapbuf_size10_3_sram[1]:14 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.564346e-05 +29 mux_tree_tapbuf_size10_3_sram[1]:19 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.795175e-05 +30 mux_tree_tapbuf_size10_3_sram[1]:15 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.448126e-05 +31 mux_tree_tapbuf_size10_3_sram[1]:16 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.795175e-05 +32 mux_tree_tapbuf_size10_3_sram[1]:14 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.448126e-05 + +*RES +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_3_sram[1]:26 0.152 +1 mux_tree_tapbuf_size10_3_sram[1]:7 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size10_3_sram[1]:9 mux_right_ipin_4\/mux_l2_in_3_:S 0.152 +3 mux_tree_tapbuf_size10_3_sram[1]:21 mux_tree_tapbuf_size10_3_sram[1]:20 0.0045 +4 mux_tree_tapbuf_size10_3_sram[1]:21 mux_tree_tapbuf_size10_3_sram[1]:13 0.0003035715 +5 mux_tree_tapbuf_size10_3_sram[1]:20 mux_tree_tapbuf_size10_3_sram[1]:19 0.001477679 +6 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:21 0.00078125 +7 mux_tree_tapbuf_size10_3_sram[1]:23 mux_tree_tapbuf_size10_3_sram[1]:22 0.0045 +8 mux_tree_tapbuf_size10_3_sram[1]:25 mux_tree_tapbuf_size10_3_sram[1]:24 0.0045 +9 mux_tree_tapbuf_size10_3_sram[1]:24 mux_tree_tapbuf_size10_3_sram[1]:23 0.002348214 +10 mux_tree_tapbuf_size10_3_sram[1]:26 mux_tree_tapbuf_size10_3_sram[1]:25 0.003073661 +11 mux_tree_tapbuf_size10_3_sram[1]:18 mux_tree_tapbuf_size10_3_sram[1]:17 0.0004263393 +12 mux_tree_tapbuf_size10_3_sram[1]:19 mux_tree_tapbuf_size10_3_sram[1]:18 0.0045 +13 mux_tree_tapbuf_size10_3_sram[1]:19 mux_tree_tapbuf_size10_3_sram[1]:16 0.002995536 +14 mux_tree_tapbuf_size10_3_sram[1]:17 mux_right_ipin_4\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size10_3_sram[1]:15 mux_tree_tapbuf_size10_3_sram[1]:14 0.001890625 +16 mux_tree_tapbuf_size10_3_sram[1]:16 mux_tree_tapbuf_size10_3_sram[1]:15 0.0045 +17 mux_tree_tapbuf_size10_3_sram[1]:14 mux_right_ipin_4\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size10_3_sram[1]:6 mux_right_ipin_4\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_3_sram[1]:8 mux_tree_tapbuf_size10_3_sram[1]:7 0.007627232 +20 mux_tree_tapbuf_size10_3_sram[1]:10 mux_tree_tapbuf_size10_3_sram[1]:9 0.0001271552 +21 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:10 0.0002879465 +22 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:8 0.0003035714 +23 mux_tree_tapbuf_size10_3_sram[1]:12 mux_tree_tapbuf_size10_3_sram[1]:11 0.003375 +24 mux_tree_tapbuf_size10_3_sram[1]:12 mux_tree_tapbuf_size10_3_sram[1]:6 0.0001271552 +25 mux_tree_tapbuf_size10_3_sram[1]:13 mux_tree_tapbuf_size10_3_sram[1]:12 0.001964286 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[1] 0.005510252 //LENGTH 39.820 LUMPCC 0.0007584399 DR + +*CONN +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 32.045 26.180 +*I mux_right_ipin_8\/mux_l2_in_1_:S I *L 0.00357 *C 26.340 34.680 +*I mux_right_ipin_8\/mux_l2_in_0_:S I *L 0.00357 *C 23.560 36.430 +*I mux_right_ipin_8\/mux_l2_in_2_:S I *L 0.00357 *C 25.860 39.440 +*I mux_right_ipin_8\/mux_l2_in_3_:S I *L 0.00357 *C 26.320 44.805 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.195 31.620 +*N mux_tree_tapbuf_size10_5_sram[1]:6 *C 17.233 31.620 +*N mux_tree_tapbuf_size10_5_sram[1]:7 *C 26.283 44.865 +*N mux_tree_tapbuf_size10_5_sram[1]:8 *C 25.805 44.880 +*N mux_tree_tapbuf_size10_5_sram[1]:9 *C 25.760 44.835 +*N mux_tree_tapbuf_size10_5_sram[1]:10 *C 25.860 39.440 +*N mux_tree_tapbuf_size10_5_sram[1]:11 *C 25.760 39.100 +*N mux_tree_tapbuf_size10_5_sram[1]:12 *C 25.760 39.100 +*N mux_tree_tapbuf_size10_5_sram[1]:13 *C 23.560 36.430 +*N mux_tree_tapbuf_size10_5_sram[1]:14 *C 23.560 36.040 +*N mux_tree_tapbuf_size10_5_sram[1]:15 *C 25.715 36.040 +*N mux_tree_tapbuf_size10_5_sram[1]:16 *C 25.760 36.040 +*N mux_tree_tapbuf_size10_5_sram[1]:17 *C 26.303 34.680 +*N mux_tree_tapbuf_size10_5_sram[1]:18 *C 25.805 34.680 +*N mux_tree_tapbuf_size10_5_sram[1]:19 *C 25.760 34.680 +*N mux_tree_tapbuf_size10_5_sram[1]:20 *C 25.760 31.665 +*N mux_tree_tapbuf_size10_5_sram[1]:21 *C 25.760 31.620 +*N mux_tree_tapbuf_size10_5_sram[1]:22 *C 31.695 31.620 +*N mux_tree_tapbuf_size10_5_sram[1]:23 *C 31.740 31.575 +*N mux_tree_tapbuf_size10_5_sram[1]:24 *C 31.740 26.225 +*N mux_tree_tapbuf_size10_5_sram[1]:25 *C 31.740 26.180 +*N mux_tree_tapbuf_size10_5_sram[1]:26 *C 32.045 26.180 + +*CAP +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_8\/mux_l2_in_1_:S 1e-06 +2 mux_right_ipin_8\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_8\/mux_l2_in_2_:S 1e-06 +4 mux_right_ipin_8\/mux_l2_in_3_:S 1e-06 +5 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_5_sram[1]:6 0.0005841063 +7 mux_tree_tapbuf_size10_5_sram[1]:7 4.927177e-05 +8 mux_tree_tapbuf_size10_5_sram[1]:8 4.927177e-05 +9 mux_tree_tapbuf_size10_5_sram[1]:9 0.0003066341 +10 mux_tree_tapbuf_size10_5_sram[1]:10 6.165019e-05 +11 mux_tree_tapbuf_size10_5_sram[1]:11 6.609684e-05 +12 mux_tree_tapbuf_size10_5_sram[1]:12 0.0004921925 +13 mux_tree_tapbuf_size10_5_sram[1]:13 5.85115e-05 +14 mux_tree_tapbuf_size10_5_sram[1]:14 0.0001931863 +15 mux_tree_tapbuf_size10_5_sram[1]:15 0.0001630352 +16 mux_tree_tapbuf_size10_5_sram[1]:16 0.0002682983 +17 mux_tree_tapbuf_size10_5_sram[1]:17 6.028321e-05 +18 mux_tree_tapbuf_size10_5_sram[1]:18 6.028321e-05 +19 mux_tree_tapbuf_size10_5_sram[1]:19 0.000262605 +20 mux_tree_tapbuf_size10_5_sram[1]:20 0.000143666 +21 mux_tree_tapbuf_size10_5_sram[1]:21 0.0008611809 +22 mux_tree_tapbuf_size10_5_sram[1]:22 0.0002418058 +23 mux_tree_tapbuf_size10_5_sram[1]:23 0.0003616173 +24 mux_tree_tapbuf_size10_5_sram[1]:24 0.0003616173 +25 mux_tree_tapbuf_size10_5_sram[1]:25 5.228951e-05 +26 mux_tree_tapbuf_size10_5_sram[1]:26 4.820857e-05 +27 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0002145747 +28 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 9.268778e-05 +29 mux_tree_tapbuf_size10_5_sram[1]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 9.268778e-05 +30 mux_tree_tapbuf_size10_5_sram[1]:22 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.0002145747 +31 mux_tree_tapbuf_size10_5_sram[1]:20 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.855116e-05 +32 mux_tree_tapbuf_size10_5_sram[1]:16 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.406269e-06 +33 mux_tree_tapbuf_size10_5_sram[1]:19 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.406269e-06 +34 mux_tree_tapbuf_size10_5_sram[1]:19 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.855116e-05 + +*RES +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_5_sram[1]:26 0.152 +1 mux_tree_tapbuf_size10_5_sram[1]:11 mux_tree_tapbuf_size10_5_sram[1]:10 0.0002073171 +2 mux_tree_tapbuf_size10_5_sram[1]:12 mux_tree_tapbuf_size10_5_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size10_5_sram[1]:12 mux_tree_tapbuf_size10_5_sram[1]:9 0.005120537 +4 mux_tree_tapbuf_size10_5_sram[1]:10 mux_right_ipin_8\/mux_l2_in_2_:S 0.152 +5 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_5_sram[1]:20 0.0045 +6 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_5_sram[1]:6 0.00761384 +7 mux_tree_tapbuf_size10_5_sram[1]:20 mux_tree_tapbuf_size10_5_sram[1]:19 0.002691964 +8 mux_tree_tapbuf_size10_5_sram[1]:15 mux_tree_tapbuf_size10_5_sram[1]:14 0.001924107 +9 mux_tree_tapbuf_size10_5_sram[1]:16 mux_tree_tapbuf_size10_5_sram[1]:15 0.0045 +10 mux_tree_tapbuf_size10_5_sram[1]:16 mux_tree_tapbuf_size10_5_sram[1]:12 0.002732143 +11 mux_tree_tapbuf_size10_5_sram[1]:13 mux_right_ipin_8\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size10_5_sram[1]:7 mux_right_ipin_8\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size10_5_sram[1]:8 mux_tree_tapbuf_size10_5_sram[1]:7 0.0004263393 +14 mux_tree_tapbuf_size10_5_sram[1]:9 mux_tree_tapbuf_size10_5_sram[1]:8 0.0045 +15 mux_tree_tapbuf_size10_5_sram[1]:17 mux_right_ipin_8\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size10_5_sram[1]:18 mux_tree_tapbuf_size10_5_sram[1]:17 0.0004441965 +17 mux_tree_tapbuf_size10_5_sram[1]:19 mux_tree_tapbuf_size10_5_sram[1]:18 0.0045 +18 mux_tree_tapbuf_size10_5_sram[1]:19 mux_tree_tapbuf_size10_5_sram[1]:16 0.001214286 +19 mux_tree_tapbuf_size10_5_sram[1]:6 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +20 mux_tree_tapbuf_size10_5_sram[1]:22 mux_tree_tapbuf_size10_5_sram[1]:21 0.005299108 +21 mux_tree_tapbuf_size10_5_sram[1]:23 mux_tree_tapbuf_size10_5_sram[1]:22 0.0045 +22 mux_tree_tapbuf_size10_5_sram[1]:25 mux_tree_tapbuf_size10_5_sram[1]:24 0.0045 +23 mux_tree_tapbuf_size10_5_sram[1]:24 mux_tree_tapbuf_size10_5_sram[1]:23 0.004776785 +24 mux_tree_tapbuf_size10_5_sram[1]:26 mux_tree_tapbuf_size10_5_sram[1]:25 0.0001657609 +25 mux_tree_tapbuf_size10_5_sram[1]:14 mux_tree_tapbuf_size10_5_sram[1]:13 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[1] 0.005190922 //LENGTH 38.875 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.025 15.300 +*I mux_right_ipin_13\/mux_l2_in_3_:S I *L 0.00357 *C 50.960 14.280 +*I mux_right_ipin_13\/mux_l2_in_0_:S I *L 0.00357 *C 47.940 12.240 +*I mux_right_ipin_13\/mux_l2_in_1_:S I *L 0.00357 *C 41.300 12.580 +*I mux_right_ipin_13\/mux_l2_in_2_:S I *L 0.00357 *C 59.460 18.360 +*I mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.975 20.740 +*N mux_tree_tapbuf_size10_8_sram[1]:6 *C 59.998 20.768 +*N mux_tree_tapbuf_size10_8_sram[1]:7 *C 60.010 21.080 +*N mux_tree_tapbuf_size10_8_sram[1]:8 *C 60.675 21.080 +*N mux_tree_tapbuf_size10_8_sram[1]:9 *C 60.720 21.035 +*N mux_tree_tapbuf_size10_8_sram[1]:10 *C 59.498 18.360 +*N mux_tree_tapbuf_size10_8_sram[1]:11 *C 60.675 18.360 +*N mux_tree_tapbuf_size10_8_sram[1]:12 *C 60.720 18.360 +*N mux_tree_tapbuf_size10_8_sram[1]:13 *C 41.300 12.580 +*N mux_tree_tapbuf_size10_8_sram[1]:14 *C 41.400 12.625 +*N mux_tree_tapbuf_size10_8_sram[1]:15 *C 41.400 14.902 +*N mux_tree_tapbuf_size10_8_sram[1]:16 *C 41.407 14.960 +*N mux_tree_tapbuf_size10_8_sram[1]:17 *C 47.977 12.240 +*N mux_tree_tapbuf_size10_8_sram[1]:18 *C 48.715 12.240 +*N mux_tree_tapbuf_size10_8_sram[1]:19 *C 48.760 12.285 +*N mux_tree_tapbuf_size10_8_sram[1]:20 *C 50.922 14.280 +*N mux_tree_tapbuf_size10_8_sram[1]:21 *C 48.805 14.280 +*N mux_tree_tapbuf_size10_8_sram[1]:22 *C 48.760 14.280 +*N mux_tree_tapbuf_size10_8_sram[1]:23 *C 48.760 14.902 +*N mux_tree_tapbuf_size10_8_sram[1]:24 *C 48.760 14.960 +*N mux_tree_tapbuf_size10_8_sram[1]:25 *C 60.713 14.960 +*N mux_tree_tapbuf_size10_8_sram[1]:26 *C 60.720 14.960 +*N mux_tree_tapbuf_size10_8_sram[1]:27 *C 60.720 15.345 +*N mux_tree_tapbuf_size10_8_sram[1]:28 *C 60.720 15.300 +*N mux_tree_tapbuf_size10_8_sram[1]:29 *C 61.025 15.300 + +*CAP +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_13\/mux_l2_in_3_:S 1e-06 +2 mux_right_ipin_13\/mux_l2_in_0_:S 1e-06 +3 mux_right_ipin_13\/mux_l2_in_1_:S 1e-06 +4 mux_right_ipin_13\/mux_l2_in_2_:S 1e-06 +5 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_8_sram[1]:6 3.051586e-05 +7 mux_tree_tapbuf_size10_8_sram[1]:7 9.328614e-05 +8 mux_tree_tapbuf_size10_8_sram[1]:8 6.277028e-05 +9 mux_tree_tapbuf_size10_8_sram[1]:9 0.0001815231 +10 mux_tree_tapbuf_size10_8_sram[1]:10 0.000108146 +11 mux_tree_tapbuf_size10_8_sram[1]:11 0.000108146 +12 mux_tree_tapbuf_size10_8_sram[1]:12 0.0004117388 +13 mux_tree_tapbuf_size10_8_sram[1]:13 3.039799e-05 +14 mux_tree_tapbuf_size10_8_sram[1]:14 0.0001511837 +15 mux_tree_tapbuf_size10_8_sram[1]:15 0.0001511837 +16 mux_tree_tapbuf_size10_8_sram[1]:16 0.0004803794 +17 mux_tree_tapbuf_size10_8_sram[1]:17 7.176954e-05 +18 mux_tree_tapbuf_size10_8_sram[1]:18 7.176954e-05 +19 mux_tree_tapbuf_size10_8_sram[1]:19 0.0001204276 +20 mux_tree_tapbuf_size10_8_sram[1]:20 0.0001629692 +21 mux_tree_tapbuf_size10_8_sram[1]:21 0.0001629692 +22 mux_tree_tapbuf_size10_8_sram[1]:22 0.0001993073 +23 mux_tree_tapbuf_size10_8_sram[1]:23 4.945564e-05 +24 mux_tree_tapbuf_size10_8_sram[1]:24 0.001319018 +25 mux_tree_tapbuf_size10_8_sram[1]:25 0.0008386389 +26 mux_tree_tapbuf_size10_8_sram[1]:26 5.666674e-05 +27 mux_tree_tapbuf_size10_8_sram[1]:27 0.0002210181 +28 mux_tree_tapbuf_size10_8_sram[1]:28 5.157607e-05 +29 mux_tree_tapbuf_size10_8_sram[1]:29 5.006495e-05 + +*RES +0 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_8_sram[1]:29 0.152 +1 mux_tree_tapbuf_size10_8_sram[1]:26 mux_tree_tapbuf_size10_8_sram[1]:25 0.00341 +2 mux_tree_tapbuf_size10_8_sram[1]:25 mux_tree_tapbuf_size10_8_sram[1]:24 0.001872558 +3 mux_tree_tapbuf_size10_8_sram[1]:18 mux_tree_tapbuf_size10_8_sram[1]:17 0.0006584821 +4 mux_tree_tapbuf_size10_8_sram[1]:19 mux_tree_tapbuf_size10_8_sram[1]:18 0.0045 +5 mux_tree_tapbuf_size10_8_sram[1]:17 mux_right_ipin_13\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size10_8_sram[1]:23 mux_tree_tapbuf_size10_8_sram[1]:22 0.0005558037 +7 mux_tree_tapbuf_size10_8_sram[1]:24 mux_tree_tapbuf_size10_8_sram[1]:23 0.00341 +8 mux_tree_tapbuf_size10_8_sram[1]:24 mux_tree_tapbuf_size10_8_sram[1]:16 0.001151892 +9 mux_tree_tapbuf_size10_8_sram[1]:21 mux_tree_tapbuf_size10_8_sram[1]:20 0.001890625 +10 mux_tree_tapbuf_size10_8_sram[1]:22 mux_tree_tapbuf_size10_8_sram[1]:21 0.0045 +11 mux_tree_tapbuf_size10_8_sram[1]:22 mux_tree_tapbuf_size10_8_sram[1]:19 0.00178125 +12 mux_tree_tapbuf_size10_8_sram[1]:20 mux_right_ipin_13\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size10_8_sram[1]:11 mux_tree_tapbuf_size10_8_sram[1]:10 0.001051339 +14 mux_tree_tapbuf_size10_8_sram[1]:12 mux_tree_tapbuf_size10_8_sram[1]:11 0.0045 +15 mux_tree_tapbuf_size10_8_sram[1]:12 mux_tree_tapbuf_size10_8_sram[1]:9 0.002388393 +16 mux_tree_tapbuf_size10_8_sram[1]:10 mux_right_ipin_13\/mux_l2_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_8_sram[1]:13 mux_right_ipin_13\/mux_l2_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_8_sram[1]:14 mux_tree_tapbuf_size10_8_sram[1]:13 0.0045 +19 mux_tree_tapbuf_size10_8_sram[1]:15 mux_tree_tapbuf_size10_8_sram[1]:14 0.002033482 +20 mux_tree_tapbuf_size10_8_sram[1]:16 mux_tree_tapbuf_size10_8_sram[1]:15 0.00341 +21 mux_tree_tapbuf_size10_8_sram[1]:8 mux_tree_tapbuf_size10_8_sram[1]:7 0.00059375 +22 mux_tree_tapbuf_size10_8_sram[1]:9 mux_tree_tapbuf_size10_8_sram[1]:8 0.0045 +23 mux_tree_tapbuf_size10_8_sram[1]:6 mem_right_ipin_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +24 mux_tree_tapbuf_size10_8_sram[1]:28 mux_tree_tapbuf_size10_8_sram[1]:27 0.0045 +25 mux_tree_tapbuf_size10_8_sram[1]:27 mux_tree_tapbuf_size10_8_sram[1]:26 0.0001850962 +26 mux_tree_tapbuf_size10_8_sram[1]:27 mux_tree_tapbuf_size10_8_sram[1]:12 0.002691964 +27 mux_tree_tapbuf_size10_8_sram[1]:29 mux_tree_tapbuf_size10_8_sram[1]:28 0.0001657609 +28 mux_tree_tapbuf_size10_8_sram[1]:7 mux_tree_tapbuf_size10_8_sram[1]:6 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[0] 0.002726713 //LENGTH 22.325 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 24.685 99.280 +*I mux_right_ipin_2\/mux_l1_in_0_:S I *L 0.00357 *C 25.420 94.520 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 12.135 102.340 +*N mux_tree_tapbuf_size8_0_sram[0]:3 *C 12.173 102.340 +*N mux_tree_tapbuf_size8_0_sram[0]:4 *C 24.795 102.340 +*N mux_tree_tapbuf_size8_0_sram[0]:5 *C 24.840 102.295 +*N mux_tree_tapbuf_size8_0_sram[0]:6 *C 25.383 94.520 +*N mux_tree_tapbuf_size8_0_sram[0]:7 *C 24.885 94.520 +*N mux_tree_tapbuf_size8_0_sram[0]:8 *C 24.840 94.565 +*N mux_tree_tapbuf_size8_0_sram[0]:9 *C 24.840 99.280 +*N mux_tree_tapbuf_size8_0_sram[0]:10 *C 24.840 99.280 +*N mux_tree_tapbuf_size8_0_sram[0]:11 *C 24.685 99.280 + +*CAP +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_2\/mux_l1_in_0_:S 1e-06 +2 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_0_sram[0]:3 0.0008087914 +4 mux_tree_tapbuf_size8_0_sram[0]:4 0.0008087914 +5 mux_tree_tapbuf_size8_0_sram[0]:5 0.0001653926 +6 mux_tree_tapbuf_size8_0_sram[0]:6 6.052511e-05 +7 mux_tree_tapbuf_size8_0_sram[0]:7 6.052511e-05 +8 mux_tree_tapbuf_size8_0_sram[0]:8 0.0002606145 +9 mux_tree_tapbuf_size8_0_sram[0]:9 0.0004573035 +10 mux_tree_tapbuf_size8_0_sram[0]:10 5.294466e-05 +11 mux_tree_tapbuf_size8_0_sram[0]:11 4.882483e-05 + +*RES +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_0_sram[0]:11 0.152 +1 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:8 0.004209822 +3 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:5 0.002691964 +4 mux_tree_tapbuf_size8_0_sram[0]:11 mux_tree_tapbuf_size8_0_sram[0]:10 8.423914e-05 +5 mux_tree_tapbuf_size8_0_sram[0]:4 mux_tree_tapbuf_size8_0_sram[0]:3 0.01127009 +6 mux_tree_tapbuf_size8_0_sram[0]:5 mux_tree_tapbuf_size8_0_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size8_0_sram[0]:3 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_0_sram[0]:7 mux_tree_tapbuf_size8_0_sram[0]:6 0.0004441965 +9 mux_tree_tapbuf_size8_0_sram[0]:8 mux_tree_tapbuf_size8_0_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size8_0_sram[0]:6 mux_right_ipin_2\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[0] 0.004980183 //LENGTH 34.505 LUMPCC 0.0003758235 DR + +*CONN +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.205 74.800 +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.735 64.260 +*I mux_right_ipin_6\/mux_l1_in_0_:S I *L 0.00357 *C 30.720 74.120 +*N mux_tree_tapbuf_size8_2_sram[0]:3 *C 30.720 74.120 +*N mux_tree_tapbuf_size8_2_sram[0]:4 *C 30.820 74.120 +*N mux_tree_tapbuf_size8_2_sram[0]:5 *C 30.828 74.120 +*N mux_tree_tapbuf_size8_2_sram[0]:6 *C 39.735 64.260 +*N mux_tree_tapbuf_size8_2_sram[0]:7 *C 39.560 64.260 +*N mux_tree_tapbuf_size8_2_sram[0]:8 *C 39.560 64.305 +*N mux_tree_tapbuf_size8_2_sram[0]:9 *C 39.560 74.062 +*N mux_tree_tapbuf_size8_2_sram[0]:10 *C 39.560 74.127 +*N mux_tree_tapbuf_size8_2_sram[0]:11 *C 39.560 74.800 +*N mux_tree_tapbuf_size8_2_sram[0]:12 *C 52.893 74.800 +*N mux_tree_tapbuf_size8_2_sram[0]:13 *C 52.900 74.800 +*N mux_tree_tapbuf_size8_2_sram[0]:14 *C 52.900 74.800 +*N mux_tree_tapbuf_size8_2_sram[0]:15 *C 53.205 74.800 + +*CAP +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_6\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_2_sram[0]:3 3.176831e-05 +4 mux_tree_tapbuf_size8_2_sram[0]:4 3.710014e-05 +5 mux_tree_tapbuf_size8_2_sram[0]:5 0.0006678815 +6 mux_tree_tapbuf_size8_2_sram[0]:6 4.934834e-05 +7 mux_tree_tapbuf_size8_2_sram[0]:7 5.496839e-05 +8 mux_tree_tapbuf_size8_2_sram[0]:8 0.0006202827 +9 mux_tree_tapbuf_size8_2_sram[0]:9 0.0006202827 +10 mux_tree_tapbuf_size8_2_sram[0]:10 0.0007374648 +11 mux_tree_tapbuf_size8_2_sram[0]:11 0.0008539602 +12 mux_tree_tapbuf_size8_2_sram[0]:12 0.000784377 +13 mux_tree_tapbuf_size8_2_sram[0]:13 3.457436e-05 +14 mux_tree_tapbuf_size8_2_sram[0]:14 5.738156e-05 +15 mux_tree_tapbuf_size8_2_sram[0]:15 5.19696e-05 +16 mux_tree_tapbuf_size8_2_sram[0]:12 chany_bottom_in[5]:18 0.0001879117 +17 mux_tree_tapbuf_size8_2_sram[0]:11 chany_bottom_in[5]:17 0.0001879117 + +*RES +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_2_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_2_sram[0]:4 mux_tree_tapbuf_size8_2_sram[0]:3 0.0045 +2 mux_tree_tapbuf_size8_2_sram[0]:5 mux_tree_tapbuf_size8_2_sram[0]:4 0.00341 +3 mux_tree_tapbuf_size8_2_sram[0]:3 mux_right_ipin_6\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size8_2_sram[0]:13 mux_tree_tapbuf_size8_2_sram[0]:12 0.00341 +5 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:11 0.002088758 +6 mux_tree_tapbuf_size8_2_sram[0]:14 mux_tree_tapbuf_size8_2_sram[0]:13 0.0045 +7 mux_tree_tapbuf_size8_2_sram[0]:15 mux_tree_tapbuf_size8_2_sram[0]:14 0.0001657609 +8 mux_tree_tapbuf_size8_2_sram[0]:9 mux_tree_tapbuf_size8_2_sram[0]:8 0.008712054 +9 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:9 0.00341 +10 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:5 0.001368092 +11 mux_tree_tapbuf_size8_2_sram[0]:7 mux_tree_tapbuf_size8_2_sram[0]:6 9.51087e-05 +12 mux_tree_tapbuf_size8_2_sram[0]:8 mux_tree_tapbuf_size8_2_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size8_2_sram[0]:6 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size8_2_sram[0]:11 mux_tree_tapbuf_size8_2_sram[0]:10 0.0001053583 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[3] 0.001710237 //LENGTH 15.090 LUMPCC 0.0002890367 DR + +*CONN +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 10.885 39.440 +*I mux_right_ipin_10\/mux_l4_in_0_:S I *L 0.00357 *C 6.540 44.880 +*I mem_right_ipin_10\/FTB_14__53:A I *L 0.001746 *C 10.580 47.600 +*N mux_tree_tapbuf_size8_4_sram[3]:3 *C 10.543 47.600 +*N mux_tree_tapbuf_size8_4_sram[3]:4 *C 9.705 47.600 +*N mux_tree_tapbuf_size8_4_sram[3]:5 *C 9.660 47.555 +*N mux_tree_tapbuf_size8_4_sram[3]:6 *C 6.578 44.880 +*N mux_tree_tapbuf_size8_4_sram[3]:7 *C 9.615 44.880 +*N mux_tree_tapbuf_size8_4_sram[3]:8 *C 9.660 44.880 +*N mux_tree_tapbuf_size8_4_sram[3]:9 *C 10.120 44.880 +*N mux_tree_tapbuf_size8_4_sram[3]:10 *C 10.120 39.485 +*N mux_tree_tapbuf_size8_4_sram[3]:11 *C 10.165 39.440 +*N mux_tree_tapbuf_size8_4_sram[3]:12 *C 10.848 39.440 + +*CAP +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_10\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_10\/FTB_14__53:A 1e-06 +3 mux_tree_tapbuf_size8_4_sram[3]:3 6.988277e-05 +4 mux_tree_tapbuf_size8_4_sram[3]:4 6.988277e-05 +5 mux_tree_tapbuf_size8_4_sram[3]:5 0.0001090148 +6 mux_tree_tapbuf_size8_4_sram[3]:6 0.0001989483 +7 mux_tree_tapbuf_size8_4_sram[3]:7 0.0001989483 +8 mux_tree_tapbuf_size8_4_sram[3]:8 0.000142548 +9 mux_tree_tapbuf_size8_4_sram[3]:9 0.0002722963 +10 mux_tree_tapbuf_size8_4_sram[3]:10 0.0002387631 +11 mux_tree_tapbuf_size8_4_sram[3]:11 5.895818e-05 +12 mux_tree_tapbuf_size8_4_sram[3]:12 5.895818e-05 +13 mux_tree_tapbuf_size8_4_sram[3]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 7.871841e-05 +14 mux_tree_tapbuf_size8_4_sram[3]:10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 6.579992e-05 +15 mux_tree_tapbuf_size8_4_sram[3]:8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 7.871841e-05 +16 mux_tree_tapbuf_size8_4_sram[3]:9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 6.579992e-05 + +*RES +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_4_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_4_sram[3]:4 mux_tree_tapbuf_size8_4_sram[3]:3 0.0007477679 +2 mux_tree_tapbuf_size8_4_sram[3]:5 mux_tree_tapbuf_size8_4_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size8_4_sram[3]:3 mem_right_ipin_10\/FTB_14__53:A 0.152 +4 mux_tree_tapbuf_size8_4_sram[3]:11 mux_tree_tapbuf_size8_4_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size8_4_sram[3]:10 mux_tree_tapbuf_size8_4_sram[3]:9 0.004816965 +6 mux_tree_tapbuf_size8_4_sram[3]:12 mux_tree_tapbuf_size8_4_sram[3]:11 0.000609375 +7 mux_tree_tapbuf_size8_4_sram[3]:7 mux_tree_tapbuf_size8_4_sram[3]:6 0.002712054 +8 mux_tree_tapbuf_size8_4_sram[3]:8 mux_tree_tapbuf_size8_4_sram[3]:7 0.0045 +9 mux_tree_tapbuf_size8_4_sram[3]:8 mux_tree_tapbuf_size8_4_sram[3]:5 0.002388393 +10 mux_tree_tapbuf_size8_4_sram[3]:6 mux_right_ipin_10\/mux_l4_in_0_:S 0.152 +11 mux_tree_tapbuf_size8_4_sram[3]:9 mux_tree_tapbuf_size8_4_sram[3]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_6_sram[3] 0.001751727 //LENGTH 15.500 LUMPCC 0.0004109598 DR + +*CONN +*I mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 49.065 53.380 +*I mem_right_ipin_14\/FTB_16__55:A I *L 0.001746 *C 48.300 55.760 +*I mux_right_ipin_14\/mux_l4_in_0_:S I *L 0.00357 *C 36.800 55.925 +*N mux_tree_tapbuf_size8_6_sram[3]:3 *C 36.837 55.820 +*N mux_tree_tapbuf_size8_6_sram[3]:4 *C 48.263 55.760 +*N mux_tree_tapbuf_size8_6_sram[3]:5 *C 48.300 55.715 +*N mux_tree_tapbuf_size8_6_sram[3]:6 *C 48.300 53.425 +*N mux_tree_tapbuf_size8_6_sram[3]:7 *C 48.345 53.380 +*N mux_tree_tapbuf_size8_6_sram[3]:8 *C 49.028 53.380 + +*CAP +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_14\/FTB_16__55:A 1e-06 +2 mux_right_ipin_14\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_6_sram[3]:3 0.0004729292 +4 mux_tree_tapbuf_size8_6_sram[3]:4 0.0004729292 +5 mux_tree_tapbuf_size8_6_sram[3]:5 0.0001361626 +6 mux_tree_tapbuf_size8_6_sram[3]:6 0.0001361626 +7 mux_tree_tapbuf_size8_6_sram[3]:7 5.979157e-05 +8 mux_tree_tapbuf_size8_6_sram[3]:8 5.979157e-05 +9 mux_tree_tapbuf_size8_6_sram[3]:3 chany_top_in[0]:51 0.0002054799 +10 mux_tree_tapbuf_size8_6_sram[3]:4 chany_top_in[0]:52 0.0002054799 + +*RES +0 mem_right_ipin_14\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_6_sram[3]:8 0.152 +1 mux_tree_tapbuf_size8_6_sram[3]:3 mux_right_ipin_14\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_6_sram[3]:4 mem_right_ipin_14\/FTB_16__55:A 0.152 +3 mux_tree_tapbuf_size8_6_sram[3]:4 mux_tree_tapbuf_size8_6_sram[3]:3 0.01020089 +4 mux_tree_tapbuf_size8_6_sram[3]:5 mux_tree_tapbuf_size8_6_sram[3]:4 0.0045 +5 mux_tree_tapbuf_size8_6_sram[3]:7 mux_tree_tapbuf_size8_6_sram[3]:6 0.0045 +6 mux_tree_tapbuf_size8_6_sram[3]:6 mux_tree_tapbuf_size8_6_sram[3]:5 0.002044643 +7 mux_tree_tapbuf_size8_6_sram[3]:8 mux_tree_tapbuf_size8_6_sram[3]:7 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[3] 0.002485038 //LENGTH 19.800 LUMPCC 0.0003013949 DR + +*CONN +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 78.965 77.520 +*I mem_right_ipin_15\/FTB_17__56:A I *L 0.001743 *C 79.120 85.680 +*I mux_right_ipin_15\/mux_l4_in_0_:S I *L 0.00357 *C 70.480 79.560 +*N mux_tree_tapbuf_size8_7_sram[3]:3 *C 70.380 79.560 +*N mux_tree_tapbuf_size8_7_sram[3]:4 *C 70.380 79.560 +*N mux_tree_tapbuf_size8_7_sram[3]:5 *C 70.388 79.560 +*N mux_tree_tapbuf_size8_7_sram[3]:6 *C 79.083 85.680 +*N mux_tree_tapbuf_size8_7_sram[3]:7 *C 78.245 85.680 +*N mux_tree_tapbuf_size8_7_sram[3]:8 *C 78.200 85.635 +*N mux_tree_tapbuf_size8_7_sram[3]:9 *C 78.200 79.618 +*N mux_tree_tapbuf_size8_7_sram[3]:10 *C 78.193 79.560 +*N mux_tree_tapbuf_size8_7_sram[3]:11 *C 78.200 79.553 +*N mux_tree_tapbuf_size8_7_sram[3]:12 *C 78.200 77.528 +*N mux_tree_tapbuf_size8_7_sram[3]:13 *C 78.220 77.520 +*N mux_tree_tapbuf_size8_7_sram[3]:14 *C 79.112 77.520 +*N mux_tree_tapbuf_size8_7_sram[3]:15 *C 79.120 77.520 +*N mux_tree_tapbuf_size8_7_sram[3]:16 *C 79.120 77.520 +*N mux_tree_tapbuf_size8_7_sram[3]:17 *C 78.965 77.520 + +*CAP +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_15\/FTB_17__56:A 1e-06 +2 mux_right_ipin_15\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_7_sram[3]:3 3.227769e-05 +4 mux_tree_tapbuf_size8_7_sram[3]:4 3.523789e-05 +5 mux_tree_tapbuf_size8_7_sram[3]:5 0.0005471889 +6 mux_tree_tapbuf_size8_7_sram[3]:6 6.61129e-05 +7 mux_tree_tapbuf_size8_7_sram[3]:7 6.61129e-05 +8 mux_tree_tapbuf_size8_7_sram[3]:8 0.0001871277 +9 mux_tree_tapbuf_size8_7_sram[3]:9 0.0001871277 +10 mux_tree_tapbuf_size8_7_sram[3]:10 0.0005471889 +11 mux_tree_tapbuf_size8_7_sram[3]:11 0.0001173559 +12 mux_tree_tapbuf_size8_7_sram[3]:12 0.0001173559 +13 mux_tree_tapbuf_size8_7_sram[3]:13 6.845218e-05 +14 mux_tree_tapbuf_size8_7_sram[3]:14 6.845218e-05 +15 mux_tree_tapbuf_size8_7_sram[3]:15 3.22921e-05 +16 mux_tree_tapbuf_size8_7_sram[3]:16 5.637592e-05 +17 mux_tree_tapbuf_size8_7_sram[3]:17 5.198441e-05 +18 mux_tree_tapbuf_size8_7_sram[3]:9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.732437e-05 +19 mux_tree_tapbuf_size8_7_sram[3]:8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.732437e-05 +20 mux_tree_tapbuf_size8_7_sram[3]:9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.337307e-05 +21 mux_tree_tapbuf_size8_7_sram[3]:8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.337307e-05 + +*RES +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_7_sram[3]:17 0.152 +1 mux_tree_tapbuf_size8_7_sram[3]:9 mux_tree_tapbuf_size8_7_sram[3]:8 0.005372768 +2 mux_tree_tapbuf_size8_7_sram[3]:10 mux_tree_tapbuf_size8_7_sram[3]:9 0.00341 +3 mux_tree_tapbuf_size8_7_sram[3]:10 mux_tree_tapbuf_size8_7_sram[3]:5 0.001222783 +4 mux_tree_tapbuf_size8_7_sram[3]:7 mux_tree_tapbuf_size8_7_sram[3]:6 0.000747768 +5 mux_tree_tapbuf_size8_7_sram[3]:8 mux_tree_tapbuf_size8_7_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size8_7_sram[3]:6 mem_right_ipin_15\/FTB_17__56:A 0.152 +7 mux_tree_tapbuf_size8_7_sram[3]:4 mux_tree_tapbuf_size8_7_sram[3]:3 0.0045 +8 mux_tree_tapbuf_size8_7_sram[3]:5 mux_tree_tapbuf_size8_7_sram[3]:4 0.00341 +9 mux_tree_tapbuf_size8_7_sram[3]:3 mux_right_ipin_15\/mux_l4_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_7_sram[3]:11 mux_tree_tapbuf_size8_7_sram[3]:10 0.00341 +11 mux_tree_tapbuf_size8_7_sram[3]:13 mux_tree_tapbuf_size8_7_sram[3]:12 0.00341 +12 mux_tree_tapbuf_size8_7_sram[3]:12 mux_tree_tapbuf_size8_7_sram[3]:11 0.00031725 +13 mux_tree_tapbuf_size8_7_sram[3]:15 mux_tree_tapbuf_size8_7_sram[3]:14 0.00341 +14 mux_tree_tapbuf_size8_7_sram[3]:14 mux_tree_tapbuf_size8_7_sram[3]:13 0.000139825 +15 mux_tree_tapbuf_size8_7_sram[3]:16 mux_tree_tapbuf_size8_7_sram[3]:15 0.0045 +16 mux_tree_tapbuf_size8_7_sram[3]:17 mux_tree_tapbuf_size8_7_sram[3]:16 8.423914e-05 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001179993 //LENGTH 9.665 LUMPCC 9.489158e-05 DR + +*CONN +*I mux_left_ipin_0\/mux_l1_in_0_:X O *L 0 *C 59.165 41.820 +*I mux_left_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.500 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.463 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 61.225 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.180 45.175 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 61.180 41.865 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.135 41.820 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 59.203 41.820 + +*CAP +0 mux_left_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001907158 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001907158 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002027646 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002027646 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001480702 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001480702 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.744579e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.744579e-05 + +*RES +0 mux_left_ipin_0\/mux_l1_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_ipin_0\/mux_l2_in_0_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002890625 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002955357 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003378943 //LENGTH 2.305 LUMPCC 8.135748e-05 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_0_:X O *L 0 *C 32.025 77.785 +*I mux_right_ipin_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.040 77.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.003 77.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 32.062 77.845 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001272684 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001272684 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:6 4.067874e-05 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:15 4.067874e-05 + +*RES +0 mux_right_ipin_0\/mux_l1_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001732143 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_0\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0004607479 //LENGTH 3.395 LUMPCC 0.0001065276 DR + +*CONN +*I mux_right_ipin_0\/mux_l3_in_1_:X O *L 0 *C 30.075 87.720 +*I mux_right_ipin_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 26.970 87.720 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 27.008 87.720 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 30.038 87.720 + +*CAP +0 mux_right_ipin_0\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_0\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001761102 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001761102 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:9 5.326381e-05 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:10 5.326381e-05 + +*RES +0 mux_right_ipin_0\/mux_l3_in_1_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_0\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002705357 + +*END + +*D_NET mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00142808 //LENGTH 10.980 LUMPCC 0.0001512225 DR + +*CONN +*I mux_right_ipin_1\/mux_l2_in_2_:X O *L 0 *C 43.875 90.440 +*I mux_right_ipin_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 37.260 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 37.260 94.180 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 37.260 94.135 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 37.260 90.485 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 37.305 90.440 +*N mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 43.837 90.440 + +*CAP +0 mux_right_ipin_1\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_1\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.371983e-05 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001769782 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001769782 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004435905 +6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004435905 +7 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 optlc_net_132:18 7.561123e-05 +8 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 optlc_net_132:19 7.561123e-05 + +*RES +0 mux_right_ipin_1\/mux_l2_in_2_:X mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.005832589 +2 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.003258929 +4 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_1\/mux_l3_in_1_:A1 0.152 +5 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009676676 //LENGTH 8.420 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l2_in_2_:X O *L 0 *C 18.115 78.200 +*I mux_right_ipin_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 12.325 79.900 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 12.363 79.900 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 17.435 79.900 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 17.480 79.855 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 17.480 78.245 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 17.525 78.200 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 18.078 78.200 + +*CAP +0 mux_right_ipin_4\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_4\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003091659 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003091659 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000106657 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000106657 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.701096e-05 +7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.701096e-05 + +*RES +0 mux_right_ipin_4\/mux_l2_in_2_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_4\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.004529018 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.008096628 //LENGTH 62.625 LUMPCC 0.0005839472 DR + +*CONN +*I mux_right_ipin_5\/mux_l4_in_0_:X O *L 0 *C 51.235 64.600 +*I mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.805 80.385 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.843 80.290 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 8.695 80.240 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 8.740 80.195 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 8.740 78.258 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 8.748 78.200 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 50.133 78.200 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 50.140 78.142 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 50.140 64.645 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 50.185 64.600 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 51.198 64.600 + +*CAP +0 mux_right_ipin_5\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001644888 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001644888 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001203306 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001203306 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.002697923 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.002697923 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0006817412 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0006817412 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 9.08568e-05 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 9.08568e-05 +12 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_bottom_in[11]:17 0.0001023425 +13 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_bottom_in[11]:21 0.0001478655 +14 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_bottom_in[11]:21 0.0001023425 +15 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_bottom_in[11]:22 0.0001478655 +16 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 4.176564e-05 +17 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 4.176564e-05 + +*RES +0 mux_right_ipin_5\/mux_l4_in_0_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0009040179 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0045 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.01205134 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.006483649 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001729911 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.002546875 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001016578 //LENGTH 8.430 LUMPCC 0.0003392698 DR + +*CONN +*I mux_right_ipin_9\/mux_l1_in_2_:X O *L 0 *C 71.935 25.840 +*I mux_right_ipin_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 72.125 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 72.125 18.020 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.220 18.065 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.220 25.795 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.220 25.840 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 71.935 25.840 + +*CAP +0 mux_right_ipin_9\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_9\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.279501e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002693168 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002693168 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.424258e-05 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.963682e-05 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[4]:34 3.679686e-06 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[4]:35 5.145383e-05 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[4]:32 4.422319e-06 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[4]:31 3.679686e-06 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[4]:34 5.145383e-05 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[4]:33 4.422319e-06 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_6_sram[0]:9 5.687126e-05 +14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[0]:8 5.687126e-05 +15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_6_sram[1]:28 5.320777e-05 +16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[1]:29 5.320777e-05 + +*RES +0 mux_right_ipin_9\/mux_l1_in_2_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_9\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.006901786 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001548913 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001320251 //LENGTH 10.395 LUMPCC 0.00037583 DR + +*CONN +*I mux_right_ipin_12\/mux_l2_in_1_:X O *L 0 *C 19.145 9.860 +*I mux_right_ipin_12\/mux_l3_in_0_:A0 I *L 0.001631 *C 21.910 15.300 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 21.948 15.300 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 22.495 15.300 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 22.540 15.255 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 22.540 9.905 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 22.495 9.860 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 19.183 9.860 + +*CAP +0 mux_right_ipin_12\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_12\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.782146e-05 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.782146e-05 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002258457 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002258457 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001775431 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001775431 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_bottom_in[13]:29 6.417195e-06 +9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chany_bottom_in[13]:25 6.890076e-05 +10 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[13]:30 6.417195e-06 +11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_bottom_in[13]:24 6.890076e-05 +12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:16 2.045361e-05 +13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:17 2.013856e-05 +14 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:12 1.777025e-05 +15 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:13 2.045361e-05 +16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:16 2.013856e-05 +17 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size10_7_sram[1]:11 1.777025e-05 +18 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.423463e-05 +19 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.423463e-05 + +*RES +0 mux_right_ipin_12\/mux_l2_in_1_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_12\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004888393 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004776786 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002957589 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0] 0.007880799 //LENGTH 62.450 LUMPCC 0.001499686 DR + +*CONN +*I mux_right_ipin_13\/mux_l4_in_0_:X O *L 0 *C 41.115 21.080 +*I mux_right_ipin_13\/BUFT_RR_60:A I *L 0.001746 *C 7.360 47.600 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 6.650 47.600 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 7.360 47.600 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 7.360 47.600 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 7.357 47.600 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 7.360 47.593 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 7.360 26.527 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 7.380 26.520 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 40.933 26.520 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 40.940 26.463 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 40.940 21.125 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 40.940 21.080 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 41.115 21.080 + +*CAP +0 mux_right_ipin_13\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_13\/BUFT_RR_60:A 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.126815e-05 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.529681e-05 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.598021e-05 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 7.126815e-05 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.000847779 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.000847779 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001880022 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001880022 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0002981866 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0002981866 +12 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:12 5.782883e-05 +13 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:13 5.549599e-05 +14 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 prog_clk[0]:216 1.069228e-06 +15 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 prog_clk[0]:220 9.574866e-06 +16 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 prog_clk[0]:220 1.069228e-06 +17 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 prog_clk[0]:221 9.574866e-06 +18 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:102 0.0004808691 +19 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:112 2.984122e-05 +20 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:118 2.96848e-05 +21 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:127 1.964637e-05 +22 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:137 1.109102e-06 +23 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:103 0.0004808691 +24 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:127 2.96848e-05 +25 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:128 1.964637e-05 +26 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:137 2.984122e-05 +27 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:138 1.109102e-06 +28 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:165 1.493544e-05 +29 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:169 2.16166e-07 +30 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 prog_clk[0]:164 1.493544e-05 +31 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 prog_clk[0]:168 2.16166e-07 +32 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.000162897 +33 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.000162897 + +*RES +0 mux_right_ipin_13\/mux_l4_in_0_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:12 9.51087e-05 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0045 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.004765625 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.005256558 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.003300183 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.00341 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001039141 +10 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +11 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +12 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_13\/BUFT_RR_60:A 0.152 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008585812 //LENGTH 7.320 LUMPCC 0.000214607 DR + +*CONN +*I mux_right_ipin_7\/mux_l2_in_1_:X O *L 0 *C 63.655 87.720 +*I mux_right_ipin_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 63.195 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.158 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 62.145 91.460 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 62.100 91.415 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 62.100 87.765 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 62.145 87.720 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 63.617 87.720 + +*CAP +0 mux_right_ipin_7\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_7\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.826477e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.826477e-05 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001327643 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001327643 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001199581 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001199581 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.58925e-05 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.58925e-05 +10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.141098e-05 +11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.141098e-05 + +*RES +0 mux_right_ipin_7\/mux_l2_in_1_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_7\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0009040179 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003258929 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004384268 //LENGTH 2.260 LUMPCC 9.109102e-05 DR + +*CONN +*I mux_right_ipin_10\/mux_l3_in_1_:X O *L 0 *C 7.535 42.840 +*I mux_right_ipin_10\/mux_l4_in_0_:A0 I *L 0.001631 *C 7.650 44.200 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 7.650 44.200 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 7.820 44.200 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 7.820 44.155 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 7.820 42.885 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 7.820 42.840 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 7.535 42.840 + +*CAP +0 mux_right_ipin_10\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_10\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.653282e-05 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.717127e-05 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.434451e-05 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.434451e-05 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.571628e-05 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.722636e-05 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.554551e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.554551e-05 + +*RES +0 mux_right_ipin_10\/mux_l3_in_1_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_10\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009296483 //LENGTH 6.800 LUMPCC 0.000198543 DR + +*CONN +*I mux_right_ipin_14\/mux_l2_in_0_:X O *L 0 *C 38.925 41.820 +*I mux_right_ipin_14\/mux_l3_in_0_:A1 I *L 0.00198 *C 37.165 45.220 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 37.128 45.220 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 36.800 45.220 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 36.800 44.880 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 38.595 44.880 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 38.640 44.835 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 38.640 41.865 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 38.640 41.820 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 38.925 41.820 + +*CAP +0 mux_right_ipin_14\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_14\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.963051e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.420867e-05 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001096493 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.507117e-05 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001499021 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001499021 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.006725e-05 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.06742e-05 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.530007e-05 +11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.518187e-06 +12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.530007e-05 +13 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.518187e-06 +14 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.755266e-07 +15 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.755266e-07 +16 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.907771e-05 +17 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.907771e-05 + +*RES +0 mux_right_ipin_14\/mux_l2_in_0_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001548913 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002651786 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001602679 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_14\/mux_l3_in_0_:A1 0.152 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003035715 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002924107 + +*END + +*D_NET chany_top_out[14] 0.0009321356 //LENGTH 7.095 LUMPCC 0.0001654345 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 39.215 102.340 +*P chany_top_out[14] O *L 0.7423 *C 37.720 107.475 +*N chany_top_out[14]:2 *C 37.720 102.385 +*N chany_top_out[14]:3 *C 37.765 102.340 +*N chany_top_out[14]:4 *C 39.178 102.340 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 chany_top_out[14] 0.000302029 +2 chany_top_out[14]:2 0.000302029 +3 chany_top_out[14]:3 8.082149e-05 +4 chany_top_out[14]:4 8.082149e-05 +5 chany_top_out[14] ropt_net_180:5 5.916625e-06 +6 chany_top_out[14]:3 ropt_net_180:3 3.187951e-05 +7 chany_top_out[14]:3 ropt_net_180:7 4.492113e-05 +8 chany_top_out[14]:2 ropt_net_180:4 5.916625e-06 +9 chany_top_out[14]:4 ropt_net_180:2 3.187951e-05 +10 chany_top_out[14]:4 ropt_net_180:6 4.492113e-05 + +*RES +0 ropt_mt_inst_777:X chany_top_out[14]:4 0.152 +1 chany_top_out[14]:3 chany_top_out[14]:2 0.0045 +2 chany_top_out[14]:2 chany_top_out[14] 0.004544643 +3 chany_top_out[14]:4 chany_top_out[14]:3 0.001261161 + +*END + +*D_NET left_grid_pin_13_[0] 0.001071029 //LENGTH 8.190 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 7.095 58.480 +*P left_grid_pin_13_[0] O *L 0.7423 *C 1.305 57.120 +*N left_grid_pin_13_[0]:2 *C 1.380 57.800 +*N left_grid_pin_13_[0]:3 *C 5.053 57.800 +*N left_grid_pin_13_[0]:4 *C 5.060 57.858 +*N left_grid_pin_13_[0]:5 *C 5.060 58.435 +*N left_grid_pin_13_[0]:6 *C 5.105 58.480 +*N left_grid_pin_13_[0]:7 *C 7.058 58.480 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 left_grid_pin_13_[0] 5.96982e-05 +2 left_grid_pin_13_[0]:2 0.0003275394 +3 left_grid_pin_13_[0]:3 0.0002678412 +4 left_grid_pin_13_[0]:4 7.168554e-05 +5 left_grid_pin_13_[0]:5 7.168554e-05 +6 left_grid_pin_13_[0]:6 0.0001357894 +7 left_grid_pin_13_[0]:7 0.0001357894 + +*RES +0 ropt_mt_inst_740:X left_grid_pin_13_[0]:7 0.152 +1 left_grid_pin_13_[0]:7 left_grid_pin_13_[0]:6 0.001743304 +2 left_grid_pin_13_[0]:6 left_grid_pin_13_[0]:5 0.0045 +3 left_grid_pin_13_[0]:5 left_grid_pin_13_[0]:4 0.000515625 +4 left_grid_pin_13_[0]:4 left_grid_pin_13_[0]:3 0.00341 +5 left_grid_pin_13_[0]:3 left_grid_pin_13_[0]:2 0.0005753583 +6 left_grid_pin_13_[0]:2 left_grid_pin_13_[0] 0.0001065333 + +*END + +*D_NET ropt_net_182 0.002312679 //LENGTH 15.220 LUMPCC 0.0007511378 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 71.495 102.000 +*I ropt_mt_inst_797:A I *L 0.001766 *C 60.260 104.720 +*N ropt_net_182:2 *C 60.260 104.720 +*N ropt_net_182:3 *C 60.260 104.675 +*N ropt_net_182:4 *C 60.260 102.725 +*N ropt_net_182:5 *C 60.305 102.680 +*N ropt_net_182:6 *C 68.495 102.680 +*N ropt_net_182:7 *C 68.540 102.635 +*N ropt_net_182:8 *C 68.540 102.045 +*N ropt_net_182:9 *C 68.585 102.000 +*N ropt_net_182:10 *C 71.458 102.000 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_182:2 3.66376e-05 +3 ropt_net_182:3 0.0001648052 +4 ropt_net_182:4 0.0001648052 +5 ropt_net_182:5 0.0004210129 +6 ropt_net_182:6 0.0004210129 +7 ropt_net_182:7 6.224529e-05 +8 ropt_net_182:8 6.224529e-05 +9 ropt_net_182:9 0.0001133884 +10 ropt_net_182:10 0.0001133884 +11 ropt_net_182:5 ropt_net_175:4 0.0002537775 +12 ropt_net_182:6 ropt_net_175:5 0.0002537775 +13 ropt_net_182:9 chany_top_out[6]:3 0.0001217915 +14 ropt_net_182:10 chany_top_out[6]:4 0.0001217915 + +*RES +0 ropt_mt_inst_744:X ropt_net_182:10 0.152 +1 ropt_net_182:2 ropt_mt_inst_797:A 0.152 +2 ropt_net_182:3 ropt_net_182:2 0.0045 +3 ropt_net_182:5 ropt_net_182:4 0.0045 +4 ropt_net_182:4 ropt_net_182:3 0.001741071 +5 ropt_net_182:6 ropt_net_182:5 0.0073125 +6 ropt_net_182:7 ropt_net_182:6 0.0045 +7 ropt_net_182:9 ropt_net_182:8 0.0045 +8 ropt_net_182:8 ropt_net_182:7 0.0005267857 +9 ropt_net_182:10 ropt_net_182:9 0.002564732 + +*END + +*D_NET ropt_net_174 0.002797009 //LENGTH 19.565 LUMPCC 0.0007687013 DR + +*CONN +*I ropt_mt_inst_753:X O *L 0 *C 46.655 11.560 +*I ropt_mt_inst_783:A I *L 0.001766 *C 36.800 4.080 +*N ropt_net_174:2 *C 36.837 4.080 +*N ropt_net_174:3 *C 40.435 4.080 +*N ropt_net_174:4 *C 40.480 4.125 +*N ropt_net_174:5 *C 40.480 9.463 +*N ropt_net_174:6 *C 40.488 9.520 +*N ropt_net_174:7 *C 44.160 9.520 +*N ropt_net_174:8 *C 44.160 10.200 +*N ropt_net_174:9 *C 45.532 10.200 +*N ropt_net_174:10 *C 45.540 10.258 +*N ropt_net_174:11 *C 45.540 11.515 +*N ropt_net_174:12 *C 45.585 11.560 +*N ropt_net_174:13 *C 46.617 11.560 + +*CAP +0 ropt_mt_inst_753:X 1e-06 +1 ropt_mt_inst_783:A 1e-06 +2 ropt_net_174:2 0.0002037899 +3 ropt_net_174:3 0.0002037899 +4 ropt_net_174:4 0.0001313049 +5 ropt_net_174:5 0.0001313049 +6 ropt_net_174:6 0.0002959182 +7 ropt_net_174:7 0.0003672218 +8 ropt_net_174:8 0.0002076328 +9 ropt_net_174:9 0.0001363292 +10 ropt_net_174:10 8.576241e-05 +11 ropt_net_174:11 8.576241e-05 +12 ropt_net_174:12 8.874576e-05 +13 ropt_net_174:13 8.874576e-05 +14 ropt_net_174:4 chany_bottom_in[8] 0.0001510975 +15 ropt_net_174:5 chany_bottom_in[8]:48 0.0001510975 +16 ropt_net_174:4 chany_top_in[4]:10 0.0001387532 +17 ropt_net_174:5 chany_top_in[4]:9 0.0001387532 +18 ropt_net_174:2 chany_top_in[16]:25 9.374234e-05 +19 ropt_net_174:3 chany_top_in[16]:24 9.374234e-05 +20 ropt_net_174:4 chany_top_in[16]:23 7.576664e-07 +21 ropt_net_174:5 chany_top_in[16]:22 7.576664e-07 + +*RES +0 ropt_mt_inst_753:X ropt_net_174:13 0.152 +1 ropt_net_174:2 ropt_mt_inst_783:A 0.152 +2 ropt_net_174:3 ropt_net_174:2 0.003212054 +3 ropt_net_174:4 ropt_net_174:3 0.0045 +4 ropt_net_174:5 ropt_net_174:4 0.004765626 +5 ropt_net_174:6 ropt_net_174:5 0.00341 +6 ropt_net_174:10 ropt_net_174:9 0.00341 +7 ropt_net_174:9 ropt_net_174:8 0.000215025 +8 ropt_net_174:12 ropt_net_174:11 0.0045 +9 ropt_net_174:11 ropt_net_174:10 0.001122768 +10 ropt_net_174:13 ropt_net_174:12 0.0009218751 +11 ropt_net_174:7 ropt_net_174:6 0.0005753583 +12 ropt_net_174:8 ropt_net_174:7 0.0001065333 + +*END + +*D_NET chany_bottom_out[12] 0.0004711886 //LENGTH 3.350 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 23.920 3.740 +*P chany_bottom_out[12] O *L 0.7423 *C 24.380 1.290 +*N chany_bottom_out[12]:2 *C 24.380 2.040 +*N chany_bottom_out[12]:3 *C 23.920 2.040 +*N chany_bottom_out[12]:4 *C 23.920 3.695 +*N chany_bottom_out[12]:5 *C 23.920 3.740 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 chany_bottom_out[12] 5.514024e-05 +2 chany_bottom_out[12]:2 8.504671e-05 +3 chany_bottom_out[12]:3 0.000163211 +4 chany_bottom_out[12]:4 0.0001333046 +5 chany_bottom_out[12]:5 3.348609e-05 + +*RES +0 ropt_mt_inst_788:X chany_bottom_out[12]:5 0.152 +1 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0045 +2 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.001477679 +3 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0004107143 +4 chany_bottom_out[12]:2 chany_bottom_out[12] 0.0006696428 + +*END + +*D_NET ropt_net_185 0.0004870488 //LENGTH 3.780 LUMPCC 0.0001080009 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 73.335 104.040 +*I ropt_mt_inst_801:A I *L 0.001767 *C 72.220 102.000 +*N ropt_net_185:2 *C 72.220 102.000 +*N ropt_net_185:3 *C 72.220 102.045 +*N ropt_net_185:4 *C 72.220 103.995 +*N ropt_net_185:5 *C 72.265 104.040 +*N ropt_net_185:6 *C 73.297 104.040 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_185:2 3.089396e-05 +3 ropt_net_185:3 0.0001254928 +4 ropt_net_185:4 0.0001254928 +5 ropt_net_185:5 4.758418e-05 +6 ropt_net_185:6 4.758418e-05 +7 ropt_net_185:5 chany_bottom_in[6]:6 5.400044e-05 +8 ropt_net_185:6 chany_bottom_in[6]:5 5.400044e-05 + +*RES +0 ropt_mt_inst_768:X ropt_net_185:6 0.152 +1 ropt_net_185:2 ropt_mt_inst_801:A 0.152 +2 ropt_net_185:3 ropt_net_185:2 0.0045 +3 ropt_net_185:5 ropt_net_185:4 0.0045 +4 ropt_net_185:4 ropt_net_185:3 0.001741071 +5 ropt_net_185:6 ropt_net_185:5 0.0009218751 + +*END + +*D_NET ropt_net_167 0.001081878 //LENGTH 7.530 LUMPCC 0.0005137483 DR + +*CONN +*I BUFT_P_98:X O *L 0 *C 29.440 104.040 +*I ropt_mt_inst_772:A I *L 0.001766 *C 31.280 99.280 +*N ropt_net_167:2 *C 31.243 99.280 +*N ropt_net_167:3 *C 30.865 99.280 +*N ropt_net_167:4 *C 30.820 99.325 +*N ropt_net_167:5 *C 30.820 103.995 +*N ropt_net_167:6 *C 30.775 104.040 +*N ropt_net_167:7 *C 29.478 104.040 + +*CAP +0 BUFT_P_98:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_167:2 5.750041e-05 +3 ropt_net_167:3 5.750041e-05 +4 ropt_net_167:4 0.0001185693 +5 ropt_net_167:5 0.0001185693 +6 ropt_net_167:6 0.0001069952 +7 ropt_net_167:7 0.0001069952 +8 ropt_net_167:5 chany_top_in[1] 0.0001325682 +9 ropt_net_167:4 chany_top_in[1]:57 0.0001325682 +10 ropt_net_167:5 chany_top_in[17] 0.0001243059 +11 ropt_net_167:4 chany_top_in[17]:33 0.0001243059 + +*RES +0 BUFT_P_98:X ropt_net_167:7 0.152 +1 ropt_net_167:7 ropt_net_167:6 0.001158482 +2 ropt_net_167:6 ropt_net_167:5 0.0045 +3 ropt_net_167:5 ropt_net_167:4 0.004169643 +4 ropt_net_167:3 ropt_net_167:2 0.0003370536 +5 ropt_net_167:4 ropt_net_167:3 0.0045 +6 ropt_net_167:2 ropt_mt_inst_772:A 0.152 + +*END + +*D_NET chany_bottom_in[13] 0.01790518 //LENGTH 125.865 LUMPCC 0.006663325 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 35.880 1.325 +*I mux_right_ipin_12\/mux_l2_in_1_:A0 I *L 0.001631 *C 17.195 10.200 +*I BUFT_RR_67:A I *L 0.001776 *C 34.960 91.120 +*I mux_right_ipin_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.560 33.660 +*N chany_bottom_in[13]:4 *C 23.210 7.480 +*N chany_bottom_in[13]:5 *C 23.210 34.000 +*N chany_bottom_in[13]:6 *C 25.560 33.660 +*N chany_bottom_in[13]:7 *C 34.922 91.120 +*N chany_bottom_in[13]:8 *C 34.085 91.120 +*N chany_bottom_in[13]:9 *C 34.040 91.075 +*N chany_bottom_in[13]:10 *C 34.040 83.698 +*N chany_bottom_in[13]:11 *C 34.032 83.640 +*N chany_bottom_in[13]:12 *C 33.140 83.640 +*N chany_bottom_in[13]:13 *C 33.120 83.633 +*N chany_bottom_in[13]:14 *C 33.120 34.008 +*N chany_bottom_in[13]:15 *C 33.100 34.000 +*N chany_bottom_in[13]:16 *C 26.228 34.000 +*N chany_bottom_in[13]:17 *C 26.220 34.000 +*N chany_bottom_in[13]:18 *C 26.175 34.000 +*N chany_bottom_in[13]:19 *C 25.560 34.000 +*N chany_bottom_in[13]:20 *C 23.965 34.000 +*N chany_bottom_in[13]:21 *C 23.920 34.000 +*N chany_bottom_in[13]:22 *C 23.918 34.000 +*N chany_bottom_in[13]:23 *C 23.920 33.992 +*N chany_bottom_in[13]:24 *C 17.233 10.200 +*N chany_bottom_in[13]:25 *C 20.655 10.200 +*N chany_bottom_in[13]:26 *C 20.700 10.200 +*N chany_bottom_in[13]:27 *C 20.707 10.200 +*N chany_bottom_in[13]:28 *C 23.900 10.200 +*N chany_bottom_in[13]:29 *C 23.920 10.200 +*N chany_bottom_in[13]:30 *C 23.920 7.488 +*N chany_bottom_in[13]:31 *C 23.918 7.480 +*N chany_bottom_in[13]:32 *C 23.920 7.480 +*N chany_bottom_in[13]:33 *C 23.965 7.480 +*N chany_bottom_in[13]:34 *C 35.375 7.480 +*N chany_bottom_in[13]:35 *C 35.420 7.435 +*N chany_bottom_in[13]:36 *C 35.420 5.440 +*N chany_bottom_in[13]:37 *C 35.880 5.440 + +*CAP +0 chany_bottom_in[13] 0.0002685796 +1 mux_right_ipin_12\/mux_l2_in_1_:A0 1e-06 +2 BUFT_RR_67:A 1e-06 +3 mux_right_ipin_8\/mux_l2_in_1_:A0 1e-06 +4 chany_bottom_in[13]:4 7.35792e-05 +5 chany_bottom_in[13]:5 0.0001061149 +6 chany_bottom_in[13]:6 5.831409e-05 +7 chany_bottom_in[13]:7 7.388189e-05 +8 chany_bottom_in[13]:8 7.388189e-05 +9 chany_bottom_in[13]:9 0.0004292107 +10 chany_bottom_in[13]:10 0.0004292107 +11 chany_bottom_in[13]:11 9.545897e-05 +12 chany_bottom_in[13]:12 9.545897e-05 +13 chany_bottom_in[13]:13 0.00158686 +14 chany_bottom_in[13]:14 0.00158686 +15 chany_bottom_in[13]:15 0.000552365 +16 chany_bottom_in[13]:16 0.000552365 +17 chany_bottom_in[13]:17 4.034191e-05 +18 chany_bottom_in[13]:18 5.221308e-05 +19 chany_bottom_in[13]:19 0.0001966067 +20 chany_bottom_in[13]:20 0.0001146141 +21 chany_bottom_in[13]:21 4.034191e-05 +22 chany_bottom_in[13]:22 0.0001061149 +23 chany_bottom_in[13]:23 0.0008895573 +24 chany_bottom_in[13]:24 0.0002159648 +25 chany_bottom_in[13]:25 0.0002159648 +26 chany_bottom_in[13]:26 3.48018e-05 +27 chany_bottom_in[13]:27 0.0002144288 +28 chany_bottom_in[13]:28 0.0002144288 +29 chany_bottom_in[13]:29 0.0009673467 +30 chany_bottom_in[13]:30 7.778948e-05 +31 chany_bottom_in[13]:31 7.35792e-05 +32 chany_bottom_in[13]:32 3.912325e-05 +33 chany_bottom_in[13]:33 0.0006680756 +34 chany_bottom_in[13]:34 0.0006680756 +35 chany_bottom_in[13]:35 0.0001380187 +36 chany_bottom_in[13]:36 7.938326e-05 +37 chany_bottom_in[13]:37 0.0002099442 +38 chany_bottom_in[13]:14 chany_bottom_in[8]:40 0.0003713421 +39 chany_bottom_in[13]:13 chany_bottom_in[8]:39 0.0003713421 +40 chany_bottom_in[13]:14 chany_bottom_in[11]:29 0.0005461383 +41 chany_bottom_in[13]:14 chany_bottom_in[11]:30 0.0007227471 +42 chany_bottom_in[13]:14 chany_bottom_in[11]:36 2.65503e-05 +43 chany_bottom_in[13]:13 chany_bottom_in[11]:23 0.0005461383 +44 chany_bottom_in[13]:13 chany_bottom_in[11]:29 0.0007227471 +45 chany_bottom_in[13]:13 chany_bottom_in[11]:35 2.65503e-05 +46 chany_bottom_in[13]:23 chany_bottom_in[15]:25 0.0002877676 +47 chany_bottom_in[13]:28 chany_bottom_in[15]:28 6.626737e-06 +48 chany_bottom_in[13]:29 chany_bottom_in[15]:26 0.0002877676 +49 chany_bottom_in[13]:29 chany_bottom_in[15]:25 4.361999e-05 +50 chany_bottom_in[13]:27 chany_bottom_in[15]:27 6.626737e-06 +51 chany_bottom_in[13]:30 chany_bottom_in[15]:26 4.361999e-05 +52 chany_bottom_in[13]:14 chany_top_in[8]:27 0.0005090503 +53 chany_bottom_in[13]:13 chany_top_in[8]:28 0.0005090503 +54 chany_bottom_in[13]:23 chany_top_in[16]:31 0.0004040155 +55 chany_bottom_in[13]:29 chany_top_in[16]:31 3.42699e-05 +56 chany_bottom_in[13]:29 chany_top_in[16]:30 0.0004040155 +57 chany_bottom_in[13]:30 chany_top_in[16]:30 3.42699e-05 +58 chany_bottom_in[13]:36 chany_top_in[16]:25 7.214177e-05 +59 chany_bottom_in[13]:37 chany_top_in[16]:24 7.214177e-05 +60 chany_bottom_in[13]:29 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.417195e-06 +61 chany_bottom_in[13]:25 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.890076e-05 +62 chany_bottom_in[13]:24 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.890076e-05 +63 chany_bottom_in[13]:30 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.417195e-06 +64 chany_bottom_in[13]:33 ropt_net_155:7 7.882214e-05 +65 chany_bottom_in[13]:34 ropt_net_155:6 7.882214e-05 +66 chany_bottom_in[13]:33 ropt_net_179:2 1.271425e-05 +67 chany_bottom_in[13]:33 ropt_net_179:4 0.0001236892 +68 chany_bottom_in[13]:34 ropt_net_179:5 0.0001236892 +69 chany_bottom_in[13]:34 ropt_net_179:3 1.271425e-05 +70 chany_bottom_in[13]:36 ropt_net_179:4 1.684929e-05 +71 chany_bottom_in[13]:37 ropt_net_179:5 1.684929e-05 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:37 0.003674107 +1 chany_bottom_in[13]:18 chany_bottom_in[13]:17 0.0045 +2 chany_bottom_in[13]:17 chany_bottom_in[13]:16 0.00341 +3 chany_bottom_in[13]:16 chany_bottom_in[13]:15 0.001076692 +4 chany_bottom_in[13]:15 chany_bottom_in[13]:14 0.00341 +5 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.007774583 +6 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.000139825 +7 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.00341 +8 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.006587054 +9 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.00341 +10 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.0007477679 +11 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.0045 +12 chany_bottom_in[13]:7 BUFT_RR_67:A 0.152 +13 chany_bottom_in[13]:22 chany_bottom_in[13]:21 0.00341 +14 chany_bottom_in[13]:22 chany_bottom_in[13]:5 0.0001039141 +15 chany_bottom_in[13]:23 chany_bottom_in[13]:22 0.00341 +16 chany_bottom_in[13]:21 chany_bottom_in[13]:20 0.0045 +17 chany_bottom_in[13]:20 chany_bottom_in[13]:19 0.001424107 +18 chany_bottom_in[13]:28 chany_bottom_in[13]:27 0.0005001583 +19 chany_bottom_in[13]:29 chany_bottom_in[13]:28 0.00341 +20 chany_bottom_in[13]:29 chany_bottom_in[13]:23 0.003727491 +21 chany_bottom_in[13]:26 chany_bottom_in[13]:25 0.0045 +22 chany_bottom_in[13]:27 chany_bottom_in[13]:26 0.00341 +23 chany_bottom_in[13]:25 chany_bottom_in[13]:24 0.003055804 +24 chany_bottom_in[13]:24 mux_right_ipin_12\/mux_l2_in_1_:A0 0.152 +25 chany_bottom_in[13]:6 mux_right_ipin_8\/mux_l2_in_1_:A0 0.152 +26 chany_bottom_in[13]:31 chany_bottom_in[13]:30 0.00341 +27 chany_bottom_in[13]:31 chany_bottom_in[13]:4 0.0001039141 +28 chany_bottom_in[13]:30 chany_bottom_in[13]:29 0.0004249583 +29 chany_bottom_in[13]:32 chany_bottom_in[13]:31 0.00341 +30 chany_bottom_in[13]:33 chany_bottom_in[13]:32 0.0045 +31 chany_bottom_in[13]:34 chany_bottom_in[13]:33 0.0101875 +32 chany_bottom_in[13]:35 chany_bottom_in[13]:34 0.0045 +33 chany_bottom_in[13]:19 chany_bottom_in[13]:18 0.0005491071 +34 chany_bottom_in[13]:19 chany_bottom_in[13]:6 0.0003035715 +35 chany_bottom_in[13]:36 chany_bottom_in[13]:35 0.00178125 +36 chany_bottom_in[13]:37 chany_bottom_in[13]:36 0.0004107143 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001381351 //LENGTH 10.660 LUMPCC 0.0004271035 DR + +*CONN +*I mux_right_ipin_0\/mux_l3_in_0_:X O *L 0 *C 30.535 82.960 +*I mux_right_ipin_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 26.585 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 26.623 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 28.015 88.740 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 28.060 88.695 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 28.060 83.005 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 28.105 82.960 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 30.498 82.960 + +*CAP +0 mux_right_ipin_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_0\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.146439e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.146439e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002564109 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002564109 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001682486 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001682486 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_bottom_in[3]:29 7.148513e-05 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_bottom_in[3]:31 7.148513e-05 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:9 4.514414e-05 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:10 4.514414e-05 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:7 6.828423e-06 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:8 6.828423e-06 +14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_1_sram[3]:5 5.512425e-05 +15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_1_sram[3]:6 5.512425e-05 +16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_1_sram[3]:7 3.496981e-05 +17 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[3]:4 3.496981e-05 + +*RES +0 mux_right_ipin_0\/mux_l3_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_0\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001243304 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.005080357 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002136161 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001266745 //LENGTH 11.780 LUMPCC 9.388273e-05 DR + +*CONN +*I mux_right_ipin_5\/mux_l1_in_1_:X O *L 0 *C 47.665 66.300 +*I mux_right_ipin_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 53.075 60.860 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 53.038 60.860 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 48.345 60.860 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 48.300 60.905 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 48.300 66.255 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 48.255 66.300 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 47.703 66.300 + +*CAP +0 mux_right_ipin_5\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_5\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002902797 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002902797 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002350811 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002350811 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.007022e-05 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.007022e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:19 3.166618e-05 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:20 1.527518e-05 +10 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:6 1.527518e-05 +11 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:20 3.166618e-05 + +*RES +0 mux_right_ipin_5\/mux_l1_in_1_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_5\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004189732 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776787 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0] 0.004166146 //LENGTH 35.570 LUMPCC 0.000485185 DR + +*CONN +*I mux_right_ipin_8\/mux_l4_in_0_:X O *L 0 *C 16.735 42.160 +*I mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.800 64.050 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.800 64.050 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 5.980 63.920 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 5.980 63.875 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 5.980 62.617 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 5.978 62.560 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 5.535 62.560 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 5.520 62.553 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 5.520 44.888 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 5.540 44.880 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 16.553 44.880 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 16.560 44.823 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 16.560 42.205 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 16.560 42.160 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 16.735 42.160 + +*CAP +0 mux_right_ipin_8\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.562494e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.053572e-05 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 9.185798e-05 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 9.185798e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.664862e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.664862e-05 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0006972252 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0006972252 +10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0007440688 +11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0007440688 +12 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0001528235 +13 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0001528235 +14 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.510704e-05 +15 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.244506e-05 +16 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 3.642563e-06 +17 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 3.642563e-06 +18 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0002389499 +19 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002389499 + +*RES +0 mux_right_ipin_8\/mux_l4_in_0_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.782609e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001122768 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.499218e-05 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +8 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.002767517 +10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.001725292 +12 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +13 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.002337054 +14 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 9.510871e-05 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00107954 //LENGTH 8.080 LUMPCC 0.0002281031 DR + +*CONN +*I mux_right_ipin_13\/mux_l2_in_1_:X O *L 0 *C 42.145 12.580 +*I mux_right_ipin_13\/mux_l3_in_0_:A0 I *L 0.001631 *C 42.525 17.000 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 42.562 17.000 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 43.655 17.000 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 43.700 16.955 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 43.700 12.625 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 43.655 12.580 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 42.183 12.580 + +*CAP +0 mux_right_ipin_13\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_13\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.44711e-05 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.44711e-05 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001856197 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001856197 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001446276 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001446276 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[11]:7 0.0001140515 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[11]:10 0.0001140515 + +*RES +0 mux_right_ipin_13\/mux_l2_in_1_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001314732 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009754464 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_13\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001203226 //LENGTH 9.485 LUMPCC 0.0003040851 DR + +*CONN +*I mux_right_ipin_3\/mux_l2_in_3_:X O *L 0 *C 25.935 61.880 +*I mux_right_ipin_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 23.290 66.300 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 23.328 66.300 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 26.635 66.300 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 26.680 66.255 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 26.680 61.925 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 26.635 61.880 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 25.973 61.880 + +*CAP +0 mux_right_ipin_3\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_3\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001935636 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001935636 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001807154 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001807154 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.429169e-05 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.429169e-05 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_bottom_in[8]:29 1.853589e-05 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_bottom_in[8]:32 2.629315e-05 +10 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[8]:32 1.853589e-05 +11 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[8]:35 2.629315e-05 +12 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:10 4.452086e-05 +13 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_1_sram[1]:7 4.845349e-06 +14 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_1_sram[1]:12 3.360484e-06 +15 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:11 4.452086e-05 +16 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size8_1_sram[1]:12 4.845349e-06 +17 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size8_1_sram[1]:13 3.360484e-06 +18 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.360476e-06 +19 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.112637e-05 +20 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.360476e-06 +21 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.112637e-05 + +*RES +0 mux_right_ipin_3\/mux_l2_in_3_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_ipin_3\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002953125 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005915179 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0010322 //LENGTH 8.420 LUMPCC 0.0001007912 DR + +*CONN +*I mux_right_ipin_10\/mux_l2_in_0_:X O *L 0 *C 17.195 36.040 +*I mux_right_ipin_10\/mux_l3_in_0_:A1 I *L 0.00198 *C 11.405 34.340 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 11.443 34.340 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 11.915 34.340 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 11.960 34.385 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 11.960 35.995 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 12.005 36.040 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 17.158 36.040 + +*CAP +0 mux_right_ipin_10\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_10\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.608954e-05 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.608954e-05 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001040601 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001040601 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003045547 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003045547 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_4_sram[1]:13 2.071799e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_4_sram[1]:14 2.96776e-05 +10 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size8_4_sram[1]:12 2.96776e-05 +11 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size8_4_sram[1]:14 2.071799e-05 + +*RES +0 mux_right_ipin_10\/mux_l2_in_0_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_10\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000421875 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.004600447 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0] 0.004394134 //LENGTH 32.685 LUMPCC 0.000532931 DR + +*CONN +*I mux_right_ipin_14\/mux_l4_in_0_:X O *L 0 *C 33.755 55.080 +*I mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.685 55.570 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.723 55.473 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 7.315 55.420 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 7.360 55.375 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 7.360 53.778 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 7.368 53.720 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 33.113 53.720 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 33.120 53.778 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 33.120 55.035 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 33.165 55.080 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 33.718 55.080 + +*CAP +0 mux_right_ipin_14\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001079195 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001079195 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001068289 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001068289 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001539535 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.001539535 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0001137451 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001137451 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:10 6.157213e-05 +11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:11 6.157213e-05 +12 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_bottom_in[0]:37 0.0002664655 +13 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_bottom_in[0]:38 0.0002664655 + +*RES +0 mux_right_ipin_14\/mux_l4_in_0_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001421875 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001426339 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.004033383 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0045 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.001122768 +10 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0004933036 + +*END + +*D_NET ropt_net_160 0.0009694129 //LENGTH 7.810 LUMPCC 0.0002678105 DR + +*CONN +*I FTB_16__15:X O *L 0 *C 14.260 105.060 +*I ropt_mt_inst_760:A I *L 0.001766 *C 20.240 104.720 +*N ropt_net_160:2 *C 20.277 104.720 +*N ropt_net_160:3 *C 20.700 104.720 +*N ropt_net_160:4 *C 20.700 105.060 +*N ropt_net_160:5 *C 14.298 105.060 + +*CAP +0 FTB_16__15:X 1e-06 +1 ropt_mt_inst_760:A 1e-06 +2 ropt_net_160:2 1.797178e-05 +3 ropt_net_160:3 4.27686e-05 +4 ropt_net_160:4 0.0003318294 +5 ropt_net_160:5 0.0003070325 +6 ropt_net_160:5 chany_bottom_in[15]:6 0.0001339053 +7 ropt_net_160:4 chany_bottom_in[15]:7 0.0001339053 + +*RES +0 FTB_16__15:X ropt_net_160:5 0.152 +1 ropt_net_160:5 ropt_net_160:4 0.005716518 +2 ropt_net_160:2 ropt_mt_inst_760:A 0.152 +3 ropt_net_160:4 ropt_net_160:3 0.0003035715 +4 ropt_net_160:3 ropt_net_160:2 0.0003772322 + +*END + +*D_NET ropt_net_173 0.002286276 //LENGTH 16.075 LUMPCC 0.00038517 DR + +*CONN +*I ropt_mt_inst_749:X O *L 0 *C 56.775 99.620 +*I ropt_mt_inst_782:A I *L 0.001766 *C 51.060 104.720 +*N ropt_net_173:2 *C 51.023 104.720 +*N ropt_net_173:3 *C 50.185 104.720 +*N ropt_net_173:4 *C 50.140 104.765 +*N ropt_net_173:5 *C 50.140 105.343 +*N ropt_net_173:6 *C 50.148 105.400 +*N ropt_net_173:7 *C 52.433 105.400 +*N ropt_net_173:8 *C 52.440 105.343 +*N ropt_net_173:9 *C 52.440 102.725 +*N ropt_net_173:10 *C 52.485 102.680 +*N ropt_net_173:11 *C 56.535 102.680 +*N ropt_net_173:12 *C 56.580 102.635 +*N ropt_net_173:13 *C 56.580 99.665 +*N ropt_net_173:14 *C 56.580 99.620 +*N ropt_net_173:15 *C 56.775 99.620 + +*CAP +0 ropt_mt_inst_749:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_173:2 9.364048e-05 +3 ropt_net_173:3 9.364048e-05 +4 ropt_net_173:4 5.263921e-05 +5 ropt_net_173:5 5.263921e-05 +6 ropt_net_173:6 5.300368e-05 +7 ropt_net_173:7 5.300368e-05 +8 ropt_net_173:8 0.0001935688 +9 ropt_net_173:9 0.0001935688 +10 ropt_net_173:10 0.000300842 +11 ropt_net_173:11 0.000300842 +12 ropt_net_173:12 0.0001943912 +13 ropt_net_173:13 0.0001943912 +14 ropt_net_173:14 6.283676e-05 +15 ropt_net_173:15 6.00988e-05 +16 ropt_net_173:7 chany_bottom_in[10]:13 6.224134e-05 +17 ropt_net_173:6 chany_bottom_in[10]:12 6.224134e-05 +18 ropt_net_173:7 chany_top_in[12]:34 0.0001220952 +19 ropt_net_173:5 chany_top_in[12]:32 8.248464e-06 +20 ropt_net_173:6 chany_top_in[12]:33 0.0001220952 +21 ropt_net_173:4 chany_top_in[12]:31 8.248464e-06 + +*RES +0 ropt_mt_inst_749:X ropt_net_173:15 0.152 +1 ropt_net_173:15 ropt_net_173:14 0.0001059783 +2 ropt_net_173:14 ropt_net_173:13 0.0045 +3 ropt_net_173:13 ropt_net_173:12 0.002651786 +4 ropt_net_173:11 ropt_net_173:10 0.003616072 +5 ropt_net_173:12 ropt_net_173:11 0.0045 +6 ropt_net_173:10 ropt_net_173:9 0.0045 +7 ropt_net_173:9 ropt_net_173:8 0.002337053 +8 ropt_net_173:8 ropt_net_173:7 0.00341 +9 ropt_net_173:7 ropt_net_173:6 0.0003579833 +10 ropt_net_173:5 ropt_net_173:4 0.000515625 +11 ropt_net_173:6 ropt_net_173:5 0.00341 +12 ropt_net_173:3 ropt_net_173:2 0.0007477679 +13 ropt_net_173:4 ropt_net_173:3 0.0045 +14 ropt_net_173:2 ropt_mt_inst_782:A 0.152 + +*END + +*D_NET ropt_net_181 0.0009362407 //LENGTH 6.700 LUMPCC 0.0001987999 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 55.855 8.840 +*I ropt_mt_inst_792:A I *L 0.001767 *C 53.820 6.800 +*N ropt_net_181:2 *C 53.820 6.800 +*N ropt_net_181:3 *C 53.820 6.755 +*N ropt_net_181:4 *C 53.820 6.165 +*N ropt_net_181:5 *C 53.865 6.120 +*N ropt_net_181:6 *C 54.695 6.120 +*N ropt_net_181:7 *C 54.740 6.165 +*N ropt_net_181:8 *C 54.740 8.795 +*N ropt_net_181:9 *C 54.785 8.840 +*N ropt_net_181:10 *C 55.818 8.840 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_181:2 3.916886e-05 +3 ropt_net_181:3 4.062334e-05 +4 ropt_net_181:4 4.062334e-05 +5 ropt_net_181:5 8.357821e-05 +6 ropt_net_181:6 8.357821e-05 +7 ropt_net_181:7 0.0001290042 +8 ropt_net_181:8 0.0001290042 +9 ropt_net_181:9 9.493025e-05 +10 ropt_net_181:10 9.493025e-05 +11 ropt_net_181:3 chany_top_in[2]:38 2.478509e-05 +12 ropt_net_181:4 chany_top_in[2]:35 2.478509e-05 +13 ropt_net_181:7 chany_top_in[2]:35 7.461484e-05 +14 ropt_net_181:8 chany_top_in[2]:38 7.461484e-05 + +*RES +0 ropt_mt_inst_757:X ropt_net_181:10 0.152 +1 ropt_net_181:2 ropt_mt_inst_792:A 0.152 +2 ropt_net_181:3 ropt_net_181:2 0.0045 +3 ropt_net_181:5 ropt_net_181:4 0.0045 +4 ropt_net_181:4 ropt_net_181:3 0.0005267857 +5 ropt_net_181:6 ropt_net_181:5 0.0007410714 +6 ropt_net_181:7 ropt_net_181:6 0.0045 +7 ropt_net_181:9 ropt_net_181:8 0.0045 +8 ropt_net_181:8 ropt_net_181:7 0.002348214 +9 ropt_net_181:10 ropt_net_181:9 0.0009218751 + +*END + +*D_NET chany_top_out[6] 0.001850468 //LENGTH 13.675 LUMPCC 0.0002435829 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 73.140 101.660 +*P chany_top_out[6] O *L 0.7423 *C 65.780 107.510 +*N chany_top_out[6]:2 *C 65.780 101.705 +*N chany_top_out[6]:3 *C 65.825 101.660 +*N chany_top_out[6]:4 *C 73.103 101.660 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 chany_top_out[6] 0.0003867645 +2 chany_top_out[6]:2 0.0003867645 +3 chany_top_out[6]:3 0.0004161783 +4 chany_top_out[6]:4 0.0004161783 +5 chany_top_out[6]:4 ropt_net_182:10 0.0001217915 +6 chany_top_out[6]:3 ropt_net_182:9 0.0001217915 + +*RES +0 ropt_mt_inst_801:X chany_top_out[6]:4 0.152 +1 chany_top_out[6]:4 chany_top_out[6]:3 0.006497768 +2 chany_top_out[6]:3 chany_top_out[6]:2 0.0045 +3 chany_top_out[6]:2 chany_top_out[6] 0.005183036 + +*END + +*D_NET ropt_net_145 0.003864901 //LENGTH 25.635 LUMPCC 0.001016133 DR + +*CONN +*I BUFT_P_110:X O *L 0 *C 47.380 98.600 +*I ropt_mt_inst_744:A I *L 0.001766 *C 67.620 102.000 +*N ropt_net_145:2 *C 67.583 102.000 +*N ropt_net_145:3 *C 64.445 102.000 +*N ropt_net_145:4 *C 64.400 101.955 +*N ropt_net_145:5 *C 64.400 101.378 +*N ropt_net_145:6 *C 64.392 101.320 +*N ropt_net_145:7 *C 52.460 101.320 +*N ropt_net_145:8 *C 52.440 101.312 +*N ropt_net_145:9 *C 52.440 98.608 +*N ropt_net_145:10 *C 52.420 98.600 +*N ropt_net_145:11 *C 48.768 98.600 +*N ropt_net_145:12 *C 48.760 98.600 +*N ropt_net_145:13 *C 48.715 98.600 +*N ropt_net_145:14 *C 47.418 98.600 + +*CAP +0 BUFT_P_110:X 1e-06 +1 ropt_mt_inst_744:A 1e-06 +2 ropt_net_145:2 0.0001784922 +3 ropt_net_145:3 0.0001784922 +4 ropt_net_145:4 6.318632e-05 +5 ropt_net_145:5 6.318632e-05 +6 ropt_net_145:6 0.0006915732 +7 ropt_net_145:7 0.0006915732 +8 ropt_net_145:8 0.0001846871 +9 ropt_net_145:9 0.0001846871 +10 ropt_net_145:10 0.0001709327 +11 ropt_net_145:11 0.0001709327 +12 ropt_net_145:12 3.670884e-05 +13 ropt_net_145:13 0.0001161576 +14 ropt_net_145:14 0.0001161576 +15 ropt_net_145:7 chany_bottom_in[11]:10 0.0001540829 +16 ropt_net_145:6 chany_bottom_in[11]:9 0.0001540829 +17 ropt_net_145:11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002198464 +18 ropt_net_145:10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002198464 +19 ropt_net_145:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.112678e-05 +20 ropt_net_145:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_7_X[0]:6 3.112678e-05 +21 ropt_net_145:3 ropt_net_175:4 0.0001030106 +22 ropt_net_145:2 ropt_net_175:5 0.0001030106 + +*RES +0 BUFT_P_110:X ropt_net_145:14 0.152 +1 ropt_net_145:14 ropt_net_145:13 0.001158482 +2 ropt_net_145:13 ropt_net_145:12 0.0045 +3 ropt_net_145:12 ropt_net_145:11 0.00341 +4 ropt_net_145:11 ropt_net_145:10 0.000572225 +5 ropt_net_145:10 ropt_net_145:9 0.00341 +6 ropt_net_145:9 ropt_net_145:8 0.0004237833 +7 ropt_net_145:7 ropt_net_145:6 0.001869425 +8 ropt_net_145:8 ropt_net_145:7 0.00341 +9 ropt_net_145:5 ropt_net_145:4 0.000515625 +10 ropt_net_145:6 ropt_net_145:5 0.00341 +11 ropt_net_145:3 ropt_net_145:2 0.002801339 +12 ropt_net_145:4 ropt_net_145:3 0.0045 +13 ropt_net_145:2 ropt_mt_inst_744:A 0.152 + +*END + +*D_NET chany_bottom_in[14] 0.02160926 //LENGTH 176.755 LUMPCC 0.002672357 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 69.000 1.290 +*I mux_right_ipin_13\/mux_l2_in_1_:A0 I *L 0.001631 *C 40.195 11.900 +*I ropt_mt_inst_747:A I *L 0.001766 *C 35.880 99.280 +*I mux_right_ipin_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 74.350 31.620 +*N chany_bottom_in[14]:4 *C 74.388 31.620 +*N chany_bottom_in[14]:5 *C 76.315 31.620 +*N chany_bottom_in[14]:6 *C 76.360 31.575 +*N chany_bottom_in[14]:7 *C 40.080 90.440 +*N chany_bottom_in[14]:8 *C 35.918 99.280 +*N chany_bottom_in[14]:9 *C 37.675 99.280 +*N chany_bottom_in[14]:10 *C 37.720 99.325 +*N chany_bottom_in[14]:11 *C 37.720 99.960 +*N chany_bottom_in[14]:12 *C 39.100 99.960 +*N chany_bottom_in[14]:13 *C 39.100 91.178 +*N chany_bottom_in[14]:14 *C 39.108 91.120 +*N chany_bottom_in[14]:15 *C 40.473 91.120 +*N chany_bottom_in[14]:16 *C 40.480 91.062 +*N chany_bottom_in[14]:17 *C 40.480 90.498 +*N chany_bottom_in[14]:18 *C 40.480 90.440 +*N chany_bottom_in[14]:19 *C 40.480 90.433 +*N chany_bottom_in[14]:20 *C 40.480 73.800 +*N chany_bottom_in[14]:21 *C 40.233 11.900 +*N chany_bottom_in[14]:22 *C 41.815 11.900 +*N chany_bottom_in[14]:23 *C 41.860 11.900 +*N chany_bottom_in[14]:24 *C 41.860 12.240 +*N chany_bottom_in[14]:25 *C 41.852 12.240 +*N chany_bottom_in[14]:26 *C 40.500 12.240 +*N chany_bottom_in[14]:27 *C 40.480 12.248 +*N chany_bottom_in[14]:28 *C 40.480 23.800 +*N chany_bottom_in[14]:29 *C 40.500 23.800 +*N chany_bottom_in[14]:30 *C 76.353 23.800 +*N chany_bottom_in[14]:31 *C 76.360 23.800 +*N chany_bottom_in[14]:32 *C 76.360 12.285 +*N chany_bottom_in[14]:33 *C 76.315 12.240 +*N chany_bottom_in[14]:34 *C 69.045 12.240 +*N chany_bottom_in[14]:35 *C 69.000 12.195 + +*CAP +0 chany_bottom_in[14] 0.0005633066 +1 mux_right_ipin_13\/mux_l2_in_1_:A0 1e-06 +2 ropt_mt_inst_747:A 1e-06 +3 mux_right_ipin_9\/mux_l2_in_2_:A0 1e-06 +4 chany_bottom_in[14]:4 0.0001300959 +5 chany_bottom_in[14]:5 0.0001300959 +6 chany_bottom_in[14]:6 0.0004067902 +7 chany_bottom_in[14]:7 2.84331e-05 +8 chany_bottom_in[14]:8 0.0001628399 +9 chany_bottom_in[14]:9 0.0001628399 +10 chany_bottom_in[14]:10 3.21079e-05 +11 chany_bottom_in[14]:11 0.0001145939 +12 chany_bottom_in[14]:12 0.0005421409 +13 chany_bottom_in[14]:13 0.000459655 +14 chany_bottom_in[14]:14 0.0001267032 +15 chany_bottom_in[14]:15 0.0001267032 +16 chany_bottom_in[14]:16 5.736878e-05 +17 chany_bottom_in[14]:17 5.736878e-05 +18 chany_bottom_in[14]:18 2.84331e-05 +19 chany_bottom_in[14]:19 0.000754514 +20 chany_bottom_in[14]:20 0.003269305 +21 chany_bottom_in[14]:21 7.185627e-05 +22 chany_bottom_in[14]:22 7.185627e-05 +23 chany_bottom_in[14]:23 5.623644e-05 +24 chany_bottom_in[14]:24 6.044745e-05 +25 chany_bottom_in[14]:25 0.0001389525 +26 chany_bottom_in[14]:26 0.0001389525 +27 chany_bottom_in[14]:27 0.0006705194 +28 chany_bottom_in[14]:28 0.003185311 +29 chany_bottom_in[14]:29 0.002270829 +30 chany_bottom_in[14]:30 0.002270829 +31 chany_bottom_in[14]:31 0.0009694024 +32 chany_bottom_in[14]:32 0.0005361367 +33 chany_bottom_in[14]:33 0.0003879848 +34 chany_bottom_in[14]:34 0.0003879848 +35 chany_bottom_in[14]:35 0.0005633066 +36 chany_bottom_in[14]:27 chany_top_in[8]:13 3.171069e-05 +37 chany_bottom_in[14]:28 chany_top_in[8]:13 0.0004572163 +38 chany_bottom_in[14]:28 chany_top_in[8]:14 3.171069e-05 +39 chany_bottom_in[14]:20 chany_top_in[8]:14 0.0004572163 +40 chany_bottom_in[14]:28 chany_top_in[19]:33 0.0001811995 +41 chany_bottom_in[14]:19 chany_top_in[19]:34 0.0003432025 +42 chany_bottom_in[14]:20 chany_top_in[19]:33 0.0003432025 +43 chany_bottom_in[14]:20 chany_top_in[19]:34 0.0001811995 +44 chany_bottom_in[14]:29 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001591702 +45 chany_bottom_in[14]:30 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001591702 +46 chany_bottom_in[14]:22 ropt_net_154:3 7.108542e-05 +47 chany_bottom_in[14]:21 ropt_net_154:4 7.108542e-05 +48 chany_bottom_in[14]:13 ropt_net_168:5 1.564366e-06 +49 chany_bottom_in[14]:13 ropt_net_168:8 6.758175e-05 +50 chany_bottom_in[14]:10 ropt_net_168:5 2.274636e-05 +51 chany_bottom_in[14]:10 ropt_net_168:8 7.014565e-07 +52 chany_bottom_in[14]:11 ropt_net_168:4 2.274636e-05 +53 chany_bottom_in[14]:11 ropt_net_168:9 7.014565e-07 +54 chany_bottom_in[14]:12 ropt_net_168:4 1.564366e-06 +55 chany_bottom_in[14]:12 ropt_net_168:9 6.758175e-05 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:35 0.009736607 +1 chany_bottom_in[14]:26 chany_bottom_in[14]:25 0.0002118917 +2 chany_bottom_in[14]:27 chany_bottom_in[14]:26 0.00341 +3 chany_bottom_in[14]:24 chany_bottom_in[14]:23 0.0001634615 +4 chany_bottom_in[14]:25 chany_bottom_in[14]:24 0.00341 +5 chany_bottom_in[14]:22 chany_bottom_in[14]:21 0.001412947 +6 chany_bottom_in[14]:23 chany_bottom_in[14]:22 0.0045 +7 chany_bottom_in[14]:21 mux_right_ipin_13\/mux_l2_in_1_:A0 0.152 +8 chany_bottom_in[14]:29 chany_bottom_in[14]:28 0.00341 +9 chany_bottom_in[14]:28 chany_bottom_in[14]:27 0.001809892 +10 chany_bottom_in[14]:28 chany_bottom_in[14]:20 0.007833333 +11 chany_bottom_in[14]:31 chany_bottom_in[14]:30 0.00341 +12 chany_bottom_in[14]:31 chany_bottom_in[14]:6 0.006941965 +13 chany_bottom_in[14]:30 chany_bottom_in[14]:29 0.005616892 +14 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.001720982 +15 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.0045 +16 chany_bottom_in[14]:4 mux_right_ipin_9\/mux_l2_in_2_:A0 0.152 +17 chany_bottom_in[14]:33 chany_bottom_in[14]:32 0.0045 +18 chany_bottom_in[14]:32 chany_bottom_in[14]:31 0.01028125 +19 chany_bottom_in[14]:34 chany_bottom_in[14]:33 0.006491072 +20 chany_bottom_in[14]:35 chany_bottom_in[14]:34 0.0045 +21 chany_bottom_in[14]:18 chany_bottom_in[14]:17 0.00341 +22 chany_bottom_in[14]:18 chany_bottom_in[14]:7 5.696969e-05 +23 chany_bottom_in[14]:19 chany_bottom_in[14]:18 0.00341 +24 chany_bottom_in[14]:17 chany_bottom_in[14]:16 0.0005044643 +25 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.00341 +26 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.00021385 +27 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.007841518 +28 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.00341 +29 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.001569197 +30 chany_bottom_in[14]:10 chany_bottom_in[14]:9 0.0045 +31 chany_bottom_in[14]:8 ropt_mt_inst_747:A 0.152 +32 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.0005669643 +33 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.001232143 +34 chany_bottom_in[14]:20 chany_bottom_in[14]:19 0.002605758 + +*END + +*D_NET left_grid_pin_1_[0] 0.0008572835 //LENGTH 6.870 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 5.925 93.840 +*P left_grid_pin_1_[0] O *L 0.7423 *C 1.230 95.200 +*N left_grid_pin_1_[0]:2 *C 5.513 95.200 +*N left_grid_pin_1_[0]:3 *C 5.520 95.142 +*N left_grid_pin_1_[0]:4 *C 5.520 93.885 +*N left_grid_pin_1_[0]:5 *C 5.543 93.840 +*N left_grid_pin_1_[0]:6 *C 5.910 93.840 + +*CAP +0 mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_1_[0] 0.0002810816 +2 left_grid_pin_1_[0]:2 0.0002810816 +3 left_grid_pin_1_[0]:3 9.646347e-05 +4 left_grid_pin_1_[0]:4 9.646347e-05 +5 left_grid_pin_1_[0]:5 5.059673e-05 +6 left_grid_pin_1_[0]:6 5.059673e-05 + +*RES +0 mux_right_ipin_1\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_1_[0]:6 0.152 +1 left_grid_pin_1_[0]:6 left_grid_pin_1_[0]:5 0.0001997283 +2 left_grid_pin_1_[0]:5 left_grid_pin_1_[0]:4 0.0045 +3 left_grid_pin_1_[0]:4 left_grid_pin_1_[0]:3 0.001122768 +4 left_grid_pin_1_[0]:3 left_grid_pin_1_[0]:2 0.00341 +5 left_grid_pin_1_[0]:2 left_grid_pin_1_[0] 0.000670925 + +*END + +*D_NET left_grid_pin_4_[0] 0.002510926 //LENGTH 21.775 LUMPCC 0.0008614815 DR + +*CONN +*I mux_right_ipin_4\/mux_l4_in_0_:X O *L 0 *C 7.120 85.680 +*P left_grid_pin_4_[0] O *L 0.7423 *C 1.298 100.640 +*N left_grid_pin_4_[0]:2 *C 1.380 100.640 +*N left_grid_pin_4_[0]:3 *C 1.380 100.640 +*N left_grid_pin_4_[0]:4 *C 1.840 100.640 +*N left_grid_pin_4_[0]:5 *C 1.840 85.725 +*N left_grid_pin_4_[0]:6 *C 1.885 85.680 +*N left_grid_pin_4_[0]:7 *C 7.083 85.680 + +*CAP +0 mux_right_ipin_4\/mux_l4_in_0_:X 1e-06 +1 left_grid_pin_4_[0] 1.185711e-05 +2 left_grid_pin_4_[0]:2 1.185711e-05 +3 left_grid_pin_4_[0]:3 5.581168e-05 +4 left_grid_pin_4_[0]:4 0.0005108317 +5 left_grid_pin_4_[0]:5 0.0004838147 +6 left_grid_pin_4_[0]:6 0.0002871361 +7 left_grid_pin_4_[0]:7 0.0002871361 +8 left_grid_pin_4_[0] left_grid_pin_5_[0]:5 1.471442e-05 +9 left_grid_pin_4_[0]:5 left_grid_pin_5_[0]:5 0.0004146107 +10 left_grid_pin_4_[0]:3 left_grid_pin_5_[0]:3 1.415645e-06 +11 left_grid_pin_4_[0]:2 left_grid_pin_5_[0]:4 1.471442e-05 +12 left_grid_pin_4_[0]:4 left_grid_pin_5_[0]:4 0.0004160263 + +*RES +0 mux_right_ipin_4\/mux_l4_in_0_:X left_grid_pin_4_[0]:7 0.152 +1 left_grid_pin_4_[0]:7 left_grid_pin_4_[0]:6 0.004640625 +2 left_grid_pin_4_[0]:6 left_grid_pin_4_[0]:5 0.0045 +3 left_grid_pin_4_[0]:5 left_grid_pin_4_[0]:4 0.01331696 +4 left_grid_pin_4_[0]:3 left_grid_pin_4_[0]:2 0.00341 +5 left_grid_pin_4_[0]:2 left_grid_pin_4_[0] 2.35e-05 +6 left_grid_pin_4_[0]:4 left_grid_pin_4_[0]:3 0.0004107143 + +*END + +*D_NET left_grid_pin_12_[0] 0.001564575 //LENGTH 13.800 LUMPCC 0.0001101174 DR + +*CONN +*I mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.385 28.560 +*P left_grid_pin_12_[0] O *L 0.7423 *C 1.230 35.360 +*N left_grid_pin_12_[0]:2 *C 6.893 35.360 +*N left_grid_pin_12_[0]:3 *C 6.900 35.303 +*N left_grid_pin_12_[0]:4 *C 6.900 28.605 +*N left_grid_pin_12_[0]:5 *C 6.855 28.560 +*N left_grid_pin_12_[0]:6 *C 6.423 28.560 + +*CAP +0 mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_12_[0] 0.0003327382 +2 left_grid_pin_12_[0]:2 0.0003327382 +3 left_grid_pin_12_[0]:3 0.0003475053 +4 left_grid_pin_12_[0]:4 0.0003475053 +5 left_grid_pin_12_[0]:5 4.648521e-05 +6 left_grid_pin_12_[0]:6 4.648521e-05 +7 left_grid_pin_12_[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.505869e-05 +8 left_grid_pin_12_[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.505869e-05 + +*RES +0 mux_right_ipin_12\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_12_[0]:6 0.152 +1 left_grid_pin_12_[0]:6 left_grid_pin_12_[0]:5 0.0003861607 +2 left_grid_pin_12_[0]:5 left_grid_pin_12_[0]:4 0.0045 +3 left_grid_pin_12_[0]:4 left_grid_pin_12_[0]:3 0.00597991 +4 left_grid_pin_12_[0]:3 left_grid_pin_12_[0]:2 0.00341 +5 left_grid_pin_12_[0]:2 left_grid_pin_12_[0] 0.0008871249 + +*END + +*D_NET left_grid_pin_14_[0] 0.0005255525 //LENGTH 3.645 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.085 55.420 +*P left_grid_pin_14_[0] O *L 0.7423 *C 1.230 55.760 +*N left_grid_pin_14_[0]:2 *C 3.673 55.760 +*N left_grid_pin_14_[0]:3 *C 3.680 55.760 +*N left_grid_pin_14_[0]:4 *C 3.680 55.420 +*N left_grid_pin_14_[0]:5 *C 3.703 55.420 +*N left_grid_pin_14_[0]:6 *C 4.070 55.420 + +*CAP +0 mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 left_grid_pin_14_[0] 0.0001693121 +2 left_grid_pin_14_[0]:2 0.0001693121 +3 left_grid_pin_14_[0]:3 5.34529e-05 +4 left_grid_pin_14_[0]:4 4.97561e-05 +5 left_grid_pin_14_[0]:5 4.135965e-05 +6 left_grid_pin_14_[0]:6 4.135965e-05 + +*RES +0 mux_right_ipin_14\/sky130_fd_sc_hd__buf_4_0_:X left_grid_pin_14_[0]:6 0.152 +1 left_grid_pin_14_[0]:6 left_grid_pin_14_[0]:5 0.0001997283 +2 left_grid_pin_14_[0]:5 left_grid_pin_14_[0]:4 0.0045 +3 left_grid_pin_14_[0]:4 left_grid_pin_14_[0]:3 0.0001634615 +4 left_grid_pin_14_[0]:3 left_grid_pin_14_[0]:2 0.00341 +5 left_grid_pin_14_[0]:2 left_grid_pin_14_[0] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.002509661 //LENGTH 22.188 LUMPCC 0.000456383 DR + +*CONN +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 79.885 53.380 +*I mux_left_ipin_0\/mux_l3_in_0_:S I *L 0.00357 *C 79.020 45.560 +*I mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 74.695 58.820 +*I mux_left_ipin_0\/mux_l3_in_1_:S I *L 0.00357 *C 74.420 61.200 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 74.420 61.200 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 74.520 61.155 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 74.520 58.865 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 74.520 58.820 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 74.733 58.820 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 79.075 58.820 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 79.120 58.775 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 79.020 45.560 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 79.120 45.605 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 79.120 53.380 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 79.165 53.380 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 79.848 53.380 + +*CAP +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_ipin_0\/mux_l3_in_0_:S 1e-06 +2 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_ipin_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 2.935352e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 0.0001430028 +6 mux_tree_tapbuf_size10_0_sram[2]:6 0.0001430028 +7 mux_tree_tapbuf_size10_0_sram[2]:7 5.589609e-05 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0002964831 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.000274695 +10 mux_tree_tapbuf_size10_0_sram[2]:10 0.0002055505 +11 mux_tree_tapbuf_size10_0_sram[2]:11 2.669645e-05 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0002612176 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0004915457 +14 mux_tree_tapbuf_size10_0_sram[2]:14 6.091734e-05 +15 mux_tree_tapbuf_size10_0_sram[2]:15 6.091734e-05 +16 mux_tree_tapbuf_size10_0_sram[2]:10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.699718e-05 +17 mux_tree_tapbuf_size10_0_sram[2]:13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.883255e-05 +18 mux_tree_tapbuf_size10_0_sram[2]:13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.699718e-05 +19 mux_tree_tapbuf_size10_0_sram[2]:13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 6.236177e-05 +20 mux_tree_tapbuf_size10_0_sram[2]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.883255e-05 +21 mux_tree_tapbuf_size10_0_sram[2]:12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 6.236177e-05 + +*RES +0 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:15 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:4 mux_left_ipin_0\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.002044643 +5 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.003877232 +6 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.0045 +7 mux_tree_tapbuf_size10_0_sram[2]:8 mem_left_ipin_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.0001154892 +9 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +10 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.006941964 +11 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:10 0.004816965 +12 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.000609375 +13 mux_tree_tapbuf_size10_0_sram[2]:11 mux_left_ipin_0\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.009535191 //LENGTH 70.820 LUMPCC 0.001645341 DR + +*CONN +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 78.505 66.640 +*I mux_right_ipin_0\/mux_l1_in_2_:S I *L 0.00357 *C 37.620 72.375 +*I mux_right_ipin_0\/mux_l1_in_1_:S I *L 0.00357 *C 29.340 79.900 +*I mux_right_ipin_0\/mux_l1_in_0_:S I *L 0.00357 *C 31.180 77.520 +*I mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.515 75.140 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 36.553 75.140 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 37.675 75.140 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 37.720 75.095 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 31.180 77.520 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 29.378 79.900 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 31.235 79.900 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 31.280 79.855 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 31.280 77.225 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 31.280 77.180 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 33.075 77.180 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 33.120 77.135 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 33.120 72.805 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 33.165 72.760 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 37.620 72.760 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 37.620 72.375 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 37.720 72.080 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 37.720 72.080 +*N mux_tree_tapbuf_size10_1_sram[0]:22 *C 37.720 71.445 +*N mux_tree_tapbuf_size10_1_sram[0]:23 *C 37.765 71.400 +*N mux_tree_tapbuf_size10_1_sram[0]:24 *C 49.175 71.400 +*N mux_tree_tapbuf_size10_1_sram[0]:25 *C 49.220 71.355 +*N mux_tree_tapbuf_size10_1_sram[0]:26 *C 49.220 67.377 +*N mux_tree_tapbuf_size10_1_sram[0]:27 *C 49.227 67.320 +*N mux_tree_tapbuf_size10_1_sram[0]:28 *C 78.193 67.320 +*N mux_tree_tapbuf_size10_1_sram[0]:29 *C 78.200 67.263 +*N mux_tree_tapbuf_size10_1_sram[0]:30 *C 78.200 66.685 +*N mux_tree_tapbuf_size10_1_sram[0]:31 *C 78.200 66.640 +*N mux_tree_tapbuf_size10_1_sram[0]:32 *C 78.505 66.640 + +*CAP +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_ipin_0\/mux_l1_in_2_:S 1e-06 +2 mux_right_ipin_0\/mux_l1_in_1_:S 1e-06 +3 mux_right_ipin_0\/mux_l1_in_0_:S 1e-06 +4 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 8.867787e-05 +6 mux_tree_tapbuf_size10_1_sram[0]:6 8.867787e-05 +7 mux_tree_tapbuf_size10_1_sram[0]:7 0.0001785094 +8 mux_tree_tapbuf_size10_1_sram[0]:8 6.996271e-05 +9 mux_tree_tapbuf_size10_1_sram[0]:9 0.0001027959 +10 mux_tree_tapbuf_size10_1_sram[0]:10 0.0001027959 +11 mux_tree_tapbuf_size10_1_sram[0]:11 0.0001677712 +12 mux_tree_tapbuf_size10_1_sram[0]:12 0.0001677712 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0001673312 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.0001292782 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0002132184 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0002132184 +17 mux_tree_tapbuf_size10_1_sram[0]:17 0.0003010136 +18 mux_tree_tapbuf_size10_1_sram[0]:18 0.000323292 +19 mux_tree_tapbuf_size10_1_sram[0]:19 6.87206e-05 +20 mux_tree_tapbuf_size10_1_sram[0]:20 5.057671e-05 +21 mux_tree_tapbuf_size10_1_sram[0]:21 0.0002586742 +22 mux_tree_tapbuf_size10_1_sram[0]:22 4.654434e-05 +23 mux_tree_tapbuf_size10_1_sram[0]:23 0.0006250299 +24 mux_tree_tapbuf_size10_1_sram[0]:24 0.0006250299 +25 mux_tree_tapbuf_size10_1_sram[0]:25 0.0002308684 +26 mux_tree_tapbuf_size10_1_sram[0]:26 0.0002308684 +27 mux_tree_tapbuf_size10_1_sram[0]:27 0.001616079 +28 mux_tree_tapbuf_size10_1_sram[0]:28 0.001616079 +29 mux_tree_tapbuf_size10_1_sram[0]:29 4.926357e-05 +30 mux_tree_tapbuf_size10_1_sram[0]:30 4.926357e-05 +31 mux_tree_tapbuf_size10_1_sram[0]:31 5.431786e-05 +32 mux_tree_tapbuf_size10_1_sram[0]:32 4.922033e-05 +33 mux_tree_tapbuf_size10_1_sram[0]:19 chany_bottom_in[5]:7 4.770193e-06 +34 mux_tree_tapbuf_size10_1_sram[0]:19 chany_bottom_in[5]:13 1.795837e-06 +35 mux_tree_tapbuf_size10_1_sram[0]:17 chany_bottom_in[5]:12 2.687069e-05 +36 mux_tree_tapbuf_size10_1_sram[0]:17 chany_bottom_in[5]:13 3.352502e-06 +37 mux_tree_tapbuf_size10_1_sram[0]:20 chany_bottom_in[5]:13 4.770193e-06 +38 mux_tree_tapbuf_size10_1_sram[0]:23 chany_bottom_in[5]:13 0.0002462037 +39 mux_tree_tapbuf_size10_1_sram[0]:24 chany_bottom_in[5]:14 0.0002462037 +40 mux_tree_tapbuf_size10_1_sram[0]:18 chany_bottom_in[5]:7 1.795837e-06 +41 mux_tree_tapbuf_size10_1_sram[0]:18 chany_bottom_in[5]:13 2.687069e-05 +42 mux_tree_tapbuf_size10_1_sram[0]:18 chany_bottom_in[5]:14 3.352502e-06 +43 mux_tree_tapbuf_size10_1_sram[0]:16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.578079e-06 +44 mux_tree_tapbuf_size10_1_sram[0]:15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.578079e-06 +45 mux_tree_tapbuf_size10_1_sram[0]:10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.959774e-05 +46 mux_tree_tapbuf_size10_1_sram[0]:9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.959774e-05 +47 mux_tree_tapbuf_size10_1_sram[0]:16 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.345988e-05 +48 mux_tree_tapbuf_size10_1_sram[0]:15 mux_right_ipin_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.345988e-05 +49 mux_tree_tapbuf_size10_1_sram[0]:27 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 8.829226e-05 +50 mux_tree_tapbuf_size10_1_sram[0]:27 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0003347498 +51 mux_tree_tapbuf_size10_1_sram[0]:28 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0003347498 +52 mux_tree_tapbuf_size10_1_sram[0]:28 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 8.829226e-05 + +*RES +0 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:32 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:19 mux_right_ipin_0\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 0.00034375 +3 mux_tree_tapbuf_size10_1_sram[0]:17 mux_tree_tapbuf_size10_1_sram[0]:16 0.0045 +4 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:15 0.003866072 +5 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:13 0.001602679 +6 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.0045 +7 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.0045 +8 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:8 0.0001847826 +9 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.002348215 +10 mux_tree_tapbuf_size10_1_sram[0]:10 mux_tree_tapbuf_size10_1_sram[0]:9 0.001658482 +11 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.0045 +12 mux_tree_tapbuf_size10_1_sram[0]:9 mux_right_ipin_0\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.0002633929 +14 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.0045 +15 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:7 0.002691964 +16 mux_tree_tapbuf_size10_1_sram[0]:23 mux_tree_tapbuf_size10_1_sram[0]:22 0.0045 +17 mux_tree_tapbuf_size10_1_sram[0]:22 mux_tree_tapbuf_size10_1_sram[0]:21 0.0005669643 +18 mux_tree_tapbuf_size10_1_sram[0]:24 mux_tree_tapbuf_size10_1_sram[0]:23 0.0101875 +19 mux_tree_tapbuf_size10_1_sram[0]:25 mux_tree_tapbuf_size10_1_sram[0]:24 0.0045 +20 mux_tree_tapbuf_size10_1_sram[0]:26 mux_tree_tapbuf_size10_1_sram[0]:25 0.003551339 +21 mux_tree_tapbuf_size10_1_sram[0]:27 mux_tree_tapbuf_size10_1_sram[0]:26 0.00341 +22 mux_tree_tapbuf_size10_1_sram[0]:29 mux_tree_tapbuf_size10_1_sram[0]:28 0.00341 +23 mux_tree_tapbuf_size10_1_sram[0]:28 mux_tree_tapbuf_size10_1_sram[0]:27 0.00453785 +24 mux_tree_tapbuf_size10_1_sram[0]:31 mux_tree_tapbuf_size10_1_sram[0]:30 0.0045 +25 mux_tree_tapbuf_size10_1_sram[0]:30 mux_tree_tapbuf_size10_1_sram[0]:29 0.0005156251 +26 mux_tree_tapbuf_size10_1_sram[0]:32 mux_tree_tapbuf_size10_1_sram[0]:31 0.0001657609 +27 mux_tree_tapbuf_size10_1_sram[0]:6 mux_tree_tapbuf_size10_1_sram[0]:5 0.001002232 +28 mux_tree_tapbuf_size10_1_sram[0]:7 mux_tree_tapbuf_size10_1_sram[0]:6 0.0045 +29 mux_tree_tapbuf_size10_1_sram[0]:5 mem_right_ipin_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +30 mux_tree_tapbuf_size10_1_sram[0]:8 mux_right_ipin_0\/mux_l1_in_0_:S 0.152 +31 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.003977679 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[3] 0.00185432 //LENGTH 14.040 LUMPCC 0.0002653771 DR + +*CONN +*I mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 12.725 75.140 +*I mem_right_ipin_4\/FTB_4__43:A I *L 0.001746 *C 12.420 72.080 +*I mux_right_ipin_4\/mux_l4_in_0_:S I *L 0.008363 *C 12.420 85.510 +*N mux_tree_tapbuf_size10_3_sram[3]:3 *C 12.420 85.465 +*N mux_tree_tapbuf_size10_3_sram[3]:4 *C 12.420 72.080 +*N mux_tree_tapbuf_size10_3_sram[3]:5 *C 12.420 72.125 +*N mux_tree_tapbuf_size10_3_sram[3]:6 *C 12.420 75.140 +*N mux_tree_tapbuf_size10_3_sram[3]:7 *C 12.420 75.140 +*N mux_tree_tapbuf_size10_3_sram[3]:8 *C 12.725 75.140 + +*CAP +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_4\/FTB_4__43:A 1e-06 +2 mux_right_ipin_4\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_3_sram[3]:3 0.0005175293 +4 mux_tree_tapbuf_size10_3_sram[3]:4 3.500183e-05 +5 mux_tree_tapbuf_size10_3_sram[3]:5 0.0001876179 +6 mux_tree_tapbuf_size10_3_sram[3]:6 0.0007368726 +7 mux_tree_tapbuf_size10_3_sram[3]:7 5.740103e-05 +8 mux_tree_tapbuf_size10_3_sram[3]:8 5.151994e-05 +9 mux_tree_tapbuf_size10_3_sram[3]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001326886 +10 mux_tree_tapbuf_size10_3_sram[3]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001326886 + +*RES +0 mem_right_ipin_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_3_sram[3]:8 0.152 +1 mux_tree_tapbuf_size10_3_sram[3]:3 mux_right_ipin_4\/mux_l4_in_0_:S 0.0045 +2 mux_tree_tapbuf_size10_3_sram[3]:7 mux_tree_tapbuf_size10_3_sram[3]:6 0.0045 +3 mux_tree_tapbuf_size10_3_sram[3]:6 mux_tree_tapbuf_size10_3_sram[3]:5 0.002691964 +4 mux_tree_tapbuf_size10_3_sram[3]:6 mux_tree_tapbuf_size10_3_sram[3]:3 0.00921875 +5 mux_tree_tapbuf_size10_3_sram[3]:8 mux_tree_tapbuf_size10_3_sram[3]:7 0.0001657609 +6 mux_tree_tapbuf_size10_3_sram[3]:4 mem_right_ipin_4\/FTB_4__43:A 0.152 +7 mux_tree_tapbuf_size10_3_sram[3]:5 mux_tree_tapbuf_size10_3_sram[3]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[3] 0.00254922 //LENGTH 19.385 LUMPCC 0.000162805 DR + +*CONN +*I mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 58.630 70.040 +*I mux_right_ipin_5\/mux_l4_in_0_:S I *L 0.00357 *C 52.080 63.240 +*I mem_right_ipin_5\/FTB_5__44:A I *L 0.001746 *C 52.900 72.080 +*N mux_tree_tapbuf_size10_4_sram[3]:3 *C 52.938 72.080 +*N mux_tree_tapbuf_size10_4_sram[3]:4 *C 55.615 72.080 +*N mux_tree_tapbuf_size10_4_sram[3]:5 *C 55.660 72.035 +*N mux_tree_tapbuf_size10_4_sram[3]:6 *C 52.117 63.240 +*N mux_tree_tapbuf_size10_4_sram[3]:7 *C 55.615 63.240 +*N mux_tree_tapbuf_size10_4_sram[3]:8 *C 55.660 63.285 +*N mux_tree_tapbuf_size10_4_sram[3]:9 *C 55.660 70.040 +*N mux_tree_tapbuf_size10_4_sram[3]:10 *C 55.705 70.040 +*N mux_tree_tapbuf_size10_4_sram[3]:11 *C 58.593 70.040 + +*CAP +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_5\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_5\/FTB_5__44:A 1e-06 +3 mux_tree_tapbuf_size10_4_sram[3]:3 0.0001905371 +4 mux_tree_tapbuf_size10_4_sram[3]:4 0.0001905371 +5 mux_tree_tapbuf_size10_4_sram[3]:5 0.000121676 +6 mux_tree_tapbuf_size10_4_sram[3]:6 0.0002144285 +7 mux_tree_tapbuf_size10_4_sram[3]:7 0.0002144285 +8 mux_tree_tapbuf_size10_4_sram[3]:8 0.0003766595 +9 mux_tree_tapbuf_size10_4_sram[3]:9 0.0005324851 +10 mux_tree_tapbuf_size10_4_sram[3]:10 0.0002713318 +11 mux_tree_tapbuf_size10_4_sram[3]:11 0.0002713318 +12 mux_tree_tapbuf_size10_4_sram[3]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.616977e-05 +13 mux_tree_tapbuf_size10_4_sram[3]:7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.232715e-06 +14 mux_tree_tapbuf_size10_4_sram[3]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.232715e-06 +15 mux_tree_tapbuf_size10_4_sram[3]:6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.616977e-05 + +*RES +0 mem_right_ipin_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_4_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_4_sram[3]:10 mux_tree_tapbuf_size10_4_sram[3]:9 0.0045 +2 mux_tree_tapbuf_size10_4_sram[3]:9 mux_tree_tapbuf_size10_4_sram[3]:8 0.00603125 +3 mux_tree_tapbuf_size10_4_sram[3]:9 mux_tree_tapbuf_size10_4_sram[3]:5 0.00178125 +4 mux_tree_tapbuf_size10_4_sram[3]:11 mux_tree_tapbuf_size10_4_sram[3]:10 0.002578125 +5 mux_tree_tapbuf_size10_4_sram[3]:4 mux_tree_tapbuf_size10_4_sram[3]:3 0.002390625 +6 mux_tree_tapbuf_size10_4_sram[3]:5 mux_tree_tapbuf_size10_4_sram[3]:4 0.0045 +7 mux_tree_tapbuf_size10_4_sram[3]:3 mem_right_ipin_5\/FTB_5__44:A 0.152 +8 mux_tree_tapbuf_size10_4_sram[3]:7 mux_tree_tapbuf_size10_4_sram[3]:6 0.003122768 +9 mux_tree_tapbuf_size10_4_sram[3]:8 mux_tree_tapbuf_size10_4_sram[3]:7 0.0045 +10 mux_tree_tapbuf_size10_4_sram[3]:6 mux_right_ipin_5\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[2] 0.002762009 //LENGTH 23.185 LUMPCC 0.0002624737 DR + +*CONN +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 22.845 31.280 +*I mux_right_ipin_8\/mux_l3_in_0_:S I *L 0.00357 *C 21.720 39.440 +*I mux_right_ipin_8\/mux_l3_in_1_:S I *L 0.00357 *C 22.180 41.820 +*I mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 18.115 28.220 +*N mux_tree_tapbuf_size10_5_sram[2]:4 *C 18.152 28.220 +*N mux_tree_tapbuf_size10_5_sram[2]:5 *C 22.143 41.820 +*N mux_tree_tapbuf_size10_5_sram[2]:6 *C 21.665 41.820 +*N mux_tree_tapbuf_size10_5_sram[2]:7 *C 21.620 41.775 +*N mux_tree_tapbuf_size10_5_sram[2]:8 *C 21.620 39.440 +*N mux_tree_tapbuf_size10_5_sram[2]:9 *C 21.620 39.440 +*N mux_tree_tapbuf_size10_5_sram[2]:10 *C 21.620 28.265 +*N mux_tree_tapbuf_size10_5_sram[2]:11 *C 21.620 28.220 +*N mux_tree_tapbuf_size10_5_sram[2]:12 *C 22.495 28.220 +*N mux_tree_tapbuf_size10_5_sram[2]:13 *C 22.540 28.265 +*N mux_tree_tapbuf_size10_5_sram[2]:14 *C 22.540 31.235 +*N mux_tree_tapbuf_size10_5_sram[2]:15 *C 22.540 31.280 +*N mux_tree_tapbuf_size10_5_sram[2]:16 *C 22.845 31.280 + +*CAP +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_8\/mux_l3_in_0_:S 1e-06 +2 mux_right_ipin_8\/mux_l3_in_1_:S 1e-06 +3 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_5_sram[2]:4 0.0002296216 +5 mux_tree_tapbuf_size10_5_sram[2]:5 5.869494e-05 +6 mux_tree_tapbuf_size10_5_sram[2]:6 5.869494e-05 +7 mux_tree_tapbuf_size10_5_sram[2]:7 0.0001232818 +8 mux_tree_tapbuf_size10_5_sram[2]:8 3.508494e-05 +9 mux_tree_tapbuf_size10_5_sram[2]:9 0.0006327843 +10 mux_tree_tapbuf_size10_5_sram[2]:10 0.0004805902 +11 mux_tree_tapbuf_size10_5_sram[2]:11 0.00032925 +12 mux_tree_tapbuf_size10_5_sram[2]:12 6.9427e-05 +13 mux_tree_tapbuf_size10_5_sram[2]:13 0.0001836971 +14 mux_tree_tapbuf_size10_5_sram[2]:14 0.0001836971 +15 mux_tree_tapbuf_size10_5_sram[2]:15 5.729848e-05 +16 mux_tree_tapbuf_size10_5_sram[2]:16 5.341252e-05 +17 mux_tree_tapbuf_size10_5_sram[2]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.82666e-06 +18 mux_tree_tapbuf_size10_5_sram[2]:10 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.467943e-05 +19 mux_tree_tapbuf_size10_5_sram[2]:9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.467943e-05 +20 mux_tree_tapbuf_size10_5_sram[2]:9 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.82666e-06 +21 mux_tree_tapbuf_size10_5_sram[2]:10 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.973077e-05 +22 mux_tree_tapbuf_size10_5_sram[2]:9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.973077e-05 + +*RES +0 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_5_sram[2]:16 0.152 +1 mux_tree_tapbuf_size10_5_sram[2]:5 mux_right_ipin_8\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_5_sram[2]:6 mux_tree_tapbuf_size10_5_sram[2]:5 0.0004263393 +3 mux_tree_tapbuf_size10_5_sram[2]:7 mux_tree_tapbuf_size10_5_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size10_5_sram[2]:4 mem_right_ipin_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +5 mux_tree_tapbuf_size10_5_sram[2]:11 mux_tree_tapbuf_size10_5_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size10_5_sram[2]:11 mux_tree_tapbuf_size10_5_sram[2]:4 0.003095982 +7 mux_tree_tapbuf_size10_5_sram[2]:10 mux_tree_tapbuf_size10_5_sram[2]:9 0.009977679 +8 mux_tree_tapbuf_size10_5_sram[2]:8 mux_right_ipin_8\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size10_5_sram[2]:9 mux_tree_tapbuf_size10_5_sram[2]:8 0.0045 +10 mux_tree_tapbuf_size10_5_sram[2]:9 mux_tree_tapbuf_size10_5_sram[2]:7 0.002084821 +11 mux_tree_tapbuf_size10_5_sram[2]:12 mux_tree_tapbuf_size10_5_sram[2]:11 0.00078125 +12 mux_tree_tapbuf_size10_5_sram[2]:13 mux_tree_tapbuf_size10_5_sram[2]:12 0.0045 +13 mux_tree_tapbuf_size10_5_sram[2]:15 mux_tree_tapbuf_size10_5_sram[2]:14 0.0045 +14 mux_tree_tapbuf_size10_5_sram[2]:14 mux_tree_tapbuf_size10_5_sram[2]:13 0.002651786 +15 mux_tree_tapbuf_size10_5_sram[2]:16 mux_tree_tapbuf_size10_5_sram[2]:15 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[3] 0.00163144 //LENGTH 14.230 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 59.645 39.100 +*I mem_right_ipin_9\/FTB_7__46:A I *L 0.001746 *C 54.740 34.000 +*I mux_right_ipin_9\/mux_l4_in_0_:S I *L 0.00357 *C 55.320 30.600 +*N mux_tree_tapbuf_size10_6_sram[3]:3 *C 55.200 30.600 +*N mux_tree_tapbuf_size10_6_sram[3]:4 *C 55.200 30.645 +*N mux_tree_tapbuf_size10_6_sram[3]:5 *C 54.740 34.000 +*N mux_tree_tapbuf_size10_6_sram[3]:6 *C 54.740 34.000 +*N mux_tree_tapbuf_size10_6_sram[3]:7 *C 55.200 34.000 +*N mux_tree_tapbuf_size10_6_sram[3]:8 *C 55.200 39.055 +*N mux_tree_tapbuf_size10_6_sram[3]:9 *C 55.245 39.100 +*N mux_tree_tapbuf_size10_6_sram[3]:10 *C 59.608 39.100 + +*CAP +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_ipin_9\/FTB_7__46:A 1e-06 +2 mux_right_ipin_9\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_6_sram[3]:3 3.144306e-05 +4 mux_tree_tapbuf_size10_6_sram[3]:4 0.0001868267 +5 mux_tree_tapbuf_size10_6_sram[3]:5 3.191307e-05 +6 mux_tree_tapbuf_size10_6_sram[3]:6 6.425192e-05 +7 mux_tree_tapbuf_size10_6_sram[3]:7 0.0004923375 +8 mux_tree_tapbuf_size10_6_sram[3]:8 0.000272469 +9 mux_tree_tapbuf_size10_6_sram[3]:9 0.0002745997 +10 mux_tree_tapbuf_size10_6_sram[3]:10 0.0002745997 + +*RES +0 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_6_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_6_sram[3]:3 mux_right_ipin_9\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_6_sram[3]:4 mux_tree_tapbuf_size10_6_sram[3]:3 0.0045 +3 mux_tree_tapbuf_size10_6_sram[3]:9 mux_tree_tapbuf_size10_6_sram[3]:8 0.0045 +4 mux_tree_tapbuf_size10_6_sram[3]:8 mux_tree_tapbuf_size10_6_sram[3]:7 0.004513393 +5 mux_tree_tapbuf_size10_6_sram[3]:10 mux_tree_tapbuf_size10_6_sram[3]:9 0.003895089 +6 mux_tree_tapbuf_size10_6_sram[3]:5 mem_right_ipin_9\/FTB_7__46:A 0.152 +7 mux_tree_tapbuf_size10_6_sram[3]:6 mux_tree_tapbuf_size10_6_sram[3]:5 0.0045 +8 mux_tree_tapbuf_size10_6_sram[3]:7 mux_tree_tapbuf_size10_6_sram[3]:6 0.0004107143 +9 mux_tree_tapbuf_size10_6_sram[3]:7 mux_tree_tapbuf_size10_6_sram[3]:4 0.002995536 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[2] 0.001952097 //LENGTH 17.330 LUMPCC 0 DR + +*CONN +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 18.245 14.960 +*I mux_right_ipin_12\/mux_l3_in_1_:S I *L 0.00357 *C 21.720 20.060 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 17.655 22.780 +*I mux_right_ipin_12\/mux_l3_in_0_:S I *L 0.00357 *C 20.800 14.280 +*N mux_tree_tapbuf_size10_7_sram[2]:4 *C 20.838 14.280 +*N mux_tree_tapbuf_size10_7_sram[2]:5 *C 21.160 14.280 +*N mux_tree_tapbuf_size10_7_sram[2]:6 *C 17.693 22.780 +*N mux_tree_tapbuf_size10_7_sram[2]:7 *C 21.115 22.780 +*N mux_tree_tapbuf_size10_7_sram[2]:8 *C 21.160 22.735 +*N mux_tree_tapbuf_size10_7_sram[2]:9 *C 21.683 20.060 +*N mux_tree_tapbuf_size10_7_sram[2]:10 *C 21.205 20.060 +*N mux_tree_tapbuf_size10_7_sram[2]:11 *C 21.160 20.060 +*N mux_tree_tapbuf_size10_7_sram[2]:12 *C 21.160 15.005 +*N mux_tree_tapbuf_size10_7_sram[2]:13 *C 21.160 14.930 +*N mux_tree_tapbuf_size10_7_sram[2]:14 *C 18.283 14.960 + +*CAP +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_ipin_12\/mux_l3_in_1_:S 1e-06 +2 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_ipin_12\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_7_sram[2]:4 3.049299e-05 +5 mux_tree_tapbuf_size10_7_sram[2]:5 6.690593e-05 +6 mux_tree_tapbuf_size10_7_sram[2]:6 0.0002218391 +7 mux_tree_tapbuf_size10_7_sram[2]:7 0.0002218391 +8 mux_tree_tapbuf_size10_7_sram[2]:8 0.0001429812 +9 mux_tree_tapbuf_size10_7_sram[2]:9 5.849758e-05 +10 mux_tree_tapbuf_size10_7_sram[2]:10 5.849758e-05 +11 mux_tree_tapbuf_size10_7_sram[2]:11 0.0004374307 +12 mux_tree_tapbuf_size10_7_sram[2]:12 0.0002639594 +13 mux_tree_tapbuf_size10_7_sram[2]:13 0.0002410334 +14 mux_tree_tapbuf_size10_7_sram[2]:14 0.0002046204 + +*RES +0 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_7_sram[2]:14 0.152 +1 mux_tree_tapbuf_size10_7_sram[2]:13 mux_tree_tapbuf_size10_7_sram[2]:12 0.0045 +2 mux_tree_tapbuf_size10_7_sram[2]:13 mux_tree_tapbuf_size10_7_sram[2]:5 0.0005803572 +3 mux_tree_tapbuf_size10_7_sram[2]:12 mux_tree_tapbuf_size10_7_sram[2]:11 0.004513393 +4 mux_tree_tapbuf_size10_7_sram[2]:7 mux_tree_tapbuf_size10_7_sram[2]:6 0.003055804 +5 mux_tree_tapbuf_size10_7_sram[2]:8 mux_tree_tapbuf_size10_7_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size10_7_sram[2]:6 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size10_7_sram[2]:14 mux_tree_tapbuf_size10_7_sram[2]:13 0.002569197 +8 mux_tree_tapbuf_size10_7_sram[2]:10 mux_tree_tapbuf_size10_7_sram[2]:9 0.0004263393 +9 mux_tree_tapbuf_size10_7_sram[2]:11 mux_tree_tapbuf_size10_7_sram[2]:10 0.0045 +10 mux_tree_tapbuf_size10_7_sram[2]:11 mux_tree_tapbuf_size10_7_sram[2]:8 0.002388393 +11 mux_tree_tapbuf_size10_7_sram[2]:9 mux_right_ipin_12\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_7_sram[2]:4 mux_right_ipin_12\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_7_sram[2]:5 mux_tree_tapbuf_size10_7_sram[2]:4 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_2_ccff_tail[0] 0.0005096669 //LENGTH 3.360 LUMPCC 0.0001067047 DR + +*CONN +*I mem_right_ipin_1\/FTB_3__42:X O *L 0 *C 19.545 97.240 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 19.035 98.940 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 *C 19.073 98.940 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 *C 19.735 98.940 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 *C 19.780 98.895 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 *C 19.780 97.285 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 *C 19.780 97.240 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 *C 19.545 97.240 + +*CAP +0 mem_right_ipin_1\/FTB_3__42:X 1e-06 +1 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 6.699654e-05 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 6.699654e-05 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 7.197943e-05 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 7.197943e-05 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 6.271189e-05 +7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 6.029833e-05 +8 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 chany_bottom_in[15]:10 5.335233e-05 +9 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 chany_bottom_in[15]:13 5.335233e-05 + +*RES +0 mem_right_ipin_1\/FTB_3__42:X mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 0.0005915179 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_5_ccff_tail[0] 0.00300307 //LENGTH 20.310 LUMPCC 0.0006145251 DR + +*CONN +*I mem_right_ipin_8\/FTB_6__45:X O *L 0 *C 23.190 34.000 +*I mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 39.735 31.620 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 *C 39.610 31.620 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 *C 32.200 31.620 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 *C 32.200 31.960 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 *C 23.045 31.960 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 *C 23.000 32.005 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 *C 23.000 33.955 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 *C 23.000 34.000 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 *C 23.190 34.000 + +*CAP +0 mem_right_ipin_8\/FTB_6__45:X 1e-06 +1 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 0.0004917354 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 0.0005178823 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.0005055508 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0004794038 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 0.0001431126 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 0.0001431126 +8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 5.573163e-05 +9 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 5.001534e-05 +10 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_5_sram[1]:6 9.268778e-05 +11 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_5_sram[1]:21 0.0002145747 +12 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_5_sram[1]:21 9.268778e-05 +13 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_5_sram[1]:22 0.0002145747 + +*RES +0 mem_right_ipin_8\/FTB_6__45:X mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 0.0001032609 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 0.0045 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 0.001741071 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.008174107 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0045 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 mem_right_ipin_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 0.0003035715 +8 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 0.006616072 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[1] 0.004523557 //LENGTH 34.515 LUMPCC 0.0001362596 DR + +*CONN +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 17.785 102.000 +*I mux_right_ipin_2\/mux_l2_in_3_:S I *L 0.00357 *C 16.200 96.270 +*I mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 7.995 96.900 +*I mux_right_ipin_2\/mux_l2_in_2_:S I *L 0.00357 *C 18.960 93.840 +*I mux_right_ipin_2\/mux_l2_in_1_:S I *L 0.00357 *C 17.580 89.080 +*I mux_right_ipin_2\/mux_l2_in_0_:S I *L 0.00357 *C 21.260 90.440 +*N mux_tree_tapbuf_size8_0_sram[1]:6 *C 17.617 89.080 +*N mux_tree_tapbuf_size8_0_sram[1]:7 *C 21.115 89.080 +*N mux_tree_tapbuf_size8_0_sram[1]:8 *C 21.160 89.125 +*N mux_tree_tapbuf_size8_0_sram[1]:9 *C 21.160 90.395 +*N mux_tree_tapbuf_size8_0_sram[1]:10 *C 21.160 90.440 +*N mux_tree_tapbuf_size8_0_sram[1]:11 *C 21.160 90.780 +*N mux_tree_tapbuf_size8_0_sram[1]:12 *C 18.905 90.780 +*N mux_tree_tapbuf_size8_0_sram[1]:13 *C 18.860 90.825 +*N mux_tree_tapbuf_size8_0_sram[1]:14 *C 18.860 93.840 +*N mux_tree_tapbuf_size8_0_sram[1]:15 *C 18.860 93.840 +*N mux_tree_tapbuf_size8_0_sram[1]:16 *C 8.033 96.900 +*N mux_tree_tapbuf_size8_0_sram[1]:17 *C 16.100 96.900 +*N mux_tree_tapbuf_size8_0_sram[1]:18 *C 16.100 96.305 +*N mux_tree_tapbuf_size8_0_sram[1]:19 *C 16.200 96.270 +*N mux_tree_tapbuf_size8_0_sram[1]:20 *C 16.160 95.910 +*N mux_tree_tapbuf_size8_0_sram[1]:21 *C 16.530 95.910 +*N mux_tree_tapbuf_size8_0_sram[1]:22 *C 16.560 95.880 +*N mux_tree_tapbuf_size8_0_sram[1]:23 *C 16.568 95.880 +*N mux_tree_tapbuf_size8_0_sram[1]:24 *C 18.852 95.880 +*N mux_tree_tapbuf_size8_0_sram[1]:25 *C 18.860 95.880 +*N mux_tree_tapbuf_size8_0_sram[1]:26 *C 18.860 101.955 +*N mux_tree_tapbuf_size8_0_sram[1]:27 *C 18.815 102.000 +*N mux_tree_tapbuf_size8_0_sram[1]:28 *C 17.823 102.000 + +*CAP +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_ipin_2\/mux_l2_in_3_:S 1e-06 +2 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_ipin_2\/mux_l2_in_2_:S 1e-06 +4 mux_right_ipin_2\/mux_l2_in_1_:S 1e-06 +5 mux_right_ipin_2\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_0_sram[1]:6 0.000308933 +7 mux_tree_tapbuf_size8_0_sram[1]:7 0.000308933 +8 mux_tree_tapbuf_size8_0_sram[1]:8 9.318537e-05 +9 mux_tree_tapbuf_size8_0_sram[1]:9 9.318537e-05 +10 mux_tree_tapbuf_size8_0_sram[1]:10 6.232115e-05 +11 mux_tree_tapbuf_size8_0_sram[1]:11 0.0001384408 +12 mux_tree_tapbuf_size8_0_sram[1]:12 0.0001096571 +13 mux_tree_tapbuf_size8_0_sram[1]:13 0.0001685373 +14 mux_tree_tapbuf_size8_0_sram[1]:14 3.309287e-05 +15 mux_tree_tapbuf_size8_0_sram[1]:15 0.0003085355 +16 mux_tree_tapbuf_size8_0_sram[1]:16 0.0005371154 +17 mux_tree_tapbuf_size8_0_sram[1]:17 0.0005730111 +18 mux_tree_tapbuf_size8_0_sram[1]:18 1.392055e-05 +19 mux_tree_tapbuf_size8_0_sram[1]:19 0.0001100676 +20 mux_tree_tapbuf_size8_0_sram[1]:20 7.962629e-05 +21 mux_tree_tapbuf_size8_0_sram[1]:21 5.158451e-05 +22 mux_tree_tapbuf_size8_0_sram[1]:22 3.542046e-05 +23 mux_tree_tapbuf_size8_0_sram[1]:23 0.0001734145 +24 mux_tree_tapbuf_size8_0_sram[1]:24 0.0001734145 +25 mux_tree_tapbuf_size8_0_sram[1]:25 0.0004724097 +26 mux_tree_tapbuf_size8_0_sram[1]:26 0.000328075 +27 mux_tree_tapbuf_size8_0_sram[1]:27 0.000104208 +28 mux_tree_tapbuf_size8_0_sram[1]:28 0.000104208 +29 mux_tree_tapbuf_size8_0_sram[1]:12 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.812978e-05 +30 mux_tree_tapbuf_size8_0_sram[1]:11 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.812978e-05 + +*RES +0 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_0_sram[1]:28 0.152 +1 mux_tree_tapbuf_size8_0_sram[1]:12 mux_tree_tapbuf_size8_0_sram[1]:11 0.002013393 +2 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:12 0.0045 +3 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:24 0.00341 +4 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:15 0.001821429 +5 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size8_0_sram[1]:23 0.0003579833 +6 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:21 0.0045 +7 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size8_0_sram[1]:22 0.00341 +8 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:20 0.00023125 +9 mux_tree_tapbuf_size8_0_sram[1]:19 mux_right_ipin_2\/mux_l2_in_3_:S 0.152 +10 mux_tree_tapbuf_size8_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:18 1.822917e-05 +11 mux_tree_tapbuf_size8_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:17 0.0005625 +12 mux_tree_tapbuf_size8_0_sram[1]:14 mux_right_ipin_2\/mux_l2_in_2_:S 0.152 +13 mux_tree_tapbuf_size8_0_sram[1]:15 mux_tree_tapbuf_size8_0_sram[1]:14 0.0045 +14 mux_tree_tapbuf_size8_0_sram[1]:15 mux_tree_tapbuf_size8_0_sram[1]:13 0.002691964 +15 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[1]:9 0.0045 +16 mux_tree_tapbuf_size8_0_sram[1]:10 mux_right_ipin_2\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size8_0_sram[1]:9 mux_tree_tapbuf_size8_0_sram[1]:8 0.001133929 +18 mux_tree_tapbuf_size8_0_sram[1]:7 mux_tree_tapbuf_size8_0_sram[1]:6 0.003122768 +19 mux_tree_tapbuf_size8_0_sram[1]:8 mux_tree_tapbuf_size8_0_sram[1]:7 0.0045 +20 mux_tree_tapbuf_size8_0_sram[1]:6 mux_right_ipin_2\/mux_l2_in_1_:S 0.152 +21 mux_tree_tapbuf_size8_0_sram[1]:16 mem_right_ipin_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +22 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size8_0_sram[1]:26 0.0045 +23 mux_tree_tapbuf_size8_0_sram[1]:26 mux_tree_tapbuf_size8_0_sram[1]:25 0.005424107 +24 mux_tree_tapbuf_size8_0_sram[1]:28 mux_tree_tapbuf_size8_0_sram[1]:27 0.0008861608 +25 mux_tree_tapbuf_size8_0_sram[1]:17 mux_tree_tapbuf_size8_0_sram[1]:16 0.007203125 +26 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:19 0.0001875 +27 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[1]:10 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[3] 0.005431818 //LENGTH 37.965 LUMPCC 0.001104243 DR + +*CONN +*I mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 44.465 69.700 +*I mux_right_ipin_6\/mux_l4_in_0_:S I *L 0.00357 *C 30.000 72.760 +*I mem_right_ipin_6\/FTB_12__51:A I *L 0.001746 *C 42.320 72.080 +*N mux_tree_tapbuf_size8_2_sram[3]:3 *C 42.320 72.080 +*N mux_tree_tapbuf_size8_2_sram[3]:4 *C 42.320 72.035 +*N mux_tree_tapbuf_size8_2_sram[3]:5 *C 29.963 72.760 +*N mux_tree_tapbuf_size8_2_sram[3]:6 *C 24.425 72.760 +*N mux_tree_tapbuf_size8_2_sram[3]:7 *C 24.380 72.715 +*N mux_tree_tapbuf_size8_2_sram[3]:8 *C 24.380 67.377 +*N mux_tree_tapbuf_size8_2_sram[3]:9 *C 24.388 67.320 +*N mux_tree_tapbuf_size8_2_sram[3]:10 *C 41.852 67.320 +*N mux_tree_tapbuf_size8_2_sram[3]:11 *C 41.860 67.377 +*N mux_tree_tapbuf_size8_2_sram[3]:12 *C 41.860 69.700 +*N mux_tree_tapbuf_size8_2_sram[3]:13 *C 42.320 69.745 +*N mux_tree_tapbuf_size8_2_sram[3]:14 *C 42.365 69.700 +*N mux_tree_tapbuf_size8_2_sram[3]:15 *C 44.428 69.700 + +*CAP +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_ipin_6\/mux_l4_in_0_:S 1e-06 +2 mem_right_ipin_6\/FTB_12__51:A 1e-06 +3 mux_tree_tapbuf_size8_2_sram[3]:3 3.704365e-05 +4 mux_tree_tapbuf_size8_2_sram[3]:4 0.0001656818 +5 mux_tree_tapbuf_size8_2_sram[3]:5 0.0004019521 +6 mux_tree_tapbuf_size8_2_sram[3]:6 0.0004019521 +7 mux_tree_tapbuf_size8_2_sram[3]:7 0.0003018619 +8 mux_tree_tapbuf_size8_2_sram[3]:8 0.0003018619 +9 mux_tree_tapbuf_size8_2_sram[3]:9 0.0009048192 +10 mux_tree_tapbuf_size8_2_sram[3]:10 0.0009048192 +11 mux_tree_tapbuf_size8_2_sram[3]:11 0.0001853225 +12 mux_tree_tapbuf_size8_2_sram[3]:12 0.0002200742 +13 mux_tree_tapbuf_size8_2_sram[3]:13 0.0002004335 +14 mux_tree_tapbuf_size8_2_sram[3]:14 0.0001493761 +15 mux_tree_tapbuf_size8_2_sram[3]:15 0.0001493761 +16 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size10_4_sram[0]:25 0.0002255146 +17 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size10_4_sram[0]:27 5.878347e-07 +18 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size10_4_sram[0]:26 0.0002255146 +19 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size10_4_sram[0]:28 5.878347e-07 +20 mux_tree_tapbuf_size8_2_sram[3]:10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.000326019 +21 mux_tree_tapbuf_size8_2_sram[3]:9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.000326019 + +*RES +0 mem_right_ipin_6\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_2_sram[3]:15 0.152 +1 mux_tree_tapbuf_size8_2_sram[3]:3 mem_right_ipin_6\/FTB_12__51:A 0.152 +2 mux_tree_tapbuf_size8_2_sram[3]:4 mux_tree_tapbuf_size8_2_sram[3]:3 0.0045 +3 mux_tree_tapbuf_size8_2_sram[3]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.00341 +4 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.002736183 +5 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size8_2_sram[3]:7 0.004765625 +6 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:8 0.00341 +7 mux_tree_tapbuf_size8_2_sram[3]:6 mux_tree_tapbuf_size8_2_sram[3]:5 0.004944196 +8 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size8_2_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size8_2_sram[3]:5 mux_right_ipin_6\/mux_l4_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_2_sram[3]:14 mux_tree_tapbuf_size8_2_sram[3]:13 0.0045 +11 mux_tree_tapbuf_size8_2_sram[3]:13 mux_tree_tapbuf_size8_2_sram[3]:12 0.0004107143 +12 mux_tree_tapbuf_size8_2_sram[3]:13 mux_tree_tapbuf_size8_2_sram[3]:4 0.002044643 +13 mux_tree_tapbuf_size8_2_sram[3]:15 mux_tree_tapbuf_size8_2_sram[3]:14 0.001841518 +14 mux_tree_tapbuf_size8_2_sram[3]:12 mux_tree_tapbuf_size8_2_sram[3]:11 0.002073661 + +*END + +*D_NET mux_tree_tapbuf_size8_4_sram[0] 0.006269831 //LENGTH 45.315 LUMPCC 0.0008017559 DR + +*CONN +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 46.305 36.720 +*I mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.455 31.620 +*I mux_right_ipin_10\/mux_l1_in_0_:S I *L 0.00357 *C 30.460 34.295 +*N mux_tree_tapbuf_size8_4_sram[0]:3 *C 30.460 34.295 +*N mux_tree_tapbuf_size8_4_sram[0]:4 *C 8.455 31.620 +*N mux_tree_tapbuf_size8_4_sram[0]:5 *C 8.740 31.620 +*N mux_tree_tapbuf_size8_4_sram[0]:6 *C 8.740 31.620 +*N mux_tree_tapbuf_size8_4_sram[0]:7 *C 8.740 31.960 +*N mux_tree_tapbuf_size8_4_sram[0]:8 *C 8.748 31.960 +*N mux_tree_tapbuf_size8_4_sram[0]:9 *C 28.973 31.960 +*N mux_tree_tapbuf_size8_4_sram[0]:10 *C 28.980 32.017 +*N mux_tree_tapbuf_size8_4_sram[0]:11 *C 28.980 33.955 +*N mux_tree_tapbuf_size8_4_sram[0]:12 *C 29.025 34.000 +*N mux_tree_tapbuf_size8_4_sram[0]:13 *C 30.460 34.000 +*N mux_tree_tapbuf_size8_4_sram[0]:14 *C 32.200 34.000 +*N mux_tree_tapbuf_size8_4_sram[0]:15 *C 32.200 34.340 +*N mux_tree_tapbuf_size8_4_sram[0]:16 *C 45.495 34.340 +*N mux_tree_tapbuf_size8_4_sram[0]:17 *C 45.540 34.385 +*N mux_tree_tapbuf_size8_4_sram[0]:18 *C 45.540 36.675 +*N mux_tree_tapbuf_size8_4_sram[0]:19 *C 45.585 36.720 +*N mux_tree_tapbuf_size8_4_sram[0]:20 *C 46.268 36.720 + +*CAP +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_10\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_4_sram[0]:3 6.075914e-05 +4 mux_tree_tapbuf_size8_4_sram[0]:4 4.970595e-05 +5 mux_tree_tapbuf_size8_4_sram[0]:5 5.371622e-05 +6 mux_tree_tapbuf_size8_4_sram[0]:6 5.721517e-05 +7 mux_tree_tapbuf_size8_4_sram[0]:7 5.930381e-05 +8 mux_tree_tapbuf_size8_4_sram[0]:8 0.001204187 +9 mux_tree_tapbuf_size8_4_sram[0]:9 0.001204187 +10 mux_tree_tapbuf_size8_4_sram[0]:10 0.0001522121 +11 mux_tree_tapbuf_size8_4_sram[0]:11 0.0001522121 +12 mux_tree_tapbuf_size8_4_sram[0]:12 0.0001088128 +13 mux_tree_tapbuf_size8_4_sram[0]:13 0.0002609633 +14 mux_tree_tapbuf_size8_4_sram[0]:14 0.0001472714 +15 mux_tree_tapbuf_size8_4_sram[0]:15 0.0007800774 +16 mux_tree_tapbuf_size8_4_sram[0]:16 0.0007539305 +17 mux_tree_tapbuf_size8_4_sram[0]:17 0.0001314111 +18 mux_tree_tapbuf_size8_4_sram[0]:18 0.0001314111 +19 mux_tree_tapbuf_size8_4_sram[0]:19 7.884945e-05 +20 mux_tree_tapbuf_size8_4_sram[0]:20 7.884945e-05 +21 mux_tree_tapbuf_size8_4_sram[0]:9 prog_clk[0]:112 0.0004008779 +22 mux_tree_tapbuf_size8_4_sram[0]:8 prog_clk[0]:137 0.0004008779 + +*RES +0 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_4_sram[0]:20 0.152 +1 mux_tree_tapbuf_size8_4_sram[0]:12 mux_tree_tapbuf_size8_4_sram[0]:11 0.0045 +2 mux_tree_tapbuf_size8_4_sram[0]:11 mux_tree_tapbuf_size8_4_sram[0]:10 0.001729911 +3 mux_tree_tapbuf_size8_4_sram[0]:10 mux_tree_tapbuf_size8_4_sram[0]:9 0.00341 +4 mux_tree_tapbuf_size8_4_sram[0]:9 mux_tree_tapbuf_size8_4_sram[0]:8 0.003168583 +5 mux_tree_tapbuf_size8_4_sram[0]:7 mux_tree_tapbuf_size8_4_sram[0]:6 0.0001634615 +6 mux_tree_tapbuf_size8_4_sram[0]:8 mux_tree_tapbuf_size8_4_sram[0]:7 0.00341 +7 mux_tree_tapbuf_size8_4_sram[0]:5 mux_tree_tapbuf_size8_4_sram[0]:4 0.0001548913 +8 mux_tree_tapbuf_size8_4_sram[0]:6 mux_tree_tapbuf_size8_4_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size8_4_sram[0]:4 mem_right_ipin_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size8_4_sram[0]:20 mux_tree_tapbuf_size8_4_sram[0]:19 0.000609375 +11 mux_tree_tapbuf_size8_4_sram[0]:19 mux_tree_tapbuf_size8_4_sram[0]:18 0.0045 +12 mux_tree_tapbuf_size8_4_sram[0]:18 mux_tree_tapbuf_size8_4_sram[0]:17 0.002044643 +13 mux_tree_tapbuf_size8_4_sram[0]:16 mux_tree_tapbuf_size8_4_sram[0]:15 0.01187054 +14 mux_tree_tapbuf_size8_4_sram[0]:17 mux_tree_tapbuf_size8_4_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size8_4_sram[0]:3 mux_right_ipin_10\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size8_4_sram[0]:13 mux_tree_tapbuf_size8_4_sram[0]:12 0.00128125 +17 mux_tree_tapbuf_size8_4_sram[0]:13 mux_tree_tapbuf_size8_4_sram[0]:3 0.0001271552 +18 mux_tree_tapbuf_size8_4_sram[0]:14 mux_tree_tapbuf_size8_4_sram[0]:13 0.001553571 +19 mux_tree_tapbuf_size8_4_sram[0]:15 mux_tree_tapbuf_size8_4_sram[0]:14 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_7_sram[0] 0.004083988 //LENGTH 34.685 LUMPCC 0.00060804 DR + +*CONN +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.945 47.940 +*I mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.955 71.740 +*I mux_right_ipin_15\/mux_l1_in_0_:S I *L 0.00357 *C 58.780 72.080 +*N mux_tree_tapbuf_size8_7_sram[0]:3 *C 58.818 72.080 +*N mux_tree_tapbuf_size8_7_sram[0]:4 *C 62.055 72.080 +*N mux_tree_tapbuf_size8_7_sram[0]:5 *C 62.100 72.035 +*N mux_tree_tapbuf_size8_7_sram[0]:6 *C 65.955 71.740 +*N mux_tree_tapbuf_size8_7_sram[0]:7 *C 65.780 71.740 +*N mux_tree_tapbuf_size8_7_sram[0]:8 *C 65.780 71.695 +*N mux_tree_tapbuf_size8_7_sram[0]:9 *C 65.780 70.085 +*N mux_tree_tapbuf_size8_7_sram[0]:10 *C 65.735 70.040 +*N mux_tree_tapbuf_size8_7_sram[0]:11 *C 62.145 70.040 +*N mux_tree_tapbuf_size8_7_sram[0]:12 *C 62.100 70.040 +*N mux_tree_tapbuf_size8_7_sram[0]:13 *C 62.100 47.985 +*N mux_tree_tapbuf_size8_7_sram[0]:14 *C 62.100 47.940 +*N mux_tree_tapbuf_size8_7_sram[0]:15 *C 61.945 47.940 + +*CAP +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_ipin_15\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_7_sram[0]:3 0.000160987 +4 mux_tree_tapbuf_size8_7_sram[0]:4 0.000160987 +5 mux_tree_tapbuf_size8_7_sram[0]:5 0.0001005418 +6 mux_tree_tapbuf_size8_7_sram[0]:6 5.01553e-05 +7 mux_tree_tapbuf_size8_7_sram[0]:7 5.071373e-05 +8 mux_tree_tapbuf_size8_7_sram[0]:8 0.0001040747 +9 mux_tree_tapbuf_size8_7_sram[0]:9 0.0001040747 +10 mux_tree_tapbuf_size8_7_sram[0]:10 0.000289827 +11 mux_tree_tapbuf_size8_7_sram[0]:11 0.000289827 +12 mux_tree_tapbuf_size8_7_sram[0]:12 0.00109571 +13 mux_tree_tapbuf_size8_7_sram[0]:13 0.0009649512 +14 mux_tree_tapbuf_size8_7_sram[0]:14 5.139406e-05 +15 mux_tree_tapbuf_size8_7_sram[0]:15 4.970409e-05 +16 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size10_4_sram[1]:23 6.0568e-05 +17 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size10_4_sram[1]:24 7.42871e-06 +18 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size10_4_sram[1]:30 8.733908e-05 +19 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size10_4_sram[1]:31 7.058181e-05 +20 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size10_4_sram[1]:9 6.0568e-05 +21 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size10_4_sram[1]:23 7.42871e-06 +22 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size10_4_sram[1]:27 8.733908e-05 +23 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size10_4_sram[1]:30 7.058181e-05 +24 mux_tree_tapbuf_size8_7_sram[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.908794e-05 +25 mux_tree_tapbuf_size8_7_sram[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.01447e-06 +26 mux_tree_tapbuf_size8_7_sram[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.908794e-05 +27 mux_tree_tapbuf_size8_7_sram[0]:12 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.01447e-06 + +*RES +0 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_7_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_7_sram[0]:14 mux_tree_tapbuf_size8_7_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size8_7_sram[0]:13 mux_tree_tapbuf_size8_7_sram[0]:12 0.01969196 +3 mux_tree_tapbuf_size8_7_sram[0]:15 mux_tree_tapbuf_size8_7_sram[0]:14 8.423914e-05 +4 mux_tree_tapbuf_size8_7_sram[0]:4 mux_tree_tapbuf_size8_7_sram[0]:3 0.002890625 +5 mux_tree_tapbuf_size8_7_sram[0]:5 mux_tree_tapbuf_size8_7_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size8_7_sram[0]:3 mux_right_ipin_15\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_7_sram[0]:11 mux_tree_tapbuf_size8_7_sram[0]:10 0.003205357 +8 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size8_7_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size8_7_sram[0]:12 mux_tree_tapbuf_size8_7_sram[0]:5 0.00178125 +10 mux_tree_tapbuf_size8_7_sram[0]:10 mux_tree_tapbuf_size8_7_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size8_7_sram[0]:9 mux_tree_tapbuf_size8_7_sram[0]:8 0.0014375 +12 mux_tree_tapbuf_size8_7_sram[0]:7 mux_tree_tapbuf_size8_7_sram[0]:6 9.510869e-05 +13 mux_tree_tapbuf_size8_7_sram[0]:8 mux_tree_tapbuf_size8_7_sram[0]:7 0.0045 +14 mux_tree_tapbuf_size8_7_sram[0]:6 mem_right_ipin_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_5_ccff_tail[0] 0.002903861 //LENGTH 25.530 LUMPCC 0.0004656211 DR + +*CONN +*I mem_right_ipin_11\/FTB_15__54:X O *L 0 *C 8.045 49.640 +*I mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 9.375 26.180 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 *C 9.375 26.180 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 *C 9.200 26.180 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 *C 9.200 26.225 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 *C 9.200 49.595 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 *C 9.155 49.640 +*N mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 *C 8.082 49.640 + +*CAP +0 mem_right_ipin_11\/FTB_15__54:X 1e-06 +1 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 4.626771e-05 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 5.05087e-05 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.001074291 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.001074291 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 9.544045e-05 +7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 9.544045e-05 +8 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_4_sram[2]:9 3.746311e-05 +9 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_4_sram[2]:13 3.369141e-05 +10 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_4_sram[2]:14 1.713769e-05 +11 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_4_sram[2]:5 3.746311e-05 +12 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_4_sram[2]:9 1.713769e-05 +13 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_4_sram[2]:14 3.369141e-05 +14 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_4_sram[3]:8 7.871841e-05 +15 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_4_sram[3]:10 6.579992e-05 +16 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_4_sram[3]:5 7.871841e-05 +17 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_4_sram[3]:9 6.579992e-05 + +*RES +0 mem_right_ipin_11\/FTB_15__54:X mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 mem_right_ipin_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:4 0.02086607 +6 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_5_ccff_tail[0]:6 0.0009575894 + +*END + +*D_NET mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001620975 //LENGTH 13.145 LUMPCC 0.0004984291 DR + +*CONN +*I mux_left_ipin_0\/mux_l2_in_0_:X O *L 0 *C 66.065 44.880 +*I mux_left_ipin_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 78.300 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.263 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 77.740 45.220 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 77.740 44.880 +*N mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 66.103 44.880 + +*CAP +0 mux_left_ipin_0\/mux_l2_in_0_:X 1e-06 +1 mux_left_ipin_0\/mux_l3_in_0_:A1 1e-06 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.008031e-05 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.54012e-05 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0005101926 +5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004848718 +6 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:27 9.187937e-05 +7 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:29 5.608923e-05 +8 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:26 5.608923e-05 +9 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:28 9.187937e-05 +10 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.672083e-06 +11 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.657381e-05 +12 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.657381e-05 +13 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.672083e-06 + +*RES +0 mux_left_ipin_0\/mux_l2_in_0_:X mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.152 +1 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_ipin_0\/mux_l3_in_0_:A1 0.152 +2 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.01039063 +3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 +4 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_ipin_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004665179 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00114497 //LENGTH 9.400 LUMPCC 0.0001497773 DR + +*CONN +*I mux_right_ipin_0\/mux_l1_in_2_:X O *L 0 *C 38.465 72.420 +*I mux_right_ipin_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 39.465 77.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.503 77.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 40.435 77.860 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 40.480 77.815 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 40.480 72.465 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 40.435 72.420 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 38.503 72.420 + +*CAP +0 mux_right_ipin_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001032456 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001032456 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002352292 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002352292 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001581217 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001581217 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[19]:15 7.488867e-05 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[19]:16 7.488867e-05 + +*RES +0 mux_right_ipin_0\/mux_l1_in_2_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_0\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008325894 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725446 + +*END + +*D_NET mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003802533 //LENGTH 30.790 LUMPCC 0.0008311633 DR + +*CONN +*I mux_right_ipin_0\/mux_l4_in_0_:X O *L 0 *C 25.015 88.400 +*I mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 8.485 102.165 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 8.485 102.165 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 8.740 102.000 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 8.740 101.955 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 8.740 88.445 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 8.785 88.400 +*N mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 24.978 88.400 + +*CAP +0 mux_right_ipin_0\/mux_l4_in_0_:X 1e-06 +1 mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.545206e-05 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.741898e-05 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0006748634 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0006748634 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.000763386 +7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.000763386 +8 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_top_in[3]:54 0.0002166255 +9 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_top_in[3]:55 0.0002166255 +10 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size8_0_sram[3]:4 1.008988e-05 +11 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size8_0_sram[3]:10 1.491888e-05 +12 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size8_0_sram[3]:7 8.106061e-05 +13 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size8_0_sram[3]:9 1.491888e-05 +14 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size8_0_sram[3]:10 1.008988e-05 +15 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size8_0_sram[3]:8 8.106061e-05 +16 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.288674e-05 +17 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.288674e-05 + +*RES +0 mux_right_ipin_0\/mux_l4_in_0_:X mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.000138587 +2 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +3 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +4 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0120625 +5 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.01445759 +6 mux_right_ipin_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_ipin_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003895664 //LENGTH 2.310 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l1_in_2_:X O *L 0 *C 22.715 78.200 +*I mux_right_ipin_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 22.445 79.900 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 22.445 79.900 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.540 79.855 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 22.540 78.245 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 22.540 78.200 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 22.715 78.200 + +*CAP +0 mux_right_ipin_4\/mux_l1_in_2_:X 1e-06 +1 mux_right_ipin_4\/mux_l2_in_1_:A1 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.035036e-05 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001171794 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001171794 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.114643e-05 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.171076e-05 + +*RES +0 mux_right_ipin_4\/mux_l1_in_2_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_4\/mux_l2_in_1_:A1 0.152 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0014375 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.510871e-05 + +*END + +*D_NET mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005822393 //LENGTH 4.385 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_4\/mux_l2_in_3_:X O *L 0 *C 13.975 78.200 +*I mux_right_ipin_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 12.710 80.580 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 12.748 80.580 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 13.755 80.580 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 13.800 80.535 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 13.800 78.245 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 13.800 78.200 +*N mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 13.975 78.200 + +*CAP +0 mux_right_ipin_4\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_4\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.083838e-05 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.083838e-05 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001449934 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001449934 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.603572e-05 +7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.254006e-05 + +*RES +0 mux_right_ipin_4\/mux_l2_in_3_:X mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_4\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0008995535 +3 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002044643 +6 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001501637 //LENGTH 12.635 LUMPCC 0.000162805 DR + +*CONN +*I mux_right_ipin_5\/mux_l3_in_1_:X O *L 0 *C 64.575 63.580 +*I mux_right_ipin_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 53.190 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 53.227 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 53.820 64.260 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 53.820 63.580 +*N mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 64.538 63.580 + +*CAP +0 mux_right_ipin_5\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_5\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.737681e-05 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 8.944788e-05 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0006210392 +5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0005789681 +6 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_4_sram[3]:6 5.232715e-06 +7 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_4_sram[3]:7 7.616977e-05 +8 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_4_sram[3]:7 5.232715e-06 +9 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_4_sram[3]:6 7.616977e-05 + +*RES +0 mux_right_ipin_5\/mux_l3_in_1_:X mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.152 +1 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_ipin_5\/mux_l4_in_0_:A0 0.152 +2 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.009569198 +3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0005290179 +4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_ipin_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0006071429 + +*END + +*D_NET mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000521115 //LENGTH 4.475 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_8\/mux_l2_in_3_:X O *L 0 *C 25.475 44.200 +*I mux_right_ipin_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 23.290 42.840 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 23.328 42.840 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 23.875 42.840 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 23.920 42.885 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 23.920 44.155 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 23.965 44.200 +*N mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 25.438 44.200 + +*CAP +0 mux_right_ipin_8\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_8\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.782111e-05 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.782111e-05 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.521111e-05 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.521111e-05 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001165253 +7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001165253 + +*RES +0 mux_right_ipin_8\/mux_l2_in_3_:X mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_8\/mux_l3_in_1_:A0 0.152 +2 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +6 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002864175 //LENGTH 20.760 LUMPCC 0.0007453607 DR + +*CONN +*I mux_right_ipin_9\/mux_l1_in_1_:X O *L 0 *C 53.645 25.160 +*I mux_right_ipin_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 65.495 17.340 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 65.495 17.340 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 65.320 17.680 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 53.405 17.680 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 53.360 17.725 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 53.360 25.115 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 53.360 25.160 +*N mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 53.645 25.160 + +*CAP +0 mux_right_ipin_9\/mux_l1_in_1_:X 1e-06 +1 mux_right_ipin_9\/mux_l2_in_0_:A0 1e-06 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.7085e-05 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0005923067 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0005712734 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003923037 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003923037 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.156231e-05 +8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.99797e-05 +9 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_bottom_in[18]:26 2.341624e-06 +10 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[18]:4 0.0002084759 +11 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[18]:26 7.414239e-06 +12 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_in[18]:25 0.0002108175 +13 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_in[18]:27 7.414239e-06 +14 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:210 7.57347e-05 +15 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:211 7.57347e-05 +16 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.871394e-05 +17 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.871394e-05 + +*RES +0 mux_right_ipin_9\/mux_l1_in_1_:X mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_9\/mux_l2_in_0_:A0 0.152 +2 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.01063839 +3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.006598215 +6 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001548913 +7 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00123105 //LENGTH 8.920 LUMPCC 0.0001223702 DR + +*CONN +*I mux_right_ipin_12\/mux_l2_in_2_:X O *L 0 *C 27.775 17.000 +*I mux_right_ipin_12\/mux_l3_in_1_:A1 I *L 0.00198 *C 22.445 20.060 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 22.445 20.060 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 22.540 20.015 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 22.540 17.045 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 22.585 17.000 +*N mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 27.738 17.000 + +*CAP +0 mux_right_ipin_12\/mux_l2_in_2_:X 1e-06 +1 mux_right_ipin_12\/mux_l3_in_1_:A1 1e-06 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.692215e-05 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001940814 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001940814 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003457975 +6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003457975 +7 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_7_sram[1]:17 4.58435e-06 +8 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:20 2.830589e-05 +9 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:23 7.951667e-06 +10 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:24 4.740899e-06 +11 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:25 1.560232e-05 +12 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:16 4.58435e-06 +13 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:19 2.830589e-05 +14 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:20 5.618843e-06 +15 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:22 2.332823e-06 +16 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:23 4.740899e-06 +17 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:24 1.560232e-05 + +*RES +0 mux_right_ipin_12\/mux_l2_in_2_:X mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_12\/mux_l3_in_1_:A1 0.152 +2 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002651786 +5 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_12/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.004600447 + +*END + +*D_NET mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0010583 //LENGTH 7.560 LUMPCC 0.0003029989 DR + +*CONN +*I mux_right_ipin_13\/mux_l2_in_3_:X O *L 0 *C 51.805 15.640 +*I mux_right_ipin_13\/mux_l3_in_1_:A0 I *L 0.001631 *C 50.435 21.080 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 50.435 21.080 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 50.600 21.080 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 50.600 21.035 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 50.600 15.685 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 50.645 15.640 +*N mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 51.768 15.640 + +*CAP +0 mux_right_ipin_13\/mux_l2_in_3_:X 1e-06 +1 mux_right_ipin_13\/mux_l3_in_1_:A0 1e-06 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.191686e-05 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.770363e-05 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002207174 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002207174 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001011228 +7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001011228 +8 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_bottom_in[2]:60 0.0001514994 +9 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_bottom_in[2]:56 0.0001514994 + +*RES +0 mux_right_ipin_13\/mux_l2_in_3_:X mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001002232 +2 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004776786 +4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.967391e-05 +5 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_right_ipin_13/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_13\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008788109 //LENGTH 7.560 LUMPCC 0 DR + +*CONN +*I mux_right_ipin_2\/mux_l3_in_0_:X O *L 0 *C 12.595 88.740 +*I mux_right_ipin_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 11.405 94.180 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 11.443 94.180 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 11.915 94.180 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 11.960 94.135 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 11.960 88.785 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 12.005 88.740 +*N mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 12.558 88.740 + +*CAP +0 mux_right_ipin_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_2\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.88825e-05 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.88825e-05 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003022894 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003022894 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.723355e-05 +7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.723355e-05 + +*RES +0 mux_right_ipin_2\/mux_l3_in_0_:X mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_2\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004776786 +6 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_ipin_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001849408 //LENGTH 13.575 LUMPCC 0.000228946 DR + +*CONN +*I mux_right_ipin_3\/mux_l3_in_1_:X O *L 0 *C 21.335 66.300 +*I mux_right_ipin_3\/mux_l4_in_0_:A0 I *L 0.005103 *C 13.340 64.760 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 13.303 64.760 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 12.005 64.710 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 11.960 64.645 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 11.960 65.915 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 12.005 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 15.180 65.960 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 15.180 66.300 +*N mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 21.297 66.300 + +*CAP +0 mux_right_ipin_3\/mux_l3_in_1_:X 1e-06 +1 mux_right_ipin_3\/mux_l4_in_0_:A0 1e-06 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001168784 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001168784 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000104218 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000104218 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001630575 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001880451 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.000425077 +9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0004000894 +10 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size8_1_sram[1]:15 0.0001140115 +11 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:17 4.61456e-07 +12 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:18 4.61456e-07 +13 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size8_1_sram[1]:16 0.0001140115 + +*RES +0 mux_right_ipin_3\/mux_l3_in_1_:X mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.005462054 +2 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001133929 +4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001158482 +5 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_ipin_3\/mux_l4_in_0_:A0 0.152 +7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002834822 +8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_ipin_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003035715 + +*END + +*D_NET mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008179559 //LENGTH 6.355 LUMPCC 0.000214607 DR + +*CONN +*I mux_right_ipin_7\/mux_l2_in_0_:X O *L 0 *C 62.385 86.360 +*I mux_right_ipin_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 63.580 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 63.543 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 62.605 90.780 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.560 90.735 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.560 86.405 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.560 86.360 +*N mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.385 86.360 + +*CAP +0 mux_right_ipin_7\/mux_l2_in_0_:X 1e-06 +1 mux_right_ipin_7\/mux_l3_in_0_:A1 1e-06 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.235206e-05 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.235206e-05 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001727502 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001727502 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.571565e-05 +7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.542874e-05 +8 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.58925e-05 +9 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.58925e-05 +10 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.141098e-05 +11 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.141098e-05 + +*RES +0 mux_right_ipin_7\/mux_l2_in_0_:X mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_ipin_7\/mux_l3_in_0_:A1 0.152 +2 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008370536 +3 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_ipin_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001655798 //LENGTH 14.660 LUMPCC 0.0003999892 DR + +*CONN +*I mux_right_ipin_10\/mux_l3_in_0_:X O *L 0 *C 9.835 33.660 +*I mux_right_ipin_10\/mux_l4_in_0_:A1 I *L 0.00198 *C 7.265 45.220 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 7.265 45.220 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 7.360 45.175 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 7.360 33.705 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 7.405 33.660 +*N mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 9.798 33.660 + +*CAP +0 mux_right_ipin_10\/mux_l3_in_0_:X 1e-06 +1 mux_right_ipin_10\/mux_l4_in_0_:A1 1e-06 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.962263e-05 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0004735168 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004735168 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001385763 +6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001385763 +7 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 left_grid_pin_12_[0]:3 5.505869e-05 +8 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 left_grid_pin_12_[0]:4 5.505869e-05 +9 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_4_sram[2]:5 2.915403e-05 +10 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_4_sram[2]:9 1.713769e-05 +11 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_4_sram[2]:14 3.700701e-05 +12 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_4_sram[2]:12 1.609166e-05 +13 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_4_sram[2]:9 2.915403e-05 +14 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_4_sram[2]:13 3.700701e-05 +15 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_4_sram[2]:14 1.713769e-05 +16 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_4_sram[2]:11 1.609166e-05 +17 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.554551e-05 +18 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.554551e-05 + +*RES +0 mux_right_ipin_10\/mux_l3_in_0_:X mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_ipin_10\/mux_l4_in_0_:A1 0.152 +2 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.01024107 +5 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_ipin_10/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.002136161 + +*END + +*D_NET mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006244485 //LENGTH 4.405 LUMPCC 0.0001352294 DR + +*CONN +*I mux_right_ipin_14\/mux_l1_in_0_:X O *L 0 *C 33.865 41.480 +*I mux_right_ipin_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 37.360 41.820 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 37.323 41.820 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.800 41.820 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.800 41.480 +*N mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 33.903 41.480 + +*CAP +0 mux_right_ipin_14\/mux_l1_in_0_:X 1e-06 +1 mux_right_ipin_14\/mux_l2_in_0_:A1 1e-06 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.01979e-05 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.570802e-05 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002034117 +5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001779016 +6 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size8_6_sram[0]:4 2.83498e-05 +7 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size8_6_sram[0]:3 3.926491e-05 +8 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size8_6_sram[0]:4 3.926491e-05 +9 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size8_6_sram[0]:3 2.83498e-05 + +*RES +0 mux_right_ipin_14\/mux_l1_in_0_:X mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_ipin_14\/mux_l2_in_0_:A1 0.152 +2 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002587054 +3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035714 +4 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_ipin_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004665179 + +*END + +*D_NET mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001062991 //LENGTH 7.350 LUMPCC 0.0003979752 DR + +*CONN +*I mux_right_ipin_15\/mux_l2_in_1_:X O *L 0 *C 66.415 85.340 +*I mux_right_ipin_15\/mux_l3_in_0_:A0 I *L 0.001631 *C 64.575 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 64.575 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 64.400 80.920 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 64.400 80.965 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 64.400 85.295 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 64.445 85.340 +*N mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 66.377 85.340 + +*CAP +0 mux_right_ipin_15\/mux_l2_in_1_:X 1e-06 +1 mux_right_ipin_15\/mux_l3_in_0_:A0 1e-06 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.758318e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.187909e-05 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001266935 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001266935 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000155083 +7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000155083 +8 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[10]:27 0.0001300344 +9 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[10] 0.0001300344 +10 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_3_sram[1]:22 1.24301e-05 +11 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_3_sram[1]:23 5.652307e-05 +12 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:19 1.24301e-05 +13 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:22 5.652307e-05 + +*RES +0 mux_right_ipin_15\/mux_l2_in_1_:X mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_ipin_15\/mux_l3_in_0_:A0 0.152 +2 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.51087e-05 +3 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_ipin_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 + +*END + +*D_NET chany_top_out[3] 0.001345483 //LENGTH 9.710 LUMPCC 0 DR + +*CONN +*I FTB_4__3:X O *L 0 *C 66.240 104.720 +*P chany_top_out[3] O *L 0.7423 *C 59.800 107.475 +*N chany_top_out[3]:2 *C 59.800 104.778 +*N chany_top_out[3]:3 *C 59.808 104.720 +*N chany_top_out[3]:4 *C 66.233 104.720 +*N chany_top_out[3]:5 *C 66.240 104.720 +*N chany_top_out[3]:6 *C 66.240 104.720 + +*CAP +0 FTB_4__3:X 1e-06 +1 chany_top_out[3] 0.0001880074 +2 chany_top_out[3]:2 0.0001880074 +3 chany_top_out[3]:3 0.0004485756 +4 chany_top_out[3]:4 0.0004485756 +5 chany_top_out[3]:5 3.841261e-05 +6 chany_top_out[3]:6 3.290411e-05 + +*RES +0 FTB_4__3:X chany_top_out[3]:6 0.152 +1 chany_top_out[3]:2 chany_top_out[3] 0.002408482 +2 chany_top_out[3]:3 chany_top_out[3]:2 0.00341 +3 chany_top_out[3]:5 chany_top_out[3]:4 0.00341 +4 chany_top_out[3]:4 chany_top_out[3]:3 0.001006583 +5 chany_top_out[3]:6 chany_top_out[3]:5 0.0045 + +*END + +*D_NET chany_top_out[1] 0.000730171 //LENGTH 5.675 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 38.180 104.040 +*P chany_top_out[1] O *L 0.7423 *C 38.640 107.475 +*N chany_top_out[1]:2 *C 39.100 107.440 +*N chany_top_out[1]:3 *C 39.100 104.085 +*N chany_top_out[1]:4 *C 39.100 104.040 +*N chany_top_out[1]:5 *C 38.218 104.040 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 chany_top_out[1] 3.614896e-05 +2 chany_top_out[1]:2 0.0002454837 +3 chany_top_out[1]:3 0.0002093348 +4 chany_top_out[1]:4 0.0001373266 +5 chany_top_out[1]:5 0.0001008769 + +*RES +0 ropt_mt_inst_738:X chany_top_out[1]:5 0.152 +1 chany_top_out[1]:5 chany_top_out[1]:4 0.0007879465 +2 chany_top_out[1]:4 chany_top_out[1]:3 0.0045 +3 chany_top_out[1]:3 chany_top_out[1]:2 0.002995536 +4 chany_top_out[1]:2 chany_top_out[1] 0.0004107143 + +*END + +*D_NET chany_top_out[8] 0.001592728 //LENGTH 10.940 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 50.140 101.320 +*P chany_top_out[8] O *L 0.7423 *C 49.220 107.780 +*N chany_top_out[8]:2 *C 49.220 107.145 +*N chany_top_out[8]:3 *C 49.265 107.100 +*N chany_top_out[8]:4 *C 51.475 107.100 +*N chany_top_out[8]:5 *C 51.520 107.055 +*N chany_top_out[8]:6 *C 51.520 101.365 +*N chany_top_out[8]:7 *C 51.475 101.320 +*N chany_top_out[8]:8 *C 50.178 101.320 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 chany_top_out[8] 4.293363e-05 +2 chany_top_out[8]:2 4.293363e-05 +3 chany_top_out[8]:3 0.0001961622 +4 chany_top_out[8]:4 0.0001961622 +5 chany_top_out[8]:5 0.0004171857 +6 chany_top_out[8]:6 0.0004171857 +7 chany_top_out[8]:7 0.0001395823 +8 chany_top_out[8]:8 0.0001395823 + +*RES +0 ropt_mt_inst_778:X chany_top_out[8]:8 0.152 +1 chany_top_out[8]:8 chany_top_out[8]:7 0.001158482 +2 chany_top_out[8]:7 chany_top_out[8]:6 0.0045 +3 chany_top_out[8]:6 chany_top_out[8]:5 0.005080358 +4 chany_top_out[8]:4 chany_top_out[8]:3 0.001973214 +5 chany_top_out[8]:5 chany_top_out[8]:4 0.0045 +6 chany_top_out[8]:3 chany_top_out[8]:2 0.0045 +7 chany_top_out[8]:2 chany_top_out[8] 0.0002946429 + +*END + +*D_NET ropt_net_172 0.001422241 //LENGTH 9.960 LUMPCC 0.0005688402 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 48.010 97.240 +*I ropt_mt_inst_781:A I *L 0.001767 *C 46.460 104.720 +*N ropt_net_172:2 *C 46.498 104.720 +*N ropt_net_172:3 *C 47.335 104.720 +*N ropt_net_172:4 *C 47.380 104.675 +*N ropt_net_172:5 *C 47.380 97.285 +*N ropt_net_172:6 *C 47.425 97.240 +*N ropt_net_172:7 *C 47.973 97.240 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 ropt_mt_inst_781:A 1e-06 +2 ropt_net_172:2 9.419568e-05 +3 ropt_net_172:3 9.419568e-05 +4 ropt_net_172:4 0.0002698133 +5 ropt_net_172:5 0.0002698133 +6 ropt_net_172:6 6.169122e-05 +7 ropt_net_172:7 6.169122e-05 +8 ropt_net_172:4 chany_bottom_in[11]:11 7.833025e-05 +9 ropt_net_172:5 chany_bottom_in[11]:12 7.833025e-05 +10 ropt_net_172:4 chany_bottom_in[16]:9 7.604252e-05 +11 ropt_net_172:5 chany_bottom_in[16]:8 7.604252e-05 +12 ropt_net_172:4 ropt_net_143:9 0.0001300473 +13 ropt_net_172:5 ropt_net_143:10 0.0001300473 + +*RES +0 ropt_mt_inst_746:X ropt_net_172:7 0.152 +1 ropt_net_172:2 ropt_mt_inst_781:A 0.152 +2 ropt_net_172:3 ropt_net_172:2 0.0007477679 +3 ropt_net_172:4 ropt_net_172:3 0.0045 +4 ropt_net_172:6 ropt_net_172:5 0.0045 +5 ropt_net_172:5 ropt_net_172:4 0.006598215 +6 ropt_net_172:7 ropt_net_172:6 0.0004888393 + +*END + +*D_NET chany_bottom_out[17] 0.001784866 //LENGTH 12.915 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 59.340 6.120 +*P chany_bottom_out[17] O *L 0.7423 *C 52.900 1.325 +*N chany_bottom_out[17]:2 *C 53.360 1.360 +*N chany_bottom_out[17]:3 *C 53.360 3.355 +*N chany_bottom_out[17]:4 *C 53.405 3.400 +*N chany_bottom_out[17]:5 *C 57.960 3.400 +*N chany_bottom_out[17]:6 *C 57.960 3.445 +*N chany_bottom_out[17]:7 *C 57.960 6.075 +*N chany_bottom_out[17]:8 *C 58.005 6.120 +*N chany_bottom_out[17]:9 *C 59.303 6.120 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 chany_bottom_out[17] 3.127141e-05 +2 chany_bottom_out[17]:2 0.0001790586 +3 chany_bottom_out[17]:3 0.0001477872 +4 chany_bottom_out[17]:4 0.0003872476 +5 chany_bottom_out[17]:5 0.0004212701 +6 chany_bottom_out[17]:6 0.0002013808 +7 chany_bottom_out[17]:7 0.0002013808 +8 chany_bottom_out[17]:8 0.0001072346 +9 chany_bottom_out[17]:9 0.0001072346 + +*RES +0 ropt_mt_inst_751:X chany_bottom_out[17]:9 0.152 +1 chany_bottom_out[17]:9 chany_bottom_out[17]:8 0.001158482 +2 chany_bottom_out[17]:8 chany_bottom_out[17]:7 0.0045 +3 chany_bottom_out[17]:7 chany_bottom_out[17]:6 0.002348214 +4 chany_bottom_out[17]:5 chany_bottom_out[17]:4 0.004066964 +5 chany_bottom_out[17]:6 chany_bottom_out[17]:5 0.0045 +6 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.0045 +7 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.00178125 +8 chany_bottom_out[17]:2 chany_bottom_out[17] 0.0004107143 + +*END + +*D_NET ropt_net_166 0.001137229 //LENGTH 8.445 LUMPCC 0 DR + +*CONN +*I BUFT_RR_63:X O *L 0 *C 57.500 99.960 +*I ropt_mt_inst_770:A I *L 0.001766 *C 53.360 96.560 +*N ropt_net_166:2 *C 53.360 96.560 +*N ropt_net_166:3 *C 53.360 96.605 +*N ropt_net_166:4 *C 53.360 99.235 +*N ropt_net_166:5 *C 53.405 99.280 +*N ropt_net_166:6 *C 53.820 99.280 +*N ropt_net_166:7 *C 53.820 99.960 +*N ropt_net_166:8 *C 57.463 99.960 + +*CAP +0 BUFT_RR_63:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_166:2 3.529183e-05 +3 ropt_net_166:3 0.0001681094 +4 ropt_net_166:4 0.0001681094 +5 ropt_net_166:5 4.774878e-05 +6 ropt_net_166:6 9.420307e-05 +7 ropt_net_166:7 0.0003341102 +8 ropt_net_166:8 0.0002876559 + +*RES +0 BUFT_RR_63:X ropt_net_166:8 0.152 +1 ropt_net_166:2 ropt_mt_inst_770:A 0.152 +2 ropt_net_166:3 ropt_net_166:2 0.0045 +3 ropt_net_166:5 ropt_net_166:4 0.0045 +4 ropt_net_166:4 ropt_net_166:3 0.002348214 +5 ropt_net_166:8 ropt_net_166:7 0.003252232 +6 ropt_net_166:6 ropt_net_166:5 0.0003705357 +7 ropt_net_166:7 ropt_net_166:6 0.0006071429 + +*END + +*D_NET chany_bottom_out[8] 0.001582294 //LENGTH 11.320 LUMPCC 0.0001220091 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 48.460 7.140 +*P chany_bottom_out[8] O *L 0.7423 *C 43.700 1.325 +*N chany_bottom_out[8]:2 *C 43.700 3.060 +*N chany_bottom_out[8]:3 *C 44.160 3.060 +*N chany_bottom_out[8]:4 *C 44.160 7.095 +*N chany_bottom_out[8]:5 *C 44.205 7.140 +*N chany_bottom_out[8]:6 *C 48.422 7.140 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 chany_bottom_out[8] 0.0001069756 +2 chany_bottom_out[8]:2 0.000138308 +3 chany_bottom_out[8]:3 0.000261362 +4 chany_bottom_out[8]:4 0.0002300295 +5 chany_bottom_out[8]:5 0.0003613051 +6 chany_bottom_out[8]:6 0.0003613051 +7 chany_bottom_out[8]:4 ropt_net_177:3 6.100453e-05 +8 chany_bottom_out[8]:3 ropt_net_177:4 6.100453e-05 + +*RES +0 ropt_mt_inst_786:X chany_bottom_out[8]:6 0.152 +1 chany_bottom_out[8]:5 chany_bottom_out[8]:4 0.0045 +2 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.003602679 +3 chany_bottom_out[8]:6 chany_bottom_out[8]:5 0.003765625 +4 chany_bottom_out[8]:2 chany_bottom_out[8] 0.001549107 +5 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0004107143 + +*END + +*D_NET ropt_net_180 0.00188566 //LENGTH 14.435 LUMPCC 0.0001654345 DR + +*CONN +*I BUFT_RR_84:X O *L 0 *C 30.555 99.960 +*I ropt_mt_inst_791:A I *L 0.001766 *C 40.020 102.000 +*N ropt_net_180:2 *C 39.983 102.000 +*N ropt_net_180:3 *C 38.685 102.000 +*N ropt_net_180:4 *C 38.640 102.045 +*N ropt_net_180:5 *C 38.640 102.635 +*N ropt_net_180:6 *C 38.595 102.680 +*N ropt_net_180:7 *C 34.545 102.680 +*N ropt_net_180:8 *C 34.500 102.635 +*N ropt_net_180:9 *C 34.500 100.005 +*N ropt_net_180:10 *C 34.455 99.960 +*N ropt_net_180:11 *C 30.593 99.960 + +*CAP +0 BUFT_RR_84:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_180:2 8.583541e-05 +3 ropt_net_180:3 8.583541e-05 +4 ropt_net_180:4 5.320621e-05 +5 ropt_net_180:5 5.320621e-05 +6 ropt_net_180:6 0.0002759675 +7 ropt_net_180:7 0.0002759675 +8 ropt_net_180:8 0.0001706239 +9 ropt_net_180:9 0.0001706239 +10 ropt_net_180:10 0.0002734796 +11 ropt_net_180:11 0.0002734796 +12 ropt_net_180:2 chany_top_out[14]:4 3.187951e-05 +13 ropt_net_180:3 chany_top_out[14]:3 3.187951e-05 +14 ropt_net_180:4 chany_top_out[14]:2 5.916625e-06 +15 ropt_net_180:6 chany_top_out[14]:4 4.492113e-05 +16 ropt_net_180:5 chany_top_out[14] 5.916625e-06 +17 ropt_net_180:7 chany_top_out[14]:3 4.492113e-05 + +*RES +0 BUFT_RR_84:X ropt_net_180:11 0.152 +1 ropt_net_180:2 ropt_mt_inst_791:A 0.152 +2 ropt_net_180:3 ropt_net_180:2 0.001158482 +3 ropt_net_180:4 ropt_net_180:3 0.0045 +4 ropt_net_180:6 ropt_net_180:5 0.0045 +5 ropt_net_180:5 ropt_net_180:4 0.0005267857 +6 ropt_net_180:7 ropt_net_180:6 0.003616072 +7 ropt_net_180:8 ropt_net_180:7 0.0045 +8 ropt_net_180:10 ropt_net_180:9 0.0045 +9 ropt_net_180:9 ropt_net_180:8 0.002348214 +10 ropt_net_180:11 ropt_net_180:10 0.003448661 + +*END + +*D_NET ropt_net_143 0.003066074 //LENGTH 20.570 LUMPCC 0.0007392172 DR + +*CONN +*I BUFT_P_111:X O *L 0 *C 48.035 94.180 +*I ropt_mt_inst_742:A I *L 0.001766 *C 55.660 104.720 +*N ropt_net_143:2 *C 55.660 104.720 +*N ropt_net_143:3 *C 55.660 104.675 +*N ropt_net_143:4 *C 55.660 101.705 +*N ropt_net_143:5 *C 55.615 101.660 +*N ropt_net_143:6 *C 48.300 101.660 +*N ropt_net_143:7 *C 48.300 102.000 +*N ropt_net_143:8 *C 47.885 102.000 +*N ropt_net_143:9 *C 47.840 101.955 +*N ropt_net_143:10 *C 47.840 94.225 +*N ropt_net_143:11 *C 47.840 94.180 +*N ropt_net_143:12 *C 48.035 94.180 + +*CAP +0 BUFT_P_111:X 1e-06 +1 ropt_mt_inst_742:A 1e-06 +2 ropt_net_143:2 3.401255e-05 +3 ropt_net_143:3 0.0001971909 +4 ropt_net_143:4 0.0001971909 +5 ropt_net_143:5 0.0005221308 +6 ropt_net_143:6 0.0005391153 +7 ropt_net_143:7 7.18667e-05 +8 ropt_net_143:8 5.488215e-05 +9 ropt_net_143:9 0.0002848352 +10 ropt_net_143:10 0.0002848352 +11 ropt_net_143:11 6.802873e-05 +12 ropt_net_143:12 7.076807e-05 +13 ropt_net_143:10 chany_bottom_in[8]:7 7.802475e-05 +14 ropt_net_143:8 chany_bottom_in[8]:9 5.583101e-06 +15 ropt_net_143:9 chany_bottom_in[8]:8 7.802475e-05 +16 ropt_net_143:7 chany_bottom_in[8]:8 1.831003e-05 +17 ropt_net_143:6 chany_bottom_in[8]:7 1.272693e-05 +18 ropt_net_143:5 ropt_net_153:3 6.087149e-05 +19 ropt_net_143:4 ropt_net_153:5 1.683323e-05 +20 ropt_net_143:3 ropt_net_153:4 1.683323e-05 +21 ropt_net_143:6 ropt_net_153:2 6.087149e-05 +22 ropt_net_143:10 ropt_net_147:8 6.552182e-05 +23 ropt_net_143:9 ropt_net_147:7 6.552182e-05 +24 ropt_net_143:10 ropt_net_172:5 0.0001300473 +25 ropt_net_143:9 ropt_net_172:4 0.0001300473 + +*RES +0 BUFT_P_111:X ropt_net_143:12 0.152 +1 ropt_net_143:12 ropt_net_143:11 0.0001059783 +2 ropt_net_143:11 ropt_net_143:10 0.0045 +3 ropt_net_143:10 ropt_net_143:9 0.006901786 +4 ropt_net_143:8 ropt_net_143:7 0.0003705357 +5 ropt_net_143:9 ropt_net_143:8 0.0045 +6 ropt_net_143:5 ropt_net_143:4 0.0045 +7 ropt_net_143:4 ropt_net_143:3 0.002651786 +8 ropt_net_143:2 ropt_mt_inst_742:A 0.152 +9 ropt_net_143:3 ropt_net_143:2 0.0045 +10 ropt_net_143:7 ropt_net_143:6 0.0003035715 +11 ropt_net_143:6 ropt_net_143:5 0.00653125 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..7696139 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef @@ -0,0 +1,12417 @@ +*SPEF "1481-1998" +*DESIGN "sb_0__0_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 14.720 102.680 +chany_top_in[0] I *C 67.620 102.680 +chany_top_in[1] I *C 62.100 102.680 +chany_top_in[2] I *C 70.380 102.680 +chany_top_in[3] I *C 45.540 102.680 +chany_top_in[4] I *C 43.700 102.680 +chany_top_in[5] I *C 28.980 102.680 +chany_top_in[6] I *C 69.460 102.680 +chany_top_in[7] I *C 68.540 102.680 +chany_top_in[8] I *C 63.020 102.680 +chany_top_in[9] I *C 51.980 102.680 +chany_top_in[10] I *C 50.140 102.680 +chany_top_in[11] I *C 41.860 102.680 +chany_top_in[12] I *C 72.220 102.680 +chany_top_in[13] I *C 20.240 102.680 +chany_top_in[14] I *C 29.440 102.680 +chany_top_in[15] I *C 49.680 102.680 +chany_top_in[16] I *C 58.880 102.680 +chany_top_in[17] I *C 14.720 102.680 +chany_top_in[18] I *C 44.160 102.680 +chany_top_in[19] I *C 47.380 102.680 +top_left_grid_pin_1_[0] I *C 2.300 102.680 +chanx_right_in[0] I *C 112.470 46.240 +chanx_right_in[1] I *C 112.470 16.320 +chanx_right_in[2] I *C 112.470 12.240 +chanx_right_in[3] I *C 112.470 8.160 +chanx_right_in[4] I *C 112.470 13.600 +chanx_right_in[5] I *C 112.470 9.520 +chanx_right_in[6] I *C 112.470 31.280 +chanx_right_in[7] I *C 112.470 47.600 +chanx_right_in[8] I *C 112.470 14.960 +chanx_right_in[9] I *C 112.470 72.080 +chanx_right_in[10] I *C 112.470 25.840 +chanx_right_in[11] I *C 112.470 29.920 +chanx_right_in[12] I *C 112.470 19.040 +chanx_right_in[13] I *C 112.470 44.880 +chanx_right_in[14] I *C 112.470 17.680 +chanx_right_in[15] I *C 112.470 42.160 +chanx_right_in[16] I *C 112.470 4.080 +chanx_right_in[17] I *C 112.470 63.920 +chanx_right_in[18] I *C 112.470 50.320 +chanx_right_in[19] I *C 112.470 58.480 +right_top_grid_pin_42_[0] I *C 109.940 75.480 +right_top_grid_pin_43_[0] I *C 83.950 99.280 +right_top_grid_pin_44_[0] I *C 110.860 75.480 +right_top_grid_pin_45_[0] I *C 109.020 75.480 +right_top_grid_pin_46_[0] I *C 83.950 91.800 +right_top_grid_pin_47_[0] I *C 83.950 90.440 +right_top_grid_pin_48_[0] I *C 107.180 75.480 +right_top_grid_pin_49_[0] I *C 108.100 75.480 +right_bottom_grid_pin_1_[0] I *C 109.940 0.680 +ccff_head[0] I *C 110.860 0.680 +chany_top_out[0] O *C 42.780 102.680 +chany_top_out[1] O *C 25.760 102.680 +chany_top_out[2] O *C 71.300 102.680 +chany_top_out[3] O *C 49.220 102.680 +chany_top_out[4] O *C 36.340 102.680 +chany_top_out[5] O *C 44.620 102.680 +chany_top_out[6] O *C 5.520 102.680 +chany_top_out[7] O *C 69.000 102.680 +chany_top_out[8] O *C 22.080 102.680 +chany_top_out[9] O *C 9.200 102.680 +chany_top_out[10] O *C 46.460 102.680 +chany_top_out[11] O *C 51.060 102.680 +chany_top_out[12] O *C 7.360 102.680 +chany_top_out[13] O *C 23.920 102.680 +chany_top_out[14] O *C 7.360 102.680 +chany_top_out[15] O *C 46.000 102.680 +chany_top_out[16] O *C 48.300 102.680 +chany_top_out[17] O *C 52.900 102.680 +chany_top_out[18] O *C 47.840 102.680 +chany_top_out[19] O *C 25.760 102.680 +chanx_right_out[0] O *C 112.470 59.840 +chanx_right_out[1] O *C 112.470 66.640 +chanx_right_out[2] O *C 112.470 6.800 +chanx_right_out[3] O *C 112.470 68.000 +chanx_right_out[4] O *C 112.470 35.360 +chanx_right_out[5] O *C 112.470 57.120 +chanx_right_out[6] O *C 112.470 28.560 +chanx_right_out[7] O *C 112.470 51.680 +chanx_right_out[8] O *C 112.470 34.000 +chanx_right_out[9] O *C 112.470 40.800 +chanx_right_out[10] O *C 112.470 24.480 +chanx_right_out[11] O *C 112.470 55.760 +chanx_right_out[12] O *C 112.470 69.360 +chanx_right_out[13] O *C 112.470 61.200 +chanx_right_out[14] O *C 112.470 23.120 +chanx_right_out[15] O *C 112.470 39.440 +chanx_right_out[16] O *C 112.470 36.720 +chanx_right_out[17] O *C 112.470 62.560 +chanx_right_out[18] O *C 112.470 20.400 +chanx_right_out[19] O *C 112.470 53.040 +ccff_tail[0] O *C 0.690 68.680 +VDD I *C 56.580 51.680 +VSS I *C 56.580 51.680 + +*D_NET chany_top_in[13] 0.01705342 //LENGTH 169.625 LUMPCC 0.003089438 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 20.240 102.150 +*I ropt_mt_inst_748:A I *L 0.001767 *C 106.260 23.120 +*N chany_top_in[13]:2 *C 19.840 87.040 +*N chany_top_in[13]:3 *C 106.223 23.120 +*N chany_top_in[13]:4 *C 104.925 23.120 +*N chany_top_in[13]:5 *C 104.880 23.165 +*N chany_top_in[13]:6 *C 104.880 28.855 +*N chany_top_in[13]:7 *C 104.835 28.900 +*N chany_top_in[13]:8 *C 100.280 28.900 +*N chany_top_in[13]:9 *C 100.360 29.240 +*N chany_top_in[13]:10 *C 100.290 29.195 +*N chany_top_in[13]:11 *C 100.280 28.605 +*N chany_top_in[13]:12 *C 100.235 28.560 +*N chany_top_in[13]:13 *C 99.360 28.560 +*N chany_top_in[13]:14 *C 99.360 28.900 +*N chany_top_in[13]:15 *C 70.080 28.900 +*N chany_top_in[13]:16 *C 20.285 28.900 +*N chany_top_in[13]:17 *C 20.240 28.945 +*N chany_top_in[13]:18 *C 20.240 78.740 +*N chany_top_in[13]:19 *C 20.240 86.983 +*N chany_top_in[13]:20 *C 20.240 87.040 +*N chany_top_in[13]:21 *C 20.240 87.047 + +*CAP +0 chany_top_in[13] 0.0006795235 +1 ropt_mt_inst_748:A 1e-06 +2 chany_top_in[13]:2 5.245576e-05 +3 chany_top_in[13]:3 8.921875e-05 +4 chany_top_in[13]:4 8.921875e-05 +5 chany_top_in[13]:5 0.0002487939 +6 chany_top_in[13]:6 0.0002487939 +7 chany_top_in[13]:7 0.0002734233 +8 chany_top_in[13]:8 0.0002975503 +9 chany_top_in[13]:9 5.130829e-05 +10 chany_top_in[13]:10 6.107725e-05 +11 chany_top_in[13]:11 6.107725e-05 +12 chany_top_in[13]:12 6.22564e-05 +13 chany_top_in[13]:13 8.202481e-05 +14 chany_top_in[13]:14 0.001589375 +15 chany_top_in[13]:15 0.004054883 +16 chany_top_in[13]:16 0.002485276 +17 chany_top_in[13]:17 0.001208578 +18 chany_top_in[13]:18 0.001402371 +19 chany_top_in[13]:19 0.0001937932 +20 chany_top_in[13]:20 5.245576e-05 +21 chany_top_in[13]:21 0.0006795235 +22 chany_top_in[13] chany_top_in[17] 2.562183e-05 +23 chany_top_in[13] chany_top_in[17]:11 5.509636e-06 +24 chany_top_in[13]:5 chany_top_in[17]:4 4.461578e-05 +25 chany_top_in[13]:6 chany_top_in[17]:5 4.461578e-05 +26 chany_top_in[13]:17 chany_top_in[17]:9 0.0004689837 +27 chany_top_in[13]:17 chany_top_in[17]:10 3.223612e-05 +28 chany_top_in[13]:19 chany_top_in[17]:11 8.881444e-05 +29 chany_top_in[13]:21 chany_top_in[17]:14 2.562183e-05 +30 chany_top_in[13]:21 chany_top_in[17]:10 5.509636e-06 +31 chany_top_in[13]:18 chany_top_in[17]:11 3.223612e-05 +32 chany_top_in[13]:18 chany_top_in[17]:10 0.0005577982 +33 chany_top_in[13]:17 chanx_right_in[10]:10 0.0007001939 +34 chany_top_in[13]:17 chanx_right_in[10]:9 4.77273e-05 +35 chany_top_in[13]:19 chanx_right_in[10]:8 0.0001310165 +36 chany_top_in[13]:18 chanx_right_in[10]:8 4.77273e-05 +37 chany_top_in[13]:18 chanx_right_in[10]:9 0.0008312103 + +*RES +0 chany_top_in[13] chany_top_in[13]:21 0.002366058 +1 chany_top_in[13]:3 ropt_mt_inst_748:A 0.152 +2 chany_top_in[13]:4 chany_top_in[13]:3 0.001158482 +3 chany_top_in[13]:5 chany_top_in[13]:4 0.0045 +4 chany_top_in[13]:7 chany_top_in[13]:6 0.0045 +5 chany_top_in[13]:6 chany_top_in[13]:5 0.005080357 +6 chany_top_in[13]:9 chany_top_in[13]:8 0.0003035715 +7 chany_top_in[13]:10 chany_top_in[13]:9 0.0045 +8 chany_top_in[13]:12 chany_top_in[13]:11 0.0045 +9 chany_top_in[13]:11 chany_top_in[13]:10 0.0005267857 +10 chany_top_in[13]:16 chany_top_in[13]:15 0.04445983 +11 chany_top_in[13]:17 chany_top_in[13]:16 0.0045 +12 chany_top_in[13]:19 chany_top_in[13]:18 0.007359375 +13 chany_top_in[13]:20 chany_top_in[13]:19 0.00341 +14 chany_top_in[13]:20 chany_top_in[13]:2 5.69697e-05 +15 chany_top_in[13]:21 chany_top_in[13]:20 0.00341 +16 chany_top_in[13]:14 chany_top_in[13]:13 0.0003035715 +17 chany_top_in[13]:13 chany_top_in[13]:12 0.00078125 +18 chany_top_in[13]:8 chany_top_in[13]:7 0.004066965 +19 chany_top_in[13]:15 chany_top_in[13]:14 0.02614286 +20 chany_top_in[13]:18 chany_top_in[13]:17 0.04445982 + +*END + +*D_NET chanx_right_in[14] 0.01836244 //LENGTH 177.645 LUMPCC 0.00316782 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 111.930 17.680 +*I ropt_mt_inst_735:A I *L 0.001767 *C 21.160 99.280 +*N chanx_right_in[14]:2 *C 21.198 99.280 +*N chanx_right_in[14]:3 *C 25.255 99.280 +*N chanx_right_in[14]:4 *C 25.300 99.235 +*N chanx_right_in[14]:5 *C 25.300 91.800 +*N chanx_right_in[14]:6 *C 25.760 91.800 +*N chanx_right_in[14]:7 *C 25.760 88.105 +*N chanx_right_in[14]:8 *C 25.805 88.060 +*N chanx_right_in[14]:9 *C 31.235 88.060 +*N chanx_right_in[14]:10 *C 31.280 88.015 +*N chanx_right_in[14]:11 *C 31.280 38.805 +*N chanx_right_in[14]:12 *C 31.325 38.760 +*N chanx_right_in[14]:13 *C 45.035 38.760 +*N chanx_right_in[14]:14 *C 45.080 38.805 +*N chanx_right_in[14]:15 *C 45.080 39.380 +*N chanx_right_in[14]:16 *C 45.080 39.425 +*N chanx_right_in[14]:17 *C 45.080 39.780 +*N chanx_right_in[14]:18 *C 47.380 39.780 +*N chanx_right_in[14]:19 *C 47.380 39.440 +*N chanx_right_in[14]:20 *C 47.380 39.395 +*N chanx_right_in[14]:21 *C 47.380 17.738 +*N chanx_right_in[14]:22 *C 47.388 17.680 +*N chanx_right_in[14]:23 *C 97.215 17.680 + +*CAP +0 chanx_right_in[14] 0.000353857 +1 ropt_mt_inst_735:A 1e-06 +2 chanx_right_in[14]:2 0.0002418215 +3 chanx_right_in[14]:3 0.0002418215 +4 chanx_right_in[14]:4 0.0004003538 +5 chanx_right_in[14]:5 0.0004278546 +6 chanx_right_in[14]:6 0.0002217493 +7 chanx_right_in[14]:7 0.0001942485 +8 chanx_right_in[14]:8 0.0003109014 +9 chanx_right_in[14]:9 0.0003109014 +10 chanx_right_in[14]:10 0.002082408 +11 chanx_right_in[14]:11 0.002082408 +12 chanx_right_in[14]:12 0.0007802031 +13 chanx_right_in[14]:13 0.0007802031 +14 chanx_right_in[14]:14 3.882679e-05 +15 chanx_right_in[14]:15 3.882679e-05 +16 chanx_right_in[14]:16 4.509201e-05 +17 chanx_right_in[14]:17 0.0001571198 +18 chanx_right_in[14]:18 0.0001606703 +19 chanx_right_in[14]:19 5.520835e-05 +20 chanx_right_in[14]:20 0.001001506 +21 chanx_right_in[14]:21 0.001001506 +22 chanx_right_in[14]:22 0.001956138 +23 chanx_right_in[14]:23 0.002309995 +24 chanx_right_in[14]:11 chanx_right_in[0]:5 0.000274747 +25 chanx_right_in[14]:10 chanx_right_in[0]:4 0.000274747 +26 chanx_right_in[14] chanx_right_in[12] 0.0001077329 +27 chanx_right_in[14] chanx_right_in[12]:36 0.0001526175 +28 chanx_right_in[14]:22 chanx_right_in[12]:35 8.299771e-05 +29 chanx_right_in[14]:23 chanx_right_in[12]:35 0.0001526175 +30 chanx_right_in[14]:23 chanx_right_in[12]:36 8.299771e-05 +31 chanx_right_in[14]:23 chanx_right_in[12]:37 0.0001077329 +32 chanx_right_in[14] chanx_right_in[1] 0.0003725494 +33 chanx_right_in[14]:22 chanx_right_in[1]:6 0.0005932653 +34 chanx_right_in[14]:23 chanx_right_in[1] 0.0005932653 +35 chanx_right_in[14]:23 chanx_right_in[1]:6 0.0003725494 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:23 0.00230535 +1 chanx_right_in[14]:13 chanx_right_in[14]:12 0.01224107 +2 chanx_right_in[14]:14 chanx_right_in[14]:13 0.0045 +3 chanx_right_in[14]:12 chanx_right_in[14]:11 0.0045 +4 chanx_right_in[14]:11 chanx_right_in[14]:10 0.0439375 +5 chanx_right_in[14]:9 chanx_right_in[14]:8 0.004848214 +6 chanx_right_in[14]:10 chanx_right_in[14]:9 0.0045 +7 chanx_right_in[14]:8 chanx_right_in[14]:7 0.0045 +8 chanx_right_in[14]:7 chanx_right_in[14]:6 0.003299107 +9 chanx_right_in[14]:3 chanx_right_in[14]:2 0.003622768 +10 chanx_right_in[14]:4 chanx_right_in[14]:3 0.0045 +11 chanx_right_in[14]:2 ropt_mt_inst_735:A 0.152 +12 chanx_right_in[14]:16 chanx_right_in[14]:15 0.0045 +13 chanx_right_in[14]:15 chanx_right_in[14]:14 0.0005133929 +14 chanx_right_in[14]:19 chanx_right_in[14]:18 0.0003035715 +15 chanx_right_in[14]:20 chanx_right_in[14]:19 0.0045 +16 chanx_right_in[14]:21 chanx_right_in[14]:20 0.01933706 +17 chanx_right_in[14]:22 chanx_right_in[14]:21 0.00341 +18 chanx_right_in[14]:17 chanx_right_in[14]:16 0.0003169643 +19 chanx_right_in[14]:18 chanx_right_in[14]:17 0.002053572 +20 chanx_right_in[14]:5 chanx_right_in[14]:4 0.006638392 +21 chanx_right_in[14]:6 chanx_right_in[14]:5 0.0004107143 +22 chanx_right_in[14]:23 chanx_right_in[14]:22 0.007806308 + +*END + +*D_NET chanx_right_in[17] 0.01147505 //LENGTH 80.780 LUMPCC 0.003678826 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 111.930 63.920 +*I BUFT_RR_62:A I *L 0.001776 *C 54.280 82.960 +*N chanx_right_in[17]:2 *C 54.318 82.960 +*N chanx_right_in[17]:3 *C 54.695 82.960 +*N chanx_right_in[17]:4 *C 54.740 82.915 +*N chanx_right_in[17]:5 *C 54.740 79.618 +*N chanx_right_in[17]:6 *C 54.748 79.560 +*N chanx_right_in[17]:7 *C 71.293 79.560 +*N chanx_right_in[17]:8 *C 71.300 79.560 +*N chanx_right_in[17]:9 *C 71.300 79.900 +*N chanx_right_in[17]:10 *C 71.345 79.900 +*N chanx_right_in[17]:11 *C 82.295 79.900 +*N chanx_right_in[17]:12 *C 82.340 79.855 +*N chanx_right_in[17]:13 *C 82.340 73.498 +*N chanx_right_in[17]:14 *C 82.348 73.440 +*N chanx_right_in[17]:15 *C 103.493 73.440 +*N chanx_right_in[17]:16 *C 103.500 73.383 +*N chanx_right_in[17]:17 *C 103.500 72.465 +*N chanx_right_in[17]:18 *C 103.545 72.420 +*N chanx_right_in[17]:19 *C 107.640 72.420 +*N chanx_right_in[17]:20 *C 107.640 72.080 +*N chanx_right_in[17]:21 *C 109.435 72.080 +*N chanx_right_in[17]:22 *C 109.480 72.035 +*N chanx_right_in[17]:23 *C 109.480 63.978 +*N chanx_right_in[17]:24 *C 109.488 63.920 + +*CAP +0 chanx_right_in[17] 0.0001708006 +1 BUFT_RR_62:A 1e-06 +2 chanx_right_in[17]:2 4.367675e-05 +3 chanx_right_in[17]:3 4.367675e-05 +4 chanx_right_in[17]:4 0.0002021376 +5 chanx_right_in[17]:5 0.0002021376 +6 chanx_right_in[17]:6 0.0008902135 +7 chanx_right_in[17]:7 0.0008902135 +8 chanx_right_in[17]:8 5.797511e-05 +9 chanx_right_in[17]:9 5.388618e-05 +10 chanx_right_in[17]:10 0.0006340595 +11 chanx_right_in[17]:11 0.0006340595 +12 chanx_right_in[17]:12 0.0004996861 +13 chanx_right_in[17]:13 0.0004996861 +14 chanx_right_in[17]:14 0.0004350101 +15 chanx_right_in[17]:15 0.0004350101 +16 chanx_right_in[17]:16 7.090704e-05 +17 chanx_right_in[17]:17 7.090704e-05 +18 chanx_right_in[17]:18 0.0002502949 +19 chanx_right_in[17]:19 0.0002754644 +20 chanx_right_in[17]:20 0.0001027739 +21 chanx_right_in[17]:21 7.760436e-05 +22 chanx_right_in[17]:22 0.0005421202 +23 chanx_right_in[17]:23 0.0005421202 +24 chanx_right_in[17]:24 0.0001708006 +25 chanx_right_in[17]:23 chany_top_in[16]:5 4.908409e-06 +26 chanx_right_in[17]:21 chany_top_in[16]:7 7.70504e-05 +27 chanx_right_in[17]:22 chany_top_in[16]:6 4.908409e-06 +28 chanx_right_in[17]:18 chany_top_in[16]:8 8.181424e-05 +29 chanx_right_in[17]:17 chany_top_in[16]:14 3.9352e-06 +30 chanx_right_in[17]:16 chany_top_in[16]:15 3.9352e-06 +31 chanx_right_in[17]:15 chany_top_in[16]:16 5.406843e-06 +32 chanx_right_in[17]:14 chany_top_in[16]:17 5.406843e-06 +33 chanx_right_in[17]:11 chany_top_in[16]:20 7.731679e-06 +34 chanx_right_in[17]:10 chany_top_in[16]:21 7.731679e-06 +35 chanx_right_in[17]:7 chany_top_in[16]:20 0.0002646359 +36 chanx_right_in[17]:6 chany_top_in[16]:21 0.0002646359 +37 chanx_right_in[17]:19 chany_top_in[16]:7 8.181424e-05 +38 chanx_right_in[17]:20 chany_top_in[16]:8 7.70504e-05 +39 chanx_right_in[17]:15 right_top_grid_pin_48_[0]:16 0.0004809521 +40 chanx_right_in[17]:15 right_top_grid_pin_48_[0]:20 0.0002288085 +41 chanx_right_in[17]:15 right_top_grid_pin_48_[0]:18 0.000190327 +42 chanx_right_in[17]:14 right_top_grid_pin_48_[0]:8 0.0004809521 +43 chanx_right_in[17]:14 right_top_grid_pin_48_[0]:17 0.000190327 +44 chanx_right_in[17]:14 right_top_grid_pin_48_[0]:19 0.0002288085 +45 chanx_right_in[17]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.277552e-07 +46 chanx_right_in[17]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.277552e-07 +47 chanx_right_in[17]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004937151 +48 chanx_right_in[17]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004937151 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:24 0.0003826583 +1 chanx_right_in[17]:23 chanx_right_in[17]:22 0.007194197 +2 chanx_right_in[17]:24 chanx_right_in[17]:23 0.00341 +3 chanx_right_in[17]:21 chanx_right_in[17]:20 0.001602679 +4 chanx_right_in[17]:22 chanx_right_in[17]:21 0.0045 +5 chanx_right_in[17]:18 chanx_right_in[17]:17 0.0045 +6 chanx_right_in[17]:17 chanx_right_in[17]:16 0.0008191965 +7 chanx_right_in[17]:16 chanx_right_in[17]:15 0.00341 +8 chanx_right_in[17]:15 chanx_right_in[17]:14 0.003312716 +9 chanx_right_in[17]:13 chanx_right_in[17]:12 0.005676339 +10 chanx_right_in[17]:14 chanx_right_in[17]:13 0.00341 +11 chanx_right_in[17]:11 chanx_right_in[17]:10 0.009776786 +12 chanx_right_in[17]:12 chanx_right_in[17]:11 0.0045 +13 chanx_right_in[17]:10 chanx_right_in[17]:9 0.0045 +14 chanx_right_in[17]:9 chanx_right_in[17]:8 0.0001634615 +15 chanx_right_in[17]:8 chanx_right_in[17]:7 0.00341 +16 chanx_right_in[17]:7 chanx_right_in[17]:6 0.00259205 +17 chanx_right_in[17]:5 chanx_right_in[17]:4 0.002944197 +18 chanx_right_in[17]:6 chanx_right_in[17]:5 0.00341 +19 chanx_right_in[17]:3 chanx_right_in[17]:2 0.0003370536 +20 chanx_right_in[17]:4 chanx_right_in[17]:3 0.0045 +21 chanx_right_in[17]:2 BUFT_RR_62:A 0.152 +22 chanx_right_in[17]:19 chanx_right_in[17]:18 0.00365625 +23 chanx_right_in[17]:20 chanx_right_in[17]:19 0.0003035715 + +*END + +*D_NET chany_top_in[6] 0.00463058 //LENGTH 39.220 LUMPCC 0 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 69.460 102.070 +*I mux_right_track_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 69.920 63.580 +*N chany_top_in[6]:2 *C 69.920 63.580 +*N chany_top_in[6]:3 *C 69.920 63.580 +*N chany_top_in[6]:4 *C 69.460 63.580 + +*CAP +0 chany_top_in[6] 0.002248388 +1 mux_right_track_14\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[6]:2 3.533927e-05 +3 chany_top_in[6]:3 6.437235e-05 +4 chany_top_in[6]:4 0.00228148 + +*RES +0 chany_top_in[6] chany_top_in[6]:4 0.03436607 +1 chany_top_in[6]:2 mux_right_track_14\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[6]:3 chany_top_in[6]:2 0.0045 +3 chany_top_in[6]:4 chany_top_in[6]:3 0.0004107143 + +*END + +*D_NET chany_top_in[10] 0.01061417 //LENGTH 77.540 LUMPCC 0.00145286 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 50.140 102.070 +*I mux_right_track_22\/mux_l1_in_0_:A1 I *L 0.00198 *C 95.220 72.420 +*N chany_top_in[10]:2 *C 95.220 72.420 +*N chany_top_in[10]:3 *C 95.220 72.465 +*N chany_top_in[10]:4 *C 95.220 74.415 +*N chany_top_in[10]:5 *C 95.175 74.460 +*N chany_top_in[10]:6 *C 84.225 74.460 +*N chany_top_in[10]:7 *C 84.180 74.505 +*N chany_top_in[10]:8 *C 84.180 75.422 +*N chany_top_in[10]:9 *C 84.172 75.480 +*N chany_top_in[10]:10 *C 73.600 75.480 +*N chany_top_in[10]:11 *C 73.600 76.160 +*N chany_top_in[10]:12 *C 60.740 76.160 +*N chany_top_in[10]:13 *C 60.720 76.168 +*N chany_top_in[10]:14 *C 60.720 94.513 +*N chany_top_in[10]:15 *C 60.700 94.520 +*N chany_top_in[10]:16 *C 50.148 94.520 +*N chany_top_in[10]:17 *C 50.140 94.578 + +*CAP +0 chany_top_in[10] 0.0004802271 +1 mux_right_track_22\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[10]:2 3.092721e-05 +3 chany_top_in[10]:3 0.0001455775 +4 chany_top_in[10]:4 0.0001455775 +5 chany_top_in[10]:5 0.0003901831 +6 chany_top_in[10]:6 0.0003901831 +7 chany_top_in[10]:7 8.759699e-05 +8 chany_top_in[10]:8 8.759699e-05 +9 chany_top_in[10]:9 0.0008450309 +10 chany_top_in[10]:10 0.0009152439 +11 chany_top_in[10]:11 0.001034611 +12 chany_top_in[10]:12 0.0009643976 +13 chany_top_in[10]:13 0.0007801367 +14 chany_top_in[10]:14 0.0007801367 +15 chany_top_in[10]:15 0.0008013302 +16 chany_top_in[10]:16 0.0008013302 +17 chany_top_in[10]:17 0.0004802271 +18 chany_top_in[10]:5 chany_top_in[16]:16 0.0004333371 +19 chany_top_in[10]:6 chany_top_in[16]:17 0.0004333371 +20 chany_top_in[10]:12 chany_top_in[16]:21 5.345074e-07 +21 chany_top_in[10]:13 chany_top_in[16]:22 0.0002925585 +22 chany_top_in[10]:14 chany_top_in[16] 0.0002925585 +23 chany_top_in[10]:11 chany_top_in[16]:20 5.345074e-07 + +*RES +0 chany_top_in[10] chany_top_in[10]:17 0.006689732 +1 chany_top_in[10]:2 mux_right_track_22\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[10]:3 chany_top_in[10]:2 0.0045 +3 chany_top_in[10]:5 chany_top_in[10]:4 0.0045 +4 chany_top_in[10]:4 chany_top_in[10]:3 0.001741072 +5 chany_top_in[10]:6 chany_top_in[10]:5 0.009776786 +6 chany_top_in[10]:7 chany_top_in[10]:6 0.0045 +7 chany_top_in[10]:8 chany_top_in[10]:7 0.0008191965 +8 chany_top_in[10]:9 chany_top_in[10]:8 0.00341 +9 chany_top_in[10]:12 chany_top_in[10]:11 0.002014733 +10 chany_top_in[10]:13 chany_top_in[10]:12 0.00341 +11 chany_top_in[10]:15 chany_top_in[10]:14 0.00341 +12 chany_top_in[10]:14 chany_top_in[10]:13 0.00287405 +13 chany_top_in[10]:17 chany_top_in[10]:16 0.00341 +14 chany_top_in[10]:16 chany_top_in[10]:15 0.001653225 +15 chany_top_in[10]:11 chany_top_in[10]:10 0.0001065333 +16 chany_top_in[10]:10 chany_top_in[10]:9 0.001656358 + +*END + +*D_NET chanx_right_in[5] 0.009222189 //LENGTH 94.235 LUMPCC 0.001516787 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 111.930 9.520 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 53.190 44.200 +*N chanx_right_in[5]:2 *C 53.227 44.200 +*N chanx_right_in[5]:3 *C 53.775 44.200 +*N chanx_right_in[5]:4 *C 53.820 44.155 +*N chanx_right_in[5]:5 *C 53.820 9.578 +*N chanx_right_in[5]:6 *C 53.828 9.520 +*N chanx_right_in[5]:7 *C 103.655 9.520 + +*CAP +0 chanx_right_in[5] 0.0003878771 +1 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[5]:2 7.656192e-05 +3 chanx_right_in[5]:3 7.656192e-05 +4 chanx_right_in[5]:4 0.001602742 +5 chanx_right_in[5]:5 0.001602742 +6 chanx_right_in[5]:6 0.00178502 +7 chanx_right_in[5]:7 0.002172897 +8 chanx_right_in[5] chanx_right_in[2] 0.0001035883 +9 chanx_right_in[5]:4 chanx_right_in[2]:15 3.435209e-05 +10 chanx_right_in[5]:5 chanx_right_in[2]:16 3.435209e-05 +11 chanx_right_in[5]:6 chanx_right_in[2]:17 0.0006204533 +12 chanx_right_in[5]:7 chanx_right_in[2] 0.0006204533 +13 chanx_right_in[5]:7 chanx_right_in[2]:17 0.0001035883 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:7 0.001296417 +1 chanx_right_in[5]:2 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[5]:3 chanx_right_in[5]:2 0.0004888393 +3 chanx_right_in[5]:4 chanx_right_in[5]:3 0.0045 +4 chanx_right_in[5]:5 chanx_right_in[5]:4 0.03087277 +5 chanx_right_in[5]:6 chanx_right_in[5]:5 0.00341 +6 chanx_right_in[5]:7 chanx_right_in[5]:6 0.007806308 + +*END + +*D_NET right_top_grid_pin_45_[0] 0.01165533 //LENGTH 78.420 LUMPCC 0.002302582 DR + +*CONN +*P right_top_grid_pin_45_[0] I *L 0.29796 *C 109.020 74.870 +*I mux_right_track_6\/mux_l1_in_1_:A1 I *L 0.00198 *C 79.025 83.300 +*I mux_right_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 78.105 85.340 +*I mux_right_track_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 70.095 64.600 +*N right_top_grid_pin_45_[0]:4 *C 70.095 64.600 +*N right_top_grid_pin_45_[0]:5 *C 70.380 64.600 +*N right_top_grid_pin_45_[0]:6 *C 70.380 64.645 +*N right_top_grid_pin_45_[0]:7 *C 70.380 66.583 +*N right_top_grid_pin_45_[0]:8 *C 70.388 66.640 +*N right_top_grid_pin_45_[0]:9 *C 72.680 66.640 +*N right_top_grid_pin_45_[0]:10 *C 78.105 85.340 +*N right_top_grid_pin_45_[0]:11 *C 78.200 85.295 +*N right_top_grid_pin_45_[0]:12 *C 79.062 83.300 +*N right_top_grid_pin_45_[0]:13 *C 79.580 83.300 +*N right_top_grid_pin_45_[0]:14 *C 79.580 83.640 +*N right_top_grid_pin_45_[0]:15 *C 78.245 83.640 +*N right_top_grid_pin_45_[0]:16 *C 78.200 83.640 +*N right_top_grid_pin_45_[0]:17 *C 78.200 82.280 +*N right_top_grid_pin_45_[0]:18 *C 77.740 82.280 +*N right_top_grid_pin_45_[0]:19 *C 77.740 79.618 +*N right_top_grid_pin_45_[0]:20 *C 77.733 79.560 +*N right_top_grid_pin_45_[0]:21 *C 72.700 79.560 +*N right_top_grid_pin_45_[0]:22 *C 72.680 79.553 +*N right_top_grid_pin_45_[0]:23 *C 72.680 67.328 +*N right_top_grid_pin_45_[0]:24 *C 72.680 67.320 +*N right_top_grid_pin_45_[0]:25 *C 109.013 67.320 +*N right_top_grid_pin_45_[0]:26 *C 109.020 67.377 + +*CAP +0 right_top_grid_pin_45_[0] 0.0004763082 +1 mux_right_track_6\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_1_:A1 1e-06 +3 mux_right_track_14\/mux_l1_in_0_:A0 1e-06 +4 right_top_grid_pin_45_[0]:4 5.438647e-05 +5 right_top_grid_pin_45_[0]:5 5.587357e-05 +6 right_top_grid_pin_45_[0]:6 0.0001319993 +7 right_top_grid_pin_45_[0]:7 0.0001319993 +8 right_top_grid_pin_45_[0]:8 0.0001340653 +9 right_top_grid_pin_45_[0]:9 0.0001946941 +10 right_top_grid_pin_45_[0]:10 2.748493e-05 +11 right_top_grid_pin_45_[0]:11 0.0001083591 +12 right_top_grid_pin_45_[0]:12 3.784716e-05 +13 right_top_grid_pin_45_[0]:13 6.407152e-05 +14 right_top_grid_pin_45_[0]:14 0.0001418713 +15 right_top_grid_pin_45_[0]:15 0.0001156469 +16 right_top_grid_pin_45_[0]:16 0.000226306 +17 right_top_grid_pin_45_[0]:17 0.0001163641 +18 right_top_grid_pin_45_[0]:18 0.0002121324 +19 right_top_grid_pin_45_[0]:19 0.0001809133 +20 right_top_grid_pin_45_[0]:20 0.0004286178 +21 right_top_grid_pin_45_[0]:21 0.0004286178 +22 right_top_grid_pin_45_[0]:22 0.001198514 +23 right_top_grid_pin_45_[0]:23 0.001198514 +24 right_top_grid_pin_45_[0]:24 0.001634743 +25 right_top_grid_pin_45_[0]:25 0.001574114 +26 right_top_grid_pin_45_[0]:26 0.0004763082 +27 right_top_grid_pin_45_[0]:25 prog_clk[0]:102 5.607733e-05 +28 right_top_grid_pin_45_[0]:25 prog_clk[0]:116 0.0001629619 +29 right_top_grid_pin_45_[0]:25 prog_clk[0]:121 7.373455e-05 +30 right_top_grid_pin_45_[0]:25 prog_clk[0]:123 8.197381e-07 +31 right_top_grid_pin_45_[0]:25 prog_clk[0]:124 8.197381e-07 +32 right_top_grid_pin_45_[0]:25 prog_clk[0]:129 7.947512e-05 +33 right_top_grid_pin_45_[0]:25 prog_clk[0]:138 1.335477e-05 +34 right_top_grid_pin_45_[0]:8 prog_clk[0]:139 5.266659e-05 +35 right_top_grid_pin_45_[0]:24 prog_clk[0]:116 5.607733e-05 +36 right_top_grid_pin_45_[0]:24 prog_clk[0]:121 0.0001629619 +37 right_top_grid_pin_45_[0]:24 prog_clk[0]:122 7.373455e-05 +38 right_top_grid_pin_45_[0]:24 prog_clk[0]:124 8.197381e-07 +39 right_top_grid_pin_45_[0]:24 prog_clk[0]:129 8.197381e-07 +40 right_top_grid_pin_45_[0]:24 prog_clk[0]:132 5.261229e-06 +41 right_top_grid_pin_45_[0]:24 prog_clk[0]:138 7.947512e-05 +42 right_top_grid_pin_45_[0]:24 prog_clk[0]:139 1.335477e-05 +43 right_top_grid_pin_45_[0]:9 prog_clk[0]:133 5.261229e-06 +44 right_top_grid_pin_45_[0]:9 prog_clk[0]:138 5.266659e-05 +45 right_top_grid_pin_45_[0]:25 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0006899564 +46 right_top_grid_pin_45_[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.616384e-05 +47 right_top_grid_pin_45_[0]:24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0006899564 +48 right_top_grid_pin_45_[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.616384e-05 + +*RES +0 right_top_grid_pin_45_[0] right_top_grid_pin_45_[0]:26 0.006689732 +1 right_top_grid_pin_45_[0]:10 mux_right_track_2\/mux_l1_in_1_:A1 0.152 +2 right_top_grid_pin_45_[0]:11 right_top_grid_pin_45_[0]:10 0.0045 +3 right_top_grid_pin_45_[0]:15 right_top_grid_pin_45_[0]:14 0.001191964 +4 right_top_grid_pin_45_[0]:16 right_top_grid_pin_45_[0]:15 0.0045 +5 right_top_grid_pin_45_[0]:16 right_top_grid_pin_45_[0]:11 0.001477679 +6 right_top_grid_pin_45_[0]:12 mux_right_track_6\/mux_l1_in_1_:A1 0.152 +7 right_top_grid_pin_45_[0]:26 right_top_grid_pin_45_[0]:25 0.00341 +8 right_top_grid_pin_45_[0]:25 right_top_grid_pin_45_[0]:24 0.005692091 +9 right_top_grid_pin_45_[0]:7 right_top_grid_pin_45_[0]:6 0.001729911 +10 right_top_grid_pin_45_[0]:8 right_top_grid_pin_45_[0]:7 0.00341 +11 right_top_grid_pin_45_[0]:5 right_top_grid_pin_45_[0]:4 0.0001548913 +12 right_top_grid_pin_45_[0]:6 right_top_grid_pin_45_[0]:5 0.0045 +13 right_top_grid_pin_45_[0]:4 mux_right_track_14\/mux_l1_in_0_:A0 0.152 +14 right_top_grid_pin_45_[0]:24 right_top_grid_pin_45_[0]:23 0.00341 +15 right_top_grid_pin_45_[0]:24 right_top_grid_pin_45_[0]:9 0.0001065333 +16 right_top_grid_pin_45_[0]:23 right_top_grid_pin_45_[0]:22 0.00191525 +17 right_top_grid_pin_45_[0]:21 right_top_grid_pin_45_[0]:20 0.000788425 +18 right_top_grid_pin_45_[0]:22 right_top_grid_pin_45_[0]:21 0.00341 +19 right_top_grid_pin_45_[0]:19 right_top_grid_pin_45_[0]:18 0.002377233 +20 right_top_grid_pin_45_[0]:20 right_top_grid_pin_45_[0]:19 0.00341 +21 right_top_grid_pin_45_[0]:14 right_top_grid_pin_45_[0]:13 0.0003035715 +22 right_top_grid_pin_45_[0]:13 right_top_grid_pin_45_[0]:12 0.0004620536 +23 right_top_grid_pin_45_[0]:18 right_top_grid_pin_45_[0]:17 0.0004107143 +24 right_top_grid_pin_45_[0]:17 right_top_grid_pin_45_[0]:16 0.001214286 +25 right_top_grid_pin_45_[0]:9 right_top_grid_pin_45_[0]:8 0.0003591583 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[1] 0.002208979 //LENGTH 18.450 LUMPCC 0 DR + +*CONN +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 57.805 66.640 +*I mem_right_track_26\/FTB_12__33:A I *L 0.001746 *C 52.440 63.920 +*I mux_right_track_26\/mux_l2_in_0_:S I *L 0.00357 *C 64.280 68.680 +*N mux_tree_tapbuf_size2_11_sram[1]:3 *C 64.243 68.680 +*N mux_tree_tapbuf_size2_11_sram[1]:4 *C 58.465 68.680 +*N mux_tree_tapbuf_size2_11_sram[1]:5 *C 58.420 68.635 +*N mux_tree_tapbuf_size2_11_sram[1]:6 *C 52.477 63.920 +*N mux_tree_tapbuf_size2_11_sram[1]:7 *C 58.375 63.920 +*N mux_tree_tapbuf_size2_11_sram[1]:8 *C 58.420 63.965 +*N mux_tree_tapbuf_size2_11_sram[1]:9 *C 58.420 66.640 +*N mux_tree_tapbuf_size2_11_sram[1]:10 *C 58.375 66.640 +*N mux_tree_tapbuf_size2_11_sram[1]:11 *C 57.843 66.640 + +*CAP +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_26\/FTB_12__33:A 1e-06 +2 mux_right_track_26\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_11_sram[1]:3 0.0004347698 +4 mux_tree_tapbuf_size2_11_sram[1]:4 0.0004347698 +5 mux_tree_tapbuf_size2_11_sram[1]:5 0.0001232811 +6 mux_tree_tapbuf_size2_11_sram[1]:6 0.0003284847 +7 mux_tree_tapbuf_size2_11_sram[1]:7 0.0003284847 +8 mux_tree_tapbuf_size2_11_sram[1]:8 0.0001347417 +9 mux_tree_tapbuf_size2_11_sram[1]:9 0.0002863508 +10 mux_tree_tapbuf_size2_11_sram[1]:10 6.754808e-05 +11 mux_tree_tapbuf_size2_11_sram[1]:11 6.754808e-05 + +*RES +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_11_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_11_sram[1]:3 mux_right_track_26\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_11_sram[1]:4 mux_tree_tapbuf_size2_11_sram[1]:3 0.005158482 +3 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_11_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_11_sram[1]:6 0.005265625 +5 mux_tree_tapbuf_size2_11_sram[1]:8 mux_tree_tapbuf_size2_11_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size2_11_sram[1]:6 mem_right_track_26\/FTB_12__33:A 0.152 +7 mux_tree_tapbuf_size2_11_sram[1]:10 mux_tree_tapbuf_size2_11_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_11_sram[1]:8 0.002388393 +9 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_11_sram[1]:5 0.00178125 +10 mux_tree_tapbuf_size2_11_sram[1]:11 mux_tree_tapbuf_size2_11_sram[1]:10 0.0004754464 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[1] 0.001238175 //LENGTH 10.895 LUMPCC 0 DR + +*CONN +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 72.985 53.380 +*I mux_right_track_14\/mux_l2_in_0_:S I *L 0.00357 *C 76.720 58.140 +*I mem_right_track_14\/FTB_7__28:A I *L 0.001746 *C 77.740 53.040 +*N mux_tree_tapbuf_size2_6_sram[1]:3 *C 77.703 53.040 +*N mux_tree_tapbuf_size2_6_sram[1]:4 *C 76.820 53.040 +*N mux_tree_tapbuf_size2_6_sram[1]:5 *C 76.720 58.140 +*N mux_tree_tapbuf_size2_6_sram[1]:6 *C 76.820 58.095 +*N mux_tree_tapbuf_size2_6_sram[1]:7 *C 76.820 53.425 +*N mux_tree_tapbuf_size2_6_sram[1]:8 *C 76.820 53.350 +*N mux_tree_tapbuf_size2_6_sram[1]:9 *C 73.023 53.380 + +*CAP +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_14\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_14\/FTB_7__28:A 1e-06 +3 mux_tree_tapbuf_size2_6_sram[1]:3 6.323461e-05 +4 mux_tree_tapbuf_size2_6_sram[1]:4 9.016095e-05 +5 mux_tree_tapbuf_size2_6_sram[1]:5 2.705291e-05 +6 mux_tree_tapbuf_size2_6_sram[1]:6 0.0002752928 +7 mux_tree_tapbuf_size2_6_sram[1]:7 0.0002752928 +8 mux_tree_tapbuf_size2_6_sram[1]:8 0.0002655338 +9 mux_tree_tapbuf_size2_6_sram[1]:9 0.0002386075 + +*RES +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_6_sram[1]:9 0.152 +1 mux_tree_tapbuf_size2_6_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:8 0.003390625 +2 mux_tree_tapbuf_size2_6_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size2_6_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:4 0.0002767858 +4 mux_tree_tapbuf_size2_6_sram[1]:7 mux_tree_tapbuf_size2_6_sram[1]:6 0.004169643 +5 mux_tree_tapbuf_size2_6_sram[1]:5 mux_right_track_14\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[1]:5 0.0045 +7 mux_tree_tapbuf_size2_6_sram[1]:3 mem_right_track_14\/FTB_7__28:A 0.152 +8 mux_tree_tapbuf_size2_6_sram[1]:4 mux_tree_tapbuf_size2_6_sram[1]:3 0.0007879465 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[2] 0.003275495 //LENGTH 22.680 LUMPCC 0 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 71.415 98.600 +*I mem_right_track_6\/FTB_16__37:A I *L 0.001746 *C 65.780 96.560 +*I mux_right_track_6\/mux_l3_in_0_:S I *L 0.00357 *C 79.940 94.520 +*N mux_tree_tapbuf_size5_1_sram[2]:3 *C 79.903 94.520 +*N mux_tree_tapbuf_size5_1_sram[2]:4 *C 69.045 94.520 +*N mux_tree_tapbuf_size5_1_sram[2]:5 *C 69.000 94.565 +*N mux_tree_tapbuf_size5_1_sram[2]:6 *C 65.780 96.560 +*N mux_tree_tapbuf_size5_1_sram[2]:7 *C 65.780 95.880 +*N mux_tree_tapbuf_size5_1_sram[2]:8 *C 68.955 95.880 +*N mux_tree_tapbuf_size5_1_sram[2]:9 *C 69.000 95.880 +*N mux_tree_tapbuf_size5_1_sram[2]:10 *C 69.000 98.555 +*N mux_tree_tapbuf_size5_1_sram[2]:11 *C 69.045 98.600 +*N mux_tree_tapbuf_size5_1_sram[2]:12 *C 71.377 98.600 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_6\/FTB_16__37:A 1e-06 +2 mux_right_track_6\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_1_sram[2]:3 0.0007991983 +4 mux_tree_tapbuf_size5_1_sram[2]:4 0.0007991983 +5 mux_tree_tapbuf_size5_1_sram[2]:5 0.0001065267 +6 mux_tree_tapbuf_size5_1_sram[2]:6 7.889471e-05 +7 mux_tree_tapbuf_size5_1_sram[2]:7 0.0002699338 +8 mux_tree_tapbuf_size5_1_sram[2]:8 0.000221747 +9 mux_tree_tapbuf_size5_1_sram[2]:9 0.0003436249 +10 mux_tree_tapbuf_size5_1_sram[2]:10 0.0002025547 +11 mux_tree_tapbuf_size5_1_sram[2]:11 0.0002254082 +12 mux_tree_tapbuf_size5_1_sram[2]:12 0.0002254082 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_1_sram[2]:12 0.152 +1 mux_tree_tapbuf_size5_1_sram[2]:6 mem_right_track_6\/FTB_16__37:A 0.152 +2 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:7 0.002834822 +3 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:8 0.0045 +4 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:5 0.001174107 +5 mux_tree_tapbuf_size5_1_sram[2]:4 mux_tree_tapbuf_size5_1_sram[2]:3 0.009694196 +6 mux_tree_tapbuf_size5_1_sram[2]:5 mux_tree_tapbuf_size5_1_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size5_1_sram[2]:3 mux_right_track_6\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_1_sram[2]:11 mux_tree_tapbuf_size5_1_sram[2]:10 0.0045 +9 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:9 0.002388393 +10 mux_tree_tapbuf_size5_1_sram[2]:12 mux_tree_tapbuf_size5_1_sram[2]:11 0.002082589 +11 mux_tree_tapbuf_size5_1_sram[2]:7 mux_tree_tapbuf_size5_1_sram[2]:6 0.0006071429 + +*END + +*D_NET optlc_net_113 0.00423224 //LENGTH 36.250 LUMPCC 0.0003425393 DR + +*CONN +*I optlc_107:HI O *L 0 *C 45.080 60.860 +*I mux_right_track_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 50.775 53.720 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 42.150 47.940 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 37.090 64.600 +*N optlc_net_113:4 *C 37.128 64.600 +*N optlc_net_113:5 *C 44.115 64.600 +*N optlc_net_113:6 *C 44.160 64.555 +*N optlc_net_113:7 *C 42.188 47.940 +*N optlc_net_113:8 *C 42.735 47.940 +*N optlc_net_113:9 *C 42.780 47.985 +*N optlc_net_113:10 *C 42.780 50.615 +*N optlc_net_113:11 *C 42.825 50.660 +*N optlc_net_113:12 *C 43.655 50.660 +*N optlc_net_113:13 *C 43.700 50.705 +*N optlc_net_113:14 *C 43.700 53.720 +*N optlc_net_113:15 *C 50.738 53.720 +*N optlc_net_113:16 *C 49.265 53.720 +*N optlc_net_113:17 *C 49.220 53.720 +*N optlc_net_113:18 *C 49.213 53.720 +*N optlc_net_113:19 *C 44.168 53.720 +*N optlc_net_113:20 *C 44.160 53.778 +*N optlc_net_113:21 *C 44.160 60.860 +*N optlc_net_113:22 *C 44.205 60.860 +*N optlc_net_113:23 *C 45.043 60.860 + +*CAP +0 optlc_107:HI 1e-06 +1 mux_right_track_12\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +3 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +4 optlc_net_113:4 0.000378329 +5 optlc_net_113:5 0.000378329 +6 optlc_net_113:6 0.0001963536 +7 optlc_net_113:7 6.074031e-05 +8 optlc_net_113:8 6.074031e-05 +9 optlc_net_113:9 0.0001601622 +10 optlc_net_113:10 0.0001601622 +11 optlc_net_113:11 6.964615e-05 +12 optlc_net_113:12 6.964615e-05 +13 optlc_net_113:13 0.0001613544 +14 optlc_net_113:14 0.0001932692 +15 optlc_net_113:15 0.0001144792 +16 optlc_net_113:16 0.0001144792 +17 optlc_net_113:17 2.912622e-05 +18 optlc_net_113:18 0.000294287 +19 optlc_net_113:19 0.000294287 +20 optlc_net_113:20 0.0004121669 +21 optlc_net_113:21 0.0006048231 +22 optlc_net_113:22 6.66601e-05 +23 optlc_net_113:23 6.66601e-05 +24 optlc_net_113:5 mux_tree_tapbuf_size2_3_sram[1]:6 0.000117715 +25 optlc_net_113:4 mux_tree_tapbuf_size2_3_sram[1]:5 0.000117715 +26 optlc_net_113:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 5.35546e-05 +27 optlc_net_113:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 5.35546e-05 + +*RES +0 optlc_107:HI optlc_net_113:23 0.152 +1 optlc_net_113:20 optlc_net_113:19 0.00341 +2 optlc_net_113:20 optlc_net_113:14 0.0004107143 +3 optlc_net_113:19 optlc_net_113:18 0.0007903833 +4 optlc_net_113:17 optlc_net_113:16 0.0045 +5 optlc_net_113:18 optlc_net_113:17 0.00341 +6 optlc_net_113:16 optlc_net_113:15 0.001314732 +7 optlc_net_113:15 mux_right_track_12\/mux_l2_in_0_:A0 0.152 +8 optlc_net_113:5 optlc_net_113:4 0.00623884 +9 optlc_net_113:6 optlc_net_113:5 0.0045 +10 optlc_net_113:4 mux_top_track_24\/mux_l2_in_0_:A0 0.152 +11 optlc_net_113:22 optlc_net_113:21 0.0045 +12 optlc_net_113:21 optlc_net_113:20 0.006323661 +13 optlc_net_113:21 optlc_net_113:6 0.003299107 +14 optlc_net_113:23 optlc_net_113:22 0.0007477679 +15 optlc_net_113:12 optlc_net_113:11 0.0007410714 +16 optlc_net_113:13 optlc_net_113:12 0.0045 +17 optlc_net_113:11 optlc_net_113:10 0.0045 +18 optlc_net_113:10 optlc_net_113:9 0.002348214 +19 optlc_net_113:8 optlc_net_113:7 0.0004888393 +20 optlc_net_113:9 optlc_net_113:8 0.0045 +21 optlc_net_113:7 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +22 optlc_net_113:14 optlc_net_113:13 0.002691964 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008242661 //LENGTH 6.660 LUMPCC 0.0001105571 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_1_:X O *L 0 *C 50.775 88.060 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 48.935 86.360 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 48.898 86.360 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 47.885 86.360 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 47.840 86.405 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 47.840 88.015 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 47.885 88.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 50.738 88.060 + +*CAP +0 mux_right_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.338476e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.338476e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.243449e-05 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.243449e-05 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001900352 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001900352 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 right_top_grid_pin_42_[0]:9 5.527856e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 right_top_grid_pin_42_[0]:8 5.527856e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009040179 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002546875 + +*END + +*D_NET ropt_net_146 0.001929909 //LENGTH 15.070 LUMPCC 0.0002556953 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 107.180 39.780 +*I ropt_mt_inst_771:A I *L 0.001766 *C 106.260 36.720 +*N ropt_net_146:2 *C 106.260 36.720 +*N ropt_net_146:3 *C 106.260 36.765 +*N ropt_net_146:4 *C 106.260 37.343 +*N ropt_net_146:5 *C 106.267 37.400 +*N ropt_net_146:6 *C 111.312 37.400 +*N ropt_net_146:7 *C 111.320 37.400 +*N ropt_net_146:8 *C 111.320 38.715 +*N ropt_net_146:9 *C 111.275 38.760 +*N ropt_net_146:10 *C 110.135 38.760 +*N ropt_net_146:11 *C 110.135 39.100 +*N ropt_net_146:12 *C 108.605 39.100 +*N ropt_net_146:13 *C 108.560 39.145 +*N ropt_net_146:14 *C 108.560 39.735 +*N ropt_net_146:15 *C 108.515 39.780 +*N ropt_net_146:16 *C 107.218 39.780 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_146:2 2.911898e-05 +3 ropt_net_146:3 5.111969e-05 +4 ropt_net_146:4 5.111969e-05 +5 ropt_net_146:5 0.0002467603 +6 ropt_net_146:6 0.0002467603 +7 ropt_net_146:7 0.0001542322 +8 ropt_net_146:8 0.0001202643 +9 ropt_net_146:9 0.000101533 +10 ropt_net_146:10 0.0001324036 +11 ropt_net_146:11 0.0001623763 +12 ropt_net_146:12 0.0001315056 +13 ropt_net_146:13 4.867159e-05 +14 ropt_net_146:14 4.867159e-05 +15 ropt_net_146:15 7.383854e-05 +16 ropt_net_146:16 7.383854e-05 +17 ropt_net_146:16 chany_top_in[15]:2 3.799884e-05 +18 ropt_net_146:15 chany_top_in[15]:3 3.799884e-05 +19 ropt_net_146:14 chany_top_in[15]:5 1.745746e-05 +20 ropt_net_146:13 chany_top_in[15]:4 1.745746e-05 +21 ropt_net_146:14 chanx_right_out[15]:4 3.808171e-07 +22 ropt_net_146:13 chanx_right_out[15]:3 3.808171e-07 +23 ropt_net_146:6 chanx_right_out[15] 7.201052e-05 +24 ropt_net_146:5 chanx_right_out[15]:2 7.201052e-05 + +*RES +0 ropt_mt_inst_743:X ropt_net_146:16 0.152 +1 ropt_net_146:16 ropt_net_146:15 0.001158482 +2 ropt_net_146:15 ropt_net_146:14 0.0045 +3 ropt_net_146:14 ropt_net_146:13 0.0005267858 +4 ropt_net_146:12 ropt_net_146:11 0.001366072 +5 ropt_net_146:13 ropt_net_146:12 0.0045 +6 ropt_net_146:9 ropt_net_146:8 0.0045 +7 ropt_net_146:8 ropt_net_146:7 0.001174107 +8 ropt_net_146:7 ropt_net_146:6 0.00341 +9 ropt_net_146:6 ropt_net_146:5 0.0007903833 +10 ropt_net_146:4 ropt_net_146:3 0.000515625 +11 ropt_net_146:5 ropt_net_146:4 0.00341 +12 ropt_net_146:2 ropt_mt_inst_771:A 0.152 +13 ropt_net_146:3 ropt_net_146:2 0.0045 +14 ropt_net_146:11 ropt_net_146:10 0.0003035715 +15 ropt_net_146:10 ropt_net_146:9 0.001017857 + +*END + +*D_NET chany_top_in[14] 0.01602266 //LENGTH 137.420 LUMPCC 0.00626901 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 29.440 102.150 +*I BUFT_P_97:A I *L 0.001776 *C 103.040 42.160 +*N chany_top_in[14]:2 *C 103.040 42.160 +*N chany_top_in[14]:3 *C 103.040 42.500 +*N chany_top_in[14]:4 *C 103.915 42.500 +*N chany_top_in[14]:5 *C 103.960 42.545 +*N chany_top_in[14]:6 *C 103.960 44.143 +*N chany_top_in[14]:7 *C 103.953 44.200 +*N chany_top_in[14]:8 *C 82.930 44.200 +*N chany_top_in[14]:9 *C 33.140 44.200 +*N chany_top_in[14]:10 *C 33.120 44.208 +*N chany_top_in[14]:11 *C 33.120 95.873 +*N chany_top_in[14]:12 *C 33.100 95.880 +*N chany_top_in[14]:13 *C 29.460 95.880 +*N chany_top_in[14]:14 *C 29.440 95.888 + +*CAP +0 chany_top_in[14] 0.0003914662 +1 BUFT_P_97:A 1e-06 +2 chany_top_in[14]:2 6.16759e-05 +3 chany_top_in[14]:3 8.044924e-05 +4 chany_top_in[14]:4 5.041836e-05 +5 chany_top_in[14]:5 0.0001098141 +6 chany_top_in[14]:6 0.0001098141 +7 chany_top_in[14]:7 0.0005118885 +8 chany_top_in[14]:8 0.002504248 +9 chany_top_in[14]:9 0.00199236 +10 chany_top_in[14]:10 0.00158343 +11 chany_top_in[14]:11 0.00158343 +12 chany_top_in[14]:12 0.0001910955 +13 chany_top_in[14]:13 0.0001910955 +14 chany_top_in[14]:14 0.0003914662 +15 chany_top_in[14]:4 chany_top_in[15]:6 4.234692e-05 +16 chany_top_in[14]:5 chany_top_in[15]:9 4.162322e-07 +17 chany_top_in[14]:6 chany_top_in[15]:8 4.162322e-07 +18 chany_top_in[14]:7 chany_top_in[15]:13 0.0002843637 +19 chany_top_in[14]:9 chany_top_in[15]:14 0.0004944106 +20 chany_top_in[14]:3 chany_top_in[15]:7 4.234692e-05 +21 chany_top_in[14]:8 chany_top_in[15]:13 0.0004944106 +22 chany_top_in[14]:8 chany_top_in[15]:14 0.0002843637 +23 chany_top_in[14] chanx_right_in[2]:7 3.505232e-06 +24 chany_top_in[14]:10 chanx_right_in[2]:9 0.0006185351 +25 chany_top_in[14]:10 chanx_right_in[2]:8 0.0001857312 +26 chany_top_in[14]:12 chanx_right_in[2]:6 7.022938e-05 +27 chany_top_in[14]:11 chanx_right_in[2]:7 0.0001857312 +28 chany_top_in[14]:11 chanx_right_in[2]:8 0.0006185351 +29 chany_top_in[14]:13 chanx_right_in[2]:5 7.022938e-05 +30 chany_top_in[14]:14 chanx_right_in[2]:8 3.505232e-06 +31 chany_top_in[14]:9 prog_clk[0]:183 0.0002215777 +32 chany_top_in[14]:9 prog_clk[0]:47 6.349575e-05 +33 chany_top_in[14]:10 prog_clk[0]:56 1.234897e-05 +34 chany_top_in[14]:10 prog_clk[0]:71 8.611011e-06 +35 chany_top_in[14]:10 prog_clk[0]:59 8.049999e-06 +36 chany_top_in[14]:10 prog_clk[0]:48 8.83126e-06 +37 chany_top_in[14]:10 prog_clk[0]:82 1.482667e-05 +38 chany_top_in[14]:12 prog_clk[0]:247 5.166552e-07 +39 chany_top_in[14]:11 prog_clk[0]:85 1.482667e-05 +40 chany_top_in[14]:11 prog_clk[0]:72 8.611011e-06 +41 chany_top_in[14]:11 prog_clk[0]:59 1.234897e-05 +42 chany_top_in[14]:11 prog_clk[0]:52 8.83126e-06 +43 chany_top_in[14]:11 prog_clk[0]:65 8.049999e-06 +44 chany_top_in[14]:13 prog_clk[0]:248 5.166552e-07 +45 chany_top_in[14]:8 prog_clk[0]:182 0.0002215777 +46 chany_top_in[14]:8 prog_clk[0]:46 6.349575e-05 +47 chany_top_in[14]:7 chanx_right_in[13] 0.0008516385 +48 chany_top_in[14]:8 chanx_right_in[13]:10 0.0008516385 +49 chany_top_in[14]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.998586e-05 +50 chany_top_in[14]:9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002050842 +51 chany_top_in[14]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.998586e-05 +52 chany_top_in[14]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002050842 + +*RES +0 chany_top_in[14] chany_top_in[14]:14 0.0009811249 +1 chany_top_in[14]:2 BUFT_P_97:A 0.152 +2 chany_top_in[14]:4 chany_top_in[14]:3 0.0007812501 +3 chany_top_in[14]:5 chany_top_in[14]:4 0.0045 +4 chany_top_in[14]:6 chany_top_in[14]:5 0.001426339 +5 chany_top_in[14]:7 chany_top_in[14]:6 0.00341 +6 chany_top_in[14]:9 chany_top_in[14]:8 0.007800433 +7 chany_top_in[14]:10 chany_top_in[14]:9 0.00341 +8 chany_top_in[14]:12 chany_top_in[14]:11 0.00341 +9 chany_top_in[14]:11 chany_top_in[14]:10 0.008094183 +10 chany_top_in[14]:13 chany_top_in[14]:12 0.0005702666 +11 chany_top_in[14]:14 chany_top_in[14]:13 0.00341 +12 chany_top_in[14]:3 chany_top_in[14]:2 0.0003035715 +13 chany_top_in[14]:8 chany_top_in[14]:7 0.003293525 + +*END + +*D_NET right_bottom_grid_pin_1_[0] 0.01834214 //LENGTH 150.875 LUMPCC 0.002476429 DR + +*CONN +*P right_bottom_grid_pin_1_[0] I *L 0.29796 *C 109.940 1.325 +*I mux_right_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 83.895 58.820 +*I mux_right_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 73.045 69.020 +*I mux_right_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 65.610 75.140 +*I mux_right_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 52.345 88.740 +*N right_bottom_grid_pin_1_[0]:5 *C 52.383 88.740 +*N right_bottom_grid_pin_1_[0]:6 *C 54.235 88.740 +*N right_bottom_grid_pin_1_[0]:7 *C 54.280 88.695 +*N right_bottom_grid_pin_1_[0]:8 *C 54.280 87.778 +*N right_bottom_grid_pin_1_[0]:9 *C 54.288 87.720 +*N right_bottom_grid_pin_1_[0]:10 *C 65.312 87.720 +*N right_bottom_grid_pin_1_[0]:11 *C 65.320 87.663 +*N right_bottom_grid_pin_1_[0]:12 *C 65.320 75.140 +*N right_bottom_grid_pin_1_[0]:13 *C 65.610 75.140 +*N right_bottom_grid_pin_1_[0]:14 *C 65.780 75.140 +*N right_bottom_grid_pin_1_[0]:15 *C 65.780 75.095 +*N right_bottom_grid_pin_1_[0]:16 *C 65.780 69.745 +*N right_bottom_grid_pin_1_[0]:17 *C 65.825 69.700 +*N right_bottom_grid_pin_1_[0]:18 *C 73.140 69.700 +*N right_bottom_grid_pin_1_[0]:19 *C 73.140 69.020 +*N right_bottom_grid_pin_1_[0]:20 *C 77.695 69.020 +*N right_bottom_grid_pin_1_[0]:21 *C 77.740 68.975 +*N right_bottom_grid_pin_1_[0]:22 *C 77.740 61.258 +*N right_bottom_grid_pin_1_[0]:23 *C 77.748 61.200 +*N right_bottom_grid_pin_1_[0]:24 *C 82.793 61.200 +*N right_bottom_grid_pin_1_[0]:25 *C 82.800 61.143 +*N right_bottom_grid_pin_1_[0]:26 *C 82.800 58.865 +*N right_bottom_grid_pin_1_[0]:27 *C 82.845 58.820 +*N right_bottom_grid_pin_1_[0]:28 *C 83.895 58.820 +*N right_bottom_grid_pin_1_[0]:29 *C 85.975 58.820 +*N right_bottom_grid_pin_1_[0]:30 *C 86.020 58.775 +*N right_bottom_grid_pin_1_[0]:31 *C 86.020 51.540 +*N right_bottom_grid_pin_1_[0]:32 *C 86.020 1.745 +*N right_bottom_grid_pin_1_[0]:33 *C 86.020 1.700 +*N right_bottom_grid_pin_1_[0]:34 *C 86.020 1.360 +*N right_bottom_grid_pin_1_[0]:35 *C 102.580 1.360 +*N right_bottom_grid_pin_1_[0]:36 *C 102.580 1.700 +*N right_bottom_grid_pin_1_[0]:37 *C 109.895 1.700 +*N right_bottom_grid_pin_1_[0]:38 *C 109.940 1.655 + +*CAP +0 right_bottom_grid_pin_1_[0] 3.325241e-05 +1 mux_right_track_4\/mux_l1_in_2_:A0 1e-06 +2 mux_right_track_24\/mux_l1_in_1_:A1 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A0 1e-06 +4 mux_right_track_8\/mux_l1_in_1_:A1 1e-06 +5 right_bottom_grid_pin_1_[0]:5 0.0001439326 +6 right_bottom_grid_pin_1_[0]:6 0.0001439326 +7 right_bottom_grid_pin_1_[0]:7 8.439322e-05 +8 right_bottom_grid_pin_1_[0]:8 8.439322e-05 +9 right_bottom_grid_pin_1_[0]:9 0.0005359239 +10 right_bottom_grid_pin_1_[0]:10 0.0005359239 +11 right_bottom_grid_pin_1_[0]:11 0.0007798811 +12 right_bottom_grid_pin_1_[0]:12 0.0008156649 +13 right_bottom_grid_pin_1_[0]:13 5.517739e-05 +14 right_bottom_grid_pin_1_[0]:14 5.800088e-05 +15 right_bottom_grid_pin_1_[0]:15 0.0003710396 +16 right_bottom_grid_pin_1_[0]:16 0.0003352558 +17 right_bottom_grid_pin_1_[0]:17 0.0004995371 +18 right_bottom_grid_pin_1_[0]:18 0.0005473924 +19 right_bottom_grid_pin_1_[0]:19 0.0003697418 +20 right_bottom_grid_pin_1_[0]:20 0.0003218865 +21 right_bottom_grid_pin_1_[0]:21 0.0004622538 +22 right_bottom_grid_pin_1_[0]:22 0.0004622538 +23 right_bottom_grid_pin_1_[0]:23 0.000105823 +24 right_bottom_grid_pin_1_[0]:24 0.000105823 +25 right_bottom_grid_pin_1_[0]:25 0.0001554667 +26 right_bottom_grid_pin_1_[0]:26 0.0001554667 +27 right_bottom_grid_pin_1_[0]:27 9.522739e-05 +28 right_bottom_grid_pin_1_[0]:28 0.0002850951 +29 right_bottom_grid_pin_1_[0]:29 0.0001592189 +30 right_bottom_grid_pin_1_[0]:30 0.0004007822 +31 right_bottom_grid_pin_1_[0]:31 0.002811201 +32 right_bottom_grid_pin_1_[0]:32 0.002410419 +33 right_bottom_grid_pin_1_[0]:33 5.067067e-05 +34 right_bottom_grid_pin_1_[0]:34 0.0008279704 +35 right_bottom_grid_pin_1_[0]:35 0.0008258692 +36 right_bottom_grid_pin_1_[0]:36 0.000410666 +37 right_bottom_grid_pin_1_[0]:37 0.0003889215 +38 right_bottom_grid_pin_1_[0]:38 3.325241e-05 +39 right_bottom_grid_pin_1_[0]:10 chanx_right_in[19]:6 0.0005657898 +40 right_bottom_grid_pin_1_[0]:9 chanx_right_in[19]:5 0.0005657898 +41 right_bottom_grid_pin_1_[0]:23 chanx_right_in[19]:9 0.0002974173 +42 right_bottom_grid_pin_1_[0]:24 chanx_right_in[19]:10 0.0002974173 +43 right_bottom_grid_pin_1_[0]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.624253e-05 +44 right_bottom_grid_pin_1_[0]:18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.624253e-05 +45 right_bottom_grid_pin_1_[0]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 1.347478e-06 +46 right_bottom_grid_pin_1_[0]:23 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002974173 +47 right_bottom_grid_pin_1_[0]:24 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002974173 +48 right_bottom_grid_pin_1_[0]:18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 1.347478e-06 + +*RES +0 right_bottom_grid_pin_1_[0] right_bottom_grid_pin_1_[0]:38 0.0002946429 +1 right_bottom_grid_pin_1_[0]:29 right_bottom_grid_pin_1_[0]:28 0.001857143 +2 right_bottom_grid_pin_1_[0]:30 right_bottom_grid_pin_1_[0]:29 0.0045 +3 right_bottom_grid_pin_1_[0]:33 right_bottom_grid_pin_1_[0]:32 0.0045 +4 right_bottom_grid_pin_1_[0]:32 right_bottom_grid_pin_1_[0]:31 0.04445982 +5 right_bottom_grid_pin_1_[0]:37 right_bottom_grid_pin_1_[0]:36 0.00653125 +6 right_bottom_grid_pin_1_[0]:38 right_bottom_grid_pin_1_[0]:37 0.0045 +7 right_bottom_grid_pin_1_[0]:17 right_bottom_grid_pin_1_[0]:16 0.0045 +8 right_bottom_grid_pin_1_[0]:16 right_bottom_grid_pin_1_[0]:15 0.004776786 +9 right_bottom_grid_pin_1_[0]:11 right_bottom_grid_pin_1_[0]:10 0.00341 +10 right_bottom_grid_pin_1_[0]:10 right_bottom_grid_pin_1_[0]:9 0.00172725 +11 right_bottom_grid_pin_1_[0]:8 right_bottom_grid_pin_1_[0]:7 0.0008191965 +12 right_bottom_grid_pin_1_[0]:9 right_bottom_grid_pin_1_[0]:8 0.00341 +13 right_bottom_grid_pin_1_[0]:6 right_bottom_grid_pin_1_[0]:5 0.001654018 +14 right_bottom_grid_pin_1_[0]:7 right_bottom_grid_pin_1_[0]:6 0.0045 +15 right_bottom_grid_pin_1_[0]:5 mux_right_track_8\/mux_l1_in_1_:A1 0.152 +16 right_bottom_grid_pin_1_[0]:14 right_bottom_grid_pin_1_[0]:13 9.239131e-05 +17 right_bottom_grid_pin_1_[0]:15 right_bottom_grid_pin_1_[0]:14 0.0045 +18 right_bottom_grid_pin_1_[0]:15 right_bottom_grid_pin_1_[0]:12 0.0004107143 +19 right_bottom_grid_pin_1_[0]:13 mux_right_track_0\/mux_l1_in_2_:A0 0.152 +20 right_bottom_grid_pin_1_[0]:19 mux_right_track_24\/mux_l1_in_1_:A1 0.152 +21 right_bottom_grid_pin_1_[0]:19 right_bottom_grid_pin_1_[0]:18 0.000607143 +22 right_bottom_grid_pin_1_[0]:20 right_bottom_grid_pin_1_[0]:19 0.004066965 +23 right_bottom_grid_pin_1_[0]:21 right_bottom_grid_pin_1_[0]:20 0.0045 +24 right_bottom_grid_pin_1_[0]:22 right_bottom_grid_pin_1_[0]:21 0.006890625 +25 right_bottom_grid_pin_1_[0]:23 right_bottom_grid_pin_1_[0]:22 0.00341 +26 right_bottom_grid_pin_1_[0]:25 right_bottom_grid_pin_1_[0]:24 0.00341 +27 right_bottom_grid_pin_1_[0]:24 right_bottom_grid_pin_1_[0]:23 0.0007903833 +28 right_bottom_grid_pin_1_[0]:27 right_bottom_grid_pin_1_[0]:26 0.0045 +29 right_bottom_grid_pin_1_[0]:26 right_bottom_grid_pin_1_[0]:25 0.002033482 +30 right_bottom_grid_pin_1_[0]:28 mux_right_track_4\/mux_l1_in_2_:A0 0.152 +31 right_bottom_grid_pin_1_[0]:28 right_bottom_grid_pin_1_[0]:27 0.0009375002 +32 right_bottom_grid_pin_1_[0]:18 right_bottom_grid_pin_1_[0]:17 0.006531251 +33 right_bottom_grid_pin_1_[0]:34 right_bottom_grid_pin_1_[0]:33 0.0003035715 +34 right_bottom_grid_pin_1_[0]:35 right_bottom_grid_pin_1_[0]:34 0.01478571 +35 right_bottom_grid_pin_1_[0]:36 right_bottom_grid_pin_1_[0]:35 0.0003035715 +36 right_bottom_grid_pin_1_[0]:12 right_bottom_grid_pin_1_[0]:11 0.0111808 +37 right_bottom_grid_pin_1_[0]:31 right_bottom_grid_pin_1_[0]:30 0.006459821 + +*END + +*D_NET chanx_right_out[12] 0.0004730896 //LENGTH 2.845 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 109.480 69.360 +*P chanx_right_out[12] O *L 0.7423 *C 111.855 69.360 +*N chanx_right_out[12]:2 *C 110.868 69.360 +*N chanx_right_out[12]:3 *C 110.860 69.360 +*N chanx_right_out[12]:4 *C 110.815 69.360 +*N chanx_right_out[12]:5 *C 109.517 69.360 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 0.0001041528 +2 chanx_right_out[12]:2 0.0001041528 +3 chanx_right_out[12]:3 3.566153e-05 +4 chanx_right_out[12]:4 0.0001140613 +5 chanx_right_out[12]:5 0.0001140613 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:5 0.152 +1 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +2 chanx_right_out[12]:2 chanx_right_out[12] 0.0001547083 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0045 +4 chanx_right_out[12]:5 chanx_right_out[12]:4 0.001158482 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[1] 0.00135416 //LENGTH 10.065 LUMPCC 0.0004453443 DR + +*CONN +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 101.305 65.960 +*I mux_right_track_22\/mux_l2_in_0_:S I *L 0.00357 *C 100.180 63.630 +*I mem_right_track_22\/FTB_11__32:A I *L 0.001746 *C 94.760 63.920 +*N mux_tree_tapbuf_size2_10_sram[1]:3 *C 94.797 63.920 +*N mux_tree_tapbuf_size2_10_sram[1]:4 *C 100.070 63.920 +*N mux_tree_tapbuf_size2_10_sram[1]:5 *C 100.180 63.630 +*N mux_tree_tapbuf_size2_10_sram[1]:6 *C 100.280 63.920 +*N mux_tree_tapbuf_size2_10_sram[1]:7 *C 100.280 63.965 +*N mux_tree_tapbuf_size2_10_sram[1]:8 *C 100.280 65.915 +*N mux_tree_tapbuf_size2_10_sram[1]:9 *C 100.325 65.960 +*N mux_tree_tapbuf_size2_10_sram[1]:10 *C 101.267 65.960 + +*CAP +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_22\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_22\/FTB_11__32:A 1e-06 +3 mux_tree_tapbuf_size2_10_sram[1]:3 0.0002125347 +4 mux_tree_tapbuf_size2_10_sram[1]:4 0.0002186208 +5 mux_tree_tapbuf_size2_10_sram[1]:5 5.081868e-05 +6 mux_tree_tapbuf_size2_10_sram[1]:6 6.14735e-05 +7 mux_tree_tapbuf_size2_10_sram[1]:7 9.818005e-05 +8 mux_tree_tapbuf_size2_10_sram[1]:8 9.818005e-05 +9 mux_tree_tapbuf_size2_10_sram[1]:9 8.300397e-05 +10 mux_tree_tapbuf_size2_10_sram[1]:10 8.300397e-05 +11 mux_tree_tapbuf_size2_10_sram[1]:3 optlc_net_112:28 0.0001734937 +12 mux_tree_tapbuf_size2_10_sram[1]:4 optlc_net_112:27 0.0001734937 +13 mux_tree_tapbuf_size2_10_sram[1]:8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.736344e-05 +14 mux_tree_tapbuf_size2_10_sram[1]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.736344e-05 +15 mux_tree_tapbuf_size2_10_sram[1]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.18151e-05 +16 mux_tree_tapbuf_size2_10_sram[1]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.18151e-05 + +*RES +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_10_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_10_sram[1]:10 mux_tree_tapbuf_size2_10_sram[1]:9 0.0008415179 +2 mux_tree_tapbuf_size2_10_sram[1]:9 mux_tree_tapbuf_size2_10_sram[1]:8 0.0045 +3 mux_tree_tapbuf_size2_10_sram[1]:8 mux_tree_tapbuf_size2_10_sram[1]:7 0.001741072 +4 mux_tree_tapbuf_size2_10_sram[1]:6 mux_tree_tapbuf_size2_10_sram[1]:5 0.000125 +5 mux_tree_tapbuf_size2_10_sram[1]:6 mux_tree_tapbuf_size2_10_sram[1]:4 1e-05 +6 mux_tree_tapbuf_size2_10_sram[1]:7 mux_tree_tapbuf_size2_10_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size2_10_sram[1]:3 mem_right_track_22\/FTB_11__32:A 0.152 +8 mux_tree_tapbuf_size2_10_sram[1]:5 mux_right_track_22\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_10_sram[1]:4 mux_tree_tapbuf_size2_10_sram[1]:3 0.004707589 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.0007738743 //LENGTH 6.595 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.545 44.880 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 67.720 46.920 +*I mem_top_track_4\/FTB_2__23:A I *L 0.001746 *C 66.240 47.600 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 66.278 47.600 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 67.663 47.600 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 67.720 47.235 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 67.720 46.943 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 66.745 46.920 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 66.700 46.875 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 66.700 44.925 +*N mux_tree_tapbuf_size2_1_sram[1]:10 *C 66.700 44.880 +*N mux_tree_tapbuf_size2_1_sram[1]:11 *C 66.545 44.880 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_4\/FTB_2__23:A 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 9.879819e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:4 0.0001251572 +5 mux_tree_tapbuf_size2_1_sram[1]:5 5.035033e-05 +6 mux_tree_tapbuf_size2_1_sram[1]:6 9.086657e-05 +7 mux_tree_tapbuf_size2_1_sram[1]:7 6.68752e-05 +8 mux_tree_tapbuf_size2_1_sram[1]:8 0.000120149 +9 mux_tree_tapbuf_size2_1_sram[1]:9 0.000120149 +10 mux_tree_tapbuf_size2_1_sram[1]:10 4.954635e-05 +11 mux_tree_tapbuf_size2_1_sram[1]:11 4.898253e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:6 mux_top_track_4\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[1]:6 mux_tree_tapbuf_size2_1_sram[1]:5 0.0002611607 +3 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.0008705357 +4 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_1_sram[1]:9 mux_tree_tapbuf_size2_1_sram[1]:8 0.001741072 +7 mux_tree_tapbuf_size2_1_sram[1]:11 mux_tree_tapbuf_size2_1_sram[1]:10 8.423914e-05 +8 mux_tree_tapbuf_size2_1_sram[1]:3 mem_top_track_4\/FTB_2__23:A 0.152 +9 mux_tree_tapbuf_size2_1_sram[1]:4 mux_tree_tapbuf_size2_1_sram[1]:3 0.001236607 +10 mux_tree_tapbuf_size2_1_sram[1]:5 mux_tree_tapbuf_size2_1_sram[1]:4 0.0002122093 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[1] 0.0009743271 //LENGTH 7.480 LUMPCC 0 DR + +*CONN +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 89.545 49.980 +*I mux_right_track_18\/mux_l2_in_0_:S I *L 0.00357 *C 89.600 44.880 +*I mem_right_track_18\/FTB_9__30:A I *L 0.001746 *C 91.080 44.880 +*N mux_tree_tapbuf_size2_8_sram[1]:3 *C 91.043 44.880 +*N mux_tree_tapbuf_size2_8_sram[1]:4 *C 89.745 44.880 +*N mux_tree_tapbuf_size2_8_sram[1]:5 *C 89.700 44.925 +*N mux_tree_tapbuf_size2_8_sram[1]:6 *C 89.700 49.935 +*N mux_tree_tapbuf_size2_8_sram[1]:7 *C 89.700 49.980 +*N mux_tree_tapbuf_size2_8_sram[1]:8 *C 89.545 49.980 + +*CAP +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_18\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_18\/FTB_9__30:A 1e-06 +3 mux_tree_tapbuf_size2_8_sram[1]:3 0.0001188572 +4 mux_tree_tapbuf_size2_8_sram[1]:4 0.0001188572 +5 mux_tree_tapbuf_size2_8_sram[1]:5 0.0003193596 +6 mux_tree_tapbuf_size2_8_sram[1]:6 0.0003193596 +7 mux_tree_tapbuf_size2_8_sram[1]:7 4.922891e-05 +8 mux_tree_tapbuf_size2_8_sram[1]:8 4.566456e-05 + +*RES +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_8_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_8_sram[1]:4 mux_right_track_18\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_8_sram[1]:4 mux_tree_tapbuf_size2_8_sram[1]:3 0.001158482 +3 mux_tree_tapbuf_size2_8_sram[1]:5 mux_tree_tapbuf_size2_8_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_8_sram[1]:7 mux_tree_tapbuf_size2_8_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size2_8_sram[1]:6 mux_tree_tapbuf_size2_8_sram[1]:5 0.004473215 +6 mux_tree_tapbuf_size2_8_sram[1]:8 mux_tree_tapbuf_size2_8_sram[1]:7 8.423914e-05 +7 mux_tree_tapbuf_size2_8_sram[1]:3 mem_right_track_18\/FTB_9__30:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_5_ccff_tail[0] 0.0008292582 //LENGTH 6.710 LUMPCC 0.0002164106 DR + +*CONN +*I mem_right_track_12\/FTB_6__27:X O *L 0 *C 62.335 55.420 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 58.595 53.380 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 *C 58.633 53.380 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 *C 59.755 53.380 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 *C 59.800 53.425 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 *C 59.800 55.375 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 *C 59.845 55.420 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 *C 62.298 55.420 + +*CAP +0 mem_right_track_12\/FTB_6__27:X 1e-06 +1 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 8.564606e-05 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 8.564606e-05 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.000123128 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.000123128 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 9.664975e-05 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 9.664975e-05 +8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001082053 +9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001082053 + +*RES +0 mem_right_track_12\/FTB_6__27:X mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.002189732 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.001002232 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.004148612 //LENGTH 32.400 LUMPCC 0.0002512313 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.805 63.920 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.495 60.860 +*I mux_right_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 72.320 69.360 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 72.320 72.080 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 72.220 72.080 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 72.220 72.035 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 72.220 69.360 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 72.220 69.360 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 65.532 60.860 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 66.240 60.860 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 66.240 60.520 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 72.175 60.520 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 72.220 60.565 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 72.220 61.540 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 72.265 61.540 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 78.615 61.540 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 78.660 61.585 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 78.660 64.215 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 78.705 64.260 +*N mux_tree_tapbuf_size3_1_sram[0]:19 *C 79.120 64.260 +*N mux_tree_tapbuf_size3_1_sram[0]:20 *C 79.120 63.920 +*N mux_tree_tapbuf_size3_1_sram[0]:21 *C 80.767 63.920 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_24\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 3.350045e-05 +5 mux_tree_tapbuf_size3_1_sram[0]:5 0.0001699335 +6 mux_tree_tapbuf_size3_1_sram[0]:6 3.466706e-05 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0006466574 +8 mux_tree_tapbuf_size3_1_sram[0]:8 6.322383e-05 +9 mux_tree_tapbuf_size3_1_sram[0]:9 8.71084e-05 +10 mux_tree_tapbuf_size3_1_sram[0]:10 0.0003581566 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.000334272 +12 mux_tree_tapbuf_size3_1_sram[0]:12 6.66798e-05 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0005392253 +14 mux_tree_tapbuf_size3_1_sram[0]:14 0.0003799144 +15 mux_tree_tapbuf_size3_1_sram[0]:15 0.0003799144 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.0001728863 +17 mux_tree_tapbuf_size3_1_sram[0]:17 0.0001728863 +18 mux_tree_tapbuf_size3_1_sram[0]:18 5.201657e-05 +19 mux_tree_tapbuf_size3_1_sram[0]:19 7.749826e-05 +20 mux_tree_tapbuf_size3_1_sram[0]:20 0.0001751609 +21 mux_tree_tapbuf_size3_1_sram[0]:21 0.0001496793 +22 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[1]:13 0.0001256156 +23 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[1]:12 0.0001256156 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:21 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.0008705358 +3 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:7 0.006982143 +4 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.005669643 +5 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.0045 +6 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.0045 +7 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.002348214 +8 mux_tree_tapbuf_size3_1_sram[0]:21 mux_tree_tapbuf_size3_1_sram[0]:20 0.001470982 +9 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.005299107 +10 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size3_1_sram[0]:8 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size3_1_sram[0]:4 mux_right_track_24\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size3_1_sram[0]:5 mux_tree_tapbuf_size3_1_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size3_1_sram[0]:6 mux_right_track_24\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:6 0.0045 +16 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:5 0.002388393 +17 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:8 0.0006316964 +18 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0003035715 +19 mux_tree_tapbuf_size3_1_sram[0]:19 mux_tree_tapbuf_size3_1_sram[0]:18 0.0003705357 +20 mux_tree_tapbuf_size3_1_sram[0]:20 mux_tree_tapbuf_size3_1_sram[0]:19 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.00114613 //LENGTH 10.025 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 92.765 66.300 +*I mem_right_track_4\/FTB_14__35:A I *L 0.001746 *C 92.000 69.360 +*I mux_right_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 93.280 61.880 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 93.265 61.880 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 92.943 61.880 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 92.920 61.925 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 92.920 66.255 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 92.797 66.300 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 92.000 69.360 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 92.000 69.315 +*N mux_tree_tapbuf_size6_1_sram[2]:10 *C 92.000 66.345 +*N mux_tree_tapbuf_size6_1_sram[2]:11 *C 92.045 66.300 +*N mux_tree_tapbuf_size6_1_sram[2]:12 *C 92.728 66.300 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_4\/FTB_14__35:A 1e-06 +2 mux_right_track_4\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 5.428938e-05 +4 mux_tree_tapbuf_size6_1_sram[2]:4 5.428938e-05 +5 mux_tree_tapbuf_size6_1_sram[2]:5 0.0002545432 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0002545432 +7 mux_tree_tapbuf_size6_1_sram[2]:7 2.060189e-05 +8 mux_tree_tapbuf_size6_1_sram[2]:8 3.029697e-05 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.000175112 +10 mux_tree_tapbuf_size6_1_sram[2]:10 0.000175112 +11 mux_tree_tapbuf_size6_1_sram[2]:11 5.187001e-05 +12 mux_tree_tapbuf_size6_1_sram[2]:12 7.24719e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:12 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:12 mux_tree_tapbuf_size6_1_sram[2]:11 0.000609375 +2 mux_tree_tapbuf_size6_1_sram[2]:12 mux_tree_tapbuf_size6_1_sram[2]:7 6.25e-05 +3 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.003866072 +5 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.0001752718 +6 mux_tree_tapbuf_size6_1_sram[2]:5 mux_tree_tapbuf_size6_1_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size6_1_sram[2]:3 mux_right_track_4\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_1_sram[2]:11 mux_tree_tapbuf_size6_1_sram[2]:10 0.0045 +9 mux_tree_tapbuf_size6_1_sram[2]:10 mux_tree_tapbuf_size6_1_sram[2]:9 0.002651786 +10 mux_tree_tapbuf_size6_1_sram[2]:8 mem_right_track_4\/FTB_14__35:A 0.152 +11 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.0045 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004826456 //LENGTH 45.750 LUMPCC 0.0003511434 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 40.195 48.280 +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 36.105 88.270 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 36.105 88.270 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.215 88.400 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 37.260 88.355 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 37.260 67.365 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 37.305 67.320 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 39.055 67.320 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 39.100 67.275 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 39.100 48.325 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 39.145 48.280 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 40.157 48.280 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001017705 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.380309e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0009904463 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0009904463 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001298047 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001298047 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0009484923 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0009484923 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 8.01264e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 8.01264e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 4.21417e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 4.21417e-05 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.00013343 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.00013343 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0009040179 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.01691964 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0015625 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01874107 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009910715 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001527069 //LENGTH 13.670 LUMPCC 0.0001305661 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_0_:X O *L 0 *C 84.005 41.820 +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 92.200 36.915 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 92.200 36.915 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 37.060 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 37.105 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.000 41.775 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 91.955 41.820 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 84.043 41.820 + +*CAP +0 mux_right_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.664288e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.719385e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002442558 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002442558 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000406077 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000406077 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[6]:23 4.32815e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[6]:24 2.200155e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[6]:24 4.32815e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[6]:25 2.200155e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.007064732 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001086957 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001714993 //LENGTH 15.515 LUMPCC 0 DR + +*CONN +*I mux_right_track_22\/mux_l2_in_0_:X O *L 0 *C 101.025 63.580 +*I mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 107.865 55.630 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 107.828 55.718 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 104.465 55.760 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 104.420 55.805 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 104.420 63.535 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 104.375 63.580 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 101.062 63.580 + +*CAP +0 mux_right_track_22\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002109596 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002109596 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004169763 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004169763 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002285606 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002285606 + +*RES +0 mux_right_track_22\/mux_l2_in_0_:X mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003002232 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00295759 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009829109 //LENGTH 7.565 LUMPCC 0.0002384135 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 85.385 69.020 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 86.580 63.580 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.543 63.580 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.065 63.580 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.020 63.625 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.020 68.975 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 85.975 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 85.422 69.020 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.424508e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.424508e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002389155 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002389155 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.808805e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.808805e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001192067 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001192067 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004776786 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002568388 //LENGTH 20.065 LUMPCC 0.00109433 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_0_:X O *L 0 *C 75.725 88.060 +*I mux_right_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 79.220 72.420 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 79.183 72.420 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 76.405 72.420 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 76.360 72.465 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 76.360 88.015 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 76.315 88.060 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 75.763 88.060 + +*CAP +0 mux_right_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.104336e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.104336e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0006117917 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0006117917 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.319367e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.319367e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[8]:6 1.648931e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[8]:10 0.0001223187 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[8]:5 1.648931e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[8]:9 0.0001223187 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 right_top_grid_pin_44_[0]:17 0.0001150152 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 right_top_grid_pin_44_[0]:16 0.0001150152 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_0_sram[2]:9 0.0001150152 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_0_sram[2]:10 0.0001150152 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 optlc_net_112:24 0.0001183845 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 optlc_net_112:15 0.0001183845 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.994227e-05 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.994227e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002479911 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01388393 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004272912 //LENGTH 2.590 LUMPCC 0.0001524851 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_1_:X O *L 0 *C 71.475 70.040 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 69.175 70.040 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 69.213 70.040 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 71.438 70.040 + +*CAP +0 mux_right_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001364031 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001364031 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 right_bottom_grid_pin_1_[0]:17 7.624253e-05 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 right_bottom_grid_pin_1_[0]:18 7.624253e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001986607 + +*END + +*D_NET chany_top_out[15] 0.001732925 //LENGTH 9.980 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 48.025 98.600 +*P chany_top_out[15] O *L 0.7423 *C 46.000 102.075 +*N chany_top_out[15]:2 *C 46.000 99.288 +*N chany_top_out[15]:3 *C 46.020 99.280 +*N chany_top_out[15]:4 *C 49.672 99.280 +*N chany_top_out[15]:5 *C 49.680 99.223 +*N chany_top_out[15]:6 *C 49.680 98.645 +*N chany_top_out[15]:7 *C 49.635 98.600 +*N chany_top_out[15]:8 *C 48.062 98.600 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 chany_top_out[15] 0.0002140879 +2 chany_top_out[15]:2 0.0002140879 +3 chany_top_out[15]:3 0.0004444625 +4 chany_top_out[15]:4 0.0004444625 +5 chany_top_out[15]:5 7.01092e-05 +6 chany_top_out[15]:6 7.01092e-05 +7 chany_top_out[15]:7 0.000137303 +8 chany_top_out[15]:8 0.000137303 + +*RES +0 ropt_mt_inst_732:X chany_top_out[15]:8 0.152 +1 chany_top_out[15]:3 chany_top_out[15]:2 0.00341 +2 chany_top_out[15]:2 chany_top_out[15] 0.0004367083 +3 chany_top_out[15]:5 chany_top_out[15]:4 0.00341 +4 chany_top_out[15]:4 chany_top_out[15]:3 0.000572225 +5 chany_top_out[15]:7 chany_top_out[15]:6 0.0045 +6 chany_top_out[15]:6 chany_top_out[15]:5 0.000515625 +7 chany_top_out[15]:8 chany_top_out[15]:7 0.001404018 + +*END + +*D_NET chany_top_out[17] 0.00106063 //LENGTH 9.255 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 58.880 99.960 +*P chany_top_out[17] O *L 0.7423 *C 52.900 102.070 +*N chany_top_out[17]:2 *C 52.900 101.378 +*N chany_top_out[17]:3 *C 52.908 101.320 +*N chany_top_out[17]:4 *C 56.573 101.320 +*N chany_top_out[17]:5 *C 56.580 101.263 +*N chany_top_out[17]:6 *C 56.580 100.005 +*N chany_top_out[17]:7 *C 56.625 99.960 +*N chany_top_out[17]:8 *C 58.843 99.960 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 chany_top_out[17] 5.729574e-05 +2 chany_top_out[17]:2 5.729574e-05 +3 chany_top_out[17]:3 0.0002421619 +4 chany_top_out[17]:4 0.0002421619 +5 chany_top_out[17]:5 7.549443e-05 +6 chany_top_out[17]:6 7.549443e-05 +7 chany_top_out[17]:7 0.0001548631 +8 chany_top_out[17]:8 0.0001548631 + +*RES +0 ropt_mt_inst_736:X chany_top_out[17]:8 0.152 +1 chany_top_out[17]:8 chany_top_out[17]:7 0.001979911 +2 chany_top_out[17]:7 chany_top_out[17]:6 0.0045 +3 chany_top_out[17]:6 chany_top_out[17]:5 0.001122768 +4 chany_top_out[17]:5 chany_top_out[17]:4 0.00341 +5 chany_top_out[17]:4 chany_top_out[17]:3 0.0005741833 +6 chany_top_out[17]:2 chany_top_out[17] 0.0006183035 +7 chany_top_out[17]:3 chany_top_out[17]:2 0.00341 + +*END + +*D_NET ropt_net_120 0.002278086 //LENGTH 15.465 LUMPCC 0.0008738341 DR + +*CONN +*I BUFT_RR_82:X O *L 0 *C 56.315 96.900 +*I ropt_mt_inst_732:A I *L 0.001766 *C 44.160 99.280 +*N ropt_net_120:2 *C 44.198 99.280 +*N ropt_net_120:3 *C 48.255 99.280 +*N ropt_net_120:4 *C 48.300 99.235 +*N ropt_net_120:5 *C 48.300 96.945 +*N ropt_net_120:6 *C 48.345 96.900 +*N ropt_net_120:7 *C 56.278 96.900 + +*CAP +0 BUFT_RR_82:X 1e-06 +1 ropt_mt_inst_732:A 1e-06 +2 ropt_net_120:2 0.0001810641 +3 ropt_net_120:3 0.0001810641 +4 ropt_net_120:4 0.0001544948 +5 ropt_net_120:5 0.0001544948 +6 ropt_net_120:6 0.0003655671 +7 ropt_net_120:7 0.0003655671 +8 ropt_net_120:6 chanx_right_in[4]:2 9.027078e-05 +9 ropt_net_120:6 chanx_right_in[4]:4 3.072818e-05 +10 ropt_net_120:7 chanx_right_in[4]:3 9.027078e-05 +11 ropt_net_120:7 chanx_right_in[4]:5 3.072818e-05 +12 ropt_net_120:4 ropt_net_145:4 1.200898e-05 +13 ropt_net_120:6 ropt_net_145:6 0.0001437504 +14 ropt_net_120:5 ropt_net_145:5 1.200898e-05 +15 ropt_net_120:7 ropt_net_145:7 0.0001437504 +16 ropt_net_120:2 BUF_net_62:3 0.0001601588 +17 ropt_net_120:3 BUF_net_62:4 0.0001601588 + +*RES +0 BUFT_RR_82:X ropt_net_120:7 0.152 +1 ropt_net_120:2 ropt_mt_inst_732:A 0.152 +2 ropt_net_120:3 ropt_net_120:2 0.003622768 +3 ropt_net_120:4 ropt_net_120:3 0.0045 +4 ropt_net_120:6 ropt_net_120:5 0.0045 +5 ropt_net_120:5 ropt_net_120:4 0.002044643 +6 ropt_net_120:7 ropt_net_120:6 0.007082589 + +*END + +*D_NET chany_top_in[15] 0.01393015 //LENGTH 126.355 LUMPCC 0.004058841 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 49.680 102.150 +*I ropt_mt_inst_743:A I *L 0.001767 *C 106.260 39.440 +*N chany_top_in[15]:2 *C 106.297 39.440 +*N chany_top_in[15]:3 *C 108.055 39.440 +*N chany_top_in[15]:4 *C 108.100 39.485 +*N chany_top_in[15]:5 *C 108.100 42.795 +*N chany_top_in[15]:6 *C 108.055 42.840 +*N chany_top_in[15]:7 *C 100.360 42.840 +*N chany_top_in[15]:8 *C 100.290 42.830 +*N chany_top_in[15]:9 *C 100.280 42.205 +*N chany_top_in[15]:10 *C 100.235 42.160 +*N chany_top_in[15]:11 *C 99.405 42.160 +*N chany_top_in[15]:12 *C 99.360 42.160 +*N chany_top_in[15]:13 *C 99.353 42.160 +*N chany_top_in[15]:14 *C 49.700 42.160 +*N chany_top_in[15]:15 *C 49.680 42.168 +*N chany_top_in[15]:16 *C 49.680 91.995 + +*CAP +0 chany_top_in[15] 0.0004840824 +1 ropt_mt_inst_743:A 1e-06 +2 chany_top_in[15]:2 0.0001359193 +3 chany_top_in[15]:3 0.0001359193 +4 chany_top_in[15]:4 0.000190402 +5 chany_top_in[15]:5 0.000190402 +6 chany_top_in[15]:6 0.0005178771 +7 chany_top_in[15]:7 0.0005178771 +8 chany_top_in[15]:8 4.843285e-05 +9 chany_top_in[15]:9 4.843285e-05 +10 chany_top_in[15]:10 6.415923e-05 +11 chany_top_in[15]:11 6.415923e-05 +12 chany_top_in[15]:12 3.494268e-05 +13 chany_top_in[15]:13 0.0013451 +14 chany_top_in[15]:14 0.0013451 +15 chany_top_in[15]:15 0.002131708 +16 chany_top_in[15]:16 0.002615791 +17 chany_top_in[15]:6 chany_top_in[14]:4 4.234692e-05 +18 chany_top_in[15]:7 chany_top_in[14]:3 4.234692e-05 +19 chany_top_in[15]:8 chany_top_in[14]:6 4.162322e-07 +20 chany_top_in[15]:9 chany_top_in[14]:5 4.162322e-07 +21 chany_top_in[15]:13 chany_top_in[14]:7 0.0002843637 +22 chany_top_in[15]:13 chany_top_in[14]:8 0.0004944106 +23 chany_top_in[15]:14 chany_top_in[14]:8 0.0002843637 +24 chany_top_in[15]:14 chany_top_in[14]:9 0.0004944106 +25 chany_top_in[15]:8 chanx_right_in[15]:9 2.233954e-06 +26 chany_top_in[15]:9 chanx_right_in[15]:8 2.233954e-06 +27 chany_top_in[15]:13 chanx_right_in[15]:7 0.0005804251 +28 chany_top_in[15]:13 chanx_right_in[15]:6 0.0002359105 +29 chany_top_in[15]:14 chanx_right_in[15]:5 0.0002359105 +30 chany_top_in[15]:14 chanx_right_in[15]:6 0.0005804251 +31 chany_top_in[15] chany_top_in[11]:8 8.454915e-05 +32 chany_top_in[15]:15 chany_top_in[11]:7 0.0002493077 +33 chany_top_in[15]:16 chany_top_in[11]:7 8.454915e-05 +34 chany_top_in[15]:16 chany_top_in[11]:8 0.0002493077 +35 chany_top_in[15]:2 ropt_net_146:16 3.799884e-05 +36 chany_top_in[15]:3 ropt_net_146:15 3.799884e-05 +37 chany_top_in[15]:4 ropt_net_146:13 1.745746e-05 +38 chany_top_in[15]:5 ropt_net_146:14 1.745746e-05 + +*RES +0 chany_top_in[15] chany_top_in[15]:16 0.00159095 +1 chany_top_in[15]:2 ropt_mt_inst_743:A 0.152 +2 chany_top_in[15]:3 chany_top_in[15]:2 0.001569197 +3 chany_top_in[15]:4 chany_top_in[15]:3 0.0045 +4 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +5 chany_top_in[15]:5 chany_top_in[15]:4 0.002955357 +6 chany_top_in[15]:7 chany_top_in[15]:6 0.006870536 +7 chany_top_in[15]:8 chany_top_in[15]:7 0.0045 +8 chany_top_in[15]:10 chany_top_in[15]:9 0.0045 +9 chany_top_in[15]:9 chany_top_in[15]:8 0.0005580357 +10 chany_top_in[15]:11 chany_top_in[15]:10 0.0007410715 +11 chany_top_in[15]:12 chany_top_in[15]:11 0.0045 +12 chany_top_in[15]:13 chany_top_in[15]:12 0.00341 +13 chany_top_in[15]:14 chany_top_in[15]:13 0.007778891 +14 chany_top_in[15]:15 chany_top_in[15]:14 0.00341 +15 chany_top_in[15]:16 chany_top_in[15]:15 0.007806308 + +*END + +*D_NET ccff_head[0] 0.0067947 //LENGTH 64.920 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 110.860 1.290 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 82.515 37.060 +*N ccff_head[0]:2 *C 82.515 37.060 +*N ccff_head[0]:3 *C 82.800 37.060 +*N ccff_head[0]:4 *C 82.800 37.015 +*N ccff_head[0]:5 *C 82.800 34.385 +*N ccff_head[0]:6 *C 82.845 34.340 +*N ccff_head[0]:7 *C 110.815 34.340 +*N ccff_head[0]:8 *C 110.860 34.295 + +*CAP +0 ccff_head[0] 0.001655167 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 4.465247e-05 +3 ccff_head[0]:3 4.833546e-05 +4 ccff_head[0]:4 0.0001430222 +5 ccff_head[0]:5 0.0001430222 +6 ccff_head[0]:6 0.001552166 +7 ccff_head[0]:7 0.001552166 +8 ccff_head[0]:8 0.001655167 + +*RES +0 ccff_head[0] ccff_head[0]:8 0.02946875 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001548913 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:6 ccff_head[0]:5 0.0045 +5 ccff_head[0]:5 ccff_head[0]:4 0.002348214 +6 ccff_head[0]:7 ccff_head[0]:6 0.02497322 +7 ccff_head[0]:8 ccff_head[0]:7 0.0045 + +*END + +*D_NET chanx_right_out[1] 0.001172292 //LENGTH 7.765 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 66.300 +*P chanx_right_out[1] O *L 0.7423 *C 111.855 66.640 +*N chanx_right_out[1]:2 *C 111.328 66.640 +*N chanx_right_out[1]:3 *C 111.320 66.640 +*N chanx_right_out[1]:4 *C 111.320 66.300 +*N chanx_right_out[1]:5 *C 111.275 66.300 +*N chanx_right_out[1]:6 *C 104.918 66.300 + +*CAP +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[1] 9.277993e-05 +2 chanx_right_out[1]:2 9.277993e-05 +3 chanx_right_out[1]:3 5.868939e-05 +4 chanx_right_out[1]:4 5.49565e-05 +5 chanx_right_out[1]:5 0.0004360432 +6 chanx_right_out[1]:6 0.0004360432 + +*RES +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[1]:6 0.152 +1 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +2 chanx_right_out[1]:2 chanx_right_out[1] 8.264166e-05 +3 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +4 chanx_right_out[1]:4 chanx_right_out[1]:3 0.0001634615 +5 chanx_right_out[1]:6 chanx_right_out[1]:5 0.005676339 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.002565828 //LENGTH 21.735 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 88.165 37.060 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 74.160 39.440 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 73.310 37.060 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 73.310 37.060 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 73.140 37.060 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 73.140 37.105 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 73.140 39.055 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 73.185 39.100 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 74.520 39.100 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 74.198 39.440 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 74.520 39.440 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 87.815 39.440 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 87.860 39.395 +*N mux_tree_tapbuf_size2_0_sram[0]:13 *C 87.860 37.105 +*N mux_tree_tapbuf_size2_0_sram[0]:14 *C 87.860 37.060 +*N mux_tree_tapbuf_size2_0_sram[0]:15 *C 88.165 37.060 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 5.763131e-05 +4 mux_tree_tapbuf_size2_0_sram[0]:4 5.655645e-05 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.0001547476 +6 mux_tree_tapbuf_size2_0_sram[0]:6 0.0001547476 +7 mux_tree_tapbuf_size2_0_sram[0]:7 0.0001020118 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0001287477 +9 mux_tree_tapbuf_size2_0_sram[0]:9 3.94782e-05 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0007916954 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.0007254813 +12 mux_tree_tapbuf_size2_0_sram[0]:12 0.0001273935 +13 mux_tree_tapbuf_size2_0_sram[0]:13 0.0001273935 +14 mux_tree_tapbuf_size2_0_sram[0]:14 4.945856e-05 +15 mux_tree_tapbuf_size2_0_sram[0]:15 4.748509e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.01187054 +2 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.0045 +3 mux_tree_tapbuf_size2_0_sram[0]:14 mux_tree_tapbuf_size2_0_sram[0]:13 0.0045 +4 mux_tree_tapbuf_size2_0_sram[0]:13 mux_tree_tapbuf_size2_0_sram[0]:12 0.002044643 +5 mux_tree_tapbuf_size2_0_sram[0]:15 mux_tree_tapbuf_size2_0_sram[0]:14 0.0001657609 +6 mux_tree_tapbuf_size2_0_sram[0]:9 mux_top_track_0\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_0_sram[0]:3 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 1e-05 +9 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.0045 +11 mux_tree_tapbuf_size2_0_sram[0]:6 mux_tree_tapbuf_size2_0_sram[0]:5 0.001741072 +12 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.001191964 +13 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0002879465 +14 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:8 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[0] 0.002411432 //LENGTH 19.435 LUMPCC 0.0004232049 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.345 49.980 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 72.855 47.940 +*I mux_right_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 80.860 57.800 +*N mux_tree_tapbuf_size2_7_sram[0]:3 *C 80.845 57.800 +*N mux_tree_tapbuf_size2_7_sram[0]:4 *C 80.523 57.800 +*N mux_tree_tapbuf_size2_7_sram[0]:5 *C 80.500 57.755 +*N mux_tree_tapbuf_size2_7_sram[0]:6 *C 80.500 50.025 +*N mux_tree_tapbuf_size2_7_sram[0]:7 *C 80.377 49.980 +*N mux_tree_tapbuf_size2_7_sram[0]:8 *C 72.892 47.940 +*N mux_tree_tapbuf_size2_7_sram[0]:9 *C 77.235 47.940 +*N mux_tree_tapbuf_size2_7_sram[0]:10 *C 77.280 47.985 +*N mux_tree_tapbuf_size2_7_sram[0]:11 *C 77.280 49.935 +*N mux_tree_tapbuf_size2_7_sram[0]:12 *C 77.325 49.980 +*N mux_tree_tapbuf_size2_7_sram[0]:13 *C 80.308 49.980 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_16\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_7_sram[0]:3 5.138749e-05 +4 mux_tree_tapbuf_size2_7_sram[0]:4 5.138749e-05 +5 mux_tree_tapbuf_size2_7_sram[0]:5 0.000322119 +6 mux_tree_tapbuf_size2_7_sram[0]:6 0.000322119 +7 mux_tree_tapbuf_size2_7_sram[0]:7 2.056605e-05 +8 mux_tree_tapbuf_size2_7_sram[0]:8 0.0002932054 +9 mux_tree_tapbuf_size2_7_sram[0]:9 0.0002932054 +10 mux_tree_tapbuf_size2_7_sram[0]:10 0.0001206773 +11 mux_tree_tapbuf_size2_7_sram[0]:11 0.0001206773 +12 mux_tree_tapbuf_size2_7_sram[0]:12 0.0001846584 +13 mux_tree_tapbuf_size2_7_sram[0]:13 0.0002052245 +14 mux_tree_tapbuf_size2_7_sram[0]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.56532e-07 +15 mux_tree_tapbuf_size2_7_sram[0]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.56532e-07 +16 mux_tree_tapbuf_size2_7_sram[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 8.347769e-07 +17 mux_tree_tapbuf_size2_7_sram[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.347769e-07 +18 mux_tree_tapbuf_size2_7_sram[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002106111 +19 mux_tree_tapbuf_size2_7_sram[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002106111 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_7_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_7_sram[0]:12 mux_tree_tapbuf_size2_7_sram[0]:11 0.0045 +2 mux_tree_tapbuf_size2_7_sram[0]:11 mux_tree_tapbuf_size2_7_sram[0]:10 0.001741071 +3 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:8 0.003877232 +4 mux_tree_tapbuf_size2_7_sram[0]:10 mux_tree_tapbuf_size2_7_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size2_7_sram[0]:8 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_7_sram[0]:3 mux_right_track_16\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_7_sram[0]:4 mux_tree_tapbuf_size2_7_sram[0]:3 0.0001752718 +8 mux_tree_tapbuf_size2_7_sram[0]:5 mux_tree_tapbuf_size2_7_sram[0]:4 0.0045 +9 mux_tree_tapbuf_size2_7_sram[0]:7 mux_tree_tapbuf_size2_7_sram[0]:6 0.0045 +10 mux_tree_tapbuf_size2_7_sram[0]:6 mux_tree_tapbuf_size2_7_sram[0]:5 0.006901786 +11 mux_tree_tapbuf_size2_7_sram[0]:13 mux_tree_tapbuf_size2_7_sram[0]:12 0.002662947 +12 mux_tree_tapbuf_size2_7_sram[0]:13 mux_tree_tapbuf_size2_7_sram[0]:7 6.25e-05 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.001683983 //LENGTH 12.865 LUMPCC 0.000103399 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 88.625 61.200 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 87.300 63.240 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 87.125 66.300 +*I mux_right_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 88.220 55.760 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 88.220 55.760 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 88.320 55.805 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 87.125 66.300 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 87.400 66.300 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 87.400 66.255 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 87.300 63.240 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 87.400 63.240 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 87.400 62.560 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 87.860 62.560 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 87.860 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 88.320 61.155 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 88.320 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 88.625 61.200 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_4\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 2.856801e-05 +5 mux_tree_tapbuf_size6_1_sram[1]:5 0.0002670926 +6 mux_tree_tapbuf_size6_1_sram[1]:6 5.428938e-05 +7 mux_tree_tapbuf_size6_1_sram[1]:7 5.89907e-05 +8 mux_tree_tapbuf_size6_1_sram[1]:8 0.0001705251 +9 mux_tree_tapbuf_size6_1_sram[1]:9 2.826037e-05 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.00024127 +11 mux_tree_tapbuf_size6_1_sram[1]:11 6.899337e-05 +12 mux_tree_tapbuf_size6_1_sram[1]:12 0.0001235508 +13 mux_tree_tapbuf_size6_1_sram[1]:13 0.0001260309 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0003012833 +15 mux_tree_tapbuf_size6_1_sram[1]:15 5.502812e-05 +16 mux_tree_tapbuf_size6_1_sram[1]:16 5.270111e-05 +17 mux_tree_tapbuf_size6_1_sram[1]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.169951e-05 +18 mux_tree_tapbuf_size6_1_sram[1]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.169951e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:6 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:7 mux_tree_tapbuf_size6_1_sram[1]:6 0.0001494565 +3 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.0004107143 +6 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:5 0.004776786 +7 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.0001657609 +8 mux_tree_tapbuf_size6_1_sram[1]:4 mux_right_track_4\/mux_l2_in_1_:S 0.152 +9 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size6_1_sram[1]:9 mux_right_track_4\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:8 0.002691964 +13 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.0006071429 +14 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.0004107143 +15 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.001214286 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005979943 //LENGTH 4.285 LUMPCC 0.00010307 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_2_:X O *L 0 *C 85.845 57.800 +*I mux_right_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 87.500 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 87.463 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 86.985 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 86.940 56.145 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 86.940 57.755 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 86.895 57.800 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 85.883 57.800 + +*CAP +0 mux_right_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.661183e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.661183e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001163683 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001163683 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.348196e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.348196e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 right_top_grid_pin_48_[0]:13 5.153502e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 right_top_grid_pin_48_[0]:12 5.153502e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009040179 + +*END + +*D_NET chany_top_out[5] 0.0009704849 //LENGTH 7.515 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 43.700 96.220 +*P chany_top_out[5] O *L 0.7423 *C 44.620 102.070 +*N chany_top_out[5]:2 *C 44.620 101.660 +*N chany_top_out[5]:3 *C 44.160 101.660 +*N chany_top_out[5]:4 *C 44.160 96.265 +*N chany_top_out[5]:5 *C 44.115 96.220 +*N chany_top_out[5]:6 *C 43.738 96.220 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 chany_top_out[5] 3.557053e-05 +2 chany_top_out[5]:2 6.323079e-05 +3 chany_top_out[5]:3 0.0003928178 +4 chany_top_out[5]:4 0.0003651575 +5 chany_top_out[5]:5 5.635416e-05 +6 chany_top_out[5]:6 5.635416e-05 + +*RES +0 ropt_mt_inst_757:X chany_top_out[5]:6 0.152 +1 chany_top_out[5]:6 chany_top_out[5]:5 0.0003370536 +2 chany_top_out[5]:5 chany_top_out[5]:4 0.0045 +3 chany_top_out[5]:4 chany_top_out[5]:3 0.004816964 +4 chany_top_out[5]:3 chany_top_out[5]:2 0.0004107143 +5 chany_top_out[5]:2 chany_top_out[5] 0.0003660714 + +*END + +*D_NET BUF_net_57 0.002862445 //LENGTH 23.865 LUMPCC 0.0004596403 DR + +*CONN +*I BUFT_RR_57:X O *L 0 *C 46.000 83.300 +*I BUFT_RR_78:A I *L 0.001766 *C 38.005 96.560 +*N BUF_net_57:2 *C 38.850 96.560 +*N BUF_net_57:3 *C 38.043 96.560 +*N BUF_net_57:4 *C 39.515 96.560 +*N BUF_net_57:5 *C 39.560 96.560 +*N BUF_net_57:6 *C 39.558 96.560 +*N BUF_net_57:7 *C 39.560 96.553 +*N BUF_net_57:8 *C 39.560 85.008 +*N BUF_net_57:9 *C 39.580 85.000 +*N BUF_net_57:10 *C 45.992 85.000 +*N BUF_net_57:11 *C 46.000 84.943 +*N BUF_net_57:12 *C 46.000 83.685 +*N BUF_net_57:13 *C 46.000 83.640 +*N BUF_net_57:14 *C 46.000 83.300 + +*CAP +0 BUFT_RR_57:X 1e-06 +1 BUFT_RR_78:A 1e-06 +2 BUF_net_57:2 8.681085e-05 +3 BUF_net_57:3 5.18075e-05 +4 BUF_net_57:4 5.18075e-05 +5 BUF_net_57:5 3.726286e-05 +6 BUF_net_57:6 8.681085e-05 +7 BUF_net_57:7 0.0004734574 +8 BUF_net_57:8 0.0004734574 +9 BUF_net_57:9 0.0004090693 +10 BUF_net_57:10 0.0004090693 +11 BUF_net_57:11 8.401937e-05 +12 BUF_net_57:12 8.401937e-05 +13 BUF_net_57:13 7.929037e-05 +14 BUF_net_57:14 7.392213e-05 +15 BUF_net_57:7 chanx_right_in[2]:7 9.096541e-05 +16 BUF_net_57:8 chanx_right_in[2]:8 9.096541e-05 +17 BUF_net_57:9 chanx_right_in[9]:11 6.862178e-05 +18 BUF_net_57:10 chanx_right_in[9]:12 6.862178e-05 +19 BUF_net_57:3 ropt_net_125:8 7.023299e-05 +20 BUF_net_57:4 ropt_net_125:7 7.023299e-05 + +*RES +0 BUFT_RR_57:X BUF_net_57:14 0.152 +1 BUF_net_57:3 BUFT_RR_78:A 0.152 +2 BUF_net_57:4 BUF_net_57:3 0.001314732 +3 BUF_net_57:5 BUF_net_57:4 0.0045 +4 BUF_net_57:6 BUF_net_57:5 0.00341 +5 BUF_net_57:6 BUF_net_57:2 0.0001039141 +6 BUF_net_57:7 BUF_net_57:6 0.00341 +7 BUF_net_57:9 BUF_net_57:8 0.00341 +8 BUF_net_57:8 BUF_net_57:7 0.001808717 +9 BUF_net_57:11 BUF_net_57:10 0.00341 +10 BUF_net_57:10 BUF_net_57:9 0.001004625 +11 BUF_net_57:13 BUF_net_57:12 0.0045 +12 BUF_net_57:12 BUF_net_57:11 0.001122768 +13 BUF_net_57:14 BUF_net_57:13 0.0001465518 + +*END + +*D_NET chany_top_in[16] 0.0132618 //LENGTH 100.640 LUMPCC 0.002850888 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 58.880 102.150 +*I ropt_mt_inst_745:A I *L 0.001767 *C 106.260 63.920 +*N chany_top_in[16]:2 *C 106.260 63.920 +*N chany_top_in[16]:3 *C 106.260 64.260 +*N chany_top_in[16]:4 *C 111.735 64.260 +*N chany_top_in[16]:5 *C 111.780 64.305 +*N chany_top_in[16]:6 *C 111.780 71.695 +*N chany_top_in[16]:7 *C 111.735 71.740 +*N chany_top_in[16]:8 *C 102.580 71.740 +*N chany_top_in[16]:9 *C 102.580 71.400 +*N chany_top_in[16]:10 *C 102.580 71.400 +*N chany_top_in[16]:11 *C 102.580 72.035 +*N chany_top_in[16]:12 *C 102.535 72.080 +*N chany_top_in[16]:13 *C 101.705 72.080 +*N chany_top_in[16]:14 *C 101.660 72.125 +*N chany_top_in[16]:15 *C 101.660 74.075 +*N chany_top_in[16]:16 *C 101.615 74.120 +*N chany_top_in[16]:17 *C 79.625 74.120 +*N chany_top_in[16]:18 *C 79.580 74.165 +*N chany_top_in[16]:19 *C 79.580 80.862 +*N chany_top_in[16]:20 *C 79.573 80.920 +*N chany_top_in[16]:21 *C 58.900 80.920 +*N chany_top_in[16]:22 *C 58.880 80.928 + +*CAP +0 chany_top_in[16] 0.001059822 +1 ropt_mt_inst_745:A 1e-06 +2 chany_top_in[16]:2 5.732145e-05 +3 chany_top_in[16]:3 0.0003823548 +4 chany_top_in[16]:4 0.0003542526 +5 chany_top_in[16]:5 0.0004000907 +6 chany_top_in[16]:6 0.0004000907 +7 chany_top_in[16]:7 0.0004077107 +8 chany_top_in[16]:8 0.0004348552 +9 chany_top_in[16]:9 5.964281e-05 +10 chany_top_in[16]:10 5.924234e-05 +11 chany_top_in[16]:11 5.924234e-05 +12 chany_top_in[16]:12 7.474989e-05 +13 chany_top_in[16]:13 7.474989e-05 +14 chany_top_in[16]:14 0.0001101056 +15 chany_top_in[16]:15 0.0001101056 +16 chany_top_in[16]:16 0.001207198 +17 chany_top_in[16]:17 0.001207198 +18 chany_top_in[16]:18 0.0004441077 +19 chany_top_in[16]:19 0.0004441077 +20 chany_top_in[16]:20 0.001001572 +21 chany_top_in[16]:21 0.001001572 +22 chany_top_in[16]:22 0.001059822 +23 chany_top_in[16]:14 chanx_right_in[9]:16 6.286045e-06 +24 chany_top_in[16]:15 chanx_right_in[9]:17 6.286045e-06 +25 chany_top_in[16]:20 chanx_right_in[9]:12 0.0002414191 +26 chany_top_in[16]:21 chanx_right_in[9]:11 0.0002414191 +27 chany_top_in[16]:7 chanx_right_in[9]:16 5.826055e-06 +28 chany_top_in[16]:8 chanx_right_in[9]:15 5.826055e-06 +29 chany_top_in[16]:14 chanx_right_in[17]:17 3.9352e-06 +30 chany_top_in[16]:16 chanx_right_in[17]:15 5.406843e-06 +31 chany_top_in[16]:15 chanx_right_in[17]:16 3.9352e-06 +32 chany_top_in[16]:17 chanx_right_in[17]:14 5.406843e-06 +33 chany_top_in[16]:20 chanx_right_in[17]:11 7.731679e-06 +34 chany_top_in[16]:20 chanx_right_in[17]:7 0.0002646359 +35 chany_top_in[16]:21 chanx_right_in[17]:10 7.731679e-06 +36 chany_top_in[16]:21 chanx_right_in[17]:6 0.0002646359 +37 chany_top_in[16]:5 chanx_right_in[17]:23 4.908409e-06 +38 chany_top_in[16]:7 chanx_right_in[17]:21 7.70504e-05 +39 chany_top_in[16]:7 chanx_right_in[17]:19 8.181424e-05 +40 chany_top_in[16]:6 chanx_right_in[17]:22 4.908409e-06 +41 chany_top_in[16]:8 chanx_right_in[17]:18 8.181424e-05 +42 chany_top_in[16]:8 chanx_right_in[17]:20 7.70504e-05 +43 chany_top_in[16] chany_top_in[10]:14 0.0002925585 +44 chany_top_in[16]:16 chany_top_in[10]:5 0.0004333371 +45 chany_top_in[16]:17 chany_top_in[10]:6 0.0004333371 +46 chany_top_in[16]:20 chany_top_in[10]:11 5.345074e-07 +47 chany_top_in[16]:21 chany_top_in[10]:12 5.345074e-07 +48 chany_top_in[16]:22 chany_top_in[10]:13 0.0002925585 + +*RES +0 chany_top_in[16] chany_top_in[16]:22 0.003324858 +1 chany_top_in[16]:12 chany_top_in[16]:11 0.0045 +2 chany_top_in[16]:11 chany_top_in[16]:10 0.0005669643 +3 chany_top_in[16]:13 chany_top_in[16]:12 0.0007410714 +4 chany_top_in[16]:14 chany_top_in[16]:13 0.0045 +5 chany_top_in[16]:16 chany_top_in[16]:15 0.0045 +6 chany_top_in[16]:15 chany_top_in[16]:14 0.001741071 +7 chany_top_in[16]:17 chany_top_in[16]:16 0.01963393 +8 chany_top_in[16]:18 chany_top_in[16]:17 0.0045 +9 chany_top_in[16]:19 chany_top_in[16]:18 0.005979911 +10 chany_top_in[16]:20 chany_top_in[16]:19 0.00341 +11 chany_top_in[16]:21 chany_top_in[16]:20 0.003238692 +12 chany_top_in[16]:22 chany_top_in[16]:21 0.00341 +13 chany_top_in[16]:2 ropt_mt_inst_745:A 0.152 +14 chany_top_in[16]:4 chany_top_in[16]:3 0.004888393 +15 chany_top_in[16]:5 chany_top_in[16]:4 0.0045 +16 chany_top_in[16]:7 chany_top_in[16]:6 0.0045 +17 chany_top_in[16]:6 chany_top_in[16]:5 0.006598215 +18 chany_top_in[16]:9 chany_top_in[16]:8 0.0003035715 +19 chany_top_in[16]:10 chany_top_in[16]:9 0.0045 +20 chany_top_in[16]:8 chany_top_in[16]:7 0.008174107 +21 chany_top_in[16]:3 chany_top_in[16]:2 0.0003035714 + +*END + +*D_NET chany_top_in[0] 0.002179389 //LENGTH 17.835 LUMPCC 0 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 67.620 102.070 +*I mux_right_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.700 90.780 +*N chany_top_in[0]:2 *C 73.663 90.780 +*N chany_top_in[0]:3 *C 67.665 90.780 +*N chany_top_in[0]:4 *C 67.620 90.825 + +*CAP +0 chany_top_in[0] 0.0006639069 +1 mux_right_track_2\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[0]:2 0.0004252878 +3 chany_top_in[0]:3 0.0004252878 +4 chany_top_in[0]:4 0.0006639069 + +*RES +0 chany_top_in[0] chany_top_in[0]:4 0.01004018 +1 chany_top_in[0]:2 mux_right_track_2\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[0]:3 chany_top_in[0]:2 0.005354911 +3 chany_top_in[0]:4 chany_top_in[0]:3 0.0045 + +*END + +*D_NET chany_top_in[2] 0.001104383 //LENGTH 9.045 LUMPCC 0 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 70.380 102.035 +*I mux_right_track_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 71.300 94.180 +*N chany_top_in[2]:2 *C 71.300 94.180 +*N chany_top_in[2]:3 *C 71.300 94.180 +*N chany_top_in[2]:4 *C 70.380 94.180 + +*CAP +0 chany_top_in[2] 0.0004549596 +1 mux_right_track_6\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[2]:2 3.645373e-05 +3 chany_top_in[2]:3 9.575907e-05 +4 chany_top_in[2]:4 0.0005162103 + +*RES +0 chany_top_in[2] chany_top_in[2]:4 0.007013394 +1 chany_top_in[2]:2 mux_right_track_6\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[2]:3 chany_top_in[2]:2 0.0045 +3 chany_top_in[2]:4 chany_top_in[2]:3 0.0008214285 + +*END + +*D_NET chany_top_in[4] 0.002658026 //LENGTH 21.470 LUMPCC 0.0001791112 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 43.700 102.070 +*I mux_right_track_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.765 83.300 +*N chany_top_in[4]:2 *C 41.765 83.300 +*N chany_top_in[4]:3 *C 41.860 83.345 +*N chany_top_in[4]:4 *C 41.860 95.823 +*N chany_top_in[4]:5 *C 41.867 95.880 +*N chany_top_in[4]:6 *C 43.693 95.880 +*N chany_top_in[4]:7 *C 43.700 95.938 + +*CAP +0 chany_top_in[4] 0.0004033819 +1 mux_right_track_10\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[4]:2 2.812545e-05 +3 chany_top_in[4]:3 0.000640224 +4 chany_top_in[4]:4 0.000640224 +5 chany_top_in[4]:5 0.000181289 +6 chany_top_in[4]:6 0.000181289 +7 chany_top_in[4]:7 0.0004033819 +8 chany_top_in[4]:3 BUF_net_64:6 8.955559e-05 +9 chany_top_in[4]:4 BUF_net_64:5 8.955559e-05 + +*RES +0 chany_top_in[4] chany_top_in[4]:7 0.005475447 +1 chany_top_in[4]:2 mux_right_track_10\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[4]:3 chany_top_in[4]:2 0.0045 +3 chany_top_in[4]:4 chany_top_in[4]:3 0.01114062 +4 chany_top_in[4]:5 chany_top_in[4]:4 0.00341 +5 chany_top_in[4]:7 chany_top_in[4]:6 0.00341 +6 chany_top_in[4]:6 chany_top_in[4]:5 0.0002859167 + +*END + +*D_NET chany_top_in[8] 0.008672703 //LENGTH 70.665 LUMPCC 0.002716816 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 63.020 102.070 +*I mux_right_track_18\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.440 52.700 +*N chany_top_in[8]:2 *C 82.403 52.700 +*N chany_top_in[8]:3 *C 79.625 52.700 +*N chany_top_in[8]:4 *C 79.580 52.745 +*N chany_top_in[8]:5 *C 79.580 54.343 +*N chany_top_in[8]:6 *C 79.573 54.400 +*N chany_top_in[8]:7 *C 66.260 54.400 +*N chany_top_in[8]:8 *C 66.240 54.408 +*N chany_top_in[8]:9 *C 66.240 100.633 +*N chany_top_in[8]:10 *C 66.220 100.640 +*N chany_top_in[8]:11 *C 63.028 100.640 +*N chany_top_in[8]:12 *C 63.020 100.698 + +*CAP +0 chany_top_in[8] 8.851744e-05 +1 mux_right_track_18\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[8]:2 0.000201146 +3 chany_top_in[8]:3 0.000201146 +4 chany_top_in[8]:4 0.0001123833 +5 chany_top_in[8]:5 0.0001123833 +6 chany_top_in[8]:6 0.0006799868 +7 chany_top_in[8]:7 0.0006799868 +8 chany_top_in[8]:8 0.00166564 +9 chany_top_in[8]:9 0.00166564 +10 chany_top_in[8]:10 0.0002297697 +11 chany_top_in[8]:11 0.0002297697 +12 chany_top_in[8]:12 8.851744e-05 +13 chany_top_in[8]:8 chanx_right_in[19]:8 0.0005718758 +14 chany_top_in[8]:9 chanx_right_in[19]:7 0.0005718758 +15 chany_top_in[8]:8 chany_top_in[7]:9 0.0004786508 +16 chany_top_in[8]:9 chany_top_in[7]:10 0.0004786508 +17 chany_top_in[8]:6 chanx_right_in[13]:7 0.0003078816 +18 chany_top_in[8]:7 chanx_right_in[13]:6 0.0003078816 + +*RES +0 chany_top_in[8] chany_top_in[8]:12 0.001225446 +1 chany_top_in[8]:2 mux_right_track_18\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[8]:3 chany_top_in[8]:2 0.002479911 +3 chany_top_in[8]:4 chany_top_in[8]:3 0.0045 +4 chany_top_in[8]:5 chany_top_in[8]:4 0.001426339 +5 chany_top_in[8]:6 chany_top_in[8]:5 0.00341 +6 chany_top_in[8]:7 chany_top_in[8]:6 0.002085625 +7 chany_top_in[8]:8 chany_top_in[8]:7 0.00341 +8 chany_top_in[8]:10 chany_top_in[8]:9 0.00341 +9 chany_top_in[8]:9 chany_top_in[8]:8 0.007241916 +10 chany_top_in[8]:12 chany_top_in[8]:11 0.00341 +11 chany_top_in[8]:11 chany_top_in[8]:10 0.0005001583 + +*END + +*D_NET chanx_right_in[3] 0.007785817 //LENGTH 78.435 LUMPCC 0 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 111.930 8.160 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 69.290 42.500 +*N chanx_right_in[3]:2 *C 69.328 42.500 +*N chanx_right_in[3]:3 *C 69.875 42.500 +*N chanx_right_in[3]:4 *C 69.920 42.455 +*N chanx_right_in[3]:5 *C 69.920 9.225 +*N chanx_right_in[3]:6 *C 69.965 9.180 +*N chanx_right_in[3]:7 *C 108.975 9.180 +*N chanx_right_in[3]:8 *C 109.020 9.135 +*N chanx_right_in[3]:9 *C 109.020 8.218 +*N chanx_right_in[3]:10 *C 109.028 8.160 + +*CAP +0 chanx_right_in[3] 0.0002247206 +1 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[3]:2 7.516153e-05 +3 chanx_right_in[3]:3 7.516153e-05 +4 chanx_right_in[3]:4 0.001580403 +5 chanx_right_in[3]:5 0.001580403 +6 chanx_right_in[3]:6 0.001945753 +7 chanx_right_in[3]:7 0.001945753 +8 chanx_right_in[3]:8 6.637047e-05 +9 chanx_right_in[3]:9 6.637047e-05 +10 chanx_right_in[3]:10 0.0002247206 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:10 0.000454725 +1 chanx_right_in[3]:2 mux_top_track_4\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[3]:3 chanx_right_in[3]:2 0.0004888393 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0045 +4 chanx_right_in[3]:6 chanx_right_in[3]:5 0.0045 +5 chanx_right_in[3]:5 chanx_right_in[3]:4 0.02966965 +6 chanx_right_in[3]:7 chanx_right_in[3]:6 0.03483036 +7 chanx_right_in[3]:8 chanx_right_in[3]:7 0.0045 +8 chanx_right_in[3]:9 chanx_right_in[3]:8 0.0008191965 +9 chanx_right_in[3]:10 chanx_right_in[3]:9 0.00341 + +*END + +*D_NET right_top_grid_pin_44_[0] 0.009035766 //LENGTH 64.952 LUMPCC 0.0006518407 DR + +*CONN +*P right_top_grid_pin_44_[0] I *L 0.29796 *C 110.860 74.870 +*I mux_right_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.445 72.420 +*I mux_right_track_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 53.200 69.700 +*I mux_right_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 87.305 72.420 +*N right_top_grid_pin_44_[0]:4 *C 87.305 72.420 +*N right_top_grid_pin_44_[0]:5 *C 68.493 72.420 +*N right_top_grid_pin_44_[0]:6 *C 53.200 69.700 +*N right_top_grid_pin_44_[0]:7 *C 54.695 69.700 +*N right_top_grid_pin_44_[0]:8 *C 54.740 69.700 +*N right_top_grid_pin_44_[0]:9 *C 54.740 70.040 +*N right_top_grid_pin_44_[0]:10 *C 54.748 70.040 +*N right_top_grid_pin_44_[0]:11 *C 64.853 70.040 +*N right_top_grid_pin_44_[0]:12 *C 64.860 70.097 +*N right_top_grid_pin_44_[0]:13 *C 64.860 72.375 +*N right_top_grid_pin_44_[0]:14 *C 64.905 72.420 +*N right_top_grid_pin_44_[0]:15 *C 68.530 72.443 +*N right_top_grid_pin_44_[0]:16 *C 68.540 72.760 +*N right_top_grid_pin_44_[0]:17 *C 87.400 72.760 +*N right_top_grid_pin_44_[0]:18 *C 110.815 72.760 +*N right_top_grid_pin_44_[0]:19 *C 110.860 72.805 + +*CAP +0 right_top_grid_pin_44_[0] 0.0001224354 +1 mux_right_track_0\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_12\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_4\/mux_l1_in_1_:A1 1e-06 +4 right_top_grid_pin_44_[0]:4 4.907543e-05 +5 right_top_grid_pin_44_[0]:5 1.581436e-05 +6 right_top_grid_pin_44_[0]:6 0.0001695596 +7 right_top_grid_pin_44_[0]:7 0.0001271609 +8 right_top_grid_pin_44_[0]:8 5.020963e-05 +9 right_top_grid_pin_44_[0]:9 5.404617e-05 +10 right_top_grid_pin_44_[0]:10 0.0006036212 +11 right_top_grid_pin_44_[0]:11 0.0006036212 +12 right_top_grid_pin_44_[0]:12 0.0001941942 +13 right_top_grid_pin_44_[0]:13 0.0001941942 +14 right_top_grid_pin_44_[0]:14 0.0002503974 +15 right_top_grid_pin_44_[0]:15 0.0002869162 +16 right_top_grid_pin_44_[0]:16 0.001170982 +17 right_top_grid_pin_44_[0]:17 0.002770479 +18 right_top_grid_pin_44_[0]:18 0.001595783 +19 right_top_grid_pin_44_[0]:19 0.0001224354 +20 right_top_grid_pin_44_[0]:16 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 7.734932e-05 +21 right_top_grid_pin_44_[0]:17 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 7.734932e-05 +22 right_top_grid_pin_44_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.286903e-06 +23 right_top_grid_pin_44_[0]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 8.97498e-08 +24 right_top_grid_pin_44_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.97498e-08 +25 right_top_grid_pin_44_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001281792 +26 right_top_grid_pin_44_[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001281792 +27 right_top_grid_pin_44_[0]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.286903e-06 +28 right_top_grid_pin_44_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001150152 +29 right_top_grid_pin_44_[0]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001150152 + +*RES +0 right_top_grid_pin_44_[0] right_top_grid_pin_44_[0]:19 0.00184375 +1 right_top_grid_pin_44_[0]:14 right_top_grid_pin_44_[0]:13 0.0045 +2 right_top_grid_pin_44_[0]:13 right_top_grid_pin_44_[0]:12 0.002033482 +3 right_top_grid_pin_44_[0]:12 right_top_grid_pin_44_[0]:11 0.00341 +4 right_top_grid_pin_44_[0]:11 right_top_grid_pin_44_[0]:10 0.001583117 +5 right_top_grid_pin_44_[0]:9 right_top_grid_pin_44_[0]:8 0.0001634615 +6 right_top_grid_pin_44_[0]:10 right_top_grid_pin_44_[0]:9 0.00341 +7 right_top_grid_pin_44_[0]:7 right_top_grid_pin_44_[0]:6 0.001334821 +8 right_top_grid_pin_44_[0]:8 right_top_grid_pin_44_[0]:7 0.0045 +9 right_top_grid_pin_44_[0]:6 mux_right_track_12\/mux_l1_in_0_:A0 0.152 +10 right_top_grid_pin_44_[0]:15 mux_right_track_0\/mux_l1_in_1_:A1 0.152 +11 right_top_grid_pin_44_[0]:15 right_top_grid_pin_44_[0]:14 0.003236607 +12 right_top_grid_pin_44_[0]:15 right_top_grid_pin_44_[0]:5 3.348214e-05 +13 right_top_grid_pin_44_[0]:4 mux_right_track_4\/mux_l1_in_1_:A1 0.152 +14 right_top_grid_pin_44_[0]:18 right_top_grid_pin_44_[0]:17 0.02090625 +15 right_top_grid_pin_44_[0]:19 right_top_grid_pin_44_[0]:18 0.0045 +16 right_top_grid_pin_44_[0]:16 right_top_grid_pin_44_[0]:15 0.0002834821 +17 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:16 0.01683929 +18 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:4 0.0003035715 + +*END + +*D_NET chanx_right_out[8] 0.002458774 //LENGTH 21.830 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 93.900 37.060 +*P chanx_right_out[8] O *L 0.7423 *C 111.855 34.000 +*N chanx_right_out[8]:2 *C 108.108 34.000 +*N chanx_right_out[8]:3 *C 108.100 34.058 +*N chanx_right_out[8]:4 *C 108.100 37.015 +*N chanx_right_out[8]:5 *C 108.055 37.060 +*N chanx_right_out[8]:6 *C 93.938 37.060 + +*CAP +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[8] 0.000239478 +2 chanx_right_out[8]:2 0.000239478 +3 chanx_right_out[8]:3 0.0002190312 +4 chanx_right_out[8]:4 0.0002190312 +5 chanx_right_out[8]:5 0.000770378 +6 chanx_right_out[8]:6 0.000770378 + +*RES +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +2 chanx_right_out[8]:2 chanx_right_out[8] 0.0005871083 +3 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +4 chanx_right_out[8]:4 chanx_right_out[8]:3 0.002640625 +5 chanx_right_out[8]:6 chanx_right_out[8]:5 0.01260491 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[0] 0.004565606 //LENGTH 38.725 LUMPCC 0 DR + +*CONN +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.485 60.860 +*I mux_right_track_26\/mux_l1_in_0_:S I *L 0.00357 *C 62.000 82.960 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 52.155 66.300 +*N mux_tree_tapbuf_size2_11_sram[0]:3 *C 52.193 66.300 +*N mux_tree_tapbuf_size2_11_sram[0]:4 *C 61.963 82.960 +*N mux_tree_tapbuf_size2_11_sram[0]:5 *C 57.545 82.960 +*N mux_tree_tapbuf_size2_11_sram[0]:6 *C 57.500 82.915 +*N mux_tree_tapbuf_size2_11_sram[0]:7 *C 57.500 74.165 +*N mux_tree_tapbuf_size2_11_sram[0]:8 *C 57.455 74.120 +*N mux_tree_tapbuf_size2_11_sram[0]:9 *C 56.625 74.120 +*N mux_tree_tapbuf_size2_11_sram[0]:10 *C 56.580 74.075 +*N mux_tree_tapbuf_size2_11_sram[0]:11 *C 56.580 66.345 +*N mux_tree_tapbuf_size2_11_sram[0]:12 *C 56.580 66.300 +*N mux_tree_tapbuf_size2_11_sram[0]:13 *C 61.135 66.300 +*N mux_tree_tapbuf_size2_11_sram[0]:14 *C 61.180 66.255 +*N mux_tree_tapbuf_size2_11_sram[0]:15 *C 61.180 60.905 +*N mux_tree_tapbuf_size2_11_sram[0]:16 *C 61.180 60.860 +*N mux_tree_tapbuf_size2_11_sram[0]:17 *C 61.485 60.860 + +*CAP +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_26\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_11_sram[0]:3 0.0003054002 +4 mux_tree_tapbuf_size2_11_sram[0]:4 0.0003123418 +5 mux_tree_tapbuf_size2_11_sram[0]:5 0.0003123418 +6 mux_tree_tapbuf_size2_11_sram[0]:6 0.0005051027 +7 mux_tree_tapbuf_size2_11_sram[0]:7 0.0005051027 +8 mux_tree_tapbuf_size2_11_sram[0]:8 7.92884e-05 +9 mux_tree_tapbuf_size2_11_sram[0]:9 7.92884e-05 +10 mux_tree_tapbuf_size2_11_sram[0]:10 0.0004477927 +11 mux_tree_tapbuf_size2_11_sram[0]:11 0.0004477927 +12 mux_tree_tapbuf_size2_11_sram[0]:12 0.0006279972 +13 mux_tree_tapbuf_size2_11_sram[0]:13 0.0002947105 +14 mux_tree_tapbuf_size2_11_sram[0]:14 0.0002776423 +15 mux_tree_tapbuf_size2_11_sram[0]:15 0.0002776423 +16 mux_tree_tapbuf_size2_11_sram[0]:16 4.693033e-05 +17 mux_tree_tapbuf_size2_11_sram[0]:17 4.323249e-05 + +*RES +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_11_sram[0]:17 0.152 +1 mux_tree_tapbuf_size2_11_sram[0]:3 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_11_sram[0]:13 mux_tree_tapbuf_size2_11_sram[0]:12 0.004066965 +3 mux_tree_tapbuf_size2_11_sram[0]:14 mux_tree_tapbuf_size2_11_sram[0]:13 0.0045 +4 mux_tree_tapbuf_size2_11_sram[0]:16 mux_tree_tapbuf_size2_11_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size2_11_sram[0]:15 mux_tree_tapbuf_size2_11_sram[0]:14 0.004776786 +6 mux_tree_tapbuf_size2_11_sram[0]:17 mux_tree_tapbuf_size2_11_sram[0]:16 0.0001657609 +7 mux_tree_tapbuf_size2_11_sram[0]:12 mux_tree_tapbuf_size2_11_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size2_11_sram[0]:12 mux_tree_tapbuf_size2_11_sram[0]:3 0.003917411 +9 mux_tree_tapbuf_size2_11_sram[0]:11 mux_tree_tapbuf_size2_11_sram[0]:10 0.006901787 +10 mux_tree_tapbuf_size2_11_sram[0]:9 mux_tree_tapbuf_size2_11_sram[0]:8 0.0007410714 +11 mux_tree_tapbuf_size2_11_sram[0]:10 mux_tree_tapbuf_size2_11_sram[0]:9 0.0045 +12 mux_tree_tapbuf_size2_11_sram[0]:8 mux_tree_tapbuf_size2_11_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size2_11_sram[0]:7 mux_tree_tapbuf_size2_11_sram[0]:6 0.0078125 +14 mux_tree_tapbuf_size2_11_sram[0]:5 mux_tree_tapbuf_size2_11_sram[0]:4 0.003944197 +15 mux_tree_tapbuf_size2_11_sram[0]:6 mux_tree_tapbuf_size2_11_sram[0]:5 0.0045 +16 mux_tree_tapbuf_size2_11_sram[0]:4 mux_right_track_26\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.00137215 //LENGTH 9.730 LUMPCC 0.000619231 DR + +*CONN +*I mem_right_track_10\/FTB_5__26:X O *L 0 *C 35.240 74.460 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 39.280 69.700 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 39.242 69.700 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 36.845 69.700 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 *C 36.800 69.745 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 *C 36.800 74.415 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 *C 36.755 74.460 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 *C 35.278 74.460 + +*CAP +0 mem_right_track_10\/FTB_5__26:X 1e-06 +1 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 9.757307e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 9.757307e-05 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0001654225 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0001654225 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.000112464 +7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.000112464 +8 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 prog_clk[0]:60 5.547253e-05 +9 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 prog_clk[0]:61 5.547253e-05 +10 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 prog_clk[0]:65 5.044994e-06 +11 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 prog_clk[0]:71 1.19827e-05 +12 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 prog_clk[0]:71 5.044994e-06 +13 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 prog_clk[0]:72 1.19827e-05 +14 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 chany_top_in[5]:4 0.0001036852 +15 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 chany_top_in[5]:5 0.0001036852 +16 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00013343 +17 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00013343 + +*RES +0 mem_right_track_10\/FTB_5__26:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 0.002140625 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.004169643 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.001319197 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.003097334 //LENGTH 23.465 LUMPCC 8.529167e-05 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 81.725 66.640 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 82.975 60.860 +*I mux_right_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 85.000 58.480 +*I mux_right_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 86.580 72.080 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 84.540 69.070 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 84.540 69.070 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 86.543 72.080 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 84.685 72.080 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 84.640 72.035 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 84.640 69.405 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 84.583 69.330 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 84.517 69.330 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 84.210 69.330 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 84.180 69.315 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 84.985 58.480 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 84.663 58.480 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 84.640 58.525 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 84.640 60.860 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 83.013 60.860 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 84.135 60.860 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 84.180 60.860 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 84.180 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 84.135 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:23 *C 81.763 66.640 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_4\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_4\/mux_l1_in_1_:S 1e-06 +4 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 5.472433e-05 +6 mux_tree_tapbuf_size6_1_sram[0]:6 0.000168489 +7 mux_tree_tapbuf_size6_1_sram[0]:7 0.000168489 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0001604521 +9 mux_tree_tapbuf_size6_1_sram[0]:9 0.0001604521 +10 mux_tree_tapbuf_size6_1_sram[0]:10 2.358032e-05 +11 mux_tree_tapbuf_size6_1_sram[0]:11 9.531777e-05 +12 mux_tree_tapbuf_size6_1_sram[0]:12 4.716065e-05 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0001658985 +14 mux_tree_tapbuf_size6_1_sram[0]:14 6.22588e-05 +15 mux_tree_tapbuf_size6_1_sram[0]:15 6.22588e-05 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.0001562973 +17 mux_tree_tapbuf_size6_1_sram[0]:17 0.0001928376 +18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001229138 +19 mux_tree_tapbuf_size6_1_sram[0]:19 0.0001229138 +20 mux_tree_tapbuf_size6_1_sram[0]:20 0.0003480261 +21 mux_tree_tapbuf_size6_1_sram[0]:21 0.0005088365 +22 mux_tree_tapbuf_size6_1_sram[0]:22 0.0001930682 +23 mux_tree_tapbuf_size6_1_sram[0]:23 0.0001930682 +24 mux_tree_tapbuf_size6_1_sram[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.628685e-06 +25 mux_tree_tapbuf_size6_1_sram[0]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.786313e-06 +26 mux_tree_tapbuf_size6_1_sram[0]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.628685e-06 +27 mux_tree_tapbuf_size6_1_sram[0]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.786313e-06 +28 mux_tree_tapbuf_size6_1_sram[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.523084e-05 +29 mux_tree_tapbuf_size6_1_sram[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.523084e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:23 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:14 mux_right_track_4\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.0001752718 +3 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.0045 +4 mux_tree_tapbuf_size6_1_sram[0]:5 mux_right_track_4\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_1_sram[0]:12 mux_tree_tapbuf_size6_1_sram[0]:11 0.0001921875 +6 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.0045 +7 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.001002232 +8 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.0045 +9 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:17 0.0004107143 +10 mux_tree_tapbuf_size6_1_sram[0]:18 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:21 0.0045 +12 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.005160714 +13 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:13 0.002388393 +14 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:22 0.002118304 +15 mux_tree_tapbuf_size6_1_sram[0]:10 mux_tree_tapbuf_size6_1_sram[0]:9 0.0045 +16 mux_tree_tapbuf_size6_1_sram[0]:9 mux_tree_tapbuf_size6_1_sram[0]:8 0.002348214 +17 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.001658482 +18 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.0045 +19 mux_tree_tapbuf_size6_1_sram[0]:6 mux_right_track_4\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 4.0625e-05 +21 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:5 0.000112069 +22 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:16 0.002084821 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006395878 //LENGTH 4.665 LUMPCC 0 DR + +*CONN +*I mux_right_track_6\/mux_l2_in_0_:X O *L 0 *C 80.325 91.460 +*I mux_right_track_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 79.120 94.180 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 79.120 94.180 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 79.120 93.840 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 79.995 93.840 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 80.040 93.795 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 80.040 91.505 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 80.040 91.460 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 80.325 91.460 + +*CAP +0 mux_right_track_6\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_6\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.360397e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.811235e-05 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.106066e-05 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001523136 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001523136 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.586191e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.432167e-05 + +*RES +0 mux_right_track_6\/mux_l2_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001548913 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002044643 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.00078125 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_6\/mux_l3_in_0_:A1 0.152 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET chany_top_out[1] 0.001008882 //LENGTH 8.220 LUMPCC 0.0001898264 DR + +*CONN +*I ropt_mt_inst_767:X O *L 0 *C 29.635 98.600 +*P chany_top_out[1] O *L 0.7423 *C 25.760 102.340 +*N chany_top_out[1]:2 *C 26.220 102.340 +*N chany_top_out[1]:3 *C 26.220 98.645 +*N chany_top_out[1]:4 *C 26.265 98.600 +*N chany_top_out[1]:5 *C 29.598 98.600 + +*CAP +0 ropt_mt_inst_767:X 1e-06 +1 chany_top_out[1] 3.052946e-05 +2 chany_top_out[1]:2 0.0001841393 +3 chany_top_out[1]:3 0.0001536098 +4 chany_top_out[1]:4 0.0002248885 +5 chany_top_out[1]:5 0.0002248885 +6 chany_top_out[1]:5 ropt_net_144:3 1.366731e-05 +7 chany_top_out[1]:4 ropt_net_144:2 1.366731e-05 +8 chany_top_out[1]:3 ropt_net_144:4 7.471584e-05 +9 chany_top_out[1]:3 ropt_net_144:9 6.530046e-06 +10 chany_top_out[1]:2 ropt_net_144:5 7.471584e-05 +11 chany_top_out[1]:2 ropt_net_144:8 6.530046e-06 + +*RES +0 ropt_mt_inst_767:X chany_top_out[1]:5 0.152 +1 chany_top_out[1]:5 chany_top_out[1]:4 0.002975446 +2 chany_top_out[1]:4 chany_top_out[1]:3 0.0045 +3 chany_top_out[1]:3 chany_top_out[1]:2 0.003299107 +4 chany_top_out[1]:2 chany_top_out[1] 0.0004107143 + +*END + +*D_NET chanx_right_out[18] 0.0007122073 //LENGTH 5.670 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 107.180 20.060 +*P chanx_right_out[18] O *L 0.7423 *C 111.930 20.400 +*N chanx_right_out[18]:2 *C 110.407 20.400 +*N chanx_right_out[18]:3 *C 110.400 20.400 +*N chanx_right_out[18]:4 *C 110.355 20.400 +*N chanx_right_out[18]:5 *C 107.180 20.400 +*N chanx_right_out[18]:6 *C 107.180 20.060 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 chanx_right_out[18] 0.0001219419 +2 chanx_right_out[18]:2 0.0001219419 +3 chanx_right_out[18]:3 3.555512e-05 +4 chanx_right_out[18]:4 0.0001782482 +5 chanx_right_out[18]:5 0.0002032022 +6 chanx_right_out[18]:6 5.031809e-05 + +*RES +0 ropt_mt_inst_747:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +2 chanx_right_out[18]:2 chanx_right_out[18] 0.000238525 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.0045 +4 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0003035715 +5 chanx_right_out[18]:5 chanx_right_out[18]:4 0.002834822 + +*END + +*D_NET chany_top_in[17] 0.01649908 //LENGTH 175.100 LUMPCC 0.001331563 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 14.720 102.150 +*I ropt_mt_inst_747:A I *L 0.001767 *C 106.260 20.400 +*N chany_top_in[17]:2 *C 106.223 20.400 +*N chany_top_in[17]:3 *C 105.845 20.400 +*N chany_top_in[17]:4 *C 105.800 20.445 +*N chany_top_in[17]:5 *C 105.800 25.795 +*N chany_top_in[17]:6 *C 105.755 25.840 +*N chany_top_in[17]:7 *C 68.700 25.840 +*N chany_top_in[17]:8 *C 18.905 25.840 +*N chany_top_in[17]:9 *C 18.860 25.885 +*N chany_top_in[17]:10 *C 18.860 75.680 +*N chany_top_in[17]:11 *C 18.860 97.863 +*N chany_top_in[17]:12 *C 18.852 97.920 +*N chany_top_in[17]:13 *C 14.740 97.920 +*N chany_top_in[17]:14 *C 14.720 97.928 + +*CAP +0 chany_top_in[17] 0.000233534 +1 ropt_mt_inst_747:A 1e-06 +2 chany_top_in[17]:2 3.978632e-05 +3 chany_top_in[17]:3 3.978632e-05 +4 chany_top_in[17]:4 0.0002339178 +5 chany_top_in[17]:5 0.0002339178 +6 chany_top_in[17]:6 0.001812176 +7 chany_top_in[17]:7 0.004178831 +8 chany_top_in[17]:8 0.002366656 +9 chany_top_in[17]:9 0.001742367 +10 chany_top_in[17]:10 0.002612313 +11 chany_top_in[17]:11 0.0008699454 +12 chany_top_in[17]:12 0.0002848785 +13 chany_top_in[17]:13 0.0002848785 +14 chany_top_in[17]:14 0.000233534 +15 chany_top_in[17] chany_top_in[13] 2.562183e-05 +16 chany_top_in[17]:4 chany_top_in[13]:5 4.461578e-05 +17 chany_top_in[17]:5 chany_top_in[13]:6 4.461578e-05 +18 chany_top_in[17]:9 chany_top_in[13]:17 0.0004689837 +19 chany_top_in[17]:11 chany_top_in[13] 5.509636e-06 +20 chany_top_in[17]:11 chany_top_in[13]:18 3.223612e-05 +21 chany_top_in[17]:11 chany_top_in[13]:19 8.881444e-05 +22 chany_top_in[17]:14 chany_top_in[13]:21 2.562183e-05 +23 chany_top_in[17]:10 chany_top_in[13]:17 3.223612e-05 +24 chany_top_in[17]:10 chany_top_in[13]:18 0.0005577982 +25 chany_top_in[17]:10 chany_top_in[13]:21 5.509636e-06 + +*RES +0 chany_top_in[17] chany_top_in[17]:14 0.0006615249 +1 chany_top_in[17]:2 ropt_mt_inst_747:A 0.152 +2 chany_top_in[17]:3 chany_top_in[17]:2 0.0003370536 +3 chany_top_in[17]:4 chany_top_in[17]:3 0.0045 +4 chany_top_in[17]:6 chany_top_in[17]:5 0.0045 +5 chany_top_in[17]:5 chany_top_in[17]:4 0.004776786 +6 chany_top_in[17]:8 chany_top_in[17]:7 0.04445983 +7 chany_top_in[17]:9 chany_top_in[17]:8 0.0045 +8 chany_top_in[17]:11 chany_top_in[17]:10 0.01980581 +9 chany_top_in[17]:12 chany_top_in[17]:11 0.00341 +10 chany_top_in[17]:13 chany_top_in[17]:12 0.0006442916 +11 chany_top_in[17]:14 chany_top_in[17]:13 0.00341 +12 chany_top_in[17]:7 chany_top_in[17]:6 0.03308482 +13 chany_top_in[17]:10 chany_top_in[17]:9 0.04445983 + +*END + +*D_NET chanx_right_in[15] 0.01637964 //LENGTH 154.640 LUMPCC 0.003760437 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 111.930 42.160 +*I BUFT_P_101:A I *L 0.001767 *C 14.260 93.840 +*N chanx_right_in[15]:2 *C 14.260 93.840 +*N chanx_right_in[15]:3 *C 14.260 93.795 +*N chanx_right_in[15]:4 *C 14.260 40.178 +*N chanx_right_in[15]:5 *C 14.268 40.120 +*N chanx_right_in[15]:6 *C 64.095 40.120 +*N chanx_right_in[15]:7 *C 101.653 40.120 +*N chanx_right_in[15]:8 *C 101.660 40.178 +*N chanx_right_in[15]:9 *C 101.660 42.102 +*N chanx_right_in[15]:10 *C 101.668 42.160 + +*CAP +0 chanx_right_in[15] 0.000629072 +1 BUFT_P_101:A 1e-06 +2 chanx_right_in[15]:2 3.46743e-05 +3 chanx_right_in[15]:3 0.002377521 +4 chanx_right_in[15]:4 0.002377521 +5 chanx_right_in[15]:5 0.002112069 +6 chanx_right_in[15]:6 0.003168275 +7 chanx_right_in[15]:7 0.001056205 +8 chanx_right_in[15]:8 0.0001168951 +9 chanx_right_in[15]:9 0.0001168951 +10 chanx_right_in[15]:10 0.000629072 +11 chanx_right_in[15]:5 chany_top_in[15]:14 0.0002359105 +12 chanx_right_in[15]:8 chany_top_in[15]:9 2.233954e-06 +13 chanx_right_in[15]:7 chany_top_in[15]:13 0.0005804251 +14 chanx_right_in[15]:9 chany_top_in[15]:8 2.233954e-06 +15 chanx_right_in[15]:6 chany_top_in[15]:13 0.0002359105 +16 chanx_right_in[15]:6 chany_top_in[15]:14 0.0005804251 +17 chanx_right_in[15]:5 chanx_right_in[11]:6 0.0003891844 +18 chanx_right_in[15]:7 chanx_right_in[11]:7 0.0006724644 +19 chanx_right_in[15]:6 chanx_right_in[11]:6 0.0006724644 +20 chanx_right_in[15]:6 chanx_right_in[11]:7 0.0003891844 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:10 0.001607792 +1 chanx_right_in[15]:2 BUFT_P_101:A 0.152 +2 chanx_right_in[15]:3 chanx_right_in[15]:2 0.0045 +3 chanx_right_in[15]:4 chanx_right_in[15]:3 0.04787277 +4 chanx_right_in[15]:5 chanx_right_in[15]:4 0.00341 +5 chanx_right_in[15]:8 chanx_right_in[15]:7 0.00341 +6 chanx_right_in[15]:7 chanx_right_in[15]:6 0.005884008 +7 chanx_right_in[15]:9 chanx_right_in[15]:8 0.00171875 +8 chanx_right_in[15]:10 chanx_right_in[15]:9 0.00341 +9 chanx_right_in[15]:6 chanx_right_in[15]:5 0.007806308 + +*END + +*D_NET chanx_right_in[16] 0.01667138 //LENGTH 152.140 LUMPCC 0.0006344438 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 111.930 4.080 +*I BUFT_RR_82:A I *L 0.001766 *C 60.260 96.560 +*N chanx_right_in[16]:2 *C 60.223 96.560 +*N chanx_right_in[16]:3 *C 57.998 96.560 +*N chanx_right_in[16]:4 *C 57.960 96.220 +*N chanx_right_in[16]:5 *C 57.960 96.175 +*N chanx_right_in[16]:6 *C 57.960 93.898 +*N chanx_right_in[16]:7 *C 57.968 93.840 +*N chanx_right_in[16]:8 *C 75.420 93.840 +*N chanx_right_in[16]:9 *C 75.440 93.833 +*N chanx_right_in[16]:10 *C 75.440 81.115 +*N chanx_right_in[16]:11 *C 75.440 31.288 +*N chanx_right_in[16]:12 *C 75.460 31.280 +*N chanx_right_in[16]:13 *C 77.273 31.280 +*N chanx_right_in[16]:14 *C 77.280 31.223 +*N chanx_right_in[16]:15 *C 77.280 28.590 +*N chanx_right_in[16]:16 *C 77.325 28.560 +*N chanx_right_in[16]:17 *C 79.580 28.560 +*N chanx_right_in[16]:18 *C 79.580 28.220 +*N chanx_right_in[16]:19 *C 81.835 28.220 +*N chanx_right_in[16]:20 *C 81.880 28.175 +*N chanx_right_in[16]:21 *C 81.880 4.138 +*N chanx_right_in[16]:22 *C 81.888 4.080 + +*CAP +0 chanx_right_in[16] 0.0014013 +1 BUFT_RR_82:A 1e-06 +2 chanx_right_in[16]:2 0.0001473986 +3 chanx_right_in[16]:3 0.0001851083 +4 chanx_right_in[16]:4 7.216539e-05 +5 chanx_right_in[16]:5 0.0001593678 +6 chanx_right_in[16]:6 0.0001593678 +7 chanx_right_in[16]:7 0.001224786 +8 chanx_right_in[16]:8 0.001224786 +9 chanx_right_in[16]:9 0.0006235809 +10 chanx_right_in[16]:10 0.003308404 +11 chanx_right_in[16]:11 0.002684823 +12 chanx_right_in[16]:12 0.0001205151 +13 chanx_right_in[16]:13 0.0001205151 +14 chanx_right_in[16]:14 0.0001625804 +15 chanx_right_in[16]:15 0.0001625804 +16 chanx_right_in[16]:16 0.0001919148 +17 chanx_right_in[16]:17 0.000213676 +18 chanx_right_in[16]:18 0.0001730546 +19 chanx_right_in[16]:19 0.0001512934 +20 chanx_right_in[16]:20 0.001073708 +21 chanx_right_in[16]:21 0.001073708 +22 chanx_right_in[16]:22 0.0014013 +23 chanx_right_in[16]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 3.031662e-05 +24 chanx_right_in[16]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002869053 +25 chanx_right_in[16]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0002869053 +26 chanx_right_in[16]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 3.031662e-05 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:22 0.004706658 +1 chanx_right_in[16]:2 BUFT_RR_82:A 0.152 +2 chanx_right_in[16]:4 chanx_right_in[16]:3 0.0001465517 +3 chanx_right_in[16]:5 chanx_right_in[16]:4 0.0045 +4 chanx_right_in[16]:6 chanx_right_in[16]:5 0.002033482 +5 chanx_right_in[16]:7 chanx_right_in[16]:6 0.00341 +6 chanx_right_in[16]:8 chanx_right_in[16]:7 0.002734225 +7 chanx_right_in[16]:9 chanx_right_in[16]:8 0.00341 +8 chanx_right_in[16]:12 chanx_right_in[16]:11 0.00341 +9 chanx_right_in[16]:11 chanx_right_in[16]:10 0.007806308 +10 chanx_right_in[16]:14 chanx_right_in[16]:13 0.00341 +11 chanx_right_in[16]:13 chanx_right_in[16]:12 0.0002839583 +12 chanx_right_in[16]:16 chanx_right_in[16]:15 0.0045 +13 chanx_right_in[16]:15 chanx_right_in[16]:14 0.002350446 +14 chanx_right_in[16]:19 chanx_right_in[16]:18 0.002013393 +15 chanx_right_in[16]:20 chanx_right_in[16]:19 0.0045 +16 chanx_right_in[16]:21 chanx_right_in[16]:20 0.02146205 +17 chanx_right_in[16]:22 chanx_right_in[16]:21 0.00341 +18 chanx_right_in[16]:3 chanx_right_in[16]:2 0.001986607 +19 chanx_right_in[16]:17 chanx_right_in[16]:16 0.002013393 +20 chanx_right_in[16]:18 chanx_right_in[16]:17 0.0003035715 +21 chanx_right_in[16]:10 chanx_right_in[16]:9 0.001992408 + +*END + +*D_NET prog_clk[0] 0.05550917 //LENGTH 420.380 LUMPCC 0.007126718 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 14.720 102.035 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 51.325 80.240 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 49.025 74.800 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 50.865 66.640 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 57.305 53.040 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.045 53.040 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.405 50.320 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.565 47.600 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 81.225 36.720 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 72.025 36.720 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 80.305 47.600 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 82.605 50.320 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 54.545 47.600 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.605 44.880 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.525 39.440 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 54.545 61.200 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 50.405 58.480 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 49.945 93.840 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 61.075 91.120 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 63.285 85.680 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 64.665 77.520 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.405 74.800 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.865 63.920 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 74.760 66.640 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 81.615 61.200 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 85.820 66.640 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 93.600 58.480 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 92.265 53.040 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 91.805 47.600 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 94.565 66.640 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 64.205 61.200 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 64.665 99.280 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.405 99.280 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 36.515 93.840 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 34.305 85.680 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 39.365 72.080 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.985 69.360 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 34.305 61.200 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 36.605 53.040 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 44.425 47.600 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.005 77.520 +*N prog_clk[0]:41 *C 32.005 77.520 +*N prog_clk[0]:42 *C 32.200 77.520 +*N prog_clk[0]:43 *C 44.388 47.600 +*N prog_clk[0]:44 *C 43.745 47.600 +*N prog_clk[0]:45 *C 43.700 47.600 +*N prog_clk[0]:46 *C 43.693 47.600 +*N prog_clk[0]:47 *C 35.428 47.600 +*N prog_clk[0]:48 *C 35.420 47.657 +*N prog_clk[0]:49 *C 36.605 53.040 +*N prog_clk[0]:50 *C 36.800 53.380 +*N prog_clk[0]:51 *C 35.465 53.380 +*N prog_clk[0]:52 *C 35.420 53.380 +*N prog_clk[0]:53 *C 35.420 55.023 +*N prog_clk[0]:54 *C 35.413 55.080 +*N prog_clk[0]:55 *C 34.508 55.080 +*N prog_clk[0]:56 *C 34.500 55.138 +*N prog_clk[0]:57 *C 34.305 61.200 +*N prog_clk[0]:58 *C 34.500 60.860 +*N prog_clk[0]:59 *C 34.500 60.860 +*N prog_clk[0]:60 *C 37.948 69.360 +*N prog_clk[0]:61 *C 36.385 69.360 +*N prog_clk[0]:62 *C 36.340 69.360 +*N prog_clk[0]:63 *C 36.333 69.360 +*N prog_clk[0]:64 *C 34.508 69.360 +*N prog_clk[0]:65 *C 34.500 69.360 +*N prog_clk[0]:66 *C 39.365 72.080 +*N prog_clk[0]:67 *C 39.100 72.080 +*N prog_clk[0]:68 *C 39.100 72.080 +*N prog_clk[0]:69 *C 39.093 72.080 +*N prog_clk[0]:70 *C 34.508 72.080 +*N prog_clk[0]:71 *C 34.500 72.080 +*N prog_clk[0]:72 *C 34.500 77.463 +*N prog_clk[0]:73 *C 34.492 77.520 +*N prog_clk[0]:74 *C 32.208 77.520 +*N prog_clk[0]:75 *C 32.200 77.520 +*N prog_clk[0]:76 *C 32.200 85.680 +*N prog_clk[0]:77 *C 34.267 85.680 +*N prog_clk[0]:78 *C 33.625 85.680 +*N prog_clk[0]:79 *C 33.580 85.680 +*N prog_clk[0]:80 *C 33.573 85.680 +*N prog_clk[0]:81 *C 32.668 85.680 +*N prog_clk[0]:82 *C 32.660 85.737 +*N prog_clk[0]:83 *C 36.477 93.840 +*N prog_clk[0]:84 *C 32.705 93.840 +*N prog_clk[0]:85 *C 32.660 93.840 +*N prog_clk[0]:86 *C 73.368 99.280 +*N prog_clk[0]:87 *C 71.805 99.280 +*N prog_clk[0]:88 *C 71.760 99.280 +*N prog_clk[0]:89 *C 71.752 99.280 +*N prog_clk[0]:90 *C 64.665 99.280 +*N prog_clk[0]:91 *C 64.400 99.280 +*N prog_clk[0]:92 *C 64.400 99.280 +*N prog_clk[0]:93 *C 64.400 99.280 +*N prog_clk[0]:94 *C 62.100 99.280 +*N prog_clk[0]:95 *C 64.205 61.200 +*N prog_clk[0]:96 *C 64.400 61.200 +*N prog_clk[0]:97 *C 64.400 61.245 +*N prog_clk[0]:98 *C 94.565 66.640 +*N prog_clk[0]:99 *C 94.300 66.640 +*N prog_clk[0]:100 *C 94.300 66.595 +*N prog_clk[0]:101 *C 94.300 66.017 +*N prog_clk[0]:102 *C 94.293 65.960 +*N prog_clk[0]:103 *C 91.600 58.480 +*N prog_clk[0]:104 *C 91.805 47.600 +*N prog_clk[0]:105 *C 92.000 47.600 +*N prog_clk[0]:106 *C 92.000 47.645 +*N prog_clk[0]:107 *C 92.265 53.040 +*N prog_clk[0]:108 *C 92.000 53.380 +*N prog_clk[0]:109 *C 92.000 53.380 +*N prog_clk[0]:110 *C 93.562 58.480 +*N prog_clk[0]:111 *C 92.045 58.480 +*N prog_clk[0]:112 *C 92.000 58.480 +*N prog_clk[0]:113 *C 92.000 58.480 +*N prog_clk[0]:114 *C 92.000 58.488 +*N prog_clk[0]:115 *C 92.000 65.953 +*N prog_clk[0]:116 *C 92.000 65.960 +*N prog_clk[0]:117 *C 85.782 66.640 +*N prog_clk[0]:118 *C 85.145 66.640 +*N prog_clk[0]:119 *C 85.100 66.595 +*N prog_clk[0]:120 *C 85.100 66.017 +*N prog_clk[0]:121 *C 85.100 65.960 +*N prog_clk[0]:122 *C 81.880 65.960 +*N prog_clk[0]:123 *C 81.880 65.285 +*N prog_clk[0]:124 *C 81.725 65.288 +*N prog_clk[0]:125 *C 81.615 61.200 +*N prog_clk[0]:126 *C 81.420 61.200 +*N prog_clk[0]:127 *C 81.420 61.245 +*N prog_clk[0]:128 *C 81.420 65.222 +*N prog_clk[0]:129 *C 81.502 65.295 +*N prog_clk[0]:130 *C 74.760 66.640 +*N prog_clk[0]:131 *C 74.520 66.640 +*N prog_clk[0]:132 *C 74.520 66.595 +*N prog_clk[0]:133 *C 74.520 65.280 +*N prog_clk[0]:134 *C 73.865 63.920 +*N prog_clk[0]:135 *C 74.060 63.920 +*N prog_clk[0]:136 *C 74.060 63.965 +*N prog_clk[0]:137 *C 74.060 65.280 +*N prog_clk[0]:138 *C 74.060 65.280 +*N prog_clk[0]:139 *C 64.407 65.280 +*N prog_clk[0]:140 *C 64.400 65.280 +*N prog_clk[0]:141 *C 73.368 74.800 +*N prog_clk[0]:142 *C 71.805 74.800 +*N prog_clk[0]:143 *C 71.760 74.800 +*N prog_clk[0]:144 *C 71.752 74.800 +*N prog_clk[0]:145 *C 64.407 74.800 +*N prog_clk[0]:146 *C 64.400 74.800 +*N prog_clk[0]:147 *C 64.665 77.520 +*N prog_clk[0]:148 *C 64.400 77.180 +*N prog_clk[0]:149 *C 64.400 77.180 +*N prog_clk[0]:150 *C 64.400 85.680 +*N prog_clk[0]:151 *C 63.285 85.680 +*N prog_clk[0]:152 *C 63.480 86.020 +*N prog_clk[0]:153 *C 63.895 86.020 +*N prog_clk[0]:154 *C 63.940 86.020 +*N prog_clk[0]:155 *C 63.940 85.680 +*N prog_clk[0]:156 *C 63.933 85.680 +*N prog_clk[0]:157 *C 62.108 85.680 +*N prog_clk[0]:158 *C 62.100 85.737 +*N prog_clk[0]:159 *C 61.075 91.120 +*N prog_clk[0]:160 *C 61.180 91.120 +*N prog_clk[0]:161 *C 62.100 91.120 +*N prog_clk[0]:162 *C 62.100 98.543 +*N prog_clk[0]:163 *C 62.100 98.608 +*N prog_clk[0]:164 *C 48.760 98.600 +*N prog_clk[0]:165 *C 49.907 93.840 +*N prog_clk[0]:166 *C 49.265 93.840 +*N prog_clk[0]:167 *C 49.220 93.840 +*N prog_clk[0]:168 *C 50.405 58.480 +*N prog_clk[0]:169 *C 50.600 58.480 +*N prog_clk[0]:170 *C 50.600 58.525 +*N prog_clk[0]:171 *C 50.600 59.840 +*N prog_clk[0]:172 *C 54.545 61.200 +*N prog_clk[0]:173 *C 54.740 61.200 +*N prog_clk[0]:174 *C 54.740 61.155 +*N prog_clk[0]:175 *C 60.525 39.440 +*N prog_clk[0]:176 *C 60.260 39.440 +*N prog_clk[0]:177 *C 60.260 39.485 +*N prog_clk[0]:178 *C 60.260 44.880 +*N prog_clk[0]:179 *C 59.605 44.880 +*N prog_clk[0]:180 *C 59.340 44.880 +*N prog_clk[0]:181 *C 59.340 44.880 +*N prog_clk[0]:182 *C 59.333 44.880 +*N prog_clk[0]:183 *C 55.668 44.880 +*N prog_clk[0]:184 *C 55.660 44.938 +*N prog_clk[0]:185 *C 55.660 47.940 +*N prog_clk[0]:186 *C 54.545 47.600 +*N prog_clk[0]:187 *C 54.740 47.940 +*N prog_clk[0]:188 *C 55.155 47.940 +*N prog_clk[0]:189 *C 55.200 47.940 +*N prog_clk[0]:190 *C 82.568 50.320 +*N prog_clk[0]:191 *C 81.925 50.320 +*N prog_clk[0]:192 *C 81.880 50.320 +*N prog_clk[0]:193 *C 81.873 50.320 +*N prog_clk[0]:194 *C 80.305 47.600 +*N prog_clk[0]:195 *C 80.040 47.600 +*N prog_clk[0]:196 *C 80.040 47.645 +*N prog_clk[0]:197 *C 80.040 50.263 +*N prog_clk[0]:198 *C 80.040 50.320 +*N prog_clk[0]:199 *C 73.608 50.320 +*N prog_clk[0]:200 *C 72.025 36.720 +*N prog_clk[0]:201 *C 72.220 36.720 +*N prog_clk[0]:202 *C 81.188 36.720 +*N prog_clk[0]:203 *C 80.085 36.720 +*N prog_clk[0]:204 *C 80.040 36.720 +*N prog_clk[0]:205 *C 80.032 36.720 +*N prog_clk[0]:206 *C 72.228 36.720 +*N prog_clk[0]:207 *C 72.220 36.720 +*N prog_clk[0]:208 *C 71.565 47.600 +*N prog_clk[0]:209 *C 71.760 47.940 +*N prog_clk[0]:210 *C 72.175 47.940 +*N prog_clk[0]:211 *C 72.220 47.940 +*N prog_clk[0]:212 *C 72.220 50.275 +*N prog_clk[0]:213 *C 72.265 50.320 +*N prog_clk[0]:214 *C 73.368 50.320 +*N prog_clk[0]:215 *C 73.458 50.320 +*N prog_clk[0]:216 *C 73.600 50.320 +*N prog_clk[0]:217 *C 73.600 52.983 +*N prog_clk[0]:218 *C 73.593 53.040 +*N prog_clk[0]:219 *C 66.045 53.040 +*N prog_clk[0]:220 *C 66.240 53.040 +*N prog_clk[0]:221 *C 66.240 53.040 +*N prog_clk[0]:222 *C 66.240 53.040 +*N prog_clk[0]:223 *C 57.305 53.040 +*N prog_clk[0]:224 *C 57.500 53.040 +*N prog_clk[0]:225 *C 57.500 53.040 +*N prog_clk[0]:226 *C 57.500 53.040 +*N prog_clk[0]:227 *C 55.208 53.040 +*N prog_clk[0]:228 *C 55.200 52.983 +*N prog_clk[0]:229 *C 54.740 53.040 +*N prog_clk[0]:230 *C 54.740 59.840 +*N prog_clk[0]:231 *C 54.733 59.840 +*N prog_clk[0]:232 *C 51.068 59.840 +*N prog_clk[0]:233 *C 51.060 59.898 +*N prog_clk[0]:234 *C 50.865 66.640 +*N prog_clk[0]:235 *C 51.060 66.300 +*N prog_clk[0]:236 *C 51.060 66.300 +*N prog_clk[0]:237 *C 51.060 75.140 +*N prog_clk[0]:238 *C 49.025 74.800 +*N prog_clk[0]:239 *C 49.220 75.140 +*N prog_clk[0]:240 *C 49.220 75.140 +*N prog_clk[0]:241 *C 51.288 80.240 +*N prog_clk[0]:242 *C 49.265 80.240 +*N prog_clk[0]:243 *C 49.220 80.195 +*N prog_clk[0]:244 *C 48.760 80.240 +*N prog_clk[0]:245 *C 48.760 93.840 +*N prog_clk[0]:246 *C 48.760 97.863 +*N prog_clk[0]:247 *C 48.760 97.928 +*N prog_clk[0]:248 *C 32.668 97.920 +*N prog_clk[0]:249 *C 32.660 97.920 +*N prog_clk[0]:250 *C 32.660 101.263 +*N prog_clk[0]:251 *C 32.660 101.328 +*N prog_clk[0]:252 *C 32.660 102.000 +*N prog_clk[0]:253 *C 22.080 102.000 +*N prog_clk[0]:254 *C 22.080 101.320 +*N prog_clk[0]:255 *C 14.728 101.320 +*N prog_clk[0]:256 *C 14.720 101.378 + +*CAP +0 prog_clk[0] 4.744524e-05 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +3 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +6 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +7 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +8 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +9 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +10 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +12 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +13 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +14 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +15 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +16 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +18 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +19 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +20 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +21 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +22 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +23 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +24 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +25 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +26 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +27 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +28 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +29 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +30 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +32 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +33 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +35 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +37 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +39 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +40 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +41 prog_clk[0]:41 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prog_clk[0]:129 right_top_grid_pin_45_[0]:24 8.197381e-07 +326 prog_clk[0]:132 right_top_grid_pin_45_[0]:24 5.261229e-06 +327 prog_clk[0]:133 right_top_grid_pin_45_[0]:9 5.261229e-06 +328 prog_clk[0]:124 right_top_grid_pin_45_[0]:25 8.197381e-07 +329 prog_clk[0]:124 right_top_grid_pin_45_[0]:24 8.197381e-07 +330 prog_clk[0]:123 right_top_grid_pin_45_[0]:25 8.197381e-07 +331 prog_clk[0]:122 right_top_grid_pin_45_[0]:24 7.373455e-05 +332 prog_clk[0]:72 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 1.19827e-05 +333 prog_clk[0]:71 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 1.19827e-05 +334 prog_clk[0]:71 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 5.044994e-06 +335 prog_clk[0]:65 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 5.044994e-06 +336 prog_clk[0]:61 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 5.547253e-05 +337 prog_clk[0]:60 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 5.547253e-05 +338 prog_clk[0]:233 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.50914e-05 +339 prog_clk[0]:236 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.012982e-05 +340 prog_clk[0]:236 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.50914e-05 +341 prog_clk[0]:170 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.111912e-05 +342 prog_clk[0]:237 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.012982e-05 +343 prog_clk[0]:171 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.111912e-05 +344 prog_clk[0]:182 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.979173e-05 +345 prog_clk[0]:184 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.941043e-07 +346 prog_clk[0]:183 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.979173e-05 +347 prog_clk[0]:228 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 1.588576e-05 +348 prog_clk[0]:189 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 1.588576e-05 +349 prog_clk[0]:109 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.575396e-06 +350 prog_clk[0]:106 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.575396e-06 +351 prog_clk[0]:193 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.387164e-05 +352 prog_clk[0]:198 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.387164e-05 +353 prog_clk[0]:198 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.109609e-05 +354 prog_clk[0]:199 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.109609e-05 +355 prog_clk[0]:185 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.941043e-07 +356 prog_clk[0]:121 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000105602 +357 prog_clk[0]:121 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.415316e-05 +358 prog_clk[0]:138 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001565351 +359 prog_clk[0]:138 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001509694 +360 prog_clk[0]:116 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.544477e-05 +361 prog_clk[0]:116 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000105602 +362 prog_clk[0]:102 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.544477e-05 +363 prog_clk[0]:97 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.389054e-06 +364 prog_clk[0]:140 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.389054e-06 +365 prog_clk[0]:140 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 6.697077e-06 +366 prog_clk[0]:139 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001509694 +367 prog_clk[0]:129 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.673305e-06 +368 prog_clk[0]:129 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001565351 +369 prog_clk[0]:146 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.697077e-06 +370 prog_clk[0]:124 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.673305e-06 +371 prog_clk[0]:124 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.673305e-06 +372 prog_clk[0]:123 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.673305e-06 +373 prog_clk[0]:122 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.415316e-05 +374 prog_clk[0]:244 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001656879 +375 prog_clk[0]:245 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001656879 +376 prog_clk[0]:248 ropt_net_139:10 6.457598e-05 +377 prog_clk[0]:163 ropt_net_139:11 1.228204e-06 +378 prog_clk[0]:246 ropt_net_139:12 4.319672e-05 +379 prog_clk[0]:247 ropt_net_139:11 6.457598e-05 +380 prog_clk[0]:166 ropt_net_139:14 6.781413e-08 +381 prog_clk[0]:165 ropt_net_139:15 6.781413e-08 +382 prog_clk[0]:245 ropt_net_139:13 4.319672e-05 +383 prog_clk[0]:164 ropt_net_139:10 1.228204e-06 + +*RES +0 prog_clk[0] prog_clk[0]:256 0.0005870535 +1 prog_clk[0]:117 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +2 prog_clk[0]:118 prog_clk[0]:117 0.0005691964 +3 prog_clk[0]:119 prog_clk[0]:118 0.0045 +4 prog_clk[0]:120 prog_clk[0]:119 0.000515625 +5 prog_clk[0]:121 prog_clk[0]:120 0.00341 +6 prog_clk[0]:121 prog_clk[0]:116 0.001081 +7 prog_clk[0]:56 prog_clk[0]:55 0.00341 +8 prog_clk[0]:55 prog_clk[0]:54 0.0001417833 +9 prog_clk[0]:53 prog_clk[0]:52 0.001466518 +10 prog_clk[0]:54 prog_clk[0]:53 0.00341 +11 prog_clk[0]:181 prog_clk[0]:180 0.0045 +12 prog_clk[0]:181 prog_clk[0]:178 0.0008214285 +13 prog_clk[0]:182 prog_clk[0]:181 0.00341 +14 prog_clk[0]:184 prog_clk[0]:183 0.00341 +15 prog_clk[0]:183 prog_clk[0]:182 0.0005741833 +16 prog_clk[0]:215 prog_clk[0]:214 8.035715e-05 +17 prog_clk[0]:216 prog_clk[0]:215 0.0045 +18 prog_clk[0]:216 prog_clk[0]:199 0.00341 +19 prog_clk[0]:233 prog_clk[0]:232 0.00341 +20 prog_clk[0]:233 prog_clk[0]:171 0.0004107143 +21 prog_clk[0]:232 prog_clk[0]:231 0.0005741833 +22 prog_clk[0]:230 prog_clk[0]:229 0.006071429 +23 prog_clk[0]:230 prog_clk[0]:174 0.001174107 +24 prog_clk[0]:231 prog_clk[0]:230 0.00341 +25 prog_clk[0]:83 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +26 prog_clk[0]:84 prog_clk[0]:83 0.003368304 +27 prog_clk[0]:85 prog_clk[0]:84 0.0045 +28 prog_clk[0]:85 prog_clk[0]:82 0.007234375 +29 prog_clk[0]:137 prog_clk[0]:136 0.001174107 +30 prog_clk[0]:137 prog_clk[0]:133 0.0004107143 +31 prog_clk[0]:138 prog_clk[0]:137 0.00341 +32 prog_clk[0]:138 prog_clk[0]:129 0.001165992 +33 prog_clk[0]:112 prog_clk[0]:111 0.0045 +34 prog_clk[0]:112 prog_clk[0]:109 0.004553572 +35 prog_clk[0]:113 prog_clk[0]:112 0.00341 +36 prog_clk[0]:113 prog_clk[0]:103 5.69697e-05 +37 prog_clk[0]:114 prog_clk[0]:113 0.00341 +38 prog_clk[0]:116 prog_clk[0]:115 0.00341 +39 prog_clk[0]:116 prog_clk[0]:102 0.0003591583 +40 prog_clk[0]:115 prog_clk[0]:114 0.001169517 +41 prog_clk[0]:135 prog_clk[0]:134 0.0001059783 +42 prog_clk[0]:136 prog_clk[0]:135 0.0045 +43 prog_clk[0]:134 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +44 prog_clk[0]:75 prog_clk[0]:74 0.00341 +45 prog_clk[0]:75 prog_clk[0]:42 0.0045 +46 prog_clk[0]:74 prog_clk[0]:73 0.0003579833 +47 prog_clk[0]:72 prog_clk[0]:71 0.004805804 +48 prog_clk[0]:73 prog_clk[0]:72 0.00341 +49 prog_clk[0]:71 prog_clk[0]:70 0.00341 +50 prog_clk[0]:71 prog_clk[0]:65 0.002428571 +51 prog_clk[0]:70 prog_clk[0]:69 0.0007183166 +52 prog_clk[0]:68 prog_clk[0]:67 0.0045 +53 prog_clk[0]:69 prog_clk[0]:68 0.00341 +54 prog_clk[0]:67 prog_clk[0]:66 0.0001440218 +55 prog_clk[0]:66 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +56 prog_clk[0]:207 prog_clk[0]:206 0.00341 +57 prog_clk[0]:207 prog_clk[0]:201 0.0045 +58 prog_clk[0]:206 prog_clk[0]:205 0.001222783 +59 prog_clk[0]:204 prog_clk[0]:203 0.0045 +60 prog_clk[0]:205 prog_clk[0]:204 0.00341 +61 prog_clk[0]:203 prog_clk[0]:202 0.0009843751 +62 prog_clk[0]:202 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +63 prog_clk[0]:249 prog_clk[0]:248 0.00341 +64 prog_clk[0]:249 prog_clk[0]:85 0.003642857 +65 prog_clk[0]:248 prog_clk[0]:247 0.002521158 +66 prog_clk[0]:213 prog_clk[0]:212 0.0045 +67 prog_clk[0]:212 prog_clk[0]:211 0.002084821 +68 prog_clk[0]:98 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +69 prog_clk[0]:99 prog_clk[0]:98 0.0001440218 +70 prog_clk[0]:100 prog_clk[0]:99 0.0045 +71 prog_clk[0]:101 prog_clk[0]:100 0.000515625 +72 prog_clk[0]:102 prog_clk[0]:101 0.00341 +73 prog_clk[0]:217 prog_clk[0]:216 0.002377232 +74 prog_clk[0]:218 prog_clk[0]:217 0.00341 +75 prog_clk[0]:228 prog_clk[0]:227 0.00341 +76 prog_clk[0]:228 prog_clk[0]:189 0.004502233 +77 prog_clk[0]:227 prog_clk[0]:226 0.0003591583 +78 prog_clk[0]:155 prog_clk[0]:154 0.0001634615 +79 prog_clk[0]:155 prog_clk[0]:150 0.0004107143 +80 prog_clk[0]:156 prog_clk[0]:155 0.00341 +81 prog_clk[0]:158 prog_clk[0]:157 0.00341 +82 prog_clk[0]:157 prog_clk[0]:156 0.0002859166 +83 prog_clk[0]:162 prog_clk[0]:161 0.006627233 +84 prog_clk[0]:163 prog_clk[0]:162 0.00341 +85 prog_clk[0]:163 prog_clk[0]:94 0.0001053583 +86 prog_clk[0]:246 prog_clk[0]:245 0.003591518 +87 prog_clk[0]:247 prog_clk[0]:246 0.00341 +88 prog_clk[0]:247 prog_clk[0]:164 0.0001053583 +89 prog_clk[0]:96 prog_clk[0]:95 0.0001059783 +90 prog_clk[0]:97 prog_clk[0]:96 0.0045 +91 prog_clk[0]:95 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +92 prog_clk[0]:58 prog_clk[0]:57 0.0001847826 +93 prog_clk[0]:59 prog_clk[0]:58 0.0045 +94 prog_clk[0]:59 prog_clk[0]:56 0.005109375 +95 prog_clk[0]:57 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +96 prog_clk[0]:140 prog_clk[0]:139 0.00341 +97 prog_clk[0]:140 prog_clk[0]:97 0.003602678 +98 prog_clk[0]:139 prog_clk[0]:138 0.001512225 +99 prog_clk[0]:128 prog_clk[0]:127 0.00355134 +100 prog_clk[0]:129 prog_clk[0]:128 0.00341 +101 prog_clk[0]:129 prog_clk[0]:124 3.485833e-05 +102 prog_clk[0]:126 prog_clk[0]:125 0.0001059783 +103 prog_clk[0]:127 prog_clk[0]:126 0.0045 +104 prog_clk[0]:125 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +105 prog_clk[0]:51 prog_clk[0]:50 0.001191964 +106 prog_clk[0]:52 prog_clk[0]:51 0.0045 +107 prog_clk[0]:52 prog_clk[0]:48 0.005109375 +108 prog_clk[0]:49 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +109 prog_clk[0]:166 prog_clk[0]:165 0.0005736608 +110 prog_clk[0]:167 prog_clk[0]:166 0.0045 +111 prog_clk[0]:165 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +112 prog_clk[0]:235 prog_clk[0]:234 0.0001847826 +113 prog_clk[0]:236 prog_clk[0]:235 0.0045 +114 prog_clk[0]:236 prog_clk[0]:233 0.005716518 +115 prog_clk[0]:234 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +116 prog_clk[0]:131 prog_clk[0]:130 0.0001304348 +117 prog_clk[0]:132 prog_clk[0]:131 0.0045 +118 prog_clk[0]:130 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +119 prog_clk[0]:48 prog_clk[0]:47 0.00341 +120 prog_clk[0]:47 prog_clk[0]:46 0.00129485 +121 prog_clk[0]:45 prog_clk[0]:44 0.0045 +122 prog_clk[0]:46 prog_clk[0]:45 0.00341 +123 prog_clk[0]:44 prog_clk[0]:43 0.0005736608 +124 prog_clk[0]:43 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +125 prog_clk[0]:173 prog_clk[0]:172 0.0001059783 +126 prog_clk[0]:174 prog_clk[0]:173 0.0045 +127 prog_clk[0]:172 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +128 prog_clk[0]:242 prog_clk[0]:241 0.001805804 +129 prog_clk[0]:243 prog_clk[0]:242 0.0045 +130 prog_clk[0]:243 prog_clk[0]:240 0.004513393 +131 prog_clk[0]:241 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +132 prog_clk[0]:188 prog_clk[0]:187 0.0003705357 +133 prog_clk[0]:189 prog_clk[0]:188 0.0045 +134 prog_clk[0]:189 prog_clk[0]:185 0.0004107143 +135 prog_clk[0]:186 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +136 prog_clk[0]:180 prog_clk[0]:179 0.0001440218 +137 prog_clk[0]:179 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +138 prog_clk[0]:239 prog_clk[0]:238 0.0001847826 +139 prog_clk[0]:240 prog_clk[0]:239 0.0045 +140 prog_clk[0]:240 prog_clk[0]:237 0.001642857 +141 prog_clk[0]:238 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +142 prog_clk[0]:176 prog_clk[0]:175 0.0001440218 +143 prog_clk[0]:177 prog_clk[0]:176 0.0045 +144 prog_clk[0]:175 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +145 prog_clk[0]:111 prog_clk[0]:110 0.001354911 +146 prog_clk[0]:110 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +147 prog_clk[0]:201 prog_clk[0]:200 0.0001059783 +148 prog_clk[0]:200 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +149 prog_clk[0]:108 prog_clk[0]:107 0.0001847826 +150 prog_clk[0]:109 prog_clk[0]:108 0.0045 +151 prog_clk[0]:109 prog_clk[0]:106 0.005120536 +152 prog_clk[0]:107 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +153 prog_clk[0]:65 prog_clk[0]:64 0.00341 +154 prog_clk[0]:65 prog_clk[0]:59 0.007589286 +155 prog_clk[0]:64 prog_clk[0]:63 0.0002859166 +156 prog_clk[0]:62 prog_clk[0]:61 0.0045 +157 prog_clk[0]:63 prog_clk[0]:62 0.00341 +158 prog_clk[0]:61 prog_clk[0]:60 0.001395089 +159 prog_clk[0]:60 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +160 prog_clk[0]:105 prog_clk[0]:104 0.0001059783 +161 prog_clk[0]:106 prog_clk[0]:105 0.0045 +162 prog_clk[0]:104 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +163 prog_clk[0]:192 prog_clk[0]:191 0.0045 +164 prog_clk[0]:193 prog_clk[0]:192 0.00341 +165 prog_clk[0]:191 prog_clk[0]:190 0.0005736608 +166 prog_clk[0]:190 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +167 prog_clk[0]:92 prog_clk[0]:91 0.0045 +168 prog_clk[0]:93 prog_clk[0]:92 0.00341 +169 prog_clk[0]:93 prog_clk[0]:89 0.001151892 +170 prog_clk[0]:91 prog_clk[0]:90 0.0001440218 +171 prog_clk[0]:90 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +172 prog_clk[0]:197 prog_clk[0]:196 0.002337054 +173 prog_clk[0]:198 prog_clk[0]:197 0.00341 +174 prog_clk[0]:198 prog_clk[0]:193 0.0002870917 +175 prog_clk[0]:195 prog_clk[0]:194 0.0001440217 +176 prog_clk[0]:196 prog_clk[0]:195 0.0045 +177 prog_clk[0]:194 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +178 prog_clk[0]:88 prog_clk[0]:87 0.0045 +179 prog_clk[0]:89 prog_clk[0]:88 0.00341 +180 prog_clk[0]:87 prog_clk[0]:86 0.001395089 +181 prog_clk[0]:86 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +182 prog_clk[0]:210 prog_clk[0]:209 0.0003705357 +183 prog_clk[0]:211 prog_clk[0]:210 0.0045 +184 prog_clk[0]:211 prog_clk[0]:207 0.01001786 +185 prog_clk[0]:208 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +186 prog_clk[0]:146 prog_clk[0]:145 0.00341 +187 prog_clk[0]:146 prog_clk[0]:140 0.0085 +188 prog_clk[0]:145 prog_clk[0]:144 0.001150717 +189 prog_clk[0]:143 prog_clk[0]:142 0.0045 +190 prog_clk[0]:144 prog_clk[0]:143 0.00341 +191 prog_clk[0]:142 prog_clk[0]:141 0.00139509 +192 prog_clk[0]:141 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +193 prog_clk[0]:214 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +194 prog_clk[0]:214 prog_clk[0]:213 0.000984375 +195 prog_clk[0]:148 prog_clk[0]:147 0.0001847826 +196 prog_clk[0]:149 prog_clk[0]:148 0.0045 +197 prog_clk[0]:149 prog_clk[0]:146 0.002125 +198 prog_clk[0]:147 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +199 prog_clk[0]:221 prog_clk[0]:220 0.0045 +200 prog_clk[0]:222 prog_clk[0]:221 0.00341 +201 prog_clk[0]:222 prog_clk[0]:218 0.001151892 +202 prog_clk[0]:220 prog_clk[0]:219 0.0001059783 +203 prog_clk[0]:219 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +204 prog_clk[0]:153 prog_clk[0]:152 0.0003705357 +205 prog_clk[0]:154 prog_clk[0]:153 0.0045 +206 prog_clk[0]:151 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +207 prog_clk[0]:225 prog_clk[0]:224 0.0045 +208 prog_clk[0]:226 prog_clk[0]:225 0.00341 +209 prog_clk[0]:226 prog_clk[0]:222 0.001369267 +210 prog_clk[0]:224 prog_clk[0]:223 0.0001059783 +211 prog_clk[0]:223 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +212 prog_clk[0]:159 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +213 prog_clk[0]:160 prog_clk[0]:159 0.0045 +214 prog_clk[0]:169 prog_clk[0]:168 0.0001059783 +215 prog_clk[0]:170 prog_clk[0]:169 0.0045 +216 prog_clk[0]:168 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +217 prog_clk[0]:199 prog_clk[0]:198 0.001007758 +218 prog_clk[0]:42 prog_clk[0]:41 0.0001059783 +219 prog_clk[0]:41 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +220 prog_clk[0]:82 prog_clk[0]:81 0.00341 +221 prog_clk[0]:82 prog_clk[0]:76 0.0004107143 +222 prog_clk[0]:81 prog_clk[0]:80 0.0001417833 +223 prog_clk[0]:79 prog_clk[0]:78 0.0045 +224 prog_clk[0]:80 prog_clk[0]:79 0.00341 +225 prog_clk[0]:78 prog_clk[0]:77 0.0005736608 +226 prog_clk[0]:77 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +227 prog_clk[0]:250 prog_clk[0]:249 0.002984375 +228 prog_clk[0]:251 prog_clk[0]:250 0.00341 +229 prog_clk[0]:256 prog_clk[0]:255 0.00341 +230 prog_clk[0]:255 prog_clk[0]:254 0.001151892 +231 prog_clk[0]:50 prog_clk[0]:49 0.0003035715 +232 prog_clk[0]:187 prog_clk[0]:186 0.0003035715 +233 prog_clk[0]:152 prog_clk[0]:151 0.0003035715 +234 prog_clk[0]:209 prog_clk[0]:208 0.0003035715 +235 prog_clk[0]:76 prog_clk[0]:75 0.007285715 +236 prog_clk[0]:244 prog_clk[0]:243 0.0004107143 +237 prog_clk[0]:245 prog_clk[0]:244 0.01214286 +238 prog_clk[0]:245 prog_clk[0]:167 0.0004107143 +239 prog_clk[0]:237 prog_clk[0]:236 0.007892857 +240 prog_clk[0]:171 prog_clk[0]:170 0.001174107 +241 prog_clk[0]:229 prog_clk[0]:228 0.0004107143 +242 prog_clk[0]:185 prog_clk[0]:184 0.002680804 +243 prog_clk[0]:178 prog_clk[0]:177 0.004816964 +244 prog_clk[0]:161 prog_clk[0]:160 0.0008214285 +245 prog_clk[0]:161 prog_clk[0]:158 0.004805804 +246 prog_clk[0]:150 prog_clk[0]:149 0.007589286 +247 prog_clk[0]:133 prog_clk[0]:132 0.001174107 +248 prog_clk[0]:254 prog_clk[0]:253 0.0001065333 +249 prog_clk[0]:253 prog_clk[0]:252 0.001657533 +250 prog_clk[0]:252 prog_clk[0]:251 0.0001053583 +251 prog_clk[0]:164 prog_clk[0]:163 0.002089933 +252 prog_clk[0]:94 prog_clk[0]:93 0.0003603333 +253 prog_clk[0]:124 prog_clk[0]:123 2.428333e-05 +254 prog_clk[0]:123 prog_clk[0]:122 0.00010575 +255 prog_clk[0]:122 prog_clk[0]:121 0.0005044666 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001176972 //LENGTH 9.000 LUMPCC 0.0002798984 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 36.975 55.760 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 37.260 63.580 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 37.260 63.580 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 37.260 63.535 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 37.260 55.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.800 55.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 36.800 55.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 36.975 55.760 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.071654e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000322044 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003555916 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.530641e-05 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.721994e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.419531e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_3_sram[0]:6 0.0001399492 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_3_sram[0]:7 0.0001399492 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004107143 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.510869e-05 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006941965 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001229266 //LENGTH 10.265 LUMPCC 0.0001520918 DR + +*CONN +*I mux_right_track_14\/mux_l1_in_0_:X O *L 0 *C 72.045 63.240 +*I mux_right_track_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 76.000 58.140 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.963 58.140 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 74.520 58.140 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 74.520 58.820 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.185 58.820 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 73.140 58.865 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 73.140 63.195 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 73.095 63.240 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 72.083 63.240 + +*CAP +0 mux_right_track_14\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_14\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.916875e-05 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001010453 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001289903 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.711383e-05 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002531923 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002531923 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.623558e-05 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 9.623558e-05 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_top_in[7]:3 6.451052e-05 +11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[7]:4 1.05325e-05 +12 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[7]:5 1.002883e-06 +13 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[7]:6 1.002883e-06 +14 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[7]:3 1.05325e-05 +15 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[7]:4 6.451052e-05 + +*RES +0 mux_right_track_14\/mux_l1_in_0_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_14\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001191964 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003866071 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0009040179 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0006071429 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001287946 + +*END + +*D_NET mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001235482 //LENGTH 11.665 LUMPCC 9.835706e-05 DR + +*CONN +*I mux_right_track_22\/mux_l1_in_0_:X O *L 0 *C 96.885 71.740 +*I mux_right_track_22\/mux_l2_in_0_:A1 I *L 0.00198 *C 99.460 63.580 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 99.422 63.580 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 98.945 63.580 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 98.900 63.625 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 98.900 71.695 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 98.855 71.740 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 96.922 71.740 + +*CAP +0 mux_right_track_22\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_22\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.359046e-05 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.359046e-05 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004095631 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004095631 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001344091 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001344091 +8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_10_sram[1]:4 3.18151e-05 +9 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_10_sram[1]:3 3.18151e-05 +10 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_10_sram[1]:7 1.736344e-05 +11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_10_sram[1]:8 1.736344e-05 + +*RES +0 mux_right_track_22\/mux_l1_in_0_:X mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_22\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007205357 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725446 + +*END + +*D_NET optlc_net_115 0.008562888 //LENGTH 66.120 LUMPCC 0.001108795 DR + +*CONN +*I optlc_111:HI O *L 0 *C 85.560 42.500 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 68.830 47.940 +*I mux_right_track_20\/mux_l2_in_0_:A0 I *L 0.001631 *C 102.755 53.720 +*I mux_right_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 87.115 55.080 +*I mux_right_track_18\/mux_l2_in_0_:A0 I *L 0.001631 *C 88.495 44.540 +*I mux_right_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 82.055 42.500 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.430 42.500 +*N optlc_net_115:7 *C 73.468 42.500 +*N optlc_net_115:8 *C 82.055 42.500 +*N optlc_net_115:9 *C 88.495 44.540 +*N optlc_net_115:10 *C 87.153 55.080 +*N optlc_net_115:11 *C 88.275 55.080 +*N optlc_net_115:12 *C 88.320 55.035 +*N optlc_net_115:13 *C 102.718 53.720 +*N optlc_net_115:14 *C 88.365 53.720 +*N optlc_net_115:15 *C 88.320 53.720 +*N optlc_net_115:16 *C 88.320 44.585 +*N optlc_net_115:17 *C 88.320 44.540 +*N optlc_net_115:18 *C 88.320 44.200 +*N optlc_net_115:19 *C 68.830 47.940 +*N optlc_net_115:20 *C 69.000 47.940 +*N optlc_net_115:21 *C 69.000 47.895 +*N optlc_net_115:22 *C 69.000 44.245 +*N optlc_net_115:23 *C 69.045 44.200 +*N optlc_net_115:24 *C 85.100 44.200 +*N optlc_net_115:25 *C 85.100 44.155 +*N optlc_net_115:26 *C 85.100 42.545 +*N optlc_net_115:27 *C 85.100 42.500 +*N optlc_net_115:28 *C 85.523 42.500 + +*CAP +0 optlc_111:HI 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_20\/mux_l2_in_0_:A0 1e-06 +3 mux_right_track_4\/mux_l2_in_1_:A0 1e-06 +4 mux_right_track_18\/mux_l2_in_0_:A0 1e-06 +5 mux_right_track_16\/mux_l2_in_0_:A0 1e-06 +6 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +7 optlc_net_115:7 0.0003097072 +8 optlc_net_115:8 0.0004532352 +9 optlc_net_115:9 5.268892e-05 +10 optlc_net_115:10 9.616501e-05 +11 optlc_net_115:11 9.616501e-05 +12 optlc_net_115:12 8.574293e-05 +13 optlc_net_115:13 0.0009467795 +14 optlc_net_115:14 0.0009467795 +15 optlc_net_115:15 0.0005854286 +16 optlc_net_115:16 0.0004705032 +17 optlc_net_115:17 7.521348e-05 +18 optlc_net_115:18 0.000241739 +19 optlc_net_115:19 4.662887e-05 +20 optlc_net_115:20 5.083749e-05 +21 optlc_net_115:21 0.00015566 +22 optlc_net_115:22 0.00015566 +23 optlc_net_115:23 0.000999843 +24 optlc_net_115:24 0.001256003 +25 optlc_net_115:25 0.0001123758 +26 optlc_net_115:26 0.0001123758 +27 optlc_net_115:27 0.0001739818 +28 optlc_net_115:28 2.35796e-05 +29 optlc_net_115:7 chanx_right_in[6]:23 0.0003298145 +30 optlc_net_115:28 chanx_right_in[6]:24 2.275412e-05 +31 optlc_net_115:27 chanx_right_in[6]:23 2.275412e-05 +32 optlc_net_115:27 chanx_right_in[6]:24 0.000115072 +33 optlc_net_115:8 chanx_right_in[6]:23 0.000115072 +34 optlc_net_115:8 chanx_right_in[6]:24 0.0003298145 +35 optlc_net_115:22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.675682e-05 +36 optlc_net_115:21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.675682e-05 + +*RES +0 optlc_111:HI optlc_net_115:28 0.152 +1 optlc_net_115:7 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +2 optlc_net_115:23 optlc_net_115:22 0.0045 +3 optlc_net_115:22 optlc_net_115:21 0.003258929 +4 optlc_net_115:20 optlc_net_115:19 9.23913e-05 +5 optlc_net_115:21 optlc_net_115:20 0.0045 +6 optlc_net_115:19 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +7 optlc_net_115:28 optlc_net_115:27 0.0003772322 +8 optlc_net_115:24 optlc_net_115:23 0.01433482 +9 optlc_net_115:24 optlc_net_115:18 0.002875 +10 optlc_net_115:25 optlc_net_115:24 0.0045 +11 optlc_net_115:27 optlc_net_115:26 0.0045 +12 optlc_net_115:27 optlc_net_115:8 0.00271875 +13 optlc_net_115:26 optlc_net_115:25 0.0014375 +14 optlc_net_115:17 optlc_net_115:16 0.0045 +15 optlc_net_115:17 optlc_net_115:9 9.510869e-05 +16 optlc_net_115:16 optlc_net_115:15 0.008156251 +17 optlc_net_115:14 optlc_net_115:13 0.01281473 +18 optlc_net_115:15 optlc_net_115:14 0.0045 +19 optlc_net_115:15 optlc_net_115:12 0.001174107 +20 optlc_net_115:13 mux_right_track_20\/mux_l2_in_0_:A0 0.152 +21 optlc_net_115:9 mux_right_track_18\/mux_l2_in_0_:A0 0.152 +22 optlc_net_115:11 optlc_net_115:10 0.001002232 +23 optlc_net_115:12 optlc_net_115:11 0.0045 +24 optlc_net_115:10 mux_right_track_4\/mux_l2_in_1_:A0 0.152 +25 optlc_net_115:8 mux_right_track_16\/mux_l2_in_0_:A0 0.152 +26 optlc_net_115:8 optlc_net_115:7 0.007667411 +27 optlc_net_115:18 optlc_net_115:17 0.0003035715 + +*END + +*D_NET chany_top_out[16] 0.001548207 //LENGTH 11.520 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 48.300 96.220 +*P chany_top_out[16] O *L 0.7423 *C 48.300 102.035 +*N chany_top_out[16]:2 *C 48.300 101.705 +*N chany_top_out[16]:3 *C 48.255 101.660 +*N chany_top_out[16]:4 *C 46.045 101.660 +*N chany_top_out[16]:5 *C 46.000 101.615 +*N chany_top_out[16]:6 *C 46.000 96.265 +*N chany_top_out[16]:7 *C 46.045 96.220 +*N chany_top_out[16]:8 *C 48.263 96.220 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 chany_top_out[16] 3.550669e-05 +2 chany_top_out[16]:2 3.550669e-05 +3 chany_top_out[16]:3 0.0001514558 +4 chany_top_out[16]:4 0.0001514558 +5 chany_top_out[16]:5 0.0004113339 +6 chany_top_out[16]:6 0.0004113339 +7 chany_top_out[16]:7 0.0001753072 +8 chany_top_out[16]:8 0.0001753072 + +*RES +0 ropt_mt_inst_758:X chany_top_out[16]:8 0.152 +1 chany_top_out[16]:3 chany_top_out[16]:2 0.0045 +2 chany_top_out[16]:2 chany_top_out[16] 0.0002946429 +3 chany_top_out[16]:4 chany_top_out[16]:3 0.001973214 +4 chany_top_out[16]:5 chany_top_out[16]:4 0.0045 +5 chany_top_out[16]:7 chany_top_out[16]:6 0.0045 +6 chany_top_out[16]:6 chany_top_out[16]:5 0.004776786 +7 chany_top_out[16]:8 chany_top_out[16]:7 0.001979911 + +*END + +*D_NET chanx_right_out[16] 0.000334104 //LENGTH 2.280 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 110.135 36.720 +*P chanx_right_out[16] O *L 0.7423 *C 111.863 36.720 +*N chanx_right_out[16]:2 *C 111.780 36.720 +*N chanx_right_out[16]:3 *C 111.780 36.720 +*N chanx_right_out[16]:4 *C 111.735 36.720 +*N chanx_right_out[16]:5 *C 110.172 36.720 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 chanx_right_out[16] 3.34082e-05 +2 chanx_right_out[16]:2 3.34082e-05 +3 chanx_right_out[16]:3 3.396784e-05 +4 chanx_right_out[16]:4 0.0001161599 +5 chanx_right_out[16]:5 0.0001161599 + +*RES +0 ropt_mt_inst_771:X chanx_right_out[16]:5 0.152 +1 chanx_right_out[16]:5 chanx_right_out[16]:4 0.001395089 +2 chanx_right_out[16]:4 chanx_right_out[16]:3 0.0045 +3 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +4 chanx_right_out[16]:2 chanx_right_out[16] 2.35e-05 + +*END + +*D_NET chany_top_out[8] 0.0009853516 //LENGTH 7.115 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 23.000 97.240 +*P chany_top_out[8] O *L 0.7423 *C 22.080 102.150 +*N chany_top_out[8]:2 *C 21.680 97.240 +*N chany_top_out[8]:3 *C 22.080 97.248 +*N chany_top_out[8]:4 *C 22.080 97.240 +*N chany_top_out[8]:5 *C 22.080 97.240 +*N chany_top_out[8]:6 *C 22.125 97.240 +*N chany_top_out[8]:7 *C 23.000 97.240 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 chany_top_out[8] 0.0003113012 +2 chany_top_out[8]:2 6.990831e-05 +3 chany_top_out[8]:3 0.0003113012 +4 chany_top_out[8]:4 6.990831e-05 +5 chany_top_out[8]:5 3.326284e-05 +6 chany_top_out[8]:6 8.065271e-05 +7 chany_top_out[8]:7 0.0001080171 + +*RES +0 ropt_mt_inst_746:X chany_top_out[8]:7 0.152 +1 chany_top_out[8]:7 chany_top_out[8]:6 0.00078125 +2 chany_top_out[8]:6 chany_top_out[8]:5 0.0045 +3 chany_top_out[8]:5 chany_top_out[8]:4 0.00341 +4 chany_top_out[8]:4 chany_top_out[8]:3 0.00341 +5 chany_top_out[8]:4 chany_top_out[8]:2 5.69697e-05 +6 chany_top_out[8]:3 chany_top_out[8] 0.0007680582 + +*END + +*D_NET ropt_net_135 0.0005454998 //LENGTH 3.925 LUMPCC 0.0002304921 DR + +*CONN +*I BUFT_P_97:X O *L 0 *C 105.340 42.500 +*I ropt_mt_inst_752:A I *L 0.001766 *C 106.260 44.880 +*N ropt_net_135:2 *C 106.223 44.880 +*N ropt_net_135:3 *C 105.385 44.880 +*N ropt_net_135:4 *C 105.340 44.835 +*N ropt_net_135:5 *C 105.340 42.545 +*N ropt_net_135:6 *C 105.340 42.500 + +*CAP +0 BUFT_P_97:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_135:2 3.963675e-05 +3 ropt_net_135:3 3.963675e-05 +4 ropt_net_135:4 9.992094e-05 +5 ropt_net_135:5 9.992094e-05 +6 ropt_net_135:6 3.38924e-05 +7 ropt_net_135:2 chanx_right_out[9]:7 4.520288e-05 +8 ropt_net_135:3 chanx_right_out[9]:8 4.520288e-05 +9 ropt_net_135:4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.004316e-05 +10 ropt_net_135:5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.004316e-05 + +*RES +0 BUFT_P_97:X ropt_net_135:6 0.152 +1 ropt_net_135:2 ropt_mt_inst_752:A 0.152 +2 ropt_net_135:3 ropt_net_135:2 0.0007477679 +3 ropt_net_135:4 ropt_net_135:3 0.0045 +4 ropt_net_135:6 ropt_net_135:5 0.0045 +5 ropt_net_135:5 ropt_net_135:4 0.002044643 + +*END + +*D_NET chany_top_in[18] 0.01631978 //LENGTH 106.595 LUMPCC 0.007613583 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 44.160 102.150 +*I FTB_6__5:A I *L 0.001767 *C 103.500 55.760 +*N chany_top_in[18]:2 *C 103.500 55.760 +*N chany_top_in[18]:3 *C 103.500 55.805 +*N chany_top_in[18]:4 *C 103.500 56.383 +*N chany_top_in[18]:5 *C 103.493 56.440 +*N chany_top_in[18]:6 *C 93.970 56.440 +*N chany_top_in[18]:7 *C 44.180 56.440 +*N chany_top_in[18]:8 *C 44.160 56.448 + +*CAP +0 chany_top_in[18] 0.002544431 +1 FTB_6__5:A 1e-06 +2 chany_top_in[18]:2 3.240521e-05 +3 chany_top_in[18]:3 5.58012e-05 +4 chany_top_in[18]:4 5.58012e-05 +5 chany_top_in[18]:5 0.0003785184 +6 chany_top_in[18]:6 0.001736162 +7 chany_top_in[18]:7 0.001357643 +8 chany_top_in[18]:8 0.002544431 +9 chany_top_in[18]:7 chanx_right_in[13]:6 0.002420845 +10 chany_top_in[18]:6 chanx_right_in[13]:7 0.002420845 +11 chany_top_in[18] mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.095732e-05 +12 chany_top_in[18]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002296929 +13 chany_top_in[18]:7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001083098 +14 chany_top_in[18]:7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.219828e-05 +15 chany_top_in[18]:8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.095732e-05 +16 chany_top_in[18]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.219828e-05 +17 chany_top_in[18]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001312791 + +*RES +0 chany_top_in[18] chany_top_in[18]:8 0.007160057 +1 chany_top_in[18]:2 FTB_6__5:A 0.152 +2 chany_top_in[18]:3 chany_top_in[18]:2 0.0045 +3 chany_top_in[18]:4 chany_top_in[18]:3 0.0005156249 +4 chany_top_in[18]:5 chany_top_in[18]:4 0.00341 +5 chany_top_in[18]:7 chany_top_in[18]:6 0.007800433 +6 chany_top_in[18]:8 chany_top_in[18]:7 0.00341 +7 chany_top_in[18]:6 chany_top_in[18]:5 0.001491858 + +*END + +*D_NET ropt_net_117 0.002661186 //LENGTH 22.905 LUMPCC 0 DR + +*CONN +*I mem_right_track_26\/BUFT_RR_65:X O *L 0 *C 23.460 67.320 +*I ropt_mt_inst_729:A I *L 0.001766 *C 3.220 69.360 +*N ropt_net_117:2 *C 3.220 69.360 +*N ropt_net_117:3 *C 3.220 69.315 +*N ropt_net_117:4 *C 3.220 67.365 +*N ropt_net_117:5 *C 3.265 67.320 +*N ropt_net_117:6 *C 23.422 67.320 + +*CAP +0 mem_right_track_26\/BUFT_RR_65:X 1e-06 +1 ropt_mt_inst_729:A 1e-06 +2 ropt_net_117:2 2.901871e-05 +3 ropt_net_117:3 0.0001159623 +4 ropt_net_117:4 0.0001159623 +5 ropt_net_117:5 0.001199121 +6 ropt_net_117:6 0.001199121 + +*RES +0 mem_right_track_26\/BUFT_RR_65:X ropt_net_117:6 0.152 +1 ropt_net_117:6 ropt_net_117:5 0.01799777 +2 ropt_net_117:5 ropt_net_117:4 0.0045 +3 ropt_net_117:4 ropt_net_117:3 0.001741072 +4 ropt_net_117:2 ropt_mt_inst_729:A 0.152 +5 ropt_net_117:3 ropt_net_117:2 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.002227342 //LENGTH 18.790 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 51.365 47.940 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 41.040 47.260 +*I mem_top_track_8\/FTB_3__24:A I *L 0.001746 *C 39.560 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 39.598 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 40.480 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 41.003 47.260 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 40.525 47.260 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 40.480 47.305 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 40.480 49.595 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 40.480 49.640 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 51.015 49.640 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 51.060 49.595 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 51.060 47.985 +*N mux_tree_tapbuf_size2_2_sram[1]:13 *C 51.060 47.940 +*N mux_tree_tapbuf_size2_2_sram[1]:14 *C 51.365 47.940 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_8\/FTB_3__24:A 1e-06 +3 mux_tree_tapbuf_size2_2_sram[1]:3 7.185581e-05 +4 mux_tree_tapbuf_size2_2_sram[1]:4 0.0001155978 +5 mux_tree_tapbuf_size2_2_sram[1]:5 5.766161e-05 +6 mux_tree_tapbuf_size2_2_sram[1]:6 5.766161e-05 +7 mux_tree_tapbuf_size2_2_sram[1]:7 0.0001388806 +8 mux_tree_tapbuf_size2_2_sram[1]:8 0.0001388806 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.000686435 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.000642693 +11 mux_tree_tapbuf_size2_2_sram[1]:11 0.0001059951 +12 mux_tree_tapbuf_size2_2_sram[1]:12 0.0001059951 +13 mux_tree_tapbuf_size2_2_sram[1]:13 5.040354e-05 +14 mux_tree_tapbuf_size2_2_sram[1]:14 5.228216e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:14 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.009406251 +2 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size2_2_sram[1]:13 mux_tree_tapbuf_size2_2_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 0.0014375 +5 mux_tree_tapbuf_size2_2_sram[1]:14 mux_tree_tapbuf_size2_2_sram[1]:13 0.0001657609 +6 mux_tree_tapbuf_size2_2_sram[1]:3 mem_top_track_8\/FTB_3__24:A 0.152 +7 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:4 0.0006071429 +9 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.002044643 +10 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.0004263393 +11 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.0045 +12 mux_tree_tapbuf_size2_2_sram[1]:5 mux_top_track_8\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size2_2_sram[1]:4 mux_tree_tapbuf_size2_2_sram[1]:3 0.0007879465 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[1] 0.001387327 //LENGTH 11.360 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.505 47.600 +*I mem_right_track_16\/FTB_8__29:A I *L 0.001746 *C 77.280 44.880 +*I mux_right_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 81.300 41.480 +*N mux_tree_tapbuf_size2_7_sram[1]:3 *C 81.263 41.480 +*N mux_tree_tapbuf_size2_7_sram[1]:4 *C 78.705 41.480 +*N mux_tree_tapbuf_size2_7_sram[1]:5 *C 78.660 41.525 +*N mux_tree_tapbuf_size2_7_sram[1]:6 *C 77.318 44.880 +*N mux_tree_tapbuf_size2_7_sram[1]:7 *C 78.615 44.880 +*N mux_tree_tapbuf_size2_7_sram[1]:8 *C 78.660 44.880 +*N mux_tree_tapbuf_size2_7_sram[1]:9 *C 78.660 47.555 +*N mux_tree_tapbuf_size2_7_sram[1]:10 *C 78.660 47.600 +*N mux_tree_tapbuf_size2_7_sram[1]:11 *C 78.505 47.600 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_16\/FTB_8__29:A 1e-06 +2 mux_right_track_16\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_7_sram[1]:3 0.0001906782 +4 mux_tree_tapbuf_size2_7_sram[1]:4 0.0001906782 +5 mux_tree_tapbuf_size2_7_sram[1]:5 0.0001874846 +6 mux_tree_tapbuf_size2_7_sram[1]:6 9.979105e-05 +7 mux_tree_tapbuf_size2_7_sram[1]:7 9.979105e-05 +8 mux_tree_tapbuf_size2_7_sram[1]:8 0.0003654819 +9 mux_tree_tapbuf_size2_7_sram[1]:9 0.0001469118 +10 mux_tree_tapbuf_size2_7_sram[1]:10 5.374917e-05 +11 mux_tree_tapbuf_size2_7_sram[1]:11 4.97606e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_7_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_7_sram[1]:3 mux_right_track_16\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_7_sram[1]:4 mux_tree_tapbuf_size2_7_sram[1]:3 0.002283482 +3 mux_tree_tapbuf_size2_7_sram[1]:5 mux_tree_tapbuf_size2_7_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_7_sram[1]:7 mux_tree_tapbuf_size2_7_sram[1]:6 0.001158482 +5 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:5 0.002995536 +7 mux_tree_tapbuf_size2_7_sram[1]:6 mem_right_track_16\/FTB_8__29:A 0.152 +8 mux_tree_tapbuf_size2_7_sram[1]:10 mux_tree_tapbuf_size2_7_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size2_7_sram[1]:9 mux_tree_tapbuf_size2_7_sram[1]:8 0.002388393 +10 mux_tree_tapbuf_size2_7_sram[1]:11 mux_tree_tapbuf_size2_7_sram[1]:10 8.423912e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.001035279 //LENGTH 8.320 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/FTB_2__23:X O *L 0 *C 63.245 48.280 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 55.835 47.940 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 55.873 47.940 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 56.580 47.940 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 56.580 48.280 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 63.208 48.280 + +*CAP +0 mem_top_track_4\/FTB_2__23:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 5.990798e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 8.33461e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0004567316 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0004332935 + +*RES +0 mem_top_track_4\/FTB_2__23:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.005917411 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 0.0006316964 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001792802 //LENGTH 14.370 LUMPCC 0.0002512313 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.145 60.860 +*I mem_right_track_24\/FTB_18__39:A I *L 0.001746 *C 67.160 63.920 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 68.420 69.020 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 68.405 69.020 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 68.103 69.020 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 68.080 68.975 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 67.198 63.920 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 67.620 63.920 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 67.620 64.260 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 67.620 64.260 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 68.080 64.260 +*N mux_tree_tapbuf_size3_1_sram[1]:11 *C 68.080 60.905 +*N mux_tree_tapbuf_size3_1_sram[1]:12 *C 68.125 60.860 +*N mux_tree_tapbuf_size3_1_sram[1]:13 *C 71.108 60.860 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_24\/FTB_18__39:A 1e-06 +2 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 4.621004e-05 +4 mux_tree_tapbuf_size3_1_sram[1]:4 4.621004e-05 +5 mux_tree_tapbuf_size3_1_sram[1]:5 0.0002660802 +6 mux_tree_tapbuf_size3_1_sram[1]:6 4.216143e-05 +7 mux_tree_tapbuf_size3_1_sram[1]:7 7.184752e-05 +8 mux_tree_tapbuf_size3_1_sram[1]:8 6.454728e-05 +9 mux_tree_tapbuf_size3_1_sram[1]:9 6.437235e-05 +10 mux_tree_tapbuf_size3_1_sram[1]:10 0.000490012 +11 mux_tree_tapbuf_size3_1_sram[1]:11 0.0001908394 +12 mux_tree_tapbuf_size3_1_sram[1]:12 0.0001281453 +13 mux_tree_tapbuf_size3_1_sram[1]:13 0.0001281453 +14 mux_tree_tapbuf_size3_1_sram[1]:12 mux_tree_tapbuf_size3_1_sram[0]:10 0.0001256156 +15 mux_tree_tapbuf_size3_1_sram[1]:13 mux_tree_tapbuf_size3_1_sram[0]:11 0.0001256156 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:3 mux_right_track_24\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.0001644022 +3 mux_tree_tapbuf_size3_1_sram[1]:5 mux_tree_tapbuf_size3_1_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size3_1_sram[1]:12 mux_tree_tapbuf_size3_1_sram[1]:11 0.0045 +5 mux_tree_tapbuf_size3_1_sram[1]:11 mux_tree_tapbuf_size3_1_sram[1]:10 0.002995536 +6 mux_tree_tapbuf_size3_1_sram[1]:13 mux_tree_tapbuf_size3_1_sram[1]:12 0.002662947 +7 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.0003035715 +8 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size3_1_sram[1]:6 mem_right_track_24\/FTB_18__39:A 0.152 +10 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.0003772322 +11 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0004107143 +12 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:5 0.004209821 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_1_ccff_tail[0] 0.001892833 //LENGTH 15.080 LUMPCC 0 DR + +*CONN +*I mem_right_track_6\/FTB_16__37:X O *L 0 *C 62.785 95.880 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 51.235 93.500 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 *C 51.273 93.500 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 *C 62.975 93.500 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 *C 63.020 93.545 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 *C 63.020 95.835 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 *C 63.020 95.880 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 *C 62.785 95.880 + +*CAP +0 mem_right_track_6\/FTB_16__37:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.0007468686 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0007468686 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.0001422233 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0001422233 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 5.655808e-05 +7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 5.609111e-05 + +*RES +0 mem_right_track_6\/FTB_16__37:X mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.01044866 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.002733622 //LENGTH 20.590 LUMPCC 0.0003651744 DR + +*CONN +*I mem_right_track_4\/FTB_14__35:X O *L 0 *C 88.975 70.040 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 74.695 75.140 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 74.733 75.140 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 83.675 75.140 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 83.720 75.095 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 83.720 72.760 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 86.020 72.760 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 86.020 70.085 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 *C 86.065 70.040 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 *C 88.938 70.040 + +*CAP +0 mem_right_track_4\/FTB_14__35:X 1e-06 +1 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 0.0006120256 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0006120256 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.0001792166 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0002324721 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.0002309615 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.000177706 +8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 0.0001610202 +9 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 0.0001610202 +10 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 right_top_grid_pin_44_[0]:16 7.734932e-05 +11 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 right_top_grid_pin_44_[0]:17 7.734932e-05 +12 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001052379 +13 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001052379 + +*RES +0 mem_right_track_4\/FTB_14__35:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 0.007984376 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.0045 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.002388393 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 0.002564732 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.002084821 +8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.002053571 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003767758 //LENGTH 39.620 LUMPCC 0.0004076859 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 35.135 64.260 +*I mux_top_track_24\/BUFT_RR_43:A I *L 0.001776 *C 23.000 91.120 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 23.000 91.120 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 23.000 91.075 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 23.000 64.305 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 23.045 64.260 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 35.098 64.260 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/BUFT_RR_43:A 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.935565e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001018438 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001018438 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006459196 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006459196 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[10]:9 0.0001177024 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[10]:10 8.614053e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[10]:8 0.0001177024 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[10]:9 8.614053e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.01076116 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.02390179 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/BUFT_RR_43:A 0.152 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005817103 //LENGTH 47.065 LUMPCC 0.0004355593 DR + +*CONN +*I mux_right_track_14\/mux_l2_in_0_:X O *L 0 *C 77.565 58.820 +*I mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 107.905 50.160 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 107.868 50.263 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 99.405 50.320 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 99.360 50.365 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 99.360 60.475 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 99.315 60.520 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 75.945 60.520 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 75.900 60.475 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 75.900 58.865 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 75.945 58.820 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 77.528 58.820 + +*CAP +0 mux_right_track_14\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004643765 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0004643765 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0005174383 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0005174383 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001452922 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001452922 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001317832 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001317832 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001232519 +11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001232519 +12 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001199936 +13 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001199936 +14 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.01278e-05 +15 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.765826e-05 +16 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.01278e-05 +17 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.765826e-05 + +*RES +0 mux_right_track_14\/mux_l2_in_0_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.007555804 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.009026786 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.02086607 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0014375 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001412946 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001788993 //LENGTH 10.755 LUMPCC 0.0005907089 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_1_:X O *L 0 *C 66.875 71.740 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.595 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.595 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 58.880 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.880 70.085 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.880 71.343 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.888 71.400 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 66.693 71.400 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 66.700 71.400 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 66.700 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 66.700 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 66.875 71.740 + +*CAP +0 mux_right_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.070462e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.472879e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.738204e-05 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.738204e-05 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003346691 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003346691 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.823033e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.595685e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.71885e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.537308e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[11]:6 0.0001617986 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[11]:5 0.0001617986 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 right_top_grid_pin_44_[0]:10 0.0001281792 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 right_top_grid_pin_44_[0]:12 8.97498e-08 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 right_top_grid_pin_44_[0]:11 0.0001281792 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 right_top_grid_pin_44_[0]:14 5.286903e-06 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 right_top_grid_pin_44_[0]:13 8.97498e-08 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 right_top_grid_pin_44_[0]:15 5.286903e-06 + +*RES +0 mux_right_track_0\/mux_l1_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001122768 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001222783 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001634616 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.004355587 //LENGTH 30.410 LUMPCC 0.002258202 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_0_:X O *L 0 *C 80.785 72.080 +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.360 66.470 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 103.398 66.470 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 103.915 66.525 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 103.960 66.685 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 103.960 72.023 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 103.953 72.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 83.728 72.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 83.720 72.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 83.675 72.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 80.823 72.080 + +*CAP +0 mux_right_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.01133e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.01133e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003324799 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003324799 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003992909 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003992909 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.971292e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.000225952 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.000225952 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[9]:16 0.0004113045 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[9]:15 0.0004113045 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[17]:17 1.277552e-07 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[17]:16 1.277552e-07 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[17]:15 0.0004937151 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[17]:14 0.0004937151 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_46_[0]:7 0.0002239537 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 right_top_grid_pin_46_[0]:17 0.0002239537 + +*RES +0 mux_right_track_2\/mux_l3_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004620536 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004765626 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.003168583 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.002546875 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.007651986 //LENGTH 53.730 LUMPCC 0.002836012 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 71.125 68.680 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 107.835 69.530 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 107.835 69.530 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 107.835 70.040 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 102.165 70.040 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 102.120 69.995 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 102.120 61.938 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 102.113 61.880 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 71.308 61.880 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 71.300 61.938 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 71.300 68.635 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 71.300 68.680 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 71.125 68.680 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.833399e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004812437 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004315036 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004384457 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004384457 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001008503 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001008503 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0004032828 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0004032828 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 5.785108e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 5.457956e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[0]:11 0.0002843525 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[0]:12 0.0002497935 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[0]:12 0.0002843525 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[0]:13 0.0002497935 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[19]:9 0.0005850953 +18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[19]:10 0.0005850953 +19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 right_bottom_grid_pin_1_[0]:17 1.347478e-06 +20 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 right_bottom_grid_pin_1_[0]:18 1.347478e-06 +21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 right_bottom_grid_pin_1_[0]:23 0.0002974173 +22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 right_bottom_grid_pin_1_[0]:24 0.0002974173 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 9.51087e-05 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.005979911 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.00341 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.004826116 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.007194197 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00341 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0050625 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004553572 + +*END + +*D_NET mem_right_track_26/net_aps_33 0.003253489 //LENGTH 28.070 LUMPCC 0.0002586816 DR + +*CONN +*I mem_right_track_26\/FTB_12__33:X O *L 0 *C 49.445 63.580 +*I mem_right_track_26\/BUFT_RR_65:A I *L 0.001776 *C 25.760 66.640 +*N mem_right_track_26/net_aps_33:2 *C 25.760 66.640 +*N mem_right_track_26/net_aps_33:3 *C 25.760 66.595 +*N mem_right_track_26/net_aps_33:4 *C 25.760 64.657 +*N mem_right_track_26/net_aps_33:5 *C 25.768 64.600 +*N mem_right_track_26/net_aps_33:6 *C 40.933 64.600 +*N mem_right_track_26/net_aps_33:7 *C 40.940 64.543 +*N mem_right_track_26/net_aps_33:8 *C 40.940 63.625 +*N mem_right_track_26/net_aps_33:9 *C 40.985 63.580 +*N mem_right_track_26/net_aps_33:10 *C 49.407 63.580 + +*CAP +0 mem_right_track_26\/FTB_12__33:X 1e-06 +1 mem_right_track_26\/BUFT_RR_65:A 1e-06 +2 mem_right_track_26/net_aps_33:2 3.036706e-05 +3 mem_right_track_26/net_aps_33:3 0.000103939 +4 mem_right_track_26/net_aps_33:4 0.000103939 +5 mem_right_track_26/net_aps_33:5 0.000821459 +6 mem_right_track_26/net_aps_33:6 0.000821459 +7 mem_right_track_26/net_aps_33:7 7.088634e-05 +8 mem_right_track_26/net_aps_33:8 7.088634e-05 +9 mem_right_track_26/net_aps_33:9 0.0004849356 +10 mem_right_track_26/net_aps_33:10 0.0004849356 +11 mem_right_track_26/net_aps_33:5 chanx_right_in[0]:11 0.0001293408 +12 mem_right_track_26/net_aps_33:6 chanx_right_in[0]:12 0.0001293408 + +*RES +0 mem_right_track_26\/FTB_12__33:X mem_right_track_26/net_aps_33:10 0.152 +1 mem_right_track_26/net_aps_33:2 mem_right_track_26\/BUFT_RR_65:A 0.152 +2 mem_right_track_26/net_aps_33:3 mem_right_track_26/net_aps_33:2 0.0045 +3 mem_right_track_26/net_aps_33:4 mem_right_track_26/net_aps_33:3 0.001729911 +4 mem_right_track_26/net_aps_33:5 mem_right_track_26/net_aps_33:4 0.00341 +5 mem_right_track_26/net_aps_33:7 mem_right_track_26/net_aps_33:6 0.00341 +6 mem_right_track_26/net_aps_33:6 mem_right_track_26/net_aps_33:5 0.00237585 +7 mem_right_track_26/net_aps_33:9 mem_right_track_26/net_aps_33:8 0.0045 +8 mem_right_track_26/net_aps_33:8 mem_right_track_26/net_aps_33:7 0.0008191965 +9 mem_right_track_26/net_aps_33:10 mem_right_track_26/net_aps_33:9 0.00752009 + +*END + +*D_NET BUF_net_62 0.003809923 //LENGTH 29.310 LUMPCC 0.001077833 DR + +*CONN +*I BUFT_RR_62:X O *L 0 *C 51.980 83.300 +*I BUFT_RR_83:A I *L 0.001766 *C 43.240 99.280 +*N BUF_net_62:2 *C 43.240 99.280 +*N BUF_net_62:3 *C 43.240 99.620 +*N BUF_net_62:4 *C 52.855 99.620 +*N BUF_net_62:5 *C 52.900 99.620 +*N BUF_net_62:6 *C 53.360 99.620 +*N BUF_net_62:7 *C 53.360 83.345 +*N BUF_net_62:8 *C 53.315 83.300 +*N BUF_net_62:9 *C 52.018 83.300 + +*CAP +0 BUFT_RR_62:X 1e-06 +1 BUFT_RR_83:A 1e-06 +2 BUF_net_62:2 5.924969e-05 +3 BUF_net_62:3 0.0005960079 +4 BUF_net_62:4 0.0005669869 +5 BUF_net_62:5 6.554974e-05 +6 BUF_net_62:6 0.0006421259 +7 BUF_net_62:7 0.0006085981 +8 BUF_net_62:8 9.578594e-05 +9 BUF_net_62:9 9.578594e-05 +10 BUF_net_62:7 chany_top_in[9]:5 0.0001121567 +11 BUF_net_62:6 chany_top_in[9] 0.0001121567 +12 BUF_net_62:7 chany_top_in[19]:3 0.0002666012 +13 BUF_net_62:6 chany_top_in[19]:4 0.0002666012 +14 BUF_net_62:4 ropt_net_120:3 0.0001601588 +15 BUF_net_62:3 ropt_net_120:2 0.0001601588 + +*RES +0 BUFT_RR_62:X BUF_net_62:9 0.152 +1 BUF_net_62:9 BUF_net_62:8 0.001158482 +2 BUF_net_62:8 BUF_net_62:7 0.0045 +3 BUF_net_62:7 BUF_net_62:6 0.01453125 +4 BUF_net_62:4 BUF_net_62:3 0.008584822 +5 BUF_net_62:5 BUF_net_62:4 0.0045 +6 BUF_net_62:2 BUFT_RR_83:A 0.152 +7 BUF_net_62:3 BUF_net_62:2 0.0003035715 +8 BUF_net_62:6 BUF_net_62:5 0.0004107143 + +*END + +*D_NET ropt_net_143 0.000850868 //LENGTH 7.450 LUMPCC 0.0001422296 DR + +*CONN +*I BUFT_P_101:X O *L 0 *C 13.340 94.180 +*I ropt_mt_inst_765:A I *L 0.001766 *C 9.200 96.560 +*N ropt_net_143:2 *C 9.238 96.560 +*N ropt_net_143:3 *C 10.075 96.560 +*N ropt_net_143:4 *C 10.120 96.515 +*N ropt_net_143:5 *C 10.120 94.225 +*N ropt_net_143:6 *C 10.165 94.180 +*N ropt_net_143:7 *C 13.303 94.180 + +*CAP +0 BUFT_P_101:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_143:2 3.512614e-05 +3 ropt_net_143:3 3.512614e-05 +4 ropt_net_143:4 0.000125699 +5 ropt_net_143:5 0.000125699 +6 ropt_net_143:6 0.000192494 +7 ropt_net_143:7 0.000192494 +8 ropt_net_143:5 chanx_right_in[7]:7 2.563415e-05 +9 ropt_net_143:3 chanx_right_in[7]:5 4.548067e-05 +10 ropt_net_143:4 chanx_right_in[7]:6 2.563415e-05 +11 ropt_net_143:2 chanx_right_in[7]:4 4.548067e-05 + +*RES +0 BUFT_P_101:X ropt_net_143:7 0.152 +1 ropt_net_143:7 ropt_net_143:6 0.002801339 +2 ropt_net_143:6 ropt_net_143:5 0.0045 +3 ropt_net_143:5 ropt_net_143:4 0.002044643 +4 ropt_net_143:3 ropt_net_143:2 0.0007477679 +5 ropt_net_143:4 ropt_net_143:3 0.0045 +6 ropt_net_143:2 ropt_mt_inst_765:A 0.152 + +*END + +*D_NET chanx_right_in[0] 0.01849712 //LENGTH 137.315 LUMPCC 0.006198572 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 111.930 46.240 +*I ropt_mt_inst_730:A I *L 0.001767 *C 30.360 99.280 +*N chanx_right_in[0]:2 *C 30.360 99.280 +*N chanx_right_in[0]:3 *C 30.360 98.940 +*N chanx_right_in[0]:4 *C 30.360 98.895 +*N chanx_right_in[0]:5 *C 30.360 69.405 +*N chanx_right_in[0]:6 *C 30.405 69.360 +*N chanx_right_in[0]:7 *C 33.435 69.360 +*N chanx_right_in[0]:8 *C 35.375 69.360 +*N chanx_right_in[0]:9 *C 35.420 69.315 +*N chanx_right_in[0]:10 *C 35.420 63.298 +*N chanx_right_in[0]:11 *C 35.428 63.240 +*N chanx_right_in[0]:12 *C 85.255 63.240 +*N chanx_right_in[0]:13 *C 95.660 63.240 +*N chanx_right_in[0]:14 *C 95.680 63.233 +*N chanx_right_in[0]:15 *C 95.680 46.928 +*N chanx_right_in[0]:16 *C 95.700 46.920 +*N chanx_right_in[0]:17 *C 108.100 46.920 +*N chanx_right_in[0]:18 *C 108.100 46.240 + +*CAP +0 chanx_right_in[0] 0.0001816037 +1 ropt_mt_inst_730:A 1e-06 +2 chanx_right_in[0]:2 6.284674e-05 +3 chanx_right_in[0]:3 6.720806e-05 +4 chanx_right_in[0]:4 0.001152583 +5 chanx_right_in[0]:5 0.001152583 +6 chanx_right_in[0]:6 0.0001204977 +7 chanx_right_in[0]:7 0.0002010077 +8 chanx_right_in[0]:8 8.051007e-05 +9 chanx_right_in[0]:9 0.0003260476 +10 chanx_right_in[0]:10 0.0003260476 +11 chanx_right_in[0]:11 0.002432966 +12 chanx_right_in[0]:12 0.002645163 +13 chanx_right_in[0]:13 0.0002121981 +14 chanx_right_in[0]:14 0.0009046715 +15 chanx_right_in[0]:15 0.0009046715 +16 chanx_right_in[0]:16 0.0006242989 +17 chanx_right_in[0]:17 0.0006726699 +18 chanx_right_in[0]:18 0.0002299747 +19 chanx_right_in[0]:4 chanx_right_in[14]:10 0.000274747 +20 chanx_right_in[0]:5 chanx_right_in[14]:11 0.000274747 +21 chanx_right_in[0]:4 chany_top_in[5] 0.0001794687 +22 chanx_right_in[0]:6 chany_top_in[5]:5 5.778063e-05 +23 chanx_right_in[0]:5 chany_top_in[5]:6 0.0001794687 +24 chanx_right_in[0]:8 chany_top_in[5]:4 3.917309e-05 +25 chanx_right_in[0]:7 chany_top_in[5]:5 3.917309e-05 +26 chanx_right_in[0]:7 chany_top_in[5]:4 5.778063e-05 +27 chanx_right_in[0] chanx_right_in[13] 0.0001018877 +28 chanx_right_in[0]:16 chanx_right_in[13]:10 0.0001725051 +29 chanx_right_in[0]:17 chanx_right_in[13] 0.0001725051 +30 chanx_right_in[0]:18 chanx_right_in[13]:10 0.0001018877 +31 chanx_right_in[0]:11 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001014581 +32 chanx_right_in[0]:13 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005956556 +33 chanx_right_in[0]:12 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005956556 +34 chanx_right_in[0]:12 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001014581 +35 chanx_right_in[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002843525 +36 chanx_right_in[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002497935 +37 chanx_right_in[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002497935 +38 chanx_right_in[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002843525 +39 chanx_right_in[0]:11 mem_right_track_26/net_aps_33:5 0.0001293408 +40 chanx_right_in[0]:12 mem_right_track_26/net_aps_33:6 0.0001293408 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:18 0.0006000333 +1 chanx_right_in[0]:2 ropt_mt_inst_730:A 0.152 +2 chanx_right_in[0]:3 chanx_right_in[0]:2 0.0001465517 +3 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0045 +4 chanx_right_in[0]:6 chanx_right_in[0]:5 0.0045 +5 chanx_right_in[0]:5 chanx_right_in[0]:4 0.02633036 +6 chanx_right_in[0]:8 chanx_right_in[0]:7 0.001732143 +7 chanx_right_in[0]:9 chanx_right_in[0]:8 0.0045 +8 chanx_right_in[0]:10 chanx_right_in[0]:9 0.005372768 +9 chanx_right_in[0]:11 chanx_right_in[0]:10 0.00341 +10 chanx_right_in[0]:13 chanx_right_in[0]:12 0.001630117 +11 chanx_right_in[0]:14 chanx_right_in[0]:13 0.00341 +12 chanx_right_in[0]:16 chanx_right_in[0]:15 0.00341 +13 chanx_right_in[0]:15 chanx_right_in[0]:14 0.00255445 +14 chanx_right_in[0]:7 chanx_right_in[0]:6 0.002705357 +15 chanx_right_in[0]:17 chanx_right_in[0]:16 0.001942667 +16 chanx_right_in[0]:18 chanx_right_in[0]:17 0.0001065333 +17 chanx_right_in[0]:12 chanx_right_in[0]:11 0.007806308 + +*END + +*D_NET chanx_right_in[18] 0.01536939 //LENGTH 108.145 LUMPCC 0.004506076 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 111.930 50.320 +*I ropt_mt_inst_736:A I *L 0.001767 *C 57.960 99.280 +*N chanx_right_in[18]:2 *C 57.960 99.280 +*N chanx_right_in[18]:3 *C 57.960 98.940 +*N chanx_right_in[18]:4 *C 65.275 98.940 +*N chanx_right_in[18]:5 *C 65.320 98.895 +*N chanx_right_in[18]:6 *C 65.320 88.740 +*N chanx_right_in[18]:7 *C 65.780 88.740 +*N chanx_right_in[18]:8 *C 65.780 80.285 +*N chanx_right_in[18]:9 *C 65.825 80.240 +*N chanx_right_in[18]:10 *C 69.875 80.240 +*N chanx_right_in[18]:11 *C 69.920 80.195 +*N chanx_right_in[18]:12 *C 69.920 77.578 +*N chanx_right_in[18]:13 *C 69.928 77.520 +*N chanx_right_in[18]:14 *C 81.860 77.520 +*N chanx_right_in[18]:15 *C 81.880 77.513 +*N chanx_right_in[18]:16 *C 81.880 52.367 +*N chanx_right_in[18]:17 *C 81.900 52.360 +*N chanx_right_in[18]:18 *C 105.800 52.360 +*N chanx_right_in[18]:19 *C 105.800 53.040 +*N chanx_right_in[18]:20 *C 107.633 53.040 +*N chanx_right_in[18]:21 *C 107.640 52.983 +*N chanx_right_in[18]:22 *C 107.640 50.378 +*N chanx_right_in[18]:23 *C 107.648 50.320 + +*CAP +0 chanx_right_in[18] 0.000190373 +1 ropt_mt_inst_736:A 1e-06 +2 chanx_right_in[18]:2 5.289518e-05 +3 chanx_right_in[18]:3 0.0004423927 +4 chanx_right_in[18]:4 0.0004162968 +5 chanx_right_in[18]:5 0.000532702 +6 chanx_right_in[18]:6 0.0005627434 +7 chanx_right_in[18]:7 0.0005850612 +8 chanx_right_in[18]:8 0.0005550198 +9 chanx_right_in[18]:9 0.0002543597 +10 chanx_right_in[18]:10 0.0002543597 +11 chanx_right_in[18]:11 0.0001944541 +12 chanx_right_in[18]:12 0.0001944541 +13 chanx_right_in[18]:13 0.0008653384 +14 chanx_right_in[18]:14 0.0008653384 +15 chanx_right_in[18]:15 0.001348206 +16 chanx_right_in[18]:16 0.001348206 +17 chanx_right_in[18]:17 0.0006395172 +18 chanx_right_in[18]:18 0.0006960008 +19 chanx_right_in[18]:19 0.0002197434 +20 chanx_right_in[18]:20 0.0001632598 +21 chanx_right_in[18]:21 0.0001456096 +22 chanx_right_in[18]:22 0.0001456096 +23 chanx_right_in[18]:23 0.000190373 +24 chanx_right_in[18] chanx_right_in[7] 3.402926e-05 +25 chanx_right_in[18] chanx_right_in[7]:10 0.0001291641 +26 chanx_right_in[18]:17 chanx_right_in[7]:9 0.0005503987 +27 chanx_right_in[18]:20 chanx_right_in[7]:10 7.735675e-06 +28 chanx_right_in[18]:23 chanx_right_in[7]:9 0.0001291641 +29 chanx_right_in[18]:23 chanx_right_in[7]:13 3.402926e-05 +30 chanx_right_in[18]:18 chanx_right_in[7]:10 0.0005503987 +31 chanx_right_in[18]:19 chanx_right_in[7]:9 7.735675e-06 +32 chanx_right_in[18]:13 chanx_right_in[9]:11 3.779759e-06 +33 chanx_right_in[18]:14 chanx_right_in[9]:12 3.779759e-06 +34 chanx_right_in[18]:15 chanx_right_in[9]:13 0.0003127194 +35 chanx_right_in[18]:16 chanx_right_in[9]:14 0.0003127194 +36 chanx_right_in[18]:15 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001123158 +37 chanx_right_in[18]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001102895 +38 chanx_right_in[18]:16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001123158 +39 chanx_right_in[18]:18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001102895 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:23 0.0006709249 +1 chanx_right_in[18]:2 ropt_mt_inst_736:A 0.152 +2 chanx_right_in[18]:4 chanx_right_in[18]:3 0.006531251 +3 chanx_right_in[18]:5 chanx_right_in[18]:4 0.0045 +4 chanx_right_in[18]:9 chanx_right_in[18]:8 0.0045 +5 chanx_right_in[18]:8 chanx_right_in[18]:7 0.007549108 +6 chanx_right_in[18]:10 chanx_right_in[18]:9 0.003616072 +7 chanx_right_in[18]:11 chanx_right_in[18]:10 0.0045 +8 chanx_right_in[18]:12 chanx_right_in[18]:11 0.002337054 +9 chanx_right_in[18]:13 chanx_right_in[18]:12 0.00341 +10 chanx_right_in[18]:14 chanx_right_in[18]:13 0.001869425 +11 chanx_right_in[18]:15 chanx_right_in[18]:14 0.00341 +12 chanx_right_in[18]:17 chanx_right_in[18]:16 0.00341 +13 chanx_right_in[18]:16 chanx_right_in[18]:15 0.003939383 +14 chanx_right_in[18]:21 chanx_right_in[18]:20 0.00341 +15 chanx_right_in[18]:20 chanx_right_in[18]:19 0.0002870916 +16 chanx_right_in[18]:22 chanx_right_in[18]:21 0.002325893 +17 chanx_right_in[18]:23 chanx_right_in[18]:22 0.00341 +18 chanx_right_in[18]:3 chanx_right_in[18]:2 0.0003035715 +19 chanx_right_in[18]:6 chanx_right_in[18]:5 0.009066964 +20 chanx_right_in[18]:7 chanx_right_in[18]:6 0.0004107143 +21 chanx_right_in[18]:18 chanx_right_in[18]:17 0.003744333 +22 chanx_right_in[18]:19 chanx_right_in[18]:18 0.0001065333 + +*END + +*D_NET chany_top_in[1] 0.006644696 //LENGTH 57.575 LUMPCC 0.0009369224 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 62.100 102.035 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 83.260 69.020 +*N chany_top_in[1]:2 *C 83.223 69.020 +*N chany_top_in[1]:3 *C 82.845 69.020 +*N chany_top_in[1]:4 *C 82.800 69.065 +*N chany_top_in[1]:5 *C 82.800 101.263 +*N chany_top_in[1]:6 *C 82.800 101.328 +*N chany_top_in[1]:7 *C 82.800 102.000 +*N chany_top_in[1]:8 *C 77.280 102.000 +*N chany_top_in[1]:9 *C 77.280 101.328 +*N chany_top_in[1]:10 *C 77.280 101.320 +*N chany_top_in[1]:11 *C 77.280 101.660 +*N chany_top_in[1]:12 *C 77.235 101.660 +*N chany_top_in[1]:13 *C 62.145 101.660 +*N chany_top_in[1]:14 *C 62.100 101.705 + +*CAP +0 chany_top_in[1] 3.068546e-05 +1 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[1]:2 5.706657e-05 +3 chany_top_in[1]:3 5.706657e-05 +4 chany_top_in[1]:4 0.001442194 +5 chany_top_in[1]:5 0.001442194 +6 chany_top_in[1]:6 4.368441e-05 +7 chany_top_in[1]:7 0.0003059434 +8 chany_top_in[1]:8 0.0003012583 +9 chany_top_in[1]:9 3.89994e-05 +10 chany_top_in[1]:10 4.845891e-05 +11 chany_top_in[1]:11 4.507259e-05 +12 chany_top_in[1]:12 0.0009317318 +13 chany_top_in[1]:13 0.0009317318 +14 chany_top_in[1]:14 3.068546e-05 +15 chany_top_in[1]:4 right_top_grid_pin_49_[0]:10 0.0001620433 +16 chany_top_in[1]:4 right_top_grid_pin_49_[0]:9 0.000306418 +17 chany_top_in[1]:5 right_top_grid_pin_49_[0]:6 0.000306418 +18 chany_top_in[1]:5 right_top_grid_pin_49_[0]:9 0.0001620433 + +*RES +0 chany_top_in[1] chany_top_in[1]:14 0.0002946429 +1 chany_top_in[1]:2 mux_right_track_4\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[1]:3 chany_top_in[1]:2 0.0003370536 +3 chany_top_in[1]:4 chany_top_in[1]:3 0.0045 +4 chany_top_in[1]:5 chany_top_in[1]:4 0.02874777 +5 chany_top_in[1]:6 chany_top_in[1]:5 0.00341 +6 chany_top_in[1]:10 chany_top_in[1]:9 0.00341 +7 chany_top_in[1]:9 chany_top_in[1]:8 0.0001053583 +8 chany_top_in[1]:12 chany_top_in[1]:11 0.0045 +9 chany_top_in[1]:11 chany_top_in[1]:10 0.0001634616 +10 chany_top_in[1]:13 chany_top_in[1]:12 0.01347321 +11 chany_top_in[1]:14 chany_top_in[1]:13 0.0045 +12 chany_top_in[1]:8 chany_top_in[1]:7 0.0008647999 +13 chany_top_in[1]:7 chany_top_in[1]:6 0.0001053583 + +*END + +*D_NET chany_top_in[3] 0.001677973 //LENGTH 13.275 LUMPCC 0.0001550713 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 45.540 102.070 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 46.920 90.780 +*N chany_top_in[3]:2 *C 46.898 90.808 +*N chany_top_in[3]:3 *C 46.885 91.120 +*N chany_top_in[3]:4 *C 45.585 91.120 +*N chany_top_in[3]:5 *C 45.540 91.165 + +*CAP +0 chany_top_in[3] 0.0006075968 +1 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[3]:2 3.046142e-05 +3 chany_top_in[3]:3 0.000153354 +4 chany_top_in[3]:4 0.0001228926 +5 chany_top_in[3]:5 0.0006075968 +6 chany_top_in[3] ropt_net_125:5 7.753567e-05 +7 chany_top_in[3]:5 ropt_net_125:4 7.753567e-05 + +*RES +0 chany_top_in[3] chany_top_in[3]:5 0.009736608 +1 chany_top_in[3]:4 chany_top_in[3]:3 0.001160714 +2 chany_top_in[3]:5 chany_top_in[3]:4 0.0045 +3 chany_top_in[3]:2 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +4 chany_top_in[3]:3 chany_top_in[3]:2 0.0002111487 + +*END + +*D_NET chany_top_in[5] 0.006525454 //LENGTH 57.715 LUMPCC 0.0008791695 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 28.980 102.070 +*I mux_right_track_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.900 69.020 +*N chany_top_in[5]:2 *C 52.863 69.020 +*N chany_top_in[5]:3 *C 52.440 69.020 +*N chany_top_in[5]:4 *C 52.440 70.040 +*N chany_top_in[5]:5 *C 29.025 70.040 +*N chany_top_in[5]:6 *C 28.980 70.085 + +*CAP +0 chany_top_in[5] 0.001333619 +1 mux_right_track_12\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[5]:2 4.286643e-05 +3 chany_top_in[5]:3 0.0001009687 +4 chany_top_in[5]:4 0.001446157 +5 chany_top_in[5]:5 0.001388055 +6 chany_top_in[5]:6 0.001333619 +7 chany_top_in[5] chanx_right_in[0]:4 0.0001794687 +8 chany_top_in[5]:5 chanx_right_in[0]:6 5.778063e-05 +9 chany_top_in[5]:5 chanx_right_in[0]:7 3.917309e-05 +10 chany_top_in[5]:6 chanx_right_in[0]:5 0.0001794687 +11 chany_top_in[5]:4 chanx_right_in[0]:7 5.778063e-05 +12 chany_top_in[5]:4 chanx_right_in[0]:8 3.917309e-05 +13 chany_top_in[5]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0001036852 +14 chany_top_in[5]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 0.0001036852 +15 chany_top_in[5] ropt_net_144:5 1.81935e-06 +16 chany_top_in[5] ropt_net_144:8 5.765777e-05 +17 chany_top_in[5]:6 ropt_net_144:4 1.81935e-06 +18 chany_top_in[5]:6 ropt_net_144:9 5.765777e-05 + +*RES +0 chany_top_in[5] chany_top_in[5]:6 0.02855804 +1 chany_top_in[5]:2 mux_right_track_12\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[5]:5 chany_top_in[5]:4 0.02090625 +3 chany_top_in[5]:6 chany_top_in[5]:5 0.0045 +4 chany_top_in[5]:4 chany_top_in[5]:3 0.0009107143 +5 chany_top_in[5]:3 chany_top_in[5]:2 0.0003772322 + +*END + +*D_NET chany_top_in[7] 0.007140494 //LENGTH 57.635 LUMPCC 0.001109394 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 68.540 102.070 +*I mux_right_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 79.580 58.140 +*N chany_top_in[7]:2 *C 79.580 58.140 +*N chany_top_in[7]:3 *C 79.580 57.800 +*N chany_top_in[7]:4 *C 70.425 57.800 +*N chany_top_in[7]:5 *C 70.380 57.845 +*N chany_top_in[7]:6 *C 70.380 61.143 +*N chany_top_in[7]:7 *C 70.373 61.200 +*N chany_top_in[7]:8 *C 69.020 61.200 +*N chany_top_in[7]:9 *C 69.000 61.208 +*N chany_top_in[7]:10 *C 69.000 97.913 +*N chany_top_in[7]:11 *C 68.985 97.920 +*N chany_top_in[7]:12 *C 68.543 97.920 +*N chany_top_in[7]:13 *C 68.540 97.978 + +*CAP +0 chany_top_in[7] 0.0002632484 +1 mux_right_track_16\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[7]:2 5.477043e-05 +3 chany_top_in[7]:3 0.0005811654 +4 chany_top_in[7]:4 0.0005541607 +5 chany_top_in[7]:5 0.0002012414 +6 chany_top_in[7]:6 0.0002012414 +7 chany_top_in[7]:7 0.0001769878 +8 chany_top_in[7]:8 0.0001769878 +9 chany_top_in[7]:9 0.001717279 +10 chany_top_in[7]:10 0.001717279 +11 chany_top_in[7]:11 6.12454e-05 +12 chany_top_in[7]:12 6.12454e-05 +13 chany_top_in[7]:13 0.0002632484 +14 chany_top_in[7]:9 chany_top_in[8]:8 0.0004786508 +15 chany_top_in[7]:10 chany_top_in[8]:9 0.0004786508 +16 chany_top_in[7]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.05325e-05 +17 chany_top_in[7]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.451052e-05 +18 chany_top_in[7]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.002883e-06 +19 chany_top_in[7]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.002883e-06 +20 chany_top_in[7]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.451052e-05 +21 chany_top_in[7]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.05325e-05 + +*RES +0 chany_top_in[7] chany_top_in[7]:13 0.003654018 +1 chany_top_in[7]:2 mux_right_track_16\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[7]:4 chany_top_in[7]:3 0.008174108 +3 chany_top_in[7]:5 chany_top_in[7]:4 0.0045 +4 chany_top_in[7]:6 chany_top_in[7]:5 0.002944196 +5 chany_top_in[7]:7 chany_top_in[7]:6 0.00341 +6 chany_top_in[7]:8 chany_top_in[7]:7 0.0002118916 +7 chany_top_in[7]:9 chany_top_in[7]:8 0.00341 +8 chany_top_in[7]:11 chany_top_in[7]:10 0.00341 +9 chany_top_in[7]:10 chany_top_in[7]:9 0.00575045 +10 chany_top_in[7]:13 chany_top_in[7]:12 0.00341 +11 chany_top_in[7]:12 chany_top_in[7]:11 6.499219e-05 +12 chany_top_in[7]:3 chany_top_in[7]:2 0.0003035715 + +*END + +*D_NET chany_top_in[11] 0.00808514 //LENGTH 62.100 LUMPCC 0.0009913109 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 41.860 102.035 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.140 72.420 +*N chany_top_in[11]:2 *C 73.140 72.420 +*N chany_top_in[11]:3 *C 73.140 72.420 +*N chany_top_in[11]:4 *C 73.140 72.760 +*N chany_top_in[11]:5 *C 73.133 72.760 +*N chany_top_in[11]:6 *C 52.460 72.760 +*N chany_top_in[11]:7 *C 52.440 72.767 +*N chany_top_in[11]:8 *C 52.440 99.953 +*N chany_top_in[11]:9 *C 52.420 99.960 +*N chany_top_in[11]:10 *C 41.867 99.960 +*N chany_top_in[11]:11 *C 41.860 100.017 + +*CAP +0 chany_top_in[11] 0.0001254153 +1 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[11]:2 3.368733e-05 +3 chany_top_in[11]:3 5.521252e-05 +4 chany_top_in[11]:4 5.957281e-05 +5 chany_top_in[11]:5 0.001341474 +6 chany_top_in[11]:6 0.001341474 +7 chany_top_in[11]:7 0.001059806 +8 chany_top_in[11]:8 0.001059806 +9 chany_top_in[11]:9 0.000945483 +10 chany_top_in[11]:10 0.000945483 +11 chany_top_in[11]:11 0.0001254153 +12 chany_top_in[11]:7 chany_top_in[15]:15 0.0002493077 +13 chany_top_in[11]:7 chany_top_in[15]:16 8.454915e-05 +14 chany_top_in[11]:8 chany_top_in[15] 8.454915e-05 +15 chany_top_in[11]:8 chany_top_in[15]:16 0.0002493077 +16 chany_top_in[11]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001617986 +17 chany_top_in[11]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001617986 + +*RES +0 chany_top_in[11] chany_top_in[11]:11 0.001801339 +1 chany_top_in[11]:2 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[11]:3 chany_top_in[11]:2 0.0045 +3 chany_top_in[11]:4 chany_top_in[11]:3 0.0001634615 +4 chany_top_in[11]:5 chany_top_in[11]:4 0.00341 +5 chany_top_in[11]:6 chany_top_in[11]:5 0.003238691 +6 chany_top_in[11]:7 chany_top_in[11]:6 0.00341 +7 chany_top_in[11]:9 chany_top_in[11]:8 0.00341 +8 chany_top_in[11]:8 chany_top_in[11]:7 0.004258983 +9 chany_top_in[11]:11 chany_top_in[11]:10 0.00341 +10 chany_top_in[11]:10 chany_top_in[11]:9 0.001653225 + +*END + +*D_NET chanx_right_in[1] 0.007654257 //LENGTH 61.415 LUMPCC 0.00442195 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 111.930 16.320 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 75.270 38.760 +*N chanx_right_in[1]:2 *C 75.233 38.760 +*N chanx_right_in[1]:3 *C 74.565 38.760 +*N chanx_right_in[1]:4 *C 74.520 38.715 +*N chanx_right_in[1]:5 *C 74.520 16.378 +*N chanx_right_in[1]:6 *C 74.528 16.320 + +*CAP +0 chanx_right_in[1] 0.000675361 +1 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[1]:2 7.761272e-05 +3 chanx_right_in[1]:3 7.761272e-05 +4 chanx_right_in[1]:4 0.0008626797 +5 chanx_right_in[1]:5 0.0008626797 +6 chanx_right_in[1]:6 0.000675361 +7 chanx_right_in[1] chanx_right_in[8] 0.0009443256 +8 chanx_right_in[1]:4 chanx_right_in[8]:10 0.0003008346 +9 chanx_right_in[1]:5 chanx_right_in[8]:11 0.0003008346 +10 chanx_right_in[1]:6 chanx_right_in[8]:12 0.0009443256 +11 chanx_right_in[1] chanx_right_in[14] 0.0003725494 +12 chanx_right_in[1] chanx_right_in[14]:23 0.0005932653 +13 chanx_right_in[1]:6 chanx_right_in[14]:22 0.0005932653 +14 chanx_right_in[1]:6 chanx_right_in[14]:23 0.0003725494 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:6 0.005859724 +1 chanx_right_in[1]:2 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[1]:3 chanx_right_in[1]:2 0.0005959822 +3 chanx_right_in[1]:4 chanx_right_in[1]:3 0.0045 +4 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0199442 +5 chanx_right_in[1]:6 chanx_right_in[1]:5 0.00341 + +*END + +*D_NET right_top_grid_pin_43_[0] 0.008449618 //LENGTH 62.930 LUMPCC 0.001649491 DR + +*CONN +*P right_top_grid_pin_43_[0] I *L 0.29796 *C 83.410 99.280 +*I mux_right_track_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.475 93.500 +*I mux_right_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.315 91.460 +*I mux_right_track_26\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.895 82.280 +*I mux_right_track_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 42.150 82.280 +*N right_top_grid_pin_43_[0]:5 *C 42.188 82.280 +*N right_top_grid_pin_43_[0]:6 *C 60.895 82.280 +*N right_top_grid_pin_43_[0]:7 *C 72.635 82.280 +*N right_top_grid_pin_43_[0]:8 *C 72.680 82.325 +*N right_top_grid_pin_43_[0]:9 *C 72.680 91.460 +*N right_top_grid_pin_43_[0]:10 *C 73.095 91.460 +*N right_top_grid_pin_43_[0]:11 *C 73.315 91.460 +*N right_top_grid_pin_43_[0]:12 *C 73.140 91.800 +*N right_top_grid_pin_43_[0]:13 *C 73.140 91.845 +*N right_top_grid_pin_43_[0]:14 *C 71.513 93.500 +*N right_top_grid_pin_43_[0]:15 *C 73.095 93.500 +*N right_top_grid_pin_43_[0]:16 *C 73.140 93.500 +*N right_top_grid_pin_43_[0]:17 *C 73.140 96.502 +*N right_top_grid_pin_43_[0]:18 *C 73.148 96.560 +*N right_top_grid_pin_43_[0]:19 *C 81.873 96.560 +*N right_top_grid_pin_43_[0]:20 *C 81.880 96.618 +*N right_top_grid_pin_43_[0]:21 *C 81.880 99.223 +*N right_top_grid_pin_43_[0]:22 *C 81.888 99.280 + +*CAP +0 right_top_grid_pin_43_[0] 8.831896e-05 +1 mux_right_track_6\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_26\/mux_l1_in_0_:A0 1e-06 +4 mux_right_track_10\/mux_l1_in_0_:A0 1e-06 +5 right_top_grid_pin_43_[0]:5 0.001205711 +6 right_top_grid_pin_43_[0]:6 0.001953167 +7 right_top_grid_pin_43_[0]:7 0.0007202587 +8 right_top_grid_pin_43_[0]:8 0.0003445906 +9 right_top_grid_pin_43_[0]:9 0.0003748942 +10 right_top_grid_pin_43_[0]:10 6.352695e-05 +11 right_top_grid_pin_43_[0]:11 6.663475e-05 +12 right_top_grid_pin_43_[0]:12 7.026031e-05 +13 right_top_grid_pin_43_[0]:13 0.0001303232 +14 right_top_grid_pin_43_[0]:14 7.535884e-05 +15 right_top_grid_pin_43_[0]:15 7.535884e-05 +16 right_top_grid_pin_43_[0]:16 0.000303758 +17 right_top_grid_pin_43_[0]:17 0.0001749263 +18 right_top_grid_pin_43_[0]:18 0.0003826466 +19 right_top_grid_pin_43_[0]:19 0.0003826466 +20 right_top_grid_pin_43_[0]:20 0.0001477138 +21 right_top_grid_pin_43_[0]:21 0.0001477138 +22 right_top_grid_pin_43_[0]:22 8.831896e-05 +23 right_top_grid_pin_43_[0]:17 ropt_net_116:4 1.504661e-05 +24 right_top_grid_pin_43_[0]:13 ropt_net_116:5 1.220514e-05 +25 right_top_grid_pin_43_[0]:13 ropt_net_116:4 3.740286e-06 +26 right_top_grid_pin_43_[0]:8 ropt_net_116:5 0.0002515441 +27 right_top_grid_pin_43_[0]:16 ropt_net_116:5 1.504661e-05 +28 right_top_grid_pin_43_[0]:16 ropt_net_116:4 1.220514e-05 +29 right_top_grid_pin_43_[0]:9 ropt_net_116:4 0.0002515441 +30 right_top_grid_pin_43_[0]:10 ropt_net_116:5 3.740286e-06 +31 right_top_grid_pin_43_[0]:17 mux_tree_tapbuf_size5_1_sram[0]:7 2.055271e-05 +32 right_top_grid_pin_43_[0]:6 mux_tree_tapbuf_size5_1_sram[0]:16 0.0001586414 +33 right_top_grid_pin_43_[0]:7 mux_tree_tapbuf_size5_1_sram[0]:17 0.0001586414 +34 right_top_grid_pin_43_[0]:15 mux_tree_tapbuf_size5_1_sram[0]:9 6.359594e-05 +35 right_top_grid_pin_43_[0]:16 mux_tree_tapbuf_size5_1_sram[0]:8 2.055271e-05 +36 right_top_grid_pin_43_[0]:14 mux_tree_tapbuf_size5_1_sram[0]:10 6.359594e-05 +37 right_top_grid_pin_43_[0]:18 ropt_net_141:6 0.0002994193 +38 right_top_grid_pin_43_[0]:19 ropt_net_141:7 0.0002994193 + +*RES +0 right_top_grid_pin_43_[0] right_top_grid_pin_43_[0]:22 0.000238525 +1 right_top_grid_pin_43_[0]:17 right_top_grid_pin_43_[0]:16 0.002680804 +2 right_top_grid_pin_43_[0]:18 right_top_grid_pin_43_[0]:17 0.00341 +3 right_top_grid_pin_43_[0]:20 right_top_grid_pin_43_[0]:19 0.00341 +4 right_top_grid_pin_43_[0]:19 right_top_grid_pin_43_[0]:18 0.001366917 +5 right_top_grid_pin_43_[0]:21 right_top_grid_pin_43_[0]:20 0.002325893 +6 right_top_grid_pin_43_[0]:22 right_top_grid_pin_43_[0]:21 0.00341 +7 right_top_grid_pin_43_[0]:5 mux_right_track_10\/mux_l1_in_0_:A0 0.152 +8 right_top_grid_pin_43_[0]:12 right_top_grid_pin_43_[0]:11 0.0001847826 +9 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:12 0.0045 +10 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:10 0.000240625 +11 right_top_grid_pin_43_[0]:11 mux_right_track_2\/mux_l1_in_0_:A0 0.152 +12 right_top_grid_pin_43_[0]:6 mux_right_track_26\/mux_l1_in_0_:A0 0.152 +13 right_top_grid_pin_43_[0]:6 right_top_grid_pin_43_[0]:5 0.01670313 +14 right_top_grid_pin_43_[0]:7 right_top_grid_pin_43_[0]:6 0.01048214 +15 right_top_grid_pin_43_[0]:8 right_top_grid_pin_43_[0]:7 0.0045 +16 right_top_grid_pin_43_[0]:15 right_top_grid_pin_43_[0]:14 0.001412946 +17 right_top_grid_pin_43_[0]:16 right_top_grid_pin_43_[0]:15 0.0045 +18 right_top_grid_pin_43_[0]:16 right_top_grid_pin_43_[0]:13 0.001477679 +19 right_top_grid_pin_43_[0]:14 mux_right_track_6\/mux_l1_in_0_:A0 0.152 +20 right_top_grid_pin_43_[0]:9 right_top_grid_pin_43_[0]:8 0.00815625 +21 right_top_grid_pin_43_[0]:10 right_top_grid_pin_43_[0]:9 0.0003705357 + +*END + +*D_NET ropt_net_116 0.003395798 //LENGTH 27.070 LUMPCC 0.0009402239 DR + +*CONN +*I mux_top_track_4\/BUFT_RR_41:X O *L 0 *C 70.840 75.480 +*I ropt_mt_inst_728:A I *L 0.001766 *C 75.900 96.560 +*N ropt_net_116:2 *C 75.862 96.560 +*N ropt_net_116:3 *C 72.265 96.560 +*N ropt_net_116:4 *C 72.220 96.515 +*N ropt_net_116:5 *C 72.220 75.525 +*N ropt_net_116:6 *C 72.175 75.480 +*N ropt_net_116:7 *C 70.877 75.480 + +*CAP +0 mux_top_track_4\/BUFT_RR_41:X 1e-06 +1 ropt_mt_inst_728:A 1e-06 +2 ropt_net_116:2 0.000172477 +3 ropt_net_116:3 0.000172477 +4 ropt_net_116:4 0.0009413988 +5 ropt_net_116:5 0.0009413988 +6 ropt_net_116:6 0.0001129113 +7 ropt_net_116:7 0.0001129113 +8 ropt_net_116:5 chanx_right_in[8]:6 2.762258e-06 +9 ropt_net_116:5 chanx_right_in[8]:10 2.896899e-06 +10 ropt_net_116:3 chanx_right_in[8]:3 7.573859e-05 +11 ropt_net_116:4 chanx_right_in[8]:5 2.762258e-06 +12 ropt_net_116:4 chanx_right_in[8]:9 2.896899e-06 +13 ropt_net_116:2 chanx_right_in[8]:4 7.573859e-05 +14 ropt_net_116:5 right_top_grid_pin_43_[0]:8 0.0002515441 +15 ropt_net_116:5 right_top_grid_pin_43_[0]:10 3.740286e-06 +16 ropt_net_116:5 right_top_grid_pin_43_[0]:13 1.220514e-05 +17 ropt_net_116:5 right_top_grid_pin_43_[0]:16 1.504661e-05 +18 ropt_net_116:4 right_top_grid_pin_43_[0]:9 0.0002515441 +19 ropt_net_116:4 right_top_grid_pin_43_[0]:13 3.740286e-06 +20 ropt_net_116:4 right_top_grid_pin_43_[0]:16 1.220514e-05 +21 ropt_net_116:4 right_top_grid_pin_43_[0]:17 1.504661e-05 +22 ropt_net_116:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 4.950449e-05 +23 ropt_net_116:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.667351e-05 +24 ropt_net_116:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 4.950449e-05 +25 ropt_net_116:2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.667351e-05 + +*RES +0 mux_top_track_4\/BUFT_RR_41:X ropt_net_116:7 0.152 +1 ropt_net_116:7 ropt_net_116:6 0.001158482 +2 ropt_net_116:6 ropt_net_116:5 0.0045 +3 ropt_net_116:5 ropt_net_116:4 0.01874107 +4 ropt_net_116:3 ropt_net_116:2 0.003212054 +5 ropt_net_116:4 ropt_net_116:3 0.0045 +6 ropt_net_116:2 ropt_mt_inst_728:A 0.152 + +*END + +*D_NET chanx_right_out[4] 0.002406174 //LENGTH 22.225 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 103.100 47.940 +*P chanx_right_out[4] O *L 0.7423 *C 111.930 35.360 +*N chanx_right_out[4]:2 *C 109.948 35.360 +*N chanx_right_out[4]:3 *C 109.940 35.418 +*N chanx_right_out[4]:4 *C 109.940 47.895 +*N chanx_right_out[4]:5 *C 109.895 47.940 +*N chanx_right_out[4]:6 *C 103.138 47.940 + +*CAP +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[4] 0.0001498088 +2 chanx_right_out[4]:2 0.0001498088 +3 chanx_right_out[4]:3 0.0006763893 +4 chanx_right_out[4]:4 0.0006763893 +5 chanx_right_out[4]:5 0.0003763886 +6 chanx_right_out[4]:6 0.0003763886 + +*RES +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[4]:6 0.152 +1 chanx_right_out[4]:6 chanx_right_out[4]:5 0.006033482 +2 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +3 chanx_right_out[4]:4 chanx_right_out[4]:3 0.01114063 +4 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +5 chanx_right_out[4]:2 chanx_right_out[4] 0.0003105917 + +*END + +*D_NET chanx_right_out[10] 0.002762423 //LENGTH 22.610 LUMPCC 0 DR + +*CONN +*I mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.940 39.100 +*P chanx_right_out[10] O *L 0.7423 *C 111.930 24.480 +*N chanx_right_out[10]:2 *C 107.648 24.480 +*N chanx_right_out[10]:3 *C 107.640 24.538 +*N chanx_right_out[10]:4 *C 107.640 39.055 +*N chanx_right_out[10]:5 *C 107.618 39.100 +*N chanx_right_out[10]:6 *C 107.218 39.100 +*N chanx_right_out[10]:7 *C 104.978 39.100 + +*CAP +0 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[10] 0.0002907738 +2 chanx_right_out[10]:2 0.0002907738 +3 chanx_right_out[10]:3 0.0008210267 +4 chanx_right_out[10]:4 0.0008210267 +5 chanx_right_out[10]:5 6.373932e-05 +6 chanx_right_out[10]:6 0.0002689109 +7 chanx_right_out[10]:7 0.0002051716 + +*RES +0 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[10]:7 0.152 +1 chanx_right_out[10]:7 chanx_right_out[10]:6 0.002 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.01296206 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.000670925 +6 chanx_right_out[10]:6 chanx_right_out[10]:5 0.0002173913 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[0] 0.002434027 //LENGTH 21.250 LUMPCC 0 DR + +*CONN +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 100.585 58.480 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 95.850 66.300 +*I mux_right_track_22\/mux_l1_in_0_:S I *L 0.00357 *C 96.040 72.420 +*N mux_tree_tapbuf_size2_10_sram[0]:3 *C 96.078 72.420 +*N mux_tree_tapbuf_size2_10_sram[0]:4 *C 97.015 72.420 +*N mux_tree_tapbuf_size2_10_sram[0]:5 *C 97.060 72.375 +*N mux_tree_tapbuf_size2_10_sram[0]:6 *C 95.888 66.300 +*N mux_tree_tapbuf_size2_10_sram[0]:7 *C 97.015 66.300 +*N mux_tree_tapbuf_size2_10_sram[0]:8 *C 97.060 66.300 +*N mux_tree_tapbuf_size2_10_sram[0]:9 *C 97.060 61.585 +*N mux_tree_tapbuf_size2_10_sram[0]:10 *C 97.105 61.540 +*N mux_tree_tapbuf_size2_10_sram[0]:11 *C 100.235 61.540 +*N mux_tree_tapbuf_size2_10_sram[0]:12 *C 100.280 61.495 +*N mux_tree_tapbuf_size2_10_sram[0]:13 *C 100.280 58.525 +*N mux_tree_tapbuf_size2_10_sram[0]:14 *C 100.280 58.480 +*N mux_tree_tapbuf_size2_10_sram[0]:15 *C 100.585 58.480 + +*CAP +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_22\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_10_sram[0]:3 0.0001012539 +4 mux_tree_tapbuf_size2_10_sram[0]:4 0.0001012539 +5 mux_tree_tapbuf_size2_10_sram[0]:5 0.0003233282 +6 mux_tree_tapbuf_size2_10_sram[0]:6 0.0001018757 +7 mux_tree_tapbuf_size2_10_sram[0]:7 0.0001018757 +8 mux_tree_tapbuf_size2_10_sram[0]:8 0.0006033712 +9 mux_tree_tapbuf_size2_10_sram[0]:9 0.0002493843 +10 mux_tree_tapbuf_size2_10_sram[0]:10 0.0001959864 +11 mux_tree_tapbuf_size2_10_sram[0]:11 0.0001959864 +12 mux_tree_tapbuf_size2_10_sram[0]:12 0.0001748061 +13 mux_tree_tapbuf_size2_10_sram[0]:13 0.0001748061 +14 mux_tree_tapbuf_size2_10_sram[0]:14 5.540785e-05 +15 mux_tree_tapbuf_size2_10_sram[0]:15 5.169118e-05 + +*RES +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_10_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_10_sram[0]:6 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_10_sram[0]:7 mux_tree_tapbuf_size2_10_sram[0]:6 0.001006696 +3 mux_tree_tapbuf_size2_10_sram[0]:8 mux_tree_tapbuf_size2_10_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size2_10_sram[0]:8 mux_tree_tapbuf_size2_10_sram[0]:5 0.005424107 +5 mux_tree_tapbuf_size2_10_sram[0]:10 mux_tree_tapbuf_size2_10_sram[0]:9 0.0045 +6 mux_tree_tapbuf_size2_10_sram[0]:9 mux_tree_tapbuf_size2_10_sram[0]:8 0.004209821 +7 mux_tree_tapbuf_size2_10_sram[0]:11 mux_tree_tapbuf_size2_10_sram[0]:10 0.002794643 +8 mux_tree_tapbuf_size2_10_sram[0]:12 mux_tree_tapbuf_size2_10_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_10_sram[0]:14 mux_tree_tapbuf_size2_10_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size2_10_sram[0]:13 mux_tree_tapbuf_size2_10_sram[0]:12 0.002651786 +11 mux_tree_tapbuf_size2_10_sram[0]:15 mux_tree_tapbuf_size2_10_sram[0]:14 0.0001657609 +12 mux_tree_tapbuf_size2_10_sram[0]:4 mux_tree_tapbuf_size2_10_sram[0]:3 0.0008370536 +13 mux_tree_tapbuf_size2_10_sram[0]:5 mux_tree_tapbuf_size2_10_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size2_10_sram[0]:3 mux_right_track_22\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.002929928 //LENGTH 23.452 LUMPCC 0.0004428577 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.290 46.920 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 52.080 45.175 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 45.715 47.940 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 51.935 45.105 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 52.050 45.290 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 45.715 47.940 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 45.540 47.940 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 45.540 47.895 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 45.540 44.925 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 45.585 44.880 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 52.043 44.880 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 52.080 45.175 +*N mux_tree_tapbuf_size2_2_sram[0]:12 *C 51.980 45.560 +*N mux_tree_tapbuf_size2_2_sram[0]:13 *C 59.295 45.560 +*N mux_tree_tapbuf_size2_2_sram[0]:14 *C 59.340 45.605 +*N mux_tree_tapbuf_size2_2_sram[0]:15 *C 59.340 46.875 +*N mux_tree_tapbuf_size2_2_sram[0]:16 *C 59.385 46.920 +*N mux_tree_tapbuf_size2_2_sram[0]:17 *C 61.253 46.920 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 9.531188e-06 +4 mux_tree_tapbuf_size2_2_sram[0]:4 1.159154e-05 +5 mux_tree_tapbuf_size2_2_sram[0]:5 4.563685e-05 +6 mux_tree_tapbuf_size2_2_sram[0]:6 4.990338e-05 +7 mux_tree_tapbuf_size2_2_sram[0]:7 0.0001765605 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.0001765605 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.0002760394 +10 mux_tree_tapbuf_size2_2_sram[0]:10 0.0002967504 +11 mux_tree_tapbuf_size2_2_sram[0]:11 8.053118e-05 +12 mux_tree_tapbuf_size2_2_sram[0]:12 0.0004558677 +13 mux_tree_tapbuf_size2_2_sram[0]:13 0.0004343179 +14 mux_tree_tapbuf_size2_2_sram[0]:14 9.139589e-05 +15 mux_tree_tapbuf_size2_2_sram[0]:15 9.139589e-05 +16 mux_tree_tapbuf_size2_2_sram[0]:16 0.0001439941 +17 mux_tree_tapbuf_size2_2_sram[0]:17 0.0001439941 +18 mux_tree_tapbuf_size2_2_sram[0]:13 top_left_grid_pin_1_[0]:19 4.957177e-05 +19 mux_tree_tapbuf_size2_2_sram[0]:13 top_left_grid_pin_1_[0]:20 5.39535e-06 +20 mux_tree_tapbuf_size2_2_sram[0]:11 top_left_grid_pin_1_[0]:6 6.232662e-07 +21 mux_tree_tapbuf_size2_2_sram[0]:11 top_left_grid_pin_1_[0]:20 2.453795e-07 +22 mux_tree_tapbuf_size2_2_sram[0]:9 top_left_grid_pin_1_[0]:21 8.614145e-05 +23 mux_tree_tapbuf_size2_2_sram[0]:10 top_left_grid_pin_1_[0]:20 8.676472e-05 +24 mux_tree_tapbuf_size2_2_sram[0]:12 top_left_grid_pin_1_[0]:6 2.453795e-07 +25 mux_tree_tapbuf_size2_2_sram[0]:12 top_left_grid_pin_1_[0]:20 4.957177e-05 +26 mux_tree_tapbuf_size2_2_sram[0]:12 top_left_grid_pin_1_[0]:21 5.39535e-06 +27 mux_tree_tapbuf_size2_2_sram[0]:3 top_left_grid_pin_1_[0]:21 4.279071e-07 +28 mux_tree_tapbuf_size2_2_sram[0]:4 top_left_grid_pin_1_[0]:20 4.279071e-07 +29 mux_tree_tapbuf_size2_2_sram[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.79564e-05 +30 mux_tree_tapbuf_size2_2_sram[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.067306e-06 +31 mux_tree_tapbuf_size2_2_sram[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.067306e-06 +32 mux_tree_tapbuf_size2_2_sram[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.79564e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:17 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:17 mux_tree_tapbuf_size2_2_sram[0]:16 0.001667411 +2 mux_tree_tapbuf_size2_2_sram[0]:16 mux_tree_tapbuf_size2_2_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size2_2_sram[0]:15 mux_tree_tapbuf_size2_2_sram[0]:14 0.001133929 +4 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_2_sram[0]:12 0.006531251 +5 mux_tree_tapbuf_size2_2_sram[0]:14 mux_tree_tapbuf_size2_2_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size2_2_sram[0]:11 mux_top_track_8\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.0001271552 +8 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:4 4.956897e-05 +9 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.0045 +10 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.002651786 +11 mux_tree_tapbuf_size2_2_sram[0]:6 mux_tree_tapbuf_size2_2_sram[0]:5 9.51087e-05 +12 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 0.0045 +13 mux_tree_tapbuf_size2_2_sram[0]:5 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.005765625 +15 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_2_sram[0]:11 0.00034375 +16 mux_tree_tapbuf_size2_2_sram[0]:4 mux_tree_tapbuf_size2_2_sram[0]:3 7.77027e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[1] 0.001616294 //LENGTH 13.240 LUMPCC 7.643081e-05 DR + +*CONN +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 99.205 53.040 +*I mux_right_track_20\/mux_l2_in_0_:S I *L 0.00357 *C 103.860 52.750 +*I mem_right_track_20\/FTB_10__31:A I *L 0.001746 *C 105.340 58.480 +*N mux_tree_tapbuf_size2_9_sram[1]:3 *C 105.340 58.465 +*N mux_tree_tapbuf_size2_9_sram[1]:4 *C 105.340 58.140 +*N mux_tree_tapbuf_size2_9_sram[1]:5 *C 105.340 58.095 +*N mux_tree_tapbuf_size2_9_sram[1]:6 *C 105.340 53.085 +*N mux_tree_tapbuf_size2_9_sram[1]:7 *C 105.295 53.040 +*N mux_tree_tapbuf_size2_9_sram[1]:8 *C 103.860 52.750 +*N mux_tree_tapbuf_size2_9_sram[1]:9 *C 103.803 53.040 +*N mux_tree_tapbuf_size2_9_sram[1]:10 *C 99.243 53.040 + +*CAP +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_20\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_20\/FTB_10__31:A 1e-06 +3 mux_tree_tapbuf_size2_9_sram[1]:3 3.606472e-05 +4 mux_tree_tapbuf_size2_9_sram[1]:4 7.184689e-05 +5 mux_tree_tapbuf_size2_9_sram[1]:5 0.0002718298 +6 mux_tree_tapbuf_size2_9_sram[1]:6 0.0002718298 +7 mux_tree_tapbuf_size2_9_sram[1]:7 0.0001004569 +8 mux_tree_tapbuf_size2_9_sram[1]:8 5.295949e-05 +9 mux_tree_tapbuf_size2_9_sram[1]:9 0.0004296187 +10 mux_tree_tapbuf_size2_9_sram[1]:10 0.0003022573 +11 mux_tree_tapbuf_size2_9_sram[1]:5 ropt_net_134:4 3.821541e-05 +12 mux_tree_tapbuf_size2_9_sram[1]:6 ropt_net_134:3 3.821541e-05 + +*RES +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_9_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_9_sram[1]:3 mem_right_track_20\/FTB_10__31:A 0.152 +2 mux_tree_tapbuf_size2_9_sram[1]:4 mux_tree_tapbuf_size2_9_sram[1]:3 0.0001766304 +3 mux_tree_tapbuf_size2_9_sram[1]:5 mux_tree_tapbuf_size2_9_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_9_sram[1]:7 mux_tree_tapbuf_size2_9_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size2_9_sram[1]:6 mux_tree_tapbuf_size2_9_sram[1]:5 0.004473215 +6 mux_tree_tapbuf_size2_9_sram[1]:10 mux_tree_tapbuf_size2_9_sram[1]:9 0.004071429 +7 mux_tree_tapbuf_size2_9_sram[1]:8 mux_right_track_20\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_9_sram[1]:9 mux_tree_tapbuf_size2_9_sram[1]:8 0.000125 +9 mux_tree_tapbuf_size2_9_sram[1]:9 mux_tree_tapbuf_size2_9_sram[1]:7 0.001332589 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[1] 0.004447378 //LENGTH 34.230 LUMPCC 0.0002401043 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 70.225 85.680 +*I mux_right_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 74.880 88.400 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 65.955 77.180 +*I mux_right_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 77.840 77.520 +*N mux_tree_tapbuf_size5_0_sram[1]:4 *C 77.840 77.520 +*N mux_tree_tapbuf_size5_0_sram[1]:5 *C 77.740 77.180 +*N mux_tree_tapbuf_size5_0_sram[1]:6 *C 65.993 77.180 +*N mux_tree_tapbuf_size5_0_sram[1]:7 *C 67.160 77.180 +*N mux_tree_tapbuf_size5_0_sram[1]:8 *C 67.160 77.225 +*N mux_tree_tapbuf_size5_0_sram[1]:9 *C 67.160 85.975 +*N mux_tree_tapbuf_size5_0_sram[1]:10 *C 67.205 86.020 +*N mux_tree_tapbuf_size5_0_sram[1]:11 *C 74.843 88.400 +*N mux_tree_tapbuf_size5_0_sram[1]:12 *C 73.600 88.400 +*N mux_tree_tapbuf_size5_0_sram[1]:13 *C 73.600 88.740 +*N mux_tree_tapbuf_size5_0_sram[1]:14 *C 69.965 88.740 +*N mux_tree_tapbuf_size5_0_sram[1]:15 *C 69.920 88.695 +*N mux_tree_tapbuf_size5_0_sram[1]:16 *C 69.920 86.065 +*N mux_tree_tapbuf_size5_0_sram[1]:17 *C 69.965 86.013 +*N mux_tree_tapbuf_size5_0_sram[1]:18 *C 70.225 85.680 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_2\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[1]:4 6.234976e-05 +5 mux_tree_tapbuf_size5_0_sram[1]:5 0.0006271556 +6 mux_tree_tapbuf_size5_0_sram[1]:6 8.455577e-05 +7 mux_tree_tapbuf_size5_0_sram[1]:7 0.0007165333 +8 mux_tree_tapbuf_size5_0_sram[1]:8 0.000506266 +9 mux_tree_tapbuf_size5_0_sram[1]:9 0.000506266 +10 mux_tree_tapbuf_size5_0_sram[1]:10 0.0002380939 +11 mux_tree_tapbuf_size5_0_sram[1]:11 0.000110417 +12 mux_tree_tapbuf_size5_0_sram[1]:12 0.0001359328 +13 mux_tree_tapbuf_size5_0_sram[1]:13 0.000261537 +14 mux_tree_tapbuf_size5_0_sram[1]:14 0.0002360212 +15 mux_tree_tapbuf_size5_0_sram[1]:15 0.0001928172 +16 mux_tree_tapbuf_size5_0_sram[1]:16 0.0001928172 +17 mux_tree_tapbuf_size5_0_sram[1]:17 0.0002697566 +18 mux_tree_tapbuf_size5_0_sram[1]:18 6.27547e-05 +19 mux_tree_tapbuf_size5_0_sram[1]:7 mux_tree_tapbuf_size5_0_sram[2]:14 0.0001200522 +20 mux_tree_tapbuf_size5_0_sram[1]:5 mux_tree_tapbuf_size5_0_sram[2]:13 0.0001200522 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_0_sram[1]:18 0.152 +1 mux_tree_tapbuf_size5_0_sram[1]:4 mux_right_track_2\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size5_0_sram[1]:9 mux_tree_tapbuf_size5_0_sram[1]:8 0.0078125 +4 mux_tree_tapbuf_size5_0_sram[1]:7 mux_tree_tapbuf_size5_0_sram[1]:6 0.001042411 +5 mux_tree_tapbuf_size5_0_sram[1]:7 mux_tree_tapbuf_size5_0_sram[1]:5 0.009446429 +6 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size5_0_sram[1]:17 mux_tree_tapbuf_size5_0_sram[1]:16 0.0045 +8 mux_tree_tapbuf_size5_0_sram[1]:17 mux_tree_tapbuf_size5_0_sram[1]:10 0.002464286 +9 mux_tree_tapbuf_size5_0_sram[1]:16 mux_tree_tapbuf_size5_0_sram[1]:15 0.002348214 +10 mux_tree_tapbuf_size5_0_sram[1]:14 mux_tree_tapbuf_size5_0_sram[1]:13 0.003245536 +11 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:14 0.0045 +12 mux_tree_tapbuf_size5_0_sram[1]:11 mux_right_track_2\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size5_0_sram[1]:18 mux_tree_tapbuf_size5_0_sram[1]:17 0.0001807065 +14 mux_tree_tapbuf_size5_0_sram[1]:6 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +15 mux_tree_tapbuf_size5_0_sram[1]:5 mux_tree_tapbuf_size5_0_sram[1]:4 0.0003035715 +16 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:12 0.0003035715 +17 mux_tree_tapbuf_size5_0_sram[1]:12 mux_tree_tapbuf_size5_0_sram[1]:11 0.001109375 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004596031 //LENGTH 35.930 LUMPCC 0.0007867023 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 71.475 42.500 +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 50.425 55.600 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 50.425 55.600 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 50.600 55.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 66.700 55.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 66.700 55.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 70.795 55.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 70.840 55.375 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 70.840 42.545 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 70.885 42.500 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 71.438 42.500 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.50753e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0008504868 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0008424407 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002726241 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002457186 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006899285 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0006899285 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.556346e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 7.556346e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size2_5_sram[1]:8 0.000195367 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size2_5_sram[1]:9 8.977884e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_5_sram[1]:4 8.977884e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_5_sram[1]:9 0.000195367 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0001082053 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0001082053 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004933036 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.01145536 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00365625 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004642857 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.014375 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003035715 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002367415 //LENGTH 19.945 LUMPCC 0.000784664 DR + +*CONN +*I mux_right_track_12\/mux_l1_in_0_:X O *L 0 *C 51.235 68.680 +*I mux_right_track_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 51.160 52.700 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.123 52.700 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.725 52.700 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.680 52.745 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.680 68.635 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 49.725 68.680 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 51.198 68.680 + +*CAP +0 mux_right_track_12\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_12\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001094733 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001094733 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000600244 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000600244 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.065782e-05 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.065782e-05 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:170 2.111912e-05 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:233 4.50914e-05 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:236 2.012982e-05 +11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:171 2.111912e-05 +12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:236 4.50914e-05 +13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:237 2.012982e-05 +14 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_1_[0]:22 9.822292e-05 +15 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_1_[0]:23 9.822292e-05 +16 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_5_sram[0]:6 0.0001390477 +17 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_5_sram[0]:8 6.872108e-05 +18 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_5_sram[0]:7 0.0001390477 +19 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_5_sram[0]:3 6.872108e-05 + +*RES +0 mux_right_track_12\/mux_l1_in_0_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_12\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0141875 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00830216 //LENGTH 50.780 LUMPCC 0.004216749 DR + +*CONN +*I mux_right_track_26\/mux_l2_in_0_:X O *L 0 *C 66.985 68.680 +*I mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 105.200 69.555 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 105.200 69.555 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 105.340 69.700 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 105.340 69.655 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 105.340 63.978 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 105.333 63.920 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 66.708 63.920 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 66.700 63.978 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 66.700 68.635 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 66.700 68.680 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 66.985 68.680 + +*CAP +0 mux_right_track_26\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.153678e-05 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.637066e-05 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003193313 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003193313 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001348829 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001348829 +8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000250746 +9 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.000250746 +10 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.336449e-05 +11 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.432777e-05 +12 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[0]:11 0.001014581 +13 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[0]:12 0.0005956556 +14 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[0]:12 0.001014581 +15 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[0]:13 0.0005956556 +16 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:140 5.389054e-06 +17 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:146 6.697077e-06 +18 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:97 5.389054e-06 +19 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:140 6.697077e-06 +20 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:116 3.544477e-05 +21 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:121 0.000105602 +22 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:122 2.415316e-05 +23 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:124 6.673305e-06 +24 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:129 6.673305e-06 +25 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:138 0.0001565351 +26 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:139 0.0001509694 +27 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:102 3.544477e-05 +28 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:116 0.000105602 +29 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:121 2.415316e-05 +30 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:123 6.673305e-06 +31 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:124 6.673305e-06 +32 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:129 0.0001565351 +33 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:138 0.0001509694 + +*RES +0 mux_right_track_26\/mux_l2_in_0_:X mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001548913 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.004158482 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00605125 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005069196 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.880436e-05 +9 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001168232 //LENGTH 9.830 LUMPCC 0.0002018115 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_1_:X O *L 0 *C 77.455 83.640 +*I mux_right_track_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 78.375 91.460 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 78.338 91.460 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 77.325 91.460 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 77.280 91.415 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 77.280 83.685 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 77.280 83.640 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 77.455 83.640 + +*CAP +0 mux_right_track_6\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.390495e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.390495e-05 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003371464 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003371464 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.283051e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.948761e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.994227e-05 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.994227e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.096349e-05 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.096349e-05 + +*RES +0 mux_right_track_6\/mux_l1_in_1_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_6\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009040179 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901787 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.510871e-05 + +*END + +*D_NET ropt_net_134 0.0007782954 //LENGTH 5.890 LUMPCC 7.643081e-05 DR + +*CONN +*I FTB_6__5:X O *L 0 *C 104.420 56.440 +*I ropt_mt_inst_750:A I *L 0.001766 *C 106.260 53.040 +*N ropt_net_134:2 *C 106.260 53.040 +*N ropt_net_134:3 *C 106.260 53.085 +*N ropt_net_134:4 *C 106.260 56.395 +*N ropt_net_134:5 *C 106.260 56.440 +*N ropt_net_134:6 *C 104.458 56.440 + +*CAP +0 FTB_6__5:X 1e-06 +1 ropt_mt_inst_750:A 1e-06 +2 ropt_net_134:2 2.975533e-05 +3 ropt_net_134:3 0.0001740841 +4 ropt_net_134:4 0.0001740841 +5 ropt_net_134:5 0.0001772441 +6 ropt_net_134:6 0.0001446971 +7 ropt_net_134:4 mux_tree_tapbuf_size2_9_sram[1]:5 3.821541e-05 +8 ropt_net_134:3 mux_tree_tapbuf_size2_9_sram[1]:6 3.821541e-05 + +*RES +0 FTB_6__5:X ropt_net_134:6 0.152 +1 ropt_net_134:6 ropt_net_134:5 0.001609375 +2 ropt_net_134:5 ropt_net_134:4 0.0045 +3 ropt_net_134:4 ropt_net_134:3 0.002955357 +4 ropt_net_134:2 ropt_mt_inst_750:A 0.152 +5 ropt_net_134:3 ropt_net_134:2 0.0045 + +*END + +*D_NET ropt_net_144 0.001199663 //LENGTH 11.130 LUMPCC 0.0003087806 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 27.600 97.240 +*I ropt_mt_inst_767:A I *L 0.001766 *C 25.760 99.280 +*N ropt_net_144:2 *C 25.798 99.280 +*N ropt_net_144:3 *C 26.635 99.280 +*N ropt_net_144:4 *C 26.680 99.325 +*N ropt_net_144:5 *C 26.680 101.615 +*N ropt_net_144:6 *C 26.725 101.660 +*N ropt_net_144:7 *C 28.015 101.660 +*N ropt_net_144:8 *C 28.060 101.615 +*N ropt_net_144:9 *C 28.060 97.285 +*N ropt_net_144:10 *C 28.015 97.240 +*N ropt_net_144:11 *C 27.638 97.240 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 ropt_mt_inst_767:A 1e-06 +2 ropt_net_144:2 5.477731e-05 +3 ropt_net_144:3 5.477731e-05 +4 ropt_net_144:4 6.10958e-05 +5 ropt_net_144:5 6.10958e-05 +6 ropt_net_144:6 9.20524e-05 +7 ropt_net_144:7 9.20524e-05 +8 ropt_net_144:8 0.0001895054 +9 ropt_net_144:9 0.0001895054 +10 ropt_net_144:10 4.701048e-05 +11 ropt_net_144:11 4.701048e-05 +12 ropt_net_144:4 chany_top_in[5]:6 1.81935e-06 +13 ropt_net_144:5 chany_top_in[5] 1.81935e-06 +14 ropt_net_144:8 chany_top_in[5] 5.765777e-05 +15 ropt_net_144:9 chany_top_in[5]:6 5.765777e-05 +16 ropt_net_144:2 chany_top_out[1]:4 1.366731e-05 +17 ropt_net_144:3 chany_top_out[1]:5 1.366731e-05 +18 ropt_net_144:4 chany_top_out[1]:3 7.471584e-05 +19 ropt_net_144:5 chany_top_out[1]:2 7.471584e-05 +20 ropt_net_144:8 chany_top_out[1]:2 6.530046e-06 +21 ropt_net_144:9 chany_top_out[1]:3 6.530046e-06 + +*RES +0 ropt_mt_inst_734:X ropt_net_144:11 0.152 +1 ropt_net_144:2 ropt_mt_inst_767:A 0.152 +2 ropt_net_144:3 ropt_net_144:2 0.0007477679 +3 ropt_net_144:4 ropt_net_144:3 0.0045 +4 ropt_net_144:6 ropt_net_144:5 0.0045 +5 ropt_net_144:5 ropt_net_144:4 0.002044643 +6 ropt_net_144:7 ropt_net_144:6 0.001151786 +7 ropt_net_144:8 ropt_net_144:7 0.0045 +8 ropt_net_144:10 ropt_net_144:9 0.0045 +9 ropt_net_144:9 ropt_net_144:8 0.003866072 +10 ropt_net_144:11 ropt_net_144:10 0.0003370536 + +*END + +*D_NET ropt_net_140 0.00160272 //LENGTH 11.945 LUMPCC 0.000120015 DR + +*CONN +*I BUFT_RR_83:X O *L 0 *C 39.365 99.280 +*I ropt_mt_inst_758:A I *L 0.001767 *C 47.380 96.560 +*N ropt_net_140:2 *C 47.343 96.560 +*N ropt_net_140:3 *C 46.965 96.560 +*N ropt_net_140:4 *C 46.920 96.605 +*N ropt_net_140:5 *C 46.920 98.555 +*N ropt_net_140:6 *C 46.875 98.600 +*N ropt_net_140:7 *C 40.020 98.600 +*N ropt_net_140:8 *C 40.020 99.280 +*N ropt_net_140:9 *C 39.403 99.280 + +*CAP +0 BUFT_RR_83:X 1e-06 +1 ropt_mt_inst_758:A 1e-06 +2 ropt_net_140:2 6.395308e-05 +3 ropt_net_140:3 6.395308e-05 +4 ropt_net_140:4 0.0001043037 +5 ropt_net_140:5 0.0001043037 +6 ropt_net_140:6 0.0004678475 +7 ropt_net_140:7 0.0005095337 +8 ropt_net_140:8 0.0001042482 +9 ropt_net_140:9 6.256197e-05 +10 ropt_net_140:4 chany_top_in[19]:7 6.000752e-05 +11 ropt_net_140:5 chany_top_in[19] 6.000752e-05 + +*RES +0 BUFT_RR_83:X ropt_net_140:9 0.152 +1 ropt_net_140:2 ropt_mt_inst_758:A 0.152 +2 ropt_net_140:3 ropt_net_140:2 0.0003370536 +3 ropt_net_140:4 ropt_net_140:3 0.0045 +4 ropt_net_140:6 ropt_net_140:5 0.0045 +5 ropt_net_140:5 ropt_net_140:4 0.001741072 +6 ropt_net_140:9 ropt_net_140:8 0.0005513393 +7 ropt_net_140:8 ropt_net_140:7 0.0006071429 +8 ropt_net_140:7 ropt_net_140:6 0.006120536 + +*END + +*D_NET chanx_right_in[2] 0.01769965 //LENGTH 173.145 LUMPCC 0.00505788 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 111.930 12.240 +*I ropt_mt_inst_734:A I *L 0.001767 *C 26.680 96.560 +*N chanx_right_in[2]:2 *C 26.680 96.560 +*N chanx_right_in[2]:3 *C 26.680 96.605 +*N chanx_right_in[2]:4 *C 26.680 97.183 +*N chanx_right_in[2]:5 *C 26.688 97.240 +*N chanx_right_in[2]:6 *C 35.860 97.240 +*N chanx_right_in[2]:7 *C 35.880 97.233 +*N chanx_right_in[2]:8 *C 35.880 83.835 +*N chanx_right_in[2]:9 *C 35.880 34.008 +*N chanx_right_in[2]:10 *C 35.900 34.000 +*N chanx_right_in[2]:11 *C 52.893 34.000 +*N chanx_right_in[2]:12 *C 52.900 34.000 +*N chanx_right_in[2]:13 *C 52.945 34.000 +*N chanx_right_in[2]:14 *C 57.455 34.000 +*N chanx_right_in[2]:15 *C 57.500 33.955 +*N chanx_right_in[2]:16 *C 57.500 12.298 +*N chanx_right_in[2]:17 *C 57.508 12.240 + +*CAP +0 chanx_right_in[2] 0.001615051 +1 ropt_mt_inst_734:A 1e-06 +2 chanx_right_in[2]:2 3.471043e-05 +3 chanx_right_in[2]:3 5.324486e-05 +4 chanx_right_in[2]:4 5.324486e-05 +5 chanx_right_in[2]:5 0.0007047387 +6 chanx_right_in[2]:6 0.0007047387 +7 chanx_right_in[2]:7 0.0003521923 +8 chanx_right_in[2]:8 0.001821896 +9 chanx_right_in[2]:9 0.001469704 +10 chanx_right_in[2]:10 0.0008191281 +11 chanx_right_in[2]:11 0.0008191281 +12 chanx_right_in[2]:12 3.08277e-05 +13 chanx_right_in[2]:13 0.0002452116 +14 chanx_right_in[2]:14 0.0002452116 +15 chanx_right_in[2]:15 0.001028346 +16 chanx_right_in[2]:16 0.001028346 +17 chanx_right_in[2]:17 0.001615051 +18 chanx_right_in[2]:9 chany_top_in[14]:10 0.0006185351 +19 chanx_right_in[2]:6 chany_top_in[14]:12 7.022938e-05 +20 chanx_right_in[2]:7 chany_top_in[14] 3.505232e-06 +21 chanx_right_in[2]:7 chany_top_in[14]:11 0.0001857312 +22 chanx_right_in[2]:5 chany_top_in[14]:13 7.022938e-05 +23 chanx_right_in[2]:8 chany_top_in[14]:10 0.0001857312 +24 chanx_right_in[2]:8 chany_top_in[14]:11 0.0006185351 +25 chanx_right_in[2]:8 chany_top_in[14]:14 3.505232e-06 +26 chanx_right_in[2] chanx_right_in[4] 0.0001068372 +27 chanx_right_in[2] chanx_right_in[4]:29 0.0003854706 +28 chanx_right_in[2]:17 chanx_right_in[4]:28 0.0003854706 +29 chanx_right_in[2]:17 chanx_right_in[4]:30 0.0001068372 +30 chanx_right_in[2]:9 chanx_right_in[6]:20 0.000309272 +31 chanx_right_in[2]:8 chanx_right_in[6]:19 0.000309272 +32 chanx_right_in[2] chanx_right_in[5] 0.0001035883 +33 chanx_right_in[2] chanx_right_in[5]:7 0.0006204533 +34 chanx_right_in[2]:15 chanx_right_in[5]:4 3.435209e-05 +35 chanx_right_in[2]:16 chanx_right_in[5]:5 3.435209e-05 +36 chanx_right_in[2]:17 chanx_right_in[5]:6 0.0006204533 +37 chanx_right_in[2]:17 chanx_right_in[5]:7 0.0001035883 +38 chanx_right_in[2]:7 BUF_net_57:7 9.096541e-05 +39 chanx_right_in[2]:8 BUF_net_57:8 9.096541e-05 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:17 0.008526191 +1 chanx_right_in[2]:12 chanx_right_in[2]:11 0.00341 +2 chanx_right_in[2]:11 chanx_right_in[2]:10 0.002662158 +3 chanx_right_in[2]:10 chanx_right_in[2]:9 0.00341 +4 chanx_right_in[2]:9 chanx_right_in[2]:8 0.007806308 +5 chanx_right_in[2]:6 chanx_right_in[2]:5 0.001437025 +6 chanx_right_in[2]:7 chanx_right_in[2]:6 0.00341 +7 chanx_right_in[2]:4 chanx_right_in[2]:3 0.000515625 +8 chanx_right_in[2]:5 chanx_right_in[2]:4 0.00341 +9 chanx_right_in[2]:2 ropt_mt_inst_734:A 0.152 +10 chanx_right_in[2]:3 chanx_right_in[2]:2 0.0045 +11 chanx_right_in[2]:13 chanx_right_in[2]:12 0.0045 +12 chanx_right_in[2]:14 chanx_right_in[2]:13 0.004026786 +13 chanx_right_in[2]:15 chanx_right_in[2]:14 0.0045 +14 chanx_right_in[2]:16 chanx_right_in[2]:15 0.01933706 +15 chanx_right_in[2]:17 chanx_right_in[2]:16 0.00341 +16 chanx_right_in[2]:8 chanx_right_in[2]:7 0.002098942 + +*END + +*D_NET chany_top_in[12] 0.004109892 //LENGTH 30.840 LUMPCC 0.000587227 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 72.220 102.035 +*I mux_right_track_26\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.280 83.300 +*N chany_top_in[12]:2 *C 61.318 83.300 +*N chany_top_in[12]:3 *C 66.655 83.300 +*N chany_top_in[12]:4 *C 66.700 83.345 +*N chany_top_in[12]:5 *C 66.700 99.903 +*N chany_top_in[12]:6 *C 66.708 99.960 +*N chany_top_in[12]:7 *C 72.213 99.960 +*N chany_top_in[12]:8 *C 72.220 100.017 + +*CAP +0 chany_top_in[12] 0.0001347865 +1 mux_right_track_26\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[12]:2 0.0003634371 +3 chany_top_in[12]:3 0.0003634371 +4 chany_top_in[12]:4 0.0009370391 +5 chany_top_in[12]:5 0.0009370391 +6 chany_top_in[12]:6 0.0003255696 +7 chany_top_in[12]:7 0.0003255696 +8 chany_top_in[12]:8 0.0001347865 +9 chany_top_in[12]:7 prog_clk[0]:89 0.0002936135 +10 chany_top_in[12]:6 prog_clk[0]:93 0.0002936135 + +*RES +0 chany_top_in[12] chany_top_in[12]:8 0.001801339 +1 chany_top_in[12]:8 chany_top_in[12]:7 0.00341 +2 chany_top_in[12]:7 chany_top_in[12]:6 0.00086245 +3 chany_top_in[12]:5 chany_top_in[12]:4 0.01478348 +4 chany_top_in[12]:6 chany_top_in[12]:5 0.00341 +5 chany_top_in[12]:3 chany_top_in[12]:2 0.004765625 +6 chany_top_in[12]:4 chany_top_in[12]:3 0.0045 +7 chany_top_in[12]:2 mux_right_track_26\/mux_l1_in_0_:A1 0.152 + +*END + +*D_NET top_left_grid_pin_1_[0] 0.01520157 //LENGTH 139.100 LUMPCC 0.0008527784 DR + +*CONN +*P top_left_grid_pin_1_[0] I *L 0.29796 *C 2.300 102.070 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 68.905 41.820 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 74.885 39.780 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.360 45.220 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 38.545 56.100 +*N top_left_grid_pin_1_[0]:5 *C 38.545 56.100 +*N top_left_grid_pin_1_[0]:6 *C 53.360 45.220 +*N top_left_grid_pin_1_[0]:7 *C 74.847 39.780 +*N top_left_grid_pin_1_[0]:8 *C 74.520 39.780 +*N top_left_grid_pin_1_[0]:9 *C 74.520 40.120 +*N top_left_grid_pin_1_[0]:10 *C 69.045 40.120 +*N top_left_grid_pin_1_[0]:11 *C 69.000 40.165 +*N top_left_grid_pin_1_[0]:12 *C 69.000 41.775 +*N top_left_grid_pin_1_[0]:13 *C 68.907 41.820 +*N top_left_grid_pin_1_[0]:14 *C 68.540 41.820 +*N top_left_grid_pin_1_[0]:15 *C 68.540 42.160 +*N top_left_grid_pin_1_[0]:16 *C 57.545 42.160 +*N top_left_grid_pin_1_[0]:17 *C 57.500 42.205 +*N top_left_grid_pin_1_[0]:18 *C 57.500 44.495 +*N top_left_grid_pin_1_[0]:19 *C 57.455 44.540 +*N top_left_grid_pin_1_[0]:20 *C 53.360 44.540 +*N top_left_grid_pin_1_[0]:21 *C 50.185 44.540 +*N top_left_grid_pin_1_[0]:22 *C 50.140 44.585 +*N top_left_grid_pin_1_[0]:23 *C 50.140 56.395 +*N top_left_grid_pin_1_[0]:24 *C 50.095 56.440 +*N top_left_grid_pin_1_[0]:25 *C 38.640 56.440 +*N top_left_grid_pin_1_[0]:26 *C 2.345 56.440 +*N top_left_grid_pin_1_[0]:27 *C 2.300 56.485 + +*CAP +0 top_left_grid_pin_1_[0] 0.001930388 +1 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_1_[0]:5 5.478048e-05 +6 top_left_grid_pin_1_[0]:6 7.433268e-05 +7 top_left_grid_pin_1_[0]:7 4.414569e-05 +8 top_left_grid_pin_1_[0]:8 7.088159e-05 +9 top_left_grid_pin_1_[0]:9 0.0004124588 +10 top_left_grid_pin_1_[0]:10 0.0003857228 +11 top_left_grid_pin_1_[0]:11 0.0001184563 +12 top_left_grid_pin_1_[0]:12 0.0001184563 +13 top_left_grid_pin_1_[0]:13 3.459646e-05 +14 top_left_grid_pin_1_[0]:14 6.083738e-05 +15 top_left_grid_pin_1_[0]:15 0.0005501747 +16 top_left_grid_pin_1_[0]:16 0.0005239337 +17 top_left_grid_pin_1_[0]:17 0.0001458724 +18 top_left_grid_pin_1_[0]:18 0.0001458724 +19 top_left_grid_pin_1_[0]:19 0.000217712 +20 top_left_grid_pin_1_[0]:20 0.000452719 +21 top_left_grid_pin_1_[0]:21 0.0001912067 +22 top_left_grid_pin_1_[0]:22 0.0005704573 +23 top_left_grid_pin_1_[0]:23 0.0005704573 +24 top_left_grid_pin_1_[0]:24 0.0007353947 +25 top_left_grid_pin_1_[0]:25 0.002883942 +26 top_left_grid_pin_1_[0]:26 0.002121605 +27 top_left_grid_pin_1_[0]:27 0.001930388 +28 top_left_grid_pin_1_[0]:16 mux_tree_tapbuf_size2_1_sram[0]:8 0.0001120629 +29 top_left_grid_pin_1_[0]:16 mux_tree_tapbuf_size2_1_sram[0]:9 1.497845e-05 +30 top_left_grid_pin_1_[0]:12 mux_tree_tapbuf_size2_1_sram[0]:10 3.752327e-06 +31 top_left_grid_pin_1_[0]:11 mux_tree_tapbuf_size2_1_sram[0]:11 3.752327e-06 +32 top_left_grid_pin_1_[0]:15 mux_tree_tapbuf_size2_1_sram[0]:9 0.0001120629 +33 top_left_grid_pin_1_[0]:15 mux_tree_tapbuf_size2_1_sram[0]:3 1.497845e-05 +34 top_left_grid_pin_1_[0]:6 mux_tree_tapbuf_size2_2_sram[0]:11 6.232662e-07 +35 top_left_grid_pin_1_[0]:6 mux_tree_tapbuf_size2_2_sram[0]:12 2.453795e-07 +36 top_left_grid_pin_1_[0]:21 mux_tree_tapbuf_size2_2_sram[0]:9 8.614145e-05 +37 top_left_grid_pin_1_[0]:21 mux_tree_tapbuf_size2_2_sram[0]:12 5.39535e-06 +38 top_left_grid_pin_1_[0]:21 mux_tree_tapbuf_size2_2_sram[0]:3 4.279071e-07 +39 top_left_grid_pin_1_[0]:19 mux_tree_tapbuf_size2_2_sram[0]:13 4.957177e-05 +40 top_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_2_sram[0]:13 5.39535e-06 +41 top_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_2_sram[0]:11 2.453795e-07 +42 top_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_2_sram[0]:10 8.676472e-05 +43 top_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_2_sram[0]:12 4.957177e-05 +44 top_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_2_sram[0]:4 4.279071e-07 +45 top_left_grid_pin_1_[0]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.231945e-05 +46 top_left_grid_pin_1_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.648044e-06 +47 top_left_grid_pin_1_[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.231945e-05 +48 top_left_grid_pin_1_[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.648044e-06 +49 top_left_grid_pin_1_[0]:23 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.822292e-05 +50 top_left_grid_pin_1_[0]:22 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.822292e-05 + +*RES +0 top_left_grid_pin_1_[0] top_left_grid_pin_1_[0]:27 0.0407009 +1 top_left_grid_pin_1_[0]:6 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_1_[0]:24 top_left_grid_pin_1_[0]:23 0.0045 +3 top_left_grid_pin_1_[0]:23 top_left_grid_pin_1_[0]:22 0.01054464 +4 top_left_grid_pin_1_[0]:21 top_left_grid_pin_1_[0]:20 0.002834822 +5 top_left_grid_pin_1_[0]:22 top_left_grid_pin_1_[0]:21 0.0045 +6 top_left_grid_pin_1_[0]:26 top_left_grid_pin_1_[0]:25 0.03240626 +7 top_left_grid_pin_1_[0]:27 top_left_grid_pin_1_[0]:26 0.0045 +8 top_left_grid_pin_1_[0]:5 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +9 top_left_grid_pin_1_[0]:19 top_left_grid_pin_1_[0]:18 0.0045 +10 top_left_grid_pin_1_[0]:18 top_left_grid_pin_1_[0]:17 0.002044643 +11 top_left_grid_pin_1_[0]:16 top_left_grid_pin_1_[0]:15 0.009816964 +12 top_left_grid_pin_1_[0]:17 top_left_grid_pin_1_[0]:16 0.0045 +13 top_left_grid_pin_1_[0]:13 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +14 top_left_grid_pin_1_[0]:13 top_left_grid_pin_1_[0]:12 0.0045 +15 top_left_grid_pin_1_[0]:12 top_left_grid_pin_1_[0]:11 0.0014375 +16 top_left_grid_pin_1_[0]:10 top_left_grid_pin_1_[0]:9 0.004888393 +17 top_left_grid_pin_1_[0]:11 top_left_grid_pin_1_[0]:10 0.0045 +18 top_left_grid_pin_1_[0]:7 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +19 top_left_grid_pin_1_[0]:25 top_left_grid_pin_1_[0]:24 0.01022768 +20 top_left_grid_pin_1_[0]:25 top_left_grid_pin_1_[0]:5 0.0003035715 +21 top_left_grid_pin_1_[0]:20 top_left_grid_pin_1_[0]:19 0.00365625 +22 top_left_grid_pin_1_[0]:20 top_left_grid_pin_1_[0]:6 0.0006071429 +23 top_left_grid_pin_1_[0]:15 top_left_grid_pin_1_[0]:14 0.0003035715 +24 top_left_grid_pin_1_[0]:14 top_left_grid_pin_1_[0]:13 0.000328125 +25 top_left_grid_pin_1_[0]:9 top_left_grid_pin_1_[0]:8 0.0003035715 +26 top_left_grid_pin_1_[0]:8 top_left_grid_pin_1_[0]:7 0.0002924108 + +*END + +*D_NET right_top_grid_pin_49_[0] 0.00695647 //LENGTH 57.105 LUMPCC 0.0009369224 DR + +*CONN +*P right_top_grid_pin_49_[0] I *L 0.29796 *C 108.100 74.835 +*I mux_right_track_22\/mux_l1_in_0_:A0 I *L 0.001631 *C 94.935 71.740 +*I mux_right_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 78.565 77.860 +*I mux_right_track_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 79.025 88.740 +*N right_top_grid_pin_49_[0]:4 *C 79.062 88.740 +*N right_top_grid_pin_49_[0]:5 *C 83.215 88.740 +*N right_top_grid_pin_49_[0]:6 *C 83.260 88.695 +*N right_top_grid_pin_49_[0]:7 *C 78.603 77.860 +*N right_top_grid_pin_49_[0]:8 *C 83.215 77.860 +*N right_top_grid_pin_49_[0]:9 *C 83.260 77.860 +*N right_top_grid_pin_49_[0]:10 *C 83.260 71.785 +*N right_top_grid_pin_49_[0]:11 *C 83.305 71.740 +*N right_top_grid_pin_49_[0]:12 *C 94.973 71.740 +*N right_top_grid_pin_49_[0]:13 *C 95.635 71.740 +*N right_top_grid_pin_49_[0]:14 *C 95.680 71.785 +*N right_top_grid_pin_49_[0]:15 *C 95.680 74.415 +*N right_top_grid_pin_49_[0]:16 *C 95.680 74.460 +*N right_top_grid_pin_49_[0]:17 *C 95.680 74.800 +*N right_top_grid_pin_49_[0]:18 *C 108.100 74.800 +*N right_top_grid_pin_49_[0]:19 *C 108.100 74.460 +*N right_top_grid_pin_49_[0]:20 *C 108.100 74.505 + +*CAP +0 right_top_grid_pin_49_[0] 3.471777e-05 +1 mux_right_track_22\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_2\/mux_l2_in_1_:A1 1e-06 +3 mux_right_track_6\/mux_l2_in_1_:A1 1e-06 +4 right_top_grid_pin_49_[0]:4 0.0002692637 +5 right_top_grid_pin_49_[0]:5 0.0002692637 +6 right_top_grid_pin_49_[0]:6 0.0003392558 +7 right_top_grid_pin_49_[0]:7 0.0003052841 +8 right_top_grid_pin_49_[0]:8 0.0003052841 +9 right_top_grid_pin_49_[0]:9 0.0006395211 +10 right_top_grid_pin_49_[0]:10 0.0002728726 +11 right_top_grid_pin_49_[0]:11 0.0007543836 +12 right_top_grid_pin_49_[0]:12 0.0008138524 +13 right_top_grid_pin_49_[0]:13 5.946874e-05 +14 right_top_grid_pin_49_[0]:14 0.0001806599 +15 right_top_grid_pin_49_[0]:15 0.0001806599 +16 right_top_grid_pin_49_[0]:16 5.527577e-05 +17 right_top_grid_pin_49_[0]:17 0.0007156549 +18 right_top_grid_pin_49_[0]:18 0.0007200246 +19 right_top_grid_pin_49_[0]:19 6.638643e-05 +20 right_top_grid_pin_49_[0]:20 3.471777e-05 +21 right_top_grid_pin_49_[0]:10 chany_top_in[1]:4 0.0001620433 +22 right_top_grid_pin_49_[0]:6 chany_top_in[1]:5 0.000306418 +23 right_top_grid_pin_49_[0]:9 chany_top_in[1]:4 0.000306418 +24 right_top_grid_pin_49_[0]:9 chany_top_in[1]:5 0.0001620433 + +*RES +0 right_top_grid_pin_49_[0] right_top_grid_pin_49_[0]:20 0.0002946429 +1 right_top_grid_pin_49_[0]:11 right_top_grid_pin_49_[0]:10 0.0045 +2 right_top_grid_pin_49_[0]:10 right_top_grid_pin_49_[0]:9 0.005424107 +3 right_top_grid_pin_49_[0]:5 right_top_grid_pin_49_[0]:4 0.003707589 +4 right_top_grid_pin_49_[0]:6 right_top_grid_pin_49_[0]:5 0.0045 +5 right_top_grid_pin_49_[0]:4 mux_right_track_6\/mux_l2_in_1_:A1 0.152 +6 right_top_grid_pin_49_[0]:8 right_top_grid_pin_49_[0]:7 0.004118304 +7 right_top_grid_pin_49_[0]:9 right_top_grid_pin_49_[0]:8 0.0045 +8 right_top_grid_pin_49_[0]:9 right_top_grid_pin_49_[0]:6 0.009674108 +9 right_top_grid_pin_49_[0]:7 mux_right_track_2\/mux_l2_in_1_:A1 0.152 +10 right_top_grid_pin_49_[0]:12 mux_right_track_22\/mux_l1_in_0_:A0 0.152 +11 right_top_grid_pin_49_[0]:12 right_top_grid_pin_49_[0]:11 0.01041741 +12 right_top_grid_pin_49_[0]:13 right_top_grid_pin_49_[0]:12 0.0005915179 +13 right_top_grid_pin_49_[0]:14 right_top_grid_pin_49_[0]:13 0.0045 +14 right_top_grid_pin_49_[0]:16 right_top_grid_pin_49_[0]:15 0.0045 +15 right_top_grid_pin_49_[0]:15 right_top_grid_pin_49_[0]:14 0.002348214 +16 right_top_grid_pin_49_[0]:19 right_top_grid_pin_49_[0]:18 0.0003035715 +17 right_top_grid_pin_49_[0]:20 right_top_grid_pin_49_[0]:19 0.0045 +18 right_top_grid_pin_49_[0]:17 right_top_grid_pin_49_[0]:16 0.0003035715 +19 right_top_grid_pin_49_[0]:18 right_top_grid_pin_49_[0]:17 0.01108929 + +*END + +*D_NET ropt_net_119 0.00282515 //LENGTH 24.625 LUMPCC 0.0003157727 DR + +*CONN +*I mux_top_track_24\/BUFT_RR_43:X O *L 0 *C 20.700 91.800 +*I ropt_mt_inst_731:A I *L 0.001766 *C 6.440 99.280 +*N ropt_net_119:2 *C 6.440 99.280 +*N ropt_net_119:3 *C 6.440 99.325 +*N ropt_net_119:4 *C 6.440 99.915 +*N ropt_net_119:5 *C 6.485 99.960 +*N ropt_net_119:6 *C 18.280 99.960 +*N ropt_net_119:7 *C 18.393 99.915 +*N ropt_net_119:8 *C 18.400 99.325 +*N ropt_net_119:9 *C 18.445 99.280 +*N ropt_net_119:10 *C 20.655 99.280 +*N ropt_net_119:11 *C 20.700 99.235 +*N ropt_net_119:12 *C 20.700 91.845 +*N ropt_net_119:13 *C 20.700 91.800 + +*CAP +0 mux_top_track_24\/BUFT_RR_43:X 1e-06 +1 ropt_mt_inst_731:A 1e-06 +2 ropt_net_119:2 3.184985e-05 +3 ropt_net_119:3 4.718081e-05 +4 ropt_net_119:4 4.718081e-05 +5 ropt_net_119:5 0.0006963442 +6 ropt_net_119:6 0.0006963442 +7 ropt_net_119:7 4.214404e-05 +8 ropt_net_119:8 4.214404e-05 +9 ropt_net_119:9 0.0001298778 +10 ropt_net_119:10 0.0001298778 +11 ropt_net_119:11 0.0003053259 +12 ropt_net_119:12 0.0003053259 +13 ropt_net_119:13 3.378117e-05 +14 ropt_net_119:5 chanx_right_in[10]:3 3.658672e-05 +15 ropt_net_119:6 chanx_right_in[10]:2 3.658672e-05 +16 ropt_net_119:11 chanx_right_in[10]:8 0.0001212996 +17 ropt_net_119:12 chanx_right_in[10]:9 0.0001212996 + +*RES +0 mux_top_track_24\/BUFT_RR_43:X ropt_net_119:13 0.152 +1 ropt_net_119:2 ropt_mt_inst_731:A 0.152 +2 ropt_net_119:3 ropt_net_119:2 0.0045 +3 ropt_net_119:5 ropt_net_119:4 0.0045 +4 ropt_net_119:4 ropt_net_119:3 0.0005267857 +5 ropt_net_119:6 ropt_net_119:5 0.01053125 +6 ropt_net_119:7 ropt_net_119:6 0.0045 +7 ropt_net_119:9 ropt_net_119:8 0.0045 +8 ropt_net_119:8 ropt_net_119:7 0.0005267857 +9 ropt_net_119:10 ropt_net_119:9 0.001973214 +10 ropt_net_119:11 ropt_net_119:10 0.0045 +11 ropt_net_119:13 ropt_net_119:12 0.0045 +12 ropt_net_119:12 ropt_net_119:11 0.006598215 + +*END + +*D_NET chanx_right_out[7] 0.0006495906 //LENGTH 4.320 LUMPCC 0 DR + +*CONN +*I mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 109.540 50.320 +*P chanx_right_out[7] O *L 0.7423 *C 111.930 51.680 +*N chanx_right_out[7]:2 *C 109.488 51.680 +*N chanx_right_out[7]:3 *C 109.480 51.623 +*N chanx_right_out[7]:4 *C 109.480 50.365 +*N chanx_right_out[7]:5 *C 109.480 50.320 + +*CAP +0 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[7] 0.0002288567 +2 chanx_right_out[7]:2 0.0002288567 +3 chanx_right_out[7]:3 7.985221e-05 +4 chanx_right_out[7]:4 7.985221e-05 +5 chanx_right_out[7]:5 3.117281e-05 + +*RES +0 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[7]:5 0.152 +1 chanx_right_out[7]:5 chanx_right_out[7]:4 0.0045 +2 chanx_right_out[7]:4 chanx_right_out[7]:3 0.001122768 +3 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +4 chanx_right_out[7]:2 chanx_right_out[7] 0.0003826583 + +*END + +*D_NET chanx_right_out[11] 0.000454306 //LENGTH 3.180 LUMPCC 0 DR + +*CONN +*I mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 109.540 55.420 +*P chanx_right_out[11] O *L 0.7423 *C 111.930 55.760 +*N chanx_right_out[11]:2 *C 109.948 55.760 +*N chanx_right_out[11]:3 *C 109.940 55.760 +*N chanx_right_out[11]:4 *C 109.940 55.420 +*N chanx_right_out[11]:5 *C 109.918 55.420 +*N chanx_right_out[11]:6 *C 109.555 55.420 + +*CAP +0 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[11] 0.0001339208 +2 chanx_right_out[11]:2 0.0001339208 +3 chanx_right_out[11]:3 5.272629e-05 +4 chanx_right_out[11]:4 4.897229e-05 +5 chanx_right_out[11]:5 4.188291e-05 +6 chanx_right_out[11]:6 4.188291e-05 + +*RES +0 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[11]:6 0.152 +1 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +2 chanx_right_out[11]:2 chanx_right_out[11] 0.0003105917 +3 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +4 chanx_right_out[11]:4 chanx_right_out[11]:3 0.0001634615 +5 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0001970109 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.001324649 //LENGTH 10.480 LUMPCC 0 DR + +*CONN +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.945 77.520 +*I mem_right_track_10\/FTB_5__26:A I *L 0.001746 *C 38.180 74.800 +*I mux_right_track_10\/mux_l2_in_0_:S I *L 0.00357 *C 42.680 79.560 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 42.643 79.560 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 39.145 79.560 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 39.100 79.515 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 38.218 74.800 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 39.055 74.800 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 39.100 74.845 +*N mux_tree_tapbuf_size2_4_sram[1]:9 *C 39.100 77.520 +*N mux_tree_tapbuf_size2_4_sram[1]:10 *C 39.100 77.520 +*N mux_tree_tapbuf_size2_4_sram[1]:11 *C 38.945 77.520 + +*CAP +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_10\/FTB_5__26:A 1e-06 +2 mux_right_track_10\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 0.0002654134 +4 mux_tree_tapbuf_size2_4_sram[1]:4 0.0002654134 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.0001062629 +6 mux_tree_tapbuf_size2_4_sram[1]:6 7.723901e-05 +7 mux_tree_tapbuf_size2_4_sram[1]:7 7.723901e-05 +8 mux_tree_tapbuf_size2_4_sram[1]:8 0.0001381119 +9 mux_tree_tapbuf_size2_4_sram[1]:9 0.000273296 +10 mux_tree_tapbuf_size2_4_sram[1]:10 6.198041e-05 +11 mux_tree_tapbuf_size2_4_sram[1]:11 5.669294e-05 + +*RES +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:10 mux_tree_tapbuf_size2_4_sram[1]:9 0.0045 +2 mux_tree_tapbuf_size2_4_sram[1]:9 mux_tree_tapbuf_size2_4_sram[1]:8 0.002388393 +3 mux_tree_tapbuf_size2_4_sram[1]:9 mux_tree_tapbuf_size2_4_sram[1]:5 0.00178125 +4 mux_tree_tapbuf_size2_4_sram[1]:11 mux_tree_tapbuf_size2_4_sram[1]:10 8.423912e-05 +5 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.0007477679 +6 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size2_4_sram[1]:6 mem_right_track_10\/FTB_5__26:A 0.152 +8 mux_tree_tapbuf_size2_4_sram[1]:4 mux_tree_tapbuf_size2_4_sram[1]:3 0.003122768 +9 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size2_4_sram[1]:3 mux_right_track_10\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[0] 0.001872077 //LENGTH 16.085 LUMPCC 0 DR + +*CONN +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 98.745 47.940 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 93.555 53.380 +*I mux_right_track_20\/mux_l1_in_0_:S I *L 0.00357 *C 92.360 56.100 +*N mux_tree_tapbuf_size2_9_sram[0]:3 *C 92.398 56.100 +*N mux_tree_tapbuf_size2_9_sram[0]:4 *C 93.335 56.100 +*N mux_tree_tapbuf_size2_9_sram[0]:5 *C 93.380 56.055 +*N mux_tree_tapbuf_size2_9_sram[0]:6 *C 93.555 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:7 *C 93.380 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:8 *C 93.380 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:9 *C 93.380 50.025 +*N mux_tree_tapbuf_size2_9_sram[0]:10 *C 93.425 49.980 +*N mux_tree_tapbuf_size2_9_sram[0]:11 *C 98.395 49.980 +*N mux_tree_tapbuf_size2_9_sram[0]:12 *C 98.440 49.935 +*N mux_tree_tapbuf_size2_9_sram[0]:13 *C 98.440 47.985 +*N mux_tree_tapbuf_size2_9_sram[0]:14 *C 98.440 47.940 +*N mux_tree_tapbuf_size2_9_sram[0]:15 *C 98.745 47.940 + +*CAP +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_20\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_9_sram[0]:3 8.802101e-05 +4 mux_tree_tapbuf_size2_9_sram[0]:4 8.802101e-05 +5 mux_tree_tapbuf_size2_9_sram[0]:5 0.0001499173 +6 mux_tree_tapbuf_size2_9_sram[0]:6 5.326267e-05 +7 mux_tree_tapbuf_size2_9_sram[0]:7 5.749559e-05 +8 mux_tree_tapbuf_size2_9_sram[0]:8 0.0003527775 +9 mux_tree_tapbuf_size2_9_sram[0]:9 0.0001735971 +10 mux_tree_tapbuf_size2_9_sram[0]:10 0.000284885 +11 mux_tree_tapbuf_size2_9_sram[0]:11 0.000284885 +12 mux_tree_tapbuf_size2_9_sram[0]:12 0.0001217978 +13 mux_tree_tapbuf_size2_9_sram[0]:13 0.0001217978 +14 mux_tree_tapbuf_size2_9_sram[0]:14 4.736821e-05 +15 mux_tree_tapbuf_size2_9_sram[0]:15 4.525116e-05 + +*RES +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_9_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_9_sram[0]:3 mux_right_track_20\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_9_sram[0]:4 mux_tree_tapbuf_size2_9_sram[0]:3 0.0008370536 +3 mux_tree_tapbuf_size2_9_sram[0]:5 mux_tree_tapbuf_size2_9_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_9_sram[0]:7 mux_tree_tapbuf_size2_9_sram[0]:6 9.510869e-05 +5 mux_tree_tapbuf_size2_9_sram[0]:8 mux_tree_tapbuf_size2_9_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_9_sram[0]:8 mux_tree_tapbuf_size2_9_sram[0]:5 0.002388393 +7 mux_tree_tapbuf_size2_9_sram[0]:6 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_9_sram[0]:10 mux_tree_tapbuf_size2_9_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_9_sram[0]:9 mux_tree_tapbuf_size2_9_sram[0]:8 0.002995536 +10 mux_tree_tapbuf_size2_9_sram[0]:11 mux_tree_tapbuf_size2_9_sram[0]:10 0.0044375 +11 mux_tree_tapbuf_size2_9_sram[0]:12 mux_tree_tapbuf_size2_9_sram[0]:11 0.0045 +12 mux_tree_tapbuf_size2_9_sram[0]:14 mux_tree_tapbuf_size2_9_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size2_9_sram[0]:13 mux_tree_tapbuf_size2_9_sram[0]:12 0.001741071 +14 mux_tree_tapbuf_size2_9_sram[0]:15 mux_tree_tapbuf_size2_9_sram[0]:14 0.0001005435 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.003714075 //LENGTH 28.490 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 56.885 93.840 +*I mux_right_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 51.620 89.080 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 48.200 90.830 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 37.895 93.500 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 37.933 93.500 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 39.975 93.500 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 40.020 93.455 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 40.020 91.505 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 40.065 91.460 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 48.300 91.460 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 48.288 90.853 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 51.520 89.080 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 51.520 89.125 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 51.520 90.735 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 51.520 90.780 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 56.535 90.780 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 56.580 90.825 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 56.580 93.795 +*N mux_tree_tapbuf_size3_0_sram[0]:18 *C 56.580 93.840 +*N mux_tree_tapbuf_size3_0_sram[0]:19 *C 56.885 93.840 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_8\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 0.0001818484 +5 mux_tree_tapbuf_size3_0_sram[0]:5 0.0001818484 +6 mux_tree_tapbuf_size3_0_sram[0]:6 0.0001203302 +7 mux_tree_tapbuf_size3_0_sram[0]:7 0.0001203302 +8 mux_tree_tapbuf_size3_0_sram[0]:8 0.0005659814 +9 mux_tree_tapbuf_size3_0_sram[0]:9 0.0006082337 +10 mux_tree_tapbuf_size3_0_sram[0]:10 0.0002598065 +11 mux_tree_tapbuf_size3_0_sram[0]:11 3.550266e-05 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0001369236 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0001369236 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0005606532 +15 mux_tree_tapbuf_size3_0_sram[0]:15 0.0003099834 +16 mux_tree_tapbuf_size3_0_sram[0]:16 0.0001894683 +17 mux_tree_tapbuf_size3_0_sram[0]:17 0.0001894683 +18 mux_tree_tapbuf_size3_0_sram[0]:18 5.855713e-05 +19 mux_tree_tapbuf_size3_0_sram[0]:19 5.42162e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:19 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:8 mux_tree_tapbuf_size3_0_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size3_0_sram[0]:7 mux_tree_tapbuf_size3_0_sram[0]:6 0.001741072 +3 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 0.001823661 +4 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size3_0_sram[0]:4 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.004477679 +7 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0045 +8 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:17 0.0045 +9 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.002651786 +10 mux_tree_tapbuf_size3_0_sram[0]:19 mux_tree_tapbuf_size3_0_sram[0]:18 0.0001657609 +11 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.0045 +12 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:10 0.002886161 +13 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.0014375 +14 mux_tree_tapbuf_size3_0_sram[0]:11 mux_right_track_8\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.0045 +16 mux_tree_tapbuf_size3_0_sram[0]:10 mux_right_track_8\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size3_0_sram[0]:10 mux_tree_tapbuf_size3_0_sram[0]:9 0.0005424108 +18 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.007352679 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.004762762 //LENGTH 34.430 LUMPCC 0.0005447727 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 46.305 72.080 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 50.320 75.140 +*I mux_right_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 64.500 74.510 +*I mux_right_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 67.720 72.760 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 54.640 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 54.602 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 64.470 74.580 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 67.683 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 67.205 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 67.160 72.805 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 67.160 74.075 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 67.115 74.120 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 64.500 74.120 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 64.430 74.440 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 64.500 74.510 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 64.400 75.480 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 50.343 75.168 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 50.355 75.480 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 51.520 75.480 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 51.520 75.435 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 51.520 72.125 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 51.520 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 46.343 72.080 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_0\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_0\/mux_l1_in_1_:S 1e-06 +4 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 0.0002097801 +6 mux_tree_tapbuf_size6_0_sram[0]:6 7.970037e-06 +7 mux_tree_tapbuf_size6_0_sram[0]:7 6.103273e-05 +8 mux_tree_tapbuf_size6_0_sram[0]:8 6.103273e-05 +9 mux_tree_tapbuf_size6_0_sram[0]:9 9.382401e-05 +10 mux_tree_tapbuf_size6_0_sram[0]:10 9.382401e-05 +11 mux_tree_tapbuf_size6_0_sram[0]:11 0.0002180835 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.0002438467 +13 mux_tree_tapbuf_size6_0_sram[0]:13 7.883951e-06 +14 mux_tree_tapbuf_size6_0_sram[0]:14 0.0001269185 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0007480597 +16 mux_tree_tapbuf_size6_0_sram[0]:16 3.031294e-05 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0001134919 +18 mux_tree_tapbuf_size6_0_sram[0]:18 0.0008063677 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0002673261 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0002673261 +21 mux_tree_tapbuf_size6_0_sram[0]:21 0.0005498942 +22 mux_tree_tapbuf_size6_0_sram[0]:22 0.0003060142 +23 mux_tree_tapbuf_size6_0_sram[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002723863 +24 mux_tree_tapbuf_size6_0_sram[0]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002723863 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:16 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.004622768 +3 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.0045 +4 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:5 0.002752232 +5 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.002955357 +6 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.001040179 +7 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:15 0.0115 +8 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.0045 +9 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.001133929 +11 mux_tree_tapbuf_size6_0_sram[0]:8 mux_tree_tapbuf_size6_0_sram[0]:7 0.0004263393 +12 mux_tree_tapbuf_size6_0_sram[0]:9 mux_tree_tapbuf_size6_0_sram[0]:8 0.0045 +13 mux_tree_tapbuf_size6_0_sram[0]:7 mux_right_track_0\/mux_l1_in_1_:S 0.152 +14 mux_tree_tapbuf_size6_0_sram[0]:5 mux_right_track_0\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size6_0_sram[0]:14 mux_right_track_0\/mux_l1_in_2_:S 0.152 +16 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 6.250001e-05 +17 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:12 0.0003482143 +18 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:6 6.25e-05 +19 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.0002111486 +20 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.0008660716 +21 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 0.002334822 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01184049 //LENGTH 86.940 LUMPCC 0.005256938 DR + +*CONN +*I mux_right_track_10\/mux_l2_in_0_:X O *L 0 *C 43.525 79.900 +*I mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 106.060 58.635 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 106.060 58.635 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 105.800 58.480 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 105.800 58.435 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 105.800 57.858 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 105.793 57.800 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 93.075 57.800 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 43.248 57.800 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 43.240 57.858 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 43.240 79.855 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 43.240 79.900 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 43.525 79.900 + +*CAP +0 mux_right_track_10\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.769116e-05 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.278948e-05 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.52219e-05 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.52219e-05 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004585777 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.002383804 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001925226 +9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.000731463 +10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000731463 +11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.066414e-05 +12 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.942784e-05 +13 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_top_in[18] 5.095732e-05 +14 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_top_in[18]:8 5.095732e-05 +15 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_top_in[18]:7 0.001083098 +16 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[18]:5 0.0002296929 +17 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[18]:6 2.219828e-05 +18 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[18]:6 0.001312791 +19 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[18]:7 2.219828e-05 +20 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[19]:9 0.0001220078 +21 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[19]:10 0.0001279319 +22 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[19]:9 0.0001279319 +23 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[19]:10 0.0001220078 +24 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_top_out[0] 0.0006100982 +25 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_top_out[0]:2 0.0006100982 +26 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 optlc_net_112:32 0.0003640312 +27 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_112:31 1.84531e-05 +28 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_112:31 0.0003640312 +29 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_112:32 1.84531e-05 + +*RES +0 mux_right_track_10\/mux_l2_in_0_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001548913 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0045 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.01964063 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.007806308 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000515625 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001413044 +9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001992408 + +*END + +*D_NET mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00186589 //LENGTH 15.665 LUMPCC 0.0001400863 DR + +*CONN +*I mux_right_track_20\/mux_l2_in_0_:X O *L 0 *C 104.705 52.360 +*I mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.320 39.280 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 103.320 39.280 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 103.320 39.780 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 104.835 39.780 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 104.880 39.825 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 104.880 52.315 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 104.880 52.360 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 104.705 52.360 + +*CAP +0 mux_right_track_20\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.277965e-05 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001549422 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001199786 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006404467 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006404467 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.241268e-05 +8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.279723e-05 +9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_135:4 7.004316e-05 +10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_135:5 7.004316e-05 + +*RES +0 mux_right_track_20\/mux_l2_in_0_:X mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.51087e-05 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.01115179 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001352679 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004464286 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001228905 //LENGTH 8.350 LUMPCC 0.0003237051 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_1_:X O *L 0 *C 85.735 71.400 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.195 64.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 86.157 64.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 85.605 64.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 85.560 64.645 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.560 71.355 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 85.560 71.400 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 85.735 71.400 + +*CAP +0 mux_right_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.71198e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.71198e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003087185 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003087185 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.091929e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.060428e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[0]:9 2.523084e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[0]:20 9.786313e-06 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[0]:21 7.628685e-06 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[0]:8 2.523084e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[0]:13 7.628685e-06 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[0]:21 9.786313e-06 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001192067 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001192067 + +*RES +0 mux_right_track_4\/mux_l1_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005991072 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001905178 //LENGTH 15.195 LUMPCC 0.000212356 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_0_:X O *L 0 *C 73.425 94.180 +*I mux_right_track_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 78.760 90.780 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 78.723 90.780 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 76.405 90.780 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 76.360 90.825 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 76.360 95.835 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 76.315 95.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 72.725 95.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 72.680 95.835 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 72.680 94.225 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 72.725 94.180 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 73.388 94.180 + +*CAP +0 mux_right_track_6\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001689921 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001689921 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002803507 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002803507 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002133251 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002133251 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.178197e-05 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 9.178197e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.096134e-05 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:11 9.096134e-05 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 ropt_net_116:2 5.667351e-05 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 ropt_net_116:3 5.667351e-05 +14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 ropt_net_116:4 4.950449e-05 +15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 ropt_net_116:5 4.950449e-05 + +*RES +0 mux_right_track_6\/mux_l1_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_6\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002069197 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004473215 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003205357 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0014375 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0005915179 + +*END + +*D_NET ropt_net_141 0.002273725 //LENGTH 14.330 LUMPCC 0.0005988386 DR + +*CONN +*I ropt_mt_inst_728:X O *L 0 *C 79.775 96.900 +*I ropt_mt_inst_759:A I *L 0.001766 *C 71.300 96.560 +*N ropt_net_141:2 *C 71.300 96.560 +*N ropt_net_141:3 *C 71.300 95.880 +*N ropt_net_141:4 *C 69.965 95.880 +*N ropt_net_141:5 *C 69.920 95.880 +*N ropt_net_141:6 *C 69.928 95.880 +*N ropt_net_141:7 *C 78.193 95.880 +*N ropt_net_141:8 *C 78.200 95.938 +*N ropt_net_141:9 *C 78.200 96.855 +*N ropt_net_141:10 *C 78.245 96.900 +*N ropt_net_141:11 *C 79.737 96.900 + +*CAP +0 ropt_mt_inst_728:X 1e-06 +1 ropt_mt_inst_759:A 1e-06 +2 ropt_net_141:2 8.137862e-05 +3 ropt_net_141:3 0.0001564414 +4 ropt_net_141:4 0.0001067305 +5 ropt_net_141:5 3.891275e-05 +6 ropt_net_141:6 0.0004687411 +7 ropt_net_141:7 0.0004687411 +8 ropt_net_141:8 7.432471e-05 +9 ropt_net_141:9 7.432471e-05 +10 ropt_net_141:10 0.0001016456 +11 ropt_net_141:11 0.0001016456 +12 ropt_net_141:6 right_top_grid_pin_43_[0]:18 0.0002994193 +13 ropt_net_141:7 right_top_grid_pin_43_[0]:19 0.0002994193 + +*RES +0 ropt_mt_inst_728:X ropt_net_141:11 0.152 +1 ropt_net_141:2 ropt_mt_inst_759:A 0.152 +2 ropt_net_141:4 ropt_net_141:3 0.001191964 +3 ropt_net_141:5 ropt_net_141:4 0.0045 +4 ropt_net_141:6 ropt_net_141:5 0.00341 +5 ropt_net_141:8 ropt_net_141:7 0.00341 +6 ropt_net_141:7 ropt_net_141:6 0.00129485 +7 ropt_net_141:10 ropt_net_141:9 0.0045 +8 ropt_net_141:9 ropt_net_141:8 0.0008191965 +9 ropt_net_141:11 ropt_net_141:10 0.001332589 +10 ropt_net_141:3 ropt_net_141:2 0.0006071429 + +*END + +*D_NET chany_top_out[3] 0.001122576 //LENGTH 7.740 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 52.655 98.940 +*P chany_top_out[3] O *L 0.7423 *C 49.220 102.035 +*N chany_top_out[3]:2 *C 49.680 102.000 +*N chany_top_out[3]:3 *C 49.680 101.365 +*N chany_top_out[3]:4 *C 49.725 101.320 +*N chany_top_out[3]:5 *C 51.475 101.320 +*N chany_top_out[3]:6 *C 51.520 101.275 +*N chany_top_out[3]:7 *C 51.520 98.985 +*N chany_top_out[3]:8 *C 51.565 98.940 +*N chany_top_out[3]:9 *C 52.617 98.940 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 chany_top_out[3] 3.239144e-05 +2 chany_top_out[3]:2 9.388163e-05 +3 chany_top_out[3]:3 6.149019e-05 +4 chany_top_out[3]:4 0.000140303 +5 chany_top_out[3]:5 0.000140303 +6 chany_top_out[3]:6 0.0001956021 +7 chany_top_out[3]:7 0.0001956021 +8 chany_top_out[3]:8 0.0001310012 +9 chany_top_out[3]:9 0.0001310012 + +*RES +0 ropt_mt_inst_768:X chany_top_out[3]:9 0.152 +1 chany_top_out[3]:4 chany_top_out[3]:3 0.0045 +2 chany_top_out[3]:3 chany_top_out[3]:2 0.0005669643 +3 chany_top_out[3]:5 chany_top_out[3]:4 0.0015625 +4 chany_top_out[3]:6 chany_top_out[3]:5 0.0045 +5 chany_top_out[3]:8 chany_top_out[3]:7 0.0045 +6 chany_top_out[3]:7 chany_top_out[3]:6 0.002044643 +7 chany_top_out[3]:9 chany_top_out[3]:8 0.0009397322 +8 chany_top_out[3]:2 chany_top_out[3] 0.0004107143 + +*END + +*D_NET ropt_net_125 0.002196998 //LENGTH 15.300 LUMPCC 0.0006430293 DR + +*CONN +*I BUFT_RR_73:X O *L 0 *C 34.960 97.240 +*I ropt_mt_inst_737:A I *L 0.001766 *C 45.540 93.840 +*N ropt_net_125:2 *C 45.503 93.840 +*N ropt_net_125:3 *C 45.125 93.840 +*N ropt_net_125:4 *C 45.080 93.885 +*N ropt_net_125:5 *C 45.080 96.515 +*N ropt_net_125:6 *C 45.080 96.560 +*N ropt_net_125:7 *C 45.045 96.900 +*N ropt_net_125:8 *C 37.260 96.900 +*N ropt_net_125:9 *C 37.260 97.240 +*N ropt_net_125:10 *C 34.998 97.240 + +*CAP +0 BUFT_RR_73:X 1e-06 +1 ropt_mt_inst_737:A 1e-06 +2 ropt_net_125:2 4.219578e-05 +3 ropt_net_125:3 4.219578e-05 +4 ropt_net_125:4 0.0001048423 +5 ropt_net_125:5 0.0001048423 +6 ropt_net_125:6 6.880219e-05 +7 ropt_net_125:7 0.0004067792 +8 ropt_net_125:8 0.000399944 +9 ropt_net_125:9 0.0002040684 +10 ropt_net_125:10 0.0001782985 +11 ropt_net_125:4 chany_top_in[3]:5 7.753567e-05 +12 ropt_net_125:5 chany_top_in[3] 7.753567e-05 +13 ropt_net_125:4 ropt_net_139:9 2.158165e-05 +14 ropt_net_125:5 ropt_net_139:2 2.158165e-05 +15 ropt_net_125:8 ropt_net_139:3 2.753817e-05 +16 ropt_net_125:8 ropt_net_139:7 8.210985e-06 +17 ropt_net_125:7 ropt_net_139:4 2.753817e-05 +18 ropt_net_125:7 ropt_net_139:8 8.210985e-06 +19 ropt_net_125:8 BUF_net_57:3 7.023299e-05 +20 ropt_net_125:7 BUF_net_57:4 7.023299e-05 +21 ropt_net_125:8 chany_top_out[10]:4 0.0001164152 +22 ropt_net_125:7 chany_top_out[10]:3 0.0001164152 + +*RES +0 BUFT_RR_73:X ropt_net_125:10 0.152 +1 ropt_net_125:2 ropt_mt_inst_737:A 0.152 +2 ropt_net_125:3 ropt_net_125:2 0.0003370536 +3 ropt_net_125:4 ropt_net_125:3 0.0045 +4 ropt_net_125:6 ropt_net_125:5 0.0045 +5 ropt_net_125:5 ropt_net_125:4 0.002348214 +6 ropt_net_125:10 ropt_net_125:9 0.002020089 +7 ropt_net_125:9 ropt_net_125:8 0.0003035715 +8 ropt_net_125:8 ropt_net_125:7 0.006950893 +9 ropt_net_125:7 ropt_net_125:6 0.0002297297 + +*END + +*D_NET chanx_right_in[4] 0.01811973 //LENGTH 148.855 LUMPCC 0.005496546 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 111.930 13.600 +*I ropt_mt_inst_739:A I *L 0.001767 *C 51.980 96.560 +*N chanx_right_in[4]:2 *C 52.018 96.560 +*N chanx_right_in[4]:3 *C 54.280 96.560 +*N chanx_right_in[4]:4 *C 54.280 96.220 +*N chanx_right_in[4]:5 *C 57.455 96.220 +*N chanx_right_in[4]:6 *C 57.500 96.175 +*N chanx_right_in[4]:7 *C 57.500 89.125 +*N chanx_right_in[4]:8 *C 57.545 89.080 +*N chanx_right_in[4]:9 *C 58.760 89.080 +*N chanx_right_in[4]:10 *C 58.873 89.035 +*N chanx_right_in[4]:11 *C 58.880 88.445 +*N chanx_right_in[4]:12 *C 58.925 88.400 +*N chanx_right_in[4]:13 *C 59.800 88.400 +*N chanx_right_in[4]:14 *C 59.800 87.720 +*N chanx_right_in[4]:15 *C 63.435 87.720 +*N chanx_right_in[4]:16 *C 63.480 87.675 +*N chanx_right_in[4]:17 *C 63.480 80.780 +*N chanx_right_in[4]:18 *C 63.480 30.985 +*N chanx_right_in[4]:19 *C 63.525 30.940 +*N chanx_right_in[4]:20 *C 80.500 30.940 +*N chanx_right_in[4]:21 *C 80.410 30.600 +*N chanx_right_in[4]:22 *C 80.485 30.645 +*N chanx_right_in[4]:23 *C 80.500 31.250 +*N chanx_right_in[4]:24 *C 80.545 31.280 +*N chanx_right_in[4]:25 *C 84.595 31.280 +*N chanx_right_in[4]:26 *C 84.640 31.235 +*N chanx_right_in[4]:27 *C 84.640 14.338 +*N chanx_right_in[4]:28 *C 84.648 14.280 +*N chanx_right_in[4]:29 *C 108.100 14.280 +*N chanx_right_in[4]:30 *C 108.100 13.600 + +*CAP +0 chanx_right_in[4] 8.415432e-05 +1 ropt_mt_inst_739:A 1e-06 +2 chanx_right_in[4]:2 0.0001030447 +3 chanx_right_in[4]:3 0.0001264355 +4 chanx_right_in[4]:4 0.0001957628 +5 chanx_right_in[4]:5 0.000172372 +6 chanx_right_in[4]:6 0.0004291106 +7 chanx_right_in[4]:7 0.0004291106 +8 chanx_right_in[4]:8 0.0001088714 +9 chanx_right_in[4]:9 0.0001088714 +10 chanx_right_in[4]:10 4.936472e-05 +11 chanx_right_in[4]:11 4.936472e-05 +12 chanx_right_in[4]:12 6.385199e-05 +13 chanx_right_in[4]:13 0.0001070947 +14 chanx_right_in[4]:14 0.0002847078 +15 chanx_right_in[4]:15 0.0002414651 +16 chanx_right_in[4]:16 0.0002769482 +17 chanx_right_in[4]:17 0.002427322 +18 chanx_right_in[4]:18 0.002150374 +19 chanx_right_in[4]:19 0.0008885391 +20 chanx_right_in[4]:20 0.0009160179 +21 chanx_right_in[4]:21 5.849537e-05 +22 chanx_right_in[4]:22 5.318063e-05 +23 chanx_right_in[4]:23 5.318063e-05 +24 chanx_right_in[4]:24 0.0002275124 +25 chanx_right_in[4]:25 0.0002275124 +26 chanx_right_in[4]:26 0.0008105444 +27 chanx_right_in[4]:27 0.0008105444 +28 chanx_right_in[4]:28 0.0004967147 +29 chanx_right_in[4]:29 0.0005421356 +30 chanx_right_in[4]:30 0.0001295751 +31 chanx_right_in[4] chanx_right_in[2] 0.0001068372 +32 chanx_right_in[4]:28 chanx_right_in[2]:17 0.0003854706 +33 chanx_right_in[4]:29 chanx_right_in[2] 0.0003854706 +34 chanx_right_in[4]:30 chanx_right_in[2]:17 0.0001068372 +35 chanx_right_in[4] chanx_right_in[8] 9.380199e-05 +36 chanx_right_in[4]:28 chanx_right_in[8]:12 0.001367598 +37 chanx_right_in[4]:29 chanx_right_in[8] 0.001367598 +38 chanx_right_in[4]:30 chanx_right_in[8]:12 9.380199e-05 +39 chanx_right_in[4]:10 prog_clk[0]:161 2.171605e-07 +40 chanx_right_in[4]:11 prog_clk[0]:158 2.171605e-07 +41 chanx_right_in[4]:16 prog_clk[0]:154 8.461319e-06 +42 chanx_right_in[4]:16 prog_clk[0]:161 1.788461e-05 +43 chanx_right_in[4]:16 prog_clk[0]:150 5.654131e-05 +44 chanx_right_in[4]:18 prog_clk[0]:97 5.324432e-05 +45 chanx_right_in[4]:18 prog_clk[0]:140 0.0001082059 +46 chanx_right_in[4]:18 prog_clk[0]:177 1.436978e-06 +47 chanx_right_in[4]:18 prog_clk[0]:146 2.527315e-05 +48 chanx_right_in[4]:18 prog_clk[0]:149 4.221035e-05 +49 chanx_right_in[4]:17 prog_clk[0]:155 8.461319e-06 +50 chanx_right_in[4]:17 prog_clk[0]:158 1.788461e-05 +51 chanx_right_in[4]:17 prog_clk[0]:140 5.324432e-05 +52 chanx_right_in[4]:17 prog_clk[0]:146 0.0001082059 +53 chanx_right_in[4]:17 prog_clk[0]:149 8.181446e-05 +54 chanx_right_in[4]:17 prog_clk[0]:178 1.436978e-06 +55 chanx_right_in[4]:17 prog_clk[0]:150 4.221035e-05 +56 chanx_right_in[4]:16 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.206902e-05 +57 chanx_right_in[4]:18 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003080229 +58 chanx_right_in[4]:17 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.206902e-05 +59 chanx_right_in[4]:17 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003080229 +60 chanx_right_in[4]:2 ropt_net_120:6 9.027078e-05 +61 chanx_right_in[4]:5 ropt_net_120:7 3.072818e-05 +62 chanx_right_in[4]:3 ropt_net_120:7 9.027078e-05 +63 chanx_right_in[4]:4 ropt_net_120:6 3.072818e-05 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:30 0.0006000333 +1 chanx_right_in[4]:2 ropt_mt_inst_739:A 0.152 +2 chanx_right_in[4]:5 chanx_right_in[4]:4 0.002834822 +3 chanx_right_in[4]:6 chanx_right_in[4]:5 0.0045 +4 chanx_right_in[4]:8 chanx_right_in[4]:7 0.0045 +5 chanx_right_in[4]:7 chanx_right_in[4]:6 0.006294643 +6 chanx_right_in[4]:9 chanx_right_in[4]:8 0.001084822 +7 chanx_right_in[4]:10 chanx_right_in[4]:9 0.0045 +8 chanx_right_in[4]:12 chanx_right_in[4]:11 0.0045 +9 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0005267857 +10 chanx_right_in[4]:15 chanx_right_in[4]:14 0.003245536 +11 chanx_right_in[4]:16 chanx_right_in[4]:15 0.0045 +12 chanx_right_in[4]:19 chanx_right_in[4]:18 0.0045 +13 chanx_right_in[4]:18 chanx_right_in[4]:17 0.04445982 +14 chanx_right_in[4]:21 chanx_right_in[4]:20 0.0003035715 +15 chanx_right_in[4]:22 chanx_right_in[4]:21 0.0045 +16 chanx_right_in[4]:24 chanx_right_in[4]:23 0.0045 +17 chanx_right_in[4]:23 chanx_right_in[4]:22 0.0005401786 +18 chanx_right_in[4]:25 chanx_right_in[4]:24 0.003616072 +19 chanx_right_in[4]:26 chanx_right_in[4]:25 0.0045 +20 chanx_right_in[4]:27 chanx_right_in[4]:26 0.01508705 +21 chanx_right_in[4]:28 chanx_right_in[4]:27 0.00341 +22 chanx_right_in[4]:3 chanx_right_in[4]:2 0.002020089 +23 chanx_right_in[4]:4 chanx_right_in[4]:3 0.0003035715 +24 chanx_right_in[4]:13 chanx_right_in[4]:12 0.00078125 +25 chanx_right_in[4]:14 chanx_right_in[4]:13 0.0006071429 +26 chanx_right_in[4]:20 chanx_right_in[4]:19 0.01515625 +27 chanx_right_in[4]:29 chanx_right_in[4]:28 0.003674225 +28 chanx_right_in[4]:30 chanx_right_in[4]:29 0.0001065333 +29 chanx_right_in[4]:17 chanx_right_in[4]:16 0.00615625 + +*END + +*D_NET chanx_right_in[19] 0.01406251 //LENGTH 100.180 LUMPCC 0.005918222 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 111.930 58.480 +*I BUFT_RR_64:A I *L 0.001776 *C 45.540 88.400 +*N chanx_right_in[19]:2 *C 109.993 61.200 +*N chanx_right_in[19]:3 *C 45.540 88.400 +*N chanx_right_in[19]:4 *C 45.540 88.400 +*N chanx_right_in[19]:5 *C 45.547 88.400 +*N chanx_right_in[19]:6 *C 64.380 88.400 +*N chanx_right_in[19]:7 *C 64.400 88.392 +*N chanx_right_in[19]:8 *C 64.400 60.528 +*N chanx_right_in[19]:9 *C 64.420 60.520 +*N chanx_right_in[19]:10 *C 106.253 60.520 +*N chanx_right_in[19]:11 *C 106.260 60.520 +*N chanx_right_in[19]:12 *C 106.305 60.520 +*N chanx_right_in[19]:13 *C 107.595 60.520 +*N chanx_right_in[19]:14 *C 107.640 60.565 +*N chanx_right_in[19]:15 *C 107.640 61.140 +*N chanx_right_in[19]:16 *C 107.685 61.200 +*N chanx_right_in[19]:17 *C 110.038 61.193 +*N chanx_right_in[19]:18 *C 109.940 61.155 +*N chanx_right_in[19]:19 *C 109.940 58.538 +*N chanx_right_in[19]:20 *C 109.948 58.480 + +*CAP +0 chanx_right_in[19] 0.0001477792 +1 BUFT_RR_64:A 1e-06 +2 chanx_right_in[19]:2 1.816027e-05 +3 chanx_right_in[19]:3 3.482338e-05 +4 chanx_right_in[19]:4 3.173825e-05 +5 chanx_right_in[19]:5 0.0009214972 +6 chanx_right_in[19]:6 0.0009214972 +7 chanx_right_in[19]:7 0.000929223 +8 chanx_right_in[19]:8 0.000929223 +9 chanx_right_in[19]:9 0.001560906 +10 chanx_right_in[19]:10 0.001560906 +11 chanx_right_in[19]:11 3.3195e-05 +12 chanx_right_in[19]:12 9.863754e-05 +13 chanx_right_in[19]:13 9.863754e-05 +14 chanx_right_in[19]:14 5.004424e-05 +15 chanx_right_in[19]:15 5.004424e-05 +16 chanx_right_in[19]:16 0.0001285595 +17 chanx_right_in[19]:17 0.0001467198 +18 chanx_right_in[19]:18 0.0001669601 +19 chanx_right_in[19]:19 0.0001669601 +20 chanx_right_in[19]:20 0.0001477792 +21 chanx_right_in[19]:8 chany_top_in[8]:8 0.0005718758 +22 chanx_right_in[19]:7 chany_top_in[8]:9 0.0005718758 +23 chanx_right_in[19]:10 right_bottom_grid_pin_1_[0]:24 0.0002974173 +24 chanx_right_in[19]:9 right_bottom_grid_pin_1_[0]:23 0.0002974173 +25 chanx_right_in[19]:6 right_bottom_grid_pin_1_[0]:10 0.0005657898 +26 chanx_right_in[19]:5 right_bottom_grid_pin_1_[0]:9 0.0005657898 +27 chanx_right_in[19]:10 optlc_net_112:31 0.0003976299 +28 chanx_right_in[19]:9 optlc_net_112:32 0.0003976299 +29 chanx_right_in[19]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002913626 +30 chanx_right_in[19]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002913626 +31 chanx_right_in[19]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001279319 +32 chanx_right_in[19]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001220078 +33 chanx_right_in[19]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001220078 +34 chanx_right_in[19]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001279319 +35 chanx_right_in[19]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0005850953 +36 chanx_right_in[19]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0005850953 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:20 0.0003105917 +1 chanx_right_in[19]:16 chanx_right_in[19]:15 0.0045 +2 chanx_right_in[19]:15 chanx_right_in[19]:14 0.0005133929 +3 chanx_right_in[19]:13 chanx_right_in[19]:12 0.001151786 +4 chanx_right_in[19]:14 chanx_right_in[19]:13 0.0045 +5 chanx_right_in[19]:12 chanx_right_in[19]:11 0.0045 +6 chanx_right_in[19]:11 chanx_right_in[19]:10 0.00341 +7 chanx_right_in[19]:10 chanx_right_in[19]:9 0.006553758 +8 chanx_right_in[19]:9 chanx_right_in[19]:8 0.00341 +9 chanx_right_in[19]:8 chanx_right_in[19]:7 0.004365516 +10 chanx_right_in[19]:6 chanx_right_in[19]:5 0.002950425 +11 chanx_right_in[19]:7 chanx_right_in[19]:6 0.00341 +12 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +13 chanx_right_in[19]:5 chanx_right_in[19]:4 0.00341 +14 chanx_right_in[19]:3 BUFT_RR_64:A 0.152 +15 chanx_right_in[19]:17 chanx_right_in[19]:16 0.002100446 +16 chanx_right_in[19]:17 chanx_right_in[19]:2 4.017857e-05 +17 chanx_right_in[19]:18 chanx_right_in[19]:17 0.0045 +18 chanx_right_in[19]:19 chanx_right_in[19]:18 0.002337054 +19 chanx_right_in[19]:20 chanx_right_in[19]:19 0.00341 + +*END + +*D_NET chany_top_in[9] 0.01031597 //LENGTH 86.105 LUMPCC 0.0008110697 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 51.980 102.070 +*I mux_right_track_20\/mux_l1_in_0_:A1 I *L 0.00198 *C 91.640 56.100 +*N chany_top_in[9]:2 *C 91.640 56.100 +*N chany_top_in[9]:3 *C 91.540 56.440 +*N chany_top_in[9]:4 *C 52.025 56.440 +*N chany_top_in[9]:5 *C 51.980 56.485 + +*CAP +0 chany_top_in[9] 0.002221777 +1 mux_right_track_20\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[9]:2 5.791475e-05 +3 chany_top_in[9]:3 0.002515207 +4 chany_top_in[9]:4 0.002487224 +5 chany_top_in[9]:5 0.002221777 +6 chany_top_in[9] optlc_net_114:8 0.0002924328 +7 chany_top_in[9] optlc_net_114:19 9.453948e-07 +8 chany_top_in[9]:5 optlc_net_114:9 0.0002924328 +9 chany_top_in[9]:5 optlc_net_114:20 9.453948e-07 +10 chany_top_in[9] BUF_net_62:6 0.0001121567 +11 chany_top_in[9]:5 BUF_net_62:7 0.0001121567 + +*RES +0 chany_top_in[9] chany_top_in[9]:5 0.0407009 +1 chany_top_in[9]:2 mux_right_track_20\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[9]:4 chany_top_in[9]:3 0.03528126 +3 chany_top_in[9]:5 chany_top_in[9]:4 0.0045 +4 chany_top_in[9]:3 chany_top_in[9]:2 0.0003035715 + +*END + +*D_NET chany_top_in[19] 0.004435486 //LENGTH 36.950 LUMPCC 0.0006532174 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 47.380 102.070 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.920 72.420 +*N chany_top_in[19]:2 *C 53.820 72.420 +*N chany_top_in[19]:3 *C 53.820 72.465 +*N chany_top_in[19]:4 *C 53.820 93.103 +*N chany_top_in[19]:5 *C 53.812 93.160 +*N chany_top_in[19]:6 *C 47.388 93.160 +*N chany_top_in[19]:7 *C 47.380 93.218 + +*CAP +0 chany_top_in[19] 0.0004701426 +1 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[19]:2 3.269456e-05 +3 chany_top_in[19]:3 0.0009628178 +4 chany_top_in[19]:4 0.0009628178 +5 chany_top_in[19]:5 0.0004413265 +6 chany_top_in[19]:6 0.0004413265 +7 chany_top_in[19]:7 0.0004701426 +8 chany_top_in[19]:3 BUF_net_62:7 0.0002666012 +9 chany_top_in[19]:4 BUF_net_62:6 0.0002666012 +10 chany_top_in[19] ropt_net_140:5 6.000752e-05 +11 chany_top_in[19]:7 ropt_net_140:4 6.000752e-05 + +*RES +0 chany_top_in[19] chany_top_in[19]:7 0.007904018 +1 chany_top_in[19]:2 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[19]:3 chany_top_in[19]:2 0.0045 +3 chany_top_in[19]:4 chany_top_in[19]:3 0.01842634 +4 chany_top_in[19]:5 chany_top_in[19]:4 0.00341 +5 chany_top_in[19]:7 chany_top_in[19]:6 0.00341 +6 chany_top_in[19]:6 chany_top_in[19]:5 0.001006583 + +*END + +*D_NET right_top_grid_pin_42_[0] 0.01294903 //LENGTH 95.152 LUMPCC 0.00164438 DR + +*CONN +*P right_top_grid_pin_42_[0] I *L 0.29796 *C 109.940 74.870 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.435 70.040 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 53.535 71.400 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 47.095 91.800 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.430 71.740 +*N right_top_grid_pin_42_[0]:5 *C 73.430 71.740 +*N right_top_grid_pin_42_[0]:6 *C 47.095 91.800 +*N right_top_grid_pin_42_[0]:7 *C 47.380 91.800 +*N right_top_grid_pin_42_[0]:8 *C 47.380 91.755 +*N right_top_grid_pin_42_[0]:9 *C 47.380 71.445 +*N right_top_grid_pin_42_[0]:10 *C 47.425 71.400 +*N right_top_grid_pin_42_[0]:11 *C 53.535 71.400 +*N right_top_grid_pin_42_[0]:12 *C 73.430 71.400 +*N right_top_grid_pin_42_[0]:13 *C 74.015 71.400 +*N right_top_grid_pin_42_[0]:14 *C 74.060 71.355 +*N right_top_grid_pin_42_[0]:15 *C 74.060 70.097 +*N right_top_grid_pin_42_[0]:16 *C 74.068 70.040 +*N right_top_grid_pin_42_[0]:17 *C 83.713 70.040 +*N right_top_grid_pin_42_[0]:18 *C 83.435 70.040 +*N right_top_grid_pin_42_[0]:19 *C 83.720 70.040 +*N right_top_grid_pin_42_[0]:20 *C 83.720 70.040 +*N right_top_grid_pin_42_[0]:21 *C 83.720 68.725 +*N right_top_grid_pin_42_[0]:22 *C 83.765 68.680 +*N right_top_grid_pin_42_[0]:23 *C 88.320 68.680 +*N right_top_grid_pin_42_[0]:24 *C 88.320 69.020 +*N right_top_grid_pin_42_[0]:25 *C 109.895 69.020 +*N right_top_grid_pin_42_[0]:26 *C 109.940 69.065 + +*CAP +0 right_top_grid_pin_42_[0] 0.0003628204 +1 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +4 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +5 right_top_grid_pin_42_[0]:5 6.292846e-05 +6 right_top_grid_pin_42_[0]:6 6.016303e-05 +7 right_top_grid_pin_42_[0]:7 6.261491e-05 +8 right_top_grid_pin_42_[0]:8 0.0009949139 +9 right_top_grid_pin_42_[0]:9 0.0009949139 +10 right_top_grid_pin_42_[0]:10 0.0004140622 +11 right_top_grid_pin_42_[0]:11 0.001628348 +12 right_top_grid_pin_42_[0]:12 0.001270265 +13 right_top_grid_pin_42_[0]:13 5.310902e-05 +14 right_top_grid_pin_42_[0]:14 9.868771e-05 +15 right_top_grid_pin_42_[0]:15 9.868771e-05 +16 right_top_grid_pin_42_[0]:16 0.0006200562 +17 right_top_grid_pin_42_[0]:17 0.0006200562 +18 right_top_grid_pin_42_[0]:18 5.561265e-05 +19 right_top_grid_pin_42_[0]:19 6.293027e-05 +20 right_top_grid_pin_42_[0]:20 0.0001286987 +21 right_top_grid_pin_42_[0]:21 9.090102e-05 +22 right_top_grid_pin_42_[0]:22 0.0003331653 +23 right_top_grid_pin_42_[0]:23 0.0003586092 +24 right_top_grid_pin_42_[0]:24 0.001295865 +25 right_top_grid_pin_42_[0]:25 0.001270421 +26 right_top_grid_pin_42_[0]:26 0.0003628204 +27 right_top_grid_pin_42_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.550036e-05 +28 right_top_grid_pin_42_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.550036e-05 +29 right_top_grid_pin_42_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.973927e-05 +30 right_top_grid_pin_42_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.973927e-05 +31 right_top_grid_pin_42_[0]:25 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.749269e-05 +32 right_top_grid_pin_42_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 6.667073e-05 +33 right_top_grid_pin_42_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002025062 +34 right_top_grid_pin_42_[0]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002025062 +35 right_top_grid_pin_42_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 6.667073e-05 +36 right_top_grid_pin_42_[0]:24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.749269e-05 +37 right_top_grid_pin_42_[0]:22 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.945317e-05 +38 right_top_grid_pin_42_[0]:25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002026832 +39 right_top_grid_pin_42_[0]:25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.845085e-05 +40 right_top_grid_pin_42_[0]:19 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.899511e-06 +41 right_top_grid_pin_42_[0]:18 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.899511e-06 +42 right_top_grid_pin_42_[0]:23 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.945317e-05 +43 right_top_grid_pin_42_[0]:24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.845085e-05 +44 right_top_grid_pin_42_[0]:24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002026832 +45 right_top_grid_pin_42_[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.527856e-05 +46 right_top_grid_pin_42_[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.527856e-05 +47 right_top_grid_pin_42_[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.151522e-05 +48 right_top_grid_pin_42_[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.151522e-05 + +*RES +0 right_top_grid_pin_42_[0] right_top_grid_pin_42_[0]:26 0.005183036 +1 right_top_grid_pin_42_[0]:22 right_top_grid_pin_42_[0]:21 0.0045 +2 right_top_grid_pin_42_[0]:21 right_top_grid_pin_42_[0]:20 0.001174107 +3 right_top_grid_pin_42_[0]:25 right_top_grid_pin_42_[0]:24 0.01926339 +4 right_top_grid_pin_42_[0]:26 right_top_grid_pin_42_[0]:25 0.0045 +5 right_top_grid_pin_42_[0]:10 right_top_grid_pin_42_[0]:9 0.0045 +6 right_top_grid_pin_42_[0]:9 right_top_grid_pin_42_[0]:8 0.01813393 +7 right_top_grid_pin_42_[0]:7 right_top_grid_pin_42_[0]:6 0.0001548913 +8 right_top_grid_pin_42_[0]:8 right_top_grid_pin_42_[0]:7 0.0045 +9 right_top_grid_pin_42_[0]:6 mux_right_track_8\/mux_l1_in_0_:A0 0.152 +10 right_top_grid_pin_42_[0]:19 right_top_grid_pin_42_[0]:18 0.0001548913 +11 right_top_grid_pin_42_[0]:20 right_top_grid_pin_42_[0]:19 0.0045 +12 right_top_grid_pin_42_[0]:20 right_top_grid_pin_42_[0]:17 0.00341 +13 right_top_grid_pin_42_[0]:18 mux_right_track_4\/mux_l1_in_0_:A0 0.152 +14 right_top_grid_pin_42_[0]:11 mux_right_track_0\/mux_l1_in_0_:A0 0.152 +15 right_top_grid_pin_42_[0]:11 right_top_grid_pin_42_[0]:10 0.005455357 +16 right_top_grid_pin_42_[0]:5 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +17 right_top_grid_pin_42_[0]:17 right_top_grid_pin_42_[0]:16 0.00151105 +18 right_top_grid_pin_42_[0]:15 right_top_grid_pin_42_[0]:14 0.001122768 +19 right_top_grid_pin_42_[0]:16 right_top_grid_pin_42_[0]:15 0.00341 +20 right_top_grid_pin_42_[0]:13 right_top_grid_pin_42_[0]:12 0.0005223214 +21 right_top_grid_pin_42_[0]:14 right_top_grid_pin_42_[0]:13 0.0045 +22 right_top_grid_pin_42_[0]:12 right_top_grid_pin_42_[0]:11 0.01776339 +23 right_top_grid_pin_42_[0]:12 right_top_grid_pin_42_[0]:5 0.0003035715 +24 right_top_grid_pin_42_[0]:23 right_top_grid_pin_42_[0]:22 0.004066965 +25 right_top_grid_pin_42_[0]:24 right_top_grid_pin_42_[0]:23 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.001321225 //LENGTH 10.325 LUMPCC 0.0002354301 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 41.245 60.860 +*I mem_top_track_24\/FTB_4__25:A I *L 0.001746 *C 40.020 63.920 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 35.980 63.920 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 36.017 63.920 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 36.340 63.920 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 36.340 64.260 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 40.020 64.260 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 40.020 63.920 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 40.020 63.875 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 40.020 60.905 +*N mux_tree_tapbuf_size2_3_sram[1]:10 *C 40.065 60.860 +*N mux_tree_tapbuf_size2_3_sram[1]:11 *C 41.208 60.860 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_24\/FTB_4__25:A 1e-06 +2 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 3.622895e-05 +4 mux_tree_tapbuf_size2_3_sram[1]:4 6.028821e-05 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0001931578 +6 mux_tree_tapbuf_size2_3_sram[1]:6 0.0001980578 +7 mux_tree_tapbuf_size2_3_sram[1]:7 6.299576e-05 +8 mux_tree_tapbuf_size2_3_sram[1]:8 0.0001787543 +9 mux_tree_tapbuf_size2_3_sram[1]:9 0.0001787543 +10 mux_tree_tapbuf_size2_3_sram[1]:10 8.727887e-05 +11 mux_tree_tapbuf_size2_3_sram[1]:11 8.727887e-05 +12 mux_tree_tapbuf_size2_3_sram[1]:5 optlc_net_113:4 0.000117715 +13 mux_tree_tapbuf_size2_3_sram[1]:6 optlc_net_113:5 0.000117715 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:7 mem_top_track_24\/FTB_4__25:A 0.152 +2 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.0003035715 +3 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size2_3_sram[1]:10 mux_tree_tapbuf_size2_3_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 0.002651786 +6 mux_tree_tapbuf_size2_3_sram[1]:11 mux_tree_tapbuf_size2_3_sram[1]:10 0.001020089 +7 mux_tree_tapbuf_size2_3_sram[1]:3 mux_top_track_24\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_3_sram[1]:3 0.0002879465 +9 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.0003035715 +10 mux_tree_tapbuf_size2_3_sram[1]:6 mux_tree_tapbuf_size2_3_sram[1]:5 0.003285714 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_7_ccff_tail[0] 0.0006718266 //LENGTH 4.780 LUMPCC 0.0001526819 DR + +*CONN +*I mem_right_track_16\/FTB_8__29:X O *L 0 *C 80.275 45.220 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 81.595 47.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 *C 81.595 47.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 *C 81.420 47.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 *C 81.420 47.895 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 *C 81.420 45.265 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 *C 81.375 45.220 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 *C 80.312 45.220 + +*CAP +0 mem_right_track_16\/FTB_8__29:X 1e-06 +1 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 5.213027e-05 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 5.472515e-05 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.0001191589 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.0001191589 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 8.598577e-05 +7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 8.598577e-05 +8 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.634096e-05 +9 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.634096e-05 + +*RES +0 mem_right_track_16\/FTB_8__29:X mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 0.0009486608 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.002536733 //LENGTH 22.780 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 58.265 80.240 +*I mux_right_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 62.920 72.760 +*I mem_right_track_0\/FTB_13__34:A I *L 0.001746 *C 61.180 88.400 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 61.180 88.415 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 61.180 88.740 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 61.180 88.695 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 62.883 72.760 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 61.685 72.760 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 61.640 72.805 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 61.640 79.900 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 61.225 79.900 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 61.180 80.255 +*N mux_tree_tapbuf_size6_0_sram[2]:12 *C 61.135 80.240 +*N mux_tree_tapbuf_size6_0_sram[2]:13 *C 58.303 80.240 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_0\/FTB_13__34:A 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 3.548106e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 6.822377e-05 +5 mux_tree_tapbuf_size6_0_sram[2]:5 0.0004639389 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0001126531 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0001126531 +8 mux_tree_tapbuf_size6_0_sram[2]:8 0.000406632 +9 mux_tree_tapbuf_size6_0_sram[2]:9 0.0004349735 +10 mux_tree_tapbuf_size6_0_sram[2]:10 6.188141e-05 +11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0004974788 +12 mux_tree_tapbuf_size6_0_sram[2]:12 0.000169909 +13 mux_tree_tapbuf_size6_0_sram[2]:13 0.000169909 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:4 mux_tree_tapbuf_size6_0_sram[2]:3 0.0001766304 +2 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size6_0_sram[2]:3 mem_right_track_0\/FTB_13__34:A 0.152 +4 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:11 0.0045 +5 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.000221875 +6 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:5 0.007535715 +7 mux_tree_tapbuf_size6_0_sram[2]:13 mux_tree_tapbuf_size6_0_sram[2]:12 0.002529018 +8 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.001069196 +9 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +10 mux_tree_tapbuf_size6_0_sram[2]:6 mux_right_track_0\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.0003705357 +12 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:8 0.006334822 + +*END + +*D_NET optlc_net_114 0.004189457 //LENGTH 33.595 LUMPCC 0.0005867563 DR + +*CONN +*I optlc_109:HI O *L 0 *C 50.140 76.840 +*I mux_right_track_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 41.575 80.580 +*I mux_right_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 52.730 88.060 +*I mux_right_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 56.755 77.180 +*N optlc_net_114:4 *C 56.718 77.180 +*N optlc_net_114:5 *C 51.520 77.180 +*N optlc_net_114:6 *C 52.693 88.060 +*N optlc_net_114:7 *C 51.565 88.060 +*N optlc_net_114:8 *C 51.520 88.015 +*N optlc_net_114:9 *C 51.520 77.565 +*N optlc_net_114:10 *C 51.520 77.490 +*N optlc_net_114:11 *C 41.602 80.558 +*N optlc_net_114:12 *C 41.860 80.545 +*N optlc_net_114:13 *C 41.860 80.240 +*N optlc_net_114:14 *C 44.575 80.240 +*N optlc_net_114:15 *C 44.620 80.195 +*N optlc_net_114:16 *C 44.620 77.565 +*N optlc_net_114:17 *C 44.665 77.520 +*N optlc_net_114:18 *C 50.140 77.520 +*N optlc_net_114:19 *C 50.140 77.475 +*N optlc_net_114:20 *C 50.140 76.885 +*N optlc_net_114:21 *C 50.140 76.840 + +*CAP +0 optlc_109:HI 1e-06 +1 mux_right_track_10\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_8\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_0\/mux_l2_in_1_:A0 1e-06 +4 optlc_net_114:4 0.000381047 +5 optlc_net_114:5 0.0004122614 +6 optlc_net_114:6 8.852766e-05 +7 optlc_net_114:7 8.852766e-05 +8 optlc_net_114:8 0.0003903772 +9 optlc_net_114:9 0.0003903772 +10 optlc_net_114:10 0.000131452 +11 optlc_net_114:11 3.971209e-05 +12 optlc_net_114:12 6.505857e-05 +13 optlc_net_114:13 0.0002231988 +14 optlc_net_114:14 0.0001978524 +15 optlc_net_114:15 0.0001510594 +16 optlc_net_114:16 0.0001510594 +17 optlc_net_114:17 0.0003080863 +18 optlc_net_114:18 0.0004435006 +19 optlc_net_114:19 5.004635e-05 +20 optlc_net_114:20 5.004635e-05 +21 optlc_net_114:21 3.651058e-05 +22 optlc_net_114:9 chany_top_in[9]:5 0.0002924328 +23 optlc_net_114:8 chany_top_in[9] 0.0002924328 +24 optlc_net_114:19 chany_top_in[9] 9.453948e-07 +25 optlc_net_114:20 chany_top_in[9]:5 9.453948e-07 + +*RES +0 optlc_109:HI optlc_net_114:21 0.152 +1 optlc_net_114:10 optlc_net_114:9 0.0045 +2 optlc_net_114:10 optlc_net_114:5 0.0002767857 +3 optlc_net_114:9 optlc_net_114:8 0.009330357 +4 optlc_net_114:7 optlc_net_114:6 0.001006696 +5 optlc_net_114:8 optlc_net_114:7 0.0045 +6 optlc_net_114:6 mux_right_track_8\/mux_l1_in_1_:A0 0.152 +7 optlc_net_114:4 mux_right_track_0\/mux_l2_in_1_:A0 0.152 +8 optlc_net_114:18 optlc_net_114:17 0.004888393 +9 optlc_net_114:18 optlc_net_114:10 0.001232143 +10 optlc_net_114:19 optlc_net_114:18 0.0045 +11 optlc_net_114:21 optlc_net_114:20 0.0045 +12 optlc_net_114:20 optlc_net_114:19 0.0005267857 +13 optlc_net_114:17 optlc_net_114:16 0.0045 +14 optlc_net_114:16 optlc_net_114:15 0.002348214 +15 optlc_net_114:14 optlc_net_114:13 0.002424107 +16 optlc_net_114:15 optlc_net_114:14 0.0045 +17 optlc_net_114:11 mux_right_track_10\/mux_l2_in_0_:A0 0.152 +18 optlc_net_114:12 optlc_net_114:11 0.0001739865 +19 optlc_net_114:13 optlc_net_114:12 0.0002723215 +20 optlc_net_114:5 optlc_net_114:4 0.004640625 + +*END + +*D_NET chanx_right_out[15] 0.0009122883 //LENGTH 7.300 LUMPCC 0.0001447827 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 107.180 41.480 +*P chanx_right_out[15] O *L 0.7423 *C 111.930 39.440 +*N chanx_right_out[15]:2 *C 107.188 39.440 +*N chanx_right_out[15]:3 *C 107.180 39.498 +*N chanx_right_out[15]:4 *C 107.180 41.435 +*N chanx_right_out[15]:5 *C 107.180 41.480 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chanx_right_out[15] 0.0002311454 +2 chanx_right_out[15]:2 0.0002311454 +3 chanx_right_out[15]:3 0.0001362192 +4 chanx_right_out[15]:4 0.0001362192 +5 chanx_right_out[15]:5 3.177635e-05 +6 chanx_right_out[15] ropt_net_146:6 7.201052e-05 +7 chanx_right_out[15]:4 ropt_net_146:14 3.808171e-07 +8 chanx_right_out[15]:3 ropt_net_146:13 3.808171e-07 +9 chanx_right_out[15]:2 ropt_net_146:5 7.201052e-05 + +*RES +0 ropt_mt_inst_761:X chanx_right_out[15]:5 0.152 +1 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +2 chanx_right_out[15]:4 chanx_right_out[15]:3 0.001729911 +3 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +4 chanx_right_out[15]:2 chanx_right_out[15] 0.0007429916 + +*END + +*D_NET chanx_right_out[14] 0.000689945 //LENGTH 5.670 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 107.180 23.460 +*P chanx_right_out[14] O *L 0.7423 *C 111.930 23.120 +*N chanx_right_out[14]:2 *C 110.407 23.120 +*N chanx_right_out[14]:3 *C 110.400 23.120 +*N chanx_right_out[14]:4 *C 110.355 23.120 +*N chanx_right_out[14]:5 *C 107.180 23.120 +*N chanx_right_out[14]:6 *C 107.180 23.460 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 chanx_right_out[14] 0.0001126446 +2 chanx_right_out[14]:2 0.0001126446 +3 chanx_right_out[14]:3 3.108037e-05 +4 chanx_right_out[14]:4 0.000177889 +5 chanx_right_out[14]:5 0.0002033078 +6 chanx_right_out[14]:6 5.137848e-05 + +*RES +0 ropt_mt_inst_748:X chanx_right_out[14]:6 0.152 +1 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +2 chanx_right_out[14]:2 chanx_right_out[14] 0.000238525 +3 chanx_right_out[14]:4 chanx_right_out[14]:3 0.0045 +4 chanx_right_out[14]:6 chanx_right_out[14]:5 0.0003035715 +5 chanx_right_out[14]:5 chanx_right_out[14]:4 0.002834822 + +*END + +*D_NET chanx_right_in[6] 0.01872861 //LENGTH 152.235 LUMPCC 0.002676611 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 111.930 31.280 +*I BUFT_RR_73:A I *L 0.001776 *C 32.660 96.560 +*N chanx_right_in[6]:2 *C 96.043 42.168 +*N chanx_right_in[6]:3 *C 39.770 42.840 +*N chanx_right_in[6]:4 *C 32.698 96.560 +*N chanx_right_in[6]:5 *C 34.915 96.560 +*N chanx_right_in[6]:6 *C 34.960 96.515 +*N chanx_right_in[6]:7 *C 34.960 83.345 +*N chanx_right_in[6]:8 *C 35.005 83.300 +*N chanx_right_in[6]:9 *C 37.720 83.300 +*N chanx_right_in[6]:10 *C 37.645 83.640 +*N chanx_right_in[6]:11 *C 37.712 83.595 +*N chanx_right_in[6]:12 *C 37.720 83.005 +*N chanx_right_in[6]:13 *C 37.765 82.960 +*N chanx_right_in[6]:14 *C 38.595 82.960 +*N chanx_right_in[6]:15 *C 38.640 82.915 +*N chanx_right_in[6]:16 *C 38.640 81.657 +*N chanx_right_in[6]:17 *C 38.648 81.600 +*N chanx_right_in[6]:18 *C 40.460 81.600 +*N chanx_right_in[6]:19 *C 40.480 81.593 +*N chanx_right_in[6]:20 *C 40.480 42.848 +*N chanx_right_in[6]:21 *C 40.477 42.840 +*N chanx_right_in[6]:22 *C 40.480 42.840 +*N chanx_right_in[6]:23 *C 40.525 42.840 +*N chanx_right_in[6]:24 *C 90.320 42.840 +*N chanx_right_in[6]:25 *C 95.680 42.840 +*N chanx_right_in[6]:26 *C 95.680 42.795 +*N chanx_right_in[6]:27 *C 95.680 42.220 +*N chanx_right_in[6]:28 *C 95.680 42.163 +*N chanx_right_in[6]:29 *C 95.680 41.820 +*N chanx_right_in[6]:30 *C 98.440 41.820 +*N chanx_right_in[6]:31 *C 98.440 42.160 +*N chanx_right_in[6]:32 *C 98.440 42.115 +*N chanx_right_in[6]:33 *C 98.440 31.338 +*N chanx_right_in[6]:34 *C 98.448 31.280 + +*CAP +0 chanx_right_in[6] 0.0005738193 +1 BUFT_RR_73:A 1e-06 +2 chanx_right_in[6]:2 3.162851e-05 +3 chanx_right_in[6]:3 8.196529e-05 +4 chanx_right_in[6]:4 0.0001407594 +5 chanx_right_in[6]:5 0.0001407594 +6 chanx_right_in[6]:6 0.0007240334 +7 chanx_right_in[6]:7 0.0007240334 +8 chanx_right_in[6]:8 0.0001781682 +9 chanx_right_in[6]:9 0.0002052149 +10 chanx_right_in[6]:10 5.856135e-05 +11 chanx_right_in[6]:11 5.928718e-05 +12 chanx_right_in[6]:12 5.928718e-05 +13 chanx_right_in[6]:13 6.844095e-05 +14 chanx_right_in[6]:14 6.844095e-05 +15 chanx_right_in[6]:15 8.662229e-05 +16 chanx_right_in[6]:16 8.662229e-05 +17 chanx_right_in[6]:17 0.0001405167 +18 chanx_right_in[6]:18 0.0001405167 +19 chanx_right_in[6]:19 0.001894665 +20 chanx_right_in[6]:20 0.001894665 +21 chanx_right_in[6]:21 8.196529e-05 +22 chanx_right_in[6]:22 3.356746e-05 +23 chanx_right_in[6]:23 0.002871851 +24 chanx_right_in[6]:24 0.003212753 +25 chanx_right_in[6]:25 0.0003695549 +26 chanx_right_in[6]:26 6.151671e-05 +27 chanx_right_in[6]:27 6.151671e-05 +28 chanx_right_in[6]:28 5.591234e-05 +29 chanx_right_in[6]:29 0.0001879421 +30 chanx_right_in[6]:30 0.0001904703 +31 chanx_right_in[6]:31 5.774445e-05 +32 chanx_right_in[6]:32 0.0004671869 +33 chanx_right_in[6]:33 0.0004671869 +34 chanx_right_in[6]:34 0.0005738193 +35 chanx_right_in[6]:20 chanx_right_in[2]:9 0.000309272 +36 chanx_right_in[6]:19 chanx_right_in[2]:8 0.000309272 +37 chanx_right_in[6] chanx_right_in[11] 6.700887e-05 +38 chanx_right_in[6] chanx_right_in[11]:20 0.0002990376 +39 chanx_right_in[6]:32 chanx_right_in[11]:13 7.420901e-05 +40 chanx_right_in[6]:33 chanx_right_in[11]:14 7.420901e-05 +41 chanx_right_in[6]:34 chanx_right_in[11]:19 0.0002990376 +42 chanx_right_in[6]:34 chanx_right_in[11]:21 6.700887e-05 +43 chanx_right_in[6]:23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.585442e-05 +44 chanx_right_in[6]:24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.585442e-05 +45 chanx_right_in[6]:25 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.200155e-05 +46 chanx_right_in[6]:23 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.32815e-05 +47 chanx_right_in[6]:24 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.200155e-05 +48 chanx_right_in[6]:24 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.32815e-05 +49 chanx_right_in[6]:23 optlc_net_115:7 0.0003298145 +50 chanx_right_in[6]:23 optlc_net_115:27 2.275412e-05 +51 chanx_right_in[6]:23 optlc_net_115:8 0.000115072 +52 chanx_right_in[6]:24 optlc_net_115:28 2.275412e-05 +53 chanx_right_in[6]:24 optlc_net_115:27 0.000115072 +54 chanx_right_in[6]:24 optlc_net_115:8 0.0003298145 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:34 0.002112258 +1 chanx_right_in[6]:31 chanx_right_in[6]:30 0.0003035715 +2 chanx_right_in[6]:32 chanx_right_in[6]:31 0.0045 +3 chanx_right_in[6]:33 chanx_right_in[6]:32 0.009622768 +4 chanx_right_in[6]:34 chanx_right_in[6]:33 0.00341 +5 chanx_right_in[6]:28 chanx_right_in[6]:27 0.0045 +6 chanx_right_in[6]:28 chanx_right_in[6]:2 0.0002923388 +7 chanx_right_in[6]:27 chanx_right_in[6]:26 0.0005133929 +8 chanx_right_in[6]:25 chanx_right_in[6]:24 0.004785715 +9 chanx_right_in[6]:26 chanx_right_in[6]:25 0.0045 +10 chanx_right_in[6]:23 chanx_right_in[6]:22 0.0045 +11 chanx_right_in[6]:22 chanx_right_in[6]:21 0.00341 +12 chanx_right_in[6]:21 chanx_right_in[6]:20 0.00341 +13 chanx_right_in[6]:21 chanx_right_in[6]:3 0.0001039141 +14 chanx_right_in[6]:20 chanx_right_in[6]:19 0.006070049 +15 chanx_right_in[6]:18 chanx_right_in[6]:17 0.0002839583 +16 chanx_right_in[6]:19 chanx_right_in[6]:18 0.00341 +17 chanx_right_in[6]:16 chanx_right_in[6]:15 0.001122768 +18 chanx_right_in[6]:17 chanx_right_in[6]:16 0.00341 +19 chanx_right_in[6]:14 chanx_right_in[6]:13 0.0007410715 +20 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0045 +21 chanx_right_in[6]:13 chanx_right_in[6]:12 0.0045 +22 chanx_right_in[6]:12 chanx_right_in[6]:11 0.0005267857 +23 chanx_right_in[6]:10 chanx_right_in[6]:9 0.0003035715 +24 chanx_right_in[6]:11 chanx_right_in[6]:10 0.0045 +25 chanx_right_in[6]:8 chanx_right_in[6]:7 0.0045 +26 chanx_right_in[6]:7 chanx_right_in[6]:6 0.01175893 +27 chanx_right_in[6]:5 chanx_right_in[6]:4 0.001979911 +28 chanx_right_in[6]:6 chanx_right_in[6]:5 0.0045 +29 chanx_right_in[6]:4 BUFT_RR_73:A 0.152 +30 chanx_right_in[6]:9 chanx_right_in[6]:8 0.002424107 +31 chanx_right_in[6]:29 chanx_right_in[6]:28 0.0003058036 +32 chanx_right_in[6]:30 chanx_right_in[6]:29 0.002464286 +33 chanx_right_in[6]:24 chanx_right_in[6]:23 0.04445983 + +*END + +*D_NET right_top_grid_pin_48_[0] 0.01051525 //LENGTH 73.130 LUMPCC 0.001903245 DR + +*CONN +*P right_top_grid_pin_48_[0] I *L 0.29796 *C 107.180 74.835 +*I mux_right_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 84.180 58.140 +*I mux_right_track_20\/mux_l1_in_0_:A0 I *L 0.001631 *C 91.255 55.420 +*I mux_right_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 65.225 74.460 +*N right_top_grid_pin_48_[0]:4 *C 65.263 74.460 +*N right_top_grid_pin_48_[0]:5 *C 68.035 74.460 +*N right_top_grid_pin_48_[0]:6 *C 68.080 74.460 +*N right_top_grid_pin_48_[0]:7 *C 68.080 74.120 +*N right_top_grid_pin_48_[0]:8 *C 68.088 74.120 +*N right_top_grid_pin_48_[0]:9 *C 91.218 55.420 +*N right_top_grid_pin_48_[0]:10 *C 90.665 55.420 +*N right_top_grid_pin_48_[0]:11 *C 90.620 55.465 +*N right_top_grid_pin_48_[0]:12 *C 84.218 58.140 +*N right_top_grid_pin_48_[0]:13 *C 90.575 58.140 +*N right_top_grid_pin_48_[0]:14 *C 90.620 58.140 +*N right_top_grid_pin_48_[0]:15 *C 90.620 74.062 +*N right_top_grid_pin_48_[0]:16 *C 90.620 74.127 +*N right_top_grid_pin_48_[0]:17 *C 90.620 74.800 +*N right_top_grid_pin_48_[0]:18 *C 99.820 74.800 +*N right_top_grid_pin_48_[0]:19 *C 99.820 74.120 +*N right_top_grid_pin_48_[0]:20 *C 107.172 74.120 +*N right_top_grid_pin_48_[0]:21 *C 107.180 74.178 + +*CAP +0 right_top_grid_pin_48_[0] 5.706579e-05 +1 mux_right_track_4\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_20\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_48_[0]:4 0.00021894 +5 right_top_grid_pin_48_[0]:5 0.00021894 +6 right_top_grid_pin_48_[0]:6 5.596051e-05 +7 right_top_grid_pin_48_[0]:7 6.016527e-05 +8 right_top_grid_pin_48_[0]:8 0.001591305 +9 right_top_grid_pin_48_[0]:9 5.389281e-05 +10 right_top_grid_pin_48_[0]:10 5.389281e-05 +11 right_top_grid_pin_48_[0]:11 0.0001527269 +12 right_top_grid_pin_48_[0]:12 0.0004072127 +13 right_top_grid_pin_48_[0]:13 0.0004072127 +14 right_top_grid_pin_48_[0]:14 0.001031271 +15 right_top_grid_pin_48_[0]:15 0.0008461382 +16 right_top_grid_pin_48_[0]:16 0.00163558 +17 right_top_grid_pin_48_[0]:17 0.0004534207 +18 right_top_grid_pin_48_[0]:18 0.0004530698 +19 right_top_grid_pin_48_[0]:19 0.0004495324 +20 right_top_grid_pin_48_[0]:20 0.0004056084 +21 right_top_grid_pin_48_[0]:21 5.706579e-05 +22 right_top_grid_pin_48_[0]:8 chanx_right_in[17]:14 0.0004809521 +23 right_top_grid_pin_48_[0]:16 chanx_right_in[17]:15 0.0004809521 +24 right_top_grid_pin_48_[0]:20 chanx_right_in[17]:15 0.0002288085 +25 right_top_grid_pin_48_[0]:17 chanx_right_in[17]:14 0.000190327 +26 right_top_grid_pin_48_[0]:18 chanx_right_in[17]:15 0.000190327 +27 right_top_grid_pin_48_[0]:19 chanx_right_in[17]:14 0.0002288085 +28 right_top_grid_pin_48_[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.153502e-05 +29 right_top_grid_pin_48_[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.153502e-05 + +*RES +0 right_top_grid_pin_48_[0] right_top_grid_pin_48_[0]:21 0.0005870537 +1 right_top_grid_pin_48_[0]:7 right_top_grid_pin_48_[0]:6 0.0001634616 +2 right_top_grid_pin_48_[0]:8 right_top_grid_pin_48_[0]:7 0.00341 +3 right_top_grid_pin_48_[0]:5 right_top_grid_pin_48_[0]:4 0.002475447 +4 right_top_grid_pin_48_[0]:6 right_top_grid_pin_48_[0]:5 0.0045 +5 right_top_grid_pin_48_[0]:4 mux_right_track_0\/mux_l1_in_2_:A1 0.152 +6 right_top_grid_pin_48_[0]:15 right_top_grid_pin_48_[0]:14 0.01421652 +7 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:15 0.00341 +8 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:8 0.003530091 +9 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:20 0.00341 +10 right_top_grid_pin_48_[0]:20 right_top_grid_pin_48_[0]:19 0.001151892 +11 right_top_grid_pin_48_[0]:12 mux_right_track_4\/mux_l1_in_2_:A1 0.152 +12 right_top_grid_pin_48_[0]:13 right_top_grid_pin_48_[0]:12 0.005676339 +13 right_top_grid_pin_48_[0]:14 right_top_grid_pin_48_[0]:13 0.0045 +14 right_top_grid_pin_48_[0]:14 right_top_grid_pin_48_[0]:11 0.002388393 +15 right_top_grid_pin_48_[0]:10 right_top_grid_pin_48_[0]:9 0.0004933035 +16 right_top_grid_pin_48_[0]:11 right_top_grid_pin_48_[0]:10 0.0045 +17 right_top_grid_pin_48_[0]:9 mux_right_track_20\/mux_l1_in_0_:A0 0.152 +18 right_top_grid_pin_48_[0]:17 right_top_grid_pin_48_[0]:16 0.0001053583 +19 right_top_grid_pin_48_[0]:18 right_top_grid_pin_48_[0]:17 0.001441333 +20 right_top_grid_pin_48_[0]:19 right_top_grid_pin_48_[0]:18 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.002209273 //LENGTH 17.540 LUMPCC 0.0002798984 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 43.545 53.380 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 35.595 60.860 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 37.820 56.055 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 37.820 56.055 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 35.633 60.860 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 37.675 60.860 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 37.720 60.815 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 37.720 55.805 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 37.878 55.760 +*N mux_tree_tapbuf_size2_3_sram[0]:9 *C 41.815 55.760 +*N mux_tree_tapbuf_size2_3_sram[0]:10 *C 41.860 55.715 +*N mux_tree_tapbuf_size2_3_sram[0]:11 *C 41.860 53.425 +*N mux_tree_tapbuf_size2_3_sram[0]:12 *C 41.905 53.380 +*N mux_tree_tapbuf_size2_3_sram[0]:13 *C 43.508 53.380 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 6.159417e-05 +4 mux_tree_tapbuf_size2_3_sram[0]:4 0.0001461899 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0001461899 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.0001895714 +7 mux_tree_tapbuf_size2_3_sram[0]:7 0.0001895714 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.0003567794 +9 mux_tree_tapbuf_size2_3_sram[0]:9 0.0003235186 +10 mux_tree_tapbuf_size2_3_sram[0]:10 0.0001462891 +11 mux_tree_tapbuf_size2_3_sram[0]:11 0.0001462891 +12 mux_tree_tapbuf_size2_3_sram[0]:12 0.000110191 +13 mux_tree_tapbuf_size2_3_sram[0]:13 0.000110191 +14 mux_tree_tapbuf_size2_3_sram[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001399492 +15 mux_tree_tapbuf_size2_3_sram[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001399492 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:3 0.0001271552 +3 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.004473214 +4 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.001823661 +5 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size2_3_sram[0]:4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_3_sram[0]:9 mux_tree_tapbuf_size2_3_sram[0]:8 0.003515625 +8 mux_tree_tapbuf_size2_3_sram[0]:10 mux_tree_tapbuf_size2_3_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_3_sram[0]:12 mux_tree_tapbuf_size2_3_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size2_3_sram[0]:11 mux_tree_tapbuf_size2_3_sram[0]:10 0.002044643 +11 mux_tree_tapbuf_size2_3_sram[0]:13 mux_tree_tapbuf_size2_3_sram[0]:12 0.001430803 +12 mux_tree_tapbuf_size2_3_sram[0]:3 mux_top_track_24\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.001342151 //LENGTH 11.980 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/FTB_18__39:X O *L 0 *C 64.165 63.580 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 55.835 60.860 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 55.873 60.860 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 60.215 60.860 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 60.260 60.905 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 60.260 63.535 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 60.305 63.580 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 64.127 63.580 + +*CAP +0 mem_right_track_24\/FTB_18__39:X 1e-06 +1 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.0002758321 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0002758321 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.000149943 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.000149943 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0002443002 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0002443002 + +*RES +0 mem_right_track_24\/FTB_18__39:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.003877232 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.003412947 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008972582 //LENGTH 6.590 LUMPCC 0.0003951575 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 67.335 42.500 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.540 47.260 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.540 47.260 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.540 47.215 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 68.540 42.545 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 68.495 42.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 67.373 42.500 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.119538e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002237743 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002237743 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.067829e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.067829e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[6]:23 5.585442e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[6]:24 5.585442e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_1_[0]:14 2.648044e-06 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_1_[0]:16 5.231945e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_1_[0]:13 2.648044e-06 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_1_[0]:15 5.231945e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_115:22 8.675682e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_115:21 8.675682e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001002232 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004169643 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001460047 //LENGTH 13.585 LUMPCC 0 DR + +*CONN +*I mux_right_track_20\/mux_l1_in_0_:X O *L 0 *C 93.205 55.420 +*I mux_right_track_20\/mux_l2_in_0_:A1 I *L 0.00198 *C 103.140 52.700 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 103.103 52.700 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 102.625 52.700 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 102.580 52.745 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 102.580 55.375 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 102.535 55.420 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 93.243 55.420 + +*CAP +0 mux_right_track_20\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_20\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.296749e-05 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.296749e-05 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001525782 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001525782 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005134778 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0005134778 + +*RES +0 mux_right_track_20\/mux_l1_in_0_:X mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_20\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.008296875 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001179422 //LENGTH 8.195 LUMPCC 0.0003897793 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_1_:X O *L 0 *C 76.995 77.520 +*I mux_right_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 78.780 71.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.743 71.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 77.325 71.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 77.280 71.785 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 77.280 77.475 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 77.280 77.520 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 76.995 77.520 + +*CAP +0 mux_right_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.991167e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.991167e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002628661 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002628661 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.536692e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.671966e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_0_sram[2]:8 2.567547e-07 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size5_0_sram[2]:10 6.559319e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_0_sram[2]:7 2.567547e-07 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size5_0_sram[2]:9 6.559319e-05 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 optlc_net_112:14 1.035162e-06 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 optlc_net_112:13 1.035162e-06 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_112:10 1.763581e-06 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_112:15 0.000126241 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_112:11 1.763581e-06 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_112:24 0.000126241 + +*RES +0 mux_right_track_2\/mux_l2_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005080357 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001265625 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET chany_top_out[7] 0.002511449 //LENGTH 17.215 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 68.080 96.560 +*P chany_top_out[7] O *L 0.7423 *C 69.000 102.150 +*N chany_top_out[7]:2 *C 69.000 101.328 +*N chany_top_out[7]:3 *C 69.020 101.320 +*N chany_top_out[7]:4 *C 73.593 101.320 +*N chany_top_out[7]:5 *C 73.600 101.263 +*N chany_top_out[7]:6 *C 73.600 97.285 +*N chany_top_out[7]:7 *C 73.555 97.240 +*N chany_top_out[7]:8 *C 68.125 97.240 +*N chany_top_out[7]:9 *C 68.080 97.195 +*N chany_top_out[7]:10 *C 68.080 96.605 +*N chany_top_out[7]:11 *C 68.080 96.560 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 chany_top_out[7] 7.884804e-05 +2 chany_top_out[7]:2 7.884804e-05 +3 chany_top_out[7]:3 0.0003426549 +4 chany_top_out[7]:4 0.0003426549 +5 chany_top_out[7]:5 0.0002696228 +6 chany_top_out[7]:6 0.0002696228 +7 chany_top_out[7]:7 0.0004770897 +8 chany_top_out[7]:8 0.0004770897 +9 chany_top_out[7]:9 6.944835e-05 +10 chany_top_out[7]:10 6.944835e-05 +11 chany_top_out[7]:11 3.512125e-05 + +*RES +0 ropt_mt_inst_742:X chany_top_out[7]:11 0.152 +1 chany_top_out[7]:11 chany_top_out[7]:10 0.0045 +2 chany_top_out[7]:10 chany_top_out[7]:9 0.0005267857 +3 chany_top_out[7]:8 chany_top_out[7]:7 0.004848214 +4 chany_top_out[7]:9 chany_top_out[7]:8 0.0045 +5 chany_top_out[7]:7 chany_top_out[7]:6 0.0045 +6 chany_top_out[7]:6 chany_top_out[7]:5 0.003551339 +7 chany_top_out[7]:5 chany_top_out[7]:4 0.00341 +8 chany_top_out[7]:4 chany_top_out[7]:3 0.0007163583 +9 chany_top_out[7]:3 chany_top_out[7]:2 0.00341 +10 chany_top_out[7]:2 chany_top_out[7] 0.0001288583 + +*END + +*D_NET chanx_right_in[7] 0.01779418 //LENGTH 154.385 LUMPCC 0.00375541 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 111.930 47.600 +*I BUFT_P_98:A I *L 0.001767 *C 8.280 96.560 +*N chanx_right_in[7]:2 *C 8.280 96.560 +*N chanx_right_in[7]:3 *C 8.740 96.560 +*N chanx_right_in[7]:4 *C 8.740 96.220 +*N chanx_right_in[7]:5 *C 10.995 96.220 +*N chanx_right_in[7]:6 *C 11.040 96.175 +*N chanx_right_in[7]:7 *C 11.040 51.058 +*N chanx_right_in[7]:8 *C 11.048 51.000 +*N chanx_right_in[7]:9 *C 60.875 51.000 +*N chanx_right_in[7]:10 *C 109.460 51.000 +*N chanx_right_in[7]:11 *C 109.480 50.992 +*N chanx_right_in[7]:12 *C 109.480 47.608 +*N chanx_right_in[7]:13 *C 109.500 47.600 + +*CAP +0 chanx_right_in[7] 0.0001556355 +1 BUFT_P_98:A 1e-06 +2 chanx_right_in[7]:2 6.107446e-05 +3 chanx_right_in[7]:3 5.677303e-05 +4 chanx_right_in[7]:4 0.0001753257 +5 chanx_right_in[7]:5 0.0001517822 +6 chanx_right_in[7]:6 0.002029315 +7 chanx_right_in[7]:7 0.002029315 +8 chanx_right_in[7]:8 0.00247471 +9 chanx_right_in[7]:9 0.004387856 +10 chanx_right_in[7]:10 0.001913148 +11 chanx_right_in[7]:11 0.0002236017 +12 chanx_right_in[7]:12 0.0002236017 +13 chanx_right_in[7]:13 0.0001556355 +14 chanx_right_in[7] chanx_right_in[18] 3.402926e-05 +15 chanx_right_in[7]:10 chanx_right_in[18] 0.0001291641 +16 chanx_right_in[7]:10 chanx_right_in[18]:20 7.735675e-06 +17 chanx_right_in[7]:10 chanx_right_in[18]:18 0.0005503987 +18 chanx_right_in[7]:13 chanx_right_in[18]:23 3.402926e-05 +19 chanx_right_in[7]:9 chanx_right_in[18]:17 0.0005503987 +20 chanx_right_in[7]:9 chanx_right_in[18]:23 0.0001291641 +21 chanx_right_in[7]:9 chanx_right_in[18]:19 7.735675e-06 +22 chanx_right_in[7]:8 prog_clk[0]:55 7.113772e-06 +23 chanx_right_in[7]:8 prog_clk[0]:227 3.472201e-05 +24 chanx_right_in[7]:8 prog_clk[0]:47 6.138612e-05 +25 chanx_right_in[7]:8 prog_clk[0]:226 4.689409e-05 +26 chanx_right_in[7]:10 prog_clk[0]:218 9.546459e-05 +27 chanx_right_in[7]:10 prog_clk[0]:193 0.00011222 +28 chanx_right_in[7]:10 prog_clk[0]:198 0.0003658429 +29 chanx_right_in[7]:10 prog_clk[0]:222 8.144684e-05 +30 chanx_right_in[7]:9 prog_clk[0]:54 7.113772e-06 +31 chanx_right_in[7]:9 prog_clk[0]:46 6.138612e-05 +32 chanx_right_in[7]:9 prog_clk[0]:198 0.00011222 +33 chanx_right_in[7]:9 prog_clk[0]:222 0.0001423587 +34 chanx_right_in[7]:9 prog_clk[0]:226 0.0001161688 +35 chanx_right_in[7]:9 prog_clk[0]:199 0.0003658429 +36 chanx_right_in[7]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001081206 +37 chanx_right_in[7]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001081206 +38 chanx_right_in[7]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.923371e-05 +39 chanx_right_in[7]:10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001228177 +40 chanx_right_in[7]:9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001228177 +41 chanx_right_in[7]:9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.923371e-05 +42 chanx_right_in[7]:5 ropt_net_143:3 4.548067e-05 +43 chanx_right_in[7]:6 ropt_net_143:4 2.563415e-05 +44 chanx_right_in[7]:7 ropt_net_143:5 2.563415e-05 +45 chanx_right_in[7]:4 ropt_net_143:2 4.548067e-05 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:13 0.0003807 +1 chanx_right_in[7]:2 BUFT_P_98:A 0.152 +2 chanx_right_in[7]:5 chanx_right_in[7]:4 0.002013393 +3 chanx_right_in[7]:6 chanx_right_in[7]:5 0.0045 +4 chanx_right_in[7]:7 chanx_right_in[7]:6 0.04028349 +5 chanx_right_in[7]:8 chanx_right_in[7]:7 0.00341 +6 chanx_right_in[7]:10 chanx_right_in[7]:9 0.00761165 +7 chanx_right_in[7]:11 chanx_right_in[7]:10 0.00341 +8 chanx_right_in[7]:13 chanx_right_in[7]:12 0.00341 +9 chanx_right_in[7]:12 chanx_right_in[7]:11 0.0005303166 +10 chanx_right_in[7]:3 chanx_right_in[7]:2 0.0004107143 +11 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0003035715 +12 chanx_right_in[7]:9 chanx_right_in[7]:8 0.007806308 + +*END + +*D_NET right_top_grid_pin_46_[0] 0.008768098 //LENGTH 59.185 LUMPCC 0.002355347 DR + +*CONN +*P right_top_grid_pin_46_[0] I *L 0.29796 *C 83.410 91.800 +*I mux_right_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 79.755 59.160 +*I mux_right_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.830 71.740 +*I mux_right_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 87.690 71.400 +*N right_top_grid_pin_46_[0]:4 *C 87.690 71.400 +*N right_top_grid_pin_46_[0]:5 *C 87.400 71.400 +*N right_top_grid_pin_46_[0]:6 *C 87.400 71.400 +*N right_top_grid_pin_46_[0]:7 *C 87.392 71.400 +*N right_top_grid_pin_46_[0]:8 *C 68.830 71.740 +*N right_top_grid_pin_46_[0]:9 *C 69.000 71.740 +*N right_top_grid_pin_46_[0]:10 *C 69.000 71.740 +*N right_top_grid_pin_46_[0]:11 *C 69.000 71.400 +*N right_top_grid_pin_46_[0]:12 *C 69.008 71.400 +*N right_top_grid_pin_46_[0]:13 *C 79.755 59.160 +*N right_top_grid_pin_46_[0]:14 *C 79.580 59.160 +*N right_top_grid_pin_46_[0]:15 *C 79.580 59.205 +*N right_top_grid_pin_46_[0]:16 *C 79.580 71.343 +*N right_top_grid_pin_46_[0]:17 *C 79.580 71.400 +*N right_top_grid_pin_46_[0]:18 *C 79.575 71.407 +*N right_top_grid_pin_46_[0]:19 *C 79.120 71.413 +*N right_top_grid_pin_46_[0]:20 *C 79.120 88.392 +*N right_top_grid_pin_46_[0]:21 *C 79.140 88.400 +*N right_top_grid_pin_46_[0]:22 *C 82.780 88.400 +*N right_top_grid_pin_46_[0]:23 *C 82.800 88.407 +*N right_top_grid_pin_46_[0]:24 *C 82.800 91.793 +*N right_top_grid_pin_46_[0]:25 *C 82.820 91.800 + +*CAP +0 right_top_grid_pin_46_[0] 6.227478e-05 +1 mux_right_track_16\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_4\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_46_[0]:4 5.845149e-05 +5 right_top_grid_pin_46_[0]:5 6.132862e-05 +6 right_top_grid_pin_46_[0]:6 3.894497e-05 +7 right_top_grid_pin_46_[0]:7 0.0003224115 +8 right_top_grid_pin_46_[0]:8 5.528157e-05 +9 right_top_grid_pin_46_[0]:9 5.897509e-05 +10 right_top_grid_pin_46_[0]:10 6.02205e-05 +11 right_top_grid_pin_46_[0]:11 6.671071e-05 +12 right_top_grid_pin_46_[0]:12 0.000801934 +13 right_top_grid_pin_46_[0]:13 5.109641e-05 +14 right_top_grid_pin_46_[0]:14 5.539745e-05 +15 right_top_grid_pin_46_[0]:15 0.0007096942 +16 right_top_grid_pin_46_[0]:16 0.0007096942 +17 right_top_grid_pin_46_[0]:17 0.001124345 +18 right_top_grid_pin_46_[0]:18 4.986264e-05 +19 right_top_grid_pin_46_[0]:19 0.0006664778 +20 right_top_grid_pin_46_[0]:20 0.0006166152 +21 right_top_grid_pin_46_[0]:21 0.0002134175 +22 right_top_grid_pin_46_[0]:22 0.0002134175 +23 right_top_grid_pin_46_[0]:23 0.0001754618 +24 right_top_grid_pin_46_[0]:24 0.0001754618 +25 right_top_grid_pin_46_[0]:25 6.227478e-05 +26 right_top_grid_pin_46_[0]:7 chanx_right_in[9]:16 0.0002750533 +27 right_top_grid_pin_46_[0]:17 chanx_right_in[9]:15 0.0002750533 +28 right_top_grid_pin_46_[0]:21 chanx_right_in[9]:11 9.759686e-06 +29 right_top_grid_pin_46_[0]:20 chanx_right_in[9]:13 4.587262e-05 +30 right_top_grid_pin_46_[0]:22 chanx_right_in[9]:12 9.759686e-06 +31 right_top_grid_pin_46_[0]:19 chanx_right_in[9]:14 4.587262e-05 +32 right_top_grid_pin_46_[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002239537 +33 right_top_grid_pin_46_[0]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002239537 +34 right_top_grid_pin_46_[0]:20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0006230342 +35 right_top_grid_pin_46_[0]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0006230342 + +*RES +0 right_top_grid_pin_46_[0] right_top_grid_pin_46_[0]:25 9.243332e-05 +1 right_top_grid_pin_46_[0]:6 right_top_grid_pin_46_[0]:5 0.0045 +2 right_top_grid_pin_46_[0]:7 right_top_grid_pin_46_[0]:6 0.00341 +3 right_top_grid_pin_46_[0]:5 right_top_grid_pin_46_[0]:4 0.0001576087 +4 right_top_grid_pin_46_[0]:4 mux_right_track_4\/mux_l1_in_1_:A0 0.152 +5 right_top_grid_pin_46_[0]:16 right_top_grid_pin_46_[0]:15 0.01083705 +6 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:16 0.00341 +7 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:12 0.001656358 +8 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:7 0.001223958 +9 right_top_grid_pin_46_[0]:14 right_top_grid_pin_46_[0]:13 9.51087e-05 +10 right_top_grid_pin_46_[0]:15 right_top_grid_pin_46_[0]:14 0.0045 +11 right_top_grid_pin_46_[0]:13 mux_right_track_16\/mux_l1_in_0_:A0 0.152 +12 right_top_grid_pin_46_[0]:11 right_top_grid_pin_46_[0]:10 0.0001634616 +13 right_top_grid_pin_46_[0]:12 right_top_grid_pin_46_[0]:11 0.00341 +14 right_top_grid_pin_46_[0]:9 right_top_grid_pin_46_[0]:8 9.239131e-05 +15 right_top_grid_pin_46_[0]:10 right_top_grid_pin_46_[0]:9 0.0045 +16 right_top_grid_pin_46_[0]:8 mux_right_track_0\/mux_l1_in_1_:A0 0.152 +17 right_top_grid_pin_46_[0]:18 right_top_grid_pin_46_[0]:17 0.00341 +18 right_top_grid_pin_46_[0]:21 right_top_grid_pin_46_[0]:20 0.00341 +19 right_top_grid_pin_46_[0]:20 right_top_grid_pin_46_[0]:19 0.0026602 +20 right_top_grid_pin_46_[0]:22 right_top_grid_pin_46_[0]:21 0.0005702666 +21 right_top_grid_pin_46_[0]:23 right_top_grid_pin_46_[0]:22 0.00341 +22 right_top_grid_pin_46_[0]:25 right_top_grid_pin_46_[0]:24 0.00341 +23 right_top_grid_pin_46_[0]:24 right_top_grid_pin_46_[0]:23 0.0005303166 +24 right_top_grid_pin_46_[0]:19 right_top_grid_pin_46_[0]:18 6.788888e-05 + +*END + +*D_NET chanx_right_out[0] 0.001466183 //LENGTH 11.980 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 63.920 +*P chanx_right_out[0] O *L 0.7423 *C 111.855 59.840 +*N chanx_right_out[0]:2 *C 110.868 59.840 +*N chanx_right_out[0]:3 *C 110.860 59.898 +*N chanx_right_out[0]:4 *C 110.860 63.535 +*N chanx_right_out[0]:5 *C 110.815 63.580 +*N chanx_right_out[0]:6 *C 104.880 63.580 +*N chanx_right_out[0]:7 *C 104.880 63.920 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 8.983136e-05 +2 chanx_right_out[0]:2 8.983136e-05 +3 chanx_right_out[0]:3 0.0002299009 +4 chanx_right_out[0]:4 0.0002299009 +5 chanx_right_out[0]:5 0.0003718359 +6 chanx_right_out[0]:6 0.000398922 +7 chanx_right_out[0]:7 5.49603e-05 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:7 0.152 +1 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +2 chanx_right_out[0]:2 chanx_right_out[0] 0.0001547083 +3 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +4 chanx_right_out[0]:4 chanx_right_out[0]:3 0.003247768 +5 chanx_right_out[0]:7 chanx_right_out[0]:6 0.0003035714 +6 chanx_right_out[0]:6 chanx_right_out[0]:5 0.005299107 + +*END + +*D_NET chanx_right_out[5] 0.0007774883 //LENGTH 6.745 LUMPCC 0 DR + +*CONN +*I mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 107.700 58.820 +*P chanx_right_out[5] O *L 0.7423 *C 111.930 57.120 +*N chanx_right_out[5]:2 *C 109.028 57.120 +*N chanx_right_out[5]:3 *C 109.020 57.178 +*N chanx_right_out[5]:4 *C 109.020 58.775 +*N chanx_right_out[5]:5 *C 108.975 58.820 +*N chanx_right_out[5]:6 *C 107.738 58.820 + +*CAP +0 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[5] 0.0001930887 +2 chanx_right_out[5]:2 0.0001930887 +3 chanx_right_out[5]:3 0.0001075873 +4 chanx_right_out[5]:4 0.0001075873 +5 chanx_right_out[5]:5 8.756815e-05 +6 chanx_right_out[5]:6 8.756815e-05 + +*RES +0 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[5]:6 0.152 +1 chanx_right_out[5]:6 chanx_right_out[5]:5 0.001104911 +2 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0045 +3 chanx_right_out[5]:4 chanx_right_out[5]:3 0.001426339 +4 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +5 chanx_right_out[5]:2 chanx_right_out[5] 0.0004547249 + +*END + +*D_NET chanx_right_out[9] 0.00173886 //LENGTH 13.590 LUMPCC 0.0002044466 DR + +*CONN +*I mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.020 44.540 +*P chanx_right_out[9] O *L 0.7423 *C 111.855 40.800 +*N chanx_right_out[9]:2 *C 111.328 40.800 +*N chanx_right_out[9]:3 *C 111.320 40.858 +*N chanx_right_out[9]:4 *C 111.320 42.500 +*N chanx_right_out[9]:5 *C 111.780 42.500 +*N chanx_right_out[9]:6 *C 111.780 44.495 +*N chanx_right_out[9]:7 *C 111.735 44.540 +*N chanx_right_out[9]:8 *C 104.058 44.540 + +*CAP +0 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[9] 6.491459e-05 +2 chanx_right_out[9]:2 6.491459e-05 +3 chanx_right_out[9]:3 0.0001095422 +4 chanx_right_out[9]:4 0.0001401418 +5 chanx_right_out[9]:5 0.0001487843 +6 chanx_right_out[9]:6 0.0001181847 +7 chanx_right_out[9]:7 0.0004434657 +8 chanx_right_out[9]:8 0.0004434657 +9 chanx_right_out[9]:3 ropt_net_142:4 1.475934e-05 +10 chanx_right_out[9]:7 ropt_net_142:6 3.014578e-05 +11 chanx_right_out[9]:6 ropt_net_142:5 1.211528e-05 +12 chanx_right_out[9]:8 ropt_net_142:7 3.014578e-05 +13 chanx_right_out[9]:4 ropt_net_142:5 1.475934e-05 +14 chanx_right_out[9]:5 ropt_net_142:4 1.211528e-05 +15 chanx_right_out[9]:7 ropt_net_135:2 4.520288e-05 +16 chanx_right_out[9]:8 ropt_net_135:3 4.520288e-05 + +*RES +0 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[9]:8 0.152 +1 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +2 chanx_right_out[9]:2 chanx_right_out[9] 8.264167e-05 +3 chanx_right_out[9]:7 chanx_right_out[9]:6 0.0045 +4 chanx_right_out[9]:6 chanx_right_out[9]:5 0.00178125 +5 chanx_right_out[9]:8 chanx_right_out[9]:7 0.006854911 +6 chanx_right_out[9]:4 chanx_right_out[9]:3 0.001466518 +7 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.001807718 //LENGTH 13.625 LUMPCC 0.0002615873 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.465 39.440 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.895 44.540 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 68.180 41.480 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 68.142 41.480 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 60.895 44.540 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 61.180 44.540 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 61.180 44.495 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 61.180 41.525 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 61.225 41.480 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 67.160 41.480 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 67.160 41.435 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 67.160 39.485 +*N mux_tree_tapbuf_size2_1_sram[0]:12 *C 67.160 39.440 +*N mux_tree_tapbuf_size2_1_sram[0]:13 *C 67.465 39.440 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 6.527049e-05 +4 mux_tree_tapbuf_size2_1_sram[0]:4 5.072616e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:5 5.493252e-05 +6 mux_tree_tapbuf_size2_1_sram[0]:6 0.0001797305 +7 mux_tree_tapbuf_size2_1_sram[0]:7 0.0001797305 +8 mux_tree_tapbuf_size2_1_sram[0]:8 0.0002906753 +9 mux_tree_tapbuf_size2_1_sram[0]:9 0.000386749 +10 mux_tree_tapbuf_size2_1_sram[0]:10 0.000117567 +11 mux_tree_tapbuf_size2_1_sram[0]:11 0.000117567 +12 mux_tree_tapbuf_size2_1_sram[0]:12 4.981921e-05 +13 mux_tree_tapbuf_size2_1_sram[0]:13 5.036313e-05 +14 mux_tree_tapbuf_size2_1_sram[0]:8 top_left_grid_pin_1_[0]:16 0.0001120629 +15 mux_tree_tapbuf_size2_1_sram[0]:9 top_left_grid_pin_1_[0]:15 0.0001120629 +16 mux_tree_tapbuf_size2_1_sram[0]:9 top_left_grid_pin_1_[0]:16 1.497845e-05 +17 mux_tree_tapbuf_size2_1_sram[0]:10 top_left_grid_pin_1_[0]:12 3.752327e-06 +18 mux_tree_tapbuf_size2_1_sram[0]:11 top_left_grid_pin_1_[0]:11 3.752327e-06 +19 mux_tree_tapbuf_size2_1_sram[0]:3 top_left_grid_pin_1_[0]:15 1.497845e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size2_1_sram[0]:7 mux_tree_tapbuf_size2_1_sram[0]:6 0.002651786 +3 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 0.0001548913 +4 mux_tree_tapbuf_size2_1_sram[0]:6 mux_tree_tapbuf_size2_1_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size2_1_sram[0]:4 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.005299107 +7 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:3 0.0008772323 +8 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.001741071 +11 mux_tree_tapbuf_size2_1_sram[0]:13 mux_tree_tapbuf_size2_1_sram[0]:12 0.0001440218 +12 mux_tree_tapbuf_size2_1_sram[0]:3 mux_top_track_4\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[0] 0.001823449 //LENGTH 16.045 LUMPCC 0 DR + +*CONN +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 64.245 53.380 +*I mux_right_track_14\/mux_l1_in_0_:S I *L 0.00357 *C 69.340 63.240 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.335 53.380 +*N mux_tree_tapbuf_size2_6_sram[0]:3 *C 67.210 53.380 +*N mux_tree_tapbuf_size2_6_sram[0]:4 *C 69.303 63.240 +*N mux_tree_tapbuf_size2_6_sram[0]:5 *C 67.205 63.240 +*N mux_tree_tapbuf_size2_6_sram[0]:6 *C 67.160 63.195 +*N mux_tree_tapbuf_size2_6_sram[0]:7 *C 67.160 53.425 +*N mux_tree_tapbuf_size2_6_sram[0]:8 *C 67.115 53.380 +*N mux_tree_tapbuf_size2_6_sram[0]:9 *C 64.282 53.380 + +*CAP +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_14\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_6_sram[0]:3 2.113803e-05 +4 mux_tree_tapbuf_size2_6_sram[0]:4 0.0001731351 +5 mux_tree_tapbuf_size2_6_sram[0]:5 0.0001731351 +6 mux_tree_tapbuf_size2_6_sram[0]:6 0.0005343627 +7 mux_tree_tapbuf_size2_6_sram[0]:7 0.0005343627 +8 mux_tree_tapbuf_size2_6_sram[0]:8 0.0002027266 +9 mux_tree_tapbuf_size2_6_sram[0]:9 0.0001815885 + +*RES +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_6_sram[0]:9 0.152 +1 mux_tree_tapbuf_size2_6_sram[0]:4 mux_right_track_14\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_6_sram[0]:5 mux_tree_tapbuf_size2_6_sram[0]:4 0.001872768 +3 mux_tree_tapbuf_size2_6_sram[0]:6 mux_tree_tapbuf_size2_6_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:3 8.482144e-05 +6 mux_tree_tapbuf_size2_6_sram[0]:7 mux_tree_tapbuf_size2_6_sram[0]:6 0.008723215 +7 mux_tree_tapbuf_size2_6_sram[0]:3 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:8 0.002529018 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_10_ccff_tail[0] 0.002367915 //LENGTH 18.145 LUMPCC 0 DR + +*CONN +*I mem_right_track_22\/FTB_11__32:X O *L 0 *C 91.765 64.260 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 75.150 64.260 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 *C 75.188 64.260 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 *C 78.200 64.260 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 *C 78.200 64.600 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 *C 81.420 64.600 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 *C 81.420 64.260 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 *C 91.728 64.260 + +*CAP +0 mem_right_track_22\/FTB_11__32:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 0.0002302739 +3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 0.0002557739 +4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 0.0002857024 +5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 0.0002855239 +6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 0.000666981 +7 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 0.0006416595 + +*RES +0 mem_right_track_22\/FTB_11__32:X mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 0.009203126 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 0.002689732 +4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 0.0003035715 +5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 0.002875 +6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_9_ccff_tail[0] 0.0009109074 //LENGTH 7.700 LUMPCC 0 DR + +*CONN +*I mem_right_track_20\/FTB_10__31:X O *L 0 *C 102.345 58.820 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.935 58.820 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 *C 94.973 58.820 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 *C 102.308 58.820 + +*CAP +0 mem_right_track_20\/FTB_10__31:X 1e-06 +1 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 0.0004544537 +3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 0.0004544537 + +*RES +0 mem_right_track_20\/FTB_10__31:X mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 0.006549107 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.001128315 //LENGTH 9.760 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/FTB_17__38:X O *L 0 *C 40.245 90.440 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 35.595 86.020 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 35.633 86.020 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 39.975 86.020 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 40.020 86.065 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 40.020 90.395 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 40.020 90.440 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 40.245 90.440 + +*CAP +0 mem_right_track_8\/FTB_17__38:X 1e-06 +1 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0002810829 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0002810829 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.00023299 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.00023299 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 4.888494e-05 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 4.928385e-05 + +*RES +0 mem_right_track_8\/FTB_17__38:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.003877232 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[0] 0.00627816 //LENGTH 47.250 LUMPCC 0.0009217124 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.345 74.800 +*I mux_right_track_6\/mux_l1_in_0_:S I *L 0.00357 *C 70.720 94.180 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 74.680 98.940 +*I mux_right_track_6\/mux_l1_in_1_:S I *L 0.00357 *C 78.300 83.255 +*N mux_tree_tapbuf_size5_1_sram[0]:4 *C 78.300 83.255 +*N mux_tree_tapbuf_size5_1_sram[0]:5 *C 74.642 98.940 +*N mux_tree_tapbuf_size5_1_sram[0]:6 *C 74.105 98.940 +*N mux_tree_tapbuf_size5_1_sram[0]:7 *C 74.060 98.895 +*N mux_tree_tapbuf_size5_1_sram[0]:8 *C 74.060 93.885 +*N mux_tree_tapbuf_size5_1_sram[0]:9 *C 74.015 93.840 +*N mux_tree_tapbuf_size5_1_sram[0]:10 *C 70.380 93.840 +*N mux_tree_tapbuf_size5_1_sram[0]:11 *C 70.693 94.135 +*N mux_tree_tapbuf_size5_1_sram[0]:12 *C 70.380 94.168 +*N mux_tree_tapbuf_size5_1_sram[0]:13 *C 68.585 94.180 +*N mux_tree_tapbuf_size5_1_sram[0]:14 *C 68.540 94.135 +*N mux_tree_tapbuf_size5_1_sram[0]:15 *C 68.540 82.665 +*N mux_tree_tapbuf_size5_1_sram[0]:16 *C 68.585 82.620 +*N mux_tree_tapbuf_size5_1_sram[0]:17 *C 76.360 82.620 +*N mux_tree_tapbuf_size5_1_sram[0]:18 *C 76.360 82.960 +*N mux_tree_tapbuf_size5_1_sram[0]:19 *C 78.300 82.960 +*N mux_tree_tapbuf_size5_1_sram[0]:20 *C 80.455 82.960 +*N mux_tree_tapbuf_size5_1_sram[0]:21 *C 80.500 82.915 +*N mux_tree_tapbuf_size5_1_sram[0]:22 *C 80.500 74.845 +*N mux_tree_tapbuf_size5_1_sram[0]:23 *C 80.500 74.800 +*N mux_tree_tapbuf_size5_1_sram[0]:24 *C 80.345 74.800 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_6\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_track_6\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[0]:4 5.972614e-05 +5 mux_tree_tapbuf_size5_1_sram[0]:5 6.287112e-05 +6 mux_tree_tapbuf_size5_1_sram[0]:6 6.287112e-05 +7 mux_tree_tapbuf_size5_1_sram[0]:7 0.0003442902 +8 mux_tree_tapbuf_size5_1_sram[0]:8 0.0003442902 +9 mux_tree_tapbuf_size5_1_sram[0]:9 0.0002416066 +10 mux_tree_tapbuf_size5_1_sram[0]:10 0.0002679065 +11 mux_tree_tapbuf_size5_1_sram[0]:11 3.695143e-05 +12 mux_tree_tapbuf_size5_1_sram[0]:12 0.0002156283 +13 mux_tree_tapbuf_size5_1_sram[0]:13 0.000152377 +14 mux_tree_tapbuf_size5_1_sram[0]:14 0.0006434558 +15 mux_tree_tapbuf_size5_1_sram[0]:15 0.0006434558 +16 mux_tree_tapbuf_size5_1_sram[0]:16 0.0004074315 +17 mux_tree_tapbuf_size5_1_sram[0]:17 0.0004366461 +18 mux_tree_tapbuf_size5_1_sram[0]:18 0.0001600188 +19 mux_tree_tapbuf_size5_1_sram[0]:19 0.0003147005 +20 mux_tree_tapbuf_size5_1_sram[0]:20 0.0001533979 +21 mux_tree_tapbuf_size5_1_sram[0]:21 0.0003382051 +22 mux_tree_tapbuf_size5_1_sram[0]:22 0.0003382051 +23 mux_tree_tapbuf_size5_1_sram[0]:23 6.609134e-05 +24 mux_tree_tapbuf_size5_1_sram[0]:24 6.232195e-05 +25 mux_tree_tapbuf_size5_1_sram[0]:7 right_top_grid_pin_43_[0]:17 2.055271e-05 +26 mux_tree_tapbuf_size5_1_sram[0]:9 right_top_grid_pin_43_[0]:15 6.359594e-05 +27 mux_tree_tapbuf_size5_1_sram[0]:8 right_top_grid_pin_43_[0]:16 2.055271e-05 +28 mux_tree_tapbuf_size5_1_sram[0]:16 right_top_grid_pin_43_[0]:6 0.0001586414 +29 mux_tree_tapbuf_size5_1_sram[0]:17 right_top_grid_pin_43_[0]:7 0.0001586414 +30 mux_tree_tapbuf_size5_1_sram[0]:10 right_top_grid_pin_43_[0]:14 6.359594e-05 +31 mux_tree_tapbuf_size5_1_sram[0]:21 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002180662 +32 mux_tree_tapbuf_size5_1_sram[0]:22 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002180662 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_1_sram[0]:24 0.152 +1 mux_tree_tapbuf_size5_1_sram[0]:5 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size5_1_sram[0]:6 mux_tree_tapbuf_size5_1_sram[0]:5 0.0004799107 +3 mux_tree_tapbuf_size5_1_sram[0]:7 mux_tree_tapbuf_size5_1_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size5_1_sram[0]:8 mux_tree_tapbuf_size5_1_sram[0]:7 0.004473215 +6 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:12 0.001602679 +7 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size5_1_sram[0]:13 0.0045 +8 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:14 0.01024107 +10 mux_tree_tapbuf_size5_1_sram[0]:20 mux_tree_tapbuf_size5_1_sram[0]:19 0.001924107 +11 mux_tree_tapbuf_size5_1_sram[0]:21 mux_tree_tapbuf_size5_1_sram[0]:20 0.0045 +12 mux_tree_tapbuf_size5_1_sram[0]:23 mux_tree_tapbuf_size5_1_sram[0]:22 0.0045 +13 mux_tree_tapbuf_size5_1_sram[0]:22 mux_tree_tapbuf_size5_1_sram[0]:21 0.007205358 +14 mux_tree_tapbuf_size5_1_sram[0]:24 mux_tree_tapbuf_size5_1_sram[0]:23 8.423914e-05 +15 mux_tree_tapbuf_size5_1_sram[0]:4 mux_right_track_6\/mux_l1_in_1_:S 0.152 +16 mux_tree_tapbuf_size5_1_sram[0]:11 mux_right_track_6\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size5_1_sram[0]:17 mux_tree_tapbuf_size5_1_sram[0]:16 0.006941964 +18 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size5_1_sram[0]:11 0.0002790179 +19 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size5_1_sram[0]:10 0.0002924108 +20 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size5_1_sram[0]:9 0.003245536 +21 mux_tree_tapbuf_size5_1_sram[0]:18 mux_tree_tapbuf_size5_1_sram[0]:17 0.0003035715 +22 mux_tree_tapbuf_size5_1_sram[0]:19 mux_tree_tapbuf_size5_1_sram[0]:18 0.001732143 +23 mux_tree_tapbuf_size5_1_sram[0]:19 mux_tree_tapbuf_size5_1_sram[0]:4 0.0001271552 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005150345 //LENGTH 38.660 LUMPCC 0.001240274 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 66.875 48.280 +*I mux_top_track_4\/BUFT_RR_41:A I *L 0.001776 *C 68.540 74.800 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 68.540 74.800 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 68.540 74.755 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 68.540 73.498 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 68.532 73.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.580 73.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.560 73.433 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 62.560 49.648 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 62.580 49.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 66.693 49.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 66.700 49.583 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 66.700 48.325 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 66.700 48.280 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 66.875 48.280 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/BUFT_RR_41:A 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.37027e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.919284e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.919284e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006929619 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006929619 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0008286562 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0008286562 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001779888 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001779888 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:11 8.683583e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:12 8.683583e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:13 5.139801e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:14 5.169946e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_right_in[7]:10 0.0001081206 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_right_in[7]:9 0.0001081206 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[12]:22 0.0002206538 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[12]:21 0.0002206538 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[19]:8 0.0002913626 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[19]:7 0.0002913626 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:13 9.510871e-05 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.001122768 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.00341 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0006442916 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.003726316 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0009325583 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001122768 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00341 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/BUFT_RR_41:A 0.152 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001587073 //LENGTH 13.555 LUMPCC 0.0001334943 DR + +*CONN +*I mux_right_track_18\/mux_l1_in_0_:X O *L 0 *C 84.005 52.700 +*I mux_right_track_18\/mux_l2_in_0_:A1 I *L 0.00198 *C 88.880 45.220 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 88.843 45.220 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 83.765 45.220 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 83.720 45.265 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 83.720 52.655 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 83.720 52.700 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 84.005 52.700 + +*CAP +0 mux_right_track_18\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_18\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003218306 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003218306 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003614507 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003614507 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.572763e-05 +7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 3.928833e-05 +8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_8_sram[0]:8 3.133695e-05 +9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_8_sram[0]:9 2.475226e-05 +10 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_8_sram[0]:3 1.063606e-05 +11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_8_sram[0]:6 2.188076e-08 +12 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_8_sram[0]:5 3.133695e-05 +13 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_8_sram[0]:8 2.475226e-05 +14 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_8_sram[0]:4 1.063606e-05 +15 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_8_sram[0]:7 2.188076e-08 + +*RES +0 mux_right_track_18\/mux_l1_in_0_:X mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_18\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004533482 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006598215 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00226826 //LENGTH 16.915 LUMPCC 0.0007201838 DR + +*CONN +*I mux_right_track_26\/mux_l1_in_0_:X O *L 0 *C 62.845 82.620 +*I mux_right_track_26\/mux_l2_in_0_:A1 I *L 0.00198 *C 65.420 69.020 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 65.383 69.020 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.065 69.020 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.020 69.065 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.020 82.575 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.020 82.620 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 62.845 82.620 + +*CAP +0 mux_right_track_26\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_26\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001866344 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001866344 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005226365 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005226365 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.398064e-05 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.355337e-05 +8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:17 5.206902e-05 +9 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:18 0.0003080229 +10 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[4]:16 5.206902e-05 +11 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[4]:17 0.0003080229 + +*RES +0 mux_right_track_26\/mux_l1_in_0_:X mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_26\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002069197 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0120625 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008149025 //LENGTH 6.180 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 88.145 63.240 +*I mux_right_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 92.000 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 92.000 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 92.000 61.585 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 92.000 63.195 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 91.955 63.240 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 88.183 63.240 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.220245e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001093082 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001093082 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002810418 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002810418 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.003368304 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0014375 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A1 0.152 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007694811 //LENGTH 5.090 LUMPCC 0.0003125525 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_1_:X O *L 0 *C 76.535 86.020 +*I mux_right_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.815 87.720 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 73.815 87.720 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 74.060 87.720 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 74.060 87.675 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 74.060 86.065 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 74.105 86.020 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 76.498 86.020 + +*CAP +0 mux_right_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.187801e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.780991e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.921304e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.921304e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001034073 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001034073 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[8]:6 5.524658e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[8]:5 5.524658e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_0_sram[0]:4 0.0001010297 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_0_sram[0]:5 0.0001010297 + +*RES +0 mux_right_track_2\/mux_l1_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002136161 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001331522 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.01335973 //LENGTH 89.165 LUMPCC 0.004924331 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 50.885 85.000 +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 101.375 47.795 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 101.375 47.795 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 101.200 47.940 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 101.200 47.985 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 101.200 52.983 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 101.193 53.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 78.220 53.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 78.200 53.047 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 78.200 84.993 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 78.180 85.000 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 51.068 85.000 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 51.060 85.000 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 51.060 85.000 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 50.885 85.000 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.303829e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.683581e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002671 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002671 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009213057 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0009213057 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001272013 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001272013 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.001625686 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.001625686 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:12 3.453772e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:13 6.040501e-05 +14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:14 6.636984e-05 +15 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 chanx_right_in[9]:11 0.0003066987 +16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 chanx_right_in[9]:12 0.0003066987 +17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chanx_right_in[16]:9 3.031662e-05 +18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chanx_right_in[16]:10 0.0002869053 +19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[16]:10 3.031662e-05 +20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[16]:11 0.0002869053 +21 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chanx_right_in[18]:15 0.0001123158 +22 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[18]:17 0.001102895 +23 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_right_in[18]:16 0.0001123158 +24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[18]:18 0.001102895 +25 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 right_top_grid_pin_46_[0]:20 0.0006230342 +26 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 right_top_grid_pin_46_[0]:19 0.0006230342 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:13 9.51087e-05 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.00341 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.004247625 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.00341 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.005004716 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003599025 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004462053 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.51087e-05 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chany_top_out[13] 0.0007640072 //LENGTH 5.230 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 22.080 99.960 +*P chany_top_out[13] O *L 0.7423 *C 23.920 102.150 +*N chany_top_out[13]:2 *C 23.520 99.960 +*N chany_top_out[13]:3 *C 23.920 99.968 +*N chany_top_out[13]:4 *C 23.920 99.960 +*N chany_top_out[13]:5 *C 23.920 99.960 +*N chany_top_out[13]:6 *C 23.875 99.960 +*N chany_top_out[13]:7 *C 22.117 99.960 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 chany_top_out[13] 0.0001571753 +2 chany_top_out[13]:2 6.7407e-05 +3 chany_top_out[13]:3 0.0001571753 +4 chany_top_out[13]:4 6.7407e-05 +5 chany_top_out[13]:5 3.15583e-05 +6 chany_top_out[13]:6 0.0001411421 +7 chany_top_out[13]:7 0.0001411421 + +*RES +0 ropt_mt_inst_735:X chany_top_out[13]:7 0.152 +1 chany_top_out[13]:7 chany_top_out[13]:6 0.001569196 +2 chany_top_out[13]:6 chany_top_out[13]:5 0.0045 +3 chany_top_out[13]:5 chany_top_out[13]:4 0.00341 +4 chany_top_out[13]:4 chany_top_out[13]:3 0.00341 +5 chany_top_out[13]:4 chany_top_out[13]:2 5.69697e-05 +6 chany_top_out[13]:3 chany_top_out[13] 0.000341925 + +*END + +*D_NET chany_top_out[9] 0.001637832 //LENGTH 12.655 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 11.960 98.600 +*P chany_top_out[9] O *L 0.7423 *C 9.200 102.150 +*N chany_top_out[9]:2 *C 9.200 98.608 +*N chany_top_out[9]:3 *C 9.220 98.600 +*N chany_top_out[9]:4 *C 14.713 98.600 +*N chany_top_out[9]:5 *C 14.720 98.600 +*N chany_top_out[9]:6 *C 14.675 98.600 +*N chany_top_out[9]:7 *C 11.998 98.600 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 chany_top_out[9] 0.0002154156 +2 chany_top_out[9]:2 0.0002154156 +3 chany_top_out[9]:3 0.0004033561 +4 chany_top_out[9]:4 0.0004033561 +5 chany_top_out[9]:5 2.97163e-05 +6 chany_top_out[9]:6 0.0001847864 +7 chany_top_out[9]:7 0.0001847864 + +*RES +0 ropt_mt_inst_744:X chany_top_out[9]:7 0.152 +1 chany_top_out[9]:7 chany_top_out[9]:6 0.002390625 +2 chany_top_out[9]:6 chany_top_out[9]:5 0.0045 +3 chany_top_out[9]:5 chany_top_out[9]:4 0.00341 +4 chany_top_out[9]:4 chany_top_out[9]:3 0.0008604917 +5 chany_top_out[9]:3 chany_top_out[9]:2 0.00341 +6 chany_top_out[9]:2 chany_top_out[9] 0.0005549917 + +*END + +*D_NET BUF_net_64 0.002381637 //LENGTH 20.200 LUMPCC 0.0001791112 DR + +*CONN +*I BUFT_RR_64:X O *L 0 *C 43.240 89.080 +*I BUFT_RR_85:A I *L 0.001766 *C 34.960 99.280 +*N BUF_net_64:2 *C 34.960 99.280 +*N BUF_net_64:3 *C 34.960 99.620 +*N BUF_net_64:4 *C 40.895 99.620 +*N BUF_net_64:5 *C 40.940 99.575 +*N BUF_net_64:6 *C 40.940 89.125 +*N BUF_net_64:7 *C 40.985 89.080 +*N BUF_net_64:8 *C 43.203 89.080 + +*CAP +0 BUFT_RR_64:X 1e-06 +1 BUFT_RR_85:A 1e-06 +2 BUF_net_64:2 5.033873e-05 +3 BUF_net_64:3 0.0004258478 +4 BUF_net_64:4 0.0004008887 +5 BUF_net_64:5 0.0005007027 +6 BUF_net_64:6 0.0005007027 +7 BUF_net_64:7 0.000161023 +8 BUF_net_64:8 0.000161023 +9 BUF_net_64:5 chany_top_in[4]:4 8.955559e-05 +10 BUF_net_64:6 chany_top_in[4]:3 8.955559e-05 + +*RES +0 BUFT_RR_64:X BUF_net_64:8 0.152 +1 BUF_net_64:2 BUFT_RR_85:A 0.152 +2 BUF_net_64:4 BUF_net_64:3 0.005299108 +3 BUF_net_64:5 BUF_net_64:4 0.0045 +4 BUF_net_64:7 BUF_net_64:6 0.0045 +5 BUF_net_64:6 BUF_net_64:5 0.009330356 +6 BUF_net_64:8 BUF_net_64:7 0.001979911 +7 BUF_net_64:3 BUF_net_64:2 0.0003035715 + +*END + +*D_NET chany_top_out[6] 0.000869445 //LENGTH 7.685 LUMPCC 0 DR + +*CONN +*I BUFT_P_98:X O *L 0 *C 6.900 96.560 +*P chany_top_out[6] O *L 0.7423 *C 5.520 102.075 +*N chany_top_out[6]:2 *C 5.520 96.568 +*N chany_top_out[6]:3 *C 5.540 96.560 +*N chany_top_out[6]:4 *C 6.433 96.560 +*N chany_top_out[6]:5 *C 6.440 96.560 +*N chany_top_out[6]:6 *C 6.900 96.560 +*N chany_top_out[6]:7 *C 6.900 96.560 + +*CAP +0 BUFT_P_98:X 1e-06 +1 chany_top_out[6] 0.0002795828 +2 chany_top_out[6]:2 0.0002795828 +3 chany_top_out[6]:3 6.908645e-05 +4 chany_top_out[6]:4 6.908645e-05 +5 chany_top_out[6]:5 7.172894e-05 +6 chany_top_out[6]:6 6.787669e-05 +7 chany_top_out[6]:7 3.150084e-05 + +*RES +0 BUFT_P_98:X chany_top_out[6]:7 0.152 +1 chany_top_out[6]:3 chany_top_out[6]:2 0.00341 +2 chany_top_out[6]:2 chany_top_out[6] 0.0008628416 +3 chany_top_out[6]:5 chany_top_out[6]:4 0.00341 +4 chany_top_out[6]:4 chany_top_out[6]:3 0.000139825 +5 chany_top_out[6]:7 chany_top_out[6]:6 0.0045 +6 chany_top_out[6]:6 chany_top_out[6]:5 0.0004107143 + +*END + +*D_NET chanx_right_in[8] 0.01684146 //LENGTH 129.105 LUMPCC 0.006169273 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 111.930 14.960 +*I ropt_mt_inst_742:A I *L 0.001767 *C 66.700 96.560 +*N chanx_right_in[8]:2 *C 66.722 96.588 +*N chanx_right_in[8]:3 *C 66.735 96.900 +*N chanx_right_in[8]:4 *C 74.475 96.900 +*N chanx_right_in[8]:5 *C 74.520 96.855 +*N chanx_right_in[8]:6 *C 74.520 83.005 +*N chanx_right_in[8]:7 *C 74.565 82.960 +*N chanx_right_in[8]:8 *C 75.395 82.960 +*N chanx_right_in[8]:9 *C 75.440 82.915 +*N chanx_right_in[8]:10 *C 75.440 64.775 +*N chanx_right_in[8]:11 *C 75.440 15.018 +*N chanx_right_in[8]:12 *C 75.448 14.960 + +*CAP +0 chanx_right_in[8] 0.0007393376 +1 ropt_mt_inst_742:A 1e-06 +2 chanx_right_in[8]:2 3.252276e-05 +3 chanx_right_in[8]:3 0.0006091826 +4 chanx_right_in[8]:4 0.0005766598 +5 chanx_right_in[8]:5 0.0007416225 +6 chanx_right_in[8]:6 0.0007416225 +7 chanx_right_in[8]:7 9.025866e-05 +8 chanx_right_in[8]:8 9.025866e-05 +9 chanx_right_in[8]:9 0.0008658187 +10 chanx_right_in[8]:10 0.003155193 +11 chanx_right_in[8]:11 0.002289375 +12 chanx_right_in[8]:12 0.0007393375 +13 chanx_right_in[8] chanx_right_in[4] 9.380199e-05 +14 chanx_right_in[8] chanx_right_in[4]:29 0.001367598 +15 chanx_right_in[8]:12 chanx_right_in[4]:28 0.001367598 +16 chanx_right_in[8]:12 chanx_right_in[4]:30 9.380199e-05 +17 chanx_right_in[8] chanx_right_in[1] 0.0009443256 +18 chanx_right_in[8]:11 chanx_right_in[1]:5 0.0003008346 +19 chanx_right_in[8]:12 chanx_right_in[1]:6 0.0009443256 +20 chanx_right_in[8]:10 chanx_right_in[1]:4 0.0003008346 +21 chanx_right_in[8]:4 ropt_net_116:2 7.573859e-05 +22 chanx_right_in[8]:5 ropt_net_116:4 2.762258e-06 +23 chanx_right_in[8]:6 ropt_net_116:5 2.762258e-06 +24 chanx_right_in[8]:9 ropt_net_116:4 2.896899e-06 +25 chanx_right_in[8]:3 ropt_net_116:3 7.573859e-05 +26 chanx_right_in[8]:10 ropt_net_116:5 2.896899e-06 +27 chanx_right_in[8]:11 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 4.011354e-05 +28 chanx_right_in[8]:10 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 4.011354e-05 +29 chanx_right_in[8]:9 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 6.251027e-05 +30 chanx_right_in[8]:10 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 6.251027e-05 +31 chanx_right_in[8]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.524658e-05 +32 chanx_right_in[8]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.524658e-05 +33 chanx_right_in[8]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.648931e-05 +34 chanx_right_in[8]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.648931e-05 +35 chanx_right_in[8]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001223187 +36 chanx_right_in[8]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001223187 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:12 0.005715591 +1 chanx_right_in[8]:2 ropt_mt_inst_742:A 0.152 +2 chanx_right_in[8]:4 chanx_right_in[8]:3 0.006910714 +3 chanx_right_in[8]:5 chanx_right_in[8]:4 0.0045 +4 chanx_right_in[8]:7 chanx_right_in[8]:6 0.0045 +5 chanx_right_in[8]:6 chanx_right_in[8]:5 0.01236607 +6 chanx_right_in[8]:8 chanx_right_in[8]:7 0.0007410714 +7 chanx_right_in[8]:9 chanx_right_in[8]:8 0.0045 +8 chanx_right_in[8]:11 chanx_right_in[8]:10 0.04442634 +9 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00341 +10 chanx_right_in[8]:3 chanx_right_in[8]:2 0.0002111487 +11 chanx_right_in[8]:10 chanx_right_in[8]:9 0.01619643 + +*END + +*D_NET chanx_right_in[13] 0.01473664 //LENGTH 85.380 LUMPCC 0.007709516 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 111.930 44.880 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.930 55.420 +*N chanx_right_in[13]:2 *C 38.968 55.420 +*N chanx_right_in[13]:3 *C 39.515 55.420 +*N chanx_right_in[13]:4 *C 39.560 55.420 +*N chanx_right_in[13]:5 *C 39.560 55.760 +*N chanx_right_in[13]:6 *C 39.568 55.760 +*N chanx_right_in[13]:7 *C 87.380 55.760 +*N chanx_right_in[13]:8 *C 87.400 55.753 +*N chanx_right_in[13]:9 *C 87.400 44.888 +*N chanx_right_in[13]:10 *C 87.420 44.880 + +*CAP +0 chanx_right_in[13] 0.0009342302 +1 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[13]:2 6.997404e-05 +3 chanx_right_in[13]:3 6.997404e-05 +4 chanx_right_in[13]:4 5.778715e-05 +5 chanx_right_in[13]:5 5.952916e-05 +6 chanx_right_in[13]:6 0.00183683 +7 chanx_right_in[13]:7 0.00183683 +8 chanx_right_in[13]:8 0.0006133695 +9 chanx_right_in[13]:9 0.0006133695 +10 chanx_right_in[13]:10 0.0009342303 +11 chanx_right_in[13] chany_top_in[14]:7 0.0008516385 +12 chanx_right_in[13]:10 chany_top_in[14]:8 0.0008516385 +13 chanx_right_in[13]:6 chany_top_in[18]:7 0.002420845 +14 chanx_right_in[13]:7 chany_top_in[18]:6 0.002420845 +15 chanx_right_in[13] chanx_right_in[0] 0.0001018877 +16 chanx_right_in[13] chanx_right_in[0]:17 0.0001725051 +17 chanx_right_in[13]:10 chanx_right_in[0]:16 0.0001725051 +18 chanx_right_in[13]:10 chanx_right_in[0]:18 0.0001018877 +19 chanx_right_in[13]:6 chany_top_in[8]:7 0.0003078816 +20 chanx_right_in[13]:7 chany_top_in[8]:6 0.0003078816 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:10 0.0038399 +1 chanx_right_in[13]:2 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[13]:3 chanx_right_in[13]:2 0.0004888393 +3 chanx_right_in[13]:4 chanx_right_in[13]:3 0.0045 +4 chanx_right_in[13]:5 chanx_right_in[13]:4 0.0001634615 +5 chanx_right_in[13]:6 chanx_right_in[13]:5 0.00341 +6 chanx_right_in[13]:7 chanx_right_in[13]:6 0.007490624 +7 chanx_right_in[13]:8 chanx_right_in[13]:7 0.00341 +8 chanx_right_in[13]:10 chanx_right_in[13]:9 0.00341 +9 chanx_right_in[13]:9 chanx_right_in[13]:8 0.001702183 + +*END + +*D_NET right_top_grid_pin_47_[0] 0.005504516 //LENGTH 45.860 LUMPCC 0.0005518253 DR + +*CONN +*P right_top_grid_pin_47_[0] I *L 0.29796 *C 83.410 90.440 +*I mux_right_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.490 86.020 +*I mux_right_track_6\/mux_l1_in_1_:A0 I *L 0.001631 *C 79.410 82.280 +*I mux_right_track_18\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.055 53.380 +*N right_top_grid_pin_47_[0]:4 *C 82.055 53.380 +*N right_top_grid_pin_47_[0]:5 *C 81.880 53.380 +*N right_top_grid_pin_47_[0]:6 *C 81.880 53.425 +*N right_top_grid_pin_47_[0]:7 *C 79.448 82.280 +*N right_top_grid_pin_47_[0]:8 *C 81.835 82.280 +*N right_top_grid_pin_47_[0]:9 *C 81.880 82.280 +*N right_top_grid_pin_47_[0]:10 *C 78.528 86.020 +*N right_top_grid_pin_47_[0]:11 *C 81.835 86.020 +*N right_top_grid_pin_47_[0]:12 *C 81.880 86.020 +*N right_top_grid_pin_47_[0]:13 *C 81.880 90.383 +*N right_top_grid_pin_47_[0]:14 *C 81.888 90.440 + +*CAP +0 right_top_grid_pin_47_[0] 0.0001161175 +1 mux_right_track_2\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_6\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_18\/mux_l1_in_0_:A0 1e-06 +4 right_top_grid_pin_47_[0]:4 5.342571e-05 +5 right_top_grid_pin_47_[0]:5 5.294607e-05 +6 right_top_grid_pin_47_[0]:6 0.001553428 +7 right_top_grid_pin_47_[0]:7 0.0001816957 +8 right_top_grid_pin_47_[0]:8 0.0001816957 +9 right_top_grid_pin_47_[0]:9 0.001725367 +10 right_top_grid_pin_47_[0]:10 0.0002204663 +11 right_top_grid_pin_47_[0]:11 0.0002204663 +12 right_top_grid_pin_47_[0]:12 0.0003500651 +13 right_top_grid_pin_47_[0]:13 0.0001778991 +14 right_top_grid_pin_47_[0]:14 0.0001161175 +15 right_top_grid_pin_47_[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001574902 +16 right_top_grid_pin_47_[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001574902 +17 right_top_grid_pin_47_[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.313553e-05 +18 right_top_grid_pin_47_[0]:12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.313553e-05 +19 right_top_grid_pin_47_[0]:12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.528697e-05 +20 right_top_grid_pin_47_[0]:13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.528697e-05 + +*RES +0 right_top_grid_pin_47_[0] right_top_grid_pin_47_[0]:14 0.000238525 +1 right_top_grid_pin_47_[0]:5 right_top_grid_pin_47_[0]:4 9.51087e-05 +2 right_top_grid_pin_47_[0]:6 right_top_grid_pin_47_[0]:5 0.0045 +3 right_top_grid_pin_47_[0]:4 mux_right_track_18\/mux_l1_in_0_:A0 0.152 +4 right_top_grid_pin_47_[0]:8 right_top_grid_pin_47_[0]:7 0.002131696 +5 right_top_grid_pin_47_[0]:9 right_top_grid_pin_47_[0]:8 0.0045 +6 right_top_grid_pin_47_[0]:9 right_top_grid_pin_47_[0]:6 0.02576339 +7 right_top_grid_pin_47_[0]:7 mux_right_track_6\/mux_l1_in_1_:A0 0.152 +8 right_top_grid_pin_47_[0]:11 right_top_grid_pin_47_[0]:10 0.002953125 +9 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:11 0.0045 +10 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:9 0.003339286 +11 right_top_grid_pin_47_[0]:10 mux_right_track_2\/mux_l1_in_1_:A0 0.152 +12 right_top_grid_pin_47_[0]:13 right_top_grid_pin_47_[0]:12 0.003895089 +13 right_top_grid_pin_47_[0]:14 right_top_grid_pin_47_[0]:13 0.00341 + +*END + +*D_NET chanx_right_out[3] 0.002408461 //LENGTH 15.270 LUMPCC 0 DR + +*CONN +*I mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 99.360 69.360 +*P chanx_right_out[3] O *L 0.7423 *C 111.855 68.000 +*N chanx_right_out[3]:2 *C 107.640 68.000 +*N chanx_right_out[3]:3 *C 107.640 68.680 +*N chanx_right_out[3]:4 *C 104.428 68.680 +*N chanx_right_out[3]:5 *C 104.420 68.737 +*N chanx_right_out[3]:6 *C 104.420 69.315 +*N chanx_right_out[3]:7 *C 104.375 69.360 +*N chanx_right_out[3]:8 *C 99.398 69.360 + +*CAP +0 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[3] 0.0003843138 +2 chanx_right_out[3]:2 0.0004412367 +3 chanx_right_out[3]:3 0.00034116 +4 chanx_right_out[3]:4 0.0002842371 +5 chanx_right_out[3]:5 6.701313e-05 +6 chanx_right_out[3]:6 6.701313e-05 +7 chanx_right_out[3]:7 0.0004112438 +8 chanx_right_out[3]:8 0.0004112438 + +*RES +0 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[3]:8 0.152 +1 chanx_right_out[3]:5 chanx_right_out[3]:4 0.00341 +2 chanx_right_out[3]:4 chanx_right_out[3]:3 0.0005032916 +3 chanx_right_out[3]:7 chanx_right_out[3]:6 0.0045 +4 chanx_right_out[3]:6 chanx_right_out[3]:5 0.000515625 +5 chanx_right_out[3]:8 chanx_right_out[3]:7 0.004444197 +6 chanx_right_out[3]:3 chanx_right_out[3]:2 0.0001065333 +7 chanx_right_out[3]:2 chanx_right_out[3] 0.00066035 + +*END + +*D_NET chanx_right_out[13] 0.00251527 //LENGTH 18.200 LUMPCC 0 DR + +*CONN +*I mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 106.780 69.700 +*P chanx_right_out[13] O *L 0.7423 *C 111.930 61.200 +*N chanx_right_out[13]:2 *C 108.910 68.680 +*N chanx_right_out[13]:3 *C 107.850 66.300 +*N chanx_right_out[13]:4 *C 108.568 61.200 +*N chanx_right_out[13]:5 *C 108.560 61.258 +*N chanx_right_out[13]:6 *C 108.560 66.243 +*N chanx_right_out[13]:7 *C 108.558 66.300 +*N chanx_right_out[13]:8 *C 108.560 66.308 +*N chanx_right_out[13]:9 *C 108.560 68.672 +*N chanx_right_out[13]:10 *C 108.562 68.680 +*N chanx_right_out[13]:11 *C 108.560 68.680 +*N chanx_right_out[13]:12 *C 108.515 68.680 +*N chanx_right_out[13]:13 *C 106.305 68.680 +*N chanx_right_out[13]:14 *C 106.260 68.725 +*N chanx_right_out[13]:15 *C 106.260 69.655 +*N chanx_right_out[13]:16 *C 106.305 69.700 +*N chanx_right_out[13]:17 *C 106.743 69.700 + +*CAP +0 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[13] 0.0002231902 +2 chanx_right_out[13]:2 9.548295e-05 +3 chanx_right_out[13]:3 0.0001091556 +4 chanx_right_out[13]:4 0.0002231902 +5 chanx_right_out[13]:5 0.0002937671 +6 chanx_right_out[13]:6 0.0002937671 +7 chanx_right_out[13]:7 0.0001091556 +8 chanx_right_out[13]:8 0.0001656764 +9 chanx_right_out[13]:9 0.0001656764 +10 chanx_right_out[13]:10 9.548295e-05 +11 chanx_right_out[13]:11 3.566153e-05 +12 chanx_right_out[13]:12 0.0002072281 +13 chanx_right_out[13]:13 0.0002072281 +14 chanx_right_out[13]:14 7.580495e-05 +15 chanx_right_out[13]:15 7.580495e-05 +16 chanx_right_out[13]:16 6.899893e-05 +17 chanx_right_out[13]:17 6.899893e-05 + +*RES +0 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[13]:17 0.152 +1 chanx_right_out[13]:17 chanx_right_out[13]:16 0.000390625 +2 chanx_right_out[13]:16 chanx_right_out[13]:15 0.0045 +3 chanx_right_out[13]:15 chanx_right_out[13]:14 0.0008303572 +4 chanx_right_out[13]:13 chanx_right_out[13]:12 0.001973215 +5 chanx_right_out[13]:14 chanx_right_out[13]:13 0.0045 +6 chanx_right_out[13]:12 chanx_right_out[13]:11 0.0045 +7 chanx_right_out[13]:11 chanx_right_out[13]:10 0.00341 +8 chanx_right_out[13]:10 chanx_right_out[13]:9 0.00341 +9 chanx_right_out[13]:10 chanx_right_out[13]:2 5.103906e-05 +10 chanx_right_out[13]:9 chanx_right_out[13]:8 0.0003705166 +11 chanx_right_out[13]:7 chanx_right_out[13]:6 0.00341 +12 chanx_right_out[13]:7 chanx_right_out[13]:3 0.0001039141 +13 chanx_right_out[13]:8 chanx_right_out[13]:7 0.00341 +14 chanx_right_out[13]:6 chanx_right_out[13]:5 0.004450893 +15 chanx_right_out[13]:5 chanx_right_out[13]:4 0.00341 +16 chanx_right_out[13]:4 chanx_right_out[13] 0.0005267916 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.002095132 //LENGTH 17.060 LUMPCC 0.0001431384 DR + +*CONN +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 41.245 85.680 +*I mux_right_track_10\/mux_l1_in_0_:S I *L 0.00357 *C 41.040 82.960 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 33.295 77.180 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 33.333 77.180 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 40.895 77.180 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 40.940 77.225 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 40.940 82.960 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 40.940 82.960 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 40.940 85.635 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 40.940 85.680 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 41.245 85.680 + +*CAP +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_10\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 0.0004807214 +4 mux_tree_tapbuf_size2_4_sram[0]:4 0.0004807214 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.0002519026 +6 mux_tree_tapbuf_size2_4_sram[0]:6 3.253942e-05 +7 mux_tree_tapbuf_size2_4_sram[0]:7 0.0004450618 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.0001612004 +9 mux_tree_tapbuf_size2_4_sram[0]:9 5.021828e-05 +10 mux_tree_tapbuf_size2_4_sram[0]:10 4.662777e-05 +11 mux_tree_tapbuf_size2_4_sram[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.156922e-05 +12 mux_tree_tapbuf_size2_4_sram[0]:7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.156922e-05 + +*RES +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:10 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.0045 +2 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.002388393 +3 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 0.0001657609 +4 mux_tree_tapbuf_size2_4_sram[0]:4 mux_tree_tapbuf_size2_4_sram[0]:3 0.006752233 +5 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_4_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_4_sram[0]:3 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_4_sram[0]:6 mux_right_track_10\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:6 0.0045 +9 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:5 0.005120535 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_6_ccff_tail[0] 0.000540222 //LENGTH 3.620 LUMPCC 8.022707e-05 DR + +*CONN +*I mem_right_track_14\/FTB_7__28:X O *L 0 *C 74.745 52.700 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 74.695 49.980 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 *C 74.695 49.980 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 *C 74.520 49.980 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 *C 74.520 50.025 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 *C 74.520 52.655 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 *C 74.520 52.700 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 *C 74.745 52.700 + +*CAP +0 mem_right_track_14\/FTB_7__28:X 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 5.26667e-05 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 5.508311e-05 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.0001244318 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0001244318 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 5.189796e-05 +7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 4.948364e-05 +8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chanx_right_in[8]:10 4.011354e-05 +9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chanx_right_in[8]:11 4.011354e-05 + +*RES +0 mem_right_track_14\/FTB_7__28:X mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[1] 0.003485238 //LENGTH 28.205 LUMPCC 8.551873e-05 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.345 98.940 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 65.945 98.940 +*I mux_right_track_6\/mux_l2_in_0_:S I *L 0.00357 *C 79.480 90.440 +*I mux_right_track_6\/mux_l2_in_1_:S I *L 0.00357 *C 80.160 89.080 +*N mux_tree_tapbuf_size5_1_sram[1]:4 *C 80.123 89.080 +*N mux_tree_tapbuf_size5_1_sram[1]:5 *C 79.625 89.080 +*N mux_tree_tapbuf_size5_1_sram[1]:6 *C 79.580 89.125 +*N mux_tree_tapbuf_size5_1_sram[1]:7 *C 79.480 90.440 +*N mux_tree_tapbuf_size5_1_sram[1]:8 *C 79.580 90.395 +*N mux_tree_tapbuf_size5_1_sram[1]:9 *C 79.120 90.440 +*N mux_tree_tapbuf_size5_1_sram[1]:10 *C 65.983 98.940 +*N mux_tree_tapbuf_size5_1_sram[1]:11 *C 72.635 98.940 +*N mux_tree_tapbuf_size5_1_sram[1]:12 *C 72.680 98.940 +*N mux_tree_tapbuf_size5_1_sram[1]:13 *C 73.088 98.940 +*N mux_tree_tapbuf_size5_1_sram[1]:14 *C 73.105 99.240 +*N mux_tree_tapbuf_size5_1_sram[1]:15 *C 73.148 99.280 +*N mux_tree_tapbuf_size5_1_sram[1]:16 *C 79.112 99.280 +*N mux_tree_tapbuf_size5_1_sram[1]:17 *C 79.120 99.280 +*N mux_tree_tapbuf_size5_1_sram[1]:18 *C 79.120 98.895 +*N mux_tree_tapbuf_size5_1_sram[1]:19 *C 79.165 98.940 +*N mux_tree_tapbuf_size5_1_sram[1]:20 *C 80.308 98.940 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_6\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_6\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[1]:4 7.199944e-05 +5 mux_tree_tapbuf_size5_1_sram[1]:5 7.199944e-05 +6 mux_tree_tapbuf_size5_1_sram[1]:6 8.931677e-05 +7 mux_tree_tapbuf_size5_1_sram[1]:7 2.993574e-05 +8 mux_tree_tapbuf_size5_1_sram[1]:8 0.0001207778 +9 mux_tree_tapbuf_size5_1_sram[1]:9 0.0004609449 +10 mux_tree_tapbuf_size5_1_sram[1]:10 0.0004975893 +11 mux_tree_tapbuf_size5_1_sram[1]:11 0.0004975893 +12 mux_tree_tapbuf_size5_1_sram[1]:12 6.261496e-05 +13 mux_tree_tapbuf_size5_1_sram[1]:13 7.178848e-05 +14 mux_tree_tapbuf_size5_1_sram[1]:14 3.95319e-05 +15 mux_tree_tapbuf_size5_1_sram[1]:15 0.0003586244 +16 mux_tree_tapbuf_size5_1_sram[1]:16 0.0003586244 +17 mux_tree_tapbuf_size5_1_sram[1]:17 4.832832e-05 +18 mux_tree_tapbuf_size5_1_sram[1]:18 0.0004461443 +19 mux_tree_tapbuf_size5_1_sram[1]:19 8.495484e-05 +20 mux_tree_tapbuf_size5_1_sram[1]:20 8.495484e-05 +21 mux_tree_tapbuf_size5_1_sram[1]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.261947e-06 +22 mux_tree_tapbuf_size5_1_sram[1]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.261947e-06 +23 mux_tree_tapbuf_size5_1_sram[1]:18 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.949742e-05 +24 mux_tree_tapbuf_size5_1_sram[1]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.949742e-05 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_1_sram[1]:20 0.152 +1 mux_tree_tapbuf_size5_1_sram[1]:4 mux_right_track_6\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size5_1_sram[1]:5 mux_tree_tapbuf_size5_1_sram[1]:4 0.0004441964 +3 mux_tree_tapbuf_size5_1_sram[1]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size5_1_sram[1]:7 mux_right_track_6\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size5_1_sram[1]:8 mux_tree_tapbuf_size5_1_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size5_1_sram[1]:8 mux_tree_tapbuf_size5_1_sram[1]:6 0.001133929 +7 mux_tree_tapbuf_size5_1_sram[1]:17 mux_tree_tapbuf_size5_1_sram[1]:16 0.00341 +8 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:15 0.0009345167 +9 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:13 0.0001785715 +10 mux_tree_tapbuf_size5_1_sram[1]:15 mux_tree_tapbuf_size5_1_sram[1]:14 0.00341 +11 mux_tree_tapbuf_size5_1_sram[1]:11 mux_tree_tapbuf_size5_1_sram[1]:10 0.005939732 +12 mux_tree_tapbuf_size5_1_sram[1]:12 mux_tree_tapbuf_size5_1_sram[1]:11 0.0045 +13 mux_tree_tapbuf_size5_1_sram[1]:10 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size5_1_sram[1]:19 mux_tree_tapbuf_size5_1_sram[1]:18 0.0045 +15 mux_tree_tapbuf_size5_1_sram[1]:18 mux_tree_tapbuf_size5_1_sram[1]:17 0.0001850962 +16 mux_tree_tapbuf_size5_1_sram[1]:18 mux_tree_tapbuf_size5_1_sram[1]:9 0.007549108 +17 mux_tree_tapbuf_size5_1_sram[1]:20 mux_tree_tapbuf_size5_1_sram[1]:19 0.001020089 +18 mux_tree_tapbuf_size5_1_sram[1]:13 mux_tree_tapbuf_size5_1_sram[1]:12 0.0003638393 +19 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:8 0.0004107143 + +*END + +*D_NET mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001452392 //LENGTH 12.730 LUMPCC 0 DR + +*CONN +*I mux_right_track_18\/mux_l2_in_0_:X O *L 0 *C 90.445 44.540 +*I mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.340 44.735 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 102.303 44.830 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 44.880 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 44.540 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 90.483 44.540 + +*CAP +0 mux_right_track_18\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005754819 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0005995319 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000149714 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000125664 + +*RES +0 mux_right_track_18\/mux_l2_in_0_:X mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.152 +1 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001354911 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003035715 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.009198661 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001556166 //LENGTH 11.375 LUMPCC 0.0005447727 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_2_:X O *L 0 *C 63.655 75.140 +*I mux_right_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 56.580 77.860 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 56.580 77.875 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 56.580 78.200 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 56.580 78.155 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 56.580 75.185 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 56.625 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 63.617 75.140 + +*CAP +0 mux_right_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.526271e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.763988e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000190403 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000190403 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002628427 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002628427 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size6_0_sram[0]:15 0.0002723863 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_0_sram[0]:18 0.0002723863 + +*RES +0 mux_right_track_0\/mux_l1_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.006243304 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002651786 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001766305 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_0\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.005299659 //LENGTH 41.655 LUMPCC 0.001745407 DR + +*CONN +*I mux_right_track_6\/mux_l3_in_0_:X O *L 0 *C 80.785 93.160 +*I mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 97.695 69.510 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 97.657 69.413 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 92.460 69.360 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 92.460 69.700 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 81.005 69.700 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 80.960 69.745 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 80.960 93.115 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 80.960 93.160 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 80.785 93.160 + +*CAP +0 mux_right_track_6\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002008853 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002250789 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0006730658 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0006488722 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0008493124 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0008493124 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.243858e-05 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.328703e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_42_[0]:18 2.899511e-06 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_42_[0]:22 1.945317e-05 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_42_[0]:24 4.845085e-05 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 right_top_grid_pin_42_[0]:25 0.0002026832 +14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 right_top_grid_pin_42_[0]:19 2.899511e-06 +15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 right_top_grid_pin_42_[0]:23 1.945317e-05 +16 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 right_top_grid_pin_42_[0]:25 4.845085e-05 +17 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 right_top_grid_pin_42_[0]:24 0.0002026832 +18 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 right_top_grid_pin_47_[0]:9 0.0001574902 +19 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 right_top_grid_pin_47_[0]:12 5.313553e-05 +20 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 right_top_grid_pin_47_[0]:13 6.528697e-05 +21 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_47_[0]:6 0.0001574902 +22 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_47_[0]:9 5.313553e-05 +23 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_47_[0]:12 6.528697e-05 +24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size5_1_sram[0]:21 0.0002180662 +25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size5_1_sram[0]:22 0.0002180662 +26 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:8 0.0001052379 +27 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:9 0.0001052379 + +*RES +0 mux_right_track_6\/mux_l3_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 9.51087e-05 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.02086607 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.01022768 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.004640625 + +*END + +*D_NET chany_top_out[10] 0.001407315 //LENGTH 9.665 LUMPCC 0.0002328304 DR + +*CONN +*I BUFT_RR_78:X O *L 0 *C 42.055 97.240 +*P chany_top_out[10] O *L 0.7423 *C 46.460 102.035 +*N chany_top_out[10]:2 *C 46.460 97.285 +*N chany_top_out[10]:3 *C 46.415 97.240 +*N chany_top_out[10]:4 *C 42.093 97.240 + +*CAP +0 BUFT_RR_78:X 1e-06 +1 chany_top_out[10] 0.0003283932 +2 chany_top_out[10]:2 0.0003283932 +3 chany_top_out[10]:3 0.0002583491 +4 chany_top_out[10]:4 0.0002583491 +5 chany_top_out[10]:4 ropt_net_125:8 0.0001164152 +6 chany_top_out[10]:3 ropt_net_125:7 0.0001164152 + +*RES +0 BUFT_RR_78:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.003859375 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.004241072 + +*END + +*D_NET chanx_right_in[9] 0.01532799 //LENGTH 119.880 LUMPCC 0.003997904 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 111.855 72.080 +*I ropt_mt_inst_746:A I *L 0.001767 *C 22.080 96.560 +*N chanx_right_in[9]:2 *C 22.103 96.532 +*N chanx_right_in[9]:3 *C 22.115 96.220 +*N chanx_right_in[9]:4 *C 24.335 96.220 +*N chanx_right_in[9]:5 *C 24.380 96.175 +*N chanx_right_in[9]:6 *C 24.380 91.165 +*N chanx_right_in[9]:7 *C 24.425 91.120 +*N chanx_right_in[9]:8 *C 29.855 91.120 +*N chanx_right_in[9]:9 *C 29.900 91.075 +*N chanx_right_in[9]:10 *C 29.900 83.017 +*N chanx_right_in[9]:11 *C 29.908 82.960 +*N chanx_right_in[9]:12 *C 82.780 82.960 +*N chanx_right_in[9]:13 *C 82.800 82.953 +*N chanx_right_in[9]:14 *C 82.800 70.728 +*N chanx_right_in[9]:15 *C 82.820 70.720 +*N chanx_right_in[9]:16 *C 105.800 70.720 +*N chanx_right_in[9]:17 *C 105.800 72.080 + +*CAP +0 chanx_right_in[9] 0.0003593828 +1 ropt_mt_inst_746:A 1e-06 +2 chanx_right_in[9]:2 2.989863e-05 +3 chanx_right_in[9]:3 0.0001803778 +4 chanx_right_in[9]:4 0.0001504791 +5 chanx_right_in[9]:5 0.0002715825 +6 chanx_right_in[9]:6 0.0002715825 +7 chanx_right_in[9]:7 0.0003024692 +8 chanx_right_in[9]:8 0.0003024692 +9 chanx_right_in[9]:9 0.0005329316 +10 chanx_right_in[9]:10 0.0005329316 +11 chanx_right_in[9]:11 0.002769799 +12 chanx_right_in[9]:12 0.002769799 +13 chanx_right_in[9]:13 0.0004767489 +14 chanx_right_in[9]:14 0.0004767489 +15 chanx_right_in[9]:15 0.0006763624 +16 chanx_right_in[9]:16 0.0007712513 +17 chanx_right_in[9]:17 0.0004542718 +18 chanx_right_in[9]:11 chany_top_in[16]:21 0.0002414191 +19 chanx_right_in[9]:12 chany_top_in[16]:20 0.0002414191 +20 chanx_right_in[9]:15 chany_top_in[16]:8 5.826055e-06 +21 chanx_right_in[9]:16 chany_top_in[16]:7 5.826055e-06 +22 chanx_right_in[9]:16 chany_top_in[16]:14 6.286045e-06 +23 chanx_right_in[9]:17 chany_top_in[16]:15 6.286045e-06 +24 chanx_right_in[9]:11 chanx_right_in[18]:13 3.779759e-06 +25 chanx_right_in[9]:12 chanx_right_in[18]:14 3.779759e-06 +26 chanx_right_in[9]:13 chanx_right_in[18]:15 0.0003127194 +27 chanx_right_in[9]:14 chanx_right_in[18]:16 0.0003127194 +28 chanx_right_in[9]:11 right_top_grid_pin_46_[0]:21 9.759686e-06 +29 chanx_right_in[9]:12 right_top_grid_pin_46_[0]:22 9.759686e-06 +30 chanx_right_in[9]:13 right_top_grid_pin_46_[0]:20 4.587262e-05 +31 chanx_right_in[9]:15 right_top_grid_pin_46_[0]:17 0.0002750533 +32 chanx_right_in[9]:14 right_top_grid_pin_46_[0]:19 4.587262e-05 +33 chanx_right_in[9]:16 right_top_grid_pin_46_[0]:7 0.0002750533 +34 chanx_right_in[9]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003116109 +35 chanx_right_in[9]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003116109 +36 chanx_right_in[9]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004113045 +37 chanx_right_in[9]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004113045 +38 chanx_right_in[9]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0003066987 +39 chanx_right_in[9]:12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0003066987 +40 chanx_right_in[9]:11 BUF_net_57:9 6.862178e-05 +41 chanx_right_in[9]:12 BUF_net_57:10 6.862178e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:17 0.0009486165 +1 chanx_right_in[9]:2 ropt_mt_inst_746:A 0.152 +2 chanx_right_in[9]:4 chanx_right_in[9]:3 0.001982143 +3 chanx_right_in[9]:5 chanx_right_in[9]:4 0.0045 +4 chanx_right_in[9]:7 chanx_right_in[9]:6 0.0045 +5 chanx_right_in[9]:6 chanx_right_in[9]:5 0.004473215 +6 chanx_right_in[9]:8 chanx_right_in[9]:7 0.004848214 +7 chanx_right_in[9]:9 chanx_right_in[9]:8 0.0045 +8 chanx_right_in[9]:10 chanx_right_in[9]:9 0.007194196 +9 chanx_right_in[9]:11 chanx_right_in[9]:10 0.00341 +10 chanx_right_in[9]:12 chanx_right_in[9]:11 0.008283358 +11 chanx_right_in[9]:13 chanx_right_in[9]:12 0.00341 +12 chanx_right_in[9]:15 chanx_right_in[9]:14 0.00341 +13 chanx_right_in[9]:14 chanx_right_in[9]:13 0.00191525 +14 chanx_right_in[9]:3 chanx_right_in[9]:2 0.0002111487 +15 chanx_right_in[9]:16 chanx_right_in[9]:15 0.0036002 +16 chanx_right_in[9]:17 chanx_right_in[9]:16 0.0002130666 + +*END + +*D_NET chany_top_out[0] 0.006300561 //LENGTH 53.040 LUMPCC 0.001403299 DR + +*CONN +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 48.705 55.420 +*P chany_top_out[0] O *L 0.7423 *C 42.780 102.070 +*N chany_top_out[0]:2 *C 42.780 55.465 +*N chany_top_out[0]:3 *C 42.825 55.420 +*N chany_top_out[0]:4 *C 48.668 55.420 + +*CAP +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[0] 0.002085957 +2 chany_top_out[0]:2 0.002085957 +3 chany_top_out[0]:3 0.0003621738 +4 chany_top_out[0]:4 0.0003621738 +5 chany_top_out[0] mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 9.155131e-05 +6 chany_top_out[0]:2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 9.155131e-05 +7 chany_top_out[0] mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0006100982 +8 chany_top_out[0]:2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0006100982 + +*RES +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[0]:4 0.152 +1 chany_top_out[0]:4 chany_top_out[0]:3 0.005216518 +2 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +3 chany_top_out[0]:2 chany_top_out[0] 0.04161161 + +*END + +*D_NET chany_top_out[4] 0.001750931 //LENGTH 16.255 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 34.500 88.400 +*P chany_top_out[4] O *L 0.7423 *C 36.340 102.070 +*N chany_top_out[4]:2 *C 36.340 94.520 +*N chany_top_out[4]:3 *C 35.420 94.520 +*N chany_top_out[4]:4 *C 35.420 88.445 +*N chany_top_out[4]:5 *C 35.375 88.400 +*N chany_top_out[4]:6 *C 34.538 88.400 + +*CAP +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[4] 0.000377314 +2 chany_top_out[4]:2 0.0004318141 +3 chany_top_out[4]:3 0.0004296753 +4 chany_top_out[4]:4 0.0003751752 +5 chany_top_out[4]:5 6.797598e-05 +6 chany_top_out[4]:6 6.797598e-05 + +*RES +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[4]:6 0.152 +1 chany_top_out[4]:5 chany_top_out[4]:4 0.0045 +2 chany_top_out[4]:4 chany_top_out[4]:3 0.005424107 +3 chany_top_out[4]:6 chany_top_out[4]:5 0.0007477679 +4 chany_top_out[4]:3 chany_top_out[4]:2 0.0008214286 +5 chany_top_out[4]:2 chany_top_out[4] 0.006741072 + +*END + +*D_NET chanx_right_out[2] 0.004011307 //LENGTH 40.185 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 99.420 33.660 +*P chanx_right_out[2] O *L 0.7423 *C 111.930 6.800 +*N chanx_right_out[2]:2 *C 99.828 6.800 +*N chanx_right_out[2]:3 *C 99.820 6.857 +*N chanx_right_out[2]:4 *C 99.820 33.615 +*N chanx_right_out[2]:5 *C 99.797 33.660 +*N chanx_right_out[2]:6 *C 99.435 33.660 + +*CAP +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[2] 0.0007010715 +2 chanx_right_out[2]:2 0.0007010715 +3 chanx_right_out[2]:3 0.001258793 +4 chanx_right_out[2]:4 0.001258793 +5 chanx_right_out[2]:5 4.528885e-05 +6 chanx_right_out[2]:6 4.528885e-05 + +*RES +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[2]:6 0.152 +1 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +2 chanx_right_out[2]:2 chanx_right_out[2] 0.001896058 +3 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0045 +4 chanx_right_out[2]:4 chanx_right_out[2]:3 0.02389063 +5 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0001970109 + +*END + +*D_NET chanx_right_out[6] 0.003904588 //LENGTH 31.505 LUMPCC 0 DR + +*CONN +*I mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 92.060 39.100 +*P chanx_right_out[6] O *L 0.7423 *C 111.930 28.560 +*N chanx_right_out[6]:2 *C 109.028 28.560 +*N chanx_right_out[6]:3 *C 109.020 28.617 +*N chanx_right_out[6]:4 *C 109.020 38.715 +*N chanx_right_out[6]:5 *C 108.975 38.760 +*N chanx_right_out[6]:6 *C 93.840 38.760 +*N chanx_right_out[6]:7 *C 93.840 39.100 +*N chanx_right_out[6]:8 *C 92.098 39.100 + +*CAP +0 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[6] 0.000199328 +2 chanx_right_out[6]:2 0.000199328 +3 chanx_right_out[6]:3 0.0005662377 +4 chanx_right_out[6]:4 0.0005662377 +5 chanx_right_out[6]:5 0.001018651 +6 chanx_right_out[6]:6 0.001042011 +7 chanx_right_out[6]:7 0.0001675776 +8 chanx_right_out[6]:8 0.0001442171 + +*RES +0 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[6]:8 0.152 +1 chanx_right_out[6]:8 chanx_right_out[6]:7 0.001555804 +2 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +3 chanx_right_out[6]:4 chanx_right_out[6]:3 0.009015625 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 0.0004547249 +6 chanx_right_out[6]:7 chanx_right_out[6]:6 0.0003035715 +7 chanx_right_out[6]:6 chanx_right_out[6]:5 0.01351339 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.002009118 //LENGTH 16.230 LUMPCC 0.0001026591 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.960 37.060 +*I mem_top_track_0\/FTB_1__22:A I *L 0.001746 *C 70.840 36.720 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 74.180 41.480 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 74.142 41.480 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 73.645 41.480 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 73.600 41.435 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 70.840 36.720 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 70.840 36.675 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 70.840 36.040 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 73.600 36.040 +*N mux_tree_tapbuf_size2_0_sram[1]:10 *C 73.600 37.060 +*N mux_tree_tapbuf_size2_0_sram[1]:11 *C 74.060 37.060 +*N mux_tree_tapbuf_size2_0_sram[1]:12 *C 74.105 37.060 +*N mux_tree_tapbuf_size2_0_sram[1]:13 *C 78.922 37.060 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_0\/FTB_1__22:A 1e-06 +2 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 5.885787e-05 +4 mux_tree_tapbuf_size2_0_sram[1]:4 5.885787e-05 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.0002336701 +6 mux_tree_tapbuf_size2_0_sram[1]:6 3.30153e-05 +7 mux_tree_tapbuf_size2_0_sram[1]:7 4.628004e-05 +8 mux_tree_tapbuf_size2_0_sram[1]:8 0.0001913905 +9 mux_tree_tapbuf_size2_0_sram[1]:9 0.0002147993 +10 mux_tree_tapbuf_size2_0_sram[1]:10 0.0003385454 +11 mux_tree_tapbuf_size2_0_sram[1]:11 6.875715e-05 +12 mux_tree_tapbuf_size2_0_sram[1]:12 0.0003296426 +13 mux_tree_tapbuf_size2_0_sram[1]:13 0.0003296426 +14 mux_tree_tapbuf_size2_0_sram[1]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.132957e-05 +15 mux_tree_tapbuf_size2_0_sram[1]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.132957e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.0004441965 +2 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size2_0_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_0_sram[1]:3 mux_top_track_0\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_0_sram[1]:6 mem_top_track_0\/FTB_1__22:A 0.152 +5 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_0_sram[1]:13 mux_tree_tapbuf_size2_0_sram[1]:12 0.00430134 +7 mux_tree_tapbuf_size2_0_sram[1]:12 mux_tree_tapbuf_size2_0_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size2_0_sram[1]:11 mux_tree_tapbuf_size2_0_sram[1]:10 0.0004107143 +9 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.0005669643 +10 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 0.002464286 +11 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:9 0.0009107143 +12 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:5 0.00390625 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[1] 0.001832848 //LENGTH 13.545 LUMPCC 0.0005702917 DR + +*CONN +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 57.170 57.800 +*I mux_right_track_12\/mux_l2_in_0_:S I *L 0.00357 *C 51.880 53.040 +*I mem_right_track_12\/FTB_6__27:A I *L 0.001746 *C 59.340 55.760 +*N mux_tree_tapbuf_size2_5_sram[1]:3 *C 59.318 55.733 +*N mux_tree_tapbuf_size2_5_sram[1]:4 *C 59.305 55.420 +*N mux_tree_tapbuf_size2_5_sram[1]:5 *C 51.880 53.040 +*N mux_tree_tapbuf_size2_5_sram[1]:6 *C 51.980 53.085 +*N mux_tree_tapbuf_size2_5_sram[1]:7 *C 51.980 55.375 +*N mux_tree_tapbuf_size2_5_sram[1]:8 *C 52.025 55.420 +*N mux_tree_tapbuf_size2_5_sram[1]:9 *C 57.040 55.420 +*N mux_tree_tapbuf_size2_5_sram[1]:10 *C 57.040 55.465 +*N mux_tree_tapbuf_size2_5_sram[1]:11 *C 57.040 57.755 +*N mux_tree_tapbuf_size2_5_sram[1]:12 *C 57.040 57.800 + +*CAP +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_12\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_12\/FTB_6__27:A 1e-06 +3 mux_tree_tapbuf_size2_5_sram[1]:3 3.329249e-05 +4 mux_tree_tapbuf_size2_5_sram[1]:4 0.0001154536 +5 mux_tree_tapbuf_size2_5_sram[1]:5 2.68402e-05 +6 mux_tree_tapbuf_size2_5_sram[1]:6 0.0001449729 +7 mux_tree_tapbuf_size2_5_sram[1]:7 0.0001449729 +8 mux_tree_tapbuf_size2_5_sram[1]:8 0.000177723 +9 mux_tree_tapbuf_size2_5_sram[1]:9 0.0002904075 +10 mux_tree_tapbuf_size2_5_sram[1]:10 0.0001473432 +11 mux_tree_tapbuf_size2_5_sram[1]:11 0.0001473432 +12 mux_tree_tapbuf_size2_5_sram[1]:12 3.120727e-05 +13 mux_tree_tapbuf_size2_5_sram[1]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.977884e-05 +14 mux_tree_tapbuf_size2_5_sram[1]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000195367 +15 mux_tree_tapbuf_size2_5_sram[1]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000195367 +16 mux_tree_tapbuf_size2_5_sram[1]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.977884e-05 + +*RES +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_5_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_5_sram[1]:12 mux_tree_tapbuf_size2_5_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size2_5_sram[1]:11 mux_tree_tapbuf_size2_5_sram[1]:10 0.002044643 +3 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:8 0.004477679 +4 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:4 0.002022321 +5 mux_tree_tapbuf_size2_5_sram[1]:10 mux_tree_tapbuf_size2_5_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_5_sram[1]:3 mem_right_track_12\/FTB_6__27:A 0.152 +7 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:6 0.002044643 +9 mux_tree_tapbuf_size2_5_sram[1]:5 mux_right_track_12\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size2_5_sram[1]:6 mux_tree_tapbuf_size2_5_sram[1]:5 0.0045 +11 mux_tree_tapbuf_size2_5_sram[1]:4 mux_tree_tapbuf_size2_5_sram[1]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.0006255732 //LENGTH 5.195 LUMPCC 8.428339e-05 DR + +*CONN +*I mem_top_track_8\/FTB_3__24:X O *L 0 *C 36.620 50.660 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 37.905 53.380 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 37.905 53.380 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 38.180 53.380 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 38.180 53.335 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 38.180 50.705 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 38.135 50.660 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 36.657 50.660 + +*CAP +0 mem_top_track_8\/FTB_3__24:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 4.972612e-05 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 4.62375e-05 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.0001112742 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0001112742 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.0001103889 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.0001103889 +8 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 4.21417e-05 +9 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 4.21417e-05 + +*RES +0 mem_top_track_8\/FTB_3__24:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.001319197 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 1e-05 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[0] 0.003677809 //LENGTH 27.350 LUMPCC 0.0002020593 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.925 91.460 +*I mux_right_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 74.420 90.440 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 64.575 86.020 +*I mux_right_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 77.380 85.680 +*N mux_tree_tapbuf_size5_0_sram[0]:4 *C 77.343 85.680 +*N mux_tree_tapbuf_size5_0_sram[0]:5 *C 70.840 85.680 +*N mux_tree_tapbuf_size5_0_sram[0]:6 *C 64.603 86.043 +*N mux_tree_tapbuf_size5_0_sram[0]:7 *C 64.860 86.055 +*N mux_tree_tapbuf_size5_0_sram[0]:8 *C 64.860 86.360 +*N mux_tree_tapbuf_size5_0_sram[0]:9 *C 70.840 86.330 +*N mux_tree_tapbuf_size5_0_sram[0]:10 *C 70.840 86.405 +*N mux_tree_tapbuf_size5_0_sram[0]:11 *C 74.383 90.440 +*N mux_tree_tapbuf_size5_0_sram[0]:12 *C 70.885 90.440 +*N mux_tree_tapbuf_size5_0_sram[0]:13 *C 70.840 90.440 +*N mux_tree_tapbuf_size5_0_sram[0]:14 *C 70.840 91.415 +*N mux_tree_tapbuf_size5_0_sram[0]:15 *C 70.795 91.460 +*N mux_tree_tapbuf_size5_0_sram[0]:16 *C 67.963 91.460 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_2\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[0]:4 0.0003637405 +5 mux_tree_tapbuf_size5_0_sram[0]:5 0.0004120096 +6 mux_tree_tapbuf_size5_0_sram[0]:6 3.369952e-05 +7 mux_tree_tapbuf_size5_0_sram[0]:7 6.048441e-05 +8 mux_tree_tapbuf_size5_0_sram[0]:8 0.0005001466 +9 mux_tree_tapbuf_size5_0_sram[0]:9 0.0005216309 +10 mux_tree_tapbuf_size5_0_sram[0]:10 0.000222429 +11 mux_tree_tapbuf_size5_0_sram[0]:11 0.0002943812 +12 mux_tree_tapbuf_size5_0_sram[0]:12 0.0002943812 +13 mux_tree_tapbuf_size5_0_sram[0]:13 0.0003152727 +14 mux_tree_tapbuf_size5_0_sram[0]:14 6.223908e-05 +15 mux_tree_tapbuf_size5_0_sram[0]:15 0.0001956675 +16 mux_tree_tapbuf_size5_0_sram[0]:16 0.0001956675 +17 mux_tree_tapbuf_size5_0_sram[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001010297 +18 mux_tree_tapbuf_size5_0_sram[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001010297 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_0_sram[0]:16 0.152 +1 mux_tree_tapbuf_size5_0_sram[0]:12 mux_tree_tapbuf_size5_0_sram[0]:11 0.003122768 +2 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:12 0.0045 +3 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:10 0.003602679 +4 mux_tree_tapbuf_size5_0_sram[0]:11 mux_right_track_2\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:8 0.005339286 +6 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:5 0.0005803571 +7 mux_tree_tapbuf_size5_0_sram[0]:10 mux_tree_tapbuf_size5_0_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size5_0_sram[0]:4 mux_right_track_2\/mux_l1_in_1_:S 0.152 +9 mux_tree_tapbuf_size5_0_sram[0]:6 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size5_0_sram[0]:15 mux_tree_tapbuf_size5_0_sram[0]:14 0.0045 +11 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:13 0.0008705358 +12 mux_tree_tapbuf_size5_0_sram[0]:16 mux_tree_tapbuf_size5_0_sram[0]:15 0.002529018 +13 mux_tree_tapbuf_size5_0_sram[0]:7 mux_tree_tapbuf_size5_0_sram[0]:6 0.0001739865 +14 mux_tree_tapbuf_size5_0_sram[0]:8 mux_tree_tapbuf_size5_0_sram[0]:7 0.0002723214 +15 mux_tree_tapbuf_size5_0_sram[0]:5 mux_tree_tapbuf_size5_0_sram[0]:4 0.005805804 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004485221 //LENGTH 2.650 LUMPCC 0.0001026591 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 73.315 39.780 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 73.045 41.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 73.045 41.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.140 41.775 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.140 39.825 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.140 39.780 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 73.315 39.780 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.055126e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.236729e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.236729e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.635366e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.222343e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_0_sram[1]:5 5.132957e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_0_sram[1]:10 5.132957e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001741071 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.510871e-05 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005828622 //LENGTH 4.210 LUMPCC 0.0001431384 DR + +*CONN +*I mux_right_track_10\/mux_l1_in_0_:X O *L 0 *C 40.195 82.280 +*I mux_right_track_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.400 79.900 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.400 79.900 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.400 79.945 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 41.400 82.235 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 41.355 82.280 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 40.233 82.280 + +*CAP +0 mux_right_track_10\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_10\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.459268e-05 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001063333 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001063333 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.523223e-05 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.523223e-05 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_4_sram[0]:7 7.156922e-05 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_4_sram[0]:5 7.156922e-05 + +*RES +0 mux_right_track_10\/mux_l1_in_0_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001002232 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_10\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002460772 //LENGTH 19.365 LUMPCC 0.0005758868 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_0_:X O *L 0 *C 81.705 58.480 +*I mux_right_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 81.880 41.820 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 81.843 41.820 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 80.960 41.820 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 80.960 42.160 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 80.960 42.205 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 80.960 58.435 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 81.005 58.480 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 81.668 58.480 + +*CAP +0 mux_right_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.210112e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.980374e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.988992e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0007403386 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0007403386 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.520634e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 8.520634e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_7_sram[0]:6 0.0002106111 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_7_sram[0]:10 1.56532e-07 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_7_sram[0]:4 8.347769e-07 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_7_sram[0]:5 0.0002106111 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_7_sram[0]:11 1.56532e-07 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size2_7_sram[0]:3 8.347769e-07 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 7.634096e-05 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 7.634096e-05 + +*RES +0 mux_right_track_16\/mux_l1_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.01449107 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0005915179 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0007879465 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006438268 //LENGTH 5.305 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 60.545 69.700 +*I mux_right_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 62.200 72.420 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 62.163 72.420 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.225 72.420 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 61.180 72.375 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 61.180 69.745 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 61.135 69.700 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.583 69.700 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.397373e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.397373e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001706667 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001706667 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.627297e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.627297e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008370536 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.003398195 //LENGTH 31.325 LUMPCC 0.0001955721 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_0_:X O *L 0 *C 94.125 60.860 +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 97.735 33.850 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 97.698 33.948 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 96.185 34.000 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 96.140 34.045 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 96.140 60.815 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 96.095 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 94.163 60.860 + +*CAP +0 mux_right_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001311333 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001311333 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001387246 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001387246 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.193199e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.193199e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.01278e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.765826e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.01278e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.765826e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001350446 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.02390179 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007068717 //LENGTH 5.565 LUMPCC 0.0001030304 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 71.475 71.740 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 69.560 69.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 69.597 69.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 70.335 69.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 70.380 69.065 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 70.380 71.695 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 70.425 71.740 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 71.438 71.740 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.139767e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.139767e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001761608 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001761608 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.33622e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.33622e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_42_[0]:11 5.151522e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_42_[0]:12 5.151522e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006584821 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348215 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET chany_top_out[2] 0.001293825 //LENGTH 9.275 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 75.105 97.240 +*P chany_top_out[2] O *L 0.7423 *C 71.300 102.035 +*N chany_top_out[2]:2 *C 71.300 101.365 +*N chany_top_out[2]:3 *C 71.345 101.320 +*N chany_top_out[2]:4 *C 74.935 101.320 +*N chany_top_out[2]:5 *C 74.980 101.275 +*N chany_top_out[2]:6 *C 74.980 97.285 +*N chany_top_out[2]:7 *C 74.980 97.240 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 chany_top_out[2] 5.789166e-05 +2 chany_top_out[2]:2 5.789166e-05 +3 chany_top_out[2]:3 0.0003284197 +4 chany_top_out[2]:4 0.0003284197 +5 chany_top_out[2]:5 0.0002402061 +6 chany_top_out[2]:6 0.0002402061 +7 chany_top_out[2]:7 3.979003e-05 + +*RES +0 ropt_mt_inst_759:X chany_top_out[2]:7 0.152 +1 chany_top_out[2]:7 chany_top_out[2]:6 0.0045 +2 chany_top_out[2]:6 chany_top_out[2]:5 0.0035625 +3 chany_top_out[2]:4 chany_top_out[2]:3 0.003205357 +4 chany_top_out[2]:5 chany_top_out[2]:4 0.0045 +5 chany_top_out[2]:3 chany_top_out[2]:2 0.0045 +6 chany_top_out[2]:2 chany_top_out[2] 0.0005982143 + +*END + +*D_NET ropt_net_139 0.001609906 //LENGTH 11.210 LUMPCC 0.000332799 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 49.415 94.520 +*I ropt_mt_inst_757:A I *L 0.001767 *C 42.780 96.560 +*N ropt_net_139:2 *C 44.620 96.560 +*N ropt_net_139:3 *C 42.818 96.560 +*N ropt_net_139:4 *C 43.195 96.560 +*N ropt_net_139:5 *C 43.240 96.515 +*N ropt_net_139:6 *C 43.240 95.925 +*N ropt_net_139:7 *C 43.285 95.880 +*N ropt_net_139:8 *C 44.575 95.880 +*N ropt_net_139:9 *C 44.620 95.880 +*N ropt_net_139:10 *C 44.628 95.880 +*N ropt_net_139:11 *C 49.213 95.880 +*N ropt_net_139:12 *C 49.220 95.823 +*N ropt_net_139:13 *C 49.220 94.565 +*N ropt_net_139:14 *C 49.220 94.520 +*N ropt_net_139:15 *C 49.415 94.520 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_139:2 4.239021e-05 +3 ropt_net_139:3 3.456992e-05 +4 ropt_net_139:4 3.456992e-05 +5 ropt_net_139:5 7.151836e-05 +6 ropt_net_139:6 7.151836e-05 +7 ropt_net_139:7 0.00010783 +8 ropt_net_139:8 0.00010783 +9 ropt_net_139:9 8.057657e-05 +10 ropt_net_139:10 0.0002343412 +11 ropt_net_139:11 0.0002343412 +12 ropt_net_139:12 6.951569e-05 +13 ropt_net_139:13 6.951569e-05 +14 ropt_net_139:14 6.069836e-05 +15 ropt_net_139:15 5.589188e-05 +16 ropt_net_139:15 prog_clk[0]:165 6.781413e-08 +17 ropt_net_139:14 prog_clk[0]:166 6.781413e-08 +18 ropt_net_139:13 prog_clk[0]:245 4.319672e-05 +19 ropt_net_139:12 prog_clk[0]:246 4.319672e-05 +20 ropt_net_139:11 prog_clk[0]:163 1.228204e-06 +21 ropt_net_139:11 prog_clk[0]:247 6.457598e-05 +22 ropt_net_139:10 prog_clk[0]:164 1.228204e-06 +23 ropt_net_139:10 prog_clk[0]:248 6.457598e-05 +24 ropt_net_139:9 ropt_net_125:4 2.158165e-05 +25 ropt_net_139:8 ropt_net_125:7 8.210985e-06 +26 ropt_net_139:7 ropt_net_125:8 8.210985e-06 +27 ropt_net_139:4 ropt_net_125:7 2.753817e-05 +28 ropt_net_139:3 ropt_net_125:8 2.753817e-05 +29 ropt_net_139:2 ropt_net_125:5 2.158165e-05 + +*RES +0 ropt_mt_inst_737:X ropt_net_139:15 0.152 +1 ropt_net_139:15 ropt_net_139:14 0.0001059783 +2 ropt_net_139:14 ropt_net_139:13 0.0045 +3 ropt_net_139:13 ropt_net_139:12 0.001122768 +4 ropt_net_139:12 ropt_net_139:11 0.00341 +5 ropt_net_139:11 ropt_net_139:10 0.0007183166 +6 ropt_net_139:9 ropt_net_139:8 0.0045 +7 ropt_net_139:9 ropt_net_139:2 0.0006071429 +8 ropt_net_139:10 ropt_net_139:9 0.00341 +9 ropt_net_139:8 ropt_net_139:7 0.001151786 +10 ropt_net_139:7 ropt_net_139:6 0.0045 +11 ropt_net_139:6 ropt_net_139:5 0.0005267857 +12 ropt_net_139:4 ropt_net_139:3 0.0003370536 +13 ropt_net_139:5 ropt_net_139:4 0.0045 +14 ropt_net_139:3 ropt_mt_inst_757:A 0.152 + +*END + +*D_NET chanx_right_in[10] 0.01732214 //LENGTH 179.260 LUMPCC 0.002481334 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 111.930 25.840 +*I ropt_mt_inst_744:A I *L 0.001767 *C 10.835 99.280 +*N chanx_right_in[10]:2 *C 10.798 99.280 +*N chanx_right_in[10]:3 *C 9.245 99.280 +*N chanx_right_in[10]:4 *C 9.200 99.235 +*N chanx_right_in[10]:5 *C 9.200 95.925 +*N chanx_right_in[10]:6 *C 9.245 95.880 +*N chanx_right_in[10]:7 *C 21.115 95.880 +*N chanx_right_in[10]:8 *C 21.160 95.835 +*N chanx_right_in[10]:9 *C 21.160 75.655 +*N chanx_right_in[10]:10 *C 21.160 25.898 +*N chanx_right_in[10]:11 *C 21.168 25.840 +*N chanx_right_in[10]:12 *C 70.995 25.840 + +*CAP +0 chanx_right_in[10] 0.00193942 +1 ropt_mt_inst_744:A 1e-06 +2 chanx_right_in[10]:2 7.746213e-05 +3 chanx_right_in[10]:3 7.746213e-05 +4 chanx_right_in[10]:4 0.0001972088 +5 chanx_right_in[10]:5 0.0001972088 +6 chanx_right_in[10]:6 0.0007860983 +7 chanx_right_in[10]:7 0.0007860983 +8 chanx_right_in[10]:8 0.000595526 +9 chanx_right_in[10]:9 0.002156683 +10 chanx_right_in[10]:10 0.001561157 +11 chanx_right_in[10]:11 0.002263033 +12 chanx_right_in[10]:12 0.004202453 +13 chanx_right_in[10]:8 chany_top_in[13]:18 4.77273e-05 +14 chanx_right_in[10]:8 chany_top_in[13]:19 0.0001310165 +15 chanx_right_in[10]:10 chany_top_in[13]:17 0.0007001939 +16 chanx_right_in[10]:9 chany_top_in[13]:17 4.77273e-05 +17 chanx_right_in[10]:9 chany_top_in[13]:18 0.0008312103 +18 chanx_right_in[10]:2 ropt_net_119:6 3.658672e-05 +19 chanx_right_in[10]:3 ropt_net_119:5 3.658672e-05 +20 chanx_right_in[10]:8 ropt_net_119:11 0.0001212996 +21 chanx_right_in[10]:9 ropt_net_119:12 0.0001212996 +22 chanx_right_in[10]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001177024 +23 chanx_right_in[10]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.614053e-05 +24 chanx_right_in[10]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001177024 +25 chanx_right_in[10]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.614053e-05 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:12 0.00641315 +1 chanx_right_in[10]:2 ropt_mt_inst_744:A 0.152 +2 chanx_right_in[10]:3 chanx_right_in[10]:2 0.001386161 +3 chanx_right_in[10]:4 chanx_right_in[10]:3 0.0045 +4 chanx_right_in[10]:6 chanx_right_in[10]:5 0.0045 +5 chanx_right_in[10]:5 chanx_right_in[10]:4 0.002955357 +6 chanx_right_in[10]:7 chanx_right_in[10]:6 0.01059821 +7 chanx_right_in[10]:8 chanx_right_in[10]:7 0.0045 +8 chanx_right_in[10]:10 chanx_right_in[10]:9 0.04442634 +9 chanx_right_in[10]:11 chanx_right_in[10]:10 0.00341 +10 chanx_right_in[10]:9 chanx_right_in[10]:8 0.01801786 +11 chanx_right_in[10]:12 chanx_right_in[10]:11 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[0] 0.001274588 //LENGTH 10.485 LUMPCC 0.0001334943 DR + +*CONN +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 87.245 47.940 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 83.895 49.980 +*I mux_right_track_18\/mux_l1_in_0_:S I *L 0.00357 *C 83.160 52.360 +*N mux_tree_tapbuf_size2_8_sram[0]:3 *C 83.198 52.360 +*N mux_tree_tapbuf_size2_8_sram[0]:4 *C 84.595 52.360 +*N mux_tree_tapbuf_size2_8_sram[0]:5 *C 84.640 52.315 +*N mux_tree_tapbuf_size2_8_sram[0]:6 *C 83.933 49.980 +*N mux_tree_tapbuf_size2_8_sram[0]:7 *C 84.595 49.980 +*N mux_tree_tapbuf_size2_8_sram[0]:8 *C 84.640 49.980 +*N mux_tree_tapbuf_size2_8_sram[0]:9 *C 84.640 47.985 +*N mux_tree_tapbuf_size2_8_sram[0]:10 *C 84.685 47.940 +*N mux_tree_tapbuf_size2_8_sram[0]:11 *C 87.208 47.940 + +*CAP +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_18\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_8_sram[0]:3 0.0001221477 +4 mux_tree_tapbuf_size2_8_sram[0]:4 0.0001221477 +5 mux_tree_tapbuf_size2_8_sram[0]:5 0.0001034717 +6 mux_tree_tapbuf_size2_8_sram[0]:6 6.841894e-05 +7 mux_tree_tapbuf_size2_8_sram[0]:7 6.841894e-05 +8 mux_tree_tapbuf_size2_8_sram[0]:8 0.0002313503 +9 mux_tree_tapbuf_size2_8_sram[0]:9 9.693799e-05 +10 mux_tree_tapbuf_size2_8_sram[0]:10 0.0001626002 +11 mux_tree_tapbuf_size2_8_sram[0]:11 0.0001626002 +12 mux_tree_tapbuf_size2_8_sram[0]:9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.475226e-05 +13 mux_tree_tapbuf_size2_8_sram[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.188076e-08 +14 mux_tree_tapbuf_size2_8_sram[0]:8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.133695e-05 +15 mux_tree_tapbuf_size2_8_sram[0]:8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.475226e-05 +16 mux_tree_tapbuf_size2_8_sram[0]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.188076e-08 +17 mux_tree_tapbuf_size2_8_sram[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.063606e-05 +18 mux_tree_tapbuf_size2_8_sram[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.133695e-05 +19 mux_tree_tapbuf_size2_8_sram[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.063606e-05 + +*RES +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_8_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_8_sram[0]:10 mux_tree_tapbuf_size2_8_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size2_8_sram[0]:9 mux_tree_tapbuf_size2_8_sram[0]:8 0.00178125 +3 mux_tree_tapbuf_size2_8_sram[0]:11 mux_tree_tapbuf_size2_8_sram[0]:10 0.002252232 +4 mux_tree_tapbuf_size2_8_sram[0]:7 mux_tree_tapbuf_size2_8_sram[0]:6 0.0005915179 +5 mux_tree_tapbuf_size2_8_sram[0]:8 mux_tree_tapbuf_size2_8_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_8_sram[0]:8 mux_tree_tapbuf_size2_8_sram[0]:5 0.002084821 +7 mux_tree_tapbuf_size2_8_sram[0]:6 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_8_sram[0]:4 mux_tree_tapbuf_size2_8_sram[0]:3 0.001247768 +9 mux_tree_tapbuf_size2_8_sram[0]:5 mux_tree_tapbuf_size2_8_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size2_8_sram[0]:3 mux_right_track_18\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001874864 //LENGTH 16.470 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 43.545 93.500 +*I mem_right_track_8\/FTB_17__38:A I *L 0.001746 *C 43.240 91.120 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 50.040 85.680 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 50.003 85.680 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 44.205 85.680 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 44.160 85.725 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 43.278 91.120 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 44.115 91.120 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 44.160 91.120 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 44.160 93.455 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 44.115 93.500 +*N mux_tree_tapbuf_size3_0_sram[1]:11 *C 43.583 93.500 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_8\/FTB_17__38:A 1e-06 +2 mux_right_track_8\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 0.0003711402 +4 mux_tree_tapbuf_size3_0_sram[1]:4 0.0003711402 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0002702801 +6 mux_tree_tapbuf_size3_0_sram[1]:6 9.170502e-05 +7 mux_tree_tapbuf_size3_0_sram[1]:7 9.170502e-05 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0004335591 +9 mux_tree_tapbuf_size3_0_sram[1]:9 0.0001322657 +10 mux_tree_tapbuf_size3_0_sram[1]:10 5.503415e-05 +11 mux_tree_tapbuf_size3_0_sram[1]:11 5.503415e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.00517634 +2 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size3_0_sram[1]:3 mux_right_track_8\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.0007477679 +5 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:5 0.004816964 +7 mux_tree_tapbuf_size3_0_sram[1]:6 mem_right_track_8\/FTB_17__38:A 0.152 +8 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.002084821 +10 mux_tree_tapbuf_size3_0_sram[1]:11 mux_tree_tapbuf_size3_0_sram[1]:10 0.0004754465 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_0_ccff_tail[0] 0.0005988332 //LENGTH 3.280 LUMPCC 0.0001250205 DR + +*CONN +*I mem_right_track_2\/FTB_15__36:X O *L 0 *C 76.125 68.680 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.075 66.300 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 *C 76.075 66.300 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 *C 75.900 66.300 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 *C 75.900 66.345 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 *C 75.900 68.635 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 *C 75.900 68.680 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 *C 76.125 68.680 + +*CAP +0 mem_right_track_2\/FTB_15__36:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 5.139766e-05 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 5.488427e-05 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0001171616 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0001171616 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 6.699469e-05 +7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 6.421281e-05 +8 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 chanx_right_in[8]:10 6.251027e-05 +9 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 chanx_right_in[8]:9 6.251027e-05 + +*RES +0 mem_right_track_2\/FTB_15__36:X mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET optlc_net_112 0.01146367 //LENGTH 82.220 LUMPCC 0.002402065 DR + +*CONN +*I optlc_105:HI O *L 0 *C 83.720 66.300 +*I mux_right_track_22\/mux_l2_in_0_:A0 I *L 0.001631 *C 99.100 64.260 +*I mux_right_track_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 75.615 59.235 +*I mux_right_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 73.430 70.040 +*I mux_right_track_26\/mux_l2_in_0_:A0 I *L 0.001631 *C 65.035 70.040 +*I mux_right_track_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 79.410 87.720 +*I mux_right_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 78.950 77.180 +*N optlc_net_112:7 *C 78.950 77.180 +*N optlc_net_112:8 *C 79.410 87.720 +*N optlc_net_112:9 *C 79.120 87.720 +*N optlc_net_112:10 *C 79.120 87.675 +*N optlc_net_112:11 *C 79.120 77.225 +*N optlc_net_112:12 *C 79.120 77.180 +*N optlc_net_112:13 *C 78.950 76.840 +*N optlc_net_112:14 *C 76.865 76.840 +*N optlc_net_112:15 *C 76.820 76.795 +*N optlc_net_112:16 *C 65.073 70.040 +*N optlc_net_112:17 *C 68.035 70.040 +*N optlc_net_112:18 *C 68.080 70.040 +*N optlc_net_112:19 *C 68.088 70.040 +*N optlc_net_112:20 *C 73.422 70.040 +*N optlc_net_112:21 *C 73.430 70.040 +*N optlc_net_112:22 *C 73.430 70.040 +*N optlc_net_112:23 *C 76.775 70.040 +*N optlc_net_112:24 *C 76.820 70.040 +*N optlc_net_112:25 *C 75.615 59.235 +*N optlc_net_112:26 *C 76.775 59.160 +*N optlc_net_112:27 *C 99.062 64.260 +*N optlc_net_112:28 *C 93.885 64.260 +*N optlc_net_112:29 *C 93.840 64.215 +*N optlc_net_112:30 *C 93.840 59.218 +*N optlc_net_112:31 *C 93.833 59.160 +*N optlc_net_112:32 *C 76.828 59.160 +*N optlc_net_112:33 *C 76.820 59.160 +*N optlc_net_112:34 *C 76.820 66.300 +*N optlc_net_112:35 *C 76.865 66.300 +*N optlc_net_112:36 *C 83.683 66.300 + +*CAP +0 optlc_105:HI 1e-06 +1 mux_right_track_22\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_14\/mux_l2_in_0_:A0 1e-06 +3 mux_right_track_24\/mux_l1_in_1_:A0 1e-06 +4 mux_right_track_26\/mux_l2_in_0_:A0 1e-06 +5 mux_right_track_6\/mux_l2_in_1_:A0 1e-06 +6 mux_right_track_2\/mux_l2_in_1_:A0 1e-06 +7 optlc_net_112:7 5.548565e-05 +8 optlc_net_112:8 4.964043e-05 +9 optlc_net_112:9 5.381047e-05 +10 optlc_net_112:10 0.000625535 +11 optlc_net_112:11 0.000625535 +12 optlc_net_112:12 8.09184e-05 +13 optlc_net_112:13 0.0001884956 +14 optlc_net_112:14 0.0001675502 +15 optlc_net_112:15 0.0002426011 +16 optlc_net_112:16 0.0002584395 +17 optlc_net_112:17 0.0002584395 +18 optlc_net_112:18 4.003626e-05 +19 optlc_net_112:19 0.0004342166 +20 optlc_net_112:20 0.0004342166 +21 optlc_net_112:21 4.105351e-05 +22 optlc_net_112:22 0.0003076821 +23 optlc_net_112:23 0.0002701246 +24 optlc_net_112:24 0.0004914121 +25 optlc_net_112:25 0.0001624714 +26 optlc_net_112:26 0.000108034 +27 optlc_net_112:27 0.0002197301 +28 optlc_net_112:28 0.0002197301 +29 optlc_net_112:29 0.0002980658 +30 optlc_net_112:30 0.0002980658 +31 optlc_net_112:31 0.0005097805 +32 optlc_net_112:32 0.0005097805 +33 optlc_net_112:33 0.0004466446 +34 optlc_net_112:34 0.000658563 +35 optlc_net_112:35 0.0004992755 +36 optlc_net_112:36 0.0004992755 +37 optlc_net_112:31 chanx_right_in[19]:10 0.0003976299 +38 optlc_net_112:32 chanx_right_in[19]:9 0.0003976299 +39 optlc_net_112:27 mux_tree_tapbuf_size2_10_sram[1]:4 0.0001734937 +40 optlc_net_112:28 mux_tree_tapbuf_size2_10_sram[1]:3 0.0001734937 +41 optlc_net_112:31 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.84531e-05 +42 optlc_net_112:31 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003640312 +43 optlc_net_112:32 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0003640312 +44 optlc_net_112:32 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.84531e-05 +45 optlc_net_112:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001183845 +46 optlc_net_112:24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001183845 +47 optlc_net_112:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.035162e-06 +48 optlc_net_112:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000126241 +49 optlc_net_112:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.763581e-06 +50 optlc_net_112:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.763581e-06 +51 optlc_net_112:24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000126241 +52 optlc_net_112:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.035162e-06 + +*RES +0 optlc_105:HI optlc_net_112:36 0.152 +1 optlc_net_112:27 mux_right_track_22\/mux_l2_in_0_:A0 0.152 +2 optlc_net_112:28 optlc_net_112:27 0.004622768 +3 optlc_net_112:29 optlc_net_112:28 0.0045 +4 optlc_net_112:30 optlc_net_112:29 0.004462054 +5 optlc_net_112:31 optlc_net_112:30 0.00341 +6 optlc_net_112:33 optlc_net_112:32 0.00341 +7 optlc_net_112:33 optlc_net_112:26 0.0045 +8 optlc_net_112:32 optlc_net_112:31 0.002664116 +9 optlc_net_112:14 optlc_net_112:13 0.001861607 +10 optlc_net_112:15 optlc_net_112:14 0.0045 +11 optlc_net_112:12 optlc_net_112:11 0.0045 +12 optlc_net_112:12 optlc_net_112:7 9.239131e-05 +13 optlc_net_112:11 optlc_net_112:10 0.009330357 +14 optlc_net_112:9 optlc_net_112:8 0.0001576087 +15 optlc_net_112:10 optlc_net_112:9 0.0045 +16 optlc_net_112:8 mux_right_track_6\/mux_l2_in_1_:A0 0.152 +17 optlc_net_112:7 mux_right_track_2\/mux_l2_in_1_:A0 0.152 +18 optlc_net_112:25 mux_right_track_14\/mux_l2_in_0_:A0 0.152 +19 optlc_net_112:26 optlc_net_112:25 0.001035714 +20 optlc_net_112:22 mux_right_track_24\/mux_l1_in_1_:A0 0.152 +21 optlc_net_112:22 optlc_net_112:21 0.0045 +22 optlc_net_112:21 optlc_net_112:20 0.00341 +23 optlc_net_112:20 optlc_net_112:19 0.0008358166 +24 optlc_net_112:18 optlc_net_112:17 0.0045 +25 optlc_net_112:19 optlc_net_112:18 0.00341 +26 optlc_net_112:17 optlc_net_112:16 0.002645089 +27 optlc_net_112:16 mux_right_track_26\/mux_l2_in_0_:A0 0.152 +28 optlc_net_112:23 optlc_net_112:22 0.002986607 +29 optlc_net_112:24 optlc_net_112:23 0.0045 +30 optlc_net_112:24 optlc_net_112:15 0.006031251 +31 optlc_net_112:35 optlc_net_112:34 0.0045 +32 optlc_net_112:34 optlc_net_112:33 0.006375001 +33 optlc_net_112:34 optlc_net_112:24 0.003339286 +34 optlc_net_112:36 optlc_net_112:35 0.006087054 +35 optlc_net_112:13 optlc_net_112:12 0.0003035715 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001072481 //LENGTH 9.140 LUMPCC 0.0001394785 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_1_:X O *L 0 *C 58.705 76.840 +*I mux_right_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 61.815 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 61.778 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 60.305 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 60.260 71.785 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 60.260 76.795 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 60.215 76.840 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 58.742 76.840 + +*CAP +0 mux_right_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.802024e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.802024e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002855653 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002855653 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001119158 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001119158 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 right_top_grid_pin_42_[0]:12 6.973927e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 right_top_grid_pin_42_[0]:11 6.973927e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001314732 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473214 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005520223 //LENGTH 3.895 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_0_:X O *L 0 *C 75.265 90.440 +*I mux_right_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 74.160 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 74.198 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.395 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 75.440 88.785 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 75.440 90.395 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 75.440 90.440 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 75.265 90.440 + +*CAP +0 mux_right_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001029452 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001029452 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001102316 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001102316 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.987879e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.378993e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001069196 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008949577 //LENGTH 6.390 LUMPCC 0.0003313757 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 49.045 91.120 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 49.320 85.340 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 49.220 85.340 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.220 85.385 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.220 91.075 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.220 91.120 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 49.045 91.120 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.481304e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002028372 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002028372 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.21543e-05 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.89403e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 prog_clk[0]:244 0.0001656879 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:245 0.0001656879 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005080357 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 + +*END + +*D_NET ccff_tail[0] 0.0007456379 //LENGTH 7.150 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_729:X O *L 0 *C 7.095 69.360 +*P ccff_tail[0] O *L 0.7423 *C 1.230 68.680 +*N ccff_tail[0]:2 *C 6.893 68.680 +*N ccff_tail[0]:3 *C 6.900 68.737 +*N ccff_tail[0]:4 *C 6.900 69.315 +*N ccff_tail[0]:5 *C 6.900 69.360 +*N ccff_tail[0]:6 *C 7.095 69.360 + +*CAP +0 ropt_mt_inst_729:X 1e-06 +1 ccff_tail[0] 0.0002703029 +2 ccff_tail[0]:2 0.0002703029 +3 ccff_tail[0]:3 4.747093e-05 +4 ccff_tail[0]:4 4.747093e-05 +5 ccff_tail[0]:5 5.271455e-05 +6 ccff_tail[0]:6 5.637568e-05 + +*RES +0 ropt_mt_inst_729:X ccff_tail[0]:6 0.152 +1 ccff_tail[0]:6 ccff_tail[0]:5 0.0001059783 +2 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +3 ccff_tail[0]:4 ccff_tail[0]:3 0.000515625 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 0.0008871249 + +*END + +*D_NET chany_top_out[12] 0.0007348594 //LENGTH 6.890 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 10.315 98.600 +*P chany_top_out[12] O *L 0.7423 *C 7.360 102.070 +*N chany_top_out[12]:2 *C 7.360 98.645 +*N chany_top_out[12]:3 *C 7.405 98.600 +*N chany_top_out[12]:4 *C 10.277 98.600 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 chany_top_out[12] 0.0001678755 +2 chany_top_out[12]:2 0.0001678755 +3 chany_top_out[12]:3 0.0001990542 +4 chany_top_out[12]:4 0.0001990542 + +*RES +0 ropt_mt_inst_731:X chany_top_out[12]:4 0.152 +1 chany_top_out[12]:4 chany_top_out[12]:3 0.002564732 +2 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +3 chany_top_out[12]:2 chany_top_out[12] 0.003058036 + +*END + +*D_NET chanx_right_out[17] 0.0008059766 //LENGTH 5.730 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 110.135 65.960 +*P chanx_right_out[17] O *L 0.7423 *C 111.930 62.560 +*N chanx_right_out[17]:2 *C 110.407 62.560 +*N chanx_right_out[17]:3 *C 110.400 62.617 +*N chanx_right_out[17]:4 *C 110.400 65.915 +*N chanx_right_out[17]:5 *C 110.400 65.960 +*N chanx_right_out[17]:6 *C 110.135 65.960 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 chanx_right_out[17] 0.0001255309 +2 chanx_right_out[17]:2 0.0001255309 +3 chanx_right_out[17]:3 0.0002132213 +4 chanx_right_out[17]:4 0.0002132213 +5 chanx_right_out[17]:5 6.104225e-05 +6 chanx_right_out[17]:6 6.642988e-05 + +*RES +0 ropt_mt_inst_772:X chanx_right_out[17]:6 0.152 +1 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0001440218 +2 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.002944197 +4 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +5 chanx_right_out[17]:2 chanx_right_out[17] 0.000238525 + +*END + +*D_NET chanx_right_out[19] 0.0003569394 //LENGTH 1.985 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 110.135 53.040 +*P chanx_right_out[19] O *L 0.7423 *C 111.930 53.040 +*N chanx_right_out[19]:2 *C 110.407 53.040 +*N chanx_right_out[19]:3 *C 110.400 53.040 +*N chanx_right_out[19]:4 *C 110.400 53.040 +*N chanx_right_out[19]:5 *C 110.135 53.040 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 chanx_right_out[19] 0.0001133934 +2 chanx_right_out[19]:2 0.0001133934 +3 chanx_right_out[19]:3 3.143216e-05 +4 chanx_right_out[19]:4 4.670001e-05 +5 chanx_right_out[19]:5 5.102041e-05 + +*RES +0 ropt_mt_inst_750:X chanx_right_out[19]:5 0.152 +1 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0001440218 +2 chanx_right_out[19]:4 chanx_right_out[19]:3 0.0045 +3 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +4 chanx_right_out[19]:2 chanx_right_out[19] 0.000238525 + +*END + +*D_NET chanx_right_in[11] 0.01439427 //LENGTH 121.135 LUMPCC 0.004121214 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 111.930 29.920 +*I BUFT_RR_57:A I *L 0.001776 *C 48.300 82.960 +*N chanx_right_in[11]:2 *C 97.113 39.440 +*N chanx_right_in[11]:3 *C 48.300 82.960 +*N chanx_right_in[11]:4 *C 48.300 82.915 +*N chanx_right_in[11]:5 *C 48.300 38.818 +*N chanx_right_in[11]:6 *C 48.308 38.760 +*N chanx_right_in[11]:7 *C 91.073 38.760 +*N chanx_right_in[11]:8 *C 91.080 38.818 +*N chanx_right_in[11]:9 *C 91.080 39.395 +*N chanx_right_in[11]:10 *C 91.125 39.440 +*N chanx_right_in[11]:11 *C 94.615 39.440 +*N chanx_right_in[11]:12 *C 97.157 39.433 +*N chanx_right_in[11]:13 *C 97.060 39.395 +*N chanx_right_in[11]:14 *C 97.060 31.325 +*N chanx_right_in[11]:15 *C 97.105 31.280 +*N chanx_right_in[11]:16 *C 103.455 31.280 +*N chanx_right_in[11]:17 *C 103.500 31.235 +*N chanx_right_in[11]:18 *C 103.500 30.658 +*N chanx_right_in[11]:19 *C 103.508 30.600 +*N chanx_right_in[11]:20 *C 108.560 30.600 +*N chanx_right_in[11]:21 *C 108.560 29.920 + +*CAP +0 chanx_right_in[11] 0.0001934932 +1 BUFT_RR_57:A 1e-06 +2 chanx_right_in[11]:2 1.867436e-05 +3 chanx_right_in[11]:3 3.200098e-05 +4 chanx_right_in[11]:4 0.001947505 +5 chanx_right_in[11]:5 0.001947505 +6 chanx_right_in[11]:6 0.001491448 +7 chanx_right_in[11]:7 0.001491448 +8 chanx_right_in[11]:8 5.080675e-05 +9 chanx_right_in[11]:9 5.080675e-05 +10 chanx_right_in[11]:10 0.0002227754 +11 chanx_right_in[11]:11 0.0003567733 +12 chanx_right_in[11]:12 0.0001526723 +13 chanx_right_in[11]:13 0.0003482787 +14 chanx_right_in[11]:14 0.0003482787 +15 chanx_right_in[11]:15 0.0003323267 +16 chanx_right_in[11]:16 0.0003323267 +17 chanx_right_in[11]:17 5.082269e-05 +18 chanx_right_in[11]:18 5.082269e-05 +19 chanx_right_in[11]:19 0.0002794766 +20 chanx_right_in[11]:20 0.0003299002 +21 chanx_right_in[11]:21 0.0002439168 +22 chanx_right_in[11] chanx_right_in[6] 6.700887e-05 +23 chanx_right_in[11]:13 chanx_right_in[6]:32 7.420901e-05 +24 chanx_right_in[11]:14 chanx_right_in[6]:33 7.420901e-05 +25 chanx_right_in[11]:19 chanx_right_in[6]:34 0.0002990376 +26 chanx_right_in[11]:20 chanx_right_in[6] 0.0002990376 +27 chanx_right_in[11]:21 chanx_right_in[6]:34 6.700887e-05 +28 chanx_right_in[11]:7 chanx_right_in[15]:7 0.0006724644 +29 chanx_right_in[11]:7 chanx_right_in[15]:6 0.0003891844 +30 chanx_right_in[11]:6 chanx_right_in[15]:5 0.0003891844 +31 chanx_right_in[11]:6 chanx_right_in[15]:6 0.0006724644 +32 chanx_right_in[11]:7 prog_clk[0]:205 0.000122385 +33 chanx_right_in[11]:5 prog_clk[0]:236 1.382875e-05 +34 chanx_right_in[11]:5 prog_clk[0]:240 6.696437e-05 +35 chanx_right_in[11]:5 prog_clk[0]:244 7.98231e-05 +36 chanx_right_in[11]:6 prog_clk[0]:206 0.000122385 +37 chanx_right_in[11]:4 prog_clk[0]:243 6.696437e-05 +38 chanx_right_in[11]:4 prog_clk[0]:245 7.98231e-05 +39 chanx_right_in[11]:4 prog_clk[0]:237 1.382875e-05 +40 chanx_right_in[11]:5 mux_tree_tapbuf_size2_5_sram[0]:6 0.0002757011 +41 chanx_right_in[11]:4 mux_tree_tapbuf_size2_5_sram[0]:7 0.0002757011 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:21 0.0005279667 +1 chanx_right_in[11]:10 chanx_right_in[11]:9 0.0045 +2 chanx_right_in[11]:9 chanx_right_in[11]:8 0.0005156251 +3 chanx_right_in[11]:8 chanx_right_in[11]:7 0.00341 +4 chanx_right_in[11]:7 chanx_right_in[11]:6 0.00669985 +5 chanx_right_in[11]:5 chanx_right_in[11]:4 0.03937277 +6 chanx_right_in[11]:6 chanx_right_in[11]:5 0.00341 +7 chanx_right_in[11]:3 BUFT_RR_57:A 0.152 +8 chanx_right_in[11]:4 chanx_right_in[11]:3 0.0045 +9 chanx_right_in[11]:12 chanx_right_in[11]:11 0.002270089 +10 chanx_right_in[11]:12 chanx_right_in[11]:2 4.017857e-05 +11 chanx_right_in[11]:13 chanx_right_in[11]:12 0.0045 +12 chanx_right_in[11]:15 chanx_right_in[11]:14 0.0045 +13 chanx_right_in[11]:14 chanx_right_in[11]:13 0.007205358 +14 chanx_right_in[11]:16 chanx_right_in[11]:15 0.005669643 +15 chanx_right_in[11]:17 chanx_right_in[11]:16 0.0045 +16 chanx_right_in[11]:18 chanx_right_in[11]:17 0.000515625 +17 chanx_right_in[11]:19 chanx_right_in[11]:18 0.00341 +18 chanx_right_in[11]:11 chanx_right_in[11]:10 0.003116071 +19 chanx_right_in[11]:20 chanx_right_in[11]:19 0.0007915584 +20 chanx_right_in[11]:21 chanx_right_in[11]:20 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.001251741 //LENGTH 10.770 LUMPCC 0.0002902118 DR + +*CONN +*I mem_top_track_24\/FTB_4__25:X O *L 0 *C 43.015 64.260 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 40.655 71.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 40.693 71.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 41.815 71.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 41.860 71.695 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 41.860 64.305 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 41.905 64.260 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 42.977 64.260 + +*CAP +0 mem_top_track_24\/FTB_4__25:X 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 9.201941e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 9.201941e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0003300235 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0003300235 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 5.772164e-05 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 5.772164e-05 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 chany_top_out[0]:2 9.155131e-05 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 chany_top_out[0] 9.155131e-05 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 optlc_net_113:5 5.35546e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 optlc_net_113:4 5.35546e-05 + +*RES +0 mem_top_track_24\/FTB_4__25:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.0009575893 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.006598215 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 0.001002232 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.002539279 //LENGTH 19.800 LUMPCC 0.0001328562 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.965 74.800 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 59.700 69.360 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 52.615 80.580 +*I mux_right_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 55.660 77.695 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 55.660 77.695 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 52.615 80.580 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 52.900 80.580 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 52.900 80.535 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 52.900 77.565 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 52.945 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 55.615 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 55.660 77.475 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 59.663 69.360 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 55.705 69.360 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 55.660 69.405 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 55.660 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 55.660 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:17 *C 55.965 74.800 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_0\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 3.658512e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 5.230989e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 5.664317e-05 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.00018744 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.00018744 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.00019384 +10 mux_tree_tapbuf_size6_0_sram[1]:10 0.0002017412 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0001532793 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0002227078 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0002227078 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.0002976521 +15 mux_tree_tapbuf_size6_0_sram[1]:15 0.0004819835 +16 mux_tree_tapbuf_size6_0_sram[1]:16 5.543057e-05 +17 mux_tree_tapbuf_size6_0_sram[1]:17 5.266266e-05 +18 mux_tree_tapbuf_size6_0_sram[1]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.635064e-05 +19 mux_tree_tapbuf_size6_0_sram[1]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.744236e-08 +20 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.635064e-05 +21 mux_tree_tapbuf_size6_0_sram[1]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.744236e-08 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:17 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:4 mux_right_track_0\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.002383929 +3 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:4 4.017857e-05 +4 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.003533483 +6 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_0\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.002651786 +10 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0001548913 +11 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[1]:6 0.0045 +12 mux_tree_tapbuf_size6_0_sram[1]:5 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.004816964 +15 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:11 0.002388393 +16 mux_tree_tapbuf_size6_0_sram[1]:17 mux_tree_tapbuf_size6_0_sram[1]:16 0.0001657609 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00668125 //LENGTH 48.370 LUMPCC 0.002608801 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_0_:X O *L 0 *C 63.765 71.740 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.215 64.085 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 103.215 64.085 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 103.040 64.260 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 103.040 64.305 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 103.040 68.623 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 103.032 68.680 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 65.328 68.680 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 65.320 68.737 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 65.320 71.695 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 65.275 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 63.803 71.740 + +*CAP +0 mux_right_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.332711e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.239347e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002585781 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002585781 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001426417 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001426417 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002199587 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0002199587 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 7.74103e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 7.74103e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[9]:15 0.0003116109 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[9]:16 0.0003116109 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 right_top_grid_pin_42_[0]:11 6.667073e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 right_top_grid_pin_42_[0]:12 6.667073e-05 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_42_[0]:16 0.0002025062 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_42_[0]:24 1.749269e-05 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_42_[0]:17 0.0002025062 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_42_[0]:25 1.749269e-05 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_45_[0]:8 1.616384e-05 +21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_45_[0]:24 0.0006899564 +22 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_45_[0]:9 1.616384e-05 +23 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_45_[0]:25 0.0006899564 + +*RES +0 mux_right_track_0\/mux_l3_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.001314732 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002640625 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.005907116 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003854911 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chany_top_out[11] 0.001154803 //LENGTH 8.320 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 54.280 98.600 +*P chany_top_out[11] O *L 0.7423 *C 51.060 102.035 +*N chany_top_out[11]:2 *C 51.060 99.960 +*N chany_top_out[11]:3 *C 50.600 99.960 +*N chany_top_out[11]:4 *C 50.600 98.645 +*N chany_top_out[11]:5 *C 50.645 98.600 +*N chany_top_out[11]:6 *C 54.242 98.600 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 chany_top_out[11] 0.0001471814 +2 chany_top_out[11]:2 0.0001776764 +3 chany_top_out[11]:3 0.0001422845 +4 chany_top_out[11]:4 0.0001117894 +5 chany_top_out[11]:5 0.0002874355 +6 chany_top_out[11]:6 0.0002874355 + +*RES +0 ropt_mt_inst_733:X chany_top_out[11]:6 0.152 +1 chany_top_out[11]:5 chany_top_out[11]:4 0.0045 +2 chany_top_out[11]:4 chany_top_out[11]:3 0.001174107 +3 chany_top_out[11]:6 chany_top_out[11]:5 0.003212054 +4 chany_top_out[11]:3 chany_top_out[11]:2 0.0004107143 +5 chany_top_out[11]:2 chany_top_out[11] 0.001852679 + +*END + +*D_NET chany_top_out[18] 0.001739931 //LENGTH 12.290 LUMPCC 0 DR + +*CONN +*I BUFT_RR_85:X O *L 0 *C 38.835 99.960 +*P chany_top_out[18] O *L 0.7423 *C 47.840 102.075 +*N chany_top_out[18]:2 *C 47.840 101.328 +*N chany_top_out[18]:3 *C 47.820 101.320 +*N chany_top_out[18]:4 *C 39.568 101.320 +*N chany_top_out[18]:5 *C 39.560 101.263 +*N chany_top_out[18]:6 *C 39.560 100.005 +*N chany_top_out[18]:7 *C 39.515 99.960 +*N chany_top_out[18]:8 *C 38.873 99.960 + +*CAP +0 BUFT_RR_85:X 1e-06 +1 chany_top_out[18] 8.002121e-05 +2 chany_top_out[18]:2 8.002121e-05 +3 chany_top_out[18]:3 0.0006302397 +4 chany_top_out[18]:4 0.0006302397 +5 chany_top_out[18]:5 7.577922e-05 +6 chany_top_out[18]:6 7.577922e-05 +7 chany_top_out[18]:7 8.342547e-05 +8 chany_top_out[18]:8 8.342547e-05 + +*RES +0 BUFT_RR_85:X chany_top_out[18]:8 0.152 +1 chany_top_out[18]:3 chany_top_out[18]:2 0.00341 +2 chany_top_out[18]:2 chany_top_out[18] 0.0001171083 +3 chany_top_out[18]:5 chany_top_out[18]:4 0.00341 +4 chany_top_out[18]:4 chany_top_out[18]:3 0.001292892 +5 chany_top_out[18]:7 chany_top_out[18]:6 0.0045 +6 chany_top_out[18]:6 chany_top_out[18]:5 0.001122768 +7 chany_top_out[18]:8 chany_top_out[18]:7 0.0005736608 + +*END + +*D_NET chanx_right_in[12] 0.01704407 //LENGTH 152.555 LUMPCC 0.001128004 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 111.930 19.040 +*I ropt_mt_inst_733:A I *L 0.001767 *C 53.360 99.280 +*N chanx_right_in[12]:2 *C 58.480 74.800 +*N chanx_right_in[12]:3 *C 53.323 99.280 +*N chanx_right_in[12]:4 *C 51.105 99.280 +*N chanx_right_in[12]:5 *C 51.060 99.235 +*N chanx_right_in[12]:6 *C 51.060 91.505 +*N chanx_right_in[12]:7 *C 51.105 91.460 +*N chanx_right_in[12]:8 *C 55.615 91.460 +*N chanx_right_in[12]:9 *C 55.660 91.415 +*N chanx_right_in[12]:10 *C 55.660 85.385 +*N chanx_right_in[12]:11 *C 55.705 85.340 +*N chanx_right_in[12]:12 *C 57.960 85.340 +*N chanx_right_in[12]:13 *C 57.885 85.000 +*N chanx_right_in[12]:14 *C 57.953 85.045 +*N chanx_right_in[12]:15 *C 57.960 85.635 +*N chanx_right_in[12]:16 *C 58.005 85.680 +*N chanx_right_in[12]:17 *C 58.835 85.680 +*N chanx_right_in[12]:18 *C 58.880 85.635 +*N chanx_right_in[12]:19 *C 58.880 74.858 +*N chanx_right_in[12]:20 *C 58.880 74.800 +*N chanx_right_in[12]:21 *C 58.880 74.793 +*N chanx_right_in[12]:22 *C 58.880 33.328 +*N chanx_right_in[12]:23 *C 58.900 33.320 +*N chanx_right_in[12]:24 *C 87.853 33.320 +*N chanx_right_in[12]:25 *C 87.860 33.378 +*N chanx_right_in[12]:26 *C 87.850 33.935 +*N chanx_right_in[12]:27 *C 87.778 34.000 +*N chanx_right_in[12]:28 *C 90.153 34.000 +*N chanx_right_in[12]:29 *C 90.160 34.000 +*N chanx_right_in[12]:30 *C 90.160 34.000 +*N chanx_right_in[12]:31 *C 90.160 33.660 +*N chanx_right_in[12]:32 *C 92.875 33.660 +*N chanx_right_in[12]:33 *C 92.920 33.615 +*N chanx_right_in[12]:34 *C 92.920 19.777 +*N chanx_right_in[12]:35 *C 92.928 19.720 +*N chanx_right_in[12]:36 *C 108.100 19.720 +*N chanx_right_in[12]:37 *C 108.100 19.040 + +*CAP +0 chanx_right_in[12] 0.0001585528 +1 ropt_mt_inst_733:A 1e-06 +2 chanx_right_in[12]:2 6.606941e-05 +3 chanx_right_in[12]:3 0.000215689 +4 chanx_right_in[12]:4 0.000215689 +5 chanx_right_in[12]:5 0.0004799458 +6 chanx_right_in[12]:6 0.0004799458 +7 chanx_right_in[12]:7 0.0003003481 +8 chanx_right_in[12]:8 0.0003003481 +9 chanx_right_in[12]:9 0.0003236109 +10 chanx_right_in[12]:10 0.0003236109 +11 chanx_right_in[12]:11 0.0001484281 +12 chanx_right_in[12]:12 0.0001788358 +13 chanx_right_in[12]:13 6.601268e-05 +14 chanx_right_in[12]:14 4.339444e-05 +15 chanx_right_in[12]:15 4.339444e-05 +16 chanx_right_in[12]:16 7.104097e-05 +17 chanx_right_in[12]:17 7.104097e-05 +18 chanx_right_in[12]:18 0.0005767831 +19 chanx_right_in[12]:19 0.0005767831 +20 chanx_right_in[12]:20 6.606941e-05 +21 chanx_right_in[12]:21 0.002253609 +22 chanx_right_in[12]:22 0.002253609 +23 chanx_right_in[12]:23 0.001456389 +24 chanx_right_in[12]:24 0.001456389 +25 chanx_right_in[12]:25 5.1342e-05 +26 chanx_right_in[12]:26 5.1342e-05 +27 chanx_right_in[12]:27 0.00017875 +28 chanx_right_in[12]:28 0.00017875 +29 chanx_right_in[12]:29 3.247549e-05 +30 chanx_right_in[12]:30 5.499797e-05 +31 chanx_right_in[12]:31 0.000200115 +32 chanx_right_in[12]:32 0.0001745218 +33 chanx_right_in[12]:33 0.000646601 +34 chanx_right_in[12]:34 0.000646601 +35 chanx_right_in[12]:35 0.000661224 +36 chanx_right_in[12]:36 0.0007077132 +37 chanx_right_in[12]:37 0.0002050421 +38 chanx_right_in[12] chanx_right_in[14] 0.0001077329 +39 chanx_right_in[12]:35 chanx_right_in[14]:22 8.299771e-05 +40 chanx_right_in[12]:35 chanx_right_in[14]:23 0.0001526175 +41 chanx_right_in[12]:36 chanx_right_in[14] 0.0001526175 +42 chanx_right_in[12]:36 chanx_right_in[14]:23 8.299771e-05 +43 chanx_right_in[12]:37 chanx_right_in[14]:23 0.0001077329 +44 chanx_right_in[12]:22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002206538 +45 chanx_right_in[12]:21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002206538 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:37 0.0006000333 +1 chanx_right_in[12]:25 chanx_right_in[12]:24 0.00341 +2 chanx_right_in[12]:24 chanx_right_in[12]:23 0.004535892 +3 chanx_right_in[12]:23 chanx_right_in[12]:22 0.00341 +4 chanx_right_in[12]:22 chanx_right_in[12]:21 0.006496183 +5 chanx_right_in[12]:20 chanx_right_in[12]:19 0.00341 +6 chanx_right_in[12]:20 chanx_right_in[12]:2 5.69697e-05 +7 chanx_right_in[12]:21 chanx_right_in[12]:20 0.00341 +8 chanx_right_in[12]:19 chanx_right_in[12]:18 0.009622769 +9 chanx_right_in[12]:17 chanx_right_in[12]:16 0.0007410715 +10 chanx_right_in[12]:18 chanx_right_in[12]:17 0.0045 +11 chanx_right_in[12]:16 chanx_right_in[12]:15 0.0045 +12 chanx_right_in[12]:15 chanx_right_in[12]:14 0.0005267857 +13 chanx_right_in[12]:13 chanx_right_in[12]:12 0.0003035714 +14 chanx_right_in[12]:14 chanx_right_in[12]:13 0.0045 +15 chanx_right_in[12]:11 chanx_right_in[12]:10 0.0045 +16 chanx_right_in[12]:10 chanx_right_in[12]:9 0.005383929 +17 chanx_right_in[12]:8 chanx_right_in[12]:7 0.004026785 +18 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0045 +19 chanx_right_in[12]:7 chanx_right_in[12]:6 0.0045 +20 chanx_right_in[12]:6 chanx_right_in[12]:5 0.006901786 +21 chanx_right_in[12]:4 chanx_right_in[12]:3 0.001979911 +22 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0045 +23 chanx_right_in[12]:3 ropt_mt_inst_733:A 0.152 +24 chanx_right_in[12]:26 chanx_right_in[12]:25 0.0004977679 +25 chanx_right_in[12]:27 chanx_right_in[12]:26 0.00341 +26 chanx_right_in[12]:29 chanx_right_in[12]:28 0.00341 +27 chanx_right_in[12]:28 chanx_right_in[12]:27 0.0003720833 +28 chanx_right_in[12]:30 chanx_right_in[12]:29 0.0045 +29 chanx_right_in[12]:32 chanx_right_in[12]:31 0.002424107 +30 chanx_right_in[12]:33 chanx_right_in[12]:32 0.0045 +31 chanx_right_in[12]:34 chanx_right_in[12]:33 0.01235491 +32 chanx_right_in[12]:35 chanx_right_in[12]:34 0.00341 +33 chanx_right_in[12]:12 chanx_right_in[12]:11 0.002013393 +34 chanx_right_in[12]:31 chanx_right_in[12]:30 0.0003035715 +35 chanx_right_in[12]:36 chanx_right_in[12]:35 0.002377025 +36 chanx_right_in[12]:37 chanx_right_in[12]:36 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[0] 0.002767303 //LENGTH 21.825 LUMPCC 0.0009669397 DR + +*CONN +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.925 69.360 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 51.695 58.820 +*I mux_right_track_12\/mux_l1_in_0_:S I *L 0.00357 *C 52.080 69.020 +*N mux_tree_tapbuf_size2_5_sram[0]:3 *C 52.043 69.020 +*N mux_tree_tapbuf_size2_5_sram[0]:4 *C 51.658 58.820 +*N mux_tree_tapbuf_size2_5_sram[0]:5 *C 48.805 58.820 +*N mux_tree_tapbuf_size2_5_sram[0]:6 *C 48.760 58.865 +*N mux_tree_tapbuf_size2_5_sram[0]:7 *C 48.760 68.975 +*N mux_tree_tapbuf_size2_5_sram[0]:8 *C 48.760 69.020 +*N mux_tree_tapbuf_size2_5_sram[0]:9 *C 45.540 69.020 +*N mux_tree_tapbuf_size2_5_sram[0]:10 *C 45.540 69.360 +*N mux_tree_tapbuf_size2_5_sram[0]:11 *C 44.963 69.360 + +*CAP +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_12\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[0]:3 0.0001548928 +4 mux_tree_tapbuf_size2_5_sram[0]:4 0.0002034312 +5 mux_tree_tapbuf_size2_5_sram[0]:5 0.0002034312 +6 mux_tree_tapbuf_size2_5_sram[0]:6 0.0002470657 +7 mux_tree_tapbuf_size2_5_sram[0]:7 0.0002470657 +8 mux_tree_tapbuf_size2_5_sram[0]:8 0.0003786748 +9 mux_tree_tapbuf_size2_5_sram[0]:9 0.0002151491 +10 mux_tree_tapbuf_size2_5_sram[0]:10 8.552378e-05 +11 mux_tree_tapbuf_size2_5_sram[0]:11 6.212837e-05 +12 mux_tree_tapbuf_size2_5_sram[0]:7 chanx_right_in[11]:4 0.0002757011 +13 mux_tree_tapbuf_size2_5_sram[0]:6 chanx_right_in[11]:5 0.0002757011 +14 mux_tree_tapbuf_size2_5_sram[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.872108e-05 +15 mux_tree_tapbuf_size2_5_sram[0]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.872108e-05 +16 mux_tree_tapbuf_size2_5_sram[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001390477 +17 mux_tree_tapbuf_size2_5_sram[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001390477 + +*RES +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_5_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:10 0.000515625 +2 mux_tree_tapbuf_size2_5_sram[0]:3 mux_right_track_12\/mux_l1_in_0_:S 0.152 +3 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:3 0.002930804 +5 mux_tree_tapbuf_size2_5_sram[0]:7 mux_tree_tapbuf_size2_5_sram[0]:6 0.009026786 +6 mux_tree_tapbuf_size2_5_sram[0]:5 mux_tree_tapbuf_size2_5_sram[0]:4 0.002546875 +7 mux_tree_tapbuf_size2_5_sram[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 0.0045 +8 mux_tree_tapbuf_size2_5_sram[0]:4 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size2_5_sram[0]:10 mux_tree_tapbuf_size2_5_sram[0]:9 0.0003035715 +10 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:8 0.002875 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.001025009 //LENGTH 9.380 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/FTB_1__22:X O *L 0 *C 67.845 36.380 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 61.815 39.100 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 61.815 39.100 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 62.100 39.100 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 62.100 39.055 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 62.100 36.425 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 62.145 36.380 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 67.808 36.380 + +*CAP +0 mem_top_track_0\/FTB_1__22:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 4.416133e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 4.939473e-05 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0001428272 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001428272 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0003218991 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0003218991 + +*RES +0 mem_top_track_0\/FTB_1__22:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.002348215 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.005055804 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_8_ccff_tail[0] 0.0005533446 //LENGTH 4.380 LUMPCC 0 DR + +*CONN +*I mem_right_track_18\/FTB_9__30:X O *L 0 *C 94.075 45.220 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 93.095 47.940 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 *C 93.133 47.940 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 *C 93.795 47.940 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 *C 93.840 47.895 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 *C 93.840 45.265 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 *C 93.840 45.220 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 *C 94.075 45.220 + +*CAP +0 mem_right_track_18\/FTB_9__30:X 1e-06 +1 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 6.519384e-05 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 6.519384e-05 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 0.0001555559 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 0.0001555559 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 5.705256e-05 +7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 5.279246e-05 + +*RES +0 mem_right_track_18\/FTB_9__30:X mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[2] 0.00264413 //LENGTH 19.350 LUMPCC 0.0006018346 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 71.605 77.520 +*I mem_right_track_2\/FTB_15__36:A I *L 0.001746 *C 79.120 69.360 +*I mux_right_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 79.940 72.375 +*N mux_tree_tapbuf_size5_0_sram[2]:3 *C 79.940 72.375 +*N mux_tree_tapbuf_size5_0_sram[2]:4 *C 79.883 72.080 +*N mux_tree_tapbuf_size5_0_sram[2]:5 *C 79.157 69.360 +*N mux_tree_tapbuf_size5_0_sram[2]:6 *C 79.995 69.360 +*N mux_tree_tapbuf_size5_0_sram[2]:7 *C 80.040 69.405 +*N mux_tree_tapbuf_size5_0_sram[2]:8 *C 80.040 72.035 +*N mux_tree_tapbuf_size5_0_sram[2]:9 *C 79.983 72.110 +*N mux_tree_tapbuf_size5_0_sram[2]:10 *C 74.565 72.080 +*N mux_tree_tapbuf_size5_0_sram[2]:11 *C 74.520 72.125 +*N mux_tree_tapbuf_size5_0_sram[2]:12 *C 74.520 77.475 +*N mux_tree_tapbuf_size5_0_sram[2]:13 *C 74.475 77.520 +*N mux_tree_tapbuf_size5_0_sram[2]:14 *C 71.642 77.520 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_2\/FTB_15__36:A 1e-06 +2 mux_right_track_2\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_0_sram[2]:3 5.254088e-05 +4 mux_tree_tapbuf_size5_0_sram[2]:4 2.169801e-05 +5 mux_tree_tapbuf_size5_0_sram[2]:5 7.965398e-05 +6 mux_tree_tapbuf_size5_0_sram[2]:6 7.965398e-05 +7 mux_tree_tapbuf_size5_0_sram[2]:7 0.0001983395 +8 mux_tree_tapbuf_size5_0_sram[2]:8 0.0001983395 +9 mux_tree_tapbuf_size5_0_sram[2]:9 0.0002883674 +10 mux_tree_tapbuf_size5_0_sram[2]:10 0.0002429009 +11 mux_tree_tapbuf_size5_0_sram[2]:11 0.0003212845 +12 mux_tree_tapbuf_size5_0_sram[2]:12 0.0003212845 +13 mux_tree_tapbuf_size5_0_sram[2]:13 0.0001176157 +14 mux_tree_tapbuf_size5_0_sram[2]:14 0.0001176157 +15 mux_tree_tapbuf_size5_0_sram[2]:13 mux_tree_tapbuf_size5_0_sram[1]:5 0.0001200522 +16 mux_tree_tapbuf_size5_0_sram[2]:14 mux_tree_tapbuf_size5_0_sram[1]:7 0.0001200522 +17 mux_tree_tapbuf_size5_0_sram[2]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001150152 +18 mux_tree_tapbuf_size5_0_sram[2]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001150152 +19 mux_tree_tapbuf_size5_0_sram[2]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.559319e-05 +20 mux_tree_tapbuf_size5_0_sram[2]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.567547e-07 +21 mux_tree_tapbuf_size5_0_sram[2]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.559319e-05 +22 mux_tree_tapbuf_size5_0_sram[2]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.567547e-07 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_0_sram[2]:14 0.152 +1 mux_tree_tapbuf_size5_0_sram[2]:3 mux_right_track_2\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_0_sram[2]:10 mux_tree_tapbuf_size5_0_sram[2]:9 0.004837054 +3 mux_tree_tapbuf_size5_0_sram[2]:11 mux_tree_tapbuf_size5_0_sram[2]:10 0.0045 +4 mux_tree_tapbuf_size5_0_sram[2]:13 mux_tree_tapbuf_size5_0_sram[2]:12 0.0045 +5 mux_tree_tapbuf_size5_0_sram[2]:12 mux_tree_tapbuf_size5_0_sram[2]:11 0.004776786 +6 mux_tree_tapbuf_size5_0_sram[2]:14 mux_tree_tapbuf_size5_0_sram[2]:13 0.002529018 +7 mux_tree_tapbuf_size5_0_sram[2]:5 mem_right_track_2\/FTB_15__36:A 0.152 +8 mux_tree_tapbuf_size5_0_sram[2]:6 mux_tree_tapbuf_size5_0_sram[2]:5 0.0007477678 +9 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:6 0.0045 +10 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:8 0.0045 +11 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:4 8.928572e-05 +12 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:3 0.0001142241 +13 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[2]:7 0.002348214 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.0006635461 //LENGTH 4.920 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/FTB_13__34:X O *L 0 *C 64.120 89.080 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.285 91.460 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 62.285 91.460 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 63.895 91.460 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 63.940 91.415 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 63.940 89.125 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 63.940 89.080 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 64.120 89.080 + +*CAP +0 mem_right_track_0\/FTB_13__34:X 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0001465315 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0001141561 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001452055 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001452055 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 5.639722e-05 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 5.40503e-05 + +*RES +0 mem_right_track_0\/FTB_13__34:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0014375 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 9.78261e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001663904 //LENGTH 13.060 LUMPCC 0.0001580474 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 51.235 44.200 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.765 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.765 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.860 47.215 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 41.860 44.245 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 41.905 44.200 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 51.198 44.200 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.66359e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001799923 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001799923 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005586182 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005586182 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_2_sram[0]:7 1.067306e-06 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_2_sram[0]:9 7.79564e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_2_sram[0]:8 1.067306e-06 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_2_sram[0]:10 7.79564e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002651786 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.008296875 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005897602 //LENGTH 51.780 LUMPCC 0.001140273 DR + +*CONN +*I mux_right_track_12\/mux_l2_in_0_:X O *L 0 *C 52.725 52.360 +*I mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 90.435 39.310 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 90.435 39.310 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 90.160 39.440 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 90.160 39.485 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 90.160 47.543 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 90.153 47.600 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 52.908 47.600 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 52.900 47.657 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 52.900 52.315 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 52.900 52.360 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 52.725 52.360 + +*CAP +0 mux_right_track_12\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.897753e-05 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.240908e-05 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004659522 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004659522 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001579572 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001579572 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000227948 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.000227948 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.451125e-05 +11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.248831e-05 +12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[14]:8 3.998586e-05 +13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[14]:9 0.0002050842 +14 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[14]:7 3.998586e-05 +15 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[14]:8 0.0002050842 +16 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[7]:8 4.923371e-05 +17 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[7]:9 0.0001228177 +18 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[7]:9 4.923371e-05 +19 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[7]:10 0.0001228177 +20 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:185 7.941043e-07 +21 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:228 1.588576e-05 +22 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:184 7.941043e-07 +23 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:189 1.588576e-05 +24 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:183 3.979173e-05 +25 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:198 2.387164e-05 +26 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:199 7.109609e-05 +27 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:109 1.575396e-06 +28 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:182 3.979173e-05 +29 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:193 2.387164e-05 +30 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:198 7.109609e-05 +31 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:106 1.575396e-06 + +*RES +0 mux_right_track_12\/mux_l2_in_0_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.004158483 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00583505 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.007194197 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001494565 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009753769 //LENGTH 7.145 LUMPCC 0.0003038569 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 55.485 71.740 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.980 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.943 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.545 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.500 69.065 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.500 71.695 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 57.455 71.740 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 55.523 71.740 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.729612e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.729612e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001697077 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001697077 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.775623e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.775623e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_42_[0]:12 8.550036e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_42_[0]:11 8.550036e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size6_0_sram[1]:12 6.635064e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_0_sram[1]:13 6.635064e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:14 7.744236e-08 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:15 7.744236e-08 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001173284 //LENGTH 8.610 LUMPCC 0.0003433861 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_1_:X O *L 0 *C 89.065 56.100 +*I mux_right_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 92.175 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 92.138 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 89.285 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 89.240 60.815 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 89.240 56.145 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 89.240 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 89.065 56.100 + +*CAP +0 mux_right_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001217585 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001217585 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002340889 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002340889 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.087586e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.532741e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:14 5.169951e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:5 5.169951e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001199936 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001199936 + +*RES +0 mux_right_track_4\/mux_l2_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002546875 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004169643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007650384 //LENGTH 6.730 LUMPCC 0.0001674457 DR + +*CONN +*I mux_right_track_6\/mux_l2_in_1_:X O *L 0 *C 77.455 88.740 +*I mux_right_track_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 78.835 93.160 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.797 93.160 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 78.245 93.160 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 78.200 93.115 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 78.200 88.785 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 78.155 88.740 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 77.493 88.740 + +*CAP +0 mux_right_track_6\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_6\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.112124e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.112124e-05 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001662601 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001662601 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.041503e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.041503e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:8 3.261947e-06 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:18 3.949742e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:6 3.261947e-06 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:9 3.949742e-05 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.096349e-05 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.096349e-05 + +*RES +0 mux_right_track_6\/mux_l2_in_1_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_6\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004933035 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003866071 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005915179 + +*END + +*D_NET chany_top_out[19] 0.001314929 //LENGTH 9.135 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 31.280 99.960 +*P chany_top_out[19] O *L 0.7423 *C 25.760 102.150 +*N chany_top_out[19]:2 *C 25.760 101.320 +*N chany_top_out[19]:3 *C 26.680 101.320 +*N chany_top_out[19]:4 *C 26.680 99.968 +*N chany_top_out[19]:5 *C 26.700 99.960 +*N chany_top_out[19]:6 *C 28.513 99.960 +*N chany_top_out[19]:7 *C 28.520 99.960 +*N chany_top_out[19]:8 *C 28.565 99.960 +*N chany_top_out[19]:9 *C 31.243 99.960 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 chany_top_out[19] 7.117076e-05 +2 chany_top_out[19]:2 0.0001316835 +3 chany_top_out[19]:3 0.000229654 +4 chany_top_out[19]:4 0.0001691412 +5 chany_top_out[19]:5 0.0001513765 +6 chany_top_out[19]:6 0.0001513765 +7 chany_top_out[19]:7 3.157212e-05 +8 chany_top_out[19]:8 0.0001889775 +9 chany_top_out[19]:9 0.0001889775 + +*RES +0 ropt_mt_inst_730:X chany_top_out[19]:9 0.152 +1 chany_top_out[19]:9 chany_top_out[19]:8 0.002390625 +2 chany_top_out[19]:8 chany_top_out[19]:7 0.0045 +3 chany_top_out[19]:7 chany_top_out[19]:6 0.00341 +4 chany_top_out[19]:6 chany_top_out[19]:5 0.0002839583 +5 chany_top_out[19]:5 chany_top_out[19]:4 0.00341 +6 chany_top_out[19]:4 chany_top_out[19]:3 0.0002118916 +7 chany_top_out[19]:2 chany_top_out[19] 0.0001300333 +8 chany_top_out[19]:3 chany_top_out[19]:2 0.0001441333 + +*END + +*D_NET chany_top_out[14] 0.001562924 //LENGTH 11.920 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 13.075 96.560 +*P chany_top_out[14] O *L 0.7423 *C 7.360 102.150 +*N chany_top_out[14]:2 *C 7.360 96.568 +*N chany_top_out[14]:3 *C 7.380 96.560 +*N chany_top_out[14]:4 *C 12.873 96.560 +*N chany_top_out[14]:5 *C 12.880 96.560 +*N chany_top_out[14]:6 *C 12.880 96.560 +*N chany_top_out[14]:7 *C 13.075 96.560 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 chany_top_out[14] 0.0003277178 +2 chany_top_out[14]:2 0.0003277178 +3 chany_top_out[14]:3 0.0003767065 +4 chany_top_out[14]:4 0.0003767065 +5 chany_top_out[14]:5 3.808757e-05 +6 chany_top_out[14]:6 5.765123e-05 +7 chany_top_out[14]:7 5.733621e-05 + +*RES +0 ropt_mt_inst_765:X chany_top_out[14]:7 0.152 +1 chany_top_out[14]:7 chany_top_out[14]:6 0.0001059783 +2 chany_top_out[14]:6 chany_top_out[14]:5 0.0045 +3 chany_top_out[14]:5 chany_top_out[14]:4 0.00341 +4 chany_top_out[14]:4 chany_top_out[14]:3 0.0008604917 +5 chany_top_out[14]:3 chany_top_out[14]:2 0.00341 +6 chany_top_out[14]:2 chany_top_out[14] 0.0008745916 + +*END + +*D_NET ropt_net_145 0.001080144 //LENGTH 7.110 LUMPCC 0.0003115187 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 52.900 97.240 +*I ropt_mt_inst_768:A I *L 0.001766 *C 48.760 99.280 +*N ropt_net_145:2 *C 48.797 99.280 +*N ropt_net_145:3 *C 49.175 99.280 +*N ropt_net_145:4 *C 49.220 99.235 +*N ropt_net_145:5 *C 49.220 97.285 +*N ropt_net_145:6 *C 49.265 97.240 +*N ropt_net_145:7 *C 52.863 97.240 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_145:2 6.032524e-05 +3 ropt_net_145:3 6.032524e-05 +4 ropt_net_145:4 0.0001385745 +5 ropt_net_145:5 0.0001385745 +6 ropt_net_145:6 0.0001844128 +7 ropt_net_145:7 0.0001844128 +8 ropt_net_145:4 ropt_net_120:4 1.200898e-05 +9 ropt_net_145:6 ropt_net_120:6 0.0001437504 +10 ropt_net_145:5 ropt_net_120:5 1.200898e-05 +11 ropt_net_145:7 ropt_net_120:7 0.0001437504 + +*RES +0 ropt_mt_inst_739:X ropt_net_145:7 0.152 +1 ropt_net_145:2 ropt_mt_inst_768:A 0.152 +2 ropt_net_145:3 ropt_net_145:2 0.0003370536 +3 ropt_net_145:4 ropt_net_145:3 0.0045 +4 ropt_net_145:6 ropt_net_145:5 0.0045 +5 ropt_net_145:5 ropt_net_145:4 0.001741071 +6 ropt_net_145:7 ropt_net_145:6 0.003212054 + +*END + +*D_NET ropt_net_147 0.0004499419 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 107.180 64.600 +*I ropt_mt_inst_772:A I *L 0.001766 *C 106.260 66.640 +*N ropt_net_147:2 *C 106.297 66.640 +*N ropt_net_147:3 *C 107.135 66.640 +*N ropt_net_147:4 *C 107.180 66.595 +*N ropt_net_147:5 *C 107.180 64.645 +*N ropt_net_147:6 *C 107.180 64.600 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_147:2 8.900049e-05 +3 ropt_net_147:3 8.900049e-05 +4 ropt_net_147:4 0.0001191519 +5 ropt_net_147:5 0.0001191519 +6 ropt_net_147:6 3.163709e-05 + +*RES +0 ropt_mt_inst_745:X ropt_net_147:6 0.152 +1 ropt_net_147:6 ropt_net_147:5 0.0045 +2 ropt_net_147:5 ropt_net_147:4 0.001741072 +3 ropt_net_147:3 ropt_net_147:2 0.0007477679 +4 ropt_net_147:4 ropt_net_147:3 0.0045 +5 ropt_net_147:2 ropt_mt_inst_772:A 0.152 + +*END + +*D_NET ropt_net_142 0.0010311 //LENGTH 8.295 LUMPCC 0.0001140408 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 110.135 44.200 +*I ropt_mt_inst_761:A I *L 0.001767 *C 106.260 42.160 +*N ropt_net_142:2 *C 106.297 42.160 +*N ropt_net_142:3 *C 110.815 42.160 +*N ropt_net_142:4 *C 110.860 42.205 +*N ropt_net_142:5 *C 110.860 44.155 +*N ropt_net_142:6 *C 110.815 44.200 +*N ropt_net_142:7 *C 110.172 44.200 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_142:2 0.0002868144 +3 ropt_net_142:3 0.0002868144 +4 ropt_net_142:4 0.0001142095 +5 ropt_net_142:5 0.0001142095 +6 ropt_net_142:6 5.650587e-05 +7 ropt_net_142:7 5.650587e-05 +8 ropt_net_142:7 chanx_right_out[9]:8 3.014578e-05 +9 ropt_net_142:6 chanx_right_out[9]:7 3.014578e-05 +10 ropt_net_142:5 chanx_right_out[9]:4 1.475934e-05 +11 ropt_net_142:5 chanx_right_out[9]:6 1.211528e-05 +12 ropt_net_142:4 chanx_right_out[9]:3 1.475934e-05 +13 ropt_net_142:4 chanx_right_out[9]:5 1.211528e-05 + +*RES +0 ropt_mt_inst_752:X ropt_net_142:7 0.152 +1 ropt_net_142:7 ropt_net_142:6 0.0005736608 +2 ropt_net_142:6 ropt_net_142:5 0.0045 +3 ropt_net_142:5 ropt_net_142:4 0.001741071 +4 ropt_net_142:3 ropt_net_142:2 0.004033482 +5 ropt_net_142:4 ropt_net_142:3 0.0045 +6 ropt_net_142:2 ropt_mt_inst_761:A 0.152 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..11d6843 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef @@ -0,0 +1,23861 @@ +*SPEF "1481-1998" +*DESIGN "sb_0__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 0.690 59.160 +chany_top_in[0] I *C 67.620 129.880 +chany_top_in[1] I *C 62.100 129.880 +chany_top_in[2] I *C 70.380 129.880 +chany_top_in[3] I *C 45.540 129.880 +chany_top_in[4] I *C 43.700 129.880 +chany_top_in[5] I *C 28.980 129.880 +chany_top_in[6] I *C 69.460 129.880 +chany_top_in[7] I *C 68.540 129.880 +chany_top_in[8] I *C 63.020 129.880 +chany_top_in[9] I *C 51.980 129.880 +chany_top_in[10] I *C 50.140 129.880 +chany_top_in[11] I *C 41.860 129.880 +chany_top_in[12] I *C 72.220 129.880 +chany_top_in[13] I *C 20.240 129.880 +chany_top_in[14] I *C 29.440 129.880 +chany_top_in[15] I *C 49.680 129.880 +chany_top_in[16] I *C 58.880 129.880 +chany_top_in[17] I *C 14.720 129.880 +chany_top_in[18] I *C 44.160 129.880 +chany_top_in[19] I *C 47.380 129.880 +top_left_grid_pin_1_[0] I *C 2.300 129.880 +chanx_right_in[0] I *C 112.470 48.960 +chanx_right_in[1] I *C 112.470 99.280 +chanx_right_in[2] I *C 112.470 55.760 +chanx_right_in[3] I *C 112.470 43.520 +chanx_right_in[4] I *C 112.470 93.840 +chanx_right_in[5] I *C 112.470 95.200 +chanx_right_in[6] I *C 112.470 77.520 +chanx_right_in[7] I *C 112.470 69.360 +chanx_right_in[8] I *C 112.470 44.880 +chanx_right_in[9] I *C 112.470 51.000 +chanx_right_in[10] I *C 112.470 36.720 +chanx_right_in[11] I *C 112.470 38.080 +chanx_right_in[12] I *C 112.470 96.560 +chanx_right_in[13] I *C 112.470 32.640 +chanx_right_in[14] I *C 112.470 91.120 +chanx_right_in[15] I *C 112.470 57.120 +chanx_right_in[16] I *C 112.470 39.440 +chanx_right_in[17] I *C 112.470 34.000 +chanx_right_in[18] I *C 112.470 65.280 +chanx_right_in[19] I *C 112.470 31.280 +right_top_grid_pin_42_[0] I *C 109.940 102.680 +right_top_grid_pin_43_[0] I *C 83.950 126.480 +right_top_grid_pin_44_[0] I *C 110.860 102.680 +right_top_grid_pin_45_[0] I *C 109.020 102.680 +right_top_grid_pin_46_[0] I *C 83.950 119.000 +right_top_grid_pin_47_[0] I *C 83.950 117.640 +right_top_grid_pin_48_[0] I *C 107.180 102.680 +right_top_grid_pin_49_[0] I *C 108.100 102.680 +chany_bottom_in[0] I *C 65.780 0.680 +chany_bottom_in[1] I *C 14.720 0.680 +chany_bottom_in[2] I *C 71.300 0.680 +chany_bottom_in[3] I *C 13.800 0.680 +chany_bottom_in[4] I *C 73.140 0.680 +chany_bottom_in[5] I *C 49.220 0.680 +chany_bottom_in[6] I *C 52.900 0.680 +chany_bottom_in[7] I *C 22.080 0.680 +chany_bottom_in[8] I *C 23.920 0.680 +chany_bottom_in[9] I *C 23.000 0.680 +chany_bottom_in[10] I *C 51.980 0.680 +chany_bottom_in[11] I *C 30.820 0.680 +chany_bottom_in[12] I *C 63.940 0.680 +chany_bottom_in[13] I *C 72.220 0.680 +chany_bottom_in[14] I *C 43.700 0.680 +chany_bottom_in[15] I *C 46.460 0.680 +chany_bottom_in[16] I *C 41.860 0.680 +chany_bottom_in[17] I *C 29.900 0.680 +chany_bottom_in[18] I *C 26.680 0.680 +chany_bottom_in[19] I *C 24.840 0.680 +bottom_left_grid_pin_1_[0] I *C 2.300 0.680 +ccff_head[0] I *C 112.470 88.400 +chany_top_out[0] O *C 42.780 129.880 +chany_top_out[1] O *C 25.760 129.880 +chany_top_out[2] O *C 71.300 129.880 +chany_top_out[3] O *C 49.220 129.880 +chany_top_out[4] O *C 36.340 129.880 +chany_top_out[5] O *C 44.620 129.880 +chany_top_out[6] O *C 5.520 129.880 +chany_top_out[7] O *C 69.000 129.880 +chany_top_out[8] O *C 22.080 129.880 +chany_top_out[9] O *C 9.200 129.880 +chany_top_out[10] O *C 46.460 129.880 +chany_top_out[11] O *C 51.060 129.880 +chany_top_out[12] O *C 7.360 129.880 +chany_top_out[13] O *C 23.920 129.880 +chany_top_out[14] O *C 7.360 129.880 +chany_top_out[15] O *C 46.000 129.880 +chany_top_out[16] O *C 48.300 129.880 +chany_top_out[17] O *C 52.900 129.880 +chany_top_out[18] O *C 47.840 129.880 +chany_top_out[19] O *C 25.760 129.880 +chanx_right_out[0] O *C 112.470 84.320 +chanx_right_out[1] O *C 112.470 82.960 +chanx_right_out[2] O *C 112.470 62.560 +chanx_right_out[3] O *C 112.470 74.120 +chanx_right_out[4] O *C 112.470 80.240 +chanx_right_out[5] O *C 112.470 72.080 +chanx_right_out[6] O *C 112.470 58.480 +chanx_right_out[7] O *C 112.470 35.360 +chanx_right_out[8] O *C 112.470 46.240 +chanx_right_out[9] O *C 112.470 63.920 +chanx_right_out[10] O *C 112.470 61.200 +chanx_right_out[11] O *C 112.470 78.880 +chanx_right_out[12] O *C 112.470 42.160 +chanx_right_out[13] O *C 112.470 85.680 +chanx_right_out[14] O *C 112.470 47.600 +chanx_right_out[15] O *C 112.470 68.000 +chanx_right_out[16] O *C 112.470 40.800 +chanx_right_out[17] O *C 112.470 66.640 +chanx_right_out[18] O *C 112.470 52.360 +chanx_right_out[19] O *C 112.470 89.760 +chany_bottom_out[0] O *C 50.140 0.680 +chany_bottom_out[1] O *C 34.500 0.680 +chany_bottom_out[2] O *C 66.700 0.680 +chany_bottom_out[3] O *C 44.620 0.680 +chany_bottom_out[4] O *C 51.060 0.680 +chany_bottom_out[5] O *C 45.540 0.680 +chany_bottom_out[6] O *C 70.380 0.680 +chany_bottom_out[7] O *C 68.540 0.680 +chany_bottom_out[8] O *C 69.460 0.680 +chany_bottom_out[9] O *C 25.760 0.680 +chany_bottom_out[10] O *C 42.780 0.680 +chany_bottom_out[11] O *C 48.300 0.680 +chany_bottom_out[12] O *C 67.620 0.680 +chany_bottom_out[13] O *C 49.680 0.680 +chany_bottom_out[14] O *C 46.000 0.680 +chany_bottom_out[15] O *C 47.840 0.680 +chany_bottom_out[16] O *C 28.520 0.680 +chany_bottom_out[17] O *C 47.380 0.680 +chany_bottom_out[18] O *C 23.920 0.680 +chany_bottom_out[19] O *C 25.760 0.680 +ccff_tail[0] O *C 54.280 0.680 +VDD I *C 56.580 65.280 +VSS I *C 56.580 65.280 + +*D_NET chany_top_in[4] 0.02109228 //LENGTH 164.615 LUMPCC 0.006680334 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 43.700 129.270 +*I BUFT_RR_75:A I *L 0.001776 *C 45.540 17.680 +*I mux_bottom_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 67.160 41.820 +*I mux_right_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 70.095 126.140 +*N chany_top_in[4]:4 *C 70.058 126.140 +*N chany_top_in[4]:5 *C 65.840 45.560 +*N chany_top_in[4]:6 *C 67.123 41.820 +*N chany_top_in[4]:7 *C 66.240 41.820 +*N chany_top_in[4]:8 *C 45.578 17.680 +*N chany_top_in[4]:9 *C 54.280 17.680 +*N chany_top_in[4]:10 *C 54.280 18.360 +*N chany_top_in[4]:11 *C 60.215 18.360 +*N chany_top_in[4]:12 *C 60.260 18.405 +*N chany_top_in[4]:13 *C 60.260 41.435 +*N chany_top_in[4]:14 *C 60.305 41.480 +*N chany_top_in[4]:15 *C 66.240 41.510 +*N chany_top_in[4]:16 *C 66.240 41.525 +*N chany_top_in[4]:17 *C 66.240 45.503 +*N chany_top_in[4]:18 *C 66.240 45.560 +*N chany_top_in[4]:19 *C 66.240 45.568 +*N chany_top_in[4]:20 *C 66.240 95.395 +*N chany_top_in[4]:21 *C 66.240 124.433 +*N chany_top_in[4]:22 *C 66.255 124.440 +*N chany_top_in[4]:23 *C 66.698 124.440 +*N chany_top_in[4]:24 *C 66.700 124.498 +*N chany_top_in[4]:25 *C 66.700 126.095 +*N chany_top_in[4]:26 *C 66.700 126.140 +*N chany_top_in[4]:27 *C 43.745 126.140 +*N chany_top_in[4]:28 *C 43.700 126.185 + +*CAP +0 chany_top_in[4] 0.0001781548 +1 BUFT_RR_75:A 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:A1 1e-06 +3 mux_right_track_2\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[4]:4 0.0002326291 +5 chany_top_in[4]:5 7.230758e-05 +6 chany_top_in[4]:6 9.630208e-05 +7 chany_top_in[4]:7 0.0001262423 +8 chany_top_in[4]:8 0.000558835 +9 chany_top_in[4]:9 0.0006021236 +10 chany_top_in[4]:10 0.0004394057 +11 chany_top_in[4]:11 0.0003961172 +12 chany_top_in[4]:12 0.001084032 +13 chany_top_in[4]:13 0.001084032 +14 chany_top_in[4]:14 0.0004483831 +15 chany_top_in[4]:15 0.0004783233 +16 chany_top_in[4]:16 0.0002489884 +17 chany_top_in[4]:17 0.0002489884 +18 chany_top_in[4]:18 7.230758e-05 +19 chany_top_in[4]:19 0.001416877 +20 chany_top_in[4]:20 0.002583887 +21 chany_top_in[4]:21 0.00116701 +22 chany_top_in[4]:22 6.01476e-05 +23 chany_top_in[4]:23 6.01476e-05 +24 chany_top_in[4]:24 0.0001092136 +25 chany_top_in[4]:25 0.0001092136 +26 chany_top_in[4]:26 0.001310982 +27 chany_top_in[4]:27 0.001046137 +28 chany_top_in[4]:28 0.0001781548 +29 chany_top_in[4]:16 chany_top_in[6]:15 2.767161e-08 +30 chany_top_in[4]:16 chany_top_in[6]:19 1.085351e-06 +31 chany_top_in[4]:17 chany_top_in[6]:20 1.085351e-06 +32 chany_top_in[4]:17 chany_top_in[6]:19 2.767161e-08 +33 chany_top_in[4]:19 chany_top_in[6]:23 0.0009255211 +34 chany_top_in[4]:21 chany_top_in[6]:25 0.0004320639 +35 chany_top_in[4]:21 chany_top_in[6]:24 8.809994e-05 +36 chany_top_in[4]:20 chany_top_in[6]:23 8.809994e-05 +37 chany_top_in[4]:20 chany_top_in[6]:24 0.001357585 +38 chany_top_in[4]:27 chany_bottom_in[6]:7 0.0002662871 +39 chany_top_in[4]:26 chany_bottom_in[6]:7 2.26894e-05 +40 chany_top_in[4]:26 chany_bottom_in[6]:6 0.0002662871 +41 chany_top_in[4]:4 chany_bottom_in[6]:6 2.26894e-05 +42 chany_top_in[4]:19 chany_bottom_in[12]:43 0.0004683808 +43 chany_top_in[4]:19 chany_bottom_in[12]:41 0.0002471306 +44 chany_top_in[4]:19 chany_bottom_in[12]:42 0.0001724076 +45 chany_top_in[4]:20 chany_bottom_in[12]:31 0.0002471306 +46 chany_top_in[4]:20 chany_bottom_in[12]:41 0.0001724076 +47 chany_top_in[4]:20 chany_bottom_in[12]:42 0.0004683808 +48 chany_top_in[4]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.750454e-05 +49 chany_top_in[4]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.750454e-05 +50 chany_top_in[4]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 0.0001320814 +51 chany_top_in[4]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 0.0001320814 +52 chany_top_in[4]:27 ropt_net_238:5 0.0002588432 +53 chany_top_in[4]:26 ropt_net_238:6 0.0002588432 +54 chany_top_in[4]:27 ropt_net_232:4 0.0001992463 +55 chany_top_in[4]:26 ropt_net_232:5 0.0001992463 +56 chany_top_in[4] ropt_net_217:4 1.822503e-05 +57 chany_top_in[4]:27 ropt_net_217:3 4.422649e-05 +58 chany_top_in[4]:27 ropt_net_217:6 6.346746e-06 +59 chany_top_in[4]:28 ropt_net_217:5 1.822503e-05 +60 chany_top_in[4]:26 ropt_net_217:2 4.422649e-05 +61 chany_top_in[4]:26 ropt_net_217:5 6.346746e-06 + +*RES +0 chany_top_in[4] chany_top_in[4]:28 0.002754464 +1 chany_top_in[4]:6 mux_bottom_track_3\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[4]:8 BUFT_RR_75:A 0.152 +3 chany_top_in[4]:11 chany_top_in[4]:10 0.005299107 +4 chany_top_in[4]:12 chany_top_in[4]:11 0.0045 +5 chany_top_in[4]:14 chany_top_in[4]:13 0.0045 +6 chany_top_in[4]:13 chany_top_in[4]:12 0.0205625 +7 chany_top_in[4]:27 chany_top_in[4]:26 0.02049554 +8 chany_top_in[4]:28 chany_top_in[4]:27 0.0045 +9 chany_top_in[4]:15 chany_top_in[4]:14 0.005299107 +10 chany_top_in[4]:15 chany_top_in[4]:7 0.0002767857 +11 chany_top_in[4]:16 chany_top_in[4]:15 0.0045 +12 chany_top_in[4]:17 chany_top_in[4]:16 0.003551339 +13 chany_top_in[4]:18 chany_top_in[4]:17 0.00341 +14 chany_top_in[4]:18 chany_top_in[4]:5 5.696969e-05 +15 chany_top_in[4]:19 chany_top_in[4]:18 0.00341 +16 chany_top_in[4]:22 chany_top_in[4]:21 0.00341 +17 chany_top_in[4]:21 chany_top_in[4]:20 0.004549208 +18 chany_top_in[4]:24 chany_top_in[4]:23 0.00341 +19 chany_top_in[4]:23 chany_top_in[4]:22 6.499219e-05 +20 chany_top_in[4]:26 chany_top_in[4]:25 0.0045 +21 chany_top_in[4]:26 chany_top_in[4]:4 0.002997768 +22 chany_top_in[4]:25 chany_top_in[4]:24 0.001426339 +23 chany_top_in[4]:4 mux_right_track_2\/mux_l1_in_0_:A0 0.152 +24 chany_top_in[4]:9 chany_top_in[4]:8 0.007770089 +25 chany_top_in[4]:10 chany_top_in[4]:9 0.0006071429 +26 chany_top_in[4]:7 chany_top_in[4]:6 0.0007879465 +27 chany_top_in[4]:20 chany_top_in[4]:19 0.007806308 + +*END + +*D_NET chanx_right_out[7] 0.00664926 //LENGTH 48.785 LUMPCC 0.0009741295 DR + +*CONN +*I mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 102.120 71.740 +*P chanx_right_out[7] O *L 0.7423 *C 111.855 35.360 +*N chanx_right_out[7]:2 *C 111.780 36.040 +*N chanx_right_out[7]:3 *C 104.900 36.040 +*N chanx_right_out[7]:4 *C 104.880 36.047 +*N chanx_right_out[7]:5 *C 104.880 70.713 +*N chanx_right_out[7]:6 *C 104.860 70.720 +*N chanx_right_out[7]:7 *C 101.668 70.720 +*N chanx_right_out[7]:8 *C 101.660 70.778 +*N chanx_right_out[7]:9 *C 101.660 71.695 +*N chanx_right_out[7]:10 *C 101.705 71.740 +*N chanx_right_out[7]:11 *C 102.083 71.740 + +*CAP +0 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[7] 1e-09 +2 chanx_right_out[7]:2 0.0002815971 +3 chanx_right_out[7]:3 0.0003077994 +4 chanx_right_out[7]:4 0.00213971 +5 chanx_right_out[7]:5 0.00213971 +6 chanx_right_out[7]:6 0.0002659779 +7 chanx_right_out[7]:7 0.0002659779 +8 chanx_right_out[7]:8 8.28078e-05 +9 chanx_right_out[7]:9 8.28078e-05 +10 chanx_right_out[7]:10 5.387207e-05 +11 chanx_right_out[7]:11 5.387207e-05 +12 chanx_right_out[7]:3 chanx_right_in[10]:11 0.0004046765 +13 chanx_right_out[7]:2 chanx_right_in[10] 0.0004046765 +14 chanx_right_out[7] ropt_net_213:5 7.476562e-05 +15 chanx_right_out[7]:3 ropt_net_213:7 7.622629e-06 +16 chanx_right_out[7]:2 ropt_net_213:6 7.622629e-06 +17 chanx_right_out[7]:2 ropt_net_213:4 7.476562e-05 + +*RES +0 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[7]:11 0.152 +1 chanx_right_out[7]:3 chanx_right_out[7]:2 0.001077867 +2 chanx_right_out[7]:4 chanx_right_out[7]:3 0.00341 +3 chanx_right_out[7]:6 chanx_right_out[7]:5 0.00341 +4 chanx_right_out[7]:5 chanx_right_out[7]:4 0.005430849 +5 chanx_right_out[7]:8 chanx_right_out[7]:7 0.00341 +6 chanx_right_out[7]:7 chanx_right_out[7]:6 0.0005001583 +7 chanx_right_out[7]:10 chanx_right_out[7]:9 0.0045 +8 chanx_right_out[7]:9 chanx_right_out[7]:8 0.0008191965 +9 chanx_right_out[7]:11 chanx_right_out[7]:10 0.0003370536 +10 chanx_right_out[7]:2 chanx_right_out[7] 0.0001065333 + +*END + +*D_NET ropt_net_191 0.001311501 //LENGTH 12.195 LUMPCC 9.483719e-05 DR + +*CONN +*I mux_bottom_track_25\/BUFT_P_147:X O *L 0 *C 66.015 14.620 +*I ropt_mt_inst_812:A I *L 0.001766 *C 65.780 6.800 +*N ropt_net_191:2 *C 65.818 6.800 +*N ropt_net_191:3 *C 67.575 6.800 +*N ropt_net_191:4 *C 67.620 6.845 +*N ropt_net_191:5 *C 67.620 14.575 +*N ropt_net_191:6 *C 67.575 14.620 +*N ropt_net_191:7 *C 66.053 14.620 + +*CAP +0 mux_bottom_track_25\/BUFT_P_147:X 1e-06 +1 ropt_mt_inst_812:A 1e-06 +2 ropt_net_191:2 0.0001213678 +3 ropt_net_191:3 0.0001213678 +4 ropt_net_191:4 0.0003765245 +5 ropt_net_191:5 0.0003765245 +6 ropt_net_191:6 0.0001094395 +7 ropt_net_191:7 0.0001094395 +8 ropt_net_191:4 chany_bottom_out[2] 4.741859e-05 +9 ropt_net_191:5 chany_bottom_out[2]:2 4.741859e-05 + +*RES +0 mux_bottom_track_25\/BUFT_P_147:X ropt_net_191:7 0.152 +1 ropt_net_191:2 ropt_mt_inst_812:A 0.152 +2 ropt_net_191:3 ropt_net_191:2 0.001569196 +3 ropt_net_191:4 ropt_net_191:3 0.0045 +4 ropt_net_191:6 ropt_net_191:5 0.0045 +5 ropt_net_191:5 ropt_net_191:4 0.006901786 +6 ropt_net_191:7 ropt_net_191:6 0.001359375 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.005649967 //LENGTH 43.760 LUMPCC 0.001903494 DR + +*CONN +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 97.365 74.800 +*I mux_right_track_18\/mux_l1_in_1_:S I *L 0.00357 *C 78.560 69.360 +*I mux_right_track_18\/mux_l1_in_0_:S I *L 0.00357 *C 76.260 85.000 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.615 80.580 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 75.615 80.580 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 76.245 85.000 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 75.922 85.000 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 75.900 84.955 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 75.900 80.625 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 75.945 80.580 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 78.615 80.580 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 78.660 80.535 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 78.560 69.360 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 78.660 69.405 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 78.660 70.720 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 78.668 70.720 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 97.053 70.720 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 97.060 70.778 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 97.060 74.755 +*N mux_tree_tapbuf_size3_1_sram[0]:19 *C 97.060 74.800 +*N mux_tree_tapbuf_size3_1_sram[0]:20 *C 97.365 74.800 + +*CAP +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_18\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_18\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 5.441353e-05 +5 mux_tree_tapbuf_size3_1_sram[0]:5 5.044228e-05 +6 mux_tree_tapbuf_size3_1_sram[0]:6 5.044228e-05 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0002101419 +8 mux_tree_tapbuf_size3_1_sram[0]:8 0.0002101419 +9 mux_tree_tapbuf_size3_1_sram[0]:9 0.0002066832 +10 mux_tree_tapbuf_size3_1_sram[0]:10 0.0001865608 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.0004790561 +12 mux_tree_tapbuf_size3_1_sram[0]:12 2.886196e-05 +13 mux_tree_tapbuf_size3_1_sram[0]:13 8.198502e-05 +14 mux_tree_tapbuf_size3_1_sram[0]:14 0.0005987764 +15 mux_tree_tapbuf_size3_1_sram[0]:15 0.000528159 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.000528159 +17 mux_tree_tapbuf_size3_1_sram[0]:17 0.0002132718 +18 mux_tree_tapbuf_size3_1_sram[0]:18 0.0002132718 +19 mux_tree_tapbuf_size3_1_sram[0]:19 5.276204e-05 +20 mux_tree_tapbuf_size3_1_sram[0]:20 4.9343e-05 +21 mux_tree_tapbuf_size3_1_sram[0]:15 chanx_right_in[7]:10 0.0004247676 +22 mux_tree_tapbuf_size3_1_sram[0]:16 chanx_right_in[7] 0.0004247676 +23 mux_tree_tapbuf_size3_1_sram[0]:15 chanx_right_in[12]:10 0.0003941383 +24 mux_tree_tapbuf_size3_1_sram[0]:17 chanx_right_in[12]:12 5.753229e-06 +25 mux_tree_tapbuf_size3_1_sram[0]:16 chanx_right_in[12]:11 0.0003941383 +26 mux_tree_tapbuf_size3_1_sram[0]:18 chanx_right_in[12]:13 5.753229e-06 +27 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 6.051376e-05 +28 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 6.051376e-05 +29 mux_tree_tapbuf_size3_1_sram[0]:14 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.446703e-05 +30 mux_tree_tapbuf_size3_1_sram[0]:11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.446703e-05 +31 mux_tree_tapbuf_size3_1_sram[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.210713e-05 +32 mux_tree_tapbuf_size3_1_sram[0]:8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.210713e-05 + +*RES +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.001174107 +2 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:11 0.008763393 +3 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.00341 +4 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.00341 +5 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.002880316 +6 mux_tree_tapbuf_size3_1_sram[0]:19 mux_tree_tapbuf_size3_1_sram[0]:18 0.0045 +7 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.003551339 +8 mux_tree_tapbuf_size3_1_sram[0]:20 mux_tree_tapbuf_size3_1_sram[0]:19 0.0001657609 +9 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.002383929 +10 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.0045 +11 mux_tree_tapbuf_size3_1_sram[0]:4 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size3_1_sram[0]:12 mux_right_track_18\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.0045 +14 mux_tree_tapbuf_size3_1_sram[0]:5 mux_right_track_18\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size3_1_sram[0]:6 mux_tree_tapbuf_size3_1_sram[0]:5 0.0001752718 +16 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:6 0.0045 +17 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:8 0.0045 +18 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:4 0.0001793478 +19 mux_tree_tapbuf_size3_1_sram[0]:8 mux_tree_tapbuf_size3_1_sram[0]:7 0.003866072 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[2] 0.002830205 //LENGTH 23.085 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 37.565 85.680 +*I mux_top_track_24\/mux_l3_in_0_:S I *L 0.008363 *C 26.050 85.588 +*I mem_top_track_24\/FTB_13__43:A I *L 0.001746 *C 41.400 80.240 +*N mux_tree_tapbuf_size4_0_sram[2]:3 *C 41.363 80.240 +*N mux_tree_tapbuf_size4_0_sram[2]:4 *C 37.765 80.240 +*N mux_tree_tapbuf_size4_0_sram[2]:5 *C 37.720 80.285 +*N mux_tree_tapbuf_size4_0_sram[2]:6 *C 26.130 85.465 +*N mux_tree_tapbuf_size4_0_sram[2]:7 *C 26.130 85.450 +*N mux_tree_tapbuf_size4_0_sram[2]:8 *C 26.130 85.028 +*N mux_tree_tapbuf_size4_0_sram[2]:9 *C 26.138 85.000 +*N mux_tree_tapbuf_size4_0_sram[2]:10 *C 37.712 85.000 +*N mux_tree_tapbuf_size4_0_sram[2]:11 *C 37.720 85.000 +*N mux_tree_tapbuf_size4_0_sram[2]:12 *C 37.720 85.635 +*N mux_tree_tapbuf_size4_0_sram[2]:13 *C 37.720 85.680 +*N mux_tree_tapbuf_size4_0_sram[2]:14 *C 37.565 85.680 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:S 3.490398e-05 +2 mem_top_track_24\/FTB_13__43:A 1e-06 +3 mux_tree_tapbuf_size4_0_sram[2]:3 0.0002186343 +4 mux_tree_tapbuf_size4_0_sram[2]:4 0.0002186343 +5 mux_tree_tapbuf_size4_0_sram[2]:5 0.0002715138 +6 mux_tree_tapbuf_size4_0_sram[2]:6 3.490398e-05 +7 mux_tree_tapbuf_size4_0_sram[2]:7 5.433735e-05 +8 mux_tree_tapbuf_size4_0_sram[2]:8 5.433735e-05 +9 mux_tree_tapbuf_size4_0_sram[2]:9 0.0007143966 +10 mux_tree_tapbuf_size4_0_sram[2]:10 0.0007143966 +11 mux_tree_tapbuf_size4_0_sram[2]:11 0.0003490658 +12 mux_tree_tapbuf_size4_0_sram[2]:12 4.579522e-05 +13 mux_tree_tapbuf_size4_0_sram[2]:13 5.879794e-05 +14 mux_tree_tapbuf_size4_0_sram[2]:14 5.848773e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_0_sram[2]:14 0.152 +1 mux_tree_tapbuf_size4_0_sram[2]:6 mux_top_track_24\/mux_l3_in_0_:S 7.692308e-05 +2 mux_tree_tapbuf_size4_0_sram[2]:7 mux_tree_tapbuf_size4_0_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size4_0_sram[2]:8 mux_tree_tapbuf_size4_0_sram[2]:7 0.000203125 +4 mux_tree_tapbuf_size4_0_sram[2]:9 mux_tree_tapbuf_size4_0_sram[2]:8 0.00341 +5 mux_tree_tapbuf_size4_0_sram[2]:11 mux_tree_tapbuf_size4_0_sram[2]:10 0.00341 +6 mux_tree_tapbuf_size4_0_sram[2]:11 mux_tree_tapbuf_size4_0_sram[2]:5 0.004209822 +7 mux_tree_tapbuf_size4_0_sram[2]:10 mux_tree_tapbuf_size4_0_sram[2]:9 0.001813416 +8 mux_tree_tapbuf_size4_0_sram[2]:13 mux_tree_tapbuf_size4_0_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size4_0_sram[2]:12 mux_tree_tapbuf_size4_0_sram[2]:11 0.0005669643 +10 mux_tree_tapbuf_size4_0_sram[2]:14 mux_tree_tapbuf_size4_0_sram[2]:13 8.423914e-05 +11 mux_tree_tapbuf_size4_0_sram[2]:4 mux_tree_tapbuf_size4_0_sram[2]:3 0.003212054 +12 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:4 0.0045 +13 mux_tree_tapbuf_size4_0_sram[2]:3 mem_top_track_24\/FTB_13__43:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_4_sram[2] 0.001568314 //LENGTH 11.930 LUMPCC 0.0002877493 DR + +*CONN +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 64.245 91.460 +*I mux_right_track_12\/mux_l3_in_0_:S I *L 0.00357 *C 63.380 89.080 +*I mem_right_track_12\/FTB_17__47:A I *L 0.001746 *C 68.080 93.840 +*N mux_tree_tapbuf_size4_4_sram[2]:3 *C 68.058 93.868 +*N mux_tree_tapbuf_size4_4_sram[2]:4 *C 68.045 94.180 +*N mux_tree_tapbuf_size4_4_sram[2]:5 *C 64.445 94.180 +*N mux_tree_tapbuf_size4_4_sram[2]:6 *C 64.400 94.135 +*N mux_tree_tapbuf_size4_4_sram[2]:7 *C 64.400 91.460 +*N mux_tree_tapbuf_size4_4_sram[2]:8 *C 63.418 89.080 +*N mux_tree_tapbuf_size4_4_sram[2]:9 *C 63.895 89.080 +*N mux_tree_tapbuf_size4_4_sram[2]:10 *C 63.940 89.125 +*N mux_tree_tapbuf_size4_4_sram[2]:11 *C 63.940 91.460 +*N mux_tree_tapbuf_size4_4_sram[2]:12 *C 63.940 91.460 +*N mux_tree_tapbuf_size4_4_sram[2]:13 *C 64.245 91.460 + +*CAP +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_12\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_12\/FTB_17__47:A 1e-06 +3 mux_tree_tapbuf_size4_4_sram[2]:3 3.081738e-05 +4 mux_tree_tapbuf_size4_4_sram[2]:4 0.0001921044 +5 mux_tree_tapbuf_size4_4_sram[2]:5 0.000161287 +6 mux_tree_tapbuf_size4_4_sram[2]:6 0.00016619 +7 mux_tree_tapbuf_size4_4_sram[2]:7 0.0001975739 +8 mux_tree_tapbuf_size4_4_sram[2]:8 5.787783e-05 +9 mux_tree_tapbuf_size4_4_sram[2]:9 5.787783e-05 +10 mux_tree_tapbuf_size4_4_sram[2]:10 0.0001435066 +11 mux_tree_tapbuf_size4_4_sram[2]:11 0.0001748904 +12 mux_tree_tapbuf_size4_4_sram[2]:12 4.925315e-05 +13 mux_tree_tapbuf_size4_4_sram[2]:13 4.618685e-05 +14 mux_tree_tapbuf_size4_4_sram[2]:5 chany_top_in[12]:25 0.0001438747 +15 mux_tree_tapbuf_size4_4_sram[2]:4 chany_top_in[12]:26 0.0001438747 + +*RES +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_4_sram[2]:13 0.152 +1 mux_tree_tapbuf_size4_4_sram[2]:5 mux_tree_tapbuf_size4_4_sram[2]:4 0.003214286 +2 mux_tree_tapbuf_size4_4_sram[2]:6 mux_tree_tapbuf_size4_4_sram[2]:5 0.0045 +3 mux_tree_tapbuf_size4_4_sram[2]:3 mem_right_track_12\/FTB_17__47:A 0.152 +4 mux_tree_tapbuf_size4_4_sram[2]:9 mux_tree_tapbuf_size4_4_sram[2]:8 0.0004263393 +5 mux_tree_tapbuf_size4_4_sram[2]:10 mux_tree_tapbuf_size4_4_sram[2]:9 0.0045 +6 mux_tree_tapbuf_size4_4_sram[2]:8 mux_right_track_12\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size4_4_sram[2]:12 mux_tree_tapbuf_size4_4_sram[2]:11 0.0045 +8 mux_tree_tapbuf_size4_4_sram[2]:11 mux_tree_tapbuf_size4_4_sram[2]:10 0.002084821 +9 mux_tree_tapbuf_size4_4_sram[2]:11 mux_tree_tapbuf_size4_4_sram[2]:7 0.0004107143 +10 mux_tree_tapbuf_size4_4_sram[2]:13 mux_tree_tapbuf_size4_4_sram[2]:12 0.0001657609 +11 mux_tree_tapbuf_size4_4_sram[2]:4 mux_tree_tapbuf_size4_4_sram[2]:3 0.0002111487 +12 mux_tree_tapbuf_size4_4_sram[2]:7 mux_tree_tapbuf_size4_4_sram[2]:6 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_3_ccff_tail[0] 0.0006712117 //LENGTH 4.220 LUMPCC 0.0002456348 DR + +*CONN +*I mem_right_track_10\/FTB_16__46:X O *L 0 *C 44.395 86.360 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 46.175 88.060 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 *C 46.175 88.060 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 *C 46.000 88.060 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 *C 46.000 88.015 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 *C 46.000 86.405 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 *C 45.955 86.360 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 *C 44.433 86.360 + +*CAP +0 mem_right_track_10\/FTB_16__46:X 1e-06 +1 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 5.031446e-05 +3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 5.50246e-05 +4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 7.748442e-05 +5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 7.748442e-05 +6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 8.163451e-05 +7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 8.163451e-05 +8 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 chany_bottom_in[14]:13 5.311198e-05 +9 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 chany_bottom_in[14]:14 5.311198e-05 +10 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 optlc_net_184:31 6.970539e-05 +11 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 optlc_net_184:32 6.970539e-05 + +*RES +0 mem_right_track_10\/FTB_16__46:X mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 0.001359375 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[2] 0.001371837 //LENGTH 11.180 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 29.085 75.480 +*I mux_top_track_16\/mux_l3_in_0_:S I *L 0.008363 *C 25.635 72.343 +*I mem_top_track_16\/FTB_9__39:A I *L 0.001746 *C 24.380 77.520 +*N mux_tree_tapbuf_size5_1_sram[2]:3 *C 24.418 77.520 +*N mux_tree_tapbuf_size5_1_sram[2]:4 *C 25.715 77.520 +*N mux_tree_tapbuf_size5_1_sram[2]:5 *C 25.760 77.475 +*N mux_tree_tapbuf_size5_1_sram[2]:6 *C 25.760 72.295 +*N mux_tree_tapbuf_size5_1_sram[2]:7 *C 25.760 72.340 +*N mux_tree_tapbuf_size5_1_sram[2]:8 *C 25.760 75.480 +*N mux_tree_tapbuf_size5_1_sram[2]:9 *C 25.805 75.480 +*N mux_tree_tapbuf_size5_1_sram[2]:10 *C 29.048 75.480 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:S 3.360166e-05 +2 mem_top_track_16\/FTB_9__39:A 1e-06 +3 mux_tree_tapbuf_size5_1_sram[2]:3 8.730083e-05 +4 mux_tree_tapbuf_size5_1_sram[2]:4 8.730083e-05 +5 mux_tree_tapbuf_size5_1_sram[2]:5 0.0001173881 +6 mux_tree_tapbuf_size5_1_sram[2]:6 3.360166e-05 +7 mux_tree_tapbuf_size5_1_sram[2]:7 0.0001785995 +8 mux_tree_tapbuf_size5_1_sram[2]:8 0.0003273556 +9 mux_tree_tapbuf_size5_1_sram[2]:9 0.0002523445 +10 mux_tree_tapbuf_size5_1_sram[2]:10 0.0002523445 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_1_sram[2]:10 0.152 +1 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:9 0.002895089 +2 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:8 0.0045 +3 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:7 0.002803572 +4 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:5 0.00178125 +5 mux_tree_tapbuf_size5_1_sram[2]:4 mux_tree_tapbuf_size5_1_sram[2]:3 0.001158482 +6 mux_tree_tapbuf_size5_1_sram[2]:5 mux_tree_tapbuf_size5_1_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size5_1_sram[2]:3 mem_top_track_16\/FTB_9__39:A 0.152 +8 mux_tree_tapbuf_size5_1_sram[2]:6 mux_top_track_16\/mux_l3_in_0_:S 7.692308e-05 +9 mux_tree_tapbuf_size5_1_sram[2]:7 mux_tree_tapbuf_size5_1_sram[2]:6 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[1] 0.004577769 //LENGTH 34.620 LUMPCC 0.0004428624 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 58.265 55.760 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 60.820 51.000 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 42.495 47.940 +*I mux_bottom_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 62.200 45.560 +*N mux_tree_tapbuf_size5_4_sram[1]:4 *C 62.163 45.560 +*N mux_tree_tapbuf_size5_4_sram[1]:5 *C 60.305 45.560 +*N mux_tree_tapbuf_size5_4_sram[1]:6 *C 60.260 45.605 +*N mux_tree_tapbuf_size5_4_sram[1]:7 *C 42.523 47.963 +*N mux_tree_tapbuf_size5_4_sram[1]:8 *C 42.780 47.975 +*N mux_tree_tapbuf_size5_4_sram[1]:9 *C 42.780 48.280 +*N mux_tree_tapbuf_size5_4_sram[1]:10 *C 60.215 48.280 +*N mux_tree_tapbuf_size5_4_sram[1]:11 *C 60.260 48.280 +*N mux_tree_tapbuf_size5_4_sram[1]:12 *C 60.783 51.000 +*N mux_tree_tapbuf_size5_4_sram[1]:13 *C 60.305 51.000 +*N mux_tree_tapbuf_size5_4_sram[1]:14 *C 60.260 51.000 +*N mux_tree_tapbuf_size5_4_sram[1]:15 *C 60.260 55.715 +*N mux_tree_tapbuf_size5_4_sram[1]:16 *C 60.215 55.760 +*N mux_tree_tapbuf_size5_4_sram[1]:17 *C 58.303 55.760 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_25\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_4_sram[1]:4 0.0001474733 +5 mux_tree_tapbuf_size5_4_sram[1]:5 0.0001474733 +6 mux_tree_tapbuf_size5_4_sram[1]:6 0.0001547016 +7 mux_tree_tapbuf_size5_4_sram[1]:7 3.270663e-05 +8 mux_tree_tapbuf_size5_4_sram[1]:8 5.733672e-05 +9 mux_tree_tapbuf_size5_4_sram[1]:9 0.001039992 +10 mux_tree_tapbuf_size5_4_sram[1]:10 0.001015362 +11 mux_tree_tapbuf_size5_4_sram[1]:11 0.0003454025 +12 mux_tree_tapbuf_size5_4_sram[1]:12 6.985862e-05 +13 mux_tree_tapbuf_size5_4_sram[1]:13 6.985862e-05 +14 mux_tree_tapbuf_size5_4_sram[1]:14 0.0004913374 +15 mux_tree_tapbuf_size5_4_sram[1]:15 0.0003034476 +16 mux_tree_tapbuf_size5_4_sram[1]:16 0.0001279781 +17 mux_tree_tapbuf_size5_4_sram[1]:17 0.0001279781 +18 mux_tree_tapbuf_size5_4_sram[1]:10 chany_top_in[18]:4 0.0002214312 +19 mux_tree_tapbuf_size5_4_sram[1]:9 chany_top_in[18]:5 0.0002214312 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_4_sram[1]:17 0.152 +1 mux_tree_tapbuf_size5_4_sram[1]:5 mux_tree_tapbuf_size5_4_sram[1]:4 0.001658482 +2 mux_tree_tapbuf_size5_4_sram[1]:6 mux_tree_tapbuf_size5_4_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size5_4_sram[1]:4 mux_bottom_track_25\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size5_4_sram[1]:16 mux_tree_tapbuf_size5_4_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size5_4_sram[1]:15 mux_tree_tapbuf_size5_4_sram[1]:14 0.004209822 +6 mux_tree_tapbuf_size5_4_sram[1]:17 mux_tree_tapbuf_size5_4_sram[1]:16 0.001707589 +7 mux_tree_tapbuf_size5_4_sram[1]:10 mux_tree_tapbuf_size5_4_sram[1]:9 0.01556697 +8 mux_tree_tapbuf_size5_4_sram[1]:11 mux_tree_tapbuf_size5_4_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size5_4_sram[1]:11 mux_tree_tapbuf_size5_4_sram[1]:6 0.002388393 +10 mux_tree_tapbuf_size5_4_sram[1]:7 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size5_4_sram[1]:13 mux_tree_tapbuf_size5_4_sram[1]:12 0.0004263393 +12 mux_tree_tapbuf_size5_4_sram[1]:14 mux_tree_tapbuf_size5_4_sram[1]:13 0.0045 +13 mux_tree_tapbuf_size5_4_sram[1]:14 mux_tree_tapbuf_size5_4_sram[1]:11 0.002428571 +14 mux_tree_tapbuf_size5_4_sram[1]:12 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size5_4_sram[1]:8 mux_tree_tapbuf_size5_4_sram[1]:7 0.0001739865 +16 mux_tree_tapbuf_size5_4_sram[1]:9 mux_tree_tapbuf_size5_4_sram[1]:8 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[2] 0.001053078 //LENGTH 7.580 LUMPCC 0.0002537837 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 60.565 64.260 +*I mem_top_track_8\/FTB_3__33:A I *L 0.001746 *C 58.880 66.640 +*I mux_top_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 60.820 68.680 +*N mux_tree_tapbuf_size6_2_sram[2]:3 *C 60.783 68.680 +*N mux_tree_tapbuf_size6_2_sram[2]:4 *C 60.305 68.680 +*N mux_tree_tapbuf_size6_2_sram[2]:5 *C 60.260 68.635 +*N mux_tree_tapbuf_size6_2_sram[2]:6 *C 58.918 66.640 +*N mux_tree_tapbuf_size6_2_sram[2]:7 *C 60.215 66.640 +*N mux_tree_tapbuf_size6_2_sram[2]:8 *C 60.260 66.640 +*N mux_tree_tapbuf_size6_2_sram[2]:9 *C 60.260 64.305 +*N mux_tree_tapbuf_size6_2_sram[2]:10 *C 60.260 64.260 +*N mux_tree_tapbuf_size6_2_sram[2]:11 *C 60.565 64.260 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_8\/FTB_3__33:A 1e-06 +2 mux_top_track_8\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_2_sram[2]:3 6.188479e-05 +4 mux_tree_tapbuf_size6_2_sram[2]:4 6.188479e-05 +5 mux_tree_tapbuf_size6_2_sram[2]:5 7.705177e-05 +6 mux_tree_tapbuf_size6_2_sram[2]:6 9.532295e-05 +7 mux_tree_tapbuf_size6_2_sram[2]:7 9.532295e-05 +8 mux_tree_tapbuf_size6_2_sram[2]:8 0.0001973899 +9 mux_tree_tapbuf_size6_2_sram[2]:9 9.150159e-05 +10 mux_tree_tapbuf_size6_2_sram[2]:10 6.030456e-05 +11 mux_tree_tapbuf_size6_2_sram[2]:11 5.563073e-05 +12 mux_tree_tapbuf_size6_2_sram[2]:9 chanx_right_in[0]:9 6.943575e-05 +13 mux_tree_tapbuf_size6_2_sram[2]:5 chanx_right_in[0]:6 5.745611e-05 +14 mux_tree_tapbuf_size6_2_sram[2]:8 chanx_right_in[0]:6 6.943575e-05 +15 mux_tree_tapbuf_size6_2_sram[2]:8 chanx_right_in[0]:9 5.745611e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_2_sram[2]:11 0.152 +1 mux_tree_tapbuf_size6_2_sram[2]:10 mux_tree_tapbuf_size6_2_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size6_2_sram[2]:9 mux_tree_tapbuf_size6_2_sram[2]:8 0.002084821 +3 mux_tree_tapbuf_size6_2_sram[2]:11 mux_tree_tapbuf_size6_2_sram[2]:10 0.0001657609 +4 mux_tree_tapbuf_size6_2_sram[2]:4 mux_tree_tapbuf_size6_2_sram[2]:3 0.0004263393 +5 mux_tree_tapbuf_size6_2_sram[2]:5 mux_tree_tapbuf_size6_2_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size6_2_sram[2]:3 mux_top_track_8\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size6_2_sram[2]:7 mux_tree_tapbuf_size6_2_sram[2]:6 0.001158482 +8 mux_tree_tapbuf_size6_2_sram[2]:8 mux_tree_tapbuf_size6_2_sram[2]:7 0.0045 +9 mux_tree_tapbuf_size6_2_sram[2]:8 mux_tree_tapbuf_size6_2_sram[2]:5 0.00178125 +10 mux_tree_tapbuf_size6_2_sram[2]:6 mem_top_track_8\/FTB_3__33:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_5_sram[1] 0.00217849 //LENGTH 17.660 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.805 31.620 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 79.020 28.900 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 74.235 37.060 +*I mux_bottom_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 79.680 34.340 +*N mux_tree_tapbuf_size6_5_sram[1]:4 *C 79.680 34.340 +*N mux_tree_tapbuf_size6_5_sram[1]:5 *C 74.273 37.060 +*N mux_tree_tapbuf_size6_5_sram[1]:6 *C 75.395 37.060 +*N mux_tree_tapbuf_size6_5_sram[1]:7 *C 75.440 37.015 +*N mux_tree_tapbuf_size6_5_sram[1]:8 *C 75.440 34.045 +*N mux_tree_tapbuf_size6_5_sram[1]:9 *C 75.485 34.000 +*N mux_tree_tapbuf_size6_5_sram[1]:10 *C 79.580 34.000 +*N mux_tree_tapbuf_size6_5_sram[1]:11 *C 79.580 33.660 +*N mux_tree_tapbuf_size6_5_sram[1]:12 *C 79.580 33.615 +*N mux_tree_tapbuf_size6_5_sram[1]:13 *C 79.058 28.900 +*N mux_tree_tapbuf_size6_5_sram[1]:14 *C 79.535 28.900 +*N mux_tree_tapbuf_size6_5_sram[1]:15 *C 79.580 28.945 +*N mux_tree_tapbuf_size6_5_sram[1]:16 *C 79.580 31.620 +*N mux_tree_tapbuf_size6_5_sram[1]:17 *C 79.625 31.620 +*N mux_tree_tapbuf_size6_5_sram[1]:18 *C 80.767 31.620 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_5\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_5_sram[1]:4 5.213109e-05 +5 mux_tree_tapbuf_size6_5_sram[1]:5 9.543697e-05 +6 mux_tree_tapbuf_size6_5_sram[1]:6 9.543697e-05 +7 mux_tree_tapbuf_size6_5_sram[1]:7 0.000180698 +8 mux_tree_tapbuf_size6_5_sram[1]:8 0.000180698 +9 mux_tree_tapbuf_size6_5_sram[1]:9 0.0002761595 +10 mux_tree_tapbuf_size6_5_sram[1]:10 0.0003245892 +11 mux_tree_tapbuf_size6_5_sram[1]:11 5.734064e-05 +12 mux_tree_tapbuf_size6_5_sram[1]:12 0.0001166349 +13 mux_tree_tapbuf_size6_5_sram[1]:13 6.691687e-05 +14 mux_tree_tapbuf_size6_5_sram[1]:14 6.691687e-05 +15 mux_tree_tapbuf_size6_5_sram[1]:15 0.0001624477 +16 mux_tree_tapbuf_size6_5_sram[1]:16 0.0003118283 +17 mux_tree_tapbuf_size6_5_sram[1]:17 9.362751e-05 +18 mux_tree_tapbuf_size6_5_sram[1]:18 9.362751e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_5_sram[1]:18 0.152 +1 mux_tree_tapbuf_size6_5_sram[1]:13 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_5_sram[1]:14 mux_tree_tapbuf_size6_5_sram[1]:13 0.0004263393 +3 mux_tree_tapbuf_size6_5_sram[1]:15 mux_tree_tapbuf_size6_5_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size6_5_sram[1]:11 mux_tree_tapbuf_size6_5_sram[1]:10 0.0003035715 +5 mux_tree_tapbuf_size6_5_sram[1]:12 mux_tree_tapbuf_size6_5_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size6_5_sram[1]:9 mux_tree_tapbuf_size6_5_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size6_5_sram[1]:8 mux_tree_tapbuf_size6_5_sram[1]:7 0.002651786 +8 mux_tree_tapbuf_size6_5_sram[1]:6 mux_tree_tapbuf_size6_5_sram[1]:5 0.001002232 +9 mux_tree_tapbuf_size6_5_sram[1]:7 mux_tree_tapbuf_size6_5_sram[1]:6 0.0045 +10 mux_tree_tapbuf_size6_5_sram[1]:5 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size6_5_sram[1]:17 mux_tree_tapbuf_size6_5_sram[1]:16 0.0045 +12 mux_tree_tapbuf_size6_5_sram[1]:16 mux_tree_tapbuf_size6_5_sram[1]:15 0.002388393 +13 mux_tree_tapbuf_size6_5_sram[1]:16 mux_tree_tapbuf_size6_5_sram[1]:12 0.00178125 +14 mux_tree_tapbuf_size6_5_sram[1]:18 mux_tree_tapbuf_size6_5_sram[1]:17 0.001020089 +15 mux_tree_tapbuf_size6_5_sram[1]:4 mux_bottom_track_5\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size6_5_sram[1]:10 mux_tree_tapbuf_size6_5_sram[1]:9 0.00365625 +17 mux_tree_tapbuf_size6_5_sram[1]:10 mux_tree_tapbuf_size6_5_sram[1]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_5_ccff_tail[0] 0.0005819775 //LENGTH 3.845 LUMPCC 0.0002028385 DR + +*CONN +*I mem_bottom_track_5\/FTB_6__36:X O *L 0 *C 75.350 40.120 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.065 42.500 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:2 *C 76.065 42.500 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:3 *C 75.900 42.500 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 *C 75.900 42.455 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 *C 75.900 40.165 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 *C 75.855 40.120 +*N mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 *C 75.388 40.120 + +*CAP +0 mem_bottom_track_5\/FTB_6__36:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:2 5.360372e-05 +3 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:3 5.804756e-05 +4 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 9.484968e-05 +5 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 9.484968e-05 +6 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 3.789419e-05 +7 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 3.789419e-05 +8 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 chany_top_in[2]:18 3.182553e-05 +9 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 chany_top_in[2]:19 3.182553e-05 +10 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 chany_top_in[2]:20 6.959371e-05 +11 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 chany_top_in[2]:21 6.959371e-05 + +*RES +0 mem_bottom_track_5\/FTB_6__36:X mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 0.0004174107 +2 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:2 8.967391e-05 +5 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[0] 0.00594789 //LENGTH 44.070 LUMPCC 0.0004527675 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 73.445 107.440 +*I mux_right_track_4\/mux_l1_in_3_:S I *L 0.00357 *C 73.040 105.015 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 68.440 101.710 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 57.215 96.900 +*I mux_right_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 77.380 99.620 +*I mux_right_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 74.160 101.710 +*N mux_tree_tapbuf_size7_1_sram[0]:6 *C 73.040 105.090 +*N mux_tree_tapbuf_size7_1_sram[0]:7 *C 74.198 101.663 +*N mux_tree_tapbuf_size7_1_sram[0]:8 *C 74.520 101.660 +*N mux_tree_tapbuf_size7_1_sram[0]:9 *C 74.520 101.320 +*N mux_tree_tapbuf_size7_1_sram[0]:10 *C 77.343 99.620 +*N mux_tree_tapbuf_size7_1_sram[0]:11 *C 72.680 99.620 +*N mux_tree_tapbuf_size7_1_sram[0]:12 *C 72.680 99.960 +*N mux_tree_tapbuf_size7_1_sram[0]:13 *C 72.680 100.005 +*N mux_tree_tapbuf_size7_1_sram[0]:14 *C 72.680 101.275 +*N mux_tree_tapbuf_size7_1_sram[0]:15 *C 72.680 101.320 +*N mux_tree_tapbuf_size7_1_sram[0]:16 *C 57.253 96.900 +*N mux_tree_tapbuf_size7_1_sram[0]:17 *C 59.295 96.900 +*N mux_tree_tapbuf_size7_1_sram[0]:18 *C 59.340 96.945 +*N mux_tree_tapbuf_size7_1_sram[0]:19 *C 59.340 102.295 +*N mux_tree_tapbuf_size7_1_sram[0]:20 *C 59.385 102.340 +*N mux_tree_tapbuf_size7_1_sram[0]:21 *C 68.080 102.340 +*N mux_tree_tapbuf_size7_1_sram[0]:22 *C 68.080 102.000 +*N mux_tree_tapbuf_size7_1_sram[0]:23 *C 68.383 102.000 +*N mux_tree_tapbuf_size7_1_sram[0]:24 *C 68.440 101.710 +*N mux_tree_tapbuf_size7_1_sram[0]:25 *C 68.440 101.320 +*N mux_tree_tapbuf_size7_1_sram[0]:26 *C 70.380 101.320 +*N mux_tree_tapbuf_size7_1_sram[0]:27 *C 70.380 101.660 +*N mux_tree_tapbuf_size7_1_sram[0]:28 *C 70.380 101.705 +*N mux_tree_tapbuf_size7_1_sram[0]:29 *C 70.380 104.675 +*N mux_tree_tapbuf_size7_1_sram[0]:30 *C 70.425 104.720 +*N mux_tree_tapbuf_size7_1_sram[0]:31 *C 72.983 104.720 +*N mux_tree_tapbuf_size7_1_sram[0]:32 *C 73.040 105.015 +*N mux_tree_tapbuf_size7_1_sram[0]:33 *C 73.140 105.400 +*N mux_tree_tapbuf_size7_1_sram[0]:34 *C 73.140 105.445 +*N mux_tree_tapbuf_size7_1_sram[0]:35 *C 73.140 107.395 +*N mux_tree_tapbuf_size7_1_sram[0]:36 *C 73.140 107.440 +*N mux_tree_tapbuf_size7_1_sram[0]:37 *C 73.445 107.440 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_4\/mux_l1_in_3_:S 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_track_4\/mux_l1_in_2_:S 1e-06 +5 mux_right_track_4\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_1_sram[0]:6 1.480427e-05 +7 mux_tree_tapbuf_size7_1_sram[0]:7 4.559994e-05 +8 mux_tree_tapbuf_size7_1_sram[0]:8 7.462619e-05 +9 mux_tree_tapbuf_size7_1_sram[0]:9 0.0001452969 +10 mux_tree_tapbuf_size7_1_sram[0]:10 0.0002804853 +11 mux_tree_tapbuf_size7_1_sram[0]:11 0.0003115463 +12 mux_tree_tapbuf_size7_1_sram[0]:12 6.787662e-05 +13 mux_tree_tapbuf_size7_1_sram[0]:13 6.641779e-05 +14 mux_tree_tapbuf_size7_1_sram[0]:14 6.641779e-05 +15 mux_tree_tapbuf_size7_1_sram[0]:15 0.0003097336 +16 mux_tree_tapbuf_size7_1_sram[0]:16 0.0001461048 +17 mux_tree_tapbuf_size7_1_sram[0]:17 0.0001461048 +18 mux_tree_tapbuf_size7_1_sram[0]:18 0.0003060802 +19 mux_tree_tapbuf_size7_1_sram[0]:19 0.0003060802 +20 mux_tree_tapbuf_size7_1_sram[0]:20 0.0005696826 +21 mux_tree_tapbuf_size7_1_sram[0]:21 0.0005928389 +22 mux_tree_tapbuf_size7_1_sram[0]:22 5.103898e-05 +23 mux_tree_tapbuf_size7_1_sram[0]:23 5.596288e-05 +24 mux_tree_tapbuf_size7_1_sram[0]:24 8.597344e-05 +25 mux_tree_tapbuf_size7_1_sram[0]:25 0.0001742582 +26 mux_tree_tapbuf_size7_1_sram[0]:26 0.0003286291 +27 mux_tree_tapbuf_size7_1_sram[0]:27 5.742911e-05 +28 mux_tree_tapbuf_size7_1_sram[0]:28 0.0001881644 +29 mux_tree_tapbuf_size7_1_sram[0]:29 0.0001881644 +30 mux_tree_tapbuf_size7_1_sram[0]:30 0.0001756523 +31 mux_tree_tapbuf_size7_1_sram[0]:31 0.0001979335 +32 mux_tree_tapbuf_size7_1_sram[0]:32 9.056184e-05 +33 mux_tree_tapbuf_size7_1_sram[0]:33 5.822209e-05 +34 mux_tree_tapbuf_size7_1_sram[0]:34 0.0001412886 +35 mux_tree_tapbuf_size7_1_sram[0]:35 0.0001412886 +36 mux_tree_tapbuf_size7_1_sram[0]:36 5.394885e-05 +37 mux_tree_tapbuf_size7_1_sram[0]:37 5.091001e-05 +38 mux_tree_tapbuf_size7_1_sram[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.344841e-05 +39 mux_tree_tapbuf_size7_1_sram[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.046886e-05 +40 mux_tree_tapbuf_size7_1_sram[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.627012e-05 +41 mux_tree_tapbuf_size7_1_sram[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.344841e-05 +42 mux_tree_tapbuf_size7_1_sram[0]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.230659e-07 +43 mux_tree_tapbuf_size7_1_sram[0]:28 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.230659e-07 +44 mux_tree_tapbuf_size7_1_sram[0]:26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.627012e-05 +45 mux_tree_tapbuf_size7_1_sram[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.046886e-05 +46 mux_tree_tapbuf_size7_1_sram[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001458733 +47 mux_tree_tapbuf_size7_1_sram[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001458733 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_1_sram[0]:37 0.152 +1 mux_tree_tapbuf_size7_1_sram[0]:10 mux_right_track_4\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:11 0.0003035715 +3 mux_tree_tapbuf_size7_1_sram[0]:13 mux_tree_tapbuf_size7_1_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:9 0.001642857 +6 mux_tree_tapbuf_size7_1_sram[0]:14 mux_tree_tapbuf_size7_1_sram[0]:13 0.001133929 +7 mux_tree_tapbuf_size7_1_sram[0]:24 mux_right_track_4\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_1_sram[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 0.0001686047 +9 mux_tree_tapbuf_size7_1_sram[0]:32 mux_right_track_4\/mux_l1_in_3_:S 0.152 +10 mux_tree_tapbuf_size7_1_sram[0]:32 mux_tree_tapbuf_size7_1_sram[0]:31 0.0001715116 +11 mux_tree_tapbuf_size7_1_sram[0]:32 mux_tree_tapbuf_size7_1_sram[0]:6 4.360465e-05 +12 mux_tree_tapbuf_size7_1_sram[0]:33 mux_tree_tapbuf_size7_1_sram[0]:32 0.00034375 +13 mux_tree_tapbuf_size7_1_sram[0]:34 mux_tree_tapbuf_size7_1_sram[0]:33 0.0045 +14 mux_tree_tapbuf_size7_1_sram[0]:36 mux_tree_tapbuf_size7_1_sram[0]:35 0.0045 +15 mux_tree_tapbuf_size7_1_sram[0]:35 mux_tree_tapbuf_size7_1_sram[0]:34 0.001741072 +16 mux_tree_tapbuf_size7_1_sram[0]:37 mux_tree_tapbuf_size7_1_sram[0]:36 0.0001657609 +17 mux_tree_tapbuf_size7_1_sram[0]:30 mux_tree_tapbuf_size7_1_sram[0]:29 0.0045 +18 mux_tree_tapbuf_size7_1_sram[0]:29 mux_tree_tapbuf_size7_1_sram[0]:28 0.002651786 +19 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:26 0.0003035715 +20 mux_tree_tapbuf_size7_1_sram[0]:28 mux_tree_tapbuf_size7_1_sram[0]:27 0.0045 +21 mux_tree_tapbuf_size7_1_sram[0]:7 mux_right_track_4\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_1_sram[0]:16 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +23 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size7_1_sram[0]:16 0.001823661 +24 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size7_1_sram[0]:17 0.0045 +25 mux_tree_tapbuf_size7_1_sram[0]:20 mux_tree_tapbuf_size7_1_sram[0]:19 0.0045 +26 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:18 0.004776786 +27 mux_tree_tapbuf_size7_1_sram[0]:21 mux_tree_tapbuf_size7_1_sram[0]:20 0.007763394 +28 mux_tree_tapbuf_size7_1_sram[0]:22 mux_tree_tapbuf_size7_1_sram[0]:21 0.0003035715 +29 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:22 0.0002700893 +30 mux_tree_tapbuf_size7_1_sram[0]:25 mux_tree_tapbuf_size7_1_sram[0]:24 0.0003482143 +31 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:25 0.001732143 +32 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:15 0.002053571 +33 mux_tree_tapbuf_size7_1_sram[0]:9 mux_tree_tapbuf_size7_1_sram[0]:8 0.0003035715 +34 mux_tree_tapbuf_size7_1_sram[0]:31 mux_tree_tapbuf_size7_1_sram[0]:30 0.002283482 +35 mux_tree_tapbuf_size7_1_sram[0]:11 mux_tree_tapbuf_size7_1_sram[0]:10 0.004162947 +36 mux_tree_tapbuf_size7_1_sram[0]:8 mux_tree_tapbuf_size7_1_sram[0]:7 0.0002879465 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001202959 //LENGTH 8.720 LUMPCC 0.0003309241 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_1_:X O *L 0 *C 68.715 56.440 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 68.830 64.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 68.830 64.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 69.000 64.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 69.000 64.215 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 69.000 56.485 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 69.000 56.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 68.715 56.440 + +*CAP +0 mux_top_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.858078e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.143448e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000316045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000316045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.76239e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.030631e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_2_sram[0]:8 3.593932e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_2_sram[0]:13 4.40982e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_2_sram[0]:15 3.299482e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_2_sram[0]:10 4.40982e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_2_sram[0]:14 3.299482e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_2_sram[0]:15 3.593932e-05 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.242972e-05 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.242972e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001290264 //LENGTH 9.575 LUMPCC 0.0003045022 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_2_:X O *L 0 *C 84.005 93.160 +*I mux_right_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 90.160 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 90.160 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 90.160 91.120 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 87.905 91.120 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 87.860 91.165 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 87.860 93.115 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 87.815 93.160 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 84.043 93.160 + +*CAP +0 mux_right_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.760785e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001329672 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001047556 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001295026 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001295026 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002147127 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002147127 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 right_top_grid_pin_48_[0]:23 6.446099e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 right_top_grid_pin_48_[0]:24 6.446099e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_3_sram[1]:6 7.785729e-08 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_3_sram[1]:12 2.20436e-06 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_3_sram[1]:9 7.950755e-05 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_3_sram[1]:11 6.000363e-06 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_3_sram[1]:8 7.785729e-08 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_3_sram[1]:11 2.20436e-06 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_3_sram[1]:8 6.000363e-06 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_3_sram[1]:10 7.950755e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.003368304 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001741072 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002013393 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_0\/mux_l2_in_1_:A1 0.152 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00268209 //LENGTH 21.040 LUMPCC 0.0005131338 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_1_:X O *L 0 *C 87.575 37.400 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 77.915 28.220 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 77.877 28.220 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 77.325 28.220 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 77.280 28.265 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 77.280 37.355 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 77.325 37.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 87.538 37.400 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.284604e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.284604e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003888378 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003888379 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006217941 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006217941 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_5_sram[2]:5 4.007138e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_5_sram[2]:6 6.622839e-06 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size6_5_sram[2]:7 7.44213e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_5_sram[2]:4 6.622839e-06 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_5_sram[2]:6 4.007138e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size6_5_sram[2]:8 7.44213e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001354514 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001354514 + +*RES +0 mux_bottom_track_5\/mux_l1_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.008116072 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.009118304 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.006780297 //LENGTH 58.000 LUMPCC 0.0009672298 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_0_:X O *L 0 *C 91.715 36.040 +*I mux_bottom_track_9\/BUFT_P_143:A I *L 0.001746 *C 64.860 6.800 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 64.860 6.800 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 64.860 6.845 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 64.860 12.535 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 64.905 12.580 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 73.095 12.580 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 73.140 12.625 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 73.140 29.195 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 73.185 29.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 91.035 29.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 91.080 29.285 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 91.080 35.995 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 91.125 36.040 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 91.678 36.040 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_9\/BUFT_P_143:A 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.748458e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003020034 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003020034 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000463506 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000463506 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0007167009 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0007167009 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0009477107 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0009477107 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0003888507 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0003888507 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:13 6.801935e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:14 6.801935e-05 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 chany_bottom_in[1]:9 0.0001753172 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_bottom_in[1]:10 0.0001753172 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_out[2]:6 0.0001375682 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_out[2]:5 0.0001375682 +19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_out[2]:2 1.481876e-05 +20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_bottom_out[2] 1.481876e-05 +21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001559108 +22 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001559108 + +*RES +0 mux_bottom_track_9\/mux_l3_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0004933036 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.005991071 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0159375 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0045 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0045 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.01479464 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0073125 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.005080357 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_9\/BUFT_P_143:A 0.152 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001832637 //LENGTH 15.280 LUMPCC 0.0006517816 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_0_:X O *L 0 *C 67.335 36.040 +*I mux_bottom_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 61.085 28.900 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 61.123 28.900 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 62.100 28.900 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 62.100 28.560 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 66.195 28.560 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 66.240 28.605 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 66.240 35.995 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 66.285 36.040 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 67.297 36.040 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.648593e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.236641e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001799224 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001540419 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002729198 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002729198 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001000998 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001000998 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[6]:11 9.273899e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[6]:12 9.273899e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[13]:15 6.941746e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[13]:16 6.941746e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[14]:9 7.431906e-06 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[14]:10 6.703282e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[14]:10 7.431906e-06 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[14]:9 6.703282e-05 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_2_sram[2]:6 4.465023e-05 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_2_sram[2]:5 2.137736e-05 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_2_sram[2]:7 2.3242e-05 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_2_sram[2]:7 4.465023e-05 +22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_2_sram[2]:6 2.3242e-05 +23 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_2_sram[2]:8 2.137736e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00365625 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.006598215 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0009040179 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008727679 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006811429 //LENGTH 6.470 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_1_:X O *L 0 *C 26.395 88.060 +*I mux_top_track_24\/mux_l3_in_0_:A0 I *L 0.005103 *C 22.080 86.530 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 22.080 86.530 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.080 86.575 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 22.080 88.015 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 22.125 88.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 26.358 88.060 + +*CAP +0 mux_top_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.880744e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.163755e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.163755e-05 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002435302 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002435302 + +*RES +0 mux_top_track_24\/mux_l2_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.003779018 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001285714 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A0 0.152 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008483914 //LENGTH 6.880 LUMPCC 0.000189948 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_1_:X O *L 0 *C 36.165 101.660 +*I mux_right_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 39.735 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.698 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.145 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 39.100 103.995 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.100 101.705 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.055 101.660 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 36.203 101.660 + +*CAP +0 mux_right_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.972003e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.972003e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001356912 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001356912 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001328106 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001328106 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[8]:19 9.51013e-06 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[8]:18 8.546388e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[8]:20 9.51013e-06 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[8]:17 8.546388e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004933036 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002546875 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004697655 //LENGTH 4.320 LUMPCC 0 DR + +*CONN +*I mux_right_track_12\/mux_l2_in_1_:X O *L 0 *C 58.245 88.060 +*I mux_right_track_12\/mux_l3_in_0_:A0 I *L 0.001631 *C 62.275 88.060 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 62.238 88.060 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 58.283 88.060 + +*CAP +0 mux_right_track_12\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_12\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002338827 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002338827 + +*RES +0 mux_right_track_12\/mux_l2_in_1_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_12\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.00353125 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007928829 //LENGTH 6.110 LUMPCC 0.0001246624 DR + +*CONN +*I mux_right_track_14\/mux_l2_in_1_:X O *L 0 *C 81.245 83.300 +*I mux_right_track_14\/mux_l3_in_0_:A0 I *L 0.001631 *C 83.895 86.020 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 83.858 86.020 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 81.465 86.020 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 81.420 85.975 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 81.420 83.345 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 81.420 83.300 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 81.245 83.300 + +*CAP +0 mux_right_track_14\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_14\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001361 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001361 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001431268 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001431268 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.428362e-05 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.348323e-05 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.628689e-05 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.628689e-05 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.604432e-05 +11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.604432e-05 + +*RES +0 mux_right_track_14\/mux_l2_in_1_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_14\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002136161 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00122601 //LENGTH 9.755 LUMPCC 0.0001915897 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_0_:X O *L 0 *C 75.265 120.360 +*I mux_right_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 76.460 112.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 76.422 112.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 75.485 112.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 75.440 112.585 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 75.440 120.315 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 75.440 120.360 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 75.265 120.360 + +*CAP +0 mux_right_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.442246e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.442246e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003711637 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003711637 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.119526e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.005227e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[12]:33 9.579487e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[12]:34 9.579487e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008370536 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.006901786 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009713164 //LENGTH 7.490 LUMPCC 0.0001713533 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_1_:X O *L 0 *C 71.015 95.880 +*I mux_right_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 66.875 98.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 66.875 98.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 67.160 98.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 67.160 98.555 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 67.160 95.925 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 67.205 95.880 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 70.978 95.880 + +*CAP +0 mux_right_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.879921e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.479986e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000156085 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000156085 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001910971 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001910971 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_1_sram[1]:6 1.438549e-06 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_1_sram[1]:9 7.911576e-08 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_1_sram[1]:12 3.199945e-07 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:8 8.485991e-06 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:11 1.295331e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:22 6.239967e-05 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_1_sram[1]:10 7.911576e-08 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_1_sram[1]:11 3.199945e-07 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_1_sram[1]:12 1.438549e-06 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:7 8.485991e-06 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:10 1.295331e-05 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:13 6.239967e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001548913 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.003368304 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003134436 //LENGTH 28.050 LUMPCC 0.000357772 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_0_:X O *L 0 *C 93.665 76.840 +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.840 58.675 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 102.803 58.770 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 95.265 58.820 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 95.220 58.865 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 95.220 76.795 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 95.175 76.840 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 93.703 76.840 + +*CAP +0 mux_right_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004298708 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004298708 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0008267727 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0008267727 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001306886 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001306886 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:6 2.466287e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:11 3.834743e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:12 2.793213e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:9 3.834743e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:11 2.793213e-05 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:12 2.466287e-05 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 8.794357e-05 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 8.794357e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01600893 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.006729911 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0] 0.006344147 //LENGTH 49.380 LUMPCC 0.001662372 DR + +*CONN +*I mux_right_track_22\/mux_l2_in_0_:X O *L 0 *C 61.925 77.860 +*I mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 104.650 80.410 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 104.613 80.303 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 94.805 80.240 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 94.760 80.285 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 94.760 81.543 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 94.752 81.600 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 63.028 81.600 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 63.020 81.543 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 63.020 77.905 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 62.975 77.860 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 61.963 77.860 + +*CAP +0 mux_right_track_22\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005359469 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0005359469 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.763245e-05 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.763245e-05 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001384946 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001384946 +8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002275875 +9 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0002275875 +10 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001037749 +11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001037749 +12 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[13]:34 0.0003083023 +13 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[13]:35 0.0001405179 +14 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[13]:33 0.0003083023 +15 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[13]:34 0.0001405179 +16 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:184 0.0001152855 +17 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:214 5.57902e-05 +18 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:215 4.551098e-05 +19 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:233 6.000478e-06 +20 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:183 0.0001152855 +21 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:209 5.57902e-05 +22 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:214 4.551098e-05 +23 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:234 6.000478e-06 +24 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[14]:11 0.0001541656 +25 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[14]:12 0.0001541656 +26 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[14]:11 5.61312e-06 +27 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[14]:12 5.61312e-06 + +*RES +0 mux_right_track_22\/mux_l2_in_0_:X mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0009040178 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.003247768 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.004970249 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001122768 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.008756697 +9 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +10 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chany_bottom_out[18] 0.0005452074 //LENGTH 3.775 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 24.380 4.080 +*P chany_bottom_out[18] O *L 0.7423 *C 23.920 1.285 +*N chany_bottom_out[18]:2 *C 23.920 4.072 +*N chany_bottom_out[18]:3 *C 23.935 4.080 +*N chany_bottom_out[18]:4 *C 24.378 4.080 +*N chany_bottom_out[18]:5 *C 24.380 4.080 +*N chany_bottom_out[18]:6 *C 24.380 4.080 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 chany_bottom_out[18] 0.0001784199 +2 chany_bottom_out[18]:2 0.0001784199 +3 chany_bottom_out[18]:3 5.855882e-05 +4 chany_bottom_out[18]:4 5.855882e-05 +5 chany_bottom_out[18]:5 3.587058e-05 +6 chany_bottom_out[18]:6 3.437935e-05 + +*RES +0 ropt_mt_inst_823:X chany_bottom_out[18]:6 0.152 +1 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.0045 +2 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.00341 +3 chany_bottom_out[18]:4 chany_bottom_out[18]:3 6.499219e-05 +4 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.00341 +5 chany_bottom_out[18]:2 chany_bottom_out[18] 0.0004367083 + +*END + +*D_NET ropt_net_233 0.001053653 //LENGTH 7.095 LUMPCC 0.0003794715 DR + +*CONN +*I ropt_mt_inst_832:X O *L 0 *C 110.135 64.600 +*I ropt_mt_inst_853:A I *L 0.001767 *C 106.260 66.640 +*N ropt_net_233:2 *C 106.297 66.640 +*N ropt_net_233:3 *C 110.355 66.640 +*N ropt_net_233:4 *C 110.400 66.595 +*N ropt_net_233:5 *C 110.400 64.645 +*N ropt_net_233:6 *C 110.400 64.600 +*N ropt_net_233:7 *C 110.135 64.600 + +*CAP +0 ropt_mt_inst_832:X 1e-06 +1 ropt_mt_inst_853:A 1e-06 +2 ropt_net_233:2 0.0001697219 +3 ropt_net_233:3 0.0001697219 +4 ropt_net_233:4 0.0001074369 +5 ropt_net_233:5 0.0001074369 +6 ropt_net_233:6 5.593472e-05 +7 ropt_net_233:7 6.192915e-05 +8 ropt_net_233:2 chanx_right_out[9]:6 0.000142834 +9 ropt_net_233:3 chanx_right_out[9]:5 0.000142834 +10 ropt_net_233:2 ropt_net_211:5 2.928947e-05 +11 ropt_net_233:3 ropt_net_211:6 2.928947e-05 +12 ropt_net_233:4 ropt_net_211:5 9.705707e-07 +13 ropt_net_233:4 ropt_net_211:6 1.664172e-05 +14 ropt_net_233:5 ropt_net_211:7 1.664172e-05 +15 ropt_net_233:5 ropt_net_211:4 9.705707e-07 + +*RES +0 ropt_mt_inst_832:X ropt_net_233:7 0.152 +1 ropt_net_233:2 ropt_mt_inst_853:A 0.152 +2 ropt_net_233:3 ropt_net_233:2 0.003622768 +3 ropt_net_233:4 ropt_net_233:3 0.0045 +4 ropt_net_233:6 ropt_net_233:5 0.0045 +5 ropt_net_233:5 ropt_net_233:4 0.001741072 +6 ropt_net_233:7 ropt_net_233:6 0.0001440218 + +*END + +*D_NET chany_bottom_out[9] 0.001089406 //LENGTH 8.710 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_843:X O *L 0 *C 29.175 6.120 +*P chany_bottom_out[9] O *L 0.7423 *C 25.760 1.290 +*N chany_bottom_out[9]:2 *C 25.760 6.075 +*N chany_bottom_out[9]:3 *C 25.805 6.120 +*N chany_bottom_out[9]:4 *C 29.138 6.120 + +*CAP +0 ropt_mt_inst_843:X 1e-06 +1 chany_bottom_out[9] 0.0003006695 +2 chany_bottom_out[9]:2 0.0003006695 +3 chany_bottom_out[9]:3 0.0002435335 +4 chany_bottom_out[9]:4 0.0002435335 + +*RES +0 ropt_mt_inst_843:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.002975447 +2 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +3 chany_bottom_out[9]:2 chany_bottom_out[9] 0.004272321 + +*END + +*D_NET chanx_right_out[16] 0.0008055256 //LENGTH 6.585 LUMPCC 9.135189e-05 DR + +*CONN +*I ropt_mt_inst_850:X O *L 0 *C 107.180 41.820 +*P chanx_right_out[16] O *L 0.7423 *C 111.930 40.800 +*N chanx_right_out[16]:2 *C 111.328 40.800 +*N chanx_right_out[16]:3 *C 111.320 40.858 +*N chanx_right_out[16]:4 *C 111.320 41.775 +*N chanx_right_out[16]:5 *C 111.275 41.820 +*N chanx_right_out[16]:6 *C 107.218 41.820 + +*CAP +0 ropt_mt_inst_850:X 1e-06 +1 chanx_right_out[16] 6.900921e-05 +2 chanx_right_out[16]:2 6.900921e-05 +3 chanx_right_out[16]:3 7.035797e-05 +4 chanx_right_out[16]:4 7.035797e-05 +5 chanx_right_out[16]:5 0.0002172196 +6 chanx_right_out[16]:6 0.0002172196 +7 chanx_right_out[16]:6 ropt_net_230:2 4.567594e-05 +8 chanx_right_out[16]:5 ropt_net_230:3 4.567594e-05 + +*RES +0 ropt_mt_inst_850:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:6 chanx_right_out[16]:5 0.003622768 +2 chanx_right_out[16]:5 chanx_right_out[16]:4 0.0045 +3 chanx_right_out[16]:4 chanx_right_out[16]:3 0.0008191965 +4 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +5 chanx_right_out[16]:2 chanx_right_out[16] 9.439165e-05 + +*END + +*D_NET chanx_right_out[14] 0.0004531687 //LENGTH 1.910 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_859:X O *L 0 *C 110.140 47.600 +*P chanx_right_out[14] O *L 0.7423 *C 112.700 47.600 +*N chanx_right_out[14]:2 *C 110.407 47.600 +*N chanx_right_out[14]:3 *C 110.400 47.600 +*N chanx_right_out[14]:4 *C 110.400 47.600 +*N chanx_right_out[14]:5 *C 110.140 47.600 + +*CAP +0 ropt_mt_inst_859:X 1e-06 +1 chanx_right_out[14] 0.0001524675 +2 chanx_right_out[14]:2 0.0001524675 +3 chanx_right_out[14]:3 3.737727e-05 +4 chanx_right_out[14]:4 5.17554e-05 +5 chanx_right_out[14]:5 5.81011e-05 + +*RES +0 ropt_mt_inst_859:X chanx_right_out[14]:5 0.152 +1 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +2 chanx_right_out[14]:2 chanx_right_out[14] 0.000226775 +3 chanx_right_out[14]:4 chanx_right_out[14]:3 0.0045 +4 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0001413044 + +*END + +*D_NET BUF_net_89 0.002458673 //LENGTH 22.650 LUMPCC 0 DR + +*CONN +*I BUFT_RR_89:X O *L 0 *C 22.540 114.920 +*I BUFT_P_162:A I *L 0.001766 *C 13.340 123.760 +*N BUF_net_89:2 *C 13.303 123.760 +*N BUF_net_89:3 *C 11.545 123.760 +*N BUF_net_89:4 *C 11.500 123.715 +*N BUF_net_89:5 *C 11.500 114.965 +*N BUF_net_89:6 *C 11.545 114.920 +*N BUF_net_89:7 *C 22.503 114.920 + +*CAP +0 BUFT_RR_89:X 1e-06 +1 BUFT_P_162:A 1e-06 +2 BUF_net_89:2 0.0001224993 +3 BUF_net_89:3 0.0001224993 +4 BUF_net_89:4 0.0004584463 +5 BUF_net_89:5 0.0004584463 +6 BUF_net_89:6 0.0006473911 +7 BUF_net_89:7 0.0006473911 + +*RES +0 BUFT_RR_89:X BUF_net_89:7 0.152 +1 BUF_net_89:2 BUFT_P_162:A 0.152 +2 BUF_net_89:3 BUF_net_89:2 0.001569197 +3 BUF_net_89:4 BUF_net_89:3 0.0045 +4 BUF_net_89:6 BUF_net_89:5 0.0045 +5 BUF_net_89:5 BUF_net_89:4 0.0078125 +6 BUF_net_89:7 BUF_net_89:6 0.009783483 + +*END + +*D_NET ropt_net_215 0.002488473 //LENGTH 17.505 LUMPCC 0.0009963427 DR + +*CONN +*I BUFT_P_136:X O *L 0 *C 45.080 14.280 +*I ropt_mt_inst_836:A I *L 0.001766 *C 51.060 4.080 +*N ropt_net_215:2 *C 51.023 4.080 +*N ropt_net_215:3 *C 48.345 4.080 +*N ropt_net_215:4 *C 48.300 4.125 +*N ropt_net_215:5 *C 48.300 12.863 +*N ropt_net_215:6 *C 48.293 12.920 +*N ropt_net_215:7 *C 45.088 12.920 +*N ropt_net_215:8 *C 45.080 12.978 +*N ropt_net_215:9 *C 45.080 14.235 +*N ropt_net_215:10 *C 45.080 14.280 + +*CAP +0 BUFT_P_136:X 1e-06 +1 ropt_mt_inst_836:A 1e-06 +2 ropt_net_215:2 6.690734e-05 +3 ropt_net_215:3 6.690734e-05 +4 ropt_net_215:4 0.000368034 +5 ropt_net_215:5 0.000368034 +6 ropt_net_215:6 0.0001831335 +7 ropt_net_215:7 0.0001831335 +8 ropt_net_215:8 0.0001093384 +9 ropt_net_215:9 0.0001093384 +10 ropt_net_215:10 3.530334e-05 +11 ropt_net_215:7 chany_bottom_in[3]:13 7.038557e-05 +12 ropt_net_215:6 chany_bottom_in[3]:12 7.038557e-05 +13 ropt_net_215:5 ropt_net_231:4 6.186829e-05 +14 ropt_net_215:3 ropt_net_231:6 9.391311e-05 +15 ropt_net_215:4 ropt_net_231:5 6.186829e-05 +16 ropt_net_215:2 ropt_net_231:7 9.391311e-05 +17 ropt_net_215:3 chany_bottom_out[17]:4 8.388528e-05 +18 ropt_net_215:2 chany_bottom_out[17]:5 8.388528e-05 +19 ropt_net_215:5 chany_bottom_out[15]:6 0.0001881192 +20 ropt_net_215:4 chany_bottom_out[15]:5 0.0001881192 + +*RES +0 BUFT_P_136:X ropt_net_215:10 0.152 +1 ropt_net_215:10 ropt_net_215:9 0.0045 +2 ropt_net_215:9 ropt_net_215:8 0.001122768 +3 ropt_net_215:8 ropt_net_215:7 0.00341 +4 ropt_net_215:7 ropt_net_215:6 0.0005021166 +5 ropt_net_215:5 ropt_net_215:4 0.00780134 +6 ropt_net_215:6 ropt_net_215:5 0.00341 +7 ropt_net_215:3 ropt_net_215:2 0.002390625 +8 ropt_net_215:4 ropt_net_215:3 0.0045 +9 ropt_net_215:2 ropt_mt_inst_836:A 0.152 + +*END + +*D_NET chany_top_in[2] 0.02116298 //LENGTH 173.005 LUMPCC 0.00494008 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 70.380 129.270 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 78.760 96.220 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 51.885 36.380 +*I ropt_mt_inst_819:A I *L 0.001767 *C 40.940 9.520 +*N chany_top_in[2]:4 *C 75.650 43.520 +*N chany_top_in[2]:5 *C 40.977 9.520 +*N chany_top_in[2]:6 *C 45.080 9.520 +*N chany_top_in[2]:7 *C 45.080 9.860 +*N chany_top_in[2]:8 *C 52.395 9.860 +*N chany_top_in[2]:9 *C 52.440 9.905 +*N chany_top_in[2]:10 *C 52.477 17.623 +*N chany_top_in[2]:11 *C 52.593 17.680 +*N chany_top_in[2]:12 *C 54.733 17.680 +*N chany_top_in[2]:13 *C 54.740 17.738 +*N chany_top_in[2]:14 *C 51.922 36.380 +*N chany_top_in[2]:15 *C 54.695 36.380 +*N chany_top_in[2]:16 *C 54.740 36.380 +*N chany_top_in[2]:17 *C 54.740 39.735 +*N chany_top_in[2]:18 *C 54.785 39.780 +*N chany_top_in[2]:19 *C 76.315 39.780 +*N chany_top_in[2]:20 *C 76.360 39.825 +*N chany_top_in[2]:21 *C 76.360 43.462 +*N chany_top_in[2]:22 *C 76.358 43.520 +*N chany_top_in[2]:23 *C 76.360 43.528 +*N chany_top_in[2]:24 *C 76.360 94.513 +*N chany_top_in[2]:25 *C 76.380 94.520 +*N chany_top_in[2]:26 *C 77.733 94.520 +*N chany_top_in[2]:27 *C 77.740 94.578 +*N chany_top_in[2]:28 *C 78.723 96.220 +*N chany_top_in[2]:29 *C 77.785 96.220 +*N chany_top_in[2]:30 *C 77.740 96.220 +*N chany_top_in[2]:31 *C 77.740 109.422 +*N chany_top_in[2]:32 *C 77.733 109.480 +*N chany_top_in[2]:33 *C 70.388 109.480 +*N chany_top_in[2]:34 *C 70.380 109.538 + +*CAP +0 chany_top_in[2] 0.0008054539 +1 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +3 ropt_mt_inst_819:A 1e-06 +4 chany_top_in[2]:4 0.0001300715 +5 chany_top_in[2]:5 0.0002112342 +6 chany_top_in[2]:6 0.0002330853 +7 chany_top_in[2]:7 0.0004911778 +8 chany_top_in[2]:8 0.0004693267 +9 chany_top_in[2]:9 0.0004468297 +10 chany_top_in[2]:10 0.0004468297 +11 chany_top_in[2]:11 0.0001593348 +12 chany_top_in[2]:12 0.0001593348 +13 chany_top_in[2]:13 0.0009602784 +14 chany_top_in[2]:14 0.0001904413 +15 chany_top_in[2]:15 0.0001904413 +16 chany_top_in[2]:16 0.001166473 +17 chany_top_in[2]:17 0.0001783915 +18 chany_top_in[2]:18 0.001225319 +19 chany_top_in[2]:19 0.001225319 +20 chany_top_in[2]:20 0.0001703375 +21 chany_top_in[2]:21 0.0001703375 +22 chany_top_in[2]:22 0.0001300715 +23 chany_top_in[2]:23 0.001572106 +24 chany_top_in[2]:24 0.001572106 +25 chany_top_in[2]:25 0.0001005941 +26 chany_top_in[2]:26 0.0001005941 +27 chany_top_in[2]:27 0.000100589 +28 chany_top_in[2]:28 9.060447e-05 +29 chany_top_in[2]:29 9.060447e-05 +30 chany_top_in[2]:30 0.0008602504 +31 chany_top_in[2]:31 0.0007279912 +32 chany_top_in[2]:32 0.0005194571 +33 chany_top_in[2]:33 0.0005194571 +34 chany_top_in[2]:34 0.0008054539 +35 chany_top_in[2]:23 chany_top_in[14]:22 0.0001596654 +36 chany_top_in[2]:23 chany_top_in[14]:15 0.0008281374 +37 chany_top_in[2]:24 chany_top_in[14]:23 0.0001596654 +38 chany_top_in[2]:24 chany_top_in[14]:22 0.0008281374 +39 chany_top_in[2] chany_bottom_in[2]:7 8.06114e-05 +40 chany_top_in[2]:34 chany_bottom_in[2]:8 8.06114e-05 +41 chany_top_in[2]:23 chany_bottom_in[2]:32 8.453055e-05 +42 chany_top_in[2]:23 chany_bottom_in[2]:31 6.412462e-05 +43 chany_top_in[2]:25 chany_bottom_in[2]:13 2.359173e-05 +44 chany_top_in[2]:24 chany_bottom_in[2]:30 6.412462e-05 +45 chany_top_in[2]:24 chany_bottom_in[2]:31 8.453055e-05 +46 chany_top_in[2]:26 chany_bottom_in[2]:14 2.359173e-05 +47 chany_top_in[2] prog_clk[0]:257 0.0001510145 +48 chany_top_in[2] prog_clk[0]:254 0.0002200831 +49 chany_top_in[2]:32 prog_clk[0]:259 8.38855e-06 +50 chany_top_in[2]:34 prog_clk[0]:258 0.0001510145 +51 chany_top_in[2]:34 prog_clk[0]:257 0.0002200831 +52 chany_top_in[2]:33 prog_clk[0]:263 8.38855e-06 +53 chany_top_in[2]:20 prog_clk[0]:153 4.713786e-07 +54 chany_top_in[2]:21 prog_clk[0]:159 4.713786e-07 +55 chany_top_in[2]:22 prog_clk[0]:161 1.488148e-06 +56 chany_top_in[2]:4 prog_clk[0]:146 1.488148e-06 +57 chany_top_in[2]:18 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:7 3.182553e-05 +58 chany_top_in[2]:19 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:6 3.182553e-05 +59 chany_top_in[2]:20 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:5 6.959371e-05 +60 chany_top_in[2]:21 mux_tree_tapbuf_size6_mem_5_ccff_tail[0]:4 6.959371e-05 +61 chany_top_in[2]:31 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.242409e-06 +62 chany_top_in[2]:30 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 5.242409e-06 +63 chany_top_in[2]:23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0006206616 +64 chany_top_in[2]:24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0006206616 +65 chany_top_in[2]:8 ropt_net_242:3 6.30286e-06 +66 chany_top_in[2]:5 ropt_net_242:4 0.0001094517 +67 chany_top_in[2]:6 ropt_net_242:3 0.0001143067 +68 chany_top_in[2]:7 ropt_net_242:2 4.855065e-06 +69 chany_top_in[2]:7 ropt_net_242:4 6.30286e-06 + +*RES +0 chany_top_in[2] chany_top_in[2]:34 0.0176183 +1 chany_top_in[2]:31 chany_top_in[2]:30 0.01178795 +2 chany_top_in[2]:32 chany_top_in[2]:31 0.00341 +3 chany_top_in[2]:34 chany_top_in[2]:33 0.00341 +4 chany_top_in[2]:33 chany_top_in[2]:32 0.001150717 +5 chany_top_in[2]:13 chany_top_in[2]:12 0.00341 +6 chany_top_in[2]:12 chany_top_in[2]:11 0.0003352666 +7 chany_top_in[2]:10 chany_top_in[2]:9 0.006890625 +8 chany_top_in[2]:11 chany_top_in[2]:10 0.00341 +9 chany_top_in[2]:8 chany_top_in[2]:7 0.006531251 +10 chany_top_in[2]:9 chany_top_in[2]:8 0.0045 +11 chany_top_in[2]:5 ropt_mt_inst_819:A 0.152 +12 chany_top_in[2]:15 chany_top_in[2]:14 0.002475447 +13 chany_top_in[2]:16 chany_top_in[2]:15 0.0045 +14 chany_top_in[2]:16 chany_top_in[2]:13 0.01664509 +15 chany_top_in[2]:14 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[2]:29 chany_top_in[2]:28 0.0008370536 +17 chany_top_in[2]:30 chany_top_in[2]:29 0.0045 +18 chany_top_in[2]:30 chany_top_in[2]:27 0.001466518 +19 chany_top_in[2]:28 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +20 chany_top_in[2]:18 chany_top_in[2]:17 0.0045 +21 chany_top_in[2]:17 chany_top_in[2]:16 0.002995536 +22 chany_top_in[2]:19 chany_top_in[2]:18 0.01922322 +23 chany_top_in[2]:20 chany_top_in[2]:19 0.0045 +24 chany_top_in[2]:21 chany_top_in[2]:20 0.003247768 +25 chany_top_in[2]:22 chany_top_in[2]:21 0.00341 +26 chany_top_in[2]:22 chany_top_in[2]:4 0.0001039141 +27 chany_top_in[2]:23 chany_top_in[2]:22 0.00341 +28 chany_top_in[2]:25 chany_top_in[2]:24 0.00341 +29 chany_top_in[2]:24 chany_top_in[2]:23 0.007987649 +30 chany_top_in[2]:27 chany_top_in[2]:26 0.00341 +31 chany_top_in[2]:26 chany_top_in[2]:25 0.0002118917 +32 chany_top_in[2]:6 chany_top_in[2]:5 0.003662947 +33 chany_top_in[2]:7 chany_top_in[2]:6 0.0003035715 + +*END + +*D_NET chany_bottom_in[3] 0.01380838 //LENGTH 125.465 LUMPCC 0.0009263441 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 13.800 1.290 +*I BUFT_RR_87:A I *L 0.001776 *C 103.960 34.000 +*N chany_bottom_in[3]:2 *C 103.960 34.000 +*N chany_bottom_in[3]:3 *C 103.960 34.340 +*N chany_bottom_in[3]:4 *C 88.365 34.340 +*N chany_bottom_in[3]:5 *C 88.320 34.295 +*N chany_bottom_in[3]:6 *C 88.320 31.665 +*N chany_bottom_in[3]:7 *C 88.275 31.620 +*N chany_bottom_in[3]:8 *C 83.305 31.620 +*N chany_bottom_in[3]:9 *C 83.260 31.575 +*N chany_bottom_in[3]:10 *C 83.260 14.338 +*N chany_bottom_in[3]:11 *C 83.252 14.280 +*N chany_bottom_in[3]:12 *C 63.635 14.280 +*N chany_bottom_in[3]:13 *C 13.808 14.280 +*N chany_bottom_in[3]:14 *C 13.800 14.223 + +*CAP +0 chany_bottom_in[3] 0.0004451096 +1 BUFT_RR_87:A 1e-06 +2 chany_bottom_in[3]:2 6.129771e-05 +3 chany_bottom_in[3]:3 0.0009823025 +4 chany_bottom_in[3]:4 0.0009524883 +5 chany_bottom_in[3]:5 0.0001601153 +6 chany_bottom_in[3]:6 0.0001601153 +7 chany_bottom_in[3]:7 0.0002117541 +8 chany_bottom_in[3]:8 0.0002117541 +9 chany_bottom_in[3]:9 0.0007501852 +10 chany_bottom_in[3]:10 0.0007501852 +11 chany_bottom_in[3]:11 0.001146588 +12 chany_bottom_in[3]:12 0.003875309 +13 chany_bottom_in[3]:13 0.00272872 +14 chany_bottom_in[3]:14 0.0004451096 +15 chany_bottom_in[3] chany_bottom_in[1] 0.0001936462 +16 chany_bottom_in[3]:9 chany_bottom_in[1]:11 9.206664e-05 +17 chany_bottom_in[3]:10 chany_bottom_in[1]:12 9.206664e-05 +18 chany_bottom_in[3]:14 chany_bottom_in[1]:16 0.0001936462 +19 chany_bottom_in[3]:7 optlc_net_183:11 0.0001046185 +20 chany_bottom_in[3]:8 optlc_net_183:10 0.0001046185 +21 chany_bottom_in[3]:9 optlc_net_183:8 2.45507e-06 +22 chany_bottom_in[3]:10 optlc_net_183:9 2.45507e-06 +23 chany_bottom_in[3]:13 ropt_net_215:7 7.038557e-05 +24 chany_bottom_in[3]:12 ropt_net_215:6 7.038557e-05 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:14 0.01154688 +1 chany_bottom_in[3]:2 BUFT_RR_87:A 0.152 +2 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.01392411 +3 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.0045 +4 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.0045 +5 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.002348214 +6 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.0044375 +7 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.0045 +8 chany_bottom_in[3]:10 chany_bottom_in[3]:9 0.01539062 +9 chany_bottom_in[3]:11 chany_bottom_in[3]:10 0.00341 +10 chany_bottom_in[3]:14 chany_bottom_in[3]:13 0.00341 +11 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.007806308 +12 chany_bottom_in[3]:3 chany_bottom_in[3]:2 0.0003035715 +13 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.003073408 + +*END + +*D_NET chany_bottom_in[4] 0.02439272 //LENGTH 191.930 LUMPCC 0.008030557 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 73.140 1.290 +*I mux_top_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 96.890 47.940 +*I mux_right_track_2\/mux_l1_in_3_:A1 I *L 0.00198 *C 77.840 107.100 +*I BUFT_P_161:A I *L 0.001776 *C 41.860 123.760 +*N chany_bottom_in[4]:4 *C 76.880 107.100 +*N chany_bottom_in[4]:5 *C 41.883 123.733 +*N chany_bottom_in[4]:6 *C 41.895 123.420 +*N chany_bottom_in[4]:7 *C 44.575 123.420 +*N chany_bottom_in[4]:8 *C 44.620 123.420 +*N chany_bottom_in[4]:9 *C 44.620 123.080 +*N chany_bottom_in[4]:10 *C 44.628 123.080 +*N chany_bottom_in[4]:11 *C 76.340 123.080 +*N chany_bottom_in[4]:12 *C 76.360 123.073 +*N chany_bottom_in[4]:13 *C 76.360 107.100 +*N chany_bottom_in[4]:14 *C 77.273 107.100 +*N chany_bottom_in[4]:15 *C 77.280 107.100 +*N chany_bottom_in[4]:16 *C 77.280 107.100 +*N chany_bottom_in[4]:17 *C 77.325 107.100 +*N chany_bottom_in[4]:18 *C 77.840 107.100 +*N chany_bottom_in[4]:19 *C 79.995 107.100 +*N chany_bottom_in[4]:20 *C 80.040 107.100 +*N chany_bottom_in[4]:21 *C 80.040 106.760 +*N chany_bottom_in[4]:22 *C 80.047 106.760 +*N chany_bottom_in[4]:23 *C 81.860 106.760 +*N chany_bottom_in[4]:24 *C 81.880 106.753 +*N chany_bottom_in[4]:25 *C 81.880 96.920 +*N chany_bottom_in[4]:26 *C 96.853 47.940 +*N chany_bottom_in[4]:27 *C 96.185 47.940 +*N chany_bottom_in[4]:28 *C 96.140 47.895 +*N chany_bottom_in[4]:29 *C 96.140 46.977 +*N chany_bottom_in[4]:30 *C 96.133 46.920 +*N chany_bottom_in[4]:31 *C 81.900 46.920 +*N chany_bottom_in[4]:32 *C 81.880 46.920 +*N chany_bottom_in[4]:33 *C 81.880 10.888 +*N chany_bottom_in[4]:34 *C 81.860 10.880 +*N chany_bottom_in[4]:35 *C 73.148 10.880 +*N chany_bottom_in[4]:36 *C 73.140 10.822 + +*CAP +0 chany_bottom_in[4] 0.0005070377 +1 mux_top_track_2\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_3_:A1 1e-06 +3 BUFT_P_161:A 1e-06 +4 chany_bottom_in[4]:4 8.288633e-05 +5 chany_bottom_in[4]:5 3.315988e-05 +6 chany_bottom_in[4]:6 0.0001813545 +7 chany_bottom_in[4]:7 0.0001481946 +8 chany_bottom_in[4]:8 5.348915e-05 +9 chany_bottom_in[4]:9 5.772721e-05 +10 chany_bottom_in[4]:10 0.001530916 +11 chany_bottom_in[4]:11 0.001530916 +12 chany_bottom_in[4]:12 0.0003205093 +13 chany_bottom_in[4]:13 0.0003393564 +14 chany_bottom_in[4]:14 1.884707e-05 +15 chany_bottom_in[4]:15 8.288633e-05 +16 chany_bottom_in[4]:16 3.839174e-05 +17 chany_bottom_in[4]:17 4.455569e-05 +18 chany_bottom_in[4]:18 0.0002195693 +19 chany_bottom_in[4]:19 0.0001460436 +20 chany_bottom_in[4]:20 5.785785e-05 +21 chany_bottom_in[4]:21 6.215272e-05 +22 chany_bottom_in[4]:22 0.0001724773 +23 chany_bottom_in[4]:23 0.0001724773 +24 chany_bottom_in[4]:24 0.0001860362 +25 chany_bottom_in[4]:25 0.002160584 +26 chany_bottom_in[4]:26 8.461039e-05 +27 chany_bottom_in[4]:27 8.461039e-05 +28 chany_bottom_in[4]:28 8.845937e-05 +29 chany_bottom_in[4]:29 8.845937e-05 +30 chany_bottom_in[4]:30 0.0009051267 +31 chany_bottom_in[4]:31 0.0009051267 +32 chany_bottom_in[4]:32 0.00321055 +33 chany_bottom_in[4]:33 0.001236003 +34 chany_bottom_in[4]:34 0.0005508747 +35 chany_bottom_in[4]:35 0.0005508747 +36 chany_bottom_in[4]:36 0.0005070377 +37 chany_bottom_in[4]:32 chany_top_in[13]:25 0.0002805097 +38 chany_bottom_in[4]:32 chany_top_in[13]:26 1.922283e-05 +39 chany_bottom_in[4]:33 chany_top_in[13]:25 1.922283e-05 +40 chany_bottom_in[4]:25 chany_top_in[13]:26 0.0002805097 +41 chany_bottom_in[4]:11 chany_top_in[14]:24 0.0002309685 +42 chany_bottom_in[4]:12 chany_top_in[14]:23 0.0003493161 +43 chany_bottom_in[4]:10 chany_top_in[14]:25 0.0002309685 +44 chany_bottom_in[4]:13 chany_top_in[14]:22 0.0003493161 +45 chany_bottom_in[4]:32 chany_bottom_in[2]:31 0.001025048 +46 chany_bottom_in[4]:32 chany_bottom_in[2]:32 0.000144088 +47 chany_bottom_in[4]:33 chany_bottom_in[2]:32 0.0007732883 +48 chany_bottom_in[4]:25 chany_bottom_in[2]:30 0.0002517595 +49 chany_bottom_in[4]:25 chany_bottom_in[2]:31 0.000144088 +50 chany_bottom_in[4]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003797404 +51 chany_bottom_in[4]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.802001e-06 +52 chany_bottom_in[4]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003797404 +53 chany_bottom_in[4]:32 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 5.717797e-05 +54 chany_bottom_in[4]:32 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.000171118 +55 chany_bottom_in[4]:24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002085096 +56 chany_bottom_in[4]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.802001e-06 +57 chany_bottom_in[4]:25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 5.717797e-05 +58 chany_bottom_in[4]:25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002085096 +59 chany_bottom_in[4]:25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000171118 +60 chany_bottom_in[4]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002314745 +61 chany_bottom_in[4]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 9.369855e-05 +62 chany_bottom_in[4]:32 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001597759 +63 chany_bottom_in[4]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 9.369855e-05 +64 chany_bottom_in[4]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0002314745 +65 chany_bottom_in[4]:25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001597759 +66 chany_bottom_in[4]:15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 4.016443e-07 +67 chany_bottom_in[4]:14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 4.965192e-05 +68 chany_bottom_in[4]:32 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.505154e-05 +69 chany_bottom_in[4]:24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0004492011 +70 chany_bottom_in[4]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 4.016443e-07 +71 chany_bottom_in[4]:13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 4.965192e-05 +72 chany_bottom_in[4]:25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.505154e-05 +73 chany_bottom_in[4]:25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0004492011 +74 chany_bottom_in[4]:9 ropt_net_217:7 2.879452e-06 +75 chany_bottom_in[4]:7 ropt_net_217:8 7.564198e-05 +76 chany_bottom_in[4]:8 ropt_net_217:6 2.879452e-06 +77 chany_bottom_in[4]:6 ropt_net_217:9 7.564198e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:36 0.008511161 +1 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.0045 +2 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.00341 +3 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.00341 +4 chany_bottom_in[4]:15 chany_bottom_in[4]:4 5.69697e-05 +5 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.0001429583 +6 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.004968291 +7 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.00341 +8 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.0001634615 +9 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.00341 +10 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.002392857 +11 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.0045 +12 chany_bottom_in[4]:5 BUFT_P_161:A 0.152 +13 chany_bottom_in[4]:31 chany_bottom_in[4]:30 0.002229758 +14 chany_bottom_in[4]:32 chany_bottom_in[4]:31 0.00341 +15 chany_bottom_in[4]:32 chany_bottom_in[4]:25 0.007833333 +16 chany_bottom_in[4]:29 chany_bottom_in[4]:28 0.0008191965 +17 chany_bottom_in[4]:30 chany_bottom_in[4]:29 0.00341 +18 chany_bottom_in[4]:27 chany_bottom_in[4]:26 0.0005959821 +19 chany_bottom_in[4]:28 chany_bottom_in[4]:27 0.0045 +20 chany_bottom_in[4]:26 mux_top_track_2\/mux_l1_in_1_:A0 0.152 +21 chany_bottom_in[4]:34 chany_bottom_in[4]:33 0.00341 +22 chany_bottom_in[4]:33 chany_bottom_in[4]:32 0.005645091 +23 chany_bottom_in[4]:36 chany_bottom_in[4]:35 0.00341 +24 chany_bottom_in[4]:35 chany_bottom_in[4]:34 0.001364958 +25 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.0002839583 +26 chany_bottom_in[4]:24 chany_bottom_in[4]:23 0.00341 +27 chany_bottom_in[4]:21 chany_bottom_in[4]:20 0.0001634615 +28 chany_bottom_in[4]:22 chany_bottom_in[4]:21 0.00341 +29 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.001924107 +30 chany_bottom_in[4]:20 chany_bottom_in[4]:19 0.0045 +31 chany_bottom_in[4]:18 mux_right_track_2\/mux_l1_in_3_:A1 0.152 +32 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.0004598215 +33 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.0002111487 +34 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.002502358 +35 chany_bottom_in[4]:25 chany_bottom_in[4]:24 0.001540425 + +*END + +*D_NET chany_bottom_in[5] 0.02755152 //LENGTH 195.545 LUMPCC 0.009560503 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 49.220 1.290 +*I mux_top_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 75.080 56.100 +*I BUFT_RR_89:A I *L 0.001776 *C 24.840 115.600 +*I mux_right_track_4\/mux_l1_in_3_:A1 I *L 0.00198 *C 72.320 105.060 +*N chany_bottom_in[5]:4 *C 72.220 105.060 +*N chany_bottom_in[5]:5 *C 72.220 105.015 +*N chany_bottom_in[5]:6 *C 72.220 102.738 +*N chany_bottom_in[5]:7 *C 72.213 102.680 +*N chany_bottom_in[5]:8 *C 24.840 115.600 +*N chany_bottom_in[5]:9 *C 24.840 115.555 +*N chany_bottom_in[5]:10 *C 24.840 107.498 +*N chany_bottom_in[5]:11 *C 24.848 107.440 +*N chany_bottom_in[5]:12 *C 46.900 107.440 +*N chany_bottom_in[5]:13 *C 46.920 107.433 +*N chany_bottom_in[5]:14 *C 46.920 102.688 +*N chany_bottom_in[5]:15 *C 46.940 102.680 +*N chany_bottom_in[5]:16 *C 55.200 102.680 +*N chany_bottom_in[5]:17 *C 55.200 102.672 +*N chany_bottom_in[5]:18 *C 75.043 56.100 +*N chany_bottom_in[5]:19 *C 73.600 56.100 +*N chany_bottom_in[5]:20 *C 73.600 55.760 +*N chany_bottom_in[5]:21 *C 73.185 55.760 +*N chany_bottom_in[5]:22 *C 73.140 55.805 +*N chany_bottom_in[5]:23 *C 73.140 56.383 +*N chany_bottom_in[5]:24 *C 73.133 56.440 +*N chany_bottom_in[5]:25 *C 55.220 56.440 +*N chany_bottom_in[5]:26 *C 55.200 56.440 +*N chany_bottom_in[5]:27 *C 55.200 46.928 +*N chany_bottom_in[5]:28 *C 55.180 46.920 +*N chany_bottom_in[5]:29 *C 49.700 46.920 +*N chany_bottom_in[5]:30 *C 49.680 46.913 +*N chany_bottom_in[5]:31 *C 49.680 3.408 +*N chany_bottom_in[5]:32 *C 49.665 3.400 +*N chany_bottom_in[5]:33 *C 49.223 3.400 +*N chany_bottom_in[5]:34 *C 49.220 3.343 + +*CAP +0 chany_bottom_in[5] 0.0001456003 +1 mux_top_track_4\/mux_l1_in_2_:A1 1e-06 +2 BUFT_RR_89:A 1e-06 +3 mux_right_track_4\/mux_l1_in_3_:A1 1e-06 +4 chany_bottom_in[5]:4 3.410249e-05 +5 chany_bottom_in[5]:5 0.0001606933 +6 chany_bottom_in[5]:6 0.0001606933 +7 chany_bottom_in[5]:7 0.0008931247 +8 chany_bottom_in[5]:8 3.176572e-05 +9 chany_bottom_in[5]:9 0.0003906525 +10 chany_bottom_in[5]:10 0.0003906525 +11 chany_bottom_in[5]:11 0.0009261031 +12 chany_bottom_in[5]:12 0.0009261031 +13 chany_bottom_in[5]:13 0.0004196824 +14 chany_bottom_in[5]:14 0.0004196824 +15 chany_bottom_in[5]:15 0.0004636128 +16 chany_bottom_in[5]:16 0.001356737 +17 chany_bottom_in[5]:17 0.002072238 +18 chany_bottom_in[5]:18 0.0001080922 +19 chany_bottom_in[5]:19 0.0001340313 +20 chany_bottom_in[5]:20 7.546383e-05 +21 chany_bottom_in[5]:21 4.952474e-05 +22 chany_bottom_in[5]:22 6.229661e-05 +23 chany_bottom_in[5]:23 6.229661e-05 +24 chany_bottom_in[5]:24 0.0009029432 +25 chany_bottom_in[5]:25 0.0009029431 +26 chany_bottom_in[5]:26 0.0025001 +27 chany_bottom_in[5]:27 0.0004278627 +28 chany_bottom_in[5]:28 0.0004057453 +29 chany_bottom_in[5]:29 0.0004057453 +30 chany_bottom_in[5]:30 0.001441558 +31 chany_bottom_in[5]:31 0.001441558 +32 chany_bottom_in[5]:32 6.540216e-05 +33 chany_bottom_in[5]:33 6.540216e-05 +34 chany_bottom_in[5]:34 0.0001456003 +35 chany_bottom_in[5]:15 chany_top_in[5]:23 1.618427e-05 +36 chany_bottom_in[5]:12 chany_top_in[5]:22 0.0002282401 +37 chany_bottom_in[5]:11 chany_top_in[5]:23 0.0002282401 +38 chany_bottom_in[5]:7 chany_top_in[5]:18 0.0001623448 +39 chany_bottom_in[5]:7 chany_top_in[5]:22 3.989215e-05 +40 chany_bottom_in[5]:16 chany_top_in[5]:19 0.0001623448 +41 chany_bottom_in[5]:16 chany_top_in[5]:22 1.618427e-05 +42 chany_bottom_in[5]:16 chany_top_in[5]:23 3.989215e-05 +43 chany_bottom_in[5]:30 chany_top_in[12]:8 1.56933e-05 +44 chany_bottom_in[5]:30 chany_top_in[12]:17 2.773929e-05 +45 chany_bottom_in[5]:30 chany_top_in[12]:19 0.000494634 +46 chany_bottom_in[5]:31 chany_top_in[12]:7 1.56933e-05 +47 chany_bottom_in[5]:31 chany_top_in[12]:10 2.773929e-05 +48 chany_bottom_in[5]:31 chany_top_in[12]:18 0.000494634 +49 chany_bottom_in[5]:27 chany_bottom_in[10]:22 0.0001505689 +50 chany_bottom_in[5]:30 chany_bottom_in[10]:21 0.0002883968 +51 chany_bottom_in[5]:31 chany_bottom_in[10]:22 0.0002883968 +52 chany_bottom_in[5]:26 chany_bottom_in[10]:22 7.100217e-05 +53 chany_bottom_in[5]:26 chany_bottom_in[10]:21 0.0003034821 +54 chany_bottom_in[5]:17 chany_bottom_in[10]:20 0.0001529132 +55 chany_bottom_in[5]:17 chany_bottom_in[10]:21 7.100217e-05 +56 chany_bottom_in[5]:25 chany_bottom_in[13]:20 0.0003667783 +57 chany_bottom_in[5]:24 chany_bottom_in[13]:21 0.0003667783 +58 chany_bottom_in[5]:30 chany_bottom_in[14]:18 0.0005443045 +59 chany_bottom_in[5]:31 chany_bottom_in[14]:19 0.0005443045 +60 chany_bottom_in[5]:18 chany_bottom_in[14]:5 2.23482e-06 +61 chany_bottom_in[5]:19 chany_bottom_in[14]:4 2.23482e-06 +62 chany_bottom_in[5]:15 chany_bottom_in[16]:17 9.973008e-06 +63 chany_bottom_in[5]:26 chany_bottom_in[16]:19 0.001280569 +64 chany_bottom_in[5]:16 chany_bottom_in[16]:16 9.973008e-06 +65 chany_bottom_in[5]:17 chany_bottom_in[16]:18 0.001280569 +66 chany_bottom_in[5]:12 prog_clk[0]:334 0.0001646269 +67 chany_bottom_in[5]:12 prog_clk[0]:341 3.588635e-06 +68 chany_bottom_in[5]:12 prog_clk[0]:329 0.00014177 +69 chany_bottom_in[5]:11 prog_clk[0]:334 0.00014177 +70 chany_bottom_in[5]:11 prog_clk[0]:342 3.588635e-06 +71 chany_bottom_in[5]:11 prog_clk[0]:335 0.0001646269 +72 chany_bottom_in[5]:7 prog_clk[0]:259 1.209242e-06 +73 chany_bottom_in[5]:25 prog_clk[0]:246 1.008847e-06 +74 chany_bottom_in[5]:25 prog_clk[0]:172 2.775723e-05 +75 chany_bottom_in[5]:25 prog_clk[0]:301 4.099763e-06 +76 chany_bottom_in[5]:25 prog_clk[0]:251 4.454146e-05 +77 chany_bottom_in[5]:25 prog_clk[0]:124 5.47812e-06 +78 chany_bottom_in[5]:26 prog_clk[0]:276 9.443239e-06 +79 chany_bottom_in[5]:26 prog_clk[0]:299 5.702622e-06 +80 chany_bottom_in[5]:26 prog_clk[0]:282 8.044556e-06 +81 chany_bottom_in[5]:26 prog_clk[0]:288 1.546125e-05 +82 chany_bottom_in[5]:24 prog_clk[0]:246 4.454146e-05 +83 chany_bottom_in[5]:24 prog_clk[0]:172 1.008847e-06 +84 chany_bottom_in[5]:24 prog_clk[0]:251 4.099763e-06 +85 chany_bottom_in[5]:24 prog_clk[0]:124 2.775723e-05 +86 chany_bottom_in[5]:24 prog_clk[0]:119 5.47812e-06 +87 chany_bottom_in[5]:16 prog_clk[0]:263 1.209242e-06 +88 chany_bottom_in[5]:17 prog_clk[0]:276 8.044556e-06 +89 chany_bottom_in[5]:17 prog_clk[0]:273 9.443239e-06 +90 chany_bottom_in[5]:17 prog_clk[0]:296 5.702622e-06 +91 chany_bottom_in[5]:17 prog_clk[0]:283 1.546125e-05 +92 chany_bottom_in[5]:15 right_top_grid_pin_42_[0]:22 0.0001668225 +93 chany_bottom_in[5]:7 right_top_grid_pin_42_[0]:23 0.0003292307 +94 chany_bottom_in[5]:16 right_top_grid_pin_42_[0]:22 0.0003292307 +95 chany_bottom_in[5]:16 right_top_grid_pin_42_[0]:23 0.0001668225 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:34 0.001832589 +1 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.00341 +2 chany_bottom_in[5]:14 chany_bottom_in[5]:13 0.0007433833 +3 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.003454891 +4 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.00341 +5 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.007194197 +6 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.00341 +7 chany_bottom_in[5]:8 BUFT_RR_89:A 0.152 +8 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.0045 +9 chany_bottom_in[5]:28 chany_bottom_in[5]:27 0.00341 +10 chany_bottom_in[5]:27 chany_bottom_in[5]:26 0.001490292 +11 chany_bottom_in[5]:29 chany_bottom_in[5]:28 0.0008585333 +12 chany_bottom_in[5]:30 chany_bottom_in[5]:29 0.00341 +13 chany_bottom_in[5]:32 chany_bottom_in[5]:31 0.00341 +14 chany_bottom_in[5]:31 chany_bottom_in[5]:30 0.006815783 +15 chany_bottom_in[5]:34 chany_bottom_in[5]:33 0.00341 +16 chany_bottom_in[5]:33 chany_bottom_in[5]:32 6.499219e-05 +17 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.002033482 +18 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.00341 +19 chany_bottom_in[5]:4 mux_right_track_4\/mux_l1_in_3_:A1 0.152 +20 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.0045 +21 chany_bottom_in[5]:25 chany_bottom_in[5]:24 0.002806291 +22 chany_bottom_in[5]:26 chany_bottom_in[5]:25 0.00341 +23 chany_bottom_in[5]:26 chany_bottom_in[5]:17 0.007243091 +24 chany_bottom_in[5]:23 chany_bottom_in[5]:22 0.000515625 +25 chany_bottom_in[5]:24 chany_bottom_in[5]:23 0.00341 +26 chany_bottom_in[5]:21 chany_bottom_in[5]:20 0.0003705358 +27 chany_bottom_in[5]:22 chany_bottom_in[5]:21 0.0045 +28 chany_bottom_in[5]:18 mux_top_track_4\/mux_l1_in_2_:A1 0.152 +29 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.001294067 +30 chany_bottom_in[5]:16 chany_bottom_in[5]:7 0.002665292 +31 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.00341 +32 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.0003035715 +33 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.001287946 + +*END + +*D_NET chany_bottom_in[6] 0.01822159 //LENGTH 156.350 LUMPCC 0.004345953 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 52.900 1.290 +*I mux_top_track_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 66.700 58.140 +*I BUFT_P_139:A I *L 0.001767 *C 67.160 126.480 +*I mux_right_track_6\/mux_l1_in_3_:A1 I *L 0.00198 *C 63.120 110.500 +*N chany_bottom_in[6]:4 *C 63.083 110.500 +*N chany_bottom_in[6]:5 *C 61.640 110.500 +*N chany_bottom_in[6]:6 *C 67.123 126.480 +*N chany_bottom_in[6]:7 *C 59.845 126.480 +*N chany_bottom_in[6]:8 *C 59.800 126.435 +*N chany_bottom_in[6]:9 *C 59.800 110.205 +*N chany_bottom_in[6]:10 *C 59.845 110.160 +*N chany_bottom_in[6]:11 *C 61.640 110.190 +*N chany_bottom_in[6]:12 *C 61.640 110.115 +*N chany_bottom_in[6]:13 *C 61.640 83.017 +*N chany_bottom_in[6]:14 *C 61.648 82.960 +*N chany_bottom_in[6]:15 *C 62.540 82.960 +*N chany_bottom_in[6]:16 *C 62.560 82.953 +*N chany_bottom_in[6]:17 *C 62.560 59.840 +*N chany_bottom_in[6]:18 *C 61.640 59.840 +*N chany_bottom_in[6]:19 *C 66.700 58.155 +*N chany_bottom_in[6]:20 *C 66.700 58.480 +*N chany_bottom_in[6]:21 *C 66.700 58.480 +*N chany_bottom_in[6]:22 *C 66.693 58.480 +*N chany_bottom_in[6]:23 *C 61.660 58.480 +*N chany_bottom_in[6]:24 *C 61.640 58.480 +*N chany_bottom_in[6]:25 *C 61.640 4.088 +*N chany_bottom_in[6]:26 *C 61.620 4.080 +*N chany_bottom_in[6]:27 *C 52.908 4.080 +*N chany_bottom_in[6]:28 *C 52.900 4.022 + +*CAP +0 chany_bottom_in[6] 0.0001629554 +1 mux_top_track_8\/mux_l1_in_2_:A1 1e-06 +2 BUFT_P_139:A 1e-06 +3 mux_right_track_6\/mux_l1_in_3_:A1 1e-06 +4 chany_bottom_in[6]:4 0.0001122406 +5 chany_bottom_in[6]:5 0.0001392275 +6 chany_bottom_in[6]:6 0.000273445 +7 chany_bottom_in[6]:7 0.000273445 +8 chany_bottom_in[6]:8 0.0008179353 +9 chany_bottom_in[6]:9 0.0008179353 +10 chany_bottom_in[6]:10 0.0001188736 +11 chany_bottom_in[6]:11 0.0001458605 +12 chany_bottom_in[6]:12 0.001398421 +13 chany_bottom_in[6]:13 0.001398421 +14 chany_bottom_in[6]:14 8.886098e-05 +15 chany_bottom_in[6]:15 8.886098e-05 +16 chany_bottom_in[6]:16 0.0007439543 +17 chany_bottom_in[6]:17 0.0007577565 +18 chany_bottom_in[6]:18 0.0001043764 +19 chany_bottom_in[6]:19 3.562869e-05 +20 chany_bottom_in[6]:20 6.899312e-05 +21 chany_bottom_in[6]:21 3.723837e-05 +22 chany_bottom_in[6]:22 0.0002504002 +23 chany_bottom_in[6]:23 0.0002504002 +24 chany_bottom_in[6]:24 0.002340236 +25 chany_bottom_in[6]:25 0.002249662 +26 chany_bottom_in[6]:26 0.0005172763 +27 chany_bottom_in[6]:27 0.0005172763 +28 chany_bottom_in[6]:28 0.0001629554 +29 chany_bottom_in[6]:7 chany_top_in[4]:26 2.26894e-05 +30 chany_bottom_in[6]:7 chany_top_in[4]:27 0.0002662871 +31 chany_bottom_in[6]:6 chany_top_in[4]:4 2.26894e-05 +32 chany_bottom_in[6]:6 chany_top_in[4]:26 0.0002662871 +33 chany_bottom_in[6]:12 chany_bottom_in[12]:31 5.234186e-06 +34 chany_bottom_in[6]:13 chany_bottom_in[12]:41 5.234186e-06 +35 chany_bottom_in[6]:16 chany_bottom_in[12]:31 9.399005e-05 +36 chany_bottom_in[6]:16 chany_bottom_in[12]:41 0.0001807273 +37 chany_bottom_in[6]:16 chany_bottom_in[12]:42 0.0001823553 +38 chany_bottom_in[6]:24 chany_bottom_in[12]:43 6.274585e-06 +39 chany_bottom_in[6]:24 chany_bottom_in[12]:42 0.0005307265 +40 chany_bottom_in[6]:25 chany_bottom_in[12]:43 0.0005307265 +41 chany_bottom_in[6]:18 chany_bottom_in[12]:42 6.274585e-06 +42 chany_bottom_in[6]:17 chany_bottom_in[12]:43 0.0001823553 +43 chany_bottom_in[6]:17 chany_bottom_in[12]:41 9.399005e-05 +44 chany_bottom_in[6]:17 chany_bottom_in[12]:42 0.0001807273 +45 chany_bottom_in[6]:23 prog_clk[0]:246 9.820707e-05 +46 chany_bottom_in[6]:23 prog_clk[0]:172 3.335838e-05 +47 chany_bottom_in[6]:23 prog_clk[0]:251 0.0001588424 +48 chany_bottom_in[6]:22 prog_clk[0]:246 0.0001588424 +49 chany_bottom_in[6]:22 prog_clk[0]:172 9.820707e-05 +50 chany_bottom_in[6]:22 prog_clk[0]:124 3.335838e-05 +51 chany_bottom_in[6]:18 prog_clk[0]:251 3.56392e-05 +52 chany_bottom_in[6]:17 prog_clk[0]:246 3.56392e-05 +53 chany_bottom_in[6]:12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.216865e-05 +54 chany_bottom_in[6]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.216865e-05 +55 chany_bottom_in[6]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003887853 +56 chany_bottom_in[6]:18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 1.769049e-05 +57 chany_bottom_in[6]:17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 1.769049e-05 +58 chany_bottom_in[6]:17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0003887853 +59 chany_bottom_in[6]:12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.981967e-05 +60 chany_bottom_in[6]:13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.981967e-05 +61 chany_bottom_in[6]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.0181e-05 +62 chany_bottom_in[6]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.0181e-05 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:28 0.002439732 +1 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.001602679 +2 chany_bottom_in[6]:11 chany_bottom_in[6]:5 0.0002767857 +3 chany_bottom_in[6]:12 chany_bottom_in[6]:11 0.0045 +4 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.0241942 +5 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.00341 +6 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.000139825 +7 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.00341 +8 chany_bottom_in[6]:4 mux_right_track_6\/mux_l1_in_3_:A1 0.152 +9 chany_bottom_in[6]:23 chany_bottom_in[6]:22 0.000788425 +10 chany_bottom_in[6]:24 chany_bottom_in[6]:23 0.00341 +11 chany_bottom_in[6]:24 chany_bottom_in[6]:18 0.0002130667 +12 chany_bottom_in[6]:21 chany_bottom_in[6]:20 0.0045 +13 chany_bottom_in[6]:22 chany_bottom_in[6]:21 0.00341 +14 chany_bottom_in[6]:20 chany_bottom_in[6]:19 0.0001766304 +15 chany_bottom_in[6]:19 mux_top_track_8\/mux_l1_in_2_:A1 0.152 +16 chany_bottom_in[6]:26 chany_bottom_in[6]:25 0.00341 +17 chany_bottom_in[6]:25 chany_bottom_in[6]:24 0.008521492 +18 chany_bottom_in[6]:28 chany_bottom_in[6]:27 0.00341 +19 chany_bottom_in[6]:27 chany_bottom_in[6]:26 0.001364958 +20 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.0045 +21 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.01449107 +22 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.006497768 +23 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.0045 +24 chany_bottom_in[6]:6 BUFT_P_139:A 0.152 +25 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.001287946 +26 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.0001441333 +27 chany_bottom_in[6]:17 chany_bottom_in[6]:16 0.003620958 + +*END + +*D_NET chany_bottom_in[7] 0.01638278 //LENGTH 145.410 LUMPCC 0.001251776 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 22.080 1.290 +*I BUFT_RR_90:A I *L 0.001776 *C 102.580 63.920 +*N chany_bottom_in[7]:2 *C 102.580 63.920 +*N chany_bottom_in[7]:3 *C 102.580 63.875 +*N chany_bottom_in[7]:4 *C 102.580 62.617 +*N chany_bottom_in[7]:5 *C 102.573 62.560 +*N chany_bottom_in[7]:6 *C 95.700 62.560 +*N chany_bottom_in[7]:7 *C 95.680 62.553 +*N chany_bottom_in[7]:8 *C 95.680 35.367 +*N chany_bottom_in[7]:9 *C 95.660 35.360 +*N chany_bottom_in[7]:10 *C 76.380 35.360 +*N chany_bottom_in[7]:11 *C 76.360 35.352 +*N chany_bottom_in[7]:12 *C 76.360 9.527 +*N chany_bottom_in[7]:13 *C 76.340 9.520 +*N chany_bottom_in[7]:14 *C 22.088 9.520 +*N chany_bottom_in[7]:15 *C 22.080 9.463 + +*CAP +0 chany_bottom_in[7] 0.000405273 +1 BUFT_RR_90:A 1e-06 +2 chany_bottom_in[7]:2 3.492125e-05 +3 chany_bottom_in[7]:3 8.697168e-05 +4 chany_bottom_in[7]:4 8.697168e-05 +5 chany_bottom_in[7]:5 0.0004173341 +6 chany_bottom_in[7]:6 0.0004173341 +7 chany_bottom_in[7]:7 0.001506301 +8 chany_bottom_in[7]:8 0.001506301 +9 chany_bottom_in[7]:9 0.00126363 +10 chany_bottom_in[7]:10 0.00126363 +11 chany_bottom_in[7]:11 0.0007609508 +12 chany_bottom_in[7]:12 0.0007609508 +13 chany_bottom_in[7]:13 0.00310708 +14 chany_bottom_in[7]:14 0.00310708 +15 chany_bottom_in[7]:15 0.000405273 +16 chany_bottom_in[7]:11 chany_bottom_in[2]:31 0.0002723652 +17 chany_bottom_in[7]:13 chany_bottom_in[2]:33 9.501752e-06 +18 chany_bottom_in[7]:12 chany_bottom_in[2]:32 0.0002723652 +19 chany_bottom_in[7]:14 chany_bottom_in[2]:34 9.501752e-06 +20 chany_bottom_in[7]:11 chany_bottom_in[13]:22 0.0003380963 +21 chany_bottom_in[7]:13 chany_bottom_in[13]:24 5.924655e-06 +22 chany_bottom_in[7]:12 chany_bottom_in[13]:23 0.0003380963 +23 chany_bottom_in[7]:14 chany_bottom_in[13]:25 5.924655e-06 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:15 0.007296875 +1 chany_bottom_in[7]:2 BUFT_RR_90:A 0.152 +2 chany_bottom_in[7]:3 chany_bottom_in[7]:2 0.0045 +3 chany_bottom_in[7]:4 chany_bottom_in[7]:3 0.001122768 +4 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.00341 +5 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.001076692 +6 chany_bottom_in[7]:7 chany_bottom_in[7]:6 0.00341 +7 chany_bottom_in[7]:9 chany_bottom_in[7]:8 0.00341 +8 chany_bottom_in[7]:8 chany_bottom_in[7]:7 0.004258983 +9 chany_bottom_in[7]:10 chany_bottom_in[7]:9 0.003020533 +10 chany_bottom_in[7]:11 chany_bottom_in[7]:10 0.00341 +11 chany_bottom_in[7]:13 chany_bottom_in[7]:12 0.00341 +12 chany_bottom_in[7]:12 chany_bottom_in[7]:11 0.004045916 +13 chany_bottom_in[7]:15 chany_bottom_in[7]:14 0.00341 +14 chany_bottom_in[7]:14 chany_bottom_in[7]:13 0.008499558 + +*END + +*D_NET chany_bottom_in[8] 0.01910757 //LENGTH 175.730 LUMPCC 0.001040199 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 23.920 1.290 +*I mux_top_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 40.310 66.300 +*I mux_right_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 34.040 101.660 +*I ropt_mt_inst_822:A I *L 0.001767 *C 11.960 126.480 +*N chany_bottom_in[8]:4 *C 11.960 126.480 +*N chany_bottom_in[8]:5 *C 11.960 126.435 +*N chany_bottom_in[8]:6 *C 11.960 121.765 +*N chany_bottom_in[8]:7 *C 12.005 121.720 +*N chany_bottom_in[8]:8 *C 21.040 121.720 +*N chany_bottom_in[8]:9 *C 21.152 121.675 +*N chany_bottom_in[8]:10 *C 21.160 121.085 +*N chany_bottom_in[8]:11 *C 21.205 121.040 +*N chany_bottom_in[8]:12 *C 22.080 121.040 +*N chany_bottom_in[8]:13 *C 22.080 120.995 +*N chany_bottom_in[8]:14 *C 22.080 101.705 +*N chany_bottom_in[8]:15 *C 22.125 101.660 +*N chany_bottom_in[8]:16 *C 34.040 101.683 +*N chany_bottom_in[8]:17 *C 34.040 102.000 +*N chany_bottom_in[8]:18 *C 38.135 102.000 +*N chany_bottom_in[8]:19 *C 38.180 101.955 +*N chany_bottom_in[8]:20 *C 38.180 90.780 +*N chany_bottom_in[8]:21 *C 38.640 90.780 +*N chany_bottom_in[8]:22 *C 38.640 66.345 +*N chany_bottom_in[8]:23 *C 38.685 66.300 +*N chany_bottom_in[8]:24 *C 40.273 66.300 +*N chany_bottom_in[8]:25 *C 40.350 66.300 +*N chany_bottom_in[8]:26 *C 40.480 66.255 +*N chany_bottom_in[8]:27 *C 40.480 63.978 +*N chany_bottom_in[8]:28 *C 40.473 63.920 +*N chany_bottom_in[8]:29 *C 30.380 63.920 +*N chany_bottom_in[8]:30 *C 30.360 63.913 +*N chany_bottom_in[8]:31 *C 30.360 52.555 +*N chany_bottom_in[8]:32 *C 30.360 2.728 +*N chany_bottom_in[8]:33 *C 30.340 2.720 +*N chany_bottom_in[8]:34 *C 23.928 2.720 +*N chany_bottom_in[8]:35 *C 23.920 2.663 + +*CAP +0 chany_bottom_in[8] 9.733089e-05 +1 mux_top_track_16\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_8\/mux_l2_in_1_:A1 1e-06 +3 ropt_mt_inst_822:A 1e-06 +4 chany_bottom_in[8]:4 2.870326e-05 +5 chany_bottom_in[8]:5 0.0002969512 +6 chany_bottom_in[8]:6 0.0002969512 +7 chany_bottom_in[8]:7 0.0005719732 +8 chany_bottom_in[8]:8 0.0005719732 +9 chany_bottom_in[8]:9 4.645421e-05 +10 chany_bottom_in[8]:10 4.645421e-05 +11 chany_bottom_in[8]:11 6.488958e-05 +12 chany_bottom_in[8]:12 9.28642e-05 +13 chany_bottom_in[8]:13 0.0008635651 +14 chany_bottom_in[8]:14 0.0008635651 +15 chany_bottom_in[8]:15 0.0007195427 +16 chany_bottom_in[8]:16 0.0007457599 +17 chany_bottom_in[8]:17 0.0002523571 +18 chany_bottom_in[8]:18 0.00022614 +19 chany_bottom_in[8]:19 0.0005122481 +20 chany_bottom_in[8]:20 0.0005301124 +21 chany_bottom_in[8]:21 0.001124759 +22 chany_bottom_in[8]:22 0.001106895 +23 chany_bottom_in[8]:23 0.0001038896 +24 chany_bottom_in[8]:24 0.0001249863 +25 chany_bottom_in[8]:25 2.109676e-05 +26 chany_bottom_in[8]:26 0.0001684951 +27 chany_bottom_in[8]:27 0.0001684951 +28 chany_bottom_in[8]:28 0.0006818511 +29 chany_bottom_in[8]:29 0.0006818511 +30 chany_bottom_in[8]:30 0.0005996514 +31 chany_bottom_in[8]:31 0.003023625 +32 chany_bottom_in[8]:32 0.002423973 +33 chany_bottom_in[8]:33 0.0004548191 +34 chany_bottom_in[8]:34 0.0004548191 +35 chany_bottom_in[8]:35 9.733089e-05 +36 chany_bottom_in[8]:22 chanx_right_in[6]:12 3.081172e-05 +37 chany_bottom_in[8]:22 chanx_right_in[6]:11 0.0002825012 +38 chany_bottom_in[8]:21 chanx_right_in[6]:12 0.0002825012 +39 chany_bottom_in[8]:21 chanx_right_in[6]:4 3.081172e-05 +40 chany_bottom_in[8]:19 mux_tree_tapbuf_size4_3_sram[2]:12 8.063658e-05 +41 chany_bottom_in[8]:22 mux_tree_tapbuf_size4_3_sram[2]:6 4.444548e-06 +42 chany_bottom_in[8]:22 mux_tree_tapbuf_size4_3_sram[2]:11 1.662969e-05 +43 chany_bottom_in[8]:20 mux_tree_tapbuf_size4_3_sram[2]:10 1.010158e-05 +44 chany_bottom_in[8]:20 mux_tree_tapbuf_size4_3_sram[2]:11 8.063658e-05 +45 chany_bottom_in[8]:21 mux_tree_tapbuf_size4_3_sram[2]:7 4.444548e-06 +46 chany_bottom_in[8]:21 mux_tree_tapbuf_size4_3_sram[2]:12 1.662969e-05 +47 chany_bottom_in[8]:21 mux_tree_tapbuf_size4_3_sram[2]:9 1.010158e-05 +48 chany_bottom_in[8]:18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.546388e-05 +49 chany_bottom_in[8]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.51013e-06 +50 chany_bottom_in[8]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.546388e-05 +51 chany_bottom_in[8]:20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.51013e-06 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:35 0.001225446 +1 chany_bottom_in[8]:25 chany_bottom_in[8]:24 6.919643e-05 +2 chany_bottom_in[8]:26 chany_bottom_in[8]:25 0.0045 +3 chany_bottom_in[8]:27 chany_bottom_in[8]:26 0.002033482 +4 chany_bottom_in[8]:28 chany_bottom_in[8]:27 0.00341 +5 chany_bottom_in[8]:29 chany_bottom_in[8]:28 0.001581158 +6 chany_bottom_in[8]:30 chany_bottom_in[8]:29 0.00341 +7 chany_bottom_in[8]:33 chany_bottom_in[8]:32 0.00341 +8 chany_bottom_in[8]:32 chany_bottom_in[8]:31 0.007806308 +9 chany_bottom_in[8]:35 chany_bottom_in[8]:34 0.00341 +10 chany_bottom_in[8]:34 chany_bottom_in[8]:33 0.001004625 +11 chany_bottom_in[8]:18 chany_bottom_in[8]:17 0.00365625 +12 chany_bottom_in[8]:19 chany_bottom_in[8]:18 0.0045 +13 chany_bottom_in[8]:23 chany_bottom_in[8]:22 0.0045 +14 chany_bottom_in[8]:22 chany_bottom_in[8]:21 0.02181697 +15 chany_bottom_in[8]:16 mux_right_track_8\/mux_l2_in_1_:A1 0.152 +16 chany_bottom_in[8]:16 chany_bottom_in[8]:15 0.01063839 +17 chany_bottom_in[8]:24 mux_top_track_16\/mux_l1_in_1_:A0 0.152 +18 chany_bottom_in[8]:24 chany_bottom_in[8]:23 0.001417411 +19 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.0045 +20 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.01722321 +21 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.00078125 +22 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.0045 +23 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.0045 +24 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.0005267858 +25 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.008066964 +26 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.0045 +27 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.0045 +28 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.004169643 +29 chany_bottom_in[8]:4 ropt_mt_inst_822:A 0.152 +30 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.0045 +31 chany_bottom_in[8]:17 chany_bottom_in[8]:16 0.0002834821 +32 chany_bottom_in[8]:20 chany_bottom_in[8]:19 0.00997768 +33 chany_bottom_in[8]:21 chany_bottom_in[8]:20 0.0004107143 +34 chany_bottom_in[8]:31 chany_bottom_in[8]:30 0.001779342 + +*END + +*D_NET chany_bottom_in[9] 0.01497951 //LENGTH 143.270 LUMPCC 0.002505798 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 23.000 1.325 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.350 80.920 +*I BUFT_P_140:A I *L 0.001776 *C 37.720 121.040 +*I mux_right_track_10\/mux_l2_in_1_:A1 I *L 0.00198 *C 34.140 88.740 +*N chany_bottom_in[9]:4 *C 34.102 88.740 +*N chany_bottom_in[9]:5 *C 37.683 121.040 +*N chany_bottom_in[9]:6 *C 35.925 121.040 +*N chany_bottom_in[9]:7 *C 35.880 120.995 +*N chany_bottom_in[9]:8 *C 35.880 89.125 +*N chany_bottom_in[9]:9 *C 35.835 89.080 +*N chany_bottom_in[9]:10 *C 33.580 89.080 +*N chany_bottom_in[9]:11 *C 33.580 88.740 +*N chany_bottom_in[9]:12 *C 33.580 88.695 +*N chany_bottom_in[9]:13 *C 33.580 79.605 +*N chany_bottom_in[9]:14 *C 33.535 79.560 +*N chany_bottom_in[9]:15 *C 28.388 80.920 +*N chany_bottom_in[9]:16 *C 29.395 80.920 +*N chany_bottom_in[9]:17 *C 29.440 80.875 +*N chany_bottom_in[9]:18 *C 29.440 79.605 +*N chany_bottom_in[9]:19 *C 29.440 79.560 +*N chany_bottom_in[9]:20 *C 21.665 79.560 +*N chany_bottom_in[9]:21 *C 21.620 79.515 +*N chany_bottom_in[9]:22 *C 21.620 60.130 +*N chany_bottom_in[9]:23 *C 21.620 10.200 +*N chany_bottom_in[9]:24 *C 23.000 10.200 + +*CAP +0 chany_bottom_in[9] 0.0004863354 +1 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +2 BUFT_P_140:A 1e-06 +3 mux_right_track_10\/mux_l2_in_1_:A1 1e-06 +4 chany_bottom_in[9]:4 4.835435e-05 +5 chany_bottom_in[9]:5 0.0001044447 +6 chany_bottom_in[9]:6 0.0001044447 +7 chany_bottom_in[9]:7 0.001127172 +8 chany_bottom_in[9]:8 0.001127172 +9 chany_bottom_in[9]:9 0.000184096 +10 chany_bottom_in[9]:10 0.0002110744 +11 chany_bottom_in[9]:11 7.533279e-05 +12 chany_bottom_in[9]:12 0.0004918111 +13 chany_bottom_in[9]:13 0.0004918111 +14 chany_bottom_in[9]:14 0.0002307578 +15 chany_bottom_in[9]:15 7.700187e-05 +16 chany_bottom_in[9]:16 7.700187e-05 +17 chany_bottom_in[9]:17 7.091836e-05 +18 chany_bottom_in[9]:18 7.091836e-05 +19 chany_bottom_in[9]:19 0.0007373631 +20 chany_bottom_in[9]:20 0.0004729698 +21 chany_bottom_in[9]:21 0.0007667012 +22 chany_bottom_in[9]:22 0.0028358 +23 chany_bottom_in[9]:23 0.002130997 +24 chany_bottom_in[9]:24 0.0005482342 +25 chany_bottom_in[9]:8 chany_bottom_in[12]:21 4.717354e-06 +26 chany_bottom_in[9]:8 chany_bottom_in[12]:28 0.0008207754 +27 chany_bottom_in[9]:6 chany_bottom_in[12]:25 1.304822e-05 +28 chany_bottom_in[9]:7 chany_bottom_in[12]:27 0.0008207754 +29 chany_bottom_in[9]:7 chany_bottom_in[12]:22 4.717354e-06 +30 chany_bottom_in[9]:5 chany_bottom_in[12]:26 1.304822e-05 +31 chany_bottom_in[9]:21 prog_clk[0]:407 3.38046e-06 +32 chany_bottom_in[9]:21 prog_clk[0]:403 0.0001147512 +33 chany_bottom_in[9]:21 prog_clk[0]:471 3.321195e-05 +34 chany_bottom_in[9]:8 prog_clk[0]:340 6.47456e-07 +35 chany_bottom_in[9]:8 prog_clk[0]:339 3.000709e-06 +36 chany_bottom_in[9]:7 prog_clk[0]:336 3.000709e-06 +37 chany_bottom_in[9]:7 prog_clk[0]:339 6.47456e-07 +38 chany_bottom_in[9]:13 prog_clk[0]:359 6.826017e-06 +39 chany_bottom_in[9]:13 prog_clk[0]:356 4.979271e-06 +40 chany_bottom_in[9]:12 prog_clk[0]:353 4.979271e-06 +41 chany_bottom_in[9]:12 prog_clk[0]:356 6.826017e-06 +42 chany_bottom_in[9]:18 prog_clk[0]:365 1.802456e-05 +43 chany_bottom_in[9]:17 prog_clk[0]:362 1.802456e-05 +44 chany_bottom_in[9]:23 prog_clk[0]:467 1.266041e-06 +45 chany_bottom_in[9]:23 prog_clk[0]:466 3.916174e-05 +46 chany_bottom_in[9]:23 prog_clk[0]:410 1.130505e-05 +47 chany_bottom_in[9]:23 prog_clk[0]:472 3.118683e-05 +48 chany_bottom_in[9]:22 prog_clk[0]:407 1.266041e-06 +49 chany_bottom_in[9]:22 prog_clk[0]:467 4.25422e-05 +50 chany_bottom_in[9]:22 prog_clk[0]:466 1.130505e-05 +51 chany_bottom_in[9]:22 prog_clk[0]:404 0.0001147512 +52 chany_bottom_in[9]:22 prog_clk[0]:472 3.321195e-05 +53 chany_bottom_in[9]:22 prog_clk[0]:471 3.118683e-05 +54 chany_bottom_in[9]:20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.00638e-05 +55 chany_bottom_in[9]:14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.150247e-05 +56 chany_bottom_in[9]:13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.493669e-06 +57 chany_bottom_in[9]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.493669e-06 +58 chany_bottom_in[9]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.150247e-05 +59 chany_bottom_in[9]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.00638e-05 +60 chany_bottom_in[9]:18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.338167e-06 +61 chany_bottom_in[9]:16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.12188e-05 +62 chany_bottom_in[9]:17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.338167e-06 +63 chany_bottom_in[9]:15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.12188e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:24 0.007924108 +1 chany_bottom_in[9]:20 chany_bottom_in[9]:19 0.006941964 +2 chany_bottom_in[9]:21 chany_bottom_in[9]:20 0.0045 +3 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.0045 +4 chany_bottom_in[9]:8 chany_bottom_in[9]:7 0.02845536 +5 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.001569197 +6 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.0045 +7 chany_bottom_in[9]:5 BUFT_P_140:A 0.152 +8 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.0045 +9 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.008116072 +10 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.0003035715 +11 chany_bottom_in[9]:11 chany_bottom_in[9]:4 0.0004665179 +12 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.0045 +13 chany_bottom_in[9]:4 mux_right_track_10\/mux_l2_in_1_:A1 0.152 +14 chany_bottom_in[9]:19 chany_bottom_in[9]:18 0.0045 +15 chany_bottom_in[9]:19 chany_bottom_in[9]:14 0.00365625 +16 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.001133929 +17 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.0008995536 +18 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.0045 +19 chany_bottom_in[9]:15 mux_top_track_24\/mux_l2_in_0_:A0 0.152 +20 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.002013393 +21 chany_bottom_in[9]:23 chany_bottom_in[9]:22 0.04458036 +22 chany_bottom_in[9]:24 chany_bottom_in[9]:23 0.001232143 +23 chany_bottom_in[9]:22 chany_bottom_in[9]:21 0.01730804 + +*END + +*D_NET chany_bottom_in[13] 0.02853624 //LENGTH 225.705 LUMPCC 0.007374123 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 72.220 1.290 +*I BUFT_P_164:A I *L 0.001776 *C 16.560 123.760 +*I mux_top_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 88.420 61.540 +*I mux_right_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 89.340 79.900 +*N chany_bottom_in[13]:4 *C 89.303 79.900 +*N chany_bottom_in[13]:5 *C 88.365 79.900 +*N chany_bottom_in[13]:6 *C 88.320 79.855 +*N chany_bottom_in[13]:7 *C 88.320 61.540 +*N chany_bottom_in[13]:8 *C 88.320 61.540 +*N chany_bottom_in[13]:9 *C 88.780 61.540 +*N chany_bottom_in[13]:10 *C 88.780 55.138 +*N chany_bottom_in[13]:11 *C 88.773 55.080 +*N chany_bottom_in[13]:12 *C 16.560 123.760 +*N chany_bottom_in[13]:13 *C 16.560 123.715 +*N chany_bottom_in[13]:14 *C 16.560 118.378 +*N chany_bottom_in[13]:15 *C 16.568 118.320 +*N chany_bottom_in[13]:16 *C 34.940 118.320 +*N chany_bottom_in[13]:17 *C 34.960 118.312 +*N chany_bottom_in[13]:18 *C 34.960 104.915 +*N chany_bottom_in[13]:19 *C 34.960 55.088 +*N chany_bottom_in[13]:20 *C 34.980 55.080 +*N chany_bottom_in[13]:21 *C 73.600 55.080 +*N chany_bottom_in[13]:22 *C 73.600 55.073 +*N chany_bottom_in[13]:23 *C 73.600 5.448 +*N chany_bottom_in[13]:24 *C 73.580 5.440 +*N chany_bottom_in[13]:25 *C 72.228 5.440 +*N chany_bottom_in[13]:26 *C 72.220 5.383 + +*CAP +0 chany_bottom_in[13] 0.0002510886 +1 BUFT_P_164:A 1e-06 +2 mux_top_track_2\/mux_l2_in_1_:A1 1e-06 +3 mux_right_track_16\/mux_l1_in_1_:A1 1e-06 +4 chany_bottom_in[13]:4 9.671936e-05 +5 chany_bottom_in[13]:5 9.671936e-05 +6 chany_bottom_in[13]:6 0.0009462064 +7 chany_bottom_in[13]:7 3.131579e-05 +8 chany_bottom_in[13]:8 0.0009798878 +9 chany_bottom_in[13]:9 0.0004027641 +10 chany_bottom_in[13]:10 0.0003690826 +11 chany_bottom_in[13]:11 0.001069875 +12 chany_bottom_in[13]:12 3.223199e-05 +13 chany_bottom_in[13]:13 0.0002780793 +14 chany_bottom_in[13]:14 0.0002780793 +15 chany_bottom_in[13]:15 0.001001852 +16 chany_bottom_in[13]:16 0.001001852 +17 chany_bottom_in[13]:17 0.0005996511 +18 chany_bottom_in[13]:18 0.002113172 +19 chany_bottom_in[13]:19 0.001513521 +20 chany_bottom_in[13]:20 0.002005724 +21 chany_bottom_in[13]:21 0.003075599 +22 chany_bottom_in[13]:22 0.002267741 +23 chany_bottom_in[13]:23 0.002267741 +24 chany_bottom_in[13]:24 0.0001145644 +25 chany_bottom_in[13]:25 0.0001145644 +26 chany_bottom_in[13]:26 0.0002510886 +27 chany_bottom_in[13]:22 chany_top_in[14]:22 0.00094872 +28 chany_bottom_in[13]:23 chany_top_in[14]:15 0.00094872 +29 chany_bottom_in[13]:20 chany_top_in[18]:15 0.0005107663 +30 chany_bottom_in[13]:20 chany_top_in[18]:16 0.0002624447 +31 chany_bottom_in[13]:21 chany_top_in[18]:8 0.0002624447 +32 chany_bottom_in[13]:21 chany_top_in[18]:16 0.0005107663 +33 chany_bottom_in[13]:20 chany_bottom_in[5]:25 0.0003667783 +34 chany_bottom_in[13]:21 chany_bottom_in[5]:24 0.0003667783 +35 chany_bottom_in[13]:22 chany_bottom_in[7]:11 0.0003380963 +36 chany_bottom_in[13]:24 chany_bottom_in[7]:13 5.924655e-06 +37 chany_bottom_in[13]:23 chany_bottom_in[7]:12 0.0003380963 +38 chany_bottom_in[13]:25 chany_bottom_in[7]:14 5.924655e-06 +39 chany_bottom_in[13]:19 right_top_grid_pin_42_[0]:15 0.000520582 +40 chany_bottom_in[13]:18 right_top_grid_pin_42_[0]:16 0.000520582 +41 chany_bottom_in[13]:19 right_top_grid_pin_43_[0]:11 0.0006771887 +42 chany_bottom_in[13]:18 right_top_grid_pin_43_[0]:12 0.0006771887 +43 chany_bottom_in[13]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.656061e-05 +44 chany_bottom_in[13]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.656061e-05 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:26 0.003654018 +1 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.005716518 +2 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.00341 +3 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.0008370536 +4 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.0045 +5 chany_bottom_in[13]:4 mux_right_track_16\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[13]:20 chany_bottom_in[13]:19 0.00341 +7 chany_bottom_in[13]:19 chany_bottom_in[13]:18 0.007806308 +8 chany_bottom_in[13]:16 chany_bottom_in[13]:15 0.002878358 +9 chany_bottom_in[13]:17 chany_bottom_in[13]:16 0.00341 +10 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.004765625 +11 chany_bottom_in[13]:15 chany_bottom_in[13]:14 0.00341 +12 chany_bottom_in[13]:12 BUFT_P_164:A 0.152 +13 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.0045 +14 chany_bottom_in[13]:7 mux_top_track_2\/mux_l2_in_1_:A1 0.152 +15 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.0045 +16 chany_bottom_in[13]:8 chany_bottom_in[13]:6 0.01635268 +17 chany_bottom_in[13]:21 chany_bottom_in[13]:20 0.006050466 +18 chany_bottom_in[13]:21 chany_bottom_in[13]:11 0.002377025 +19 chany_bottom_in[13]:22 chany_bottom_in[13]:21 0.00341 +20 chany_bottom_in[13]:24 chany_bottom_in[13]:23 0.00341 +21 chany_bottom_in[13]:23 chany_bottom_in[13]:22 0.007774583 +22 chany_bottom_in[13]:26 chany_bottom_in[13]:25 0.00341 +23 chany_bottom_in[13]:25 chany_bottom_in[13]:24 0.0002118916 +24 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.0004107143 +25 chany_bottom_in[13]:18 chany_bottom_in[13]:17 0.002098941 + +*END + +*D_NET chany_bottom_in[18] 0.01041326 //LENGTH 99.150 LUMPCC 0.001554681 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 26.680 1.290 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 30.995 58.820 +*I mux_top_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 28.060 88.740 +*I FTB_31__30:A I *L 0.001776 *C 25.760 91.120 +*N chany_bottom_in[18]:4 *C 25.798 91.120 +*N chany_bottom_in[18]:5 *C 26.635 91.120 +*N chany_bottom_in[18]:6 *C 26.680 91.075 +*N chany_bottom_in[18]:7 *C 28.023 88.740 +*N chany_bottom_in[18]:8 *C 26.725 88.740 +*N chany_bottom_in[18]:9 *C 26.680 88.740 +*N chany_bottom_in[18]:10 *C 30.958 58.820 +*N chany_bottom_in[18]:11 *C 26.725 58.820 +*N chany_bottom_in[18]:12 *C 26.680 58.865 +*N chany_bottom_in[18]:13 *C 26.220 58.820 +*N chany_bottom_in[18]:14 *C 26.220 53.670 +*N chany_bottom_in[18]:15 *C 26.220 3.740 +*N chany_bottom_in[18]:16 *C 26.680 3.740 + +*CAP +0 chany_bottom_in[18] 0.0001440849 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24\/mux_l2_in_1_:A1 1e-06 +3 FTB_31__30:A 1e-06 +4 chany_bottom_in[18]:4 5.967392e-05 +5 chany_bottom_in[18]:5 5.967392e-05 +6 chany_bottom_in[18]:6 0.0001314714 +7 chany_bottom_in[18]:7 9.965298e-05 +8 chany_bottom_in[18]:8 9.965298e-05 +9 chany_bottom_in[18]:9 0.001633943 +10 chany_bottom_in[18]:10 0.000220615 +11 chany_bottom_in[18]:11 0.000220615 +12 chany_bottom_in[18]:12 0.001507421 +13 chany_bottom_in[18]:13 0.00023812 +14 chany_bottom_in[18]:14 0.00222157 +15 chany_bottom_in[18]:15 0.002046179 +16 chany_bottom_in[18]:16 0.0001729092 +17 chany_bottom_in[18]:15 chany_bottom_in[19] 0.000317343 +18 chany_bottom_in[18]:14 chany_bottom_in[19]:4 0.000317343 +19 chany_bottom_in[18]:9 mux_tree_tapbuf_size4_0_sram[1]:6 5.896682e-05 +20 chany_bottom_in[18]:9 mux_tree_tapbuf_size4_0_sram[1]:9 0.000169787 +21 chany_bottom_in[18]:12 mux_tree_tapbuf_size4_0_sram[1]:8 0.000169787 +22 chany_bottom_in[18]:12 mux_tree_tapbuf_size4_0_sram[1]:9 5.896682e-05 +23 chany_bottom_in[18]:9 mux_tree_tapbuf_size4_6_sram[1]:17 1.258489e-05 +24 chany_bottom_in[18]:11 mux_tree_tapbuf_size4_6_sram[1]:14 1.783512e-05 +25 chany_bottom_in[18]:11 mux_tree_tapbuf_size4_6_sram[1]:15 3.839504e-05 +26 chany_bottom_in[18]:12 mux_tree_tapbuf_size4_6_sram[1]:16 1.258489e-05 +27 chany_bottom_in[18]:10 mux_tree_tapbuf_size4_6_sram[1]:4 3.839504e-05 +28 chany_bottom_in[18]:10 mux_tree_tapbuf_size4_6_sram[1]:15 1.783512e-05 +29 chany_bottom_in[18]:15 mux_tree_tapbuf_size4_6_sram[1]:7 1.396229e-05 +30 chany_bottom_in[18]:15 mux_tree_tapbuf_size4_6_sram[1]:12 8.550598e-05 +31 chany_bottom_in[18]:13 mux_tree_tapbuf_size4_6_sram[1]:13 6.276357e-05 +32 chany_bottom_in[18]:13 mux_tree_tapbuf_size4_6_sram[1]:17 1.9711e-07 +33 chany_bottom_in[18]:14 mux_tree_tapbuf_size4_6_sram[1]:8 1.396229e-05 +34 chany_bottom_in[18]:14 mux_tree_tapbuf_size4_6_sram[1]:12 6.276357e-05 +35 chany_bottom_in[18]:14 mux_tree_tapbuf_size4_6_sram[1]:13 8.550598e-05 +36 chany_bottom_in[18]:14 mux_tree_tapbuf_size4_6_sram[1]:16 1.9711e-07 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:16 0.0021875 +1 chany_bottom_in[18]:7 mux_top_track_24\/mux_l2_in_1_:A1 0.152 +2 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.001158482 +3 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.0045 +4 chany_bottom_in[18]:9 chany_bottom_in[18]:6 0.002084822 +5 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.003779018 +6 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.0045 +7 chany_bottom_in[18]:12 chany_bottom_in[18]:9 0.02667411 +8 chany_bottom_in[18]:10 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +9 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.0007477679 +10 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.0045 +11 chany_bottom_in[18]:4 FTB_31__30:A 0.152 +12 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.04458036 +13 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.0004107143 +14 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.0004107143 +15 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.004598215 + +*END + +*D_NET chany_top_in[1] 0.004277516 //LENGTH 34.395 LUMPCC 0.0008070382 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 62.100 129.270 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 67.720 101.660 +*N chany_top_in[1]:2 *C 67.683 101.660 +*N chany_top_in[1]:3 *C 66.285 101.660 +*N chany_top_in[1]:4 *C 66.240 101.705 +*N chany_top_in[1]:5 *C 66.240 104.663 +*N chany_top_in[1]:6 *C 66.233 104.720 +*N chany_top_in[1]:7 *C 62.108 104.720 +*N chany_top_in[1]:8 *C 62.100 104.778 + +*CAP +0 chany_top_in[1] 0.001267077 +1 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[1]:2 0.0001260014 +3 chany_top_in[1]:3 0.0001260014 +4 chany_top_in[1]:4 0.0001554626 +5 chany_top_in[1]:5 0.0001554626 +6 chany_top_in[1]:6 0.0001861978 +7 chany_top_in[1]:7 0.0001861978 +8 chany_top_in[1]:8 0.001267077 +9 chany_top_in[1]:2 chany_top_in[5]:4 3.069353e-07 +10 chany_top_in[1]:3 chany_top_in[5]:5 3.069353e-07 +11 chany_top_in[1]:4 chany_top_in[5]:6 9.966855e-06 +12 chany_top_in[1]:4 chany_top_in[5]:20 1.627878e-05 +13 chany_top_in[1]:5 chany_top_in[5]:20 9.966855e-06 +14 chany_top_in[1]:5 chany_top_in[5]:21 1.627878e-05 +15 chany_top_in[1]:6 chany_top_in[5]:22 0.0002469371 +16 chany_top_in[1]:7 chany_top_in[5]:23 0.0002469371 +17 chany_top_in[1] mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.008799e-05 +18 chany_top_in[1]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.008799e-05 +19 chany_top_in[1] mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.994144e-05 +20 chany_top_in[1]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.994144e-05 + +*RES +0 chany_top_in[1] chany_top_in[1]:8 0.0218683 +1 chany_top_in[1]:2 mux_right_track_4\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[1]:3 chany_top_in[1]:2 0.001247768 +3 chany_top_in[1]:4 chany_top_in[1]:3 0.0045 +4 chany_top_in[1]:5 chany_top_in[1]:4 0.002640625 +5 chany_top_in[1]:6 chany_top_in[1]:5 0.00341 +6 chany_top_in[1]:8 chany_top_in[1]:7 0.00341 +7 chany_top_in[1]:7 chany_top_in[1]:6 0.00064625 + +*END + +*D_NET chanx_right_in[2] 0.003049509 //LENGTH 25.620 LUMPCC 0 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 111.930 55.760 +*I mux_top_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 100.645 52.700 +*I mux_bottom_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 101.105 45.220 +*N chanx_right_in[2]:3 *C 101.142 45.220 +*N chanx_right_in[2]:4 *C 102.995 45.220 +*N chanx_right_in[2]:5 *C 103.040 45.265 +*N chanx_right_in[2]:6 *C 103.040 46.920 +*N chanx_right_in[2]:7 *C 103.500 46.920 +*N chanx_right_in[2]:8 *C 100.683 52.700 +*N chanx_right_in[2]:9 *C 103.455 52.700 +*N chanx_right_in[2]:10 *C 103.500 52.700 +*N chanx_right_in[2]:11 *C 103.500 55.703 +*N chanx_right_in[2]:12 *C 103.508 55.760 + +*CAP +0 chanx_right_in[2] 0.0005577688 +1 mux_top_track_2\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_9\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[2]:3 0.0001452692 +4 chanx_right_in[2]:4 0.0001452692 +5 chanx_right_in[2]:5 0.0001094563 +6 chanx_right_in[2]:6 0.0001404682 +7 chanx_right_in[2]:7 0.0003371296 +8 chanx_right_in[2]:8 0.0002003902 +9 chanx_right_in[2]:9 0.0002003902 +10 chanx_right_in[2]:10 0.0004938947 +11 chanx_right_in[2]:11 0.0001597042 +12 chanx_right_in[2]:12 0.0005577688 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:12 0.001319525 +1 chanx_right_in[2]:4 chanx_right_in[2]:3 0.001654018 +2 chanx_right_in[2]:5 chanx_right_in[2]:4 0.0045 +3 chanx_right_in[2]:3 mux_bottom_track_9\/mux_l1_in_1_:A1 0.152 +4 chanx_right_in[2]:9 chanx_right_in[2]:8 0.002475447 +5 chanx_right_in[2]:10 chanx_right_in[2]:9 0.0045 +6 chanx_right_in[2]:10 chanx_right_in[2]:7 0.005160714 +7 chanx_right_in[2]:8 mux_top_track_2\/mux_l1_in_0_:A1 0.152 +8 chanx_right_in[2]:11 chanx_right_in[2]:10 0.002680804 +9 chanx_right_in[2]:12 chanx_right_in[2]:11 0.00341 +10 chanx_right_in[2]:6 chanx_right_in[2]:5 0.001477679 +11 chanx_right_in[2]:7 chanx_right_in[2]:6 0.0004107143 + +*END + +*D_NET chanx_right_in[5] 0.01519415 //LENGTH 99.425 LUMPCC 0.006630672 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 111.930 95.200 +*I mux_bottom_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 50.965 66.980 +*I mux_top_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 47.380 69.020 +*N chanx_right_in[5]:3 *C 47.403 69.047 +*N chanx_right_in[5]:4 *C 47.415 69.360 +*N chanx_right_in[5]:5 *C 50.555 69.360 +*N chanx_right_in[5]:6 *C 50.600 69.315 +*N chanx_right_in[5]:7 *C 50.950 66.980 +*N chanx_right_in[5]:8 *C 50.623 66.980 +*N chanx_right_in[5]:9 *C 50.600 66.980 +*N chanx_right_in[5]:10 *C 50.600 67.377 +*N chanx_right_in[5]:11 *C 50.608 67.320 +*N chanx_right_in[5]:12 *C 101.180 67.320 +*N chanx_right_in[5]:13 *C 101.200 67.328 +*N chanx_right_in[5]:14 *C 101.200 95.873 +*N chanx_right_in[5]:15 *C 101.220 95.880 +*N chanx_right_in[5]:16 *C 108.100 95.880 +*N chanx_right_in[5]:17 *C 108.100 95.200 + +*CAP +0 chanx_right_in[5] 9.136975e-05 +1 mux_bottom_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_16\/mux_l1_in_0_:A1 1e-06 +3 chanx_right_in[5]:3 3.027149e-05 +4 chanx_right_in[5]:4 0.0002342067 +5 chanx_right_in[5]:5 0.0002039352 +6 chanx_right_in[5]:6 9.207045e-05 +7 chanx_right_in[5]:7 4.509323e-05 +8 chanx_right_in[5]:8 4.509323e-05 +9 chanx_right_in[5]:9 4.312241e-05 +10 chanx_right_in[5]:10 0.0001062626 +11 chanx_right_in[5]:11 0.002267822 +12 chanx_right_in[5]:12 0.002267822 +13 chanx_right_in[5]:13 0.001163497 +14 chanx_right_in[5]:14 0.001163497 +15 chanx_right_in[5]:15 0.0003133334 +16 chanx_right_in[5]:16 0.0003580209 +17 chanx_right_in[5]:17 0.0001360573 +18 chanx_right_in[5]:11 chany_bottom_in[14]:16 0.0004542963 +19 chanx_right_in[5]:12 chany_bottom_in[14]:11 0.0004542963 +20 chanx_right_in[5] chanx_right_in[4] 0.000100748 +21 chanx_right_in[5]:13 chanx_right_in[4]:16 0.0003681426 +22 chanx_right_in[5]:15 chanx_right_in[4]:18 6.428534e-05 +23 chanx_right_in[5]:14 chanx_right_in[4]:17 0.0003681426 +24 chanx_right_in[5]:16 chanx_right_in[4] 6.428534e-05 +25 chanx_right_in[5]:17 chanx_right_in[4]:18 0.000100748 +26 chanx_right_in[5] chanx_right_in[12] 9.211986e-05 +27 chanx_right_in[5]:5 chanx_right_in[12]:7 2.588458e-05 +28 chanx_right_in[5]:6 chanx_right_in[12]:8 6.146898e-05 +29 chanx_right_in[5]:9 chanx_right_in[12]:8 1.081902e-05 +30 chanx_right_in[5]:10 chanx_right_in[12]:5 7.2288e-05 +31 chanx_right_in[5]:13 chanx_right_in[12]:12 8.724882e-06 +32 chanx_right_in[5]:15 chanx_right_in[12]:14 0.0004031553 +33 chanx_right_in[5]:14 chanx_right_in[12]:13 8.724882e-06 +34 chanx_right_in[5]:4 chanx_right_in[12]:6 2.588458e-05 +35 chanx_right_in[5]:16 chanx_right_in[12] 0.0004031553 +36 chanx_right_in[5]:17 chanx_right_in[12]:14 9.211986e-05 +37 chanx_right_in[5]:11 chanx_right_in[18]:18 0.0003326026 +38 chanx_right_in[5]:12 chanx_right_in[18] 0.0003326026 +39 chanx_right_in[5]:11 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001393089 +40 chanx_right_in[5]:12 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001393089 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:17 0.0006000333 +1 chanx_right_in[5]:5 chanx_right_in[5]:4 0.002803572 +2 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +3 chanx_right_in[5]:3 mux_top_track_16\/mux_l1_in_0_:A1 0.152 +4 chanx_right_in[5]:7 mux_bottom_track_1\/mux_l1_in_1_:A1 0.152 +5 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0001779891 +6 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0045 +7 chanx_right_in[5]:10 chanx_right_in[5]:9 0.0001057692 +8 chanx_right_in[5]:10 chanx_right_in[5]:6 0.001729911 +9 chanx_right_in[5]:11 chanx_right_in[5]:10 0.00341 +10 chanx_right_in[5]:12 chanx_right_in[5]:11 0.007923025 +11 chanx_right_in[5]:13 chanx_right_in[5]:12 0.00341 +12 chanx_right_in[5]:15 chanx_right_in[5]:14 0.00341 +13 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00447205 +14 chanx_right_in[5]:4 chanx_right_in[5]:3 0.0002111487 +15 chanx_right_in[5]:16 chanx_right_in[5]:15 0.001077867 +16 chanx_right_in[5]:17 chanx_right_in[5]:16 0.0001065333 + +*END + +*D_NET chanx_right_in[11] 0.008141081 //LENGTH 61.305 LUMPCC 0.003198099 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 111.930 38.080 +*I mux_bottom_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 72.050 44.540 +*I mux_top_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 70.285 56.100 +*N chanx_right_in[11]:3 *C 70.285 56.100 +*N chanx_right_in[11]:4 *C 70.380 56.055 +*N chanx_right_in[11]:5 *C 70.380 46.965 +*N chanx_right_in[11]:6 *C 70.425 46.920 +*N chanx_right_in[11]:7 *C 72.175 46.920 +*N chanx_right_in[11]:8 *C 72.220 46.875 +*N chanx_right_in[11]:9 *C 72.050 44.540 +*N chanx_right_in[11]:10 *C 72.220 44.200 +*N chanx_right_in[11]:11 *C 72.220 44.200 +*N chanx_right_in[11]:12 *C 72.220 38.138 +*N chanx_right_in[11]:13 *C 72.228 38.080 + +*CAP +0 chanx_right_in[11] 0.001399316 +1 mux_bottom_track_3\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_8\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[11]:3 2.98581e-05 +4 chanx_right_in[11]:4 0.0003562018 +5 chanx_right_in[11]:5 0.0003562018 +6 chanx_right_in[11]:6 0.0001541445 +7 chanx_right_in[11]:7 0.0001541445 +8 chanx_right_in[11]:8 0.0001555096 +9 chanx_right_in[11]:9 6.446383e-05 +10 chanx_right_in[11]:10 6.953966e-05 +11 chanx_right_in[11]:11 0.0004954056 +12 chanx_right_in[11]:12 0.0003068799 +13 chanx_right_in[11]:13 0.001399316 +14 chanx_right_in[11]:4 chany_top_in[16]:35 0.000248777 +15 chanx_right_in[11]:5 chany_top_in[16]:34 0.000248777 +16 chanx_right_in[11]:8 chany_top_in[16]:35 1.360683e-05 +17 chanx_right_in[11]:11 chany_top_in[16]:34 4.855469e-05 +18 chanx_right_in[11]:11 chany_top_in[16]:35 1.071517e-05 +19 chanx_right_in[11]:12 chany_top_in[16]:31 3.494786e-05 +20 chanx_right_in[11]:12 chany_top_in[16]:34 1.071517e-05 +21 chanx_right_in[11] chanx_right_in[10] 0.0005244312 +22 chanx_right_in[11]:13 chanx_right_in[10]:11 0.0005244312 +23 chanx_right_in[11] chanx_right_in[16] 0.0003280071 +24 chanx_right_in[11] chanx_right_in[16]:11 9.411105e-05 +25 chanx_right_in[11]:13 chanx_right_in[16]:6 9.411105e-05 +26 chanx_right_in[11]:13 chanx_right_in[16]:12 0.0003280071 +27 chanx_right_in[11] mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.413433e-05 +28 chanx_right_in[11] mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000290319 +29 chanx_right_in[11]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000290319 +30 chanx_right_in[11]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.413433e-05 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:13 0.006220058 +1 chanx_right_in[11]:3 mux_top_track_8\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[11]:4 chanx_right_in[11]:3 0.0045 +3 chanx_right_in[11]:6 chanx_right_in[11]:5 0.0045 +4 chanx_right_in[11]:5 chanx_right_in[11]:4 0.008116072 +5 chanx_right_in[11]:7 chanx_right_in[11]:6 0.0015625 +6 chanx_right_in[11]:8 chanx_right_in[11]:7 0.0045 +7 chanx_right_in[11]:9 mux_bottom_track_3\/mux_l1_in_1_:A0 0.152 +8 chanx_right_in[11]:10 chanx_right_in[11]:9 0.0001976745 +9 chanx_right_in[11]:11 chanx_right_in[11]:10 0.0045 +10 chanx_right_in[11]:11 chanx_right_in[11]:8 0.002388393 +11 chanx_right_in[11]:12 chanx_right_in[11]:11 0.005412946 +12 chanx_right_in[11]:13 chanx_right_in[11]:12 0.00341 + +*END + +*D_NET chanx_right_in[19] 0.01614688 //LENGTH 108.440 LUMPCC 0.00830962 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 111.930 31.280 +*I mux_bottom_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 49.220 30.940 +*I mux_top_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 39.925 66.980 +*N chanx_right_in[19]:3 *C 39.925 66.980 +*N chanx_right_in[19]:4 *C 40.020 66.935 +*N chanx_right_in[19]:5 *C 40.020 31.338 +*N chanx_right_in[19]:6 *C 40.028 31.280 +*N chanx_right_in[19]:7 *C 49.220 30.940 +*N chanx_right_in[19]:8 *C 49.220 30.940 +*N chanx_right_in[19]:9 *C 49.220 31.280 +*N chanx_right_in[19]:10 *C 49.220 31.280 +*N chanx_right_in[19]:11 *C 99.220 31.280 + +*CAP +0 chanx_right_in[19] 0.0004242683 +1 mux_bottom_track_1\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[19]:3 2.675223e-05 +4 chanx_right_in[19]:4 0.001667418 +5 chanx_right_in[19]:5 0.001667418 +6 chanx_right_in[19]:6 0.0004528009 +7 chanx_right_in[19]:7 3.330337e-05 +8 chanx_right_in[19]:8 4.711009e-05 +9 chanx_right_in[19]:9 5.134634e-05 +10 chanx_right_in[19]:10 0.00174669 +11 chanx_right_in[19]:11 0.001718157 +12 chanx_right_in[19] chany_bottom_in[11]:15 4.517857e-05 +13 chanx_right_in[19]:10 chany_bottom_in[11]:16 0.0002315611 +14 chanx_right_in[19]:10 chany_bottom_in[11]:17 5.654439e-05 +15 chanx_right_in[19]:10 chany_bottom_in[11]:18 3.585478e-07 +16 chanx_right_in[19]:6 chany_bottom_in[11]:18 5.654439e-05 +17 chanx_right_in[19]:11 chany_bottom_in[11]:15 0.0002315611 +18 chanx_right_in[19]:11 chany_bottom_in[11]:16 4.517857e-05 +19 chanx_right_in[19]:11 chany_bottom_in[11]:17 3.585478e-07 +20 chanx_right_in[19] chanx_right_in[13] 0.0003195047 +21 chanx_right_in[19]:10 chanx_right_in[13]:12 0.0001020369 +22 chanx_right_in[19]:10 chanx_right_in[13]:13 0.000107396 +23 chanx_right_in[19]:10 chanx_right_in[13]:14 0.0009120154 +24 chanx_right_in[19]:6 chanx_right_in[13]:12 0.000107396 +25 chanx_right_in[19]:11 chanx_right_in[13] 0.0009120154 +26 chanx_right_in[19]:11 chanx_right_in[13]:13 0.0001020369 +27 chanx_right_in[19]:11 chanx_right_in[13]:14 0.0003195047 +28 chanx_right_in[19]:8 bottom_left_grid_pin_1_[0]:6 8.111515e-06 +29 chanx_right_in[19]:9 bottom_left_grid_pin_1_[0]:18 8.111515e-06 +30 chanx_right_in[19]:10 bottom_left_grid_pin_1_[0]:19 8.427329e-06 +31 chanx_right_in[19]:10 bottom_left_grid_pin_1_[0]:17 0.002016588 +32 chanx_right_in[19]:10 bottom_left_grid_pin_1_[0]:16 3.316542e-05 +33 chanx_right_in[19]:6 bottom_left_grid_pin_1_[0]:20 8.427329e-06 +34 chanx_right_in[19]:6 bottom_left_grid_pin_1_[0]:17 3.316542e-05 +35 chanx_right_in[19]:11 bottom_left_grid_pin_1_[0]:16 0.002016588 +36 chanx_right_in[19]:5 mux_tree_tapbuf_size2_0_sram[0]:5 4.259799e-07 +37 chanx_right_in[19]:5 mux_tree_tapbuf_size2_0_sram[0]:10 0.0001119875 +38 chanx_right_in[19]:4 mux_tree_tapbuf_size2_0_sram[0]:6 4.259799e-07 +39 chanx_right_in[19]:4 mux_tree_tapbuf_size2_0_sram[0]:9 0.0001119875 +40 chanx_right_in[19]:5 mux_tree_tapbuf_size2_0_sram[1]:8 7.362734e-05 +41 chanx_right_in[19]:5 mux_tree_tapbuf_size2_0_sram[1]:7 0.0001278815 +42 chanx_right_in[19]:4 mux_tree_tapbuf_size2_0_sram[1]:5 0.0001278815 +43 chanx_right_in[19]:4 mux_tree_tapbuf_size2_0_sram[1]:7 7.362734e-05 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:11 0.001991233 +1 chanx_right_in[19]:7 mux_bottom_track_1\/mux_l1_in_2_:A1 0.152 +2 chanx_right_in[19]:8 chanx_right_in[19]:7 0.0045 +3 chanx_right_in[19]:9 chanx_right_in[19]:8 0.0001634615 +4 chanx_right_in[19]:10 chanx_right_in[19]:9 0.00341 +5 chanx_right_in[19]:10 chanx_right_in[19]:6 0.001440158 +6 chanx_right_in[19]:5 chanx_right_in[19]:4 0.03178349 +7 chanx_right_in[19]:6 chanx_right_in[19]:5 0.00341 +8 chanx_right_in[19]:3 mux_top_track_16\/mux_l1_in_1_:A1 0.152 +9 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +10 chanx_right_in[19]:11 chanx_right_in[19]:10 0.007833333 + +*END + +*D_NET ccff_head[0] 0.002943559 //LENGTH 24.590 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 111.930 88.400 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 99.075 77.180 +*N ccff_head[0]:2 *C 99.075 77.180 +*N ccff_head[0]:3 *C 99.360 77.180 +*N ccff_head[0]:4 *C 99.360 77.225 +*N ccff_head[0]:5 *C 99.360 88.343 +*N ccff_head[0]:6 *C 99.368 88.400 + +*CAP +0 ccff_head[0] 0.0007898179 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 5.036339e-05 +3 ccff_head[0]:3 5.288864e-05 +4 ccff_head[0]:4 0.0006298355 +5 ccff_head[0]:5 0.0006298355 +6 ccff_head[0]:6 0.0007898179 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.001968125 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001548913 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:5 ccff_head[0]:4 0.00992634 +5 ccff_head[0]:6 ccff_head[0]:5 0.00341 + +*END + +*D_NET chanx_right_out[1] 0.00194591 //LENGTH 17.180 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 105.860 93.500 +*P chanx_right_out[1] O *L 0.7423 *C 111.930 82.960 +*N chanx_right_out[1]:2 *C 105.808 82.960 +*N chanx_right_out[1]:3 *C 105.800 83.017 +*N chanx_right_out[1]:4 *C 105.800 93.455 +*N chanx_right_out[1]:5 *C 105.800 93.500 + +*CAP +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[1] 0.0004149843 +2 chanx_right_out[1]:2 0.0004149843 +3 chanx_right_out[1]:3 0.0005427408 +4 chanx_right_out[1]:4 0.0005427408 +5 chanx_right_out[1]:5 2.945985e-05 + +*RES +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[1]:5 0.152 +1 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +2 chanx_right_out[1]:4 chanx_right_out[1]:3 0.009319196 +3 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +4 chanx_right_out[1]:2 chanx_right_out[1] 0.0009591916 + +*END + +*D_NET chanx_right_out[9] 0.001467862 //LENGTH 10.660 LUMPCC 0.000285668 DR + +*CONN +*I mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.480 66.300 +*P chanx_right_out[9] O *L 0.7423 *C 111.863 63.920 +*N chanx_right_out[9]:2 *C 111.780 63.920 +*N chanx_right_out[9]:3 *C 111.780 63.978 +*N chanx_right_out[9]:4 *C 111.780 66.255 +*N chanx_right_out[9]:5 *C 111.735 66.300 +*N chanx_right_out[9]:6 *C 104.517 66.300 + +*CAP +0 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[9] 3.357479e-05 +2 chanx_right_out[9]:2 3.357479e-05 +3 chanx_right_out[9]:3 0.0001666839 +4 chanx_right_out[9]:4 0.0001666839 +5 chanx_right_out[9]:5 0.0003903384 +6 chanx_right_out[9]:6 0.0003903384 +7 chanx_right_out[9]:6 ropt_net_233:2 0.000142834 +8 chanx_right_out[9]:5 ropt_net_233:3 0.000142834 + +*RES +0 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[9]:6 0.152 +1 chanx_right_out[9]:6 chanx_right_out[9]:5 0.006444196 +2 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0045 +3 chanx_right_out[9]:4 chanx_right_out[9]:3 0.002033482 +4 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +5 chanx_right_out[9]:2 chanx_right_out[9] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.001514377 //LENGTH 10.575 LUMPCC 0.0004030176 DR + +*CONN +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 40.785 55.760 +*I mem_right_track_26\/FTB_28__58:A I *L 0.001746 *C 40.480 58.480 +*I mux_right_track_26\/mux_l2_in_0_:S I *L 0.00357 *C 42.660 63.240 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 42.623 63.240 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 40.525 63.240 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 40.480 63.195 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 40.480 58.480 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 40.480 58.480 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 40.480 55.805 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 40.480 55.760 +*N mux_tree_tapbuf_size2_0_sram[1]:10 *C 40.785 55.760 + +*CAP +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_26\/FTB_28__58:A 1e-06 +2 mux_right_track_26\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 0.0001715212 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0001715212 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.0001863872 +6 mux_tree_tapbuf_size2_0_sram[1]:6 3.37489e-05 +7 mux_tree_tapbuf_size2_0_sram[1]:7 0.000330582 +8 mux_tree_tapbuf_size2_0_sram[1]:8 0.0001122582 +9 mux_tree_tapbuf_size2_0_sram[1]:9 5.223582e-05 +10 mux_tree_tapbuf_size2_0_sram[1]:10 5.010453e-05 +11 mux_tree_tapbuf_size2_0_sram[1]:5 chanx_right_in[19]:4 0.0001278815 +12 mux_tree_tapbuf_size2_0_sram[1]:8 chanx_right_in[19]:5 7.362734e-05 +13 mux_tree_tapbuf_size2_0_sram[1]:7 chanx_right_in[19]:4 7.362734e-05 +14 mux_tree_tapbuf_size2_0_sram[1]:7 chanx_right_in[19]:5 0.0001278815 + +*RES +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.001872768 +2 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size2_0_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_0_sram[1]:3 mux_right_track_26\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 0.0045 +5 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.002388393 +6 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:9 0.0001657609 +7 mux_tree_tapbuf_size2_0_sram[1]:6 mem_right_track_26\/FTB_28__58:A 0.152 +8 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0045 +9 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:5 0.004209822 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[1] 0.004223085 //LENGTH 32.795 LUMPCC 0.00010494 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 46.765 112.880 +*I mux_right_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 35.320 101.320 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 34.215 107.780 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 44.720 105.015 +*N mux_tree_tapbuf_size4_2_sram[1]:4 *C 44.720 105.015 +*N mux_tree_tapbuf_size4_2_sram[1]:5 *C 34.253 107.780 +*N mux_tree_tapbuf_size4_2_sram[1]:6 *C 34.915 107.780 +*N mux_tree_tapbuf_size4_2_sram[1]:7 *C 34.960 107.735 +*N mux_tree_tapbuf_size4_2_sram[1]:8 *C 35.305 101.320 +*N mux_tree_tapbuf_size4_2_sram[1]:9 *C 34.983 101.320 +*N mux_tree_tapbuf_size4_2_sram[1]:10 *C 34.960 101.365 +*N mux_tree_tapbuf_size4_2_sram[1]:11 *C 34.960 102.680 +*N mux_tree_tapbuf_size4_2_sram[1]:12 *C 35.005 102.680 +*N mux_tree_tapbuf_size4_2_sram[1]:13 *C 37.215 102.680 +*N mux_tree_tapbuf_size4_2_sram[1]:14 *C 37.260 102.725 +*N mux_tree_tapbuf_size4_2_sram[1]:15 *C 37.260 105.355 +*N mux_tree_tapbuf_size4_2_sram[1]:16 *C 37.305 105.400 +*N mux_tree_tapbuf_size4_2_sram[1]:17 *C 44.720 105.400 +*N mux_tree_tapbuf_size4_2_sram[1]:18 *C 46.875 105.400 +*N mux_tree_tapbuf_size4_2_sram[1]:19 *C 46.920 105.445 +*N mux_tree_tapbuf_size4_2_sram[1]:20 *C 46.920 112.835 +*N mux_tree_tapbuf_size4_2_sram[1]:21 *C 46.920 112.880 +*N mux_tree_tapbuf_size4_2_sram[1]:22 *C 46.765 112.880 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_8\/mux_l2_in_1_:S 1e-06 +2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_8\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_2_sram[1]:4 5.881155e-05 +5 mux_tree_tapbuf_size4_2_sram[1]:5 7.469771e-05 +6 mux_tree_tapbuf_size4_2_sram[1]:6 7.469771e-05 +7 mux_tree_tapbuf_size4_2_sram[1]:7 0.0002994449 +8 mux_tree_tapbuf_size4_2_sram[1]:8 6.198143e-05 +9 mux_tree_tapbuf_size4_2_sram[1]:9 6.198143e-05 +10 mux_tree_tapbuf_size4_2_sram[1]:10 9.630734e-05 +11 mux_tree_tapbuf_size4_2_sram[1]:11 0.0004259731 +12 mux_tree_tapbuf_size4_2_sram[1]:12 0.0001735929 +13 mux_tree_tapbuf_size4_2_sram[1]:13 0.0001735929 +14 mux_tree_tapbuf_size4_2_sram[1]:14 0.0001692756 +15 mux_tree_tapbuf_size4_2_sram[1]:15 0.0001692756 +16 mux_tree_tapbuf_size4_2_sram[1]:16 0.0004994056 +17 mux_tree_tapbuf_size4_2_sram[1]:17 0.0006942558 +18 mux_tree_tapbuf_size4_2_sram[1]:18 0.0001647413 +19 mux_tree_tapbuf_size4_2_sram[1]:19 0.0004033486 +20 mux_tree_tapbuf_size4_2_sram[1]:20 0.0004033486 +21 mux_tree_tapbuf_size4_2_sram[1]:21 5.6738e-05 +22 mux_tree_tapbuf_size4_2_sram[1]:22 5.26748e-05 +23 mux_tree_tapbuf_size4_2_sram[1]:16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.118796e-05 +24 mux_tree_tapbuf_size4_2_sram[1]:16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.128202e-05 +25 mux_tree_tapbuf_size4_2_sram[1]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.128202e-05 +26 mux_tree_tapbuf_size4_2_sram[1]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.118796e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_2_sram[1]:22 0.152 +1 mux_tree_tapbuf_size4_2_sram[1]:12 mux_tree_tapbuf_size4_2_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size4_2_sram[1]:11 mux_tree_tapbuf_size4_2_sram[1]:10 0.001174107 +3 mux_tree_tapbuf_size4_2_sram[1]:11 mux_tree_tapbuf_size4_2_sram[1]:7 0.004513393 +4 mux_tree_tapbuf_size4_2_sram[1]:13 mux_tree_tapbuf_size4_2_sram[1]:12 0.001973215 +5 mux_tree_tapbuf_size4_2_sram[1]:14 mux_tree_tapbuf_size4_2_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size4_2_sram[1]:16 mux_tree_tapbuf_size4_2_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size4_2_sram[1]:15 mux_tree_tapbuf_size4_2_sram[1]:14 0.002348214 +8 mux_tree_tapbuf_size4_2_sram[1]:18 mux_tree_tapbuf_size4_2_sram[1]:17 0.001924107 +9 mux_tree_tapbuf_size4_2_sram[1]:19 mux_tree_tapbuf_size4_2_sram[1]:18 0.0045 +10 mux_tree_tapbuf_size4_2_sram[1]:21 mux_tree_tapbuf_size4_2_sram[1]:20 0.0045 +11 mux_tree_tapbuf_size4_2_sram[1]:20 mux_tree_tapbuf_size4_2_sram[1]:19 0.006598215 +12 mux_tree_tapbuf_size4_2_sram[1]:22 mux_tree_tapbuf_size4_2_sram[1]:21 8.423914e-05 +13 mux_tree_tapbuf_size4_2_sram[1]:6 mux_tree_tapbuf_size4_2_sram[1]:5 0.0005915179 +14 mux_tree_tapbuf_size4_2_sram[1]:7 mux_tree_tapbuf_size4_2_sram[1]:6 0.0045 +15 mux_tree_tapbuf_size4_2_sram[1]:5 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size4_2_sram[1]:8 mux_right_track_8\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size4_2_sram[1]:9 mux_tree_tapbuf_size4_2_sram[1]:8 0.0001752718 +18 mux_tree_tapbuf_size4_2_sram[1]:10 mux_tree_tapbuf_size4_2_sram[1]:9 0.0045 +19 mux_tree_tapbuf_size4_2_sram[1]:4 mux_right_track_8\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size4_2_sram[1]:17 mux_tree_tapbuf_size4_2_sram[1]:16 0.006620536 +21 mux_tree_tapbuf_size4_2_sram[1]:17 mux_tree_tapbuf_size4_2_sram[1]:4 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[1] 0.003596728 //LENGTH 29.315 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 101.505 55.760 +*I mux_top_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 94.860 53.040 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 86.655 55.420 +*I mux_top_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 89.140 61.200 +*N mux_tree_tapbuf_size5_0_sram[1]:4 *C 89.103 61.200 +*N mux_tree_tapbuf_size5_0_sram[1]:5 *C 86.525 61.200 +*N mux_tree_tapbuf_size5_0_sram[1]:6 *C 86.480 61.155 +*N mux_tree_tapbuf_size5_0_sram[1]:7 *C 86.655 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:8 *C 86.480 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:9 *C 86.480 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:10 *C 86.480 55.818 +*N mux_tree_tapbuf_size5_0_sram[1]:11 *C 86.487 55.760 +*N mux_tree_tapbuf_size5_0_sram[1]:12 *C 94.760 53.040 +*N mux_tree_tapbuf_size5_0_sram[1]:13 *C 94.760 53.085 +*N mux_tree_tapbuf_size5_0_sram[1]:14 *C 94.760 55.703 +*N mux_tree_tapbuf_size5_0_sram[1]:15 *C 94.760 55.760 +*N mux_tree_tapbuf_size5_0_sram[1]:16 *C 102.113 55.760 +*N mux_tree_tapbuf_size5_0_sram[1]:17 *C 102.120 55.760 +*N mux_tree_tapbuf_size5_0_sram[1]:18 *C 102.075 55.760 +*N mux_tree_tapbuf_size5_0_sram[1]:19 *C 101.543 55.760 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_2\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[1]:4 0.0001773627 +5 mux_tree_tapbuf_size5_0_sram[1]:5 0.0001773627 +6 mux_tree_tapbuf_size5_0_sram[1]:6 0.0003080434 +7 mux_tree_tapbuf_size5_0_sram[1]:7 5.324711e-05 +8 mux_tree_tapbuf_size5_0_sram[1]:8 5.645617e-05 +9 mux_tree_tapbuf_size5_0_sram[1]:9 5.266484e-05 +10 mux_tree_tapbuf_size5_0_sram[1]:10 0.0003281345 +11 mux_tree_tapbuf_size5_0_sram[1]:11 0.000546657 +12 mux_tree_tapbuf_size5_0_sram[1]:12 3.163911e-05 +13 mux_tree_tapbuf_size5_0_sram[1]:13 0.0001605324 +14 mux_tree_tapbuf_size5_0_sram[1]:14 0.0001605324 +15 mux_tree_tapbuf_size5_0_sram[1]:15 0.0009590409 +16 mux_tree_tapbuf_size5_0_sram[1]:16 0.0004123839 +17 mux_tree_tapbuf_size5_0_sram[1]:17 3.459278e-05 +18 mux_tree_tapbuf_size5_0_sram[1]:18 6.703895e-05 +19 mux_tree_tapbuf_size5_0_sram[1]:19 6.703895e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_0_sram[1]:19 0.152 +1 mux_tree_tapbuf_size5_0_sram[1]:12 mux_top_track_2\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:12 0.0045 +3 mux_tree_tapbuf_size5_0_sram[1]:14 mux_tree_tapbuf_size5_0_sram[1]:13 0.002337054 +4 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:14 0.00341 +5 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:11 0.001296025 +6 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:9 0.0001911058 +7 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:6 0.004765625 +8 mux_tree_tapbuf_size5_0_sram[1]:11 mux_tree_tapbuf_size5_0_sram[1]:10 0.00341 +9 mux_tree_tapbuf_size5_0_sram[1]:17 mux_tree_tapbuf_size5_0_sram[1]:16 0.00341 +10 mux_tree_tapbuf_size5_0_sram[1]:16 mux_tree_tapbuf_size5_0_sram[1]:15 0.001151892 +11 mux_tree_tapbuf_size5_0_sram[1]:18 mux_tree_tapbuf_size5_0_sram[1]:17 0.0045 +12 mux_tree_tapbuf_size5_0_sram[1]:19 mux_tree_tapbuf_size5_0_sram[1]:18 0.0004754465 +13 mux_tree_tapbuf_size5_0_sram[1]:5 mux_tree_tapbuf_size5_0_sram[1]:4 0.002301339 +14 mux_tree_tapbuf_size5_0_sram[1]:6 mux_tree_tapbuf_size5_0_sram[1]:5 0.0045 +15 mux_tree_tapbuf_size5_0_sram[1]:4 mux_top_track_2\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:7 9.51087e-05 +17 mux_tree_tapbuf_size5_0_sram[1]:9 mux_tree_tapbuf_size5_0_sram[1]:8 0.0045 +18 mux_tree_tapbuf_size5_0_sram[1]:7 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.004512141 //LENGTH 30.605 LUMPCC 0.001738643 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 97.365 69.700 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 94.400 67.320 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 82.975 64.260 +*I mux_top_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 87.760 72.080 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 87.797 72.080 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 94.255 72.080 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 94.300 72.035 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 83.013 64.260 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 94.255 64.260 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 94.300 64.305 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 94.300 67.320 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 94.300 67.320 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 94.300 70.040 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 94.345 70.040 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 96.140 70.040 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 96.140 69.700 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 97.328 69.700 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_0\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 0.000282544 +5 mux_tree_tapbuf_size6_0_sram[1]:5 0.000282544 +6 mux_tree_tapbuf_size6_0_sram[1]:6 8.991858e-05 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.0004008625 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.0004008625 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.0001293853 +10 mux_tree_tapbuf_size6_0_sram[1]:10 3.367234e-05 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0002801149 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0002409212 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0001669118 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.000193061 +15 mux_tree_tapbuf_size6_0_sram[1]:15 0.0001474246 +16 mux_tree_tapbuf_size6_0_sram[1]:16 0.0001212753 +17 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[2]:7 4.596081e-05 +18 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[2]:3 9.144338e-05 +19 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[2]:7 9.144338e-05 +20 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[2]:8 4.596081e-05 +21 mux_tree_tapbuf_size6_0_sram[1]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.834743e-05 +22 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.793213e-05 +23 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.466287e-05 +24 mux_tree_tapbuf_size6_0_sram[1]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.466287e-05 +25 mux_tree_tapbuf_size6_0_sram[1]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.834743e-05 +26 mux_tree_tapbuf_size6_0_sram[1]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.793213e-05 +27 mux_tree_tapbuf_size6_0_sram[1]:9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.518184e-06 +28 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.900682e-06 +29 mux_tree_tapbuf_size6_0_sram[1]:12 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.053773e-06 +30 mux_tree_tapbuf_size6_0_sram[1]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001872771 +31 mux_tree_tapbuf_size6_0_sram[1]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.900682e-06 +32 mux_tree_tapbuf_size6_0_sram[1]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001872771 +33 mux_tree_tapbuf_size6_0_sram[1]:11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.053773e-06 +34 mux_tree_tapbuf_size6_0_sram[1]:11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.518184e-06 +35 mux_tree_tapbuf_size6_0_sram[1]:8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000436225 +36 mux_tree_tapbuf_size6_0_sram[1]:7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000436225 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.01003795 +2 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:8 0.0045 +3 mux_tree_tapbuf_size6_0_sram[1]:7 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +4 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:11 0.002428572 +6 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:6 0.00178125 +7 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.001060268 +8 mux_tree_tapbuf_size6_0_sram[1]:5 mux_tree_tapbuf_size6_0_sram[1]:4 0.005765625 +9 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0045 +10 mux_tree_tapbuf_size6_0_sram[1]:4 mux_top_track_0\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size6_0_sram[1]:10 mux_top_track_0\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0045 +13 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:9 0.002691964 +14 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.001602679 +15 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.0006841924 //LENGTH 4.660 LUMPCC 0.0001758871 DR + +*CONN +*I mem_top_track_0\/FTB_1__31:X O *L 0 *C 94.995 63.920 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 95.395 60.860 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 95.395 60.860 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 95.680 60.860 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 95.680 60.905 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 95.680 63.875 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 95.635 63.920 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 95.032 63.920 + +*CAP +0 mem_top_track_0\/FTB_1__31:X 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 4.950218e-05 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 5.297214e-05 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001325182 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001325182 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 6.93973e-05 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 6.93973e-05 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.794357e-05 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.794357e-05 + +*RES +0 mem_top_track_0\/FTB_1__31:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[2] 0.00135434 //LENGTH 11.000 LUMPCC 0 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 55.505 115.260 +*I mem_right_track_6\/FTB_22__52:A I *L 0.001746 *C 54.280 112.880 +*I mux_right_track_6\/mux_l3_in_0_:S I *L 0.00357 *C 62.000 112.880 +*N mux_tree_tapbuf_size7_2_sram[2]:3 *C 61.963 112.880 +*N mux_tree_tapbuf_size7_2_sram[2]:4 *C 54.318 112.880 +*N mux_tree_tapbuf_size7_2_sram[2]:5 *C 55.660 112.880 +*N mux_tree_tapbuf_size7_2_sram[2]:6 *C 55.660 112.925 +*N mux_tree_tapbuf_size7_2_sram[2]:7 *C 55.660 115.215 +*N mux_tree_tapbuf_size7_2_sram[2]:8 *C 55.660 115.260 +*N mux_tree_tapbuf_size7_2_sram[2]:9 *C 55.505 115.260 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_6\/FTB_22__52:A 1e-06 +2 mux_right_track_6\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_2_sram[2]:3 0.0003909986 +4 mux_tree_tapbuf_size7_2_sram[2]:4 8.591847e-05 +5 mux_tree_tapbuf_size7_2_sram[2]:5 0.0005090878 +6 mux_tree_tapbuf_size7_2_sram[2]:6 0.0001348357 +7 mux_tree_tapbuf_size7_2_sram[2]:7 0.0001348357 +8 mux_tree_tapbuf_size7_2_sram[2]:8 4.992695e-05 +9 mux_tree_tapbuf_size7_2_sram[2]:9 4.573716e-05 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_2_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_2_sram[2]:3 mux_right_track_6\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[2]:4 mem_right_track_6\/FTB_22__52:A 0.152 +3 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:4 0.001198661 +4 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:3 0.005627233 +5 mux_tree_tapbuf_size7_2_sram[2]:6 mux_tree_tapbuf_size7_2_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:7 0.0045 +7 mux_tree_tapbuf_size7_2_sram[2]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.002044643 +8 mux_tree_tapbuf_size7_2_sram[2]:9 mux_tree_tapbuf_size7_2_sram[2]:8 8.423914e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001730378 //LENGTH 13.625 LUMPCC 0.0004452147 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_1_:X O *L 0 *C 83.435 42.500 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.470 53.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 84.433 53.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 83.765 53.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 83.720 53.675 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 83.720 44.880 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 83.260 44.880 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 83.260 42.545 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 83.260 42.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 83.435 42.500 + +*CAP +0 mux_top_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.741161e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.741161e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003479383 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003820464 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001705075 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001363994 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.790793e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.354059e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:13 0.0001370853 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:14 0.0001370853 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.850966e-06 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.850966e-06 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.367108e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.367108e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005959822 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002084821 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.51087e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004107143 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.007852679 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001925276 //LENGTH 14.345 LUMPCC 0.0009692192 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 50.315 37.400 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 44.720 45.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 44.758 45.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.175 45.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.220 45.175 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.220 37.445 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 49.265 37.400 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 50.278 37.400 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001057822 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001057822 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002795002 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002795002 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.174593e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.174593e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[10]:13 5.868035e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[10]:12 5.868035e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_4_sram[2]:4 0.0001037261 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_4_sram[2]:5 7.396523e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_4_sram[2]:3 7.396523e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_4_sram[2]:5 0.0001037261 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_4_sram[0]:16 6.434501e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_4_sram[0]:17 3.205552e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_4_sram[0]:11 7.890886e-07 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_4_sram[0]:13 6.434501e-05 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_4_sram[0]:16 3.205552e-05 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_4_sram[0]:10 7.890886e-07 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size6_4_sram[1]:15 0.0001510483 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_4_sram[1]:16 0.0001510483 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003944196 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008691718 //LENGTH 7.920 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_0_:X O *L 0 *C 94.015 53.720 +*I mux_top_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 91.445 58.140 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 91.483 58.140 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.875 58.140 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.920 58.095 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.920 53.765 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.965 53.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 93.978 53.720 + +*CAP +0 mux_top_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001022139 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001022139 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002469988 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002469988 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.437309e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.437309e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243304 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001214918 //LENGTH 8.685 LUMPCC 0.0005899231 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_1_:X O *L 0 *C 70.095 44.540 +*I mux_bottom_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 69.290 37.400 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 69.328 37.400 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 69.875 37.400 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 69.920 37.445 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 69.920 44.495 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 69.920 44.540 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 70.095 44.540 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.040134e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.040134e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001824668 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001824668 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.825379e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.900445e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[16]:31 6.851098e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[16]:34 2.566777e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[16]:34 6.851098e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[16]:35 2.566777e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_out[8] 0.0002007828 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_out[8]:2 0.0002007828 + +*RES +0 mux_bottom_track_3\/mux_l1_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006294643 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.000594609 //LENGTH 4.895 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_1_:X O *L 0 *C 53.185 86.020 +*I mux_top_track_32\/mux_l3_in_0_:A0 I *L 0.001631 *C 57.790 86.020 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 57.753 86.020 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 53.223 86.020 + +*CAP +0 mux_top_track_32\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002963045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002963045 + +*RES +0 mux_top_track_32\/mux_l2_in_1_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004044643 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006589625 //LENGTH 4.780 LUMPCC 0.0002071337 DR + +*CONN +*I mux_right_track_10\/mux_l2_in_1_:X O *L 0 *C 35.705 88.060 +*I mux_right_track_10\/mux_l3_in_0_:A0 I *L 0.001631 *C 40.195 88.060 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 40.157 88.060 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 35.742 88.060 + +*CAP +0 mux_right_track_10\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_10\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002249145 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002249145 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size4_3_sram[2]:9 0.0001035668 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size4_3_sram[2]:10 0.0001035668 + +*RES +0 mux_right_track_10\/mux_l2_in_1_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_10\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003941964 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003111988 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_1_:X O *L 0 *C 31.105 42.500 +*I mux_right_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 33.295 42.500 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 33.258 42.500 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 31.143 42.500 + +*CAP +0 mux_right_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001545994 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001545994 + +*RES +0 mux_right_track_24\/mux_l2_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001888393 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008198033 //LENGTH 5.835 LUMPCC 0.0001610209 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_1_:X O *L 0 *C 73.315 101.660 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 71.130 98.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 71.168 98.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 72.175 98.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 72.220 98.985 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 72.220 101.615 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 72.265 101.660 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 73.278 101.660 + +*CAP +0 mux_right_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000104684 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000104684 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001494202 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001494202 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.428696e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.428696e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:13 4.344841e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:28 3.230659e-07 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:15 2.046886e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:26 1.627012e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:14 4.344841e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:29 3.230659e-07 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_1_sram[0]:9 2.046886e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_1_sram[0]:15 1.627012e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008995535 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005517581 //LENGTH 4.210 LUMPCC 0 DR + +*CONN +*I mux_right_track_20\/mux_l1_in_0_:X O *L 0 *C 71.935 71.400 +*I mux_right_track_20\/mux_l2_in_0_:A1 I *L 0.00198 *C 73.140 69.020 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 73.140 69.020 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.140 69.065 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.140 71.355 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.095 71.400 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 71.972 71.400 + +*CAP +0 mux_right_track_20\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_20\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.370031e-05 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001529933 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001529933 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001050356 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001050356 + +*RES +0 mux_right_track_20\/mux_l1_in_0_:X mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001002232 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_20\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001359914 //LENGTH 9.820 LUMPCC 0.0003738819 DR + +*CONN +*I mux_right_track_26\/mux_l1_in_0_:X O *L 0 *C 38.465 59.160 +*I mux_right_track_26\/mux_l2_in_0_:A1 I *L 0.00198 *C 43.240 63.580 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 43.240 63.580 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 43.240 63.535 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 43.240 59.205 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 43.195 59.160 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 38.503 59.160 + +*CAP +0 mux_right_track_26\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_26\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.158267e-05 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00025568 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00025568 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002205449 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002205449 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[15]:2 0.0001869409 +8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[15]:3 0.0001869409 + +*RES +0 mux_right_track_26\/mux_l1_in_0_:X mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.004189732 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_26\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_223 0.001876766 //LENGTH 14.335 LUMPCC 0.0004003133 DR + +*CONN +*I ropt_mt_inst_828:X O *L 0 *C 31.475 3.400 +*I ropt_mt_inst_843:A I *L 0.001766 *C 25.300 6.800 +*N ropt_net_223:2 *C 25.338 6.800 +*N ropt_net_223:3 *C 28.015 6.800 +*N ropt_net_223:4 *C 28.060 6.755 +*N ropt_net_223:5 *C 28.060 1.745 +*N ropt_net_223:6 *C 28.105 1.700 +*N ropt_net_223:7 *C 31.235 1.700 +*N ropt_net_223:8 *C 31.280 1.745 +*N ropt_net_223:9 *C 31.280 3.355 +*N ropt_net_223:10 *C 31.280 3.400 +*N ropt_net_223:11 *C 31.475 3.400 + +*CAP +0 ropt_mt_inst_828:X 1e-06 +1 ropt_mt_inst_843:A 1e-06 +2 ropt_net_223:2 0.0002023721 +3 ropt_net_223:3 0.0002023721 +4 ropt_net_223:4 0.000204636 +5 ropt_net_223:5 0.000204636 +6 ropt_net_223:6 0.0002010703 +7 ropt_net_223:7 0.0002010703 +8 ropt_net_223:8 6.887099e-05 +9 ropt_net_223:9 6.887099e-05 +10 ropt_net_223:10 6.355474e-05 +11 ropt_net_223:11 5.699958e-05 +12 ropt_net_223:8 chany_bottom_in[11] 5.5367e-05 +13 ropt_net_223:9 chany_bottom_in[11]:19 5.5367e-05 +14 ropt_net_223:4 chany_bottom_out[16]:2 0.0001447896 +15 ropt_net_223:5 chany_bottom_out[16] 0.0001447896 + +*RES +0 ropt_mt_inst_828:X ropt_net_223:11 0.152 +1 ropt_net_223:2 ropt_mt_inst_843:A 0.152 +2 ropt_net_223:3 ropt_net_223:2 0.002390625 +3 ropt_net_223:4 ropt_net_223:3 0.0045 +4 ropt_net_223:6 ropt_net_223:5 0.0045 +5 ropt_net_223:5 ropt_net_223:4 0.004473215 +6 ropt_net_223:7 ropt_net_223:6 0.002794643 +7 ropt_net_223:8 ropt_net_223:7 0.0045 +8 ropt_net_223:10 ropt_net_223:9 0.0045 +9 ropt_net_223:9 ropt_net_223:8 0.0014375 +10 ropt_net_223:11 ropt_net_223:10 0.0001059783 + +*END + +*D_NET mux_bottom_track_25/BUF_net_66 0.0004417798 //LENGTH 3.415 LUMPCC 6.437508e-05 DR + +*CONN +*I mux_bottom_track_25\/BUFT_RR_66:X O *L 0 *C 62.795 17.000 +*I mux_bottom_track_25\/BUFT_P_147:A I *L 0.001746 *C 63.020 14.960 +*N mux_bottom_track_25/BUF_net_66:2 *C 62.983 14.960 +*N mux_bottom_track_25/BUF_net_66:3 *C 62.605 14.960 +*N mux_bottom_track_25/BUF_net_66:4 *C 62.560 15.005 +*N mux_bottom_track_25/BUF_net_66:5 *C 62.560 16.955 +*N mux_bottom_track_25/BUF_net_66:6 *C 62.560 17.000 +*N mux_bottom_track_25/BUF_net_66:7 *C 62.795 17.000 + +*CAP +0 mux_bottom_track_25\/BUFT_RR_66:X 1e-06 +1 mux_bottom_track_25\/BUFT_P_147:A 1e-06 +2 mux_bottom_track_25/BUF_net_66:2 4.31767e-05 +3 mux_bottom_track_25/BUF_net_66:3 4.31767e-05 +4 mux_bottom_track_25/BUF_net_66:4 9.039442e-05 +5 mux_bottom_track_25/BUF_net_66:5 9.039442e-05 +6 mux_bottom_track_25/BUF_net_66:6 5.13882e-05 +7 mux_bottom_track_25/BUF_net_66:7 5.687428e-05 +8 mux_bottom_track_25/BUF_net_66:4 chany_top_in[16]:25 3.218754e-05 +9 mux_bottom_track_25/BUF_net_66:5 chany_top_in[16]:26 3.218754e-05 + +*RES +0 mux_bottom_track_25\/BUFT_RR_66:X mux_bottom_track_25/BUF_net_66:7 0.152 +1 mux_bottom_track_25/BUF_net_66:2 mux_bottom_track_25\/BUFT_P_147:A 0.152 +2 mux_bottom_track_25/BUF_net_66:3 mux_bottom_track_25/BUF_net_66:2 0.0003370536 +3 mux_bottom_track_25/BUF_net_66:4 mux_bottom_track_25/BUF_net_66:3 0.0045 +4 mux_bottom_track_25/BUF_net_66:6 mux_bottom_track_25/BUF_net_66:5 0.0045 +5 mux_bottom_track_25/BUF_net_66:5 mux_bottom_track_25/BUF_net_66:4 0.001741072 +6 mux_bottom_track_25/BUF_net_66:7 mux_bottom_track_25/BUF_net_66:6 0.0001277174 + +*END + +*D_NET chany_top_in[5] 0.02150119 //LENGTH 163.830 LUMPCC 0.005339686 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 28.980 129.270 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.220 28.900 +*I BUFT_RR_76:A I *L 0.001776 *C 68.540 14.960 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 67.335 102.680 +*N chany_top_in[5]:4 *C 67.335 102.680 +*N chany_top_in[5]:5 *C 67.160 102.680 +*N chany_top_in[5]:6 *C 67.160 102.725 +*N chany_top_in[5]:7 *C 68.540 14.960 +*N chany_top_in[5]:8 *C 68.540 15.005 +*N chany_top_in[5]:9 *C 72.183 28.900 +*N chany_top_in[5]:10 *C 68.585 28.900 +*N chany_top_in[5]:11 *C 68.540 28.900 +*N chany_top_in[5]:12 *C 68.540 35.303 +*N chany_top_in[5]:13 *C 68.547 35.360 +*N chany_top_in[5]:14 *C 69.900 35.360 +*N chany_top_in[5]:15 *C 69.920 35.367 +*N chany_top_in[5]:16 *C 69.920 85.195 +*N chany_top_in[5]:17 *C 69.920 103.353 +*N chany_top_in[5]:18 *C 69.900 103.360 +*N chany_top_in[5]:19 *C 67.168 103.360 +*N chany_top_in[5]:20 *C 67.160 103.360 +*N chany_top_in[5]:21 *C 67.160 105.343 +*N chany_top_in[5]:22 *C 67.153 105.400 +*N chany_top_in[5]:23 *C 28.988 105.400 +*N chany_top_in[5]:24 *C 28.980 105.458 + +*CAP +0 chany_top_in[5] 0.001040102 +1 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +2 BUFT_RR_76:A 1e-06 +3 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[5]:4 5.22289e-05 +5 chany_top_in[5]:5 5.635123e-05 +6 chany_top_in[5]:6 3.388268e-05 +7 chany_top_in[5]:7 3.135182e-05 +8 chany_top_in[5]:8 0.0006729672 +9 chany_top_in[5]:9 0.0002535799 +10 chany_top_in[5]:10 0.0002535799 +11 chany_top_in[5]:11 0.001072389 +12 chany_top_in[5]:12 0.0003638387 +13 chany_top_in[5]:13 0.0001075418 +14 chany_top_in[5]:14 0.0001075418 +15 chany_top_in[5]:15 0.002614815 +16 chany_top_in[5]:16 0.003221036 +17 chany_top_in[5]:17 0.0006062201 +18 chany_top_in[5]:18 0.0001493451 +19 chany_top_in[5]:19 0.0001493451 +20 chany_top_in[5]:20 0.0001795411 +21 chany_top_in[5]:21 0.0001069602 +22 chany_top_in[5]:22 0.002022892 +23 chany_top_in[5]:23 0.002022892 +24 chany_top_in[5]:24 0.001040102 +25 chany_top_in[5]:11 chany_top_in[6]:12 4.834919e-05 +26 chany_top_in[5]:11 chany_top_in[6]:10 2.05486e-05 +27 chany_top_in[5]:11 chany_top_in[6]:11 4.515565e-05 +28 chany_top_in[5]:12 chany_top_in[6]:12 4.515565e-05 +29 chany_top_in[5]:15 chany_top_in[6]:23 0.0006914637 +30 chany_top_in[5]:17 chany_top_in[6]:25 7.22581e-05 +31 chany_top_in[5]:17 chany_top_in[6]:24 0.0002936183 +32 chany_top_in[5]:8 chany_top_in[6]:9 2.05486e-05 +33 chany_top_in[5]:8 chany_top_in[6]:11 4.834919e-05 +34 chany_top_in[5]:16 chany_top_in[6]:23 0.0002936183 +35 chany_top_in[5]:16 chany_top_in[6]:24 0.0007637218 +36 chany_top_in[5]:17 chany_bottom_in[2]:11 0.0004638032 +37 chany_top_in[5]:16 chany_bottom_in[2]:12 0.0004638032 +38 chany_top_in[5]:18 chany_bottom_in[5]:7 0.0001623448 +39 chany_top_in[5]:19 chany_bottom_in[5]:16 0.0001623448 +40 chany_top_in[5]:22 chany_bottom_in[5]:12 0.0002282401 +41 chany_top_in[5]:22 chany_bottom_in[5]:7 3.989215e-05 +42 chany_top_in[5]:22 chany_bottom_in[5]:16 1.618427e-05 +43 chany_top_in[5]:23 chany_bottom_in[5]:15 1.618427e-05 +44 chany_top_in[5]:23 chany_bottom_in[5]:11 0.0002282401 +45 chany_top_in[5]:23 chany_bottom_in[5]:16 3.989215e-05 +46 chany_top_in[5]:20 chany_top_in[1]:4 1.627878e-05 +47 chany_top_in[5]:20 chany_top_in[1]:5 9.966855e-06 +48 chany_top_in[5]:21 chany_top_in[1]:5 1.627878e-05 +49 chany_top_in[5]:22 chany_top_in[1]:6 0.0002469371 +50 chany_top_in[5]:23 chany_top_in[1]:7 0.0002469371 +51 chany_top_in[5]:5 chany_top_in[1]:3 3.069353e-07 +52 chany_top_in[5]:6 chany_top_in[1]:4 9.966855e-06 +53 chany_top_in[5]:4 chany_top_in[1]:2 3.069353e-07 +54 chany_top_in[5]:22 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0002084401 +55 chany_top_in[5]:23 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0002084401 +56 chany_top_in[5] aps_rename_2_:4 0.0001060551 +57 chany_top_in[5]:24 aps_rename_2_:5 0.0001060551 + +*RES +0 chany_top_in[5] chany_top_in[5]:24 0.02126116 +1 chany_top_in[5]:9 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[5]:10 chany_top_in[5]:9 0.003212054 +3 chany_top_in[5]:11 chany_top_in[5]:10 0.0045 +4 chany_top_in[5]:11 chany_top_in[5]:8 0.01240625 +5 chany_top_in[5]:12 chany_top_in[5]:11 0.005716518 +6 chany_top_in[5]:13 chany_top_in[5]:12 0.00341 +7 chany_top_in[5]:14 chany_top_in[5]:13 0.0002118916 +8 chany_top_in[5]:15 chany_top_in[5]:14 0.00341 +9 chany_top_in[5]:18 chany_top_in[5]:17 0.00341 +10 chany_top_in[5]:17 chany_top_in[5]:16 0.002844675 +11 chany_top_in[5]:20 chany_top_in[5]:19 0.00341 +12 chany_top_in[5]:20 chany_top_in[5]:6 0.0005669643 +13 chany_top_in[5]:19 chany_top_in[5]:18 0.0004280917 +14 chany_top_in[5]:21 chany_top_in[5]:20 0.001770089 +15 chany_top_in[5]:22 chany_top_in[5]:21 0.00341 +16 chany_top_in[5]:24 chany_top_in[5]:23 0.00341 +17 chany_top_in[5]:23 chany_top_in[5]:22 0.005979183 +18 chany_top_in[5]:7 BUFT_RR_76:A 0.152 +19 chany_top_in[5]:8 chany_top_in[5]:7 0.0045 +20 chany_top_in[5]:5 chany_top_in[5]:4 9.51087e-05 +21 chany_top_in[5]:6 chany_top_in[5]:5 0.0045 +22 chany_top_in[5]:4 mux_right_track_4\/mux_l1_in_0_:A0 0.152 +23 chany_top_in[5]:16 chany_top_in[5]:15 0.007806308 + +*END + +*D_NET chany_top_in[15] 0.003960898 //LENGTH 32.785 LUMPCC 0.00116722 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 49.680 129.350 +*I mux_right_track_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 48.475 98.940 +*N chany_top_in[15]:2 *C 48.513 98.940 +*N chany_top_in[15]:3 *C 49.175 98.940 +*N chany_top_in[15]:4 *C 49.220 98.985 +*N chany_top_in[15]:5 *C 49.220 106.703 +*N chany_top_in[15]:6 *C 49.223 106.760 +*N chany_top_in[15]:7 *C 49.665 106.760 +*N chany_top_in[15]:8 *C 49.680 106.767 + +*CAP +0 chany_top_in[15] 0.0007702389 +1 mux_right_track_12\/mux_l1_in_0_:A0 1e-06 +2 chany_top_in[15]:2 6.226003e-05 +3 chany_top_in[15]:3 6.226003e-05 +4 chany_top_in[15]:4 0.0005008852 +5 chany_top_in[15]:5 0.0005008852 +6 chany_top_in[15]:6 6.295468e-05 +7 chany_top_in[15]:7 6.295468e-05 +8 chany_top_in[15]:8 0.0007702389 +9 chany_top_in[15] chany_top_in[19]:9 0.0004314557 +10 chany_top_in[15]:8 chany_top_in[19]:8 0.0004314557 +11 chany_top_in[15] mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001521545 +12 chany_top_in[15]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001521545 + +*RES +0 chany_top_in[15] chany_top_in[15]:8 0.003537924 +1 chany_top_in[15]:2 mux_right_track_12\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[15]:3 chany_top_in[15]:2 0.0005915179 +3 chany_top_in[15]:4 chany_top_in[15]:3 0.0045 +4 chany_top_in[15]:5 chany_top_in[15]:4 0.006890625 +5 chany_top_in[15]:6 chany_top_in[15]:5 0.00341 +6 chany_top_in[15]:7 chany_top_in[15]:6 6.499219e-05 +7 chany_top_in[15]:8 chany_top_in[15]:7 0.00341 + +*END + +*D_NET chanx_right_in[3] 0.004019801 //LENGTH 31.930 LUMPCC 0 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 111.930 43.520 +*I mux_bottom_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 89.145 36.380 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 88.610 44.200 +*N chanx_right_in[3]:3 *C 88.648 44.200 +*N chanx_right_in[3]:4 *C 89.195 44.200 +*N chanx_right_in[3]:5 *C 89.240 44.155 +*N chanx_right_in[3]:6 *C 89.145 36.380 +*N chanx_right_in[3]:7 *C 89.240 36.425 +*N chanx_right_in[3]:8 *C 89.240 43.520 +*N chanx_right_in[3]:9 *C 89.248 43.520 + +*CAP +0 chanx_right_in[3] 0.001496277 +1 mux_bottom_track_5\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[3]:3 6.67819e-05 +4 chanx_right_in[3]:4 6.67819e-05 +5 chanx_right_in[3]:5 4.267907e-05 +6 chanx_right_in[3]:6 2.806296e-05 +7 chanx_right_in[3]:7 0.0003714786 +8 chanx_right_in[3]:8 0.0004494625 +9 chanx_right_in[3]:9 0.001496277 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:9 0.003553591 +1 chanx_right_in[3]:6 mux_bottom_track_5\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[3]:7 chanx_right_in[3]:6 0.0045 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0004888393 +4 chanx_right_in[3]:5 chanx_right_in[3]:4 0.0045 +5 chanx_right_in[3]:3 mux_top_track_4\/mux_l1_in_0_:A0 0.152 +6 chanx_right_in[3]:8 chanx_right_in[3]:7 0.006334822 +7 chanx_right_in[3]:8 chanx_right_in[3]:5 0.0005669642 +8 chanx_right_in[3]:9 chanx_right_in[3]:8 0.00341 + +*END + +*D_NET chanx_right_in[7] 0.0100619 //LENGTH 65.460 LUMPCC 0.004292631 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 111.930 69.360 +*I mux_bottom_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 60.435 59.160 +*I mux_top_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.550 71.400 +*N chanx_right_in[7]:3 *C 60.588 71.400 +*N chanx_right_in[7]:4 *C 61.135 71.400 +*N chanx_right_in[7]:5 *C 61.180 71.355 +*N chanx_right_in[7]:6 *C 60.473 59.160 +*N chanx_right_in[7]:7 *C 61.135 59.160 +*N chanx_right_in[7]:8 *C 61.180 59.205 +*N chanx_right_in[7]:9 *C 61.180 69.360 +*N chanx_right_in[7]:10 *C 61.188 69.360 + +*CAP +0 chanx_right_in[7] 0.002175814 +1 mux_bottom_track_25\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[7]:3 6.04268e-05 +4 chanx_right_in[7]:4 6.04268e-05 +5 chanx_right_in[7]:5 0.0001171022 +6 chanx_right_in[7]:6 6.946909e-05 +7 chanx_right_in[7]:7 6.946909e-05 +8 chanx_right_in[7]:8 0.0004424253 +9 chanx_right_in[7]:9 0.0005963261 +10 chanx_right_in[7]:10 0.002175814 +11 chanx_right_in[7] chany_bottom_in[14]:11 0.0007519773 +12 chanx_right_in[7]:10 chany_bottom_in[14]:16 0.0007519773 +13 chanx_right_in[7] mux_tree_tapbuf_size3_1_sram[0]:16 0.0004247676 +14 chanx_right_in[7]:10 mux_tree_tapbuf_size3_1_sram[0]:15 0.0004247676 +15 chanx_right_in[7]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00011446 +16 chanx_right_in[7]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00011446 +17 chanx_right_in[7]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.677426e-06 +18 chanx_right_in[7]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.677426e-06 +19 chanx_right_in[7] mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006024307 +20 chanx_right_in[7]:10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0006024307 +21 chanx_right_in[7] ropt_net_235:6 0.0002470024 +22 chanx_right_in[7]:10 ropt_net_235:5 0.0002470024 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:10 0.007949658 +1 chanx_right_in[7]:7 chanx_right_in[7]:6 0.0005915179 +2 chanx_right_in[7]:8 chanx_right_in[7]:7 0.0045 +3 chanx_right_in[7]:6 mux_bottom_track_25\/mux_l1_in_1_:A0 0.152 +4 chanx_right_in[7]:9 chanx_right_in[7]:8 0.009066965 +5 chanx_right_in[7]:9 chanx_right_in[7]:5 0.00178125 +6 chanx_right_in[7]:10 chanx_right_in[7]:9 0.00341 +7 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0004888392 +8 chanx_right_in[7]:5 chanx_right_in[7]:4 0.0045 +9 chanx_right_in[7]:3 mux_top_track_32\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chanx_right_in[16] 0.003996765 //LENGTH 29.235 LUMPCC 0.0008442363 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 111.930 39.440 +*I mux_bottom_track_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 97.425 36.380 +*I mux_top_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 96.600 47.260 +*N chanx_right_in[16]:3 *C 96.600 47.260 +*N chanx_right_in[16]:4 *C 96.600 47.215 +*N chanx_right_in[16]:5 *C 96.600 38.818 +*N chanx_right_in[16]:6 *C 96.608 38.760 +*N chanx_right_in[16]:7 *C 97.463 36.380 +*N chanx_right_in[16]:8 *C 97.935 36.380 +*N chanx_right_in[16]:9 *C 97.980 36.425 +*N chanx_right_in[16]:10 *C 97.980 38.703 +*N chanx_right_in[16]:11 *C 97.980 38.768 +*N chanx_right_in[16]:12 *C 97.980 39.440 + +*CAP +0 chanx_right_in[16] 0.0007001648 +1 mux_bottom_track_9\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[16]:3 3.23326e-05 +4 chanx_right_in[16]:4 0.0004897864 +5 chanx_right_in[16]:5 0.0004897864 +6 chanx_right_in[16]:6 6.889222e-05 +7 chanx_right_in[16]:7 6.435244e-05 +8 chanx_right_in[16]:8 6.435244e-05 +9 chanx_right_in[16]:9 0.0001793948 +10 chanx_right_in[16]:10 0.0001793948 +11 chanx_right_in[16]:11 0.0001253993 +12 chanx_right_in[16]:12 0.0007566719 +13 chanx_right_in[16] chanx_right_in[11] 0.0003280071 +14 chanx_right_in[16]:6 chanx_right_in[11]:13 9.411105e-05 +15 chanx_right_in[16]:11 chanx_right_in[11] 9.411105e-05 +16 chanx_right_in[16]:12 chanx_right_in[11]:13 0.0003280071 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:12 0.0021855 +1 chanx_right_in[16]:3 mux_top_track_2\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[16]:4 chanx_right_in[16]:3 0.0045 +3 chanx_right_in[16]:5 chanx_right_in[16]:4 0.007497768 +4 chanx_right_in[16]:6 chanx_right_in[16]:5 0.00341 +5 chanx_right_in[16]:10 chanx_right_in[16]:9 0.002033482 +6 chanx_right_in[16]:11 chanx_right_in[16]:10 0.00341 +7 chanx_right_in[16]:11 chanx_right_in[16]:6 0.000215025 +8 chanx_right_in[16]:8 chanx_right_in[16]:7 0.000421875 +9 chanx_right_in[16]:9 chanx_right_in[16]:8 0.0045 +10 chanx_right_in[16]:7 mux_bottom_track_9\/mux_l1_in_2_:A1 0.152 +11 chanx_right_in[16]:12 chanx_right_in[16]:11 0.0001053583 + +*END + +*D_NET right_top_grid_pin_47_[0] 0.007838259 //LENGTH 62.065 LUMPCC 0.001646294 DR + +*CONN +*P right_top_grid_pin_47_[0] I *L 0.29796 *C 83.410 117.640 +*I mux_right_track_6\/mux_l1_in_2_:A1 I *L 0.00198 *C 67.525 112.540 +*I mux_right_track_2\/mux_l1_in_2_:A1 I *L 0.00198 *C 79.580 101.660 +*I mux_right_track_18\/mux_l1_in_0_:A0 I *L 0.001631 *C 75.155 86.020 +*N right_top_grid_pin_47_[0]:4 *C 75.193 86.020 +*N right_top_grid_pin_47_[0]:5 *C 79.535 86.020 +*N right_top_grid_pin_47_[0]:6 *C 79.580 86.065 +*N right_top_grid_pin_47_[0]:7 *C 79.580 101.660 +*N right_top_grid_pin_47_[0]:8 *C 79.580 102.000 +*N right_top_grid_pin_47_[0]:9 *C 79.580 102.000 +*N right_top_grid_pin_47_[0]:10 *C 79.580 105.355 +*N right_top_grid_pin_47_[0]:11 *C 79.625 105.400 +*N right_top_grid_pin_47_[0]:12 *C 83.215 105.400 +*N right_top_grid_pin_47_[0]:13 *C 83.260 105.445 +*N right_top_grid_pin_47_[0]:14 *C 83.260 114.183 +*N right_top_grid_pin_47_[0]:15 *C 83.252 114.240 +*N right_top_grid_pin_47_[0]:16 *C 67.562 112.540 +*N right_top_grid_pin_47_[0]:17 *C 69.415 112.540 +*N right_top_grid_pin_47_[0]:18 *C 69.460 112.585 +*N right_top_grid_pin_47_[0]:19 *C 69.460 114.183 +*N right_top_grid_pin_47_[0]:20 *C 69.468 114.240 +*N right_top_grid_pin_47_[0]:21 *C 81.880 114.240 +*N right_top_grid_pin_47_[0]:22 *C 81.880 114.248 +*N right_top_grid_pin_47_[0]:23 *C 81.880 117.633 +*N right_top_grid_pin_47_[0]:24 *C 81.900 117.640 + +*CAP +0 right_top_grid_pin_47_[0] 0.0001070956 +1 mux_right_track_6\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_2_:A1 1e-06 +3 mux_right_track_18\/mux_l1_in_0_:A0 1e-06 +4 right_top_grid_pin_47_[0]:4 0.0002659104 +5 right_top_grid_pin_47_[0]:5 0.0002659104 +6 right_top_grid_pin_47_[0]:6 0.0007730046 +7 right_top_grid_pin_47_[0]:7 6.762554e-05 +8 right_top_grid_pin_47_[0]:8 7.235185e-05 +9 right_top_grid_pin_47_[0]:9 0.0009425143 +10 right_top_grid_pin_47_[0]:10 0.0001380298 +11 right_top_grid_pin_47_[0]:11 0.000249074 +12 right_top_grid_pin_47_[0]:12 0.000249074 +13 right_top_grid_pin_47_[0]:13 0.0002910942 +14 right_top_grid_pin_47_[0]:14 0.0002910942 +15 right_top_grid_pin_47_[0]:15 5.511273e-05 +16 right_top_grid_pin_47_[0]:16 0.0001069684 +17 right_top_grid_pin_47_[0]:17 0.0001069684 +18 right_top_grid_pin_47_[0]:18 0.0001101413 +19 right_top_grid_pin_47_[0]:19 0.0001101413 +20 right_top_grid_pin_47_[0]:20 0.0006874503 +21 right_top_grid_pin_47_[0]:21 0.0007425629 +22 right_top_grid_pin_47_[0]:22 0.0002248718 +23 right_top_grid_pin_47_[0]:23 0.0002248718 +24 right_top_grid_pin_47_[0]:24 0.0001070956 +25 right_top_grid_pin_47_[0]:9 chany_top_in[12]:29 9.125518e-05 +26 right_top_grid_pin_47_[0]:9 chany_top_in[12]:30 0.0002102359 +27 right_top_grid_pin_47_[0]:10 chany_top_in[12]:30 9.125518e-05 +28 right_top_grid_pin_47_[0]:6 chany_top_in[12]:29 0.0002102359 +29 right_top_grid_pin_47_[0]:14 right_top_grid_pin_49_[0]:9 0.0002344529 +30 right_top_grid_pin_47_[0]:13 right_top_grid_pin_49_[0]:22 0.0002344529 +31 right_top_grid_pin_47_[0]:17 right_top_grid_pin_49_[0]:5 7.996938e-06 +32 right_top_grid_pin_47_[0]:17 right_top_grid_pin_49_[0]:8 1.412156e-05 +33 right_top_grid_pin_47_[0]:16 right_top_grid_pin_49_[0]:6 7.996938e-06 +34 right_top_grid_pin_47_[0]:16 right_top_grid_pin_49_[0]:7 1.412156e-05 +35 right_top_grid_pin_47_[0] mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 1.274738e-06 +36 right_top_grid_pin_47_[0]:15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 2.546895e-05 +37 right_top_grid_pin_47_[0]:20 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0002383408 +38 right_top_grid_pin_47_[0]:21 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 2.546895e-05 +39 right_top_grid_pin_47_[0]:21 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0002383408 +40 right_top_grid_pin_47_[0]:24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 1.274738e-06 + +*RES +0 right_top_grid_pin_47_[0] right_top_grid_pin_47_[0]:24 0.0002365667 +1 right_top_grid_pin_47_[0]:8 right_top_grid_pin_47_[0]:7 0.0001465517 +2 right_top_grid_pin_47_[0]:9 right_top_grid_pin_47_[0]:8 0.0045 +3 right_top_grid_pin_47_[0]:9 right_top_grid_pin_47_[0]:6 0.01422768 +4 right_top_grid_pin_47_[0]:7 mux_right_track_2\/mux_l1_in_2_:A1 0.152 +5 right_top_grid_pin_47_[0]:14 right_top_grid_pin_47_[0]:13 0.007801339 +6 right_top_grid_pin_47_[0]:15 right_top_grid_pin_47_[0]:14 0.00341 +7 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:11 0.003205357 +8 right_top_grid_pin_47_[0]:13 right_top_grid_pin_47_[0]:12 0.0045 +9 right_top_grid_pin_47_[0]:11 right_top_grid_pin_47_[0]:10 0.0045 +10 right_top_grid_pin_47_[0]:10 right_top_grid_pin_47_[0]:9 0.002995536 +11 right_top_grid_pin_47_[0]:5 right_top_grid_pin_47_[0]:4 0.003877233 +12 right_top_grid_pin_47_[0]:6 right_top_grid_pin_47_[0]:5 0.0045 +13 right_top_grid_pin_47_[0]:4 mux_right_track_18\/mux_l1_in_0_:A0 0.152 +14 right_top_grid_pin_47_[0]:19 right_top_grid_pin_47_[0]:18 0.001426339 +15 right_top_grid_pin_47_[0]:20 right_top_grid_pin_47_[0]:19 0.00341 +16 right_top_grid_pin_47_[0]:17 right_top_grid_pin_47_[0]:16 0.001654018 +17 right_top_grid_pin_47_[0]:18 right_top_grid_pin_47_[0]:17 0.0045 +18 right_top_grid_pin_47_[0]:16 mux_right_track_6\/mux_l1_in_2_:A1 0.152 +19 right_top_grid_pin_47_[0]:21 right_top_grid_pin_47_[0]:20 0.001944625 +20 right_top_grid_pin_47_[0]:21 right_top_grid_pin_47_[0]:15 0.000215025 +21 right_top_grid_pin_47_[0]:22 right_top_grid_pin_47_[0]:21 0.00341 +22 right_top_grid_pin_47_[0]:24 right_top_grid_pin_47_[0]:23 0.00341 +23 right_top_grid_pin_47_[0]:23 right_top_grid_pin_47_[0]:22 0.0005303167 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001299183 //LENGTH 10.440 LUMPCC 0.0001245124 DR + +*CONN +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 81.265 80.240 +*I mem_right_track_18\/FTB_24__54:A I *L 0.001746 *C 82.800 77.520 +*I mux_right_track_18\/mux_l2_in_0_:S I *L 0.00357 *C 81.780 72.760 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 81.765 72.760 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 81.443 72.760 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 81.420 72.805 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 82.763 77.520 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 81.465 77.520 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 81.420 77.520 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 81.420 80.195 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 81.420 80.240 +*N mux_tree_tapbuf_size3_1_sram[1]:11 *C 81.265 80.240 + +*CAP +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_18\/FTB_24__54:A 1e-06 +2 mux_right_track_18\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 5.116488e-05 +4 mux_tree_tapbuf_size3_1_sram[1]:4 5.116488e-05 +5 mux_tree_tapbuf_size3_1_sram[1]:5 0.0002551382 +6 mux_tree_tapbuf_size3_1_sram[1]:6 6.141537e-05 +7 mux_tree_tapbuf_size3_1_sram[1]:7 6.141537e-05 +8 mux_tree_tapbuf_size3_1_sram[1]:8 0.0004372662 +9 mux_tree_tapbuf_size3_1_sram[1]:9 0.0001502796 +10 mux_tree_tapbuf_size3_1_sram[1]:10 5.496304e-05 +11 mux_tree_tapbuf_size3_1_sram[1]:11 4.886337e-05 +12 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 6.225622e-05 +13 mux_tree_tapbuf_size3_1_sram[1]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 6.225622e-05 + +*RES +0 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:3 mux_right_track_18\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.0001752718 +3 mux_tree_tapbuf_size3_1_sram[1]:5 mux_tree_tapbuf_size3_1_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.002388393 +6 mux_tree_tapbuf_size3_1_sram[1]:11 mux_tree_tapbuf_size3_1_sram[1]:10 8.423914e-05 +7 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.001158482 +8 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.0045 +9 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:5 0.004209822 +10 mux_tree_tapbuf_size3_1_sram[1]:6 mem_right_track_18\/FTB_24__54:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[2] 0.001766043 //LENGTH 13.405 LUMPCC 0.0004307585 DR + +*CONN +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.025 93.500 +*I mem_right_track_10\/FTB_16__46:A I *L 0.001746 *C 41.400 85.680 +*I mux_right_track_10\/mux_l3_in_0_:S I *L 0.00357 *C 41.300 88.695 +*N mux_tree_tapbuf_size4_3_sram[2]:3 *C 41.300 88.695 +*N mux_tree_tapbuf_size4_3_sram[2]:4 *C 41.400 85.695 +*N mux_tree_tapbuf_size4_3_sram[2]:5 *C 41.400 86.020 +*N mux_tree_tapbuf_size4_3_sram[2]:6 *C 41.400 86.065 +*N mux_tree_tapbuf_size4_3_sram[2]:7 *C 41.400 88.355 +*N mux_tree_tapbuf_size4_3_sram[2]:8 *C 41.343 88.430 +*N mux_tree_tapbuf_size4_3_sram[2]:9 *C 41.263 88.400 +*N mux_tree_tapbuf_size4_3_sram[2]:10 *C 37.765 88.400 +*N mux_tree_tapbuf_size4_3_sram[2]:11 *C 37.720 88.445 +*N mux_tree_tapbuf_size4_3_sram[2]:12 *C 37.720 93.455 +*N mux_tree_tapbuf_size4_3_sram[2]:13 *C 37.720 93.500 +*N mux_tree_tapbuf_size4_3_sram[2]:14 *C 38.025 93.500 + +*CAP +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_10\/FTB_16__46:A 1e-06 +2 mux_right_track_10\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_3_sram[2]:3 6.135861e-05 +4 mux_tree_tapbuf_size4_3_sram[2]:4 3.858763e-05 +5 mux_tree_tapbuf_size4_3_sram[2]:5 7.454906e-05 +6 mux_tree_tapbuf_size4_3_sram[2]:6 0.0001360836 +7 mux_tree_tapbuf_size4_3_sram[2]:7 0.0001360836 +8 mux_tree_tapbuf_size4_3_sram[2]:8 4.398274e-05 +9 mux_tree_tapbuf_size4_3_sram[2]:9 0.0001663242 +10 mux_tree_tapbuf_size4_3_sram[2]:10 0.000150099 +11 mux_tree_tapbuf_size4_3_sram[2]:11 0.0002116431 +12 mux_tree_tapbuf_size4_3_sram[2]:12 0.0002116431 +13 mux_tree_tapbuf_size4_3_sram[2]:13 5.178405e-05 +14 mux_tree_tapbuf_size4_3_sram[2]:14 5.014543e-05 +15 mux_tree_tapbuf_size4_3_sram[2]:7 chany_bottom_in[8]:21 4.444548e-06 +16 mux_tree_tapbuf_size4_3_sram[2]:6 chany_bottom_in[8]:22 4.444548e-06 +17 mux_tree_tapbuf_size4_3_sram[2]:10 chany_bottom_in[8]:20 1.010158e-05 +18 mux_tree_tapbuf_size4_3_sram[2]:11 chany_bottom_in[8]:20 8.063658e-05 +19 mux_tree_tapbuf_size4_3_sram[2]:11 chany_bottom_in[8]:22 1.662969e-05 +20 mux_tree_tapbuf_size4_3_sram[2]:12 chany_bottom_in[8]:19 8.063658e-05 +21 mux_tree_tapbuf_size4_3_sram[2]:12 chany_bottom_in[8]:21 1.662969e-05 +22 mux_tree_tapbuf_size4_3_sram[2]:9 chany_bottom_in[8]:21 1.010158e-05 +23 mux_tree_tapbuf_size4_3_sram[2]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001035668 +24 mux_tree_tapbuf_size4_3_sram[2]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001035668 + +*RES +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_3_sram[2]:14 0.152 +1 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_3_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_3_sram[2]:3 0.0001142242 +3 mux_tree_tapbuf_size4_3_sram[2]:7 mux_tree_tapbuf_size4_3_sram[2]:6 0.002044643 +4 mux_tree_tapbuf_size4_3_sram[2]:5 mux_tree_tapbuf_size4_3_sram[2]:4 0.0001766305 +5 mux_tree_tapbuf_size4_3_sram[2]:6 mux_tree_tapbuf_size4_3_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size4_3_sram[2]:4 mem_right_track_10\/FTB_16__46:A 0.152 +7 mux_tree_tapbuf_size4_3_sram[2]:10 mux_tree_tapbuf_size4_3_sram[2]:9 0.003122768 +8 mux_tree_tapbuf_size4_3_sram[2]:11 mux_tree_tapbuf_size4_3_sram[2]:10 0.0045 +9 mux_tree_tapbuf_size4_3_sram[2]:13 mux_tree_tapbuf_size4_3_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size4_3_sram[2]:12 mux_tree_tapbuf_size4_3_sram[2]:11 0.004473214 +11 mux_tree_tapbuf_size4_3_sram[2]:14 mux_tree_tapbuf_size4_3_sram[2]:13 0.0001657609 +12 mux_tree_tapbuf_size4_3_sram[2]:3 mux_right_track_10\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size4_3_sram[2]:9 mux_tree_tapbuf_size4_3_sram[2]:8 7.142857e-05 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[0] 0.006195361 //LENGTH 47.842 LUMPCC 0.0003644431 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 97.825 44.540 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 66.875 47.940 +*I mux_bottom_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 66.580 45.560 +*I mux_bottom_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 99.920 47.260 +*N mux_tree_tapbuf_size5_3_sram[0]:4 *C 99.883 47.260 +*N mux_tree_tapbuf_size5_3_sram[0]:5 *C 98.900 47.260 +*N mux_tree_tapbuf_size5_3_sram[0]:6 *C 98.900 48.280 +*N mux_tree_tapbuf_size5_3_sram[0]:7 *C 98.900 48.325 +*N mux_tree_tapbuf_size5_3_sram[0]:8 *C 98.900 49.935 +*N mux_tree_tapbuf_size5_3_sram[0]:9 *C 98.855 49.980 +*N mux_tree_tapbuf_size5_3_sram[0]:10 *C 97.565 49.980 +*N mux_tree_tapbuf_size5_3_sram[0]:11 *C 97.520 49.935 +*N mux_tree_tapbuf_size5_3_sram[0]:12 *C 66.580 45.560 +*N mux_tree_tapbuf_size5_3_sram[0]:13 *C 66.700 45.605 +*N mux_tree_tapbuf_size5_3_sram[0]:14 *C 66.700 47.895 +*N mux_tree_tapbuf_size5_3_sram[0]:15 *C 66.700 47.940 +*N mux_tree_tapbuf_size5_3_sram[0]:16 *C 66.913 47.940 +*N mux_tree_tapbuf_size5_3_sram[0]:17 *C 71.300 47.940 +*N mux_tree_tapbuf_size5_3_sram[0]:18 *C 71.300 48.280 +*N mux_tree_tapbuf_size5_3_sram[0]:19 *C 86.020 48.280 +*N mux_tree_tapbuf_size5_3_sram[0]:20 *C 86.020 47.940 +*N mux_tree_tapbuf_size5_3_sram[0]:21 *C 89.240 47.940 +*N mux_tree_tapbuf_size5_3_sram[0]:22 *C 89.240 47.600 +*N mux_tree_tapbuf_size5_3_sram[0]:23 *C 97.475 47.600 +*N mux_tree_tapbuf_size5_3_sram[0]:24 *C 97.520 47.600 +*N mux_tree_tapbuf_size5_3_sram[0]:25 *C 97.520 44.585 +*N mux_tree_tapbuf_size5_3_sram[0]:26 *C 97.520 44.540 +*N mux_tree_tapbuf_size5_3_sram[0]:27 *C 97.825 44.540 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_17\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_3_sram[0]:4 5.982035e-05 +5 mux_tree_tapbuf_size5_3_sram[0]:5 0.0001214082 +6 mux_tree_tapbuf_size5_3_sram[0]:6 9.306942e-05 +7 mux_tree_tapbuf_size5_3_sram[0]:7 0.0001134858 +8 mux_tree_tapbuf_size5_3_sram[0]:8 0.0001134858 +9 mux_tree_tapbuf_size5_3_sram[0]:9 9.337431e-05 +10 mux_tree_tapbuf_size5_3_sram[0]:10 9.337431e-05 +11 mux_tree_tapbuf_size5_3_sram[0]:11 0.0001534989 +12 mux_tree_tapbuf_size5_3_sram[0]:12 2.853832e-05 +13 mux_tree_tapbuf_size5_3_sram[0]:13 0.0001536314 +14 mux_tree_tapbuf_size5_3_sram[0]:14 0.0001536314 +15 mux_tree_tapbuf_size5_3_sram[0]:15 5.300442e-05 +16 mux_tree_tapbuf_size5_3_sram[0]:16 0.0002983811 +17 mux_tree_tapbuf_size5_3_sram[0]:17 0.000304191 +18 mux_tree_tapbuf_size5_3_sram[0]:18 0.001064946 +19 mux_tree_tapbuf_size5_3_sram[0]:19 0.001066668 +20 mux_tree_tapbuf_size5_3_sram[0]:20 0.0001877153 +21 mux_tree_tapbuf_size5_3_sram[0]:21 0.0001842879 +22 mux_tree_tapbuf_size5_3_sram[0]:22 0.0004179795 +23 mux_tree_tapbuf_size5_3_sram[0]:23 0.0003938951 +24 mux_tree_tapbuf_size5_3_sram[0]:24 0.0003821088 +25 mux_tree_tapbuf_size5_3_sram[0]:25 0.0001941116 +26 mux_tree_tapbuf_size5_3_sram[0]:26 5.13048e-05 +27 mux_tree_tapbuf_size5_3_sram[0]:27 5.100603e-05 +28 mux_tree_tapbuf_size5_3_sram[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.458321e-05 +29 mux_tree_tapbuf_size5_3_sram[0]:23 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001305738 +30 mux_tree_tapbuf_size5_3_sram[0]:18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.543326e-07 +31 mux_tree_tapbuf_size5_3_sram[0]:19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.543326e-07 +32 mux_tree_tapbuf_size5_3_sram[0]:20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.64102e-05 +33 mux_tree_tapbuf_size5_3_sram[0]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.64102e-05 +34 mux_tree_tapbuf_size5_3_sram[0]:22 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001305738 +35 mux_tree_tapbuf_size5_3_sram[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.458321e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_3_sram[0]:27 0.152 +1 mux_tree_tapbuf_size5_3_sram[0]:12 mux_bottom_track_17\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_3_sram[0]:13 mux_tree_tapbuf_size5_3_sram[0]:12 0.0045 +3 mux_tree_tapbuf_size5_3_sram[0]:15 mux_tree_tapbuf_size5_3_sram[0]:14 0.0045 +4 mux_tree_tapbuf_size5_3_sram[0]:14 mux_tree_tapbuf_size5_3_sram[0]:13 0.002044643 +5 mux_tree_tapbuf_size5_3_sram[0]:4 mux_bottom_track_17\/mux_l1_in_1_:S 0.152 +6 mux_tree_tapbuf_size5_3_sram[0]:6 mux_tree_tapbuf_size5_3_sram[0]:5 0.0009107143 +7 mux_tree_tapbuf_size5_3_sram[0]:7 mux_tree_tapbuf_size5_3_sram[0]:6 0.0045 +8 mux_tree_tapbuf_size5_3_sram[0]:9 mux_tree_tapbuf_size5_3_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size5_3_sram[0]:8 mux_tree_tapbuf_size5_3_sram[0]:7 0.0014375 +10 mux_tree_tapbuf_size5_3_sram[0]:10 mux_tree_tapbuf_size5_3_sram[0]:9 0.001151786 +11 mux_tree_tapbuf_size5_3_sram[0]:11 mux_tree_tapbuf_size5_3_sram[0]:10 0.0045 +12 mux_tree_tapbuf_size5_3_sram[0]:23 mux_tree_tapbuf_size5_3_sram[0]:22 0.007352679 +13 mux_tree_tapbuf_size5_3_sram[0]:24 mux_tree_tapbuf_size5_3_sram[0]:23 0.0045 +14 mux_tree_tapbuf_size5_3_sram[0]:24 mux_tree_tapbuf_size5_3_sram[0]:11 0.002084821 +15 mux_tree_tapbuf_size5_3_sram[0]:26 mux_tree_tapbuf_size5_3_sram[0]:25 0.0045 +16 mux_tree_tapbuf_size5_3_sram[0]:25 mux_tree_tapbuf_size5_3_sram[0]:24 0.002691964 +17 mux_tree_tapbuf_size5_3_sram[0]:27 mux_tree_tapbuf_size5_3_sram[0]:26 0.0001657609 +18 mux_tree_tapbuf_size5_3_sram[0]:16 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size5_3_sram[0]:16 mux_tree_tapbuf_size5_3_sram[0]:15 0.0001154891 +20 mux_tree_tapbuf_size5_3_sram[0]:17 mux_tree_tapbuf_size5_3_sram[0]:16 0.003917411 +21 mux_tree_tapbuf_size5_3_sram[0]:18 mux_tree_tapbuf_size5_3_sram[0]:17 0.0003035715 +22 mux_tree_tapbuf_size5_3_sram[0]:19 mux_tree_tapbuf_size5_3_sram[0]:18 0.01314286 +23 mux_tree_tapbuf_size5_3_sram[0]:20 mux_tree_tapbuf_size5_3_sram[0]:19 0.0003035715 +24 mux_tree_tapbuf_size5_3_sram[0]:21 mux_tree_tapbuf_size5_3_sram[0]:20 0.002875 +25 mux_tree_tapbuf_size5_3_sram[0]:22 mux_tree_tapbuf_size5_3_sram[0]:21 0.0003035715 +26 mux_tree_tapbuf_size5_3_sram[0]:5 mux_tree_tapbuf_size5_3_sram[0]:4 0.0008772322 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_3_ccff_tail[0] 0.0006711592 //LENGTH 5.480 LUMPCC 8.952241e-05 DR + +*CONN +*I mem_right_track_0\/FTB_4__34:X O *L 0 *C 97.285 96.900 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.475 98.940 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 *C 94.475 98.940 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 *C 94.760 98.940 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 *C 94.760 98.895 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 *C 94.760 96.945 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 *C 94.805 96.900 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 *C 97.248 96.900 + +*CAP +0 mem_right_track_0\/FTB_4__34:X 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 4.329603e-05 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 4.713638e-05 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.0001236959 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0001236959 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 0.0001209063 +7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 0.0001209063 +8 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 right_top_grid_pin_48_[0]:27 4.47612e-05 +9 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 right_top_grid_pin_48_[0]:28 4.47612e-05 + +*RES +0 mem_right_track_0\/FTB_4__34:X mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.001741071 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 0.002180804 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009738805 //LENGTH 6.390 LUMPCC 0.0002963613 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 99.075 68.680 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 95.125 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 95.163 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 98.855 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 98.900 67.025 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 98.900 68.635 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 98.900 68.680 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 99.075 68.680 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000173179 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000173179 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001078541 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001078541 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.6678e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.677483e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001481806 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001481806 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003296875 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001371471 //LENGTH 11.700 LUMPCC 0.0002271484 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 66.875 63.580 +*I mux_top_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 61.545 69.020 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 61.583 69.020 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 63.435 69.020 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 63.480 68.975 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 63.480 63.625 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 63.525 63.580 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 66.838 63.580 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001446932 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001446932 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002006464 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002006464 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002258218 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002258218 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:241 3.390595e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:244 3.254466e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:244 3.390595e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:245 3.254466e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.052274e-06 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.052274e-06 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.40713e-05 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.40713e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00295759 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008948872 //LENGTH 7.770 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_2_:X O *L 0 *C 95.855 36.040 +*I mux_bottom_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 94.205 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 94.243 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 95.220 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 95.220 31.620 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 95.635 31.620 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 95.680 31.665 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 95.680 35.995 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 95.680 36.040 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 95.855 36.040 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.194847e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001030383 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.897042e-05 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.78806e-05 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002498617 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002498617 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.586279e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.546324e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_2_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003705357 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003866072 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 9.510871e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008727679 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0006071429 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.005645537 //LENGTH 46.785 LUMPCC 0.000620306 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_0_:X O *L 0 *C 59.515 28.220 +*I mux_bottom_track_3\/BUFT_P_145:A I *L 0.001746 *C 40.020 9.520 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 40.020 9.520 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 40.020 9.180 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 41.355 9.180 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 41.400 9.135 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 41.400 6.845 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 41.445 6.800 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 42.780 6.800 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 42.780 7.480 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 54.695 7.480 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 54.740 7.525 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 54.740 14.235 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 *C 54.785 14.280 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 *C 56.265 14.280 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 *C 56.185 14.325 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 *C 56.120 14.915 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 *C 56.165 14.960 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 *C 59.295 14.960 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 *C 59.340 15.005 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 *C 59.340 28.175 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:21 *C 59.340 28.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:22 *C 59.515 28.220 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_3\/BUFT_P_145:A 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.958637e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001424774 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001134689 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001678865 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001678865 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.353525e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001397304 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0008538153 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0008076202 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.000261835 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.000261835 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.0001063134 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.0001063134 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 4.518008e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 4.518008e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.0001853826 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 0.0001853826 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 0.0005769003 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 0.0005769003 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:21 6.474189e-05 +22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:22 6.125998e-05 +23 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 chany_top_in[4]:12 0.0001320814 +24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 chany_top_in[4]:13 0.0001320814 +25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 ropt_net_197:8 0.0001174621 +26 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 ropt_net_197:9 0.0001174621 +27 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 ropt_net_220:5 6.060945e-05 +28 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 ropt_net_220:4 6.060945e-05 + +*RES +0 mux_bottom_track_3\/mux_l3_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:22 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3\/BUFT_P_145:A 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.001191964 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.002044643 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.01063839 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0045 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0045 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.005991071 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.001321429 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.0045 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.0045 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 0.0005267857 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.002794643 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 0.0045 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 0.0045 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 0.01175893 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:21 9.51087e-05 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003035715 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.001191964 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0006071429 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008651558 //LENGTH 6.310 LUMPCC 0.0002440699 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_1_:X O *L 0 *C 76.995 119.000 +*I mux_right_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.315 120.700 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 73.353 120.700 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 76.315 120.700 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 76.360 120.655 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 76.360 119.045 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 76.405 119.000 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 76.958 119.000 + +*CAP +0 mux_right_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001245 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001245 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001094552 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001094552 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.558775e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.558775e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_0_sram[1]:13 5.072093e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_0_sram[1]:14 7.131402e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_0_sram[1]:14 5.072093e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_0_sram[1]:15 7.131402e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00264509 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000564897 //LENGTH 4.270 LUMPCC 7.807821e-05 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_1_:X O *L 0 *C 90.905 79.900 +*I mux_right_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 91.715 77.180 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 91.678 77.180 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 91.125 77.180 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 91.080 77.225 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 91.080 79.855 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 91.080 79.900 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 90.905 79.900 + +*CAP +0 mux_right_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.582055e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.582055e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001562253 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001562253 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.008533e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.064167e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 prog_clk[0]:90 3.524938e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 prog_clk[0]:91 3.524938e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:96 3.789717e-06 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:93 3.789717e-06 + +*RES +0 mux_right_track_16\/mux_l1_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_227 0.001045787 //LENGTH 8.010 LUMPCC 0.000414883 DR + +*CONN +*I ropt_mt_inst_818:X O *L 0 *C 61.180 3.400 +*I ropt_mt_inst_847:A I *L 0.001766 *C 57.500 6.800 +*N ropt_net_227:2 *C 57.538 6.800 +*N ropt_net_227:3 *C 58.835 6.800 +*N ropt_net_227:4 *C 58.880 6.755 +*N ropt_net_227:5 *C 58.880 3.445 +*N ropt_net_227:6 *C 58.925 3.400 +*N ropt_net_227:7 *C 61.143 3.400 + +*CAP +0 ropt_mt_inst_818:X 1e-06 +1 ropt_mt_inst_847:A 1e-06 +2 ropt_net_227:2 5.574065e-05 +3 ropt_net_227:3 5.574065e-05 +4 ropt_net_227:4 7.967176e-05 +5 ropt_net_227:5 7.967176e-05 +6 ropt_net_227:6 0.0001790397 +7 ropt_net_227:7 0.0001790397 +8 ropt_net_227:2 ropt_net_194:6 6.139318e-05 +9 ropt_net_227:3 ropt_net_194:7 6.139318e-05 +10 ropt_net_227:4 ropt_net_194:5 7.488023e-08 +11 ropt_net_227:5 ropt_net_194:4 7.488023e-08 +12 ropt_net_227:4 chany_bottom_out[4]:6 0.0001006274 +13 ropt_net_227:5 chany_bottom_out[4]:5 0.0001006274 +14 ropt_net_227:4 ccff_tail[0]:6 4.534607e-05 +15 ropt_net_227:5 ccff_tail[0]:5 4.534607e-05 + +*RES +0 ropt_mt_inst_818:X ropt_net_227:7 0.152 +1 ropt_net_227:2 ropt_mt_inst_847:A 0.152 +2 ropt_net_227:3 ropt_net_227:2 0.001158482 +3 ropt_net_227:4 ropt_net_227:3 0.0045 +4 ropt_net_227:6 ropt_net_227:5 0.0045 +5 ropt_net_227:5 ropt_net_227:4 0.002955358 +6 ropt_net_227:7 ropt_net_227:6 0.001979911 + +*END + +*D_NET chany_top_out[14] 0.0007534956 //LENGTH 6.560 LUMPCC 7.654284e-05 DR + +*CONN +*I ropt_mt_inst_841:X O *L 0 *C 8.280 125.800 +*P chany_top_out[14] O *L 0.7423 *C 7.360 129.350 +*N chany_top_out[14]:2 *C 7.360 128.528 +*N chany_top_out[14]:3 *C 7.380 128.520 +*N chany_top_out[14]:4 *C 8.732 128.520 +*N chany_top_out[14]:5 *C 8.740 128.463 +*N chany_top_out[14]:6 *C 8.740 125.845 +*N chany_top_out[14]:7 *C 8.695 125.800 +*N chany_top_out[14]:8 *C 8.318 125.800 + +*CAP +0 ropt_mt_inst_841:X 1e-06 +1 chany_top_out[14] 7.195074e-05 +2 chany_top_out[14]:2 7.195074e-05 +3 chany_top_out[14]:3 0.0001052488 +4 chany_top_out[14]:4 0.0001052488 +5 chany_top_out[14]:5 0.0001169945 +6 chany_top_out[14]:6 0.0001169945 +7 chany_top_out[14]:7 4.378238e-05 +8 chany_top_out[14]:8 4.378238e-05 +9 chany_top_out[14]:8 ropt_net_221:4 2.829482e-06 +10 chany_top_out[14]:7 ropt_net_221:5 2.829482e-06 +11 chany_top_out[14]:6 ropt_net_221:7 3.544194e-05 +12 chany_top_out[14]:5 ropt_net_221:6 3.544194e-05 + +*RES +0 ropt_mt_inst_841:X chany_top_out[14]:8 0.152 +1 chany_top_out[14]:8 chany_top_out[14]:7 0.0003370536 +2 chany_top_out[14]:7 chany_top_out[14]:6 0.0045 +3 chany_top_out[14]:6 chany_top_out[14]:5 0.002337054 +4 chany_top_out[14]:5 chany_top_out[14]:4 0.00341 +5 chany_top_out[14]:4 chany_top_out[14]:3 0.0002118916 +6 chany_top_out[14]:3 chany_top_out[14]:2 0.00341 +7 chany_top_out[14]:2 chany_top_out[14] 0.0001288583 + +*END + +*D_NET mem_bottom_track_33/net_net_101 0.002612627 //LENGTH 21.805 LUMPCC 0.0002047205 DR + +*CONN +*I mem_bottom_track_33\/FTB_27__57:X O *L 0 *C 40.255 22.440 +*I mem_bottom_track_33\/BUFT_P_168:A I *L 0.001746 *C 51.060 12.240 +*N mem_bottom_track_33/net_net_101:2 *C 51.060 12.240 +*N mem_bottom_track_33/net_net_101:3 *C 51.060 12.580 +*N mem_bottom_track_33/net_net_101:4 *C 40.525 12.580 +*N mem_bottom_track_33/net_net_101:5 *C 40.480 12.625 +*N mem_bottom_track_33/net_net_101:6 *C 40.480 22.395 +*N mem_bottom_track_33/net_net_101:7 *C 40.480 22.440 +*N mem_bottom_track_33/net_net_101:8 *C 40.255 22.440 + +*CAP +0 mem_bottom_track_33\/FTB_27__57:X 1e-06 +1 mem_bottom_track_33\/BUFT_P_168:A 1e-06 +2 mem_bottom_track_33/net_net_101:2 5.997501e-05 +3 mem_bottom_track_33/net_net_101:3 0.0007045624 +4 mem_bottom_track_33/net_net_101:4 0.000675266 +5 mem_bottom_track_33/net_net_101:5 0.0004318693 +6 mem_bottom_track_33/net_net_101:6 0.0004318693 +7 mem_bottom_track_33/net_net_101:7 4.894479e-05 +8 mem_bottom_track_33/net_net_101:8 5.341994e-05 +9 mem_bottom_track_33/net_net_101:5 chany_top_in[8]:10 0.0001023602 +10 mem_bottom_track_33/net_net_101:6 chany_top_in[8]:11 0.0001023602 + +*RES +0 mem_bottom_track_33\/FTB_27__57:X mem_bottom_track_33/net_net_101:8 0.152 +1 mem_bottom_track_33/net_net_101:2 mem_bottom_track_33\/BUFT_P_168:A 0.152 +2 mem_bottom_track_33/net_net_101:4 mem_bottom_track_33/net_net_101:3 0.009406251 +3 mem_bottom_track_33/net_net_101:5 mem_bottom_track_33/net_net_101:4 0.0045 +4 mem_bottom_track_33/net_net_101:7 mem_bottom_track_33/net_net_101:6 0.0045 +5 mem_bottom_track_33/net_net_101:6 mem_bottom_track_33/net_net_101:5 0.008723215 +6 mem_bottom_track_33/net_net_101:8 mem_bottom_track_33/net_net_101:7 0.0001222826 +7 mem_bottom_track_33/net_net_101:3 mem_bottom_track_33/net_net_101:2 0.0003035715 + +*END + +*D_NET chany_top_in[8] 0.02050106 //LENGTH 177.160 LUMPCC 0.00228844 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 63.020 129.235 +*I mux_bottom_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 67.160 45.220 +*I ropt_mt_inst_828:A I *L 0.001766 *C 27.600 4.080 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 104.040 +*N chany_top_in[8]:4 *C 55.068 104.040 +*N chany_top_in[8]:5 *C 27.600 4.080 +*N chany_top_in[8]:6 *C 27.600 3.740 +*N chany_top_in[8]:7 *C 38.595 3.740 +*N chany_top_in[8]:8 *C 38.640 3.785 +*N chany_top_in[8]:9 *C 38.640 11.560 +*N chany_top_in[8]:10 *C 39.560 11.560 +*N chany_top_in[8]:11 *C 39.560 19.663 +*N chany_top_in[8]:12 *C 39.568 19.720 +*N chany_top_in[8]:13 *C 56.573 19.720 +*N chany_top_in[8]:14 *C 56.580 19.777 +*N chany_top_in[8]:15 *C 67.123 45.220 +*N chany_top_in[8]:16 *C 64.905 45.220 +*N chany_top_in[8]:17 *C 64.860 45.220 +*N chany_top_in[8]:18 *C 64.860 45.560 +*N chany_top_in[8]:19 *C 64.853 45.560 +*N chany_top_in[8]:20 *C 56.588 45.560 +*N chany_top_in[8]:21 *C 56.580 45.560 +*N chany_top_in[8]:22 *C 56.580 95.560 +*N chany_top_in[8]:23 *C 56.580 103.995 +*N chany_top_in[8]:24 *C 56.580 104.040 +*N chany_top_in[8]:25 *C 57.915 104.040 +*N chany_top_in[8]:26 *C 57.960 104.085 +*N chany_top_in[8]:27 *C 57.960 128.815 +*N chany_top_in[8]:28 *C 58.005 128.860 +*N chany_top_in[8]:29 *C 62.975 128.860 +*N chany_top_in[8]:30 *C 63.020 128.905 + +*CAP +0 chany_top_in[8] 3.364576e-05 +1 mux_bottom_track_17\/mux_l1_in_0_:A1 1e-06 +2 ropt_mt_inst_828:A 1e-06 +3 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[8]:4 0.0001074573 +5 chany_top_in[8]:5 5.825342e-05 +6 chany_top_in[8]:6 0.0005773483 +7 chany_top_in[8]:7 0.0005487784 +8 chany_top_in[8]:8 0.0003612988 +9 chany_top_in[8]:9 0.0004082829 +10 chany_top_in[8]:10 0.0003624343 +11 chany_top_in[8]:11 0.0003154502 +12 chany_top_in[8]:12 0.001155602 +13 chany_top_in[8]:13 0.001155602 +14 chany_top_in[8]:14 0.001127248 +15 chany_top_in[8]:15 0.0001578591 +16 chany_top_in[8]:16 0.0001578591 +17 chany_top_in[8]:17 5.3887e-05 +18 chany_top_in[8]:18 5.802526e-05 +19 chany_top_in[8]:19 0.0005940484 +20 chany_top_in[8]:20 0.0005940484 +21 chany_top_in[8]:21 0.003598504 +22 chany_top_in[8]:22 0.002790561 +23 chany_top_in[8]:23 0.0003568522 +24 chany_top_in[8]:24 0.0002463971 +25 chany_top_in[8]:25 9.763081e-05 +26 chany_top_in[8]:26 0.001333004 +27 chany_top_in[8]:27 0.001333004 +28 chany_top_in[8]:28 0.0002964474 +29 chany_top_in[8]:29 0.0002964474 +30 chany_top_in[8]:30 3.364576e-05 +31 chany_top_in[8]:26 prog_clk[0]:273 3.073093e-07 +32 chany_top_in[8]:27 prog_clk[0]:269 3.073093e-07 +33 chany_top_in[8]:14 prog_clk[0]:440 8.232238e-07 +34 chany_top_in[8]:23 prog_clk[0]:269 2.013172e-05 +35 chany_top_in[8]:23 prog_clk[0]:276 1.632988e-05 +36 chany_top_in[8]:23 prog_clk[0]:273 7.008115e-05 +37 chany_top_in[8]:21 prog_clk[0]:300 3.312841e-06 +38 chany_top_in[8]:21 prog_clk[0]:290 3.281544e-06 +39 chany_top_in[8]:21 prog_clk[0]:287 4.019215e-06 +40 chany_top_in[8]:21 prog_clk[0]:441 8.232238e-07 +41 chany_top_in[8]:21 prog_clk[0]:249 7.677562e-05 +42 chany_top_in[8]:21 prog_clk[0]:299 3.075273e-06 +43 chany_top_in[8]:21 prog_clk[0]:282 5.750934e-05 +44 chany_top_in[8]:21 prog_clk[0]:288 4.524094e-05 +45 chany_top_in[8]:22 prog_clk[0]:276 0.0001275905 +46 chany_top_in[8]:22 prog_clk[0]:273 2.013172e-05 +47 chany_top_in[8]:22 prog_clk[0]:250 7.677562e-05 +48 chany_top_in[8]:22 prog_clk[0]:296 3.075273e-06 +49 chany_top_in[8]:22 prog_clk[0]:299 3.312841e-06 +50 chany_top_in[8]:22 prog_clk[0]:282 1.632988e-05 +51 chany_top_in[8]:22 prog_clk[0]:289 3.281544e-06 +52 chany_top_in[8]:22 prog_clk[0]:288 4.019215e-06 +53 chany_top_in[8]:22 prog_clk[0]:283 4.524094e-05 +54 chany_top_in[8]:7 ropt_net_192:3 0.0001511994 +55 chany_top_in[8]:8 ropt_net_192:4 1.285716e-05 +56 chany_top_in[8]:6 ropt_net_192:2 0.0001511994 +57 chany_top_in[8]:9 ropt_net_192:5 1.285716e-05 +58 chany_top_in[8]:14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.214815e-06 +59 chany_top_in[8]:21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.6281e-05 +60 chany_top_in[8]:21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.214815e-06 +61 chany_top_in[8]:22 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.6281e-05 +62 chany_top_in[8]:14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002856173 +63 chany_top_in[8]:21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002856173 +64 chany_top_in[8]:21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.976634e-05 +65 chany_top_in[8]:21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.223657e-05 +66 chany_top_in[8]:22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.976634e-05 +67 chany_top_in[8]:22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.223657e-05 +68 chany_top_in[8]:7 ropt_net_237:8 4.652979e-05 +69 chany_top_in[8]:6 ropt_net_237:9 4.652979e-05 +70 chany_top_in[8]:11 ropt_net_203:5 3.294002e-06 +71 chany_top_in[8]:7 ropt_net_203:3 6.358125e-05 +72 chany_top_in[8]:8 ropt_net_203:4 1.439405e-05 +73 chany_top_in[8]:6 ropt_net_203:2 6.358125e-05 +74 chany_top_in[8]:9 ropt_net_203:5 1.439405e-05 +75 chany_top_in[8]:10 ropt_net_203:4 3.294002e-06 +76 chany_top_in[8]:11 mem_bottom_track_33/net_net_101:6 0.0001023602 +77 chany_top_in[8]:10 mem_bottom_track_33/net_net_101:5 0.0001023602 + +*RES +0 chany_top_in[8] chany_top_in[8]:30 0.0002946429 +1 chany_top_in[8]:25 chany_top_in[8]:24 0.001191964 +2 chany_top_in[8]:26 chany_top_in[8]:25 0.0045 +3 chany_top_in[8]:28 chany_top_in[8]:27 0.0045 +4 chany_top_in[8]:27 chany_top_in[8]:26 0.02208036 +5 chany_top_in[8]:29 chany_top_in[8]:28 0.0044375 +6 chany_top_in[8]:30 chany_top_in[8]:29 0.0045 +7 chany_top_in[8]:14 chany_top_in[8]:13 0.00341 +8 chany_top_in[8]:13 chany_top_in[8]:12 0.002664117 +9 chany_top_in[8]:11 chany_top_in[8]:10 0.007234375 +10 chany_top_in[8]:12 chany_top_in[8]:11 0.00341 +11 chany_top_in[8]:7 chany_top_in[8]:6 0.009816965 +12 chany_top_in[8]:8 chany_top_in[8]:7 0.0045 +13 chany_top_in[8]:5 ropt_mt_inst_828:A 0.152 +14 chany_top_in[8]:4 mux_right_track_8\/mux_l1_in_0_:A0 0.152 +15 chany_top_in[8]:24 chany_top_in[8]:23 0.0045 +16 chany_top_in[8]:24 chany_top_in[8]:4 0.001350446 +17 chany_top_in[8]:23 chany_top_in[8]:22 0.00753125 +18 chany_top_in[8]:21 chany_top_in[8]:20 0.00341 +19 chany_top_in[8]:21 chany_top_in[8]:14 0.02302009 +20 chany_top_in[8]:20 chany_top_in[8]:19 0.00129485 +21 chany_top_in[8]:18 chany_top_in[8]:17 0.0001634615 +22 chany_top_in[8]:19 chany_top_in[8]:18 0.00341 +23 chany_top_in[8]:16 chany_top_in[8]:15 0.001979911 +24 chany_top_in[8]:17 chany_top_in[8]:16 0.0045 +25 chany_top_in[8]:15 mux_bottom_track_17\/mux_l1_in_0_:A1 0.152 +26 chany_top_in[8]:6 chany_top_in[8]:5 0.0003035715 +27 chany_top_in[8]:9 chany_top_in[8]:8 0.006941964 +28 chany_top_in[8]:10 chany_top_in[8]:9 0.0008214285 +29 chany_top_in[8]:22 chany_top_in[8]:21 0.04464286 + +*END + +*D_NET chanx_right_in[18] 0.009858004 //LENGTH 81.565 LUMPCC 0.0006652052 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 111.930 65.280 +*I mux_bottom_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 62.465 36.380 +*I mux_top_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 70.670 55.080 +*N chanx_right_in[18]:3 *C 70.633 55.080 +*N chanx_right_in[18]:4 *C 62.503 36.380 +*N chanx_right_in[18]:5 *C 63.895 36.380 +*N chanx_right_in[18]:6 *C 63.940 36.425 +*N chanx_right_in[18]:7 *C 63.940 55.035 +*N chanx_right_in[18]:8 *C 63.985 55.080 +*N chanx_right_in[18]:9 *C 69.920 55.080 +*N chanx_right_in[18]:10 *C 69.920 55.420 +*N chanx_right_in[18]:11 *C 72.635 55.420 +*N chanx_right_in[18]:12 *C 72.680 55.465 +*N chanx_right_in[18]:13 *C 72.680 58.435 +*N chanx_right_in[18]:14 *C 72.725 58.480 +*N chanx_right_in[18]:15 *C 75.855 58.480 +*N chanx_right_in[18]:16 *C 75.900 58.525 +*N chanx_right_in[18]:17 *C 75.900 65.222 +*N chanx_right_in[18]:18 *C 75.907 65.280 + +*CAP +0 chanx_right_in[18] 0.001949006 +1 mux_bottom_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_8\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[18]:3 2.98384e-05 +4 chanx_right_in[18]:4 0.0001399084 +5 chanx_right_in[18]:5 0.0001399084 +6 chanx_right_in[18]:6 0.001046045 +7 chanx_right_in[18]:7 0.001046045 +8 chanx_right_in[18]:8 0.0003905518 +9 chanx_right_in[18]:9 0.0004455234 +10 chanx_right_in[18]:10 0.0002400886 +11 chanx_right_in[18]:11 0.0002149554 +12 chanx_right_in[18]:12 0.0001953822 +13 chanx_right_in[18]:13 0.0001953822 +14 chanx_right_in[18]:14 0.000199651 +15 chanx_right_in[18]:15 0.000199651 +16 chanx_right_in[18]:16 0.0004049285 +17 chanx_right_in[18]:17 0.0004049285 +18 chanx_right_in[18]:18 0.001949006 +19 chanx_right_in[18] chanx_right_in[5]:12 0.0003326026 +20 chanx_right_in[18]:18 chanx_right_in[5]:11 0.0003326026 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:18 0.005643525 +1 chanx_right_in[18]:11 chanx_right_in[18]:10 0.002424107 +2 chanx_right_in[18]:12 chanx_right_in[18]:11 0.0045 +3 chanx_right_in[18]:14 chanx_right_in[18]:13 0.0045 +4 chanx_right_in[18]:13 chanx_right_in[18]:12 0.002651786 +5 chanx_right_in[18]:15 chanx_right_in[18]:14 0.002794643 +6 chanx_right_in[18]:16 chanx_right_in[18]:15 0.0045 +7 chanx_right_in[18]:17 chanx_right_in[18]:16 0.00597991 +8 chanx_right_in[18]:18 chanx_right_in[18]:17 0.00341 +9 chanx_right_in[18]:8 chanx_right_in[18]:7 0.0045 +10 chanx_right_in[18]:7 chanx_right_in[18]:6 0.01661607 +11 chanx_right_in[18]:5 chanx_right_in[18]:4 0.001243304 +12 chanx_right_in[18]:6 chanx_right_in[18]:5 0.0045 +13 chanx_right_in[18]:4 mux_bottom_track_3\/mux_l2_in_1_:A1 0.152 +14 chanx_right_in[18]:3 mux_top_track_8\/mux_l1_in_1_:A0 0.152 +15 chanx_right_in[18]:9 chanx_right_in[18]:8 0.005299108 +16 chanx_right_in[18]:9 chanx_right_in[18]:3 0.0006361608 +17 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0003035715 + +*END + +*D_NET bottom_left_grid_pin_1_[0] 0.01827813 //LENGTH 135.425 LUMPCC 0.005334426 DR + +*CONN +*P bottom_left_grid_pin_1_[0] I *L 0.29796 *C 2.300 1.290 +*I mux_bottom_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 85.850 33.660 +*I mux_bottom_track_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 97.775 37.060 +*I mux_bottom_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 49.050 31.960 +*N bottom_left_grid_pin_1_[0]:4 *C 49.050 31.960 +*N bottom_left_grid_pin_1_[0]:5 *C 48.760 31.960 +*N bottom_left_grid_pin_1_[0]:6 *C 48.760 31.915 +*N bottom_left_grid_pin_1_[0]:7 *C 97.738 37.060 +*N bottom_left_grid_pin_1_[0]:8 *C 94.805 37.060 +*N bottom_left_grid_pin_1_[0]:9 *C 94.760 37.015 +*N bottom_left_grid_pin_1_[0]:10 *C 94.760 33.705 +*N bottom_left_grid_pin_1_[0]:11 *C 94.715 33.660 +*N bottom_left_grid_pin_1_[0]:12 *C 85.850 33.660 +*N bottom_left_grid_pin_1_[0]:13 *C 86.065 33.660 +*N bottom_left_grid_pin_1_[0]:14 *C 86.020 33.615 +*N bottom_left_grid_pin_1_[0]:15 *C 86.020 30.658 +*N bottom_left_grid_pin_1_[0]:16 *C 86.013 30.600 +*N bottom_left_grid_pin_1_[0]:17 *C 48.768 30.600 +*N bottom_left_grid_pin_1_[0]:18 *C 48.760 30.600 +*N bottom_left_grid_pin_1_[0]:19 *C 48.715 30.600 +*N bottom_left_grid_pin_1_[0]:20 *C 2.345 30.600 +*N bottom_left_grid_pin_1_[0]:21 *C 2.300 30.555 + +*CAP +0 bottom_left_grid_pin_1_[0] 0.001239655 +1 mux_bottom_track_5\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_track_9\/mux_l1_in_2_:A0 1e-06 +3 mux_bottom_track_1\/mux_l1_in_2_:A0 1e-06 +4 bottom_left_grid_pin_1_[0]:4 5.522568e-05 +5 bottom_left_grid_pin_1_[0]:5 5.934704e-05 +6 bottom_left_grid_pin_1_[0]:6 9.456762e-05 +7 bottom_left_grid_pin_1_[0]:7 0.0002231197 +8 bottom_left_grid_pin_1_[0]:8 0.0002231197 +9 bottom_left_grid_pin_1_[0]:9 0.0002020736 +10 bottom_left_grid_pin_1_[0]:10 0.0002020736 +11 bottom_left_grid_pin_1_[0]:11 0.0005207755 +12 bottom_left_grid_pin_1_[0]:12 4.748734e-05 +13 bottom_left_grid_pin_1_[0]:13 0.0005394046 +14 bottom_left_grid_pin_1_[0]:14 0.0001845962 +15 bottom_left_grid_pin_1_[0]:15 0.0001845962 +16 bottom_left_grid_pin_1_[0]:16 0.001162751 +17 bottom_left_grid_pin_1_[0]:17 0.001162751 +18 bottom_left_grid_pin_1_[0]:18 0.0001326004 +19 bottom_left_grid_pin_1_[0]:19 0.002733452 +20 bottom_left_grid_pin_1_[0]:20 0.002733452 +21 bottom_left_grid_pin_1_[0]:21 0.001239655 +22 bottom_left_grid_pin_1_[0]:17 chany_bottom_in[11]:16 0.000365798 +23 bottom_left_grid_pin_1_[0]:17 chany_bottom_in[11]:18 0.0002351232 +24 bottom_left_grid_pin_1_[0]:16 chany_bottom_in[11]:15 0.000365798 +25 bottom_left_grid_pin_1_[0]:16 chany_bottom_in[11]:17 0.0002351232 +26 bottom_left_grid_pin_1_[0]:19 chanx_right_in[19]:10 8.427329e-06 +27 bottom_left_grid_pin_1_[0]:18 chanx_right_in[19]:9 8.111515e-06 +28 bottom_left_grid_pin_1_[0]:20 chanx_right_in[19]:6 8.427329e-06 +29 bottom_left_grid_pin_1_[0]:17 chanx_right_in[19]:6 3.316542e-05 +30 bottom_left_grid_pin_1_[0]:17 chanx_right_in[19]:10 0.002016588 +31 bottom_left_grid_pin_1_[0]:16 chanx_right_in[19]:10 3.316542e-05 +32 bottom_left_grid_pin_1_[0]:16 chanx_right_in[19]:11 0.002016588 +33 bottom_left_grid_pin_1_[0]:6 chanx_right_in[19]:8 8.111515e-06 + +*RES +0 bottom_left_grid_pin_1_[0] bottom_left_grid_pin_1_[0]:21 0.02612947 +1 bottom_left_grid_pin_1_[0]:19 bottom_left_grid_pin_1_[0]:18 0.0045 +2 bottom_left_grid_pin_1_[0]:18 bottom_left_grid_pin_1_[0]:17 0.00341 +3 bottom_left_grid_pin_1_[0]:18 bottom_left_grid_pin_1_[0]:6 0.001174107 +4 bottom_left_grid_pin_1_[0]:20 bottom_left_grid_pin_1_[0]:19 0.04140179 +5 bottom_left_grid_pin_1_[0]:21 bottom_left_grid_pin_1_[0]:20 0.0045 +6 bottom_left_grid_pin_1_[0]:17 bottom_left_grid_pin_1_[0]:16 0.00583505 +7 bottom_left_grid_pin_1_[0]:15 bottom_left_grid_pin_1_[0]:14 0.002640625 +8 bottom_left_grid_pin_1_[0]:16 bottom_left_grid_pin_1_[0]:15 0.00341 +9 bottom_left_grid_pin_1_[0]:13 bottom_left_grid_pin_1_[0]:12 0.0001168478 +10 bottom_left_grid_pin_1_[0]:13 bottom_left_grid_pin_1_[0]:11 0.007723214 +11 bottom_left_grid_pin_1_[0]:14 bottom_left_grid_pin_1_[0]:13 0.0045 +12 bottom_left_grid_pin_1_[0]:12 mux_bottom_track_5\/mux_l1_in_2_:A0 0.152 +13 bottom_left_grid_pin_1_[0]:5 bottom_left_grid_pin_1_[0]:4 0.0001576087 +14 bottom_left_grid_pin_1_[0]:6 bottom_left_grid_pin_1_[0]:5 0.0045 +15 bottom_left_grid_pin_1_[0]:4 mux_bottom_track_1\/mux_l1_in_2_:A0 0.152 +16 bottom_left_grid_pin_1_[0]:7 mux_bottom_track_9\/mux_l1_in_2_:A0 0.152 +17 bottom_left_grid_pin_1_[0]:8 bottom_left_grid_pin_1_[0]:7 0.002618304 +18 bottom_left_grid_pin_1_[0]:9 bottom_left_grid_pin_1_[0]:8 0.0045 +19 bottom_left_grid_pin_1_[0]:11 bottom_left_grid_pin_1_[0]:10 0.0045 +20 bottom_left_grid_pin_1_[0]:10 bottom_left_grid_pin_1_[0]:9 0.002955358 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.002173174 //LENGTH 15.145 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 93.685 85.680 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.795 82.620 +*I mux_right_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 90.060 79.950 +*I mux_right_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 85.920 79.560 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 85.958 79.560 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 90.060 79.560 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 90.060 79.950 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 90.160 80.240 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 90.160 80.285 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 90.160 82.575 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 90.205 82.620 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 90.795 82.620 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 93.335 82.620 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 93.380 82.665 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 93.380 85.635 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 93.380 85.680 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 93.685 85.680 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_16\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 0.0003230965 +5 mux_tree_tapbuf_size3_0_sram[0]:5 0.0003486097 +6 mux_tree_tapbuf_size3_0_sram[0]:6 7.946024e-05 +7 mux_tree_tapbuf_size3_0_sram[0]:7 5.737742e-05 +8 mux_tree_tapbuf_size3_0_sram[0]:8 0.0001443057 +9 mux_tree_tapbuf_size3_0_sram[0]:9 0.0001443057 +10 mux_tree_tapbuf_size3_0_sram[0]:10 6.388072e-05 +11 mux_tree_tapbuf_size3_0_sram[0]:11 0.0003145967 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0002205693 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0001783576 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0001783576 +15 mux_tree_tapbuf_size3_0_sram[0]:15 5.880597e-05 +16 mux_tree_tapbuf_size3_0_sram[0]:16 5.745107e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:16 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.002267857 +2 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.0045 +3 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.0045 +4 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.002651786 +5 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0001657609 +6 mux_tree_tapbuf_size3_0_sram[0]:6 mux_right_track_16\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0003482143 +8 mux_tree_tapbuf_size3_0_sram[0]:11 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.0005267857 +10 mux_tree_tapbuf_size3_0_sram[0]:4 mux_right_track_16\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size3_0_sram[0]:10 mux_tree_tapbuf_size3_0_sram[0]:9 0.0045 +12 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.002044643 +13 mux_tree_tapbuf_size3_0_sram[0]:7 mux_tree_tapbuf_size3_0_sram[0]:6 0.0002589286 +14 mux_tree_tapbuf_size3_0_sram[0]:8 mux_tree_tapbuf_size3_0_sram[0]:7 0.0045 +15 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 0.003662946 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[0] 0.002709821 //LENGTH 23.140 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 55.505 109.820 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 53.920 105.400 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 41.115 113.220 +*N mux_tree_tapbuf_size4_2_sram[0]:3 *C 41.153 113.220 +*N mux_tree_tapbuf_size4_2_sram[0]:4 *C 53.775 113.220 +*N mux_tree_tapbuf_size4_2_sram[0]:5 *C 53.820 113.175 +*N mux_tree_tapbuf_size4_2_sram[0]:6 *C 53.820 105.400 +*N mux_tree_tapbuf_size4_2_sram[0]:7 *C 53.820 105.445 +*N mux_tree_tapbuf_size4_2_sram[0]:8 *C 53.820 109.820 +*N mux_tree_tapbuf_size4_2_sram[0]:9 *C 53.865 109.820 +*N mux_tree_tapbuf_size4_2_sram[0]:10 *C 55.468 109.820 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size4_2_sram[0]:3 0.0007625472 +4 mux_tree_tapbuf_size4_2_sram[0]:4 0.0007625472 +5 mux_tree_tapbuf_size4_2_sram[0]:5 0.0001908265 +6 mux_tree_tapbuf_size4_2_sram[0]:6 3.37925e-05 +7 mux_tree_tapbuf_size4_2_sram[0]:7 0.0002577595 +8 mux_tree_tapbuf_size4_2_sram[0]:8 0.0004779974 +9 mux_tree_tapbuf_size4_2_sram[0]:9 0.0001106753 +10 mux_tree_tapbuf_size4_2_sram[0]:10 0.0001106753 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_2_sram[0]:10 0.152 +1 mux_tree_tapbuf_size4_2_sram[0]:4 mux_tree_tapbuf_size4_2_sram[0]:3 0.01127009 +2 mux_tree_tapbuf_size4_2_sram[0]:5 mux_tree_tapbuf_size4_2_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size4_2_sram[0]:3 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size4_2_sram[0]:9 mux_tree_tapbuf_size4_2_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size4_2_sram[0]:8 mux_tree_tapbuf_size4_2_sram[0]:7 0.00390625 +6 mux_tree_tapbuf_size4_2_sram[0]:8 mux_tree_tapbuf_size4_2_sram[0]:5 0.002995536 +7 mux_tree_tapbuf_size4_2_sram[0]:10 mux_tree_tapbuf_size4_2_sram[0]:9 0.001430804 +8 mux_tree_tapbuf_size4_2_sram[0]:6 mux_right_track_8\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size4_2_sram[0]:7 mux_tree_tapbuf_size4_2_sram[0]:6 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size4_6_sram[0] 0.002344114 //LENGTH 20.175 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 35.265 66.300 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 22.255 60.860 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 30.920 63.630 +*N mux_tree_tapbuf_size4_6_sram[0]:3 *C 30.920 63.630 +*N mux_tree_tapbuf_size4_6_sram[0]:4 *C 22.293 60.860 +*N mux_tree_tapbuf_size4_6_sram[0]:5 *C 22.955 60.860 +*N mux_tree_tapbuf_size4_6_sram[0]:6 *C 23.000 60.905 +*N mux_tree_tapbuf_size4_6_sram[0]:7 *C 23.000 63.875 +*N mux_tree_tapbuf_size4_6_sram[0]:8 *C 23.045 63.920 +*N mux_tree_tapbuf_size4_6_sram[0]:9 *C 30.920 63.920 +*N mux_tree_tapbuf_size4_6_sram[0]:10 *C 34.915 63.920 +*N mux_tree_tapbuf_size4_6_sram[0]:11 *C 34.960 63.965 +*N mux_tree_tapbuf_size4_6_sram[0]:12 *C 34.960 66.255 +*N mux_tree_tapbuf_size4_6_sram[0]:13 *C 34.960 66.300 +*N mux_tree_tapbuf_size4_6_sram[0]:14 *C 35.265 66.300 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_6_sram[0]:3 5.339322e-05 +4 mux_tree_tapbuf_size4_6_sram[0]:4 6.302071e-05 +5 mux_tree_tapbuf_size4_6_sram[0]:5 6.302071e-05 +6 mux_tree_tapbuf_size4_6_sram[0]:6 0.0001736571 +7 mux_tree_tapbuf_size4_6_sram[0]:7 0.0001736571 +8 mux_tree_tapbuf_size4_6_sram[0]:8 0.0004306888 +9 mux_tree_tapbuf_size4_6_sram[0]:9 0.0007023211 +10 mux_tree_tapbuf_size4_6_sram[0]:10 0.0002445074 +11 mux_tree_tapbuf_size4_6_sram[0]:11 0.0001679031 +12 mux_tree_tapbuf_size4_6_sram[0]:12 0.0001679031 +13 mux_tree_tapbuf_size4_6_sram[0]:13 5.284579e-05 +14 mux_tree_tapbuf_size4_6_sram[0]:14 4.819655e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_6_sram[0]:14 0.152 +1 mux_tree_tapbuf_size4_6_sram[0]:10 mux_tree_tapbuf_size4_6_sram[0]:9 0.003566965 +2 mux_tree_tapbuf_size4_6_sram[0]:11 mux_tree_tapbuf_size4_6_sram[0]:10 0.0045 +3 mux_tree_tapbuf_size4_6_sram[0]:13 mux_tree_tapbuf_size4_6_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size4_6_sram[0]:12 mux_tree_tapbuf_size4_6_sram[0]:11 0.002044643 +5 mux_tree_tapbuf_size4_6_sram[0]:14 mux_tree_tapbuf_size4_6_sram[0]:13 0.0001657609 +6 mux_tree_tapbuf_size4_6_sram[0]:8 mux_tree_tapbuf_size4_6_sram[0]:7 0.0045 +7 mux_tree_tapbuf_size4_6_sram[0]:7 mux_tree_tapbuf_size4_6_sram[0]:6 0.002651786 +8 mux_tree_tapbuf_size4_6_sram[0]:5 mux_tree_tapbuf_size4_6_sram[0]:4 0.0005915179 +9 mux_tree_tapbuf_size4_6_sram[0]:6 mux_tree_tapbuf_size4_6_sram[0]:5 0.0045 +10 mux_tree_tapbuf_size4_6_sram[0]:4 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size4_6_sram[0]:3 mux_right_track_24\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size4_6_sram[0]:9 mux_tree_tapbuf_size4_6_sram[0]:8 0.007031251 +13 mux_tree_tapbuf_size4_6_sram[0]:9 mux_tree_tapbuf_size4_6_sram[0]:3 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[1] 0.003360737 //LENGTH 26.985 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 72.525 47.600 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 70.095 53.380 +*I mux_bottom_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 79.220 50.320 +*I mux_bottom_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 75.080 44.880 +*N mux_tree_tapbuf_size5_3_sram[1]:4 *C 74.980 44.880 +*N mux_tree_tapbuf_size5_3_sram[1]:5 *C 74.980 44.925 +*N mux_tree_tapbuf_size5_3_sram[1]:6 *C 74.980 47.555 +*N mux_tree_tapbuf_size5_3_sram[1]:7 *C 74.935 47.600 +*N mux_tree_tapbuf_size5_3_sram[1]:8 *C 79.258 50.320 +*N mux_tree_tapbuf_size5_3_sram[1]:9 *C 79.580 50.320 +*N mux_tree_tapbuf_size5_3_sram[1]:10 *C 79.580 49.980 +*N mux_tree_tapbuf_size5_3_sram[1]:11 *C 77.325 49.980 +*N mux_tree_tapbuf_size5_3_sram[1]:12 *C 77.280 50.025 +*N mux_tree_tapbuf_size5_3_sram[1]:13 *C 77.280 53.335 +*N mux_tree_tapbuf_size5_3_sram[1]:14 *C 77.235 53.380 +*N mux_tree_tapbuf_size5_3_sram[1]:15 *C 70.133 53.380 +*N mux_tree_tapbuf_size5_3_sram[1]:16 *C 72.220 53.380 +*N mux_tree_tapbuf_size5_3_sram[1]:17 *C 72.220 53.335 +*N mux_tree_tapbuf_size5_3_sram[1]:18 *C 72.220 47.645 +*N mux_tree_tapbuf_size5_3_sram[1]:19 *C 72.220 47.600 +*N mux_tree_tapbuf_size5_3_sram[1]:20 *C 72.562 47.600 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_17\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_track_17\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_3_sram[1]:4 3.492733e-05 +5 mux_tree_tapbuf_size5_3_sram[1]:5 0.0001999261 +6 mux_tree_tapbuf_size5_3_sram[1]:6 0.0001999261 +7 mux_tree_tapbuf_size5_3_sram[1]:7 0.0001669512 +8 mux_tree_tapbuf_size5_3_sram[1]:8 4.698961e-05 +9 mux_tree_tapbuf_size5_3_sram[1]:9 7.175373e-05 +10 mux_tree_tapbuf_size5_3_sram[1]:10 0.0001843393 +11 mux_tree_tapbuf_size5_3_sram[1]:11 0.0001595752 +12 mux_tree_tapbuf_size5_3_sram[1]:12 0.0001841829 +13 mux_tree_tapbuf_size5_3_sram[1]:13 0.0001841829 +14 mux_tree_tapbuf_size5_3_sram[1]:14 0.0003344158 +15 mux_tree_tapbuf_size5_3_sram[1]:15 0.0001525868 +16 mux_tree_tapbuf_size5_3_sram[1]:16 0.0005198271 +17 mux_tree_tapbuf_size5_3_sram[1]:17 0.0003382728 +18 mux_tree_tapbuf_size5_3_sram[1]:18 0.0003382728 +19 mux_tree_tapbuf_size5_3_sram[1]:19 5.391009e-05 +20 mux_tree_tapbuf_size5_3_sram[1]:20 0.0001866974 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_3_sram[1]:20 0.152 +1 mux_tree_tapbuf_size5_3_sram[1]:14 mux_tree_tapbuf_size5_3_sram[1]:13 0.0045 +2 mux_tree_tapbuf_size5_3_sram[1]:13 mux_tree_tapbuf_size5_3_sram[1]:12 0.002955358 +3 mux_tree_tapbuf_size5_3_sram[1]:11 mux_tree_tapbuf_size5_3_sram[1]:10 0.002013393 +4 mux_tree_tapbuf_size5_3_sram[1]:12 mux_tree_tapbuf_size5_3_sram[1]:11 0.0045 +5 mux_tree_tapbuf_size5_3_sram[1]:8 mux_bottom_track_17\/mux_l2_in_1_:S 0.152 +6 mux_tree_tapbuf_size5_3_sram[1]:7 mux_tree_tapbuf_size5_3_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size5_3_sram[1]:6 mux_tree_tapbuf_size5_3_sram[1]:5 0.002348214 +8 mux_tree_tapbuf_size5_3_sram[1]:4 mux_bottom_track_17\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size5_3_sram[1]:5 mux_tree_tapbuf_size5_3_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size5_3_sram[1]:19 mux_tree_tapbuf_size5_3_sram[1]:18 0.0045 +11 mux_tree_tapbuf_size5_3_sram[1]:18 mux_tree_tapbuf_size5_3_sram[1]:17 0.005080357 +12 mux_tree_tapbuf_size5_3_sram[1]:16 mux_tree_tapbuf_size5_3_sram[1]:15 0.001863839 +13 mux_tree_tapbuf_size5_3_sram[1]:16 mux_tree_tapbuf_size5_3_sram[1]:14 0.004477679 +14 mux_tree_tapbuf_size5_3_sram[1]:17 mux_tree_tapbuf_size5_3_sram[1]:16 0.0045 +15 mux_tree_tapbuf_size5_3_sram[1]:15 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size5_3_sram[1]:20 mux_tree_tapbuf_size5_3_sram[1]:19 0.0001861413 +17 mux_tree_tapbuf_size5_3_sram[1]:20 mux_tree_tapbuf_size5_3_sram[1]:7 0.002118304 +18 mux_tree_tapbuf_size5_3_sram[1]:10 mux_tree_tapbuf_size5_3_sram[1]:9 0.0003035715 +19 mux_tree_tapbuf_size5_3_sram[1]:9 mux_tree_tapbuf_size5_3_sram[1]:8 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size6_6_sram[0] 0.006493458 //LENGTH 45.375 LUMPCC 0.001699023 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 81.725 42.675 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 73.500 41.820 +*I mux_bottom_track_9\/mux_l1_in_2_:S I *L 0.00357 *C 96.700 36.720 +*I mux_bottom_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 100.380 45.560 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 82.055 39.100 +*N mux_tree_tapbuf_size6_6_sram[0]:5 *C 82.055 39.100 +*N mux_tree_tapbuf_size6_6_sram[0]:6 *C 81.880 39.100 +*N mux_tree_tapbuf_size6_6_sram[0]:7 *C 81.880 39.145 +*N mux_tree_tapbuf_size6_6_sram[0]:8 *C 100.343 45.560 +*N mux_tree_tapbuf_size6_6_sram[0]:9 *C 98.485 45.560 +*N mux_tree_tapbuf_size6_6_sram[0]:10 *C 98.440 45.515 +*N mux_tree_tapbuf_size6_6_sram[0]:11 *C 96.738 36.720 +*N mux_tree_tapbuf_size6_6_sram[0]:12 *C 98.395 36.720 +*N mux_tree_tapbuf_size6_6_sram[0]:13 *C 98.440 36.765 +*N mux_tree_tapbuf_size6_6_sram[0]:14 *C 98.440 42.160 +*N mux_tree_tapbuf_size6_6_sram[0]:15 *C 98.433 42.160 +*N mux_tree_tapbuf_size6_6_sram[0]:16 *C 81.888 42.160 +*N mux_tree_tapbuf_size6_6_sram[0]:17 *C 81.880 42.102 +*N mux_tree_tapbuf_size6_6_sram[0]:18 *C 81.880 42.500 +*N mux_tree_tapbuf_size6_6_sram[0]:19 *C 81.758 42.500 +*N mux_tree_tapbuf_size6_6_sram[0]:20 *C 73.538 41.820 +*N mux_tree_tapbuf_size6_6_sram[0]:21 *C 74.015 41.820 +*N mux_tree_tapbuf_size6_6_sram[0]:22 *C 74.060 41.820 +*N mux_tree_tapbuf_size6_6_sram[0]:23 *C 74.060 41.480 +*N mux_tree_tapbuf_size6_6_sram[0]:24 *C 74.068 41.480 +*N mux_tree_tapbuf_size6_6_sram[0]:25 *C 80.032 41.480 +*N mux_tree_tapbuf_size6_6_sram[0]:26 *C 80.040 41.538 +*N mux_tree_tapbuf_size6_6_sram[0]:27 *C 80.040 42.455 +*N mux_tree_tapbuf_size6_6_sram[0]:28 *C 80.085 42.500 +*N mux_tree_tapbuf_size6_6_sram[0]:29 *C 81.688 42.565 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_track_9\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_track_9\/mux_l1_in_1_:S 1e-06 +4 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size6_6_sram[0]:5 4.602535e-05 +6 mux_tree_tapbuf_size6_6_sram[0]:6 5.00114e-05 +7 mux_tree_tapbuf_size6_6_sram[0]:7 0.0001802384 +8 mux_tree_tapbuf_size6_6_sram[0]:8 0.0001630923 +9 mux_tree_tapbuf_size6_6_sram[0]:9 0.0001630923 +10 mux_tree_tapbuf_size6_6_sram[0]:10 0.0002006295 +11 mux_tree_tapbuf_size6_6_sram[0]:11 0.000168031 +12 mux_tree_tapbuf_size6_6_sram[0]:12 0.000168031 +13 mux_tree_tapbuf_size6_6_sram[0]:13 0.0002987644 +14 mux_tree_tapbuf_size6_6_sram[0]:14 0.0005351945 +15 mux_tree_tapbuf_size6_6_sram[0]:15 0.0007379389 +16 mux_tree_tapbuf_size6_6_sram[0]:16 0.0007379389 +17 mux_tree_tapbuf_size6_6_sram[0]:17 0.0002005147 +18 mux_tree_tapbuf_size6_6_sram[0]:18 5.309371e-05 +19 mux_tree_tapbuf_size6_6_sram[0]:19 1.347123e-05 +20 mux_tree_tapbuf_size6_6_sram[0]:20 6.380461e-05 +21 mux_tree_tapbuf_size6_6_sram[0]:21 6.380461e-05 +22 mux_tree_tapbuf_size6_6_sram[0]:22 5.459403e-05 +23 mux_tree_tapbuf_size6_6_sram[0]:23 5.87159e-05 +24 mux_tree_tapbuf_size6_6_sram[0]:24 0.0002808863 +25 mux_tree_tapbuf_size6_6_sram[0]:25 0.0002808863 +26 mux_tree_tapbuf_size6_6_sram[0]:26 6.36016e-05 +27 mux_tree_tapbuf_size6_6_sram[0]:27 6.36016e-05 +28 mux_tree_tapbuf_size6_6_sram[0]:28 6.500098e-05 +29 mux_tree_tapbuf_size6_6_sram[0]:29 7.847221e-05 +30 mux_tree_tapbuf_size6_6_sram[0]:25 chany_top_in[13]:24 0.0001145646 +31 mux_tree_tapbuf_size6_6_sram[0]:24 chany_top_in[13]:23 0.0001145646 +32 mux_tree_tapbuf_size6_6_sram[0]:16 chany_top_in[13]:23 0.0001697198 +33 mux_tree_tapbuf_size6_6_sram[0]:15 chany_top_in[13]:24 0.0001697198 +34 mux_tree_tapbuf_size6_6_sram[0]:13 mux_tree_tapbuf_size6_6_sram[2]:11 1.06538e-05 +35 mux_tree_tapbuf_size6_6_sram[0]:13 mux_tree_tapbuf_size6_6_sram[2]:10 1.585454e-05 +36 mux_tree_tapbuf_size6_6_sram[0]:10 mux_tree_tapbuf_size6_6_sram[2]:4 1.865241e-06 +37 mux_tree_tapbuf_size6_6_sram[0]:16 mux_tree_tapbuf_size6_6_sram[2]:8 0.0001252111 +38 mux_tree_tapbuf_size6_6_sram[0]:14 mux_tree_tapbuf_size6_6_sram[2]:10 1.251904e-05 +39 mux_tree_tapbuf_size6_6_sram[0]:14 mux_tree_tapbuf_size6_6_sram[2]:4 1.585454e-05 +40 mux_tree_tapbuf_size6_6_sram[0]:15 mux_tree_tapbuf_size6_6_sram[2]:9 0.0001252111 +41 mux_tree_tapbuf_size6_6_sram[0]:19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.303656e-05 +42 mux_tree_tapbuf_size6_6_sram[0]:28 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.50395e-05 +43 mux_tree_tapbuf_size6_6_sram[0]:28 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.002208e-05 +44 mux_tree_tapbuf_size6_6_sram[0]:27 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.651136e-05 +45 mux_tree_tapbuf_size6_6_sram[0]:26 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.651136e-05 +46 mux_tree_tapbuf_size6_6_sram[0]:21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.334691e-08 +47 mux_tree_tapbuf_size6_6_sram[0]:20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 8.334691e-08 +48 mux_tree_tapbuf_size6_6_sram[0]:29 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.50395e-05 +49 mux_tree_tapbuf_size6_6_sram[0]:29 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.303656e-05 +50 mux_tree_tapbuf_size6_6_sram[0]:29 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.002208e-05 +51 mux_tree_tapbuf_size6_6_sram[0]:25 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001260952 +52 mux_tree_tapbuf_size6_6_sram[0]:24 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001260952 +53 mux_tree_tapbuf_size6_6_sram[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.295116e-06 +54 mux_tree_tapbuf_size6_6_sram[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.687958e-07 +55 mux_tree_tapbuf_size6_6_sram[0]:16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000149908 +56 mux_tree_tapbuf_size6_6_sram[0]:16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.638262e-05 +57 mux_tree_tapbuf_size6_6_sram[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.687958e-07 +58 mux_tree_tapbuf_size6_6_sram[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.295116e-06 +59 mux_tree_tapbuf_size6_6_sram[0]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.638262e-05 +60 mux_tree_tapbuf_size6_6_sram[0]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000149908 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_6_sram[0]:29 0.152 +1 mux_tree_tapbuf_size6_6_sram[0]:19 mux_tree_tapbuf_size6_6_sram[0]:18 0.0045 +2 mux_tree_tapbuf_size6_6_sram[0]:18 mux_tree_tapbuf_size6_6_sram[0]:17 0.0001911058 +3 mux_tree_tapbuf_size6_6_sram[0]:28 mux_tree_tapbuf_size6_6_sram[0]:27 0.0045 +4 mux_tree_tapbuf_size6_6_sram[0]:27 mux_tree_tapbuf_size6_6_sram[0]:26 0.0008191965 +5 mux_tree_tapbuf_size6_6_sram[0]:26 mux_tree_tapbuf_size6_6_sram[0]:25 0.00341 +6 mux_tree_tapbuf_size6_6_sram[0]:25 mux_tree_tapbuf_size6_6_sram[0]:24 0.0009345167 +7 mux_tree_tapbuf_size6_6_sram[0]:23 mux_tree_tapbuf_size6_6_sram[0]:22 0.0001634615 +8 mux_tree_tapbuf_size6_6_sram[0]:24 mux_tree_tapbuf_size6_6_sram[0]:23 0.00341 +9 mux_tree_tapbuf_size6_6_sram[0]:21 mux_tree_tapbuf_size6_6_sram[0]:20 0.0004263393 +10 mux_tree_tapbuf_size6_6_sram[0]:22 mux_tree_tapbuf_size6_6_sram[0]:21 0.0045 +11 mux_tree_tapbuf_size6_6_sram[0]:20 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size6_6_sram[0]:6 mux_tree_tapbuf_size6_6_sram[0]:5 9.51087e-05 +13 mux_tree_tapbuf_size6_6_sram[0]:7 mux_tree_tapbuf_size6_6_sram[0]:6 0.0045 +14 mux_tree_tapbuf_size6_6_sram[0]:5 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size6_6_sram[0]:29 mux_tree_tapbuf_size6_6_sram[0]:28 0.001430804 +16 mux_tree_tapbuf_size6_6_sram[0]:29 mux_tree_tapbuf_size6_6_sram[0]:19 6.25e-05 +17 mux_tree_tapbuf_size6_6_sram[0]:12 mux_tree_tapbuf_size6_6_sram[0]:11 0.001479911 +18 mux_tree_tapbuf_size6_6_sram[0]:13 mux_tree_tapbuf_size6_6_sram[0]:12 0.0045 +19 mux_tree_tapbuf_size6_6_sram[0]:11 mux_bottom_track_9\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size6_6_sram[0]:9 mux_tree_tapbuf_size6_6_sram[0]:8 0.001658482 +21 mux_tree_tapbuf_size6_6_sram[0]:10 mux_tree_tapbuf_size6_6_sram[0]:9 0.0045 +22 mux_tree_tapbuf_size6_6_sram[0]:8 mux_bottom_track_9\/mux_l1_in_1_:S 0.152 +23 mux_tree_tapbuf_size6_6_sram[0]:17 mux_tree_tapbuf_size6_6_sram[0]:16 0.00341 +24 mux_tree_tapbuf_size6_6_sram[0]:17 mux_tree_tapbuf_size6_6_sram[0]:7 0.002640625 +25 mux_tree_tapbuf_size6_6_sram[0]:16 mux_tree_tapbuf_size6_6_sram[0]:15 0.00259205 +26 mux_tree_tapbuf_size6_6_sram[0]:14 mux_tree_tapbuf_size6_6_sram[0]:13 0.004816964 +27 mux_tree_tapbuf_size6_6_sram[0]:14 mux_tree_tapbuf_size6_6_sram[0]:10 0.002995536 +28 mux_tree_tapbuf_size6_6_sram[0]:15 mux_tree_tapbuf_size6_6_sram[0]:14 0.00341 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.01208527 //LENGTH 62.415 LUMPCC 0.003550877 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_0_:X O *L 0 *C 59.975 69.700 +*I mux_top_track_8\/BUFT_RR_59:A I *L 0.001776 *C 59.800 121.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 59.763 121.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 58.925 121.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 58.880 120.995 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 58.880 112.938 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 58.873 112.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 57.980 112.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 57.960 112.873 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 57.960 73.448 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 57.940 73.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 55.668 73.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 55.660 73.383 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 55.660 70.085 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 55.705 70.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 58.880 70.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:16 *C 58.880 69.700 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:17 *C 59.938 69.700 + +*CAP +0 mux_top_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_8\/BUFT_RR_59:A 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.310969e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.310969e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004639167 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004639167 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.310462e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.310462e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002798247 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.002798247 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0002885732 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0002885732 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.00021552 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.00021552 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0002318831 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.0002603003 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.000111844 +17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:17 8.342678e-05 +18 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[16]:39 0.001775439 +19 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[16]:38 0.001775439 + +*RES +0 mux_top_track_8\/mux_l3_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:17 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_8\/BUFT_RR_59:A 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0007477679 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.007194197 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000139825 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.00341 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.006176583 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.00341 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.000356025 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0045 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.002944197 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.0009441964 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.002834822 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.0003035715 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000482288 //LENGTH 3.780 LUMPCC 0.0001034328 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_0_:X O *L 0 *C 99.075 52.700 +*I mux_top_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 95.585 52.700 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 95.623 52.700 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 99.038 52.700 + +*CAP +0 mux_top_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001884276 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001884276 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_0_sram[0]:9 5.171638e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_0_sram[0]:10 5.171638e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003049107 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001170237 //LENGTH 7.430 LUMPCC 0.0003856287 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_0_:X O *L 0 *C 69.285 44.880 +*I mux_bottom_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 75.805 45.220 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.767 45.220 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.600 45.220 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.600 44.880 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 69.323 44.880 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001207829 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001490989 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000270521 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000242205 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[4]:11 8.768427e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[4]:8 2.792274e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[4]:10 5.678036e-06 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:9 2.869652e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:11 5.678036e-06 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[4]:10 8.845804e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size5_2_sram[0]:7 7.075554e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size5_2_sram[0]:6 7.075554e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003819196 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001935268 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002286708 //LENGTH 18.560 LUMPCC 0.0001621824 DR + +*CONN +*I mux_right_track_12\/mux_l1_in_0_:X O *L 0 *C 50.425 98.600 +*I mux_right_track_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 63.940 94.180 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 63.940 94.180 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.940 94.225 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.940 98.555 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.895 98.600 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 50.463 98.600 + +*CAP +0 mux_right_track_12\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_12\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.375886e-05 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002376991 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002376991 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0008066845 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0008066845 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:18 5.294945e-05 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_1_sram[1]:19 5.294945e-05 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_1_sram[1]:20 2.814173e-05 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_1_sram[1]:21 2.814173e-05 + +*RES +0 mux_right_track_12\/mux_l1_in_0_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0119933 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_12\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.005952802 //LENGTH 46.790 LUMPCC 0.0029548 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_0_:X O *L 0 *C 78.025 112.880 +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 104.220 93.675 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 104.183 93.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 103.545 93.840 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 103.500 93.885 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 103.500 100.583 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 103.493 100.640 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 81.888 100.640 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 81.880 100.698 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 81.880 112.835 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 81.835 112.880 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 78.062 112.880 + +*CAP +0 mux_right_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.89416e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.89416e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003514829 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003514829 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000513539 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.000513539 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003285111 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0003285111 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0002555265 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0002555265 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 right_top_grid_pin_45_[0]:19 0.0004742467 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 right_top_grid_pin_45_[0]:21 0.0001226203 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 right_top_grid_pin_45_[0]:16 8.378674e-06 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 right_top_grid_pin_45_[0]:18 0.0004742467 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 right_top_grid_pin_45_[0]:20 0.0001226203 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 right_top_grid_pin_45_[0]:17 8.378674e-06 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 right_top_grid_pin_46_[0]:15 0.0003399492 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 right_top_grid_pin_46_[0]:16 0.0003399492 +20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004197958 +21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004197958 +22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001124095 +23 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001124095 + +*RES +0 mux_right_track_2\/mux_l3_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005691964 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005979911 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.003384783 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.01083705 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.003368304 + +*END + +*D_NET ropt_net_237 0.0007071632 //LENGTH 6.450 LUMPCC 9.305958e-05 DR + +*CONN +*I ropt_mt_inst_813:X O *L 0 *C 33.580 3.400 +*I ropt_mt_inst_857:A I *L 0.001766 *C 34.500 6.800 +*N ropt_net_237:2 *C 34.462 6.800 +*N ropt_net_237:3 *C 34.085 6.800 +*N ropt_net_237:4 *C 34.040 6.755 +*N ropt_net_237:5 *C 34.040 4.420 +*N ropt_net_237:6 *C 34.500 4.420 +*N ropt_net_237:7 *C 34.500 3.445 +*N ropt_net_237:8 *C 34.455 3.400 +*N ropt_net_237:9 *C 33.617 3.400 + +*CAP +0 ropt_mt_inst_813:X 1e-06 +1 ropt_mt_inst_857:A 1e-06 +2 ropt_net_237:2 4.059772e-05 +3 ropt_net_237:3 4.059772e-05 +4 ropt_net_237:4 0.0001232974 +5 ropt_net_237:5 0.000151971 +6 ropt_net_237:6 8.994061e-05 +7 ropt_net_237:7 6.126704e-05 +8 ropt_net_237:8 5.221603e-05 +9 ropt_net_237:9 5.221603e-05 +10 ropt_net_237:8 chany_top_in[8]:7 4.652979e-05 +11 ropt_net_237:9 chany_top_in[8]:6 4.652979e-05 + +*RES +0 ropt_mt_inst_813:X ropt_net_237:9 0.152 +1 ropt_net_237:2 ropt_mt_inst_857:A 0.152 +2 ropt_net_237:3 ropt_net_237:2 0.0003370536 +3 ropt_net_237:4 ropt_net_237:3 0.0045 +4 ropt_net_237:8 ropt_net_237:7 0.0045 +5 ropt_net_237:7 ropt_net_237:6 0.0008705358 +6 ropt_net_237:9 ropt_net_237:8 0.0007477679 +7 ropt_net_237:5 ropt_net_237:4 0.002084822 +8 ropt_net_237:6 ropt_net_237:5 0.0004107143 + +*END + +*D_NET ropt_net_230 0.0008418428 //LENGTH 6.755 LUMPCC 0.0002397322 DR + +*CONN +*I ropt_mt_inst_834:X O *L 0 *C 110.045 40.120 +*I ropt_mt_inst_850:A I *L 0.001767 *C 106.260 42.160 +*N ropt_net_230:2 *C 106.297 42.160 +*N ropt_net_230:3 *C 108.055 42.160 +*N ropt_net_230:4 *C 108.100 42.115 +*N ropt_net_230:5 *C 108.100 40.165 +*N ropt_net_230:6 *C 108.145 40.120 +*N ropt_net_230:7 *C 110.008 40.120 + +*CAP +0 ropt_mt_inst_834:X 1e-06 +1 ropt_mt_inst_850:A 1e-06 +2 ropt_net_230:2 8.60287e-05 +3 ropt_net_230:3 8.60287e-05 +4 ropt_net_230:4 0.0001003745 +5 ropt_net_230:5 0.0001003745 +6 ropt_net_230:6 0.0001136521 +7 ropt_net_230:7 0.0001136521 +8 ropt_net_230:7 chany_bottom_in[11]:6 4.730081e-05 +9 ropt_net_230:6 chany_bottom_in[11]:7 4.730081e-05 +10 ropt_net_230:5 chany_bottom_in[11]:5 2.688932e-05 +11 ropt_net_230:4 chany_bottom_in[11]:4 2.688932e-05 +12 ropt_net_230:3 chanx_right_out[16]:5 4.567594e-05 +13 ropt_net_230:2 chanx_right_out[16]:6 4.567594e-05 + +*RES +0 ropt_mt_inst_834:X ropt_net_230:7 0.152 +1 ropt_net_230:7 ropt_net_230:6 0.001662947 +2 ropt_net_230:6 ropt_net_230:5 0.0045 +3 ropt_net_230:5 ropt_net_230:4 0.001741071 +4 ropt_net_230:3 ropt_net_230:2 0.001569196 +5 ropt_net_230:4 ropt_net_230:3 0.0045 +6 ropt_net_230:2 ropt_mt_inst_850:A 0.152 + +*END + +*D_NET chany_top_out[10] 0.0008394402 //LENGTH 7.135 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_854:X O *L 0 *C 48.300 124.440 +*P chany_top_out[10] O *L 0.7423 *C 46.460 129.270 +*N chany_top_out[10]:2 *C 46.460 124.485 +*N chany_top_out[10]:3 *C 46.505 124.440 +*N chany_top_out[10]:4 *C 48.263 124.440 + +*CAP +0 ropt_mt_inst_854:X 1e-06 +1 chany_top_out[10] 0.0002808837 +2 chany_top_out[10]:2 0.0002808837 +3 chany_top_out[10]:3 0.0001383364 +4 chany_top_out[10]:4 0.0001383364 + +*RES +0 ropt_mt_inst_854:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.001569197 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.004272322 + +*END + +*D_NET chany_top_out[19] 0.002095271 //LENGTH 18.445 LUMPCC 0 DR + +*CONN +*I BUFT_RR_99:X O *L 0 *C 24.645 113.220 +*P chany_top_out[19] O *L 0.7423 *C 25.760 129.350 +*N chany_top_out[19]:2 *C 25.360 113.220 +*N chany_top_out[19]:3 *C 25.760 113.228 +*N chany_top_out[19]:4 *C 25.760 113.220 +*N chany_top_out[19]:5 *C 25.760 113.220 +*N chany_top_out[19]:6 *C 25.715 113.220 +*N chany_top_out[19]:7 *C 24.683 113.220 + +*CAP +0 BUFT_RR_99:X 1e-06 +1 chany_top_out[19] 0.0009037822 +2 chany_top_out[19]:2 5.313418e-05 +3 chany_top_out[19]:3 0.0009037822 +4 chany_top_out[19]:4 5.313418e-05 +5 chany_top_out[19]:5 3.008734e-05 +6 chany_top_out[19]:6 7.517546e-05 +7 chany_top_out[19]:7 7.517546e-05 + +*RES +0 BUFT_RR_99:X chany_top_out[19]:7 0.152 +1 chany_top_out[19]:7 chany_top_out[19]:6 0.0009218751 +2 chany_top_out[19]:6 chany_top_out[19]:5 0.0045 +3 chany_top_out[19]:5 chany_top_out[19]:4 0.00341 +4 chany_top_out[19]:4 chany_top_out[19]:3 0.00341 +5 chany_top_out[19]:4 chany_top_out[19]:2 5.696969e-05 +6 chany_top_out[19]:3 chany_top_out[19] 0.002525858 + +*END + +*D_NET chany_bottom_out[15] 0.002319653 //LENGTH 16.220 LUMPCC 0.0003762383 DR + +*CONN +*I BUFT_P_138:X O *L 0 *C 49.220 14.280 +*P chany_bottom_out[15] O *L 0.7423 *C 47.840 1.285 +*N chany_bottom_out[15]:2 *C 47.130 6.120 +*N chany_bottom_out[15]:3 *C 47.840 6.113 +*N chany_bottom_out[15]:4 *C 47.838 6.120 +*N chany_bottom_out[15]:5 *C 47.840 6.178 +*N chany_bottom_out[15]:6 *C 47.840 14.235 +*N chany_bottom_out[15]:7 *C 47.885 14.280 +*N chany_bottom_out[15]:8 *C 49.183 14.280 + +*CAP +0 BUFT_P_138:X 1e-06 +1 chany_bottom_out[15] 0.0003955879 +2 chany_bottom_out[15]:2 9.553997e-05 +3 chany_bottom_out[15]:3 0.0003955879 +4 chany_bottom_out[15]:4 9.553997e-05 +5 chany_bottom_out[15]:5 0.0003684899 +6 chany_bottom_out[15]:6 0.0003684899 +7 chany_bottom_out[15]:7 0.0001115897 +8 chany_bottom_out[15]:8 0.0001115897 +9 chany_bottom_out[15]:6 ropt_net_215:5 0.0001881192 +10 chany_bottom_out[15]:5 ropt_net_215:4 0.0001881192 + +*RES +0 BUFT_P_138:X chany_bottom_out[15]:8 0.152 +1 chany_bottom_out[15]:8 chany_bottom_out[15]:7 0.001158482 +2 chany_bottom_out[15]:7 chany_bottom_out[15]:6 0.0045 +3 chany_bottom_out[15]:6 chany_bottom_out[15]:5 0.007194197 +4 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.00341 +5 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.00341 +6 chany_bottom_out[15]:4 chany_bottom_out[15]:2 0.0001039141 +7 chany_bottom_out[15]:3 chany_bottom_out[15] 0.0007563082 + +*END + +*D_NET chany_top_in[14] 0.02543491 //LENGTH 194.450 LUMPCC 0.00644346 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 29.440 129.350 +*I mux_right_track_18\/mux_l1_in_0_:A1 I *L 0.00198 *C 74.980 85.340 +*I BUFT_P_138:A I *L 0.001767 *C 48.300 14.960 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.395 27.880 +*N chany_top_in[14]:4 *C 72.358 27.880 +*N chany_top_in[14]:5 *C 48.338 14.960 +*N chany_top_in[14]:6 *C 49.175 14.960 +*N chany_top_in[14]:7 *C 49.220 15.005 +*N chany_top_in[14]:8 *C 49.220 27.835 +*N chany_top_in[14]:9 *C 49.265 27.880 +*N chany_top_in[14]:10 *C 69.000 27.880 +*N chany_top_in[14]:11 *C 69.000 27.925 +*N chany_top_in[14]:12 *C 69.000 33.943 +*N chany_top_in[14]:13 *C 69.008 34.000 +*N chany_top_in[14]:14 *C 74.500 34.000 +*N chany_top_in[14]:15 *C 74.520 34.008 +*N chany_top_in[14]:16 *C 74.120 86.360 +*N chany_top_in[14]:17 *C 74.943 85.340 +*N chany_top_in[14]:18 *C 74.565 85.340 +*N chany_top_in[14]:19 *C 74.520 85.385 +*N chany_top_in[14]:20 *C 74.520 86.303 +*N chany_top_in[14]:21 *C 74.520 86.360 +*N chany_top_in[14]:22 *C 74.520 86.360 +*N chany_top_in[14]:23 *C 74.520 125.793 +*N chany_top_in[14]:24 *C 74.500 125.800 +*N chany_top_in[14]:25 *C 29.460 125.800 +*N chany_top_in[14]:26 *C 29.440 125.808 + +*CAP +0 chany_top_in[14] 0.0002043435 +1 mux_right_track_18\/mux_l1_in_0_:A1 1e-06 +2 BUFT_P_138:A 1e-06 +3 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[14]:4 0.0002277186 +5 chany_top_in[14]:5 6.836181e-05 +6 chany_top_in[14]:6 6.836181e-05 +7 chany_top_in[14]:7 0.0005937099 +8 chany_top_in[14]:8 0.0005937099 +9 chany_top_in[14]:9 0.001219218 +10 chany_top_in[14]:10 0.001481116 +11 chany_top_in[14]:11 0.0004836898 +12 chany_top_in[14]:12 0.0004836898 +13 chany_top_in[14]:13 0.000415083 +14 chany_top_in[14]:14 0.000415083 +15 chany_top_in[14]:15 0.00201534 +16 chany_top_in[14]:16 7.844859e-05 +17 chany_top_in[14]:17 4.644377e-05 +18 chany_top_in[14]:18 4.644377e-05 +19 chany_top_in[14]:19 6.955943e-05 +20 chany_top_in[14]:20 6.955943e-05 +21 chany_top_in[14]:21 7.844859e-05 +22 chany_top_in[14]:22 0.003605406 +23 chany_top_in[14]:23 0.001590067 +24 chany_top_in[14]:24 0.002465153 +25 chany_top_in[14]:25 0.002465153 +26 chany_top_in[14]:26 0.0002043435 +27 chany_top_in[14]:23 chany_top_in[2]:24 0.0001596654 +28 chany_top_in[14]:22 chany_top_in[2]:23 0.0001596654 +29 chany_top_in[14]:22 chany_top_in[2]:24 0.0008281374 +30 chany_top_in[14]:15 chany_top_in[2]:23 0.0008281374 +31 chany_top_in[14]:24 chany_bottom_in[4]:11 0.0002309685 +32 chany_top_in[14]:23 chany_bottom_in[4]:12 0.0003493161 +33 chany_top_in[14]:25 chany_bottom_in[4]:10 0.0002309685 +34 chany_top_in[14]:22 chany_bottom_in[4]:13 0.0003493161 +35 chany_top_in[14]:22 chany_bottom_in[13]:22 0.00094872 +36 chany_top_in[14]:15 chany_bottom_in[13]:23 0.00094872 +37 chany_top_in[14]:23 right_top_grid_pin_49_[0]:19 0.000530145 +38 chany_top_in[14]:22 right_top_grid_pin_49_[0]:18 0.000530145 +39 chany_top_in[14]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001003121 +40 chany_top_in[14]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001003121 +41 chany_top_in[14]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.431906e-06 +42 chany_top_in[14]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.703282e-05 +43 chany_top_in[14]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.703282e-05 +44 chany_top_in[14]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.431906e-06 + +*RES +0 chany_top_in[14] chany_top_in[14]:26 0.0005549917 +1 chany_top_in[14]:5 BUFT_P_138:A 0.152 +2 chany_top_in[14]:6 chany_top_in[14]:5 0.0007477679 +3 chany_top_in[14]:7 chany_top_in[14]:6 0.0045 +4 chany_top_in[14]:9 chany_top_in[14]:8 0.0045 +5 chany_top_in[14]:8 chany_top_in[14]:7 0.01145536 +6 chany_top_in[14]:24 chany_top_in[14]:23 0.00341 +7 chany_top_in[14]:23 chany_top_in[14]:22 0.006177758 +8 chany_top_in[14]:25 chany_top_in[14]:24 0.007056266 +9 chany_top_in[14]:26 chany_top_in[14]:25 0.00341 +10 chany_top_in[14]:21 chany_top_in[14]:20 0.00341 +11 chany_top_in[14]:21 chany_top_in[14]:16 5.69697e-05 +12 chany_top_in[14]:22 chany_top_in[14]:21 0.00341 +13 chany_top_in[14]:22 chany_top_in[14]:15 0.008201891 +14 chany_top_in[14]:20 chany_top_in[14]:19 0.0008191965 +15 chany_top_in[14]:18 chany_top_in[14]:17 0.0003370536 +16 chany_top_in[14]:19 chany_top_in[14]:18 0.0045 +17 chany_top_in[14]:17 mux_right_track_18\/mux_l1_in_0_:A1 0.152 +18 chany_top_in[14]:4 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +19 chany_top_in[14]:10 chany_top_in[14]:9 0.01762054 +20 chany_top_in[14]:10 chany_top_in[14]:4 0.002997768 +21 chany_top_in[14]:11 chany_top_in[14]:10 0.0045 +22 chany_top_in[14]:12 chany_top_in[14]:11 0.005372768 +23 chany_top_in[14]:13 chany_top_in[14]:12 0.00341 +24 chany_top_in[14]:14 chany_top_in[14]:13 0.0008604916 +25 chany_top_in[14]:15 chany_top_in[14]:14 0.00341 + +*END + +*D_NET chany_bottom_in[10] 0.01586544 //LENGTH 135.415 LUMPCC 0.004502973 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 51.980 1.290 +*I mux_top_track_32\/mux_l2_in_1_:A1 I *L 0.00198 *C 51.620 85.340 +*I mux_right_track_12\/mux_l2_in_1_:A1 I *L 0.00198 *C 56.680 88.740 +*I FTB_24__23:A I *L 0.001776 *C 50.140 121.040 +*N chany_bottom_in[10]:4 *C 50.178 121.040 +*N chany_bottom_in[10]:5 *C 52.855 121.040 +*N chany_bottom_in[10]:6 *C 52.900 120.995 +*N chany_bottom_in[10]:7 *C 56.643 88.740 +*N chany_bottom_in[10]:8 *C 52.945 88.740 +*N chany_bottom_in[10]:9 *C 52.900 88.740 +*N chany_bottom_in[10]:10 *C 52.900 89.138 +*N chany_bottom_in[10]:11 *C 52.893 89.080 +*N chany_bottom_in[10]:12 *C 50.608 89.080 +*N chany_bottom_in[10]:13 *C 50.600 89.023 +*N chany_bottom_in[10]:14 *C 51.583 85.340 +*N chany_bottom_in[10]:15 *C 50.645 85.340 +*N chany_bottom_in[10]:16 *C 50.600 85.340 +*N chany_bottom_in[10]:17 *C 50.600 83.017 +*N chany_bottom_in[10]:18 *C 50.608 82.960 +*N chany_bottom_in[10]:19 *C 52.420 82.960 +*N chany_bottom_in[10]:20 *C 52.440 82.953 +*N chany_bottom_in[10]:21 *C 52.440 61.735 +*N chany_bottom_in[10]:22 *C 52.440 11.908 +*N chany_bottom_in[10]:23 *C 52.425 11.900 +*N chany_bottom_in[10]:24 *C 51.983 11.900 +*N chany_bottom_in[10]:25 *C 51.980 11.843 + +*CAP +0 chany_bottom_in[10] 0.0006193489 +1 mux_top_track_32\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_12\/mux_l2_in_1_:A1 1e-06 +3 FTB_24__23:A 1e-06 +4 chany_bottom_in[10]:4 0.0001144038 +5 chany_bottom_in[10]:5 0.0001144038 +6 chany_bottom_in[10]:6 0.001346577 +7 chany_bottom_in[10]:7 0.0002644737 +8 chany_bottom_in[10]:8 0.0002644737 +9 chany_bottom_in[10]:9 5.195448e-05 +10 chany_bottom_in[10]:10 0.001367657 +11 chany_bottom_in[10]:11 0.0001882216 +12 chany_bottom_in[10]:12 0.0001882216 +13 chany_bottom_in[10]:13 0.0001802677 +14 chany_bottom_in[10]:14 8.496142e-05 +15 chany_bottom_in[10]:15 8.496142e-05 +16 chany_bottom_in[10]:16 0.0003674243 +17 chany_bottom_in[10]:17 0.0001562824 +18 chany_bottom_in[10]:18 0.0001451168 +19 chany_bottom_in[10]:19 0.0001451168 +20 chany_bottom_in[10]:20 0.0007567724 +21 chany_bottom_in[10]:21 0.002475565 +22 chany_bottom_in[10]:22 0.001718793 +23 chany_bottom_in[10]:23 5.256079e-05 +24 chany_bottom_in[10]:24 5.256079e-05 +25 chany_bottom_in[10]:25 0.0006193489 +26 chany_bottom_in[10]:17 chany_top_in[9]:16 2.025476e-06 +27 chany_bottom_in[10]:20 chany_top_in[9]:23 2.400878e-05 +28 chany_bottom_in[10]:22 chany_top_in[9]:16 2.410339e-05 +29 chany_bottom_in[10]:10 chany_top_in[9]:16 4.94709e-05 +30 chany_bottom_in[10]:10 chany_top_in[9]:24 0.0003013248 +31 chany_bottom_in[10]:13 chany_top_in[9]:23 3.613633e-05 +32 chany_bottom_in[10]:16 chany_top_in[9]:16 3.613633e-05 +33 chany_bottom_in[10]:16 chany_top_in[9]:23 2.025476e-06 +34 chany_bottom_in[10]:9 chany_top_in[9]:23 7.788334e-07 +35 chany_bottom_in[10]:6 chany_top_in[9] 0.0003013248 +36 chany_bottom_in[10]:6 chany_top_in[9]:23 4.869207e-05 +37 chany_bottom_in[10]:21 chany_top_in[9]:16 2.400878e-05 +38 chany_bottom_in[10]:21 chany_top_in[9]:23 2.410339e-05 +39 chany_bottom_in[10] chany_top_in[12]:7 1.341341e-07 +40 chany_bottom_in[10]:20 chany_top_in[12]:19 0.000402763 +41 chany_bottom_in[10]:22 chany_top_in[12]:10 6.827011e-05 +42 chany_bottom_in[10]:22 chany_top_in[12]:18 0.0005398194 +43 chany_bottom_in[10]:25 chany_top_in[12]:8 1.341341e-07 +44 chany_bottom_in[10]:10 chany_top_in[12]:23 2.832436e-05 +45 chany_bottom_in[10]:6 chany_top_in[12]:24 2.832436e-05 +46 chany_bottom_in[10]:21 chany_top_in[12]:17 6.827011e-05 +47 chany_bottom_in[10]:21 chany_top_in[12]:18 0.000402763 +48 chany_bottom_in[10]:21 chany_top_in[12]:19 0.0005398194 +49 chany_bottom_in[10]:20 chany_bottom_in[5]:17 0.0001529132 +50 chany_bottom_in[10]:22 chany_bottom_in[5]:26 7.100217e-05 +51 chany_bottom_in[10]:22 chany_bottom_in[5]:27 0.0001505689 +52 chany_bottom_in[10]:22 chany_bottom_in[5]:31 0.0002883968 +53 chany_bottom_in[10]:21 chany_bottom_in[5]:17 7.100217e-05 +54 chany_bottom_in[10]:21 chany_bottom_in[5]:26 0.0003034821 +55 chany_bottom_in[10]:21 chany_bottom_in[5]:30 0.0002883968 +56 chany_bottom_in[10]:5 ropt_net_216:6 0.0001122245 +57 chany_bottom_in[10]:4 ropt_net_216:7 0.0001122245 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:25 0.009421875 +1 chany_bottom_in[10]:17 chany_bottom_in[10]:16 0.002073661 +2 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.00341 +3 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.0002839583 +4 chany_bottom_in[10]:20 chany_bottom_in[10]:19 0.00341 +5 chany_bottom_in[10]:23 chany_bottom_in[10]:22 0.00341 +6 chany_bottom_in[10]:22 chany_bottom_in[10]:21 0.007806308 +7 chany_bottom_in[10]:25 chany_bottom_in[10]:24 0.00341 +8 chany_bottom_in[10]:24 chany_bottom_in[10]:23 6.499219e-05 +9 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.0001911058 +10 chany_bottom_in[10]:10 chany_bottom_in[10]:6 0.0284442 +11 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.00341 +12 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.00341 +13 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.0003579833 +14 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.0008370536 +15 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.0045 +16 chany_bottom_in[10]:16 chany_bottom_in[10]:13 0.003287947 +17 chany_bottom_in[10]:14 mux_top_track_32\/mux_l2_in_1_:A1 0.152 +18 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.003301339 +19 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.0045 +20 chany_bottom_in[10]:7 mux_right_track_12\/mux_l2_in_1_:A1 0.152 +21 chany_bottom_in[10]:5 chany_bottom_in[10]:4 0.002390625 +22 chany_bottom_in[10]:6 chany_bottom_in[10]:5 0.0045 +23 chany_bottom_in[10]:4 FTB_24__23:A 0.152 +24 chany_bottom_in[10]:21 chany_bottom_in[10]:20 0.003324075 + +*END + +*D_NET chany_bottom_in[12] 0.02555511 //LENGTH 206.160 LUMPCC 0.006667485 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 63.940 1.290 +*I mux_right_track_14\/mux_l2_in_1_:A1 I *L 0.00198 *C 79.680 83.300 +*I mux_top_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 82.975 69.700 +*I ropt_mt_inst_814:A I *L 0.001767 *C 24.380 126.480 +*N chany_bottom_in[12]:4 *C 24.380 126.480 +*N chany_bottom_in[12]:5 *C 24.380 126.435 +*N chany_bottom_in[12]:6 *C 24.380 124.498 +*N chany_bottom_in[12]:7 *C 24.380 124.440 +*N chany_bottom_in[12]:8 *C 25.293 124.440 +*N chany_bottom_in[12]:9 *C 25.300 124.440 +*N chany_bottom_in[12]:10 *C 25.345 124.440 +*N chany_bottom_in[12]:11 *C 26.680 124.440 +*N chany_bottom_in[12]:12 *C 26.680 124.395 +*N chany_bottom_in[12]:13 *C 26.680 123.805 +*N chany_bottom_in[12]:14 *C 26.725 123.760 +*N chany_bottom_in[12]:15 *C 30.775 123.760 +*N chany_bottom_in[12]:16 *C 30.820 123.715 +*N chany_bottom_in[12]:17 *C 30.820 120.745 +*N chany_bottom_in[12]:18 *C 30.865 120.700 +*N chany_bottom_in[12]:19 *C 34.040 120.700 +*N chany_bottom_in[12]:20 *C 34.040 120.360 +*N chany_bottom_in[12]:21 *C 34.040 120.405 +*N chany_bottom_in[12]:22 *C 34.040 120.995 +*N chany_bottom_in[12]:23 *C 34.085 121.040 +*N chany_bottom_in[12]:24 *C 34.960 121.040 +*N chany_bottom_in[12]:25 *C 34.960 120.360 +*N chany_bottom_in[12]:26 *C 36.295 120.360 +*N chany_bottom_in[12]:27 *C 36.340 120.315 +*N chany_bottom_in[12]:28 *C 36.340 90.498 +*N chany_bottom_in[12]:29 *C 36.348 90.440 +*N chany_bottom_in[12]:30 *C 64.380 90.440 +*N chany_bottom_in[12]:31 *C 64.400 90.433 +*N chany_bottom_in[12]:32 *C 82.938 69.700 +*N chany_bottom_in[12]:33 *C 80.085 69.700 +*N chany_bottom_in[12]:34 *C 80.040 69.745 +*N chany_bottom_in[12]:35 *C 80.040 78.200 +*N chany_bottom_in[12]:36 *C 79.580 83.300 +*N chany_bottom_in[12]:37 *C 79.580 83.255 +*N chany_bottom_in[12]:38 *C 79.580 78.200 +*N chany_bottom_in[12]:39 *C 79.573 78.200 +*N chany_bottom_in[12]:40 *C 64.420 78.200 +*N chany_bottom_in[12]:41 *C 64.400 78.200 +*N chany_bottom_in[12]:42 *C 64.400 68.875 +*N chany_bottom_in[12]:43 *C 64.400 19.047 +*N chany_bottom_in[12]:44 *C 64.385 19.040 +*N chany_bottom_in[12]:45 *C 63.943 19.040 +*N chany_bottom_in[12]:46 *C 63.940 18.983 + +*CAP +0 chany_bottom_in[12] 0.0008708916 +1 mux_right_track_14\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_814:A 1e-06 +4 chany_bottom_in[12]:4 3.20426e-05 +5 chany_bottom_in[12]:5 0.0001136844 +6 chany_bottom_in[12]:6 0.0001136844 +7 chany_bottom_in[12]:7 9.435543e-05 +8 chany_bottom_in[12]:8 9.435543e-05 +9 chany_bottom_in[12]:9 3.42395e-05 +10 chany_bottom_in[12]:10 0.0001134866 +11 chany_bottom_in[12]:11 0.0001418938 +12 chany_bottom_in[12]:12 6.207728e-05 +13 chany_bottom_in[12]:13 6.207728e-05 +14 chany_bottom_in[12]:14 0.0002199776 +15 chany_bottom_in[12]:15 0.0002199776 +16 chany_bottom_in[12]:16 0.000166496 +17 chany_bottom_in[12]:17 0.000166496 +18 chany_bottom_in[12]:18 0.0002127518 +19 chany_bottom_in[12]:19 0.0002320222 +20 chany_bottom_in[12]:20 4.190658e-05 +21 chany_bottom_in[12]:21 4.281784e-05 +22 chany_bottom_in[12]:22 4.281784e-05 +23 chany_bottom_in[12]:23 7.183038e-05 +24 chany_bottom_in[12]:24 0.0001123222 +25 chany_bottom_in[12]:25 0.0001365287 +26 chany_bottom_in[12]:26 9.603686e-05 +27 chany_bottom_in[12]:27 0.001024773 +28 chany_bottom_in[12]:28 0.001024773 +29 chany_bottom_in[12]:29 0.002056437 +30 chany_bottom_in[12]:30 0.002056437 +31 chany_bottom_in[12]:31 0.0004106731 +32 chany_bottom_in[12]:32 0.0002169159 +33 chany_bottom_in[12]:33 0.0002169159 +34 chany_bottom_in[12]:34 0.0004481066 +35 chany_bottom_in[12]:35 0.0004839631 +36 chany_bottom_in[12]:36 3.20127e-05 +37 chany_bottom_in[12]:37 0.0003076925 +38 chany_bottom_in[12]:38 0.000343549 +39 chany_bottom_in[12]:39 0.0007094528 +40 chany_bottom_in[12]:40 0.0007094528 +41 chany_bottom_in[12]:41 0.0007152926 +42 chany_bottom_in[12]:42 0.001988498 +43 chany_bottom_in[12]:43 0.001683878 +44 chany_bottom_in[12]:44 4.506914e-05 +45 chany_bottom_in[12]:45 4.506914e-05 +46 chany_bottom_in[12]:46 0.0008708916 +47 chany_bottom_in[12]:31 chany_top_in[4]:20 0.0002471306 +48 chany_bottom_in[12]:43 chany_top_in[4]:19 0.0004683808 +49 chany_bottom_in[12]:41 chany_top_in[4]:19 0.0002471306 +50 chany_bottom_in[12]:41 chany_top_in[4]:20 0.0001724076 +51 chany_bottom_in[12]:42 chany_top_in[4]:19 0.0001724076 +52 chany_bottom_in[12]:42 chany_top_in[4]:20 0.0004683808 +53 chany_bottom_in[12]:31 chany_bottom_in[6]:12 5.234186e-06 +54 chany_bottom_in[12]:31 chany_bottom_in[6]:16 9.399005e-05 +55 chany_bottom_in[12]:43 chany_bottom_in[6]:17 0.0001823553 +56 chany_bottom_in[12]:43 chany_bottom_in[6]:24 6.274585e-06 +57 chany_bottom_in[12]:43 chany_bottom_in[6]:25 0.0005307265 +58 chany_bottom_in[12]:41 chany_bottom_in[6]:13 5.234186e-06 +59 chany_bottom_in[12]:41 chany_bottom_in[6]:16 0.0001807273 +60 chany_bottom_in[12]:41 chany_bottom_in[6]:17 9.399005e-05 +61 chany_bottom_in[12]:42 chany_bottom_in[6]:16 0.0001823553 +62 chany_bottom_in[12]:42 chany_bottom_in[6]:17 0.0001807273 +63 chany_bottom_in[12]:42 chany_bottom_in[6]:18 6.274585e-06 +64 chany_bottom_in[12]:42 chany_bottom_in[6]:24 0.0005307265 +65 chany_bottom_in[12]:21 chany_bottom_in[9]:8 4.717354e-06 +66 chany_bottom_in[12]:28 chany_bottom_in[9]:8 0.0008207754 +67 chany_bottom_in[12]:26 chany_bottom_in[9]:5 1.304822e-05 +68 chany_bottom_in[12]:27 chany_bottom_in[9]:7 0.0008207754 +69 chany_bottom_in[12]:22 chany_bottom_in[9]:7 4.717354e-06 +70 chany_bottom_in[12]:25 chany_bottom_in[9]:6 1.304822e-05 +71 chany_bottom_in[12]:40 chanx_right_in[6]:13 0.000268275 +72 chany_bottom_in[12]:39 chanx_right_in[6]:14 0.000268275 +73 chany_bottom_in[12]:40 chanx_right_in[14]:11 0.0002779562 +74 chany_bottom_in[12]:39 chanx_right_in[14]:12 0.0002779562 +75 chany_bottom_in[12]:33 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.924324e-05 +76 chany_bottom_in[12]:34 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.249977e-05 +77 chany_bottom_in[12]:32 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.924324e-05 +78 chany_bottom_in[12]:35 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.249977e-05 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:46 0.01579688 +1 chany_bottom_in[12]:33 chany_bottom_in[12]:32 0.002546875 +2 chany_bottom_in[12]:34 chany_bottom_in[12]:33 0.0045 +3 chany_bottom_in[12]:32 mux_top_track_0\/mux_l1_in_2_:A0 0.152 +4 chany_bottom_in[12]:20 chany_bottom_in[12]:19 0.0003035715 +5 chany_bottom_in[12]:21 chany_bottom_in[12]:20 0.0045 +6 chany_bottom_in[12]:18 chany_bottom_in[12]:17 0.0045 +7 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.002651786 +8 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.003616072 +9 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.0045 +10 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.0045 +11 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.0005267857 +12 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.001191964 +13 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0045 +14 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.0045 +15 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.00341 +16 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.0001429583 +17 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.001729911 +18 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.00341 +19 chany_bottom_in[12]:4 ropt_mt_inst_814:A 0.152 +20 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.0045 +21 chany_bottom_in[12]:30 chany_bottom_in[12]:29 0.004391758 +22 chany_bottom_in[12]:31 chany_bottom_in[12]:30 0.00341 +23 chany_bottom_in[12]:28 chany_bottom_in[12]:27 0.02662277 +24 chany_bottom_in[12]:29 chany_bottom_in[12]:28 0.00341 +25 chany_bottom_in[12]:26 chany_bottom_in[12]:25 0.001191964 +26 chany_bottom_in[12]:27 chany_bottom_in[12]:26 0.0045 +27 chany_bottom_in[12]:23 chany_bottom_in[12]:22 0.0045 +28 chany_bottom_in[12]:22 chany_bottom_in[12]:21 0.0005267857 +29 chany_bottom_in[12]:36 mux_right_track_14\/mux_l2_in_1_:A1 0.152 +30 chany_bottom_in[12]:37 chany_bottom_in[12]:36 0.0045 +31 chany_bottom_in[12]:44 chany_bottom_in[12]:43 0.00341 +32 chany_bottom_in[12]:43 chany_bottom_in[12]:42 0.007806308 +33 chany_bottom_in[12]:46 chany_bottom_in[12]:45 0.00341 +34 chany_bottom_in[12]:45 chany_bottom_in[12]:44 6.499219e-05 +35 chany_bottom_in[12]:40 chany_bottom_in[12]:39 0.002373892 +36 chany_bottom_in[12]:41 chany_bottom_in[12]:40 0.00341 +37 chany_bottom_in[12]:41 chany_bottom_in[12]:31 0.001916425 +38 chany_bottom_in[12]:38 chany_bottom_in[12]:37 0.004513393 +39 chany_bottom_in[12]:38 chany_bottom_in[12]:35 0.0004107143 +40 chany_bottom_in[12]:39 chany_bottom_in[12]:38 0.00341 +41 chany_bottom_in[12]:19 chany_bottom_in[12]:18 0.002834821 +42 chany_bottom_in[12]:24 chany_bottom_in[12]:23 0.00078125 +43 chany_bottom_in[12]:25 chany_bottom_in[12]:24 0.0006071428 +44 chany_bottom_in[12]:35 chany_bottom_in[12]:34 0.007549107 +45 chany_bottom_in[12]:42 chany_bottom_in[12]:41 0.001460917 + +*END + +*D_NET chany_bottom_in[14] 0.02155825 //LENGTH 165.648 LUMPCC 0.00666358 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 43.700 1.325 +*I BUFT_RR_96:A I *L 0.001767 *C 45.540 115.600 +*I mux_right_track_18\/mux_l1_in_1_:A1 I *L 0.00198 *C 77.840 69.020 +*I mux_top_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 74.695 55.420 +*N chany_bottom_in[14]:4 *C 74.695 55.420 +*N chany_bottom_in[14]:5 *C 74.980 55.420 +*N chany_bottom_in[14]:6 *C 74.980 55.465 +*N chany_bottom_in[14]:7 *C 77.840 69.020 +*N chany_bottom_in[14]:8 *C 77.740 68.680 +*N chany_bottom_in[14]:9 *C 75.025 68.680 +*N chany_bottom_in[14]:10 *C 74.980 68.680 +*N chany_bottom_in[14]:11 *C 74.972 68.680 +*N chany_bottom_in[14]:12 *C 45.540 115.600 +*N chany_bottom_in[14]:13 *C 45.540 115.555 +*N chany_bottom_in[14]:14 *C 45.540 68.737 +*N chany_bottom_in[14]:15 *C 45.547 68.680 +*N chany_bottom_in[14]:16 *C 46.920 68.680 +*N chany_bottom_in[14]:17 *C 46.920 68.672 +*N chany_bottom_in[14]:18 *C 46.920 52.555 +*N chany_bottom_in[14]:19 *C 46.920 2.728 +*N chany_bottom_in[14]:20 *C 46.900 2.720 +*N chany_bottom_in[14]:21 *C 43.708 2.720 +*N chany_bottom_in[14]:22 *C 43.700 2.663 + +*CAP +0 chany_bottom_in[14] 9.782302e-05 +1 BUFT_RR_96:A 1e-06 +2 mux_right_track_18\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_4\/mux_l1_in_2_:A0 1e-06 +4 chany_bottom_in[14]:4 4.998716e-05 +5 chany_bottom_in[14]:5 5.448669e-05 +6 chany_bottom_in[14]:6 0.0008010593 +7 chany_bottom_in[14]:7 5.909242e-05 +8 chany_bottom_in[14]:8 0.0002323478 +9 chany_bottom_in[14]:9 0.00020303 +10 chany_bottom_in[14]:10 0.0008396565 +11 chany_bottom_in[14]:11 0.001179557 +12 chany_bottom_in[14]:12 3.330845e-05 +13 chany_bottom_in[14]:13 0.002437937 +14 chany_bottom_in[14]:14 0.002437937 +15 chany_bottom_in[14]:15 5.100501e-05 +16 chany_bottom_in[14]:16 0.001230562 +17 chany_bottom_in[14]:17 0.00083055 +18 chany_bottom_in[14]:18 0.002274705 +19 chany_bottom_in[14]:19 0.001444155 +20 chany_bottom_in[14]:20 0.0002683264 +21 chany_bottom_in[14]:21 0.0002683264 +22 chany_bottom_in[14]:22 9.782302e-05 +23 chany_bottom_in[14]:19 chany_bottom_in[5]:31 0.0005443045 +24 chany_bottom_in[14]:5 chany_bottom_in[5]:18 2.23482e-06 +25 chany_bottom_in[14]:4 chany_bottom_in[5]:19 2.23482e-06 +26 chany_bottom_in[14]:18 chany_bottom_in[5]:30 0.0005443045 +27 chany_bottom_in[14]:11 chanx_right_in[5]:12 0.0004542963 +28 chany_bottom_in[14]:16 chanx_right_in[5]:11 0.0004542963 +29 chany_bottom_in[14]:11 chanx_right_in[7] 0.0007519773 +30 chany_bottom_in[14]:16 chanx_right_in[7]:10 0.0007519773 +31 chany_bottom_in[14]:17 chany_bottom_in[15]:8 3.301384e-05 +32 chany_bottom_in[14]:20 chany_bottom_in[15]:11 2.048185e-05 +33 chany_bottom_in[14]:19 chany_bottom_in[15]:9 0.001045677 +34 chany_bottom_in[14]:21 chany_bottom_in[15]:10 2.048185e-05 +35 chany_bottom_in[14]:18 chany_bottom_in[15]:8 0.001045677 +36 chany_bottom_in[14]:18 chany_bottom_in[15]:9 3.301384e-05 +37 chany_bottom_in[14]:14 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 4.845243e-06 +38 chany_bottom_in[14]:15 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 8.717945e-05 +39 chany_bottom_in[14]:13 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 4.845243e-06 +40 chany_bottom_in[14]:11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 0.0003346684 +41 chany_bottom_in[14]:16 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 8.717945e-05 +42 chany_bottom_in[14]:16 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 0.0003346684 +43 chany_bottom_in[14]:14 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 5.311198e-05 +44 chany_bottom_in[14]:13 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 5.311198e-05 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:22 0.001194197 +1 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.04180134 +2 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.00341 +3 chany_bottom_in[14]:12 BUFT_RR_96:A 0.152 +4 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.0045 +5 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.002424107 +6 chany_bottom_in[14]:10 chany_bottom_in[14]:9 0.0045 +7 chany_bottom_in[14]:10 chany_bottom_in[14]:6 0.01179911 +8 chany_bottom_in[14]:7 mux_right_track_18\/mux_l1_in_1_:A1 0.152 +9 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.00341 +10 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.000215025 +11 chany_bottom_in[14]:16 chany_bottom_in[14]:11 0.004394891 +12 chany_bottom_in[14]:17 chany_bottom_in[14]:16 0.00341 +13 chany_bottom_in[14]:20 chany_bottom_in[14]:19 0.00341 +14 chany_bottom_in[14]:19 chany_bottom_in[14]:18 0.007806308 +15 chany_bottom_in[14]:22 chany_bottom_in[14]:21 0.00341 +16 chany_bottom_in[14]:21 chany_bottom_in[14]:20 0.0005001583 +17 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.0001548913 +18 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.0045 +19 chany_bottom_in[14]:4 mux_top_track_4\/mux_l1_in_2_:A0 0.152 +20 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.0003035715 +21 chany_bottom_in[14]:18 chany_bottom_in[14]:17 0.002525075 + +*END + +*D_NET prog_clk[0] 0.09957831 //LENGTH 749.633 LUMPCC 0.01411847 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 1.230 59.160 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 20.965 61.200 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 32.465 50.320 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 41.205 47.600 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 46.725 42.160 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 55.465 42.160 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 57.355 34.000 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.205 25.840 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 57.765 20.400 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.525 39.440 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 45.265 23.120 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 36.145 34.000 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 24.185 47.600 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 22.345 74.800 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 28.325 66.640 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.925 72.080 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 43.045 72.080 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 41.660 77.520 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 45.345 82.960 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 44.885 88.400 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.645 93.840 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 28.785 77.520 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 82.960 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 30.625 85.680 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.085 93.840 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 30.165 96.560 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 30.165 99.280 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 32.925 107.440 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 39.825 112.880 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 48.565 110.160 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.185 118.320 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 48.565 115.600 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 33.845 55.760 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.265 61.200 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 51.325 55.760 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 53.625 63.920 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 54.085 74.800 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 56.385 82.960 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 57.305 91.120 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 55.925 96.560 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 56.845 102.000 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 57.765 107.440 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.505 107.440 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 71.105 115.600 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 72.025 123.760 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 55.465 53.040 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 64.205 66.640 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.965 77.520 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 65.675 82.960 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 69.725 88.400 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.505 91.120 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 74.290 80.240 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 78.465 88.400 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 86.745 85.680 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 82.145 96.560 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 90.425 93.840 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 93.185 99.280 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.505 82.960 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 77.085 74.800 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 63.745 74.800 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 68.805 53.040 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 74.785 42.160 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 72.945 36.720 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.865 31.280 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 78.465 47.600 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 90.885 44.880 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 93.645 39.440 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 80.765 39.440 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 65.585 47.600 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 72.025 63.920 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 77.545 58.480 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 81.685 63.920 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 85.365 55.760 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 85.825 50.320 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 90.425 69.360 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 90.425 74.800 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 97.695 77.520 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 94.565 55.760 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 94.105 61.200 +*N prog_clk[0]:79 *C 94.105 61.200 +*N prog_clk[0]:80 *C 93.840 61.200 +*N prog_clk[0]:81 *C 93.840 61.155 +*N prog_clk[0]:82 *C 94.528 55.760 +*N prog_clk[0]:83 *C 93.885 55.760 +*N prog_clk[0]:84 *C 93.840 55.805 +*N prog_clk[0]:85 *C 93.840 59.160 +*N prog_clk[0]:86 *C 93.833 59.160 +*N prog_clk[0]:87 *C 97.695 77.520 +*N prog_clk[0]:88 *C 97.520 76.840 +*N prog_clk[0]:89 *C 95.680 76.840 +*N prog_clk[0]:90 *C 95.680 77.520 +*N prog_clk[0]:91 *C 90.160 77.520 +*N prog_clk[0]:92 *C 90.160 77.180 +*N prog_clk[0]:93 *C 90.160 77.135 +*N prog_clk[0]:94 *C 90.425 74.800 +*N prog_clk[0]:95 *C 90.160 75.140 +*N prog_clk[0]:96 *C 90.160 75.140 +*N prog_clk[0]:97 *C 90.425 69.360 +*N prog_clk[0]:98 *C 90.160 69.700 +*N prog_clk[0]:99 *C 90.160 69.700 +*N prog_clk[0]:100 *C 90.160 59.218 +*N prog_clk[0]:101 *C 90.160 59.160 +*N prog_clk[0]:102 *C 85.825 50.320 +*N prog_clk[0]:103 *C 85.560 50.320 +*N prog_clk[0]:104 *C 85.560 50.365 +*N prog_clk[0]:105 *C 85.365 55.760 +*N prog_clk[0]:106 *C 85.560 55.420 +*N prog_clk[0]:107 *C 85.560 55.420 +*N prog_clk[0]:108 *C 85.560 59.103 +*N prog_clk[0]:109 *C 85.560 59.160 +*N prog_clk[0]:110 *C 81.685 63.920 +*N prog_clk[0]:111 *C 81.880 63.920 +*N prog_clk[0]:112 *C 81.880 63.875 +*N prog_clk[0]:113 *C 81.880 59.218 +*N prog_clk[0]:114 *C 81.880 59.160 +*N prog_clk[0]:115 *C 77.545 58.480 +*N prog_clk[0]:116 *C 77.280 58.480 +*N prog_clk[0]:117 *C 77.280 58.525 +*N prog_clk[0]:118 *C 77.280 59.103 +*N prog_clk[0]:119 *C 77.280 59.160 +*N prog_clk[0]:120 *C 72.025 63.920 +*N prog_clk[0]:121 *C 72.220 63.920 +*N prog_clk[0]:122 *C 72.220 63.875 +*N prog_clk[0]:123 *C 72.220 59.218 +*N prog_clk[0]:124 *C 72.220 59.160 +*N prog_clk[0]:125 *C 65.585 47.600 +*N prog_clk[0]:126 *C 65.780 47.600 +*N prog_clk[0]:127 *C 80.765 39.440 +*N prog_clk[0]:128 *C 80.960 39.440 +*N prog_clk[0]:129 *C 80.960 39.485 +*N prog_clk[0]:130 *C 93.608 39.440 +*N prog_clk[0]:131 *C 92.965 39.440 +*N prog_clk[0]:132 *C 92.920 39.485 +*N prog_clk[0]:133 *C 92.920 44.823 +*N prog_clk[0]:134 *C 92.913 44.880 +*N prog_clk[0]:135 *C 90.885 44.880 +*N prog_clk[0]:136 *C 91.080 44.880 +*N prog_clk[0]:137 *C 91.080 44.880 +*N prog_clk[0]:138 *C 91.080 44.880 +*N prog_clk[0]:139 *C 80.968 44.880 +*N prog_clk[0]:140 *C 80.960 44.880 +*N prog_clk[0]:141 *C 80.960 47.543 +*N prog_clk[0]:142 *C 80.953 47.600 +*N prog_clk[0]:143 *C 78.465 47.600 +*N prog_clk[0]:144 *C 78.200 47.600 +*N prog_clk[0]:145 *C 78.200 47.600 +*N prog_clk[0]:146 *C 78.200 47.600 +*N prog_clk[0]:147 *C 73.865 31.280 +*N prog_clk[0]:148 *C 73.600 31.280 +*N prog_clk[0]:149 *C 73.600 31.280 +*N prog_clk[0]:150 *C 73.140 31.280 +*N prog_clk[0]:151 *C 72.945 36.720 +*N prog_clk[0]:152 *C 73.140 37.060 +*N prog_clk[0]:153 *C 73.140 37.060 +*N prog_clk[0]:154 *C 74.785 42.160 +*N prog_clk[0]:155 *C 74.520 42.160 +*N prog_clk[0]:156 *C 74.520 42.160 +*N prog_clk[0]:157 *C 74.513 42.160 +*N prog_clk[0]:158 *C 73.148 42.160 +*N prog_clk[0]:159 *C 73.140 42.160 +*N prog_clk[0]:160 *C 73.140 47.543 +*N prog_clk[0]:161 *C 73.140 47.600 +*N prog_clk[0]:162 *C 65.788 47.600 +*N prog_clk[0]:163 *C 65.780 47.600 +*N prog_clk[0]:164 *C 65.780 53.040 +*N prog_clk[0]:165 *C 68.767 53.040 +*N prog_clk[0]:166 *C 68.125 53.040 +*N prog_clk[0]:167 *C 68.080 53.040 +*N prog_clk[0]:168 *C 68.073 53.040 +*N prog_clk[0]:169 *C 66.248 53.040 +*N prog_clk[0]:170 *C 66.240 53.098 +*N prog_clk[0]:171 *C 66.240 59.103 +*N prog_clk[0]:172 *C 66.240 59.160 +*N prog_clk[0]:173 *C 63.745 74.800 +*N prog_clk[0]:174 *C 63.940 74.800 +*N prog_clk[0]:175 *C 63.940 74.800 +*N prog_clk[0]:176 *C 77.047 74.800 +*N prog_clk[0]:177 *C 76.405 74.800 +*N prog_clk[0]:178 *C 76.360 74.800 +*N prog_clk[0]:179 *C 76.353 74.800 +*N prog_clk[0]:180 *C 89.468 82.960 +*N prog_clk[0]:181 *C 88.365 82.960 +*N prog_clk[0]:182 *C 88.320 82.960 +*N prog_clk[0]:183 *C 88.312 82.960 +*N prog_clk[0]:184 *C 83.720 82.960 +*N prog_clk[0]:185 *C 93.185 99.280 +*N prog_clk[0]:186 *C 92.920 99.280 +*N prog_clk[0]:187 *C 92.920 99.235 +*N prog_clk[0]:188 *C 92.920 93.898 +*N prog_clk[0]:189 *C 92.913 93.840 +*N prog_clk[0]:190 *C 90.425 93.840 +*N prog_clk[0]:191 *C 90.160 93.840 +*N prog_clk[0]:192 *C 90.160 93.840 +*N prog_clk[0]:193 *C 90.160 93.840 +*N prog_clk[0]:194 *C 82.145 96.560 +*N prog_clk[0]:195 *C 82.340 96.560 +*N prog_clk[0]:196 *C 82.340 96.515 +*N prog_clk[0]:197 *C 82.340 93.898 +*N prog_clk[0]:198 *C 82.348 93.840 +*N prog_clk[0]:199 *C 84.180 93.840 +*N prog_clk[0]:200 *C 84.180 93.782 +*N prog_clk[0]:201 *C 86.708 85.680 +*N prog_clk[0]:202 *C 85.605 85.680 +*N prog_clk[0]:203 *C 85.560 85.680 +*N prog_clk[0]:204 *C 85.553 85.680 +*N prog_clk[0]:205 *C 84.188 85.680 +*N prog_clk[0]:206 *C 84.180 85.737 +*N prog_clk[0]:207 *C 83.720 85.680 +*N prog_clk[0]:208 *C 83.720 83.698 +*N prog_clk[0]:209 *C 83.720 83.633 +*N prog_clk[0]:210 *C 78.465 88.400 +*N prog_clk[0]:211 *C 78.200 88.400 +*N prog_clk[0]:212 *C 78.200 88.355 +*N prog_clk[0]:213 *C 78.200 83.698 +*N prog_clk[0]:214 *C 78.200 83.640 +*N prog_clk[0]:215 *C 74.528 83.640 +*N prog_clk[0]:216 *C 74.520 83.583 +*N prog_clk[0]:217 *C 74.290 80.240 +*N prog_clk[0]:218 *C 74.520 80.240 +*N prog_clk[0]:219 *C 74.520 80.240 +*N prog_clk[0]:220 *C 74.520 74.858 +*N prog_clk[0]:221 *C 74.520 74.800 +*N prog_clk[0]:222 *C 66.505 91.120 +*N prog_clk[0]:223 *C 66.700 91.120 +*N prog_clk[0]:224 *C 66.700 91.075 +*N prog_clk[0]:225 *C 66.700 88.400 +*N prog_clk[0]:226 *C 69.688 88.400 +*N prog_clk[0]:227 *C 69.045 88.400 +*N prog_clk[0]:228 *C 69.000 88.400 +*N prog_clk[0]:229 *C 68.993 88.400 +*N prog_clk[0]:230 *C 67.168 88.400 +*N prog_clk[0]:231 *C 67.160 88.343 +*N prog_clk[0]:232 *C 65.675 82.960 +*N prog_clk[0]:233 *C 65.780 82.960 +*N prog_clk[0]:234 *C 67.160 82.960 +*N prog_clk[0]:235 *C 66.965 77.520 +*N prog_clk[0]:236 *C 67.160 77.180 +*N prog_clk[0]:237 *C 67.160 77.180 +*N prog_clk[0]:238 *C 67.160 74.858 +*N prog_clk[0]:239 *C 67.160 74.800 +*N prog_clk[0]:240 *C 64.407 74.800 +*N prog_clk[0]:241 *C 64.400 74.743 +*N prog_clk[0]:242 *C 64.205 66.640 +*N prog_clk[0]:243 *C 64.400 66.300 +*N prog_clk[0]:244 *C 64.400 66.300 +*N prog_clk[0]:245 *C 64.400 59.218 +*N prog_clk[0]:246 *C 64.400 59.160 +*N prog_clk[0]:247 *C 55.465 53.040 +*N prog_clk[0]:248 *C 55.660 53.040 +*N prog_clk[0]:249 *C 55.660 53.085 +*N prog_clk[0]:250 *C 55.660 59.103 +*N prog_clk[0]:251 *C 55.660 59.160 +*N prog_clk[0]:252 *C 71.987 123.760 +*N prog_clk[0]:253 *C 70.885 123.760 +*N prog_clk[0]:254 *C 70.840 123.715 +*N prog_clk[0]:255 *C 71.105 115.600 +*N prog_clk[0]:256 *C 70.840 115.260 +*N prog_clk[0]:257 *C 70.840 115.260 +*N prog_clk[0]:258 *C 70.840 107.498 +*N prog_clk[0]:259 *C 70.833 107.440 +*N prog_clk[0]:260 *C 66.505 107.440 +*N prog_clk[0]:261 *C 66.240 107.440 +*N prog_clk[0]:262 *C 66.240 107.440 +*N prog_clk[0]:263 *C 66.240 107.440 +*N prog_clk[0]:264 *C 57.765 107.440 +*N prog_clk[0]:265 *C 57.500 107.440 +*N prog_clk[0]:266 *C 57.500 107.440 +*N prog_clk[0]:267 *C 57.500 107.440 +*N prog_clk[0]:268 *C 55.668 107.440 +*N prog_clk[0]:269 *C 55.660 107.383 +*N prog_clk[0]:270 *C 56.808 102.000 +*N prog_clk[0]:271 *C 55.660 102.000 +*N prog_clk[0]:272 *C 55.660 102.340 +*N prog_clk[0]:273 *C 55.660 102.340 +*N prog_clk[0]:274 *C 55.925 96.560 +*N prog_clk[0]:275 *C 55.660 96.900 +*N prog_clk[0]:276 *C 55.660 96.900 +*N prog_clk[0]:277 *C 57.305 91.120 +*N prog_clk[0]:278 *C 57.500 91.120 +*N prog_clk[0]:279 *C 57.500 91.120 +*N prog_clk[0]:280 *C 57.492 91.120 +*N prog_clk[0]:281 *C 55.668 91.120 +*N prog_clk[0]:282 *C 55.660 91.178 +*N prog_clk[0]:283 *C 55.200 91.120 +*N prog_clk[0]:284 *C 56.348 82.960 +*N prog_clk[0]:285 *C 55.200 82.960 +*N prog_clk[0]:286 *C 55.200 82.620 +*N prog_clk[0]:287 *C 55.170 82.650 +*N prog_clk[0]:288 *C 55.155 82.960 +*N prog_clk[0]:289 *C 54.740 82.960 +*N prog_clk[0]:290 *C 54.740 79.618 +*N prog_clk[0]:291 *C 54.733 79.560 +*N prog_clk[0]:292 *C 53.828 79.560 +*N prog_clk[0]:293 *C 53.820 79.502 +*N prog_clk[0]:294 *C 54.085 74.800 +*N prog_clk[0]:295 *C 53.820 75.140 +*N prog_clk[0]:296 *C 53.820 75.140 +*N prog_clk[0]:297 *C 53.625 63.920 +*N prog_clk[0]:298 *C 53.820 64.260 +*N prog_clk[0]:299 *C 53.820 64.260 +*N prog_clk[0]:300 *C 53.820 59.218 +*N prog_clk[0]:301 *C 53.820 59.160 +*N prog_clk[0]:302 *C 51.325 55.760 +*N prog_clk[0]:303 *C 51.060 55.760 +*N prog_clk[0]:304 *C 51.060 55.805 +*N prog_clk[0]:305 *C 51.060 59.103 +*N prog_clk[0]:306 *C 51.060 59.160 +*N prog_clk[0]:307 *C 46.265 61.200 +*N prog_clk[0]:308 *C 46.460 61.200 +*N prog_clk[0]:309 *C 46.460 61.155 +*N prog_clk[0]:310 *C 46.460 59.218 +*N prog_clk[0]:311 *C 46.460 59.160 +*N prog_clk[0]:312 *C 33.845 55.760 +*N prog_clk[0]:313 *C 33.580 55.760 +*N prog_clk[0]:314 *C 33.580 55.805 +*N prog_clk[0]:315 *C 33.580 59.103 +*N prog_clk[0]:316 *C 33.580 59.160 +*N prog_clk[0]:317 *C 48.565 115.600 +*N prog_clk[0]:318 *C 47.185 118.320 +*N prog_clk[0]:319 *C 47.380 118.320 +*N prog_clk[0]:320 *C 47.380 118.275 +*N prog_clk[0]:321 *C 47.380 115.305 +*N prog_clk[0]:322 *C 47.425 115.260 +*N prog_clk[0]:323 *C 48.345 115.268 +*N prog_clk[0]:324 *C 48.300 115.215 +*N prog_clk[0]:325 *C 48.565 110.160 +*N prog_clk[0]:326 *C 48.300 110.160 +*N prog_clk[0]:327 *C 48.300 110.160 +*N prog_clk[0]:328 *C 48.300 108.858 +*N prog_clk[0]:329 *C 48.293 108.800 +*N prog_clk[0]:330 *C 39.825 112.880 +*N prog_clk[0]:331 *C 40.020 112.880 +*N prog_clk[0]:332 *C 40.020 112.835 +*N prog_clk[0]:333 *C 40.020 108.858 +*N prog_clk[0]:334 *C 40.020 108.800 +*N prog_clk[0]:335 *C 33.128 108.800 +*N prog_clk[0]:336 *C 33.120 108.743 +*N prog_clk[0]:337 *C 32.925 107.440 +*N prog_clk[0]:338 *C 33.120 107.780 +*N prog_clk[0]:339 *C 33.120 107.780 +*N prog_clk[0]:340 *C 33.120 104.098 +*N prog_clk[0]:341 *C 33.113 104.040 +*N prog_clk[0]:342 *C 30.367 104.040 +*N prog_clk[0]:343 *C 30.360 103.983 +*N prog_clk[0]:344 *C 30.165 99.280 +*N prog_clk[0]:345 *C 30.360 98.940 +*N prog_clk[0]:346 *C 30.360 98.940 +*N prog_clk[0]:347 *C 30.165 96.560 +*N prog_clk[0]:348 *C 30.360 96.900 +*N prog_clk[0]:349 *C 30.360 96.900 +*N prog_clk[0]:350 *C 30.820 96.900 +*N prog_clk[0]:351 *C 31.085 93.840 +*N prog_clk[0]:352 *C 30.820 93.500 +*N prog_clk[0]:353 *C 30.820 93.500 +*N prog_clk[0]:354 *C 30.625 85.680 +*N prog_clk[0]:355 *C 30.820 86.020 +*N prog_clk[0]:356 *C 30.820 86.020 +*N prog_clk[0]:357 *C 31.508 82.960 +*N prog_clk[0]:358 *C 30.865 82.960 +*N prog_clk[0]:359 *C 30.820 82.960 +*N prog_clk[0]:360 *C 30.812 82.960 +*N prog_clk[0]:361 *C 28.527 82.960 +*N prog_clk[0]:362 *C 28.520 82.903 +*N prog_clk[0]:363 *C 28.785 77.520 +*N prog_clk[0]:364 *C 28.520 77.180 +*N prog_clk[0]:365 *C 28.520 77.180 +*N prog_clk[0]:366 *C 47.645 93.840 +*N prog_clk[0]:367 *C 47.380 93.840 +*N prog_clk[0]:368 *C 47.380 93.840 +*N prog_clk[0]:369 *C 47.373 93.840 +*N prog_clk[0]:370 *C 44.628 93.840 +*N prog_clk[0]:371 *C 44.620 93.782 +*N prog_clk[0]:372 *C 44.885 88.400 +*N prog_clk[0]:373 *C 44.620 88.060 +*N prog_clk[0]:374 *C 44.620 88.060 +*N prog_clk[0]:375 *C 45.308 82.960 +*N prog_clk[0]:376 *C 44.620 82.960 +*N prog_clk[0]:377 *C 44.620 82.620 +*N prog_clk[0]:378 *C 44.620 82.620 +*N prog_clk[0]:379 *C 44.620 81.657 +*N prog_clk[0]:380 *C 44.613 81.600 +*N prog_clk[0]:381 *C 40.948 81.600 +*N prog_clk[0]:382 *C 40.940 81.543 +*N prog_clk[0]:383 *C 41.623 77.520 +*N prog_clk[0]:384 *C 40.985 77.520 +*N prog_clk[0]:385 *C 40.940 77.520 +*N prog_clk[0]:386 *C 43.008 72.080 +*N prog_clk[0]:387 *C 40.985 72.080 +*N prog_clk[0]:388 *C 40.940 72.080 +*N prog_clk[0]:389 *C 40.933 72.080 +*N prog_clk[0]:390 *C 32.925 72.080 +*N prog_clk[0]:391 *C 33.120 72.080 +*N prog_clk[0]:392 *C 33.120 72.080 +*N prog_clk[0]:393 *C 33.120 72.080 +*N prog_clk[0]:394 *C 28.527 72.080 +*N prog_clk[0]:395 *C 28.520 72.080 +*N prog_clk[0]:396 *C 28.325 66.640 +*N prog_clk[0]:397 *C 28.520 66.640 +*N prog_clk[0]:398 *C 28.520 66.685 +*N prog_clk[0]:399 *C 28.520 67.320 +*N prog_clk[0]:400 *C 28.513 67.320 +*N prog_clk[0]:401 *C 22.345 74.800 +*N prog_clk[0]:402 *C 22.540 74.800 +*N prog_clk[0]:403 *C 22.540 74.755 +*N prog_clk[0]:404 *C 22.540 67.377 +*N prog_clk[0]:405 *C 22.547 67.320 +*N prog_clk[0]:406 *C 24.380 67.320 +*N prog_clk[0]:407 *C 24.380 67.263 +*N prog_clk[0]:408 *C 24.185 47.600 +*N prog_clk[0]:409 *C 24.380 47.600 +*N prog_clk[0]:410 *C 24.380 47.645 +*N prog_clk[0]:411 *C 36.145 34.000 +*N prog_clk[0]:412 *C 36.340 34.000 +*N prog_clk[0]:413 *C 45.265 23.120 +*N prog_clk[0]:414 *C 45.080 23.120 +*N prog_clk[0]:415 *C 45.080 23.165 +*N prog_clk[0]:416 *C 45.080 28.900 +*N prog_clk[0]:417 *C 44.620 28.900 +*N prog_clk[0]:418 *C 44.620 33.943 +*N prog_clk[0]:419 *C 44.613 34.000 +*N prog_clk[0]:420 *C 36.348 34.000 +*N prog_clk[0]:421 *C 36.340 34.000 +*N prog_clk[0]:422 *C 37.488 39.440 +*N prog_clk[0]:423 *C 36.340 39.440 +*N prog_clk[0]:424 *C 36.340 39.100 +*N prog_clk[0]:425 *C 36.340 39.100 +*N prog_clk[0]:426 *C 57.765 20.400 +*N prog_clk[0]:427 *C 57.960 20.400 +*N prog_clk[0]:428 *C 57.960 20.445 +*N prog_clk[0]:429 *C 57.960 25.840 +*N prog_clk[0]:430 *C 64.168 25.840 +*N prog_clk[0]:431 *C 63.525 25.840 +*N prog_clk[0]:432 *C 63.480 25.840 +*N prog_clk[0]:433 *C 63.473 25.840 +*N prog_clk[0]:434 *C 58.428 25.840 +*N prog_clk[0]:435 *C 58.420 25.898 +*N prog_clk[0]:436 *C 57.355 34.000 +*N prog_clk[0]:437 *C 57.500 33.660 +*N prog_clk[0]:438 *C 57.915 33.660 +*N prog_clk[0]:439 *C 57.960 33.660 +*N prog_clk[0]:440 *C 58.420 33.660 +*N prog_clk[0]:441 *C 58.420 42.102 +*N prog_clk[0]:442 *C 58.413 42.160 +*N prog_clk[0]:443 *C 55.465 42.160 +*N prog_clk[0]:444 *C 55.660 42.160 +*N prog_clk[0]:445 *C 55.660 42.160 +*N prog_clk[0]:446 *C 55.660 42.160 +*N prog_clk[0]:447 *C 46.725 42.160 +*N prog_clk[0]:448 *C 46.460 42.160 +*N prog_clk[0]:449 *C 46.460 42.160 +*N prog_clk[0]:450 *C 46.460 42.160 +*N prog_clk[0]:451 *C 36.348 42.160 +*N prog_clk[0]:452 *C 36.340 42.160 +*N prog_clk[0]:453 *C 41.205 47.600 +*N prog_clk[0]:454 *C 40.940 47.600 +*N prog_clk[0]:455 *C 40.940 47.600 +*N prog_clk[0]:456 *C 40.933 47.600 +*N prog_clk[0]:457 *C 36.348 47.600 +*N prog_clk[0]:458 *C 36.340 47.600 +*N prog_clk[0]:459 *C 36.340 50.263 +*N prog_clk[0]:460 *C 36.333 50.320 +*N prog_clk[0]:461 *C 32.465 50.320 +*N prog_clk[0]:462 *C 32.200 50.320 +*N prog_clk[0]:463 *C 32.200 50.320 +*N prog_clk[0]:464 *C 32.200 50.320 +*N prog_clk[0]:465 *C 24.388 50.320 +*N prog_clk[0]:466 *C 24.380 50.320 +*N prog_clk[0]:467 *C 24.380 59.160 +*N prog_clk[0]:468 *C 24.380 59.160 +*N prog_clk[0]:469 *C 20.965 61.200 +*N prog_clk[0]:470 *C 21.160 61.200 +*N prog_clk[0]:471 *C 21.160 61.155 +*N prog_clk[0]:472 *C 21.160 59.218 +*N prog_clk[0]:473 *C 21.160 59.160 + +*CAP +0 prog_clk[0] 0.0008304185 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +2 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +4 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +5 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +6 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +7 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +8 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +9 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +11 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +12 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +13 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +14 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +15 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +16 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +17 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +18 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +19 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +21 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +22 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +23 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +24 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +25 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +27 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +28 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +29 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +32 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +33 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +34 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +36 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +37 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +38 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +39 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +40 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +41 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +42 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +43 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +44 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +46 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +47 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +48 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +49 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +50 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +51 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +52 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +54 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +55 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +56 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +57 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +58 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +59 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +60 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +61 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +62 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +63 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +64 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +65 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +66 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +67 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +68 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +69 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +70 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +71 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +72 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +73 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +74 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +75 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +76 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +77 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +78 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +79 prog_clk[0]:79 5.307683e-05 +80 prog_clk[0]:80 5.745382e-05 +81 prog_clk[0]:81 0.0001160721 +82 prog_clk[0]:82 7.873483e-05 +83 prog_clk[0]:83 7.873483e-05 +84 prog_clk[0]:84 0.000197453 +85 prog_clk[0]:85 0.000349112 +86 prog_clk[0]:86 0.0001392245 +87 prog_clk[0]:87 7.050336e-05 +88 prog_clk[0]:88 0.0001709113 +89 prog_clk[0]:89 0.0001681037 +90 prog_clk[0]:90 0.000314434 +91 prog_clk[0]:91 0.0003037351 +92 prog_clk[0]:92 6.477017e-05 +93 prog_clk[0]:93 0.0001125544 +94 prog_clk[0]:94 6.060225e-05 +95 prog_clk[0]:95 6.2799e-05 +96 prog_clk[0]:96 0.0004268751 +97 prog_clk[0]:97 6.839677e-05 +98 prog_clk[0]:98 7.149777e-05 +99 prog_clk[0]:99 0.0008151436 +100 prog_clk[0]:100 0.0004977577 +101 prog_clk[0]:101 0.0003006841 +102 prog_clk[0]:102 5.985943e-05 +103 prog_clk[0]:103 6.097258e-05 +104 prog_clk[0]:104 0.0002855066 +105 prog_clk[0]:105 6.881556e-05 +106 prog_clk[0]:106 7.170398e-05 +107 prog_clk[0]:107 0.0005458375 +108 prog_clk[0]:108 0.0002261284 +109 prog_clk[0]:109 0.0003508743 +110 prog_clk[0]:110 6.030439e-05 +111 prog_clk[0]:111 6.072246e-05 +112 prog_clk[0]:112 0.0002432815 +113 prog_clk[0]:113 0.0002432815 +114 prog_clk[0]:114 0.0004325434 +115 prog_clk[0]:115 5.97351e-05 +116 prog_clk[0]:116 6.129468e-05 +117 prog_clk[0]:117 6.292959e-05 +118 prog_clk[0]:118 6.292959e-05 +119 prog_clk[0]:119 0.0005089707 +120 prog_clk[0]:120 6.413722e-05 +121 prog_clk[0]:121 6.685637e-05 +122 prog_clk[0]:122 0.0002841179 +123 prog_clk[0]:123 0.0002841179 +124 prog_clk[0]:124 0.0006398219 +125 prog_clk[0]:125 6.544239e-05 +126 prog_clk[0]:126 6.380085e-05 +127 prog_clk[0]:127 5.783634e-05 +128 prog_clk[0]:128 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prog_clk[0]:276 chany_bottom_in[5]:26 9.443239e-06 +554 prog_clk[0]:301 chany_bottom_in[5]:25 4.099763e-06 +555 prog_clk[0]:259 chany_bottom_in[5]:7 1.209242e-06 +556 prog_clk[0]:273 chany_bottom_in[5]:17 9.443239e-06 +557 prog_clk[0]:263 chany_bottom_in[5]:16 1.209242e-06 +558 prog_clk[0]:329 chany_bottom_in[5]:12 0.00014177 +559 prog_clk[0]:251 chany_bottom_in[5]:24 4.099763e-06 +560 prog_clk[0]:251 chany_bottom_in[5]:25 4.454146e-05 +561 prog_clk[0]:296 chany_bottom_in[5]:17 5.702622e-06 +562 prog_clk[0]:299 chany_bottom_in[5]:26 5.702622e-06 +563 prog_clk[0]:124 chany_bottom_in[5]:24 2.775723e-05 +564 prog_clk[0]:124 chany_bottom_in[5]:25 5.47812e-06 +565 prog_clk[0]:119 chany_bottom_in[5]:24 5.47812e-06 +566 prog_clk[0]:282 chany_bottom_in[5]:26 8.044556e-06 +567 prog_clk[0]:288 chany_bottom_in[5]:26 1.546125e-05 +568 prog_clk[0]:283 chany_bottom_in[5]:17 1.546125e-05 +569 prog_clk[0]:246 chany_bottom_in[6]:17 3.56392e-05 +570 prog_clk[0]:246 chany_bottom_in[6]:22 0.0001588424 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0.0001147512 +589 prog_clk[0]:353 chany_bottom_in[9]:12 4.979271e-06 +590 prog_clk[0]:339 chany_bottom_in[9]:7 6.47456e-07 +591 prog_clk[0]:339 chany_bottom_in[9]:8 3.000709e-06 +592 prog_clk[0]:356 chany_bottom_in[9]:12 6.826017e-06 +593 prog_clk[0]:356 chany_bottom_in[9]:13 4.979271e-06 +594 prog_clk[0]:365 chany_bottom_in[9]:18 1.802456e-05 +595 prog_clk[0]:410 chany_bottom_in[9]:23 1.130505e-05 +596 prog_clk[0]:472 chany_bottom_in[9]:22 3.321195e-05 +597 prog_clk[0]:472 chany_bottom_in[9]:23 3.118683e-05 +598 prog_clk[0]:471 chany_bottom_in[9]:21 3.321195e-05 +599 prog_clk[0]:471 chany_bottom_in[9]:22 3.118683e-05 +600 prog_clk[0] top_left_grid_pin_1_[0]:22 0.000222601 +601 prog_clk[0]:85 top_left_grid_pin_1_[0]:7 1.373955e-07 +602 prog_clk[0]:85 top_left_grid_pin_1_[0]:6 2.371897e-06 +603 prog_clk[0]:406 top_left_grid_pin_1_[0]:22 1.321864e-05 +604 prog_clk[0]:406 top_left_grid_pin_1_[0]:21 8.909669e-06 +605 prog_clk[0]:468 top_left_grid_pin_1_[0]:22 7.342699e-05 +606 prog_clk[0]:468 top_left_grid_pin_1_[0]:21 3.906427e-05 +607 prog_clk[0]:400 top_left_grid_pin_1_[0]:21 1.321864e-05 +608 prog_clk[0]:246 top_left_grid_pin_1_[0]:20 6.417111e-05 +609 prog_clk[0]:246 top_left_grid_pin_1_[0]:21 1.316322e-05 +610 prog_clk[0]:172 top_left_grid_pin_1_[0]:20 1.316322e-05 +611 prog_clk[0]:172 top_left_grid_pin_1_[0]:21 3.317557e-05 +612 prog_clk[0]:405 top_left_grid_pin_1_[0]:22 8.909669e-06 +613 prog_clk[0]:301 top_left_grid_pin_1_[0]:20 5.565114e-06 +614 prog_clk[0]:301 top_left_grid_pin_1_[0]:21 2.41321e-05 +615 prog_clk[0]:316 top_left_grid_pin_1_[0]:22 0.0001093618 +616 prog_clk[0]:316 top_left_grid_pin_1_[0]:21 7.342699e-05 +617 prog_clk[0]:306 top_left_grid_pin_1_[0]:22 1.489581e-05 +618 prog_clk[0]:306 top_left_grid_pin_1_[0]:21 4.610451e-05 +619 prog_clk[0]:251 top_left_grid_pin_1_[0]:20 9.236293e-06 +620 prog_clk[0]:251 top_left_grid_pin_1_[0]:21 6.417111e-05 +621 prog_clk[0]:311 top_left_grid_pin_1_[0]:22 4.053939e-05 +622 prog_clk[0]:311 top_left_grid_pin_1_[0]:21 0.0001093618 +623 prog_clk[0]:123 top_left_grid_pin_1_[0]:14 3.540591e-06 +624 prog_clk[0]:124 top_left_grid_pin_1_[0]:20 3.317557e-05 +625 prog_clk[0]:124 top_left_grid_pin_1_[0]:21 3.269324e-06 +626 prog_clk[0]:122 top_left_grid_pin_1_[0]:19 3.540591e-06 +627 prog_clk[0]:107 top_left_grid_pin_1_[0]:11 1.169113e-06 +628 prog_clk[0]:84 top_left_grid_pin_1_[0]:7 2.371897e-06 +629 prog_clk[0]:81 top_left_grid_pin_1_[0]:6 1.373955e-07 +630 prog_clk[0]:119 top_left_grid_pin_1_[0]:20 3.269324e-06 +631 prog_clk[0]:104 top_left_grid_pin_1_[0]:10 1.169113e-06 +632 prog_clk[0]:473 top_left_grid_pin_1_[0]:22 3.906427e-05 +633 prog_clk[0]:473 top_left_grid_pin_1_[0]:21 0.000222601 +634 prog_clk[0]:161 chanx_right_in[0] 0.0001476967 +635 prog_clk[0]:161 chanx_right_in[0]:11 9.440506e-05 +636 prog_clk[0]:142 chanx_right_in[0] 6.055593e-05 +637 prog_clk[0]:162 chanx_right_in[0]:11 0.0001476967 +638 prog_clk[0]:139 chanx_right_in[0]:11 4.874066e-07 +639 prog_clk[0]:169 chanx_right_in[0]:11 6.572648e-06 +640 prog_clk[0]:168 chanx_right_in[0] 6.572648e-06 +641 prog_clk[0]:138 chanx_right_in[0] 4.874066e-07 +642 prog_clk[0]:146 chanx_right_in[0] 9.440506e-05 +643 prog_clk[0]:146 chanx_right_in[0]:11 6.055593e-05 +644 prog_clk[0]:141 chanx_right_in[4]:13 1.968632e-06 +645 prog_clk[0]:86 chanx_right_in[4]:15 9.267002e-05 +646 prog_clk[0]:140 chanx_right_in[4]:12 1.968632e-06 +647 prog_clk[0]:109 chanx_right_in[4]:15 7.460775e-05 +648 prog_clk[0]:109 chanx_right_in[4]:14 0.0001129805 +649 prog_clk[0]:101 chanx_right_in[4]:15 0.0001129805 +650 prog_clk[0]:101 chanx_right_in[4]:14 9.267002e-05 +651 prog_clk[0]:123 chanx_right_in[4]:6 8.015794e-06 +652 prog_clk[0]:124 chanx_right_in[4]:7 9.14933e-05 +653 prog_clk[0]:122 chanx_right_in[4]:5 8.015794e-06 +654 prog_clk[0]:118 chanx_right_in[4]:13 1.867215e-06 +655 prog_clk[0]:119 chanx_right_in[4]:7 3.597101e-05 +656 prog_clk[0]:119 chanx_right_in[4]:14 0.0001456154 +657 prog_clk[0]:117 chanx_right_in[4]:12 1.867215e-06 +658 prog_clk[0]:114 chanx_right_in[4]:15 5.412209e-05 +659 prog_clk[0]:114 chanx_right_in[4]:14 0.0001105788 +660 prog_clk[0]:421 chanx_right_in[13]:10 2.417962e-05 +661 prog_clk[0]:421 chanx_right_in[13]:11 2.200415e-05 +662 prog_clk[0]:420 chanx_right_in[13]:12 0.0004682779 +663 prog_clk[0]:419 chanx_right_in[13]:13 0.0004682779 +664 prog_clk[0]:459 chanx_right_in[13]:5 3.965082e-05 +665 prog_clk[0]:452 chanx_right_in[13]:5 2.670041e-05 +666 prog_clk[0]:452 chanx_right_in[13]:7 9.689627e-06 +667 prog_clk[0]:452 chanx_right_in[13]:6 6.911314e-05 +668 prog_clk[0]:315 chanx_right_in[13]:5 1.934165e-05 +669 prog_clk[0]:314 chanx_right_in[13]:6 1.934165e-05 +670 prog_clk[0]:458 chanx_right_in[13]:5 6.911314e-05 +671 prog_clk[0]:458 chanx_right_in[13]:6 3.965082e-05 +672 prog_clk[0]:435 chanx_right_in[13]:14 7.394791e-06 +673 prog_clk[0]:425 chanx_right_in[13]:10 3.169378e-05 +674 prog_clk[0]:425 chanx_right_in[13]:7 2.417962e-05 +675 prog_clk[0]:425 chanx_right_in[13]:6 2.670041e-05 +676 prog_clk[0]:440 chanx_right_in[13]:13 7.394791e-06 +677 prog_clk[0]:96 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 5.347799e-07 +678 prog_clk[0]:96 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 4.105535e-06 +679 prog_clk[0]:93 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 4.105535e-06 +680 prog_clk[0]:99 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 5.347799e-07 +681 prog_clk[0]:91 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 7.294807e-05 +682 prog_clk[0]:90 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 7.294807e-05 +683 prog_clk[0]:241 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 5.553594e-05 +684 prog_clk[0]:238 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 1.285812e-06 +685 prog_clk[0]:237 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 1.285812e-06 +686 prog_clk[0]:244 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 5.553594e-05 +687 prog_clk[0]:237 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 5.969356e-06 +688 prog_clk[0]:231 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 3.072024e-05 +689 prog_clk[0]:234 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 5.969356e-06 +690 prog_clk[0]:234 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 3.072024e-05 +691 prog_clk[0]:343 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 3.787039e-05 +692 prog_clk[0]:349 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 8.127158e-06 +693 prog_clk[0]:349 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 7.269145e-06 +694 prog_clk[0]:345 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 2.548364e-06 +695 prog_clk[0]:346 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 3.787039e-05 +696 prog_clk[0]:346 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 7.269145e-06 +697 prog_clk[0]:344 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 2.548364e-06 +698 prog_clk[0]:350 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 8.127158e-06 +699 prog_clk[0]:100 mux_tree_tapbuf_size6_0_sram[2]:6 9.585111e-05 +700 prog_clk[0]:99 mux_tree_tapbuf_size6_0_sram[2]:5 9.585111e-05 +701 prog_clk[0]:161 mux_tree_tapbuf_size6_1_sram[0]:17 2.494643e-05 +702 prog_clk[0]:141 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mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 4.191712e-05 +717 prog_clk[0]:132 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 4.191712e-05 +718 prog_clk[0]:100 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.215379e-05 +719 prog_clk[0]:96 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.525781e-05 +720 prog_clk[0]:99 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.525781e-05 +721 prog_clk[0]:99 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.215379e-05 +722 prog_clk[0]:113 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.570601e-05 +723 prog_clk[0]:112 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.570601e-05 +724 prog_clk[0]:245 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.96478e-05 +725 prog_clk[0]:171 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.07473e-06 +726 prog_clk[0]:170 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.07473e-06 +727 prog_clk[0]:244 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.96478e-05 +728 prog_clk[0]:241 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.390595e-05 +729 prog_clk[0]:245 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.254466e-05 +730 prog_clk[0]:244 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.254466e-05 +731 prog_clk[0]:244 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.390595e-05 +732 prog_clk[0]:418 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 4.665687e-05 +733 prog_clk[0]:415 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 2.306712e-05 +734 prog_clk[0]:417 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 4.665687e-05 +735 prog_clk[0]:416 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 2.306712e-05 +736 prog_clk[0]:441 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001125002 +737 prog_clk[0]:435 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.757942e-05 +738 prog_clk[0]:428 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001537934 +739 prog_clk[0]:429 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001537934 +740 prog_clk[0]:440 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001125002 +741 prog_clk[0]:440 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.757942e-05 +742 prog_clk[0]:205 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.400168e-05 +743 prog_clk[0]:204 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.400168e-05 +744 prog_clk[0]:209 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001168647 +745 prog_clk[0]:183 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.124866e-05 +746 prog_clk[0]:233 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.000478e-06 +747 prog_clk[0]:215 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.102584e-05 +748 prog_clk[0]:230 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.776195e-07 +749 prog_clk[0]:229 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.776195e-07 +750 prog_clk[0]:214 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001168647 +751 prog_clk[0]:214 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mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.330699e-05 +763 prog_clk[0]:314 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.330699e-05 +764 prog_clk[0]:199 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001321912 +765 prog_clk[0]:199 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 3.306823e-05 +766 prog_clk[0]:259 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 6.939541e-06 +767 prog_clk[0]:267 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 1.041836e-05 +768 prog_clk[0]:263 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 6.939541e-06 +769 prog_clk[0]:263 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 1.041836e-05 +770 prog_clk[0]:189 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.232142e-05 +771 prog_clk[0]:193 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.232142e-05 +772 prog_clk[0]:193 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001321912 +773 prog_clk[0]:198 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.306823e-05 +774 prog_clk[0]:91 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.542368e-05 +775 prog_clk[0]:90 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.542368e-05 +776 prog_clk[0]:96 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.789717e-06 +777 prog_clk[0]:93 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.789717e-06 +778 prog_clk[0]:91 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.524938e-05 +779 prog_clk[0]:90 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.524938e-05 +780 prog_clk[0]:209 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.57902e-05 +781 prog_clk[0]:183 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001152855 +782 prog_clk[0]:233 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.000478e-06 +783 prog_clk[0]:215 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.551098e-05 +784 prog_clk[0]:214 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.57902e-05 +785 prog_clk[0]:214 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.551098e-05 +786 prog_clk[0]:234 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.000478e-06 +787 prog_clk[0]:184 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001152855 + +*RES +0 prog_clk[0] prog_clk[0]:473 0.003122366 +1 prog_clk[0]:206 prog_clk[0]:205 0.00341 +2 prog_clk[0]:206 prog_clk[0]:200 0.007183036 +3 prog_clk[0]:205 prog_clk[0]:204 0.00021385 +4 prog_clk[0]:203 prog_clk[0]:202 0.0045 +5 prog_clk[0]:204 prog_clk[0]:203 0.00341 +6 prog_clk[0]:202 prog_clk[0]:201 0.000984375 +7 prog_clk[0]:201 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +8 prog_clk[0]:333 prog_clk[0]:332 0.003551339 +9 prog_clk[0]:334 prog_clk[0]:333 0.00341 +10 prog_clk[0]:334 prog_clk[0]:329 0.001296025 +11 prog_clk[0]:331 prog_clk[0]:330 0.0001059783 +12 prog_clk[0]:332 prog_clk[0]:331 0.0045 +13 prog_clk[0]:330 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +14 prog_clk[0]:388 prog_clk[0]:387 0.0045 +15 prog_clk[0]:388 prog_clk[0]:385 0.004857143 +16 prog_clk[0]:389 prog_clk[0]:388 0.00341 +17 prog_clk[0]:421 prog_clk[0]:420 0.00341 +18 prog_clk[0]:421 prog_clk[0]:412 0.0045 +19 prog_clk[0]:420 prog_clk[0]:419 0.00129485 +20 prog_clk[0]:418 prog_clk[0]:417 0.004502232 +21 prog_clk[0]:419 prog_clk[0]:418 0.00341 +22 prog_clk[0]:414 prog_clk[0]:413 0.0001005435 +23 prog_clk[0]:415 prog_clk[0]:414 0.0045 +24 prog_clk[0]:413 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +25 prog_clk[0]:160 prog_clk[0]:159 0.004805804 +26 prog_clk[0]:161 prog_clk[0]:160 0.00341 +27 prog_clk[0]:161 prog_clk[0]:146 0.0007927333 +28 prog_clk[0]:141 prog_clk[0]:140 0.002377232 +29 prog_clk[0]:142 prog_clk[0]:141 0.00341 +30 prog_clk[0]:208 prog_clk[0]:207 0.001770089 +31 prog_clk[0]:209 prog_clk[0]:208 0.00341 +32 prog_clk[0]:209 prog_clk[0]:184 0.0001053583 +33 prog_clk[0]:163 prog_clk[0]:162 0.00341 +34 prog_clk[0]:163 prog_clk[0]:126 0.0045 +35 prog_clk[0]:162 prog_clk[0]:161 0.001151892 +36 prog_clk[0]:85 prog_clk[0]:84 0.002995536 +37 prog_clk[0]:85 prog_clk[0]:81 0.00178125 +38 prog_clk[0]:86 prog_clk[0]:85 0.00341 +39 prog_clk[0]:241 prog_clk[0]:240 0.00341 +40 prog_clk[0]:241 prog_clk[0]:175 0.0004107143 +41 prog_clk[0]:240 prog_clk[0]:239 0.000431225 +42 prog_clk[0]:407 prog_clk[0]:406 0.00341 +43 prog_clk[0]:406 prog_clk[0]:405 0.0002870917 +44 prog_clk[0]:406 prog_clk[0]:400 0.000647425 +45 prog_clk[0]:467 prog_clk[0]:466 0.007892857 +46 prog_clk[0]:467 prog_clk[0]:407 0.007234375 +47 prog_clk[0]:468 prog_clk[0]:467 0.00341 +48 prog_clk[0]:468 prog_clk[0]:316 0.001441333 +49 prog_clk[0]:399 prog_clk[0]:398 0.0005669643 +50 prog_clk[0]:399 prog_clk[0]:395 0.00425 +51 prog_clk[0]:400 prog_clk[0]:399 0.00341 +52 prog_clk[0]:182 prog_clk[0]:181 0.0045 +53 prog_clk[0]:183 prog_clk[0]:182 0.00341 +54 prog_clk[0]:181 prog_clk[0]:180 0.000984375 +55 prog_clk[0]:180 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +56 prog_clk[0]:343 prog_clk[0]:342 0.00341 +57 prog_clk[0]:342 prog_clk[0]:341 0.00043005 +58 prog_clk[0]:340 prog_clk[0]:339 0.003287947 +59 prog_clk[0]:341 prog_clk[0]:340 0.00341 +60 prog_clk[0]:379 prog_clk[0]:378 0.0008593751 +61 prog_clk[0]:380 prog_clk[0]:379 0.00341 +62 prog_clk[0]:382 prog_clk[0]:381 0.00341 +63 prog_clk[0]:381 prog_clk[0]:380 0.0005741833 +64 prog_clk[0]:245 prog_clk[0]:244 0.006323661 +65 prog_clk[0]:246 prog_clk[0]:245 0.00341 +66 prog_clk[0]:246 prog_clk[0]:172 0.0002882667 +67 prog_clk[0]:323 prog_clk[0]:322 0.0008214287 +68 prog_clk[0]:323 prog_clk[0]:317 0.0001807065 +69 prog_clk[0]:324 prog_clk[0]:323 0.0045 +70 prog_clk[0]:140 prog_clk[0]:139 0.00341 +71 prog_clk[0]:140 prog_clk[0]:129 0.004816964 +72 prog_clk[0]:139 prog_clk[0]:138 0.001584292 +73 prog_clk[0]:159 prog_clk[0]:158 0.00341 +74 prog_clk[0]:159 prog_clk[0]:153 0.004553571 +75 prog_clk[0]:158 prog_clk[0]:157 0.00021385 +76 prog_clk[0]:156 prog_clk[0]:155 0.0045 +77 prog_clk[0]:157 prog_clk[0]:156 0.00341 +78 prog_clk[0]:155 prog_clk[0]:154 0.0001440218 +79 prog_clk[0]:154 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +80 prog_clk[0]:359 prog_clk[0]:358 0.0045 +81 prog_clk[0]:359 prog_clk[0]:356 0.002732143 +82 prog_clk[0]:360 prog_clk[0]:359 0.00341 +83 prog_clk[0]:362 prog_clk[0]:361 0.00341 +84 prog_clk[0]:361 prog_clk[0]:360 0.0003579833 +85 prog_clk[0]:269 prog_clk[0]:268 0.00341 +86 prog_clk[0]:268 prog_clk[0]:267 0.0002870917 +87 prog_clk[0]:387 prog_clk[0]:386 0.001805804 +88 prog_clk[0]:386 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +89 prog_clk[0]:466 prog_clk[0]:465 0.00341 +90 prog_clk[0]:466 prog_clk[0]:410 0.002388393 +91 prog_clk[0]:465 prog_clk[0]:464 0.001223958 +92 prog_clk[0]:171 prog_clk[0]:170 0.005361607 +93 prog_clk[0]:172 prog_clk[0]:171 0.00341 +94 prog_clk[0]:172 prog_clk[0]:124 0.0009368666 +95 prog_clk[0]:336 prog_clk[0]:335 0.00341 +96 prog_clk[0]:335 prog_clk[0]:334 0.001079825 +97 prog_clk[0]:371 prog_clk[0]:370 0.00341 +98 prog_clk[0]:370 prog_clk[0]:369 0.00043005 +99 prog_clk[0]:368 prog_clk[0]:367 0.0045 +100 prog_clk[0]:369 prog_clk[0]:368 0.00341 +101 prog_clk[0]:367 prog_clk[0]:366 0.0001440218 +102 prog_clk[0]:366 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +103 prog_clk[0]:459 prog_clk[0]:458 0.002377232 +104 prog_clk[0]:460 prog_clk[0]:459 0.00341 +105 prog_clk[0]:238 prog_clk[0]:237 0.002073661 +106 prog_clk[0]:239 prog_clk[0]:238 0.00341 +107 prog_clk[0]:239 prog_clk[0]:221 0.001153067 +108 prog_clk[0]:404 prog_clk[0]:403 0.006587054 +109 prog_clk[0]:405 prog_clk[0]:404 0.00341 +110 prog_clk[0]:402 prog_clk[0]:401 0.0001059783 +111 prog_clk[0]:403 prog_clk[0]:402 0.0045 +112 prog_clk[0]:401 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +113 prog_clk[0]:220 prog_clk[0]:219 0.004805804 +114 prog_clk[0]:221 prog_clk[0]:220 0.00341 +115 prog_clk[0]:221 prog_clk[0]:179 0.0002870917 +116 prog_clk[0]:275 prog_clk[0]:274 0.0001847826 +117 prog_clk[0]:276 prog_clk[0]:275 0.0045 +118 prog_clk[0]:276 prog_clk[0]:273 0.004857143 +119 prog_clk[0]:274 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +120 prog_clk[0]:395 prog_clk[0]:394 0.00341 +121 prog_clk[0]:395 prog_clk[0]:365 0.004553571 +122 prog_clk[0]:394 prog_clk[0]:393 0.0007194917 +123 prog_clk[0]:232 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +124 prog_clk[0]:233 prog_clk[0]:232 0.0045 +125 prog_clk[0]:216 prog_clk[0]:215 0.00341 +126 prog_clk[0]:215 prog_clk[0]:214 0.0005753583 +127 prog_clk[0]:200 prog_clk[0]:199 0.00341 +128 prog_clk[0]:199 prog_clk[0]:198 0.0002870917 +129 prog_clk[0]:199 prog_clk[0]:193 0.0009368666 +130 prog_clk[0]:108 prog_clk[0]:107 0.003287947 +131 prog_clk[0]:109 prog_clk[0]:108 0.00341 +132 prog_clk[0]:109 prog_clk[0]:101 0.0007206667 +133 prog_clk[0]:300 prog_clk[0]:299 0.004502233 +134 prog_clk[0]:301 prog_clk[0]:300 0.00341 +135 prog_clk[0]:301 prog_clk[0]:251 0.0002882667 +136 prog_clk[0]:452 prog_clk[0]:451 0.00341 +137 prog_clk[0]:452 prog_clk[0]:425 0.002732143 +138 prog_clk[0]:451 prog_clk[0]:450 0.001584292 +139 prog_clk[0]:258 prog_clk[0]:257 0.006930804 +140 prog_clk[0]:259 prog_clk[0]:258 0.00341 +141 prog_clk[0]:100 prog_clk[0]:99 0.009359376 +142 prog_clk[0]:101 prog_clk[0]:100 0.00341 +143 prog_clk[0]:101 prog_clk[0]:86 0.0005753583 +144 prog_clk[0]:293 prog_clk[0]:292 0.00341 +145 prog_clk[0]:292 prog_clk[0]:291 0.0001417833 +146 prog_clk[0]:290 prog_clk[0]:289 0.002984375 +147 prog_clk[0]:291 prog_clk[0]:290 0.00341 +148 prog_clk[0]:373 prog_clk[0]:372 0.0001847826 +149 prog_clk[0]:374 prog_clk[0]:373 0.0045 +150 prog_clk[0]:374 prog_clk[0]:371 0.005109375 +151 prog_clk[0]:372 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +152 prog_clk[0]:352 prog_clk[0]:351 0.0001847826 +153 prog_clk[0]:353 prog_clk[0]:352 0.0045 +154 prog_clk[0]:353 prog_clk[0]:350 0.003035714 +155 prog_clk[0]:351 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +156 prog_clk[0]:348 prog_clk[0]:347 0.0001847826 +157 prog_clk[0]:349 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prog_clk[0]:377 prog_clk[0]:376 0.0003035715 +176 prog_clk[0]:378 prog_clk[0]:377 0.0045 +177 prog_clk[0]:378 prog_clk[0]:374 0.004857143 +178 prog_clk[0]:375 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +179 prog_clk[0]:384 prog_clk[0]:383 0.0005691964 +180 prog_clk[0]:385 prog_clk[0]:384 0.0045 +181 prog_clk[0]:385 prog_clk[0]:382 0.003591518 +182 prog_clk[0]:383 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +183 prog_clk[0]:355 prog_clk[0]:354 0.0001847826 +184 prog_clk[0]:356 prog_clk[0]:355 0.0045 +185 prog_clk[0]:356 prog_clk[0]:353 0.006678572 +186 prog_clk[0]:354 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +187 prog_clk[0]:358 prog_clk[0]:357 0.0005736607 +188 prog_clk[0]:357 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +189 prog_clk[0]:364 prog_clk[0]:363 0.0001847826 +190 prog_clk[0]:365 prog_clk[0]:364 0.0045 +191 prog_clk[0]:365 prog_clk[0]:362 0.005109374 +192 prog_clk[0]:363 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +193 prog_clk[0]:322 prog_clk[0]:321 0.0045 +194 prog_clk[0]:321 prog_clk[0]:320 0.002651786 +195 prog_clk[0]:319 prog_clk[0]:318 0.0001059783 +196 prog_clk[0]:320 prog_clk[0]:319 0.0045 +197 prog_clk[0]:318 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +198 prog_clk[0]:266 prog_clk[0]:265 0.0045 +199 prog_clk[0]:267 prog_clk[0]:266 0.00341 +200 prog_clk[0]:267 prog_clk[0]:263 0.001369267 +201 prog_clk[0]:265 prog_clk[0]:264 0.0001440218 +202 prog_clk[0]:264 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +203 prog_clk[0]:272 prog_clk[0]:271 0.0003035715 +204 prog_clk[0]:273 prog_clk[0]:272 0.0045 +205 prog_clk[0]:273 prog_clk[0]:269 0.004502232 +206 prog_clk[0]:270 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +207 prog_clk[0]:262 prog_clk[0]:261 0.0045 +208 prog_clk[0]:263 prog_clk[0]:262 0.00341 +209 prog_clk[0]:263 prog_clk[0]:259 0.0007194916 +210 prog_clk[0]:261 prog_clk[0]:260 0.0001440218 +211 prog_clk[0]:260 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +212 prog_clk[0]:256 prog_clk[0]:255 0.0001847826 +213 prog_clk[0]:257 prog_clk[0]:256 0.0045 +214 prog_clk[0]:257 prog_clk[0]:254 0.007549107 +215 prog_clk[0]:255 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +216 prog_clk[0]:253 prog_clk[0]:252 0.000984375 +217 prog_clk[0]:254 prog_clk[0]:253 0.0045 +218 prog_clk[0]:252 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +219 prog_clk[0]:133 prog_clk[0]:132 0.004765625 +220 prog_clk[0]:134 prog_clk[0]:133 0.00341 +221 prog_clk[0]:131 prog_clk[0]:130 0.0005736608 +222 prog_clk[0]:132 prog_clk[0]:131 0.0045 +223 prog_clk[0]:130 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +224 prog_clk[0]:188 prog_clk[0]:187 0.004765625 +225 prog_clk[0]:189 prog_clk[0]:188 0.00341 +226 prog_clk[0]:186 prog_clk[0]:185 0.0001440218 +227 prog_clk[0]:187 prog_clk[0]:186 0.0045 +228 prog_clk[0]:185 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +229 prog_clk[0]:128 prog_clk[0]:127 0.0001059783 +230 prog_clk[0]:129 prog_clk[0]:128 0.0045 +231 prog_clk[0]:127 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +232 prog_clk[0]:441 prog_clk[0]:440 0.007537947 +233 prog_clk[0]:442 prog_clk[0]:441 0.00341 +234 prog_clk[0]:315 prog_clk[0]:314 0.002944197 +235 prog_clk[0]:316 prog_clk[0]:315 0.00341 +236 prog_clk[0]:316 prog_clk[0]:311 0.002017867 +237 prog_clk[0]:313 prog_clk[0]:312 0.0001440218 +238 prog_clk[0]:314 prog_clk[0]:313 0.0045 +239 prog_clk[0]:312 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +240 prog_clk[0]:152 prog_clk[0]:151 0.0001847826 +241 prog_clk[0]:153 prog_clk[0]:152 0.0045 +242 prog_clk[0]:153 prog_clk[0]:150 0.005160714 +243 prog_clk[0]:151 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +244 prog_clk[0]:463 prog_clk[0]:462 0.0045 +245 prog_clk[0]:464 prog_clk[0]:463 0.00341 +246 prog_clk[0]:464 prog_clk[0]:460 0.000647425 +247 prog_clk[0]:462 prog_clk[0]:461 0.0001440218 +248 prog_clk[0]:461 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +249 prog_clk[0]:458 prog_clk[0]:457 0.00341 +250 prog_clk[0]:458 prog_clk[0]:452 0.004857143 +251 prog_clk[0]:457 prog_clk[0]:456 0.0007183166 +252 prog_clk[0]:455 prog_clk[0]:454 0.0045 +253 prog_clk[0]:456 prog_clk[0]:455 0.00341 +254 prog_clk[0]:454 prog_clk[0]:453 0.0001440218 +255 prog_clk[0]:453 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +256 prog_clk[0]:328 prog_clk[0]:327 0.001162947 +257 prog_clk[0]:329 prog_clk[0]:328 0.00341 +258 prog_clk[0]:305 prog_clk[0]:304 0.002944197 +259 prog_clk[0]:306 prog_clk[0]:305 0.00341 +260 prog_clk[0]:306 prog_clk[0]:301 0.0004324 +261 prog_clk[0]:303 prog_clk[0]:302 0.0001440218 +262 prog_clk[0]:304 prog_clk[0]:303 0.0045 +263 prog_clk[0]:302 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +264 prog_clk[0]:250 prog_clk[0]:249 0.005372768 +265 prog_clk[0]:251 prog_clk[0]:250 0.00341 +266 prog_clk[0]:251 prog_clk[0]:246 0.001369267 +267 prog_clk[0]:248 prog_clk[0]:247 0.0001059783 +268 prog_clk[0]:249 prog_clk[0]:248 0.0045 +269 prog_clk[0]:247 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +270 prog_clk[0]:435 prog_clk[0]:434 0.00341 +271 prog_clk[0]:435 prog_clk[0]:429 0.0004107143 +272 prog_clk[0]:434 prog_clk[0]:433 0.0007903833 +273 prog_clk[0]:432 prog_clk[0]:431 0.0045 +274 prog_clk[0]:433 prog_clk[0]:432 0.00341 +275 prog_clk[0]:431 prog_clk[0]:430 0.0005736608 +276 prog_clk[0]:430 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +277 prog_clk[0]:412 prog_clk[0]:411 0.0001059783 +278 prog_clk[0]:411 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +279 prog_clk[0]:170 prog_clk[0]:169 0.00341 +280 prog_clk[0]:170 prog_clk[0]:164 0.0004107143 +281 prog_clk[0]:169 prog_clk[0]:168 0.0002859166 +282 prog_clk[0]:167 prog_clk[0]:166 0.0045 +283 prog_clk[0]:168 prog_clk[0]:167 0.00341 +284 prog_clk[0]:166 prog_clk[0]:165 0.0005736608 +285 prog_clk[0]:165 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +286 prog_clk[0]:436 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +287 prog_clk[0]:438 prog_clk[0]:437 0.0003705357 +288 prog_clk[0]:439 prog_clk[0]:438 0.0045 +289 prog_clk[0]:424 prog_clk[0]:423 0.0003035715 +290 prog_clk[0]:425 prog_clk[0]:424 0.0045 +291 prog_clk[0]:425 prog_clk[0]:421 0.004553571 +292 prog_clk[0]:422 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +293 prog_clk[0]:126 prog_clk[0]:125 0.0001059783 +294 prog_clk[0]:125 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +295 prog_clk[0]:449 prog_clk[0]:448 0.0045 +296 prog_clk[0]:450 prog_clk[0]:449 0.00341 +297 prog_clk[0]:450 prog_clk[0]:446 0.001441333 +298 prog_clk[0]:448 prog_clk[0]:447 0.0001440218 +299 prog_clk[0]:447 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +300 prog_clk[0]:295 prog_clk[0]:294 0.0001847826 +301 prog_clk[0]:296 prog_clk[0]:295 0.0045 +302 prog_clk[0]:296 prog_clk[0]:293 0.00389509 +303 prog_clk[0]:294 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +304 prog_clk[0]:137 prog_clk[0]:136 0.0045 +305 prog_clk[0]:138 prog_clk[0]:137 0.00341 +306 prog_clk[0]:138 prog_clk[0]:134 0.0002870917 +307 prog_clk[0]:136 prog_clk[0]:135 0.0001059783 +308 prog_clk[0]:135 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +309 prog_clk[0]:174 prog_clk[0]:173 0.0001059783 +310 prog_clk[0]:175 prog_clk[0]:174 0.0045 +311 prog_clk[0]:173 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +312 prog_clk[0]:148 prog_clk[0]:147 0.0001440218 +313 prog_clk[0]:149 prog_clk[0]:148 0.0045 +314 prog_clk[0]:147 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +315 prog_clk[0]:310 prog_clk[0]:309 0.001729911 +316 prog_clk[0]:311 prog_clk[0]:310 0.00341 +317 prog_clk[0]:311 prog_clk[0]:306 0.0007206666 +318 prog_clk[0]:308 prog_clk[0]:307 0.0001059783 +319 prog_clk[0]:309 prog_clk[0]:308 0.0045 +320 prog_clk[0]:307 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +321 prog_clk[0]:236 prog_clk[0]:235 0.0001847826 +322 prog_clk[0]:237 prog_clk[0]:236 0.0045 +323 prog_clk[0]:237 prog_clk[0]:234 0.005160714 +324 prog_clk[0]:235 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +325 prog_clk[0]:192 prog_clk[0]:191 0.0045 +326 prog_clk[0]:193 prog_clk[0]:192 0.00341 +327 prog_clk[0]:193 prog_clk[0]:189 0.000431225 +328 prog_clk[0]:191 prog_clk[0]:190 0.0001440218 +329 prog_clk[0]:190 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +330 prog_clk[0]:445 prog_clk[0]:444 0.0045 +331 prog_clk[0]:446 prog_clk[0]:445 0.00341 +332 prog_clk[0]:446 prog_clk[0]:442 0.000431225 +333 prog_clk[0]:444 prog_clk[0]:443 0.0001059783 +334 prog_clk[0]:443 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +335 prog_clk[0]:178 prog_clk[0]:177 0.0045 +336 prog_clk[0]:179 prog_clk[0]:178 0.00341 +337 prog_clk[0]:177 prog_clk[0]:176 0.0005736608 +338 prog_clk[0]:176 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +339 prog_clk[0]:427 prog_clk[0]:426 0.0001059783 +340 prog_clk[0]:428 prog_clk[0]:427 0.0045 +341 prog_clk[0]:426 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +342 prog_clk[0]:197 prog_clk[0]:196 0.002337054 +343 prog_clk[0]:198 prog_clk[0]:197 0.00341 +344 prog_clk[0]:195 prog_clk[0]:194 0.0001059783 +345 prog_clk[0]:196 prog_clk[0]:195 0.0045 +346 prog_clk[0]:194 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +347 prog_clk[0]:218 prog_clk[0]:217 0.000125 +348 prog_clk[0]:219 prog_clk[0]:218 0.0045 +349 prog_clk[0]:219 prog_clk[0]:216 0.002984375 +350 prog_clk[0]:217 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +351 prog_clk[0]:95 prog_clk[0]:94 0.0001847826 +352 prog_clk[0]:96 prog_clk[0]:95 0.0045 +353 prog_clk[0]:96 prog_clk[0]:93 0.00178125 +354 prog_clk[0]:94 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +355 prog_clk[0]:392 prog_clk[0]:391 0.0045 +356 prog_clk[0]:393 prog_clk[0]:392 0.00341 +357 prog_clk[0]:393 prog_clk[0]:389 0.001223958 +358 prog_clk[0]:391 prog_clk[0]:390 0.0001059783 +359 prog_clk[0]:390 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +360 prog_clk[0]:87 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +361 prog_clk[0]:92 prog_clk[0]:91 0.0003035715 +362 prog_clk[0]:93 prog_clk[0]:92 0.0045 +363 prog_clk[0]:298 prog_clk[0]:297 0.0001847826 +364 prog_clk[0]:299 prog_clk[0]:298 0.0045 +365 prog_clk[0]:299 prog_clk[0]:296 0.009714287 +366 prog_clk[0]:297 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +367 prog_clk[0]:123 prog_clk[0]:122 0.004158482 +368 prog_clk[0]:124 prog_clk[0]:123 0.00341 +369 prog_clk[0]:124 prog_clk[0]:119 0.0007927332 +370 prog_clk[0]:121 prog_clk[0]:120 0.0001059783 +371 prog_clk[0]:122 prog_clk[0]:121 0.0045 +372 prog_clk[0]:120 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +373 prog_clk[0]:106 prog_clk[0]:105 0.0001847826 +374 prog_clk[0]:107 prog_clk[0]:106 0.0045 +375 prog_clk[0]:107 prog_clk[0]:104 0.004513393 +376 prog_clk[0]:105 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +377 prog_clk[0]:243 prog_clk[0]:242 0.0001847826 +378 prog_clk[0]:244 prog_clk[0]:243 0.0045 +379 prog_clk[0]:244 prog_clk[0]:241 0.007537947 +380 prog_clk[0]:242 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +381 prog_clk[0]:83 prog_clk[0]:82 0.0005736608 +382 prog_clk[0]:84 prog_clk[0]:83 0.0045 +383 prog_clk[0]:82 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +384 prog_clk[0]:80 prog_clk[0]:79 0.0001440217 +385 prog_clk[0]:81 prog_clk[0]:80 0.0045 +386 prog_clk[0]:79 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +387 prog_clk[0]:118 prog_clk[0]:117 0.000515625 +388 prog_clk[0]:119 prog_clk[0]:118 0.00341 +389 prog_clk[0]:119 prog_clk[0]:114 0.0007206667 +390 prog_clk[0]:116 prog_clk[0]:115 0.0001440218 +391 prog_clk[0]:117 prog_clk[0]:116 0.0045 +392 prog_clk[0]:115 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +393 prog_clk[0]:145 prog_clk[0]:144 0.0045 +394 prog_clk[0]:146 prog_clk[0]:145 0.00341 +395 prog_clk[0]:146 prog_clk[0]:142 0.000431225 +396 prog_clk[0]:144 prog_clk[0]:143 0.0001440218 +397 prog_clk[0]:143 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +398 prog_clk[0]:409 prog_clk[0]:408 0.0001059783 +399 prog_clk[0]:410 prog_clk[0]:409 0.0045 +400 prog_clk[0]:408 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +401 prog_clk[0]:103 prog_clk[0]:102 0.0001440218 +402 prog_clk[0]:104 prog_clk[0]:103 0.0045 +403 prog_clk[0]:102 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +404 prog_clk[0]:472 prog_clk[0]:471 0.001729911 +405 prog_clk[0]:473 prog_clk[0]:472 0.00341 +406 prog_clk[0]:473 prog_clk[0]:468 0.0005044666 +407 prog_clk[0]:470 prog_clk[0]:469 0.0001059783 +408 prog_clk[0]:471 prog_clk[0]:470 0.0045 +409 prog_clk[0]:469 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +410 prog_clk[0]:113 prog_clk[0]:112 0.004158482 +411 prog_clk[0]:114 prog_clk[0]:113 0.00341 +412 prog_clk[0]:114 prog_clk[0]:109 0.0005765333 +413 prog_clk[0]:111 prog_clk[0]:110 0.0001059783 +414 prog_clk[0]:112 prog_clk[0]:111 0.0045 +415 prog_clk[0]:110 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +416 prog_clk[0]:397 prog_clk[0]:396 0.0001059783 +417 prog_clk[0]:398 prog_clk[0]:397 0.0045 +418 prog_clk[0]:396 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +419 prog_clk[0]:98 prog_clk[0]:97 0.0001847826 +420 prog_clk[0]:99 prog_clk[0]:98 0.0045 +421 prog_clk[0]:99 prog_clk[0]:96 0.004857143 +422 prog_clk[0]:97 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +423 prog_clk[0]:231 prog_clk[0]:230 0.00341 +424 prog_clk[0]:231 prog_clk[0]:225 0.0004107143 +425 prog_clk[0]:230 prog_clk[0]:229 0.0002859166 +426 prog_clk[0]:228 prog_clk[0]:227 0.0045 +427 prog_clk[0]:229 prog_clk[0]:228 0.00341 +428 prog_clk[0]:227 prog_clk[0]:226 0.0005736608 +429 prog_clk[0]:226 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +430 prog_clk[0]:223 prog_clk[0]:222 0.0001059783 +431 prog_clk[0]:224 prog_clk[0]:223 0.0045 +432 prog_clk[0]:222 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +433 prog_clk[0]:282 prog_clk[0]:281 0.00341 +434 prog_clk[0]:282 prog_clk[0]:276 0.005109375 +435 prog_clk[0]:281 prog_clk[0]:280 0.0002859167 +436 prog_clk[0]:279 prog_clk[0]:278 0.0045 +437 prog_clk[0]:280 prog_clk[0]:279 0.00341 +438 prog_clk[0]:278 prog_clk[0]:277 0.0001059783 +439 prog_clk[0]:277 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +440 prog_clk[0]:317 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +441 prog_clk[0]:213 prog_clk[0]:212 0.004158482 +442 prog_clk[0]:214 prog_clk[0]:213 0.00341 +443 prog_clk[0]:214 prog_clk[0]:209 0.0008647999 +444 prog_clk[0]:211 prog_clk[0]:210 0.0001440218 +445 prog_clk[0]:212 prog_clk[0]:211 0.0045 +446 prog_clk[0]:210 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +447 prog_clk[0]:423 prog_clk[0]:422 0.001024554 +448 prog_clk[0]:376 prog_clk[0]:375 0.0006138393 +449 prog_clk[0]:285 prog_clk[0]:284 0.001024554 +450 prog_clk[0]:271 prog_clk[0]:270 0.001024554 +451 prog_clk[0]:437 prog_clk[0]:436 0.0003035715 +452 prog_clk[0]:91 prog_clk[0]:90 0.004928572 +453 prog_clk[0]:90 prog_clk[0]:89 0.0006071429 +454 prog_clk[0]:89 prog_clk[0]:88 0.001642857 +455 prog_clk[0]:88 prog_clk[0]:87 0.0006071429 +456 prog_clk[0]:350 prog_clk[0]:349 0.0004107143 +457 prog_clk[0]:417 prog_clk[0]:416 0.0004107143 +458 prog_clk[0]:416 prog_clk[0]:415 0.005120536 +459 prog_clk[0]:289 prog_clk[0]:288 0.0003705357 +460 prog_clk[0]:288 prog_clk[0]:287 0.00019375 +461 prog_clk[0]:288 prog_clk[0]:283 0.007285715 +462 prog_clk[0]:283 prog_clk[0]:282 0.0004107143 +463 prog_clk[0]:429 prog_clk[0]:428 0.004816964 +464 prog_clk[0]:440 prog_clk[0]:439 0.0004107143 +465 prog_clk[0]:440 prog_clk[0]:435 0.006930804 +466 prog_clk[0]:164 prog_clk[0]:163 0.004857143 +467 prog_clk[0]:234 prog_clk[0]:233 0.001232143 +468 prog_clk[0]:234 prog_clk[0]:231 0.004805804 +469 prog_clk[0]:225 prog_clk[0]:224 0.002388393 +470 prog_clk[0]:150 prog_clk[0]:149 0.0004107143 +471 prog_clk[0]:207 prog_clk[0]:206 0.0004107143 +472 prog_clk[0]:184 prog_clk[0]:183 0.0007194916 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.009979725 //LENGTH 73.640 LUMPCC 0.002287107 DR + +*CONN +*I mux_right_track_24\/mux_l3_in_0_:X O *L 0 *C 35.245 42.160 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.250 42.330 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 103.213 42.223 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 100.325 42.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 100.280 42.115 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 100.280 40.178 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 100.273 40.120 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 92.615 40.120 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 42.788 40.120 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 42.780 40.178 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 42.780 42.115 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 42.735 42.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 35.282 42.160 + +*CAP +0 mux_right_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000181553 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000181553 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000117271 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000117271 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003396824 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002990816 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.002651133 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001265095 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001265095 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0004291588 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0004291588 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[11]:13 0.000290319 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[11] 5.413433e-05 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[11] 0.000290319 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[11]:13 5.413433e-05 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_6_sram[0]:16 0.000149908 +18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_6_sram[0]:24 0.0001260952 +19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_6_sram[0]:13 4.295116e-06 +20 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_6_sram[0]:14 2.687958e-07 +21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_6_sram[0]:15 2.638262e-05 +22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_6_sram[0]:10 2.687958e-07 +23 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_6_sram[0]:14 4.295116e-06 +24 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_6_sram[0]:15 0.000149908 +25 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_6_sram[0]:16 2.638262e-05 +26 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_6_sram[0]:25 0.0001260952 +27 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_6_sram[2]:8 1.79667e-05 +28 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_6_sram[2]:11 2.103366e-08 +29 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_6_sram[2]:9 0.0002806575 +30 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_6_sram[2]:10 2.103366e-08 +31 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_6_sram[2]:8 0.0002806575 +32 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_6_sram[2]:9 1.79667e-05 +33 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 optlc_net_185:25 0.0001935053 +34 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 optlc_net_185:26 0.0001935053 + +*RES +0 mux_right_track_24\/mux_l3_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.006654018 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001729911 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.007806308 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001729911 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002578125 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001199675 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009781944 //LENGTH 7.980 LUMPCC 0.000120176 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_2_:X O *L 0 *C 65.955 113.560 +*I mux_right_track_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 63.020 117.980 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.020 117.980 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 63.020 117.935 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 63.020 113.605 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 63.065 113.560 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 65.918 113.560 + +*CAP +0 mux_right_track_6\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.336994e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002012444 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002012444 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002100798 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002100798 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[1]:8 6.008799e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[1] 6.008799e-05 + +*RES +0 mux_right_track_6\/mux_l1_in_2_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002546875 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.003866072 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_6\/mux_l2_in_1_:A1 0.152 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003551808 //LENGTH 26.710 LUMPCC 0.0008105811 DR + +*CONN +*I mux_right_track_18\/mux_l2_in_0_:X O *L 0 *C 82.625 72.080 +*I mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.760 66.510 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 102.723 66.597 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.505 66.640 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.460 66.685 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.460 71.695 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.415 71.740 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 85.560 71.740 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 85.560 72.080 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 82.663 72.080 + +*CAP +0 mux_right_track_18\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004849844 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004849844 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002728206 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002728206 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003592894 +7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003835967 +8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002525194 +9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.000228212 +10 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:9 3.518184e-06 +11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:11 8.053773e-06 +12 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:12 5.900682e-06 +13 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0001872771 +14 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:6 5.900682e-06 +15 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:11 3.518184e-06 +16 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_0_sram[1]:12 8.053773e-06 +17 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size6_0_sram[1]:4 0.0001872771 +18 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001481806 +19 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001481806 +20 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.236022e-05 +21 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.236022e-05 + +*RES +0 mux_right_track_18\/mux_l2_in_0_:X mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_18\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.009122768 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004473215 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002587053 +7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003035715 +8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.006120536 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001682346 //LENGTH 14.040 LUMPCC 0.0006910905 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_0_:X O *L 0 *C 39.275 36.040 +*I mux_bottom_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 36.705 25.500 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 36.742 25.500 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 38.135 25.500 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 38.180 25.545 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 38.180 35.995 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 38.225 36.040 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 39.238 36.040 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.718886e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.718886e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003599349 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003599349 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.750403e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.750403e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[0]:8 7.113769e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_4_sram[0]:10 1.767771e-05 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_4_sram[0]:9 7.113769e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_4_sram[0]:11 1.767771e-05 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_4_sram[1]:7 6.661633e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[1]:8 6.661633e-05 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[1]:5 7.274788e-06 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[1]:9 9.715597e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_4_sram[1]:9 7.274788e-06 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_4_sram[1]:10 9.715597e-05 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.79992e-07 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.79992e-07 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.500282e-05 +21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.500282e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001243304 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.009330357 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET chany_top_out[9] 0.001248077 //LENGTH 9.895 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_822:X O *L 0 *C 12.880 125.800 +*P chany_top_out[9] O *L 0.7423 *C 9.200 129.350 +*N chany_top_out[9]:2 *C 9.200 125.808 +*N chany_top_out[9]:3 *C 9.220 125.800 +*N chany_top_out[9]:4 *C 13.793 125.800 +*N chany_top_out[9]:5 *C 13.800 125.800 +*N chany_top_out[9]:6 *C 13.755 125.800 +*N chany_top_out[9]:7 *C 12.918 125.800 + +*CAP +0 ropt_mt_inst_822:X 1e-06 +1 chany_top_out[9] 0.0002129118 +2 chany_top_out[9]:2 0.0002129118 +3 chany_top_out[9]:3 0.0003239625 +4 chany_top_out[9]:4 0.0003239625 +5 chany_top_out[9]:5 2.760382e-05 +6 chany_top_out[9]:6 7.286207e-05 +7 chany_top_out[9]:7 7.286207e-05 + +*RES +0 ropt_mt_inst_822:X chany_top_out[9]:7 0.152 +1 chany_top_out[9]:7 chany_top_out[9]:6 0.0007477679 +2 chany_top_out[9]:6 chany_top_out[9]:5 0.0045 +3 chany_top_out[9]:5 chany_top_out[9]:4 0.00341 +4 chany_top_out[9]:4 chany_top_out[9]:3 0.0007163583 +5 chany_top_out[9]:3 chany_top_out[9]:2 0.00341 +6 chany_top_out[9]:2 chany_top_out[9] 0.0005549917 + +*END + +*D_NET ropt_net_234 0.0001577138 //LENGTH 1.015 LUMPCC 5.992123e-05 DR + +*CONN +*I ropt_mt_inst_830:X O *L 0 *C 46.655 123.760 +*I ropt_mt_inst_854:A I *L 0.001767 *C 47.380 123.760 +*N ropt_net_234:2 *C 47.343 123.760 +*N ropt_net_234:3 *C 46.693 123.760 + +*CAP +0 ropt_mt_inst_830:X 1e-06 +1 ropt_mt_inst_854:A 1e-06 +2 ropt_net_234:2 4.789629e-05 +3 ropt_net_234:3 4.789629e-05 +4 ropt_net_234:2 chany_top_in[3]:2 2.996061e-05 +5 ropt_net_234:3 chany_top_in[3]:3 2.996061e-05 + +*RES +0 ropt_mt_inst_830:X ropt_net_234:3 0.152 +1 ropt_net_234:2 ropt_mt_inst_854:A 0.152 +2 ropt_net_234:3 ropt_net_234:2 0.0005803572 + +*END + +*D_NET chany_bottom_out[4] 0.002233193 //LENGTH 16.985 LUMPCC 0.0002012548 DR + +*CONN +*I ropt_mt_inst_840:X O *L 0 *C 58.615 9.860 +*P chany_bottom_out[4] O *L 0.7423 *C 51.060 1.325 +*N chany_bottom_out[4]:2 *C 51.060 1.995 +*N chany_bottom_out[4]:3 *C 51.105 2.040 +*N chany_bottom_out[4]:4 *C 58.375 2.040 +*N chany_bottom_out[4]:5 *C 58.420 2.085 +*N chany_bottom_out[4]:6 *C 58.420 9.815 +*N chany_bottom_out[4]:7 *C 58.420 9.860 +*N chany_bottom_out[4]:8 *C 58.615 9.860 + +*CAP +0 ropt_mt_inst_840:X 1e-06 +1 chany_bottom_out[4] 5.430768e-05 +2 chany_bottom_out[4]:2 5.430768e-05 +3 chany_bottom_out[4]:3 0.0005602057 +4 chany_bottom_out[4]:4 0.0005602057 +5 chany_bottom_out[4]:5 0.0003476187 +6 chany_bottom_out[4]:6 0.0003476187 +7 chany_bottom_out[4]:7 5.271177e-05 +8 chany_bottom_out[4]:8 5.396231e-05 +9 chany_bottom_out[4]:6 ropt_net_227:4 0.0001006274 +10 chany_bottom_out[4]:5 ropt_net_227:5 0.0001006274 + +*RES +0 ropt_mt_inst_840:X chany_bottom_out[4]:8 0.152 +1 chany_bottom_out[4]:8 chany_bottom_out[4]:7 0.0001059783 +2 chany_bottom_out[4]:7 chany_bottom_out[4]:6 0.0045 +3 chany_bottom_out[4]:6 chany_bottom_out[4]:5 0.006901786 +4 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.006491072 +5 chany_bottom_out[4]:5 chany_bottom_out[4]:4 0.0045 +6 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +7 chany_bottom_out[4]:2 chany_bottom_out[4] 0.0005982143 + +*END + +*D_NET chany_top_out[4] 0.0003528959 //LENGTH 3.035 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_848:X O *L 0 *C 36.800 127.160 +*P chany_top_out[4] O *L 0.7423 *C 36.340 129.540 +*N chany_top_out[4]:2 *C 36.340 127.205 +*N chany_top_out[4]:3 *C 36.385 127.160 +*N chany_top_out[4]:4 *C 36.763 127.160 + +*CAP +0 ropt_mt_inst_848:X 1e-06 +1 chany_top_out[4] 0.0001286241 +2 chany_top_out[4]:2 0.0001286241 +3 chany_top_out[4]:3 4.732387e-05 +4 chany_top_out[4]:4 4.732387e-05 + +*RES +0 ropt_mt_inst_848:X chany_top_out[4]:4 0.152 +1 chany_top_out[4]:4 chany_top_out[4]:3 0.0003370536 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0045 +3 chany_top_out[4]:2 chany_top_out[4] 0.00184375 + +*END + +*D_NET chanx_right_out[15] 0.001051616 //LENGTH 8.260 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_855:X O *L 0 *C 107.180 68.680 +*P chanx_right_out[15] O *L 0.7423 *C 111.863 68.000 +*N chanx_right_out[15]:2 *C 111.780 68.000 +*N chanx_right_out[15]:3 *C 111.780 68.058 +*N chanx_right_out[15]:4 *C 111.780 69.315 +*N chanx_right_out[15]:5 *C 111.735 69.360 +*N chanx_right_out[15]:6 *C 108.145 69.360 +*N chanx_right_out[15]:7 *C 108.100 69.315 +*N chanx_right_out[15]:8 *C 108.100 68.725 +*N chanx_right_out[15]:9 *C 108.055 68.680 +*N chanx_right_out[15]:10 *C 107.218 68.680 + +*CAP +0 ropt_mt_inst_855:X 1e-06 +1 chanx_right_out[15] 3.072782e-05 +2 chanx_right_out[15]:2 3.072782e-05 +3 chanx_right_out[15]:3 0.0001059606 +4 chanx_right_out[15]:4 0.0001059606 +5 chanx_right_out[15]:5 0.0002508139 +6 chanx_right_out[15]:6 0.0002508139 +7 chanx_right_out[15]:7 5.402918e-05 +8 chanx_right_out[15]:8 5.402918e-05 +9 chanx_right_out[15]:9 8.377643e-05 +10 chanx_right_out[15]:10 8.377643e-05 + +*RES +0 ropt_mt_inst_855:X chanx_right_out[15]:10 0.152 +1 chanx_right_out[15]:10 chanx_right_out[15]:9 0.0007477679 +2 chanx_right_out[15]:9 chanx_right_out[15]:8 0.0045 +3 chanx_right_out[15]:8 chanx_right_out[15]:7 0.0005267858 +4 chanx_right_out[15]:6 chanx_right_out[15]:5 0.003205357 +5 chanx_right_out[15]:7 chanx_right_out[15]:6 0.0045 +6 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +7 chanx_right_out[15]:4 chanx_right_out[15]:3 0.001122768 +8 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +9 chanx_right_out[15]:2 chanx_right_out[15] 2.35e-05 + +*END + +*D_NET ropt_net_211 0.001719627 //LENGTH 16.450 LUMPCC 0.0002091166 DR + +*CONN +*I BUFT_RR_85:X O *L 0 *C 108.100 57.800 +*I ropt_mt_inst_832:A I *L 0.001766 *C 106.260 63.920 +*N ropt_net_211:2 *C 106.297 63.920 +*N ropt_net_211:3 *C 108.055 63.920 +*N ropt_net_211:4 *C 108.100 63.965 +*N ropt_net_211:5 *C 108.100 66.640 +*N ropt_net_211:6 *C 109.020 66.640 +*N ropt_net_211:7 *C 109.020 57.845 +*N ropt_net_211:8 *C 108.975 57.800 +*N ropt_net_211:9 *C 108.138 57.800 + +*CAP +0 BUFT_RR_85:X 1e-06 +1 ropt_mt_inst_832:A 1e-06 +2 ropt_net_211:2 0.0001390062 +3 ropt_net_211:3 0.0001390062 +4 ropt_net_211:4 9.754747e-05 +5 ropt_net_211:5 0.0001201217 +6 ropt_net_211:6 0.0004410728 +7 ropt_net_211:7 0.0004184986 +8 ropt_net_211:8 7.66285e-05 +9 ropt_net_211:9 7.66285e-05 +10 ropt_net_211:7 chanx_right_in[1]:11 2.670232e-05 +11 ropt_net_211:4 chanx_right_in[1]:11 3.095422e-05 +12 ropt_net_211:5 chanx_right_in[1]:12 3.095422e-05 +13 ropt_net_211:6 chanx_right_in[1]:12 2.670232e-05 +14 ropt_net_211:7 ropt_net_233:5 1.664172e-05 +15 ropt_net_211:4 ropt_net_233:5 9.705707e-07 +16 ropt_net_211:5 ropt_net_233:2 2.928947e-05 +17 ropt_net_211:5 ropt_net_233:4 9.705707e-07 +18 ropt_net_211:6 ropt_net_233:3 2.928947e-05 +19 ropt_net_211:6 ropt_net_233:4 1.664172e-05 + +*RES +0 BUFT_RR_85:X ropt_net_211:9 0.152 +1 ropt_net_211:9 ropt_net_211:8 0.0007477679 +2 ropt_net_211:8 ropt_net_211:7 0.0045 +3 ropt_net_211:7 ropt_net_211:6 0.007852679 +4 ropt_net_211:3 ropt_net_211:2 0.001569196 +5 ropt_net_211:4 ropt_net_211:3 0.0045 +6 ropt_net_211:2 ropt_mt_inst_832:A 0.152 +7 ropt_net_211:5 ropt_net_211:4 0.002388393 +8 ropt_net_211:6 ropt_net_211:5 0.0008214285 + +*END + +*D_NET ropt_net_217 0.001400037 //LENGTH 10.130 LUMPCC 0.0002946394 DR + +*CONN +*I BUFT_P_161:X O *L 0 *C 39.560 123.080 +*I ropt_mt_inst_838:A I *L 0.001766 *C 45.080 126.480 +*N ropt_net_217:2 *C 45.043 126.480 +*N ropt_net_217:3 *C 44.205 126.480 +*N ropt_net_217:4 *C 44.160 126.435 +*N ropt_net_217:5 *C 44.160 124.440 +*N ropt_net_217:6 *C 43.700 124.440 +*N ropt_net_217:7 *C 43.700 123.125 +*N ropt_net_217:8 *C 43.655 123.080 +*N ropt_net_217:9 *C 39.598 123.080 + +*CAP +0 BUFT_P_161:X 1e-06 +1 ropt_mt_inst_838:A 1e-06 +2 ropt_net_217:2 5.099384e-05 +3 ropt_net_217:3 5.099384e-05 +4 ropt_net_217:4 0.0001331886 +5 ropt_net_217:5 0.0001594765 +6 ropt_net_217:6 0.0001144253 +7 ropt_net_217:7 8.813739e-05 +8 ropt_net_217:8 0.0002530909 +9 ropt_net_217:9 0.0002530909 +10 ropt_net_217:2 chany_top_in[4]:26 4.422649e-05 +11 ropt_net_217:3 chany_top_in[4]:27 4.422649e-05 +12 ropt_net_217:4 chany_top_in[4] 1.822503e-05 +13 ropt_net_217:6 chany_top_in[4]:27 6.346746e-06 +14 ropt_net_217:5 chany_top_in[4]:26 6.346746e-06 +15 ropt_net_217:5 chany_top_in[4]:28 1.822503e-05 +16 ropt_net_217:8 chany_bottom_in[4]:7 7.564198e-05 +17 ropt_net_217:7 chany_bottom_in[4]:9 2.879452e-06 +18 ropt_net_217:9 chany_bottom_in[4]:6 7.564198e-05 +19 ropt_net_217:6 chany_bottom_in[4]:8 2.879452e-06 + +*RES +0 BUFT_P_161:X ropt_net_217:9 0.152 +1 ropt_net_217:2 ropt_mt_inst_838:A 0.152 +2 ropt_net_217:3 ropt_net_217:2 0.0007477679 +3 ropt_net_217:4 ropt_net_217:3 0.0045 +4 ropt_net_217:8 ropt_net_217:7 0.0045 +5 ropt_net_217:7 ropt_net_217:6 0.001174107 +6 ropt_net_217:9 ropt_net_217:8 0.003622768 +7 ropt_net_217:6 ropt_net_217:5 0.0004107143 +8 ropt_net_217:5 ropt_net_217:4 0.00178125 + +*END + +*D_NET chany_top_in[9] 0.0160486 //LENGTH 143.985 LUMPCC 0.0009531331 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 51.980 129.270 +*I mux_right_track_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.040 99.620 +*I BUFT_RR_79:A I *L 0.001776 *C 40.940 17.680 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.840 47.260 +*N chany_top_in[9]:4 *C 54.840 47.260 +*N chany_top_in[9]:5 *C 54.740 46.920 +*N chany_top_in[9]:6 *C 40.977 17.680 +*N chany_top_in[9]:7 *C 41.815 17.680 +*N chany_top_in[9]:8 *C 41.860 17.725 +*N chany_top_in[9]:9 *C 41.860 20.015 +*N chany_top_in[9]:10 *C 41.905 20.060 +*N chany_top_in[9]:11 *C 52.855 20.060 +*N chany_top_in[9]:12 *C 52.900 20.105 +*N chany_top_in[9]:13 *C 52.900 46.875 +*N chany_top_in[9]:14 *C 52.900 46.920 +*N chany_top_in[9]:15 *C 51.565 46.920 +*N chany_top_in[9]:16 *C 51.520 46.965 +*N chany_top_in[9]:17 *C 41.078 99.620 +*N chany_top_in[9]:18 *C 44.575 99.620 +*N chany_top_in[9]:19 *C 44.620 99.575 +*N chany_top_in[9]:20 *C 44.620 96.945 +*N chany_top_in[9]:21 *C 44.665 96.900 +*N chany_top_in[9]:22 *C 51.475 96.900 +*N chany_top_in[9]:23 *C 51.520 96.900 +*N chany_top_in[9]:24 *C 51.980 96.900 + +*CAP +0 chany_top_in[9] 0.001425645 +1 mux_right_track_10\/mux_l1_in_0_:A1 1e-06 +2 BUFT_RR_79:A 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +4 chany_top_in[9]:4 5.58524e-05 +5 chany_top_in[9]:5 0.0001565383 +6 chany_top_in[9]:6 8.329866e-05 +7 chany_top_in[9]:7 8.329866e-05 +8 chany_top_in[9]:8 0.0001445674 +9 chany_top_in[9]:9 0.0001445674 +10 chany_top_in[9]:10 0.0006234696 +11 chany_top_in[9]:11 0.0006234696 +12 chany_top_in[9]:12 0.001503202 +13 chany_top_in[9]:13 0.001503202 +14 chany_top_in[9]:14 0.0002637306 +15 chany_top_in[9]:15 0.000100169 +16 chany_top_in[9]:16 0.002623506 +17 chany_top_in[9]:17 0.000255301 +18 chany_top_in[9]:18 0.000255301 +19 chany_top_in[9]:19 0.0001645841 +20 chany_top_in[9]:20 0.0001645841 +21 chany_top_in[9]:21 0.0004011746 +22 chany_top_in[9]:22 0.0004011746 +23 chany_top_in[9]:23 0.002656848 +24 chany_top_in[9]:24 0.001458987 +25 chany_top_in[9] chany_bottom_in[10]:6 0.0003013248 +26 chany_top_in[9]:16 chany_bottom_in[10]:17 2.025476e-06 +27 chany_top_in[9]:16 chany_bottom_in[10]:22 2.410339e-05 +28 chany_top_in[9]:16 chany_bottom_in[10]:10 4.94709e-05 +29 chany_top_in[9]:16 chany_bottom_in[10]:16 3.613633e-05 +30 chany_top_in[9]:16 chany_bottom_in[10]:21 2.400878e-05 +31 chany_top_in[9]:23 chany_bottom_in[10]:20 2.400878e-05 +32 chany_top_in[9]:23 chany_bottom_in[10]:13 3.613633e-05 +33 chany_top_in[9]:23 chany_bottom_in[10]:16 2.025476e-06 +34 chany_top_in[9]:23 chany_bottom_in[10]:9 7.788334e-07 +35 chany_top_in[9]:23 chany_bottom_in[10]:6 4.869207e-05 +36 chany_top_in[9]:23 chany_bottom_in[10]:21 2.410339e-05 +37 chany_top_in[9]:24 chany_bottom_in[10]:10 0.0003013248 +38 chany_top_in[9] mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 3.949695e-05 +39 chany_top_in[9]:24 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 3.949695e-05 + +*RES +0 chany_top_in[9] chany_top_in[9]:24 0.02890179 +1 chany_top_in[9]:15 chany_top_in[9]:14 0.001191964 +2 chany_top_in[9]:16 chany_top_in[9]:15 0.0045 +3 chany_top_in[9]:14 chany_top_in[9]:13 0.0045 +4 chany_top_in[9]:14 chany_top_in[9]:5 0.001642857 +5 chany_top_in[9]:13 chany_top_in[9]:12 0.02390179 +6 chany_top_in[9]:11 chany_top_in[9]:10 0.009776786 +7 chany_top_in[9]:12 chany_top_in[9]:11 0.0045 +8 chany_top_in[9]:10 chany_top_in[9]:9 0.0045 +9 chany_top_in[9]:9 chany_top_in[9]:8 0.002044643 +10 chany_top_in[9]:7 chany_top_in[9]:6 0.000747768 +11 chany_top_in[9]:8 chany_top_in[9]:7 0.0045 +12 chany_top_in[9]:6 BUFT_RR_79:A 0.152 +13 chany_top_in[9]:22 chany_top_in[9]:21 0.006080357 +14 chany_top_in[9]:23 chany_top_in[9]:22 0.0045 +15 chany_top_in[9]:23 chany_top_in[9]:16 0.04458483 +16 chany_top_in[9]:21 chany_top_in[9]:20 0.0045 +17 chany_top_in[9]:20 chany_top_in[9]:19 0.002348214 +18 chany_top_in[9]:18 chany_top_in[9]:17 0.003122768 +19 chany_top_in[9]:19 chany_top_in[9]:18 0.0045 +20 chany_top_in[9]:17 mux_right_track_10\/mux_l1_in_0_:A1 0.152 +21 chany_top_in[9]:4 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +22 chany_top_in[9]:5 chany_top_in[9]:4 0.0003035715 +23 chany_top_in[9]:24 chany_top_in[9]:23 0.0004107143 + +*END + +*D_NET chanx_right_in[14] 0.01620435 //LENGTH 110.570 LUMPCC 0.005421236 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 111.930 91.120 +*I mux_bottom_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 63.020 45.220 +*I mux_top_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 55.845 80.920 +*N chanx_right_in[14]:3 *C 55.883 80.920 +*N chanx_right_in[14]:4 *C 58.375 80.920 +*N chanx_right_in[14]:5 *C 58.420 80.875 +*N chanx_right_in[14]:6 *C 62.998 45.193 +*N chanx_right_in[14]:7 *C 62.985 44.880 +*N chanx_right_in[14]:8 *C 58.465 44.880 +*N chanx_right_in[14]:9 *C 58.420 44.925 +*N chanx_right_in[14]:10 *C 58.420 79.560 +*N chanx_right_in[14]:11 *C 58.428 79.560 +*N chanx_right_in[14]:12 *C 109.460 79.560 +*N chanx_right_in[14]:13 *C 109.480 79.568 +*N chanx_right_in[14]:14 *C 109.480 91.113 +*N chanx_right_in[14]:15 *C 109.500 91.120 + +*CAP +0 chanx_right_in[14] 0.0001593206 +1 mux_bottom_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_32\/mux_l2_in_0_:A0 1e-06 +3 chanx_right_in[14]:3 0.0002165627 +4 chanx_right_in[14]:4 0.0002165627 +5 chanx_right_in[14]:5 9.013707e-05 +6 chanx_right_in[14]:6 3.117027e-05 +7 chanx_right_in[14]:7 0.000249872 +8 chanx_right_in[14]:8 0.0002187017 +9 chanx_right_in[14]:9 0.001628412 +10 chanx_right_in[14]:10 0.001757083 +11 chanx_right_in[14]:11 0.002358321 +12 chanx_right_in[14]:12 0.002358321 +13 chanx_right_in[14]:13 0.0006686646 +14 chanx_right_in[14]:14 0.0006686646 +15 chanx_right_in[14]:15 0.0001593206 +16 chanx_right_in[14]:11 chany_top_in[13]:34 0.000817471 +17 chanx_right_in[14]:11 chany_top_in[13]:35 0.0006230451 +18 chanx_right_in[14]:12 chany_top_in[13]:33 0.000817471 +19 chanx_right_in[14]:12 chany_top_in[13]:34 0.0006230451 +20 chanx_right_in[14]:11 chany_bottom_in[12]:40 0.0002779562 +21 chanx_right_in[14]:12 chany_bottom_in[12]:39 0.0002779562 +22 chanx_right_in[14]:11 chanx_right_out[4]:2 0.0004990408 +23 chanx_right_in[14]:12 chanx_right_out[4] 0.0004990408 +24 chanx_right_in[14]:10 mux_tree_tapbuf_size3_3_sram[1]:4 4.14426e-05 +25 chanx_right_in[14]:10 mux_tree_tapbuf_size3_3_sram[1]:8 6.432418e-05 +26 chanx_right_in[14]:9 mux_tree_tapbuf_size3_3_sram[1]:7 6.432418e-05 +27 chanx_right_in[14]:9 mux_tree_tapbuf_size3_3_sram[1]:8 4.14426e-05 +28 chanx_right_in[14]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.032053e-05 +29 chanx_right_in[14]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.032053e-05 +30 chanx_right_in[14]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001220508 +31 chanx_right_in[14]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001220508 +32 chanx_right_in[14]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.518803e-05 +33 chanx_right_in[14]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.518803e-05 +34 chanx_right_in[14]:11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001541656 +35 chanx_right_in[14]:11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.61312e-06 +36 chanx_right_in[14]:12 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001541656 +37 chanx_right_in[14]:12 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.61312e-06 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:15 0.0003807 +1 chanx_right_in[14]:3 mux_top_track_32\/mux_l2_in_0_:A0 0.152 +2 chanx_right_in[14]:4 chanx_right_in[14]:3 0.002225447 +3 chanx_right_in[14]:5 chanx_right_in[14]:4 0.0045 +4 chanx_right_in[14]:10 chanx_right_in[14]:9 0.03092411 +5 chanx_right_in[14]:10 chanx_right_in[14]:5 0.001174107 +6 chanx_right_in[14]:11 chanx_right_in[14]:10 0.00341 +7 chanx_right_in[14]:12 chanx_right_in[14]:11 0.00799509 +8 chanx_right_in[14]:13 chanx_right_in[14]:12 0.00341 +9 chanx_right_in[14]:15 chanx_right_in[14]:14 0.00341 +10 chanx_right_in[14]:14 chanx_right_in[14]:13 0.001808716 +11 chanx_right_in[14]:6 mux_bottom_track_25\/mux_l2_in_1_:A1 0.152 +12 chanx_right_in[14]:8 chanx_right_in[14]:7 0.004035715 +13 chanx_right_in[14]:9 chanx_right_in[14]:8 0.0045 +14 chanx_right_in[14]:7 chanx_right_in[14]:6 0.0002111487 + +*END + +*D_NET ropt_net_190 0.004309131 //LENGTH 38.100 LUMPCC 0.0002411854 DR + +*CONN +*I mux_top_track_8\/BUFT_RR_59:X O *L 0 *C 57.500 121.040 +*I ropt_mt_inst_811:A I *L 0.001766 *C 34.960 123.760 +*N ropt_net_190:2 *C 34.998 123.760 +*N ropt_net_190:3 *C 35.375 123.760 +*N ropt_net_190:4 *C 35.420 123.805 +*N ropt_net_190:5 *C 35.420 128.815 +*N ropt_net_190:6 *C 35.465 128.860 +*N ropt_net_190:7 *C 42.320 128.860 +*N ropt_net_190:8 *C 42.320 129.200 +*N ropt_net_190:9 *C 56.580 129.200 +*N ropt_net_190:10 *C 56.580 128.860 +*N ropt_net_190:11 *C 56.580 128.815 +*N ropt_net_190:12 *C 56.580 121.085 +*N ropt_net_190:13 *C 56.625 121.040 +*N ropt_net_190:14 *C 57.463 121.040 + +*CAP +0 mux_top_track_8\/BUFT_RR_59:X 1e-06 +1 ropt_mt_inst_811:A 1e-06 +2 ropt_net_190:2 3.756956e-05 +3 ropt_net_190:3 3.756956e-05 +4 ropt_net_190:4 0.0002492584 +5 ropt_net_190:5 0.0002492584 +6 ropt_net_190:6 0.0004021321 +7 ropt_net_190:7 0.0004281712 +8 ropt_net_190:8 0.0008085146 +9 ropt_net_190:9 0.0008114497 +10 ropt_net_190:10 6.269217e-05 +11 ropt_net_190:11 0.0004135713 +12 ropt_net_190:12 0.0004135713 +13 ropt_net_190:13 7.609378e-05 +14 ropt_net_190:14 7.609378e-05 +15 ropt_net_190:12 chany_top_out[11]:6 4.708438e-05 +16 ropt_net_190:11 chany_top_out[11]:5 4.708438e-05 +17 ropt_net_190:8 chany_top_out[11]:3 7.350829e-05 +18 ropt_net_190:9 chany_top_out[11]:4 7.350829e-05 + +*RES +0 mux_top_track_8\/BUFT_RR_59:X ropt_net_190:14 0.152 +1 ropt_net_190:14 ropt_net_190:13 0.0007477679 +2 ropt_net_190:13 ropt_net_190:12 0.0045 +3 ropt_net_190:12 ropt_net_190:11 0.006901786 +4 ropt_net_190:10 ropt_net_190:9 0.0003035715 +5 ropt_net_190:11 ropt_net_190:10 0.0045 +6 ropt_net_190:6 ropt_net_190:5 0.0045 +7 ropt_net_190:5 ropt_net_190:4 0.004473215 +8 ropt_net_190:3 ropt_net_190:2 0.0003370536 +9 ropt_net_190:4 ropt_net_190:3 0.0045 +10 ropt_net_190:2 ropt_mt_inst_811:A 0.152 +11 ropt_net_190:7 ropt_net_190:6 0.006120536 +12 ropt_net_190:8 ropt_net_190:7 0.0003035715 +13 ropt_net_190:9 ropt_net_190:8 0.01273214 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_3_ccff_tail[0] 0.004592034 //LENGTH 28.605 LUMPCC 0.002126561 DR + +*CONN +*I mem_right_track_22\/FTB_26__56:X O *L 0 *C 53.605 69.360 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 29.620 66.300 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 *C 29.658 66.300 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 *C 33.535 66.300 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 *C 33.580 66.345 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 *C 33.580 68.975 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 *C 33.625 69.020 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 *C 44.575 69.020 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 *C 44.620 69.020 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 *C 44.620 69.360 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 *C 44.628 69.360 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 *C 52.893 69.360 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:12 *C 52.900 69.360 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:13 *C 52.945 69.360 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:14 *C 53.568 69.360 + +*CAP +0 mem_right_track_22\/FTB_26__56:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.0002695587 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0002695587 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.0001106987 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0001106987 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0003407958 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0003407958 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 4.589473e-05 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 4.977734e-05 +10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 0.0003832705 +11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 0.0003832705 +12 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:12 3.669524e-05 +13 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:13 6.122886e-05 +14 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:14 6.122886e-05 +15 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 chany_bottom_in[14]:11 0.0003346684 +16 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 chany_bottom_in[14]:16 8.717945e-05 +17 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 chany_bottom_in[14]:14 4.845243e-06 +18 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 chany_bottom_in[14]:15 8.717945e-05 +19 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 chany_bottom_in[14]:16 0.0003346684 +20 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 chany_bottom_in[14]:13 4.845243e-06 +21 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size5_1_sram[0]:15 0.0001501692 +22 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size5_1_sram[0]:14 0.0001501692 +23 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size5_1_sram[0]:9 2.081201e-06 +24 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size5_1_sram[0]:10 2.081201e-06 +25 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004223553 +26 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004223553 +27 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.198179e-05 +28 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.198179e-05 + +*RES +0 mem_right_track_22\/FTB_26__56:X mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:14 0.152 +1 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:14 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:13 0.0005558036 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:13 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:12 0.0045 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:12 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 0.00341 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 0.00129485 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 0.0001634615 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:9 0.00341 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.009776786 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0045 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0045 +10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.002348214 +11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.003462054 +12 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0045 +13 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_2_ccff_tail[0] 0.0008186591 //LENGTH 6.590 LUMPCC 0.0001116301 DR + +*CONN +*I mem_right_track_8\/FTB_15__45:X O *L 0 *C 28.745 101.320 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 31.455 98.940 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 *C 31.455 98.940 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 *C 31.280 98.600 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 *C 29.485 98.600 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 *C 29.440 98.645 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 *C 29.440 101.275 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 *C 29.395 101.320 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:8 *C 28.783 101.320 + +*CAP +0 mem_right_track_8\/FTB_15__45:X 1e-06 +1 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 4.867942e-05 +3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 0.0001492783 +4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 0.0001276109 +5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 0.0001080223 +6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 0.0001080223 +7 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 8.170788e-05 +8 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:8 8.170788e-05 +9 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 prog_clk[0]:344 2.548364e-06 +10 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 prog_clk[0]:349 8.127158e-06 +11 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 prog_clk[0]:346 3.787039e-05 +12 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 prog_clk[0]:349 7.269145e-06 +13 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 prog_clk[0]:343 3.787039e-05 +14 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 prog_clk[0]:346 7.269145e-06 +15 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 prog_clk[0]:345 2.548364e-06 +16 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 prog_clk[0]:350 8.127158e-06 + +*RES +0 mem_right_track_8\/FTB_15__45:X mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 0.001602679 +3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 0.0045 +4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 0.0045 +5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 0.002348214 +6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 0.000546875 +7 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_3_ccff_tail[0] 0.0009691264 //LENGTH 7.700 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/FTB_11__41:X O *L 0 *C 64.165 53.380 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 56.755 53.380 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 *C 56.793 53.380 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 *C 64.127 53.380 + +*CAP +0 mem_bottom_track_17\/FTB_11__41:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 0.0004835632 +3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 0.0004835632 + +*RES +0 mem_bottom_track_17\/FTB_11__41:X mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 0.006549107 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[0] 0.004657791 //LENGTH 34.412 LUMPCC 0.0005610737 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.525 82.620 +*I mux_right_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 83.160 94.520 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 79.480 96.560 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 83.435 96.900 +*I mux_right_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 84.080 99.620 +*N mux_tree_tapbuf_size6_3_sram[0]:5 *C 84.080 99.620 +*N mux_tree_tapbuf_size6_3_sram[0]:6 *C 84.180 99.575 +*N mux_tree_tapbuf_size6_3_sram[0]:7 *C 84.180 96.945 +*N mux_tree_tapbuf_size6_3_sram[0]:8 *C 84.135 96.900 +*N mux_tree_tapbuf_size6_3_sram[0]:9 *C 83.473 96.900 +*N mux_tree_tapbuf_size6_3_sram[0]:10 *C 79.517 96.560 +*N mux_tree_tapbuf_size6_3_sram[0]:11 *C 81.420 96.560 +*N mux_tree_tapbuf_size6_3_sram[0]:12 *C 81.420 96.900 +*N mux_tree_tapbuf_size6_3_sram[0]:13 *C 83.392 96.900 +*N mux_tree_tapbuf_size6_3_sram[0]:14 *C 83.260 96.855 +*N mux_tree_tapbuf_size6_3_sram[0]:15 *C 83.160 94.520 +*N mux_tree_tapbuf_size6_3_sram[0]:16 *C 83.260 94.520 +*N mux_tree_tapbuf_size6_3_sram[0]:17 *C 83.260 82.665 +*N mux_tree_tapbuf_size6_3_sram[0]:18 *C 83.215 82.620 +*N mux_tree_tapbuf_size6_3_sram[0]:19 *C 72.562 82.620 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_0\/mux_l1_in_2_:S 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_track_0\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_3_sram[0]:5 2.80656e-05 +6 mux_tree_tapbuf_size6_3_sram[0]:6 0.0001685398 +7 mux_tree_tapbuf_size6_3_sram[0]:7 0.0001685398 +8 mux_tree_tapbuf_size6_3_sram[0]:8 6.735152e-05 +9 mux_tree_tapbuf_size6_3_sram[0]:9 9.568963e-05 +10 mux_tree_tapbuf_size6_3_sram[0]:10 0.0001668444 +11 mux_tree_tapbuf_size6_3_sram[0]:11 0.0001965084 +12 mux_tree_tapbuf_size6_3_sram[0]:12 0.00017446 +13 mux_tree_tapbuf_size6_3_sram[0]:13 0.0001731342 +14 mux_tree_tapbuf_size6_3_sram[0]:14 0.0001379558 +15 mux_tree_tapbuf_size6_3_sram[0]:15 2.874179e-05 +16 mux_tree_tapbuf_size6_3_sram[0]:16 0.0006808872 +17 mux_tree_tapbuf_size6_3_sram[0]:17 0.0005094435 +18 mux_tree_tapbuf_size6_3_sram[0]:18 0.0007477779 +19 mux_tree_tapbuf_size6_3_sram[0]:19 0.0007477779 +20 mux_tree_tapbuf_size6_3_sram[0]:17 chany_bottom_in[2]:26 0.0002805368 +21 mux_tree_tapbuf_size6_3_sram[0]:16 chany_bottom_in[2]:22 0.0002805368 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_3_sram[0]:19 0.152 +1 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:12 0.001761161 +2 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:9 7.142857e-05 +3 mux_tree_tapbuf_size6_3_sram[0]:14 mux_tree_tapbuf_size6_3_sram[0]:13 0.0045 +4 mux_tree_tapbuf_size6_3_sram[0]:9 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +5 mux_tree_tapbuf_size6_3_sram[0]:9 mux_tree_tapbuf_size6_3_sram[0]:8 0.0005915179 +6 mux_tree_tapbuf_size6_3_sram[0]:18 mux_tree_tapbuf_size6_3_sram[0]:17 0.0045 +7 mux_tree_tapbuf_size6_3_sram[0]:17 mux_tree_tapbuf_size6_3_sram[0]:16 0.01058482 +8 mux_tree_tapbuf_size6_3_sram[0]:19 mux_tree_tapbuf_size6_3_sram[0]:18 0.009511162 +9 mux_tree_tapbuf_size6_3_sram[0]:15 mux_right_track_0\/mux_l1_in_2_:S 0.152 +10 mux_tree_tapbuf_size6_3_sram[0]:16 mux_tree_tapbuf_size6_3_sram[0]:15 0.0045 +11 mux_tree_tapbuf_size6_3_sram[0]:16 mux_tree_tapbuf_size6_3_sram[0]:14 0.002084821 +12 mux_tree_tapbuf_size6_3_sram[0]:8 mux_tree_tapbuf_size6_3_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size6_3_sram[0]:7 mux_tree_tapbuf_size6_3_sram[0]:6 0.002348214 +14 mux_tree_tapbuf_size6_3_sram[0]:5 mux_right_track_0\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size6_3_sram[0]:6 mux_tree_tapbuf_size6_3_sram[0]:5 0.0045 +16 mux_tree_tapbuf_size6_3_sram[0]:10 mux_right_track_0\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size6_3_sram[0]:11 mux_tree_tapbuf_size6_3_sram[0]:10 0.001698661 +18 mux_tree_tapbuf_size6_3_sram[0]:12 mux_tree_tapbuf_size6_3_sram[0]:11 0.0003035715 + +*END + +*D_NET optlc_net_183 0.002225451 //LENGTH 19.075 LUMPCC 0.0002141472 DR + +*CONN +*I optlc_171:HI O *L 0 *C 90.160 31.620 +*I mux_bottom_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 80.790 33.660 +*I mux_bottom_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 94.590 31.620 +*N optlc_net_183:3 *C 94.553 31.620 +*N optlc_net_183:4 *C 93.380 31.620 +*N optlc_net_183:5 *C 93.380 31.280 +*N optlc_net_183:6 *C 80.828 33.660 +*N optlc_net_183:7 *C 81.375 33.660 +*N optlc_net_183:8 *C 81.420 33.615 +*N optlc_net_183:9 *C 81.420 30.985 +*N optlc_net_183:10 *C 81.465 30.940 +*N optlc_net_183:11 *C 90.160 30.940 +*N optlc_net_183:12 *C 90.160 31.280 +*N optlc_net_183:13 *C 90.160 31.620 + +*CAP +0 optlc_171:HI 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_9\/mux_l2_in_1_:A0 1e-06 +3 optlc_net_183:3 9.371211e-05 +4 optlc_net_183:4 0.0001174514 +5 optlc_net_183:5 0.0002276863 +6 optlc_net_183:6 6.479416e-05 +7 optlc_net_183:7 6.479416e-05 +8 optlc_net_183:8 0.0001573578 +9 optlc_net_183:9 0.0001573578 +10 optlc_net_183:10 0.0004002982 +11 optlc_net_183:11 0.0004212477 +12 optlc_net_183:12 0.0002493827 +13 optlc_net_183:13 5.42212e-05 +14 optlc_net_183:10 chany_bottom_in[3]:8 0.0001046185 +15 optlc_net_183:9 chany_bottom_in[3]:10 2.45507e-06 +16 optlc_net_183:8 chany_bottom_in[3]:9 2.45507e-06 +17 optlc_net_183:11 chany_bottom_in[3]:7 0.0001046185 + +*RES +0 optlc_171:HI optlc_net_183:13 0.152 +1 optlc_net_183:10 optlc_net_183:9 0.0045 +2 optlc_net_183:9 optlc_net_183:8 0.002348214 +3 optlc_net_183:7 optlc_net_183:6 0.0004888393 +4 optlc_net_183:8 optlc_net_183:7 0.0045 +5 optlc_net_183:6 mux_bottom_track_5\/mux_l2_in_1_:A0 0.152 +6 optlc_net_183:13 optlc_net_183:12 0.0003035714 +7 optlc_net_183:3 mux_bottom_track_9\/mux_l2_in_1_:A0 0.152 +8 optlc_net_183:11 optlc_net_183:10 0.007763393 +9 optlc_net_183:12 optlc_net_183:11 0.0003035715 +10 optlc_net_183:12 optlc_net_183:5 0.002875 +11 optlc_net_183:5 optlc_net_183:4 0.0003035714 +12 optlc_net_183:4 optlc_net_183:3 0.001046875 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.003437781 //LENGTH 29.730 LUMPCC 0.000922312 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 46.285 44.200 +*I mux_bottom_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 48.400 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 48.300 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 48.300 18.065 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 48.300 25.455 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 48.255 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 46.045 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 46.000 25.545 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 46.000 44.155 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 46.000 44.200 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 46.285 44.200 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.24572e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002299976 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002299976 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001506429 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001506429 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000801356 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000801356 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 5.720845e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:10 5.981098e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chany_top_in[14]:7 0.0001003121 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[14]:8 0.0001003121 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_4_sram[1]:7 0.0001127197 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_4_sram[1]:8 0.0001127197 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.975307e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.975307e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001483712 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001483712 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.006598215 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001973214 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.01661607 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001548913 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00325723 //LENGTH 26.195 LUMPCC 0.0003644431 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_1_:X O *L 0 *C 99.075 46.920 +*I mux_bottom_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 76.190 44.540 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 76.228 44.540 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 85.515 44.540 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 85.560 44.585 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.560 46.875 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 85.605 46.920 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 99.038 46.920 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005482486 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0005482486 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001550088 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001550088 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000742136 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000742136 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_3_sram[0]:5 1.458321e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_3_sram[0]:18 6.543326e-07 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_3_sram[0]:20 3.64102e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_3_sram[0]:22 0.0001305738 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_3_sram[0]:4 1.458321e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_3_sram[0]:19 6.543326e-07 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_3_sram[0]:21 3.64102e-05 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_3_sram[0]:23 0.0001305738 + +*RES +0 mux_bottom_track_17\/mux_l1_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.008292411 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0119933 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0] 0.006277516 //LENGTH 46.695 LUMPCC 0.0007759709 DR + +*CONN +*I mux_right_track_12\/mux_l3_in_0_:X O *L 0 *C 64.225 88.400 +*I mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.770 82.795 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 103.770 82.795 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 103.500 82.960 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 103.500 82.960 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 103.493 82.960 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 92.940 82.960 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 92.920 82.968 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 92.920 87.713 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 92.900 87.720 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 65.328 87.720 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 65.320 87.778 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 65.320 88.355 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 65.275 88.400 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 64.263 88.400 + +*CAP +0 mux_right_track_12\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.715373e-05 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.201543e-05 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.209841e-05 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005954962 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005954962 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002826737 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002826737 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001680483 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.001680483 +11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 4.319956e-05 +12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 4.319956e-05 +13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:13 7.72866e-05 +14 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:14 7.72866e-05 +15 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 prog_clk[0]:224 1.980103e-06 +16 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 prog_clk[0]:231 3.338992e-06 +17 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 prog_clk[0]:225 1.980103e-06 +18 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 prog_clk[0]:234 3.338992e-06 +19 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 prog_clk[0]:205 1.551385e-05 +20 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 prog_clk[0]:230 0.000115315 +21 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 prog_clk[0]:204 1.551385e-05 +22 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 prog_clk[0]:229 0.000115315 +23 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001521617 +24 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001521617 +25 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.967577e-05 +26 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.967577e-05 + +*RES +0 mux_right_track_12\/mux_l3_in_0_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0009040179 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.000515625 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.00341 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.004319692 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0007433833 +9 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001653225 +10 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +11 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +12 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +13 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001467391 + +*END + +*D_NET chany_top_out[18] 0.001632481 //LENGTH 12.825 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 50.600 126.820 +*P chany_top_out[18] O *L 0.7423 *C 47.840 129.275 +*N chany_top_out[18]:2 *C 47.840 128.528 +*N chany_top_out[18]:3 *C 47.860 128.520 +*N chany_top_out[18]:4 *C 53.812 128.520 +*N chany_top_out[18]:5 *C 53.820 128.463 +*N chany_top_out[18]:6 *C 53.820 126.865 +*N chany_top_out[18]:7 *C 53.775 126.820 +*N chany_top_out[18]:8 *C 50.638 126.820 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chany_top_out[18] 7.516032e-05 +2 chany_top_out[18]:2 7.516032e-05 +3 chany_top_out[18]:3 0.0003918713 +4 chany_top_out[18]:4 0.0003918713 +5 chany_top_out[18]:5 0.0001165902 +6 chany_top_out[18]:6 0.0001165902 +7 chany_top_out[18]:7 0.0002321187 +8 chany_top_out[18]:8 0.0002321187 + +*RES +0 ropt_mt_inst_810:X chany_top_out[18]:8 0.152 +1 chany_top_out[18]:8 chany_top_out[18]:7 0.002801339 +2 chany_top_out[18]:7 chany_top_out[18]:6 0.0045 +3 chany_top_out[18]:6 chany_top_out[18]:5 0.001426339 +4 chany_top_out[18]:5 chany_top_out[18]:4 0.00341 +5 chany_top_out[18]:4 chany_top_out[18]:3 0.0009325583 +6 chany_top_out[18]:3 chany_top_out[18]:2 0.00341 +7 chany_top_out[18]:2 chany_top_out[18] 0.0001171083 + +*END + +*D_NET chany_bottom_out[14] 0.001503056 //LENGTH 9.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 42.780 4.760 +*P chany_bottom_out[14] O *L 0.7423 *C 46.000 1.210 +*N chany_bottom_out[14]:2 *C 45.600 2.040 +*N chany_bottom_out[14]:3 *C 46.000 2.033 +*N chany_bottom_out[14]:4 *C 46.000 2.040 +*N chany_bottom_out[14]:5 *C 46.000 2.098 +*N chany_bottom_out[14]:6 *C 46.000 3.343 +*N chany_bottom_out[14]:7 *C 45.992 3.400 +*N chany_bottom_out[14]:8 *C 45.088 3.400 +*N chany_bottom_out[14]:9 *C 45.080 3.458 +*N chany_bottom_out[14]:10 *C 45.080 4.715 +*N chany_bottom_out[14]:11 *C 45.035 4.760 +*N chany_bottom_out[14]:12 *C 42.818 4.760 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 chany_bottom_out[14] 9.254907e-05 +2 chany_bottom_out[14]:2 8.45819e-05 +3 chany_bottom_out[14]:3 9.254907e-05 +4 chany_bottom_out[14]:4 8.45819e-05 +5 chany_bottom_out[14]:5 0.0001280293 +6 chany_bottom_out[14]:6 0.0001280293 +7 chany_bottom_out[14]:7 0.0001304611 +8 chany_bottom_out[14]:8 0.0001304611 +9 chany_bottom_out[14]:9 0.0001165496 +10 chany_bottom_out[14]:10 0.0001165496 +11 chany_bottom_out[14]:11 0.0001988572 +12 chany_bottom_out[14]:12 0.0001988572 + +*RES +0 ropt_mt_inst_821:X chany_bottom_out[14]:12 0.152 +1 chany_bottom_out[14]:12 chany_bottom_out[14]:11 0.001979911 +2 chany_bottom_out[14]:11 chany_bottom_out[14]:10 0.0045 +3 chany_bottom_out[14]:10 chany_bottom_out[14]:9 0.001122768 +4 chany_bottom_out[14]:9 chany_bottom_out[14]:8 0.00341 +5 chany_bottom_out[14]:8 chany_bottom_out[14]:7 0.0001417833 +6 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.001111607 +7 chany_bottom_out[14]:7 chany_bottom_out[14]:6 0.00341 +8 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.00341 +9 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.00341 +10 chany_bottom_out[14]:4 chany_bottom_out[14]:2 5.69697e-05 +11 chany_bottom_out[14]:3 chany_bottom_out[14] 0.0001288583 + +*END + +*D_NET chany_bottom_out[12] 0.0004542198 //LENGTH 3.565 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_846:X O *L 0 *C 66.700 3.400 +*P chany_bottom_out[12] O *L 0.7423 *C 67.620 1.325 +*N chany_bottom_out[12]:2 *C 67.160 1.360 +*N chany_bottom_out[12]:3 *C 67.160 3.355 +*N chany_bottom_out[12]:4 *C 67.115 3.400 +*N chany_bottom_out[12]:5 *C 66.737 3.400 + +*CAP +0 ropt_mt_inst_846:X 1e-06 +1 chany_bottom_out[12] 3.182014e-05 +2 chany_bottom_out[12]:2 0.0001781378 +3 chany_bottom_out[12]:3 0.0001463177 +4 chany_bottom_out[12]:4 4.847209e-05 +5 chany_bottom_out[12]:5 4.847209e-05 + +*RES +0 ropt_mt_inst_846:X chany_bottom_out[12]:5 0.152 +1 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0003370536 +2 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.0045 +3 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.00178125 +4 chany_bottom_out[12]:2 chany_bottom_out[12] 0.0004107143 + +*END + +*D_NET chany_bottom_out[3] 0.001966385 //LENGTH 14.530 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_862:X O *L 0 *C 49.295 8.840 +*P chany_bottom_out[3] O *L 0.7423 *C 44.620 1.290 +*N chany_bottom_out[3]:2 *C 44.620 1.995 +*N chany_bottom_out[3]:3 *C 44.665 2.040 +*N chany_bottom_out[3]:4 *C 47.795 2.040 +*N chany_bottom_out[3]:5 *C 47.840 2.085 +*N chany_bottom_out[3]:6 *C 47.840 5.440 +*N chany_bottom_out[3]:7 *C 47.380 5.440 +*N chany_bottom_out[3]:8 *C 47.380 8.795 +*N chany_bottom_out[3]:9 *C 47.425 8.840 +*N chany_bottom_out[3]:10 *C 49.258 8.840 + +*CAP +0 ropt_mt_inst_862:X 1e-06 +1 chany_bottom_out[3] 5.881871e-05 +2 chany_bottom_out[3]:2 5.881871e-05 +3 chany_bottom_out[3]:3 0.0002297181 +4 chany_bottom_out[3]:4 0.0002297181 +5 chany_bottom_out[3]:5 0.0002654332 +6 chany_bottom_out[3]:6 0.0002958834 +7 chany_bottom_out[3]:7 0.0002722504 +8 chany_bottom_out[3]:8 0.0002418001 +9 chany_bottom_out[3]:9 0.0001564724 +10 chany_bottom_out[3]:10 0.0001564724 + +*RES +0 ropt_mt_inst_862:X chany_bottom_out[3]:10 0.152 +1 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0045 +2 chany_bottom_out[3]:2 chany_bottom_out[3] 0.0006294643 +3 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.002794643 +4 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.0045 +5 chany_bottom_out[3]:9 chany_bottom_out[3]:8 0.0045 +6 chany_bottom_out[3]:8 chany_bottom_out[3]:7 0.002995536 +7 chany_bottom_out[3]:10 chany_bottom_out[3]:9 0.001636161 +8 chany_bottom_out[3]:7 chany_bottom_out[3]:6 0.0004107143 +9 chany_bottom_out[3]:6 chany_bottom_out[3]:5 0.002995536 + +*END + +*D_NET chany_top_in[12] 0.02097401 //LENGTH 165.092 LUMPCC 0.004467001 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 72.220 129.235 +*I mux_right_track_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.700 94.180 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.270 37.060 +*I ropt_mt_inst_827:A I *L 0.001767 *C 54.740 12.240 +*N chany_top_in[12]:4 *C 50.810 34.680 +*N chany_top_in[12]:5 *C 54.703 12.240 +*N chany_top_in[12]:6 *C 51.565 12.240 +*N chany_top_in[12]:7 *C 51.520 12.285 +*N chany_top_in[12]:8 *C 51.520 34.623 +*N chany_top_in[12]:9 *C 51.518 34.680 +*N chany_top_in[12]:10 *C 51.520 34.688 +*N chany_top_in[12]:11 *C 52.270 37.060 +*N chany_top_in[12]:12 *C 52.440 37.060 +*N chany_top_in[12]:13 *C 52.440 37.015 +*N chany_top_in[12]:14 *C 52.440 36.098 +*N chany_top_in[12]:15 *C 52.433 36.040 +*N chany_top_in[12]:16 *C 51.540 36.040 +*N chany_top_in[12]:17 *C 51.520 36.032 +*N chany_top_in[12]:18 *C 50.600 36.040 +*N chany_top_in[12]:19 *C 50.600 85.890 +*N chany_top_in[12]:20 *C 50.600 91.113 +*N chany_top_in[12]:21 *C 50.620 91.120 +*N chany_top_in[12]:22 *C 54.273 91.120 +*N chany_top_in[12]:23 *C 54.280 91.178 +*N chany_top_in[12]:24 *C 54.280 94.475 +*N chany_top_in[12]:25 *C 54.325 94.520 +*N chany_top_in[12]:26 *C 73.600 94.520 +*N chany_top_in[12]:27 *C 73.737 94.180 +*N chany_top_in[12]:28 *C 79.075 94.180 +*N chany_top_in[12]:29 *C 79.120 94.225 +*N chany_top_in[12]:30 *C 79.120 106.023 +*N chany_top_in[12]:31 *C 79.112 106.080 +*N chany_top_in[12]:32 *C 74.528 106.080 +*N chany_top_in[12]:33 *C 74.520 106.138 +*N chany_top_in[12]:34 *C 74.520 127.840 +*N chany_top_in[12]:35 *C 72.220 127.840 + +*CAP +0 chany_top_in[12] 8.908696e-05 +1 mux_right_track_14\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +3 ropt_mt_inst_827:A 1e-06 +4 chany_top_in[12]:4 9.041367e-05 +5 chany_top_in[12]:5 0.0002221125 +6 chany_top_in[12]:6 0.0002221125 +7 chany_top_in[12]:7 0.001150064 +8 chany_top_in[12]:8 0.001150064 +9 chany_top_in[12]:9 9.041367e-05 +10 chany_top_in[12]:10 3.630249e-05 +11 chany_top_in[12]:11 5.157146e-05 +12 chany_top_in[12]:12 5.666162e-05 +13 chany_top_in[12]:13 9.423852e-05 +14 chany_top_in[12]:14 9.423852e-05 +15 chany_top_in[12]:15 9.570297e-05 +16 chany_top_in[12]:16 9.570297e-05 +17 chany_top_in[12]:17 0.0001017669 +18 chany_top_in[12]:18 0.001790782 +19 chany_top_in[12]:19 0.002022135 +20 chany_top_in[12]:20 0.0002968177 +21 chany_top_in[12]:21 0.0003902081 +22 chany_top_in[12]:22 0.0003902081 +23 chany_top_in[12]:23 0.000167616 +24 chany_top_in[12]:24 0.000167616 +25 chany_top_in[12]:25 0.001226124 +26 chany_top_in[12]:26 0.00125415 +27 chany_top_in[12]:27 0.0004165714 +28 chany_top_in[12]:28 0.000388546 +29 chany_top_in[12]:29 0.0005711602 +30 chany_top_in[12]:30 0.0005711602 +31 chany_top_in[12]:31 0.0003772101 +32 chany_top_in[12]:32 0.0003772101 +33 chany_top_in[12]:33 0.001076709 +34 chany_top_in[12]:34 0.001183478 +35 chany_top_in[12]:35 0.000195856 +36 chany_top_in[12]:7 chany_bottom_in[5]:31 1.56933e-05 +37 chany_top_in[12]:8 chany_bottom_in[5]:30 1.56933e-05 +38 chany_top_in[12]:10 chany_bottom_in[5]:31 2.773929e-05 +39 chany_top_in[12]:17 chany_bottom_in[5]:30 2.773929e-05 +40 chany_top_in[12]:18 chany_bottom_in[5]:31 0.000494634 +41 chany_top_in[12]:19 chany_bottom_in[5]:30 0.000494634 +42 chany_top_in[12]:24 chany_bottom_in[10]:6 2.832436e-05 +43 chany_top_in[12]:23 chany_bottom_in[10]:10 2.832436e-05 +44 chany_top_in[12]:7 chany_bottom_in[10] 1.341341e-07 +45 chany_top_in[12]:8 chany_bottom_in[10]:25 1.341341e-07 +46 chany_top_in[12]:10 chany_bottom_in[10]:22 6.827011e-05 +47 chany_top_in[12]:17 chany_bottom_in[10]:21 6.827011e-05 +48 chany_top_in[12]:18 chany_bottom_in[10]:22 0.0005398194 +49 chany_top_in[12]:18 chany_bottom_in[10]:21 0.000402763 +50 chany_top_in[12]:19 chany_bottom_in[10]:20 0.000402763 +51 chany_top_in[12]:19 chany_bottom_in[10]:21 0.0005398194 +52 chany_top_in[12]:29 right_top_grid_pin_47_[0]:9 9.125518e-05 +53 chany_top_in[12]:29 right_top_grid_pin_47_[0]:6 0.0002102359 +54 chany_top_in[12]:30 right_top_grid_pin_47_[0]:9 0.0002102359 +55 chany_top_in[12]:30 right_top_grid_pin_47_[0]:10 9.125518e-05 +56 chany_top_in[12]:25 mux_tree_tapbuf_size4_4_sram[2]:5 0.0001438747 +57 chany_top_in[12]:26 mux_tree_tapbuf_size4_4_sram[2]:4 0.0001438747 +58 chany_top_in[12]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.46051e-05 +59 chany_top_in[12]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.46051e-05 +60 chany_top_in[12]:33 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.035736e-05 +61 chany_top_in[12]:34 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.035736e-05 +62 chany_top_in[12]:33 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.579487e-05 +63 chany_top_in[12]:34 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.579487e-05 + +*RES +0 chany_top_in[12] chany_top_in[12]:35 0.001245536 +1 chany_top_in[12]:25 chany_top_in[12]:24 0.0045 +2 chany_top_in[12]:24 chany_top_in[12]:23 0.002944196 +3 chany_top_in[12]:23 chany_top_in[12]:22 0.00341 +4 chany_top_in[12]:22 chany_top_in[12]:21 0.000572225 +5 chany_top_in[12]:21 chany_top_in[12]:20 0.00341 +6 chany_top_in[12]:20 chany_top_in[12]:19 0.0008181916 +7 chany_top_in[12]:5 ropt_mt_inst_827:A 0.152 +8 chany_top_in[12]:6 chany_top_in[12]:5 0.002801339 +9 chany_top_in[12]:7 chany_top_in[12]:6 0.0045 +10 chany_top_in[12]:8 chany_top_in[12]:7 0.0199442 +11 chany_top_in[12]:9 chany_top_in[12]:8 0.00341 +12 chany_top_in[12]:9 chany_top_in[12]:4 0.0001039141 +13 chany_top_in[12]:10 chany_top_in[12]:9 0.00341 +14 chany_top_in[12]:27 mux_right_track_14\/mux_l1_in_0_:A1 0.152 +15 chany_top_in[12]:27 chany_top_in[12]:26 0.0003035715 +16 chany_top_in[12]:16 chany_top_in[12]:15 0.000139825 +17 chany_top_in[12]:17 chany_top_in[12]:16 0.00341 +18 chany_top_in[12]:17 chany_top_in[12]:10 0.0002107167 +19 chany_top_in[12]:14 chany_top_in[12]:13 0.0008191965 +20 chany_top_in[12]:15 chany_top_in[12]:14 0.00341 +21 chany_top_in[12]:12 chany_top_in[12]:11 9.239132e-05 +22 chany_top_in[12]:13 chany_top_in[12]:12 0.0045 +23 chany_top_in[12]:11 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +24 chany_top_in[12]:28 chany_top_in[12]:27 0.004765626 +25 chany_top_in[12]:29 chany_top_in[12]:28 0.0045 +26 chany_top_in[12]:30 chany_top_in[12]:29 0.01053348 +27 chany_top_in[12]:31 chany_top_in[12]:30 0.00341 +28 chany_top_in[12]:33 chany_top_in[12]:32 0.00341 +29 chany_top_in[12]:32 chany_top_in[12]:31 0.0007183166 +30 chany_top_in[12]:26 chany_top_in[12]:25 0.01720982 +31 chany_top_in[12]:35 chany_top_in[12]:34 0.002053572 +32 chany_top_in[12]:34 chany_top_in[12]:33 0.01937724 +33 chany_top_in[12]:18 chany_top_in[12]:17 0.0001441333 +34 chany_top_in[12]:19 chany_top_in[12]:18 0.007809833 + +*END + +*D_NET right_top_grid_pin_44_[0] 0.009248725 //LENGTH 66.205 LUMPCC 0.00228014 DR + +*CONN +*P right_top_grid_pin_44_[0] I *L 0.29796 *C 110.860 102.070 +*I mux_right_track_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.230 93.500 +*I mux_right_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 75.270 102.340 +*I mux_right_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 83.360 99.620 +*N right_top_grid_pin_44_[0]:4 *C 83.360 99.620 +*N right_top_grid_pin_44_[0]:5 *C 75.233 102.340 +*N right_top_grid_pin_44_[0]:6 *C 74.105 102.340 +*N right_top_grid_pin_44_[0]:7 *C 74.060 102.295 +*N right_top_grid_pin_44_[0]:8 *C 64.267 93.500 +*N right_top_grid_pin_44_[0]:9 *C 65.275 93.500 +*N right_top_grid_pin_44_[0]:10 *C 65.320 93.545 +*N right_top_grid_pin_44_[0]:11 *C 65.320 99.903 +*N right_top_grid_pin_44_[0]:12 *C 65.328 99.960 +*N right_top_grid_pin_44_[0]:13 *C 74.053 99.960 +*N right_top_grid_pin_44_[0]:14 *C 74.060 99.960 +*N right_top_grid_pin_44_[0]:15 *C 74.105 99.960 +*N right_top_grid_pin_44_[0]:16 *C 83.260 99.960 +*N right_top_grid_pin_44_[0]:17 *C 90.115 99.960 +*N right_top_grid_pin_44_[0]:18 *C 90.160 99.915 +*N right_top_grid_pin_44_[0]:19 *C 90.160 97.978 +*N right_top_grid_pin_44_[0]:20 *C 90.168 97.920 +*N right_top_grid_pin_44_[0]:21 *C 110.853 97.920 +*N right_top_grid_pin_44_[0]:22 *C 110.860 97.978 + +*CAP +0 right_top_grid_pin_44_[0] 0.0002073567 +1 mux_right_track_12\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_4\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_0\/mux_l1_in_1_:A1 1e-06 +4 right_top_grid_pin_44_[0]:4 5.625209e-05 +5 right_top_grid_pin_44_[0]:5 9.276078e-05 +6 right_top_grid_pin_44_[0]:6 9.276078e-05 +7 right_top_grid_pin_44_[0]:7 0.0001313909 +8 right_top_grid_pin_44_[0]:8 9.15725e-05 +9 right_top_grid_pin_44_[0]:9 9.15725e-05 +10 right_top_grid_pin_44_[0]:10 0.000356468 +11 right_top_grid_pin_44_[0]:11 0.000356468 +12 right_top_grid_pin_44_[0]:12 0.0005164923 +13 right_top_grid_pin_44_[0]:13 0.0005164923 +14 right_top_grid_pin_44_[0]:14 0.0001678632 +15 right_top_grid_pin_44_[0]:15 0.0006929042 +16 right_top_grid_pin_44_[0]:16 0.001140746 +17 right_top_grid_pin_44_[0]:17 0.0004200137 +18 right_top_grid_pin_44_[0]:18 0.0001261668 +19 right_top_grid_pin_44_[0]:19 0.0001261668 +20 right_top_grid_pin_44_[0]:20 0.0007873906 +21 right_top_grid_pin_44_[0]:21 0.0007873906 +22 right_top_grid_pin_44_[0]:22 0.0002073567 +23 right_top_grid_pin_44_[0]:20 chanx_right_in[12]:14 0.0003725702 +24 right_top_grid_pin_44_[0]:21 chanx_right_in[12] 0.0003725702 +25 right_top_grid_pin_44_[0]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.109079e-05 +26 right_top_grid_pin_44_[0]:20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002094533 +27 right_top_grid_pin_44_[0]:21 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002094533 +28 right_top_grid_pin_44_[0]:13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004764815 +29 right_top_grid_pin_44_[0]:12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004764815 +30 right_top_grid_pin_44_[0]:16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.109079e-05 +31 right_top_grid_pin_44_[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.047435e-05 +32 right_top_grid_pin_44_[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.047435e-05 + +*RES +0 right_top_grid_pin_44_[0] right_top_grid_pin_44_[0]:22 0.003654018 +1 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:16 0.006120536 +2 right_top_grid_pin_44_[0]:18 right_top_grid_pin_44_[0]:17 0.0045 +3 right_top_grid_pin_44_[0]:19 right_top_grid_pin_44_[0]:18 0.001729911 +4 right_top_grid_pin_44_[0]:20 right_top_grid_pin_44_[0]:19 0.00341 +5 right_top_grid_pin_44_[0]:22 right_top_grid_pin_44_[0]:21 0.00341 +6 right_top_grid_pin_44_[0]:21 right_top_grid_pin_44_[0]:20 0.00324065 +7 right_top_grid_pin_44_[0]:15 right_top_grid_pin_44_[0]:14 0.0045 +8 right_top_grid_pin_44_[0]:14 right_top_grid_pin_44_[0]:13 0.00341 +9 right_top_grid_pin_44_[0]:14 right_top_grid_pin_44_[0]:7 0.002084821 +10 right_top_grid_pin_44_[0]:13 right_top_grid_pin_44_[0]:12 0.001366917 +11 right_top_grid_pin_44_[0]:11 right_top_grid_pin_44_[0]:10 0.00567634 +12 right_top_grid_pin_44_[0]:12 right_top_grid_pin_44_[0]:11 0.00341 +13 right_top_grid_pin_44_[0]:9 right_top_grid_pin_44_[0]:8 0.0008995536 +14 right_top_grid_pin_44_[0]:10 right_top_grid_pin_44_[0]:9 0.0045 +15 right_top_grid_pin_44_[0]:8 mux_right_track_12\/mux_l2_in_0_:A0 0.152 +16 right_top_grid_pin_44_[0]:6 right_top_grid_pin_44_[0]:5 0.001006696 +17 right_top_grid_pin_44_[0]:7 right_top_grid_pin_44_[0]:6 0.0045 +18 right_top_grid_pin_44_[0]:5 mux_right_track_4\/mux_l1_in_1_:A0 0.152 +19 right_top_grid_pin_44_[0]:4 mux_right_track_0\/mux_l1_in_1_:A1 0.152 +20 right_top_grid_pin_44_[0]:16 right_top_grid_pin_44_[0]:15 0.008174107 +21 right_top_grid_pin_44_[0]:16 right_top_grid_pin_44_[0]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[1] 0.00240074 //LENGTH 21.120 LUMPCC 0.0003420942 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 43.085 33.660 +*I mux_bottom_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 35.980 25.550 +*I mem_bottom_track_33\/FTB_27__57:A I *L 0.001746 *C 37.260 23.120 +*N mux_tree_tapbuf_size3_4_sram[1]:3 *C 37.297 23.120 +*N mux_tree_tapbuf_size3_4_sram[1]:4 *C 39.055 23.120 +*N mux_tree_tapbuf_size3_4_sram[1]:5 *C 39.100 23.165 +*N mux_tree_tapbuf_size3_4_sram[1]:6 *C 35.980 25.550 +*N mux_tree_tapbuf_size3_4_sram[1]:7 *C 36.038 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:8 *C 39.055 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:9 *C 39.100 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:10 *C 39.100 33.615 +*N mux_tree_tapbuf_size3_4_sram[1]:11 *C 39.145 33.660 +*N mux_tree_tapbuf_size3_4_sram[1]:12 *C 43.047 33.660 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_33\/FTB_27__57:A 1e-06 +3 mux_tree_tapbuf_size3_4_sram[1]:3 0.0001118571 +4 mux_tree_tapbuf_size3_4_sram[1]:4 0.0001118571 +5 mux_tree_tapbuf_size3_4_sram[1]:5 0.0001277894 +6 mux_tree_tapbuf_size3_4_sram[1]:6 5.164181e-05 +7 mux_tree_tapbuf_size3_4_sram[1]:7 0.0001706535 +8 mux_tree_tapbuf_size3_4_sram[1]:8 0.000145286 +9 mux_tree_tapbuf_size3_4_sram[1]:9 0.0004879628 +10 mux_tree_tapbuf_size3_4_sram[1]:10 0.0003325929 +11 mux_tree_tapbuf_size3_4_sram[1]:11 0.0002580026 +12 mux_tree_tapbuf_size3_4_sram[1]:12 0.0002580026 +13 mux_tree_tapbuf_size3_4_sram[1]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.274788e-06 +14 mux_tree_tapbuf_size3_4_sram[1]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.715597e-05 +15 mux_tree_tapbuf_size3_4_sram[1]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.661633e-05 +16 mux_tree_tapbuf_size3_4_sram[1]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.715597e-05 +17 mux_tree_tapbuf_size3_4_sram[1]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.274788e-06 +18 mux_tree_tapbuf_size3_4_sram[1]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.661633e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_4_sram[1]:12 0.152 +1 mux_tree_tapbuf_size3_4_sram[1]:4 mux_tree_tapbuf_size3_4_sram[1]:3 0.001569197 +2 mux_tree_tapbuf_size3_4_sram[1]:5 mux_tree_tapbuf_size3_4_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size3_4_sram[1]:3 mem_bottom_track_33\/FTB_27__57:A 0.152 +4 mux_tree_tapbuf_size3_4_sram[1]:12 mux_tree_tapbuf_size3_4_sram[1]:11 0.003484375 +5 mux_tree_tapbuf_size3_4_sram[1]:11 mux_tree_tapbuf_size3_4_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size3_4_sram[1]:10 mux_tree_tapbuf_size3_4_sram[1]:9 0.006941965 +7 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size3_4_sram[1]:7 0.002694197 +8 mux_tree_tapbuf_size3_4_sram[1]:9 mux_tree_tapbuf_size3_4_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size3_4_sram[1]:9 mux_tree_tapbuf_size3_4_sram[1]:5 0.002388393 +10 mux_tree_tapbuf_size3_4_sram[1]:6 mux_bottom_track_33\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size3_4_sram[1]:7 mux_tree_tapbuf_size3_4_sram[1]:6 0.0001686047 + +*END + +*D_NET mux_tree_tapbuf_size4_5_sram[2] 0.001373349 //LENGTH 10.525 LUMPCC 0.0001627435 DR + +*CONN +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 85.405 88.060 +*I mux_right_track_14\/mux_l3_in_0_:S I *L 0.00357 *C 85.000 85.340 +*I mem_right_track_14\/FTB_18__48:A I *L 0.001746 *C 91.540 88.400 +*N mux_tree_tapbuf_size4_5_sram[2]:3 *C 91.502 88.400 +*N mux_tree_tapbuf_size4_5_sram[2]:4 *C 85.100 88.400 +*N mux_tree_tapbuf_size4_5_sram[2]:5 *C 85.000 85.340 +*N mux_tree_tapbuf_size4_5_sram[2]:6 *C 85.100 85.385 +*N mux_tree_tapbuf_size4_5_sram[2]:7 *C 85.100 88.015 +*N mux_tree_tapbuf_size4_5_sram[2]:8 *C 85.100 88.060 +*N mux_tree_tapbuf_size4_5_sram[2]:9 *C 85.405 88.060 + +*CAP +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_14\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_14\/FTB_18__48:A 1e-06 +3 mux_tree_tapbuf_size4_5_sram[2]:3 0.0003392914 +4 mux_tree_tapbuf_size4_5_sram[2]:4 0.000369114 +5 mux_tree_tapbuf_size4_5_sram[2]:5 3.032432e-05 +6 mux_tree_tapbuf_size4_5_sram[2]:6 0.0001749189 +7 mux_tree_tapbuf_size4_5_sram[2]:7 0.0001749189 +8 mux_tree_tapbuf_size4_5_sram[2]:8 7.716636e-05 +9 mux_tree_tapbuf_size4_5_sram[2]:9 4.187135e-05 +10 mux_tree_tapbuf_size4_5_sram[2]:3 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 8.137173e-05 +11 mux_tree_tapbuf_size4_5_sram[2]:4 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 8.137173e-05 + +*RES +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_5_sram[2]:9 0.152 +1 mux_tree_tapbuf_size4_5_sram[2]:3 mem_right_track_14\/FTB_18__48:A 0.152 +2 mux_tree_tapbuf_size4_5_sram[2]:8 mux_tree_tapbuf_size4_5_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size4_5_sram[2]:8 mux_tree_tapbuf_size4_5_sram[2]:4 0.0003035715 +4 mux_tree_tapbuf_size4_5_sram[2]:7 mux_tree_tapbuf_size4_5_sram[2]:6 0.002348215 +5 mux_tree_tapbuf_size4_5_sram[2]:5 mux_right_track_14\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size4_5_sram[2]:6 mux_tree_tapbuf_size4_5_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size4_5_sram[2]:9 mux_tree_tapbuf_size4_5_sram[2]:8 0.0001548913 +8 mux_tree_tapbuf_size4_5_sram[2]:4 mux_tree_tapbuf_size4_5_sram[2]:3 0.005716518 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[2] 0.001594429 //LENGTH 12.792 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 75.745 53.040 +*I mem_bottom_track_17\/FTB_11__41:A I *L 0.001746 *C 67.160 53.040 +*I mux_bottom_track_17\/mux_l3_in_0_:S I *L 0.008363 *C 75.440 50.545 +*N mux_tree_tapbuf_size5_3_sram[2]:3 *C 67.160 53.040 +*N mux_tree_tapbuf_size5_3_sram[2]:4 *C 67.160 52.995 +*N mux_tree_tapbuf_size5_3_sram[2]:5 *C 67.160 50.705 +*N mux_tree_tapbuf_size5_3_sram[2]:6 *C 67.205 50.660 +*N mux_tree_tapbuf_size5_3_sram[2]:7 *C 75.440 50.545 +*N mux_tree_tapbuf_size5_3_sram[2]:8 *C 75.440 50.660 +*N mux_tree_tapbuf_size5_3_sram[2]:9 *C 75.440 50.705 +*N mux_tree_tapbuf_size5_3_sram[2]:10 *C 75.440 52.995 +*N mux_tree_tapbuf_size5_3_sram[2]:11 *C 75.440 53.040 +*N mux_tree_tapbuf_size5_3_sram[2]:12 *C 75.745 53.040 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_17\/FTB_11__41:A 1e-06 +2 mux_bottom_track_17\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_3_sram[2]:3 3.59225e-05 +4 mux_tree_tapbuf_size5_3_sram[2]:4 0.0001256123 +5 mux_tree_tapbuf_size5_3_sram[2]:5 0.0001256123 +6 mux_tree_tapbuf_size5_3_sram[2]:6 0.0004037745 +7 mux_tree_tapbuf_size5_3_sram[2]:7 0.0004201868 +8 mux_tree_tapbuf_size5_3_sram[2]:8 1.641225e-05 +9 mux_tree_tapbuf_size5_3_sram[2]:9 0.0001734944 +10 mux_tree_tapbuf_size5_3_sram[2]:10 0.0001734944 +11 mux_tree_tapbuf_size5_3_sram[2]:11 6.068957e-05 +12 mux_tree_tapbuf_size5_3_sram[2]:12 5.623045e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_3_sram[2]:12 0.152 +1 mux_tree_tapbuf_size5_3_sram[2]:8 mux_tree_tapbuf_size5_3_sram[2]:7 4.503907e-05 +2 mux_tree_tapbuf_size5_3_sram[2]:9 mux_tree_tapbuf_size5_3_sram[2]:8 0.0045 +3 mux_tree_tapbuf_size5_3_sram[2]:11 mux_tree_tapbuf_size5_3_sram[2]:10 0.0045 +4 mux_tree_tapbuf_size5_3_sram[2]:10 mux_tree_tapbuf_size5_3_sram[2]:9 0.002044643 +5 mux_tree_tapbuf_size5_3_sram[2]:12 mux_tree_tapbuf_size5_3_sram[2]:11 0.0001657609 +6 mux_tree_tapbuf_size5_3_sram[2]:6 mux_tree_tapbuf_size5_3_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size5_3_sram[2]:5 mux_tree_tapbuf_size5_3_sram[2]:4 0.002044643 +8 mux_tree_tapbuf_size5_3_sram[2]:3 mem_bottom_track_17\/FTB_11__41:A 0.152 +9 mux_tree_tapbuf_size5_3_sram[2]:4 mux_tree_tapbuf_size5_3_sram[2]:3 0.0045 +10 mux_tree_tapbuf_size5_3_sram[2]:7 mux_tree_tapbuf_size5_3_sram[2]:6 0.007352411 +11 mux_tree_tapbuf_size5_3_sram[2]:7 mux_bottom_track_17\/mux_l3_in_0_:S 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[1] 0.001835262 //LENGTH 15.155 LUMPCC 0.0003334181 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 89.085 96.560 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 87.300 90.780 +*I mux_right_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 91.440 90.830 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 91.715 93.500 +*N mux_tree_tapbuf_size6_3_sram[1]:4 *C 91.715 93.500 +*N mux_tree_tapbuf_size6_3_sram[1]:5 *C 91.540 93.500 +*N mux_tree_tapbuf_size6_3_sram[1]:6 *C 91.540 93.455 +*N mux_tree_tapbuf_size6_3_sram[1]:7 *C 91.440 90.830 +*N mux_tree_tapbuf_size6_3_sram[1]:8 *C 91.540 90.825 +*N mux_tree_tapbuf_size6_3_sram[1]:9 *C 87.338 90.780 +*N mux_tree_tapbuf_size6_3_sram[1]:10 *C 89.655 90.780 +*N mux_tree_tapbuf_size6_3_sram[1]:11 *C 89.700 90.780 +*N mux_tree_tapbuf_size6_3_sram[1]:12 *C 89.700 96.515 +*N mux_tree_tapbuf_size6_3_sram[1]:13 *C 89.655 96.560 +*N mux_tree_tapbuf_size6_3_sram[1]:14 *C 89.123 96.560 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +2 mux_right_track_0\/mux_l2_in_1_:S 1e-06 +3 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_3_sram[1]:4 4.957366e-05 +5 mux_tree_tapbuf_size6_3_sram[1]:5 5.447469e-05 +6 mux_tree_tapbuf_size6_3_sram[1]:6 0.0001563646 +7 mux_tree_tapbuf_size6_3_sram[1]:7 2.824464e-05 +8 mux_tree_tapbuf_size6_3_sram[1]:8 0.0002467954 +9 mux_tree_tapbuf_size6_3_sram[1]:9 4.838288e-05 +10 mux_tree_tapbuf_size6_3_sram[1]:10 4.838288e-05 +11 mux_tree_tapbuf_size6_3_sram[1]:11 0.0004146424 +12 mux_tree_tapbuf_size6_3_sram[1]:12 0.0003242116 +13 mux_tree_tapbuf_size6_3_sram[1]:13 6.338544e-05 +14 mux_tree_tapbuf_size6_3_sram[1]:14 6.338544e-05 +15 mux_tree_tapbuf_size6_3_sram[1]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.950755e-05 +16 mux_tree_tapbuf_size6_3_sram[1]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.000363e-06 +17 mux_tree_tapbuf_size6_3_sram[1]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.20436e-06 +18 mux_tree_tapbuf_size6_3_sram[1]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.950755e-05 +19 mux_tree_tapbuf_size6_3_sram[1]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.20436e-06 +20 mux_tree_tapbuf_size6_3_sram[1]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.785729e-08 +21 mux_tree_tapbuf_size6_3_sram[1]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.785729e-08 +22 mux_tree_tapbuf_size6_3_sram[1]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.000363e-06 +23 mux_tree_tapbuf_size6_3_sram[1]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.84798e-05 +24 mux_tree_tapbuf_size6_3_sram[1]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.043911e-05 +25 mux_tree_tapbuf_size6_3_sram[1]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.84798e-05 +26 mux_tree_tapbuf_size6_3_sram[1]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.043911e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_3_sram[1]:14 0.152 +1 mux_tree_tapbuf_size6_3_sram[1]:10 mux_tree_tapbuf_size6_3_sram[1]:9 0.002069196 +2 mux_tree_tapbuf_size6_3_sram[1]:11 mux_tree_tapbuf_size6_3_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size6_3_sram[1]:11 mux_tree_tapbuf_size6_3_sram[1]:8 0.001642857 +4 mux_tree_tapbuf_size6_3_sram[1]:9 mux_right_track_0\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_3_sram[1]:13 mux_tree_tapbuf_size6_3_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size6_3_sram[1]:12 mux_tree_tapbuf_size6_3_sram[1]:11 0.005120536 +7 mux_tree_tapbuf_size6_3_sram[1]:14 mux_tree_tapbuf_size6_3_sram[1]:13 0.0004754464 +8 mux_tree_tapbuf_size6_3_sram[1]:5 mux_tree_tapbuf_size6_3_sram[1]:4 9.51087e-05 +9 mux_tree_tapbuf_size6_3_sram[1]:6 mux_tree_tapbuf_size6_3_sram[1]:5 0.0045 +10 mux_tree_tapbuf_size6_3_sram[1]:4 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size6_3_sram[1]:7 mux_right_track_0\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size6_3_sram[1]:8 mux_tree_tapbuf_size6_3_sram[1]:7 0.0045 +13 mux_tree_tapbuf_size6_3_sram[1]:8 mux_tree_tapbuf_size6_3_sram[1]:6 0.002348214 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[0] 0.005836109 //LENGTH 41.940 LUMPCC 0.001343731 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 64.705 107.780 +*I mux_right_track_6\/mux_l1_in_3_:S I *L 0.00357 *C 63.840 110.160 +*I mux_right_track_6\/mux_l1_in_2_:S I *L 0.00357 *C 66.800 112.880 +*I mux_right_track_6\/mux_l1_in_1_:S I *L 0.00357 *C 67.720 117.640 +*I mux_right_track_6\/mux_l1_in_0_:S I *L 0.00357 *C 63.840 123.420 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.475 118.660 +*N mux_tree_tapbuf_size7_2_sram[0]:6 *C 48.475 118.660 +*N mux_tree_tapbuf_size7_2_sram[0]:7 *C 48.760 118.660 +*N mux_tree_tapbuf_size7_2_sram[0]:8 *C 48.760 118.660 +*N mux_tree_tapbuf_size7_2_sram[0]:9 *C 48.760 119.000 +*N mux_tree_tapbuf_size7_2_sram[0]:10 *C 48.768 119.000 +*N mux_tree_tapbuf_size7_2_sram[0]:11 *C 63.825 123.420 +*N mux_tree_tapbuf_size7_2_sram[0]:12 *C 63.503 123.420 +*N mux_tree_tapbuf_size7_2_sram[0]:13 *C 63.480 123.375 +*N mux_tree_tapbuf_size7_2_sram[0]:14 *C 63.480 119.058 +*N mux_tree_tapbuf_size7_2_sram[0]:15 *C 63.480 119.000 +*N mux_tree_tapbuf_size7_2_sram[0]:16 *C 65.312 119.000 +*N mux_tree_tapbuf_size7_2_sram[0]:17 *C 65.320 118.943 +*N mux_tree_tapbuf_size7_2_sram[0]:18 *C 67.683 117.640 +*N mux_tree_tapbuf_size7_2_sram[0]:19 *C 65.365 117.640 +*N mux_tree_tapbuf_size7_2_sram[0]:20 *C 65.320 117.640 +*N mux_tree_tapbuf_size7_2_sram[0]:21 *C 66.763 112.880 +*N mux_tree_tapbuf_size7_2_sram[0]:22 *C 65.365 112.880 +*N mux_tree_tapbuf_size7_2_sram[0]:23 *C 65.320 112.880 +*N mux_tree_tapbuf_size7_2_sram[0]:24 *C 65.320 109.820 +*N mux_tree_tapbuf_size7_2_sram[0]:25 *C 63.878 110.160 +*N mux_tree_tapbuf_size7_2_sram[0]:26 *C 64.860 110.160 +*N mux_tree_tapbuf_size7_2_sram[0]:27 *C 64.860 109.820 +*N mux_tree_tapbuf_size7_2_sram[0]:28 *C 64.860 109.820 +*N mux_tree_tapbuf_size7_2_sram[0]:29 *C 64.860 107.825 +*N mux_tree_tapbuf_size7_2_sram[0]:30 *C 64.860 107.780 +*N mux_tree_tapbuf_size7_2_sram[0]:31 *C 64.705 107.780 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_6\/mux_l1_in_3_:S 1e-06 +2 mux_right_track_6\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_6\/mux_l1_in_1_:S 1e-06 +4 mux_right_track_6\/mux_l1_in_0_:S 1e-06 +5 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_2_sram[0]:6 5.235098e-05 +7 mux_tree_tapbuf_size7_2_sram[0]:7 5.442045e-05 +8 mux_tree_tapbuf_size7_2_sram[0]:8 5.238452e-05 +9 mux_tree_tapbuf_size7_2_sram[0]:9 5.627495e-05 +10 mux_tree_tapbuf_size7_2_sram[0]:10 0.0006873445 +11 mux_tree_tapbuf_size7_2_sram[0]:11 4.645266e-05 +12 mux_tree_tapbuf_size7_2_sram[0]:12 4.645266e-05 +13 mux_tree_tapbuf_size7_2_sram[0]:13 0.0002720804 +14 mux_tree_tapbuf_size7_2_sram[0]:14 0.0002720804 +15 mux_tree_tapbuf_size7_2_sram[0]:15 0.0007800993 +16 mux_tree_tapbuf_size7_2_sram[0]:16 9.275488e-05 +17 mux_tree_tapbuf_size7_2_sram[0]:17 6.98003e-05 +18 mux_tree_tapbuf_size7_2_sram[0]:18 0.0001887196 +19 mux_tree_tapbuf_size7_2_sram[0]:19 0.0001887196 +20 mux_tree_tapbuf_size7_2_sram[0]:20 0.0002742405 +21 mux_tree_tapbuf_size7_2_sram[0]:21 9.994094e-05 +22 mux_tree_tapbuf_size7_2_sram[0]:22 9.994094e-05 +23 mux_tree_tapbuf_size7_2_sram[0]:23 0.0003492683 +24 mux_tree_tapbuf_size7_2_sram[0]:24 0.000180741 +25 mux_tree_tapbuf_size7_2_sram[0]:25 7.575338e-05 +26 mux_tree_tapbuf_size7_2_sram[0]:26 0.0001018604 +27 mux_tree_tapbuf_size7_2_sram[0]:27 5.589442e-05 +28 mux_tree_tapbuf_size7_2_sram[0]:28 0.0001635641 +29 mux_tree_tapbuf_size7_2_sram[0]:29 0.0001325908 +30 mux_tree_tapbuf_size7_2_sram[0]:30 4.831948e-05 +31 mux_tree_tapbuf_size7_2_sram[0]:31 4.43277e-05 +32 mux_tree_tapbuf_size7_2_sram[0]:15 right_top_grid_pin_43_[0]:20 4.415236e-05 +33 mux_tree_tapbuf_size7_2_sram[0]:15 right_top_grid_pin_43_[0]:21 0.0003103371 +34 mux_tree_tapbuf_size7_2_sram[0]:10 right_top_grid_pin_43_[0]:20 0.0003103371 +35 mux_tree_tapbuf_size7_2_sram[0]:16 right_top_grid_pin_43_[0]:21 4.415236e-05 +36 mux_tree_tapbuf_size7_2_sram[0]:15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002162253 +37 mux_tree_tapbuf_size7_2_sram[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002162253 +38 mux_tree_tapbuf_size7_2_sram[0]:13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.500611e-08 +39 mux_tree_tapbuf_size7_2_sram[0]:14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.500611e-08 +40 mux_tree_tapbuf_size7_2_sram[0]:17 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.390869e-05 +41 mux_tree_tapbuf_size7_2_sram[0]:25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.792479e-06 +42 mux_tree_tapbuf_size7_2_sram[0]:23 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.987703e-05 +43 mux_tree_tapbuf_size7_2_sram[0]:23 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.55178e-05 +44 mux_tree_tapbuf_size7_2_sram[0]:20 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.55178e-05 +45 mux_tree_tapbuf_size7_2_sram[0]:20 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.390869e-05 +46 mux_tree_tapbuf_size7_2_sram[0]:26 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.792479e-06 +47 mux_tree_tapbuf_size7_2_sram[0]:24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.987703e-05 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_2_sram[0]:31 0.152 +1 mux_tree_tapbuf_size7_2_sram[0]:11 mux_right_track_6\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[0]:12 mux_tree_tapbuf_size7_2_sram[0]:11 0.0001752718 +3 mux_tree_tapbuf_size7_2_sram[0]:13 mux_tree_tapbuf_size7_2_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:13 0.003854911 +5 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:14 0.00341 +6 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:10 0.002304958 +7 mux_tree_tapbuf_size7_2_sram[0]:9 mux_tree_tapbuf_size7_2_sram[0]:8 0.0001634615 +8 mux_tree_tapbuf_size7_2_sram[0]:10 mux_tree_tapbuf_size7_2_sram[0]:9 0.00341 +9 mux_tree_tapbuf_size7_2_sram[0]:7 mux_tree_tapbuf_size7_2_sram[0]:6 0.0001548913 +10 mux_tree_tapbuf_size7_2_sram[0]:8 mux_tree_tapbuf_size7_2_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size7_2_sram[0]:6 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size7_2_sram[0]:17 mux_tree_tapbuf_size7_2_sram[0]:16 0.00341 +13 mux_tree_tapbuf_size7_2_sram[0]:16 mux_tree_tapbuf_size7_2_sram[0]:15 0.0002870917 +14 mux_tree_tapbuf_size7_2_sram[0]:30 mux_tree_tapbuf_size7_2_sram[0]:29 0.0045 +15 mux_tree_tapbuf_size7_2_sram[0]:29 mux_tree_tapbuf_size7_2_sram[0]:28 0.00178125 +16 mux_tree_tapbuf_size7_2_sram[0]:31 mux_tree_tapbuf_size7_2_sram[0]:30 8.423914e-05 +17 mux_tree_tapbuf_size7_2_sram[0]:27 mux_tree_tapbuf_size7_2_sram[0]:26 0.0003035715 +18 mux_tree_tapbuf_size7_2_sram[0]:28 mux_tree_tapbuf_size7_2_sram[0]:27 0.0045 +19 mux_tree_tapbuf_size7_2_sram[0]:28 mux_tree_tapbuf_size7_2_sram[0]:24 0.0004107143 +20 mux_tree_tapbuf_size7_2_sram[0]:25 mux_right_track_6\/mux_l1_in_3_:S 0.152 +21 mux_tree_tapbuf_size7_2_sram[0]:22 mux_tree_tapbuf_size7_2_sram[0]:21 0.001247768 +22 mux_tree_tapbuf_size7_2_sram[0]:23 mux_tree_tapbuf_size7_2_sram[0]:22 0.0045 +23 mux_tree_tapbuf_size7_2_sram[0]:23 mux_tree_tapbuf_size7_2_sram[0]:20 0.00425 +24 mux_tree_tapbuf_size7_2_sram[0]:21 mux_right_track_6\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:18 0.002069196 +26 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:19 0.0045 +27 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:17 0.001162947 +28 mux_tree_tapbuf_size7_2_sram[0]:18 mux_right_track_6\/mux_l1_in_1_:S 0.152 +29 mux_tree_tapbuf_size7_2_sram[0]:26 mux_tree_tapbuf_size7_2_sram[0]:25 0.0008772322 +30 mux_tree_tapbuf_size7_2_sram[0]:24 mux_tree_tapbuf_size7_2_sram[0]:23 0.002732143 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008239333 //LENGTH 5.880 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_0_:X O *L 0 *C 74.235 44.880 +*I mux_bottom_track_17\/mux_l3_in_0_:A1 I *L 0.005458 *C 74.520 50.150 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 74.520 50.105 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 74.520 44.925 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 74.520 44.880 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 74.235 44.880 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003452808 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003452808 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.502164e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.635008e-05 + +*RES +0 mux_bottom_track_17\/mux_l2_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001548913 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004625 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A1 0.0045 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00102002 //LENGTH 8.540 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 53.075 104.720 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 45.445 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 45.483 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 46.000 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 46.000 104.720 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 53.038 104.720 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.198722e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.642764e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004470227 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004225823 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006283483 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004620536 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008201521 //LENGTH 6.495 LUMPCC 0 DR + +*CONN +*I mux_right_track_14\/mux_l1_in_0_:X O *L 0 *C 75.265 93.500 +*I mux_right_track_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 78.300 90.780 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 78.263 90.780 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.485 90.780 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 75.440 90.825 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 75.440 93.455 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 75.440 93.500 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 75.265 93.500 + +*CAP +0 mux_right_track_14\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_14\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001960272 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001960272 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001582247 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001582247 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.483122e-05 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.481705e-05 + +*RES +0 mux_right_track_14\/mux_l1_in_0_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_14\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002479911 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348215 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003609291 //LENGTH 2.825 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 69.175 99.280 +*I mux_right_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 67.260 99.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 67.297 99.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 67.620 99.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 67.620 99.280 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 69.138 99.280 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.359423e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.898636e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001358703 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001104782 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001354911 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002879465 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004551254 //LENGTH 2.480 LUMPCC 0.0003614536 DR + +*CONN +*I mux_right_track_20\/mux_l1_in_1_:X O *L 0 *C 71.125 69.700 +*I mux_right_track_20\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.315 69.700 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 73.278 69.700 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 71.163 69.700 + +*CAP +0 mux_right_track_20\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_20\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.583588e-05 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.583588e-05 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_2_sram[1]:9 9.208119e-05 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_2_sram[1]:8 9.208119e-05 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 optlc_net_187:10 8.864562e-05 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 optlc_net_187:9 8.864562e-05 + +*RES +0 mux_right_track_20\/mux_l1_in_1_:X mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_20\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001888393 + +*END + +*D_NET ropt_net_241 0.0007884217 //LENGTH 7.090 LUMPCC 9.213308e-05 DR + +*CONN +*I ropt_mt_inst_817:X O *L 0 *C 107.180 52.360 +*I ropt_mt_inst_861:A I *L 0.001766 *C 106.260 55.760 +*N ropt_net_241:2 *C 106.297 55.760 +*N ropt_net_241:3 *C 108.055 55.760 +*N ropt_net_241:4 *C 108.100 55.715 +*N ropt_net_241:5 *C 108.100 52.405 +*N ropt_net_241:6 *C 108.055 52.360 +*N ropt_net_241:7 *C 107.218 52.360 + +*CAP +0 ropt_mt_inst_817:X 1e-06 +1 ropt_mt_inst_861:A 1e-06 +2 ropt_net_241:2 0.000115799 +3 ropt_net_241:3 0.000115799 +4 ropt_net_241:4 0.0001509337 +5 ropt_net_241:5 0.0001509337 +6 ropt_net_241:6 8.041154e-05 +7 ropt_net_241:7 8.041154e-05 +8 ropt_net_241:4 chanx_right_in[1]:12 4.606654e-05 +9 ropt_net_241:5 chanx_right_in[1]:11 4.606654e-05 + +*RES +0 ropt_mt_inst_817:X ropt_net_241:7 0.152 +1 ropt_net_241:2 ropt_mt_inst_861:A 0.152 +2 ropt_net_241:3 ropt_net_241:2 0.001569196 +3 ropt_net_241:4 ropt_net_241:3 0.0045 +4 ropt_net_241:6 ropt_net_241:5 0.0045 +5 ropt_net_241:5 ropt_net_241:4 0.002955357 +6 ropt_net_241:7 ropt_net_241:6 0.0007477679 + +*END + +*D_NET ropt_net_225 0.001353925 //LENGTH 9.385 LUMPCC 0.0006323524 DR + +*CONN +*I ropt_mt_inst_837:X O *L 0 *C 60.455 124.100 +*I ropt_mt_inst_845:A I *L 0.001767 *C 51.980 123.760 +*N ropt_net_225:2 *C 52.018 123.760 +*N ropt_net_225:3 *C 52.900 123.760 +*N ropt_net_225:4 *C 52.900 124.100 +*N ropt_net_225:5 *C 60.418 124.100 + +*CAP +0 ropt_mt_inst_837:X 1e-06 +1 ropt_mt_inst_845:A 1e-06 +2 ropt_net_225:2 4.240532e-05 +3 ropt_net_225:3 6.749498e-05 +4 ropt_net_225:4 0.0003173812 +5 ropt_net_225:5 0.0002922915 +6 ropt_net_225:2 chany_top_in[3]:3 3.878732e-05 +7 ropt_net_225:5 chany_top_in[3]:2 7.209439e-05 +8 ropt_net_225:3 chany_top_in[3]:2 3.878732e-05 +9 ropt_net_225:4 chany_top_in[3]:3 7.209439e-05 +10 ropt_net_225:5 ropt_net_216:2 9.401386e-05 +11 ropt_net_225:4 ropt_net_216:3 9.401386e-05 +12 ropt_net_225:2 chany_top_out[11]:8 2.883896e-06 +13 ropt_net_225:5 chany_top_out[11]:7 0.0001083967 +14 ropt_net_225:3 chany_top_out[11]:7 2.883896e-06 +15 ropt_net_225:4 chany_top_out[11]:8 0.0001083967 + +*RES +0 ropt_mt_inst_837:X ropt_net_225:5 0.152 +1 ropt_net_225:2 ropt_mt_inst_845:A 0.152 +2 ropt_net_225:5 ropt_net_225:4 0.006712054 +3 ropt_net_225:3 ropt_net_225:2 0.0007879465 +4 ropt_net_225:4 ropt_net_225:3 0.0003035715 + +*END + +*D_NET chany_bottom_out[7] 0.001437283 //LENGTH 11.500 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_860:X O *L 0 *C 74.255 6.120 +*P chany_bottom_out[7] O *L 0.7423 *C 68.540 1.290 +*N chany_bottom_out[7]:2 *C 68.540 1.983 +*N chany_bottom_out[7]:3 *C 68.547 2.040 +*N chany_bottom_out[7]:4 *C 74.053 2.040 +*N chany_bottom_out[7]:5 *C 74.060 2.098 +*N chany_bottom_out[7]:6 *C 74.060 6.075 +*N chany_bottom_out[7]:7 *C 74.060 6.120 +*N chany_bottom_out[7]:8 *C 74.255 6.120 + +*CAP +0 ropt_mt_inst_860:X 1e-06 +1 chany_bottom_out[7] 5.836595e-05 +2 chany_bottom_out[7]:2 5.836595e-05 +3 chany_bottom_out[7]:3 0.000373658 +4 chany_bottom_out[7]:4 0.000373658 +5 chany_bottom_out[7]:5 0.0002331055 +6 chany_bottom_out[7]:6 0.0002331055 +7 chany_bottom_out[7]:7 5.215043e-05 +8 chany_bottom_out[7]:8 5.387332e-05 + +*RES +0 ropt_mt_inst_860:X chany_bottom_out[7]:8 0.152 +1 chany_bottom_out[7]:8 chany_bottom_out[7]:7 0.0001059783 +2 chany_bottom_out[7]:7 chany_bottom_out[7]:6 0.0045 +3 chany_bottom_out[7]:6 chany_bottom_out[7]:5 0.003551339 +4 chany_bottom_out[7]:5 chany_bottom_out[7]:4 0.00341 +5 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.00086245 +6 chany_bottom_out[7]:2 chany_bottom_out[7] 0.0006183035 +7 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.00341 + +*END + +*D_NET chany_top_in[13] 0.03063827 //LENGTH 238.375 LUMPCC 0.008526038 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 20.240 129.350 +*I mux_right_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 85.200 79.900 +*I mux_bottom_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 67.335 42.840 +*I ropt_mt_inst_821:A I *L 0.001767 *C 41.860 4.080 +*N chany_top_in[13]:4 *C 41.883 4.107 +*N chany_top_in[13]:5 *C 41.895 4.420 +*N chany_top_in[13]:6 *C 45.955 4.420 +*N chany_top_in[13]:7 *C 46.000 4.465 +*N chany_top_in[13]:8 *C 46.000 23.062 +*N chany_top_in[13]:9 *C 46.008 23.120 +*N chany_top_in[13]:10 *C 55.653 23.120 +*N chany_top_in[13]:11 *C 55.660 23.178 +*N chany_top_in[13]:12 *C 55.660 30.895 +*N chany_top_in[13]:13 *C 55.705 30.940 +*N chany_top_in[13]:14 *C 65.275 30.940 +*N chany_top_in[13]:15 *C 65.320 30.985 +*N chany_top_in[13]:16 *C 65.320 40.742 +*N chany_top_in[13]:17 *C 65.328 40.800 +*N chany_top_in[13]:18 *C 67.153 40.800 +*N chany_top_in[13]:19 *C 67.160 40.858 +*N chany_top_in[13]:20 *C 67.335 42.840 +*N chany_top_in[13]:21 *C 67.160 42.840 +*N chany_top_in[13]:22 *C 67.160 42.840 +*N chany_top_in[13]:23 *C 67.168 42.840 +*N chany_top_in[13]:24 *C 84.620 42.840 +*N chany_top_in[13]:25 *C 84.640 42.848 +*N chany_top_in[13]:26 *C 84.640 74.793 +*N chany_top_in[13]:27 *C 84.655 74.800 +*N chany_top_in[13]:28 *C 85.098 74.800 +*N chany_top_in[13]:29 *C 85.100 74.858 +*N chany_top_in[13]:30 *C 85.100 79.900 +*N chany_top_in[13]:31 *C 85.100 79.855 +*N chany_top_in[13]:32 *C 85.100 80.240 +*N chany_top_in[13]:33 *C 85.093 80.240 +*N chany_top_in[13]:34 *C 70.050 80.240 +*N chany_top_in[13]:35 *C 20.260 80.240 +*N chany_top_in[13]:36 *C 20.240 80.248 + +*CAP +0 chany_top_in[13] 0.001677536 +1 mux_right_track_16\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:A0 1e-06 +3 ropt_mt_inst_821:A 1e-06 +4 chany_top_in[13]:4 3.136034e-05 +5 chany_top_in[13]:5 0.0003533956 +6 chany_top_in[13]:6 0.0003220353 +7 chany_top_in[13]:7 0.001024452 +8 chany_top_in[13]:8 0.001024452 +9 chany_top_in[13]:9 0.0004346797 +10 chany_top_in[13]:10 0.0004346797 +11 chany_top_in[13]:11 0.0004480869 +12 chany_top_in[13]:12 0.0004480869 +13 chany_top_in[13]:13 0.0005208495 +14 chany_top_in[13]:14 0.0005208495 +15 chany_top_in[13]:15 0.0004762999 +16 chany_top_in[13]:16 0.0004762999 +17 chany_top_in[13]:17 0.0001915438 +18 chany_top_in[13]:18 0.0001915438 +19 chany_top_in[13]:19 0.0001326233 +20 chany_top_in[13]:20 5.987852e-05 +21 chany_top_in[13]:21 6.130737e-05 +22 chany_top_in[13]:22 0.0001679096 +23 chany_top_in[13]:23 0.0009720803 +24 chany_top_in[13]:24 0.0009720803 +25 chany_top_in[13]:25 0.00159615 +26 chany_top_in[13]:26 0.00159615 +27 chany_top_in[13]:27 5.278243e-05 +28 chany_top_in[13]:28 5.278243e-05 +29 chany_top_in[13]:29 0.0002797021 +30 chany_top_in[13]:30 3.339681e-05 +31 chany_top_in[13]:31 0.0002985313 +32 chany_top_in[13]:32 5.462055e-05 +33 chany_top_in[13]:33 0.0004590742 +34 chany_top_in[13]:34 0.002762776 +35 chany_top_in[13]:35 0.002303703 +36 chany_top_in[13]:36 0.001677536 +37 chany_top_in[13] chany_top_in[17] 0.000344399 +38 chany_top_in[13]:18 chany_top_in[17]:14 1.222661e-05 +39 chany_top_in[13]:17 chany_top_in[17]:23 1.222661e-05 +40 chany_top_in[13]:24 chany_top_in[17]:14 6.872403e-06 +41 chany_top_in[13]:23 chany_top_in[17]:23 6.872403e-06 +42 chany_top_in[13]:35 chany_top_in[17]:9 0.0004661058 +43 chany_top_in[13]:36 chany_top_in[17]:28 0.000344399 +44 chany_top_in[13]:34 chany_top_in[17]:8 0.0004661058 +45 chany_top_in[13]:10 chany_bottom_in[1]:14 0.0005339 +46 chany_top_in[13]:9 chany_bottom_in[1]:15 0.0005339 +47 chany_top_in[13]:26 chany_bottom_in[4]:32 1.922283e-05 +48 chany_top_in[13]:26 chany_bottom_in[4]:25 0.0002805097 +49 chany_top_in[13]:25 chany_bottom_in[4]:32 0.0002805097 +50 chany_top_in[13]:25 chany_bottom_in[4]:33 1.922283e-05 +51 chany_top_in[13]:14 prog_clk[0]:440 4.016729e-05 +52 chany_top_in[13]:13 prog_clk[0]:439 4.016729e-05 +53 chany_top_in[13]:8 prog_clk[0]:416 4.679944e-06 +54 chany_top_in[13]:7 prog_clk[0]:415 4.679944e-06 +55 chany_top_in[13]:24 prog_clk[0]:161 1.026091e-05 +56 chany_top_in[13]:24 prog_clk[0]:157 8.888457e-05 +57 chany_top_in[13]:24 prog_clk[0]:138 5.180071e-05 +58 chany_top_in[13]:24 prog_clk[0]:146 3.06212e-06 +59 chany_top_in[13]:23 prog_clk[0]:161 3.06212e-06 +60 chany_top_in[13]:23 prog_clk[0]:162 1.026091e-05 +61 chany_top_in[13]:23 prog_clk[0]:139 5.180071e-05 +62 chany_top_in[13]:23 prog_clk[0]:158 8.888457e-05 +63 chany_top_in[13]:35 prog_clk[0]:381 7.727923e-05 +64 chany_top_in[13]:35 prog_clk[0]:361 1.748409e-05 +65 chany_top_in[13]:35 prog_clk[0]:292 6.312533e-05 +66 chany_top_in[13]:34 prog_clk[0]:380 7.727923e-05 +67 chany_top_in[13]:34 prog_clk[0]:360 1.748409e-05 +68 chany_top_in[13]:34 prog_clk[0]:291 6.312533e-05 +69 chany_top_in[13]:33 chanx_right_in[14]:12 0.000817471 +70 chany_top_in[13]:35 chanx_right_in[14]:11 0.0006230451 +71 chany_top_in[13]:34 chanx_right_in[14]:11 0.000817471 +72 chany_top_in[13]:34 chanx_right_in[14]:12 0.0006230451 +73 chany_top_in[13]:24 mux_tree_tapbuf_size6_6_sram[0]:25 0.0001145646 +74 chany_top_in[13]:24 mux_tree_tapbuf_size6_6_sram[0]:15 0.0001697198 +75 chany_top_in[13]:23 mux_tree_tapbuf_size6_6_sram[0]:24 0.0001145646 +76 chany_top_in[13]:23 mux_tree_tapbuf_size6_6_sram[0]:16 0.0001697198 +77 chany_top_in[13]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.941746e-05 +78 chany_top_in[13]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.941746e-05 +79 chany_top_in[13]:33 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003083023 +80 chany_top_in[13]:35 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001405179 +81 chany_top_in[13]:34 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003083023 +82 chany_top_in[13]:34 mux_right_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001405179 + +*RES +0 chany_top_in[13] chany_top_in[13]:36 0.007692724 +1 chany_top_in[13]:30 mux_right_track_16\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[13]:31 chany_top_in[13]:30 0.0045 +3 chany_top_in[13]:31 chany_top_in[13]:29 0.004462054 +4 chany_top_in[13]:19 chany_top_in[13]:18 0.00341 +5 chany_top_in[13]:18 chany_top_in[13]:17 0.0002859167 +6 chany_top_in[13]:16 chany_top_in[13]:15 0.008712054 +7 chany_top_in[13]:17 chany_top_in[13]:16 0.00341 +8 chany_top_in[13]:14 chany_top_in[13]:13 0.008544643 +9 chany_top_in[13]:15 chany_top_in[13]:14 0.0045 +10 chany_top_in[13]:13 chany_top_in[13]:12 0.0045 +11 chany_top_in[13]:12 chany_top_in[13]:11 0.006890626 +12 chany_top_in[13]:11 chany_top_in[13]:10 0.00341 +13 chany_top_in[13]:10 chany_top_in[13]:9 0.00151105 +14 chany_top_in[13]:8 chany_top_in[13]:7 0.01660491 +15 chany_top_in[13]:9 chany_top_in[13]:8 0.00341 +16 chany_top_in[13]:6 chany_top_in[13]:5 0.003625 +17 chany_top_in[13]:7 chany_top_in[13]:6 0.0045 +18 chany_top_in[13]:4 ropt_mt_inst_821:A 0.152 +19 chany_top_in[13]:29 chany_top_in[13]:28 0.00341 +20 chany_top_in[13]:28 chany_top_in[13]:27 6.499219e-05 +21 chany_top_in[13]:27 chany_top_in[13]:26 0.00341 +22 chany_top_in[13]:26 chany_top_in[13]:25 0.005004717 +23 chany_top_in[13]:24 chany_top_in[13]:23 0.002734225 +24 chany_top_in[13]:25 chany_top_in[13]:24 0.00341 +25 chany_top_in[13]:22 chany_top_in[13]:21 0.0045 +26 chany_top_in[13]:22 chany_top_in[13]:19 0.001770089 +27 chany_top_in[13]:23 chany_top_in[13]:22 0.00341 +28 chany_top_in[13]:21 chany_top_in[13]:20 9.51087e-05 +29 chany_top_in[13]:20 mux_bottom_track_3\/mux_l1_in_0_:A0 0.152 +30 chany_top_in[13]:32 chany_top_in[13]:31 0.0001850962 +31 chany_top_in[13]:33 chany_top_in[13]:32 0.00341 +32 chany_top_in[13]:35 chany_top_in[13]:34 0.007800432 +33 chany_top_in[13]:36 chany_top_in[13]:35 0.00341 +34 chany_top_in[13]:5 chany_top_in[13]:4 0.0002111487 +35 chany_top_in[13]:34 chany_top_in[13]:33 0.002356658 + +*END + +*D_NET chany_top_out[1] 0.002342417 //LENGTH 22.520 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 33.525 115.260 +*P chany_top_out[1] O *L 0.7423 *C 25.760 129.270 +*N chany_top_out[1]:2 *C 25.760 127.160 +*N chany_top_out[1]:3 *C 26.220 127.160 +*N chany_top_out[1]:4 *C 26.220 115.305 +*N chany_top_out[1]:5 *C 26.265 115.260 +*N chany_top_out[1]:6 *C 33.488 115.260 + +*CAP +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[1] 0.000123245 +2 chany_top_out[1]:2 0.000148613 +3 chany_top_out[1]:3 0.0006426416 +4 chany_top_out[1]:4 0.0006172735 +5 chany_top_out[1]:5 0.0004048219 +6 chany_top_out[1]:6 0.0004048219 + +*RES +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[1]:6 0.152 +1 chany_top_out[1]:6 chany_top_out[1]:5 0.006448661 +2 chany_top_out[1]:5 chany_top_out[1]:4 0.0045 +3 chany_top_out[1]:4 chany_top_out[1]:3 0.01058482 +4 chany_top_out[1]:2 chany_top_out[1] 0.001883928 +5 chany_top_out[1]:3 chany_top_out[1]:2 0.0004107143 + +*END + +*D_NET chanx_right_out[3] 0.002725189 //LENGTH 25.605 LUMPCC 0 DR + +*CONN +*I mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.480 91.460 +*P chanx_right_out[3] O *L 0.7423 *C 111.930 74.120 +*N chanx_right_out[3]:2 *C 109.948 74.120 +*N chanx_right_out[3]:3 *C 109.940 74.178 +*N chanx_right_out[3]:4 *C 109.940 91.415 +*N chanx_right_out[3]:5 *C 109.895 91.460 +*N chanx_right_out[3]:6 *C 104.517 91.460 + +*CAP +0 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[3] 0.0001302466 +2 chanx_right_out[3]:2 0.0001302466 +3 chanx_right_out[3]:3 0.0009301004 +4 chanx_right_out[3]:4 0.0009301004 +5 chanx_right_out[3]:5 0.0003017473 +6 chanx_right_out[3]:6 0.0003017473 + +*RES +0 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:6 chanx_right_out[3]:5 0.004801339 +2 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +3 chanx_right_out[3]:4 chanx_right_out[3]:3 0.01539063 +4 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +5 chanx_right_out[3]:2 chanx_right_out[3] 0.0003105917 + +*END + +*D_NET chanx_right_out[11] 0.001088429 //LENGTH 7.770 LUMPCC 0 DR + +*CONN +*I mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 106.260 80.240 +*P chanx_right_out[11] O *L 0.7423 *C 111.855 78.880 +*N chanx_right_out[11]:2 *C 108.108 78.880 +*N chanx_right_out[11]:3 *C 108.100 78.938 +*N chanx_right_out[11]:4 *C 108.100 80.195 +*N chanx_right_out[11]:5 *C 108.055 80.240 +*N chanx_right_out[11]:6 *C 106.297 80.240 + +*CAP +0 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[11] 0.0003353521 +2 chanx_right_out[11]:2 0.0003353521 +3 chanx_right_out[11]:3 9.376249e-05 +4 chanx_right_out[11]:4 9.376249e-05 +5 chanx_right_out[11]:5 0.0001145998 +6 chanx_right_out[11]:6 0.0001145998 + +*RES +0 mux_right_track_22\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[11]:6 0.152 +1 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +2 chanx_right_out[11]:2 chanx_right_out[11] 0.0005871083 +3 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +4 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001122768 +5 chanx_right_out[11]:6 chanx_right_out[11]:5 0.001569196 + +*END + +*D_NET chany_bottom_out[2] 0.003118441 //LENGTH 28.455 LUMPCC 0.0003996111 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_0_:X O *L 0 *C 72.900 22.440 +*P chany_bottom_out[2] O *L 0.7423 *C 66.700 1.290 +*N chany_bottom_out[2]:2 *C 66.700 9.815 +*N chany_bottom_out[2]:3 *C 66.745 9.860 +*N chany_bottom_out[2]:4 *C 72.175 9.860 +*N chany_bottom_out[2]:5 *C 72.220 9.905 +*N chany_bottom_out[2]:6 *C 72.220 22.395 +*N chany_bottom_out[2]:7 *C 72.265 22.440 +*N chany_bottom_out[2]:8 *C 72.862 22.440 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_0_:X 1e-06 +1 chany_bottom_out[2] 0.0003937154 +2 chany_bottom_out[2]:2 0.0003937154 +3 chany_bottom_out[2]:3 0.0003661063 +4 chany_bottom_out[2]:4 0.0003661063 +5 chany_bottom_out[2]:5 0.0005393584 +6 chany_bottom_out[2]:6 0.0005393584 +7 chany_bottom_out[2]:7 5.973468e-05 +8 chany_bottom_out[2]:8 5.973468e-05 +9 chany_bottom_out[2] ropt_net_191:4 4.741859e-05 +10 chany_bottom_out[2]:2 ropt_net_191:5 4.741859e-05 +11 chany_bottom_out[2] mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.481876e-05 +12 chany_bottom_out[2]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001375682 +13 chany_bottom_out[2]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001375682 +14 chany_bottom_out[2]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.481876e-05 + +*RES +0 mux_bottom_track_5\/mux_l3_in_0_:X chany_bottom_out[2]:8 0.152 +1 chany_bottom_out[2]:8 chany_bottom_out[2]:7 0.0005334822 +2 chany_bottom_out[2]:7 chany_bottom_out[2]:6 0.0045 +3 chany_bottom_out[2]:6 chany_bottom_out[2]:5 0.01115179 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.004848214 +5 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.0045 +6 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +7 chany_bottom_out[2]:2 chany_bottom_out[2] 0.007611607 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001373299 //LENGTH 10.885 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 96.445 82.620 +*I mux_right_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 92.820 78.200 +*I mem_right_track_16\/FTB_23__53:A I *L 0.001746 *C 97.060 77.520 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 97.060 77.520 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 97.060 77.565 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 92.858 78.200 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 97.015 78.200 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 97.060 78.200 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 97.060 82.575 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 97.015 82.620 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 96.483 82.620 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_16\/FTB_23__53:A 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 3.675312e-05 +4 mux_tree_tapbuf_size3_0_sram[1]:4 4.368367e-05 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0003257655 +6 mux_tree_tapbuf_size3_0_sram[1]:6 0.0003257655 +7 mux_tree_tapbuf_size3_0_sram[1]:7 0.0003072747 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0002311044 +9 mux_tree_tapbuf_size3_0_sram[1]:9 4.997608e-05 +10 mux_tree_tapbuf_size3_0_sram[1]:10 4.997608e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:5 mux_right_track_16\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_0_sram[1]:6 mux_tree_tapbuf_size3_0_sram[1]:5 0.003712053 +3 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:4 0.0005669644 +5 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.00390625 +7 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.0004754465 +8 mux_tree_tapbuf_size3_0_sram[1]:3 mem_right_track_16\/FTB_23__53:A 0.152 +9 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[0] 0.004407563 //LENGTH 33.695 LUMPCC 0.0002632787 DR + +*CONN +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 70.685 75.140 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 55.375 75.140 +*I mux_right_track_22\/mux_l1_in_1_:S I *L 0.00357 *C 52.800 79.560 +*I mux_right_track_22\/mux_l1_in_0_:S I *L 0.00357 *C 63.120 79.950 +*N mux_tree_tapbuf_size3_3_sram[0]:4 *C 63.120 79.950 +*N mux_tree_tapbuf_size3_3_sram[0]:5 *C 52.800 79.560 +*N mux_tree_tapbuf_size3_3_sram[0]:6 *C 52.900 79.515 +*N mux_tree_tapbuf_size3_3_sram[0]:7 *C 55.375 75.140 +*N mux_tree_tapbuf_size3_3_sram[0]:8 *C 55.200 75.140 +*N mux_tree_tapbuf_size3_3_sram[0]:9 *C 55.200 75.185 +*N mux_tree_tapbuf_size3_3_sram[0]:10 *C 55.200 77.475 +*N mux_tree_tapbuf_size3_3_sram[0]:11 *C 55.155 77.520 +*N mux_tree_tapbuf_size3_3_sram[0]:12 *C 52.945 77.520 +*N mux_tree_tapbuf_size3_3_sram[0]:13 *C 52.900 77.565 +*N mux_tree_tapbuf_size3_3_sram[0]:14 *C 52.900 78.200 +*N mux_tree_tapbuf_size3_3_sram[0]:15 *C 52.945 78.200 +*N mux_tree_tapbuf_size3_3_sram[0]:16 *C 60.675 78.200 +*N mux_tree_tapbuf_size3_3_sram[0]:17 *C 60.720 78.245 +*N mux_tree_tapbuf_size3_3_sram[0]:18 *C 60.720 79.515 +*N mux_tree_tapbuf_size3_3_sram[0]:19 *C 60.765 79.560 +*N mux_tree_tapbuf_size3_3_sram[0]:20 *C 63.120 79.560 +*N mux_tree_tapbuf_size3_3_sram[0]:21 *C 68.955 79.560 +*N mux_tree_tapbuf_size3_3_sram[0]:22 *C 69.000 79.515 +*N mux_tree_tapbuf_size3_3_sram[0]:23 *C 69.000 75.185 +*N mux_tree_tapbuf_size3_3_sram[0]:24 *C 69.045 75.140 +*N mux_tree_tapbuf_size3_3_sram[0]:25 *C 70.648 75.140 + +*CAP +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_22\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_22\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_3_sram[0]:4 5.963352e-05 +5 mux_tree_tapbuf_size3_3_sram[0]:5 2.71136e-05 +6 mux_tree_tapbuf_size3_3_sram[0]:6 8.352573e-05 +7 mux_tree_tapbuf_size3_3_sram[0]:7 5.255272e-05 +8 mux_tree_tapbuf_size3_3_sram[0]:8 5.530194e-05 +9 mux_tree_tapbuf_size3_3_sram[0]:9 0.0001598935 +10 mux_tree_tapbuf_size3_3_sram[0]:10 0.0001598935 +11 mux_tree_tapbuf_size3_3_sram[0]:11 0.0001380983 +12 mux_tree_tapbuf_size3_3_sram[0]:12 0.0001380983 +13 mux_tree_tapbuf_size3_3_sram[0]:13 4.615896e-05 +14 mux_tree_tapbuf_size3_3_sram[0]:14 0.0001622286 +15 mux_tree_tapbuf_size3_3_sram[0]:15 0.000521069 +16 mux_tree_tapbuf_size3_3_sram[0]:16 0.000521069 +17 mux_tree_tapbuf_size3_3_sram[0]:17 7.435547e-05 +18 mux_tree_tapbuf_size3_3_sram[0]:18 7.435547e-05 +19 mux_tree_tapbuf_size3_3_sram[0]:19 0.0001427683 +20 mux_tree_tapbuf_size3_3_sram[0]:20 0.0005740783 +21 mux_tree_tapbuf_size3_3_sram[0]:21 0.0004006944 +22 mux_tree_tapbuf_size3_3_sram[0]:22 0.0002623688 +23 mux_tree_tapbuf_size3_3_sram[0]:23 0.0002623688 +24 mux_tree_tapbuf_size3_3_sram[0]:24 0.0001123287 +25 mux_tree_tapbuf_size3_3_sram[0]:25 0.0001123287 +26 mux_tree_tapbuf_size3_3_sram[0]:16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.197268e-05 +27 mux_tree_tapbuf_size3_3_sram[0]:15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.197268e-05 +28 mux_tree_tapbuf_size3_3_sram[0]:19 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.35123e-05 +29 mux_tree_tapbuf_size3_3_sram[0]:18 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.203413e-05 +30 mux_tree_tapbuf_size3_3_sram[0]:16 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.12025e-06 +31 mux_tree_tapbuf_size3_3_sram[0]:17 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.203413e-05 +32 mux_tree_tapbuf_size3_3_sram[0]:15 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.12025e-06 +33 mux_tree_tapbuf_size3_3_sram[0]:20 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.35123e-05 + +*RES +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_3_sram[0]:25 0.152 +1 mux_tree_tapbuf_size3_3_sram[0]:25 mux_tree_tapbuf_size3_3_sram[0]:24 0.001430803 +2 mux_tree_tapbuf_size3_3_sram[0]:24 mux_tree_tapbuf_size3_3_sram[0]:23 0.0045 +3 mux_tree_tapbuf_size3_3_sram[0]:23 mux_tree_tapbuf_size3_3_sram[0]:22 0.003866072 +4 mux_tree_tapbuf_size3_3_sram[0]:21 mux_tree_tapbuf_size3_3_sram[0]:20 0.005209822 +5 mux_tree_tapbuf_size3_3_sram[0]:22 mux_tree_tapbuf_size3_3_sram[0]:21 0.0045 +6 mux_tree_tapbuf_size3_3_sram[0]:12 mux_tree_tapbuf_size3_3_sram[0]:11 0.001973215 +7 mux_tree_tapbuf_size3_3_sram[0]:13 mux_tree_tapbuf_size3_3_sram[0]:12 0.0045 +8 mux_tree_tapbuf_size3_3_sram[0]:11 mux_tree_tapbuf_size3_3_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size3_3_sram[0]:10 mux_tree_tapbuf_size3_3_sram[0]:9 0.002044643 +10 mux_tree_tapbuf_size3_3_sram[0]:8 mux_tree_tapbuf_size3_3_sram[0]:7 9.51087e-05 +11 mux_tree_tapbuf_size3_3_sram[0]:9 mux_tree_tapbuf_size3_3_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size3_3_sram[0]:7 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size3_3_sram[0]:5 mux_right_track_22\/mux_l1_in_1_:S 0.152 +14 mux_tree_tapbuf_size3_3_sram[0]:6 mux_tree_tapbuf_size3_3_sram[0]:5 0.0045 +15 mux_tree_tapbuf_size3_3_sram[0]:4 mux_right_track_22\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size3_3_sram[0]:19 mux_tree_tapbuf_size3_3_sram[0]:18 0.0045 +17 mux_tree_tapbuf_size3_3_sram[0]:18 mux_tree_tapbuf_size3_3_sram[0]:17 0.001133929 +18 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:15 0.006901786 +19 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:16 0.0045 +20 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:14 0.0045 +21 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:13 0.0005669643 +22 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:6 0.001174107 +23 mux_tree_tapbuf_size3_3_sram[0]:20 mux_tree_tapbuf_size3_3_sram[0]:19 0.002102679 +24 mux_tree_tapbuf_size3_3_sram[0]:20 mux_tree_tapbuf_size3_3_sram[0]:4 0.0003482142 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[0] 0.002056335 //LENGTH 14.815 LUMPCC 0.0002885556 DR + +*CONN +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 37.105 99.280 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 31.455 96.900 +*I mux_right_track_10\/mux_l1_in_0_:S I *L 0.00357 *C 41.760 99.960 +*N mux_tree_tapbuf_size4_3_sram[0]:3 *C 41.723 99.960 +*N mux_tree_tapbuf_size4_3_sram[0]:4 *C 37.260 99.960 +*N mux_tree_tapbuf_size4_3_sram[0]:5 *C 31.493 96.900 +*N mux_tree_tapbuf_size4_3_sram[0]:6 *C 32.200 96.900 +*N mux_tree_tapbuf_size4_3_sram[0]:7 *C 32.200 97.240 +*N mux_tree_tapbuf_size4_3_sram[0]:8 *C 37.215 97.240 +*N mux_tree_tapbuf_size4_3_sram[0]:9 *C 37.260 97.285 +*N mux_tree_tapbuf_size4_3_sram[0]:10 *C 37.260 99.235 +*N mux_tree_tapbuf_size4_3_sram[0]:11 *C 37.260 99.280 +*N mux_tree_tapbuf_size4_3_sram[0]:12 *C 37.105 99.280 + +*CAP +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_10\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_3_sram[0]:3 0.0003239812 +4 mux_tree_tapbuf_size4_3_sram[0]:4 0.0003604263 +5 mux_tree_tapbuf_size4_3_sram[0]:5 6.520165e-05 +6 mux_tree_tapbuf_size4_3_sram[0]:6 8.919807e-05 +7 mux_tree_tapbuf_size4_3_sram[0]:7 0.0002837063 +8 mux_tree_tapbuf_size4_3_sram[0]:8 0.0002597099 +9 mux_tree_tapbuf_size4_3_sram[0]:9 0.0001265223 +10 mux_tree_tapbuf_size4_3_sram[0]:10 0.0001265223 +11 mux_tree_tapbuf_size4_3_sram[0]:11 8.510731e-05 +12 mux_tree_tapbuf_size4_3_sram[0]:12 4.440398e-05 +13 mux_tree_tapbuf_size4_3_sram[0]:8 mux_tree_tapbuf_size4_3_sram[1]:4 5.691974e-06 +14 mux_tree_tapbuf_size4_3_sram[0]:8 mux_tree_tapbuf_size4_3_sram[1]:17 0.0001385858 +15 mux_tree_tapbuf_size4_3_sram[0]:7 mux_tree_tapbuf_size4_3_sram[1]:16 0.0001385858 +16 mux_tree_tapbuf_size4_3_sram[0]:7 mux_tree_tapbuf_size4_3_sram[1]:18 5.691974e-06 + +*RES +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_3_sram[0]:12 0.152 +1 mux_tree_tapbuf_size4_3_sram[0]:11 mux_tree_tapbuf_size4_3_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size4_3_sram[0]:11 mux_tree_tapbuf_size4_3_sram[0]:4 0.0006071429 +3 mux_tree_tapbuf_size4_3_sram[0]:10 mux_tree_tapbuf_size4_3_sram[0]:9 0.001741071 +4 mux_tree_tapbuf_size4_3_sram[0]:8 mux_tree_tapbuf_size4_3_sram[0]:7 0.004477679 +5 mux_tree_tapbuf_size4_3_sram[0]:9 mux_tree_tapbuf_size4_3_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size4_3_sram[0]:5 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size4_3_sram[0]:12 mux_tree_tapbuf_size4_3_sram[0]:11 8.423914e-05 +8 mux_tree_tapbuf_size4_3_sram[0]:3 mux_right_track_10\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size4_3_sram[0]:6 mux_tree_tapbuf_size4_3_sram[0]:5 0.0006316964 +10 mux_tree_tapbuf_size4_3_sram[0]:7 mux_tree_tapbuf_size4_3_sram[0]:6 0.0003035715 +11 mux_tree_tapbuf_size4_3_sram[0]:4 mux_tree_tapbuf_size4_3_sram[0]:3 0.003984375 + +*END + +*D_NET mux_tree_tapbuf_size4_6_sram[1] 0.003304408 //LENGTH 28.750 LUMPCC 0.000462488 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 27.905 60.860 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 25.475 47.940 +*I mux_right_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 30.260 42.160 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 30.240 58.140 +*N mux_tree_tapbuf_size4_6_sram[1]:4 *C 30.203 58.140 +*N mux_tree_tapbuf_size4_6_sram[1]:5 *C 30.223 42.160 +*N mux_tree_tapbuf_size4_6_sram[1]:6 *C 28.565 42.160 +*N mux_tree_tapbuf_size4_6_sram[1]:7 *C 28.520 42.205 +*N mux_tree_tapbuf_size4_6_sram[1]:8 *C 28.520 47.895 +*N mux_tree_tapbuf_size4_6_sram[1]:9 *C 28.475 47.940 +*N mux_tree_tapbuf_size4_6_sram[1]:10 *C 25.513 47.940 +*N mux_tree_tapbuf_size4_6_sram[1]:11 *C 27.140 47.940 +*N mux_tree_tapbuf_size4_6_sram[1]:12 *C 27.140 47.985 +*N mux_tree_tapbuf_size4_6_sram[1]:13 *C 27.140 58.095 +*N mux_tree_tapbuf_size4_6_sram[1]:14 *C 27.185 58.140 +*N mux_tree_tapbuf_size4_6_sram[1]:15 *C 28.060 58.140 +*N mux_tree_tapbuf_size4_6_sram[1]:16 *C 28.060 58.185 +*N mux_tree_tapbuf_size4_6_sram[1]:17 *C 28.060 60.815 +*N mux_tree_tapbuf_size4_6_sram[1]:18 *C 28.060 60.860 +*N mux_tree_tapbuf_size4_6_sram[1]:19 *C 27.905 60.860 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_24\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_6_sram[1]:4 9.863614e-05 +5 mux_tree_tapbuf_size4_6_sram[1]:5 0.0001466676 +6 mux_tree_tapbuf_size4_6_sram[1]:6 0.0001466676 +7 mux_tree_tapbuf_size4_6_sram[1]:7 0.0003068227 +8 mux_tree_tapbuf_size4_6_sram[1]:8 0.0003068227 +9 mux_tree_tapbuf_size4_6_sram[1]:9 9.33835e-05 +10 mux_tree_tapbuf_size4_6_sram[1]:10 0.0001115925 +11 mux_tree_tapbuf_size4_6_sram[1]:11 0.0002359922 +12 mux_tree_tapbuf_size4_6_sram[1]:12 0.0003851112 +13 mux_tree_tapbuf_size4_6_sram[1]:13 0.0003851112 +14 mux_tree_tapbuf_size4_6_sram[1]:14 4.581807e-05 +15 mux_tree_tapbuf_size4_6_sram[1]:15 0.0001767991 +16 mux_tree_tapbuf_size4_6_sram[1]:16 0.0001484385 +17 mux_tree_tapbuf_size4_6_sram[1]:17 0.0001484385 +18 mux_tree_tapbuf_size4_6_sram[1]:18 5.227716e-05 +19 mux_tree_tapbuf_size4_6_sram[1]:19 4.934147e-05 +20 mux_tree_tapbuf_size4_6_sram[1]:4 chany_bottom_in[18]:10 3.839504e-05 +21 mux_tree_tapbuf_size4_6_sram[1]:8 chany_bottom_in[18]:14 1.396229e-05 +22 mux_tree_tapbuf_size4_6_sram[1]:7 chany_bottom_in[18]:15 1.396229e-05 +23 mux_tree_tapbuf_size4_6_sram[1]:12 chany_bottom_in[18]:14 6.276357e-05 +24 mux_tree_tapbuf_size4_6_sram[1]:12 chany_bottom_in[18]:15 8.550598e-05 +25 mux_tree_tapbuf_size4_6_sram[1]:14 chany_bottom_in[18]:11 1.783512e-05 +26 mux_tree_tapbuf_size4_6_sram[1]:13 chany_bottom_in[18]:13 6.276357e-05 +27 mux_tree_tapbuf_size4_6_sram[1]:13 chany_bottom_in[18]:14 8.550598e-05 +28 mux_tree_tapbuf_size4_6_sram[1]:15 chany_bottom_in[18]:10 1.783512e-05 +29 mux_tree_tapbuf_size4_6_sram[1]:15 chany_bottom_in[18]:11 3.839504e-05 +30 mux_tree_tapbuf_size4_6_sram[1]:16 chany_bottom_in[18]:12 1.258489e-05 +31 mux_tree_tapbuf_size4_6_sram[1]:16 chany_bottom_in[18]:14 1.9711e-07 +32 mux_tree_tapbuf_size4_6_sram[1]:17 chany_bottom_in[18]:9 1.258489e-05 +33 mux_tree_tapbuf_size4_6_sram[1]:17 chany_bottom_in[18]:13 1.9711e-07 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_6_sram[1]:19 0.152 +1 mux_tree_tapbuf_size4_6_sram[1]:4 mux_right_track_24\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_6_sram[1]:9 mux_tree_tapbuf_size4_6_sram[1]:8 0.0045 +3 mux_tree_tapbuf_size4_6_sram[1]:8 mux_tree_tapbuf_size4_6_sram[1]:7 0.005080358 +4 mux_tree_tapbuf_size4_6_sram[1]:6 mux_tree_tapbuf_size4_6_sram[1]:5 0.001479911 +5 mux_tree_tapbuf_size4_6_sram[1]:7 mux_tree_tapbuf_size4_6_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size4_6_sram[1]:5 mux_right_track_24\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size4_6_sram[1]:11 mux_tree_tapbuf_size4_6_sram[1]:10 0.001453125 +8 mux_tree_tapbuf_size4_6_sram[1]:11 mux_tree_tapbuf_size4_6_sram[1]:9 0.001191964 +9 mux_tree_tapbuf_size4_6_sram[1]:12 mux_tree_tapbuf_size4_6_sram[1]:11 0.0045 +10 mux_tree_tapbuf_size4_6_sram[1]:14 mux_tree_tapbuf_size4_6_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size4_6_sram[1]:13 mux_tree_tapbuf_size4_6_sram[1]:12 0.009026786 +12 mux_tree_tapbuf_size4_6_sram[1]:10 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size4_6_sram[1]:15 mux_tree_tapbuf_size4_6_sram[1]:14 0.00078125 +14 mux_tree_tapbuf_size4_6_sram[1]:15 mux_tree_tapbuf_size4_6_sram[1]:4 0.001912947 +15 mux_tree_tapbuf_size4_6_sram[1]:16 mux_tree_tapbuf_size4_6_sram[1]:15 0.0045 +16 mux_tree_tapbuf_size4_6_sram[1]:18 mux_tree_tapbuf_size4_6_sram[1]:17 0.0045 +17 mux_tree_tapbuf_size4_6_sram[1]:17 mux_tree_tapbuf_size4_6_sram[1]:16 0.002348214 +18 mux_tree_tapbuf_size4_6_sram[1]:19 mux_tree_tapbuf_size4_6_sram[1]:18 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[1] 0.002636308 //LENGTH 21.020 LUMPCC 0.0001412198 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 62.405 42.160 +*I mux_bottom_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 61.740 36.430 +*I mux_bottom_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 68.180 36.720 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 58.595 33.660 +*N mux_tree_tapbuf_size5_2_sram[1]:4 *C 58.595 33.660 +*N mux_tree_tapbuf_size5_2_sram[1]:5 *C 60.675 33.660 +*N mux_tree_tapbuf_size5_2_sram[1]:6 *C 60.720 33.705 +*N mux_tree_tapbuf_size5_2_sram[1]:7 *C 60.720 36.720 +*N mux_tree_tapbuf_size5_2_sram[1]:8 *C 68.142 36.720 +*N mux_tree_tapbuf_size5_2_sram[1]:9 *C 61.740 36.430 +*N mux_tree_tapbuf_size5_2_sram[1]:10 *C 61.778 36.720 +*N mux_tree_tapbuf_size5_2_sram[1]:11 *C 61.640 36.765 +*N mux_tree_tapbuf_size5_2_sram[1]:12 *C 61.640 42.115 +*N mux_tree_tapbuf_size5_2_sram[1]:13 *C 61.685 42.160 +*N mux_tree_tapbuf_size5_2_sram[1]:14 *C 62.367 42.160 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_3\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_track_3\/mux_l2_in_0_:S 1e-06 +3 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size5_2_sram[1]:4 0.0001866801 +5 mux_tree_tapbuf_size5_2_sram[1]:5 0.0001512352 +6 mux_tree_tapbuf_size5_2_sram[1]:6 0.0001612537 +7 mux_tree_tapbuf_size5_2_sram[1]:7 0.0002130564 +8 mux_tree_tapbuf_size5_2_sram[1]:8 0.0004339217 +9 mux_tree_tapbuf_size5_2_sram[1]:9 5.723089e-05 +10 mux_tree_tapbuf_size5_2_sram[1]:10 0.0004646941 +11 mux_tree_tapbuf_size5_2_sram[1]:11 0.0003518062 +12 mux_tree_tapbuf_size5_2_sram[1]:12 0.0003000034 +13 mux_tree_tapbuf_size5_2_sram[1]:13 8.560294e-05 +14 mux_tree_tapbuf_size5_2_sram[1]:14 8.560294e-05 +15 mux_tree_tapbuf_size5_2_sram[1]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.060991e-05 +16 mux_tree_tapbuf_size5_2_sram[1]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.060991e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_2_sram[1]:14 0.152 +1 mux_tree_tapbuf_size5_2_sram[1]:4 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size5_2_sram[1]:5 mux_tree_tapbuf_size5_2_sram[1]:4 0.001857143 +3 mux_tree_tapbuf_size5_2_sram[1]:6 mux_tree_tapbuf_size5_2_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size5_2_sram[1]:12 mux_tree_tapbuf_size5_2_sram[1]:11 0.004776785 +6 mux_tree_tapbuf_size5_2_sram[1]:14 mux_tree_tapbuf_size5_2_sram[1]:13 0.000609375 +7 mux_tree_tapbuf_size5_2_sram[1]:9 mux_bottom_track_3\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size5_2_sram[1]:8 mux_bottom_track_3\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[1]:9 0.000125 +10 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[1]:8 0.005683036 +11 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[1]:10 0.0045 +12 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[1]:7 0.0008214285 +13 mux_tree_tapbuf_size5_2_sram[1]:7 mux_tree_tapbuf_size5_2_sram[1]:6 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_1_ccff_tail[0] 0.0005349988 //LENGTH 4.180 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/FTB_9__39:X O *L 0 *C 27.375 76.840 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 30.075 77.180 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 *C 30.103 77.157 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 *C 30.360 77.145 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 *C 30.360 76.840 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 *C 27.413 76.840 + +*CAP +0 mem_top_track_16\/FTB_9__39:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 4.102104e-05 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 6.567125e-05 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.0002254784 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0002008282 + +*RES +0 mem_top_track_16\/FTB_9__39:X mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.152 +1 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.002631697 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0002723215 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.0001739865 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.001116035 //LENGTH 7.385 LUMPCC 0.0004665106 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 88.625 63.920 +*I mux_top_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 89.820 67.320 +*I mem_top_track_0\/FTB_1__31:A I *L 0.001746 *C 92.000 63.920 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 91.963 63.920 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 89.700 67.320 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 89.700 67.275 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 89.700 63.965 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 89.700 63.920 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 88.740 63.920 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_0\/FTB_1__31:A 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 8.620791e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 3.551656e-05 +5 mux_tree_tapbuf_size6_0_sram[2]:5 0.0001515676 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0001515676 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0001693444 +8 mux_tree_tapbuf_size6_0_sram[2]:8 5.232055e-05 +9 mux_tree_tapbuf_size6_0_sram[2]:5 prog_clk[0]:99 9.585111e-05 +10 mux_tree_tapbuf_size6_0_sram[2]:6 prog_clk[0]:100 9.585111e-05 +11 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[1]:7 9.144338e-05 +12 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[1]:8 4.596081e-05 +13 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[1]:7 4.596081e-05 +14 mux_tree_tapbuf_size6_0_sram[2]:3 mux_tree_tapbuf_size6_0_sram[1]:8 9.144338e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:8 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:4 mux_top_track_0\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:3 0.002020089 +5 mux_tree_tapbuf_size6_0_sram[2]:6 mux_tree_tapbuf_size6_0_sram[2]:5 0.002955358 +6 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0008571429 +7 mux_tree_tapbuf_size6_0_sram[2]:3 mem_top_track_0\/FTB_1__31:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[2] 0.001192312 //LENGTH 10.020 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 97.365 93.840 +*I mux_right_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 96.960 91.120 +*I mem_right_track_0\/FTB_4__34:A I *L 0.001746 *C 100.280 96.560 +*N mux_tree_tapbuf_size6_3_sram[2]:3 *C 100.280 96.560 +*N mux_tree_tapbuf_size6_3_sram[2]:4 *C 100.280 96.515 +*N mux_tree_tapbuf_size6_3_sram[2]:5 *C 100.280 94.225 +*N mux_tree_tapbuf_size6_3_sram[2]:6 *C 100.235 94.180 +*N mux_tree_tapbuf_size6_3_sram[2]:7 *C 97.060 94.180 +*N mux_tree_tapbuf_size6_3_sram[2]:8 *C 96.960 91.120 +*N mux_tree_tapbuf_size6_3_sram[2]:9 *C 97.060 91.165 +*N mux_tree_tapbuf_size6_3_sram[2]:10 *C 97.060 93.795 +*N mux_tree_tapbuf_size6_3_sram[2]:11 *C 97.060 93.840 +*N mux_tree_tapbuf_size6_3_sram[2]:12 *C 97.365 93.840 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_0\/FTB_4__34:A 1e-06 +3 mux_tree_tapbuf_size6_3_sram[2]:3 2.967911e-05 +4 mux_tree_tapbuf_size6_3_sram[2]:4 0.0001492944 +5 mux_tree_tapbuf_size6_3_sram[2]:5 0.0001492944 +6 mux_tree_tapbuf_size6_3_sram[2]:6 0.0002025962 +7 mux_tree_tapbuf_size6_3_sram[2]:7 0.0002286679 +8 mux_tree_tapbuf_size6_3_sram[2]:8 2.607279e-05 +9 mux_tree_tapbuf_size6_3_sram[2]:9 0.0001526111 +10 mux_tree_tapbuf_size6_3_sram[2]:10 0.0001526111 +11 mux_tree_tapbuf_size6_3_sram[2]:11 6.384785e-05 +12 mux_tree_tapbuf_size6_3_sram[2]:12 3.463727e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_3_sram[2]:12 0.152 +1 mux_tree_tapbuf_size6_3_sram[2]:12 mux_tree_tapbuf_size6_3_sram[2]:11 0.0001657609 +2 mux_tree_tapbuf_size6_3_sram[2]:11 mux_tree_tapbuf_size6_3_sram[2]:10 0.0045 +3 mux_tree_tapbuf_size6_3_sram[2]:11 mux_tree_tapbuf_size6_3_sram[2]:7 0.0003035715 +4 mux_tree_tapbuf_size6_3_sram[2]:10 mux_tree_tapbuf_size6_3_sram[2]:9 0.002348214 +5 mux_tree_tapbuf_size6_3_sram[2]:8 mux_right_track_0\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_3_sram[2]:9 mux_tree_tapbuf_size6_3_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size6_3_sram[2]:6 mux_tree_tapbuf_size6_3_sram[2]:5 0.0045 +8 mux_tree_tapbuf_size6_3_sram[2]:5 mux_tree_tapbuf_size6_3_sram[2]:4 0.002044643 +9 mux_tree_tapbuf_size6_3_sram[2]:3 mem_right_track_0\/FTB_4__34:A 0.152 +10 mux_tree_tapbuf_size6_3_sram[2]:4 mux_tree_tapbuf_size6_3_sram[2]:3 0.0045 +11 mux_tree_tapbuf_size6_3_sram[2]:7 mux_tree_tapbuf_size6_3_sram[2]:6 0.002834822 + +*END + +*D_NET mux_tree_tapbuf_size6_6_sram[1] 0.00265718 //LENGTH 21.170 LUMPCC 0.0003410296 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 87.705 39.100 +*I mux_bottom_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 93.480 30.600 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 92.360 41.480 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 94.935 39.100 +*N mux_tree_tapbuf_size6_6_sram[1]:4 *C 94.898 39.100 +*N mux_tree_tapbuf_size6_6_sram[1]:5 *C 92.345 41.480 +*N mux_tree_tapbuf_size6_6_sram[1]:6 *C 92.023 41.480 +*N mux_tree_tapbuf_size6_6_sram[1]:7 *C 92.000 41.435 +*N mux_tree_tapbuf_size6_6_sram[1]:8 *C 93.443 30.600 +*N mux_tree_tapbuf_size6_6_sram[1]:9 *C 92.045 30.600 +*N mux_tree_tapbuf_size6_6_sram[1]:10 *C 92.000 30.645 +*N mux_tree_tapbuf_size6_6_sram[1]:11 *C 92.000 39.100 +*N mux_tree_tapbuf_size6_6_sram[1]:12 *C 92.000 39.100 +*N mux_tree_tapbuf_size6_6_sram[1]:13 *C 87.743 39.100 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_9\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_6_sram[1]:4 0.0001928649 +5 mux_tree_tapbuf_size6_6_sram[1]:5 5.509614e-05 +6 mux_tree_tapbuf_size6_6_sram[1]:6 5.509614e-05 +7 mux_tree_tapbuf_size6_6_sram[1]:7 0.0001089491 +8 mux_tree_tapbuf_size6_6_sram[1]:8 0.0001182392 +9 mux_tree_tapbuf_size6_6_sram[1]:9 0.0001182392 +10 mux_tree_tapbuf_size6_6_sram[1]:10 0.0003829487 +11 mux_tree_tapbuf_size6_6_sram[1]:11 0.0005227411 +12 mux_tree_tapbuf_size6_6_sram[1]:12 0.0004921102 +13 mux_tree_tapbuf_size6_6_sram[1]:13 0.0002658661 +14 mux_tree_tapbuf_size6_6_sram[1]:10 mux_tree_tapbuf_size6_6_sram[2]:6 7.609167e-05 +15 mux_tree_tapbuf_size6_6_sram[1]:11 mux_tree_tapbuf_size6_6_sram[2]:7 7.609167e-05 +16 mux_tree_tapbuf_size6_6_sram[1]:11 mux_tree_tapbuf_size6_6_sram[2]:6 4.771932e-05 +17 mux_tree_tapbuf_size6_6_sram[1]:7 mux_tree_tapbuf_size6_6_sram[2]:7 4.771932e-05 +18 mux_tree_tapbuf_size6_6_sram[1]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.170599e-07 +19 mux_tree_tapbuf_size6_6_sram[1]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.628677e-05 +20 mux_tree_tapbuf_size6_6_sram[1]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.170599e-07 +21 mux_tree_tapbuf_size6_6_sram[1]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.628677e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_6_sram[1]:13 0.152 +1 mux_tree_tapbuf_size6_6_sram[1]:9 mux_tree_tapbuf_size6_6_sram[1]:8 0.001247768 +2 mux_tree_tapbuf_size6_6_sram[1]:10 mux_tree_tapbuf_size6_6_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size6_6_sram[1]:8 mux_bottom_track_9\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size6_6_sram[1]:12 mux_tree_tapbuf_size6_6_sram[1]:11 0.0045 +5 mux_tree_tapbuf_size6_6_sram[1]:12 mux_tree_tapbuf_size6_6_sram[1]:4 0.002587053 +6 mux_tree_tapbuf_size6_6_sram[1]:11 mux_tree_tapbuf_size6_6_sram[1]:10 0.007549107 +7 mux_tree_tapbuf_size6_6_sram[1]:11 mux_tree_tapbuf_size6_6_sram[1]:7 0.002084821 +8 mux_tree_tapbuf_size6_6_sram[1]:4 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size6_6_sram[1]:13 mux_tree_tapbuf_size6_6_sram[1]:12 0.003801339 +10 mux_tree_tapbuf_size6_6_sram[1]:5 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size6_6_sram[1]:6 mux_tree_tapbuf_size6_6_sram[1]:5 0.0001752718 +12 mux_tree_tapbuf_size6_6_sram[1]:7 mux_tree_tapbuf_size6_6_sram[1]:6 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[1] 0.003720644 //LENGTH 28.765 LUMPCC 0.0007430072 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.965 123.760 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 72.395 115.260 +*I mux_right_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 78.300 110.160 +*I mux_right_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 74.420 121.335 +*N mux_tree_tapbuf_size7_0_sram[1]:4 *C 74.420 121.335 +*N mux_tree_tapbuf_size7_0_sram[1]:5 *C 78.263 110.160 +*N mux_tree_tapbuf_size7_0_sram[1]:6 *C 73.185 110.160 +*N mux_tree_tapbuf_size7_0_sram[1]:7 *C 73.140 110.205 +*N mux_tree_tapbuf_size7_0_sram[1]:8 *C 72.433 115.260 +*N mux_tree_tapbuf_size7_0_sram[1]:9 *C 73.095 115.260 +*N mux_tree_tapbuf_size7_0_sram[1]:10 *C 73.140 115.260 +*N mux_tree_tapbuf_size7_0_sram[1]:11 *C 73.140 121.335 +*N mux_tree_tapbuf_size7_0_sram[1]:12 *C 73.140 121.380 +*N mux_tree_tapbuf_size7_0_sram[1]:13 *C 73.140 121.040 +*N mux_tree_tapbuf_size7_0_sram[1]:14 *C 74.310 121.040 +*N mux_tree_tapbuf_size7_0_sram[1]:15 *C 78.155 121.040 +*N mux_tree_tapbuf_size7_0_sram[1]:16 *C 78.200 121.085 +*N mux_tree_tapbuf_size7_0_sram[1]:17 *C 78.200 123.715 +*N mux_tree_tapbuf_size7_0_sram[1]:18 *C 78.245 123.760 +*N mux_tree_tapbuf_size7_0_sram[1]:19 *C 78.928 123.760 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_2\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_2\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_0_sram[1]:4 6.356367e-05 +5 mux_tree_tapbuf_size7_0_sram[1]:5 0.0001715294 +6 mux_tree_tapbuf_size7_0_sram[1]:6 0.0001715294 +7 mux_tree_tapbuf_size7_0_sram[1]:7 0.0002721648 +8 mux_tree_tapbuf_size7_0_sram[1]:8 6.438095e-05 +9 mux_tree_tapbuf_size7_0_sram[1]:9 6.438095e-05 +10 mux_tree_tapbuf_size7_0_sram[1]:10 0.0006913529 +11 mux_tree_tapbuf_size7_0_sram[1]:11 0.0003878616 +12 mux_tree_tapbuf_size7_0_sram[1]:12 5.237156e-05 +13 mux_tree_tapbuf_size7_0_sram[1]:13 8.856361e-05 +14 mux_tree_tapbuf_size7_0_sram[1]:14 0.0002930815 +15 mux_tree_tapbuf_size7_0_sram[1]:15 0.0001967973 +16 mux_tree_tapbuf_size7_0_sram[1]:16 0.0001600609 +17 mux_tree_tapbuf_size7_0_sram[1]:17 0.0001600609 +18 mux_tree_tapbuf_size7_0_sram[1]:18 6.796869e-05 +19 mux_tree_tapbuf_size7_0_sram[1]:19 6.796869e-05 +20 mux_tree_tapbuf_size7_0_sram[1]:6 mux_tree_tapbuf_size7_0_sram[2]:4 0.0001809919 +21 mux_tree_tapbuf_size7_0_sram[1]:5 mux_tree_tapbuf_size7_0_sram[2]:5 0.0001809919 +22 mux_tree_tapbuf_size7_0_sram[1]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.131402e-05 +23 mux_tree_tapbuf_size7_0_sram[1]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.072093e-05 +24 mux_tree_tapbuf_size7_0_sram[1]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.131402e-05 +25 mux_tree_tapbuf_size7_0_sram[1]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.072093e-05 +26 mux_tree_tapbuf_size7_0_sram[1]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.84767e-05 +27 mux_tree_tapbuf_size7_0_sram[1]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.84767e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_0_sram[1]:19 0.152 +1 mux_tree_tapbuf_size7_0_sram[1]:12 mux_tree_tapbuf_size7_0_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size7_0_sram[1]:11 mux_tree_tapbuf_size7_0_sram[1]:10 0.005424107 +3 mux_tree_tapbuf_size7_0_sram[1]:9 mux_tree_tapbuf_size7_0_sram[1]:8 0.0005915179 +4 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:7 0.004513393 +6 mux_tree_tapbuf_size7_0_sram[1]:8 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:14 0.003433036 +8 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:15 0.0045 +9 mux_tree_tapbuf_size7_0_sram[1]:18 mux_tree_tapbuf_size7_0_sram[1]:17 0.0045 +10 mux_tree_tapbuf_size7_0_sram[1]:17 mux_tree_tapbuf_size7_0_sram[1]:16 0.002348214 +11 mux_tree_tapbuf_size7_0_sram[1]:19 mux_tree_tapbuf_size7_0_sram[1]:18 0.000609375 +12 mux_tree_tapbuf_size7_0_sram[1]:6 mux_tree_tapbuf_size7_0_sram[1]:5 0.004533482 +13 mux_tree_tapbuf_size7_0_sram[1]:7 mux_tree_tapbuf_size7_0_sram[1]:6 0.0045 +14 mux_tree_tapbuf_size7_0_sram[1]:5 mux_right_track_2\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size7_0_sram[1]:4 mux_right_track_2\/mux_l2_in_0_:S 0.152 +16 mux_tree_tapbuf_size7_0_sram[1]:13 mux_tree_tapbuf_size7_0_sram[1]:12 0.0003035715 +17 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:13 0.001044643 +18 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:4 0.0001271552 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006003965 //LENGTH 4.355 LUMPCC 0.0001009552 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_1_:X O *L 0 *C 97.235 64.260 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 95.510 65.960 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 95.547 65.960 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 96.095 65.960 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 96.140 65.915 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 96.140 64.305 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 96.185 64.260 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 97.198 64.260 + +*CAP +0 mux_top_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.376894e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.376894e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001187769 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001187769 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.617476e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.617476e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.047761e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.047761e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040179 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001345686 //LENGTH 10.980 LUMPCC 0.0003440817 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 86.655 45.220 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 84.085 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 84.123 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.595 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 84.640 52.655 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 84.640 45.265 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 84.685 45.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 86.618 45.220 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.853688e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.853688e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003602294 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003602294 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.103594e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.103594e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_1_sram[0]:25 8.651878e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_1_sram[0]:26 8.651878e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.850966e-06 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.850966e-06 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.367108e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.367108e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006598215 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005164167 //LENGTH 3.330 LUMPCC 0.0001474451 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_2_:X O *L 0 *C 65.035 58.820 +*I mux_top_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 64.765 61.540 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 64.765 61.540 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 64.860 61.495 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 64.860 58.865 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 64.860 58.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 65.035 58.820 + +*CAP +0 mux_top_track_8\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.94617e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001154659 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001154659 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.398101e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.25971e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:171 4.07473e-06 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:244 6.96478e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:170 4.07473e-06 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:245 6.96478e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_2_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_8\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002348214 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001224418 //LENGTH 8.735 LUMPCC 0.0001578378 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 88.145 90.440 +*I mux_right_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 96.240 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 96.240 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 96.140 90.440 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 88.183 90.440 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.142911e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0005193175 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004938334 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_3_sram[1]:9 6.84798e-05 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_3_sram[1]:11 1.043911e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_3_sram[1]:8 1.043911e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_3_sram[1]:10 6.84798e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.007104911 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007876979 //LENGTH 6.310 LUMPCC 0.0001292102 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_0_:X O *L 0 *C 49.965 17.000 +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 50.425 12.090 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 50.425 12.090 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 50.600 12.240 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 50.600 12.285 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 50.600 16.955 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 50.555 17.000 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 50.003 17.000 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.006064e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.509332e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002125535 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002125535 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.311342e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.311342e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[12]:7 6.46051e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[12]:8 6.46051e-05 + +*RES +0 mux_bottom_track_1\/mux_l3_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001449522 //LENGTH 10.720 LUMPCC 0.0001635184 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_1_:X O *L 0 *C 99.535 44.200 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 91.255 42.500 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 91.293 42.500 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 99.315 42.500 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 99.360 42.545 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 99.360 44.155 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 99.360 44.200 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 99.535 44.200 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004825244 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0004825244 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001087444 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001087444 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.162037e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.984534e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 8.175922e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 8.175922e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.007162946 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.01442787 //LENGTH 115.400 LUMPCC 0.003294942 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_0_:X O *L 0 *C 89.875 59.160 +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 35.245 115.470 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 35.282 115.558 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 40.895 115.600 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 40.940 115.600 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 40.948 115.600 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 60.700 115.600 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 60.720 115.593 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 60.720 63.248 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 60.740 63.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 91.073 63.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 91.080 63.183 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 91.080 59.205 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:13 *C 91.035 59.160 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:14 *C 89.913 59.160 + +*CAP +0 mux_top_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003045004 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003045004 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.402722e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00130911 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00130911 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.001744932 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.001744932 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.00185969 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.00185969 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0002343037 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0002343037 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:13 9.591399e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:14 9.591399e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chany_top_in[16]:38 0.0009573804 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_top_in[16]:39 0.0009573804 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 chany_bottom_in[6]:17 1.769049e-05 +18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 chany_bottom_in[6]:18 1.769049e-05 +19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chany_bottom_in[6]:13 3.216865e-05 +20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chany_bottom_in[6]:17 0.0003887853 +21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_bottom_in[6]:12 3.216865e-05 +22 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_bottom_in[6]:16 0.0003887853 +23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 top_left_grid_pin_1_[0]:20 0.0002514462 +24 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 top_left_grid_pin_1_[0]:21 0.0002514462 + +*RES +0 mux_top_track_2\/mux_l3_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.001002232 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.00355134 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.00341 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.004752092 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.00341 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.008200716 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.003094558 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00341 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00341 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.005011161 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008767322 //LENGTH 5.810 LUMPCC 0.0003471826 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_1_:X O *L 0 *C 61.355 44.540 +*I mux_bottom_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 55.835 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 55.873 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.318 44.540 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002637748 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002637748 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_right_in[14]:8 0.0001220508 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[14]:7 0.0001220508 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size5_4_sram[2]:5 5.154052e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size5_4_sram[2]:3 5.154052e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004861608 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001499684 //LENGTH 10.880 LUMPCC 0.0004583272 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_0_:X O *L 0 *C 58.595 72.760 +*I mux_top_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 56.120 79.900 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 56.120 79.900 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 56.120 79.855 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 56.120 77.905 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 56.165 77.860 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 57.455 77.860 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 57.500 77.815 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 57.500 72.805 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 57.545 72.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 58.558 72.760 + +*CAP +0 mux_top_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.484788e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.331346e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.331346e-05 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.36262e-05 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.36262e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002155389 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002155389 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.000109776 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.000109776 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[8]:22 5.976634e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[8]:21 5.976634e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[8]:22 5.223657e-05 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_top_in[8]:21 5.223657e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[14]:10 5.518803e-05 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[14]:9 5.518803e-05 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:15 6.197268e-05 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_3_sram[0]:16 6.197268e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001741072 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001151786 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.004473215 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0009040179 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0] 0.009071022 //LENGTH 64.905 LUMPCC 0.001573631 DR + +*CONN +*I mux_right_track_10\/mux_l3_in_0_:X O *L 0 *C 42.145 88.400 +*I mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 100.065 82.765 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 100.065 82.765 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 99.820 82.960 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 99.820 83.005 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 99.820 84.943 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 99.812 85.000 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 46.940 85.000 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 46.920 85.008 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 46.920 88.392 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 46.900 88.400 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 42.328 88.400 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 42.320 88.400 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 42.320 88.400 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 42.145 88.400 + +*CAP +0 mux_right_track_10\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.27426e-05 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.556622e-05 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001514946 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001514946 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002954543 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002954543 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001889913 +9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001889913 +10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0003295413 +11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0003295413 +12 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.330088e-05 +13 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 5.278763e-05 +14 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 5.185333e-05 +15 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:184 6.124866e-05 +16 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:205 9.400168e-05 +17 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:214 0.0001168647 +18 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:215 7.102584e-05 +19 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:230 5.776195e-07 +20 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:233 6.000478e-06 +21 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:183 6.124866e-05 +22 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:204 9.400168e-05 +23 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:209 0.0001168647 +24 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:214 7.102584e-05 +25 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:229 5.776195e-07 +26 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:234 6.000478e-06 +27 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001852591 +28 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001852591 +29 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001521617 +30 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.967577e-05 +31 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001521617 +32 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.967577e-05 + +*RES +0 mux_right_track_10\/mux_l3_in_0_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 9.51087e-05 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.00341 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0007163583 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00341 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0005303166 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.008283358 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001729911 +10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001059783 +12 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +13 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004058958 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_3_:X O *L 0 *C 79.405 108.120 +*I mux_right_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 79.410 109.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 79.410 109.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 79.580 109.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 79.580 109.435 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 79.580 108.165 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 79.580 108.120 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 79.405 108.120 + +*CAP +0 mux_right_track_2\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.360787e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.578166e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.180696e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.180696e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.653214e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.436012e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_3_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_2\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.239131e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001133929 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003697545 //LENGTH 2.310 LUMPCC 0 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_0_:X O *L 0 *C 64.685 123.080 +*I mux_right_track_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.400 121.380 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.400 121.380 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 64.400 121.425 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 64.400 123.035 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 64.400 123.080 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 64.685 123.080 + +*CAP +0 mux_right_track_6\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.460768e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001134083 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001134083 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.735856e-05 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.897173e-05 + +*RES +0 mux_right_track_6\/mux_l1_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548913 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0014375 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_6\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001153186 //LENGTH 9.825 LUMPCC 0.000202302 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_3_:X O *L 0 *C 64.685 110.840 +*I mux_right_track_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 63.310 118.660 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 63.348 118.660 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 64.355 118.660 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 64.400 118.615 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 64.400 110.885 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 64.400 110.840 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 64.685 110.840 + +*CAP +0 mux_right_track_6\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.23031e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.23031e-05 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003288726 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003288726 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.043466e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.609786e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:13 5.500611e-08 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:17 1.390869e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:20 6.55178e-05 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:23 1.987703e-05 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:25 1.792479e-06 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:14 5.500611e-08 +14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:20 1.390869e-05 +15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:23 6.55178e-05 +16 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:24 1.987703e-05 +17 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:26 1.792479e-06 + +*RES +0 mux_right_track_6\/mux_l1_in_3_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_6\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008995536 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00137754 //LENGTH 9.910 LUMPCC 0 DR + +*CONN +*I mux_right_track_22\/mux_l1_in_1_:X O *L 0 *C 53.645 79.560 +*I mux_right_track_22\/mux_l2_in_0_:A0 I *L 0.001631 *C 59.975 77.180 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 59.975 77.180 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 60.260 77.180 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 60.260 77.225 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 60.260 79.515 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 60.215 79.560 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 53.683 79.560 + +*CAP +0 mux_right_track_22\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_22\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.21566e-05 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.468027e-05 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001638413 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001638413 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004705102 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004705102 + +*RES +0 mux_right_track_22\/mux_l1_in_1_:X mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_22\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00583259 + +*END + +*D_NET ropt_net_226 0.0008504437 //LENGTH 7.160 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 69.630 6.460 +*I ropt_mt_inst_846:A I *L 0.001767 *C 65.780 4.080 +*N ropt_net_226:2 *C 65.818 4.080 +*N ropt_net_226:3 *C 68.035 4.080 +*N ropt_net_226:4 *C 68.080 4.125 +*N ropt_net_226:5 *C 68.080 6.415 +*N ropt_net_226:6 *C 68.125 6.460 +*N ropt_net_226:7 *C 69.593 6.460 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 ropt_mt_inst_846:A 1e-06 +2 ropt_net_226:2 0.0001470743 +3 ropt_net_226:3 0.0001470743 +4 ropt_net_226:4 0.0001551455 +5 ropt_net_226:5 0.0001551455 +6 ropt_net_226:6 0.000122002 +7 ropt_net_226:7 0.000122002 + +*RES +0 ropt_mt_inst_812:X ropt_net_226:7 0.152 +1 ropt_net_226:2 ropt_mt_inst_846:A 0.152 +2 ropt_net_226:3 ropt_net_226:2 0.001979911 +3 ropt_net_226:4 ropt_net_226:3 0.0045 +4 ropt_net_226:6 ropt_net_226:5 0.0045 +5 ropt_net_226:5 ropt_net_226:4 0.002044643 +6 ropt_net_226:7 ropt_net_226:6 0.001310268 + +*END + +*D_NET ropt_net_242 0.0006805992 //LENGTH 4.420 LUMPCC 0.0002412192 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 41.860 9.180 +*I ropt_mt_inst_862:A I *L 0.001766 *C 45.540 9.520 +*N ropt_net_242:2 *C 45.540 9.520 +*N ropt_net_242:3 *C 45.540 9.180 +*N ropt_net_242:4 *C 41.898 9.180 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 ropt_mt_inst_862:A 1e-06 +2 ropt_net_242:2 5.631996e-05 +3 ropt_net_242:3 0.0002030096 +4 ropt_net_242:4 0.0001780505 +5 ropt_net_242:2 chany_top_in[2]:7 4.855065e-06 +6 ropt_net_242:4 chany_top_in[2]:5 0.0001094517 +7 ropt_net_242:4 chany_top_in[2]:7 6.30286e-06 +8 ropt_net_242:3 chany_top_in[2]:6 0.0001143067 +9 ropt_net_242:3 chany_top_in[2]:8 6.30286e-06 + +*RES +0 ropt_mt_inst_819:X ropt_net_242:4 0.152 +1 ropt_net_242:2 ropt_mt_inst_862:A 0.152 +2 ropt_net_242:4 ropt_net_242:3 0.003252232 +3 ropt_net_242:3 ropt_net_242:2 0.0003035715 + +*END + +*D_NET ropt_net_231 0.001557786 //LENGTH 9.890 LUMPCC 0.0008390408 DR + +*CONN +*I ropt_mt_inst_836:X O *L 0 *C 54.880 4.420 +*I ropt_mt_inst_851:A I *L 0.001767 *C 48.300 6.800 +*N ropt_net_231:2 *C 48.338 6.800 +*N ropt_net_231:3 *C 48.715 6.800 +*N ropt_net_231:4 *C 48.760 6.755 +*N ropt_net_231:5 *C 48.760 4.465 +*N ropt_net_231:6 *C 48.805 4.420 +*N ropt_net_231:7 *C 54.843 4.420 + +*CAP +0 ropt_mt_inst_836:X 1e-06 +1 ropt_mt_inst_851:A 1e-06 +2 ropt_net_231:2 5.084528e-05 +3 ropt_net_231:3 5.084528e-05 +4 ropt_net_231:4 7.564881e-05 +5 ropt_net_231:5 7.564881e-05 +6 ropt_net_231:6 0.0002318786 +7 ropt_net_231:7 0.0002318786 +8 ropt_net_231:7 chany_top_in[16]:14 0.000201682 +9 ropt_net_231:6 chany_top_in[16]:13 0.000201682 +10 ropt_net_231:5 chany_top_in[16]:12 6.205701e-05 +11 ropt_net_231:4 chany_top_in[16]:11 6.205701e-05 +12 ropt_net_231:7 ropt_net_215:2 9.391311e-05 +13 ropt_net_231:6 ropt_net_215:3 9.391311e-05 +14 ropt_net_231:5 ropt_net_215:4 6.186829e-05 +15 ropt_net_231:4 ropt_net_215:5 6.186829e-05 + +*RES +0 ropt_mt_inst_836:X ropt_net_231:7 0.152 +1 ropt_net_231:7 ropt_net_231:6 0.005390625 +2 ropt_net_231:6 ropt_net_231:5 0.0045 +3 ropt_net_231:5 ropt_net_231:4 0.002044643 +4 ropt_net_231:3 ropt_net_231:2 0.0003370536 +5 ropt_net_231:4 ropt_net_231:3 0.0045 +6 ropt_net_231:2 ropt_mt_inst_851:A 0.152 + +*END + +*D_NET chany_top_out[11] 0.001764425 //LENGTH 13.295 LUMPCC 0.0004637466 DR + +*CONN +*I ropt_mt_inst_845:X O *L 0 *C 52.900 124.440 +*P chany_top_out[11] O *L 0.7423 *C 51.060 129.270 +*N chany_top_out[11]:2 *C 51.060 128.565 +*N chany_top_out[11]:3 *C 51.105 128.520 +*N chany_top_out[11]:4 *C 55.615 128.520 +*N chany_top_out[11]:5 *C 55.660 128.475 +*N chany_top_out[11]:6 *C 55.660 124.485 +*N chany_top_out[11]:7 *C 55.615 124.440 +*N chany_top_out[11]:8 *C 52.938 124.440 + +*CAP +0 ropt_mt_inst_845:X 1e-06 +1 chany_top_out[11] 5.692552e-05 +2 chany_top_out[11]:2 5.692552e-05 +3 chany_top_out[11]:3 0.0002632536 +4 chany_top_out[11]:4 0.0002632536 +5 chany_top_out[11]:5 0.0002013623 +6 chany_top_out[11]:6 0.0002013623 +7 chany_top_out[11]:7 0.0001282978 +8 chany_top_out[11]:8 0.0001282978 +9 chany_top_out[11]:6 ropt_net_190:12 4.708438e-05 +10 chany_top_out[11]:4 ropt_net_190:9 7.350829e-05 +11 chany_top_out[11]:5 ropt_net_190:11 4.708438e-05 +12 chany_top_out[11]:3 ropt_net_190:8 7.350829e-05 +13 chany_top_out[11]:8 ropt_net_225:2 2.883896e-06 +14 chany_top_out[11]:8 ropt_net_225:4 0.0001083967 +15 chany_top_out[11]:7 ropt_net_225:3 2.883896e-06 +16 chany_top_out[11]:7 ropt_net_225:5 0.0001083967 + +*RES +0 ropt_mt_inst_845:X chany_top_out[11]:8 0.152 +1 chany_top_out[11]:8 chany_top_out[11]:7 0.002390625 +2 chany_top_out[11]:7 chany_top_out[11]:6 0.0045 +3 chany_top_out[11]:6 chany_top_out[11]:5 0.0035625 +4 chany_top_out[11]:4 chany_top_out[11]:3 0.004026785 +5 chany_top_out[11]:5 chany_top_out[11]:4 0.0045 +6 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +7 chany_top_out[11]:2 chany_top_out[11] 0.0006294643 + +*END + +*D_NET chany_top_out[17] 0.001018009 //LENGTH 7.830 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_858:X O *L 0 *C 58.085 127.160 +*P chany_top_out[17] O *L 0.7423 *C 52.900 129.235 +*N chany_top_out[17]:2 *C 54.740 129.200 +*N chany_top_out[17]:3 *C 54.740 127.205 +*N chany_top_out[17]:4 *C 54.785 127.160 +*N chany_top_out[17]:5 *C 58.047 127.160 + +*CAP +0 ropt_mt_inst_858:X 1e-06 +1 chany_top_out[17] 0.0001029002 +2 chany_top_out[17]:2 0.0002374555 +3 chany_top_out[17]:3 0.0001345553 +4 chany_top_out[17]:4 0.0002710489 +5 chany_top_out[17]:5 0.0002710489 + +*RES +0 ropt_mt_inst_858:X chany_top_out[17]:5 0.152 +1 chany_top_out[17]:4 chany_top_out[17]:3 0.0045 +2 chany_top_out[17]:3 chany_top_out[17]:2 0.00178125 +3 chany_top_out[17]:5 chany_top_out[17]:4 0.002912947 +4 chany_top_out[17]:2 chany_top_out[17] 0.001642857 + +*END + +*D_NET BUF_net_86 0.00177093 //LENGTH 13.570 LUMPCC 0 DR + +*CONN +*I BUFT_RR_86:X O *L 0 *C 66.700 121.720 +*I BUFT_P_160:A I *L 0.001766 *C 54.740 121.040 +*N BUF_net_86:2 *C 54.778 121.040 +*N BUF_net_86:3 *C 55.615 121.040 +*N BUF_net_86:4 *C 55.660 121.085 +*N BUF_net_86:5 *C 55.660 121.675 +*N BUF_net_86:6 *C 55.705 121.720 +*N BUF_net_86:7 *C 66.663 121.720 + +*CAP +0 BUFT_RR_86:X 1e-06 +1 BUFT_P_160:A 1e-06 +2 BUF_net_86:2 7.199548e-05 +3 BUF_net_86:3 7.199548e-05 +4 BUF_net_86:4 5.822818e-05 +5 BUF_net_86:5 5.822818e-05 +6 BUF_net_86:6 0.0007542414 +7 BUF_net_86:7 0.0007542414 + +*RES +0 BUFT_RR_86:X BUF_net_86:7 0.152 +1 BUF_net_86:2 BUFT_P_160:A 0.152 +2 BUF_net_86:3 BUF_net_86:2 0.0007477679 +3 BUF_net_86:4 BUF_net_86:3 0.0045 +4 BUF_net_86:6 BUF_net_86:5 0.0045 +5 BUF_net_86:5 BUF_net_86:4 0.0005267857 +6 BUF_net_86:7 BUF_net_86:6 0.009783483 + +*END + +*D_NET chany_top_out[6] 0.001193018 //LENGTH 10.025 LUMPCC 0.0002310612 DR + +*CONN +*I BUFT_P_162:X O *L 0 *C 9.465 124.440 +*P chany_top_out[6] O *L 0.7423 *C 5.520 129.350 +*N chany_top_out[6]:2 *C 5.520 125.128 +*N chany_top_out[6]:3 *C 5.540 125.120 +*N chany_top_out[6]:4 *C 6.433 125.120 +*N chany_top_out[6]:5 *C 6.440 125.062 +*N chany_top_out[6]:6 *C 6.440 124.485 +*N chany_top_out[6]:7 *C 6.485 124.440 +*N chany_top_out[6]:8 *C 9.428 124.440 + +*CAP +0 BUFT_P_162:X 1e-06 +1 chany_top_out[6] 0.0002103981 +2 chany_top_out[6]:2 0.0002103981 +3 chany_top_out[6]:3 3.645176e-05 +4 chany_top_out[6]:4 3.645176e-05 +5 chany_top_out[6]:5 4.685254e-05 +6 chany_top_out[6]:6 4.685254e-05 +7 chany_top_out[6]:7 0.000186776 +8 chany_top_out[6]:8 0.000186776 +9 chany_top_out[6]:8 ropt_net_221:9 3.632892e-05 +10 chany_top_out[6]:7 ropt_net_221:8 3.632892e-05 +11 chany_top_out[6]:6 ropt_net_221:7 4.180944e-06 +12 chany_top_out[6]:5 ropt_net_221:6 4.180944e-06 +13 chany_top_out[6]:6 ropt_net_210:3 1.93977e-06 +14 chany_top_out[6]:5 ropt_net_210:4 1.93977e-06 +15 chany_top_out[6]:4 ropt_net_210:6 7.308096e-05 +16 chany_top_out[6]:3 ropt_net_210:5 7.308096e-05 + +*RES +0 BUFT_P_162:X chany_top_out[6]:8 0.152 +1 chany_top_out[6]:8 chany_top_out[6]:7 0.002627232 +2 chany_top_out[6]:7 chany_top_out[6]:6 0.0045 +3 chany_top_out[6]:6 chany_top_out[6]:5 0.000515625 +4 chany_top_out[6]:5 chany_top_out[6]:4 0.00341 +5 chany_top_out[6]:4 chany_top_out[6]:3 0.000139825 +6 chany_top_out[6]:3 chany_top_out[6]:2 0.00341 +7 chany_top_out[6]:2 chany_top_out[6] 0.0006615249 + +*END + +*D_NET chany_top_in[6] 0.01761341 //LENGTH 142.965 LUMPCC 0.005629398 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 69.460 129.270 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.780 41.820 +*I ropt_mt_inst_816:A I *L 0.001767 *C 69.000 9.520 +*I mux_right_track_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 62.735 124.100 +*N chany_top_in[6]:4 *C 62.773 124.100 +*N chany_top_in[6]:5 *C 68.080 124.100 +*N chany_top_in[6]:6 *C 67.680 119.680 +*N chany_top_in[6]:7 *C 68.963 9.520 +*N chany_top_in[6]:8 *C 65.825 9.520 +*N chany_top_in[6]:9 *C 65.780 9.520 +*N chany_top_in[6]:10 *C 65.780 22.780 +*N chany_top_in[6]:11 *C 67.160 22.780 +*N chany_top_in[6]:12 *C 67.160 39.055 +*N chany_top_in[6]:13 *C 67.205 39.100 +*N chany_top_in[6]:14 *C 68.495 39.100 +*N chany_top_in[6]:15 *C 68.540 39.145 +*N chany_top_in[6]:16 *C 72.780 41.820 +*N chany_top_in[6]:17 *C 72.680 41.480 +*N chany_top_in[6]:18 *C 68.585 41.480 +*N chany_top_in[6]:19 *C 68.540 41.480 +*N chany_top_in[6]:20 *C 68.540 49.583 +*N chany_top_in[6]:21 *C 68.538 49.640 +*N chany_top_in[6]:22 *C 68.095 49.640 +*N chany_top_in[6]:23 *C 68.080 49.648 +*N chany_top_in[6]:24 *C 68.080 99.475 +*N chany_top_in[6]:25 *C 68.080 119.672 +*N chany_top_in[6]:26 *C 68.080 119.680 +*N chany_top_in[6]:27 *C 68.080 119.738 +*N chany_top_in[6]:28 *C 68.080 123.375 +*N chany_top_in[6]:29 *C 68.080 123.420 +*N chany_top_in[6]:30 *C 69.415 123.420 +*N chany_top_in[6]:31 *C 69.460 123.465 + +*CAP +0 chany_top_in[6] 0.0003374085 +1 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +2 ropt_mt_inst_816:A 1e-06 +3 mux_right_track_6\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[6]:4 0.0003173963 +5 chany_top_in[6]:5 0.0003675909 +6 chany_top_in[6]:6 7.503515e-05 +7 chany_top_in[6]:7 0.0002334505 +8 chany_top_in[6]:8 0.0002334505 +9 chany_top_in[6]:9 0.000678441 +10 chany_top_in[6]:10 0.0007196222 +11 chany_top_in[6]:11 0.0007269665 +12 chany_top_in[6]:12 0.0006583298 +13 chany_top_in[6]:13 0.0001042215 +14 chany_top_in[6]:14 0.0001042215 +15 chany_top_in[6]:15 8.907885e-05 +16 chany_top_in[6]:16 5.80126e-05 +17 chany_top_in[6]:17 0.0003370766 +18 chany_top_in[6]:18 0.0003084554 +19 chany_top_in[6]:19 0.0006123807 +20 chany_top_in[6]:20 0.0004924008 +21 chany_top_in[6]:21 8.352509e-05 +22 chany_top_in[6]:22 8.352509e-05 +23 chany_top_in[6]:23 0.001327776 +24 chany_top_in[6]:24 0.002081663 +25 chany_top_in[6]:25 0.0007538875 +26 chany_top_in[6]:26 7.503515e-05 +27 chany_top_in[6]:27 0.0002562002 +28 chany_top_in[6]:28 0.0002562002 +29 chany_top_in[6]:29 0.0001612235 +30 chany_top_in[6]:30 0.000111029 +31 chany_top_in[6]:31 0.0003374085 +32 chany_top_in[6]:25 chany_top_in[4]:21 0.0004320639 +33 chany_top_in[6]:23 chany_top_in[4]:19 0.0009255211 +34 chany_top_in[6]:23 chany_top_in[4]:20 8.809994e-05 +35 chany_top_in[6]:20 chany_top_in[4]:17 1.085351e-06 +36 chany_top_in[6]:15 chany_top_in[4]:16 2.767161e-08 +37 chany_top_in[6]:19 chany_top_in[4]:16 1.085351e-06 +38 chany_top_in[6]:19 chany_top_in[4]:17 2.767161e-08 +39 chany_top_in[6]:24 chany_top_in[4]:20 0.001357585 +40 chany_top_in[6]:24 chany_top_in[4]:21 8.809994e-05 +41 chany_top_in[6]:25 chany_top_in[5]:17 7.22581e-05 +42 chany_top_in[6]:23 chany_top_in[5]:15 0.0006914637 +43 chany_top_in[6]:23 chany_top_in[5]:16 0.0002936183 +44 chany_top_in[6]:12 chany_top_in[5]:11 4.834919e-05 +45 chany_top_in[6]:12 chany_top_in[5]:12 4.515565e-05 +46 chany_top_in[6]:9 chany_top_in[5]:8 2.05486e-05 +47 chany_top_in[6]:10 chany_top_in[5]:11 2.05486e-05 +48 chany_top_in[6]:11 chany_top_in[5]:8 4.834919e-05 +49 chany_top_in[6]:11 chany_top_in[5]:11 4.515565e-05 +50 chany_top_in[6]:24 chany_top_in[5]:16 0.0007637218 +51 chany_top_in[6]:24 chany_top_in[5]:17 0.0002936183 +52 chany_top_in[6]:20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.323877e-05 +53 chany_top_in[6]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.871374e-05 +54 chany_top_in[6]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.151921e-05 +55 chany_top_in[6]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.029695e-05 +56 chany_top_in[6]:19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.323877e-05 +57 chany_top_in[6]:19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.871374e-05 +58 chany_top_in[6]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.029695e-05 +59 chany_top_in[6]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.151921e-05 +60 chany_top_in[6]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.273899e-05 +61 chany_top_in[6]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.273899e-05 + +*RES +0 chany_top_in[6] chany_top_in[6]:31 0.005183036 +1 chany_top_in[6]:29 chany_top_in[6]:28 0.0045 +2 chany_top_in[6]:29 chany_top_in[6]:5 0.000607143 +3 chany_top_in[6]:28 chany_top_in[6]:27 0.003247768 +4 chany_top_in[6]:27 chany_top_in[6]:26 0.00341 +5 chany_top_in[6]:26 chany_top_in[6]:25 0.00341 +6 chany_top_in[6]:26 chany_top_in[6]:6 5.69697e-05 +7 chany_top_in[6]:25 chany_top_in[6]:24 0.003164275 +8 chany_top_in[6]:22 chany_top_in[6]:21 6.499219e-05 +9 chany_top_in[6]:23 chany_top_in[6]:22 0.00341 +10 chany_top_in[6]:20 chany_top_in[6]:19 0.007234375 +11 chany_top_in[6]:21 chany_top_in[6]:20 0.00341 +12 chany_top_in[6]:4 mux_right_track_6\/mux_l1_in_0_:A0 0.152 +13 chany_top_in[6]:14 chany_top_in[6]:13 0.001151786 +14 chany_top_in[6]:15 chany_top_in[6]:14 0.0045 +15 chany_top_in[6]:13 chany_top_in[6]:12 0.0045 +16 chany_top_in[6]:12 chany_top_in[6]:11 0.01453125 +17 chany_top_in[6]:8 chany_top_in[6]:7 0.002801339 +18 chany_top_in[6]:9 chany_top_in[6]:8 0.0045 +19 chany_top_in[6]:7 ropt_mt_inst_816:A 0.152 +20 chany_top_in[6]:30 chany_top_in[6]:29 0.001191964 +21 chany_top_in[6]:31 chany_top_in[6]:30 0.0045 +22 chany_top_in[6]:18 chany_top_in[6]:17 0.00365625 +23 chany_top_in[6]:19 chany_top_in[6]:18 0.0045 +24 chany_top_in[6]:19 chany_top_in[6]:15 0.002084821 +25 chany_top_in[6]:16 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +26 chany_top_in[6]:5 chany_top_in[6]:4 0.00473884 +27 chany_top_in[6]:17 chany_top_in[6]:16 0.0003035715 +28 chany_top_in[6]:10 chany_top_in[6]:9 0.01183929 +29 chany_top_in[6]:11 chany_top_in[6]:10 0.001232143 +30 chany_top_in[6]:24 chany_top_in[6]:23 0.007806308 + +*END + +*D_NET chany_top_out[12] 0.005178115 //LENGTH 54.575 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l3_in_0_:X O *L 0 *C 17.240 85.680 +*P chany_top_out[12] O *L 0.7423 *C 7.360 129.270 +*N chany_top_out[12]:2 *C 7.360 127.205 +*N chany_top_out[12]:3 *C 7.405 127.160 +*N chany_top_out[12]:4 *C 14.675 127.160 +*N chany_top_out[12]:5 *C 14.720 127.115 +*N chany_top_out[12]:6 *C 14.720 85.725 +*N chany_top_out[12]:7 *C 14.765 85.680 +*N chany_top_out[12]:8 *C 17.203 85.680 + +*CAP +0 mux_top_track_24\/mux_l3_in_0_:X 1e-06 +1 chany_top_out[12] 0.000109677 +2 chany_top_out[12]:2 0.000109677 +3 chany_top_out[12]:3 0.0004710171 +4 chany_top_out[12]:4 0.0004710171 +5 chany_top_out[12]:5 0.001869807 +6 chany_top_out[12]:6 0.001869807 +7 chany_top_out[12]:7 0.000138057 +8 chany_top_out[12]:8 0.000138057 + +*RES +0 mux_top_track_24\/mux_l3_in_0_:X chany_top_out[12]:8 0.152 +1 chany_top_out[12]:8 chany_top_out[12]:7 0.002176339 +2 chany_top_out[12]:7 chany_top_out[12]:6 0.0045 +3 chany_top_out[12]:6 chany_top_out[12]:5 0.03695536 +4 chany_top_out[12]:4 chany_top_out[12]:3 0.006491072 +5 chany_top_out[12]:5 chany_top_out[12]:4 0.0045 +6 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +7 chany_top_out[12]:2 chany_top_out[12] 0.00184375 + +*END + +*D_NET chanx_right_out[8] 0.002209181 //LENGTH 20.860 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.480 58.820 +*P chanx_right_out[8] O *L 0.7423 *C 111.863 46.240 +*N chanx_right_out[8]:2 *C 111.780 46.240 +*N chanx_right_out[8]:3 *C 111.780 46.297 +*N chanx_right_out[8]:4 *C 111.780 58.775 +*N chanx_right_out[8]:5 *C 111.735 58.820 +*N chanx_right_out[8]:6 *C 104.517 58.820 + +*CAP +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[8] 3.278921e-05 +2 chanx_right_out[8]:2 3.278921e-05 +3 chanx_right_out[8]:3 0.0006489993 +4 chanx_right_out[8]:4 0.0006489993 +5 chanx_right_out[8]:5 0.0004223018 +6 chanx_right_out[8]:6 0.0004223018 + +*RES +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:6 chanx_right_out[8]:5 0.006444197 +2 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.01114062 +4 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +5 chanx_right_out[8]:2 chanx_right_out[8] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.001944525 //LENGTH 16.825 LUMPCC 0.0002248269 DR + +*CONN +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 39.405 50.320 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 35.135 55.420 +*I mux_right_track_26\/mux_l1_in_0_:S I *L 0.00357 *C 37.620 58.480 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 35.172 55.420 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 37.675 55.420 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 37.720 55.465 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 37.720 58.435 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 37.765 58.480 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 39.055 58.480 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 39.100 58.435 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 39.100 50.365 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 39.100 50.320 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 39.405 50.320 + +*CAP +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_26\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 0.0001838713 +4 mux_tree_tapbuf_size2_0_sram[0]:4 0.0001838713 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.0001594326 +6 mux_tree_tapbuf_size2_0_sram[0]:6 0.0001594326 +7 mux_tree_tapbuf_size2_0_sram[0]:7 0.0001391298 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0001391298 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0003261142 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0003261142 +11 mux_tree_tapbuf_size2_0_sram[0]:11 5.180012e-05 +12 mux_tree_tapbuf_size2_0_sram[0]:12 4.780204e-05 +13 mux_tree_tapbuf_size2_0_sram[0]:6 chanx_right_in[19]:4 4.259799e-07 +14 mux_tree_tapbuf_size2_0_sram[0]:5 chanx_right_in[19]:5 4.259799e-07 +15 mux_tree_tapbuf_size2_0_sram[0]:9 chanx_right_in[19]:4 0.0001119875 +16 mux_tree_tapbuf_size2_0_sram[0]:10 chanx_right_in[19]:5 0.0001119875 + +*RES +0 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size2_0_sram[0]:7 mux_right_track_26\/mux_l1_in_0_:S 0.152 +3 mux_tree_tapbuf_size2_0_sram[0]:6 mux_tree_tapbuf_size2_0_sram[0]:5 0.002651786 +4 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 0.002234375 +5 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_0_sram[0]:3 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.001151786 +8 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.007205357 +11 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.001390601 //LENGTH 10.550 LUMPCC 0.00024554 DR + +*CONN +*I mem_right_track_18\/FTB_24__54:X O *L 0 *C 85.795 77.180 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 78.375 75.140 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 78.375 75.140 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 78.200 75.140 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 78.200 75.185 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 78.200 77.135 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 78.245 77.180 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 85.758 77.180 + +*CAP +0 mem_right_track_18\/FTB_24__54:X 1e-06 +1 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 5.185701e-05 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 5.748253e-05 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 9.424635e-05 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 9.424635e-05 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0004226143 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0004226143 +8 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_1_sram[0]:14 6.051376e-05 +9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_1_sram[0]:11 6.051376e-05 +10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_1_sram[1]:7 6.225622e-05 +11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_1_sram[1]:6 6.225622e-05 + +*RES +0 mem_right_track_18\/FTB_24__54:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.00670759 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[2] 0.001883995 //LENGTH 14.850 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 39.865 107.780 +*I mux_right_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 38.980 105.060 +*I mem_right_track_8\/FTB_15__45:A I *L 0.001746 *C 31.740 102.000 +*N mux_tree_tapbuf_size4_2_sram[2]:3 *C 31.740 102.000 +*N mux_tree_tapbuf_size4_2_sram[2]:4 *C 31.740 102.045 +*N mux_tree_tapbuf_size4_2_sram[2]:5 *C 31.740 105.015 +*N mux_tree_tapbuf_size4_2_sram[2]:6 *C 31.785 105.060 +*N mux_tree_tapbuf_size4_2_sram[2]:7 *C 38.980 105.060 +*N mux_tree_tapbuf_size4_2_sram[2]:8 *C 39.515 105.060 +*N mux_tree_tapbuf_size4_2_sram[2]:9 *C 39.560 105.105 +*N mux_tree_tapbuf_size4_2_sram[2]:10 *C 39.560 107.735 +*N mux_tree_tapbuf_size4_2_sram[2]:11 *C 39.560 107.780 +*N mux_tree_tapbuf_size4_2_sram[2]:12 *C 39.865 107.780 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_8\/FTB_15__45:A 1e-06 +3 mux_tree_tapbuf_size4_2_sram[2]:3 3.25107e-05 +4 mux_tree_tapbuf_size4_2_sram[2]:4 0.0001812346 +5 mux_tree_tapbuf_size4_2_sram[2]:5 0.0001812346 +6 mux_tree_tapbuf_size4_2_sram[2]:6 0.0004495364 +7 mux_tree_tapbuf_size4_2_sram[2]:7 0.0005285357 +8 mux_tree_tapbuf_size4_2_sram[2]:8 5.084218e-05 +9 mux_tree_tapbuf_size4_2_sram[2]:9 0.0001757792 +10 mux_tree_tapbuf_size4_2_sram[2]:10 0.0001757792 +11 mux_tree_tapbuf_size4_2_sram[2]:11 5.340396e-05 +12 mux_tree_tapbuf_size4_2_sram[2]:12 5.213859e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_2_sram[2]:12 0.152 +1 mux_tree_tapbuf_size4_2_sram[2]:7 mux_right_track_8\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_2_sram[2]:7 mux_tree_tapbuf_size4_2_sram[2]:6 0.006424107 +3 mux_tree_tapbuf_size4_2_sram[2]:8 mux_tree_tapbuf_size4_2_sram[2]:7 0.0004776785 +4 mux_tree_tapbuf_size4_2_sram[2]:9 mux_tree_tapbuf_size4_2_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size4_2_sram[2]:11 mux_tree_tapbuf_size4_2_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size4_2_sram[2]:10 mux_tree_tapbuf_size4_2_sram[2]:9 0.002348214 +7 mux_tree_tapbuf_size4_2_sram[2]:12 mux_tree_tapbuf_size4_2_sram[2]:11 0.0001657609 +8 mux_tree_tapbuf_size4_2_sram[2]:3 mem_right_track_8\/FTB_15__45:A 0.152 +9 mux_tree_tapbuf_size4_2_sram[2]:4 mux_tree_tapbuf_size4_2_sram[2]:3 0.0045 +10 mux_tree_tapbuf_size4_2_sram[2]:6 mux_tree_tapbuf_size4_2_sram[2]:5 0.0045 +11 mux_tree_tapbuf_size4_2_sram[2]:5 mux_tree_tapbuf_size4_2_sram[2]:4 0.002651786 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_4_ccff_tail[0] 0.0007180672 //LENGTH 6.230 LUMPCC 0 DR + +*CONN +*I mem_right_track_12\/FTB_17__47:X O *L 0 *C 71.055 93.500 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.795 91.460 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:2 *C 67.833 91.460 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:3 *C 69.415 91.460 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:4 *C 69.460 91.505 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:5 *C 69.460 93.455 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:6 *C 69.505 93.500 +*N mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:7 *C 71.017 93.500 + +*CAP +0 mem_right_track_12\/FTB_17__47:X 1e-06 +1 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:2 0.0001149305 +3 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:3 0.0001149305 +4 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:4 0.000137676 +5 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:5 0.000137676 +6 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:6 0.0001054271 +7 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:7 0.0001054271 + +*RES +0 mem_right_track_12\/FTB_17__47:X mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:2 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:2 0.001412946 +3 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_4_ccff_tail[0]:6 0.001350446 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[2] 0.003025533 //LENGTH 23.160 LUMPCC 0.0004584637 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 48.145 47.600 +*I mem_bottom_track_25\/FTB_12__42:A I *L 0.001746 *C 38.180 44.880 +*I mux_bottom_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 56.940 44.880 +*N mux_tree_tapbuf_size5_4_sram[2]:3 *C 56.903 44.880 +*N mux_tree_tapbuf_size5_4_sram[2]:4 *C 38.218 44.880 +*N mux_tree_tapbuf_size5_4_sram[2]:5 *C 47.380 44.880 +*N mux_tree_tapbuf_size5_4_sram[2]:6 *C 47.380 44.925 +*N mux_tree_tapbuf_size5_4_sram[2]:7 *C 47.380 47.555 +*N mux_tree_tapbuf_size5_4_sram[2]:8 *C 47.425 47.600 +*N mux_tree_tapbuf_size5_4_sram[2]:9 *C 48.108 47.600 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_25\/FTB_12__42:A 1e-06 +2 mux_bottom_track_25\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_4_sram[2]:3 0.0005129902 +4 mux_tree_tapbuf_size5_4_sram[2]:4 0.000479735 +5 mux_tree_tapbuf_size5_4_sram[2]:5 0.001024408 +6 mux_tree_tapbuf_size5_4_sram[2]:6 0.000194563 +7 mux_tree_tapbuf_size5_4_sram[2]:7 0.000194563 +8 mux_tree_tapbuf_size5_4_sram[2]:8 7.890485e-05 +9 mux_tree_tapbuf_size5_4_sram[2]:9 7.890485e-05 +10 mux_tree_tapbuf_size5_4_sram[2]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001037261 +11 mux_tree_tapbuf_size5_4_sram[2]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.396523e-05 +12 mux_tree_tapbuf_size5_4_sram[2]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.396523e-05 +13 mux_tree_tapbuf_size5_4_sram[2]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001037261 +14 mux_tree_tapbuf_size5_4_sram[2]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.154052e-05 +15 mux_tree_tapbuf_size5_4_sram[2]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.154052e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_4_sram[2]:9 0.152 +1 mux_tree_tapbuf_size5_4_sram[2]:4 mem_bottom_track_25\/FTB_12__42:A 0.152 +2 mux_tree_tapbuf_size5_4_sram[2]:3 mux_bottom_track_25\/mux_l3_in_0_:S 0.152 +3 mux_tree_tapbuf_size5_4_sram[2]:5 mux_tree_tapbuf_size5_4_sram[2]:4 0.008180804 +4 mux_tree_tapbuf_size5_4_sram[2]:5 mux_tree_tapbuf_size5_4_sram[2]:3 0.008502233 +5 mux_tree_tapbuf_size5_4_sram[2]:6 mux_tree_tapbuf_size5_4_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size5_4_sram[2]:8 mux_tree_tapbuf_size5_4_sram[2]:7 0.0045 +7 mux_tree_tapbuf_size5_4_sram[2]:7 mux_tree_tapbuf_size5_4_sram[2]:6 0.002348214 +8 mux_tree_tapbuf_size5_4_sram[2]:9 mux_tree_tapbuf_size5_4_sram[2]:8 0.0006093751 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[1] 0.003861567 //LENGTH 29.795 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.145 66.300 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 67.720 63.920 +*I mux_top_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 64.040 61.495 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 54.915 64.260 +*N mux_tree_tapbuf_size6_2_sram[1]:4 *C 64.040 61.570 +*N mux_tree_tapbuf_size6_2_sram[1]:5 *C 54.953 64.260 +*N mux_tree_tapbuf_size6_2_sram[1]:6 *C 55.615 64.260 +*N mux_tree_tapbuf_size6_2_sram[1]:7 *C 55.660 64.215 +*N mux_tree_tapbuf_size6_2_sram[1]:8 *C 55.660 61.245 +*N mux_tree_tapbuf_size6_2_sram[1]:9 *C 55.705 61.200 +*N mux_tree_tapbuf_size6_2_sram[1]:10 *C 63.983 61.200 +*N mux_tree_tapbuf_size6_2_sram[1]:11 *C 64.040 61.495 +*N mux_tree_tapbuf_size6_2_sram[1]:12 *C 64.040 61.880 +*N mux_tree_tapbuf_size6_2_sram[1]:13 *C 66.655 61.880 +*N mux_tree_tapbuf_size6_2_sram[1]:14 *C 66.700 61.925 +*N mux_tree_tapbuf_size6_2_sram[1]:15 *C 67.683 63.920 +*N mux_tree_tapbuf_size6_2_sram[1]:16 *C 66.285 63.920 +*N mux_tree_tapbuf_size6_2_sram[1]:17 *C 66.240 63.920 +*N mux_tree_tapbuf_size6_2_sram[1]:18 *C 66.700 63.920 +*N mux_tree_tapbuf_size6_2_sram[1]:19 *C 67.160 63.920 +*N mux_tree_tapbuf_size6_2_sram[1]:20 *C 67.160 65.222 +*N mux_tree_tapbuf_size6_2_sram[1]:21 *C 67.168 65.280 +*N mux_tree_tapbuf_size6_2_sram[1]:22 *C 71.293 65.280 +*N mux_tree_tapbuf_size6_2_sram[1]:23 *C 71.300 65.338 +*N mux_tree_tapbuf_size6_2_sram[1]:24 *C 71.300 66.255 +*N mux_tree_tapbuf_size6_2_sram[1]:25 *C 71.300 66.300 +*N mux_tree_tapbuf_size6_2_sram[1]:26 *C 71.145 66.300 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_8\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_2_sram[1]:4 1.407401e-05 +5 mux_tree_tapbuf_size6_2_sram[1]:5 8.76305e-05 +6 mux_tree_tapbuf_size6_2_sram[1]:6 8.76305e-05 +7 mux_tree_tapbuf_size6_2_sram[1]:7 0.0001821742 +8 mux_tree_tapbuf_size6_2_sram[1]:8 0.0001821742 +9 mux_tree_tapbuf_size6_2_sram[1]:9 0.0004813911 +10 mux_tree_tapbuf_size6_2_sram[1]:10 0.0005023798 +11 mux_tree_tapbuf_size6_2_sram[1]:11 8.437295e-05 +12 mux_tree_tapbuf_size6_2_sram[1]:12 0.0002265501 +13 mux_tree_tapbuf_size6_2_sram[1]:13 0.0002064497 +14 mux_tree_tapbuf_size6_2_sram[1]:14 0.0001274754 +15 mux_tree_tapbuf_size6_2_sram[1]:15 0.0001288906 +16 mux_tree_tapbuf_size6_2_sram[1]:16 0.0001288906 +17 mux_tree_tapbuf_size6_2_sram[1]:17 6.134721e-05 +18 mux_tree_tapbuf_size6_2_sram[1]:18 0.000184096 +19 mux_tree_tapbuf_size6_2_sram[1]:19 0.0001325627 +20 mux_tree_tapbuf_size6_2_sram[1]:20 0.0001057564 +21 mux_tree_tapbuf_size6_2_sram[1]:21 0.0003248383 +22 mux_tree_tapbuf_size6_2_sram[1]:22 0.0003248383 +23 mux_tree_tapbuf_size6_2_sram[1]:23 8.804713e-05 +24 mux_tree_tapbuf_size6_2_sram[1]:24 8.804713e-05 +25 mux_tree_tapbuf_size6_2_sram[1]:25 5.708817e-05 +26 mux_tree_tapbuf_size6_2_sram[1]:26 5.086105e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_2_sram[1]:26 0.152 +1 mux_tree_tapbuf_size6_2_sram[1]:15 mux_top_track_8\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[1]:16 mux_tree_tapbuf_size6_2_sram[1]:15 0.001247768 +3 mux_tree_tapbuf_size6_2_sram[1]:17 mux_tree_tapbuf_size6_2_sram[1]:16 0.0045 +4 mux_tree_tapbuf_size6_2_sram[1]:13 mux_tree_tapbuf_size6_2_sram[1]:12 0.002334822 +5 mux_tree_tapbuf_size6_2_sram[1]:14 mux_tree_tapbuf_size6_2_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size6_2_sram[1]:20 mux_tree_tapbuf_size6_2_sram[1]:19 0.001162947 +7 mux_tree_tapbuf_size6_2_sram[1]:21 mux_tree_tapbuf_size6_2_sram[1]:20 0.00341 +8 mux_tree_tapbuf_size6_2_sram[1]:23 mux_tree_tapbuf_size6_2_sram[1]:22 0.00341 +9 mux_tree_tapbuf_size6_2_sram[1]:22 mux_tree_tapbuf_size6_2_sram[1]:21 0.00064625 +10 mux_tree_tapbuf_size6_2_sram[1]:25 mux_tree_tapbuf_size6_2_sram[1]:24 0.0045 +11 mux_tree_tapbuf_size6_2_sram[1]:24 mux_tree_tapbuf_size6_2_sram[1]:23 0.0008191963 +12 mux_tree_tapbuf_size6_2_sram[1]:26 mux_tree_tapbuf_size6_2_sram[1]:25 8.423914e-05 +13 mux_tree_tapbuf_size6_2_sram[1]:11 mux_top_track_8\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:10 0.0001715116 +15 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:4 4.360465e-05 +16 mux_tree_tapbuf_size6_2_sram[1]:9 mux_tree_tapbuf_size6_2_sram[1]:8 0.0045 +17 mux_tree_tapbuf_size6_2_sram[1]:8 mux_tree_tapbuf_size6_2_sram[1]:7 0.002651786 +18 mux_tree_tapbuf_size6_2_sram[1]:6 mux_tree_tapbuf_size6_2_sram[1]:5 0.0005915179 +19 mux_tree_tapbuf_size6_2_sram[1]:7 mux_tree_tapbuf_size6_2_sram[1]:6 0.0045 +20 mux_tree_tapbuf_size6_2_sram[1]:5 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +21 mux_tree_tapbuf_size6_2_sram[1]:10 mux_tree_tapbuf_size6_2_sram[1]:9 0.007390625 +22 mux_tree_tapbuf_size6_2_sram[1]:12 mux_tree_tapbuf_size6_2_sram[1]:11 0.00034375 +23 mux_tree_tapbuf_size6_2_sram[1]:18 mux_tree_tapbuf_size6_2_sram[1]:17 0.0004107143 +24 mux_tree_tapbuf_size6_2_sram[1]:18 mux_tree_tapbuf_size6_2_sram[1]:14 0.00178125 +25 mux_tree_tapbuf_size6_2_sram[1]:19 mux_tree_tapbuf_size6_2_sram[1]:18 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[2] 0.001611958 //LENGTH 12.050 LUMPCC 0.0003619839 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 78.045 115.260 +*I mux_right_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 77.180 112.200 +*I mem_right_track_2\/FTB_20__50:A I *L 0.001746 *C 72.680 110.160 +*N mux_tree_tapbuf_size7_0_sram[2]:3 *C 72.680 110.160 +*N mux_tree_tapbuf_size7_0_sram[2]:4 *C 72.680 110.500 +*N mux_tree_tapbuf_size7_0_sram[2]:5 *C 77.695 110.500 +*N mux_tree_tapbuf_size7_0_sram[2]:6 *C 77.740 110.545 +*N mux_tree_tapbuf_size7_0_sram[2]:7 *C 77.218 112.200 +*N mux_tree_tapbuf_size7_0_sram[2]:8 *C 77.695 112.200 +*N mux_tree_tapbuf_size7_0_sram[2]:9 *C 77.740 112.200 +*N mux_tree_tapbuf_size7_0_sram[2]:10 *C 77.740 115.215 +*N mux_tree_tapbuf_size7_0_sram[2]:11 *C 77.740 115.260 +*N mux_tree_tapbuf_size7_0_sram[2]:12 *C 78.045 115.260 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_2\/FTB_20__50:A 1e-06 +3 mux_tree_tapbuf_size7_0_sram[2]:3 5.783277e-05 +4 mux_tree_tapbuf_size7_0_sram[2]:4 0.000217204 +5 mux_tree_tapbuf_size7_0_sram[2]:5 0.000188852 +6 mux_tree_tapbuf_size7_0_sram[2]:6 0.0001003322 +7 mux_tree_tapbuf_size7_0_sram[2]:7 5.816312e-05 +8 mux_tree_tapbuf_size7_0_sram[2]:8 5.816312e-05 +9 mux_tree_tapbuf_size7_0_sram[2]:9 0.0002985493 +10 mux_tree_tapbuf_size7_0_sram[2]:10 0.0001677975 +11 mux_tree_tapbuf_size7_0_sram[2]:11 5.118565e-05 +12 mux_tree_tapbuf_size7_0_sram[2]:12 4.889421e-05 +13 mux_tree_tapbuf_size7_0_sram[2]:5 mux_tree_tapbuf_size7_0_sram[1]:5 0.0001809919 +14 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[1]:6 0.0001809919 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_0_sram[2]:12 0.152 +1 mux_tree_tapbuf_size7_0_sram[2]:5 mux_tree_tapbuf_size7_0_sram[2]:4 0.004477679 +2 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_0_sram[2]:5 0.0045 +3 mux_tree_tapbuf_size7_0_sram[2]:3 mem_right_track_2\/FTB_20__50:A 0.152 +4 mux_tree_tapbuf_size7_0_sram[2]:11 mux_tree_tapbuf_size7_0_sram[2]:10 0.0045 +5 mux_tree_tapbuf_size7_0_sram[2]:10 mux_tree_tapbuf_size7_0_sram[2]:9 0.002691964 +6 mux_tree_tapbuf_size7_0_sram[2]:12 mux_tree_tapbuf_size7_0_sram[2]:11 0.0001657609 +7 mux_tree_tapbuf_size7_0_sram[2]:8 mux_tree_tapbuf_size7_0_sram[2]:7 0.0004263393 +8 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:8 0.0045 +9 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:6 0.001477679 +10 mux_tree_tapbuf_size7_0_sram[2]:7 mux_right_track_2\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[2]:3 0.0003035715 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007246326 //LENGTH 5.765 LUMPCC 0.0001300397 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_2_:X O *L 0 *C 84.925 69.700 +*I mux_top_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 87.040 72.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 87.002 72.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 86.525 72.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 86.480 72.375 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 86.480 69.745 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 86.435 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 84.963 69.700 + +*CAP +0 mux_top_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.919965e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.919965e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001664513 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001664513 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.064552e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.064552e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_0_sram[0]:9 6.501986e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size6_0_sram[0]:8 6.501986e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000591599 //LENGTH 4.340 LUMPCC 0.0001048594 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 70.555 61.880 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.445 63.580 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.445 63.580 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.540 63.535 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 68.540 61.925 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 68.585 61.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 70.517 61.880 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.986047e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.25882e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.25882e-05 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548514 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548514 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.242972e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.242972e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0014375 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725447 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002874468 //LENGTH 27.110 LUMPCC 0.0001802407 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_1_:X O *L 0 *C 49.395 65.960 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 44.335 44.540 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 44.335 44.540 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 44.620 44.540 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 44.620 44.585 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 44.620 65.915 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 44.665 65.960 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 49.358 65.960 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.154956e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.570407e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0009968658 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0009968658 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002956212 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002956212 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[15]:5 6.779281e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[15]:9 2.232756e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[15]:4 6.779281e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[15]:8 2.232756e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01904464 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.004189732 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008807928 //LENGTH 7.560 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 93.205 41.820 +*I mux_bottom_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 93.285 36.380 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 93.323 36.380 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 93.795 36.380 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 93.840 36.425 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 93.840 41.775 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 93.795 41.820 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 93.243 41.820 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.425038e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.425038e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003089128 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003089128 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.623322e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.623322e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007702402 //LENGTH 4.605 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_1_:X O *L 0 *C 25.935 71.240 +*I mux_top_track_16\/mux_l3_in_0_:A0 I *L 0.005103 *C 21.620 71.240 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 21.658 71.240 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 25.898 71.240 + +*CAP +0 mux_top_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003841201 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003841201 + +*RES +0 mux_top_track_16\/mux_l2_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003785715 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001219524 //LENGTH 9.810 LUMPCC 0.0001006411 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 56.405 46.920 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 61.545 50.660 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 61.508 50.660 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.545 50.660 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.500 50.615 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.500 46.965 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 57.455 46.920 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 56.443 46.920 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002805633 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002805633 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001804337 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001804337 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.744427e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.744427e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[14]:10 5.032053e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[14]:9 5.032053e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003537947 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003258929 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.01085866 //LENGTH 75.230 LUMPCC 0.003101592 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_0_:X O *L 0 *C 41.685 104.040 +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 99.085 88.255 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 99.047 88.350 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 98.485 88.400 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 98.440 88.445 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 98.440 99.223 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 98.433 99.280 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 51.540 99.280 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 51.520 99.288 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 51.520 104.032 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 51.500 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 41.407 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 41.400 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 41.400 104.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 41.685 104.040 + +*CAP +0 mux_right_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.866972e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.866972e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0005872345 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005872345 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002387335 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002387335 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000191055 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.000191055 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0005794922 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0005794922 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.898365e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:13 6.359153e-05 +14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:14 6.492148e-05 +15 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 chany_top_in[5]:23 0.0002084401 +16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 chany_top_in[5]:22 0.0002084401 +17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 right_top_grid_pin_44_[0]:12 0.0004764815 +18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 right_top_grid_pin_44_[0]:16 1.109079e-05 +19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 right_top_grid_pin_44_[0]:20 0.0002094533 +20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 right_top_grid_pin_44_[0]:13 0.0004764815 +21 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 right_top_grid_pin_44_[0]:17 1.109079e-05 +22 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 right_top_grid_pin_44_[0]:21 0.0002094533 +23 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002255345 +24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002255345 +25 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004197958 +26 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004197958 + +*RES +0 mux_right_track_8\/mux_l3_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0001548913 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.00341 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.001581158 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00341 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0007433833 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.007346491 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.009622768 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005022322 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006512777 //LENGTH 5.020 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 69.285 102.000 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 71.300 99.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 71.300 99.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 71.300 99.665 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 71.300 101.955 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 71.255 102.000 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 69.323 102.000 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.134506e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001552294 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001552294 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001537369 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001537369 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725447 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001122609 //LENGTH 8.115 LUMPCC 0.0001508474 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_0_:X O *L 0 *C 86.765 79.900 +*I mux_right_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 92.100 77.860 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 92.062 77.860 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.985 77.860 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.940 77.905 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.940 79.855 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 86.940 79.900 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 86.765 79.900 + +*CAP +0 mux_right_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002895695 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002895695 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001385808 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001385808 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.687892e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.658192e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 prog_clk[0]:90 7.542368e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 prog_clk[0]:91 7.542368e-05 + +*RES +0 mux_right_track_16\/mux_l1_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004533482 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741072 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001045926 //LENGTH 10.630 LUMPCC 0.0001163883 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_0_:X O *L 0 *C 35.135 25.840 +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 33.310 17.550 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 33.310 17.550 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 33.580 17.680 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 33.580 17.725 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 33.580 25.795 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 33.625 25.840 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 35.098 25.840 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.391449e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.028605e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003196904 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003196904 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.697829e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.697829e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[18]:13 5.819413e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[18]:14 5.819413e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001467391 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.007205357 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ropt_net_221 0.0006805757 //LENGTH 5.845 LUMPCC 0.0001575626 DR + +*CONN +*I ropt_mt_inst_831:X O *L 0 *C 8.935 124.100 +*I ropt_mt_inst_841:A I *L 0.001767 *C 7.360 126.480 +*N ropt_net_221:2 *C 7.397 126.480 +*N ropt_net_221:3 *C 7.820 126.480 +*N ropt_net_221:4 *C 7.820 126.820 +*N ropt_net_221:5 *C 8.235 126.820 +*N ropt_net_221:6 *C 8.280 126.775 +*N ropt_net_221:7 *C 8.280 124.145 +*N ropt_net_221:8 *C 8.325 124.100 +*N ropt_net_221:9 *C 8.898 124.100 + +*CAP +0 ropt_mt_inst_831:X 1e-06 +1 ropt_mt_inst_841:A 1e-06 +2 ropt_net_221:2 3.435196e-05 +3 ropt_net_221:3 5.866706e-05 +4 ropt_net_221:4 6.850879e-05 +5 ropt_net_221:5 4.419369e-05 +6 ropt_net_221:6 0.0001272603 +7 ropt_net_221:7 0.0001272603 +8 ropt_net_221:8 3.038552e-05 +9 ropt_net_221:9 3.038552e-05 +10 ropt_net_221:7 chany_top_out[14]:6 3.544194e-05 +11 ropt_net_221:5 chany_top_out[14]:7 2.829482e-06 +12 ropt_net_221:6 chany_top_out[14]:5 3.544194e-05 +13 ropt_net_221:4 chany_top_out[14]:8 2.829482e-06 +14 ropt_net_221:9 chany_top_out[6]:8 3.632892e-05 +15 ropt_net_221:8 chany_top_out[6]:7 3.632892e-05 +16 ropt_net_221:7 chany_top_out[6]:6 4.180944e-06 +17 ropt_net_221:6 chany_top_out[6]:5 4.180944e-06 + +*RES +0 ropt_mt_inst_831:X ropt_net_221:9 0.152 +1 ropt_net_221:9 ropt_net_221:8 0.0005111608 +2 ropt_net_221:8 ropt_net_221:7 0.0045 +3 ropt_net_221:7 ropt_net_221:6 0.002348214 +4 ropt_net_221:5 ropt_net_221:4 0.0003705357 +5 ropt_net_221:6 ropt_net_221:5 0.0045 +6 ropt_net_221:2 ropt_mt_inst_841:A 0.152 +7 ropt_net_221:3 ropt_net_221:2 0.0003772322 +8 ropt_net_221:4 ropt_net_221:3 0.0003035715 + +*END + +*D_NET chanx_right_out[17] 0.0008354642 //LENGTH 5.540 LUMPCC 9.712813e-05 DR + +*CONN +*I ropt_mt_inst_853:X O *L 0 *C 107.180 66.980 +*P chanx_right_out[17] O *L 0.7423 *C 111.930 66.640 +*N chanx_right_out[17]:2 *C 107.648 66.640 +*N chanx_right_out[17]:3 *C 107.640 66.640 +*N chanx_right_out[17]:4 *C 107.640 66.980 +*N chanx_right_out[17]:5 *C 107.595 66.980 +*N chanx_right_out[17]:6 *C 107.218 66.980 + +*CAP +0 ropt_mt_inst_853:X 1e-06 +1 chanx_right_out[17] 0.0002544033 +2 chanx_right_out[17]:2 0.0002544033 +3 chanx_right_out[17]:3 6.166707e-05 +4 chanx_right_out[17]:4 6.229128e-05 +5 chanx_right_out[17]:5 5.228553e-05 +6 chanx_right_out[17]:6 5.228553e-05 +7 chanx_right_out[17] ropt_net_235:6 4.856407e-05 +8 chanx_right_out[17]:2 ropt_net_235:5 4.856407e-05 + +*RES +0 ropt_mt_inst_853:X chanx_right_out[17]:6 0.152 +1 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0003370535 +2 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.0001634615 +4 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +5 chanx_right_out[17]:2 chanx_right_out[17] 0.000670925 + +*END + +*D_NET chany_top_out[3] 0.001287199 //LENGTH 9.660 LUMPCC 0.0001429221 DR + +*CONN +*I BUFT_P_160:X O *L 0 *C 50.865 121.720 +*P chany_top_out[3] O *L 0.7423 *C 49.220 129.270 +*N chany_top_out[3]:2 *C 49.220 121.765 +*N chany_top_out[3]:3 *C 49.265 121.720 +*N chany_top_out[3]:4 *C 50.828 121.720 + +*CAP +0 BUFT_P_160:X 1e-06 +1 chany_top_out[3] 0.0004852381 +2 chany_top_out[3]:2 0.0004852381 +3 chany_top_out[3]:3 8.640034e-05 +4 chany_top_out[3]:4 8.640034e-05 +5 chany_top_out[3]:4 ropt_net_216:6 7.146107e-05 +6 chany_top_out[3]:3 ropt_net_216:7 7.146107e-05 + +*RES +0 BUFT_P_160:X chany_top_out[3]:4 0.152 +1 chany_top_out[3]:4 chany_top_out[3]:3 0.001395089 +2 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +3 chany_top_out[3]:2 chany_top_out[3] 0.006700893 + +*END + +*D_NET chany_top_in[10] 0.0145474 //LENGTH 130.245 LUMPCC 0.002461405 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 50.140 129.270 +*I mux_right_track_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 48.300 99.620 +*I BUFT_P_136:A I *L 0.001776 *C 47.380 14.960 +*I mux_bottom_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 40.845 36.380 +*N chany_top_in[10]:4 *C 40.883 36.380 +*N chany_top_in[10]:5 *C 43.240 36.380 +*N chany_top_in[10]:6 *C 47.343 14.960 +*N chany_top_in[10]:7 *C 43.285 14.960 +*N chany_top_in[10]:8 *C 43.240 15.005 +*N chany_top_in[10]:9 *C 43.240 35.995 +*N chany_top_in[10]:10 *C 43.240 36.040 +*N chany_top_in[10]:11 *C 47.795 36.040 +*N chany_top_in[10]:12 *C 47.840 36.085 +*N chany_top_in[10]:13 *C 47.840 85.880 +*N chany_top_in[10]:14 *C 47.840 99.575 +*N chany_top_in[10]:15 *C 47.885 99.620 +*N chany_top_in[10]:16 *C 48.300 99.620 +*N chany_top_in[10]:17 *C 50.095 99.620 +*N chany_top_in[10]:18 *C 50.140 99.665 + +*CAP +0 chany_top_in[10] 0.001162778 +1 mux_right_track_12\/mux_l1_in_0_:A1 1e-06 +2 BUFT_P_136:A 1e-06 +3 mux_bottom_track_33\/mux_l1_in_0_:A1 1e-06 +4 chany_top_in[10]:4 0.0002099968 +5 chany_top_in[10]:5 0.0002366071 +6 chany_top_in[10]:6 0.0002459915 +7 chany_top_in[10]:7 0.0002459915 +8 chany_top_in[10]:8 0.001090702 +9 chany_top_in[10]:9 0.001090702 +10 chany_top_in[10]:10 0.0003372764 +11 chany_top_in[10]:11 0.0003106661 +12 chany_top_in[10]:12 0.002409012 +13 chany_top_in[10]:13 0.002852448 +14 chany_top_in[10]:14 0.0004434365 +15 chany_top_in[10]:15 3.93466e-05 +16 chany_top_in[10]:16 0.000156027 +17 chany_top_in[10]:17 8.923489e-05 +18 chany_top_in[10]:18 0.001162778 +19 chany_top_in[10] chany_bottom_in[17]:5 0.0006506158 +20 chany_top_in[10]:12 chany_bottom_in[17]:12 7.258859e-05 +21 chany_top_in[10]:12 chany_bottom_in[17]:13 5.54718e-05 +22 chany_top_in[10]:14 chany_bottom_in[17]:9 0.0001689931 +23 chany_top_in[10]:18 chany_bottom_in[17]:6 0.0006506158 +24 chany_top_in[10]:13 chany_bottom_in[17]:9 7.258859e-05 +25 chany_top_in[10]:13 chany_bottom_in[17]:12 0.0002244649 +26 chany_top_in[10]:14 mux_tree_tapbuf_size4_4_sram[0]:5 8.115399e-05 +27 chany_top_in[10]:14 mux_tree_tapbuf_size4_4_sram[0]:8 6.771498e-05 +28 chany_top_in[10]:16 mux_tree_tapbuf_size4_4_sram[0]:4 3.598676e-05 +29 chany_top_in[10]:17 mux_tree_tapbuf_size4_4_sram[0]:3 3.598676e-05 +30 chany_top_in[10]:13 mux_tree_tapbuf_size4_4_sram[0]:9 6.771498e-05 +31 chany_top_in[10]:13 mux_tree_tapbuf_size4_4_sram[0]:8 8.115399e-05 +32 chany_top_in[10] mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 3.949695e-05 +33 chany_top_in[10]:18 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 3.949695e-05 +34 chany_top_in[10]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.868035e-05 +35 chany_top_in[10]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.868035e-05 + +*RES +0 chany_top_in[10] chany_top_in[10]:18 0.02643304 +1 chany_top_in[10]:6 BUFT_P_136:A 0.152 +2 chany_top_in[10]:7 chany_top_in[10]:6 0.003622768 +3 chany_top_in[10]:8 chany_top_in[10]:7 0.0045 +4 chany_top_in[10]:10 chany_top_in[10]:9 0.0045 +5 chany_top_in[10]:10 chany_top_in[10]:5 0.0003035715 +6 chany_top_in[10]:9 chany_top_in[10]:8 0.01874107 +7 chany_top_in[10]:11 chany_top_in[10]:10 0.004066965 +8 chany_top_in[10]:12 chany_top_in[10]:11 0.0045 +9 chany_top_in[10]:15 chany_top_in[10]:14 0.0045 +10 chany_top_in[10]:14 chany_top_in[10]:13 0.01222768 +11 chany_top_in[10]:4 mux_bottom_track_33\/mux_l1_in_0_:A1 0.152 +12 chany_top_in[10]:16 mux_right_track_12\/mux_l1_in_0_:A1 0.152 +13 chany_top_in[10]:16 chany_top_in[10]:15 0.0003705357 +14 chany_top_in[10]:17 chany_top_in[10]:16 0.001602678 +15 chany_top_in[10]:18 chany_top_in[10]:17 0.0045 +16 chany_top_in[10]:5 chany_top_in[10]:4 0.002104911 +17 chany_top_in[10]:13 chany_top_in[10]:12 0.04445983 + +*END + +*D_NET right_top_grid_pin_49_[0] 0.01379383 //LENGTH 102.540 LUMPCC 0.003355003 DR + +*CONN +*P right_top_grid_pin_49_[0] I *L 0.29796 *C 108.100 102.035 +*I mux_right_track_22\/mux_l1_in_0_:A0 I *L 0.001631 *C 64.230 80.580 +*I mux_right_track_6\/mux_l1_in_2_:A0 I *L 0.001631 *C 67.910 113.220 +*I mux_right_track_2\/mux_l1_in_2_:A0 I *L 0.001631 *C 79.295 102.680 +*N right_top_grid_pin_49_[0]:4 *C 79.333 102.680 +*N right_top_grid_pin_49_[0]:5 *C 67.883 113.243 +*N right_top_grid_pin_49_[0]:6 *C 67.620 113.255 +*N right_top_grid_pin_49_[0]:7 *C 67.620 113.560 +*N right_top_grid_pin_49_[0]:8 *C 82.755 113.560 +*N right_top_grid_pin_49_[0]:9 *C 82.800 113.515 +*N right_top_grid_pin_49_[0]:10 *C 64.267 80.580 +*N right_top_grid_pin_49_[0]:11 *C 64.860 80.580 +*N right_top_grid_pin_49_[0]:12 *C 64.860 80.240 +*N right_top_grid_pin_49_[0]:13 *C 69.875 80.240 +*N right_top_grid_pin_49_[0]:14 *C 69.920 80.285 +*N right_top_grid_pin_49_[0]:15 *C 69.920 91.743 +*N right_top_grid_pin_49_[0]:16 *C 69.928 91.800 +*N right_top_grid_pin_49_[0]:17 *C 73.580 91.800 +*N right_top_grid_pin_49_[0]:18 *C 73.600 91.808 +*N right_top_grid_pin_49_[0]:19 *C 73.600 103.353 +*N right_top_grid_pin_49_[0]:20 *C 73.620 103.360 +*N right_top_grid_pin_49_[0]:21 *C 82.793 103.360 +*N right_top_grid_pin_49_[0]:22 *C 82.800 103.360 +*N right_top_grid_pin_49_[0]:23 *C 82.800 102.725 +*N right_top_grid_pin_49_[0]:24 *C 82.800 102.680 +*N right_top_grid_pin_49_[0]:25 *C 100.740 102.680 +*N right_top_grid_pin_49_[0]:26 *C 100.740 101.660 +*N right_top_grid_pin_49_[0]:27 *C 108.055 101.660 +*N right_top_grid_pin_49_[0]:28 *C 108.100 101.705 + +*CAP +0 right_top_grid_pin_49_[0] 3.209703e-05 +1 mux_right_track_22\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_6\/mux_l1_in_2_:A0 1e-06 +3 mux_right_track_2\/mux_l1_in_2_:A0 1e-06 +4 right_top_grid_pin_49_[0]:4 0.0001816324 +5 right_top_grid_pin_49_[0]:5 1.171935e-05 +6 right_top_grid_pin_49_[0]:6 3.686718e-05 +7 right_top_grid_pin_49_[0]:7 0.001040631 +8 right_top_grid_pin_49_[0]:8 0.001015484 +9 right_top_grid_pin_49_[0]:9 0.0002028377 +10 right_top_grid_pin_49_[0]:10 5.600828e-05 +11 right_top_grid_pin_49_[0]:11 8.003564e-05 +12 right_top_grid_pin_49_[0]:12 0.0003399551 +13 right_top_grid_pin_49_[0]:13 0.0003159278 +14 right_top_grid_pin_49_[0]:14 0.0006174893 +15 right_top_grid_pin_49_[0]:15 0.0006174893 +16 right_top_grid_pin_49_[0]:16 0.0002941277 +17 right_top_grid_pin_49_[0]:17 0.0002941277 +18 right_top_grid_pin_49_[0]:18 0.0005012422 +19 right_top_grid_pin_49_[0]:19 0.0005012422 +20 right_top_grid_pin_49_[0]:20 0.00069586 +21 right_top_grid_pin_49_[0]:21 0.00069586 +22 right_top_grid_pin_49_[0]:22 0.0002706729 +23 right_top_grid_pin_49_[0]:23 3.279765e-05 +24 right_top_grid_pin_49_[0]:24 0.001092506 +25 right_top_grid_pin_49_[0]:25 0.0009312968 +26 right_top_grid_pin_49_[0]:26 0.000299811 +27 right_top_grid_pin_49_[0]:27 0.0002460084 +28 right_top_grid_pin_49_[0]:28 3.209703e-05 +29 right_top_grid_pin_49_[0]:18 chany_top_in[14]:22 0.000530145 +30 right_top_grid_pin_49_[0]:19 chany_top_in[14]:23 0.000530145 +31 right_top_grid_pin_49_[0] right_top_grid_pin_42_[0] 1.111813e-06 +32 right_top_grid_pin_49_[0]:27 right_top_grid_pin_42_[0]:26 0.0002802349 +33 right_top_grid_pin_49_[0]:28 right_top_grid_pin_42_[0]:27 1.111813e-06 +34 right_top_grid_pin_49_[0]:20 right_top_grid_pin_42_[0]:22 1.307297e-05 +35 right_top_grid_pin_49_[0]:21 right_top_grid_pin_42_[0]:23 1.307297e-05 +36 right_top_grid_pin_49_[0]:24 right_top_grid_pin_42_[0]:25 6.216184e-06 +37 right_top_grid_pin_49_[0]:25 right_top_grid_pin_42_[0]:26 6.216184e-06 +38 right_top_grid_pin_49_[0]:26 right_top_grid_pin_42_[0]:25 0.0002802349 +39 right_top_grid_pin_49_[0]:22 right_top_grid_pin_46_[0]:15 0.0002841479 +40 right_top_grid_pin_49_[0]:22 right_top_grid_pin_46_[0]:16 2.179418e-05 +41 right_top_grid_pin_49_[0]:23 right_top_grid_pin_46_[0]:15 2.179418e-05 +42 right_top_grid_pin_49_[0]:9 right_top_grid_pin_46_[0]:16 0.0002841479 +43 right_top_grid_pin_49_[0]:22 right_top_grid_pin_47_[0]:13 0.0002344529 +44 right_top_grid_pin_49_[0]:5 right_top_grid_pin_47_[0]:17 7.996938e-06 +45 right_top_grid_pin_49_[0]:8 right_top_grid_pin_47_[0]:17 1.412156e-05 +46 right_top_grid_pin_49_[0]:9 right_top_grid_pin_47_[0]:14 0.0002344529 +47 right_top_grid_pin_49_[0]:6 right_top_grid_pin_47_[0]:16 7.996938e-06 +48 right_top_grid_pin_49_[0]:7 right_top_grid_pin_47_[0]:16 1.412156e-05 +49 right_top_grid_pin_49_[0]:24 mux_tree_tapbuf_size7_0_sram[0]:23 2.118669e-05 +50 right_top_grid_pin_49_[0]:24 mux_tree_tapbuf_size7_0_sram[0]:22 0.0002115795 +51 right_top_grid_pin_49_[0]:24 mux_tree_tapbuf_size7_0_sram[0]:21 5.144102e-05 +52 right_top_grid_pin_49_[0]:4 mux_tree_tapbuf_size7_0_sram[0]:20 5.144102e-05 +53 right_top_grid_pin_49_[0]:4 mux_tree_tapbuf_size7_0_sram[0]:22 2.118669e-05 +54 right_top_grid_pin_49_[0]:25 mux_tree_tapbuf_size7_0_sram[0]:23 0.0002115795 + +*RES +0 right_top_grid_pin_49_[0] right_top_grid_pin_49_[0]:28 0.0002946429 +1 right_top_grid_pin_49_[0]:27 right_top_grid_pin_49_[0]:26 0.00653125 +2 right_top_grid_pin_49_[0]:28 right_top_grid_pin_49_[0]:27 0.0045 +3 right_top_grid_pin_49_[0]:10 mux_right_track_22\/mux_l1_in_0_:A0 0.152 +4 right_top_grid_pin_49_[0]:13 right_top_grid_pin_49_[0]:12 0.004477679 +5 right_top_grid_pin_49_[0]:14 right_top_grid_pin_49_[0]:13 0.0045 +6 right_top_grid_pin_49_[0]:15 right_top_grid_pin_49_[0]:14 0.01022991 +7 right_top_grid_pin_49_[0]:16 right_top_grid_pin_49_[0]:15 0.00341 +8 right_top_grid_pin_49_[0]:17 right_top_grid_pin_49_[0]:16 0.000572225 +9 right_top_grid_pin_49_[0]:18 right_top_grid_pin_49_[0]:17 0.00341 +10 right_top_grid_pin_49_[0]:20 right_top_grid_pin_49_[0]:19 0.00341 +11 right_top_grid_pin_49_[0]:19 right_top_grid_pin_49_[0]:18 0.001808717 +12 right_top_grid_pin_49_[0]:22 right_top_grid_pin_49_[0]:21 0.00341 +13 right_top_grid_pin_49_[0]:22 right_top_grid_pin_49_[0]:9 0.009066964 +14 right_top_grid_pin_49_[0]:21 right_top_grid_pin_49_[0]:20 0.001437025 +15 right_top_grid_pin_49_[0]:24 right_top_grid_pin_49_[0]:23 0.0045 +16 right_top_grid_pin_49_[0]:24 right_top_grid_pin_49_[0]:4 0.003095982 +17 right_top_grid_pin_49_[0]:23 right_top_grid_pin_49_[0]:22 0.0005669643 +18 right_top_grid_pin_49_[0]:4 mux_right_track_2\/mux_l1_in_2_:A0 0.152 +19 right_top_grid_pin_49_[0]:5 mux_right_track_6\/mux_l1_in_2_:A0 0.152 +20 right_top_grid_pin_49_[0]:8 right_top_grid_pin_49_[0]:7 0.01351339 +21 right_top_grid_pin_49_[0]:9 right_top_grid_pin_49_[0]:8 0.0045 +22 right_top_grid_pin_49_[0]:11 right_top_grid_pin_49_[0]:10 0.0005290179 +23 right_top_grid_pin_49_[0]:12 right_top_grid_pin_49_[0]:11 0.0003035715 +24 right_top_grid_pin_49_[0]:6 right_top_grid_pin_49_[0]:5 0.0001773649 +25 right_top_grid_pin_49_[0]:7 right_top_grid_pin_49_[0]:6 0.0002723215 +26 right_top_grid_pin_49_[0]:25 right_top_grid_pin_49_[0]:24 0.01601786 +27 right_top_grid_pin_49_[0]:26 right_top_grid_pin_49_[0]:25 0.0009107144 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[0] 0.002090091 //LENGTH 15.680 LUMPCC 0.000328424 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.465 39.100 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 37.435 33.660 +*I mux_bottom_track_33\/mux_l1_in_1_:S I *L 0.00357 *C 36.240 36.720 +*I mux_bottom_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 40.120 36.430 +*N mux_tree_tapbuf_size3_4_sram[0]:4 *C 40.120 36.430 +*N mux_tree_tapbuf_size3_4_sram[0]:5 *C 36.278 36.720 +*N mux_tree_tapbuf_size3_4_sram[0]:6 *C 37.435 33.660 +*N mux_tree_tapbuf_size3_4_sram[0]:7 *C 37.720 33.660 +*N mux_tree_tapbuf_size3_4_sram[0]:8 *C 37.720 33.705 +*N mux_tree_tapbuf_size3_4_sram[0]:9 *C 37.720 36.675 +*N mux_tree_tapbuf_size3_4_sram[0]:10 *C 37.720 36.720 +*N mux_tree_tapbuf_size3_4_sram[0]:11 *C 40.120 36.720 +*N mux_tree_tapbuf_size3_4_sram[0]:12 *C 43.655 36.720 +*N mux_tree_tapbuf_size3_4_sram[0]:13 *C 43.700 36.765 +*N mux_tree_tapbuf_size3_4_sram[0]:14 *C 43.700 39.055 +*N mux_tree_tapbuf_size3_4_sram[0]:15 *C 43.745 39.100 +*N mux_tree_tapbuf_size3_4_sram[0]:16 *C 44.428 39.100 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_33\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_track_33\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_4_sram[0]:4 5.655575e-05 +5 mux_tree_tapbuf_size3_4_sram[0]:5 9.577967e-05 +6 mux_tree_tapbuf_size3_4_sram[0]:6 5.459295e-05 +7 mux_tree_tapbuf_size3_4_sram[0]:7 5.679032e-05 +8 mux_tree_tapbuf_size3_4_sram[0]:8 8.597856e-05 +9 mux_tree_tapbuf_size3_4_sram[0]:9 8.597856e-05 +10 mux_tree_tapbuf_size3_4_sram[0]:10 0.0002569382 +11 mux_tree_tapbuf_size3_4_sram[0]:11 0.0004108059 +12 mux_tree_tapbuf_size3_4_sram[0]:12 0.0002520027 +13 mux_tree_tapbuf_size3_4_sram[0]:13 0.000139641 +14 mux_tree_tapbuf_size3_4_sram[0]:14 0.000139641 +15 mux_tree_tapbuf_size3_4_sram[0]:15 6.148153e-05 +16 mux_tree_tapbuf_size3_4_sram[0]:16 6.148153e-05 +17 mux_tree_tapbuf_size3_4_sram[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.767771e-05 +18 mux_tree_tapbuf_size3_4_sram[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.113769e-05 +19 mux_tree_tapbuf_size3_4_sram[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.113769e-05 +20 mux_tree_tapbuf_size3_4_sram[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.767771e-05 +21 mux_tree_tapbuf_size3_4_sram[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.258919e-06 +22 mux_tree_tapbuf_size3_4_sram[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.113769e-05 +23 mux_tree_tapbuf_size3_4_sram[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.113769e-05 +24 mux_tree_tapbuf_size3_4_sram[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.258919e-06 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_4_sram[0]:16 0.152 +1 mux_tree_tapbuf_size3_4_sram[0]:10 mux_tree_tapbuf_size3_4_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size3_4_sram[0]:10 mux_tree_tapbuf_size3_4_sram[0]:5 0.001287946 +3 mux_tree_tapbuf_size3_4_sram[0]:9 mux_tree_tapbuf_size3_4_sram[0]:8 0.002651786 +4 mux_tree_tapbuf_size3_4_sram[0]:7 mux_tree_tapbuf_size3_4_sram[0]:6 0.0001548913 +5 mux_tree_tapbuf_size3_4_sram[0]:8 mux_tree_tapbuf_size3_4_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size3_4_sram[0]:6 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size3_4_sram[0]:12 mux_tree_tapbuf_size3_4_sram[0]:11 0.00315625 +8 mux_tree_tapbuf_size3_4_sram[0]:13 mux_tree_tapbuf_size3_4_sram[0]:12 0.0045 +9 mux_tree_tapbuf_size3_4_sram[0]:15 mux_tree_tapbuf_size3_4_sram[0]:14 0.0045 +10 mux_tree_tapbuf_size3_4_sram[0]:14 mux_tree_tapbuf_size3_4_sram[0]:13 0.002044643 +11 mux_tree_tapbuf_size3_4_sram[0]:16 mux_tree_tapbuf_size3_4_sram[0]:15 0.000609375 +12 mux_tree_tapbuf_size3_4_sram[0]:5 mux_bottom_track_33\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_4_sram[0]:4 mux_bottom_track_33\/mux_l1_in_0_:S 0.152 +14 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:10 0.002142857 +15 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:4 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size4_4_sram[1] 0.001953409 //LENGTH 15.520 LUMPCC 0 DR + +*CONN +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.585 93.840 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 58.595 91.460 +*I mux_right_track_12\/mux_l2_in_1_:S I *L 0.00357 *C 57.400 89.080 +*I mux_right_track_12\/mux_l2_in_0_:S I *L 0.00357 *C 63.120 93.840 +*N mux_tree_tapbuf_size4_4_sram[1]:4 *C 63.083 93.840 +*N mux_tree_tapbuf_size4_4_sram[1]:5 *C 57.438 89.080 +*N mux_tree_tapbuf_size4_4_sram[1]:6 *C 58.375 89.080 +*N mux_tree_tapbuf_size4_4_sram[1]:7 *C 58.420 89.125 +*N mux_tree_tapbuf_size4_4_sram[1]:8 *C 58.595 91.460 +*N mux_tree_tapbuf_size4_4_sram[1]:9 *C 58.420 91.460 +*N mux_tree_tapbuf_size4_4_sram[1]:10 *C 58.420 91.460 +*N mux_tree_tapbuf_size4_4_sram[1]:11 *C 58.420 93.795 +*N mux_tree_tapbuf_size4_4_sram[1]:12 *C 58.420 93.840 +*N mux_tree_tapbuf_size4_4_sram[1]:13 *C 54.623 93.840 + +*CAP +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_12\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_12\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_4_sram[1]:4 0.0002971796 +5 mux_tree_tapbuf_size4_4_sram[1]:5 9.998379e-05 +6 mux_tree_tapbuf_size4_4_sram[1]:6 9.998379e-05 +7 mux_tree_tapbuf_size4_4_sram[1]:7 0.0001295215 +8 mux_tree_tapbuf_size4_4_sram[1]:8 4.924959e-05 +9 mux_tree_tapbuf_size4_4_sram[1]:9 5.160905e-05 +10 mux_tree_tapbuf_size4_4_sram[1]:10 0.0002937704 +11 mux_tree_tapbuf_size4_4_sram[1]:11 0.0001321595 +12 mux_tree_tapbuf_size4_4_sram[1]:12 0.0005626029 +13 mux_tree_tapbuf_size4_4_sram[1]:13 0.0002333486 + +*RES +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_4_sram[1]:13 0.152 +1 mux_tree_tapbuf_size4_4_sram[1]:12 mux_tree_tapbuf_size4_4_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size4_4_sram[1]:12 mux_tree_tapbuf_size4_4_sram[1]:4 0.004162947 +3 mux_tree_tapbuf_size4_4_sram[1]:11 mux_tree_tapbuf_size4_4_sram[1]:10 0.002084821 +4 mux_tree_tapbuf_size4_4_sram[1]:6 mux_tree_tapbuf_size4_4_sram[1]:5 0.0008370536 +5 mux_tree_tapbuf_size4_4_sram[1]:7 mux_tree_tapbuf_size4_4_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size4_4_sram[1]:5 mux_right_track_12\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size4_4_sram[1]:4 mux_right_track_12\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_4_sram[1]:9 mux_tree_tapbuf_size4_4_sram[1]:8 9.51087e-05 +9 mux_tree_tapbuf_size4_4_sram[1]:10 mux_tree_tapbuf_size4_4_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size4_4_sram[1]:10 mux_tree_tapbuf_size4_4_sram[1]:7 0.002084821 +11 mux_tree_tapbuf_size4_4_sram[1]:8 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size4_4_sram[1]:13 mux_tree_tapbuf_size4_4_sram[1]:12 0.003390625 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[2] 0.001264683 //LENGTH 10.325 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 92.305 55.420 +*I mem_top_track_2\/FTB_8__38:A I *L 0.001746 *C 91.080 53.040 +*I mux_top_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 90.720 58.480 +*N mux_tree_tapbuf_size5_0_sram[2]:3 *C 90.720 58.480 +*N mux_tree_tapbuf_size5_0_sram[2]:4 *C 90.620 58.140 +*N mux_tree_tapbuf_size5_0_sram[2]:5 *C 89.745 58.140 +*N mux_tree_tapbuf_size5_0_sram[2]:6 *C 89.700 58.095 +*N mux_tree_tapbuf_size5_0_sram[2]:7 *C 89.700 55.465 +*N mux_tree_tapbuf_size5_0_sram[2]:8 *C 89.745 55.420 +*N mux_tree_tapbuf_size5_0_sram[2]:9 *C 91.080 53.040 +*N mux_tree_tapbuf_size5_0_sram[2]:10 *C 91.080 53.085 +*N mux_tree_tapbuf_size5_0_sram[2]:11 *C 91.080 55.375 +*N mux_tree_tapbuf_size5_0_sram[2]:12 *C 91.080 55.420 +*N mux_tree_tapbuf_size5_0_sram[2]:13 *C 92.267 55.420 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_2\/FTB_8__38:A 1e-06 +2 mux_top_track_2\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_0_sram[2]:3 5.908399e-05 +4 mux_tree_tapbuf_size5_0_sram[2]:4 9.441434e-05 +5 mux_tree_tapbuf_size5_0_sram[2]:5 6.590429e-05 +6 mux_tree_tapbuf_size5_0_sram[2]:6 0.0001589551 +7 mux_tree_tapbuf_size5_0_sram[2]:7 0.0001589551 +8 mux_tree_tapbuf_size5_0_sram[2]:8 0.0001037511 +9 mux_tree_tapbuf_size5_0_sram[2]:9 2.851145e-05 +10 mux_tree_tapbuf_size5_0_sram[2]:10 0.0001353303 +11 mux_tree_tapbuf_size5_0_sram[2]:11 0.0001353303 +12 mux_tree_tapbuf_size5_0_sram[2]:12 0.0002287385 +13 mux_tree_tapbuf_size5_0_sram[2]:13 9.270885e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:6 0.002348214 +3 mux_tree_tapbuf_size5_0_sram[2]:5 mux_tree_tapbuf_size5_0_sram[2]:4 0.00078125 +4 mux_tree_tapbuf_size5_0_sram[2]:6 mux_tree_tapbuf_size5_0_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size5_0_sram[2]:3 mux_top_track_2\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size5_0_sram[2]:13 mux_tree_tapbuf_size5_0_sram[2]:12 0.001060268 +7 mux_tree_tapbuf_size5_0_sram[2]:12 mux_tree_tapbuf_size5_0_sram[2]:11 0.0045 +8 mux_tree_tapbuf_size5_0_sram[2]:12 mux_tree_tapbuf_size5_0_sram[2]:8 0.001191964 +9 mux_tree_tapbuf_size5_0_sram[2]:11 mux_tree_tapbuf_size5_0_sram[2]:10 0.002044643 +10 mux_tree_tapbuf_size5_0_sram[2]:9 mem_top_track_2\/FTB_8__38:A 0.152 +11 mux_tree_tapbuf_size5_0_sram[2]:10 mux_tree_tapbuf_size5_0_sram[2]:9 0.0045 +12 mux_tree_tapbuf_size5_0_sram[2]:4 mux_tree_tapbuf_size5_0_sram[2]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_2_ccff_tail[0] 0.0006547896 //LENGTH 5.250 LUMPCC 8.807583e-05 DR + +*CONN +*I mem_bottom_track_3\/FTB_10__40:X O *L 0 *C 66.935 23.460 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.495 26.180 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 *C 65.495 26.180 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 *C 65.320 26.180 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 *C 65.320 26.135 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 *C 65.320 23.505 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 *C 65.365 23.460 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 *C 66.898 23.460 + +*CAP +0 mem_bottom_track_3\/FTB_10__40:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 5.136171e-05 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 5.593467e-05 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.0001129647 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0001129647 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.000115744 +7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.000115744 +8 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size5_2_sram[0]:14 4.403792e-05 +9 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size5_2_sram[0]:15 4.403792e-05 + +*RES +0 mem_bottom_track_3\/FTB_10__40:X mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 9.510869e-05 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.001368304 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[1] 0.005143163 //LENGTH 40.825 LUMPCC 0.0008362354 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 53.665 42.500 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 45.440 45.560 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 46.635 22.780 +*I mux_bottom_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 47.480 34.295 +*N mux_tree_tapbuf_size6_4_sram[1]:4 *C 47.480 34.295 +*N mux_tree_tapbuf_size6_4_sram[1]:5 *C 46.635 22.780 +*N mux_tree_tapbuf_size6_4_sram[1]:6 *C 46.920 22.780 +*N mux_tree_tapbuf_size6_4_sram[1]:7 *C 46.920 22.825 +*N mux_tree_tapbuf_size6_4_sram[1]:8 *C 46.920 34.635 +*N mux_tree_tapbuf_size6_4_sram[1]:9 *C 46.965 34.680 +*N mux_tree_tapbuf_size6_4_sram[1]:10 *C 47.480 34.680 +*N mux_tree_tapbuf_size6_4_sram[1]:11 *C 53.775 34.680 +*N mux_tree_tapbuf_size6_4_sram[1]:12 *C 53.820 34.725 +*N mux_tree_tapbuf_size6_4_sram[1]:13 *C 53.820 42.455 +*N mux_tree_tapbuf_size6_4_sram[1]:14 *C 53.698 42.500 +*N mux_tree_tapbuf_size6_4_sram[1]:15 *C 45.477 45.560 +*N mux_tree_tapbuf_size6_4_sram[1]:16 *C 51.935 45.560 +*N mux_tree_tapbuf_size6_4_sram[1]:17 *C 51.980 45.515 +*N mux_tree_tapbuf_size6_4_sram[1]:18 *C 51.980 42.545 +*N mux_tree_tapbuf_size6_4_sram[1]:19 *C 52.025 42.500 +*N mux_tree_tapbuf_size6_4_sram[1]:20 *C 53.628 42.500 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_1\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_4_sram[1]:4 6.266103e-05 +5 mux_tree_tapbuf_size6_4_sram[1]:5 5.263514e-05 +6 mux_tree_tapbuf_size6_4_sram[1]:6 5.535935e-05 +7 mux_tree_tapbuf_size6_4_sram[1]:7 0.0004562812 +8 mux_tree_tapbuf_size6_4_sram[1]:8 0.0004562812 +9 mux_tree_tapbuf_size6_4_sram[1]:9 4.82653e-05 +10 mux_tree_tapbuf_size6_4_sram[1]:10 0.0005003168 +11 mux_tree_tapbuf_size6_4_sram[1]:11 0.000420129 +12 mux_tree_tapbuf_size6_4_sram[1]:12 0.0004366444 +13 mux_tree_tapbuf_size6_4_sram[1]:13 0.0004366444 +14 mux_tree_tapbuf_size6_4_sram[1]:14 2.190515e-05 +15 mux_tree_tapbuf_size6_4_sram[1]:15 0.000369719 +16 mux_tree_tapbuf_size6_4_sram[1]:16 0.000369719 +17 mux_tree_tapbuf_size6_4_sram[1]:17 0.0001909111 +18 mux_tree_tapbuf_size6_4_sram[1]:18 0.0001909111 +19 mux_tree_tapbuf_size6_4_sram[1]:19 0.0001063196 +20 mux_tree_tapbuf_size6_4_sram[1]:20 0.0001282247 +21 mux_tree_tapbuf_size6_4_sram[1]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001510483 +22 mux_tree_tapbuf_size6_4_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001510483 +23 mux_tree_tapbuf_size6_4_sram[1]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001127197 +24 mux_tree_tapbuf_size6_4_sram[1]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001127197 +25 mux_tree_tapbuf_size6_4_sram[1]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001541954 +26 mux_tree_tapbuf_size6_4_sram[1]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 1.543662e-07 +27 mux_tree_tapbuf_size6_4_sram[1]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001541954 +28 mux_tree_tapbuf_size6_4_sram[1]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 1.543662e-07 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_4_sram[1]:20 0.152 +1 mux_tree_tapbuf_size6_4_sram[1]:11 mux_tree_tapbuf_size6_4_sram[1]:10 0.005620536 +2 mux_tree_tapbuf_size6_4_sram[1]:12 mux_tree_tapbuf_size6_4_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size6_4_sram[1]:14 mux_tree_tapbuf_size6_4_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size6_4_sram[1]:13 mux_tree_tapbuf_size6_4_sram[1]:12 0.006901786 +5 mux_tree_tapbuf_size6_4_sram[1]:19 mux_tree_tapbuf_size6_4_sram[1]:18 0.0045 +6 mux_tree_tapbuf_size6_4_sram[1]:18 mux_tree_tapbuf_size6_4_sram[1]:17 0.002651786 +7 mux_tree_tapbuf_size6_4_sram[1]:16 mux_tree_tapbuf_size6_4_sram[1]:15 0.005765625 +8 mux_tree_tapbuf_size6_4_sram[1]:17 mux_tree_tapbuf_size6_4_sram[1]:16 0.0045 +9 mux_tree_tapbuf_size6_4_sram[1]:15 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size6_4_sram[1]:4 mux_bottom_track_1\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size6_4_sram[1]:20 mux_tree_tapbuf_size6_4_sram[1]:19 0.001430804 +12 mux_tree_tapbuf_size6_4_sram[1]:20 mux_tree_tapbuf_size6_4_sram[1]:14 6.25e-05 +13 mux_tree_tapbuf_size6_4_sram[1]:5 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size6_4_sram[1]:6 mux_tree_tapbuf_size6_4_sram[1]:5 0.0001548913 +15 mux_tree_tapbuf_size6_4_sram[1]:7 mux_tree_tapbuf_size6_4_sram[1]:6 0.0045 +16 mux_tree_tapbuf_size6_4_sram[1]:9 mux_tree_tapbuf_size6_4_sram[1]:8 0.0045 +17 mux_tree_tapbuf_size6_4_sram[1]:8 mux_tree_tapbuf_size6_4_sram[1]:7 0.01054464 +18 mux_tree_tapbuf_size6_4_sram[1]:10 mux_tree_tapbuf_size6_4_sram[1]:9 0.0004598215 +19 mux_tree_tapbuf_size6_4_sram[1]:10 mux_tree_tapbuf_size6_4_sram[1]:4 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[1] 0.002889927 //LENGTH 22.975 LUMPCC 0.0001374071 DR + +*CONN +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.125 118.660 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 49.855 115.260 +*I mux_right_track_6\/mux_l2_in_0_:S I *L 0.00357 *C 63.120 121.040 +*I mux_right_track_6\/mux_l2_in_1_:S I *L 0.00357 *C 62.200 118.030 +*N mux_tree_tapbuf_size7_2_sram[1]:4 *C 62.200 118.030 +*N mux_tree_tapbuf_size7_2_sram[1]:5 *C 62.143 118.320 +*N mux_tree_tapbuf_size7_2_sram[1]:6 *C 63.083 121.040 +*N mux_tree_tapbuf_size7_2_sram[1]:7 *C 61.685 121.040 +*N mux_tree_tapbuf_size7_2_sram[1]:8 *C 61.640 120.995 +*N mux_tree_tapbuf_size7_2_sram[1]:9 *C 61.640 118.365 +*N mux_tree_tapbuf_size7_2_sram[1]:10 *C 61.640 118.320 +*N mux_tree_tapbuf_size7_2_sram[1]:11 *C 53.820 118.320 +*N mux_tree_tapbuf_size7_2_sram[1]:12 *C 49.893 115.260 +*N mux_tree_tapbuf_size7_2_sram[1]:13 *C 51.015 115.260 +*N mux_tree_tapbuf_size7_2_sram[1]:14 *C 51.060 115.305 +*N mux_tree_tapbuf_size7_2_sram[1]:15 *C 51.060 118.615 +*N mux_tree_tapbuf_size7_2_sram[1]:16 *C 51.105 118.660 +*N mux_tree_tapbuf_size7_2_sram[1]:17 *C 53.820 118.648 +*N mux_tree_tapbuf_size7_2_sram[1]:18 *C 54.098 118.615 + +*CAP +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_6\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_6\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_2_sram[1]:4 6.177636e-05 +5 mux_tree_tapbuf_size7_2_sram[1]:5 7.366455e-05 +6 mux_tree_tapbuf_size7_2_sram[1]:6 9.828973e-05 +7 mux_tree_tapbuf_size7_2_sram[1]:7 9.828973e-05 +8 mux_tree_tapbuf_size7_2_sram[1]:8 0.0001656433 +9 mux_tree_tapbuf_size7_2_sram[1]:9 0.0001656433 +10 mux_tree_tapbuf_size7_2_sram[1]:10 0.0005304109 +11 mux_tree_tapbuf_size7_2_sram[1]:11 0.000483569 +12 mux_tree_tapbuf_size7_2_sram[1]:12 9.430188e-05 +13 mux_tree_tapbuf_size7_2_sram[1]:13 9.430188e-05 +14 mux_tree_tapbuf_size7_2_sram[1]:14 0.0002097688 +15 mux_tree_tapbuf_size7_2_sram[1]:15 0.0002097688 +16 mux_tree_tapbuf_size7_2_sram[1]:16 0.0001857598 +17 mux_tree_tapbuf_size7_2_sram[1]:17 0.0002436381 +18 mux_tree_tapbuf_size7_2_sram[1]:18 3.369369e-05 +19 mux_tree_tapbuf_size7_2_sram[1]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.472881e-05 +20 mux_tree_tapbuf_size7_2_sram[1]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.472881e-05 +21 mux_tree_tapbuf_size7_2_sram[1]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.397472e-05 +22 mux_tree_tapbuf_size7_2_sram[1]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.397472e-05 + +*RES +0 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_2_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_2_sram[1]:6 mux_right_track_6\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[1]:7 mux_tree_tapbuf_size7_2_sram[1]:6 0.001247768 +3 mux_tree_tapbuf_size7_2_sram[1]:8 mux_tree_tapbuf_size7_2_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:5 0.0004486607 +6 mux_tree_tapbuf_size7_2_sram[1]:9 mux_tree_tapbuf_size7_2_sram[1]:8 0.002348214 +7 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:15 0.0045 +8 mux_tree_tapbuf_size7_2_sram[1]:15 mux_tree_tapbuf_size7_2_sram[1]:14 0.002955357 +9 mux_tree_tapbuf_size7_2_sram[1]:13 mux_tree_tapbuf_size7_2_sram[1]:12 0.001002232 +10 mux_tree_tapbuf_size7_2_sram[1]:14 mux_tree_tapbuf_size7_2_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size7_2_sram[1]:12 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size7_2_sram[1]:4 mux_right_track_6\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size7_2_sram[1]:18 mux_tree_tapbuf_size7_2_sram[1]:17 0.0002477679 +14 mux_tree_tapbuf_size7_2_sram[1]:17 mux_tree_tapbuf_size7_2_sram[1]:16 0.002424107 +15 mux_tree_tapbuf_size7_2_sram[1]:17 mux_tree_tapbuf_size7_2_sram[1]:11 0.0002924107 +16 mux_tree_tapbuf_size7_2_sram[1]:11 mux_tree_tapbuf_size7_2_sram[1]:10 0.006982143 +17 mux_tree_tapbuf_size7_2_sram[1]:5 mux_tree_tapbuf_size7_2_sram[1]:4 0.000125 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001107914 //LENGTH 8.810 LUMPCC 0.0001855397 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_1_:X O *L 0 *C 84.925 98.600 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.195 91.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 86.157 91.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 85.145 91.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 85.100 91.845 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.100 98.555 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 85.100 98.600 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 84.925 98.600 + +*CAP +0 mux_right_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.189201e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.189201e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003244492 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003244492 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.432511e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.336706e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 right_top_grid_pin_46_[0]:9 7.915811e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 right_top_grid_pin_46_[0]:11 1.361171e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 right_top_grid_pin_46_[0]:10 7.915811e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 right_top_grid_pin_46_[0]:12 1.361171e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009040179 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005991071 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002658178 //LENGTH 18.795 LUMPCC 0.0002093857 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 74.345 42.840 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 91.080 41.820 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 91.080 41.820 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 91.080 42.160 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 80.545 42.160 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 80.500 42.205 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 80.500 42.795 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 80.455 42.840 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 74.383 42.840 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.789881e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0007167876 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0006883972 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.361894e-05 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.361894e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004382354 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0004382354 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size6_6_sram[0]:20 8.334691e-08 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size6_6_sram[0]:28 2.50395e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_6_sram[0]:21 8.334691e-08 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_6_sram[0]:29 2.50395e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_6_sram[0]:27 1.651136e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_6_sram[0]:28 5.002208e-05 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_6_sram[0]:29 1.303656e-05 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_6_sram[0]:26 1.651136e-05 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_6_sram[0]:19 1.303656e-05 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_6_sram[0]:29 5.002208e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.005421876 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005267857 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.009406251 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00108605 //LENGTH 8.720 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_1_:X O *L 0 *C 62.385 57.800 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 61.930 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 61.930 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 62.100 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.100 50.025 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.100 57.755 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.100 57.800 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.385 57.800 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.194405e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.652868e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004292825 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004292825 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.971841e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.729371e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.23913e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008773592 //LENGTH 7.750 LUMPCC 0 DR + +*CONN +*I mux_right_track_10\/mux_l2_in_0_:X O *L 0 *C 40.655 95.880 +*I mux_right_track_10\/mux_l3_in_0_:A1 I *L 0.00198 *C 40.580 88.740 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 40.480 88.740 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 40.480 88.785 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 40.480 95.835 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 40.480 95.880 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 40.655 95.880 + +*CAP +0 mux_right_track_10\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_10\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.146776e-05 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003661232 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003661232 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.407318e-05 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.75719e-05 + +*RES +0 mux_right_track_10\/mux_l2_in_0_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_10\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.006294644 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008957628 //LENGTH 6.600 LUMPCC 0.0002405412 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_0_:X O *L 0 *C 72.045 125.800 +*I mux_right_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 73.700 121.380 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 73.600 121.380 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.600 121.425 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.600 125.755 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.555 125.800 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 72.083 125.800 + +*CAP +0 mux_right_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.69417e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002296249 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002296249 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.85151e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.85151e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[12]:33 5.035736e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[12]:34 5.035736e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_out[2]:4 6.991321e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_out[2]:3 6.991321e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005461848 //LENGTH 3.370 LUMPCC 0.000123486 DR + +*CONN +*I mux_right_track_18\/mux_l1_in_1_:X O *L 0 *C 79.405 70.040 +*I mux_right_track_18\/mux_l2_in_0_:A0 I *L 0.001631 *C 80.675 71.400 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 80.675 71.400 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 80.500 71.400 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 80.500 71.355 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 80.500 70.085 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 80.455 70.040 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 79.443 70.040 + +*CAP +0 mux_right_track_18\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_18\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.753059e-05 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.188371e-05 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.747155e-05 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.747155e-05 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.817069e-05 +7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.817069e-05 +8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[12]:35 4.249977e-05 +9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[12]:32 1.924324e-05 +10 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[12]:34 4.249977e-05 +11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[12]:33 1.924324e-05 + +*RES +0 mux_right_track_18\/mux_l1_in_1_:X mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_18\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.510871e-05 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001133929 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040179 + +*END + +*D_NET ropt_net_238 0.00136902 //LENGTH 8.080 LUMPCC 0.0005176863 DR + +*CONN +*I ropt_mt_inst_820:X O *L 0 *C 59.945 125.800 +*I ropt_mt_inst_858:A I *L 0.001766 *C 54.280 126.480 +*N ropt_net_238:2 *C 54.280 126.480 +*N ropt_net_238:3 *C 54.280 126.435 +*N ropt_net_238:4 *C 54.280 125.845 +*N ropt_net_238:5 *C 54.280 125.800 +*N ropt_net_238:6 *C 59.908 125.800 + +*CAP +0 ropt_mt_inst_820:X 1e-06 +1 ropt_mt_inst_858:A 1e-06 +2 ropt_net_238:2 3.364305e-05 +3 ropt_net_238:3 6.733504e-05 +4 ropt_net_238:4 6.733504e-05 +5 ropt_net_238:5 0.0003573319 +6 ropt_net_238:6 0.0003236889 +7 ropt_net_238:5 chany_top_in[4]:27 0.0002588432 +8 ropt_net_238:6 chany_top_in[4]:26 0.0002588432 + +*RES +0 ropt_mt_inst_820:X ropt_net_238:6 0.152 +1 ropt_net_238:2 ropt_mt_inst_858:A 0.152 +2 ropt_net_238:3 ropt_net_238:2 0.0045 +3 ropt_net_238:5 ropt_net_238:4 0.0045 +4 ropt_net_238:4 ropt_net_238:3 0.0005267857 +5 ropt_net_238:6 ropt_net_238:5 0.005024554 + +*END + +*D_NET ropt_net_232 0.001504777 //LENGTH 9.695 LUMPCC 0.0005486413 DR + +*CONN +*I ropt_mt_inst_838:X O *L 0 *C 48.925 125.800 +*I ropt_mt_inst_852:A I *L 0.001767 *C 40.480 126.480 +*N ropt_net_232:2 *C 40.518 126.480 +*N ropt_net_232:3 *C 43.240 126.480 +*N ropt_net_232:4 *C 43.240 125.800 +*N ropt_net_232:5 *C 48.888 125.800 + +*CAP +0 ropt_mt_inst_838:X 1e-06 +1 ropt_mt_inst_852:A 1e-06 +2 ropt_net_232:2 0.0001612471 +3 ropt_net_232:3 0.0002059944 +4 ropt_net_232:4 0.0003158209 +5 ropt_net_232:5 0.0002710735 +6 ropt_net_232:5 chany_top_in[4]:26 0.0001992463 +7 ropt_net_232:4 chany_top_in[4]:27 0.0001992463 +8 ropt_net_232:5 chany_top_out[5]:3 7.594816e-07 +9 ropt_net_232:2 chany_top_out[5]:4 7.431489e-05 +10 ropt_net_232:3 chany_top_out[5]:3 7.431489e-05 +11 ropt_net_232:4 chany_top_out[5]:4 7.594816e-07 + +*RES +0 ropt_mt_inst_838:X ropt_net_232:5 0.152 +1 ropt_net_232:5 ropt_net_232:4 0.005042411 +2 ropt_net_232:2 ropt_mt_inst_852:A 0.152 +3 ropt_net_232:3 ropt_net_232:2 0.002430804 +4 ropt_net_232:4 ropt_net_232:3 0.0006071429 + +*END + +*D_NET chany_bottom_out[13] 0.001876283 //LENGTH 13.660 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_856:X O *L 0 *C 56.775 6.800 +*P chany_bottom_out[13] O *L 0.7423 *C 49.680 1.285 +*N chany_bottom_out[13]:2 *C 50.600 1.360 +*N chany_bottom_out[13]:3 *C 50.600 6.793 +*N chany_bottom_out[13]:4 *C 50.620 6.800 +*N chany_bottom_out[13]:5 *C 54.733 6.800 +*N chany_bottom_out[13]:6 *C 54.740 6.800 +*N chany_bottom_out[13]:7 *C 54.785 6.800 +*N chany_bottom_out[13]:8 *C 56.738 6.800 + +*CAP +0 ropt_mt_inst_856:X 1e-06 +1 chany_bottom_out[13] 6.014859e-05 +2 chany_bottom_out[13]:2 0.0004589778 +3 chany_bottom_out[13]:3 0.0003988292 +4 chany_bottom_out[13]:4 0.000296696 +5 chany_bottom_out[13]:5 0.000296696 +6 chany_bottom_out[13]:6 3.676416e-05 +7 chany_bottom_out[13]:7 0.0001635854 +8 chany_bottom_out[13]:8 0.0001635854 + +*RES +0 ropt_mt_inst_856:X chany_bottom_out[13]:8 0.152 +1 chany_bottom_out[13]:8 chany_bottom_out[13]:7 0.001743304 +2 chany_bottom_out[13]:7 chany_bottom_out[13]:6 0.0045 +3 chany_bottom_out[13]:6 chany_bottom_out[13]:5 0.00341 +4 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.0006442916 +5 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.00341 +6 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.0008510916 +7 chany_bottom_out[13]:2 chany_bottom_out[13] 0.0001441333 + +*END + +*D_NET chany_top_in[16] 0.02373302 //LENGTH 178.375 LUMPCC 0.007486051 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 58.880 129.350 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.395 42.500 +*I ropt_mt_inst_825:A I *L 0.001766 *C 50.140 9.520 +*I mux_right_track_20\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.505 72.420 +*N chany_top_in[16]:4 *C 73.543 72.420 +*N chany_top_in[16]:5 *C 74.520 72.420 +*N chany_top_in[16]:6 *C 74.520 72.760 +*N chany_top_in[16]:7 *C 70.885 72.760 +*N chany_top_in[16]:8 *C 70.840 72.715 +*N chany_top_in[16]:9 *C 50.102 9.520 +*N chany_top_in[16]:10 *C 49.265 9.520 +*N chany_top_in[16]:11 *C 49.220 9.475 +*N chany_top_in[16]:12 *C 49.220 4.805 +*N chany_top_in[16]:13 *C 49.265 4.760 +*N chany_top_in[16]:14 *C 55.615 4.760 +*N chany_top_in[16]:15 *C 55.660 4.805 +*N chany_top_in[16]:16 *C 55.660 8.795 +*N chany_top_in[16]:17 *C 55.705 8.840 +*N chany_top_in[16]:18 *C 57.380 8.840 +*N chany_top_in[16]:19 *C 57.492 8.885 +*N chany_top_in[16]:20 *C 57.500 9.475 +*N chany_top_in[16]:21 *C 57.545 9.520 +*N chany_top_in[16]:22 *C 58.420 9.520 +*N chany_top_in[16]:23 *C 58.420 9.180 +*N chany_top_in[16]:24 *C 61.595 9.180 +*N chany_top_in[16]:25 *C 61.640 9.225 +*N chany_top_in[16]:26 *C 61.640 33.615 +*N chany_top_in[16]:27 *C 61.685 33.660 +*N chany_top_in[16]:28 *C 63.020 33.660 +*N chany_top_in[16]:29 *C 63.020 34.000 +*N chany_top_in[16]:30 *C 70.795 34.000 +*N chany_top_in[16]:31 *C 70.840 34.045 +*N chany_top_in[16]:32 *C 72.358 42.500 +*N chany_top_in[16]:33 *C 70.885 42.500 +*N chany_top_in[16]:34 *C 70.840 42.500 +*N chany_top_in[16]:35 *C 70.840 70.720 +*N chany_top_in[16]:36 *C 70.833 70.720 +*N chany_top_in[16]:37 *C 58.900 70.720 +*N chany_top_in[16]:38 *C 58.880 70.728 +*N chany_top_in[16]:39 *C 58.880 120.555 + +*CAP +0 chany_top_in[16] 0.0005196105 +1 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +2 ropt_mt_inst_825:A 1e-06 +3 mux_right_track_20\/mux_l1_in_0_:A1 1e-06 +4 chany_top_in[16]:4 6.131439e-05 +5 chany_top_in[16]:5 8.60802e-05 +6 chany_top_in[16]:6 0.0003005704 +7 chany_top_in[16]:7 0.0002758045 +8 chany_top_in[16]:8 0.0001213361 +9 chany_top_in[16]:9 8.917711e-05 +10 chany_top_in[16]:10 8.917711e-05 +11 chany_top_in[16]:11 0.000272284 +12 chany_top_in[16]:12 0.000272284 +13 chany_top_in[16]:13 0.0003280852 +14 chany_top_in[16]:14 0.0003280852 +15 chany_top_in[16]:15 0.0001425698 +16 chany_top_in[16]:16 0.0001425698 +17 chany_top_in[16]:17 0.0001376162 +18 chany_top_in[16]:18 0.0001376162 +19 chany_top_in[16]:19 5.404491e-05 +20 chany_top_in[16]:20 5.404491e-05 +21 chany_top_in[16]:21 7.870097e-05 +22 chany_top_in[16]:22 0.0001039486 +23 chany_top_in[16]:23 0.0002039013 +24 chany_top_in[16]:24 0.0001786537 +25 chany_top_in[16]:25 0.001119731 +26 chany_top_in[16]:26 0.001119731 +27 chany_top_in[16]:27 0.000100814 +28 chany_top_in[16]:28 0.0001265116 +29 chany_top_in[16]:29 0.0005008951 +30 chany_top_in[16]:30 0.0004751976 +31 chany_top_in[16]:31 0.0003425994 +32 chany_top_in[16]:32 0.0001359654 +33 chany_top_in[16]:33 0.0001359654 +34 chany_top_in[16]:34 0.001730013 +35 chany_top_in[16]:35 0.001517091 +36 chany_top_in[16]:36 0.0009627173 +37 chany_top_in[16]:37 0.0009627173 +38 chany_top_in[16]:38 0.001258465 +39 chany_top_in[16]:39 0.001778076 +40 chany_top_in[16]:31 chanx_right_in[11]:12 3.494786e-05 +41 chany_top_in[16]:35 chanx_right_in[11]:4 0.000248777 +42 chany_top_in[16]:35 chanx_right_in[11]:8 1.360683e-05 +43 chany_top_in[16]:35 chanx_right_in[11]:11 1.071517e-05 +44 chany_top_in[16]:34 chanx_right_in[11]:5 0.000248777 +45 chany_top_in[16]:34 chanx_right_in[11]:11 4.855469e-05 +46 chany_top_in[16]:34 chanx_right_in[11]:12 1.071517e-05 +47 chany_top_in[16]:16 ropt_net_194:5 5.211605e-05 +48 chany_top_in[16]:14 ropt_net_194:3 3.410263e-06 +49 chany_top_in[16]:15 ropt_net_194:4 5.211605e-05 +50 chany_top_in[16]:13 ropt_net_194:2 3.410263e-06 +51 chany_top_in[16]:38 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.001775439 +52 chany_top_in[16]:39 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.001775439 +53 chany_top_in[16]:38 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0009573804 +54 chany_top_in[16]:39 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0009573804 +55 chany_top_in[16]:31 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.851098e-05 +56 chany_top_in[16]:35 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.566777e-05 +57 chany_top_in[16]:34 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.566777e-05 +58 chany_top_in[16]:34 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.851098e-05 +59 chany_top_in[16]:26 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000140425 +60 chany_top_in[16]:25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000140425 +61 chany_top_in[16]:16 ropt_net_220:4 0.0001128171 +62 chany_top_in[16]:14 ropt_net_220:7 3.286697e-06 +63 chany_top_in[16]:15 ropt_net_220:5 0.0001128171 +64 chany_top_in[16]:13 ropt_net_220:6 3.286697e-06 +65 chany_top_in[16]:14 ropt_net_231:7 0.000201682 +66 chany_top_in[16]:13 ropt_net_231:6 0.000201682 +67 chany_top_in[16]:12 ropt_net_231:5 6.205701e-05 +68 chany_top_in[16]:11 ropt_net_231:4 6.205701e-05 +69 chany_top_in[16]:26 mux_bottom_track_25/BUF_net_66:5 3.218754e-05 +70 chany_top_in[16]:25 mux_bottom_track_25/BUF_net_66:4 3.218754e-05 + +*RES +0 chany_top_in[16] chany_top_in[16]:39 0.001377883 +1 chany_top_in[16]:30 chany_top_in[16]:29 0.006941965 +2 chany_top_in[16]:31 chany_top_in[16]:30 0.0045 +3 chany_top_in[16]:27 chany_top_in[16]:26 0.0045 +4 chany_top_in[16]:26 chany_top_in[16]:25 0.02177679 +5 chany_top_in[16]:24 chany_top_in[16]:23 0.002834822 +6 chany_top_in[16]:25 chany_top_in[16]:24 0.0045 +7 chany_top_in[16]:21 chany_top_in[16]:20 0.0045 +8 chany_top_in[16]:20 chany_top_in[16]:19 0.0005267858 +9 chany_top_in[16]:18 chany_top_in[16]:17 0.001495536 +10 chany_top_in[16]:19 chany_top_in[16]:18 0.0045 +11 chany_top_in[16]:17 chany_top_in[16]:16 0.0045 +12 chany_top_in[16]:16 chany_top_in[16]:15 0.0035625 +13 chany_top_in[16]:14 chany_top_in[16]:13 0.005669643 +14 chany_top_in[16]:15 chany_top_in[16]:14 0.0045 +15 chany_top_in[16]:13 chany_top_in[16]:12 0.0045 +16 chany_top_in[16]:12 chany_top_in[16]:11 0.004169643 +17 chany_top_in[16]:10 chany_top_in[16]:9 0.0007477679 +18 chany_top_in[16]:11 chany_top_in[16]:10 0.0045 +19 chany_top_in[16]:9 ropt_mt_inst_825:A 0.152 +20 chany_top_in[16]:7 chany_top_in[16]:6 0.003245536 +21 chany_top_in[16]:8 chany_top_in[16]:7 0.0045 +22 chany_top_in[16]:4 mux_right_track_20\/mux_l1_in_0_:A1 0.152 +23 chany_top_in[16]:35 chany_top_in[16]:34 0.02519643 +24 chany_top_in[16]:35 chany_top_in[16]:8 0.00178125 +25 chany_top_in[16]:36 chany_top_in[16]:35 0.00341 +26 chany_top_in[16]:37 chany_top_in[16]:36 0.001869425 +27 chany_top_in[16]:38 chany_top_in[16]:37 0.00341 +28 chany_top_in[16]:33 chany_top_in[16]:32 0.001314732 +29 chany_top_in[16]:34 chany_top_in[16]:33 0.0045 +30 chany_top_in[16]:34 chany_top_in[16]:31 0.007549108 +31 chany_top_in[16]:32 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +32 chany_top_in[16]:22 chany_top_in[16]:21 0.0007812501 +33 chany_top_in[16]:23 chany_top_in[16]:22 0.0003035715 +34 chany_top_in[16]:28 chany_top_in[16]:27 0.001191964 +35 chany_top_in[16]:29 chany_top_in[16]:28 0.0003035715 +36 chany_top_in[16]:6 chany_top_in[16]:5 0.0003035714 +37 chany_top_in[16]:5 chany_top_in[16]:4 0.0008727679 +38 chany_top_in[16]:39 chany_top_in[16]:38 0.007806308 + +*END + +*D_NET right_top_grid_pin_45_[0] 0.01057996 //LENGTH 74.870 LUMPCC 0.00396636 DR + +*CONN +*P right_top_grid_pin_45_[0] I *L 0.29796 *C 109.020 102.035 +*I mux_right_track_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 77.915 91.460 +*I mux_right_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.950 118.660 +*I mux_right_track_6\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.830 118.660 +*N right_top_grid_pin_45_[0]:4 *C 78.720 115.600 +*N right_top_grid_pin_45_[0]:5 *C 68.868 118.660 +*N right_top_grid_pin_45_[0]:6 *C 78.913 118.660 +*N right_top_grid_pin_45_[0]:7 *C 78.990 118.660 +*N right_top_grid_pin_45_[0]:8 *C 79.120 118.615 +*N right_top_grid_pin_45_[0]:9 *C 79.120 115.657 +*N right_top_grid_pin_45_[0]:10 *C 79.120 115.600 +*N right_top_grid_pin_45_[0]:11 *C 79.120 115.593 +*N right_top_grid_pin_45_[0]:12 *C 79.120 102.008 +*N right_top_grid_pin_45_[0]:13 *C 79.140 102.000 +*N right_top_grid_pin_45_[0]:14 *C 77.953 91.460 +*N right_top_grid_pin_45_[0]:15 *C 80.455 91.460 +*N right_top_grid_pin_45_[0]:16 *C 80.500 91.505 +*N right_top_grid_pin_45_[0]:17 *C 80.500 101.943 +*N right_top_grid_pin_45_[0]:18 *C 80.500 102.000 +*N right_top_grid_pin_45_[0]:19 *C 101.660 102.000 +*N right_top_grid_pin_45_[0]:20 *C 101.660 101.320 +*N right_top_grid_pin_45_[0]:21 *C 109.013 101.320 +*N right_top_grid_pin_45_[0]:22 *C 109.020 101.378 + +*CAP +0 right_top_grid_pin_45_[0] 4.918373e-05 +1 mux_right_track_14\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_6\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_45_[0]:4 7.900524e-05 +5 right_top_grid_pin_45_[0]:5 0.0006469938 +6 right_top_grid_pin_45_[0]:6 0.0006725191 +7 right_top_grid_pin_45_[0]:7 2.552529e-05 +8 right_top_grid_pin_45_[0]:8 0.0002012869 +9 right_top_grid_pin_45_[0]:9 0.0002012869 +10 right_top_grid_pin_45_[0]:10 7.900524e-05 +11 right_top_grid_pin_45_[0]:11 0.0001852858 +12 right_top_grid_pin_45_[0]:12 0.0001852858 +13 right_top_grid_pin_45_[0]:13 0.0001170326 +14 right_top_grid_pin_45_[0]:14 0.0001727032 +15 right_top_grid_pin_45_[0]:15 0.0001727032 +16 right_top_grid_pin_45_[0]:16 0.0005265879 +17 right_top_grid_pin_45_[0]:17 0.0005265879 +18 right_top_grid_pin_45_[0]:18 0.0009350976 +19 right_top_grid_pin_45_[0]:19 0.0008611538 +20 right_top_grid_pin_45_[0]:20 0.0004836294 +21 right_top_grid_pin_45_[0]:21 0.0004405408 +22 right_top_grid_pin_45_[0]:22 4.918373e-05 +23 right_top_grid_pin_45_[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.478355e-07 +24 right_top_grid_pin_45_[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0006309195 +25 right_top_grid_pin_45_[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0006309195 +26 right_top_grid_pin_45_[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.478355e-07 +27 right_top_grid_pin_45_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002122458 +28 right_top_grid_pin_45_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0004186737 +29 right_top_grid_pin_45_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0004186737 +30 right_top_grid_pin_45_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0002122458 +31 right_top_grid_pin_45_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001155476 +32 right_top_grid_pin_45_[0]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001155476 +33 right_top_grid_pin_45_[0]:21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001226203 +34 right_top_grid_pin_45_[0]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.378674e-06 +35 right_top_grid_pin_45_[0]:18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004742467 +36 right_top_grid_pin_45_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.378674e-06 +37 right_top_grid_pin_45_[0]:19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004742467 +38 right_top_grid_pin_45_[0]:20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001226203 + +*RES +0 right_top_grid_pin_45_[0] right_top_grid_pin_45_[0]:22 0.0005870537 +1 right_top_grid_pin_45_[0]:22 right_top_grid_pin_45_[0]:21 0.00341 +2 right_top_grid_pin_45_[0]:21 right_top_grid_pin_45_[0]:20 0.001151892 +3 right_top_grid_pin_45_[0]:7 right_top_grid_pin_45_[0]:6 6.919643e-05 +4 right_top_grid_pin_45_[0]:8 right_top_grid_pin_45_[0]:7 0.0045 +5 right_top_grid_pin_45_[0]:9 right_top_grid_pin_45_[0]:8 0.002640625 +6 right_top_grid_pin_45_[0]:10 right_top_grid_pin_45_[0]:9 0.00341 +7 right_top_grid_pin_45_[0]:10 right_top_grid_pin_45_[0]:4 5.69697e-05 +8 right_top_grid_pin_45_[0]:11 right_top_grid_pin_45_[0]:10 0.00341 +9 right_top_grid_pin_45_[0]:13 right_top_grid_pin_45_[0]:12 0.00341 +10 right_top_grid_pin_45_[0]:12 right_top_grid_pin_45_[0]:11 0.002128317 +11 right_top_grid_pin_45_[0]:5 mux_right_track_6\/mux_l1_in_1_:A0 0.152 +12 right_top_grid_pin_45_[0]:17 right_top_grid_pin_45_[0]:16 0.009319196 +13 right_top_grid_pin_45_[0]:18 right_top_grid_pin_45_[0]:17 0.00341 +14 right_top_grid_pin_45_[0]:18 right_top_grid_pin_45_[0]:13 0.0002130667 +15 right_top_grid_pin_45_[0]:15 right_top_grid_pin_45_[0]:14 0.002234375 +16 right_top_grid_pin_45_[0]:16 right_top_grid_pin_45_[0]:15 0.0045 +17 right_top_grid_pin_45_[0]:14 mux_right_track_14\/mux_l2_in_0_:A0 0.152 +18 right_top_grid_pin_45_[0]:6 mux_right_track_2\/mux_l1_in_1_:A0 0.152 +19 right_top_grid_pin_45_[0]:6 right_top_grid_pin_45_[0]:5 0.00896875 +20 right_top_grid_pin_45_[0]:19 right_top_grid_pin_45_[0]:18 0.003315066 +21 right_top_grid_pin_45_[0]:20 right_top_grid_pin_45_[0]:19 0.0001065333 + +*END + +*D_NET chany_top_out[0] 0.001014368 //LENGTH 8.355 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 42.780 121.040 +*P chany_top_out[0] O *L 0.7423 *C 42.780 129.235 +*N chany_top_out[0]:2 *C 42.780 121.085 +*N chany_top_out[0]:3 *C 42.780 121.040 + +*CAP +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[0] 0.0004893579 +2 chany_top_out[0]:2 0.0004893579 +3 chany_top_out[0]:3 3.465257e-05 + +*RES +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[0]:3 0.152 +1 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +2 chany_top_out[0]:2 chany_top_out[0] 0.007276786 + +*END + +*D_NET chany_top_out[16] 0.001503572 //LENGTH 12.550 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 45.540 120.700 +*P chany_top_out[16] O *L 0.7423 *C 48.300 129.235 +*N chany_top_out[16]:2 *C 48.300 120.405 +*N chany_top_out[16]:3 *C 48.255 120.360 +*N chany_top_out[16]:4 *C 45.540 120.360 +*N chany_top_out[16]:5 *C 45.540 120.700 + +*CAP +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[16] 0.0005030623 +2 chany_top_out[16]:2 0.0005030623 +3 chany_top_out[16]:3 0.0002006239 +4 chany_top_out[16]:4 0.0002317083 +5 chany_top_out[16]:5 6.411459e-05 + +*RES +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[16]:5 0.152 +1 chany_top_out[16]:3 chany_top_out[16]:2 0.0045 +2 chany_top_out[16]:2 chany_top_out[16] 0.007883929 +3 chany_top_out[16]:5 chany_top_out[16]:4 0.0003035715 +4 chany_top_out[16]:4 chany_top_out[16]:3 0.002424107 + +*END + +*D_NET chanx_right_out[4] 0.003060599 //LENGTH 19.520 LUMPCC 0.001347345 DR + +*CONN +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 100.740 88.060 +*P chanx_right_out[4] O *L 0.7423 *C 111.930 80.240 +*N chanx_right_out[4]:2 *C 100.748 80.240 +*N chanx_right_out[4]:3 *C 100.740 80.297 +*N chanx_right_out[4]:4 *C 100.740 88.015 +*N chanx_right_out[4]:5 *C 100.740 88.060 + +*CAP +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[4] 0.0005298111 +2 chanx_right_out[4]:2 0.0005298111 +3 chanx_right_out[4]:3 0.000310755 +4 chanx_right_out[4]:4 0.000310755 +5 chanx_right_out[4]:5 3.112175e-05 +6 chanx_right_out[4] chanx_right_in[14]:12 0.0004990408 +7 chanx_right_out[4]:2 chanx_right_in[14]:11 0.0004990408 +8 chanx_right_out[4]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001746318 +9 chanx_right_out[4]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001746318 + +*RES +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[4]:5 0.152 +1 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +2 chanx_right_out[4]:2 chanx_right_out[4] 0.001751925 +3 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +4 chanx_right_out[4]:4 chanx_right_out[4]:3 0.006890625 + +*END + +*D_NET chanx_right_out[12] 0.001071716 //LENGTH 7.140 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 42.160 +*P chanx_right_out[12] O *L 0.7423 *C 111.855 42.160 +*N chanx_right_out[12]:2 *C 104.888 42.160 +*N chanx_right_out[12]:3 *C 104.880 42.160 +*N chanx_right_out[12]:4 *C 104.880 42.160 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 0.000502522 +2 chanx_right_out[12]:2 0.000502522 +3 chanx_right_out[12]:3 3.39482e-05 +4 chanx_right_out[12]:4 3.172378e-05 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:4 0.152 +1 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +2 chanx_right_out[12]:2 chanx_right_out[12] 0.001091575 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0045 + +*END + +*D_NET chany_bottom_out[0] 0.00151218 //LENGTH 12.530 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 48.760 11.900 +*P chany_bottom_out[0] O *L 0.7423 *C 50.140 1.325 +*N chany_bottom_out[0]:2 *C 50.140 11.900 +*N chany_bottom_out[0]:3 *C 49.680 11.900 +*N chany_bottom_out[0]:4 *C 49.635 11.900 +*N chany_bottom_out[0]:5 *C 48.797 11.900 + +*CAP +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[0] 0.0006199109 +2 chany_bottom_out[0]:2 0.0006520682 +3 chany_bottom_out[0]:3 6.240416e-05 +4 chany_bottom_out[0]:4 8.839837e-05 +5 chany_bottom_out[0]:5 8.839837e-05 + +*RES +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[0]:5 0.152 +1 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.0045 +2 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0004107143 +3 chany_bottom_out[0]:5 chany_bottom_out[0]:4 0.0007477679 +4 chany_bottom_out[0]:2 chany_bottom_out[0] 0.009441964 + +*END + +*D_NET ropt_net_197 0.002197809 //LENGTH 16.375 LUMPCC 0.0006742707 DR + +*CONN +*I mem_bottom_track_33\/BUFT_P_168:X O *L 0 *C 54.055 11.560 +*I ropt_mt_inst_818:A I *L 0.001767 *C 60.260 4.080 +*N ropt_net_197:2 *C 60.223 4.080 +*N ropt_net_197:3 *C 58.005 4.080 +*N ropt_net_197:4 *C 57.960 4.035 +*N ropt_net_197:5 *C 57.960 3.445 +*N ropt_net_197:6 *C 57.915 3.400 +*N ropt_net_197:7 *C 54.325 3.400 +*N ropt_net_197:8 *C 54.280 3.445 +*N ropt_net_197:9 *C 54.280 11.515 +*N ropt_net_197:10 *C 54.280 11.560 +*N ropt_net_197:11 *C 54.055 11.560 + +*CAP +0 mem_bottom_track_33\/BUFT_P_168:X 1e-06 +1 ropt_mt_inst_818:A 1e-06 +2 ropt_net_197:2 9.451028e-05 +3 ropt_net_197:3 9.451028e-05 +4 ropt_net_197:4 5.877573e-05 +5 ropt_net_197:5 5.877573e-05 +6 ropt_net_197:6 0.0001879786 +7 ropt_net_197:7 0.0001879786 +8 ropt_net_197:8 0.0003661908 +9 ropt_net_197:9 0.0003661908 +10 ropt_net_197:10 5.29778e-05 +11 ropt_net_197:11 5.364956e-05 +12 ropt_net_197:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0001174621 +13 ropt_net_197:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0001174621 +14 ropt_net_197:9 ropt_net_220:4 3.408001e-05 +15 ropt_net_197:7 ropt_net_220:6 0.0001154418 +16 ropt_net_197:8 ropt_net_220:5 3.408001e-05 +17 ropt_net_197:6 ropt_net_220:7 0.0001154418 +18 ropt_net_197:5 ropt_net_220:5 7.02762e-07 +19 ropt_net_197:3 ropt_net_220:6 6.944859e-05 +20 ropt_net_197:4 ropt_net_220:4 7.02762e-07 +21 ropt_net_197:2 ropt_net_220:7 6.944859e-05 + +*RES +0 mem_bottom_track_33\/BUFT_P_168:X ropt_net_197:11 0.152 +1 ropt_net_197:11 ropt_net_197:10 0.0001222826 +2 ropt_net_197:10 ropt_net_197:9 0.0045 +3 ropt_net_197:9 ropt_net_197:8 0.007205358 +4 ropt_net_197:7 ropt_net_197:6 0.003205357 +5 ropt_net_197:8 ropt_net_197:7 0.0045 +6 ropt_net_197:6 ropt_net_197:5 0.0045 +7 ropt_net_197:5 ropt_net_197:4 0.0005267857 +8 ropt_net_197:3 ropt_net_197:2 0.001979911 +9 ropt_net_197:4 ropt_net_197:3 0.0045 +10 ropt_net_197:2 ropt_mt_inst_818:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[1] 0.00273321 //LENGTH 20.335 LUMPCC 0.0001841624 DR + +*CONN +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.845 76.840 +*I mem_right_track_20\/FTB_25__55:A I *L 0.001746 *C 66.240 72.080 +*I mux_right_track_20\/mux_l2_in_0_:S I *L 0.00357 *C 74.420 69.070 +*N mux_tree_tapbuf_size3_2_sram[1]:3 *C 74.420 69.070 +*N mux_tree_tapbuf_size3_2_sram[1]:4 *C 74.377 69.330 +*N mux_tree_tapbuf_size3_2_sram[1]:5 *C 66.240 72.080 +*N mux_tree_tapbuf_size3_2_sram[1]:6 *C 66.240 72.035 +*N mux_tree_tapbuf_size3_2_sram[1]:7 *C 66.240 69.405 +*N mux_tree_tapbuf_size3_2_sram[1]:8 *C 66.285 69.360 +*N mux_tree_tapbuf_size3_2_sram[1]:9 *C 74.090 69.330 +*N mux_tree_tapbuf_size3_2_sram[1]:10 *C 74.060 69.405 +*N mux_tree_tapbuf_size3_2_sram[1]:11 *C 74.060 76.795 +*N mux_tree_tapbuf_size3_2_sram[1]:12 *C 74.060 76.840 +*N mux_tree_tapbuf_size3_2_sram[1]:13 *C 73.845 76.840 + +*CAP +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_20\/FTB_25__55:A 1e-06 +2 mux_right_track_20\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_2_sram[1]:3 5.409741e-05 +4 mux_tree_tapbuf_size3_2_sram[1]:4 7.165241e-05 +5 mux_tree_tapbuf_size3_2_sram[1]:5 3.126783e-05 +6 mux_tree_tapbuf_size3_2_sram[1]:6 0.0001579692 +7 mux_tree_tapbuf_size3_2_sram[1]:7 0.0001579692 +8 mux_tree_tapbuf_size3_2_sram[1]:8 0.0004708067 +9 mux_tree_tapbuf_size3_2_sram[1]:9 0.0005159784 +10 mux_tree_tapbuf_size3_2_sram[1]:10 0.0004892824 +11 mux_tree_tapbuf_size3_2_sram[1]:11 0.0004892824 +12 mux_tree_tapbuf_size3_2_sram[1]:12 5.362904e-05 +13 mux_tree_tapbuf_size3_2_sram[1]:13 5.411211e-05 +14 mux_tree_tapbuf_size3_2_sram[1]:8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.208119e-05 +15 mux_tree_tapbuf_size3_2_sram[1]:9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.208119e-05 + +*RES +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_2_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_2_sram[1]:8 mux_tree_tapbuf_size3_2_sram[1]:7 0.0045 +2 mux_tree_tapbuf_size3_2_sram[1]:7 mux_tree_tapbuf_size3_2_sram[1]:6 0.002348214 +3 mux_tree_tapbuf_size3_2_sram[1]:5 mem_right_track_20\/FTB_25__55:A 0.152 +4 mux_tree_tapbuf_size3_2_sram[1]:6 mux_tree_tapbuf_size3_2_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size3_2_sram[1]:13 mux_tree_tapbuf_size3_2_sram[1]:12 0.0001168478 +6 mux_tree_tapbuf_size3_2_sram[1]:12 mux_tree_tapbuf_size3_2_sram[1]:11 0.0045 +7 mux_tree_tapbuf_size3_2_sram[1]:11 mux_tree_tapbuf_size3_2_sram[1]:10 0.006598215 +8 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:8 0.006968751 +9 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:4 0.0001796875 +10 mux_tree_tapbuf_size3_2_sram[1]:10 mux_tree_tapbuf_size3_2_sram[1]:9 0.0045 +11 mux_tree_tapbuf_size3_2_sram[1]:3 mux_right_track_20\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size3_2_sram[1]:3 0.0001511628 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.0006706301 //LENGTH 5.350 LUMPCC 0.0001551768 DR + +*CONN +*I mem_right_track_16\/FTB_23__53:X O *L 0 *C 94.100 77.180 +*I mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 91.720 75.140 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 91.758 75.140 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 92.415 75.140 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 92.460 75.185 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 92.460 77.135 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 92.505 77.180 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 94.062 77.180 + +*CAP +0 mem_right_track_16\/FTB_23__53:X 1e-06 +1 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 6.564229e-05 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 6.564229e-05 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.0001160207 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0001160207 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 7.506365e-05 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 7.506365e-05 +8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 prog_clk[0]:90 7.294807e-05 +9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 prog_clk[0]:91 7.294807e-05 +10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 prog_clk[0]:93 4.105535e-06 +11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 prog_clk[0]:96 5.347799e-07 +12 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 prog_clk[0]:96 4.105535e-06 +13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 prog_clk[0]:99 5.347799e-07 + +*RES +0 mem_right_track_16\/FTB_23__53:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.001390625 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.001741072 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0005870535 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_right_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[0] 0.002999996 //LENGTH 24.225 LUMPCC 0.0001995025 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 48.605 77.180 +*I mux_top_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 59.440 72.420 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 46.635 82.620 +*N mux_tree_tapbuf_size4_1_sram[0]:3 *C 46.672 82.620 +*N mux_tree_tapbuf_size4_1_sram[0]:4 *C 48.715 82.620 +*N mux_tree_tapbuf_size4_1_sram[0]:5 *C 48.760 82.575 +*N mux_tree_tapbuf_size4_1_sram[0]:6 *C 59.403 72.420 +*N mux_tree_tapbuf_size4_1_sram[0]:7 *C 48.805 72.420 +*N mux_tree_tapbuf_size4_1_sram[0]:8 *C 48.760 72.465 +*N mux_tree_tapbuf_size4_1_sram[0]:9 *C 48.760 77.180 +*N mux_tree_tapbuf_size4_1_sram[0]:10 *C 48.760 77.180 +*N mux_tree_tapbuf_size4_1_sram[0]:11 *C 48.605 77.180 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_32\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size4_1_sram[0]:3 0.000184119 +4 mux_tree_tapbuf_size4_1_sram[0]:4 0.000184119 +5 mux_tree_tapbuf_size4_1_sram[0]:5 0.0002981119 +6 mux_tree_tapbuf_size4_1_sram[0]:6 0.0005873755 +7 mux_tree_tapbuf_size4_1_sram[0]:7 0.0005873755 +8 mux_tree_tapbuf_size4_1_sram[0]:8 0.0002598713 +9 mux_tree_tapbuf_size4_1_sram[0]:9 0.000589505 +10 mux_tree_tapbuf_size4_1_sram[0]:10 5.508607e-05 +11 mux_tree_tapbuf_size4_1_sram[0]:11 5.192974e-05 +12 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 9.975125e-05 +13 mux_tree_tapbuf_size4_1_sram[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 9.975125e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_1_sram[0]:11 0.152 +1 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[0]:6 0.009462054 +2 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size4_1_sram[0]:6 mux_top_track_32\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size4_1_sram[0]:4 mux_tree_tapbuf_size4_1_sram[0]:3 0.001823661 +5 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size4_1_sram[0]:3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size4_1_sram[0]:10 mux_tree_tapbuf_size4_1_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size4_1_sram[0]:9 mux_tree_tapbuf_size4_1_sram[0]:8 0.004209822 +9 mux_tree_tapbuf_size4_1_sram[0]:9 mux_tree_tapbuf_size4_1_sram[0]:5 0.004816964 +10 mux_tree_tapbuf_size4_1_sram[0]:11 mux_tree_tapbuf_size4_1_sram[0]:10 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size4_6_sram[2] 0.001406191 //LENGTH 10.770 LUMPCC 0.0003864424 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 31.125 47.600 +*I mux_right_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 34.400 41.480 +*I mem_right_track_24\/FTB_19__49:A I *L 0.001746 *C 33.120 47.600 +*N mux_tree_tapbuf_size4_6_sram[2]:3 *C 33.083 47.600 +*N mux_tree_tapbuf_size4_6_sram[2]:4 *C 34.363 41.480 +*N mux_tree_tapbuf_size4_6_sram[2]:5 *C 32.705 41.480 +*N mux_tree_tapbuf_size4_6_sram[2]:6 *C 32.660 41.525 +*N mux_tree_tapbuf_size4_6_sram[2]:7 *C 32.660 47.555 +*N mux_tree_tapbuf_size4_6_sram[2]:8 *C 32.660 47.600 +*N mux_tree_tapbuf_size4_6_sram[2]:9 *C 31.163 47.600 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_24\/FTB_19__49:A 1e-06 +3 mux_tree_tapbuf_size4_6_sram[2]:3 3.470369e-05 +4 mux_tree_tapbuf_size4_6_sram[2]:4 0.0001092765 +5 mux_tree_tapbuf_size4_6_sram[2]:5 0.0001092765 +6 mux_tree_tapbuf_size4_6_sram[2]:6 0.0002411509 +7 mux_tree_tapbuf_size4_6_sram[2]:7 0.0002411509 +8 mux_tree_tapbuf_size4_6_sram[2]:8 0.0001761958 +9 mux_tree_tapbuf_size4_6_sram[2]:9 0.0001049946 +10 mux_tree_tapbuf_size4_6_sram[2]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001615853 +11 mux_tree_tapbuf_size4_6_sram[2]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.163587e-05 +12 mux_tree_tapbuf_size4_6_sram[2]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001615853 +13 mux_tree_tapbuf_size4_6_sram[2]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.163587e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_6_sram[2]:9 0.152 +1 mux_tree_tapbuf_size4_6_sram[2]:8 mux_tree_tapbuf_size4_6_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size4_6_sram[2]:8 mux_tree_tapbuf_size4_6_sram[2]:3 0.0003772322 +3 mux_tree_tapbuf_size4_6_sram[2]:7 mux_tree_tapbuf_size4_6_sram[2]:6 0.005383929 +4 mux_tree_tapbuf_size4_6_sram[2]:5 mux_tree_tapbuf_size4_6_sram[2]:4 0.001479911 +5 mux_tree_tapbuf_size4_6_sram[2]:6 mux_tree_tapbuf_size4_6_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size4_6_sram[2]:4 mux_right_track_24\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size4_6_sram[2]:9 mux_tree_tapbuf_size4_6_sram[2]:8 0.001337054 +8 mux_tree_tapbuf_size4_6_sram[2]:3 mem_right_track_24\/FTB_19__49:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_6_ccff_tail[0] 0.0007367663 //LENGTH 6.350 LUMPCC 9.057652e-05 DR + +*CONN +*I mem_right_track_24\/FTB_19__49:X O *L 0 *C 36.115 46.920 +*I mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 33.755 49.980 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:2 *C 33.793 49.980 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:3 *C 34.455 49.980 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 *C 34.500 49.935 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 *C 34.500 46.965 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:6 *C 34.545 46.920 +*N mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:7 *C 36.078 46.920 + +*CAP +0 mem_right_track_24\/FTB_19__49:X 1e-06 +1 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:2 6.679039e-05 +3 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:3 6.679039e-05 +4 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 0.0001307472 +5 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 0.0001307472 +6 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:6 0.0001245573 +7 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:7 0.0001245573 +8 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 chanx_right_in[13]:5 4.528826e-05 +9 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 chanx_right_in[13]:6 4.528826e-05 + +*RES +0 mem_right_track_24\/FTB_19__49:X mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:2 mem_right_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:2 0.0005915179 +3 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:6 0.001368304 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[0] 0.004005027 //LENGTH 31.885 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 62.405 53.040 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 53.700 47.260 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 52.615 55.420 +*I mux_bottom_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 61.540 58.480 +*N mux_tree_tapbuf_size5_4_sram[0]:4 *C 61.503 58.480 +*N mux_tree_tapbuf_size5_4_sram[0]:5 *C 54.325 58.480 +*N mux_tree_tapbuf_size5_4_sram[0]:6 *C 54.280 58.435 +*N mux_tree_tapbuf_size5_4_sram[0]:7 *C 52.653 55.420 +*N mux_tree_tapbuf_size5_4_sram[0]:8 *C 54.235 55.420 +*N mux_tree_tapbuf_size5_4_sram[0]:9 *C 54.280 55.420 +*N mux_tree_tapbuf_size5_4_sram[0]:10 *C 53.738 47.260 +*N mux_tree_tapbuf_size5_4_sram[0]:11 *C 54.235 47.260 +*N mux_tree_tapbuf_size5_4_sram[0]:12 *C 54.280 47.305 +*N mux_tree_tapbuf_size5_4_sram[0]:13 *C 54.280 53.720 +*N mux_tree_tapbuf_size5_4_sram[0]:14 *C 54.288 53.720 +*N mux_tree_tapbuf_size5_4_sram[0]:15 *C 62.553 53.720 +*N mux_tree_tapbuf_size5_4_sram[0]:16 *C 62.560 53.663 +*N mux_tree_tapbuf_size5_4_sram[0]:17 *C 62.560 53.085 +*N mux_tree_tapbuf_size5_4_sram[0]:18 *C 62.560 53.040 +*N mux_tree_tapbuf_size5_4_sram[0]:19 *C 62.405 53.040 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_4_sram[0]:4 0.0004387632 +5 mux_tree_tapbuf_size5_4_sram[0]:5 0.0004387632 +6 mux_tree_tapbuf_size5_4_sram[0]:6 0.0001738055 +7 mux_tree_tapbuf_size5_4_sram[0]:7 0.0001336657 +8 mux_tree_tapbuf_size5_4_sram[0]:8 0.0001336657 +9 mux_tree_tapbuf_size5_4_sram[0]:9 0.0002962136 +10 mux_tree_tapbuf_size5_4_sram[0]:10 6.187045e-05 +11 mux_tree_tapbuf_size5_4_sram[0]:11 6.187045e-05 +12 mux_tree_tapbuf_size5_4_sram[0]:12 0.0003244439 +13 mux_tree_tapbuf_size5_4_sram[0]:13 0.000444308 +14 mux_tree_tapbuf_size5_4_sram[0]:14 0.0006245985 +15 mux_tree_tapbuf_size5_4_sram[0]:15 0.0006245985 +16 mux_tree_tapbuf_size5_4_sram[0]:16 6.293074e-05 +17 mux_tree_tapbuf_size5_4_sram[0]:17 6.293074e-05 +18 mux_tree_tapbuf_size5_4_sram[0]:18 6.162505e-05 +19 mux_tree_tapbuf_size5_4_sram[0]:19 5.697417e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_4_sram[0]:19 0.152 +1 mux_tree_tapbuf_size5_4_sram[0]:10 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_4_sram[0]:11 mux_tree_tapbuf_size5_4_sram[0]:10 0.0004441965 +3 mux_tree_tapbuf_size5_4_sram[0]:12 mux_tree_tapbuf_size5_4_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size5_4_sram[0]:8 mux_tree_tapbuf_size5_4_sram[0]:7 0.001412946 +5 mux_tree_tapbuf_size5_4_sram[0]:9 mux_tree_tapbuf_size5_4_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size5_4_sram[0]:9 mux_tree_tapbuf_size5_4_sram[0]:6 0.002691964 +7 mux_tree_tapbuf_size5_4_sram[0]:7 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size5_4_sram[0]:13 mux_tree_tapbuf_size5_4_sram[0]:12 0.005727679 +9 mux_tree_tapbuf_size5_4_sram[0]:13 mux_tree_tapbuf_size5_4_sram[0]:9 0.001517857 +10 mux_tree_tapbuf_size5_4_sram[0]:14 mux_tree_tapbuf_size5_4_sram[0]:13 0.00341 +11 mux_tree_tapbuf_size5_4_sram[0]:16 mux_tree_tapbuf_size5_4_sram[0]:15 0.00341 +12 mux_tree_tapbuf_size5_4_sram[0]:15 mux_tree_tapbuf_size5_4_sram[0]:14 0.00129485 +13 mux_tree_tapbuf_size5_4_sram[0]:18 mux_tree_tapbuf_size5_4_sram[0]:17 0.0045 +14 mux_tree_tapbuf_size5_4_sram[0]:17 mux_tree_tapbuf_size5_4_sram[0]:16 0.000515625 +15 mux_tree_tapbuf_size5_4_sram[0]:19 mux_tree_tapbuf_size5_4_sram[0]:18 8.423914e-05 +16 mux_tree_tapbuf_size5_4_sram[0]:5 mux_tree_tapbuf_size5_4_sram[0]:4 0.006408482 +17 mux_tree_tapbuf_size5_4_sram[0]:6 mux_tree_tapbuf_size5_4_sram[0]:5 0.0045 +18 mux_tree_tapbuf_size5_4_sram[0]:4 mux_bottom_track_25\/mux_l1_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.00299757 //LENGTH 22.605 LUMPCC 0.0003971925 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 85.405 47.940 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 83.360 53.040 +*I mux_top_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 81.780 56.440 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 78.835 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 78.835 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 78.660 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 78.660 58.775 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 81.743 56.440 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 78.705 56.440 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 78.660 56.440 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 78.660 53.085 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 78.705 53.040 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 83.273 53.040 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 83.260 52.995 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 83.260 47.985 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 83.305 47.940 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 85.368 47.940 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 5.667434e-05 +5 mux_tree_tapbuf_size6_1_sram[1]:5 5.810909e-05 +6 mux_tree_tapbuf_size6_1_sram[1]:6 0.000156488 +7 mux_tree_tapbuf_size6_1_sram[1]:7 0.0001663806 +8 mux_tree_tapbuf_size6_1_sram[1]:8 0.0001663806 +9 mux_tree_tapbuf_size6_1_sram[1]:9 0.0004094824 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.0002212786 +11 mux_tree_tapbuf_size6_1_sram[1]:11 0.000299947 +12 mux_tree_tapbuf_size6_1_sram[1]:12 0.000299947 +13 mux_tree_tapbuf_size6_1_sram[1]:13 0.0001978356 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0001978356 +15 mux_tree_tapbuf_size6_1_sram[1]:15 0.0001830092 +16 mux_tree_tapbuf_size6_1_sram[1]:16 0.0001830092 +17 mux_tree_tapbuf_size6_1_sram[1]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001370853 +18 mux_tree_tapbuf_size6_1_sram[1]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001370853 +19 mux_tree_tapbuf_size6_1_sram[1]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.277114e-05 +20 mux_tree_tapbuf_size6_1_sram[1]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.87398e-05 +21 mux_tree_tapbuf_size6_1_sram[1]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.87398e-05 +22 mux_tree_tapbuf_size6_1_sram[1]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.277114e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:12 mux_top_track_4\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.004078125 +3 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.004473214 +6 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.001841518 +7 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:9 0.002995536 +9 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 9.51087e-05 +10 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +11 mux_tree_tapbuf_size6_1_sram[1]:4 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.002712054 +13 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0045 +14 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:6 0.002084821 +15 mux_tree_tapbuf_size6_1_sram[1]:7 mux_top_track_4\/mux_l2_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_5_sram[2] 0.002277924 //LENGTH 18.460 LUMPCC 0.0007800861 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 79.885 37.060 +*I mux_bottom_track_5\/mux_l3_in_0_:S I *L 0.008363 *C 78.200 23.290 +*I mem_bottom_track_5\/FTB_6__36:A I *L 0.001746 *C 78.200 39.440 +*N mux_tree_tapbuf_size6_5_sram[2]:3 *C 78.200 39.440 +*N mux_tree_tapbuf_size6_5_sram[2]:4 *C 78.200 39.395 +*N mux_tree_tapbuf_size6_5_sram[2]:5 *C 78.200 23.335 +*N mux_tree_tapbuf_size6_5_sram[2]:6 *C 78.200 37.060 +*N mux_tree_tapbuf_size6_5_sram[2]:7 *C 78.245 37.060 +*N mux_tree_tapbuf_size6_5_sram[2]:8 *C 79.848 37.060 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_5\/FTB_6__36:A 1e-06 +3 mux_tree_tapbuf_size6_5_sram[2]:3 3.024094e-05 +4 mux_tree_tapbuf_size6_5_sram[2]:4 0.0001188621 +5 mux_tree_tapbuf_size6_5_sram[2]:5 0.0005350678 +6 mux_tree_tapbuf_size6_5_sram[2]:6 0.0006836289 +7 mux_tree_tapbuf_size6_5_sram[2]:7 6.351926e-05 +8 mux_tree_tapbuf_size6_5_sram[2]:8 6.351926e-05 +9 mux_tree_tapbuf_size6_5_sram[2]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.44213e-05 +10 mux_tree_tapbuf_size6_5_sram[2]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.622839e-06 +11 mux_tree_tapbuf_size6_5_sram[2]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.007138e-05 +12 mux_tree_tapbuf_size6_5_sram[2]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.44213e-05 +13 mux_tree_tapbuf_size6_5_sram[2]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.622839e-06 +14 mux_tree_tapbuf_size6_5_sram[2]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.007138e-05 +15 mux_tree_tapbuf_size6_5_sram[2]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002689275 +16 mux_tree_tapbuf_size6_5_sram[2]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002689275 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_5_sram[2]:8 0.152 +1 mux_tree_tapbuf_size6_5_sram[2]:7 mux_tree_tapbuf_size6_5_sram[2]:6 0.0045 +2 mux_tree_tapbuf_size6_5_sram[2]:6 mux_tree_tapbuf_size6_5_sram[2]:5 0.01225447 +3 mux_tree_tapbuf_size6_5_sram[2]:6 mux_tree_tapbuf_size6_5_sram[2]:4 0.002084821 +4 mux_tree_tapbuf_size6_5_sram[2]:8 mux_tree_tapbuf_size6_5_sram[2]:7 0.001430804 +5 mux_tree_tapbuf_size6_5_sram[2]:3 mem_bottom_track_5\/FTB_6__36:A 0.152 +6 mux_tree_tapbuf_size6_5_sram[2]:4 mux_tree_tapbuf_size6_5_sram[2]:3 0.0045 +7 mux_tree_tapbuf_size6_5_sram[2]:5 mux_bottom_track_5\/mux_l3_in_0_:S 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_2_ccff_tail[0] 0.002027022 //LENGTH 16.900 LUMPCC 0.0003112381 DR + +*CONN +*I mem_top_track_8\/FTB_3__33:X O *L 0 *C 55.885 67.320 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 44.335 71.740 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 *C 44.373 71.740 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 *C 54.695 71.740 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 *C 54.740 71.695 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 *C 54.740 67.365 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 *C 54.785 67.320 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 *C 55.848 67.320 + +*CAP +0 mem_top_track_8\/FTB_3__33:X 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 0.0005596972 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0005596972 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.0002066829 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0002066829 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 9.051165e-05 +7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 9.051165e-05 +8 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 prog_clk[0]:296 5.58678e-05 +9 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 prog_clk[0]:299 5.58678e-05 +10 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 mux_tree_tapbuf_size4_1_sram[0]:7 9.975125e-05 +11 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size4_1_sram[0]:6 9.975125e-05 + +*RES +0 mem_top_track_8\/FTB_3__33:X mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 0.009216518 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.0009486608 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[1] 0.00301328 //LENGTH 26.165 LUMPCC 0.0003335355 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 62.865 96.560 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 58.135 102.340 +*I mux_right_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 71.860 96.560 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 70.020 99.280 +*N mux_tree_tapbuf_size7_1_sram[1]:4 *C 70.035 99.280 +*N mux_tree_tapbuf_size7_1_sram[1]:5 *C 70.358 99.280 +*N mux_tree_tapbuf_size7_1_sram[1]:6 *C 70.380 99.235 +*N mux_tree_tapbuf_size7_1_sram[1]:7 *C 71.823 96.560 +*N mux_tree_tapbuf_size7_1_sram[1]:8 *C 70.885 96.560 +*N mux_tree_tapbuf_size7_1_sram[1]:9 *C 70.810 96.530 +*N mux_tree_tapbuf_size7_1_sram[1]:10 *C 70.795 96.220 +*N mux_tree_tapbuf_size7_1_sram[1]:11 *C 70.425 96.220 +*N mux_tree_tapbuf_size7_1_sram[1]:12 *C 70.380 96.575 +*N mux_tree_tapbuf_size7_1_sram[1]:13 *C 70.335 96.560 +*N mux_tree_tapbuf_size7_1_sram[1]:14 *C 58.135 102.340 +*N mux_tree_tapbuf_size7_1_sram[1]:15 *C 58.420 102.340 +*N mux_tree_tapbuf_size7_1_sram[1]:16 *C 58.420 102.295 +*N mux_tree_tapbuf_size7_1_sram[1]:17 *C 58.420 99.665 +*N mux_tree_tapbuf_size7_1_sram[1]:18 *C 58.465 99.620 +*N mux_tree_tapbuf_size7_1_sram[1]:19 *C 62.975 99.620 +*N mux_tree_tapbuf_size7_1_sram[1]:20 *C 63.020 99.575 +*N mux_tree_tapbuf_size7_1_sram[1]:21 *C 63.020 96.605 +*N mux_tree_tapbuf_size7_1_sram[1]:22 *C 63.065 96.560 +*N mux_tree_tapbuf_size7_1_sram[1]:23 *C 62.865 96.560 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_4\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_1_sram[1]:4 5.032856e-05 +5 mux_tree_tapbuf_size7_1_sram[1]:5 5.032856e-05 +6 mux_tree_tapbuf_size7_1_sram[1]:6 0.0001566592 +7 mux_tree_tapbuf_size7_1_sram[1]:7 7.374397e-05 +8 mux_tree_tapbuf_size7_1_sram[1]:8 7.374397e-05 +9 mux_tree_tapbuf_size7_1_sram[1]:9 3.999474e-05 +10 mux_tree_tapbuf_size7_1_sram[1]:10 5.844247e-05 +11 mux_tree_tapbuf_size7_1_sram[1]:11 3.157718e-05 +12 mux_tree_tapbuf_size7_1_sram[1]:12 0.0001697886 +13 mux_tree_tapbuf_size7_1_sram[1]:13 0.0003551863 +14 mux_tree_tapbuf_size7_1_sram[1]:14 4.844975e-05 +15 mux_tree_tapbuf_size7_1_sram[1]:15 5.228988e-05 +16 mux_tree_tapbuf_size7_1_sram[1]:16 0.000163777 +17 mux_tree_tapbuf_size7_1_sram[1]:17 0.000163777 +18 mux_tree_tapbuf_size7_1_sram[1]:18 0.0002305275 +19 mux_tree_tapbuf_size7_1_sram[1]:19 0.0002305275 +20 mux_tree_tapbuf_size7_1_sram[1]:20 0.0001536432 +21 mux_tree_tapbuf_size7_1_sram[1]:21 0.0001536432 +22 mux_tree_tapbuf_size7_1_sram[1]:22 0.0003728826 +23 mux_tree_tapbuf_size7_1_sram[1]:23 4.643325e-05 +24 mux_tree_tapbuf_size7_1_sram[1]:21 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.814173e-05 +25 mux_tree_tapbuf_size7_1_sram[1]:19 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.294945e-05 +26 mux_tree_tapbuf_size7_1_sram[1]:20 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.814173e-05 +27 mux_tree_tapbuf_size7_1_sram[1]:18 mux_right_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.294945e-05 +28 mux_tree_tapbuf_size7_1_sram[1]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.438549e-06 +29 mux_tree_tapbuf_size7_1_sram[1]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.239967e-05 +30 mux_tree_tapbuf_size7_1_sram[1]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.199945e-07 +31 mux_tree_tapbuf_size7_1_sram[1]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.438549e-06 +32 mux_tree_tapbuf_size7_1_sram[1]:22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.239967e-05 +33 mux_tree_tapbuf_size7_1_sram[1]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.485991e-06 +34 mux_tree_tapbuf_size7_1_sram[1]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.911576e-08 +35 mux_tree_tapbuf_size7_1_sram[1]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.485991e-06 +36 mux_tree_tapbuf_size7_1_sram[1]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.295331e-05 +37 mux_tree_tapbuf_size7_1_sram[1]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.199945e-07 +38 mux_tree_tapbuf_size7_1_sram[1]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.911576e-08 +39 mux_tree_tapbuf_size7_1_sram[1]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.295331e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_1_sram[1]:23 0.152 +1 mux_tree_tapbuf_size7_1_sram[1]:5 mux_tree_tapbuf_size7_1_sram[1]:4 0.0001752718 +2 mux_tree_tapbuf_size7_1_sram[1]:6 mux_tree_tapbuf_size7_1_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size7_1_sram[1]:4 mux_right_track_4\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size7_1_sram[1]:12 mux_tree_tapbuf_size7_1_sram[1]:11 0.000221875 +6 mux_tree_tapbuf_size7_1_sram[1]:12 mux_tree_tapbuf_size7_1_sram[1]:6 0.002375 +7 mux_tree_tapbuf_size7_1_sram[1]:22 mux_tree_tapbuf_size7_1_sram[1]:21 0.0045 +8 mux_tree_tapbuf_size7_1_sram[1]:22 mux_tree_tapbuf_size7_1_sram[1]:13 0.006491072 +9 mux_tree_tapbuf_size7_1_sram[1]:21 mux_tree_tapbuf_size7_1_sram[1]:20 0.002651786 +10 mux_tree_tapbuf_size7_1_sram[1]:19 mux_tree_tapbuf_size7_1_sram[1]:18 0.004026786 +11 mux_tree_tapbuf_size7_1_sram[1]:20 mux_tree_tapbuf_size7_1_sram[1]:19 0.0045 +12 mux_tree_tapbuf_size7_1_sram[1]:18 mux_tree_tapbuf_size7_1_sram[1]:17 0.0045 +13 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:16 0.002348214 +14 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:14 0.0001548913 +15 mux_tree_tapbuf_size7_1_sram[1]:16 mux_tree_tapbuf_size7_1_sram[1]:15 0.0045 +16 mux_tree_tapbuf_size7_1_sram[1]:14 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size7_1_sram[1]:23 mux_tree_tapbuf_size7_1_sram[1]:22 0.0001086957 +18 mux_tree_tapbuf_size7_1_sram[1]:8 mux_tree_tapbuf_size7_1_sram[1]:7 0.0008370535 +19 mux_tree_tapbuf_size7_1_sram[1]:9 mux_tree_tapbuf_size7_1_sram[1]:8 0.0045 +20 mux_tree_tapbuf_size7_1_sram[1]:7 mux_right_track_4\/mux_l2_in_1_:S 0.152 +21 mux_tree_tapbuf_size7_1_sram[1]:11 mux_tree_tapbuf_size7_1_sram[1]:10 0.0003303571 +22 mux_tree_tapbuf_size7_1_sram[1]:10 mux_tree_tapbuf_size7_1_sram[1]:9 0.00019375 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.01341091 //LENGTH 99.175 LUMPCC 0.003732236 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_0_:X O *L 0 *C 87.115 67.320 +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 44.340 120.890 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 44.340 120.890 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 44.620 121.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 44.620 121.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 44.628 121.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 80.020 121.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 80.040 121.032 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 80.040 89.088 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 80.060 89.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 84.620 89.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 84.640 89.073 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 84.640 78.208 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 84.660 78.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 87.392 78.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 87.400 78.142 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:16 *C 87.400 67.365 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:17 *C 87.400 67.320 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:18 *C 87.115 67.320 + +*CAP +0 mux_top_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.440729e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.948434e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.859925e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001990293 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001990293 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0008748764 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0008748763 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0003656013 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0003656013 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0006354216 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0006354216 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0002202271 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0002202271 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.00062421 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.00062421 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:17 5.758496e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:18 5.534145e-05 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 chany_bottom_in[4]:32 5.717797e-05 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 chany_bottom_in[4]:25 5.717797e-05 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[4]:13 1.802001e-06 +22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[4]:25 0.0002085096 +23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[4]:32 0.000171118 +24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chany_bottom_in[4]:11 0.0003797404 +25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_in[4]:12 1.802001e-06 +26 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_in[4]:24 0.0002085096 +27 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_in[4]:25 0.000171118 +28 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[4]:10 0.0003797404 +29 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 right_top_grid_pin_45_[0]:12 0.0006309195 +30 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_45_[0]:4 5.478355e-07 +31 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_45_[0]:11 0.0006309195 +32 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 right_top_grid_pin_45_[0]:10 5.478355e-07 +33 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.000269753 +34 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001176572 +35 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.889261e-05 +36 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001176572 +37 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.000269753 +38 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.889261e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:18 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:17 0.0001548913 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.009622768 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.00341 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0004280916 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.00341 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.001702183 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0007143999 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.00341 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.00341 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.005004716 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.005544825 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.00341 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.00341 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001521739 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004742363 //LENGTH 3.860 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_1_:X O *L 0 *C 92.285 91.460 +*I mux_right_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 95.855 91.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 95.818 91.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 92.323 91.460 + +*CAP +0 mux_right_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002361182 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002361182 + +*RES +0 mux_right_track_0\/mux_l2_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003120536 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002659783 //LENGTH 21.460 LUMPCC 0.000944396 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_1_:X O *L 0 *C 46.635 33.660 +*I mux_bottom_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 48.015 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 47.977 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 47.425 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 47.380 17.385 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 47.380 28.175 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 47.335 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 45.585 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 45.540 28.265 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 45.540 33.615 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 45.585 33.660 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 46.598 33.660 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.05639e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.05639e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0004079062 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004079062 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001275631 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001275631 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001694849 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001694849 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 8.11752e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 8.11752e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 prog_clk[0]:415 2.306712e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 prog_clk[0]:417 4.665687e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 prog_clk[0]:416 2.306712e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 prog_clk[0]:418 4.665687e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_4_sram[1]:7 0.0001541954 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_4_sram[1]:8 0.0001541954 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size6_4_sram[1]:9 1.543662e-07 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size6_4_sram[1]:10 1.543662e-07 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.975307e-05 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.975307e-05 +22 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001483712 +23 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001483712 + +*RES +0 mux_bottom_track_1\/mux_l2_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004933036 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.009633929 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0015625 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.004776786 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0009040179 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000863297 //LENGTH 6.765 LUMPCC 9.340767e-05 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_1_:X O *L 0 *C 92.635 31.960 +*I mux_bottom_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 93.670 37.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 93.633 37.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 92.965 37.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 92.920 37.015 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 92.920 32.005 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 92.920 31.960 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 92.635 31.960 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.539556e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.539556e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002627613 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002627613 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.663078e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.494491e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_6_sram[1]:11 4.628677e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_6_sram[1]:8 4.170599e-07 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_6_sram[1]:10 4.628677e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size6_6_sram[1]:9 4.170599e-07 + +*RES +0 mux_bottom_track_9\/mux_l2_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0005959822 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473215 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001110567 //LENGTH 9.940 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_0_:X O *L 0 *C 30.995 69.360 +*I mux_top_track_16\/mux_l3_in_0_:A1 I *L 0.005458 *C 24.255 71.818 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 24.290 71.770 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 24.380 71.695 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 24.380 69.405 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 24.425 69.360 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 30.958 69.360 + +*CAP +0 mux_top_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A1 3.424199e-05 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.424199e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001345559 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001345559 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003859855 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003859855 + +*RES +0 mux_top_track_16\/mux_l2_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A1 3.365385e-05 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002044643 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.005832589 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001320069 //LENGTH 8.720 LUMPCC 0.0005370789 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_1_:X O *L 0 *C 60.895 36.040 +*I mux_bottom_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 61.470 28.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 61.470 28.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.180 28.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 61.180 28.265 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 61.180 35.995 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 61.180 36.040 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.895 36.040 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.114443e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.123599e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002761855 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002761855 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.425292e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.198588e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[4]:12 5.750454e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[4]:13 5.750454e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[16]:25 0.000140425 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[16]:26 0.000140425 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_2_sram[1]:6 7.060991e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_2_sram[1]:7 7.060991e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001576087 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008237434 //LENGTH 7.940 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 26.395 80.580 +*I mux_top_track_24\/mux_l3_in_0_:A1 I *L 0.005458 *C 24.715 85.943 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 24.750 85.990 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 24.840 85.975 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 24.840 80.625 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 24.885 80.580 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 26.358 80.580 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A1 3.719782e-05 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.719782e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002723874 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002723874 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001017865 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001017865 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001314732 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.004776786 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A1 3.365385e-05 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0] 0.006341531 //LENGTH 45.265 LUMPCC 0.002348494 DR + +*CONN +*I mux_top_track_32\/mux_l3_in_0_:X O *L 0 *C 55.835 85.680 +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 47.190 120.875 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 47.190 120.875 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 47.380 120.700 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 47.380 120.655 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 47.380 119.738 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 47.388 119.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 52.420 119.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 52.440 119.672 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 52.440 85.688 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 52.460 85.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 55.653 85.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 55.660 85.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 55.660 85.680 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 55.835 85.680 + +*CAP +0 mux_top_track_32\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.896028e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.955675e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.121267e-05 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.121267e-05 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002845612 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002845612 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001315708 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001315708 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001851619 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001851619 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.558636e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 6.278107e-05 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 6.086467e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chany_bottom_in[16]:15 5.589842e-06 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chany_bottom_in[16]:19 0.0003894838 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chany_bottom_in[16]:14 5.589842e-06 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chany_bottom_in[16]:18 0.0003894838 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chany_top_in[15]:8 0.0001521545 +20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chany_top_in[15] 0.0001521545 +21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:15 0.0002162253 +22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:10 0.0002162253 +23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002255345 +24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002255345 +25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001852591 +26 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001852591 + +*RES +0 mux_top_track_32\/mux_l3_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 9.51087e-05 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.00341 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0005001583 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00341 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.005324316 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000788425 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0008191965 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002056914 //LENGTH 17.455 LUMPCC 0.000680847 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 32.945 57.800 +*I mux_right_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 33.680 41.820 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 33.642 41.820 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 33.165 41.820 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 33.120 41.865 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 33.120 57.755 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.120 57.800 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 32.945 57.800 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.994459e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.994459e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0005972763 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0005972763 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.585481e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.377061e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[18]:13 6.659655e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[18]:14 1.729878e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[18]:10 1.729878e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[18]:14 6.659655e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:314 6.330699e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:315 6.330699e-05 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_6_sram[2]:4 3.163587e-05 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_6_sram[2]:5 3.163587e-05 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_6_sram[2]:6 0.0001615853 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_6_sram[2]:7 0.0001615853 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004263393 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0141875 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008142765 //LENGTH 5.870 LUMPCC 0.0001369534 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_1_:X O *L 0 *C 77.455 109.820 +*I mux_right_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 76.075 113.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 76.075 113.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 75.900 113.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 75.900 113.175 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 75.900 109.865 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 75.945 109.820 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 77.418 109.820 + +*CAP +0 mux_right_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.5137e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.961112e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002105727 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002105727 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.971475e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.971475e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_0_sram[1]:6 6.84767e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_0_sram[1]:5 6.84767e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002955357 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000639251 //LENGTH 5.275 LUMPCC 0 DR + +*CONN +*I mux_right_track_6\/mux_l1_in_1_:X O *L 0 *C 66.875 119.000 +*I mux_right_track_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.230 120.700 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 64.267 120.700 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.195 120.700 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 66.240 120.655 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 66.240 119.045 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 66.285 119.000 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 66.838 119.000 + +*CAP +0 mux_right_track_6\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_6\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001409698 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001409698 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001077742 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001077742 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.988152e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.988152e-05 + +*RES +0 mux_right_track_6\/mux_l1_in_1_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_6\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001720982 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0] 0.008395824 //LENGTH 63.250 LUMPCC 0.002208659 DR + +*CONN +*I mux_right_track_6\/mux_l3_in_0_:X O *L 0 *C 62.845 112.880 +*I mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.755 91.310 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 102.718 91.407 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 99.865 91.460 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 99.820 91.505 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 99.820 95.142 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 99.812 95.200 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 82.820 95.200 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 82.800 95.208 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 82.800 112.873 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 82.780 112.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 63.488 112.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 63.480 112.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 63.435 112.880 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 62.883 112.880 + +*CAP +0 mux_right_track_6\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001650498 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001650498 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002183684 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002183684 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009143762 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0009143762 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0007008713 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0007008713 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.00102598 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00102598 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 3.033878e-05 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 5.276826e-05 +14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 5.276826e-05 +15 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chany_bottom_in[4]:13 4.965192e-05 +16 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chany_bottom_in[4]:15 4.016443e-07 +17 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chany_bottom_in[4]:4 4.016443e-07 +18 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chany_bottom_in[4]:14 4.965192e-05 +19 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[4]:24 0.0004492011 +20 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[4]:25 8.505154e-05 +21 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[4]:25 0.0004492011 +22 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[4]:32 8.505154e-05 +23 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 prog_clk[0]:263 6.939541e-06 +24 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 prog_clk[0]:267 1.041836e-05 +25 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 prog_clk[0]:259 6.939541e-06 +26 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 prog_clk[0]:263 1.041836e-05 +27 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:193 7.232142e-05 +28 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:198 3.306823e-05 +29 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:199 0.0001321912 +30 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:189 7.232142e-05 +31 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:193 0.0001321912 +32 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:199 3.306823e-05 +33 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 right_top_grid_pin_47_[0]:20 0.0002383408 +34 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 right_top_grid_pin_47_[0]:21 2.546895e-05 +35 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 right_top_grid_pin_47_[0]:24 1.274738e-06 +36 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 right_top_grid_pin_47_[0] 1.274738e-06 +37 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 right_top_grid_pin_47_[0]:15 2.546895e-05 +38 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 right_top_grid_pin_47_[0]:21 0.0002383408 + +*RES +0 mux_right_track_6\/mux_l3_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0004933036 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.003022492 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.002767517 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002662158 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003247768 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002546875 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_6\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0] 0.009130049 //LENGTH 67.325 LUMPCC 0.0009734053 DR + +*CONN +*I mux_right_track_26\/mux_l2_in_0_:X O *L 0 *C 45.365 64.600 +*I mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.410 71.950 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 103.410 71.987 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 103.500 72.420 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 103.500 72.375 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 103.500 64.645 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 103.455 64.600 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 95.220 64.600 +*N mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 45.403 64.600 + +*CAP +0 mux_right_track_26\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.929398e-05 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.192853e-05 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004517831 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004517831 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005451058 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.003569927 +8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.003024821 +9 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.000436225 +10 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size6_0_sram[1]:8 0.000436225 +11 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.047761e-05 +12 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.047761e-05 + +*RES +0 mux_right_track_26\/mux_l2_in_0_:X mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003861607 +3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.04447991 +7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00735268 + +*END + +*D_NET ropt_net_229 0.0007119911 //LENGTH 6.365 LUMPCC 0.0001141054 DR + +*CONN +*I ropt_mt_inst_824:X O *L 0 *C 41.135 3.400 +*I ropt_mt_inst_849:A I *L 0.001767 *C 39.100 6.800 +*N ropt_net_229:2 *C 39.138 6.800 +*N ropt_net_229:3 *C 39.975 6.800 +*N ropt_net_229:4 *C 40.020 6.755 +*N ropt_net_229:5 *C 40.020 3.445 +*N ropt_net_229:6 *C 40.065 3.400 +*N ropt_net_229:7 *C 41.098 3.400 + +*CAP +0 ropt_mt_inst_824:X 1e-06 +1 ropt_mt_inst_849:A 1e-06 +2 ropt_net_229:2 6.933705e-05 +3 ropt_net_229:3 6.933705e-05 +4 ropt_net_229:4 0.000147102 +5 ropt_net_229:5 0.000147102 +6 ropt_net_229:6 8.150376e-05 +7 ropt_net_229:7 8.150376e-05 +8 ropt_net_229:4 ropt_net_203:5 4.166249e-05 +9 ropt_net_229:6 ropt_net_203:2 1.539021e-05 +10 ropt_net_229:5 ropt_net_203:4 4.166249e-05 +11 ropt_net_229:7 ropt_net_203:3 1.539021e-05 + +*RES +0 ropt_mt_inst_824:X ropt_net_229:7 0.152 +1 ropt_net_229:2 ropt_mt_inst_849:A 0.152 +2 ropt_net_229:3 ropt_net_229:2 0.0007477679 +3 ropt_net_229:4 ropt_net_229:3 0.0045 +4 ropt_net_229:6 ropt_net_229:5 0.0045 +5 ropt_net_229:5 ropt_net_229:4 0.002955357 +6 ropt_net_229:7 ropt_net_229:6 0.000921875 + +*END + +*D_NET chany_bottom_out[17] 0.00088113 //LENGTH 5.980 LUMPCC 0.0001677706 DR + +*CONN +*I ropt_mt_inst_839:X O *L 0 *C 50.335 3.740 +*P chany_bottom_out[17] O *L 0.7423 *C 47.380 1.290 +*N chany_bottom_out[17]:2 *C 47.380 3.355 +*N chany_bottom_out[17]:3 *C 47.380 3.400 +*N chany_bottom_out[17]:4 *C 47.380 3.740 +*N chany_bottom_out[17]:5 *C 50.297 3.740 + +*CAP +0 ropt_mt_inst_839:X 1e-06 +1 chany_bottom_out[17] 0.0001510579 +2 chany_bottom_out[17]:2 0.0001510579 +3 chany_bottom_out[17]:3 6.877081e-05 +4 chany_bottom_out[17]:4 0.0001864659 +5 chany_bottom_out[17]:5 0.0001550069 +6 chany_bottom_out[17]:5 ropt_net_215:2 8.388528e-05 +7 chany_bottom_out[17]:4 ropt_net_215:3 8.388528e-05 + +*RES +0 ropt_mt_inst_839:X chany_bottom_out[17]:5 0.152 +1 chany_bottom_out[17]:5 chany_bottom_out[17]:4 0.002604911 +2 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0045 +3 chany_bottom_out[17]:2 chany_bottom_out[17] 0.00184375 +4 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.0003035715 + +*END + +*D_NET chany_bottom_out[5] 0.0009626417 //LENGTH 7.005 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_842:X O *L 0 *C 44.620 6.120 +*P chany_bottom_out[5] O *L 0.7423 *C 45.540 1.290 +*N chany_bottom_out[5]:2 *C 45.540 6.415 +*N chany_bottom_out[5]:3 *C 45.540 6.460 +*N chany_bottom_out[5]:4 *C 45.540 6.120 +*N chany_bottom_out[5]:5 *C 44.657 6.120 + +*CAP +0 ropt_mt_inst_842:X 1e-06 +1 chany_bottom_out[5] 0.0003506985 +2 chany_bottom_out[5]:2 0.0003506985 +3 chany_bottom_out[5]:3 7.128442e-05 +4 chany_bottom_out[5]:4 0.0001107 +5 chany_bottom_out[5]:5 7.826024e-05 + +*RES +0 ropt_mt_inst_842:X chany_bottom_out[5]:5 0.152 +1 chany_bottom_out[5]:5 chany_bottom_out[5]:4 0.0007879464 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +3 chany_bottom_out[5]:2 chany_bottom_out[5] 0.004575893 +4 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.0003035715 + +*END + +*D_NET chany_bottom_out[10] 0.001137556 //LENGTH 9.255 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_849:X O *L 0 *C 40.020 6.120 +*P chany_bottom_out[10] O *L 0.7423 *C 42.780 1.290 +*N chany_bottom_out[10]:2 *C 42.780 2.040 +*N chany_bottom_out[10]:3 *C 43.240 2.040 +*N chany_bottom_out[10]:4 *C 43.240 6.075 +*N chany_bottom_out[10]:5 *C 43.195 6.120 +*N chany_bottom_out[10]:6 *C 40.058 6.120 + +*CAP +0 ropt_mt_inst_849:X 1e-06 +1 chany_bottom_out[10] 5.237184e-05 +2 chany_bottom_out[10]:2 8.086527e-05 +3 chany_bottom_out[10]:3 0.000285347 +4 chany_bottom_out[10]:4 0.0002568536 +5 chany_bottom_out[10]:5 0.0002305593 +6 chany_bottom_out[10]:6 0.0002305593 + +*RES +0 ropt_mt_inst_849:X chany_bottom_out[10]:6 0.152 +1 chany_bottom_out[10]:6 chany_bottom_out[10]:5 0.002801339 +2 chany_bottom_out[10]:5 chany_bottom_out[10]:4 0.0045 +3 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.003602678 +4 chany_bottom_out[10]:2 chany_bottom_out[10] 0.0006696429 +5 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0004107143 + +*END + +*D_NET ropt_net_214 0.001924669 //LENGTH 16.810 LUMPCC 0.0005239284 DR + +*CONN +*I BUFT_RR_76:X O *L 0 *C 70.840 14.620 +*I ropt_mt_inst_835:A I *L 0.001766 *C 74.980 4.080 +*N ropt_net_214:2 *C 74.943 4.080 +*N ropt_net_214:3 *C 70.885 4.080 +*N ropt_net_214:4 *C 70.840 4.125 +*N ropt_net_214:5 *C 70.840 6.120 +*N ropt_net_214:6 *C 70.380 6.120 +*N ropt_net_214:7 *C 70.380 14.575 +*N ropt_net_214:8 *C 70.425 14.620 +*N ropt_net_214:9 *C 70.803 14.620 + +*CAP +0 BUFT_RR_76:X 1e-06 +1 ropt_mt_inst_835:A 1e-06 +2 ropt_net_214:2 0.0001883531 +3 ropt_net_214:3 0.0001883531 +4 ropt_net_214:4 0.0001214179 +5 ropt_net_214:5 0.0001429179 +6 ropt_net_214:6 0.0003447954 +7 ropt_net_214:7 0.0003232954 +8 ropt_net_214:8 4.480387e-05 +9 ropt_net_214:9 4.480387e-05 +10 ropt_net_214:4 chany_bottom_out[8] 4.300487e-06 +11 ropt_net_214:7 chany_bottom_out[8]:2 0.0001123298 +12 ropt_net_214:6 chany_bottom_out[8] 0.0001123298 +13 ropt_net_214:5 chany_bottom_out[8]:2 4.300487e-06 +14 ropt_net_214:7 ropt_net_240:5 5.453866e-05 +15 ropt_net_214:6 ropt_net_240:4 5.453866e-05 +16 ropt_net_214:6 ropt_net_240:7 6.744983e-06 +17 ropt_net_214:5 ropt_net_240:6 6.744983e-06 +18 ropt_net_214:2 ropt_net_224:4 7.396415e-05 +19 ropt_net_214:3 ropt_net_224:3 7.396415e-05 +20 ropt_net_214:4 ropt_net_224:3 1.008611e-05 +21 ropt_net_214:5 ropt_net_224:2 1.008611e-05 + +*RES +0 BUFT_RR_76:X ropt_net_214:9 0.152 +1 ropt_net_214:2 ropt_mt_inst_835:A 0.152 +2 ropt_net_214:3 ropt_net_214:2 0.003622768 +3 ropt_net_214:4 ropt_net_214:3 0.0045 +4 ropt_net_214:8 ropt_net_214:7 0.0045 +5 ropt_net_214:7 ropt_net_214:6 0.007549107 +6 ropt_net_214:9 ropt_net_214:8 0.0003370536 +7 ropt_net_214:6 ropt_net_214:5 0.0004107143 +8 ropt_net_214:5 ropt_net_214:4 0.00178125 + +*END + +*D_NET chany_top_in[17] 0.0269093 //LENGTH 235.355 LUMPCC 0.00437418 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 14.720 129.350 +*I ropt_mt_inst_823:A I *L 0.001767 *C 23.000 4.080 +*I mux_bottom_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 67.335 44.200 +*I mux_right_track_22\/mux_l1_in_0_:A1 I *L 0.00198 *C 63.940 79.900 +*N chany_top_in[17]:4 *C 63.940 79.900 +*N chany_top_in[17]:5 *C 63.940 79.855 +*N chany_top_in[17]:6 *C 63.940 78.200 +*N chany_top_in[17]:7 *C 63.480 78.200 +*N chany_top_in[17]:8 *C 63.473 78.200 +*N chany_top_in[17]:9 *C 15.660 78.200 +*N chany_top_in[17]:10 *C 15.640 78.193 +*N chany_top_in[17]:11 *C 67.335 44.200 +*N chany_top_in[17]:12 *C 67.160 44.200 +*N chany_top_in[17]:13 *C 67.160 44.200 +*N chany_top_in[17]:14 *C 67.153 44.200 +*N chany_top_in[17]:15 *C 23.038 4.080 +*N chany_top_in[17]:16 *C 23.875 4.080 +*N chany_top_in[17]:17 *C 23.920 4.125 +*N chany_top_in[17]:18 *C 23.920 28.503 +*N chany_top_in[17]:19 *C 23.928 28.560 +*N chany_top_in[17]:20 *C 25.740 28.560 +*N chany_top_in[17]:21 *C 25.760 28.568 +*N chany_top_in[17]:22 *C 25.760 44.193 +*N chany_top_in[17]:23 *C 25.760 44.200 +*N chany_top_in[17]:24 *C 25.760 44.880 +*N chany_top_in[17]:25 *C 15.660 44.880 +*N chany_top_in[17]:26 *C 15.640 44.888 +*N chany_top_in[17]:27 *C 15.640 77.520 +*N chany_top_in[17]:28 *C 14.720 77.520 + +*CAP +0 chany_top_in[17] 0.002286219 +1 ropt_mt_inst_823:A 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_22\/mux_l1_in_0_:A1 1e-06 +4 chany_top_in[17]:4 3.263562e-05 +5 chany_top_in[17]:5 0.0001055733 +6 chany_top_in[17]:6 0.0001410335 +7 chany_top_in[17]:7 7.303837e-05 +8 chany_top_in[17]:8 0.002197676 +9 chany_top_in[17]:9 0.002197676 +10 chany_top_in[17]:10 5.43718e-05 +11 chany_top_in[17]:11 5.909114e-05 +12 chany_top_in[17]:12 6.051999e-05 +13 chany_top_in[17]:13 3.528633e-05 +14 chany_top_in[17]:14 0.00244911 +15 chany_top_in[17]:15 6.946528e-05 +16 chany_top_in[17]:16 6.946528e-05 +17 chany_top_in[17]:17 0.0009107526 +18 chany_top_in[17]:18 0.0009107526 +19 chany_top_in[17]:19 0.0001184623 +20 chany_top_in[17]:20 0.0001184623 +21 chany_top_in[17]:21 0.0008119527 +22 chany_top_in[17]:22 0.0008119527 +23 chany_top_in[17]:23 0.002501273 +24 chany_top_in[17]:24 0.0005913518 +25 chany_top_in[17]:25 0.0005391893 +26 chany_top_in[17]:26 0.001473231 +27 chany_top_in[17]:27 0.001577481 +28 chany_top_in[17]:28 0.002336097 +29 chany_top_in[17] chany_top_in[13] 0.000344399 +30 chany_top_in[17]:23 chany_top_in[13]:17 1.222661e-05 +31 chany_top_in[17]:23 chany_top_in[13]:23 6.872403e-06 +32 chany_top_in[17]:14 chany_top_in[13]:18 1.222661e-05 +33 chany_top_in[17]:14 chany_top_in[13]:24 6.872403e-06 +34 chany_top_in[17]:9 chany_top_in[13]:35 0.0004661058 +35 chany_top_in[17]:8 chany_top_in[13]:34 0.0004661058 +36 chany_top_in[17]:28 chany_top_in[13]:36 0.000344399 +37 chany_top_in[17]:23 prog_clk[0]:162 1.860426e-06 +38 chany_top_in[17]:23 prog_clk[0]:451 0.0001338073 +39 chany_top_in[17]:23 prog_clk[0]:457 3.624849e-05 +40 chany_top_in[17]:23 prog_clk[0]:450 9.523665e-05 +41 chany_top_in[17]:23 prog_clk[0]:446 3.004925e-05 +42 chany_top_in[17]:14 prog_clk[0]:161 1.860426e-06 +43 chany_top_in[17]:14 prog_clk[0]:442 3.004925e-05 +44 chany_top_in[17]:14 prog_clk[0]:456 3.624849e-05 +45 chany_top_in[17]:14 prog_clk[0]:450 0.0001338073 +46 chany_top_in[17]:14 prog_clk[0]:446 9.523665e-05 +47 chany_top_in[17]:9 prog_clk[0]:292 1.980234e-05 +48 chany_top_in[17]:7 prog_clk[0]:175 1.577791e-07 +49 chany_top_in[17]:8 prog_clk[0]:291 1.980234e-05 +50 chany_top_in[17]:5 prog_clk[0]:234 1.213292e-06 +51 chany_top_in[17]:25 prog_clk[0]:465 7.233835e-06 +52 chany_top_in[17]:6 prog_clk[0]:241 1.577791e-07 +53 chany_top_in[17]:6 prog_clk[0]:237 1.213292e-06 +54 chany_top_in[17]:24 prog_clk[0]:464 7.233835e-06 +55 chany_top_in[17]:9 chanx_right_in[6]:13 0.0004699545 +56 chany_top_in[17]:8 chanx_right_in[6]:14 0.0004699545 +57 chany_top_in[17]:18 chany_bottom_in[19]:4 0.000344584 +58 chany_top_in[17]:17 chany_bottom_in[19] 0.000344584 +59 chany_top_in[17]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000217338 +60 chany_top_in[17]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000217338 + +*RES +0 chany_top_in[17] chany_top_in[17]:28 0.008120032 +1 chany_top_in[17]:23 chany_top_in[17]:22 0.00341 +2 chany_top_in[17]:23 chany_top_in[17]:14 0.006484824 +3 chany_top_in[17]:22 chany_top_in[17]:21 0.002447917 +4 chany_top_in[17]:20 chany_top_in[17]:19 0.0002839583 +5 chany_top_in[17]:21 chany_top_in[17]:20 0.00341 +6 chany_top_in[17]:18 chany_top_in[17]:17 0.02176563 +7 chany_top_in[17]:19 chany_top_in[17]:18 0.00341 +8 chany_top_in[17]:16 chany_top_in[17]:15 0.0007477679 +9 chany_top_in[17]:17 chany_top_in[17]:16 0.0045 +10 chany_top_in[17]:15 ropt_mt_inst_823:A 0.152 +11 chany_top_in[17]:13 chany_top_in[17]:12 0.0045 +12 chany_top_in[17]:14 chany_top_in[17]:13 0.00341 +13 chany_top_in[17]:12 chany_top_in[17]:11 9.51087e-05 +14 chany_top_in[17]:11 mux_bottom_track_17\/mux_l1_in_0_:A0 0.152 +15 chany_top_in[17]:9 chany_top_in[17]:8 0.007490624 +16 chany_top_in[17]:10 chany_top_in[17]:9 0.00341 +17 chany_top_in[17]:7 chany_top_in[17]:6 0.0004107143 +18 chany_top_in[17]:8 chany_top_in[17]:7 0.00341 +19 chany_top_in[17]:4 mux_right_track_22\/mux_l1_in_0_:A1 0.152 +20 chany_top_in[17]:5 chany_top_in[17]:4 0.0045 +21 chany_top_in[17]:25 chany_top_in[17]:24 0.001582333 +22 chany_top_in[17]:26 chany_top_in[17]:25 0.00341 +23 chany_top_in[17]:6 chany_top_in[17]:5 0.001477679 +24 chany_top_in[17]:24 chany_top_in[17]:23 0.0001065333 +25 chany_top_in[17]:28 chany_top_in[17]:27 0.0001441333 +26 chany_top_in[17]:27 chany_top_in[17]:26 0.005112424 +27 chany_top_in[17]:27 chany_top_in[17]:10 0.0001053583 + +*END + +*D_NET chany_bottom_in[17] 0.01749429 //LENGTH 154.340 LUMPCC 0.003359041 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 29.900 1.290 +*I mux_top_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 28.060 72.420 +*I mux_right_track_22\/mux_l1_in_1_:A1 I *L 0.00198 *C 52.080 79.900 +*I ropt_mt_inst_810:A I *L 0.001767 *C 49.680 126.480 +*N chany_bottom_in[17]:4 *C 49.680 126.480 +*N chany_bottom_in[17]:5 *C 49.680 126.435 +*N chany_bottom_in[17]:6 *C 49.680 101.705 +*N chany_bottom_in[17]:7 *C 49.635 101.660 +*N chany_bottom_in[17]:8 *C 46.965 101.660 +*N chany_bottom_in[17]:9 *C 46.920 101.615 +*N chany_bottom_in[17]:10 *C 52.043 79.900 +*N chany_bottom_in[17]:11 *C 46.965 79.900 +*N chany_bottom_in[17]:12 *C 46.920 79.900 +*N chany_bottom_in[17]:13 *C 46.920 75.525 +*N chany_bottom_in[17]:14 *C 46.875 75.480 +*N chany_bottom_in[17]:15 *C 31.325 75.480 +*N chany_bottom_in[17]:16 *C 31.280 75.435 +*N chany_bottom_in[17]:17 *C 31.280 72.465 +*N chany_bottom_in[17]:18 *C 31.235 72.420 +*N chany_bottom_in[17]:19 *C 28.098 72.420 +*N chany_bottom_in[17]:20 *C 29.900 72.420 +*N chany_bottom_in[17]:21 *C 29.900 72.375 +*N chany_bottom_in[17]:22 *C 29.900 51.290 + +*CAP +0 chany_bottom_in[17] 0.002207788 +1 mux_top_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_22\/mux_l1_in_1_:A1 1e-06 +3 ropt_mt_inst_810:A 1e-06 +4 chany_bottom_in[17]:4 3.326635e-05 +5 chany_bottom_in[17]:5 0.00105933 +6 chany_bottom_in[17]:6 0.00105933 +7 chany_bottom_in[17]:7 0.0001699553 +8 chany_bottom_in[17]:8 0.0001699553 +9 chany_bottom_in[17]:9 0.0009264573 +10 chany_bottom_in[17]:10 0.0003088313 +11 chany_bottom_in[17]:11 0.0003088313 +12 chany_bottom_in[17]:12 0.001149373 +13 chany_bottom_in[17]:13 0.0001913941 +14 chany_bottom_in[17]:14 0.000836614 +15 chany_bottom_in[17]:15 0.0008366141 +16 chany_bottom_in[17]:16 0.0001476553 +17 chany_bottom_in[17]:17 0.0001476553 +18 chany_bottom_in[17]:18 7.591502e-05 +19 chany_bottom_in[17]:19 9.459195e-05 +20 chany_bottom_in[17]:20 0.0002026158 +21 chany_bottom_in[17]:21 0.0009991423 +22 chany_bottom_in[17]:22 0.00320693 +23 chany_bottom_in[17]:9 chany_top_in[10]:13 7.258859e-05 +24 chany_bottom_in[17]:9 chany_top_in[10]:14 0.0001689931 +25 chany_bottom_in[17]:6 chany_top_in[10]:18 0.0006506158 +26 chany_bottom_in[17]:5 chany_top_in[10] 0.0006506158 +27 chany_bottom_in[17]:12 chany_top_in[10]:12 7.258859e-05 +28 chany_bottom_in[17]:12 chany_top_in[10]:13 0.0002244649 +29 chany_bottom_in[17]:13 chany_top_in[10]:12 5.54718e-05 +30 chany_bottom_in[17] chany_bottom_in[11] 0.0003764981 +31 chany_bottom_in[17]:22 chany_bottom_in[11]:19 0.0003764981 +32 chany_bottom_in[17]:20 optlc_net_184:14 3.325636e-05 +33 chany_bottom_in[17]:20 optlc_net_184:13 2.468403e-05 +34 chany_bottom_in[17]:21 optlc_net_184:16 6.961201e-07 +35 chany_bottom_in[17]:19 optlc_net_184:13 3.325636e-05 +36 chany_bottom_in[17]:11 optlc_net_184:28 1.64812e-05 +37 chany_bottom_in[17]:10 optlc_net_184:27 1.64812e-05 +38 chany_bottom_in[17]:14 optlc_net_184:18 0.0001682247 +39 chany_bottom_in[17]:14 optlc_net_184:12 1.794396e-05 +40 chany_bottom_in[17]:15 optlc_net_184:19 1.794396e-05 +41 chany_bottom_in[17]:15 optlc_net_184:17 0.0001682247 +42 chany_bottom_in[17]:16 optlc_net_184:16 2.995227e-05 +43 chany_bottom_in[17]:18 optlc_net_184:14 2.468403e-05 +44 chany_bottom_in[17]:17 optlc_net_184:15 2.995227e-05 +45 chany_bottom_in[17]:22 optlc_net_184:15 6.961201e-07 +46 chany_bottom_in[17]:21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.411436e-05 +47 chany_bottom_in[17]:22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.411436e-05 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:22 0.04464286 +1 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.002383929 +2 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.0045 +3 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.0045 +4 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.02208036 +5 chany_bottom_in[17]:4 ropt_mt_inst_810:A 0.152 +6 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.0045 +7 chany_bottom_in[17]:20 chany_bottom_in[17]:19 0.001609375 +8 chany_bottom_in[17]:20 chany_bottom_in[17]:18 0.001191964 +9 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.0045 +10 chany_bottom_in[17]:19 mux_top_track_16\/mux_l2_in_1_:A1 0.152 +11 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.004533482 +12 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.0045 +13 chany_bottom_in[17]:12 chany_bottom_in[17]:9 0.01938839 +14 chany_bottom_in[17]:10 mux_right_track_22\/mux_l1_in_1_:A1 0.152 +15 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.0045 +16 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.00390625 +17 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.01388393 +18 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.0045 +19 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.0045 +20 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.002651786 +21 chany_bottom_in[17]:22 chany_bottom_in[17]:21 0.01882589 + +*END + +*D_NET chany_top_in[0] 0.0008763266 //LENGTH 6.735 LUMPCC 0 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 67.620 129.270 +*I mux_right_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 70.480 126.820 +*N chany_top_in[0]:2 *C 70.443 126.820 +*N chany_top_in[0]:3 *C 69.920 126.820 +*N chany_top_in[0]:4 *C 69.920 126.480 +*N chany_top_in[0]:5 *C 67.665 126.480 +*N chany_top_in[0]:6 *C 67.620 126.525 + +*CAP +0 chany_top_in[0] 0.0001570245 +1 mux_right_track_2\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[0]:2 6.101289e-05 +3 chany_top_in[0]:3 8.709742e-05 +4 chany_top_in[0]:4 0.0002196259 +5 chany_top_in[0]:5 0.0001935414 +6 chany_top_in[0]:6 0.0001570245 + +*RES +0 chany_top_in[0] chany_top_in[0]:6 0.002450893 +1 chany_top_in[0]:2 mux_right_track_2\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[0]:5 chany_top_in[0]:4 0.002013393 +3 chany_top_in[0]:6 chany_top_in[0]:5 0.0045 +4 chany_top_in[0]:4 chany_top_in[0]:3 0.0003035715 +5 chany_top_in[0]:3 chany_top_in[0]:2 0.0004665179 + +*END + +*D_NET chany_top_in[3] 0.002928784 //LENGTH 23.150 LUMPCC 0.000444642 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 45.540 129.270 +*I mux_right_track_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 62.375 123.420 +*N chany_top_in[3]:2 *C 62.338 123.420 +*N chany_top_in[3]:3 *C 45.585 123.420 +*N chany_top_in[3]:4 *C 45.540 123.465 + +*CAP +0 chany_top_in[3] 0.0003404551 +1 mux_right_track_6\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[3]:2 0.0009011158 +3 chany_top_in[3]:3 0.0009011158 +4 chany_top_in[3]:4 0.0003404551 +5 chany_top_in[3]:2 ropt_net_234:2 2.996061e-05 +6 chany_top_in[3]:3 ropt_net_234:3 2.996061e-05 +7 chany_top_in[3]:2 ropt_net_216:2 8.147868e-05 +8 chany_top_in[3]:3 ropt_net_216:3 8.147868e-05 +9 chany_top_in[3]:2 ropt_net_225:5 7.209439e-05 +10 chany_top_in[3]:2 ropt_net_225:3 3.878732e-05 +11 chany_top_in[3]:3 ropt_net_225:2 3.878732e-05 +12 chany_top_in[3]:3 ropt_net_225:4 7.209439e-05 + +*RES +0 chany_top_in[3] chany_top_in[3]:4 0.005183036 +1 chany_top_in[3]:2 mux_right_track_6\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[3]:3 chany_top_in[3]:2 0.01495759 +3 chany_top_in[3]:4 chany_top_in[3]:3 0.0045 + +*END + +*D_NET chany_top_in[11] 0.003462645 //LENGTH 32.000 LUMPCC 0 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 41.860 129.270 +*I mux_right_track_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 40.655 98.940 +*N chany_top_in[11]:2 *C 40.693 98.940 +*N chany_top_in[11]:3 *C 41.815 98.940 +*N chany_top_in[11]:4 *C 41.860 98.985 + +*CAP +0 chany_top_in[11] 0.001637246 +1 mux_right_track_10\/mux_l1_in_0_:A0 1e-06 +2 chany_top_in[11]:2 9.357623e-05 +3 chany_top_in[11]:3 9.357623e-05 +4 chany_top_in[11]:4 0.001637246 + +*RES +0 chany_top_in[11] chany_top_in[11]:4 0.02704018 +1 chany_top_in[11]:2 mux_right_track_10\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[11]:3 chany_top_in[11]:2 0.001002232 +3 chany_top_in[11]:4 chany_top_in[11]:3 0.0045 + +*END + +*D_NET chanx_right_in[0] 0.01021905 //LENGTH 78.165 LUMPCC 0.001750698 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 111.930 48.960 +*I mux_bottom_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 60.820 58.140 +*I mux_top_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 60.260 72.420 +*N chanx_right_in[0]:3 *C 60.260 72.420 +*N chanx_right_in[0]:4 *C 60.260 72.375 +*N chanx_right_in[0]:5 *C 60.260 69.360 +*N chanx_right_in[0]:6 *C 59.800 69.360 +*N chanx_right_in[0]:7 *C 60.783 58.140 +*N chanx_right_in[0]:8 *C 59.845 58.140 +*N chanx_right_in[0]:9 *C 59.800 58.140 +*N chanx_right_in[0]:10 *C 59.800 49.018 +*N chanx_right_in[0]:11 *C 59.808 48.960 + +*CAP +0 chanx_right_in[0] 0.002786378 +1 mux_bottom_track_25\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_0_:A1 1e-06 +3 chanx_right_in[0]:3 3.166279e-05 +4 chanx_right_in[0]:4 0.0001931559 +5 chanx_right_in[0]:5 0.0002244848 +6 chanx_right_in[0]:6 0.0005599965 +7 chanx_right_in[0]:7 9.998046e-05 +8 chanx_right_in[0]:8 9.998046e-05 +9 chanx_right_in[0]:9 0.001122343 +10 chanx_right_in[0]:10 0.0005619967 +11 chanx_right_in[0]:11 0.002786378 +12 chanx_right_in[0] prog_clk[0]:138 4.874066e-07 +13 chanx_right_in[0] prog_clk[0]:142 6.055593e-05 +14 chanx_right_in[0] prog_clk[0]:146 9.440506e-05 +15 chanx_right_in[0] prog_clk[0]:161 0.0001476967 +16 chanx_right_in[0] prog_clk[0]:168 6.572648e-06 +17 chanx_right_in[0]:11 prog_clk[0]:139 4.874066e-07 +18 chanx_right_in[0]:11 prog_clk[0]:146 6.055593e-05 +19 chanx_right_in[0]:11 prog_clk[0]:161 9.440506e-05 +20 chanx_right_in[0]:11 prog_clk[0]:162 0.0001476967 +21 chanx_right_in[0]:11 prog_clk[0]:169 6.572648e-06 +22 chanx_right_in[0] chanx_right_in[15]:11 0.00026322 +23 chanx_right_in[0]:11 chanx_right_in[15]:10 0.00026322 +24 chanx_right_in[0]:9 mux_tree_tapbuf_size6_2_sram[2]:9 6.943575e-05 +25 chanx_right_in[0]:9 mux_tree_tapbuf_size6_2_sram[2]:8 5.745611e-05 +26 chanx_right_in[0]:6 mux_tree_tapbuf_size6_2_sram[2]:5 5.745611e-05 +27 chanx_right_in[0]:6 mux_tree_tapbuf_size6_2_sram[2]:8 6.943575e-05 +28 chanx_right_in[0] ropt_net_239:7 0.0001755193 +29 chanx_right_in[0]:11 ropt_net_239:6 0.0001755193 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:11 0.008165858 +1 chanx_right_in[0]:3 mux_top_track_32\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0045 +3 chanx_right_in[0]:8 chanx_right_in[0]:7 0.0008370536 +4 chanx_right_in[0]:9 chanx_right_in[0]:8 0.0045 +5 chanx_right_in[0]:9 chanx_right_in[0]:6 0.01001786 +6 chanx_right_in[0]:7 mux_bottom_track_25\/mux_l1_in_1_:A1 0.152 +7 chanx_right_in[0]:10 chanx_right_in[0]:9 0.00814509 +8 chanx_right_in[0]:11 chanx_right_in[0]:10 0.00341 +9 chanx_right_in[0]:6 chanx_right_in[0]:5 0.0004107143 +10 chanx_right_in[0]:5 chanx_right_in[0]:4 0.002691964 + +*END + +*D_NET chanx_right_in[4] 0.0122031 //LENGTH 97.740 LUMPCC 0.002920919 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 111.930 93.840 +*I mux_bottom_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 71.665 45.220 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.510 60.860 +*N chanx_right_in[4]:3 *C 72.510 60.860 +*N chanx_right_in[4]:4 *C 72.680 60.860 +*N chanx_right_in[4]:5 *C 72.680 60.860 +*N chanx_right_in[4]:6 *C 72.680 60.520 +*N chanx_right_in[4]:7 *C 72.688 60.520 +*N chanx_right_in[4]:8 *C 71.703 45.220 +*N chanx_right_in[4]:9 *C 72.220 45.220 +*N chanx_right_in[4]:10 *C 72.220 45.560 +*N chanx_right_in[4]:11 *C 79.075 45.560 +*N chanx_right_in[4]:12 *C 79.120 45.605 +*N chanx_right_in[4]:13 *C 79.120 60.463 +*N chanx_right_in[4]:14 *C 79.120 60.520 +*N chanx_right_in[4]:15 *C 98.420 60.520 +*N chanx_right_in[4]:16 *C 98.440 60.528 +*N chanx_right_in[4]:17 *C 98.440 93.833 +*N chanx_right_in[4]:18 *C 98.460 93.840 + +*CAP +0 chanx_right_in[4] 0.0006774708 +1 mux_bottom_track_3\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[4]:3 6.74149e-05 +4 chanx_right_in[4]:4 6.903609e-05 +5 chanx_right_in[4]:5 5.043492e-05 +6 chanx_right_in[4]:6 5.475316e-05 +7 chanx_right_in[4]:7 0.0004146256 +8 chanx_right_in[4]:8 3.055355e-05 +9 chanx_right_in[4]:9 5.583461e-05 +10 chanx_right_in[4]:10 0.0004480628 +11 chanx_right_in[4]:11 0.0004227817 +12 chanx_right_in[4]:12 0.0008799852 +13 chanx_right_in[4]:13 0.0008799852 +14 chanx_right_in[4]:14 0.001365092 +15 chanx_right_in[4]:15 0.0009504668 +16 chanx_right_in[4]:16 0.001118108 +17 chanx_right_in[4]:17 0.001118108 +18 chanx_right_in[4]:18 0.0006774708 +19 chanx_right_in[4]:6 prog_clk[0]:123 8.015794e-06 +20 chanx_right_in[4]:7 prog_clk[0]:119 3.597101e-05 +21 chanx_right_in[4]:7 prog_clk[0]:124 9.14933e-05 +22 chanx_right_in[4]:5 prog_clk[0]:122 8.015794e-06 +23 chanx_right_in[4]:15 prog_clk[0]:86 9.267002e-05 +24 chanx_right_in[4]:15 prog_clk[0]:101 0.0001129805 +25 chanx_right_in[4]:15 prog_clk[0]:109 7.460775e-05 +26 chanx_right_in[4]:15 prog_clk[0]:114 5.412209e-05 +27 chanx_right_in[4]:13 prog_clk[0]:118 1.867215e-06 +28 chanx_right_in[4]:13 prog_clk[0]:141 1.968632e-06 +29 chanx_right_in[4]:14 prog_clk[0]:101 9.267002e-05 +30 chanx_right_in[4]:14 prog_clk[0]:109 0.0001129805 +31 chanx_right_in[4]:14 prog_clk[0]:114 0.0001105788 +32 chanx_right_in[4]:14 prog_clk[0]:119 0.0001456154 +33 chanx_right_in[4]:12 prog_clk[0]:117 1.867215e-06 +34 chanx_right_in[4]:12 prog_clk[0]:140 1.968632e-06 +35 chanx_right_in[4] chanx_right_in[5] 0.000100748 +36 chanx_right_in[4] chanx_right_in[5]:16 6.428534e-05 +37 chanx_right_in[4]:16 chanx_right_in[5]:13 0.0003681426 +38 chanx_right_in[4]:18 chanx_right_in[5]:15 6.428534e-05 +39 chanx_right_in[4]:18 chanx_right_in[5]:17 0.000100748 +40 chanx_right_in[4]:17 chanx_right_in[5]:14 0.0003681426 +41 chanx_right_in[4] chanx_right_in[12] 1.349008e-05 +42 chanx_right_in[4]:16 chanx_right_in[12]:12 0.0003180384 +43 chanx_right_in[4]:18 chanx_right_in[12]:14 1.349008e-05 +44 chanx_right_in[4]:17 chanx_right_in[12]:13 0.0003180384 +45 chanx_right_in[4]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.768427e-05 +46 chanx_right_in[4]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.678036e-06 +47 chanx_right_in[4]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.792274e-05 +48 chanx_right_in[4]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.869652e-05 +49 chanx_right_in[4]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.678036e-06 +50 chanx_right_in[4]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.845804e-05 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:18 0.0021103 +1 chanx_right_in[4]:6 chanx_right_in[4]:5 0.0001634615 +2 chanx_right_in[4]:7 chanx_right_in[4]:6 0.00341 +3 chanx_right_in[4]:4 chanx_right_in[4]:3 9.239131e-05 +4 chanx_right_in[4]:5 chanx_right_in[4]:4 0.0045 +5 chanx_right_in[4]:3 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +6 chanx_right_in[4]:15 chanx_right_in[4]:14 0.003023666 +7 chanx_right_in[4]:16 chanx_right_in[4]:15 0.00341 +8 chanx_right_in[4]:18 chanx_right_in[4]:17 0.00341 +9 chanx_right_in[4]:17 chanx_right_in[4]:16 0.005217783 +10 chanx_right_in[4]:13 chanx_right_in[4]:12 0.01326562 +11 chanx_right_in[4]:14 chanx_right_in[4]:13 0.00341 +12 chanx_right_in[4]:14 chanx_right_in[4]:7 0.001007758 +13 chanx_right_in[4]:11 chanx_right_in[4]:10 0.006120536 +14 chanx_right_in[4]:12 chanx_right_in[4]:11 0.0045 +15 chanx_right_in[4]:8 mux_bottom_track_3\/mux_l1_in_1_:A1 0.152 +16 chanx_right_in[4]:9 chanx_right_in[4]:8 0.0004620536 +17 chanx_right_in[4]:10 chanx_right_in[4]:9 0.0003035715 + +*END + +*D_NET chanx_right_in[9] 0.002684247 //LENGTH 20.820 LUMPCC 0 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 111.930 51.000 +*I mux_bottom_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 101.490 44.540 +*I mux_top_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 101.030 53.380 +*N chanx_right_in[9]:3 *C 101.068 53.380 +*N chanx_right_in[9]:4 *C 101.615 53.380 +*N chanx_right_in[9]:5 *C 101.660 53.335 +*N chanx_right_in[9]:6 *C 101.490 44.540 +*N chanx_right_in[9]:7 *C 101.660 44.540 +*N chanx_right_in[9]:8 *C 101.660 44.585 +*N chanx_right_in[9]:9 *C 101.660 51.000 +*N chanx_right_in[9]:10 *C 101.668 51.000 + +*CAP +0 chanx_right_in[9] 0.0006941121 +1 mux_bottom_track_9\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_2\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[9]:3 5.486323e-05 +4 chanx_right_in[9]:4 5.486323e-05 +5 chanx_right_in[9]:5 0.00014879 +6 chanx_right_in[9]:6 5.125884e-05 +7 chanx_right_in[9]:7 5.299795e-05 +8 chanx_right_in[9]:8 0.0003766376 +9 chanx_right_in[9]:9 0.0005546121 +10 chanx_right_in[9]:10 0.0006941121 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:10 0.001607792 +1 chanx_right_in[9]:7 chanx_right_in[9]:6 9.239131e-05 +2 chanx_right_in[9]:8 chanx_right_in[9]:7 0.0045 +3 chanx_right_in[9]:6 mux_bottom_track_9\/mux_l1_in_1_:A0 0.152 +4 chanx_right_in[9]:4 chanx_right_in[9]:3 0.0004888393 +5 chanx_right_in[9]:5 chanx_right_in[9]:4 0.0045 +6 chanx_right_in[9]:3 mux_top_track_2\/mux_l1_in_0_:A0 0.152 +7 chanx_right_in[9]:9 chanx_right_in[9]:8 0.005727679 +8 chanx_right_in[9]:9 chanx_right_in[9]:5 0.002084821 +9 chanx_right_in[9]:10 chanx_right_in[9]:9 0.00341 + +*END + +*D_NET chanx_right_in[13] 0.01670137 //LENGTH 128.160 LUMPCC 0.005848286 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 111.930 32.640 +*I mux_bottom_track_33\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.520 36.380 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 39.390 76.840 +*N chanx_right_in[13]:3 *C 39.352 76.840 +*N chanx_right_in[13]:4 *C 35.465 76.840 +*N chanx_right_in[13]:5 *C 35.420 76.795 +*N chanx_right_in[13]:6 *C 35.420 40.120 +*N chanx_right_in[13]:7 *C 34.960 40.120 +*N chanx_right_in[13]:8 *C 35.483 36.380 +*N chanx_right_in[13]:9 *C 35.005 36.380 +*N chanx_right_in[13]:10 *C 34.960 36.380 +*N chanx_right_in[13]:11 *C 34.960 33.378 +*N chanx_right_in[13]:12 *C 34.968 33.320 +*N chanx_right_in[13]:13 *C 59.800 33.320 +*N chanx_right_in[13]:14 *C 59.800 32.640 + +*CAP +0 chanx_right_in[13] 0.00178154 +1 mux_bottom_track_33\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[13]:3 0.0002175813 +4 chanx_right_in[13]:4 0.0002175813 +5 chanx_right_in[13]:5 0.001726922 +6 chanx_right_in[13]:6 0.001753071 +7 chanx_right_in[13]:7 0.0001658858 +8 chanx_right_in[13]:8 5.025477e-05 +9 chanx_right_in[13]:9 5.025477e-05 +10 chanx_right_in[13]:10 0.0002907451 +11 chanx_right_in[13]:11 0.0001256125 +12 chanx_right_in[13]:12 0.001295478 +13 chanx_right_in[13]:13 0.001345049 +14 chanx_right_in[13]:14 0.001831112 +15 chanx_right_in[13]:10 prog_clk[0]:421 2.417962e-05 +16 chanx_right_in[13]:10 prog_clk[0]:425 3.169378e-05 +17 chanx_right_in[13]:5 prog_clk[0]:315 1.934165e-05 +18 chanx_right_in[13]:5 prog_clk[0]:452 2.670041e-05 +19 chanx_right_in[13]:5 prog_clk[0]:458 6.911314e-05 +20 chanx_right_in[13]:5 prog_clk[0]:459 3.965082e-05 +21 chanx_right_in[13]:11 prog_clk[0]:421 2.200415e-05 +22 chanx_right_in[13]:12 prog_clk[0]:420 0.0004682779 +23 chanx_right_in[13]:7 prog_clk[0]:425 2.417962e-05 +24 chanx_right_in[13]:7 prog_clk[0]:452 9.689627e-06 +25 chanx_right_in[13]:6 prog_clk[0]:314 1.934165e-05 +26 chanx_right_in[13]:6 prog_clk[0]:425 2.670041e-05 +27 chanx_right_in[13]:6 prog_clk[0]:452 6.911314e-05 +28 chanx_right_in[13]:6 prog_clk[0]:458 3.965082e-05 +29 chanx_right_in[13]:13 prog_clk[0]:419 0.0004682779 +30 chanx_right_in[13]:13 prog_clk[0]:440 7.394791e-06 +31 chanx_right_in[13]:14 prog_clk[0]:435 7.394791e-06 +32 chanx_right_in[13] chanx_right_in[17] 0.0006651179 +33 chanx_right_in[13]:14 chanx_right_in[17]:10 0.0006651179 +34 chanx_right_in[13] chanx_right_in[19] 0.0003195047 +35 chanx_right_in[13] chanx_right_in[19]:11 0.0009120154 +36 chanx_right_in[13]:12 chanx_right_in[19]:10 0.0001020369 +37 chanx_right_in[13]:12 chanx_right_in[19]:6 0.000107396 +38 chanx_right_in[13]:13 chanx_right_in[19]:10 0.000107396 +39 chanx_right_in[13]:13 chanx_right_in[19]:11 0.0001020369 +40 chanx_right_in[13]:14 chanx_right_in[19]:10 0.0009120154 +41 chanx_right_in[13]:14 chanx_right_in[19]:11 0.0003195047 +42 chanx_right_in[13]:5 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:4 4.528826e-05 +43 chanx_right_in[13]:6 mux_tree_tapbuf_size4_mem_6_ccff_tail[0]:5 4.528826e-05 +44 chanx_right_in[13]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 8.643181e-05 +45 chanx_right_in[13]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 8.643181e-05 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:14 0.008167033 +1 chanx_right_in[13]:9 chanx_right_in[13]:8 0.0004263393 +2 chanx_right_in[13]:10 chanx_right_in[13]:9 0.0045 +3 chanx_right_in[13]:10 chanx_right_in[13]:7 0.003339286 +4 chanx_right_in[13]:8 mux_bottom_track_33\/mux_l1_in_1_:A1 0.152 +5 chanx_right_in[13]:4 chanx_right_in[13]:3 0.003470982 +6 chanx_right_in[13]:5 chanx_right_in[13]:4 0.0045 +7 chanx_right_in[13]:3 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +8 chanx_right_in[13]:11 chanx_right_in[13]:10 0.002680804 +9 chanx_right_in[13]:12 chanx_right_in[13]:11 0.00341 +10 chanx_right_in[13]:7 chanx_right_in[13]:6 0.0004107143 +11 chanx_right_in[13]:6 chanx_right_in[13]:5 0.03274554 +12 chanx_right_in[13]:13 chanx_right_in[13]:12 0.003890425 +13 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0001065333 + +*END + +*D_NET right_top_grid_pin_42_[0] 0.01746167 //LENGTH 130.997 LUMPCC 0.004095788 DR + +*CONN +*P right_top_grid_pin_42_[0] I *L 0.29796 *C 109.940 102.070 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 45.830 104.040 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 32.030 64.600 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 78.375 96.900 +*I mux_right_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 74.980 101.660 +*N right_top_grid_pin_42_[0]:5 *C 74.980 101.645 +*N right_top_grid_pin_42_[0]:6 *C 78.338 96.900 +*N right_top_grid_pin_42_[0]:7 *C 75.025 96.900 +*N right_top_grid_pin_42_[0]:8 *C 74.980 96.945 +*N right_top_grid_pin_42_[0]:9 *C 31.490 65.280 +*N right_top_grid_pin_42_[0]:10 *C 32.030 64.600 +*N right_top_grid_pin_42_[0]:11 *C 32.200 64.600 +*N right_top_grid_pin_42_[0]:12 *C 32.200 64.645 +*N right_top_grid_pin_42_[0]:13 *C 32.200 65.222 +*N right_top_grid_pin_42_[0]:14 *C 32.197 65.280 +*N right_top_grid_pin_42_[0]:15 *C 32.200 65.288 +*N right_top_grid_pin_42_[0]:16 *C 32.200 101.312 +*N right_top_grid_pin_42_[0]:17 *C 32.220 101.320 +*N right_top_grid_pin_42_[0]:18 *C 45.793 104.040 +*N right_top_grid_pin_42_[0]:19 *C 45.125 104.040 +*N right_top_grid_pin_42_[0]:20 *C 45.080 103.995 +*N right_top_grid_pin_42_[0]:21 *C 45.080 101.378 +*N right_top_grid_pin_42_[0]:22 *C 45.080 101.320 +*N right_top_grid_pin_42_[0]:23 *C 74.972 101.320 +*N right_top_grid_pin_42_[0]:24 *C 74.980 101.320 +*N right_top_grid_pin_42_[0]:25 *C 75.002 101.320 +*N right_top_grid_pin_42_[0]:26 *C 109.895 101.320 +*N right_top_grid_pin_42_[0]:27 *C 109.940 101.365 + +*CAP +0 right_top_grid_pin_42_[0] 5.12498e-05 +1 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +4 mux_right_track_4\/mux_l1_in_1_:A1 1e-06 +5 right_top_grid_pin_42_[0]:5 3.902138e-05 +6 right_top_grid_pin_42_[0]:6 0.0002582599 +7 right_top_grid_pin_42_[0]:7 0.0002582599 +8 right_top_grid_pin_42_[0]:8 0.0002857852 +9 right_top_grid_pin_42_[0]:9 9.082218e-05 +10 right_top_grid_pin_42_[0]:10 4.969697e-05 +11 right_top_grid_pin_42_[0]:11 5.40904e-05 +12 right_top_grid_pin_42_[0]:12 5.460027e-05 +13 right_top_grid_pin_42_[0]:13 5.460027e-05 +14 right_top_grid_pin_42_[0]:14 9.082218e-05 +15 right_top_grid_pin_42_[0]:15 0.00128832 +16 right_top_grid_pin_42_[0]:16 0.00128832 +17 right_top_grid_pin_42_[0]:17 0.0008069709 +18 right_top_grid_pin_42_[0]:18 6.934739e-05 +19 right_top_grid_pin_42_[0]:19 6.934739e-05 +20 right_top_grid_pin_42_[0]:20 0.0001963401 +21 right_top_grid_pin_42_[0]:21 0.0001963401 +22 right_top_grid_pin_42_[0]:22 0.002566462 +23 right_top_grid_pin_42_[0]:23 0.001759491 +24 right_top_grid_pin_42_[0]:24 0.0003222517 +25 right_top_grid_pin_42_[0]:25 0.001749626 +26 right_top_grid_pin_42_[0]:26 0.001710605 +27 right_top_grid_pin_42_[0]:27 5.12498e-05 +28 right_top_grid_pin_42_[0]:22 chany_bottom_in[5]:15 0.0001668225 +29 right_top_grid_pin_42_[0]:22 chany_bottom_in[5]:16 0.0003292307 +30 right_top_grid_pin_42_[0]:23 chany_bottom_in[5]:7 0.0003292307 +31 right_top_grid_pin_42_[0]:23 chany_bottom_in[5]:16 0.0001668225 +32 right_top_grid_pin_42_[0]:16 chany_bottom_in[13]:18 0.000520582 +33 right_top_grid_pin_42_[0]:15 chany_bottom_in[13]:19 0.000520582 +34 right_top_grid_pin_42_[0] right_top_grid_pin_49_[0] 1.111813e-06 +35 right_top_grid_pin_42_[0]:26 right_top_grid_pin_49_[0]:27 0.0002802349 +36 right_top_grid_pin_42_[0]:26 right_top_grid_pin_49_[0]:25 6.216184e-06 +37 right_top_grid_pin_42_[0]:27 right_top_grid_pin_49_[0]:28 1.111813e-06 +38 right_top_grid_pin_42_[0]:25 right_top_grid_pin_49_[0]:24 6.216184e-06 +39 right_top_grid_pin_42_[0]:25 right_top_grid_pin_49_[0]:26 0.0002802349 +40 right_top_grid_pin_42_[0]:22 right_top_grid_pin_49_[0]:20 1.307297e-05 +41 right_top_grid_pin_42_[0]:23 right_top_grid_pin_49_[0]:21 1.307297e-05 +42 right_top_grid_pin_42_[0]:26 mux_tree_tapbuf_size7_0_sram[0]:23 0.0007172013 +43 right_top_grid_pin_42_[0]:26 mux_tree_tapbuf_size7_0_sram[0]:21 1.342175e-05 +44 right_top_grid_pin_42_[0]:25 mux_tree_tapbuf_size7_0_sram[0]:20 1.342175e-05 +45 right_top_grid_pin_42_[0]:25 mux_tree_tapbuf_size7_0_sram[0]:22 0.0007172013 + +*RES +0 right_top_grid_pin_42_[0] right_top_grid_pin_42_[0]:27 0.0006294643 +1 right_top_grid_pin_42_[0]:5 mux_right_track_4\/mux_l1_in_1_:A1 0.152 +2 right_top_grid_pin_42_[0]:17 right_top_grid_pin_42_[0]:16 0.00341 +3 right_top_grid_pin_42_[0]:16 right_top_grid_pin_42_[0]:15 0.005643916 +4 right_top_grid_pin_42_[0]:14 right_top_grid_pin_42_[0]:13 0.00341 +5 right_top_grid_pin_42_[0]:14 right_top_grid_pin_42_[0]:9 0.000103914 +6 right_top_grid_pin_42_[0]:15 right_top_grid_pin_42_[0]:14 0.00341 +7 right_top_grid_pin_42_[0]:13 right_top_grid_pin_42_[0]:12 0.000515625 +8 right_top_grid_pin_42_[0]:11 right_top_grid_pin_42_[0]:10 9.239131e-05 +9 right_top_grid_pin_42_[0]:12 right_top_grid_pin_42_[0]:11 0.0045 +10 right_top_grid_pin_42_[0]:10 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +11 right_top_grid_pin_42_[0]:26 right_top_grid_pin_42_[0]:25 0.03115402 +12 right_top_grid_pin_42_[0]:27 right_top_grid_pin_42_[0]:26 0.0045 +13 right_top_grid_pin_42_[0]:25 right_top_grid_pin_42_[0]:24 0.0045 +14 right_top_grid_pin_42_[0]:25 right_top_grid_pin_42_[0]:5 0.0001766304 +15 right_top_grid_pin_42_[0]:24 right_top_grid_pin_42_[0]:23 0.00341 +16 right_top_grid_pin_42_[0]:24 right_top_grid_pin_42_[0]:8 0.00390625 +17 right_top_grid_pin_42_[0]:7 right_top_grid_pin_42_[0]:6 0.002957589 +18 right_top_grid_pin_42_[0]:8 right_top_grid_pin_42_[0]:7 0.0045 +19 right_top_grid_pin_42_[0]:6 mux_right_track_0\/mux_l1_in_0_:A0 0.152 +20 right_top_grid_pin_42_[0]:21 right_top_grid_pin_42_[0]:20 0.002337054 +21 right_top_grid_pin_42_[0]:22 right_top_grid_pin_42_[0]:21 0.00341 +22 right_top_grid_pin_42_[0]:22 right_top_grid_pin_42_[0]:17 0.002014733 +23 right_top_grid_pin_42_[0]:19 right_top_grid_pin_42_[0]:18 0.0005959822 +24 right_top_grid_pin_42_[0]:20 right_top_grid_pin_42_[0]:19 0.0045 +25 right_top_grid_pin_42_[0]:18 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +26 right_top_grid_pin_42_[0]:23 right_top_grid_pin_42_[0]:22 0.004683158 + +*END + +*D_NET chany_bottom_in[15] 0.008542049 //LENGTH 69.350 LUMPCC 0.002752467 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 46.460 1.290 +*I mux_right_track_26\/mux_l1_in_0_:A0 I *L 0.001631 *C 36.515 58.820 +*N chany_bottom_in[15]:2 *C 36.553 58.820 +*N chany_bottom_in[15]:3 *C 43.655 58.820 +*N chany_bottom_in[15]:4 *C 43.700 58.775 +*N chany_bottom_in[15]:5 *C 43.700 53.778 +*N chany_bottom_in[15]:6 *C 43.708 53.720 +*N chany_bottom_in[15]:7 *C 45.060 53.720 +*N chany_bottom_in[15]:8 *C 45.080 53.713 +*N chany_bottom_in[15]:9 *C 45.080 4.088 +*N chany_bottom_in[15]:10 *C 45.100 4.080 +*N chany_bottom_in[15]:11 *C 46.453 4.080 +*N chany_bottom_in[15]:12 *C 46.460 4.022 + +*CAP +0 chany_bottom_in[15] 0.0001953923 +1 mux_right_track_26\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[15]:2 0.0003939528 +3 chany_bottom_in[15]:3 0.0003939528 +4 chany_bottom_in[15]:4 0.0002273375 +5 chany_bottom_in[15]:5 0.0002273375 +6 chany_bottom_in[15]:6 0.0001206475 +7 chany_bottom_in[15]:7 0.0001206475 +8 chany_bottom_in[15]:8 0.001832616 +9 chany_bottom_in[15]:9 0.001832616 +10 chany_bottom_in[15]:10 0.0001243445 +11 chany_bottom_in[15]:11 0.0001243445 +12 chany_bottom_in[15]:12 0.0001953923 +13 chany_bottom_in[15]:8 chany_bottom_in[14]:17 3.301384e-05 +14 chany_bottom_in[15]:8 chany_bottom_in[14]:18 0.001045677 +15 chany_bottom_in[15]:10 chany_bottom_in[14]:21 2.048185e-05 +16 chany_bottom_in[15]:9 chany_bottom_in[14]:18 3.301384e-05 +17 chany_bottom_in[15]:9 chany_bottom_in[14]:19 0.001045677 +18 chany_bottom_in[15]:11 chany_bottom_in[14]:20 2.048185e-05 +19 chany_bottom_in[15]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.779281e-05 +20 chany_bottom_in[15]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.779281e-05 +21 chany_bottom_in[15]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.232756e-05 +22 chany_bottom_in[15]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.232756e-05 +23 chany_bottom_in[15]:2 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001869409 +24 chany_bottom_in[15]:3 mux_right_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001869409 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:12 0.002439732 +1 chany_bottom_in[15]:2 mux_right_track_26\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[15]:3 chany_bottom_in[15]:2 0.006341519 +3 chany_bottom_in[15]:4 chany_bottom_in[15]:3 0.0045 +4 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.004462054 +5 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.00341 +6 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.0002118917 +7 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.00341 +8 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.00341 +9 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.007774583 +10 chany_bottom_in[15]:12 chany_bottom_in[15]:11 0.00341 +11 chany_bottom_in[15]:11 chany_bottom_in[15]:10 0.0002118916 + +*END + +*D_NET chany_top_out[8] 0.005803254 //LENGTH 63.400 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/mux_l3_in_0_:X O *L 0 *C 16.780 72.420 +*P chany_top_out[8] O *L 0.7423 *C 22.080 129.350 +*N chany_top_out[8]:2 *C 22.080 125.128 +*N chany_top_out[8]:3 *C 22.060 125.120 +*N chany_top_out[8]:4 *C 19.328 125.120 +*N chany_top_out[8]:5 *C 19.320 125.062 +*N chany_top_out[8]:6 *C 19.320 72.465 +*N chany_top_out[8]:7 *C 19.275 72.420 +*N chany_top_out[8]:8 *C 16.818 72.420 + +*CAP +0 mux_top_track_16\/mux_l3_in_0_:X 1e-06 +1 chany_top_out[8] 0.000241343 +2 chany_top_out[8]:2 0.000241343 +3 chany_top_out[8]:3 0.0001742388 +4 chany_top_out[8]:4 0.0001742388 +5 chany_top_out[8]:5 0.002327989 +6 chany_top_out[8]:6 0.002327989 +7 chany_top_out[8]:7 0.0001575562 +8 chany_top_out[8]:8 0.0001575562 + +*RES +0 mux_top_track_16\/mux_l3_in_0_:X chany_top_out[8]:8 0.152 +1 chany_top_out[8]:8 chany_top_out[8]:7 0.002194196 +2 chany_top_out[8]:7 chany_top_out[8]:6 0.0045 +3 chany_top_out[8]:6 chany_top_out[8]:5 0.04696206 +4 chany_top_out[8]:5 chany_top_out[8]:4 0.00341 +5 chany_top_out[8]:4 chany_top_out[8]:3 0.0004280916 +6 chany_top_out[8]:3 chany_top_out[8]:2 0.00341 +7 chany_top_out[8]:2 chany_top_out[8] 0.0006615249 + +*END + +*D_NET chanx_right_out[2] 0.003939083 //LENGTH 36.360 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 100.800 85.680 +*P chanx_right_out[2] O *L 0.7423 *C 111.855 62.560 +*N chanx_right_out[2]:2 *C 111.328 62.560 +*N chanx_right_out[2]:3 *C 111.320 62.617 +*N chanx_right_out[2]:4 *C 111.320 81.260 +*N chanx_right_out[2]:5 *C 111.780 81.260 +*N chanx_right_out[2]:6 *C 111.780 85.295 +*N chanx_right_out[2]:7 *C 111.735 85.340 +*N chanx_right_out[2]:8 *C 100.740 85.340 +*N chanx_right_out[2]:9 *C 100.800 85.680 + +*CAP +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[2] 5.62648e-05 +2 chanx_right_out[2]:2 5.62648e-05 +3 chanx_right_out[2]:3 0.001022327 +4 chanx_right_out[2]:4 0.001050713 +5 chanx_right_out[2]:5 0.0002457107 +6 chanx_right_out[2]:6 0.0002173245 +7 chanx_right_out[2]:7 0.0006049395 +8 chanx_right_out[2]:8 0.0006312765 +9 chanx_right_out[2]:9 5.326247e-05 + +*RES +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[2]:9 0.152 +1 chanx_right_out[2]:9 chanx_right_out[2]:8 0.0003035715 +2 chanx_right_out[2]:7 chanx_right_out[2]:6 0.0045 +3 chanx_right_out[2]:6 chanx_right_out[2]:5 0.003602679 +4 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +5 chanx_right_out[2]:2 chanx_right_out[2] 8.264167e-05 +6 chanx_right_out[2]:8 chanx_right_out[2]:7 0.009816965 +7 chanx_right_out[2]:4 chanx_right_out[2]:3 0.01664509 +8 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0004107143 + +*END + +*D_NET chanx_right_out[10] 0.001949346 //LENGTH 16.945 LUMPCC 0 DR + +*CONN +*I mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 69.360 +*P chanx_right_out[10] O *L 0.7423 *C 111.930 61.200 +*N chanx_right_out[10]:2 *C 104.428 61.200 +*N chanx_right_out[10]:3 *C 104.420 61.258 +*N chanx_right_out[10]:4 *C 104.420 69.315 +*N chanx_right_out[10]:5 *C 104.465 69.360 +*N chanx_right_out[10]:6 *C 104.843 69.360 + +*CAP +0 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[10] 0.0004662031 +2 chanx_right_out[10]:2 0.0004662031 +3 chanx_right_out[10]:3 0.0004604802 +4 chanx_right_out[10]:4 0.0004604802 +5 chanx_right_out[10]:5 4.748975e-05 +6 chanx_right_out[10]:6 4.748975e-05 + +*RES +0 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +2 chanx_right_out[10]:2 chanx_right_out[10] 0.001175392 +3 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +4 chanx_right_out[10]:4 chanx_right_out[10]:3 0.007194197 +5 chanx_right_out[10]:6 chanx_right_out[10]:5 0.0003370536 + +*END + +*D_NET ropt_net_192 0.001177844 //LENGTH 10.340 LUMPCC 0.0003281131 DR + +*CONN +*I mux_bottom_track_3\/BUFT_P_145:X O *L 0 *C 36.970 9.180 +*I ropt_mt_inst_813:A I *L 0.001767 *C 32.660 4.080 +*N ropt_net_192:2 *C 32.698 4.080 +*N ropt_net_192:3 *C 36.295 4.080 +*N ropt_net_192:4 *C 36.340 4.125 +*N ropt_net_192:5 *C 36.340 9.135 +*N ropt_net_192:6 *C 36.385 9.180 +*N ropt_net_192:7 *C 36.933 9.180 + +*CAP +0 mux_bottom_track_3\/BUFT_P_145:X 1e-06 +1 ropt_mt_inst_813:A 1e-06 +2 ropt_net_192:2 0.0001282007 +3 ropt_net_192:3 0.0001282007 +4 ropt_net_192:4 0.0002434761 +5 ropt_net_192:5 0.0002434761 +6 ropt_net_192:6 5.21888e-05 +7 ropt_net_192:7 5.21888e-05 +8 ropt_net_192:2 chany_top_in[8]:6 0.0001511994 +9 ropt_net_192:3 chany_top_in[8]:7 0.0001511994 +10 ropt_net_192:4 chany_top_in[8]:8 1.285716e-05 +11 ropt_net_192:5 chany_top_in[8]:9 1.285716e-05 + +*RES +0 mux_bottom_track_3\/BUFT_P_145:X ropt_net_192:7 0.152 +1 ropt_net_192:2 ropt_mt_inst_813:A 0.152 +2 ropt_net_192:3 ropt_net_192:2 0.003212054 +3 ropt_net_192:4 ropt_net_192:3 0.0045 +4 ropt_net_192:6 ropt_net_192:5 0.0045 +5 ropt_net_192:5 ropt_net_192:4 0.004473215 +6 ropt_net_192:7 ropt_net_192:6 0.0004888393 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.0009087806 //LENGTH 7.730 LUMPCC 0 DR + +*CONN +*I mem_right_track_26\/FTB_28__58:X O *L 0 *C 43.475 58.140 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.555 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 47.518 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 45.585 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 45.540 60.815 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 45.540 58.185 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 45.495 58.140 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 43.513 58.140 + +*CAP +0 mem_right_track_26\/FTB_28__58:X 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.0001459739 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0001459739 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0001662797 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001662797 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0001411366 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0001411366 + +*RES +0 mem_right_track_26\/FTB_28__58:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.001725447 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[0] 0.001461296 //LENGTH 11.720 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 35.725 77.520 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 82.620 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 38.280 77.860 +*N mux_tree_tapbuf_size4_0_sram[0]:3 *C 38.242 77.860 +*N mux_tree_tapbuf_size4_0_sram[0]:4 *C 32.873 82.620 +*N mux_tree_tapbuf_size4_0_sram[0]:5 *C 35.835 82.620 +*N mux_tree_tapbuf_size4_0_sram[0]:6 *C 35.880 82.575 +*N mux_tree_tapbuf_size4_0_sram[0]:7 *C 35.880 77.905 +*N mux_tree_tapbuf_size4_0_sram[0]:8 *C 35.925 77.860 +*N mux_tree_tapbuf_size4_0_sram[0]:9 *C 35.725 77.520 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_0_sram[0]:3 0.0001782866 +4 mux_tree_tapbuf_size4_0_sram[0]:4 0.0002454896 +5 mux_tree_tapbuf_size4_0_sram[0]:5 0.0002454896 +6 mux_tree_tapbuf_size4_0_sram[0]:6 0.000260818 +7 mux_tree_tapbuf_size4_0_sram[0]:7 0.000260818 +8 mux_tree_tapbuf_size4_0_sram[0]:8 0.0002097638 +9 mux_tree_tapbuf_size4_0_sram[0]:9 5.763074e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_0_sram[0]:9 0.152 +1 mux_tree_tapbuf_size4_0_sram[0]:3 mux_top_track_24\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:3 0.002069197 +4 mux_tree_tapbuf_size4_0_sram[0]:7 mux_tree_tapbuf_size4_0_sram[0]:6 0.004169643 +5 mux_tree_tapbuf_size4_0_sram[0]:5 mux_tree_tapbuf_size4_0_sram[0]:4 0.002645089 +6 mux_tree_tapbuf_size4_0_sram[0]:6 mux_tree_tapbuf_size4_0_sram[0]:5 0.0045 +7 mux_tree_tapbuf_size4_0_sram[0]:4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size4_0_sram[0]:9 mux_tree_tapbuf_size4_0_sram[0]:8 0.0001847826 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[2] 0.001610122 //LENGTH 13.810 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 63.325 82.620 +*I mux_top_track_32\/mux_l3_in_0_:S I *L 0.00357 *C 56.680 85.000 +*I mem_top_track_32\/FTB_14__44:A I *L 0.001746 *C 65.320 85.680 +*N mux_tree_tapbuf_size4_1_sram[2]:3 *C 65.282 85.680 +*N mux_tree_tapbuf_size4_1_sram[2]:4 *C 62.560 85.680 +*N mux_tree_tapbuf_size4_1_sram[2]:5 *C 56.718 85.000 +*N mux_tree_tapbuf_size4_1_sram[2]:6 *C 62.560 85.030 +*N mux_tree_tapbuf_size4_1_sram[2]:7 *C 62.560 84.955 +*N mux_tree_tapbuf_size4_1_sram[2]:8 *C 62.560 82.665 +*N mux_tree_tapbuf_size4_1_sram[2]:9 *C 62.605 82.620 +*N mux_tree_tapbuf_size4_1_sram[2]:10 *C 63.288 82.620 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_32\/FTB_14__44:A 1e-06 +3 mux_tree_tapbuf_size4_1_sram[2]:3 0.0001539074 +4 mux_tree_tapbuf_size4_1_sram[2]:4 0.0001969039 +5 mux_tree_tapbuf_size4_1_sram[2]:5 0.000384864 +6 mux_tree_tapbuf_size4_1_sram[2]:6 0.0004278605 +7 mux_tree_tapbuf_size4_1_sram[2]:7 0.0001534642 +8 mux_tree_tapbuf_size4_1_sram[2]:8 0.0001534642 +9 mux_tree_tapbuf_size4_1_sram[2]:9 6.832893e-05 +10 mux_tree_tapbuf_size4_1_sram[2]:10 6.832893e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_1_sram[2]:10 0.152 +1 mux_tree_tapbuf_size4_1_sram[2]:3 mem_top_track_32\/FTB_14__44:A 0.152 +2 mux_tree_tapbuf_size4_1_sram[2]:6 mux_tree_tapbuf_size4_1_sram[2]:5 0.005216518 +3 mux_tree_tapbuf_size4_1_sram[2]:6 mux_tree_tapbuf_size4_1_sram[2]:4 0.0005803572 +4 mux_tree_tapbuf_size4_1_sram[2]:7 mux_tree_tapbuf_size4_1_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size4_1_sram[2]:9 mux_tree_tapbuf_size4_1_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size4_1_sram[2]:8 mux_tree_tapbuf_size4_1_sram[2]:7 0.002044643 +7 mux_tree_tapbuf_size4_1_sram[2]:10 mux_tree_tapbuf_size4_1_sram[2]:9 0.000609375 +8 mux_tree_tapbuf_size4_1_sram[2]:5 mux_top_track_32\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size4_1_sram[2]:4 mux_tree_tapbuf_size4_1_sram[2]:3 0.002430804 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[1] 0.00282706 //LENGTH 22.520 LUMPCC 0.0002885556 DR + +*CONN +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 37.105 96.560 +*I mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.375 93.500 +*I mux_right_track_10\/mux_l2_in_1_:S I *L 0.00357 *C 34.860 88.400 +*I mux_right_track_10\/mux_l2_in_0_:S I *L 0.00357 *C 41.500 96.560 +*N mux_tree_tapbuf_size4_3_sram[1]:4 *C 41.462 96.560 +*N mux_tree_tapbuf_size4_3_sram[1]:5 *C 34.823 88.400 +*N mux_tree_tapbuf_size4_3_sram[1]:6 *C 32.705 88.400 +*N mux_tree_tapbuf_size4_3_sram[1]:7 *C 32.660 88.445 +*N mux_tree_tapbuf_size4_3_sram[1]:8 *C 32.375 93.500 +*N mux_tree_tapbuf_size4_3_sram[1]:9 *C 32.660 93.500 +*N mux_tree_tapbuf_size4_3_sram[1]:10 *C 32.660 93.500 +*N mux_tree_tapbuf_size4_3_sram[1]:11 *C 32.660 93.103 +*N mux_tree_tapbuf_size4_3_sram[1]:12 *C 32.668 93.160 +*N mux_tree_tapbuf_size4_3_sram[1]:13 *C 33.573 93.160 +*N mux_tree_tapbuf_size4_3_sram[1]:14 *C 33.580 93.218 +*N mux_tree_tapbuf_size4_3_sram[1]:15 *C 33.580 96.855 +*N mux_tree_tapbuf_size4_3_sram[1]:16 *C 33.625 96.900 +*N mux_tree_tapbuf_size4_3_sram[1]:17 *C 37.105 96.900 +*N mux_tree_tapbuf_size4_3_sram[1]:18 *C 37.105 96.560 + +*CAP +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_10\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_10\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_3_sram[1]:4 0.0002844167 +5 mux_tree_tapbuf_size4_3_sram[1]:5 0.0001668245 +6 mux_tree_tapbuf_size4_3_sram[1]:6 0.0001668245 +7 mux_tree_tapbuf_size4_3_sram[1]:7 0.000257948 +8 mux_tree_tapbuf_size4_3_sram[1]:8 5.218263e-05 +9 mux_tree_tapbuf_size4_3_sram[1]:9 5.286662e-05 +10 mux_tree_tapbuf_size4_3_sram[1]:10 4.341578e-05 +11 mux_tree_tapbuf_size4_3_sram[1]:11 0.0002712224 +12 mux_tree_tapbuf_size4_3_sram[1]:12 7.900043e-05 +13 mux_tree_tapbuf_size4_3_sram[1]:13 7.900043e-05 +14 mux_tree_tapbuf_size4_3_sram[1]:14 0.000225746 +15 mux_tree_tapbuf_size4_3_sram[1]:15 0.000225746 +16 mux_tree_tapbuf_size4_3_sram[1]:16 0.0001458006 +17 mux_tree_tapbuf_size4_3_sram[1]:17 0.0001724468 +18 mux_tree_tapbuf_size4_3_sram[1]:18 0.000311063 +19 mux_tree_tapbuf_size4_3_sram[1]:16 mux_tree_tapbuf_size4_3_sram[0]:7 0.0001385858 +20 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[0]:7 5.691974e-06 +21 mux_tree_tapbuf_size4_3_sram[1]:4 mux_tree_tapbuf_size4_3_sram[0]:8 5.691974e-06 +22 mux_tree_tapbuf_size4_3_sram[1]:17 mux_tree_tapbuf_size4_3_sram[0]:8 0.0001385858 + +*RES +0 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_3_sram[1]:18 0.152 +1 mux_tree_tapbuf_size4_3_sram[1]:11 mux_tree_tapbuf_size4_3_sram[1]:10 0.0001911058 +2 mux_tree_tapbuf_size4_3_sram[1]:11 mux_tree_tapbuf_size4_3_sram[1]:7 0.004158483 +3 mux_tree_tapbuf_size4_3_sram[1]:12 mux_tree_tapbuf_size4_3_sram[1]:11 0.00341 +4 mux_tree_tapbuf_size4_3_sram[1]:14 mux_tree_tapbuf_size4_3_sram[1]:13 0.00341 +5 mux_tree_tapbuf_size4_3_sram[1]:13 mux_tree_tapbuf_size4_3_sram[1]:12 0.0001417833 +6 mux_tree_tapbuf_size4_3_sram[1]:16 mux_tree_tapbuf_size4_3_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size4_3_sram[1]:15 mux_tree_tapbuf_size4_3_sram[1]:14 0.003247768 +8 mux_tree_tapbuf_size4_3_sram[1]:9 mux_tree_tapbuf_size4_3_sram[1]:8 0.0001548913 +9 mux_tree_tapbuf_size4_3_sram[1]:10 mux_tree_tapbuf_size4_3_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size4_3_sram[1]:8 mem_right_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[1]:17 0.0003035715 +12 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[1]:4 0.003890626 +13 mux_tree_tapbuf_size4_3_sram[1]:6 mux_tree_tapbuf_size4_3_sram[1]:5 0.001890625 +14 mux_tree_tapbuf_size4_3_sram[1]:7 mux_tree_tapbuf_size4_3_sram[1]:6 0.0045 +15 mux_tree_tapbuf_size4_3_sram[1]:5 mux_right_track_10\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size4_3_sram[1]:4 mux_right_track_10\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size4_3_sram[1]:17 mux_tree_tapbuf_size4_3_sram[1]:16 0.003107143 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_0_ccff_tail[0] 0.000628999 //LENGTH 4.840 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/FTB_13__43:X O *L 0 *C 44.395 79.900 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 42.955 77.180 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 *C 42.992 77.180 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 *C 44.115 77.180 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 *C 44.160 77.225 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 *C 44.160 79.855 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 *C 44.160 79.900 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 *C 44.395 79.900 + +*CAP +0 mem_top_track_24\/FTB_13__43:X 1e-06 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 9.931427e-05 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 9.931427e-05 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.0001600987 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0001600987 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 5.531548e-05 +7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 5.285757e-05 + +*RES +0 mem_top_track_24\/FTB_13__43:X mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 0.001002232 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[0] 0.003007735 //LENGTH 22.150 LUMPCC 0.0001034328 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 101.045 60.860 +*I mux_top_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 99.920 52.360 +*I mux_top_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 97.980 47.425 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 95.855 55.420 +*N mux_tree_tapbuf_size5_0_sram[0]:4 *C 95.892 55.420 +*N mux_tree_tapbuf_size5_0_sram[0]:5 *C 97.980 47.425 +*N mux_tree_tapbuf_size5_0_sram[0]:6 *C 97.980 47.600 +*N mux_tree_tapbuf_size5_0_sram[0]:7 *C 97.980 47.645 +*N mux_tree_tapbuf_size5_0_sram[0]:8 *C 97.980 52.315 +*N mux_tree_tapbuf_size5_0_sram[0]:9 *C 98.025 52.360 +*N mux_tree_tapbuf_size5_0_sram[0]:10 *C 99.833 52.360 +*N mux_tree_tapbuf_size5_0_sram[0]:11 *C 99.820 52.405 +*N mux_tree_tapbuf_size5_0_sram[0]:12 *C 99.820 55.375 +*N mux_tree_tapbuf_size5_0_sram[0]:13 *C 99.820 55.420 +*N mux_tree_tapbuf_size5_0_sram[0]:14 *C 100.695 55.420 +*N mux_tree_tapbuf_size5_0_sram[0]:15 *C 100.740 55.465 +*N mux_tree_tapbuf_size5_0_sram[0]:16 *C 100.740 60.815 +*N mux_tree_tapbuf_size5_0_sram[0]:17 *C 100.740 60.860 +*N mux_tree_tapbuf_size5_0_sram[0]:18 *C 101.045 60.860 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_2\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_2\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_0_sram[0]:4 0.0003049251 +5 mux_tree_tapbuf_size5_0_sram[0]:5 4.172925e-05 +6 mux_tree_tapbuf_size5_0_sram[0]:6 4.608888e-05 +7 mux_tree_tapbuf_size5_0_sram[0]:7 0.0003189894 +8 mux_tree_tapbuf_size5_0_sram[0]:8 0.0003189894 +9 mux_tree_tapbuf_size5_0_sram[0]:9 0.0001154087 +10 mux_tree_tapbuf_size5_0_sram[0]:10 0.0001154087 +11 mux_tree_tapbuf_size5_0_sram[0]:11 0.0001666473 +12 mux_tree_tapbuf_size5_0_sram[0]:12 0.0001666473 +13 mux_tree_tapbuf_size5_0_sram[0]:13 0.0004129803 +14 mux_tree_tapbuf_size5_0_sram[0]:14 7.63299e-05 +15 mux_tree_tapbuf_size5_0_sram[0]:15 0.0003567642 +16 mux_tree_tapbuf_size5_0_sram[0]:16 0.0003567642 +17 mux_tree_tapbuf_size5_0_sram[0]:17 5.183895e-05 +18 mux_tree_tapbuf_size5_0_sram[0]:18 5.079076e-05 +19 mux_tree_tapbuf_size5_0_sram[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.171638e-05 +20 mux_tree_tapbuf_size5_0_sram[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.171638e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_0_sram[0]:18 0.152 +1 mux_tree_tapbuf_size5_0_sram[0]:5 mux_top_track_2\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size5_0_sram[0]:6 mux_tree_tapbuf_size5_0_sram[0]:5 7.543104e-05 +3 mux_tree_tapbuf_size5_0_sram[0]:7 mux_tree_tapbuf_size5_0_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size5_0_sram[0]:8 mux_tree_tapbuf_size5_0_sram[0]:7 0.004169643 +6 mux_tree_tapbuf_size5_0_sram[0]:10 mux_top_track_2\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size5_0_sram[0]:10 mux_tree_tapbuf_size5_0_sram[0]:9 0.001613839 +8 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:4 0.003506697 +11 mux_tree_tapbuf_size5_0_sram[0]:12 mux_tree_tapbuf_size5_0_sram[0]:11 0.002651786 +12 mux_tree_tapbuf_size5_0_sram[0]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:13 0.0007812501 +14 mux_tree_tapbuf_size5_0_sram[0]:15 mux_tree_tapbuf_size5_0_sram[0]:14 0.0045 +15 mux_tree_tapbuf_size5_0_sram[0]:17 mux_tree_tapbuf_size5_0_sram[0]:16 0.0045 +16 mux_tree_tapbuf_size5_0_sram[0]:16 mux_tree_tapbuf_size5_0_sram[0]:15 0.004776786 +17 mux_tree_tapbuf_size5_0_sram[0]:18 mux_tree_tapbuf_size5_0_sram[0]:17 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_0_ccff_tail[0] 0.0005195179 //LENGTH 4.320 LUMPCC 7.375568e-05 DR + +*CONN +*I mem_top_track_2\/FTB_8__38:X O *L 0 *C 88.085 52.700 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 87.115 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 *C 87.115 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 *C 87.400 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 *C 87.400 50.025 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 *C 87.400 52.655 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 *C 87.445 52.700 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 *C 88.047 52.700 + +*CAP +0 mem_top_track_2\/FTB_8__38:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 4.999996e-05 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 5.296468e-05 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0001162379 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0001162379 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 5.416085e-05 +7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 5.416085e-05 +8 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 top_left_grid_pin_1_[0]:10 3.687784e-05 +9 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 top_left_grid_pin_1_[0]:11 3.687784e-05 + +*RES +0 mem_top_track_2\/FTB_8__38:X mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.005207214 //LENGTH 37.430 LUMPCC 0.0001300397 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 104.725 77.180 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 99.920 69.360 +*I mux_top_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 98.080 63.845 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 91.715 69.700 +*I mux_top_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 84.080 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 84.080 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 84.180 69.405 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 84.180 69.995 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 84.225 70.040 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 91.715 70.040 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 91.715 69.700 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 95.680 69.700 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 95.680 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 97.980 63.920 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 97.980 63.965 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 97.980 69.315 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 97.980 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 99.920 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 102.075 69.360 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 102.120 69.405 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 102.120 77.135 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 102.165 77.180 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 104.688 77.180 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_0\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 3.026041e-05 +6 mux_tree_tapbuf_size6_0_sram[0]:6 6.498702e-05 +7 mux_tree_tapbuf_size6_0_sram[0]:7 6.498702e-05 +8 mux_tree_tapbuf_size6_0_sram[0]:8 0.0005159968 +9 mux_tree_tapbuf_size6_0_sram[0]:9 0.0005434694 +10 mux_tree_tapbuf_size6_0_sram[0]:10 0.0003815214 +11 mux_tree_tapbuf_size6_0_sram[0]:11 0.0003816371 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.000215184 +13 mux_tree_tapbuf_size6_0_sram[0]:13 3.653457e-05 +14 mux_tree_tapbuf_size6_0_sram[0]:14 0.0003299654 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0003299654 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.0003591666 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0003209471 +18 mux_tree_tapbuf_size6_0_sram[0]:18 0.0001559086 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0005045206 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0005045206 +21 mux_tree_tapbuf_size6_0_sram[0]:21 0.0001663007 +22 mux_tree_tapbuf_size6_0_sram[0]:22 0.0001663007 +23 mux_tree_tapbuf_size6_0_sram[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.501986e-05 +24 mux_tree_tapbuf_size6_0_sram[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.501986e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:8 mux_tree_tapbuf_size6_0_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.0005267857 +3 mux_tree_tapbuf_size6_0_sram[0]:5 mux_top_track_0\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size6_0_sram[0]:6 mux_tree_tapbuf_size6_0_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size6_0_sram[0]:17 mux_top_track_0\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.001732143 +7 mux_tree_tapbuf_size6_0_sram[0]:10 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0003035715 +9 mux_tree_tapbuf_size6_0_sram[0]:13 mux_top_track_0\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 0.0045 +11 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.0045 +12 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:12 0.002053572 +13 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.004776786 +14 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.001924107 +15 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.0045 +17 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.006901786 +18 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.002252232 +19 mux_tree_tapbuf_size6_0_sram[0]:9 mux_tree_tapbuf_size6_0_sram[0]:8 0.006687501 +20 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:10 0.003540179 +21 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[2] 0.001508344 //LENGTH 11.855 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 52.285 23.120 +*I mux_bottom_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 49.120 18.360 +*I mem_bottom_track_1\/FTB_5__35:A I *L 0.001746 *C 55.200 23.120 +*N mux_tree_tapbuf_size6_4_sram[2]:3 *C 55.163 23.120 +*N mux_tree_tapbuf_size6_4_sram[2]:4 *C 49.157 18.360 +*N mux_tree_tapbuf_size6_4_sram[2]:5 *C 52.395 18.360 +*N mux_tree_tapbuf_size6_4_sram[2]:6 *C 52.440 18.405 +*N mux_tree_tapbuf_size6_4_sram[2]:7 *C 52.440 23.075 +*N mux_tree_tapbuf_size6_4_sram[2]:8 *C 52.485 23.120 +*N mux_tree_tapbuf_size6_4_sram[2]:9 *C 52.285 23.120 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_1\/FTB_5__35:A 1e-06 +3 mux_tree_tapbuf_size6_4_sram[2]:3 0.000167438 +4 mux_tree_tapbuf_size6_4_sram[2]:4 0.0002418156 +5 mux_tree_tapbuf_size6_4_sram[2]:5 0.0002418156 +6 mux_tree_tapbuf_size6_4_sram[2]:6 0.0003097779 +7 mux_tree_tapbuf_size6_4_sram[2]:7 0.0003097779 +8 mux_tree_tapbuf_size6_4_sram[2]:8 0.0001877019 +9 mux_tree_tapbuf_size6_4_sram[2]:9 4.701731e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_4_sram[2]:9 0.152 +1 mux_tree_tapbuf_size6_4_sram[2]:9 mux_tree_tapbuf_size6_4_sram[2]:8 0.0001086957 +2 mux_tree_tapbuf_size6_4_sram[2]:8 mux_tree_tapbuf_size6_4_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size6_4_sram[2]:8 mux_tree_tapbuf_size6_4_sram[2]:3 0.002390625 +4 mux_tree_tapbuf_size6_4_sram[2]:7 mux_tree_tapbuf_size6_4_sram[2]:6 0.004169643 +5 mux_tree_tapbuf_size6_4_sram[2]:5 mux_tree_tapbuf_size6_4_sram[2]:4 0.002890625 +6 mux_tree_tapbuf_size6_4_sram[2]:6 mux_tree_tapbuf_size6_4_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size6_4_sram[2]:4 mux_bottom_track_1\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_4_sram[2]:3 mem_bottom_track_1\/FTB_5__35:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_6_sram[2] 0.002654016 //LENGTH 16.905 LUMPCC 0.001152082 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 100.585 39.100 +*I mux_bottom_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 92.560 36.380 +*I mem_bottom_track_9\/FTB_7__37:A I *L 0.001746 *C 97.520 42.160 +*N mux_tree_tapbuf_size6_6_sram[2]:3 *C 97.520 42.160 +*N mux_tree_tapbuf_size6_6_sram[2]:4 *C 97.520 42.115 +*N mux_tree_tapbuf_size6_6_sram[2]:5 *C 92.460 36.380 +*N mux_tree_tapbuf_size6_6_sram[2]:6 *C 92.460 36.425 +*N mux_tree_tapbuf_size6_6_sram[2]:7 *C 92.460 40.742 +*N mux_tree_tapbuf_size6_6_sram[2]:8 *C 92.468 40.800 +*N mux_tree_tapbuf_size6_6_sram[2]:9 *C 97.513 40.800 +*N mux_tree_tapbuf_size6_6_sram[2]:10 *C 97.520 40.800 +*N mux_tree_tapbuf_size6_6_sram[2]:11 *C 97.520 39.145 +*N mux_tree_tapbuf_size6_6_sram[2]:12 *C 97.565 39.100 +*N mux_tree_tapbuf_size6_6_sram[2]:13 *C 100.547 39.100 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_9\/FTB_7__37:A 1e-06 +3 mux_tree_tapbuf_size6_6_sram[2]:3 3.187673e-05 +4 mux_tree_tapbuf_size6_6_sram[2]:4 6.756286e-05 +5 mux_tree_tapbuf_size6_6_sram[2]:5 3.337919e-05 +6 mux_tree_tapbuf_size6_6_sram[2]:6 0.0002046768 +7 mux_tree_tapbuf_size6_6_sram[2]:7 0.0002046768 +8 mux_tree_tapbuf_size6_6_sram[2]:8 0.000118886 +9 mux_tree_tapbuf_size6_6_sram[2]:9 0.000118886 +10 mux_tree_tapbuf_size6_6_sram[2]:10 0.0002044329 +11 mux_tree_tapbuf_size6_6_sram[2]:11 0.0001009511 +12 mux_tree_tapbuf_size6_6_sram[2]:12 0.0002068031 +13 mux_tree_tapbuf_size6_6_sram[2]:13 0.0002068031 +14 mux_tree_tapbuf_size6_6_sram[2]:11 mux_tree_tapbuf_size6_6_sram[0]:13 1.06538e-05 +15 mux_tree_tapbuf_size6_6_sram[2]:10 mux_tree_tapbuf_size6_6_sram[0]:13 1.585454e-05 +16 mux_tree_tapbuf_size6_6_sram[2]:10 mux_tree_tapbuf_size6_6_sram[0]:14 1.251904e-05 +17 mux_tree_tapbuf_size6_6_sram[2]:9 mux_tree_tapbuf_size6_6_sram[0]:15 0.0001252111 +18 mux_tree_tapbuf_size6_6_sram[2]:8 mux_tree_tapbuf_size6_6_sram[0]:16 0.0001252111 +19 mux_tree_tapbuf_size6_6_sram[2]:4 mux_tree_tapbuf_size6_6_sram[0]:10 1.865241e-06 +20 mux_tree_tapbuf_size6_6_sram[2]:4 mux_tree_tapbuf_size6_6_sram[0]:14 1.585454e-05 +21 mux_tree_tapbuf_size6_6_sram[2]:7 mux_tree_tapbuf_size6_6_sram[1]:7 4.771932e-05 +22 mux_tree_tapbuf_size6_6_sram[2]:7 mux_tree_tapbuf_size6_6_sram[1]:11 7.609167e-05 +23 mux_tree_tapbuf_size6_6_sram[2]:6 mux_tree_tapbuf_size6_6_sram[1]:10 7.609167e-05 +24 mux_tree_tapbuf_size6_6_sram[2]:6 mux_tree_tapbuf_size6_6_sram[1]:11 4.771932e-05 +25 mux_tree_tapbuf_size6_6_sram[2]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.103366e-08 +26 mux_tree_tapbuf_size6_6_sram[2]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.103366e-08 +27 mux_tree_tapbuf_size6_6_sram[2]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002806575 +28 mux_tree_tapbuf_size6_6_sram[2]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.79667e-05 +29 mux_tree_tapbuf_size6_6_sram[2]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.79667e-05 +30 mux_tree_tapbuf_size6_6_sram[2]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002806575 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_6_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_6_sram[2]:12 mux_tree_tapbuf_size6_6_sram[2]:11 0.0045 +2 mux_tree_tapbuf_size6_6_sram[2]:11 mux_tree_tapbuf_size6_6_sram[2]:10 0.001477679 +3 mux_tree_tapbuf_size6_6_sram[2]:13 mux_tree_tapbuf_size6_6_sram[2]:12 0.002662946 +4 mux_tree_tapbuf_size6_6_sram[2]:10 mux_tree_tapbuf_size6_6_sram[2]:9 0.00341 +5 mux_tree_tapbuf_size6_6_sram[2]:10 mux_tree_tapbuf_size6_6_sram[2]:4 0.001174107 +6 mux_tree_tapbuf_size6_6_sram[2]:9 mux_tree_tapbuf_size6_6_sram[2]:8 0.0007903833 +7 mux_tree_tapbuf_size6_6_sram[2]:7 mux_tree_tapbuf_size6_6_sram[2]:6 0.003854911 +8 mux_tree_tapbuf_size6_6_sram[2]:8 mux_tree_tapbuf_size6_6_sram[2]:7 0.00341 +9 mux_tree_tapbuf_size6_6_sram[2]:5 mux_bottom_track_9\/mux_l3_in_0_:S 0.152 +10 mux_tree_tapbuf_size6_6_sram[2]:6 mux_tree_tapbuf_size6_6_sram[2]:5 0.0045 +11 mux_tree_tapbuf_size6_6_sram[2]:3 mem_bottom_track_9\/FTB_7__37:A 0.152 +12 mux_tree_tapbuf_size6_6_sram[2]:4 mux_tree_tapbuf_size6_6_sram[2]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[0] 0.008056565 //LENGTH 60.745 LUMPCC 0.00202966 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 100.125 98.940 +*I mux_right_track_2\/mux_l1_in_2_:S I *L 0.00357 *C 80.400 101.710 +*I mux_right_track_2\/mux_l1_in_3_:S I *L 0.00357 *C 78.560 107.440 +*I mux_right_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 77.840 117.640 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 73.315 124.100 +*I mux_right_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 71.200 127.160 +*N mux_tree_tapbuf_size7_0_sram[0]:6 *C 71.237 127.160 +*N mux_tree_tapbuf_size7_0_sram[0]:7 *C 72.635 127.160 +*N mux_tree_tapbuf_size7_0_sram[0]:8 *C 72.680 127.115 +*N mux_tree_tapbuf_size7_0_sram[0]:9 *C 73.278 124.100 +*N mux_tree_tapbuf_size7_0_sram[0]:10 *C 72.725 124.100 +*N mux_tree_tapbuf_size7_0_sram[0]:11 *C 72.680 124.100 +*N mux_tree_tapbuf_size7_0_sram[0]:12 *C 72.680 117.685 +*N mux_tree_tapbuf_size7_0_sram[0]:13 *C 72.725 117.640 +*N mux_tree_tapbuf_size7_0_sram[0]:14 *C 77.840 117.640 +*N mux_tree_tapbuf_size7_0_sram[0]:15 *C 78.615 117.640 +*N mux_tree_tapbuf_size7_0_sram[0]:16 *C 78.660 117.595 +*N mux_tree_tapbuf_size7_0_sram[0]:17 *C 78.560 107.440 +*N mux_tree_tapbuf_size7_0_sram[0]:18 *C 78.660 107.440 +*N mux_tree_tapbuf_size7_0_sram[0]:19 *C 78.660 102.385 +*N mux_tree_tapbuf_size7_0_sram[0]:20 *C 78.705 102.340 +*N mux_tree_tapbuf_size7_0_sram[0]:21 *C 80.500 102.340 +*N mux_tree_tapbuf_size7_0_sram[0]:22 *C 80.487 101.733 +*N mux_tree_tapbuf_size7_0_sram[0]:23 *C 98.855 101.660 +*N mux_tree_tapbuf_size7_0_sram[0]:24 *C 98.900 101.615 +*N mux_tree_tapbuf_size7_0_sram[0]:25 *C 98.900 98.985 +*N mux_tree_tapbuf_size7_0_sram[0]:26 *C 98.945 98.940 +*N mux_tree_tapbuf_size7_0_sram[0]:27 *C 100.088 98.940 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_2\/mux_l1_in_2_:S 1e-06 +2 mux_right_track_2\/mux_l1_in_3_:S 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:S 1e-06 +4 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_right_track_2\/mux_l1_in_0_:S 1e-06 +6 mux_tree_tapbuf_size7_0_sram[0]:6 0.0001172733 +7 mux_tree_tapbuf_size7_0_sram[0]:7 0.0001172733 +8 mux_tree_tapbuf_size7_0_sram[0]:8 0.0001779376 +9 mux_tree_tapbuf_size7_0_sram[0]:9 5.936999e-05 +10 mux_tree_tapbuf_size7_0_sram[0]:10 5.936999e-05 +11 mux_tree_tapbuf_size7_0_sram[0]:11 0.0006237485 +12 mux_tree_tapbuf_size7_0_sram[0]:12 0.000410803 +13 mux_tree_tapbuf_size7_0_sram[0]:13 0.0004370684 +14 mux_tree_tapbuf_size7_0_sram[0]:14 0.0005447011 +15 mux_tree_tapbuf_size7_0_sram[0]:15 7.995667e-05 +16 mux_tree_tapbuf_size7_0_sram[0]:16 0.0005765221 +17 mux_tree_tapbuf_size7_0_sram[0]:17 2.945174e-05 +18 mux_tree_tapbuf_size7_0_sram[0]:18 0.000947308 +19 mux_tree_tapbuf_size7_0_sram[0]:19 0.000336689 +20 mux_tree_tapbuf_size7_0_sram[0]:20 7.441142e-05 +21 mux_tree_tapbuf_size7_0_sram[0]:21 0.0001193767 +22 mux_tree_tapbuf_size7_0_sram[0]:22 0.0004450399 +23 mux_tree_tapbuf_size7_0_sram[0]:23 0.0004000746 +24 mux_tree_tapbuf_size7_0_sram[0]:24 0.0001538162 +25 mux_tree_tapbuf_size7_0_sram[0]:25 0.0001538162 +26 mux_tree_tapbuf_size7_0_sram[0]:26 7.844819e-05 +27 mux_tree_tapbuf_size7_0_sram[0]:27 7.844819e-05 +28 mux_tree_tapbuf_size7_0_sram[0]:20 right_top_grid_pin_42_[0]:25 1.342175e-05 +29 mux_tree_tapbuf_size7_0_sram[0]:23 right_top_grid_pin_42_[0]:26 0.0007172013 +30 mux_tree_tapbuf_size7_0_sram[0]:22 right_top_grid_pin_42_[0]:25 0.0007172013 +31 mux_tree_tapbuf_size7_0_sram[0]:21 right_top_grid_pin_42_[0]:26 1.342175e-05 +32 mux_tree_tapbuf_size7_0_sram[0]:20 right_top_grid_pin_49_[0]:4 5.144102e-05 +33 mux_tree_tapbuf_size7_0_sram[0]:23 right_top_grid_pin_49_[0]:24 2.118669e-05 +34 mux_tree_tapbuf_size7_0_sram[0]:23 right_top_grid_pin_49_[0]:25 0.0002115795 +35 mux_tree_tapbuf_size7_0_sram[0]:22 right_top_grid_pin_49_[0]:4 2.118669e-05 +36 mux_tree_tapbuf_size7_0_sram[0]:22 right_top_grid_pin_49_[0]:24 0.0002115795 +37 mux_tree_tapbuf_size7_0_sram[0]:21 right_top_grid_pin_49_[0]:24 5.144102e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_0_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_0_sram[0]:20 mux_tree_tapbuf_size7_0_sram[0]:19 0.0045 +2 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:18 0.004513393 +3 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:22 0.01639955 +4 mux_tree_tapbuf_size7_0_sram[0]:24 mux_tree_tapbuf_size7_0_sram[0]:23 0.0045 +5 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:25 0.0045 +6 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_0_sram[0]:24 0.002348215 +7 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:26 0.001020089 +8 mux_tree_tapbuf_size7_0_sram[0]:13 mux_tree_tapbuf_size7_0_sram[0]:12 0.0045 +9 mux_tree_tapbuf_size7_0_sram[0]:12 mux_tree_tapbuf_size7_0_sram[0]:11 0.005727679 +10 mux_tree_tapbuf_size7_0_sram[0]:10 mux_tree_tapbuf_size7_0_sram[0]:9 0.0004933036 +11 mux_tree_tapbuf_size7_0_sram[0]:11 mux_tree_tapbuf_size7_0_sram[0]:10 0.0045 +12 mux_tree_tapbuf_size7_0_sram[0]:11 mux_tree_tapbuf_size7_0_sram[0]:8 0.002691964 +13 mux_tree_tapbuf_size7_0_sram[0]:9 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:14 0.0006919643 +15 mux_tree_tapbuf_size7_0_sram[0]:16 mux_tree_tapbuf_size7_0_sram[0]:15 0.0045 +16 mux_tree_tapbuf_size7_0_sram[0]:17 mux_right_track_2\/mux_l1_in_3_:S 0.152 +17 mux_tree_tapbuf_size7_0_sram[0]:18 mux_tree_tapbuf_size7_0_sram[0]:17 0.0045 +18 mux_tree_tapbuf_size7_0_sram[0]:18 mux_tree_tapbuf_size7_0_sram[0]:16 0.009066964 +19 mux_tree_tapbuf_size7_0_sram[0]:22 mux_right_track_2\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size7_0_sram[0]:22 mux_tree_tapbuf_size7_0_sram[0]:21 0.0005424108 +21 mux_tree_tapbuf_size7_0_sram[0]:14 mux_right_track_2\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_0_sram[0]:14 mux_tree_tapbuf_size7_0_sram[0]:13 0.004566964 +23 mux_tree_tapbuf_size7_0_sram[0]:7 mux_tree_tapbuf_size7_0_sram[0]:6 0.001247768 +24 mux_tree_tapbuf_size7_0_sram[0]:8 mux_tree_tapbuf_size7_0_sram[0]:7 0.0045 +25 mux_tree_tapbuf_size7_0_sram[0]:6 mux_right_track_2\/mux_l1_in_0_:S 0.152 +26 mux_tree_tapbuf_size7_0_sram[0]:21 mux_tree_tapbuf_size7_0_sram[0]:20 0.001602679 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006819415 //LENGTH 5.160 LUMPCC 0.0001047204 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 93.555 66.980 +*I mux_top_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 88.685 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 88.723 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 93.517 66.980 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002876105 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002876105 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.236022e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.236022e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.00428125 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008342485 //LENGTH 6.085 LUMPCC 0.0002439114 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_1_:X O *L 0 *C 82.625 56.440 +*I mux_top_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 81.710 60.520 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 81.748 60.520 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 82.755 60.520 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 82.800 60.475 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 82.800 56.485 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 82.800 56.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 82.625 56.440 + +*CAP +0 mux_top_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.127172e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.127172e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001601864 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001601864 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.425757e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.116326e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.860054e-06 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.860054e-06 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001140956 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001140956 + +*RES +0 mux_top_track_4\/mux_l2_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008995536 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001301704 //LENGTH 11.190 LUMPCC 0.0003345219 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_1_:X O *L 0 *C 63.195 60.520 +*I mux_top_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 61.930 69.700 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 61.930 69.700 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 62.100 69.700 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 62.100 69.655 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 62.100 60.565 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 62.145 60.520 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 63.158 60.520 + +*CAP +0 mux_top_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.048295e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.644368e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003374174 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003374173 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.171022e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.171022e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[7]:5 5.677426e-06 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[7]:9 0.00011446 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[7]:8 0.00011446 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[7]:9 5.677426e-06 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.052274e-06 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.052274e-06 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.40713e-05 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.40713e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.23913e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.008116072 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005600356 //LENGTH 4.550 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_2_:X O *L 0 *C 47.095 31.620 +*I mux_bottom_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 48.205 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 48.205 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 48.300 34.295 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 48.300 31.665 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 48.255 31.620 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 47.133 31.620 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.886627e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001664836 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001664836 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.810109e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.810109e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002348214 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001002232 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006948267 //LENGTH 4.245 LUMPCC 0.0003118217 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 74.345 28.900 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 78.300 28.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 78.263 28.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 74.383 28.900 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001905025 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001905025 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001559108 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001559108 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003464286 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002153071 //LENGTH 15.775 LUMPCC 0.0008087578 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_1_:X O *L 0 *C 78.835 33.320 +*I mux_bottom_track_5\/mux_l3_in_0_:A0 I *L 0.005103 *C 77.740 22.285 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 77.703 22.285 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 76.405 22.285 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 76.360 22.285 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 77.740 22.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 77.740 33.275 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 77.785 33.320 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 78.797 33.320 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001485538 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001485538 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001010874 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004124105 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003411465 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.528072e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 9.528072e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_5_sram[2]:6 0.0002689275 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_5_sram[2]:5 0.0002689275 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001354514 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001354514 + +*RES +0 mux_bottom_track_5\/mux_l2_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0009040179 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.009674108 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001158482 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A0 0.152 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001232143 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005711013 //LENGTH 4.290 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_1_:X O *L 0 *C 89.985 60.520 +*I mux_top_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 91.830 59.160 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 91.830 59.160 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 92.000 59.160 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 92.000 59.205 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 92.000 60.475 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 91.955 60.520 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 90.023 60.520 + +*CAP +0 mux_top_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.011917e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.311999e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.750444e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.750444e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001454267 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001454267 + +*RES +0 mux_top_track_2\/mux_l2_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.239131e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001133929 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009402786 //LENGTH 6.050 LUMPCC 0.0005212387 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_0_:X O *L 0 *C 69.285 41.820 +*I mux_bottom_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.905 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.905 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 69.000 36.425 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 69.000 41.775 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 69.000 41.820 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 69.285 41.820 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.871929e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001393041 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001393041 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.482286e-05 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.488972e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[6]:11 1.151921e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[6]:15 6.871374e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[6]:19 1.323877e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[6]:18 1.029695e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[6]:12 1.151921e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[6]:19 6.871374e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[6]:20 1.323877e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[6]:17 1.029695e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_out[8] 0.0001568506 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_out[8]:2 0.0001568506 + +*RES +0 mux_bottom_track_3\/mux_l1_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004776786 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548913 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001239226 //LENGTH 10.225 LUMPCC 0.0001029916 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 59.975 49.640 +*I mux_bottom_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 56.220 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 56.183 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 55.705 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 55.660 45.265 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 55.660 49.595 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 55.705 49.640 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 59.938 49.640 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.267519e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.267519e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002097364 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002097364 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002947057 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002947057 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[8]:14 5.214815e-06 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[8]:21 4.6281e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[8]:21 5.214815e-06 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[8]:22 4.6281e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003779018 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000858158 //LENGTH 6.570 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_0_:X O *L 0 *C 57.785 80.240 +*I mux_top_track_32\/mux_l3_in_0_:A1 I *L 0.00198 *C 57.405 85.340 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 57.443 85.340 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 57.915 85.340 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 57.960 85.295 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 57.960 80.285 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 57.960 80.240 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 57.785 80.240 + +*CAP +0 mux_top_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.173911e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.173911e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000303647 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000303647 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.107319e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.431264e-05 + +*RES +0 mux_top_track_32\/mux_l2_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000421875 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004212959 //LENGTH 2.990 LUMPCC 7.276518e-05 DR + +*CONN +*I mux_right_track_10\/mux_l1_in_0_:X O *L 0 *C 42.605 98.600 +*I mux_right_track_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 42.225 96.220 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 42.225 96.220 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 42.320 96.265 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 42.320 98.555 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 42.320 98.600 +*N mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 42.605 98.600 + +*CAP +0 mux_right_track_10\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_10\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.734531e-05 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001057351 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001057351 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.476525e-05 +6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.294989e-05 +7 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 right_top_grid_pin_43_[0]:15 1.1279e-05 +8 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 right_top_grid_pin_43_[0]:18 2.510359e-05 +9 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 right_top_grid_pin_43_[0]:18 1.1279e-05 +10 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 right_top_grid_pin_43_[0]:19 2.510359e-05 + +*RES +0 mux_right_track_10\/mux_l1_in_0_:X mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_10\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +5 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548913 + +*END + +*D_NET optlc_net_187 0.009340896 //LENGTH 73.140 LUMPCC 0.0001772912 DR + +*CONN +*I optlc_179:HI O *L 0 *C 76.820 60.860 +*I mux_top_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 88.035 60.520 +*I mux_top_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 80.675 55.080 +*I mux_bottom_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 80.330 49.640 +*I mux_top_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 86.655 71.400 +*I mux_right_track_18\/mux_l1_in_1_:A0 I *L 0.001631 *C 77.455 69.700 +*I mux_right_track_20\/mux_l1_in_1_:A0 I *L 0.001631 *C 69.175 70.040 +*I mux_top_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 65.150 60.520 +*N optlc_net_187:8 *C 65.188 60.520 +*N optlc_net_187:9 *C 69.213 70.040 +*N optlc_net_187:10 *C 77.280 70.040 +*N optlc_net_187:11 *C 77.455 69.700 +*N optlc_net_187:12 *C 77.280 69.700 +*N optlc_net_187:13 *C 77.280 69.655 +*N optlc_net_187:14 *C 86.618 71.400 +*N optlc_net_187:15 *C 84.685 71.400 +*N optlc_net_187:16 *C 84.640 71.355 +*N optlc_net_187:17 *C 80.330 49.640 +*N optlc_net_187:18 *C 80.500 49.640 +*N optlc_net_187:19 *C 80.500 49.685 +*N optlc_net_187:20 *C 80.675 55.080 +*N optlc_net_187:21 *C 80.500 55.080 +*N optlc_net_187:22 *C 80.500 55.080 +*N optlc_net_187:23 *C 80.500 57.062 +*N optlc_net_187:24 *C 80.508 57.120 +*N optlc_net_187:25 *C 84.633 57.120 +*N optlc_net_187:26 *C 84.640 57.178 +*N optlc_net_187:27 *C 87.998 60.520 +*N optlc_net_187:28 *C 84.685 60.520 +*N optlc_net_187:29 *C 84.640 60.520 +*N optlc_net_187:30 *C 84.640 66.980 +*N optlc_net_187:31 *C 84.595 66.980 +*N optlc_net_187:32 *C 77.325 66.980 +*N optlc_net_187:33 *C 77.280 67.025 +*N optlc_net_187:34 *C 76.820 66.980 +*N optlc_net_187:35 *C 76.820 60.565 +*N optlc_net_187:36 *C 76.820 60.520 +*N optlc_net_187:37 *C 76.820 60.860 + +*CAP +0 optlc_179:HI 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_track_17\/mux_l2_in_1_:A0 1e-06 +4 mux_top_track_0\/mux_l2_in_1_:A0 1e-06 +5 mux_right_track_18\/mux_l1_in_1_:A0 1e-06 +6 mux_right_track_20\/mux_l1_in_1_:A0 1e-06 +7 mux_top_track_8\/mux_l2_in_1_:A0 1e-06 +8 optlc_net_187:8 0.0008078276 +9 optlc_net_187:9 0.0005281835 +10 optlc_net_187:10 0.0005499047 +11 optlc_net_187:11 6.091033e-05 +12 optlc_net_187:12 8.341682e-05 +13 optlc_net_187:13 0.0001699402 +14 optlc_net_187:14 0.0001862057 +15 optlc_net_187:15 0.0001862057 +16 optlc_net_187:16 0.0002551481 +17 optlc_net_187:17 5.411996e-05 +18 optlc_net_187:18 5.832789e-05 +19 optlc_net_187:19 0.0002873071 +20 optlc_net_187:20 4.996145e-05 +21 optlc_net_187:21 5.387902e-05 +22 optlc_net_187:22 0.000434879 +23 optlc_net_187:23 0.000115856 +24 optlc_net_187:24 0.0003013461 +25 optlc_net_187:25 0.0003013461 +26 optlc_net_187:26 0.0001915252 +27 optlc_net_187:27 0.0002397381 +28 optlc_net_187:28 0.0002397381 +29 optlc_net_187:29 0.0005625332 +30 optlc_net_187:30 0.000626253 +31 optlc_net_187:31 0.0004496135 +32 optlc_net_187:32 0.0004496135 +33 optlc_net_187:33 0.0002034908 +34 optlc_net_187:34 0.0004099006 +35 optlc_net_187:35 0.00037635 +36 optlc_net_187:36 0.0008488331 +37 optlc_net_187:37 7.324913e-05 +38 optlc_net_187:9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.864562e-05 +39 optlc_net_187:10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.864562e-05 + +*RES +0 optlc_179:HI optlc_net_187:37 0.152 +1 optlc_net_187:26 optlc_net_187:25 0.00341 +2 optlc_net_187:25 optlc_net_187:24 0.00064625 +3 optlc_net_187:23 optlc_net_187:22 0.001770089 +4 optlc_net_187:24 optlc_net_187:23 0.00341 +5 optlc_net_187:28 optlc_net_187:27 0.002957589 +6 optlc_net_187:29 optlc_net_187:28 0.0045 +7 optlc_net_187:29 optlc_net_187:26 0.002984375 +8 optlc_net_187:27 mux_top_track_2\/mux_l2_in_1_:A0 0.152 +9 optlc_net_187:15 optlc_net_187:14 0.001725446 +10 optlc_net_187:16 optlc_net_187:15 0.0045 +11 optlc_net_187:14 mux_top_track_0\/mux_l2_in_1_:A0 0.152 +12 optlc_net_187:12 optlc_net_187:11 9.51087e-05 +13 optlc_net_187:12 optlc_net_187:10 0.0003035715 +14 optlc_net_187:13 optlc_net_187:12 0.0045 +15 optlc_net_187:9 mux_right_track_20\/mux_l1_in_1_:A0 0.152 +16 optlc_net_187:32 optlc_net_187:31 0.006491072 +17 optlc_net_187:33 optlc_net_187:32 0.0045 +18 optlc_net_187:33 optlc_net_187:13 0.002348214 +19 optlc_net_187:31 optlc_net_187:30 0.0045 +20 optlc_net_187:30 optlc_net_187:29 0.005767858 +21 optlc_net_187:30 optlc_net_187:16 0.00390625 +22 optlc_net_187:36 optlc_net_187:35 0.0045 +23 optlc_net_187:36 optlc_net_187:8 0.01038616 +24 optlc_net_187:35 optlc_net_187:34 0.005727679 +25 optlc_net_187:18 optlc_net_187:17 9.239131e-05 +26 optlc_net_187:19 optlc_net_187:18 0.0045 +27 optlc_net_187:17 mux_bottom_track_17\/mux_l2_in_1_:A0 0.152 +28 optlc_net_187:21 optlc_net_187:20 9.510871e-05 +29 optlc_net_187:22 optlc_net_187:21 0.0045 +30 optlc_net_187:22 optlc_net_187:19 0.004816964 +31 optlc_net_187:20 mux_top_track_4\/mux_l2_in_1_:A0 0.152 +32 optlc_net_187:11 mux_right_track_18\/mux_l1_in_1_:A0 0.152 +33 optlc_net_187:37 optlc_net_187:36 0.0001465517 +34 optlc_net_187:8 mux_top_track_8\/mux_l2_in_1_:A0 0.152 +35 optlc_net_187:10 optlc_net_187:9 0.007203125 +36 optlc_net_187:34 optlc_net_187:33 0.0004107143 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001246064 //LENGTH 9.540 LUMPCC 0.0005179162 DR + +*CONN +*I mux_right_track_6\/mux_l2_in_0_:X O *L 0 *C 62.275 120.360 +*I mux_right_track_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 61.280 112.540 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 61.180 112.540 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 61.180 112.585 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 61.180 120.315 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 61.225 120.360 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 62.238 120.360 + +*CAP +0 mux_right_track_6\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_6\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.321502e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002668331 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002668331 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.963301e-05 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.963301e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chany_top_in[1]:8 6.994144e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[1] 6.994144e-05 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_2_sram[1]:9 5.397472e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_2_sram[1]:7 1.472881e-05 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_2_sram[1]:8 5.397472e-05 +12 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_2_sram[1]:6 1.472881e-05 +13 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001203131 +14 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001203131 + +*RES +0 mux_right_track_6\/mux_l2_in_0_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_6\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.006901786 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0009040179 + +*END + +*D_NET mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0] 0.006094402 //LENGTH 32.110 LUMPCC 0.003991039 DR + +*CONN +*I mux_right_track_20\/mux_l2_in_0_:X O *L 0 *C 75.265 69.360 +*I mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.255 69.495 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 103.255 69.495 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 103.040 69.360 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 103.040 69.315 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 103.040 68.058 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 103.032 68.000 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 76.368 68.000 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 76.360 68.058 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 76.360 69.315 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 76.315 69.360 +*N mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 75.303 69.360 + +*CAP +0 mux_right_track_20\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.716221e-05 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.791542e-05 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001087977 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001087977 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006923315 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0006923315 +8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 9.378193e-05 +9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 9.378193e-05 +10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 9.823193e-05 +11 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 9.823193e-05 +12 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[5]:12 0.001393089 +13 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[5]:11 0.001393089 +14 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[7] 0.0006024307 +15 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_right_in[7]:10 0.0006024307 + +*RES +0 mux_right_track_20\/mux_l2_in_0_:X mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_20\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001168478 +3 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001122768 +5 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +6 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.004177516 +8 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001122768 +10 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_right_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0009040179 + +*END + +*D_NET ropt_net_240 0.0005361112 //LENGTH 4.350 LUMPCC 0.0001225673 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 69.920 8.840 +*I ropt_mt_inst_860:A I *L 0.001766 *C 70.380 6.800 +*N ropt_net_240:2 *C 70.418 6.800 +*N ropt_net_240:3 *C 70.795 6.800 +*N ropt_net_240:4 *C 70.840 6.845 +*N ropt_net_240:5 *C 70.840 8.795 +*N ropt_net_240:6 *C 70.795 8.840 +*N ropt_net_240:7 *C 69.958 8.840 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 ropt_mt_inst_860:A 1e-06 +2 ropt_net_240:2 5.01851e-05 +3 ropt_net_240:3 5.01851e-05 +4 ropt_net_240:4 8.137135e-05 +5 ropt_net_240:5 8.137135e-05 +6 ropt_net_240:6 7.42155e-05 +7 ropt_net_240:7 7.42155e-05 +8 ropt_net_240:7 ropt_net_214:6 6.744983e-06 +9 ropt_net_240:6 ropt_net_214:5 6.744983e-06 +10 ropt_net_240:5 ropt_net_214:7 5.453866e-05 +11 ropt_net_240:4 ropt_net_214:6 5.453866e-05 + +*RES +0 ropt_mt_inst_816:X ropt_net_240:7 0.152 +1 ropt_net_240:7 ropt_net_240:6 0.0007477679 +2 ropt_net_240:6 ropt_net_240:5 0.0045 +3 ropt_net_240:5 ropt_net_240:4 0.001741072 +4 ropt_net_240:3 ropt_net_240:2 0.0003370536 +5 ropt_net_240:4 ropt_net_240:3 0.0045 +6 ropt_net_240:2 ropt_mt_inst_860:A 0.152 + +*END + +*D_NET ropt_net_219 0.001806857 //LENGTH 13.885 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_825:X O *L 0 *C 54.015 8.840 +*I ropt_mt_inst_839:A I *L 0.001766 *C 46.460 4.080 +*N ropt_net_219:2 *C 46.498 4.080 +*N ropt_net_219:3 *C 46.875 4.080 +*N ropt_net_219:4 *C 46.920 4.125 +*N ropt_net_219:5 *C 46.920 6.075 +*N ropt_net_219:6 *C 46.965 6.120 +*N ropt_net_219:7 *C 52.855 6.120 +*N ropt_net_219:8 *C 52.900 6.165 +*N ropt_net_219:9 *C 52.900 8.795 +*N ropt_net_219:10 *C 52.945 8.840 +*N ropt_net_219:11 *C 53.977 8.840 + +*CAP +0 ropt_mt_inst_825:X 1e-06 +1 ropt_mt_inst_839:A 1e-06 +2 ropt_net_219:2 5.946367e-05 +3 ropt_net_219:3 5.946367e-05 +4 ropt_net_219:4 0.0001562027 +5 ropt_net_219:5 0.0001562027 +6 ropt_net_219:6 0.0004239635 +7 ropt_net_219:7 0.0004239635 +8 ropt_net_219:8 0.0001689159 +9 ropt_net_219:9 0.0001689159 +10 ropt_net_219:10 9.388238e-05 +11 ropt_net_219:11 9.388238e-05 + +*RES +0 ropt_mt_inst_825:X ropt_net_219:11 0.152 +1 ropt_net_219:11 ropt_net_219:10 0.000921875 +2 ropt_net_219:10 ropt_net_219:9 0.0045 +3 ropt_net_219:9 ropt_net_219:8 0.002348214 +4 ropt_net_219:7 ropt_net_219:6 0.005258929 +5 ropt_net_219:8 ropt_net_219:7 0.0045 +6 ropt_net_219:6 ropt_net_219:5 0.0045 +7 ropt_net_219:5 ropt_net_219:4 0.001741071 +8 ropt_net_219:3 ropt_net_219:2 0.0003370536 +9 ropt_net_219:4 ropt_net_219:3 0.0045 +10 ropt_net_219:2 ropt_mt_inst_839:A 0.152 + +*END + +*D_NET ropt_net_224 0.001233234 //LENGTH 9.540 LUMPCC 0.0001681005 DR + +*CONN +*I ropt_mt_inst_835:X O *L 0 *C 78.840 3.400 +*I ropt_mt_inst_844:A I *L 0.001767 *C 70.380 4.080 +*N ropt_net_224:2 *C 70.380 4.080 +*N ropt_net_224:3 *C 70.380 3.400 +*N ropt_net_224:4 *C 78.803 3.400 + +*CAP +0 ropt_mt_inst_835:X 1e-06 +1 ropt_mt_inst_844:A 1e-06 +2 ropt_net_224:2 7.457194e-05 +3 ropt_net_224:3 0.0005149771 +4 ropt_net_224:4 0.0004735841 +5 ropt_net_224:4 ropt_net_214:2 7.396415e-05 +6 ropt_net_224:2 ropt_net_214:5 1.008611e-05 +7 ropt_net_224:3 ropt_net_214:3 7.396415e-05 +8 ropt_net_224:3 ropt_net_214:4 1.008611e-05 + +*RES +0 ropt_mt_inst_835:X ropt_net_224:4 0.152 +1 ropt_net_224:4 ropt_net_224:3 0.00752009 +2 ropt_net_224:2 ropt_mt_inst_844:A 0.152 +3 ropt_net_224:3 ropt_net_224:2 0.0006071429 + +*END + +*D_NET aps_rename_2_ 0.002307079 //LENGTH 22.505 LUMPCC 0.0002121103 DR + +*CONN +*I FTB_31__30:X O *L 0 *C 28.060 91.460 +*I BUFT_RR_99:A I *L 0.001766 *C 28.520 112.880 +*N aps_rename_2_:2 *C 28.483 112.880 +*N aps_rename_2_:3 *C 28.105 112.880 +*N aps_rename_2_:4 *C 28.060 112.835 +*N aps_rename_2_:5 *C 28.060 91.505 +*N aps_rename_2_:6 *C 28.060 91.460 + +*CAP +0 FTB_31__30:X 1e-06 +1 BUFT_RR_99:A 1e-06 +2 aps_rename_2_:2 3.831846e-05 +3 aps_rename_2_:3 3.831846e-05 +4 aps_rename_2_:4 0.0009933155 +5 aps_rename_2_:5 0.0009933155 +6 aps_rename_2_:6 2.970084e-05 +7 aps_rename_2_:5 chany_top_in[5]:24 0.0001060551 +8 aps_rename_2_:4 chany_top_in[5] 0.0001060551 + +*RES +0 FTB_31__30:X aps_rename_2_:6 0.152 +1 aps_rename_2_:6 aps_rename_2_:5 0.0045 +2 aps_rename_2_:5 aps_rename_2_:4 0.01904464 +3 aps_rename_2_:3 aps_rename_2_:2 0.0003370536 +4 aps_rename_2_:4 aps_rename_2_:3 0.0045 +5 aps_rename_2_:2 BUFT_RR_99:A 0.152 + +*END + +*D_NET chany_bottom_out[11] 0.001135511 //LENGTH 7.655 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_851:X O *L 0 *C 49.680 6.800 +*P chany_bottom_out[11] O *L 0.7423 *C 48.300 1.325 +*N chany_bottom_out[11]:2 *C 48.300 3.355 +*N chany_bottom_out[11]:3 *C 48.345 3.400 +*N chany_bottom_out[11]:4 *C 49.635 3.400 +*N chany_bottom_out[11]:5 *C 49.680 3.445 +*N chany_bottom_out[11]:6 *C 49.680 6.755 +*N chany_bottom_out[11]:7 *C 49.680 6.800 + +*CAP +0 ropt_mt_inst_851:X 1e-06 +1 chany_bottom_out[11] 0.000149791 +2 chany_bottom_out[11]:2 0.000149791 +3 chany_bottom_out[11]:3 0.0001257076 +4 chany_bottom_out[11]:4 0.0001257076 +5 chany_bottom_out[11]:5 0.0002749819 +6 chany_bottom_out[11]:6 0.0002749819 +7 chany_bottom_out[11]:7 3.354962e-05 + +*RES +0 ropt_mt_inst_851:X chany_bottom_out[11]:7 0.152 +1 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +2 chany_bottom_out[11]:2 chany_bottom_out[11] 0.0018125 +3 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.001151786 +4 chany_bottom_out[11]:5 chany_bottom_out[11]:4 0.0045 +5 chany_bottom_out[11]:7 chany_bottom_out[11]:6 0.0045 +6 chany_bottom_out[11]:6 chany_bottom_out[11]:5 0.002955357 + +*END + +*D_NET ropt_net_203 0.003039749 //LENGTH 25.430 LUMPCC 0.000276644 DR + +*CONN +*I BUFT_RR_79:X O *L 0 *C 38.640 18.360 +*I ropt_mt_inst_824:A I *L 0.001766 *C 37.260 4.080 +*N ropt_net_203:2 *C 37.297 4.080 +*N ropt_net_203:3 *C 40.895 4.080 +*N ropt_net_203:4 *C 40.940 4.125 +*N ropt_net_203:5 *C 40.940 11.900 +*N ropt_net_203:6 *C 42.780 11.900 +*N ropt_net_203:7 *C 42.780 16.955 +*N ropt_net_203:8 *C 42.735 17.000 +*N ropt_net_203:9 *C 40.020 17.000 +*N ropt_net_203:10 *C 40.020 18.360 +*N ropt_net_203:11 *C 38.678 18.360 + +*CAP +0 BUFT_RR_79:X 1e-06 +1 ropt_mt_inst_824:A 1e-06 +2 ropt_net_203:2 0.0001870077 +3 ropt_net_203:3 0.0001870077 +4 ropt_net_203:4 0.0003974675 +5 ropt_net_203:5 0.0004954435 +6 ropt_net_203:6 0.0004154856 +7 ropt_net_203:7 0.0003175096 +8 ropt_net_203:8 0.0002091675 +9 ropt_net_203:9 0.0002883022 +10 ropt_net_203:10 0.0001714242 +11 ropt_net_203:11 9.228945e-05 +12 ropt_net_203:3 chany_top_in[8]:7 6.358125e-05 +13 ropt_net_203:4 chany_top_in[8]:8 1.439405e-05 +14 ropt_net_203:4 chany_top_in[8]:10 3.294002e-06 +15 ropt_net_203:2 chany_top_in[8]:6 6.358125e-05 +16 ropt_net_203:5 chany_top_in[8]:9 1.439405e-05 +17 ropt_net_203:5 chany_top_in[8]:11 3.294002e-06 +18 ropt_net_203:3 ropt_net_229:7 1.539021e-05 +19 ropt_net_203:4 ropt_net_229:5 4.166249e-05 +20 ropt_net_203:2 ropt_net_229:6 1.539021e-05 +21 ropt_net_203:5 ropt_net_229:4 4.166249e-05 + +*RES +0 BUFT_RR_79:X ropt_net_203:11 0.152 +1 ropt_net_203:11 ropt_net_203:10 0.001198661 +2 ropt_net_203:8 ropt_net_203:7 0.0045 +3 ropt_net_203:7 ropt_net_203:6 0.004513393 +4 ropt_net_203:3 ropt_net_203:2 0.003212054 +5 ropt_net_203:4 ropt_net_203:3 0.0045 +6 ropt_net_203:2 ropt_mt_inst_824:A 0.152 +7 ropt_net_203:10 ropt_net_203:9 0.001214286 +8 ropt_net_203:9 ropt_net_203:8 0.002424107 +9 ropt_net_203:5 ropt_net_203:4 0.006941965 +10 ropt_net_203:6 ropt_net_203:5 0.001642857 + +*END + +*D_NET chany_top_out[15] 0.002095601 //LENGTH 15.920 LUMPCC 0 DR + +*CONN +*I BUFT_RR_96:X O *L 0 *C 44.620 116.280 +*P chany_top_out[15] O *L 0.7423 *C 46.000 129.275 +*N chany_top_out[15]:2 *C 45.600 121.720 +*N chany_top_out[15]:3 *C 46.000 121.728 +*N chany_top_out[15]:4 *C 46.000 121.720 +*N chany_top_out[15]:5 *C 46.000 121.663 +*N chany_top_out[15]:6 *C 46.000 116.325 +*N chany_top_out[15]:7 *C 45.955 116.280 +*N chany_top_out[15]:8 *C 44.657 116.280 + +*CAP +0 BUFT_RR_96:X 1e-06 +1 chany_top_out[15] 0.0005203028 +2 chany_top_out[15]:2 0.0001035976 +3 chany_top_out[15]:3 0.0005203028 +4 chany_top_out[15]:4 0.0001035976 +5 chany_top_out[15]:5 0.0003112086 +6 chany_top_out[15]:6 0.0003112086 +7 chany_top_out[15]:7 0.0001121914 +8 chany_top_out[15]:8 0.0001121914 + +*RES +0 BUFT_RR_96:X chany_top_out[15]:8 0.152 +1 chany_top_out[15]:8 chany_top_out[15]:7 0.001158482 +2 chany_top_out[15]:7 chany_top_out[15]:6 0.0045 +3 chany_top_out[15]:6 chany_top_out[15]:5 0.004765625 +4 chany_top_out[15]:5 chany_top_out[15]:4 0.00341 +5 chany_top_out[15]:4 chany_top_out[15]:3 0.00341 +6 chany_top_out[15]:4 chany_top_out[15]:2 5.69697e-05 +7 chany_top_out[15]:3 chany_top_out[15] 0.001182442 + +*END + +*D_NET chany_top_out[7] 0.001018424 //LENGTH 8.805 LUMPCC 0 DR + +*CONN +*I BUFT_P_139:X O *L 0 *C 66.240 127.160 +*P chany_top_out[7] O *L 0.7423 *C 69.000 129.275 +*N chany_top_out[7]:2 *C 69.000 128.528 +*N chany_top_out[7]:3 *C 68.980 128.520 +*N chany_top_out[7]:4 *C 64.868 128.520 +*N chany_top_out[7]:5 *C 64.860 128.463 +*N chany_top_out[7]:6 *C 64.860 127.205 +*N chany_top_out[7]:7 *C 64.905 127.160 +*N chany_top_out[7]:8 *C 66.203 127.160 + +*CAP +0 BUFT_P_139:X 1e-06 +1 chany_top_out[7] 6.52389e-05 +2 chany_top_out[7]:2 6.52389e-05 +3 chany_top_out[7]:3 0.0002516196 +4 chany_top_out[7]:4 0.0002516196 +5 chany_top_out[7]:5 8.174736e-05 +6 chany_top_out[7]:6 8.174736e-05 +7 chany_top_out[7]:7 0.0001101063 +8 chany_top_out[7]:8 0.0001101063 + +*RES +0 BUFT_P_139:X chany_top_out[7]:8 0.152 +1 chany_top_out[7]:8 chany_top_out[7]:7 0.001158482 +2 chany_top_out[7]:7 chany_top_out[7]:6 0.0045 +3 chany_top_out[7]:6 chany_top_out[7]:5 0.001122768 +4 chany_top_out[7]:5 chany_top_out[7]:4 0.00341 +5 chany_top_out[7]:4 chany_top_out[7]:3 0.0006442916 +6 chany_top_out[7]:3 chany_top_out[7]:2 0.00341 +7 chany_top_out[7]:2 chany_top_out[7] 0.0001171083 + +*END + +*D_NET chany_top_in[18] 0.01956621 //LENGTH 164.485 LUMPCC 0.003027349 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 44.160 129.350 +*I BUFT_P_158:A I *L 0.001767 *C 33.580 6.800 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 31.645 63.580 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 54.425 47.940 +*N chany_top_in[18]:4 *C 54.388 47.940 +*N chany_top_in[18]:5 *C 48.805 47.940 +*N chany_top_in[18]:6 *C 48.760 47.985 +*N chany_top_in[18]:7 *C 48.760 55.703 +*N chany_top_in[18]:8 *C 48.753 55.760 +*N chany_top_in[18]:9 *C 31.645 63.580 +*N chany_top_in[18]:10 *C 31.740 63.535 +*N chany_top_in[18]:11 *C 33.543 6.800 +*N chany_top_in[18]:12 *C 31.785 6.800 +*N chany_top_in[18]:13 *C 31.740 6.845 +*N chany_top_in[18]:14 *C 31.740 55.760 +*N chany_top_in[18]:15 *C 31.748 55.760 +*N chany_top_in[18]:16 *C 44.160 55.760 +*N chany_top_in[18]:17 *C 44.160 55.768 +*N chany_top_in[18]:18 *C 44.160 105.595 + +*CAP +0 chany_top_in[18] 0.001424432 +1 BUFT_P_158:A 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[18]:4 0.0002236084 +5 chany_top_in[18]:5 0.0002236084 +6 chany_top_in[18]:6 0.0004184735 +7 chany_top_in[18]:7 0.0004184735 +8 chany_top_in[18]:8 0.0001877716 +9 chany_top_in[18]:9 2.807517e-05 +10 chany_top_in[18]:10 0.0003240185 +11 chany_top_in[18]:11 0.0001138328 +12 chany_top_in[18]:12 0.0001138328 +13 chany_top_in[18]:13 0.001976921 +14 chany_top_in[18]:14 0.002334726 +15 chany_top_in[18]:15 0.0005780195 +16 chany_top_in[18]:16 0.0007657912 +17 chany_top_in[18]:17 0.002989925 +18 chany_top_in[18]:18 0.004414357 +19 chany_top_in[18]:13 chany_bottom_in[11] 0.000308249 +20 chany_top_in[18]:14 chany_bottom_in[11]:19 0.000308249 +21 chany_top_in[18]:8 chany_bottom_in[13]:21 0.0002624447 +22 chany_top_in[18]:15 chany_bottom_in[13]:20 0.0005107663 +23 chany_top_in[18]:16 chany_bottom_in[13]:20 0.0002624447 +24 chany_top_in[18]:16 chany_bottom_in[13]:21 0.0005107663 +25 chany_top_in[18]:5 mux_tree_tapbuf_size5_4_sram[1]:9 0.0002214312 +26 chany_top_in[18]:4 mux_tree_tapbuf_size5_4_sram[1]:10 0.0002214312 +27 chany_top_in[18]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.869396e-05 +28 chany_top_in[18]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.869396e-05 +29 chany_top_in[18]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.659655e-05 +30 chany_top_in[18]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.729878e-05 +31 chany_top_in[18]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.659655e-05 +32 chany_top_in[18]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.729878e-05 +33 chany_top_in[18]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.819413e-05 +34 chany_top_in[18]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.819413e-05 + +*RES +0 chany_top_in[18] chany_top_in[18]:18 0.003721616 +1 chany_top_in[18]:12 chany_top_in[18]:11 0.001569197 +2 chany_top_in[18]:13 chany_top_in[18]:12 0.0045 +3 chany_top_in[18]:11 BUFT_P_158:A 0.152 +4 chany_top_in[18]:7 chany_top_in[18]:6 0.006890625 +5 chany_top_in[18]:8 chany_top_in[18]:7 0.00341 +6 chany_top_in[18]:5 chany_top_in[18]:4 0.004984376 +7 chany_top_in[18]:6 chany_top_in[18]:5 0.0045 +8 chany_top_in[18]:4 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +9 chany_top_in[18]:14 chany_top_in[18]:13 0.04367411 +10 chany_top_in[18]:14 chany_top_in[18]:10 0.006941965 +11 chany_top_in[18]:15 chany_top_in[18]:14 0.00341 +12 chany_top_in[18]:16 chany_top_in[18]:15 0.001944625 +13 chany_top_in[18]:16 chany_top_in[18]:8 0.0007194916 +14 chany_top_in[18]:17 chany_top_in[18]:16 0.00341 +15 chany_top_in[18]:9 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[18]:10 chany_top_in[18]:9 0.0045 +17 chany_top_in[18]:18 chany_top_in[18]:17 0.007806308 + +*END + +*D_NET right_top_grid_pin_48_[0] 0.008963928 //LENGTH 74.170 LUMPCC 0.0002184444 DR + +*CONN +*P right_top_grid_pin_48_[0] I *L 0.29796 *C 107.180 102.070 +*I mux_right_track_20\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.890 71.740 +*I mux_right_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 78.490 98.600 +*I mux_right_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 82.440 94.180 +*N right_top_grid_pin_48_[0]:4 *C 82.403 94.180 +*N right_top_grid_pin_48_[0]:5 *C 81.880 94.180 +*N right_top_grid_pin_48_[0]:6 *C 78.490 98.600 +*N right_top_grid_pin_48_[0]:7 *C 78.660 98.600 +*N right_top_grid_pin_48_[0]:8 *C 78.660 98.555 +*N right_top_grid_pin_48_[0]:9 *C 78.660 93.935 +*N right_top_grid_pin_48_[0]:10 *C 73.890 71.740 +*N right_top_grid_pin_48_[0]:11 *C 73.600 71.740 +*N right_top_grid_pin_48_[0]:12 *C 73.600 71.785 +*N right_top_grid_pin_48_[0]:13 *C 73.600 74.460 +*N right_top_grid_pin_48_[0]:14 *C 73.140 74.460 +*N right_top_grid_pin_48_[0]:15 *C 73.140 89.023 +*N right_top_grid_pin_48_[0]:16 *C 73.148 89.080 +*N right_top_grid_pin_48_[0]:17 *C 78.193 89.080 +*N right_top_grid_pin_48_[0]:18 *C 78.200 89.138 +*N right_top_grid_pin_48_[0]:19 *C 78.200 93.500 +*N right_top_grid_pin_48_[0]:20 *C 78.615 93.500 +*N right_top_grid_pin_48_[0]:21 *C 78.660 93.965 +*N right_top_grid_pin_48_[0]:22 *C 78.705 93.840 +*N right_top_grid_pin_48_[0]:23 *C 81.880 93.840 +*N right_top_grid_pin_48_[0]:24 *C 88.275 93.840 +*N right_top_grid_pin_48_[0]:25 *C 88.320 93.885 +*N right_top_grid_pin_48_[0]:26 *C 88.320 96.175 +*N right_top_grid_pin_48_[0]:27 *C 88.365 96.220 +*N right_top_grid_pin_48_[0]:28 *C 107.135 96.220 +*N right_top_grid_pin_48_[0]:29 *C 107.180 96.265 + +*CAP +0 right_top_grid_pin_48_[0] 0.0003125301 +1 mux_right_track_20\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_4\/mux_l1_in_2_:A0 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_48_[0]:4 6.129345e-05 +5 right_top_grid_pin_48_[0]:5 8.911006e-05 +6 right_top_grid_pin_48_[0]:6 5.300574e-05 +7 right_top_grid_pin_48_[0]:7 5.770536e-05 +8 right_top_grid_pin_48_[0]:8 0.0003116564 +9 right_top_grid_pin_48_[0]:9 1.798944e-05 +10 right_top_grid_pin_48_[0]:10 5.776282e-05 +11 right_top_grid_pin_48_[0]:11 6.201342e-05 +12 right_top_grid_pin_48_[0]:12 0.0001961729 +13 right_top_grid_pin_48_[0]:13 0.0002260513 +14 right_top_grid_pin_48_[0]:14 0.0008186906 +15 right_top_grid_pin_48_[0]:15 0.0007888122 +16 right_top_grid_pin_48_[0]:16 0.0004127502 +17 right_top_grid_pin_48_[0]:17 0.0004127502 +18 right_top_grid_pin_48_[0]:18 0.0002611548 +19 right_top_grid_pin_48_[0]:19 0.0002924254 +20 right_top_grid_pin_48_[0]:20 5.964767e-05 +21 right_top_grid_pin_48_[0]:21 0.0003580229 +22 right_top_grid_pin_48_[0]:22 0.0002623364 +23 right_top_grid_pin_48_[0]:23 0.0006043446 +24 right_top_grid_pin_48_[0]:24 0.0003141915 +25 right_top_grid_pin_48_[0]:25 0.0001478204 +26 right_top_grid_pin_48_[0]:26 0.0001478204 +27 right_top_grid_pin_48_[0]:27 0.001051947 +28 right_top_grid_pin_48_[0]:28 0.001051947 +29 right_top_grid_pin_48_[0]:29 0.0003125301 +30 right_top_grid_pin_48_[0]:27 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 4.47612e-05 +31 right_top_grid_pin_48_[0]:28 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 4.47612e-05 +32 right_top_grid_pin_48_[0]:24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.446099e-05 +33 right_top_grid_pin_48_[0]:23 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.446099e-05 + +*RES +0 right_top_grid_pin_48_[0] right_top_grid_pin_48_[0]:29 0.005183036 +1 right_top_grid_pin_48_[0]:22 right_top_grid_pin_48_[0]:21 0.0045 +2 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:20 0.000290625 +3 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:9 1.875e-05 +4 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:8 0.004098215 +5 right_top_grid_pin_48_[0]:7 right_top_grid_pin_48_[0]:6 9.239131e-05 +6 right_top_grid_pin_48_[0]:8 right_top_grid_pin_48_[0]:7 0.0045 +7 right_top_grid_pin_48_[0]:6 mux_right_track_4\/mux_l1_in_2_:A0 0.152 +8 right_top_grid_pin_48_[0]:18 right_top_grid_pin_48_[0]:17 0.00341 +9 right_top_grid_pin_48_[0]:17 right_top_grid_pin_48_[0]:16 0.0007903833 +10 right_top_grid_pin_48_[0]:15 right_top_grid_pin_48_[0]:14 0.01300223 +11 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:15 0.00341 +12 right_top_grid_pin_48_[0]:11 right_top_grid_pin_48_[0]:10 0.0001576087 +13 right_top_grid_pin_48_[0]:12 right_top_grid_pin_48_[0]:11 0.0045 +14 right_top_grid_pin_48_[0]:10 mux_right_track_20\/mux_l1_in_0_:A0 0.152 +15 right_top_grid_pin_48_[0]:4 mux_right_track_0\/mux_l1_in_2_:A1 0.152 +16 right_top_grid_pin_48_[0]:24 right_top_grid_pin_48_[0]:23 0.005709821 +17 right_top_grid_pin_48_[0]:25 right_top_grid_pin_48_[0]:24 0.0045 +18 right_top_grid_pin_48_[0]:27 right_top_grid_pin_48_[0]:26 0.0045 +19 right_top_grid_pin_48_[0]:26 right_top_grid_pin_48_[0]:25 0.002044643 +20 right_top_grid_pin_48_[0]:28 right_top_grid_pin_48_[0]:27 0.01675893 +21 right_top_grid_pin_48_[0]:29 right_top_grid_pin_48_[0]:28 0.0045 +22 right_top_grid_pin_48_[0]:23 right_top_grid_pin_48_[0]:22 0.002834822 +23 right_top_grid_pin_48_[0]:23 right_top_grid_pin_48_[0]:5 0.0003035715 +24 right_top_grid_pin_48_[0]:5 right_top_grid_pin_48_[0]:4 0.0004665179 +25 right_top_grid_pin_48_[0]:14 right_top_grid_pin_48_[0]:13 0.0004107143 +26 right_top_grid_pin_48_[0]:13 right_top_grid_pin_48_[0]:12 0.002388393 +27 right_top_grid_pin_48_[0]:19 right_top_grid_pin_48_[0]:18 0.00389509 +28 right_top_grid_pin_48_[0]:20 right_top_grid_pin_48_[0]:19 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[1] 0.001733712 //LENGTH 14.925 LUMPCC 0.0002115336 DR + +*CONN +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.025 75.140 +*I mem_right_track_22\/FTB_26__56:A I *L 0.001746 *C 56.580 69.360 +*I mux_right_track_22\/mux_l2_in_0_:S I *L 0.00357 *C 59.220 77.860 +*N mux_tree_tapbuf_size3_3_sram[1]:3 *C 59.220 77.860 +*N mux_tree_tapbuf_size3_3_sram[1]:4 *C 59.340 77.815 +*N mux_tree_tapbuf_size3_3_sram[1]:5 *C 56.617 69.360 +*N mux_tree_tapbuf_size3_3_sram[1]:6 *C 59.295 69.360 +*N mux_tree_tapbuf_size3_3_sram[1]:7 *C 59.340 69.405 +*N mux_tree_tapbuf_size3_3_sram[1]:8 *C 59.340 74.460 +*N mux_tree_tapbuf_size3_3_sram[1]:9 *C 59.800 74.460 +*N mux_tree_tapbuf_size3_3_sram[1]:10 *C 59.800 75.095 +*N mux_tree_tapbuf_size3_3_sram[1]:11 *C 59.845 75.140 +*N mux_tree_tapbuf_size3_3_sram[1]:12 *C 60.988 75.140 + +*CAP +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_22\/FTB_26__56:A 1e-06 +2 mux_right_track_22\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_3_sram[1]:3 2.864879e-05 +4 mux_tree_tapbuf_size3_3_sram[1]:4 0.0001370989 +5 mux_tree_tapbuf_size3_3_sram[1]:5 0.0001956568 +6 mux_tree_tapbuf_size3_3_sram[1]:6 0.0001956568 +7 mux_tree_tapbuf_size3_3_sram[1]:7 0.0002390651 +8 mux_tree_tapbuf_size3_3_sram[1]:8 0.0004054576 +9 mux_tree_tapbuf_size3_3_sram[1]:9 8.782792e-05 +10 mux_tree_tapbuf_size3_3_sram[1]:10 5.853434e-05 +11 mux_tree_tapbuf_size3_3_sram[1]:11 8.561598e-05 +12 mux_tree_tapbuf_size3_3_sram[1]:12 8.561598e-05 +13 mux_tree_tapbuf_size3_3_sram[1]:4 chanx_right_in[14]:10 4.14426e-05 +14 mux_tree_tapbuf_size3_3_sram[1]:7 chanx_right_in[14]:9 6.432418e-05 +15 mux_tree_tapbuf_size3_3_sram[1]:8 chanx_right_in[14]:9 4.14426e-05 +16 mux_tree_tapbuf_size3_3_sram[1]:8 chanx_right_in[14]:10 6.432418e-05 + +*RES +0 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_3_sram[1]:12 0.152 +1 mux_tree_tapbuf_size3_3_sram[1]:3 mux_right_track_22\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_3_sram[1]:4 mux_tree_tapbuf_size3_3_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size3_3_sram[1]:5 mem_right_track_22\/FTB_26__56:A 0.152 +4 mux_tree_tapbuf_size3_3_sram[1]:6 mux_tree_tapbuf_size3_3_sram[1]:5 0.002390625 +5 mux_tree_tapbuf_size3_3_sram[1]:7 mux_tree_tapbuf_size3_3_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size3_3_sram[1]:11 mux_tree_tapbuf_size3_3_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size3_3_sram[1]:10 mux_tree_tapbuf_size3_3_sram[1]:9 0.0005669644 +8 mux_tree_tapbuf_size3_3_sram[1]:12 mux_tree_tapbuf_size3_3_sram[1]:11 0.001020089 +9 mux_tree_tapbuf_size3_3_sram[1]:8 mux_tree_tapbuf_size3_3_sram[1]:7 0.004513393 +10 mux_tree_tapbuf_size3_3_sram[1]:8 mux_tree_tapbuf_size3_3_sram[1]:4 0.002995536 +11 mux_tree_tapbuf_size3_3_sram[1]:9 mux_tree_tapbuf_size3_3_sram[1]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size4_5_sram[1] 0.001913297 //LENGTH 14.115 LUMPCC 0 DR + +*CONN +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 76.665 88.060 +*I mux_right_track_14\/mux_l2_in_1_:S I *L 0.00357 *C 80.400 82.960 +*I mux_right_track_14\/mux_l2_in_0_:S I *L 0.00357 *C 79.020 90.440 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 79.755 88.060 +*N mux_tree_tapbuf_size4_5_sram[1]:4 *C 79.718 88.060 +*N mux_tree_tapbuf_size4_5_sram[1]:5 *C 79.020 90.440 +*N mux_tree_tapbuf_size4_5_sram[1]:6 *C 79.120 90.395 +*N mux_tree_tapbuf_size4_5_sram[1]:7 *C 80.362 82.960 +*N mux_tree_tapbuf_size4_5_sram[1]:8 *C 78.705 82.960 +*N mux_tree_tapbuf_size4_5_sram[1]:9 *C 78.660 83.005 +*N mux_tree_tapbuf_size4_5_sram[1]:10 *C 78.660 88.060 +*N mux_tree_tapbuf_size4_5_sram[1]:11 *C 79.120 88.105 +*N mux_tree_tapbuf_size4_5_sram[1]:12 *C 79.120 88.060 +*N mux_tree_tapbuf_size4_5_sram[1]:13 *C 76.703 88.060 + +*CAP +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_14\/mux_l2_in_1_:S 1e-06 +2 mux_right_track_14\/mux_l2_in_0_:S 1e-06 +3 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size4_5_sram[1]:4 4.893206e-05 +5 mux_tree_tapbuf_size4_5_sram[1]:5 2.830344e-05 +6 mux_tree_tapbuf_size4_5_sram[1]:6 0.0001853764 +7 mux_tree_tapbuf_size4_5_sram[1]:7 0.0001579267 +8 mux_tree_tapbuf_size4_5_sram[1]:8 0.0001579267 +9 mux_tree_tapbuf_size4_5_sram[1]:9 0.0003359155 +10 mux_tree_tapbuf_size4_5_sram[1]:10 0.0003685878 +11 mux_tree_tapbuf_size4_5_sram[1]:11 0.0002180486 +12 mux_tree_tapbuf_size4_5_sram[1]:12 0.0002451725 +13 mux_tree_tapbuf_size4_5_sram[1]:13 0.0001631069 + +*RES +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_5_sram[1]:13 0.152 +1 mux_tree_tapbuf_size4_5_sram[1]:12 mux_tree_tapbuf_size4_5_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size4_5_sram[1]:12 mux_tree_tapbuf_size4_5_sram[1]:4 0.0005334822 +3 mux_tree_tapbuf_size4_5_sram[1]:11 mux_tree_tapbuf_size4_5_sram[1]:10 0.0004107143 +4 mux_tree_tapbuf_size4_5_sram[1]:11 mux_tree_tapbuf_size4_5_sram[1]:6 0.002044643 +5 mux_tree_tapbuf_size4_5_sram[1]:5 mux_right_track_14\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size4_5_sram[1]:6 mux_tree_tapbuf_size4_5_sram[1]:5 0.0045 +7 mux_tree_tapbuf_size4_5_sram[1]:8 mux_tree_tapbuf_size4_5_sram[1]:7 0.001479911 +8 mux_tree_tapbuf_size4_5_sram[1]:9 mux_tree_tapbuf_size4_5_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size4_5_sram[1]:7 mux_right_track_14\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size4_5_sram[1]:4 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size4_5_sram[1]:13 mux_tree_tapbuf_size4_5_sram[1]:12 0.002158482 +12 mux_tree_tapbuf_size4_5_sram[1]:10 mux_tree_tapbuf_size4_5_sram[1]:9 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[0] 0.005450826 //LENGTH 42.380 LUMPCC 0.0006525792 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 64.705 20.740 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 56.755 42.500 +*I mux_bottom_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 70.940 45.220 +*I mux_bottom_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 68.440 41.870 +*N mux_tree_tapbuf_size5_2_sram[0]:4 *C 68.440 41.870 +*N mux_tree_tapbuf_size5_2_sram[0]:5 *C 68.398 42.130 +*N mux_tree_tapbuf_size5_2_sram[0]:6 *C 70.903 45.220 +*N mux_tree_tapbuf_size5_2_sram[0]:7 *C 68.125 45.220 +*N mux_tree_tapbuf_size5_2_sram[0]:8 *C 68.080 45.175 +*N mux_tree_tapbuf_size5_2_sram[0]:9 *C 68.080 42.205 +*N mux_tree_tapbuf_size5_2_sram[0]:10 *C 68.110 42.130 +*N mux_tree_tapbuf_size5_2_sram[0]:11 *C 64.400 42.160 +*N mux_tree_tapbuf_size5_2_sram[0]:12 *C 56.793 42.500 +*N mux_tree_tapbuf_size5_2_sram[0]:13 *C 64.400 42.470 +*N mux_tree_tapbuf_size5_2_sram[0]:14 *C 64.400 42.455 +*N mux_tree_tapbuf_size5_2_sram[0]:15 *C 64.400 20.785 +*N mux_tree_tapbuf_size5_2_sram[0]:16 *C 64.400 20.740 +*N mux_tree_tapbuf_size5_2_sram[0]:17 *C 64.705 20.740 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_3\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_track_3\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_2_sram[0]:4 6.077288e-05 +5 mux_tree_tapbuf_size5_2_sram[0]:5 7.693794e-05 +6 mux_tree_tapbuf_size5_2_sram[0]:6 0.0001468665 +7 mux_tree_tapbuf_size5_2_sram[0]:7 0.0001468665 +8 mux_tree_tapbuf_size5_2_sram[0]:8 0.0002181621 +9 mux_tree_tapbuf_size5_2_sram[0]:9 0.0002181621 +10 mux_tree_tapbuf_size5_2_sram[0]:10 0.0003212102 +11 mux_tree_tapbuf_size5_2_sram[0]:11 0.0003094613 +12 mux_tree_tapbuf_size5_2_sram[0]:12 0.0005250554 +13 mux_tree_tapbuf_size5_2_sram[0]:13 0.0005605664 +14 mux_tree_tapbuf_size5_2_sram[0]:14 0.001058875 +15 mux_tree_tapbuf_size5_2_sram[0]:15 0.001058875 +16 mux_tree_tapbuf_size5_2_sram[0]:16 4.839651e-05 +17 mux_tree_tapbuf_size5_2_sram[0]:17 4.403816e-05 +18 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[2]:9 4.274323e-05 +19 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[2]:5 0.0001687529 +20 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_2_sram[2]:4 0.0001687529 +21 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_2_sram[2]:8 4.274323e-05 +22 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 4.403792e-05 +23 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 4.403792e-05 +24 mux_tree_tapbuf_size5_2_sram[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.075554e-05 +25 mux_tree_tapbuf_size5_2_sram[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.075554e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_2_sram[0]:17 0.152 +1 mux_tree_tapbuf_size5_2_sram[0]:6 mux_bottom_track_3\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size5_2_sram[0]:7 mux_tree_tapbuf_size5_2_sram[0]:6 0.002479911 +3 mux_tree_tapbuf_size5_2_sram[0]:8 mux_tree_tapbuf_size5_2_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size5_2_sram[0]:10 mux_tree_tapbuf_size5_2_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size5_2_sram[0]:10 mux_tree_tapbuf_size5_2_sram[0]:5 0.0001796875 +6 mux_tree_tapbuf_size5_2_sram[0]:9 mux_tree_tapbuf_size5_2_sram[0]:8 0.002651786 +7 mux_tree_tapbuf_size5_2_sram[0]:13 mux_tree_tapbuf_size5_2_sram[0]:12 0.006792411 +8 mux_tree_tapbuf_size5_2_sram[0]:13 mux_tree_tapbuf_size5_2_sram[0]:11 0.0002767857 +9 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size5_2_sram[0]:16 mux_tree_tapbuf_size5_2_sram[0]:15 0.0045 +11 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_2_sram[0]:14 0.01934822 +12 mux_tree_tapbuf_size5_2_sram[0]:17 mux_tree_tapbuf_size5_2_sram[0]:16 0.0001657609 +13 mux_tree_tapbuf_size5_2_sram[0]:12 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size5_2_sram[0]:4 mux_bottom_track_3\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size5_2_sram[0]:11 mux_tree_tapbuf_size5_2_sram[0]:10 0.0033125 +16 mux_tree_tapbuf_size5_2_sram[0]:5 mux_tree_tapbuf_size5_2_sram[0]:4 0.0001511628 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[0] 0.003852902 //LENGTH 31.015 LUMPCC 0.0002260647 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 78.965 63.920 +*I mux_top_track_8\/mux_l1_in_2_:S I *L 0.00357 *C 67.740 58.140 +*I mux_top_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 69.560 56.440 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.495 66.300 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 71.400 61.495 +*N mux_tree_tapbuf_size6_2_sram[0]:5 *C 71.400 61.495 +*N mux_tree_tapbuf_size6_2_sram[0]:6 *C 65.532 66.300 +*N mux_tree_tapbuf_size6_2_sram[0]:7 *C 69.875 66.300 +*N mux_tree_tapbuf_size6_2_sram[0]:8 *C 69.920 66.255 +*N mux_tree_tapbuf_size6_2_sram[0]:9 *C 69.460 56.440 +*N mux_tree_tapbuf_size6_2_sram[0]:10 *C 69.460 56.485 +*N mux_tree_tapbuf_size6_2_sram[0]:11 *C 67.778 58.140 +*N mux_tree_tapbuf_size6_2_sram[0]:12 *C 69.415 58.140 +*N mux_tree_tapbuf_size6_2_sram[0]:13 *C 69.460 58.140 +*N mux_tree_tapbuf_size6_2_sram[0]:14 *C 69.920 58.140 +*N mux_tree_tapbuf_size6_2_sram[0]:15 *C 69.920 61.200 +*N mux_tree_tapbuf_size6_2_sram[0]:16 *C 69.965 61.200 +*N mux_tree_tapbuf_size6_2_sram[0]:17 *C 71.400 61.200 +*N mux_tree_tapbuf_size6_2_sram[0]:18 *C 77.695 61.200 +*N mux_tree_tapbuf_size6_2_sram[0]:19 *C 77.740 61.245 +*N mux_tree_tapbuf_size6_2_sram[0]:20 *C 77.740 63.875 +*N mux_tree_tapbuf_size6_2_sram[0]:21 *C 77.785 63.920 +*N mux_tree_tapbuf_size6_2_sram[0]:22 *C 78.928 63.920 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_8\/mux_l1_in_2_:S 1e-06 +2 mux_top_track_8\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_2_sram[0]:5 6.353023e-05 +6 mux_tree_tapbuf_size6_2_sram[0]:6 0.0002977965 +7 mux_tree_tapbuf_size6_2_sram[0]:7 0.0002977965 +8 mux_tree_tapbuf_size6_2_sram[0]:8 0.0002568663 +9 mux_tree_tapbuf_size6_2_sram[0]:9 3.608462e-05 +10 mux_tree_tapbuf_size6_2_sram[0]:10 7.230246e-05 +11 mux_tree_tapbuf_size6_2_sram[0]:11 0.0001127505 +12 mux_tree_tapbuf_size6_2_sram[0]:12 0.0001127505 +13 mux_tree_tapbuf_size6_2_sram[0]:13 0.0001072633 +14 mux_tree_tapbuf_size6_2_sram[0]:14 0.0001834628 +15 mux_tree_tapbuf_size6_2_sram[0]:15 0.0004379721 +16 mux_tree_tapbuf_size6_2_sram[0]:16 0.0001049223 +17 mux_tree_tapbuf_size6_2_sram[0]:17 0.0005711163 +18 mux_tree_tapbuf_size6_2_sram[0]:18 0.000433753 +19 mux_tree_tapbuf_size6_2_sram[0]:19 0.0001699743 +20 mux_tree_tapbuf_size6_2_sram[0]:20 0.0001699743 +21 mux_tree_tapbuf_size6_2_sram[0]:21 9.676057e-05 +22 mux_tree_tapbuf_size6_2_sram[0]:22 9.676057e-05 +23 mux_tree_tapbuf_size6_2_sram[0]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.40982e-05 +24 mux_tree_tapbuf_size6_2_sram[0]:15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.299482e-05 +25 mux_tree_tapbuf_size6_2_sram[0]:15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.593932e-05 +26 mux_tree_tapbuf_size6_2_sram[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.593932e-05 +27 mux_tree_tapbuf_size6_2_sram[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.40982e-05 +28 mux_tree_tapbuf_size6_2_sram[0]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.299482e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_2_sram[0]:22 0.152 +1 mux_tree_tapbuf_size6_2_sram[0]:11 mux_top_track_8\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:11 0.001462054 +3 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:10 0.001477679 +5 mux_tree_tapbuf_size6_2_sram[0]:18 mux_tree_tapbuf_size6_2_sram[0]:17 0.005620536 +6 mux_tree_tapbuf_size6_2_sram[0]:19 mux_tree_tapbuf_size6_2_sram[0]:18 0.0045 +7 mux_tree_tapbuf_size6_2_sram[0]:21 mux_tree_tapbuf_size6_2_sram[0]:20 0.0045 +8 mux_tree_tapbuf_size6_2_sram[0]:20 mux_tree_tapbuf_size6_2_sram[0]:19 0.002348214 +9 mux_tree_tapbuf_size6_2_sram[0]:22 mux_tree_tapbuf_size6_2_sram[0]:21 0.001020089 +10 mux_tree_tapbuf_size6_2_sram[0]:16 mux_tree_tapbuf_size6_2_sram[0]:15 0.0045 +11 mux_tree_tapbuf_size6_2_sram[0]:15 mux_tree_tapbuf_size6_2_sram[0]:14 0.002732143 +12 mux_tree_tapbuf_size6_2_sram[0]:15 mux_tree_tapbuf_size6_2_sram[0]:8 0.004513393 +13 mux_tree_tapbuf_size6_2_sram[0]:7 mux_tree_tapbuf_size6_2_sram[0]:6 0.003877232 +14 mux_tree_tapbuf_size6_2_sram[0]:8 mux_tree_tapbuf_size6_2_sram[0]:7 0.0045 +15 mux_tree_tapbuf_size6_2_sram[0]:6 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size6_2_sram[0]:9 mux_top_track_8\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size6_2_sram[0]:10 mux_tree_tapbuf_size6_2_sram[0]:9 0.0045 +18 mux_tree_tapbuf_size6_2_sram[0]:5 mux_top_track_8\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size6_2_sram[0]:17 mux_tree_tapbuf_size6_2_sram[0]:16 0.00128125 +20 mux_tree_tapbuf_size6_2_sram[0]:17 mux_tree_tapbuf_size6_2_sram[0]:5 0.0001271552 +21 mux_tree_tapbuf_size6_2_sram[0]:14 mux_tree_tapbuf_size6_2_sram[0]:13 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_4_ccff_tail[0] 0.000470624 //LENGTH 3.250 LUMPCC 0.0001081412 DR + +*CONN +*I mem_bottom_track_1\/FTB_5__35:X O *L 0 *C 58.195 22.440 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 59.055 20.740 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 *C 59.018 20.740 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 *C 58.465 20.740 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 *C 58.420 20.785 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 *C 58.420 22.395 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 *C 58.420 22.440 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 *C 58.195 22.440 + +*CAP +0 mem_bottom_track_1\/FTB_5__35:X 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 5.742028e-05 +3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 5.742028e-05 +4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 6.925751e-05 +5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 6.925751e-05 +6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 5.269667e-05 +7 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 5.443052e-05 +8 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 prog_clk[0]:428 5.407059e-05 +9 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 prog_clk[0]:429 5.407059e-05 + +*RES +0 mem_bottom_track_1\/FTB_5__35:X mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_1_ccff_tail[0] 0.0006571267 //LENGTH 4.780 LUMPCC 0.000107293 DR + +*CONN +*I mem_right_track_4\/FTB_21__51:X O *L 0 *C 60.485 105.060 +*I mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 59.055 107.780 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 *C 59.055 107.780 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 *C 59.340 107.780 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 *C 59.340 107.735 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 *C 59.340 105.105 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 *C 59.385 105.060 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 *C 60.448 105.060 + +*CAP +0 mem_right_track_4\/FTB_21__51:X 1e-06 +1 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 5.28764e-05 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 5.473764e-05 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.0001688998 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0001688998 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 5.120999e-05 +7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 5.120999e-05 +8 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 chany_top_in[7]:3 5.364652e-05 +9 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 chany_top_in[7]:4 5.364652e-05 + +*RES +0 mem_right_track_4\/FTB_21__51:X mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mem_right_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 0.0009486608 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.009444103 //LENGTH 69.460 LUMPCC 0.00431615 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_0_:X O *L 0 *C 79.755 61.200 +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 76.965 126.295 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 77.002 126.225 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 77.250 126.170 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 77.280 126.095 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 77.280 122.458 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 77.288 122.400 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 78.180 122.400 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 78.200 122.393 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 78.200 111.035 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 78.200 61.208 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 78.220 61.200 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 79.573 61.200 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 79.580 61.200 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 79.580 61.200 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 79.755 61.200 + +*CAP +0 mux_top_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.875522e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.875522e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002041305 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002041305 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.941105e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.941105e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002472914 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.00202525 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.001777958 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0001746338 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0001746338 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:13 3.62468e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:14 5.434949e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:15 5.099477e-05 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 chany_top_in[2]:23 0.0006206616 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 chany_top_in[2]:30 5.242409e-06 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[2]:24 0.0006206616 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[2]:31 5.242409e-06 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 chany_bottom_in[4]:13 9.369855e-05 +21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 chany_bottom_in[4]:32 0.0001597759 +22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[4]:12 0.0002314745 +23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_bottom_in[4]:12 9.369855e-05 +24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_bottom_in[4]:13 0.0002314745 +25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_bottom_in[4]:25 0.0001597759 +26 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 right_top_grid_pin_45_[0]:12 0.0004186737 +27 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 right_top_grid_pin_45_[0]:11 0.0002122458 +28 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 right_top_grid_pin_45_[0]:11 0.0004186737 +29 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 right_top_grid_pin_45_[0]:12 0.0002122458 +30 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.000269753 +31 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.889261e-05 +32 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001176572 +33 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.889261e-05 +34 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000269753 +35 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001176572 + +*RES +0 mux_top_track_4\/mux_l3_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:14 9.51087e-05 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.00341 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0002118916 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.00341 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.007806308 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000139825 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003247768 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001546875 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.001779342 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007893768 //LENGTH 7.100 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_1_:X O *L 0 *C 94.935 48.280 +*I mux_top_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 96.005 53.380 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 95.990 53.380 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 95.703 53.380 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 95.680 53.335 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 95.680 48.325 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 95.635 48.280 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 94.973 48.280 + +*CAP +0 mux_top_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.592279e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.592279e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002722519 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002722519 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.55137e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.55137e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00015625 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 + +*END + +*D_NET optlc_net_186 0.01013447 //LENGTH 76.183 LUMPCC 0.0002925939 DR + +*CONN +*I optlc_177:HI O *L 0 *C 75.900 96.560 +*I mux_right_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 90.335 91.800 +*I mux_right_track_14\/mux_l2_in_1_:A0 I *L 0.001631 *C 79.295 82.280 +*I mux_right_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 88.955 80.920 +*I mux_right_track_4\/mux_l1_in_3_:A0 I *L 0.001631 *C 71.935 104.040 +*I mux_right_track_2\/mux_l1_in_3_:A0 I *L 0.001631 *C 77.455 107.780 +*I mux_right_track_6\/mux_l1_in_3_:A0 I *L 0.001631 *C 62.735 109.480 +*N optlc_net_186:7 *C 62.773 109.480 +*N optlc_net_186:8 *C 74.935 109.480 +*N optlc_net_186:9 *C 74.980 109.435 +*N optlc_net_186:10 *C 77.418 107.780 +*N optlc_net_186:11 *C 75.025 107.780 +*N optlc_net_186:12 *C 74.980 107.780 +*N optlc_net_186:13 *C 74.980 105.060 +*N optlc_net_186:14 *C 74.520 105.060 +*N optlc_net_186:15 *C 71.972 104.040 +*N optlc_net_186:16 *C 74.475 104.040 +*N optlc_net_186:17 *C 74.520 104.040 +*N optlc_net_186:18 *C 88.955 80.920 +*N optlc_net_186:19 *C 88.780 80.920 +*N optlc_net_186:20 *C 88.780 80.965 +*N optlc_net_186:21 *C 79.333 82.280 +*N optlc_net_186:22 *C 88.735 82.280 +*N optlc_net_186:23 *C 88.780 82.280 +*N optlc_net_186:24 *C 90.297 91.800 +*N optlc_net_186:25 *C 88.825 91.800 +*N optlc_net_186:26 *C 88.780 91.800 +*N optlc_net_186:27 *C 88.773 91.800 +*N optlc_net_186:28 *C 74.528 91.800 +*N optlc_net_186:29 *C 74.520 91.858 +*N optlc_net_186:30 *C 74.520 96.560 +*N optlc_net_186:31 *C 74.565 96.560 +*N optlc_net_186:32 *C 75.862 96.560 + +*CAP +0 optlc_177:HI 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_14\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_16\/mux_l1_in_1_:A0 1e-06 +4 mux_right_track_4\/mux_l1_in_3_:A0 1e-06 +5 mux_right_track_2\/mux_l1_in_3_:A0 1e-06 +6 mux_right_track_6\/mux_l1_in_3_:A0 1e-06 +7 optlc_net_186:7 0.000776418 +8 optlc_net_186:8 0.000776418 +9 optlc_net_186:9 0.0001197119 +10 optlc_net_186:10 0.000176341 +11 optlc_net_186:11 0.000176341 +12 optlc_net_186:12 0.0003325582 +13 optlc_net_186:13 0.0002134954 +14 optlc_net_186:14 9.123107e-05 +15 optlc_net_186:15 0.0001825562 +16 optlc_net_186:16 0.0001825562 +17 optlc_net_186:17 0.0005330843 +18 optlc_net_186:18 6.319739e-05 +19 optlc_net_186:19 5.947063e-05 +20 optlc_net_186:20 8.200307e-05 +21 optlc_net_186:21 0.0007052814 +22 optlc_net_186:22 0.0007052814 +23 optlc_net_186:23 0.0006243165 +24 optlc_net_186:24 0.0001264394 +25 optlc_net_186:25 0.0001264394 +26 optlc_net_186:26 0.0005472646 +27 optlc_net_186:27 0.0009705401 +28 optlc_net_186:28 0.0009705401 +29 optlc_net_186:29 0.0002770846 +30 optlc_net_186:30 0.0007550386 +31 optlc_net_186:31 0.0001306359 +32 optlc_net_186:32 0.0001306359 +33 optlc_net_186:8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 8.643647e-05 +34 optlc_net_186:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 8.643647e-05 +35 optlc_net_186:16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.27163e-05 +36 optlc_net_186:17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.615118e-06 +37 optlc_net_186:17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.252909e-05 +38 optlc_net_186:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.27163e-05 +39 optlc_net_186:30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.252909e-05 +40 optlc_net_186:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.615118e-06 + +*RES +0 optlc_177:HI optlc_net_186:32 0.152 +1 optlc_net_186:22 optlc_net_186:21 0.008395089 +2 optlc_net_186:23 optlc_net_186:22 0.0045 +3 optlc_net_186:23 optlc_net_186:20 0.001174107 +4 optlc_net_186:21 mux_right_track_14\/mux_l2_in_1_:A0 0.152 +5 optlc_net_186:8 optlc_net_186:7 0.01085937 +6 optlc_net_186:9 optlc_net_186:8 0.0045 +7 optlc_net_186:7 mux_right_track_6\/mux_l1_in_3_:A0 0.152 +8 optlc_net_186:16 optlc_net_186:15 0.002234375 +9 optlc_net_186:17 optlc_net_186:16 0.0045 +10 optlc_net_186:17 optlc_net_186:14 0.0009107144 +11 optlc_net_186:15 mux_right_track_4\/mux_l1_in_3_:A0 0.152 +12 optlc_net_186:31 optlc_net_186:30 0.0045 +13 optlc_net_186:30 optlc_net_186:29 0.004198661 +14 optlc_net_186:30 optlc_net_186:17 0.006678571 +15 optlc_net_186:32 optlc_net_186:31 0.001158482 +16 optlc_net_186:26 optlc_net_186:25 0.0045 +17 optlc_net_186:26 optlc_net_186:23 0.0085 +18 optlc_net_186:27 optlc_net_186:26 0.00341 +19 optlc_net_186:29 optlc_net_186:28 0.00341 +20 optlc_net_186:28 optlc_net_186:27 0.002231717 +21 optlc_net_186:25 optlc_net_186:24 0.001314732 +22 optlc_net_186:24 mux_right_track_0\/mux_l2_in_1_:A0 0.152 +23 optlc_net_186:11 optlc_net_186:10 0.002136161 +24 optlc_net_186:12 optlc_net_186:11 0.0045 +25 optlc_net_186:12 optlc_net_186:9 0.001477679 +26 optlc_net_186:10 mux_right_track_2\/mux_l1_in_3_:A0 0.152 +27 optlc_net_186:19 optlc_net_186:18 9.51087e-05 +28 optlc_net_186:20 optlc_net_186:19 0.0045 +29 optlc_net_186:18 mux_right_track_16\/mux_l1_in_1_:A0 0.152 +30 optlc_net_186:14 optlc_net_186:13 0.0004107143 +31 optlc_net_186:13 optlc_net_186:12 0.002428571 + +*END + +*D_NET ropt_net_228 0.0009138556 //LENGTH 7.105 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_811:X O *L 0 *C 38.835 124.440 +*I ropt_mt_inst_848:A I *L 0.001767 *C 35.880 126.480 +*N ropt_net_228:2 *C 35.918 126.480 +*N ropt_net_228:3 *C 36.755 126.480 +*N ropt_net_228:4 *C 36.800 126.435 +*N ropt_net_228:5 *C 36.800 125.845 +*N ropt_net_228:6 *C 36.845 125.800 +*N ropt_net_228:7 *C 39.100 125.800 +*N ropt_net_228:8 *C 39.100 125.755 +*N ropt_net_228:9 *C 39.100 124.485 +*N ropt_net_228:10 *C 39.100 124.440 +*N ropt_net_228:11 *C 38.835 124.440 + +*CAP +0 ropt_mt_inst_811:X 1e-06 +1 ropt_mt_inst_848:A 1e-06 +2 ropt_net_228:2 6.886704e-05 +3 ropt_net_228:3 6.886704e-05 +4 ropt_net_228:4 5.535862e-05 +5 ropt_net_228:5 5.535862e-05 +6 ropt_net_228:6 0.0001734657 +7 ropt_net_228:7 0.0002027973 +8 ropt_net_228:8 9.085335e-05 +9 ropt_net_228:9 9.085335e-05 +10 ropt_net_228:10 5.144697e-05 +11 ropt_net_228:11 5.398769e-05 + +*RES +0 ropt_mt_inst_811:X ropt_net_228:11 0.152 +1 ropt_net_228:11 ropt_net_228:10 0.0001440218 +2 ropt_net_228:10 ropt_net_228:9 0.0045 +3 ropt_net_228:9 ropt_net_228:8 0.001133929 +4 ropt_net_228:7 ropt_net_228:6 0.002013393 +5 ropt_net_228:8 ropt_net_228:7 0.0045 +6 ropt_net_228:6 ropt_net_228:5 0.0045 +7 ropt_net_228:5 ropt_net_228:4 0.0005267857 +8 ropt_net_228:3 ropt_net_228:2 0.0007477679 +9 ropt_net_228:4 ropt_net_228:3 0.0045 +10 ropt_net_228:2 ropt_mt_inst_848:A 0.152 + +*END + +*D_NET ropt_net_239 0.001813568 //LENGTH 11.820 LUMPCC 0.0006671979 DR + +*CONN +*I ropt_mt_inst_829:X O *L 0 *C 107.180 49.640 +*I ropt_mt_inst_859:A I *L 0.001766 *C 106.260 47.600 +*N ropt_net_239:2 *C 106.297 47.600 +*N ropt_net_239:3 *C 107.595 47.600 +*N ropt_net_239:4 *C 107.640 47.645 +*N ropt_net_239:5 *C 107.640 48.223 +*N ropt_net_239:6 *C 107.648 48.280 +*N ropt_net_239:7 *C 110.392 48.280 +*N ropt_net_239:8 *C 110.400 48.338 +*N ropt_net_239:9 *C 110.400 49.935 +*N ropt_net_239:10 *C 110.355 49.980 +*N ropt_net_239:11 *C 107.180 49.980 +*N ropt_net_239:12 *C 107.180 49.640 + +*CAP +0 ropt_mt_inst_829:X 1e-06 +1 ropt_mt_inst_859:A 1e-06 +2 ropt_net_239:2 9.079835e-05 +3 ropt_net_239:3 9.079835e-05 +4 ropt_net_239:4 4.218011e-05 +5 ropt_net_239:5 4.218011e-05 +6 ropt_net_239:6 0.000145379 +7 ropt_net_239:7 0.000145379 +8 ropt_net_239:8 0.0001087418 +9 ropt_net_239:9 0.0001087418 +10 ropt_net_239:10 0.0001444857 +11 ropt_net_239:11 0.0001713174 +12 ropt_net_239:12 5.436848e-05 +13 ropt_net_239:4 chany_bottom_in[11]:5 5.816504e-06 +14 ropt_net_239:5 chany_bottom_in[11]:4 5.816504e-06 +15 ropt_net_239:8 chany_bottom_in[11]:5 7.240122e-07 +16 ropt_net_239:10 chany_bottom_in[11]:3 7.595335e-05 +17 ropt_net_239:9 chany_bottom_in[11]:4 7.240122e-07 +18 ropt_net_239:11 chany_bottom_in[11]:2 7.595335e-05 +19 ropt_net_239:6 chanx_right_in[0]:11 0.0001755193 +20 ropt_net_239:7 chanx_right_in[0] 0.0001755193 +21 ropt_net_239:2 chanx_right_in[8]:8 4.486631e-05 +22 ropt_net_239:3 chanx_right_in[8]:9 4.486631e-05 +23 ropt_net_239:4 chanx_right_in[8]:11 1.715875e-05 +24 ropt_net_239:5 chanx_right_in[8]:10 1.715875e-05 +25 ropt_net_239:6 chanx_right_in[8]:12 1.356068e-05 +26 ropt_net_239:7 chanx_right_in[8] 1.356068e-05 + +*RES +0 ropt_mt_inst_829:X ropt_net_239:12 0.152 +1 ropt_net_239:2 ropt_mt_inst_859:A 0.152 +2 ropt_net_239:3 ropt_net_239:2 0.001158482 +3 ropt_net_239:4 ropt_net_239:3 0.0045 +4 ropt_net_239:5 ropt_net_239:4 0.000515625 +5 ropt_net_239:6 ropt_net_239:5 0.00341 +6 ropt_net_239:8 ropt_net_239:7 0.00341 +7 ropt_net_239:7 ropt_net_239:6 0.00043005 +8 ropt_net_239:10 ropt_net_239:9 0.0045 +9 ropt_net_239:9 ropt_net_239:8 0.001426339 +10 ropt_net_239:12 ropt_net_239:11 0.0003035715 +11 ropt_net_239:11 ropt_net_239:10 0.002834821 + +*END + +*D_NET chanx_right_out[18] 0.0006606732 //LENGTH 5.050 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_861:X O *L 0 *C 110.135 55.080 +*P chanx_right_out[18] O *L 0.7423 *C 111.930 52.360 +*N chanx_right_out[18]:2 *C 110.407 52.360 +*N chanx_right_out[18]:3 *C 110.400 52.418 +*N chanx_right_out[18]:4 *C 110.400 55.035 +*N chanx_right_out[18]:5 *C 110.400 55.080 +*N chanx_right_out[18]:6 *C 110.135 55.080 + +*CAP +0 ropt_mt_inst_861:X 1e-06 +1 chanx_right_out[18] 0.000116629 +2 chanx_right_out[18]:2 0.000116629 +3 chanx_right_out[18]:3 0.0001577516 +4 chanx_right_out[18]:4 0.0001577516 +5 chanx_right_out[18]:5 5.135461e-05 +6 chanx_right_out[18]:6 5.955734e-05 + +*RES +0 ropt_mt_inst_861:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0001440218 +2 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.002337054 +4 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +5 chanx_right_out[18]:2 chanx_right_out[18] 0.000238525 + +*END + +*D_NET chany_bottom_out[19] 0.001856211 //LENGTH 14.180 LUMPCC 0 DR + +*CONN +*I BUFT_P_158:X O *L 0 *C 32.660 7.480 +*P chany_bottom_out[19] O *L 0.7423 *C 25.760 1.285 +*N chany_bottom_out[19]:2 *C 25.760 6.793 +*N chany_bottom_out[19]:3 *C 25.780 6.800 +*N chany_bottom_out[19]:4 *C 27.133 6.800 +*N chany_bottom_out[19]:5 *C 27.140 6.800 +*N chany_bottom_out[19]:6 *C 27.140 7.140 +*N chany_bottom_out[19]:7 *C 27.185 7.140 +*N chany_bottom_out[19]:8 *C 31.280 7.140 +*N chany_bottom_out[19]:9 *C 31.280 7.480 +*N chany_bottom_out[19]:10 *C 32.623 7.480 + +*CAP +0 BUFT_P_158:X 1e-06 +1 chany_bottom_out[19] 0.0003541795 +2 chany_bottom_out[19]:2 0.0003541795 +3 chany_bottom_out[19]:3 0.0001092561 +4 chany_bottom_out[19]:4 0.0001092561 +5 chany_bottom_out[19]:5 5.564292e-05 +6 chany_bottom_out[19]:6 5.185733e-05 +7 chany_bottom_out[19]:7 0.0002781233 +8 chany_bottom_out[19]:8 0.0003048398 +9 chany_bottom_out[19]:9 0.0001322963 +10 chany_bottom_out[19]:10 0.0001055798 + +*RES +0 BUFT_P_158:X chany_bottom_out[19]:10 0.152 +1 chany_bottom_out[19]:10 chany_bottom_out[19]:9 0.001198661 +2 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.0045 +3 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.0001634615 +4 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.00341 +5 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.0002118917 +6 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.00341 +7 chany_bottom_out[19]:2 chany_bottom_out[19] 0.0008628416 +8 chany_bottom_out[19]:8 chany_bottom_out[19]:7 0.00365625 +9 chany_bottom_out[19]:9 chany_bottom_out[19]:8 0.0003035715 + +*END + +*D_NET chany_bottom_in[0] 0.01158123 //LENGTH 102.410 LUMPCC 0.0009172182 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 65.780 1.325 +*I ropt_mt_inst_817:A I *L 0.001767 *C 106.260 53.040 +*N chany_bottom_in[0]:2 *C 106.297 53.040 +*N chany_bottom_in[0]:3 *C 109.435 53.040 +*N chany_bottom_in[0]:4 *C 109.480 52.995 +*N chany_bottom_in[0]:5 *C 109.480 44.925 +*N chany_bottom_in[0]:6 *C 109.435 44.880 +*N chany_bottom_in[0]:7 *C 105.385 44.880 +*N chany_bottom_in[0]:8 *C 105.340 44.835 +*N chany_bottom_in[0]:9 *C 105.340 37.105 +*N chany_bottom_in[0]:10 *C 105.295 37.060 +*N chany_bottom_in[0]:11 *C 102.625 37.060 +*N chany_bottom_in[0]:12 *C 102.580 37.015 +*N chany_bottom_in[0]:13 *C 102.580 34.045 +*N chany_bottom_in[0]:14 *C 102.535 34.000 +*N chany_bottom_in[0]:15 *C 100.325 34.000 +*N chany_bottom_in[0]:16 *C 100.280 33.955 +*N chany_bottom_in[0]:17 *C 100.280 28.945 +*N chany_bottom_in[0]:18 *C 100.280 28.900 +*N chany_bottom_in[0]:19 *C 100.280 27.880 +*N chany_bottom_in[0]:20 *C 75.485 27.880 +*N chany_bottom_in[0]:21 *C 75.440 27.835 +*N chany_bottom_in[0]:22 *C 75.440 1.745 +*N chany_bottom_in[0]:23 *C 75.395 1.700 +*N chany_bottom_in[0]:24 *C 65.825 1.700 +*N chany_bottom_in[0]:25 *C 65.780 1.655 + +*CAP +0 chany_bottom_in[0] 3.253211e-05 +1 ropt_mt_inst_817:A 1e-06 +2 chany_bottom_in[0]:2 0.0001992706 +3 chany_bottom_in[0]:3 0.0001992706 +4 chany_bottom_in[0]:4 0.0005037852 +5 chany_bottom_in[0]:5 0.0005037852 +6 chany_bottom_in[0]:6 0.0002508632 +7 chany_bottom_in[0]:7 0.0002508632 +8 chany_bottom_in[0]:8 0.0003299877 +9 chany_bottom_in[0]:9 0.0003299877 +10 chany_bottom_in[0]:10 0.0001646064 +11 chany_bottom_in[0]:11 0.0001646064 +12 chany_bottom_in[0]:12 0.0001721186 +13 chany_bottom_in[0]:13 0.0001721186 +14 chany_bottom_in[0]:14 0.0001881536 +15 chany_bottom_in[0]:15 0.0001881536 +16 chany_bottom_in[0]:16 0.000276791 +17 chany_bottom_in[0]:17 0.000276791 +18 chany_bottom_in[0]:18 7.342606e-05 +19 chany_bottom_in[0]:19 0.001371036 +20 chany_bottom_in[0]:20 0.001327627 +21 chany_bottom_in[0]:21 0.001266108 +22 chany_bottom_in[0]:22 0.001266108 +23 chany_bottom_in[0]:23 0.0005612439 +24 chany_bottom_in[0]:24 0.0005612439 +25 chany_bottom_in[0]:25 3.253211e-05 +26 chany_bottom_in[0]:8 chany_bottom_in[1]:5 0.0001027614 +27 chany_bottom_in[0]:9 chany_bottom_in[1]:6 0.0001027614 +28 chany_bottom_in[0]:12 chany_bottom_in[1]:5 2.952394e-06 +29 chany_bottom_in[0]:13 chany_bottom_in[1]:6 2.952394e-06 +30 chany_bottom_in[0]:18 chany_bottom_in[1]:8 1.538153e-05 +31 chany_bottom_in[0]:20 chany_bottom_in[1]:10 0.0003337865 +32 chany_bottom_in[0]:20 chany_bottom_in[1]:8 3.727191e-06 +33 chany_bottom_in[0]:19 chany_bottom_in[1]:7 3.727191e-06 +34 chany_bottom_in[0]:19 chany_bottom_in[1]:9 0.0003491681 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:25 0.0002946429 +1 chany_bottom_in[0]:2 ropt_mt_inst_817:A 0.152 +2 chany_bottom_in[0]:3 chany_bottom_in[0]:2 0.002801339 +3 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.0045 +4 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.0045 +5 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.007205357 +6 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.003616072 +7 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.0045 +8 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.0045 +9 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.006901786 +10 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.002383929 +11 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.0045 +12 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.0045 +13 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.002651786 +14 chany_bottom_in[0]:15 chany_bottom_in[0]:14 0.001973214 +15 chany_bottom_in[0]:16 chany_bottom_in[0]:15 0.0045 +16 chany_bottom_in[0]:18 chany_bottom_in[0]:17 0.0045 +17 chany_bottom_in[0]:17 chany_bottom_in[0]:16 0.004473215 +18 chany_bottom_in[0]:20 chany_bottom_in[0]:19 0.02213839 +19 chany_bottom_in[0]:21 chany_bottom_in[0]:20 0.0045 +20 chany_bottom_in[0]:23 chany_bottom_in[0]:22 0.0045 +21 chany_bottom_in[0]:22 chany_bottom_in[0]:21 0.02329464 +22 chany_bottom_in[0]:24 chany_bottom_in[0]:23 0.008544643 +23 chany_bottom_in[0]:25 chany_bottom_in[0]:24 0.0045 +24 chany_bottom_in[0]:19 chany_bottom_in[0]:18 0.0009107143 + +*END + +*D_NET chany_top_in[19] 0.008342897 //LENGTH 63.550 LUMPCC 0.001231416 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 47.380 129.270 +*I mux_right_track_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.285 93.500 +*N chany_top_in[19]:2 *C 73.248 93.500 +*N chany_top_in[19]:3 *C 72.265 93.500 +*N chany_top_in[19]:4 *C 72.220 93.545 +*N chany_top_in[19]:5 *C 72.220 95.823 +*N chany_top_in[19]:6 *C 72.213 95.880 +*N chany_top_in[19]:7 *C 47.860 95.880 +*N chany_top_in[19]:8 *C 47.840 95.888 +*N chany_top_in[19]:9 *C 47.840 127.153 +*N chany_top_in[19]:10 *C 47.825 127.160 +*N chany_top_in[19]:11 *C 47.383 127.160 +*N chany_top_in[19]:12 *C 47.380 127.218 + +*CAP +0 chany_top_in[19] 0.0001324538 +1 mux_right_track_14\/mux_l1_in_0_:A0 1e-06 +2 chany_top_in[19]:2 8.134433e-05 +3 chany_top_in[19]:3 8.134433e-05 +4 chany_top_in[19]:4 0.0001727206 +5 chany_top_in[19]:5 0.0001727206 +6 chany_top_in[19]:6 0.001567961 +7 chany_top_in[19]:7 0.001567961 +8 chany_top_in[19]:8 0.001538522 +9 chany_top_in[19]:9 0.001538522 +10 chany_top_in[19]:10 6.22396e-05 +11 chany_top_in[19]:11 6.22396e-05 +12 chany_top_in[19]:12 0.0001324538 +13 chany_top_in[19]:8 chany_top_in[15]:8 0.0004314557 +14 chany_top_in[19]:9 chany_top_in[15] 0.0004314557 +15 chany_top_in[19]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.000184252 +16 chany_top_in[19]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.000184252 + +*RES +0 chany_top_in[19] chany_top_in[19]:12 0.001832589 +1 chany_top_in[19]:2 mux_right_track_14\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[19]:3 chany_top_in[19]:2 0.0008772322 +3 chany_top_in[19]:4 chany_top_in[19]:3 0.0045 +4 chany_top_in[19]:5 chany_top_in[19]:4 0.002033482 +5 chany_top_in[19]:6 chany_top_in[19]:5 0.00341 +6 chany_top_in[19]:7 chany_top_in[19]:6 0.003815225 +7 chany_top_in[19]:8 chany_top_in[19]:7 0.00341 +8 chany_top_in[19]:10 chany_top_in[19]:9 0.00341 +9 chany_top_in[19]:9 chany_top_in[19]:8 0.004898183 +10 chany_top_in[19]:12 chany_top_in[19]:11 0.00341 +11 chany_top_in[19]:11 chany_top_in[19]:10 6.499219e-05 + +*END + +*D_NET chanx_right_in[1] 0.008122483 //LENGTH 72.620 LUMPCC 0.0002074462 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 111.930 99.280 +*I mux_bottom_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 101.200 47.260 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 101.030 70.040 +*N chanx_right_in[1]:3 *C 101.068 70.040 +*N chanx_right_in[1]:4 *C 107.180 70.040 +*N chanx_right_in[1]:5 *C 101.238 47.260 +*N chanx_right_in[1]:6 *C 104.375 47.260 +*N chanx_right_in[1]:7 *C 104.420 47.305 +*N chanx_right_in[1]:8 *C 104.420 50.615 +*N chanx_right_in[1]:9 *C 104.465 50.660 +*N chanx_right_in[1]:10 *C 107.135 50.660 +*N chanx_right_in[1]:11 *C 107.180 50.705 +*N chanx_right_in[1]:12 *C 107.180 69.315 +*N chanx_right_in[1]:13 *C 107.180 69.360 +*N chanx_right_in[1]:14 *C 107.180 69.020 +*N chanx_right_in[1]:15 *C 108.975 69.020 +*N chanx_right_in[1]:16 *C 109.020 69.065 +*N chanx_right_in[1]:17 *C 109.020 99.223 +*N chanx_right_in[1]:18 *C 109.028 99.280 + +*CAP +0 chanx_right_in[1] 0.0001916522 +1 mux_bottom_track_17\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +3 chanx_right_in[1]:3 0.0004236392 +4 chanx_right_in[1]:4 0.0004653423 +5 chanx_right_in[1]:5 0.0002268488 +6 chanx_right_in[1]:6 0.0002268488 +7 chanx_right_in[1]:7 0.0001942789 +8 chanx_right_in[1]:8 0.0001942789 +9 chanx_right_in[1]:9 0.0001918796 +10 chanx_right_in[1]:10 0.0001918796 +11 chanx_right_in[1]:11 0.0009271876 +12 chanx_right_in[1]:12 0.0009271876 +13 chanx_right_in[1]:13 9.965934e-05 +14 chanx_right_in[1]:14 0.0001825523 +15 chanx_right_in[1]:15 0.0001597546 +16 chanx_right_in[1]:16 0.001559198 +17 chanx_right_in[1]:17 0.001559198 +18 chanx_right_in[1]:18 0.0001916522 +19 chanx_right_in[1]:11 ropt_net_241:5 4.606654e-05 +20 chanx_right_in[1]:12 ropt_net_241:4 4.606654e-05 +21 chanx_right_in[1]:11 ropt_net_211:7 2.670232e-05 +22 chanx_right_in[1]:11 ropt_net_211:4 3.095422e-05 +23 chanx_right_in[1]:12 ropt_net_211:5 3.095422e-05 +24 chanx_right_in[1]:12 ropt_net_211:6 2.670232e-05 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:18 0.000454725 +1 chanx_right_in[1]:5 mux_bottom_track_17\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[1]:6 chanx_right_in[1]:5 0.00280134 +3 chanx_right_in[1]:7 chanx_right_in[1]:6 0.0045 +4 chanx_right_in[1]:9 chanx_right_in[1]:8 0.0045 +5 chanx_right_in[1]:8 chanx_right_in[1]:7 0.002955357 +6 chanx_right_in[1]:10 chanx_right_in[1]:9 0.002383929 +7 chanx_right_in[1]:11 chanx_right_in[1]:10 0.0045 +8 chanx_right_in[1]:13 chanx_right_in[1]:12 0.0045 +9 chanx_right_in[1]:13 chanx_right_in[1]:4 0.0006071429 +10 chanx_right_in[1]:12 chanx_right_in[1]:11 0.01661607 +11 chanx_right_in[1]:3 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +12 chanx_right_in[1]:15 chanx_right_in[1]:14 0.001602679 +13 chanx_right_in[1]:16 chanx_right_in[1]:15 0.0045 +14 chanx_right_in[1]:17 chanx_right_in[1]:16 0.02692634 +15 chanx_right_in[1]:18 chanx_right_in[1]:17 0.00341 +16 chanx_right_in[1]:4 chanx_right_in[1]:3 0.005457589 +17 chanx_right_in[1]:14 chanx_right_in[1]:13 0.0003035715 + +*END + +*D_NET chanx_right_in[6] 0.01489962 //LENGTH 117.835 LUMPCC 0.002103085 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 111.855 77.520 +*I mux_bottom_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 41.230 37.400 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.005 77.860 +*N chanx_right_in[6]:3 *C 39.005 77.860 +*N chanx_right_in[6]:4 *C 39.100 77.815 +*N chanx_right_in[6]:5 *C 41.230 37.400 +*N chanx_right_in[6]:6 *C 41.400 37.400 +*N chanx_right_in[6]:7 *C 41.400 37.445 +*N chanx_right_in[6]:8 *C 41.400 60.815 +*N chanx_right_in[6]:9 *C 41.355 60.860 +*N chanx_right_in[6]:10 *C 39.145 60.860 +*N chanx_right_in[6]:11 *C 39.100 60.905 +*N chanx_right_in[6]:12 *C 39.100 76.840 +*N chanx_right_in[6]:13 *C 39.108 76.840 +*N chanx_right_in[6]:14 *C 88.935 76.840 +*N chanx_right_in[6]:15 *C 111.780 76.840 + +*CAP +0 chanx_right_in[6] 5.687736e-05 +1 mux_bottom_track_33\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +3 chanx_right_in[6]:3 2.878421e-05 +4 chanx_right_in[6]:4 4.312484e-05 +5 chanx_right_in[6]:5 4.832826e-05 +6 chanx_right_in[6]:6 5.242103e-05 +7 chanx_right_in[6]:7 0.001223931 +8 chanx_right_in[6]:8 0.001223931 +9 chanx_right_in[6]:9 0.0001450145 +10 chanx_right_in[6]:10 0.0001450145 +11 chanx_right_in[6]:11 0.0007040217 +12 chanx_right_in[6]:12 0.0007827875 +13 chanx_right_in[6]:13 0.002805424 +14 chanx_right_in[6]:14 0.004141711 +15 chanx_right_in[6]:15 0.001393164 +16 chanx_right_in[6]:13 chany_top_in[17]:9 0.0004699545 +17 chanx_right_in[6]:14 chany_top_in[17]:8 0.0004699545 +18 chanx_right_in[6]:12 chany_bottom_in[8]:21 0.0002825012 +19 chanx_right_in[6]:12 chany_bottom_in[8]:22 3.081172e-05 +20 chanx_right_in[6]:4 chany_bottom_in[8]:21 3.081172e-05 +21 chanx_right_in[6]:11 chany_bottom_in[8]:22 0.0002825012 +22 chanx_right_in[6]:13 chany_bottom_in[12]:40 0.000268275 +23 chanx_right_in[6]:14 chany_bottom_in[12]:39 0.000268275 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:15 0.0001065333 +1 chanx_right_in[6]:12 chanx_right_in[6]:11 0.01422768 +2 chanx_right_in[6]:12 chanx_right_in[6]:4 0.0008705358 +3 chanx_right_in[6]:13 chanx_right_in[6]:12 0.00341 +4 chanx_right_in[6]:3 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +5 chanx_right_in[6]:4 chanx_right_in[6]:3 0.0045 +6 chanx_right_in[6]:10 chanx_right_in[6]:9 0.001973214 +7 chanx_right_in[6]:11 chanx_right_in[6]:10 0.0045 +8 chanx_right_in[6]:9 chanx_right_in[6]:8 0.0045 +9 chanx_right_in[6]:8 chanx_right_in[6]:7 0.02086607 +10 chanx_right_in[6]:6 chanx_right_in[6]:5 9.239131e-05 +11 chanx_right_in[6]:7 chanx_right_in[6]:6 0.0045 +12 chanx_right_in[6]:5 mux_bottom_track_33\/mux_l1_in_0_:A0 0.152 +13 chanx_right_in[6]:15 chanx_right_in[6]:14 0.00357905 +14 chanx_right_in[6]:14 chanx_right_in[6]:13 0.007806308 + +*END + +*D_NET chanx_right_in[8] 0.004088957 //LENGTH 33.365 LUMPCC 0.0001511715 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 111.930 44.880 +*I mux_top_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 98.805 63.580 +*I mux_bottom_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 101.030 47.940 +*N chanx_right_in[8]:3 *C 101.030 47.940 +*N chanx_right_in[8]:4 *C 98.843 63.580 +*N chanx_right_in[8]:5 *C 101.155 63.580 +*N chanx_right_in[8]:6 *C 101.200 63.535 +*N chanx_right_in[8]:7 *C 101.200 47.985 +*N chanx_right_in[8]:8 *C 101.245 47.940 +*N chanx_right_in[8]:9 *C 107.135 47.940 +*N chanx_right_in[8]:10 *C 107.180 47.895 +*N chanx_right_in[8]:11 *C 107.180 44.938 +*N chanx_right_in[8]:12 *C 107.188 44.880 + +*CAP +0 chanx_right_in[8] 0.0003166744 +1 mux_top_track_0\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[8]:3 4.575225e-05 +4 chanx_right_in[8]:4 0.0001579735 +5 chanx_right_in[8]:5 0.0001579735 +6 chanx_right_in[8]:6 0.0009311709 +7 chanx_right_in[8]:7 0.0009311709 +8 chanx_right_in[8]:8 0.0003632014 +9 chanx_right_in[8]:9 0.0003437461 +10 chanx_right_in[8]:10 0.0001857242 +11 chanx_right_in[8]:11 0.0001857242 +12 chanx_right_in[8]:12 0.0003166744 +13 chanx_right_in[8] ropt_net_239:7 1.356068e-05 +14 chanx_right_in[8]:9 ropt_net_239:3 4.486631e-05 +15 chanx_right_in[8]:10 ropt_net_239:5 1.715875e-05 +16 chanx_right_in[8]:11 ropt_net_239:4 1.715875e-05 +17 chanx_right_in[8]:12 ropt_net_239:6 1.356068e-05 +18 chanx_right_in[8]:8 ropt_net_239:2 4.486631e-05 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:12 0.0007429916 +1 chanx_right_in[8]:9 chanx_right_in[8]:8 0.005258929 +2 chanx_right_in[8]:10 chanx_right_in[8]:9 0.0045 +3 chanx_right_in[8]:11 chanx_right_in[8]:10 0.002640625 +4 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00341 +5 chanx_right_in[8]:3 mux_bottom_track_17\/mux_l1_in_1_:A0 0.152 +6 chanx_right_in[8]:8 chanx_right_in[8]:7 0.0045 +7 chanx_right_in[8]:8 chanx_right_in[8]:3 0.0001168478 +8 chanx_right_in[8]:7 chanx_right_in[8]:6 0.01388393 +9 chanx_right_in[8]:5 chanx_right_in[8]:4 0.002064732 +10 chanx_right_in[8]:6 chanx_right_in[8]:5 0.0045 +11 chanx_right_in[8]:4 mux_top_track_0\/mux_l1_in_1_:A1 0.152 + +*END + +*D_NET chanx_right_in[12] 0.01301424 //LENGTH 96.795 LUMPCC 0.003412326 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 111.930 96.560 +*I mux_top_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 47.210 70.040 +*I mux_bottom_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 51.350 66.300 +*N chanx_right_in[12]:3 *C 51.350 66.300 +*N chanx_right_in[12]:4 *C 51.060 66.300 +*N chanx_right_in[12]:5 *C 51.060 66.345 +*N chanx_right_in[12]:6 *C 47.248 70.040 +*N chanx_right_in[12]:7 *C 51.015 70.040 +*N chanx_right_in[12]:8 *C 51.060 70.040 +*N chanx_right_in[12]:9 *C 51.060 72.023 +*N chanx_right_in[12]:10 *C 51.068 72.080 +*N chanx_right_in[12]:11 *C 95.660 72.080 +*N chanx_right_in[12]:12 *C 95.680 72.088 +*N chanx_right_in[12]:13 *C 95.680 96.553 +*N chanx_right_in[12]:14 *C 95.700 96.560 + +*CAP +0 chanx_right_in[12] 0.000493727 +1 mux_top_track_16\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_1\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[12]:3 4.746014e-05 +4 chanx_right_in[12]:4 5.16123e-05 +5 chanx_right_in[12]:5 0.0001952053 +6 chanx_right_in[12]:6 0.0002844707 +7 chanx_right_in[12]:7 0.0002844707 +8 chanx_right_in[12]:8 0.000378707 +9 chanx_right_in[12]:9 0.000150871 +10 chanx_right_in[12]:10 0.002698319 +11 chanx_right_in[12]:11 0.002698319 +12 chanx_right_in[12]:12 0.0009115121 +13 chanx_right_in[12]:13 0.0009115121 +14 chanx_right_in[12]:14 0.0004937271 +15 chanx_right_in[12] chanx_right_in[4] 1.349008e-05 +16 chanx_right_in[12]:12 chanx_right_in[4]:16 0.0003180384 +17 chanx_right_in[12]:14 chanx_right_in[4]:18 1.349008e-05 +18 chanx_right_in[12]:13 chanx_right_in[4]:17 0.0003180384 +19 chanx_right_in[12] chanx_right_in[5] 9.211986e-05 +20 chanx_right_in[12] chanx_right_in[5]:16 0.0004031553 +21 chanx_right_in[12]:12 chanx_right_in[5]:13 8.724882e-06 +22 chanx_right_in[12]:14 chanx_right_in[5]:15 0.0004031553 +23 chanx_right_in[12]:14 chanx_right_in[5]:17 9.211986e-05 +24 chanx_right_in[12]:13 chanx_right_in[5]:14 8.724882e-06 +25 chanx_right_in[12]:7 chanx_right_in[5]:5 2.588458e-05 +26 chanx_right_in[12]:8 chanx_right_in[5]:6 6.146898e-05 +27 chanx_right_in[12]:8 chanx_right_in[5]:9 1.081902e-05 +28 chanx_right_in[12]:6 chanx_right_in[5]:4 2.588458e-05 +29 chanx_right_in[12]:5 chanx_right_in[5]:10 7.2288e-05 +30 chanx_right_in[12] right_top_grid_pin_44_[0]:21 0.0003725702 +31 chanx_right_in[12]:14 right_top_grid_pin_44_[0]:20 0.0003725702 +32 chanx_right_in[12]:10 mux_tree_tapbuf_size3_1_sram[0]:15 0.0003941383 +33 chanx_right_in[12]:11 mux_tree_tapbuf_size3_1_sram[0]:16 0.0003941383 +34 chanx_right_in[12]:12 mux_tree_tapbuf_size3_1_sram[0]:17 5.753229e-06 +35 chanx_right_in[12]:13 mux_tree_tapbuf_size3_1_sram[0]:18 5.753229e-06 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:14 0.0025427 +1 chanx_right_in[12]:9 chanx_right_in[12]:8 0.001770089 +2 chanx_right_in[12]:10 chanx_right_in[12]:9 0.00341 +3 chanx_right_in[12]:11 chanx_right_in[12]:10 0.006986158 +4 chanx_right_in[12]:12 chanx_right_in[12]:11 0.00341 +5 chanx_right_in[12]:14 chanx_right_in[12]:13 0.00341 +6 chanx_right_in[12]:13 chanx_right_in[12]:12 0.00383285 +7 chanx_right_in[12]:7 chanx_right_in[12]:6 0.003363839 +8 chanx_right_in[12]:8 chanx_right_in[12]:7 0.0045 +9 chanx_right_in[12]:8 chanx_right_in[12]:5 0.003299107 +10 chanx_right_in[12]:6 mux_top_track_16\/mux_l1_in_0_:A0 0.152 +11 chanx_right_in[12]:4 chanx_right_in[12]:3 0.0001576087 +12 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0045 +13 chanx_right_in[12]:3 mux_bottom_track_1\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET chanx_right_in[17] 0.004728741 //LENGTH 36.850 LUMPCC 0.001330236 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 111.930 34.000 +*I mux_bottom_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 85.560 34.340 +*I mux_top_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 85.390 42.500 +*N chanx_right_in[17]:3 *C 85.390 42.500 +*N chanx_right_in[17]:4 *C 85.100 42.500 +*N chanx_right_in[17]:5 *C 85.100 42.455 +*N chanx_right_in[17]:6 *C 85.523 34.340 +*N chanx_right_in[17]:7 *C 85.145 34.340 +*N chanx_right_in[17]:8 *C 85.100 34.385 +*N chanx_right_in[17]:9 *C 85.100 34.000 +*N chanx_right_in[17]:10 *C 85.108 34.000 + +*CAP +0 chanx_right_in[17] 0.001109754 +1 mux_bottom_track_5\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[17]:3 5.729773e-05 +4 chanx_right_in[17]:4 5.989297e-05 +5 chanx_right_in[17]:5 0.0004418634 +6 chanx_right_in[17]:6 5.002091e-05 +7 chanx_right_in[17]:7 5.002091e-05 +8 chanx_right_in[17]:8 0.0004615848 +9 chanx_right_in[17]:9 5.631672e-05 +10 chanx_right_in[17]:10 0.001109754 +11 chanx_right_in[17] chanx_right_in[13] 0.0006651179 +12 chanx_right_in[17]:10 chanx_right_in[13]:14 0.0006651179 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:10 0.004202191 +1 chanx_right_in[17]:3 mux_top_track_4\/mux_l1_in_1_:A0 0.152 +2 chanx_right_in[17]:4 chanx_right_in[17]:3 0.0001467391 +3 chanx_right_in[17]:5 chanx_right_in[17]:4 0.0045 +4 chanx_right_in[17]:7 chanx_right_in[17]:6 0.0003370536 +5 chanx_right_in[17]:8 chanx_right_in[17]:7 0.0045 +6 chanx_right_in[17]:8 chanx_right_in[17]:5 0.007205358 +7 chanx_right_in[17]:6 mux_bottom_track_5\/mux_l1_in_2_:A1 0.152 +8 chanx_right_in[17]:9 chanx_right_in[17]:8 0.0001850961 +9 chanx_right_in[17]:10 chanx_right_in[17]:9 0.00341 + +*END + +*D_NET right_top_grid_pin_43_[0] 0.01441423 //LENGTH 119.995 LUMPCC 0.002136122 DR + +*CONN +*P right_top_grid_pin_43_[0] I *L 0.29796 *C 83.410 126.480 +*I mux_right_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 79.120 117.980 +*I mux_right_track_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 42.610 96.900 +*I mux_right_track_26\/mux_l1_in_0_:A1 I *L 0.00198 *C 36.900 58.140 +*I mux_right_track_6\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.445 117.980 +*N right_top_grid_pin_43_[0]:5 *C 68.483 117.980 +*N right_top_grid_pin_43_[0]:6 *C 36.090 62.560 +*N right_top_grid_pin_43_[0]:7 *C 36.800 58.140 +*N right_top_grid_pin_43_[0]:8 *C 36.800 58.185 +*N right_top_grid_pin_43_[0]:9 *C 36.800 62.503 +*N right_top_grid_pin_43_[0]:10 *C 36.797 62.560 +*N right_top_grid_pin_43_[0]:11 *C 36.800 62.568 +*N right_top_grid_pin_43_[0]:12 *C 36.800 93.833 +*N right_top_grid_pin_43_[0]:13 *C 36.820 93.840 +*N right_top_grid_pin_43_[0]:14 *C 43.233 93.840 +*N right_top_grid_pin_43_[0]:15 *C 43.240 93.898 +*N right_top_grid_pin_43_[0]:16 *C 42.648 96.900 +*N right_top_grid_pin_43_[0]:17 *C 43.195 96.900 +*N right_top_grid_pin_43_[0]:18 *C 43.240 96.900 +*N right_top_grid_pin_43_[0]:19 *C 43.240 117.583 +*N right_top_grid_pin_43_[0]:20 *C 43.248 117.640 +*N right_top_grid_pin_43_[0]:21 *C 68.993 117.640 +*N right_top_grid_pin_43_[0]:22 *C 69.000 117.640 +*N right_top_grid_pin_43_[0]:23 *C 69.000 117.980 +*N right_top_grid_pin_43_[0]:24 *C 69.000 117.980 +*N right_top_grid_pin_43_[0]:25 *C 79.120 117.980 +*N right_top_grid_pin_43_[0]:26 *C 79.995 117.980 +*N right_top_grid_pin_43_[0]:27 *C 80.040 118.025 +*N right_top_grid_pin_43_[0]:28 *C 80.040 126.422 +*N right_top_grid_pin_43_[0]:29 *C 80.047 126.480 + +*CAP +0 right_top_grid_pin_43_[0] 0.0001535209 +1 mux_right_track_2\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_10\/mux_l2_in_0_:A0 1e-06 +3 mux_right_track_26\/mux_l1_in_0_:A1 1e-06 +4 mux_right_track_6\/mux_l1_in_1_:A1 1e-06 +5 right_top_grid_pin_43_[0]:5 4.470479e-05 +6 right_top_grid_pin_43_[0]:6 0.0001279081 +7 right_top_grid_pin_43_[0]:7 3.194566e-05 +8 right_top_grid_pin_43_[0]:8 0.0002515306 +9 right_top_grid_pin_43_[0]:9 0.0002515306 +10 right_top_grid_pin_43_[0]:10 0.0001279081 +11 right_top_grid_pin_43_[0]:11 0.001076379 +12 right_top_grid_pin_43_[0]:12 0.001076379 +13 right_top_grid_pin_43_[0]:13 0.0004203095 +14 right_top_grid_pin_43_[0]:14 0.0004203095 +15 right_top_grid_pin_43_[0]:15 0.0001554945 +16 right_top_grid_pin_43_[0]:16 6.268562e-05 +17 right_top_grid_pin_43_[0]:17 6.268562e-05 +18 right_top_grid_pin_43_[0]:18 0.001226025 +19 right_top_grid_pin_43_[0]:19 0.001040564 +20 right_top_grid_pin_43_[0]:20 0.001441826 +21 right_top_grid_pin_43_[0]:21 0.001441826 +22 right_top_grid_pin_43_[0]:22 5.9862e-05 +23 right_top_grid_pin_43_[0]:23 5.598765e-05 +24 right_top_grid_pin_43_[0]:24 0.0008006266 +25 right_top_grid_pin_43_[0]:25 0.0008267572 +26 right_top_grid_pin_43_[0]:26 7.715116e-05 +27 right_top_grid_pin_43_[0]:27 0.0004433335 +28 right_top_grid_pin_43_[0]:28 0.0004433335 +29 right_top_grid_pin_43_[0]:29 0.0001535209 +30 right_top_grid_pin_43_[0]:12 chany_bottom_in[13]:18 0.0006771887 +31 right_top_grid_pin_43_[0]:11 chany_bottom_in[13]:19 0.0006771887 +32 right_top_grid_pin_43_[0]:21 mux_tree_tapbuf_size7_2_sram[0]:15 0.0003103371 +33 right_top_grid_pin_43_[0]:21 mux_tree_tapbuf_size7_2_sram[0]:16 4.415236e-05 +34 right_top_grid_pin_43_[0]:20 mux_tree_tapbuf_size7_2_sram[0]:15 4.415236e-05 +35 right_top_grid_pin_43_[0]:20 mux_tree_tapbuf_size7_2_sram[0]:10 0.0003103371 +36 right_top_grid_pin_43_[0]:19 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.510359e-05 +37 right_top_grid_pin_43_[0]:18 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.510359e-05 +38 right_top_grid_pin_43_[0]:18 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.1279e-05 +39 right_top_grid_pin_43_[0]:15 mux_right_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.1279e-05 + +*RES +0 right_top_grid_pin_43_[0] right_top_grid_pin_43_[0]:29 0.0005267917 +1 right_top_grid_pin_43_[0]:25 mux_right_track_2\/mux_l1_in_1_:A1 0.152 +2 right_top_grid_pin_43_[0]:25 right_top_grid_pin_43_[0]:24 0.009035714 +3 right_top_grid_pin_43_[0]:24 right_top_grid_pin_43_[0]:23 0.0045 +4 right_top_grid_pin_43_[0]:24 right_top_grid_pin_43_[0]:5 0.0004620536 +5 right_top_grid_pin_43_[0]:23 right_top_grid_pin_43_[0]:22 0.0001634615 +6 right_top_grid_pin_43_[0]:22 right_top_grid_pin_43_[0]:21 0.00341 +7 right_top_grid_pin_43_[0]:21 right_top_grid_pin_43_[0]:20 0.004033383 +8 right_top_grid_pin_43_[0]:19 right_top_grid_pin_43_[0]:18 0.01846652 +9 right_top_grid_pin_43_[0]:20 right_top_grid_pin_43_[0]:19 0.00341 +10 right_top_grid_pin_43_[0]:26 right_top_grid_pin_43_[0]:25 0.00078125 +11 right_top_grid_pin_43_[0]:27 right_top_grid_pin_43_[0]:26 0.0045 +12 right_top_grid_pin_43_[0]:28 right_top_grid_pin_43_[0]:27 0.007497768 +13 right_top_grid_pin_43_[0]:29 right_top_grid_pin_43_[0]:28 0.00341 +14 right_top_grid_pin_43_[0]:17 right_top_grid_pin_43_[0]:16 0.0004888393 +15 right_top_grid_pin_43_[0]:18 right_top_grid_pin_43_[0]:17 0.0045 +16 right_top_grid_pin_43_[0]:18 right_top_grid_pin_43_[0]:15 0.002680804 +17 right_top_grid_pin_43_[0]:16 mux_right_track_10\/mux_l2_in_0_:A0 0.152 +18 right_top_grid_pin_43_[0]:5 mux_right_track_6\/mux_l1_in_1_:A1 0.152 +19 right_top_grid_pin_43_[0]:15 right_top_grid_pin_43_[0]:14 0.00341 +20 right_top_grid_pin_43_[0]:14 right_top_grid_pin_43_[0]:13 0.001004625 +21 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:12 0.00341 +22 right_top_grid_pin_43_[0]:12 right_top_grid_pin_43_[0]:11 0.004898183 +23 right_top_grid_pin_43_[0]:10 right_top_grid_pin_43_[0]:9 0.00341 +24 right_top_grid_pin_43_[0]:10 right_top_grid_pin_43_[0]:6 0.0001039141 +25 right_top_grid_pin_43_[0]:11 right_top_grid_pin_43_[0]:10 0.00341 +26 right_top_grid_pin_43_[0]:9 right_top_grid_pin_43_[0]:8 0.003854911 +27 right_top_grid_pin_43_[0]:7 mux_right_track_26\/mux_l1_in_0_:A1 0.152 +28 right_top_grid_pin_43_[0]:8 right_top_grid_pin_43_[0]:7 0.0045 + +*END + +*D_NET chany_bottom_in[19] 0.004704244 //LENGTH 45.695 LUMPCC 0.001323854 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 24.840 1.290 +*I mux_right_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 29.540 41.820 +*N chany_bottom_in[19]:2 *C 29.503 41.820 +*N chany_bottom_in[19]:3 *C 24.885 41.820 +*N chany_bottom_in[19]:4 *C 24.840 41.775 + +*CAP +0 chany_bottom_in[19] 0.001390929 +1 mux_right_track_24\/mux_l2_in_1_:A1 1e-06 +2 chany_bottom_in[19]:2 0.0002987657 +3 chany_bottom_in[19]:3 0.0002987657 +4 chany_bottom_in[19]:4 0.001390929 +5 chany_bottom_in[19] chany_top_in[17]:17 0.000344584 +6 chany_bottom_in[19]:4 chany_top_in[17]:18 0.000344584 +7 chany_bottom_in[19] chany_bottom_in[18]:15 0.000317343 +8 chany_bottom_in[19]:4 chany_bottom_in[18]:14 0.000317343 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:4 0.03614732 +1 chany_bottom_in[19]:2 mux_right_track_24\/mux_l2_in_1_:A1 0.152 +2 chany_bottom_in[19]:3 chany_bottom_in[19]:2 0.004122768 +3 chany_bottom_in[19]:4 chany_bottom_in[19]:3 0.0045 + +*END + +*D_NET chany_top_out[2] 0.0009354017 //LENGTH 7.680 LUMPCC 0.0001398264 DR + +*CONN +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 75.385 126.140 +*P chany_top_out[2] O *L 0.7423 *C 71.300 129.270 +*N chany_top_out[2]:2 *C 71.300 126.185 +*N chany_top_out[2]:3 *C 71.345 126.140 +*N chany_top_out[2]:4 *C 75.347 126.140 + +*CAP +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[2] 0.0001845849 +2 chany_top_out[2]:2 0.0001845849 +3 chany_top_out[2]:3 0.0002127027 +4 chany_top_out[2]:4 0.0002127027 +5 chany_top_out[2]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.991321e-05 +6 chany_top_out[2]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.991321e-05 + +*RES +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[2]:4 0.152 +1 chany_top_out[2]:4 chany_top_out[2]:3 0.003573661 +2 chany_top_out[2]:3 chany_top_out[2]:2 0.0045 +3 chany_top_out[2]:2 chany_top_out[2] 0.002754464 + +*END + +*D_NET chanx_right_out[0] 0.001384253 //LENGTH 12.390 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.020 88.060 +*P chanx_right_out[0] O *L 0.7423 *C 111.855 84.320 +*N chanx_right_out[0]:2 *C 110.868 84.320 +*N chanx_right_out[0]:3 *C 110.860 84.377 +*N chanx_right_out[0]:4 *C 110.860 88.015 +*N chanx_right_out[0]:5 *C 110.815 88.060 +*N chanx_right_out[0]:6 *C 104.058 88.060 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 0.0001034874 +2 chanx_right_out[0]:2 0.0001034874 +3 chanx_right_out[0]:3 0.0002141926 +4 chanx_right_out[0]:4 0.0002141926 +5 chanx_right_out[0]:5 0.0003739467 +6 chanx_right_out[0]:6 0.0003739467 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:6 0.152 +1 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +2 chanx_right_out[0]:2 chanx_right_out[0] 0.0001547083 +3 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +4 chanx_right_out[0]:4 chanx_right_out[0]:3 0.003247768 +5 chanx_right_out[0]:6 chanx_right_out[0]:5 0.006033482 + +*END + +*D_NET chanx_right_out[5] 0.002517499 //LENGTH 21.565 LUMPCC 0 DR + +*CONN +*I mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 101.720 82.620 +*P chanx_right_out[5] O *L 0.7423 *C 111.930 72.080 +*N chanx_right_out[5]:2 *C 102.588 72.080 +*N chanx_right_out[5]:3 *C 102.580 72.138 +*N chanx_right_out[5]:4 *C 102.580 82.575 +*N chanx_right_out[5]:5 *C 102.535 82.620 +*N chanx_right_out[5]:6 *C 101.758 82.620 + +*CAP +0 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[5] 0.0005761501 +2 chanx_right_out[5]:2 0.0005761501 +3 chanx_right_out[5]:3 0.0006134402 +4 chanx_right_out[5]:4 0.0006134402 +5 chanx_right_out[5]:5 6.86589e-05 +6 chanx_right_out[5]:6 6.86589e-05 + +*RES +0 mux_right_track_10\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[5]:6 0.152 +1 chanx_right_out[5]:6 chanx_right_out[5]:5 0.0006941964 +2 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0045 +3 chanx_right_out[5]:4 chanx_right_out[5]:3 0.009319197 +4 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +5 chanx_right_out[5]:2 chanx_right_out[5] 0.001463658 + +*END + +*D_NET chanx_right_out[13] 0.002455401 //LENGTH 21.575 LUMPCC 0 DR + +*CONN +*I mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 72.080 +*P chanx_right_out[13] O *L 0.7423 *C 111.930 85.680 +*N chanx_right_out[13]:2 *C 107.188 85.680 +*N chanx_right_out[13]:3 *C 107.180 85.623 +*N chanx_right_out[13]:4 *C 107.180 72.805 +*N chanx_right_out[13]:5 *C 107.135 72.760 +*N chanx_right_out[13]:6 *C 104.880 72.760 +*N chanx_right_out[13]:7 *C 104.880 72.080 + +*CAP +0 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[13] 0.0003242526 +2 chanx_right_out[13]:2 0.0003242526 +3 chanx_right_out[13]:3 0.0006860849 +4 chanx_right_out[13]:4 0.0006860849 +5 chanx_right_out[13]:5 0.0001603712 +6 chanx_right_out[13]:6 0.000203494 +7 chanx_right_out[13]:7 6.986094e-05 + +*RES +0 mux_right_track_26\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[13]:7 0.152 +1 chanx_right_out[13]:7 chanx_right_out[13]:6 0.0006071429 +2 chanx_right_out[13]:5 chanx_right_out[13]:4 0.0045 +3 chanx_right_out[13]:4 chanx_right_out[13]:3 0.0114442 +4 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +5 chanx_right_out[13]:2 chanx_right_out[13] 0.0007429916 +6 chanx_right_out[13]:6 chanx_right_out[13]:5 0.002013393 + +*END + +*D_NET ropt_net_194 0.001556461 //LENGTH 10.110 LUMPCC 0.000346754 DR + +*CONN +*I mux_bottom_track_9\/BUFT_P_143:X O *L 0 *C 61.840 6.120 +*I ropt_mt_inst_815:A I *L 0.001766 *C 55.660 4.080 +*N ropt_net_194:2 *C 55.698 4.080 +*N ropt_net_194:3 *C 56.075 4.080 +*N ropt_net_194:4 *C 56.120 4.125 +*N ropt_net_194:5 *C 56.120 6.415 +*N ropt_net_194:6 *C 56.165 6.460 +*N ropt_net_194:7 *C 59.340 6.460 +*N ropt_net_194:8 *C 59.340 6.120 +*N ropt_net_194:9 *C 61.803 6.120 + +*CAP +0 mux_bottom_track_9\/BUFT_P_143:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_194:2 5.501414e-05 +3 ropt_net_194:3 5.501414e-05 +4 ropt_net_194:4 0.0001322994 +5 ropt_net_194:5 0.0001322994 +6 ropt_net_194:6 0.000234937 +7 ropt_net_194:7 0.00026107 +8 ropt_net_194:8 0.0001816032 +9 ropt_net_194:9 0.0001554702 +10 ropt_net_194:2 chany_top_in[16]:13 3.410263e-06 +11 ropt_net_194:3 chany_top_in[16]:14 3.410263e-06 +12 ropt_net_194:4 chany_top_in[16]:15 5.211605e-05 +13 ropt_net_194:5 chany_top_in[16]:16 5.211605e-05 +14 ropt_net_194:4 ropt_net_227:5 7.488023e-08 +15 ropt_net_194:6 ropt_net_227:2 6.139318e-05 +16 ropt_net_194:5 ropt_net_227:4 7.488023e-08 +17 ropt_net_194:7 ropt_net_227:3 6.139318e-05 +18 ropt_net_194:4 ccff_tail[0]:5 2.04283e-07 +19 ropt_net_194:5 ccff_tail[0]:6 2.04283e-07 +20 ropt_net_194:9 ccff_tail[0]:8 5.617835e-05 +21 ropt_net_194:8 ccff_tail[0]:7 5.617835e-05 + +*RES +0 mux_bottom_track_9\/BUFT_P_143:X ropt_net_194:9 0.152 +1 ropt_net_194:2 ropt_mt_inst_815:A 0.152 +2 ropt_net_194:3 ropt_net_194:2 0.0003370536 +3 ropt_net_194:4 ropt_net_194:3 0.0045 +4 ropt_net_194:6 ropt_net_194:5 0.0045 +5 ropt_net_194:5 ropt_net_194:4 0.002044643 +6 ropt_net_194:9 ropt_net_194:8 0.002198661 +7 ropt_net_194:7 ropt_net_194:6 0.002834822 +8 ropt_net_194:8 ropt_net_194:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_2_ccff_tail[0] 0.000664037 //LENGTH 4.865 LUMPCC 0.0001136435 DR + +*CONN +*I mem_right_track_20\/FTB_25__55:X O *L 0 *C 63.290 72.760 +*I mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.015 75.140 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 *C 65.015 75.140 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 *C 64.860 75.140 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 *C 64.860 75.095 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 *C 64.860 72.805 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 *C 64.815 72.760 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 *C 63.328 72.760 + +*CAP +0 mem_right_track_20\/FTB_25__55:X 1e-06 +1 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 4.862314e-05 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 5.295717e-05 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.0001073957 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0001073957 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.0001160108 +7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.0001160108 +8 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 prog_clk[0]:238 1.285812e-06 +9 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 prog_clk[0]:244 5.553594e-05 +10 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 prog_clk[0]:237 1.285812e-06 +11 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 prog_clk[0]:241 5.553594e-05 + +*RES +0 mem_right_track_20\/FTB_25__55:X mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.001328125 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 8.423914e-05 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 mem_right_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[1] 0.002181221 //LENGTH 16.115 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 52.285 82.620 +*I mux_top_track_32\/mux_l2_in_1_:S I *L 0.00357 *C 52.340 85.000 +*I mux_top_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 56.940 80.240 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 57.670 82.620 +*N mux_tree_tapbuf_size4_1_sram[1]:4 *C 57.633 82.620 +*N mux_tree_tapbuf_size4_1_sram[1]:5 *C 55.660 82.620 +*N mux_tree_tapbuf_size4_1_sram[1]:6 *C 55.660 82.280 +*N mux_tree_tapbuf_size4_1_sram[1]:7 *C 53.820 82.280 +*N mux_tree_tapbuf_size4_1_sram[1]:8 *C 56.903 80.240 +*N mux_tree_tapbuf_size4_1_sram[1]:9 *C 55.660 80.240 +*N mux_tree_tapbuf_size4_1_sram[1]:10 *C 55.660 80.580 +*N mux_tree_tapbuf_size4_1_sram[1]:11 *C 53.865 80.580 +*N mux_tree_tapbuf_size4_1_sram[1]:12 *C 53.820 80.625 +*N mux_tree_tapbuf_size4_1_sram[1]:13 *C 53.820 82.575 +*N mux_tree_tapbuf_size4_1_sram[1]:14 *C 53.820 82.590 +*N mux_tree_tapbuf_size4_1_sram[1]:15 *C 52.340 85.000 +*N mux_tree_tapbuf_size4_1_sram[1]:16 *C 52.440 84.955 +*N mux_tree_tapbuf_size4_1_sram[1]:17 *C 52.440 82.665 +*N mux_tree_tapbuf_size4_1_sram[1]:18 *C 52.485 82.620 +*N mux_tree_tapbuf_size4_1_sram[1]:19 *C 52.285 82.620 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_32\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_32\/mux_l2_in_0_:S 1e-06 +3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size4_1_sram[1]:4 0.0001733042 +5 mux_tree_tapbuf_size4_1_sram[1]:5 0.0002030329 +6 mux_tree_tapbuf_size4_1_sram[1]:6 0.000179133 +7 mux_tree_tapbuf_size4_1_sram[1]:7 0.0001793798 +8 mux_tree_tapbuf_size4_1_sram[1]:8 0.0001053337 +9 mux_tree_tapbuf_size4_1_sram[1]:9 0.0001309681 +10 mux_tree_tapbuf_size4_1_sram[1]:10 0.0001887134 +11 mux_tree_tapbuf_size4_1_sram[1]:11 0.0001630789 +12 mux_tree_tapbuf_size4_1_sram[1]:12 0.0001280002 +13 mux_tree_tapbuf_size4_1_sram[1]:13 0.0001280002 +14 mux_tree_tapbuf_size4_1_sram[1]:14 0.0001237712 +15 mux_tree_tapbuf_size4_1_sram[1]:15 2.87772e-05 +16 mux_tree_tapbuf_size4_1_sram[1]:16 0.0001429298 +17 mux_tree_tapbuf_size4_1_sram[1]:17 0.0001429298 +18 mux_tree_tapbuf_size4_1_sram[1]:18 0.0001134947 +19 mux_tree_tapbuf_size4_1_sram[1]:19 4.63746e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_1_sram[1]:19 0.152 +1 mux_tree_tapbuf_size4_1_sram[1]:4 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:13 0.0045 +3 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:7 0.0002767858 +4 mux_tree_tapbuf_size4_1_sram[1]:13 mux_tree_tapbuf_size4_1_sram[1]:12 0.001741071 +5 mux_tree_tapbuf_size4_1_sram[1]:11 mux_tree_tapbuf_size4_1_sram[1]:10 0.001602678 +6 mux_tree_tapbuf_size4_1_sram[1]:12 mux_tree_tapbuf_size4_1_sram[1]:11 0.0045 +7 mux_tree_tapbuf_size4_1_sram[1]:8 mux_top_track_32\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_1_sram[1]:19 mux_tree_tapbuf_size4_1_sram[1]:18 0.0001086957 +9 mux_tree_tapbuf_size4_1_sram[1]:18 mux_tree_tapbuf_size4_1_sram[1]:17 0.0045 +10 mux_tree_tapbuf_size4_1_sram[1]:18 mux_tree_tapbuf_size4_1_sram[1]:14 0.001191964 +11 mux_tree_tapbuf_size4_1_sram[1]:17 mux_tree_tapbuf_size4_1_sram[1]:16 0.002044643 +12 mux_tree_tapbuf_size4_1_sram[1]:15 mux_top_track_32\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:9 0.0003035715 +15 mux_tree_tapbuf_size4_1_sram[1]:7 mux_tree_tapbuf_size4_1_sram[1]:6 0.001642857 +16 mux_tree_tapbuf_size4_1_sram[1]:6 mux_tree_tapbuf_size4_1_sram[1]:5 0.0003035715 +17 mux_tree_tapbuf_size4_1_sram[1]:9 mux_tree_tapbuf_size4_1_sram[1]:8 0.001109375 +18 mux_tree_tapbuf_size4_1_sram[1]:5 mux_tree_tapbuf_size4_1_sram[1]:4 0.001761161 + +*END + +*D_NET mux_tree_tapbuf_size4_5_sram[0] 0.001228818 //LENGTH 9.870 LUMPCC 0 DR + +*CONN +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 73.445 91.120 +*I mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 71.015 88.060 +*I mux_right_track_14\/mux_l1_in_0_:S I *L 0.00357 *C 72.560 94.180 +*N mux_tree_tapbuf_size4_5_sram[0]:3 *C 72.560 94.180 +*N mux_tree_tapbuf_size4_5_sram[0]:4 *C 72.680 94.135 +*N mux_tree_tapbuf_size4_5_sram[0]:5 *C 71.053 88.060 +*N mux_tree_tapbuf_size4_5_sram[0]:6 *C 72.635 88.060 +*N mux_tree_tapbuf_size4_5_sram[0]:7 *C 72.680 88.105 +*N mux_tree_tapbuf_size4_5_sram[0]:8 *C 72.680 90.780 +*N mux_tree_tapbuf_size4_5_sram[0]:9 *C 73.095 90.780 +*N mux_tree_tapbuf_size4_5_sram[0]:10 *C 73.110 91.090 +*N mux_tree_tapbuf_size4_5_sram[0]:11 *C 73.140 91.120 +*N mux_tree_tapbuf_size4_5_sram[0]:12 *C 73.445 91.120 + +*CAP +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_14\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_5_sram[0]:3 2.839931e-05 +4 mux_tree_tapbuf_size4_5_sram[0]:4 0.0001887612 +5 mux_tree_tapbuf_size4_5_sram[0]:5 0.0001196252 +6 mux_tree_tapbuf_size4_5_sram[0]:6 0.0001196252 +7 mux_tree_tapbuf_size4_5_sram[0]:7 0.0001699775 +8 mux_tree_tapbuf_size4_5_sram[0]:8 0.0003889879 +9 mux_tree_tapbuf_size4_5_sram[0]:9 7.043171e-05 +10 mux_tree_tapbuf_size4_5_sram[0]:10 4.018257e-05 +11 mux_tree_tapbuf_size4_5_sram[0]:11 5.212915e-05 +12 mux_tree_tapbuf_size4_5_sram[0]:12 4.769856e-05 + +*RES +0 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_5_sram[0]:12 0.152 +1 mux_tree_tapbuf_size4_5_sram[0]:3 mux_right_track_14\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_5_sram[0]:4 mux_tree_tapbuf_size4_5_sram[0]:3 0.0045 +3 mux_tree_tapbuf_size4_5_sram[0]:6 mux_tree_tapbuf_size4_5_sram[0]:5 0.001412946 +4 mux_tree_tapbuf_size4_5_sram[0]:7 mux_tree_tapbuf_size4_5_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size4_5_sram[0]:5 mem_right_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size4_5_sram[0]:11 mux_tree_tapbuf_size4_5_sram[0]:10 0.0045 +7 mux_tree_tapbuf_size4_5_sram[0]:10 mux_tree_tapbuf_size4_5_sram[0]:9 0.00019375 +8 mux_tree_tapbuf_size4_5_sram[0]:12 mux_tree_tapbuf_size4_5_sram[0]:11 0.0001657609 +9 mux_tree_tapbuf_size4_5_sram[0]:8 mux_tree_tapbuf_size4_5_sram[0]:7 0.002388393 +10 mux_tree_tapbuf_size4_5_sram[0]:8 mux_tree_tapbuf_size4_5_sram[0]:4 0.002995536 +11 mux_tree_tapbuf_size4_5_sram[0]:9 mux_tree_tapbuf_size4_5_sram[0]:8 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_5_ccff_tail[0] 0.001224725 //LENGTH 9.470 LUMPCC 0.0003089948 DR + +*CONN +*I mem_right_track_14\/FTB_18__48:X O *L 0 *C 94.535 88.060 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 88.035 86.020 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 *C 88.073 86.020 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 *C 89.655 86.020 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:4 *C 89.700 86.065 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:5 *C 89.700 88.015 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 *C 89.745 88.060 +*N mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 *C 94.498 88.060 + +*CAP +0 mem_right_track_14\/FTB_18__48:X 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 8.939672e-05 +3 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 8.939672e-05 +4 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:4 0.0001269896 +5 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:5 0.0001269896 +6 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 0.0002404787 +7 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 0.0002404787 +8 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size4_5_sram[2]:4 8.137173e-05 +9 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size4_5_sram[2]:3 8.137173e-05 +10 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.312565e-05 +11 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.312565e-05 + +*RES +0 mem_right_track_14\/FTB_18__48:X mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 0.001412946 +3 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:6 0.004243304 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[0] 0.003917282 //LENGTH 27.933 LUMPCC 0.0003045009 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.985 72.080 +*I mux_top_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 46.100 69.070 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 34.215 71.740 +*I mux_top_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 39.200 67.320 +*N mux_tree_tapbuf_size5_1_sram[0]:4 *C 39.238 67.320 +*N mux_tree_tapbuf_size5_1_sram[0]:5 *C 40.895 67.320 +*N mux_tree_tapbuf_size5_1_sram[0]:6 *C 40.940 67.365 +*N mux_tree_tapbuf_size5_1_sram[0]:7 *C 34.215 71.740 +*N mux_tree_tapbuf_size5_1_sram[0]:8 *C 34.500 71.740 +*N mux_tree_tapbuf_size5_1_sram[0]:9 *C 34.500 71.695 +*N mux_tree_tapbuf_size5_1_sram[0]:10 *C 34.500 68.737 +*N mux_tree_tapbuf_size5_1_sram[0]:11 *C 34.508 68.680 +*N mux_tree_tapbuf_size5_1_sram[0]:12 *C 40.933 68.680 +*N mux_tree_tapbuf_size5_1_sram[0]:13 *C 40.940 68.680 +*N mux_tree_tapbuf_size5_1_sram[0]:14 *C 40.985 68.680 +*N mux_tree_tapbuf_size5_1_sram[0]:15 *C 46.100 68.680 +*N mux_tree_tapbuf_size5_1_sram[0]:16 *C 46.100 69.070 +*N mux_tree_tapbuf_size5_1_sram[0]:17 *C 46.070 69.430 +*N mux_tree_tapbuf_size5_1_sram[0]:18 *C 45.955 69.290 +*N mux_tree_tapbuf_size5_1_sram[0]:19 *C 46.000 69.700 +*N mux_tree_tapbuf_size5_1_sram[0]:20 *C 49.635 69.700 +*N mux_tree_tapbuf_size5_1_sram[0]:21 *C 49.680 69.745 +*N mux_tree_tapbuf_size5_1_sram[0]:22 *C 49.680 72.035 +*N mux_tree_tapbuf_size5_1_sram[0]:23 *C 49.680 72.080 +*N mux_tree_tapbuf_size5_1_sram[0]:24 *C 49.985 72.080 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_16\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_16\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[0]:4 0.0001451939 +5 mux_tree_tapbuf_size5_1_sram[0]:5 0.0001451939 +6 mux_tree_tapbuf_size5_1_sram[0]:6 7.911424e-05 +7 mux_tree_tapbuf_size5_1_sram[0]:7 5.018968e-05 +8 mux_tree_tapbuf_size5_1_sram[0]:8 5.191338e-05 +9 mux_tree_tapbuf_size5_1_sram[0]:9 0.0002091364 +10 mux_tree_tapbuf_size5_1_sram[0]:10 0.0002091364 +11 mux_tree_tapbuf_size5_1_sram[0]:11 0.0004302278 +12 mux_tree_tapbuf_size5_1_sram[0]:12 0.0004302278 +13 mux_tree_tapbuf_size5_1_sram[0]:13 0.0001144665 +14 mux_tree_tapbuf_size5_1_sram[0]:14 0.0002630605 +15 mux_tree_tapbuf_size5_1_sram[0]:15 0.0002916795 +16 mux_tree_tapbuf_size5_1_sram[0]:16 8.09445e-05 +17 mux_tree_tapbuf_size5_1_sram[0]:17 2.953909e-05 +18 mux_tree_tapbuf_size5_1_sram[0]:18 2.772687e-05 +19 mux_tree_tapbuf_size5_1_sram[0]:19 0.0003317787 +20 mux_tree_tapbuf_size5_1_sram[0]:20 0.0003079296 +21 mux_tree_tapbuf_size5_1_sram[0]:21 0.000145019 +22 mux_tree_tapbuf_size5_1_sram[0]:22 0.000145019 +23 mux_tree_tapbuf_size5_1_sram[0]:23 6.206563e-05 +24 mux_tree_tapbuf_size5_1_sram[0]:24 5.921899e-05 +25 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0001501692 +26 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 2.081201e-06 +27 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 2.081201e-06 +28 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0001501692 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_1_sram[0]:24 0.152 +1 mux_tree_tapbuf_size5_1_sram[0]:24 mux_tree_tapbuf_size5_1_sram[0]:23 0.0001657609 +2 mux_tree_tapbuf_size5_1_sram[0]:23 mux_tree_tapbuf_size5_1_sram[0]:22 0.0045 +3 mux_tree_tapbuf_size5_1_sram[0]:22 mux_tree_tapbuf_size5_1_sram[0]:21 0.002044643 +4 mux_tree_tapbuf_size5_1_sram[0]:20 mux_tree_tapbuf_size5_1_sram[0]:19 0.003245536 +5 mux_tree_tapbuf_size5_1_sram[0]:21 mux_tree_tapbuf_size5_1_sram[0]:20 0.0045 +6 mux_tree_tapbuf_size5_1_sram[0]:16 mux_top_track_16\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:15 0.0003482143 +8 mux_tree_tapbuf_size5_1_sram[0]:5 mux_tree_tapbuf_size5_1_sram[0]:4 0.001479911 +9 mux_tree_tapbuf_size5_1_sram[0]:6 mux_tree_tapbuf_size5_1_sram[0]:5 0.0045 +10 mux_tree_tapbuf_size5_1_sram[0]:4 mux_top_track_16\/mux_l1_in_1_:S 0.152 +11 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size5_1_sram[0]:13 0.0045 +12 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:12 0.00341 +13 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:6 0.001174107 +14 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size5_1_sram[0]:11 0.001006583 +15 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size5_1_sram[0]:9 0.002640625 +16 mux_tree_tapbuf_size5_1_sram[0]:11 mux_tree_tapbuf_size5_1_sram[0]:10 0.00341 +17 mux_tree_tapbuf_size5_1_sram[0]:8 mux_tree_tapbuf_size5_1_sram[0]:7 0.0001548913 +18 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:8 0.0045 +19 mux_tree_tapbuf_size5_1_sram[0]:7 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:14 0.004566965 +21 mux_tree_tapbuf_size5_1_sram[0]:19 mux_tree_tapbuf_size5_1_sram[0]:18 0.0003660714 +22 mux_tree_tapbuf_size5_1_sram[0]:18 mux_tree_tapbuf_size5_1_sram[0]:17 0.0001026786 +23 mux_tree_tapbuf_size5_1_sram[0]:17 mux_tree_tapbuf_size5_1_sram[0]:16 0.0002093024 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_4_ccff_tail[0] 0.001147699 //LENGTH 9.470 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_25\/FTB_12__42:X O *L 0 *C 35.185 44.200 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.815 39.100 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 *C 38.815 39.100 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 *C 38.640 39.100 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 *C 38.640 39.145 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 *C 38.640 44.155 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 *C 38.595 44.200 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 *C 35.223 44.200 + +*CAP +0 mem_bottom_track_25\/FTB_12__42:X 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 5.332323e-05 +3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 5.567849e-05 +4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 0.0002788522 +5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 0.0002788522 +6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 0.0002394965 +7 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 0.0002394965 + +*RES +0 mem_bottom_track_25\/FTB_12__42:X mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 0.004473215 +6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 0.003011161 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.005920165 //LENGTH 44.110 LUMPCC 0.0007085869 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 92.555 49.640 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 79.755 47.940 +*I mux_top_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 75.800 55.760 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 87.500 45.175 +*I mux_top_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 84.280 41.480 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 87.400 45.210 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 84.318 41.480 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 87.355 41.480 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 87.400 41.525 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 87.400 44.835 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 87.400 44.880 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 87.413 45.233 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 75.800 55.760 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 75.900 55.715 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 75.900 48.620 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 76.360 48.620 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 76.360 45.617 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 76.368 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 79.755 47.940 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 80.040 47.940 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 80.040 47.895 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 80.040 45.617 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 80.040 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:23 *C 84.172 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:24 *C 84.180 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:25 *C 84.225 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:26 *C 87.400 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:27 *C 90.575 45.560 +*N mux_tree_tapbuf_size6_1_sram[0]:28 *C 90.620 45.605 +*N mux_tree_tapbuf_size6_1_sram[0]:29 *C 90.620 49.595 +*N mux_tree_tapbuf_size6_1_sram[0]:30 *C 90.665 49.640 +*N mux_tree_tapbuf_size6_1_sram[0]:31 *C 92.517 49.640 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_4\/mux_l1_in_2_:S 1e-06 +3 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +4 mux_top_track_4\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 1.406714e-05 +6 mux_tree_tapbuf_size6_1_sram[0]:6 0.0002477225 +7 mux_tree_tapbuf_size6_1_sram[0]:7 0.0002477225 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0001949085 +9 mux_tree_tapbuf_size6_1_sram[0]:9 0.0001949085 +10 mux_tree_tapbuf_size6_1_sram[0]:10 6.025659e-05 +11 mux_tree_tapbuf_size6_1_sram[0]:11 6.171782e-05 +12 mux_tree_tapbuf_size6_1_sram[0]:12 2.987958e-05 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0004277135 +14 mux_tree_tapbuf_size6_1_sram[0]:14 0.0004609224 +15 mux_tree_tapbuf_size6_1_sram[0]:15 0.0002187948 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.0001855859 +17 mux_tree_tapbuf_size6_1_sram[0]:17 0.0002058972 +18 mux_tree_tapbuf_size6_1_sram[0]:18 5.548718e-05 +19 mux_tree_tapbuf_size6_1_sram[0]:19 5.972959e-05 +20 mux_tree_tapbuf_size6_1_sram[0]:20 0.0001360973 +21 mux_tree_tapbuf_size6_1_sram[0]:21 0.0001360973 +22 mux_tree_tapbuf_size6_1_sram[0]:22 0.0004260716 +23 mux_tree_tapbuf_size6_1_sram[0]:23 0.0002201744 +24 mux_tree_tapbuf_size6_1_sram[0]:24 4.116159e-05 +25 mux_tree_tapbuf_size6_1_sram[0]:25 0.000155022 +26 mux_tree_tapbuf_size6_1_sram[0]:26 0.000420418 +27 mux_tree_tapbuf_size6_1_sram[0]:27 0.0002435913 +28 mux_tree_tapbuf_size6_1_sram[0]:28 0.0002475937 +29 mux_tree_tapbuf_size6_1_sram[0]:29 0.0002475937 +30 mux_tree_tapbuf_size6_1_sram[0]:30 0.0001337221 +31 mux_tree_tapbuf_size6_1_sram[0]:31 0.0001337221 +32 mux_tree_tapbuf_size6_1_sram[0]:17 prog_clk[0]:146 2.289348e-05 +33 mux_tree_tapbuf_size6_1_sram[0]:17 prog_clk[0]:161 2.494643e-05 +34 mux_tree_tapbuf_size6_1_sram[0]:23 prog_clk[0]:138 0.0001893536 +35 mux_tree_tapbuf_size6_1_sram[0]:23 prog_clk[0]:142 8.543936e-06 +36 mux_tree_tapbuf_size6_1_sram[0]:27 prog_clk[0]:136 6.379977e-07 +37 mux_tree_tapbuf_size6_1_sram[0]:21 prog_clk[0]:140 2.139922e-05 +38 mux_tree_tapbuf_size6_1_sram[0]:22 prog_clk[0]:139 0.0001893536 +39 mux_tree_tapbuf_size6_1_sram[0]:22 prog_clk[0]:142 2.289348e-05 +40 mux_tree_tapbuf_size6_1_sram[0]:22 prog_clk[0]:146 3.349036e-05 +41 mux_tree_tapbuf_size6_1_sram[0]:20 prog_clk[0]:141 2.139922e-05 +42 mux_tree_tapbuf_size6_1_sram[0]:26 prog_clk[0]:135 6.379977e-07 +43 mux_tree_tapbuf_size6_1_sram[0]:25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.651878e-05 +44 mux_tree_tapbuf_size6_1_sram[0]:26 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.651878e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:31 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.002680804 +2 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:16 0.00341 +3 mux_tree_tapbuf_size6_1_sram[0]:12 mux_top_track_4\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size6_1_sram[0]:11 mux_top_track_4\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 0.0001398809 +7 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:5 1e-05 +8 mux_tree_tapbuf_size6_1_sram[0]:25 mux_tree_tapbuf_size6_1_sram[0]:24 0.0045 +9 mux_tree_tapbuf_size6_1_sram[0]:24 mux_tree_tapbuf_size6_1_sram[0]:23 0.00341 +10 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:22 0.000647425 +11 mux_tree_tapbuf_size6_1_sram[0]:31 mux_tree_tapbuf_size6_1_sram[0]:30 0.001654018 +12 mux_tree_tapbuf_size6_1_sram[0]:30 mux_tree_tapbuf_size6_1_sram[0]:29 0.0045 +13 mux_tree_tapbuf_size6_1_sram[0]:29 mux_tree_tapbuf_size6_1_sram[0]:28 0.0035625 +14 mux_tree_tapbuf_size6_1_sram[0]:27 mux_tree_tapbuf_size6_1_sram[0]:26 0.002834822 +15 mux_tree_tapbuf_size6_1_sram[0]:28 mux_tree_tapbuf_size6_1_sram[0]:27 0.0045 +16 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.002033482 +17 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:21 0.00341 +18 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:17 0.0005753583 +19 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001548913 +20 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.0045 +21 mux_tree_tapbuf_size6_1_sram[0]:18 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size6_1_sram[0]:10 mux_tree_tapbuf_size6_1_sram[0]:9 0.0045 +23 mux_tree_tapbuf_size6_1_sram[0]:9 mux_tree_tapbuf_size6_1_sram[0]:8 0.002955357 +24 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.002712054 +25 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.0045 +26 mux_tree_tapbuf_size6_1_sram[0]:6 mux_top_track_4\/mux_l1_in_1_:S 0.152 +27 mux_tree_tapbuf_size6_1_sram[0]:26 mux_tree_tapbuf_size6_1_sram[0]:25 0.002834821 +28 mux_tree_tapbuf_size6_1_sram[0]:26 mux_tree_tapbuf_size6_1_sram[0]:11 0.0002924107 +29 mux_tree_tapbuf_size6_1_sram[0]:14 mux_tree_tapbuf_size6_1_sram[0]:13 0.006334822 +30 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.0009010293 //LENGTH 7.320 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/FTB_2__32:X O *L 0 *C 77.505 66.300 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 73.315 64.260 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 73.315 64.260 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 73.140 64.260 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 73.140 64.305 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 73.140 66.255 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 73.185 66.300 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 77.468 66.300 + +*CAP +0 mem_top_track_4\/FTB_2__32:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 5.714489e-05 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 6.266903e-05 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.0001225624 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0001225624 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.0002670453 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.0002670453 + +*RES +0 mem_top_track_4\/FTB_2__32:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.001741071 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.003823661 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_6_ccff_tail[0] 0.0007322191 //LENGTH 5.105 LUMPCC 0.0002473527 DR + +*CONN +*I mem_bottom_track_9\/FTB_7__37:X O *L 0 *C 94.515 42.840 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 92.180 44.540 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:2 *C 92.203 44.513 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:3 *C 92.203 44.235 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:4 *C 92.430 44.230 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 *C 92.460 44.155 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 *C 92.460 42.885 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 *C 92.505 42.840 +*N mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 *C 94.478 42.840 + +*CAP +0 mem_bottom_track_9\/FTB_7__37:X 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:2 2.993354e-05 +3 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:3 6.696775e-05 +4 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:4 3.703421e-05 +5 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 7.168879e-05 +6 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 7.168879e-05 +7 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 0.0001027767 +8 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 0.0001027767 +9 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 prog_clk[0]:132 4.191712e-05 +10 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 prog_clk[0]:133 4.191712e-05 +11 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.175922e-05 +12 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.175922e-05 + +*RES +0 mem_bottom_track_9\/FTB_7__37:X mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:8 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 0.001761161 +2 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 0.001133929 +4 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:3 0.0001421875 +5 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_6_ccff_tail[0]:2 0.0001875 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_2_ccff_tail[0] 0.0006398987 //LENGTH 4.840 LUMPCC 0.0001579878 DR + +*CONN +*I mem_right_track_6\/FTB_22__52:X O *L 0 *C 51.285 112.540 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 49.855 109.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 *C 49.893 109.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 *C 51.015 109.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 *C 51.060 109.865 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 *C 51.060 112.495 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 *C 51.060 112.540 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 *C 51.285 112.540 + +*CAP +0 mem_right_track_6\/FTB_22__52:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 9.625558e-05 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 9.625558e-05 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 8.959993e-05 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 8.959993e-05 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 5.453356e-05 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 5.366632e-05 +8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 chany_top_in[9]:24 3.949695e-05 +9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 chany_top_in[9] 3.949695e-05 +10 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 chany_top_in[10]:18 3.949695e-05 +11 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 chany_top_in[10] 3.949695e-05 + +*RES +0 mem_right_track_6\/FTB_22__52:X mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.001002232 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008981214 //LENGTH 6.650 LUMPCC 0.0001879444 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_1_:X O *L 0 *C 88.605 71.400 +*I mux_top_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 89.070 66.300 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 89.070 66.300 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 89.240 66.300 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 89.240 66.345 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 89.240 71.355 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 89.195 71.400 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 88.642 71.400 + +*CAP +0 mux_top_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.40169e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.805731e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002316075 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002316075 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.644392e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.644392e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_bottom_in[13]:8 5.656061e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[13]:6 5.656061e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:99 1.525781e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:100 2.215379e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:96 1.525781e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:99 2.215379e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239132e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473215 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET optlc_net_184 0.01209303 //LENGTH 99.927 LUMPCC 0.000721888 DR + +*CONN +*I optlc_173:HI O *L 0 *C 40.940 82.620 +*I mux_right_track_10\/mux_l2_in_1_:A0 I *L 0.001631 *C 33.755 87.720 +*I mux_top_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 28.350 87.720 +*I mux_right_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 34.215 102.340 +*I mux_right_track_22\/mux_l1_in_1_:A0 I *L 0.001631 *C 51.695 80.580 +*I mux_top_track_32\/mux_l2_in_1_:A0 I *L 0.001631 *C 51.235 86.020 +*I mux_right_track_12\/mux_l2_in_1_:A0 I *L 0.001631 *C 56.295 88.060 +*I mux_top_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 27.890 71.740 +*I mux_right_track_26\/mux_l2_in_0_:A0 I *L 0.001631 *C 43.415 64.260 +*N optlc_net_184:9 *C 43.378 64.260 +*N optlc_net_184:10 *C 41.905 64.260 +*N optlc_net_184:11 *C 41.860 64.305 +*N optlc_net_184:12 *C 41.860 74.800 +*N optlc_net_184:13 *C 27.928 71.740 +*N optlc_net_184:14 *C 32.155 71.740 +*N optlc_net_184:15 *C 32.200 71.785 +*N optlc_net_184:16 *C 32.200 74.755 +*N optlc_net_184:17 *C 32.245 74.800 +*N optlc_net_184:18 *C 41.355 74.800 +*N optlc_net_184:19 *C 41.400 74.800 +*N optlc_net_184:20 *C 41.400 82.960 +*N optlc_net_184:21 *C 56.258 88.060 +*N optlc_net_184:22 *C 52.485 88.060 +*N optlc_net_184:23 *C 52.440 88.015 +*N optlc_net_184:24 *C 52.440 86.065 +*N optlc_net_184:25 *C 52.395 86.020 +*N optlc_net_184:26 *C 51.273 86.020 +*N optlc_net_184:27 *C 51.658 80.580 +*N optlc_net_184:28 *C 51.105 80.580 +*N optlc_net_184:29 *C 51.060 80.625 +*N optlc_net_184:30 *C 51.060 85.975 +*N optlc_net_184:31 *C 51.193 86.020 +*N optlc_net_184:32 *C 43.700 86.020 +*N optlc_net_184:33 *C 43.700 86.360 +*N optlc_net_184:34 *C 40.940 86.360 +*N optlc_net_184:35 *C 34.215 102.340 +*N optlc_net_184:36 *C 34.500 102.340 +*N optlc_net_184:37 *C 34.500 102.295 +*N optlc_net_184:38 *C 28.388 87.720 +*N optlc_net_184:39 *C 33.755 87.720 +*N optlc_net_184:40 *C 34.455 87.720 +*N optlc_net_184:41 *C 34.500 87.720 +*N optlc_net_184:42 *C 34.500 86.065 +*N optlc_net_184:43 *C 34.545 86.020 +*N optlc_net_184:44 *C 40.940 86.020 +*N optlc_net_184:45 *C 40.940 85.680 +*N optlc_net_184:46 *C 40.940 85.635 +*N optlc_net_184:47 *C 40.940 82.960 +*N optlc_net_184:48 *C 40.970 82.650 +*N optlc_net_184:49 *C 40.940 82.620 + +*CAP +0 optlc_173:HI 1e-06 +1 mux_right_track_10\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_24\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_8\/mux_l2_in_1_:A0 1e-06 +4 mux_right_track_22\/mux_l1_in_1_:A0 1e-06 +5 mux_top_track_32\/mux_l2_in_1_:A0 1e-06 +6 mux_right_track_12\/mux_l2_in_1_:A0 1e-06 +7 mux_top_track_16\/mux_l2_in_1_:A0 1e-06 +8 mux_right_track_26\/mux_l2_in_0_:A0 1e-06 +9 optlc_net_184:9 0.0001050929 +10 optlc_net_184:10 0.0001050929 +11 optlc_net_184:11 0.0005836543 +12 optlc_net_184:12 0.0005988053 +13 optlc_net_184:13 0.0002254726 +14 optlc_net_184:14 0.0002254726 +15 optlc_net_184:15 0.000150664 +16 optlc_net_184:16 0.000150664 +17 optlc_net_184:17 0.0003738209 +18 optlc_net_184:18 0.0003738209 +19 optlc_net_184:19 0.0005458007 +20 optlc_net_184:20 0.0005599263 +21 optlc_net_184:21 0.000243376 +22 optlc_net_184:22 0.000243376 +23 optlc_net_184:23 0.0001315536 +24 optlc_net_184:24 0.0001315536 +25 optlc_net_184:25 7.723368e-05 +26 optlc_net_184:26 9.84693e-05 +27 optlc_net_184:27 3.838801e-05 +28 optlc_net_184:28 3.838801e-05 +29 optlc_net_184:29 0.0003983196 +30 optlc_net_184:30 0.0003983196 +31 optlc_net_184:31 0.0004114711 +32 optlc_net_184:32 0.0004174156 +33 optlc_net_184:33 0.0002325434 +34 optlc_net_184:34 0.0002277062 +35 optlc_net_184:35 5.124017e-05 +36 optlc_net_184:36 5.683476e-05 +37 optlc_net_184:37 0.0008007303 +38 optlc_net_184:38 0.0003574081 +39 optlc_net_184:39 0.0004447619 +40 optlc_net_184:40 6.055401e-05 +41 optlc_net_184:41 0.0009346561 +42 optlc_net_184:42 0.0001012657 +43 optlc_net_184:43 0.0004662419 +44 optlc_net_184:44 0.000514544 +45 optlc_net_184:45 6.155818e-05 +46 optlc_net_184:46 0.0001635129 +47 optlc_net_184:47 0.0002094237 +48 optlc_net_184:48 1.663405e-05 +49 optlc_net_184:49 3.637975e-05 +50 optlc_net_184:28 chany_bottom_in[17]:11 1.64812e-05 +51 optlc_net_184:27 chany_bottom_in[17]:10 1.64812e-05 +52 optlc_net_184:18 chany_bottom_in[17]:14 0.0001682247 +53 optlc_net_184:19 chany_bottom_in[17]:15 1.794396e-05 +54 optlc_net_184:17 chany_bottom_in[17]:15 0.0001682247 +55 optlc_net_184:16 chany_bottom_in[17]:16 2.995227e-05 +56 optlc_net_184:16 chany_bottom_in[17]:21 6.961201e-07 +57 optlc_net_184:14 chany_bottom_in[17]:18 2.468403e-05 +58 optlc_net_184:14 chany_bottom_in[17]:20 3.325636e-05 +59 optlc_net_184:15 chany_bottom_in[17]:17 2.995227e-05 +60 optlc_net_184:15 chany_bottom_in[17]:22 6.961201e-07 +61 optlc_net_184:13 chany_bottom_in[17]:19 3.325636e-05 +62 optlc_net_184:13 chany_bottom_in[17]:20 2.468403e-05 +63 optlc_net_184:12 chany_bottom_in[17]:14 1.794396e-05 +64 optlc_net_184:31 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 6.970539e-05 +65 optlc_net_184:32 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 6.970539e-05 + +*RES +0 optlc_173:HI optlc_net_184:49 0.152 +1 optlc_net_184:45 optlc_net_184:44 0.0003035715 +2 optlc_net_184:46 optlc_net_184:45 0.0045 +3 optlc_net_184:31 optlc_net_184:30 0.0045 +4 optlc_net_184:31 optlc_net_184:26 7.142857e-05 +5 optlc_net_184:30 optlc_net_184:29 0.004776786 +6 optlc_net_184:28 optlc_net_184:27 0.0004933036 +7 optlc_net_184:29 optlc_net_184:28 0.0045 +8 optlc_net_184:27 mux_right_track_22\/mux_l1_in_1_:A0 0.152 +9 optlc_net_184:40 optlc_net_184:39 0.000625 +10 optlc_net_184:41 optlc_net_184:40 0.0045 +11 optlc_net_184:41 optlc_net_184:37 0.01301339 +12 optlc_net_184:43 optlc_net_184:42 0.0045 +13 optlc_net_184:42 optlc_net_184:41 0.001477679 +14 optlc_net_184:18 optlc_net_184:17 0.008133929 +15 optlc_net_184:19 optlc_net_184:18 0.0045 +16 optlc_net_184:19 optlc_net_184:12 0.0004107143 +17 optlc_net_184:17 optlc_net_184:16 0.0045 +18 optlc_net_184:16 optlc_net_184:15 0.002651786 +19 optlc_net_184:14 optlc_net_184:13 0.003774554 +20 optlc_net_184:15 optlc_net_184:14 0.0045 +21 optlc_net_184:13 mux_top_track_16\/mux_l2_in_1_:A0 0.152 +22 optlc_net_184:25 optlc_net_184:24 0.0045 +23 optlc_net_184:24 optlc_net_184:23 0.001741072 +24 optlc_net_184:22 optlc_net_184:21 0.003368304 +25 optlc_net_184:23 optlc_net_184:22 0.0045 +26 optlc_net_184:21 mux_right_track_12\/mux_l2_in_1_:A0 0.152 +27 optlc_net_184:39 mux_right_track_10\/mux_l2_in_1_:A0 0.152 +28 optlc_net_184:39 optlc_net_184:38 0.004792411 +29 optlc_net_184:38 mux_top_track_24\/mux_l2_in_1_:A0 0.152 +30 optlc_net_184:10 optlc_net_184:9 0.001314732 +31 optlc_net_184:11 optlc_net_184:10 0.0045 +32 optlc_net_184:9 mux_right_track_26\/mux_l2_in_0_:A0 0.152 +33 optlc_net_184:49 optlc_net_184:48 0.0045 +34 optlc_net_184:48 optlc_net_184:47 0.00019375 +35 optlc_net_184:36 optlc_net_184:35 0.0001548913 +36 optlc_net_184:37 optlc_net_184:36 0.0045 +37 optlc_net_184:35 mux_right_track_8\/mux_l2_in_1_:A0 0.152 +38 optlc_net_184:26 mux_top_track_32\/mux_l2_in_1_:A0 0.152 +39 optlc_net_184:26 optlc_net_184:25 0.001002232 +40 optlc_net_184:44 optlc_net_184:43 0.005709822 +41 optlc_net_184:44 optlc_net_184:34 0.0003035715 +42 optlc_net_184:34 optlc_net_184:33 0.002464285 +43 optlc_net_184:33 optlc_net_184:32 0.0003035715 +44 optlc_net_184:32 optlc_net_184:31 0.006689732 +45 optlc_net_184:47 optlc_net_184:46 0.002388393 +46 optlc_net_184:47 optlc_net_184:20 0.0004107143 +47 optlc_net_184:20 optlc_net_184:19 0.007285715 +48 optlc_net_184:12 optlc_net_184:11 0.009370536 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001286524 //LENGTH 9.380 LUMPCC 0.0002116787 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_1_:X O *L 0 *C 38.355 66.980 +*I mux_top_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 32.965 70.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 33.003 70.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 33.995 70.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 34.040 69.995 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 34.040 67.025 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 34.085 66.980 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 38.318 66.980 + +*CAP +0 mux_top_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.794854e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.794854e-05 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001601944 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001601944 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003082795 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003082795 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 6.198179e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 6.198179e-05 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:16 4.385755e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:15 4.385755e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003779018 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008861608 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008622707 //LENGTH 5.065 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_1_:X O *L 0 *C 78.375 49.470 +*I mux_bottom_track_17\/mux_l3_in_0_:A0 I *L 0.005103 *C 73.600 49.470 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 73.638 49.470 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 78.338 49.470 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004301353 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004301353 + +*RES +0 mux_bottom_track_17\/mux_l2_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004196429 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003518394 //LENGTH 29.735 LUMPCC 0.00125898 DR + +*CONN +*I mux_bottom_track_25\/mux_l3_in_0_:X O *L 0 *C 57.785 44.200 +*I mux_bottom_track_25\/BUFT_RR_66:A I *L 0.001746 *C 59.800 17.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 59.763 17.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 57.545 17.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 57.500 17.725 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 57.500 44.155 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 57.500 44.200 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 57.785 44.200 + +*CAP +0 mux_bottom_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_25\/BUFT_RR_66:A 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001432924 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001432924 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0009280581 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0009280581 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.849989e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.621275e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[8]:14 0.0002856173 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[8]:21 0.0002856173 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:428 0.0001537934 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:435 7.757942e-05 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:440 0.0001125002 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:429 0.0001537934 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:440 7.757942e-05 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:441 0.0001125002 + +*RES +0 mux_bottom_track_25\/mux_l3_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_25\/BUFT_RR_66:A 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001979911 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.02359822 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000603274 //LENGTH 5.005 LUMPCC 0.00010494 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 43.875 104.380 +*I mux_right_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 40.120 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 40.157 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 40.480 105.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 40.480 104.380 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 43.837 104.380 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.015429e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.285834e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002280128 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001853087 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_2_sram[1]:16 2.118796e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_2_sram[1]:17 3.128202e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_2_sram[1]:17 2.118796e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_2_sram[1]:16 3.128202e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002997768 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002879464 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006071429 + +*END + +*D_NET mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006433761 //LENGTH 5.030 LUMPCC 0.0001196393 DR + +*CONN +*I mux_right_track_12\/mux_l2_in_0_:X O *L 0 *C 62.275 93.160 +*I mux_right_track_12\/mux_l3_in_0_:A1 I *L 0.00198 *C 62.660 88.740 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 62.560 88.740 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 62.560 88.785 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.560 93.115 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.560 93.160 +*N mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.275 93.160 + +*CAP +0 mux_right_track_12\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_12\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.961699e-05 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001932509 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001932509 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.373163e-05 +6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.188628e-05 +7 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_in[6]:13 5.981967e-05 +8 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[6]:12 5.981967e-05 + +*RES +0 mux_right_track_12\/mux_l2_in_0_:X mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_12\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003866072 +5 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001548913 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00076879 //LENGTH 6.470 LUMPCC 0.0002656167 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 30.075 63.240 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 30.820 58.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 30.820 58.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 30.820 58.185 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 30.820 63.195 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 30.775 63.240 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 30.113 63.240 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.025093e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001651943 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001651943 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.026691e-05 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.026691e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[18]:10 6.869396e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[18]:14 6.869396e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[17]:21 6.411436e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[17]:22 6.411436e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005915179 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004473215 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001317123 //LENGTH 11.010 LUMPCC 0.000224819 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_2_:X O *L 0 *C 81.245 102.340 +*I mux_right_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 79.025 110.500 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 79.062 110.500 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 80.915 110.500 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.960 110.455 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 80.960 102.385 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 80.960 102.340 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 81.245 102.340 + +*CAP +0 mux_right_track_2\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001440562 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001440562 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003388904 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003388904 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.469992e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.971089e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001124095 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001124095 + +*RES +0 mux_right_track_2\/mux_l1_in_2_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_2\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001654018 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.007205357 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001220952 //LENGTH 9.025 LUMPCC 0.0002606697 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_3_:X O *L 0 *C 73.885 104.380 +*I mux_right_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 72.970 96.900 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 73.008 96.900 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 73.555 96.900 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 73.600 96.945 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 73.600 104.335 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 73.600 104.380 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 73.885 104.380 + +*CAP +0 mux_right_track_4\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.886314e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.886314e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003598857 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003598857 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.066699e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.011822e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 right_top_grid_pin_44_[0]:14 7.047435e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 right_top_grid_pin_44_[0]:7 7.047435e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_186:17 4.615118e-06 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_186:30 4.252909e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 optlc_net_186:15 1.27163e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_186:14 4.615118e-06 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_186:17 4.252909e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 optlc_net_186:16 1.27163e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_3_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004888393 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006598215 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007928223 //LENGTH 5.630 LUMPCC 0.0003609883 DR + +*CONN +*I mux_right_track_6\/mux_l2_in_1_:X O *L 0 *C 61.355 117.640 +*I mux_right_track_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 60.895 113.560 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 60.895 113.560 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 60.720 113.560 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 60.720 113.605 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 60.720 117.595 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 60.765 117.640 +*N mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 61.318 117.640 + +*CAP +0 mux_right_track_6\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_6\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.319252e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.579982e-05 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.520802e-05 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.520802e-05 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.521281e-05 +7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.521281e-05 +8 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[6]:9 6.0181e-05 +9 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[6]:8 6.0181e-05 +10 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001203131 +11 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001203131 + +*RES +0 mux_right_track_6\/mux_l2_in_1_:X mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_6\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0035625 +6 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007953345 //LENGTH 6.115 LUMPCC 0.0001393334 DR + +*CONN +*I mux_right_track_22\/mux_l1_in_0_:X O *L 0 *C 62.275 80.240 +*I mux_right_track_22\/mux_l2_in_0_:A1 I *L 0.00198 *C 60.260 77.860 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 60.260 77.860 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.260 77.520 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.135 77.520 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 61.180 77.565 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.180 80.195 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 61.225 80.240 +*N mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 62.238 80.240 + +*CAP +0 mux_right_track_22\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_22\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.617662e-05 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000109892 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.2218e-05 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000142552 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000142552 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.030528e-05 +8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 6.030528e-05 +9 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size3_3_sram[0]:20 2.35123e-05 +10 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_3_sram[0]:19 2.35123e-05 +11 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_3_sram[0]:18 4.203413e-05 +12 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[0]:16 4.12025e-06 +13 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:17 4.203413e-05 +14 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:15 4.12025e-06 + +*RES +0 mux_right_track_22\/mux_l1_in_0_:X mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0009040179 +2 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002348214 +4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00078125 +5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_22\/mux_l2_in_0_:A1 0.152 +7 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET ropt_net_220 0.00163794 //LENGTH 11.470 LUMPCC 0.0007927727 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 59.500 3.740 +*I ropt_mt_inst_840:A I *L 0.001766 *C 54.740 9.520 +*N ropt_net_220:2 *C 54.778 9.520 +*N ropt_net_220:3 *C 55.155 9.520 +*N ropt_net_220:4 *C 55.200 9.475 +*N ropt_net_220:5 *C 55.200 3.785 +*N ropt_net_220:6 *C 55.245 3.740 +*N ropt_net_220:7 *C 59.463 3.740 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 ropt_mt_inst_840:A 1e-06 +2 ropt_net_220:2 4.355074e-05 +3 ropt_net_220:3 4.355074e-05 +4 ropt_net_220:4 0.0002006316 +5 ropt_net_220:5 0.0002006316 +6 ropt_net_220:6 0.0001774011 +7 ropt_net_220:7 0.0001774011 +8 ropt_net_220:4 chany_top_in[16]:16 0.0001128171 +9 ropt_net_220:6 chany_top_in[16]:13 3.286697e-06 +10 ropt_net_220:5 chany_top_in[16]:15 0.0001128171 +11 ropt_net_220:7 chany_top_in[16]:14 3.286697e-06 +12 ropt_net_220:4 ropt_net_197:4 7.02762e-07 +13 ropt_net_220:4 ropt_net_197:9 3.408001e-05 +14 ropt_net_220:6 ropt_net_197:3 6.944859e-05 +15 ropt_net_220:6 ropt_net_197:7 0.0001154418 +16 ropt_net_220:5 ropt_net_197:5 7.02762e-07 +17 ropt_net_220:5 ropt_net_197:8 3.408001e-05 +18 ropt_net_220:7 ropt_net_197:2 6.944859e-05 +19 ropt_net_220:7 ropt_net_197:6 0.0001154418 +20 ropt_net_220:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 6.060945e-05 +21 ropt_net_220:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 6.060945e-05 + +*RES +0 ropt_mt_inst_815:X ropt_net_220:7 0.152 +1 ropt_net_220:2 ropt_mt_inst_840:A 0.152 +2 ropt_net_220:3 ropt_net_220:2 0.0003370536 +3 ropt_net_220:4 ropt_net_220:3 0.0045 +4 ropt_net_220:6 ropt_net_220:5 0.0045 +5 ropt_net_220:5 ropt_net_220:4 0.005080358 +6 ropt_net_220:7 ropt_net_220:6 0.003765625 + +*END + +*D_NET ropt_net_222 0.001133782 //LENGTH 9.525 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_826:X O *L 0 *C 47.535 11.560 +*I ropt_mt_inst_842:A I *L 0.001767 *C 43.700 6.800 +*N ropt_net_222:2 *C 43.738 6.800 +*N ropt_net_222:3 *C 44.575 6.800 +*N ropt_net_222:4 *C 44.620 6.845 +*N ropt_net_222:5 *C 44.620 11.515 +*N ropt_net_222:6 *C 44.665 11.560 +*N ropt_net_222:7 *C 47.498 11.560 + +*CAP +0 ropt_mt_inst_826:X 1e-06 +1 ropt_mt_inst_842:A 1e-06 +2 ropt_net_222:2 7.299025e-05 +3 ropt_net_222:3 7.299025e-05 +4 ropt_net_222:4 0.000275937 +5 ropt_net_222:5 0.000275937 +6 ropt_net_222:6 0.0002169638 +7 ropt_net_222:7 0.0002169638 + +*RES +0 ropt_mt_inst_826:X ropt_net_222:7 0.152 +1 ropt_net_222:7 ropt_net_222:6 0.002529018 +2 ropt_net_222:6 ropt_net_222:5 0.0045 +3 ropt_net_222:5 ropt_net_222:4 0.004169643 +4 ropt_net_222:3 ropt_net_222:2 0.0007477679 +5 ropt_net_222:4 ropt_net_222:3 0.0045 +6 ropt_net_222:2 ropt_mt_inst_842:A 0.152 + +*END + +*D_NET ropt_net_216 0.001868796 //LENGTH 12.050 LUMPCC 0.0008510232 DR + +*CONN +*I FTB_24__23:X O *L 0 *C 47.840 121.380 +*I ropt_mt_inst_837:A I *L 0.001766 *C 56.580 123.760 +*N ropt_net_216:2 *C 56.543 123.760 +*N ropt_net_216:3 *C 54.325 123.760 +*N ropt_net_216:4 *C 54.280 123.715 +*N ropt_net_216:5 *C 54.280 121.425 +*N ropt_net_216:6 *C 54.235 121.380 +*N ropt_net_216:7 *C 47.878 121.380 + +*CAP +0 FTB_24__23:X 1e-06 +1 ropt_mt_inst_837:A 1e-06 +2 ropt_net_216:2 6.776628e-05 +3 ropt_net_216:3 6.776628e-05 +4 ropt_net_216:4 0.0001097766 +5 ropt_net_216:5 0.0001097766 +6 ropt_net_216:6 0.0003303438 +7 ropt_net_216:7 0.0003303438 +8 ropt_net_216:6 chany_bottom_in[10]:5 0.0001122245 +9 ropt_net_216:7 chany_bottom_in[10]:4 0.0001122245 +10 ropt_net_216:4 chany_bottom_in[16]:14 6.633353e-05 +11 ropt_net_216:5 chany_bottom_in[16]:15 6.633353e-05 +12 ropt_net_216:2 chany_top_in[3]:2 8.147868e-05 +13 ropt_net_216:3 chany_top_in[3]:3 8.147868e-05 +14 ropt_net_216:2 ropt_net_225:5 9.401386e-05 +15 ropt_net_216:3 ropt_net_225:4 9.401386e-05 +16 ropt_net_216:6 chany_top_out[3]:4 7.146107e-05 +17 ropt_net_216:7 chany_top_out[3]:3 7.146107e-05 + +*RES +0 FTB_24__23:X ropt_net_216:7 0.152 +1 ropt_net_216:2 ropt_mt_inst_837:A 0.152 +2 ropt_net_216:3 ropt_net_216:2 0.001979911 +3 ropt_net_216:4 ropt_net_216:3 0.0045 +4 ropt_net_216:6 ropt_net_216:5 0.0045 +5 ropt_net_216:5 ropt_net_216:4 0.002044643 +6 ropt_net_216:7 ropt_net_216:6 0.005676339 + +*END + +*D_NET ccff_tail[0] 0.001624903 //LENGTH 13.370 LUMPCC 0.0002034574 DR + +*CONN +*I ropt_mt_inst_847:X O *L 0 *C 61.375 6.460 +*P ccff_tail[0] O *L 0.7423 *C 54.280 1.290 +*N ccff_tail[0]:2 *C 54.280 1.655 +*N ccff_tail[0]:3 *C 54.325 1.700 +*N ccff_tail[0]:4 *C 59.755 1.700 +*N ccff_tail[0]:5 *C 59.800 1.745 +*N ccff_tail[0]:6 *C 59.800 6.415 +*N ccff_tail[0]:7 *C 59.845 6.460 +*N ccff_tail[0]:8 *C 61.338 6.460 + +*CAP +0 ropt_mt_inst_847:X 1e-06 +1 ccff_tail[0] 3.744233e-05 +2 ccff_tail[0]:2 3.744233e-05 +3 ccff_tail[0]:3 0.000388094 +4 ccff_tail[0]:4 0.000388094 +5 ccff_tail[0]:5 0.0002050964 +6 ccff_tail[0]:6 0.0002050964 +7 ccff_tail[0]:7 7.959011e-05 +8 ccff_tail[0]:8 7.959011e-05 +9 ccff_tail[0]:8 ropt_net_194:9 5.617835e-05 +10 ccff_tail[0]:7 ropt_net_194:8 5.617835e-05 +11 ccff_tail[0]:6 ropt_net_194:5 2.04283e-07 +12 ccff_tail[0]:5 ropt_net_194:4 2.04283e-07 +13 ccff_tail[0]:6 ropt_net_227:4 4.534607e-05 +14 ccff_tail[0]:5 ropt_net_227:5 4.534607e-05 + +*RES +0 ropt_mt_inst_847:X ccff_tail[0]:8 0.152 +1 ccff_tail[0]:8 ccff_tail[0]:7 0.001332589 +2 ccff_tail[0]:7 ccff_tail[0]:6 0.0045 +3 ccff_tail[0]:6 ccff_tail[0]:5 0.004169642 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.004848214 +5 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +6 ccff_tail[0]:3 ccff_tail[0]:2 0.0045 +7 ccff_tail[0]:2 ccff_tail[0] 0.0003258929 + +*END + +*D_NET chany_bottom_out[1] 0.001032432 //LENGTH 9.810 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_857:X O *L 0 *C 38.375 6.120 +*P chany_bottom_out[1] O *L 0.7423 *C 34.500 1.290 +*N chany_bottom_out[1]:2 *C 34.500 1.655 +*N chany_bottom_out[1]:3 *C 34.545 1.700 +*N chany_bottom_out[1]:4 *C 37.675 1.700 +*N chany_bottom_out[1]:5 *C 37.720 1.745 +*N chany_bottom_out[1]:6 *C 37.720 6.075 +*N chany_bottom_out[1]:7 *C 37.765 6.120 +*N chany_bottom_out[1]:8 *C 38.337 6.120 + +*CAP +0 ropt_mt_inst_857:X 1e-06 +1 chany_bottom_out[1] 3.367583e-05 +2 chany_bottom_out[1]:2 3.367583e-05 +3 chany_bottom_out[1]:3 0.0001839925 +4 chany_bottom_out[1]:4 0.0001839925 +5 chany_bottom_out[1]:5 0.0002369129 +6 chany_bottom_out[1]:6 0.0002369129 +7 chany_bottom_out[1]:7 6.113482e-05 +8 chany_bottom_out[1]:8 6.113482e-05 + +*RES +0 ropt_mt_inst_857:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0005111608 +2 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +3 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.003866071 +4 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.002794643 +5 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0045 +6 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +7 chany_bottom_out[1]:2 chany_bottom_out[1] 0.0003258929 + +*END + +*D_NET ropt_net_213 0.001909318 //LENGTH 17.070 LUMPCC 0.0003808089 DR + +*CONN +*I BUFT_RR_87:X O *L 0 *C 106.260 34.340 +*I ropt_mt_inst_834:A I *L 0.001766 *C 106.260 39.440 +*N ropt_net_213:2 *C 106.297 39.440 +*N ropt_net_213:3 *C 111.735 39.440 +*N ropt_net_213:4 *C 111.780 39.395 +*N ropt_net_213:5 *C 111.780 34.385 +*N ropt_net_213:6 *C 111.735 34.340 +*N ropt_net_213:7 *C 106.297 34.340 + +*CAP +0 BUFT_RR_87:X 1e-06 +1 ropt_mt_inst_834:A 1e-06 +2 ropt_net_213:2 0.0002716533 +3 ropt_net_213:3 0.0002716533 +4 ropt_net_213:4 0.0001985531 +5 ropt_net_213:5 0.0001985531 +6 ropt_net_213:6 0.0002930479 +7 ropt_net_213:7 0.0002930479 +8 ropt_net_213:3 chany_bottom_in[11]:6 0.0001080162 +9 ropt_net_213:2 chany_bottom_in[11]:7 0.0001080162 +10 ropt_net_213:7 chanx_right_out[7]:3 7.622629e-06 +11 ropt_net_213:6 chanx_right_out[7]:2 7.622629e-06 +12 ropt_net_213:5 chanx_right_out[7] 7.476562e-05 +13 ropt_net_213:4 chanx_right_out[7]:2 7.476562e-05 + +*RES +0 BUFT_RR_87:X ropt_net_213:7 0.152 +1 ropt_net_213:7 ropt_net_213:6 0.004854911 +2 ropt_net_213:6 ropt_net_213:5 0.0045 +3 ropt_net_213:5 ropt_net_213:4 0.004473215 +4 ropt_net_213:3 ropt_net_213:2 0.004854911 +5 ropt_net_213:4 ropt_net_213:3 0.0045 +6 ropt_net_213:2 ropt_mt_inst_834:A 0.152 + +*END + +*D_NET ropt_net_210 0.001419942 //LENGTH 10.860 LUMPCC 0.0001500415 DR + +*CONN +*I BUFT_P_164:X O *L 0 *C 14.260 124.440 +*I ropt_mt_inst_831:A I *L 0.001766 *C 5.060 123.760 +*N ropt_net_210:2 *C 5.060 123.760 +*N ropt_net_210:3 *C 5.060 123.805 +*N ropt_net_210:4 *C 5.060 124.383 +*N ropt_net_210:5 *C 5.067 124.440 +*N ropt_net_210:6 *C 12.413 124.440 +*N ropt_net_210:7 *C 12.420 124.440 +*N ropt_net_210:8 *C 12.550 124.440 +*N ropt_net_210:9 *C 14.223 124.440 + +*CAP +0 BUFT_P_164:X 1e-06 +1 ropt_mt_inst_831:A 1e-06 +2 ropt_net_210:2 3.609409e-05 +3 ropt_net_210:3 5.10995e-05 +4 ropt_net_210:4 5.10995e-05 +5 ropt_net_210:5 0.0004091003 +6 ropt_net_210:6 0.0004091003 +7 ropt_net_210:7 3.670943e-05 +8 ropt_net_210:8 0.0001373487 +9 ropt_net_210:9 0.0001373487 +10 ropt_net_210:6 chany_top_out[6]:4 7.308096e-05 +11 ropt_net_210:4 chany_top_out[6]:5 1.93977e-06 +12 ropt_net_210:5 chany_top_out[6]:3 7.308096e-05 +13 ropt_net_210:3 chany_top_out[6]:6 1.93977e-06 + +*RES +0 BUFT_P_164:X ropt_net_210:9 0.152 +1 ropt_net_210:9 ropt_net_210:8 0.001493304 +2 ropt_net_210:8 ropt_net_210:7 0.0045 +3 ropt_net_210:7 ropt_net_210:6 0.00341 +4 ropt_net_210:6 ropt_net_210:5 0.001150717 +5 ropt_net_210:4 ropt_net_210:3 0.000515625 +6 ropt_net_210:5 ropt_net_210:4 0.00341 +7 ropt_net_210:2 ropt_mt_inst_831:A 0.152 +8 ropt_net_210:3 ropt_net_210:2 0.0045 + +*END + +*D_NET chany_bottom_in[1] 0.01719035 //LENGTH 151.385 LUMPCC 0.002907078 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 14.720 1.290 +*I BUFT_RR_85:A I *L 0.001776 *C 105.800 58.480 +*N chany_bottom_in[1]:2 *C 105.800 58.480 +*N chany_bottom_in[1]:3 *C 105.800 58.140 +*N chany_bottom_in[1]:4 *C 106.215 58.140 +*N chany_bottom_in[1]:5 *C 106.260 58.095 +*N chany_bottom_in[1]:6 *C 106.260 29.285 +*N chany_bottom_in[1]:7 *C 106.215 29.240 +*N chany_bottom_in[1]:8 *C 99.820 29.240 +*N chany_bottom_in[1]:9 *C 99.820 28.560 +*N chany_bottom_in[1]:10 *C 82.385 28.560 +*N chany_bottom_in[1]:11 *C 82.340 28.515 +*N chany_bottom_in[1]:12 *C 82.340 22.498 +*N chany_bottom_in[1]:13 *C 82.333 22.440 +*N chany_bottom_in[1]:14 *C 64.555 22.440 +*N chany_bottom_in[1]:15 *C 14.728 22.440 +*N chany_bottom_in[1]:16 *C 14.720 22.383 + +*CAP +0 chany_bottom_in[1] 0.0008096664 +1 BUFT_RR_85:A 1e-06 +2 chany_bottom_in[1]:2 6.06595e-05 +3 chany_bottom_in[1]:3 7.120905e-05 +4 chany_bottom_in[1]:4 4.18765e-05 +5 chany_bottom_in[1]:5 0.001441477 +6 chany_bottom_in[1]:6 0.001441477 +7 chany_bottom_in[1]:7 0.0003925593 +8 chany_bottom_in[1]:8 0.0004193126 +9 chany_bottom_in[1]:9 0.0005367344 +10 chany_bottom_in[1]:10 0.0005099811 +11 chany_bottom_in[1]:11 0.0002294058 +12 chany_bottom_in[1]:12 0.0002294058 +13 chany_bottom_in[1]:13 0.001035603 +14 chany_bottom_in[1]:14 0.003644422 +15 chany_bottom_in[1]:15 0.00260882 +16 chany_bottom_in[1]:16 0.0008096664 +17 chany_bottom_in[1]:15 chany_top_in[13]:9 0.0005339 +18 chany_bottom_in[1]:14 chany_top_in[13]:10 0.0005339 +19 chany_bottom_in[1]:5 chany_bottom_in[0]:8 0.0001027614 +20 chany_bottom_in[1]:5 chany_bottom_in[0]:12 2.952394e-06 +21 chany_bottom_in[1]:7 chany_bottom_in[0]:19 3.727191e-06 +22 chany_bottom_in[1]:6 chany_bottom_in[0]:9 0.0001027614 +23 chany_bottom_in[1]:6 chany_bottom_in[0]:13 2.952394e-06 +24 chany_bottom_in[1]:10 chany_bottom_in[0]:20 0.0003337865 +25 chany_bottom_in[1]:9 chany_bottom_in[0]:19 0.0003491681 +26 chany_bottom_in[1]:8 chany_bottom_in[0]:18 1.538153e-05 +27 chany_bottom_in[1]:8 chany_bottom_in[0]:20 3.727191e-06 +28 chany_bottom_in[1] chany_bottom_in[3] 0.0001936462 +29 chany_bottom_in[1]:11 chany_bottom_in[3]:9 9.206664e-05 +30 chany_bottom_in[1]:12 chany_bottom_in[3]:10 9.206664e-05 +31 chany_bottom_in[1]:16 chany_bottom_in[3]:14 0.0001936462 +32 chany_bottom_in[1]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001753172 +33 chany_bottom_in[1]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001753172 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:16 0.01883259 +1 chany_bottom_in[1]:2 BUFT_RR_85:A 0.152 +2 chany_bottom_in[1]:4 chany_bottom_in[1]:3 0.0003705357 +3 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.0045 +4 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.0045 +5 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.02572322 +6 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.01556697 +7 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.0045 +8 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.005372768 +9 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.00341 +10 chany_bottom_in[1]:16 chany_bottom_in[1]:15 0.00341 +11 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.007806308 +12 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.0006071428 +13 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.005709822 +14 chany_bottom_in[1]:3 chany_bottom_in[1]:2 0.0003035715 +15 chany_bottom_in[1]:14 chany_bottom_in[1]:13 0.002785141 + +*END + +*D_NET chany_bottom_in[11] 0.01589693 //LENGTH 133.825 LUMPCC 0.003878755 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 30.820 1.290 +*I ropt_mt_inst_829:A I *L 0.001767 *C 106.260 50.320 +*N chany_bottom_in[11]:2 *C 106.297 50.320 +*N chany_bottom_in[11]:3 *C 108.975 50.320 +*N chany_bottom_in[11]:4 *C 109.020 50.275 +*N chany_bottom_in[11]:5 *C 109.020 39.825 +*N chany_bottom_in[11]:6 *C 108.975 39.780 +*N chany_bottom_in[11]:7 *C 103.500 39.780 +*N chany_bottom_in[11]:8 *C 103.580 40.120 +*N chany_bottom_in[11]:9 *C 103.510 40.075 +*N chany_bottom_in[11]:10 *C 103.500 39.485 +*N chany_bottom_in[11]:11 *C 103.455 39.440 +*N chany_bottom_in[11]:12 *C 101.705 39.440 +*N chany_bottom_in[11]:13 *C 101.660 39.395 +*N chany_bottom_in[11]:14 *C 101.660 29.298 +*N chany_bottom_in[11]:15 *C 101.653 29.240 +*N chany_bottom_in[11]:16 *C 68.080 29.240 +*N chany_bottom_in[11]:17 *C 68.080 28.560 +*N chany_bottom_in[11]:18 *C 30.828 28.560 +*N chany_bottom_in[11]:19 *C 30.820 28.503 + +*CAP +0 chany_bottom_in[11] 0.0007514777 +1 ropt_mt_inst_829:A 1e-06 +2 chany_bottom_in[11]:2 0.0001377845 +3 chany_bottom_in[11]:3 0.0001377845 +4 chany_bottom_in[11]:4 0.0006022167 +5 chany_bottom_in[11]:5 0.0006022167 +6 chany_bottom_in[11]:6 0.0002678048 +7 chany_bottom_in[11]:7 0.0002938102 +8 chany_bottom_in[11]:8 5.564024e-05 +9 chany_bottom_in[11]:9 5.041743e-05 +10 chany_bottom_in[11]:10 5.041743e-05 +11 chany_bottom_in[11]:11 0.0001315715 +12 chany_bottom_in[11]:12 0.0001315715 +13 chany_bottom_in[11]:13 0.0005325219 +14 chany_bottom_in[11]:14 0.0005325219 +15 chany_bottom_in[11]:15 0.001430871 +16 chany_bottom_in[11]:16 0.001484705 +17 chany_bottom_in[11]:17 0.002063097 +18 chany_bottom_in[11]:18 0.002009264 +19 chany_bottom_in[11]:19 0.0007514777 +20 chany_bottom_in[11] chany_top_in[18]:13 0.000308249 +21 chany_bottom_in[11]:19 chany_top_in[18]:14 0.000308249 +22 chany_bottom_in[11] chany_bottom_in[17] 0.0003764981 +23 chany_bottom_in[11]:19 chany_bottom_in[17]:22 0.0003764981 +24 chany_bottom_in[11]:15 chanx_right_in[19] 4.517857e-05 +25 chany_bottom_in[11]:15 chanx_right_in[19]:11 0.0002315611 +26 chany_bottom_in[11]:18 chanx_right_in[19]:10 3.585478e-07 +27 chany_bottom_in[11]:18 chanx_right_in[19]:6 5.654439e-05 +28 chany_bottom_in[11]:17 chanx_right_in[19]:10 5.654439e-05 +29 chany_bottom_in[11]:17 chanx_right_in[19]:11 3.585478e-07 +30 chany_bottom_in[11]:16 chanx_right_in[19]:10 0.0002315611 +31 chany_bottom_in[11]:16 chanx_right_in[19]:11 4.517857e-05 +32 chany_bottom_in[11]:15 bottom_left_grid_pin_1_[0]:16 0.000365798 +33 chany_bottom_in[11]:18 bottom_left_grid_pin_1_[0]:17 0.0002351232 +34 chany_bottom_in[11]:17 bottom_left_grid_pin_1_[0]:16 0.0002351232 +35 chany_bottom_in[11]:16 bottom_left_grid_pin_1_[0]:17 0.000365798 +36 chany_bottom_in[11] ropt_net_223:8 5.5367e-05 +37 chany_bottom_in[11]:19 ropt_net_223:9 5.5367e-05 +38 chany_bottom_in[11]:2 ropt_net_239:11 7.595335e-05 +39 chany_bottom_in[11]:3 ropt_net_239:10 7.595335e-05 +40 chany_bottom_in[11]:4 ropt_net_239:5 5.816504e-06 +41 chany_bottom_in[11]:4 ropt_net_239:9 7.240122e-07 +42 chany_bottom_in[11]:5 ropt_net_239:4 5.816504e-06 +43 chany_bottom_in[11]:5 ropt_net_239:8 7.240122e-07 +44 chany_bottom_in[11]:4 ropt_net_230:4 2.688932e-05 +45 chany_bottom_in[11]:6 ropt_net_230:7 4.730081e-05 +46 chany_bottom_in[11]:5 ropt_net_230:5 2.688932e-05 +47 chany_bottom_in[11]:7 ropt_net_230:6 4.730081e-05 +48 chany_bottom_in[11]:6 ropt_net_213:3 0.0001080162 +49 chany_bottom_in[11]:7 ropt_net_213:2 0.0001080162 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:19 0.02429688 +1 chany_bottom_in[11]:2 ropt_mt_inst_829:A 0.152 +2 chany_bottom_in[11]:3 chany_bottom_in[11]:2 0.002390625 +3 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.0045 +4 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.0045 +5 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.009330357 +6 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.0003035715 +7 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.0045 +8 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.0045 +9 chany_bottom_in[11]:10 chany_bottom_in[11]:9 0.0005267857 +10 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.0015625 +11 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.0045 +12 chany_bottom_in[11]:14 chany_bottom_in[11]:13 0.009015625 +13 chany_bottom_in[11]:15 chany_bottom_in[11]:14 0.00341 +14 chany_bottom_in[11]:19 chany_bottom_in[11]:18 0.00341 +15 chany_bottom_in[11]:18 chany_bottom_in[11]:17 0.005836224 +16 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.004888393 +17 chany_bottom_in[11]:17 chany_bottom_in[11]:16 0.0001065333 +18 chany_bottom_in[11]:16 chany_bottom_in[11]:15 0.005259691 + +*END + +*D_NET chany_bottom_in[16] 0.02347516 //LENGTH 178.795 LUMPCC 0.003503897 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 41.860 1.290 +*I ropt_mt_inst_820:A I *L 0.001767 *C 58.880 126.480 +*I mux_right_track_20\/mux_l1_in_1_:A1 I *L 0.00198 *C 69.000 69.020 +*I mux_top_track_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 66.990 59.160 +*N chany_bottom_in[16]:4 *C 67.028 59.160 +*N chany_bottom_in[16]:5 *C 67.575 59.160 +*N chany_bottom_in[16]:6 *C 67.620 59.205 +*N chany_bottom_in[16]:7 *C 68.963 69.020 +*N chany_bottom_in[16]:8 *C 67.665 69.020 +*N chany_bottom_in[16]:9 *C 67.620 69.020 +*N chany_bottom_in[16]:10 *C 67.620 74.062 +*N chany_bottom_in[16]:11 *C 67.612 74.120 +*N chany_bottom_in[16]:12 *C 58.843 126.480 +*N chany_bottom_in[16]:13 *C 54.785 126.480 +*N chany_bottom_in[16]:14 *C 54.740 126.435 +*N chany_bottom_in[16]:15 *C 54.740 104.098 +*N chany_bottom_in[16]:16 *C 54.738 104.040 +*N chany_bottom_in[16]:17 *C 54.295 104.040 +*N chany_bottom_in[16]:18 *C 54.280 104.032 +*N chany_bottom_in[16]:19 *C 54.280 74.127 +*N chany_bottom_in[16]:20 *C 54.280 74.120 +*N chany_bottom_in[16]:21 *C 40.500 74.120 +*N chany_bottom_in[16]:22 *C 40.480 74.112 +*N chany_bottom_in[16]:23 *C 40.480 53.915 +*N chany_bottom_in[16]:24 *C 40.480 4.088 +*N chany_bottom_in[16]:25 *C 40.500 4.080 +*N chany_bottom_in[16]:26 *C 41.852 4.080 +*N chany_bottom_in[16]:27 *C 41.860 4.022 + +*CAP +0 chany_bottom_in[16] 0.0001626083 +1 ropt_mt_inst_820:A 1e-06 +2 mux_right_track_20\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_2_:A0 1e-06 +4 chany_bottom_in[16]:4 6.054049e-05 +5 chany_bottom_in[16]:5 6.054049e-05 +6 chany_bottom_in[16]:6 0.0005609479 +7 chany_bottom_in[16]:7 0.0001378909 +8 chany_bottom_in[16]:8 0.0001378909 +9 chany_bottom_in[16]:9 0.00089174 +10 chany_bottom_in[16]:10 0.0002959618 +11 chany_bottom_in[16]:11 0.001169974 +12 chany_bottom_in[16]:12 0.0003507143 +13 chany_bottom_in[16]:13 0.0003507143 +14 chany_bottom_in[16]:14 0.001175148 +15 chany_bottom_in[16]:15 0.001175148 +16 chany_bottom_in[16]:16 6.250909e-05 +17 chany_bottom_in[16]:17 6.250909e-05 +18 chany_bottom_in[16]:18 0.000879327 +19 chany_bottom_in[16]:19 0.000879327 +20 chany_bottom_in[16]:20 0.002095271 +21 chany_bottom_in[16]:21 0.0009252968 +22 chany_bottom_in[16]:22 0.001195072 +23 chany_bottom_in[16]:23 0.004071245 +24 chany_bottom_in[16]:24 0.002876173 +25 chany_bottom_in[16]:25 0.0001145528 +26 chany_bottom_in[16]:26 0.0001145528 +27 chany_bottom_in[16]:27 0.0001626083 +28 chany_bottom_in[16]:19 chany_bottom_in[5]:26 0.001280569 +29 chany_bottom_in[16]:17 chany_bottom_in[5]:15 9.973008e-06 +30 chany_bottom_in[16]:18 chany_bottom_in[5]:17 0.001280569 +31 chany_bottom_in[16]:16 chany_bottom_in[5]:16 9.973008e-06 +32 chany_bottom_in[16]:19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0003894838 +33 chany_bottom_in[16]:18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0003894838 +34 chany_bottom_in[16]:15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 5.589842e-06 +35 chany_bottom_in[16]:14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.589842e-06 +36 chany_bottom_in[16]:15 ropt_net_216:5 6.633353e-05 +37 chany_bottom_in[16]:14 ropt_net_216:4 6.633353e-05 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:27 0.002439732 +1 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.002158866 +2 chany_bottom_in[16]:22 chany_bottom_in[16]:21 0.00341 +3 chany_bottom_in[16]:25 chany_bottom_in[16]:24 0.00341 +4 chany_bottom_in[16]:24 chany_bottom_in[16]:23 0.007806308 +5 chany_bottom_in[16]:27 chany_bottom_in[16]:26 0.00341 +6 chany_bottom_in[16]:26 chany_bottom_in[16]:25 0.0002118916 +7 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.004502233 +8 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.00341 +9 chany_bottom_in[16]:20 chany_bottom_in[16]:19 0.00341 +10 chany_bottom_in[16]:20 chany_bottom_in[16]:11 0.002088758 +11 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.004685116 +12 chany_bottom_in[16]:17 chany_bottom_in[16]:16 6.499219e-05 +13 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.00341 +14 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.0199442 +15 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.00341 +16 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.003622768 +17 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.0045 +18 chany_bottom_in[16]:12 ropt_mt_inst_820:A 0.152 +19 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.001158482 +20 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.0045 +21 chany_bottom_in[16]:9 chany_bottom_in[16]:6 0.008763393 +22 chany_bottom_in[16]:7 mux_right_track_20\/mux_l1_in_1_:A1 0.152 +23 chany_bottom_in[16]:5 chany_bottom_in[16]:4 0.0004888393 +24 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.0045 +25 chany_bottom_in[16]:4 mux_top_track_8\/mux_l1_in_2_:A0 0.152 +26 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.003164275 + +*END + +*D_NET chany_top_in[7] 0.00448847 //LENGTH 38.125 LUMPCC 0.000107293 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 68.540 129.270 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.200 105.060 +*N chany_top_in[7]:2 *C 55.200 105.060 +*N chany_top_in[7]:3 *C 55.200 105.400 +*N chany_top_in[7]:4 *C 68.495 105.400 +*N chany_top_in[7]:5 *C 68.540 105.445 + +*CAP +0 chany_top_in[7] 0.001314918 +1 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[7]:2 6.036138e-05 +3 chany_top_in[7]:3 0.0008597416 +4 chany_top_in[7]:4 0.0008302379 +5 chany_top_in[7]:5 0.001314918 +6 chany_top_in[7]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 5.364652e-05 +7 chany_top_in[7]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 5.364652e-05 + +*RES +0 chany_top_in[7] chany_top_in[7]:5 0.02127232 +1 chany_top_in[7]:2 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[7]:4 chany_top_in[7]:3 0.01187054 +3 chany_top_in[7]:5 chany_top_in[7]:4 0.0045 +4 chany_top_in[7]:3 chany_top_in[7]:2 0.0003035715 + +*END + +*D_NET top_left_grid_pin_1_[0] 0.02281292 //LENGTH 204.830 LUMPCC 0.002778784 DR + +*CONN +*P top_left_grid_pin_1_[0] I *L 0.29796 *C 2.300 129.235 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.125 61.540 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 88.225 45.220 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 100.645 69.020 +*N top_left_grid_pin_1_[0]:4 *C 100.608 69.020 +*N top_left_grid_pin_1_[0]:5 *C 97.105 69.020 +*N top_left_grid_pin_1_[0]:6 *C 97.060 68.975 +*N top_left_grid_pin_1_[0]:7 *C 97.060 52.418 +*N top_left_grid_pin_1_[0]:8 *C 97.053 52.360 +*N top_left_grid_pin_1_[0]:9 *C 88.225 45.220 +*N top_left_grid_pin_1_[0]:10 *C 88.320 45.265 +*N top_left_grid_pin_1_[0]:11 *C 88.320 52.303 +*N top_left_grid_pin_1_[0]:12 *C 88.320 52.360 +*N top_left_grid_pin_1_[0]:13 *C 74.528 52.360 +*N top_left_grid_pin_1_[0]:14 *C 74.520 52.418 +*N top_left_grid_pin_1_[0]:15 *C 72.163 61.540 +*N top_left_grid_pin_1_[0]:16 *C 73.140 61.540 +*N top_left_grid_pin_1_[0]:17 *C 73.140 61.880 +*N top_left_grid_pin_1_[0]:18 *C 74.475 61.880 +*N top_left_grid_pin_1_[0]:19 *C 74.520 61.880 +*N top_left_grid_pin_1_[0]:20 *C 74.513 61.880 +*N top_left_grid_pin_1_[0]:21 *C 53.055 61.880 +*N top_left_grid_pin_1_[0]:22 *C 3.228 61.880 +*N top_left_grid_pin_1_[0]:23 *C 3.220 61.938 +*N top_left_grid_pin_1_[0]:24 *C 3.220 111.695 +*N top_left_grid_pin_1_[0]:25 *C 3.220 121.720 +*N top_left_grid_pin_1_[0]:26 *C 2.300 121.720 + +*CAP +0 top_left_grid_pin_1_[0] 0.0003231178 +1 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_1_[0]:4 0.000306159 +5 top_left_grid_pin_1_[0]:5 0.000306159 +6 top_left_grid_pin_1_[0]:6 0.0008414418 +7 top_left_grid_pin_1_[0]:7 0.0008414418 +8 top_left_grid_pin_1_[0]:8 0.0003244184 +9 top_left_grid_pin_1_[0]:9 2.760205e-05 +10 top_left_grid_pin_1_[0]:10 0.0003594219 +11 top_left_grid_pin_1_[0]:11 0.0003594219 +12 top_left_grid_pin_1_[0]:12 0.001099881 +13 top_left_grid_pin_1_[0]:13 0.0007754624 +14 top_left_grid_pin_1_[0]:14 0.0005983873 +15 top_left_grid_pin_1_[0]:15 9.926279e-05 +16 top_left_grid_pin_1_[0]:16 0.000126419 +17 top_left_grid_pin_1_[0]:17 0.0001446957 +18 top_left_grid_pin_1_[0]:18 0.0001175395 +19 top_left_grid_pin_1_[0]:19 0.00063694 +20 top_left_grid_pin_1_[0]:20 0.001192041 +21 top_left_grid_pin_1_[0]:21 0.003659449 +22 top_left_grid_pin_1_[0]:22 0.002467408 +23 top_left_grid_pin_1_[0]:23 0.002086092 +24 top_left_grid_pin_1_[0]:24 0.002501796 +25 top_left_grid_pin_1_[0]:25 0.0004645788 +26 top_left_grid_pin_1_[0]:26 0.0003719927 +27 top_left_grid_pin_1_[0]:19 prog_clk[0]:122 3.540591e-06 +28 top_left_grid_pin_1_[0]:20 prog_clk[0]:119 3.269324e-06 +29 top_left_grid_pin_1_[0]:20 prog_clk[0]:124 3.317557e-05 +30 top_left_grid_pin_1_[0]:20 prog_clk[0]:172 1.316322e-05 +31 top_left_grid_pin_1_[0]:20 prog_clk[0]:246 6.417111e-05 +32 top_left_grid_pin_1_[0]:20 prog_clk[0]:251 9.236293e-06 +33 top_left_grid_pin_1_[0]:20 prog_clk[0]:301 5.565114e-06 +34 top_left_grid_pin_1_[0]:22 prog_clk[0] 0.000222601 +35 top_left_grid_pin_1_[0]:22 prog_clk[0]:306 1.489581e-05 +36 top_left_grid_pin_1_[0]:22 prog_clk[0]:311 4.053939e-05 +37 top_left_grid_pin_1_[0]:22 prog_clk[0]:316 0.0001093618 +38 top_left_grid_pin_1_[0]:22 prog_clk[0]:405 8.909669e-06 +39 top_left_grid_pin_1_[0]:22 prog_clk[0]:406 1.321864e-05 +40 top_left_grid_pin_1_[0]:22 prog_clk[0]:468 7.342699e-05 +41 top_left_grid_pin_1_[0]:22 prog_clk[0]:473 3.906427e-05 +42 top_left_grid_pin_1_[0]:11 prog_clk[0]:107 1.169113e-06 +43 top_left_grid_pin_1_[0]:10 prog_clk[0]:104 1.169113e-06 +44 top_left_grid_pin_1_[0]:14 prog_clk[0]:123 3.540591e-06 +45 top_left_grid_pin_1_[0]:7 prog_clk[0]:84 2.371897e-06 +46 top_left_grid_pin_1_[0]:7 prog_clk[0]:85 1.373955e-07 +47 top_left_grid_pin_1_[0]:6 prog_clk[0]:81 1.373955e-07 +48 top_left_grid_pin_1_[0]:6 prog_clk[0]:85 2.371897e-06 +49 top_left_grid_pin_1_[0]:21 prog_clk[0]:124 3.269324e-06 +50 top_left_grid_pin_1_[0]:21 prog_clk[0]:172 3.317557e-05 +51 top_left_grid_pin_1_[0]:21 prog_clk[0]:246 1.316322e-05 +52 top_left_grid_pin_1_[0]:21 prog_clk[0]:251 6.417111e-05 +53 top_left_grid_pin_1_[0]:21 prog_clk[0]:301 2.41321e-05 +54 top_left_grid_pin_1_[0]:21 prog_clk[0]:306 4.610451e-05 +55 top_left_grid_pin_1_[0]:21 prog_clk[0]:311 0.0001093618 +56 top_left_grid_pin_1_[0]:21 prog_clk[0]:316 7.342699e-05 +57 top_left_grid_pin_1_[0]:21 prog_clk[0]:400 1.321864e-05 +58 top_left_grid_pin_1_[0]:21 prog_clk[0]:406 8.909669e-06 +59 top_left_grid_pin_1_[0]:21 prog_clk[0]:468 3.906427e-05 +60 top_left_grid_pin_1_[0]:21 prog_clk[0]:473 0.000222601 +61 top_left_grid_pin_1_[0]:12 chanx_right_in[15]:11 0.0001640535 +62 top_left_grid_pin_1_[0]:12 chanx_right_in[15]:10 0.0002146142 +63 top_left_grid_pin_1_[0]:13 chanx_right_in[15]:10 0.0001640535 +64 top_left_grid_pin_1_[0]:7 chanx_right_in[15]:12 2.918358e-05 +65 top_left_grid_pin_1_[0]:7 chanx_right_in[15]:13 3.539992e-05 +66 top_left_grid_pin_1_[0]:8 chanx_right_in[15]:11 0.0002146142 +67 top_left_grid_pin_1_[0]:6 chanx_right_in[15]:5 3.539992e-05 +68 top_left_grid_pin_1_[0]:6 chanx_right_in[15]:13 2.918358e-05 +69 top_left_grid_pin_1_[0]:11 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 3.687784e-05 +70 top_left_grid_pin_1_[0]:10 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 3.687784e-05 +71 top_left_grid_pin_1_[0]:20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0002514462 +72 top_left_grid_pin_1_[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0002514462 + +*RES +0 top_left_grid_pin_1_[0] top_left_grid_pin_1_[0]:26 0.006709822 +1 top_left_grid_pin_1_[0]:19 top_left_grid_pin_1_[0]:18 0.0045 +2 top_left_grid_pin_1_[0]:19 top_left_grid_pin_1_[0]:14 0.008448661 +3 top_left_grid_pin_1_[0]:20 top_left_grid_pin_1_[0]:19 0.00341 +4 top_left_grid_pin_1_[0]:23 top_left_grid_pin_1_[0]:22 0.00341 +5 top_left_grid_pin_1_[0]:22 top_left_grid_pin_1_[0]:21 0.007806308 +6 top_left_grid_pin_1_[0]:11 top_left_grid_pin_1_[0]:10 0.006283483 +7 top_left_grid_pin_1_[0]:12 top_left_grid_pin_1_[0]:11 0.00341 +8 top_left_grid_pin_1_[0]:12 top_left_grid_pin_1_[0]:8 0.001368092 +9 top_left_grid_pin_1_[0]:9 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +10 top_left_grid_pin_1_[0]:10 top_left_grid_pin_1_[0]:9 0.0045 +11 top_left_grid_pin_1_[0]:14 top_left_grid_pin_1_[0]:13 0.00341 +12 top_left_grid_pin_1_[0]:13 top_left_grid_pin_1_[0]:12 0.002160825 +13 top_left_grid_pin_1_[0]:7 top_left_grid_pin_1_[0]:6 0.01478348 +14 top_left_grid_pin_1_[0]:8 top_left_grid_pin_1_[0]:7 0.00341 +15 top_left_grid_pin_1_[0]:5 top_left_grid_pin_1_[0]:4 0.003127232 +16 top_left_grid_pin_1_[0]:6 top_left_grid_pin_1_[0]:5 0.0045 +17 top_left_grid_pin_1_[0]:4 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +18 top_left_grid_pin_1_[0]:18 top_left_grid_pin_1_[0]:17 0.001191964 +19 top_left_grid_pin_1_[0]:15 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +20 top_left_grid_pin_1_[0]:16 top_left_grid_pin_1_[0]:15 0.0008727679 +21 top_left_grid_pin_1_[0]:17 top_left_grid_pin_1_[0]:16 0.0003035715 +22 top_left_grid_pin_1_[0]:26 top_left_grid_pin_1_[0]:25 0.0008214285 +23 top_left_grid_pin_1_[0]:25 top_left_grid_pin_1_[0]:24 0.008950893 +24 top_left_grid_pin_1_[0]:24 top_left_grid_pin_1_[0]:23 0.04442634 +25 top_left_grid_pin_1_[0]:21 top_left_grid_pin_1_[0]:20 0.003361675 + +*END + +*D_NET chanx_right_in[10] 0.005010456 //LENGTH 33.583 LUMPCC 0.001858215 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 111.930 36.720 +*I mux_top_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 85.005 41.820 +*I mux_bottom_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 89.530 37.060 +*N chanx_right_in[10]:3 *C 89.530 37.060 +*N chanx_right_in[10]:4 *C 85.043 41.820 +*N chanx_right_in[10]:5 *C 86.435 41.820 +*N chanx_right_in[10]:6 *C 86.480 41.775 +*N chanx_right_in[10]:7 *C 86.480 36.765 +*N chanx_right_in[10]:8 *C 86.525 36.720 +*N chanx_right_in[10]:9 *C 89.655 36.727 +*N chanx_right_in[10]:10 *C 89.700 36.720 +*N chanx_right_in[10]:11 *C 89.708 36.720 + +*CAP +0 chanx_right_in[10] 0.0008443831 +1 mux_top_track_4\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_5\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[10]:3 5.887375e-05 +4 chanx_right_in[10]:4 0.000150897 +5 chanx_right_in[10]:5 0.000150897 +6 chanx_right_in[10]:6 0.0002770172 +7 chanx_right_in[10]:7 0.0002770172 +8 chanx_right_in[10]:8 0.0002421237 +9 chanx_right_in[10]:9 0.0002701352 +10 chanx_right_in[10]:10 3.451306e-05 +11 chanx_right_in[10]:11 0.0008443831 +12 chanx_right_in[10] chanx_right_in[11] 0.0005244312 +13 chanx_right_in[10]:11 chanx_right_in[11]:13 0.0005244312 +14 chanx_right_in[10] chanx_right_out[7]:2 0.0004046765 +15 chanx_right_in[10]:11 chanx_right_out[7]:3 0.0004046765 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:11 0.003481525 +1 chanx_right_in[10]:9 chanx_right_in[10]:8 0.002794643 +2 chanx_right_in[10]:9 chanx_right_in[10]:3 0.0001807066 +3 chanx_right_in[10]:10 chanx_right_in[10]:9 0.0045 +4 chanx_right_in[10]:11 chanx_right_in[10]:10 0.00341 +5 chanx_right_in[10]:8 chanx_right_in[10]:7 0.0045 +6 chanx_right_in[10]:7 chanx_right_in[10]:6 0.004473215 +7 chanx_right_in[10]:5 chanx_right_in[10]:4 0.001243304 +8 chanx_right_in[10]:6 chanx_right_in[10]:5 0.0045 +9 chanx_right_in[10]:4 mux_top_track_4\/mux_l1_in_1_:A1 0.152 +10 chanx_right_in[10]:3 mux_bottom_track_5\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET chanx_right_in[15] 0.006566483 //LENGTH 49.035 LUMPCC 0.001932557 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 111.930 57.120 +*I mux_bottom_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 79.945 50.660 +*I mux_top_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 99.180 64.260 +*N chanx_right_in[15]:3 *C 99.142 64.260 +*N chanx_right_in[15]:4 *C 98.485 64.260 +*N chanx_right_in[15]:5 *C 98.440 64.215 +*N chanx_right_in[15]:6 *C 79.983 50.660 +*N chanx_right_in[15]:7 *C 80.915 50.660 +*N chanx_right_in[15]:8 *C 80.960 50.660 +*N chanx_right_in[15]:9 *C 80.960 51.000 +*N chanx_right_in[15]:10 *C 80.968 51.000 +*N chanx_right_in[15]:11 *C 98.433 51.000 +*N chanx_right_in[15]:12 *C 98.440 51.058 +*N chanx_right_in[15]:13 *C 98.440 57.800 +*N chanx_right_in[15]:14 *C 98.448 57.800 +*N chanx_right_in[15]:15 *C 108.560 57.800 +*N chanx_right_in[15]:16 *C 108.560 57.120 + +*CAP +0 chanx_right_in[15] 0.0002011524 +1 mux_bottom_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[15]:3 8.272569e-05 +4 chanx_right_in[15]:4 8.272569e-05 +5 chanx_right_in[15]:5 0.0003272721 +6 chanx_right_in[15]:6 8.060102e-05 +7 chanx_right_in[15]:7 8.060102e-05 +8 chanx_right_in[15]:8 5.104529e-05 +9 chanx_right_in[15]:9 5.443015e-05 +10 chanx_right_in[15]:10 0.0005170415 +11 chanx_right_in[15]:11 0.0005170415 +12 chanx_right_in[15]:12 0.0003647253 +13 chanx_right_in[15]:13 0.0007281312 +14 chanx_right_in[15]:14 0.0006254136 +15 chanx_right_in[15]:15 0.0006716402 +16 chanx_right_in[15]:16 0.0002473789 +17 chanx_right_in[15]:5 top_left_grid_pin_1_[0]:6 3.539992e-05 +18 chanx_right_in[15]:12 top_left_grid_pin_1_[0]:7 2.918358e-05 +19 chanx_right_in[15]:11 top_left_grid_pin_1_[0]:8 0.0002146142 +20 chanx_right_in[15]:11 top_left_grid_pin_1_[0]:12 0.0001640535 +21 chanx_right_in[15]:10 top_left_grid_pin_1_[0]:12 0.0002146142 +22 chanx_right_in[15]:10 top_left_grid_pin_1_[0]:13 0.0001640535 +23 chanx_right_in[15]:13 top_left_grid_pin_1_[0]:6 2.918358e-05 +24 chanx_right_in[15]:13 top_left_grid_pin_1_[0]:7 3.539992e-05 +25 chanx_right_in[15]:11 chanx_right_in[0] 0.00026322 +26 chanx_right_in[15]:10 chanx_right_in[0]:11 0.00026322 +27 chanx_right_in[15] chanx_right_out[6] 6.752754e-05 +28 chanx_right_in[15]:14 chanx_right_out[6]:2 0.0001922801 +29 chanx_right_in[15]:15 chanx_right_out[6] 0.0001922801 +30 chanx_right_in[15]:16 chanx_right_out[6]:2 6.752754e-05 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:16 0.0005279667 +1 chanx_right_in[15]:3 mux_top_track_0\/mux_l1_in_1_:A0 0.152 +2 chanx_right_in[15]:4 chanx_right_in[15]:3 0.0005870537 +3 chanx_right_in[15]:5 chanx_right_in[15]:4 0.0045 +4 chanx_right_in[15]:12 chanx_right_in[15]:11 0.00341 +5 chanx_right_in[15]:11 chanx_right_in[15]:10 0.002736183 +6 chanx_right_in[15]:9 chanx_right_in[15]:8 0.0001634615 +7 chanx_right_in[15]:10 chanx_right_in[15]:9 0.00341 +8 chanx_right_in[15]:7 chanx_right_in[15]:6 0.0008325892 +9 chanx_right_in[15]:8 chanx_right_in[15]:7 0.0045 +10 chanx_right_in[15]:6 mux_bottom_track_17\/mux_l2_in_1_:A1 0.152 +11 chanx_right_in[15]:13 chanx_right_in[15]:12 0.00602009 +12 chanx_right_in[15]:13 chanx_right_in[15]:5 0.005727679 +13 chanx_right_in[15]:14 chanx_right_in[15]:13 0.00341 +14 chanx_right_in[15]:15 chanx_right_in[15]:14 0.001584292 +15 chanx_right_in[15]:16 chanx_right_in[15]:15 0.0001065333 + +*END + +*D_NET right_top_grid_pin_46_[0] 0.006289294 //LENGTH 51.502 LUMPCC 0.001477322 DR + +*CONN +*P right_top_grid_pin_46_[0] I *L 0.29796 *C 83.410 119.000 +*I mux_right_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 82.975 98.940 +*I mux_right_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 84.815 80.580 +*I mux_right_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 78.105 99.620 +*N right_top_grid_pin_46_[0]:4 *C 78.105 99.620 +*N right_top_grid_pin_46_[0]:5 *C 78.200 99.280 +*N right_top_grid_pin_46_[0]:6 *C 82.800 99.280 +*N right_top_grid_pin_46_[0]:7 *C 84.853 80.580 +*N right_top_grid_pin_46_[0]:8 *C 85.975 80.580 +*N right_top_grid_pin_46_[0]:9 *C 86.020 80.625 +*N right_top_grid_pin_46_[0]:10 *C 86.020 98.895 +*N right_top_grid_pin_46_[0]:11 *C 85.975 98.940 +*N right_top_grid_pin_46_[0]:12 *C 83.013 98.940 +*N right_top_grid_pin_46_[0]:13 *C 82.800 98.940 +*N right_top_grid_pin_46_[0]:14 *C 82.800 98.940 +*N right_top_grid_pin_46_[0]:15 *C 82.340 98.940 +*N right_top_grid_pin_46_[0]:16 *C 82.340 118.943 +*N right_top_grid_pin_46_[0]:17 *C 82.348 119.000 + +*CAP +0 right_top_grid_pin_46_[0] 8.188959e-05 +1 mux_right_track_0\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_16\/mux_l1_in_0_:A0 1e-06 +3 mux_right_track_4\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_46_[0]:4 5.714823e-05 +5 right_top_grid_pin_46_[0]:5 0.0003614017 +6 right_top_grid_pin_46_[0]:6 0.0003534258 +7 right_top_grid_pin_46_[0]:7 9.500718e-05 +8 right_top_grid_pin_46_[0]:8 9.500718e-05 +9 right_top_grid_pin_46_[0]:9 0.0009230586 +10 right_top_grid_pin_46_[0]:10 0.0009230586 +11 right_top_grid_pin_46_[0]:11 0.0001884229 +12 right_top_grid_pin_46_[0]:12 0.0002096933 +13 right_top_grid_pin_46_[0]:13 7.479145e-05 +14 right_top_grid_pin_46_[0]:14 6.753472e-05 +15 right_top_grid_pin_46_[0]:15 0.0006656355 +16 right_top_grid_pin_46_[0]:16 0.0006310075 +17 right_top_grid_pin_46_[0]:17 8.188959e-05 +18 right_top_grid_pin_46_[0]:16 right_top_grid_pin_49_[0]:22 2.179418e-05 +19 right_top_grid_pin_46_[0]:16 right_top_grid_pin_49_[0]:9 0.0002841479 +20 right_top_grid_pin_46_[0]:15 right_top_grid_pin_49_[0]:22 0.0002841479 +21 right_top_grid_pin_46_[0]:15 right_top_grid_pin_49_[0]:23 2.179418e-05 +22 right_top_grid_pin_46_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.361171e-05 +23 right_top_grid_pin_46_[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.915811e-05 +24 right_top_grid_pin_46_[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.915811e-05 +25 right_top_grid_pin_46_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.361171e-05 +26 right_top_grid_pin_46_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0003399492 +27 right_top_grid_pin_46_[0]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003399492 + +*RES +0 right_top_grid_pin_46_[0] right_top_grid_pin_46_[0]:17 0.0001664583 +1 right_top_grid_pin_46_[0]:11 right_top_grid_pin_46_[0]:10 0.0045 +2 right_top_grid_pin_46_[0]:10 right_top_grid_pin_46_[0]:9 0.0163125 +3 right_top_grid_pin_46_[0]:8 right_top_grid_pin_46_[0]:7 0.001002232 +4 right_top_grid_pin_46_[0]:9 right_top_grid_pin_46_[0]:8 0.0045 +5 right_top_grid_pin_46_[0]:7 mux_right_track_16\/mux_l1_in_0_:A0 0.152 +6 right_top_grid_pin_46_[0]:4 mux_right_track_4\/mux_l1_in_2_:A1 0.152 +7 right_top_grid_pin_46_[0]:12 mux_right_track_0\/mux_l1_in_1_:A0 0.152 +8 right_top_grid_pin_46_[0]:12 right_top_grid_pin_46_[0]:11 0.002645089 +9 right_top_grid_pin_46_[0]:13 right_top_grid_pin_46_[0]:12 0.0001154891 +10 right_top_grid_pin_46_[0]:13 right_top_grid_pin_46_[0]:6 0.0003035715 +11 right_top_grid_pin_46_[0]:14 right_top_grid_pin_46_[0]:13 0.0045 +12 right_top_grid_pin_46_[0]:16 right_top_grid_pin_46_[0]:15 0.01785938 +13 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:16 0.00341 +14 right_top_grid_pin_46_[0]:5 right_top_grid_pin_46_[0]:4 0.0003035715 +15 right_top_grid_pin_46_[0]:6 right_top_grid_pin_46_[0]:5 0.004107143 +16 right_top_grid_pin_46_[0]:15 right_top_grid_pin_46_[0]:14 0.0004107143 + +*END + +*D_NET chanx_right_out[6] 0.003837785 //LENGTH 31.240 LUMPCC 0.0009700772 DR + +*CONN +*I mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 105.400 82.620 +*P chanx_right_out[6] O *L 0.7423 *C 111.930 58.480 +*N chanx_right_out[6]:2 *C 105.348 58.480 +*N chanx_right_out[6]:3 *C 105.340 58.538 +*N chanx_right_out[6]:4 *C 105.340 82.575 +*N chanx_right_out[6]:5 *C 105.340 82.620 + +*CAP +0 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[6] 0.0002837516 +2 chanx_right_out[6]:2 0.0002837516 +3 chanx_right_out[6]:3 0.001133445 +4 chanx_right_out[6]:4 0.001133445 +5 chanx_right_out[6]:5 3.231478e-05 +6 chanx_right_out[6] chanx_right_in[15] 6.752754e-05 +7 chanx_right_out[6] chanx_right_in[15]:15 0.0001922801 +8 chanx_right_out[6]:2 chanx_right_in[15]:14 0.0001922801 +9 chanx_right_out[6]:2 chanx_right_in[15]:16 6.752754e-05 +10 chanx_right_out[6]:4 ropt_net_212:5 0.000225231 +11 chanx_right_out[6]:3 ropt_net_212:6 0.000225231 + +*RES +0 mux_right_track_12\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[6]:5 0.152 +1 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +2 chanx_right_out[6]:4 chanx_right_out[6]:3 0.02146206 +3 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +4 chanx_right_out[6]:2 chanx_right_out[6] 0.001031258 + +*END + +*D_NET chany_bottom_out[8] 0.005707898 //LENGTH 49.515 LUMPCC 0.0009485274 DR + +*CONN +*I mux_bottom_track_17\/mux_l3_in_0_:X O *L 0 *C 68.760 49.640 +*P chany_bottom_out[8] O *L 0.7423 *C 69.460 1.290 +*N chany_bottom_out[8]:2 *C 69.460 49.595 +*N chany_bottom_out[8]:3 *C 69.415 49.640 +*N chany_bottom_out[8]:4 *C 68.797 49.640 + +*CAP +0 mux_bottom_track_17\/mux_l3_in_0_:X 1e-06 +1 chany_bottom_out[8] 0.002315469 +2 chany_bottom_out[8]:2 0.002315469 +3 chany_bottom_out[8]:3 6.371637e-05 +4 chany_bottom_out[8]:4 6.371637e-05 +5 chany_bottom_out[8] mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001568506 +6 chany_bottom_out[8]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001568506 +7 chany_bottom_out[8] mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002007828 +8 chany_bottom_out[8]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002007828 +9 chany_bottom_out[8] ropt_net_214:4 4.300487e-06 +10 chany_bottom_out[8] ropt_net_214:6 0.0001123298 +11 chany_bottom_out[8]:2 ropt_net_214:7 0.0001123298 +12 chany_bottom_out[8]:2 ropt_net_214:5 4.300487e-06 + +*RES +0 mux_bottom_track_17\/mux_l3_in_0_:X chany_bottom_out[8]:4 0.152 +1 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.0005513393 +2 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0045 +3 chany_bottom_out[8]:2 chany_bottom_out[8] 0.04312947 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[1] 0.003491712 //LENGTH 24.530 LUMPCC 0.0004575077 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.485 82.960 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 27.240 80.240 +*I mux_top_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 27.240 88.400 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 31.915 86.020 +*N mux_tree_tapbuf_size4_0_sram[1]:4 *C 31.915 86.020 +*N mux_tree_tapbuf_size4_0_sram[1]:5 *C 27.140 88.400 +*N mux_tree_tapbuf_size4_0_sram[1]:6 *C 27.140 88.355 +*N mux_tree_tapbuf_size4_0_sram[1]:7 *C 27.140 80.240 +*N mux_tree_tapbuf_size4_0_sram[1]:8 *C 27.140 80.285 +*N mux_tree_tapbuf_size4_0_sram[1]:9 *C 27.140 86.360 +*N mux_tree_tapbuf_size4_0_sram[1]:10 *C 28.060 86.360 +*N mux_tree_tapbuf_size4_0_sram[1]:11 *C 28.105 86.360 +*N mux_tree_tapbuf_size4_0_sram[1]:12 *C 31.740 86.360 +*N mux_tree_tapbuf_size4_0_sram[1]:13 *C 38.135 86.360 +*N mux_tree_tapbuf_size4_0_sram[1]:14 *C 38.180 86.315 +*N mux_tree_tapbuf_size4_0_sram[1]:15 *C 38.180 83.005 +*N mux_tree_tapbuf_size4_0_sram[1]:16 *C 38.180 82.960 +*N mux_tree_tapbuf_size4_0_sram[1]:17 *C 38.485 82.960 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_24\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size4_0_sram[1]:4 5.603673e-05 +5 mux_tree_tapbuf_size4_0_sram[1]:5 3.252757e-05 +6 mux_tree_tapbuf_size4_0_sram[1]:6 7.944024e-05 +7 mux_tree_tapbuf_size4_0_sram[1]:7 3.528432e-05 +8 mux_tree_tapbuf_size4_0_sram[1]:8 0.0002313791 +9 mux_tree_tapbuf_size4_0_sram[1]:9 0.000364439 +10 mux_tree_tapbuf_size4_0_sram[1]:10 8.326357e-05 +11 mux_tree_tapbuf_size4_0_sram[1]:11 0.0002480064 +12 mux_tree_tapbuf_size4_0_sram[1]:12 0.0007719789 +13 mux_tree_tapbuf_size4_0_sram[1]:13 0.0004975008 +14 mux_tree_tapbuf_size4_0_sram[1]:14 0.0002642194 +15 mux_tree_tapbuf_size4_0_sram[1]:15 0.0002642194 +16 mux_tree_tapbuf_size4_0_sram[1]:16 5.353915e-05 +17 mux_tree_tapbuf_size4_0_sram[1]:17 4.836959e-05 +18 mux_tree_tapbuf_size4_0_sram[1]:6 chany_bottom_in[18]:9 5.896682e-05 +19 mux_tree_tapbuf_size4_0_sram[1]:8 chany_bottom_in[18]:12 0.000169787 +20 mux_tree_tapbuf_size4_0_sram[1]:9 chany_bottom_in[18]:9 0.000169787 +21 mux_tree_tapbuf_size4_0_sram[1]:9 chany_bottom_in[18]:12 5.896682e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_0_sram[1]:17 0.152 +1 mux_tree_tapbuf_size4_0_sram[1]:5 mux_top_track_24\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size4_0_sram[1]:6 mux_tree_tapbuf_size4_0_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size4_0_sram[1]:7 mux_top_track_24\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size4_0_sram[1]:8 mux_tree_tapbuf_size4_0_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:12 0.005709821 +6 mux_tree_tapbuf_size4_0_sram[1]:14 mux_tree_tapbuf_size4_0_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size4_0_sram[1]:16 mux_tree_tapbuf_size4_0_sram[1]:15 0.0045 +8 mux_tree_tapbuf_size4_0_sram[1]:15 mux_tree_tapbuf_size4_0_sram[1]:14 0.002955357 +9 mux_tree_tapbuf_size4_0_sram[1]:17 mux_tree_tapbuf_size4_0_sram[1]:16 0.0001657609 +10 mux_tree_tapbuf_size4_0_sram[1]:4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size4_0_sram[1]:11 mux_tree_tapbuf_size4_0_sram[1]:10 0.0045 +12 mux_tree_tapbuf_size4_0_sram[1]:10 mux_tree_tapbuf_size4_0_sram[1]:9 0.0008214285 +13 mux_tree_tapbuf_size4_0_sram[1]:12 mux_tree_tapbuf_size4_0_sram[1]:11 0.003245536 +14 mux_tree_tapbuf_size4_0_sram[1]:12 mux_tree_tapbuf_size4_0_sram[1]:4 0.0003035715 +15 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:8 0.005424107 +16 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:6 0.00178125 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_1_ccff_tail[0] 0.0006493896 //LENGTH 4.810 LUMPCC 7.337919e-05 DR + +*CONN +*I mem_top_track_32\/FTB_14__44:X O *L 0 *C 68.310 85.340 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 66.875 82.620 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 *C 66.875 82.620 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 *C 68.035 82.620 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 *C 68.080 82.665 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 *C 68.080 85.295 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 *C 68.080 85.340 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 *C 68.310 85.340 + +*CAP +0 mem_top_track_32\/FTB_14__44:X 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.0001288905 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 9.346403e-05 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.0001266846 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0001266846 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 4.887219e-05 +7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 4.941436e-05 +8 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 prog_clk[0]:231 3.072024e-05 +9 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 prog_clk[0]:234 5.969356e-06 +10 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 prog_clk[0]:234 3.072024e-05 +11 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 prog_clk[0]:237 5.969356e-06 + +*RES +0 mem_top_track_32\/FTB_14__44:X mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 0.000125 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.001035714 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[2] 0.002098751 //LENGTH 16.245 LUMPCC 0.0006015315 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 64.245 33.660 +*I mux_bottom_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 60.360 29.240 +*I mem_bottom_track_3\/FTB_10__40:A I *L 0.001746 *C 63.940 23.120 +*N mux_tree_tapbuf_size5_2_sram[2]:3 *C 63.940 23.120 +*N mux_tree_tapbuf_size5_2_sram[2]:4 *C 63.940 23.165 +*N mux_tree_tapbuf_size5_2_sram[2]:5 *C 63.940 29.240 +*N mux_tree_tapbuf_size5_2_sram[2]:6 *C 60.398 29.240 +*N mux_tree_tapbuf_size5_2_sram[2]:7 *C 63.435 29.240 +*N mux_tree_tapbuf_size5_2_sram[2]:8 *C 63.480 29.240 +*N mux_tree_tapbuf_size5_2_sram[2]:9 *C 63.480 33.615 +*N mux_tree_tapbuf_size5_2_sram[2]:10 *C 63.525 33.660 +*N mux_tree_tapbuf_size5_2_sram[2]:11 *C 64.207 33.660 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_3\/FTB_10__40:A 1e-06 +3 mux_tree_tapbuf_size5_2_sram[2]:3 3.52974e-05 +4 mux_tree_tapbuf_size5_2_sram[2]:4 0.0002445884 +5 mux_tree_tapbuf_size5_2_sram[2]:5 0.0002600365 +6 mux_tree_tapbuf_size5_2_sram[2]:6 0.0001690797 +7 mux_tree_tapbuf_size5_2_sram[2]:7 0.0001690797 +8 mux_tree_tapbuf_size5_2_sram[2]:8 0.0002355706 +9 mux_tree_tapbuf_size5_2_sram[2]:9 0.0002201225 +10 mux_tree_tapbuf_size5_2_sram[2]:10 8.022226e-05 +11 mux_tree_tapbuf_size5_2_sram[2]:11 8.022226e-05 +12 mux_tree_tapbuf_size5_2_sram[2]:9 mux_tree_tapbuf_size5_2_sram[0]:14 4.274323e-05 +13 mux_tree_tapbuf_size5_2_sram[2]:4 mux_tree_tapbuf_size5_2_sram[0]:15 0.0001687529 +14 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[0]:15 4.274323e-05 +15 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[0]:14 0.0001687529 +16 mux_tree_tapbuf_size5_2_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.3242e-05 +17 mux_tree_tapbuf_size5_2_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.465023e-05 +18 mux_tree_tapbuf_size5_2_sram[2]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.137736e-05 +19 mux_tree_tapbuf_size5_2_sram[2]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.465023e-05 +20 mux_tree_tapbuf_size5_2_sram[2]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.3242e-05 +21 mux_tree_tapbuf_size5_2_sram[2]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.137736e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_2_sram[2]:11 0.152 +1 mux_tree_tapbuf_size5_2_sram[2]:10 mux_tree_tapbuf_size5_2_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size5_2_sram[2]:9 mux_tree_tapbuf_size5_2_sram[2]:8 0.00390625 +3 mux_tree_tapbuf_size5_2_sram[2]:11 mux_tree_tapbuf_size5_2_sram[2]:10 0.000609375 +4 mux_tree_tapbuf_size5_2_sram[2]:3 mem_bottom_track_3\/FTB_10__40:A 0.152 +5 mux_tree_tapbuf_size5_2_sram[2]:4 mux_tree_tapbuf_size5_2_sram[2]:3 0.0045 +6 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[2]:6 0.002712054 +7 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[2]:7 0.0045 +8 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[2]:5 0.0004107143 +9 mux_tree_tapbuf_size5_2_sram[2]:6 mux_bottom_track_3\/mux_l3_in_0_:S 0.152 +10 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[2]:4 0.005424107 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.001457494 //LENGTH 12.425 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 84.480 58.820 +*I mux_top_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 80.600 61.200 +*I mem_top_track_4\/FTB_2__32:A I *L 0.001746 *C 80.500 66.640 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 80.500 66.640 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 80.500 66.595 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 80.500 61.200 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 80.500 61.200 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 80.500 58.865 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 80.545 58.820 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 84.443 58.820 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_4\/FTB_2__32:A 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 3.287912e-05 +4 mux_tree_tapbuf_size6_1_sram[2]:4 0.0002887945 +5 mux_tree_tapbuf_size6_1_sram[2]:5 3.263883e-05 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0004555711 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0001345305 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0002550399 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.0002550399 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:9 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.00347991 +2 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.002084821 +4 mux_tree_tapbuf_size6_1_sram[2]:5 mux_top_track_4\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:4 0.004816964 +7 mux_tree_tapbuf_size6_1_sram[2]:3 mem_top_track_4\/FTB_2__32:A 0.152 +8 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_5_sram[0] 0.00427128 //LENGTH 32.950 LUMPCC 0.0001481583 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.145 26.180 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 73.500 28.855 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.155 31.620 +*I mux_bottom_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 88.420 36.040 +*I mux_bottom_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 84.740 34.755 +*N mux_tree_tapbuf_size6_5_sram[0]:5 *C 84.740 34.755 +*N mux_tree_tapbuf_size6_5_sram[0]:6 *C 88.383 36.040 +*N mux_tree_tapbuf_size6_5_sram[0]:7 *C 84.225 36.040 +*N mux_tree_tapbuf_size6_5_sram[0]:8 *C 84.180 35.995 +*N mux_tree_tapbuf_size6_5_sram[0]:9 *C 84.180 34.725 +*N mux_tree_tapbuf_size6_5_sram[0]:10 *C 84.180 34.680 +*N mux_tree_tapbuf_size6_5_sram[0]:11 *C 74.565 34.680 +*N mux_tree_tapbuf_size6_5_sram[0]:12 *C 74.520 34.635 +*N mux_tree_tapbuf_size6_5_sram[0]:13 *C 75.118 31.620 +*N mux_tree_tapbuf_size6_5_sram[0]:14 *C 74.565 31.620 +*N mux_tree_tapbuf_size6_5_sram[0]:15 *C 74.520 31.620 +*N mux_tree_tapbuf_size6_5_sram[0]:16 *C 74.980 31.620 +*N mux_tree_tapbuf_size6_5_sram[0]:17 *C 74.980 28.605 +*N mux_tree_tapbuf_size6_5_sram[0]:18 *C 74.935 28.560 +*N mux_tree_tapbuf_size6_5_sram[0]:19 *C 73.500 28.855 +*N mux_tree_tapbuf_size6_5_sram[0]:20 *C 73.463 28.560 +*N mux_tree_tapbuf_size6_5_sram[0]:21 *C 71.805 28.560 +*N mux_tree_tapbuf_size6_5_sram[0]:22 *C 71.760 28.515 +*N mux_tree_tapbuf_size6_5_sram[0]:23 *C 71.760 26.225 +*N mux_tree_tapbuf_size6_5_sram[0]:24 *C 71.715 26.180 +*N mux_tree_tapbuf_size6_5_sram[0]:25 *C 71.183 26.180 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_5\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_5\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_5_sram[0]:5 9.857444e-05 +6 mux_tree_tapbuf_size6_5_sram[0]:6 0.0003060065 +7 mux_tree_tapbuf_size6_5_sram[0]:7 0.0003060065 +8 mux_tree_tapbuf_size6_5_sram[0]:8 8.859859e-05 +9 mux_tree_tapbuf_size6_5_sram[0]:9 8.859859e-05 +10 mux_tree_tapbuf_size6_5_sram[0]:10 0.0006681376 +11 mux_tree_tapbuf_size6_5_sram[0]:11 0.0005893289 +12 mux_tree_tapbuf_size6_5_sram[0]:12 0.0001744495 +13 mux_tree_tapbuf_size6_5_sram[0]:13 6.680522e-05 +14 mux_tree_tapbuf_size6_5_sram[0]:14 6.680522e-05 +15 mux_tree_tapbuf_size6_5_sram[0]:15 0.0002094854 +16 mux_tree_tapbuf_size6_5_sram[0]:16 0.0002321843 +17 mux_tree_tapbuf_size6_5_sram[0]:17 0.0001971485 +18 mux_tree_tapbuf_size6_5_sram[0]:18 0.0001265823 +19 mux_tree_tapbuf_size6_5_sram[0]:19 5.922873e-05 +20 mux_tree_tapbuf_size6_5_sram[0]:20 0.0003020861 +21 mux_tree_tapbuf_size6_5_sram[0]:21 0.0001452594 +22 mux_tree_tapbuf_size6_5_sram[0]:22 0.000143866 +23 mux_tree_tapbuf_size6_5_sram[0]:23 0.000143866 +24 mux_tree_tapbuf_size6_5_sram[0]:24 5.255242e-05 +25 mux_tree_tapbuf_size6_5_sram[0]:25 5.255242e-05 +26 mux_tree_tapbuf_size6_5_sram[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.856138e-05 +27 mux_tree_tapbuf_size6_5_sram[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.551774e-05 +28 mux_tree_tapbuf_size6_5_sram[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.551774e-05 +29 mux_tree_tapbuf_size6_5_sram[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.856138e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_5_sram[0]:25 0.152 +1 mux_tree_tapbuf_size6_5_sram[0]:11 mux_tree_tapbuf_size6_5_sram[0]:10 0.008584823 +2 mux_tree_tapbuf_size6_5_sram[0]:12 mux_tree_tapbuf_size6_5_sram[0]:11 0.0045 +3 mux_tree_tapbuf_size6_5_sram[0]:21 mux_tree_tapbuf_size6_5_sram[0]:20 0.001479911 +4 mux_tree_tapbuf_size6_5_sram[0]:22 mux_tree_tapbuf_size6_5_sram[0]:21 0.0045 +5 mux_tree_tapbuf_size6_5_sram[0]:24 mux_tree_tapbuf_size6_5_sram[0]:23 0.0045 +6 mux_tree_tapbuf_size6_5_sram[0]:23 mux_tree_tapbuf_size6_5_sram[0]:22 0.002044643 +7 mux_tree_tapbuf_size6_5_sram[0]:25 mux_tree_tapbuf_size6_5_sram[0]:24 0.0004754465 +8 mux_tree_tapbuf_size6_5_sram[0]:14 mux_tree_tapbuf_size6_5_sram[0]:13 0.0004933036 +9 mux_tree_tapbuf_size6_5_sram[0]:15 mux_tree_tapbuf_size6_5_sram[0]:14 0.0045 +10 mux_tree_tapbuf_size6_5_sram[0]:15 mux_tree_tapbuf_size6_5_sram[0]:12 0.002691964 +11 mux_tree_tapbuf_size6_5_sram[0]:13 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size6_5_sram[0]:5 mux_bottom_track_5\/mux_l1_in_2_:S 0.152 +13 mux_tree_tapbuf_size6_5_sram[0]:18 mux_tree_tapbuf_size6_5_sram[0]:17 0.0045 +14 mux_tree_tapbuf_size6_5_sram[0]:17 mux_tree_tapbuf_size6_5_sram[0]:16 0.002691964 +15 mux_tree_tapbuf_size6_5_sram[0]:10 mux_tree_tapbuf_size6_5_sram[0]:9 0.0045 +16 mux_tree_tapbuf_size6_5_sram[0]:10 mux_tree_tapbuf_size6_5_sram[0]:5 0.0005 +17 mux_tree_tapbuf_size6_5_sram[0]:9 mux_tree_tapbuf_size6_5_sram[0]:8 0.001133929 +18 mux_tree_tapbuf_size6_5_sram[0]:7 mux_tree_tapbuf_size6_5_sram[0]:6 0.003712054 +19 mux_tree_tapbuf_size6_5_sram[0]:8 mux_tree_tapbuf_size6_5_sram[0]:7 0.0045 +20 mux_tree_tapbuf_size6_5_sram[0]:6 mux_bottom_track_5\/mux_l1_in_1_:S 0.152 +21 mux_tree_tapbuf_size6_5_sram[0]:19 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +22 mux_tree_tapbuf_size6_5_sram[0]:20 mux_tree_tapbuf_size6_5_sram[0]:19 0.0001271552 +23 mux_tree_tapbuf_size6_5_sram[0]:20 mux_tree_tapbuf_size6_5_sram[0]:18 0.001314732 +24 mux_tree_tapbuf_size6_5_sram[0]:16 mux_tree_tapbuf_size6_5_sram[0]:15 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_0_ccff_tail[0] 0.0007007763 //LENGTH 5.020 LUMPCC 0.0001728729 DR + +*CONN +*I mem_right_track_2\/FTB_20__50:X O *L 0 *C 69.685 109.820 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.795 107.780 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 *C 67.795 107.780 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 *C 67.620 107.780 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 *C 67.620 107.825 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 *C 67.620 109.775 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 *C 67.665 109.820 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 *C 69.648 109.820 + +*CAP +0 mem_right_track_2\/FTB_20__50:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 4.979106e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 5.430044e-05 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0001237925 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0001237925 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 8.711344e-05 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 8.711344e-05 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 optlc_net_186:7 8.643647e-05 +9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 optlc_net_186:8 8.643647e-05 + +*RES +0 mem_right_track_2\/FTB_20__50:X mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001278318 //LENGTH 9.750 LUMPCC 0.0003753234 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 82.515 53.720 +*I mux_top_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 81.325 61.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 81.362 61.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 82.295 61.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 82.340 61.495 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 82.340 53.765 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 82.340 53.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 82.515 53.720 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.193338e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.193338e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003221116 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003221116 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.698376e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.592124e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:112 6.570601e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:113 6.570601e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.860054e-06 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.860054e-06 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001140956 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001140956 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009118062 //LENGTH 7.565 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_0_:X O *L 0 *C 97.805 90.440 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.430 88.270 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 102.430 88.270 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 99.865 88.400 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 99.820 88.445 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 99.820 90.395 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 99.775 90.440 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 97.843 90.440 + +*CAP +0 mux_right_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001938253 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001648397 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000132862 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000132862 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001427086 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001427086 + +*RES +0 mux_right_track_0\/mux_l3_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002290179 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001741071 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005938592 //LENGTH 4.400 LUMPCC 0.0001481583 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_2_:X O *L 0 *C 83.895 34.000 +*I mux_bottom_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 80.405 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 80.443 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 80.960 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.960 34.000 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 83.858 34.000 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.926213e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.349476e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001825884 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001583557 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_5_sram[0]:10 4.551774e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size6_5_sram[0]:11 2.856138e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_5_sram[0]:10 2.856138e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_5_sram[0]:11 4.551774e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002587054 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A1 0.152 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004620536 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00208634 //LENGTH 12.905 LUMPCC 0.001343939 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_0_:X O *L 0 *C 45.255 69.360 +*I mux_top_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 33.120 69.020 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 33.142 69.047 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 33.155 69.360 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 45.218 69.360 + +*CAP +0 mux_top_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.829041e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003702004 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003419099 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0004223553 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0004223553 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:16 0.000246229 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:13 9.686262e-07 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:14 2.416607e-06 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:4 1.038255e-06 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:14 9.686262e-07 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:15 0.0002476074 + +*RES +0 mux_top_track_16\/mux_l1_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.01077009 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A1 0.152 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002111487 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002126002 //LENGTH 13.455 LUMPCC 0.0009007733 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 37.435 77.180 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.965 79.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 28.003 79.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 31.235 79.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 31.280 79.855 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 31.280 77.578 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 31.288 77.520 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 34.953 77.520 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 34.960 77.520 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 34.960 77.180 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 35.005 77.180 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 37.398 77.180 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001342893 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001342893 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001405086 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001405086 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001689245 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001689245 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.733214e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.330822e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001125718 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001125718 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[17]:9 0.000217338 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[17]:8 0.000217338 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[9]:15 1.12188e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[9]:19 7.150247e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[9]:20 6.00638e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[9]:14 7.150247e-05 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[9]:16 1.12188e-05 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[9]:19 6.00638e-05 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[9]:12 1.493669e-06 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[9]:17 2.338167e-06 +22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[9]:13 1.493669e-06 +23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[9]:18 2.338167e-06 +24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chanx_right_in[13]:4 8.643181e-05 +25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chanx_right_in[13]:3 8.643181e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002886161 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002033482 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005741833 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001634615 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002136161 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001324873 //LENGTH 10.785 LUMPCC 0.0002532734 DR + +*CONN +*I mux_right_track_14\/mux_l2_in_0_:X O *L 0 *C 79.865 90.780 +*I mux_right_track_14\/mux_l3_in_0_:A1 I *L 0.00198 *C 84.280 85.340 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 84.243 85.340 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.925 85.340 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 81.880 85.385 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.880 90.735 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.835 90.780 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 79.903 90.780 + +*CAP +0 mux_right_track_14\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_14\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001293917 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001293917 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00024208 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00024208 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000163328 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000163328 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[2]:26 6.430547e-05 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[2]:22 6.430547e-05 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.628689e-05 +11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.628689e-05 +12 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.604432e-05 +13 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.604432e-05 + +*RES +0 mux_right_track_14\/mux_l2_in_0_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_14\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002069197 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001725446 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001066907 //LENGTH 7.540 LUMPCC 0.0002917466 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_2_:X O *L 0 *C 76.535 99.280 +*I mux_right_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 72.585 96.220 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 72.585 96.220 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.680 96.265 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.680 99.235 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.725 99.280 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 76.498 99.280 + +*CAP +0 mux_right_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.840216e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002073187 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002073187 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001650604 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001650604 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:11 0.0001458733 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:10 0.0001458733 + +*RES +0 mux_right_track_4\/mux_l1_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002651786 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.003368303 + +*END + +*D_NET mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00205611 //LENGTH 16.715 LUMPCC 0.0003904425 DR + +*CONN +*I mux_right_track_18\/mux_l1_in_0_:X O *L 0 *C 77.105 85.000 +*I mux_right_track_18\/mux_l2_in_0_:A1 I *L 0.00198 *C 80.500 72.420 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 80.463 72.420 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 77.325 72.420 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 77.280 72.465 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 77.280 84.955 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 77.280 85.000 +*N mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 77.105 85.000 + +*CAP +0 mux_right_track_18\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_18\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001379971 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001379971 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0006341779 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0006341779 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.682161e-05 +7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.249598e-05 +8 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[0]:7 3.210713e-05 +9 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[0]:11 3.446703e-05 +10 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_1_sram[0]:8 3.210713e-05 +11 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_1_sram[0]:14 3.446703e-05 +12 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_2_sram[0]:13 0.0001286471 +13 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_2_sram[0]:14 0.0001286471 + +*RES +0 mux_right_track_18\/mux_l1_in_0_:X mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 +2 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01115179 +4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002801339 +5 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_18\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET chany_top_out[13] 0.000566051 //LENGTH 4.435 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 25.300 127.160 +*P chany_top_out[13] O *L 0.7423 *C 23.920 129.350 +*N chany_top_out[13]:2 *C 23.920 128.528 +*N chany_top_out[13]:3 *C 23.940 128.520 +*N chany_top_out[13]:4 *C 25.293 128.520 +*N chany_top_out[13]:5 *C 25.300 128.463 +*N chany_top_out[13]:6 *C 25.300 127.205 +*N chany_top_out[13]:7 *C 25.300 127.160 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 chany_top_out[13] 7.209985e-05 +2 chany_top_out[13]:2 7.209985e-05 +3 chany_top_out[13]:3 0.0001029931 +4 chany_top_out[13]:4 0.0001029931 +5 chany_top_out[13]:5 9.252844e-05 +6 chany_top_out[13]:6 9.252844e-05 +7 chany_top_out[13]:7 2.980812e-05 + +*RES +0 ropt_mt_inst_814:X chany_top_out[13]:7 0.152 +1 chany_top_out[13]:7 chany_top_out[13]:6 0.0045 +2 chany_top_out[13]:6 chany_top_out[13]:5 0.001122768 +3 chany_top_out[13]:5 chany_top_out[13]:4 0.00341 +4 chany_top_out[13]:4 chany_top_out[13]:3 0.0002118916 +5 chany_top_out[13]:3 chany_top_out[13]:2 0.00341 +6 chany_top_out[13]:2 chany_top_out[13] 0.0001288583 + +*END + +*D_NET ropt_net_236 0.001584506 //LENGTH 12.290 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_827:X O *L 0 *C 55.660 11.560 +*I ropt_mt_inst_856:A I *L 0.001766 *C 52.900 6.800 +*N ropt_net_236:2 *C 52.938 6.800 +*N ropt_net_236:3 *C 53.775 6.800 +*N ropt_net_236:4 *C 53.820 6.755 +*N ropt_net_236:5 *C 53.820 6.165 +*N ropt_net_236:6 *C 53.865 6.120 +*N ropt_net_236:7 *C 56.535 6.120 +*N ropt_net_236:8 *C 56.580 6.165 +*N ropt_net_236:9 *C 56.580 11.515 +*N ropt_net_236:10 *C 56.535 11.560 +*N ropt_net_236:11 *C 55.698 11.560 + +*CAP +0 ropt_mt_inst_827:X 1e-06 +1 ropt_mt_inst_856:A 1e-06 +2 ropt_net_236:2 7.907068e-05 +3 ropt_net_236:3 7.907068e-05 +4 ropt_net_236:4 6.531554e-05 +5 ropt_net_236:5 6.531554e-05 +6 ropt_net_236:6 0.0002412274 +7 ropt_net_236:7 0.0002412274 +8 ropt_net_236:8 0.0003279166 +9 ropt_net_236:9 0.0003279166 +10 ropt_net_236:10 7.772255e-05 +11 ropt_net_236:11 7.772255e-05 + +*RES +0 ropt_mt_inst_827:X ropt_net_236:11 0.152 +1 ropt_net_236:2 ropt_mt_inst_856:A 0.152 +2 ropt_net_236:3 ropt_net_236:2 0.0007477679 +3 ropt_net_236:4 ropt_net_236:3 0.0045 +4 ropt_net_236:6 ropt_net_236:5 0.0045 +5 ropt_net_236:5 ropt_net_236:4 0.0005267857 +6 ropt_net_236:7 ropt_net_236:6 0.002383929 +7 ropt_net_236:8 ropt_net_236:7 0.0045 +8 ropt_net_236:10 ropt_net_236:9 0.0045 +9 ropt_net_236:9 ropt_net_236:8 0.004776785 +10 ropt_net_236:11 ropt_net_236:10 0.0007477679 + +*END + +*D_NET chany_bottom_out[6] 0.0007718157 //LENGTH 5.845 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_844:X O *L 0 *C 71.300 4.760 +*P chany_bottom_out[6] O *L 0.7423 *C 70.380 1.325 +*N chany_bottom_out[6]:2 *C 69.920 1.360 +*N chany_bottom_out[6]:3 *C 69.920 4.715 +*N chany_bottom_out[6]:4 *C 69.965 4.760 +*N chany_bottom_out[6]:5 *C 71.263 4.760 + +*CAP +0 ropt_mt_inst_844:X 1e-06 +1 chany_bottom_out[6] 3.226406e-05 +2 chany_bottom_out[6]:2 0.0002744295 +3 chany_bottom_out[6]:3 0.0002421654 +4 chany_bottom_out[6]:4 0.0001109783 +5 chany_bottom_out[6]:5 0.0001109783 + +*RES +0 ropt_mt_inst_844:X chany_bottom_out[6]:5 0.152 +1 chany_bottom_out[6]:5 chany_bottom_out[6]:4 0.001158482 +2 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.0045 +3 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.002995536 +4 chany_bottom_out[6]:2 chany_bottom_out[6] 0.0004107143 + +*END + +*D_NET ropt_net_205 0.001411654 //LENGTH 10.505 LUMPCC 0 DR + +*CONN +*I BUFT_RR_75:X O *L 0 *C 43.240 17.340 +*I ropt_mt_inst_826:A I *L 0.001766 *C 43.700 12.240 +*N ropt_net_205:2 *C 43.738 12.240 +*N ropt_net_205:3 *C 44.575 12.240 +*N ropt_net_205:4 *C 44.620 12.285 +*N ropt_net_205:5 *C 44.620 16.943 +*N ropt_net_205:6 *C 44.613 17.000 +*N ropt_net_205:7 *C 42.328 17.000 +*N ropt_net_205:8 *C 42.320 17.000 +*N ropt_net_205:9 *C 42.320 17.340 +*N ropt_net_205:10 *C 42.365 17.340 +*N ropt_net_205:11 *C 43.203 17.340 + +*CAP +0 BUFT_RR_75:X 1e-06 +1 ropt_mt_inst_826:A 1e-06 +2 ropt_net_205:2 9.04157e-05 +3 ropt_net_205:3 9.04157e-05 +4 ropt_net_205:4 0.0002801645 +5 ropt_net_205:5 0.0002801645 +6 ropt_net_205:6 0.000180012 +7 ropt_net_205:7 0.000180012 +8 ropt_net_205:8 5.854751e-05 +9 ropt_net_205:9 5.473868e-05 +10 ropt_net_205:10 9.759188e-05 +11 ropt_net_205:11 9.759188e-05 + +*RES +0 BUFT_RR_75:X ropt_net_205:11 0.152 +1 ropt_net_205:11 ropt_net_205:10 0.0007477679 +2 ropt_net_205:10 ropt_net_205:9 0.0045 +3 ropt_net_205:9 ropt_net_205:8 0.0001634616 +4 ropt_net_205:8 ropt_net_205:7 0.00341 +5 ropt_net_205:7 ropt_net_205:6 0.0003579833 +6 ropt_net_205:5 ropt_net_205:4 0.004158482 +7 ropt_net_205:6 ropt_net_205:5 0.00341 +8 ropt_net_205:3 ropt_net_205:2 0.0007477679 +9 ropt_net_205:4 ropt_net_205:3 0.0045 +10 ropt_net_205:2 ropt_mt_inst_826:A 0.152 + +*END + +*D_NET chany_bottom_in[2] 0.02054722 //LENGTH 151.410 LUMPCC 0.005025013 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 71.300 1.290 +*I mux_top_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 83.360 69.020 +*I BUFT_RR_86:A I *L 0.001776 *C 69.000 121.040 +*I mux_right_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 82.055 93.500 +*N chany_bottom_in[2]:4 *C 82.055 93.500 +*N chany_bottom_in[2]:5 *C 69.038 121.040 +*N chany_bottom_in[2]:6 *C 69.875 121.040 +*N chany_bottom_in[2]:7 *C 69.920 120.995 +*N chany_bottom_in[2]:8 *C 69.920 118.378 +*N chany_bottom_in[2]:9 *C 69.928 118.320 +*N chany_bottom_in[2]:10 *C 70.820 118.320 +*N chany_bottom_in[2]:11 *C 70.840 118.312 +*N chany_bottom_in[2]:12 *C 70.840 93.168 +*N chany_bottom_in[2]:13 *C 70.860 93.160 +*N chany_bottom_in[2]:14 *C 77.273 93.160 +*N chany_bottom_in[2]:15 *C 77.280 93.160 +*N chany_bottom_in[2]:16 *C 77.280 93.500 +*N chany_bottom_in[2]:17 *C 77.325 93.500 +*N chany_bottom_in[2]:18 *C 80.500 93.500 +*N chany_bottom_in[2]:19 *C 80.500 93.160 +*N chany_bottom_in[2]:20 *C 82.055 93.160 +*N chany_bottom_in[2]:21 *C 82.755 93.160 +*N chany_bottom_in[2]:22 *C 82.800 93.115 +*N chany_bottom_in[2]:23 *C 83.323 69.020 +*N chany_bottom_in[2]:24 *C 82.800 69.020 +*N chany_bottom_in[2]:25 *C 82.800 68.680 +*N chany_bottom_in[2]:26 *C 82.800 68.680 +*N chany_bottom_in[2]:27 *C 82.800 66.698 +*N chany_bottom_in[2]:28 *C 82.793 66.640 +*N chany_bottom_in[2]:29 *C 80.060 66.640 +*N chany_bottom_in[2]:30 *C 80.040 66.633 +*N chany_bottom_in[2]:31 *C 80.040 53.915 +*N chany_bottom_in[2]:32 *C 80.040 4.088 +*N chany_bottom_in[2]:33 *C 80.020 4.080 +*N chany_bottom_in[2]:34 *C 71.308 4.080 +*N chany_bottom_in[2]:35 *C 71.300 4.022 + +*CAP +0 chany_bottom_in[2] 0.0001773577 +1 mux_top_track_0\/mux_l1_in_2_:A1 1e-06 +2 BUFT_RR_86:A 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A0 1e-06 +4 chany_bottom_in[2]:4 5.922173e-05 +5 chany_bottom_in[2]:5 6.730148e-05 +6 chany_bottom_in[2]:6 6.730148e-05 +7 chany_bottom_in[2]:7 0.0001148489 +8 chany_bottom_in[2]:8 0.0001148489 +9 chany_bottom_in[2]:9 0.000106387 +10 chany_bottom_in[2]:10 0.000106387 +11 chany_bottom_in[2]:11 0.002110719 +12 chany_bottom_in[2]:12 0.002110719 +13 chany_bottom_in[2]:13 0.0004845257 +14 chany_bottom_in[2]:14 0.0004845257 +15 chany_bottom_in[2]:15 5.907963e-05 +16 chany_bottom_in[2]:16 5.268153e-05 +17 chany_bottom_in[2]:17 0.0002462677 +18 chany_bottom_in[2]:18 0.0002698163 +19 chany_bottom_in[2]:19 0.0001334734 +20 chany_bottom_in[2]:20 0.0002024954 +21 chany_bottom_in[2]:21 6.297426e-05 +22 chany_bottom_in[2]:22 0.00108573 +23 chany_bottom_in[2]:23 4.956851e-05 +24 chany_bottom_in[2]:24 7.742091e-05 +25 chany_bottom_in[2]:25 5.997138e-05 +26 chany_bottom_in[2]:26 0.00123555 +27 chany_bottom_in[2]:27 0.0001173464 +28 chany_bottom_in[2]:28 0.0003260169 +29 chany_bottom_in[2]:29 0.0003260169 +30 chany_bottom_in[2]:30 0.0005026213 +31 chany_bottom_in[2]:31 0.002029277 +32 chany_bottom_in[2]:32 0.001526656 +33 chany_bottom_in[2]:33 0.0004873727 +34 chany_bottom_in[2]:34 0.0004873727 +35 chany_bottom_in[2]:35 0.0001773577 +36 chany_bottom_in[2]:14 chany_top_in[2]:26 2.359173e-05 +37 chany_bottom_in[2]:13 chany_top_in[2]:25 2.359173e-05 +38 chany_bottom_in[2]:8 chany_top_in[2]:34 8.06114e-05 +39 chany_bottom_in[2]:7 chany_top_in[2] 8.06114e-05 +40 chany_bottom_in[2]:30 chany_top_in[2]:24 6.412462e-05 +41 chany_bottom_in[2]:32 chany_top_in[2]:23 8.453055e-05 +42 chany_bottom_in[2]:31 chany_top_in[2]:23 6.412462e-05 +43 chany_bottom_in[2]:31 chany_top_in[2]:24 8.453055e-05 +44 chany_bottom_in[2]:12 chany_top_in[5]:16 0.0004638032 +45 chany_bottom_in[2]:11 chany_top_in[5]:17 0.0004638032 +46 chany_bottom_in[2]:30 chany_bottom_in[4]:25 0.0002517595 +47 chany_bottom_in[2]:32 chany_bottom_in[4]:32 0.000144088 +48 chany_bottom_in[2]:32 chany_bottom_in[4]:33 0.0007732883 +49 chany_bottom_in[2]:31 chany_bottom_in[4]:32 0.001025048 +50 chany_bottom_in[2]:31 chany_bottom_in[4]:25 0.000144088 +51 chany_bottom_in[2]:33 chany_bottom_in[7]:13 9.501752e-06 +52 chany_bottom_in[2]:32 chany_bottom_in[7]:12 0.0002723652 +53 chany_bottom_in[2]:34 chany_bottom_in[7]:14 9.501752e-06 +54 chany_bottom_in[2]:31 chany_bottom_in[7]:11 0.0002723652 +55 chany_bottom_in[2]:22 mux_tree_tapbuf_size6_3_sram[0]:16 0.0002805368 +56 chany_bottom_in[2]:26 mux_tree_tapbuf_size6_3_sram[0]:17 0.0002805368 +57 chany_bottom_in[2]:22 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.430547e-05 +58 chany_bottom_in[2]:26 mux_right_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.430547e-05 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:35 0.002439732 +1 chany_bottom_in[2]:17 chany_bottom_in[2]:16 0.0045 +2 chany_bottom_in[2]:16 chany_bottom_in[2]:15 0.0001634615 +3 chany_bottom_in[2]:15 chany_bottom_in[2]:14 0.00341 +4 chany_bottom_in[2]:14 chany_bottom_in[2]:13 0.001004625 +5 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.00341 +6 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.003939383 +7 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.000139825 +8 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.00341 +9 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.002337054 +10 chany_bottom_in[2]:9 chany_bottom_in[2]:8 0.00341 +11 chany_bottom_in[2]:6 chany_bottom_in[2]:5 0.0007477679 +12 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.0045 +13 chany_bottom_in[2]:5 BUFT_RR_86:A 0.152 +14 chany_bottom_in[2]:4 mux_right_track_0\/mux_l1_in_2_:A0 0.152 +15 chany_bottom_in[2]:21 chany_bottom_in[2]:20 0.000625 +16 chany_bottom_in[2]:22 chany_bottom_in[2]:21 0.0045 +17 chany_bottom_in[2]:25 chany_bottom_in[2]:24 0.0003035715 +18 chany_bottom_in[2]:26 chany_bottom_in[2]:25 0.0045 +19 chany_bottom_in[2]:26 chany_bottom_in[2]:22 0.02181697 +20 chany_bottom_in[2]:23 mux_top_track_0\/mux_l1_in_2_:A1 0.152 +21 chany_bottom_in[2]:27 chany_bottom_in[2]:26 0.001770089 +22 chany_bottom_in[2]:28 chany_bottom_in[2]:27 0.00341 +23 chany_bottom_in[2]:29 chany_bottom_in[2]:28 0.0004280916 +24 chany_bottom_in[2]:30 chany_bottom_in[2]:29 0.00341 +25 chany_bottom_in[2]:33 chany_bottom_in[2]:32 0.00341 +26 chany_bottom_in[2]:32 chany_bottom_in[2]:31 0.007806308 +27 chany_bottom_in[2]:35 chany_bottom_in[2]:34 0.00341 +28 chany_bottom_in[2]:34 chany_bottom_in[2]:33 0.001364958 +29 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.002834822 +30 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.0003035715 +31 chany_bottom_in[2]:20 chany_bottom_in[2]:19 0.001388393 +32 chany_bottom_in[2]:20 chany_bottom_in[2]:4 0.0003035715 +33 chany_bottom_in[2]:24 chany_bottom_in[2]:23 0.0004665179 +34 chany_bottom_in[2]:31 chany_bottom_in[2]:30 0.001992408 + +*END + +*D_NET chany_bottom_out[16] 0.002123419 //LENGTH 19.680 LUMPCC 0.0002895793 DR + +*CONN +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 31.685 17.340 +*P chany_bottom_out[16] O *L 0.7423 *C 28.520 1.290 +*N chany_bottom_out[16]:2 *C 28.520 17.295 +*N chany_bottom_out[16]:3 *C 28.565 17.340 +*N chany_bottom_out[16]:4 *C 31.648 17.340 + +*CAP +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[16] 0.0007263586 +2 chany_bottom_out[16]:2 0.0007263586 +3 chany_bottom_out[16]:3 0.0001900611 +4 chany_bottom_out[16]:4 0.0001900611 +5 chany_bottom_out[16] ropt_net_223:5 0.0001447896 +6 chany_bottom_out[16]:2 ropt_net_223:4 0.0001447896 + +*RES +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[16]:4 0.152 +1 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.002752232 +2 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0045 +3 chany_bottom_out[16]:2 chany_bottom_out[16] 0.01429018 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[0] 0.003929776 //LENGTH 30.345 LUMPCC 0.0002572942 DR + +*CONN +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 84.025 74.800 +*I mux_right_track_20\/mux_l1_in_1_:S I *L 0.00357 *C 70.280 68.680 +*I mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 68.255 77.180 +*I mux_right_track_20\/mux_l1_in_0_:S I *L 0.00357 *C 72.780 72.375 +*N mux_tree_tapbuf_size3_2_sram[0]:4 *C 72.780 72.375 +*N mux_tree_tapbuf_size3_2_sram[0]:5 *C 68.293 77.180 +*N mux_tree_tapbuf_size3_2_sram[0]:6 *C 69.875 77.180 +*N mux_tree_tapbuf_size3_2_sram[0]:7 *C 69.920 77.135 +*N mux_tree_tapbuf_size3_2_sram[0]:8 *C 70.265 68.680 +*N mux_tree_tapbuf_size3_2_sram[0]:9 *C 69.943 68.680 +*N mux_tree_tapbuf_size3_2_sram[0]:10 *C 69.920 68.725 +*N mux_tree_tapbuf_size3_2_sram[0]:11 *C 69.920 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:12 *C 69.965 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:13 *C 72.780 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:14 *C 80.960 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:15 *C 80.960 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:16 *C 83.675 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:17 *C 83.720 71.785 +*N mux_tree_tapbuf_size3_2_sram[0]:18 *C 83.720 74.755 +*N mux_tree_tapbuf_size3_2_sram[0]:19 *C 83.720 74.800 +*N mux_tree_tapbuf_size3_2_sram[0]:20 *C 84.025 74.800 + +*CAP +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_20\/mux_l1_in_1_:S 1e-06 +2 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_track_20\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_2_sram[0]:4 5.846389e-05 +5 mux_tree_tapbuf_size3_2_sram[0]:5 0.0001181568 +6 mux_tree_tapbuf_size3_2_sram[0]:6 0.0001181568 +7 mux_tree_tapbuf_size3_2_sram[0]:7 0.0002830848 +8 mux_tree_tapbuf_size3_2_sram[0]:8 5.776479e-05 +9 mux_tree_tapbuf_size3_2_sram[0]:9 5.776479e-05 +10 mux_tree_tapbuf_size3_2_sram[0]:10 0.0002001857 +11 mux_tree_tapbuf_size3_2_sram[0]:11 0.000515376 +12 mux_tree_tapbuf_size3_2_sram[0]:12 0.0001814711 +13 mux_tree_tapbuf_size3_2_sram[0]:13 0.0006652577 +14 mux_tree_tapbuf_size3_2_sram[0]:14 0.0004788335 +15 mux_tree_tapbuf_size3_2_sram[0]:15 0.000247026 +16 mux_tree_tapbuf_size3_2_sram[0]:16 0.0002221251 +17 mux_tree_tapbuf_size3_2_sram[0]:17 0.0001796381 +18 mux_tree_tapbuf_size3_2_sram[0]:18 0.0001796381 +19 mux_tree_tapbuf_size3_2_sram[0]:19 5.480247e-05 +20 mux_tree_tapbuf_size3_2_sram[0]:20 5.073504e-05 +21 mux_tree_tapbuf_size3_2_sram[0]:13 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001286471 +22 mux_tree_tapbuf_size3_2_sram[0]:14 mux_right_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001286471 + +*RES +0 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_2_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_2_sram[0]:8 mux_right_track_20\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_2_sram[0]:9 mux_tree_tapbuf_size3_2_sram[0]:8 0.0001752718 +3 mux_tree_tapbuf_size3_2_sram[0]:10 mux_tree_tapbuf_size3_2_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size3_2_sram[0]:6 mux_tree_tapbuf_size3_2_sram[0]:5 0.001412946 +5 mux_tree_tapbuf_size3_2_sram[0]:7 mux_tree_tapbuf_size3_2_sram[0]:6 0.0045 +6 mux_tree_tapbuf_size3_2_sram[0]:5 mem_right_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size3_2_sram[0]:12 mux_tree_tapbuf_size3_2_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:10 0.002995536 +9 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:7 0.004513394 +10 mux_tree_tapbuf_size3_2_sram[0]:16 mux_tree_tapbuf_size3_2_sram[0]:15 0.002424107 +11 mux_tree_tapbuf_size3_2_sram[0]:17 mux_tree_tapbuf_size3_2_sram[0]:16 0.0045 +12 mux_tree_tapbuf_size3_2_sram[0]:19 mux_tree_tapbuf_size3_2_sram[0]:18 0.0045 +13 mux_tree_tapbuf_size3_2_sram[0]:18 mux_tree_tapbuf_size3_2_sram[0]:17 0.002651786 +14 mux_tree_tapbuf_size3_2_sram[0]:20 mux_tree_tapbuf_size3_2_sram[0]:19 0.0001657609 +15 mux_tree_tapbuf_size3_2_sram[0]:4 mux_right_track_20\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:12 0.002513393 +17 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:4 0.0001271552 +18 mux_tree_tapbuf_size3_2_sram[0]:14 mux_tree_tapbuf_size3_2_sram[0]:13 0.007303572 +19 mux_tree_tapbuf_size3_2_sram[0]:15 mux_tree_tapbuf_size3_2_sram[0]:14 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size4_4_sram[0] 0.001992633 //LENGTH 17.005 LUMPCC 0.0003697115 DR + +*CONN +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 51.825 88.060 +*I mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.935 93.500 +*I mux_right_track_12\/mux_l1_in_0_:S I *L 0.00357 *C 49.580 99.960 +*N mux_tree_tapbuf_size4_4_sram[0]:3 *C 49.543 99.960 +*N mux_tree_tapbuf_size4_4_sram[0]:4 *C 48.805 99.960 +*N mux_tree_tapbuf_size4_4_sram[0]:5 *C 48.760 99.915 +*N mux_tree_tapbuf_size4_4_sram[0]:6 *C 48.935 93.500 +*N mux_tree_tapbuf_size4_4_sram[0]:7 *C 48.760 93.500 +*N mux_tree_tapbuf_size4_4_sram[0]:8 *C 48.760 93.500 +*N mux_tree_tapbuf_size4_4_sram[0]:9 *C 48.760 88.105 +*N mux_tree_tapbuf_size4_4_sram[0]:10 *C 48.805 88.060 +*N mux_tree_tapbuf_size4_4_sram[0]:11 *C 51.788 88.060 + +*CAP +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_12\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_4_sram[0]:3 4.651581e-05 +4 mux_tree_tapbuf_size4_4_sram[0]:4 4.651581e-05 +5 mux_tree_tapbuf_size4_4_sram[0]:5 0.0002759711 +6 mux_tree_tapbuf_size4_4_sram[0]:6 5.014156e-05 +7 mux_tree_tapbuf_size4_4_sram[0]:7 5.458085e-05 +8 mux_tree_tapbuf_size4_4_sram[0]:8 0.0005263694 +9 mux_tree_tapbuf_size4_4_sram[0]:9 0.0002212004 +10 mux_tree_tapbuf_size4_4_sram[0]:10 0.0001993136 +11 mux_tree_tapbuf_size4_4_sram[0]:11 0.0001993136 +12 mux_tree_tapbuf_size4_4_sram[0]:4 chany_top_in[10]:16 3.598676e-05 +13 mux_tree_tapbuf_size4_4_sram[0]:5 chany_top_in[10]:14 8.115399e-05 +14 mux_tree_tapbuf_size4_4_sram[0]:3 chany_top_in[10]:17 3.598676e-05 +15 mux_tree_tapbuf_size4_4_sram[0]:9 chany_top_in[10]:13 6.771498e-05 +16 mux_tree_tapbuf_size4_4_sram[0]:8 chany_top_in[10]:13 8.115399e-05 +17 mux_tree_tapbuf_size4_4_sram[0]:8 chany_top_in[10]:14 6.771498e-05 + +*RES +0 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_4_sram[0]:11 0.152 +1 mux_tree_tapbuf_size4_4_sram[0]:4 mux_tree_tapbuf_size4_4_sram[0]:3 0.0006584822 +2 mux_tree_tapbuf_size4_4_sram[0]:5 mux_tree_tapbuf_size4_4_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size4_4_sram[0]:3 mux_right_track_12\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size4_4_sram[0]:10 mux_tree_tapbuf_size4_4_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size4_4_sram[0]:9 mux_tree_tapbuf_size4_4_sram[0]:8 0.004816965 +6 mux_tree_tapbuf_size4_4_sram[0]:11 mux_tree_tapbuf_size4_4_sram[0]:10 0.002662946 +7 mux_tree_tapbuf_size4_4_sram[0]:7 mux_tree_tapbuf_size4_4_sram[0]:6 9.510871e-05 +8 mux_tree_tapbuf_size4_4_sram[0]:8 mux_tree_tapbuf_size4_4_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size4_4_sram[0]:8 mux_tree_tapbuf_size4_4_sram[0]:5 0.005727679 +10 mux_tree_tapbuf_size4_4_sram[0]:6 mem_right_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[1] 0.004062333 //LENGTH 28.205 LUMPCC 0.0005869436 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 39.865 71.740 +*I mux_top_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 31.840 69.070 +*I mux_top_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 26.780 72.760 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 23.635 75.140 +*N mux_tree_tapbuf_size5_1_sram[1]:4 *C 31.740 69.105 +*N mux_tree_tapbuf_size5_1_sram[1]:5 *C 23.672 75.140 +*N mux_tree_tapbuf_size5_1_sram[1]:6 *C 27.095 75.140 +*N mux_tree_tapbuf_size5_1_sram[1]:7 *C 27.140 75.095 +*N mux_tree_tapbuf_size5_1_sram[1]:8 *C 26.795 72.760 +*N mux_tree_tapbuf_size5_1_sram[1]:9 *C 27.117 72.760 +*N mux_tree_tapbuf_size5_1_sram[1]:10 *C 27.140 72.760 +*N mux_tree_tapbuf_size5_1_sram[1]:11 *C 27.140 68.725 +*N mux_tree_tapbuf_size5_1_sram[1]:12 *C 27.185 68.680 +*N mux_tree_tapbuf_size5_1_sram[1]:13 *C 31.765 68.680 +*N mux_tree_tapbuf_size5_1_sram[1]:14 *C 31.840 69.070 +*N mux_tree_tapbuf_size5_1_sram[1]:15 *C 31.740 69.700 +*N mux_tree_tapbuf_size5_1_sram[1]:16 *C 39.515 69.700 +*N mux_tree_tapbuf_size5_1_sram[1]:17 *C 39.560 69.745 +*N mux_tree_tapbuf_size5_1_sram[1]:18 *C 39.560 71.695 +*N mux_tree_tapbuf_size5_1_sram[1]:19 *C 39.560 71.740 +*N mux_tree_tapbuf_size5_1_sram[1]:20 *C 39.865 71.740 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_16\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size5_1_sram[1]:4 1.209773e-05 +5 mux_tree_tapbuf_size5_1_sram[1]:5 0.0002798911 +6 mux_tree_tapbuf_size5_1_sram[1]:6 0.0002798911 +7 mux_tree_tapbuf_size5_1_sram[1]:7 0.0001639117 +8 mux_tree_tapbuf_size5_1_sram[1]:8 6.256417e-05 +9 mux_tree_tapbuf_size5_1_sram[1]:9 6.256417e-05 +10 mux_tree_tapbuf_size5_1_sram[1]:10 0.0004694021 +11 mux_tree_tapbuf_size5_1_sram[1]:11 0.0002747729 +12 mux_tree_tapbuf_size5_1_sram[1]:12 0.0003339975 +13 mux_tree_tapbuf_size5_1_sram[1]:13 0.0003585471 +14 mux_tree_tapbuf_size5_1_sram[1]:14 9.700274e-05 +15 mux_tree_tapbuf_size5_1_sram[1]:15 0.0003583948 +16 mux_tree_tapbuf_size5_1_sram[1]:16 0.0003263251 +17 mux_tree_tapbuf_size5_1_sram[1]:17 0.0001488152 +18 mux_tree_tapbuf_size5_1_sram[1]:18 0.0001488152 +19 mux_tree_tapbuf_size5_1_sram[1]:19 4.930697e-05 +20 mux_tree_tapbuf_size5_1_sram[1]:20 4.508972e-05 +21 mux_tree_tapbuf_size5_1_sram[1]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000246229 +22 mux_tree_tapbuf_size5_1_sram[1]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.416607e-06 +23 mux_tree_tapbuf_size5_1_sram[1]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.686262e-07 +24 mux_tree_tapbuf_size5_1_sram[1]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.686262e-07 +25 mux_tree_tapbuf_size5_1_sram[1]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.038255e-06 +26 mux_tree_tapbuf_size5_1_sram[1]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002476074 +27 mux_tree_tapbuf_size5_1_sram[1]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.385755e-05 +28 mux_tree_tapbuf_size5_1_sram[1]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.385755e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_1_sram[1]:20 0.152 +1 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:8 0.0001752718 +2 mux_tree_tapbuf_size5_1_sram[1]:10 mux_tree_tapbuf_size5_1_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size5_1_sram[1]:10 mux_tree_tapbuf_size5_1_sram[1]:7 0.002084821 +4 mux_tree_tapbuf_size5_1_sram[1]:8 mux_top_track_16\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:15 0.006941964 +6 mux_tree_tapbuf_size5_1_sram[1]:17 mux_tree_tapbuf_size5_1_sram[1]:16 0.0045 +7 mux_tree_tapbuf_size5_1_sram[1]:19 mux_tree_tapbuf_size5_1_sram[1]:18 0.0045 +8 mux_tree_tapbuf_size5_1_sram[1]:18 mux_tree_tapbuf_size5_1_sram[1]:17 0.001741071 +9 mux_tree_tapbuf_size5_1_sram[1]:20 mux_tree_tapbuf_size5_1_sram[1]:19 0.0001657609 +10 mux_tree_tapbuf_size5_1_sram[1]:12 mux_tree_tapbuf_size5_1_sram[1]:11 0.0045 +11 mux_tree_tapbuf_size5_1_sram[1]:11 mux_tree_tapbuf_size5_1_sram[1]:10 0.003602679 +12 mux_tree_tapbuf_size5_1_sram[1]:14 mux_top_track_16\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:13 0.000203125 +14 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:4 1.822917e-05 +15 mux_tree_tapbuf_size5_1_sram[1]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.003055803 +16 mux_tree_tapbuf_size5_1_sram[1]:7 mux_tree_tapbuf_size5_1_sram[1]:6 0.0045 +17 mux_tree_tapbuf_size5_1_sram[1]:5 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size5_1_sram[1]:13 mux_tree_tapbuf_size5_1_sram[1]:12 0.004089286 +19 mux_tree_tapbuf_size5_1_sram[1]:15 mux_tree_tapbuf_size5_1_sram[1]:14 0.0005625001 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[0] 0.004894517 //LENGTH 43.545 LUMPCC 0.0001943792 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.205 60.860 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.015 42.500 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 51.160 36.040 +*I mux_bottom_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 50.140 31.110 +*I mux_bottom_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 50.240 66.565 +*N mux_tree_tapbuf_size6_4_sram[0]:5 *C 50.140 66.640 +*N mux_tree_tapbuf_size6_4_sram[0]:6 *C 50.140 66.595 +*N mux_tree_tapbuf_size6_4_sram[0]:7 *C 50.140 31.110 +*N mux_tree_tapbuf_size6_4_sram[0]:8 *C 50.140 31.280 +*N mux_tree_tapbuf_size6_4_sram[0]:9 *C 50.140 31.325 +*N mux_tree_tapbuf_size6_4_sram[0]:10 *C 51.123 36.040 +*N mux_tree_tapbuf_size6_4_sram[0]:11 *C 50.140 36.040 +*N mux_tree_tapbuf_size6_4_sram[0]:12 *C 50.140 36.380 +*N mux_tree_tapbuf_size6_4_sram[0]:13 *C 50.140 36.380 +*N mux_tree_tapbuf_size6_4_sram[0]:14 *C 48.053 42.500 +*N mux_tree_tapbuf_size6_4_sram[0]:15 *C 50.095 42.500 +*N mux_tree_tapbuf_size6_4_sram[0]:16 *C 50.140 42.500 +*N mux_tree_tapbuf_size6_4_sram[0]:17 *C 50.140 60.860 +*N mux_tree_tapbuf_size6_4_sram[0]:18 *C 50.185 60.860 +*N mux_tree_tapbuf_size6_4_sram[0]:19 *C 53.168 60.860 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_1\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_track_1\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_4_sram[0]:5 3.081094e-05 +6 mux_tree_tapbuf_size6_4_sram[0]:6 0.0003073113 +7 mux_tree_tapbuf_size6_4_sram[0]:7 4.015334e-05 +8 mux_tree_tapbuf_size6_4_sram[0]:8 4.589964e-05 +9 mux_tree_tapbuf_size6_4_sram[0]:9 0.0002747057 +10 mux_tree_tapbuf_size6_4_sram[0]:10 9.169095e-05 +11 mux_tree_tapbuf_size6_4_sram[0]:11 0.000122892 +12 mux_tree_tapbuf_size6_4_sram[0]:12 6.843766e-05 +13 mux_tree_tapbuf_size6_4_sram[0]:13 0.0005597264 +14 mux_tree_tapbuf_size6_4_sram[0]:14 0.0001513981 +15 mux_tree_tapbuf_size6_4_sram[0]:15 0.0001513981 +16 mux_tree_tapbuf_size6_4_sram[0]:16 0.001202337 +17 mux_tree_tapbuf_size6_4_sram[0]:17 0.001254156 +18 mux_tree_tapbuf_size6_4_sram[0]:18 0.0001971109 +19 mux_tree_tapbuf_size6_4_sram[0]:19 0.0001971109 +20 mux_tree_tapbuf_size6_4_sram[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.434501e-05 +21 mux_tree_tapbuf_size6_4_sram[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.205552e-05 +22 mux_tree_tapbuf_size6_4_sram[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.205552e-05 +23 mux_tree_tapbuf_size6_4_sram[0]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.434501e-05 +24 mux_tree_tapbuf_size6_4_sram[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.890886e-07 +25 mux_tree_tapbuf_size6_4_sram[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.890886e-07 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_4_sram[0]:19 0.152 +1 mux_tree_tapbuf_size6_4_sram[0]:5 mux_bottom_track_1\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_4_sram[0]:6 mux_tree_tapbuf_size6_4_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size6_4_sram[0]:7 mux_bottom_track_1\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size6_4_sram[0]:8 mux_tree_tapbuf_size6_4_sram[0]:7 7.327587e-05 +5 mux_tree_tapbuf_size6_4_sram[0]:9 mux_tree_tapbuf_size6_4_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size6_4_sram[0]:15 mux_tree_tapbuf_size6_4_sram[0]:14 0.001823661 +7 mux_tree_tapbuf_size6_4_sram[0]:16 mux_tree_tapbuf_size6_4_sram[0]:15 0.0045 +8 mux_tree_tapbuf_size6_4_sram[0]:16 mux_tree_tapbuf_size6_4_sram[0]:13 0.005464287 +9 mux_tree_tapbuf_size6_4_sram[0]:14 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size6_4_sram[0]:18 mux_tree_tapbuf_size6_4_sram[0]:17 0.0045 +11 mux_tree_tapbuf_size6_4_sram[0]:17 mux_tree_tapbuf_size6_4_sram[0]:16 0.01639286 +12 mux_tree_tapbuf_size6_4_sram[0]:17 mux_tree_tapbuf_size6_4_sram[0]:6 0.005120536 +13 mux_tree_tapbuf_size6_4_sram[0]:19 mux_tree_tapbuf_size6_4_sram[0]:18 0.002662947 +14 mux_tree_tapbuf_size6_4_sram[0]:12 mux_tree_tapbuf_size6_4_sram[0]:11 0.0003035715 +15 mux_tree_tapbuf_size6_4_sram[0]:13 mux_tree_tapbuf_size6_4_sram[0]:12 0.0045 +16 mux_tree_tapbuf_size6_4_sram[0]:13 mux_tree_tapbuf_size6_4_sram[0]:9 0.004513393 +17 mux_tree_tapbuf_size6_4_sram[0]:10 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size6_4_sram[0]:11 mux_tree_tapbuf_size6_4_sram[0]:10 0.0008772322 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[2] 0.001418046 //LENGTH 10.805 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 63.785 102.000 +*I mux_right_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 67.980 99.960 +*I mem_right_track_4\/FTB_21__51:A I *L 0.001746 *C 63.480 104.720 +*N mux_tree_tapbuf_size7_1_sram[2]:3 *C 63.518 104.720 +*N mux_tree_tapbuf_size7_1_sram[2]:4 *C 63.895 104.720 +*N mux_tree_tapbuf_size7_1_sram[2]:5 *C 63.940 104.675 +*N mux_tree_tapbuf_size7_1_sram[2]:6 *C 63.940 102.095 +*N mux_tree_tapbuf_size7_1_sram[2]:7 *C 67.943 99.960 +*N mux_tree_tapbuf_size7_1_sram[2]:8 *C 64.445 99.960 +*N mux_tree_tapbuf_size7_1_sram[2]:9 *C 64.400 100.005 +*N mux_tree_tapbuf_size7_1_sram[2]:10 *C 64.400 101.660 +*N mux_tree_tapbuf_size7_1_sram[2]:11 *C 63.985 101.660 +*N mux_tree_tapbuf_size7_1_sram[2]:12 *C 63.940 102.125 +*N mux_tree_tapbuf_size7_1_sram[2]:13 *C 63.940 102.000 +*N mux_tree_tapbuf_size7_1_sram[2]:14 *C 63.785 102.000 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_4\/FTB_21__51:A 1e-06 +3 mux_tree_tapbuf_size7_1_sram[2]:3 4.347566e-05 +4 mux_tree_tapbuf_size7_1_sram[2]:4 4.347566e-05 +5 mux_tree_tapbuf_size7_1_sram[2]:5 0.0001511635 +6 mux_tree_tapbuf_size7_1_sram[2]:6 1.558604e-05 +7 mux_tree_tapbuf_size7_1_sram[2]:7 0.0002755756 +8 mux_tree_tapbuf_size7_1_sram[2]:8 0.0002755756 +9 mux_tree_tapbuf_size7_1_sram[2]:9 0.0001132405 +10 mux_tree_tapbuf_size7_1_sram[2]:10 0.0001426371 +11 mux_tree_tapbuf_size7_1_sram[2]:11 4.890403e-05 +12 mux_tree_tapbuf_size7_1_sram[2]:12 0.0001862571 +13 mux_tree_tapbuf_size7_1_sram[2]:13 6.099824e-05 +14 mux_tree_tapbuf_size7_1_sram[2]:14 5.815717e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_1_sram[2]:14 0.152 +1 mux_tree_tapbuf_size7_1_sram[2]:13 mux_tree_tapbuf_size7_1_sram[2]:12 0.0045 +2 mux_tree_tapbuf_size7_1_sram[2]:12 mux_tree_tapbuf_size7_1_sram[2]:11 0.000290625 +3 mux_tree_tapbuf_size7_1_sram[2]:12 mux_tree_tapbuf_size7_1_sram[2]:6 1.875e-05 +4 mux_tree_tapbuf_size7_1_sram[2]:12 mux_tree_tapbuf_size7_1_sram[2]:5 0.002276786 +5 mux_tree_tapbuf_size7_1_sram[2]:14 mux_tree_tapbuf_size7_1_sram[2]:13 8.423915e-05 +6 mux_tree_tapbuf_size7_1_sram[2]:4 mux_tree_tapbuf_size7_1_sram[2]:3 0.0003370536 +7 mux_tree_tapbuf_size7_1_sram[2]:5 mux_tree_tapbuf_size7_1_sram[2]:4 0.0045 +8 mux_tree_tapbuf_size7_1_sram[2]:3 mem_right_track_4\/FTB_21__51:A 0.152 +9 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:7 0.003122768 +10 mux_tree_tapbuf_size7_1_sram[2]:9 mux_tree_tapbuf_size7_1_sram[2]:8 0.0045 +11 mux_tree_tapbuf_size7_1_sram[2]:7 mux_right_track_4\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_1_sram[2]:11 mux_tree_tapbuf_size7_1_sram[2]:10 0.0003705357 +13 mux_tree_tapbuf_size7_1_sram[2]:10 mux_tree_tapbuf_size7_1_sram[2]:9 0.001477679 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006198284 //LENGTH 5.325 LUMPCC 0.0001230219 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_2_:X O *L 0 *C 76.645 55.760 +*I mux_top_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 81.060 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 81.023 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 80.500 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.500 55.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 76.683 55.760 + +*CAP +0 mux_top_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.418097e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.939095e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002232223 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001980123 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size6_1_sram[1]:7 2.87398e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:8 3.277114e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:7 3.277114e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_1_sram[1]:8 2.87398e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003408482 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004665179 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001675386 //LENGTH 12.565 LUMPCC 0.0002310952 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 80.325 95.880 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 86.580 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.543 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.640 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 84.640 91.120 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 81.005 91.120 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 80.960 91.165 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 80.960 95.835 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 80.915 95.880 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 80.362 95.880 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001522304 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001810494 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000292602 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000263783 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002020421 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002020421 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.42706e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.42706e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_45_[0]:16 0.0001155476 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_45_[0]:17 0.0001155476 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003245535 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.004169643 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0004933036 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001698661 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007836048 //LENGTH 6.850 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 79.865 28.220 +*I mux_bottom_track_5\/mux_l3_in_0_:A1 I *L 0.005458 *C 80.375 23.043 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 80.500 22.950 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 80.500 22.995 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 80.500 28.175 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 80.455 28.220 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 79.903 28.220 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A1 4.275756e-05 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.275756e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002754737 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002754737 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.307114e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.307114e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A1 7.692308e-05 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.004625001 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004933036 + +*END + +*D_NET optlc_net_185 0.008045659 //LENGTH 64.260 LUMPCC 0.0003870106 DR + +*CONN +*I optlc_175:HI O *L 0 *C 52.440 39.100 +*I mux_bottom_track_33\/mux_l1_in_1_:A0 I *L 0.001631 *C 35.135 37.060 +*I mux_right_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 29.155 42.500 +*I mux_bottom_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 48.590 33.660 +*I mux_bottom_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 62.850 37.400 +*I mux_bottom_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 63.310 44.200 +*N optlc_net_185:6 *C 63.310 44.200 +*N optlc_net_185:7 *C 63.020 44.200 +*N optlc_net_185:8 *C 63.020 44.155 +*N optlc_net_185:9 *C 62.850 37.400 +*N optlc_net_185:10 *C 63.020 37.400 +*N optlc_net_185:11 *C 63.020 37.445 +*N optlc_net_185:12 *C 63.020 38.760 +*N optlc_net_185:13 *C 62.975 38.760 +*N optlc_net_185:14 *C 48.628 33.660 +*N optlc_net_185:15 *C 51.935 33.660 +*N optlc_net_185:16 *C 51.980 33.705 +*N optlc_net_185:17 *C 51.980 38.760 +*N optlc_net_185:18 *C 29.155 42.500 +*N optlc_net_185:19 *C 29.440 42.500 +*N optlc_net_185:20 *C 29.440 42.455 +*N optlc_net_185:21 *C 35.098 37.060 +*N optlc_net_185:22 *C 29.485 37.060 +*N optlc_net_185:23 *C 29.440 37.105 +*N optlc_net_185:24 *C 29.440 38.760 +*N optlc_net_185:25 *C 29.448 38.760 +*N optlc_net_185:26 *C 52.433 38.760 +*N optlc_net_185:27 *C 52.440 38.760 +*N optlc_net_185:28 *C 52.477 38.760 +*N optlc_net_185:29 *C 52.440 39.100 + +*CAP +0 optlc_175:HI 1e-06 +1 mux_bottom_track_33\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_24\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_track_1\/mux_l2_in_1_:A0 1e-06 +4 mux_bottom_track_3\/mux_l2_in_1_:A0 1e-06 +5 mux_bottom_track_25\/mux_l2_in_1_:A0 1e-06 +6 optlc_net_185:6 5.294922e-05 +7 optlc_net_185:7 5.626027e-05 +8 optlc_net_185:8 0.0002980278 +9 optlc_net_185:9 5.049091e-05 +10 optlc_net_185:10 5.504805e-05 +11 optlc_net_185:11 7.847652e-05 +12 optlc_net_185:12 0.0004053441 +13 optlc_net_185:13 0.0006875904 +14 optlc_net_185:14 0.0002131841 +15 optlc_net_185:15 0.0002131841 +16 optlc_net_185:16 0.0003166195 +17 optlc_net_185:17 0.0003489049 +18 optlc_net_185:18 5.383648e-05 +19 optlc_net_185:19 5.410357e-05 +20 optlc_net_185:20 0.0002388398 +21 optlc_net_185:21 0.0003230732 +22 optlc_net_185:22 0.0003230732 +23 optlc_net_185:23 0.0001078175 +24 optlc_net_185:24 0.0003761882 +25 optlc_net_185:25 0.001270736 +26 optlc_net_185:26 0.001270736 +27 optlc_net_185:27 6.573422e-05 +28 optlc_net_185:28 0.0007252176 +29 optlc_net_185:29 6.72144e-05 +30 optlc_net_185:25 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001935053 +31 optlc_net_185:26 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001935053 + +*RES +0 optlc_175:HI optlc_net_185:29 0.152 +1 optlc_net_185:22 optlc_net_185:21 0.005011161 +2 optlc_net_185:23 optlc_net_185:22 0.0045 +3 optlc_net_185:21 mux_bottom_track_33\/mux_l1_in_1_:A0 0.152 +4 optlc_net_185:24 optlc_net_185:23 0.001477679 +5 optlc_net_185:24 optlc_net_185:20 0.003299107 +6 optlc_net_185:25 optlc_net_185:24 0.00341 +7 optlc_net_185:27 optlc_net_185:26 0.00341 +8 optlc_net_185:27 optlc_net_185:17 0.0004107143 +9 optlc_net_185:26 optlc_net_185:25 0.003600983 +10 optlc_net_185:15 optlc_net_185:14 0.002953125 +11 optlc_net_185:16 optlc_net_185:15 0.0045 +12 optlc_net_185:14 mux_bottom_track_1\/mux_l2_in_1_:A0 0.152 +13 optlc_net_185:13 optlc_net_185:12 0.0045 +14 optlc_net_185:12 optlc_net_185:11 0.001174107 +15 optlc_net_185:12 optlc_net_185:8 0.004816964 +16 optlc_net_185:28 optlc_net_185:27 0.0045 +17 optlc_net_185:28 optlc_net_185:13 0.009372769 +18 optlc_net_185:19 optlc_net_185:18 0.0001548913 +19 optlc_net_185:20 optlc_net_185:19 0.0045 +20 optlc_net_185:18 mux_right_track_24\/mux_l2_in_1_:A0 0.152 +21 optlc_net_185:7 optlc_net_185:6 0.0001576087 +22 optlc_net_185:8 optlc_net_185:7 0.0045 +23 optlc_net_185:6 mux_bottom_track_25\/mux_l2_in_1_:A0 0.152 +24 optlc_net_185:10 optlc_net_185:9 9.239131e-05 +25 optlc_net_185:11 optlc_net_185:10 0.0045 +26 optlc_net_185:9 mux_bottom_track_3\/mux_l2_in_1_:A0 0.152 +27 optlc_net_185:29 optlc_net_185:28 0.0001465517 +28 optlc_net_185:17 optlc_net_185:16 0.004513393 + +*END + +*D_NET mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0] 0.004051437 //LENGTH 31.085 LUMPCC 0.001057236 DR + +*CONN +*I mux_right_track_14\/mux_l3_in_0_:X O *L 0 *C 85.845 86.360 +*I mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 100.590 71.935 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 100.627 71.935 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 101.155 71.978 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 101.200 72.125 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 101.200 86.315 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 101.155 86.360 +*N mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 85.883 86.360 + +*CAP +0 mux_right_track_14\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.417418e-05 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.417418e-05 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0006479412 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0006479412 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0008039851 +7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0008039851 +8 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_right_out[4]:4 0.0001746318 +9 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_right_out[4]:3 0.0001746318 +10 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:2 7.312565e-05 +11 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size4_mem_5_ccff_tail[0]:3 7.312565e-05 +12 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002808604 +13 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002808604 + +*RES +0 mux_right_track_14\/mux_l3_in_0_:X mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.01363616 +2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.01266964 +4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004709822 +5 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.006181075 //LENGTH 44.550 LUMPCC 0.0009302249 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_0_:X O *L 0 *C 68.825 98.600 +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 99.085 85.865 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 99.047 85.965 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 92.045 86.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 92.000 86.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 92.000 86.360 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 91.993 86.360 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 87.420 86.360 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 87.400 86.368 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 87.400 96.553 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 87.380 96.560 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 69.008 96.560 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 69.000 96.618 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 69.000 98.555 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 69.000 98.600 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 68.825 98.600 + +*CAP +0 mux_right_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002442172 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002442172 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.084236e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.481501e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0003428989 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003428989 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.000566392 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.000566392 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001234822 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.001234822 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.000126047 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.000126047 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 5.684948e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 5.758871e-05 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chany_top_in[19]:7 0.000184252 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chany_top_in[19]:6 0.000184252 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002808604 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_14/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002808604 + +*RES +0 mux_right_track_4\/mux_l3_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 9.51087e-05 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.001729911 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.002878358 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.00159565 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0007163583 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001634615 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.006252233 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001334669 //LENGTH 10.420 LUMPCC 0.0003221589 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_1_:X O *L 0 *C 37.085 36.040 +*I mux_bottom_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 37.090 26.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 37.090 26.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.260 26.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 37.260 26.565 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 37.260 35.995 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 37.260 36.040 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 37.085 36.040 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.081412e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.294557e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003999404 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003999404 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.258565e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.428421e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_4_sram[0]:8 7.113769e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size3_4_sram[0]:10 4.258919e-06 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_4_sram[0]:9 7.113769e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size3_4_sram[0]:5 4.258919e-06 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.79992e-07 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.79992e-07 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.500282e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.500282e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_1_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.008419643 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_235 0.001517737 //LENGTH 8.850 LUMPCC 0.000591133 DR + +*CONN +*I ropt_mt_inst_833:X O *L 0 *C 110.135 71.400 +*I ropt_mt_inst_855:A I *L 0.001767 *C 106.260 69.360 +*N ropt_net_235:2 *C 106.260 69.360 +*N ropt_net_235:3 *C 106.260 69.315 +*N ropt_net_235:4 *C 106.260 68.737 +*N ropt_net_235:5 *C 106.267 68.680 +*N ropt_net_235:6 *C 110.392 68.680 +*N ropt_net_235:7 *C 110.400 68.737 +*N ropt_net_235:8 *C 110.400 71.355 +*N ropt_net_235:9 *C 110.400 71.400 +*N ropt_net_235:10 *C 110.135 71.400 + +*CAP +0 ropt_mt_inst_833:X 1e-06 +1 ropt_mt_inst_855:A 1e-06 +2 ropt_net_235:2 3.903718e-05 +3 ropt_net_235:3 6.73418e-05 +4 ropt_net_235:4 6.73418e-05 +5 ropt_net_235:5 0.0001523217 +6 ropt_net_235:6 0.0001523217 +7 ropt_net_235:7 0.0001651065 +8 ropt_net_235:8 0.0001651065 +9 ropt_net_235:9 5.274417e-05 +10 ropt_net_235:10 6.328301e-05 +11 ropt_net_235:5 chanx_right_in[7]:10 0.0002470024 +12 ropt_net_235:6 chanx_right_in[7] 0.0002470024 +13 ropt_net_235:5 chanx_right_out[17]:2 4.856407e-05 +14 ropt_net_235:6 chanx_right_out[17] 4.856407e-05 + +*RES +0 ropt_mt_inst_833:X ropt_net_235:10 0.152 +1 ropt_net_235:2 ropt_mt_inst_855:A 0.152 +2 ropt_net_235:3 ropt_net_235:2 0.0045 +3 ropt_net_235:4 ropt_net_235:3 0.000515625 +4 ropt_net_235:5 ropt_net_235:4 0.00341 +5 ropt_net_235:7 ropt_net_235:6 0.00341 +6 ropt_net_235:6 ropt_net_235:5 0.00064625 +7 ropt_net_235:9 ropt_net_235:8 0.0045 +8 ropt_net_235:8 ropt_net_235:7 0.002337054 +9 ropt_net_235:10 ropt_net_235:9 0.0001440218 + +*END + +*D_NET chany_top_out[5] 0.0008464307 //LENGTH 6.135 LUMPCC 0.0001501487 DR + +*CONN +*I ropt_mt_inst_852:X O *L 0 *C 41.400 126.820 +*P chany_top_out[5] O *L 0.7423 *C 44.620 129.270 +*N chany_top_out[5]:2 *C 44.620 126.865 +*N chany_top_out[5]:3 *C 44.575 126.820 +*N chany_top_out[5]:4 *C 41.438 126.820 + +*CAP +0 ropt_mt_inst_852:X 1e-06 +1 chany_top_out[5] 0.0001577539 +2 chany_top_out[5]:2 0.0001577539 +3 chany_top_out[5]:3 0.0001898871 +4 chany_top_out[5]:4 0.0001898871 +5 chany_top_out[5]:4 ropt_net_232:2 7.431489e-05 +6 chany_top_out[5]:4 ropt_net_232:4 7.594816e-07 +7 chany_top_out[5]:3 ropt_net_232:3 7.431489e-05 +8 chany_top_out[5]:3 ropt_net_232:5 7.594816e-07 + +*RES +0 ropt_mt_inst_852:X chany_top_out[5]:4 0.152 +1 chany_top_out[5]:4 chany_top_out[5]:3 0.002801339 +2 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +3 chany_top_out[5]:2 chany_top_out[5] 0.002147322 + +*END + +*D_NET ropt_net_212 0.001807379 //LENGTH 14.330 LUMPCC 0.000450462 DR + +*CONN +*I BUFT_RR_90:X O *L 0 *C 104.880 63.240 +*I ropt_mt_inst_833:A I *L 0.001766 *C 106.260 72.080 +*N ropt_net_212:2 *C 106.238 72.053 +*N ropt_net_212:3 *C 106.225 71.740 +*N ropt_net_212:4 *C 105.845 71.740 +*N ropt_net_212:5 *C 105.800 71.695 +*N ropt_net_212:6 *C 105.800 63.625 +*N ropt_net_212:7 *C 105.755 63.580 +*N ropt_net_212:8 *C 103.500 63.580 +*N ropt_net_212:9 *C 103.500 63.240 +*N ropt_net_212:10 *C 104.843 63.240 + +*CAP +0 BUFT_RR_90:X 1e-06 +1 ropt_mt_inst_833:A 1e-06 +2 ropt_net_212:2 3.007525e-05 +3 ropt_net_212:3 6.949327e-05 +4 ropt_net_212:4 3.941802e-05 +5 ropt_net_212:5 0.0003223303 +6 ropt_net_212:6 0.0003223303 +7 ropt_net_212:7 0.0001845923 +8 ropt_net_212:8 0.0002111114 +9 ropt_net_212:9 0.0001010426 +10 ropt_net_212:10 7.452347e-05 +11 ropt_net_212:5 chanx_right_out[6]:4 0.000225231 +12 ropt_net_212:6 chanx_right_out[6]:3 0.000225231 + +*RES +0 BUFT_RR_90:X ropt_net_212:10 0.152 +1 ropt_net_212:2 ropt_mt_inst_833:A 0.152 +2 ropt_net_212:4 ropt_net_212:3 0.0003392857 +3 ropt_net_212:5 ropt_net_212:4 0.0045 +4 ropt_net_212:7 ropt_net_212:6 0.0045 +5 ropt_net_212:6 ropt_net_212:5 0.007205357 +6 ropt_net_212:10 ropt_net_212:9 0.001198661 +7 ropt_net_212:9 ropt_net_212:8 0.0003035715 +8 ropt_net_212:8 ropt_net_212:7 0.002013393 +9 ropt_net_212:3 ropt_net_212:2 0.0002111487 + +*END + +*D_NET ropt_net_209 0.001228743 //LENGTH 10.240 LUMPCC 0 DR + +*CONN +*I BUFT_P_140:X O *L 0 *C 40.020 121.720 +*I ropt_mt_inst_830:A I *L 0.001766 *C 42.780 123.760 +*N ropt_net_209:2 *C 42.780 123.760 +*N ropt_net_209:3 *C 42.780 124.440 +*N ropt_net_209:4 *C 39.560 124.440 +*N ropt_net_209:5 *C 39.560 123.760 +*N ropt_net_209:6 *C 38.685 123.760 +*N ropt_net_209:7 *C 38.640 123.715 +*N ropt_net_209:8 *C 38.640 121.765 +*N ropt_net_209:9 *C 38.685 121.720 +*N ropt_net_209:10 *C 39.983 121.720 + +*CAP +0 BUFT_P_140:X 1e-06 +1 ropt_mt_inst_830:A 1e-06 +2 ropt_net_209:2 7.906459e-05 +3 ropt_net_209:3 0.0002606054 +4 ropt_net_209:4 0.0002570586 +5 ropt_net_209:5 0.0001038981 +6 ropt_net_209:6 5.908044e-05 +7 ropt_net_209:7 0.0001278584 +8 ropt_net_209:8 0.0001278584 +9 ropt_net_209:9 0.0001056595 +10 ropt_net_209:10 0.0001056595 + +*RES +0 BUFT_P_140:X ropt_net_209:10 0.152 +1 ropt_net_209:2 ropt_mt_inst_830:A 0.152 +2 ropt_net_209:6 ropt_net_209:5 0.0007812501 +3 ropt_net_209:7 ropt_net_209:6 0.0045 +4 ropt_net_209:9 ropt_net_209:8 0.0045 +5 ropt_net_209:8 ropt_net_209:7 0.001741072 +6 ropt_net_209:10 ropt_net_209:9 0.001158482 +7 ropt_net_209:5 ropt_net_209:4 0.0006071429 +8 ropt_net_209:4 ropt_net_209:3 0.002875 +9 ropt_net_209:3 ropt_net_209:2 0.000607143 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..0946df0 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef @@ -0,0 +1,8031 @@ +*SPEF "1481-1998" +*DESIGN "sb_0__2_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 36.340 0.680 +chanx_right_in[0] I *C 112.470 87.040 +chanx_right_in[1] I *C 112.470 57.120 +chanx_right_in[2] I *C 112.470 99.280 +chanx_right_in[3] I *C 112.470 96.560 +chanx_right_in[4] I *C 112.470 34.000 +chanx_right_in[5] I *C 112.470 62.560 +chanx_right_in[6] I *C 112.470 31.280 +chanx_right_in[7] I *C 112.470 50.320 +chanx_right_in[8] I *C 112.470 77.520 +chanx_right_in[9] I *C 112.470 35.360 +chanx_right_in[10] I *C 112.470 80.240 +chanx_right_in[11] I *C 112.470 58.480 +chanx_right_in[12] I *C 112.470 74.800 +chanx_right_in[13] I *C 112.470 36.720 +chanx_right_in[14] I *C 112.470 43.520 +chanx_right_in[15] I *C 112.470 55.760 +chanx_right_in[16] I *C 112.470 40.800 +chanx_right_in[17] I *C 112.470 61.200 +chanx_right_in[18] I *C 112.470 39.440 +chanx_right_in[19] I *C 112.470 72.080 +right_top_grid_pin_1_[0] I *C 109.940 102.680 +chany_bottom_in[0] I *C 65.780 0.680 +chany_bottom_in[1] I *C 14.720 0.680 +chany_bottom_in[2] I *C 71.300 0.680 +chany_bottom_in[3] I *C 13.800 0.680 +chany_bottom_in[4] I *C 73.140 0.680 +chany_bottom_in[5] I *C 49.220 0.680 +chany_bottom_in[6] I *C 52.900 0.680 +chany_bottom_in[7] I *C 22.080 0.680 +chany_bottom_in[8] I *C 23.920 0.680 +chany_bottom_in[9] I *C 23.000 0.680 +chany_bottom_in[10] I *C 51.980 0.680 +chany_bottom_in[11] I *C 30.820 0.680 +chany_bottom_in[12] I *C 63.940 0.680 +chany_bottom_in[13] I *C 72.220 0.680 +chany_bottom_in[14] I *C 43.700 0.680 +chany_bottom_in[15] I *C 46.460 0.680 +chany_bottom_in[16] I *C 41.860 0.680 +chany_bottom_in[17] I *C 29.900 0.680 +chany_bottom_in[18] I *C 26.680 0.680 +chany_bottom_in[19] I *C 24.840 0.680 +bottom_left_grid_pin_1_[0] I *C 2.300 0.680 +ccff_head[0] I *C 110.860 102.680 +chanx_right_out[0] O *C 112.470 73.440 +chanx_right_out[1] O *C 112.470 47.600 +chanx_right_out[2] O *C 112.470 53.040 +chanx_right_out[3] O *C 112.470 82.960 +chanx_right_out[4] O *C 112.470 78.880 +chanx_right_out[5] O *C 112.470 95.200 +chanx_right_out[6] O *C 112.470 84.320 +chanx_right_out[7] O *C 112.470 93.840 +chanx_right_out[8] O *C 112.470 85.680 +chanx_right_out[9] O *C 112.470 44.880 +chanx_right_out[10] O *C 112.470 51.680 +chanx_right_out[11] O *C 112.470 69.360 +chanx_right_out[12] O *C 112.470 42.160 +chanx_right_out[13] O *C 112.470 66.640 +chanx_right_out[14] O *C 112.470 91.120 +chanx_right_out[15] O *C 112.470 68.000 +chanx_right_out[16] O *C 112.470 63.920 +chanx_right_out[17] O *C 112.470 88.400 +chanx_right_out[18] O *C 112.470 89.760 +chanx_right_out[19] O *C 112.470 46.240 +chany_bottom_out[0] O *C 50.140 0.680 +chany_bottom_out[1] O *C 34.500 0.680 +chany_bottom_out[2] O *C 66.700 0.680 +chany_bottom_out[3] O *C 44.620 0.680 +chany_bottom_out[4] O *C 51.060 0.680 +chany_bottom_out[5] O *C 45.540 0.680 +chany_bottom_out[6] O *C 70.380 0.680 +chany_bottom_out[7] O *C 68.540 0.680 +chany_bottom_out[8] O *C 69.460 0.680 +chany_bottom_out[9] O *C 25.760 0.680 +chany_bottom_out[10] O *C 42.780 0.680 +chany_bottom_out[11] O *C 48.300 0.680 +chany_bottom_out[12] O *C 67.620 0.680 +chany_bottom_out[13] O *C 49.680 0.680 +chany_bottom_out[14] O *C 46.000 0.680 +chany_bottom_out[15] O *C 47.840 0.680 +chany_bottom_out[16] O *C 28.520 0.680 +chany_bottom_out[17] O *C 47.380 0.680 +chany_bottom_out[18] O *C 23.920 0.680 +chany_bottom_out[19] O *C 25.760 0.680 +ccff_tail[0] O *C 54.280 0.680 +VDD I *C 56.580 51.680 +VSS I *C 56.580 51.680 + +*D_NET chanx_right_in[0] 0.0148509 //LENGTH 153.665 LUMPCC 0.001646014 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 111.930 87.040 +*I BUFT_RR_42:A I *L 0.001776 *C 33.120 14.960 +*N chanx_right_in[0]:2 *C 33.157 14.960 +*N chanx_right_in[0]:3 *C 34.455 14.960 +*N chanx_right_in[0]:4 *C 34.500 15.005 +*N chanx_right_in[0]:5 *C 34.500 64.800 +*N chanx_right_in[0]:6 *C 34.500 87.663 +*N chanx_right_in[0]:7 *C 34.508 87.720 +*N chanx_right_in[0]:8 *C 58.420 87.720 +*N chanx_right_in[0]:9 *C 58.420 87.040 + +*CAP +0 chanx_right_in[0] 0.002256515 +1 BUFT_RR_42:A 1e-06 +2 chanx_right_in[0]:2 9.352979e-05 +3 chanx_right_in[0]:3 9.352979e-05 +4 chanx_right_in[0]:4 0.002047793 +5 chanx_right_in[0]:5 0.003031913 +6 chanx_right_in[0]:6 0.0009841204 +7 chanx_right_in[0]:7 0.00117693 +8 chanx_right_in[0]:8 0.001219982 +9 chanx_right_in[0]:9 0.002299567 +10 chanx_right_in[0]:4 chanx_right_in[19]:10 0.0002209021 +11 chanx_right_in[0]:4 chanx_right_in[19]:11 1.260426e-05 +12 chanx_right_in[0]:6 chanx_right_in[19]:12 3.455915e-05 +13 chanx_right_in[0]:5 chanx_right_in[19]:12 1.260426e-05 +14 chanx_right_in[0]:5 chanx_right_in[19]:11 0.0002554613 +15 chanx_right_in[0] chany_bottom_in[10]:12 0.0002775929 +16 chanx_right_in[0]:7 chany_bottom_in[10]:13 1.753833e-05 +17 chanx_right_in[0]:8 chany_bottom_in[10]:12 1.753833e-05 +18 chanx_right_in[0]:9 chany_bottom_in[10]:13 0.0002775929 +19 chanx_right_in[0] ropt_net_156:6 9.261654e-05 +20 chanx_right_in[0]:9 ropt_net_156:7 9.261654e-05 +21 chanx_right_in[0] ropt_net_162:6 0.0001671938 +22 chanx_right_in[0]:9 ropt_net_162:7 0.0001671938 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:9 0.008383232 +1 chanx_right_in[0]:2 BUFT_RR_42:A 0.152 +2 chanx_right_in[0]:3 chanx_right_in[0]:2 0.001158482 +3 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0045 +4 chanx_right_in[0]:6 chanx_right_in[0]:5 0.02041295 +5 chanx_right_in[0]:7 chanx_right_in[0]:6 0.00341 +6 chanx_right_in[0]:8 chanx_right_in[0]:7 0.003746292 +7 chanx_right_in[0]:9 chanx_right_in[0]:8 0.0001065333 +8 chanx_right_in[0]:5 chanx_right_in[0]:4 0.04445983 + +*END + +*D_NET chanx_right_in[2] 0.0149674 //LENGTH 158.920 LUMPCC 0.0008497233 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 111.930 99.280 +*I BUFT_RR_44:A I *L 0.001776 *C 36.340 17.680 +*N chanx_right_in[2]:2 *C 59.393 47.600 +*N chanx_right_in[2]:3 *C 36.340 17.680 +*N chanx_right_in[2]:4 *C 36.340 17.725 +*N chanx_right_in[2]:5 *C 36.340 46.875 +*N chanx_right_in[2]:6 *C 36.385 46.920 +*N chanx_right_in[2]:7 *C 56.905 46.920 +*N chanx_right_in[2]:8 *C 57.025 46.965 +*N chanx_right_in[2]:9 *C 57.040 47.570 +*N chanx_right_in[2]:10 *C 57.085 47.600 +*N chanx_right_in[2]:11 *C 59.438 47.608 +*N chanx_right_in[2]:12 *C 59.340 47.645 +*N chanx_right_in[2]:13 *C 59.340 99.223 +*N chanx_right_in[2]:14 *C 59.348 99.280 + +*CAP +0 chanx_right_in[2] 0.001972259 +1 BUFT_RR_44:A 1e-06 +2 chanx_right_in[2]:2 1.748005e-05 +3 chanx_right_in[2]:3 3.185537e-05 +4 chanx_right_in[2]:4 0.001384527 +5 chanx_right_in[2]:5 0.001384527 +6 chanx_right_in[2]:6 0.00121176 +7 chanx_right_in[2]:7 0.00121176 +8 chanx_right_in[2]:8 5.532752e-05 +9 chanx_right_in[2]:9 5.532752e-05 +10 chanx_right_in[2]:10 0.0001284453 +11 chanx_right_in[2]:11 0.0001459253 +12 chanx_right_in[2]:12 0.002272613 +13 chanx_right_in[2]:13 0.002272613 +14 chanx_right_in[2]:14 0.001972259 +15 chanx_right_in[2] chanx_right_in[3] 0.0004248616 +16 chanx_right_in[2]:14 chanx_right_in[3]:11 0.0004248616 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:14 0.008237924 +1 chanx_right_in[2]:10 chanx_right_in[2]:9 0.0045 +2 chanx_right_in[2]:9 chanx_right_in[2]:8 0.0005401786 +3 chanx_right_in[2]:7 chanx_right_in[2]:6 0.01832143 +4 chanx_right_in[2]:8 chanx_right_in[2]:7 0.0045 +5 chanx_right_in[2]:6 chanx_right_in[2]:5 0.0045 +6 chanx_right_in[2]:5 chanx_right_in[2]:4 0.02602679 +7 chanx_right_in[2]:3 BUFT_RR_44:A 0.152 +8 chanx_right_in[2]:4 chanx_right_in[2]:3 0.0045 +9 chanx_right_in[2]:11 chanx_right_in[2]:10 0.002100446 +10 chanx_right_in[2]:11 chanx_right_in[2]:2 4.017857e-05 +11 chanx_right_in[2]:12 chanx_right_in[2]:11 0.0045 +12 chanx_right_in[2]:13 chanx_right_in[2]:12 0.04605134 +13 chanx_right_in[2]:14 chanx_right_in[2]:13 0.00341 + +*END + +*D_NET chanx_right_in[6] 0.007139163 //LENGTH 58.705 LUMPCC 0.00228573 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 111.930 31.280 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 70.840 14.620 +*N chanx_right_in[6]:2 *C 70.862 14.648 +*N chanx_right_in[6]:3 *C 70.875 14.960 +*N chanx_right_in[6]:4 *C 75.855 14.960 +*N chanx_right_in[6]:5 *C 75.900 15.005 +*N chanx_right_in[6]:6 *C 75.900 31.223 +*N chanx_right_in[6]:7 *C 75.907 31.280 + +*CAP +0 chanx_right_in[6] 0.001273958 +1 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[6]:2 3.097319e-05 +3 chanx_right_in[6]:3 0.0003568875 +4 chanx_right_in[6]:4 0.0003259143 +5 chanx_right_in[6]:5 0.0007953713 +6 chanx_right_in[6]:6 0.0007953713 +7 chanx_right_in[6]:7 0.001273958 +8 chanx_right_in[6] chany_bottom_in[2]:12 0.0003772762 +9 chanx_right_in[6]:5 chany_bottom_in[2]:15 6.352981e-06 +10 chanx_right_in[6]:6 chany_bottom_in[2]:14 6.352981e-06 +11 chanx_right_in[6]:7 chany_bottom_in[2]:13 0.0003772762 +12 chanx_right_in[6] chany_bottom_in[9]:10 0.0005760266 +13 chanx_right_in[6]:7 chany_bottom_in[9]:11 0.0005760266 +14 chanx_right_in[6]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 2.863419e-05 +15 chanx_right_in[6]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0001545751 +16 chanx_right_in[6]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0001545751 +17 chanx_right_in[6]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 2.863419e-05 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:7 0.005643524 +1 chanx_right_in[6]:2 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[6]:4 chanx_right_in[6]:3 0.004446429 +3 chanx_right_in[6]:5 chanx_right_in[6]:4 0.0045 +4 chanx_right_in[6]:6 chanx_right_in[6]:5 0.01447991 +5 chanx_right_in[6]:7 chanx_right_in[6]:6 0.00341 +6 chanx_right_in[6]:3 chanx_right_in[6]:2 0.0002111487 + +*END + +*D_NET right_top_grid_pin_1_[0] 0.009316442 //LENGTH 90.630 LUMPCC 0.0003900079 DR + +*CONN +*P right_top_grid_pin_1_[0] I *L 0.29796 *C 109.940 102.035 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 96.240 47.260 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 87.765 39.780 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 89.340 36.380 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 95.320 41.820 +*N right_top_grid_pin_1_[0]:5 *C 95.358 41.820 +*N right_top_grid_pin_1_[0]:6 *C 95.680 41.820 +*N right_top_grid_pin_1_[0]:7 *C 89.240 36.380 +*N right_top_grid_pin_1_[0]:8 *C 89.240 36.425 +*N right_top_grid_pin_1_[0]:9 *C 87.803 39.780 +*N right_top_grid_pin_1_[0]:10 *C 89.195 39.780 +*N right_top_grid_pin_1_[0]:11 *C 89.240 39.780 +*N right_top_grid_pin_1_[0]:12 *C 89.240 41.435 +*N right_top_grid_pin_1_[0]:13 *C 89.285 41.480 +*N right_top_grid_pin_1_[0]:14 *C 95.680 41.480 +*N right_top_grid_pin_1_[0]:15 *C 96.095 41.480 +*N right_top_grid_pin_1_[0]:16 *C 96.140 41.525 +*N right_top_grid_pin_1_[0]:17 *C 96.140 47.260 +*N right_top_grid_pin_1_[0]:18 *C 96.140 47.260 +*N right_top_grid_pin_1_[0]:19 *C 96.140 101.615 +*N right_top_grid_pin_1_[0]:20 *C 96.185 101.660 +*N right_top_grid_pin_1_[0]:21 *C 109.895 101.660 +*N right_top_grid_pin_1_[0]:22 *C 109.940 101.705 + +*CAP +0 right_top_grid_pin_1_[0] 3.123818e-05 +1 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +3 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +4 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +5 right_top_grid_pin_1_[0]:5 4.405999e-05 +6 right_top_grid_pin_1_[0]:6 6.772058e-05 +7 right_top_grid_pin_1_[0]:7 3.18023e-05 +8 right_top_grid_pin_1_[0]:8 0.0001957053 +9 right_top_grid_pin_1_[0]:9 0.00012592 +10 right_top_grid_pin_1_[0]:10 0.00012592 +11 right_top_grid_pin_1_[0]:11 0.000324966 +12 right_top_grid_pin_1_[0]:12 9.596726e-05 +13 right_top_grid_pin_1_[0]:13 0.0004100026 +14 right_top_grid_pin_1_[0]:14 0.0004726426 +15 right_top_grid_pin_1_[0]:15 3.897933e-05 +16 right_top_grid_pin_1_[0]:16 0.0002656037 +17 right_top_grid_pin_1_[0]:17 3.433214e-05 +18 right_top_grid_pin_1_[0]:18 0.00276067 +19 right_top_grid_pin_1_[0]:19 0.002462935 +20 right_top_grid_pin_1_[0]:20 0.0007013654 +21 right_top_grid_pin_1_[0]:21 0.0007013654 +22 right_top_grid_pin_1_[0]:22 3.123818e-05 +23 right_top_grid_pin_1_[0]:19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001388395 +24 right_top_grid_pin_1_[0]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.616443e-05 +25 right_top_grid_pin_1_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.616443e-05 +26 right_top_grid_pin_1_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001388395 + +*RES +0 right_top_grid_pin_1_[0] right_top_grid_pin_1_[0]:22 0.0002946429 +1 right_top_grid_pin_1_[0]:20 right_top_grid_pin_1_[0]:19 0.0045 +2 right_top_grid_pin_1_[0]:19 right_top_grid_pin_1_[0]:18 0.04853126 +3 right_top_grid_pin_1_[0]:21 right_top_grid_pin_1_[0]:20 0.01224107 +4 right_top_grid_pin_1_[0]:22 right_top_grid_pin_1_[0]:21 0.0045 +5 right_top_grid_pin_1_[0]:13 right_top_grid_pin_1_[0]:12 0.0045 +6 right_top_grid_pin_1_[0]:12 right_top_grid_pin_1_[0]:11 0.001477679 +7 right_top_grid_pin_1_[0]:15 right_top_grid_pin_1_[0]:14 0.0003705357 +8 right_top_grid_pin_1_[0]:16 right_top_grid_pin_1_[0]:15 0.0045 +9 right_top_grid_pin_1_[0]:5 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +10 right_top_grid_pin_1_[0]:7 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +11 right_top_grid_pin_1_[0]:8 right_top_grid_pin_1_[0]:7 0.0045 +12 right_top_grid_pin_1_[0]:10 right_top_grid_pin_1_[0]:9 0.001243304 +13 right_top_grid_pin_1_[0]:11 right_top_grid_pin_1_[0]:10 0.0045 +14 right_top_grid_pin_1_[0]:11 right_top_grid_pin_1_[0]:8 0.002995536 +15 right_top_grid_pin_1_[0]:9 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +16 right_top_grid_pin_1_[0]:17 mux_right_track_4\/mux_l1_in_0_:A1 0.152 +17 right_top_grid_pin_1_[0]:18 right_top_grid_pin_1_[0]:17 0.0045 +18 right_top_grid_pin_1_[0]:18 right_top_grid_pin_1_[0]:16 0.005120536 +19 right_top_grid_pin_1_[0]:14 right_top_grid_pin_1_[0]:13 0.005709822 +20 right_top_grid_pin_1_[0]:14 right_top_grid_pin_1_[0]:6 0.0003035715 +21 right_top_grid_pin_1_[0]:6 right_top_grid_pin_1_[0]:5 0.0002879465 + +*END + +*D_NET chanx_right_out[0] 0.00238453 //LENGTH 20.245 LUMPCC 0.0002002091 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 61.200 +*P chanx_right_out[0] O *L 0.7423 *C 111.930 73.440 +*N chanx_right_out[0]:2 *C 107.648 73.440 +*N chanx_right_out[0]:3 *C 107.640 73.383 +*N chanx_right_out[0]:4 *C 107.640 61.585 +*N chanx_right_out[0]:5 *C 107.595 61.540 +*N chanx_right_out[0]:6 *C 104.915 61.540 +*N chanx_right_out[0]:7 *C 104.903 61.228 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 0.0003181366 +2 chanx_right_out[0]:2 0.0003181366 +3 chanx_right_out[0]:3 0.0005848231 +4 chanx_right_out[0]:4 0.0005848231 +5 chanx_right_out[0]:5 0.0001602605 +6 chanx_right_out[0]:6 0.0001887009 +7 chanx_right_out[0]:7 2.844044e-05 +8 chanx_right_out[0]:3 ropt_net_168:5 5.40545e-05 +9 chanx_right_out[0]:5 ropt_net_168:3 4.605005e-05 +10 chanx_right_out[0]:4 ropt_net_168:4 5.40545e-05 +11 chanx_right_out[0]:6 ropt_net_168:2 4.605005e-05 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:7 0.152 +1 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +2 chanx_right_out[0]:2 chanx_right_out[0] 0.000670925 +3 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +4 chanx_right_out[0]:4 chanx_right_out[0]:3 0.01053348 +5 chanx_right_out[0]:7 chanx_right_out[0]:6 0.0002111487 +6 chanx_right_out[0]:6 chanx_right_out[0]:5 0.002392857 + +*END + +*D_NET chany_bottom_out[0] 0.0023698 //LENGTH 18.485 LUMPCC 0.0002799962 DR + +*CONN +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 46.920 15.300 +*P chany_bottom_out[0] O *L 0.7423 *C 50.140 1.290 +*N chany_bottom_out[0]:2 *C 50.140 15.595 +*N chany_bottom_out[0]:3 *C 50.095 15.640 +*N chany_bottom_out[0]:4 *C 46.920 15.640 +*N chany_bottom_out[0]:5 *C 46.920 15.300 + +*CAP +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[0] 0.0007648158 +2 chany_bottom_out[0]:2 0.0007648158 +3 chany_bottom_out[0]:3 0.0002353387 +4 chany_bottom_out[0]:4 0.0002644142 +5 chany_bottom_out[0]:5 5.941912e-05 +6 chany_bottom_out[0] ropt_net_148:4 0.0001399981 +7 chany_bottom_out[0]:2 ropt_net_148:5 0.0001399981 + +*RES +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[0]:5 0.152 +1 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +2 chany_bottom_out[0]:2 chany_bottom_out[0] 0.01277232 +3 chany_bottom_out[0]:5 chany_bottom_out[0]:4 0.0003035715 +4 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002834822 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.0008677832 //LENGTH 7.410 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 91.845 61.200 +*I mem_right_track_0\/FTB_1__32:A I *L 0.001746 *C 93.840 58.480 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 95.680 58.315 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 95.642 58.420 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 93.877 58.480 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 93.840 58.525 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 93.840 61.155 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 93.795 61.200 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 91.883 61.200 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_0\/FTB_1__32:A 1e-06 +2 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 0.0001279353 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0001279353 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.0001620114 +6 mux_tree_tapbuf_size2_0_sram[1]:6 0.0001620114 +7 mux_tree_tapbuf_size2_0_sram[1]:7 0.0001424449 +8 mux_tree_tapbuf_size2_0_sram[1]:8 0.0001424449 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:3 mux_right_track_0\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_0_sram[1]:4 mem_right_track_0\/FTB_1__32:A 0.152 +3 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.001575893 +4 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size2_0_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_0_sram[1]:6 mux_tree_tapbuf_size2_0_sram[1]:5 0.002348214 +7 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.001707589 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.003338655 //LENGTH 28.235 LUMPCC 0.0002365365 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 58.265 25.840 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 51.620 19.720 +*I mem_bottom_track_1\/FTB_5__36:A I *L 0.001746 *C 49.680 31.280 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 49.718 31.280 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 50.095 31.280 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 50.140 31.235 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 50.140 19.765 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 50.185 19.720 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 51.620 19.742 +*N mux_tree_tapbuf_size2_4_sram[1]:9 *C 51.640 20.400 +*N mux_tree_tapbuf_size2_4_sram[1]:10 *C 51.695 20.400 +*N mux_tree_tapbuf_size2_4_sram[1]:11 *C 57.455 20.400 +*N mux_tree_tapbuf_size2_4_sram[1]:12 *C 57.500 20.445 +*N mux_tree_tapbuf_size2_4_sram[1]:13 *C 57.500 25.795 +*N mux_tree_tapbuf_size2_4_sram[1]:14 *C 57.545 25.840 +*N mux_tree_tapbuf_size2_4_sram[1]:15 *C 58.228 25.840 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_1\/FTB_5__36:A 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 4.13715e-05 +4 mux_tree_tapbuf_size2_4_sram[1]:4 4.13715e-05 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.000657664 +6 mux_tree_tapbuf_size2_4_sram[1]:6 0.000657664 +7 mux_tree_tapbuf_size2_4_sram[1]:7 0.0001323957 +8 mux_tree_tapbuf_size2_4_sram[1]:8 0.000182756 +9 mux_tree_tapbuf_size2_4_sram[1]:9 6.12014e-05 +10 mux_tree_tapbuf_size2_4_sram[1]:10 0.0002850061 +11 mux_tree_tapbuf_size2_4_sram[1]:11 0.0002741651 +12 mux_tree_tapbuf_size2_4_sram[1]:12 0.0002911694 +13 mux_tree_tapbuf_size2_4_sram[1]:13 0.0002911694 +14 mux_tree_tapbuf_size2_4_sram[1]:14 9.159202e-05 +15 mux_tree_tapbuf_size2_4_sram[1]:15 9.159202e-05 +16 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.179876e-07 +17 mux_tree_tapbuf_size2_4_sram[1]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.585332e-05 +18 mux_tree_tapbuf_size2_4_sram[1]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.06914e-05 +19 mux_tree_tapbuf_size2_4_sram[1]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.100554e-05 +20 mux_tree_tapbuf_size2_4_sram[1]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.585332e-05 +21 mux_tree_tapbuf_size2_4_sram[1]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.179876e-07 +22 mux_tree_tapbuf_size2_4_sram[1]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.100554e-05 +23 mux_tree_tapbuf_size2_4_sram[1]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.06914e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.00128125 +3 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size2_4_sram[1]:6 mux_tree_tapbuf_size2_4_sram[1]:5 0.01024107 +5 mux_tree_tapbuf_size2_4_sram[1]:4 mux_tree_tapbuf_size2_4_sram[1]:3 0.0003370536 +6 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size2_4_sram[1]:3 mem_bottom_track_1\/FTB_5__36:A 0.152 +8 mux_tree_tapbuf_size2_4_sram[1]:15 mux_tree_tapbuf_size2_4_sram[1]:14 0.000609375 +9 mux_tree_tapbuf_size2_4_sram[1]:14 mux_tree_tapbuf_size2_4_sram[1]:13 0.0045 +10 mux_tree_tapbuf_size2_4_sram[1]:13 mux_tree_tapbuf_size2_4_sram[1]:12 0.004776786 +11 mux_tree_tapbuf_size2_4_sram[1]:11 mux_tree_tapbuf_size2_4_sram[1]:10 0.005142857 +12 mux_tree_tapbuf_size2_4_sram[1]:12 mux_tree_tapbuf_size2_4_sram[1]:11 0.0045 +13 mux_tree_tapbuf_size2_4_sram[1]:9 mux_tree_tapbuf_size2_4_sram[1]:8 0.0005870537 +14 mux_tree_tapbuf_size2_4_sram[1]:10 mux_tree_tapbuf_size2_4_sram[1]:9 4.910714e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.001437795 //LENGTH 11.220 LUMPCC 0.0002865714 DR + +*CONN +*I mem_right_track_24\/FTB_4__35:X O *L 0 *C 77.505 36.380 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 70.095 33.660 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 70.095 33.660 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 69.920 33.660 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 69.920 33.705 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 69.920 36.335 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 69.965 36.380 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 77.468 36.380 + +*CAP +0 mem_right_track_24\/FTB_4__35:X 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 5.361986e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 5.442664e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0001112819 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0001112819 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.0004093064 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.0004093064 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 chanx_right_in[11]:3 8.013703e-05 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 chanx_right_in[11]:4 8.013703e-05 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_3_sram[1]:5 6.314868e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_3_sram[1]:4 6.314868e-05 + +*RES +0 mem_right_track_24\/FTB_4__35:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.006698661 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005164468 //LENGTH 3.325 LUMPCC 0.0002505752 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 90.905 36.380 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 93.940 36.380 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 93.903 36.380 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 90.943 36.380 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001319358 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001319358 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_3_sram[1]:3 0.0001252876 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_3_sram[1]:4 0.0001252876 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002642857 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00102253 //LENGTH 6.675 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 49.395 14.280 +*I mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 45.765 12.070 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 45.803 11.963 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 49.175 11.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 49.220 11.945 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 49.220 14.235 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 49.220 14.280 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 49.395 14.280 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002999853 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002999853 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001493804 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001493804 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.245475e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.934436e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003011161 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.510869e-05 + +*END + +*D_NET chany_bottom_out[7] 0.0009380062 //LENGTH 6.715 LUMPCC 0.0003064641 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 69.000 7.140 +*P chany_bottom_out[7] O *L 0.7423 *C 68.540 1.325 +*N chany_bottom_out[7]:2 *C 68.540 2.040 +*N chany_bottom_out[7]:3 *C 69.000 2.040 +*N chany_bottom_out[7]:4 *C 69.000 7.095 +*N chany_bottom_out[7]:5 *C 69.000 7.140 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chany_bottom_out[7] 4.986964e-05 +2 chany_bottom_out[7]:2 7.22745e-05 +3 chany_bottom_out[7]:3 0.0002490498 +4 chany_bottom_out[7]:4 0.0002266449 +5 chany_bottom_out[7]:5 3.270323e-05 +6 chany_bottom_out[7]:4 ropt_net_146:5 5.757513e-05 +7 chany_bottom_out[7]:3 ropt_net_146:4 5.757513e-05 +8 chany_bottom_out[7]:4 ropt_net_122:5 8.821252e-05 +9 chany_bottom_out[7]:2 ropt_net_122:2 7.444386e-06 +10 chany_bottom_out[7]:3 ropt_net_122:3 7.444386e-06 +11 chany_bottom_out[7]:3 ropt_net_122:4 8.821252e-05 + +*RES +0 ropt_mt_inst_761:X chany_bottom_out[7]:5 0.152 +1 chany_bottom_out[7]:5 chany_bottom_out[7]:4 0.0045 +2 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.004513393 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.0006383929 +4 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0004107143 + +*END + +*D_NET chanx_right_out[7] 0.0009260164 //LENGTH 7.480 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 110.135 98.600 +*P chanx_right_out[7] O *L 0.7423 *C 111.863 93.840 +*N chanx_right_out[7]:2 *C 111.780 93.840 +*N chanx_right_out[7]:3 *C 111.780 93.840 +*N chanx_right_out[7]:4 *C 111.320 93.840 +*N chanx_right_out[7]:5 *C 111.320 98.555 +*N chanx_right_out[7]:6 *C 111.275 98.600 +*N chanx_right_out[7]:7 *C 110.172 98.600 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 chanx_right_out[7] 2.943837e-05 +2 chanx_right_out[7]:2 2.943837e-05 +3 chanx_right_out[7]:3 6.82142e-05 +4 chanx_right_out[7]:4 0.0003280828 +5 chanx_right_out[7]:5 0.0002947135 +6 chanx_right_out[7]:6 8.756459e-05 +7 chanx_right_out[7]:7 8.756459e-05 + +*RES +0 ropt_mt_inst_765:X chanx_right_out[7]:7 0.152 +1 chanx_right_out[7]:7 chanx_right_out[7]:6 0.000984375 +2 chanx_right_out[7]:6 chanx_right_out[7]:5 0.0045 +3 chanx_right_out[7]:5 chanx_right_out[7]:4 0.004209822 +4 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +5 chanx_right_out[7]:2 chanx_right_out[7] 2.35e-05 +6 chanx_right_out[7]:4 chanx_right_out[7]:3 0.0004107143 + +*END + +*D_NET ropt_net_145 0.0005485233 //LENGTH 3.760 LUMPCC 0.0002317557 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 69.175 4.760 +*I ropt_mt_inst_761:A I *L 0.001767 *C 68.080 6.800 +*N ropt_net_145:2 *C 68.080 6.800 +*N ropt_net_145:3 *C 68.080 6.755 +*N ropt_net_145:4 *C 68.080 4.805 +*N ropt_net_145:5 *C 68.125 4.760 +*N ropt_net_145:6 *C 69.138 4.760 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_145:2 3.679109e-05 +3 ropt_net_145:3 5.55705e-05 +4 ropt_net_145:4 5.55705e-05 +5 ropt_net_145:5 8.341776e-05 +6 ropt_net_145:6 8.341776e-05 +7 ropt_net_145:4 chany_bottom_out[12] 4.552572e-05 +8 ropt_net_145:3 chany_bottom_out[12]:2 4.552572e-05 +9 ropt_net_145:6 ropt_net_122:3 8.980812e-06 +10 ropt_net_145:5 ropt_net_122:2 8.980812e-06 +11 ropt_net_145:4 ropt_net_122:4 6.13713e-05 +12 ropt_net_145:3 ropt_net_122:5 6.13713e-05 + +*RES +0 ropt_mt_inst_738:X ropt_net_145:6 0.152 +1 ropt_net_145:6 ropt_net_145:5 0.0009040179 +2 ropt_net_145:5 ropt_net_145:4 0.0045 +3 ropt_net_145:4 ropt_net_145:3 0.001741072 +4 ropt_net_145:2 ropt_mt_inst_761:A 0.152 +5 ropt_net_145:3 ropt_net_145:2 0.0045 + +*END + +*D_NET ropt_net_160 0.0005433689 //LENGTH 4.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 102.580 83.640 +*I ropt_mt_inst_776:A I *L 0.001766 *C 106.260 82.960 +*N ropt_net_160:2 *C 106.223 82.960 +*N ropt_net_160:3 *C 102.580 82.960 +*N ropt_net_160:4 *C 102.580 83.640 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 ropt_mt_inst_776:A 1e-06 +2 ropt_net_160:2 0.0002103417 +3 ropt_net_160:3 0.0002562261 +4 ropt_net_160:4 7.480112e-05 + +*RES +0 ropt_mt_inst_746:X ropt_net_160:4 0.152 +1 ropt_net_160:4 ropt_net_160:3 0.0006071429 +2 ropt_net_160:2 ropt_mt_inst_776:A 0.152 +3 ropt_net_160:3 ropt_net_160:2 0.003252232 + +*END + +*D_NET ropt_net_169 0.0006014346 //LENGTH 4.590 LUMPCC 0.0002647082 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 102.580 66.980 +*I ropt_mt_inst_785:A I *L 0.001766 *C 106.260 66.640 +*N ropt_net_169:2 *C 106.223 66.640 +*N ropt_net_169:3 *C 104.420 66.640 +*N ropt_net_169:4 *C 104.420 66.980 +*N ropt_net_169:5 *C 102.618 66.980 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_169:2 0.0001097379 +3 ropt_net_169:3 0.0001329952 +4 ropt_net_169:4 5.762532e-05 +5 ropt_net_169:5 3.436799e-05 +6 ropt_net_169:5 chany_bottom_in[5]:2 4.638626e-05 +7 ropt_net_169:4 chany_bottom_in[5]:3 4.638626e-05 +8 ropt_net_169:2 ropt_net_137:6 8.365473e-06 +9 ropt_net_169:5 ropt_net_137:7 7.76024e-05 +10 ropt_net_169:4 ropt_net_137:6 7.76024e-05 +11 ropt_net_169:3 ropt_net_137:7 8.365473e-06 + +*RES +0 ropt_mt_inst_750:X ropt_net_169:5 0.152 +1 ropt_net_169:2 ropt_mt_inst_785:A 0.152 +2 ropt_net_169:5 ropt_net_169:4 0.001609375 +3 ropt_net_169:4 ropt_net_169:3 0.0003035715 +4 ropt_net_169:3 ropt_net_169:2 0.001609375 + +*END + +*D_NET BUF_net_48 0.001104715 //LENGTH 8.830 LUMPCC 0.0001923573 DR + +*CONN +*I BUFT_RR_48:X O *L 0 *C 60.260 9.860 +*I BUFT_RR_80:A I *L 0.001766 *C 54.740 12.240 +*N BUF_net_48:2 *C 54.778 12.240 +*N BUF_net_48:3 *C 57.915 12.240 +*N BUF_net_48:4 *C 57.960 12.195 +*N BUF_net_48:5 *C 57.960 9.905 +*N BUF_net_48:6 *C 58.005 9.860 +*N BUF_net_48:7 *C 60.223 9.860 + +*CAP +0 BUFT_RR_48:X 1e-06 +1 BUFT_RR_80:A 1e-06 +2 BUF_net_48:2 0.0001559478 +3 BUF_net_48:3 0.0001559478 +4 BUF_net_48:4 0.0001415938 +5 BUF_net_48:5 0.0001415938 +6 BUF_net_48:6 0.0001576371 +7 BUF_net_48:7 0.0001576371 +8 BUF_net_48:3 chanx_right_in[8]:4 9.617864e-05 +9 BUF_net_48:2 chanx_right_in[8]:3 9.617864e-05 + +*RES +0 BUFT_RR_48:X BUF_net_48:7 0.152 +1 BUF_net_48:7 BUF_net_48:6 0.001979911 +2 BUF_net_48:6 BUF_net_48:5 0.0045 +3 BUF_net_48:5 BUF_net_48:4 0.002044643 +4 BUF_net_48:3 BUF_net_48:2 0.002801339 +5 BUF_net_48:4 BUF_net_48:3 0.0045 +6 BUF_net_48:2 BUFT_RR_80:A 0.152 + +*END + +*D_NET chany_bottom_out[19] 0.001045047 //LENGTH 6.635 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 29.135 3.740 +*P chany_bottom_out[19] O *L 0.7423 *C 25.760 1.285 +*N chany_bottom_out[19]:2 *C 25.760 3.393 +*N chany_bottom_out[19]:3 *C 25.780 3.400 +*N chany_bottom_out[19]:4 *C 27.593 3.400 +*N chany_bottom_out[19]:5 *C 27.600 3.400 +*N chany_bottom_out[19]:6 *C 27.600 3.740 +*N chany_bottom_out[19]:7 *C 27.645 3.740 +*N chany_bottom_out[19]:8 *C 29.098 3.740 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 chany_bottom_out[19] 0.0001572316 +2 chany_bottom_out[19]:2 0.0001572316 +3 chany_bottom_out[19]:3 0.0001915112 +4 chany_bottom_out[19]:4 0.0001915112 +5 chany_bottom_out[19]:5 5.484701e-05 +6 chany_bottom_out[19]:6 5.109103e-05 +7 chany_bottom_out[19]:7 0.0001203118 +8 chany_bottom_out[19]:8 0.0001203118 + +*RES +0 ropt_mt_inst_771:X chany_bottom_out[19]:8 0.152 +1 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.00341 +2 chany_bottom_out[19]:2 chany_bottom_out[19] 0.000330175 +3 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.00341 +4 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.0002839583 +5 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.0045 +6 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.0001634615 +7 chany_bottom_out[19]:8 chany_bottom_out[19]:7 0.001296875 + +*END + +*D_NET ropt_net_135 0.001690435 //LENGTH 13.390 LUMPCC 0.0002652677 DR + +*CONN +*I BUFT_RR_61:X O *L 0 *C 100.740 88.740 +*I ropt_mt_inst_751:A I *L 0.001766 *C 106.260 93.840 +*N ropt_net_135:2 *C 106.297 93.840 +*N ropt_net_135:3 *C 107.135 93.840 +*N ropt_net_135:4 *C 107.180 93.795 +*N ropt_net_135:5 *C 107.180 88.785 +*N ropt_net_135:6 *C 107.135 88.740 +*N ropt_net_135:7 *C 100.778 88.740 + +*CAP +0 BUFT_RR_61:X 1e-06 +1 ropt_mt_inst_751:A 1e-06 +2 ropt_net_135:2 7.371732e-05 +3 ropt_net_135:3 7.371732e-05 +4 ropt_net_135:4 0.0002861566 +5 ropt_net_135:5 0.0002861566 +6 ropt_net_135:6 0.0003517099 +7 ropt_net_135:7 0.0003517099 +8 ropt_net_135:4 ropt_net_164:4 1.869703e-06 +9 ropt_net_135:6 ropt_net_164:6 6.870177e-05 +10 ropt_net_135:5 ropt_net_164:5 1.869703e-06 +11 ropt_net_135:7 ropt_net_164:7 6.870177e-05 +12 ropt_net_135:6 ropt_net_156:2 6.206238e-05 +13 ropt_net_135:7 ropt_net_156:3 6.206238e-05 + +*RES +0 BUFT_RR_61:X ropt_net_135:7 0.152 +1 ropt_net_135:2 ropt_mt_inst_751:A 0.152 +2 ropt_net_135:3 ropt_net_135:2 0.0007477679 +3 ropt_net_135:4 ropt_net_135:3 0.0045 +4 ropt_net_135:6 ropt_net_135:5 0.0045 +5 ropt_net_135:5 ropt_net_135:4 0.004473214 +6 ropt_net_135:7 ropt_net_135:6 0.005676339 + +*END + +*D_NET ropt_net_138 0.00148698 //LENGTH 11.870 LUMPCC 0.0001216519 DR + +*CONN +*I BUFT_RR_69:X O *L 0 *C 100.740 94.180 +*I ropt_mt_inst_754:A I *L 0.001766 *C 106.260 96.560 +*N ropt_net_138:2 *C 106.223 96.560 +*N ropt_net_138:3 *C 105.845 96.560 +*N ropt_net_138:4 *C 105.800 96.515 +*N ropt_net_138:5 *C 105.800 94.565 +*N ropt_net_138:6 *C 105.755 94.520 +*N ropt_net_138:7 *C 99.360 94.520 +*N ropt_net_138:8 *C 99.360 94.180 +*N ropt_net_138:9 *C 100.703 94.180 + +*CAP +0 BUFT_RR_69:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_138:2 5.54732e-05 +3 ropt_net_138:3 5.54732e-05 +4 ropt_net_138:4 8.794014e-05 +5 ropt_net_138:5 8.794014e-05 +6 ropt_net_138:6 0.0004533628 +7 ropt_net_138:7 0.0004761548 +8 ropt_net_138:8 8.488812e-05 +9 ropt_net_138:9 6.209618e-05 +10 ropt_net_138:5 ropt_net_149:4 6.082595e-05 +11 ropt_net_138:4 ropt_net_149:3 6.082595e-05 + +*RES +0 BUFT_RR_69:X ropt_net_138:9 0.152 +1 ropt_net_138:9 ropt_net_138:8 0.001198661 +2 ropt_net_138:6 ropt_net_138:5 0.0045 +3 ropt_net_138:5 ropt_net_138:4 0.001741072 +4 ropt_net_138:3 ropt_net_138:2 0.0003370536 +5 ropt_net_138:4 ropt_net_138:3 0.0045 +6 ropt_net_138:2 ropt_mt_inst_754:A 0.152 +7 ropt_net_138:8 ropt_net_138:7 0.0003035715 +8 ropt_net_138:7 ropt_net_138:6 0.005709821 + +*END + +*D_NET chanx_right_out[16] 0.000578841 //LENGTH 4.370 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 110.135 61.880 +*P chanx_right_out[16] O *L 0.7423 *C 111.930 63.920 +*N chanx_right_out[16]:2 *C 110.407 63.920 +*N chanx_right_out[16]:3 *C 110.400 63.863 +*N chanx_right_out[16]:4 *C 110.400 61.925 +*N chanx_right_out[16]:5 *C 110.400 61.880 +*N chanx_right_out[16]:6 *C 110.135 61.880 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 chanx_right_out[16] 0.0001203248 +2 chanx_right_out[16]:2 0.0001203248 +3 chanx_right_out[16]:3 0.000111954 +4 chanx_right_out[16]:4 0.000111954 +5 chanx_right_out[16]:5 5.330603e-05 +6 chanx_right_out[16]:6 5.997724e-05 + +*RES +0 ropt_mt_inst_784:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:6 chanx_right_out[16]:5 0.0001440218 +2 chanx_right_out[16]:5 chanx_right_out[16]:4 0.0045 +3 chanx_right_out[16]:4 chanx_right_out[16]:3 0.001729911 +4 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +5 chanx_right_out[16]:2 chanx_right_out[16] 0.000238525 + +*END + +*D_NET ropt_net_148 0.0009778972 //LENGTH 6.475 LUMPCC 0.0004183293 DR + +*CONN +*I BUFT_RR_80:X O *L 0 *C 50.865 11.900 +*I ropt_mt_inst_764:A I *L 0.001767 *C 51.060 6.800 +*N ropt_net_148:2 *C 51.023 6.800 +*N ropt_net_148:3 *C 50.645 6.800 +*N ropt_net_148:4 *C 50.600 6.845 +*N ropt_net_148:5 *C 50.600 11.855 +*N ropt_net_148:6 *C 50.600 11.900 +*N ropt_net_148:7 *C 50.865 11.900 + +*CAP +0 BUFT_RR_80:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_148:2 5.744382e-05 +3 ropt_net_148:3 5.744382e-05 +4 ropt_net_148:4 0.000162621 +5 ropt_net_148:5 0.000162621 +6 ropt_net_148:6 5.853736e-05 +7 ropt_net_148:7 5.890088e-05 +8 ropt_net_148:4 chany_bottom_out[0] 0.0001399981 +9 ropt_net_148:5 chany_bottom_out[0]:2 0.0001399981 +10 ropt_net_148:4 chany_bottom_out[4] 6.916658e-05 +11 ropt_net_148:5 chany_bottom_out[4]:2 6.916658e-05 + +*RES +0 BUFT_RR_80:X ropt_net_148:7 0.152 +1 ropt_net_148:2 ropt_mt_inst_764:A 0.152 +2 ropt_net_148:3 ropt_net_148:2 0.0003370536 +3 ropt_net_148:4 ropt_net_148:3 0.0045 +4 ropt_net_148:6 ropt_net_148:5 0.0045 +5 ropt_net_148:5 ropt_net_148:4 0.004473215 +6 ropt_net_148:7 ropt_net_148:6 0.0001440218 + +*END + +*D_NET ropt_net_129 0.002242452 //LENGTH 19.480 LUMPCC 0.0005286671 DR + +*CONN +*I BUFT_P_95:X O *L 0 *C 43.700 19.720 +*I ropt_mt_inst_745:A I *L 0.001766 *C 41.860 6.800 +*N ropt_net_129:2 *C 41.898 6.800 +*N ropt_net_129:3 *C 45.035 6.800 +*N ropt_net_129:4 *C 45.080 6.800 +*N ropt_net_129:5 *C 45.540 6.800 +*N ropt_net_129:6 *C 45.540 19.675 +*N ropt_net_129:7 *C 45.495 19.720 +*N ropt_net_129:8 *C 43.738 19.720 + +*CAP +0 BUFT_P_95:X 1e-06 +1 ropt_mt_inst_745:A 1e-06 +2 ropt_net_129:2 0.0002107812 +3 ropt_net_129:3 0.0002107812 +4 ropt_net_129:4 6.758281e-05 +5 ropt_net_129:5 0.0004937944 +6 ropt_net_129:6 0.0004591432 +7 ropt_net_129:7 0.0001348514 +8 ropt_net_129:8 0.0001348514 +9 ropt_net_129:6 chany_bottom_in[15]:18 0.0001417005 +10 ropt_net_129:5 chany_bottom_in[15] 0.0001417005 +11 ropt_net_129:6 chany_bottom_in[14]:8 6.181014e-05 +12 ropt_net_129:5 chany_bottom_in[14] 6.181014e-05 +13 ropt_net_129:6 ropt_net_157:3 6.082285e-05 +14 ropt_net_129:5 ropt_net_157:4 6.082285e-05 + +*RES +0 BUFT_P_95:X ropt_net_129:8 0.152 +1 ropt_net_129:8 ropt_net_129:7 0.001569197 +2 ropt_net_129:7 ropt_net_129:6 0.0045 +3 ropt_net_129:6 ropt_net_129:5 0.01149554 +4 ropt_net_129:3 ropt_net_129:2 0.00280134 +5 ropt_net_129:4 ropt_net_129:3 0.0045 +6 ropt_net_129:2 ropt_mt_inst_745:A 0.152 +7 ropt_net_129:5 ropt_net_129:4 0.0004107143 + +*END + +*D_NET chanx_right_in[1] 0.01508606 //LENGTH 112.220 LUMPCC 0.006299715 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 111.855 57.120 +*I ropt_mt_inst_736:A I *L 0.001767 *C 55.660 6.800 +*N chanx_right_in[1]:2 *C 55.660 6.800 +*N chanx_right_in[1]:3 *C 55.660 6.845 +*N chanx_right_in[1]:4 *C 55.660 9.520 +*N chanx_right_in[1]:5 *C 55.200 9.520 +*N chanx_right_in[1]:6 *C 55.200 41.435 +*N chanx_right_in[1]:7 *C 55.155 41.480 +*N chanx_right_in[1]:8 *C 54.650 41.480 +*N chanx_right_in[1]:9 *C 54.650 42.160 +*N chanx_right_in[1]:10 *C 61.595 42.160 +*N chanx_right_in[1]:11 *C 61.640 42.205 +*N chanx_right_in[1]:12 *C 61.640 57.742 +*N chanx_right_in[1]:13 *C 61.648 57.800 +*N chanx_right_in[1]:14 *C 107.640 57.800 +*N chanx_right_in[1]:15 *C 107.640 57.120 + +*CAP +0 chanx_right_in[1] 6.931122e-05 +1 ropt_mt_inst_736:A 1e-06 +2 chanx_right_in[1]:2 3.296037e-05 +3 chanx_right_in[1]:3 0.0001242678 +4 chanx_right_in[1]:4 0.0001538655 +5 chanx_right_in[1]:5 0.001567138 +6 chanx_right_in[1]:6 0.001537541 +7 chanx_right_in[1]:7 3.53821e-05 +8 chanx_right_in[1]:8 7.789982e-05 +9 chanx_right_in[1]:9 0.0004494855 +10 chanx_right_in[1]:10 0.0004069678 +11 chanx_right_in[1]:11 0.0007601699 +12 chanx_right_in[1]:12 0.0007601699 +13 chanx_right_in[1]:13 0.001326872 +14 chanx_right_in[1]:14 0.001370439 +15 chanx_right_in[1]:15 0.0001128776 +16 chanx_right_in[1] chanx_right_in[11] 0.0001110052 +17 chanx_right_in[1]:13 chanx_right_in[11]:5 0.002121772 +18 chanx_right_in[1]:14 chanx_right_in[11] 0.002121772 +19 chanx_right_in[1]:15 chanx_right_in[11]:5 0.0001110052 +20 chanx_right_in[1] chanx_right_in[15] 0.0001195435 +21 chanx_right_in[1]:6 chanx_right_in[15]:9 4.627724e-05 +22 chanx_right_in[1]:6 chanx_right_in[15]:15 2.931324e-05 +23 chanx_right_in[1]:13 chanx_right_in[15]:16 0.0006461455 +24 chanx_right_in[1]:13 chanx_right_in[15]:17 1.55327e-05 +25 chanx_right_in[1]:5 chanx_right_in[15]:8 4.627724e-05 +26 chanx_right_in[1]:5 chanx_right_in[15]:14 2.931324e-05 +27 chanx_right_in[1]:14 chanx_right_in[15] 1.55327e-05 +28 chanx_right_in[1]:14 chanx_right_in[15]:17 0.0006461455 +29 chanx_right_in[1]:15 chanx_right_in[15]:17 0.0001195435 +30 chanx_right_in[1]:3 mem_bottom_track_25/net_net_74:4 6.026765e-05 +31 chanx_right_in[1]:4 mem_bottom_track_25/net_net_74:5 6.026765e-05 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:15 0.00066035 +1 chanx_right_in[1]:2 ropt_mt_inst_736:A 0.152 +2 chanx_right_in[1]:3 chanx_right_in[1]:2 0.0045 +3 chanx_right_in[1]:7 chanx_right_in[1]:6 0.0045 +4 chanx_right_in[1]:6 chanx_right_in[1]:5 0.02849554 +5 chanx_right_in[1]:10 chanx_right_in[1]:9 0.006200893 +6 chanx_right_in[1]:11 chanx_right_in[1]:10 0.0045 +7 chanx_right_in[1]:12 chanx_right_in[1]:11 0.01387277 +8 chanx_right_in[1]:13 chanx_right_in[1]:12 0.00341 +9 chanx_right_in[1]:8 chanx_right_in[1]:7 0.0004508929 +10 chanx_right_in[1]:9 chanx_right_in[1]:8 0.0006071429 +11 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0004107143 +12 chanx_right_in[1]:4 chanx_right_in[1]:3 0.002388393 +13 chanx_right_in[1]:14 chanx_right_in[1]:13 0.007205491 +14 chanx_right_in[1]:15 chanx_right_in[1]:14 0.0001065333 + +*END + +*D_NET chany_bottom_in[0] 0.01325601 //LENGTH 129.365 LUMPCC 0.0008454958 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 65.780 1.325 +*I ropt_mt_inst_749:A I *L 0.001767 *C 101.660 91.120 +*N chany_bottom_in[0]:2 *C 101.660 91.120 +*N chany_bottom_in[0]:3 *C 101.660 91.075 +*N chany_bottom_in[0]:4 *C 101.660 90.440 +*N chany_bottom_in[0]:5 *C 102.580 90.440 +*N chany_bottom_in[0]:6 *C 102.580 69.418 +*N chany_bottom_in[0]:7 *C 102.573 69.360 +*N chany_bottom_in[0]:8 *C 68.100 69.360 +*N chany_bottom_in[0]:9 *C 68.080 69.353 +*N chany_bottom_in[0]:10 *C 68.080 51.875 +*N chany_bottom_in[0]:11 *C 68.080 2.048 +*N chany_bottom_in[0]:12 *C 68.060 2.040 +*N chany_bottom_in[0]:13 *C 65.788 2.040 +*N chany_bottom_in[0]:14 *C 65.780 1.983 + +*CAP +0 chany_bottom_in[0] 5.376134e-05 +1 ropt_mt_inst_749:A 1e-06 +2 chany_bottom_in[0]:2 3.654e-05 +3 chany_bottom_in[0]:3 4.257032e-05 +4 chany_bottom_in[0]:4 9.012556e-05 +5 chany_bottom_in[0]:5 0.00113737 +6 chany_bottom_in[0]:6 0.001089814 +7 chany_bottom_in[0]:7 0.001366701 +8 chany_bottom_in[0]:8 0.001366701 +9 chany_bottom_in[0]:9 0.0008921116 +10 chany_bottom_in[0]:10 0.003414822 +11 chany_bottom_in[0]:11 0.00252271 +12 chany_bottom_in[0]:12 0.0001712626 +13 chany_bottom_in[0]:13 0.0001712626 +14 chany_bottom_in[0]:14 5.376134e-05 +15 chany_bottom_in[0]:7 chanx_right_in[19] 0.0002607428 +16 chany_bottom_in[0]:7 chanx_right_in[19]:14 0.0001620051 +17 chany_bottom_in[0]:8 chanx_right_in[19]:13 0.0001620051 +18 chany_bottom_in[0]:8 chanx_right_in[19]:14 0.0002607428 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:14 0.0005870535 +1 chany_bottom_in[0]:2 ropt_mt_inst_749:A 0.152 +2 chany_bottom_in[0]:3 chany_bottom_in[0]:2 0.0045 +3 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.01877009 +4 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.00341 +5 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.005400691 +6 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.00341 +7 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.00341 +8 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.007806308 +9 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.00341 +10 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.000356025 +11 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.0005669643 +12 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.0008214285 +13 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.002738141 + +*END + +*D_NET chany_bottom_in[2] 0.01150538 //LENGTH 103.155 LUMPCC 0.003316371 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 71.300 1.325 +*I ropt_mt_inst_747:A I *L 0.001767 *C 106.260 63.920 +*N chany_bottom_in[2]:2 *C 75.650 8.840 +*N chany_bottom_in[2]:3 *C 106.260 63.920 +*N chany_bottom_in[2]:4 *C 102.165 63.920 +*N chany_bottom_in[2]:5 *C 102.120 63.875 +*N chany_bottom_in[2]:6 *C 102.120 55.760 +*N chany_bottom_in[2]:7 *C 102.120 56.440 +*N chany_bottom_in[2]:8 *C 102.113 56.440 +*N chany_bottom_in[2]:9 *C 101.208 56.440 +*N chany_bottom_in[2]:10 *C 101.200 56.383 +*N chany_bottom_in[2]:11 *C 101.200 29.298 +*N chany_bottom_in[2]:12 *C 101.193 29.240 +*N chany_bottom_in[2]:13 *C 76.380 29.240 +*N chany_bottom_in[2]:14 *C 76.360 29.233 +*N chany_bottom_in[2]:15 *C 76.360 8.848 +*N chany_bottom_in[2]:16 *C 76.358 8.840 +*N chany_bottom_in[2]:17 *C 76.360 8.783 +*N chany_bottom_in[2]:18 *C 76.360 2.085 +*N chany_bottom_in[2]:19 *C 76.315 2.040 +*N chany_bottom_in[2]:20 *C 71.345 2.040 +*N chany_bottom_in[2]:21 *C 71.300 1.995 + +*CAP +0 chany_bottom_in[2] 5.564892e-05 +1 ropt_mt_inst_747:A 1e-06 +2 chany_bottom_in[2]:2 7.560107e-05 +3 chany_bottom_in[2]:3 0.0003182972 +4 chany_bottom_in[2]:4 0.0002924501 +5 chany_bottom_in[2]:5 0.0003866708 +6 chany_bottom_in[2]:6 4.358418e-05 +7 chany_bottom_in[2]:7 0.0004633615 +8 chany_bottom_in[2]:8 0.000122719 +9 chany_bottom_in[2]:9 0.000122719 +10 chany_bottom_in[2]:10 0.00118799 +11 chany_bottom_in[2]:11 0.00118799 +12 chany_bottom_in[2]:12 0.0005867775 +13 chany_bottom_in[2]:13 0.0005867775 +14 chany_bottom_in[2]:14 0.000664953 +15 chany_bottom_in[2]:15 0.000664953 +16 chany_bottom_in[2]:16 7.560107e-05 +17 chany_bottom_in[2]:17 0.0003237986 +18 chany_bottom_in[2]:18 0.0003237986 +19 chany_bottom_in[2]:19 0.0003243364 +20 chany_bottom_in[2]:20 0.0003243364 +21 chany_bottom_in[2]:21 5.564892e-05 +22 chany_bottom_in[2]:10 chany_bottom_in[9]:4 7.324083e-06 +23 chany_bottom_in[2]:10 chany_bottom_in[9]:8 5.602714e-05 +24 chany_bottom_in[2]:11 chany_bottom_in[9]:5 7.324083e-06 +25 chany_bottom_in[2]:11 chany_bottom_in[9]:9 5.602714e-05 +26 chany_bottom_in[2]:14 chany_bottom_in[9]:12 0.0003313184 +27 chany_bottom_in[2]:16 chany_bottom_in[9]:15 1.234654e-05 +28 chany_bottom_in[2]:15 chany_bottom_in[9]:13 0.0003313184 +29 chany_bottom_in[2]:2 chany_bottom_in[9]:14 1.234654e-05 +30 chany_bottom_in[2]:10 chany_bottom_in[19]:10 8.569015e-05 +31 chany_bottom_in[2]:10 chany_bottom_in[19]:13 1.663373e-05 +32 chany_bottom_in[2]:11 chany_bottom_in[19]:11 8.569015e-05 +33 chany_bottom_in[2]:11 chany_bottom_in[19]:14 1.663373e-05 +34 chany_bottom_in[2]:12 chany_bottom_in[19]:14 0.0004668763 +35 chany_bottom_in[2]:12 chany_bottom_in[19]:13 9.848437e-05 +36 chany_bottom_in[2]:12 chany_bottom_in[19]:15 0.0001453485 +37 chany_bottom_in[2]:13 chany_bottom_in[19]:12 9.848437e-05 +38 chany_bottom_in[2]:13 chany_bottom_in[19]:16 0.0001453485 +39 chany_bottom_in[2]:13 chany_bottom_in[19]:15 0.0004668763 +40 chany_bottom_in[2]:12 chanx_right_in[6] 0.0003772762 +41 chany_bottom_in[2]:13 chanx_right_in[6]:7 0.0003772762 +42 chany_bottom_in[2]:14 chanx_right_in[6]:6 6.352981e-06 +43 chany_bottom_in[2]:15 chanx_right_in[6]:5 6.352981e-06 +44 chany_bottom_in[2]:17 ropt_net_144:6 5.450706e-05 +45 chany_bottom_in[2]:18 ropt_net_144:5 5.450706e-05 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:21 0.0005982143 +1 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.0006071429 +2 chany_bottom_in[2]:7 chany_bottom_in[2]:5 0.006638393 +3 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.00341 +4 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.00341 +5 chany_bottom_in[2]:9 chany_bottom_in[2]:8 0.0001417833 +6 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.02418304 +7 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.00341 +8 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.003887291 +9 chany_bottom_in[2]:14 chany_bottom_in[2]:13 0.00341 +10 chany_bottom_in[2]:16 chany_bottom_in[2]:15 0.00341 +11 chany_bottom_in[2]:16 chany_bottom_in[2]:2 0.0001039141 +12 chany_bottom_in[2]:15 chany_bottom_in[2]:14 0.00319365 +13 chany_bottom_in[2]:17 chany_bottom_in[2]:16 0.00341 +14 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.0045 +15 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.005979911 +16 chany_bottom_in[2]:20 chany_bottom_in[2]:19 0.0044375 +17 chany_bottom_in[2]:21 chany_bottom_in[2]:20 0.0045 +18 chany_bottom_in[2]:4 chany_bottom_in[2]:3 0.00365625 +19 chany_bottom_in[2]:5 chany_bottom_in[2]:4 0.0045 +20 chany_bottom_in[2]:3 ropt_mt_inst_747:A 0.152 + +*END + +*D_NET chany_bottom_in[7] 0.01326481 //LENGTH 142.980 LUMPCC 0.0001286755 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 22.080 1.290 +*I BUFT_RR_63:A I *L 0.001776 *C 98.440 66.640 +*N chany_bottom_in[7]:2 *C 98.440 66.640 +*N chany_bottom_in[7]:3 *C 71.920 66.640 +*N chany_bottom_in[7]:4 *C 22.125 66.640 +*N chany_bottom_in[7]:5 *C 22.080 66.595 +*N chany_bottom_in[7]:6 *C 22.080 51.290 + +*CAP +0 chany_bottom_in[7] 0.002122823 +1 BUFT_RR_63:A 1e-06 +2 chany_bottom_in[7]:2 0.001416561 +3 chany_bottom_in[7]:3 0.003792798 +4 chany_bottom_in[7]:4 0.002401614 +5 chany_bottom_in[7]:5 0.0006392584 +6 chany_bottom_in[7]:6 0.002762082 +7 chany_bottom_in[7] ropt_net_159:5 6.433776e-05 +8 chany_bottom_in[7]:6 ropt_net_159:4 6.433776e-05 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:6 0.04464286 +1 chany_bottom_in[7]:2 BUFT_RR_63:A 0.152 +2 chany_bottom_in[7]:4 chany_bottom_in[7]:3 0.04445983 +3 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.0045 +4 chany_bottom_in[7]:3 chany_bottom_in[7]:2 0.02367857 +5 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.01366518 + +*END + +*D_NET chany_bottom_in[9] 0.01563252 //LENGTH 131.810 LUMPCC 0.003546104 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 23.000 1.325 +*I ropt_mt_inst_741:A I *L 0.001767 *C 101.660 44.880 +*N chany_bottom_in[9]:2 *C 101.698 44.880 +*N chany_bottom_in[9]:3 *C 104.835 44.880 +*N chany_bottom_in[9]:4 *C 104.880 44.835 +*N chany_bottom_in[9]:5 *C 104.880 36.765 +*N chany_bottom_in[9]:6 *C 104.835 36.720 +*N chany_bottom_in[9]:7 *C 102.165 36.720 +*N chany_bottom_in[9]:8 *C 102.120 36.675 +*N chany_bottom_in[9]:9 *C 102.120 32.698 +*N chany_bottom_in[9]:10 *C 102.113 32.640 +*N chany_bottom_in[9]:11 *C 79.140 32.640 +*N chany_bottom_in[9]:12 *C 79.120 32.633 +*N chany_bottom_in[9]:13 *C 79.120 6.808 +*N chany_bottom_in[9]:14 *C 79.100 6.800 +*N chany_bottom_in[9]:15 *C 39.568 6.800 +*N chany_bottom_in[9]:16 *C 39.560 6.743 +*N chany_bottom_in[9]:17 *C 39.560 1.745 +*N chany_bottom_in[9]:18 *C 39.515 1.700 +*N chany_bottom_in[9]:19 *C 23.045 1.700 +*N chany_bottom_in[9]:20 *C 23.000 1.655 + +*CAP +0 chany_bottom_in[9] 3.542304e-05 +1 ropt_mt_inst_741:A 1e-06 +2 chany_bottom_in[9]:2 0.0001679217 +3 chany_bottom_in[9]:3 0.0001679217 +4 chany_bottom_in[9]:4 0.0003968466 +5 chany_bottom_in[9]:5 0.0003968466 +6 chany_bottom_in[9]:6 0.0002222341 +7 chany_bottom_in[9]:7 0.0002222341 +8 chany_bottom_in[9]:8 0.0001696549 +9 chany_bottom_in[9]:9 0.0001696549 +10 chany_bottom_in[9]:10 0.000455648 +11 chany_bottom_in[9]:11 0.000455648 +12 chany_bottom_in[9]:12 0.0009416915 +13 chany_bottom_in[9]:13 0.0009416915 +14 chany_bottom_in[9]:14 0.002390152 +15 chany_bottom_in[9]:15 0.002390152 +16 chany_bottom_in[9]:16 0.0002737351 +17 chany_bottom_in[9]:17 0.0002737351 +18 chany_bottom_in[9]:18 0.0009893995 +19 chany_bottom_in[9]:19 0.0009893995 +20 chany_bottom_in[9]:20 3.542304e-05 +21 chany_bottom_in[9]:10 chanx_right_in[4] 0.0001838404 +22 chany_bottom_in[9]:10 chanx_right_in[4]:10 0.0003952083 +23 chany_bottom_in[9]:11 chanx_right_in[4]:9 0.0003952083 +24 chany_bottom_in[9]:11 chanx_right_in[4]:10 0.0001838404 +25 chany_bottom_in[9]:4 chany_bottom_in[2]:10 7.324083e-06 +26 chany_bottom_in[9]:5 chany_bottom_in[2]:11 7.324083e-06 +27 chany_bottom_in[9]:8 chany_bottom_in[2]:10 5.602714e-05 +28 chany_bottom_in[9]:9 chany_bottom_in[2]:11 5.602714e-05 +29 chany_bottom_in[9]:12 chany_bottom_in[2]:14 0.0003313184 +30 chany_bottom_in[9]:14 chany_bottom_in[2]:2 1.234654e-05 +31 chany_bottom_in[9]:13 chany_bottom_in[2]:15 0.0003313184 +32 chany_bottom_in[9]:15 chany_bottom_in[2]:16 1.234654e-05 +33 chany_bottom_in[9]:10 chanx_right_in[6] 0.0005760266 +34 chany_bottom_in[9]:11 chanx_right_in[6]:7 0.0005760266 +35 chany_bottom_in[9]:14 ropt_net_157:6 0.0001672337 +36 chany_bottom_in[9]:15 ropt_net_157:5 0.0001672337 +37 chany_bottom_in[9]:2 ropt_net_167:7 2.166722e-05 +38 chany_bottom_in[9]:3 ropt_net_167:6 2.166722e-05 +39 chany_bottom_in[9]:4 ropt_net_167:5 2.205968e-05 +40 chany_bottom_in[9]:5 ropt_net_167:4 2.205968e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:20 0.0002946429 +1 chany_bottom_in[9]:2 ropt_mt_inst_741:A 0.152 +2 chany_bottom_in[9]:3 chany_bottom_in[9]:2 0.002801339 +3 chany_bottom_in[9]:4 chany_bottom_in[9]:3 0.0045 +4 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.0045 +5 chany_bottom_in[9]:5 chany_bottom_in[9]:4 0.007205357 +6 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.002383929 +7 chany_bottom_in[9]:8 chany_bottom_in[9]:7 0.0045 +8 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.003551339 +9 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.00341 +10 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.003599025 +11 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.00341 +12 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.00341 +13 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.004045916 +14 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.00341 +15 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.006193425 +16 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.0045 +17 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.004462054 +18 chany_bottom_in[9]:19 chany_bottom_in[9]:18 0.01470536 +19 chany_bottom_in[9]:20 chany_bottom_in[9]:19 0.0045 + +*END + +*D_NET chany_bottom_in[12] 0.0147821 //LENGTH 140.785 LUMPCC 0.0009442882 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 63.940 1.290 +*I ropt_mt_inst_748:A I *L 0.001767 *C 101.660 85.680 +*N chany_bottom_in[12]:2 *C 101.660 85.680 +*N chany_bottom_in[12]:3 *C 102.120 85.680 +*N chany_bottom_in[12]:4 *C 102.120 86.020 +*N chany_bottom_in[12]:5 *C 108.975 86.020 +*N chany_bottom_in[12]:6 *C 109.020 85.975 +*N chany_bottom_in[12]:7 *C 109.020 79.605 +*N chany_bottom_in[12]:8 *C 108.975 79.560 +*N chany_bottom_in[12]:9 *C 101.325 79.560 +*N chany_bottom_in[12]:10 *C 101.210 79.605 +*N chany_bottom_in[12]:11 *C 101.200 80.195 +*N chany_bottom_in[12]:12 *C 101.155 80.240 +*N chany_bottom_in[12]:13 *C 63.985 80.240 +*N chany_bottom_in[12]:14 *C 63.940 80.195 +*N chany_bottom_in[12]:15 *C 63.940 51.290 + +*CAP +0 chany_bottom_in[12] 0.002553579 +1 ropt_mt_inst_748:A 1e-06 +2 chany_bottom_in[12]:2 7.607893e-05 +3 chany_bottom_in[12]:3 6.409668e-05 +4 chany_bottom_in[12]:4 0.0004840968 +5 chany_bottom_in[12]:5 0.0004587734 +6 chany_bottom_in[12]:6 0.0002587082 +7 chany_bottom_in[12]:7 0.0002587082 +8 chany_bottom_in[12]:8 0.0004760713 +9 chany_bottom_in[12]:9 0.0004760713 +10 chany_bottom_in[12]:10 5.98091e-05 +11 chany_bottom_in[12]:11 5.98091e-05 +12 chany_bottom_in[12]:12 0.001688722 +13 chany_bottom_in[12]:13 0.001688722 +14 chany_bottom_in[12]:14 0.001339995 +15 chany_bottom_in[12]:15 0.003893574 +16 chany_bottom_in[12]:8 chanx_right_out[4]:7 1.303242e-05 +17 chany_bottom_in[12]:8 chanx_right_out[4]:3 6.256396e-06 +18 chany_bottom_in[12]:9 chanx_right_out[4]:8 1.303242e-05 +19 chany_bottom_in[12]:9 chanx_right_out[4]:4 6.256396e-06 +20 chany_bottom_in[12]:12 chanx_right_out[4]:7 0.0003644829 +21 chany_bottom_in[12]:13 chanx_right_out[4]:8 0.0003644829 +22 chany_bottom_in[12]:6 ropt_net_149:7 8.837232e-05 +23 chany_bottom_in[12]:7 ropt_net_149:8 8.837232e-05 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:15 0.04464286 +1 chany_bottom_in[12]:2 ropt_mt_inst_748:A 0.152 +2 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.006120536 +3 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.0045 +4 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.0045 +5 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.0056875 +6 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.006830357 +7 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.0045 +8 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0045 +9 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.0005267857 +10 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.0331875 +11 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.0045 +12 chany_bottom_in[12]:3 chany_bottom_in[12]:2 0.0004107143 +13 chany_bottom_in[12]:4 chany_bottom_in[12]:3 0.0003035715 +14 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.02580804 + +*END + +*D_NET chany_bottom_in[15] 0.01506168 //LENGTH 148.255 LUMPCC 0.0005897004 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 46.460 1.290 +*I ropt_mt_inst_744:A I *L 0.001767 *C 97.060 85.680 +*N chany_bottom_in[15]:2 *C 97.098 85.680 +*N chany_bottom_in[15]:3 *C 101.155 85.680 +*N chany_bottom_in[15]:4 *C 101.200 85.680 +*N chany_bottom_in[15]:5 *C 101.660 85.680 +*N chany_bottom_in[15]:6 *C 101.660 77.225 +*N chany_bottom_in[15]:7 *C 101.660 77.180 +*N chany_bottom_in[15]:8 *C 99.405 77.180 +*N chany_bottom_in[15]:9 *C 99.360 77.135 +*N chany_bottom_in[15]:10 *C 99.360 74.845 +*N chany_bottom_in[15]:11 *C 99.315 74.800 +*N chany_bottom_in[15]:12 *C 98.440 74.800 +*N chany_bottom_in[15]:13 *C 98.440 75.480 +*N chany_bottom_in[15]:14 *C 92.460 75.480 +*N chany_bottom_in[15]:15 *C 92.460 74.800 +*N chany_bottom_in[15]:16 *C 46.505 74.800 +*N chany_bottom_in[15]:17 *C 46.460 74.755 +*N chany_bottom_in[15]:18 *C 46.460 51.290 + +*CAP +0 chany_bottom_in[15] 0.002370392 +1 ropt_mt_inst_744:A 1e-06 +2 chany_bottom_in[15]:2 0.0002930116 +3 chany_bottom_in[15]:3 0.0002930116 +4 chany_bottom_in[15]:4 6.143317e-05 +5 chany_bottom_in[15]:5 0.0004913176 +6 chany_bottom_in[15]:6 0.0004596327 +7 chany_bottom_in[15]:7 0.0001825454 +8 chany_bottom_in[15]:8 0.0001535 +9 chany_bottom_in[15]:9 0.0001270949 +10 chany_bottom_in[15]:10 0.0001270949 +11 chany_bottom_in[15]:11 3.728877e-05 +12 chany_bottom_in[15]:12 7.493495e-05 +13 chany_bottom_in[15]:13 0.0003737937 +14 chany_bottom_in[15]:14 0.0003828741 +15 chany_bottom_in[15]:15 0.002316919 +16 chany_bottom_in[15]:16 0.002270192 +17 chany_bottom_in[15]:17 0.001042774 +18 chany_bottom_in[15]:18 0.003413166 +19 chany_bottom_in[15]:11 BUF_net_67:5 4.160986e-05 +20 chany_bottom_in[15]:14 BUF_net_67:6 4.026866e-05 +21 chany_bottom_in[15]:13 BUF_net_67:5 4.026866e-05 +22 chany_bottom_in[15]:12 BUF_net_67:6 4.160986e-05 +23 chany_bottom_in[15] ropt_net_115:4 7.127113e-05 +24 chany_bottom_in[15]:18 ropt_net_115:5 7.127113e-05 +25 chany_bottom_in[15] ropt_net_129:5 0.0001417005 +26 chany_bottom_in[15]:18 ropt_net_129:6 0.0001417005 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:18 0.04464286 +1 chany_bottom_in[15]:2 ropt_mt_inst_744:A 0.152 +2 chany_bottom_in[15]:3 chany_bottom_in[15]:2 0.003622768 +3 chany_bottom_in[15]:4 chany_bottom_in[15]:3 0.0045 +4 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.0045 +5 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.007549108 +6 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.002013393 +7 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.0045 +8 chany_bottom_in[15]:11 chany_bottom_in[15]:10 0.0045 +9 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.002044643 +10 chany_bottom_in[15]:16 chany_bottom_in[15]:15 0.04103125 +11 chany_bottom_in[15]:17 chany_bottom_in[15]:16 0.0045 +12 chany_bottom_in[15]:15 chany_bottom_in[15]:14 0.0006071429 +13 chany_bottom_in[15]:14 chany_bottom_in[15]:13 0.005339286 +14 chany_bottom_in[15]:13 chany_bottom_in[15]:12 0.0006071429 +15 chany_bottom_in[15]:12 chany_bottom_in[15]:11 0.00078125 +16 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.0004107143 +17 chany_bottom_in[15]:18 chany_bottom_in[15]:17 0.02095089 + +*END + +*D_NET chanx_right_in[14] 0.009265086 //LENGTH 80.925 LUMPCC 0.002115306 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 111.930 43.520 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.640 14.620 +*N chanx_right_in[14]:2 *C 61.603 14.620 +*N chanx_right_in[14]:3 *C 61.225 14.620 +*N chanx_right_in[14]:4 *C 61.180 14.665 +*N chanx_right_in[14]:5 *C 61.180 43.462 +*N chanx_right_in[14]:6 *C 61.188 43.520 + +*CAP +0 chanx_right_in[14] 0.002255201 +1 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[14]:2 4.700892e-05 +3 chanx_right_in[14]:3 4.700892e-05 +4 chanx_right_in[14]:4 0.00127218 +5 chanx_right_in[14]:5 0.00127218 +6 chanx_right_in[14]:6 0.002255201 +7 chanx_right_in[14] chanx_right_in[7]:17 4.74706e-05 +8 chanx_right_in[14]:4 chanx_right_in[7]:10 0.0002225923 +9 chanx_right_in[14]:5 chanx_right_in[7]:11 0.0002225923 +10 chanx_right_in[14]:6 chanx_right_in[7]:16 4.74706e-05 +11 chanx_right_in[14] chany_bottom_in[18]:6 0.0004288127 +12 chanx_right_in[14] chany_bottom_in[18]:7 0.0003587771 +13 chanx_right_in[14]:6 chany_bottom_in[18]:8 0.0003587771 +14 chanx_right_in[14]:6 chany_bottom_in[18]:7 0.0004288127 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:6 0.007949658 +1 chanx_right_in[14]:2 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[14]:3 chanx_right_in[14]:2 0.0003370536 +3 chanx_right_in[14]:4 chanx_right_in[14]:3 0.0045 +4 chanx_right_in[14]:5 chanx_right_in[14]:4 0.02571206 +5 chanx_right_in[14]:6 chanx_right_in[14]:5 0.00341 + +*END + +*D_NET chany_bottom_in[6] 0.007999226 //LENGTH 72.990 LUMPCC 0.001093645 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 52.900 1.290 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 88.955 37.060 +*N chany_bottom_in[6]:2 *C 88.918 37.060 +*N chany_bottom_in[6]:3 *C 83.305 37.060 +*N chany_bottom_in[6]:4 *C 83.260 37.015 +*N chany_bottom_in[6]:5 *C 83.260 3.458 +*N chany_bottom_in[6]:6 *C 83.252 3.400 +*N chany_bottom_in[6]:7 *C 52.908 3.400 +*N chany_bottom_in[6]:8 *C 52.900 3.343 + +*CAP +0 chany_bottom_in[6] 0.0001352494 +1 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[6]:2 0.0002192152 +3 chany_bottom_in[6]:3 0.0002192152 +4 chany_bottom_in[6]:4 0.00132387 +5 chany_bottom_in[6]:5 0.00132387 +6 chany_bottom_in[6]:6 0.001773956 +7 chany_bottom_in[6]:7 0.001773956 +8 chany_bottom_in[6]:8 0.0001352494 +9 chany_bottom_in[6]:2 mux_tree_tapbuf_size2_3_sram[1]:3 0.0002262328 +10 chany_bottom_in[6]:3 mux_tree_tapbuf_size2_3_sram[1]:4 0.0002262328 +11 chany_bottom_in[6]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003205895 +12 chany_bottom_in[6]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003205895 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:8 0.001832589 +1 chany_bottom_in[6]:2 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[6]:3 chany_bottom_in[6]:2 0.005011161 +3 chany_bottom_in[6]:4 chany_bottom_in[6]:3 0.0045 +4 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.02996206 +5 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.00341 +6 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.00341 +7 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.00475405 + +*END + +*D_NET chany_bottom_in[16] 0.0115046 //LENGTH 101.255 LUMPCC 0.001991074 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 41.860 1.290 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 95.855 47.940 +*N chany_bottom_in[16]:2 *C 95.855 47.940 +*N chany_bottom_in[16]:3 *C 95.680 47.940 +*N chany_bottom_in[16]:4 *C 95.680 47.940 +*N chany_bottom_in[16]:5 *C 95.680 47.600 +*N chany_bottom_in[16]:6 *C 95.672 47.600 +*N chany_bottom_in[16]:7 *C 41.867 47.600 +*N chany_bottom_in[16]:8 *C 41.860 47.543 + +*CAP +0 chany_bottom_in[16] 0.002143664 +1 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[16]:2 5.593026e-05 +3 chany_bottom_in[16]:3 5.632437e-05 +4 chany_bottom_in[16]:4 5.606338e-05 +5 chany_bottom_in[16]:5 6.005341e-05 +6 chany_bottom_in[16]:6 0.002498412 +7 chany_bottom_in[16]:7 0.002498412 +8 chany_bottom_in[16]:8 0.002143664 +9 chany_bottom_in[16]:6 chanx_right_in[7]:17 0.0007367207 +10 chany_bottom_in[16]:7 chanx_right_in[7]:16 0.0007367207 +11 chany_bottom_in[16] chany_bottom_in[17]:10 0.0002588163 +12 chany_bottom_in[16]:8 chany_bottom_in[17]:9 0.0002588163 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:8 0.04129688 +1 chany_bottom_in[16]:2 mux_right_track_4\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[16]:3 chany_bottom_in[16]:2 9.51087e-05 +3 chany_bottom_in[16]:4 chany_bottom_in[16]:3 0.0045 +4 chany_bottom_in[16]:5 chany_bottom_in[16]:4 0.0001634615 +5 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.00341 +6 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.00341 +7 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.00842945 + +*END + +*D_NET ccff_head[0] 0.006572278 //LENGTH 62.200 LUMPCC 0.0006578079 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 110.860 102.070 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 87.575 64.260 +*N ccff_head[0]:2 *C 87.612 64.260 +*N ccff_head[0]:3 *C 88.275 64.260 +*N ccff_head[0]:4 *C 88.320 64.305 +*N ccff_head[0]:5 *C 88.320 96.175 +*N ccff_head[0]:6 *C 88.365 96.220 +*N ccff_head[0]:7 *C 110.815 96.220 +*N ccff_head[0]:8 *C 110.860 96.265 + +*CAP +0 ccff_head[0] 0.0003278184 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 6.91773e-05 +3 ccff_head[0]:3 6.91773e-05 +4 ccff_head[0]:4 0.001509515 +5 ccff_head[0]:5 0.001509515 +6 ccff_head[0]:6 0.001050224 +7 ccff_head[0]:7 0.001050224 +8 ccff_head[0]:8 0.0003278184 +9 ccff_head[0]:6 ropt_net_154:5 0.000328904 +10 ccff_head[0]:7 ropt_net_154:6 0.000328904 + +*RES +0 ccff_head[0] ccff_head[0]:8 0.005183036 +1 ccff_head[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0005915179 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:6 ccff_head[0]:5 0.0045 +5 ccff_head[0]:5 ccff_head[0]:4 0.02845536 +6 ccff_head[0]:7 ccff_head[0]:6 0.02004464 +7 ccff_head[0]:8 ccff_head[0]:7 0.0045 + +*END + +*D_NET chanx_right_out[4] 0.006886131 //LENGTH 56.235 LUMPCC 0.001902682 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 91.780 47.940 +*P chanx_right_out[4] O *L 0.7423 *C 111.855 78.880 +*N chanx_right_out[4]:2 *C 107.640 78.880 +*N chanx_right_out[4]:3 *C 107.640 79.560 +*N chanx_right_out[4]:4 *C 103.508 79.560 +*N chanx_right_out[4]:5 *C 103.500 79.618 +*N chanx_right_out[4]:6 *C 103.500 80.535 +*N chanx_right_out[4]:7 *C 103.455 80.580 +*N chanx_right_out[4]:8 *C 92.045 80.580 +*N chanx_right_out[4]:9 *C 92.000 80.535 +*N chanx_right_out[4]:10 *C 92.000 47.985 +*N chanx_right_out[4]:11 *C 92.000 47.940 +*N chanx_right_out[4]:12 *C 91.780 47.940 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 chanx_right_out[4] 0.0001960931 +2 chanx_right_out[4]:2 0.0002409819 +3 chanx_right_out[4]:3 0.0002776834 +4 chanx_right_out[4]:4 0.0002327946 +5 chanx_right_out[4]:5 7.17312e-05 +6 chanx_right_out[4]:6 7.17312e-05 +7 chanx_right_out[4]:7 0.0004505068 +8 chanx_right_out[4]:8 0.0004505068 +9 chanx_right_out[4]:9 0.001441626 +10 chanx_right_out[4]:10 0.001441626 +11 chanx_right_out[4]:11 5.562868e-05 +12 chanx_right_out[4]:12 5.153961e-05 +13 chanx_right_out[4] chanx_right_in[10] 0.0001069962 +14 chanx_right_out[4]:4 chanx_right_in[10]:8 0.0002464278 +15 chanx_right_out[4]:3 chanx_right_in[10] 0.0002464278 +16 chanx_right_out[4]:2 chanx_right_in[10]:8 0.0001069962 +17 chanx_right_out[4]:8 chany_bottom_in[12]:9 1.303242e-05 +18 chanx_right_out[4]:8 chany_bottom_in[12]:13 0.0003644829 +19 chanx_right_out[4]:7 chany_bottom_in[12]:8 1.303242e-05 +20 chanx_right_out[4]:7 chany_bottom_in[12]:12 0.0003644829 +21 chanx_right_out[4]:4 chany_bottom_in[12]:9 6.256396e-06 +22 chanx_right_out[4]:3 chany_bottom_in[12]:8 6.256396e-06 +23 chanx_right_out[4]:10 mux_tree_tapbuf_size2_0_sram[0]:5 0.0001699738 +24 chanx_right_out[4]:10 mux_tree_tapbuf_size2_0_sram[0]:10 4.41714e-05 +25 chanx_right_out[4]:9 mux_tree_tapbuf_size2_0_sram[0]:10 0.0001699738 +26 chanx_right_out[4]:9 mux_tree_tapbuf_size2_0_sram[0]:11 4.41714e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X chanx_right_out[4]:12 0.152 +1 chanx_right_out[4]:12 chanx_right_out[4]:11 0.0001195652 +2 chanx_right_out[4]:11 chanx_right_out[4]:10 0.0045 +3 chanx_right_out[4]:10 chanx_right_out[4]:9 0.0290625 +4 chanx_right_out[4]:8 chanx_right_out[4]:7 0.0101875 +5 chanx_right_out[4]:9 chanx_right_out[4]:8 0.0045 +6 chanx_right_out[4]:7 chanx_right_out[4]:6 0.0045 +7 chanx_right_out[4]:6 chanx_right_out[4]:5 0.0008191965 +8 chanx_right_out[4]:5 chanx_right_out[4]:4 0.00341 +9 chanx_right_out[4]:4 chanx_right_out[4]:3 0.000647425 +10 chanx_right_out[4]:3 chanx_right_out[4]:2 0.0001065333 +11 chanx_right_out[4]:2 chanx_right_out[4] 0.00066035 + +*END + +*D_NET ropt_net_139 0.001123822 //LENGTH 8.490 LUMPCC 0.0002557018 DR + +*CONN +*I mem_bottom_track_25\/BUFT_RR_88:X O *L 0 *C 58.420 4.760 +*I ropt_mt_inst_755:A I *L 0.001766 *C 60.260 6.800 +*N ropt_net_139:2 *C 60.223 6.800 +*N ropt_net_139:3 *C 56.625 6.800 +*N ropt_net_139:4 *C 56.580 6.755 +*N ropt_net_139:5 *C 56.580 4.805 +*N ropt_net_139:6 *C 56.625 4.760 +*N ropt_net_139:7 *C 58.383 4.760 + +*CAP +0 mem_bottom_track_25\/BUFT_RR_88:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_139:2 0.0002270431 +3 ropt_net_139:3 0.0002270431 +4 ropt_net_139:4 0.0001053232 +5 ropt_net_139:5 0.0001053232 +6 ropt_net_139:6 0.0001006938 +7 ropt_net_139:7 0.0001006938 +8 ropt_net_139:4 mem_bottom_track_25/net_net_74:5 5.288653e-05 +9 ropt_net_139:5 mem_bottom_track_25/net_net_74:4 5.288653e-05 +10 ropt_net_139:6 ropt_net_117:8 7.496439e-05 +11 ropt_net_139:7 ropt_net_117:9 7.496439e-05 + +*RES +0 mem_bottom_track_25\/BUFT_RR_88:X ropt_net_139:7 0.152 +1 ropt_net_139:2 ropt_mt_inst_755:A 0.152 +2 ropt_net_139:3 ropt_net_139:2 0.003212054 +3 ropt_net_139:4 ropt_net_139:3 0.0045 +4 ropt_net_139:6 ropt_net_139:5 0.0045 +5 ropt_net_139:5 ropt_net_139:4 0.001741072 +6 ropt_net_139:7 ropt_net_139:6 0.001569196 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.002396583 //LENGTH 19.695 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 90.465 55.420 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 86.655 49.980 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 96.960 47.600 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 96.922 47.600 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 90.205 47.600 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 90.160 47.645 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 86.655 49.980 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 86.940 49.980 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 86.940 49.980 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 86.940 50.320 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 86.948 50.320 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 90.153 50.320 +*N mux_tree_tapbuf_size2_1_sram[0]:12 *C 90.160 50.320 +*N mux_tree_tapbuf_size2_1_sram[0]:13 *C 90.160 55.375 +*N mux_tree_tapbuf_size2_1_sram[0]:14 *C 90.160 55.420 +*N mux_tree_tapbuf_size2_1_sram[0]:15 *C 90.465 55.420 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 0.0004373314 +4 mux_tree_tapbuf_size2_1_sram[0]:4 0.0004373314 +5 mux_tree_tapbuf_size2_1_sram[0]:5 0.0001401829 +6 mux_tree_tapbuf_size2_1_sram[0]:6 4.403287e-05 +7 mux_tree_tapbuf_size2_1_sram[0]:7 4.786122e-05 +8 mux_tree_tapbuf_size2_1_sram[0]:8 4.645294e-05 +9 mux_tree_tapbuf_size2_1_sram[0]:9 5.006692e-05 +10 mux_tree_tapbuf_size2_1_sram[0]:10 0.0002156819 +11 mux_tree_tapbuf_size2_1_sram[0]:11 0.0002156819 +12 mux_tree_tapbuf_size2_1_sram[0]:12 0.0004138596 +13 mux_tree_tapbuf_size2_1_sram[0]:13 0.0002436996 +14 mux_tree_tapbuf_size2_1_sram[0]:14 5.176457e-05 +15 mux_tree_tapbuf_size2_1_sram[0]:15 4.963591e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:4 mux_tree_tapbuf_size2_1_sram[0]:3 0.005997769 +2 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size2_1_sram[0]:3 mux_right_track_4\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:11 0.00341 +5 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:5 0.002388393 +6 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.0005021166 +7 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.0001634615 +8 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.00341 +9 mux_tree_tapbuf_size2_1_sram[0]:7 mux_tree_tapbuf_size2_1_sram[0]:6 0.0001548913 +10 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size2_1_sram[0]:6 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_1_sram[0]:14 mux_tree_tapbuf_size2_1_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size2_1_sram[0]:13 mux_tree_tapbuf_size2_1_sram[0]:12 0.004513393 +14 mux_tree_tapbuf_size2_1_sram[0]:15 mux_tree_tapbuf_size2_1_sram[0]:14 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[0] 0.003607429 //LENGTH 26.370 LUMPCC 0.0003782208 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.465 20.400 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 63.020 14.785 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.935 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:3 *C 48.935 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:4 *C 48.760 17.000 +*N mux_tree_tapbuf_size2_6_sram[0]:5 *C 63.020 14.785 +*N mux_tree_tapbuf_size2_6_sram[0]:6 *C 63.020 14.960 +*N mux_tree_tapbuf_size2_6_sram[0]:7 *C 63.020 15.005 +*N mux_tree_tapbuf_size2_6_sram[0]:8 *C 63.020 16.955 +*N mux_tree_tapbuf_size2_6_sram[0]:9 *C 63.020 17.000 +*N mux_tree_tapbuf_size2_6_sram[0]:10 *C 63.480 17.000 +*N mux_tree_tapbuf_size2_6_sram[0]:11 *C 63.480 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:12 *C 65.735 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:13 *C 65.780 17.385 +*N mux_tree_tapbuf_size2_6_sram[0]:14 *C 65.780 20.355 +*N mux_tree_tapbuf_size2_6_sram[0]:15 *C 65.825 20.400 +*N mux_tree_tapbuf_size2_6_sram[0]:16 *C 67.428 20.400 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_6_sram[0]:3 6.337078e-05 +4 mux_tree_tapbuf_size2_6_sram[0]:4 0.0008399411 +5 mux_tree_tapbuf_size2_6_sram[0]:5 4.702716e-05 +6 mux_tree_tapbuf_size2_6_sram[0]:6 5.215909e-05 +7 mux_tree_tapbuf_size2_6_sram[0]:7 0.0001281703 +8 mux_tree_tapbuf_size2_6_sram[0]:8 0.0001281703 +9 mux_tree_tapbuf_size2_6_sram[0]:9 0.0008658377 +10 mux_tree_tapbuf_size2_6_sram[0]:10 6.086201e-05 +11 mux_tree_tapbuf_size2_6_sram[0]:11 0.0001784254 +12 mux_tree_tapbuf_size2_6_sram[0]:12 0.0001515727 +13 mux_tree_tapbuf_size2_6_sram[0]:13 0.0002151452 +14 mux_tree_tapbuf_size2_6_sram[0]:14 0.0002151452 +15 mux_tree_tapbuf_size2_6_sram[0]:15 0.0001401906 +16 mux_tree_tapbuf_size2_6_sram[0]:16 0.0001401906 +17 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[1]:12 0.0001004882 +18 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[1]:11 8.846569e-05 +19 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[1]:8 1.565016e-07 +20 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[1]:6 8.846569e-05 +21 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[1]:11 0.0001004882 +22 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[1]:7 1.565016e-07 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_6_sram[0]:16 0.152 +1 mux_tree_tapbuf_size2_6_sram[0]:5 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_6_sram[0]:6 mux_tree_tapbuf_size2_6_sram[0]:5 7.543104e-05 +3 mux_tree_tapbuf_size2_6_sram[0]:7 mux_tree_tapbuf_size2_6_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:4 0.01273214 +6 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:7 0.001741072 +7 mux_tree_tapbuf_size2_6_sram[0]:3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_6_sram[0]:12 mux_tree_tapbuf_size2_6_sram[0]:11 0.002013393 +9 mux_tree_tapbuf_size2_6_sram[0]:13 mux_tree_tapbuf_size2_6_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size2_6_sram[0]:15 mux_tree_tapbuf_size2_6_sram[0]:14 0.0045 +11 mux_tree_tapbuf_size2_6_sram[0]:14 mux_tree_tapbuf_size2_6_sram[0]:13 0.002651786 +12 mux_tree_tapbuf_size2_6_sram[0]:16 mux_tree_tapbuf_size2_6_sram[0]:15 0.001430803 +13 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[0]:3 0.0003035715 +14 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:9 0.0004107143 +15 mux_tree_tapbuf_size2_6_sram[0]:11 mux_tree_tapbuf_size2_6_sram[0]:10 0.0003035715 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001929126 //LENGTH 16.525 LUMPCC 0.000733369 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 96.885 42.500 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 97.060 58.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 97.060 58.125 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 97.060 57.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 97.060 57.755 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 97.060 42.545 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 97.060 42.500 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 96.885 42.500 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.433135e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.59729e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004878902 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004878902 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.143482e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.623706e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 right_top_grid_pin_1_[0]:18 5.616443e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 right_top_grid_pin_1_[0]:19 0.0001388395 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 right_top_grid_pin_1_[0]:16 5.616443e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 right_top_grid_pin_1_[0]:18 0.0001388395 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_111:10 6.107504e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_111:7 0.0001106055 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_111:11 6.107504e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_111:10 0.0001106055 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001766305 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01358036 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007008443 //LENGTH 5.320 LUMPCC 0.000129248 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 81.245 8.840 +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 81.245 4.270 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 81.245 4.270 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.420 4.420 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 81.420 4.465 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.420 8.795 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.420 8.840 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.245 8.840 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.344297e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.529778e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001823428 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001823428 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.924654e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.69234e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_110:7 6.448579e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_110:5 1.381983e-07 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_110:6 6.448579e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_110:4 1.381983e-07 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.510869e-05 + +*END + +*D_NET ropt_net_143 0.001436287 //LENGTH 10.155 LUMPCC 0.0003997738 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 50.350 11.485 +*I ropt_mt_inst_759:A I *L 0.001767 *C 48.300 4.080 +*N ropt_net_143:2 *C 48.300 4.080 +*N ropt_net_143:3 *C 48.300 4.125 +*N ropt_net_143:4 *C 48.300 11.515 +*N ropt_net_143:5 *C 48.345 11.560 +*N ropt_net_143:6 *C 50.312 11.545 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 ropt_mt_inst_759:A 1e-06 +2 ropt_net_143:2 3.460677e-05 +3 ropt_net_143:3 0.000322418 +4 ropt_net_143:4 0.000322418 +5 ropt_net_143:5 0.0001775352 +6 ropt_net_143:6 0.0001775352 +7 ropt_net_143:4 prog_clk[0]:100 0.0001998869 +8 ropt_net_143:3 prog_clk[0]:101 0.0001998869 + +*RES +0 ropt_mt_inst_731:X ropt_net_143:6 0.152 +1 ropt_net_143:6 ropt_net_143:5 0.001756696 +2 ropt_net_143:5 ropt_net_143:4 0.0045 +3 ropt_net_143:4 ropt_net_143:3 0.006598215 +4 ropt_net_143:2 ropt_mt_inst_759:A 0.152 +5 ropt_net_143:3 ropt_net_143:2 0.0045 + +*END + +*D_NET chanx_right_in[3] 0.01457386 //LENGTH 136.875 LUMPCC 0.003391372 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 111.930 96.560 +*I BUFT_RR_45:A I *L 0.001776 *C 67.160 6.800 +*N chanx_right_in[3]:2 *C 67.160 6.800 +*N chanx_right_in[3]:3 *C 66.745 6.800 +*N chanx_right_in[3]:4 *C 66.700 6.845 +*N chanx_right_in[3]:5 *C 66.700 56.640 +*N chanx_right_in[3]:6 *C 66.700 63.535 +*N chanx_right_in[3]:7 *C 66.745 63.580 +*N chanx_right_in[3]:8 *C 79.075 63.580 +*N chanx_right_in[3]:9 *C 79.120 63.625 +*N chanx_right_in[3]:10 *C 79.120 96.502 +*N chanx_right_in[3]:11 *C 79.127 96.560 + +*CAP +0 chanx_right_in[3] 0.001098902 +1 BUFT_RR_45:A 1e-06 +2 chanx_right_in[3]:2 7.86164e-05 +3 chanx_right_in[3]:3 4.295488e-05 +4 chanx_right_in[3]:4 0.001855702 +5 chanx_right_in[3]:5 0.002187653 +6 chanx_right_in[3]:6 0.0003319516 +7 chanx_right_in[3]:7 0.0006389809 +8 chanx_right_in[3]:8 0.0006389809 +9 chanx_right_in[3]:9 0.001604421 +10 chanx_right_in[3]:10 0.001604421 +11 chanx_right_in[3]:11 0.001098902 +12 chanx_right_in[3] chanx_right_in[2] 0.0004248616 +13 chanx_right_in[3]:11 chanx_right_in[2]:14 0.0004248616 +14 chanx_right_in[3]:4 chanx_right_in[5]:9 2.755388e-05 +15 chanx_right_in[3]:4 chanx_right_in[5]:12 0.0005291906 +16 chanx_right_in[3]:5 chanx_right_in[5]:8 2.755388e-05 +17 chanx_right_in[3]:5 chanx_right_in[5]:13 0.0005291906 +18 chanx_right_in[3]:4 mux_tree_tapbuf_size2_7_sram[0]:8 0.000220611 +19 chanx_right_in[3]:4 mux_tree_tapbuf_size2_7_sram[0]:5 7.889525e-05 +20 chanx_right_in[3]:5 mux_tree_tapbuf_size2_7_sram[0]:8 7.889525e-05 +21 chanx_right_in[3]:5 mux_tree_tapbuf_size2_7_sram[0]:9 0.000220611 +22 chanx_right_in[3] chanx_right_out[5] 9.06049e-05 +23 chanx_right_in[3] chanx_right_out[5]:3 0.0003239686 +24 chanx_right_in[3]:11 chanx_right_out[5]:4 0.0003239686 +25 chanx_right_in[3]:11 chanx_right_out[5]:2 9.06049e-05 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:11 0.005139058 +1 chanx_right_in[3]:2 BUFT_RR_45:A 0.152 +2 chanx_right_in[3]:3 chanx_right_in[3]:2 0.0003705357 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0045 +4 chanx_right_in[3]:7 chanx_right_in[3]:6 0.0045 +5 chanx_right_in[3]:6 chanx_right_in[3]:5 0.00615625 +6 chanx_right_in[3]:8 chanx_right_in[3]:7 0.01100893 +7 chanx_right_in[3]:9 chanx_right_in[3]:8 0.0045 +8 chanx_right_in[3]:10 chanx_right_in[3]:9 0.02935491 +9 chanx_right_in[3]:11 chanx_right_in[3]:10 0.00341 +10 chanx_right_in[3]:5 chanx_right_in[3]:4 0.04445983 + +*END + +*D_NET chany_bottom_out[4] 0.002631936 //LENGTH 18.915 LUMPCC 0.0002716478 DR + +*CONN +*I mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 44.105 11.900 +*P chany_bottom_out[4] O *L 0.7423 *C 51.060 1.325 +*N chany_bottom_out[4]:2 *C 51.060 9.135 +*N chany_bottom_out[4]:3 *C 51.015 9.180 +*N chany_bottom_out[4]:4 *C 46.965 9.180 +*N chany_bottom_out[4]:5 *C 46.920 9.225 +*N chany_bottom_out[4]:6 *C 46.920 11.515 +*N chany_bottom_out[4]:7 *C 46.875 11.560 +*N chany_bottom_out[4]:8 *C 44.620 11.560 +*N chany_bottom_out[4]:9 *C 44.620 11.900 +*N chany_bottom_out[4]:10 *C 44.143 11.900 + +*CAP +0 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[4] 0.0004605267 +2 chany_bottom_out[4]:2 0.0004605267 +3 chany_bottom_out[4]:3 0.0002702991 +4 chany_bottom_out[4]:4 0.0002702991 +5 chany_bottom_out[4]:5 0.0001794698 +6 chany_bottom_out[4]:6 0.0001794698 +7 chany_bottom_out[4]:7 0.00019878 +8 chany_bottom_out[4]:8 0.0002239092 +9 chany_bottom_out[4]:9 7.056812e-05 +10 chany_bottom_out[4]:10 4.543894e-05 +11 chany_bottom_out[4]:4 ropt_net_142:5 3.357845e-05 +12 chany_bottom_out[4]:4 ropt_net_142:3 3.307888e-05 +13 chany_bottom_out[4]:3 ropt_net_142:2 3.307888e-05 +14 chany_bottom_out[4]:3 ropt_net_142:4 3.357845e-05 +15 chany_bottom_out[4] ropt_net_148:4 6.916658e-05 +16 chany_bottom_out[4]:2 ropt_net_148:5 6.916658e-05 + +*RES +0 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[4]:10 0.152 +1 chany_bottom_out[4]:10 chany_bottom_out[4]:9 0.0004263393 +2 chany_bottom_out[4]:7 chany_bottom_out[4]:6 0.0045 +3 chany_bottom_out[4]:6 chany_bottom_out[4]:5 0.002044643 +4 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.003616071 +5 chany_bottom_out[4]:5 chany_bottom_out[4]:4 0.0045 +6 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +7 chany_bottom_out[4]:2 chany_bottom_out[4] 0.006973214 +8 chany_bottom_out[4]:9 chany_bottom_out[4]:8 0.0003035714 +9 chany_bottom_out[4]:8 chany_bottom_out[4]:7 0.002013393 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.001806201 //LENGTH 14.815 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.805 44.880 +*I mem_right_track_8\/FTB_3__34:A I *L 0.001746 *C 75.900 50.320 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.008363 *C 82.960 47.323 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 75.862 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 75.485 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 75.440 50.275 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 75.440 47.305 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 75.485 47.260 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 80.500 47.260 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 80.500 47.215 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 80.500 44.925 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 80.500 44.880 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 80.805 44.880 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_8\/FTB_3__34:A 1e-06 +2 mux_right_track_8\/mux_l2_in_0_:S 0.0001528429 +3 mux_tree_tapbuf_size2_2_sram[1]:3 4.061318e-05 +4 mux_tree_tapbuf_size2_2_sram[1]:4 4.061318e-05 +5 mux_tree_tapbuf_size2_2_sram[1]:5 0.0001813853 +6 mux_tree_tapbuf_size2_2_sram[1]:6 0.0001813853 +7 mux_tree_tapbuf_size2_2_sram[1]:7 0.0002851236 +8 mux_tree_tapbuf_size2_2_sram[1]:8 0.0004694082 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.0001722962 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.0001722962 +11 mux_tree_tapbuf_size2_2_sram[1]:11 5.39898e-05 +12 mux_tree_tapbuf_size2_2_sram[1]:12 5.424683e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.004477679 +2 mux_tree_tapbuf_size2_2_sram[1]:8 mux_right_track_8\/mux_l2_in_0_:S 0.002196429 +3 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.002044643 +6 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 8.967391e-05 +7 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.0045 +8 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.002651786 +9 mux_tree_tapbuf_size2_2_sram[1]:4 mux_tree_tapbuf_size2_2_sram[1]:3 0.0003370536 +10 mux_tree_tapbuf_size2_2_sram[1]:5 mux_tree_tapbuf_size2_2_sram[1]:4 0.0045 +11 mux_tree_tapbuf_size2_2_sram[1]:3 mem_right_track_8\/FTB_3__34:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[1] 0.002090766 //LENGTH 14.015 LUMPCC 0.0003782208 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.585 17.340 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 50.240 14.280 +*I mem_bottom_track_9\/FTB_7__38:A I *L 0.001746 *C 49.680 20.400 +*N mux_tree_tapbuf_size2_6_sram[1]:3 *C 49.680 20.400 +*N mux_tree_tapbuf_size2_6_sram[1]:4 *C 49.680 20.355 +*N mux_tree_tapbuf_size2_6_sram[1]:5 *C 49.680 17.385 +*N mux_tree_tapbuf_size2_6_sram[1]:6 *C 49.725 17.340 +*N mux_tree_tapbuf_size2_6_sram[1]:7 *C 50.278 14.280 +*N mux_tree_tapbuf_size2_6_sram[1]:8 *C 51.935 14.280 +*N mux_tree_tapbuf_size2_6_sram[1]:9 *C 51.980 14.325 +*N mux_tree_tapbuf_size2_6_sram[1]:10 *C 51.980 17.295 +*N mux_tree_tapbuf_size2_6_sram[1]:11 *C 51.980 17.340 +*N mux_tree_tapbuf_size2_6_sram[1]:12 *C 54.547 17.340 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_9\/FTB_7__38:A 1e-06 +3 mux_tree_tapbuf_size2_6_sram[1]:3 3.38025e-05 +4 mux_tree_tapbuf_size2_6_sram[1]:4 0.0002225034 +5 mux_tree_tapbuf_size2_6_sram[1]:5 0.0002225034 +6 mux_tree_tapbuf_size2_6_sram[1]:6 0.0001121172 +7 mux_tree_tapbuf_size2_6_sram[1]:7 0.0001551712 +8 mux_tree_tapbuf_size2_6_sram[1]:8 0.0001551712 +9 mux_tree_tapbuf_size2_6_sram[1]:9 0.0002178761 +10 mux_tree_tapbuf_size2_6_sram[1]:10 0.0002178761 +11 mux_tree_tapbuf_size2_6_sram[1]:11 0.0002593868 +12 mux_tree_tapbuf_size2_6_sram[1]:12 0.0001131375 +13 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[0]:4 8.846569e-05 +14 mux_tree_tapbuf_size2_6_sram[1]:12 mux_tree_tapbuf_size2_6_sram[0]:9 0.0001004882 +15 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[0]:4 0.0001004882 +16 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[0]:9 8.846569e-05 +17 mux_tree_tapbuf_size2_6_sram[1]:8 mux_tree_tapbuf_size2_6_sram[0]:9 1.565016e-07 +18 mux_tree_tapbuf_size2_6_sram[1]:7 mux_tree_tapbuf_size2_6_sram[0]:4 1.565016e-07 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_6_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_6_sram[1]:3 mem_bottom_track_9\/FTB_7__38:A 0.152 +2 mux_tree_tapbuf_size2_6_sram[1]:4 mux_tree_tapbuf_size2_6_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_6_sram[1]:4 0.002651786 +5 mux_tree_tapbuf_size2_6_sram[1]:12 mux_tree_tapbuf_size2_6_sram[1]:11 0.002292411 +6 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[1]:6 0.002013393 +8 mux_tree_tapbuf_size2_6_sram[1]:10 mux_tree_tapbuf_size2_6_sram[1]:9 0.002651786 +9 mux_tree_tapbuf_size2_6_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:7 0.001479911 +10 mux_tree_tapbuf_size2_6_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size2_6_sram[1]:7 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET optlc_net_111 0.005017079 //LENGTH 44.790 LUMPCC 0.00042213 DR + +*CONN +*I optlc_111:HI O *L 0 *C 90.620 42.160 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 93.555 37.400 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.005103 *C 86.940 48.435 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 99.075 49.640 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 96.775 58.820 +*N optlc_net_111:5 *C 96.812 58.820 +*N optlc_net_111:6 *C 97.935 58.820 +*N optlc_net_111:7 *C 97.980 58.775 +*N optlc_net_111:8 *C 99.038 49.640 +*N optlc_net_111:9 *C 98.025 49.640 +*N optlc_net_111:10 *C 97.980 49.640 +*N optlc_net_111:11 *C 97.980 44.585 +*N optlc_net_111:12 *C 97.935 44.540 +*N optlc_net_111:13 *C 86.978 48.435 +*N optlc_net_111:14 *C 88.275 48.388 +*N optlc_net_111:15 *C 88.320 48.235 +*N optlc_net_111:16 *C 88.320 44.585 +*N optlc_net_111:17 *C 88.365 44.540 +*N optlc_net_111:18 *C 92.000 44.540 +*N optlc_net_111:19 *C 92.000 44.495 +*N optlc_net_111:20 *C 93.517 37.400 +*N optlc_net_111:21 *C 92.965 37.400 +*N optlc_net_111:22 *C 92.920 37.445 +*N optlc_net_111:23 *C 92.920 39.055 +*N optlc_net_111:24 *C 92.875 39.100 +*N optlc_net_111:25 *C 92.045 39.100 +*N optlc_net_111:26 *C 92.000 39.145 +*N optlc_net_111:27 *C 92.000 42.160 +*N optlc_net_111:28 *C 91.955 42.160 +*N optlc_net_111:29 *C 90.657 42.160 + +*CAP +0 optlc_111:HI 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +3 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +4 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +5 optlc_net_111:5 9.426435e-05 +6 optlc_net_111:6 9.426435e-05 +7 optlc_net_111:7 0.0003541374 +8 optlc_net_111:8 9.462026e-05 +9 optlc_net_111:9 9.462026e-05 +10 optlc_net_111:10 0.0005847102 +11 optlc_net_111:11 0.0002037396 +12 optlc_net_111:12 0.0003274189 +13 optlc_net_111:13 0.0001192301 +14 optlc_net_111:14 0.0001192301 +15 optlc_net_111:15 0.0002207537 +16 optlc_net_111:16 0.0002207537 +17 optlc_net_111:17 0.0002031764 +18 optlc_net_111:18 0.0005616977 +19 optlc_net_111:19 0.0001346534 +20 optlc_net_111:20 6.171865e-05 +21 optlc_net_111:21 6.171865e-05 +22 optlc_net_111:22 0.0001002885 +23 optlc_net_111:23 0.0001002885 +24 optlc_net_111:24 6.592974e-05 +25 optlc_net_111:25 6.592974e-05 +26 optlc_net_111:26 0.0001634385 +27 optlc_net_111:27 0.0003301654 +28 optlc_net_111:28 0.0001066002 +29 optlc_net_111:29 0.0001066002 +30 optlc_net_111:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.107504e-05 +31 optlc_net_111:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.107504e-05 +32 optlc_net_111:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001106055 +33 optlc_net_111:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001106055 +34 optlc_net_111:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.230707e-05 +35 optlc_net_111:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.230707e-05 +36 optlc_net_111:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.707737e-05 +37 optlc_net_111:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.707737e-05 + +*RES +0 optlc_111:HI optlc_net_111:29 0.152 +1 optlc_net_111:12 optlc_net_111:11 0.0045 +2 optlc_net_111:11 optlc_net_111:10 0.004513393 +3 optlc_net_111:18 optlc_net_111:17 0.003245536 +4 optlc_net_111:18 optlc_net_111:12 0.005299107 +5 optlc_net_111:19 optlc_net_111:18 0.0045 +6 optlc_net_111:25 optlc_net_111:24 0.0007410714 +7 optlc_net_111:26 optlc_net_111:25 0.0045 +8 optlc_net_111:24 optlc_net_111:23 0.0045 +9 optlc_net_111:23 optlc_net_111:22 0.0014375 +10 optlc_net_111:21 optlc_net_111:20 0.0004933036 +11 optlc_net_111:22 optlc_net_111:21 0.0045 +12 optlc_net_111:20 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +13 optlc_net_111:13 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +14 optlc_net_111:14 optlc_net_111:13 0.001158482 +15 optlc_net_111:15 optlc_net_111:14 0.0045 +16 optlc_net_111:17 optlc_net_111:16 0.0045 +17 optlc_net_111:16 optlc_net_111:15 0.003258928 +18 optlc_net_111:9 optlc_net_111:8 0.0009040178 +19 optlc_net_111:10 optlc_net_111:9 0.0045 +20 optlc_net_111:10 optlc_net_111:7 0.008156251 +21 optlc_net_111:8 mux_right_track_4\/mux_l2_in_0_:A0 0.152 +22 optlc_net_111:6 optlc_net_111:5 0.001002232 +23 optlc_net_111:7 optlc_net_111:6 0.0045 +24 optlc_net_111:5 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +25 optlc_net_111:28 optlc_net_111:27 0.0045 +26 optlc_net_111:27 optlc_net_111:26 0.002691964 +27 optlc_net_111:27 optlc_net_111:19 0.002084821 +28 optlc_net_111:29 optlc_net_111:28 0.001158482 + +*END + +*D_NET ropt_net_153 0.001470708 //LENGTH 10.005 LUMPCC 0.0005880172 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 41.135 6.120 +*I ropt_mt_inst_769:A I *L 0.001767 *C 39.100 4.080 +*N ropt_net_153:2 *C 39.100 4.080 +*N ropt_net_153:3 *C 39.100 3.740 +*N ropt_net_153:4 *C 43.195 3.740 +*N ropt_net_153:5 *C 43.240 3.785 +*N ropt_net_153:6 *C 43.240 6.075 +*N ropt_net_153:7 *C 43.195 6.120 +*N ropt_net_153:8 *C 41.172 6.120 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 ropt_mt_inst_769:A 1e-06 +2 ropt_net_153:2 5.181301e-05 +3 ropt_net_153:3 0.000155953 +4 ropt_net_153:4 0.0001303275 +5 ropt_net_153:5 0.000110088 +6 ropt_net_153:6 0.000110088 +7 ropt_net_153:7 0.0001612106 +8 ropt_net_153:8 0.0001612106 +9 ropt_net_153:5 chany_bottom_in[14] 7.050472e-05 +10 ropt_net_153:6 chany_bottom_in[14]:8 7.050472e-05 +11 ropt_net_153:4 ropt_net_158:2 0.0001116964 +12 ropt_net_153:3 ropt_net_158:3 0.0001116964 +13 ropt_net_153:4 chany_bottom_out[10]:3 0.0001118075 +14 ropt_net_153:3 chany_bottom_out[10]:4 0.0001118075 + +*RES +0 ropt_mt_inst_734:X ropt_net_153:8 0.152 +1 ropt_net_153:2 ropt_mt_inst_769:A 0.152 +2 ropt_net_153:4 ropt_net_153:3 0.00365625 +3 ropt_net_153:5 ropt_net_153:4 0.0045 +4 ropt_net_153:7 ropt_net_153:6 0.0045 +5 ropt_net_153:6 ropt_net_153:5 0.002044643 +6 ropt_net_153:8 ropt_net_153:7 0.001805804 +7 ropt_net_153:3 ropt_net_153:2 0.0003035715 + +*END + +*D_NET ropt_net_159 0.0006766872 //LENGTH 4.795 LUMPCC 0.0003437312 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 21.815 4.760 +*I ropt_mt_inst_775:A I *L 0.001766 *C 23.460 6.800 +*N ropt_net_159:2 *C 23.422 6.800 +*N ropt_net_159:3 *C 21.665 6.800 +*N ropt_net_159:4 *C 21.620 6.755 +*N ropt_net_159:5 *C 21.620 4.805 +*N ropt_net_159:6 *C 21.620 4.760 +*N ropt_net_159:7 *C 21.815 4.760 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 ropt_mt_inst_775:A 1e-06 +2 ropt_net_159:2 6.596154e-05 +3 ropt_net_159:3 6.596154e-05 +4 ropt_net_159:4 5.223485e-05 +5 ropt_net_159:5 5.223485e-05 +6 ropt_net_159:6 4.928545e-05 +7 ropt_net_159:7 4.52777e-05 +8 ropt_net_159:5 chanx_right_in[9]:3 2.756531e-05 +9 ropt_net_159:3 chanx_right_in[9]:5 7.996253e-05 +10 ropt_net_159:4 chanx_right_in[9]:4 2.756531e-05 +11 ropt_net_159:2 chanx_right_in[9]:6 7.996253e-05 +12 ropt_net_159:5 chany_bottom_in[7] 6.433776e-05 +13 ropt_net_159:4 chany_bottom_in[7]:6 6.433776e-05 + +*RES +0 ropt_mt_inst_742:X ropt_net_159:7 0.152 +1 ropt_net_159:7 ropt_net_159:6 0.0001059783 +2 ropt_net_159:6 ropt_net_159:5 0.0045 +3 ropt_net_159:5 ropt_net_159:4 0.001741072 +4 ropt_net_159:3 ropt_net_159:2 0.001569197 +5 ropt_net_159:4 ropt_net_159:3 0.0045 +6 ropt_net_159:2 ropt_mt_inst_775:A 0.152 + +*END + +*D_NET chanx_right_in[4] 0.01060941 //LENGTH 91.640 LUMPCC 0.003245706 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 111.930 34.000 +*I BUFT_P_93:A I *L 0.001776 *C 40.480 14.960 +*N chanx_right_in[4]:2 *C 40.480 14.960 +*N chanx_right_in[4]:3 *C 40.480 15.005 +*N chanx_right_in[4]:4 *C 40.480 28.515 +*N chanx_right_in[4]:5 *C 40.525 28.560 +*N chanx_right_in[4]:6 *C 45.035 28.560 +*N chanx_right_in[4]:7 *C 45.080 28.605 +*N chanx_right_in[4]:8 *C 45.080 33.943 +*N chanx_right_in[4]:9 *C 45.088 34.000 +*N chanx_right_in[4]:10 *C 94.915 34.000 + +*CAP +0 chanx_right_in[4] 0.0005639813 +1 BUFT_P_93:A 1e-06 +2 chanx_right_in[4]:2 3.378196e-05 +3 chanx_right_in[4]:3 0.0006614198 +4 chanx_right_in[4]:4 0.0006614198 +5 chanx_right_in[4]:5 0.0002832196 +6 chanx_right_in[4]:6 0.0002832196 +7 chanx_right_in[4]:7 0.000298614 +8 chanx_right_in[4]:8 0.000298614 +9 chanx_right_in[4]:9 0.001857229 +10 chanx_right_in[4]:10 0.00242121 +11 chanx_right_in[4] chanx_right_in[9] 0.0001193239 +12 chanx_right_in[4] chanx_right_in[9]:19 0.0001806511 +13 chanx_right_in[4]:9 chanx_right_in[9]:17 0.0005128845 +14 chanx_right_in[4]:9 chanx_right_in[9]:18 0.0002309448 +15 chanx_right_in[4]:10 chanx_right_in[9]:19 0.0002309448 +16 chanx_right_in[4]:10 chanx_right_in[9]:20 0.0001193239 +17 chanx_right_in[4]:10 chanx_right_in[9]:18 0.0006935355 +18 chanx_right_in[4] chany_bottom_in[9]:10 0.0001838404 +19 chanx_right_in[4]:9 chany_bottom_in[9]:11 0.0003952083 +20 chanx_right_in[4]:10 chany_bottom_in[9]:10 0.0003952083 +21 chanx_right_in[4]:10 chany_bottom_in[9]:11 0.0001838404 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:10 0.002665683 +1 chanx_right_in[4]:2 BUFT_P_93:A 0.152 +2 chanx_right_in[4]:3 chanx_right_in[4]:2 0.0045 +3 chanx_right_in[4]:5 chanx_right_in[4]:4 0.0045 +4 chanx_right_in[4]:4 chanx_right_in[4]:3 0.0120625 +5 chanx_right_in[4]:6 chanx_right_in[4]:5 0.004026786 +6 chanx_right_in[4]:7 chanx_right_in[4]:6 0.0045 +7 chanx_right_in[4]:8 chanx_right_in[4]:7 0.004765625 +8 chanx_right_in[4]:9 chanx_right_in[4]:8 0.00341 +9 chanx_right_in[4]:10 chanx_right_in[4]:9 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.001363022 //LENGTH 11.975 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 92.305 49.980 +*I mem_right_track_4\/FTB_2__33:A I *L 0.001746 *C 94.760 53.040 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 100.180 50.320 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 100.142 50.320 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 94.760 53.040 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 94.760 52.995 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 94.760 50.365 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 94.760 50.320 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 94.760 49.980 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 92.343 49.980 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_4\/FTB_2__33:A 1e-06 +2 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 0.0003332226 +4 mux_tree_tapbuf_size2_1_sram[1]:4 3.307891e-05 +5 mux_tree_tapbuf_size2_1_sram[1]:5 0.0001424913 +6 mux_tree_tapbuf_size2_1_sram[1]:6 0.0001424913 +7 mux_tree_tapbuf_size2_1_sram[1]:7 0.0003615995 +8 mux_tree_tapbuf_size2_1_sram[1]:8 0.0001877575 +9 mux_tree_tapbuf_size2_1_sram[1]:9 0.0001593806 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:9 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:3 mux_right_track_4\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[1]:9 mux_tree_tapbuf_size2_1_sram[1]:8 0.002158482 +3 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:3 0.004805804 +5 mux_tree_tapbuf_size2_1_sram[1]:6 mux_tree_tapbuf_size2_1_sram[1]:5 0.002348214 +6 mux_tree_tapbuf_size2_1_sram[1]:4 mem_right_track_4\/FTB_2__33:A 0.152 +7 mux_tree_tapbuf_size2_1_sram[1]:5 mux_tree_tapbuf_size2_1_sram[1]:4 0.0045 +8 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.001054768 //LENGTH 8.740 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/FTB_3__34:X O *L 0 *C 72.905 49.640 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 71.935 42.500 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 71.935 42.500 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 72.220 42.500 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 72.220 42.545 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 72.220 49.595 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 72.265 49.640 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 72.868 49.640 + +*CAP +0 mem_right_track_8\/FTB_3__34:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 5.166938e-05 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 5.54748e-05 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.0004099465 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0004099465 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 6.286561e-05 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 6.286561e-05 + +*RES +0 mem_right_track_8\/FTB_3__34:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.006294644 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007092753 //LENGTH 5.180 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 77.105 9.180 +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 79.195 6.665 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 79.195 6.665 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 77.325 6.800 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 77.280 6.845 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 77.280 9.135 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 77.280 9.180 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 77.105 9.180 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001667219 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001368048 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001474992 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001474992 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.300954e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.574055e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001669643 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_163 0.0006682933 //LENGTH 5.425 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 35.420 4.760 +*I ropt_mt_inst_779:A I *L 0.001766 *C 32.660 6.800 +*N ropt_net_163:2 *C 32.660 6.800 +*N ropt_net_163:3 *C 32.660 6.755 +*N ropt_net_163:4 *C 32.660 4.805 +*N ropt_net_163:5 *C 32.705 4.760 +*N ropt_net_163:6 *C 35.383 4.760 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_163:2 3.099691e-05 +3 ropt_net_163:3 0.0001229156 +4 ropt_net_163:4 0.0001229156 +5 ropt_net_163:5 0.0001947326 +6 ropt_net_163:6 0.0001947326 + +*RES +0 ropt_mt_inst_735:X ropt_net_163:6 0.152 +1 ropt_net_163:6 ropt_net_163:5 0.002390625 +2 ropt_net_163:5 ropt_net_163:4 0.0045 +3 ropt_net_163:4 ropt_net_163:3 0.001741072 +4 ropt_net_163:2 ropt_mt_inst_779:A 0.152 +5 ropt_net_163:3 ropt_net_163:2 0.0045 + +*END + +*D_NET chanx_right_in[5] 0.0145786 //LENGTH 114.750 LUMPCC 0.005639648 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 111.930 62.560 +*I BUFT_RR_79:A I *L 0.001776 *C 64.400 4.080 +*N chanx_right_in[5]:2 *C 64.362 4.080 +*N chanx_right_in[5]:3 *C 63.065 4.080 +*N chanx_right_in[5]:4 *C 63.020 4.125 +*N chanx_right_in[5]:5 *C 63.020 10.155 +*N chanx_right_in[5]:6 *C 63.065 10.200 +*N chanx_right_in[5]:7 *C 66.165 10.230 +*N chanx_right_in[5]:8 *C 66.233 10.190 +*N chanx_right_in[5]:9 *C 66.240 9.565 +*N chanx_right_in[5]:10 *C 66.285 9.520 +*N chanx_right_in[5]:11 *C 67.575 9.520 +*N chanx_right_in[5]:12 *C 67.620 9.565 +*N chanx_right_in[5]:13 *C 67.620 50.275 +*N chanx_right_in[5]:14 *C 67.665 50.320 +*N chanx_right_in[5]:15 *C 69.315 50.320 +*N chanx_right_in[5]:16 *C 73.095 50.320 +*N chanx_right_in[5]:17 *C 73.140 50.365 +*N chanx_right_in[5]:18 *C 73.140 63.183 +*N chanx_right_in[5]:19 *C 73.148 63.240 +*N chanx_right_in[5]:20 *C 108.100 63.240 +*N chanx_right_in[5]:21 *C 108.100 62.560 + +*CAP +0 chanx_right_in[5] 0.0001537461 +1 BUFT_RR_79:A 1e-06 +2 chanx_right_in[5]:2 0.0001083529 +3 chanx_right_in[5]:3 0.0001083529 +4 chanx_right_in[5]:4 0.0003368983 +5 chanx_right_in[5]:5 0.0003368983 +6 chanx_right_in[5]:6 0.0002193577 +7 chanx_right_in[5]:7 0.0002193577 +8 chanx_right_in[5]:8 3.226082e-05 +9 chanx_right_in[5]:9 3.226082e-05 +10 chanx_right_in[5]:10 0.0001067166 +11 chanx_right_in[5]:11 0.0001067166 +12 chanx_right_in[5]:12 0.001514157 +13 chanx_right_in[5]:13 0.001514157 +14 chanx_right_in[5]:14 9.271283e-05 +15 chanx_right_in[5]:15 0.0002969198 +16 chanx_right_in[5]:16 0.000204207 +17 chanx_right_in[5]:17 0.0006354742 +18 chanx_right_in[5]:18 0.0006354742 +19 chanx_right_in[5]:19 0.001020139 +20 chanx_right_in[5]:20 0.001065092 +21 chanx_right_in[5]:21 0.0001986992 +22 chanx_right_in[5]:8 chanx_right_in[3]:5 2.755388e-05 +23 chanx_right_in[5]:9 chanx_right_in[3]:4 2.755388e-05 +24 chanx_right_in[5]:12 chanx_right_in[3]:4 0.0005291906 +25 chanx_right_in[5]:13 chanx_right_in[3]:5 0.0005291906 +26 chanx_right_in[5] chanx_right_in[17] 0.0001066661 +27 chanx_right_in[5]:19 chanx_right_in[17]:15 0.0004447889 +28 chanx_right_in[5]:19 chanx_right_in[17]:16 8.068379e-05 +29 chanx_right_in[5]:20 chanx_right_in[17] 8.068379e-05 +30 chanx_right_in[5]:20 chanx_right_in[17]:16 0.0004447889 +31 chanx_right_in[5]:21 chanx_right_in[17]:16 0.0001066661 +32 chanx_right_in[5]:19 chany_bottom_in[3]:10 0.001441823 +33 chanx_right_in[5]:20 chany_bottom_in[3]:9 0.001441823 +34 chanx_right_in[5]:12 ropt_net_122:4 0.0001891183 +35 chanx_right_in[5]:13 ropt_net_122:5 0.0001891183 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:21 0.0006000333 +1 chanx_right_in[5]:2 BUFT_RR_79:A 0.152 +2 chanx_right_in[5]:3 chanx_right_in[5]:2 0.001158482 +3 chanx_right_in[5]:4 chanx_right_in[5]:3 0.0045 +4 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +5 chanx_right_in[5]:5 chanx_right_in[5]:4 0.005383929 +6 chanx_right_in[5]:7 chanx_right_in[5]:6 0.002767857 +7 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0045 +8 chanx_right_in[5]:10 chanx_right_in[5]:9 0.0045 +9 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0005580357 +10 chanx_right_in[5]:11 chanx_right_in[5]:10 0.001151786 +11 chanx_right_in[5]:12 chanx_right_in[5]:11 0.0045 +12 chanx_right_in[5]:14 chanx_right_in[5]:13 0.0045 +13 chanx_right_in[5]:13 chanx_right_in[5]:12 0.03634822 +14 chanx_right_in[5]:16 chanx_right_in[5]:15 0.003375 +15 chanx_right_in[5]:17 chanx_right_in[5]:16 0.0045 +16 chanx_right_in[5]:18 chanx_right_in[5]:17 0.0114442 +17 chanx_right_in[5]:19 chanx_right_in[5]:18 0.00341 +18 chanx_right_in[5]:15 chanx_right_in[5]:14 0.001473214 +19 chanx_right_in[5]:20 chanx_right_in[5]:19 0.005475891 +20 chanx_right_in[5]:21 chanx_right_in[5]:20 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.004268906 //LENGTH 37.460 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 75.745 33.660 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 52.615 26.180 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 76.460 23.800 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 76.360 23.800 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 76.360 23.845 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 76.360 26.135 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 76.315 26.180 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 52.653 26.180 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 73.140 26.180 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 73.140 26.225 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 73.140 33.615 +*N mux_tree_tapbuf_size2_4_sram[0]:11 *C 73.185 33.660 +*N mux_tree_tapbuf_size2_4_sram[0]:12 *C 75.708 33.660 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 3.069842e-05 +4 mux_tree_tapbuf_size2_4_sram[0]:4 0.0001597024 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.0001597024 +6 mux_tree_tapbuf_size2_4_sram[0]:6 0.0001818772 +7 mux_tree_tapbuf_size2_4_sram[0]:7 0.001183109 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.001395069 +9 mux_tree_tapbuf_size2_4_sram[0]:9 0.0004143738 +10 mux_tree_tapbuf_size2_4_sram[0]:10 0.0004143738 +11 mux_tree_tapbuf_size2_4_sram[0]:11 0.0001634998 +12 mux_tree_tapbuf_size2_4_sram[0]:12 0.0001634998 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.01829241 +2 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:6 0.002834822 +3 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.0045 +4 mux_tree_tapbuf_size2_4_sram[0]:11 mux_tree_tapbuf_size2_4_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 0.006598215 +6 mux_tree_tapbuf_size2_4_sram[0]:12 mux_tree_tapbuf_size2_4_sram[0]:11 0.002252232 +7 mux_tree_tapbuf_size2_4_sram[0]:6 mux_tree_tapbuf_size2_4_sram[0]:5 0.0045 +8 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_4_sram[0]:4 0.002044643 +9 mux_tree_tapbuf_size2_4_sram[0]:3 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size2_4_sram[0]:4 mux_tree_tapbuf_size2_4_sram[0]:3 0.0045 +11 mux_tree_tapbuf_size2_4_sram[0]:7 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.001766963 //LENGTH 14.260 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/FTB_5__36:X O *L 0 *C 52.675 31.960 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 66.415 31.620 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 66.415 31.620 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 66.240 31.960 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 *C 52.713 31.960 + +*CAP +0 mem_bottom_track_1\/FTB_5__36:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 5.008027e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0008692946 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0008455884 + +*RES +0 mem_bottom_track_1\/FTB_5__36:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.01207813 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000312651 //LENGTH 2.490 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 101.025 50.320 +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.300 50.155 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 103.300 50.155 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 101.062 50.320 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001693896 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001412614 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001997768 + +*END + +*D_NET ropt_net_157 0.002463621 //LENGTH 15.585 LUMPCC 0.0005845772 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 56.580 6.120 +*I ropt_mt_inst_773:A I *L 0.001766 *C 46.000 9.520 +*N ropt_net_157:2 *C 46.000 9.520 +*N ropt_net_157:3 *C 46.000 9.475 +*N ropt_net_157:4 *C 46.000 7.538 +*N ropt_net_157:5 *C 46.008 7.480 +*N ropt_net_157:6 *C 48.753 7.480 +*N ropt_net_157:7 *C 48.760 7.423 +*N ropt_net_157:8 *C 48.760 6.505 +*N ropt_net_157:9 *C 48.805 6.460 +*N ropt_net_157:10 *C 54.740 6.460 +*N ropt_net_157:11 *C 54.740 6.120 +*N ropt_net_157:12 *C 56.543 6.120 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 ropt_mt_inst_773:A 1e-06 +2 ropt_net_157:2 3.687389e-05 +3 ropt_net_157:3 0.0001152063 +4 ropt_net_157:4 0.0001152063 +5 ropt_net_157:5 8.949089e-05 +6 ropt_net_157:6 8.949089e-05 +7 ropt_net_157:7 8.734612e-05 +8 ropt_net_157:8 8.734612e-05 +9 ropt_net_157:9 0.0004631674 +10 ropt_net_157:10 0.0004895147 +11 ropt_net_157:11 0.0001648741 +12 ropt_net_157:12 0.0001385268 +13 ropt_net_157:5 chany_bottom_in[9]:15 0.0001672337 +14 ropt_net_157:6 chany_bottom_in[9]:14 0.0001672337 +15 ropt_net_157:5 bottom_left_grid_pin_1_[0]:30 6.423207e-05 +16 ropt_net_157:6 bottom_left_grid_pin_1_[0]:29 6.423207e-05 +17 ropt_net_157:3 ropt_net_129:6 6.082285e-05 +18 ropt_net_157:4 ropt_net_129:5 6.082285e-05 + +*RES +0 ropt_mt_inst_736:X ropt_net_157:12 0.152 +1 ropt_net_157:2 ropt_mt_inst_773:A 0.152 +2 ropt_net_157:3 ropt_net_157:2 0.0045 +3 ropt_net_157:4 ropt_net_157:3 0.001729911 +4 ropt_net_157:5 ropt_net_157:4 0.00341 +5 ropt_net_157:7 ropt_net_157:6 0.00341 +6 ropt_net_157:6 ropt_net_157:5 0.00043005 +7 ropt_net_157:9 ropt_net_157:8 0.0045 +8 ropt_net_157:8 ropt_net_157:7 0.0008191965 +9 ropt_net_157:12 ropt_net_157:11 0.001609375 +10 ropt_net_157:10 ropt_net_157:9 0.005299107 +11 ropt_net_157:11 ropt_net_157:10 0.0003035715 + +*END + +*D_NET ropt_net_156 0.001631808 //LENGTH 12.980 LUMPCC 0.0004597284 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 97.980 85.340 +*I ropt_mt_inst_772:A I *L 0.001766 *C 106.260 88.400 +*N ropt_net_156:2 *C 106.223 88.400 +*N ropt_net_156:3 *C 104.925 88.400 +*N ropt_net_156:4 *C 104.880 88.355 +*N ropt_net_156:5 *C 104.880 85.058 +*N ropt_net_156:6 *C 104.873 85.000 +*N ropt_net_156:7 *C 97.988 85.000 +*N ropt_net_156:8 *C 97.980 85.000 +*N ropt_net_156:9 *C 97.980 85.340 +*N ropt_net_156:10 *C 97.980 85.340 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_156:2 6.184777e-05 +3 ropt_net_156:3 6.184777e-05 +4 ropt_net_156:4 0.0001751205 +5 ropt_net_156:5 0.0001751205 +6 ropt_net_156:6 0.0002852476 +7 ropt_net_156:7 0.0002852476 +8 ropt_net_156:8 4.920589e-05 +9 ropt_net_156:9 4.521319e-05 +10 ropt_net_156:10 3.122904e-05 +11 ropt_net_156:7 chanx_right_in[0]:9 9.261654e-05 +12 ropt_net_156:6 chanx_right_in[0] 9.261654e-05 +13 ropt_net_156:7 ropt_net_162:7 4.795202e-05 +14 ropt_net_156:5 ropt_net_162:4 2.226213e-05 +15 ropt_net_156:5 ropt_net_162:9 4.971122e-06 +16 ropt_net_156:6 ropt_net_162:6 4.795202e-05 +17 ropt_net_156:4 ropt_net_162:5 2.226213e-05 +18 ropt_net_156:4 ropt_net_162:8 4.971122e-06 +19 ropt_net_156:3 ropt_net_135:7 6.206238e-05 +20 ropt_net_156:2 ropt_net_135:6 6.206238e-05 + +*RES +0 ropt_mt_inst_744:X ropt_net_156:10 0.152 +1 ropt_net_156:10 ropt_net_156:9 0.0045 +2 ropt_net_156:9 ropt_net_156:8 0.0001057692 +3 ropt_net_156:8 ropt_net_156:7 0.00341 +4 ropt_net_156:7 ropt_net_156:6 0.00107865 +5 ropt_net_156:5 ropt_net_156:4 0.002944197 +6 ropt_net_156:6 ropt_net_156:5 0.00341 +7 ropt_net_156:3 ropt_net_156:2 0.001158482 +8 ropt_net_156:4 ropt_net_156:3 0.0045 +9 ropt_net_156:2 ropt_mt_inst_772:A 0.152 + +*END + +*D_NET ropt_net_161 0.0004710794 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 107.180 46.920 +*I ropt_mt_inst_777:A I *L 0.001766 *C 106.260 44.880 +*N ropt_net_161:2 *C 106.260 44.880 +*N ropt_net_161:3 *C 106.260 44.925 +*N ropt_net_161:4 *C 106.260 46.875 +*N ropt_net_161:5 *C 106.305 46.920 +*N ropt_net_161:6 *C 107.142 46.920 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 ropt_mt_inst_777:A 1e-06 +2 ropt_net_161:2 3.113505e-05 +3 ropt_net_161:3 0.0001406912 +4 ropt_net_161:4 0.0001406912 +5 ropt_net_161:5 7.828103e-05 +6 ropt_net_161:6 7.828103e-05 + +*RES +0 ropt_mt_inst_752:X ropt_net_161:6 0.152 +1 ropt_net_161:6 ropt_net_161:5 0.0007477679 +2 ropt_net_161:5 ropt_net_161:4 0.0045 +3 ropt_net_161:4 ropt_net_161:3 0.001741072 +4 ropt_net_161:2 ropt_mt_inst_777:A 0.152 +5 ropt_net_161:3 ropt_net_161:2 0.0045 + +*END + +*D_NET ropt_net_152 0.001244305 //LENGTH 11.215 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_753:X O *L 0 *C 110.135 74.120 +*I ropt_mt_inst_768:A I *L 0.001767 *C 106.260 72.080 +*N ropt_net_152:2 *C 106.297 72.080 +*N ropt_net_152:3 *C 108.055 72.080 +*N ropt_net_152:4 *C 108.100 72.035 +*N ropt_net_152:5 *C 108.100 71.445 +*N ropt_net_152:6 *C 108.145 71.400 +*N ropt_net_152:7 *C 111.275 71.400 +*N ropt_net_152:8 *C 111.320 71.445 +*N ropt_net_152:9 *C 111.320 74.075 +*N ropt_net_152:10 *C 111.275 74.120 +*N ropt_net_152:11 *C 110.172 74.120 + +*CAP +0 ropt_mt_inst_753:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_152:2 0.0001157332 +3 ropt_net_152:3 0.0001157332 +4 ropt_net_152:4 5.641369e-05 +5 ropt_net_152:5 5.641369e-05 +6 ropt_net_152:6 0.0002096097 +7 ropt_net_152:7 0.0002096097 +8 ropt_net_152:8 0.0001502321 +9 ropt_net_152:9 0.0001502321 +10 ropt_net_152:10 8.916395e-05 +11 ropt_net_152:11 8.916395e-05 + +*RES +0 ropt_mt_inst_753:X ropt_net_152:11 0.152 +1 ropt_net_152:2 ropt_mt_inst_768:A 0.152 +2 ropt_net_152:3 ropt_net_152:2 0.001569197 +3 ropt_net_152:4 ropt_net_152:3 0.0045 +4 ropt_net_152:6 ropt_net_152:5 0.0045 +5 ropt_net_152:5 ropt_net_152:4 0.0005267857 +6 ropt_net_152:7 ropt_net_152:6 0.002794643 +7 ropt_net_152:8 ropt_net_152:7 0.0045 +8 ropt_net_152:10 ropt_net_152:9 0.0045 +9 ropt_net_152:9 ropt_net_152:8 0.002348214 +10 ropt_net_152:11 ropt_net_152:10 0.000984375 + +*END + +*D_NET chany_bottom_out[10] 0.0007571637 //LENGTH 5.335 LUMPCC 0.000223615 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 40.020 3.400 +*P chany_bottom_out[10] O *L 0.7423 *C 42.780 1.290 +*N chany_bottom_out[10]:2 *C 42.780 3.355 +*N chany_bottom_out[10]:3 *C 42.735 3.400 +*N chany_bottom_out[10]:4 *C 40.058 3.400 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 chany_bottom_out[10] 0.0001424511 +2 chany_bottom_out[10]:2 0.0001424511 +3 chany_bottom_out[10]:3 0.0001238233 +4 chany_bottom_out[10]:4 0.0001238233 +5 chany_bottom_out[10]:4 ropt_net_153:3 0.0001118075 +6 chany_bottom_out[10]:3 ropt_net_153:4 0.0001118075 + +*RES +0 ropt_mt_inst_769:X chany_bottom_out[10]:4 0.152 +1 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.002390625 +2 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0045 +3 chany_bottom_out[10]:2 chany_bottom_out[10] 0.00184375 + +*END + +*D_NET chanx_right_out[1] 0.000572774 //LENGTH 4.545 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_756:X O *L 0 *C 110.165 49.640 +*P chanx_right_out[1] O *L 0.7423 *C 111.855 47.600 +*N chanx_right_out[1]:2 *C 111.328 47.600 +*N chanx_right_out[1]:3 *C 111.320 47.657 +*N chanx_right_out[1]:4 *C 111.320 49.595 +*N chanx_right_out[1]:5 *C 111.275 49.640 +*N chanx_right_out[1]:6 *C 110.203 49.640 + +*CAP +0 ropt_mt_inst_756:X 1e-06 +1 chanx_right_out[1] 5.702723e-05 +2 chanx_right_out[1]:2 5.702723e-05 +3 chanx_right_out[1]:3 0.0001409095 +4 chanx_right_out[1]:4 0.0001409095 +5 chanx_right_out[1]:5 8.795032e-05 +6 chanx_right_out[1]:6 8.795032e-05 + +*RES +0 ropt_mt_inst_756:X chanx_right_out[1]:6 0.152 +1 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +2 chanx_right_out[1]:2 chanx_right_out[1] 8.264167e-05 +3 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +4 chanx_right_out[1]:4 chanx_right_out[1]:3 0.001729911 +5 chanx_right_out[1]:6 chanx_right_out[1]:5 0.0009575893 + +*END + +*D_NET chany_bottom_out[3] 0.0007047049 //LENGTH 5.530 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 47.575 3.400 +*P chany_bottom_out[3] O *L 0.7423 *C 44.620 1.290 +*N chany_bottom_out[3]:2 *C 44.620 3.355 +*N chany_bottom_out[3]:3 *C 44.665 3.400 +*N chany_bottom_out[3]:4 *C 47.538 3.400 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 chany_bottom_out[3] 0.0001327089 +2 chany_bottom_out[3]:2 0.0001327089 +3 chany_bottom_out[3]:3 0.0002191435 +4 chany_bottom_out[3]:4 0.0002191435 + +*RES +0 ropt_mt_inst_774:X chany_bottom_out[3]:4 0.152 +1 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.002564732 +2 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0045 +3 chany_bottom_out[3]:2 chany_bottom_out[3] 0.00184375 + +*END + +*D_NET chanx_right_in[7] 0.01075336 //LENGTH 94.695 LUMPCC 0.002013567 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 111.863 50.320 +*I BUFT_RR_48:A I *L 0.001776 *C 62.560 9.520 +*N chanx_right_in[7]:2 *C 61.850 9.520 +*N chanx_right_in[7]:3 *C 62.560 9.520 +*N chanx_right_in[7]:4 *C 62.560 9.520 +*N chanx_right_in[7]:5 *C 62.558 9.520 +*N chanx_right_in[7]:6 *C 62.560 9.527 +*N chanx_right_in[7]:7 *C 62.560 23.113 +*N chanx_right_in[7]:8 *C 62.545 23.120 +*N chanx_right_in[7]:9 *C 62.103 23.120 +*N chanx_right_in[7]:10 *C 62.100 23.178 +*N chanx_right_in[7]:11 *C 62.100 39.055 +*N chanx_right_in[7]:12 *C 62.145 39.100 +*N chanx_right_in[7]:13 *C 64.815 39.100 +*N chanx_right_in[7]:14 *C 64.860 39.145 +*N chanx_right_in[7]:15 *C 64.860 48.903 +*N chanx_right_in[7]:16 *C 64.868 48.960 +*N chanx_right_in[7]:17 *C 111.773 48.960 +*N chanx_right_in[7]:18 *C 111.780 49.018 +*N chanx_right_in[7]:19 *C 111.780 50.263 +*N chanx_right_in[7]:20 *C 111.780 50.320 + +*CAP +0 chanx_right_in[7] 2.770886e-05 +1 BUFT_RR_48:A 1e-06 +2 chanx_right_in[7]:2 8.903247e-05 +3 chanx_right_in[7]:3 2.89325e-05 +4 chanx_right_in[7]:4 3.215246e-05 +5 chanx_right_in[7]:5 8.903247e-05 +6 chanx_right_in[7]:6 0.0006312482 +7 chanx_right_in[7]:7 0.0006312482 +8 chanx_right_in[7]:8 4.170418e-05 +9 chanx_right_in[7]:9 4.170418e-05 +10 chanx_right_in[7]:10 0.0006015477 +11 chanx_right_in[7]:11 0.0006015477 +12 chanx_right_in[7]:12 0.0001610167 +13 chanx_right_in[7]:13 0.0001610167 +14 chanx_right_in[7]:14 0.0005374287 +15 chanx_right_in[7]:15 0.0005374287 +16 chanx_right_in[7]:16 0.002162137 +17 chanx_right_in[7]:17 0.002162137 +18 chanx_right_in[7]:18 8.70322e-05 +19 chanx_right_in[7]:19 8.70322e-05 +20 chanx_right_in[7]:20 2.770886e-05 +21 chanx_right_in[7]:10 chanx_right_in[14]:4 0.0002225923 +22 chanx_right_in[7]:11 chanx_right_in[14]:5 0.0002225923 +23 chanx_right_in[7]:16 chanx_right_in[14]:6 4.74706e-05 +24 chanx_right_in[7]:17 chanx_right_in[14] 4.74706e-05 +25 chanx_right_in[7]:16 chany_bottom_in[16]:7 0.0007367207 +26 chanx_right_in[7]:17 chany_bottom_in[16]:6 0.0007367207 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:20 2.35e-05 +1 chanx_right_in[7]:3 BUFT_RR_48:A 0.152 +2 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0045 +3 chanx_right_in[7]:5 chanx_right_in[7]:4 0.00341 +4 chanx_right_in[7]:5 chanx_right_in[7]:2 0.0001039141 +5 chanx_right_in[7]:6 chanx_right_in[7]:5 0.00341 +6 chanx_right_in[7]:8 chanx_right_in[7]:7 0.00341 +7 chanx_right_in[7]:7 chanx_right_in[7]:6 0.002128317 +8 chanx_right_in[7]:10 chanx_right_in[7]:9 0.00341 +9 chanx_right_in[7]:9 chanx_right_in[7]:8 6.499219e-05 +10 chanx_right_in[7]:12 chanx_right_in[7]:11 0.0045 +11 chanx_right_in[7]:11 chanx_right_in[7]:10 0.01417634 +12 chanx_right_in[7]:13 chanx_right_in[7]:12 0.002383929 +13 chanx_right_in[7]:14 chanx_right_in[7]:13 0.0045 +14 chanx_right_in[7]:15 chanx_right_in[7]:14 0.008712054 +15 chanx_right_in[7]:16 chanx_right_in[7]:15 0.00341 +16 chanx_right_in[7]:18 chanx_right_in[7]:17 0.00341 +17 chanx_right_in[7]:17 chanx_right_in[7]:16 0.007348449 +18 chanx_right_in[7]:19 chanx_right_in[7]:18 0.001111607 +19 chanx_right_in[7]:20 chanx_right_in[7]:19 0.00341 + +*END + +*D_NET chany_bottom_in[4] 0.01179746 //LENGTH 113.515 LUMPCC 0.002070099 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 73.140 1.290 +*I BUFT_RR_61:A I *L 0.001776 *C 98.440 88.400 +*N chany_bottom_in[4]:2 *C 98.403 88.400 +*N chany_bottom_in[4]:3 *C 81.005 88.400 +*N chany_bottom_in[4]:4 *C 80.960 88.355 +*N chany_bottom_in[4]:5 *C 80.960 62.760 +*N chany_bottom_in[4]:6 *C 80.960 12.965 +*N chany_bottom_in[4]:7 *C 80.915 12.920 +*N chany_bottom_in[4]:8 *C 73.185 12.920 +*N chany_bottom_in[4]:9 *C 73.140 12.875 + +*CAP +0 chany_bottom_in[4] 0.000559739 +1 BUFT_RR_61:A 1e-06 +2 chany_bottom_in[4]:2 0.0008639548 +3 chany_bottom_in[4]:3 0.0008639548 +4 chany_bottom_in[4]:4 0.001022944 +5 chany_bottom_in[4]:5 0.002950781 +6 chany_bottom_in[4]:6 0.001927837 +7 chany_bottom_in[4]:7 0.0004887033 +8 chany_bottom_in[4]:8 0.0004887033 +9 chany_bottom_in[4]:9 0.000559739 +10 chany_bottom_in[4]:4 chanx_right_in[10]:6 6.814374e-05 +11 chany_bottom_in[4]:4 chanx_right_in[10]:7 0.000170391 +12 chany_bottom_in[4]:6 chanx_right_in[10]:5 0.0005818862 +13 chany_bottom_in[4]:5 chanx_right_in[10]:5 6.814374e-05 +14 chany_bottom_in[4]:5 chanx_right_in[10]:6 0.0007522771 +15 chany_bottom_in[4]:6 mux_tree_tapbuf_size2_5_sram[1]:5 2.947745e-05 +16 chany_bottom_in[4]:6 mux_tree_tapbuf_size2_5_sram[1]:7 7.369748e-05 +17 chany_bottom_in[4]:5 mux_tree_tapbuf_size2_5_sram[1]:7 2.947745e-05 +18 chany_bottom_in[4]:5 mux_tree_tapbuf_size2_5_sram[1]:8 7.369748e-05 +19 chany_bottom_in[4] mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001114538 +20 chany_bottom_in[4]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001114538 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:9 0.01034375 +1 chany_bottom_in[4]:2 BUFT_RR_61:A 0.152 +2 chany_bottom_in[4]:3 chany_bottom_in[4]:2 0.01553348 +3 chany_bottom_in[4]:4 chany_bottom_in[4]:3 0.0045 +4 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.0045 +5 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.04445983 +6 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.006901786 +7 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.0045 +8 chany_bottom_in[4]:5 chany_bottom_in[4]:4 0.02285268 + +*END + +*D_NET chany_bottom_in[8] 0.01237162 //LENGTH 107.760 LUMPCC 0 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 23.920 1.290 +*I BUFT_RR_64:A I *L 0.001776 *C 96.140 34.000 +*N chany_bottom_in[8]:2 *C 96.140 34.000 +*N chany_bottom_in[8]:3 *C 96.140 33.955 +*N chany_bottom_in[8]:4 *C 96.140 28.945 +*N chany_bottom_in[8]:5 *C 96.140 28.900 +*N chany_bottom_in[8]:6 *C 96.140 28.560 +*N chany_bottom_in[8]:7 *C 81.420 28.560 +*N chany_bottom_in[8]:8 *C 81.420 29.240 +*N chany_bottom_in[8]:9 *C 73.600 29.240 +*N chany_bottom_in[8]:10 *C 73.600 27.880 +*N chany_bottom_in[8]:11 *C 23.965 27.880 +*N chany_bottom_in[8]:12 *C 23.920 27.835 + +*CAP +0 chany_bottom_in[8] 0.001269546 +1 BUFT_RR_64:A 1e-06 +2 chany_bottom_in[8]:2 3.763839e-05 +3 chany_bottom_in[8]:3 0.0002730822 +4 chany_bottom_in[8]:4 0.0002730822 +5 chany_bottom_in[8]:5 6.303374e-05 +6 chany_bottom_in[8]:6 0.0008973624 +7 chany_bottom_in[8]:7 0.0009160573 +8 chany_bottom_in[8]:8 0.0006181644 +9 chany_bottom_in[8]:9 0.0006476471 +10 chany_bottom_in[8]:10 0.003091227 +11 chany_bottom_in[8]:11 0.003014234 +12 chany_bottom_in[8]:12 0.001269546 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:12 0.02370089 +1 chany_bottom_in[8]:2 BUFT_RR_64:A 0.152 +2 chany_bottom_in[8]:3 chany_bottom_in[8]:2 0.0045 +3 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.0045 +4 chany_bottom_in[8]:4 chany_bottom_in[8]:3 0.004473215 +5 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.04431697 +6 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.0045 +7 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.001214286 +8 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.006982143 +9 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.000607143 +10 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.01314286 +11 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.0003035715 + +*END + +*D_NET chany_bottom_in[10] 0.01423264 //LENGTH 136.870 LUMPCC 0.002648143 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 51.980 1.290 +*I ropt_mt_inst_746:A I *L 0.001767 *C 101.660 82.960 +*N chany_bottom_in[10]:2 *C 101.698 82.960 +*N chany_bottom_in[10]:3 *C 102.120 82.960 +*N chany_bottom_in[10]:4 *C 102.120 82.620 +*N chany_bottom_in[10]:5 *C 98.440 82.620 +*N chany_bottom_in[10]:6 *C 98.520 83.640 +*N chany_bottom_in[10]:7 *C 98.450 83.595 +*N chany_bottom_in[10]:8 *C 98.440 83.005 +*N chany_bottom_in[10]:9 *C 98.440 82.960 +*N chany_bottom_in[10]:10 *C 97.565 82.960 +*N chany_bottom_in[10]:11 *C 97.520 82.960 +*N chany_bottom_in[10]:12 *C 97.513 82.960 +*N chany_bottom_in[10]:13 *C 53.380 82.960 +*N chany_bottom_in[10]:14 *C 53.360 82.953 +*N chany_bottom_in[10]:15 *C 53.360 55.275 +*N chany_bottom_in[10]:16 *C 53.360 5.448 +*N chany_bottom_in[10]:17 *C 53.340 5.440 +*N chany_bottom_in[10]:18 *C 51.988 5.440 +*N chany_bottom_in[10]:19 *C 51.980 5.383 + +*CAP +0 chany_bottom_in[10] 0.0002753907 +1 ropt_mt_inst_746:A 1e-06 +2 chany_bottom_in[10]:2 4.674983e-05 +3 chany_bottom_in[10]:3 7.276037e-05 +4 chany_bottom_in[10]:4 0.0002298289 +5 chany_bottom_in[10]:5 0.0002227537 +6 chany_bottom_in[10]:6 6.56679e-05 +7 chany_bottom_in[10]:7 4.879436e-05 +8 chany_bottom_in[10]:8 4.879436e-05 +9 chany_bottom_in[10]:9 0.0001219623 +10 chany_bottom_in[10]:10 6.561799e-05 +11 chany_bottom_in[10]:11 3.226388e-05 +12 chany_bottom_in[10]:12 0.001939892 +13 chany_bottom_in[10]:13 0.001939892 +14 chany_bottom_in[10]:14 0.001190995 +15 chany_bottom_in[10]:15 0.002940193 +16 chany_bottom_in[10]:16 0.001749197 +17 chany_bottom_in[10]:17 0.0001586786 +18 chany_bottom_in[10]:18 0.0001586786 +19 chany_bottom_in[10]:19 0.0002753907 +20 chany_bottom_in[10]:12 chanx_right_in[0] 0.0002775929 +21 chany_bottom_in[10]:12 chanx_right_in[0]:8 1.753833e-05 +22 chany_bottom_in[10]:13 chanx_right_in[0]:7 1.753833e-05 +23 chany_bottom_in[10]:13 chanx_right_in[0]:9 0.0002775929 +24 chany_bottom_in[10]:16 chany_bottom_in[5]:17 0.00102894 +25 chany_bottom_in[10]:15 chany_bottom_in[5]:16 0.00102894 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:19 0.003654018 +1 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.00078125 +2 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.0045 +3 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.00341 +4 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.006914091 +5 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.00341 +6 chany_bottom_in[10]:17 chany_bottom_in[10]:16 0.00341 +7 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.007806308 +8 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.00341 +9 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.0002118916 +10 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.0045 +11 chany_bottom_in[10]:9 chany_bottom_in[10]:5 0.0003035715 +12 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.0005267857 +13 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.0045 +14 chany_bottom_in[10]:2 ropt_mt_inst_746:A 0.152 +15 chany_bottom_in[10]:5 chany_bottom_in[10]:4 0.003285715 +16 chany_bottom_in[10]:4 chany_bottom_in[10]:3 0.0003035715 +17 chany_bottom_in[10]:3 chany_bottom_in[10]:2 0.0003772322 +18 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.004336141 + +*END + +*D_NET chany_bottom_in[19] 0.01513528 //LENGTH 137.565 LUMPCC 0.001852221 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 24.840 1.290 +*I ropt_mt_inst_752:A I *L 0.001767 *C 106.260 47.600 +*N chany_bottom_in[19]:2 *C 106.297 47.600 +*N chany_bottom_in[19]:3 *C 107.135 47.600 +*N chany_bottom_in[19]:4 *C 107.180 47.555 +*N chany_bottom_in[19]:5 *C 107.180 42.545 +*N chany_bottom_in[19]:6 *C 107.135 42.500 +*N chany_bottom_in[19]:7 *C 100.740 42.500 +*N chany_bottom_in[19]:8 *C 100.740 42.160 +*N chany_bottom_in[19]:9 *C 99.865 42.160 +*N chany_bottom_in[19]:10 *C 99.820 42.115 +*N chany_bottom_in[19]:11 *C 99.820 29.978 +*N chany_bottom_in[19]:12 *C 99.828 29.920 +*N chany_bottom_in[19]:13 *C 102.120 29.920 +*N chany_bottom_in[19]:14 *C 102.120 27.880 +*N chany_bottom_in[19]:15 *C 82.930 27.880 +*N chany_bottom_in[19]:16 *C 33.140 27.880 +*N chany_bottom_in[19]:17 *C 33.120 27.873 +*N chany_bottom_in[19]:18 *C 33.120 2.728 +*N chany_bottom_in[19]:19 *C 33.100 2.720 +*N chany_bottom_in[19]:20 *C 24.848 2.720 +*N chany_bottom_in[19]:21 *C 24.840 2.663 + +*CAP +0 chany_bottom_in[19] 9.241607e-05 +1 ropt_mt_inst_752:A 1e-06 +2 chany_bottom_in[19]:2 7.207856e-05 +3 chany_bottom_in[19]:3 7.207856e-05 +4 chany_bottom_in[19]:4 0.0002986684 +5 chany_bottom_in[19]:5 0.0002986684 +6 chany_bottom_in[19]:6 0.0003584329 +7 chany_bottom_in[19]:7 0.0003839216 +8 chany_bottom_in[19]:8 9.315737e-05 +9 chany_bottom_in[19]:9 6.76686e-05 +10 chany_bottom_in[19]:10 0.0005466087 +11 chany_bottom_in[19]:11 0.0005466087 +12 chany_bottom_in[19]:12 0.0001177278 +13 chany_bottom_in[19]:13 0.0002100095 +14 chany_bottom_in[19]:14 0.0007061739 +15 chany_bottom_in[19]:15 0.003328875 +16 chany_bottom_in[19]:16 0.002714983 +17 chany_bottom_in[19]:17 0.001048971 +18 chany_bottom_in[19]:18 0.001048971 +19 chany_bottom_in[19]:19 0.0005918131 +20 chany_bottom_in[19]:20 0.0005918131 +21 chany_bottom_in[19]:21 9.241607e-05 +22 chany_bottom_in[19]:10 chany_bottom_in[2]:10 8.569015e-05 +23 chany_bottom_in[19]:11 chany_bottom_in[2]:11 8.569015e-05 +24 chany_bottom_in[19]:12 chany_bottom_in[2]:13 9.848437e-05 +25 chany_bottom_in[19]:16 chany_bottom_in[2]:13 0.0001453485 +26 chany_bottom_in[19]:14 chany_bottom_in[2]:11 1.663373e-05 +27 chany_bottom_in[19]:14 chany_bottom_in[2]:12 0.0004668763 +28 chany_bottom_in[19]:13 chany_bottom_in[2]:10 1.663373e-05 +29 chany_bottom_in[19]:13 chany_bottom_in[2]:12 9.848437e-05 +30 chany_bottom_in[19]:15 chany_bottom_in[2]:12 0.0001453485 +31 chany_bottom_in[19]:15 chany_bottom_in[2]:13 0.0004668763 +32 chany_bottom_in[19]:4 ropt_net_167:5 8.032206e-08 +33 chany_bottom_in[19]:6 ropt_net_167:2 0.0001129972 +34 chany_bottom_in[19]:5 ropt_net_167:4 8.032206e-08 +35 chany_bottom_in[19]:7 ropt_net_167:3 0.0001129972 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:21 0.001225446 +1 chany_bottom_in[19]:2 ropt_mt_inst_752:A 0.152 +2 chany_bottom_in[19]:3 chany_bottom_in[19]:2 0.0007477679 +3 chany_bottom_in[19]:4 chany_bottom_in[19]:3 0.0045 +4 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.0045 +5 chany_bottom_in[19]:5 chany_bottom_in[19]:4 0.004473215 +6 chany_bottom_in[19]:9 chany_bottom_in[19]:8 0.00078125 +7 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.0045 +8 chany_bottom_in[19]:11 chany_bottom_in[19]:10 0.01083705 +9 chany_bottom_in[19]:12 chany_bottom_in[19]:11 0.00341 +10 chany_bottom_in[19]:16 chany_bottom_in[19]:15 0.007800433 +11 chany_bottom_in[19]:17 chany_bottom_in[19]:16 0.00341 +12 chany_bottom_in[19]:19 chany_bottom_in[19]:18 0.00341 +13 chany_bottom_in[19]:18 chany_bottom_in[19]:17 0.003939383 +14 chany_bottom_in[19]:21 chany_bottom_in[19]:20 0.00341 +15 chany_bottom_in[19]:20 chany_bottom_in[19]:19 0.001292892 +16 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.0003035715 +17 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.005709822 +18 chany_bottom_in[19]:14 chany_bottom_in[19]:13 0.0003196 +19 chany_bottom_in[19]:13 chany_bottom_in[19]:12 0.0003591583 +20 chany_bottom_in[19]:15 chany_bottom_in[19]:14 0.003006433 + +*END + +*D_NET chanx_right_in[16] 0.003719141 //LENGTH 34.960 LUMPCC 0 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 111.930 40.800 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 89.605 30.940 +*N chanx_right_in[16]:2 *C 89.642 30.940 +*N chanx_right_in[16]:3 *C 107.135 30.940 +*N chanx_right_in[16]:4 *C 107.180 30.985 +*N chanx_right_in[16]:5 *C 107.180 41.422 +*N chanx_right_in[16]:6 *C 107.185 41.473 +*N chanx_right_in[16]:7 *C 107.640 41.468 +*N chanx_right_in[16]:8 *C 107.640 40.800 + +*CAP +0 chanx_right_in[16] 0.000293807 +1 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[16]:2 0.0009049522 +3 chanx_right_in[16]:3 0.0009049522 +4 chanx_right_in[16]:4 0.0005425388 +5 chanx_right_in[16]:5 0.0005425388 +6 chanx_right_in[16]:6 6.605522e-05 +7 chanx_right_in[16]:7 0.0001177726 +8 chanx_right_in[16]:8 0.0003455243 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:8 0.0006721001 +1 chanx_right_in[16]:5 chanx_right_in[16]:4 0.009319198 +2 chanx_right_in[16]:6 chanx_right_in[16]:5 0.00341 +3 chanx_right_in[16]:3 chanx_right_in[16]:2 0.0156183 +4 chanx_right_in[16]:4 chanx_right_in[16]:3 0.0045 +5 chanx_right_in[16]:2 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +6 chanx_right_in[16]:7 chanx_right_in[16]:6 6.788888e-05 +7 chanx_right_in[16]:8 chanx_right_in[16]:7 0.000104575 + +*END + +*D_NET chanx_right_in[18] 0.006240784 //LENGTH 51.540 LUMPCC 0.001606655 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 111.930 39.440 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 77.185 23.460 +*N chanx_right_in[18]:2 *C 77.223 23.460 +*N chanx_right_in[18]:3 *C 79.075 23.460 +*N chanx_right_in[18]:4 *C 79.120 23.505 +*N chanx_right_in[18]:5 *C 79.120 39.383 +*N chanx_right_in[18]:6 *C 79.127 39.440 + +*CAP +0 chanx_right_in[18] 0.001332039 +1 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[18]:2 0.000132935 +3 chanx_right_in[18]:3 0.000132935 +4 chanx_right_in[18]:4 0.0008515909 +5 chanx_right_in[18]:5 0.0008515909 +6 chanx_right_in[18]:6 0.001332039 +7 chanx_right_in[18] chanx_right_in[13] 0.0001567234 +8 chanx_right_in[18] chanx_right_in[13]:7 0.0001368079 +9 chanx_right_in[18]:6 chanx_right_in[13]:6 0.0001368079 +10 chanx_right_in[18]:6 chanx_right_in[13]:7 0.0001567234 +11 chanx_right_in[18] chany_bottom_in[14]:6 0.000509796 +12 chanx_right_in[18]:6 chany_bottom_in[14]:7 0.000509796 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:6 0.005139058 +1 chanx_right_in[18]:2 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[18]:3 chanx_right_in[18]:2 0.001654018 +3 chanx_right_in[18]:4 chanx_right_in[18]:3 0.0045 +4 chanx_right_in[18]:5 chanx_right_in[18]:4 0.01417634 +5 chanx_right_in[18]:6 chanx_right_in[18]:5 0.00341 + +*END + +*D_NET chany_bottom_in[14] 0.009891812 //LENGTH 82.755 LUMPCC 0.00297914 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 43.700 1.290 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 88.165 39.100 +*N chany_bottom_in[14]:2 *C 88.165 39.100 +*N chany_bottom_in[14]:3 *C 87.860 39.100 +*N chany_bottom_in[14]:4 *C 87.860 39.100 +*N chany_bottom_in[14]:5 *C 87.860 38.760 +*N chany_bottom_in[14]:6 *C 87.853 38.760 +*N chany_bottom_in[14]:7 *C 43.708 38.760 +*N chany_bottom_in[14]:8 *C 43.700 38.703 + +*CAP +0 chany_bottom_in[14] 0.001789244 +1 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[14]:2 5.541489e-05 +3 chany_bottom_in[14]:3 5.949752e-05 +4 chany_bottom_in[14]:4 5.296303e-05 +5 chany_bottom_in[14]:5 5.713262e-05 +6 chany_bottom_in[14]:6 0.001554088 +7 chany_bottom_in[14]:7 0.001554088 +8 chany_bottom_in[14]:8 0.001789244 +9 chany_bottom_in[14]:6 chanx_right_in[13]:7 0.0005726922 +10 chany_bottom_in[14]:7 chanx_right_in[13]:6 0.0005726922 +11 chany_bottom_in[14]:6 chanx_right_in[18] 0.000509796 +12 chany_bottom_in[14]:7 chanx_right_in[18]:6 0.000509796 +13 chany_bottom_in[14]:6 chany_bottom_in[18]:6 2.262874e-05 +14 chany_bottom_in[14]:6 chany_bottom_in[18]:7 0.0002521382 +15 chany_bottom_in[14]:7 chany_bottom_in[18]:8 0.0002521382 +16 chany_bottom_in[14]:7 chany_bottom_in[18]:7 2.262874e-05 +17 chany_bottom_in[14] ropt_net_153:5 7.050472e-05 +18 chany_bottom_in[14]:8 ropt_net_153:6 7.050472e-05 +19 chany_bottom_in[14] ropt_net_129:5 6.181014e-05 +20 chany_bottom_in[14]:8 ropt_net_129:6 6.181014e-05 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:8 0.03340402 +1 chany_bottom_in[14]:2 mux_right_track_8\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[14]:3 chany_bottom_in[14]:2 0.0001657609 +3 chany_bottom_in[14]:4 chany_bottom_in[14]:3 0.0045 +4 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.0001634615 +5 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.00341 +6 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.00341 +7 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.006916049 + +*END + +*D_NET chany_bottom_in[18] 0.01230451 //LENGTH 110.265 LUMPCC 0.002124714 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 26.680 1.290 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 94.935 42.500 +*N chany_bottom_in[18]:2 *C 94.898 42.500 +*N chany_bottom_in[18]:3 *C 93.885 42.500 +*N chany_bottom_in[18]:4 *C 93.840 42.500 +*N chany_bottom_in[18]:5 *C 93.840 42.160 +*N chany_bottom_in[18]:6 *C 93.833 42.160 +*N chany_bottom_in[18]:7 *C 76.515 42.160 +*N chany_bottom_in[18]:8 *C 26.688 42.160 +*N chany_bottom_in[18]:9 *C 26.680 42.102 + +*CAP +0 chany_bottom_in[18] 0.002017745 +1 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[18]:2 0.000118534 +3 chany_bottom_in[18]:3 0.000118534 +4 chany_bottom_in[18]:4 5.166139e-05 +5 chany_bottom_in[18]:5 5.564263e-05 +6 chany_bottom_in[18]:6 0.0006348728 +7 chany_bottom_in[18]:7 0.002899469 +8 chany_bottom_in[18]:8 0.002264596 +9 chany_bottom_in[18]:9 0.002017745 +10 chany_bottom_in[18]:6 chanx_right_in[14] 0.0004288127 +11 chany_bottom_in[18]:8 chanx_right_in[14]:6 0.0003587771 +12 chany_bottom_in[18]:7 chanx_right_in[14] 0.0003587771 +13 chany_bottom_in[18]:7 chanx_right_in[14]:6 0.0004288127 +14 chany_bottom_in[18]:6 chany_bottom_in[14]:6 2.262874e-05 +15 chany_bottom_in[18]:8 chany_bottom_in[14]:7 0.0002521382 +16 chany_bottom_in[18]:7 chany_bottom_in[14]:6 0.0002521382 +17 chany_bottom_in[18]:7 chany_bottom_in[14]:7 2.262874e-05 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:9 0.03643974 +1 chany_bottom_in[18]:2 mux_right_track_0\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[18]:3 chany_bottom_in[18]:2 0.0009040179 +3 chany_bottom_in[18]:4 chany_bottom_in[18]:3 0.0045 +4 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.0001634616 +5 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.00341 +6 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.00341 +7 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.007806308 +8 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.002713075 + +*END + +*D_NET bottom_left_grid_pin_1_[0] 0.01427837 //LENGTH 121.853 LUMPCC 0.0002727934 DR + +*CONN +*P bottom_left_grid_pin_1_[0] I *L 0.29796 *C 2.300 1.290 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 61.930 15.300 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 70.555 15.300 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 77.570 22.780 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 90.010 31.620 +*N bottom_left_grid_pin_1_[0]:5 *C 89.973 31.620 +*N bottom_left_grid_pin_1_[0]:6 *C 88.825 31.620 +*N bottom_left_grid_pin_1_[0]:7 *C 88.780 31.575 +*N bottom_left_grid_pin_1_[0]:8 *C 88.780 28.945 +*N bottom_left_grid_pin_1_[0]:9 *C 88.735 28.900 +*N bottom_left_grid_pin_1_[0]:10 *C 84.225 28.900 +*N bottom_left_grid_pin_1_[0]:11 *C 84.180 28.855 +*N bottom_left_grid_pin_1_[0]:12 *C 84.180 27.925 +*N bottom_left_grid_pin_1_[0]:13 *C 84.135 27.880 +*N bottom_left_grid_pin_1_[0]:14 *C 77.785 27.880 +*N bottom_left_grid_pin_1_[0]:15 *C 77.740 27.835 +*N bottom_left_grid_pin_1_[0]:16 *C 77.570 22.780 +*N bottom_left_grid_pin_1_[0]:17 *C 77.740 22.780 +*N bottom_left_grid_pin_1_[0]:18 *C 77.740 22.780 +*N bottom_left_grid_pin_1_[0]:19 *C 77.740 15.685 +*N bottom_left_grid_pin_1_[0]:20 *C 77.695 15.640 +*N bottom_left_grid_pin_1_[0]:21 *C 70.380 15.640 +*N bottom_left_grid_pin_1_[0]:22 *C 70.430 15.323 +*N bottom_left_grid_pin_1_[0]:23 *C 70.380 15.300 +*N bottom_left_grid_pin_1_[0]:24 *C 61.930 15.300 +*N bottom_left_grid_pin_1_[0]:25 *C 59.845 15.300 +*N bottom_left_grid_pin_1_[0]:26 *C 59.800 15.255 +*N bottom_left_grid_pin_1_[0]:27 *C 59.800 8.898 +*N bottom_left_grid_pin_1_[0]:28 *C 59.793 8.840 +*N bottom_left_grid_pin_1_[0]:29 *C 52.135 8.840 +*N bottom_left_grid_pin_1_[0]:30 *C 2.308 8.840 +*N bottom_left_grid_pin_1_[0]:31 *C 2.300 8.783 + +*CAP +0 bottom_left_grid_pin_1_[0] 0.0003352171 +1 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_1_[0]:5 8.662679e-05 +6 bottom_left_grid_pin_1_[0]:6 8.662679e-05 +7 bottom_left_grid_pin_1_[0]:7 0.0001615637 +8 bottom_left_grid_pin_1_[0]:8 0.0001615637 +9 bottom_left_grid_pin_1_[0]:9 0.0003629674 +10 bottom_left_grid_pin_1_[0]:10 0.0003629674 +11 bottom_left_grid_pin_1_[0]:11 7.686419e-05 +12 bottom_left_grid_pin_1_[0]:12 7.686419e-05 +13 bottom_left_grid_pin_1_[0]:13 0.0004325967 +14 bottom_left_grid_pin_1_[0]:14 0.0004325967 +15 bottom_left_grid_pin_1_[0]:15 0.0002598468 +16 bottom_left_grid_pin_1_[0]:16 4.561193e-05 +17 bottom_left_grid_pin_1_[0]:17 5.083668e-05 +18 bottom_left_grid_pin_1_[0]:18 0.0006484428 +19 bottom_left_grid_pin_1_[0]:19 0.0003629948 +20 bottom_left_grid_pin_1_[0]:20 0.0004694014 +21 bottom_left_grid_pin_1_[0]:21 0.0004918572 +22 bottom_left_grid_pin_1_[0]:22 3.238932e-05 +23 bottom_left_grid_pin_1_[0]:23 0.0005340322 +24 bottom_left_grid_pin_1_[0]:24 0.0006910632 +25 bottom_left_grid_pin_1_[0]:25 0.0001394153 +26 bottom_left_grid_pin_1_[0]:26 0.000328996 +27 bottom_left_grid_pin_1_[0]:27 0.000328996 +28 bottom_left_grid_pin_1_[0]:28 0.0005390204 +29 bottom_left_grid_pin_1_[0]:29 0.003353011 +30 bottom_left_grid_pin_1_[0]:30 0.002813991 +31 bottom_left_grid_pin_1_[0]:31 0.0003352171 +32 bottom_left_grid_pin_1_[0]:20 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 7.030298e-05 +33 bottom_left_grid_pin_1_[0]:19 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 1.861672e-06 +34 bottom_left_grid_pin_1_[0]:18 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 1.861672e-06 +35 bottom_left_grid_pin_1_[0]:21 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 7.030298e-05 +36 bottom_left_grid_pin_1_[0]:30 ropt_net_157:5 6.423207e-05 +37 bottom_left_grid_pin_1_[0]:29 ropt_net_157:6 6.423207e-05 + +*RES +0 bottom_left_grid_pin_1_[0] bottom_left_grid_pin_1_[0]:31 0.006689732 +1 bottom_left_grid_pin_1_[0]:5 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +2 bottom_left_grid_pin_1_[0]:6 bottom_left_grid_pin_1_[0]:5 0.001024554 +3 bottom_left_grid_pin_1_[0]:7 bottom_left_grid_pin_1_[0]:6 0.0045 +4 bottom_left_grid_pin_1_[0]:9 bottom_left_grid_pin_1_[0]:8 0.0045 +5 bottom_left_grid_pin_1_[0]:8 bottom_left_grid_pin_1_[0]:7 0.002348214 +6 bottom_left_grid_pin_1_[0]:10 bottom_left_grid_pin_1_[0]:9 0.004026786 +7 bottom_left_grid_pin_1_[0]:11 bottom_left_grid_pin_1_[0]:10 0.0045 +8 bottom_left_grid_pin_1_[0]:13 bottom_left_grid_pin_1_[0]:12 0.0045 +9 bottom_left_grid_pin_1_[0]:12 bottom_left_grid_pin_1_[0]:11 0.0008303572 +10 bottom_left_grid_pin_1_[0]:14 bottom_left_grid_pin_1_[0]:13 0.005669643 +11 bottom_left_grid_pin_1_[0]:15 bottom_left_grid_pin_1_[0]:14 0.0045 +12 bottom_left_grid_pin_1_[0]:25 bottom_left_grid_pin_1_[0]:24 0.001861607 +13 bottom_left_grid_pin_1_[0]:26 bottom_left_grid_pin_1_[0]:25 0.0045 +14 bottom_left_grid_pin_1_[0]:27 bottom_left_grid_pin_1_[0]:26 0.00567634 +15 bottom_left_grid_pin_1_[0]:28 bottom_left_grid_pin_1_[0]:27 0.00341 +16 bottom_left_grid_pin_1_[0]:31 bottom_left_grid_pin_1_[0]:30 0.00341 +17 bottom_left_grid_pin_1_[0]:30 bottom_left_grid_pin_1_[0]:29 0.007806308 +18 bottom_left_grid_pin_1_[0]:20 bottom_left_grid_pin_1_[0]:19 0.0045 +19 bottom_left_grid_pin_1_[0]:19 bottom_left_grid_pin_1_[0]:18 0.006334822 +20 bottom_left_grid_pin_1_[0]:22 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +21 bottom_left_grid_pin_1_[0]:22 bottom_left_grid_pin_1_[0]:21 0.0002834821 +22 bottom_left_grid_pin_1_[0]:24 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +23 bottom_left_grid_pin_1_[0]:24 bottom_left_grid_pin_1_[0]:23 0.007544643 +24 bottom_left_grid_pin_1_[0]:17 bottom_left_grid_pin_1_[0]:16 9.239131e-05 +25 bottom_left_grid_pin_1_[0]:18 bottom_left_grid_pin_1_[0]:17 0.0045 +26 bottom_left_grid_pin_1_[0]:18 bottom_left_grid_pin_1_[0]:15 0.004513393 +27 bottom_left_grid_pin_1_[0]:16 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +28 bottom_left_grid_pin_1_[0]:23 bottom_left_grid_pin_1_[0]:22 4.464286e-05 +29 bottom_left_grid_pin_1_[0]:21 bottom_left_grid_pin_1_[0]:20 0.006531251 +30 bottom_left_grid_pin_1_[0]:29 bottom_left_grid_pin_1_[0]:28 0.001199675 + +*END + +*D_NET chany_bottom_out[2] 0.002256969 //LENGTH 16.295 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 79.525 4.080 +*P chany_bottom_out[2] O *L 0.7423 *C 66.700 1.325 +*N chany_bottom_out[2]:2 *C 66.700 3.355 +*N chany_bottom_out[2]:3 *C 66.745 3.400 +*N chany_bottom_out[2]:4 *C 78.200 3.400 +*N chany_bottom_out[2]:5 *C 78.200 4.080 +*N chany_bottom_out[2]:6 *C 79.525 4.080 + +*CAP +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[2] 0.000126741 +2 chany_bottom_out[2]:2 0.000126741 +3 chany_bottom_out[2]:3 0.0008618833 +4 chany_bottom_out[2]:4 0.0009004998 +5 chany_bottom_out[2]:5 0.0001237139 +6 chany_bottom_out[2]:6 0.0001163898 + +*RES +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[2]:6 0.152 +1 chany_bottom_out[2]:6 chany_bottom_out[2]:5 0.001183036 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +3 chany_bottom_out[2]:2 chany_bottom_out[2] 0.0018125 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.01022768 +5 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.003884435 //LENGTH 33.445 LUMPCC 0.0004282903 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 93.225 63.920 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 86.195 60.860 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 96.040 42.160 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 96.002 42.160 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 92.965 42.160 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 92.920 42.205 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 86.223 60.838 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 86.480 60.825 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 86.480 60.520 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 92.875 60.520 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 92.920 60.520 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 92.920 63.875 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 92.920 63.920 +*N mux_tree_tapbuf_size2_0_sram[0]:13 *C 93.225 63.920 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 0.0002285713 +4 mux_tree_tapbuf_size2_0_sram[0]:4 0.0002285713 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.0007895294 +6 mux_tree_tapbuf_size2_0_sram[0]:6 3.994924e-05 +7 mux_tree_tapbuf_size2_0_sram[0]:7 6.305645e-05 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0004547305 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0004316233 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0009684219 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.0001475438 +12 mux_tree_tapbuf_size2_0_sram[0]:12 5.221037e-05 +13 mux_tree_tapbuf_size2_0_sram[0]:13 4.893648e-05 +14 mux_tree_tapbuf_size2_0_sram[0]:5 chanx_right_out[4]:10 0.0001699738 +15 mux_tree_tapbuf_size2_0_sram[0]:10 chanx_right_out[4]:9 0.0001699738 +16 mux_tree_tapbuf_size2_0_sram[0]:10 chanx_right_out[4]:10 4.41714e-05 +17 mux_tree_tapbuf_size2_0_sram[0]:11 chanx_right_out[4]:9 4.41714e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 0.002712054 +2 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size2_0_sram[0]:3 mux_right_track_0\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.005709822 +5 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0045 +6 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:5 0.01635268 +7 mux_tree_tapbuf_size2_0_sram[0]:6 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.002995536 +10 mux_tree_tapbuf_size2_0_sram[0]:13 mux_tree_tapbuf_size2_0_sram[0]:12 0.0001657609 +11 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.0001739865 +12 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.00299052 //LENGTH 22.055 LUMPCC 0.0008293382 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 75.745 39.100 +*I mem_right_track_24\/FTB_4__35:A I *L 0.001746 *C 80.500 36.720 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 94.660 36.720 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 94.623 36.720 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 80.500 36.720 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 75.945 36.720 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 75.900 36.765 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 75.900 39.055 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 75.900 39.100 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 75.745 39.100 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_24\/FTB_4__35:A 1e-06 +2 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 0.0006360274 +4 mux_tree_tapbuf_size2_3_sram[1]:4 0.0009042909 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0002415329 +6 mux_tree_tapbuf_size2_3_sram[1]:6 0.0001359661 +7 mux_tree_tapbuf_size2_3_sram[1]:7 0.0001359661 +8 mux_tree_tapbuf_size2_3_sram[1]:8 5.409578e-05 +9 mux_tree_tapbuf_size2_3_sram[1]:9 5.030246e-05 +10 mux_tree_tapbuf_size2_3_sram[1]:3 chany_bottom_in[6]:2 0.0002262328 +11 mux_tree_tapbuf_size2_3_sram[1]:4 chany_bottom_in[6]:3 0.0002262328 +12 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 6.314868e-05 +13 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 6.314868e-05 +14 mux_tree_tapbuf_size2_3_sram[1]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001252876 +15 mux_tree_tapbuf_size2_3_sram[1]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001252876 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:9 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:3 mux_right_track_24\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.004066965 +3 mux_tree_tapbuf_size2_3_sram[1]:6 mux_tree_tapbuf_size2_3_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.002044643 +6 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 8.423914e-05 +7 mux_tree_tapbuf_size2_3_sram[1]:4 mem_right_track_24\/FTB_4__35:A 0.152 +8 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_3_sram[1]:3 0.01260938 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[1] 0.001772368 //LENGTH 12.390 LUMPCC 0.0001326696 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.885 11.560 +*I mem_bottom_track_25\/FTB_8__39:A I *L 0.001746 *C 68.080 9.520 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 76.260 9.520 +*N mux_tree_tapbuf_size2_7_sram[1]:3 *C 76.222 9.520 +*N mux_tree_tapbuf_size2_7_sram[1]:4 *C 71.760 9.520 +*N mux_tree_tapbuf_size2_7_sram[1]:5 *C 68.080 9.520 +*N mux_tree_tapbuf_size2_7_sram[1]:6 *C 68.080 9.180 +*N mux_tree_tapbuf_size2_7_sram[1]:7 *C 71.760 9.210 +*N mux_tree_tapbuf_size2_7_sram[1]:8 *C 71.760 9.225 +*N mux_tree_tapbuf_size2_7_sram[1]:9 *C 71.760 11.515 +*N mux_tree_tapbuf_size2_7_sram[1]:10 *C 71.760 11.560 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_25\/FTB_8__39:A 1e-06 +2 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_7_sram[1]:3 0.0003178302 +4 mux_tree_tapbuf_size2_7_sram[1]:4 0.0003461546 +5 mux_tree_tapbuf_size2_7_sram[1]:5 5.836123e-05 +6 mux_tree_tapbuf_size2_7_sram[1]:6 0.0003069728 +7 mux_tree_tapbuf_size2_7_sram[1]:7 0.0003067257 +8 mux_tree_tapbuf_size2_7_sram[1]:8 0.0001339077 +9 mux_tree_tapbuf_size2_7_sram[1]:9 0.0001339077 +10 mux_tree_tapbuf_size2_7_sram[1]:10 3.283856e-05 +11 mux_tree_tapbuf_size2_7_sram[1]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.5387e-05 +12 mux_tree_tapbuf_size2_7_sram[1]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.477848e-07 +13 mux_tree_tapbuf_size2_7_sram[1]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.477848e-07 +14 mux_tree_tapbuf_size2_7_sram[1]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.5387e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_7_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_7_sram[1]:3 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_7_sram[1]:5 mem_bottom_track_25\/FTB_8__39:A 0.152 +3 mux_tree_tapbuf_size2_7_sram[1]:7 mux_tree_tapbuf_size2_7_sram[1]:6 0.003285714 +4 mux_tree_tapbuf_size2_7_sram[1]:7 mux_tree_tapbuf_size2_7_sram[1]:4 0.0002767857 +5 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size2_7_sram[1]:10 mux_tree_tapbuf_size2_7_sram[1]:9 0.0045 +7 mux_tree_tapbuf_size2_7_sram[1]:9 mux_tree_tapbuf_size2_7_sram[1]:8 0.002044643 +8 mux_tree_tapbuf_size2_7_sram[1]:6 mux_tree_tapbuf_size2_7_sram[1]:5 0.0003035715 +9 mux_tree_tapbuf_size2_7_sram[1]:4 mux_tree_tapbuf_size2_7_sram[1]:3 0.003984375 + +*END + +*D_NET optlc_net_110 0.001295286 //LENGTH 9.730 LUMPCC 0.000129248 DR + +*CONN +*I optlc_109:HI O *L 0 *C 80.960 6.800 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 79.295 9.860 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 75.155 9.860 +*N optlc_net_110:3 *C 75.155 9.860 +*N optlc_net_110:4 *C 79.295 9.860 +*N optlc_net_110:5 *C 80.915 9.860 +*N optlc_net_110:6 *C 80.960 9.815 +*N optlc_net_110:7 *C 80.960 6.845 +*N optlc_net_110:8 *C 80.960 6.800 + +*CAP +0 optlc_109:HI 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +3 optlc_net_110:3 0.0003318756 +4 optlc_net_110:4 0.000439914 +5 optlc_net_110:5 0.0001115687 +6 optlc_net_110:6 0.000122585 +7 optlc_net_110:7 0.000122585 +8 optlc_net_110:8 3.45101e-05 +9 optlc_net_110:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.448579e-05 +10 optlc_net_110:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.381983e-07 +11 optlc_net_110:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.448579e-05 +12 optlc_net_110:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.381983e-07 + +*RES +0 optlc_109:HI optlc_net_110:8 0.152 +1 optlc_net_110:8 optlc_net_110:7 0.0045 +2 optlc_net_110:7 optlc_net_110:6 0.002651786 +3 optlc_net_110:5 optlc_net_110:4 0.001446429 +4 optlc_net_110:6 optlc_net_110:5 0.0045 +5 optlc_net_110:4 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 +6 optlc_net_110:4 optlc_net_110:3 0.003696429 +7 optlc_net_110:3 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003768631 //LENGTH 32.185 LUMPCC 0.001614577 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 88.035 31.620 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 79.220 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 79.258 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 82.295 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 82.340 9.225 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 82.340 31.575 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 82.385 31.620 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 87.998 31.620 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002145733 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002145733 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000623473 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000623473 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002379805 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002379805 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[10]:5 0.0003776047 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[10]:6 0.0003776047 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[6]:5 0.0003205895 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[6]:4 0.0003205895 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 0.0001090942 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_5_sram[0]:4 0.0001090942 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002712054 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01995536 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.005011161 + +*END + +*D_NET chany_bottom_out[6] 0.001152502 //LENGTH 7.975 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 75.440 3.740 +*P chany_bottom_out[6] O *L 0.7423 *C 70.380 1.290 +*N chany_bottom_out[6]:2 *C 70.380 3.695 +*N chany_bottom_out[6]:3 *C 70.425 3.740 +*N chany_bottom_out[6]:4 *C 75.403 3.740 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 chany_bottom_out[6] 0.0001545418 +2 chany_bottom_out[6]:2 0.0001545418 +3 chany_bottom_out[6]:3 0.000421209 +4 chany_bottom_out[6]:4 0.000421209 + +*RES +0 ropt_mt_inst_760:X chany_bottom_out[6]:4 0.152 +1 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.004444196 +2 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +3 chany_bottom_out[6]:2 chany_bottom_out[6] 0.002147322 + +*END + +*D_NET ropt_net_144 0.0007715172 //LENGTH 5.365 LUMPCC 0.0001090141 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 76.555 6.120 +*I ropt_mt_inst_760:A I *L 0.001767 *C 74.520 4.080 +*N ropt_net_144:2 *C 74.520 4.080 +*N ropt_net_144:3 *C 74.520 4.420 +*N ropt_net_144:4 *C 76.775 4.420 +*N ropt_net_144:5 *C 76.820 4.465 +*N ropt_net_144:6 *C 76.820 6.075 +*N ropt_net_144:7 *C 76.820 6.120 +*N ropt_net_144:8 *C 76.555 6.120 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 ropt_mt_inst_760:A 1e-06 +2 ropt_net_144:2 5.526197e-05 +3 ropt_net_144:3 0.0001783056 +4 ropt_net_144:4 0.0001511211 +5 ropt_net_144:5 7.93703e-05 +6 ropt_net_144:6 7.93703e-05 +7 ropt_net_144:7 5.689492e-05 +8 ropt_net_144:8 6.01789e-05 +9 ropt_net_144:6 chany_bottom_in[2]:17 5.450706e-05 +10 ropt_net_144:5 chany_bottom_in[2]:18 5.450706e-05 + +*RES +0 ropt_mt_inst_730:X ropt_net_144:8 0.152 +1 ropt_net_144:8 ropt_net_144:7 0.0001440218 +2 ropt_net_144:7 ropt_net_144:6 0.0045 +3 ropt_net_144:6 ropt_net_144:5 0.0014375 +4 ropt_net_144:4 ropt_net_144:3 0.002013393 +5 ropt_net_144:5 ropt_net_144:4 0.0045 +6 ropt_net_144:2 ropt_mt_inst_760:A 0.152 +7 ropt_net_144:3 ropt_net_144:2 0.0003035715 + +*END + +*D_NET ropt_net_164 0.0008445399 //LENGTH 6.650 LUMPCC 0.0002260174 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 102.580 89.080 +*I ropt_mt_inst_780:A I *L 0.001766 *C 106.260 91.120 +*N ropt_net_164:2 *C 106.223 91.120 +*N ropt_net_164:3 *C 104.465 91.120 +*N ropt_net_164:4 *C 104.420 91.075 +*N ropt_net_164:5 *C 104.420 89.125 +*N ropt_net_164:6 *C 104.375 89.080 +*N ropt_net_164:7 *C 102.618 89.080 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 ropt_mt_inst_780:A 1e-06 +2 ropt_net_164:2 8.338509e-05 +3 ropt_net_164:3 8.338509e-05 +4 ropt_net_164:4 0.0001194498 +5 ropt_net_164:5 0.0001194498 +6 ropt_net_164:6 0.0001054263 +7 ropt_net_164:7 0.0001054263 +8 ropt_net_164:5 ropt_net_165:3 4.847791e-06 +9 ropt_net_164:3 ropt_net_165:6 3.758945e-05 +10 ropt_net_164:4 ropt_net_165:4 4.847791e-06 +11 ropt_net_164:2 ropt_net_165:5 3.758945e-05 +12 ropt_net_164:7 ropt_net_135:7 6.870177e-05 +13 ropt_net_164:6 ropt_net_135:6 6.870177e-05 +14 ropt_net_164:5 ropt_net_135:5 1.869703e-06 +15 ropt_net_164:4 ropt_net_135:4 1.869703e-06 + +*RES +0 ropt_mt_inst_737:X ropt_net_164:7 0.152 +1 ropt_net_164:7 ropt_net_164:6 0.001569197 +2 ropt_net_164:6 ropt_net_164:5 0.0045 +3 ropt_net_164:5 ropt_net_164:4 0.001741072 +4 ropt_net_164:3 ropt_net_164:2 0.001569197 +5 ropt_net_164:4 ropt_net_164:3 0.0045 +6 ropt_net_164:2 ropt_mt_inst_780:A 0.152 + +*END + +*D_NET ropt_net_147 0.0001576774 //LENGTH 0.935 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 45.785 6.800 +*I ropt_mt_inst_763:A I *L 0.001767 *C 46.460 6.800 +*N ropt_net_147:2 *C 46.422 6.800 +*N ropt_net_147:3 *C 45.785 6.800 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_147:2 5.98014e-05 +3 ropt_net_147:3 9.587598e-05 + +*RES +0 ropt_mt_inst_745:X ropt_net_147:3 0.152 +1 ropt_net_147:2 ropt_mt_inst_763:A 0.152 +2 ropt_net_147:3 ropt_net_147:2 0.0005691964 + +*END + +*D_NET ropt_net_162 0.001657054 //LENGTH 12.450 LUMPCC 0.0004847581 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 102.580 85.340 +*I ropt_mt_inst_778:A I *L 0.001766 *C 106.260 80.240 +*N ropt_net_162:2 *C 106.223 80.240 +*N ropt_net_162:3 *C 105.845 80.240 +*N ropt_net_162:4 *C 105.800 80.285 +*N ropt_net_162:5 *C 105.800 86.303 +*N ropt_net_162:6 *C 105.793 86.360 +*N ropt_net_162:7 *C 103.047 86.360 +*N ropt_net_162:8 *C 103.040 86.303 +*N ropt_net_162:9 *C 103.040 85.385 +*N ropt_net_162:10 *C 102.995 85.340 +*N ropt_net_162:11 *C 102.618 85.340 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 ropt_mt_inst_778:A 1e-06 +2 ropt_net_162:2 4.630119e-05 +3 ropt_net_162:3 4.630119e-05 +4 ropt_net_162:4 0.0003089351 +5 ropt_net_162:5 0.0003089351 +6 ropt_net_162:6 9.6387e-05 +7 ropt_net_162:7 9.6387e-05 +8 ropt_net_162:8 7.912214e-05 +9 ropt_net_162:9 7.912214e-05 +10 ropt_net_162:10 5.440242e-05 +11 ropt_net_162:11 5.440242e-05 +12 ropt_net_162:6 chanx_right_in[0] 0.0001671938 +13 ropt_net_162:7 chanx_right_in[0]:9 0.0001671938 +14 ropt_net_162:4 ropt_net_156:5 2.226213e-05 +15 ropt_net_162:5 ropt_net_156:4 2.226213e-05 +16 ropt_net_162:6 ropt_net_156:6 4.795202e-05 +17 ropt_net_162:8 ropt_net_156:4 4.971122e-06 +18 ropt_net_162:7 ropt_net_156:7 4.795202e-05 +19 ropt_net_162:9 ropt_net_156:5 4.971122e-06 + +*RES +0 ropt_mt_inst_748:X ropt_net_162:11 0.152 +1 ropt_net_162:2 ropt_mt_inst_778:A 0.152 +2 ropt_net_162:3 ropt_net_162:2 0.0003370536 +3 ropt_net_162:4 ropt_net_162:3 0.0045 +4 ropt_net_162:5 ropt_net_162:4 0.005372768 +5 ropt_net_162:6 ropt_net_162:5 0.00341 +6 ropt_net_162:8 ropt_net_162:7 0.00341 +7 ropt_net_162:7 ropt_net_162:6 0.0004300499 +8 ropt_net_162:10 ropt_net_162:9 0.0045 +9 ropt_net_162:9 ropt_net_162:8 0.0008191965 +10 ropt_net_162:11 ropt_net_162:10 0.0003370536 + +*END + +*D_NET chanx_right_out[10] 0.0006819308 //LENGTH 5.520 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 110.135 52.360 +*P chanx_right_out[10] O *L 0.7423 *C 111.930 51.680 +*N chanx_right_out[10]:2 *C 109.028 51.680 +*N chanx_right_out[10]:3 *C 109.020 51.738 +*N chanx_right_out[10]:4 *C 109.020 52.315 +*N chanx_right_out[10]:5 *C 109.065 52.360 +*N chanx_right_out[10]:6 *C 110.098 52.360 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 chanx_right_out[10] 0.0001994876 +2 chanx_right_out[10]:2 0.0001994876 +3 chanx_right_out[10]:3 5.060752e-05 +4 chanx_right_out[10]:4 5.060752e-05 +5 chanx_right_out[10]:5 9.037033e-05 +6 chanx_right_out[10]:6 9.037033e-05 + +*RES +0 ropt_mt_inst_766:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:6 chanx_right_out[10]:5 0.0009218751 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.000515625 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.000454725 + +*END + +*D_NET chanx_right_out[11] 0.0009692379 //LENGTH 8.525 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 107.180 71.400 +*P chanx_right_out[11] O *L 0.7423 *C 111.930 69.360 +*N chanx_right_out[11]:2 *C 106.728 69.360 +*N chanx_right_out[11]:3 *C 106.720 69.418 +*N chanx_right_out[11]:4 *C 106.720 71.355 +*N chanx_right_out[11]:5 *C 106.765 71.400 +*N chanx_right_out[11]:6 *C 107.142 71.400 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 chanx_right_out[11] 0.0003140557 +2 chanx_right_out[11]:2 0.0003140557 +3 chanx_right_out[11]:3 0.0001222646 +4 chanx_right_out[11]:4 0.0001222646 +5 chanx_right_out[11]:5 4.779863e-05 +6 chanx_right_out[11]:6 4.779863e-05 + +*RES +0 ropt_mt_inst_768:X chanx_right_out[11]:6 0.152 +1 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0003370536 +2 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +3 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001729911 +4 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +5 chanx_right_out[11]:2 chanx_right_out[11] 0.0008150582 + +*END + +*D_NET ropt_net_154 0.001546104 //LENGTH 9.780 LUMPCC 0.0006578079 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 110.135 95.880 +*I ropt_mt_inst_770:A I *L 0.001767 *C 101.660 96.560 +*N ropt_net_154:2 *C 101.660 96.560 +*N ropt_net_154:3 *C 101.660 96.515 +*N ropt_net_154:4 *C 101.660 95.925 +*N ropt_net_154:5 *C 101.705 95.880 +*N ropt_net_154:6 *C 110.098 95.880 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_154:2 3.582427e-05 +3 ropt_net_154:3 5.175987e-05 +4 ropt_net_154:4 5.175987e-05 +5 ropt_net_154:5 0.000373476 +6 ropt_net_154:6 0.000373476 +7 ropt_net_154:5 ccff_head[0]:6 0.000328904 +8 ropt_net_154:6 ccff_head[0]:7 0.000328904 + +*RES +0 ropt_mt_inst_754:X ropt_net_154:6 0.152 +1 ropt_net_154:2 ropt_mt_inst_770:A 0.152 +2 ropt_net_154:3 ropt_net_154:2 0.0045 +3 ropt_net_154:5 ropt_net_154:4 0.0045 +4 ropt_net_154:4 ropt_net_154:3 0.0005267857 +5 ropt_net_154:6 ropt_net_154:5 0.007493304 + +*END + +*D_NET chanx_right_out[5] 0.00207533 //LENGTH 12.500 LUMPCC 0.001005899 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 102.580 97.240 +*P chanx_right_out[5] O *L 0.7423 *C 111.930 95.200 +*N chanx_right_out[5]:2 *C 108.100 95.200 +*N chanx_right_out[5]:3 *C 108.100 95.880 +*N chanx_right_out[5]:4 *C 102.588 95.880 +*N chanx_right_out[5]:5 *C 102.580 95.938 +*N chanx_right_out[5]:6 *C 102.580 97.195 +*N chanx_right_out[5]:7 *C 102.580 97.240 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 chanx_right_out[5] 0.0001287517 +2 chanx_right_out[5]:2 0.0001551876 +3 chanx_right_out[5]:3 0.0003046872 +4 chanx_right_out[5]:4 0.0002782513 +5 chanx_right_out[5]:5 8.601049e-05 +6 chanx_right_out[5]:6 8.601049e-05 +7 chanx_right_out[5]:7 2.953159e-05 +8 chanx_right_out[5] chanx_right_in[3] 9.06049e-05 +9 chanx_right_out[5]:4 chanx_right_in[3]:11 0.0003239686 +10 chanx_right_out[5]:3 chanx_right_in[3] 0.0003239686 +11 chanx_right_out[5]:2 chanx_right_in[3]:11 9.06049e-05 +12 chanx_right_out[5] ropt_net_149:6 5.365479e-05 +13 chanx_right_out[5]:6 ropt_net_149:3 9.656754e-07 +14 chanx_right_out[5]:5 ropt_net_149:4 9.656754e-07 +15 chanx_right_out[5]:4 ropt_net_149:5 1.396211e-05 +16 chanx_right_out[5]:3 ropt_net_149:6 1.396211e-05 +17 chanx_right_out[5]:3 ropt_net_149:3 1.97936e-05 +18 chanx_right_out[5]:2 ropt_net_149:4 1.97936e-05 +19 chanx_right_out[5]:2 ropt_net_149:5 5.365479e-05 + +*RES +0 ropt_mt_inst_770:X chanx_right_out[5]:7 0.152 +1 chanx_right_out[5]:7 chanx_right_out[5]:6 0.0045 +2 chanx_right_out[5]:6 chanx_right_out[5]:5 0.001122768 +3 chanx_right_out[5]:5 chanx_right_out[5]:4 0.00341 +4 chanx_right_out[5]:4 chanx_right_out[5]:3 0.000863625 +5 chanx_right_out[5]:3 chanx_right_out[5]:2 0.0001065333 +6 chanx_right_out[5]:2 chanx_right_out[5] 0.0006000333 + +*END + +*D_NET chany_bottom_out[17] 0.001421552 //LENGTH 10.510 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 49.875 8.840 +*P chany_bottom_out[17] O *L 0.7423 *C 47.380 1.290 +*N chany_bottom_out[17]:2 *C 47.380 8.795 +*N chany_bottom_out[17]:3 *C 47.425 8.840 +*N chany_bottom_out[17]:4 *C 49.838 8.840 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 chany_bottom_out[17] 0.0004965048 +2 chany_bottom_out[17]:2 0.0004965048 +3 chany_bottom_out[17]:3 0.0002137714 +4 chany_bottom_out[17]:4 0.0002137714 + +*RES +0 ropt_mt_inst_773:X chany_bottom_out[17]:4 0.152 +1 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.002154018 +2 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0045 +3 chany_bottom_out[17]:2 chany_bottom_out[17] 0.006700893 + +*END + +*D_NET BUF_net_64 0.001399913 //LENGTH 13.085 LUMPCC 0 DR + +*CONN +*I BUFT_RR_64:X O *L 0 *C 98.440 34.340 +*I BUFT_P_105:A I *L 0.001766 *C 105.800 39.440 +*N BUF_net_64:2 *C 105.800 39.440 +*N BUF_net_64:3 *C 105.800 39.395 +*N BUF_net_64:4 *C 105.800 34.385 +*N BUF_net_64:5 *C 105.755 34.340 +*N BUF_net_64:6 *C 98.478 34.340 + +*CAP +0 BUFT_RR_64:X 1e-06 +1 BUFT_P_105:A 1e-06 +2 BUF_net_64:2 3.029433e-05 +3 BUF_net_64:3 0.0002751218 +4 BUF_net_64:4 0.0002751218 +5 BUF_net_64:5 0.0004086875 +6 BUF_net_64:6 0.0004086875 + +*RES +0 BUFT_RR_64:X BUF_net_64:6 0.152 +1 BUF_net_64:2 BUFT_P_105:A 0.152 +2 BUF_net_64:3 BUF_net_64:2 0.0045 +3 BUF_net_64:5 BUF_net_64:4 0.0045 +4 BUF_net_64:4 BUF_net_64:3 0.004473215 +5 BUF_net_64:6 BUF_net_64:5 0.006497768 + +*END + +*D_NET BUF_net_67 0.001678228 //LENGTH 14.265 LUMPCC 0.000163757 DR + +*CONN +*I BUFT_RR_67:X O *L 0 *C 95.220 74.460 +*I BUFT_P_106:A I *L 0.001766 *C 105.800 77.520 +*N BUF_net_67:2 *C 105.800 77.520 +*N BUF_net_67:3 *C 105.800 77.475 +*N BUF_net_67:4 *C 105.800 74.505 +*N BUF_net_67:5 *C 105.755 74.460 +*N BUF_net_67:6 *C 95.258 74.460 + +*CAP +0 BUFT_RR_67:X 1e-06 +1 BUFT_P_106:A 1e-06 +2 BUF_net_67:2 3.299061e-05 +3 BUF_net_67:3 0.0001720644 +4 BUF_net_67:4 0.0001720644 +5 BUF_net_67:5 0.0005676757 +6 BUF_net_67:6 0.0005676757 +7 BUF_net_67:5 chany_bottom_in[15]:11 4.160986e-05 +8 BUF_net_67:5 chany_bottom_in[15]:13 4.026866e-05 +9 BUF_net_67:6 chany_bottom_in[15]:12 4.160986e-05 +10 BUF_net_67:6 chany_bottom_in[15]:14 4.026866e-05 + +*RES +0 BUFT_RR_67:X BUF_net_67:6 0.152 +1 BUF_net_67:2 BUFT_P_106:A 0.152 +2 BUF_net_67:3 BUF_net_67:2 0.0045 +3 BUF_net_67:5 BUF_net_67:4 0.0045 +4 BUF_net_67:4 BUF_net_67:3 0.002651786 +5 BUF_net_67:6 BUF_net_67:5 0.009372768 + +*END + +*D_NET chany_bottom_out[1] 0.0008929143 //LENGTH 8.030 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 36.535 6.120 +*P chany_bottom_out[1] O *L 0.7423 *C 34.500 1.290 +*N chany_bottom_out[1]:2 *C 34.500 1.983 +*N chany_bottom_out[1]:3 *C 34.508 2.040 +*N chany_bottom_out[1]:4 *C 35.413 2.040 +*N chany_bottom_out[1]:5 *C 35.420 2.098 +*N chany_bottom_out[1]:6 *C 35.420 6.075 +*N chany_bottom_out[1]:7 *C 35.465 6.120 +*N chany_bottom_out[1]:8 *C 36.498 6.120 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 chany_bottom_out[1] 4.810456e-05 +2 chany_bottom_out[1]:2 4.810456e-05 +3 chany_bottom_out[1]:3 8.501684e-05 +4 chany_bottom_out[1]:4 8.501684e-05 +5 chany_bottom_out[1]:5 0.0002247716 +6 chany_bottom_out[1]:6 0.0002247716 +7 chany_bottom_out[1]:7 8.806413e-05 +8 chany_bottom_out[1]:8 8.806413e-05 + +*RES +0 ropt_mt_inst_779:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0009218751 +2 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +3 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.003551339 +4 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.00341 +5 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.0001417833 +6 chany_bottom_out[1]:2 chany_bottom_out[1] 0.0006183035 +7 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.00341 + +*END + +*D_NET chanx_right_out[18] 0.0007871123 //LENGTH 6.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 110.135 85.680 +*P chanx_right_out[18] O *L 0.7423 *C 111.930 89.760 +*N chanx_right_out[18]:2 *C 110.868 89.760 +*N chanx_right_out[18]:3 *C 110.860 89.703 +*N chanx_right_out[18]:4 *C 110.860 85.725 +*N chanx_right_out[18]:5 *C 110.815 85.680 +*N chanx_right_out[18]:6 *C 110.172 85.680 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 chanx_right_out[18] 8.947701e-05 +2 chanx_right_out[18]:2 8.947701e-05 +3 chanx_right_out[18]:3 0.0002395097 +4 chanx_right_out[18]:4 0.0002395097 +5 chanx_right_out[18]:5 6.406944e-05 +6 chanx_right_out[18]:6 6.406944e-05 + +*RES +0 ropt_mt_inst_781:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0005736608 +2 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.003551339 +4 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +5 chanx_right_out[18]:2 chanx_right_out[18] 0.0001664583 + +*END + +*D_NET chanx_right_out[9] 0.0005677964 //LENGTH 4.650 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 110.135 42.840 +*P chanx_right_out[9] O *L 0.7423 *C 111.930 44.880 +*N chanx_right_out[9]:2 *C 110.868 44.880 +*N chanx_right_out[9]:3 *C 110.860 44.823 +*N chanx_right_out[9]:4 *C 110.860 42.885 +*N chanx_right_out[9]:5 *C 110.815 42.840 +*N chanx_right_out[9]:6 *C 110.172 42.840 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 chanx_right_out[9] 8.935653e-05 +2 chanx_right_out[9]:2 8.935653e-05 +3 chanx_right_out[9]:3 0.0001312828 +4 chanx_right_out[9]:4 0.0001312828 +5 chanx_right_out[9]:5 6.275891e-05 +6 chanx_right_out[9]:6 6.275891e-05 + +*RES +0 ropt_mt_inst_783:X chanx_right_out[9]:6 0.152 +1 chanx_right_out[9]:6 chanx_right_out[9]:5 0.0005736608 +2 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0045 +3 chanx_right_out[9]:4 chanx_right_out[9]:3 0.001729911 +4 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +5 chanx_right_out[9]:2 chanx_right_out[9] 0.0001664583 + +*END + +*D_NET ropt_net_142 0.002188581 //LENGTH 15.115 LUMPCC 0.0008049682 DR + +*CONN +*I BUFT_RR_78:X O *L 0 *C 36.605 9.520 +*I ropt_mt_inst_758:A I *L 0.001766 *C 50.600 9.520 +*N ropt_net_142:2 *C 50.562 9.520 +*N ropt_net_142:3 *C 49.680 9.520 +*N ropt_net_142:4 *C 49.680 9.860 +*N ropt_net_142:5 *C 36.800 9.860 +*N ropt_net_142:6 *C 36.605 9.520 + +*CAP +0 BUFT_RR_78:X 1e-06 +1 ropt_mt_inst_758:A 1e-06 +2 ropt_net_142:2 2.961927e-05 +3 ropt_net_142:3 5.623391e-05 +4 ropt_net_142:4 0.000621875 +5 ropt_net_142:5 0.0006201093 +6 ropt_net_142:6 5.377507e-05 +7 ropt_net_142:2 chanx_right_in[15]:7 1.620068e-05 +8 ropt_net_142:5 chanx_right_in[15]:2 0.0001300652 +9 ropt_net_142:5 chanx_right_in[15]:6 0.0001895609 +10 ropt_net_142:4 chanx_right_in[15]:3 0.0001300652 +11 ropt_net_142:4 chanx_right_in[15]:7 0.0001895609 +12 ropt_net_142:3 chanx_right_in[15]:6 1.620068e-05 +13 ropt_net_142:2 chany_bottom_out[4]:3 3.307888e-05 +14 ropt_net_142:5 chany_bottom_out[4]:4 3.357845e-05 +15 ropt_net_142:4 chany_bottom_out[4]:3 3.357845e-05 +16 ropt_net_142:3 chany_bottom_out[4]:4 3.307888e-05 + +*RES +0 BUFT_RR_78:X ropt_net_142:6 0.152 +1 ropt_net_142:6 ropt_net_142:5 0.0003035715 +2 ropt_net_142:2 ropt_mt_inst_758:A 0.152 +3 ropt_net_142:5 ropt_net_142:4 0.0115 +4 ropt_net_142:4 ropt_net_142:3 0.0003035714 +5 ropt_net_142:3 ropt_net_142:2 0.0007879465 + +*END + +*D_NET chany_bottom_out[16] 0.0005606466 //LENGTH 4.440 LUMPCC 0 DR + +*CONN +*I BUFT_P_92:X O *L 0 *C 29.705 4.080 +*P chany_bottom_out[16] O *L 0.7423 *C 28.520 1.290 +*N chany_bottom_out[16]:2 *C 28.520 4.035 +*N chany_bottom_out[16]:3 *C 28.565 4.080 +*N chany_bottom_out[16]:4 *C 29.668 4.080 + +*CAP +0 BUFT_P_92:X 1e-06 +1 chany_bottom_out[16] 0.0001678545 +2 chany_bottom_out[16]:2 0.0001678545 +3 chany_bottom_out[16]:3 0.0001119688 +4 chany_bottom_out[16]:4 0.0001119688 + +*RES +0 BUFT_P_92:X chany_bottom_out[16]:4 0.152 +1 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.000984375 +2 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0045 +3 chany_bottom_out[16]:2 chany_bottom_out[16] 0.002450893 + +*END + +*D_NET chany_bottom_out[18] 0.001186511 //LENGTH 10.640 LUMPCC 0 DR + +*CONN +*I BUFT_P_99:X O *L 0 *C 22.345 9.180 +*P chany_bottom_out[18] O *L 0.7423 *C 23.920 1.285 +*N chany_bottom_out[18]:2 *C 23.920 6.113 +*N chany_bottom_out[18]:3 *C 23.900 6.120 +*N chany_bottom_out[18]:4 *C 23.008 6.120 +*N chany_bottom_out[18]:5 *C 23.000 6.178 +*N chany_bottom_out[18]:6 *C 23.000 9.135 +*N chany_bottom_out[18]:7 *C 22.955 9.180 +*N chany_bottom_out[18]:8 *C 22.383 9.180 + +*CAP +0 BUFT_P_99:X 1e-06 +1 chany_bottom_out[18] 0.0002761717 +2 chany_bottom_out[18]:2 0.0002761717 +3 chany_bottom_out[18]:3 7.230729e-05 +4 chany_bottom_out[18]:4 7.230729e-05 +5 chany_bottom_out[18]:5 0.0001884062 +6 chany_bottom_out[18]:6 0.0001884062 +7 chany_bottom_out[18]:7 5.587013e-05 +8 chany_bottom_out[18]:8 5.587013e-05 + +*RES +0 BUFT_P_99:X chany_bottom_out[18]:8 0.152 +1 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.00341 +2 chany_bottom_out[18]:2 chany_bottom_out[18] 0.0007563083 +3 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.00341 +4 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.000139825 +5 chany_bottom_out[18]:7 chany_bottom_out[18]:6 0.0045 +6 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.002640625 +7 chany_bottom_out[18]:8 chany_bottom_out[18]:7 0.0005111607 + +*END + +*D_NET ropt_net_149 0.003006207 //LENGTH 26.410 LUMPCC 0.0004751489 DR + +*CONN +*I BUFT_P_106:X O *L 0 *C 109.675 77.860 +*I ropt_mt_inst_765:A I *L 0.001766 *C 106.260 99.280 +*N ropt_net_149:2 *C 106.260 99.280 +*N ropt_net_149:3 *C 106.260 99.235 +*N ropt_net_149:4 *C 106.260 93.898 +*N ropt_net_149:5 *C 106.267 93.840 +*N ropt_net_149:6 *C 109.933 93.840 +*N ropt_net_149:7 *C 109.940 93.782 +*N ropt_net_149:8 *C 109.940 77.905 +*N ropt_net_149:9 *C 109.940 77.860 +*N ropt_net_149:10 *C 109.675 77.860 + +*CAP +0 BUFT_P_106:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_149:2 2.624745e-05 +3 ropt_net_149:3 0.0002578586 +4 ropt_net_149:4 0.0002578586 +5 ropt_net_149:5 0.0001794918 +6 ropt_net_149:6 0.0001794918 +7 ropt_net_149:7 0.000764069 +8 ropt_net_149:8 0.000764069 +9 ropt_net_149:9 5.01611e-05 +10 ropt_net_149:10 4.981072e-05 +11 ropt_net_149:8 chany_bottom_in[12]:7 8.837232e-05 +12 ropt_net_149:7 chany_bottom_in[12]:6 8.837232e-05 +13 ropt_net_149:6 chanx_right_out[5] 5.365479e-05 +14 ropt_net_149:6 chanx_right_out[5]:3 1.396211e-05 +15 ropt_net_149:4 chanx_right_out[5]:2 1.97936e-05 +16 ropt_net_149:4 chanx_right_out[5]:5 9.656754e-07 +17 ropt_net_149:5 chanx_right_out[5]:2 5.365479e-05 +18 ropt_net_149:5 chanx_right_out[5]:4 1.396211e-05 +19 ropt_net_149:3 chanx_right_out[5]:3 1.97936e-05 +20 ropt_net_149:3 chanx_right_out[5]:6 9.656754e-07 +21 ropt_net_149:4 ropt_net_138:5 6.082595e-05 +22 ropt_net_149:3 ropt_net_138:4 6.082595e-05 + +*RES +0 BUFT_P_106:X ropt_net_149:10 0.152 +1 ropt_net_149:10 ropt_net_149:9 0.0001440218 +2 ropt_net_149:9 ropt_net_149:8 0.0045 +3 ropt_net_149:8 ropt_net_149:7 0.01417634 +4 ropt_net_149:7 ropt_net_149:6 0.00341 +5 ropt_net_149:6 ropt_net_149:5 0.0005741833 +6 ropt_net_149:4 ropt_net_149:3 0.004765625 +7 ropt_net_149:5 ropt_net_149:4 0.00341 +8 ropt_net_149:2 ropt_mt_inst_765:A 0.152 +9 ropt_net_149:3 ropt_net_149:2 0.0045 + +*END + +*D_NET chanx_right_in[8] 0.01495989 //LENGTH 139.640 LUMPCC 0.001836769 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 111.930 77.520 +*I BUFT_P_94:A I *L 0.001776 *C 40.480 12.240 +*N chanx_right_in[8]:2 *C 40.480 12.240 +*N chanx_right_in[8]:3 *C 40.480 12.580 +*N chanx_right_in[8]:4 *C 56.995 12.580 +*N chanx_right_in[8]:5 *C 57.040 12.625 +*N chanx_right_in[8]:6 *C 57.040 14.915 +*N chanx_right_in[8]:7 *C 57.085 14.960 +*N chanx_right_in[8]:8 *C 58.375 14.960 +*N chanx_right_in[8]:9 *C 58.420 15.005 +*N chanx_right_in[8]:10 *C 58.420 52.995 +*N chanx_right_in[8]:11 *C 58.465 53.040 +*N chanx_right_in[8]:12 *C 68.855 53.040 +*N chanx_right_in[8]:13 *C 68.855 53.040 +*N chanx_right_in[8]:14 *C 68.862 53.040 +*N chanx_right_in[8]:15 *C 71.398 53.040 +*N chanx_right_in[8]:16 *C 71.405 53.040 +*N chanx_right_in[8]:17 *C 71.450 53.040 +*N chanx_right_in[8]:18 *C 75.855 53.040 +*N chanx_right_in[8]:19 *C 75.900 53.085 +*N chanx_right_in[8]:20 *C 75.900 77.463 +*N chanx_right_in[8]:21 *C 75.907 77.520 + +*CAP +0 chanx_right_in[8] 0.001280887 +1 BUFT_P_94:A 1e-06 +2 chanx_right_in[8]:2 5.811139e-05 +3 chanx_right_in[8]:3 0.0009953906 +4 chanx_right_in[8]:4 0.0009669474 +5 chanx_right_in[8]:5 0.000136719 +6 chanx_right_in[8]:6 0.000136719 +7 chanx_right_in[8]:7 6.255254e-05 +8 chanx_right_in[8]:8 6.255254e-05 +9 chanx_right_in[8]:9 0.001842933 +10 chanx_right_in[8]:10 0.001842933 +11 chanx_right_in[8]:11 0.0005457881 +12 chanx_right_in[8]:12 0.0005752032 +13 chanx_right_in[8]:13 3.1467e-05 +14 chanx_right_in[8]:14 0.0002762116 +15 chanx_right_in[8]:15 0.0002762116 +16 chanx_right_in[8]:16 3.1467e-05 +17 chanx_right_in[8]:17 0.0002474898 +18 chanx_right_in[8]:18 0.0002474898 +19 chanx_right_in[8]:19 0.001112081 +20 chanx_right_in[8]:20 0.001112081 +21 chanx_right_in[8]:21 0.001280887 +22 chanx_right_in[8] chanx_right_in[10] 0.0002689404 +23 chanx_right_in[8]:21 chanx_right_in[10]:8 0.0002689404 +24 chanx_right_in[8] chanx_right_in[12] 0.0004121939 +25 chanx_right_in[8]:20 chanx_right_in[12]:10 7.744887e-05 +26 chanx_right_in[8]:21 chanx_right_in[12]:11 0.0004121939 +27 chanx_right_in[8]:19 chanx_right_in[12]:9 7.744887e-05 +28 chanx_right_in[8]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.362263e-05 +29 chanx_right_in[8]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.362263e-05 +30 chanx_right_in[8]:4 BUF_net_48:3 9.617864e-05 +31 chanx_right_in[8]:3 BUF_net_48:2 9.617864e-05 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:21 0.005643524 +1 chanx_right_in[8]:20 chanx_right_in[8]:19 0.02176563 +2 chanx_right_in[8]:21 chanx_right_in[8]:20 0.00341 +3 chanx_right_in[8]:18 chanx_right_in[8]:17 0.003933036 +4 chanx_right_in[8]:19 chanx_right_in[8]:18 0.0045 +5 chanx_right_in[8]:17 chanx_right_in[8]:16 0.0045 +6 chanx_right_in[8]:16 chanx_right_in[8]:15 0.00341 +7 chanx_right_in[8]:15 chanx_right_in[8]:14 0.00039715 +8 chanx_right_in[8]:13 chanx_right_in[8]:12 0.0045 +9 chanx_right_in[8]:14 chanx_right_in[8]:13 0.00341 +10 chanx_right_in[8]:12 chanx_right_in[8]:11 0.009276786 +11 chanx_right_in[8]:11 chanx_right_in[8]:10 0.0045 +12 chanx_right_in[8]:10 chanx_right_in[8]:9 0.03391965 +13 chanx_right_in[8]:8 chanx_right_in[8]:7 0.001151786 +14 chanx_right_in[8]:9 chanx_right_in[8]:8 0.0045 +15 chanx_right_in[8]:7 chanx_right_in[8]:6 0.0045 +16 chanx_right_in[8]:6 chanx_right_in[8]:5 0.002044643 +17 chanx_right_in[8]:4 chanx_right_in[8]:3 0.01474554 +18 chanx_right_in[8]:5 chanx_right_in[8]:4 0.0045 +19 chanx_right_in[8]:2 BUFT_P_94:A 0.152 +20 chanx_right_in[8]:3 chanx_right_in[8]:2 0.0003035715 + +*END + +*D_NET chanx_right_out[2] 0.001223014 //LENGTH 10.620 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 104.880 50.320 +*P chanx_right_out[2] O *L 0.7423 *C 111.855 53.040 +*N chanx_right_out[2]:2 *C 106.267 53.040 +*N chanx_right_out[2]:3 *C 106.260 52.983 +*N chanx_right_out[2]:4 *C 106.260 50.320 +*N chanx_right_out[2]:5 *C 105.800 50.320 +*N chanx_right_out[2]:6 *C 105.755 50.320 +*N chanx_right_out[2]:7 *C 104.918 50.320 + +*CAP +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[2] 0.0003463285 +2 chanx_right_out[2]:2 0.0003463285 +3 chanx_right_out[2]:3 0.0001594816 +4 chanx_right_out[2]:4 0.0001880673 +5 chanx_right_out[2]:5 5.497872e-05 +6 chanx_right_out[2]:6 6.341471e-05 +7 chanx_right_out[2]:7 6.341471e-05 + +*RES +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[2]:7 0.152 +1 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +2 chanx_right_out[2]:2 chanx_right_out[2] 0.000875375 +3 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0045 +4 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0004107143 +5 chanx_right_out[2]:7 chanx_right_out[2]:6 0.0007477679 +6 chanx_right_out[2]:4 chanx_right_out[2]:3 0.002377232 + +*END + +*D_NET chanx_right_out[12] 0.00210008 //LENGTH 18.900 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 98.960 37.060 +*P chanx_right_out[12] O *L 0.7423 *C 111.863 42.160 +*N chanx_right_out[12]:2 *C 111.780 42.160 +*N chanx_right_out[12]:3 *C 111.780 42.102 +*N chanx_right_out[12]:4 *C 111.780 37.105 +*N chanx_right_out[12]:5 *C 111.735 37.060 +*N chanx_right_out[12]:6 *C 98.998 37.060 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 3.042144e-05 +2 chanx_right_out[12]:2 3.042144e-05 +3 chanx_right_out[12]:3 0.0002623512 +4 chanx_right_out[12]:4 0.0002623512 +5 chanx_right_out[12]:5 0.0007567672 +6 chanx_right_out[12]:6 0.0007567672 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:6 0.152 +1 chanx_right_out[12]:6 chanx_right_out[12]:5 0.01137277 +2 chanx_right_out[12]:5 chanx_right_out[12]:4 0.0045 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.004462054 +4 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +5 chanx_right_out[12]:2 chanx_right_out[12] 2.35e-05 + +*END + +*D_NET chany_bottom_out[12] 0.002100165 //LENGTH 15.720 LUMPCC 0.0002943221 DR + +*CONN +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 77.740 6.460 +*P chany_bottom_out[12] O *L 0.7423 *C 67.620 1.325 +*N chany_bottom_out[12]:2 *C 67.620 6.415 +*N chany_bottom_out[12]:3 *C 67.665 6.460 +*N chany_bottom_out[12]:4 *C 77.703 6.460 + +*CAP +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[12] 0.0002630445 +2 chany_bottom_out[12]:2 0.0002630445 +3 chany_bottom_out[12]:3 0.0006393768 +4 chany_bottom_out[12]:4 0.0006393768 +5 chany_bottom_out[12] ropt_net_145:4 4.552572e-05 +6 chany_bottom_out[12]:2 ropt_net_145:3 4.552572e-05 +7 chany_bottom_out[12] ropt_net_146:4 3.180641e-07 +8 chany_bottom_out[12]:3 ropt_net_146:6 0.0001013173 +9 chany_bottom_out[12]:2 ropt_net_146:5 3.180641e-07 +10 chany_bottom_out[12]:4 ropt_net_146:7 0.0001013173 + +*RES +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[12]:4 0.152 +1 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +2 chany_bottom_out[12]:2 chany_bottom_out[12] 0.004544643 +3 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.008962054 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.003737512 //LENGTH 28.960 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 77.585 42.160 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 70.095 39.100 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 90.060 36.040 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 90.060 36.040 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 90.160 36.085 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 90.160 39.055 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 90.115 39.100 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 88.780 39.100 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 88.780 38.760 +*N mux_tree_tapbuf_size2_3_sram[0]:9 *C 70.095 39.100 +*N mux_tree_tapbuf_size2_3_sram[0]:10 *C 69.920 38.760 +*N mux_tree_tapbuf_size2_3_sram[0]:11 *C 77.740 38.760 +*N mux_tree_tapbuf_size2_3_sram[0]:12 *C 77.740 38.805 +*N mux_tree_tapbuf_size2_3_sram[0]:13 *C 77.740 42.115 +*N mux_tree_tapbuf_size2_3_sram[0]:14 *C 77.740 42.160 +*N mux_tree_tapbuf_size2_3_sram[0]:15 *C 77.585 42.160 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 2.629106e-05 +4 mux_tree_tapbuf_size2_3_sram[0]:4 0.0001753289 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0001753289 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.0001102546 +7 mux_tree_tapbuf_size2_3_sram[0]:7 0.0001338986 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.0007335633 +9 mux_tree_tapbuf_size2_3_sram[0]:9 5.238521e-05 +10 mux_tree_tapbuf_size2_3_sram[0]:10 0.0005286699 +11 mux_tree_tapbuf_size2_3_sram[0]:11 0.001244761 +12 mux_tree_tapbuf_size2_3_sram[0]:12 0.0002303031 +13 mux_tree_tapbuf_size2_3_sram[0]:13 0.0002303031 +14 mux_tree_tapbuf_size2_3_sram[0]:14 4.880245e-05 +15 mux_tree_tapbuf_size2_3_sram[0]:15 4.462191e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:9 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.002651786 +4 mux_tree_tapbuf_size2_3_sram[0]:3 mux_right_track_24\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_3_sram[0]:4 mux_tree_tapbuf_size2_3_sram[0]:3 0.0045 +6 mux_tree_tapbuf_size2_3_sram[0]:11 mux_tree_tapbuf_size2_3_sram[0]:10 0.006982143 +7 mux_tree_tapbuf_size2_3_sram[0]:11 mux_tree_tapbuf_size2_3_sram[0]:8 0.009857143 +8 mux_tree_tapbuf_size2_3_sram[0]:12 mux_tree_tapbuf_size2_3_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_3_sram[0]:14 mux_tree_tapbuf_size2_3_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size2_3_sram[0]:13 mux_tree_tapbuf_size2_3_sram[0]:12 0.002955357 +11 mux_tree_tapbuf_size2_3_sram[0]:15 mux_tree_tapbuf_size2_3_sram[0]:14 8.423914e-05 +12 mux_tree_tapbuf_size2_3_sram[0]:10 mux_tree_tapbuf_size2_3_sram[0]:9 0.0003035715 +13 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.0003035715 +14 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.001191964 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.001073073 //LENGTH 10.020 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/FTB_1__32:X O *L 0 *C 90.845 58.480 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 84.815 55.420 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 84.853 55.420 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 85.975 55.420 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 86.020 55.465 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 86.020 58.435 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 86.065 58.480 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 90.808 58.480 + +*CAP +0 mem_right_track_0\/FTB_1__32:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 9.321254e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 9.321254e-05 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0001789466 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001789466 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0002633776 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0002633776 + +*RES +0 mem_right_track_0\/FTB_1__32:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.004234375 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.001002232 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008662583 //LENGTH 7.270 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 98.725 58.820 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.280 61.000 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 103.280 61.000 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 103.040 60.860 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 103.040 60.815 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 103.040 58.865 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 102.995 58.820 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 98.763 58.820 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.307957e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.787362e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001311816 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001311816 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000245471 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000245471 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003779018 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741072 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001304348 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001188712 //LENGTH 8.095 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 50.775 20.060 +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 48.445 15.110 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 48.445 15.110 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 50.555 14.960 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 50.600 15.005 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 50.600 20.015 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 50.600 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 50.775 20.060 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002152578 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001788793 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000332625 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000332625 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.288731e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.443795e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001883929 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chany_bottom_out[13] 0.001403091 //LENGTH 10.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 56.775 3.400 +*P chany_bottom_out[13] O *L 0.7423 *C 49.680 1.210 +*N chany_bottom_out[13]:2 *C 49.680 2.033 +*N chany_bottom_out[13]:3 *C 49.700 2.040 +*N chany_bottom_out[13]:4 *C 56.573 2.040 +*N chany_bottom_out[13]:5 *C 56.580 2.098 +*N chany_bottom_out[13]:6 *C 56.580 3.355 +*N chany_bottom_out[13]:7 *C 56.580 3.400 +*N chany_bottom_out[13]:8 *C 56.775 3.400 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 chany_bottom_out[13] 7.731797e-05 +2 chany_bottom_out[13]:2 7.731797e-05 +3 chany_bottom_out[13]:3 0.0004647086 +4 chany_bottom_out[13]:4 0.0004647086 +5 chany_bottom_out[13]:5 9.898737e-05 +6 chany_bottom_out[13]:6 9.898737e-05 +7 chany_bottom_out[13]:7 6.111153e-05 +8 chany_bottom_out[13]:8 5.895179e-05 + +*RES +0 ropt_mt_inst_757:X chany_bottom_out[13]:8 0.152 +1 chany_bottom_out[13]:8 chany_bottom_out[13]:7 0.0001059783 +2 chany_bottom_out[13]:7 chany_bottom_out[13]:6 0.0045 +3 chany_bottom_out[13]:6 chany_bottom_out[13]:5 0.001122768 +4 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.00341 +5 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.001076692 +6 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.00341 +7 chany_bottom_out[13]:2 chany_bottom_out[13] 0.0001288583 + +*END + +*D_NET ropt_net_166 0.000525929 //LENGTH 4.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 102.580 68.680 +*I ropt_mt_inst_782:A I *L 0.001766 *C 106.260 69.360 +*N ropt_net_166:2 *C 106.223 69.360 +*N ropt_net_166:3 *C 102.580 69.360 +*N ropt_net_166:4 *C 102.580 68.680 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_166:2 0.0002052985 +3 ropt_net_166:3 0.0002485274 +4 ropt_net_166:4 7.010311e-05 + +*RES +0 ropt_mt_inst_739:X ropt_net_166:4 0.152 +1 ropt_net_166:4 ropt_net_166:3 0.0006071429 +2 ropt_net_166:2 ropt_mt_inst_782:A 0.152 +3 ropt_net_166:3 ropt_net_166:2 0.003252232 + +*END + +*D_NET ropt_net_155 0.001076034 //LENGTH 7.630 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 28.980 6.120 +*I ropt_mt_inst_771:A I *L 0.001766 *C 25.300 4.080 +*N ropt_net_155:2 *C 25.300 4.080 +*N ropt_net_155:3 *C 25.300 4.420 +*N ropt_net_155:4 *C 28.935 4.420 +*N ropt_net_155:5 *C 28.980 4.420 +*N ropt_net_155:6 *C 28.980 6.415 +*N ropt_net_155:7 *C 28.980 6.460 +*N ropt_net_155:8 *C 28.980 6.120 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_155:2 6.15831e-05 +3 ropt_net_155:3 0.0002742901 +4 ropt_net_155:4 0.0002443037 +5 ropt_net_155:5 0.0001916621 +6 ropt_net_155:6 0.0001610091 +7 ropt_net_155:7 7.298769e-05 +8 ropt_net_155:8 6.819816e-05 + +*RES +0 ropt_mt_inst_743:X ropt_net_155:8 0.152 +1 ropt_net_155:2 ropt_mt_inst_771:A 0.152 +2 ropt_net_155:4 ropt_net_155:3 0.003245536 +3 ropt_net_155:5 ropt_net_155:4 0.0045 +4 ropt_net_155:7 ropt_net_155:6 0.0045 +5 ropt_net_155:6 ropt_net_155:5 0.00178125 +6 ropt_net_155:8 ropt_net_155:7 0.0001465517 +7 ropt_net_155:3 ropt_net_155:2 0.0003035715 + +*END + +*D_NET ropt_net_165 0.00111012 //LENGTH 9.065 LUMPCC 8.487449e-05 DR + +*CONN +*I ropt_mt_inst_749:X O *L 0 *C 102.580 90.440 +*I ropt_mt_inst_781:A I *L 0.001766 *C 106.260 85.680 +*N ropt_net_165:2 *C 106.260 85.680 +*N ropt_net_165:3 *C 106.260 85.725 +*N ropt_net_165:4 *C 106.260 90.395 +*N ropt_net_165:5 *C 106.215 90.440 +*N ropt_net_165:6 *C 102.618 90.440 + +*CAP +0 ropt_mt_inst_749:X 1e-06 +1 ropt_mt_inst_781:A 1e-06 +2 ropt_net_165:2 3.214796e-05 +3 ropt_net_165:3 0.0002800509 +4 ropt_net_165:4 0.0002800509 +5 ropt_net_165:5 0.0002154978 +6 ropt_net_165:6 0.0002154978 +7 ropt_net_165:3 ropt_net_164:5 4.847791e-06 +8 ropt_net_165:5 ropt_net_164:2 3.758945e-05 +9 ropt_net_165:4 ropt_net_164:4 4.847791e-06 +10 ropt_net_165:6 ropt_net_164:3 3.758945e-05 + +*RES +0 ropt_mt_inst_749:X ropt_net_165:6 0.152 +1 ropt_net_165:2 ropt_mt_inst_781:A 0.152 +2 ropt_net_165:3 ropt_net_165:2 0.0045 +3 ropt_net_165:5 ropt_net_165:4 0.0045 +4 ropt_net_165:4 ropt_net_165:3 0.004169643 +5 ropt_net_165:6 ropt_net_165:5 0.003212054 + +*END + +*D_NET BUF_net_45 0.004748897 //LENGTH 34.765 LUMPCC 0.001135831 DR + +*CONN +*I BUFT_RR_45:X O *L 0 *C 64.860 6.800 +*I BUFT_RR_78:A I *L 0.001766 *C 40.480 9.520 +*N BUF_net_45:2 *C 40.518 9.520 +*N BUF_net_45:3 *C 40.895 9.520 +*N BUF_net_45:4 *C 40.940 9.475 +*N BUF_net_45:5 *C 40.940 4.465 +*N BUF_net_45:6 *C 40.985 4.420 +*N BUF_net_45:7 *C 51.060 4.420 +*N BUF_net_45:8 *C 51.060 3.740 +*N BUF_net_45:9 *C 64.815 3.740 +*N BUF_net_45:10 *C 64.860 3.785 +*N BUF_net_45:11 *C 64.860 6.755 +*N BUF_net_45:12 *C 64.860 6.800 + +*CAP +0 BUFT_RR_45:X 1e-06 +1 BUFT_RR_78:A 1e-06 +2 BUF_net_45:2 4.87537e-05 +3 BUF_net_45:3 4.87537e-05 +4 BUF_net_45:4 0.0002192345 +5 BUF_net_45:5 0.0002192345 +6 BUF_net_45:6 0.0006292671 +7 BUF_net_45:7 0.0006757495 +8 BUF_net_45:8 0.0007142541 +9 BUF_net_45:9 0.0006677717 +10 BUF_net_45:10 0.0001769222 +11 BUF_net_45:11 0.0001769222 +12 BUF_net_45:12 3.420176e-05 +13 BUF_net_45:6 ropt_net_158:3 0.0001111524 +14 BUF_net_45:5 ropt_net_158:4 0.0001228975 +15 BUF_net_45:3 ropt_net_158:7 9.004717e-06 +16 BUF_net_45:4 ropt_net_158:5 0.0001228975 +17 BUF_net_45:2 ropt_net_158:6 9.004717e-06 +18 BUF_net_45:7 ropt_net_158:2 0.0001111524 +19 BUF_net_45:9 ropt_net_141:3 4.424376e-05 +20 BUF_net_45:9 ropt_net_141:6 9.426366e-05 +21 BUF_net_45:8 ropt_net_141:2 4.424376e-05 +22 BUF_net_45:8 ropt_net_141:7 9.426366e-05 +23 BUF_net_45:9 mem_bottom_track_25/net_net_74:2 6.286517e-05 +24 BUF_net_45:8 mem_bottom_track_25/net_net_74:3 6.286517e-05 +25 BUF_net_45:9 ropt_net_117:9 0.0001234885 +26 BUF_net_45:8 ropt_net_117:8 0.0001234885 + +*RES +0 BUFT_RR_45:X BUF_net_45:12 0.152 +1 BUF_net_45:12 BUF_net_45:11 0.0045 +2 BUF_net_45:11 BUF_net_45:10 0.002651786 +3 BUF_net_45:9 BUF_net_45:8 0.01228125 +4 BUF_net_45:10 BUF_net_45:9 0.0045 +5 BUF_net_45:6 BUF_net_45:5 0.0045 +6 BUF_net_45:5 BUF_net_45:4 0.004473215 +7 BUF_net_45:3 BUF_net_45:2 0.0003370536 +8 BUF_net_45:4 BUF_net_45:3 0.0045 +9 BUF_net_45:2 BUFT_RR_78:A 0.152 +10 BUF_net_45:7 BUF_net_45:6 0.008995537 +11 BUF_net_45:8 BUF_net_45:7 0.0006071429 + +*END + +*D_NET chanx_right_out[3] 0.0008306552 //LENGTH 7.385 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 110.135 87.720 +*P chanx_right_out[3] O *L 0.7423 *C 111.863 82.960 +*N chanx_right_out[3]:2 *C 111.780 82.960 +*N chanx_right_out[3]:3 *C 111.780 83.017 +*N chanx_right_out[3]:4 *C 111.780 87.675 +*N chanx_right_out[3]:5 *C 111.735 87.720 +*N chanx_right_out[3]:6 *C 110.172 87.720 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 chanx_right_out[3] 3.4354e-05 +2 chanx_right_out[3]:2 3.4354e-05 +3 chanx_right_out[3]:3 0.000259518 +4 chanx_right_out[3]:4 0.000259518 +5 chanx_right_out[3]:5 0.0001209556 +6 chanx_right_out[3]:6 0.0001209556 + +*RES +0 ropt_mt_inst_772:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:6 chanx_right_out[3]:5 0.001395089 +2 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +3 chanx_right_out[3]:4 chanx_right_out[3]:3 0.004158482 +4 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +5 chanx_right_out[3]:2 chanx_right_out[3] 2.35e-05 + +*END + +*D_NET chanx_right_out[19] 0.0005036095 //LENGTH 4.325 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 110.135 44.540 +*P chanx_right_out[19] O *L 0.7423 *C 111.863 46.240 +*N chanx_right_out[19]:2 *C 111.780 46.240 +*N chanx_right_out[19]:3 *C 111.780 46.183 +*N chanx_right_out[19]:4 *C 111.780 44.585 +*N chanx_right_out[19]:5 *C 111.735 44.540 +*N chanx_right_out[19]:6 *C 110.172 44.540 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 chanx_right_out[19] 3.235127e-05 +2 chanx_right_out[19]:2 3.235127e-05 +3 chanx_right_out[19]:3 0.0001127732 +4 chanx_right_out[19]:4 0.0001127732 +5 chanx_right_out[19]:5 0.0001061803 +6 chanx_right_out[19]:6 0.0001061803 + +*RES +0 ropt_mt_inst_777:X chanx_right_out[19]:6 0.152 +1 chanx_right_out[19]:6 chanx_right_out[19]:5 0.001395089 +2 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0045 +3 chanx_right_out[19]:4 chanx_right_out[19]:3 0.001426339 +4 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +5 chanx_right_out[19]:2 chanx_right_out[19] 2.35e-05 + +*END + +*D_NET ropt_net_140 0.0009303851 //LENGTH 7.570 LUMPCC 0 DR + +*CONN +*I BUFT_RR_71:X O *L 0 *C 102.580 48.280 +*I ropt_mt_inst_756:A I *L 0.001766 *C 106.260 50.320 +*N ropt_net_140:2 *C 106.297 50.320 +*N ropt_net_140:3 *C 106.675 50.320 +*N ropt_net_140:4 *C 106.720 50.275 +*N ropt_net_140:5 *C 106.720 48.325 +*N ropt_net_140:6 *C 106.675 48.280 +*N ropt_net_140:7 *C 102.618 48.280 + +*CAP +0 BUFT_RR_71:X 1e-06 +1 ropt_mt_inst_756:A 1e-06 +2 ropt_net_140:2 3.960184e-05 +3 ropt_net_140:3 3.960184e-05 +4 ropt_net_140:4 0.0001423591 +5 ropt_net_140:5 0.0001423591 +6 ropt_net_140:6 0.0002822316 +7 ropt_net_140:7 0.0002822316 + +*RES +0 BUFT_RR_71:X ropt_net_140:7 0.152 +1 ropt_net_140:7 ropt_net_140:6 0.003622768 +2 ropt_net_140:6 ropt_net_140:5 0.0045 +3 ropt_net_140:5 ropt_net_140:4 0.001741071 +4 ropt_net_140:3 ropt_net_140:2 0.0003370536 +5 ropt_net_140:4 ropt_net_140:3 0.0045 +6 ropt_net_140:2 ropt_mt_inst_756:A 0.152 + +*END + +*D_NET chanx_right_out[15] 0.0004448512 //LENGTH 3.160 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 110.135 68.680 +*P chanx_right_out[15] O *L 0.7423 *C 111.855 68.000 +*N chanx_right_out[15]:2 *C 111.780 68.000 +*N chanx_right_out[15]:3 *C 110.407 68.000 +*N chanx_right_out[15]:4 *C 110.400 68.058 +*N chanx_right_out[15]:5 *C 110.400 68.635 +*N chanx_right_out[15]:6 *C 110.400 68.680 +*N chanx_right_out[15]:7 *C 110.135 68.680 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 chanx_right_out[15] 1.929622e-05 +2 chanx_right_out[15]:2 0.0001160059 +3 chanx_right_out[15]:3 9.670967e-05 +4 chanx_right_out[15]:4 5.079636e-05 +5 chanx_right_out[15]:5 5.079636e-05 +6 chanx_right_out[15]:6 4.921002e-05 +7 chanx_right_out[15]:7 6.103662e-05 + +*RES +0 ropt_mt_inst_782:X chanx_right_out[15]:7 0.152 +1 chanx_right_out[15]:7 chanx_right_out[15]:6 0.0001440218 +2 chanx_right_out[15]:6 chanx_right_out[15]:5 0.0045 +3 chanx_right_out[15]:5 chanx_right_out[15]:4 0.000515625 +4 chanx_right_out[15]:4 chanx_right_out[15]:3 0.00341 +5 chanx_right_out[15]:3 chanx_right_out[15]:2 0.000215025 +6 chanx_right_out[15]:2 chanx_right_out[15] 1.175e-05 + +*END + +*D_NET chanx_right_out[13] 0.0003430081 //LENGTH 1.985 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 110.135 66.640 +*P chanx_right_out[13] O *L 0.7423 *C 111.930 66.640 +*N chanx_right_out[13]:2 *C 110.407 66.640 +*N chanx_right_out[13]:3 *C 110.400 66.640 +*N chanx_right_out[13]:4 *C 110.400 66.640 +*N chanx_right_out[13]:5 *C 110.135 66.640 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 chanx_right_out[13] 0.0001050418 +2 chanx_right_out[13]:2 0.0001050418 +3 chanx_right_out[13]:3 3.093517e-05 +4 chanx_right_out[13]:4 4.615875e-05 +5 chanx_right_out[13]:5 5.483064e-05 + +*RES +0 ropt_mt_inst_785:X chanx_right_out[13]:5 0.152 +1 chanx_right_out[13]:5 chanx_right_out[13]:4 0.0001440218 +2 chanx_right_out[13]:4 chanx_right_out[13]:3 0.0045 +3 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +4 chanx_right_out[13]:2 chanx_right_out[13] 0.000238525 + +*END + +*D_NET ropt_net_118 0.0007898204 //LENGTH 7.695 LUMPCC 0.0001513334 DR + +*CONN +*I BUFT_P_94:X O *L 0 *C 38.005 11.900 +*I ropt_mt_inst_734:A I *L 0.001766 *C 37.260 6.800 +*N ropt_net_118:2 *C 37.223 6.800 +*N ropt_net_118:3 *C 36.845 6.800 +*N ropt_net_118:4 *C 36.800 6.845 +*N ropt_net_118:5 *C 36.800 11.855 +*N ropt_net_118:6 *C 36.845 11.900 +*N ropt_net_118:7 *C 37.968 11.900 + +*CAP +0 BUFT_P_94:X 1e-06 +1 ropt_mt_inst_734:A 1e-06 +2 ropt_net_118:2 4.182098e-05 +3 ropt_net_118:3 4.182098e-05 +4 ropt_net_118:4 0.0001959572 +5 ropt_net_118:5 0.0001959572 +6 ropt_net_118:6 8.046532e-05 +7 ropt_net_118:7 8.046532e-05 +8 ropt_net_118:5 chanx_right_in[17]:5 7.566671e-05 +9 ropt_net_118:4 chanx_right_in[17]:4 7.566671e-05 + +*RES +0 BUFT_P_94:X ropt_net_118:7 0.152 +1 ropt_net_118:7 ropt_net_118:6 0.001002232 +2 ropt_net_118:6 ropt_net_118:5 0.0045 +3 ropt_net_118:5 ropt_net_118:4 0.004473215 +4 ropt_net_118:3 ropt_net_118:2 0.0003370536 +5 ropt_net_118:4 ropt_net_118:3 0.0045 +6 ropt_net_118:2 ropt_mt_inst_734:A 0.152 + +*END + +*D_NET chanx_right_in[9] 0.01917738 //LENGTH 126.750 LUMPCC 0.01091948 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 111.855 35.360 +*I ropt_mt_inst_742:A I *L 0.001767 *C 20.700 4.080 +*N chanx_right_in[9]:2 *C 20.700 4.080 +*N chanx_right_in[9]:3 *C 20.700 4.125 +*N chanx_right_in[9]:4 *C 20.700 6.415 +*N chanx_right_in[9]:5 *C 20.745 6.460 +*N chanx_right_in[9]:6 *C 28.475 6.460 +*N chanx_right_in[9]:7 *C 28.520 6.505 +*N chanx_right_in[9]:8 *C 28.520 16.955 +*N chanx_right_in[9]:9 *C 28.565 17.000 +*N chanx_right_in[9]:10 *C 29.365 16.970 +*N chanx_right_in[9]:11 *C 29.433 17.010 +*N chanx_right_in[9]:12 *C 29.440 17.635 +*N chanx_right_in[9]:13 *C 29.485 17.680 +*N chanx_right_in[9]:14 *C 31.235 17.680 +*N chanx_right_in[9]:15 *C 31.280 17.725 +*N chanx_right_in[9]:16 *C 31.280 35.983 +*N chanx_right_in[9]:17 *C 31.288 36.040 +*N chanx_right_in[9]:18 *C 81.115 36.040 +*N chanx_right_in[9]:19 *C 107.640 36.040 +*N chanx_right_in[9]:20 *C 107.640 35.360 + +*CAP +0 chanx_right_in[9] 6.861816e-05 +1 ropt_mt_inst_742:A 1e-06 +2 chanx_right_in[9]:2 2.982207e-05 +3 chanx_right_in[9]:3 0.0001001675 +4 chanx_right_in[9]:4 0.0001001675 +5 chanx_right_in[9]:5 0.0004184975 +6 chanx_right_in[9]:6 0.0004184975 +7 chanx_right_in[9]:7 0.0005222728 +8 chanx_right_in[9]:8 0.0005222728 +9 chanx_right_in[9]:9 7.250067e-05 +10 chanx_right_in[9]:10 7.250067e-05 +11 chanx_right_in[9]:11 6.322571e-05 +12 chanx_right_in[9]:12 6.322571e-05 +13 chanx_right_in[9]:13 0.0001202217 +14 chanx_right_in[9]:14 0.0001202217 +15 chanx_right_in[9]:15 0.0003945566 +16 chanx_right_in[9]:16 0.0003945566 +17 chanx_right_in[9]:17 0.001699847 +18 chanx_right_in[9]:18 0.002310776 +19 chanx_right_in[9]:19 0.0006536351 +20 chanx_right_in[9]:20 0.0001113252 +21 chanx_right_in[9] chanx_right_in[4] 0.0001193239 +22 chanx_right_in[9]:17 chanx_right_in[4]:9 0.0005128845 +23 chanx_right_in[9]:19 chanx_right_in[4] 0.0001806511 +24 chanx_right_in[9]:19 chanx_right_in[4]:10 0.0002309448 +25 chanx_right_in[9]:20 chanx_right_in[4]:10 0.0001193239 +26 chanx_right_in[9]:18 chanx_right_in[4]:9 0.0002309448 +27 chanx_right_in[9]:18 chanx_right_in[4]:10 0.0006935355 +28 chanx_right_in[9] chanx_right_in[13] 0.0001111674 +29 chanx_right_in[9]:17 chanx_right_in[13]:6 0.001816079 +30 chanx_right_in[9]:19 chanx_right_in[13] 0.0005141352 +31 chanx_right_in[9]:19 chanx_right_in[13]:7 0.0009959164 +32 chanx_right_in[9]:20 chanx_right_in[13]:7 0.0001111674 +33 chanx_right_in[9]:18 chanx_right_in[13]:6 0.0009959164 +34 chanx_right_in[9]:18 chanx_right_in[13]:7 0.002330214 +35 chanx_right_in[9]:5 chanx_right_in[19]:3 4.442843e-05 +36 chanx_right_in[9]:6 chanx_right_in[19]:2 4.442843e-05 +37 chanx_right_in[9]:7 chanx_right_in[19]:4 4.295883e-05 +38 chanx_right_in[9]:8 chanx_right_in[19]:5 4.295883e-05 +39 chanx_right_in[9]:15 chanx_right_in[19]:10 0.0002658574 +40 chanx_right_in[9]:16 chanx_right_in[19]:11 0.0002658574 +41 chanx_right_in[9]:15 chany_bottom_in[11] 0.0005178626 +42 chanx_right_in[9]:16 chany_bottom_in[11]:9 0.0005178626 +43 chanx_right_in[9]:3 ropt_net_159:5 2.756531e-05 +44 chanx_right_in[9]:5 ropt_net_159:3 7.996253e-05 +45 chanx_right_in[9]:4 ropt_net_159:4 2.756531e-05 +46 chanx_right_in[9]:6 ropt_net_159:2 7.996253e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:20 0.00066035 +1 chanx_right_in[9]:2 ropt_mt_inst_742:A 0.152 +2 chanx_right_in[9]:3 chanx_right_in[9]:2 0.0045 +3 chanx_right_in[9]:5 chanx_right_in[9]:4 0.0045 +4 chanx_right_in[9]:4 chanx_right_in[9]:3 0.002044643 +5 chanx_right_in[9]:6 chanx_right_in[9]:5 0.006901786 +6 chanx_right_in[9]:7 chanx_right_in[9]:6 0.0045 +7 chanx_right_in[9]:9 chanx_right_in[9]:8 0.0045 +8 chanx_right_in[9]:8 chanx_right_in[9]:7 0.009330358 +9 chanx_right_in[9]:10 chanx_right_in[9]:9 0.0007142858 +10 chanx_right_in[9]:11 chanx_right_in[9]:10 0.0045 +11 chanx_right_in[9]:13 chanx_right_in[9]:12 0.0045 +12 chanx_right_in[9]:12 chanx_right_in[9]:11 0.0005580357 +13 chanx_right_in[9]:14 chanx_right_in[9]:13 0.0015625 +14 chanx_right_in[9]:15 chanx_right_in[9]:14 0.0045 +15 chanx_right_in[9]:16 chanx_right_in[9]:15 0.01630134 +16 chanx_right_in[9]:17 chanx_right_in[9]:16 0.00341 +17 chanx_right_in[9]:19 chanx_right_in[9]:18 0.004155583 +18 chanx_right_in[9]:20 chanx_right_in[9]:19 0.0001065333 +19 chanx_right_in[9]:18 chanx_right_in[9]:17 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[0] 0.003593382 //LENGTH 29.225 LUMPCC 0.0006613638 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.065 31.280 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 74.680 20.740 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 88.880 30.600 +*N mux_tree_tapbuf_size2_5_sram[0]:3 *C 88.880 30.600 +*N mux_tree_tapbuf_size2_5_sram[0]:4 *C 88.780 30.940 +*N mux_tree_tapbuf_size2_5_sram[0]:5 *C 74.980 30.940 +*N mux_tree_tapbuf_size2_5_sram[0]:6 *C 74.980 31.280 +*N mux_tree_tapbuf_size2_5_sram[0]:7 *C 74.680 20.740 +*N mux_tree_tapbuf_size2_5_sram[0]:8 *C 74.520 20.740 +*N mux_tree_tapbuf_size2_5_sram[0]:9 *C 74.520 20.785 +*N mux_tree_tapbuf_size2_5_sram[0]:10 *C 74.520 31.235 +*N mux_tree_tapbuf_size2_5_sram[0]:11 *C 74.520 31.280 +*N mux_tree_tapbuf_size2_5_sram[0]:12 *C 72.103 31.280 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[0]:3 5.373008e-05 +4 mux_tree_tapbuf_size2_5_sram[0]:4 0.0007247173 +5 mux_tree_tapbuf_size2_5_sram[0]:5 0.000723016 +6 mux_tree_tapbuf_size2_5_sram[0]:6 5.677219e-05 +7 mux_tree_tapbuf_size2_5_sram[0]:7 6.465854e-05 +8 mux_tree_tapbuf_size2_5_sram[0]:8 6.839714e-05 +9 mux_tree_tapbuf_size2_5_sram[0]:9 0.0004395195 +10 mux_tree_tapbuf_size2_5_sram[0]:10 0.0004395195 +11 mux_tree_tapbuf_size2_5_sram[0]:11 0.0002039883 +12 mux_tree_tapbuf_size2_5_sram[0]:12 0.0001547005 +13 mux_tree_tapbuf_size2_5_sram[0]:9 chanx_right_in[12]:5 0.0002215877 +14 mux_tree_tapbuf_size2_5_sram[0]:10 chanx_right_in[12]:6 0.0002215877 +15 mux_tree_tapbuf_size2_5_sram[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001090942 +16 mux_tree_tapbuf_size2_5_sram[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001090942 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_5_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_5_sram[0]:7 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:7 8.695653e-05 +3 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:8 0.0045 +4 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:6 0.0004107143 +6 mux_tree_tapbuf_size2_5_sram[0]:10 mux_tree_tapbuf_size2_5_sram[0]:9 0.009330357 +7 mux_tree_tapbuf_size2_5_sram[0]:3 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_5_sram[0]:12 mux_tree_tapbuf_size2_5_sram[0]:11 0.002158482 +9 mux_tree_tapbuf_size2_5_sram[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 0.0003035715 +10 mux_tree_tapbuf_size2_5_sram[0]:5 mux_tree_tapbuf_size2_5_sram[0]:4 0.01232143 +11 mux_tree_tapbuf_size2_5_sram[0]:4 mux_tree_tapbuf_size2_5_sram[0]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_6_ccff_tail[0] 0.001274465 //LENGTH 9.940 LUMPCC 0.000324581 DR + +*CONN +*I mem_bottom_track_9\/FTB_7__38:X O *L 0 *C 46.685 21.080 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 53.995 22.780 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 *C 53.958 22.780 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 *C 49.265 22.780 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 *C 49.220 22.735 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 *C 49.220 21.125 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 *C 49.175 21.080 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 *C 46.723 21.080 + +*CAP +0 mem_bottom_track_9\/FTB_7__38:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.0002541695 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0002541695 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 7.106055e-05 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 7.106055e-05 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.000148712 +7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.000148712 +8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chanx_right_in[13]:5 5.489729e-05 +9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 chanx_right_in[13]:3 3.982181e-05 +10 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chanx_right_in[13]:4 5.489729e-05 +11 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 chanx_right_in[13]:2 3.982181e-05 +12 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 prog_clk[0]:20 3.788391e-05 +13 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 prog_clk[0]:23 2.624884e-05 +14 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 prog_clk[0]:21 3.788391e-05 +15 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 prog_clk[0]:24 2.624884e-05 +16 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 prog_clk[0]:27 3.438688e-06 +17 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 prog_clk[0]:30 3.438688e-06 + +*RES +0 mem_bottom_track_9\/FTB_7__38:X mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.004189732 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.002189732 + +*END + +*D_NET chany_bottom_out[15] 0.002165468 //LENGTH 16.495 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 54.520 10.200 +*P chany_bottom_out[15] O *L 0.7423 *C 47.840 1.210 +*N chany_bottom_out[15]:2 *C 47.840 10.193 +*N chany_bottom_out[15]:3 *C 47.860 10.200 +*N chany_bottom_out[15]:4 *C 53.812 10.200 +*N chany_bottom_out[15]:5 *C 53.820 10.200 +*N chany_bottom_out[15]:6 *C 53.865 10.200 +*N chany_bottom_out[15]:7 *C 54.483 10.200 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 chany_bottom_out[15] 0.0005520369 +2 chany_bottom_out[15]:2 0.0005520369 +3 chany_bottom_out[15]:3 0.0004458178 +4 chany_bottom_out[15]:4 0.0004458178 +5 chany_bottom_out[15]:5 3.540164e-05 +6 chany_bottom_out[15]:6 6.667826e-05 +7 chany_bottom_out[15]:7 6.667826e-05 + +*RES +0 ropt_mt_inst_758:X chany_bottom_out[15]:7 0.152 +1 chany_bottom_out[15]:7 chany_bottom_out[15]:6 0.0005513393 +2 chany_bottom_out[15]:6 chany_bottom_out[15]:5 0.0045 +3 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.00341 +4 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.0009325582 +5 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.00341 +6 chany_bottom_out[15]:2 chany_bottom_out[15] 0.001407258 + +*END + +*D_NET ropt_net_158 0.001552183 //LENGTH 10.750 LUMPCC 0.0007095021 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 42.320 8.840 +*I ropt_mt_inst_774:A I *L 0.001766 *C 43.700 4.080 +*N ropt_net_158:2 *C 43.663 4.080 +*N ropt_net_158:3 *C 40.525 4.080 +*N ropt_net_158:4 *C 40.480 4.125 +*N ropt_net_158:5 *C 40.480 8.795 +*N ropt_net_158:6 *C 40.525 8.840 +*N ropt_net_158:7 *C 42.282 8.840 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 ropt_mt_inst_774:A 1e-06 +2 ropt_net_158:2 8.599953e-05 +3 ropt_net_158:3 8.599953e-05 +4 ropt_net_158:4 0.0001967999 +5 ropt_net_158:5 0.0001967999 +6 ropt_net_158:6 0.0001375409 +7 ropt_net_158:7 0.0001375409 +8 ropt_net_158:2 ropt_net_153:4 0.0001116964 +9 ropt_net_158:3 ropt_net_153:3 0.0001116964 +10 ropt_net_158:2 BUF_net_45:7 0.0001111524 +11 ropt_net_158:3 BUF_net_45:6 0.0001111524 +12 ropt_net_158:4 BUF_net_45:5 0.0001228975 +13 ropt_net_158:6 BUF_net_45:2 9.004717e-06 +14 ropt_net_158:5 BUF_net_45:4 0.0001228975 +15 ropt_net_158:7 BUF_net_45:3 9.004717e-06 + +*RES +0 ropt_mt_inst_732:X ropt_net_158:7 0.152 +1 ropt_net_158:2 ropt_mt_inst_774:A 0.152 +2 ropt_net_158:3 ropt_net_158:2 0.002801339 +3 ropt_net_158:4 ropt_net_158:3 0.0045 +4 ropt_net_158:6 ropt_net_158:5 0.0045 +5 ropt_net_158:5 ropt_net_158:4 0.004169643 +6 ropt_net_158:7 ropt_net_158:6 0.001569197 + +*END + +*D_NET ropt_net_146 0.001396258 //LENGTH 10.205 LUMPCC 0.0003184209 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 72.875 8.840 +*I ropt_mt_inst_762:A I *L 0.001767 *C 69.920 4.080 +*N ropt_net_146:2 *C 69.883 4.080 +*N ropt_net_146:3 *C 69.505 4.080 +*N ropt_net_146:4 *C 69.460 4.125 +*N ropt_net_146:5 *C 69.460 6.075 +*N ropt_net_146:6 *C 69.505 6.120 +*N ropt_net_146:7 *C 72.175 6.120 +*N ropt_net_146:8 *C 72.220 6.165 +*N ropt_net_146:9 *C 72.220 8.795 +*N ropt_net_146:10 *C 72.265 8.840 +*N ropt_net_146:11 *C 72.838 8.840 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_146:2 5.339841e-05 +3 ropt_net_146:3 5.339841e-05 +4 ropt_net_146:4 8.649741e-05 +5 ropt_net_146:5 8.649741e-05 +6 ropt_net_146:6 0.0001548643 +7 ropt_net_146:7 0.0001548643 +8 ropt_net_146:8 0.0001684431 +9 ropt_net_146:9 0.0001684431 +10 ropt_net_146:10 7.471563e-05 +11 ropt_net_146:11 7.471563e-05 +12 ropt_net_146:7 chany_bottom_out[12]:4 0.0001013173 +13 ropt_net_146:6 chany_bottom_out[12]:3 0.0001013173 +14 ropt_net_146:5 chany_bottom_out[12]:2 3.180641e-07 +15 ropt_net_146:4 chany_bottom_out[12] 3.180641e-07 +16 ropt_net_146:5 chany_bottom_out[7]:4 5.757513e-05 +17 ropt_net_146:4 chany_bottom_out[7]:3 5.757513e-05 + +*RES +0 ropt_mt_inst_740:X ropt_net_146:11 0.152 +1 ropt_net_146:11 ropt_net_146:10 0.0005111608 +2 ropt_net_146:10 ropt_net_146:9 0.0045 +3 ropt_net_146:9 ropt_net_146:8 0.002348214 +4 ropt_net_146:7 ropt_net_146:6 0.002383929 +5 ropt_net_146:8 ropt_net_146:7 0.0045 +6 ropt_net_146:6 ropt_net_146:5 0.0045 +7 ropt_net_146:5 ropt_net_146:4 0.001741071 +8 ropt_net_146:3 ropt_net_146:2 0.0003370536 +9 ropt_net_146:4 ropt_net_146:3 0.0045 +10 ropt_net_146:2 ropt_mt_inst_762:A 0.152 + +*END + +*D_NET BUF_net_44 0.001490654 //LENGTH 14.455 LUMPCC 0 DR + +*CONN +*I BUFT_RR_44:X O *L 0 *C 34.040 17.340 +*I BUFT_P_92:A I *L 0.001766 *C 33.580 4.080 +*N BUF_net_44:2 *C 33.580 4.080 +*N BUF_net_44:3 *C 33.580 4.125 +*N BUF_net_44:4 *C 33.580 16.955 +*N BUF_net_44:5 *C 33.625 17.000 +*N BUF_net_44:6 *C 34.040 17.000 +*N BUF_net_44:7 *C 34.040 17.340 + +*CAP +0 BUFT_RR_44:X 1e-06 +1 BUFT_P_92:A 1e-06 +2 BUF_net_44:2 3.490571e-05 +3 BUF_net_44:3 0.0006394759 +4 BUF_net_44:4 0.0006394759 +5 BUF_net_44:5 4.404177e-05 +6 BUF_net_44:6 7.253858e-05 +7 BUF_net_44:7 5.821648e-05 + +*RES +0 BUFT_RR_44:X BUF_net_44:7 0.152 +1 BUF_net_44:7 BUF_net_44:6 0.0003035715 +2 BUF_net_44:5 BUF_net_44:4 0.0045 +3 BUF_net_44:4 BUF_net_44:3 0.01145536 +4 BUF_net_44:2 BUFT_P_92:A 0.152 +5 BUF_net_44:3 BUF_net_44:2 0.0045 +6 BUF_net_44:6 BUF_net_44:5 0.0003705357 + +*END + +*D_NET ccff_tail[0] 0.001860038 //LENGTH 15.790 LUMPCC 0.0002725247 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 64.135 6.120 +*P ccff_tail[0] O *L 0.7423 *C 54.280 1.290 +*N ccff_tail[0]:2 *C 54.280 1.655 +*N ccff_tail[0]:3 *C 54.325 1.700 +*N ccff_tail[0]:4 *C 60.675 1.700 +*N ccff_tail[0]:5 *C 60.720 1.745 +*N ccff_tail[0]:6 *C 60.720 6.075 +*N ccff_tail[0]:7 *C 60.863 6.120 +*N ccff_tail[0]:8 *C 64.097 6.120 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 ccff_tail[0] 3.960252e-05 +2 ccff_tail[0]:2 3.960252e-05 +3 ccff_tail[0]:3 0.0002940126 +4 ccff_tail[0]:4 0.0002940126 +5 ccff_tail[0]:5 0.0002266015 +6 ccff_tail[0]:6 0.0002266015 +7 ccff_tail[0]:7 0.00023304 +8 ccff_tail[0]:8 0.00023304 +9 ccff_tail[0]:6 ropt_net_141:13 4.189504e-06 +10 ccff_tail[0]:4 ropt_net_141:11 0.0001320728 +11 ccff_tail[0]:5 ropt_net_141:12 4.189504e-06 +12 ccff_tail[0]:3 ropt_net_141:10 0.0001320728 + +*RES +0 ropt_mt_inst_755:X ccff_tail[0]:8 0.152 +1 ccff_tail[0]:8 ccff_tail[0]:7 0.002888393 +2 ccff_tail[0]:7 ccff_tail[0]:6 0.0045 +3 ccff_tail[0]:6 ccff_tail[0]:5 0.003866071 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.005669643 +5 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +6 ccff_tail[0]:3 ccff_tail[0]:2 0.0045 +7 ccff_tail[0]:2 ccff_tail[0] 0.0003258929 + +*END + +*D_NET chanx_right_out[8] 0.0007805296 //LENGTH 5.110 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 110.135 83.640 +*P chanx_right_out[8] O *L 0.7423 *C 111.930 85.680 +*N chanx_right_out[8]:2 *C 110.000 83.640 +*N chanx_right_out[8]:3 *C 110.420 85.680 +*N chanx_right_out[8]:4 *C 110.400 85.672 +*N chanx_right_out[8]:5 *C 110.400 83.648 +*N chanx_right_out[8]:6 *C 110.400 83.640 +*N chanx_right_out[8]:7 *C 110.400 83.640 +*N chanx_right_out[8]:8 *C 110.400 83.640 +*N chanx_right_out[8]:9 *C 110.135 83.640 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 chanx_right_out[8] 0.0001275278 +2 chanx_right_out[8]:2 6.656236e-05 +3 chanx_right_out[8]:3 0.0001275278 +4 chanx_right_out[8]:4 0.0001205339 +5 chanx_right_out[8]:5 0.0001205339 +6 chanx_right_out[8]:6 6.656236e-05 +7 chanx_right_out[8]:7 3.315815e-05 +8 chanx_right_out[8]:8 5.341014e-05 +9 chanx_right_out[8]:9 6.371328e-05 + +*RES +0 ropt_mt_inst_776:X chanx_right_out[8]:9 0.152 +1 chanx_right_out[8]:9 chanx_right_out[8]:8 0.0001440218 +2 chanx_right_out[8]:8 chanx_right_out[8]:7 0.0045 +3 chanx_right_out[8]:7 chanx_right_out[8]:6 0.00341 +4 chanx_right_out[8]:6 chanx_right_out[8]:5 0.00341 +5 chanx_right_out[8]:6 chanx_right_out[8]:2 5.696969e-05 +6 chanx_right_out[8]:5 chanx_right_out[8]:4 0.00031725 +7 chanx_right_out[8]:3 chanx_right_out[8] 0.0002365666 +8 chanx_right_out[8]:4 chanx_right_out[8]:3 0.00341 + +*END + +*D_NET chanx_right_in[10] 0.01138734 //LENGTH 101.815 LUMPCC 0.00364078 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 111.930 80.240 +*I BUFT_RR_51:A I *L 0.001776 *C 73.600 17.680 +*N chanx_right_in[10]:2 *C 73.600 17.680 +*N chanx_right_in[10]:3 *C 73.600 18.020 +*N chanx_right_in[10]:4 *C 81.835 18.020 +*N chanx_right_in[10]:5 *C 81.880 18.065 +*N chanx_right_in[10]:6 *C 81.880 67.860 +*N chanx_right_in[10]:7 *C 81.880 80.183 +*N chanx_right_in[10]:8 *C 81.888 80.240 + +*CAP +0 chanx_right_in[10] 0.001160025 +1 BUFT_RR_51:A 1e-06 +2 chanx_right_in[10]:2 5.951621e-05 +3 chanx_right_in[10]:3 0.0005140618 +4 chanx_right_in[10]:4 0.0004846122 +5 chanx_right_in[10]:5 0.001729449 +6 chanx_right_in[10]:6 0.00218366 +7 chanx_right_in[10]:7 0.000454211 +8 chanx_right_in[10]:8 0.001160025 +9 chanx_right_in[10] chanx_right_in[8] 0.0002689404 +10 chanx_right_in[10]:8 chanx_right_in[8]:21 0.0002689404 +11 chanx_right_in[10]:5 chany_bottom_in[4]:6 0.0005818862 +12 chanx_right_in[10]:5 chany_bottom_in[4]:5 6.814374e-05 +13 chanx_right_in[10]:7 chany_bottom_in[4]:4 0.000170391 +14 chanx_right_in[10]:6 chany_bottom_in[4]:4 6.814374e-05 +15 chanx_right_in[10]:6 chany_bottom_in[4]:5 0.0007522771 +16 chanx_right_in[10] chanx_right_out[4] 0.0001069962 +17 chanx_right_in[10] chanx_right_out[4]:3 0.0002464278 +18 chanx_right_in[10]:8 chanx_right_out[4]:4 0.0002464278 +19 chanx_right_in[10]:8 chanx_right_out[4]:2 0.0001069962 +20 chanx_right_in[10]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003776047 +21 chanx_right_in[10]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003776047 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:8 0.004706657 +1 chanx_right_in[10]:2 BUFT_RR_51:A 0.152 +2 chanx_right_in[10]:4 chanx_right_in[10]:3 0.007352678 +3 chanx_right_in[10]:5 chanx_right_in[10]:4 0.0045 +4 chanx_right_in[10]:7 chanx_right_in[10]:6 0.01100223 +5 chanx_right_in[10]:8 chanx_right_in[10]:7 0.00341 +6 chanx_right_in[10]:3 chanx_right_in[10]:2 0.0003035715 +7 chanx_right_in[10]:6 chanx_right_in[10]:5 0.04445983 + +*END + +*D_NET chany_bottom_in[1] 0.01702645 //LENGTH 175.490 LUMPCC 0.001827425 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 14.720 1.290 +*I ropt_mt_inst_737:A I *L 0.001767 *C 101.660 88.400 +*N chany_bottom_in[1]:2 *C 101.660 88.400 +*N chany_bottom_in[1]:3 *C 101.660 88.355 +*N chany_bottom_in[1]:4 *C 101.660 86.405 +*N chany_bottom_in[1]:5 *C 101.615 86.360 +*N chany_bottom_in[1]:6 *C 93.885 86.360 +*N chany_bottom_in[1]:7 *C 93.840 86.315 +*N chany_bottom_in[1]:8 *C 93.840 83.005 +*N chany_bottom_in[1]:9 *C 93.795 82.960 +*N chany_bottom_in[1]:10 *C 64.560 82.960 +*N chany_bottom_in[1]:11 *C 14.765 82.960 +*N chany_bottom_in[1]:12 *C 14.720 82.915 +*N chany_bottom_in[1]:13 *C 14.720 51.290 + +*CAP +0 chany_bottom_in[1] 0.001678091 +1 ropt_mt_inst_737:A 1e-06 +2 chany_bottom_in[1]:2 3.880839e-05 +3 chany_bottom_in[1]:3 0.0001236733 +4 chany_bottom_in[1]:4 0.0001236733 +5 chany_bottom_in[1]:5 0.000519626 +6 chany_bottom_in[1]:6 0.000519626 +7 chany_bottom_in[1]:7 0.0001728548 +8 chany_bottom_in[1]:8 0.0001728548 +9 chany_bottom_in[1]:9 0.001435394 +10 chany_bottom_in[1]:10 0.003835344 +11 chany_bottom_in[1]:11 0.00239995 +12 chany_bottom_in[1]:12 0.00125002 +13 chany_bottom_in[1]:13 0.002928111 +14 chany_bottom_in[1] chany_bottom_in[3] 0.0007255779 +15 chany_bottom_in[1]:12 chany_bottom_in[3]:12 0.0001881345 +16 chany_bottom_in[1]:13 chany_bottom_in[3]:13 0.0009137124 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:13 0.04464286 +1 chany_bottom_in[1]:2 ropt_mt_inst_737:A 0.152 +2 chany_bottom_in[1]:3 chany_bottom_in[1]:2 0.0045 +3 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.0045 +4 chany_bottom_in[1]:4 chany_bottom_in[1]:3 0.001741072 +5 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.006901787 +6 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.0045 +7 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.0045 +8 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.002955357 +9 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.04445983 +10 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.0045 +11 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.02610268 +12 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.02823661 + +*END + +*D_NET chany_bottom_in[3] 0.01762307 //LENGTH 157.695 LUMPCC 0.00471107 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 13.800 1.290 +*I ropt_mt_inst_739:A I *L 0.001767 *C 101.660 69.360 +*N chany_bottom_in[3]:2 *C 101.660 69.360 +*N chany_bottom_in[3]:3 *C 98.945 69.360 +*N chany_bottom_in[3]:4 *C 98.900 69.315 +*N chany_bottom_in[3]:5 *C 98.900 63.965 +*N chany_bottom_in[3]:6 *C 98.855 63.920 +*N chany_bottom_in[3]:7 *C 98.025 63.920 +*N chany_bottom_in[3]:8 *C 97.980 63.920 +*N chany_bottom_in[3]:9 *C 97.973 63.920 +*N chany_bottom_in[3]:10 *C 63.635 63.920 +*N chany_bottom_in[3]:11 *C 13.808 63.920 +*N chany_bottom_in[3]:12 *C 13.800 63.863 +*N chany_bottom_in[3]:13 *C 13.800 51.290 + +*CAP +0 chany_bottom_in[3] 0.001707078 +1 ropt_mt_inst_739:A 1e-06 +2 chany_bottom_in[3]:2 0.0002058308 +3 chany_bottom_in[3]:3 0.0001743021 +4 chany_bottom_in[3]:4 0.0002689432 +5 chany_bottom_in[3]:5 0.0002689432 +6 chany_bottom_in[3]:6 6.216617e-05 +7 chany_bottom_in[3]:7 6.216617e-05 +8 chany_bottom_in[3]:8 3.10884e-05 +9 chany_bottom_in[3]:9 0.001291821 +10 chany_bottom_in[3]:10 0.003779918 +11 chany_bottom_in[3]:11 0.002488098 +12 chany_bottom_in[3]:12 0.0004317828 +13 chany_bottom_in[3]:13 0.00213886 +14 chany_bottom_in[3]:9 chanx_right_in[5]:20 0.001441823 +15 chany_bottom_in[3]:10 chanx_right_in[5]:19 0.001441823 +16 chany_bottom_in[3] chany_bottom_in[1] 0.0007255779 +17 chany_bottom_in[3]:12 chany_bottom_in[1]:12 0.0001881345 +18 chany_bottom_in[3]:13 chany_bottom_in[1]:13 0.0009137124 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:13 0.04464286 +1 chany_bottom_in[3]:2 ropt_mt_inst_739:A 0.152 +2 chany_bottom_in[3]:3 chany_bottom_in[3]:2 0.002424107 +3 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.0045 +4 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.0045 +5 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.004776786 +6 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.0007410714 +7 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.0045 +8 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.00341 +9 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.00341 +10 chany_bottom_in[3]:11 chany_bottom_in[3]:10 0.007806308 +11 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.01122545 +12 chany_bottom_in[3]:10 chany_bottom_in[3]:9 0.005379541 + +*END + +*D_NET chany_bottom_in[5] 0.01392024 //LENGTH 124.545 LUMPCC 0.002890363 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 49.220 1.290 +*I ropt_mt_inst_750:A I *L 0.001767 *C 101.660 66.640 +*N chany_bottom_in[5]:2 *C 101.698 66.640 +*N chany_bottom_in[5]:3 *C 103.455 66.640 +*N chany_bottom_in[5]:4 *C 103.500 66.595 +*N chany_bottom_in[5]:5 *C 103.500 61.925 +*N chany_bottom_in[5]:6 *C 103.455 61.880 +*N chany_bottom_in[5]:7 *C 100.865 61.880 +*N chany_bottom_in[5]:8 *C 100.750 61.835 +*N chany_bottom_in[5]:9 *C 100.740 61.245 +*N chany_bottom_in[5]:10 *C 100.695 61.200 +*N chany_bottom_in[5]:11 *C 99.865 61.200 +*N chany_bottom_in[5]:12 *C 99.820 61.155 +*N chany_bottom_in[5]:13 *C 99.820 52.418 +*N chany_bottom_in[5]:14 *C 99.812 52.360 +*N chany_bottom_in[5]:15 *C 51.540 52.360 +*N chany_bottom_in[5]:16 *C 51.520 52.352 +*N chany_bottom_in[5]:17 *C 51.520 4.088 +*N chany_bottom_in[5]:18 *C 51.500 4.080 +*N chany_bottom_in[5]:19 *C 49.227 4.080 +*N chany_bottom_in[5]:20 *C 49.220 4.022 + +*CAP +0 chany_bottom_in[5] 0.0001698564 +1 ropt_mt_inst_750:A 1e-06 +2 chany_bottom_in[5]:2 7.798051e-05 +3 chany_bottom_in[5]:3 7.798051e-05 +4 chany_bottom_in[5]:4 0.0002517391 +5 chany_bottom_in[5]:5 0.0002517391 +6 chany_bottom_in[5]:6 0.0001957769 +7 chany_bottom_in[5]:7 0.0001957769 +8 chany_bottom_in[5]:8 5.269796e-05 +9 chany_bottom_in[5]:9 5.269796e-05 +10 chany_bottom_in[5]:10 6.631936e-05 +11 chany_bottom_in[5]:11 6.631936e-05 +12 chany_bottom_in[5]:12 0.000446811 +13 chany_bottom_in[5]:13 0.000446811 +14 chany_bottom_in[5]:14 0.002393546 +15 chany_bottom_in[5]:15 0.002393546 +16 chany_bottom_in[5]:16 0.001622401 +17 chany_bottom_in[5]:17 0.001622401 +18 chany_bottom_in[5]:18 0.0002373093 +19 chany_bottom_in[5]:19 0.0002373093 +20 chany_bottom_in[5]:20 0.0001698564 +21 chany_bottom_in[5]:14 chanx_right_in[15]:17 0.0003523834 +22 chany_bottom_in[5]:15 chanx_right_in[15]:16 0.0003523834 +23 chany_bottom_in[5]:16 chanx_right_in[15]:9 1.74719e-05 +24 chany_bottom_in[5]:17 chanx_right_in[15]:8 1.74719e-05 +25 chany_bottom_in[5]:16 chany_bottom_in[10]:15 0.00102894 +26 chany_bottom_in[5]:17 chany_bottom_in[10]:16 0.00102894 +27 chany_bottom_in[5]:2 ropt_net_169:5 4.638626e-05 +28 chany_bottom_in[5]:3 ropt_net_169:4 4.638626e-05 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:20 0.002439732 +1 chany_bottom_in[5]:2 ropt_mt_inst_750:A 0.152 +2 chany_bottom_in[5]:3 chany_bottom_in[5]:2 0.001569197 +3 chany_bottom_in[5]:4 chany_bottom_in[5]:3 0.0045 +4 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.0045 +5 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.004169643 +6 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.0023125 +7 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.0045 +8 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.0045 +9 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.0005267858 +10 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.0007410714 +11 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.0045 +12 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.00780134 +13 chany_bottom_in[5]:14 chany_bottom_in[5]:13 0.00341 +14 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.007562691 +15 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.00341 +16 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.00341 +17 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.007561516 +18 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.00341 +19 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.000356025 + +*END + +*D_NET chany_bottom_in[11] 0.0141366 //LENGTH 136.410 LUMPCC 0.002567862 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 30.820 1.290 +*I BUFT_RR_67:A I *L 0.001776 *C 92.920 74.800 +*N chany_bottom_in[11]:2 *C 92.920 74.800 +*N chany_bottom_in[11]:3 *C 92.920 74.755 +*N chany_bottom_in[11]:4 *C 92.920 69.065 +*N chany_bottom_in[11]:5 *C 92.875 69.020 +*N chany_bottom_in[11]:6 *C 80.660 69.020 +*N chany_bottom_in[11]:7 *C 30.865 69.020 +*N chany_bottom_in[11]:8 *C 30.820 68.975 +*N chany_bottom_in[11]:9 *C 30.820 51.290 + +*CAP +0 chany_bottom_in[11] 0.001631739 +1 BUFT_RR_67:A 1e-06 +2 chany_bottom_in[11]:2 3.562307e-05 +3 chany_bottom_in[11]:3 0.0003105702 +4 chany_bottom_in[11]:4 0.0003105702 +5 chany_bottom_in[11]:5 0.0006413272 +6 chany_bottom_in[11]:6 0.003154628 +7 chany_bottom_in[11]:7 0.0025133 +8 chany_bottom_in[11]:8 0.0006691186 +9 chany_bottom_in[11]:9 0.002300858 +10 chany_bottom_in[11] chanx_right_in[9]:15 0.0005178626 +11 chany_bottom_in[11]:9 chanx_right_in[9]:16 0.0005178626 +12 chany_bottom_in[11] chanx_right_in[19]:10 0.0001561096 +13 chany_bottom_in[11]:8 chanx_right_in[19]:11 0.0001019456 +14 chany_bottom_in[11]:8 chanx_right_in[19]:12 6.134901e-05 +15 chany_bottom_in[11]:9 chanx_right_in[19]:10 0.0001019456 +16 chany_bottom_in[11]:9 chanx_right_in[19]:11 0.0002174586 +17 chany_bottom_in[11] chany_bottom_in[17] 0.0002916409 +18 chany_bottom_in[11]:9 chany_bottom_in[17]:13 0.0002916409 +19 chany_bottom_in[11] BUF_net_42:4 0.0001550234 +20 chany_bottom_in[11]:9 BUF_net_42:5 0.0001550234 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:9 0.04464286 +1 chany_bottom_in[11]:2 BUFT_RR_67:A 0.152 +2 chany_bottom_in[11]:3 chany_bottom_in[11]:2 0.0045 +3 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.0045 +4 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.005080357 +5 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.04445982 +6 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.0045 +7 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.01090625 +8 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.01579018 + +*END + +*D_NET chany_bottom_in[13] 0.01281998 //LENGTH 120.705 LUMPCC 0 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 72.220 1.290 +*I BUFT_RR_69:A I *L 0.001776 *C 98.440 93.840 +*N chany_bottom_in[13]:2 *C 98.440 93.840 +*N chany_bottom_in[13]:3 *C 98.440 93.840 +*N chany_bottom_in[13]:4 *C 98.433 93.840 +*N chany_bottom_in[13]:5 *C 81.900 93.840 +*N chany_bottom_in[13]:6 *C 81.880 93.833 +*N chany_bottom_in[13]:7 *C 81.880 69.555 +*N chany_bottom_in[13]:8 *C 81.880 19.728 +*N chany_bottom_in[13]:9 *C 81.860 19.720 +*N chany_bottom_in[13]:10 *C 73.620 19.720 +*N chany_bottom_in[13]:11 *C 73.600 19.713 +*N chany_bottom_in[13]:12 *C 73.600 2.048 +*N chany_bottom_in[13]:13 *C 73.580 2.040 +*N chany_bottom_in[13]:14 *C 72.228 2.040 +*N chany_bottom_in[13]:15 *C 72.220 1.983 + +*CAP +0 chany_bottom_in[13] 6.015841e-05 +1 BUFT_RR_69:A 1e-06 +2 chany_bottom_in[13]:2 2.721358e-05 +3 chany_bottom_in[13]:3 3.078646e-05 +4 chany_bottom_in[13]:4 0.0008089531 +5 chany_bottom_in[13]:5 0.0008089531 +6 chany_bottom_in[13]:6 0.001150911 +7 chany_bottom_in[13]:7 0.003830044 +8 chany_bottom_in[13]:8 0.002679134 +9 chany_bottom_in[13]:9 0.0005432091 +10 chany_bottom_in[13]:10 0.0005432091 +11 chany_bottom_in[13]:11 0.00101197 +12 chany_bottom_in[13]:12 0.00101197 +13 chany_bottom_in[13]:13 0.0001261562 +14 chany_bottom_in[13]:14 0.0001261562 +15 chany_bottom_in[13]:15 6.015841e-05 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:15 0.0006183035 +1 chany_bottom_in[13]:2 BUFT_RR_69:A 0.152 +2 chany_bottom_in[13]:3 chany_bottom_in[13]:2 0.0045 +3 chany_bottom_in[13]:4 chany_bottom_in[13]:3 0.00341 +4 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.002590091 +5 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.00341 +6 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.00341 +7 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.007806308 +8 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.001290933 +9 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.00341 +10 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.00341 +11 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.002767516 +12 chany_bottom_in[13]:15 chany_bottom_in[13]:14 0.00341 +13 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.0002118916 +14 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.003803475 + +*END + +*D_NET chany_bottom_in[17] 0.01394371 //LENGTH 119.815 LUMPCC 0.001100915 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 29.900 1.290 +*I BUFT_RR_71:A I *L 0.001767 *C 101.660 47.600 +*N chany_bottom_in[17]:2 *C 101.623 47.600 +*N chany_bottom_in[17]:3 *C 100.325 47.600 +*N chany_bottom_in[17]:4 *C 100.280 47.555 +*N chany_bottom_in[17]:5 *C 100.280 42.885 +*N chany_bottom_in[17]:6 *C 100.235 42.840 +*N chany_bottom_in[17]:7 *C 92.620 42.840 +*N chany_bottom_in[17]:8 *C 42.825 42.840 +*N chany_bottom_in[17]:9 *C 42.780 42.795 +*N chany_bottom_in[17]:10 *C 42.780 22.825 +*N chany_bottom_in[17]:11 *C 42.735 22.780 +*N chany_bottom_in[17]:12 *C 29.945 22.780 +*N chany_bottom_in[17]:13 *C 29.900 22.735 + +*CAP +0 chany_bottom_in[17] 0.0008665128 +1 BUFT_RR_71:A 1e-06 +2 chany_bottom_in[17]:2 9.455722e-05 +3 chany_bottom_in[17]:3 9.455722e-05 +4 chany_bottom_in[17]:4 0.0002789777 +5 chany_bottom_in[17]:5 0.0002789777 +6 chany_bottom_in[17]:6 0.0005563116 +7 chany_bottom_in[17]:7 0.003659934 +8 chany_bottom_in[17]:8 0.003103623 +9 chany_bottom_in[17]:9 0.0008334082 +10 chany_bottom_in[17]:10 0.0008334082 +11 chany_bottom_in[17]:11 0.0006875069 +12 chany_bottom_in[17]:12 0.0006875069 +13 chany_bottom_in[17]:13 0.0008665128 +14 chany_bottom_in[17] chany_bottom_in[11] 0.0002916409 +15 chany_bottom_in[17]:13 chany_bottom_in[11]:9 0.0002916409 +16 chany_bottom_in[17]:9 chany_bottom_in[16]:8 0.0002588163 +17 chany_bottom_in[17]:10 chany_bottom_in[16] 0.0002588163 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:13 0.01914732 +1 chany_bottom_in[17]:2 BUFT_RR_71:A 0.152 +2 chany_bottom_in[17]:3 chany_bottom_in[17]:2 0.001158482 +3 chany_bottom_in[17]:4 chany_bottom_in[17]:3 0.0045 +4 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.0045 +5 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.004169643 +6 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.04445983 +7 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.0045 +8 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.0045 +9 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.01783036 +10 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.01141964 +11 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.0045 +12 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.006799108 + +*END + +*D_NET prog_clk[0] 0.0209972 //LENGTH 163.115 LUMPCC 0.0005349166 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 36.340 1.325 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.525 20.400 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 65.125 31.280 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 68.805 34.000 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 68.805 39.440 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 70.645 42.160 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.865 44.880 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 85.365 50.320 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 83.525 55.760 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 84.905 61.200 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 86.285 63.920 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 76.625 50.320 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.405 20.400 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 65.125 12.240 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.645 17.680 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 52.705 23.120 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 51.325 25.840 +*N prog_clk[0]:17 *C 51.325 25.840 +*N prog_clk[0]:18 *C 51.060 25.840 +*N prog_clk[0]:19 *C 51.060 25.795 +*N prog_clk[0]:20 *C 52.668 23.120 +*N prog_clk[0]:21 *C 52.025 23.120 +*N prog_clk[0]:22 *C 51.980 23.075 +*N prog_clk[0]:23 *C 51.980 21.760 +*N prog_clk[0]:24 *C 51.060 21.760 +*N prog_clk[0]:25 *C 51.053 21.760 +*N prog_clk[0]:26 *C 47.848 21.760 +*N prog_clk[0]:27 *C 47.840 21.703 +*N prog_clk[0]:28 *C 47.645 17.680 +*N prog_clk[0]:29 *C 47.840 17.340 +*N prog_clk[0]:30 *C 47.840 17.340 +*N prog_clk[0]:31 *C 65.088 12.240 +*N prog_clk[0]:32 *C 63.525 12.240 +*N prog_clk[0]:33 *C 63.480 12.240 +*N prog_clk[0]:34 *C 63.473 12.240 +*N prog_clk[0]:35 *C 62.100 12.240 +*N prog_clk[0]:36 *C 73.368 20.400 +*N prog_clk[0]:37 *C 71.805 20.400 +*N prog_clk[0]:38 *C 71.760 20.400 +*N prog_clk[0]:39 *C 71.752 20.400 +*N prog_clk[0]:40 *C 76.625 50.320 +*N prog_clk[0]:41 *C 76.360 50.320 +*N prog_clk[0]:42 *C 86.248 63.920 +*N prog_clk[0]:43 *C 85.145 63.920 +*N prog_clk[0]:44 *C 85.100 63.875 +*N prog_clk[0]:45 *C 84.905 61.200 +*N prog_clk[0]:46 *C 85.100 60.860 +*N prog_clk[0]:47 *C 85.100 60.905 +*N prog_clk[0]:48 *C 85.100 60.520 +*N prog_clk[0]:49 *C 85.093 60.520 +*N prog_clk[0]:50 *C 83.728 60.520 +*N prog_clk[0]:51 *C 83.720 60.463 +*N prog_clk[0]:52 *C 83.525 55.760 +*N prog_clk[0]:53 *C 83.720 55.420 +*N prog_clk[0]:54 *C 83.720 55.420 +*N prog_clk[0]:55 *C 85.328 50.320 +*N prog_clk[0]:56 *C 84.685 50.320 +*N prog_clk[0]:57 *C 84.640 50.320 +*N prog_clk[0]:58 *C 83.720 50.320 +*N prog_clk[0]:59 *C 83.713 50.320 +*N prog_clk[0]:60 *C 76.368 50.320 +*N prog_clk[0]:61 *C 76.360 50.320 +*N prog_clk[0]:62 *C 76.360 44.938 +*N prog_clk[0]:63 *C 76.353 44.880 +*N prog_clk[0]:64 *C 73.865 44.880 +*N prog_clk[0]:65 *C 73.600 44.880 +*N prog_clk[0]:66 *C 73.600 44.880 +*N prog_clk[0]:67 *C 73.600 44.880 +*N prog_clk[0]:68 *C 69.468 44.880 +*N prog_clk[0]:69 *C 69.460 44.823 +*N prog_clk[0]:70 *C 69.460 42.500 +*N prog_clk[0]:71 *C 70.608 42.160 +*N prog_clk[0]:72 *C 69.000 42.160 +*N prog_clk[0]:73 *C 69.000 42.500 +*N prog_clk[0]:74 *C 69.000 42.500 +*N prog_clk[0]:75 *C 68.805 39.440 +*N prog_clk[0]:76 *C 69.000 39.100 +*N prog_clk[0]:77 *C 69.000 39.145 +*N prog_clk[0]:78 *C 68.540 39.100 +*N prog_clk[0]:79 *C 68.805 34.000 +*N prog_clk[0]:80 *C 68.540 33.660 +*N prog_clk[0]:81 *C 68.540 33.660 +*N prog_clk[0]:82 *C 68.540 32.698 +*N prog_clk[0]:83 *C 68.532 32.640 +*N prog_clk[0]:84 *C 64.868 32.640 +*N prog_clk[0]:85 *C 64.860 32.583 +*N prog_clk[0]:86 *C 65.125 31.280 +*N prog_clk[0]:87 *C 64.860 31.620 +*N prog_clk[0]:88 *C 64.860 31.620 +*N prog_clk[0]:89 *C 64.860 20.457 +*N prog_clk[0]:90 *C 64.860 20.400 +*N prog_clk[0]:91 *C 60.525 20.400 +*N prog_clk[0]:92 *C 60.720 20.400 +*N prog_clk[0]:93 *C 60.720 20.400 +*N prog_clk[0]:94 *C 60.728 20.400 +*N prog_clk[0]:95 *C 62.100 20.400 +*N prog_clk[0]:96 *C 62.100 20.343 +*N prog_clk[0]:97 *C 62.100 12.978 +*N prog_clk[0]:98 *C 62.100 12.913 +*N prog_clk[0]:99 *C 47.848 12.920 +*N prog_clk[0]:100 *C 47.840 12.920 +*N prog_clk[0]:101 *C 47.840 2.085 +*N prog_clk[0]:102 *C 47.795 2.040 +*N prog_clk[0]:103 *C 36.385 2.040 +*N prog_clk[0]:104 *C 36.340 1.995 + +*CAP +0 prog_clk[0] 5.309e-05 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +4 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +5 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +6 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +7 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +8 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +9 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +10 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +12 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +13 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +14 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +15 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +16 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 prog_clk[0]:17 6.090861e-05 +18 prog_clk[0]:18 6.176472e-05 +19 prog_clk[0]:19 0.0002229896 +20 prog_clk[0]:20 4.35631e-05 +21 prog_clk[0]:21 4.35631e-05 +22 prog_clk[0]:22 0.0001004959 +23 prog_clk[0]:23 0.0001360094 +24 prog_clk[0]:24 0.0002585032 +25 prog_clk[0]:25 0.0002152339 +26 prog_clk[0]:26 0.0002152339 +27 prog_clk[0]:27 0.0002492936 +28 prog_clk[0]:28 6.704833e-05 +29 prog_clk[0]:29 7.089607e-05 +30 prog_clk[0]:30 0.0005175581 +31 prog_clk[0]:31 0.0001432209 +32 prog_clk[0]:32 0.0001432209 +33 prog_clk[0]:33 3.317292e-05 +34 prog_clk[0]:34 9.811457e-05 +35 prog_clk[0]:35 0.0001520574 +36 prog_clk[0]:36 0.0001373976 +37 prog_clk[0]:37 0.0001373976 +38 prog_clk[0]:38 3.821711e-05 +39 prog_clk[0]:39 0.0004244146 +40 prog_clk[0]:40 5.949123e-05 +41 prog_clk[0]:41 5.956231e-05 +42 prog_clk[0]:42 0.0001102727 +43 prog_clk[0]:43 0.0001102727 +44 prog_clk[0]:44 0.0001661068 +45 prog_clk[0]:45 7.834223e-05 +46 prog_clk[0]:46 7.73208e-05 +47 prog_clk[0]:47 0.0001843416 +48 prog_clk[0]:48 5.500487e-05 +49 prog_clk[0]:49 0.0001635767 +50 prog_clk[0]:50 0.0001635767 +51 prog_clk[0]:51 0.0002706934 +52 prog_clk[0]:52 7.380416e-05 +53 prog_clk[0]:53 7.447712e-05 +54 prog_clk[0]:54 0.0005680231 +55 prog_clk[0]:55 7.211419e-05 +56 prog_clk[0]:56 7.211419e-05 +57 prog_clk[0]:57 8.493105e-05 +58 prog_clk[0]:58 0.0003215516 +59 prog_clk[0]:59 0.0004978619 +60 prog_clk[0]:60 0.0004978619 +61 prog_clk[0]:61 0.0003609486 +62 prog_clk[0]:62 0.0003263874 +63 prog_clk[0]:63 0.0001963453 +64 prog_clk[0]:64 5.445084e-05 +65 prog_clk[0]:65 5.308818e-05 +66 prog_clk[0]:66 3.911763e-05 +67 prog_clk[0]:67 0.0004963404 +68 prog_clk[0]:68 0.0002999951 +69 prog_clk[0]:69 0.0001590402 +70 prog_clk[0]:70 0.0001946625 +71 prog_clk[0]:71 0.0001167398 +72 prog_clk[0]:72 0.0001462419 +73 prog_clk[0]:73 6.586823e-05 +74 prog_clk[0]:74 0.0002526322 +75 prog_clk[0]:75 6.408826e-05 +76 prog_clk[0]:76 6.792847e-05 +77 prog_clk[0]:77 0.0002507871 +78 prog_clk[0]:78 0.0003391457 +79 prog_clk[0]:79 6.972897e-05 +80 prog_clk[0]:80 6.992034e-05 +81 prog_clk[0]:81 0.0004064659 +82 prog_clk[0]:82 6.809148e-05 +83 prog_clk[0]:83 0.0002515877 +84 prog_clk[0]:84 0.0002515877 +85 prog_clk[0]:85 6.664104e-05 +86 prog_clk[0]:86 6.089036e-05 +87 prog_clk[0]:87 6.523234e-05 +88 prog_clk[0]:88 0.0007239735 +89 prog_clk[0]:89 0.0006253186 +90 prog_clk[0]:90 0.0005797948 +91 prog_clk[0]:91 5.126627e-05 +92 prog_clk[0]:92 5.696521e-05 +93 prog_clk[0]:93 3.498702e-05 +94 prog_clk[0]:94 8.706977e-05 +95 prog_clk[0]:95 0.00024245 +96 prog_clk[0]:96 0.0004328734 +97 prog_clk[0]:97 0.0004328734 +98 prog_clk[0]:98 0.0009745467 +99 prog_clk[0]:99 0.0009206038 +100 prog_clk[0]:100 0.0008490754 +101 prog_clk[0]:101 0.0005728034 +102 prog_clk[0]:102 0.0008149901 +103 prog_clk[0]:103 0.0008149901 +104 prog_clk[0]:104 5.309e-05 +105 prog_clk[0]:24 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 2.624884e-05 +106 prog_clk[0]:27 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 3.438688e-06 +107 prog_clk[0]:21 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 3.788391e-05 +108 prog_clk[0]:20 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 3.788391e-05 +109 prog_clk[0]:30 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 3.438688e-06 +110 prog_clk[0]:23 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 2.624884e-05 +111 prog_clk[0]:101 ropt_net_143:3 0.0001998869 +112 prog_clk[0]:100 ropt_net_143:4 0.0001998869 + +*RES +0 prog_clk[0] prog_clk[0]:104 0.0005982143 +1 prog_clk[0]:56 prog_clk[0]:55 0.0005736607 +2 prog_clk[0]:57 prog_clk[0]:56 0.0045 +3 prog_clk[0]:55 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +4 prog_clk[0]:102 prog_clk[0]:101 0.0045 +5 prog_clk[0]:101 prog_clk[0]:100 0.009674108 +6 prog_clk[0]:103 prog_clk[0]:102 0.0101875 +7 prog_clk[0]:104 prog_clk[0]:103 0.0045 +8 prog_clk[0]:100 prog_clk[0]:99 0.00341 +9 prog_clk[0]:100 prog_clk[0]:30 0.003946429 +10 prog_clk[0]:99 prog_clk[0]:98 0.002232892 +11 prog_clk[0]:97 prog_clk[0]:96 0.006575894 +12 prog_clk[0]:98 prog_clk[0]:97 0.00341 +13 prog_clk[0]:98 prog_clk[0]:35 0.0001053583 +14 prog_clk[0]:96 prog_clk[0]:95 0.00341 +15 prog_clk[0]:95 prog_clk[0]:94 0.000215025 +16 prog_clk[0]:95 prog_clk[0]:90 0.0004324 +17 prog_clk[0]:61 prog_clk[0]:60 0.00341 +18 prog_clk[0]:61 prog_clk[0]:41 0.0045 +19 prog_clk[0]:60 prog_clk[0]:59 0.001150717 +20 prog_clk[0]:58 prog_clk[0]:57 0.0008214285 +21 prog_clk[0]:58 prog_clk[0]:54 0.004553571 +22 prog_clk[0]:59 prog_clk[0]:58 0.00341 +23 prog_clk[0]:24 prog_clk[0]:23 0.0008214285 +24 prog_clk[0]:24 prog_clk[0]:19 0.003602679 +25 prog_clk[0]:25 prog_clk[0]:24 0.00341 +26 prog_clk[0]:27 prog_clk[0]:26 0.00341 +27 prog_clk[0]:26 prog_clk[0]:25 0.0005021166 +28 prog_clk[0]:89 prog_clk[0]:88 0.009966519 +29 prog_clk[0]:90 prog_clk[0]:89 0.00341 +30 prog_clk[0]:90 prog_clk[0]:39 0.001079825 +31 prog_clk[0]:85 prog_clk[0]:84 0.00341 +32 prog_clk[0]:84 prog_clk[0]:83 0.0005741833 +33 prog_clk[0]:82 prog_clk[0]:81 0.0008593751 +34 prog_clk[0]:83 prog_clk[0]:82 0.00341 +35 prog_clk[0]:69 prog_clk[0]:68 0.00341 +36 prog_clk[0]:68 prog_clk[0]:67 0.000647425 +37 prog_clk[0]:48 prog_clk[0]:47 0.0001850962 +38 prog_clk[0]:49 prog_clk[0]:48 0.00341 +39 prog_clk[0]:51 prog_clk[0]:50 0.00341 +40 prog_clk[0]:50 prog_clk[0]:49 0.00021385 +41 prog_clk[0]:21 prog_clk[0]:20 0.0005736608 +42 prog_clk[0]:22 prog_clk[0]:21 0.0045 +43 prog_clk[0]:20 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +44 prog_clk[0]:29 prog_clk[0]:28 0.0001847826 +45 prog_clk[0]:30 prog_clk[0]:29 0.0045 +46 prog_clk[0]:30 prog_clk[0]:27 0.003895089 +47 prog_clk[0]:28 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +48 prog_clk[0]:93 prog_clk[0]:92 0.0045 +49 prog_clk[0]:94 prog_clk[0]:93 0.00341 +50 prog_clk[0]:92 prog_clk[0]:91 0.0001059783 +51 prog_clk[0]:91 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +52 prog_clk[0]:38 prog_clk[0]:37 0.0045 +53 prog_clk[0]:39 prog_clk[0]:38 0.00341 +54 prog_clk[0]:37 prog_clk[0]:36 0.001395089 +55 prog_clk[0]:36 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +56 prog_clk[0]:87 prog_clk[0]:86 0.0001847826 +57 prog_clk[0]:88 prog_clk[0]:87 0.0045 +58 prog_clk[0]:88 prog_clk[0]:85 0.0008593751 +59 prog_clk[0]:86 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +60 prog_clk[0]:46 prog_clk[0]:45 0.0001847826 +61 prog_clk[0]:47 prog_clk[0]:46 0.0045 +62 prog_clk[0]:47 prog_clk[0]:44 0.002651786 +63 prog_clk[0]:45 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +64 prog_clk[0]:18 prog_clk[0]:17 0.0001440218 +65 prog_clk[0]:19 prog_clk[0]:18 0.0045 +66 prog_clk[0]:17 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +67 prog_clk[0]:80 prog_clk[0]:79 0.0001847826 +68 prog_clk[0]:81 prog_clk[0]:80 0.0045 +69 prog_clk[0]:81 prog_clk[0]:78 0.004857143 +70 prog_clk[0]:79 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +71 prog_clk[0]:76 prog_clk[0]:75 0.0001847826 +72 prog_clk[0]:77 prog_clk[0]:76 0.0045 +73 prog_clk[0]:77 prog_clk[0]:74 0.002995536 +74 prog_clk[0]:75 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +75 prog_clk[0]:73 prog_clk[0]:72 0.0003035715 +76 prog_clk[0]:74 prog_clk[0]:73 0.0045 +77 prog_clk[0]:74 prog_clk[0]:70 0.0004107143 +78 prog_clk[0]:71 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +79 prog_clk[0]:66 prog_clk[0]:65 0.0045 +80 prog_clk[0]:67 prog_clk[0]:66 0.00341 +81 prog_clk[0]:67 prog_clk[0]:63 0.0004312249 +82 prog_clk[0]:65 prog_clk[0]:64 0.0001440218 +83 prog_clk[0]:64 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +84 prog_clk[0]:41 prog_clk[0]:40 0.0001440218 +85 prog_clk[0]:40 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +86 prog_clk[0]:62 prog_clk[0]:61 0.004805804 +87 prog_clk[0]:63 prog_clk[0]:62 0.00341 +88 prog_clk[0]:33 prog_clk[0]:32 0.0045 +89 prog_clk[0]:34 prog_clk[0]:33 0.00341 +90 prog_clk[0]:32 prog_clk[0]:31 0.001395089 +91 prog_clk[0]:31 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +92 prog_clk[0]:53 prog_clk[0]:52 0.0001847826 +93 prog_clk[0]:54 prog_clk[0]:53 0.0045 +94 prog_clk[0]:54 prog_clk[0]:51 0.004502232 +95 prog_clk[0]:52 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +96 prog_clk[0]:43 prog_clk[0]:42 0.0009843751 +97 prog_clk[0]:44 prog_clk[0]:43 0.0045 +98 prog_clk[0]:42 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +99 prog_clk[0]:72 prog_clk[0]:71 0.001435268 +100 prog_clk[0]:23 prog_clk[0]:22 0.001174107 +101 prog_clk[0]:78 prog_clk[0]:77 0.0004107143 +102 prog_clk[0]:70 prog_clk[0]:69 0.002073661 +103 prog_clk[0]:35 prog_clk[0]:34 0.000215025 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[0] 0.003081622 //LENGTH 22.255 LUMPCC 0.001113779 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 59.645 22.780 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 69.800 14.620 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 66.415 11.900 +*N mux_tree_tapbuf_size2_7_sram[0]:3 *C 66.415 11.900 +*N mux_tree_tapbuf_size2_7_sram[0]:4 *C 66.240 11.900 +*N mux_tree_tapbuf_size2_7_sram[0]:5 *C 66.240 11.945 +*N mux_tree_tapbuf_size2_7_sram[0]:6 *C 69.763 14.620 +*N mux_tree_tapbuf_size2_7_sram[0]:7 *C 66.285 14.620 +*N mux_tree_tapbuf_size2_7_sram[0]:8 *C 66.240 14.620 +*N mux_tree_tapbuf_size2_7_sram[0]:9 *C 66.240 22.735 +*N mux_tree_tapbuf_size2_7_sram[0]:10 *C 66.195 22.780 +*N mux_tree_tapbuf_size2_7_sram[0]:11 *C 59.683 22.780 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_7_sram[0]:3 5.166219e-05 +4 mux_tree_tapbuf_size2_7_sram[0]:4 5.513601e-05 +5 mux_tree_tapbuf_size2_7_sram[0]:5 9.823338e-05 +6 mux_tree_tapbuf_size2_7_sram[0]:6 0.000240771 +7 mux_tree_tapbuf_size2_7_sram[0]:7 0.000240771 +8 mux_tree_tapbuf_size2_7_sram[0]:8 0.0004680756 +9 mux_tree_tapbuf_size2_7_sram[0]:9 0.0003408316 +10 mux_tree_tapbuf_size2_7_sram[0]:10 0.0002346809 +11 mux_tree_tapbuf_size2_7_sram[0]:11 0.0002346809 +12 mux_tree_tapbuf_size2_7_sram[0]:8 chanx_right_in[3]:4 0.000220611 +13 mux_tree_tapbuf_size2_7_sram[0]:8 chanx_right_in[3]:5 7.889525e-05 +14 mux_tree_tapbuf_size2_7_sram[0]:9 chanx_right_in[3]:5 0.000220611 +15 mux_tree_tapbuf_size2_7_sram[0]:5 chanx_right_in[3]:4 7.889525e-05 +16 mux_tree_tapbuf_size2_7_sram[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002573835 +17 mux_tree_tapbuf_size2_7_sram[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002573835 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_7_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_7_sram[0]:6 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_7_sram[0]:7 mux_tree_tapbuf_size2_7_sram[0]:6 0.003104911 +3 mux_tree_tapbuf_size2_7_sram[0]:8 mux_tree_tapbuf_size2_7_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size2_7_sram[0]:8 mux_tree_tapbuf_size2_7_sram[0]:5 0.002388393 +5 mux_tree_tapbuf_size2_7_sram[0]:10 mux_tree_tapbuf_size2_7_sram[0]:9 0.0045 +6 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:8 0.007245536 +7 mux_tree_tapbuf_size2_7_sram[0]:11 mux_tree_tapbuf_size2_7_sram[0]:10 0.005814732 +8 mux_tree_tapbuf_size2_7_sram[0]:4 mux_tree_tapbuf_size2_7_sram[0]:3 9.51087e-05 +9 mux_tree_tapbuf_size2_7_sram[0]:5 mux_tree_tapbuf_size2_7_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size2_7_sram[0]:3 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_5_ccff_tail[0] 0.003103634 //LENGTH 22.550 LUMPCC 0.0005107479 DR + +*CONN +*I mem_bottom_track_5\/FTB_6__37:X O *L 0 *C 77.035 15.300 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 61.815 20.740 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 *C 61.853 20.740 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 *C 65.780 20.740 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 *C 65.780 21.080 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 *C 75.395 21.080 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 *C 75.440 21.035 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 *C 75.440 15.345 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 *C 75.485 15.300 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 *C 76.998 15.300 + +*CAP +0 mem_bottom_track_5\/FTB_6__37:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.0003195326 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0003454105 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.000699615 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0006737371 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0002270823 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0002270823 +8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 4.921306e-05 +9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 4.921306e-05 +10 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 chanx_right_in[6]:6 0.0001545751 +11 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 chanx_right_in[6]:3 2.863419e-05 +12 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 chanx_right_in[6]:5 0.0001545751 +13 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 chanx_right_in[6]:4 2.863419e-05 +14 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 bottom_left_grid_pin_1_[0]:18 1.861672e-06 +15 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 bottom_left_grid_pin_1_[0]:21 7.030298e-05 +16 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 bottom_left_grid_pin_1_[0]:19 1.861672e-06 +17 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 bottom_left_grid_pin_1_[0]:20 7.030298e-05 + +*RES +0 mem_bottom_track_5\/FTB_6__37:X mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.008584822 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0045 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0045 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.005080357 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 0.001350446 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.003506696 +8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0003035715 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009786694 //LENGTH 8.600 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 86.195 39.780 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.005458 *C 86.020 47.770 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.020 47.725 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.020 39.825 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.020 39.780 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.195 39.780 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00043159 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00043159 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.790771e-05 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.558157e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.0045 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.007053572 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.51087e-05 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003776326 //LENGTH 28.160 LUMPCC 0.0007513036 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 75.615 22.780 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 52.345 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 52.383 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.820 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 53.820 19.720 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 56.075 19.720 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 56.120 19.765 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 56.120 22.395 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 56.165 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 69.000 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 69.000 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 75.578 22.780 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.220113e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.617268e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001476562 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001236847 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001474543 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001474543 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0007206675 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0007439971 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0004235322 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0004002026 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_4_sram[1]:10 6.100554e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_4_sram[1]:11 4.06914e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_4_sram[1]:12 1.585332e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_4_sram[1]:13 1.585332e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_4_sram[1]:9 7.179876e-07 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_4_sram[1]:11 6.100554e-05 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_4_sram[1]:8 7.179876e-07 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_4_sram[1]:10 4.06914e-05 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size2_7_sram[0]:11 0.0002573835 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size2_7_sram[0]:10 0.0002573835 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002013393 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002348214 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.005872768 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001283482 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.01145982 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003035715 + +*END + +*D_NET chany_bottom_out[14] 0.001849043 //LENGTH 12.195 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 49.220 4.760 +*P chany_bottom_out[14] O *L 0.7423 *C 46.000 1.210 +*N chany_bottom_out[14]:2 *C 46.000 4.753 +*N chany_bottom_out[14]:3 *C 46.020 4.760 +*N chany_bottom_out[14]:4 *C 51.513 4.760 +*N chany_bottom_out[14]:5 *C 51.520 4.760 +*N chany_bottom_out[14]:6 *C 51.475 4.760 +*N chany_bottom_out[14]:7 *C 49.258 4.760 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 chany_bottom_out[14] 0.0002120777 +2 chany_bottom_out[14]:2 0.0002120777 +3 chany_bottom_out[14]:3 0.000479374 +4 chany_bottom_out[14]:4 0.000479374 +5 chany_bottom_out[14]:5 3.69727e-05 +6 chany_bottom_out[14]:6 0.0002140833 +7 chany_bottom_out[14]:7 0.0002140833 + +*RES +0 ropt_mt_inst_759:X chany_bottom_out[14]:7 0.152 +1 chany_bottom_out[14]:7 chany_bottom_out[14]:6 0.001979911 +2 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.0045 +3 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.00341 +4 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.0008604917 +5 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.00341 +6 chany_bottom_out[14]:2 chany_bottom_out[14] 0.0005549916 + +*END + +*D_NET chany_bottom_out[5] 0.0008970393 //LENGTH 7.135 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 47.380 6.120 +*P chany_bottom_out[5] O *L 0.7423 *C 45.540 1.290 +*N chany_bottom_out[5]:2 *C 45.540 6.075 +*N chany_bottom_out[5]:3 *C 45.585 6.120 +*N chany_bottom_out[5]:4 *C 47.343 6.120 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 chany_bottom_out[5] 0.0002877621 +2 chany_bottom_out[5]:2 0.0002877621 +3 chany_bottom_out[5]:3 0.0001602576 +4 chany_bottom_out[5]:4 0.0001602576 + +*RES +0 ropt_mt_inst_763:X chany_bottom_out[5]:4 0.152 +1 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.001569197 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +3 chany_bottom_out[5]:2 chany_bottom_out[5] 0.004272321 + +*END + +*D_NET ropt_net_141 0.003022984 //LENGTH 22.165 LUMPCC 0.0007114191 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 59.075 9.180 +*I ropt_mt_inst_757:A I *L 0.001766 *C 52.900 4.080 +*N ropt_net_141:2 *C 52.938 4.080 +*N ropt_net_141:3 *C 53.775 4.080 +*N ropt_net_141:4 *C 53.820 4.035 +*N ropt_net_141:5 *C 53.820 3.445 +*N ropt_net_141:6 *C 53.775 3.400 +*N ropt_net_141:7 *C 51.565 3.400 +*N ropt_net_141:8 *C 51.520 3.355 +*N ropt_net_141:9 *C 51.520 2.085 +*N ropt_net_141:10 *C 51.565 2.040 +*N ropt_net_141:11 *C 57.455 2.040 +*N ropt_net_141:12 *C 57.500 2.085 +*N ropt_net_141:13 *C 57.500 9.135 +*N ropt_net_141:14 *C 57.545 9.180 +*N ropt_net_141:15 *C 59.038 9.180 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_141:2 6.11036e-05 +3 ropt_net_141:3 6.11036e-05 +4 ropt_net_141:4 6.021591e-05 +5 ropt_net_141:5 6.021591e-05 +6 ropt_net_141:6 0.0001006371 +7 ropt_net_141:7 0.0001006371 +8 ropt_net_141:8 0.0001242891 +9 ropt_net_141:9 0.0001242891 +10 ropt_net_141:10 0.0003341707 +11 ropt_net_141:11 0.0003341707 +12 ropt_net_141:12 0.0004018458 +13 ropt_net_141:13 0.0004018458 +14 ropt_net_141:14 7.25202e-05 +15 ropt_net_141:15 7.25202e-05 +16 ropt_net_141:2 BUF_net_45:8 4.424376e-05 +17 ropt_net_141:3 BUF_net_45:9 4.424376e-05 +18 ropt_net_141:6 BUF_net_45:9 9.426366e-05 +19 ropt_net_141:7 BUF_net_45:8 9.426366e-05 +20 ropt_net_141:10 ccff_tail[0]:3 0.0001320728 +21 ropt_net_141:11 ccff_tail[0]:4 0.0001320728 +22 ropt_net_141:12 ccff_tail[0]:5 4.189504e-06 +23 ropt_net_141:13 ccff_tail[0]:6 4.189504e-06 +24 ropt_net_141:4 mem_bottom_track_25/net_net_74:5 3.465033e-07 +25 ropt_net_141:5 mem_bottom_track_25/net_net_74:4 3.465033e-07 +26 ropt_net_141:12 mem_bottom_track_25/net_net_74:4 1.01867e-05 +27 ropt_net_141:14 mem_bottom_track_25/net_net_74:6 7.04066e-05 +28 ropt_net_141:13 mem_bottom_track_25/net_net_74:5 1.01867e-05 +29 ropt_net_141:15 mem_bottom_track_25/net_net_74:7 7.04066e-05 + +*RES +0 ropt_mt_inst_733:X ropt_net_141:15 0.152 +1 ropt_net_141:2 ropt_mt_inst_757:A 0.152 +2 ropt_net_141:3 ropt_net_141:2 0.000747768 +3 ropt_net_141:4 ropt_net_141:3 0.0045 +4 ropt_net_141:6 ropt_net_141:5 0.0045 +5 ropt_net_141:5 ropt_net_141:4 0.0005267857 +6 ropt_net_141:7 ropt_net_141:6 0.001973214 +7 ropt_net_141:8 ropt_net_141:7 0.0045 +8 ropt_net_141:10 ropt_net_141:9 0.0045 +9 ropt_net_141:9 ropt_net_141:8 0.001133929 +10 ropt_net_141:11 ropt_net_141:10 0.005258929 +11 ropt_net_141:12 ropt_net_141:11 0.0045 +12 ropt_net_141:14 ropt_net_141:13 0.0045 +13 ropt_net_141:13 ropt_net_141:12 0.006294643 +14 ropt_net_141:15 ropt_net_141:14 0.001332589 + +*END + +*D_NET ropt_net_168 0.0004727806 //LENGTH 3.585 LUMPCC 0.0002002091 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 107.180 63.240 +*I ropt_mt_inst_784:A I *L 0.001766 *C 106.260 61.200 +*N ropt_net_168:2 *C 106.297 61.200 +*N ropt_net_168:3 *C 107.135 61.200 +*N ropt_net_168:4 *C 107.180 61.245 +*N ropt_net_168:5 *C 107.180 63.195 +*N ropt_net_168:6 *C 107.180 63.240 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 ropt_mt_inst_784:A 1e-06 +2 ropt_net_168:2 3.934753e-05 +3 ropt_net_168:3 3.934753e-05 +4 ropt_net_168:4 8.101537e-05 +5 ropt_net_168:5 8.101537e-05 +6 ropt_net_168:6 2.984568e-05 +7 ropt_net_168:2 chanx_right_out[0]:6 4.605005e-05 +8 ropt_net_168:3 chanx_right_out[0]:5 4.605005e-05 +9 ropt_net_168:4 chanx_right_out[0]:4 5.40545e-05 +10 ropt_net_168:5 chanx_right_out[0]:3 5.40545e-05 + +*RES +0 ropt_mt_inst_747:X ropt_net_168:6 0.152 +1 ropt_net_168:2 ropt_mt_inst_784:A 0.152 +2 ropt_net_168:3 ropt_net_168:2 0.000747768 +3 ropt_net_168:4 ropt_net_168:3 0.0045 +4 ropt_net_168:6 ropt_net_168:5 0.0045 +5 ropt_net_168:5 ropt_net_168:4 0.001741071 + +*END + +*D_NET BUF_net_42 0.001409792 //LENGTH 11.800 LUMPCC 0.0003100469 DR + +*CONN +*I BUFT_RR_42:X O *L 0 *C 30.820 14.620 +*I BUFT_P_99:A I *L 0.001766 *C 26.220 9.520 +*N BUF_net_42:2 *C 26.258 9.520 +*N BUF_net_42:3 *C 31.235 9.520 +*N BUF_net_42:4 *C 31.280 9.520 +*N BUF_net_42:5 *C 31.280 14.575 +*N BUF_net_42:6 *C 31.235 14.620 +*N BUF_net_42:7 *C 30.858 14.620 + +*CAP +0 BUFT_RR_42:X 1e-06 +1 BUFT_P_99:A 1e-06 +2 BUF_net_42:2 0.0002962397 +3 BUF_net_42:3 0.0002962397 +4 BUF_net_42:4 0.000223537 +5 BUF_net_42:5 0.0001955593 +6 BUF_net_42:6 4.308487e-05 +7 BUF_net_42:7 4.308487e-05 +8 BUF_net_42:5 chany_bottom_in[11]:9 0.0001550234 +9 BUF_net_42:4 chany_bottom_in[11] 0.0001550234 + +*RES +0 BUFT_RR_42:X BUF_net_42:7 0.152 +1 BUF_net_42:7 BUF_net_42:6 0.0003370536 +2 BUF_net_42:6 BUF_net_42:5 0.0045 +3 BUF_net_42:5 BUF_net_42:4 0.004513392 +4 BUF_net_42:3 BUF_net_42:2 0.004444197 +5 BUF_net_42:4 BUF_net_42:3 0.0045 +6 BUF_net_42:2 BUFT_P_99:A 0.152 + +*END + +*D_NET ropt_net_124 0.001683091 //LENGTH 15.110 LUMPCC 0.0002032346 DR + +*CONN +*I BUFT_RR_51:X O *L 0 *C 71.300 18.360 +*I ropt_mt_inst_740:A I *L 0.001766 *C 69.000 9.520 +*N ropt_net_124:2 *C 69.038 9.520 +*N ropt_net_124:3 *C 69.415 9.520 +*N ropt_net_124:4 *C 69.460 9.565 +*N ropt_net_124:5 *C 69.460 17.295 +*N ropt_net_124:6 *C 69.505 17.340 +*N ropt_net_124:7 *C 72.680 17.340 +*N ropt_net_124:8 *C 72.680 18.360 +*N ropt_net_124:9 *C 71.338 18.360 + +*CAP +0 BUFT_RR_51:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_124:2 5.7284e-05 +3 ropt_net_124:3 5.7284e-05 +4 ropt_net_124:4 0.000320502 +5 ropt_net_124:5 0.000320502 +6 ropt_net_124:6 0.0001869876 +7 ropt_net_124:7 0.0002487173 +8 ropt_net_124:8 0.0001741543 +9 ropt_net_124:9 0.0001124247 +10 ropt_net_124:4 ropt_net_122:4 0.0001016173 +11 ropt_net_124:5 ropt_net_122:5 0.0001016173 + +*RES +0 BUFT_RR_51:X ropt_net_124:9 0.152 +1 ropt_net_124:2 ropt_mt_inst_740:A 0.152 +2 ropt_net_124:3 ropt_net_124:2 0.0003370536 +3 ropt_net_124:4 ropt_net_124:3 0.0045 +4 ropt_net_124:6 ropt_net_124:5 0.0045 +5 ropt_net_124:5 ropt_net_124:4 0.006901786 +6 ropt_net_124:9 ropt_net_124:8 0.001198661 +7 ropt_net_124:7 ropt_net_124:6 0.002834822 +8 ropt_net_124:8 ropt_net_124:7 0.0009107143 + +*END + +*D_NET ropt_net_137 0.001600709 //LENGTH 13.930 LUMPCC 0.0001719357 DR + +*CONN +*I BUFT_RR_63:X O *L 0 *C 100.740 67.320 +*I ropt_mt_inst_753:A I *L 0.001766 *C 106.260 74.800 +*N ropt_net_137:2 *C 106.223 74.800 +*N ropt_net_137:3 *C 104.925 74.800 +*N ropt_net_137:4 *C 104.880 74.755 +*N ropt_net_137:5 *C 104.880 67.365 +*N ropt_net_137:6 *C 104.835 67.320 +*N ropt_net_137:7 *C 100.778 67.320 + +*CAP +0 BUFT_RR_63:X 1e-06 +1 ropt_mt_inst_753:A 1e-06 +2 ropt_net_137:2 0.00011527 +3 ropt_net_137:3 0.00011527 +4 ropt_net_137:4 0.0003798955 +5 ropt_net_137:5 0.0003798955 +6 ropt_net_137:6 0.0002182212 +7 ropt_net_137:7 0.0002182212 +8 ropt_net_137:6 ropt_net_169:2 8.365473e-06 +9 ropt_net_137:6 ropt_net_169:4 7.76024e-05 +10 ropt_net_137:7 ropt_net_169:3 8.365473e-06 +11 ropt_net_137:7 ropt_net_169:5 7.76024e-05 + +*RES +0 BUFT_RR_63:X ropt_net_137:7 0.152 +1 ropt_net_137:2 ropt_mt_inst_753:A 0.152 +2 ropt_net_137:3 ropt_net_137:2 0.001158482 +3 ropt_net_137:4 ropt_net_137:3 0.0045 +4 ropt_net_137:6 ropt_net_137:5 0.0045 +5 ropt_net_137:5 ropt_net_137:4 0.006598215 +6 ropt_net_137:7 ropt_net_137:6 0.003622768 + +*END + +*D_NET mem_bottom_track_25/net_net_74 0.002208123 //LENGTH 16.035 LUMPCC 0.0006421061 DR + +*CONN +*I mem_bottom_track_25\/FTB_8__39:X O *L 0 *C 65.085 8.840 +*I mem_bottom_track_25\/BUFT_RR_88:A I *L 0.001767 *C 57.500 4.080 +*N mem_bottom_track_25/net_net_74:2 *C 57.463 4.080 +*N mem_bottom_track_25/net_net_74:3 *C 56.165 4.080 +*N mem_bottom_track_25/net_net_74:4 *C 56.120 4.125 +*N mem_bottom_track_25/net_net_74:5 *C 56.120 8.795 +*N mem_bottom_track_25/net_net_74:6 *C 56.165 8.840 +*N mem_bottom_track_25/net_net_74:7 *C 65.047 8.840 + +*CAP +0 mem_bottom_track_25\/FTB_8__39:X 1e-06 +1 mem_bottom_track_25\/BUFT_RR_88:A 1e-06 +2 mem_bottom_track_25/net_net_74:2 2.984643e-05 +3 mem_bottom_track_25/net_net_74:3 2.984643e-05 +4 mem_bottom_track_25/net_net_74:4 0.0002079706 +5 mem_bottom_track_25/net_net_74:5 0.0002079706 +6 mem_bottom_track_25/net_net_74:6 0.0005441911 +7 mem_bottom_track_25/net_net_74:7 0.0005441911 +8 mem_bottom_track_25/net_net_74:5 chanx_right_in[1]:4 6.026765e-05 +9 mem_bottom_track_25/net_net_74:4 chanx_right_in[1]:3 6.026765e-05 +10 mem_bottom_track_25/net_net_74:5 ropt_net_139:4 5.288653e-05 +11 mem_bottom_track_25/net_net_74:4 ropt_net_139:5 5.288653e-05 +12 mem_bottom_track_25/net_net_74:7 ropt_net_141:15 7.04066e-05 +13 mem_bottom_track_25/net_net_74:6 ropt_net_141:14 7.04066e-05 +14 mem_bottom_track_25/net_net_74:5 ropt_net_141:4 3.465033e-07 +15 mem_bottom_track_25/net_net_74:5 ropt_net_141:13 1.01867e-05 +16 mem_bottom_track_25/net_net_74:4 ropt_net_141:5 3.465033e-07 +17 mem_bottom_track_25/net_net_74:4 ropt_net_141:12 1.01867e-05 +18 mem_bottom_track_25/net_net_74:3 BUF_net_45:8 6.286517e-05 +19 mem_bottom_track_25/net_net_74:2 BUF_net_45:9 6.286517e-05 +20 mem_bottom_track_25/net_net_74:5 ropt_net_117:4 9.087075e-07 +21 mem_bottom_track_25/net_net_74:5 ropt_net_117:6 3.20085e-07 +22 mem_bottom_track_25/net_net_74:3 ropt_net_117:8 6.286517e-05 +23 mem_bottom_track_25/net_net_74:4 ropt_net_117:7 3.20085e-07 +24 mem_bottom_track_25/net_net_74:4 ropt_net_117:5 9.087075e-07 +25 mem_bottom_track_25/net_net_74:2 ropt_net_117:9 6.286517e-05 + +*RES +0 mem_bottom_track_25\/FTB_8__39:X mem_bottom_track_25/net_net_74:7 0.152 +1 mem_bottom_track_25/net_net_74:7 mem_bottom_track_25/net_net_74:6 0.007930804 +2 mem_bottom_track_25/net_net_74:6 mem_bottom_track_25/net_net_74:5 0.0045 +3 mem_bottom_track_25/net_net_74:5 mem_bottom_track_25/net_net_74:4 0.004169643 +4 mem_bottom_track_25/net_net_74:3 mem_bottom_track_25/net_net_74:2 0.001158482 +5 mem_bottom_track_25/net_net_74:4 mem_bottom_track_25/net_net_74:3 0.0045 +6 mem_bottom_track_25/net_net_74:2 mem_bottom_track_25\/BUFT_RR_88:A 0.152 + +*END + +*D_NET ropt_net_150 0.001844681 //LENGTH 17.515 LUMPCC 0 DR + +*CONN +*I BUFT_P_105:X O *L 0 *C 109.675 40.120 +*I ropt_mt_inst_766:A I *L 0.001766 *C 106.260 53.040 +*N ropt_net_150:2 *C 106.297 53.040 +*N ropt_net_150:3 *C 109.895 53.040 +*N ropt_net_150:4 *C 109.940 52.995 +*N ropt_net_150:5 *C 109.940 40.165 +*N ropt_net_150:6 *C 109.940 40.120 +*N ropt_net_150:7 *C 109.675 40.120 + +*CAP +0 BUFT_P_105:X 1e-06 +1 ropt_mt_inst_766:A 1e-06 +2 ropt_net_150:2 0.0002124678 +3 ropt_net_150:3 0.0002124678 +4 ropt_net_150:4 0.0006620454 +5 ropt_net_150:5 0.0006620454 +6 ropt_net_150:6 4.644042e-05 +7 ropt_net_150:7 4.721445e-05 + +*RES +0 BUFT_P_105:X ropt_net_150:7 0.152 +1 ropt_net_150:2 ropt_mt_inst_766:A 0.152 +2 ropt_net_150:3 ropt_net_150:2 0.003212054 +3 ropt_net_150:4 ropt_net_150:3 0.0045 +4 ropt_net_150:6 ropt_net_150:5 0.0045 +5 ropt_net_150:5 ropt_net_150:4 0.01145536 +6 ropt_net_150:7 ropt_net_150:6 0.0001440218 + +*END + +*D_NET chanx_right_in[11] 0.01109942 //LENGTH 77.420 LUMPCC 0.00557439 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 111.930 58.480 +*I BUFT_RR_52:A I *L 0.001776 *C 70.380 23.120 +*N chanx_right_in[11]:2 *C 70.380 23.120 +*N chanx_right_in[11]:3 *C 70.380 23.165 +*N chanx_right_in[11]:4 *C 70.380 58.422 +*N chanx_right_in[11]:5 *C 70.388 58.480 + +*CAP +0 chanx_right_in[11] 0.0009932867 +1 BUFT_RR_52:A 1e-06 +2 chanx_right_in[11]:2 2.980903e-05 +3 chanx_right_in[11]:3 0.001753823 +4 chanx_right_in[11]:4 0.001753823 +5 chanx_right_in[11]:5 0.0009932867 +6 chanx_right_in[11] chanx_right_in[1] 0.0001110052 +7 chanx_right_in[11] chanx_right_in[1]:14 0.002121772 +8 chanx_right_in[11]:5 chanx_right_in[1]:13 0.002121772 +9 chanx_right_in[11]:5 chanx_right_in[1]:15 0.0001110052 +10 chanx_right_in[11] chanx_right_in[17] 0.0001299088 +11 chanx_right_in[11] chanx_right_in[17]:16 0.0003443721 +12 chanx_right_in[11]:5 chanx_right_in[17]:15 0.0003443721 +13 chanx_right_in[11]:5 chanx_right_in[17]:16 0.0001299088 +14 chanx_right_in[11]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 8.013703e-05 +15 chanx_right_in[11]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 8.013703e-05 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:5 0.006508324 +1 chanx_right_in[11]:2 BUFT_RR_52:A 0.152 +2 chanx_right_in[11]:3 chanx_right_in[11]:2 0.0045 +3 chanx_right_in[11]:4 chanx_right_in[11]:3 0.03147991 +4 chanx_right_in[11]:5 chanx_right_in[11]:4 0.00341 + +*END + +*D_NET chanx_right_in[12] 0.01220922 //LENGTH 109.275 LUMPCC 0.002566641 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 111.930 74.800 +*I ropt_mt_inst_730:A I *L 0.001766 *C 72.680 6.800 +*N chanx_right_in[12]:2 *C 78.200 28.560 +*N chanx_right_in[12]:3 *C 72.718 6.800 +*N chanx_right_in[12]:4 *C 74.015 6.800 +*N chanx_right_in[12]:5 *C 74.060 6.845 +*N chanx_right_in[12]:6 *C 74.060 28.855 +*N chanx_right_in[12]:7 *C 74.105 28.900 +*N chanx_right_in[12]:8 *C 78.200 28.893 +*N chanx_right_in[12]:9 *C 78.200 28.945 +*N chanx_right_in[12]:10 *C 78.200 74.743 +*N chanx_right_in[12]:11 *C 78.208 74.800 + +*CAP +0 chanx_right_in[12] 0.001110923 +1 ropt_mt_inst_730:A 1e-06 +2 chanx_right_in[12]:2 3.659989e-05 +3 chanx_right_in[12]:3 0.0001232117 +4 chanx_right_in[12]:4 0.0001232117 +5 chanx_right_in[12]:5 0.0009426636 +6 chanx_right_in[12]:6 0.0009426636 +7 chanx_right_in[12]:7 0.0003089409 +8 chanx_right_in[12]:8 0.0003455408 +9 chanx_right_in[12]:9 0.002298448 +10 chanx_right_in[12]:10 0.002298448 +11 chanx_right_in[12]:11 0.001110923 +12 chanx_right_in[12] chanx_right_in[8] 0.0004121939 +13 chanx_right_in[12]:9 chanx_right_in[8]:19 7.744887e-05 +14 chanx_right_in[12]:10 chanx_right_in[8]:20 7.744887e-05 +15 chanx_right_in[12]:11 chanx_right_in[8]:21 0.0004121939 +16 chanx_right_in[12] chanx_right_in[19] 0.0002947007 +17 chanx_right_in[12] chanx_right_in[19]:14 4.722027e-05 +18 chanx_right_in[12]:11 chanx_right_in[19]:13 4.722027e-05 +19 chanx_right_in[12]:11 chanx_right_in[19]:14 0.0002947007 +20 chanx_right_in[12]:5 mux_tree_tapbuf_size2_5_sram[0]:9 0.0002215877 +21 chanx_right_in[12]:6 mux_tree_tapbuf_size2_5_sram[0]:10 0.0002215877 +22 chanx_right_in[12]:9 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 8.230876e-05 +23 chanx_right_in[12]:10 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 8.230876e-05 +24 chanx_right_in[12]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001478604 +25 chanx_right_in[12]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001478604 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:11 0.005283191 +1 chanx_right_in[12]:3 ropt_mt_inst_730:A 0.152 +2 chanx_right_in[12]:4 chanx_right_in[12]:3 0.001158482 +3 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0045 +4 chanx_right_in[12]:7 chanx_right_in[12]:6 0.0045 +5 chanx_right_in[12]:6 chanx_right_in[12]:5 0.01965179 +6 chanx_right_in[12]:8 chanx_right_in[12]:7 0.00365625 +7 chanx_right_in[12]:8 chanx_right_in[12]:2 0.0001807065 +8 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0045 +9 chanx_right_in[12]:10 chanx_right_in[12]:9 0.04089063 +10 chanx_right_in[12]:11 chanx_right_in[12]:10 0.00341 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001137942 //LENGTH 8.745 LUMPCC 0.0001272453 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 59.975 14.620 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 51.520 14.620 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.558 14.620 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 59.938 14.620 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0005043483 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005043483 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[8]:8 6.362263e-05 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[8]:7 6.362263e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.007482143 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00132335 //LENGTH 9.065 LUMPCC 0.000651298 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 72.505 14.280 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 75.540 9.180 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.502 9.180 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.645 9.180 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.600 9.225 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.600 14.235 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 73.555 14.280 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 72.543 14.280 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001202215 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001202215 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001213961 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001213961 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.340812e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.340812e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[12]:5 0.0001478604 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[12]:6 0.0001478604 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[4] 0.0001114538 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[4]:9 0.0001114538 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_7_sram[1]:3 6.5387e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_7_sram[1]:4 6.5387e-05 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_7_sram[1]:8 9.477848e-07 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_7_sram[1]:9 9.477848e-07 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004473215 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET chanx_right_in[13] 0.01356389 //LENGTH 83.065 LUMPCC 0.008796482 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 111.930 36.720 +*I BUFT_P_95:A I *L 0.001776 *C 46.000 20.400 +*N chanx_right_in[13]:2 *C 46.038 20.400 +*N chanx_right_in[13]:3 *C 48.715 20.400 +*N chanx_right_in[13]:4 *C 48.760 20.445 +*N chanx_right_in[13]:5 *C 48.760 36.663 +*N chanx_right_in[13]:6 *C 48.768 36.720 +*N chanx_right_in[13]:7 *C 98.595 36.720 + +*CAP +0 chanx_right_in[13] 0.0003267983 +1 BUFT_P_95:A 1e-06 +2 chanx_right_in[13]:2 0.0001392694 +3 chanx_right_in[13]:3 0.0001392694 +4 chanx_right_in[13]:4 0.000770786 +5 chanx_right_in[13]:5 0.000770786 +6 chanx_right_in[13]:6 0.001146351 +7 chanx_right_in[13]:7 0.001473149 +8 chanx_right_in[13] chanx_right_in[9] 0.0001111674 +9 chanx_right_in[13] chanx_right_in[9]:19 0.0005141352 +10 chanx_right_in[13]:6 chanx_right_in[9]:17 0.001816079 +11 chanx_right_in[13]:6 chanx_right_in[9]:18 0.0009959164 +12 chanx_right_in[13]:7 chanx_right_in[9]:18 0.002330214 +13 chanx_right_in[13]:7 chanx_right_in[9]:19 0.0009959164 +14 chanx_right_in[13]:7 chanx_right_in[9]:20 0.0001111674 +15 chanx_right_in[13] chanx_right_in[18] 0.0001567234 +16 chanx_right_in[13]:6 chanx_right_in[18]:6 0.0001368079 +17 chanx_right_in[13]:7 chanx_right_in[18] 0.0001368079 +18 chanx_right_in[13]:7 chanx_right_in[18]:6 0.0001567234 +19 chanx_right_in[13]:6 chany_bottom_in[14]:7 0.0005726922 +20 chanx_right_in[13]:7 chany_bottom_in[14]:6 0.0005726922 +21 chanx_right_in[13]:2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 3.982181e-05 +22 chanx_right_in[13]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 3.982181e-05 +23 chanx_right_in[13]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 5.489729e-05 +24 chanx_right_in[13]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 5.489729e-05 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:7 0.00208915 +1 chanx_right_in[13]:2 BUFT_P_95:A 0.152 +2 chanx_right_in[13]:3 chanx_right_in[13]:2 0.002390625 +3 chanx_right_in[13]:4 chanx_right_in[13]:3 0.0045 +4 chanx_right_in[13]:5 chanx_right_in[13]:4 0.01447991 +5 chanx_right_in[13]:6 chanx_right_in[13]:5 0.00341 +6 chanx_right_in[13]:7 chanx_right_in[13]:6 0.007806308 + +*END + +*D_NET chanx_right_in[15] 0.01364496 //LENGTH 119.190 LUMPCC 0.003616998 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 111.930 55.760 +*I ropt_mt_inst_732:A I *L 0.001767 *C 41.400 9.520 +*N chanx_right_in[15]:2 *C 41.438 9.520 +*N chanx_right_in[15]:3 *C 44.575 9.520 +*N chanx_right_in[15]:4 *C 44.620 9.565 +*N chanx_right_in[15]:5 *C 44.620 10.155 +*N chanx_right_in[15]:6 *C 44.665 10.200 +*N chanx_right_in[15]:7 *C 52.395 10.200 +*N chanx_right_in[15]:8 *C 52.440 10.245 +*N chanx_right_in[15]:9 *C 52.440 39.055 +*N chanx_right_in[15]:10 *C 52.440 39.100 +*N chanx_right_in[15]:11 *C 52.375 39.433 +*N chanx_right_in[15]:12 *C 52.435 39.440 +*N chanx_right_in[15]:13 *C 56.075 39.440 +*N chanx_right_in[15]:14 *C 56.120 39.485 +*N chanx_right_in[15]:15 *C 56.120 55.703 +*N chanx_right_in[15]:16 *C 56.128 55.760 +*N chanx_right_in[15]:17 *C 105.955 55.760 + +*CAP +0 chanx_right_in[15] 0.0002295223 +1 ropt_mt_inst_732:A 1e-06 +2 chanx_right_in[15]:2 0.0001360766 +3 chanx_right_in[15]:3 0.0001360766 +4 chanx_right_in[15]:4 5.507263e-05 +5 chanx_right_in[15]:5 5.507263e-05 +6 chanx_right_in[15]:6 0.0004209883 +7 chanx_right_in[15]:7 0.0004209883 +8 chanx_right_in[15]:8 0.00133601 +9 chanx_right_in[15]:9 0.00133601 +10 chanx_right_in[15]:10 5.4243e-05 +11 chanx_right_in[15]:11 3.962195e-05 +12 chanx_right_in[15]:12 0.0002094093 +13 chanx_right_in[15]:13 0.0001964622 +14 chanx_right_in[15]:14 0.0007833068 +15 chanx_right_in[15]:15 0.0007833068 +16 chanx_right_in[15]:16 0.001802634 +17 chanx_right_in[15]:17 0.002032157 +18 chanx_right_in[15] chanx_right_in[1] 0.0001195435 +19 chanx_right_in[15] chanx_right_in[1]:14 1.55327e-05 +20 chanx_right_in[15]:9 chanx_right_in[1]:6 4.627724e-05 +21 chanx_right_in[15]:8 chanx_right_in[1]:5 4.627724e-05 +22 chanx_right_in[15]:14 chanx_right_in[1]:5 2.931324e-05 +23 chanx_right_in[15]:15 chanx_right_in[1]:6 2.931324e-05 +24 chanx_right_in[15]:16 chanx_right_in[1]:13 0.0006461455 +25 chanx_right_in[15]:17 chanx_right_in[1]:13 1.55327e-05 +26 chanx_right_in[15]:17 chanx_right_in[1]:14 0.0006461455 +27 chanx_right_in[15]:17 chanx_right_in[1]:15 0.0001195435 +28 chanx_right_in[15]:9 chany_bottom_in[5]:16 1.74719e-05 +29 chanx_right_in[15]:8 chany_bottom_in[5]:17 1.74719e-05 +30 chanx_right_in[15]:16 chany_bottom_in[5]:15 0.0003523834 +31 chanx_right_in[15]:17 chany_bottom_in[5]:14 0.0003523834 +32 chanx_right_in[15]:9 optlc_net_112:5 0.0001449728 +33 chanx_right_in[15]:9 optlc_net_112:8 0.0001010323 +34 chanx_right_in[15]:8 optlc_net_112:9 0.0001010323 +35 chanx_right_in[15]:8 optlc_net_112:8 0.0001449728 +36 chanx_right_in[15]:7 ropt_net_142:2 1.620068e-05 +37 chanx_right_in[15]:7 ropt_net_142:4 0.0001895609 +38 chanx_right_in[15]:6 ropt_net_142:5 0.0001895609 +39 chanx_right_in[15]:6 ropt_net_142:3 1.620068e-05 +40 chanx_right_in[15]:3 ropt_net_142:4 0.0001300652 +41 chanx_right_in[15]:2 ropt_net_142:5 0.0001300652 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:17 0.0009360833 +1 chanx_right_in[15]:10 chanx_right_in[15]:9 0.0045 +2 chanx_right_in[15]:9 chanx_right_in[15]:8 0.02572322 +3 chanx_right_in[15]:7 chanx_right_in[15]:6 0.006901786 +4 chanx_right_in[15]:8 chanx_right_in[15]:7 0.0045 +5 chanx_right_in[15]:6 chanx_right_in[15]:5 0.0045 +6 chanx_right_in[15]:5 chanx_right_in[15]:4 0.0005267857 +7 chanx_right_in[15]:3 chanx_right_in[15]:2 0.002801339 +8 chanx_right_in[15]:4 chanx_right_in[15]:3 0.0045 +9 chanx_right_in[15]:2 ropt_mt_inst_732:A 0.152 +10 chanx_right_in[15]:13 chanx_right_in[15]:12 0.00325 +11 chanx_right_in[15]:14 chanx_right_in[15]:13 0.0045 +12 chanx_right_in[15]:15 chanx_right_in[15]:14 0.01447991 +13 chanx_right_in[15]:16 chanx_right_in[15]:15 0.00341 +14 chanx_right_in[15]:11 chanx_right_in[15]:10 0.0001807065 +15 chanx_right_in[15]:12 chanx_right_in[15]:11 4.83871e-05 +16 chanx_right_in[15]:17 chanx_right_in[15]:16 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.002952167 //LENGTH 23.645 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 83.565 49.980 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.155 44.540 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 87.040 39.440 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 87.002 39.440 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 83.305 39.440 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 83.260 39.485 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 75.193 44.540 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 83.215 44.540 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 83.260 44.540 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 83.260 49.935 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 83.260 49.980 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 83.565 49.980 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 0.0002747421 +4 mux_tree_tapbuf_size2_2_sram[0]:4 0.0002747421 +5 mux_tree_tapbuf_size2_2_sram[0]:5 0.0002652736 +6 mux_tree_tapbuf_size2_2_sram[0]:6 0.0005734452 +7 mux_tree_tapbuf_size2_2_sram[0]:7 0.0005734452 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.0005914751 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.000295565 +10 mux_tree_tapbuf_size2_2_sram[0]:10 5.236796e-05 +11 mux_tree_tapbuf_size2_2_sram[0]:11 4.811081e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:4 mux_tree_tapbuf_size2_2_sram[0]:3 0.003301339 +2 mux_tree_tapbuf_size2_2_sram[0]:5 mux_tree_tapbuf_size2_2_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size2_2_sram[0]:3 mux_right_track_8\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.004816964 +6 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.0001657609 +7 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 0.007162947 +8 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:5 0.004513393 +10 mux_tree_tapbuf_size2_2_sram[0]:6 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[1] 0.001439077 //LENGTH 12.155 LUMPCC 0.0002063499 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.345 20.400 +*I mem_bottom_track_5\/FTB_6__37:A I *L 0.001746 *C 80.040 14.960 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 80.400 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:3 *C 80.385 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:4 *C 80.062 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:5 *C 80.040 9.565 +*N mux_tree_tapbuf_size2_5_sram[1]:6 *C 80.040 14.960 +*N mux_tree_tapbuf_size2_5_sram[1]:7 *C 80.040 14.960 +*N mux_tree_tapbuf_size2_5_sram[1]:8 *C 80.040 20.355 +*N mux_tree_tapbuf_size2_5_sram[1]:9 *C 80.040 20.400 +*N mux_tree_tapbuf_size2_5_sram[1]:10 *C 80.345 20.400 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_5\/FTB_6__37:A 1e-06 +2 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[1]:3 7.053856e-05 +4 mux_tree_tapbuf_size2_5_sram[1]:4 7.053856e-05 +5 mux_tree_tapbuf_size2_5_sram[1]:5 0.0002485383 +6 mux_tree_tapbuf_size2_5_sram[1]:6 3.343028e-05 +7 mux_tree_tapbuf_size2_5_sram[1]:7 0.0004957826 +8 mux_tree_tapbuf_size2_5_sram[1]:8 0.0002183624 +9 mux_tree_tapbuf_size2_5_sram[1]:9 4.828876e-05 +10 mux_tree_tapbuf_size2_5_sram[1]:10 4.42479e-05 +11 mux_tree_tapbuf_size2_5_sram[1]:5 chany_bottom_in[4]:6 2.947745e-05 +12 mux_tree_tapbuf_size2_5_sram[1]:7 chany_bottom_in[4]:5 2.947745e-05 +13 mux_tree_tapbuf_size2_5_sram[1]:7 chany_bottom_in[4]:6 7.369748e-05 +14 mux_tree_tapbuf_size2_5_sram[1]:8 chany_bottom_in[4]:5 7.369748e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_5_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_5_sram[1]:3 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_5_sram[1]:4 mux_tree_tapbuf_size2_5_sram[1]:3 0.0001752718 +3 mux_tree_tapbuf_size2_5_sram[1]:5 mux_tree_tapbuf_size2_5_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_5_sram[1]:6 mem_bottom_track_5\/FTB_6__37:A 0.152 +5 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:5 0.004816964 +7 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:7 0.004816964 +9 mux_tree_tapbuf_size2_5_sram[1]:10 mux_tree_tapbuf_size2_5_sram[1]:9 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.002017906 //LENGTH 17.660 LUMPCC 0.0001646175 DR + +*CONN +*I mem_right_track_4\/FTB_2__33:X O *L 0 *C 91.765 52.700 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 77.915 49.980 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 77.915 49.980 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 77.740 49.980 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 77.740 50.025 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 77.740 52.655 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 *C 77.785 52.700 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 *C 91.728 52.700 + +*CAP +0 mem_right_track_4\/FTB_2__33:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 4.730258e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 5.146833e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0001029381 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0001029381 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.0007733209 +7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.0007733209 +8 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 chanx_right_in[12]:9 8.230876e-05 +9 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 chanx_right_in[12]:10 8.230876e-05 + +*RES +0 mem_right_track_4\/FTB_2__33:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.01244866 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006357501 //LENGTH 5.305 LUMPCC 7.876887e-05 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 97.805 47.940 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 99.460 50.660 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 99.422 50.660 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 98.945 50.660 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 98.900 50.615 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 98.900 47.985 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 98.855 47.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 97.843 47.940 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.383484e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.383484e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001165045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001165045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.715131e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.715131e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_111:10 2.230707e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_111:7 1.707737e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_111:11 2.230707e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_111:10 1.707737e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0002343385 //LENGTH 2.040 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 95.505 37.060 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 97.330 36.920 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 97.293 37.013 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 95.543 37.060 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001161693 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001161693 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0015625 + +*END + +*D_NET optlc_net_112 0.002033266 //LENGTH 14.710 LUMPCC 0.0004920101 DR + +*CONN +*I optlc_113:HI O *L 0 *C 55.660 11.560 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 51.350 15.300 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 52.730 20.740 +*N optlc_net_112:3 *C 52.730 20.740 +*N optlc_net_112:4 *C 52.900 20.740 +*N optlc_net_112:5 *C 52.900 20.695 +*N optlc_net_112:6 *C 51.388 15.300 +*N optlc_net_112:7 *C 52.855 15.300 +*N optlc_net_112:8 *C 52.900 15.300 +*N optlc_net_112:9 *C 52.900 11.605 +*N optlc_net_112:10 *C 52.945 11.560 +*N optlc_net_112:11 *C 55.623 11.560 + +*CAP +0 optlc_113:HI 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +3 optlc_net_112:3 5.893477e-05 +4 optlc_net_112:4 6.184643e-05 +5 optlc_net_112:5 0.0002115665 +6 optlc_net_112:6 0.0001320933 +7 optlc_net_112:7 0.0001320933 +8 optlc_net_112:8 0.0003876007 +9 optlc_net_112:9 0.0001425668 +10 optlc_net_112:10 0.0002057768 +11 optlc_net_112:11 0.0002057768 +12 optlc_net_112:9 chanx_right_in[15]:8 0.0001010323 +13 optlc_net_112:5 chanx_right_in[15]:9 0.0001449728 +14 optlc_net_112:8 chanx_right_in[15]:8 0.0001449728 +15 optlc_net_112:8 chanx_right_in[15]:9 0.0001010323 + +*RES +0 optlc_113:HI optlc_net_112:11 0.152 +1 optlc_net_112:11 optlc_net_112:10 0.002390625 +2 optlc_net_112:10 optlc_net_112:9 0.0045 +3 optlc_net_112:9 optlc_net_112:8 0.003299107 +4 optlc_net_112:4 optlc_net_112:3 9.239131e-05 +5 optlc_net_112:5 optlc_net_112:4 0.0045 +6 optlc_net_112:3 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 +7 optlc_net_112:7 optlc_net_112:6 0.001310268 +8 optlc_net_112:8 optlc_net_112:7 0.0045 +9 optlc_net_112:8 optlc_net_112:5 0.004816964 +10 optlc_net_112:6 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET chany_bottom_out[8] 0.0007151514 //LENGTH 5.560 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 70.840 4.760 +*P chany_bottom_out[8] O *L 0.7423 *C 69.460 1.325 +*N chany_bottom_out[8]:2 *C 69.460 3.400 +*N chany_bottom_out[8]:3 *C 69.920 3.400 +*N chany_bottom_out[8]:4 *C 69.920 4.715 +*N chany_bottom_out[8]:5 *C 69.965 4.760 +*N chany_bottom_out[8]:6 *C 70.803 4.760 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 chany_bottom_out[8] 0.0001366988 +2 chany_bottom_out[8]:2 0.0001663308 +3 chany_bottom_out[8]:3 0.0001395281 +4 chany_bottom_out[8]:4 0.0001098962 +5 chany_bottom_out[8]:5 8.084875e-05 +6 chany_bottom_out[8]:6 8.084875e-05 + +*RES +0 ropt_mt_inst_762:X chany_bottom_out[8]:6 0.152 +1 chany_bottom_out[8]:5 chany_bottom_out[8]:4 0.0045 +2 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.001174107 +3 chany_bottom_out[8]:6 chany_bottom_out[8]:5 0.0007477679 +4 chany_bottom_out[8]:2 chany_bottom_out[8] 0.001852679 +5 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0004107143 + +*END + +*D_NET chany_bottom_out[11] 0.001393923 //LENGTH 9.580 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 51.980 6.120 +*P chany_bottom_out[11] O *L 0.7423 *C 48.300 1.325 +*N chany_bottom_out[11]:2 *C 48.300 3.355 +*N chany_bottom_out[11]:3 *C 48.345 3.400 +*N chany_bottom_out[11]:4 *C 50.555 3.400 +*N chany_bottom_out[11]:5 *C 50.600 3.445 +*N chany_bottom_out[11]:6 *C 50.600 6.075 +*N chany_bottom_out[11]:7 *C 50.645 6.120 +*N chany_bottom_out[11]:8 *C 51.943 6.120 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 chany_bottom_out[11] 0.0001430585 +2 chany_bottom_out[11]:2 0.0001430585 +3 chany_bottom_out[11]:3 0.0001881481 +4 chany_bottom_out[11]:4 0.0001881481 +5 chany_bottom_out[11]:5 0.0002254314 +6 chany_bottom_out[11]:6 0.0002254314 +7 chany_bottom_out[11]:7 0.0001398236 +8 chany_bottom_out[11]:8 0.0001398236 + +*RES +0 ropt_mt_inst_764:X chany_bottom_out[11]:8 0.152 +1 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +2 chany_bottom_out[11]:2 chany_bottom_out[11] 0.0018125 +3 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.001973214 +4 chany_bottom_out[11]:5 chany_bottom_out[11]:4 0.0045 +5 chany_bottom_out[11]:7 chany_bottom_out[11]:6 0.0045 +6 chany_bottom_out[11]:6 chany_bottom_out[11]:5 0.002348214 +7 chany_bottom_out[11]:8 chany_bottom_out[11]:7 0.001158482 + +*END + +*D_NET ropt_net_167 0.0009866705 //LENGTH 8.010 LUMPCC 0.0003136089 DR + +*CONN +*I ropt_mt_inst_741:X O *L 0 *C 102.580 45.560 +*I ropt_mt_inst_783:A I *L 0.001766 *C 106.260 42.160 +*N ropt_net_167:2 *C 106.223 42.160 +*N ropt_net_167:3 *C 103.545 42.160 +*N ropt_net_167:4 *C 103.500 42.205 +*N ropt_net_167:5 *C 103.500 45.515 +*N ropt_net_167:6 *C 103.455 45.560 +*N ropt_net_167:7 *C 102.618 45.560 + +*CAP +0 ropt_mt_inst_741:X 1e-06 +1 ropt_mt_inst_783:A 1e-06 +2 ropt_net_167:2 0.0001120044 +3 ropt_net_167:3 0.0001120044 +4 ropt_net_167:4 0.0001674959 +5 ropt_net_167:5 0.0001674959 +6 ropt_net_167:6 5.603053e-05 +7 ropt_net_167:7 5.603053e-05 +8 ropt_net_167:7 chany_bottom_in[9]:2 2.166722e-05 +9 ropt_net_167:6 chany_bottom_in[9]:3 2.166722e-05 +10 ropt_net_167:5 chany_bottom_in[9]:4 2.205968e-05 +11 ropt_net_167:4 chany_bottom_in[9]:5 2.205968e-05 +12 ropt_net_167:5 chany_bottom_in[19]:4 8.032206e-08 +13 ropt_net_167:3 chany_bottom_in[19]:7 0.0001129972 +14 ropt_net_167:4 chany_bottom_in[19]:5 8.032206e-08 +15 ropt_net_167:2 chany_bottom_in[19]:6 0.0001129972 + +*RES +0 ropt_mt_inst_741:X ropt_net_167:7 0.152 +1 ropt_net_167:7 ropt_net_167:6 0.0007477679 +2 ropt_net_167:6 ropt_net_167:5 0.0045 +3 ropt_net_167:5 ropt_net_167:4 0.002955357 +4 ropt_net_167:3 ropt_net_167:2 0.002390625 +5 ropt_net_167:4 ropt_net_167:3 0.0045 +6 ropt_net_167:2 ropt_mt_inst_783:A 0.152 + +*END + +*D_NET ropt_net_151 0.001233647 //LENGTH 9.780 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 110.135 93.160 +*I ropt_mt_inst_767:A I *L 0.001767 *C 101.660 93.840 +*N ropt_net_151:2 *C 101.660 93.840 +*N ropt_net_151:3 *C 101.660 93.795 +*N ropt_net_151:4 *C 101.660 93.205 +*N ropt_net_151:5 *C 101.705 93.160 +*N ropt_net_151:6 *C 110.098 93.160 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 ropt_mt_inst_767:A 1e-06 +2 ropt_net_151:2 3.654e-05 +3 ropt_net_151:3 4.901982e-05 +4 ropt_net_151:4 4.901982e-05 +5 ropt_net_151:5 0.0005485338 +6 ropt_net_151:6 0.0005485338 + +*RES +0 ropt_mt_inst_751:X ropt_net_151:6 0.152 +1 ropt_net_151:6 ropt_net_151:5 0.007493304 +2 ropt_net_151:5 ropt_net_151:4 0.0045 +3 ropt_net_151:4 ropt_net_151:3 0.0005267857 +4 ropt_net_151:2 ropt_mt_inst_767:A 0.152 +5 ropt_net_151:3 ropt_net_151:2 0.0045 + +*END + +*D_NET chanx_right_out[14] 0.001456874 //LENGTH 12.920 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_767:X O *L 0 *C 102.580 94.180 +*P chanx_right_out[14] O *L 0.7423 *C 111.930 91.120 +*N chanx_right_out[14]:2 *C 102.588 91.120 +*N chanx_right_out[14]:3 *C 102.580 91.178 +*N chanx_right_out[14]:4 *C 102.580 94.135 +*N chanx_right_out[14]:5 *C 102.580 94.180 + +*CAP +0 ropt_mt_inst_767:X 1e-06 +1 chanx_right_out[14] 0.0005497053 +2 chanx_right_out[14]:2 0.0005497053 +3 chanx_right_out[14]:3 0.0001634142 +4 chanx_right_out[14]:4 0.0001634142 +5 chanx_right_out[14]:5 2.963505e-05 + +*RES +0 ropt_mt_inst_767:X chanx_right_out[14]:5 0.152 +1 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +2 chanx_right_out[14]:4 chanx_right_out[14]:3 0.002640625 +3 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +4 chanx_right_out[14]:2 chanx_right_out[14] 0.001463658 + +*END + +*D_NET ropt_net_122 0.002819044 //LENGTH 24.155 LUMPCC 0.0009134892 DR + +*CONN +*I BUFT_RR_52:X O *L 0 *C 67.915 23.460 +*I ropt_mt_inst_738:A I *L 0.001766 *C 65.320 4.080 +*N ropt_net_122:2 *C 65.358 4.080 +*N ropt_net_122:3 *C 68.495 4.080 +*N ropt_net_122:4 *C 68.540 4.125 +*N ropt_net_122:5 *C 68.540 23.415 +*N ropt_net_122:6 *C 68.495 23.460 +*N ropt_net_122:7 *C 67.953 23.460 + +*CAP +0 BUFT_RR_52:X 1e-06 +1 ropt_mt_inst_738:A 1e-06 +2 ropt_net_122:2 0.000218494 +3 ropt_net_122:3 0.000218494 +4 ropt_net_122:4 0.0006774708 +5 ropt_net_122:5 0.0006774708 +6 ropt_net_122:6 5.581262e-05 +7 ropt_net_122:7 5.581262e-05 +8 ropt_net_122:5 chanx_right_in[5]:13 0.0001891183 +9 ropt_net_122:4 chanx_right_in[5]:12 0.0001891183 +10 ropt_net_122:5 chany_bottom_out[7]:4 8.821252e-05 +11 ropt_net_122:3 chany_bottom_out[7]:3 7.444386e-06 +12 ropt_net_122:4 chany_bottom_out[7]:3 8.821252e-05 +13 ropt_net_122:2 chany_bottom_out[7]:2 7.444386e-06 +14 ropt_net_122:5 ropt_net_145:3 6.13713e-05 +15 ropt_net_122:3 ropt_net_145:6 8.980812e-06 +16 ropt_net_122:4 ropt_net_145:4 6.13713e-05 +17 ropt_net_122:2 ropt_net_145:5 8.980812e-06 +18 ropt_net_122:5 ropt_net_124:5 0.0001016173 +19 ropt_net_122:4 ropt_net_124:4 0.0001016173 + +*RES +0 BUFT_RR_52:X ropt_net_122:7 0.152 +1 ropt_net_122:7 ropt_net_122:6 0.000484375 +2 ropt_net_122:6 ropt_net_122:5 0.0045 +3 ropt_net_122:5 ropt_net_122:4 0.01722321 +4 ropt_net_122:3 ropt_net_122:2 0.002801339 +5 ropt_net_122:4 ropt_net_122:3 0.0045 +6 ropt_net_122:2 ropt_mt_inst_738:A 0.152 + +*END + +*D_NET chany_bottom_out[9] 0.0009484761 //LENGTH 7.115 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 27.335 6.120 +*P chany_bottom_out[9] O *L 0.7423 *C 25.760 1.325 +*N chany_bottom_out[9]:2 *C 25.760 2.040 +*N chany_bottom_out[9]:3 *C 26.220 2.040 +*N chany_bottom_out[9]:4 *C 26.220 6.075 +*N chany_bottom_out[9]:5 *C 26.265 6.120 +*N chany_bottom_out[9]:6 *C 27.298 6.120 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 chany_bottom_out[9] 4.848439e-05 +2 chany_bottom_out[9]:2 7.73689e-05 +3 chany_bottom_out[9]:3 0.0003105492 +4 chany_bottom_out[9]:4 0.0002816647 +5 chany_bottom_out[9]:5 0.0001147045 +6 chany_bottom_out[9]:6 0.0001147045 + +*RES +0 ropt_mt_inst_775:X chany_bottom_out[9]:6 0.152 +1 chany_bottom_out[9]:6 chany_bottom_out[9]:5 0.000921875 +2 chany_bottom_out[9]:5 chany_bottom_out[9]:4 0.0045 +3 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.003602679 +4 chany_bottom_out[9]:2 chany_bottom_out[9] 0.0006383929 +5 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0004107143 + +*END + +*D_NET chanx_right_out[6] 0.0007570919 //LENGTH 6.010 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 110.135 80.920 +*P chanx_right_out[6] O *L 0.7423 *C 111.930 84.320 +*N chanx_right_out[6]:2 *C 110.868 84.320 +*N chanx_right_out[6]:3 *C 110.860 84.263 +*N chanx_right_out[6]:4 *C 110.860 80.965 +*N chanx_right_out[6]:5 *C 110.815 80.920 +*N chanx_right_out[6]:6 *C 110.172 80.920 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 chanx_right_out[6] 0.0001081763 +2 chanx_right_out[6]:2 0.0001081763 +3 chanx_right_out[6]:3 0.0002052423 +4 chanx_right_out[6]:4 0.0002052423 +5 chanx_right_out[6]:5 6.462725e-05 +6 chanx_right_out[6]:6 6.462725e-05 + +*RES +0 ropt_mt_inst_778:X chanx_right_out[6]:6 0.152 +1 chanx_right_out[6]:6 chanx_right_out[6]:5 0.0005736608 +2 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +3 chanx_right_out[6]:4 chanx_right_out[6]:3 0.002944197 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 0.0001664583 + +*END + +*D_NET chanx_right_out[17] 0.0005442813 //LENGTH 4.665 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 110.135 90.440 +*P chanx_right_out[17] O *L 0.7423 *C 111.863 88.400 +*N chanx_right_out[17]:2 *C 111.780 88.400 +*N chanx_right_out[17]:3 *C 111.780 88.458 +*N chanx_right_out[17]:4 *C 111.780 90.395 +*N chanx_right_out[17]:5 *C 111.735 90.440 +*N chanx_right_out[17]:6 *C 110.172 90.440 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 chanx_right_out[17] 3.245552e-05 +2 chanx_right_out[17]:2 3.245552e-05 +3 chanx_right_out[17]:3 0.0001216258 +4 chanx_right_out[17]:4 0.0001216258 +5 chanx_right_out[17]:5 0.0001175594 +6 chanx_right_out[17]:6 0.0001175594 + +*RES +0 ropt_mt_inst_780:X chanx_right_out[17]:6 0.152 +1 chanx_right_out[17]:6 chanx_right_out[17]:5 0.001395089 +2 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.001729911 +4 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +5 chanx_right_out[17]:2 chanx_right_out[17] 2.35e-05 + +*END + +*D_NET ropt_net_117 0.002522813 //LENGTH 18.730 LUMPCC 0.0005250936 DR + +*CONN +*I BUFT_RR_79:X O *L 0 *C 62.100 4.420 +*I ropt_mt_inst_733:A I *L 0.001766 *C 55.200 9.520 +*N ropt_net_117:2 *C 55.163 9.520 +*N ropt_net_117:3 *C 52.945 9.520 +*N ropt_net_117:4 *C 52.900 9.475 +*N ropt_net_117:5 *C 52.900 6.800 +*N ropt_net_117:6 *C 52.440 6.800 +*N ropt_net_117:7 *C 52.440 4.465 +*N ropt_net_117:8 *C 52.485 4.420 +*N ropt_net_117:9 *C 62.062 4.420 + +*CAP +0 BUFT_RR_79:X 1e-06 +1 ropt_mt_inst_733:A 1e-06 +2 ropt_net_117:2 0.0001821411 +3 ropt_net_117:3 0.0001821411 +4 ropt_net_117:4 0.0001749938 +5 ropt_net_117:5 0.0002064339 +6 ropt_net_117:6 0.0001895547 +7 ropt_net_117:7 0.0001581146 +8 ropt_net_117:8 0.0004511699 +9 ropt_net_117:9 0.0004511699 +10 ropt_net_117:9 ropt_net_139:7 7.496439e-05 +11 ropt_net_117:8 ropt_net_139:6 7.496439e-05 +12 ropt_net_117:9 BUF_net_45:9 0.0001234885 +13 ropt_net_117:8 BUF_net_45:8 0.0001234885 +14 ropt_net_117:9 mem_bottom_track_25/net_net_74:2 6.286517e-05 +15 ropt_net_117:8 mem_bottom_track_25/net_net_74:3 6.286517e-05 +16 ropt_net_117:7 mem_bottom_track_25/net_net_74:4 3.20085e-07 +17 ropt_net_117:4 mem_bottom_track_25/net_net_74:5 9.087075e-07 +18 ropt_net_117:6 mem_bottom_track_25/net_net_74:5 3.20085e-07 +19 ropt_net_117:5 mem_bottom_track_25/net_net_74:4 9.087075e-07 + +*RES +0 BUFT_RR_79:X ropt_net_117:9 0.152 +1 ropt_net_117:9 ropt_net_117:8 0.00855134 +2 ropt_net_117:8 ropt_net_117:7 0.0045 +3 ropt_net_117:7 ropt_net_117:6 0.002084821 +4 ropt_net_117:3 ropt_net_117:2 0.001979911 +5 ropt_net_117:4 ropt_net_117:3 0.0045 +6 ropt_net_117:2 ropt_mt_inst_733:A 0.152 +7 ropt_net_117:6 ropt_net_117:5 0.0004107143 +8 ropt_net_117:5 ropt_net_117:4 0.002388393 + +*END + +*D_NET ropt_net_115 0.001041249 //LENGTH 7.910 LUMPCC 0.0001425423 DR + +*CONN +*I BUFT_P_93:X O *L 0 *C 42.780 14.620 +*I ropt_mt_inst_731:A I *L 0.001766 *C 46.460 12.240 +*N ropt_net_115:2 *C 46.498 12.240 +*N ropt_net_115:3 *C 46.875 12.240 +*N ropt_net_115:4 *C 46.920 12.285 +*N ropt_net_115:5 *C 46.920 14.575 +*N ropt_net_115:6 *C 46.875 14.620 +*N ropt_net_115:7 *C 42.818 14.620 + +*CAP +0 BUFT_P_93:X 1e-06 +1 ropt_mt_inst_731:A 1e-06 +2 ropt_net_115:2 7.088998e-05 +3 ropt_net_115:3 7.088998e-05 +4 ropt_net_115:4 0.0001045835 +5 ropt_net_115:5 0.0001045835 +6 ropt_net_115:6 0.0002728801 +7 ropt_net_115:7 0.0002728801 +8 ropt_net_115:4 chany_bottom_in[15] 7.127113e-05 +9 ropt_net_115:5 chany_bottom_in[15]:18 7.127113e-05 + +*RES +0 BUFT_P_93:X ropt_net_115:7 0.152 +1 ropt_net_115:2 ropt_mt_inst_731:A 0.152 +2 ropt_net_115:3 ropt_net_115:2 0.0003370536 +3 ropt_net_115:4 ropt_net_115:3 0.0045 +4 ropt_net_115:6 ropt_net_115:5 0.0045 +5 ropt_net_115:5 ropt_net_115:4 0.002044643 +6 ropt_net_115:7 ropt_net_115:6 0.003622768 + +*END + +*D_NET chanx_right_in[17] 0.01418524 //LENGTH 136.645 LUMPCC 0.002364173 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 111.930 61.200 +*I ropt_mt_inst_735:A I *L 0.001767 *C 34.500 4.080 +*N chanx_right_in[17]:2 *C 34.538 4.080 +*N chanx_right_in[17]:3 *C 37.675 4.080 +*N chanx_right_in[17]:4 *C 37.720 4.125 +*N chanx_right_in[17]:5 *C 37.720 14.915 +*N chanx_right_in[17]:6 *C 37.765 14.960 +*N chanx_right_in[17]:7 *C 38.595 14.960 +*N chanx_right_in[17]:8 *C 38.640 15.005 +*N chanx_right_in[17]:9 *C 38.640 36.675 +*N chanx_right_in[17]:10 *C 38.685 36.720 +*N chanx_right_in[17]:11 *C 48.615 36.720 +*N chanx_right_in[17]:12 *C 51.015 36.720 +*N chanx_right_in[17]:13 *C 51.060 36.765 +*N chanx_right_in[17]:14 *C 51.060 61.143 +*N chanx_right_in[17]:15 *C 51.068 61.200 +*N chanx_right_in[17]:16 *C 100.895 61.200 + +*CAP +0 chanx_right_in[17] 0.0003550658 +1 ropt_mt_inst_735:A 1e-06 +2 chanx_right_in[17]:2 0.0001981904 +3 chanx_right_in[17]:3 0.0001981904 +4 chanx_right_in[17]:4 0.0004648581 +5 chanx_right_in[17]:5 0.0004648581 +6 chanx_right_in[17]:6 6.215896e-05 +7 chanx_right_in[17]:7 6.215896e-05 +8 chanx_right_in[17]:8 0.001031707 +9 chanx_right_in[17]:9 0.001031707 +10 chanx_right_in[17]:10 0.0005056519 +11 chanx_right_in[17]:11 0.0006351191 +12 chanx_right_in[17]:12 0.0001294672 +13 chanx_right_in[17]:13 0.001134337 +14 chanx_right_in[17]:14 0.001134337 +15 chanx_right_in[17]:15 0.0020286 +16 chanx_right_in[17]:16 0.002383666 +17 chanx_right_in[17] chanx_right_in[5] 0.0001066661 +18 chanx_right_in[17] chanx_right_in[5]:20 8.068379e-05 +19 chanx_right_in[17]:15 chanx_right_in[5]:19 0.0004447889 +20 chanx_right_in[17]:16 chanx_right_in[5]:19 8.068379e-05 +21 chanx_right_in[17]:16 chanx_right_in[5]:20 0.0004447889 +22 chanx_right_in[17]:16 chanx_right_in[5]:21 0.0001066661 +23 chanx_right_in[17] chanx_right_in[11] 0.0001299088 +24 chanx_right_in[17]:15 chanx_right_in[11]:5 0.0003443721 +25 chanx_right_in[17]:16 chanx_right_in[11] 0.0003443721 +26 chanx_right_in[17]:16 chanx_right_in[11]:5 0.0001299088 +27 chanx_right_in[17]:4 ropt_net_118:4 7.566671e-05 +28 chanx_right_in[17]:5 ropt_net_118:5 7.566671e-05 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:16 0.001728817 +1 chanx_right_in[17]:2 ropt_mt_inst_735:A 0.152 +2 chanx_right_in[17]:3 chanx_right_in[17]:2 0.00280134 +3 chanx_right_in[17]:4 chanx_right_in[17]:3 0.0045 +4 chanx_right_in[17]:6 chanx_right_in[17]:5 0.0045 +5 chanx_right_in[17]:5 chanx_right_in[17]:4 0.009633929 +6 chanx_right_in[17]:7 chanx_right_in[17]:6 0.0007410714 +7 chanx_right_in[17]:8 chanx_right_in[17]:7 0.0045 +8 chanx_right_in[17]:10 chanx_right_in[17]:9 0.0045 +9 chanx_right_in[17]:9 chanx_right_in[17]:8 0.01934822 +10 chanx_right_in[17]:12 chanx_right_in[17]:11 0.002142857 +11 chanx_right_in[17]:13 chanx_right_in[17]:12 0.0045 +12 chanx_right_in[17]:14 chanx_right_in[17]:13 0.02176563 +13 chanx_right_in[17]:15 chanx_right_in[17]:14 0.00341 +14 chanx_right_in[17]:11 chanx_right_in[17]:10 0.008866072 +15 chanx_right_in[17]:16 chanx_right_in[17]:15 0.007806308 + +*END + +*D_NET chanx_right_in[19] 0.01557975 //LENGTH 153.405 LUMPCC 0.003410767 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 111.930 72.080 +*I ropt_mt_inst_743:A I *L 0.001767 *C 28.060 6.800 +*N chanx_right_in[19]:2 *C 28.023 6.800 +*N chanx_right_in[19]:3 *C 27.185 6.800 +*N chanx_right_in[19]:4 *C 27.140 6.845 +*N chanx_right_in[19]:5 *C 27.140 12.535 +*N chanx_right_in[19]:6 *C 27.185 12.580 +*N chanx_right_in[19]:7 *C 29.900 12.580 +*N chanx_right_in[19]:8 *C 29.900 12.240 +*N chanx_right_in[19]:9 *C 32.155 12.240 +*N chanx_right_in[19]:10 *C 32.200 12.285 +*N chanx_right_in[19]:11 *C 32.200 62.080 +*N chanx_right_in[19]:12 *C 32.200 72.023 +*N chanx_right_in[19]:13 *C 32.208 72.080 +*N chanx_right_in[19]:14 *C 82.035 72.080 + +*CAP +0 chanx_right_in[19] 0.001083533 +1 ropt_mt_inst_743:A 1e-06 +2 chanx_right_in[19]:2 3.719916e-05 +3 chanx_right_in[19]:3 3.719916e-05 +4 chanx_right_in[19]:4 0.0003450906 +5 chanx_right_in[19]:5 0.0003450906 +6 chanx_right_in[19]:6 0.0001861967 +7 chanx_right_in[19]:7 0.0002137923 +8 chanx_right_in[19]:8 0.0001768265 +9 chanx_right_in[19]:9 0.0001492309 +10 chanx_right_in[19]:10 0.001654328 +11 chanx_right_in[19]:11 0.002020043 +12 chanx_right_in[19]:12 0.0003657152 +13 chanx_right_in[19]:13 0.002235103 +14 chanx_right_in[19]:14 0.003318636 +15 chanx_right_in[19]:10 chanx_right_in[0]:4 0.0002209021 +16 chanx_right_in[19]:12 chanx_right_in[0]:5 1.260426e-05 +17 chanx_right_in[19]:12 chanx_right_in[0]:6 3.455915e-05 +18 chanx_right_in[19]:11 chanx_right_in[0]:4 1.260426e-05 +19 chanx_right_in[19]:11 chanx_right_in[0]:5 0.0002554613 +20 chanx_right_in[19]:2 chanx_right_in[9]:6 4.442843e-05 +21 chanx_right_in[19]:3 chanx_right_in[9]:5 4.442843e-05 +22 chanx_right_in[19]:4 chanx_right_in[9]:7 4.295883e-05 +23 chanx_right_in[19]:5 chanx_right_in[9]:8 4.295883e-05 +24 chanx_right_in[19]:10 chanx_right_in[9]:15 0.0002658574 +25 chanx_right_in[19]:11 chanx_right_in[9]:16 0.0002658574 +26 chanx_right_in[19] chanx_right_in[12] 0.0002947007 +27 chanx_right_in[19]:13 chanx_right_in[12]:11 4.722027e-05 +28 chanx_right_in[19]:14 chanx_right_in[12] 4.722027e-05 +29 chanx_right_in[19]:14 chanx_right_in[12]:11 0.0002947007 +30 chanx_right_in[19] chany_bottom_in[0]:7 0.0002607428 +31 chanx_right_in[19]:13 chany_bottom_in[0]:8 0.0001620051 +32 chanx_right_in[19]:14 chany_bottom_in[0]:7 0.0001620051 +33 chanx_right_in[19]:14 chany_bottom_in[0]:8 0.0002607428 +34 chanx_right_in[19]:10 chany_bottom_in[11] 0.0001561096 +35 chanx_right_in[19]:10 chany_bottom_in[11]:9 0.0001019456 +36 chanx_right_in[19]:12 chany_bottom_in[11]:8 6.134901e-05 +37 chanx_right_in[19]:11 chany_bottom_in[11]:8 0.0001019456 +38 chanx_right_in[19]:11 chany_bottom_in[11]:9 0.0002174586 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:14 0.00468355 +1 chanx_right_in[19]:2 ropt_mt_inst_743:A 0.152 +2 chanx_right_in[19]:3 chanx_right_in[19]:2 0.0007477679 +3 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +4 chanx_right_in[19]:6 chanx_right_in[19]:5 0.0045 +5 chanx_right_in[19]:5 chanx_right_in[19]:4 0.005080357 +6 chanx_right_in[19]:9 chanx_right_in[19]:8 0.002013393 +7 chanx_right_in[19]:10 chanx_right_in[19]:9 0.0045 +8 chanx_right_in[19]:12 chanx_right_in[19]:11 0.008877233 +9 chanx_right_in[19]:13 chanx_right_in[19]:12 0.00341 +10 chanx_right_in[19]:7 chanx_right_in[19]:6 0.002424107 +11 chanx_right_in[19]:8 chanx_right_in[19]:7 0.0003035715 +12 chanx_right_in[19]:11 chanx_right_in[19]:10 0.04445983 +13 chanx_right_in[19]:14 chanx_right_in[19]:13 0.007806308 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..955eb81 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef @@ -0,0 +1,30901 @@ +*SPEF "1481-1998" +*DESIGN "sb_1__0_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 30.820 102.680 +chany_top_in[0] I *C 80.500 102.680 +chany_top_in[1] I *C 57.500 102.680 +chany_top_in[2] I *C 82.340 102.680 +chany_top_in[3] I *C 74.060 102.680 +chany_top_in[4] I *C 51.980 102.680 +chany_top_in[5] I *C 60.260 102.680 +chany_top_in[6] I *C 74.980 102.680 +chany_top_in[7] I *C 66.700 102.680 +chany_top_in[8] I *C 72.220 102.680 +chany_top_in[9] I *C 67.620 102.680 +chany_top_in[10] I *C 73.140 102.680 +chany_top_in[11] I *C 75.900 102.680 +chany_top_in[12] I *C 52.900 102.680 +chany_top_in[13] I *C 63.480 102.680 +chany_top_in[14] I *C 54.740 102.680 +chany_top_in[15] I *C 53.820 102.680 +chany_top_in[16] I *C 69.460 102.680 +chany_top_in[17] I *C 81.420 102.680 +chany_top_in[18] I *C 84.640 102.680 +chany_top_in[19] I *C 59.340 102.680 +top_left_grid_pin_34_[0] I *C 33.120 102.680 +top_left_grid_pin_35_[0] I *C 33.120 102.680 +top_left_grid_pin_36_[0] I *C 29.210 99.960 +top_left_grid_pin_37_[0] I *C 32.200 102.680 +top_left_grid_pin_38_[0] I *C 29.210 97.920 +top_left_grid_pin_39_[0] I *C 29.210 96.560 +top_left_grid_pin_40_[0] I *C 29.210 95.200 +top_left_grid_pin_41_[0] I *C 29.210 90.440 +chanx_right_in[0] I *C 140.990 46.240 +chanx_right_in[1] I *C 140.990 16.320 +chanx_right_in[2] I *C 140.990 12.240 +chanx_right_in[3] I *C 140.990 8.160 +chanx_right_in[4] I *C 140.990 13.600 +chanx_right_in[5] I *C 140.990 9.520 +chanx_right_in[6] I *C 140.990 31.280 +chanx_right_in[7] I *C 140.990 47.600 +chanx_right_in[8] I *C 140.990 14.960 +chanx_right_in[9] I *C 140.990 72.080 +chanx_right_in[10] I *C 140.990 25.840 +chanx_right_in[11] I *C 140.990 29.920 +chanx_right_in[12] I *C 140.990 19.040 +chanx_right_in[13] I *C 140.990 44.880 +chanx_right_in[14] I *C 140.990 17.680 +chanx_right_in[15] I *C 140.990 42.160 +chanx_right_in[16] I *C 140.990 4.080 +chanx_right_in[17] I *C 140.990 63.920 +chanx_right_in[18] I *C 140.990 50.320 +chanx_right_in[19] I *C 140.990 58.480 +right_top_grid_pin_42_[0] I *C 138.460 75.480 +right_top_grid_pin_43_[0] I *C 112.470 99.280 +right_top_grid_pin_44_[0] I *C 139.380 75.480 +right_top_grid_pin_45_[0] I *C 137.540 75.480 +right_top_grid_pin_46_[0] I *C 112.470 91.800 +right_top_grid_pin_47_[0] I *C 112.470 90.440 +right_top_grid_pin_48_[0] I *C 135.700 75.480 +right_top_grid_pin_49_[0] I *C 136.620 75.480 +right_bottom_grid_pin_1_[0] I *C 139.380 0.680 +chanx_left_in[0] I *C 0.690 67.320 +chanx_left_in[1] I *C 0.690 54.400 +chanx_left_in[2] I *C 0.690 51.680 +chanx_left_in[3] I *C 0.690 53.040 +chanx_left_in[4] I *C 0.690 62.560 +chanx_left_in[5] I *C 0.690 50.320 +chanx_left_in[6] I *C 0.690 47.600 +chanx_left_in[7] I *C 0.690 70.720 +chanx_left_in[8] I *C 0.690 32.640 +chanx_left_in[9] I *C 0.690 72.080 +chanx_left_in[10] I *C 0.690 57.120 +chanx_left_in[11] I *C 0.690 69.360 +chanx_left_in[12] I *C 0.690 36.720 +chanx_left_in[13] I *C 0.690 44.880 +chanx_left_in[14] I *C 0.690 6.800 +chanx_left_in[15] I *C 0.690 42.160 +chanx_left_in[16] I *C 0.690 28.560 +chanx_left_in[17] I *C 0.690 19.040 +chanx_left_in[18] I *C 0.690 5.440 +chanx_left_in[19] I *C 0.690 4.080 +left_top_grid_pin_42_[0] I *C 7.360 75.480 +left_top_grid_pin_43_[0] I *C 29.210 91.800 +left_top_grid_pin_44_[0] I *C 4.140 75.480 +left_top_grid_pin_45_[0] I *C 5.060 75.480 +left_top_grid_pin_46_[0] I *C 2.300 75.480 +left_top_grid_pin_47_[0] I *C 3.220 75.480 +left_top_grid_pin_48_[0] I *C 11.500 75.480 +left_top_grid_pin_49_[0] I *C 10.580 75.480 +left_bottom_grid_pin_1_[0] I *C 2.300 0.680 +ccff_head[0] I *C 138.460 0.680 +chany_top_out[0] O *C 76.820 102.680 +chany_top_out[1] O *C 61.180 102.680 +chany_top_out[2] O *C 77.740 102.680 +chany_top_out[3] O *C 71.300 102.680 +chany_top_out[4] O *C 98.900 102.680 +chany_top_out[5] O *C 83.720 102.680 +chany_top_out[6] O *C 70.380 102.680 +chany_top_out[7] O *C 50.140 102.680 +chany_top_out[8] O *C 68.540 102.680 +chany_top_out[9] O *C 58.420 102.680 +chany_top_out[10] O *C 96.600 102.680 +chany_top_out[11] O *C 93.840 102.680 +chany_top_out[12] O *C 79.580 102.680 +chany_top_out[13] O *C 64.400 102.680 +chany_top_out[14] O *C 97.520 102.680 +chany_top_out[15] O *C 51.060 102.680 +chany_top_out[16] O *C 86.940 102.680 +chany_top_out[17] O *C 62.100 102.680 +chany_top_out[18] O *C 95.680 102.680 +chany_top_out[19] O *C 78.660 102.680 +chanx_right_out[0] O *C 140.990 59.840 +chanx_right_out[1] O *C 140.990 66.640 +chanx_right_out[2] O *C 140.990 6.800 +chanx_right_out[3] O *C 140.990 68.000 +chanx_right_out[4] O *C 140.990 35.360 +chanx_right_out[5] O *C 140.990 57.120 +chanx_right_out[6] O *C 140.990 28.560 +chanx_right_out[7] O *C 140.990 51.680 +chanx_right_out[8] O *C 140.990 34.000 +chanx_right_out[9] O *C 140.990 40.800 +chanx_right_out[10] O *C 140.990 24.480 +chanx_right_out[11] O *C 140.990 55.760 +chanx_right_out[12] O *C 140.990 69.360 +chanx_right_out[13] O *C 140.990 61.200 +chanx_right_out[14] O *C 140.990 23.120 +chanx_right_out[15] O *C 140.990 39.440 +chanx_right_out[16] O *C 140.990 36.720 +chanx_right_out[17] O *C 140.990 62.560 +chanx_right_out[18] O *C 140.990 20.400 +chanx_right_out[19] O *C 140.990 53.040 +chanx_left_out[0] O *C 0.690 27.200 +chanx_left_out[1] O *C 0.690 64.600 +chanx_left_out[2] O *C 0.690 15.640 +chanx_left_out[3] O *C 0.690 59.840 +chanx_left_out[4] O *C 0.690 11.560 +chanx_left_out[5] O *C 0.690 61.200 +chanx_left_out[6] O *C 0.690 25.840 +chanx_left_out[7] O *C 0.690 48.960 +chanx_left_out[8] O *C 0.690 21.760 +chanx_left_out[9] O *C 0.690 34.000 +chanx_left_out[10] O *C 0.690 20.400 +chanx_left_out[11] O *C 0.690 38.080 +chanx_left_out[12] O *C 0.690 23.120 +chanx_left_out[13] O *C 0.690 65.960 +chanx_left_out[14] O *C 0.690 17.680 +chanx_left_out[15] O *C 0.690 39.440 +chanx_left_out[16] O *C 0.690 31.280 +chanx_left_out[17] O *C 0.690 43.520 +chanx_left_out[18] O *C 0.690 10.200 +chanx_left_out[19] O *C 0.690 58.480 +ccff_tail[0] O *C 0.690 55.760 +VDD I *C 70.840 51.680 +VSS I *C 70.840 51.680 + +*D_NET top_left_grid_pin_35_[0] 0.02097017 //LENGTH 145.055 LUMPCC 0.00650173 DR + +*CONN +*P top_left_grid_pin_35_[0] I *L 0.29796 *C 33.120 102.075 +*I FTB_1__0:A I *L 0.001776 *C 52.900 99.280 +*I mux_top_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 49.320 88.740 +*I mux_top_track_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 79.120 52.700 +*I mux_top_track_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 115.000 56.100 +*N top_left_grid_pin_35_[0]:5 *C 114.963 56.100 +*N top_left_grid_pin_35_[0]:6 *C 112.285 56.100 +*N top_left_grid_pin_35_[0]:7 *C 112.240 56.100 +*N top_left_grid_pin_35_[0]:8 *C 112.240 56.440 +*N top_left_grid_pin_35_[0]:9 *C 112.233 56.440 +*N top_left_grid_pin_35_[0]:10 *C 79.120 52.700 +*N top_left_grid_pin_35_[0]:11 *C 79.120 52.745 +*N top_left_grid_pin_35_[0]:12 *C 79.120 56.383 +*N top_left_grid_pin_35_[0]:13 *C 79.120 56.440 +*N top_left_grid_pin_35_[0]:14 *C 78.220 56.440 +*N top_left_grid_pin_35_[0]:15 *C 78.200 56.448 +*N top_left_grid_pin_35_[0]:16 *C 78.200 88.392 +*N top_left_grid_pin_35_[0]:17 *C 78.180 88.400 +*N top_left_grid_pin_35_[0]:18 *C 49.220 88.740 +*N top_left_grid_pin_35_[0]:19 *C 49.220 88.740 +*N top_left_grid_pin_35_[0]:20 *C 49.220 88.400 +*N top_left_grid_pin_35_[0]:21 *C 49.227 88.400 +*N top_left_grid_pin_35_[0]:22 *C 48.775 88.400 +*N top_left_grid_pin_35_[0]:23 *C 48.760 88.407 +*N top_left_grid_pin_35_[0]:24 *C 52.900 99.280 +*N top_left_grid_pin_35_[0]:25 *C 52.900 99.235 +*N top_left_grid_pin_35_[0]:26 *C 52.900 97.978 +*N top_left_grid_pin_35_[0]:27 *C 52.893 97.920 +*N top_left_grid_pin_35_[0]:28 *C 48.780 97.920 +*N top_left_grid_pin_35_[0]:29 *C 48.760 97.920 +*N top_left_grid_pin_35_[0]:30 *C 48.760 101.312 +*N top_left_grid_pin_35_[0]:31 *C 48.760 101.325 +*N top_left_grid_pin_35_[0]:32 *C 48.760 102.000 +*N top_left_grid_pin_35_[0]:33 *C 32.200 102.000 +*N top_left_grid_pin_35_[0]:34 *C 32.200 101.325 +*N top_left_grid_pin_35_[0]:35 *C 32.208 101.320 +*N top_left_grid_pin_35_[0]:36 *C 33.120 101.320 + +*CAP +0 top_left_grid_pin_35_[0] 7.524232e-05 +1 FTB_1__0:A 1e-06 +2 mux_top_track_2\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_10\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_35_[0]:5 0.0001789104 +6 top_left_grid_pin_35_[0]:6 0.0001789104 +7 top_left_grid_pin_35_[0]:7 4.980993e-05 +8 top_left_grid_pin_35_[0]:8 5.367423e-05 +9 top_left_grid_pin_35_[0]:9 0.001591533 +10 top_left_grid_pin_35_[0]:10 3.252207e-05 +11 top_left_grid_pin_35_[0]:11 0.000157902 +12 top_left_grid_pin_35_[0]:12 0.0001579019 +13 top_left_grid_pin_35_[0]:13 0.001599739 +14 top_left_grid_pin_35_[0]:14 8.205388e-06 +15 top_left_grid_pin_35_[0]:15 0.000976161 +16 top_left_grid_pin_35_[0]:16 0.000976161 +17 top_left_grid_pin_35_[0]:17 0.002001178 +18 top_left_grid_pin_35_[0]:18 3.648206e-05 +19 top_left_grid_pin_35_[0]:19 4.962483e-05 +20 top_left_grid_pin_35_[0]:20 5.32877e-05 +21 top_left_grid_pin_35_[0]:21 0.002057325 +22 top_left_grid_pin_35_[0]:22 5.614782e-05 +23 top_left_grid_pin_35_[0]:23 0.0005780382 +24 top_left_grid_pin_35_[0]:24 3.621468e-05 +25 top_left_grid_pin_35_[0]:25 9.553787e-05 +26 top_left_grid_pin_35_[0]:26 9.553787e-05 +27 top_left_grid_pin_35_[0]:27 0.0002666786 +28 top_left_grid_pin_35_[0]:28 0.0002666786 +29 top_left_grid_pin_35_[0]:29 0.0008079725 +30 top_left_grid_pin_35_[0]:30 0.0002299344 +31 top_left_grid_pin_35_[0]:31 5.217136e-05 +32 top_left_grid_pin_35_[0]:32 0.0007486833 +33 top_left_grid_pin_35_[0]:33 0.0007492446 +34 top_left_grid_pin_35_[0]:34 5.273278e-05 +35 top_left_grid_pin_35_[0]:35 5.95268e-05 +36 top_left_grid_pin_35_[0]:36 0.0001347691 +37 top_left_grid_pin_35_[0]:13 chanx_right_in[9]:24 0.000283432 +38 top_left_grid_pin_35_[0]:5 chanx_right_in[9]:25 9.964938e-06 +39 top_left_grid_pin_35_[0]:6 chanx_right_in[9]:26 9.964938e-06 +40 top_left_grid_pin_35_[0]:9 chanx_right_in[9]:29 0.000283432 +41 top_left_grid_pin_35_[0]:28 prog_clk[0]:360 5.533719e-05 +42 top_left_grid_pin_35_[0]:26 prog_clk[0]:354 4.570852e-07 +43 top_left_grid_pin_35_[0]:27 prog_clk[0]:356 5.533719e-05 +44 top_left_grid_pin_35_[0]:25 prog_clk[0]:355 4.570852e-07 +45 top_left_grid_pin_35_[0]:11 prog_clk[0]:292 8.262489e-05 +46 top_left_grid_pin_35_[0]:11 prog_clk[0]:298 2.174178e-05 +47 top_left_grid_pin_35_[0]:12 prog_clk[0]:304 2.174178e-05 +48 top_left_grid_pin_35_[0]:12 prog_clk[0]:298 8.262489e-05 +49 top_left_grid_pin_35_[0]:13 prog_clk[0]:275 4.772648e-06 +50 top_left_grid_pin_35_[0]:13 prog_clk[0]:297 0.0001575478 +51 top_left_grid_pin_35_[0]:13 prog_clk[0]:296 3.38114e-05 +52 top_left_grid_pin_35_[0]:7 prog_clk[0]:115 5.51546e-07 +53 top_left_grid_pin_35_[0]:8 prog_clk[0]:114 5.51546e-07 +54 top_left_grid_pin_35_[0]:9 prog_clk[0]:274 4.772648e-06 +55 top_left_grid_pin_35_[0]:9 prog_clk[0]:296 0.0001575478 +56 top_left_grid_pin_35_[0]:21 prog_clk[0]:177 1.674677e-06 +57 top_left_grid_pin_35_[0]:21 prog_clk[0]:348 6.044598e-08 +58 top_left_grid_pin_35_[0]:21 prog_clk[0]:176 1.091731e-05 +59 top_left_grid_pin_35_[0]:21 prog_clk[0]:183 8.346397e-07 +60 top_left_grid_pin_35_[0]:34 prog_clk[0]:596 6.092859e-06 +61 top_left_grid_pin_35_[0]:14 prog_clk[0]:297 3.38114e-05 +62 top_left_grid_pin_35_[0]:15 prog_clk[0]:306 1.771615e-05 +63 top_left_grid_pin_35_[0]:17 prog_clk[0]:182 8.346397e-07 +64 top_left_grid_pin_35_[0]:17 prog_clk[0]:347 6.044598e-08 +65 top_left_grid_pin_35_[0]:17 prog_clk[0]:171 1.091731e-05 +66 top_left_grid_pin_35_[0]:17 prog_clk[0]:176 1.674677e-06 +67 top_left_grid_pin_35_[0]:16 prog_clk[0]:283 1.771615e-05 +68 top_left_grid_pin_35_[0]:33 prog_clk[0] 6.092859e-06 +69 top_left_grid_pin_35_[0]:33 prog_clk[0]:595 1.438907e-06 +70 top_left_grid_pin_35_[0]:33 prog_clk[0]:594 7.624363e-06 +71 top_left_grid_pin_35_[0]:33 prog_clk[0]:360 3.325795e-06 +72 top_left_grid_pin_35_[0]:32 prog_clk[0]:594 1.438907e-06 +73 top_left_grid_pin_35_[0]:32 prog_clk[0]:360 7.624363e-06 +74 top_left_grid_pin_35_[0]:32 prog_clk[0]:356 3.325795e-06 +75 top_left_grid_pin_35_[0]:13 chany_top_in[16]:11 0.0002879217 +76 top_left_grid_pin_35_[0]:13 chany_top_in[16]:10 1.074806e-05 +77 top_left_grid_pin_35_[0]:9 chany_top_in[16]:10 0.0002879217 +78 top_left_grid_pin_35_[0]:14 chany_top_in[16]:11 1.074806e-05 +79 top_left_grid_pin_35_[0]:28 top_left_grid_pin_34_[0]:40 1.595555e-05 +80 top_left_grid_pin_35_[0]:27 top_left_grid_pin_34_[0]:39 1.595555e-05 +81 top_left_grid_pin_35_[0]:31 top_left_grid_pin_34_[0]:40 1.369984e-06 +82 top_left_grid_pin_35_[0]:35 top_left_grid_pin_34_[0]:42 1.481916e-05 +83 top_left_grid_pin_35_[0]:33 top_left_grid_pin_34_[0]:42 0.0006415492 +84 top_left_grid_pin_35_[0]:33 top_left_grid_pin_34_[0]:40 1.087396e-06 +85 top_left_grid_pin_35_[0]:32 top_left_grid_pin_34_[0]:41 0.0006429192 +86 top_left_grid_pin_35_[0]:32 top_left_grid_pin_34_[0]:39 1.087396e-06 +87 top_left_grid_pin_35_[0]:36 top_left_grid_pin_34_[0]:41 1.481916e-05 +88 top_left_grid_pin_35_[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002732823 +89 top_left_grid_pin_35_[0]:17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002732823 +90 top_left_grid_pin_35_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 6.004905e-05 +91 top_left_grid_pin_35_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 5.869659e-05 +92 top_left_grid_pin_35_[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 6.004905e-05 +93 top_left_grid_pin_35_[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.869659e-05 +94 top_left_grid_pin_35_[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0006203783 +95 top_left_grid_pin_35_[0]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0006203783 +96 top_left_grid_pin_35_[0]:15 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0005650811 +97 top_left_grid_pin_35_[0]:16 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0005650811 + +*RES +0 top_left_grid_pin_35_[0] top_left_grid_pin_35_[0]:36 0.0001182833 +1 top_left_grid_pin_35_[0]:28 top_left_grid_pin_35_[0]:27 0.0006442916 +2 top_left_grid_pin_35_[0]:29 top_left_grid_pin_35_[0]:28 0.00341 +3 top_left_grid_pin_35_[0]:29 top_left_grid_pin_35_[0]:23 0.001490292 +4 top_left_grid_pin_35_[0]:26 top_left_grid_pin_35_[0]:25 0.001122768 +5 top_left_grid_pin_35_[0]:27 top_left_grid_pin_35_[0]:26 0.00341 +6 top_left_grid_pin_35_[0]:24 FTB_1__0:A 0.152 +7 top_left_grid_pin_35_[0]:25 top_left_grid_pin_35_[0]:24 0.0045 +8 top_left_grid_pin_35_[0]:10 mux_top_track_6\/mux_l1_in_0_:A1 0.152 +9 top_left_grid_pin_35_[0]:11 top_left_grid_pin_35_[0]:10 0.0045 +10 top_left_grid_pin_35_[0]:12 top_left_grid_pin_35_[0]:11 0.003247768 +11 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:12 0.00341 +12 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:9 0.005187625 +13 top_left_grid_pin_35_[0]:5 mux_top_track_10\/mux_l1_in_0_:A1 0.152 +14 top_left_grid_pin_35_[0]:6 top_left_grid_pin_35_[0]:5 0.002390625 +15 top_left_grid_pin_35_[0]:7 top_left_grid_pin_35_[0]:6 0.0045 +16 top_left_grid_pin_35_[0]:8 top_left_grid_pin_35_[0]:7 0.0001634615 +17 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:8 0.00341 +18 top_left_grid_pin_35_[0]:20 top_left_grid_pin_35_[0]:19 0.0001634615 +19 top_left_grid_pin_35_[0]:21 top_left_grid_pin_35_[0]:20 0.00341 +20 top_left_grid_pin_35_[0]:21 top_left_grid_pin_35_[0]:17 0.004535892 +21 top_left_grid_pin_35_[0]:18 mux_top_track_2\/mux_l1_in_0_:A1 0.152 +22 top_left_grid_pin_35_[0]:19 top_left_grid_pin_35_[0]:18 0.0045 +23 top_left_grid_pin_35_[0]:22 top_left_grid_pin_35_[0]:21 6.646094e-05 +24 top_left_grid_pin_35_[0]:23 top_left_grid_pin_35_[0]:22 0.00341 +25 top_left_grid_pin_35_[0]:31 top_left_grid_pin_35_[0]:30 0.00341 +26 top_left_grid_pin_35_[0]:30 top_left_grid_pin_35_[0]:29 0.0005314916 +27 top_left_grid_pin_35_[0]:34 top_left_grid_pin_35_[0]:33 0.00010575 +28 top_left_grid_pin_35_[0]:35 top_left_grid_pin_35_[0]:34 0.00341 +29 top_left_grid_pin_35_[0]:14 top_left_grid_pin_35_[0]:13 0.000141 +30 top_left_grid_pin_35_[0]:15 top_left_grid_pin_35_[0]:14 0.00341 +31 top_left_grid_pin_35_[0]:17 top_left_grid_pin_35_[0]:16 0.00341 +32 top_left_grid_pin_35_[0]:16 top_left_grid_pin_35_[0]:15 0.005004716 +33 top_left_grid_pin_35_[0]:33 top_left_grid_pin_35_[0]:32 0.0025944 +34 top_left_grid_pin_35_[0]:32 top_left_grid_pin_35_[0]:31 0.00010575 +35 top_left_grid_pin_35_[0]:36 top_left_grid_pin_35_[0]:35 0.0001429583 + +*END + +*D_NET chanx_left_in[6] 0.02399241 //LENGTH 145.665 LUMPCC 0.0124776 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 47.600 +*I mux_top_track_6\/mux_l1_in_3_:A1 I *L 0.00198 *C 84.640 45.220 +*I mux_right_track_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 131.850 47.940 +*I FTB_18__17:A I *L 0.001767 *C 134.780 47.600 +*N chanx_left_in[6]:4 *C 134.743 47.600 +*N chanx_left_in[6]:5 *C 131.850 47.940 +*N chanx_left_in[6]:6 *C 132.020 47.600 +*N chanx_left_in[6]:7 *C 132.020 47.555 +*N chanx_left_in[6]:8 *C 132.020 43.578 +*N chanx_left_in[6]:9 *C 132.013 43.520 +*N chanx_left_in[6]:10 *C 90.168 43.520 +*N chanx_left_in[6]:11 *C 90.160 43.578 +*N chanx_left_in[6]:12 *C 90.160 45.515 +*N chanx_left_in[6]:13 *C 90.115 45.560 +*N chanx_left_in[6]:14 *C 84.678 45.220 +*N chanx_left_in[6]:15 *C 85.100 45.220 +*N chanx_left_in[6]:16 *C 85.100 45.560 +*N chanx_left_in[6]:17 *C 85.100 45.605 +*N chanx_left_in[6]:18 *C 85.100 47.543 +*N chanx_left_in[6]:19 *C 85.093 47.600 +*N chanx_left_in[6]:20 *C 51.230 47.600 + +*CAP +0 chanx_left_in[6] 0.001863348 +1 mux_top_track_6\/mux_l1_in_3_:A1 1e-06 +2 mux_right_track_8\/mux_l2_in_2_:A0 1e-06 +3 FTB_18__17:A 1e-06 +4 chanx_left_in[6]:4 0.0001947296 +5 chanx_left_in[6]:5 6.636619e-05 +6 chanx_left_in[6]:6 0.0002303129 +7 chanx_left_in[6]:7 0.0003283384 +8 chanx_left_in[6]:8 0.0003283384 +9 chanx_left_in[6]:9 0.001399534 +10 chanx_left_in[6]:10 0.001399534 +11 chanx_left_in[6]:11 0.0001230331 +12 chanx_left_in[6]:12 0.0001230331 +13 chanx_left_in[6]:13 0.0003606009 +14 chanx_left_in[6]:14 4.679161e-05 +15 chanx_left_in[6]:15 8.203692e-05 +16 chanx_left_in[6]:16 0.0003958462 +17 chanx_left_in[6]:17 0.0001438107 +18 chanx_left_in[6]:18 0.0001438107 +19 chanx_left_in[6]:19 0.001209499 +20 chanx_left_in[6]:20 0.003072846 +21 chanx_left_in[6] chanx_right_in[5]:16 3.277589e-05 +22 chanx_left_in[6] chanx_right_in[5]:21 7.723665e-05 +23 chanx_left_in[6]:19 chanx_right_in[5]:25 0.0002839712 +24 chanx_left_in[6]:19 chanx_right_in[5]:26 3.2326e-06 +25 chanx_left_in[6]:20 chanx_right_in[5]:21 0.0003167471 +26 chanx_left_in[6]:20 chanx_right_in[5]:25 8.046925e-05 +27 chanx_left_in[6]:9 chanx_right_in[13] 0.0009026685 +28 chanx_left_in[6]:10 chanx_right_in[13]:37 0.0009026685 +29 chanx_left_in[6]:19 chanx_right_in[13]:34 2.738444e-06 +30 chanx_left_in[6]:20 chanx_right_in[13]:33 2.738444e-06 +31 chanx_left_in[6] chanx_right_in[14]:14 0.001661054 +32 chanx_left_in[6]:19 chanx_right_in[14]:15 0.000770913 +33 chanx_left_in[6]:20 chanx_right_in[14]:14 0.000770913 +34 chanx_left_in[6]:20 chanx_right_in[14]:15 0.001661054 +35 chanx_left_in[6] chanx_left_in[5] 9.756939e-06 +36 chanx_left_in[6] chanx_left_in[5]:29 0.0002107767 +37 chanx_left_in[6]:9 chanx_left_in[5]:23 3.272557e-05 +38 chanx_left_in[6]:10 chanx_left_in[5]:27 3.272557e-05 +39 chanx_left_in[6]:19 chanx_left_in[5]:23 2.480864e-05 +40 chanx_left_in[6]:19 chanx_left_in[5]:27 7.351846e-06 +41 chanx_left_in[6]:20 chanx_left_in[5]:27 2.480864e-05 +42 chanx_left_in[6]:20 chanx_left_in[5]:28 0.0002181286 +43 chanx_left_in[6]:20 chanx_left_in[5]:32 9.756939e-06 +44 chanx_left_in[6]:9 chanx_left_in[14]:8 0.0002067697 +45 chanx_left_in[6]:9 chanx_left_in[14]:14 0.0002177194 +46 chanx_left_in[6]:10 chanx_left_in[14]:15 0.0002177194 +47 chanx_left_in[6]:10 chanx_left_in[14]:14 0.0002067697 +48 chanx_left_in[6]:9 top_left_grid_pin_34_[0]:10 7.551476e-05 +49 chanx_left_in[6]:10 top_left_grid_pin_34_[0]:11 7.551476e-05 +50 chanx_left_in[6]:17 top_left_grid_pin_34_[0]:12 5.641701e-07 +51 chanx_left_in[6]:18 top_left_grid_pin_34_[0]:13 5.641701e-07 +52 chanx_left_in[6]:19 top_left_grid_pin_34_[0]:14 0.0001376853 +53 chanx_left_in[6]:19 top_left_grid_pin_34_[0]:20 0.0005318035 +54 chanx_left_in[6]:20 top_left_grid_pin_34_[0]:21 0.0005318035 +55 chanx_left_in[6]:20 top_left_grid_pin_34_[0]:19 0.0001376853 +56 chanx_left_in[6]:19 chanx_right_in[7]:7 0.0003872563 +57 chanx_left_in[6]:20 chanx_right_in[7]:6 0.0003872563 +58 chanx_left_in[6] left_top_grid_pin_48_[0]:11 0.0004224472 +59 chanx_left_in[6]:20 left_top_grid_pin_48_[0]:10 0.0004224472 +60 chanx_left_in[6]:11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.023335e-05 +61 chanx_left_in[6]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.118456e-05 +62 chanx_left_in[6]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.023335e-05 +63 chanx_left_in[6]:16 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.118456e-05 +64 chanx_left_in[6] ropt_net_141:6 0.0001976113 +65 chanx_left_in[6]:20 ropt_net_141:7 0.0001976113 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:20 0.007833333 +1 chanx_left_in[6]:14 mux_top_track_6\/mux_l1_in_3_:A1 0.152 +2 chanx_left_in[6]:6 chanx_left_in[6]:5 0.0001847826 +3 chanx_left_in[6]:6 chanx_left_in[6]:4 0.002430804 +4 chanx_left_in[6]:7 chanx_left_in[6]:6 0.0045 +5 chanx_left_in[6]:8 chanx_left_in[6]:7 0.003551339 +6 chanx_left_in[6]:9 chanx_left_in[6]:8 0.00341 +7 chanx_left_in[6]:11 chanx_left_in[6]:10 0.00341 +8 chanx_left_in[6]:10 chanx_left_in[6]:9 0.006555717 +9 chanx_left_in[6]:13 chanx_left_in[6]:12 0.0045 +10 chanx_left_in[6]:12 chanx_left_in[6]:11 0.001729911 +11 chanx_left_in[6]:16 chanx_left_in[6]:15 0.0003035715 +12 chanx_left_in[6]:16 chanx_left_in[6]:13 0.004477679 +13 chanx_left_in[6]:17 chanx_left_in[6]:16 0.0045 +14 chanx_left_in[6]:18 chanx_left_in[6]:17 0.001729911 +15 chanx_left_in[6]:19 chanx_left_in[6]:18 0.00341 +16 chanx_left_in[6]:4 FTB_18__17:A 0.152 +17 chanx_left_in[6]:5 mux_right_track_8\/mux_l2_in_2_:A0 0.152 +18 chanx_left_in[6]:15 chanx_left_in[6]:14 0.0003772322 +19 chanx_left_in[6]:20 chanx_left_in[6]:19 0.005305124 + +*END + +*D_NET chanx_left_in[14] 0.02193801 //LENGTH 177.785 LUMPCC 0.007013658 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 6.800 +*I mux_top_track_18\/mux_l1_in_1_:A1 I *L 0.00198 *C 62.005 39.780 +*I mux_right_track_4\/mux_l1_in_6_:A0 I *L 0.001631 *C 112.120 49.980 +*I FTB_24__23:A I *L 0.001776 *C 130.180 42.160 +*N chanx_left_in[14]:4 *C 130.218 42.160 +*N chanx_left_in[14]:5 *C 130.595 42.160 +*N chanx_left_in[14]:6 *C 130.640 42.115 +*N chanx_left_in[14]:7 *C 130.640 41.538 +*N chanx_left_in[14]:8 *C 130.632 41.480 +*N chanx_left_in[14]:9 *C 112.120 49.980 +*N chanx_left_in[14]:10 *C 112.240 50.320 +*N chanx_left_in[14]:11 *C 112.655 50.320 +*N chanx_left_in[14]:12 *C 112.700 50.275 +*N chanx_left_in[14]:13 *C 112.700 41.538 +*N chanx_left_in[14]:14 *C 112.700 41.480 +*N chanx_left_in[14]:15 *C 63.948 41.480 +*N chanx_left_in[14]:16 *C 63.940 41.422 +*N chanx_left_in[14]:17 *C 63.940 39.825 +*N chanx_left_in[14]:18 *C 63.895 39.780 +*N chanx_left_in[14]:19 *C 62.005 39.780 +*N chanx_left_in[14]:20 *C 58.465 39.780 +*N chanx_left_in[14]:21 *C 58.420 39.735 +*N chanx_left_in[14]:22 *C 58.420 6.857 +*N chanx_left_in[14]:23 *C 58.413 6.800 +*N chanx_left_in[14]:24 *C 51.230 6.800 + +*CAP +0 chanx_left_in[14] 0.001860675 +1 mux_top_track_18\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_6_:A0 1e-06 +3 FTB_24__23:A 1e-06 +4 chanx_left_in[14]:4 4.391138e-05 +5 chanx_left_in[14]:5 4.391138e-05 +6 chanx_left_in[14]:6 5.480299e-05 +7 chanx_left_in[14]:7 5.480299e-05 +8 chanx_left_in[14]:8 0.0004804497 +9 chanx_left_in[14]:9 5.28324e-05 +10 chanx_left_in[14]:10 7.613537e-05 +11 chanx_left_in[14]:11 4.999326e-05 +12 chanx_left_in[14]:12 0.00042998 +13 chanx_left_in[14]:13 0.00042998 +14 chanx_left_in[14]:14 0.002645196 +15 chanx_left_in[14]:15 0.002164746 +16 chanx_left_in[14]:16 0.0001120764 +17 chanx_left_in[14]:17 0.0001120764 +18 chanx_left_in[14]:18 0.0001336709 +19 chanx_left_in[14]:19 0.0004463743 +20 chanx_left_in[14]:20 0.0002841664 +21 chanx_left_in[14]:21 0.001471287 +22 chanx_left_in[14]:22 0.001471287 +23 chanx_left_in[14]:23 0.0003211655 +24 chanx_left_in[14]:24 0.002181841 +25 chanx_left_in[14]:8 chanx_left_in[6]:9 0.0002067697 +26 chanx_left_in[14]:15 chanx_left_in[6]:10 0.0002177194 +27 chanx_left_in[14]:14 chanx_left_in[6]:9 0.0002177194 +28 chanx_left_in[14]:14 chanx_left_in[6]:10 0.0002067697 +29 chanx_left_in[14]:8 chanx_left_in[16]:25 0.0002692774 +30 chanx_left_in[14]:15 chanx_left_in[16]:26 0.0008457302 +31 chanx_left_in[14]:14 chanx_left_in[16]:25 0.0008457302 +32 chanx_left_in[14]:14 chanx_left_in[16]:26 0.0002692774 +33 chanx_left_in[14]:8 prog_clk[0]:240 0.0003229805 +34 chanx_left_in[14]:15 prog_clk[0]:241 8.628059e-05 +35 chanx_left_in[14]:13 prog_clk[0]:242 1.621116e-05 +36 chanx_left_in[14]:13 prog_clk[0]:236 1.986931e-06 +37 chanx_left_in[14]:14 prog_clk[0]:241 0.0003229805 +38 chanx_left_in[14]:14 prog_clk[0]:240 8.628059e-05 +39 chanx_left_in[14]:12 prog_clk[0]:242 1.986931e-06 +40 chanx_left_in[14]:12 prog_clk[0]:243 1.621116e-05 +41 chanx_left_in[14]:21 prog_clk[0]:418 1.678655e-05 +42 chanx_left_in[14]:21 prog_clk[0]:416 4.263904e-06 +43 chanx_left_in[14]:21 prog_clk[0]:411 1.841263e-05 +44 chanx_left_in[14]:22 prog_clk[0]:417 4.263904e-06 +45 chanx_left_in[14]:22 prog_clk[0]:410 1.841263e-05 +46 chanx_left_in[14]:22 prog_clk[0]:413 1.678655e-05 +47 chanx_left_in[14]:15 top_left_grid_pin_34_[0]:11 0.0005909223 +48 chanx_left_in[14]:14 top_left_grid_pin_34_[0]:10 0.0005909223 +49 chanx_left_in[14] chanx_left_in[19] 0.0006069721 +50 chanx_left_in[14]:21 chanx_left_in[19]:4 0.0001506353 +51 chanx_left_in[14]:22 chanx_left_in[19]:5 0.0001506353 +52 chanx_left_in[14]:23 chanx_left_in[19]:6 7.498956e-05 +53 chanx_left_in[14]:24 chanx_left_in[19]:7 0.0006819617 +54 chanx_left_in[14]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.688989e-05 +55 chanx_left_in[14]:12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.688989e-05 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:24 0.007833333 +1 chanx_left_in[14]:7 chanx_left_in[14]:6 0.000515625 +2 chanx_left_in[14]:8 chanx_left_in[14]:7 0.00341 +3 chanx_left_in[14]:5 chanx_left_in[14]:4 0.0003370536 +4 chanx_left_in[14]:6 chanx_left_in[14]:5 0.0045 +5 chanx_left_in[14]:4 FTB_24__23:A 0.152 +6 chanx_left_in[14]:16 chanx_left_in[14]:15 0.00341 +7 chanx_left_in[14]:15 chanx_left_in[14]:14 0.007637891 +8 chanx_left_in[14]:18 chanx_left_in[14]:17 0.0045 +9 chanx_left_in[14]:17 chanx_left_in[14]:16 0.001426339 +10 chanx_left_in[14]:13 chanx_left_in[14]:12 0.007801339 +11 chanx_left_in[14]:14 chanx_left_in[14]:13 0.00341 +12 chanx_left_in[14]:14 chanx_left_in[14]:8 0.002809425 +13 chanx_left_in[14]:11 chanx_left_in[14]:10 0.0003705357 +14 chanx_left_in[14]:12 chanx_left_in[14]:11 0.0045 +15 chanx_left_in[14]:9 mux_right_track_4\/mux_l1_in_6_:A0 0.152 +16 chanx_left_in[14]:19 mux_top_track_18\/mux_l1_in_1_:A1 0.152 +17 chanx_left_in[14]:19 chanx_left_in[14]:18 0.0016875 +18 chanx_left_in[14]:20 chanx_left_in[14]:19 0.003160714 +19 chanx_left_in[14]:21 chanx_left_in[14]:20 0.0045 +20 chanx_left_in[14]:22 chanx_left_in[14]:21 0.02935492 +21 chanx_left_in[14]:23 chanx_left_in[14]:22 0.00341 +22 chanx_left_in[14]:10 chanx_left_in[14]:9 0.0003035715 +23 chanx_left_in[14]:24 chanx_left_in[14]:23 0.001125258 + +*END + +*D_NET chany_top_in[2] 0.009484658 //LENGTH 72.985 LUMPCC 0.002037544 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 82.340 102.070 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 85.200 52.700 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 62.925 52.700 +*N chany_top_in[2]:3 *C 62.925 52.700 +*N chany_top_in[2]:4 *C 63.020 52.700 +*N chany_top_in[2]:5 *C 63.020 52.360 +*N chany_top_in[2]:6 *C 63.028 52.360 +*N chany_top_in[2]:7 *C 82.333 52.360 +*N chany_top_in[2]:8 *C 82.340 52.360 +*N chany_top_in[2]:9 *C 85.163 52.700 +*N chany_top_in[2]:10 *C 82.385 52.700 +*N chany_top_in[2]:11 *C 82.340 52.745 + +*CAP +0 chany_top_in[2] 0.002498315 +1 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[2]:3 3.0182e-05 +4 chany_top_in[2]:4 5.737035e-05 +5 chany_top_in[2]:5 6.016791e-05 +6 chany_top_in[2]:6 0.0009330526 +7 chany_top_in[2]:7 0.0009330526 +8 chany_top_in[2]:8 5.461275e-05 +9 chany_top_in[2]:9 0.0001794729 +10 chany_top_in[2]:10 0.0001794729 +11 chany_top_in[2]:11 0.002519415 +12 chany_top_in[2]:7 chanx_right_in[13]:34 0.0003740106 +13 chany_top_in[2]:6 chanx_right_in[13]:33 0.0003740106 +14 chany_top_in[2]:7 top_left_grid_pin_37_[0]:11 0.0002981444 +15 chany_top_in[2]:6 top_left_grid_pin_37_[0]:12 0.0002981444 +16 chany_top_in[2] mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003466169 +17 chany_top_in[2]:11 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003466169 + +*RES +0 chany_top_in[2] chany_top_in[2]:11 0.04404018 +1 chany_top_in[2]:10 chany_top_in[2]:9 0.002479911 +2 chany_top_in[2]:11 chany_top_in[2]:10 0.0045 +3 chany_top_in[2]:11 chany_top_in[2]:8 0.0001850962 +4 chany_top_in[2]:9 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +5 chany_top_in[2]:8 chany_top_in[2]:7 0.00341 +6 chany_top_in[2]:7 chany_top_in[2]:6 0.00302445 +7 chany_top_in[2]:5 chany_top_in[2]:4 0.0001634615 +8 chany_top_in[2]:6 chany_top_in[2]:5 0.00341 +9 chany_top_in[2]:3 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +10 chany_top_in[2]:4 chany_top_in[2]:3 0.0045 + +*END + +*D_NET chany_top_in[7] 0.004846767 //LENGTH 35.865 LUMPCC 0.0003496094 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 66.700 102.070 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.905 88.060 +*I mux_right_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 85.735 91.460 +*N chany_top_in[7]:3 *C 85.698 91.460 +*N chany_top_in[7]:4 *C 84.225 91.460 +*N chany_top_in[7]:5 *C 84.180 91.415 +*N chany_top_in[7]:6 *C 84.180 90.498 +*N chany_top_in[7]:7 *C 84.172 90.440 +*N chany_top_in[7]:8 *C 73.905 88.060 +*N chany_top_in[7]:9 *C 73.600 88.060 +*N chany_top_in[7]:10 *C 73.600 88.105 +*N chany_top_in[7]:11 *C 73.600 90.383 +*N chany_top_in[7]:12 *C 73.600 90.440 +*N chany_top_in[7]:13 *C 66.708 90.440 +*N chany_top_in[7]:14 *C 66.700 90.498 + +*CAP +0 chany_top_in[7] 0.0005246289 +1 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[7]:3 0.0001316505 +4 chany_top_in[7]:4 0.0001316505 +5 chany_top_in[7]:5 7.535169e-05 +6 chany_top_in[7]:6 7.535169e-05 +7 chany_top_in[7]:7 0.000757735 +8 chany_top_in[7]:8 5.041534e-05 +9 chany_top_in[7]:9 5.52456e-05 +10 chany_top_in[7]:10 0.0001664995 +11 chany_top_in[7]:11 0.0001664995 +12 chany_top_in[7]:12 0.001296618 +13 chany_top_in[7]:13 0.0005388826 +14 chany_top_in[7]:14 0.0005246289 +15 chany_top_in[7] mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001748047 +16 chany_top_in[7]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001748047 + +*RES +0 chany_top_in[7] chany_top_in[7]:14 0.01033259 +1 chany_top_in[7]:8 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[7]:9 chany_top_in[7]:8 0.0001657609 +3 chany_top_in[7]:10 chany_top_in[7]:9 0.0045 +4 chany_top_in[7]:11 chany_top_in[7]:10 0.002033482 +5 chany_top_in[7]:12 chany_top_in[7]:11 0.00341 +6 chany_top_in[7]:12 chany_top_in[7]:7 0.001656358 +7 chany_top_in[7]:6 chany_top_in[7]:5 0.0008191965 +8 chany_top_in[7]:7 chany_top_in[7]:6 0.00341 +9 chany_top_in[7]:4 chany_top_in[7]:3 0.001314732 +10 chany_top_in[7]:5 chany_top_in[7]:4 0.0045 +11 chany_top_in[7]:3 mux_right_track_2\/mux_l1_in_0_:A0 0.152 +12 chany_top_in[7]:14 chany_top_in[7]:13 0.00341 +13 chany_top_in[7]:13 chany_top_in[7]:12 0.001079825 + +*END + +*D_NET chany_top_in[12] 0.01207792 //LENGTH 76.270 LUMPCC 0.005012671 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 52.900 102.070 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 41.690 66.300 +*I mux_right_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.935 71.400 +*N chany_top_in[12]:3 *C 71.898 71.400 +*N chany_top_in[12]:4 *C 70.885 71.400 +*N chany_top_in[12]:5 *C 70.840 71.400 +*N chany_top_in[12]:6 *C 70.833 71.400 +*N chany_top_in[12]:7 *C 41.727 66.300 +*N chany_top_in[12]:8 *C 43.195 66.300 +*N chany_top_in[12]:9 *C 43.240 66.345 +*N chany_top_in[12]:10 *C 43.240 66.980 +*N chany_top_in[12]:11 *C 43.700 66.980 +*N chany_top_in[12]:12 *C 43.700 71.343 +*N chany_top_in[12]:13 *C 43.708 71.400 +*N chany_top_in[12]:14 *C 45.080 71.400 +*N chany_top_in[12]:15 *C 45.080 71.407 +*N chany_top_in[12]:16 *C 45.080 100.633 +*N chany_top_in[12]:17 *C 45.100 100.640 +*N chany_top_in[12]:18 *C 52.893 100.640 +*N chany_top_in[12]:19 *C 52.900 100.698 + +*CAP +0 chany_top_in[12] 8.518784e-05 +1 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_32\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[12]:3 8.258413e-05 +4 chany_top_in[12]:4 8.258413e-05 +5 chany_top_in[12]:5 3.679291e-05 +6 chany_top_in[12]:6 0.001305118 +7 chany_top_in[12]:7 9.890024e-05 +8 chany_top_in[12]:8 9.890024e-05 +9 chany_top_in[12]:9 4.092851e-05 +10 chany_top_in[12]:10 7.181809e-05 +11 chany_top_in[12]:11 0.0002455359 +12 chany_top_in[12]:12 0.0002146463 +13 chany_top_in[12]:13 5.43809e-05 +14 chany_top_in[12]:14 0.001359498 +15 chany_top_in[12]:15 0.001262948 +16 chany_top_in[12]:16 0.001262948 +17 chany_top_in[12]:17 0.0003376462 +18 chany_top_in[12]:18 0.0003376462 +19 chany_top_in[12]:19 8.518784e-05 +20 chany_top_in[12]:6 chany_top_in[5]:8 0.0008637732 +21 chany_top_in[12]:6 chany_top_in[5]:11 5.095994e-06 +22 chany_top_in[12]:4 chany_top_in[5]:10 8.211591e-06 +23 chany_top_in[12]:3 chany_top_in[5]:9 8.211591e-06 +24 chany_top_in[12]:12 chany_top_in[5]:6 5.113077e-05 +25 chany_top_in[12]:13 chany_top_in[5]:7 8.233782e-05 +26 chany_top_in[12]:8 chany_top_in[5]:4 1.792706e-05 +27 chany_top_in[12]:9 chany_top_in[5]:5 5.940588e-06 +28 chany_top_in[12]:7 chany_top_in[5]:3 1.792706e-05 +29 chany_top_in[12]:14 chany_top_in[5]:7 0.0008637732 +30 chany_top_in[12]:14 chany_top_in[5]:8 8.233782e-05 +31 chany_top_in[12]:14 chany_top_in[5]:12 5.095994e-06 +32 chany_top_in[12]:10 chany_top_in[5]:6 5.940588e-06 +33 chany_top_in[12]:11 chany_top_in[5]:5 5.113077e-05 +34 chany_top_in[12] top_left_grid_pin_34_[0]:38 5.538967e-06 +35 chany_top_in[12]:6 top_left_grid_pin_34_[0]:33 5.737386e-05 +36 chany_top_in[12]:14 top_left_grid_pin_34_[0]:34 5.737386e-05 +37 chany_top_in[12]:15 top_left_grid_pin_34_[0]:40 1.458253e-05 +38 chany_top_in[12]:17 top_left_grid_pin_34_[0]:40 0.0004552857 +39 chany_top_in[12]:16 top_left_grid_pin_34_[0]:41 1.458253e-05 +40 chany_top_in[12]:19 top_left_grid_pin_34_[0]:39 5.538967e-06 +41 chany_top_in[12]:18 top_left_grid_pin_34_[0]:39 0.0004552857 +42 chany_top_in[12]:6 top_left_grid_pin_38_[0]:22 0.0002118894 +43 chany_top_in[12]:14 top_left_grid_pin_38_[0]:23 0.0002118894 +44 chany_top_in[12]:15 top_left_grid_pin_38_[0]:24 0.0004079897 +45 chany_top_in[12]:16 top_left_grid_pin_38_[0]:25 0.0004079897 +46 chany_top_in[12]:15 top_left_grid_pin_39_[0]:23 0.0003192582 +47 chany_top_in[12]:16 top_left_grid_pin_39_[0]:24 0.0003192582 + +*RES +0 chany_top_in[12] chany_top_in[12]:19 0.001225446 +1 chany_top_in[12]:5 chany_top_in[12]:4 0.0045 +2 chany_top_in[12]:6 chany_top_in[12]:5 0.00341 +3 chany_top_in[12]:4 chany_top_in[12]:3 0.0009040178 +4 chany_top_in[12]:3 mux_right_track_32\/mux_l1_in_0_:A0 0.152 +5 chany_top_in[12]:12 chany_top_in[12]:11 0.003895089 +6 chany_top_in[12]:13 chany_top_in[12]:12 0.00341 +7 chany_top_in[12]:8 chany_top_in[12]:7 0.001310268 +8 chany_top_in[12]:9 chany_top_in[12]:8 0.0045 +9 chany_top_in[12]:7 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +10 chany_top_in[12]:14 chany_top_in[12]:13 0.000215025 +11 chany_top_in[12]:14 chany_top_in[12]:6 0.004034558 +12 chany_top_in[12]:15 chany_top_in[12]:14 0.00341 +13 chany_top_in[12]:17 chany_top_in[12]:16 0.00341 +14 chany_top_in[12]:16 chany_top_in[12]:15 0.004578583 +15 chany_top_in[12]:19 chany_top_in[12]:18 0.00341 +16 chany_top_in[12]:18 chany_top_in[12]:17 0.001220825 +17 chany_top_in[12]:10 chany_top_in[12]:9 0.0005669644 +18 chany_top_in[12]:11 chany_top_in[12]:10 0.0004107143 + +*END + +*D_NET top_left_grid_pin_38_[0] 0.01252762 //LENGTH 91.820 LUMPCC 0.001327597 DR + +*CONN +*P top_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 97.920 +*I mux_top_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 34.600 88.740 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.330 69.700 +*I mux_top_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 59.900 56.100 +*I mux_top_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.640 52.700 +*N top_left_grid_pin_38_[0]:5 *C 68.603 52.700 +*N top_left_grid_pin_38_[0]:6 *C 68.080 52.700 +*N top_left_grid_pin_38_[0]:7 *C 68.080 53.040 +*N top_left_grid_pin_38_[0]:8 *C 58.925 53.040 +*N top_left_grid_pin_38_[0]:9 *C 58.880 53.085 +*N top_left_grid_pin_38_[0]:10 *C 59.938 56.100 +*N top_left_grid_pin_38_[0]:11 *C 60.260 56.100 +*N top_left_grid_pin_38_[0]:12 *C 60.260 55.760 +*N top_left_grid_pin_38_[0]:13 *C 58.925 55.760 +*N top_left_grid_pin_38_[0]:14 *C 58.880 55.715 +*N top_left_grid_pin_38_[0]:15 *C 58.420 55.760 +*N top_left_grid_pin_38_[0]:16 *C 58.420 68.000 +*N top_left_grid_pin_38_[0]:17 *C 57.960 68.000 +*N top_left_grid_pin_38_[0]:18 *C 57.367 69.700 +*N top_left_grid_pin_38_[0]:19 *C 57.915 69.700 +*N top_left_grid_pin_38_[0]:20 *C 57.960 69.655 +*N top_left_grid_pin_38_[0]:21 *C 57.960 70.040 +*N top_left_grid_pin_38_[0]:22 *C 57.953 70.040 +*N top_left_grid_pin_38_[0]:23 *C 46.020 70.040 +*N top_left_grid_pin_38_[0]:24 *C 46.000 70.047 +*N top_left_grid_pin_38_[0]:25 *C 46.000 82.273 +*N top_left_grid_pin_38_[0]:26 *C 45.980 82.280 +*N top_left_grid_pin_38_[0]:27 *C 34.047 82.280 +*N top_left_grid_pin_38_[0]:28 *C 34.040 82.338 +*N top_left_grid_pin_38_[0]:29 *C 34.040 88.740 +*N top_left_grid_pin_38_[0]:30 *C 34.500 88.740 +*N top_left_grid_pin_38_[0]:31 *C 34.500 88.785 +*N top_left_grid_pin_38_[0]:32 *C 34.500 97.863 +*N top_left_grid_pin_38_[0]:33 *C 34.492 97.920 + +*CAP +0 top_left_grid_pin_38_[0] 0.0003519942 +1 mux_top_track_32\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +3 mux_top_track_16\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_4\/mux_l1_in_1_:A1 1e-06 +5 top_left_grid_pin_38_[0]:5 4.688152e-05 +6 top_left_grid_pin_38_[0]:6 7.288891e-05 +7 top_left_grid_pin_38_[0]:7 0.0006330756 +8 top_left_grid_pin_38_[0]:8 0.0006070682 +9 top_left_grid_pin_38_[0]:9 0.0001860456 +10 top_left_grid_pin_38_[0]:10 4.456305e-05 +11 top_left_grid_pin_38_[0]:11 7.049381e-05 +12 top_left_grid_pin_38_[0]:12 0.0001393355 +13 top_left_grid_pin_38_[0]:13 0.0001134047 +14 top_left_grid_pin_38_[0]:14 0.0002229026 +15 top_left_grid_pin_38_[0]:15 0.0007519688 +16 top_left_grid_pin_38_[0]:16 0.0007476353 +17 top_left_grid_pin_38_[0]:17 0.0001395987 +18 top_left_grid_pin_38_[0]:18 7.12882e-05 +19 top_left_grid_pin_38_[0]:19 7.12882e-05 +20 top_left_grid_pin_38_[0]:20 0.0001283585 +21 top_left_grid_pin_38_[0]:21 6.052936e-05 +22 top_left_grid_pin_38_[0]:22 0.0007923289 +23 top_left_grid_pin_38_[0]:23 0.0007923289 +24 top_left_grid_pin_38_[0]:24 0.0006567768 +25 top_left_grid_pin_38_[0]:25 0.0006567768 +26 top_left_grid_pin_38_[0]:26 0.0008619403 +27 top_left_grid_pin_38_[0]:27 0.0008619403 +28 top_left_grid_pin_38_[0]:28 0.0003711421 +29 top_left_grid_pin_38_[0]:29 0.0004023766 +30 top_left_grid_pin_38_[0]:30 3.334531e-05 +31 top_left_grid_pin_38_[0]:31 0.0004934951 +32 top_left_grid_pin_38_[0]:32 0.0004622607 +33 top_left_grid_pin_38_[0]:33 0.0003519942 +34 top_left_grid_pin_38_[0]:22 chany_top_in[12]:6 0.0002118894 +35 top_left_grid_pin_38_[0]:23 chany_top_in[12]:14 0.0002118894 +36 top_left_grid_pin_38_[0]:24 chany_top_in[12]:15 0.0004079897 +37 top_left_grid_pin_38_[0]:25 chany_top_in[12]:16 0.0004079897 +38 top_left_grid_pin_38_[0]:31 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 4.39194e-05 +39 top_left_grid_pin_38_[0]:32 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 4.39194e-05 + +*RES +0 top_left_grid_pin_38_[0] top_left_grid_pin_38_[0]:33 0.0007429917 +1 top_left_grid_pin_38_[0]:21 top_left_grid_pin_38_[0]:20 0.0001850962 +2 top_left_grid_pin_38_[0]:22 top_left_grid_pin_38_[0]:21 0.00341 +3 top_left_grid_pin_38_[0]:23 top_left_grid_pin_38_[0]:22 0.001869425 +4 top_left_grid_pin_38_[0]:24 top_left_grid_pin_38_[0]:23 0.00341 +5 top_left_grid_pin_38_[0]:26 top_left_grid_pin_38_[0]:25 0.00341 +6 top_left_grid_pin_38_[0]:25 top_left_grid_pin_38_[0]:24 0.00191525 +7 top_left_grid_pin_38_[0]:28 top_left_grid_pin_38_[0]:27 0.00341 +8 top_left_grid_pin_38_[0]:27 top_left_grid_pin_38_[0]:26 0.001869425 +9 top_left_grid_pin_38_[0]:8 top_left_grid_pin_38_[0]:7 0.008174107 +10 top_left_grid_pin_38_[0]:9 top_left_grid_pin_38_[0]:8 0.0045 +11 top_left_grid_pin_38_[0]:5 mux_top_track_4\/mux_l1_in_1_:A1 0.152 +12 top_left_grid_pin_38_[0]:13 top_left_grid_pin_38_[0]:12 0.001191964 +13 top_left_grid_pin_38_[0]:14 top_left_grid_pin_38_[0]:13 0.0045 +14 top_left_grid_pin_38_[0]:14 top_left_grid_pin_38_[0]:9 0.002348215 +15 top_left_grid_pin_38_[0]:10 mux_top_track_16\/mux_l1_in_0_:A1 0.152 +16 top_left_grid_pin_38_[0]:30 mux_top_track_32\/mux_l1_in_0_:A1 0.152 +17 top_left_grid_pin_38_[0]:31 top_left_grid_pin_38_[0]:30 0.0045 +18 top_left_grid_pin_38_[0]:31 top_left_grid_pin_38_[0]:29 0.0004107143 +19 top_left_grid_pin_38_[0]:19 top_left_grid_pin_38_[0]:18 0.0004888393 +20 top_left_grid_pin_38_[0]:20 top_left_grid_pin_38_[0]:19 0.0045 +21 top_left_grid_pin_38_[0]:20 top_left_grid_pin_38_[0]:17 0.001477679 +22 top_left_grid_pin_38_[0]:18 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +23 top_left_grid_pin_38_[0]:32 top_left_grid_pin_38_[0]:31 0.008104911 +24 top_left_grid_pin_38_[0]:33 top_left_grid_pin_38_[0]:32 0.00341 +25 top_left_grid_pin_38_[0]:7 top_left_grid_pin_38_[0]:6 0.0003035715 +26 top_left_grid_pin_38_[0]:12 top_left_grid_pin_38_[0]:11 0.0003035715 +27 top_left_grid_pin_38_[0]:11 top_left_grid_pin_38_[0]:10 0.0002879465 +28 top_left_grid_pin_38_[0]:6 top_left_grid_pin_38_[0]:5 0.0004665179 +29 top_left_grid_pin_38_[0]:29 top_left_grid_pin_38_[0]:28 0.005716518 +30 top_left_grid_pin_38_[0]:17 top_left_grid_pin_38_[0]:16 0.0004107143 +31 top_left_grid_pin_38_[0]:16 top_left_grid_pin_38_[0]:15 0.01092857 +32 top_left_grid_pin_38_[0]:15 top_left_grid_pin_38_[0]:14 0.0004107143 + +*END + +*D_NET chanx_right_in[19] 0.002715708 //LENGTH 18.915 LUMPCC 0.0001275706 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 140.450 58.480 +*I mux_top_track_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 125.410 55.420 +*N chanx_right_in[19]:2 *C 125.448 55.420 +*N chanx_right_in[19]:3 *C 136.115 55.420 +*N chanx_right_in[19]:4 *C 136.160 55.465 +*N chanx_right_in[19]:5 *C 136.160 58.422 +*N chanx_right_in[19]:6 *C 136.168 58.480 + +*CAP +0 chanx_right_in[19] 0.0003761535 +1 mux_top_track_10\/mux_l2_in_0_:A0 1e-06 +2 chanx_right_in[19]:2 0.0007110566 +3 chanx_right_in[19]:3 0.0007110566 +4 chanx_right_in[19]:4 0.0002063585 +5 chanx_right_in[19]:5 0.0002063585 +6 chanx_right_in[19]:6 0.0003761535 +7 chanx_right_in[19]:2 ropt_net_167:5 6.251453e-05 +8 chanx_right_in[19]:3 ropt_net_167:6 6.251453e-05 +9 chanx_right_in[19]:4 ropt_net_167:4 1.270759e-06 +10 chanx_right_in[19]:5 ropt_net_167:3 1.270759e-06 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:6 0.0006709249 +1 chanx_right_in[19]:2 mux_top_track_10\/mux_l2_in_0_:A0 0.152 +2 chanx_right_in[19]:3 chanx_right_in[19]:2 0.009524553 +3 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +4 chanx_right_in[19]:5 chanx_right_in[19]:4 0.002640625 +5 chanx_right_in[19]:6 chanx_right_in[19]:5 0.00341 + +*END + +*D_NET right_top_grid_pin_49_[0] 0.01078398 //LENGTH 65.555 LUMPCC 0.00448371 DR + +*CONN +*P right_top_grid_pin_49_[0] I *L 0.29796 *C 136.620 74.870 +*I mux_right_track_4\/mux_l1_in_5_:A1 I *L 0.00198 *C 113.525 69.020 +*I mux_right_track_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 91.080 79.900 +*I mux_right_track_32\/mux_l1_in_2_:A1 I *L 0.00198 *C 93.840 72.420 +*N right_top_grid_pin_49_[0]:4 *C 93.840 72.420 +*N right_top_grid_pin_49_[0]:5 *C 91.043 79.900 +*N right_top_grid_pin_49_[0]:6 *C 90.665 79.900 +*N right_top_grid_pin_49_[0]:7 *C 90.620 79.855 +*N right_top_grid_pin_49_[0]:8 *C 90.620 72.805 +*N right_top_grid_pin_49_[0]:9 *C 90.665 72.760 +*N right_top_grid_pin_49_[0]:10 *C 93.840 72.760 +*N right_top_grid_pin_49_[0]:11 *C 108.055 72.760 +*N right_top_grid_pin_49_[0]:12 *C 108.100 72.715 +*N right_top_grid_pin_49_[0]:13 *C 108.100 70.097 +*N right_top_grid_pin_49_[0]:14 *C 108.108 70.040 +*N right_top_grid_pin_49_[0]:15 *C 113.525 69.020 +*N right_top_grid_pin_49_[0]:16 *C 113.620 69.065 +*N right_top_grid_pin_49_[0]:17 *C 113.620 69.983 +*N right_top_grid_pin_49_[0]:18 *C 113.620 70.040 +*N right_top_grid_pin_49_[0]:19 *C 127.860 70.040 +*N right_top_grid_pin_49_[0]:20 *C 127.880 70.047 +*N right_top_grid_pin_49_[0]:21 *C 127.880 72.752 +*N right_top_grid_pin_49_[0]:22 *C 127.900 72.760 +*N right_top_grid_pin_49_[0]:23 *C 136.613 72.760 +*N right_top_grid_pin_49_[0]:24 *C 136.620 72.818 + +*CAP +0 right_top_grid_pin_49_[0] 0.0001211834 +1 mux_right_track_4\/mux_l1_in_5_:A1 1e-06 +2 mux_right_track_2\/mux_l2_in_2_:A1 1e-06 +3 mux_right_track_32\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_49_[0]:4 5.938877e-05 +5 right_top_grid_pin_49_[0]:5 6.577619e-05 +6 right_top_grid_pin_49_[0]:6 6.577619e-05 +7 right_top_grid_pin_49_[0]:7 0.0004910279 +8 right_top_grid_pin_49_[0]:8 0.0004910279 +9 right_top_grid_pin_49_[0]:9 0.0001972585 +10 right_top_grid_pin_49_[0]:10 0.000966835 +11 right_top_grid_pin_49_[0]:11 0.0007404996 +12 right_top_grid_pin_49_[0]:12 0.000193028 +13 right_top_grid_pin_49_[0]:13 0.000193028 +14 right_top_grid_pin_49_[0]:14 0.0001314001 +15 right_top_grid_pin_49_[0]:15 2.923765e-05 +16 right_top_grid_pin_49_[0]:16 8.649553e-05 +17 right_top_grid_pin_49_[0]:17 8.649553e-05 +18 right_top_grid_pin_49_[0]:18 0.0004842572 +19 right_top_grid_pin_49_[0]:19 0.0003528571 +20 right_top_grid_pin_49_[0]:20 0.0001607443 +21 right_top_grid_pin_49_[0]:21 0.0001607443 +22 right_top_grid_pin_49_[0]:22 0.000549515 +23 right_top_grid_pin_49_[0]:23 0.000549515 +24 right_top_grid_pin_49_[0]:24 0.0001211834 +25 right_top_grid_pin_49_[0]:19 prog_clk[0]:111 0.0002688408 +26 right_top_grid_pin_49_[0]:19 prog_clk[0]:126 0.0001010323 +27 right_top_grid_pin_49_[0]:18 prog_clk[0]:126 0.0005755537 +28 right_top_grid_pin_49_[0]:18 prog_clk[0]:127 0.0001010323 +29 right_top_grid_pin_49_[0]:11 prog_clk[0]:128 2.573178e-05 +30 right_top_grid_pin_49_[0]:14 prog_clk[0]:127 0.0003067129 +31 right_top_grid_pin_49_[0]:10 prog_clk[0]:106 2.573178e-05 +32 right_top_grid_pin_49_[0] right_top_grid_pin_45_[0] 1.115876e-05 +33 right_top_grid_pin_49_[0]:24 right_top_grid_pin_45_[0]:24 1.115876e-05 +34 right_top_grid_pin_49_[0]:11 right_top_grid_pin_45_[0]:18 0.0003290467 +35 right_top_grid_pin_49_[0]:10 right_top_grid_pin_45_[0]:17 0.0003290467 +36 right_top_grid_pin_49_[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.79919e-05 +37 right_top_grid_pin_49_[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.79919e-05 +38 right_top_grid_pin_49_[0]:19 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000816609 +39 right_top_grid_pin_49_[0]:22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.017751e-06 +40 right_top_grid_pin_49_[0]:23 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.017751e-06 +41 right_top_grid_pin_49_[0]:18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000816609 +42 right_top_grid_pin_49_[0]:18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003067129 +43 right_top_grid_pin_49_[0]:14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003067129 + +*RES +0 right_top_grid_pin_49_[0] right_top_grid_pin_49_[0]:24 0.001832589 +1 right_top_grid_pin_49_[0]:19 right_top_grid_pin_49_[0]:18 0.002230933 +2 right_top_grid_pin_49_[0]:20 right_top_grid_pin_49_[0]:19 0.00341 +3 right_top_grid_pin_49_[0]:22 right_top_grid_pin_49_[0]:21 0.00341 +4 right_top_grid_pin_49_[0]:21 right_top_grid_pin_49_[0]:20 0.0004237833 +5 right_top_grid_pin_49_[0]:24 right_top_grid_pin_49_[0]:23 0.00341 +6 right_top_grid_pin_49_[0]:23 right_top_grid_pin_49_[0]:22 0.001364958 +7 right_top_grid_pin_49_[0]:5 mux_right_track_2\/mux_l2_in_2_:A1 0.152 +8 right_top_grid_pin_49_[0]:6 right_top_grid_pin_49_[0]:5 0.0003370536 +9 right_top_grid_pin_49_[0]:7 right_top_grid_pin_49_[0]:6 0.0045 +10 right_top_grid_pin_49_[0]:9 right_top_grid_pin_49_[0]:8 0.0045 +11 right_top_grid_pin_49_[0]:8 right_top_grid_pin_49_[0]:7 0.006294643 +12 right_top_grid_pin_49_[0]:17 right_top_grid_pin_49_[0]:16 0.0008191965 +13 right_top_grid_pin_49_[0]:18 right_top_grid_pin_49_[0]:17 0.00341 +14 right_top_grid_pin_49_[0]:18 right_top_grid_pin_49_[0]:14 0.000863625 +15 right_top_grid_pin_49_[0]:15 mux_right_track_4\/mux_l1_in_5_:A1 0.152 +16 right_top_grid_pin_49_[0]:16 right_top_grid_pin_49_[0]:15 0.0045 +17 right_top_grid_pin_49_[0]:4 mux_right_track_32\/mux_l1_in_2_:A1 0.152 +18 right_top_grid_pin_49_[0]:11 right_top_grid_pin_49_[0]:10 0.01269196 +19 right_top_grid_pin_49_[0]:12 right_top_grid_pin_49_[0]:11 0.0045 +20 right_top_grid_pin_49_[0]:13 right_top_grid_pin_49_[0]:12 0.002337054 +21 right_top_grid_pin_49_[0]:14 right_top_grid_pin_49_[0]:13 0.00341 +22 right_top_grid_pin_49_[0]:10 right_top_grid_pin_49_[0]:9 0.002834822 +23 right_top_grid_pin_49_[0]:10 right_top_grid_pin_49_[0]:4 0.0003035715 + +*END + +*D_NET chany_top_out[1] 0.0007741784 //LENGTH 6.520 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 62.100 96.900 +*P chany_top_out[1] O *L 0.7423 *C 61.180 102.035 +*N chany_top_out[1]:2 *C 61.180 96.945 +*N chany_top_out[1]:3 *C 61.225 96.900 +*N chany_top_out[1]:4 *C 62.062 96.900 + +*CAP +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[1] 0.0002916474 +2 chany_top_out[1]:2 0.0002916474 +3 chany_top_out[1]:3 9.494183e-05 +4 chany_top_out[1]:4 9.494183e-05 + +*RES +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[1]:4 0.152 +1 chany_top_out[1]:3 chany_top_out[1]:2 0.0045 +2 chany_top_out[1]:2 chany_top_out[1] 0.004544643 +3 chany_top_out[1]:4 chany_top_out[1]:3 0.0007477679 + +*END + +*D_NET chany_top_out[6] 0.0006593762 //LENGTH 5.170 LUMPCC 0 DR + +*CONN +*I mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 72.220 99.280 +*P chany_top_out[6] O *L 0.7423 *C 70.380 102.035 +*N chany_top_out[6]:2 *C 70.380 99.665 +*N chany_top_out[6]:3 *C 70.425 99.620 +*N chany_top_out[6]:4 *C 72.220 99.620 +*N chany_top_out[6]:5 *C 72.220 99.280 + +*CAP +0 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[6] 0.0001484538 +2 chany_top_out[6]:2 0.0001484538 +3 chany_top_out[6]:3 0.0001366607 +4 chany_top_out[6]:4 0.0001656148 +5 chany_top_out[6]:5 5.919319e-05 + +*RES +0 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[6]:5 0.152 +1 chany_top_out[6]:3 chany_top_out[6]:2 0.0045 +2 chany_top_out[6]:2 chany_top_out[6] 0.002116072 +3 chany_top_out[6]:5 chany_top_out[6]:4 0.0003035715 +4 chany_top_out[6]:4 chany_top_out[6]:3 0.001602679 + +*END + +*D_NET chany_top_out[16] 0.0006440392 //LENGTH 5.630 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 84.640 99.280 +*P chany_top_out[16] O *L 0.7423 *C 86.940 102.035 +*N chany_top_out[16]:2 *C 86.940 99.665 +*N chany_top_out[16]:3 *C 86.895 99.620 +*N chany_top_out[16]:4 *C 84.640 99.620 +*N chany_top_out[16]:5 *C 84.640 99.280 + +*CAP +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[16] 0.0001299175 +2 chany_top_out[16]:2 0.0001299175 +3 chany_top_out[16]:3 0.0001488033 +4 chany_top_out[16]:4 0.0001770078 +5 chany_top_out[16]:5 5.739323e-05 + +*RES +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[16]:5 0.152 +1 chany_top_out[16]:3 chany_top_out[16]:2 0.0045 +2 chany_top_out[16]:2 chany_top_out[16] 0.002116072 +3 chany_top_out[16]:5 chany_top_out[16]:4 0.0003035715 +4 chany_top_out[16]:4 chany_top_out[16]:3 0.002013393 + +*END + +*D_NET chanx_left_out[4] 0.002848982 //LENGTH 27.890 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l4_in_0_:X O *L 0 *C 14.940 25.160 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 11.560 +*N chanx_left_out[4]:2 *C 14.713 11.560 +*N chanx_left_out[4]:3 *C 14.720 11.617 +*N chanx_left_out[4]:4 *C 14.720 25.115 +*N chanx_left_out[4]:5 *C 14.720 25.160 +*N chanx_left_out[4]:6 *C 14.940 25.160 + +*CAP +0 mux_left_track_9\/mux_l4_in_0_:X 1e-06 +1 chanx_left_out[4] 0.0007408228 +2 chanx_left_out[4]:2 0.0007408228 +3 chanx_left_out[4]:3 0.0006370114 +4 chanx_left_out[4]:4 0.0006370114 +5 chanx_left_out[4]:5 4.804291e-05 +6 chanx_left_out[4]:6 4.427086e-05 + +*RES +0 mux_left_track_9\/mux_l4_in_0_:X chanx_left_out[4]:6 0.152 +1 chanx_left_out[4]:6 chanx_left_out[4]:5 0.0001195652 +2 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +3 chanx_left_out[4]:4 chanx_left_out[4]:3 0.01205134 +4 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.002112258 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[0] 0.01082965 //LENGTH 81.690 LUMPCC 0.0006347855 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 108.865 80.240 +*I mux_right_track_4\/mux_l1_in_3_:S I *L 0.00357 *C 109.120 72.760 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 96.315 69.700 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 82.240 68.680 +*I mux_right_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 106.620 69.070 +*I mux_right_track_4\/mux_l1_in_5_:S I *L 0.00357 *C 112.800 69.360 +*I mux_right_track_4\/mux_l1_in_4_:S I *L 0.00357 *C 107.540 66.935 +*I mux_right_track_4\/mux_l1_in_6_:S I *L 0.00357 *C 112.820 51.000 +*I mux_right_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 101.300 67.320 +*N mux_tree_tapbuf_size14_0_sram[0]:9 *C 101.338 67.320 +*N mux_tree_tapbuf_size14_0_sram[0]:10 *C 112.782 51.000 +*N mux_tree_tapbuf_size14_0_sram[0]:11 *C 105.385 51.000 +*N mux_tree_tapbuf_size14_0_sram[0]:12 *C 105.340 51.045 +*N mux_tree_tapbuf_size14_0_sram[0]:13 *C 105.340 67.275 +*N mux_tree_tapbuf_size14_0_sram[0]:14 *C 105.340 67.320 +*N mux_tree_tapbuf_size14_0_sram[0]:15 *C 107.540 67.320 +*N mux_tree_tapbuf_size14_0_sram[0]:16 *C 107.540 66.980 +*N mux_tree_tapbuf_size14_0_sram[0]:17 *C 108.975 66.980 +*N mux_tree_tapbuf_size14_0_sram[0]:18 *C 109.020 67.025 +*N mux_tree_tapbuf_size14_0_sram[0]:19 *C 112.763 69.360 +*N mux_tree_tapbuf_size14_0_sram[0]:20 *C 109.940 69.360 +*N mux_tree_tapbuf_size14_0_sram[0]:21 *C 109.940 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:22 *C 106.620 69.070 +*N mux_tree_tapbuf_size14_0_sram[0]:23 *C 106.562 69.360 +*N mux_tree_tapbuf_size14_0_sram[0]:24 *C 106.260 69.360 +*N mux_tree_tapbuf_size14_0_sram[0]:25 *C 82.278 68.680 +*N mux_tree_tapbuf_size14_0_sram[0]:26 *C 84.135 68.680 +*N mux_tree_tapbuf_size14_0_sram[0]:27 *C 84.180 68.725 +*N mux_tree_tapbuf_size14_0_sram[0]:28 *C 84.180 69.655 +*N mux_tree_tapbuf_size14_0_sram[0]:29 *C 84.225 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:30 *C 96.315 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:31 *C 106.260 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:32 *C 109.020 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:33 *C 109.020 69.700 +*N mux_tree_tapbuf_size14_0_sram[0]:34 *C 109.020 72.760 +*N mux_tree_tapbuf_size14_0_sram[0]:35 *C 109.020 72.760 +*N mux_tree_tapbuf_size14_0_sram[0]:36 *C 109.020 80.195 +*N mux_tree_tapbuf_size14_0_sram[0]:37 *C 109.020 80.240 +*N mux_tree_tapbuf_size14_0_sram[0]:38 *C 108.865 80.240 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_4\/mux_l1_in_3_:S 1e-06 +2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +4 mux_right_track_4\/mux_l1_in_2_:S 1e-06 +5 mux_right_track_4\/mux_l1_in_5_:S 1e-06 +6 mux_right_track_4\/mux_l1_in_4_:S 1e-06 +7 mux_right_track_4\/mux_l1_in_6_:S 1e-06 +8 mux_right_track_4\/mux_l1_in_1_:S 1e-06 +9 mux_tree_tapbuf_size14_0_sram[0]:9 0.0002862708 +10 mux_tree_tapbuf_size14_0_sram[0]:10 0.0005323382 +11 mux_tree_tapbuf_size14_0_sram[0]:11 0.0005323382 +12 mux_tree_tapbuf_size14_0_sram[0]:12 0.0009142504 +13 mux_tree_tapbuf_size14_0_sram[0]:13 0.0009142504 +14 mux_tree_tapbuf_size14_0_sram[0]:14 0.0004796522 +15 mux_tree_tapbuf_size14_0_sram[0]:15 0.0001875775 +16 mux_tree_tapbuf_size14_0_sram[0]:16 0.0001463735 +17 mux_tree_tapbuf_size14_0_sram[0]:17 0.000115032 +18 mux_tree_tapbuf_size14_0_sram[0]:18 0.0001861397 +19 mux_tree_tapbuf_size14_0_sram[0]:19 0.0002313497 +20 mux_tree_tapbuf_size14_0_sram[0]:20 0.0002537351 +21 mux_tree_tapbuf_size14_0_sram[0]:21 5.85152e-05 +22 mux_tree_tapbuf_size14_0_sram[0]:22 6.60146e-05 +23 mux_tree_tapbuf_size14_0_sram[0]:23 5.543546e-05 +24 mux_tree_tapbuf_size14_0_sram[0]:24 4.841151e-05 +25 mux_tree_tapbuf_size14_0_sram[0]:25 0.0001341872 +26 mux_tree_tapbuf_size14_0_sram[0]:26 0.0001341872 +27 mux_tree_tapbuf_size14_0_sram[0]:27 7.52277e-05 +28 mux_tree_tapbuf_size14_0_sram[0]:28 7.52277e-05 +29 mux_tree_tapbuf_size14_0_sram[0]:29 0.0006960537 +30 mux_tree_tapbuf_size14_0_sram[0]:30 0.001451376 +31 mux_tree_tapbuf_size14_0_sram[0]:31 0.0009056056 +32 mux_tree_tapbuf_size14_0_sram[0]:32 0.0002320361 +33 mux_tree_tapbuf_size14_0_sram[0]:33 0.0003739268 +34 mux_tree_tapbuf_size14_0_sram[0]:34 3.62799e-05 +35 mux_tree_tapbuf_size14_0_sram[0]:35 0.0005773531 +36 mux_tree_tapbuf_size14_0_sram[0]:36 0.0003892382 +37 mux_tree_tapbuf_size14_0_sram[0]:37 5.051344e-05 +38 mux_tree_tapbuf_size14_0_sram[0]:38 4.697237e-05 +39 mux_tree_tapbuf_size14_0_sram[0]:22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.33028e-08 +40 mux_tree_tapbuf_size14_0_sram[0]:32 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.944955e-05 +41 mux_tree_tapbuf_size14_0_sram[0]:32 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.233079e-05 +42 mux_tree_tapbuf_size14_0_sram[0]:31 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.233079e-05 +43 mux_tree_tapbuf_size14_0_sram[0]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.317055e-05 +44 mux_tree_tapbuf_size14_0_sram[0]:23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.33028e-08 +45 mux_tree_tapbuf_size14_0_sram[0]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.721009e-06 +46 mux_tree_tapbuf_size14_0_sram[0]:35 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.621973e-05 +47 mux_tree_tapbuf_size14_0_sram[0]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.972348e-07 +48 mux_tree_tapbuf_size14_0_sram[0]:32 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 2.711487e-05 +49 mux_tree_tapbuf_size14_0_sram[0]:33 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.621973e-05 +50 mux_tree_tapbuf_size14_0_sram[0]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.711487e-05 +51 mux_tree_tapbuf_size14_0_sram[0]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.972348e-07 +52 mux_tree_tapbuf_size14_0_sram[0]:29 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.658734e-05 +53 mux_tree_tapbuf_size14_0_sram[0]:26 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 2.821494e-05 +54 mux_tree_tapbuf_size14_0_sram[0]:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.821494e-05 +55 mux_tree_tapbuf_size14_0_sram[0]:30 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.658734e-05 +56 mux_tree_tapbuf_size14_0_sram[0]:29 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.333398e-05 +57 mux_tree_tapbuf_size14_0_sram[0]:30 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.333398e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size14_0_sram[0]:38 0.152 +1 mux_tree_tapbuf_size14_0_sram[0]:34 mux_right_track_4\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size14_0_sram[0]:35 mux_tree_tapbuf_size14_0_sram[0]:34 0.0045 +3 mux_tree_tapbuf_size14_0_sram[0]:35 mux_tree_tapbuf_size14_0_sram[0]:33 0.002732143 +4 mux_tree_tapbuf_size14_0_sram[0]:19 mux_right_track_4\/mux_l1_in_5_:S 0.152 +5 mux_tree_tapbuf_size14_0_sram[0]:29 mux_tree_tapbuf_size14_0_sram[0]:28 0.0045 +6 mux_tree_tapbuf_size14_0_sram[0]:28 mux_tree_tapbuf_size14_0_sram[0]:27 0.0008303572 +7 mux_tree_tapbuf_size14_0_sram[0]:26 mux_tree_tapbuf_size14_0_sram[0]:25 0.001658482 +8 mux_tree_tapbuf_size14_0_sram[0]:27 mux_tree_tapbuf_size14_0_sram[0]:26 0.0045 +9 mux_tree_tapbuf_size14_0_sram[0]:25 mux_right_track_4\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size14_0_sram[0]:22 mux_right_track_4\/mux_l1_in_2_:S 0.152 +11 mux_tree_tapbuf_size14_0_sram[0]:10 mux_right_track_4\/mux_l1_in_6_:S 0.152 +12 mux_tree_tapbuf_size14_0_sram[0]:11 mux_tree_tapbuf_size14_0_sram[0]:10 0.006604911 +13 mux_tree_tapbuf_size14_0_sram[0]:12 mux_tree_tapbuf_size14_0_sram[0]:11 0.0045 +14 mux_tree_tapbuf_size14_0_sram[0]:14 mux_tree_tapbuf_size14_0_sram[0]:13 0.0045 +15 mux_tree_tapbuf_size14_0_sram[0]:14 mux_tree_tapbuf_size14_0_sram[0]:9 0.003573661 +16 mux_tree_tapbuf_size14_0_sram[0]:13 mux_tree_tapbuf_size14_0_sram[0]:12 0.01449107 +17 mux_tree_tapbuf_size14_0_sram[0]:30 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size14_0_sram[0]:30 mux_tree_tapbuf_size14_0_sram[0]:29 0.01079464 +19 mux_tree_tapbuf_size14_0_sram[0]:17 mux_tree_tapbuf_size14_0_sram[0]:16 0.00128125 +20 mux_tree_tapbuf_size14_0_sram[0]:18 mux_tree_tapbuf_size14_0_sram[0]:17 0.0045 +21 mux_tree_tapbuf_size14_0_sram[0]:37 mux_tree_tapbuf_size14_0_sram[0]:36 0.0045 +22 mux_tree_tapbuf_size14_0_sram[0]:36 mux_tree_tapbuf_size14_0_sram[0]:35 0.006638393 +23 mux_tree_tapbuf_size14_0_sram[0]:38 mux_tree_tapbuf_size14_0_sram[0]:37 8.423914e-05 +24 mux_tree_tapbuf_size14_0_sram[0]:16 mux_right_track_4\/mux_l1_in_4_:S 0.152 +25 mux_tree_tapbuf_size14_0_sram[0]:16 mux_tree_tapbuf_size14_0_sram[0]:15 0.0003035714 +26 mux_tree_tapbuf_size14_0_sram[0]:32 mux_tree_tapbuf_size14_0_sram[0]:31 0.002464286 +27 mux_tree_tapbuf_size14_0_sram[0]:32 mux_tree_tapbuf_size14_0_sram[0]:21 0.0008214285 +28 mux_tree_tapbuf_size14_0_sram[0]:33 mux_tree_tapbuf_size14_0_sram[0]:32 0.0045 +29 mux_tree_tapbuf_size14_0_sram[0]:33 mux_tree_tapbuf_size14_0_sram[0]:18 0.002388393 +30 mux_tree_tapbuf_size14_0_sram[0]:9 mux_right_track_4\/mux_l1_in_1_:S 0.152 +31 mux_tree_tapbuf_size14_0_sram[0]:31 mux_tree_tapbuf_size14_0_sram[0]:30 0.008879464 +32 mux_tree_tapbuf_size14_0_sram[0]:31 mux_tree_tapbuf_size14_0_sram[0]:24 0.0003035715 +33 mux_tree_tapbuf_size14_0_sram[0]:21 mux_tree_tapbuf_size14_0_sram[0]:20 0.0003035715 +34 mux_tree_tapbuf_size14_0_sram[0]:15 mux_tree_tapbuf_size14_0_sram[0]:14 0.001964286 +35 mux_tree_tapbuf_size14_0_sram[0]:24 mux_tree_tapbuf_size14_0_sram[0]:23 0.0002700893 +36 mux_tree_tapbuf_size14_0_sram[0]:23 mux_tree_tapbuf_size14_0_sram[0]:22 0.0001686047 +37 mux_tree_tapbuf_size14_0_sram[0]:20 mux_tree_tapbuf_size14_0_sram[0]:19 0.002520089 + +*END + +*D_NET mux_tree_tapbuf_size3_7_sram[1] 0.001159125 //LENGTH 9.155 LUMPCC 0.0001009126 DR + +*CONN +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 85.865 88.400 +*I mux_top_track_38\/mux_l2_in_0_:S I *L 0.00357 *C 82.900 85.680 +*I mem_top_track_38\/FTB_21__47:A I *L 0.001746 *C 88.320 88.400 +*N mux_tree_tapbuf_size3_7_sram[1]:3 *C 88.282 88.400 +*N mux_tree_tapbuf_size3_7_sram[1]:4 *C 82.938 85.680 +*N mux_tree_tapbuf_size3_7_sram[1]:5 *C 85.975 85.680 +*N mux_tree_tapbuf_size3_7_sram[1]:6 *C 86.020 85.725 +*N mux_tree_tapbuf_size3_7_sram[1]:7 *C 86.020 88.355 +*N mux_tree_tapbuf_size3_7_sram[1]:8 *C 86.065 88.400 +*N mux_tree_tapbuf_size3_7_sram[1]:9 *C 85.865 88.400 + +*CAP +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_38\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_38\/FTB_21__47:A 1e-06 +3 mux_tree_tapbuf_size3_7_sram[1]:3 0.0001295837 +4 mux_tree_tapbuf_size3_7_sram[1]:4 0.0002043181 +5 mux_tree_tapbuf_size3_7_sram[1]:5 0.0002043181 +6 mux_tree_tapbuf_size3_7_sram[1]:6 0.0001615905 +7 mux_tree_tapbuf_size3_7_sram[1]:7 0.0001615905 +8 mux_tree_tapbuf_size3_7_sram[1]:8 0.0001469389 +9 mux_tree_tapbuf_size3_7_sram[1]:9 4.687274e-05 +10 mux_tree_tapbuf_size3_7_sram[1]:5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.045628e-05 +11 mux_tree_tapbuf_size3_7_sram[1]:4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.045628e-05 + +*RES +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_7_sram[1]:9 0.152 +1 mux_tree_tapbuf_size3_7_sram[1]:8 mux_tree_tapbuf_size3_7_sram[1]:7 0.0045 +2 mux_tree_tapbuf_size3_7_sram[1]:8 mux_tree_tapbuf_size3_7_sram[1]:3 0.001979911 +3 mux_tree_tapbuf_size3_7_sram[1]:7 mux_tree_tapbuf_size3_7_sram[1]:6 0.002348214 +4 mux_tree_tapbuf_size3_7_sram[1]:5 mux_tree_tapbuf_size3_7_sram[1]:4 0.002712054 +5 mux_tree_tapbuf_size3_7_sram[1]:6 mux_tree_tapbuf_size3_7_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size3_7_sram[1]:4 mux_top_track_38\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size3_7_sram[1]:9 mux_tree_tapbuf_size3_7_sram[1]:8 0.0001086957 +8 mux_tree_tapbuf_size3_7_sram[1]:3 mem_top_track_38\/FTB_21__47:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.004443872 //LENGTH 30.800 LUMPCC 0.0008046671 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 92.620 74.460 +*I mux_right_track_32\/mux_l1_in_2_:S I *L 0.00357 *C 93.020 72.080 +*I mux_right_track_32\/mux_l1_in_1_:S I *L 0.00357 *C 82.440 72.375 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 73.315 75.140 +*I mux_right_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 73.040 72.375 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 73.040 72.375 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 73.278 75.140 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 72.725 75.140 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 72.680 75.095 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 72.680 72.805 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 72.710 72.730 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 73.040 72.715 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 73.075 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 78.660 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 78.660 72.420 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 82.478 72.370 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 82.498 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 93.035 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 93.358 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 93.380 72.125 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 93.380 74.415 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 93.335 74.460 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 92.657 74.460 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_32\/mux_l1_in_2_:S 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:S 1e-06 +3 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_track_32\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 6.140122e-05 +6 mux_tree_tapbuf_size6_0_sram[0]:6 6.176979e-05 +7 mux_tree_tapbuf_size6_0_sram[0]:7 6.176979e-05 +8 mux_tree_tapbuf_size6_0_sram[0]:8 0.0001778732 +9 mux_tree_tapbuf_size6_0_sram[0]:9 0.0001778732 +10 mux_tree_tapbuf_size6_0_sram[0]:10 4.752542e-05 +11 mux_tree_tapbuf_size6_0_sram[0]:11 8.590274e-05 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.000390017 +13 mux_tree_tapbuf_size6_0_sram[0]:13 0.0004077599 +14 mux_tree_tapbuf_size6_0_sram[0]:14 0.0002122378 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0002162746 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.0005992482 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0006298142 +18 mux_tree_tapbuf_size6_0_sram[0]:18 5.874326e-05 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0001566999 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0001566999 +21 mux_tree_tapbuf_size6_0_sram[0]:21 6.629732e-05 +22 mux_tree_tapbuf_size6_0_sram[0]:22 6.629732e-05 +23 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[1]:8 4.234733e-05 +24 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[1]:10 9.408365e-05 +25 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[1]:7 8.847397e-06 +26 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[1]:8 6.692793e-05 +27 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[1]:10 4.234733e-05 +28 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[1]:9 9.408365e-05 +29 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[1]:12 8.847397e-06 +30 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[1]:10 6.692793e-05 +31 mux_tree_tapbuf_size6_0_sram[0]:12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.830673e-05 +32 mux_tree_tapbuf_size6_0_sram[0]:13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.830673e-05 +33 mux_tree_tapbuf_size6_0_sram[0]:17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001218205 +34 mux_tree_tapbuf_size6_0_sram[0]:16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001218205 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:15 mux_right_track_32\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.003408482 +3 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size6_0_sram[0]:9 mux_tree_tapbuf_size6_0_sram[0]:8 0.002044643 +5 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.0004933036 +6 mux_tree_tapbuf_size6_0_sram[0]:8 mux_tree_tapbuf_size6_0_sram[0]:7 0.0045 +7 mux_tree_tapbuf_size6_0_sram[0]:6 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size6_0_sram[0]:17 mux_right_track_32\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.009408482 +10 mux_tree_tapbuf_size6_0_sram[0]:5 mux_right_track_32\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.0006049108 +12 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.0045 +13 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.002044643 +14 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.0001752718 +15 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:10 0.00020625 +17 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:5 0.0003035715 +18 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 2.1875e-05 +19 mux_tree_tapbuf_size6_0_sram[0]:13 mux_tree_tapbuf_size6_0_sram[0]:12 0.004986607 +20 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 0.0003035715 +21 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.0001686047 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[1] 0.003571154 //LENGTH 26.110 LUMPCC 0.0005730725 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 51.825 34.000 +*I mux_left_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 47.940 28.855 +*I mux_left_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 40.020 34.180 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 39.735 28.220 +*N mux_tree_tapbuf_size7_5_sram[1]:4 *C 39.735 28.220 +*N mux_tree_tapbuf_size7_5_sram[1]:5 *C 40.020 34.180 +*N mux_tree_tapbuf_size7_5_sram[1]:6 *C 40.020 34.000 +*N mux_tree_tapbuf_size7_5_sram[1]:7 *C 40.020 33.955 +*N mux_tree_tapbuf_size7_5_sram[1]:8 *C 40.020 28.265 +*N mux_tree_tapbuf_size7_5_sram[1]:9 *C 40.065 28.220 +*N mux_tree_tapbuf_size7_5_sram[1]:10 *C 47.840 28.220 +*N mux_tree_tapbuf_size7_5_sram[1]:11 *C 47.940 28.855 +*N mux_tree_tapbuf_size7_5_sram[1]:12 *C 47.910 28.630 +*N mux_tree_tapbuf_size7_5_sram[1]:13 *C 47.795 28.490 +*N mux_tree_tapbuf_size7_5_sram[1]:14 *C 51.015 28.560 +*N mux_tree_tapbuf_size7_5_sram[1]:15 *C 51.060 28.605 +*N mux_tree_tapbuf_size7_5_sram[1]:16 *C 51.060 33.955 +*N mux_tree_tapbuf_size7_5_sram[1]:17 *C 51.105 34.000 +*N mux_tree_tapbuf_size7_5_sram[1]:18 *C 51.788 34.000 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_17\/mux_l2_in_1_:S 1e-06 +3 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_5_sram[1]:4 4.853629e-05 +5 mux_tree_tapbuf_size7_5_sram[1]:5 4.294007e-05 +6 mux_tree_tapbuf_size7_5_sram[1]:6 4.744851e-05 +7 mux_tree_tapbuf_size7_5_sram[1]:7 0.0003294634 +8 mux_tree_tapbuf_size7_5_sram[1]:8 0.0003294634 +9 mux_tree_tapbuf_size7_5_sram[1]:9 0.0004719618 +10 mux_tree_tapbuf_size7_5_sram[1]:10 0.0004768886 +11 mux_tree_tapbuf_size7_5_sram[1]:11 6.138426e-05 +12 mux_tree_tapbuf_size7_5_sram[1]:12 4.013697e-05 +13 mux_tree_tapbuf_size7_5_sram[1]:13 0.0002248031 +14 mux_tree_tapbuf_size7_5_sram[1]:14 0.0001900773 +15 mux_tree_tapbuf_size7_5_sram[1]:15 0.0003011373 +16 mux_tree_tapbuf_size7_5_sram[1]:16 0.0003011373 +17 mux_tree_tapbuf_size7_5_sram[1]:17 6.435165e-05 +18 mux_tree_tapbuf_size7_5_sram[1]:18 6.435165e-05 +19 mux_tree_tapbuf_size7_5_sram[1]:14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.062671e-05 +20 mux_tree_tapbuf_size7_5_sram[1]:13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.062671e-05 +21 mux_tree_tapbuf_size7_5_sram[1]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002059095 +22 mux_tree_tapbuf_size7_5_sram[1]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002059095 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_5_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_5_sram[1]:5 mux_left_track_17\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_5_sram[1]:6 mux_tree_tapbuf_size7_5_sram[1]:5 7.758621e-05 +3 mux_tree_tapbuf_size7_5_sram[1]:7 mux_tree_tapbuf_size7_5_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size7_5_sram[1]:9 mux_tree_tapbuf_size7_5_sram[1]:8 0.0045 +5 mux_tree_tapbuf_size7_5_sram[1]:9 mux_tree_tapbuf_size7_5_sram[1]:4 0.0001793478 +6 mux_tree_tapbuf_size7_5_sram[1]:8 mux_tree_tapbuf_size7_5_sram[1]:7 0.005080357 +7 mux_tree_tapbuf_size7_5_sram[1]:11 mux_left_track_17\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_5_sram[1]:4 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size7_5_sram[1]:14 mux_tree_tapbuf_size7_5_sram[1]:13 0.002875 +10 mux_tree_tapbuf_size7_5_sram[1]:15 mux_tree_tapbuf_size7_5_sram[1]:14 0.0045 +11 mux_tree_tapbuf_size7_5_sram[1]:17 mux_tree_tapbuf_size7_5_sram[1]:16 0.0045 +12 mux_tree_tapbuf_size7_5_sram[1]:16 mux_tree_tapbuf_size7_5_sram[1]:15 0.004776786 +13 mux_tree_tapbuf_size7_5_sram[1]:18 mux_tree_tapbuf_size7_5_sram[1]:17 0.000609375 +14 mux_tree_tapbuf_size7_5_sram[1]:10 mux_tree_tapbuf_size7_5_sram[1]:9 0.006941964 +15 mux_tree_tapbuf_size7_5_sram[1]:13 mux_tree_tapbuf_size7_5_sram[1]:12 0.0001026786 +16 mux_tree_tapbuf_size7_5_sram[1]:13 mux_tree_tapbuf_size7_5_sram[1]:10 0.0002410715 +17 mux_tree_tapbuf_size7_5_sram[1]:12 mux_tree_tapbuf_size7_5_sram[1]:11 9.698277e-05 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[2] 0.00249872 //LENGTH 18.070 LUMPCC 0.0005392001 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 22.845 72.080 +*I mux_left_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 19.880 69.070 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 13.515 66.300 +*I mux_left_track_3\/mux_l3_in_1_:S I *L 0.00357 *C 14.160 69.070 +*N mux_tree_tapbuf_size8_2_sram[2]:4 *C 19.900 69.360 +*N mux_tree_tapbuf_size8_2_sram[2]:5 *C 14.160 69.070 +*N mux_tree_tapbuf_size8_2_sram[2]:6 *C 13.553 66.300 +*N mux_tree_tapbuf_size8_2_sram[2]:7 *C 14.215 66.300 +*N mux_tree_tapbuf_size8_2_sram[2]:8 *C 14.260 66.345 +*N mux_tree_tapbuf_size8_2_sram[2]:9 *C 14.260 68.635 +*N mux_tree_tapbuf_size8_2_sram[2]:10 *C 14.305 68.680 +*N mux_tree_tapbuf_size8_2_sram[2]:11 *C 19.880 68.680 +*N mux_tree_tapbuf_size8_2_sram[2]:12 *C 19.880 69.070 +*N mux_tree_tapbuf_size8_2_sram[2]:13 *C 19.955 69.360 +*N mux_tree_tapbuf_size8_2_sram[2]:14 *C 22.035 69.360 +*N mux_tree_tapbuf_size8_2_sram[2]:15 *C 22.080 69.405 +*N mux_tree_tapbuf_size8_2_sram[2]:16 *C 22.080 72.035 +*N mux_tree_tapbuf_size8_2_sram[2]:17 *C 22.125 72.080 +*N mux_tree_tapbuf_size8_2_sram[2]:18 *C 22.808 72.080 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_3\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size8_2_sram[2]:4 3.091997e-05 +5 mux_tree_tapbuf_size8_2_sram[2]:5 6.345042e-05 +6 mux_tree_tapbuf_size8_2_sram[2]:6 7.074512e-05 +7 mux_tree_tapbuf_size8_2_sram[2]:7 7.074512e-05 +8 mux_tree_tapbuf_size8_2_sram[2]:8 9.458443e-05 +9 mux_tree_tapbuf_size8_2_sram[2]:9 9.458443e-05 +10 mux_tree_tapbuf_size8_2_sram[2]:10 0.0003954365 +11 mux_tree_tapbuf_size8_2_sram[2]:11 0.000385677 +12 mux_tree_tapbuf_size8_2_sram[2]:12 9.739732e-05 +13 mux_tree_tapbuf_size8_2_sram[2]:13 0.0001061478 +14 mux_tree_tapbuf_size8_2_sram[2]:14 6.922719e-05 +15 mux_tree_tapbuf_size8_2_sram[2]:15 0.0001651177 +16 mux_tree_tapbuf_size8_2_sram[2]:16 0.0001651177 +17 mux_tree_tapbuf_size8_2_sram[2]:17 7.318477e-05 +18 mux_tree_tapbuf_size8_2_sram[2]:18 7.318477e-05 +19 mux_tree_tapbuf_size8_2_sram[2]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.554533e-05 +20 mux_tree_tapbuf_size8_2_sram[2]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.35847e-07 +21 mux_tree_tapbuf_size8_2_sram[2]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.35847e-07 +22 mux_tree_tapbuf_size8_2_sram[2]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.554533e-05 +23 mux_tree_tapbuf_size8_2_sram[2]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.13684e-05 +24 mux_tree_tapbuf_size8_2_sram[2]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.664361e-06 +25 mux_tree_tapbuf_size8_2_sram[2]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.664361e-06 +26 mux_tree_tapbuf_size8_2_sram[2]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.13684e-05 +27 mux_tree_tapbuf_size8_2_sram[2]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 6.855332e-05 +28 mux_tree_tapbuf_size8_2_sram[2]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 6.855332e-05 +29 mux_tree_tapbuf_size8_2_sram[2]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.762402e-05 +30 mux_tree_tapbuf_size8_2_sram[2]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 1.070877e-05 +31 mux_tree_tapbuf_size8_2_sram[2]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.762402e-05 +32 mux_tree_tapbuf_size8_2_sram[2]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 1.070877e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_2_sram[2]:18 0.152 +1 mux_tree_tapbuf_size8_2_sram[2]:6 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size8_2_sram[2]:7 mux_tree_tapbuf_size8_2_sram[2]:6 0.0005915179 +3 mux_tree_tapbuf_size8_2_sram[2]:8 mux_tree_tapbuf_size8_2_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:9 0.0045 +5 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:5 0.0003482143 +6 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:8 0.002044643 +7 mux_tree_tapbuf_size8_2_sram[2]:14 mux_tree_tapbuf_size8_2_sram[2]:13 0.001857143 +8 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:14 0.0045 +9 mux_tree_tapbuf_size8_2_sram[2]:17 mux_tree_tapbuf_size8_2_sram[2]:16 0.0045 +10 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:15 0.002348214 +11 mux_tree_tapbuf_size8_2_sram[2]:18 mux_tree_tapbuf_size8_2_sram[2]:17 0.000609375 +12 mux_tree_tapbuf_size8_2_sram[2]:5 mux_left_track_3\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size8_2_sram[2]:12 mux_left_track_3\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size8_2_sram[2]:12 mux_tree_tapbuf_size8_2_sram[2]:11 0.0003482143 +15 mux_tree_tapbuf_size8_2_sram[2]:12 mux_tree_tapbuf_size8_2_sram[2]:4 0.0002589286 +16 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:10 0.004977679 +17 mux_tree_tapbuf_size8_2_sram[2]:13 mux_tree_tapbuf_size8_2_sram[2]:12 0.0002589286 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004646994 //LENGTH 3.215 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 55.375 68.680 +*I mux_top_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 53.000 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 53.000 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 52.900 68.680 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 55.338 68.680 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.379188e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002177513 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001911562 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00217634 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00248231 //LENGTH 21.470 LUMPCC 0.0002530804 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_1_:X O *L 0 *C 117.585 63.920 +*I mux_right_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 124.375 49.980 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 124.375 49.980 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 124.200 49.980 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 124.200 50.025 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 124.200 63.875 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 124.155 63.920 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 117.623 63.920 + +*CAP +0 mux_right_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.09014e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.684607e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0007696642 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0007696642 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000290077 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000290077 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 right_top_grid_pin_42_[0]:14 0.0001265402 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 right_top_grid_pin_42_[0]:13 0.0001265402 + +*RES +0 mux_right_track_8\/mux_l2_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.510871e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01236607 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00583259 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006414407 //LENGTH 4.505 LUMPCC 0.0001122289 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_1_:X O *L 0 *C 26.395 36.040 +*I mux_left_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 27.430 33.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 27.393 33.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 26.265 33.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 26.220 33.705 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 26.220 35.995 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 26.220 36.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 26.395 36.040 + +*CAP +0 mux_left_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.442989e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.442989e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001420434 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001420434 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.899241e-05 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.527289e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[8]:20 5.611447e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[8]:21 5.611447e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001006696 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007800451 //LENGTH 5.740 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_3_:X O *L 0 *C 73.425 45.560 +*I mux_top_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 72.395 49.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 72.395 49.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 72.680 49.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 72.680 49.595 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 72.680 45.605 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 72.725 45.560 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 73.388 45.560 + +*CAP +0 mux_top_track_4\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.691614e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.121902e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002546793 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002546793 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.52756e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.52756e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_3_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001548913 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0035625 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005915179 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001432045 //LENGTH 10.135 LUMPCC 0.0004435162 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 85.845 63.580 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 89.800 58.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 89.763 58.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.065 58.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.020 58.185 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.020 63.535 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 86.020 63.580 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 85.845 63.580 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001038635 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001038635 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003270683 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003270683 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.210783e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.255696e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[12]:17 0.0001533614 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[12]:18 0.0001533614 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_4_sram[1]:11 6.695349e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_4_sram[1]:12 6.695349e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_4_sram[1]:13 1.443202e-06 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_4_sram[1]:14 1.443202e-06 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00330134 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004776787 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005365463 //LENGTH 4.700 LUMPCC 0.0001261941 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 48.935 45.220 +*I mux_left_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 44.525 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 44.562 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 48.898 45.220 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002041761 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002041761 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_6_sram[2]:7 1.162721e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_6_sram[2]:9 5.146983e-05 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_6_sram[2]:8 1.162721e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_6_sram[2]:10 5.146983e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003870536 + +*END + +*D_NET mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005044742 //LENGTH 3.510 LUMPCC 0.0001627157 DR + +*CONN +*I mux_top_track_12\/mux_l1_in_1_:X O *L 0 *C 74.695 66.300 +*I mux_top_track_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 71.475 66.300 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 71.513 66.300 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 74.657 66.300 + +*CAP +0 mux_top_track_12\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_12\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001698792 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001698792 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_0_sram[1]:4 4.184419e-05 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_0_sram[1]:5 3.951367e-05 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_0_sram[1]:5 4.184419e-05 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_0_sram[1]:6 3.951367e-05 + +*RES +0 mux_top_track_12\/mux_l1_in_1_:X mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_12\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002808036 + +*END + +*D_NET mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0] 0.01021925 //LENGTH 72.790 LUMPCC 0.003496706 DR + +*CONN +*I mux_top_track_20\/mux_l2_in_0_:X O *L 0 *C 74.345 42.840 +*I mux_top_track_20\/BUFT_RR_62:A I *L 0.001746 *C 86.020 99.280 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 86.020 99.280 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 86.020 98.940 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 87.355 98.940 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 87.400 98.895 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 87.400 96.618 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 87.392 96.560 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 76.380 96.560 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 76.360 96.553 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 76.360 42.848 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 76.340 42.840 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 74.528 42.840 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 74.520 42.840 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 74.520 42.840 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:15 *C 74.345 42.840 + +*CAP +0 mux_top_track_20\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_20\/BUFT_RR_62:A 1e-06 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.305243e-05 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001216186 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.545971e-05 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001473014 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001473014 +7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0007822996 +8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0007822996 +9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.002054695 +10 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.002054695 +11 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001636317 +12 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0001636317 +13 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:13 3.563935e-05 +14 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:14 5.787814e-05 +15 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:15 6.103817e-05 +16 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 top_left_grid_pin_35_[0]:16 0.0005650811 +17 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 top_left_grid_pin_35_[0]:15 0.0005650811 +18 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[3]:14 0.000407619 +19 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 chany_top_in[3]:13 0.000407619 +20 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[6]:14 0.0007756532 +21 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 chany_top_in[6]:13 0.0007756532 + +*RES +0 mux_top_track_20\/mux_l2_in_0_:X mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.152 +1 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_20\/BUFT_RR_62:A 0.152 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001191964 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002033482 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00341 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001725292 +7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.00341 +8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.00341 +9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.008413783 +10 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.00341 +11 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0002839583 +12 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0045 +13 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:15 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:14 9.51087e-05 +14 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003587164 //LENGTH 26.015 LUMPCC 0.0008430472 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 87.685 79.900 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 106.820 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 106.782 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 104.925 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 104.880 74.505 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 104.880 76.103 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 104.873 76.160 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 87.868 76.160 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 87.860 76.218 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 87.860 79.855 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 87.860 79.900 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 87.685 79.900 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001221252 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001221252 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001146047 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001146047 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0008661564 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0008661564 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002141088 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002141088 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.521037e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:11 5.291582e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:126 7.46397e-06 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:132 7.031739e-05 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:139 1.529758e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:127 7.46397e-06 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:133 7.031739e-05 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:140 1.529758e-05 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_45_[0]:14 0.0001702973 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_45_[0]:13 0.0001702973 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_122:21 0.0001083795 +21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_122:26 7.016786e-06 +22 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_122:26 0.0001083795 +23 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_122:27 7.016786e-06 +24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.275109e-05 +25 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.275109e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001426339 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002664116 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.003247768 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.510871e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0] 0.004462838 //LENGTH 41.860 LUMPCC 0.0002208092 DR + +*CONN +*I mux_right_track_4\/mux_l4_in_0_:X O *L 0 *C 109.765 52.360 +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 120.760 22.985 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 120.760 22.985 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 120.760 23.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:4 *C 110.905 23.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 *C 110.860 23.505 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 *C 110.860 30.895 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:7 *C 110.815 30.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:8 *C 109.985 30.940 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 *C 109.940 30.985 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 *C 109.940 52.315 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:11 *C 109.940 52.360 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:12 *C 109.765 52.360 + +*CAP +0 mux_right_track_4\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 5.938824e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0005325752 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0004997968 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0003631348 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0003631348 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:7 7.849228e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:8 7.849228e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 0.001079265 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 0.001079265 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:11 5.494135e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:12 5.154314e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 prog_clk[0]:230 2.0212e-07 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 prog_clk[0]:232 3.983767e-06 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 prog_clk[0]:236 4.482159e-05 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 prog_clk[0]:242 1.644615e-05 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 prog_clk[0]:243 2.784415e-05 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 prog_clk[0]:226 2.0212e-07 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 prog_clk[0]:231 3.983767e-06 +20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 prog_clk[0]:233 4.482159e-05 +21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 prog_clk[0]:236 1.644615e-05 +22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 prog_clk[0]:242 2.784415e-05 +23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 prog_clk[0]:230 1.71068e-05 +24 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 prog_clk[0]:226 1.71068e-05 + +*RES +0 mux_right_track_4\/mux_l4_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:12 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:11 9.51087e-05 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 0.01904464 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.0007410714 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:8 0.0045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0045 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.006598215 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.008799108 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0045 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0004241072 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001755754 //LENGTH 12.665 LUMPCC 0.0005276253 DR + +*CONN +*I mux_right_track_32\/mux_l2_in_0_:X O *L 0 *C 79.865 72.080 +*I mux_right_track_32\/mux_l3_in_0_:A1 I *L 0.00198 *C 86.120 69.020 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 86.120 69.020 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 86.020 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 78.705 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 78.660 69.405 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 78.660 72.035 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 78.705 72.080 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 79.828 72.080 + +*CAP +0 mux_right_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.763654e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003704424 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003419944 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001561243 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001561243 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.190333e-05 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 7.190333e-05 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[8]:10 0.000102776 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chany_top_in[8]:9 0.000102776 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:25 2.821494e-05 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:29 7.658734e-05 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:26 2.821494e-05 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:30 7.658734e-05 +15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.623439e-05 +16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.623439e-05 + +*RES +0 mux_right_track_32\/mux_l2_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_32\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.00653125 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002348214 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.001002232 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET ropt_net_153 0.001399018 //LENGTH 10.570 LUMPCC 0.0007522214 DR + +*CONN +*I FTB_2__1:X O *L 0 *C 7.820 61.880 +*I ropt_mt_inst_776:A I *L 0.001766 *C 3.220 66.640 +*N ropt_net_153:2 *C 3.258 66.640 +*N ropt_net_153:3 *C 5.935 66.640 +*N ropt_net_153:4 *C 5.980 66.595 +*N ropt_net_153:5 *C 5.980 64.600 +*N ropt_net_153:6 *C 6.440 64.600 +*N ropt_net_153:7 *C 6.440 61.925 +*N ropt_net_153:8 *C 6.485 61.880 +*N ropt_net_153:9 *C 7.783 61.880 + +*CAP +0 FTB_2__1:X 1e-06 +1 ropt_mt_inst_776:A 1e-06 +2 ropt_net_153:2 0.0001279755 +3 ropt_net_153:3 0.0001279755 +4 ropt_net_153:4 7.101308e-05 +5 ropt_net_153:5 1e-09 +6 ropt_net_153:6 2.247909e-05 +7 ropt_net_153:7 9.781857e-05 +8 ropt_net_153:8 9.876754e-05 +9 ropt_net_153:9 9.876754e-05 +10 ropt_net_153:4 left_top_grid_pin_45_[0]:13 1.001346e-05 +11 ropt_net_153:8 left_top_grid_pin_45_[0]:10 4.478955e-05 +12 ropt_net_153:7 left_top_grid_pin_45_[0]:11 2.10753e-06 +13 ropt_net_153:9 left_top_grid_pin_45_[0]:9 4.478955e-05 +14 ropt_net_153:5 left_top_grid_pin_45_[0]:10 1.126481e-05 +15 ropt_net_153:5 left_top_grid_pin_45_[0]:11 1.001346e-05 +16 ropt_net_153:6 left_top_grid_pin_45_[0]:9 1.126481e-05 +17 ropt_net_153:6 left_top_grid_pin_45_[0]:13 2.10753e-06 +18 ropt_net_153:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.123457e-05 +19 ropt_net_153:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.517209e-07 +20 ropt_net_153:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.123457e-05 +21 ropt_net_153:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.472069e-05 +22 ropt_net_153:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.517209e-07 +23 ropt_net_153:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.472069e-05 +24 ropt_net_153:2 ropt_net_150:8 5.045429e-05 +25 ropt_net_153:3 ropt_net_150:9 5.045429e-05 +26 ropt_net_153:5 ropt_net_150:8 2.363846e-05 +27 ropt_net_153:6 ropt_net_150:9 2.363846e-05 +28 ropt_net_153:7 chanx_left_out[3]:5 5.265798e-05 +29 ropt_net_153:6 chanx_left_out[3]:6 5.265798e-05 +30 ropt_net_153:4 ropt_net_162:9 7.294387e-06 +31 ropt_net_153:7 ropt_net_162:8 4.289117e-05 +32 ropt_net_153:5 ropt_net_162:8 7.294387e-06 +33 ropt_net_153:5 ropt_net_162:6 1.469204e-05 +34 ropt_net_153:6 ropt_net_162:9 4.289117e-05 +35 ropt_net_153:6 ropt_net_162:7 1.469204e-05 + +*RES +0 FTB_2__1:X ropt_net_153:9 0.152 +1 ropt_net_153:2 ropt_mt_inst_776:A 0.152 +2 ropt_net_153:3 ropt_net_153:2 0.002390625 +3 ropt_net_153:4 ropt_net_153:3 0.0045 +4 ropt_net_153:8 ropt_net_153:7 0.0045 +5 ropt_net_153:7 ropt_net_153:6 0.002388393 +6 ropt_net_153:9 ropt_net_153:8 0.001158482 +7 ropt_net_153:5 ropt_net_153:4 0.00178125 +8 ropt_net_153:6 ropt_net_153:5 0.0004107143 + +*END + +*D_NET chanx_left_out[18] 0.0005957275 //LENGTH 5.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 4.140 11.560 +*P chanx_left_out[18] O *L 0.7423 *C 1.230 10.200 +*N chanx_left_out[18]:2 *C 3.213 10.200 +*N chanx_left_out[18]:3 *C 3.220 10.258 +*N chanx_left_out[18]:4 *C 3.220 11.515 +*N chanx_left_out[18]:5 *C 3.265 11.560 +*N chanx_left_out[18]:6 *C 4.103 11.560 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 chanx_left_out[18] 0.0001394537 +2 chanx_left_out[18]:2 0.0001394537 +3 chanx_left_out[18]:3 8.20791e-05 +4 chanx_left_out[18]:4 8.20791e-05 +5 chanx_left_out[18]:5 7.583096e-05 +6 chanx_left_out[18]:6 7.583096e-05 + +*RES +0 ropt_mt_inst_785:X chanx_left_out[18]:6 0.152 +1 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0007477679 +2 chanx_left_out[18]:5 chanx_left_out[18]:4 0.0045 +3 chanx_left_out[18]:4 chanx_left_out[18]:3 0.001122768 +4 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +5 chanx_left_out[18]:2 chanx_left_out[18] 0.0003105917 + +*END + +*D_NET chanx_right_out[7] 0.0007910043 //LENGTH 7.295 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 138.655 51.000 +*P chanx_right_out[7] O *L 0.7423 *C 140.382 51.680 +*N chanx_right_out[7]:2 *C 140.300 51.680 +*N chanx_right_out[7]:3 *C 140.300 51.738 +*N chanx_right_out[7]:4 *C 140.300 52.655 +*N chanx_right_out[7]:5 *C 140.255 52.700 +*N chanx_right_out[7]:6 *C 138.045 52.700 +*N chanx_right_out[7]:7 *C 138.000 52.655 +*N chanx_right_out[7]:8 *C 138.000 51.045 +*N chanx_right_out[7]:9 *C 138.045 51.000 +*N chanx_right_out[7]:10 *C 138.618 51.000 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 chanx_right_out[7] 2.76614e-05 +2 chanx_right_out[7]:2 2.76614e-05 +3 chanx_right_out[7]:3 5.643327e-05 +4 chanx_right_out[7]:4 5.643327e-05 +5 chanx_right_out[7]:5 0.0001431922 +6 chanx_right_out[7]:6 0.0001431922 +7 chanx_right_out[7]:7 0.0001080467 +8 chanx_right_out[7]:8 0.0001080467 +9 chanx_right_out[7]:9 5.966855e-05 +10 chanx_right_out[7]:10 5.966855e-05 + +*RES +0 ropt_mt_inst_775:X chanx_right_out[7]:10 0.152 +1 chanx_right_out[7]:10 chanx_right_out[7]:9 0.0005111608 +2 chanx_right_out[7]:9 chanx_right_out[7]:8 0.0045 +3 chanx_right_out[7]:8 chanx_right_out[7]:7 0.0014375 +4 chanx_right_out[7]:6 chanx_right_out[7]:5 0.001973214 +5 chanx_right_out[7]:7 chanx_right_out[7]:6 0.0045 +6 chanx_right_out[7]:5 chanx_right_out[7]:4 0.0045 +7 chanx_right_out[7]:4 chanx_right_out[7]:3 0.0008191965 +8 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +9 chanx_right_out[7]:2 chanx_right_out[7] 2.35e-05 + +*END + +*D_NET chanx_left_out[6] 0.001471988 //LENGTH 11.230 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_805:X O *L 0 *C 7.095 30.600 +*P chanx_left_out[6] O *L 0.7423 *C 1.230 25.840 +*N chanx_left_out[6]:2 *C 6.893 25.840 +*N chanx_left_out[6]:3 *C 6.900 25.898 +*N chanx_left_out[6]:4 *C 6.900 30.555 +*N chanx_left_out[6]:5 *C 6.900 30.600 +*N chanx_left_out[6]:6 *C 7.095 30.600 + +*CAP +0 ropt_mt_inst_805:X 1e-06 +1 chanx_left_out[6] 0.0003660563 +2 chanx_left_out[6]:2 0.0003660563 +3 chanx_left_out[6]:3 0.0002977112 +4 chanx_left_out[6]:4 0.0002977112 +5 chanx_left_out[6]:5 7.162034e-05 +6 chanx_left_out[6]:6 7.183314e-05 + +*RES +0 ropt_mt_inst_805:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:6 chanx_left_out[6]:5 0.0001059783 +2 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +3 chanx_left_out[6]:4 chanx_left_out[6]:3 0.004158483 +4 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +5 chanx_left_out[6]:2 chanx_left_out[6] 0.000887125 + +*END + +*D_NET chanx_right_in[2] 0.02631199 //LENGTH 215.380 LUMPCC 0.008214341 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 140.450 12.240 +*I FTB_2__1:A I *L 0.001776 *C 10.120 61.200 +*I mux_top_track_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 44.620 69.020 +*I mux_left_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 46.750 80.920 +*N chanx_right_in[2]:4 *C 48.970 80.920 +*N chanx_right_in[2]:5 *C 46.788 80.920 +*N chanx_right_in[2]:6 *C 49.635 80.920 +*N chanx_right_in[2]:7 *C 49.680 80.920 +*N chanx_right_in[2]:8 *C 49.678 80.920 +*N chanx_right_in[2]:9 *C 49.680 80.913 +*N chanx_right_in[2]:10 *C 44.620 69.020 +*N chanx_right_in[2]:11 *C 44.620 69.020 +*N chanx_right_in[2]:12 *C 44.620 68.680 +*N chanx_right_in[2]:13 *C 44.628 68.680 +*N chanx_right_in[2]:14 *C 49.660 68.680 +*N chanx_right_in[2]:15 *C 49.680 68.680 +*N chanx_right_in[2]:16 *C 50.600 68.680 +*N chanx_right_in[2]:17 *C 9.410 61.200 +*N chanx_right_in[2]:18 *C 10.120 61.200 +*N chanx_right_in[2]:19 *C 10.120 61.200 +*N chanx_right_in[2]:20 *C 10.117 61.200 +*N chanx_right_in[2]:21 *C 10.120 61.208 +*N chanx_right_in[2]:22 *C 10.120 63.233 +*N chanx_right_in[2]:23 *C 10.120 63.240 +*N chanx_right_in[2]:24 *C 50.580 63.240 +*N chanx_right_in[2]:25 *C 50.600 63.240 +*N chanx_right_in[2]:26 *C 50.600 12.248 +*N chanx_right_in[2]:27 *C 50.620 12.240 +*N chanx_right_in[2]:28 *C 100.410 12.240 + +*CAP +0 chanx_right_in[2] 0.0009501183 +1 FTB_2__1:A 1e-06 +2 mux_top_track_0\/mux_l2_in_2_:A1 1e-06 +3 mux_left_track_1\/mux_l1_in_1_:A0 1e-06 +4 chanx_right_in[2]:4 0.0001306518 +5 chanx_right_in[2]:5 0.0002449412 +6 chanx_right_in[2]:6 0.0002449412 +7 chanx_right_in[2]:7 3.52834e-05 +8 chanx_right_in[2]:8 0.0001306518 +9 chanx_right_in[2]:9 0.0006907612 +10 chanx_right_in[2]:10 3.306289e-05 +11 chanx_right_in[2]:11 5.419918e-05 +12 chanx_right_in[2]:12 5.825477e-05 +13 chanx_right_in[2]:13 0.0003994625 +14 chanx_right_in[2]:14 0.0003994625 +15 chanx_right_in[2]:15 0.0007252854 +16 chanx_right_in[2]:16 0.000333028 +17 chanx_right_in[2]:17 7.310882e-05 +18 chanx_right_in[2]:18 3.43013e-05 +19 chanx_right_in[2]:19 4.105637e-05 +20 chanx_right_in[2]:20 7.310882e-05 +21 chanx_right_in[2]:21 0.0001655416 +22 chanx_right_in[2]:22 0.0001655416 +23 chanx_right_in[2]:23 0.001499444 +24 chanx_right_in[2]:24 0.001499444 +25 chanx_right_in[2]:25 0.002880215 +26 chanx_right_in[2]:26 0.002581711 +27 chanx_right_in[2]:27 0.001850476 +28 chanx_right_in[2]:28 0.002800594 +29 chanx_right_in[2] chanx_right_in[4] 4.777634e-05 +30 chanx_right_in[2] chanx_right_in[4]:27 0.0001920524 +31 chanx_right_in[2] chanx_right_in[4]:26 0.0004150383 +32 chanx_right_in[2]:27 chanx_right_in[4]:25 0.0004465627 +33 chanx_right_in[2]:28 chanx_right_in[4]:25 0.0004150383 +34 chanx_right_in[2]:28 chanx_right_in[4]:28 4.777634e-05 +35 chanx_right_in[2]:28 chanx_right_in[4]:26 0.0006386151 +36 chanx_right_in[2] chanx_right_in[5] 0.0001427706 +37 chanx_right_in[2] chanx_right_in[5]:30 0.0003960979 +38 chanx_right_in[2]:25 chanx_right_in[5]:15 8.938641e-05 +39 chanx_right_in[2]:27 chanx_right_in[5]:29 0.0002643997 +40 chanx_right_in[2]:26 chanx_right_in[5]:14 8.938641e-05 +41 chanx_right_in[2]:28 chanx_right_in[5]:29 0.0003960979 +42 chanx_right_in[2]:28 chanx_right_in[5]:30 0.0004071703 +43 chanx_right_in[2]:24 chanx_left_in[4]:26 0.0008852142 +44 chanx_right_in[2]:23 chanx_left_in[4]:27 0.0008852142 +45 chanx_right_in[2]:20 chanx_left_in[4]:27 7.024099e-05 +46 chanx_right_in[2]:17 chanx_left_in[4]:26 7.024099e-05 +47 chanx_right_in[2]:24 chany_top_in[4]:11 0.000468831 +48 chanx_right_in[2]:25 chany_top_in[4]:12 5.942773e-05 +49 chanx_right_in[2]:23 chany_top_in[4]:10 0.000468831 +50 chanx_right_in[2]:9 chany_top_in[4]:13 0.0001283582 +51 chanx_right_in[2]:15 chany_top_in[4]:10 3.969372e-05 +52 chanx_right_in[2]:15 chany_top_in[4]:12 0.0001283582 +53 chanx_right_in[2]:16 chany_top_in[4]:11 3.969372e-05 +54 chanx_right_in[2]:16 chany_top_in[4]:13 5.942773e-05 +55 chanx_right_in[2]:24 left_top_grid_pin_42_[0]:18 0.0004613201 +56 chanx_right_in[2]:23 left_top_grid_pin_42_[0]:19 0.0004613201 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:28 0.006272933 +1 chanx_right_in[2]:24 chanx_right_in[2]:23 0.006338733 +2 chanx_right_in[2]:25 chanx_right_in[2]:24 0.00341 +3 chanx_right_in[2]:25 chanx_right_in[2]:16 0.0008522666 +4 chanx_right_in[2]:23 chanx_right_in[2]:22 0.00341 +5 chanx_right_in[2]:22 chanx_right_in[2]:21 0.00031725 +6 chanx_right_in[2]:20 chanx_right_in[2]:19 0.00341 +7 chanx_right_in[2]:20 chanx_right_in[2]:17 0.0001039141 +8 chanx_right_in[2]:21 chanx_right_in[2]:20 0.00341 +9 chanx_right_in[2]:19 chanx_right_in[2]:18 0.0045 +10 chanx_right_in[2]:18 FTB_2__1:A 0.152 +11 chanx_right_in[2]:27 chanx_right_in[2]:26 0.00341 +12 chanx_right_in[2]:26 chanx_right_in[2]:25 0.007988825 +13 chanx_right_in[2]:8 chanx_right_in[2]:7 0.00341 +14 chanx_right_in[2]:8 chanx_right_in[2]:4 0.0001039141 +15 chanx_right_in[2]:9 chanx_right_in[2]:8 0.00341 +16 chanx_right_in[2]:7 chanx_right_in[2]:6 0.0045 +17 chanx_right_in[2]:6 chanx_right_in[2]:5 0.002542411 +18 chanx_right_in[2]:5 mux_left_track_1\/mux_l1_in_1_:A0 0.152 +19 chanx_right_in[2]:14 chanx_right_in[2]:13 0.000788425 +20 chanx_right_in[2]:15 chanx_right_in[2]:14 0.00341 +21 chanx_right_in[2]:15 chanx_right_in[2]:9 0.001916425 +22 chanx_right_in[2]:12 chanx_right_in[2]:11 0.0001634615 +23 chanx_right_in[2]:13 chanx_right_in[2]:12 0.00341 +24 chanx_right_in[2]:10 mux_top_track_0\/mux_l2_in_2_:A1 0.152 +25 chanx_right_in[2]:11 chanx_right_in[2]:10 0.0045 +26 chanx_right_in[2]:16 chanx_right_in[2]:15 0.0001441333 +27 chanx_right_in[2]:28 chanx_right_in[2]:27 0.007800432 + +*END + +*D_NET chanx_left_in[5] 0.0253672 //LENGTH 168.095 LUMPCC 0.01040939 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 50.320 +*I mux_top_track_4\/mux_l1_in_3_:A1 I *L 0.00198 *C 71.760 45.220 +*I ropt_mt_inst_762:A I *L 0.001767 *C 134.780 28.560 +*I mux_right_track_4\/mux_l1_in_6_:A1 I *L 0.00198 *C 112.240 50.660 +*N chanx_left_in[5]:4 *C 112.278 50.660 +*N chanx_left_in[5]:5 *C 114.495 50.660 +*N chanx_left_in[5]:6 *C 114.540 50.615 +*N chanx_left_in[5]:7 *C 134.743 28.560 +*N chanx_left_in[5]:8 *C 132.985 28.560 +*N chanx_left_in[5]:9 *C 132.940 28.605 +*N chanx_left_in[5]:10 *C 132.940 33.955 +*N chanx_left_in[5]:11 *C 132.895 34.000 +*N chanx_left_in[5]:12 *C 129.340 34.680 +*N chanx_left_in[5]:13 *C 129.270 34.635 +*N chanx_left_in[5]:14 *C 129.260 34.045 +*N chanx_left_in[5]:15 *C 129.260 34.030 +*N chanx_left_in[5]:16 *C 128.340 34.000 +*N chanx_left_in[5]:17 *C 128.340 34.340 +*N chanx_left_in[5]:18 *C 115.045 34.340 +*N chanx_left_in[5]:19 *C 115.000 34.385 +*N chanx_left_in[5]:20 *C 115.000 44.200 +*N chanx_left_in[5]:21 *C 114.540 44.200 +*N chanx_left_in[5]:22 *C 114.540 45.560 +*N chanx_left_in[5]:23 *C 114.532 45.560 +*N chanx_left_in[5]:24 *C 71.760 45.220 +*N chanx_left_in[5]:25 *C 71.760 45.220 +*N chanx_left_in[5]:26 *C 71.760 45.560 +*N chanx_left_in[5]:27 *C 71.760 45.560 +*N chanx_left_in[5]:28 *C 53.515 45.560 +*N chanx_left_in[5]:29 *C 3.688 45.560 +*N chanx_left_in[5]:30 *C 3.680 45.617 +*N chanx_left_in[5]:31 *C 3.680 50.263 +*N chanx_left_in[5]:32 *C 3.673 50.320 + +*CAP +0 chanx_left_in[5] 0.0001770091 +1 mux_top_track_4\/mux_l1_in_3_:A1 1e-06 +2 ropt_mt_inst_762:A 1e-06 +3 mux_right_track_4\/mux_l1_in_6_:A1 1e-06 +4 chanx_left_in[5]:4 0.0001776647 +5 chanx_left_in[5]:5 0.0001776647 +6 chanx_left_in[5]:6 0.0002834621 +7 chanx_left_in[5]:7 0.0001638581 +8 chanx_left_in[5]:8 0.0001638581 +9 chanx_left_in[5]:9 0.0003585206 +10 chanx_left_in[5]:10 0.0003585206 +11 chanx_left_in[5]:11 0.0002128628 +12 chanx_left_in[5]:12 7.856518e-05 +13 chanx_left_in[5]:13 5.144274e-05 +14 chanx_left_in[5]:14 5.144274e-05 +15 chanx_left_in[5]:15 0.0003216268 +16 chanx_left_in[5]:16 8.039072e-05 +17 chanx_left_in[5]:17 0.0006646995 +18 chanx_left_in[5]:18 0.0006456113 +19 chanx_left_in[5]:19 0.0005112328 +20 chanx_left_in[5]:20 0.0005429154 +21 chanx_left_in[5]:21 0.0001105435 +22 chanx_left_in[5]:22 0.0003997657 +23 chanx_left_in[5]:23 0.001884212 +24 chanx_left_in[5]:24 3.143617e-05 +25 chanx_left_in[5]:25 5.742933e-05 +26 chanx_left_in[5]:26 6.196264e-05 +27 chanx_left_in[5]:27 0.002637807 +28 chanx_left_in[5]:28 0.002431078 +29 chanx_left_in[5]:29 0.001677483 +30 chanx_left_in[5]:30 0.0002323692 +31 chanx_left_in[5]:31 0.0002323692 +32 chanx_left_in[5]:32 0.0001770091 +33 chanx_left_in[5]:23 chanx_right_in[13] 0.001209259 +34 chanx_left_in[5]:27 chanx_right_in[13]:37 0.001209259 +35 chanx_left_in[5]:27 chanx_right_in[14]:15 0.0002432275 +36 chanx_left_in[5]:29 chanx_right_in[14]:14 0.0007147481 +37 chanx_left_in[5]:28 chanx_right_in[14]:14 0.0002432275 +38 chanx_left_in[5]:28 chanx_right_in[14]:15 0.0007147481 +39 chanx_left_in[5] chanx_left_in[6] 9.756939e-06 +40 chanx_left_in[5]:23 chanx_left_in[6]:9 3.272557e-05 +41 chanx_left_in[5]:23 chanx_left_in[6]:19 2.480864e-05 +42 chanx_left_in[5]:27 chanx_left_in[6]:10 3.272557e-05 +43 chanx_left_in[5]:27 chanx_left_in[6]:19 7.351846e-06 +44 chanx_left_in[5]:27 chanx_left_in[6]:20 2.480864e-05 +45 chanx_left_in[5]:29 chanx_left_in[6] 0.0002107767 +46 chanx_left_in[5]:32 chanx_left_in[6]:20 9.756939e-06 +47 chanx_left_in[5]:28 chanx_left_in[6]:20 0.0002181286 +48 chanx_left_in[5]:29 chanx_left_in[13] 0.0008800797 +49 chanx_left_in[5]:28 chanx_left_in[13]:30 0.0008800797 +50 chanx_left_in[5]:19 prog_clk[0]:242 1.094026e-07 +51 chanx_left_in[5]:19 prog_clk[0]:236 8.858672e-07 +52 chanx_left_in[5]:19 prog_clk[0]:233 3.762576e-06 +53 chanx_left_in[5]:22 prog_clk[0]:243 5.036153e-08 +54 chanx_left_in[5]:23 prog_clk[0]:253 2.591932e-05 +55 chanx_left_in[5]:23 prog_clk[0]:223 5.31289e-05 +56 chanx_left_in[5]:23 prog_clk[0]:244 5.751552e-05 +57 chanx_left_in[5]:23 prog_clk[0]:248 6.712016e-05 +58 chanx_left_in[5]:27 prog_clk[0]:253 6.712016e-05 +59 chanx_left_in[5]:27 prog_clk[0]:254 2.591932e-05 +60 chanx_left_in[5]:27 prog_clk[0]:244 5.31289e-05 +61 chanx_left_in[5]:27 prog_clk[0]:248 5.751552e-05 +62 chanx_left_in[5]:29 prog_clk[0]:490 3.71638e-05 +63 chanx_left_in[5]:29 prog_clk[0]:489 6.788137e-05 +64 chanx_left_in[5]:29 prog_clk[0]:477 1.131305e-05 +65 chanx_left_in[5]:29 prog_clk[0]:472 6.495223e-05 +66 chanx_left_in[5]:29 prog_clk[0]:476 6.758538e-05 +67 chanx_left_in[5]:21 prog_clk[0]:242 5.036153e-08 +68 chanx_left_in[5]:20 prog_clk[0]:242 8.858672e-07 +69 chanx_left_in[5]:20 prog_clk[0]:243 1.094026e-07 +70 chanx_left_in[5]:20 prog_clk[0]:236 3.762576e-06 +71 chanx_left_in[5]:28 prog_clk[0]:468 6.495223e-05 +72 chanx_left_in[5]:28 prog_clk[0]:490 6.788137e-05 +73 chanx_left_in[5]:28 prog_clk[0]:480 3.71638e-05 +74 chanx_left_in[5]:28 prog_clk[0]:472 6.758538e-05 +75 chanx_left_in[5]:28 prog_clk[0]:476 1.131305e-05 +76 chanx_left_in[5]:23 top_left_grid_pin_34_[0]:14 0.0003886042 +77 chanx_left_in[5]:23 top_left_grid_pin_34_[0]:10 2.543746e-05 +78 chanx_left_in[5]:23 top_left_grid_pin_34_[0]:20 8.170622e-05 +79 chanx_left_in[5]:27 top_left_grid_pin_34_[0]:21 8.170622e-05 +80 chanx_left_in[5]:27 top_left_grid_pin_34_[0]:11 2.543746e-05 +81 chanx_left_in[5]:27 top_left_grid_pin_34_[0]:19 0.0003886042 +82 chanx_left_in[5]:27 top_left_grid_pin_34_[0]:20 8.607983e-05 +83 chanx_left_in[5]:28 top_left_grid_pin_34_[0]:21 8.607983e-05 +84 chanx_left_in[5]:23 top_left_grid_pin_39_[0]:11 6.850676e-05 +85 chanx_left_in[5]:27 top_left_grid_pin_39_[0]:11 0.000114175 +86 chanx_left_in[5]:27 top_left_grid_pin_39_[0]:15 0.0003157498 +87 chanx_left_in[5]:29 top_left_grid_pin_39_[0]:16 1.78737e-05 +88 chanx_left_in[5]:28 top_left_grid_pin_39_[0]:16 0.0002472431 +89 chanx_left_in[5]:28 top_left_grid_pin_39_[0]:15 0.0001320487 +90 chanx_left_in[5]:18 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.000176644 +91 chanx_left_in[5]:17 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.000176644 +92 chanx_left_in[5]:18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.349986e-05 +93 chanx_left_in[5]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.349986e-05 +94 chanx_left_in[5]:30 ropt_net_161:4 5.886623e-05 +95 chanx_left_in[5]:31 ropt_net_161:3 5.886623e-05 +96 chanx_left_in[5]:30 ropt_net_141:5 7.372444e-06 +97 chanx_left_in[5]:29 ropt_net_141:6 5.856343e-05 +98 chanx_left_in[5]:31 ropt_net_141:4 7.372444e-06 +99 chanx_left_in[5]:28 ropt_net_141:7 5.856343e-05 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:32 0.0003826583 +1 chanx_left_in[5]:18 chanx_left_in[5]:17 0.01187054 +2 chanx_left_in[5]:19 chanx_left_in[5]:18 0.0045 +3 chanx_left_in[5]:22 chanx_left_in[5]:21 0.001214286 +4 chanx_left_in[5]:22 chanx_left_in[5]:6 0.004513393 +5 chanx_left_in[5]:23 chanx_left_in[5]:22 0.00341 +6 chanx_left_in[5]:5 chanx_left_in[5]:4 0.001979911 +7 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0045 +8 chanx_left_in[5]:4 mux_right_track_4\/mux_l1_in_6_:A1 0.152 +9 chanx_left_in[5]:15 chanx_left_in[5]:14 0.0045 +10 chanx_left_in[5]:15 chanx_left_in[5]:11 0.003245536 +11 chanx_left_in[5]:14 chanx_left_in[5]:13 0.0005267857 +12 chanx_left_in[5]:13 chanx_left_in[5]:12 0.0045 +13 chanx_left_in[5]:7 ropt_mt_inst_762:A 0.152 +14 chanx_left_in[5]:8 chanx_left_in[5]:7 0.001569196 +15 chanx_left_in[5]:9 chanx_left_in[5]:8 0.0045 +16 chanx_left_in[5]:11 chanx_left_in[5]:10 0.0045 +17 chanx_left_in[5]:10 chanx_left_in[5]:9 0.004776786 +18 chanx_left_in[5]:26 chanx_left_in[5]:25 0.0001634615 +19 chanx_left_in[5]:27 chanx_left_in[5]:26 0.00341 +20 chanx_left_in[5]:27 chanx_left_in[5]:23 0.006701024 +21 chanx_left_in[5]:24 mux_top_track_4\/mux_l1_in_3_:A1 0.152 +22 chanx_left_in[5]:25 chanx_left_in[5]:24 0.0045 +23 chanx_left_in[5]:30 chanx_left_in[5]:29 0.00341 +24 chanx_left_in[5]:29 chanx_left_in[5]:28 0.007806308 +25 chanx_left_in[5]:31 chanx_left_in[5]:30 0.004147321 +26 chanx_left_in[5]:32 chanx_left_in[5]:31 0.00341 +27 chanx_left_in[5]:17 chanx_left_in[5]:16 0.0003035715 +28 chanx_left_in[5]:16 chanx_left_in[5]:15 0.0008214285 +29 chanx_left_in[5]:21 chanx_left_in[5]:20 0.0004107143 +30 chanx_left_in[5]:20 chanx_left_in[5]:19 0.008763393 +31 chanx_left_in[5]:28 chanx_left_in[5]:27 0.002858383 + +*END + +*D_NET chanx_left_in[13] 0.03193465 //LENGTH 198.100 LUMPCC 0.01262847 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 44.880 +*I BUFT_P_109:A I *L 0.001776 *C 126.960 28.560 +*I mux_right_track_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 96.505 74.460 +*I mux_top_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 55.200 56.100 +*N chanx_left_in[13]:4 *C 55.200 56.115 +*N chanx_left_in[13]:5 *C 96.543 74.460 +*N chanx_left_in[13]:6 *C 97.475 74.460 +*N chanx_left_in[13]:7 *C 97.520 74.415 +*N chanx_left_in[13]:8 *C 97.520 64.657 +*N chanx_left_in[13]:9 *C 97.513 64.600 +*N chanx_left_in[13]:10 *C 126.922 28.560 +*N chanx_left_in[13]:11 *C 119.645 28.560 +*N chanx_left_in[13]:12 *C 119.600 28.605 +*N chanx_left_in[13]:13 *C 119.600 38.703 +*N chanx_left_in[13]:14 *C 119.593 38.760 +*N chanx_left_in[13]:15 *C 96.620 38.760 +*N chanx_left_in[13]:16 *C 96.600 38.768 +*N chanx_left_in[13]:17 *C 96.600 64.593 +*N chanx_left_in[13]:18 *C 96.600 64.600 +*N chanx_left_in[13]:19 *C 55.208 64.600 +*N chanx_left_in[13]:20 *C 55.200 64.543 +*N chanx_left_in[13]:21 *C 55.200 56.485 +*N chanx_left_in[13]:22 *C 55.200 56.433 +*N chanx_left_in[13]:23 *C 53.405 56.440 +*N chanx_left_in[13]:24 *C 53.360 56.395 +*N chanx_left_in[13]:25 *C 53.360 52.418 +*N chanx_left_in[13]:26 *C 53.352 52.360 +*N chanx_left_in[13]:27 *C 19.340 52.360 +*N chanx_left_in[13]:28 *C 19.320 52.352 +*N chanx_left_in[13]:29 *C 19.320 44.888 +*N chanx_left_in[13]:30 *C 19.300 44.880 + +*CAP +0 chanx_left_in[13] 0.0008041213 +1 BUFT_P_109:A 1e-06 +2 mux_right_track_2\/mux_l2_in_3_:A1 1e-06 +3 mux_top_track_16\/mux_l1_in_1_:A1 1e-06 +4 chanx_left_in[13]:4 3.859745e-05 +5 chanx_left_in[13]:5 9.360909e-05 +6 chanx_left_in[13]:6 9.360909e-05 +7 chanx_left_in[13]:7 0.000558787 +8 chanx_left_in[13]:8 0.000558787 +9 chanx_left_in[13]:9 6.517058e-05 +10 chanx_left_in[13]:10 0.0002667666 +11 chanx_left_in[13]:11 0.0002667666 +12 chanx_left_in[13]:12 0.0005398131 +13 chanx_left_in[13]:13 0.0005398131 +14 chanx_left_in[13]:14 0.00124491 +15 chanx_left_in[13]:15 0.00124491 +16 chanx_left_in[13]:16 0.001564574 +17 chanx_left_in[13]:17 0.001564574 +18 chanx_left_in[13]:18 0.001901432 +19 chanx_left_in[13]:19 0.001836261 +20 chanx_left_in[13]:20 0.000513482 +21 chanx_left_in[13]:21 0.000513482 +22 chanx_left_in[13]:22 0.0001858553 +23 chanx_left_in[13]:23 0.0001472579 +24 chanx_left_in[13]:24 0.0002538448 +25 chanx_left_in[13]:25 0.0002538448 +26 chanx_left_in[13]:26 0.001228939 +27 chanx_left_in[13]:27 0.001228939 +28 chanx_left_in[13]:28 0.0004954531 +29 chanx_left_in[13]:29 0.0004954531 +30 chanx_left_in[13]:30 0.0008041213 +31 chanx_left_in[13] chanx_left_in[5]:29 0.0008800797 +32 chanx_left_in[13]:30 chanx_left_in[5]:28 0.0008800797 +33 chanx_left_in[13]:8 chanx_left_in[9]:17 2.663325e-05 +34 chanx_left_in[13]:9 chanx_left_in[9]:19 6.007697e-05 +35 chanx_left_in[13]:7 chanx_left_in[9]:18 2.663325e-05 +36 chanx_left_in[13]:19 chanx_left_in[9]:20 0.0002120624 +37 chanx_left_in[13]:18 chanx_left_in[9]:19 0.0002120624 +38 chanx_left_in[13]:18 chanx_left_in[9]:20 6.007697e-05 +39 chanx_left_in[13]:19 chanx_left_in[12]:14 2.625979e-06 +40 chanx_left_in[13]:24 chanx_left_in[12]:19 1.916573e-05 +41 chanx_left_in[13]:25 chanx_left_in[12]:20 1.916573e-05 +42 chanx_left_in[13]:26 chanx_left_in[12]:21 0.0007275452 +43 chanx_left_in[13]:27 chanx_left_in[12]:22 0.0007275452 +44 chanx_left_in[13]:18 chanx_left_in[12]:13 2.625979e-06 +45 chanx_left_in[13]:15 chanx_left_in[16]:26 0.0004572932 +46 chanx_left_in[13]:14 chanx_left_in[16]:25 0.0004572932 +47 chanx_left_in[13]:8 prog_clk[0]:128 1.332004e-05 +48 chanx_left_in[13]:8 prog_clk[0]:105 1.364537e-06 +49 chanx_left_in[13]:7 prog_clk[0]:134 1.332004e-05 +50 chanx_left_in[13]:7 prog_clk[0]:106 1.364537e-06 +51 chanx_left_in[13]:19 prog_clk[0]:279 1.625096e-06 +52 chanx_left_in[13]:19 prog_clk[0]:307 0.0003851567 +53 chanx_left_in[13]:19 prog_clk[0]:278 3.294113e-06 +54 chanx_left_in[13]:19 prog_clk[0]:283 0.0001370889 +55 chanx_left_in[13]:26 prog_clk[0]:510 0.0004263675 +56 chanx_left_in[13]:27 prog_clk[0]:511 0.0004263675 +57 chanx_left_in[13]:18 prog_clk[0]:282 0.0001370889 +58 chanx_left_in[13]:18 prog_clk[0]:278 1.625096e-06 +59 chanx_left_in[13]:18 prog_clk[0]:306 0.0003851567 +60 chanx_left_in[13]:18 prog_clk[0]:217 3.294113e-06 +61 chanx_left_in[13]:15 prog_clk[0]:235 8.454123e-06 +62 chanx_left_in[13]:14 prog_clk[0]:236 8.454123e-06 +63 chanx_left_in[13]:19 chany_top_in[4]:11 0.001555268 +64 chanx_left_in[13]:18 chany_top_in[4]:6 0.001555268 +65 chanx_left_in[13]:19 chanx_right_in[1]:6 0.0004511775 +66 chanx_left_in[13]:18 chanx_right_in[1]:7 0.0004511775 +67 chanx_left_in[13]:26 chanx_left_in[3]:10 0.0006708858 +68 chanx_left_in[13]:27 chanx_left_in[3] 0.0006708858 +69 chanx_left_in[13]:11 ccff_head[0]:2 0.0002747511 +70 chanx_left_in[13]:10 ccff_head[0]:3 0.0002747511 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:30 0.002830967 +1 chanx_left_in[13]:8 chanx_left_in[13]:7 0.008712053 +2 chanx_left_in[13]:9 chanx_left_in[13]:8 0.00341 +3 chanx_left_in[13]:6 chanx_left_in[13]:5 0.0008325893 +4 chanx_left_in[13]:7 chanx_left_in[13]:6 0.0045 +5 chanx_left_in[13]:5 mux_right_track_2\/mux_l2_in_3_:A1 0.152 +6 chanx_left_in[13]:20 chanx_left_in[13]:19 0.00341 +7 chanx_left_in[13]:19 chanx_left_in[13]:18 0.006484824 +8 chanx_left_in[13]:22 chanx_left_in[13]:21 0.0045 +9 chanx_left_in[13]:22 chanx_left_in[13]:4 0.0001725544 +10 chanx_left_in[13]:21 chanx_left_in[13]:20 0.007194196 +11 chanx_left_in[13]:4 mux_top_track_16\/mux_l1_in_1_:A1 0.152 +12 chanx_left_in[13]:23 chanx_left_in[13]:22 0.001602679 +13 chanx_left_in[13]:24 chanx_left_in[13]:23 0.0045 +14 chanx_left_in[13]:25 chanx_left_in[13]:24 0.003551339 +15 chanx_left_in[13]:26 chanx_left_in[13]:25 0.00341 +16 chanx_left_in[13]:27 chanx_left_in[13]:26 0.005328625 +17 chanx_left_in[13]:28 chanx_left_in[13]:27 0.00341 +18 chanx_left_in[13]:30 chanx_left_in[13]:29 0.00341 +19 chanx_left_in[13]:29 chanx_left_in[13]:28 0.001169517 +20 chanx_left_in[13]:18 chanx_left_in[13]:17 0.00341 +21 chanx_left_in[13]:18 chanx_left_in[13]:9 0.0001429583 +22 chanx_left_in[13]:17 chanx_left_in[13]:16 0.004045916 +23 chanx_left_in[13]:15 chanx_left_in[13]:14 0.003599025 +24 chanx_left_in[13]:16 chanx_left_in[13]:15 0.00341 +25 chanx_left_in[13]:13 chanx_left_in[13]:12 0.009015625 +26 chanx_left_in[13]:14 chanx_left_in[13]:13 0.00341 +27 chanx_left_in[13]:11 chanx_left_in[13]:10 0.006497768 +28 chanx_left_in[13]:12 chanx_left_in[13]:11 0.0045 +29 chanx_left_in[13]:10 BUFT_P_109:A 0.152 + +*END + +*D_NET chany_top_in[3] 0.01209382 //LENGTH 94.625 LUMPCC 0.002847101 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 74.060 102.070 +*I mux_left_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 68.445 30.940 +*I mux_right_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 84.280 39.780 +*N chany_top_in[3]:3 *C 84.243 39.780 +*N chany_top_in[3]:4 *C 82.845 39.780 +*N chany_top_in[3]:5 *C 82.800 39.735 +*N chany_top_in[3]:6 *C 82.800 34.738 +*N chany_top_in[3]:7 *C 82.793 34.680 +*N chany_top_in[3]:8 *C 68.445 30.940 +*N chany_top_in[3]:9 *C 68.540 30.985 +*N chany_top_in[3]:10 *C 68.540 34.623 +*N chany_top_in[3]:11 *C 68.547 34.680 +*N chany_top_in[3]:12 *C 73.600 34.680 +*N chany_top_in[3]:13 *C 73.600 34.688 +*N chany_top_in[3]:14 *C 73.600 84.515 +*N chany_top_in[3]:15 *C 73.600 93.833 +*N chany_top_in[3]:16 *C 73.615 93.840 +*N chany_top_in[3]:17 *C 74.058 93.840 +*N chany_top_in[3]:18 *C 74.060 93.898 + +*CAP +0 chany_top_in[3] 0.0004747112 +1 mux_left_track_17\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_16\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[3]:3 0.0001115631 +4 chany_top_in[3]:4 0.0001115631 +5 chany_top_in[3]:5 0.0002914404 +6 chany_top_in[3]:6 0.0002914404 +7 chany_top_in[3]:7 0.0004470476 +8 chany_top_in[3]:8 2.751547e-05 +9 chany_top_in[3]:9 0.0002555855 +10 chany_top_in[3]:10 0.0002555855 +11 chany_top_in[3]:11 0.0002952836 +12 chany_top_in[3]:12 0.0007423313 +13 chany_top_in[3]:13 0.002281364 +14 chany_top_in[3]:14 0.002670554 +15 chany_top_in[3]:15 0.0003891909 +16 chany_top_in[3]:16 6.241687e-05 +17 chany_top_in[3]:17 6.241687e-05 +18 chany_top_in[3]:18 0.0004747112 +19 chany_top_in[3]:13 chanx_right_in[10]:30 0.0003829805 +20 chany_top_in[3]:14 chanx_right_in[10]:29 0.0003829805 +21 chany_top_in[3]:7 chanx_right_in[17]:24 0.0002056266 +22 chany_top_in[3]:11 chanx_right_in[17]:19 0.0001063263 +23 chany_top_in[3]:12 chanx_right_in[17]:19 0.0002056266 +24 chany_top_in[3]:12 chanx_right_in[17]:24 0.0001063263 +25 chany_top_in[3] chany_top_in[6] 2.188786e-05 +26 chany_top_in[3]:13 chany_top_in[6]:13 0.0001021918 +27 chany_top_in[3]:15 chany_top_in[6]:14 0.0001969185 +28 chany_top_in[3]:18 chany_top_in[6]:17 2.188786e-05 +29 chany_top_in[3]:14 chany_top_in[6]:13 0.0001969185 +30 chany_top_in[3]:14 chany_top_in[6]:14 0.0001021918 +31 chany_top_in[3]:13 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.000407619 +32 chany_top_in[3]:14 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.000407619 + +*RES +0 chany_top_in[3] chany_top_in[3]:18 0.007296875 +1 chany_top_in[3]:6 chany_top_in[3]:5 0.004462054 +2 chany_top_in[3]:7 chany_top_in[3]:6 0.00341 +3 chany_top_in[3]:4 chany_top_in[3]:3 0.001247768 +4 chany_top_in[3]:5 chany_top_in[3]:4 0.0045 +5 chany_top_in[3]:3 mux_right_track_16\/mux_l1_in_0_:A1 0.152 +6 chany_top_in[3]:10 chany_top_in[3]:9 0.003247768 +7 chany_top_in[3]:11 chany_top_in[3]:10 0.00341 +8 chany_top_in[3]:8 mux_left_track_17\/mux_l1_in_0_:A1 0.152 +9 chany_top_in[3]:9 chany_top_in[3]:8 0.0045 +10 chany_top_in[3]:12 chany_top_in[3]:11 0.0007915583 +11 chany_top_in[3]:12 chany_top_in[3]:7 0.001440158 +12 chany_top_in[3]:13 chany_top_in[3]:12 0.00341 +13 chany_top_in[3]:16 chany_top_in[3]:15 0.00341 +14 chany_top_in[3]:15 chany_top_in[3]:14 0.001459742 +15 chany_top_in[3]:18 chany_top_in[3]:17 0.00341 +16 chany_top_in[3]:17 chany_top_in[3]:16 6.499219e-05 +17 chany_top_in[3]:14 chany_top_in[3]:13 0.007806308 + +*END + +*D_NET chany_top_in[10] 0.01403889 //LENGTH 99.360 LUMPCC 0.003840762 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 73.140 102.070 +*I mux_right_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.895 39.100 +*I mux_left_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 68.830 31.960 +*N chany_top_in[10]:3 *C 67.680 39.100 +*N chany_top_in[10]:4 *C 68.868 31.960 +*N chany_top_in[10]:5 *C 71.255 31.960 +*N chany_top_in[10]:6 *C 71.300 32.005 +*N chany_top_in[10]:7 *C 83.858 39.100 +*N chany_top_in[10]:8 *C 79.625 39.100 +*N chany_top_in[10]:9 *C 79.580 39.055 +*N chany_top_in[10]:10 *C 79.580 36.778 +*N chany_top_in[10]:11 *C 79.573 36.720 +*N chany_top_in[10]:12 *C 71.308 36.720 +*N chany_top_in[10]:13 *C 71.300 36.720 +*N chany_top_in[10]:14 *C 71.300 39.055 +*N chany_top_in[10]:15 *C 71.255 39.100 +*N chany_top_in[10]:16 *C 68.125 39.100 +*N chany_top_in[10]:17 *C 68.080 39.100 +*N chany_top_in[10]:18 *C 68.080 39.100 +*N chany_top_in[10]:19 *C 68.080 39.108 +*N chany_top_in[10]:20 *C 68.080 88.935 +*N chany_top_in[10]:21 *C 68.080 99.953 +*N chany_top_in[10]:22 *C 68.100 99.960 +*N chany_top_in[10]:23 *C 73.133 99.960 +*N chany_top_in[10]:24 *C 73.140 100.017 + +*CAP +0 chany_top_in[10] 0.0001242436 +1 mux_right_track_16\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_17\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[10]:3 6.326092e-05 +4 chany_top_in[10]:4 0.000190014 +5 chany_top_in[10]:5 0.000190014 +6 chany_top_in[10]:6 0.0002721119 +7 chany_top_in[10]:7 0.0002720168 +8 chany_top_in[10]:8 0.0002720168 +9 chany_top_in[10]:9 0.0001541159 +10 chany_top_in[10]:10 0.0001541159 +11 chany_top_in[10]:11 0.0003753871 +12 chany_top_in[10]:12 0.0003753871 +13 chany_top_in[10]:13 0.0004475578 +14 chany_top_in[10]:14 0.0001378135 +15 chany_top_in[10]:15 0.0003036367 +16 chany_top_in[10]:16 0.0003036367 +17 chany_top_in[10]:17 3.783639e-05 +18 chany_top_in[10]:18 6.326092e-05 +19 chany_top_in[10]:19 0.002458638 +20 chany_top_in[10]:20 0.002911258 +21 chany_top_in[10]:21 0.0004526208 +22 chany_top_in[10]:22 0.0002564717 +23 chany_top_in[10]:23 0.0002564717 +24 chany_top_in[10]:24 0.0001242436 +25 chany_top_in[10]:12 chanx_right_in[6]:19 0.0003166933 +26 chany_top_in[10]:12 chanx_right_in[6]:20 0.0001537301 +27 chany_top_in[10]:11 chanx_right_in[6]:20 0.0003166933 +28 chany_top_in[10]:11 chanx_right_in[6]:21 0.0001537301 +29 chany_top_in[10]:18 chanx_right_in[6]:19 1.034891e-05 +30 chany_top_in[10]:3 chanx_right_in[6]:20 1.034891e-05 +31 chany_top_in[10] chany_top_in[8] 8.969557e-06 +32 chany_top_in[10]:19 chany_top_in[8]:15 0.0003724619 +33 chany_top_in[10]:22 chany_top_in[8]:17 5.665746e-05 +34 chany_top_in[10]:21 chany_top_in[8]:16 0.000227554 +35 chany_top_in[10]:24 chany_top_in[8]:19 8.969557e-06 +36 chany_top_in[10]:23 chany_top_in[8]:18 5.665746e-05 +37 chany_top_in[10]:20 chany_top_in[8]:15 0.000227554 +38 chany_top_in[10]:20 chany_top_in[8]:16 0.0003724619 +39 chany_top_in[10]:22 chany_top_in[19]:20 0.0002921534 +40 chany_top_in[10]:23 chany_top_in[19]:10 0.0002921534 +41 chany_top_in[10]:19 chanx_right_in[1]:9 0.0004818124 +42 chany_top_in[10]:20 chanx_right_in[1]:8 0.0004818124 + +*RES +0 chany_top_in[10] chany_top_in[10]:24 0.00183259 +1 chany_top_in[10]:13 chany_top_in[10]:12 0.00341 +2 chany_top_in[10]:13 chany_top_in[10]:6 0.004209822 +3 chany_top_in[10]:12 chany_top_in[10]:11 0.00129485 +4 chany_top_in[10]:10 chany_top_in[10]:9 0.002033482 +5 chany_top_in[10]:11 chany_top_in[10]:10 0.00341 +6 chany_top_in[10]:8 chany_top_in[10]:7 0.003779018 +7 chany_top_in[10]:9 chany_top_in[10]:8 0.0045 +8 chany_top_in[10]:7 mux_right_track_16\/mux_l1_in_0_:A0 0.152 +9 chany_top_in[10]:5 chany_top_in[10]:4 0.002131697 +10 chany_top_in[10]:6 chany_top_in[10]:5 0.0045 +11 chany_top_in[10]:4 mux_left_track_17\/mux_l1_in_0_:A0 0.152 +12 chany_top_in[10]:15 chany_top_in[10]:14 0.0045 +13 chany_top_in[10]:14 chany_top_in[10]:13 0.002084821 +14 chany_top_in[10]:16 chany_top_in[10]:15 0.002794643 +15 chany_top_in[10]:17 chany_top_in[10]:16 0.0045 +16 chany_top_in[10]:18 chany_top_in[10]:17 0.00341 +17 chany_top_in[10]:18 chany_top_in[10]:3 5.69697e-05 +18 chany_top_in[10]:19 chany_top_in[10]:18 0.00341 +19 chany_top_in[10]:22 chany_top_in[10]:21 0.00341 +20 chany_top_in[10]:21 chany_top_in[10]:20 0.001726075 +21 chany_top_in[10]:24 chany_top_in[10]:23 0.00341 +22 chany_top_in[10]:23 chany_top_in[10]:22 0.000788425 +23 chany_top_in[10]:20 chany_top_in[10]:19 0.007806308 + +*END + +*D_NET chany_top_in[19] 0.02286671 //LENGTH 120.790 LUMPCC 0.004581603 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 59.340 102.070 +*I mux_left_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 41.305 56.100 +*I mux_right_track_32\/mux_l1_in_1_:A1 I *L 0.00198 *C 83.165 72.420 +*N chany_top_in[19]:3 *C 83.165 72.420 +*N chany_top_in[19]:4 *C 83.260 72.420 +*N chany_top_in[19]:5 *C 83.260 72.080 +*N chany_top_in[19]:6 *C 83.267 72.080 +*N chany_top_in[19]:7 *C 84.620 72.080 +*N chany_top_in[19]:8 *C 84.640 72.088 +*N chany_top_in[19]:9 *C 84.640 99.273 +*N chany_top_in[19]:10 *C 84.620 99.280 +*N chany_top_in[19]:11 *C 41.343 56.100 +*N chany_top_in[19]:12 *C 41.815 56.100 +*N chany_top_in[19]:13 *C 41.860 56.145 +*N chany_top_in[19]:14 *C 41.860 57.742 +*N chany_top_in[19]:15 *C 41.867 57.800 +*N chany_top_in[19]:16 *C 55.180 57.800 +*N chany_top_in[19]:17 *C 55.200 57.808 +*N chany_top_in[19]:18 *C 55.200 99.273 +*N chany_top_in[19]:19 *C 55.220 99.280 +*N chany_top_in[19]:20 *C 59.340 99.280 +*N chany_top_in[19]:21 *C 59.340 99.338 + +*CAP +0 chany_top_in[19] 0.0001768018 +1 mux_left_track_5\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[19]:3 3.017614e-05 +4 chany_top_in[19]:4 6.008496e-05 +5 chany_top_in[19]:5 6.449792e-05 +6 chany_top_in[19]:6 0.0001802163 +7 chany_top_in[19]:7 0.0001802163 +8 chany_top_in[19]:8 0.002308116 +9 chany_top_in[19]:9 0.002308116 +10 chany_top_in[19]:10 0.001500214 +11 chany_top_in[19]:11 6.896681e-05 +12 chany_top_in[19]:12 6.896681e-05 +13 chany_top_in[19]:13 0.0001195463 +14 chany_top_in[19]:14 0.0001195463 +15 chany_top_in[19]:15 0.0007482334 +16 chany_top_in[19]:16 0.0007482334 +17 chany_top_in[19]:17 0.003578458 +18 chany_top_in[19]:18 0.003578458 +19 chany_top_in[19]:19 0.0003836239 +20 chany_top_in[19]:20 0.001883837 +21 chany_top_in[19]:21 0.0001768018 +22 chany_top_in[19]:10 chany_top_in[10]:23 0.0002921534 +23 chany_top_in[19]:20 chany_top_in[10]:22 0.0002921534 +24 chany_top_in[19]:16 chany_top_in[11]:13 0.0005776896 +25 chany_top_in[19]:15 chany_top_in[11]:12 0.0005776896 +26 chany_top_in[19]:18 mux_tree_tapbuf_size2_1_sram[0]:14 0.0008718407 +27 chany_top_in[19]:17 mux_tree_tapbuf_size2_1_sram[0]:15 0.0008718407 +28 chany_top_in[19]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0005491177 +29 chany_top_in[19]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0005491177 + +*RES +0 chany_top_in[19] chany_top_in[19]:21 0.002439732 +1 chany_top_in[19]:10 chany_top_in[19]:9 0.00341 +2 chany_top_in[19]:9 chany_top_in[19]:8 0.004258983 +3 chany_top_in[19]:7 chany_top_in[19]:6 0.0002118916 +4 chany_top_in[19]:8 chany_top_in[19]:7 0.00341 +5 chany_top_in[19]:5 chany_top_in[19]:4 0.0001634616 +6 chany_top_in[19]:6 chany_top_in[19]:5 0.00341 +7 chany_top_in[19]:3 mux_right_track_32\/mux_l1_in_1_:A1 0.152 +8 chany_top_in[19]:4 chany_top_in[19]:3 0.0045 +9 chany_top_in[19]:19 chany_top_in[19]:18 0.00341 +10 chany_top_in[19]:18 chany_top_in[19]:17 0.006496183 +11 chany_top_in[19]:16 chany_top_in[19]:15 0.002085625 +12 chany_top_in[19]:17 chany_top_in[19]:16 0.00341 +13 chany_top_in[19]:14 chany_top_in[19]:13 0.001426339 +14 chany_top_in[19]:15 chany_top_in[19]:14 0.00341 +15 chany_top_in[19]:12 chany_top_in[19]:11 0.000421875 +16 chany_top_in[19]:13 chany_top_in[19]:12 0.0045 +17 chany_top_in[19]:11 mux_left_track_5\/mux_l1_in_1_:A1 0.152 +18 chany_top_in[19]:21 chany_top_in[19]:20 0.00341 +19 chany_top_in[19]:20 chany_top_in[19]:19 0.0006454667 +20 chany_top_in[19]:20 chany_top_in[19]:10 0.003960533 + +*END + +*D_NET top_left_grid_pin_41_[0] 0.01513646 //LENGTH 117.105 LUMPCC 0.002487382 DR + +*CONN +*P top_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 90.440 +*I mux_top_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 53.535 88.060 +*I mux_top_track_38\/mux_l1_in_0_:A1 I *L 0.00198 *C 80.960 83.300 +*I mux_top_track_6\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.375 44.540 +*I mux_top_track_22\/mux_l1_in_0_:A1 I *L 0.00198 *C 84.640 34.340 +*N top_left_grid_pin_41_[0]:5 *C 84.640 34.340 +*N top_left_grid_pin_41_[0]:6 *C 84.640 34.385 +*N top_left_grid_pin_41_[0]:7 *C 84.640 36.335 +*N top_left_grid_pin_41_[0]:8 *C 84.595 36.380 +*N top_left_grid_pin_41_[0]:9 *C 81.005 36.380 +*N top_left_grid_pin_41_[0]:10 *C 80.960 36.425 +*N top_left_grid_pin_41_[0]:11 *C 80.960 44.540 +*N top_left_grid_pin_41_[0]:12 *C 78.413 44.540 +*N top_left_grid_pin_41_[0]:13 *C 80.455 44.540 +*N top_left_grid_pin_41_[0]:14 *C 80.500 44.540 +*N top_left_grid_pin_41_[0]:15 *C 80.922 83.300 +*N top_left_grid_pin_41_[0]:16 *C 80.545 83.300 +*N top_left_grid_pin_41_[0]:17 *C 80.500 83.300 +*N top_left_grid_pin_41_[0]:18 *C 80.500 84.943 +*N top_left_grid_pin_41_[0]:19 *C 80.493 85.000 +*N top_left_grid_pin_41_[0]:20 *C 57.968 85.000 +*N top_left_grid_pin_41_[0]:21 *C 57.960 85.058 +*N top_left_grid_pin_41_[0]:22 *C 57.960 88.015 +*N top_left_grid_pin_41_[0]:23 *C 57.915 88.060 +*N top_left_grid_pin_41_[0]:24 *C 53.535 88.060 +*N top_left_grid_pin_41_[0]:25 *C 52.945 88.060 +*N top_left_grid_pin_41_[0]:26 *C 52.900 88.105 +*N top_left_grid_pin_41_[0]:27 *C 52.900 90.383 +*N top_left_grid_pin_41_[0]:28 *C 52.893 90.440 + +*CAP +0 top_left_grid_pin_41_[0] 0.001140866 +1 mux_top_track_2\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_38\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_1_:A0 1e-06 +4 mux_top_track_22\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_41_[0]:5 3.155641e-05 +6 top_left_grid_pin_41_[0]:6 0.0001376081 +7 top_left_grid_pin_41_[0]:7 0.0001376081 +8 top_left_grid_pin_41_[0]:8 0.0002288816 +9 top_left_grid_pin_41_[0]:9 0.0002288816 +10 top_left_grid_pin_41_[0]:10 0.0004648923 +11 top_left_grid_pin_41_[0]:11 0.0004993492 +12 top_left_grid_pin_41_[0]:12 0.0001963187 +13 top_left_grid_pin_41_[0]:13 0.0001963187 +14 top_left_grid_pin_41_[0]:14 0.002068057 +15 top_left_grid_pin_41_[0]:15 5.68059e-05 +16 top_left_grid_pin_41_[0]:16 5.68059e-05 +17 top_left_grid_pin_41_[0]:17 0.002159945 +18 top_left_grid_pin_41_[0]:18 9.594833e-05 +19 top_left_grid_pin_41_[0]:19 0.001274748 +20 top_left_grid_pin_41_[0]:20 0.001274748 +21 top_left_grid_pin_41_[0]:21 0.0001592957 +22 top_left_grid_pin_41_[0]:22 0.0001592957 +23 top_left_grid_pin_41_[0]:23 0.000241556 +24 top_left_grid_pin_41_[0]:24 0.0003349499 +25 top_left_grid_pin_41_[0]:25 6.16043e-05 +26 top_left_grid_pin_41_[0]:26 0.0001490835 +27 top_left_grid_pin_41_[0]:27 0.0001490835 +28 top_left_grid_pin_41_[0]:28 0.001140866 +29 top_left_grid_pin_41_[0] top_left_grid_pin_36_[0]:27 0.0004800965 +30 top_left_grid_pin_41_[0]:28 top_left_grid_pin_36_[0]:26 0.0004800965 +31 top_left_grid_pin_41_[0]:22 top_left_grid_pin_36_[0]:25 3.216045e-05 +32 top_left_grid_pin_41_[0]:21 top_left_grid_pin_36_[0]:24 3.216045e-05 +33 top_left_grid_pin_41_[0]:20 mux_tree_tapbuf_size10_0_sram[0]:22 0.0002934282 +34 top_left_grid_pin_41_[0]:19 mux_tree_tapbuf_size10_0_sram[0]:23 0.0002934282 +35 top_left_grid_pin_41_[0]:23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000100559 +36 top_left_grid_pin_41_[0]:24 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000100559 +37 top_left_grid_pin_41_[0]:17 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.631652e-05 +38 top_left_grid_pin_41_[0]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.08719e-06 +39 top_left_grid_pin_41_[0]:14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.631652e-05 +40 top_left_grid_pin_41_[0]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.08719e-06 +41 top_left_grid_pin_41_[0] mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 3.167828e-06 +42 top_left_grid_pin_41_[0]:28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 3.167828e-06 +43 top_left_grid_pin_41_[0]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0002868753 +44 top_left_grid_pin_41_[0]:19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0002868753 + +*RES +0 top_left_grid_pin_41_[0] top_left_grid_pin_41_[0]:28 0.003625658 +1 top_left_grid_pin_41_[0]:15 mux_top_track_38\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_41_[0]:16 top_left_grid_pin_41_[0]:15 0.0003370536 +3 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:16 0.0045 +4 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:14 0.03460715 +5 top_left_grid_pin_41_[0]:25 top_left_grid_pin_41_[0]:24 0.0005267857 +6 top_left_grid_pin_41_[0]:26 top_left_grid_pin_41_[0]:25 0.0045 +7 top_left_grid_pin_41_[0]:27 top_left_grid_pin_41_[0]:26 0.002033483 +8 top_left_grid_pin_41_[0]:28 top_left_grid_pin_41_[0]:27 0.00341 +9 top_left_grid_pin_41_[0]:23 top_left_grid_pin_41_[0]:22 0.0045 +10 top_left_grid_pin_41_[0]:22 top_left_grid_pin_41_[0]:21 0.002640625 +11 top_left_grid_pin_41_[0]:21 top_left_grid_pin_41_[0]:20 0.00341 +12 top_left_grid_pin_41_[0]:20 top_left_grid_pin_41_[0]:19 0.003528917 +13 top_left_grid_pin_41_[0]:18 top_left_grid_pin_41_[0]:17 0.001466518 +14 top_left_grid_pin_41_[0]:19 top_left_grid_pin_41_[0]:18 0.00341 +15 top_left_grid_pin_41_[0]:13 top_left_grid_pin_41_[0]:12 0.001823661 +16 top_left_grid_pin_41_[0]:14 top_left_grid_pin_41_[0]:13 0.0045 +17 top_left_grid_pin_41_[0]:14 top_left_grid_pin_41_[0]:11 0.0004107143 +18 top_left_grid_pin_41_[0]:12 mux_top_track_6\/mux_l1_in_1_:A0 0.152 +19 top_left_grid_pin_41_[0]:24 mux_top_track_2\/mux_l1_in_1_:A0 0.152 +20 top_left_grid_pin_41_[0]:24 top_left_grid_pin_41_[0]:23 0.003910715 +21 top_left_grid_pin_41_[0]:5 mux_top_track_22\/mux_l1_in_0_:A1 0.152 +22 top_left_grid_pin_41_[0]:6 top_left_grid_pin_41_[0]:5 0.0045 +23 top_left_grid_pin_41_[0]:8 top_left_grid_pin_41_[0]:7 0.0045 +24 top_left_grid_pin_41_[0]:7 top_left_grid_pin_41_[0]:6 0.001741072 +25 top_left_grid_pin_41_[0]:9 top_left_grid_pin_41_[0]:8 0.003205357 +26 top_left_grid_pin_41_[0]:10 top_left_grid_pin_41_[0]:9 0.0045 +27 top_left_grid_pin_41_[0]:11 top_left_grid_pin_41_[0]:10 0.007245536 + +*END + +*D_NET right_bottom_grid_pin_1_[0] 0.01191327 //LENGTH 97.410 LUMPCC 0.002526746 DR + +*CONN +*P right_bottom_grid_pin_1_[0] I *L 0.29796 *C 139.380 1.325 +*I mux_right_track_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 131.465 47.260 +*I mux_right_track_4\/mux_l1_in_5_:A0 I *L 0.001631 *C 113.910 69.700 +*I mux_right_track_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 132.020 63.580 +*N right_bottom_grid_pin_1_[0]:4 *C 131.983 63.580 +*N right_bottom_grid_pin_1_[0]:5 *C 131.605 63.580 +*N right_bottom_grid_pin_1_[0]:6 *C 131.560 63.535 +*N right_bottom_grid_pin_1_[0]:7 *C 113.948 69.700 +*N right_bottom_grid_pin_1_[0]:8 *C 120.015 69.700 +*N right_bottom_grid_pin_1_[0]:9 *C 120.060 69.655 +*N right_bottom_grid_pin_1_[0]:10 *C 120.060 62.617 +*N right_bottom_grid_pin_1_[0]:11 *C 120.068 62.560 +*N right_bottom_grid_pin_1_[0]:12 *C 131.553 62.560 +*N right_bottom_grid_pin_1_[0]:13 *C 131.560 62.560 +*N right_bottom_grid_pin_1_[0]:14 *C 131.465 47.260 +*N right_bottom_grid_pin_1_[0]:15 *C 131.560 47.260 +*N right_bottom_grid_pin_1_[0]:16 *C 131.560 3.785 +*N right_bottom_grid_pin_1_[0]:17 *C 131.605 3.740 +*N right_bottom_grid_pin_1_[0]:18 *C 139.335 3.740 +*N right_bottom_grid_pin_1_[0]:19 *C 139.380 3.695 + +*CAP +0 right_bottom_grid_pin_1_[0] 0.0001223739 +1 mux_right_track_8\/mux_l2_in_2_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_5_:A0 1e-06 +3 mux_right_track_0\/mux_l2_in_2_:A1 1e-06 +4 right_bottom_grid_pin_1_[0]:4 5.488388e-05 +5 right_bottom_grid_pin_1_[0]:5 5.488388e-05 +6 right_bottom_grid_pin_1_[0]:6 6.958467e-05 +7 right_bottom_grid_pin_1_[0]:7 0.0004597024 +8 right_bottom_grid_pin_1_[0]:8 0.0004597024 +9 right_bottom_grid_pin_1_[0]:9 0.0004052712 +10 right_bottom_grid_pin_1_[0]:10 0.0004052712 +11 right_bottom_grid_pin_1_[0]:11 0.0003701173 +12 right_bottom_grid_pin_1_[0]:12 0.0003701173 +13 right_bottom_grid_pin_1_[0]:13 0.0007830571 +14 right_bottom_grid_pin_1_[0]:14 3.063916e-05 +15 right_bottom_grid_pin_1_[0]:15 0.002785151 +16 right_bottom_grid_pin_1_[0]:16 0.002075914 +17 right_bottom_grid_pin_1_[0]:17 0.0004072426 +18 right_bottom_grid_pin_1_[0]:18 0.0004072426 +19 right_bottom_grid_pin_1_[0]:19 0.0001223739 +20 right_bottom_grid_pin_1_[0]:16 chanx_left_in[9]:8 0.0001576387 +21 right_bottom_grid_pin_1_[0]:15 chanx_left_in[9]:8 0.0001290087 +22 right_bottom_grid_pin_1_[0]:15 chanx_left_in[9]:9 0.0001576387 +23 right_bottom_grid_pin_1_[0]:13 chanx_left_in[9]:9 0.0001290087 +24 right_bottom_grid_pin_1_[0]:12 chanx_left_in[9]:15 0.000306571 +25 right_bottom_grid_pin_1_[0]:11 chanx_left_in[9]:16 0.000306571 +26 right_bottom_grid_pin_1_[0]:12 chanx_left_in[10]:14 0.0005657495 +27 right_bottom_grid_pin_1_[0]:11 chanx_left_in[10]:15 0.0005657495 +28 right_bottom_grid_pin_1_[0]:15 ropt_net_173:8 1.026951e-05 +29 right_bottom_grid_pin_1_[0]:13 ropt_net_173:9 1.026951e-05 +30 right_bottom_grid_pin_1_[0]:12 ropt_net_173:6 4.268513e-05 +31 right_bottom_grid_pin_1_[0]:11 ropt_net_173:7 4.268513e-05 +32 right_bottom_grid_pin_1_[0]:15 ropt_net_146:6 5.145044e-05 +33 right_bottom_grid_pin_1_[0]:13 ropt_net_146:5 5.145044e-05 + +*RES +0 right_bottom_grid_pin_1_[0] right_bottom_grid_pin_1_[0]:19 0.002116072 +1 right_bottom_grid_pin_1_[0]:4 mux_right_track_0\/mux_l2_in_2_:A1 0.152 +2 right_bottom_grid_pin_1_[0]:5 right_bottom_grid_pin_1_[0]:4 0.0003370536 +3 right_bottom_grid_pin_1_[0]:6 right_bottom_grid_pin_1_[0]:5 0.0045 +4 right_bottom_grid_pin_1_[0]:17 right_bottom_grid_pin_1_[0]:16 0.0045 +5 right_bottom_grid_pin_1_[0]:16 right_bottom_grid_pin_1_[0]:15 0.03881697 +6 right_bottom_grid_pin_1_[0]:18 right_bottom_grid_pin_1_[0]:17 0.006901786 +7 right_bottom_grid_pin_1_[0]:19 right_bottom_grid_pin_1_[0]:18 0.0045 +8 right_bottom_grid_pin_1_[0]:14 mux_right_track_8\/mux_l2_in_2_:A1 0.152 +9 right_bottom_grid_pin_1_[0]:15 right_bottom_grid_pin_1_[0]:14 0.0045 +10 right_bottom_grid_pin_1_[0]:15 right_bottom_grid_pin_1_[0]:13 0.01366072 +11 right_bottom_grid_pin_1_[0]:13 right_bottom_grid_pin_1_[0]:12 0.00341 +12 right_bottom_grid_pin_1_[0]:13 right_bottom_grid_pin_1_[0]:6 0.0008705357 +13 right_bottom_grid_pin_1_[0]:12 right_bottom_grid_pin_1_[0]:11 0.001799316 +14 right_bottom_grid_pin_1_[0]:10 right_bottom_grid_pin_1_[0]:9 0.006283483 +15 right_bottom_grid_pin_1_[0]:11 right_bottom_grid_pin_1_[0]:10 0.00341 +16 right_bottom_grid_pin_1_[0]:8 right_bottom_grid_pin_1_[0]:7 0.005417411 +17 right_bottom_grid_pin_1_[0]:9 right_bottom_grid_pin_1_[0]:8 0.0045 +18 right_bottom_grid_pin_1_[0]:7 mux_right_track_4\/mux_l1_in_5_:A0 0.152 + +*END + +*D_NET left_top_grid_pin_49_[0] 0.004761131 //LENGTH 38.740 LUMPCC 0.0007319247 DR + +*CONN +*P left_top_grid_pin_49_[0] I *L 0.29796 *C 10.580 74.870 +*I mux_left_track_5\/mux_l1_in_6_:A1 I *L 0.00198 *C 9.200 47.260 +*I mux_left_track_33\/mux_l1_in_2_:A0 I *L 0.001631 *C 12.595 60.520 +*I mux_left_track_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 9.300 72.420 +*N left_top_grid_pin_49_[0]:4 *C 9.300 72.420 +*N left_top_grid_pin_49_[0]:5 *C 12.558 60.520 +*N left_top_grid_pin_49_[0]:6 *C 9.245 60.520 +*N left_top_grid_pin_49_[0]:7 *C 9.200 60.565 +*N left_top_grid_pin_49_[0]:8 *C 9.162 47.260 +*N left_top_grid_pin_49_[0]:9 *C 8.785 47.260 +*N left_top_grid_pin_49_[0]:10 *C 8.740 47.305 +*N left_top_grid_pin_49_[0]:11 *C 8.740 52.020 +*N left_top_grid_pin_49_[0]:12 *C 7.820 52.020 +*N left_top_grid_pin_49_[0]:13 *C 7.820 61.155 +*N left_top_grid_pin_49_[0]:14 *C 7.865 61.200 +*N left_top_grid_pin_49_[0]:15 *C 9.155 61.200 +*N left_top_grid_pin_49_[0]:16 *C 9.200 61.200 +*N left_top_grid_pin_49_[0]:17 *C 9.200 72.715 +*N left_top_grid_pin_49_[0]:18 *C 9.268 72.760 +*N left_top_grid_pin_49_[0]:19 *C 10.535 72.760 +*N left_top_grid_pin_49_[0]:20 *C 10.580 72.805 + +*CAP +0 left_top_grid_pin_49_[0] 0.0001067492 +1 mux_left_track_5\/mux_l1_in_6_:A1 1e-06 +2 mux_left_track_33\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_3\/mux_l2_in_3_:A1 1e-06 +4 left_top_grid_pin_49_[0]:4 5.920074e-05 +5 left_top_grid_pin_49_[0]:5 0.0002227872 +6 left_top_grid_pin_49_[0]:6 0.0002227872 +7 left_top_grid_pin_49_[0]:7 4.105022e-05 +8 left_top_grid_pin_49_[0]:8 5.618226e-05 +9 left_top_grid_pin_49_[0]:9 5.618226e-05 +10 left_top_grid_pin_49_[0]:10 0.0002623769 +11 left_top_grid_pin_49_[0]:11 0.0003125289 +12 left_top_grid_pin_49_[0]:12 0.0005513128 +13 left_top_grid_pin_49_[0]:13 0.0005011608 +14 left_top_grid_pin_49_[0]:14 0.0001301824 +15 left_top_grid_pin_49_[0]:15 0.0001301824 +16 left_top_grid_pin_49_[0]:16 0.000540735 +17 left_top_grid_pin_49_[0]:17 0.0004632999 +18 left_top_grid_pin_49_[0]:18 0.0001474888 +19 left_top_grid_pin_49_[0]:19 0.0001152498 +20 left_top_grid_pin_49_[0]:20 0.0001067492 +21 left_top_grid_pin_49_[0] left_top_grid_pin_46_[0]:21 2.371635e-05 +22 left_top_grid_pin_49_[0]:13 left_top_grid_pin_46_[0]:7 7.023509e-07 +23 left_top_grid_pin_49_[0]:16 left_top_grid_pin_46_[0]:20 0.0002997307 +24 left_top_grid_pin_49_[0]:16 left_top_grid_pin_46_[0]:21 1.992959e-05 +25 left_top_grid_pin_49_[0]:20 left_top_grid_pin_46_[0]:20 2.371635e-05 +26 left_top_grid_pin_49_[0]:17 left_top_grid_pin_46_[0]:21 0.0002997307 +27 left_top_grid_pin_49_[0]:6 left_top_grid_pin_46_[0]:7 2.188343e-05 +28 left_top_grid_pin_49_[0]:7 left_top_grid_pin_46_[0]:20 1.992959e-05 +29 left_top_grid_pin_49_[0]:5 left_top_grid_pin_46_[0]:20 2.188343e-05 +30 left_top_grid_pin_49_[0]:12 left_top_grid_pin_46_[0]:6 7.023509e-07 + +*RES +0 left_top_grid_pin_49_[0] left_top_grid_pin_49_[0]:20 0.00184375 +1 left_top_grid_pin_49_[0]:8 mux_left_track_5\/mux_l1_in_6_:A1 0.152 +2 left_top_grid_pin_49_[0]:9 left_top_grid_pin_49_[0]:8 0.0003370536 +3 left_top_grid_pin_49_[0]:10 left_top_grid_pin_49_[0]:9 0.0045 +4 left_top_grid_pin_49_[0]:14 left_top_grid_pin_49_[0]:13 0.0045 +5 left_top_grid_pin_49_[0]:13 left_top_grid_pin_49_[0]:12 0.00815625 +6 left_top_grid_pin_49_[0]:15 left_top_grid_pin_49_[0]:14 0.001151786 +7 left_top_grid_pin_49_[0]:16 left_top_grid_pin_49_[0]:15 0.0045 +8 left_top_grid_pin_49_[0]:16 left_top_grid_pin_49_[0]:7 0.0005669643 +9 left_top_grid_pin_49_[0]:19 left_top_grid_pin_49_[0]:18 0.001131697 +10 left_top_grid_pin_49_[0]:20 left_top_grid_pin_49_[0]:19 0.0045 +11 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:17 0.0045 +12 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:4 0.0001847826 +13 left_top_grid_pin_49_[0]:17 left_top_grid_pin_49_[0]:16 0.01028125 +14 left_top_grid_pin_49_[0]:6 left_top_grid_pin_49_[0]:5 0.002957589 +15 left_top_grid_pin_49_[0]:7 left_top_grid_pin_49_[0]:6 0.0045 +16 left_top_grid_pin_49_[0]:5 mux_left_track_33\/mux_l1_in_2_:A0 0.152 +17 left_top_grid_pin_49_[0]:4 mux_left_track_3\/mux_l2_in_3_:A1 0.152 +18 left_top_grid_pin_49_[0]:12 left_top_grid_pin_49_[0]:11 0.0008214285 +19 left_top_grid_pin_49_[0]:11 left_top_grid_pin_49_[0]:10 0.004209822 + +*END + +*D_NET chanx_right_out[8] 0.002658285 //LENGTH 14.820 LUMPCC 0.001440749 DR + +*CONN +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 126.100 34.000 +*P chanx_right_out[8] O *L 0.7423 *C 140.450 34.000 +*N chanx_right_out[8]:2 *C 126.508 34.000 +*N chanx_right_out[8]:3 *C 126.500 34.000 +*N chanx_right_out[8]:4 *C 126.478 34.000 +*N chanx_right_out[8]:5 *C 126.115 34.000 + +*CAP +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[8] 0.0005377919 +2 chanx_right_out[8]:2 0.0005377919 +3 chanx_right_out[8]:3 3.609092e-05 +4 chanx_right_out[8]:4 5.243115e-05 +5 chanx_right_out[8]:5 5.243115e-05 +6 chanx_right_out[8] chanx_right_in[17]:25 0.0007203743 +7 chanx_right_out[8]:2 chanx_right_in[17]:24 0.0007203743 + +*RES +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[8]:5 0.152 +1 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +2 chanx_right_out[8]:2 chanx_right_out[8] 0.002184325 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.0045 +4 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0001970109 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.001954419 //LENGTH 15.475 LUMPCC 0.0001080775 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 33.885 69.700 +*I mux_left_track_1\/mux_l4_in_0_:S I *L 0.00357 *C 29.540 61.880 +*I mem_left_track_1\/FTB_33__59:A I *L 0.001746 *C 31.740 72.080 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 31.740 72.080 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 31.740 72.035 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 29.578 61.880 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 31.695 61.880 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 31.740 61.925 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 31.740 69.700 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 31.785 69.700 +*N mux_tree_tapbuf_size10_0_sram[3]:10 *C 33.848 69.700 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:S 1e-06 +2 mem_left_track_1\/FTB_33__59:A 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 3.564219e-05 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001378402 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0001303103 +6 mux_tree_tapbuf_size10_0_sram[3]:6 0.0001303103 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0004360994 +8 mux_tree_tapbuf_size10_0_sram[3]:8 0.0006067261 +9 mux_tree_tapbuf_size10_0_sram[3]:9 0.0001832064 +10 mux_tree_tapbuf_size10_0_sram[3]:10 0.0001832064 +11 mux_tree_tapbuf_size10_0_sram[3]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.660139e-08 +12 mux_tree_tapbuf_size10_0_sram[3]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.398215e-05 +13 mux_tree_tapbuf_size10_0_sram[3]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.660139e-08 +14 mux_tree_tapbuf_size10_0_sram[3]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.398215e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:3 mem_left_track_1\/FTB_33__59:A 0.152 +2 mux_tree_tapbuf_size10_0_sram[3]:4 mux_tree_tapbuf_size10_0_sram[3]:3 0.0045 +3 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.0045 +4 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.006941965 +5 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:4 0.002084821 +6 mux_tree_tapbuf_size10_0_sram[3]:10 mux_tree_tapbuf_size10_0_sram[3]:9 0.001841518 +7 mux_tree_tapbuf_size10_0_sram[3]:6 mux_tree_tapbuf_size10_0_sram[3]:5 0.001890625 +8 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size10_0_sram[3]:5 mux_left_track_1\/mux_l4_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.0023735 //LENGTH 19.750 LUMPCC 0.0001380366 DR + +*CONN +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 59.645 26.355 +*I mem_top_track_28\/FTB_22__48:A I *L 0.001746 *C 55.660 23.120 +*I mux_top_track_28\/mux_l2_in_0_:S I *L 0.00357 *C 65.680 31.280 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 65.642 31.280 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 59.845 31.280 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 59.800 31.235 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 59.800 26.225 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 59.678 26.180 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 55.698 23.120 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 56.535 23.120 +*N mux_tree_tapbuf_size2_0_sram[1]:10 *C 56.580 23.165 +*N mux_tree_tapbuf_size2_0_sram[1]:11 *C 56.580 26.135 +*N mux_tree_tapbuf_size2_0_sram[1]:12 *C 56.625 26.180 +*N mux_tree_tapbuf_size2_0_sram[1]:13 *C 59.608 26.245 + +*CAP +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_28\/FTB_22__48:A 1e-06 +2 mux_top_track_28\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 0.0004217841 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0004217841 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.0002458309 +6 mux_tree_tapbuf_size2_0_sram[1]:6 0.0002458309 +7 mux_tree_tapbuf_size2_0_sram[1]:7 1.902278e-05 +8 mux_tree_tapbuf_size2_0_sram[1]:8 7.119885e-05 +9 mux_tree_tapbuf_size2_0_sram[1]:9 7.119885e-05 +10 mux_tree_tapbuf_size2_0_sram[1]:10 0.0001729898 +11 mux_tree_tapbuf_size2_0_sram[1]:11 0.0001729898 +12 mux_tree_tapbuf_size2_0_sram[1]:12 0.0001854054 +13 mux_tree_tapbuf_size2_0_sram[1]:13 0.0002044281 +14 mux_tree_tapbuf_size2_0_sram[1]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 6.901832e-05 +15 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 6.901832e-05 + +*RES +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0045 +2 mux_tree_tapbuf_size2_0_sram[1]:6 mux_tree_tapbuf_size2_0_sram[1]:5 0.004473215 +3 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.00517634 +4 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size2_0_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size2_0_sram[1]:3 mux_top_track_28\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_0_sram[1]:12 mux_tree_tapbuf_size2_0_sram[1]:11 0.0045 +7 mux_tree_tapbuf_size2_0_sram[1]:11 mux_tree_tapbuf_size2_0_sram[1]:10 0.002651786 +8 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 0.0007477679 +9 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size2_0_sram[1]:8 mem_top_track_28\/FTB_22__48:A 0.152 +11 mux_tree_tapbuf_size2_0_sram[1]:13 mux_tree_tapbuf_size2_0_sram[1]:12 0.002662946 +12 mux_tree_tapbuf_size2_0_sram[1]:13 mux_tree_tapbuf_size2_0_sram[1]:7 6.25e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.001306373 //LENGTH 9.605 LUMPCC 0 DR + +*CONN +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 58.265 96.900 +*I mux_top_track_36\/mux_l1_in_0_:S I *L 0.00357 *C 56.020 94.180 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.895 93.500 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 60.858 93.500 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 58.420 93.500 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 56.058 94.180 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 58.420 94.150 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 58.420 94.225 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 58.420 96.855 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 58.420 96.900 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 58.265 96.900 + +*CAP +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_36\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 0.0001823121 +4 mux_tree_tapbuf_size2_4_sram[0]:4 0.000230695 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.000176903 +6 mux_tree_tapbuf_size2_4_sram[0]:6 0.0002252859 +7 mux_tree_tapbuf_size2_4_sram[0]:7 0.000187061 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.000187061 +9 mux_tree_tapbuf_size2_4_sram[0]:9 5.977154e-05 +10 mux_tree_tapbuf_size2_4_sram[0]:10 5.428384e-05 + +*RES +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:10 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:3 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_4_sram[0]:6 mux_tree_tapbuf_size2_4_sram[0]:5 0.002109375 +3 mux_tree_tapbuf_size2_4_sram[0]:6 mux_tree_tapbuf_size2_4_sram[0]:4 0.0005803572 +4 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.002348214 +7 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 8.423914e-05 +8 mux_tree_tapbuf_size2_4_sram[0]:5 mux_top_track_36\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_4_sram[0]:4 mux_tree_tapbuf_size2_4_sram[0]:3 0.002176339 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[0] 0.002624262 //LENGTH 19.025 LUMPCC 0.0002473772 DR + +*CONN +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 59.185 42.500 +*I mux_top_track_18\/mux_l1_in_1_:S I *L 0.00357 *C 61.280 39.440 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 58.135 37.060 +*I mux_top_track_18\/mux_l1_in_0_:S I *L 0.00357 *C 64.960 45.560 +*N mux_tree_tapbuf_size3_3_sram[0]:4 *C 64.860 45.560 +*N mux_tree_tapbuf_size3_3_sram[0]:5 *C 64.860 45.515 +*N mux_tree_tapbuf_size3_3_sram[0]:6 *C 64.860 44.245 +*N mux_tree_tapbuf_size3_3_sram[0]:7 *C 64.815 44.200 +*N mux_tree_tapbuf_size3_3_sram[0]:8 *C 59.385 44.200 +*N mux_tree_tapbuf_size3_3_sram[0]:9 *C 59.340 44.155 +*N mux_tree_tapbuf_size3_3_sram[0]:10 *C 58.172 37.060 +*N mux_tree_tapbuf_size3_3_sram[0]:11 *C 59.295 37.060 +*N mux_tree_tapbuf_size3_3_sram[0]:12 *C 59.340 37.105 +*N mux_tree_tapbuf_size3_3_sram[0]:13 *C 61.242 39.440 +*N mux_tree_tapbuf_size3_3_sram[0]:14 *C 59.385 39.440 +*N mux_tree_tapbuf_size3_3_sram[0]:15 *C 59.340 39.440 +*N mux_tree_tapbuf_size3_3_sram[0]:16 *C 59.340 42.500 +*N mux_tree_tapbuf_size3_3_sram[0]:17 *C 59.340 42.500 +*N mux_tree_tapbuf_size3_3_sram[0]:18 *C 59.185 42.500 + +*CAP +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_18\/mux_l1_in_1_:S 1e-06 +2 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_18\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_3_sram[0]:4 3.458743e-05 +5 mux_tree_tapbuf_size3_3_sram[0]:5 0.0001061296 +6 mux_tree_tapbuf_size3_3_sram[0]:6 0.0001061296 +7 mux_tree_tapbuf_size3_3_sram[0]:7 0.0003648826 +8 mux_tree_tapbuf_size3_3_sram[0]:8 0.0003648826 +9 mux_tree_tapbuf_size3_3_sram[0]:9 7.995303e-05 +10 mux_tree_tapbuf_size3_3_sram[0]:10 8.97166e-05 +11 mux_tree_tapbuf_size3_3_sram[0]:11 8.97166e-05 +12 mux_tree_tapbuf_size3_3_sram[0]:12 0.0001336405 +13 mux_tree_tapbuf_size3_3_sram[0]:13 0.0001738259 +14 mux_tree_tapbuf_size3_3_sram[0]:14 0.0001738259 +15 mux_tree_tapbuf_size3_3_sram[0]:15 0.0003012641 +16 mux_tree_tapbuf_size3_3_sram[0]:16 0.0002480105 +17 mux_tree_tapbuf_size3_3_sram[0]:17 5.495904e-05 +18 mux_tree_tapbuf_size3_3_sram[0]:18 5.136154e-05 +19 mux_tree_tapbuf_size3_3_sram[0]:8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.305648e-06 +20 mux_tree_tapbuf_size3_3_sram[0]:8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.740165e-05 +21 mux_tree_tapbuf_size3_3_sram[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.740165e-05 +22 mux_tree_tapbuf_size3_3_sram[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.305648e-06 +23 mux_tree_tapbuf_size3_3_sram[0]:16 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.920001e-05 +24 mux_tree_tapbuf_size3_3_sram[0]:16 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.412072e-05 +25 mux_tree_tapbuf_size3_3_sram[0]:15 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.920001e-05 +26 mux_tree_tapbuf_size3_3_sram[0]:8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.066059e-05 +27 mux_tree_tapbuf_size3_3_sram[0]:9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.412072e-05 +28 mux_tree_tapbuf_size3_3_sram[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.066059e-05 + +*RES +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_3_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_3_sram[0]:11 mux_tree_tapbuf_size3_3_sram[0]:10 0.001002232 +2 mux_tree_tapbuf_size3_3_sram[0]:12 mux_tree_tapbuf_size3_3_sram[0]:11 0.0045 +3 mux_tree_tapbuf_size3_3_sram[0]:10 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:16 0.0045 +5 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:15 0.002732143 +6 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:9 0.001477678 +7 mux_tree_tapbuf_size3_3_sram[0]:18 mux_tree_tapbuf_size3_3_sram[0]:17 8.423914e-05 +8 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:13 0.001658482 +9 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:14 0.0045 +10 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:12 0.002084821 +11 mux_tree_tapbuf_size3_3_sram[0]:13 mux_top_track_18\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size3_3_sram[0]:8 mux_tree_tapbuf_size3_3_sram[0]:7 0.004848215 +13 mux_tree_tapbuf_size3_3_sram[0]:9 mux_tree_tapbuf_size3_3_sram[0]:8 0.0045 +14 mux_tree_tapbuf_size3_3_sram[0]:7 mux_tree_tapbuf_size3_3_sram[0]:6 0.0045 +15 mux_tree_tapbuf_size3_3_sram[0]:6 mux_tree_tapbuf_size3_3_sram[0]:5 0.001133929 +16 mux_tree_tapbuf_size3_3_sram[0]:4 mux_top_track_18\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size3_3_sram[0]:5 mux_tree_tapbuf_size3_3_sram[0]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[1] 0.002491559 //LENGTH 17.835 LUMPCC 0.0004064728 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 108.405 37.060 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 111.490 39.100 +*I mux_top_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 105.240 40.120 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 113.260 41.480 +*N mux_tree_tapbuf_size4_0_sram[1]:4 *C 113.223 41.480 +*N mux_tree_tapbuf_size4_0_sram[1]:5 *C 108.145 41.480 +*N mux_tree_tapbuf_size4_0_sram[1]:6 *C 108.100 41.435 +*N mux_tree_tapbuf_size4_0_sram[1]:7 *C 105.278 40.120 +*N mux_tree_tapbuf_size4_0_sram[1]:8 *C 108.055 40.120 +*N mux_tree_tapbuf_size4_0_sram[1]:9 *C 108.100 40.120 +*N mux_tree_tapbuf_size4_0_sram[1]:10 *C 111.468 39.073 +*N mux_tree_tapbuf_size4_0_sram[1]:11 *C 111.455 38.760 +*N mux_tree_tapbuf_size4_0_sram[1]:12 *C 108.145 38.760 +*N mux_tree_tapbuf_size4_0_sram[1]:13 *C 108.100 38.760 +*N mux_tree_tapbuf_size4_0_sram[1]:14 *C 108.100 37.105 +*N mux_tree_tapbuf_size4_0_sram[1]:15 *C 108.100 37.060 +*N mux_tree_tapbuf_size4_0_sram[1]:16 *C 108.405 37.060 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_top_track_8\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_0_sram[1]:4 0.0002311789 +5 mux_tree_tapbuf_size4_0_sram[1]:5 0.0002311789 +6 mux_tree_tapbuf_size4_0_sram[1]:6 8.214884e-05 +7 mux_tree_tapbuf_size4_0_sram[1]:7 0.0002264736 +8 mux_tree_tapbuf_size4_0_sram[1]:8 0.0002264736 +9 mux_tree_tapbuf_size4_0_sram[1]:9 0.0001817223 +10 mux_tree_tapbuf_size4_0_sram[1]:10 3.037221e-05 +11 mux_tree_tapbuf_size4_0_sram[1]:11 0.0002598315 +12 mux_tree_tapbuf_size4_0_sram[1]:12 0.0002294593 +13 mux_tree_tapbuf_size4_0_sram[1]:13 0.0001927448 +14 mux_tree_tapbuf_size4_0_sram[1]:14 9.317128e-05 +15 mux_tree_tapbuf_size4_0_sram[1]:15 5.032656e-05 +16 mux_tree_tapbuf_size4_0_sram[1]:16 4.600432e-05 +17 mux_tree_tapbuf_size4_0_sram[1]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002032364 +18 mux_tree_tapbuf_size4_0_sram[1]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002032364 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size4_0_sram[1]:10 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size4_0_sram[1]:12 mux_tree_tapbuf_size4_0_sram[1]:11 0.002955357 +3 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:9 0.001214286 +5 mux_tree_tapbuf_size4_0_sram[1]:15 mux_tree_tapbuf_size4_0_sram[1]:14 0.0045 +6 mux_tree_tapbuf_size4_0_sram[1]:14 mux_tree_tapbuf_size4_0_sram[1]:13 0.001477679 +7 mux_tree_tapbuf_size4_0_sram[1]:16 mux_tree_tapbuf_size4_0_sram[1]:15 0.0001657609 +8 mux_tree_tapbuf_size4_0_sram[1]:8 mux_tree_tapbuf_size4_0_sram[1]:7 0.002479911 +9 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:8 0.0045 +10 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:6 0.001174107 +11 mux_tree_tapbuf_size4_0_sram[1]:7 mux_top_track_8\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size4_0_sram[1]:5 mux_tree_tapbuf_size4_0_sram[1]:4 0.004533482 +13 mux_tree_tapbuf_size4_0_sram[1]:6 mux_tree_tapbuf_size4_0_sram[1]:5 0.0045 +14 mux_tree_tapbuf_size4_0_sram[1]:4 mux_top_track_8\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size4_0_sram[1]:11 mux_tree_tapbuf_size4_0_sram[1]:10 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[2] 0.001286993 //LENGTH 10.070 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 78.965 61.200 +*I mem_top_track_4\/FTB_6__32:A I *L 0.001746 *C 78.660 58.480 +*I mux_top_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 76.720 56.440 +*N mux_tree_tapbuf_size7_1_sram[2]:3 *C 76.758 56.440 +*N mux_tree_tapbuf_size7_1_sram[2]:4 *C 77.235 56.440 +*N mux_tree_tapbuf_size7_1_sram[2]:5 *C 77.280 56.485 +*N mux_tree_tapbuf_size7_1_sram[2]:6 *C 78.623 58.480 +*N mux_tree_tapbuf_size7_1_sram[2]:7 *C 77.280 58.480 +*N mux_tree_tapbuf_size7_1_sram[2]:8 *C 77.280 58.820 +*N mux_tree_tapbuf_size7_1_sram[2]:9 *C 77.280 58.820 +*N mux_tree_tapbuf_size7_1_sram[2]:10 *C 77.280 61.155 +*N mux_tree_tapbuf_size7_1_sram[2]:11 *C 77.325 61.200 +*N mux_tree_tapbuf_size7_1_sram[2]:12 *C 78.928 61.200 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_4\/FTB_6__32:A 1e-06 +2 mux_top_track_4\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_1_sram[2]:3 5.561153e-05 +4 mux_tree_tapbuf_size7_1_sram[2]:4 5.561153e-05 +5 mux_tree_tapbuf_size7_1_sram[2]:5 0.000142787 +6 mux_tree_tapbuf_size7_1_sram[2]:6 0.0001057917 +7 mux_tree_tapbuf_size7_1_sram[2]:7 0.000134656 +8 mux_tree_tapbuf_size7_1_sram[2]:8 6.242222e-05 +9 mux_tree_tapbuf_size7_1_sram[2]:9 0.0003281604 +10 mux_tree_tapbuf_size7_1_sram[2]:10 0.0001521889 +11 mux_tree_tapbuf_size7_1_sram[2]:11 0.0001233819 +12 mux_tree_tapbuf_size7_1_sram[2]:12 0.0001233819 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_1_sram[2]:12 0.152 +1 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:7 0.0003035715 +2 mux_tree_tapbuf_size7_1_sram[2]:9 mux_tree_tapbuf_size7_1_sram[2]:8 0.0045 +3 mux_tree_tapbuf_size7_1_sram[2]:9 mux_tree_tapbuf_size7_1_sram[2]:5 0.002084821 +4 mux_tree_tapbuf_size7_1_sram[2]:6 mem_top_track_4\/FTB_6__32:A 0.152 +5 mux_tree_tapbuf_size7_1_sram[2]:11 mux_tree_tapbuf_size7_1_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size7_1_sram[2]:10 mux_tree_tapbuf_size7_1_sram[2]:9 0.002084821 +7 mux_tree_tapbuf_size7_1_sram[2]:12 mux_tree_tapbuf_size7_1_sram[2]:11 0.001430804 +8 mux_tree_tapbuf_size7_1_sram[2]:4 mux_tree_tapbuf_size7_1_sram[2]:3 0.0004263393 +9 mux_tree_tapbuf_size7_1_sram[2]:5 mux_tree_tapbuf_size7_1_sram[2]:4 0.0045 +10 mux_tree_tapbuf_size7_1_sram[2]:3 mux_top_track_4\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size7_1_sram[2]:7 mux_tree_tapbuf_size7_1_sram[2]:6 0.001198661 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[1] 0.002588892 //LENGTH 19.820 LUMPCC 0.0003675556 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 88.165 61.200 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 90.520 58.480 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 88.495 66.300 +*I mux_right_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 95.120 61.880 +*N mux_tree_tapbuf_size7_4_sram[1]:4 *C 95.083 61.880 +*N mux_tree_tapbuf_size7_4_sram[1]:5 *C 88.532 66.300 +*N mux_tree_tapbuf_size7_4_sram[1]:6 *C 89.655 66.300 +*N mux_tree_tapbuf_size7_4_sram[1]:7 *C 89.700 66.255 +*N mux_tree_tapbuf_size7_4_sram[1]:8 *C 89.700 61.925 +*N mux_tree_tapbuf_size7_4_sram[1]:9 *C 89.700 61.880 +*N mux_tree_tapbuf_size7_4_sram[1]:10 *C 88.320 61.880 +*N mux_tree_tapbuf_size7_4_sram[1]:11 *C 90.483 58.480 +*N mux_tree_tapbuf_size7_4_sram[1]:12 *C 88.365 58.480 +*N mux_tree_tapbuf_size7_4_sram[1]:13 *C 88.320 58.525 +*N mux_tree_tapbuf_size7_4_sram[1]:14 *C 88.320 61.155 +*N mux_tree_tapbuf_size7_4_sram[1]:15 *C 88.320 61.200 +*N mux_tree_tapbuf_size7_4_sram[1]:16 *C 88.165 61.200 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_24\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_4_sram[1]:4 0.0003334317 +5 mux_tree_tapbuf_size7_4_sram[1]:5 9.899508e-05 +6 mux_tree_tapbuf_size7_4_sram[1]:6 9.899508e-05 +7 mux_tree_tapbuf_size7_4_sram[1]:7 0.0002173851 +8 mux_tree_tapbuf_size7_4_sram[1]:8 0.0002173851 +9 mux_tree_tapbuf_size7_4_sram[1]:9 0.0004638589 +10 mux_tree_tapbuf_size7_4_sram[1]:10 0.0001363531 +11 mux_tree_tapbuf_size7_4_sram[1]:11 0.0001014145 +12 mux_tree_tapbuf_size7_4_sram[1]:12 0.0001014145 +13 mux_tree_tapbuf_size7_4_sram[1]:13 0.0001448133 +14 mux_tree_tapbuf_size7_4_sram[1]:14 0.0001448133 +15 mux_tree_tapbuf_size7_4_sram[1]:15 0.0001005845 +16 mux_tree_tapbuf_size7_4_sram[1]:16 5.789266e-05 +17 mux_tree_tapbuf_size7_4_sram[1]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.443202e-06 +18 mux_tree_tapbuf_size7_4_sram[1]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.695349e-05 +19 mux_tree_tapbuf_size7_4_sram[1]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.443202e-06 +20 mux_tree_tapbuf_size7_4_sram[1]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.695349e-05 +21 mux_tree_tapbuf_size7_4_sram[1]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.580189e-05 +22 mux_tree_tapbuf_size7_4_sram[1]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.829432e-06 +23 mux_tree_tapbuf_size7_4_sram[1]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.580189e-05 +24 mux_tree_tapbuf_size7_4_sram[1]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.829432e-06 +25 mux_tree_tapbuf_size7_4_sram[1]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.19187e-05 +26 mux_tree_tapbuf_size7_4_sram[1]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.19187e-05 +27 mux_tree_tapbuf_size7_4_sram[1]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.583107e-05 +28 mux_tree_tapbuf_size7_4_sram[1]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.583107e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_4_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_4_sram[1]:4 mux_right_track_24\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_4_sram[1]:15 mux_tree_tapbuf_size7_4_sram[1]:14 0.0045 +3 mux_tree_tapbuf_size7_4_sram[1]:15 mux_tree_tapbuf_size7_4_sram[1]:10 0.0006071429 +4 mux_tree_tapbuf_size7_4_sram[1]:14 mux_tree_tapbuf_size7_4_sram[1]:13 0.002348214 +5 mux_tree_tapbuf_size7_4_sram[1]:12 mux_tree_tapbuf_size7_4_sram[1]:11 0.001890625 +6 mux_tree_tapbuf_size7_4_sram[1]:13 mux_tree_tapbuf_size7_4_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size7_4_sram[1]:11 mux_right_track_24\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_4_sram[1]:9 mux_tree_tapbuf_size7_4_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size7_4_sram[1]:9 mux_tree_tapbuf_size7_4_sram[1]:4 0.004805804 +10 mux_tree_tapbuf_size7_4_sram[1]:8 mux_tree_tapbuf_size7_4_sram[1]:7 0.003866072 +11 mux_tree_tapbuf_size7_4_sram[1]:6 mux_tree_tapbuf_size7_4_sram[1]:5 0.001002232 +12 mux_tree_tapbuf_size7_4_sram[1]:7 mux_tree_tapbuf_size7_4_sram[1]:6 0.0045 +13 mux_tree_tapbuf_size7_4_sram[1]:5 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size7_4_sram[1]:16 mux_tree_tapbuf_size7_4_sram[1]:15 8.423914e-05 +15 mux_tree_tapbuf_size7_4_sram[1]:10 mux_tree_tapbuf_size7_4_sram[1]:9 0.001232143 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[2] 0.001764974 //LENGTH 13.765 LUMPCC 0.0001934692 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 50.905 75.140 +*I mux_top_track_0\/mux_l3_in_1_:S I *L 0.00357 *C 49.120 72.420 +*I mux_top_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 51.860 69.020 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 52.155 77.180 +*N mux_tree_tapbuf_size8_0_sram[2]:4 *C 52.155 77.180 +*N mux_tree_tapbuf_size8_0_sram[2]:5 *C 51.980 77.180 +*N mux_tree_tapbuf_size8_0_sram[2]:6 *C 51.980 77.135 +*N mux_tree_tapbuf_size8_0_sram[2]:7 *C 51.980 75.185 +*N mux_tree_tapbuf_size8_0_sram[2]:8 *C 51.935 75.140 +*N mux_tree_tapbuf_size8_0_sram[2]:9 *C 51.823 69.020 +*N mux_tree_tapbuf_size8_0_sram[2]:10 *C 51.105 69.020 +*N mux_tree_tapbuf_size8_0_sram[2]:11 *C 51.060 69.065 +*N mux_tree_tapbuf_size8_0_sram[2]:12 *C 49.157 72.420 +*N mux_tree_tapbuf_size8_0_sram[2]:13 *C 51.015 72.420 +*N mux_tree_tapbuf_size8_0_sram[2]:14 *C 51.060 72.420 +*N mux_tree_tapbuf_size8_0_sram[2]:15 *C 51.060 75.095 +*N mux_tree_tapbuf_size8_0_sram[2]:16 *C 51.105 75.140 +*N mux_tree_tapbuf_size8_0_sram[2]:17 *C 50.905 75.140 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:S 1e-06 +2 mux_top_track_0\/mux_l3_in_0_:S 1e-06 +3 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_0_sram[2]:4 4.954818e-05 +5 mux_tree_tapbuf_size8_0_sram[2]:5 5.258355e-05 +6 mux_tree_tapbuf_size8_0_sram[2]:6 0.0001283613 +7 mux_tree_tapbuf_size8_0_sram[2]:7 0.0001283613 +8 mux_tree_tapbuf_size8_0_sram[2]:8 3.605001e-05 +9 mux_tree_tapbuf_size8_0_sram[2]:9 6.712695e-05 +10 mux_tree_tapbuf_size8_0_sram[2]:10 6.712695e-05 +11 mux_tree_tapbuf_size8_0_sram[2]:11 0.0001882416 +12 mux_tree_tapbuf_size8_0_sram[2]:12 0.000140174 +13 mux_tree_tapbuf_size8_0_sram[2]:13 0.000140174 +14 mux_tree_tapbuf_size8_0_sram[2]:14 0.0003487559 +15 mux_tree_tapbuf_size8_0_sram[2]:15 0.0001272917 +16 mux_tree_tapbuf_size8_0_sram[2]:16 4.991203e-05 +17 mux_tree_tapbuf_size8_0_sram[2]:17 4.379679e-05 +18 mux_tree_tapbuf_size8_0_sram[2]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.534608e-06 +19 mux_tree_tapbuf_size8_0_sram[2]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.85539e-05 +20 mux_tree_tapbuf_size8_0_sram[2]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.080254e-05 +21 mux_tree_tapbuf_size8_0_sram[2]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.811581e-05 +22 mux_tree_tapbuf_size8_0_sram[2]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.85539e-05 +23 mux_tree_tapbuf_size8_0_sram[2]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.080254e-05 +24 mux_tree_tapbuf_size8_0_sram[2]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 1.372773e-05 +25 mux_tree_tapbuf_size8_0_sram[2]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.534608e-06 +26 mux_tree_tapbuf_size8_0_sram[2]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 2.811581e-05 +27 mux_tree_tapbuf_size8_0_sram[2]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 1.372773e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_0_sram[2]:17 0.152 +1 mux_tree_tapbuf_size8_0_sram[2]:9 mux_top_track_0\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[2]:10 mux_tree_tapbuf_size8_0_sram[2]:9 0.000640625 +3 mux_tree_tapbuf_size8_0_sram[2]:11 mux_tree_tapbuf_size8_0_sram[2]:10 0.0045 +4 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:15 0.0045 +5 mux_tree_tapbuf_size8_0_sram[2]:16 mux_tree_tapbuf_size8_0_sram[2]:8 0.0007410714 +6 mux_tree_tapbuf_size8_0_sram[2]:15 mux_tree_tapbuf_size8_0_sram[2]:14 0.002388393 +7 mux_tree_tapbuf_size8_0_sram[2]:8 mux_tree_tapbuf_size8_0_sram[2]:7 0.0045 +8 mux_tree_tapbuf_size8_0_sram[2]:7 mux_tree_tapbuf_size8_0_sram[2]:6 0.001741072 +9 mux_tree_tapbuf_size8_0_sram[2]:5 mux_tree_tapbuf_size8_0_sram[2]:4 9.51087e-05 +10 mux_tree_tapbuf_size8_0_sram[2]:6 mux_tree_tapbuf_size8_0_sram[2]:5 0.0045 +11 mux_tree_tapbuf_size8_0_sram[2]:4 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size8_0_sram[2]:17 mux_tree_tapbuf_size8_0_sram[2]:16 0.0001086957 +13 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:12 0.001658482 +14 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:13 0.0045 +15 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:11 0.002995536 +16 mux_tree_tapbuf_size8_0_sram[2]:12 mux_top_track_0\/mux_l3_in_1_:S 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001372618 //LENGTH 10.305 LUMPCC 0.0001468811 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_2_:X O *L 0 *C 6.725 71.400 +*I mux_left_track_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 13.440 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 13.402 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 11.960 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 11.960 69.360 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 7.405 69.360 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 7.360 69.405 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 7.360 71.355 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 7.315 71.400 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 6.763 71.400 + +*CAP +0 mux_left_track_3\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001148758 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001409498 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003024947 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002764207 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001313088 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001313088 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 6.318936e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.318936e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_right_in[4]:14 5.963643e-06 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_right_in[4]:9 5.67917e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[4]:7 1.068521e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[4]:8 1.068521e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_right_in[4]:14 5.67917e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[4]:9 5.963643e-06 + +*RES +0 mux_left_track_3\/mux_l2_in_2_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_3\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004066965 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001741072 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004933036 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001287947 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007618989 //LENGTH 4.980 LUMPCC 0.0001880068 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_1_:X O *L 0 *C 65.145 83.640 +*I mux_top_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 65.035 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 65.035 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 64.860 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 64.860 87.675 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 64.860 83.685 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 64.860 83.640 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 65.145 83.640 + +*CAP +0 mux_top_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.916907e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.353013e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001714919 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001714919 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.242091e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.378817e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:21 5.276905e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:23 5.276905e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.123434e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.123434e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0035625 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003299396 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_3_:X O *L 0 *C 104.595 26.180 +*I mux_right_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 102.410 26.180 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 102.448 26.180 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 104.558 26.180 + +*CAP +0 mux_right_track_16\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001639698 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001639698 + +*RES +0 mux_right_track_16\/mux_l1_in_3_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_16\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001883929 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006037158 //LENGTH 4.135 LUMPCC 0.0001022168 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_2_:X O *L 0 *C 35.245 34.680 +*I mux_left_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 38.545 34.340 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 38.545 34.340 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 38.640 34.680 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 35.282 34.680 + +*CAP +0 mux_left_track_17\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.72959e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002351523 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002070507 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_5_sram[0]:23 5.110841e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_5_sram[0]:24 5.110841e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_2_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002997768 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_17\/mux_l2_in_1_:A1 0.152 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000585875 //LENGTH 3.975 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_1_:X O *L 0 *C 41.225 44.200 +*I mux_left_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 44.910 44.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 44.873 44.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 41.263 44.200 + +*CAP +0 mux_left_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002919375 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002919375 + +*RES +0 mux_left_track_25\/mux_l2_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003223215 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001042644 //LENGTH 8.190 LUMPCC 0.0002007283 DR + +*CONN +*I mux_top_track_10\/mux_l1_in_0_:X O *L 0 *C 117.125 56.100 +*I mux_top_track_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 125.025 56.100 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 124.988 56.100 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 117.163 56.100 + +*CAP +0 mux_top_track_10\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_10\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004199577 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004199577 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size4_1_sram[1]:11 0.0001003641 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size4_1_sram[1]:12 0.0001003641 + +*RES +0 mux_top_track_10\/mux_l1_in_0_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_10\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.006986608 + +*END + +*D_NET mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004180968 //LENGTH 3.165 LUMPCC 9.94146e-05 DR + +*CONN +*I mux_top_track_18\/mux_l1_in_0_:X O *L 0 *C 64.115 44.540 +*I mux_top_track_18\/mux_l2_in_0_:A1 I *L 0.00198 *C 62.200 45.220 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 62.238 45.220 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 62.560 45.220 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 62.560 44.540 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 64.078 44.540 + +*CAP +0 mux_top_track_18\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_18\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.100262e-05 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.434153e-05 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001273385 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.39996e-05 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[0]:8 2.305648e-06 +7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:7 4.740165e-05 +8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:7 2.305648e-06 +9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[0]:8 4.740165e-05 + +*RES +0 mux_top_track_18\/mux_l1_in_0_:X mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_18\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001354911 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002879465 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0006071429 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00868215 //LENGTH 61.740 LUMPCC 0.002737189 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 81.245 37.060 +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.780 91.285 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 80.780 91.285 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 83.215 91.120 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 83.260 91.075 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 83.260 86.418 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 83.263 86.360 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 83.705 86.360 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 83.720 86.353 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 83.720 44.888 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 83.700 44.880 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 81.888 44.880 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 81.880 44.823 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 81.880 37.105 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 81.835 37.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:15 *C 81.282 37.060 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002021595 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001697278 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002770201 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002770201 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.751154e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.751154e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001712158 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001712158 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0002191746 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0002191746 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0004606499 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0004606499 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:14 5.902395e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:15 5.902395e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[17]:18 0.0008028259 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[17]:19 1.142859e-05 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[17]:19 0.0008028259 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[17]:20 1.142859e-05 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[17]:19 5.222138e-06 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[17]:20 5.222138e-06 +22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[19]:8 0.0005491177 +23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[19]:9 0.0005491177 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.0004933036 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.006890624 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.00341 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0002839583 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.00341 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.006496183 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.499219e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004158482 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002174107 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00125191 //LENGTH 10.035 LUMPCC 0.0002193252 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_1_:X O *L 0 *C 130.005 64.260 +*I mux_right_track_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 126.680 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 126.718 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 128.755 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 128.800 69.995 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 128.800 64.305 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 128.845 64.260 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 129.968 64.260 + +*CAP +0 mux_right_track_0\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001574732 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001574732 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002947482 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002947482 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.307118e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.307118e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 right_top_grid_pin_42_[0]:14 5.459169e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 right_top_grid_pin_42_[0]:13 5.459169e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size9_0_sram[1]:7 1.040143e-06 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size9_0_sram[1]:8 1.040143e-06 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:9 2.221897e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:14 3.181179e-05 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:10 2.221897e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:13 3.181179e-05 + +*RES +0 mux_right_track_0\/mux_l3_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001002232 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.005080357 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001819197 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_0\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005549293 //LENGTH 3.805 LUMPCC 0.0001274637 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_3_:X O *L 0 *C 108.275 71.400 +*I mux_right_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 109.790 70.040 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 109.775 70.040 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 109.503 70.040 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 109.480 70.085 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 109.480 71.355 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 109.435 71.400 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 108.312 71.400 + +*CAP +0 mux_right_track_4\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.077663e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.077663e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.245672e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.245672e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001094994 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001094994 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:19 3.972348e-07 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:21 2.711487e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:20 3.972348e-07 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:32 2.711487e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:33 3.621973e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size14_0_sram[0]:35 3.621973e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_3_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001480978 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001133929 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001002232 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001627761 //LENGTH 11.720 LUMPCC 0.0005742875 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_4_:X O *L 0 *C 11.325 58.820 +*I mux_left_track_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 14.260 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 14.260 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 14.260 50.705 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 14.260 58.775 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 14.215 58.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 11.363 58.820 + +*CAP +0 mux_left_track_5\/mux_l1_in_4_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_2_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.374997e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0004326224 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0004326224 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.62393e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.62393e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 optlc_net_123:10 1.024129e-08 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 optlc_net_123:18 1.709964e-07 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 optlc_net_123:19 2.460233e-06 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 optlc_net_123:11 2.94595e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 optlc_net_123:12 8.88314e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_123:9 1.024129e-08 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_123:15 2.460233e-06 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_123:19 1.709964e-07 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_123:12 2.94595e-05 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_123:13 8.88314e-05 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.914238e-05 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.914238e-05 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 ropt_net_129:6 9.706902e-05 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 ropt_net_129:5 9.706902e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_4_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_5\/mux_l2_in_2_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.007205357 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.002546875 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007606606 //LENGTH 5.830 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_1_:X O *L 0 *C 39.385 68.680 +*I mux_left_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 37.550 66.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 37.550 66.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 37.720 66.980 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 37.750 66.950 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 37.765 66.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 38.180 66.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 38.180 68.635 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 38.225 68.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 39.348 68.680 + +*CAP +0 mux_left_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.081157e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.409669e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.361058e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.473909e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001657638 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001346353 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001075017 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001075017 + +*RES +0 mux_left_track_1\/mux_l2_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0006071429 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00178125 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.001002232 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00019375 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003705357 + +*END + +*D_NET ropt_net_145 0.002239023 //LENGTH 16.830 LUMPCC 0.000657165 DR + +*CONN +*I FTB_11__10:X O *L 0 *C 10.580 36.380 +*I ropt_mt_inst_768:A I *L 0.001766 *C 7.820 42.160 +*N ropt_net_145:2 *C 7.783 42.160 +*N ropt_net_145:3 *C 4.185 42.160 +*N ropt_net_145:4 *C 4.140 42.115 +*N ropt_net_145:5 *C 4.140 36.425 +*N ropt_net_145:6 *C 4.185 36.380 +*N ropt_net_145:7 *C 10.543 36.380 + +*CAP +0 FTB_11__10:X 1e-06 +1 ropt_mt_inst_768:A 1e-06 +2 ropt_net_145:2 0.0001530747 +3 ropt_net_145:3 0.0001530747 +4 ropt_net_145:4 0.0002482773 +5 ropt_net_145:5 0.0002482773 +6 ropt_net_145:6 0.0003885771 +7 ropt_net_145:7 0.0003885771 +8 ropt_net_145:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.977945e-05 +9 ropt_net_145:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.977945e-05 +10 ropt_net_145:2 ropt_net_160:4 0.000145922 +11 ropt_net_145:3 ropt_net_160:3 0.000145922 +12 ropt_net_145:6 chanx_left_out[9]:5 0.000112881 +13 ropt_net_145:7 chanx_left_out[9]:6 0.000112881 + +*RES +0 FTB_11__10:X ropt_net_145:7 0.152 +1 ropt_net_145:2 ropt_mt_inst_768:A 0.152 +2 ropt_net_145:3 ropt_net_145:2 0.003212054 +3 ropt_net_145:4 ropt_net_145:3 0.0045 +4 ropt_net_145:6 ropt_net_145:5 0.0045 +5 ropt_net_145:5 ropt_net_145:4 0.005080357 +6 ropt_net_145:7 ropt_net_145:6 0.005676339 + +*END + +*D_NET ropt_net_166 0.001164124 //LENGTH 7.085 LUMPCC 0.0005113477 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 68.235 96.900 +*I ropt_mt_inst_792:A I *L 0.001767 *C 64.400 99.280 +*N ropt_net_166:2 *C 64.400 99.280 +*N ropt_net_166:3 *C 64.400 98.940 +*N ropt_net_166:4 *C 68.035 98.940 +*N ropt_net_166:5 *C 68.080 98.895 +*N ropt_net_166:6 *C 68.080 96.945 +*N ropt_net_166:7 *C 68.080 96.900 +*N ropt_net_166:8 *C 68.235 96.900 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_166:2 5.925266e-05 +3 ropt_net_166:3 0.0001117038 +4 ropt_net_166:4 8.271955e-05 +5 ropt_net_166:5 0.0001342533 +6 ropt_net_166:6 0.0001342533 +7 ropt_net_166:7 6.434281e-05 +8 ropt_net_166:8 6.425048e-05 +9 ropt_net_166:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.000112618 +10 ropt_net_166:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000112618 +11 ropt_net_166:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001430558 +12 ropt_net_166:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001430558 + +*RES +0 ropt_mt_inst_763:X ropt_net_166:8 0.152 +1 ropt_net_166:8 ropt_net_166:7 8.423914e-05 +2 ropt_net_166:7 ropt_net_166:6 0.0045 +3 ropt_net_166:6 ropt_net_166:5 0.001741071 +4 ropt_net_166:4 ropt_net_166:3 0.003245536 +5 ropt_net_166:5 ropt_net_166:4 0.0045 +6 ropt_net_166:2 ropt_mt_inst_792:A 0.152 +7 ropt_net_166:3 ropt_net_166:2 0.0003035715 + +*END + +*D_NET ropt_net_160 0.001517697 //LENGTH 10.535 LUMPCC 0.0007515805 DR + +*CONN +*I ropt_mt_inst_768:X O *L 0 *C 11.695 42.500 +*I ropt_mt_inst_786:A I *L 0.001767 *C 3.220 42.160 +*N ropt_net_160:2 *C 3.220 42.160 +*N ropt_net_160:3 *C 3.220 41.820 +*N ropt_net_160:4 *C 9.155 41.820 +*N ropt_net_160:5 *C 9.200 41.865 +*N ropt_net_160:6 *C 9.200 42.455 +*N ropt_net_160:7 *C 9.245 42.500 +*N ropt_net_160:8 *C 11.658 42.500 + +*CAP +0 ropt_mt_inst_768:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_160:2 5.871987e-05 +3 ropt_net_160:3 0.0002649583 +4 ropt_net_160:4 0.0002362567 +5 ropt_net_160:5 4.340465e-05 +6 ropt_net_160:6 4.340465e-05 +7 ropt_net_160:7 5.86863e-05 +8 ropt_net_160:8 5.86863e-05 +9 ropt_net_160:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 4.160959e-05 +10 ropt_net_160:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 4.160959e-05 +11 ropt_net_160:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 8.180304e-06 +12 ropt_net_160:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 8.180304e-06 +13 ropt_net_160:4 ropt_net_145:2 0.000145922 +14 ropt_net_160:3 ropt_net_145:3 0.000145922 +15 ropt_net_160:6 ropt_net_143:3 6.513091e-06 +16 ropt_net_160:4 ropt_net_143:6 6.236818e-05 +17 ropt_net_160:5 ropt_net_143:4 6.513091e-06 +18 ropt_net_160:3 ropt_net_143:5 6.236818e-05 +19 ropt_net_160:8 ropt_net_141:11 0.0001045996 +20 ropt_net_160:7 ropt_net_141:10 0.0001045996 +21 ropt_net_160:4 ropt_net_141:11 6.597456e-06 +22 ropt_net_160:3 ropt_net_141:10 6.597456e-06 + +*RES +0 ropt_mt_inst_768:X ropt_net_160:8 0.152 +1 ropt_net_160:8 ropt_net_160:7 0.002154018 +2 ropt_net_160:7 ropt_net_160:6 0.0045 +3 ropt_net_160:6 ropt_net_160:5 0.0005267857 +4 ropt_net_160:4 ropt_net_160:3 0.005299107 +5 ropt_net_160:5 ropt_net_160:4 0.0045 +6 ropt_net_160:2 ropt_mt_inst_786:A 0.152 +7 ropt_net_160:3 ropt_net_160:2 0.0003035715 + +*END + +*D_NET ropt_net_133 0.0015823 //LENGTH 13.690 LUMPCC 0.0003790135 DR + +*CONN +*I BUFT_P_107:X O *L 0 *C 7.820 25.840 +*I ropt_mt_inst_756:A I *L 0.001766 *C 3.220 17.680 +*N ropt_net_133:2 *C 3.258 17.680 +*N ropt_net_133:3 *C 4.095 17.680 +*N ropt_net_133:4 *C 4.140 17.725 +*N ropt_net_133:5 *C 4.140 25.795 +*N ropt_net_133:6 *C 4.185 25.840 +*N ropt_net_133:7 *C 7.783 25.840 + +*CAP +0 BUFT_P_107:X 1e-06 +1 ropt_mt_inst_756:A 1e-06 +2 ropt_net_133:2 6.204233e-05 +3 ropt_net_133:3 6.204233e-05 +4 ropt_net_133:4 0.0003567485 +5 ropt_net_133:5 0.0003567485 +6 ropt_net_133:6 0.0001818526 +7 ropt_net_133:7 0.0001818526 +8 ropt_net_133:4 chanx_right_in[5]:7 6.501078e-05 +9 ropt_net_133:5 chanx_right_in[5]:6 6.501078e-05 +10 ropt_net_133:4 chanx_right_in[9]:6 6.501077e-05 +11 ropt_net_133:6 chanx_right_in[9]:8 5.948518e-05 +12 ropt_net_133:5 chanx_right_in[9]:7 6.501077e-05 +13 ropt_net_133:7 chanx_right_in[9]:9 5.948518e-05 + +*RES +0 BUFT_P_107:X ropt_net_133:7 0.152 +1 ropt_net_133:2 ropt_mt_inst_756:A 0.152 +2 ropt_net_133:3 ropt_net_133:2 0.0007477679 +3 ropt_net_133:4 ropt_net_133:3 0.0045 +4 ropt_net_133:6 ropt_net_133:5 0.0045 +5 ropt_net_133:5 ropt_net_133:4 0.007205357 +6 ropt_net_133:7 ropt_net_133:6 0.003212054 + +*END + +*D_NET chanx_right_in[4] 0.02846182 //LENGTH 204.410 LUMPCC 0.008810664 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 140.375 13.600 +*I mux_top_track_2\/mux_l1_in_2_:A0 I *L 0.001631 *C 66.530 71.400 +*I mux_left_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 27.890 71.400 +*I FTB_3__2:A I *L 0.001767 *C 11.500 63.920 +*N chanx_right_in[4]:4 *C 11.500 63.920 +*N chanx_right_in[4]:5 *C 11.500 64.260 +*N chanx_right_in[4]:6 *C 8.325 64.260 +*N chanx_right_in[4]:7 *C 8.280 64.305 +*N chanx_right_in[4]:8 *C 8.280 69.995 +*N chanx_right_in[4]:9 *C 8.325 70.040 +*N chanx_right_in[4]:10 *C 27.890 71.400 +*N chanx_right_in[4]:11 *C 27.600 71.400 +*N chanx_right_in[4]:12 *C 27.600 71.355 +*N chanx_right_in[4]:13 *C 27.600 70.085 +*N chanx_right_in[4]:14 *C 27.600 70.040 +*N chanx_right_in[4]:15 *C 66.530 71.400 +*N chanx_right_in[4]:16 *C 66.240 71.400 +*N chanx_right_in[4]:17 *C 66.240 71.355 +*N chanx_right_in[4]:18 *C 66.240 70.085 +*N chanx_right_in[4]:19 *C 66.240 70.010 +*N chanx_right_in[4]:20 *C 66.240 69.020 +*N chanx_right_in[4]:21 *C 74.015 69.020 +*N chanx_right_in[4]:22 *C 74.060 68.975 +*N chanx_right_in[4]:23 *C 74.060 64.095 +*N chanx_right_in[4]:24 *C 74.060 14.338 +*N chanx_right_in[4]:25 *C 74.068 14.280 +*N chanx_right_in[4]:26 *C 123.895 14.280 +*N chanx_right_in[4]:27 *C 136.160 14.280 +*N chanx_right_in[4]:28 *C 136.160 13.600 + +*CAP +0 chanx_right_in[4] 0.0002111844 +1 mux_top_track_2\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_3\/mux_l2_in_0_:A0 1e-06 +3 FTB_3__2:A 1e-06 +4 chanx_right_in[4]:4 6.364999e-05 +5 chanx_right_in[4]:5 0.0001636909 +6 chanx_right_in[4]:6 0.0001327878 +7 chanx_right_in[4]:7 0.0003226971 +8 chanx_right_in[4]:8 0.0003226971 +9 chanx_right_in[4]:9 0.001189252 +10 chanx_right_in[4]:10 5.671911e-05 +11 chanx_right_in[4]:11 6.113962e-05 +12 chanx_right_in[4]:12 9.682296e-05 +13 chanx_right_in[4]:13 9.682296e-05 +14 chanx_right_in[4]:14 0.003939957 +15 chanx_right_in[4]:15 5.871098e-05 +16 chanx_right_in[4]:16 5.766456e-05 +17 chanx_right_in[4]:17 9.17392e-05 +18 chanx_right_in[4]:18 9.17392e-05 +19 chanx_right_in[4]:19 0.002785792 +20 chanx_right_in[4]:20 0.0005515464 +21 chanx_right_in[4]:21 0.0004838766 +22 chanx_right_in[4]:22 0.0003025167 +23 chanx_right_in[4]:23 0.002627479 +24 chanx_right_in[4]:24 0.002324963 +25 chanx_right_in[4]:25 0.001345081 +26 chanx_right_in[4]:26 0.001640202 +27 chanx_right_in[4]:27 0.00035668 +28 chanx_right_in[4]:28 0.0002727422 +29 chanx_right_in[4] chanx_right_in[2] 4.777634e-05 +30 chanx_right_in[4]:25 chanx_right_in[2]:27 0.0004465627 +31 chanx_right_in[4]:25 chanx_right_in[2]:28 0.0004150383 +32 chanx_right_in[4]:27 chanx_right_in[2] 0.0001920524 +33 chanx_right_in[4]:28 chanx_right_in[2]:28 4.777634e-05 +34 chanx_right_in[4]:26 chanx_right_in[2] 0.0004150383 +35 chanx_right_in[4]:26 chanx_right_in[2]:28 0.0006386151 +36 chanx_right_in[4] chanx_right_in[8] 8.138725e-05 +37 chanx_right_in[4]:25 chanx_right_in[8]:23 0.001504586 +38 chanx_right_in[4]:27 chanx_right_in[8] 0.0007133903 +39 chanx_right_in[4]:28 chanx_right_in[8]:23 8.138725e-05 +40 chanx_right_in[4]:26 chanx_right_in[8] 0.001504586 +41 chanx_right_in[4]:26 chanx_right_in[8]:23 0.0007133903 +42 chanx_right_in[4]:24 mux_tree_tapbuf_size3_4_sram[1]:7 0.0001526287 +43 chanx_right_in[4]:24 mux_tree_tapbuf_size3_4_sram[1]:8 0.0001210642 +44 chanx_right_in[4]:23 mux_tree_tapbuf_size3_4_sram[1]:8 0.0001526287 +45 chanx_right_in[4]:23 mux_tree_tapbuf_size3_4_sram[1]:4 0.0001210642 +46 chanx_right_in[4]:24 mux_tree_tapbuf_size3_6_sram[0]:10 0.0001523437 +47 chanx_right_in[4]:24 mux_tree_tapbuf_size3_6_sram[0]:13 2.344489e-06 +48 chanx_right_in[4]:24 mux_tree_tapbuf_size3_6_sram[0]:12 5.617358e-05 +49 chanx_right_in[4]:23 mux_tree_tapbuf_size3_6_sram[0]:7 5.617358e-05 +50 chanx_right_in[4]:23 mux_tree_tapbuf_size3_6_sram[0]:11 0.0001523437 +51 chanx_right_in[4]:23 mux_tree_tapbuf_size3_6_sram[0]:12 2.344489e-06 +52 chanx_right_in[4]:24 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 6.522876e-05 +53 chanx_right_in[4]:23 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 6.522876e-05 +54 chanx_right_in[4]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.940535e-05 +55 chanx_right_in[4]:19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.940535e-05 +56 chanx_right_in[4]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.285091e-05 +57 chanx_right_in[4]:19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.285091e-05 +58 chanx_right_in[4]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.54047e-05 +59 chanx_right_in[4]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.54047e-05 +60 chanx_right_in[4]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.67917e-05 +61 chanx_right_in[4]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.963643e-06 +62 chanx_right_in[4]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.068521e-05 +63 chanx_right_in[4]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.068521e-05 +64 chanx_right_in[4]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.963643e-06 +65 chanx_right_in[4]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.67917e-05 +66 chanx_right_in[4]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.292358e-07 +67 chanx_right_in[4]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000124895 +68 chanx_right_in[4]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.292358e-07 +69 chanx_right_in[4]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.000124895 +70 chanx_right_in[4]:24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.822933e-05 +71 chanx_right_in[4]:23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.822933e-05 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:28 0.00066035 +1 chanx_right_in[4]:9 chanx_right_in[4]:8 0.0045 +2 chanx_right_in[4]:8 chanx_right_in[4]:7 0.005080357 +3 chanx_right_in[4]:6 chanx_right_in[4]:5 0.002834822 +4 chanx_right_in[4]:7 chanx_right_in[4]:6 0.0045 +5 chanx_right_in[4]:4 FTB_3__2:A 0.152 +6 chanx_right_in[4]:14 chanx_right_in[4]:13 0.0045 +7 chanx_right_in[4]:14 chanx_right_in[4]:9 0.01720982 +8 chanx_right_in[4]:13 chanx_right_in[4]:12 0.001133929 +9 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0001576087 +10 chanx_right_in[4]:12 chanx_right_in[4]:11 0.0045 +11 chanx_right_in[4]:10 mux_left_track_3\/mux_l2_in_0_:A0 0.152 +12 chanx_right_in[4]:19 chanx_right_in[4]:18 0.0045 +13 chanx_right_in[4]:19 chanx_right_in[4]:14 0.0345 +14 chanx_right_in[4]:18 chanx_right_in[4]:17 0.001133929 +15 chanx_right_in[4]:16 chanx_right_in[4]:15 0.0001576087 +16 chanx_right_in[4]:17 chanx_right_in[4]:16 0.0045 +17 chanx_right_in[4]:15 mux_top_track_2\/mux_l1_in_2_:A0 0.152 +18 chanx_right_in[4]:21 chanx_right_in[4]:20 0.006941964 +19 chanx_right_in[4]:22 chanx_right_in[4]:21 0.0045 +20 chanx_right_in[4]:24 chanx_right_in[4]:23 0.04442634 +21 chanx_right_in[4]:25 chanx_right_in[4]:24 0.00341 +22 chanx_right_in[4]:5 chanx_right_in[4]:4 0.0003035715 +23 chanx_right_in[4]:20 chanx_right_in[4]:19 0.0008839285 +24 chanx_right_in[4]:27 chanx_right_in[4]:26 0.001921516 +25 chanx_right_in[4]:28 chanx_right_in[4]:27 0.0001065333 +26 chanx_right_in[4]:23 chanx_right_in[4]:22 0.004357143 +27 chanx_right_in[4]:26 chanx_right_in[4]:25 0.007806308 + +*END + +*D_NET chanx_left_in[8] 0.01991466 //LENGTH 148.295 LUMPCC 0.002791055 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 32.640 +*I mux_right_track_16\/mux_l1_in_2_:A0 I *L 0.001631 *C 100.915 27.880 +*I BUFT_P_96:A I *L 0.001776 *C 131.560 36.720 +*I mux_top_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 104.520 39.780 +*N chanx_left_in[8]:4 *C 104.420 39.780 +*N chanx_left_in[8]:5 *C 104.420 39.735 +*N chanx_left_in[8]:6 *C 131.523 36.720 +*N chanx_left_in[8]:7 *C 127.925 36.720 +*N chanx_left_in[8]:8 *C 127.880 36.720 +*N chanx_left_in[8]:9 *C 127.873 36.720 +*N chanx_left_in[8]:10 *C 104.428 36.720 +*N chanx_left_in[8]:11 *C 104.420 36.720 +*N chanx_left_in[8]:12 *C 104.420 35.360 +*N chanx_left_in[8]:13 *C 103.960 35.360 +*N chanx_left_in[8]:14 *C 103.960 33.320 +*N chanx_left_in[8]:15 *C 100.953 27.880 +*N chanx_left_in[8]:16 *C 103.455 27.880 +*N chanx_left_in[8]:17 *C 103.500 27.925 +*N chanx_left_in[8]:18 *C 103.500 33.320 +*N chanx_left_in[8]:19 *C 103.455 33.320 +*N chanx_left_in[8]:20 *C 55.360 33.320 +*N chanx_left_in[8]:21 *C 5.565 33.320 +*N chanx_left_in[8]:22 *C 5.520 33.275 +*N chanx_left_in[8]:23 *C 5.520 32.698 +*N chanx_left_in[8]:24 *C 5.513 32.640 + +*CAP +0 chanx_left_in[8] 0.0002824225 +1 mux_right_track_16\/mux_l1_in_2_:A0 1e-06 +2 BUFT_P_96:A 1e-06 +3 mux_top_track_8\/mux_l2_in_1_:A1 1e-06 +4 chanx_left_in[8]:4 3.160256e-05 +5 chanx_left_in[8]:5 0.0001655864 +6 chanx_left_in[8]:6 0.0001975912 +7 chanx_left_in[8]:7 0.0001975912 +8 chanx_left_in[8]:8 3.180734e-05 +9 chanx_left_in[8]:9 0.001195998 +10 chanx_left_in[8]:10 0.001195998 +11 chanx_left_in[8]:11 0.0002773992 +12 chanx_left_in[8]:12 7.92194e-05 +13 chanx_left_in[8]:13 0.0001245443 +14 chanx_left_in[8]:14 0.0001365708 +15 chanx_left_in[8]:15 0.0001991521 +16 chanx_left_in[8]:16 0.0001991521 +17 chanx_left_in[8]:17 0.0002995423 +18 chanx_left_in[8]:18 0.0003147641 +19 chanx_left_in[8]:19 0.002842677 +20 chanx_left_in[8]:20 0.005891287 +21 chanx_left_in[8]:21 0.00304861 +22 chanx_left_in[8]:22 6.333436e-05 +23 chanx_left_in[8]:23 6.333436e-05 +24 chanx_left_in[8]:24 0.0002824225 +25 chanx_left_in[8]:10 chanx_right_in[17]:24 0.0002035983 +26 chanx_left_in[8]:9 chanx_right_in[17]:25 0.0002035983 +27 chanx_left_in[8]:19 chanx_right_in[17]:21 1.289695e-05 +28 chanx_left_in[8]:19 chanx_right_in[17]:24 5.166171e-06 +29 chanx_left_in[8]:19 chanx_right_in[17]:25 5.100426e-06 +30 chanx_left_in[8]:21 chanx_right_in[17]:17 2.63093e-05 +31 chanx_left_in[8]:20 chanx_right_in[17]:18 2.63093e-05 +32 chanx_left_in[8]:20 chanx_right_in[17]:19 5.166171e-06 +33 chanx_left_in[8]:20 chanx_right_in[17]:20 1.289695e-05 +34 chanx_left_in[8]:20 chanx_right_in[17]:24 5.100426e-06 +35 chanx_left_in[8]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001206877 +36 chanx_left_in[8]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001206877 +37 chanx_left_in[8]:21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.611447e-05 +38 chanx_left_in[8]:20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.611447e-05 +39 chanx_left_in[8]:21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001532015 +40 chanx_left_in[8]:20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001532015 +41 chanx_left_in[8]:19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.096853e-05 +42 chanx_left_in[8]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.096853e-05 +43 chanx_left_in[8]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.40284e-06 +44 chanx_left_in[8]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.40284e-06 +45 chanx_left_in[8]:19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.645884e-05 +46 chanx_left_in[8]:18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.670171e-05 +47 chanx_left_in[8]:14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.670171e-05 +48 chanx_left_in[8]:13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 2.610156e-05 +49 chanx_left_in[8]:12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 2.610156e-05 +50 chanx_left_in[8]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.645884e-05 +51 chanx_left_in[8]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001390061 +52 chanx_left_in[8]:20 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001390061 +53 chanx_left_in[8]:19 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.977527e-05 +54 chanx_left_in[8]:20 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.977527e-05 +55 chanx_left_in[8]:19 optlc_net_126:15 2.866454e-05 +56 chanx_left_in[8]:19 optlc_net_126:20 0.0003244225 +57 chanx_left_in[8]:20 optlc_net_126:21 0.0003244225 +58 chanx_left_in[8]:20 optlc_net_126:20 2.866454e-05 +59 chanx_left_in[8]:21 ropt_net_149:2 5.395065e-05 +60 chanx_left_in[8]:20 ropt_net_149:3 5.395065e-05 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:24 0.0006709249 +1 chanx_left_in[8]:11 chanx_left_in[8]:10 0.00341 +2 chanx_left_in[8]:11 chanx_left_in[8]:5 0.002691964 +3 chanx_left_in[8]:10 chanx_left_in[8]:9 0.00367305 +4 chanx_left_in[8]:8 chanx_left_in[8]:7 0.0045 +5 chanx_left_in[8]:9 chanx_left_in[8]:8 0.00341 +6 chanx_left_in[8]:7 chanx_left_in[8]:6 0.003212053 +7 chanx_left_in[8]:6 BUFT_P_96:A 0.152 +8 chanx_left_in[8]:4 mux_top_track_8\/mux_l2_in_1_:A1 0.152 +9 chanx_left_in[8]:5 chanx_left_in[8]:4 0.0045 +10 chanx_left_in[8]:16 chanx_left_in[8]:15 0.002234375 +11 chanx_left_in[8]:17 chanx_left_in[8]:16 0.0045 +12 chanx_left_in[8]:15 mux_right_track_16\/mux_l1_in_2_:A0 0.152 +13 chanx_left_in[8]:19 chanx_left_in[8]:18 0.0045 +14 chanx_left_in[8]:18 chanx_left_in[8]:17 0.004816964 +15 chanx_left_in[8]:18 chanx_left_in[8]:14 0.0004107143 +16 chanx_left_in[8]:21 chanx_left_in[8]:20 0.04445982 +17 chanx_left_in[8]:22 chanx_left_in[8]:21 0.0045 +18 chanx_left_in[8]:23 chanx_left_in[8]:22 0.000515625 +19 chanx_left_in[8]:24 chanx_left_in[8]:23 0.00341 +20 chanx_left_in[8]:14 chanx_left_in[8]:13 0.001821428 +21 chanx_left_in[8]:13 chanx_left_in[8]:12 0.0004107143 +22 chanx_left_in[8]:12 chanx_left_in[8]:11 0.001214286 +23 chanx_left_in[8]:20 chanx_left_in[8]:19 0.04294197 + +*END + +*D_NET chanx_left_in[16] 0.02571835 //LENGTH 181.690 LUMPCC 0.01062518 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 28.560 +*I mux_right_track_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 127.325 47.260 +*I ropt_mt_inst_759:A I *L 0.001767 *C 132.020 69.360 +*I mux_top_track_20\/mux_l1_in_1_:A1 I *L 0.00198 *C 69.560 39.780 +*N chanx_left_in[16]:4 *C 69.560 39.780 +*N chanx_left_in[16]:5 *C 132.058 69.360 +*N chanx_left_in[16]:6 *C 132.435 69.360 +*N chanx_left_in[16]:7 *C 132.480 69.315 +*N chanx_left_in[16]:8 *C 132.480 63.978 +*N chanx_left_in[16]:9 *C 132.488 63.920 +*N chanx_left_in[16]:10 *C 134.312 63.920 +*N chanx_left_in[16]:11 *C 134.320 63.863 +*N chanx_left_in[16]:12 *C 134.320 53.085 +*N chanx_left_in[16]:13 *C 134.275 53.040 +*N chanx_left_in[16]:14 *C 132.940 53.040 +*N chanx_left_in[16]:15 *C 132.905 52.700 +*N chanx_left_in[16]:16 *C 129.305 52.700 +*N chanx_left_in[16]:17 *C 129.260 52.655 +*N chanx_left_in[16]:18 *C 129.260 47.305 +*N chanx_left_in[16]:19 *C 129.215 47.260 +*N chanx_left_in[16]:20 *C 127.420 47.260 +*N chanx_left_in[16]:21 *C 127.420 46.920 +*N chanx_left_in[16]:22 *C 122.865 46.920 +*N chanx_left_in[16]:23 *C 122.820 46.875 +*N chanx_left_in[16]:24 *C 122.820 40.178 +*N chanx_left_in[16]:25 *C 122.812 40.120 +*N chanx_left_in[16]:26 *C 73.148 40.120 +*N chanx_left_in[16]:27 *C 73.140 40.062 +*N chanx_left_in[16]:28 *C 73.140 39.485 +*N chanx_left_in[16]:29 *C 73.095 39.440 +*N chanx_left_in[16]:30 *C 69.460 39.440 +*N chanx_left_in[16]:31 *C 67.665 39.440 +*N chanx_left_in[16]:32 *C 67.620 39.395 +*N chanx_left_in[16]:33 *C 67.620 28.617 +*N chanx_left_in[16]:34 *C 67.612 28.560 +*N chanx_left_in[16]:35 *C 51.230 28.560 + +*CAP +0 chanx_left_in[16] 0.001657326 +1 mux_right_track_8\/mux_l2_in_3_:A1 1e-06 +2 ropt_mt_inst_759:A 1e-06 +3 mux_top_track_20\/mux_l1_in_1_:A1 1e-06 +4 chanx_left_in[16]:4 5.889934e-05 +5 chanx_left_in[16]:5 6.282431e-05 +6 chanx_left_in[16]:6 6.282431e-05 +7 chanx_left_in[16]:7 0.000323773 +8 chanx_left_in[16]:8 0.000323773 +9 chanx_left_in[16]:9 0.0001465248 +10 chanx_left_in[16]:10 0.0001465248 +11 chanx_left_in[16]:11 0.0005295869 +12 chanx_left_in[16]:12 0.0005295869 +13 chanx_left_in[16]:13 7.759575e-05 +14 chanx_left_in[16]:14 0.0001024757 +15 chanx_left_in[16]:15 0.000210439 +16 chanx_left_in[16]:16 0.0001855591 +17 chanx_left_in[16]:17 0.0003066121 +18 chanx_left_in[16]:18 0.0003066121 +19 chanx_left_in[16]:19 0.0001564474 +20 chanx_left_in[16]:20 0.0001843426 +21 chanx_left_in[16]:21 0.0003560823 +22 chanx_left_in[16]:22 0.0003281871 +23 chanx_left_in[16]:23 0.0003709651 +24 chanx_left_in[16]:24 0.0003709651 +25 chanx_left_in[16]:25 0.001639183 +26 chanx_left_in[16]:26 0.001639183 +27 chanx_left_in[16]:27 5.593092e-05 +28 chanx_left_in[16]:28 5.593092e-05 +29 chanx_left_in[16]:29 0.0002442955 +30 chanx_left_in[16]:30 0.000421726 +31 chanx_left_in[16]:31 0.0001485295 +32 chanx_left_in[16]:32 0.0005392108 +33 chanx_left_in[16]:33 0.0005392108 +34 chanx_left_in[16]:34 0.0006758578 +35 chanx_left_in[16]:35 0.002333184 +36 chanx_left_in[16] chanx_right_in[8]:11 0.0006219519 +37 chanx_left_in[16]:34 chanx_right_in[8]:12 5.689192e-05 +38 chanx_left_in[16]:35 chanx_right_in[8]:11 5.689192e-05 +39 chanx_left_in[16]:35 chanx_right_in[8]:12 0.0006219519 +40 chanx_left_in[16]:25 chanx_left_in[13]:14 0.0004572932 +41 chanx_left_in[16]:26 chanx_left_in[13]:15 0.0004572932 +42 chanx_left_in[16]:25 chanx_left_in[14]:8 0.0002692774 +43 chanx_left_in[16]:25 chanx_left_in[14]:14 0.0008457302 +44 chanx_left_in[16]:26 chanx_left_in[14]:14 0.0002692774 +45 chanx_left_in[16]:26 chanx_left_in[14]:15 0.0008457302 +46 chanx_left_in[16]:25 prog_clk[0]:287 0.00039539 +47 chanx_left_in[16]:25 prog_clk[0]:236 8.454123e-06 +48 chanx_left_in[16]:26 prog_clk[0]:288 0.00039539 +49 chanx_left_in[16]:26 prog_clk[0]:235 8.454123e-06 +50 chanx_left_in[16]:32 prog_clk[0]:369 3.68786e-05 +51 chanx_left_in[16]:33 prog_clk[0]:370 3.68786e-05 +52 chanx_left_in[16]:34 chany_top_in[17]:8 0.0005629295 +53 chanx_left_in[16]:35 chany_top_in[17]:7 0.0005629295 +54 chanx_left_in[16]:25 chanx_right_in[15]:7 0.0003930653 +55 chanx_left_in[16]:26 chanx_right_in[15]:6 0.0003930653 +56 chanx_left_in[16] chanx_left_out[0]:2 0.0002755075 +57 chanx_left_in[16]:35 chanx_left_out[0]:3 0.0002755075 +58 chanx_left_in[16]:29 mux_tree_tapbuf_size3_4_sram[0]:6 8.869823e-06 +59 chanx_left_in[16]:31 mux_tree_tapbuf_size3_4_sram[0]:7 1.838305e-05 +60 chanx_left_in[16]:32 mux_tree_tapbuf_size3_4_sram[0]:12 8.427427e-05 +61 chanx_left_in[16]:32 mux_tree_tapbuf_size3_4_sram[0]:9 7.024932e-05 +62 chanx_left_in[16]:33 mux_tree_tapbuf_size3_4_sram[0]:13 8.427427e-05 +63 chanx_left_in[16]:33 mux_tree_tapbuf_size3_4_sram[0]:12 7.024932e-05 +64 chanx_left_in[16]:30 mux_tree_tapbuf_size3_4_sram[0]:7 8.869823e-06 +65 chanx_left_in[16]:30 mux_tree_tapbuf_size3_4_sram[0]:6 1.838305e-05 +66 chanx_left_in[16]:34 mux_tree_tapbuf_size8_0_sram[0]:16 0.0002909279 +67 chanx_left_in[16]:35 mux_tree_tapbuf_size8_0_sram[0]:15 0.0002909279 +68 chanx_left_in[16]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.557683e-05 +69 chanx_left_in[16]:20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.557683e-05 +70 chanx_left_in[16] mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005889847 +71 chanx_left_in[16] mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.124378e-06 +72 chanx_left_in[16]:35 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0005889847 +73 chanx_left_in[16]:35 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.124378e-06 +74 chanx_left_in[16]:27 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.998252e-06 +75 chanx_left_in[16]:29 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.047668e-05 +76 chanx_left_in[16]:28 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.998252e-06 +77 chanx_left_in[16]:30 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.047668e-05 +78 chanx_left_in[16]:12 ropt_net_154:5 9.151126e-05 +79 chanx_left_in[16]:11 ropt_net_154:4 9.151126e-05 +80 chanx_left_in[16]:8 ropt_net_154:5 4.439286e-06 +81 chanx_left_in[16]:7 ropt_net_154:4 4.439286e-06 +82 chanx_left_in[16]:16 ropt_net_137:5 2.853094e-05 +83 chanx_left_in[16]:16 ropt_net_137:4 3.739543e-05 +84 chanx_left_in[16]:13 ropt_net_137:3 6.20467e-05 +85 chanx_left_in[16]:15 ropt_net_137:6 2.853094e-05 +86 chanx_left_in[16]:15 ropt_net_137:2 4.307264e-07 +87 chanx_left_in[16]:15 ropt_net_137:3 3.739543e-05 +88 chanx_left_in[16]:14 ropt_net_137:4 6.20467e-05 +89 chanx_left_in[16]:14 ropt_net_137:3 4.307264e-07 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:35 0.007833333 +1 chanx_left_in[16]:22 chanx_left_in[16]:21 0.004066964 +2 chanx_left_in[16]:23 chanx_left_in[16]:22 0.0045 +3 chanx_left_in[16]:24 chanx_left_in[16]:23 0.005979911 +4 chanx_left_in[16]:25 chanx_left_in[16]:24 0.00341 +5 chanx_left_in[16]:27 chanx_left_in[16]:26 0.00341 +6 chanx_left_in[16]:26 chanx_left_in[16]:25 0.007780849 +7 chanx_left_in[16]:29 chanx_left_in[16]:28 0.0045 +8 chanx_left_in[16]:28 chanx_left_in[16]:27 0.000515625 +9 chanx_left_in[16]:19 chanx_left_in[16]:18 0.0045 +10 chanx_left_in[16]:18 chanx_left_in[16]:17 0.004776786 +11 chanx_left_in[16]:16 chanx_left_in[16]:15 0.003214286 +12 chanx_left_in[16]:17 chanx_left_in[16]:16 0.0045 +13 chanx_left_in[16]:13 chanx_left_in[16]:12 0.0045 +14 chanx_left_in[16]:12 chanx_left_in[16]:11 0.009622768 +15 chanx_left_in[16]:11 chanx_left_in[16]:10 0.00341 +16 chanx_left_in[16]:10 chanx_left_in[16]:9 0.0002859166 +17 chanx_left_in[16]:8 chanx_left_in[16]:7 0.004765625 +18 chanx_left_in[16]:9 chanx_left_in[16]:8 0.00341 +19 chanx_left_in[16]:6 chanx_left_in[16]:5 0.0003370536 +20 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0045 +21 chanx_left_in[16]:5 ropt_mt_inst_759:A 0.152 +22 chanx_left_in[16]:20 mux_right_track_8\/mux_l2_in_3_:A1 0.152 +23 chanx_left_in[16]:20 chanx_left_in[16]:19 0.001602679 +24 chanx_left_in[16]:4 mux_top_track_20\/mux_l1_in_1_:A1 0.152 +25 chanx_left_in[16]:31 chanx_left_in[16]:30 0.001602679 +26 chanx_left_in[16]:32 chanx_left_in[16]:31 0.0045 +27 chanx_left_in[16]:33 chanx_left_in[16]:32 0.009622768 +28 chanx_left_in[16]:34 chanx_left_in[16]:33 0.00341 +29 chanx_left_in[16]:30 chanx_left_in[16]:29 0.003245536 +30 chanx_left_in[16]:30 chanx_left_in[16]:4 0.0003035715 +31 chanx_left_in[16]:21 chanx_left_in[16]:20 0.0003035715 +32 chanx_left_in[16]:15 chanx_left_in[16]:14 0.0002297297 +33 chanx_left_in[16]:14 chanx_left_in[16]:13 0.001191964 +34 chanx_left_in[16]:35 chanx_left_in[16]:34 0.002566591 + +*END + +*D_NET chany_top_in[8] 0.01075883 //LENGTH 73.870 LUMPCC 0.003930068 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 72.220 102.035 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 81.135 69.700 +*I mux_left_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.730 65.960 +*N chany_top_in[8]:3 *C 52.768 65.960 +*N chany_top_in[8]:4 *C 54.695 65.960 +*N chany_top_in[8]:5 *C 54.740 65.960 +*N chany_top_in[8]:6 *C 54.748 65.960 +*N chany_top_in[8]:7 *C 67.153 65.960 +*N chany_top_in[8]:8 *C 67.160 66.017 +*N chany_top_in[8]:9 *C 81.098 69.700 +*N chany_top_in[8]:10 *C 67.205 69.700 +*N chany_top_in[8]:11 *C 67.160 69.655 +*N chany_top_in[8]:12 *C 67.160 70.040 +*N chany_top_in[8]:13 *C 67.153 70.040 +*N chany_top_in[8]:14 *C 66.260 70.040 +*N chany_top_in[8]:15 *C 66.240 70.047 +*N chany_top_in[8]:16 *C 66.240 101.312 +*N chany_top_in[8]:17 *C 66.260 101.320 +*N chany_top_in[8]:18 *C 72.213 101.320 +*N chany_top_in[8]:19 *C 72.220 101.378 + +*CAP +0 chany_top_in[8] 4.635182e-05 +1 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_33\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[8]:3 0.0001654341 +4 chany_top_in[8]:4 0.0001654341 +5 chany_top_in[8]:5 3.8279e-05 +6 chany_top_in[8]:6 0.0007795282 +7 chany_top_in[8]:7 0.0007795282 +8 chany_top_in[8]:8 0.0002425229 +9 chany_top_in[8]:9 0.0007873137 +10 chany_top_in[8]:10 0.0007873137 +11 chany_top_in[8]:11 0.0002627274 +12 chany_top_in[8]:12 5.663889e-05 +13 chany_top_in[8]:13 9.906453e-05 +14 chany_top_in[8]:14 9.906453e-05 +15 chany_top_in[8]:15 0.0008745909 +16 chany_top_in[8]:16 0.0008745909 +17 chany_top_in[8]:17 0.000361016 +18 chany_top_in[8]:18 0.000361016 +19 chany_top_in[8]:19 4.635182e-05 +20 chany_top_in[8]:15 chany_top_in[9]:10 0.00061344 +21 chany_top_in[8]:17 chany_top_in[9]:12 9.380934e-05 +22 chany_top_in[8]:16 chany_top_in[9]:11 0.00061344 +23 chany_top_in[8]:18 chany_top_in[9]:13 9.380934e-05 +24 chany_top_in[8] chany_top_in[10] 8.969557e-06 +25 chany_top_in[8]:15 chany_top_in[10]:19 0.0003724619 +26 chany_top_in[8]:15 chany_top_in[10]:20 0.000227554 +27 chany_top_in[8]:17 chany_top_in[10]:22 5.665746e-05 +28 chany_top_in[8]:16 chany_top_in[10]:21 0.000227554 +29 chany_top_in[8]:16 chany_top_in[10]:20 0.0003724619 +30 chany_top_in[8]:19 chany_top_in[10]:24 8.969557e-06 +31 chany_top_in[8]:18 chany_top_in[10]:23 5.665746e-05 +32 chany_top_in[8]:7 chanx_right_in[1]:7 0.0004893659 +33 chany_top_in[8]:6 chanx_right_in[1]:6 0.0004893659 +34 chany_top_in[8]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000102776 +35 chany_top_in[8]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000102776 + +*RES +0 chany_top_in[8] chany_top_in[8]:19 0.0005870535 +1 chany_top_in[8]:12 chany_top_in[8]:11 0.0001850962 +2 chany_top_in[8]:13 chany_top_in[8]:12 0.00341 +3 chany_top_in[8]:14 chany_top_in[8]:13 0.000139825 +4 chany_top_in[8]:15 chany_top_in[8]:14 0.00341 +5 chany_top_in[8]:17 chany_top_in[8]:16 0.00341 +6 chany_top_in[8]:16 chany_top_in[8]:15 0.004898183 +7 chany_top_in[8]:19 chany_top_in[8]:18 0.00341 +8 chany_top_in[8]:18 chany_top_in[8]:17 0.0009325583 +9 chany_top_in[8]:8 chany_top_in[8]:7 0.00341 +10 chany_top_in[8]:7 chany_top_in[8]:6 0.00194345 +11 chany_top_in[8]:5 chany_top_in[8]:4 0.0045 +12 chany_top_in[8]:6 chany_top_in[8]:5 0.00341 +13 chany_top_in[8]:4 chany_top_in[8]:3 0.001720982 +14 chany_top_in[8]:3 mux_left_track_33\/mux_l1_in_0_:A0 0.152 +15 chany_top_in[8]:10 chany_top_in[8]:9 0.01240402 +16 chany_top_in[8]:11 chany_top_in[8]:10 0.0045 +17 chany_top_in[8]:11 chany_top_in[8]:8 0.003247768 +18 chany_top_in[8]:9 mux_right_track_4\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_top_in[16] 0.01351842 //LENGTH 93.035 LUMPCC 0.004326802 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 69.460 102.070 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 94.015 55.420 +*I mux_left_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 60.165 47.260 +*N chany_top_in[16]:3 *C 60.203 47.260 +*N chany_top_in[16]:4 *C 68.955 47.260 +*N chany_top_in[16]:5 *C 69.000 47.305 +*N chany_top_in[16]:6 *C 94.015 55.420 +*N chany_top_in[16]:7 *C 93.840 55.420 +*N chany_top_in[16]:8 *C 93.840 55.465 +*N chany_top_in[16]:9 *C 93.840 57.742 +*N chany_top_in[16]:10 *C 93.833 57.800 +*N chany_top_in[16]:11 *C 69.008 57.800 +*N chany_top_in[16]:12 *C 69.000 57.800 +*N chany_top_in[16]:13 *C 69.000 97.240 +*N chany_top_in[16]:14 *C 69.460 97.240 + +*CAP +0 chany_top_in[16] 0.0002973367 +1 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[16]:3 0.0006100704 +4 chany_top_in[16]:4 0.0006100704 +5 chany_top_in[16]:5 0.0004840241 +6 chany_top_in[16]:6 4.762543e-05 +7 chany_top_in[16]:7 5.183394e-05 +8 chany_top_in[16]:8 0.0001426664 +9 chany_top_in[16]:9 0.0001426664 +10 chany_top_in[16]:10 0.001243412 +11 chany_top_in[16]:11 0.001243412 +12 chany_top_in[16]:12 0.00224059 +13 chany_top_in[16]:13 0.00174755 +14 chany_top_in[16]:14 0.0003283592 +15 chany_top_in[16]:11 top_left_grid_pin_35_[0]:13 0.0002879217 +16 chany_top_in[16]:11 top_left_grid_pin_35_[0]:14 1.074806e-05 +17 chany_top_in[16]:10 top_left_grid_pin_35_[0]:9 0.0002879217 +18 chany_top_in[16]:10 top_left_grid_pin_35_[0]:13 1.074806e-05 +19 chany_top_in[16]:12 chanx_right_in[3]:4 8.810548e-05 +20 chany_top_in[16]:12 chanx_right_in[3]:5 0.000383084 +21 chany_top_in[16]:12 chanx_right_in[3]:8 5.085246e-05 +22 chany_top_in[16]:11 chanx_right_in[3]:6 2.365971e-06 +23 chany_top_in[16]:10 chanx_right_in[3]:7 2.365971e-06 +24 chany_top_in[16]:5 chanx_right_in[3]:5 8.810548e-05 +25 chany_top_in[16]:5 chanx_right_in[3]:9 5.085246e-05 +26 chany_top_in[16]:13 chanx_right_in[3]:4 0.000383084 +27 chany_top_in[16]:11 mux_tree_tapbuf_size3_0_sram[0]:17 0.001036044 +28 chany_top_in[16]:10 mux_tree_tapbuf_size3_0_sram[0]:18 0.001036044 +29 chany_top_in[16]:12 mux_tree_tapbuf_size7_1_sram[0]:19 1.298603e-05 +30 chany_top_in[16]:12 mux_tree_tapbuf_size7_1_sram[0]:21 2.331875e-06 +31 chany_top_in[16]:12 mux_tree_tapbuf_size7_1_sram[0]:24 0.0002638416 +32 chany_top_in[16]:12 mux_tree_tapbuf_size7_1_sram[0]:25 2.511905e-05 +33 chany_top_in[16]:5 mux_tree_tapbuf_size7_1_sram[0]:17 1.298603e-05 +34 chany_top_in[16]:5 mux_tree_tapbuf_size7_1_sram[0]:24 2.511905e-05 +35 chany_top_in[16]:5 mux_tree_tapbuf_size7_1_sram[0]:20 2.331875e-06 +36 chany_top_in[16]:13 mux_tree_tapbuf_size7_1_sram[0]:25 0.0002638416 + +*RES +0 chany_top_in[16] chany_top_in[16]:14 0.0043125 +1 chany_top_in[16]:12 chany_top_in[16]:11 0.00341 +2 chany_top_in[16]:12 chany_top_in[16]:5 0.009370536 +3 chany_top_in[16]:11 chany_top_in[16]:10 0.00388925 +4 chany_top_in[16]:9 chany_top_in[16]:8 0.002033482 +5 chany_top_in[16]:10 chany_top_in[16]:9 0.00341 +6 chany_top_in[16]:7 chany_top_in[16]:6 9.51087e-05 +7 chany_top_in[16]:8 chany_top_in[16]:7 0.0045 +8 chany_top_in[16]:6 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +9 chany_top_in[16]:4 chany_top_in[16]:3 0.007814732 +10 chany_top_in[16]:5 chany_top_in[16]:4 0.0045 +11 chany_top_in[16]:3 mux_left_track_25\/mux_l1_in_1_:A1 0.152 +12 chany_top_in[16]:13 chany_top_in[16]:12 0.03521429 +13 chany_top_in[16]:14 chany_top_in[16]:13 0.0004107143 + +*END + +*D_NET top_left_grid_pin_39_[0] 0.01632306 //LENGTH 123.105 LUMPCC 0.001534114 DR + +*CONN +*P top_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 96.560 +*I mux_top_track_34\/mux_l1_in_0_:A1 I *L 0.00198 *C 42.880 90.780 +*I mux_top_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 53.920 88.740 +*I mux_top_track_18\/mux_l1_in_0_:A1 I *L 0.00198 *C 65.685 45.220 +*I mux_top_track_6\/mux_l1_in_1_:A1 I *L 0.00198 *C 78.760 45.220 +*N top_left_grid_pin_39_[0]:5 *C 42.530 87.040 +*N top_left_grid_pin_39_[0]:6 *C 42.840 55.080 +*N top_left_grid_pin_39_[0]:7 *C 78.723 45.220 +*N top_left_grid_pin_39_[0]:8 *C 75.025 45.220 +*N top_left_grid_pin_39_[0]:9 *C 74.980 45.175 +*N top_left_grid_pin_39_[0]:10 *C 74.980 44.258 +*N top_left_grid_pin_39_[0]:11 *C 74.972 44.200 +*N top_left_grid_pin_39_[0]:12 *C 65.685 45.220 +*N top_left_grid_pin_39_[0]:13 *C 65.780 45.175 +*N top_left_grid_pin_39_[0]:14 *C 65.780 44.258 +*N top_left_grid_pin_39_[0]:15 *C 65.780 44.200 +*N top_left_grid_pin_39_[0]:16 *C 52.908 44.200 +*N top_left_grid_pin_39_[0]:17 *C 52.900 44.258 +*N top_left_grid_pin_39_[0]:18 *C 52.900 55.035 +*N top_left_grid_pin_39_[0]:19 *C 52.855 55.080 +*N top_left_grid_pin_39_[0]:20 *C 43.285 55.080 +*N top_left_grid_pin_39_[0]:21 *C 43.240 55.080 +*N top_left_grid_pin_39_[0]:22 *C 43.240 55.080 +*N top_left_grid_pin_39_[0]:23 *C 43.240 55.088 +*N top_left_grid_pin_39_[0]:24 *C 43.240 87.032 +*N top_left_grid_pin_39_[0]:25 *C 43.238 87.040 +*N top_left_grid_pin_39_[0]:26 *C 43.240 87.098 +*N top_left_grid_pin_39_[0]:27 *C 53.883 88.740 +*N top_left_grid_pin_39_[0]:28 *C 52.025 88.740 +*N top_left_grid_pin_39_[0]:29 *C 51.980 88.785 +*N top_left_grid_pin_39_[0]:30 *C 51.980 90.395 +*N top_left_grid_pin_39_[0]:31 *C 51.935 90.440 +*N top_left_grid_pin_39_[0]:32 *C 43.240 90.440 +*N top_left_grid_pin_39_[0]:33 *C 42.895 90.780 +*N top_left_grid_pin_39_[0]:34 *C 43.240 90.750 +*N top_left_grid_pin_39_[0]:35 *C 43.240 90.780 +*N top_left_grid_pin_39_[0]:36 *C 43.240 93.455 +*N top_left_grid_pin_39_[0]:37 *C 43.195 93.500 +*N top_left_grid_pin_39_[0]:38 *C 39.605 93.500 +*N top_left_grid_pin_39_[0]:39 *C 39.560 93.545 +*N top_left_grid_pin_39_[0]:40 *C 39.560 96.502 +*N top_left_grid_pin_39_[0]:41 *C 39.553 96.560 + +*CAP +0 top_left_grid_pin_39_[0] 0.0005970979 +1 mux_top_track_34\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_18\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_6\/mux_l1_in_1_:A1 1e-06 +5 top_left_grid_pin_39_[0]:5 9.647105e-05 +6 top_left_grid_pin_39_[0]:6 7.21755e-05 +7 top_left_grid_pin_39_[0]:7 0.0002733626 +8 top_left_grid_pin_39_[0]:8 0.0002733626 +9 top_left_grid_pin_39_[0]:9 7.926975e-05 +10 top_left_grid_pin_39_[0]:10 7.926975e-05 +11 top_left_grid_pin_39_[0]:11 0.0005089113 +12 top_left_grid_pin_39_[0]:12 3.163732e-05 +13 top_left_grid_pin_39_[0]:13 9.488779e-05 +14 top_left_grid_pin_39_[0]:14 9.488779e-05 +15 top_left_grid_pin_39_[0]:15 0.001201348 +16 top_left_grid_pin_39_[0]:16 0.0006924368 +17 top_left_grid_pin_39_[0]:17 0.0006812233 +18 top_left_grid_pin_39_[0]:18 0.0006812233 +19 top_left_grid_pin_39_[0]:19 0.0007018858 +20 top_left_grid_pin_39_[0]:20 0.0007018858 +21 top_left_grid_pin_39_[0]:21 3.935235e-05 +22 top_left_grid_pin_39_[0]:22 7.21755e-05 +23 top_left_grid_pin_39_[0]:23 0.001811399 +24 top_left_grid_pin_39_[0]:24 0.001811399 +25 top_left_grid_pin_39_[0]:25 9.647105e-05 +26 top_left_grid_pin_39_[0]:26 0.0002120969 +27 top_left_grid_pin_39_[0]:27 0.0001630483 +28 top_left_grid_pin_39_[0]:28 0.0001630483 +29 top_left_grid_pin_39_[0]:29 0.0001108174 +30 top_left_grid_pin_39_[0]:30 0.0001108174 +31 top_left_grid_pin_39_[0]:31 0.0005773214 +32 top_left_grid_pin_39_[0]:32 0.0006064934 +33 top_left_grid_pin_39_[0]:33 4.976837e-05 +34 top_left_grid_pin_39_[0]:34 7.894036e-05 +35 top_left_grid_pin_39_[0]:35 0.0004024931 +36 top_left_grid_pin_39_[0]:36 0.0001576398 +37 top_left_grid_pin_39_[0]:37 0.0002508444 +38 top_left_grid_pin_39_[0]:38 0.0002508444 +39 top_left_grid_pin_39_[0]:39 0.0001807692 +40 top_left_grid_pin_39_[0]:40 0.0001807692 +41 top_left_grid_pin_39_[0]:41 0.0005970979 +42 top_left_grid_pin_39_[0]:16 chanx_left_in[5]:28 0.0002472431 +43 top_left_grid_pin_39_[0]:16 chanx_left_in[5]:29 1.78737e-05 +44 top_left_grid_pin_39_[0]:11 chanx_left_in[5]:23 6.850676e-05 +45 top_left_grid_pin_39_[0]:11 chanx_left_in[5]:27 0.000114175 +46 top_left_grid_pin_39_[0]:15 chanx_left_in[5]:27 0.0003157498 +47 top_left_grid_pin_39_[0]:15 chanx_left_in[5]:28 0.0001320487 +48 top_left_grid_pin_39_[0]:23 chany_top_in[12]:15 0.0003192582 +49 top_left_grid_pin_39_[0]:24 chany_top_in[12]:16 0.0003192582 + +*RES +0 top_left_grid_pin_39_[0] top_left_grid_pin_39_[0]:41 0.001535725 +1 top_left_grid_pin_39_[0]:17 top_left_grid_pin_39_[0]:16 0.00341 +2 top_left_grid_pin_39_[0]:16 top_left_grid_pin_39_[0]:15 0.002016691 +3 top_left_grid_pin_39_[0]:19 top_left_grid_pin_39_[0]:18 0.0045 +4 top_left_grid_pin_39_[0]:18 top_left_grid_pin_39_[0]:17 0.009622768 +5 top_left_grid_pin_39_[0]:20 top_left_grid_pin_39_[0]:19 0.008544642 +6 top_left_grid_pin_39_[0]:21 top_left_grid_pin_39_[0]:20 0.0045 +7 top_left_grid_pin_39_[0]:22 top_left_grid_pin_39_[0]:21 0.00341 +8 top_left_grid_pin_39_[0]:22 top_left_grid_pin_39_[0]:6 5.696969e-05 +9 top_left_grid_pin_39_[0]:23 top_left_grid_pin_39_[0]:22 0.00341 +10 top_left_grid_pin_39_[0]:25 top_left_grid_pin_39_[0]:24 0.00341 +11 top_left_grid_pin_39_[0]:25 top_left_grid_pin_39_[0]:5 0.0001039141 +12 top_left_grid_pin_39_[0]:24 top_left_grid_pin_39_[0]:23 0.005004717 +13 top_left_grid_pin_39_[0]:26 top_left_grid_pin_39_[0]:25 0.00341 +14 top_left_grid_pin_39_[0]:31 top_left_grid_pin_39_[0]:30 0.0045 +15 top_left_grid_pin_39_[0]:30 top_left_grid_pin_39_[0]:29 0.0014375 +16 top_left_grid_pin_39_[0]:28 top_left_grid_pin_39_[0]:27 0.001658482 +17 top_left_grid_pin_39_[0]:29 top_left_grid_pin_39_[0]:28 0.0045 +18 top_left_grid_pin_39_[0]:27 mux_top_track_2\/mux_l1_in_1_:A1 0.152 +19 top_left_grid_pin_39_[0]:37 top_left_grid_pin_39_[0]:36 0.0045 +20 top_left_grid_pin_39_[0]:36 top_left_grid_pin_39_[0]:35 0.002388393 +21 top_left_grid_pin_39_[0]:38 top_left_grid_pin_39_[0]:37 0.003205357 +22 top_left_grid_pin_39_[0]:39 top_left_grid_pin_39_[0]:38 0.0045 +23 top_left_grid_pin_39_[0]:40 top_left_grid_pin_39_[0]:39 0.002640625 +24 top_left_grid_pin_39_[0]:41 top_left_grid_pin_39_[0]:40 0.00341 +25 top_left_grid_pin_39_[0]:34 top_left_grid_pin_39_[0]:33 0.0001875 +26 top_left_grid_pin_39_[0]:34 top_left_grid_pin_39_[0]:32 0.0002767857 +27 top_left_grid_pin_39_[0]:35 top_left_grid_pin_39_[0]:34 0.0045 +28 top_left_grid_pin_39_[0]:35 top_left_grid_pin_39_[0]:26 0.003287946 +29 top_left_grid_pin_39_[0]:10 top_left_grid_pin_39_[0]:9 0.0008191965 +30 top_left_grid_pin_39_[0]:11 top_left_grid_pin_39_[0]:10 0.00341 +31 top_left_grid_pin_39_[0]:8 top_left_grid_pin_39_[0]:7 0.00330134 +32 top_left_grid_pin_39_[0]:9 top_left_grid_pin_39_[0]:8 0.0045 +33 top_left_grid_pin_39_[0]:7 mux_top_track_6\/mux_l1_in_1_:A1 0.152 +34 top_left_grid_pin_39_[0]:14 top_left_grid_pin_39_[0]:13 0.0008191965 +35 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:14 0.00341 +36 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:11 0.001440158 +37 top_left_grid_pin_39_[0]:12 mux_top_track_18\/mux_l1_in_0_:A1 0.152 +38 top_left_grid_pin_39_[0]:13 top_left_grid_pin_39_[0]:12 0.0045 +39 top_left_grid_pin_39_[0]:33 mux_top_track_34\/mux_l1_in_0_:A1 0.152 +40 top_left_grid_pin_39_[0]:32 top_left_grid_pin_39_[0]:31 0.007763393 + +*END + +*D_NET right_top_grid_pin_45_[0] 0.01172796 //LENGTH 74.150 LUMPCC 0.00465988 DR + +*CONN +*P right_top_grid_pin_45_[0] I *L 0.29796 *C 137.540 74.870 +*I mux_right_track_4\/mux_l1_in_3_:A1 I *L 0.00198 *C 109.845 72.420 +*I mux_right_track_32\/mux_l1_in_1_:A0 I *L 0.001631 *C 83.550 71.740 +*I mux_right_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 98.440 83.300 +*N right_top_grid_pin_45_[0]:4 *C 98.478 83.300 +*N right_top_grid_pin_45_[0]:5 *C 98.855 83.300 +*N right_top_grid_pin_45_[0]:6 *C 98.900 83.255 +*N right_top_grid_pin_45_[0]:7 *C 98.900 78.200 +*N right_top_grid_pin_45_[0]:8 *C 99.360 78.200 +*N right_top_grid_pin_45_[0]:9 *C 83.550 71.740 +*N right_top_grid_pin_45_[0]:10 *C 83.720 71.740 +*N right_top_grid_pin_45_[0]:11 *C 83.720 71.785 +*N right_top_grid_pin_45_[0]:12 *C 83.720 74.743 +*N right_top_grid_pin_45_[0]:13 *C 83.728 74.800 +*N right_top_grid_pin_45_[0]:14 *C 99.353 74.800 +*N right_top_grid_pin_45_[0]:15 *C 99.360 74.800 +*N right_top_grid_pin_45_[0]:16 *C 99.360 72.465 +*N right_top_grid_pin_45_[0]:17 *C 99.405 72.420 +*N right_top_grid_pin_45_[0]:18 *C 109.435 72.420 +*N right_top_grid_pin_45_[0]:19 *C 109.870 72.420 +*N right_top_grid_pin_45_[0]:20 *C 109.940 72.465 +*N right_top_grid_pin_45_[0]:21 *C 109.940 74.075 +*N right_top_grid_pin_45_[0]:22 *C 109.985 74.120 +*N right_top_grid_pin_45_[0]:23 *C 137.495 74.120 +*N right_top_grid_pin_45_[0]:24 *C 137.540 74.165 + +*CAP +0 right_top_grid_pin_45_[0] 4.67615e-05 +1 mux_right_track_4\/mux_l1_in_3_:A1 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_2\/mux_l2_in_1_:A1 1e-06 +4 right_top_grid_pin_45_[0]:4 4.794121e-05 +5 right_top_grid_pin_45_[0]:5 4.794121e-05 +6 right_top_grid_pin_45_[0]:6 0.000295823 +7 right_top_grid_pin_45_[0]:7 0.0003268645 +8 right_top_grid_pin_45_[0]:8 0.0002354026 +9 right_top_grid_pin_45_[0]:9 5.619756e-05 +10 right_top_grid_pin_45_[0]:10 6.007573e-05 +11 right_top_grid_pin_45_[0]:11 0.0001976587 +12 right_top_grid_pin_45_[0]:12 0.0001976587 +13 right_top_grid_pin_45_[0]:13 0.000409132 +14 right_top_grid_pin_45_[0]:14 0.000409132 +15 right_top_grid_pin_45_[0]:15 0.000381892 +16 right_top_grid_pin_45_[0]:16 0.0001405903 +17 right_top_grid_pin_45_[0]:17 0.0004365394 +18 right_top_grid_pin_45_[0]:18 0.0004848693 +19 right_top_grid_pin_45_[0]:19 4.832993e-05 +20 right_top_grid_pin_45_[0]:20 0.0001158399 +21 right_top_grid_pin_45_[0]:21 0.0001158399 +22 right_top_grid_pin_45_[0]:22 0.001481917 +23 right_top_grid_pin_45_[0]:23 0.001481917 +24 right_top_grid_pin_45_[0]:24 4.67615e-05 +25 right_top_grid_pin_45_[0]:16 chany_top_in[15]:6 1.35533e-06 +26 right_top_grid_pin_45_[0]:15 chany_top_in[15]:7 1.35533e-06 +27 right_top_grid_pin_45_[0]:14 chany_top_in[15]:8 0.0002317292 +28 right_top_grid_pin_45_[0]:14 chany_top_in[15]:9 0.000631232 +29 right_top_grid_pin_45_[0]:13 chany_top_in[15]:9 0.0002317292 +30 right_top_grid_pin_45_[0]:13 chany_top_in[15]:10 0.000631232 +31 right_top_grid_pin_45_[0] right_top_grid_pin_48_[0] 2.835458e-07 +32 right_top_grid_pin_45_[0]:22 right_top_grid_pin_48_[0]:23 0.0002344913 +33 right_top_grid_pin_45_[0]:22 right_top_grid_pin_48_[0]:25 0.0002904494 +34 right_top_grid_pin_45_[0]:23 right_top_grid_pin_48_[0]:26 0.0002904494 +35 right_top_grid_pin_45_[0]:23 right_top_grid_pin_48_[0]:24 0.0002344913 +36 right_top_grid_pin_45_[0]:24 right_top_grid_pin_48_[0]:27 2.835458e-07 +37 right_top_grid_pin_45_[0] right_top_grid_pin_49_[0] 1.115876e-05 +38 right_top_grid_pin_45_[0]:17 right_top_grid_pin_49_[0]:10 0.0003290467 +39 right_top_grid_pin_45_[0]:24 right_top_grid_pin_49_[0]:24 1.115876e-05 +40 right_top_grid_pin_45_[0]:18 right_top_grid_pin_49_[0]:11 0.0003290467 +41 right_top_grid_pin_45_[0]:14 optlc_net_122:26 0.0003215166 +42 right_top_grid_pin_45_[0]:14 optlc_net_122:21 0.0001083795 +43 right_top_grid_pin_45_[0]:13 optlc_net_122:27 0.0003215166 +44 right_top_grid_pin_45_[0]:13 optlc_net_122:26 0.0001083795 +45 right_top_grid_pin_45_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001702973 +46 right_top_grid_pin_45_[0]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001702973 + +*RES +0 right_top_grid_pin_45_[0] right_top_grid_pin_45_[0]:24 0.0006294643 +1 right_top_grid_pin_45_[0]:4 mux_right_track_2\/mux_l2_in_1_:A1 0.152 +2 right_top_grid_pin_45_[0]:5 right_top_grid_pin_45_[0]:4 0.0003370536 +3 right_top_grid_pin_45_[0]:6 right_top_grid_pin_45_[0]:5 0.0045 +4 right_top_grid_pin_45_[0]:19 mux_right_track_4\/mux_l1_in_3_:A1 0.152 +5 right_top_grid_pin_45_[0]:19 right_top_grid_pin_45_[0]:18 0.0002364131 +6 right_top_grid_pin_45_[0]:17 right_top_grid_pin_45_[0]:16 0.0045 +7 right_top_grid_pin_45_[0]:16 right_top_grid_pin_45_[0]:15 0.002084821 +8 right_top_grid_pin_45_[0]:20 right_top_grid_pin_45_[0]:19 0.0045 +9 right_top_grid_pin_45_[0]:22 right_top_grid_pin_45_[0]:21 0.0045 +10 right_top_grid_pin_45_[0]:21 right_top_grid_pin_45_[0]:20 0.0014375 +11 right_top_grid_pin_45_[0]:23 right_top_grid_pin_45_[0]:22 0.0245625 +12 right_top_grid_pin_45_[0]:24 right_top_grid_pin_45_[0]:23 0.0045 +13 right_top_grid_pin_45_[0]:15 right_top_grid_pin_45_[0]:14 0.00341 +14 right_top_grid_pin_45_[0]:15 right_top_grid_pin_45_[0]:8 0.003035714 +15 right_top_grid_pin_45_[0]:14 right_top_grid_pin_45_[0]:13 0.002447916 +16 right_top_grid_pin_45_[0]:12 right_top_grid_pin_45_[0]:11 0.002640625 +17 right_top_grid_pin_45_[0]:13 right_top_grid_pin_45_[0]:12 0.00341 +18 right_top_grid_pin_45_[0]:10 right_top_grid_pin_45_[0]:9 9.239131e-05 +19 right_top_grid_pin_45_[0]:11 right_top_grid_pin_45_[0]:10 0.0045 +20 right_top_grid_pin_45_[0]:9 mux_right_track_32\/mux_l1_in_1_:A0 0.152 +21 right_top_grid_pin_45_[0]:18 right_top_grid_pin_45_[0]:17 0.008955359 +22 right_top_grid_pin_45_[0]:7 right_top_grid_pin_45_[0]:6 0.004513393 +23 right_top_grid_pin_45_[0]:8 right_top_grid_pin_45_[0]:7 0.0004107143 + +*END + +*D_NET left_top_grid_pin_48_[0] 0.00904293 //LENGTH 63.825 LUMPCC 0.002227418 DR + +*CONN +*P left_top_grid_pin_48_[0] I *L 0.29796 *C 11.500 74.835 +*I mux_left_track_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 22.715 64.260 +*I mux_left_track_5\/mux_l1_in_5_:A0 I *L 0.001631 *C 17.360 53.720 +*I mux_left_track_25\/mux_l1_in_3_:A1 I *L 0.00198 *C 33.220 47.260 +*N left_top_grid_pin_48_[0]:4 *C 33.258 47.260 +*N left_top_grid_pin_48_[0]:5 *C 33.580 47.260 +*N left_top_grid_pin_48_[0]:6 *C 33.580 46.920 +*N left_top_grid_pin_48_[0]:7 *C 25.805 46.920 +*N left_top_grid_pin_48_[0]:8 *C 25.760 46.965 +*N left_top_grid_pin_48_[0]:9 *C 25.760 48.223 +*N left_top_grid_pin_48_[0]:10 *C 25.753 48.280 +*N left_top_grid_pin_48_[0]:11 *C 18.408 48.280 +*N left_top_grid_pin_48_[0]:12 *C 18.400 48.338 +*N left_top_grid_pin_48_[0]:13 *C 17.398 53.720 +*N left_top_grid_pin_48_[0]:14 *C 18.355 53.720 +*N left_top_grid_pin_48_[0]:15 *C 18.400 53.720 +*N left_top_grid_pin_48_[0]:16 *C 18.400 60.815 +*N left_top_grid_pin_48_[0]:17 *C 18.445 60.860 +*N left_top_grid_pin_48_[0]:18 *C 22.035 60.860 +*N left_top_grid_pin_48_[0]:19 *C 22.080 60.905 +*N left_top_grid_pin_48_[0]:20 *C 22.678 64.260 +*N left_top_grid_pin_48_[0]:21 *C 22.125 64.260 +*N left_top_grid_pin_48_[0]:22 *C 22.080 64.260 +*N left_top_grid_pin_48_[0]:23 *C 22.080 66.583 +*N left_top_grid_pin_48_[0]:24 *C 22.073 66.640 +*N left_top_grid_pin_48_[0]:25 *C 20.248 66.640 +*N left_top_grid_pin_48_[0]:26 *C 20.240 66.698 +*N left_top_grid_pin_48_[0]:27 *C 20.240 74.062 +*N left_top_grid_pin_48_[0]:28 *C 20.233 74.120 +*N left_top_grid_pin_48_[0]:29 *C 11.508 74.120 +*N left_top_grid_pin_48_[0]:30 *C 11.500 74.178 + +*CAP +0 left_top_grid_pin_48_[0] 5.477336e-05 +1 mux_left_track_1\/mux_l2_in_2_:A0 1e-06 +2 mux_left_track_5\/mux_l1_in_5_:A0 1e-06 +3 mux_left_track_25\/mux_l1_in_3_:A1 1e-06 +4 left_top_grid_pin_48_[0]:4 4.239826e-05 +5 left_top_grid_pin_48_[0]:5 6.768334e-05 +6 left_top_grid_pin_48_[0]:6 0.0005035041 +7 left_top_grid_pin_48_[0]:7 0.000478219 +8 left_top_grid_pin_48_[0]:8 9.41768e-05 +9 left_top_grid_pin_48_[0]:9 9.41768e-05 +10 left_top_grid_pin_48_[0]:10 0.0003284209 +11 left_top_grid_pin_48_[0]:11 0.0003284209 +12 left_top_grid_pin_48_[0]:12 0.0002763692 +13 left_top_grid_pin_48_[0]:13 9.199666e-05 +14 left_top_grid_pin_48_[0]:14 9.199666e-05 +15 left_top_grid_pin_48_[0]:15 0.0006965171 +16 left_top_grid_pin_48_[0]:16 0.0003878128 +17 left_top_grid_pin_48_[0]:17 0.0002390929 +18 left_top_grid_pin_48_[0]:18 0.0002390929 +19 left_top_grid_pin_48_[0]:19 0.0001994287 +20 left_top_grid_pin_48_[0]:20 5.545669e-05 +21 left_top_grid_pin_48_[0]:21 5.545669e-05 +22 left_top_grid_pin_48_[0]:22 0.0003657323 +23 left_top_grid_pin_48_[0]:23 0.0001345688 +24 left_top_grid_pin_48_[0]:24 0.0002768347 +25 left_top_grid_pin_48_[0]:25 0.0002768347 +26 left_top_grid_pin_48_[0]:26 0.0004245074 +27 left_top_grid_pin_48_[0]:27 0.0004245074 +28 left_top_grid_pin_48_[0]:28 0.0002648797 +29 left_top_grid_pin_48_[0]:29 0.0002648797 +30 left_top_grid_pin_48_[0]:30 5.477336e-05 +31 left_top_grid_pin_48_[0]:11 chanx_left_in[6] 0.0004224472 +32 left_top_grid_pin_48_[0]:10 chanx_left_in[6]:20 0.0004224472 +33 left_top_grid_pin_48_[0]:29 left_top_grid_pin_44_[0]:23 0.000520076 +34 left_top_grid_pin_48_[0]:28 left_top_grid_pin_44_[0]:22 0.000520076 +35 left_top_grid_pin_48_[0]:11 left_top_grid_pin_44_[0]:14 7.436687e-06 +36 left_top_grid_pin_48_[0]:10 left_top_grid_pin_44_[0]:15 7.436687e-06 +37 left_top_grid_pin_48_[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.000113626 +38 left_top_grid_pin_48_[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000113626 +39 left_top_grid_pin_48_[0]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.0123e-05 +40 left_top_grid_pin_48_[0]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.0123e-05 + +*RES +0 left_top_grid_pin_48_[0] left_top_grid_pin_48_[0]:30 0.0005870535 +1 left_top_grid_pin_48_[0]:14 left_top_grid_pin_48_[0]:13 0.0008549108 +2 left_top_grid_pin_48_[0]:15 left_top_grid_pin_48_[0]:14 0.0045 +3 left_top_grid_pin_48_[0]:15 left_top_grid_pin_48_[0]:12 0.004805804 +4 left_top_grid_pin_48_[0]:13 mux_left_track_5\/mux_l1_in_5_:A0 0.152 +5 left_top_grid_pin_48_[0]:30 left_top_grid_pin_48_[0]:29 0.00341 +6 left_top_grid_pin_48_[0]:29 left_top_grid_pin_48_[0]:28 0.001366917 +7 left_top_grid_pin_48_[0]:27 left_top_grid_pin_48_[0]:26 0.006575894 +8 left_top_grid_pin_48_[0]:28 left_top_grid_pin_48_[0]:27 0.00341 +9 left_top_grid_pin_48_[0]:26 left_top_grid_pin_48_[0]:25 0.00341 +10 left_top_grid_pin_48_[0]:25 left_top_grid_pin_48_[0]:24 0.0002859167 +11 left_top_grid_pin_48_[0]:23 left_top_grid_pin_48_[0]:22 0.002073661 +12 left_top_grid_pin_48_[0]:24 left_top_grid_pin_48_[0]:23 0.00341 +13 left_top_grid_pin_48_[0]:18 left_top_grid_pin_48_[0]:17 0.003205357 +14 left_top_grid_pin_48_[0]:19 left_top_grid_pin_48_[0]:18 0.0045 +15 left_top_grid_pin_48_[0]:17 left_top_grid_pin_48_[0]:16 0.0045 +16 left_top_grid_pin_48_[0]:16 left_top_grid_pin_48_[0]:15 0.006334822 +17 left_top_grid_pin_48_[0]:12 left_top_grid_pin_48_[0]:11 0.00341 +18 left_top_grid_pin_48_[0]:11 left_top_grid_pin_48_[0]:10 0.001150717 +19 left_top_grid_pin_48_[0]:9 left_top_grid_pin_48_[0]:8 0.001122768 +20 left_top_grid_pin_48_[0]:10 left_top_grid_pin_48_[0]:9 0.00341 +21 left_top_grid_pin_48_[0]:7 left_top_grid_pin_48_[0]:6 0.006941965 +22 left_top_grid_pin_48_[0]:8 left_top_grid_pin_48_[0]:7 0.0045 +23 left_top_grid_pin_48_[0]:4 mux_left_track_25\/mux_l1_in_3_:A1 0.152 +24 left_top_grid_pin_48_[0]:21 left_top_grid_pin_48_[0]:20 0.0004933036 +25 left_top_grid_pin_48_[0]:22 left_top_grid_pin_48_[0]:21 0.0045 +26 left_top_grid_pin_48_[0]:22 left_top_grid_pin_48_[0]:19 0.002995536 +27 left_top_grid_pin_48_[0]:20 mux_left_track_1\/mux_l2_in_2_:A0 0.152 +28 left_top_grid_pin_48_[0]:6 left_top_grid_pin_48_[0]:5 0.0003035714 +29 left_top_grid_pin_48_[0]:5 left_top_grid_pin_48_[0]:4 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.01180443 //LENGTH 83.705 LUMPCC 0.002221048 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 75.535 83.640 +*I mux_left_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 33.940 66.980 +*I mux_left_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 45.640 79.560 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.515 75.140 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 74.640 89.080 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 74.603 89.080 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 74.105 89.080 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 74.060 89.035 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 36.515 75.140 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 36.340 75.140 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 36.340 75.185 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 36.340 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 45.602 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 33.940 66.980 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 34.040 67.025 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 34.040 75.480 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 32.660 75.480 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 32.660 79.515 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 32.705 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 36.800 79.560 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 36.800 79.605 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 36.800 83.583 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 36.808 83.640 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 73.970 83.640 +*N mux_tree_tapbuf_size10_0_sram[0]:24 *C 74.060 83.640 +*N mux_tree_tapbuf_size10_0_sram[0]:25 *C 74.105 83.640 +*N mux_tree_tapbuf_size10_0_sram[0]:26 *C 75.498 83.640 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_1\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_1\/mux_l1_in_1_:S 1e-06 +3 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 7.10948e-05 +6 mux_tree_tapbuf_size10_0_sram[0]:6 7.10948e-05 +7 mux_tree_tapbuf_size10_0_sram[0]:7 0.0003612357 +8 mux_tree_tapbuf_size10_0_sram[0]:8 4.586388e-05 +9 mux_tree_tapbuf_size10_0_sram[0]:9 5.006174e-05 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0002387083 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.000265335 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0004714602 +13 mux_tree_tapbuf_size10_0_sram[0]:13 2.935952e-05 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0004271086 +15 mux_tree_tapbuf_size10_0_sram[0]:15 0.0004944518 +16 mux_tree_tapbuf_size10_0_sram[0]:16 0.0002307117 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0001633686 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0002134579 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0007162892 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.000240936 +21 mux_tree_tapbuf_size10_0_sram[0]:21 0.0002143093 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.00231354 +23 mux_tree_tapbuf_size10_0_sram[0]:23 0.00231354 +24 mux_tree_tapbuf_size10_0_sram[0]:24 0.0003974662 +25 mux_tree_tapbuf_size10_0_sram[0]:25 0.000124496 +26 mux_tree_tapbuf_size10_0_sram[0]:26 0.000124496 +27 mux_tree_tapbuf_size10_0_sram[0]:17 prog_clk[0]:563 4.632403e-07 +28 mux_tree_tapbuf_size10_0_sram[0]:14 prog_clk[0]:553 3.133518e-07 +29 mux_tree_tapbuf_size10_0_sram[0]:14 prog_clk[0]:559 7.532494e-08 +30 mux_tree_tapbuf_size10_0_sram[0]:19 prog_clk[0]:577 1.483504e-05 +31 mux_tree_tapbuf_size10_0_sram[0]:12 prog_clk[0]:576 1.483504e-05 +32 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:187 6.555347e-05 +33 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:320 0.0001391667 +34 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:340 0.0001133073 +35 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:582 7.515775e-05 +36 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:188 6.555347e-05 +37 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:340 0.0001391667 +38 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:341 0.0001133073 +39 mux_tree_tapbuf_size10_0_sram[0]:22 prog_clk[0]:586 7.515775e-05 +40 mux_tree_tapbuf_size10_0_sram[0]:16 prog_clk[0]:558 1.266804e-05 +41 mux_tree_tapbuf_size10_0_sram[0]:16 prog_clk[0]:559 4.632403e-07 +42 mux_tree_tapbuf_size10_0_sram[0]:15 prog_clk[0]:557 1.266804e-05 +43 mux_tree_tapbuf_size10_0_sram[0]:15 prog_clk[0]:559 3.133518e-07 +44 mux_tree_tapbuf_size10_0_sram[0]:15 prog_clk[0]:563 7.532494e-08 +45 mux_tree_tapbuf_size10_0_sram[0]:23 top_left_grid_pin_41_[0]:19 0.0002934282 +46 mux_tree_tapbuf_size10_0_sram[0]:22 top_left_grid_pin_41_[0]:20 0.0002934282 +47 mux_tree_tapbuf_size10_0_sram[0]:18 chanx_left_in[15]:7 7.303314e-05 +48 mux_tree_tapbuf_size10_0_sram[0]:17 chanx_left_in[15]:8 5.165118e-05 +49 mux_tree_tapbuf_size10_0_sram[0]:14 chanx_left_in[15]:9 3.650717e-07 +50 mux_tree_tapbuf_size10_0_sram[0]:19 chanx_left_in[15]:6 7.303314e-05 +51 mux_tree_tapbuf_size10_0_sram[0]:19 chanx_left_in[15]:7 0.0001339019 +52 mux_tree_tapbuf_size10_0_sram[0]:20 chanx_left_in[15]:6 6.730373e-06 +53 mux_tree_tapbuf_size10_0_sram[0]:12 chanx_left_in[15]:6 0.0001339019 +54 mux_tree_tapbuf_size10_0_sram[0]:16 chanx_left_in[15]:9 5.165118e-05 +55 mux_tree_tapbuf_size10_0_sram[0]:15 chanx_left_in[15]:8 3.650717e-07 +56 mux_tree_tapbuf_size10_0_sram[0]:11 chanx_left_in[15]:7 6.730373e-06 +57 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 1.692572e-05 +58 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 8.354712e-05 +59 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 9.287144e-06 +60 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 2.011414e-05 +61 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 9.287144e-06 +62 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 1.692572e-05 +63 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 8.354712e-05 +64 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 2.011414e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.0045 +2 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.003602679 +3 mux_tree_tapbuf_size10_0_sram[0]:13 mux_left_track_1\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +5 mux_tree_tapbuf_size10_0_sram[0]:25 mux_tree_tapbuf_size10_0_sram[0]:24 0.0045 +6 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:23 0.00341 +7 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:7 0.004816964 +8 mux_tree_tapbuf_size10_0_sram[0]:26 mux_tree_tapbuf_size10_0_sram[0]:25 0.001243304 +9 mux_tree_tapbuf_size10_0_sram[0]:5 mux_left_track_1\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.0004441965 +11 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0045 +12 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.00365625 +13 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:12 0.007859375 +14 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0045 +15 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:11 0.0004107143 +16 mux_tree_tapbuf_size10_0_sram[0]:9 mux_tree_tapbuf_size10_0_sram[0]:8 9.51087e-05 +17 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.0045 +18 mux_tree_tapbuf_size10_0_sram[0]:8 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size10_0_sram[0]:12 mux_left_track_1\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.005822125 +21 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.003551339 +22 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.00341 +23 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.001232143 +24 mux_tree_tapbuf_size10_0_sram[0]:15 mux_tree_tapbuf_size10_0_sram[0]:14 0.007549107 +25 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.00390625 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.0007415852 //LENGTH 5.580 LUMPCC 9.777411e-05 DR + +*CONN +*I mem_top_track_34\/FTB_25__51:X O *L 0 *C 50.835 93.840 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 52.615 96.900 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 52.615 96.900 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 52.440 96.900 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 52.440 96.855 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 52.440 93.885 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 52.395 93.840 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 50.873 93.840 + +*CAP +0 mem_top_track_34\/FTB_25__51:X 1e-06 +1 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 5.780763e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 5.925283e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0001523053 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0001523053 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.00011007 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.00011007 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 prog_clk[0]:354 9.726697e-06 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 prog_clk[0]:353 9.726697e-06 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 prog_clk[0]:349 3.189249e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 prog_clk[0]:353 6.715765e-06 +12 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 prog_clk[0]:354 5.52105e-07 +13 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 prog_clk[0]:352 6.715765e-06 +14 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 prog_clk[0]:353 3.189249e-05 +15 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 prog_clk[0]:355 5.52105e-07 + +*RES +0 mem_top_track_34\/FTB_25__51:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.001359375 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[1] 0.001900908 //LENGTH 14.195 LUMPCC 0.0005473857 DR + +*CONN +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 75.285 37.060 +*I mem_top_track_20\/FTB_18__44:A I *L 0.001746 *C 72.220 31.280 +*I mux_top_track_20\/mux_l2_in_0_:S I *L 0.00357 *C 73.500 41.480 +*N mux_tree_tapbuf_size3_4_sram[1]:3 *C 73.500 41.480 +*N mux_tree_tapbuf_size3_4_sram[1]:4 *C 73.600 41.435 +*N mux_tree_tapbuf_size3_4_sram[1]:5 *C 72.258 31.280 +*N mux_tree_tapbuf_size3_4_sram[1]:6 *C 73.555 31.280 +*N mux_tree_tapbuf_size3_4_sram[1]:7 *C 73.600 31.325 +*N mux_tree_tapbuf_size3_4_sram[1]:8 *C 73.600 37.060 +*N mux_tree_tapbuf_size3_4_sram[1]:9 *C 73.645 37.060 +*N mux_tree_tapbuf_size3_4_sram[1]:10 *C 75.248 37.060 + +*CAP +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_20\/FTB_18__44:A 1e-06 +2 mux_top_track_20\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_4_sram[1]:3 3.101235e-05 +4 mux_tree_tapbuf_size3_4_sram[1]:4 0.0001758373 +5 mux_tree_tapbuf_size3_4_sram[1]:5 0.0001259746 +6 mux_tree_tapbuf_size3_4_sram[1]:6 0.0001259746 +7 mux_tree_tapbuf_size3_4_sram[1]:7 0.0002274551 +8 mux_tree_tapbuf_size3_4_sram[1]:8 0.0004339327 +9 mux_tree_tapbuf_size3_4_sram[1]:9 0.000115168 +10 mux_tree_tapbuf_size3_4_sram[1]:10 0.000115168 +11 mux_tree_tapbuf_size3_4_sram[1]:7 chanx_right_in[4]:24 0.0001526287 +12 mux_tree_tapbuf_size3_4_sram[1]:8 chanx_right_in[4]:23 0.0001526287 +13 mux_tree_tapbuf_size3_4_sram[1]:8 chanx_right_in[4]:24 0.0001210642 +14 mux_tree_tapbuf_size3_4_sram[1]:4 chanx_right_in[4]:23 0.0001210642 + +*RES +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_4_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_4_sram[1]:6 mux_tree_tapbuf_size3_4_sram[1]:5 0.001158482 +2 mux_tree_tapbuf_size3_4_sram[1]:7 mux_tree_tapbuf_size3_4_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size3_4_sram[1]:5 mem_top_track_20\/FTB_18__44:A 0.152 +4 mux_tree_tapbuf_size3_4_sram[1]:9 mux_tree_tapbuf_size3_4_sram[1]:8 0.0045 +5 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size3_4_sram[1]:7 0.005120536 +6 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size3_4_sram[1]:4 0.00390625 +7 mux_tree_tapbuf_size3_4_sram[1]:10 mux_tree_tapbuf_size3_4_sram[1]:9 0.001430803 +8 mux_tree_tapbuf_size3_4_sram[1]:3 mux_top_track_20\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size3_4_sram[1]:4 mux_tree_tapbuf_size3_4_sram[1]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.0007209193 //LENGTH 5.360 LUMPCC 0 DR + +*CONN +*I mem_top_track_14\/FTB_15__41:X O *L 0 *C 47.615 55.760 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 49.395 53.380 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 49.395 53.380 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 49.680 53.380 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 49.680 53.425 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 49.680 55.715 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 49.635 55.760 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 47.653 55.760 + +*CAP +0 mem_top_track_14\/FTB_15__41:X 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 5.22207e-05 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 5.280496e-05 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.0001452601 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0001452601 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0001616867 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0001616867 + +*RES +0 mem_top_track_14\/FTB_15__41:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_0_ccff_tail[0] 0.001644204 //LENGTH 11.440 LUMPCC 0.0005508027 DR + +*CONN +*I mem_top_track_8\/FTB_12__38:X O *L 0 *C 115.685 44.540 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 108.735 47.940 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 *C 108.735 47.940 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 *C 108.560 47.940 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 *C 108.560 47.895 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 *C 108.560 44.585 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 *C 108.605 44.540 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 *C 115.648 44.540 + +*CAP +0 mem_top_track_8\/FTB_12__38:X 1e-06 +1 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 4.817303e-05 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 5.276231e-05 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.0002122268 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0002122268 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.0002830064 +7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.0002830064 +8 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size4_0_sram[2]:4 0.0002754013 +9 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size4_0_sram[2]:5 0.0002754013 + +*RES +0 mem_top_track_8\/FTB_12__38:X mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.002955357 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.006287946 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[1] 0.001753633 //LENGTH 14.500 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 60.565 85.680 +*I mux_top_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 62.440 83.300 +*I mux_top_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 59.700 88.400 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 62.275 91.460 +*N mux_tree_tapbuf_size7_0_sram[1]:4 *C 62.238 91.460 +*N mux_tree_tapbuf_size7_0_sram[1]:5 *C 61.685 91.460 +*N mux_tree_tapbuf_size7_0_sram[1]:6 *C 61.640 91.415 +*N mux_tree_tapbuf_size7_0_sram[1]:7 *C 59.700 88.400 +*N mux_tree_tapbuf_size7_0_sram[1]:8 *C 59.800 88.060 +*N mux_tree_tapbuf_size7_0_sram[1]:9 *C 61.595 88.060 +*N mux_tree_tapbuf_size7_0_sram[1]:10 *C 61.640 88.060 +*N mux_tree_tapbuf_size7_0_sram[1]:11 *C 62.403 83.300 +*N mux_tree_tapbuf_size7_0_sram[1]:12 *C 61.685 83.300 +*N mux_tree_tapbuf_size7_0_sram[1]:13 *C 61.640 83.345 +*N mux_tree_tapbuf_size7_0_sram[1]:14 *C 61.640 85.680 +*N mux_tree_tapbuf_size7_0_sram[1]:15 *C 61.595 85.680 +*N mux_tree_tapbuf_size7_0_sram[1]:16 *C 60.603 85.680 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_2\/mux_l2_in_0_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_0_sram[1]:4 5.871858e-05 +5 mux_tree_tapbuf_size7_0_sram[1]:5 5.871858e-05 +6 mux_tree_tapbuf_size7_0_sram[1]:6 0.0001963336 +7 mux_tree_tapbuf_size7_0_sram[1]:7 5.72106e-05 +8 mux_tree_tapbuf_size7_0_sram[1]:8 0.0001568276 +9 mux_tree_tapbuf_size7_0_sram[1]:9 0.0001286868 +10 mux_tree_tapbuf_size7_0_sram[1]:10 0.0003540301 +11 mux_tree_tapbuf_size7_0_sram[1]:11 6.299022e-05 +12 mux_tree_tapbuf_size7_0_sram[1]:12 6.299022e-05 +13 mux_tree_tapbuf_size7_0_sram[1]:13 0.0001333256 +14 mux_tree_tapbuf_size7_0_sram[1]:14 0.0002907241 +15 mux_tree_tapbuf_size7_0_sram[1]:15 9.453847e-05 +16 mux_tree_tapbuf_size7_0_sram[1]:16 9.453847e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_0_sram[1]:11 mux_top_track_2\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_0_sram[1]:12 mux_tree_tapbuf_size7_0_sram[1]:11 0.000640625 +3 mux_tree_tapbuf_size7_0_sram[1]:13 mux_tree_tapbuf_size7_0_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size7_0_sram[1]:5 mux_tree_tapbuf_size7_0_sram[1]:4 0.0004933036 +5 mux_tree_tapbuf_size7_0_sram[1]:6 mux_tree_tapbuf_size7_0_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size7_0_sram[1]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:13 0.002084821 +9 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:10 0.002125 +10 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:15 0.0008861609 +11 mux_tree_tapbuf_size7_0_sram[1]:9 mux_tree_tapbuf_size7_0_sram[1]:8 0.001602679 +12 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:9 0.0045 +13 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:6 0.002995536 +14 mux_tree_tapbuf_size7_0_sram[1]:7 mux_top_track_2\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size7_0_sram[1]:8 mux_tree_tapbuf_size7_0_sram[1]:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[2] 0.001602652 //LENGTH 12.185 LUMPCC 0.0001901897 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 93.990 67.320 +*I mem_right_track_24\/FTB_9__35:A I *L 0.001746 *C 97.980 72.080 +*I mux_right_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 99.260 67.320 +*N mux_tree_tapbuf_size7_4_sram[2]:3 *C 99.245 67.320 +*N mux_tree_tapbuf_size7_4_sram[2]:4 *C 98.017 72.080 +*N mux_tree_tapbuf_size7_4_sram[2]:5 *C 98.855 72.080 +*N mux_tree_tapbuf_size7_4_sram[2]:6 *C 98.900 72.035 +*N mux_tree_tapbuf_size7_4_sram[2]:7 *C 98.900 67.365 +*N mux_tree_tapbuf_size7_4_sram[2]:8 *C 98.922 67.320 +*N mux_tree_tapbuf_size7_4_sram[2]:9 *C 94.028 67.320 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_24\/FTB_9__35:A 1e-06 +2 mux_right_track_24\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_4_sram[2]:3 5.169729e-05 +4 mux_tree_tapbuf_size7_4_sram[2]:4 7.989911e-05 +5 mux_tree_tapbuf_size7_4_sram[2]:5 7.989911e-05 +6 mux_tree_tapbuf_size7_4_sram[2]:6 0.0002788105 +7 mux_tree_tapbuf_size7_4_sram[2]:7 0.0002788105 +8 mux_tree_tapbuf_size7_4_sram[2]:8 0.0003460215 +9 mux_tree_tapbuf_size7_4_sram[2]:9 0.0002943242 +10 mux_tree_tapbuf_size7_4_sram[2]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.217947e-05 +11 mux_tree_tapbuf_size7_4_sram[2]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.915404e-06 +12 mux_tree_tapbuf_size7_4_sram[2]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.915404e-06 +13 mux_tree_tapbuf_size7_4_sram[2]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.217947e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_4_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_4_sram[2]:3 mux_right_track_24\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_4_sram[2]:8 mux_tree_tapbuf_size7_4_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size7_4_sram[2]:8 mux_tree_tapbuf_size7_4_sram[2]:3 0.0001752718 +4 mux_tree_tapbuf_size7_4_sram[2]:7 mux_tree_tapbuf_size7_4_sram[2]:6 0.004169643 +5 mux_tree_tapbuf_size7_4_sram[2]:5 mux_tree_tapbuf_size7_4_sram[2]:4 0.0007477679 +6 mux_tree_tapbuf_size7_4_sram[2]:6 mux_tree_tapbuf_size7_4_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size7_4_sram[2]:4 mem_right_track_24\/FTB_9__35:A 0.152 +8 mux_tree_tapbuf_size7_4_sram[2]:9 mux_tree_tapbuf_size7_4_sram[2]:8 0.004370536 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_0_ccff_tail[0] 0.001279687 //LENGTH 10.125 LUMPCC 0.00011601 DR + +*CONN +*I mem_top_track_2\/FTB_5__31:X O *L 0 *C 71.505 85.000 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 66.870 80.580 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 *C 66.892 80.608 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 *C 66.905 80.920 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 *C 67.575 80.920 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 *C 67.620 80.965 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 *C 67.620 84.955 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 *C 67.665 85.000 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 *C 71.468 85.000 + +*CAP +0 mem_top_track_2\/FTB_5__31:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 3.396846e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0001031177 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 6.914927e-05 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0002148178 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.0002148178 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.0002629032 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 0.0002629032 +9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 prog_clk[0]:188 1.369278e-05 +10 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 prog_clk[0]:319 4.431223e-05 +11 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 prog_clk[0]:318 4.431223e-05 +12 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 prog_clk[0]:320 1.369278e-05 + +*RES +0 mem_top_track_2\/FTB_5__31:X mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.003395089 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0035625 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0005982143 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[0] 0.002827827 //LENGTH 22.345 LUMPCC 0.0001228111 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 99.665 53.380 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 85.920 52.360 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 91.715 49.980 +*N mux_tree_tapbuf_size8_1_sram[0]:3 *C 91.715 49.980 +*N mux_tree_tapbuf_size8_1_sram[0]:4 *C 85.958 52.360 +*N mux_tree_tapbuf_size8_1_sram[0]:5 *C 86.940 52.360 +*N mux_tree_tapbuf_size8_1_sram[0]:6 *C 86.940 52.700 +*N mux_tree_tapbuf_size8_1_sram[0]:7 *C 91.955 52.700 +*N mux_tree_tapbuf_size8_1_sram[0]:8 *C 92.000 52.655 +*N mux_tree_tapbuf_size8_1_sram[0]:9 *C 92.000 50.025 +*N mux_tree_tapbuf_size8_1_sram[0]:10 *C 92.045 49.980 +*N mux_tree_tapbuf_size8_1_sram[0]:11 *C 96.095 49.980 +*N mux_tree_tapbuf_size8_1_sram[0]:12 *C 96.140 50.025 +*N mux_tree_tapbuf_size8_1_sram[0]:13 *C 96.140 53.335 +*N mux_tree_tapbuf_size8_1_sram[0]:14 *C 96.185 53.380 +*N mux_tree_tapbuf_size8_1_sram[0]:15 *C 99.627 53.380 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_1_sram[0]:3 4.968017e-05 +4 mux_tree_tapbuf_size8_1_sram[0]:4 8.812484e-05 +5 mux_tree_tapbuf_size8_1_sram[0]:5 0.0001123414 +6 mux_tree_tapbuf_size8_1_sram[0]:6 0.0003368375 +7 mux_tree_tapbuf_size8_1_sram[0]:7 0.0003126209 +8 mux_tree_tapbuf_size8_1_sram[0]:8 0.000188944 +9 mux_tree_tapbuf_size8_1_sram[0]:9 0.000188944 +10 mux_tree_tapbuf_size8_1_sram[0]:10 0.0003005575 +11 mux_tree_tapbuf_size8_1_sram[0]:11 0.0002795823 +12 mux_tree_tapbuf_size8_1_sram[0]:12 0.0001967596 +13 mux_tree_tapbuf_size8_1_sram[0]:13 0.0001967596 +14 mux_tree_tapbuf_size8_1_sram[0]:14 0.0002254319 +15 mux_tree_tapbuf_size8_1_sram[0]:15 0.0002254319 +16 mux_tree_tapbuf_size8_1_sram[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.960687e-05 +17 mux_tree_tapbuf_size8_1_sram[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.798677e-06 +18 mux_tree_tapbuf_size8_1_sram[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.798677e-06 +19 mux_tree_tapbuf_size8_1_sram[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.960687e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_1_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_1_sram[0]:3 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_1_sram[0]:10 0.003616072 +3 mux_tree_tapbuf_size8_1_sram[0]:12 mux_tree_tapbuf_size8_1_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size8_1_sram[0]:14 mux_tree_tapbuf_size8_1_sram[0]:13 0.0045 +5 mux_tree_tapbuf_size8_1_sram[0]:13 mux_tree_tapbuf_size8_1_sram[0]:12 0.002955357 +6 mux_tree_tapbuf_size8_1_sram[0]:15 mux_tree_tapbuf_size8_1_sram[0]:14 0.003073661 +7 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001793478 +9 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:8 0.002348215 +10 mux_tree_tapbuf_size8_1_sram[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 0.004477679 +11 mux_tree_tapbuf_size8_1_sram[0]:8 mux_tree_tapbuf_size8_1_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size8_1_sram[0]:4 mux_right_track_8\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_1_sram[0]:4 0.0008772322 +14 mux_tree_tapbuf_size8_1_sram[0]:6 mux_tree_tapbuf_size8_1_sram[0]:5 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[3] 0.005532387 //LENGTH 44.865 LUMPCC 0.001754588 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 127.265 71.740 +*I mux_right_track_0\/mux_l4_in_0_:S I *L 0.00357 *C 125.920 69.020 +*I mem_right_track_0\/FTB_27__53:A I *L 0.001746 *C 109.480 91.120 +*N mux_tree_tapbuf_size9_0_sram[3]:3 *C 109.480 91.120 +*N mux_tree_tapbuf_size9_0_sram[3]:4 *C 109.480 91.075 +*N mux_tree_tapbuf_size9_0_sram[3]:5 *C 109.480 85.737 +*N mux_tree_tapbuf_size9_0_sram[3]:6 *C 109.473 85.680 +*N mux_tree_tapbuf_size9_0_sram[3]:7 *C 108.580 85.680 +*N mux_tree_tapbuf_size9_0_sram[3]:8 *C 108.560 85.672 +*N mux_tree_tapbuf_size9_0_sram[3]:9 *C 108.560 73.448 +*N mux_tree_tapbuf_size9_0_sram[3]:10 *C 108.580 73.440 +*N mux_tree_tapbuf_size9_0_sram[3]:11 *C 125.113 73.440 +*N mux_tree_tapbuf_size9_0_sram[3]:12 *C 125.120 73.383 +*N mux_tree_tapbuf_size9_0_sram[3]:13 *C 125.883 69.020 +*N mux_tree_tapbuf_size9_0_sram[3]:14 *C 125.165 69.020 +*N mux_tree_tapbuf_size9_0_sram[3]:15 *C 125.120 69.065 +*N mux_tree_tapbuf_size9_0_sram[3]:16 *C 125.120 71.740 +*N mux_tree_tapbuf_size9_0_sram[3]:17 *C 125.165 71.740 +*N mux_tree_tapbuf_size9_0_sram[3]:18 *C 127.228 71.740 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_track_0\/mux_l4_in_0_:S 1e-06 +2 mem_right_track_0\/FTB_27__53:A 1e-06 +3 mux_tree_tapbuf_size9_0_sram[3]:3 3.59197e-05 +4 mux_tree_tapbuf_size9_0_sram[3]:4 0.0002808034 +5 mux_tree_tapbuf_size9_0_sram[3]:5 0.0002808034 +6 mux_tree_tapbuf_size9_0_sram[3]:6 7.574616e-05 +7 mux_tree_tapbuf_size9_0_sram[3]:7 7.574616e-05 +8 mux_tree_tapbuf_size9_0_sram[3]:8 0.0002276865 +9 mux_tree_tapbuf_size9_0_sram[3]:9 0.0002276865 +10 mux_tree_tapbuf_size9_0_sram[3]:10 0.0007941122 +11 mux_tree_tapbuf_size9_0_sram[3]:11 0.0007941122 +12 mux_tree_tapbuf_size9_0_sram[3]:12 0.0001043398 +13 mux_tree_tapbuf_size9_0_sram[3]:13 8.152625e-05 +14 mux_tree_tapbuf_size9_0_sram[3]:14 8.152625e-05 +15 mux_tree_tapbuf_size9_0_sram[3]:15 0.0001530863 +16 mux_tree_tapbuf_size9_0_sram[3]:16 0.0002924307 +17 mux_tree_tapbuf_size9_0_sram[3]:17 0.0001346371 +18 mux_tree_tapbuf_size9_0_sram[3]:18 0.0001346371 +19 mux_tree_tapbuf_size9_0_sram[3]:9 chanx_left_in[4]:18 0.0003667713 +20 mux_tree_tapbuf_size9_0_sram[3]:8 chanx_left_in[4]:19 0.0003667713 +21 mux_tree_tapbuf_size9_0_sram[3]:9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002919552 +22 mux_tree_tapbuf_size9_0_sram[3]:8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002919552 +23 mux_tree_tapbuf_size9_0_sram[3]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 1.817103e-05 +24 mux_tree_tapbuf_size9_0_sram[3]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0002003965 +25 mux_tree_tapbuf_size9_0_sram[3]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0002003965 +26 mux_tree_tapbuf_size9_0_sram[3]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.817103e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size9_0_sram[3]:18 0.152 +1 mux_tree_tapbuf_size9_0_sram[3]:13 mux_right_track_0\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size9_0_sram[3]:14 mux_tree_tapbuf_size9_0_sram[3]:13 0.000640625 +3 mux_tree_tapbuf_size9_0_sram[3]:15 mux_tree_tapbuf_size9_0_sram[3]:14 0.0045 +4 mux_tree_tapbuf_size9_0_sram[3]:12 mux_tree_tapbuf_size9_0_sram[3]:11 0.00341 +5 mux_tree_tapbuf_size9_0_sram[3]:11 mux_tree_tapbuf_size9_0_sram[3]:10 0.002590091 +6 mux_tree_tapbuf_size9_0_sram[3]:10 mux_tree_tapbuf_size9_0_sram[3]:9 0.00341 +7 mux_tree_tapbuf_size9_0_sram[3]:9 mux_tree_tapbuf_size9_0_sram[3]:8 0.00191525 +8 mux_tree_tapbuf_size9_0_sram[3]:7 mux_tree_tapbuf_size9_0_sram[3]:6 0.000139825 +9 mux_tree_tapbuf_size9_0_sram[3]:8 mux_tree_tapbuf_size9_0_sram[3]:7 0.00341 +10 mux_tree_tapbuf_size9_0_sram[3]:5 mux_tree_tapbuf_size9_0_sram[3]:4 0.004765625 +11 mux_tree_tapbuf_size9_0_sram[3]:6 mux_tree_tapbuf_size9_0_sram[3]:5 0.00341 +12 mux_tree_tapbuf_size9_0_sram[3]:3 mem_right_track_0\/FTB_27__53:A 0.152 +13 mux_tree_tapbuf_size9_0_sram[3]:4 mux_tree_tapbuf_size9_0_sram[3]:3 0.0045 +14 mux_tree_tapbuf_size9_0_sram[3]:17 mux_tree_tapbuf_size9_0_sram[3]:16 0.0045 +15 mux_tree_tapbuf_size9_0_sram[3]:16 mux_tree_tapbuf_size9_0_sram[3]:15 0.002388393 +16 mux_tree_tapbuf_size9_0_sram[3]:16 mux_tree_tapbuf_size9_0_sram[3]:12 0.001466518 +17 mux_tree_tapbuf_size9_0_sram[3]:18 mux_tree_tapbuf_size9_0_sram[3]:17 0.001841518 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004787642 //LENGTH 37.425 LUMPCC 0.0002371632 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 95.965 55.080 +*I mux_right_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 124.760 50.660 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 124.723 50.660 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 123.740 50.660 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 123.740 49.640 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 103.085 49.640 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 103.040 49.685 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 103.040 55.375 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 102.995 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 99.360 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 99.360 55.080 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 96.002 55.080 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.54042e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001360042 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001394492 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001333892 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003423457 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003423457 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001977886 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002229599 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002642088 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002390375 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 optlc_net_124:38 0.0001185816 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 optlc_net_124:37 0.0001185816 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01844197 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.005080357 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002997768 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0003035715 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.003245536 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0009107144 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008772322 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002545599 //LENGTH 22.680 LUMPCC 0.0002505974 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_2_:X O *L 0 *C 23.635 52.360 +*I mux_left_track_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 22.905 30.940 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.905 30.940 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 23.000 30.985 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.000 52.315 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 23.045 52.360 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 23.598 52.360 + +*CAP +0 mux_left_track_9\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.807562e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001065225 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001065225 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.723776e-05 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.723776e-05 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[14]:12 6.478877e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_right_in[14]:13 1.333349e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_right_in[14]:5 1.333349e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_right_in[14]:13 6.478877e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.717645e-05 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.717645e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_2_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_9\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.01904464 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004933036 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006553995 //LENGTH 5.545 LUMPCC 0 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_0_:X O *L 0 *C 80.785 52.700 +*I mux_top_track_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 83.360 50.660 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 83.323 50.660 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 81.925 50.660 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 81.880 50.705 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 81.880 52.655 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 81.835 52.700 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 80.823 52.700 + +*CAP +0 mux_top_track_6\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001079391 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001079391 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001409403 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001409403 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.782038e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.782038e-05 + +*RES +0 mux_top_track_6\/mux_l1_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_6\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741072 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003928079 //LENGTH 2.535 LUMPCC 7.166214e-05 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_2_:X O *L 0 *C 96.315 61.880 +*I mux_right_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 94.300 61.540 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 94.338 61.540 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 96.140 61.540 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 96.315 61.880 + +*CAP +0 mux_right_track_24\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001195089 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001446628 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.497417e-05 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size7_4_sram[1]:9 3.583107e-05 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_4_sram[1]:4 3.583107e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_2_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_24\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001609375 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001576151 //LENGTH 11.510 LUMPCC 0.0006729758 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_1_:X O *L 0 *C 58.595 47.600 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 50.890 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 50.890 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 51.060 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 51.060 44.585 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 51.060 47.555 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 51.105 47.600 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 58.558 47.600 + +*CAP +0 mux_left_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.005491e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.048559e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001871478 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001871478 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002131696 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002131696 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[9]:19 0.0001368108 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[9]:20 0.0001368108 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[18]:17 7.222246e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[18]:18 7.222246e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_6_sram[0]:15 0.0001274547 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_6_sram[0]:14 0.0001274547 + +*RES +0 mux_left_track_25\/mux_l1_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006654018 + +*END + +*D_NET mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008045351 //LENGTH 6.000 LUMPCC 0 DR + +*CONN +*I mux_top_track_14\/mux_l1_in_1_:X O *L 0 *C 50.315 59.160 +*I mux_top_track_14\/mux_l2_in_0_:A0 I *L 0.001631 *C 49.970 64.260 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 49.970 64.260 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 50.140 64.260 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 50.140 64.215 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 50.140 59.205 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 50.140 59.160 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 50.315 59.160 + +*CAP +0 mux_top_track_14\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_14\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.137149e-05 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.494653e-05 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002900769 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002900769 +6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.904592e-05 +7 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.701739e-05 + +*RES +0 mux_top_track_14\/mux_l1_in_1_:X mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_14\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_14/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000920075 //LENGTH 7.805 LUMPCC 0.0001395505 DR + +*CONN +*I mux_top_track_22\/mux_l1_in_0_:X O *L 0 *C 86.765 33.660 +*I mux_top_track_22\/mux_l2_in_0_:A1 I *L 0.00198 *C 88.880 28.900 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 88.843 28.900 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 88.365 28.900 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 88.320 28.945 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 88.320 33.615 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 88.275 33.660 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 86.803 33.660 + +*CAP +0 mux_top_track_22\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_22\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.27166e-05 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.27166e-05 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002693631 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002693631 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.718253e-05 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.718253e-05 +8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[8]:19 6.977527e-05 +9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[8]:20 6.977527e-05 + +*RES +0 mux_top_track_22\/mux_l1_in_0_:X mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_22\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008562775 //LENGTH 6.355 LUMPCC 0.0001984262 DR + +*CONN +*I mux_top_track_34\/mux_l1_in_0_:X O *L 0 *C 44.445 91.800 +*I mux_top_track_34\/mux_l2_in_0_:A1 I *L 0.00198 *C 45.640 96.220 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 45.602 96.220 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 44.665 96.220 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 44.620 96.175 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 44.620 91.845 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 44.620 91.800 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 44.445 91.800 + +*CAP +0 mux_top_track_34\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_34\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.544298e-05 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.544298e-05 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000179341 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000179341 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.182655e-05 +7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.445666e-05 +8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[15]:12 5.610108e-05 +9 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[15]:11 5.610108e-05 +10 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[3]:4 4.311203e-05 +11 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[3]:5 4.311203e-05 + +*RES +0 mux_top_track_34\/mux_l1_in_0_:X mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_34\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003866072 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006989189 //LENGTH 4.920 LUMPCC 0.0002098664 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_3_:X O *L 0 *C 125.755 65.960 +*I mux_right_track_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 128.045 64.260 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 128.007 64.260 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 127.005 64.260 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 126.960 64.305 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 126.960 65.915 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 126.915 65.960 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 125.793 65.960 + +*CAP +0 mux_right_track_0\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.813164e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.813164e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001149944 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001149944 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.040026e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.040026e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 right_top_grid_pin_42_[0]:13 5.02748e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 right_top_grid_pin_42_[0]:14 5.02748e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size9_0_sram[1]:17 5.461507e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size9_0_sram[1]:15 5.461507e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:10 4.333674e-08 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:9 4.333674e-08 + +*RES +0 mux_right_track_0\/mux_l2_in_3_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001002232 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008950893 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_0\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0] 0.004159967 //LENGTH 37.935 LUMPCC 0.0007092234 DR + +*CONN +*I mux_right_track_2\/mux_l4_in_0_:X O *L 0 *C 106.545 82.280 +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 131.845 71.905 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 131.808 72.015 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 129.765 72.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 129.720 72.125 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 129.720 74.062 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 129.713 74.120 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 125.120 74.120 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 125.120 75.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 112.248 75.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 *C 112.240 75.538 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 *C 112.240 81.260 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 *C 111.780 81.260 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 *C 111.780 82.235 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:14 *C 111.735 82.280 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:15 *C 106.583 82.280 + +*CAP +0 mux_right_track_2\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001345274 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001345274 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001203323 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001203323 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0002565844 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0003332231 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0005948432 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0005182046 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0002009887 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.000227172 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 6.906674e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 4.288337e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:14 0.000348029 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:15 0.000348029 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 right_top_grid_pin_46_[0]:16 3.302863e-05 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 right_top_grid_pin_46_[0]:13 7.162052e-05 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 right_top_grid_pin_46_[0]:15 3.110606e-05 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 right_top_grid_pin_46_[0]:15 3.331763e-05 +20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 right_top_grid_pin_46_[0]:14 7.190951e-05 +21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 right_top_grid_pin_46_[0]:16 3.110606e-05 +22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_tree_tapbuf_size9_0_sram[3]:10 0.0002003965 +23 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size9_0_sram[3]:11 1.817103e-05 +24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_tree_tapbuf_size9_0_sram[3]:11 0.0002003965 +25 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size9_0_sram[3]:10 1.817103e-05 + +*RES +0 mux_right_track_2\/mux_l4_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:15 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:14 0.004600447 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.0008705358 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.00341 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.002016691 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.001729911 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.00341 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001823661 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0004107143 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.005109375 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0002130667 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0007194916 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006743785 //LENGTH 4.145 LUMPCC 0.0001366135 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_0_:X O *L 0 *C 73.885 72.420 +*I mux_right_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 77.740 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 77.703 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.922 72.420 + +*CAP +0 mux_right_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002678825 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002678825 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_0_sram[0]:12 6.830673e-05 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size6_0_sram[0]:13 6.830673e-05 + +*RES +0 mux_right_track_32\/mux_l1_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003375 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001535044 //LENGTH 12.625 LUMPCC 0.0001859609 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_1_:X O *L 0 *C 44.795 79.900 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 41.690 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 41.727 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 42.320 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 42.320 72.080 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 44.575 72.080 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 44.620 72.125 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 44.620 79.855 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 44.620 79.900 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 44.795 79.900 + +*CAP +0 mux_left_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.346458e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.601678e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002041633 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001616111 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003575204 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003575204 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 6.039038e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.639575e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[15]:4 2.479756e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[15]:11 6.81829e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[15]:11 2.479756e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[15]:12 6.81829e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002013393 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006901786 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.51087e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005290179 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006071429 + +*END + +*D_NET chanx_right_out[14] 0.002097623 //LENGTH 12.240 LUMPCC 0.001020035 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 131.100 25.500 +*P chanx_right_out[14] O *L 0.7423 *C 140.450 23.120 +*N chanx_right_out[14]:2 *C 131.108 23.120 +*N chanx_right_out[14]:3 *C 131.100 23.178 +*N chanx_right_out[14]:4 *C 131.100 25.455 +*N chanx_right_out[14]:5 *C 131.100 25.500 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 chanx_right_out[14] 0.000352986 +2 chanx_right_out[14]:2 0.000352986 +3 chanx_right_out[14]:3 0.0001690592 +4 chanx_right_out[14]:4 0.0001690592 +5 chanx_right_out[14]:5 3.249774e-05 +6 chanx_right_out[14] chanx_right_in[12] 2.046036e-06 +7 chanx_right_out[14] chanx_right_in[12]:29 0.0005079713 +8 chanx_right_out[14]:2 chanx_right_in[12]:28 0.0005079713 +9 chanx_right_out[14]:2 chanx_right_in[12]:32 2.046036e-06 + +*RES +0 ropt_mt_inst_781:X chanx_right_out[14]:5 0.152 +1 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +2 chanx_right_out[14]:2 chanx_right_out[14] 0.001463658 +3 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +4 chanx_right_out[14]:4 chanx_right_out[14]:3 0.002033482 + +*END + +*D_NET mux_top_track_20/BUF_net_62 0.0005267923 //LENGTH 4.185 LUMPCC 0 DR + +*CONN +*I mux_top_track_20\/BUFT_RR_62:X O *L 0 *C 89.015 99.620 +*I mux_top_track_20\/BUFT_P_101:A I *L 0.001767 *C 92.460 99.280 +*N mux_top_track_20/BUF_net_62:2 *C 92.460 99.280 +*N mux_top_track_20/BUF_net_62:3 *C 92.460 99.620 +*N mux_top_track_20/BUF_net_62:4 *C 89.053 99.620 + +*CAP +0 mux_top_track_20\/BUFT_RR_62:X 1e-06 +1 mux_top_track_20\/BUFT_P_101:A 1e-06 +2 mux_top_track_20/BUF_net_62:2 5.228751e-05 +3 mux_top_track_20/BUF_net_62:3 0.000249157 +4 mux_top_track_20/BUF_net_62:4 0.0002233479 + +*RES +0 mux_top_track_20\/BUFT_RR_62:X mux_top_track_20/BUF_net_62:4 0.152 +1 mux_top_track_20/BUF_net_62:2 mux_top_track_20\/BUFT_P_101:A 0.152 +2 mux_top_track_20/BUF_net_62:4 mux_top_track_20/BUF_net_62:3 0.003042411 +3 mux_top_track_20/BUF_net_62:3 mux_top_track_20/BUF_net_62:2 0.0003035715 + +*END + +*D_NET chanx_left_out[19] 0.001035456 //LENGTH 7.725 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 4.140 61.880 +*P chanx_left_out[19] O *L 0.7423 *C 1.230 58.480 +*N chanx_left_out[19]:2 *C 2.300 58.480 +*N chanx_left_out[19]:3 *C 2.300 59.148 +*N chanx_left_out[19]:4 *C 2.755 59.153 +*N chanx_left_out[19]:5 *C 2.760 59.218 +*N chanx_left_out[19]:6 *C 2.760 61.835 +*N chanx_left_out[19]:7 *C 2.805 61.880 +*N chanx_left_out[19]:8 *C 4.103 61.880 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 chanx_left_out[19] 8.76265e-05 +2 chanx_left_out[19]:2 0.00015036 +3 chanx_left_out[19]:3 0.0001538913 +4 chanx_left_out[19]:4 9.115782e-05 +5 chanx_left_out[19]:5 0.0001701798 +6 chanx_left_out[19]:6 0.0001701798 +7 chanx_left_out[19]:7 0.0001055302 +8 chanx_left_out[19]:8 0.0001055302 + +*RES +0 ropt_mt_inst_789:X chanx_left_out[19]:8 0.152 +1 chanx_left_out[19]:8 chanx_left_out[19]:7 0.001158482 +2 chanx_left_out[19]:7 chanx_left_out[19]:6 0.0045 +3 chanx_left_out[19]:6 chanx_left_out[19]:5 0.002337054 +4 chanx_left_out[19]:5 chanx_left_out[19]:4 0.00341 +5 chanx_left_out[19]:4 chanx_left_out[19]:3 6.788888e-05 +6 chanx_left_out[19]:2 chanx_left_out[19] 0.0001676333 +7 chanx_left_out[19]:3 chanx_left_out[19]:2 0.000104575 + +*END + +*D_NET chanx_right_out[10] 0.0007648221 //LENGTH 6.510 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 135.700 25.500 +*P chanx_right_out[10] O *L 0.7423 *C 140.375 24.480 +*N chanx_right_out[10]:2 *C 139.388 24.480 +*N chanx_right_out[10]:3 *C 139.380 24.538 +*N chanx_right_out[10]:4 *C 139.380 25.455 +*N chanx_right_out[10]:5 *C 139.335 25.500 +*N chanx_right_out[10]:6 *C 135.738 25.500 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 chanx_right_out[10] 8.013567e-05 +2 chanx_right_out[10]:2 8.013567e-05 +3 chanx_right_out[10]:3 6.988785e-05 +4 chanx_right_out[10]:4 6.988785e-05 +5 chanx_right_out[10]:5 0.0002318875 +6 chanx_right_out[10]:6 0.0002318875 + +*RES +0 ropt_mt_inst_796:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +2 chanx_right_out[10]:2 chanx_right_out[10] 0.0001547083 +3 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +4 chanx_right_out[10]:4 chanx_right_out[10]:3 0.0008191965 +5 chanx_right_out[10]:6 chanx_right_out[10]:5 0.003212054 + +*END + +*D_NET ropt_net_134 0.001715721 //LENGTH 16.610 LUMPCC 0 DR + +*CONN +*I BUFT_P_108:X O *L 0 *C 13.800 14.620 +*I ropt_mt_inst_757:A I *L 0.001766 *C 3.220 9.520 +*N ropt_net_134:2 *C 3.258 9.520 +*N ropt_net_134:3 *C 5.015 9.520 +*N ropt_net_134:4 *C 5.060 9.565 +*N ropt_net_134:5 *C 5.060 14.575 +*N ropt_net_134:6 *C 5.105 14.620 +*N ropt_net_134:7 *C 13.763 14.620 + +*CAP +0 BUFT_P_108:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_134:2 0.0001119148 +3 ropt_net_134:3 0.0001119148 +4 ropt_net_134:4 0.0002831187 +5 ropt_net_134:5 0.0002831187 +6 ropt_net_134:6 0.0004618268 +7 ropt_net_134:7 0.0004618268 + +*RES +0 BUFT_P_108:X ropt_net_134:7 0.152 +1 ropt_net_134:7 ropt_net_134:6 0.007729911 +2 ropt_net_134:6 ropt_net_134:5 0.0045 +3 ropt_net_134:5 ropt_net_134:4 0.004473215 +4 ropt_net_134:3 ropt_net_134:2 0.001569196 +5 ropt_net_134:4 ropt_net_134:3 0.0045 +6 ropt_net_134:2 ropt_mt_inst_757:A 0.152 + +*END + +*D_NET chanx_right_in[5] 0.02614345 //LENGTH 224.750 LUMPCC 0.005038457 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 140.450 9.520 +*I mux_top_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 77.645 50.660 +*I mux_left_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 41.690 55.420 +*I ropt_mt_inst_751:A I *L 0.001767 *C 3.220 28.560 +*N chanx_right_in[5]:4 *C 3.258 28.560 +*N chanx_right_in[5]:5 *C 4.555 28.560 +*N chanx_right_in[5]:6 *C 4.600 28.515 +*N chanx_right_in[5]:7 *C 4.600 23.845 +*N chanx_right_in[5]:8 *C 4.645 23.800 +*N chanx_right_in[5]:9 *C 28.935 23.800 +*N chanx_right_in[5]:10 *C 28.980 23.755 +*N chanx_right_in[5]:11 *C 28.980 23.178 +*N chanx_right_in[5]:12 *C 28.988 23.120 +*N chanx_right_in[5]:13 *C 44.140 23.120 +*N chanx_right_in[5]:14 *C 44.160 23.128 +*N chanx_right_in[5]:15 *C 44.160 49.633 +*N chanx_right_in[5]:16 *C 44.180 49.640 +*N chanx_right_in[5]:17 *C 41.727 55.420 +*N chanx_right_in[5]:18 *C 46.415 55.420 +*N chanx_right_in[5]:19 *C 46.460 55.375 +*N chanx_right_in[5]:20 *C 46.460 49.698 +*N chanx_right_in[5]:21 *C 46.460 49.640 +*N chanx_right_in[5]:22 *C 77.645 50.660 +*N chanx_right_in[5]:23 *C 77.740 50.615 +*N chanx_right_in[5]:24 *C 77.740 49.698 +*N chanx_right_in[5]:25 *C 77.740 49.640 +*N chanx_right_in[5]:26 *C 79.100 49.640 +*N chanx_right_in[5]:27 *C 79.120 49.633 +*N chanx_right_in[5]:28 *C 79.120 9.527 +*N chanx_right_in[5]:29 *C 79.140 9.520 +*N chanx_right_in[5]:30 *C 128.930 9.520 + +*CAP +0 chanx_right_in[5] 0.0004387553 +1 mux_top_track_4\/mux_l1_in_2_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_1_:A0 1e-06 +3 ropt_mt_inst_751:A 1e-06 +4 chanx_right_in[5]:4 9.558818e-05 +5 chanx_right_in[5]:5 9.558818e-05 +6 chanx_right_in[5]:6 0.000252141 +7 chanx_right_in[5]:7 0.000252141 +8 chanx_right_in[5]:8 0.001306885 +9 chanx_right_in[5]:9 0.001306885 +10 chanx_right_in[5]:10 4.466637e-05 +11 chanx_right_in[5]:11 4.466637e-05 +12 chanx_right_in[5]:12 0.0006974934 +13 chanx_right_in[5]:13 0.0006974934 +14 chanx_right_in[5]:14 0.00147823 +15 chanx_right_in[5]:15 0.00147823 +16 chanx_right_in[5]:16 0.0001294248 +17 chanx_right_in[5]:17 0.0004020647 +18 chanx_right_in[5]:18 0.0004020647 +19 chanx_right_in[5]:19 0.0003376332 +20 chanx_right_in[5]:20 0.0003376332 +21 chanx_right_in[5]:21 0.001627029 +22 chanx_right_in[5]:22 2.908279e-05 +23 chanx_right_in[5]:23 7.481533e-05 +24 chanx_right_in[5]:24 7.481533e-05 +25 chanx_right_in[5]:25 0.001570916 +26 chanx_right_in[5]:26 7.3312e-05 +27 chanx_right_in[5]:27 0.002264556 +28 chanx_right_in[5]:28 0.002264556 +29 chanx_right_in[5]:29 0.001443284 +30 chanx_right_in[5]:30 0.00188204 +31 chanx_right_in[5] chanx_right_in[2] 0.0001427706 +32 chanx_right_in[5]:15 chanx_right_in[2]:25 8.938641e-05 +33 chanx_right_in[5]:14 chanx_right_in[2]:26 8.938641e-05 +34 chanx_right_in[5]:29 chanx_right_in[2]:27 0.0002643997 +35 chanx_right_in[5]:29 chanx_right_in[2]:28 0.0003960979 +36 chanx_right_in[5]:30 chanx_right_in[2] 0.0003960979 +37 chanx_right_in[5]:30 chanx_right_in[2]:28 0.0004071703 +38 chanx_right_in[5]:21 chanx_right_in[13]:33 0.0003708091 +39 chanx_right_in[5]:25 chanx_right_in[13]:33 3.473664e-05 +40 chanx_right_in[5]:25 chanx_right_in[13]:34 0.0003708091 +41 chanx_right_in[5]:26 chanx_right_in[13]:34 3.473664e-05 +42 chanx_right_in[5] chanx_right_in[16] 3.734316e-05 +43 chanx_right_in[5]:29 chanx_right_in[16]:24 0.0001944671 +44 chanx_right_in[5]:29 chanx_right_in[16]:25 7.719901e-05 +45 chanx_right_in[5]:30 chanx_right_in[16] 7.719901e-05 +46 chanx_right_in[5]:30 chanx_right_in[16]:25 0.0002318103 +47 chanx_right_in[5]:21 chanx_left_in[6] 7.723665e-05 +48 chanx_right_in[5]:21 chanx_left_in[6]:20 0.0003167471 +49 chanx_right_in[5]:16 chanx_left_in[6] 3.277589e-05 +50 chanx_right_in[5]:25 chanx_left_in[6]:19 0.0002839712 +51 chanx_right_in[5]:25 chanx_left_in[6]:20 8.046925e-05 +52 chanx_right_in[5]:26 chanx_left_in[6]:19 3.2326e-06 +53 chanx_right_in[5]:13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001876018 +54 chanx_right_in[5]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.077105e-06 +55 chanx_right_in[5]:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001876018 +56 chanx_right_in[5]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002591126 +57 chanx_right_in[5]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.077105e-06 +58 chanx_right_in[5]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002591126 +59 chanx_right_in[5]:7 ropt_net_133:4 6.501078e-05 +60 chanx_right_in[5]:6 ropt_net_133:5 6.501078e-05 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:30 0.0018048 +1 chanx_right_in[5]:20 chanx_right_in[5]:19 0.005069197 +2 chanx_right_in[5]:21 chanx_right_in[5]:20 0.00341 +3 chanx_right_in[5]:21 chanx_right_in[5]:16 0.0003572 +4 chanx_right_in[5]:18 chanx_right_in[5]:17 0.004185268 +5 chanx_right_in[5]:19 chanx_right_in[5]:18 0.0045 +6 chanx_right_in[5]:17 mux_left_track_5\/mux_l1_in_1_:A0 0.152 +7 chanx_right_in[5]:16 chanx_right_in[5]:15 0.00341 +8 chanx_right_in[5]:15 chanx_right_in[5]:14 0.00415245 +9 chanx_right_in[5]:13 chanx_right_in[5]:12 0.002373892 +10 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00341 +11 chanx_right_in[5]:11 chanx_right_in[5]:10 0.0005156251 +12 chanx_right_in[5]:12 chanx_right_in[5]:11 0.00341 +13 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0216875 +14 chanx_right_in[5]:10 chanx_right_in[5]:9 0.0045 +15 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0045 +16 chanx_right_in[5]:7 chanx_right_in[5]:6 0.004169643 +17 chanx_right_in[5]:5 chanx_right_in[5]:4 0.001158482 +18 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +19 chanx_right_in[5]:4 ropt_mt_inst_751:A 0.152 +20 chanx_right_in[5]:24 chanx_right_in[5]:23 0.0008191965 +21 chanx_right_in[5]:25 chanx_right_in[5]:24 0.00341 +22 chanx_right_in[5]:25 chanx_right_in[5]:21 0.004900533 +23 chanx_right_in[5]:22 mux_top_track_4\/mux_l1_in_2_:A1 0.152 +24 chanx_right_in[5]:23 chanx_right_in[5]:22 0.0045 +25 chanx_right_in[5]:26 chanx_right_in[5]:25 0.0002130667 +26 chanx_right_in[5]:27 chanx_right_in[5]:26 0.00341 +27 chanx_right_in[5]:29 chanx_right_in[5]:28 0.00341 +28 chanx_right_in[5]:28 chanx_right_in[5]:27 0.006283116 +29 chanx_right_in[5]:30 chanx_right_in[5]:29 0.007800432 + +*END + +*D_NET chanx_left_in[17] 0.01623408 //LENGTH 145.190 LUMPCC 0.001909042 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 19.040 +*I mux_top_track_22\/mux_l1_in_1_:A1 I *L 0.00198 *C 81.980 28.900 +*I mux_right_track_16\/mux_l1_in_3_:A1 I *L 0.00198 *C 106.165 25.500 +*I BUFT_RR_76:A I *L 0.001776 *C 125.120 20.400 +*N chanx_left_in[17]:4 *C 125.120 20.400 +*N chanx_left_in[17]:5 *C 125.120 20.740 +*N chanx_left_in[17]:6 *C 106.260 20.740 +*N chanx_left_in[17]:7 *C 106.165 25.500 +*N chanx_left_in[17]:8 *C 106.260 25.455 +*N chanx_left_in[17]:9 *C 106.260 21.125 +*N chanx_left_in[17]:10 *C 106.260 21.050 +*N chanx_left_in[17]:11 *C 82.017 28.900 +*N chanx_left_in[17]:12 *C 85.975 28.900 +*N chanx_left_in[17]:13 *C 86.020 28.855 +*N chanx_left_in[17]:14 *C 86.020 21.125 +*N chanx_left_in[17]:15 *C 86.020 21.080 +*N chanx_left_in[17]:16 *C 40.525 21.080 +*N chanx_left_in[17]:17 *C 40.480 21.035 +*N chanx_left_in[17]:18 *C 40.480 19.098 +*N chanx_left_in[17]:19 *C 40.473 19.040 + +*CAP +0 chanx_left_in[17] 0.001847766 +1 mux_top_track_22\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_16\/mux_l1_in_3_:A1 1e-06 +3 BUFT_RR_76:A 1e-06 +4 chanx_left_in[17]:4 5.101095e-05 +5 chanx_left_in[17]:5 0.0009777531 +6 chanx_left_in[17]:6 0.00097844 +7 chanx_left_in[17]:7 2.640531e-05 +8 chanx_left_in[17]:8 0.0002281253 +9 chanx_left_in[17]:9 0.0002281253 +10 chanx_left_in[17]:10 0.001054096 +11 chanx_left_in[17]:11 0.0002269252 +12 chanx_left_in[17]:12 0.0002269252 +13 chanx_left_in[17]:13 0.0004056866 +14 chanx_left_in[17]:14 0.0004056866 +15 chanx_left_in[17]:15 0.003322761 +16 chanx_left_in[17]:16 0.002266967 +17 chanx_left_in[17]:17 0.0001137964 +18 chanx_left_in[17]:18 0.0001137964 +19 chanx_left_in[17]:19 0.001847766 +20 chanx_left_in[17]:16 chanx_right_in[8]:19 0.0005513985 +21 chanx_left_in[17]:10 chanx_right_in[8]:20 0.000239372 +22 chanx_left_in[17]:15 chanx_right_in[8]:19 0.000239372 +23 chanx_left_in[17]:15 chanx_right_in[8]:20 0.0005513985 +24 chanx_left_in[17] mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001159484 +25 chanx_left_in[17]:19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001159484 +26 chanx_left_in[17]:12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.780225e-05 +27 chanx_left_in[17]:11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.780225e-05 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:19 0.006147991 +1 chanx_left_in[17]:16 chanx_left_in[17]:15 0.04062054 +2 chanx_left_in[17]:17 chanx_left_in[17]:16 0.0045 +3 chanx_left_in[17]:18 chanx_left_in[17]:17 0.001729911 +4 chanx_left_in[17]:19 chanx_left_in[17]:18 0.00341 +5 chanx_left_in[17]:4 BUFT_RR_76:A 0.152 +6 chanx_left_in[17]:10 chanx_left_in[17]:9 0.0045 +7 chanx_left_in[17]:10 chanx_left_in[17]:6 0.0002767858 +8 chanx_left_in[17]:9 chanx_left_in[17]:8 0.003866072 +9 chanx_left_in[17]:7 mux_right_track_16\/mux_l1_in_3_:A1 0.152 +10 chanx_left_in[17]:8 chanx_left_in[17]:7 0.0045 +11 chanx_left_in[17]:15 chanx_left_in[17]:14 0.0045 +12 chanx_left_in[17]:15 chanx_left_in[17]:10 0.01807143 +13 chanx_left_in[17]:14 chanx_left_in[17]:13 0.006901786 +14 chanx_left_in[17]:12 chanx_left_in[17]:11 0.003533482 +15 chanx_left_in[17]:13 chanx_left_in[17]:12 0.0045 +16 chanx_left_in[17]:11 mux_top_track_22\/mux_l1_in_1_:A1 0.152 +17 chanx_left_in[17]:6 chanx_left_in[17]:5 0.01683929 +18 chanx_left_in[17]:5 chanx_left_in[17]:4 0.0003035715 + +*END + +*D_NET chany_top_in[0] 0.003773393 //LENGTH 28.375 LUMPCC 0 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 80.500 102.070 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.505 88.740 +*I mux_right_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 86.120 90.780 +*N chany_top_in[0]:3 *C 86.020 90.780 +*N chany_top_in[0]:4 *C 86.020 90.825 +*N chany_top_in[0]:5 *C 86.020 91.743 +*N chany_top_in[0]:6 *C 86.013 91.800 +*N chany_top_in[0]:7 *C 73.543 88.740 +*N chany_top_in[0]:8 *C 78.155 88.740 +*N chany_top_in[0]:9 *C 78.200 88.785 +*N chany_top_in[0]:10 *C 78.200 91.743 +*N chany_top_in[0]:11 *C 78.208 91.800 +*N chany_top_in[0]:12 *C 80.500 91.800 +*N chany_top_in[0]:13 *C 80.500 91.858 + +*CAP +0 chany_top_in[0] 0.0005689756 +1 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[0]:3 3.346755e-05 +4 chany_top_in[0]:4 7.78348e-05 +5 chany_top_in[0]:5 7.78348e-05 +6 chany_top_in[0]:6 0.0004492492 +7 chany_top_in[0]:7 0.0003613489 +8 chany_top_in[0]:8 0.0003613489 +9 chany_top_in[0]:9 0.0001818601 +10 chany_top_in[0]:10 0.0001818601 +11 chany_top_in[0]:11 0.0002296941 +12 chany_top_in[0]:12 0.0006789434 +13 chany_top_in[0]:13 0.0005689756 + +*RES +0 chany_top_in[0] chany_top_in[0]:13 0.009118304 +1 chany_top_in[0]:5 chany_top_in[0]:4 0.0008191965 +2 chany_top_in[0]:6 chany_top_in[0]:5 0.00341 +3 chany_top_in[0]:3 mux_right_track_2\/mux_l1_in_0_:A1 0.152 +4 chany_top_in[0]:4 chany_top_in[0]:3 0.0045 +5 chany_top_in[0]:10 chany_top_in[0]:9 0.002640625 +6 chany_top_in[0]:11 chany_top_in[0]:10 0.00341 +7 chany_top_in[0]:8 chany_top_in[0]:7 0.004118304 +8 chany_top_in[0]:9 chany_top_in[0]:8 0.0045 +9 chany_top_in[0]:7 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +10 chany_top_in[0]:13 chany_top_in[0]:12 0.00341 +11 chany_top_in[0]:12 chany_top_in[0]:11 0.0003591583 +12 chany_top_in[0]:12 chany_top_in[0]:6 0.000863625 + +*END + +*D_NET chany_top_in[5] 0.01093645 //LENGTH 69.115 LUMPCC 0.004679553 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 60.260 102.070 +*I mux_right_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 71.760 72.420 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.305 66.980 +*N chany_top_in[5]:3 *C 41.343 66.980 +*N chany_top_in[5]:4 *C 42.735 66.980 +*N chany_top_in[5]:5 *C 42.780 67.025 +*N chany_top_in[5]:6 *C 42.780 72.023 +*N chany_top_in[5]:7 *C 42.788 72.080 +*N chany_top_in[5]:8 *C 61.172 72.080 +*N chany_top_in[5]:9 *C 71.722 72.420 +*N chany_top_in[5]:10 *C 69.000 72.420 +*N chany_top_in[5]:11 *C 69.000 72.080 +*N chany_top_in[5]:12 *C 61.225 72.080 +*N chany_top_in[5]:13 *C 61.180 72.080 +*N chany_top_in[5]:14 *C 61.180 72.760 +*N chany_top_in[5]:15 *C 60.720 72.760 +*N chany_top_in[5]:16 *C 60.720 75.480 +*N chany_top_in[5]:17 *C 60.260 75.480 + +*CAP +0 chany_top_in[5] 0.001284421 +1 mux_right_track_32\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[5]:3 0.0001176814 +4 chany_top_in[5]:4 0.0001176814 +5 chany_top_in[5]:5 0.0002437135 +6 chany_top_in[5]:6 0.0002437135 +7 chany_top_in[5]:7 0.0005059539 +8 chany_top_in[5]:8 0.0005059539 +9 chany_top_in[5]:9 0.0001847386 +10 chany_top_in[5]:10 0.000211283 +11 chany_top_in[5]:11 0.0005218234 +12 chany_top_in[5]:12 0.000495279 +13 chany_top_in[5]:13 8.062345e-05 +14 chany_top_in[5]:14 8.344902e-05 +15 chany_top_in[5]:15 0.0001736216 +16 chany_top_in[5]:16 0.0001709804 +17 chany_top_in[5]:17 0.00131398 +18 chany_top_in[5]:7 chanx_left_in[9]:25 0.0009829288 +19 chany_top_in[5]:8 chanx_left_in[9]:24 0.0009829288 +20 chany_top_in[5] prog_clk[0]:175 2.068575e-05 +21 chany_top_in[5] prog_clk[0]:181 2.098906e-05 +22 chany_top_in[5] prog_clk[0]:339 0.0001859833 +23 chany_top_in[5]:13 prog_clk[0]:337 1.233031e-06 +24 chany_top_in[5]:17 prog_clk[0]:174 2.068575e-05 +25 chany_top_in[5]:17 prog_clk[0]:178 2.098906e-05 +26 chany_top_in[5]:17 prog_clk[0]:338 0.0001891043 +27 chany_top_in[5]:16 prog_clk[0]:323 3.120997e-06 +28 chany_top_in[5]:16 prog_clk[0]:338 1.630857e-05 +29 chany_top_in[5]:16 prog_clk[0]:339 5.796884e-06 +30 chany_top_in[5]:15 prog_clk[0]:337 1.630857e-05 +31 chany_top_in[5]:15 prog_clk[0]:338 5.796884e-06 +32 chany_top_in[5]:14 prog_clk[0]:338 1.233031e-06 +33 chany_top_in[5]:9 chany_top_in[12]:3 8.211591e-06 +34 chany_top_in[5]:12 chany_top_in[12]:14 5.095994e-06 +35 chany_top_in[5]:3 chany_top_in[12]:7 1.792706e-05 +36 chany_top_in[5]:4 chany_top_in[12]:8 1.792706e-05 +37 chany_top_in[5]:5 chany_top_in[12]:9 5.940588e-06 +38 chany_top_in[5]:5 chany_top_in[12]:11 5.113077e-05 +39 chany_top_in[5]:6 chany_top_in[12]:12 5.113077e-05 +40 chany_top_in[5]:6 chany_top_in[12]:10 5.940588e-06 +41 chany_top_in[5]:7 chany_top_in[12]:13 8.233782e-05 +42 chany_top_in[5]:7 chany_top_in[12]:14 0.0008637732 +43 chany_top_in[5]:8 chany_top_in[12]:6 0.0008637732 +44 chany_top_in[5]:8 chany_top_in[12]:14 8.233782e-05 +45 chany_top_in[5]:11 chany_top_in[12]:6 5.095994e-06 +46 chany_top_in[5]:10 chany_top_in[12]:4 8.211591e-06 +47 chany_top_in[5]:12 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 5.291809e-05 +48 chany_top_in[5]:13 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 6.007679e-06 +49 chany_top_in[5]:11 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 5.291809e-05 +50 chany_top_in[5]:16 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 9.387103e-06 +51 chany_top_in[5]:15 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 9.387103e-06 +52 chany_top_in[5]:14 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 6.007679e-06 + +*RES +0 chany_top_in[5] chany_top_in[5]:17 0.02374107 +1 chany_top_in[5]:9 mux_right_track_32\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[5]:12 chany_top_in[5]:11 0.006941965 +3 chany_top_in[5]:13 chany_top_in[5]:12 0.0045 +4 chany_top_in[5]:13 chany_top_in[5]:8 0.00341 +5 chany_top_in[5]:3 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +6 chany_top_in[5]:4 chany_top_in[5]:3 0.001243304 +7 chany_top_in[5]:5 chany_top_in[5]:4 0.0045 +8 chany_top_in[5]:6 chany_top_in[5]:5 0.004462054 +9 chany_top_in[5]:7 chany_top_in[5]:6 0.00341 +10 chany_top_in[5]:8 chany_top_in[5]:7 0.002880316 +11 chany_top_in[5]:11 chany_top_in[5]:10 0.0003035715 +12 chany_top_in[5]:10 chany_top_in[5]:9 0.002430804 +13 chany_top_in[5]:17 chany_top_in[5]:16 0.0004107143 +14 chany_top_in[5]:16 chany_top_in[5]:15 0.002428572 +15 chany_top_in[5]:15 chany_top_in[5]:14 0.0004107143 +16 chany_top_in[5]:14 chany_top_in[5]:13 0.0006071429 + +*END + +*D_NET chany_top_in[15] 0.01677129 //LENGTH 113.970 LUMPCC 0.005661692 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 53.820 102.035 +*I mux_right_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 102.120 66.980 +*I mux_left_track_33\/mux_l1_in_1_:A1 I *L 0.00198 *C 45.445 61.540 +*N chany_top_in[15]:3 *C 45.445 61.540 +*N chany_top_in[15]:4 *C 45.540 61.585 +*N chany_top_in[15]:5 *C 102.120 66.980 +*N chany_top_in[15]:6 *C 102.120 67.025 +*N chany_top_in[15]:7 *C 102.120 74.062 +*N chany_top_in[15]:8 *C 102.113 74.120 +*N chany_top_in[15]:9 *C 95.375 74.120 +*N chany_top_in[15]:10 *C 45.547 74.120 +*N chany_top_in[15]:11 *C 45.540 74.120 +*N chany_top_in[15]:12 *C 45.540 101.615 +*N chany_top_in[15]:13 *C 45.585 101.660 +*N chany_top_in[15]:14 *C 53.775 101.660 +*N chany_top_in[15]:15 *C 53.820 101.705 + +*CAP +0 chany_top_in[15] 3.459608e-05 +1 mux_right_track_4\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_33\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[15]:3 2.909335e-05 +4 chany_top_in[15]:4 0.0007445997 +5 chany_top_in[15]:5 3.193846e-05 +6 chany_top_in[15]:6 0.0004709233 +7 chany_top_in[15]:7 0.0004709233 +8 chany_top_in[15]:8 0.0002925807 +9 chany_top_in[15]:9 0.002685316 +10 chany_top_in[15]:10 0.002392735 +11 chany_top_in[15]:11 0.001883772 +12 chany_top_in[15]:12 0.001100191 +13 chany_top_in[15]:13 0.0004681669 +14 chany_top_in[15]:14 0.0004681669 +15 chany_top_in[15]:15 3.459608e-05 +16 chany_top_in[15]:10 chanx_left_in[9]:24 0.0002244989 +17 chany_top_in[15]:10 chanx_left_in[9]:25 0.0006580931 +18 chany_top_in[15]:9 chanx_left_in[9]:23 0.0002244989 +19 chany_top_in[15]:9 chanx_left_in[9]:24 0.0006580931 +20 chany_top_in[15]:10 right_top_grid_pin_45_[0]:13 0.000631232 +21 chany_top_in[15]:7 right_top_grid_pin_45_[0]:15 1.35533e-06 +22 chany_top_in[15]:8 right_top_grid_pin_45_[0]:14 0.0002317292 +23 chany_top_in[15]:6 right_top_grid_pin_45_[0]:16 1.35533e-06 +24 chany_top_in[15]:9 right_top_grid_pin_45_[0]:14 0.000631232 +25 chany_top_in[15]:9 right_top_grid_pin_45_[0]:13 0.0002317292 +26 chany_top_in[15]:10 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 1.931847e-05 +27 chany_top_in[15]:8 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 7.100531e-05 +28 chany_top_in[15]:9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 1.931847e-05 +29 chany_top_in[15]:9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 7.100531e-05 +30 chany_top_in[15]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0003125387 +31 chany_top_in[15]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0003125387 +32 chany_top_in[15]:12 optlc_net_125:11 0.00014958 +33 chany_top_in[15]:12 optlc_net_125:15 1.370254e-06 +34 chany_top_in[15]:12 optlc_net_125:8 0.0002796927 +35 chany_top_in[15]:12 optlc_net_125:19 9.110117e-05 +36 chany_top_in[15]:11 optlc_net_125:11 0.0002796927 +37 chany_top_in[15]:11 optlc_net_125:18 9.110117e-05 +38 chany_top_in[15]:11 optlc_net_125:15 1.024859e-05 +39 chany_top_in[15]:11 optlc_net_125:14 1.370254e-06 +40 chany_top_in[15]:11 optlc_net_125:19 0.00014958 +41 chany_top_in[15]:4 optlc_net_125:14 1.024859e-05 +42 chany_top_in[15]:12 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.610108e-05 +43 chany_top_in[15]:11 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.610108e-05 +44 chany_top_in[15]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.81829e-05 +45 chany_top_in[15]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.81829e-05 +46 chany_top_in[15]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.479756e-05 +47 chany_top_in[15]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.479756e-05 + +*RES +0 chany_top_in[15] chany_top_in[15]:15 0.0002946429 +1 chany_top_in[15]:14 chany_top_in[15]:13 0.0073125 +2 chany_top_in[15]:15 chany_top_in[15]:14 0.0045 +3 chany_top_in[15]:13 chany_top_in[15]:12 0.0045 +4 chany_top_in[15]:12 chany_top_in[15]:11 0.02454911 +5 chany_top_in[15]:11 chany_top_in[15]:10 0.00341 +6 chany_top_in[15]:11 chany_top_in[15]:4 0.01119197 +7 chany_top_in[15]:10 chany_top_in[15]:9 0.007806308 +8 chany_top_in[15]:7 chany_top_in[15]:6 0.006283483 +9 chany_top_in[15]:8 chany_top_in[15]:7 0.00341 +10 chany_top_in[15]:5 mux_right_track_4\/mux_l1_in_1_:A1 0.152 +11 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +12 chany_top_in[15]:3 mux_left_track_33\/mux_l1_in_1_:A1 0.152 +13 chany_top_in[15]:4 chany_top_in[15]:3 0.0045 +14 chany_top_in[15]:9 chany_top_in[15]:8 0.001055542 + +*END + +*D_NET top_left_grid_pin_40_[0] 0.01178213 //LENGTH 94.910 LUMPCC 0.0001719669 DR + +*CONN +*P top_left_grid_pin_40_[0] I *L 0.29796 *C 29.818 95.200 +*I mux_top_track_36\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.300 94.180 +*I mux_top_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.255 53.380 +*I mux_top_track_20\/mux_l1_in_0_:A1 I *L 0.00198 *C 66.800 41.820 +*I mux_top_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 57.500 66.980 +*N top_left_grid_pin_40_[0]:5 *C 57.500 66.980 +*N top_left_grid_pin_40_[0]:6 *C 66.700 41.820 +*N top_left_grid_pin_40_[0]:7 *C 66.700 41.865 +*N top_left_grid_pin_40_[0]:8 *C 68.218 53.380 +*N top_left_grid_pin_40_[0]:9 *C 66.745 53.380 +*N top_left_grid_pin_40_[0]:10 *C 66.700 53.380 +*N top_left_grid_pin_40_[0]:11 *C 66.700 67.275 +*N top_left_grid_pin_40_[0]:12 *C 66.655 67.320 +*N top_left_grid_pin_40_[0]:13 *C 57.500 67.320 +*N top_left_grid_pin_40_[0]:14 *C 56.625 67.320 +*N top_left_grid_pin_40_[0]:15 *C 56.580 67.365 +*N top_left_grid_pin_40_[0]:16 *C 56.580 71.740 +*N top_left_grid_pin_40_[0]:17 *C 55.200 71.740 +*N top_left_grid_pin_40_[0]:18 *C 55.200 94.135 +*N top_left_grid_pin_40_[0]:19 *C 55.200 94.180 +*N top_left_grid_pin_40_[0]:20 *C 55.200 94.520 +*N top_left_grid_pin_40_[0]:21 *C 29.945 94.520 +*N top_left_grid_pin_40_[0]:22 *C 29.900 94.565 +*N top_left_grid_pin_40_[0]:23 *C 29.900 95.142 +*N top_left_grid_pin_40_[0]:24 *C 29.900 95.200 + +*CAP +0 top_left_grid_pin_40_[0] 2.998387e-05 +1 mux_top_track_36\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_20\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_0\/mux_l2_in_1_:A1 1e-06 +5 top_left_grid_pin_40_[0]:5 6.3644e-05 +6 top_left_grid_pin_40_[0]:6 3.596828e-05 +7 top_left_grid_pin_40_[0]:7 0.0007157268 +8 top_left_grid_pin_40_[0]:8 0.0001584485 +9 top_left_grid_pin_40_[0]:9 0.0001584485 +10 top_left_grid_pin_40_[0]:10 0.001558888 +11 top_left_grid_pin_40_[0]:11 0.0008114983 +12 top_left_grid_pin_40_[0]:12 0.000645388 +13 top_left_grid_pin_40_[0]:13 0.0007486279 +14 top_left_grid_pin_40_[0]:14 7.293707e-05 +15 top_left_grid_pin_40_[0]:15 0.0002848078 +16 top_left_grid_pin_40_[0]:16 0.0003558829 +17 top_left_grid_pin_40_[0]:17 0.001262747 +18 top_left_grid_pin_40_[0]:18 0.001191672 +19 top_left_grid_pin_40_[0]:19 6.009004e-05 +20 top_left_grid_pin_40_[0]:20 0.001676723 +21 top_left_grid_pin_40_[0]:21 0.001648843 +22 top_left_grid_pin_40_[0]:22 4.792967e-05 +23 top_left_grid_pin_40_[0]:23 4.792967e-05 +24 top_left_grid_pin_40_[0]:24 2.998387e-05 +25 top_left_grid_pin_40_[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.643658e-05 +26 top_left_grid_pin_40_[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.572904e-06 +27 top_left_grid_pin_40_[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.973962e-06 +28 top_left_grid_pin_40_[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.643658e-05 +29 top_left_grid_pin_40_[0]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.973962e-06 +30 top_left_grid_pin_40_[0]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.572904e-06 + +*RES +0 top_left_grid_pin_40_[0] top_left_grid_pin_40_[0]:24 2.35e-05 +1 top_left_grid_pin_40_[0]:12 top_left_grid_pin_40_[0]:11 0.0045 +2 top_left_grid_pin_40_[0]:11 top_left_grid_pin_40_[0]:10 0.01240625 +3 top_left_grid_pin_40_[0]:6 mux_top_track_20\/mux_l1_in_0_:A1 0.152 +4 top_left_grid_pin_40_[0]:7 top_left_grid_pin_40_[0]:6 0.0045 +5 top_left_grid_pin_40_[0]:5 mux_top_track_0\/mux_l2_in_1_:A1 0.152 +6 top_left_grid_pin_40_[0]:9 top_left_grid_pin_40_[0]:8 0.001314732 +7 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:9 0.0045 +8 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:7 0.01028125 +9 top_left_grid_pin_40_[0]:8 mux_top_track_4\/mux_l1_in_1_:A0 0.152 +10 top_left_grid_pin_40_[0]:19 mux_top_track_36\/mux_l1_in_0_:A1 0.152 +11 top_left_grid_pin_40_[0]:19 top_left_grid_pin_40_[0]:18 0.0045 +12 top_left_grid_pin_40_[0]:18 top_left_grid_pin_40_[0]:17 0.01999554 +13 top_left_grid_pin_40_[0]:14 top_left_grid_pin_40_[0]:13 0.00078125 +14 top_left_grid_pin_40_[0]:15 top_left_grid_pin_40_[0]:14 0.0045 +15 top_left_grid_pin_40_[0]:21 top_left_grid_pin_40_[0]:20 0.02254911 +16 top_left_grid_pin_40_[0]:22 top_left_grid_pin_40_[0]:21 0.0045 +17 top_left_grid_pin_40_[0]:23 top_left_grid_pin_40_[0]:22 0.000515625 +18 top_left_grid_pin_40_[0]:24 top_left_grid_pin_40_[0]:23 0.00341 +19 top_left_grid_pin_40_[0]:20 top_left_grid_pin_40_[0]:19 0.0003035715 +20 top_left_grid_pin_40_[0]:13 top_left_grid_pin_40_[0]:12 0.008174107 +21 top_left_grid_pin_40_[0]:13 top_left_grid_pin_40_[0]:5 0.0003035715 +22 top_left_grid_pin_40_[0]:17 top_left_grid_pin_40_[0]:16 0.001232143 +23 top_left_grid_pin_40_[0]:16 top_left_grid_pin_40_[0]:15 0.00390625 + +*END + +*D_NET right_top_grid_pin_42_[0] 0.008172118 //LENGTH 59.180 LUMPCC 0.001018071 DR + +*CONN +*P right_top_grid_pin_42_[0] I *L 0.29796 *C 138.460 74.835 +*I mux_right_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 102.410 65.960 +*I mux_right_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 102.680 74.460 +*I mux_right_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 115.920 63.580 +*N right_top_grid_pin_42_[0]:4 *C 115.958 63.580 +*N right_top_grid_pin_42_[0]:5 *C 116.380 63.580 +*N right_top_grid_pin_42_[0]:6 *C 102.580 74.460 +*N right_top_grid_pin_42_[0]:7 *C 102.580 74.415 +*N right_top_grid_pin_42_[0]:8 *C 102.410 65.960 +*N right_top_grid_pin_42_[0]:9 *C 102.580 65.960 +*N right_top_grid_pin_42_[0]:10 *C 102.580 65.960 +*N right_top_grid_pin_42_[0]:11 *C 102.580 64.645 +*N right_top_grid_pin_42_[0]:12 *C 102.625 64.600 +*N right_top_grid_pin_42_[0]:13 *C 116.380 64.600 +*N right_top_grid_pin_42_[0]:14 *C 137.955 64.600 +*N right_top_grid_pin_42_[0]:15 *C 138.000 64.645 +*N right_top_grid_pin_42_[0]:16 *C 138.000 65.960 +*N right_top_grid_pin_42_[0]:17 *C 138.460 65.960 + +*CAP +0 right_top_grid_pin_42_[0] 0.0005444941 +1 mux_right_track_4\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:A1 1e-06 +3 mux_right_track_8\/mux_l2_in_1_:A1 1e-06 +4 right_top_grid_pin_42_[0]:4 3.51795e-05 +5 right_top_grid_pin_42_[0]:5 9.737405e-05 +6 right_top_grid_pin_42_[0]:6 3.368538e-05 +7 right_top_grid_pin_42_[0]:7 0.0004103431 +8 right_top_grid_pin_42_[0]:8 5.469064e-05 +9 right_top_grid_pin_42_[0]:9 5.630657e-05 +10 right_top_grid_pin_42_[0]:10 0.0005019003 +11 right_top_grid_pin_42_[0]:11 5.924634e-05 +12 right_top_grid_pin_42_[0]:12 0.0009686904 +13 right_top_grid_pin_42_[0]:13 0.002295078 +14 right_top_grid_pin_42_[0]:14 0.001264193 +15 right_top_grid_pin_42_[0]:15 0.0001131649 +16 right_top_grid_pin_42_[0]:16 0.0001426849 +17 right_top_grid_pin_42_[0]:17 0.0005740142 +18 right_top_grid_pin_42_[0] right_top_grid_pin_44_[0] 6.49116e-06 +19 right_top_grid_pin_42_[0]:7 right_top_grid_pin_44_[0]:10 9.712731e-05 +20 right_top_grid_pin_42_[0]:7 right_top_grid_pin_44_[0]:11 0.0001086454 +21 right_top_grid_pin_42_[0]:10 right_top_grid_pin_44_[0]:10 0.0001452567 +22 right_top_grid_pin_42_[0]:10 right_top_grid_pin_44_[0]:7 9.712731e-05 +23 right_top_grid_pin_42_[0]:12 right_top_grid_pin_44_[0]:5 2.875395e-05 +24 right_top_grid_pin_42_[0]:11 right_top_grid_pin_44_[0]:7 3.661129e-05 +25 right_top_grid_pin_42_[0]:13 right_top_grid_pin_44_[0]:6 2.875395e-05 +26 right_top_grid_pin_42_[0]:17 right_top_grid_pin_44_[0]:18 6.49116e-06 +27 right_top_grid_pin_42_[0]:14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001265402 +28 right_top_grid_pin_42_[0]:13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001265402 +29 right_top_grid_pin_42_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.02748e-05 +30 right_top_grid_pin_42_[0]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.02748e-05 +31 right_top_grid_pin_42_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.459169e-05 +32 right_top_grid_pin_42_[0]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.459169e-05 + +*RES +0 right_top_grid_pin_42_[0] right_top_grid_pin_42_[0]:17 0.007924107 +1 right_top_grid_pin_42_[0]:6 mux_right_track_0\/mux_l1_in_1_:A1 0.152 +2 right_top_grid_pin_42_[0]:7 right_top_grid_pin_42_[0]:6 0.0045 +3 right_top_grid_pin_42_[0]:9 right_top_grid_pin_42_[0]:8 9.239131e-05 +4 right_top_grid_pin_42_[0]:10 right_top_grid_pin_42_[0]:9 0.0045 +5 right_top_grid_pin_42_[0]:10 right_top_grid_pin_42_[0]:7 0.007549107 +6 right_top_grid_pin_42_[0]:8 mux_right_track_4\/mux_l1_in_1_:A0 0.152 +7 right_top_grid_pin_42_[0]:4 mux_right_track_8\/mux_l2_in_1_:A1 0.152 +8 right_top_grid_pin_42_[0]:14 right_top_grid_pin_42_[0]:13 0.01926339 +9 right_top_grid_pin_42_[0]:15 right_top_grid_pin_42_[0]:14 0.0045 +10 right_top_grid_pin_42_[0]:12 right_top_grid_pin_42_[0]:11 0.0045 +11 right_top_grid_pin_42_[0]:11 right_top_grid_pin_42_[0]:10 0.001174107 +12 right_top_grid_pin_42_[0]:13 right_top_grid_pin_42_[0]:12 0.01228125 +13 right_top_grid_pin_42_[0]:13 right_top_grid_pin_42_[0]:5 0.0009107144 +14 right_top_grid_pin_42_[0]:5 right_top_grid_pin_42_[0]:4 0.0003772322 +15 right_top_grid_pin_42_[0]:16 right_top_grid_pin_42_[0]:15 0.001174107 +16 right_top_grid_pin_42_[0]:17 right_top_grid_pin_42_[0]:16 0.0004107143 + +*END + +*D_NET left_top_grid_pin_44_[0] 0.01184355 //LENGTH 78.905 LUMPCC 0.004567183 DR + +*CONN +*P left_top_grid_pin_44_[0] I *L 0.29796 *C 4.140 74.870 +*I mux_left_track_5\/mux_l1_in_3_:A0 I *L 0.001631 *C 26.050 49.640 +*I mux_left_track_25\/mux_l1_in_2_:A0 I *L 0.001631 *C 37.435 48.280 +*I mux_left_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 37.435 69.700 +*N left_top_grid_pin_44_[0]:4 *C 37.398 69.700 +*N left_top_grid_pin_44_[0]:5 *C 36.845 69.700 +*N left_top_grid_pin_44_[0]:6 *C 36.800 69.745 +*N left_top_grid_pin_44_[0]:7 *C 36.800 73.383 +*N left_top_grid_pin_44_[0]:8 *C 37.398 48.280 +*N left_top_grid_pin_44_[0]:9 *C 36.385 48.280 +*N left_top_grid_pin_44_[0]:10 *C 36.340 48.325 +*N left_top_grid_pin_44_[0]:11 *C 26.050 49.640 +*N left_top_grid_pin_44_[0]:12 *C 25.760 49.640 +*N left_top_grid_pin_44_[0]:13 *C 25.760 49.640 +*N left_top_grid_pin_44_[0]:14 *C 25.768 49.640 +*N left_top_grid_pin_44_[0]:15 *C 36.333 49.640 +*N left_top_grid_pin_44_[0]:16 *C 36.340 49.640 +*N left_top_grid_pin_44_[0]:17 *C 36.340 55.023 +*N left_top_grid_pin_44_[0]:18 *C 36.343 55.080 +*N left_top_grid_pin_44_[0]:19 *C 36.785 55.080 +*N left_top_grid_pin_44_[0]:20 *C 36.800 55.088 +*N left_top_grid_pin_44_[0]:21 *C 36.800 73.433 +*N left_top_grid_pin_44_[0]:22 *C 36.793 73.440 +*N left_top_grid_pin_44_[0]:23 *C 4.147 73.440 +*N left_top_grid_pin_44_[0]:24 *C 4.140 73.498 + +*CAP +0 left_top_grid_pin_44_[0] 9.171471e-05 +1 mux_left_track_5\/mux_l1_in_3_:A0 1e-06 +2 mux_left_track_25\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_1\/mux_l2_in_1_:A0 1e-06 +4 left_top_grid_pin_44_[0]:4 7.505425e-05 +5 left_top_grid_pin_44_[0]:5 7.505425e-05 +6 left_top_grid_pin_44_[0]:6 0.0002050835 +7 left_top_grid_pin_44_[0]:7 0.0002050835 +8 left_top_grid_pin_44_[0]:8 0.0001062199 +9 left_top_grid_pin_44_[0]:9 0.0001062199 +10 left_top_grid_pin_44_[0]:10 9.237233e-05 +11 left_top_grid_pin_44_[0]:11 5.53917e-05 +12 left_top_grid_pin_44_[0]:12 5.714972e-05 +13 left_top_grid_pin_44_[0]:13 3.831782e-05 +14 left_top_grid_pin_44_[0]:14 0.0007717642 +15 left_top_grid_pin_44_[0]:15 0.0007717642 +16 left_top_grid_pin_44_[0]:16 0.000416098 +17 left_top_grid_pin_44_[0]:17 0.0002927596 +18 left_top_grid_pin_44_[0]:18 5.01284e-05 +19 left_top_grid_pin_44_[0]:19 5.01284e-05 +20 left_top_grid_pin_44_[0]:20 0.0009489036 +21 left_top_grid_pin_44_[0]:21 0.0009489036 +22 left_top_grid_pin_44_[0]:22 0.0009117703 +23 left_top_grid_pin_44_[0]:23 0.0009117703 +24 left_top_grid_pin_44_[0]:24 9.171471e-05 +25 left_top_grid_pin_44_[0]:22 chanx_left_in[9]:24 0.000286383 +26 left_top_grid_pin_44_[0]:23 chanx_left_in[9]:25 0.000286383 +27 left_top_grid_pin_44_[0]:22 chanx_left_in[1]:8 0.0007094895 +28 left_top_grid_pin_44_[0]:23 chanx_left_in[1]:9 0.0007094895 +29 left_top_grid_pin_44_[0]:22 chanx_left_in[7]:10 0.0003311016 +30 left_top_grid_pin_44_[0]:21 chanx_left_in[7]:8 4.83293e-05 +31 left_top_grid_pin_44_[0]:20 chanx_left_in[7]:9 4.83293e-05 +32 left_top_grid_pin_44_[0]:23 chanx_left_in[7]:11 0.0003311016 +33 left_top_grid_pin_44_[0]:22 left_top_grid_pin_42_[0]:22 0.0002243893 +34 left_top_grid_pin_44_[0]:21 left_top_grid_pin_42_[0]:17 5.746676e-05 +35 left_top_grid_pin_44_[0]:20 left_top_grid_pin_42_[0]:16 5.746676e-05 +36 left_top_grid_pin_44_[0]:23 left_top_grid_pin_42_[0]:23 0.0002243893 +37 left_top_grid_pin_44_[0]:15 left_top_grid_pin_48_[0]:10 7.436687e-06 +38 left_top_grid_pin_44_[0]:14 left_top_grid_pin_48_[0]:11 7.436687e-06 +39 left_top_grid_pin_44_[0]:22 left_top_grid_pin_48_[0]:28 0.000520076 +40 left_top_grid_pin_44_[0]:23 left_top_grid_pin_48_[0]:29 0.000520076 +41 left_top_grid_pin_44_[0]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.197489e-05 +42 left_top_grid_pin_44_[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.197489e-05 +43 left_top_grid_pin_44_[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.694418e-05 +44 left_top_grid_pin_44_[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.694418e-05 + +*RES +0 left_top_grid_pin_44_[0] left_top_grid_pin_44_[0]:24 0.001225446 +1 left_top_grid_pin_44_[0]:16 left_top_grid_pin_44_[0]:15 0.00341 +2 left_top_grid_pin_44_[0]:16 left_top_grid_pin_44_[0]:10 0.001174107 +3 left_top_grid_pin_44_[0]:15 left_top_grid_pin_44_[0]:14 0.001655183 +4 left_top_grid_pin_44_[0]:13 left_top_grid_pin_44_[0]:12 0.0045 +5 left_top_grid_pin_44_[0]:14 left_top_grid_pin_44_[0]:13 0.00341 +6 left_top_grid_pin_44_[0]:12 left_top_grid_pin_44_[0]:11 0.0001576087 +7 left_top_grid_pin_44_[0]:11 mux_left_track_5\/mux_l1_in_3_:A0 0.152 +8 left_top_grid_pin_44_[0]:22 left_top_grid_pin_44_[0]:21 0.00341 +9 left_top_grid_pin_44_[0]:22 left_top_grid_pin_44_[0]:7 0.00341 +10 left_top_grid_pin_44_[0]:21 left_top_grid_pin_44_[0]:20 0.00287405 +11 left_top_grid_pin_44_[0]:19 left_top_grid_pin_44_[0]:18 6.499219e-05 +12 left_top_grid_pin_44_[0]:20 left_top_grid_pin_44_[0]:19 0.00341 +13 left_top_grid_pin_44_[0]:17 left_top_grid_pin_44_[0]:16 0.004805804 +14 left_top_grid_pin_44_[0]:18 left_top_grid_pin_44_[0]:17 0.00341 +15 left_top_grid_pin_44_[0]:7 left_top_grid_pin_44_[0]:6 0.003247768 +16 left_top_grid_pin_44_[0]:5 left_top_grid_pin_44_[0]:4 0.0004933036 +17 left_top_grid_pin_44_[0]:6 left_top_grid_pin_44_[0]:5 0.0045 +18 left_top_grid_pin_44_[0]:4 mux_left_track_1\/mux_l2_in_1_:A0 0.152 +19 left_top_grid_pin_44_[0]:9 left_top_grid_pin_44_[0]:8 0.0009040179 +20 left_top_grid_pin_44_[0]:10 left_top_grid_pin_44_[0]:9 0.0045 +21 left_top_grid_pin_44_[0]:8 mux_left_track_25\/mux_l1_in_2_:A0 0.152 +22 left_top_grid_pin_44_[0]:24 left_top_grid_pin_44_[0]:23 0.00341 +23 left_top_grid_pin_44_[0]:23 left_top_grid_pin_44_[0]:22 0.005114383 + +*END + +*D_NET chanx_right_out[12] 0.001369156 //LENGTH 10.170 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 130.640 69.360 +*P chanx_right_out[12] O *L 0.7423 *C 140.375 69.360 +*N chanx_right_out[12]:2 *C 131.108 69.360 +*N chanx_right_out[12]:3 *C 131.100 69.360 +*N chanx_right_out[12]:4 *C 130.640 69.360 +*N chanx_right_out[12]:5 *C 130.640 69.360 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 0.000596909 +2 chanx_right_out[12]:2 0.000596909 +3 chanx_right_out[12]:3 7.318406e-05 +4 chanx_right_out[12]:4 6.922605e-05 +5 chanx_right_out[12]:5 3.192846e-05 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:5 0.152 +1 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +2 chanx_right_out[12]:2 chanx_right_out[12] 0.001451908 +3 chanx_right_out[12]:5 chanx_right_out[12]:4 0.0045 +4 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[2] 0.004200864 //LENGTH 32.925 LUMPCC 0.0003409499 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.175 45.560 +*I mux_left_track_5\/mux_l3_in_1_:S I *L 0.00357 *C 13.220 45.560 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 15.355 37.060 +*I mux_left_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 17.580 47.310 +*N mux_tree_tapbuf_size14_1_sram[2]:4 *C 17.580 47.310 +*N mux_tree_tapbuf_size14_1_sram[2]:5 *C 15.318 37.060 +*N mux_tree_tapbuf_size14_1_sram[2]:6 *C 10.625 37.060 +*N mux_tree_tapbuf_size14_1_sram[2]:7 *C 10.580 37.105 +*N mux_tree_tapbuf_size14_1_sram[2]:8 *C 10.580 45.515 +*N mux_tree_tapbuf_size14_1_sram[2]:9 *C 10.625 45.560 +*N mux_tree_tapbuf_size14_1_sram[2]:10 *C 13.220 45.560 +*N mux_tree_tapbuf_size14_1_sram[2]:11 *C 14.675 45.560 +*N mux_tree_tapbuf_size14_1_sram[2]:12 *C 14.720 45.605 +*N mux_tree_tapbuf_size14_1_sram[2]:13 *C 14.720 47.555 +*N mux_tree_tapbuf_size14_1_sram[2]:14 *C 14.765 47.600 +*N mux_tree_tapbuf_size14_1_sram[2]:15 *C 17.470 47.600 +*N mux_tree_tapbuf_size14_1_sram[2]:16 *C 21.115 47.600 +*N mux_tree_tapbuf_size14_1_sram[2]:17 *C 21.160 47.555 +*N mux_tree_tapbuf_size14_1_sram[2]:18 *C 21.160 45.605 +*N mux_tree_tapbuf_size14_1_sram[2]:19 *C 21.205 45.560 +*N mux_tree_tapbuf_size14_1_sram[2]:20 *C 23.138 45.560 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_5\/mux_l3_in_1_:S 1e-06 +2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_5\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size14_1_sram[2]:4 5.915119e-05 +5 mux_tree_tapbuf_size14_1_sram[2]:5 0.000324937 +6 mux_tree_tapbuf_size14_1_sram[2]:6 0.000324937 +7 mux_tree_tapbuf_size14_1_sram[2]:7 0.0004704814 +8 mux_tree_tapbuf_size14_1_sram[2]:8 0.0004704814 +9 mux_tree_tapbuf_size14_1_sram[2]:9 0.0001571761 +10 mux_tree_tapbuf_size14_1_sram[2]:10 0.0002748407 +11 mux_tree_tapbuf_size14_1_sram[2]:11 8.973415e-05 +12 mux_tree_tapbuf_size14_1_sram[2]:12 0.0001360852 +13 mux_tree_tapbuf_size14_1_sram[2]:13 0.0001360852 +14 mux_tree_tapbuf_size14_1_sram[2]:14 0.0001906768 +15 mux_tree_tapbuf_size14_1_sram[2]:15 0.0003983129 +16 mux_tree_tapbuf_size14_1_sram[2]:16 0.0001775861 +17 mux_tree_tapbuf_size14_1_sram[2]:17 0.0001569931 +18 mux_tree_tapbuf_size14_1_sram[2]:18 0.0001569931 +19 mux_tree_tapbuf_size14_1_sram[2]:19 0.0001657215 +20 mux_tree_tapbuf_size14_1_sram[2]:20 0.0001657215 +21 mux_tree_tapbuf_size14_1_sram[2]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001072329 +22 mux_tree_tapbuf_size14_1_sram[2]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001072329 +23 mux_tree_tapbuf_size14_1_sram[2]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.559676e-05 +24 mux_tree_tapbuf_size14_1_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.083288e-06 +25 mux_tree_tapbuf_size14_1_sram[2]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.083288e-06 +26 mux_tree_tapbuf_size14_1_sram[2]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 2.656195e-05 +27 mux_tree_tapbuf_size14_1_sram[2]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.559676e-05 +28 mux_tree_tapbuf_size14_1_sram[2]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.656195e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size14_1_sram[2]:20 0.152 +1 mux_tree_tapbuf_size14_1_sram[2]:9 mux_tree_tapbuf_size14_1_sram[2]:8 0.0045 +2 mux_tree_tapbuf_size14_1_sram[2]:8 mux_tree_tapbuf_size14_1_sram[2]:7 0.007508929 +3 mux_tree_tapbuf_size14_1_sram[2]:6 mux_tree_tapbuf_size14_1_sram[2]:5 0.004189732 +4 mux_tree_tapbuf_size14_1_sram[2]:7 mux_tree_tapbuf_size14_1_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size14_1_sram[2]:5 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size14_1_sram[2]:20 mux_tree_tapbuf_size14_1_sram[2]:19 0.001725446 +7 mux_tree_tapbuf_size14_1_sram[2]:19 mux_tree_tapbuf_size14_1_sram[2]:18 0.0045 +8 mux_tree_tapbuf_size14_1_sram[2]:18 mux_tree_tapbuf_size14_1_sram[2]:17 0.001741072 +9 mux_tree_tapbuf_size14_1_sram[2]:16 mux_tree_tapbuf_size14_1_sram[2]:15 0.003254464 +10 mux_tree_tapbuf_size14_1_sram[2]:17 mux_tree_tapbuf_size14_1_sram[2]:16 0.0045 +11 mux_tree_tapbuf_size14_1_sram[2]:10 mux_left_track_5\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size14_1_sram[2]:10 mux_tree_tapbuf_size14_1_sram[2]:9 0.002316964 +13 mux_tree_tapbuf_size14_1_sram[2]:14 mux_tree_tapbuf_size14_1_sram[2]:13 0.0045 +14 mux_tree_tapbuf_size14_1_sram[2]:13 mux_tree_tapbuf_size14_1_sram[2]:12 0.001741072 +15 mux_tree_tapbuf_size14_1_sram[2]:11 mux_tree_tapbuf_size14_1_sram[2]:10 0.001299107 +16 mux_tree_tapbuf_size14_1_sram[2]:12 mux_tree_tapbuf_size14_1_sram[2]:11 0.0045 +17 mux_tree_tapbuf_size14_1_sram[2]:4 mux_left_track_5\/mux_l3_in_0_:S 0.152 +18 mux_tree_tapbuf_size14_1_sram[2]:15 mux_tree_tapbuf_size14_1_sram[2]:14 0.002415179 +19 mux_tree_tapbuf_size14_1_sram[2]:15 mux_tree_tapbuf_size14_1_sram[2]:4 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.0009672404 //LENGTH 8.120 LUMPCC 0.0001577301 DR + +*CONN +*I mem_top_track_30\/FTB_23__49:X O *L 0 *C 42.085 88.400 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 36.975 86.020 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 36.975 86.020 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 37.260 86.020 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 37.260 86.065 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 37.260 88.355 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 *C 37.305 88.400 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 *C 42.047 88.400 + +*CAP +0 mem_top_track_30\/FTB_23__49:X 1e-06 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 4.443471e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 4.832931e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0001387241 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0001387241 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.000218649 +7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.000218649 +8 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_2_sram[0]:9 7.886506e-05 +9 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_2_sram[0]:8 7.886506e-05 + +*RES +0 mem_top_track_30\/FTB_23__49:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.004234375 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[1] 0.002531135 //LENGTH 20.345 LUMPCC 0.0005269286 DR + +*CONN +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 63.785 37.235 +*I mux_top_track_18\/mux_l2_in_0_:S I *L 0.00357 *C 62.920 44.880 +*I mem_top_track_18\/FTB_17__43:A I *L 0.001746 *C 63.020 28.560 +*N mux_tree_tapbuf_size3_3_sram[1]:3 *C 63.058 28.560 +*N mux_tree_tapbuf_size3_3_sram[1]:4 *C 64.355 28.560 +*N mux_tree_tapbuf_size3_3_sram[1]:5 *C 64.400 28.605 +*N mux_tree_tapbuf_size3_3_sram[1]:6 *C 64.400 37.015 +*N mux_tree_tapbuf_size3_3_sram[1]:7 *C 64.355 37.060 +*N mux_tree_tapbuf_size3_3_sram[1]:8 *C 62.920 44.880 +*N mux_tree_tapbuf_size3_3_sram[1]:9 *C 63.020 44.835 +*N mux_tree_tapbuf_size3_3_sram[1]:10 *C 63.020 37.105 +*N mux_tree_tapbuf_size3_3_sram[1]:11 *C 63.065 37.060 +*N mux_tree_tapbuf_size3_3_sram[1]:12 *C 63.785 37.235 + +*CAP +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_18\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_18\/FTB_17__43:A 1e-06 +3 mux_tree_tapbuf_size3_3_sram[1]:3 0.0001025247 +4 mux_tree_tapbuf_size3_3_sram[1]:4 0.0001025247 +5 mux_tree_tapbuf_size3_3_sram[1]:5 0.0004669732 +6 mux_tree_tapbuf_size3_3_sram[1]:6 0.0004669732 +7 mux_tree_tapbuf_size3_3_sram[1]:7 4.358982e-05 +8 mux_tree_tapbuf_size3_3_sram[1]:8 3.761624e-05 +9 mux_tree_tapbuf_size3_3_sram[1]:9 0.0003025482 +10 mux_tree_tapbuf_size3_3_sram[1]:10 0.0003025482 +11 mux_tree_tapbuf_size3_3_sram[1]:11 5.202656e-05 +12 mux_tree_tapbuf_size3_3_sram[1]:12 0.000123882 +13 mux_tree_tapbuf_size3_3_sram[1]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.194694e-05 +14 mux_tree_tapbuf_size3_3_sram[1]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.194694e-05 +15 mux_tree_tapbuf_size3_3_sram[1]:10 optlc_net_126:36 0.0001555588 +16 mux_tree_tapbuf_size3_3_sram[1]:10 optlc_net_126:35 4.595855e-05 +17 mux_tree_tapbuf_size3_3_sram[1]:9 optlc_net_126:32 0.0001555588 +18 mux_tree_tapbuf_size3_3_sram[1]:9 optlc_net_126:36 4.595855e-05 + +*RES +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_3_sram[1]:12 0.152 +1 mux_tree_tapbuf_size3_3_sram[1]:7 mux_tree_tapbuf_size3_3_sram[1]:6 0.0045 +2 mux_tree_tapbuf_size3_3_sram[1]:6 mux_tree_tapbuf_size3_3_sram[1]:5 0.007508929 +3 mux_tree_tapbuf_size3_3_sram[1]:4 mux_tree_tapbuf_size3_3_sram[1]:3 0.001158482 +4 mux_tree_tapbuf_size3_3_sram[1]:5 mux_tree_tapbuf_size3_3_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size3_3_sram[1]:3 mem_top_track_18\/FTB_17__43:A 0.152 +6 mux_tree_tapbuf_size3_3_sram[1]:12 mux_tree_tapbuf_size3_3_sram[1]:11 0.0006428572 +7 mux_tree_tapbuf_size3_3_sram[1]:12 mux_tree_tapbuf_size3_3_sram[1]:7 0.0005089286 +8 mux_tree_tapbuf_size3_3_sram[1]:11 mux_tree_tapbuf_size3_3_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size3_3_sram[1]:10 mux_tree_tapbuf_size3_3_sram[1]:9 0.006901786 +10 mux_tree_tapbuf_size3_3_sram[1]:8 mux_top_track_18\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size3_3_sram[1]:9 mux_tree_tapbuf_size3_3_sram[1]:8 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_2_ccff_tail[0] 0.000536298 //LENGTH 4.100 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/FTB_16__42:X O *L 0 *C 54.965 44.540 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 53.535 42.500 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 *C 53.535 42.500 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 *C 53.820 42.500 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 *C 53.820 42.545 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 *C 53.820 44.495 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 *C 53.865 44.540 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 *C 54.928 44.540 + +*CAP +0 mem_top_track_16\/FTB_16__42:X 1e-06 +1 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 4.796637e-05 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 5.355264e-05 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.0001261425 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0001261425 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 9.024701e-05 +7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 9.024701e-05 + +*RES +0 mem_top_track_16\/FTB_16__42:X mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 0.0001222826 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.0009486608 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[1] 0.002527491 //LENGTH 18.800 LUMPCC 0.0003195678 DR + +*CONN +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 121.745 53.380 +*I mux_top_track_10\/mux_l2_in_0_:S I *L 0.00357 *C 124.300 55.760 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 118.395 58.820 +*I mux_top_track_10\/mux_l2_in_1_:S I *L 0.00357 *C 124.760 61.200 +*N mux_tree_tapbuf_size4_1_sram[1]:4 *C 124.760 61.200 +*N mux_tree_tapbuf_size4_1_sram[1]:5 *C 124.660 61.540 +*N mux_tree_tapbuf_size4_1_sram[1]:6 *C 121.945 61.540 +*N mux_tree_tapbuf_size4_1_sram[1]:7 *C 121.900 61.495 +*N mux_tree_tapbuf_size4_1_sram[1]:8 *C 118.433 58.820 +*N mux_tree_tapbuf_size4_1_sram[1]:9 *C 121.855 58.820 +*N mux_tree_tapbuf_size4_1_sram[1]:10 *C 121.900 58.820 +*N mux_tree_tapbuf_size4_1_sram[1]:11 *C 124.263 55.760 +*N mux_tree_tapbuf_size4_1_sram[1]:12 *C 121.945 55.760 +*N mux_tree_tapbuf_size4_1_sram[1]:13 *C 121.900 55.760 +*N mux_tree_tapbuf_size4_1_sram[1]:14 *C 121.900 53.425 +*N mux_tree_tapbuf_size4_1_sram[1]:15 *C 121.900 53.380 +*N mux_tree_tapbuf_size4_1_sram[1]:16 *C 121.745 53.380 + +*CAP +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_10\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_10\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size4_1_sram[1]:4 5.863777e-05 +5 mux_tree_tapbuf_size4_1_sram[1]:5 0.0002481811 +6 mux_tree_tapbuf_size4_1_sram[1]:6 0.0002196622 +7 mux_tree_tapbuf_size4_1_sram[1]:7 0.0001321816 +8 mux_tree_tapbuf_size4_1_sram[1]:8 0.0002442492 +9 mux_tree_tapbuf_size4_1_sram[1]:9 0.0002442492 +10 mux_tree_tapbuf_size4_1_sram[1]:10 0.0002991158 +11 mux_tree_tapbuf_size4_1_sram[1]:11 0.0001167987 +12 mux_tree_tapbuf_size4_1_sram[1]:12 0.0001167987 +13 mux_tree_tapbuf_size4_1_sram[1]:13 0.0002953463 +14 mux_tree_tapbuf_size4_1_sram[1]:14 0.0001309329 +15 mux_tree_tapbuf_size4_1_sram[1]:15 5.022759e-05 +16 mux_tree_tapbuf_size4_1_sram[1]:16 4.754266e-05 +17 mux_tree_tapbuf_size4_1_sram[1]:12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001003641 +18 mux_tree_tapbuf_size4_1_sram[1]:11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001003641 +19 mux_tree_tapbuf_size4_1_sram[1]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.01669e-05 +20 mux_tree_tapbuf_size4_1_sram[1]:13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.925284e-05 +21 mux_tree_tapbuf_size4_1_sram[1]:10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.925284e-05 +22 mux_tree_tapbuf_size4_1_sram[1]:10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.01669e-05 + +*RES +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size4_1_sram[1]:6 mux_tree_tapbuf_size4_1_sram[1]:5 0.002424107 +2 mux_tree_tapbuf_size4_1_sram[1]:7 mux_tree_tapbuf_size4_1_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size4_1_sram[1]:4 mux_top_track_10\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size4_1_sram[1]:12 mux_tree_tapbuf_size4_1_sram[1]:11 0.002069197 +5 mux_tree_tapbuf_size4_1_sram[1]:13 mux_tree_tapbuf_size4_1_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size4_1_sram[1]:13 mux_tree_tapbuf_size4_1_sram[1]:10 0.002732143 +7 mux_tree_tapbuf_size4_1_sram[1]:11 mux_top_track_10\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_1_sram[1]:9 mux_tree_tapbuf_size4_1_sram[1]:8 0.003055804 +9 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:7 0.002388393 +11 mux_tree_tapbuf_size4_1_sram[1]:8 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size4_1_sram[1]:15 mux_tree_tapbuf_size4_1_sram[1]:14 0.0045 +13 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:13 0.002084821 +14 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[1]:15 8.423914e-05 +15 mux_tree_tapbuf_size4_1_sram[1]:5 mux_tree_tapbuf_size4_1_sram[1]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[0] 0.005617331 //LENGTH 41.920 LUMPCC 9.605227e-05 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 89.085 55.420 +*I mux_top_track_6\/mux_l1_in_0_:S I *L 0.00357 *C 79.940 53.040 +*I mux_top_track_6\/mux_l1_in_1_:S I *L 0.00357 *C 79.480 44.880 +*I mux_top_track_6\/mux_l1_in_3_:S I *L 0.00357 *C 85.460 45.175 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 79.755 42.500 +*I mux_top_track_6\/mux_l1_in_2_:S I *L 0.00357 *C 89.800 41.480 +*N mux_tree_tapbuf_size7_2_sram[0]:6 *C 89.763 41.480 +*N mux_tree_tapbuf_size7_2_sram[0]:7 *C 86.065 41.480 +*N mux_tree_tapbuf_size7_2_sram[0]:8 *C 86.020 41.525 +*N mux_tree_tapbuf_size7_2_sram[0]:9 *C 79.793 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:10 *C 85.975 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:11 *C 86.020 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:12 *C 85.460 45.175 +*N mux_tree_tapbuf_size7_2_sram[0]:13 *C 79.517 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:14 *C 85.460 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:15 *C 85.975 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:16 *C 86.020 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:17 *C 79.940 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:18 *C 80.040 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:19 *C 80.047 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:20 *C 86.013 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:21 *C 86.020 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:22 *C 86.020 55.375 +*N mux_tree_tapbuf_size7_2_sram[0]:23 *C 86.065 55.420 +*N mux_tree_tapbuf_size7_2_sram[0]:24 *C 89.047 55.420 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_6\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_6\/mux_l1_in_1_:S 1e-06 +3 mux_top_track_6\/mux_l1_in_3_:S 1e-06 +4 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_top_track_6\/mux_l1_in_2_:S 1e-06 +6 mux_tree_tapbuf_size7_2_sram[0]:6 0.0002654172 +7 mux_tree_tapbuf_size7_2_sram[0]:7 0.0002654172 +8 mux_tree_tapbuf_size7_2_sram[0]:8 6.405242e-05 +9 mux_tree_tapbuf_size7_2_sram[0]:9 0.0003998968 +10 mux_tree_tapbuf_size7_2_sram[0]:10 0.0003998968 +11 mux_tree_tapbuf_size7_2_sram[0]:11 0.0002245394 +12 mux_tree_tapbuf_size7_2_sram[0]:12 6.95621e-05 +13 mux_tree_tapbuf_size7_2_sram[0]:13 0.0004188744 +14 mux_tree_tapbuf_size7_2_sram[0]:14 0.0005050917 +15 mux_tree_tapbuf_size7_2_sram[0]:15 5.06962e-05 +16 mux_tree_tapbuf_size7_2_sram[0]:16 0.0005877299 +17 mux_tree_tapbuf_size7_2_sram[0]:17 2.80759e-05 +18 mux_tree_tapbuf_size7_2_sram[0]:18 3.457368e-05 +19 mux_tree_tapbuf_size7_2_sram[0]:19 0.0005246326 +20 mux_tree_tapbuf_size7_2_sram[0]:20 0.0005246326 +21 mux_tree_tapbuf_size7_2_sram[0]:21 0.0006010266 +22 mux_tree_tapbuf_size7_2_sram[0]:22 0.0001444783 +23 mux_tree_tapbuf_size7_2_sram[0]:23 0.0002033421 +24 mux_tree_tapbuf_size7_2_sram[0]:24 0.0002033421 +25 mux_tree_tapbuf_size7_2_sram[0]:21 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.802614e-05 +26 mux_tree_tapbuf_size7_2_sram[0]:16 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.802614e-05 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_2_sram[0]:24 0.152 +1 mux_tree_tapbuf_size7_2_sram[0]:10 mux_tree_tapbuf_size7_2_sram[0]:9 0.00552009 +2 mux_tree_tapbuf_size7_2_sram[0]:11 mux_tree_tapbuf_size7_2_sram[0]:10 0.0045 +3 mux_tree_tapbuf_size7_2_sram[0]:11 mux_tree_tapbuf_size7_2_sram[0]:8 0.0008705358 +4 mux_tree_tapbuf_size7_2_sram[0]:9 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +5 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:20 0.00341 +6 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:16 0.007285715 +7 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:19 0.0009345166 +8 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:17 0.0045 +9 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:18 0.00341 +10 mux_tree_tapbuf_size7_2_sram[0]:17 mux_top_track_6\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size7_2_sram[0]:12 mux_top_track_6\/mux_l1_in_3_:S 0.152 +12 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:14 0.0004598215 +13 mux_tree_tapbuf_size7_2_sram[0]:16 mux_tree_tapbuf_size7_2_sram[0]:15 0.0045 +14 mux_tree_tapbuf_size7_2_sram[0]:16 mux_tree_tapbuf_size7_2_sram[0]:11 0.002125 +15 mux_tree_tapbuf_size7_2_sram[0]:7 mux_tree_tapbuf_size7_2_sram[0]:6 0.003301339 +16 mux_tree_tapbuf_size7_2_sram[0]:8 mux_tree_tapbuf_size7_2_sram[0]:7 0.0045 +17 mux_tree_tapbuf_size7_2_sram[0]:6 mux_top_track_6\/mux_l1_in_2_:S 0.152 +18 mux_tree_tapbuf_size7_2_sram[0]:23 mux_tree_tapbuf_size7_2_sram[0]:22 0.0045 +19 mux_tree_tapbuf_size7_2_sram[0]:22 mux_tree_tapbuf_size7_2_sram[0]:21 0.002084821 +20 mux_tree_tapbuf_size7_2_sram[0]:24 mux_tree_tapbuf_size7_2_sram[0]:23 0.002662947 +21 mux_tree_tapbuf_size7_2_sram[0]:13 mux_top_track_6\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:13 0.005305804 +23 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:12 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_2_ccff_tail[0] 0.0008654807 //LENGTH 7.160 LUMPCC 0 DR + +*CONN +*I mem_top_track_6\/FTB_7__33:X O *L 0 *C 94.995 47.600 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 96.315 42.500 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 *C 96.315 42.500 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 *C 96.140 42.500 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 *C 96.140 42.545 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 *C 96.140 47.555 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 *C 96.095 47.600 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 *C 95.032 47.600 + +*CAP +0 mem_top_track_6\/FTB_7__33:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 5.031431e-05 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 5.451036e-05 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.0002966124 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0002966124 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 8.271558e-05 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 8.271558e-05 + +*RES +0 mem_top_track_6\/FTB_7__33:X mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.0009486608 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.004473215 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[2] 0.001964017 //LENGTH 16.575 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 123.125 47.600 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 119.775 42.500 +*I mux_right_track_8\/mux_l3_in_1_:S I *L 0.00357 *C 125.680 45.220 +*I mux_right_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 123.620 51.000 +*N mux_tree_tapbuf_size8_1_sram[2]:4 *C 123.620 51.000 +*N mux_tree_tapbuf_size8_1_sram[2]:5 *C 123.740 50.955 +*N mux_tree_tapbuf_size8_1_sram[2]:6 *C 125.643 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:7 *C 119.812 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:8 *C 120.935 42.500 +*N mux_tree_tapbuf_size8_1_sram[2]:9 *C 120.980 42.545 +*N mux_tree_tapbuf_size8_1_sram[2]:10 *C 120.980 45.175 +*N mux_tree_tapbuf_size8_1_sram[2]:11 *C 121.025 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:12 *C 123.740 45.220 +*N mux_tree_tapbuf_size8_1_sram[2]:13 *C 123.740 45.265 +*N mux_tree_tapbuf_size8_1_sram[2]:14 *C 123.740 47.600 +*N mux_tree_tapbuf_size8_1_sram[2]:15 *C 123.695 47.600 +*N mux_tree_tapbuf_size8_1_sram[2]:16 *C 123.163 47.600 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_track_8\/mux_l3_in_1_:S 1e-06 +3 mux_right_track_8\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_1_sram[2]:4 2.952068e-05 +5 mux_tree_tapbuf_size8_1_sram[2]:5 0.0002033041 +6 mux_tree_tapbuf_size8_1_sram[2]:6 0.0001136147 +7 mux_tree_tapbuf_size8_1_sram[2]:7 9.582676e-05 +8 mux_tree_tapbuf_size8_1_sram[2]:8 9.582676e-05 +9 mux_tree_tapbuf_size8_1_sram[2]:9 0.0001549528 +10 mux_tree_tapbuf_size8_1_sram[2]:10 0.0001549528 +11 mux_tree_tapbuf_size8_1_sram[2]:11 0.000159161 +12 mux_tree_tapbuf_size8_1_sram[2]:12 0.000303661 +13 mux_tree_tapbuf_size8_1_sram[2]:13 0.0001371458 +14 mux_tree_tapbuf_size8_1_sram[2]:14 0.0003735562 +15 mux_tree_tapbuf_size8_1_sram[2]:15 6.924732e-05 +16 mux_tree_tapbuf_size8_1_sram[2]:16 6.924732e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_1_sram[2]:16 0.152 +1 mux_tree_tapbuf_size8_1_sram[2]:6 mux_right_track_8\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[2]:11 mux_tree_tapbuf_size8_1_sram[2]:10 0.0045 +3 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:9 0.002348214 +4 mux_tree_tapbuf_size8_1_sram[2]:8 mux_tree_tapbuf_size8_1_sram[2]:7 0.001002232 +5 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size8_1_sram[2]:7 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +7 mux_tree_tapbuf_size8_1_sram[2]:15 mux_tree_tapbuf_size8_1_sram[2]:14 0.0045 +8 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:13 0.002084821 +9 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:5 0.002995536 +10 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:15 0.0004754465 +11 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:11 0.002424107 +12 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:6 0.001698661 +13 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:12 0.0045 +14 mux_tree_tapbuf_size8_1_sram[2]:4 mux_right_track_8\/mux_l3_in_0_:S 0.152 +15 mux_tree_tapbuf_size8_1_sram[2]:5 mux_tree_tapbuf_size8_1_sram[2]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size9_1_sram[3] 0.001246434 //LENGTH 9.870 LUMPCC 0.0003791216 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 103.805 88.060 +*I mem_right_track_2\/FTB_28__54:A I *L 0.001746 *C 107.180 85.680 +*I mux_right_track_2\/mux_l4_in_0_:S I *L 0.00357 *C 105.700 83.640 +*N mux_tree_tapbuf_size9_1_sram[3]:3 *C 105.685 83.640 +*N mux_tree_tapbuf_size9_1_sram[3]:4 *C 105.363 83.640 +*N mux_tree_tapbuf_size9_1_sram[3]:5 *C 105.340 83.685 +*N mux_tree_tapbuf_size9_1_sram[3]:6 *C 107.157 85.708 +*N mux_tree_tapbuf_size9_1_sram[3]:7 *C 107.145 86.020 +*N mux_tree_tapbuf_size9_1_sram[3]:8 *C 105.385 86.020 +*N mux_tree_tapbuf_size9_1_sram[3]:9 *C 105.340 86.020 +*N mux_tree_tapbuf_size9_1_sram[3]:10 *C 105.340 88.015 +*N mux_tree_tapbuf_size9_1_sram[3]:11 *C 105.295 88.060 +*N mux_tree_tapbuf_size9_1_sram[3]:12 *C 103.843 88.060 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_2\/FTB_28__54:A 1e-06 +2 mux_right_track_2\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size9_1_sram[3]:3 5.145952e-05 +4 mux_tree_tapbuf_size9_1_sram[3]:4 5.145952e-05 +5 mux_tree_tapbuf_size9_1_sram[3]:5 6.444073e-05 +6 mux_tree_tapbuf_size9_1_sram[3]:6 3.136364e-05 +7 mux_tree_tapbuf_size9_1_sram[3]:7 0.0001307868 +8 mux_tree_tapbuf_size9_1_sram[3]:8 9.942319e-05 +9 mux_tree_tapbuf_size9_1_sram[3]:9 0.0001618243 +10 mux_tree_tapbuf_size9_1_sram[3]:10 6.975961e-05 +11 mux_tree_tapbuf_size9_1_sram[3]:11 0.0001018974 +12 mux_tree_tapbuf_size9_1_sram[3]:12 0.0001018974 +13 mux_tree_tapbuf_size9_1_sram[3]:5 right_top_grid_pin_43_[0]:22 6.717954e-05 +14 mux_tree_tapbuf_size9_1_sram[3]:9 right_top_grid_pin_43_[0]:22 6.081615e-05 +15 mux_tree_tapbuf_size9_1_sram[3]:9 right_top_grid_pin_43_[0]:23 6.717954e-05 +16 mux_tree_tapbuf_size9_1_sram[3]:10 right_top_grid_pin_43_[0]:23 6.081615e-05 +17 mux_tree_tapbuf_size9_1_sram[3]:5 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 4.340595e-05 +18 mux_tree_tapbuf_size9_1_sram[3]:8 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 1.815916e-05 +19 mux_tree_tapbuf_size9_1_sram[3]:9 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 4.340595e-05 +20 mux_tree_tapbuf_size9_1_sram[3]:7 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 1.815916e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size9_1_sram[3]:12 0.152 +1 mux_tree_tapbuf_size9_1_sram[3]:3 mux_right_track_2\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size9_1_sram[3]:4 mux_tree_tapbuf_size9_1_sram[3]:3 0.0001752718 +3 mux_tree_tapbuf_size9_1_sram[3]:5 mux_tree_tapbuf_size9_1_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size9_1_sram[3]:8 mux_tree_tapbuf_size9_1_sram[3]:7 0.001571429 +5 mux_tree_tapbuf_size9_1_sram[3]:9 mux_tree_tapbuf_size9_1_sram[3]:8 0.0045 +6 mux_tree_tapbuf_size9_1_sram[3]:9 mux_tree_tapbuf_size9_1_sram[3]:5 0.002084821 +7 mux_tree_tapbuf_size9_1_sram[3]:6 mem_right_track_2\/FTB_28__54:A 0.152 +8 mux_tree_tapbuf_size9_1_sram[3]:11 mux_tree_tapbuf_size9_1_sram[3]:10 0.0045 +9 mux_tree_tapbuf_size9_1_sram[3]:10 mux_tree_tapbuf_size9_1_sram[3]:9 0.00178125 +10 mux_tree_tapbuf_size9_1_sram[3]:12 mux_tree_tapbuf_size9_1_sram[3]:11 0.001296875 +11 mux_tree_tapbuf_size9_1_sram[3]:7 mux_tree_tapbuf_size9_1_sram[3]:6 0.0002111487 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001149344 //LENGTH 10.070 LUMPCC 0.0001854599 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_1_:X O *L 0 *C 124.835 44.200 +*I mux_right_track_8\/mux_l4_in_0_:A0 I *L 0.001631 *C 126.675 37.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 126.638 37.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 124.705 37.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 124.660 37.105 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 124.660 44.155 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 124.660 44.200 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 124.835 44.200 + +*CAP +0 mux_right_track_8\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000120481 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.000120481 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003093955 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003093955 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.218653e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.994493e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_1_sram[3]:3 3.826015e-06 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_1_sram[3]:9 1.990494e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_1_sram[3]:8 1.990494e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_1_sram[3]:9 3.826015e-06 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_1_sram[3]:10 6.899898e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_1_sram[3]:11 6.899898e-05 + +*RES +0 mux_right_track_8\/mux_l3_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_8\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001725447 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.006294643 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002143799 //LENGTH 9.805 LUMPCC 0.0006773512 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_0_:X O *L 0 *C 50.885 87.720 +*I mux_top_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.880 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.880 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 58.880 88.695 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 58.880 87.778 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 58.873 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 51.068 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 51.060 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 51.060 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 50.885 87.720 + +*CAP +0 mux_top_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.413187e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.774501e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.774501e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005523251 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005523251 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 3.540174e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.496932e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.980457e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_35_[0]:21 0.0002732823 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_35_[0]:17 0.0002732823 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size7_0_sram[0]:8 3.532331e-06 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size7_0_sram[0]:9 3.532331e-06 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_0_sram[0]:15 6.186093e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:16 6.186093e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.51087e-05 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00341 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001222783 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0008191965 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00341 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A1 0.152 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009058075 //LENGTH 6.545 LUMPCC 0.000496623 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_0_:X O *L 0 *C 93.665 34.340 +*I mux_right_track_16\/mux_l3_in_0_:A1 I *L 0.00198 *C 99.920 34.340 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 99.883 34.340 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 93.703 34.340 + +*CAP +0 mux_right_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002035922 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002035922 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[8]:19 6.096853e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[8]:20 6.096853e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[18]:20 0.0001380694 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[18]:21 0.0001380694 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_3_sram[2]:6 4.927355e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_3_sram[2]:7 4.927355e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.005517857 + +*END + +*D_NET optlc_net_123 0.005446692 //LENGTH 39.205 LUMPCC 0.001313308 DR + +*CONN +*I optlc_116:HI O *L 0 *C 12.420 53.040 +*I mux_left_track_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 10.295 49.980 +*I mux_left_track_33\/mux_l2_in_1_:A0 I *L 0.001631 *C 13.630 59.160 +*I mux_left_track_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 21.335 59.160 +*I mux_left_track_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 8.965 71.400 +*N optlc_net_123:5 *C 9.003 71.400 +*N optlc_net_123:6 *C 10.075 71.400 +*N optlc_net_123:7 *C 10.120 71.355 +*N optlc_net_123:8 *C 10.120 63.240 +*N optlc_net_123:9 *C 11.040 63.240 +*N optlc_net_123:10 *C 11.040 58.820 +*N optlc_net_123:11 *C 21.297 59.160 +*N optlc_net_123:12 *C 13.630 59.160 +*N optlc_net_123:13 *C 10.625 59.160 +*N optlc_net_123:14 *C 10.610 59.130 +*N optlc_net_123:15 *C 10.580 58.820 +*N optlc_net_123:16 *C 10.295 49.980 +*N optlc_net_123:17 *C 10.580 49.980 +*N optlc_net_123:18 *C 10.580 50.025 +*N optlc_net_123:19 *C 10.580 53.040 +*N optlc_net_123:20 *C 10.625 53.040 +*N optlc_net_123:21 *C 12.383 53.040 + +*CAP +0 optlc_116:HI 1e-06 +1 mux_left_track_5\/mux_l2_in_3_:A0 1e-06 +2 mux_left_track_33\/mux_l2_in_1_:A0 1e-06 +3 mux_left_track_1\/mux_l2_in_3_:A0 1e-06 +4 mux_left_track_3\/mux_l2_in_3_:A0 1e-06 +5 optlc_net_123:5 0.0001039416 +6 optlc_net_123:6 0.0001039416 +7 optlc_net_123:7 0.0003216118 +8 optlc_net_123:8 0.0003744791 +9 optlc_net_123:9 0.0003437144 +10 optlc_net_123:10 0.0003208157 +11 optlc_net_123:11 0.000401112 +12 optlc_net_123:12 0.0005900313 +13 optlc_net_123:13 0.0001612536 +14 optlc_net_123:14 2.373993e-05 +15 optlc_net_123:15 0.0003029494 +16 optlc_net_123:16 5.378817e-05 +17 optlc_net_123:17 5.831843e-05 +18 optlc_net_123:18 0.0001949076 +19 optlc_net_123:19 0.0004762351 +20 optlc_net_123:20 0.0001487721 +21 optlc_net_123:21 0.0001487721 +22 optlc_net_123:7 left_top_grid_pin_46_[0]:21 0.0002092554 +23 optlc_net_123:14 left_top_grid_pin_46_[0]:7 1.783074e-07 +24 optlc_net_123:14 left_top_grid_pin_46_[0]:21 2.608978e-06 +25 optlc_net_123:19 left_top_grid_pin_46_[0]:6 1.206197e-07 +26 optlc_net_123:8 left_top_grid_pin_46_[0]:20 0.0002092554 +27 optlc_net_123:9 left_top_grid_pin_46_[0]:7 9.44276e-08 +28 optlc_net_123:9 left_top_grid_pin_46_[0]:21 8.990518e-06 +29 optlc_net_123:15 left_top_grid_pin_46_[0]:6 1.783074e-07 +30 optlc_net_123:15 left_top_grid_pin_46_[0]:7 1.206197e-07 +31 optlc_net_123:15 left_top_grid_pin_46_[0]:20 2.608978e-06 +32 optlc_net_123:10 left_top_grid_pin_46_[0]:6 9.44276e-08 +33 optlc_net_123:10 left_top_grid_pin_46_[0]:20 8.990518e-06 +34 optlc_net_123:11 mux_tree_tapbuf_size6_1_sram[1]:15 0.0001893699 +35 optlc_net_123:12 mux_tree_tapbuf_size6_1_sram[1]:14 0.0001893699 +36 optlc_net_123:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.88314e-05 +37 optlc_net_123:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.709964e-07 +38 optlc_net_123:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.94595e-05 +39 optlc_net_123:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.460233e-06 +40 optlc_net_123:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.709964e-07 +41 optlc_net_123:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.88314e-05 +42 optlc_net_123:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.94595e-05 +43 optlc_net_123:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.024129e-08 +44 optlc_net_123:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.460233e-06 +45 optlc_net_123:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.024129e-08 +46 optlc_net_123:19 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001191456 +47 optlc_net_123:15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.958009e-06 +48 optlc_net_123:15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001191456 +49 optlc_net_123:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.958009e-06 + +*RES +0 optlc_116:HI optlc_net_123:21 0.152 +1 optlc_net_123:6 optlc_net_123:5 0.0009575893 +2 optlc_net_123:7 optlc_net_123:6 0.0045 +3 optlc_net_123:5 mux_left_track_3\/mux_l2_in_3_:A0 0.152 +4 optlc_net_123:13 optlc_net_123:12 0.002683036 +5 optlc_net_123:14 optlc_net_123:13 0.0045 +6 optlc_net_123:17 optlc_net_123:16 0.0001548913 +7 optlc_net_123:18 optlc_net_123:17 0.0045 +8 optlc_net_123:16 mux_left_track_5\/mux_l2_in_3_:A0 0.152 +9 optlc_net_123:11 mux_left_track_1\/mux_l2_in_3_:A0 0.152 +10 optlc_net_123:20 optlc_net_123:19 0.0045 +11 optlc_net_123:19 optlc_net_123:18 0.002691964 +12 optlc_net_123:19 optlc_net_123:15 0.005160714 +13 optlc_net_123:21 optlc_net_123:20 0.001569196 +14 optlc_net_123:12 mux_left_track_33\/mux_l2_in_1_:A0 0.152 +15 optlc_net_123:12 optlc_net_123:11 0.006845982 +16 optlc_net_123:8 optlc_net_123:7 0.007245536 +17 optlc_net_123:9 optlc_net_123:8 0.0008214285 +18 optlc_net_123:15 optlc_net_123:14 0.00019375 +19 optlc_net_123:15 optlc_net_123:10 0.0004107143 +20 optlc_net_123:10 optlc_net_123:9 0.003946429 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.006433333 //LENGTH 44.630 LUMPCC 0.0007736308 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_0_:X O *L 0 *C 42.145 96.560 +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 83.040 99.090 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.040 99.090 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 83.040 98.600 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.605 98.600 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.560 98.555 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.560 96.618 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.553 96.560 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 42.328 96.560 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 42.320 96.560 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 42.320 96.560 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 42.145 96.560 + +*CAP +0 mux_top_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.380119e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001352778 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00131185 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001345786 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001345786 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001248395 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001248395 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 3.523034e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.934059e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.875458e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[14]:8 0.0001553199 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[14]:18 8.843966e-05 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_top_in[14]:17 8.843966e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_top_in[14]:18 0.0001553199 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_166:3 0.0001430558 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 ropt_net_166:4 0.0001430558 + +*RES +0 mux_top_track_32\/mux_l2_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.01824554 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001729911 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.003168583 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004375001 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006660987 //LENGTH 4.630 LUMPCC 0.0001845547 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_1_:X O *L 0 *C 90.905 93.160 +*I mux_right_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 93.095 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 93.058 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 91.125 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 91.080 91.505 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 91.080 93.115 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 91.080 93.160 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 90.905 93.160 + +*CAP +0 mux_right_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.676639e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.676639e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.533615e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.533615e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.343184e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.190701e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.155498e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.155498e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.072239e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.072239e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001725447 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007736661 //LENGTH 5.480 LUMPCC 0.0001705263 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_4_:X O *L 0 *C 108.385 65.960 +*I mux_right_track_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 110.860 63.580 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 110.860 63.580 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 110.860 63.625 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 110.860 65.915 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 110.815 65.960 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 108.422 65.960 + +*CAP +0 mux_right_track_4\/mux_l1_in_4_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_2_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.47428e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000155497 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000155497 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001277015 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001277015 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_48_[0]:13 8.144304e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_48_[0]:15 3.820098e-06 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_48_[0]:14 8.144304e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_48_[0]:16 3.820098e-06 + +*RES +0 mux_right_track_4\/mux_l1_in_4_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.002136161 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002044643 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4\/mux_l2_in_2_:A1 0.152 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003425002 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_3_:X O *L 0 *C 24.095 49.640 +*I mux_left_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 21.910 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 21.948 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 24.058 49.640 + +*CAP +0 mux_left_track_5\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001702501 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001702501 + +*RES +0 mux_left_track_5\/mux_l1_in_3_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001883929 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006507493 //LENGTH 3.940 LUMPCC 0.0002013696 DR + +*CONN +*I mux_right_track_32\/mux_l2_in_1_:X O *L 0 *C 87.575 71.400 +*I mux_right_track_32\/mux_l3_in_0_:A0 I *L 0.001631 *C 85.735 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 85.773 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 87.355 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 87.400 70.085 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 87.400 71.355 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 87.400 71.400 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 87.575 71.400 + +*CAP +0 mux_right_track_32\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.789958e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.789958e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.755556e-05 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.755556e-05 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.909674e-05 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.737275e-05 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:29 6.333398e-05 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:30 6.333398e-05 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_0_sram[2]:10 3.73508e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_0_sram[2]:11 3.73508e-05 + +*RES +0 mux_right_track_32\/mux_l2_in_1_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_32\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001412946 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133929 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003597399 //LENGTH 2.540 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_1_:X O *L 0 *C 28.345 60.935 +*I mux_left_track_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 30.595 60.860 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 30.558 60.860 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 28.345 60.935 + +*CAP +0 mux_left_track_1\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001572704 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002004694 + +*RES +0 mux_left_track_1\/mux_l3_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001975446 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_1\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET ropt_net_154 0.001265124 //LENGTH 10.250 LUMPCC 0.0003500604 DR + +*CONN +*I FTB_16__15:X O *L 0 *C 133.860 56.440 +*I ropt_mt_inst_778:A I *L 0.001766 *C 134.780 63.920 +*N ropt_net_154:2 *C 134.743 63.920 +*N ropt_net_154:3 *C 133.445 63.920 +*N ropt_net_154:4 *C 133.400 63.875 +*N ropt_net_154:5 *C 133.400 56.485 +*N ropt_net_154:6 *C 133.445 56.440 +*N ropt_net_154:7 *C 133.823 56.440 + +*CAP +0 FTB_16__15:X 1e-06 +1 ropt_mt_inst_778:A 1e-06 +2 ropt_net_154:2 0.0001164388 +3 ropt_net_154:3 0.0001164388 +4 ropt_net_154:4 0.0002888592 +5 ropt_net_154:5 0.0002888592 +6 ropt_net_154:6 5.123388e-05 +7 ropt_net_154:7 5.123388e-05 +8 ropt_net_154:4 chanx_left_in[4]:15 7.907965e-05 +9 ropt_net_154:5 chanx_left_in[4]:14 7.907965e-05 +10 ropt_net_154:4 chanx_left_in[16]:7 4.439286e-06 +11 ropt_net_154:4 chanx_left_in[16]:11 9.151126e-05 +12 ropt_net_154:5 chanx_left_in[16]:8 4.439286e-06 +13 ropt_net_154:5 chanx_left_in[16]:12 9.151126e-05 + +*RES +0 FTB_16__15:X ropt_net_154:7 0.152 +1 ropt_net_154:2 ropt_mt_inst_778:A 0.152 +2 ropt_net_154:3 ropt_net_154:2 0.001158482 +3 ropt_net_154:4 ropt_net_154:3 0.0045 +4 ropt_net_154:6 ropt_net_154:5 0.0045 +5 ropt_net_154:5 ropt_net_154:4 0.006598214 +6 ropt_net_154:7 ropt_net_154:6 0.0003370536 + +*END + +*D_NET ropt_net_168 0.001090415 //LENGTH 8.115 LUMPCC 0.0004237142 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 138.655 20.060 +*I ropt_mt_inst_795:A I *L 0.001767 *C 134.780 23.120 +*N ropt_net_168:2 *C 134.817 23.120 +*N ropt_net_168:3 *C 138.875 23.120 +*N ropt_net_168:4 *C 138.920 23.075 +*N ropt_net_168:5 *C 138.920 20.105 +*N ropt_net_168:6 *C 138.920 20.060 +*N ropt_net_168:7 *C 138.655 20.060 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_168:2 0.0001896537 +3 ropt_net_168:3 0.0001896537 +4 ropt_net_168:4 9.295707e-05 +5 ropt_net_168:5 9.295707e-05 +6 ropt_net_168:6 4.683402e-05 +7 ropt_net_168:7 5.264552e-05 +8 ropt_net_168:4 ccff_head[0]:4 8.164756e-05 +9 ropt_net_168:5 ccff_head[0] 8.164756e-05 +10 ropt_net_168:2 chanx_right_out[2]:6 6.268643e-05 +11 ropt_net_168:3 chanx_right_out[2]:5 6.268643e-05 +12 ropt_net_168:2 chanx_right_out[18]:6 3.519106e-05 +13 ropt_net_168:3 chanx_right_out[18]:5 3.519106e-05 +14 ropt_net_168:4 chanx_right_out[18]:4 3.233207e-05 +15 ropt_net_168:5 chanx_right_out[18]:3 3.233207e-05 + +*RES +0 ropt_mt_inst_765:X ropt_net_168:7 0.152 +1 ropt_net_168:2 ropt_mt_inst_795:A 0.152 +2 ropt_net_168:3 ropt_net_168:2 0.003622768 +3 ropt_net_168:4 ropt_net_168:3 0.0045 +4 ropt_net_168:6 ropt_net_168:5 0.0045 +5 ropt_net_168:5 ropt_net_168:4 0.002651786 +6 ropt_net_168:7 ropt_net_168:6 0.0001222826 + +*END + +*D_NET chanx_right_out[18] 0.0009602819 //LENGTH 7.530 LUMPCC 0.0001350463 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 135.700 22.440 +*P chanx_right_out[18] O *L 0.7423 *C 140.375 20.400 +*N chanx_right_out[18]:2 *C 139.847 20.400 +*N chanx_right_out[18]:3 *C 139.840 20.457 +*N chanx_right_out[18]:4 *C 139.840 22.395 +*N chanx_right_out[18]:5 *C 139.795 22.440 +*N chanx_right_out[18]:6 *C 135.738 22.440 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 chanx_right_out[18] 5.755866e-05 +2 chanx_right_out[18]:2 5.755866e-05 +3 chanx_right_out[18]:3 8.095684e-05 +4 chanx_right_out[18]:4 8.095684e-05 +5 chanx_right_out[18]:5 0.0002736023 +6 chanx_right_out[18]:6 0.0002736023 +7 chanx_right_out[18]:3 ropt_net_168:5 3.233207e-05 +8 chanx_right_out[18]:5 ropt_net_168:3 3.519106e-05 +9 chanx_right_out[18]:4 ropt_net_168:4 3.233207e-05 +10 chanx_right_out[18]:6 ropt_net_168:2 3.519106e-05 + +*RES +0 ropt_mt_inst_795:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +2 chanx_right_out[18]:2 chanx_right_out[18] 8.264166e-05 +3 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +4 chanx_right_out[18]:4 chanx_right_out[18]:3 0.001729911 +5 chanx_right_out[18]:6 chanx_right_out[18]:5 0.003622768 + +*END + +*D_NET ropt_net_135 0.0001749847 //LENGTH 1.210 LUMPCC 7.925303e-05 DR + +*CONN +*I BUFT_P_109:X O *L 0 *C 129.260 28.560 +*I ropt_mt_inst_758:A I *L 0.001766 *C 130.180 28.560 +*N ropt_net_135:2 *C 130.143 28.560 +*N ropt_net_135:3 *C 129.298 28.560 + +*CAP +0 BUFT_P_109:X 1e-06 +1 ropt_mt_inst_758:A 1e-06 +2 ropt_net_135:2 4.686583e-05 +3 ropt_net_135:3 4.686583e-05 +4 ropt_net_135:3 ccff_head[0]:2 3.962651e-05 +5 ropt_net_135:2 ccff_head[0]:3 3.962651e-05 + +*RES +0 BUFT_P_109:X ropt_net_135:3 0.152 +1 ropt_net_135:3 ropt_net_135:2 0.0007544643 +2 ropt_net_135:2 ropt_mt_inst_758:A 0.152 + +*END + +*D_NET chanx_right_in[6] 0.02100508 //LENGTH 146.975 LUMPCC 0.008367985 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 140.450 31.280 +*I mux_left_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 28.060 36.380 +*I BUFT_P_94:A I *L 0.001776 *C 14.720 42.160 +*I mux_top_track_6\/mux_l1_in_2_:A1 I *L 0.00198 *C 90.525 41.820 +*N chanx_right_in[6]:4 *C 90.525 41.820 +*N chanx_right_in[6]:5 *C 90.620 41.775 +*N chanx_right_in[6]:6 *C 14.758 42.160 +*N chanx_right_in[6]:7 *C 17.895 42.160 +*N chanx_right_in[6]:8 *C 17.940 42.115 +*N chanx_right_in[6]:9 *C 17.940 40.858 +*N chanx_right_in[6]:10 *C 17.948 40.800 +*N chanx_right_in[6]:11 *C 27.133 40.800 +*N chanx_right_in[6]:12 *C 27.140 40.742 +*N chanx_right_in[6]:13 *C 28.023 36.380 +*N chanx_right_in[6]:14 *C 27.600 36.380 +*N chanx_right_in[6]:15 *C 27.600 36.040 +*N chanx_right_in[6]:16 *C 27.185 36.040 +*N chanx_right_in[6]:17 *C 27.140 36.085 +*N chanx_right_in[6]:18 *C 27.140 37.400 +*N chanx_right_in[6]:19 *C 27.148 37.400 +*N chanx_right_in[6]:20 *C 76.975 37.400 +*N chanx_right_in[6]:21 *C 90.613 37.400 +*N chanx_right_in[6]:22 *C 90.620 37.400 +*N chanx_right_in[6]:23 *C 90.620 36.040 +*N chanx_right_in[6]:24 *C 91.080 36.040 +*N chanx_right_in[6]:25 *C 91.080 31.325 +*N chanx_right_in[6]:26 *C 91.125 31.280 +*N chanx_right_in[6]:27 *C 109.435 31.280 +*N chanx_right_in[6]:28 *C 109.480 31.280 +*N chanx_right_in[6]:29 *C 109.488 31.280 + +*CAP +0 chanx_right_in[6] 0.0006097894 +1 mux_left_track_9\/mux_l2_in_1_:A1 1e-06 +2 BUFT_P_94:A 1e-06 +3 mux_top_track_6\/mux_l1_in_2_:A1 1e-06 +4 chanx_right_in[6]:4 2.872951e-05 +5 chanx_right_in[6]:5 0.0002011688 +6 chanx_right_in[6]:6 0.0001410216 +7 chanx_right_in[6]:7 0.0001410216 +8 chanx_right_in[6]:8 9.872211e-05 +9 chanx_right_in[6]:9 9.872211e-05 +10 chanx_right_in[6]:10 0.0004612766 +11 chanx_right_in[6]:11 0.0004612766 +12 chanx_right_in[6]:12 0.0002177882 +13 chanx_right_in[6]:13 4.856921e-05 +14 chanx_right_in[6]:14 7.634965e-05 +15 chanx_right_in[6]:15 7.715063e-05 +16 chanx_right_in[6]:16 4.93702e-05 +17 chanx_right_in[6]:17 9.208237e-05 +18 chanx_right_in[6]:18 0.0003446564 +19 chanx_right_in[6]:19 0.002160372 +20 chanx_right_in[6]:20 0.00297725 +21 chanx_right_in[6]:21 0.0008168772 +22 chanx_right_in[6]:22 0.0002944912 +23 chanx_right_in[6]:23 8.789809e-05 +24 chanx_right_in[6]:24 0.0002933453 +25 chanx_right_in[6]:25 0.000263109 +26 chanx_right_in[6]:26 0.0009729023 +27 chanx_right_in[6]:27 0.0009729023 +28 chanx_right_in[6]:28 3.746544e-05 +29 chanx_right_in[6]:29 0.0006097893 +30 chanx_right_in[6]:12 chanx_right_in[16]:14 1.98773e-06 +31 chanx_right_in[6]:11 chanx_right_in[16]:15 0.0002252394 +32 chanx_right_in[6]:10 chanx_right_in[16]:10 0.0002252394 +33 chanx_right_in[6]:18 chanx_right_in[16]:14 1.429379e-07 +34 chanx_right_in[6]:18 chanx_right_in[16]:13 1.98773e-06 +35 chanx_right_in[6]:19 chanx_right_in[16]:10 1.113296e-05 +36 chanx_right_in[6]:19 chanx_right_in[16]:16 0.0002817453 +37 chanx_right_in[6]:17 chanx_right_in[16]:13 1.429379e-07 +38 chanx_right_in[6]:20 chanx_right_in[16]:17 0.0002817453 +39 chanx_right_in[6]:20 chanx_right_in[16]:15 1.113296e-05 +40 chanx_right_in[6] chanx_right_in[17]:25 0.0005051129 +41 chanx_right_in[6]:26 chanx_right_in[17]:24 5.680431e-06 +42 chanx_right_in[6]:27 chanx_right_in[17]:25 5.680431e-06 +43 chanx_right_in[6]:29 chanx_right_in[17]:24 0.0005051129 +44 chanx_right_in[6]:21 chanx_right_in[17]:25 5.269885e-06 +45 chanx_right_in[6]:21 chanx_right_in[17]:24 2.088537e-06 +46 chanx_right_in[6]:19 chanx_right_in[17]:19 1.440822e-05 +47 chanx_right_in[6]:20 chanx_right_in[17]:24 1.967811e-05 +48 chanx_right_in[6]:20 chanx_right_in[17]:19 2.088537e-06 +49 chanx_right_in[6]:11 prog_clk[0]:490 1.426285e-06 +50 chanx_right_in[6]:10 prog_clk[0]:489 1.426285e-06 +51 chanx_right_in[6]:21 prog_clk[0]:287 9.389608e-05 +52 chanx_right_in[6]:19 prog_clk[0]:457 2.613642e-05 +53 chanx_right_in[6]:19 prog_clk[0]:463 6.49166e-05 +54 chanx_right_in[6]:19 prog_clk[0]:423 7.873919e-05 +55 chanx_right_in[6]:19 prog_clk[0]:433 7.139212e-05 +56 chanx_right_in[6]:19 prog_clk[0]:462 6.851128e-05 +57 chanx_right_in[6]:19 prog_clk[0]:434 0.0001464067 +58 chanx_right_in[6]:19 prog_clk[0]:428 0.0001373067 +59 chanx_right_in[6]:19 prog_clk[0]:412 4.873692e-05 +60 chanx_right_in[6]:19 prog_clk[0]:407 5.445675e-05 +61 chanx_right_in[6]:19 prog_clk[0]:413 2.125703e-05 +62 chanx_right_in[6]:20 prog_clk[0]:288 9.389608e-05 +63 chanx_right_in[6]:20 prog_clk[0]:463 6.851128e-05 +64 chanx_right_in[6]:20 prog_clk[0]:423 0.0001373067 +65 chanx_right_in[6]:20 prog_clk[0]:433 0.0001464067 +66 chanx_right_in[6]:20 prog_clk[0]:462 2.613642e-05 +67 chanx_right_in[6]:20 prog_clk[0]:428 7.139212e-05 +68 chanx_right_in[6]:20 prog_clk[0]:371 5.445675e-05 +69 chanx_right_in[6]:20 prog_clk[0]:418 7.873919e-05 +70 chanx_right_in[6]:20 prog_clk[0]:441 6.49166e-05 +71 chanx_right_in[6]:20 prog_clk[0]:412 2.125703e-05 +72 chanx_right_in[6]:20 prog_clk[0]:407 4.873692e-05 +73 chanx_right_in[6]:21 chany_top_in[10]:11 0.0001537301 +74 chanx_right_in[6]:19 chany_top_in[10]:12 0.0003166933 +75 chanx_right_in[6]:19 chany_top_in[10]:18 1.034891e-05 +76 chanx_right_in[6]:20 chany_top_in[10]:12 0.0001537301 +77 chanx_right_in[6]:20 chany_top_in[10]:11 0.0003166933 +78 chanx_right_in[6]:20 chany_top_in[10]:3 1.034891e-05 +79 chanx_right_in[6] chanx_right_in[11] 8.395441e-05 +80 chanx_right_in[6] chanx_right_in[11]:11 0.001547742 +81 chanx_right_in[6]:26 chanx_right_in[11]:10 1.63589e-05 +82 chanx_right_in[6]:25 chanx_right_in[11]:5 2.406471e-05 +83 chanx_right_in[6]:27 chanx_right_in[11]:11 1.63589e-05 +84 chanx_right_in[6]:29 chanx_right_in[11]:10 0.001547742 +85 chanx_right_in[6]:29 chanx_right_in[11]:12 8.395441e-05 +86 chanx_right_in[6]:22 chanx_right_in[11]:4 1.587425e-05 +87 chanx_right_in[6]:22 chanx_right_in[11]:5 5.177253e-05 +88 chanx_right_in[6]:5 chanx_right_in[11]:4 5.177253e-05 +89 chanx_right_in[6]:23 chanx_right_in[11]:5 1.587425e-05 +90 chanx_right_in[6]:24 chanx_right_in[11]:4 2.406471e-05 +91 chanx_right_in[6]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 9.507647e-05 +92 chanx_right_in[6]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 2.386367e-06 +93 chanx_right_in[6]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 2.386367e-06 +94 chanx_right_in[6]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 9.507647e-05 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:29 0.004850791 +1 chanx_right_in[6]:12 chanx_right_in[6]:11 0.00341 +2 chanx_right_in[6]:11 chanx_right_in[6]:10 0.001438983 +3 chanx_right_in[6]:9 chanx_right_in[6]:8 0.001122768 +4 chanx_right_in[6]:10 chanx_right_in[6]:9 0.00341 +5 chanx_right_in[6]:7 chanx_right_in[6]:6 0.002801339 +6 chanx_right_in[6]:8 chanx_right_in[6]:7 0.0045 +7 chanx_right_in[6]:6 BUFT_P_94:A 0.152 +8 chanx_right_in[6]:26 chanx_right_in[6]:25 0.0045 +9 chanx_right_in[6]:25 chanx_right_in[6]:24 0.004209822 +10 chanx_right_in[6]:27 chanx_right_in[6]:26 0.01634821 +11 chanx_right_in[6]:28 chanx_right_in[6]:27 0.0045 +12 chanx_right_in[6]:29 chanx_right_in[6]:28 0.00341 +13 chanx_right_in[6]:22 chanx_right_in[6]:21 0.00341 +14 chanx_right_in[6]:22 chanx_right_in[6]:5 0.00390625 +15 chanx_right_in[6]:21 chanx_right_in[6]:20 0.002136542 +16 chanx_right_in[6]:18 chanx_right_in[6]:17 0.001174107 +17 chanx_right_in[6]:18 chanx_right_in[6]:12 0.002984375 +18 chanx_right_in[6]:19 chanx_right_in[6]:18 0.00341 +19 chanx_right_in[6]:16 chanx_right_in[6]:15 0.0003705357 +20 chanx_right_in[6]:17 chanx_right_in[6]:16 0.0045 +21 chanx_right_in[6]:13 mux_left_track_9\/mux_l2_in_1_:A1 0.152 +22 chanx_right_in[6]:4 mux_top_track_6\/mux_l1_in_2_:A1 0.152 +23 chanx_right_in[6]:5 chanx_right_in[6]:4 0.0045 +24 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0003035715 +25 chanx_right_in[6]:14 chanx_right_in[6]:13 0.0003772322 +26 chanx_right_in[6]:23 chanx_right_in[6]:22 0.001214286 +27 chanx_right_in[6]:24 chanx_right_in[6]:23 0.0004107143 +28 chanx_right_in[6]:20 chanx_right_in[6]:19 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[3] 0.001329739 //LENGTH 10.380 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 57.805 77.180 +*I mux_top_track_0\/mux_l4_in_0_:S I *L 0.00357 *C 56.940 74.120 +*I mem_top_track_0\/FTB_1__27:A I *L 0.001746 *C 60.260 72.080 +*N mux_tree_tapbuf_size8_0_sram[3]:3 *C 60.260 72.080 +*N mux_tree_tapbuf_size8_0_sram[3]:4 *C 60.260 72.420 +*N mux_tree_tapbuf_size8_0_sram[3]:5 *C 58.465 72.420 +*N mux_tree_tapbuf_size8_0_sram[3]:6 *C 58.420 72.465 +*N mux_tree_tapbuf_size8_0_sram[3]:7 *C 56.978 74.120 +*N mux_tree_tapbuf_size8_0_sram[3]:8 *C 58.375 74.120 +*N mux_tree_tapbuf_size8_0_sram[3]:9 *C 58.420 74.120 +*N mux_tree_tapbuf_size8_0_sram[3]:10 *C 58.420 77.135 +*N mux_tree_tapbuf_size8_0_sram[3]:11 *C 58.375 77.180 +*N mux_tree_tapbuf_size8_0_sram[3]:12 *C 57.843 77.180 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:S 1e-06 +2 mem_top_track_0\/FTB_1__27:A 1e-06 +3 mux_tree_tapbuf_size8_0_sram[3]:3 6.502926e-05 +4 mux_tree_tapbuf_size8_0_sram[3]:4 0.0001691157 +5 mux_tree_tapbuf_size8_0_sram[3]:5 0.0001375859 +6 mux_tree_tapbuf_size8_0_sram[3]:6 0.0001015122 +7 mux_tree_tapbuf_size8_0_sram[3]:7 0.0001292223 +8 mux_tree_tapbuf_size8_0_sram[3]:8 0.0001292223 +9 mux_tree_tapbuf_size8_0_sram[3]:9 0.000308703 +10 mux_tree_tapbuf_size8_0_sram[3]:10 0.0001726834 +11 mux_tree_tapbuf_size8_0_sram[3]:11 5.683246e-05 +12 mux_tree_tapbuf_size8_0_sram[3]:12 5.683246e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_0_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_0_sram[3]:5 mux_tree_tapbuf_size8_0_sram[3]:4 0.001602679 +2 mux_tree_tapbuf_size8_0_sram[3]:6 mux_tree_tapbuf_size8_0_sram[3]:5 0.0045 +3 mux_tree_tapbuf_size8_0_sram[3]:3 mem_top_track_0\/FTB_1__27:A 0.152 +4 mux_tree_tapbuf_size8_0_sram[3]:11 mux_tree_tapbuf_size8_0_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:9 0.002691964 +6 mux_tree_tapbuf_size8_0_sram[3]:12 mux_tree_tapbuf_size8_0_sram[3]:11 0.0004754464 +7 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:7 0.001247768 +8 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:8 0.0045 +9 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:6 0.001477679 +10 mux_tree_tapbuf_size8_0_sram[3]:7 mux_top_track_0\/mux_l4_in_0_:S 0.152 +11 mux_tree_tapbuf_size8_0_sram[3]:4 mux_tree_tapbuf_size8_0_sram[3]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[3] 0.001647988 //LENGTH 14.105 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 31.125 26.180 +*I mux_left_track_9\/mux_l4_in_0_:S I *L 0.008363 *C 23.460 25.670 +*I mem_left_track_9\/FTB_4__30:A I *L 0.001746 *C 30.360 28.560 +*N mux_tree_tapbuf_size8_3_sram[3]:3 *C 30.360 28.560 +*N mux_tree_tapbuf_size8_3_sram[3]:4 *C 23.460 25.715 +*N mux_tree_tapbuf_size8_3_sram[3]:5 *C 23.460 28.175 +*N mux_tree_tapbuf_size8_3_sram[3]:6 *C 23.505 28.220 +*N mux_tree_tapbuf_size8_3_sram[3]:7 *C 30.360 28.220 +*N mux_tree_tapbuf_size8_3_sram[3]:8 *C 30.360 28.175 +*N mux_tree_tapbuf_size8_3_sram[3]:9 *C 30.360 26.225 +*N mux_tree_tapbuf_size8_3_sram[3]:10 *C 30.405 26.180 +*N mux_tree_tapbuf_size8_3_sram[3]:11 *C 31.088 26.180 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_9\/mux_l4_in_0_:S 1e-06 +2 mem_left_track_9\/FTB_4__30:A 1e-06 +3 mux_tree_tapbuf_size8_3_sram[3]:3 6.303878e-05 +4 mux_tree_tapbuf_size8_3_sram[3]:4 0.0001683673 +5 mux_tree_tapbuf_size8_3_sram[3]:5 0.0001683673 +6 mux_tree_tapbuf_size8_3_sram[3]:6 0.0004220084 +7 mux_tree_tapbuf_size8_3_sram[3]:7 0.000457298 +8 mux_tree_tapbuf_size8_3_sram[3]:8 0.0001224105 +9 mux_tree_tapbuf_size8_3_sram[3]:9 0.0001224105 +10 mux_tree_tapbuf_size8_3_sram[3]:10 6.054353e-05 +11 mux_tree_tapbuf_size8_3_sram[3]:11 6.054353e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_3_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:6 0.006120536 +2 mux_tree_tapbuf_size8_3_sram[3]:7 mux_tree_tapbuf_size8_3_sram[3]:3 0.0001465518 +3 mux_tree_tapbuf_size8_3_sram[3]:8 mux_tree_tapbuf_size8_3_sram[3]:7 0.0045 +4 mux_tree_tapbuf_size8_3_sram[3]:10 mux_tree_tapbuf_size8_3_sram[3]:9 0.0045 +5 mux_tree_tapbuf_size8_3_sram[3]:9 mux_tree_tapbuf_size8_3_sram[3]:8 0.001741071 +6 mux_tree_tapbuf_size8_3_sram[3]:11 mux_tree_tapbuf_size8_3_sram[3]:10 0.000609375 +7 mux_tree_tapbuf_size8_3_sram[3]:6 mux_tree_tapbuf_size8_3_sram[3]:5 0.0045 +8 mux_tree_tapbuf_size8_3_sram[3]:5 mux_tree_tapbuf_size8_3_sram[3]:4 0.002196429 +9 mux_tree_tapbuf_size8_3_sram[3]:4 mux_left_track_9\/mux_l4_in_0_:S 0.0045 +10 mux_tree_tapbuf_size8_3_sram[3]:3 mem_left_track_9\/FTB_4__30:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_2_ccff_tail[0] 0.0008930413 //LENGTH 6.290 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/FTB_3__29:X O *L 0 *C 20.475 63.240 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 17.195 60.860 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 *C 17.195 60.860 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 *C 17.480 60.860 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 *C 17.480 60.905 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 *C 17.480 63.195 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 *C 17.525 63.240 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 *C 20.438 63.240 + +*CAP +0 mem_left_track_3\/FTB_3__29:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 5.168971e-05 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 5.454708e-05 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.0001546354 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0001546354 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0002377668 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.0002377668 + +*RES +0 mem_left_track_3\/FTB_3__29:X mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.002600447 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[1] 0.005987971 //LENGTH 44.645 LUMPCC 0.0004316383 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 106.565 77.180 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 107.540 74.120 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 118.400 66.300 +*I mux_right_track_0\/mux_l2_in_3_:S I *L 0.00357 *C 128.460 67.320 +*I mux_right_track_0\/mux_l2_in_2_:S I *L 0.00357 *C 131.200 63.165 +*I mux_right_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 115.360 72.375 +*N mux_tree_tapbuf_size9_0_sram[1]:6 *C 115.360 72.375 +*N mux_tree_tapbuf_size9_0_sram[1]:7 *C 131.162 63.225 +*N mux_tree_tapbuf_size9_0_sram[1]:8 *C 129.765 63.240 +*N mux_tree_tapbuf_size9_0_sram[1]:9 *C 129.720 63.285 +*N mux_tree_tapbuf_size9_0_sram[1]:10 *C 129.720 66.255 +*N mux_tree_tapbuf_size9_0_sram[1]:11 *C 129.675 66.300 +*N mux_tree_tapbuf_size9_0_sram[1]:12 *C 128.340 67.320 +*N mux_tree_tapbuf_size9_0_sram[1]:13 *C 128.340 67.275 +*N mux_tree_tapbuf_size9_0_sram[1]:14 *C 128.340 66.345 +*N mux_tree_tapbuf_size9_0_sram[1]:15 *C 128.340 66.300 +*N mux_tree_tapbuf_size9_0_sram[1]:16 *C 118.438 66.300 +*N mux_tree_tapbuf_size9_0_sram[1]:17 *C 119.140 66.300 +*N mux_tree_tapbuf_size9_0_sram[1]:18 *C 119.140 66.345 +*N mux_tree_tapbuf_size9_0_sram[1]:19 *C 119.140 72.715 +*N mux_tree_tapbuf_size9_0_sram[1]:20 *C 119.095 72.760 +*N mux_tree_tapbuf_size9_0_sram[1]:21 *C 115.360 72.760 +*N mux_tree_tapbuf_size9_0_sram[1]:22 *C 112.285 72.760 +*N mux_tree_tapbuf_size9_0_sram[1]:23 *C 112.240 72.805 +*N mux_tree_tapbuf_size9_0_sram[1]:24 *C 112.240 74.415 +*N mux_tree_tapbuf_size9_0_sram[1]:25 *C 112.195 74.460 +*N mux_tree_tapbuf_size9_0_sram[1]:26 *C 107.540 74.120 +*N mux_tree_tapbuf_size9_0_sram[1]:27 *C 107.685 74.460 +*N mux_tree_tapbuf_size9_0_sram[1]:28 *C 107.640 74.505 +*N mux_tree_tapbuf_size9_0_sram[1]:29 *C 107.640 77.135 +*N mux_tree_tapbuf_size9_0_sram[1]:30 *C 107.595 77.180 +*N mux_tree_tapbuf_size9_0_sram[1]:31 *C 106.603 77.180 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_0\/mux_l2_in_3_:S 1e-06 +4 mux_right_track_0\/mux_l2_in_2_:S 1e-06 +5 mux_right_track_0\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size9_0_sram[1]:6 5.972766e-05 +7 mux_tree_tapbuf_size9_0_sram[1]:7 0.0001374662 +8 mux_tree_tapbuf_size9_0_sram[1]:8 0.0001374662 +9 mux_tree_tapbuf_size9_0_sram[1]:9 0.0002044334 +10 mux_tree_tapbuf_size9_0_sram[1]:10 0.0002044334 +11 mux_tree_tapbuf_size9_0_sram[1]:11 0.0001191063 +12 mux_tree_tapbuf_size9_0_sram[1]:12 2.943404e-05 +13 mux_tree_tapbuf_size9_0_sram[1]:13 5.886204e-05 +14 mux_tree_tapbuf_size9_0_sram[1]:14 5.886204e-05 +15 mux_tree_tapbuf_size9_0_sram[1]:15 0.0007308359 +16 mux_tree_tapbuf_size9_0_sram[1]:16 6.649249e-05 +17 mux_tree_tapbuf_size9_0_sram[1]:17 0.0006736941 +18 mux_tree_tapbuf_size9_0_sram[1]:18 0.0003628481 +19 mux_tree_tapbuf_size9_0_sram[1]:19 0.0003628481 +20 mux_tree_tapbuf_size9_0_sram[1]:20 0.0002141447 +21 mux_tree_tapbuf_size9_0_sram[1]:21 0.0004660044 +22 mux_tree_tapbuf_size9_0_sram[1]:22 0.000221302 +23 mux_tree_tapbuf_size9_0_sram[1]:23 0.000130313 +24 mux_tree_tapbuf_size9_0_sram[1]:24 0.000130313 +25 mux_tree_tapbuf_size9_0_sram[1]:25 0.0002881436 +26 mux_tree_tapbuf_size9_0_sram[1]:26 6.532847e-05 +27 mux_tree_tapbuf_size9_0_sram[1]:27 0.0003238152 +28 mux_tree_tapbuf_size9_0_sram[1]:28 0.0001728724 +29 mux_tree_tapbuf_size9_0_sram[1]:29 0.0001728724 +30 mux_tree_tapbuf_size9_0_sram[1]:30 7.935696e-05 +31 mux_tree_tapbuf_size9_0_sram[1]:31 7.935696e-05 +32 mux_tree_tapbuf_size9_0_sram[1]:25 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.516551e-05 +33 mux_tree_tapbuf_size9_0_sram[1]:24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.546992e-07 +34 mux_tree_tapbuf_size9_0_sram[1]:23 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.546992e-07 +35 mux_tree_tapbuf_size9_0_sram[1]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.408474e-06 +36 mux_tree_tapbuf_size9_0_sram[1]:20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.134709e-06 +37 mux_tree_tapbuf_size9_0_sram[1]:19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.408474e-06 +38 mux_tree_tapbuf_size9_0_sram[1]:27 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.516551e-05 +39 mux_tree_tapbuf_size9_0_sram[1]:21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.134709e-06 +40 mux_tree_tapbuf_size9_0_sram[1]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.673243e-06 +41 mux_tree_tapbuf_size9_0_sram[1]:20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.545317e-05 +42 mux_tree_tapbuf_size9_0_sram[1]:19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.673243e-06 +43 mux_tree_tapbuf_size9_0_sram[1]:21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.545317e-05 +44 mux_tree_tapbuf_size9_0_sram[1]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.461507e-05 +45 mux_tree_tapbuf_size9_0_sram[1]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.461507e-05 +46 mux_tree_tapbuf_size9_0_sram[1]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.333674e-08 +47 mux_tree_tapbuf_size9_0_sram[1]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.333674e-08 +48 mux_tree_tapbuf_size9_0_sram[1]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.181179e-05 +49 mux_tree_tapbuf_size9_0_sram[1]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.181179e-05 +50 mux_tree_tapbuf_size9_0_sram[1]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.221897e-05 +51 mux_tree_tapbuf_size9_0_sram[1]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.040143e-06 +52 mux_tree_tapbuf_size9_0_sram[1]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.221897e-05 +53 mux_tree_tapbuf_size9_0_sram[1]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.040143e-06 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size9_0_sram[1]:31 0.152 +1 mux_tree_tapbuf_size9_0_sram[1]:16 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size9_0_sram[1]:25 mux_tree_tapbuf_size9_0_sram[1]:24 0.0045 +3 mux_tree_tapbuf_size9_0_sram[1]:24 mux_tree_tapbuf_size9_0_sram[1]:23 0.0014375 +4 mux_tree_tapbuf_size9_0_sram[1]:22 mux_tree_tapbuf_size9_0_sram[1]:21 0.002745536 +5 mux_tree_tapbuf_size9_0_sram[1]:23 mux_tree_tapbuf_size9_0_sram[1]:22 0.0045 +6 mux_tree_tapbuf_size9_0_sram[1]:17 mux_tree_tapbuf_size9_0_sram[1]:16 0.0006272322 +7 mux_tree_tapbuf_size9_0_sram[1]:17 mux_tree_tapbuf_size9_0_sram[1]:15 0.008214286 +8 mux_tree_tapbuf_size9_0_sram[1]:18 mux_tree_tapbuf_size9_0_sram[1]:17 0.0045 +9 mux_tree_tapbuf_size9_0_sram[1]:20 mux_tree_tapbuf_size9_0_sram[1]:19 0.0045 +10 mux_tree_tapbuf_size9_0_sram[1]:19 mux_tree_tapbuf_size9_0_sram[1]:18 0.0056875 +11 mux_tree_tapbuf_size9_0_sram[1]:27 mux_tree_tapbuf_size9_0_sram[1]:26 0.0001847826 +12 mux_tree_tapbuf_size9_0_sram[1]:27 mux_tree_tapbuf_size9_0_sram[1]:25 0.004026786 +13 mux_tree_tapbuf_size9_0_sram[1]:28 mux_tree_tapbuf_size9_0_sram[1]:27 0.0045 +14 mux_tree_tapbuf_size9_0_sram[1]:30 mux_tree_tapbuf_size9_0_sram[1]:29 0.0045 +15 mux_tree_tapbuf_size9_0_sram[1]:29 mux_tree_tapbuf_size9_0_sram[1]:28 0.002348214 +16 mux_tree_tapbuf_size9_0_sram[1]:31 mux_tree_tapbuf_size9_0_sram[1]:30 0.0008861608 +17 mux_tree_tapbuf_size9_0_sram[1]:15 mux_tree_tapbuf_size9_0_sram[1]:14 0.0045 +18 mux_tree_tapbuf_size9_0_sram[1]:15 mux_tree_tapbuf_size9_0_sram[1]:11 0.001191964 +19 mux_tree_tapbuf_size9_0_sram[1]:14 mux_tree_tapbuf_size9_0_sram[1]:13 0.0008303572 +20 mux_tree_tapbuf_size9_0_sram[1]:12 mux_right_track_0\/mux_l2_in_3_:S 0.152 +21 mux_tree_tapbuf_size9_0_sram[1]:13 mux_tree_tapbuf_size9_0_sram[1]:12 0.0045 +22 mux_tree_tapbuf_size9_0_sram[1]:11 mux_tree_tapbuf_size9_0_sram[1]:10 0.0045 +23 mux_tree_tapbuf_size9_0_sram[1]:10 mux_tree_tapbuf_size9_0_sram[1]:9 0.002651786 +24 mux_tree_tapbuf_size9_0_sram[1]:8 mux_tree_tapbuf_size9_0_sram[1]:7 0.001247768 +25 mux_tree_tapbuf_size9_0_sram[1]:9 mux_tree_tapbuf_size9_0_sram[1]:8 0.0045 +26 mux_tree_tapbuf_size9_0_sram[1]:7 mux_right_track_0\/mux_l2_in_2_:S 0.152 +27 mux_tree_tapbuf_size9_0_sram[1]:6 mux_right_track_0\/mux_l2_in_1_:S 0.152 +28 mux_tree_tapbuf_size9_0_sram[1]:26 mux_right_track_0\/mux_l2_in_0_:S 0.152 +29 mux_tree_tapbuf_size9_0_sram[1]:21 mux_tree_tapbuf_size9_0_sram[1]:20 0.003334822 +30 mux_tree_tapbuf_size9_0_sram[1]:21 mux_tree_tapbuf_size9_0_sram[1]:6 0.00034375 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008392238 //LENGTH 6.505 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_3_:X O *L 0 *C 49.460 66.980 +*I mux_top_track_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 48.050 71.400 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 48.088 71.400 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 49.175 71.400 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 49.220 71.355 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 49.220 67.025 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 49.220 66.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 49.460 66.980 + +*CAP +0 mux_top_track_0\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.603264e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.603264e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002618463 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002618463 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.209737e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.936845e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_3_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009709823 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.782609e-05 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.006229288 //LENGTH 45.505 LUMPCC 0.002232581 DR + +*CONN +*I mux_top_track_0\/mux_l4_in_0_:X O *L 0 *C 57.785 75.480 +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.300 96.720 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 80.300 96.720 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 78.705 96.560 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 78.660 96.515 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 78.660 95.258 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 78.653 95.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 74.987 95.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 74.980 95.142 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 74.980 75.538 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 74.972 75.480 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 59.348 75.480 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 59.340 75.480 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 59.295 75.480 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 57.823 75.480 + +*CAP +0 mux_top_track_0\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001629207 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001283512 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 9.331918e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 9.331918e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000273389 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.000273389 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0007149741 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0007149741 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0006234141 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0006234141 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:12 3.877471e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.000127234 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.000127234 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 chany_top_in[11]:18 0.0002395473 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chany_top_in[11] 0.0002395473 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_top_in[11]:18 1.224826e-06 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_top_in[11] 1.224826e-06 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chany_top_in[15]:10 0.0003125387 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chany_top_in[15]:9 0.0003125387 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 chanx_left_in[1]:7 0.0003125387 +22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 chanx_left_in[1]:6 0.0003125387 +23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 optlc_net_122:11 0.000250441 +24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 optlc_net_122:10 0.000250441 + +*RES +0 mux_top_track_0\/mux_l4_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.001314732 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.00341 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.002447916 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.01750446 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.00341 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.00341 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0005741834 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001122768 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00341 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001424107 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008653171 //LENGTH 6.305 LUMPCC 0.0002629901 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_1_:X O *L 0 *C 15.005 69.020 +*I mux_left_track_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 14.090 64.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 14.128 64.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 14.675 64.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 14.720 64.305 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 14.720 68.975 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 14.720 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 15.005 69.020 + +*CAP +0 mux_left_track_3\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.762012e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.762012e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001828448 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001828448 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 4.918773e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.020934e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:539 2.652539e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:544 2.663689e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:544 2.652539e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:545 2.663689e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_2_sram[2]:8 6.762402e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size8_2_sram[2]:10 1.070877e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_2_sram[2]:9 6.762402e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size8_2_sram[2]:11 1.070877e-05 + +*RES +0 mux_left_track_3\/mux_l3_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_3\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004888393 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004169643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004242401 //LENGTH 3.055 LUMPCC 0.0001041572 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_3_:X O *L 0 *C 20.525 31.620 +*I mux_left_track_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 23.290 31.620 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 23.253 31.620 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 20.562 31.620 + +*CAP +0 mux_left_track_9\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001590415 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001590415 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_3_sram[2]:11 5.207859e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_3_sram[2]:10 5.207859e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_3_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_9\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002401786 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001696388 //LENGTH 12.275 LUMPCC 0.0007630546 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_2_:X O *L 0 *C 64.575 72.760 +*I mux_top_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 63.580 83.300 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.617 83.300 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 64.355 83.300 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 64.400 83.255 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 64.400 72.805 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 64.400 72.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 64.575 72.760 + +*CAP +0 mux_top_track_2\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.845115e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.845115e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003379169 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003379169 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.054938e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.804831e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:21 5.747102e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:23 2.733539e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:26 2.714533e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:23 5.747102e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:25 2.714533e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:26 2.733539e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002695756 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002695756 + +*RES +0 mux_top_track_2\/mux_l1_in_2_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_2\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0006584821 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.009330357 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005298243 //LENGTH 3.980 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 75.265 53.380 +*I mux_top_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 76.000 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 75.900 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 75.900 56.055 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 75.900 53.425 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 75.855 53.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 75.303 53.380 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.684127e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001636312 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001636312 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.186031e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.186031e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002348214 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004933036 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0] 0.006817043 //LENGTH 49.710 LUMPCC 0.00170658 DR + +*CONN +*I mux_top_track_6\/mux_l3_in_0_:X O *L 0 *C 86.195 51.000 +*I mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 86.180 96.730 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 86.180 96.730 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 86.480 96.560 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 86.480 96.515 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 86.480 94.578 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 86.487 94.520 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 87.380 94.520 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 87.400 94.513 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 87.400 52.367 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 87.380 52.360 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 86.487 52.360 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 86.480 52.303 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 86.480 51.045 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 86.480 51.000 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 86.195 51.000 + +*CAP +0 mux_top_track_6\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.108672e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.295145e-05 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001277616 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001277616 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.952869e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.952869e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.002011913 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.002011913 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.000103496 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.000103496 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001096914 +13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0001096914 +14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 6.240991e-05 +15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:15 5.723445e-05 +16 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0005682899 +17 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002833124 +18 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002833124 +19 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0005682899 +20 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.687569e-06 +21 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.687569e-06 + +*RES +0 mux_top_track_6\/mux_l3_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0001548913 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.001122768 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.000139825 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.006602716 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000139825 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001729911 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001630435 +13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001836775 //LENGTH 12.780 LUMPCC 0.000700288 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_0_:X O *L 0 *C 47.095 27.880 +*I mux_left_track_17\/mux_l3_in_0_:A1 I *L 0.00198 *C 37.625 25.500 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 37.663 25.500 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 41.815 25.500 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 41.860 25.545 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 41.860 27.835 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 41.905 27.880 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 47.058 27.880 + +*CAP +0 mux_left_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001928578 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001928578 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001388043 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001388043 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002355812 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002355812 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size7_5_sram[1]:10 0.0002059095 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_5_sram[1]:9 0.0002059095 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size7_5_sram[2]:10 2.449258e-06 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_5_sram[2]:9 2.449258e-06 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_5_sram[2]:8 5.491304e-06 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_5_sram[2]:6 0.0001362939 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_5_sram[2]:7 5.491304e-06 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_5_sram[2]:5 0.0001362939 + +*RES +0 mux_left_track_17\/mux_l2_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.004600447 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002044643 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.00370759 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET chanx_right_in[8] 0.02187528 //LENGTH 170.205 LUMPCC 0.009642621 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 140.450 14.960 +*I BUFT_RR_67:A I *L 0.001776 *C 11.960 34.000 +*I mux_left_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 55.490 28.220 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 99.075 39.100 +*N chanx_right_in[8]:4 *C 99.038 39.100 +*N chanx_right_in[8]:5 *C 98.025 39.100 +*N chanx_right_in[8]:6 *C 97.980 39.055 +*N chanx_right_in[8]:7 *C 55.490 28.220 +*N chanx_right_in[8]:8 *C 11.960 34.000 +*N chanx_right_in[8]:9 *C 11.960 33.955 +*N chanx_right_in[8]:10 *C 11.960 30.658 +*N chanx_right_in[8]:11 *C 11.968 30.600 +*N chanx_right_in[8]:12 *C 55.653 30.600 +*N chanx_right_in[8]:13 *C 55.660 30.543 +*N chanx_right_in[8]:14 *C 55.660 28.265 +*N chanx_right_in[8]:15 *C 55.705 28.220 +*N chanx_right_in[8]:16 *C 57.455 28.220 +*N chanx_right_in[8]:17 *C 57.500 28.175 +*N chanx_right_in[8]:18 *C 57.500 20.445 +*N chanx_right_in[8]:19 *C 57.545 20.400 +*N chanx_right_in[8]:20 *C 97.935 20.400 +*N chanx_right_in[8]:21 *C 97.980 20.400 +*N chanx_right_in[8]:22 *C 97.980 15.018 +*N chanx_right_in[8]:23 *C 97.988 14.960 + +*CAP +0 chanx_right_in[8] 0.0008929871 +1 BUFT_RR_67:A 1e-06 +2 mux_left_track_17\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +4 chanx_right_in[8]:4 8.396506e-05 +5 chanx_right_in[8]:5 8.396506e-05 +6 chanx_right_in[8]:6 0.0008521598 +7 chanx_right_in[8]:7 4.894422e-05 +8 chanx_right_in[8]:8 3.529116e-05 +9 chanx_right_in[8]:9 0.0001838846 +10 chanx_right_in[8]:10 0.0001838846 +11 chanx_right_in[8]:11 0.001590847 +12 chanx_right_in[8]:12 0.001590847 +13 chanx_right_in[8]:13 0.0001820905 +14 chanx_right_in[8]:14 0.0001820905 +15 chanx_right_in[8]:15 0.0001345468 +16 chanx_right_in[8]:16 0.000115321 +17 chanx_right_in[8]:17 0.0004379317 +18 chanx_right_in[8]:18 0.0004379317 +19 chanx_right_in[8]:19 0.001432352 +20 chanx_right_in[8]:20 0.001432352 +21 chanx_right_in[8]:21 0.001159108 +22 chanx_right_in[8]:22 0.0002761711 +23 chanx_right_in[8]:23 0.0008929872 +24 chanx_right_in[8] chanx_right_in[4] 8.138725e-05 +25 chanx_right_in[8] chanx_right_in[4]:26 0.001504586 +26 chanx_right_in[8] chanx_right_in[4]:27 0.0007133903 +27 chanx_right_in[8]:23 chanx_right_in[4]:25 0.001504586 +28 chanx_right_in[8]:23 chanx_right_in[4]:26 0.0007133903 +29 chanx_right_in[8]:23 chanx_right_in[4]:28 8.138725e-05 +30 chanx_right_in[8] chanx_right_in[14] 0.0003217938 +31 chanx_right_in[8] chanx_right_in[14]:22 0.0002234731 +32 chanx_right_in[8]:23 chanx_right_in[14]:21 0.0002234731 +33 chanx_right_in[8]:23 chanx_right_in[14]:22 0.0003217938 +34 chanx_right_in[8]:12 chanx_left_in[16]:34 5.689192e-05 +35 chanx_right_in[8]:12 chanx_left_in[16]:35 0.0006219519 +36 chanx_right_in[8]:11 chanx_left_in[16] 0.0006219519 +37 chanx_right_in[8]:11 chanx_left_in[16]:35 5.689192e-05 +38 chanx_right_in[8]:19 chanx_left_in[17]:16 0.0005513985 +39 chanx_right_in[8]:19 chanx_left_in[17]:15 0.000239372 +40 chanx_right_in[8]:20 chanx_left_in[17]:10 0.000239372 +41 chanx_right_in[8]:20 chanx_left_in[17]:15 0.0005513985 +42 chanx_right_in[8]:6 mux_tree_tapbuf_size7_3_sram[2]:5 2.798882e-05 +43 chanx_right_in[8]:6 mux_tree_tapbuf_size7_3_sram[2]:8 0.0001040296 +44 chanx_right_in[8]:21 mux_tree_tapbuf_size7_3_sram[2]:8 2.798882e-05 +45 chanx_right_in[8]:21 mux_tree_tapbuf_size7_3_sram[2]:9 0.0001040296 +46 chanx_right_in[8]:12 optlc_net_121:11 0.0003750468 +47 chanx_right_in[8]:11 optlc_net_121:10 0.0003750468 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:23 0.006652458 +1 chanx_right_in[8]:5 chanx_right_in[8]:4 0.0009040178 +2 chanx_right_in[8]:6 chanx_right_in[8]:5 0.0045 +3 chanx_right_in[8]:4 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +4 chanx_right_in[8]:15 chanx_right_in[8]:14 0.0045 +5 chanx_right_in[8]:15 chanx_right_in[8]:7 0.0001168478 +6 chanx_right_in[8]:14 chanx_right_in[8]:13 0.002033482 +7 chanx_right_in[8]:13 chanx_right_in[8]:12 0.00341 +8 chanx_right_in[8]:12 chanx_right_in[8]:11 0.006843983 +9 chanx_right_in[8]:10 chanx_right_in[8]:9 0.002944196 +10 chanx_right_in[8]:11 chanx_right_in[8]:10 0.00341 +11 chanx_right_in[8]:8 BUFT_RR_67:A 0.152 +12 chanx_right_in[8]:9 chanx_right_in[8]:8 0.0045 +13 chanx_right_in[8]:22 chanx_right_in[8]:21 0.004805804 +14 chanx_right_in[8]:23 chanx_right_in[8]:22 0.00341 +15 chanx_right_in[8]:16 chanx_right_in[8]:15 0.0015625 +16 chanx_right_in[8]:17 chanx_right_in[8]:16 0.0045 +17 chanx_right_in[8]:19 chanx_right_in[8]:18 0.0045 +18 chanx_right_in[8]:18 chanx_right_in[8]:17 0.006901786 +19 chanx_right_in[8]:20 chanx_right_in[8]:19 0.0360625 +20 chanx_right_in[8]:21 chanx_right_in[8]:20 0.0045 +21 chanx_right_in[8]:21 chanx_right_in[8]:6 0.01665625 +22 chanx_right_in[8]:7 mux_left_track_17\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET chany_top_in[1] 0.00948801 //LENGTH 66.395 LUMPCC 0.001828027 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 57.500 102.070 +*I mux_left_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.345 66.980 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 81.520 69.020 +*N chany_top_in[1]:3 *C 81.420 69.020 +*N chany_top_in[1]:4 *C 81.420 69.020 +*N chany_top_in[1]:5 *C 81.420 68.680 +*N chany_top_in[1]:6 *C 81.413 68.680 +*N chany_top_in[1]:7 *C 52.345 66.980 +*N chany_top_in[1]:8 *C 52.440 67.025 +*N chany_top_in[1]:9 *C 52.440 68.623 +*N chany_top_in[1]:10 *C 52.448 68.680 +*N chany_top_in[1]:11 *C 57.960 68.680 +*N chany_top_in[1]:12 *C 57.960 68.688 +*N chany_top_in[1]:13 *C 57.960 99.953 +*N chany_top_in[1]:14 *C 57.945 99.960 +*N chany_top_in[1]:15 *C 57.503 99.960 +*N chany_top_in[1]:16 *C 57.500 100.017 + +*CAP +0 chany_top_in[1] 0.0001069563 +1 mux_left_track_33\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[1]:3 3.255856e-05 +4 chany_top_in[1]:4 5.32788e-05 +5 chany_top_in[1]:5 5.729542e-05 +6 chany_top_in[1]:6 0.001240743 +7 chany_top_in[1]:7 3.103571e-05 +8 chany_top_in[1]:8 0.0001132323 +9 chany_top_in[1]:9 0.0001132323 +10 chany_top_in[1]:10 0.0004575139 +11 chany_top_in[1]:11 0.001698257 +12 chany_top_in[1]:12 0.00176336 +13 chany_top_in[1]:13 0.00176336 +14 chany_top_in[1]:14 6.010212e-05 +15 chany_top_in[1]:15 6.010212e-05 +16 chany_top_in[1]:16 0.0001069563 +17 chany_top_in[1]:11 chanx_left_in[2]:14 2.16599e-05 +18 chany_top_in[1]:11 chanx_left_in[2]:18 0.0004483522 +19 chany_top_in[1]:10 chanx_left_in[2]:18 2.16599e-05 +20 chany_top_in[1]:6 chanx_left_in[2]:14 0.0004483522 +21 chany_top_in[1] top_left_grid_pin_34_[0]:38 1.395534e-05 +22 chany_top_in[1]:11 top_left_grid_pin_34_[0]:34 5.737386e-05 +23 chany_top_in[1]:12 top_left_grid_pin_34_[0]:35 0.0003357381 +24 chany_top_in[1]:12 top_left_grid_pin_34_[0]:39 1.984227e-05 +25 chany_top_in[1]:14 top_left_grid_pin_34_[0]:37 1.709164e-05 +26 chany_top_in[1]:13 top_left_grid_pin_34_[0]:36 0.0003357381 +27 chany_top_in[1]:13 top_left_grid_pin_34_[0]:38 1.984227e-05 +28 chany_top_in[1]:16 top_left_grid_pin_34_[0]:39 1.395534e-05 +29 chany_top_in[1]:15 top_left_grid_pin_34_[0]:38 1.709164e-05 +30 chany_top_in[1]:6 top_left_grid_pin_34_[0]:33 5.737386e-05 + +*RES +0 chany_top_in[1] chany_top_in[1]:16 0.001832589 +1 chany_top_in[1]:11 chany_top_in[1]:10 0.000863625 +2 chany_top_in[1]:11 chany_top_in[1]:6 0.003674224 +3 chany_top_in[1]:12 chany_top_in[1]:11 0.00341 +4 chany_top_in[1]:14 chany_top_in[1]:13 0.00341 +5 chany_top_in[1]:13 chany_top_in[1]:12 0.004898183 +6 chany_top_in[1]:16 chany_top_in[1]:15 0.00341 +7 chany_top_in[1]:15 chany_top_in[1]:14 6.499219e-05 +8 chany_top_in[1]:9 chany_top_in[1]:8 0.001426339 +9 chany_top_in[1]:10 chany_top_in[1]:9 0.00341 +10 chany_top_in[1]:7 mux_left_track_33\/mux_l1_in_0_:A1 0.152 +11 chany_top_in[1]:8 chany_top_in[1]:7 0.0045 +12 chany_top_in[1]:5 chany_top_in[1]:4 0.0001634615 +13 chany_top_in[1]:6 chany_top_in[1]:5 0.00341 +14 chany_top_in[1]:3 mux_right_track_4\/mux_l1_in_0_:A1 0.152 +15 chany_top_in[1]:4 chany_top_in[1]:3 0.0045 + +*END + +*D_NET chany_top_in[4] 0.01492586 //LENGTH 86.095 LUMPCC 0.006582509 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 51.980 102.070 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 40.845 61.540 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 84.280 63.580 +*N chany_top_in[4]:3 *C 84.180 63.580 +*N chany_top_in[4]:4 *C 84.180 63.580 +*N chany_top_in[4]:5 *C 84.180 63.920 +*N chany_top_in[4]:6 *C 84.172 63.920 +*N chany_top_in[4]:7 *C 40.845 61.540 +*N chany_top_in[4]:8 *C 40.940 61.585 +*N chany_top_in[4]:9 *C 40.940 63.863 +*N chany_top_in[4]:10 *C 40.948 63.920 +*N chany_top_in[4]:11 *C 52.440 63.920 +*N chany_top_in[4]:12 *C 52.440 63.928 +*N chany_top_in[4]:13 *C 52.440 99.273 +*N chany_top_in[4]:14 *C 52.425 99.280 +*N chany_top_in[4]:15 *C 51.983 99.280 +*N chany_top_in[4]:16 *C 51.980 99.338 + +*CAP +0 chany_top_in[4] 0.0001637846 +1 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[4]:3 3.165271e-05 +4 chany_top_in[4]:4 5.250747e-05 +5 chany_top_in[4]:5 5.643172e-05 +6 chany_top_in[4]:6 0.001301282 +7 chany_top_in[4]:7 2.742546e-05 +8 chany_top_in[4]:8 0.0001538867 +9 chany_top_in[4]:9 0.0001538867 +10 chany_top_in[4]:10 0.0005732806 +11 chany_top_in[4]:11 0.001874562 +12 chany_top_in[4]:12 0.00181183 +13 chany_top_in[4]:13 0.00181183 +14 chany_top_in[4]:14 8.26017e-05 +15 chany_top_in[4]:15 8.26017e-05 +16 chany_top_in[4]:16 0.0001637846 +17 chany_top_in[4]:10 chanx_right_in[2]:15 3.969372e-05 +18 chany_top_in[4]:10 chanx_right_in[2]:23 0.000468831 +19 chany_top_in[4]:11 chanx_right_in[2]:16 3.969372e-05 +20 chany_top_in[4]:11 chanx_right_in[2]:24 0.000468831 +21 chany_top_in[4]:12 chanx_right_in[2]:15 0.0001283582 +22 chany_top_in[4]:12 chanx_right_in[2]:25 5.942773e-05 +23 chany_top_in[4]:13 chanx_right_in[2]:9 0.0001283582 +24 chany_top_in[4]:13 chanx_right_in[2]:16 5.942773e-05 +25 chany_top_in[4]:11 chanx_left_in[13]:19 0.001555268 +26 chany_top_in[4]:6 chanx_left_in[13]:18 0.001555268 +27 chany_top_in[4]:12 mux_tree_tapbuf_size2_1_sram[0]:15 0.0002831472 +28 chany_top_in[4]:12 mux_tree_tapbuf_size2_1_sram[0]:12 1.121578e-05 +29 chany_top_in[4]:13 mux_tree_tapbuf_size2_1_sram[0]:11 1.121578e-05 +30 chany_top_in[4]:13 mux_tree_tapbuf_size2_1_sram[0]:14 0.0002831472 +31 chany_top_in[4]:11 mux_tree_tapbuf_size3_1_sram[0]:15 0.0007453128 +32 chany_top_in[4]:6 mux_tree_tapbuf_size3_1_sram[0]:16 0.0007453128 + +*RES +0 chany_top_in[4] chany_top_in[4]:16 0.002439732 +1 chany_top_in[4]:9 chany_top_in[4]:8 0.002033482 +2 chany_top_in[4]:10 chany_top_in[4]:9 0.00341 +3 chany_top_in[4]:7 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +4 chany_top_in[4]:8 chany_top_in[4]:7 0.0045 +5 chany_top_in[4]:11 chany_top_in[4]:10 0.001800491 +6 chany_top_in[4]:11 chany_top_in[4]:6 0.004971425 +7 chany_top_in[4]:12 chany_top_in[4]:11 0.00341 +8 chany_top_in[4]:14 chany_top_in[4]:13 0.00341 +9 chany_top_in[4]:13 chany_top_in[4]:12 0.005537383 +10 chany_top_in[4]:16 chany_top_in[4]:15 0.00341 +11 chany_top_in[4]:15 chany_top_in[4]:14 6.499219e-05 +12 chany_top_in[4]:5 chany_top_in[4]:4 0.0001634615 +13 chany_top_in[4]:6 chany_top_in[4]:5 0.00341 +14 chany_top_in[4]:3 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +15 chany_top_in[4]:4 chany_top_in[4]:3 0.0045 + +*END + +*D_NET chany_top_in[9] 0.01069803 //LENGTH 75.395 LUMPCC 0.002973639 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 67.620 102.070 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 63.310 53.720 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 84.815 53.720 +*N chany_top_in[9]:3 *C 84.778 53.720 +*N chany_top_in[9]:4 *C 63.348 53.720 +*N chany_top_in[9]:5 *C 64.860 53.720 +*N chany_top_in[9]:6 *C 64.860 53.765 +*N chany_top_in[9]:7 *C 64.860 57.742 +*N chany_top_in[9]:8 *C 64.858 57.800 +*N chany_top_in[9]:9 *C 64.415 57.800 +*N chany_top_in[9]:10 *C 64.400 57.808 +*N chany_top_in[9]:11 *C 64.400 100.633 +*N chany_top_in[9]:12 *C 64.420 100.640 +*N chany_top_in[9]:13 *C 67.612 100.640 +*N chany_top_in[9]:14 *C 67.620 100.698 + +*CAP +0 chany_top_in[9] 9.694229e-05 +1 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[9]:3 0.00132613 +4 chany_top_in[9]:4 0.0001209135 +5 chany_top_in[9]:5 0.001484734 +6 chany_top_in[9]:6 0.0003275652 +7 chany_top_in[9]:7 0.0003275652 +8 chany_top_in[9]:8 8.593878e-05 +9 chany_top_in[9]:9 8.593878e-05 +10 chany_top_in[9]:10 0.001666692 +11 chany_top_in[9]:11 0.001666692 +12 chany_top_in[9]:12 0.000218169 +13 chany_top_in[9]:13 0.000218169 +14 chany_top_in[9]:14 9.694229e-05 +15 chany_top_in[9]:10 chany_top_in[8]:15 0.00061344 +16 chany_top_in[9]:12 chany_top_in[8]:17 9.380934e-05 +17 chany_top_in[9]:11 chany_top_in[8]:16 0.00061344 +18 chany_top_in[9]:13 chany_top_in[8]:18 9.380934e-05 +19 chany_top_in[9]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001244449 +20 chany_top_in[9]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001244449 +21 chany_top_in[9]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0006551254 +22 chany_top_in[9]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0006551254 + +*RES +0 chany_top_in[9] chany_top_in[9]:14 0.001225446 +1 chany_top_in[9]:5 chany_top_in[9]:4 0.001350446 +2 chany_top_in[9]:5 chany_top_in[9]:3 0.01778348 +3 chany_top_in[9]:6 chany_top_in[9]:5 0.0045 +4 chany_top_in[9]:7 chany_top_in[9]:6 0.003551339 +5 chany_top_in[9]:8 chany_top_in[9]:7 0.00341 +6 chany_top_in[9]:9 chany_top_in[9]:8 6.499219e-05 +7 chany_top_in[9]:10 chany_top_in[9]:9 0.00341 +8 chany_top_in[9]:12 chany_top_in[9]:11 0.00341 +9 chany_top_in[9]:11 chany_top_in[9]:10 0.006709249 +10 chany_top_in[9]:14 chany_top_in[9]:13 0.00341 +11 chany_top_in[9]:13 chany_top_in[9]:12 0.0005001583 +12 chany_top_in[9]:4 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +13 chany_top_in[9]:3 mux_right_track_8\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_top_in[11] 0.01443014 //LENGTH 95.805 LUMPCC 0.004460214 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 75.900 102.070 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 41.250 60.520 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.895 64.260 +*N chany_top_in[11]:3 *C 83.858 64.260 +*N chany_top_in[11]:4 *C 81.465 64.260 +*N chany_top_in[11]:5 *C 81.420 64.215 +*N chany_top_in[11]:6 *C 81.420 59.205 +*N chany_top_in[11]:7 *C 81.375 59.160 +*N chany_top_in[11]:8 *C 41.288 60.520 +*N chany_top_in[11]:9 *C 45.035 60.520 +*N chany_top_in[11]:10 *C 45.080 60.475 +*N chany_top_in[11]:11 *C 45.080 58.538 +*N chany_top_in[11]:12 *C 45.088 58.480 +*N chany_top_in[11]:13 *C 71.293 58.480 +*N chany_top_in[11]:14 *C 71.300 58.538 +*N chany_top_in[11]:15 *C 71.300 59.115 +*N chany_top_in[11]:16 *C 71.345 59.160 +*N chany_top_in[11]:17 *C 75.900 59.160 +*N chany_top_in[11]:18 *C 75.900 59.205 + +*CAP +0 chany_top_in[11] 0.002130377 +1 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[11]:3 0.0001579295 +4 chany_top_in[11]:4 0.0001579295 +5 chany_top_in[11]:5 0.0003097629 +6 chany_top_in[11]:6 0.0003097629 +7 chany_top_in[11]:7 0.0003774726 +8 chany_top_in[11]:8 0.0002099221 +9 chany_top_in[11]:9 0.0002099221 +10 chany_top_in[11]:10 0.0001713628 +11 chany_top_in[11]:11 0.0001713628 +12 chany_top_in[11]:12 0.001230761 +13 chany_top_in[11]:13 0.001230761 +14 chany_top_in[11]:14 6.333666e-05 +15 chany_top_in[11]:15 6.333666e-05 +16 chany_top_in[11]:16 0.0003156883 +17 chany_top_in[11]:17 0.0007278563 +18 chany_top_in[11]:18 0.002130377 +19 chany_top_in[11]:13 chany_top_in[18]:12 0.001302595 +20 chany_top_in[11]:11 chany_top_in[18]:9 7.269681e-08 +21 chany_top_in[11]:12 chany_top_in[18]:11 0.001302595 +22 chany_top_in[11]:10 chany_top_in[18]:10 7.269681e-08 +23 chany_top_in[11]:13 chany_top_in[19]:16 0.0005776896 +24 chany_top_in[11]:12 chany_top_in[19]:15 0.0005776896 +25 chany_top_in[11] mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002395473 +26 chany_top_in[11] mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.224826e-06 +27 chany_top_in[11]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0002395473 +28 chany_top_in[11]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.224826e-06 +29 chany_top_in[11]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001089783 +30 chany_top_in[11]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001089783 + +*RES +0 chany_top_in[11] chany_top_in[11]:18 0.03827232 +1 chany_top_in[11]:7 chany_top_in[11]:6 0.0045 +2 chany_top_in[11]:6 chany_top_in[11]:5 0.004473215 +3 chany_top_in[11]:4 chany_top_in[11]:3 0.002136161 +4 chany_top_in[11]:5 chany_top_in[11]:4 0.0045 +5 chany_top_in[11]:3 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +6 chany_top_in[11]:16 chany_top_in[11]:15 0.0045 +7 chany_top_in[11]:15 chany_top_in[11]:14 0.000515625 +8 chany_top_in[11]:14 chany_top_in[11]:13 0.00341 +9 chany_top_in[11]:13 chany_top_in[11]:12 0.00410545 +10 chany_top_in[11]:11 chany_top_in[11]:10 0.001729911 +11 chany_top_in[11]:12 chany_top_in[11]:11 0.00341 +12 chany_top_in[11]:9 chany_top_in[11]:8 0.003345982 +13 chany_top_in[11]:10 chany_top_in[11]:9 0.0045 +14 chany_top_in[11]:8 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +15 chany_top_in[11]:17 chany_top_in[11]:16 0.004066964 +16 chany_top_in[11]:17 chany_top_in[11]:7 0.004888393 +17 chany_top_in[11]:18 chany_top_in[11]:17 0.0045 + +*END + +*D_NET chany_top_in[13] 0.007509671 //LENGTH 54.217 LUMPCC 0.001913006 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 63.480 102.070 +*I mux_left_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 58.710 80.920 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 85.735 80.580 +*N chany_top_in[13]:3 *C 85.698 80.580 +*N chany_top_in[13]:4 *C 84.225 80.580 +*N chany_top_in[13]:5 *C 84.180 80.580 +*N chany_top_in[13]:6 *C 84.180 80.920 +*N chany_top_in[13]:7 *C 84.172 80.920 +*N chany_top_in[13]:8 *C 59.348 80.920 +*N chany_top_in[13]:9 *C 58.748 80.920 +*N chany_top_in[13]:10 *C 59.295 80.920 +*N chany_top_in[13]:11 *C 59.340 80.920 +*N chany_top_in[13]:12 *C 59.340 90.383 +*N chany_top_in[13]:13 *C 59.348 90.440 +*N chany_top_in[13]:14 *C 63.473 90.440 +*N chany_top_in[13]:15 *C 63.480 90.498 + +*CAP +0 chany_top_in[13] 0.0004879092 +1 mux_left_track_3\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[13]:3 0.0001370037 +4 chany_top_in[13]:4 0.0001370037 +5 chany_top_in[13]:5 5.409422e-05 +6 chany_top_in[13]:6 5.868634e-05 +7 chany_top_in[13]:7 0.001279911 +8 chany_top_in[13]:8 0.001279911 +9 chany_top_in[13]:9 5.129585e-05 +10 chany_top_in[13]:10 5.129585e-05 +11 chany_top_in[13]:11 0.0005481791 +12 chany_top_in[13]:12 0.0005131675 +13 chany_top_in[13]:13 0.000254149 +14 chany_top_in[13]:14 0.000254149 +15 chany_top_in[13]:15 0.0004879092 +16 chany_top_in[13] prog_clk[0]:175 2.306707e-06 +17 chany_top_in[13]:12 prog_clk[0]:339 3.926628e-05 +18 chany_top_in[13]:13 prog_clk[0]:176 2.748074e-05 +19 chany_top_in[13]:13 prog_clk[0]:177 2.325561e-05 +20 chany_top_in[13]:13 prog_clk[0]:183 2.318916e-07 +21 chany_top_in[13]:15 prog_clk[0]:174 2.306707e-06 +22 chany_top_in[13]:14 prog_clk[0]:171 2.748074e-05 +23 chany_top_in[13]:14 prog_clk[0]:176 2.325561e-05 +24 chany_top_in[13]:14 prog_clk[0]:182 2.318916e-07 +25 chany_top_in[13]:11 prog_clk[0]:338 3.926628e-05 +26 chany_top_in[13]:8 prog_clk[0]:188 1.055891e-05 +27 chany_top_in[13]:8 prog_clk[0]:317 7.589805e-06 +28 chany_top_in[13]:8 prog_clk[0]:340 0.0001453183 +29 chany_top_in[13]:8 prog_clk[0]:341 1.239235e-05 +30 chany_top_in[13]:7 prog_clk[0]:187 1.055891e-05 +31 chany_top_in[13]:7 prog_clk[0]:318 7.589805e-06 +32 chany_top_in[13]:7 prog_clk[0]:320 0.0001453183 +33 chany_top_in[13]:7 prog_clk[0]:340 1.239235e-05 +34 chany_top_in[13]:10 chany_top_in[6]:8 8.373349e-06 +35 chany_top_in[13]:9 chany_top_in[6]:7 8.373349e-06 +36 chany_top_in[13]:8 chany_top_in[6]:11 0.0002785544 +37 chany_top_in[13]:8 chany_top_in[6]:12 0.0001642989 +38 chany_top_in[13]:7 chany_top_in[6]:6 0.0001642989 +39 chany_top_in[13]:7 chany_top_in[6]:12 0.0002785544 +40 chany_top_in[13] mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002368757 +41 chany_top_in[13]:15 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002368757 + +*RES +0 chany_top_in[13] chany_top_in[13]:15 0.01033259 +1 chany_top_in[13]:12 chany_top_in[13]:11 0.008448661 +2 chany_top_in[13]:13 chany_top_in[13]:12 0.00341 +3 chany_top_in[13]:15 chany_top_in[13]:14 0.00341 +4 chany_top_in[13]:14 chany_top_in[13]:13 0.0006462499 +5 chany_top_in[13]:10 chany_top_in[13]:9 0.0004888393 +6 chany_top_in[13]:11 chany_top_in[13]:10 0.0045 +7 chany_top_in[13]:11 chany_top_in[13]:8 0.00341 +8 chany_top_in[13]:9 mux_left_track_3\/mux_l1_in_0_:A0 0.152 +9 chany_top_in[13]:8 chany_top_in[13]:7 0.00388925 +10 chany_top_in[13]:6 chany_top_in[13]:5 0.0001634616 +11 chany_top_in[13]:7 chany_top_in[13]:6 0.00341 +12 chany_top_in[13]:4 chany_top_in[13]:3 0.001314732 +13 chany_top_in[13]:5 chany_top_in[13]:4 0.0045 +14 chany_top_in[13]:3 mux_right_track_0\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_top_in[18] 0.01683833 //LENGTH 111.535 LUMPCC 0.005054891 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 84.640 102.070 +*I mux_right_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 92.365 63.580 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 35.250 55.080 +*N chany_top_in[18]:3 *C 35.212 55.080 +*N chany_top_in[18]:4 *C 33.625 55.080 +*N chany_top_in[18]:5 *C 33.580 55.125 +*N chany_top_in[18]:6 *C 33.580 56.395 +*N chany_top_in[18]:7 *C 33.625 56.440 +*N chany_top_in[18]:8 *C 47.335 56.440 +*N chany_top_in[18]:9 *C 47.380 56.485 +*N chany_top_in[18]:10 *C 47.380 59.103 +*N chany_top_in[18]:11 *C 47.388 59.160 +*N chany_top_in[18]:12 *C 85.093 59.160 +*N chany_top_in[18]:13 *C 85.100 59.218 +*N chany_top_in[18]:14 *C 92.328 63.580 +*N chany_top_in[18]:15 *C 91.540 63.580 +*N chany_top_in[18]:16 *C 91.540 63.920 +*N chany_top_in[18]:17 *C 86.940 63.920 +*N chany_top_in[18]:18 *C 86.940 64.260 +*N chany_top_in[18]:19 *C 85.145 64.260 +*N chany_top_in[18]:20 *C 85.100 64.260 +*N chany_top_in[18]:21 *C 85.100 100.640 +*N chany_top_in[18]:22 *C 84.640 100.640 + +*CAP +0 chany_top_in[18] 9.84692e-05 +1 mux_right_track_24\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +3 chany_top_in[18]:3 0.0001341432 +4 chany_top_in[18]:4 0.0001341432 +5 chany_top_in[18]:5 9.42468e-05 +6 chany_top_in[18]:6 9.42468e-05 +7 chany_top_in[18]:7 0.001037118 +8 chany_top_in[18]:8 0.001037118 +9 chany_top_in[18]:9 0.0001694626 +10 chany_top_in[18]:10 0.0001694626 +11 chany_top_in[18]:11 0.001435339 +12 chany_top_in[18]:12 0.001435339 +13 chany_top_in[18]:13 0.0002989794 +14 chany_top_in[18]:14 7.642165e-05 +15 chany_top_in[18]:15 0.0001026739 +16 chany_top_in[18]:16 0.0002996403 +17 chany_top_in[18]:17 0.0002973275 +18 chany_top_in[18]:18 0.0001621542 +19 chany_top_in[18]:19 0.0001382149 +20 chany_top_in[18]:20 0.002372034 +21 chany_top_in[18]:21 0.002068773 +22 chany_top_in[18]:22 0.0001261373 +23 chany_top_in[18]:20 chanx_left_in[10]:21 1.337351e-05 +24 chany_top_in[18]:12 chanx_left_in[10]:27 0.0005688686 +25 chany_top_in[18]:12 chanx_left_in[10]:29 2.02106e-05 +26 chany_top_in[18]:11 chanx_left_in[10]:28 0.0005688686 +27 chany_top_in[18]:11 chanx_left_in[10]:30 2.02106e-05 +28 chany_top_in[18]:21 chanx_left_in[10]:20 1.337351e-05 +29 chany_top_in[18]:12 chany_top_in[11]:13 0.001302595 +30 chany_top_in[18]:10 chany_top_in[11]:10 7.269681e-08 +31 chany_top_in[18]:11 chany_top_in[11]:12 0.001302595 +32 chany_top_in[18]:9 chany_top_in[11]:11 7.269681e-08 +33 chany_top_in[18]:12 mux_tree_tapbuf_size3_0_sram[0]:18 0.0005540893 +34 chany_top_in[18]:11 mux_tree_tapbuf_size3_0_sram[0]:17 0.0005540893 +35 chany_top_in[18]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.823608e-05 +36 chany_top_in[18]:16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.823608e-05 + +*RES +0 chany_top_in[18] chany_top_in[18]:22 0.001276786 +1 chany_top_in[18]:19 chany_top_in[18]:18 0.001602679 +2 chany_top_in[18]:20 chany_top_in[18]:19 0.0045 +3 chany_top_in[18]:20 chany_top_in[18]:13 0.004502232 +4 chany_top_in[18]:14 mux_right_track_24\/mux_l1_in_1_:A1 0.152 +5 chany_top_in[18]:13 chany_top_in[18]:12 0.00341 +6 chany_top_in[18]:12 chany_top_in[18]:11 0.005907116 +7 chany_top_in[18]:10 chany_top_in[18]:9 0.002337054 +8 chany_top_in[18]:11 chany_top_in[18]:10 0.00341 +9 chany_top_in[18]:8 chany_top_in[18]:7 0.01224107 +10 chany_top_in[18]:9 chany_top_in[18]:8 0.0045 +11 chany_top_in[18]:7 chany_top_in[18]:6 0.0045 +12 chany_top_in[18]:6 chany_top_in[18]:5 0.001133929 +13 chany_top_in[18]:4 chany_top_in[18]:3 0.001417411 +14 chany_top_in[18]:5 chany_top_in[18]:4 0.0045 +15 chany_top_in[18]:3 mux_left_track_9\/mux_l2_in_0_:A0 0.152 +16 chany_top_in[18]:18 chany_top_in[18]:17 0.0003035715 +17 chany_top_in[18]:17 chany_top_in[18]:16 0.004107143 +18 chany_top_in[18]:16 chany_top_in[18]:15 0.0003035715 +19 chany_top_in[18]:15 chany_top_in[18]:14 0.000703125 +20 chany_top_in[18]:22 chany_top_in[18]:21 0.0004107143 +21 chany_top_in[18]:21 chany_top_in[18]:20 0.03248215 + +*END + +*D_NET top_left_grid_pin_36_[0] 0.01549776 //LENGTH 124.560 LUMPCC 0.002883702 DR + +*CONN +*P top_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 99.960 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 62.850 66.300 +*I mux_top_track_28\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.740 23.460 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.875 49.980 +*I mux_top_track_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 68.180 58.140 +*N top_left_grid_pin_36_[0]:5 *C 68.180 58.140 +*N top_left_grid_pin_36_[0]:6 *C 68.080 58.480 +*N top_left_grid_pin_36_[0]:7 *C 66.838 49.980 +*N top_left_grid_pin_36_[0]:8 *C 61.640 23.460 +*N top_left_grid_pin_36_[0]:9 *C 61.640 23.505 +*N top_left_grid_pin_36_[0]:10 *C 61.640 49.935 +*N top_left_grid_pin_36_[0]:11 *C 61.685 49.980 +*N top_left_grid_pin_36_[0]:12 *C 65.320 49.980 +*N top_left_grid_pin_36_[0]:13 *C 65.320 50.025 +*N top_left_grid_pin_36_[0]:14 *C 65.320 58.435 +*N top_left_grid_pin_36_[0]:15 *C 65.320 58.480 +*N top_left_grid_pin_36_[0]:16 *C 63.525 58.480 +*N top_left_grid_pin_36_[0]:17 *C 63.480 58.525 +*N top_left_grid_pin_36_[0]:18 *C 62.888 66.300 +*N top_left_grid_pin_36_[0]:19 *C 63.435 66.300 +*N top_left_grid_pin_36_[0]:20 *C 63.480 66.300 +*N top_left_grid_pin_36_[0]:21 *C 63.480 77.815 +*N top_left_grid_pin_36_[0]:22 *C 63.435 77.860 +*N top_left_grid_pin_36_[0]:23 *C 57.085 77.860 +*N top_left_grid_pin_36_[0]:24 *C 57.040 77.905 +*N top_left_grid_pin_36_[0]:25 *C 57.040 91.743 +*N top_left_grid_pin_36_[0]:26 *C 57.033 91.800 +*N top_left_grid_pin_36_[0]:27 *C 31.300 91.800 +*N top_left_grid_pin_36_[0]:28 *C 31.280 91.808 +*N top_left_grid_pin_36_[0]:29 *C 31.280 99.953 +*N top_left_grid_pin_36_[0]:30 *C 31.260 99.960 + +*CAP +0 top_left_grid_pin_36_[0] 0.0001103272 +1 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_28\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +4 mux_top_track_12\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_36_[0]:5 5.796306e-05 +6 top_left_grid_pin_36_[0]:6 0.0002029365 +7 top_left_grid_pin_36_[0]:7 0.0001042705 +8 top_left_grid_pin_36_[0]:8 3.270695e-05 +9 top_left_grid_pin_36_[0]:9 0.001411863 +10 top_left_grid_pin_36_[0]:10 0.001411863 +11 top_left_grid_pin_36_[0]:11 0.0002260997 +12 top_left_grid_pin_36_[0]:12 0.0003673275 +13 top_left_grid_pin_36_[0]:13 0.0005218838 +14 top_left_grid_pin_36_[0]:14 0.0005218838 +15 top_left_grid_pin_36_[0]:15 0.0003300554 +16 top_left_grid_pin_36_[0]:16 0.0001205804 +17 top_left_grid_pin_36_[0]:17 0.0003243939 +18 top_left_grid_pin_36_[0]:18 5.718865e-05 +19 top_left_grid_pin_36_[0]:19 5.718865e-05 +20 top_left_grid_pin_36_[0]:20 0.0008464436 +21 top_left_grid_pin_36_[0]:21 0.0004876227 +22 top_left_grid_pin_36_[0]:22 0.0003912969 +23 top_left_grid_pin_36_[0]:23 0.0003912969 +24 top_left_grid_pin_36_[0]:24 0.0007569393 +25 top_left_grid_pin_36_[0]:25 0.0007569393 +26 top_left_grid_pin_36_[0]:26 0.001082633 +27 top_left_grid_pin_36_[0]:27 0.001082633 +28 top_left_grid_pin_36_[0]:28 0.0004226957 +29 top_left_grid_pin_36_[0]:29 0.0004226957 +30 top_left_grid_pin_36_[0]:30 0.0001103272 +31 top_left_grid_pin_36_[0]:26 top_left_grid_pin_37_[0]:24 0.0003650795 +32 top_left_grid_pin_36_[0]:27 top_left_grid_pin_37_[0]:25 0.0003650795 +33 top_left_grid_pin_36_[0]:24 top_left_grid_pin_41_[0]:21 3.216045e-05 +34 top_left_grid_pin_36_[0]:25 top_left_grid_pin_41_[0]:22 3.216045e-05 +35 top_left_grid_pin_36_[0]:26 top_left_grid_pin_41_[0]:28 0.0004800965 +36 top_left_grid_pin_36_[0]:27 top_left_grid_pin_41_[0] 0.0004800965 +37 top_left_grid_pin_36_[0]:10 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.065393e-05 +38 top_left_grid_pin_36_[0]:9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.065393e-05 +39 top_left_grid_pin_36_[0]:17 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001994914 +40 top_left_grid_pin_36_[0]:14 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.558479e-06 +41 top_left_grid_pin_36_[0]:13 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.558479e-06 +42 top_left_grid_pin_36_[0]:21 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002998108 +43 top_left_grid_pin_36_[0]:20 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001994914 +44 top_left_grid_pin_36_[0]:20 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002998108 + +*RES +0 top_left_grid_pin_36_[0] top_left_grid_pin_36_[0]:30 0.0002365667 +1 top_left_grid_pin_36_[0]:11 top_left_grid_pin_36_[0]:10 0.0045 +2 top_left_grid_pin_36_[0]:10 top_left_grid_pin_36_[0]:9 0.02359822 +3 top_left_grid_pin_36_[0]:8 mux_top_track_28\/mux_l1_in_0_:A1 0.152 +4 top_left_grid_pin_36_[0]:9 top_left_grid_pin_36_[0]:8 0.0045 +5 top_left_grid_pin_36_[0]:16 top_left_grid_pin_36_[0]:15 0.001602679 +6 top_left_grid_pin_36_[0]:17 top_left_grid_pin_36_[0]:16 0.0045 +7 top_left_grid_pin_36_[0]:15 top_left_grid_pin_36_[0]:14 0.0045 +8 top_left_grid_pin_36_[0]:15 top_left_grid_pin_36_[0]:6 0.002464286 +9 top_left_grid_pin_36_[0]:14 top_left_grid_pin_36_[0]:13 0.007508929 +10 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:11 0.003245536 +11 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:7 0.001354911 +12 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:12 0.0045 +13 top_left_grid_pin_36_[0]:22 top_left_grid_pin_36_[0]:21 0.0045 +14 top_left_grid_pin_36_[0]:21 top_left_grid_pin_36_[0]:20 0.01028125 +15 top_left_grid_pin_36_[0]:23 top_left_grid_pin_36_[0]:22 0.005669643 +16 top_left_grid_pin_36_[0]:24 top_left_grid_pin_36_[0]:23 0.0045 +17 top_left_grid_pin_36_[0]:25 top_left_grid_pin_36_[0]:24 0.01235491 +18 top_left_grid_pin_36_[0]:26 top_left_grid_pin_36_[0]:25 0.00341 +19 top_left_grid_pin_36_[0]:27 top_left_grid_pin_36_[0]:26 0.004031424 +20 top_left_grid_pin_36_[0]:28 top_left_grid_pin_36_[0]:27 0.00341 +21 top_left_grid_pin_36_[0]:30 top_left_grid_pin_36_[0]:29 0.00341 +22 top_left_grid_pin_36_[0]:29 top_left_grid_pin_36_[0]:28 0.00127605 +23 top_left_grid_pin_36_[0]:5 mux_top_track_12\/mux_l1_in_0_:A1 0.152 +24 top_left_grid_pin_36_[0]:7 mux_top_track_4\/mux_l1_in_0_:A0 0.152 +25 top_left_grid_pin_36_[0]:19 top_left_grid_pin_36_[0]:18 0.0004888393 +26 top_left_grid_pin_36_[0]:20 top_left_grid_pin_36_[0]:19 0.0045 +27 top_left_grid_pin_36_[0]:20 top_left_grid_pin_36_[0]:17 0.006941965 +28 top_left_grid_pin_36_[0]:18 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +29 top_left_grid_pin_36_[0]:6 top_left_grid_pin_36_[0]:5 0.0003035715 + +*END + +*D_NET chanx_right_in[0] 0.01396748 //LENGTH 99.195 LUMPCC 0.003192302 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 140.450 46.240 +*I mux_top_track_38\/mux_l1_in_0_:A0 I *L 0.001631 *C 81.135 82.620 +*N chanx_right_in[0]:2 *C 81.135 82.620 +*N chanx_right_in[0]:3 *C 80.960 82.960 +*N chanx_right_in[0]:4 *C 85.975 82.960 +*N chanx_right_in[0]:5 *C 86.020 82.960 +*N chanx_right_in[0]:6 *C 86.028 82.960 +*N chanx_right_in[0]:7 *C 110.853 82.960 +*N chanx_right_in[0]:8 *C 110.860 82.903 +*N chanx_right_in[0]:9 *C 110.860 74.858 +*N chanx_right_in[0]:10 *C 110.868 74.800 +*N chanx_right_in[0]:11 *C 112.220 74.800 +*N chanx_right_in[0]:12 *C 112.240 74.793 +*N chanx_right_in[0]:13 *C 112.240 52.367 +*N chanx_right_in[0]:14 *C 112.260 52.360 +*N chanx_right_in[0]:15 *C 137.073 52.360 +*N chanx_right_in[0]:16 *C 137.080 52.303 +*N chanx_right_in[0]:17 *C 137.080 46.297 +*N chanx_right_in[0]:18 *C 137.088 46.240 + +*CAP +0 chanx_right_in[0] 0.0002486425 +1 mux_top_track_38\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[0]:2 5.774698e-05 +3 chanx_right_in[0]:3 0.0003716668 +4 chanx_right_in[0]:4 0.000345003 +5 chanx_right_in[0]:5 3.618158e-05 +6 chanx_right_in[0]:6 0.001463457 +7 chanx_right_in[0]:7 0.001463457 +8 chanx_right_in[0]:8 0.0004743976 +9 chanx_right_in[0]:9 0.0004743976 +10 chanx_right_in[0]:10 0.0001399831 +11 chanx_right_in[0]:11 0.0001399831 +12 chanx_right_in[0]:12 0.00116963 +13 chanx_right_in[0]:13 0.00116963 +14 chanx_right_in[0]:14 0.001138669 +15 chanx_right_in[0]:15 0.001138669 +16 chanx_right_in[0]:16 0.0003470115 +17 chanx_right_in[0]:17 0.0003470115 +18 chanx_right_in[0]:18 0.0002486425 +19 chanx_right_in[0]:14 chanx_left_in[18]:12 0.0008325791 +20 chanx_right_in[0]:15 chanx_left_in[18]:8 0.0008325791 +21 chanx_right_in[0]:6 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 0.0001427393 +22 chanx_right_in[0]:7 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 0.0001427393 +23 chanx_right_in[0]:14 mux_tree_tapbuf_size8_1_sram[1]:25 0.0003330982 +24 chanx_right_in[0]:15 mux_tree_tapbuf_size8_1_sram[1]:24 0.0003330982 +25 chanx_right_in[0]:8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.983668e-05 +26 chanx_right_in[0]:9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 1.983668e-05 +27 chanx_right_in[0]:12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002678976 +28 chanx_right_in[0]:13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002678976 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:18 0.0005267917 +1 chanx_right_in[0]:2 mux_top_track_38\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[0]:4 chanx_right_in[0]:3 0.004477679 +3 chanx_right_in[0]:5 chanx_right_in[0]:4 0.0045 +4 chanx_right_in[0]:6 chanx_right_in[0]:5 0.00341 +5 chanx_right_in[0]:8 chanx_right_in[0]:7 0.00341 +6 chanx_right_in[0]:7 chanx_right_in[0]:6 0.00388925 +7 chanx_right_in[0]:9 chanx_right_in[0]:8 0.007183036 +8 chanx_right_in[0]:10 chanx_right_in[0]:9 0.00341 +9 chanx_right_in[0]:11 chanx_right_in[0]:10 0.0002118916 +10 chanx_right_in[0]:12 chanx_right_in[0]:11 0.00341 +11 chanx_right_in[0]:14 chanx_right_in[0]:13 0.00341 +12 chanx_right_in[0]:13 chanx_right_in[0]:12 0.00351325 +13 chanx_right_in[0]:16 chanx_right_in[0]:15 0.00341 +14 chanx_right_in[0]:15 chanx_right_in[0]:14 0.003887291 +15 chanx_right_in[0]:17 chanx_right_in[0]:16 0.005361608 +16 chanx_right_in[0]:18 chanx_right_in[0]:17 0.00341 +17 chanx_right_in[0]:3 chanx_right_in[0]:2 0.0003035715 + +*END + +*D_NET chanx_right_in[3] 0.0152986 //LENGTH 141.015 LUMPCC 0.001152782 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 140.382 8.160 +*I mux_top_track_2\/mux_l1_in_2_:A1 I *L 0.00198 *C 66.145 72.420 +*N chanx_right_in[3]:2 *C 66.183 72.420 +*N chanx_right_in[3]:3 *C 68.495 72.420 +*N chanx_right_in[3]:4 *C 68.540 72.375 +*N chanx_right_in[3]:5 *C 68.540 54.458 +*N chanx_right_in[3]:6 *C 68.547 54.400 +*N chanx_right_in[3]:7 *C 69.913 54.400 +*N chanx_right_in[3]:8 *C 69.920 54.343 +*N chanx_right_in[3]:9 *C 69.920 14.960 +*N chanx_right_in[3]:10 *C 70.380 14.960 +*N chanx_right_in[3]:11 *C 70.380 9.225 +*N chanx_right_in[3]:12 *C 70.425 9.180 +*N chanx_right_in[3]:13 *C 120.220 9.180 +*N chanx_right_in[3]:14 *C 140.255 9.180 +*N chanx_right_in[3]:15 *C 140.300 9.135 +*N chanx_right_in[3]:16 *C 140.300 8.218 +*N chanx_right_in[3]:17 *C 140.300 8.160 + +*CAP +0 chanx_right_in[3] 2.47807e-05 +1 mux_top_track_2\/mux_l1_in_2_:A1 1e-06 +2 chanx_right_in[3]:2 0.0001952141 +3 chanx_right_in[3]:3 0.0001952141 +4 chanx_right_in[3]:4 0.0007106717 +5 chanx_right_in[3]:5 0.0007106717 +6 chanx_right_in[3]:6 0.0001849452 +7 chanx_right_in[3]:7 0.0001849452 +8 chanx_right_in[3]:8 0.002129441 +9 chanx_right_in[3]:9 0.00215862 +10 chanx_right_in[3]:10 0.000321218 +11 chanx_right_in[3]:11 0.0002920389 +12 chanx_right_in[3]:12 0.002442524 +13 chanx_right_in[3]:13 0.003448061 +14 chanx_right_in[3]:14 0.001005537 +15 chanx_right_in[3]:15 5.80773e-05 +16 chanx_right_in[3]:16 5.80773e-05 +17 chanx_right_in[3]:17 2.47807e-05 +18 chanx_right_in[3]:4 chany_top_in[16]:12 8.810548e-05 +19 chanx_right_in[3]:4 chany_top_in[16]:13 0.000383084 +20 chanx_right_in[3]:5 chany_top_in[16]:5 8.810548e-05 +21 chanx_right_in[3]:5 chany_top_in[16]:12 0.000383084 +22 chanx_right_in[3]:6 chany_top_in[16]:11 2.365971e-06 +23 chanx_right_in[3]:8 chany_top_in[16]:12 5.085246e-05 +24 chanx_right_in[3]:7 chany_top_in[16]:10 2.365971e-06 +25 chanx_right_in[3]:9 chany_top_in[16]:5 5.085246e-05 +26 chanx_right_in[3]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.198288e-05 +27 chanx_right_in[3]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.198288e-05 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:17 2.35e-05 +1 chanx_right_in[3]:2 mux_top_track_2\/mux_l1_in_2_:A1 0.152 +2 chanx_right_in[3]:3 chanx_right_in[3]:2 0.002064733 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0045 +4 chanx_right_in[3]:5 chanx_right_in[3]:4 0.01599777 +5 chanx_right_in[3]:6 chanx_right_in[3]:5 0.00341 +6 chanx_right_in[3]:8 chanx_right_in[3]:7 0.00341 +7 chanx_right_in[3]:7 chanx_right_in[3]:6 0.00021385 +8 chanx_right_in[3]:12 chanx_right_in[3]:11 0.0045 +9 chanx_right_in[3]:11 chanx_right_in[3]:10 0.005120536 +10 chanx_right_in[3]:14 chanx_right_in[3]:13 0.0178884 +11 chanx_right_in[3]:15 chanx_right_in[3]:14 0.0045 +12 chanx_right_in[3]:16 chanx_right_in[3]:15 0.0008191965 +13 chanx_right_in[3]:17 chanx_right_in[3]:16 0.00341 +14 chanx_right_in[3]:9 chanx_right_in[3]:8 0.03516295 +15 chanx_right_in[3]:10 chanx_right_in[3]:9 0.0004107143 +16 chanx_right_in[3]:13 chanx_right_in[3]:12 0.04445983 + +*END + +*D_NET chanx_right_in[7] 0.009816295 //LENGTH 65.240 LUMPCC 0.004103794 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 140.375 47.600 +*I mux_top_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 78.030 49.640 +*N chanx_right_in[7]:2 *C 78.030 49.640 +*N chanx_right_in[7]:3 *C 78.200 49.640 +*N chanx_right_in[7]:4 *C 78.200 49.595 +*N chanx_right_in[7]:5 *C 78.200 48.338 +*N chanx_right_in[7]:6 *C 78.208 48.280 +*N chanx_right_in[7]:7 *C 128.035 48.280 +*N chanx_right_in[7]:8 *C 140.300 48.280 + +*CAP +0 chanx_right_in[7] 5.103936e-05 +1 mux_top_track_4\/mux_l1_in_2_:A0 1e-06 +2 chanx_right_in[7]:2 5.017731e-05 +3 chanx_right_in[7]:3 5.453132e-05 +4 chanx_right_in[7]:4 6.888935e-05 +5 chanx_right_in[7]:5 6.888935e-05 +6 chanx_right_in[7]:6 0.002116059 +7 chanx_right_in[7]:7 0.002683468 +8 chanx_right_in[7]:8 0.0006184482 +9 chanx_right_in[7]:4 chanx_right_in[18]:19 3.167986e-06 +10 chanx_right_in[7]:5 chanx_right_in[18]:23 3.167986e-06 +11 chanx_right_in[7]:6 chanx_right_in[18]:24 5.465669e-06 +12 chanx_right_in[7]:6 chanx_right_in[18]:28 0.0003874587 +13 chanx_right_in[7]:8 chanx_right_in[18] 0.0001833646 +14 chanx_right_in[7]:7 chanx_right_in[18] 0.0003874587 +15 chanx_right_in[7]:7 chanx_right_in[18]:25 5.465669e-06 +16 chanx_right_in[7]:7 chanx_right_in[18]:28 0.0001833646 +17 chanx_right_in[7]:6 chanx_left_in[6]:20 0.0003872563 +18 chanx_right_in[7]:7 chanx_left_in[6]:19 0.0003872563 +19 chanx_right_in[7]:4 prog_clk[0]:298 4.230829e-05 +20 chanx_right_in[7]:5 prog_clk[0]:292 4.230829e-05 +21 chanx_right_in[7]:6 prog_clk[0]:244 0.0002430885 +22 chanx_right_in[7]:6 prog_clk[0]:248 0.0002284681 +23 chanx_right_in[7]:6 prog_clk[0]:253 0.0003013224 +24 chanx_right_in[7]:6 prog_clk[0]:254 0.0001578866 +25 chanx_right_in[7]:6 prog_clk[0]:267 7.357873e-05 +26 chanx_right_in[7]:6 prog_clk[0]:268 3.853133e-05 +27 chanx_right_in[7]:7 prog_clk[0]:223 0.0002430885 +28 chanx_right_in[7]:7 prog_clk[0]:244 0.0002284681 +29 chanx_right_in[7]:7 prog_clk[0]:248 0.0003013224 +30 chanx_right_in[7]:7 prog_clk[0]:253 0.0001578866 +31 chanx_right_in[7]:7 prog_clk[0]:259 7.357873e-05 +32 chanx_right_in[7]:7 prog_clk[0]:267 3.853133e-05 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:8 0.0001065333 +1 chanx_right_in[7]:2 mux_top_track_4\/mux_l1_in_2_:A0 0.152 +2 chanx_right_in[7]:3 chanx_right_in[7]:2 9.239131e-05 +3 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0045 +4 chanx_right_in[7]:5 chanx_right_in[7]:4 0.001122768 +5 chanx_right_in[7]:6 chanx_right_in[7]:5 0.00341 +6 chanx_right_in[7]:8 chanx_right_in[7]:7 0.001921517 +7 chanx_right_in[7]:7 chanx_right_in[7]:6 0.007806308 + +*END + +*D_NET right_top_grid_pin_43_[0] 0.0133175 //LENGTH 107.965 LUMPCC 0.001429062 DR + +*CONN +*P right_top_grid_pin_43_[0] I *L 0.29796 *C 111.930 99.280 +*I mux_right_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 105.900 69.020 +*I mux_right_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 91.285 37.060 +*I mux_right_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 88.955 93.160 +*N right_top_grid_pin_43_[0]:4 *C 88.955 93.160 +*N right_top_grid_pin_43_[0]:5 *C 89.240 93.160 +*N right_top_grid_pin_43_[0]:6 *C 89.240 93.115 +*N right_top_grid_pin_43_[0]:7 *C 89.240 88.458 +*N right_top_grid_pin_43_[0]:8 *C 89.248 88.400 +*N right_top_grid_pin_43_[0]:9 *C 91.323 37.060 +*N right_top_grid_pin_43_[0]:10 *C 93.795 37.060 +*N right_top_grid_pin_43_[0]:11 *C 93.840 37.060 +*N right_top_grid_pin_43_[0]:12 *C 93.840 37.400 +*N right_top_grid_pin_43_[0]:13 *C 93.848 37.400 +*N right_top_grid_pin_43_[0]:14 *C 103.020 37.400 +*N right_top_grid_pin_43_[0]:15 *C 103.040 37.407 +*N right_top_grid_pin_43_[0]:16 *C 103.040 67.993 +*N right_top_grid_pin_43_[0]:17 *C 103.060 68.000 +*N right_top_grid_pin_43_[0]:18 *C 105.793 68.000 +*N right_top_grid_pin_43_[0]:19 *C 105.800 68.058 +*N right_top_grid_pin_43_[0]:20 *C 105.900 69.020 +*N right_top_grid_pin_43_[0]:21 *C 105.800 69.360 +*N right_top_grid_pin_43_[0]:22 *C 105.800 69.360 +*N right_top_grid_pin_43_[0]:23 *C 105.800 88.343 +*N right_top_grid_pin_43_[0]:24 *C 105.800 88.400 +*N right_top_grid_pin_43_[0]:25 *C 110.853 88.400 +*N right_top_grid_pin_43_[0]:26 *C 110.860 88.458 +*N right_top_grid_pin_43_[0]:27 *C 110.860 99.223 +*N right_top_grid_pin_43_[0]:28 *C 110.868 99.280 + +*CAP +0 right_top_grid_pin_43_[0] 6.322727e-05 +1 mux_right_track_4\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_43_[0]:4 5.554865e-05 +5 right_top_grid_pin_43_[0]:5 6.230411e-05 +6 right_top_grid_pin_43_[0]:6 0.0002637994 +7 right_top_grid_pin_43_[0]:7 0.0002637994 +8 right_top_grid_pin_43_[0]:8 0.0008576555 +9 right_top_grid_pin_43_[0]:9 0.000227115 +10 right_top_grid_pin_43_[0]:10 0.000227115 +11 right_top_grid_pin_43_[0]:11 5.253194e-05 +12 right_top_grid_pin_43_[0]:12 5.634222e-05 +13 right_top_grid_pin_43_[0]:13 0.0006187676 +14 right_top_grid_pin_43_[0]:14 0.0006187676 +15 right_top_grid_pin_43_[0]:15 0.00175019 +16 right_top_grid_pin_43_[0]:16 0.00175019 +17 right_top_grid_pin_43_[0]:17 0.0003149085 +18 right_top_grid_pin_43_[0]:18 0.0003149085 +19 right_top_grid_pin_43_[0]:19 7.694619e-05 +20 right_top_grid_pin_43_[0]:20 6.96303e-05 +21 right_top_grid_pin_43_[0]:21 7.36372e-05 +22 right_top_grid_pin_43_[0]:22 0.0008532663 +23 right_top_grid_pin_43_[0]:23 0.0007404521 +24 right_top_grid_pin_43_[0]:24 0.001086234 +25 right_top_grid_pin_43_[0]:25 0.0002285785 +26 right_top_grid_pin_43_[0]:26 0.0005981463 +27 right_top_grid_pin_43_[0]:27 0.0005981463 +28 right_top_grid_pin_43_[0]:28 6.322727e-05 +29 right_top_grid_pin_43_[0]:19 right_top_grid_pin_47_[0]:20 1.435477e-05 +30 right_top_grid_pin_43_[0]:16 right_top_grid_pin_47_[0]:16 0.0001963548 +31 right_top_grid_pin_43_[0]:15 right_top_grid_pin_47_[0]:15 0.0001963548 +32 right_top_grid_pin_43_[0]:23 right_top_grid_pin_47_[0]:21 0.0002342986 +33 right_top_grid_pin_43_[0]:24 right_top_grid_pin_47_[0]:22 0.0001273197 +34 right_top_grid_pin_43_[0]:24 right_top_grid_pin_47_[0]:8 1.420729e-05 +35 right_top_grid_pin_43_[0]:22 right_top_grid_pin_47_[0]:21 1.435477e-05 +36 right_top_grid_pin_43_[0]:22 right_top_grid_pin_47_[0]:20 0.0002342986 +37 right_top_grid_pin_43_[0]:8 right_top_grid_pin_47_[0]:8 6.767613e-05 +38 right_top_grid_pin_43_[0]:25 right_top_grid_pin_47_[0] 5.964353e-05 +39 right_top_grid_pin_43_[0]:25 right_top_grid_pin_47_[0]:22 1.420729e-05 +40 right_top_grid_pin_43_[0]:23 mux_tree_tapbuf_size9_1_sram[3]:9 6.717954e-05 +41 right_top_grid_pin_43_[0]:23 mux_tree_tapbuf_size9_1_sram[3]:10 6.081615e-05 +42 right_top_grid_pin_43_[0]:22 mux_tree_tapbuf_size9_1_sram[3]:5 6.717954e-05 +43 right_top_grid_pin_43_[0]:22 mux_tree_tapbuf_size9_1_sram[3]:9 6.081615e-05 + +*RES +0 right_top_grid_pin_43_[0] right_top_grid_pin_43_[0]:28 0.0001664583 +1 right_top_grid_pin_43_[0]:19 right_top_grid_pin_43_[0]:18 0.00341 +2 right_top_grid_pin_43_[0]:18 right_top_grid_pin_43_[0]:17 0.0004280916 +3 right_top_grid_pin_43_[0]:17 right_top_grid_pin_43_[0]:16 0.00341 +4 right_top_grid_pin_43_[0]:16 right_top_grid_pin_43_[0]:15 0.00479165 +5 right_top_grid_pin_43_[0]:14 right_top_grid_pin_43_[0]:13 0.001437025 +6 right_top_grid_pin_43_[0]:15 right_top_grid_pin_43_[0]:14 0.00341 +7 right_top_grid_pin_43_[0]:12 right_top_grid_pin_43_[0]:11 0.0001634616 +8 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:12 0.00341 +9 right_top_grid_pin_43_[0]:10 right_top_grid_pin_43_[0]:9 0.002207589 +10 right_top_grid_pin_43_[0]:11 right_top_grid_pin_43_[0]:10 0.0045 +11 right_top_grid_pin_43_[0]:9 mux_right_track_16\/mux_l1_in_1_:A0 0.152 +12 right_top_grid_pin_43_[0]:23 right_top_grid_pin_43_[0]:22 0.01694866 +13 right_top_grid_pin_43_[0]:24 right_top_grid_pin_43_[0]:23 0.00341 +14 right_top_grid_pin_43_[0]:24 right_top_grid_pin_43_[0]:8 0.002593225 +15 right_top_grid_pin_43_[0]:21 right_top_grid_pin_43_[0]:20 0.0001847826 +16 right_top_grid_pin_43_[0]:22 right_top_grid_pin_43_[0]:21 0.0045 +17 right_top_grid_pin_43_[0]:22 right_top_grid_pin_43_[0]:19 0.001162947 +18 right_top_grid_pin_43_[0]:20 mux_right_track_4\/mux_l1_in_2_:A1 0.152 +19 right_top_grid_pin_43_[0]:7 right_top_grid_pin_43_[0]:6 0.004158482 +20 right_top_grid_pin_43_[0]:8 right_top_grid_pin_43_[0]:7 0.00341 +21 right_top_grid_pin_43_[0]:5 right_top_grid_pin_43_[0]:4 0.0001548913 +22 right_top_grid_pin_43_[0]:6 right_top_grid_pin_43_[0]:5 0.0045 +23 right_top_grid_pin_43_[0]:4 mux_right_track_2\/mux_l1_in_1_:A0 0.152 +24 right_top_grid_pin_43_[0]:26 right_top_grid_pin_43_[0]:25 0.00341 +25 right_top_grid_pin_43_[0]:25 right_top_grid_pin_43_[0]:24 0.0007915583 +26 right_top_grid_pin_43_[0]:27 right_top_grid_pin_43_[0]:26 0.009611608 +27 right_top_grid_pin_43_[0]:28 right_top_grid_pin_43_[0]:27 0.00341 + +*END + +*D_NET chanx_left_in[1] 0.01776343 //LENGTH 110.735 LUMPCC 0.006641678 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.305 54.400 +*I mux_top_track_38\/mux_l1_in_1_:A1 I *L 0.00198 *C 78.760 85.340 +*N chanx_left_in[1]:2 *C 78.723 85.340 +*N chanx_left_in[1]:3 *C 77.785 85.340 +*N chanx_left_in[1]:4 *C 77.740 85.295 +*N chanx_left_in[1]:5 *C 77.740 76.898 +*N chanx_left_in[1]:6 *C 77.733 76.840 +*N chanx_left_in[1]:7 *C 37.260 76.840 +*N chanx_left_in[1]:8 *C 37.260 74.120 +*N chanx_left_in[1]:9 *C 24.388 74.120 +*N chanx_left_in[1]:10 *C 24.380 74.062 +*N chanx_left_in[1]:11 *C 24.380 55.138 +*N chanx_left_in[1]:12 *C 24.373 55.080 +*N chanx_left_in[1]:13 *C 1.380 55.080 + +*CAP +0 chanx_left_in[1] 5.197118e-05 +1 mux_top_track_38\/mux_l1_in_1_:A1 1e-06 +2 chanx_left_in[1]:2 8.363682e-05 +3 chanx_left_in[1]:3 8.363682e-05 +4 chanx_left_in[1]:4 0.0004673245 +5 chanx_left_in[1]:5 0.0004673245 +6 chanx_left_in[1]:6 0.002252537 +7 chanx_left_in[1]:7 0.002436126 +8 chanx_left_in[1]:8 0.0006085321 +9 chanx_left_in[1]:9 0.0004249433 +10 chanx_left_in[1]:10 0.001099066 +11 chanx_left_in[1]:11 0.001099066 +12 chanx_left_in[1]:12 0.0009973098 +13 chanx_left_in[1]:13 0.001049281 +14 chanx_left_in[1]:6 prog_clk[0]:197 0.0003269819 +15 chanx_left_in[1]:6 prog_clk[0]:313 0.0002530274 +16 chanx_left_in[1]:6 prog_clk[0]:320 8.170623e-07 +17 chanx_left_in[1]:6 prog_clk[0]:340 7.067414e-07 +18 chanx_left_in[1]:6 prog_clk[0]:574 0.0003551776 +19 chanx_left_in[1]:10 prog_clk[0]:550 9.282558e-07 +20 chanx_left_in[1]:9 prog_clk[0]:558 0.0001963311 +21 chanx_left_in[1]:11 prog_clk[0]:549 9.282558e-07 +22 chanx_left_in[1]:12 prog_clk[0]:535 0.0001951114 +23 chanx_left_in[1]:13 prog_clk[0]:534 0.0001951114 +24 chanx_left_in[1]:8 prog_clk[0]:557 0.0001963311 +25 chanx_left_in[1]:7 prog_clk[0]:313 0.0003269819 +26 chanx_left_in[1]:7 prog_clk[0]:314 0.0002530274 +27 chanx_left_in[1]:7 prog_clk[0]:340 8.170623e-07 +28 chanx_left_in[1]:7 prog_clk[0]:341 7.067414e-07 +29 chanx_left_in[1]:7 prog_clk[0]:575 0.0003551776 +30 chanx_left_in[1]:9 left_top_grid_pin_44_[0]:23 0.0007094895 +31 chanx_left_in[1]:8 left_top_grid_pin_44_[0]:22 0.0007094895 +32 chanx_left_in[1]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0003125387 +33 chanx_left_in[1]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0003125387 +34 chanx_left_in[1]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0008402602 +35 chanx_left_in[1]:13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0008402602 +36 chanx_left_in[1]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001294692 +37 chanx_left_in[1]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001294692 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:13 0.0001065333 +1 chanx_left_in[1]:2 mux_top_track_38\/mux_l1_in_1_:A1 0.152 +2 chanx_left_in[1]:3 chanx_left_in[1]:2 0.0008370536 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.0045 +4 chanx_left_in[1]:5 chanx_left_in[1]:4 0.007497768 +5 chanx_left_in[1]:6 chanx_left_in[1]:5 0.00341 +6 chanx_left_in[1]:10 chanx_left_in[1]:9 0.00341 +7 chanx_left_in[1]:9 chanx_left_in[1]:8 0.002016692 +8 chanx_left_in[1]:11 chanx_left_in[1]:10 0.01689732 +9 chanx_left_in[1]:12 chanx_left_in[1]:11 0.00341 +10 chanx_left_in[1]:13 chanx_left_in[1]:12 0.003602158 +11 chanx_left_in[1]:8 chanx_left_in[1]:7 0.0004261333 +12 chanx_left_in[1]:7 chanx_left_in[1]:6 0.006340691 + +*END + +*D_NET chanx_left_in[19] 0.007673324 //LENGTH 79.640 LUMPCC 0.001665194 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 4.080 +*I mux_top_track_28\/mux_l1_in_0_:A0 I *L 0.001631 *C 61.355 22.780 +*N chanx_left_in[19]:2 *C 61.318 22.780 +*N chanx_left_in[19]:3 *C 59.845 22.780 +*N chanx_left_in[19]:4 *C 59.800 22.735 +*N chanx_left_in[19]:5 *C 59.800 4.138 +*N chanx_left_in[19]:6 *C 59.793 4.080 +*N chanx_left_in[19]:7 *C 51.230 4.080 + +*CAP +0 chanx_left_in[19] 0.00181229 +1 mux_top_track_28\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[19]:2 0.0001044021 +3 chanx_left_in[19]:3 0.0001044021 +4 chanx_left_in[19]:4 0.0007167923 +5 chanx_left_in[19]:5 0.0007167923 +6 chanx_left_in[19]:6 0.0003700807 +7 chanx_left_in[19]:7 0.002182371 +8 chanx_left_in[19] chanx_left_in[14] 0.0006069721 +9 chanx_left_in[19]:4 chanx_left_in[14]:21 0.0001506353 +10 chanx_left_in[19]:5 chanx_left_in[14]:22 0.0001506353 +11 chanx_left_in[19]:6 chanx_left_in[14]:23 7.498956e-05 +12 chanx_left_in[19]:7 chanx_left_in[14]:24 0.0006819617 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:7 0.007833333 +1 chanx_left_in[19]:2 mux_top_track_28\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[19]:3 chanx_left_in[19]:2 0.001314732 +3 chanx_left_in[19]:4 chanx_left_in[19]:3 0.0045 +4 chanx_left_in[19]:5 chanx_left_in[19]:4 0.01660491 +5 chanx_left_in[19]:6 chanx_left_in[19]:5 0.00341 +6 chanx_left_in[19]:7 chanx_left_in[19]:6 0.001341458 + +*END + +*D_NET left_top_grid_pin_45_[0] 0.003724555 //LENGTH 26.005 LUMPCC 0.0009374071 DR + +*CONN +*P left_top_grid_pin_45_[0] I *L 0.29796 *C 5.060 74.870 +*I mux_left_track_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 5.160 72.420 +*I mux_left_track_5\/mux_l1_in_4_:A1 I *L 0.00198 *C 9.200 58.140 +*I mux_left_track_33\/mux_l1_in_2_:A1 I *L 0.00198 *C 12.980 61.540 +*N left_top_grid_pin_45_[0]:4 *C 12.943 61.540 +*N left_top_grid_pin_45_[0]:5 *C 9.200 58.140 +*N left_top_grid_pin_45_[0]:6 *C 9.200 58.140 +*N left_top_grid_pin_45_[0]:7 *C 8.740 58.140 +*N left_top_grid_pin_45_[0]:8 *C 8.740 61.495 +*N left_top_grid_pin_45_[0]:9 *C 8.740 61.540 +*N left_top_grid_pin_45_[0]:10 *C 5.105 61.540 +*N left_top_grid_pin_45_[0]:11 *C 5.060 61.585 +*N left_top_grid_pin_45_[0]:12 *C 5.060 72.420 +*N left_top_grid_pin_45_[0]:13 *C 5.060 72.420 + +*CAP +0 left_top_grid_pin_45_[0] 0.0001315475 +1 mux_left_track_3\/mux_l2_in_2_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_4_:A1 1e-06 +3 mux_left_track_33\/mux_l1_in_2_:A1 1e-06 +4 left_top_grid_pin_45_[0]:4 0.0003209203 +5 left_top_grid_pin_45_[0]:5 3.205549e-05 +6 left_top_grid_pin_45_[0]:6 6.922608e-05 +7 left_top_grid_pin_45_[0]:7 0.0002688135 +8 left_top_grid_pin_45_[0]:8 0.0002337655 +9 left_top_grid_pin_45_[0]:9 0.0005932356 +10 left_top_grid_pin_45_[0]:10 0.0002380799 +11 left_top_grid_pin_45_[0]:11 0.0003516681 +12 left_top_grid_pin_45_[0]:12 3.038429e-05 +13 left_top_grid_pin_45_[0]:13 0.000514451 +14 left_top_grid_pin_45_[0] left_top_grid_pin_47_[0] 4.051342e-06 +15 left_top_grid_pin_45_[0]:11 left_top_grid_pin_47_[0]:23 1.223671e-06 +16 left_top_grid_pin_45_[0]:11 left_top_grid_pin_47_[0]:19 0.0002623671 +17 left_top_grid_pin_45_[0]:13 left_top_grid_pin_47_[0] 1.223671e-06 +18 left_top_grid_pin_45_[0]:13 left_top_grid_pin_47_[0]:23 4.051342e-06 +19 left_top_grid_pin_45_[0]:13 left_top_grid_pin_47_[0]:20 0.0002623671 +20 left_top_grid_pin_45_[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001328861 +21 left_top_grid_pin_45_[0]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001328861 +22 left_top_grid_pin_45_[0]:10 ropt_net_153:8 4.478955e-05 +23 left_top_grid_pin_45_[0]:10 ropt_net_153:5 1.126481e-05 +24 left_top_grid_pin_45_[0]:11 ropt_net_153:7 2.10753e-06 +25 left_top_grid_pin_45_[0]:11 ropt_net_153:5 1.001346e-05 +26 left_top_grid_pin_45_[0]:9 ropt_net_153:9 4.478955e-05 +27 left_top_grid_pin_45_[0]:9 ropt_net_153:6 1.126481e-05 +28 left_top_grid_pin_45_[0]:13 ropt_net_153:4 1.001346e-05 +29 left_top_grid_pin_45_[0]:13 ropt_net_153:6 2.10753e-06 + +*RES +0 left_top_grid_pin_45_[0] left_top_grid_pin_45_[0]:13 0.0021875 +1 left_top_grid_pin_45_[0]:10 left_top_grid_pin_45_[0]:9 0.003245536 +2 left_top_grid_pin_45_[0]:11 left_top_grid_pin_45_[0]:10 0.0045 +3 left_top_grid_pin_45_[0]:9 left_top_grid_pin_45_[0]:8 0.0045 +4 left_top_grid_pin_45_[0]:9 left_top_grid_pin_45_[0]:4 0.003752232 +5 left_top_grid_pin_45_[0]:8 left_top_grid_pin_45_[0]:7 0.002995536 +6 left_top_grid_pin_45_[0]:5 mux_left_track_5\/mux_l1_in_4_:A1 0.152 +7 left_top_grid_pin_45_[0]:6 left_top_grid_pin_45_[0]:5 0.0045 +8 left_top_grid_pin_45_[0]:4 mux_left_track_33\/mux_l1_in_2_:A1 0.152 +9 left_top_grid_pin_45_[0]:12 mux_left_track_3\/mux_l2_in_2_:A1 0.152 +10 left_top_grid_pin_45_[0]:13 left_top_grid_pin_45_[0]:12 0.0045 +11 left_top_grid_pin_45_[0]:13 left_top_grid_pin_45_[0]:11 0.009674109 +12 left_top_grid_pin_45_[0]:7 left_top_grid_pin_45_[0]:6 0.0004107143 + +*END + +*D_NET chany_top_out[0] 0.001500418 //LENGTH 11.935 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 81.880 96.900 +*P chany_top_out[0] O *L 0.7423 *C 76.820 102.070 +*N chany_top_out[0]:2 *C 76.820 96.945 +*N chany_top_out[0]:3 *C 76.865 96.900 +*N chany_top_out[0]:4 *C 77.740 96.900 +*N chany_top_out[0]:5 *C 77.740 97.240 +*N chany_top_out[0]:6 *C 80.960 97.240 +*N chany_top_out[0]:7 *C 80.960 96.900 +*N chany_top_out[0]:8 *C 81.843 96.900 + +*CAP +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[0] 0.0003093922 +2 chany_top_out[0]:2 0.0003093922 +3 chany_top_out[0]:3 8.638702e-05 +4 chany_top_out[0]:4 0.0001138731 +5 chany_top_out[0]:5 0.0002667056 +6 chany_top_out[0]:6 0.0002654507 +7 chany_top_out[0]:7 8.722443e-05 +8 chany_top_out[0]:8 6.099318e-05 + +*RES +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[0]:8 0.152 +1 chany_top_out[0]:8 chany_top_out[0]:7 0.0007879465 +2 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +3 chany_top_out[0]:2 chany_top_out[0] 0.004575893 +4 chany_top_out[0]:4 chany_top_out[0]:3 0.00078125 +5 chany_top_out[0]:5 chany_top_out[0]:4 0.0003035715 +6 chany_top_out[0]:6 chany_top_out[0]:5 0.002875 +7 chany_top_out[0]:7 chany_top_out[0]:6 0.0003035715 + +*END + +*D_NET chany_top_out[2] 0.0004952875 //LENGTH 4.235 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 78.720 99.280 +*P chany_top_out[2] O *L 0.7423 *C 77.740 102.070 +*N chany_top_out[2]:2 *C 77.740 99.325 +*N chany_top_out[2]:3 *C 77.785 99.280 +*N chany_top_out[2]:4 *C 78.683 99.280 + +*CAP +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[2] 0.000167616 +2 chany_top_out[2]:2 0.000167616 +3 chany_top_out[2]:3 7.952779e-05 +4 chany_top_out[2]:4 7.952779e-05 + +*RES +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[2]:4 0.152 +1 chany_top_out[2]:4 chany_top_out[2]:3 0.0008013393 +2 chany_top_out[2]:3 chany_top_out[2]:2 0.0045 +3 chany_top_out[2]:2 chany_top_out[2] 0.002450893 + +*END + +*D_NET chany_top_out[4] 0.0007277159 //LENGTH 6.420 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 102.065 99.280 +*P chany_top_out[4] O *L 0.7423 *C 98.900 102.070 +*N chany_top_out[4]:2 *C 98.900 99.325 +*N chany_top_out[4]:3 *C 98.945 99.280 +*N chany_top_out[4]:4 *C 102.028 99.280 + +*CAP +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[4] 0.000144605 +2 chany_top_out[4]:2 0.000144605 +3 chany_top_out[4]:3 0.000218753 +4 chany_top_out[4]:4 0.000218753 + +*RES +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[4]:4 0.152 +1 chany_top_out[4]:4 chany_top_out[4]:3 0.002752232 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0045 +3 chany_top_out[4]:2 chany_top_out[4] 0.002450893 + +*END + +*D_NET chany_top_out[8] 0.0007736596 //LENGTH 5.785 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 70.380 98.940 +*P chany_top_out[8] O *L 0.7423 *C 68.540 102.035 +*N chany_top_out[8]:2 *C 69.000 102.000 +*N chany_top_out[8]:3 *C 69.000 99.665 +*N chany_top_out[8]:4 *C 69.045 99.620 +*N chany_top_out[8]:5 *C 69.460 99.620 +*N chany_top_out[8]:6 *C 69.460 98.940 +*N chany_top_out[8]:7 *C 70.343 98.940 + +*CAP +0 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[8] 3.265769e-05 +2 chany_top_out[8]:2 0.0002007208 +3 chany_top_out[8]:3 0.0001680631 +4 chany_top_out[8]:4 4.591314e-05 +5 chany_top_out[8]:5 9.25193e-05 +6 chany_top_out[8]:6 0.0001396958 +7 chany_top_out[8]:7 9.308965e-05 + +*RES +0 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[8]:7 0.152 +1 chany_top_out[8]:7 chany_top_out[8]:6 0.0007879465 +2 chany_top_out[8]:4 chany_top_out[8]:3 0.0045 +3 chany_top_out[8]:3 chany_top_out[8]:2 0.002084821 +4 chany_top_out[8]:5 chany_top_out[8]:4 0.0003705358 +5 chany_top_out[8]:6 chany_top_out[8]:5 0.000607143 +6 chany_top_out[8]:2 chany_top_out[8] 0.0004107143 + +*END + +*D_NET chany_top_out[12] 0.00167435 //LENGTH 13.945 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 82.340 91.460 +*P chany_top_out[12] O *L 0.7423 *C 79.580 102.070 +*N chany_top_out[12]:2 *C 79.580 91.845 +*N chany_top_out[12]:3 *C 79.625 91.800 +*N chany_top_out[12]:4 *C 82.340 91.800 +*N chany_top_out[12]:5 *C 82.340 91.460 + +*CAP +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[12] 0.0005904366 +2 chany_top_out[12]:2 0.0005904366 +3 chany_top_out[12]:3 0.0002029029 +4 chany_top_out[12]:4 0.0002314473 +5 chany_top_out[12]:5 5.812652e-05 + +*RES +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[12]:5 0.152 +1 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +2 chany_top_out[12]:2 chany_top_out[12] 0.009129465 +3 chany_top_out[12]:5 chany_top_out[12]:4 0.0003035715 +4 chany_top_out[12]:4 chany_top_out[12]:3 0.002424107 + +*END + +*D_NET chany_top_out[17] 0.0006557984 //LENGTH 5.170 LUMPCC 0 DR + +*CONN +*I mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 60.260 99.280 +*P chany_top_out[17] O *L 0.7423 *C 62.100 102.035 +*N chany_top_out[17]:2 *C 62.100 99.665 +*N chany_top_out[17]:3 *C 62.055 99.620 +*N chany_top_out[17]:4 *C 60.260 99.620 +*N chany_top_out[17]:5 *C 60.260 99.280 + +*CAP +0 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[17] 0.0001422003 +2 chany_top_out[17]:2 0.0001422003 +3 chany_top_out[17]:3 0.0001411119 +4 chany_top_out[17]:4 0.0001701245 +5 chany_top_out[17]:5 5.91614e-05 + +*RES +0 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[17]:5 0.152 +1 chany_top_out[17]:3 chany_top_out[17]:2 0.0045 +2 chany_top_out[17]:2 chany_top_out[17] 0.002116072 +3 chany_top_out[17]:5 chany_top_out[17]:4 0.0003035715 +4 chany_top_out[17]:4 chany_top_out[17]:3 0.001602679 + +*END + +*D_NET chanx_right_out[1] 0.001479061 //LENGTH 13.075 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 133.400 71.740 +*P chanx_right_out[1] O *L 0.7423 *C 140.382 66.640 +*N chanx_right_out[1]:2 *C 140.300 66.640 +*N chanx_right_out[1]:3 *C 140.300 66.640 +*N chanx_right_out[1]:4 *C 139.380 66.640 +*N chanx_right_out[1]:5 *C 139.380 71.695 +*N chanx_right_out[1]:6 *C 139.335 71.740 +*N chanx_right_out[1]:7 *C 133.438 71.740 + +*CAP +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[1] 2.793917e-05 +2 chanx_right_out[1]:2 2.793917e-05 +3 chanx_right_out[1]:3 7.513902e-05 +4 chanx_right_out[1]:4 0.00030613 +5 chanx_right_out[1]:5 0.0002591519 +6 chanx_right_out[1]:6 0.0003908807 +7 chanx_right_out[1]:7 0.0003908807 + +*RES +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[1]:7 0.152 +1 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +2 chanx_right_out[1]:2 chanx_right_out[1] 2.35e-05 +3 chanx_right_out[1]:6 chanx_right_out[1]:5 0.0045 +4 chanx_right_out[1]:5 chanx_right_out[1]:4 0.004513393 +5 chanx_right_out[1]:7 chanx_right_out[1]:6 0.005265625 +6 chanx_right_out[1]:4 chanx_right_out[1]:3 0.0008214285 + +*END + +*D_NET chanx_left_out[1] 0.001037217 //LENGTH 7.645 LUMPCC 0.0001149874 DR + +*CONN +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.680 69.360 +*P chanx_left_out[1] O *L 0.7423 *C 1.305 64.600 +*N chanx_left_out[1]:2 *C 3.673 64.600 +*N chanx_left_out[1]:3 *C 3.680 64.657 +*N chanx_left_out[1]:4 *C 3.680 69.315 +*N chanx_left_out[1]:5 *C 3.680 69.360 + +*CAP +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[1] 0.0001932106 +2 chanx_left_out[1]:2 0.0001932106 +3 chanx_left_out[1]:3 0.0002508347 +4 chanx_left_out[1]:4 0.0002508347 +5 chanx_left_out[1]:5 3.313933e-05 +6 chanx_left_out[1]:3 ropt_net_150:7 5.749372e-05 +7 chanx_left_out[1]:4 ropt_net_150:6 5.749372e-05 + +*RES +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[1]:5 0.152 +1 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +2 chanx_left_out[1]:2 chanx_left_out[1] 0.0003709083 +3 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +4 chanx_left_out[1]:4 chanx_left_out[1]:3 0.004158482 + +*END + +*D_NET ropt_net_131 0.0006966541 //LENGTH 5.325 LUMPCC 0.0001443282 DR + +*CONN +*I mem_left_track_33\/BUFT_RR_98:X O *L 0 *C 7.635 56.100 +*I ropt_mt_inst_754:A I *L 0.001767 *C 3.220 55.760 +*N ropt_net_131:2 *C 3.258 55.760 +*N ropt_net_131:3 *C 5.520 55.760 +*N ropt_net_131:4 *C 5.520 56.100 +*N ropt_net_131:5 *C 7.598 56.100 + +*CAP +0 mem_left_track_33\/BUFT_RR_98:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_131:2 0.0001463196 +3 ropt_net_131:3 0.0001717783 +4 ropt_net_131:4 0.0001288434 +5 ropt_net_131:5 0.0001033846 +6 ropt_net_131:5 mem_left_track_33/net_net_98:2 7.21641e-05 +7 ropt_net_131:4 mem_left_track_33/net_net_98:3 7.21641e-05 + +*RES +0 mem_left_track_33\/BUFT_RR_98:X ropt_net_131:5 0.152 +1 ropt_net_131:2 ropt_mt_inst_754:A 0.152 +2 ropt_net_131:5 ropt_net_131:4 0.001854911 +3 ropt_net_131:3 ropt_net_131:2 0.002020089 +4 ropt_net_131:4 ropt_net_131:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[3] 0.0009886366 //LENGTH 7.630 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 106.105 50.320 +*I mux_right_track_4\/mux_l4_in_0_:S I *L 0.00357 *C 108.920 52.360 +*I mem_right_track_4\/FTB_29__55:A I *L 0.001746 *C 105.340 53.040 +*N mux_tree_tapbuf_size14_0_sram[3]:3 *C 105.378 53.040 +*N mux_tree_tapbuf_size14_0_sram[3]:4 *C 105.800 53.040 +*N mux_tree_tapbuf_size14_0_sram[3]:5 *C 108.883 52.360 +*N mux_tree_tapbuf_size14_0_sram[3]:6 *C 105.800 52.360 +*N mux_tree_tapbuf_size14_0_sram[3]:7 *C 105.800 52.315 +*N mux_tree_tapbuf_size14_0_sram[3]:8 *C 105.800 50.365 +*N mux_tree_tapbuf_size14_0_sram[3]:9 *C 105.800 50.320 +*N mux_tree_tapbuf_size14_0_sram[3]:10 *C 106.105 50.320 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:S 1e-06 +2 mem_right_track_4\/FTB_29__55:A 1e-06 +3 mux_tree_tapbuf_size14_0_sram[3]:3 3.826981e-05 +4 mux_tree_tapbuf_size14_0_sram[3]:4 8.434615e-05 +5 mux_tree_tapbuf_size14_0_sram[3]:5 0.0002164944 +6 mux_tree_tapbuf_size14_0_sram[3]:6 0.0002625707 +7 mux_tree_tapbuf_size14_0_sram[3]:7 0.0001361718 +8 mux_tree_tapbuf_size14_0_sram[3]:8 0.0001361718 +9 mux_tree_tapbuf_size14_0_sram[3]:9 5.554196e-05 +10 mux_tree_tapbuf_size14_0_sram[3]:10 5.606998e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size14_0_sram[3]:10 0.152 +1 mux_tree_tapbuf_size14_0_sram[3]:6 mux_tree_tapbuf_size14_0_sram[3]:5 0.002752232 +2 mux_tree_tapbuf_size14_0_sram[3]:6 mux_tree_tapbuf_size14_0_sram[3]:4 0.000607143 +3 mux_tree_tapbuf_size14_0_sram[3]:7 mux_tree_tapbuf_size14_0_sram[3]:6 0.0045 +4 mux_tree_tapbuf_size14_0_sram[3]:9 mux_tree_tapbuf_size14_0_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size14_0_sram[3]:8 mux_tree_tapbuf_size14_0_sram[3]:7 0.001741072 +6 mux_tree_tapbuf_size14_0_sram[3]:10 mux_tree_tapbuf_size14_0_sram[3]:9 0.0001657609 +7 mux_tree_tapbuf_size14_0_sram[3]:5 mux_right_track_4\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size14_0_sram[3]:3 mem_right_track_4\/FTB_29__55:A 0.152 +9 mux_tree_tapbuf_size14_0_sram[3]:4 mux_tree_tapbuf_size14_0_sram[3]:3 0.0003772322 + +*END + +*D_NET mux_tree_tapbuf_size14_mem_1_ccff_tail[0] 0.0002469257 //LENGTH 1.945 LUMPCC 0 DR + +*CONN +*I mem_left_track_5\/FTB_30__56:X O *L 0 *C 24.200 42.500 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 25.855 42.500 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 *C 25.818 42.500 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 *C 24.238 42.500 + +*CAP +0 mem_left_track_5\/FTB_30__56:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 0.0001224628 +3 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 0.0001224628 + +*RES +0 mem_left_track_5\/FTB_30__56:X mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 0.001410714 +2 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.008870875 //LENGTH 60.130 LUMPCC 0.002332408 DR + +*CONN +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 54.585 37.060 +*I mux_top_track_30\/mux_l1_in_0_:S I *L 0.00357 *C 52.540 80.240 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 43.875 82.620 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 53.570 38.760 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 43.913 82.620 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 51.935 82.620 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 51.980 82.575 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 52.503 80.240 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 52.025 80.240 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 51.980 80.240 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 51.980 78.938 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 51.980 78.873 +*N mux_tree_tapbuf_size2_1_sram[0]:12 *C 51.980 78.200 +*N mux_tree_tapbuf_size2_1_sram[0]:13 *C 54.260 78.200 +*N mux_tree_tapbuf_size2_1_sram[0]:14 *C 54.280 78.193 +*N mux_tree_tapbuf_size2_1_sram[0]:15 *C 54.280 38.768 +*N mux_tree_tapbuf_size2_1_sram[0]:16 *C 54.278 38.760 +*N mux_tree_tapbuf_size2_1_sram[0]:17 *C 54.280 38.703 +*N mux_tree_tapbuf_size2_1_sram[0]:18 *C 54.280 37.105 +*N mux_tree_tapbuf_size2_1_sram[0]:19 *C 54.280 37.060 +*N mux_tree_tapbuf_size2_1_sram[0]:20 *C 54.585 37.060 + +*CAP +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_30\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 0.0001007486 +4 mux_tree_tapbuf_size2_1_sram[0]:4 0.0005333895 +5 mux_tree_tapbuf_size2_1_sram[0]:5 0.0005333895 +6 mux_tree_tapbuf_size2_1_sram[0]:6 0.0001303826 +7 mux_tree_tapbuf_size2_1_sram[0]:7 6.90346e-05 +8 mux_tree_tapbuf_size2_1_sram[0]:8 6.90346e-05 +9 mux_tree_tapbuf_size2_1_sram[0]:9 0.000247464 +10 mux_tree_tapbuf_size2_1_sram[0]:10 8.312192e-05 +11 mux_tree_tapbuf_size2_1_sram[0]:11 4.957253e-05 +12 mux_tree_tapbuf_size2_1_sram[0]:12 0.0002550025 +13 mux_tree_tapbuf_size2_1_sram[0]:13 0.00020543 +14 mux_tree_tapbuf_size2_1_sram[0]:14 0.001923266 +15 mux_tree_tapbuf_size2_1_sram[0]:15 0.001923266 +16 mux_tree_tapbuf_size2_1_sram[0]:16 0.0001007486 +17 mux_tree_tapbuf_size2_1_sram[0]:17 0.0001038427 +18 mux_tree_tapbuf_size2_1_sram[0]:18 0.0001038427 +19 mux_tree_tapbuf_size2_1_sram[0]:19 5.304891e-05 +20 mux_tree_tapbuf_size2_1_sram[0]:20 5.088209e-05 +21 mux_tree_tapbuf_size2_1_sram[0]:11 chany_top_in[4]:13 1.121578e-05 +22 mux_tree_tapbuf_size2_1_sram[0]:14 chany_top_in[4]:13 0.0002831472 +23 mux_tree_tapbuf_size2_1_sram[0]:15 chany_top_in[4]:12 0.0002831472 +24 mux_tree_tapbuf_size2_1_sram[0]:12 chany_top_in[4]:12 1.121578e-05 +25 mux_tree_tapbuf_size2_1_sram[0]:14 chany_top_in[19]:18 0.0008718407 +26 mux_tree_tapbuf_size2_1_sram[0]:15 chany_top_in[19]:17 0.0008718407 + +*RES +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:20 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.001162947 +2 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.00341 +3 mux_tree_tapbuf_size2_1_sram[0]:13 mux_tree_tapbuf_size2_1_sram[0]:12 0.0003572 +4 mux_tree_tapbuf_size2_1_sram[0]:14 mux_tree_tapbuf_size2_1_sram[0]:13 0.00341 +5 mux_tree_tapbuf_size2_1_sram[0]:16 mux_tree_tapbuf_size2_1_sram[0]:15 0.00341 +6 mux_tree_tapbuf_size2_1_sram[0]:16 mux_tree_tapbuf_size2_1_sram[0]:3 0.0001039141 +7 mux_tree_tapbuf_size2_1_sram[0]:15 mux_tree_tapbuf_size2_1_sram[0]:14 0.006176583 +8 mux_tree_tapbuf_size2_1_sram[0]:17 mux_tree_tapbuf_size2_1_sram[0]:16 0.00341 +9 mux_tree_tapbuf_size2_1_sram[0]:19 mux_tree_tapbuf_size2_1_sram[0]:18 0.0045 +10 mux_tree_tapbuf_size2_1_sram[0]:18 mux_tree_tapbuf_size2_1_sram[0]:17 0.001426339 +11 mux_tree_tapbuf_size2_1_sram[0]:20 mux_tree_tapbuf_size2_1_sram[0]:19 0.0001657609 +12 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 0.007162946 +13 mux_tree_tapbuf_size2_1_sram[0]:6 mux_tree_tapbuf_size2_1_sram[0]:5 0.0045 +14 mux_tree_tapbuf_size2_1_sram[0]:4 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.0004263393 +16 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.0045 +17 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:6 0.002084821 +18 mux_tree_tapbuf_size2_1_sram[0]:7 mux_top_track_30\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:11 0.0001053583 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.001004453 //LENGTH 8.580 LUMPCC 0 DR + +*CONN +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 47.685 98.940 +*I mux_top_track_34\/mux_l2_in_0_:S I *L 0.00357 *C 46.360 95.880 +*I mem_top_track_34\/FTB_25__51:A I *L 0.001746 *C 47.840 93.840 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 47.803 93.840 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 46.965 93.840 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 46.920 93.885 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 46.398 95.880 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 46.875 95.880 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 46.920 95.880 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 46.920 98.895 +*N mux_tree_tapbuf_size2_3_sram[1]:10 *C 46.965 98.940 +*N mux_tree_tapbuf_size2_3_sram[1]:11 *C 47.648 98.940 + +*CAP +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_34\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_34\/FTB_25__51:A 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 7.729967e-05 +4 mux_tree_tapbuf_size2_3_sram[1]:4 7.729967e-05 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0001192828 +6 mux_tree_tapbuf_size2_3_sram[1]:6 5.890067e-05 +7 mux_tree_tapbuf_size2_3_sram[1]:7 5.890067e-05 +8 mux_tree_tapbuf_size2_3_sram[1]:8 0.0003221004 +9 mux_tree_tapbuf_size2_3_sram[1]:9 0.0001706932 +10 mux_tree_tapbuf_size2_3_sram[1]:10 5.848804e-05 +11 mux_tree_tapbuf_size2_3_sram[1]:11 5.848804e-05 + +*RES +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.0004263393 +2 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:5 0.00178125 +4 mux_tree_tapbuf_size2_3_sram[1]:6 mux_top_track_34\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_3_sram[1]:3 0.0007477679 +6 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size2_3_sram[1]:3 mem_top_track_34\/FTB_25__51:A 0.152 +8 mux_tree_tapbuf_size2_3_sram[1]:10 mux_tree_tapbuf_size2_3_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 0.002691964 +10 mux_tree_tapbuf_size2_3_sram[1]:11 mux_tree_tapbuf_size2_3_sram[1]:10 0.0006093751 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.001557817 //LENGTH 11.010 LUMPCC 0.000379256 DR + +*CONN +*I mem_top_track_36\/FTB_26__52:X O *L 0 *C 79.355 93.500 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 71.475 91.460 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 71.475 91.460 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 71.300 91.460 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 *C 71.300 91.505 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 *C 71.300 93.455 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 *C 71.345 93.500 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 *C 79.318 93.500 + +*CAP +0 mem_top_track_36\/FTB_26__52:X 1e-06 +1 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 5.557653e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 5.710478e-05 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.000128819 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.000128819 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.0004031206 +7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.0004031206 +8 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size2_4_sram[1]:7 0.000189628 +9 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size2_4_sram[1]:3 0.000189628 + +*RES +0 mem_top_track_36\/FTB_26__52:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.007118304 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[0] 0.002129183 //LENGTH 16.035 LUMPCC 0.0003635529 DR + +*CONN +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 66.545 34.000 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 69.635 37.060 +*I mux_top_track_20\/mux_l1_in_1_:S I *L 0.00357 *C 70.280 40.120 +*I mux_top_track_20\/mux_l1_in_0_:S I *L 0.00357 *C 67.520 42.160 +*N mux_tree_tapbuf_size3_4_sram[0]:4 *C 67.520 42.160 +*N mux_tree_tapbuf_size3_4_sram[0]:5 *C 67.620 42.115 +*N mux_tree_tapbuf_size3_4_sram[0]:6 *C 70.243 40.120 +*N mux_tree_tapbuf_size3_4_sram[0]:7 *C 67.665 40.120 +*N mux_tree_tapbuf_size3_4_sram[0]:8 *C 67.620 40.165 +*N mux_tree_tapbuf_size3_4_sram[0]:9 *C 67.160 40.120 +*N mux_tree_tapbuf_size3_4_sram[0]:10 *C 69.597 37.060 +*N mux_tree_tapbuf_size3_4_sram[0]:11 *C 67.205 37.060 +*N mux_tree_tapbuf_size3_4_sram[0]:12 *C 67.160 37.060 +*N mux_tree_tapbuf_size3_4_sram[0]:13 *C 67.160 34.045 +*N mux_tree_tapbuf_size3_4_sram[0]:14 *C 67.115 34.000 +*N mux_tree_tapbuf_size3_4_sram[0]:15 *C 66.583 34.000 + +*CAP +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_20\/mux_l1_in_1_:S 1e-06 +3 mux_top_track_20\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_4_sram[0]:4 2.773243e-05 +5 mux_tree_tapbuf_size3_4_sram[0]:5 0.000133723 +6 mux_tree_tapbuf_size3_4_sram[0]:6 0.0001877977 +7 mux_tree_tapbuf_size3_4_sram[0]:7 0.0001877977 +8 mux_tree_tapbuf_size3_4_sram[0]:8 0.0001679285 +9 mux_tree_tapbuf_size3_4_sram[0]:9 0.0001537991 +10 mux_tree_tapbuf_size3_4_sram[0]:10 0.0001882829 +11 mux_tree_tapbuf_size3_4_sram[0]:11 0.0001882829 +12 mux_tree_tapbuf_size3_4_sram[0]:12 0.000272765 +13 mux_tree_tapbuf_size3_4_sram[0]:13 0.0001245041 +14 mux_tree_tapbuf_size3_4_sram[0]:14 6.450855e-05 +15 mux_tree_tapbuf_size3_4_sram[0]:15 6.450855e-05 +16 mux_tree_tapbuf_size3_4_sram[0]:13 chanx_left_in[16]:33 8.427427e-05 +17 mux_tree_tapbuf_size3_4_sram[0]:12 chanx_left_in[16]:32 8.427427e-05 +18 mux_tree_tapbuf_size3_4_sram[0]:12 chanx_left_in[16]:33 7.024932e-05 +19 mux_tree_tapbuf_size3_4_sram[0]:7 chanx_left_in[16]:30 8.869823e-06 +20 mux_tree_tapbuf_size3_4_sram[0]:7 chanx_left_in[16]:31 1.838305e-05 +21 mux_tree_tapbuf_size3_4_sram[0]:6 chanx_left_in[16]:29 8.869823e-06 +22 mux_tree_tapbuf_size3_4_sram[0]:6 chanx_left_in[16]:30 1.838305e-05 +23 mux_tree_tapbuf_size3_4_sram[0]:9 chanx_left_in[16]:32 7.024932e-05 + +*RES +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_4_sram[0]:15 0.152 +1 mux_tree_tapbuf_size3_4_sram[0]:14 mux_tree_tapbuf_size3_4_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size3_4_sram[0]:13 mux_tree_tapbuf_size3_4_sram[0]:12 0.002691964 +3 mux_tree_tapbuf_size3_4_sram[0]:15 mux_tree_tapbuf_size3_4_sram[0]:14 0.0004754465 +4 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:10 0.002136161 +5 mux_tree_tapbuf_size3_4_sram[0]:12 mux_tree_tapbuf_size3_4_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size3_4_sram[0]:12 mux_tree_tapbuf_size3_4_sram[0]:9 0.002732143 +7 mux_tree_tapbuf_size3_4_sram[0]:10 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size3_4_sram[0]:7 mux_tree_tapbuf_size3_4_sram[0]:6 0.00230134 +9 mux_tree_tapbuf_size3_4_sram[0]:8 mux_tree_tapbuf_size3_4_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size3_4_sram[0]:8 mux_tree_tapbuf_size3_4_sram[0]:5 0.001741072 +11 mux_tree_tapbuf_size3_4_sram[0]:6 mux_top_track_20\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size3_4_sram[0]:4 mux_top_track_20\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size3_4_sram[0]:5 mux_tree_tapbuf_size3_4_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size3_4_sram[0]:9 mux_tree_tapbuf_size3_4_sram[0]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_5_ccff_tail[0] 0.001620301 //LENGTH 13.560 LUMPCC 0.0001290607 DR + +*CONN +*I mem_top_track_22\/FTB_19__45:X O *L 0 *C 84.405 23.800 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 79.700 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 *C 79.700 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 *C 79.580 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 *C 79.580 31.575 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 *C 79.580 23.845 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 *C 79.625 23.800 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 *C 84.368 23.800 + +*CAP +0 mem_top_track_22\/FTB_19__45:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 6.045355e-05 +3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 5.096506e-05 +4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 0.0003674565 +5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 0.0003674565 +6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 0.0003214543 +7 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 0.0003214543 +8 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_6_sram[1]:5 2.953645e-05 +9 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_6_sram[1]:6 2.610669e-06 +10 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_6_sram[1]:13 2.792257e-05 +11 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_6_sram[1]:15 4.460675e-06 +12 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size3_6_sram[1]:12 2.792257e-05 +13 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size3_6_sram[1]:14 4.460675e-06 +14 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size3_6_sram[1]:15 3.214712e-05 + +*RES +0 mem_top_track_22\/FTB_19__45:X mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 1e-05 +3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 0.006901786 +6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 0.004234375 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.009801408 //LENGTH 69.430 LUMPCC 0.002537681 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 48.145 49.980 +*I mux_left_track_33\/mux_l1_in_2_:S I *L 0.00357 *C 13.700 61.200 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 33.765 58.820 +*I mux_left_track_33\/mux_l1_in_1_:S I *L 0.00357 *C 44.720 61.495 +*I mux_left_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 51.620 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 51.520 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 51.520 66.595 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 51.520 61.925 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 51.475 61.880 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 44.720 61.495 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 44.695 61.880 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 44.620 61.835 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 44.620 59.160 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 33.788 58.848 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 13.663 61.200 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 11.545 61.200 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 11.500 61.155 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 11.500 59.898 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 11.508 59.840 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 34.032 59.840 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 34.040 59.783 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 34.040 59.205 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 34.085 59.160 +*N mux_tree_tapbuf_size6_1_sram[0]:23 *C 44.115 59.160 +*N mux_tree_tapbuf_size6_1_sram[0]:24 *C 44.160 59.160 +*N mux_tree_tapbuf_size6_1_sram[0]:25 *C 44.160 50.025 +*N mux_tree_tapbuf_size6_1_sram[0]:26 *C 44.205 49.980 +*N mux_tree_tapbuf_size6_1_sram[0]:27 *C 48.108 49.980 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_33\/mux_l1_in_2_:S 1e-06 +2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_33\/mux_l1_in_1_:S 1e-06 +4 mux_left_track_33\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 3.497206e-05 +6 mux_tree_tapbuf_size6_1_sram[0]:6 0.0002646731 +7 mux_tree_tapbuf_size6_1_sram[0]:7 0.0002646731 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0004787149 +9 mux_tree_tapbuf_size6_1_sram[0]:9 6.153042e-05 +10 mux_tree_tapbuf_size6_1_sram[0]:10 0.0005135713 +11 mux_tree_tapbuf_size6_1_sram[0]:11 0.000191794 +12 mux_tree_tapbuf_size6_1_sram[0]:12 0.0002278287 +13 mux_tree_tapbuf_size6_1_sram[0]:13 2.95565e-05 +14 mux_tree_tapbuf_size6_1_sram[0]:14 0.0001952126 +15 mux_tree_tapbuf_size6_1_sram[0]:15 0.0001952126 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.0001111902 +17 mux_tree_tapbuf_size6_1_sram[0]:17 0.0001111902 +18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0007181832 +19 mux_tree_tapbuf_size6_1_sram[0]:19 0.0007181832 +20 mux_tree_tapbuf_size6_1_sram[0]:20 5.670676e-05 +21 mux_tree_tapbuf_size6_1_sram[0]:21 5.670676e-05 +22 mux_tree_tapbuf_size6_1_sram[0]:22 0.0007442354 +23 mux_tree_tapbuf_size6_1_sram[0]:23 0.0007146788 +24 mux_tree_tapbuf_size6_1_sram[0]:24 0.0005426732 +25 mux_tree_tapbuf_size6_1_sram[0]:25 0.0005066385 +26 mux_tree_tapbuf_size6_1_sram[0]:26 0.0002603009 +27 mux_tree_tapbuf_size6_1_sram[0]:27 0.0002603009 +28 mux_tree_tapbuf_size6_1_sram[0]:19 chanx_left_in[10]:31 0.0001186417 +29 mux_tree_tapbuf_size6_1_sram[0]:19 chanx_left_in[10]:33 0.0004067791 +30 mux_tree_tapbuf_size6_1_sram[0]:18 chanx_left_in[10]:32 0.0001186417 +31 mux_tree_tapbuf_size6_1_sram[0]:18 chanx_left_in[10]:34 0.0004067791 +32 mux_tree_tapbuf_size6_1_sram[0]:19 left_top_grid_pin_46_[0]:12 0.0001061685 +33 mux_tree_tapbuf_size6_1_sram[0]:19 left_top_grid_pin_46_[0]:17 0.0002297397 +34 mux_tree_tapbuf_size6_1_sram[0]:18 left_top_grid_pin_46_[0]:17 0.0001061685 +35 mux_tree_tapbuf_size6_1_sram[0]:18 left_top_grid_pin_46_[0]:18 0.0002297397 +36 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[1]:22 1.335036e-05 +37 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[1]:19 0.0003941611 +38 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[1]:18 0.0003941611 +39 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[1]:23 1.335036e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:27 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:10 mux_tree_tapbuf_size6_1_sram[0]:9 0.0002005209 +2 mux_tree_tapbuf_size6_1_sram[0]:10 mux_tree_tapbuf_size6_1_sram[0]:8 0.006053572 +3 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:21 0.0045 +5 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:13 0.0002111487 +6 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.000515625 +7 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.00341 +8 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.003528916 +9 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:16 0.001122768 +10 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[0]:17 0.00341 +11 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.001890625 +12 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.0045 +13 mux_tree_tapbuf_size6_1_sram[0]:14 mux_left_track_33\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size6_1_sram[0]:13 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:22 0.008955358 +16 mux_tree_tapbuf_size6_1_sram[0]:24 mux_tree_tapbuf_size6_1_sram[0]:23 0.0045 +17 mux_tree_tapbuf_size6_1_sram[0]:24 mux_tree_tapbuf_size6_1_sram[0]:12 0.0004107143 +18 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.0045 +19 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.004169643 +20 mux_tree_tapbuf_size6_1_sram[0]:5 mux_left_track_33\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size6_1_sram[0]:6 mux_tree_tapbuf_size6_1_sram[0]:5 0.0045 +22 mux_tree_tapbuf_size6_1_sram[0]:9 mux_left_track_33\/mux_l1_in_1_:S 0.152 +23 mux_tree_tapbuf_size6_1_sram[0]:26 mux_tree_tapbuf_size6_1_sram[0]:25 0.0045 +24 mux_tree_tapbuf_size6_1_sram[0]:25 mux_tree_tapbuf_size6_1_sram[0]:24 0.00815625 +25 mux_tree_tapbuf_size6_1_sram[0]:27 mux_tree_tapbuf_size6_1_sram[0]:26 0.003484375 +26 mux_tree_tapbuf_size6_1_sram[0]:12 mux_tree_tapbuf_size6_1_sram[0]:11 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[1] 0.001979667 //LENGTH 15.358 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 41.705 42.500 +*I mux_left_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 40.380 44.880 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 44.795 42.500 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 49.780 44.880 +*N mux_tree_tapbuf_size7_6_sram[1]:4 *C 49.680 44.880 +*N mux_tree_tapbuf_size7_6_sram[1]:5 *C 49.680 44.835 +*N mux_tree_tapbuf_size7_6_sram[1]:6 *C 49.680 42.885 +*N mux_tree_tapbuf_size7_6_sram[1]:7 *C 49.635 42.840 +*N mux_tree_tapbuf_size7_6_sram[1]:8 *C 44.620 42.840 +*N mux_tree_tapbuf_size7_6_sram[1]:9 *C 44.670 42.523 +*N mux_tree_tapbuf_size7_6_sram[1]:10 *C 44.620 42.500 +*N mux_tree_tapbuf_size7_6_sram[1]:11 *C 40.380 44.880 +*N mux_tree_tapbuf_size7_6_sram[1]:12 *C 40.480 44.835 +*N mux_tree_tapbuf_size7_6_sram[1]:13 *C 40.480 42.545 +*N mux_tree_tapbuf_size7_6_sram[1]:14 *C 40.525 42.500 +*N mux_tree_tapbuf_size7_6_sram[1]:15 *C 41.705 42.500 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_25\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_6_sram[1]:4 3.054656e-05 +5 mux_tree_tapbuf_size7_6_sram[1]:5 0.0001169614 +6 mux_tree_tapbuf_size7_6_sram[1]:6 0.0001169614 +7 mux_tree_tapbuf_size7_6_sram[1]:7 0.0003956486 +8 mux_tree_tapbuf_size7_6_sram[1]:8 0.0004149013 +9 mux_tree_tapbuf_size7_6_sram[1]:9 2.901226e-05 +10 mux_tree_tapbuf_size7_6_sram[1]:10 0.000186624 +11 mux_tree_tapbuf_size7_6_sram[1]:11 2.649283e-05 +12 mux_tree_tapbuf_size7_6_sram[1]:12 0.0001415049 +13 mux_tree_tapbuf_size7_6_sram[1]:13 0.0001415049 +14 mux_tree_tapbuf_size7_6_sram[1]:14 8.527192e-05 +15 mux_tree_tapbuf_size7_6_sram[1]:15 0.000290237 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_6_sram[1]:15 0.152 +1 mux_tree_tapbuf_size7_6_sram[1]:9 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_6_sram[1]:9 mux_tree_tapbuf_size7_6_sram[1]:8 0.0002834821 +3 mux_tree_tapbuf_size7_6_sram[1]:15 mux_tree_tapbuf_size7_6_sram[1]:14 0.001053571 +4 mux_tree_tapbuf_size7_6_sram[1]:15 mux_tree_tapbuf_size7_6_sram[1]:10 0.002602679 +5 mux_tree_tapbuf_size7_6_sram[1]:14 mux_tree_tapbuf_size7_6_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size7_6_sram[1]:13 mux_tree_tapbuf_size7_6_sram[1]:12 0.002044643 +7 mux_tree_tapbuf_size7_6_sram[1]:11 mux_left_track_25\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size7_6_sram[1]:12 mux_tree_tapbuf_size7_6_sram[1]:11 0.0045 +9 mux_tree_tapbuf_size7_6_sram[1]:7 mux_tree_tapbuf_size7_6_sram[1]:6 0.0045 +10 mux_tree_tapbuf_size7_6_sram[1]:6 mux_tree_tapbuf_size7_6_sram[1]:5 0.001741071 +11 mux_tree_tapbuf_size7_6_sram[1]:4 mux_left_track_25\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_6_sram[1]:5 mux_tree_tapbuf_size7_6_sram[1]:4 0.0045 +13 mux_tree_tapbuf_size7_6_sram[1]:10 mux_tree_tapbuf_size7_6_sram[1]:9 4.464286e-05 +14 mux_tree_tapbuf_size7_6_sram[1]:8 mux_tree_tapbuf_size7_6_sram[1]:7 0.004477679 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[0] 0.004860271 //LENGTH 34.275 LUMPCC 0.001373537 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 31.585 42.500 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 26.855 44.540 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 40.120 61.540 +*N mux_tree_tapbuf_size8_3_sram[0]:3 *C 40.083 61.540 +*N mux_tree_tapbuf_size8_3_sram[0]:4 *C 37.765 61.540 +*N mux_tree_tapbuf_size8_3_sram[0]:5 *C 37.720 61.495 +*N mux_tree_tapbuf_size8_3_sram[0]:6 *C 37.720 44.925 +*N mux_tree_tapbuf_size8_3_sram[0]:7 *C 37.675 44.880 +*N mux_tree_tapbuf_size8_3_sram[0]:8 *C 31.280 44.880 +*N mux_tree_tapbuf_size8_3_sram[0]:9 *C 26.893 44.540 +*N mux_tree_tapbuf_size8_3_sram[0]:10 *C 31.280 44.570 +*N mux_tree_tapbuf_size8_3_sram[0]:11 *C 31.280 44.495 +*N mux_tree_tapbuf_size8_3_sram[0]:12 *C 31.280 42.545 +*N mux_tree_tapbuf_size8_3_sram[0]:13 *C 31.280 42.500 +*N mux_tree_tapbuf_size8_3_sram[0]:14 *C 31.585 42.500 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_3_sram[0]:3 0.0002019055 +4 mux_tree_tapbuf_size8_3_sram[0]:4 0.0002019055 +5 mux_tree_tapbuf_size8_3_sram[0]:5 0.0006986207 +6 mux_tree_tapbuf_size8_3_sram[0]:6 0.0006986207 +7 mux_tree_tapbuf_size8_3_sram[0]:7 0.000302279 +8 mux_tree_tapbuf_size8_3_sram[0]:8 0.0003261814 +9 mux_tree_tapbuf_size8_3_sram[0]:9 0.0003057334 +10 mux_tree_tapbuf_size8_3_sram[0]:10 0.0003296357 +11 mux_tree_tapbuf_size8_3_sram[0]:11 0.0001556337 +12 mux_tree_tapbuf_size8_3_sram[0]:12 0.0001556337 +13 mux_tree_tapbuf_size8_3_sram[0]:13 5.59245e-05 +14 mux_tree_tapbuf_size8_3_sram[0]:14 5.166003e-05 +15 mux_tree_tapbuf_size8_3_sram[0]:6 mux_tree_tapbuf_size14_1_sram[0]:19 0.0001707931 +16 mux_tree_tapbuf_size8_3_sram[0]:5 mux_tree_tapbuf_size14_1_sram[0]:18 0.0001707931 +17 mux_tree_tapbuf_size8_3_sram[0]:7 mux_tree_tapbuf_size8_3_sram[1]:30 3.58035e-05 +18 mux_tree_tapbuf_size8_3_sram[0]:7 mux_tree_tapbuf_size8_3_sram[1]:28 2.395196e-06 +19 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[1]:28 0.0001228394 +20 mux_tree_tapbuf_size8_3_sram[0]:9 mux_tree_tapbuf_size8_3_sram[1]:27 0.0001175257 +21 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[1]:27 2.395196e-06 +22 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[1]:29 4.111714e-05 +23 mux_tree_tapbuf_size8_3_sram[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001149154 +24 mux_tree_tapbuf_size8_3_sram[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.464264e-07 +25 mux_tree_tapbuf_size8_3_sram[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.464264e-07 +26 mux_tree_tapbuf_size8_3_sram[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001149154 +27 mux_tree_tapbuf_size8_3_sram[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002398757 +28 mux_tree_tapbuf_size8_3_sram[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002398757 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_3_sram[0]:14 0.152 +1 mux_tree_tapbuf_size8_3_sram[0]:7 mux_tree_tapbuf_size8_3_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size8_3_sram[0]:6 mux_tree_tapbuf_size8_3_sram[0]:5 0.01479464 +3 mux_tree_tapbuf_size8_3_sram[0]:4 mux_tree_tapbuf_size8_3_sram[0]:3 0.002069197 +4 mux_tree_tapbuf_size8_3_sram[0]:5 mux_tree_tapbuf_size8_3_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size8_3_sram[0]:3 mux_left_track_9\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:9 0.003917411 +7 mux_tree_tapbuf_size8_3_sram[0]:10 mux_tree_tapbuf_size8_3_sram[0]:8 0.0002767857 +8 mux_tree_tapbuf_size8_3_sram[0]:11 mux_tree_tapbuf_size8_3_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size8_3_sram[0]:13 mux_tree_tapbuf_size8_3_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size8_3_sram[0]:12 mux_tree_tapbuf_size8_3_sram[0]:11 0.001741072 +11 mux_tree_tapbuf_size8_3_sram[0]:14 mux_tree_tapbuf_size8_3_sram[0]:13 0.0001222826 +12 mux_tree_tapbuf_size8_3_sram[0]:9 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size8_3_sram[0]:8 mux_tree_tapbuf_size8_3_sram[0]:7 0.005709822 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008813929 //LENGTH 6.760 LUMPCC 7.88107e-05 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_1_:X O *L 0 *C 55.375 66.640 +*I mux_top_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 52.605 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 52.643 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 53.315 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 53.360 69.655 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 53.360 66.685 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 53.405 66.640 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 55.338 66.640 + +*CAP +0 mux_top_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.945069e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.945069e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001913438 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001913438 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001694966 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001694966 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[4]:19 3.940535e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[4]:14 3.940535e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725446 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002651786 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0006004464 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.005053965 //LENGTH 38.105 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_0_:X O *L 0 *C 56.755 79.560 +*I mux_left_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.505 72.420 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 27.505 72.420 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 27.600 72.760 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 51.520 72.760 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 51.520 72.420 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 56.535 72.420 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 56.580 72.465 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 56.580 79.515 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 56.580 79.560 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 56.755 79.560 + +*CAP +0 mux_left_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.439859e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001677311 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001675354 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003463968 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003215534 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004333199 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0004333199 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.64577e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.385216e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.004477679 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.006294643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:9 9.51087e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.02135715 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003035714 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005564645 //LENGTH 3.400 LUMPCC 0.0002011181 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_1_:X O *L 0 *C 55.485 87.720 +*I mux_top_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.595 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.558 87.720 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 55.523 87.720 + +*CAP +0 mux_top_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001766733 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001766733 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 top_left_grid_pin_41_[0]:23 0.000100559 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 top_left_grid_pin_41_[0]:24 0.000100559 + +*RES +0 mux_top_track_2\/mux_l1_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002709821 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009943264 //LENGTH 8.000 LUMPCC 9.480741e-05 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_1_:X O *L 0 *C 80.325 45.560 +*I mux_top_track_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 82.975 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 82.938 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.465 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 81.420 49.935 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.420 45.605 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.375 45.560 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 80.362 45.560 + +*CAP +0 mux_top_track_6\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001130233 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001130233 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002364422 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002364422 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.929403e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.929403e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_41_[0]:17 4.631652e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_41_[0]:13 1.08719e-06 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_41_[0]:14 4.631652e-05 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_41_[0]:12 1.08719e-06 + +*RES +0 mux_top_track_6\/mux_l1_in_1_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_6\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001314732 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006427609 //LENGTH 4.775 LUMPCC 0.0001612534 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_1_:X O *L 0 *C 53.535 28.220 +*I mux_left_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 49.050 28.220 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 49.088 28.220 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 53.498 28.220 + +*CAP +0 mux_left_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002397538 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002397538 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_5_sram[1]:13 8.062671e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_5_sram[1]:14 8.062671e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0039375 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0] 0.006202166 //LENGTH 50.030 LUMPCC 0.002421914 DR + +*CONN +*I mux_left_track_25\/mux_l3_in_0_:X O *L 0 *C 42.955 44.540 +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 12.650 28.385 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 12.688 28.280 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 18.815 28.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 18.860 28.175 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 18.860 27.258 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 18.867 27.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 42.773 27.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 42.780 27.258 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 42.780 44.495 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 42.780 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 42.955 44.540 + +*CAP +0 mux_left_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003172035 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003172035 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.51519e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.51519e-05 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004988655 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004988655 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.000932486 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.000932486 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:10 6.481385e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:11 6.602463e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[9]:16 0.0006073919 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[9]:15 0.0006073919 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_right_in[9]:16 5.455905e-06 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_right_in[9]:15 5.455905e-06 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_left_in[16]:35 0.0005889847 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_left_in[16] 0.0005889847 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[16]:35 9.124378e-06 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[16] 9.124378e-06 + +*RES +0 mux_left_track_25\/mux_l3_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:10 9.51087e-05 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.01539063 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.003745116 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0008191965 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.005470983 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005906364 //LENGTH 4.705 LUMPCC 0 DR + +*CONN +*I mux_top_track_20\/mux_l1_in_0_:X O *L 0 *C 68.365 41.820 +*I mux_top_track_20\/mux_l2_in_0_:A1 I *L 0.00198 *C 72.780 41.820 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 72.743 41.820 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.403 41.820 + +*CAP +0 mux_top_track_20\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_20\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002943182 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002943182 + +*RES +0 mux_top_track_20\/mux_l1_in_0_:X mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_20\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003875 + +*END + +*D_NET mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001933839 //LENGTH 13.820 LUMPCC 0.0006932337 DR + +*CONN +*I mux_top_track_38\/mux_l2_in_0_:X O *L 0 *C 82.055 86.360 +*I mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 81.995 99.120 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 81.995 99.120 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 81.880 99.280 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 81.880 99.235 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 81.880 86.405 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 81.880 86.360 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 82.055 86.360 + +*CAP +0 mux_top_track_38\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.228034e-05 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.305648e-05 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005046139 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0005046139 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.276478e-05 +7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.12757e-05 +8 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[2] 0.0003466169 +9 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[2]:11 0.0003466169 + +*RES +0 mux_top_track_38\/mux_l2_in_0_:X mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.695653e-05 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01145536 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002157098 //LENGTH 16.535 LUMPCC 0.0005029179 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 108.385 75.140 +*I mux_right_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 117.760 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 117.723 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 115.965 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 115.920 69.065 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 115.920 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 112.700 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 112.655 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 108.422 75.140 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001511589 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001511589 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000361015 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0005263114 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001984518 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001320421 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001320421 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 right_top_grid_pin_44_[0]:14 0.0001684038 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 right_top_grid_pin_44_[0]:15 0.0001684038 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 right_top_grid_pin_44_[0]:14 1.009168e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 right_top_grid_pin_44_[0]:15 1.009168e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size9_0_sram[1]:27 6.516551e-05 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size9_0_sram[1]:25 6.516551e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size9_0_sram[1]:21 5.134709e-06 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:18 2.408474e-06 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:23 2.546992e-07 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:19 2.408474e-06 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:20 5.134709e-06 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:24 2.546992e-07 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.003779018 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002875 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001569196 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A1 0.152 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.005424107 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008428296 //LENGTH 6.305 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_5_:X O *L 0 *C 111.955 69.020 +*I mux_right_track_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 111.150 64.260 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 111.188 64.260 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 111.735 64.260 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 111.780 64.305 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 111.780 68.975 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 111.780 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 111.955 69.020 + +*CAP +0 mux_right_track_4\/mux_l1_in_5_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_2_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.235244e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.235244e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002770559 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002770559 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.03031e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.170997e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_5_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_4\/mux_l2_in_2_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004888393 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005806767 //LENGTH 4.210 LUMPCC 7.906421e-05 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_6_:X O *L 0 *C 11.325 48.280 +*I mux_left_track_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 10.120 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 10.120 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 10.120 50.615 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 10.120 48.325 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 10.165 48.280 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 11.288 48.280 + +*CAP +0 mux_left_track_5\/mux_l1_in_6_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_3_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.283727e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001354998 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001354998 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.788782e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.788782e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 left_bottom_grid_pin_1_[0]:11 3.95321e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 left_bottom_grid_pin_1_[0]:12 3.95321e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_6_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001002232 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.002044643 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_5\/mux_l2_in_3_:A1 0.152 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001039876 //LENGTH 7.520 LUMPCC 0.0002187316 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 39.735 71.400 +*I mux_left_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 37.165 66.980 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 37.165 66.980 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 37.260 67.025 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 37.260 71.355 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 37.305 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 39.698 71.400 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.024437e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002420895 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002420895 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001523606 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001523606 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 left_top_grid_pin_44_[0]:6 4.694418e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 left_top_grid_pin_44_[0]:7 4.694418e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_2_sram[1]:20 6.242162e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size8_2_sram[1]:21 6.242162e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.003866072 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002136161 + +*END + +*D_NET ropt_net_143 0.001999543 //LENGTH 13.420 LUMPCC 0.000771301 DR + +*CONN +*I FTB_12__11:X O *L 0 *C 15.180 39.780 +*I ropt_mt_inst_766:A I *L 0.001766 *C 7.820 44.880 +*N ropt_net_143:2 *C 7.820 44.880 +*N ropt_net_143:3 *C 7.820 44.835 +*N ropt_net_143:4 *C 7.820 41.525 +*N ropt_net_143:5 *C 7.865 41.480 +*N ropt_net_143:6 *C 15.135 41.480 +*N ropt_net_143:7 *C 15.180 41.435 +*N ropt_net_143:8 *C 15.180 39.825 +*N ropt_net_143:9 *C 15.180 39.780 + +*CAP +0 FTB_12__11:X 1e-06 +1 ropt_mt_inst_766:A 1e-06 +2 ropt_net_143:2 4.399374e-05 +3 ropt_net_143:3 0.0001315928 +4 ropt_net_143:4 0.0001315928 +5 ropt_net_143:5 0.0003378999 +6 ropt_net_143:6 0.0003378999 +7 ropt_net_143:7 0.0001055204 +8 ropt_net_143:8 0.0001055204 +9 ropt_net_143:9 3.222175e-05 +10 ropt_net_143:4 left_bottom_grid_pin_1_[0]:16 9.601449e-05 +11 ropt_net_143:3 left_bottom_grid_pin_1_[0]:15 9.601449e-05 +12 ropt_net_143:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.0002190137 +13 ropt_net_143:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0002190137 +14 ropt_net_143:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 1.74102e-06 +15 ropt_net_143:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 1.74102e-06 +16 ropt_net_143:6 ropt_net_160:4 6.236818e-05 +17 ropt_net_143:5 ropt_net_160:3 6.236818e-05 +18 ropt_net_143:4 ropt_net_160:5 6.513091e-06 +19 ropt_net_143:3 ropt_net_160:6 6.513091e-06 + +*RES +0 FTB_12__11:X ropt_net_143:9 0.152 +1 ropt_net_143:9 ropt_net_143:8 0.0045 +2 ropt_net_143:8 ropt_net_143:7 0.0014375 +3 ropt_net_143:6 ropt_net_143:5 0.006491072 +4 ropt_net_143:7 ropt_net_143:6 0.0045 +5 ropt_net_143:5 ropt_net_143:4 0.0045 +6 ropt_net_143:4 ropt_net_143:3 0.002955357 +7 ropt_net_143:2 ropt_mt_inst_766:A 0.152 +8 ropt_net_143:3 ropt_net_143:2 0.0045 + +*END + +*D_NET ropt_net_149 0.0008292157 //LENGTH 6.730 LUMPCC 0.0001079013 DR + +*CONN +*I BUFT_RR_67:X O *L 0 *C 9.660 34.000 +*I ropt_mt_inst_772:A I *L 0.001766 *C 3.220 34.000 +*N ropt_net_149:2 *C 3.258 34.000 +*N ropt_net_149:3 *C 9.623 34.000 + +*CAP +0 BUFT_RR_67:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_149:2 0.0003596572 +3 ropt_net_149:3 0.0003596572 +4 ropt_net_149:2 chanx_left_in[8]:21 5.395065e-05 +5 ropt_net_149:3 chanx_left_in[8]:20 5.395065e-05 + +*RES +0 BUFT_RR_67:X ropt_net_149:3 0.152 +1 ropt_net_149:2 ropt_mt_inst_772:A 0.152 +2 ropt_net_149:3 ropt_net_149:2 0.005683036 + +*END + +*D_NET ropt_net_164 0.0007258271 //LENGTH 5.105 LUMPCC 0.0002244612 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 7.095 33.660 +*I ropt_mt_inst_790:A I *L 0.001767 *C 5.980 36.720 +*N ropt_net_164:2 *C 6.018 36.720 +*N ropt_net_164:3 *C 6.395 36.720 +*N ropt_net_164:4 *C 6.440 36.675 +*N ropt_net_164:5 *C 6.440 33.705 +*N ropt_net_164:6 *C 6.485 33.660 +*N ropt_net_164:7 *C 7.058 33.660 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 ropt_mt_inst_790:A 1e-06 +2 ropt_net_164:2 5.65042e-05 +3 ropt_net_164:3 5.65042e-05 +4 ropt_net_164:4 0.0001060184 +5 ropt_net_164:5 0.0001060184 +6 ropt_net_164:6 8.716038e-05 +7 ropt_net_164:7 8.716038e-05 +8 ropt_net_164:4 left_bottom_grid_pin_1_[0]:15 4.068397e-05 +9 ropt_net_164:5 left_bottom_grid_pin_1_[0]:16 4.068397e-05 +10 ropt_net_164:4 chanx_left_out[0]:5 7.154662e-05 +11 ropt_net_164:5 chanx_left_out[0]:4 7.154662e-05 + +*RES +0 ropt_mt_inst_772:X ropt_net_164:7 0.152 +1 ropt_net_164:2 ropt_mt_inst_790:A 0.152 +2 ropt_net_164:3 ropt_net_164:2 0.0003370536 +3 ropt_net_164:4 ropt_net_164:3 0.0045 +4 ropt_net_164:6 ropt_net_164:5 0.0045 +5 ropt_net_164:5 ropt_net_164:4 0.002651786 +6 ropt_net_164:7 ropt_net_164:6 0.0005111608 + +*END + +*D_NET chanx_right_out[5] 0.00142422 //LENGTH 9.335 LUMPCC 9.057314e-05 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 136.160 61.200 +*P chanx_right_out[5] O *L 0.7423 *C 140.375 57.120 +*N chanx_right_out[5]:2 *C 140.300 57.800 +*N chanx_right_out[5]:3 *C 137.088 57.800 +*N chanx_right_out[5]:4 *C 137.080 57.858 +*N chanx_right_out[5]:5 *C 137.080 61.155 +*N chanx_right_out[5]:6 *C 137.035 61.200 +*N chanx_right_out[5]:7 *C 136.198 61.200 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 chanx_right_out[5] 5.327291e-05 +2 chanx_right_out[5]:2 0.0003907687 +3 chanx_right_out[5]:3 0.0003374958 +4 chanx_right_out[5]:4 0.0002327089 +5 chanx_right_out[5]:5 0.0002327089 +6 chanx_right_out[5]:6 4.284588e-05 +7 chanx_right_out[5]:7 4.284588e-05 +8 chanx_right_out[5]:7 ropt_net_172:3 4.528657e-05 +9 chanx_right_out[5]:6 ropt_net_172:4 4.528657e-05 + +*RES +0 ropt_mt_inst_799:X chanx_right_out[5]:7 0.152 +1 chanx_right_out[5]:7 chanx_right_out[5]:6 0.0007477679 +2 chanx_right_out[5]:6 chanx_right_out[5]:5 0.0045 +3 chanx_right_out[5]:5 chanx_right_out[5]:4 0.002944197 +4 chanx_right_out[5]:4 chanx_right_out[5]:3 0.00341 +5 chanx_right_out[5]:3 chanx_right_out[5]:2 0.0005032916 +6 chanx_right_out[5]:2 chanx_right_out[5] 0.0001065333 + +*END + +*D_NET chanx_right_in[9] 0.0241009 //LENGTH 192.985 LUMPCC 0.00568697 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 140.450 72.080 +*I mux_top_track_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 115.175 55.080 +*I mux_left_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 60.550 47.940 +*I ropt_mt_inst_761:A I *L 0.001767 *C 3.220 23.120 +*N chanx_right_in[9]:4 *C 3.258 23.120 +*N chanx_right_in[9]:5 *C 3.635 23.120 +*N chanx_right_in[9]:6 *C 3.680 23.165 +*N chanx_right_in[9]:7 *C 3.680 25.115 +*N chanx_right_in[9]:8 *C 3.725 25.160 +*N chanx_right_in[9]:9 *C 12.760 25.160 +*N chanx_right_in[9]:10 *C 12.873 25.205 +*N chanx_right_in[9]:11 *C 12.880 25.795 +*N chanx_right_in[9]:12 *C 12.925 25.840 +*N chanx_right_in[9]:13 *C 13.800 25.840 +*N chanx_right_in[9]:14 *C 13.800 25.840 +*N chanx_right_in[9]:15 *C 13.808 25.840 +*N chanx_right_in[9]:16 *C 55.193 25.840 +*N chanx_right_in[9]:17 *C 55.200 25.898 +*N chanx_right_in[9]:18 *C 55.200 47.895 +*N chanx_right_in[9]:19 *C 55.245 47.940 +*N chanx_right_in[9]:20 *C 60.550 47.940 +*N chanx_right_in[9]:21 *C 91.495 47.940 +*N chanx_right_in[9]:22 *C 91.540 47.985 +*N chanx_right_in[9]:23 *C 91.540 54.343 +*N chanx_right_in[9]:24 *C 91.547 54.400 +*N chanx_right_in[9]:25 *C 115.138 55.080 +*N chanx_right_in[9]:26 *C 114.125 55.080 +*N chanx_right_in[9]:27 *C 114.080 55.035 +*N chanx_right_in[9]:28 *C 114.080 54.458 +*N chanx_right_in[9]:29 *C 114.080 54.400 +*N chanx_right_in[9]:30 *C 132.460 54.400 +*N chanx_right_in[9]:31 *C 132.480 54.408 +*N chanx_right_in[9]:32 *C 132.480 71.392 +*N chanx_right_in[9]:33 *C 132.500 71.400 +*N chanx_right_in[9]:34 *C 138.000 71.400 +*N chanx_right_in[9]:35 *C 138.000 72.080 + +*CAP +0 chanx_right_in[9] 0.0001950514 +1 mux_top_track_10\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_25\/mux_l1_in_1_:A0 1e-06 +3 ropt_mt_inst_761:A 1e-06 +4 chanx_right_in[9]:4 4.501822e-05 +5 chanx_right_in[9]:5 4.501822e-05 +6 chanx_right_in[9]:6 5.079913e-05 +7 chanx_right_in[9]:7 5.079913e-05 +8 chanx_right_in[9]:8 0.0005558831 +9 chanx_right_in[9]:9 0.0005558831 +10 chanx_right_in[9]:10 5.051339e-05 +11 chanx_right_in[9]:11 5.051339e-05 +12 chanx_right_in[9]:12 6.884988e-05 +13 chanx_right_in[9]:13 9.720073e-05 +14 chanx_right_in[9]:14 3.077678e-05 +15 chanx_right_in[9]:15 0.001716326 +16 chanx_right_in[9]:16 0.001716326 +17 chanx_right_in[9]:17 0.001219596 +18 chanx_right_in[9]:18 0.001219596 +19 chanx_right_in[9]:19 0.0001382619 +20 chanx_right_in[9]:20 0.001665732 +21 chanx_right_in[9]:21 0.001499188 +22 chanx_right_in[9]:22 0.000421387 +23 chanx_right_in[9]:23 0.000421387 +24 chanx_right_in[9]:24 0.0008486083 +25 chanx_right_in[9]:25 7.877012e-05 +26 chanx_right_in[9]:26 7.877012e-05 +27 chanx_right_in[9]:27 5.435829e-05 +28 chanx_right_in[9]:28 5.435829e-05 +29 chanx_right_in[9]:29 0.001666195 +30 chanx_right_in[9]:30 0.0008175864 +31 chanx_right_in[9]:31 0.0009392207 +32 chanx_right_in[9]:32 0.0009392207 +33 chanx_right_in[9]:33 0.0004029675 +34 chanx_right_in[9]:34 0.0004623415 +35 chanx_right_in[9]:35 0.0002544254 +36 chanx_right_in[9]:24 top_left_grid_pin_35_[0]:13 0.000283432 +37 chanx_right_in[9]:29 top_left_grid_pin_35_[0]:9 0.000283432 +38 chanx_right_in[9]:26 top_left_grid_pin_35_[0]:6 9.964938e-06 +39 chanx_right_in[9]:25 top_left_grid_pin_35_[0]:5 9.964938e-06 +40 chanx_right_in[9]:19 chanx_right_in[18]:17 0.0002038732 +41 chanx_right_in[9]:21 chanx_right_in[18]:25 8.376945e-05 +42 chanx_right_in[9]:21 chanx_right_in[18]:18 0.0006234781 +43 chanx_right_in[9]:20 chanx_right_in[18]:24 8.376945e-05 +44 chanx_right_in[9]:20 chanx_right_in[18]:18 0.0002038732 +45 chanx_right_in[9]:20 chanx_right_in[18]:17 0.0006234781 +46 chanx_right_in[9]:24 chanx_left_in[18]:12 0.0003002086 +47 chanx_right_in[9]:24 chanx_left_in[18]:13 5.052318e-05 +48 chanx_right_in[9]:30 chanx_left_in[18]:8 0.0003124106 +49 chanx_right_in[9]:29 chanx_left_in[18]:12 0.0003629337 +50 chanx_right_in[9]:29 chanx_left_in[18]:8 0.0003002086 +51 chanx_right_in[9]:24 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 5.120382e-05 +52 chanx_right_in[9]:29 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 5.120382e-05 +53 chanx_right_in[9]:19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001368108 +54 chanx_right_in[9]:20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001368108 +55 chanx_right_in[9]:16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0006073919 +56 chanx_right_in[9]:16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.455905e-06 +57 chanx_right_in[9]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0006073919 +58 chanx_right_in[9]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.455905e-06 +59 chanx_right_in[9]:7 ropt_net_174:3 4.010835e-05 +60 chanx_right_in[9]:5 ropt_net_174:6 1.035878e-05 +61 chanx_right_in[9]:6 ropt_net_174:4 4.010835e-05 +62 chanx_right_in[9]:4 ropt_net_174:5 1.035878e-05 +63 chanx_right_in[9]:9 ropt_net_133:7 5.948518e-05 +64 chanx_right_in[9]:8 ropt_net_133:6 5.948518e-05 +65 chanx_right_in[9]:7 ropt_net_133:5 6.501077e-05 +66 chanx_right_in[9]:6 ropt_net_133:4 6.501077e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:35 0.0003838333 +1 chanx_right_in[9]:19 chanx_right_in[9]:18 0.0045 +2 chanx_right_in[9]:18 chanx_right_in[9]:17 0.01964063 +3 chanx_right_in[9]:17 chanx_right_in[9]:16 0.00341 +4 chanx_right_in[9]:16 chanx_right_in[9]:15 0.006483649 +5 chanx_right_in[9]:14 chanx_right_in[9]:13 0.0045 +6 chanx_right_in[9]:15 chanx_right_in[9]:14 0.00341 +7 chanx_right_in[9]:13 chanx_right_in[9]:12 0.0007812501 +8 chanx_right_in[9]:12 chanx_right_in[9]:11 0.0045 +9 chanx_right_in[9]:11 chanx_right_in[9]:10 0.0005267857 +10 chanx_right_in[9]:9 chanx_right_in[9]:8 0.008066964 +11 chanx_right_in[9]:10 chanx_right_in[9]:9 0.0045 +12 chanx_right_in[9]:8 chanx_right_in[9]:7 0.0045 +13 chanx_right_in[9]:7 chanx_right_in[9]:6 0.001741071 +14 chanx_right_in[9]:5 chanx_right_in[9]:4 0.0003370536 +15 chanx_right_in[9]:6 chanx_right_in[9]:5 0.0045 +16 chanx_right_in[9]:4 ropt_mt_inst_761:A 0.152 +17 chanx_right_in[9]:23 chanx_right_in[9]:22 0.00567634 +18 chanx_right_in[9]:24 chanx_right_in[9]:23 0.00341 +19 chanx_right_in[9]:21 chanx_right_in[9]:20 0.02762947 +20 chanx_right_in[9]:22 chanx_right_in[9]:21 0.0045 +21 chanx_right_in[9]:30 chanx_right_in[9]:29 0.002879533 +22 chanx_right_in[9]:31 chanx_right_in[9]:30 0.00341 +23 chanx_right_in[9]:33 chanx_right_in[9]:32 0.00341 +24 chanx_right_in[9]:32 chanx_right_in[9]:31 0.002660983 +25 chanx_right_in[9]:28 chanx_right_in[9]:27 0.000515625 +26 chanx_right_in[9]:29 chanx_right_in[9]:28 0.00341 +27 chanx_right_in[9]:29 chanx_right_in[9]:24 0.003530091 +28 chanx_right_in[9]:26 chanx_right_in[9]:25 0.000904018 +29 chanx_right_in[9]:27 chanx_right_in[9]:26 0.0045 +30 chanx_right_in[9]:25 mux_top_track_10\/mux_l1_in_0_:A0 0.152 +31 chanx_right_in[9]:20 mux_left_track_25\/mux_l1_in_1_:A0 0.152 +32 chanx_right_in[9]:20 chanx_right_in[9]:19 0.004736607 +33 chanx_right_in[9]:34 chanx_right_in[9]:33 0.0008616666 +34 chanx_right_in[9]:35 chanx_right_in[9]:34 0.0001065333 + +*END + +*D_NET chany_top_in[17] 0.01640017 //LENGTH 113.500 LUMPCC 0.005764167 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 81.420 102.070 +*I mux_right_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 91.080 36.380 +*I mux_left_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 55.660 28.900 +*N chany_top_in[17]:3 *C 55.698 28.900 +*N chany_top_in[17]:4 *C 57.455 28.900 +*N chany_top_in[17]:5 *C 57.500 28.900 +*N chany_top_in[17]:6 *C 57.500 29.240 +*N chany_top_in[17]:7 *C 57.508 29.240 +*N chany_top_in[17]:8 *C 72.220 29.240 +*N chany_top_in[17]:9 *C 72.220 28.560 +*N chany_top_in[17]:10 *C 81.860 28.560 +*N chany_top_in[17]:11 *C 81.880 28.568 +*N chany_top_in[17]:12 *C 91.043 36.380 +*N chany_top_in[17]:13 *C 86.985 36.380 +*N chany_top_in[17]:14 *C 86.940 36.380 +*N chany_top_in[17]:15 *C 86.940 36.040 +*N chany_top_in[17]:16 *C 86.933 36.040 +*N chany_top_in[17]:17 *C 81.900 36.040 +*N chany_top_in[17]:18 *C 81.880 36.040 +*N chany_top_in[17]:19 *C 81.880 86.040 +*N chany_top_in[17]:20 *C 81.880 100.633 +*N chany_top_in[17]:21 *C 81.865 100.640 +*N chany_top_in[17]:22 *C 81.422 100.640 +*N chany_top_in[17]:23 *C 81.420 100.698 + +*CAP +0 chany_top_in[17] 9.7165e-05 +1 mux_right_track_16\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_17\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[17]:3 0.0001634025 +4 chany_top_in[17]:4 0.0001634025 +5 chany_top_in[17]:5 5.624928e-05 +6 chany_top_in[17]:6 6.070383e-05 +7 chany_top_in[17]:7 0.0007987288 +8 chany_top_in[17]:8 0.0008665633 +9 chany_top_in[17]:9 0.0004665045 +10 chany_top_in[17]:10 0.00039867 +11 chany_top_in[17]:11 0.0004438381 +12 chany_top_in[17]:12 0.0002743447 +13 chany_top_in[17]:13 0.0002743447 +14 chany_top_in[17]:14 5.0046e-05 +15 chany_top_in[17]:15 5.407189e-05 +16 chany_top_in[17]:16 0.0003808889 +17 chany_top_in[17]:17 0.0003808889 +18 chany_top_in[17]:18 0.002356055 +19 chany_top_in[17]:19 0.002526624 +20 chany_top_in[17]:20 0.0006144064 +21 chany_top_in[17]:21 5.49676e-05 +22 chany_top_in[17]:22 5.49676e-05 +23 chany_top_in[17]:23 9.7165e-05 +24 chany_top_in[17]:7 chanx_left_in[16]:35 0.0005629295 +25 chany_top_in[17]:8 chanx_left_in[16]:34 0.0005629295 +26 chany_top_in[17]:10 mux_tree_tapbuf_size8_0_sram[0]:16 0.0005498166 +27 chany_top_in[17]:7 mux_tree_tapbuf_size8_0_sram[0]:15 8.151526e-05 +28 chany_top_in[17]:8 mux_tree_tapbuf_size8_0_sram[0]:16 8.151526e-05 +29 chany_top_in[17]:9 mux_tree_tapbuf_size8_0_sram[0]:15 0.0005498166 +30 chany_top_in[17]:20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002342786 +31 chany_top_in[17]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.000562335 +32 chany_top_in[17]:19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002342786 +33 chany_top_in[17]:19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.000562335 +34 chany_top_in[17]:14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 4.042555e-06 +35 chany_top_in[17]:15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 4.042555e-06 +36 chany_top_in[17]:16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.768966e-05 +37 chany_top_in[17]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.768966e-05 +38 chany_top_in[17]:20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 1.142859e-05 +39 chany_top_in[17]:20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.222138e-06 +40 chany_top_in[17]:18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0008028259 +41 chany_top_in[17]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 1.142859e-05 +42 chany_top_in[17]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0008028259 +43 chany_top_in[17]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.222138e-06 + +*RES +0 chany_top_in[17] chany_top_in[17]:23 0.001225447 +1 chany_top_in[17]:21 chany_top_in[17]:20 0.00341 +2 chany_top_in[17]:20 chany_top_in[17]:19 0.002286158 +3 chany_top_in[17]:23 chany_top_in[17]:22 0.00341 +4 chany_top_in[17]:22 chany_top_in[17]:21 6.499219e-05 +5 chany_top_in[17]:12 mux_right_track_16\/mux_l1_in_1_:A1 0.152 +6 chany_top_in[17]:13 chany_top_in[17]:12 0.003622768 +7 chany_top_in[17]:14 chany_top_in[17]:13 0.0045 +8 chany_top_in[17]:15 chany_top_in[17]:14 0.0001634615 +9 chany_top_in[17]:16 chany_top_in[17]:15 0.00341 +10 chany_top_in[17]:17 chany_top_in[17]:16 0.000788425 +11 chany_top_in[17]:18 chany_top_in[17]:17 0.00341 +12 chany_top_in[17]:18 chany_top_in[17]:11 0.001170692 +13 chany_top_in[17]:10 chany_top_in[17]:9 0.001510267 +14 chany_top_in[17]:11 chany_top_in[17]:10 0.00341 +15 chany_top_in[17]:6 chany_top_in[17]:5 0.0001634615 +16 chany_top_in[17]:7 chany_top_in[17]:6 0.00341 +17 chany_top_in[17]:4 chany_top_in[17]:3 0.001569197 +18 chany_top_in[17]:5 chany_top_in[17]:4 0.0045 +19 chany_top_in[17]:3 mux_left_track_17\/mux_l1_in_1_:A1 0.152 +20 chany_top_in[17]:8 chany_top_in[17]:7 0.002304958 +21 chany_top_in[17]:9 chany_top_in[17]:8 0.0001065333 +22 chany_top_in[17]:19 chany_top_in[17]:18 0.007833333 + +*END + +*D_NET chanx_right_in[1] 0.01749542 //LENGTH 135.450 LUMPCC 0.00372131 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 140.382 16.320 +*I mux_top_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 57.345 66.300 +*N chanx_right_in[1]:2 *C 57.345 66.300 +*N chanx_right_in[1]:3 *C 57.500 66.300 +*N chanx_right_in[1]:4 *C 57.500 66.255 +*N chanx_right_in[1]:5 *C 57.500 65.338 +*N chanx_right_in[1]:6 *C 57.508 65.280 +*N chanx_right_in[1]:7 *C 66.220 65.280 +*N chanx_right_in[1]:8 *C 66.240 65.273 +*N chanx_right_in[1]:9 *C 66.240 17.008 +*N chanx_right_in[1]:10 *C 66.260 17.000 +*N chanx_right_in[1]:11 *C 70.373 17.000 +*N chanx_right_in[1]:12 *C 70.380 17.000 +*N chanx_right_in[1]:13 *C 70.425 17.000 +*N chanx_right_in[1]:14 *C 120.220 17.000 +*N chanx_right_in[1]:15 *C 140.255 17.000 +*N chanx_right_in[1]:16 *C 140.300 16.955 +*N chanx_right_in[1]:17 *C 140.300 16.378 +*N chanx_right_in[1]:18 *C 140.300 16.320 + +*CAP +0 chanx_right_in[1] 2.61856e-05 +1 mux_top_track_0\/mux_l2_in_1_:A0 1e-06 +2 chanx_right_in[1]:2 6.315994e-05 +3 chanx_right_in[1]:3 6.532441e-05 +4 chanx_right_in[1]:4 8.023715e-05 +5 chanx_right_in[1]:5 8.023715e-05 +6 chanx_right_in[1]:6 0.0002390136 +7 chanx_right_in[1]:7 0.0002390136 +8 chanx_right_in[1]:8 0.002433281 +9 chanx_right_in[1]:9 0.002433281 +10 chanx_right_in[1]:10 0.000149859 +11 chanx_right_in[1]:11 0.000149859 +12 chanx_right_in[1]:12 3.390581e-05 +13 chanx_right_in[1]:13 0.002718708 +14 chanx_right_in[1]:14 0.003829648 +15 chanx_right_in[1]:15 0.001110941 +16 chanx_right_in[1]:16 4.713403e-05 +17 chanx_right_in[1]:17 4.713403e-05 +18 chanx_right_in[1]:18 2.61856e-05 +19 chanx_right_in[1]:10 chanx_right_in[14]:21 0.0002484336 +20 chanx_right_in[1]:11 chanx_right_in[14]:22 0.0002484336 +21 chanx_right_in[1]:13 chanx_right_in[14]:21 0.0001208696 +22 chanx_right_in[1]:13 chanx_right_in[14]:22 1.281201e-05 +23 chanx_right_in[1]:15 chanx_right_in[14] 5.618421e-05 +24 chanx_right_in[1]:14 chanx_right_in[14] 1.281201e-05 +25 chanx_right_in[1]:14 chanx_right_in[14]:22 0.0001770538 +26 chanx_right_in[1]:6 chanx_left_in[13]:19 0.0004511775 +27 chanx_right_in[1]:7 chanx_left_in[13]:18 0.0004511775 +28 chanx_right_in[1]:6 chany_top_in[8]:6 0.0004893659 +29 chanx_right_in[1]:7 chany_top_in[8]:7 0.0004893659 +30 chanx_right_in[1]:8 chany_top_in[10]:20 0.0004818124 +31 chanx_right_in[1]:9 chany_top_in[10]:19 0.0004818124 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:18 2.35e-05 +1 chanx_right_in[1]:2 mux_top_track_0\/mux_l2_in_1_:A0 0.152 +2 chanx_right_in[1]:3 chanx_right_in[1]:2 8.423914e-05 +3 chanx_right_in[1]:4 chanx_right_in[1]:3 0.0045 +4 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0008191965 +5 chanx_right_in[1]:6 chanx_right_in[1]:5 0.00341 +6 chanx_right_in[1]:7 chanx_right_in[1]:6 0.001364958 +7 chanx_right_in[1]:8 chanx_right_in[1]:7 0.00341 +8 chanx_right_in[1]:10 chanx_right_in[1]:9 0.00341 +9 chanx_right_in[1]:9 chanx_right_in[1]:8 0.007561516 +10 chanx_right_in[1]:12 chanx_right_in[1]:11 0.00341 +11 chanx_right_in[1]:11 chanx_right_in[1]:10 0.0006442917 +12 chanx_right_in[1]:13 chanx_right_in[1]:12 0.0045 +13 chanx_right_in[1]:15 chanx_right_in[1]:14 0.0178884 +14 chanx_right_in[1]:16 chanx_right_in[1]:15 0.0045 +15 chanx_right_in[1]:17 chanx_right_in[1]:16 0.000515625 +16 chanx_right_in[1]:18 chanx_right_in[1]:17 0.00341 +17 chanx_right_in[1]:14 chanx_right_in[1]:13 0.04445983 + +*END + +*D_NET chanx_right_in[15] 0.00458627 //LENGTH 33.375 LUMPCC 0.0007861307 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 140.450 42.160 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 114.370 42.500 +*N chanx_right_in[15]:2 *C 114.407 42.500 +*N chanx_right_in[15]:3 *C 116.335 42.500 +*N chanx_right_in[15]:4 *C 116.380 42.455 +*N chanx_right_in[15]:5 *C 116.380 39.498 +*N chanx_right_in[15]:6 *C 116.388 39.440 +*N chanx_right_in[15]:7 *C 134.312 39.440 +*N chanx_right_in[15]:8 *C 134.320 39.498 +*N chanx_right_in[15]:9 *C 134.320 42.102 +*N chanx_right_in[15]:10 *C 134.328 42.160 + +*CAP +0 chanx_right_in[15] 0.0004388464 +1 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +2 chanx_right_in[15]:2 0.0001356369 +3 chanx_right_in[15]:3 0.0001356369 +4 chanx_right_in[15]:4 0.000183072 +5 chanx_right_in[15]:5 0.000183072 +6 chanx_right_in[15]:6 0.0009460927 +7 chanx_right_in[15]:7 0.0009460927 +8 chanx_right_in[15]:8 0.0001959216 +9 chanx_right_in[15]:9 0.0001959216 +10 chanx_right_in[15]:10 0.0004388464 +11 chanx_right_in[15]:6 chanx_left_in[16]:26 0.0003930653 +12 chanx_right_in[15]:7 chanx_left_in[16]:25 0.0003930653 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:10 0.0009591916 +1 chanx_right_in[15]:2 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +2 chanx_right_in[15]:3 chanx_right_in[15]:2 0.001720982 +3 chanx_right_in[15]:4 chanx_right_in[15]:3 0.0045 +4 chanx_right_in[15]:5 chanx_right_in[15]:4 0.002640625 +5 chanx_right_in[15]:6 chanx_right_in[15]:5 0.00341 +6 chanx_right_in[15]:8 chanx_right_in[15]:7 0.00341 +7 chanx_right_in[15]:7 chanx_right_in[15]:6 0.00280825 +8 chanx_right_in[15]:9 chanx_right_in[15]:8 0.002325893 +9 chanx_right_in[15]:10 chanx_right_in[15]:9 0.00341 + +*END + +*D_NET right_top_grid_pin_47_[0] 0.01145497 //LENGTH 92.240 LUMPCC 0.001770082 DR + +*CONN +*P right_top_grid_pin_47_[0] I *L 0.29796 *C 111.930 90.440 +*I mux_right_track_4\/mux_l1_in_4_:A1 I *L 0.00198 *C 106.820 66.980 +*I mux_right_track_16\/mux_l1_in_2_:A1 I *L 0.00198 *C 101.200 28.900 +*I mux_right_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 98.155 82.280 +*N right_top_grid_pin_47_[0]:4 *C 98.193 82.280 +*N right_top_grid_pin_47_[0]:5 *C 100.695 82.280 +*N right_top_grid_pin_47_[0]:6 *C 100.740 82.325 +*N right_top_grid_pin_47_[0]:7 *C 100.740 90.383 +*N right_top_grid_pin_47_[0]:8 *C 100.748 90.440 +*N right_top_grid_pin_47_[0]:9 *C 106.010 65.960 +*N right_top_grid_pin_47_[0]:10 *C 101.200 28.900 +*N right_top_grid_pin_47_[0]:11 *C 101.200 28.945 +*N right_top_grid_pin_47_[0]:12 *C 101.200 31.902 +*N right_top_grid_pin_47_[0]:13 *C 101.208 31.960 +*N right_top_grid_pin_47_[0]:14 *C 106.700 31.960 +*N right_top_grid_pin_47_[0]:15 *C 106.720 31.968 +*N right_top_grid_pin_47_[0]:16 *C 106.720 65.953 +*N right_top_grid_pin_47_[0]:17 *C 106.718 65.960 +*N right_top_grid_pin_47_[0]:18 *C 106.720 66.017 +*N right_top_grid_pin_47_[0]:19 *C 106.720 66.980 +*N right_top_grid_pin_47_[0]:20 *C 106.720 66.980 +*N right_top_grid_pin_47_[0]:21 *C 106.720 90.383 +*N right_top_grid_pin_47_[0]:22 *C 106.720 90.440 + +*CAP +0 right_top_grid_pin_47_[0] 0.0002596895 +1 mux_right_track_4\/mux_l1_in_4_:A1 1e-06 +2 mux_right_track_16\/mux_l1_in_2_:A1 1e-06 +3 mux_right_track_2\/mux_l2_in_1_:A0 1e-06 +4 right_top_grid_pin_47_[0]:4 0.0002240711 +5 right_top_grid_pin_47_[0]:5 0.0002240711 +6 right_top_grid_pin_47_[0]:6 0.0004635025 +7 right_top_grid_pin_47_[0]:7 0.0004635025 +8 right_top_grid_pin_47_[0]:8 0.0002815213 +9 right_top_grid_pin_47_[0]:9 9.855221e-05 +10 right_top_grid_pin_47_[0]:10 3.24926e-05 +11 right_top_grid_pin_47_[0]:11 0.0001838255 +12 right_top_grid_pin_47_[0]:12 0.0001838255 +13 right_top_grid_pin_47_[0]:13 0.0004327187 +14 right_top_grid_pin_47_[0]:14 0.0004327187 +15 right_top_grid_pin_47_[0]:15 0.001746907 +16 right_top_grid_pin_47_[0]:16 0.001746907 +17 right_top_grid_pin_47_[0]:17 9.855221e-05 +18 right_top_grid_pin_47_[0]:18 7.250372e-05 +19 right_top_grid_pin_47_[0]:19 3.4435e-05 +20 right_top_grid_pin_47_[0]:20 0.001132779 +21 right_top_grid_pin_47_[0]:21 0.001028099 +22 right_top_grid_pin_47_[0]:22 0.0005412108 +23 right_top_grid_pin_47_[0]:16 chanx_left_in[4]:19 0.0002985059 +24 right_top_grid_pin_47_[0]:15 chanx_left_in[4]:18 0.0002985059 +25 right_top_grid_pin_47_[0] right_top_grid_pin_43_[0]:25 5.964353e-05 +26 right_top_grid_pin_47_[0]:21 right_top_grid_pin_43_[0]:22 1.435477e-05 +27 right_top_grid_pin_47_[0]:21 right_top_grid_pin_43_[0]:23 0.0002342986 +28 right_top_grid_pin_47_[0]:22 right_top_grid_pin_43_[0]:24 0.0001273197 +29 right_top_grid_pin_47_[0]:22 right_top_grid_pin_43_[0]:25 1.420729e-05 +30 right_top_grid_pin_47_[0]:16 right_top_grid_pin_43_[0]:16 0.0001963548 +31 right_top_grid_pin_47_[0]:15 right_top_grid_pin_43_[0]:15 0.0001963548 +32 right_top_grid_pin_47_[0]:8 right_top_grid_pin_43_[0]:8 6.767613e-05 +33 right_top_grid_pin_47_[0]:8 right_top_grid_pin_43_[0]:24 1.420729e-05 +34 right_top_grid_pin_47_[0]:20 right_top_grid_pin_43_[0]:19 1.435477e-05 +35 right_top_grid_pin_47_[0]:20 right_top_grid_pin_43_[0]:22 0.0002342986 + +*RES +0 right_top_grid_pin_47_[0] right_top_grid_pin_47_[0]:22 0.0008162333 +1 right_top_grid_pin_47_[0]:21 right_top_grid_pin_47_[0]:20 0.02089509 +2 right_top_grid_pin_47_[0]:22 right_top_grid_pin_47_[0]:21 0.00341 +3 right_top_grid_pin_47_[0]:22 right_top_grid_pin_47_[0]:8 0.0009356916 +4 right_top_grid_pin_47_[0]:18 right_top_grid_pin_47_[0]:17 0.00341 +5 right_top_grid_pin_47_[0]:17 right_top_grid_pin_47_[0]:16 0.00341 +6 right_top_grid_pin_47_[0]:17 right_top_grid_pin_47_[0]:9 0.0001039141 +7 right_top_grid_pin_47_[0]:16 right_top_grid_pin_47_[0]:15 0.005324316 +8 right_top_grid_pin_47_[0]:14 right_top_grid_pin_47_[0]:13 0.0008604916 +9 right_top_grid_pin_47_[0]:15 right_top_grid_pin_47_[0]:14 0.00341 +10 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:11 0.002640625 +11 right_top_grid_pin_47_[0]:13 right_top_grid_pin_47_[0]:12 0.00341 +12 right_top_grid_pin_47_[0]:10 mux_right_track_16\/mux_l1_in_2_:A1 0.152 +13 right_top_grid_pin_47_[0]:11 right_top_grid_pin_47_[0]:10 0.0045 +14 right_top_grid_pin_47_[0]:7 right_top_grid_pin_47_[0]:6 0.007194196 +15 right_top_grid_pin_47_[0]:8 right_top_grid_pin_47_[0]:7 0.00341 +16 right_top_grid_pin_47_[0]:5 right_top_grid_pin_47_[0]:4 0.002234375 +17 right_top_grid_pin_47_[0]:6 right_top_grid_pin_47_[0]:5 0.0045 +18 right_top_grid_pin_47_[0]:4 mux_right_track_2\/mux_l2_in_1_:A0 0.152 +19 right_top_grid_pin_47_[0]:19 mux_right_track_4\/mux_l1_in_4_:A1 0.152 +20 right_top_grid_pin_47_[0]:20 right_top_grid_pin_47_[0]:19 0.0045 +21 right_top_grid_pin_47_[0]:20 right_top_grid_pin_47_[0]:18 0.0008593751 + +*END + +*D_NET chanx_left_in[15] 0.01211125 //LENGTH 93.265 LUMPCC 0.001320407 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 42.160 +*I mux_top_track_30\/mux_l1_in_0_:A0 I *L 0.001631 *C 53.650 80.920 +*N chanx_left_in[15]:2 *C 53.613 80.920 +*N chanx_left_in[15]:3 *C 50.140 80.920 +*N chanx_left_in[15]:4 *C 50.140 80.580 +*N chanx_left_in[15]:5 *C 48.760 80.580 +*N chanx_left_in[15]:6 *C 48.760 80.240 +*N chanx_left_in[15]:7 *C 31.785 80.240 +*N chanx_left_in[15]:8 *C 31.740 80.195 +*N chanx_left_in[15]:9 *C 31.740 75.538 +*N chanx_left_in[15]:10 *C 31.733 75.480 +*N chanx_left_in[15]:11 *C 29.460 75.480 +*N chanx_left_in[15]:12 *C 29.440 75.472 +*N chanx_left_in[15]:13 *C 29.440 42.168 +*N chanx_left_in[15]:14 *C 29.420 42.160 + +*CAP +0 chanx_left_in[15] 0.001773217 +1 mux_top_track_30\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[15]:2 0.0002499277 +3 chanx_left_in[15]:3 0.0002761058 +4 chanx_left_in[15]:4 0.0001490923 +5 chanx_left_in[15]:5 0.0001491581 +6 chanx_left_in[15]:6 0.0009736746 +7 chanx_left_in[15]:7 0.0009474308 +8 chanx_left_in[15]:8 0.0002282672 +9 chanx_left_in[15]:9 0.0002282672 +10 chanx_left_in[15]:10 0.0002008871 +11 chanx_left_in[15]:11 0.0002008871 +12 chanx_left_in[15]:12 0.001819854 +13 chanx_left_in[15]:13 0.001819854 +14 chanx_left_in[15]:14 0.001773217 +15 chanx_left_in[15]:12 chanx_left_in[3]:8 0.0003945221 +16 chanx_left_in[15]:13 chanx_left_in[3]:9 0.0003945221 +17 chanx_left_in[15]:7 mux_tree_tapbuf_size10_0_sram[0]:18 7.303314e-05 +18 chanx_left_in[15]:7 mux_tree_tapbuf_size10_0_sram[0]:19 0.0001339019 +19 chanx_left_in[15]:7 mux_tree_tapbuf_size10_0_sram[0]:11 6.730373e-06 +20 chanx_left_in[15]:8 mux_tree_tapbuf_size10_0_sram[0]:17 5.165118e-05 +21 chanx_left_in[15]:8 mux_tree_tapbuf_size10_0_sram[0]:15 3.650717e-07 +22 chanx_left_in[15]:9 mux_tree_tapbuf_size10_0_sram[0]:14 3.650717e-07 +23 chanx_left_in[15]:9 mux_tree_tapbuf_size10_0_sram[0]:16 5.165118e-05 +24 chanx_left_in[15]:6 mux_tree_tapbuf_size10_0_sram[0]:19 7.303314e-05 +25 chanx_left_in[15]:6 mux_tree_tapbuf_size10_0_sram[0]:20 6.730373e-06 +26 chanx_left_in[15]:6 mux_tree_tapbuf_size10_0_sram[0]:12 0.0001339019 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:14 0.004416433 +1 chanx_left_in[15]:2 mux_top_track_30\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[15]:7 chanx_left_in[15]:6 0.01515625 +3 chanx_left_in[15]:8 chanx_left_in[15]:7 0.0045 +4 chanx_left_in[15]:9 chanx_left_in[15]:8 0.004158482 +5 chanx_left_in[15]:10 chanx_left_in[15]:9 0.00341 +6 chanx_left_in[15]:11 chanx_left_in[15]:10 0.000356025 +7 chanx_left_in[15]:12 chanx_left_in[15]:11 0.00341 +8 chanx_left_in[15]:14 chanx_left_in[15]:13 0.00341 +9 chanx_left_in[15]:13 chanx_left_in[15]:12 0.005217783 +10 chanx_left_in[15]:6 chanx_left_in[15]:5 0.0003035715 +11 chanx_left_in[15]:5 chanx_left_in[15]:4 0.001232143 +12 chanx_left_in[15]:4 chanx_left_in[15]:3 0.0003035714 +13 chanx_left_in[15]:3 chanx_left_in[15]:2 0.003100447 + +*END + +*D_NET left_top_grid_pin_47_[0] 0.009617451 //LENGTH 72.490 LUMPCC 0.001571739 DR + +*CONN +*P left_top_grid_pin_47_[0] I *L 0.29796 *C 3.220 74.870 +*I mux_left_track_5\/mux_l1_in_5_:A1 I *L 0.00198 *C 17.020 52.700 +*I mux_left_track_17\/mux_l1_in_3_:A1 I *L 0.00198 *C 33.120 36.380 +*I mux_left_track_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 4.775 71.400 +*N left_top_grid_pin_47_[0]:4 *C 4.650 71.400 +*N left_top_grid_pin_47_[0]:5 *C 33.083 36.380 +*N left_top_grid_pin_47_[0]:6 *C 29.485 36.380 +*N left_top_grid_pin_47_[0]:7 *C 29.440 36.425 +*N left_top_grid_pin_47_[0]:8 *C 29.440 38.023 +*N left_top_grid_pin_47_[0]:9 *C 29.433 38.080 +*N left_top_grid_pin_47_[0]:10 *C 19.788 38.080 +*N left_top_grid_pin_47_[0]:11 *C 19.780 38.138 +*N left_top_grid_pin_47_[0]:12 *C 19.780 52.995 +*N left_top_grid_pin_47_[0]:13 *C 19.735 53.040 +*N left_top_grid_pin_47_[0]:14 *C 17.058 53.040 +*N left_top_grid_pin_47_[0]:15 *C 17.020 52.700 +*N left_top_grid_pin_47_[0]:16 *C 12.880 52.700 +*N left_top_grid_pin_47_[0]:17 *C 12.880 53.720 +*N left_top_grid_pin_47_[0]:18 *C 4.645 53.720 +*N left_top_grid_pin_47_[0]:19 *C 4.600 53.765 +*N left_top_grid_pin_47_[0]:20 *C 4.600 71.355 +*N left_top_grid_pin_47_[0]:21 *C 4.555 71.400 +*N left_top_grid_pin_47_[0]:22 *C 3.265 71.400 +*N left_top_grid_pin_47_[0]:23 *C 3.220 71.445 + +*CAP +0 left_top_grid_pin_47_[0] 0.0001863602 +1 mux_left_track_5\/mux_l1_in_5_:A1 1e-06 +2 mux_left_track_17\/mux_l1_in_3_:A1 1e-06 +3 mux_left_track_3\/mux_l2_in_2_:A0 1e-06 +4 left_top_grid_pin_47_[0]:4 2.45363e-05 +5 left_top_grid_pin_47_[0]:5 0.0002805723 +6 left_top_grid_pin_47_[0]:6 0.0002805723 +7 left_top_grid_pin_47_[0]:7 0.0001079983 +8 left_top_grid_pin_47_[0]:8 0.0001079983 +9 left_top_grid_pin_47_[0]:9 0.0008132962 +10 left_top_grid_pin_47_[0]:10 0.0008132962 +11 left_top_grid_pin_47_[0]:11 0.0007799723 +12 left_top_grid_pin_47_[0]:12 0.0007799723 +13 left_top_grid_pin_47_[0]:13 0.0001919765 +14 left_top_grid_pin_47_[0]:14 0.0002290567 +15 left_top_grid_pin_47_[0]:15 0.000192442 +16 left_top_grid_pin_47_[0]:16 0.0002240931 +17 left_top_grid_pin_47_[0]:17 0.0005780101 +18 left_top_grid_pin_47_[0]:18 0.0005092789 +19 left_top_grid_pin_47_[0]:19 0.0007753483 +20 left_top_grid_pin_47_[0]:20 0.0007753483 +21 left_top_grid_pin_47_[0]:21 0.0001153794 +22 left_top_grid_pin_47_[0]:22 9.08431e-05 +23 left_top_grid_pin_47_[0]:23 0.0001863602 +24 left_top_grid_pin_47_[0] left_top_grid_pin_45_[0] 4.051342e-06 +25 left_top_grid_pin_47_[0] left_top_grid_pin_45_[0]:13 1.223671e-06 +26 left_top_grid_pin_47_[0]:23 left_top_grid_pin_45_[0]:11 1.223671e-06 +27 left_top_grid_pin_47_[0]:23 left_top_grid_pin_45_[0]:13 4.051342e-06 +28 left_top_grid_pin_47_[0]:19 left_top_grid_pin_45_[0]:11 0.0002623671 +29 left_top_grid_pin_47_[0]:20 left_top_grid_pin_45_[0]:13 0.0002623671 +30 left_top_grid_pin_47_[0]:13 mux_tree_tapbuf_size14_1_sram[0]:44 2.851665e-05 +31 left_top_grid_pin_47_[0]:15 mux_tree_tapbuf_size14_1_sram[0]:43 0.0001245947 +32 left_top_grid_pin_47_[0]:15 mux_tree_tapbuf_size14_1_sram[0]:44 3.547102e-05 +33 left_top_grid_pin_47_[0]:18 mux_tree_tapbuf_size14_1_sram[0]:42 2.378268e-06 +34 left_top_grid_pin_47_[0]:19 mux_tree_tapbuf_size14_1_sram[0]:34 0.0001141965 +35 left_top_grid_pin_47_[0]:20 mux_tree_tapbuf_size14_1_sram[0]:33 0.0001141965 +36 left_top_grid_pin_47_[0]:17 mux_tree_tapbuf_size14_1_sram[0]:43 2.378268e-06 +37 left_top_grid_pin_47_[0]:16 mux_tree_tapbuf_size14_1_sram[0]:42 0.0001245947 +38 left_top_grid_pin_47_[0]:16 mux_tree_tapbuf_size14_1_sram[0]:43 3.547102e-05 +39 left_top_grid_pin_47_[0]:14 mux_tree_tapbuf_size14_1_sram[0]:43 2.851665e-05 +40 left_top_grid_pin_47_[0]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 6.012993e-05 +41 left_top_grid_pin_47_[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 6.012993e-05 +42 left_top_grid_pin_47_[0]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 3.455209e-05 +43 left_top_grid_pin_47_[0]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.455209e-05 +44 left_top_grid_pin_47_[0]:18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001183882 +45 left_top_grid_pin_47_[0]:17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001183882 + +*RES +0 left_top_grid_pin_47_[0] left_top_grid_pin_47_[0]:23 0.003058036 +1 left_top_grid_pin_47_[0]:13 left_top_grid_pin_47_[0]:12 0.0045 +2 left_top_grid_pin_47_[0]:12 left_top_grid_pin_47_[0]:11 0.01326563 +3 left_top_grid_pin_47_[0]:11 left_top_grid_pin_47_[0]:10 0.00341 +4 left_top_grid_pin_47_[0]:10 left_top_grid_pin_47_[0]:9 0.00151105 +5 left_top_grid_pin_47_[0]:8 left_top_grid_pin_47_[0]:7 0.001426339 +6 left_top_grid_pin_47_[0]:9 left_top_grid_pin_47_[0]:8 0.00341 +7 left_top_grid_pin_47_[0]:6 left_top_grid_pin_47_[0]:5 0.003212054 +8 left_top_grid_pin_47_[0]:7 left_top_grid_pin_47_[0]:6 0.0045 +9 left_top_grid_pin_47_[0]:5 mux_left_track_17\/mux_l1_in_3_:A1 0.152 +10 left_top_grid_pin_47_[0]:15 mux_left_track_5\/mux_l1_in_5_:A1 0.152 +11 left_top_grid_pin_47_[0]:15 left_top_grid_pin_47_[0]:14 0.0001465517 +12 left_top_grid_pin_47_[0]:22 left_top_grid_pin_47_[0]:21 0.001151786 +13 left_top_grid_pin_47_[0]:23 left_top_grid_pin_47_[0]:22 0.0045 +14 left_top_grid_pin_47_[0]:18 left_top_grid_pin_47_[0]:17 0.007352679 +15 left_top_grid_pin_47_[0]:19 left_top_grid_pin_47_[0]:18 0.0045 +16 left_top_grid_pin_47_[0]:21 left_top_grid_pin_47_[0]:20 0.0045 +17 left_top_grid_pin_47_[0]:21 left_top_grid_pin_47_[0]:4 8.482143e-05 +18 left_top_grid_pin_47_[0]:20 left_top_grid_pin_47_[0]:19 0.01570536 +19 left_top_grid_pin_47_[0]:4 mux_left_track_3\/mux_l2_in_2_:A0 0.152 +20 left_top_grid_pin_47_[0]:17 left_top_grid_pin_47_[0]:16 0.0009107144 +21 left_top_grid_pin_47_[0]:16 left_top_grid_pin_47_[0]:15 0.003696429 +22 left_top_grid_pin_47_[0]:14 left_top_grid_pin_47_[0]:13 0.002390625 + +*END + +*D_NET chanx_left_out[0] 0.003733565 //LENGTH 24.645 LUMPCC 0.001147437 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 12.825 39.100 +*P chanx_left_out[0] O *L 0.7423 *C 1.305 27.200 +*N chanx_left_out[0]:2 *C 1.380 27.880 +*N chanx_left_out[0]:3 *C 5.973 27.880 +*N chanx_left_out[0]:4 *C 5.980 27.938 +*N chanx_left_out[0]:5 *C 5.980 39.055 +*N chanx_left_out[0]:6 *C 6.003 39.100 +*N chanx_left_out[0]:7 *C 6.408 39.100 +*N chanx_left_out[0]:8 *C 12.788 39.100 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 5.237269e-05 +2 chanx_left_out[0]:2 0.0002912218 +3 chanx_left_out[0]:3 0.0002388491 +4 chanx_left_out[0]:4 0.0006456499 +5 chanx_left_out[0]:5 0.0006456499 +6 chanx_left_out[0]:6 4.076597e-05 +7 chanx_left_out[0]:7 0.0003556924 +8 chanx_left_out[0]:8 0.0003149264 +9 chanx_left_out[0]:3 chanx_left_in[16]:35 0.0002755075 +10 chanx_left_out[0]:2 chanx_left_in[16] 0.0002755075 +11 chanx_left_out[0]:8 ropt_net_156:4 0.0002017509 +12 chanx_left_out[0]:6 ropt_net_156:3 2.491338e-05 +13 chanx_left_out[0]:7 ropt_net_156:4 2.491338e-05 +14 chanx_left_out[0]:7 ropt_net_156:3 0.0002017509 +15 chanx_left_out[0]:5 ropt_net_164:4 7.154662e-05 +16 chanx_left_out[0]:4 ropt_net_164:5 7.154662e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:8 0.152 +1 chanx_left_out[0]:8 chanx_left_out[0]:7 0.005696429 +2 chanx_left_out[0]:6 chanx_left_out[0]:5 0.0045 +3 chanx_left_out[0]:5 chanx_left_out[0]:4 0.00992634 +4 chanx_left_out[0]:4 chanx_left_out[0]:3 0.00341 +5 chanx_left_out[0]:3 chanx_left_out[0]:2 0.0007194916 +6 chanx_left_out[0]:7 chanx_left_out[0]:6 0.0002201087 +7 chanx_left_out[0]:2 chanx_left_out[0] 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.002787881 //LENGTH 21.920 LUMPCC 0 DR + +*CONN +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 70.225 25.840 +*I mux_top_track_28\/mux_l1_in_0_:S I *L 0.00357 *C 62.460 23.800 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 53.995 26.180 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 53.995 26.180 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 54.280 26.180 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 54.280 26.135 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 54.280 23.845 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 54.325 23.800 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 62.460 23.800 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 68.495 23.800 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 68.540 23.845 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 68.540 25.795 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 68.585 25.840 +*N mux_tree_tapbuf_size2_0_sram[0]:13 *C 70.188 25.840 + +*CAP +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_28\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 4.798081e-05 +4 mux_tree_tapbuf_size2_0_sram[0]:4 5.225832e-05 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.000132573 +6 mux_tree_tapbuf_size2_0_sram[0]:6 0.000132573 +7 mux_tree_tapbuf_size2_0_sram[0]:7 0.0005516632 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0009888518 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0004105704 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0001147077 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.0001147077 +12 mux_tree_tapbuf_size2_0_sram[0]:12 0.0001194975 +13 mux_tree_tapbuf_size2_0_sram[0]:13 0.0001194975 + +*RES +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:8 mux_top_track_28\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.007263393 +3 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size2_0_sram[0]:6 mux_tree_tapbuf_size2_0_sram[0]:5 0.002044643 +5 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 0.0001548913 +6 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size2_0_sram[0]:3 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.005388393 +9 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.001741072 +12 mux_tree_tapbuf_size2_0_sram[0]:13 mux_tree_tapbuf_size2_0_sram[0]:12 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.001897915 //LENGTH 18.760 LUMPCC 0 DR + +*CONN +*I mem_top_track_28\/FTB_22__48:X O *L 0 *C 52.665 23.120 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 48.935 37.060 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 48.935 37.060 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 48.760 37.060 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 48.760 37.015 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 48.760 23.165 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 48.805 23.120 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 52.628 23.120 + +*CAP +0 mem_top_track_28\/FTB_22__48:X 1e-06 +1 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 4.413006e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 4.789804e-05 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0006973197 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0006973197 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0002046236 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0002046236 + +*RES +0 mem_top_track_28\/FTB_22__48:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.003412946 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.01236607 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001869763 //LENGTH 13.780 LUMPCC 0 DR + +*CONN +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 48.465 59.160 +*I mux_top_track_14\/mux_l2_in_0_:S I *L 0.00357 *C 48.860 63.580 +*I mem_top_track_14\/FTB_15__41:A I *L 0.001746 *C 44.620 55.760 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 44.657 55.760 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 45.955 55.760 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 46.000 55.805 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 46.000 59.115 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 46.045 59.160 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 48.823 63.580 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 48.345 63.580 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 48.300 63.535 +*N mux_tree_tapbuf_size3_1_sram[1]:11 *C 48.300 59.205 +*N mux_tree_tapbuf_size3_1_sram[1]:12 *C 48.255 59.160 +*N mux_tree_tapbuf_size3_1_sram[1]:13 *C 48.345 59.160 + +*CAP +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_14\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_14\/FTB_15__41:A 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 0.0001233475 +4 mux_tree_tapbuf_size3_1_sram[1]:4 0.0001233475 +5 mux_tree_tapbuf_size3_1_sram[1]:5 0.0002517169 +6 mux_tree_tapbuf_size3_1_sram[1]:6 0.0002517169 +7 mux_tree_tapbuf_size3_1_sram[1]:7 0.0001987119 +8 mux_tree_tapbuf_size3_1_sram[1]:8 6.298313e-05 +9 mux_tree_tapbuf_size3_1_sram[1]:9 6.298313e-05 +10 mux_tree_tapbuf_size3_1_sram[1]:10 0.0002674118 +11 mux_tree_tapbuf_size3_1_sram[1]:11 0.0002674118 +12 mux_tree_tapbuf_size3_1_sram[1]:12 0.0002279221 +13 mux_tree_tapbuf_size3_1_sram[1]:13 2.921024e-05 + +*RES +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:13 mux_tree_tapbuf_size3_1_sram[1]:12 8.035715e-05 +2 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size3_1_sram[1]:6 mux_tree_tapbuf_size3_1_sram[1]:5 0.002955357 +4 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.001158482 +5 mux_tree_tapbuf_size3_1_sram[1]:5 mux_tree_tapbuf_size3_1_sram[1]:4 0.0045 +6 mux_tree_tapbuf_size3_1_sram[1]:3 mem_top_track_14\/FTB_15__41:A 0.152 +7 mux_tree_tapbuf_size3_1_sram[1]:12 mux_tree_tapbuf_size3_1_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size3_1_sram[1]:12 mux_tree_tapbuf_size3_1_sram[1]:7 0.001973214 +9 mux_tree_tapbuf_size3_1_sram[1]:11 mux_tree_tapbuf_size3_1_sram[1]:10 0.003866072 +10 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.0004263393 +11 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size3_1_sram[1]:8 mux_top_track_14\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_6_sram[0] 0.004444814 //LENGTH 32.910 LUMPCC 0.0005814458 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 85.250 31.960 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 72.405 28.220 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 77.640 40.120 +*I mux_top_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 79.480 34.295 +*N mux_tree_tapbuf_size3_6_sram[0]:4 *C 79.480 34.295 +*N mux_tree_tapbuf_size3_6_sram[0]:5 *C 77.603 40.120 +*N mux_tree_tapbuf_size3_6_sram[0]:6 *C 75.025 40.120 +*N mux_tree_tapbuf_size3_6_sram[0]:7 *C 74.980 40.075 +*N mux_tree_tapbuf_size3_6_sram[0]:8 *C 72.405 28.220 +*N mux_tree_tapbuf_size3_6_sram[0]:9 *C 74.475 28.220 +*N mux_tree_tapbuf_size3_6_sram[0]:10 *C 74.520 28.265 +*N mux_tree_tapbuf_size3_6_sram[0]:11 *C 74.520 34.340 +*N mux_tree_tapbuf_size3_6_sram[0]:12 *C 74.935 34.340 +*N mux_tree_tapbuf_size3_6_sram[0]:13 *C 74.950 34.030 +*N mux_tree_tapbuf_size3_6_sram[0]:14 *C 75.025 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:15 *C 79.443 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:16 *C 81.835 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:17 *C 81.880 33.955 +*N mux_tree_tapbuf_size3_6_sram[0]:18 *C 81.880 32.005 +*N mux_tree_tapbuf_size3_6_sram[0]:19 *C 81.925 31.960 +*N mux_tree_tapbuf_size3_6_sram[0]:20 *C 85.213 31.960 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_top_track_24\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size3_6_sram[0]:4 5.918759e-05 +5 mux_tree_tapbuf_size3_6_sram[0]:5 0.0002058278 +6 mux_tree_tapbuf_size3_6_sram[0]:6 0.0002058278 +7 mux_tree_tapbuf_size3_6_sram[0]:7 0.0002748321 +8 mux_tree_tapbuf_size3_6_sram[0]:8 0.0001950419 +9 mux_tree_tapbuf_size3_6_sram[0]:9 0.0001574959 +10 mux_tree_tapbuf_size3_6_sram[0]:10 0.0002191473 +11 mux_tree_tapbuf_size3_6_sram[0]:11 0.0002505387 +12 mux_tree_tapbuf_size3_6_sram[0]:12 0.0003425358 +13 mux_tree_tapbuf_size3_6_sram[0]:13 3.631231e-05 +14 mux_tree_tapbuf_size3_6_sram[0]:14 0.000373824 +15 mux_tree_tapbuf_size3_6_sram[0]:15 0.0006105264 +16 mux_tree_tapbuf_size3_6_sram[0]:16 0.0002064789 +17 mux_tree_tapbuf_size3_6_sram[0]:17 0.0001286799 +18 mux_tree_tapbuf_size3_6_sram[0]:18 0.0001286799 +19 mux_tree_tapbuf_size3_6_sram[0]:19 0.0002322161 +20 mux_tree_tapbuf_size3_6_sram[0]:20 0.0002322161 +21 mux_tree_tapbuf_size3_6_sram[0]:7 chanx_right_in[4]:23 5.617358e-05 +22 mux_tree_tapbuf_size3_6_sram[0]:10 chanx_right_in[4]:24 0.0001523437 +23 mux_tree_tapbuf_size3_6_sram[0]:13 chanx_right_in[4]:24 2.344489e-06 +24 mux_tree_tapbuf_size3_6_sram[0]:11 chanx_right_in[4]:23 0.0001523437 +25 mux_tree_tapbuf_size3_6_sram[0]:12 chanx_right_in[4]:23 2.344489e-06 +26 mux_tree_tapbuf_size3_6_sram[0]:12 chanx_right_in[4]:24 5.617358e-05 +27 mux_tree_tapbuf_size3_6_sram[0]:10 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 7.986114e-05 +28 mux_tree_tapbuf_size3_6_sram[0]:11 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 7.986114e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_6_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_6_sram[0]:5 mux_top_track_24\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_6_sram[0]:6 mux_tree_tapbuf_size3_6_sram[0]:5 0.00230134 +3 mux_tree_tapbuf_size3_6_sram[0]:7 mux_tree_tapbuf_size3_6_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size3_6_sram[0]:20 mux_tree_tapbuf_size3_6_sram[0]:19 0.002935268 +5 mux_tree_tapbuf_size3_6_sram[0]:19 mux_tree_tapbuf_size3_6_sram[0]:18 0.0045 +6 mux_tree_tapbuf_size3_6_sram[0]:18 mux_tree_tapbuf_size3_6_sram[0]:17 0.001741072 +7 mux_tree_tapbuf_size3_6_sram[0]:16 mux_tree_tapbuf_size3_6_sram[0]:15 0.002136161 +8 mux_tree_tapbuf_size3_6_sram[0]:17 mux_tree_tapbuf_size3_6_sram[0]:16 0.0045 +9 mux_tree_tapbuf_size3_6_sram[0]:8 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size3_6_sram[0]:9 mux_tree_tapbuf_size3_6_sram[0]:8 0.001848214 +11 mux_tree_tapbuf_size3_6_sram[0]:10 mux_tree_tapbuf_size3_6_sram[0]:9 0.0045 +12 mux_tree_tapbuf_size3_6_sram[0]:4 mux_top_track_24\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_6_sram[0]:14 mux_tree_tapbuf_size3_6_sram[0]:13 0.0045 +14 mux_tree_tapbuf_size3_6_sram[0]:13 mux_tree_tapbuf_size3_6_sram[0]:12 0.00019375 +15 mux_tree_tapbuf_size3_6_sram[0]:15 mux_tree_tapbuf_size3_6_sram[0]:14 0.003944197 +16 mux_tree_tapbuf_size3_6_sram[0]:15 mux_tree_tapbuf_size3_6_sram[0]:4 0.0001271552 +17 mux_tree_tapbuf_size3_6_sram[0]:11 mux_tree_tapbuf_size3_6_sram[0]:10 0.005424107 +18 mux_tree_tapbuf_size3_6_sram[0]:12 mux_tree_tapbuf_size3_6_sram[0]:11 0.0003705357 +19 mux_tree_tapbuf_size3_6_sram[0]:12 mux_tree_tapbuf_size3_6_sram[0]:7 0.005120536 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_1_ccff_tail[0] 0.0005501978 //LENGTH 4.060 LUMPCC 0.0001000057 DR + +*CONN +*I mem_top_track_10\/FTB_13__39:X O *L 0 *C 111.545 59.160 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 110.115 60.860 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 *C 110.153 60.860 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 *C 110.815 60.860 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 *C 110.860 60.815 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 *C 110.860 59.205 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 *C 110.905 59.160 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 *C 111.508 59.160 + +*CAP +0 mem_top_track_10\/FTB_13__39:X 1e-06 +1 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 7.41222e-05 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 7.41222e-05 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 8.053124e-05 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 8.053124e-05 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 6.944258e-05 +7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 6.944258e-05 +8 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size14_0_sram[1]:10 5.000287e-05 +9 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size14_0_sram[1]:11 5.000287e-05 + +*RES +0 mem_top_track_10\/FTB_13__39:X mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 0.0005379465 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.001112177 //LENGTH 8.880 LUMPCC 0.000136937 DR + +*CONN +*I mem_right_track_32\/FTB_31__57:X O *L 0 *C 75.665 80.240 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 70.095 82.620 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 70.133 82.620 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 71.715 82.620 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 71.760 82.575 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 71.760 80.285 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 71.805 80.240 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 75.627 80.240 + +*CAP +0 mem_right_track_32\/FTB_31__57:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0001432032 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0001432032 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001148477 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001148477 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0002285689 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.0002285689 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.684526e-05 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.684526e-05 +10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.162325e-05 +11 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.162325e-05 + +*RES +0 mem_right_track_32\/FTB_31__57:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.003412947 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[0] 0.007785957 //LENGTH 67.295 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 119.905 31.280 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 94.015 22.780 +*I mux_right_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 92.360 36.720 +*I mux_right_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 85.000 40.120 +*I mux_right_track_16\/mux_l1_in_2_:S I *L 0.00357 *C 102.020 28.855 +*I mux_right_track_16\/mux_l1_in_3_:S I *L 0.00357 *C 105.440 25.550 +*N mux_tree_tapbuf_size7_3_sram[0]:6 *C 105.440 25.550 +*N mux_tree_tapbuf_size7_3_sram[0]:7 *C 102.020 28.855 +*N mux_tree_tapbuf_size7_3_sram[0]:8 *C 85.000 40.120 +*N mux_tree_tapbuf_size7_3_sram[0]:9 *C 85.100 40.075 +*N mux_tree_tapbuf_size7_3_sram[0]:10 *C 85.100 37.445 +*N mux_tree_tapbuf_size7_3_sram[0]:11 *C 85.145 37.400 +*N mux_tree_tapbuf_size7_3_sram[0]:12 *C 92.360 36.720 +*N mux_tree_tapbuf_size7_3_sram[0]:13 *C 92.460 36.765 +*N mux_tree_tapbuf_size7_3_sram[0]:14 *C 92.460 37.355 +*N mux_tree_tapbuf_size7_3_sram[0]:15 *C 92.460 37.400 +*N mux_tree_tapbuf_size7_3_sram[0]:16 *C 96.095 37.400 +*N mux_tree_tapbuf_size7_3_sram[0]:17 *C 96.140 37.355 +*N mux_tree_tapbuf_size7_3_sram[0]:18 *C 94.053 22.780 +*N mux_tree_tapbuf_size7_3_sram[0]:19 *C 96.095 22.780 +*N mux_tree_tapbuf_size7_3_sram[0]:20 *C 96.140 22.825 +*N mux_tree_tapbuf_size7_3_sram[0]:21 *C 96.140 28.560 +*N mux_tree_tapbuf_size7_3_sram[0]:22 *C 96.185 28.560 +*N mux_tree_tapbuf_size7_3_sram[0]:23 *C 102.020 28.560 +*N mux_tree_tapbuf_size7_3_sram[0]:24 *C 105.295 28.560 +*N mux_tree_tapbuf_size7_3_sram[0]:25 *C 105.340 28.515 +*N mux_tree_tapbuf_size7_3_sram[0]:26 *C 105.340 25.885 +*N mux_tree_tapbuf_size7_3_sram[0]:27 *C 105.498 25.840 +*N mux_tree_tapbuf_size7_3_sram[0]:28 *C 118.635 25.840 +*N mux_tree_tapbuf_size7_3_sram[0]:29 *C 118.680 25.885 +*N mux_tree_tapbuf_size7_3_sram[0]:30 *C 118.680 31.235 +*N mux_tree_tapbuf_size7_3_sram[0]:31 *C 118.725 31.280 +*N mux_tree_tapbuf_size7_3_sram[0]:32 *C 119.868 31.280 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_16\/mux_l1_in_0_:S 1e-06 +4 mux_right_track_16\/mux_l1_in_2_:S 1e-06 +5 mux_right_track_16\/mux_l1_in_3_:S 1e-06 +6 mux_tree_tapbuf_size7_3_sram[0]:6 5.834533e-05 +7 mux_tree_tapbuf_size7_3_sram[0]:7 5.999524e-05 +8 mux_tree_tapbuf_size7_3_sram[0]:8 2.771624e-05 +9 mux_tree_tapbuf_size7_3_sram[0]:9 0.0001766964 +10 mux_tree_tapbuf_size7_3_sram[0]:10 0.0001766964 +11 mux_tree_tapbuf_size7_3_sram[0]:11 0.0005100926 +12 mux_tree_tapbuf_size7_3_sram[0]:12 2.841764e-05 +13 mux_tree_tapbuf_size7_3_sram[0]:13 5.519039e-05 +14 mux_tree_tapbuf_size7_3_sram[0]:14 5.519039e-05 +15 mux_tree_tapbuf_size7_3_sram[0]:15 0.0008165115 +16 mux_tree_tapbuf_size7_3_sram[0]:16 0.0002734229 +17 mux_tree_tapbuf_size7_3_sram[0]:17 0.0004620379 +18 mux_tree_tapbuf_size7_3_sram[0]:18 0.0001460594 +19 mux_tree_tapbuf_size7_3_sram[0]:19 0.0001460594 +20 mux_tree_tapbuf_size7_3_sram[0]:20 0.0002976655 +21 mux_tree_tapbuf_size7_3_sram[0]:21 0.0007911844 +22 mux_tree_tapbuf_size7_3_sram[0]:22 0.0003627876 +23 mux_tree_tapbuf_size7_3_sram[0]:23 0.0005909177 +24 mux_tree_tapbuf_size7_3_sram[0]:24 0.0001974942 +25 mux_tree_tapbuf_size7_3_sram[0]:25 0.0001530781 +26 mux_tree_tapbuf_size7_3_sram[0]:26 0.0001530781 +27 mux_tree_tapbuf_size7_3_sram[0]:27 0.0007263534 +28 mux_tree_tapbuf_size7_3_sram[0]:28 0.0006949818 +29 mux_tree_tapbuf_size7_3_sram[0]:29 0.0003250027 +30 mux_tree_tapbuf_size7_3_sram[0]:30 0.0003250027 +31 mux_tree_tapbuf_size7_3_sram[0]:31 8.498978e-05 +32 mux_tree_tapbuf_size7_3_sram[0]:32 8.498978e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_3_sram[0]:32 0.152 +1 mux_tree_tapbuf_size7_3_sram[0]:28 mux_tree_tapbuf_size7_3_sram[0]:27 0.01172991 +2 mux_tree_tapbuf_size7_3_sram[0]:29 mux_tree_tapbuf_size7_3_sram[0]:28 0.0045 +3 mux_tree_tapbuf_size7_3_sram[0]:31 mux_tree_tapbuf_size7_3_sram[0]:30 0.0045 +4 mux_tree_tapbuf_size7_3_sram[0]:30 mux_tree_tapbuf_size7_3_sram[0]:29 0.004776786 +5 mux_tree_tapbuf_size7_3_sram[0]:32 mux_tree_tapbuf_size7_3_sram[0]:31 0.001020089 +6 mux_tree_tapbuf_size7_3_sram[0]:16 mux_tree_tapbuf_size7_3_sram[0]:15 0.003245536 +7 mux_tree_tapbuf_size7_3_sram[0]:17 mux_tree_tapbuf_size7_3_sram[0]:16 0.0045 +8 mux_tree_tapbuf_size7_3_sram[0]:22 mux_tree_tapbuf_size7_3_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size7_3_sram[0]:21 mux_tree_tapbuf_size7_3_sram[0]:20 0.005120536 +10 mux_tree_tapbuf_size7_3_sram[0]:21 mux_tree_tapbuf_size7_3_sram[0]:17 0.007852679 +11 mux_tree_tapbuf_size7_3_sram[0]:6 mux_right_track_16\/mux_l1_in_3_:S 0.152 +12 mux_tree_tapbuf_size7_3_sram[0]:7 mux_right_track_16\/mux_l1_in_2_:S 0.152 +13 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:14 0.0045 +14 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:11 0.006531251 +15 mux_tree_tapbuf_size7_3_sram[0]:14 mux_tree_tapbuf_size7_3_sram[0]:13 0.0005267857 +16 mux_tree_tapbuf_size7_3_sram[0]:12 mux_right_track_16\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size7_3_sram[0]:13 mux_tree_tapbuf_size7_3_sram[0]:12 0.0045 +18 mux_tree_tapbuf_size7_3_sram[0]:11 mux_tree_tapbuf_size7_3_sram[0]:10 0.0045 +19 mux_tree_tapbuf_size7_3_sram[0]:10 mux_tree_tapbuf_size7_3_sram[0]:9 0.002348214 +20 mux_tree_tapbuf_size7_3_sram[0]:8 mux_right_track_16\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size7_3_sram[0]:9 mux_tree_tapbuf_size7_3_sram[0]:8 0.0045 +22 mux_tree_tapbuf_size7_3_sram[0]:19 mux_tree_tapbuf_size7_3_sram[0]:18 0.001823661 +23 mux_tree_tapbuf_size7_3_sram[0]:20 mux_tree_tapbuf_size7_3_sram[0]:19 0.0045 +24 mux_tree_tapbuf_size7_3_sram[0]:18 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +25 mux_tree_tapbuf_size7_3_sram[0]:27 mux_tree_tapbuf_size7_3_sram[0]:26 0.0045 +26 mux_tree_tapbuf_size7_3_sram[0]:27 mux_tree_tapbuf_size7_3_sram[0]:6 0.000125 +27 mux_tree_tapbuf_size7_3_sram[0]:26 mux_tree_tapbuf_size7_3_sram[0]:25 0.002348214 +28 mux_tree_tapbuf_size7_3_sram[0]:24 mux_tree_tapbuf_size7_3_sram[0]:23 0.002924107 +29 mux_tree_tapbuf_size7_3_sram[0]:25 mux_tree_tapbuf_size7_3_sram[0]:24 0.0045 +30 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:22 0.005209822 +31 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:7 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_4_ccff_tail[0] 0.002457618 //LENGTH 17.955 LUMPCC 0.0006529126 DR + +*CONN +*I mem_right_track_24\/FTB_9__35:X O *L 0 *C 100.975 72.080 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 87.115 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 *C 87.153 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 *C 94.255 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 *C 94.300 75.095 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 *C 94.300 72.138 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 *C 94.308 72.080 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 *C 100.733 72.080 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:8 *C 100.740 72.080 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:9 *C 100.740 72.080 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:10 *C 100.975 72.080 + +*CAP +0 mem_right_track_24\/FTB_9__35:X 1e-06 +1 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 0.0004042235 +3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 0.0004042235 +4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 0.0001829202 +5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 0.0001829202 +6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 0.0002345402 +7 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 0.0002345402 +8 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:8 3.742825e-05 +9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:9 6.227044e-05 +10 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:10 5.963878e-05 +11 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 prog_clk[0]:126 0.0001117121 +12 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 prog_clk[0]:128 6.751513e-06 +13 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 prog_clk[0]:127 0.0001117121 +14 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 prog_clk[0]:134 6.751513e-06 +15 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 chany_top_in[15]:8 7.100531e-05 +16 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 chany_top_in[15]:9 1.931847e-05 +17 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 chany_top_in[15]:9 7.100531e-05 +18 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 chany_top_in[15]:10 1.931847e-05 +19 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 optlc_net_122:26 5.077261e-06 +20 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 optlc_net_122:18 0.0001125916 +21 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 optlc_net_122:27 5.077261e-06 +22 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 optlc_net_122:19 0.0001125916 + +*RES +0 mem_right_track_24\/FTB_9__35:X mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:10 0.152 +1 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:10 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:9 0.0001277174 +2 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:8 0.0045 +3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:8 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 0.00341 +4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 0.001006583 +5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 0.002640625 +6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 0.00341 +7 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 0.006341518 +8 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 0.0045 +9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[1] 0.006754757 //LENGTH 52.535 LUMPCC 0.0002378751 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.485 77.520 +*I mux_left_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 24.020 66.980 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.195 71.740 +*I mux_left_track_3\/mux_l2_in_2_:S I *L 0.00357 *C 5.880 72.080 +*I mux_left_track_3\/mux_l2_in_3_:S I *L 0.00357 *C 10.020 72.375 +*I mux_left_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 26.780 72.080 +*N mux_tree_tapbuf_size8_2_sram[1]:6 *C 26.780 72.080 +*N mux_tree_tapbuf_size8_2_sram[1]:7 *C 10.020 72.375 +*N mux_tree_tapbuf_size8_2_sram[1]:8 *C 5.918 72.080 +*N mux_tree_tapbuf_size8_2_sram[1]:9 *C 10.020 72.080 +*N mux_tree_tapbuf_size8_2_sram[1]:10 *C 11.960 72.080 +*N mux_tree_tapbuf_size8_2_sram[1]:11 *C 11.960 71.740 +*N mux_tree_tapbuf_size8_2_sram[1]:12 *C 17.195 71.740 +*N mux_tree_tapbuf_size8_2_sram[1]:13 *C 18.860 71.740 +*N mux_tree_tapbuf_size8_2_sram[1]:14 *C 23.983 66.980 +*N mux_tree_tapbuf_size8_2_sram[1]:15 *C 18.905 66.980 +*N mux_tree_tapbuf_size8_2_sram[1]:16 *C 18.860 67.025 +*N mux_tree_tapbuf_size8_2_sram[1]:17 *C 18.860 71.355 +*N mux_tree_tapbuf_size8_2_sram[1]:18 *C 18.860 71.400 +*N mux_tree_tapbuf_size8_2_sram[1]:19 *C 26.680 71.400 +*N mux_tree_tapbuf_size8_2_sram[1]:20 *C 26.680 71.740 +*N mux_tree_tapbuf_size8_2_sram[1]:21 *C 38.595 71.740 +*N mux_tree_tapbuf_size8_2_sram[1]:22 *C 38.640 71.785 +*N mux_tree_tapbuf_size8_2_sram[1]:23 *C 38.640 77.475 +*N mux_tree_tapbuf_size8_2_sram[1]:24 *C 38.640 77.520 +*N mux_tree_tapbuf_size8_2_sram[1]:25 *C 38.485 77.520 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_3\/mux_l2_in_2_:S 1e-06 +4 mux_left_track_3\/mux_l2_in_3_:S 1e-06 +5 mux_left_track_3\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_2_sram[1]:6 4.533615e-05 +7 mux_tree_tapbuf_size8_2_sram[1]:7 5.588855e-05 +8 mux_tree_tapbuf_size8_2_sram[1]:8 0.0002612922 +9 mux_tree_tapbuf_size8_2_sram[1]:9 0.0004104873 +10 mux_tree_tapbuf_size8_2_sram[1]:10 0.0001450941 +11 mux_tree_tapbuf_size8_2_sram[1]:11 0.0003433604 +12 mux_tree_tapbuf_size8_2_sram[1]:12 0.000464934 +13 mux_tree_tapbuf_size8_2_sram[1]:13 0.0001511443 +14 mux_tree_tapbuf_size8_2_sram[1]:14 0.0003351903 +15 mux_tree_tapbuf_size8_2_sram[1]:15 0.0003351903 +16 mux_tree_tapbuf_size8_2_sram[1]:16 0.0002710488 +17 mux_tree_tapbuf_size8_2_sram[1]:17 0.0002710488 +18 mux_tree_tapbuf_size8_2_sram[1]:18 0.0005726788 +19 mux_tree_tapbuf_size8_2_sram[1]:19 0.0005654163 +20 mux_tree_tapbuf_size8_2_sram[1]:20 0.0007697397 +21 mux_tree_tapbuf_size8_2_sram[1]:21 0.0007278225 +22 mux_tree_tapbuf_size8_2_sram[1]:22 0.0003348083 +23 mux_tree_tapbuf_size8_2_sram[1]:23 0.0003348083 +24 mux_tree_tapbuf_size8_2_sram[1]:24 6.004849e-05 +25 mux_tree_tapbuf_size8_2_sram[1]:25 5.554477e-05 +26 mux_tree_tapbuf_size8_2_sram[1]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.200548e-05 +27 mux_tree_tapbuf_size8_2_sram[1]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.451045e-05 +28 mux_tree_tapbuf_size8_2_sram[1]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.451045e-05 +29 mux_tree_tapbuf_size8_2_sram[1]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.200548e-05 +30 mux_tree_tapbuf_size8_2_sram[1]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.242162e-05 +31 mux_tree_tapbuf_size8_2_sram[1]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.242162e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_2_sram[1]:25 0.152 +1 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:20 0.01063839 +2 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:21 0.0045 +3 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:23 0.0045 +4 mux_tree_tapbuf_size8_2_sram[1]:23 mux_tree_tapbuf_size8_2_sram[1]:22 0.005080357 +5 mux_tree_tapbuf_size8_2_sram[1]:25 mux_tree_tapbuf_size8_2_sram[1]:24 8.423914e-05 +6 mux_tree_tapbuf_size8_2_sram[1]:8 mux_left_track_3\/mux_l2_in_2_:S 0.152 +7 mux_tree_tapbuf_size8_2_sram[1]:12 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:11 0.004674107 +9 mux_tree_tapbuf_size8_2_sram[1]:7 mux_left_track_3\/mux_l2_in_3_:S 0.152 +10 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:17 0.0045 +11 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:13 0.0003035714 +12 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:16 0.003866072 +13 mux_tree_tapbuf_size8_2_sram[1]:15 mux_tree_tapbuf_size8_2_sram[1]:14 0.004533482 +14 mux_tree_tapbuf_size8_2_sram[1]:16 mux_tree_tapbuf_size8_2_sram[1]:15 0.0045 +15 mux_tree_tapbuf_size8_2_sram[1]:14 mux_left_track_3\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size8_2_sram[1]:6 mux_left_track_3\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size8_2_sram[1]:9 mux_tree_tapbuf_size8_2_sram[1]:8 0.003662947 +18 mux_tree_tapbuf_size8_2_sram[1]:9 mux_tree_tapbuf_size8_2_sram[1]:7 0.0001271552 +19 mux_tree_tapbuf_size8_2_sram[1]:10 mux_tree_tapbuf_size8_2_sram[1]:9 0.001732143 +20 mux_tree_tapbuf_size8_2_sram[1]:11 mux_tree_tapbuf_size8_2_sram[1]:10 0.0003035715 +21 mux_tree_tapbuf_size8_2_sram[1]:13 mux_tree_tapbuf_size8_2_sram[1]:12 0.001486607 +22 mux_tree_tapbuf_size8_2_sram[1]:19 mux_tree_tapbuf_size8_2_sram[1]:18 0.006982143 +23 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:19 0.0003035714 +24 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:6 0.0003035715 + +*END + +*D_NET optlc_net_121 0.00434456 //LENGTH 33.010 LUMPCC 0.001329177 DR + +*CONN +*I optlc_112:HI O *L 0 *C 33.580 42.160 +*I mux_left_track_17\/mux_l1_in_3_:A0 I *L 0.001631 *C 33.295 37.060 +*I mux_left_track_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 18.575 31.960 +*I mux_left_track_25\/mux_l1_in_3_:A0 I *L 0.001631 *C 32.835 47.940 +*N optlc_net_121:4 *C 32.835 47.940 +*N optlc_net_121:5 *C 33.120 47.940 +*N optlc_net_121:6 *C 33.120 47.895 +*N optlc_net_121:7 *C 18.575 31.960 +*N optlc_net_121:8 *C 18.400 31.960 +*N optlc_net_121:9 *C 18.400 31.960 +*N optlc_net_121:10 *C 18.408 31.960 +*N optlc_net_121:11 *C 33.113 31.960 +*N optlc_net_121:12 *C 33.120 32.017 +*N optlc_net_121:13 *C 33.295 37.060 +*N optlc_net_121:14 *C 33.120 37.060 +*N optlc_net_121:15 *C 33.120 37.060 +*N optlc_net_121:16 *C 33.120 42.160 +*N optlc_net_121:17 *C 33.165 42.160 +*N optlc_net_121:18 *C 33.543 42.160 + +*CAP +0 optlc_112:HI 1e-06 +1 mux_left_track_17\/mux_l1_in_3_:A0 1e-06 +2 mux_left_track_9\/mux_l2_in_3_:A0 1e-06 +3 mux_left_track_25\/mux_l1_in_3_:A0 1e-06 +4 optlc_net_121:4 4.831946e-05 +5 optlc_net_121:5 5.372332e-05 +6 optlc_net_121:6 0.000305473 +7 optlc_net_121:7 5.229638e-05 +8 optlc_net_121:8 5.643097e-05 +9 optlc_net_121:9 3.999792e-05 +10 optlc_net_121:10 0.000507511 +11 optlc_net_121:11 0.000507511 +12 optlc_net_121:12 0.0002688561 +13 optlc_net_121:13 4.849943e-05 +14 optlc_net_121:14 5.398381e-05 +15 optlc_net_121:15 0.0004687215 +16 optlc_net_121:16 0.0005062135 +17 optlc_net_121:17 4.692317e-05 +18 optlc_net_121:18 4.692317e-05 +19 optlc_net_121:11 chanx_right_in[8]:12 0.0003750468 +20 optlc_net_121:10 chanx_right_in[8]:11 0.0003750468 +21 optlc_net_121:6 prog_clk[0]:479 4.1245e-05 +22 optlc_net_121:15 prog_clk[0]:464 0.0001363058 +23 optlc_net_121:15 prog_clk[0]:478 4.954493e-05 +24 optlc_net_121:16 prog_clk[0]:478 0.0001775508 +25 optlc_net_121:12 prog_clk[0]:464 4.954493e-05 +26 optlc_net_121:11 prog_clk[0]:441 2.83082e-06 +27 optlc_net_121:11 prog_clk[0]:457 3.848214e-06 +28 optlc_net_121:11 prog_clk[0]:462 2.300967e-05 +29 optlc_net_121:11 prog_clk[0]:463 3.275689e-05 +30 optlc_net_121:10 prog_clk[0]:452 3.848214e-06 +31 optlc_net_121:10 prog_clk[0]:457 2.300967e-05 +32 optlc_net_121:10 prog_clk[0]:462 3.275689e-05 +33 optlc_net_121:10 prog_clk[0]:463 2.83082e-06 + +*RES +0 optlc_112:HI optlc_net_121:18 0.152 +1 optlc_net_121:5 optlc_net_121:4 0.0001548913 +2 optlc_net_121:6 optlc_net_121:5 0.0045 +3 optlc_net_121:4 mux_left_track_25\/mux_l1_in_3_:A0 0.152 +4 optlc_net_121:14 optlc_net_121:13 9.51087e-05 +5 optlc_net_121:15 optlc_net_121:14 0.0045 +6 optlc_net_121:15 optlc_net_121:12 0.004502232 +7 optlc_net_121:13 mux_left_track_17\/mux_l1_in_3_:A0 0.152 +8 optlc_net_121:17 optlc_net_121:16 0.0045 +9 optlc_net_121:16 optlc_net_121:15 0.004553572 +10 optlc_net_121:16 optlc_net_121:6 0.005120536 +11 optlc_net_121:18 optlc_net_121:17 0.0003370536 +12 optlc_net_121:12 optlc_net_121:11 0.00341 +13 optlc_net_121:11 optlc_net_121:10 0.002303783 +14 optlc_net_121:9 optlc_net_121:8 0.0045 +15 optlc_net_121:10 optlc_net_121:9 0.00341 +16 optlc_net_121:8 optlc_net_121:7 9.51087e-05 +17 optlc_net_121:7 mux_left_track_9\/mux_l2_in_3_:A0 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00181284 //LENGTH 12.290 LUMPCC 0.0007492348 DR + +*CONN +*I mux_left_track_3\/mux_l4_in_0_:X O *L 0 *C 12.135 64.600 +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.345 69.490 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 5.345 69.490 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 5.520 69.360 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 5.520 69.315 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 5.520 64.645 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 5.565 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 12.098 64.600 + +*CAP +0 mux_left_track_3\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.097829e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.646155e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001536582 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001536582 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0003234247 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0003234247 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chanx_right_in[4]:8 5.292358e-07 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[4]:6 0.000124895 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_right_in[4]:7 5.292358e-07 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_right_in[4]:5 0.000124895 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 left_top_grid_pin_45_[0]:13 0.0001328861 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 left_top_grid_pin_45_[0]:11 0.0001328861 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 ropt_net_153:4 6.123457e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 ropt_net_153:6 3.517209e-07 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 ropt_net_153:5 5.472069e-05 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_153:7 3.517209e-07 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_153:5 6.123457e-05 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 ropt_net_153:6 5.472069e-05 + +*RES +0 mux_left_track_3\/mux_l4_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 9.51087e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004169643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00583259 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000573168 //LENGTH 3.400 LUMPCC 0.0003519018 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_1_:X O *L 0 *C 70.205 53.380 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 73.315 53.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 73.278 53.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 70.243 53.380 + +*CAP +0 mux_top_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001096331 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001096331 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_top_in[9]:3 0.0001244449 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[9]:5 0.0001244449 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_1_sram[1]:11 5.150598e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_1_sram[1]:12 5.150598e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002709822 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009154647 //LENGTH 6.885 LUMPCC 9.605227e-05 DR + +*CONN +*I mux_top_track_6\/mux_l2_in_1_:X O *L 0 *C 86.655 45.220 +*I mux_top_track_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 88.150 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 88.112 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 86.985 49.980 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 86.940 49.935 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 86.940 45.265 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 86.940 45.220 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 86.655 45.220 + +*CAP +0 mux_top_track_6\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_6\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.109852e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.109852e-05 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002561467 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002561467 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.26055e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.031655e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:21 4.802614e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:16 4.802614e-05 + +*RES +0 mux_top_track_6\/mux_l2_in_1_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_6\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001006696 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009754604 //LENGTH 6.890 LUMPCC 0.0004049362 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_1_:X O *L 0 *C 90.795 63.580 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 89.415 59.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 89.415 59.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 89.240 59.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 89.240 59.205 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 89.240 63.535 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 89.285 63.580 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 90.758 63.580 + +*CAP +0 mux_right_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.715353e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.806252e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002002106 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002002106 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.644352e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.644352e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[18]:17 6.823608e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[18]:16 6.823608e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_4_sram[0]:9 5.458887e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_4_sram[0]:13 9.311476e-08 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_4_sram[0]:8 5.458887e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_4_sram[0]:14 9.311476e-08 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_4_sram[1]:11 1.829432e-06 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_4_sram[1]:12 1.829432e-06 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_4_sram[1]:8 5.19187e-05 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_4_sram[1]:13 2.580189e-05 +18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_4_sram[1]:7 5.19187e-05 +19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_4_sram[1]:14 2.580189e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001246994 //LENGTH 8.330 LUMPCC 0.0005242927 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 112.415 42.500 +*I mux_top_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 107.545 45.220 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 107.583 45.220 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 112.195 45.220 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 112.240 45.175 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 112.240 42.545 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 112.240 42.500 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 112.415 42.500 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001903305 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001903305 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001174406 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001174406 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.348829e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.16705e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[14]:12 7.688989e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[14]:13 7.688989e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_0_sram[2]:4 0.0001852565 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_0_sram[2]:5 0.0001852565 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004118304 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005540603 //LENGTH 3.780 LUMPCC 0.0002242849 DR + +*CONN +*I mux_top_track_14\/mux_l1_in_0_:X O *L 0 *C 53.075 63.580 +*I mux_top_track_14\/mux_l2_in_0_:A1 I *L 0.00198 *C 49.585 63.580 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 49.623 63.580 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.038 63.580 + +*CAP +0 mux_top_track_14\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_14\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001638877 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001638877 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[12]:18 0.0001121425 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[12]:19 0.0001121425 + +*RES +0 mux_top_track_14\/mux_l1_in_0_:X mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_14\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003049107 + +*END + +*D_NET mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008385432 //LENGTH 6.430 LUMPCC 0.0002692705 DR + +*CONN +*I mux_top_track_18\/mux_l1_in_1_:X O *L 0 *C 60.435 40.120 +*I mux_top_track_18\/mux_l2_in_0_:A0 I *L 0.001631 *C 61.815 44.540 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 61.778 44.540 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 60.765 44.540 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 60.720 44.495 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 60.720 40.165 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 60.720 40.120 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 60.435 40.120 + +*CAP +0 mux_top_track_18\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_18\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.37409e-05 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.37409e-05 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001594768 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001594768 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.166835e-05 +7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.916896e-05 +8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_36_[0]:10 6.065393e-05 +9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_36_[0]:9 6.065393e-05 +10 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_3_sram[0]:7 4.066059e-05 +11 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:8 4.066059e-05 +12 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_3_sram[0]:9 1.412072e-05 +13 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_3_sram[0]:16 1.920001e-05 +14 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:15 1.920001e-05 +15 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:16 1.412072e-05 + +*RES +0 mux_top_track_18\/mux_l1_in_1_:X mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_18\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009040179 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000391355 //LENGTH 2.960 LUMPCC 0 DR + +*CONN +*I mux_top_track_38\/mux_l1_in_0_:X O *L 0 *C 83.085 83.640 +*I mux_top_track_38\/mux_l2_in_0_:A1 I *L 0.00198 *C 83.625 85.340 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 83.625 85.340 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 83.720 85.295 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 83.720 83.685 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 83.675 83.640 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 83.123 83.640 + +*CAP +0 mux_top_track_38\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_38\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.036895e-05 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001141487 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001141487 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.534427e-05 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.534427e-05 + +*RES +0 mux_top_track_38\/mux_l1_in_0_:X mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_38\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0014375 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004933036 + +*END + +*D_NET mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00176109 //LENGTH 14.565 LUMPCC 0.0001116134 DR + +*CONN +*I mux_top_track_34\/mux_l2_in_0_:X O *L 0 *C 47.205 97.240 +*I mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 58.595 99.095 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.595 99.095 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 53.360 99.280 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 53.360 98.940 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 48.345 98.940 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 48.300 98.895 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 48.300 97.285 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 48.255 97.240 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 47.242 97.240 + +*CAP +0 mux_top_track_34\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003023987 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002880056 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003366102 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003113442 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001041194 +7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001041194 +8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001004399 +9 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001004399 +10 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 ropt_net_140:7 5.58067e-05 +11 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 ropt_net_140:8 5.58067e-05 + +*RES +0 mux_top_track_34\/mux_l2_in_0_:X mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004477679 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0014375 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0009040179 +7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003035715 +8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004674108 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003062183 //LENGTH 2.205 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_2_:X O *L 0 *C 130.355 63.580 +*I mux_right_track_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 128.440 63.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 128.477 63.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 130.317 63.580 + +*CAP +0 mux_right_track_0\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001521091 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001521091 + +*RES +0 mux_right_track_0\/mux_l2_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_0\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001642857 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004596571 //LENGTH 2.865 LUMPCC 0.0002015652 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_2_:X O *L 0 *C 93.205 79.900 +*I mux_right_track_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 95.780 79.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 95.743 79.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 93.243 79.900 + +*CAP +0 mux_right_track_2\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001280459 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001280459 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size9_0_sram[0]:5 5.150474e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size9_0_sram[0]:17 1.506243e-06 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size9_0_sram[0]:4 5.150474e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size9_0_sram[0]:18 1.506243e-06 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size9_1_sram[2]:12 4.777165e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size9_1_sram[2]:13 4.777165e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_2_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_2\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002232143 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001374488 //LENGTH 10.560 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_1_:X O *L 0 *C 97.345 80.240 +*I mux_right_track_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 104.595 82.620 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 104.558 82.620 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 100.325 82.620 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 100.280 82.575 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 100.280 80.285 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 100.235 80.240 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 97.383 80.240 + +*CAP +0 mux_right_track_2\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003128541 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003128541 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001695152 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001695152 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002038749 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002038749 + +*RES +0 mux_right_track_2\/mux_l3_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_2\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.003779018 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002044643 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002546875 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001016548 //LENGTH 7.505 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_2_:X O *L 0 *C 109.195 63.240 +*I mux_right_track_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 107.740 58.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 107.740 58.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 107.640 58.480 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 108.975 58.480 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 109.020 58.525 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 109.020 63.195 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 109.020 63.240 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 109.195 63.240 + +*CAP +0 mux_right_track_4\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.910111e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001401105 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001113105 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002899494 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002899494 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.348942e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.063756e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_4\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.001191964 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.004169643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 9.510869e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000684674 //LENGTH 4.610 LUMPCC 0.0002830789 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_5_:X O *L 0 *C 15.355 53.040 +*I mux_left_track_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 14.550 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 14.550 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 14.720 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 14.720 50.025 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 14.720 52.995 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 14.765 53.040 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 15.318 53.040 + +*CAP +0 mux_left_track_5\/mux_l1_in_5_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_2_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.563726e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.998179e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001082828 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001082828 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.370525e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 3.370525e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 prog_clk[0]:530 3.784501e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 prog_clk[0]:536 3.784501e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 left_top_grid_pin_47_[0]:16 3.455209e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 left_top_grid_pin_47_[0]:15 3.455209e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.914238e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.914238e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_5_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5\/mux_l2_in_2_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.239131e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002651786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005458258 //LENGTH 4.210 LUMPCC 0 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_2_:X O *L 0 *C 14.545 60.520 +*I mux_left_track_33\/mux_l2_in_1_:A1 I *L 0.00198 *C 13.245 58.140 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 13.245 58.140 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 13.340 58.185 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 13.340 60.475 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 13.385 60.520 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 14.508 60.520 + +*CAP +0 mux_left_track_33\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.894443e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001540227 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001540227 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001034179 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001034179 + +*RES +0 mux_left_track_33\/mux_l1_in_2_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_33\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002044643 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001002232 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001372341 //LENGTH 10.490 LUMPCC 0.0001080775 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_0_:X O *L 0 *C 35.595 65.960 +*I mux_left_track_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 30.265 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 30.303 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 35.375 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 35.420 61.585 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 35.420 65.915 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 35.420 65.960 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 35.595 65.960 + +*CAP +0 mux_left_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.000304829 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000304829 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002708947 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002708947 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.628337e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.453282e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_0_sram[3]:5 5.398215e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_0_sram[3]:6 5.398215e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:7 5.660139e-08 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[3]:8 5.660139e-08 + +*RES +0 mux_left_track_1\/mux_l3_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_1\/mux_l4_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.004529018 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.003866072 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 + +*END + +*D_NET ccff_tail[0] 0.0005403008 //LENGTH 4.420 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 4.140 56.440 +*P ccff_tail[0] O *L 0.7423 *C 1.298 55.760 +*N ccff_tail[0]:2 *C 1.380 55.760 +*N ccff_tail[0]:3 *C 1.380 55.818 +*N ccff_tail[0]:4 *C 1.380 56.395 +*N ccff_tail[0]:5 *C 1.425 56.440 +*N ccff_tail[0]:6 *C 4.103 56.440 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 ccff_tail[0] 2.89557e-05 +2 ccff_tail[0]:2 2.89557e-05 +3 ccff_tail[0]:3 5.167093e-05 +4 ccff_tail[0]:4 5.167093e-05 +5 ccff_tail[0]:5 0.0001890238 +6 ccff_tail[0]:6 0.0001890238 + +*RES +0 ropt_mt_inst_754:X ccff_tail[0]:6 0.152 +1 ccff_tail[0]:6 ccff_tail[0]:5 0.002390625 +2 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +3 ccff_tail[0]:4 ccff_tail[0]:3 0.000515625 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 + +*END + +*D_NET ropt_net_173 0.001615267 //LENGTH 11.580 LUMPCC 0.0001059093 DR + +*CONN +*I FTB_22__21:X O *L 0 *C 131.100 61.540 +*I ropt_mt_inst_802:A I *L 0.001766 *C 134.780 66.640 +*N ropt_net_173:2 *C 134.817 66.640 +*N ropt_net_173:3 *C 135.655 66.640 +*N ropt_net_173:4 *C 135.700 66.595 +*N ropt_net_173:5 *C 135.700 61.938 +*N ropt_net_173:6 *C 135.692 61.880 +*N ropt_net_173:7 *C 131.108 61.880 +*N ropt_net_173:8 *C 131.100 61.880 +*N ropt_net_173:9 *C 131.100 61.540 +*N ropt_net_173:10 *C 131.100 61.540 + +*CAP +0 FTB_22__21:X 1e-06 +1 ropt_mt_inst_802:A 1e-06 +2 ropt_net_173:2 6.962312e-05 +3 ropt_net_173:3 6.962312e-05 +4 ropt_net_173:4 0.0002720223 +5 ropt_net_173:5 0.0002720223 +6 ropt_net_173:6 0.0003451952 +7 ropt_net_173:7 0.0003451952 +8 ropt_net_173:8 5.144175e-05 +9 ropt_net_173:9 4.738239e-05 +10 ropt_net_173:10 3.485277e-05 +11 ropt_net_173:6 right_bottom_grid_pin_1_[0]:12 4.268513e-05 +12 ropt_net_173:8 right_bottom_grid_pin_1_[0]:15 1.026951e-05 +13 ropt_net_173:7 right_bottom_grid_pin_1_[0]:11 4.268513e-05 +14 ropt_net_173:9 right_bottom_grid_pin_1_[0]:13 1.026951e-05 + +*RES +0 FTB_22__21:X ropt_net_173:10 0.152 +1 ropt_net_173:2 ropt_mt_inst_802:A 0.152 +2 ropt_net_173:3 ropt_net_173:2 0.0007477679 +3 ropt_net_173:4 ropt_net_173:3 0.0045 +4 ropt_net_173:5 ropt_net_173:4 0.004158482 +5 ropt_net_173:6 ropt_net_173:5 0.00341 +6 ropt_net_173:8 ropt_net_173:7 0.00341 +7 ropt_net_173:7 ropt_net_173:6 0.0007183166 +8 ropt_net_173:10 ropt_net_173:9 0.0045 +9 ropt_net_173:9 ropt_net_173:8 0.0001634615 + +*END + +*D_NET chanx_left_out[14] 0.0006886965 //LENGTH 5.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 4.140 19.720 +*P chanx_left_out[14] O *L 0.7423 *C 1.305 17.680 +*N chanx_left_out[14]:2 *C 3.213 17.680 +*N chanx_left_out[14]:3 *C 3.220 17.738 +*N chanx_left_out[14]:4 *C 3.220 19.675 +*N chanx_left_out[14]:5 *C 3.265 19.720 +*N chanx_left_out[14]:6 *C 4.103 19.720 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 chanx_left_out[14] 0.0001421337 +2 chanx_left_out[14]:2 0.0001421337 +3 chanx_left_out[14]:3 0.0001245158 +4 chanx_left_out[14]:4 0.0001245158 +5 chanx_left_out[14]:5 7.719875e-05 +6 chanx_left_out[14]:6 7.719875e-05 + +*RES +0 ropt_mt_inst_784:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +2 chanx_left_out[14]:2 chanx_left_out[14] 0.0002988417 +3 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +4 chanx_left_out[14]:4 chanx_left_out[14]:3 0.001729911 +5 chanx_left_out[14]:6 chanx_left_out[14]:5 0.0007477679 + +*END + +*D_NET ropt_net_171 0.001239705 //LENGTH 9.475 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 138.575 59.160 +*I ropt_mt_inst_798:A I *L 0.001767 *C 130.180 58.480 +*N ropt_net_171:2 *C 130.180 58.480 +*N ropt_net_171:3 *C 130.180 59.160 +*N ropt_net_171:4 *C 138.537 59.160 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 ropt_mt_inst_798:A 1e-06 +2 ropt_net_171:2 8.647332e-05 +3 ropt_net_171:3 0.0006018826 +4 ropt_net_171:4 0.0005493488 + +*RES +0 ropt_mt_inst_769:X ropt_net_171:4 0.152 +1 ropt_net_171:4 ropt_net_171:3 0.007462054 +2 ropt_net_171:2 ropt_mt_inst_798:A 0.152 +3 ropt_net_171:3 ropt_net_171:2 0.0006071429 + +*END + +*D_NET chanx_right_out[19] 0.001193457 //LENGTH 8.245 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 135.700 56.100 +*P chanx_right_out[19] O *L 0.7423 *C 140.375 53.040 +*N chanx_right_out[19]:2 *C 135.708 53.040 +*N chanx_right_out[19]:3 *C 135.700 53.098 +*N chanx_right_out[19]:4 *C 135.700 56.055 +*N chanx_right_out[19]:5 *C 135.700 56.100 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 chanx_right_out[19] 0.0003701246 +2 chanx_right_out[19]:2 0.0003701246 +3 chanx_right_out[19]:3 0.0002097084 +4 chanx_right_out[19]:4 0.0002097084 +5 chanx_right_out[19]:5 3.279061e-05 + +*RES +0 ropt_mt_inst_794:X chanx_right_out[19]:5 0.152 +1 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +2 chanx_right_out[19]:2 chanx_right_out[19] 0.0007312415 +3 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0045 +4 chanx_right_out[19]:4 chanx_right_out[19]:3 0.002640625 + +*END + +*D_NET mem_left_track_33/net_net_98 0.001271328 //LENGTH 10.285 LUMPCC 0.0001443282 DR + +*CONN +*I mem_left_track_33\/FTB_32__58:X O *L 0 *C 5.205 52.700 +*I mem_left_track_33\/BUFT_RR_98:A I *L 0.001766 *C 11.500 55.760 +*N mem_left_track_33/net_net_98:2 *C 11.463 55.760 +*N mem_left_track_33/net_net_98:3 *C 6.025 55.760 +*N mem_left_track_33/net_net_98:4 *C 5.980 55.715 +*N mem_left_track_33/net_net_98:5 *C 5.980 52.745 +*N mem_left_track_33/net_net_98:6 *C 5.935 52.700 +*N mem_left_track_33/net_net_98:7 *C 5.243 52.700 + +*CAP +0 mem_left_track_33\/FTB_32__58:X 1e-06 +1 mem_left_track_33\/BUFT_RR_98:A 1e-06 +2 mem_left_track_33/net_net_98:2 0.000315622 +3 mem_left_track_33/net_net_98:3 0.000315622 +4 mem_left_track_33/net_net_98:4 0.0001803576 +5 mem_left_track_33/net_net_98:5 0.0001803576 +6 mem_left_track_33/net_net_98:6 6.65205e-05 +7 mem_left_track_33/net_net_98:7 6.65205e-05 +8 mem_left_track_33/net_net_98:2 ropt_net_131:5 7.21641e-05 +9 mem_left_track_33/net_net_98:3 ropt_net_131:4 7.21641e-05 + +*RES +0 mem_left_track_33\/FTB_32__58:X mem_left_track_33/net_net_98:7 0.152 +1 mem_left_track_33/net_net_98:2 mem_left_track_33\/BUFT_RR_98:A 0.152 +2 mem_left_track_33/net_net_98:3 mem_left_track_33/net_net_98:2 0.004854911 +3 mem_left_track_33/net_net_98:4 mem_left_track_33/net_net_98:3 0.0045 +4 mem_left_track_33/net_net_98:6 mem_left_track_33/net_net_98:5 0.0045 +5 mem_left_track_33/net_net_98:5 mem_left_track_33/net_net_98:4 0.002651786 +6 mem_left_track_33/net_net_98:7 mem_left_track_33/net_net_98:6 0.0006183035 + +*END + +*D_NET chanx_right_in[10] 0.02711647 //LENGTH 194.270 LUMPCC 0.00591128 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 140.375 25.840 +*I mux_top_track_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 67.795 59.160 +*I mux_left_track_33\/mux_l1_in_1_:A0 I *L 0.001631 *C 45.830 60.520 +*I ropt_mt_inst_753:A I *L 0.001766 *C 7.820 39.440 +*N chanx_right_in[10]:4 *C 71.360 55.080 +*N chanx_right_in[10]:5 *C 7.858 39.440 +*N chanx_right_in[10]:6 *C 11.040 39.440 +*N chanx_right_in[10]:7 *C 11.040 40.120 +*N chanx_right_in[10]:8 *C 25.180 40.120 +*N chanx_right_in[10]:9 *C 25.293 40.075 +*N chanx_right_in[10]:10 *C 25.300 39.485 +*N chanx_right_in[10]:11 *C 25.345 39.440 +*N chanx_right_in[10]:12 *C 26.220 39.440 +*N chanx_right_in[10]:13 *C 26.220 39.780 +*N chanx_right_in[10]:14 *C 45.495 39.780 +*N chanx_right_in[10]:15 *C 45.540 39.825 +*N chanx_right_in[10]:16 *C 45.540 60.475 +*N chanx_right_in[10]:17 *C 45.540 60.520 +*N chanx_right_in[10]:18 *C 45.867 60.520 +*N chanx_right_in[10]:19 *C 67.575 60.520 +*N chanx_right_in[10]:20 *C 67.620 60.475 +*N chanx_right_in[10]:21 *C 67.795 59.160 +*N chanx_right_in[10]:22 *C 67.620 59.160 +*N chanx_right_in[10]:23 *C 67.620 59.160 +*N chanx_right_in[10]:24 *C 67.620 55.125 +*N chanx_right_in[10]:25 *C 67.665 55.080 +*N chanx_right_in[10]:26 *C 71.715 55.080 +*N chanx_right_in[10]:27 *C 71.760 55.080 +*N chanx_right_in[10]:28 *C 71.760 55.080 +*N chanx_right_in[10]:29 *C 71.760 55.073 +*N chanx_right_in[10]:30 *C 71.760 26.527 +*N chanx_right_in[10]:31 *C 71.780 26.520 +*N chanx_right_in[10]:32 *C 121.570 26.520 +*N chanx_right_in[10]:33 *C 140.300 26.520 + +*CAP +0 chanx_right_in[10] 4.763326e-05 +1 mux_top_track_12\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_33\/mux_l1_in_1_:A0 1e-06 +3 ropt_mt_inst_753:A 1e-06 +4 chanx_right_in[10]:4 8.43298e-05 +5 chanx_right_in[10]:5 0.0002504762 +6 chanx_right_in[10]:6 0.0002916235 +7 chanx_right_in[10]:7 0.0009570134 +8 chanx_right_in[10]:8 0.0009158662 +9 chanx_right_in[10]:9 4.849348e-05 +10 chanx_right_in[10]:10 4.849348e-05 +11 chanx_right_in[10]:11 5.699762e-05 +12 chanx_right_in[10]:12 7.966999e-05 +13 chanx_right_in[10]:13 0.001138182 +14 chanx_right_in[10]:14 0.001115509 +15 chanx_right_in[10]:15 0.00118117 +16 chanx_right_in[10]:16 0.00118117 +17 chanx_right_in[10]:17 5.425783e-05 +18 chanx_right_in[10]:18 0.001387648 +19 chanx_right_in[10]:19 0.001366832 +20 chanx_right_in[10]:20 8.696871e-05 +21 chanx_right_in[10]:21 5.330478e-05 +22 chanx_right_in[10]:22 5.769472e-05 +23 chanx_right_in[10]:23 0.0003830919 +24 chanx_right_in[10]:24 0.0002626387 +25 chanx_right_in[10]:25 0.0003514872 +26 chanx_right_in[10]:26 0.0003514872 +27 chanx_right_in[10]:27 3.732971e-05 +28 chanx_right_in[10]:28 8.43298e-05 +29 chanx_right_in[10]:29 0.002423041 +30 chanx_right_in[10]:30 0.002423041 +31 chanx_right_in[10]:31 0.00134427 +32 chanx_right_in[10]:32 0.002217387 +33 chanx_right_in[10]:33 0.0009207506 +34 chanx_right_in[10]:31 chanx_right_in[12]:27 6.378053e-05 +35 chanx_right_in[10]:31 chanx_right_in[12]:28 0.0001124784 +36 chanx_right_in[10]:33 chanx_right_in[12]:29 8.062069e-05 +37 chanx_right_in[10]:32 chanx_right_in[12]:29 0.0001124784 +38 chanx_right_in[10]:32 chanx_right_in[12]:28 0.0001444012 +39 chanx_right_in[10]:31 prog_clk[0]:396 0.0005234542 +40 chanx_right_in[10]:31 prog_clk[0]:395 0.0004645338 +41 chanx_right_in[10]:31 prog_clk[0]:391 0.0001135885 +42 chanx_right_in[10]:18 prog_clk[0]:333 6.887296e-07 +43 chanx_right_in[10]:19 prog_clk[0]:334 6.887296e-07 +44 chanx_right_in[10]:32 prog_clk[0]:395 0.0005234542 +45 chanx_right_in[10]:32 prog_clk[0]:391 0.0004645338 +46 chanx_right_in[10]:32 prog_clk[0]:387 0.0001135885 +47 chanx_right_in[10]:29 chany_top_in[3]:14 0.0003829805 +48 chanx_right_in[10]:30 chany_top_in[3]:13 0.0003829805 +49 chanx_right_in[10]:31 mux_tree_tapbuf_size8_0_sram[0]:15 0.0009491743 +50 chanx_right_in[10]:31 mux_tree_tapbuf_size8_0_sram[0]:16 0.0001596061 +51 chanx_right_in[10]:18 mux_tree_tapbuf_size8_0_sram[0]:8 3.920731e-05 +52 chanx_right_in[10]:18 mux_tree_tapbuf_size8_0_sram[0]:4 6.552703e-05 +53 chanx_right_in[10]:19 mux_tree_tapbuf_size8_0_sram[0]:8 6.552703e-05 +54 chanx_right_in[10]:19 mux_tree_tapbuf_size8_0_sram[0]:9 3.920731e-05 +55 chanx_right_in[10]:32 mux_tree_tapbuf_size8_0_sram[0]:17 0.0001596061 +56 chanx_right_in[10]:32 mux_tree_tapbuf_size8_0_sram[0]:16 0.0009491743 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:33 0.0001065333 +1 chanx_right_in[10]:25 chanx_right_in[10]:24 0.0045 +2 chanx_right_in[10]:24 chanx_right_in[10]:23 0.003602679 +3 chanx_right_in[10]:26 chanx_right_in[10]:25 0.003616072 +4 chanx_right_in[10]:27 chanx_right_in[10]:26 0.0045 +5 chanx_right_in[10]:28 chanx_right_in[10]:27 0.00341 +6 chanx_right_in[10]:28 chanx_right_in[10]:4 5.69697e-05 +7 chanx_right_in[10]:29 chanx_right_in[10]:28 0.00341 +8 chanx_right_in[10]:31 chanx_right_in[10]:30 0.00341 +9 chanx_right_in[10]:30 chanx_right_in[10]:29 0.004472049 +10 chanx_right_in[10]:17 chanx_right_in[10]:16 0.0045 +11 chanx_right_in[10]:16 chanx_right_in[10]:15 0.0184375 +12 chanx_right_in[10]:14 chanx_right_in[10]:13 0.01720982 +13 chanx_right_in[10]:15 chanx_right_in[10]:14 0.0045 +14 chanx_right_in[10]:11 chanx_right_in[10]:10 0.0045 +15 chanx_right_in[10]:10 chanx_right_in[10]:9 0.0005267857 +16 chanx_right_in[10]:8 chanx_right_in[10]:7 0.012625 +17 chanx_right_in[10]:9 chanx_right_in[10]:8 0.0045 +18 chanx_right_in[10]:5 ropt_mt_inst_753:A 0.152 +19 chanx_right_in[10]:22 chanx_right_in[10]:21 9.51087e-05 +20 chanx_right_in[10]:23 chanx_right_in[10]:22 0.0045 +21 chanx_right_in[10]:23 chanx_right_in[10]:20 0.001174107 +22 chanx_right_in[10]:21 mux_top_track_12\/mux_l1_in_0_:A0 0.152 +23 chanx_right_in[10]:18 mux_left_track_33\/mux_l1_in_1_:A0 0.152 +24 chanx_right_in[10]:18 chanx_right_in[10]:17 0.0001779891 +25 chanx_right_in[10]:19 chanx_right_in[10]:18 0.0193817 +26 chanx_right_in[10]:20 chanx_right_in[10]:19 0.0045 +27 chanx_right_in[10]:6 chanx_right_in[10]:5 0.002841518 +28 chanx_right_in[10]:7 chanx_right_in[10]:6 0.000607143 +29 chanx_right_in[10]:12 chanx_right_in[10]:11 0.00078125 +30 chanx_right_in[10]:13 chanx_right_in[10]:12 0.0003035715 +31 chanx_right_in[10]:33 chanx_right_in[10]:32 0.002934367 +32 chanx_right_in[10]:32 chanx_right_in[10]:31 0.007800433 + +*END + +*D_NET chanx_left_in[10] 0.02915621 //LENGTH 169.525 LUMPCC 0.01388461 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 57.120 +*I mux_top_track_12\/mux_l1_in_1_:A1 I *L 0.00198 *C 76.265 66.980 +*I BUFT_RR_73:A I *L 0.001776 *C 128.340 55.760 +*I mux_right_track_32\/mux_l1_in_2_:A0 I *L 0.001631 *C 94.130 71.400 +*N chanx_left_in[10]:4 *C 94.093 71.400 +*N chanx_left_in[10]:5 *C 92.505 71.400 +*N chanx_left_in[10]:6 *C 92.460 71.355 +*N chanx_left_in[10]:7 *C 129.010 55.760 +*N chanx_left_in[10]:8 *C 128.377 55.760 +*N chanx_left_in[10]:9 *C 129.675 55.760 +*N chanx_left_in[10]:10 *C 129.720 55.760 +*N chanx_left_in[10]:11 *C 129.718 55.760 +*N chanx_left_in[10]:12 *C 129.720 55.768 +*N chanx_left_in[10]:13 *C 129.720 63.233 +*N chanx_left_in[10]:14 *C 129.700 63.240 +*N chanx_left_in[10]:15 *C 92.468 63.240 +*N chanx_left_in[10]:16 *C 92.460 63.298 +*N chanx_left_in[10]:17 *C 92.460 68.000 +*N chanx_left_in[10]:18 *C 92.453 68.000 +*N chanx_left_in[10]:19 *C 86.028 68.000 +*N chanx_left_in[10]:20 *C 86.020 67.943 +*N chanx_left_in[10]:21 *C 86.020 67.025 +*N chanx_left_in[10]:22 *C 85.975 66.980 +*N chanx_left_in[10]:23 *C 76.303 66.980 +*N chanx_left_in[10]:24 *C 77.740 66.980 +*N chanx_left_in[10]:25 *C 77.740 66.935 +*N chanx_left_in[10]:26 *C 77.740 60.578 +*N chanx_left_in[10]:27 *C 77.733 60.520 +*N chanx_left_in[10]:28 *C 48.760 60.520 +*N chanx_left_in[10]:29 *C 48.760 61.200 +*N chanx_left_in[10]:30 *C 43.700 61.200 +*N chanx_left_in[10]:31 *C 43.700 60.520 +*N chanx_left_in[10]:32 *C 32.200 60.520 +*N chanx_left_in[10]:33 *C 32.200 61.200 +*N chanx_left_in[10]:34 *C 11.040 61.200 +*N chanx_left_in[10]:35 *C 11.040 60.520 +*N chanx_left_in[10]:36 *C 5.540 60.520 +*N chanx_left_in[10]:37 *C 5.520 60.513 +*N chanx_left_in[10]:38 *C 5.520 57.128 +*N chanx_left_in[10]:39 *C 5.500 57.120 + +*CAP +0 chanx_left_in[10] 0.0002921134 +1 mux_top_track_12\/mux_l1_in_1_:A1 1e-06 +2 BUFT_RR_73:A 1e-06 +3 mux_right_track_32\/mux_l1_in_2_:A0 1e-06 +4 chanx_left_in[10]:4 0.0001359732 +5 chanx_left_in[10]:5 0.0001359732 +6 chanx_left_in[10]:6 0.0001664373 +7 chanx_left_in[10]:7 6.866618e-05 +8 chanx_left_in[10]:8 0.000122928 +9 chanx_left_in[10]:9 0.000122928 +10 chanx_left_in[10]:10 3.476897e-05 +11 chanx_left_in[10]:11 6.866618e-05 +12 chanx_left_in[10]:12 0.0004280324 +13 chanx_left_in[10]:13 0.0004280324 +14 chanx_left_in[10]:14 0.001182866 +15 chanx_left_in[10]:15 0.001182866 +16 chanx_left_in[10]:16 0.0002049341 +17 chanx_left_in[10]:17 0.0004079114 +18 chanx_left_in[10]:18 0.0001793636 +19 chanx_left_in[10]:19 0.0001793636 +20 chanx_left_in[10]:20 6.509691e-05 +21 chanx_left_in[10]:21 6.509691e-05 +22 chanx_left_in[10]:22 0.000482447 +23 chanx_left_in[10]:23 9.251641e-05 +24 chanx_left_in[10]:24 0.0006072719 +25 chanx_left_in[10]:25 0.0003840954 +26 chanx_left_in[10]:26 0.0003840954 +27 chanx_left_in[10]:27 0.00113667 +28 chanx_left_in[10]:28 0.001193812 +29 chanx_left_in[10]:29 0.0003160553 +30 chanx_left_in[10]:30 0.0003248101 +31 chanx_left_in[10]:31 0.0006885527 +32 chanx_left_in[10]:32 0.000680146 +33 chanx_left_in[10]:33 0.0006979103 +34 chanx_left_in[10]:34 0.0007012957 +35 chanx_left_in[10]:35 0.0005941034 +36 chanx_left_in[10]:36 0.0005332275 +37 chanx_left_in[10]:37 0.0003437282 +38 chanx_left_in[10]:38 0.0003437282 +39 chanx_left_in[10]:39 0.0002921134 +40 chanx_left_in[10]:15 chanx_left_in[2]:14 2.216709e-05 +41 chanx_left_in[10]:14 chanx_left_in[2]:13 2.216709e-05 +42 chanx_left_in[10]:24 chanx_left_in[2]:18 5.839212e-06 +43 chanx_left_in[10]:18 chanx_left_in[2]:14 0.0003584521 +44 chanx_left_in[10]:19 chanx_left_in[2]:18 0.0003584521 +45 chanx_left_in[10]:22 chanx_left_in[2]:14 5.839212e-06 +46 chanx_left_in[10] chanx_left_in[4]:27 1.981515e-07 +47 chanx_left_in[10]:16 chanx_left_in[4]:24 8.238151e-06 +48 chanx_left_in[10]:11 chanx_left_in[4]:17 1.074318e-05 +49 chanx_left_in[10]:6 chanx_left_in[4]:23 2.048032e-05 +50 chanx_left_in[10]:27 chanx_left_in[4]:25 0.0002974628 +51 chanx_left_in[10]:27 chanx_left_in[4]:26 7.633596e-05 +52 chanx_left_in[10]:36 chanx_left_in[4]:27 4.966517e-05 +53 chanx_left_in[10]:39 chanx_left_in[4]:26 1.981515e-07 +54 chanx_left_in[10]:17 chanx_left_in[4]:23 8.238151e-06 +55 chanx_left_in[10]:17 chanx_left_in[4]:24 2.048032e-05 +56 chanx_left_in[10]:35 chanx_left_in[4]:26 4.966517e-05 +57 chanx_left_in[10]:34 chanx_left_in[4]:27 0.00118771 +58 chanx_left_in[10]:33 chanx_left_in[4]:26 0.00118771 +59 chanx_left_in[10]:32 chanx_left_in[4]:27 0.0002131328 +60 chanx_left_in[10]:31 chanx_left_in[4]:26 0.0002131328 +61 chanx_left_in[10]:30 chanx_left_in[4]:27 0.0002928076 +62 chanx_left_in[10]:29 chanx_left_in[4]:26 0.0002928076 +63 chanx_left_in[10]:28 chanx_left_in[4]:26 0.0002974628 +64 chanx_left_in[10]:28 chanx_left_in[4]:27 7.633596e-05 +65 chanx_left_in[10]:7 chanx_left_in[4]:16 1.074318e-05 +66 chanx_left_in[10]:15 chanx_left_in[9]:16 0.0004514421 +67 chanx_left_in[10]:14 chanx_left_in[9]:15 0.0004514421 +68 chanx_left_in[10]:27 chany_top_in[18]:12 0.0005688686 +69 chanx_left_in[10]:20 chany_top_in[18]:21 1.337351e-05 +70 chanx_left_in[10]:21 chany_top_in[18]:20 1.337351e-05 +71 chanx_left_in[10]:30 chany_top_in[18]:11 2.02106e-05 +72 chanx_left_in[10]:29 chany_top_in[18]:12 2.02106e-05 +73 chanx_left_in[10]:28 chany_top_in[18]:11 0.0005688686 +74 chanx_left_in[10]:15 right_bottom_grid_pin_1_[0]:11 0.0005657495 +75 chanx_left_in[10]:14 right_bottom_grid_pin_1_[0]:12 0.0005657495 +76 chanx_left_in[10]:34 mux_tree_tapbuf_size6_1_sram[0]:18 0.0004067791 +77 chanx_left_in[10]:33 mux_tree_tapbuf_size6_1_sram[0]:19 0.0004067791 +78 chanx_left_in[10]:32 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001186417 +79 chanx_left_in[10]:31 mux_tree_tapbuf_size6_1_sram[0]:19 0.0001186417 +80 chanx_left_in[10]:27 mux_tree_tapbuf_size8_0_sram[1]:26 0.0004923707 +81 chanx_left_in[10]:28 mux_tree_tapbuf_size8_0_sram[1]:25 0.0004923707 +82 chanx_left_in[10]:16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.252812e-05 +83 chanx_left_in[10]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.252812e-05 +84 chanx_left_in[10]:16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 4.730296e-07 +85 chanx_left_in[10]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001455387 +86 chanx_left_in[10]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.001174646 +87 chanx_left_in[10]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001455387 +88 chanx_left_in[10]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001174646 +89 chanx_left_in[10]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 4.730296e-07 +90 chanx_left_in[10]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.000358452 +91 chanx_left_in[10]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.000358452 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:39 0.0006689666 +1 chanx_left_in[10]:16 chanx_left_in[10]:15 0.00341 +2 chanx_left_in[10]:15 chanx_left_in[10]:14 0.005833091 +3 chanx_left_in[10]:14 chanx_left_in[10]:13 0.00341 +4 chanx_left_in[10]:13 chanx_left_in[10]:12 0.001169517 +5 chanx_left_in[10]:11 chanx_left_in[10]:10 0.00341 +6 chanx_left_in[10]:11 chanx_left_in[10]:7 0.0001039141 +7 chanx_left_in[10]:12 chanx_left_in[10]:11 0.00341 +8 chanx_left_in[10]:10 chanx_left_in[10]:9 0.0045 +9 chanx_left_in[10]:9 chanx_left_in[10]:8 0.001158482 +10 chanx_left_in[10]:8 BUFT_RR_73:A 0.152 +11 chanx_left_in[10]:23 mux_top_track_12\/mux_l1_in_1_:A1 0.152 +12 chanx_left_in[10]:5 chanx_left_in[10]:4 0.001417411 +13 chanx_left_in[10]:6 chanx_left_in[10]:5 0.0045 +14 chanx_left_in[10]:4 mux_right_track_32\/mux_l1_in_2_:A0 0.152 +15 chanx_left_in[10]:24 chanx_left_in[10]:23 0.001283482 +16 chanx_left_in[10]:24 chanx_left_in[10]:22 0.007352679 +17 chanx_left_in[10]:25 chanx_left_in[10]:24 0.0045 +18 chanx_left_in[10]:26 chanx_left_in[10]:25 0.005676339 +19 chanx_left_in[10]:27 chanx_left_in[10]:26 0.00341 +20 chanx_left_in[10]:36 chanx_left_in[10]:35 0.0008616665 +21 chanx_left_in[10]:37 chanx_left_in[10]:36 0.00341 +22 chanx_left_in[10]:39 chanx_left_in[10]:38 0.00341 +23 chanx_left_in[10]:38 chanx_left_in[10]:37 0.0005303166 +24 chanx_left_in[10]:17 chanx_left_in[10]:16 0.004198661 +25 chanx_left_in[10]:17 chanx_left_in[10]:6 0.002995536 +26 chanx_left_in[10]:18 chanx_left_in[10]:17 0.00341 +27 chanx_left_in[10]:20 chanx_left_in[10]:19 0.00341 +28 chanx_left_in[10]:19 chanx_left_in[10]:18 0.001006583 +29 chanx_left_in[10]:22 chanx_left_in[10]:21 0.0045 +30 chanx_left_in[10]:21 chanx_left_in[10]:20 0.0008191965 +31 chanx_left_in[10]:35 chanx_left_in[10]:34 0.0001065333 +32 chanx_left_in[10]:34 chanx_left_in[10]:33 0.003315066 +33 chanx_left_in[10]:33 chanx_left_in[10]:32 0.0001065333 +34 chanx_left_in[10]:32 chanx_left_in[10]:31 0.001801667 +35 chanx_left_in[10]:31 chanx_left_in[10]:30 0.0001065333 +36 chanx_left_in[10]:30 chanx_left_in[10]:29 0.0007927333 +37 chanx_left_in[10]:29 chanx_left_in[10]:28 0.0001065333 +38 chanx_left_in[10]:28 chanx_left_in[10]:27 0.004539025 + +*END + +*D_NET chany_top_in[6] 0.008078038 //LENGTH 52.810 LUMPCC 0.003095756 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 74.980 102.070 +*I mux_left_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 58.325 79.900 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 86.120 79.900 +*N chany_top_in[6]:3 *C 86.020 79.900 +*N chany_top_in[6]:4 *C 86.020 79.900 +*N chany_top_in[6]:5 *C 86.020 79.560 +*N chany_top_in[6]:6 *C 86.013 79.560 +*N chany_top_in[6]:7 *C 58.363 79.900 +*N chany_top_in[6]:8 *C 61.135 79.900 +*N chany_top_in[6]:9 *C 61.180 79.900 +*N chany_top_in[6]:10 *C 61.180 79.560 +*N chany_top_in[6]:11 *C 61.188 79.560 +*N chany_top_in[6]:12 *C 75.440 79.560 +*N chany_top_in[6]:13 *C 75.440 79.568 +*N chany_top_in[6]:14 *C 75.440 100.633 +*N chany_top_in[6]:15 *C 75.425 100.640 +*N chany_top_in[6]:16 *C 74.983 100.640 +*N chany_top_in[6]:17 *C 74.980 100.698 + +*CAP +0 chany_top_in[6] 7.137279e-05 +1 mux_left_track_3\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[6]:3 3.302182e-05 +4 chany_top_in[6]:4 5.163396e-05 +5 chany_top_in[6]:5 5.535521e-05 +6 chany_top_in[6]:6 0.0006481208 +7 chany_top_in[6]:7 0.0001682629 +8 chany_top_in[6]:8 0.0001682629 +9 chany_top_in[6]:9 5.052777e-05 +10 chany_top_in[6]:10 5.431443e-05 +11 chany_top_in[6]:11 0.0008233433 +12 chany_top_in[6]:12 0.001471464 +13 chany_top_in[6]:13 0.0005919063 +14 chany_top_in[6]:14 0.0005919063 +15 chany_top_in[6]:15 6.470866e-05 +16 chany_top_in[6]:16 6.470866e-05 +17 chany_top_in[6]:17 7.137279e-05 +18 chany_top_in[6] chany_top_in[3] 2.188786e-05 +19 chany_top_in[6]:13 chany_top_in[3]:13 0.0001021918 +20 chany_top_in[6]:13 chany_top_in[3]:14 0.0001969185 +21 chany_top_in[6]:14 chany_top_in[3]:14 0.0001021918 +22 chany_top_in[6]:14 chany_top_in[3]:15 0.0001969185 +23 chany_top_in[6]:17 chany_top_in[3]:18 2.188786e-05 +24 chany_top_in[6]:11 chany_top_in[13]:8 0.0002785544 +25 chany_top_in[6]:8 chany_top_in[13]:10 8.373349e-06 +26 chany_top_in[6]:7 chany_top_in[13]:9 8.373349e-06 +27 chany_top_in[6]:6 chany_top_in[13]:7 0.0001642989 +28 chany_top_in[6]:12 chany_top_in[13]:8 0.0001642989 +29 chany_top_in[6]:12 chany_top_in[13]:7 0.0002785544 +30 chany_top_in[6]:13 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0007756532 +31 chany_top_in[6]:14 mux_top_track_20/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0007756532 + +*RES +0 chany_top_in[6] chany_top_in[6]:17 0.001225446 +1 chany_top_in[6]:10 chany_top_in[6]:9 0.0001634615 +2 chany_top_in[6]:11 chany_top_in[6]:10 0.00341 +3 chany_top_in[6]:8 chany_top_in[6]:7 0.002475447 +4 chany_top_in[6]:9 chany_top_in[6]:8 0.0045 +5 chany_top_in[6]:7 mux_left_track_3\/mux_l1_in_0_:A1 0.152 +6 chany_top_in[6]:5 chany_top_in[6]:4 0.0001634615 +7 chany_top_in[6]:6 chany_top_in[6]:5 0.00341 +8 chany_top_in[6]:3 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +9 chany_top_in[6]:4 chany_top_in[6]:3 0.0045 +10 chany_top_in[6]:12 chany_top_in[6]:11 0.002232892 +11 chany_top_in[6]:12 chany_top_in[6]:6 0.001656358 +12 chany_top_in[6]:13 chany_top_in[6]:12 0.00341 +13 chany_top_in[6]:15 chany_top_in[6]:14 0.00341 +14 chany_top_in[6]:14 chany_top_in[6]:13 0.003300183 +15 chany_top_in[6]:17 chany_top_in[6]:16 0.00341 +16 chany_top_in[6]:16 chany_top_in[6]:15 6.499218e-05 + +*END + +*D_NET chany_top_in[14] 0.009482052 //LENGTH 68.700 LUMPCC 0.0004875192 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 54.740 102.070 +*I mux_left_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 46.365 79.900 +*I mux_right_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 89.340 94.180 +*N chany_top_in[14]:3 *C 89.340 94.180 +*N chany_top_in[14]:4 *C 89.240 94.520 +*N chany_top_in[14]:5 *C 64.905 94.520 +*N chany_top_in[14]:6 *C 64.860 94.565 +*N chany_top_in[14]:7 *C 64.860 95.142 +*N chany_top_in[14]:8 *C 64.853 95.200 +*N chany_top_in[14]:9 *C 46.403 79.900 +*N chany_top_in[14]:10 *C 46.875 79.900 +*N chany_top_in[14]:11 *C 46.920 79.945 +*N chany_top_in[14]:12 *C 46.920 82.903 +*N chany_top_in[14]:13 *C 46.928 82.960 +*N chany_top_in[14]:14 *C 50.580 82.960 +*N chany_top_in[14]:15 *C 50.600 82.968 +*N chany_top_in[14]:16 *C 50.600 95.193 +*N chany_top_in[14]:17 *C 50.620 95.200 +*N chany_top_in[14]:18 *C 54.740 95.200 +*N chany_top_in[14]:19 *C 54.740 95.258 + +*CAP +0 chany_top_in[14] 0.0003751691 +1 mux_left_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[14]:3 5.718017e-05 +4 chany_top_in[14]:4 0.001655969 +5 chany_top_in[14]:5 0.001628091 +6 chany_top_in[14]:6 6.013667e-05 +7 chany_top_in[14]:7 6.013667e-05 +8 chany_top_in[14]:8 0.0006209079 +9 chany_top_in[14]:9 6.937118e-05 +10 chany_top_in[14]:10 6.937118e-05 +11 chany_top_in[14]:11 0.0001951331 +12 chany_top_in[14]:12 0.0001951331 +13 chany_top_in[14]:13 0.0004388311 +14 chany_top_in[14]:14 0.0004388311 +15 chany_top_in[14]:15 0.0008366799 +16 chany_top_in[14]:16 0.0008366799 +17 chany_top_in[14]:17 0.0002294179 +18 chany_top_in[14]:18 0.0008503258 +19 chany_top_in[14]:19 0.0003751691 +20 chany_top_in[14]:17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.843966e-05 +21 chany_top_in[14]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001553199 +22 chany_top_in[14]:18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.843966e-05 +23 chany_top_in[14]:18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001553199 + +*RES +0 chany_top_in[14] chany_top_in[14]:19 0.006082589 +1 chany_top_in[14]:17 chany_top_in[14]:16 0.00341 +2 chany_top_in[14]:16 chany_top_in[14]:15 0.00191525 +3 chany_top_in[14]:14 chany_top_in[14]:13 0.000572225 +4 chany_top_in[14]:15 chany_top_in[14]:14 0.00341 +5 chany_top_in[14]:12 chany_top_in[14]:11 0.002640625 +6 chany_top_in[14]:13 chany_top_in[14]:12 0.00341 +7 chany_top_in[14]:10 chany_top_in[14]:9 0.000421875 +8 chany_top_in[14]:11 chany_top_in[14]:10 0.0045 +9 chany_top_in[14]:9 mux_left_track_1\/mux_l1_in_1_:A1 0.152 +10 chany_top_in[14]:7 chany_top_in[14]:6 0.000515625 +11 chany_top_in[14]:8 chany_top_in[14]:7 0.00341 +12 chany_top_in[14]:5 chany_top_in[14]:4 0.02172768 +13 chany_top_in[14]:6 chany_top_in[14]:5 0.0045 +14 chany_top_in[14]:3 mux_right_track_2\/mux_l1_in_1_:A1 0.152 +15 chany_top_in[14]:19 chany_top_in[14]:18 0.00341 +16 chany_top_in[14]:18 chany_top_in[14]:17 0.0006454666 +17 chany_top_in[14]:18 chany_top_in[14]:8 0.001584292 +18 chany_top_in[14]:4 chany_top_in[14]:3 0.0003035715 + +*END + +*D_NET top_left_grid_pin_37_[0] 0.01323712 //LENGTH 99.065 LUMPCC 0.003047938 DR + +*CONN +*P top_left_grid_pin_37_[0] I *L 0.29796 *C 32.200 102.070 +*I mux_top_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 48.935 88.060 +*I mux_top_track_30\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.265 79.900 +*I mux_top_track_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 78.835 53.380 +*I mux_top_track_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.740 63.580 +*N top_left_grid_pin_37_[0]:5 *C 54.740 63.580 +*N top_left_grid_pin_37_[0]:6 *C 54.740 63.580 +*N top_left_grid_pin_37_[0]:7 *C 78.797 53.380 +*N top_left_grid_pin_37_[0]:8 *C 78.245 53.380 +*N top_left_grid_pin_37_[0]:9 *C 78.200 53.380 +*N top_left_grid_pin_37_[0]:10 *C 78.200 53.720 +*N top_left_grid_pin_37_[0]:11 *C 78.193 53.720 +*N top_left_grid_pin_37_[0]:12 *C 54.288 53.720 +*N top_left_grid_pin_37_[0]:13 *C 54.280 53.778 +*N top_left_grid_pin_37_[0]:14 *C 54.280 63.580 +*N top_left_grid_pin_37_[0]:15 *C 54.280 79.855 +*N top_left_grid_pin_37_[0]:16 *C 54.235 79.900 +*N top_left_grid_pin_37_[0]:17 *C 53.265 79.900 +*N top_left_grid_pin_37_[0]:18 *C 48.345 79.900 +*N top_left_grid_pin_37_[0]:19 *C 48.300 79.945 +*N top_left_grid_pin_37_[0]:20 *C 48.898 88.060 +*N top_left_grid_pin_37_[0]:21 *C 48.345 88.060 +*N top_left_grid_pin_37_[0]:22 *C 48.300 88.060 +*N top_left_grid_pin_37_[0]:23 *C 48.300 93.103 +*N top_left_grid_pin_37_[0]:24 *C 48.293 93.160 +*N top_left_grid_pin_37_[0]:25 *C 32.208 93.160 +*N top_left_grid_pin_37_[0]:26 *C 32.200 93.218 + +*CAP +0 top_left_grid_pin_37_[0] 0.000346917 +1 mux_top_track_2\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_30\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_0_:A0 1e-06 +4 mux_top_track_14\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_37_[0]:5 3.622999e-05 +6 top_left_grid_pin_37_[0]:6 7.057114e-05 +7 top_left_grid_pin_37_[0]:7 7.29421e-05 +8 top_left_grid_pin_37_[0]:8 7.29421e-05 +9 top_left_grid_pin_37_[0]:9 4.576772e-05 +10 top_left_grid_pin_37_[0]:10 4.953688e-05 +11 top_left_grid_pin_37_[0]:11 0.001471244 +12 top_left_grid_pin_37_[0]:12 0.001471244 +13 top_left_grid_pin_37_[0]:13 0.000609344 +14 top_left_grid_pin_37_[0]:14 0.001486867 +15 top_left_grid_pin_37_[0]:15 0.0008414992 +16 top_left_grid_pin_37_[0]:16 7.899225e-05 +17 top_left_grid_pin_37_[0]:17 0.0003823135 +18 top_left_grid_pin_37_[0]:18 0.0002766609 +19 top_left_grid_pin_37_[0]:19 0.0002515352 +20 top_left_grid_pin_37_[0]:20 5.829386e-05 +21 top_left_grid_pin_37_[0]:21 5.829386e-05 +22 top_left_grid_pin_37_[0]:22 0.0005084758 +23 top_left_grid_pin_37_[0]:23 0.0002278057 +24 top_left_grid_pin_37_[0]:24 0.000710392 +25 top_left_grid_pin_37_[0]:25 0.000710392 +26 top_left_grid_pin_37_[0]:26 0.000346917 +27 top_left_grid_pin_37_[0] prog_clk[0] 3.203321e-05 +28 top_left_grid_pin_37_[0] prog_clk[0]:593 0.0001681479 +29 top_left_grid_pin_37_[0]:26 prog_clk[0]:592 0.0001681479 +30 top_left_grid_pin_37_[0]:26 prog_clk[0]:596 3.203321e-05 +31 top_left_grid_pin_37_[0]:12 prog_clk[0]:331 4.894521e-05 +32 top_left_grid_pin_37_[0]:10 prog_clk[0]:292 1.054373e-05 +33 top_left_grid_pin_37_[0]:11 prog_clk[0]:330 4.894521e-05 +34 top_left_grid_pin_37_[0]:9 prog_clk[0]:298 1.054373e-05 +35 top_left_grid_pin_37_[0]:12 chany_top_in[2]:6 0.0002981444 +36 top_left_grid_pin_37_[0]:11 chany_top_in[2]:7 0.0002981444 +37 top_left_grid_pin_37_[0]:24 top_left_grid_pin_36_[0]:26 0.0003650795 +38 top_left_grid_pin_37_[0]:25 top_left_grid_pin_36_[0]:27 0.0003650795 +39 top_left_grid_pin_37_[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001292553 +40 top_left_grid_pin_37_[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001292553 +41 top_left_grid_pin_37_[0]:19 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002175343 +42 top_left_grid_pin_37_[0]:23 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.477655e-05 +43 top_left_grid_pin_37_[0]:22 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.477655e-05 +44 top_left_grid_pin_37_[0]:22 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002175343 +45 top_left_grid_pin_37_[0]:18 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001044191 +46 top_left_grid_pin_37_[0]:19 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.508986e-05 +47 top_left_grid_pin_37_[0]:22 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.508986e-05 +48 top_left_grid_pin_37_[0]:17 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001044191 + +*RES +0 top_left_grid_pin_37_[0] top_left_grid_pin_37_[0]:26 0.007904018 +1 top_left_grid_pin_37_[0]:5 mux_top_track_14\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_37_[0]:6 top_left_grid_pin_37_[0]:5 0.0045 +3 top_left_grid_pin_37_[0]:16 top_left_grid_pin_37_[0]:15 0.0045 +4 top_left_grid_pin_37_[0]:15 top_left_grid_pin_37_[0]:14 0.01453125 +5 top_left_grid_pin_37_[0]:18 top_left_grid_pin_37_[0]:17 0.004392858 +6 top_left_grid_pin_37_[0]:19 top_left_grid_pin_37_[0]:18 0.0045 +7 top_left_grid_pin_37_[0]:23 top_left_grid_pin_37_[0]:22 0.004502232 +8 top_left_grid_pin_37_[0]:24 top_left_grid_pin_37_[0]:23 0.00341 +9 top_left_grid_pin_37_[0]:26 top_left_grid_pin_37_[0]:25 0.00341 +10 top_left_grid_pin_37_[0]:25 top_left_grid_pin_37_[0]:24 0.002519983 +11 top_left_grid_pin_37_[0]:21 top_left_grid_pin_37_[0]:20 0.0004933036 +12 top_left_grid_pin_37_[0]:22 top_left_grid_pin_37_[0]:21 0.0045 +13 top_left_grid_pin_37_[0]:22 top_left_grid_pin_37_[0]:19 0.007245536 +14 top_left_grid_pin_37_[0]:20 mux_top_track_2\/mux_l1_in_0_:A0 0.152 +15 top_left_grid_pin_37_[0]:17 mux_top_track_30\/mux_l1_in_0_:A1 0.152 +16 top_left_grid_pin_37_[0]:17 top_left_grid_pin_37_[0]:16 0.0008660714 +17 top_left_grid_pin_37_[0]:13 top_left_grid_pin_37_[0]:12 0.00341 +18 top_left_grid_pin_37_[0]:12 top_left_grid_pin_37_[0]:11 0.003745117 +19 top_left_grid_pin_37_[0]:10 top_left_grid_pin_37_[0]:9 0.0001634615 +20 top_left_grid_pin_37_[0]:11 top_left_grid_pin_37_[0]:10 0.00341 +21 top_left_grid_pin_37_[0]:8 top_left_grid_pin_37_[0]:7 0.0004933036 +22 top_left_grid_pin_37_[0]:9 top_left_grid_pin_37_[0]:8 0.0045 +23 top_left_grid_pin_37_[0]:7 mux_top_track_6\/mux_l1_in_0_:A0 0.152 +24 top_left_grid_pin_37_[0]:14 top_left_grid_pin_37_[0]:13 0.008752232 +25 top_left_grid_pin_37_[0]:14 top_left_grid_pin_37_[0]:6 0.0004107143 + +*END + +*D_NET right_top_grid_pin_44_[0] 0.008730555 //LENGTH 64.370 LUMPCC 0.001981722 DR + +*CONN +*P right_top_grid_pin_44_[0] I *L 0.29796 *C 139.380 74.835 +*I mux_right_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 105.465 70.040 +*I mux_right_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 92.750 64.260 +*I mux_right_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 102.295 75.140 +*N right_top_grid_pin_44_[0]:4 *C 102.333 75.140 +*N right_top_grid_pin_44_[0]:5 *C 92.788 64.260 +*N right_top_grid_pin_44_[0]:6 *C 102.995 64.260 +*N right_top_grid_pin_44_[0]:7 *C 103.040 64.305 +*N right_top_grid_pin_44_[0]:8 *C 105.428 70.040 +*N right_top_grid_pin_44_[0]:9 *C 103.085 70.040 +*N right_top_grid_pin_44_[0]:10 *C 103.040 70.040 +*N right_top_grid_pin_44_[0]:11 *C 103.040 75.095 +*N right_top_grid_pin_44_[0]:12 *C 103.040 75.140 +*N right_top_grid_pin_44_[0]:13 *C 103.500 75.140 +*N right_top_grid_pin_44_[0]:14 *C 103.500 75.480 +*N right_top_grid_pin_44_[0]:15 *C 136.160 75.480 +*N right_top_grid_pin_44_[0]:16 *C 136.160 74.460 +*N right_top_grid_pin_44_[0]:17 *C 139.335 74.460 +*N right_top_grid_pin_44_[0]:18 *C 139.380 74.505 + +*CAP +0 right_top_grid_pin_44_[0] 2.39514e-05 +1 mux_right_track_4\/mux_l1_in_2_:A0 1e-06 +2 mux_right_track_24\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_0\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_44_[0]:4 5.129307e-05 +5 right_top_grid_pin_44_[0]:5 0.0005206694 +6 right_top_grid_pin_44_[0]:6 0.0005206694 +7 right_top_grid_pin_44_[0]:7 0.0002597999 +8 right_top_grid_pin_44_[0]:8 0.0002253898 +9 right_top_grid_pin_44_[0]:9 0.0002253898 +10 right_top_grid_pin_44_[0]:10 0.0005220085 +11 right_top_grid_pin_44_[0]:11 0.0002275802 +12 right_top_grid_pin_44_[0]:12 0.0001111669 +13 right_top_grid_pin_44_[0]:13 6.518541e-05 +14 right_top_grid_pin_44_[0]:14 0.001711765 +15 right_top_grid_pin_44_[0]:15 0.001746019 +16 right_top_grid_pin_44_[0]:16 0.0002853321 +17 right_top_grid_pin_44_[0]:17 0.0002256622 +18 right_top_grid_pin_44_[0]:18 2.39514e-05 +19 right_top_grid_pin_44_[0] right_top_grid_pin_42_[0] 6.49116e-06 +20 right_top_grid_pin_44_[0]:10 right_top_grid_pin_42_[0]:7 9.712731e-05 +21 right_top_grid_pin_44_[0]:10 right_top_grid_pin_42_[0]:10 0.0001452567 +22 right_top_grid_pin_44_[0]:18 right_top_grid_pin_42_[0]:17 6.49116e-06 +23 right_top_grid_pin_44_[0]:5 right_top_grid_pin_42_[0]:12 2.875395e-05 +24 right_top_grid_pin_44_[0]:6 right_top_grid_pin_42_[0]:13 2.875395e-05 +25 right_top_grid_pin_44_[0]:7 right_top_grid_pin_42_[0]:10 9.712731e-05 +26 right_top_grid_pin_44_[0]:7 right_top_grid_pin_42_[0]:11 3.661129e-05 +27 right_top_grid_pin_44_[0]:11 right_top_grid_pin_42_[0]:7 0.0001086454 +28 right_top_grid_pin_44_[0]:14 right_top_grid_pin_48_[0]:23 0.0002550397 +29 right_top_grid_pin_44_[0]:14 right_top_grid_pin_48_[0]:25 8.151316e-05 +30 right_top_grid_pin_44_[0]:15 right_top_grid_pin_48_[0]:26 8.151316e-05 +31 right_top_grid_pin_44_[0]:15 right_top_grid_pin_48_[0]:24 0.0002550397 +32 right_top_grid_pin_44_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001684038 +33 right_top_grid_pin_44_[0]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.009168e-05 +34 right_top_grid_pin_44_[0]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001684038 +35 right_top_grid_pin_44_[0]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.009168e-05 +36 right_top_grid_pin_44_[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001981836 +37 right_top_grid_pin_44_[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001981836 + +*RES +0 right_top_grid_pin_44_[0] right_top_grid_pin_44_[0]:18 0.0002946429 +1 right_top_grid_pin_44_[0]:8 mux_right_track_4\/mux_l1_in_2_:A0 0.152 +2 right_top_grid_pin_44_[0]:9 right_top_grid_pin_44_[0]:8 0.002091518 +3 right_top_grid_pin_44_[0]:10 right_top_grid_pin_44_[0]:9 0.0045 +4 right_top_grid_pin_44_[0]:10 right_top_grid_pin_44_[0]:7 0.005120536 +5 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:16 0.002834822 +6 right_top_grid_pin_44_[0]:18 right_top_grid_pin_44_[0]:17 0.0045 +7 right_top_grid_pin_44_[0]:5 mux_right_track_24\/mux_l1_in_1_:A0 0.152 +8 right_top_grid_pin_44_[0]:6 right_top_grid_pin_44_[0]:5 0.00911384 +9 right_top_grid_pin_44_[0]:7 right_top_grid_pin_44_[0]:6 0.0045 +10 right_top_grid_pin_44_[0]:4 mux_right_track_0\/mux_l1_in_1_:A0 0.152 +11 right_top_grid_pin_44_[0]:12 right_top_grid_pin_44_[0]:11 0.0045 +12 right_top_grid_pin_44_[0]:12 right_top_grid_pin_44_[0]:4 0.0006316964 +13 right_top_grid_pin_44_[0]:11 right_top_grid_pin_44_[0]:10 0.004513393 +14 right_top_grid_pin_44_[0]:13 right_top_grid_pin_44_[0]:12 0.0004107143 +15 right_top_grid_pin_44_[0]:14 right_top_grid_pin_44_[0]:13 0.0003035715 +16 right_top_grid_pin_44_[0]:15 right_top_grid_pin_44_[0]:14 0.02916072 +17 right_top_grid_pin_44_[0]:16 right_top_grid_pin_44_[0]:15 0.0009107143 + +*END + +*D_NET left_top_grid_pin_46_[0] 0.007646056 //LENGTH 55.885 LUMPCC 0.002977448 DR + +*CONN +*P left_top_grid_pin_46_[0] I *L 0.29796 *C 2.300 74.835 +*I mux_left_track_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 23.100 63.580 +*I mux_left_track_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 25.590 53.720 +*I mux_left_track_5\/mux_l1_in_4_:A0 I *L 0.001631 *C 9.375 58.820 +*N left_top_grid_pin_46_[0]:4 *C 9.375 58.820 +*N left_top_grid_pin_46_[0]:5 *C 9.200 58.820 +*N left_top_grid_pin_46_[0]:6 *C 9.230 58.850 +*N left_top_grid_pin_46_[0]:7 *C 9.245 59.160 +*N left_top_grid_pin_46_[0]:8 *C 25.590 53.720 +*N left_top_grid_pin_46_[0]:9 *C 25.760 53.720 +*N left_top_grid_pin_46_[0]:10 *C 25.760 53.765 +*N left_top_grid_pin_46_[0]:11 *C 25.760 58.422 +*N left_top_grid_pin_46_[0]:12 *C 25.753 58.480 +*N left_top_grid_pin_46_[0]:13 *C 23.062 63.580 +*N left_top_grid_pin_46_[0]:14 *C 21.205 63.580 +*N left_top_grid_pin_46_[0]:15 *C 21.160 63.535 +*N left_top_grid_pin_46_[0]:16 *C 21.160 58.538 +*N left_top_grid_pin_46_[0]:17 *C 21.160 58.480 +*N left_top_grid_pin_46_[0]:18 *C 9.660 58.480 +*N left_top_grid_pin_46_[0]:19 *C 9.660 59.153 +*N left_top_grid_pin_46_[0]:20 *C 9.660 59.218 +*N left_top_grid_pin_46_[0]:21 *C 9.660 74.415 +*N left_top_grid_pin_46_[0]:22 *C 9.615 74.460 +*N left_top_grid_pin_46_[0]:23 *C 2.345 74.460 +*N left_top_grid_pin_46_[0]:24 *C 2.300 74.505 + +*CAP +0 left_top_grid_pin_46_[0] 3.365301e-05 +1 mux_left_track_1\/mux_l2_in_2_:A1 1e-06 +2 mux_left_track_9\/mux_l2_in_2_:A0 1e-06 +3 mux_left_track_5\/mux_l1_in_4_:A0 1e-06 +4 left_top_grid_pin_46_[0]:4 6.115071e-05 +5 left_top_grid_pin_46_[0]:5 6.589048e-05 +6 left_top_grid_pin_46_[0]:6 3.745697e-05 +7 left_top_grid_pin_46_[0]:7 5.557302e-05 +8 left_top_grid_pin_46_[0]:8 5.864415e-05 +9 left_top_grid_pin_46_[0]:9 6.308623e-05 +10 left_top_grid_pin_46_[0]:10 0.0002804591 +11 left_top_grid_pin_46_[0]:11 0.0002804591 +12 left_top_grid_pin_46_[0]:12 0.0001370351 +13 left_top_grid_pin_46_[0]:13 0.000153797 +14 left_top_grid_pin_46_[0]:14 0.000153797 +15 left_top_grid_pin_46_[0]:15 0.0003124152 +16 left_top_grid_pin_46_[0]:16 0.0003124152 +17 left_top_grid_pin_46_[0]:17 0.0005349722 +18 left_top_grid_pin_46_[0]:18 0.0004582755 +19 left_top_grid_pin_46_[0]:19 6.033827e-05 +20 left_top_grid_pin_46_[0]:20 0.0005423169 +21 left_top_grid_pin_46_[0]:21 0.0005242008 +22 left_top_grid_pin_46_[0]:22 0.0002530091 +23 left_top_grid_pin_46_[0]:23 0.0002530091 +24 left_top_grid_pin_46_[0]:24 3.365301e-05 +25 left_top_grid_pin_46_[0]:23 chanx_left_in[9]:29 0.0002871369 +26 left_top_grid_pin_46_[0]:22 chanx_left_in[9]:28 0.0002871369 +27 left_top_grid_pin_46_[0]:21 left_top_grid_pin_49_[0] 2.371635e-05 +28 left_top_grid_pin_46_[0]:21 left_top_grid_pin_49_[0]:16 1.992959e-05 +29 left_top_grid_pin_46_[0]:21 left_top_grid_pin_49_[0]:17 0.0002997307 +30 left_top_grid_pin_46_[0]:20 left_top_grid_pin_49_[0]:16 0.0002997307 +31 left_top_grid_pin_46_[0]:20 left_top_grid_pin_49_[0]:20 2.371635e-05 +32 left_top_grid_pin_46_[0]:20 left_top_grid_pin_49_[0]:7 1.992959e-05 +33 left_top_grid_pin_46_[0]:20 left_top_grid_pin_49_[0]:5 2.188343e-05 +34 left_top_grid_pin_46_[0]:6 left_top_grid_pin_49_[0]:12 7.023509e-07 +35 left_top_grid_pin_46_[0]:7 left_top_grid_pin_49_[0]:13 7.023509e-07 +36 left_top_grid_pin_46_[0]:7 left_top_grid_pin_49_[0]:6 2.188343e-05 +37 left_top_grid_pin_46_[0]:12 mux_tree_tapbuf_size6_1_sram[0]:19 0.0001061685 +38 left_top_grid_pin_46_[0]:17 mux_tree_tapbuf_size6_1_sram[0]:19 0.0002297397 +39 left_top_grid_pin_46_[0]:17 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001061685 +40 left_top_grid_pin_46_[0]:18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0002297397 +41 left_top_grid_pin_46_[0]:21 optlc_net_123:7 0.0002092554 +42 left_top_grid_pin_46_[0]:21 optlc_net_123:14 2.608978e-06 +43 left_top_grid_pin_46_[0]:21 optlc_net_123:9 8.990518e-06 +44 left_top_grid_pin_46_[0]:20 optlc_net_123:8 0.0002092554 +45 left_top_grid_pin_46_[0]:20 optlc_net_123:15 2.608978e-06 +46 left_top_grid_pin_46_[0]:20 optlc_net_123:10 8.990518e-06 +47 left_top_grid_pin_46_[0]:6 optlc_net_123:19 1.206197e-07 +48 left_top_grid_pin_46_[0]:6 optlc_net_123:15 1.783074e-07 +49 left_top_grid_pin_46_[0]:6 optlc_net_123:10 9.44276e-08 +50 left_top_grid_pin_46_[0]:7 optlc_net_123:14 1.783074e-07 +51 left_top_grid_pin_46_[0]:7 optlc_net_123:9 9.44276e-08 +52 left_top_grid_pin_46_[0]:7 optlc_net_123:15 1.206197e-07 +53 left_top_grid_pin_46_[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001081095 +54 left_top_grid_pin_46_[0]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.000170359 +55 left_top_grid_pin_46_[0]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001081095 +56 left_top_grid_pin_46_[0]:18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.000170359 + +*RES +0 left_top_grid_pin_46_[0] left_top_grid_pin_46_[0]:24 0.0002946429 +1 left_top_grid_pin_46_[0]:23 left_top_grid_pin_46_[0]:22 0.006491072 +2 left_top_grid_pin_46_[0]:24 left_top_grid_pin_46_[0]:23 0.0045 +3 left_top_grid_pin_46_[0]:22 left_top_grid_pin_46_[0]:21 0.0045 +4 left_top_grid_pin_46_[0]:21 left_top_grid_pin_46_[0]:20 0.0135692 +5 left_top_grid_pin_46_[0]:20 left_top_grid_pin_46_[0]:19 0.00341 +6 left_top_grid_pin_46_[0]:20 left_top_grid_pin_46_[0]:7 0.0003705357 +7 left_top_grid_pin_46_[0]:19 left_top_grid_pin_46_[0]:18 0.0001053583 +8 left_top_grid_pin_46_[0]:5 left_top_grid_pin_46_[0]:4 9.51087e-05 +9 left_top_grid_pin_46_[0]:6 left_top_grid_pin_46_[0]:5 0.0045 +10 left_top_grid_pin_46_[0]:4 mux_left_track_5\/mux_l1_in_4_:A0 0.152 +11 left_top_grid_pin_46_[0]:11 left_top_grid_pin_46_[0]:10 0.004158482 +12 left_top_grid_pin_46_[0]:12 left_top_grid_pin_46_[0]:11 0.00341 +13 left_top_grid_pin_46_[0]:9 left_top_grid_pin_46_[0]:8 9.239131e-05 +14 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:9 0.0045 +15 left_top_grid_pin_46_[0]:8 mux_left_track_9\/mux_l2_in_2_:A0 0.152 +16 left_top_grid_pin_46_[0]:16 left_top_grid_pin_46_[0]:15 0.004462054 +17 left_top_grid_pin_46_[0]:17 left_top_grid_pin_46_[0]:16 0.00341 +18 left_top_grid_pin_46_[0]:17 left_top_grid_pin_46_[0]:12 0.0007194917 +19 left_top_grid_pin_46_[0]:14 left_top_grid_pin_46_[0]:13 0.001658482 +20 left_top_grid_pin_46_[0]:15 left_top_grid_pin_46_[0]:14 0.0045 +21 left_top_grid_pin_46_[0]:13 mux_left_track_1\/mux_l2_in_2_:A1 0.152 +22 left_top_grid_pin_46_[0]:7 left_top_grid_pin_46_[0]:6 0.00019375 +23 left_top_grid_pin_46_[0]:18 left_top_grid_pin_46_[0]:17 0.001801667 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[0] 0.01217349 //LENGTH 91.600 LUMPCC 0.001511967 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 22.845 60.860 +*I mux_left_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 22.440 52.750 +*I mux_left_track_5\/mux_l1_in_5_:S I *L 0.00357 *C 16.200 52.360 +*I mux_left_track_5\/mux_l1_in_6_:S I *L 0.00357 *C 8.280 47.430 +*I mux_left_track_5\/mux_l1_in_4_:S I *L 0.00357 *C 8.620 57.800 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 30.075 49.980 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 40.580 66.640 +*I mux_left_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 40.580 55.760 +*I mux_left_track_5\/mux_l1_in_3_:S I *L 0.00357 *C 24.940 50.615 +*N mux_tree_tapbuf_size14_1_sram[0]:9 *C 24.940 50.615 +*N mux_tree_tapbuf_size14_1_sram[0]:10 *C 40.580 55.760 +*N mux_tree_tapbuf_size14_1_sram[0]:11 *C 40.480 56.100 +*N mux_tree_tapbuf_size14_1_sram[0]:12 *C 40.543 66.640 +*N mux_tree_tapbuf_size14_1_sram[0]:13 *C 40.065 66.640 +*N mux_tree_tapbuf_size14_1_sram[0]:14 *C 40.020 66.595 +*N mux_tree_tapbuf_size14_1_sram[0]:15 *C 40.020 56.145 +*N mux_tree_tapbuf_size14_1_sram[0]:16 *C 40.020 56.100 +*N mux_tree_tapbuf_size14_1_sram[0]:17 *C 37.305 56.100 +*N mux_tree_tapbuf_size14_1_sram[0]:18 *C 37.260 56.055 +*N mux_tree_tapbuf_size14_1_sram[0]:19 *C 37.260 50.025 +*N mux_tree_tapbuf_size14_1_sram[0]:20 *C 37.215 49.980 +*N mux_tree_tapbuf_size14_1_sram[0]:21 *C 30.075 49.980 +*N mux_tree_tapbuf_size14_1_sram[0]:22 *C 27.140 49.980 +*N mux_tree_tapbuf_size14_1_sram[0]:23 *C 27.140 50.320 +*N mux_tree_tapbuf_size14_1_sram[0]:24 *C 24.940 50.320 +*N mux_tree_tapbuf_size14_1_sram[0]:25 *C 23.965 50.320 +*N mux_tree_tapbuf_size14_1_sram[0]:26 *C 23.920 50.365 +*N mux_tree_tapbuf_size14_1_sram[0]:27 *C 23.920 52.700 +*N mux_tree_tapbuf_size14_1_sram[0]:28 *C 23.505 52.700 +*N mux_tree_tapbuf_size14_1_sram[0]:29 *C 22.510 52.820 +*N mux_tree_tapbuf_size14_1_sram[0]:30 *C 22.470 52.680 +*N mux_tree_tapbuf_size14_1_sram[0]:31 *C 8.582 57.800 +*N mux_tree_tapbuf_size14_1_sram[0]:32 *C 4.185 57.800 +*N mux_tree_tapbuf_size14_1_sram[0]:33 *C 4.140 57.755 +*N mux_tree_tapbuf_size14_1_sram[0]:34 *C 4.140 51.000 +*N mux_tree_tapbuf_size14_1_sram[0]:35 *C 4.600 51.000 +*N mux_tree_tapbuf_size14_1_sram[0]:36 *C 4.600 47.645 +*N mux_tree_tapbuf_size14_1_sram[0]:37 *C 4.645 47.600 +*N mux_tree_tapbuf_size14_1_sram[0]:38 *C 8.280 47.430 +*N mux_tree_tapbuf_size14_1_sram[0]:39 *C 11.455 47.600 +*N mux_tree_tapbuf_size14_1_sram[0]:40 *C 11.500 47.645 +*N mux_tree_tapbuf_size14_1_sram[0]:41 *C 11.500 52.315 +*N mux_tree_tapbuf_size14_1_sram[0]:42 *C 11.545 52.360 +*N mux_tree_tapbuf_size14_1_sram[0]:43 *C 16.200 52.360 +*N mux_tree_tapbuf_size14_1_sram[0]:44 *C 22.440 52.360 +*N mux_tree_tapbuf_size14_1_sram[0]:45 *C 22.440 52.750 +*N mux_tree_tapbuf_size14_1_sram[0]:46 *C 22.540 53.040 +*N mux_tree_tapbuf_size14_1_sram[0]:47 *C 23.415 53.040 +*N mux_tree_tapbuf_size14_1_sram[0]:48 *C 23.460 53.055 +*N mux_tree_tapbuf_size14_1_sram[0]:49 *C 23.460 60.815 +*N mux_tree_tapbuf_size14_1_sram[0]:50 *C 23.415 60.860 +*N mux_tree_tapbuf_size14_1_sram[0]:51 *C 22.883 60.860 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_5\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_5\/mux_l1_in_5_:S 1e-06 +3 mux_left_track_5\/mux_l1_in_6_:S 1e-06 +4 mux_left_track_5\/mux_l1_in_4_:S 1e-06 +5 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +7 mux_left_track_5\/mux_l1_in_1_:S 1e-06 +8 mux_left_track_5\/mux_l1_in_3_:S 1e-06 +9 mux_tree_tapbuf_size14_1_sram[0]:9 6.123039e-05 +10 mux_tree_tapbuf_size14_1_sram[0]:10 5.850579e-05 +11 mux_tree_tapbuf_size14_1_sram[0]:11 7.033846e-05 +12 mux_tree_tapbuf_size14_1_sram[0]:12 6.371119e-05 +13 mux_tree_tapbuf_size14_1_sram[0]:13 6.371119e-05 +14 mux_tree_tapbuf_size14_1_sram[0]:14 0.0006091475 +15 mux_tree_tapbuf_size14_1_sram[0]:15 0.0006091475 +16 mux_tree_tapbuf_size14_1_sram[0]:16 0.0002967326 +17 mux_tree_tapbuf_size14_1_sram[0]:17 0.0002272255 +18 mux_tree_tapbuf_size14_1_sram[0]:18 0.0002809079 +19 mux_tree_tapbuf_size14_1_sram[0]:19 0.0002809079 +20 mux_tree_tapbuf_size14_1_sram[0]:20 0.0005091337 +21 mux_tree_tapbuf_size14_1_sram[0]:21 0.00073587 +22 mux_tree_tapbuf_size14_1_sram[0]:22 0.0002247974 +23 mux_tree_tapbuf_size14_1_sram[0]:23 0.0001940895 +24 mux_tree_tapbuf_size14_1_sram[0]:24 0.0002791259 +25 mux_tree_tapbuf_size14_1_sram[0]:25 8.232345e-05 +26 mux_tree_tapbuf_size14_1_sram[0]:26 0.0001744693 +27 mux_tree_tapbuf_size14_1_sram[0]:27 0.0002068911 +28 mux_tree_tapbuf_size14_1_sram[0]:28 7.168498e-05 +29 mux_tree_tapbuf_size14_1_sram[0]:29 6.515675e-06 +30 mux_tree_tapbuf_size14_1_sram[0]:30 6.519014e-06 +31 mux_tree_tapbuf_size14_1_sram[0]:31 0.0002286394 +32 mux_tree_tapbuf_size14_1_sram[0]:32 0.0002286394 +33 mux_tree_tapbuf_size14_1_sram[0]:33 0.0002957597 +34 mux_tree_tapbuf_size14_1_sram[0]:34 0.0003089407 +35 mux_tree_tapbuf_size14_1_sram[0]:35 0.0001617713 +36 mux_tree_tapbuf_size14_1_sram[0]:36 0.0001485903 +37 mux_tree_tapbuf_size14_1_sram[0]:37 0.000200056 +38 mux_tree_tapbuf_size14_1_sram[0]:38 0.0004335701 +39 mux_tree_tapbuf_size14_1_sram[0]:39 0.0002020319 +40 mux_tree_tapbuf_size14_1_sram[0]:40 0.0002799949 +41 mux_tree_tapbuf_size14_1_sram[0]:41 0.0002799949 +42 mux_tree_tapbuf_size14_1_sram[0]:42 0.000242919 +43 mux_tree_tapbuf_size14_1_sram[0]:43 0.0006697064 +44 mux_tree_tapbuf_size14_1_sram[0]:44 0.0004223135 +45 mux_tree_tapbuf_size14_1_sram[0]:45 8.155958e-05 +46 mux_tree_tapbuf_size14_1_sram[0]:46 0.0001142792 +47 mux_tree_tapbuf_size14_1_sram[0]:47 9.597769e-05 +48 mux_tree_tapbuf_size14_1_sram[0]:48 0.0005338906 +49 mux_tree_tapbuf_size14_1_sram[0]:49 0.0004946275 +50 mux_tree_tapbuf_size14_1_sram[0]:50 5.813873e-05 +51 mux_tree_tapbuf_size14_1_sram[0]:51 5.813873e-05 +52 mux_tree_tapbuf_size14_1_sram[0]:33 left_top_grid_pin_47_[0]:20 0.0001141965 +53 mux_tree_tapbuf_size14_1_sram[0]:42 left_top_grid_pin_47_[0]:16 0.0001245947 +54 mux_tree_tapbuf_size14_1_sram[0]:42 left_top_grid_pin_47_[0]:18 2.378268e-06 +55 mux_tree_tapbuf_size14_1_sram[0]:43 left_top_grid_pin_47_[0]:14 2.851665e-05 +56 mux_tree_tapbuf_size14_1_sram[0]:43 left_top_grid_pin_47_[0]:15 0.0001245947 +57 mux_tree_tapbuf_size14_1_sram[0]:43 left_top_grid_pin_47_[0]:16 3.547102e-05 +58 mux_tree_tapbuf_size14_1_sram[0]:43 left_top_grid_pin_47_[0]:17 2.378268e-06 +59 mux_tree_tapbuf_size14_1_sram[0]:44 left_top_grid_pin_47_[0]:13 2.851665e-05 +60 mux_tree_tapbuf_size14_1_sram[0]:44 left_top_grid_pin_47_[0]:15 3.547102e-05 +61 mux_tree_tapbuf_size14_1_sram[0]:34 left_top_grid_pin_47_[0]:19 0.0001141965 +62 mux_tree_tapbuf_size14_1_sram[0]:18 mux_tree_tapbuf_size8_3_sram[0]:5 0.0001707931 +63 mux_tree_tapbuf_size14_1_sram[0]:19 mux_tree_tapbuf_size8_3_sram[0]:6 0.0001707931 +64 mux_tree_tapbuf_size14_1_sram[0]:33 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.571694e-05 +65 mux_tree_tapbuf_size14_1_sram[0]:36 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.212501e-05 +66 mux_tree_tapbuf_size14_1_sram[0]:34 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.571694e-05 +67 mux_tree_tapbuf_size14_1_sram[0]:35 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.212501e-05 +68 mux_tree_tapbuf_size14_1_sram[0]:37 ropt_net_161:5 4.581848e-05 +69 mux_tree_tapbuf_size14_1_sram[0]:36 ropt_net_161:4 3.019059e-06 +70 mux_tree_tapbuf_size14_1_sram[0]:38 ropt_net_161:6 4.581848e-05 +71 mux_tree_tapbuf_size14_1_sram[0]:34 ropt_net_161:5 1.420341e-05 +72 mux_tree_tapbuf_size14_1_sram[0]:35 ropt_net_161:6 1.420341e-05 +73 mux_tree_tapbuf_size14_1_sram[0]:35 ropt_net_161:3 3.019059e-06 +74 mux_tree_tapbuf_size14_1_sram[0]:31 ropt_net_129:4 7.673333e-05 +75 mux_tree_tapbuf_size14_1_sram[0]:31 ropt_net_129:6 3.241711e-05 +76 mux_tree_tapbuf_size14_1_sram[0]:32 ropt_net_129:3 7.673333e-05 +77 mux_tree_tapbuf_size14_1_sram[0]:32 ropt_net_129:5 3.241711e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size14_1_sram[0]:51 0.152 +1 mux_tree_tapbuf_size14_1_sram[0]:31 mux_left_track_5\/mux_l1_in_4_:S 0.152 +2 mux_tree_tapbuf_size14_1_sram[0]:32 mux_tree_tapbuf_size14_1_sram[0]:31 0.00392634 +3 mux_tree_tapbuf_size14_1_sram[0]:33 mux_tree_tapbuf_size14_1_sram[0]:32 0.0045 +4 mux_tree_tapbuf_size14_1_sram[0]:37 mux_tree_tapbuf_size14_1_sram[0]:36 0.0045 +5 mux_tree_tapbuf_size14_1_sram[0]:36 mux_tree_tapbuf_size14_1_sram[0]:35 0.002995536 +6 mux_tree_tapbuf_size14_1_sram[0]:17 mux_tree_tapbuf_size14_1_sram[0]:16 0.002424107 +7 mux_tree_tapbuf_size14_1_sram[0]:18 mux_tree_tapbuf_size14_1_sram[0]:17 0.0045 +8 mux_tree_tapbuf_size14_1_sram[0]:20 mux_tree_tapbuf_size14_1_sram[0]:19 0.0045 +9 mux_tree_tapbuf_size14_1_sram[0]:19 mux_tree_tapbuf_size14_1_sram[0]:18 0.005383929 +10 mux_tree_tapbuf_size14_1_sram[0]:47 mux_tree_tapbuf_size14_1_sram[0]:46 0.00078125 +11 mux_tree_tapbuf_size14_1_sram[0]:48 mux_tree_tapbuf_size14_1_sram[0]:47 0.0045 +12 mux_tree_tapbuf_size14_1_sram[0]:48 mux_tree_tapbuf_size14_1_sram[0]:28 0.000221875 +13 mux_tree_tapbuf_size14_1_sram[0]:39 mux_tree_tapbuf_size14_1_sram[0]:38 0.002834822 +14 mux_tree_tapbuf_size14_1_sram[0]:40 mux_tree_tapbuf_size14_1_sram[0]:39 0.0045 +15 mux_tree_tapbuf_size14_1_sram[0]:42 mux_tree_tapbuf_size14_1_sram[0]:41 0.0045 +16 mux_tree_tapbuf_size14_1_sram[0]:41 mux_tree_tapbuf_size14_1_sram[0]:40 0.004169643 +17 mux_tree_tapbuf_size14_1_sram[0]:25 mux_tree_tapbuf_size14_1_sram[0]:24 0.0008705358 +18 mux_tree_tapbuf_size14_1_sram[0]:26 mux_tree_tapbuf_size14_1_sram[0]:25 0.0045 +19 mux_tree_tapbuf_size14_1_sram[0]:43 mux_left_track_5\/mux_l1_in_5_:S 0.152 +20 mux_tree_tapbuf_size14_1_sram[0]:43 mux_tree_tapbuf_size14_1_sram[0]:42 0.00415625 +21 mux_tree_tapbuf_size14_1_sram[0]:38 mux_left_track_5\/mux_l1_in_6_:S 0.152 +22 mux_tree_tapbuf_size14_1_sram[0]:38 mux_tree_tapbuf_size14_1_sram[0]:37 0.003245536 +23 mux_tree_tapbuf_size14_1_sram[0]:9 mux_left_track_5\/mux_l1_in_3_:S 0.152 +24 mux_tree_tapbuf_size14_1_sram[0]:45 mux_left_track_5\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size14_1_sram[0]:45 mux_tree_tapbuf_size14_1_sram[0]:44 0.0003482143 +26 mux_tree_tapbuf_size14_1_sram[0]:45 mux_tree_tapbuf_size14_1_sram[0]:30 6.250001e-05 +27 mux_tree_tapbuf_size14_1_sram[0]:45 mux_tree_tapbuf_size14_1_sram[0]:29 6.250001e-05 +28 mux_tree_tapbuf_size14_1_sram[0]:10 mux_left_track_5\/mux_l1_in_1_:S 0.152 +29 mux_tree_tapbuf_size14_1_sram[0]:16 mux_tree_tapbuf_size14_1_sram[0]:15 0.0045 +30 mux_tree_tapbuf_size14_1_sram[0]:16 mux_tree_tapbuf_size14_1_sram[0]:11 0.0004107143 +31 mux_tree_tapbuf_size14_1_sram[0]:15 mux_tree_tapbuf_size14_1_sram[0]:14 0.009330357 +32 mux_tree_tapbuf_size14_1_sram[0]:13 mux_tree_tapbuf_size14_1_sram[0]:12 0.0004263393 +33 mux_tree_tapbuf_size14_1_sram[0]:14 mux_tree_tapbuf_size14_1_sram[0]:13 0.0045 +34 mux_tree_tapbuf_size14_1_sram[0]:12 mux_left_track_5\/mux_l1_in_0_:S 0.152 +35 mux_tree_tapbuf_size14_1_sram[0]:21 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +36 mux_tree_tapbuf_size14_1_sram[0]:21 mux_tree_tapbuf_size14_1_sram[0]:20 0.006375 +37 mux_tree_tapbuf_size14_1_sram[0]:50 mux_tree_tapbuf_size14_1_sram[0]:49 0.0045 +38 mux_tree_tapbuf_size14_1_sram[0]:49 mux_tree_tapbuf_size14_1_sram[0]:48 0.006928571 +39 mux_tree_tapbuf_size14_1_sram[0]:51 mux_tree_tapbuf_size14_1_sram[0]:50 0.0004754465 +40 mux_tree_tapbuf_size14_1_sram[0]:44 mux_tree_tapbuf_size14_1_sram[0]:43 0.005571429 +41 mux_tree_tapbuf_size14_1_sram[0]:46 mux_tree_tapbuf_size14_1_sram[0]:45 0.0002589286 +42 mux_tree_tapbuf_size14_1_sram[0]:24 mux_tree_tapbuf_size14_1_sram[0]:23 0.001964286 +43 mux_tree_tapbuf_size14_1_sram[0]:24 mux_tree_tapbuf_size14_1_sram[0]:9 0.0001271552 +44 mux_tree_tapbuf_size14_1_sram[0]:23 mux_tree_tapbuf_size14_1_sram[0]:22 0.0003035715 +45 mux_tree_tapbuf_size14_1_sram[0]:22 mux_tree_tapbuf_size14_1_sram[0]:21 0.002620535 +46 mux_tree_tapbuf_size14_1_sram[0]:11 mux_tree_tapbuf_size14_1_sram[0]:10 0.0003035715 +47 mux_tree_tapbuf_size14_1_sram[0]:34 mux_tree_tapbuf_size14_1_sram[0]:33 0.00603125 +48 mux_tree_tapbuf_size14_1_sram[0]:35 mux_tree_tapbuf_size14_1_sram[0]:34 0.0004107143 +49 mux_tree_tapbuf_size14_1_sram[0]:28 mux_tree_tapbuf_size14_1_sram[0]:27 0.0003705357 +50 mux_tree_tapbuf_size14_1_sram[0]:27 mux_tree_tapbuf_size14_1_sram[0]:26 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[0] 0.001295534 //LENGTH 9.135 LUMPCC 0.0003653862 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 101.965 42.160 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 100.180 40.120 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 102.755 37.060 +*N mux_tree_tapbuf_size4_0_sram[0]:3 *C 102.755 37.060 +*N mux_tree_tapbuf_size4_0_sram[0]:4 *C 102.580 37.060 +*N mux_tree_tapbuf_size4_0_sram[0]:5 *C 102.580 37.105 +*N mux_tree_tapbuf_size4_0_sram[0]:6 *C 102.580 40.120 +*N mux_tree_tapbuf_size4_0_sram[0]:7 *C 100.218 40.120 +*N mux_tree_tapbuf_size4_0_sram[0]:8 *C 102.075 40.120 +*N mux_tree_tapbuf_size4_0_sram[0]:9 *C 102.120 40.120 +*N mux_tree_tapbuf_size4_0_sram[0]:10 *C 102.120 42.115 +*N mux_tree_tapbuf_size4_0_sram[0]:11 *C 102.120 42.160 +*N mux_tree_tapbuf_size4_0_sram[0]:12 *C 101.965 42.160 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size4_0_sram[0]:3 4.942756e-05 +4 mux_tree_tapbuf_size4_0_sram[0]:4 5.495459e-05 +5 mux_tree_tapbuf_size4_0_sram[0]:5 0.0001368236 +6 mux_tree_tapbuf_size4_0_sram[0]:6 0.0001694334 +7 mux_tree_tapbuf_size4_0_sram[0]:7 0.0001255679 +8 mux_tree_tapbuf_size4_0_sram[0]:8 0.0001255679 +9 mux_tree_tapbuf_size4_0_sram[0]:9 9.760755e-05 +10 mux_tree_tapbuf_size4_0_sram[0]:10 6.499776e-05 +11 mux_tree_tapbuf_size4_0_sram[0]:11 5.34777e-05 +12 mux_tree_tapbuf_size4_0_sram[0]:12 4.928978e-05 +13 mux_tree_tapbuf_size4_0_sram[0]:5 prog_clk[0]:251 3.55575e-05 +14 mux_tree_tapbuf_size4_0_sram[0]:10 prog_clk[0]:252 6.17402e-05 +15 mux_tree_tapbuf_size4_0_sram[0]:9 prog_clk[0]:251 6.17402e-05 +16 mux_tree_tapbuf_size4_0_sram[0]:6 prog_clk[0]:252 3.55575e-05 +17 mux_tree_tapbuf_size4_0_sram[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.411082e-05 +18 mux_tree_tapbuf_size4_0_sram[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.925783e-05 +19 mux_tree_tapbuf_size4_0_sram[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.202673e-05 +20 mux_tree_tapbuf_size4_0_sram[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.925783e-05 +21 mux_tree_tapbuf_size4_0_sram[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.202673e-05 +22 mux_tree_tapbuf_size4_0_sram[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.411082e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_0_sram[0]:12 0.152 +1 mux_tree_tapbuf_size4_0_sram[0]:4 mux_tree_tapbuf_size4_0_sram[0]:3 9.51087e-05 +2 mux_tree_tapbuf_size4_0_sram[0]:5 mux_tree_tapbuf_size4_0_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size4_0_sram[0]:3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size4_0_sram[0]:11 mux_tree_tapbuf_size4_0_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size4_0_sram[0]:10 mux_tree_tapbuf_size4_0_sram[0]:9 0.00178125 +6 mux_tree_tapbuf_size4_0_sram[0]:12 mux_tree_tapbuf_size4_0_sram[0]:11 8.423914e-05 +7 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:7 0.001658482 +8 mux_tree_tapbuf_size4_0_sram[0]:9 mux_tree_tapbuf_size4_0_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size4_0_sram[0]:9 mux_tree_tapbuf_size4_0_sram[0]:6 0.0004107143 +10 mux_tree_tapbuf_size4_0_sram[0]:7 mux_top_track_8\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size4_0_sram[0]:6 mux_tree_tapbuf_size4_0_sram[0]:5 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[1] 0.002380132 //LENGTH 17.365 LUMPCC 0.0002343522 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.605 55.760 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 74.420 53.040 +*I mux_top_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 73.500 50.320 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 73.300 60.860 +*N mux_tree_tapbuf_size7_1_sram[1]:4 *C 73.263 60.860 +*N mux_tree_tapbuf_size7_1_sram[1]:5 *C 72.220 60.860 +*N mux_tree_tapbuf_size7_1_sram[1]:6 *C 72.220 60.520 +*N mux_tree_tapbuf_size7_1_sram[1]:7 *C 72.220 60.475 +*N mux_tree_tapbuf_size7_1_sram[1]:8 *C 73.463 50.320 +*N mux_tree_tapbuf_size7_1_sram[1]:9 *C 72.265 50.320 +*N mux_tree_tapbuf_size7_1_sram[1]:10 *C 72.220 50.365 +*N mux_tree_tapbuf_size7_1_sram[1]:11 *C 74.383 53.040 +*N mux_tree_tapbuf_size7_1_sram[1]:12 *C 72.265 53.040 +*N mux_tree_tapbuf_size7_1_sram[1]:13 *C 72.220 53.040 +*N mux_tree_tapbuf_size7_1_sram[1]:14 *C 72.220 55.760 +*N mux_tree_tapbuf_size7_1_sram[1]:15 *C 72.175 55.760 +*N mux_tree_tapbuf_size7_1_sram[1]:16 *C 71.642 55.760 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_1_sram[1]:4 8.745943e-05 +5 mux_tree_tapbuf_size7_1_sram[1]:5 0.0001189083 +6 mux_tree_tapbuf_size7_1_sram[1]:6 6.890639e-05 +7 mux_tree_tapbuf_size7_1_sram[1]:7 0.0003027672 +8 mux_tree_tapbuf_size7_1_sram[1]:8 0.0001453735 +9 mux_tree_tapbuf_size7_1_sram[1]:9 0.0001453735 +10 mux_tree_tapbuf_size7_1_sram[1]:10 0.0001587275 +11 mux_tree_tapbuf_size7_1_sram[1]:11 8.548034e-05 +12 mux_tree_tapbuf_size7_1_sram[1]:12 8.548034e-05 +13 mux_tree_tapbuf_size7_1_sram[1]:13 0.0003405405 +14 mux_tree_tapbuf_size7_1_sram[1]:14 0.0004835796 +15 mux_tree_tapbuf_size7_1_sram[1]:15 5.959166e-05 +16 mux_tree_tapbuf_size7_1_sram[1]:16 5.959166e-05 +17 mux_tree_tapbuf_size7_1_sram[1]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.567012e-05 +18 mux_tree_tapbuf_size7_1_sram[1]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.567012e-05 +19 mux_tree_tapbuf_size7_1_sram[1]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.150598e-05 +20 mux_tree_tapbuf_size7_1_sram[1]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.150598e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_1_sram[1]:4 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_1_sram[1]:6 mux_tree_tapbuf_size7_1_sram[1]:5 0.0003035715 +3 mux_tree_tapbuf_size7_1_sram[1]:7 mux_tree_tapbuf_size7_1_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size7_1_sram[1]:12 mux_tree_tapbuf_size7_1_sram[1]:11 0.001890625 +5 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:10 0.002388393 +7 mux_tree_tapbuf_size7_1_sram[1]:11 mux_top_track_4\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:14 0.0045 +9 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:13 0.002428571 +10 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:7 0.004209822 +11 mux_tree_tapbuf_size7_1_sram[1]:16 mux_tree_tapbuf_size7_1_sram[1]:15 0.0004754464 +12 mux_tree_tapbuf_size7_1_sram[1]:9 mux_tree_tapbuf_size7_1_sram[1]:8 0.001069196 +13 mux_tree_tapbuf_size7_1_sram[1]:10 mux_tree_tapbuf_size7_1_sram[1]:9 0.0045 +14 mux_tree_tapbuf_size7_1_sram[1]:8 mux_top_track_4\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size7_1_sram[1]:5 mux_tree_tapbuf_size7_1_sram[1]:4 0.0009308036 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_1_ccff_tail[0] 0.0007265702 //LENGTH 5.240 LUMPCC 0.000141982 DR + +*CONN +*I mem_top_track_4\/FTB_6__32:X O *L 0 *C 81.655 58.140 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 83.435 55.420 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 *C 83.435 55.420 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 *C 83.260 55.420 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 *C 83.260 55.465 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 *C 83.260 58.095 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 *C 83.215 58.140 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 *C 81.693 58.140 + +*CAP +0 mem_top_track_4\/FTB_6__32:X 1e-06 +1 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 5.054817e-05 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 5.610298e-05 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.0001703256 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0001703256 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 6.76429e-05 +7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 6.76429e-05 +8 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 chanx_left_in[12]:18 7.099098e-05 +9 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 chanx_left_in[12]:17 7.099098e-05 + +*RES +0 mem_top_track_4\/FTB_6__32:X mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 0.001359375 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 9.510871e-05 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[1] 0.009740012 //LENGTH 64.077 LUMPCC 0.002598179 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 97.365 50.320 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 117.475 47.940 +*I mux_right_track_8\/mux_l2_in_2_:S I *L 0.00357 *C 130.740 47.260 +*I mux_right_track_8\/mux_l2_in_3_:S I *L 0.00357 *C 126.600 47.310 +*I mux_right_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 116.740 63.240 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 95.120 56.440 +*N mux_tree_tapbuf_size8_1_sram[1]:6 *C 95.157 56.440 +*N mux_tree_tapbuf_size8_1_sram[1]:7 *C 97.015 56.440 +*N mux_tree_tapbuf_size8_1_sram[1]:8 *C 97.060 56.395 +*N mux_tree_tapbuf_size8_1_sram[1]:9 *C 116.778 63.240 +*N mux_tree_tapbuf_size8_1_sram[1]:10 *C 117.715 63.240 +*N mux_tree_tapbuf_size8_1_sram[1]:11 *C 117.760 63.195 +*N mux_tree_tapbuf_size8_1_sram[1]:12 *C 126.600 47.310 +*N mux_tree_tapbuf_size8_1_sram[1]:13 *C 130.740 47.260 +*N mux_tree_tapbuf_size8_1_sram[1]:14 *C 130.640 47.600 +*N mux_tree_tapbuf_size8_1_sram[1]:15 *C 126.600 47.600 +*N mux_tree_tapbuf_size8_1_sram[1]:16 *C 126.040 47.600 +*N mux_tree_tapbuf_size8_1_sram[1]:17 *C 126.040 47.940 +*N mux_tree_tapbuf_size8_1_sram[1]:18 *C 117.513 47.940 +*N mux_tree_tapbuf_size8_1_sram[1]:19 *C 117.300 47.940 +*N mux_tree_tapbuf_size8_1_sram[1]:20 *C 117.300 47.985 +*N mux_tree_tapbuf_size8_1_sram[1]:21 *C 117.300 49.980 +*N mux_tree_tapbuf_size8_1_sram[1]:22 *C 117.760 49.980 +*N mux_tree_tapbuf_size8_1_sram[1]:23 *C 117.760 51.680 +*N mux_tree_tapbuf_size8_1_sram[1]:24 *C 117.753 51.680 +*N mux_tree_tapbuf_size8_1_sram[1]:25 *C 108.560 51.680 +*N mux_tree_tapbuf_size8_1_sram[1]:26 *C 108.560 51.000 +*N mux_tree_tapbuf_size8_1_sram[1]:27 *C 97.068 51.000 +*N mux_tree_tapbuf_size8_1_sram[1]:28 *C 97.060 51.000 +*N mux_tree_tapbuf_size8_1_sram[1]:29 *C 97.060 50.365 +*N mux_tree_tapbuf_size8_1_sram[1]:30 *C 97.060 50.320 +*N mux_tree_tapbuf_size8_1_sram[1]:31 *C 97.365 50.320 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_8\/mux_l2_in_2_:S 1e-06 +3 mux_right_track_8\/mux_l2_in_3_:S 1e-06 +4 mux_right_track_8\/mux_l2_in_1_:S 1e-06 +5 mux_right_track_8\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_1_sram[1]:6 0.0001119781 +7 mux_tree_tapbuf_size8_1_sram[1]:7 0.0001119781 +8 mux_tree_tapbuf_size8_1_sram[1]:8 0.0002965104 +9 mux_tree_tapbuf_size8_1_sram[1]:9 8.632719e-05 +10 mux_tree_tapbuf_size8_1_sram[1]:10 8.632719e-05 +11 mux_tree_tapbuf_size8_1_sram[1]:11 0.0006255808 +12 mux_tree_tapbuf_size8_1_sram[1]:12 5.944275e-05 +13 mux_tree_tapbuf_size8_1_sram[1]:13 5.844803e-05 +14 mux_tree_tapbuf_size8_1_sram[1]:14 0.0003314565 +15 mux_tree_tapbuf_size8_1_sram[1]:15 0.0003756093 +16 mux_tree_tapbuf_size8_1_sram[1]:16 6.862989e-05 +17 mux_tree_tapbuf_size8_1_sram[1]:17 0.0005524164 +18 mux_tree_tapbuf_size8_1_sram[1]:18 0.000545543 +19 mux_tree_tapbuf_size8_1_sram[1]:19 4.982472e-05 +20 mux_tree_tapbuf_size8_1_sram[1]:20 0.0001258877 +21 mux_tree_tapbuf_size8_1_sram[1]:21 0.0001502658 +22 mux_tree_tapbuf_size8_1_sram[1]:22 0.0001180478 +23 mux_tree_tapbuf_size8_1_sram[1]:23 0.0007545691 +24 mux_tree_tapbuf_size8_1_sram[1]:24 0.0002783425 +25 mux_tree_tapbuf_size8_1_sram[1]:25 0.0003300948 +26 mux_tree_tapbuf_size8_1_sram[1]:26 0.000767458 +27 mux_tree_tapbuf_size8_1_sram[1]:27 0.0007157057 +28 mux_tree_tapbuf_size8_1_sram[1]:28 0.0003779864 +29 mux_tree_tapbuf_size8_1_sram[1]:29 4.638965e-05 +30 mux_tree_tapbuf_size8_1_sram[1]:30 5.771761e-05 +31 mux_tree_tapbuf_size8_1_sram[1]:31 5.329612e-05 +32 mux_tree_tapbuf_size8_1_sram[1]:27 chanx_right_in[18]:28 0.0002923552 +33 mux_tree_tapbuf_size8_1_sram[1]:21 chanx_right_in[18]:28 5.753399e-06 +34 mux_tree_tapbuf_size8_1_sram[1]:22 chanx_right_in[18] 5.753399e-06 +35 mux_tree_tapbuf_size8_1_sram[1]:26 chanx_right_in[18] 0.0002923552 +36 mux_tree_tapbuf_size8_1_sram[1]:24 chanx_right_in[0]:15 0.0003330982 +37 mux_tree_tapbuf_size8_1_sram[1]:25 chanx_right_in[0]:14 0.0003330982 +38 mux_tree_tapbuf_size8_1_sram[1]:28 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 1.897301e-07 +39 mux_tree_tapbuf_size8_1_sram[1]:27 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 9.073714e-05 +40 mux_tree_tapbuf_size8_1_sram[1]:8 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 1.897301e-07 +41 mux_tree_tapbuf_size8_1_sram[1]:26 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 9.073714e-05 +42 mux_tree_tapbuf_size8_1_sram[1]:28 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.176853e-06 +43 mux_tree_tapbuf_size8_1_sram[1]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.406537e-05 +44 mux_tree_tapbuf_size8_1_sram[1]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.176853e-06 +45 mux_tree_tapbuf_size8_1_sram[1]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.406537e-05 +46 mux_tree_tapbuf_size8_1_sram[1]:24 optlc_net_124:33 7.290413e-05 +47 mux_tree_tapbuf_size8_1_sram[1]:24 optlc_net_124:20 0.0004340464 +48 mux_tree_tapbuf_size8_1_sram[1]:15 optlc_net_124:16 1.762777e-06 +49 mux_tree_tapbuf_size8_1_sram[1]:14 optlc_net_124:15 1.762777e-06 +50 mux_tree_tapbuf_size8_1_sram[1]:25 optlc_net_124:32 7.290413e-05 +51 mux_tree_tapbuf_size8_1_sram[1]:25 optlc_net_124:33 0.0004340464 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_1_sram[1]:31 0.152 +1 mux_tree_tapbuf_size8_1_sram[1]:9 mux_right_track_8\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[1]:10 mux_tree_tapbuf_size8_1_sram[1]:9 0.0008370536 +3 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:18 0.0001154891 +5 mux_tree_tapbuf_size8_1_sram[1]:20 mux_tree_tapbuf_size8_1_sram[1]:19 0.0045 +6 mux_tree_tapbuf_size8_1_sram[1]:12 mux_right_track_8\/mux_l2_in_3_:S 0.152 +7 mux_tree_tapbuf_size8_1_sram[1]:28 mux_tree_tapbuf_size8_1_sram[1]:27 0.00341 +8 mux_tree_tapbuf_size8_1_sram[1]:28 mux_tree_tapbuf_size8_1_sram[1]:8 0.004816964 +9 mux_tree_tapbuf_size8_1_sram[1]:27 mux_tree_tapbuf_size8_1_sram[1]:26 0.001800492 +10 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:22 0.001517857 +11 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:11 0.01028125 +12 mux_tree_tapbuf_size8_1_sram[1]:24 mux_tree_tapbuf_size8_1_sram[1]:23 0.00341 +13 mux_tree_tapbuf_size8_1_sram[1]:18 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size8_1_sram[1]:18 mux_tree_tapbuf_size8_1_sram[1]:17 0.00761384 +15 mux_tree_tapbuf_size8_1_sram[1]:30 mux_tree_tapbuf_size8_1_sram[1]:29 0.0045 +16 mux_tree_tapbuf_size8_1_sram[1]:29 mux_tree_tapbuf_size8_1_sram[1]:28 0.0005669643 +17 mux_tree_tapbuf_size8_1_sram[1]:31 mux_tree_tapbuf_size8_1_sram[1]:30 0.0001657609 +18 mux_tree_tapbuf_size8_1_sram[1]:13 mux_right_track_8\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size8_1_sram[1]:7 mux_tree_tapbuf_size8_1_sram[1]:6 0.001658482 +20 mux_tree_tapbuf_size8_1_sram[1]:8 mux_tree_tapbuf_size8_1_sram[1]:7 0.0045 +21 mux_tree_tapbuf_size8_1_sram[1]:6 mux_right_track_8\/mux_l2_in_0_:S 0.152 +22 mux_tree_tapbuf_size8_1_sram[1]:17 mux_tree_tapbuf_size8_1_sram[1]:16 0.0003035715 +23 mux_tree_tapbuf_size8_1_sram[1]:16 mux_tree_tapbuf_size8_1_sram[1]:15 0.0005000001 +24 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:14 0.003607143 +25 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:12 0.000125 +26 mux_tree_tapbuf_size8_1_sram[1]:14 mux_tree_tapbuf_size8_1_sram[1]:13 0.0003035715 +27 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:20 0.00178125 +28 mux_tree_tapbuf_size8_1_sram[1]:22 mux_tree_tapbuf_size8_1_sram[1]:21 0.0004107143 +29 mux_tree_tapbuf_size8_1_sram[1]:26 mux_tree_tapbuf_size8_1_sram[1]:25 0.0001065333 +30 mux_tree_tapbuf_size8_1_sram[1]:25 mux_tree_tapbuf_size8_1_sram[1]:24 0.001440158 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001483709 //LENGTH 11.690 LUMPCC 0.0003351533 DR + +*CONN +*I mux_right_track_8\/mux_l4_in_0_:X O *L 0 *C 128.625 37.060 +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 136.400 33.830 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 136.400 33.830 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 133.445 34.000 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 133.400 34.045 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 133.400 37.015 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 133.355 37.060 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 128.662 37.060 + +*CAP +0 mux_right_track_8\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001960028 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001682396 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001812134 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001812134 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002099431 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002099431 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_left_in[8]:6 0.0001206877 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chanx_left_in[8]:7 0.0001206877 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 ropt_net_148:4 1.799545e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 ropt_net_148:2 2.889348e-05 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 ropt_net_148:5 1.799545e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 ropt_net_148:3 2.889348e-05 + +*RES +0 mux_right_track_8\/mux_l4_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002638393 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002651786 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.004189732 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008727846 //LENGTH 5.785 LUMPCC 0.0001455025 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_0_:X O *L 0 *C 60.545 89.080 +*I mux_top_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 65.420 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 65.383 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 62.560 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 62.560 89.080 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 60.583 89.080 + +*CAP +0 mux_top_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001736365 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002007325 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001890045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001619086 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 7.275127e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 7.275127e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001765625 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.00252009 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006558644 //LENGTH 4.500 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_1_:X O *L 0 *C 93.205 36.040 +*I mux_right_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 91.695 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 91.695 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 33.705 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.000 35.995 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 92.045 36.040 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 93.168 36.040 + +*CAP +0 mux_right_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.678515e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.112805e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001597978 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001597978 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001081778 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001081778 + +*RES +0 mux_right_track_16\/mux_l1_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001002232 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001657609 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001094423 //LENGTH 7.485 LUMPCC 0.0003774621 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_3_:X O *L 0 *C 35.245 36.720 +*I mux_left_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 38.930 33.660 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 38.893 33.660 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 35.465 33.660 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 35.420 33.705 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 35.420 36.675 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 35.420 36.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 35.245 36.720 + +*CAP +0 mux_left_track_17\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001549552 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001549552 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001487615 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001487615 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.389373e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.363413e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_left_in[8]:21 0.0001390061 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 chanx_left_in[8]:20 0.0001390061 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_5_sram[0]:20 1.384689e-06 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_5_sram[0]:21 1.384689e-06 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_5_sram[0]:22 2.133106e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_5_sram[0]:25 9.34838e-06 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size7_5_sram[0]:23 1.766075e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_5_sram[0]:25 2.133106e-05 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_5_sram[0]:26 9.34838e-06 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size7_5_sram[0]:24 1.766075e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_3_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002651786 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003060268 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_17\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0] 0.006815962 //LENGTH 47.210 LUMPCC 0.003195647 DR + +*CONN +*I mux_top_track_10\/mux_l3_in_0_:X O *L 0 *C 119.315 61.200 +*I mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 109.195 96.720 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 109.233 96.618 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 109.895 96.560 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 109.940 96.515 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 109.940 92.538 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 109.943 92.480 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 110.385 92.480 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 110.400 92.473 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 110.400 61.208 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 110.420 61.200 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 119.133 61.200 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 119.140 61.200 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 119.140 61.200 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 119.315 61.200 + +*CAP +0 mux_top_track_10\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.787973e-05 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.787973e-05 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002352388 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002352388 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.460653e-05 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.460653e-05 +8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00122773 +9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00122773 +10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001563225 +11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001563225 +12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.772295e-05 +13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 5.747922e-05 +14 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 5.955677e-05 +15 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 chanx_left_in[9]:15 0.0005090669 +16 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 chanx_left_in[9]:16 0.0005090669 +17 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 chanx_left_in[12]:13 0.0005090669 +18 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 chanx_left_in[12]:14 0.0005090669 +19 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chanx_right_in[0]:9 1.983668e-05 +20 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chanx_right_in[0]:13 0.0002678976 +21 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[0]:8 1.983668e-05 +22 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[0]:12 0.0002678976 +23 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size9_0_sram[3]:9 0.0002919552 +24 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size9_0_sram[3]:8 0.0002919552 + +*RES +0 mux_top_track_10\/mux_l3_in_0_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 9.51087e-05 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.00341 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.001364958 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00341 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.004898183 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.499219e-05 +8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003551339 +10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005915179 +12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001365099 //LENGTH 10.405 LUMPCC 0.0004907436 DR + +*CONN +*I mux_top_track_28\/mux_l1_in_0_:X O *L 0 *C 63.305 23.120 +*I mux_top_track_28\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.960 30.940 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.922 30.940 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.985 30.940 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.940 30.895 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.940 23.165 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.895 23.120 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 63.343 23.120 + +*CAP +0 mux_top_track_28\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_28\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001035261 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001035261 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002767621 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002767621 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.588958e-05 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.588958e-05 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:405 0.0001243134 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:406 1.229106e-05 +10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:374 0.0001243134 +11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:405 1.229106e-05 +12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[1]:6 6.194694e-05 +13 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[1]:5 6.194694e-05 +14 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 4.682044e-05 +15 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 4.682044e-05 + +*RES +0 mux_top_track_28\/mux_l1_in_0_:X mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_28\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001089202 //LENGTH 8.105 LUMPCC 0.0001538275 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_0_:X O *L 0 *C 119.885 68.680 +*I mux_right_track_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 127.060 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 127.023 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 126.500 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 126.500 68.680 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 119.922 68.680 + +*CAP +0 mux_right_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.696819e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.013935e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0004197193 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003965482 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size9_0_sram[2]:8 2.018259e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size9_0_sram[2]:13 4.508277e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size9_0_sram[2]:16 1.164837e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size9_0_sram[2]:7 1.164837e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size9_0_sram[2]:13 2.018259e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size9_0_sram[2]:14 4.508277e-05 + +*RES +0 mux_right_track_0\/mux_l3_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_0\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005872768 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003035715 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004665179 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0] 0.000806043 //LENGTH 6.155 LUMPCC 0.0001680783 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_1_:X O *L 0 *C 109.305 57.800 +*I mux_right_track_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 107.860 53.720 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 107.898 53.720 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 108.975 53.720 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 109.020 53.765 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 109.020 57.755 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 109.020 57.800 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 109.305 57.800 + +*CAP +0 mux_right_track_4\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 9.144421e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 9.144421e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0001647587 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0001647587 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 6.129252e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 6.226631e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 optlc_net_124:35 1.942037e-06 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 optlc_net_124:40 3.347237e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 optlc_net_124:34 1.942037e-06 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 optlc_net_124:39 3.347237e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 4.862472e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 4.862472e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0001548913 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0035625 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0009620536 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_right_track_4\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008195606 //LENGTH 5.750 LUMPCC 0.0001841623 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_2_:X O *L 0 *C 23.285 53.720 +*I mux_left_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 21.525 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 21.562 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.495 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 22.540 50.705 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 22.540 53.675 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 22.585 53.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 23.248 53.720 + +*CAP +0 mux_left_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.020239e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.020239e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001697711 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001697711 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.672564e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.672564e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size14_1_sram[1]:16 4.490471e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_1_sram[1]:17 4.490471e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.717645e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.717645e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008325894 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002651786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005915179 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006926479 //LENGTH 5.445 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_2_:X O *L 0 *C 34.785 66.980 +*I mux_left_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 37.260 69.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 37.223 69.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 35.465 69.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 35.420 68.975 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 35.420 67.025 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 35.375 66.980 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 34.823 66.980 + +*CAP +0 mux_left_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001466762 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001466762 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001271162 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001271162 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.153151e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.153151e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741071 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001569197 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET ropt_net_156 0.001435207 //LENGTH 9.485 LUMPCC 0.0004533285 DR + +*CONN +*I ropt_mt_inst_753:X O *L 0 *C 11.625 38.760 +*I ropt_mt_inst_782:A I *L 0.001767 *C 3.220 39.440 +*N ropt_net_156:2 *C 3.220 39.440 +*N ropt_net_156:3 *C 3.220 38.760 +*N ropt_net_156:4 *C 11.588 38.760 + +*CAP +0 ropt_mt_inst_753:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_156:2 7.229029e-05 +3 ropt_net_156:3 0.0004760149 +4 ropt_net_156:4 0.0004315732 +5 ropt_net_156:4 chanx_left_out[0]:7 2.491338e-05 +6 ropt_net_156:4 chanx_left_out[0]:8 0.0002017509 +7 ropt_net_156:3 chanx_left_out[0]:6 2.491338e-05 +8 ropt_net_156:3 chanx_left_out[0]:7 0.0002017509 + +*RES +0 ropt_mt_inst_753:X ropt_net_156:4 0.152 +1 ropt_net_156:4 ropt_net_156:3 0.007470982 +2 ropt_net_156:2 ropt_mt_inst_782:A 0.152 +3 ropt_net_156:3 ropt_net_156:2 0.0006071429 + +*END + +*D_NET ropt_net_148 0.001056312 //LENGTH 7.990 LUMPCC 0.0004598165 DR + +*CONN +*I FTB_24__23:X O *L 0 *C 132.480 41.480 +*I ropt_mt_inst_771:A I *L 0.001766 *C 134.780 36.720 +*N ropt_net_148:2 *C 134.743 36.720 +*N ropt_net_148:3 *C 132.985 36.720 +*N ropt_net_148:4 *C 132.940 36.765 +*N ropt_net_148:5 *C 132.940 41.435 +*N ropt_net_148:6 *C 132.895 41.480 +*N ropt_net_148:7 *C 132.518 41.480 + +*CAP +0 FTB_24__23:X 1e-06 +1 ropt_mt_inst_771:A 1e-06 +2 ropt_net_148:2 7.771764e-05 +3 ropt_net_148:3 7.771764e-05 +4 ropt_net_148:4 0.0001697157 +5 ropt_net_148:5 0.0001697157 +6 ropt_net_148:6 4.981428e-05 +7 ropt_net_148:7 4.981428e-05 +8 ropt_net_148:4 chanx_left_in[9]:8 0.0001373678 +9 ropt_net_148:5 chanx_left_in[9]:9 0.0001373678 +10 ropt_net_148:2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.889348e-05 +11 ropt_net_148:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:7 2.889348e-05 +12 ropt_net_148:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.799545e-05 +13 ropt_net_148:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.799545e-05 +14 ropt_net_148:2 ropt_net_147:8 4.494977e-05 +15 ropt_net_148:3 ropt_net_147:9 4.494977e-05 +16 ropt_net_148:4 ropt_net_147:7 7.017242e-07 +17 ropt_net_148:5 ropt_net_147:6 7.017242e-07 + +*RES +0 FTB_24__23:X ropt_net_148:7 0.152 +1 ropt_net_148:2 ropt_mt_inst_771:A 0.152 +2 ropt_net_148:3 ropt_net_148:2 0.001569196 +3 ropt_net_148:4 ropt_net_148:3 0.0045 +4 ropt_net_148:6 ropt_net_148:5 0.0045 +5 ropt_net_148:5 ropt_net_148:4 0.004169643 +6 ropt_net_148:7 ropt_net_148:6 0.0003370536 + +*END + +*D_NET ropt_net_165 0.001317389 //LENGTH 10.475 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 138.655 44.200 +*I ropt_mt_inst_791:A I *L 0.001767 *C 134.780 42.160 +*N ropt_net_165:2 *C 134.743 42.160 +*N ropt_net_165:3 *C 133.905 42.160 +*N ropt_net_165:4 *C 133.860 42.115 +*N ropt_net_165:5 *C 133.860 41.525 +*N ropt_net_165:6 *C 133.905 41.480 +*N ropt_net_165:7 *C 138.415 41.480 +*N ropt_net_165:8 *C 138.460 41.525 +*N ropt_net_165:9 *C 138.460 44.155 +*N ropt_net_165:10 *C 138.460 44.200 +*N ropt_net_165:11 *C 138.655 44.200 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_165:2 7.147981e-05 +3 ropt_net_165:3 7.147981e-05 +4 ropt_net_165:4 5.941296e-05 +5 ropt_net_165:5 5.941296e-05 +6 ropt_net_165:6 0.0003010445 +7 ropt_net_165:7 0.0003010445 +8 ropt_net_165:8 0.0001693596 +9 ropt_net_165:9 0.0001693596 +10 ropt_net_165:10 5.478899e-05 +11 ropt_net_165:11 5.800574e-05 + +*RES +0 ropt_mt_inst_770:X ropt_net_165:11 0.152 +1 ropt_net_165:2 ropt_mt_inst_791:A 0.152 +2 ropt_net_165:3 ropt_net_165:2 0.0007477679 +3 ropt_net_165:4 ropt_net_165:3 0.0045 +4 ropt_net_165:6 ropt_net_165:5 0.0045 +5 ropt_net_165:5 ropt_net_165:4 0.0005267857 +6 ropt_net_165:7 ropt_net_165:6 0.004026786 +7 ropt_net_165:8 ropt_net_165:7 0.0045 +8 ropt_net_165:10 ropt_net_165:9 0.0045 +9 ropt_net_165:9 ropt_net_165:8 0.002348214 +10 ropt_net_165:11 ropt_net_165:10 0.0001059783 + +*END + +*D_NET chanx_right_out[13] 0.0008322493 //LENGTH 7.370 LUMPCC 0.0001011563 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 138.655 65.960 +*P chanx_right_out[13] O *L 0.7423 *C 140.450 61.200 +*N chanx_right_out[13]:2 *C 139.847 61.200 +*N chanx_right_out[13]:3 *C 139.840 61.258 +*N chanx_right_out[13]:4 *C 139.840 65.915 +*N chanx_right_out[13]:5 *C 139.795 65.960 +*N chanx_right_out[13]:6 *C 138.692 65.960 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 chanx_right_out[13] 6.472917e-05 +2 chanx_right_out[13]:2 6.472917e-05 +3 chanx_right_out[13]:3 0.0002119834 +4 chanx_right_out[13]:4 0.0002119834 +5 chanx_right_out[13]:5 8.833399e-05 +6 chanx_right_out[13]:6 8.833399e-05 +7 chanx_right_out[13]:4 ropt_net_172:6 5.057814e-05 +8 chanx_right_out[13]:3 ropt_net_172:5 5.057814e-05 + +*RES +0 ropt_mt_inst_802:X chanx_right_out[13]:6 0.152 +1 chanx_right_out[13]:6 chanx_right_out[13]:5 0.000984375 +2 chanx_right_out[13]:5 chanx_right_out[13]:4 0.0045 +3 chanx_right_out[13]:4 chanx_right_out[13]:3 0.004158482 +4 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +5 chanx_right_out[13]:2 chanx_right_out[13] 9.439165e-05 + +*END + +*D_NET chanx_right_in[12] 0.02442098 //LENGTH 184.860 LUMPCC 0.007958332 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 140.450 19.040 +*I FTB_9__8:A I *L 0.001767 *C 11.500 66.640 +*I mux_left_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 33.120 66.980 +*I mux_top_track_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 64.260 +*N chanx_right_in[12]:4 *C 55.068 64.260 +*N chanx_right_in[12]:5 *C 55.660 64.260 +*N chanx_right_in[12]:6 *C 33.120 66.980 +*N chanx_right_in[12]:7 *C 33.120 66.640 +*N chanx_right_in[12]:8 *C 33.120 66.640 +*N chanx_right_in[12]:9 *C 33.580 66.640 +*N chanx_right_in[12]:10 *C 11.463 66.640 +*N chanx_right_in[12]:11 *C 11.085 66.640 +*N chanx_right_in[12]:12 *C 11.040 66.595 +*N chanx_right_in[12]:13 *C 11.040 66.017 +*N chanx_right_in[12]:14 *C 11.048 65.960 +*N chanx_right_in[12]:15 *C 33.573 65.960 +*N chanx_right_in[12]:16 *C 33.580 65.960 +*N chanx_right_in[12]:17 *C 33.580 63.285 +*N chanx_right_in[12]:18 *C 33.625 63.240 +*N chanx_right_in[12]:19 *C 55.660 63.240 +*N chanx_right_in[12]:20 *C 56.995 63.240 +*N chanx_right_in[12]:21 *C 57.040 63.195 +*N chanx_right_in[12]:22 *C 57.040 57.858 +*N chanx_right_in[12]:23 *C 57.047 57.800 +*N chanx_right_in[12]:24 *C 58.860 57.800 +*N chanx_right_in[12]:25 *C 58.880 57.793 +*N chanx_right_in[12]:26 *C 58.880 22.448 +*N chanx_right_in[12]:27 *C 58.900 22.440 +*N chanx_right_in[12]:28 *C 108.690 22.440 +*N chanx_right_in[12]:29 *C 139.820 22.440 +*N chanx_right_in[12]:30 *C 139.840 22.433 +*N chanx_right_in[12]:31 *C 139.840 19.047 +*N chanx_right_in[12]:32 *C 139.860 19.040 + +*CAP +0 chanx_right_in[12] 3.956954e-05 +1 FTB_9__8:A 1e-06 +2 mux_left_track_1\/mux_l1_in_2_:A1 1e-06 +3 mux_top_track_14\/mux_l1_in_0_:A0 1e-06 +4 chanx_right_in[12]:4 5.064339e-05 +5 chanx_right_in[12]:5 0.0001183967 +6 chanx_right_in[12]:6 6.760932e-05 +7 chanx_right_in[12]:7 7.234895e-05 +8 chanx_right_in[12]:8 6.982523e-05 +9 chanx_right_in[12]:9 7.738604e-05 +10 chanx_right_in[12]:10 4.687281e-05 +11 chanx_right_in[12]:11 4.687281e-05 +12 chanx_right_in[12]:12 5.390092e-05 +13 chanx_right_in[12]:13 5.390092e-05 +14 chanx_right_in[12]:14 0.0008061389 +15 chanx_right_in[12]:15 0.0008061389 +16 chanx_right_in[12]:16 0.0002081214 +17 chanx_right_in[12]:17 0.0001368094 +18 chanx_right_in[12]:18 0.001319945 +19 chanx_right_in[12]:19 0.001500413 +20 chanx_right_in[12]:20 0.0001127145 +21 chanx_right_in[12]:21 0.000364039 +22 chanx_right_in[12]:22 0.000364039 +23 chanx_right_in[12]:23 0.0002023937 +24 chanx_right_in[12]:24 0.0002023937 +25 chanx_right_in[12]:25 0.001734518 +26 chanx_right_in[12]:26 0.001734518 +27 chanx_right_in[12]:27 0.00201766 +28 chanx_right_in[12]:28 0.002929312 +29 chanx_right_in[12]:29 0.0009116523 +30 chanx_right_in[12]:30 0.0001859685 +31 chanx_right_in[12]:31 0.0001859685 +32 chanx_right_in[12]:32 3.956954e-05 +33 chanx_right_in[12]:27 chanx_right_in[10]:31 6.378053e-05 +34 chanx_right_in[12]:29 chanx_right_in[10]:32 0.0001124784 +35 chanx_right_in[12]:29 chanx_right_in[10]:33 8.062069e-05 +36 chanx_right_in[12]:28 chanx_right_in[10]:31 0.0001124784 +37 chanx_right_in[12]:28 chanx_right_in[10]:32 0.0001444012 +38 chanx_right_in[12]:14 chanx_right_in[13]:22 0.0004954466 +39 chanx_right_in[12]:15 chanx_right_in[13]:23 0.0004954466 +40 chanx_right_in[12]:23 chanx_right_in[13]:26 3.604776e-05 +41 chanx_right_in[12]:24 chanx_right_in[13]:27 3.604776e-05 +42 chanx_right_in[12] chanx_right_in[14] 2.397464e-05 +43 chanx_right_in[12]:27 chanx_right_in[14]:21 0.000218928 +44 chanx_right_in[12]:29 chanx_right_in[14] 0.000134359 +45 chanx_right_in[12]:29 chanx_right_in[14]:22 4.180806e-05 +46 chanx_right_in[12]:32 chanx_right_in[14]:22 2.397464e-05 +47 chanx_right_in[12]:28 chanx_right_in[14]:21 4.180806e-05 +48 chanx_right_in[12]:28 chanx_right_in[14]:22 0.000353287 +49 chanx_right_in[12]:14 prog_clk[0]:542 0.0002023036 +50 chanx_right_in[12]:15 prog_clk[0]:543 0.0002023036 +51 chanx_right_in[12]:25 prog_clk[0]:418 1.171267e-05 +52 chanx_right_in[12]:27 prog_clk[0]:396 3.70279e-05 +53 chanx_right_in[12]:27 prog_clk[0]:395 6.721447e-05 +54 chanx_right_in[12]:27 prog_clk[0]:391 1.664112e-05 +55 chanx_right_in[12]:26 prog_clk[0]:413 1.171267e-05 +56 chanx_right_in[12]:28 prog_clk[0]:395 3.70279e-05 +57 chanx_right_in[12]:28 prog_clk[0]:391 6.721447e-05 +58 chanx_right_in[12]:28 prog_clk[0]:387 1.664112e-05 +59 chanx_right_in[12]:14 left_top_grid_pin_42_[0]:19 0.0003938644 +60 chanx_right_in[12]:16 left_top_grid_pin_42_[0]:7 3.995525e-06 +61 chanx_right_in[12]:16 left_top_grid_pin_42_[0]:6 3.858179e-05 +62 chanx_right_in[12]:15 left_top_grid_pin_42_[0]:18 0.0003938644 +63 chanx_right_in[12]:17 left_top_grid_pin_42_[0]:7 3.858179e-05 +64 chanx_right_in[12]:9 left_top_grid_pin_42_[0]:6 3.995525e-06 +65 chanx_right_in[12]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0002928565 +66 chanx_right_in[12]:16 mux_tree_tapbuf_size10_0_sram[2]:15 1.418001e-07 +67 chanx_right_in[12]:16 mux_tree_tapbuf_size10_0_sram[2]:5 4.996065e-08 +68 chanx_right_in[12]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.0002928565 +69 chanx_right_in[12]:18 mux_tree_tapbuf_size10_0_sram[2]:18 1.883205e-06 +70 chanx_right_in[12]:17 mux_tree_tapbuf_size10_0_sram[2]:15 4.996065e-08 +71 chanx_right_in[12]:17 mux_tree_tapbuf_size10_0_sram[2]:16 8.669642e-08 +72 chanx_right_in[12]:19 mux_tree_tapbuf_size10_0_sram[2]:17 1.883205e-06 +73 chanx_right_in[12]:9 mux_tree_tapbuf_size10_0_sram[2]:5 5.510366e-08 +74 chanx_right_in[12]:27 mux_tree_tapbuf_size3_6_sram[1]:10 0.0002069679 +75 chanx_right_in[12]:28 mux_tree_tapbuf_size3_6_sram[1]:11 0.0002069679 +76 chanx_right_in[12]:27 mux_tree_tapbuf_size7_3_sram[1]:16 0.0003310074 +77 chanx_right_in[12]:28 mux_tree_tapbuf_size7_3_sram[1]:17 0.0003310074 +78 chanx_right_in[12]:25 mux_tree_tapbuf_size8_0_sram[0]:13 0.0002444696 +79 chanx_right_in[12]:27 mux_tree_tapbuf_size8_0_sram[0]:15 1.887177e-05 +80 chanx_right_in[12]:26 mux_tree_tapbuf_size8_0_sram[0]:14 0.0002444696 +81 chanx_right_in[12]:28 mux_tree_tapbuf_size8_0_sram[0]:16 1.887177e-05 +82 chanx_right_in[12]:18 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001121425 +83 chanx_right_in[12]:19 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001121425 +84 chanx_right_in[12]:18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002819737 +85 chanx_right_in[12]:19 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002819737 +86 chanx_right_in[12] chanx_right_out[14] 2.046036e-06 +87 chanx_right_in[12]:29 chanx_right_out[14] 0.0005079713 +88 chanx_right_in[12]:32 chanx_right_out[14]:2 2.046036e-06 +89 chanx_right_in[12]:28 chanx_right_out[14]:2 0.0005079713 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:32 9.243333e-05 +1 chanx_right_in[12]:10 FTB_9__8:A 0.152 +2 chanx_right_in[12]:11 chanx_right_in[12]:10 0.0003370536 +3 chanx_right_in[12]:12 chanx_right_in[12]:11 0.0045 +4 chanx_right_in[12]:13 chanx_right_in[12]:12 0.000515625 +5 chanx_right_in[12]:14 chanx_right_in[12]:13 0.00341 +6 chanx_right_in[12]:16 chanx_right_in[12]:15 0.00341 +7 chanx_right_in[12]:16 chanx_right_in[12]:9 0.0006071429 +8 chanx_right_in[12]:15 chanx_right_in[12]:14 0.003528917 +9 chanx_right_in[12]:18 chanx_right_in[12]:17 0.0045 +10 chanx_right_in[12]:17 chanx_right_in[12]:16 0.002388393 +11 chanx_right_in[12]:7 chanx_right_in[12]:6 0.0001465517 +12 chanx_right_in[12]:8 chanx_right_in[12]:7 0.0045 +13 chanx_right_in[12]:6 mux_left_track_1\/mux_l1_in_2_:A1 0.152 +14 chanx_right_in[12]:4 mux_top_track_14\/mux_l1_in_0_:A0 0.152 +15 chanx_right_in[12]:20 chanx_right_in[12]:19 0.001191964 +16 chanx_right_in[12]:21 chanx_right_in[12]:20 0.0045 +17 chanx_right_in[12]:22 chanx_right_in[12]:21 0.004765626 +18 chanx_right_in[12]:23 chanx_right_in[12]:22 0.00341 +19 chanx_right_in[12]:24 chanx_right_in[12]:23 0.0002839583 +20 chanx_right_in[12]:25 chanx_right_in[12]:24 0.00341 +21 chanx_right_in[12]:27 chanx_right_in[12]:26 0.00341 +22 chanx_right_in[12]:26 chanx_right_in[12]:25 0.005537383 +23 chanx_right_in[12]:29 chanx_right_in[12]:28 0.004877033 +24 chanx_right_in[12]:30 chanx_right_in[12]:29 0.00341 +25 chanx_right_in[12]:32 chanx_right_in[12]:31 0.00341 +26 chanx_right_in[12]:31 chanx_right_in[12]:30 0.0005303167 +27 chanx_right_in[12]:19 chanx_right_in[12]:18 0.01967411 +28 chanx_right_in[12]:19 chanx_right_in[12]:5 0.0009107144 +29 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0005290179 +30 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0004107143 +31 chanx_right_in[12]:28 chanx_right_in[12]:27 0.007800433 + +*END + +*D_NET chanx_left_in[9] 0.02853372 //LENGTH 181.840 LUMPCC 0.01075032 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.298 72.080 +*I mux_top_track_10\/mux_l2_in_1_:A1 I *L 0.00198 *C 125.485 61.540 +*I FTB_20__19:A I *L 0.001776 *C 132.480 31.280 +*I mux_right_track_24\/mux_l1_in_2_:A0 I *L 0.001631 *C 98.270 60.860 +*N chanx_left_in[9]:4 *C 98.270 60.860 +*N chanx_left_in[9]:5 *C 97.980 60.860 +*N chanx_left_in[9]:6 *C 97.980 60.905 +*N chanx_left_in[9]:7 *C 132.480 31.280 +*N chanx_left_in[9]:8 *C 132.480 31.325 +*N chanx_left_in[9]:9 *C 132.480 61.835 +*N chanx_left_in[9]:10 *C 132.435 61.880 +*N chanx_left_in[9]:11 *C 125.485 61.540 +*N chanx_left_in[9]:12 *C 125.625 61.880 +*N chanx_left_in[9]:13 *C 125.580 61.880 +*N chanx_left_in[9]:14 *C 125.120 61.880 +*N chanx_left_in[9]:15 *C 125.113 61.880 +*N chanx_left_in[9]:16 *C 97.988 61.880 +*N chanx_left_in[9]:17 *C 97.980 61.880 +*N chanx_left_in[9]:18 *C 97.980 65.222 +*N chanx_left_in[9]:19 *C 97.973 65.280 +*N chanx_left_in[9]:20 *C 92.940 65.280 +*N chanx_left_in[9]:21 *C 92.920 65.288 +*N chanx_left_in[9]:22 *C 92.920 72.752 +*N chanx_left_in[9]:23 *C 92.900 72.760 +*N chanx_left_in[9]:24 *C 81.115 72.760 +*N chanx_left_in[9]:25 *C 31.288 72.760 +*N chanx_left_in[9]:26 *C 31.280 72.818 +*N chanx_left_in[9]:27 *C 31.280 74.075 +*N chanx_left_in[9]:28 *C 31.235 74.120 +*N chanx_left_in[9]:29 *C 1.425 74.120 +*N chanx_left_in[9]:30 *C 1.380 74.075 +*N chanx_left_in[9]:31 *C 1.380 72.138 +*N chanx_left_in[9]:32 *C 1.380 72.080 + +*CAP +0 chanx_left_in[9] 2.921802e-05 +1 mux_top_track_10\/mux_l2_in_1_:A1 1e-06 +2 FTB_20__19:A 1e-06 +3 mux_right_track_24\/mux_l1_in_2_:A0 1e-06 +4 chanx_left_in[9]:4 5.56819e-05 +5 chanx_left_in[9]:5 5.965101e-05 +6 chanx_left_in[9]:6 6.490124e-05 +7 chanx_left_in[9]:7 3.439636e-05 +8 chanx_left_in[9]:8 0.001375522 +9 chanx_left_in[9]:9 0.001375522 +10 chanx_left_in[9]:10 0.0004292348 +11 chanx_left_in[9]:11 6.09888e-05 +12 chanx_left_in[9]:12 0.0004624188 +13 chanx_left_in[9]:13 7.036011e-05 +14 chanx_left_in[9]:14 7.62547e-05 +15 chanx_left_in[9]:15 0.000828788 +16 chanx_left_in[9]:16 0.000828788 +17 chanx_left_in[9]:17 0.0002903864 +18 chanx_left_in[9]:18 0.0001879454 +19 chanx_left_in[9]:19 0.000240499 +20 chanx_left_in[9]:20 0.000240499 +21 chanx_left_in[9]:21 0.0005107801 +22 chanx_left_in[9]:22 0.0005107801 +23 chanx_left_in[9]:23 0.0007299787 +24 chanx_left_in[9]:24 0.003292949 +25 chanx_left_in[9]:25 0.002562971 +26 chanx_left_in[9]:26 0.0001021234 +27 chanx_left_in[9]:27 0.0001021234 +28 chanx_left_in[9]:28 0.001501451 +29 chanx_left_in[9]:29 0.001501451 +30 chanx_left_in[9]:30 0.0001127591 +31 chanx_left_in[9]:31 0.0001127591 +32 chanx_left_in[9]:32 2.921802e-05 +33 chanx_left_in[9]:16 chanx_left_in[10]:15 0.0004514421 +34 chanx_left_in[9]:15 chanx_left_in[10]:14 0.0004514421 +35 chanx_left_in[9]:10 chanx_left_in[12]:9 6.768545e-05 +36 chanx_left_in[9]:16 chanx_left_in[12]:14 0.0003958762 +37 chanx_left_in[9]:15 chanx_left_in[12]:13 0.0003958762 +38 chanx_left_in[9]:12 chanx_left_in[12]:10 6.768545e-05 +39 chanx_left_in[9]:18 chanx_left_in[13]:7 2.663325e-05 +40 chanx_left_in[9]:19 chanx_left_in[13]:9 6.007697e-05 +41 chanx_left_in[9]:19 chanx_left_in[13]:18 0.0002120624 +42 chanx_left_in[9]:20 chanx_left_in[13]:19 0.0002120624 +43 chanx_left_in[9]:20 chanx_left_in[13]:18 6.007697e-05 +44 chanx_left_in[9]:17 chanx_left_in[13]:8 2.663325e-05 +45 chanx_left_in[9]:25 chany_top_in[5]:7 0.0009829288 +46 chanx_left_in[9]:24 chany_top_in[5]:8 0.0009829288 +47 chanx_left_in[9]:23 chany_top_in[15]:9 0.0002244989 +48 chanx_left_in[9]:25 chany_top_in[15]:10 0.0006580931 +49 chanx_left_in[9]:24 chany_top_in[15]:10 0.0002244989 +50 chanx_left_in[9]:24 chany_top_in[15]:9 0.0006580931 +51 chanx_left_in[9]:9 right_bottom_grid_pin_1_[0]:15 0.0001576387 +52 chanx_left_in[9]:9 right_bottom_grid_pin_1_[0]:13 0.0001290087 +53 chanx_left_in[9]:8 right_bottom_grid_pin_1_[0]:16 0.0001576387 +54 chanx_left_in[9]:8 right_bottom_grid_pin_1_[0]:15 0.0001290087 +55 chanx_left_in[9]:16 right_bottom_grid_pin_1_[0]:11 0.000306571 +56 chanx_left_in[9]:15 right_bottom_grid_pin_1_[0]:12 0.000306571 +57 chanx_left_in[9]:28 chanx_left_in[11]:7 0.0004305048 +58 chanx_left_in[9]:29 chanx_left_in[11]:8 0.0004305048 +59 chanx_left_in[9]:25 left_top_grid_pin_44_[0]:23 0.000286383 +60 chanx_left_in[9]:24 left_top_grid_pin_44_[0]:22 0.000286383 +61 chanx_left_in[9]:28 left_top_grid_pin_46_[0]:22 0.0002871369 +62 chanx_left_in[9]:29 left_top_grid_pin_46_[0]:23 0.0002871369 +63 chanx_left_in[9]:16 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0005090669 +64 chanx_left_in[9]:15 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0005090669 +65 chanx_left_in[9]:9 ropt_net_148:5 0.0001373678 +66 chanx_left_in[9]:8 ropt_net_148:4 0.0001373678 +67 chanx_left_in[9]:9 ropt_net_146:5 5.218683e-05 +68 chanx_left_in[9]:8 ropt_net_146:6 5.218683e-05 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:32 2.35e-05 +1 chanx_left_in[9]:18 chanx_left_in[9]:17 0.002984375 +2 chanx_left_in[9]:19 chanx_left_in[9]:18 0.00341 +3 chanx_left_in[9]:20 chanx_left_in[9]:19 0.000788425 +4 chanx_left_in[9]:21 chanx_left_in[9]:20 0.00341 +5 chanx_left_in[9]:23 chanx_left_in[9]:22 0.00341 +6 chanx_left_in[9]:22 chanx_left_in[9]:21 0.001169517 +7 chanx_left_in[9]:26 chanx_left_in[9]:25 0.00341 +8 chanx_left_in[9]:25 chanx_left_in[9]:24 0.007806308 +9 chanx_left_in[9]:28 chanx_left_in[9]:27 0.0045 +10 chanx_left_in[9]:27 chanx_left_in[9]:26 0.001122768 +11 chanx_left_in[9]:29 chanx_left_in[9]:28 0.02661607 +12 chanx_left_in[9]:30 chanx_left_in[9]:29 0.0045 +13 chanx_left_in[9]:31 chanx_left_in[9]:30 0.001729911 +14 chanx_left_in[9]:32 chanx_left_in[9]:31 0.00341 +15 chanx_left_in[9]:10 chanx_left_in[9]:9 0.0045 +16 chanx_left_in[9]:9 chanx_left_in[9]:8 0.02724108 +17 chanx_left_in[9]:7 FTB_20__19:A 0.152 +18 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0045 +19 chanx_left_in[9]:11 mux_top_track_10\/mux_l2_in_1_:A1 0.152 +20 chanx_left_in[9]:17 chanx_left_in[9]:16 0.00341 +21 chanx_left_in[9]:17 chanx_left_in[9]:6 0.0008705358 +22 chanx_left_in[9]:16 chanx_left_in[9]:15 0.004249583 +23 chanx_left_in[9]:14 chanx_left_in[9]:13 0.0004107143 +24 chanx_left_in[9]:15 chanx_left_in[9]:14 0.00341 +25 chanx_left_in[9]:12 chanx_left_in[9]:11 0.0001847826 +26 chanx_left_in[9]:12 chanx_left_in[9]:10 0.006080357 +27 chanx_left_in[9]:13 chanx_left_in[9]:12 0.0045 +28 chanx_left_in[9]:5 chanx_left_in[9]:4 0.0001576087 +29 chanx_left_in[9]:6 chanx_left_in[9]:5 0.0045 +30 chanx_left_in[9]:4 mux_right_track_24\/mux_l1_in_2_:A0 0.152 +31 chanx_left_in[9]:24 chanx_left_in[9]:23 0.001846317 + +*END + +*D_NET chanx_left_in[12] 0.02400704 //LENGTH 164.975 LUMPCC 0.007573658 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 36.720 +*I FTB_22__21:A I *L 0.001767 *C 130.180 61.200 +*I mux_right_track_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 127.325 66.980 +*I mux_top_track_14\/mux_l1_in_1_:A1 I *L 0.00198 *C 51.885 58.140 +*N chanx_left_in[12]:4 *C 51.922 58.140 +*N chanx_left_in[12]:5 *C 52.440 58.140 +*N chanx_left_in[12]:6 *C 127.288 66.980 +*N chanx_left_in[12]:7 *C 126.085 66.980 +*N chanx_left_in[12]:8 *C 126.040 66.935 +*N chanx_left_in[12]:9 *C 130.143 61.200 +*N chanx_left_in[12]:10 *C 126.085 61.200 +*N chanx_left_in[12]:11 *C 126.040 61.200 +*N chanx_left_in[12]:12 *C 126.040 60.578 +*N chanx_left_in[12]:13 *C 126.033 60.520 +*N chanx_left_in[12]:14 *C 92.928 60.520 +*N chanx_left_in[12]:15 *C 92.920 60.463 +*N chanx_left_in[12]:16 *C 92.920 57.845 +*N chanx_left_in[12]:17 *C 92.875 57.800 +*N chanx_left_in[12]:18 *C 52.440 57.800 +*N chanx_left_in[12]:19 *C 52.440 57.755 +*N chanx_left_in[12]:20 *C 52.440 51.058 +*N chanx_left_in[12]:21 *C 52.433 51.000 +*N chanx_left_in[12]:22 *C 11.060 51.000 +*N chanx_left_in[12]:23 *C 11.040 50.992 +*N chanx_left_in[12]:24 *C 11.040 36.727 +*N chanx_left_in[12]:25 *C 11.020 36.720 + +*CAP +0 chanx_left_in[12] 0.0006434923 +1 FTB_22__21:A 1e-06 +2 mux_right_track_0\/mux_l2_in_3_:A1 1e-06 +3 mux_top_track_14\/mux_l1_in_1_:A1 1e-06 +4 chanx_left_in[12]:4 5.828477e-05 +5 chanx_left_in[12]:5 8.709729e-05 +6 chanx_left_in[12]:6 0.0001078812 +7 chanx_left_in[12]:7 0.0001078812 +8 chanx_left_in[12]:8 0.0003240152 +9 chanx_left_in[12]:9 0.0002020516 +10 chanx_left_in[12]:10 0.0002020516 +11 chanx_left_in[12]:11 0.0004039096 +12 chanx_left_in[12]:12 4.671913e-05 +13 chanx_left_in[12]:13 0.0009540015 +14 chanx_left_in[12]:14 0.0009540015 +15 chanx_left_in[12]:15 0.0001631631 +16 chanx_left_in[12]:16 0.0001631631 +17 chanx_left_in[12]:17 0.002538449 +18 chanx_left_in[12]:18 0.002567261 +19 chanx_left_in[12]:19 0.0004130731 +20 chanx_left_in[12]:20 0.0004130731 +21 chanx_left_in[12]:21 0.002054963 +22 chanx_left_in[12]:22 0.002054963 +23 chanx_left_in[12]:23 0.0006637004 +24 chanx_left_in[12]:24 0.0006637004 +25 chanx_left_in[12]:25 0.0006434923 +26 chanx_left_in[12]:21 chanx_left_in[2]:28 0.0003231234 +27 chanx_left_in[12]:22 chanx_left_in[2] 0.0003231234 +28 chanx_left_in[12]:13 chanx_left_in[4]:16 0.0004382575 +29 chanx_left_in[12]:14 chanx_left_in[4]:17 0.0004382575 +30 chanx_left_in[12]:13 chanx_left_in[9]:15 0.0003958762 +31 chanx_left_in[12]:14 chanx_left_in[9]:16 0.0003958762 +32 chanx_left_in[12]:10 chanx_left_in[9]:12 6.768545e-05 +33 chanx_left_in[12]:9 chanx_left_in[9]:10 6.768545e-05 +34 chanx_left_in[12]:13 chanx_left_in[13]:18 2.625979e-06 +35 chanx_left_in[12]:14 chanx_left_in[13]:19 2.625979e-06 +36 chanx_left_in[12]:19 chanx_left_in[13]:24 1.916573e-05 +37 chanx_left_in[12]:20 chanx_left_in[13]:25 1.916573e-05 +38 chanx_left_in[12]:21 chanx_left_in[13]:26 0.0007275452 +39 chanx_left_in[12]:22 chanx_left_in[13]:27 0.0007275452 +40 chanx_left_in[12]:13 prog_clk[0]:212 0.0005526161 +41 chanx_left_in[12]:13 prog_clk[0]:217 0.000238416 +42 chanx_left_in[12]:15 prog_clk[0]:277 2.658249e-06 +43 chanx_left_in[12]:14 prog_clk[0]:278 0.000238416 +44 chanx_left_in[12]:14 prog_clk[0]:217 0.0005526161 +45 chanx_left_in[12]:16 prog_clk[0]:276 2.658249e-06 +46 chanx_left_in[12]:19 prog_clk[0]:506 2.601405e-07 +47 chanx_left_in[12]:20 prog_clk[0]:505 2.601405e-07 +48 chanx_left_in[12]:21 prog_clk[0]:496 9.223387e-05 +49 chanx_left_in[12]:22 prog_clk[0]:495 9.223387e-05 +50 chanx_left_in[12]:17 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 7.099098e-05 +51 chanx_left_in[12]:18 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 7.099098e-05 +52 chanx_left_in[12]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001533614 +53 chanx_left_in[12]:18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001533614 +54 chanx_left_in[12]:13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0005090669 +55 chanx_left_in[12]:14 mux_top_track_10/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0005090669 +56 chanx_left_in[12]:17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.764236e-05 +57 chanx_left_in[12]:18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.764236e-05 +58 chanx_left_in[12]:23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001353025 +59 chanx_left_in[12]:24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001353025 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:25 0.001533767 +1 chanx_left_in[12]:12 chanx_left_in[12]:11 0.0005558036 +2 chanx_left_in[12]:13 chanx_left_in[12]:12 0.00341 +3 chanx_left_in[12]:15 chanx_left_in[12]:14 0.00341 +4 chanx_left_in[12]:14 chanx_left_in[12]:13 0.00518645 +5 chanx_left_in[12]:17 chanx_left_in[12]:16 0.0045 +6 chanx_left_in[12]:16 chanx_left_in[12]:15 0.002337054 +7 chanx_left_in[12]:18 chanx_left_in[12]:17 0.03610268 +8 chanx_left_in[12]:18 chanx_left_in[12]:5 0.0003035715 +9 chanx_left_in[12]:19 chanx_left_in[12]:18 0.0045 +10 chanx_left_in[12]:20 chanx_left_in[12]:19 0.005979911 +11 chanx_left_in[12]:21 chanx_left_in[12]:20 0.00341 +12 chanx_left_in[12]:22 chanx_left_in[12]:21 0.006481691 +13 chanx_left_in[12]:23 chanx_left_in[12]:22 0.00341 +14 chanx_left_in[12]:25 chanx_left_in[12]:24 0.00341 +15 chanx_left_in[12]:24 chanx_left_in[12]:23 0.00223485 +16 chanx_left_in[12]:4 mux_top_track_14\/mux_l1_in_1_:A1 0.152 +17 chanx_left_in[12]:10 chanx_left_in[12]:9 0.003622768 +18 chanx_left_in[12]:11 chanx_left_in[12]:10 0.0045 +19 chanx_left_in[12]:11 chanx_left_in[12]:8 0.005120536 +20 chanx_left_in[12]:9 FTB_22__21:A 0.152 +21 chanx_left_in[12]:7 chanx_left_in[12]:6 0.001073661 +22 chanx_left_in[12]:8 chanx_left_in[12]:7 0.0045 +23 chanx_left_in[12]:6 mux_right_track_0\/mux_l2_in_3_:A1 0.152 +24 chanx_left_in[12]:5 chanx_left_in[12]:4 0.0004620536 + +*END + +*D_NET chanx_left_in[18] 0.02197722 //LENGTH 180.870 LUMPCC 0.004104456 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 5.440 +*I mux_right_track_24\/mux_l1_in_3_:A1 I *L 0.00198 *C 100.280 56.100 +*I BUFT_P_97:A I *L 0.001776 *C 127.420 53.040 +*I mux_top_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 78.660 34.340 +*N chanx_left_in[18]:4 *C 78.660 34.340 +*N chanx_left_in[18]:5 *C 127.383 53.040 +*N chanx_left_in[18]:6 *C 126.545 53.040 +*N chanx_left_in[18]:7 *C 126.500 53.040 +*N chanx_left_in[18]:8 *C 126.493 53.040 +*N chanx_left_in[18]:9 *C 100.280 56.100 +*N chanx_left_in[18]:10 *C 100.280 56.055 +*N chanx_left_in[18]:11 *C 100.280 53.098 +*N chanx_left_in[18]:12 *C 100.280 53.040 +*N chanx_left_in[18]:13 *C 97.988 53.040 +*N chanx_left_in[18]:14 *C 97.980 52.983 +*N chanx_left_in[18]:15 *C 97.980 42.218 +*N chanx_left_in[18]:16 *C 97.973 42.160 +*N chanx_left_in[18]:17 *C 97.068 42.160 +*N chanx_left_in[18]:18 *C 97.060 42.102 +*N chanx_left_in[18]:19 *C 97.060 34.725 +*N chanx_left_in[18]:20 *C 97.015 34.680 +*N chanx_left_in[18]:21 *C 78.660 34.680 +*N chanx_left_in[18]:22 *C 76.405 34.680 +*N chanx_left_in[18]:23 *C 76.360 34.635 +*N chanx_left_in[18]:24 *C 76.360 6.505 +*N chanx_left_in[18]:25 *C 76.315 6.460 +*N chanx_left_in[18]:26 *C 54.900 6.460 +*N chanx_left_in[18]:27 *C 5.105 6.460 +*N chanx_left_in[18]:28 *C 5.060 6.415 +*N chanx_left_in[18]:29 *C 5.060 5.498 +*N chanx_left_in[18]:30 *C 5.053 5.440 + +*CAP +0 chanx_left_in[18] 0.0002892103 +1 mux_right_track_24\/mux_l1_in_3_:A1 1e-06 +2 BUFT_P_97:A 1e-06 +3 mux_top_track_24\/mux_l1_in_1_:A1 1e-06 +4 chanx_left_in[18]:4 5.936859e-05 +5 chanx_left_in[18]:5 7.617434e-05 +6 chanx_left_in[18]:6 7.617434e-05 +7 chanx_left_in[18]:7 3.246466e-05 +8 chanx_left_in[18]:8 0.0007913609 +9 chanx_left_in[18]:9 3.353842e-05 +10 chanx_left_in[18]:10 0.000204643 +11 chanx_left_in[18]:11 0.000204643 +12 chanx_left_in[18]:12 0.0008528343 +13 chanx_left_in[18]:13 6.147333e-05 +14 chanx_left_in[18]:14 0.0006163279 +15 chanx_left_in[18]:15 0.0006163279 +16 chanx_left_in[18]:16 0.0001272362 +17 chanx_left_in[18]:17 0.0001272362 +18 chanx_left_in[18]:18 0.0004104673 +19 chanx_left_in[18]:19 0.0004104673 +20 chanx_left_in[18]:20 0.001112269 +21 chanx_left_in[18]:21 0.001320288 +22 chanx_left_in[18]:22 0.0001789736 +23 chanx_left_in[18]:23 0.001375356 +24 chanx_left_in[18]:24 0.001375356 +25 chanx_left_in[18]:25 0.001080122 +26 chanx_left_in[18]:26 0.003547809 +27 chanx_left_in[18]:27 0.002467686 +28 chanx_left_in[18]:28 6.637297e-05 +29 chanx_left_in[18]:29 6.637297e-05 +30 chanx_left_in[18]:30 0.0002892103 +31 chanx_left_in[18]:12 chanx_right_in[9]:24 0.0003002086 +32 chanx_left_in[18]:12 chanx_right_in[9]:29 0.0003629337 +33 chanx_left_in[18]:13 chanx_right_in[9]:24 5.052318e-05 +34 chanx_left_in[18]:8 chanx_right_in[9]:29 0.0003002086 +35 chanx_left_in[18]:8 chanx_right_in[9]:30 0.0003124106 +36 chanx_left_in[18]:12 chanx_right_in[0]:14 0.0008325791 +37 chanx_left_in[18]:8 chanx_right_in[0]:15 0.0008325791 +38 chanx_left_in[18]:12 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 0.0001328132 +39 chanx_left_in[18]:12 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 0.0001072021 +40 chanx_left_in[18]:13 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 0.0001328132 +41 chanx_left_in[18]:8 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 0.0001072021 +42 chanx_left_in[18]:23 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 5.535899e-05 +43 chanx_left_in[18]:24 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 5.535899e-05 +44 chanx_left_in[18]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001168995 +45 chanx_left_in[18]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.163014e-06 +46 chanx_left_in[18]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001168995 +47 chanx_left_in[18]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.163014e-06 +48 chanx_left_in[18]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001380694 +49 chanx_left_in[18]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001380694 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:30 0.0005988583 +1 chanx_left_in[18]:9 mux_right_track_24\/mux_l1_in_3_:A1 0.152 +2 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0045 +3 chanx_left_in[18]:11 chanx_left_in[18]:10 0.002640625 +4 chanx_left_in[18]:12 chanx_left_in[18]:11 0.00341 +5 chanx_left_in[18]:12 chanx_left_in[18]:8 0.004106625 +6 chanx_left_in[18]:22 chanx_left_in[18]:21 0.002013393 +7 chanx_left_in[18]:23 chanx_left_in[18]:22 0.0045 +8 chanx_left_in[18]:25 chanx_left_in[18]:24 0.0045 +9 chanx_left_in[18]:24 chanx_left_in[18]:23 0.02511607 +10 chanx_left_in[18]:27 chanx_left_in[18]:26 0.04445983 +11 chanx_left_in[18]:28 chanx_left_in[18]:27 0.0045 +12 chanx_left_in[18]:29 chanx_left_in[18]:28 0.0008191965 +13 chanx_left_in[18]:30 chanx_left_in[18]:29 0.00341 +14 chanx_left_in[18]:14 chanx_left_in[18]:13 0.00341 +15 chanx_left_in[18]:13 chanx_left_in[18]:12 0.0003591583 +16 chanx_left_in[18]:15 chanx_left_in[18]:14 0.009611608 +17 chanx_left_in[18]:16 chanx_left_in[18]:15 0.00341 +18 chanx_left_in[18]:18 chanx_left_in[18]:17 0.00341 +19 chanx_left_in[18]:17 chanx_left_in[18]:16 0.0001417833 +20 chanx_left_in[18]:20 chanx_left_in[18]:19 0.0045 +21 chanx_left_in[18]:19 chanx_left_in[18]:18 0.006587054 +22 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0045 +23 chanx_left_in[18]:8 chanx_left_in[18]:7 0.00341 +24 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0007477679 +25 chanx_left_in[18]:5 BUFT_P_97:A 0.152 +26 chanx_left_in[18]:4 mux_top_track_24\/mux_l1_in_1_:A1 0.152 +27 chanx_left_in[18]:21 chanx_left_in[18]:20 0.01638839 +28 chanx_left_in[18]:21 chanx_left_in[18]:4 0.0003035715 +29 chanx_left_in[18]:26 chanx_left_in[18]:25 0.01912054 + +*END + +*D_NET prog_clk[0] 0.1340881 //LENGTH 905.643 LUMPCC 0.03422911 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 30.820 102.070 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.005 91.120 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 35.685 85.680 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 42.585 82.960 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 50.865 77.520 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 43.965 74.800 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 77.520 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.225 74.800 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 26.945 69.360 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 12.225 66.640 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 15.905 61.200 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 12.225 55.760 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.380 44.880 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 15.905 72.080 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 28.785 63.920 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 41.665 58.480 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 48.105 53.040 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 49.945 50.320 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 41.205 50.320 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.465 58.480 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 28.785 50.320 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 24.680 42.160 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 25.565 44.880 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 34.765 42.160 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 43.505 42.160 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 52.245 42.160 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 28.785 31.280 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 24.095 26.050 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.825 34.000 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 14.065 36.720 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 38.445 28.560 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 44.885 34.000 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 47.645 36.720 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 52.705 25.840 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 56.845 36.720 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 59.605 34.000 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.195 28.560 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 82.605 25.840 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 91.345 25.840 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 92.725 23.120 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.865 23.120 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 78.465 31.280 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 63.285 25.840 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 68.345 36.720 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.985 36.720 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 33.385 82.960 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 40.745 99.280 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 51.325 96.560 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 53.625 85.680 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 58.685 61.200 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 64.665 55.760 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.985 63.920 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.525 74.800 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 65.675 80.240 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 72.025 74.800 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 81.225 61.200 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 82.145 55.760 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 78.465 42.160 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 86.745 39.440 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 92.725 53.040 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 93.645 44.880 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 95.025 42.160 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 99.165 50.320 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 101.465 36.720 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 107.445 47.600 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 118.485 42.160 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 110.270 39.440 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 112.965 31.280 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 112.045 28.560 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 116.185 47.600 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 90.425 50.320 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 96.860 58.480 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 108.825 61.200 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 87.205 66.640 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.105 63.920 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 72.025 61.200 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 80.765 77.520 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 85.825 74.800 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 68.805 82.960 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.605 93.840 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 60.985 91.120 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 70.185 91.120 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 78.925 88.400 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 88.585 85.680 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 87.205 82.960 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 93.185 93.840 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 96.865 88.400 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.925 80.240 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 99.625 77.520 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 117.060 66.640 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 117.105 58.480 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 114.805 53.040 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 120.325 72.080 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 95.060 69.360 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.925 93.840 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 31.520 99.280 +*N prog_clk[0]:96 *C 31.483 99.280 +*N prog_clk[0]:97 *C 30.865 99.280 +*N prog_clk[0]:98 *C 101.925 93.840 +*N prog_clk[0]:99 *C 101.660 93.840 +*N prog_clk[0]:100 *C 101.660 93.840 +*N prog_clk[0]:101 *C 101.653 93.840 +*N prog_clk[0]:102 *C 96.600 93.840 +*N prog_clk[0]:103 *C 95.060 69.360 +*N prog_clk[0]:104 *C 95.220 69.360 +*N prog_clk[0]:105 *C 95.220 69.405 +*N prog_clk[0]:106 *C 95.220 70.720 +*N prog_clk[0]:107 *C 120.325 72.080 +*N prog_clk[0]:108 *C 120.060 72.080 +*N prog_clk[0]:109 *C 120.060 72.035 +*N prog_clk[0]:110 *C 120.060 70.778 +*N prog_clk[0]:111 *C 120.053 70.720 +*N prog_clk[0]:112 *C 114.805 53.040 +*N prog_clk[0]:113 *C 115.000 53.040 +*N prog_clk[0]:114 *C 115.000 53.085 +*N prog_clk[0]:115 *C 115.000 58.480 +*N prog_clk[0]:116 *C 117.105 58.480 +*N prog_clk[0]:117 *C 117.300 58.480 +*N prog_clk[0]:118 *C 117.300 58.480 +*N prog_clk[0]:119 *C 117.293 58.480 +*N prog_clk[0]:120 *C 115.468 58.480 +*N prog_clk[0]:121 *C 115.460 58.538 +*N prog_clk[0]:122 *C 117.023 66.640 +*N prog_clk[0]:123 *C 115.505 66.640 +*N prog_clk[0]:124 *C 115.460 66.640 +*N prog_clk[0]:125 *C 115.460 70.663 +*N prog_clk[0]:126 *C 115.460 70.720 +*N prog_clk[0]:127 *C 96.148 70.720 +*N prog_clk[0]:128 *C 96.140 70.778 +*N prog_clk[0]:129 *C 99.588 77.520 +*N prog_clk[0]:130 *C 98.945 77.520 +*N prog_clk[0]:131 *C 98.900 77.520 +*N prog_clk[0]:132 *C 98.892 77.520 +*N prog_clk[0]:133 *C 96.148 77.520 +*N prog_clk[0]:134 *C 96.140 77.520 +*N prog_clk[0]:135 *C 96.140 80.240 +*N prog_clk[0]:136 *C 101.925 80.240 +*N prog_clk[0]:137 *C 101.660 80.240 +*N prog_clk[0]:138 *C 101.660 80.240 +*N prog_clk[0]:139 *C 101.653 80.240 +*N prog_clk[0]:140 *C 96.608 80.240 +*N prog_clk[0]:141 *C 96.600 80.297 +*N prog_clk[0]:142 *C 96.865 88.400 +*N prog_clk[0]:143 *C 96.600 88.060 +*N prog_clk[0]:144 *C 96.600 88.060 +*N prog_clk[0]:145 *C 96.600 93.103 +*N prog_clk[0]:146 *C 96.600 93.168 +*N prog_clk[0]:147 *C 93.185 93.840 +*N prog_clk[0]:148 *C 92.920 93.840 +*N prog_clk[0]:149 *C 92.920 93.795 +*N prog_clk[0]:150 *C 92.920 93.218 +*N prog_clk[0]:151 *C 92.920 93.160 +*N prog_clk[0]:152 *C 87.205 82.960 +*N prog_clk[0]:153 *C 87.400 82.960 +*N prog_clk[0]:154 *C 87.400 83.005 +*N prog_clk[0]:155 *C 88.547 85.680 +*N prog_clk[0]:156 *C 87.400 85.680 +*N prog_clk[0]:157 *C 87.400 86.020 +*N prog_clk[0]:158 *C 87.400 86.020 +*N prog_clk[0]:159 *C 87.400 93.103 +*N prog_clk[0]:160 *C 87.400 93.160 +*N prog_clk[0]:161 *C 79.120 93.160 +*N prog_clk[0]:162 *C 78.925 88.400 +*N prog_clk[0]:163 *C 79.120 88.400 +*N prog_clk[0]:164 *C 79.120 88.445 +*N prog_clk[0]:165 *C 79.120 92.422 +*N prog_clk[0]:166 *C 79.120 92.488 +*N prog_clk[0]:167 *C 70.185 91.120 +*N prog_clk[0]:168 *C 69.920 91.120 +*N prog_clk[0]:169 *C 69.920 91.165 +*N prog_clk[0]:170 *C 69.920 92.422 +*N prog_clk[0]:171 *C 69.920 92.480 +*N prog_clk[0]:172 *C 60.985 91.120 +*N prog_clk[0]:173 *C 61.180 91.120 +*N prog_clk[0]:174 *C 61.180 91.165 +*N prog_clk[0]:175 *C 61.180 92.422 +*N prog_clk[0]:176 *C 61.180 92.480 +*N prog_clk[0]:177 *C 59.348 92.480 +*N prog_clk[0]:178 *C 59.340 92.538 +*N prog_clk[0]:179 *C 59.605 93.840 +*N prog_clk[0]:180 *C 59.340 93.840 +*N prog_clk[0]:181 *C 59.340 93.840 +*N prog_clk[0]:182 *C 59.333 93.840 +*N prog_clk[0]:183 *C 53.820 93.840 +*N prog_clk[0]:184 *C 68.767 82.960 +*N prog_clk[0]:185 *C 68.125 82.960 +*N prog_clk[0]:186 *C 68.080 82.960 +*N prog_clk[0]:187 *C 68.073 82.960 +*N prog_clk[0]:188 *C 67.160 82.960 +*N prog_clk[0]:189 *C 85.788 74.800 +*N prog_clk[0]:190 *C 84.685 74.800 +*N prog_clk[0]:191 *C 84.640 74.845 +*N prog_clk[0]:192 *C 84.640 77.463 +*N prog_clk[0]:193 *C 84.633 77.520 +*N prog_clk[0]:194 *C 80.765 77.520 +*N prog_clk[0]:195 *C 80.960 77.520 +*N prog_clk[0]:196 *C 80.960 77.520 +*N prog_clk[0]:197 *C 80.960 77.520 +*N prog_clk[0]:198 *C 72.025 61.200 +*N prog_clk[0]:199 *C 71.760 61.200 +*N prog_clk[0]:200 *C 71.760 61.245 +*N prog_clk[0]:201 *C 71.105 63.920 +*N prog_clk[0]:202 *C 71.300 64.260 +*N prog_clk[0]:203 *C 71.715 64.260 +*N prog_clk[0]:204 *C 71.760 64.260 +*N prog_clk[0]:205 *C 87.205 66.640 +*N prog_clk[0]:206 *C 87.400 66.640 +*N prog_clk[0]:207 *C 87.400 66.595 +*N prog_clk[0]:208 *C 108.788 61.200 +*N prog_clk[0]:209 *C 107.225 61.200 +*N prog_clk[0]:210 *C 107.180 61.155 +*N prog_clk[0]:211 *C 107.180 59.898 +*N prog_clk[0]:212 *C 107.172 59.840 +*N prog_clk[0]:213 *C 96.860 58.480 +*N prog_clk[0]:214 *C 97.060 58.480 +*N prog_clk[0]:215 *C 97.060 58.525 +*N prog_clk[0]:216 *C 97.060 59.783 +*N prog_clk[0]:217 *C 97.060 59.840 +*N prog_clk[0]:218 *C 90.425 50.320 +*N prog_clk[0]:219 *C 90.620 50.320 +*N prog_clk[0]:220 *C 116.148 47.600 +*N prog_clk[0]:221 *C 115.505 47.600 +*N prog_clk[0]:222 *C 115.460 47.600 +*N prog_clk[0]:223 *C 115.453 47.600 +*N prog_clk[0]:224 *C 112.045 28.560 +*N prog_clk[0]:225 *C 112.240 28.560 +*N prog_clk[0]:226 *C 112.240 28.605 +*N prog_clk[0]:227 *C 112.928 31.280 +*N prog_clk[0]:228 *C 112.240 31.280 +*N prog_clk[0]:229 *C 112.240 31.620 +*N prog_clk[0]:230 *C 112.240 31.575 +*N prog_clk[0]:231 *C 111.780 31.620 +*N prog_clk[0]:232 *C 111.780 33.320 +*N prog_clk[0]:233 *C 111.320 33.320 +*N prog_clk[0]:234 *C 110.270 39.440 +*N prog_clk[0]:235 *C 110.400 39.440 +*N prog_clk[0]:236 *C 111.320 39.440 +*N prog_clk[0]:237 *C 118.485 42.160 +*N prog_clk[0]:238 *C 118.220 42.160 +*N prog_clk[0]:239 *C 118.220 42.160 +*N prog_clk[0]:240 *C 118.213 42.160 +*N prog_clk[0]:241 *C 111.328 42.160 +*N prog_clk[0]:242 *C 111.320 42.160 +*N prog_clk[0]:243 *C 111.320 47.543 +*N prog_clk[0]:244 *C 111.320 47.600 +*N prog_clk[0]:245 *C 107.445 47.600 +*N prog_clk[0]:246 *C 107.180 47.600 +*N prog_clk[0]:247 *C 107.180 47.600 +*N prog_clk[0]:248 *C 107.180 47.600 +*N prog_clk[0]:249 *C 101.465 36.720 +*N prog_clk[0]:250 *C 101.660 36.720 +*N prog_clk[0]:251 *C 101.660 36.765 +*N prog_clk[0]:252 *C 101.660 47.543 +*N prog_clk[0]:253 *C 101.660 47.600 +*N prog_clk[0]:254 *C 98.907 47.600 +*N prog_clk[0]:255 *C 98.900 47.657 +*N prog_clk[0]:256 *C 99.165 50.320 +*N prog_clk[0]:257 *C 98.900 50.320 +*N prog_clk[0]:258 *C 98.900 50.320 +*N prog_clk[0]:259 *C 98.892 50.320 +*N prog_clk[0]:260 *C 94.988 42.160 +*N prog_clk[0]:261 *C 93.885 42.160 +*N prog_clk[0]:262 *C 93.840 42.205 +*N prog_clk[0]:263 *C 93.645 44.880 +*N prog_clk[0]:264 *C 93.840 44.540 +*N prog_clk[0]:265 *C 93.840 44.540 +*N prog_clk[0]:266 *C 93.840 50.263 +*N prog_clk[0]:267 *C 93.840 50.320 +*N prog_clk[0]:268 *C 90.627 50.320 +*N prog_clk[0]:269 *C 90.620 50.320 +*N prog_clk[0]:270 *C 90.620 53.040 +*N prog_clk[0]:271 *C 92.725 53.040 +*N prog_clk[0]:272 *C 92.920 53.040 +*N prog_clk[0]:273 *C 92.920 53.040 +*N prog_clk[0]:274 *C 92.913 53.040 +*N prog_clk[0]:275 *C 91.088 53.040 +*N prog_clk[0]:276 *C 91.080 53.098 +*N prog_clk[0]:277 *C 91.080 59.783 +*N prog_clk[0]:278 *C 91.080 59.840 +*N prog_clk[0]:279 *C 87.407 59.840 +*N prog_clk[0]:280 *C 87.400 59.898 +*N prog_clk[0]:281 *C 87.400 65.960 +*N prog_clk[0]:282 *C 87.392 65.960 +*N prog_clk[0]:283 *C 78.660 65.960 +*N prog_clk[0]:284 *C 86.708 39.440 +*N prog_clk[0]:285 *C 85.605 39.440 +*N prog_clk[0]:286 *C 85.560 39.440 +*N prog_clk[0]:287 *C 85.553 39.440 +*N prog_clk[0]:288 *C 78.668 39.440 +*N prog_clk[0]:289 *C 78.660 39.498 +*N prog_clk[0]:290 *C 78.465 42.160 +*N prog_clk[0]:291 *C 78.660 42.500 +*N prog_clk[0]:292 *C 78.660 42.500 +*N prog_clk[0]:293 *C 82.145 55.760 +*N prog_clk[0]:294 *C 81.880 55.760 +*N prog_clk[0]:295 *C 81.880 55.760 +*N prog_clk[0]:296 *C 81.873 55.760 +*N prog_clk[0]:297 *C 78.668 55.760 +*N prog_clk[0]:298 *C 78.660 55.760 +*N prog_clk[0]:299 *C 81.188 61.200 +*N prog_clk[0]:300 *C 80.085 61.200 +*N prog_clk[0]:301 *C 80.040 61.200 +*N prog_clk[0]:302 *C 80.032 61.200 +*N prog_clk[0]:303 *C 78.668 61.200 +*N prog_clk[0]:304 *C 78.660 61.200 +*N prog_clk[0]:305 *C 78.660 65.222 +*N prog_clk[0]:306 *C 78.660 65.288 +*N prog_clk[0]:307 *C 71.767 65.280 +*N prog_clk[0]:308 *C 71.760 65.280 +*N prog_clk[0]:309 *C 72.025 74.800 +*N prog_clk[0]:310 *C 71.760 75.140 +*N prog_clk[0]:311 *C 71.760 75.140 +*N prog_clk[0]:312 *C 71.760 77.463 +*N prog_clk[0]:313 *C 71.760 77.520 +*N prog_clk[0]:314 *C 67.168 77.520 +*N prog_clk[0]:315 *C 67.160 77.578 +*N prog_clk[0]:316 *C 65.675 80.240 +*N prog_clk[0]:317 *C 65.780 80.240 +*N prog_clk[0]:318 *C 67.160 80.240 +*N prog_clk[0]:319 *C 67.160 82.223 +*N prog_clk[0]:320 *C 67.160 82.288 +*N prog_clk[0]:321 *C 60.525 74.800 +*N prog_clk[0]:322 *C 60.260 74.800 +*N prog_clk[0]:323 *C 60.260 74.800 +*N prog_clk[0]:324 *C 60.948 63.920 +*N prog_clk[0]:325 *C 60.305 63.920 +*N prog_clk[0]:326 *C 60.260 63.920 +*N prog_clk[0]:327 *C 64.627 55.760 +*N prog_clk[0]:328 *C 63.525 55.760 +*N prog_clk[0]:329 *C 63.480 55.760 +*N prog_clk[0]:330 *C 63.473 55.760 +*N prog_clk[0]:331 *C 59.808 55.760 +*N prog_clk[0]:332 *C 59.800 55.818 +*N prog_clk[0]:333 *C 58.685 61.200 +*N prog_clk[0]:334 *C 58.880 61.200 +*N prog_clk[0]:335 *C 58.880 61.200 +*N prog_clk[0]:336 *C 59.800 61.200 +*N prog_clk[0]:337 *C 59.800 63.920 +*N prog_clk[0]:338 *C 59.800 74.800 +*N prog_clk[0]:339 *C 59.800 82.223 +*N prog_clk[0]:340 *C 59.800 82.280 +*N prog_clk[0]:341 *C 53.828 82.280 +*N prog_clk[0]:342 *C 53.820 82.338 +*N prog_clk[0]:343 *C 53.625 85.680 +*N prog_clk[0]:344 *C 53.820 86.020 +*N prog_clk[0]:345 *C 53.820 86.020 +*N prog_clk[0]:346 *C 53.820 93.103 +*N prog_clk[0]:347 *C 53.820 93.168 +*N prog_clk[0]:348 *C 51.528 93.160 +*N prog_clk[0]:349 *C 51.520 93.218 +*N prog_clk[0]:350 *C 51.325 96.560 +*N prog_clk[0]:351 *C 51.520 96.900 +*N prog_clk[0]:352 *C 51.490 96.870 +*N prog_clk[0]:353 *C 51.475 96.560 +*N prog_clk[0]:354 *C 51.060 96.560 +*N prog_clk[0]:355 *C 51.060 99.223 +*N prog_clk[0]:356 *C 51.053 99.280 +*N prog_clk[0]:357 *C 40.745 99.280 +*N prog_clk[0]:358 *C 40.480 99.280 +*N prog_clk[0]:359 *C 40.480 99.280 +*N prog_clk[0]:360 *C 40.480 99.280 +*N prog_clk[0]:361 *C 33.385 82.960 +*N prog_clk[0]:362 *C 33.120 82.960 +*N prog_clk[0]:363 *C 33.120 82.960 +*N prog_clk[0]:364 *C 37.985 36.720 +*N prog_clk[0]:365 *C 37.720 36.720 +*N prog_clk[0]:366 *C 37.720 36.675 +*N prog_clk[0]:367 *C 68.345 36.720 +*N prog_clk[0]:368 *C 68.080 36.720 +*N prog_clk[0]:369 *C 68.080 36.675 +*N prog_clk[0]:370 *C 68.080 35.418 +*N prog_clk[0]:371 *C 68.073 35.360 +*N prog_clk[0]:372 *C 63.285 25.840 +*N prog_clk[0]:373 *C 63.480 25.840 +*N prog_clk[0]:374 *C 63.480 25.885 +*N prog_clk[0]:375 *C 78.428 31.280 +*N prog_clk[0]:376 *C 77.325 31.280 +*N prog_clk[0]:377 *C 77.280 31.280 +*N prog_clk[0]:378 *C 77.273 31.280 +*N prog_clk[0]:379 *C 72.680 31.280 +*N prog_clk[0]:380 *C 73.865 23.120 +*N prog_clk[0]:381 *C 73.600 23.120 +*N prog_clk[0]:382 *C 73.600 23.165 +*N prog_clk[0]:383 *C 92.725 23.120 +*N prog_clk[0]:384 *C 92.920 23.120 +*N prog_clk[0]:385 *C 92.920 23.165 +*N prog_clk[0]:386 *C 92.920 25.783 +*N prog_clk[0]:387 *C 92.913 25.840 +*N prog_clk[0]:388 *C 91.345 25.840 +*N prog_clk[0]:389 *C 91.080 25.840 +*N prog_clk[0]:390 *C 91.080 25.840 +*N prog_clk[0]:391 *C 91.080 25.840 +*N prog_clk[0]:392 *C 82.605 25.840 +*N prog_clk[0]:393 *C 82.800 25.840 +*N prog_clk[0]:394 *C 82.800 25.840 +*N prog_clk[0]:395 *C 82.800 25.840 +*N prog_clk[0]:396 *C 73.608 25.840 +*N prog_clk[0]:397 *C 73.600 25.783 +*N prog_clk[0]:398 *C 72.680 25.840 +*N prog_clk[0]:399 *C 71.195 28.560 +*N prog_clk[0]:400 *C 71.300 28.560 +*N prog_clk[0]:401 *C 72.680 28.560 +*N prog_clk[0]:402 *C 72.680 30.543 +*N prog_clk[0]:403 *C 72.680 30.608 +*N prog_clk[0]:404 *C 63.488 30.600 +*N prog_clk[0]:405 *C 63.480 30.600 +*N prog_clk[0]:406 *C 63.480 35.303 +*N prog_clk[0]:407 *C 63.480 35.360 +*N prog_clk[0]:408 *C 59.605 34.000 +*N prog_clk[0]:409 *C 59.340 34.000 +*N prog_clk[0]:410 *C 59.340 34.045 +*N prog_clk[0]:411 *C 59.340 35.303 +*N prog_clk[0]:412 *C 59.340 35.360 +*N prog_clk[0]:413 *C 56.580 35.360 +*N prog_clk[0]:414 *C 56.845 36.720 +*N prog_clk[0]:415 *C 56.580 36.720 +*N prog_clk[0]:416 *C 56.580 36.675 +*N prog_clk[0]:417 *C 56.580 36.098 +*N prog_clk[0]:418 *C 56.580 36.032 +*N prog_clk[0]:419 *C 52.705 25.840 +*N prog_clk[0]:420 *C 52.900 25.840 +*N prog_clk[0]:421 *C 52.900 25.885 +*N prog_clk[0]:422 *C 52.900 35.983 +*N prog_clk[0]:423 *C 52.900 36.040 +*N prog_clk[0]:424 *C 47.645 36.720 +*N prog_clk[0]:425 *C 47.380 36.720 +*N prog_clk[0]:426 *C 47.380 36.675 +*N prog_clk[0]:427 *C 47.380 36.098 +*N prog_clk[0]:428 *C 47.380 36.040 +*N prog_clk[0]:429 *C 44.885 34.000 +*N prog_clk[0]:430 *C 44.620 34.000 +*N prog_clk[0]:431 *C 44.620 34.045 +*N prog_clk[0]:432 *C 44.620 35.983 +*N prog_clk[0]:433 *C 44.620 36.040 +*N prog_clk[0]:434 *C 38.188 36.040 +*N prog_clk[0]:435 *C 38.180 35.983 +*N prog_clk[0]:436 *C 38.445 28.560 +*N prog_clk[0]:437 *C 38.180 28.560 +*N prog_clk[0]:438 *C 38.180 28.605 +*N prog_clk[0]:439 *C 38.180 35.360 +*N prog_clk[0]:440 *C 37.720 35.360 +*N prog_clk[0]:441 *C 37.712 35.360 +*N prog_clk[0]:442 *C 14.065 36.720 +*N prog_clk[0]:443 *C 14.260 36.720 +*N prog_clk[0]:444 *C 14.260 36.720 +*N prog_clk[0]:445 *C 14.268 36.720 +*N prog_clk[0]:446 *C 16.553 36.720 +*N prog_clk[0]:447 *C 16.560 36.663 +*N prog_clk[0]:448 *C 16.825 34.000 +*N prog_clk[0]:449 *C 16.560 34.000 +*N prog_clk[0]:450 *C 16.560 34.045 +*N prog_clk[0]:451 *C 16.560 35.360 +*N prog_clk[0]:452 *C 16.568 35.360 +*N prog_clk[0]:453 *C 24.095 26.050 +*N prog_clk[0]:454 *C 23.920 26.180 +*N prog_clk[0]:455 *C 23.920 26.225 +*N prog_clk[0]:456 *C 23.920 35.303 +*N prog_clk[0]:457 *C 23.920 35.360 +*N prog_clk[0]:458 *C 28.785 31.280 +*N prog_clk[0]:459 *C 28.520 31.280 +*N prog_clk[0]:460 *C 28.520 31.325 +*N prog_clk[0]:461 *C 28.520 35.303 +*N prog_clk[0]:462 *C 28.520 35.360 +*N prog_clk[0]:463 *C 32.660 35.360 +*N prog_clk[0]:464 *C 32.660 35.418 +*N prog_clk[0]:465 *C 52.245 42.160 +*N prog_clk[0]:466 *C 51.980 42.160 +*N prog_clk[0]:467 *C 51.980 42.160 +*N prog_clk[0]:468 *C 51.973 42.160 +*N prog_clk[0]:469 *C 43.505 42.160 +*N prog_clk[0]:470 *C 43.700 42.160 +*N prog_clk[0]:471 *C 43.700 42.160 +*N prog_clk[0]:472 *C 43.700 42.160 +*N prog_clk[0]:473 *C 34.765 42.160 +*N prog_clk[0]:474 *C 34.500 42.160 +*N prog_clk[0]:475 *C 34.500 42.160 +*N prog_clk[0]:476 *C 34.500 42.160 +*N prog_clk[0]:477 *C 32.668 42.160 +*N prog_clk[0]:478 *C 32.660 42.160 +*N prog_clk[0]:479 *C 32.660 43.462 +*N prog_clk[0]:480 *C 32.653 43.520 +*N prog_clk[0]:481 *C 25.565 44.880 +*N prog_clk[0]:482 *C 25.760 44.880 +*N prog_clk[0]:483 *C 25.760 44.835 +*N prog_clk[0]:484 *C 24.680 42.160 +*N prog_clk[0]:485 *C 24.840 42.160 +*N prog_clk[0]:486 *C 24.840 42.205 +*N prog_clk[0]:487 *C 24.840 43.520 +*N prog_clk[0]:488 *C 25.760 43.578 +*N prog_clk[0]:489 *C 25.768 43.520 +*N prog_clk[0]:490 *C 30.360 43.520 +*N prog_clk[0]:491 *C 30.360 43.578 +*N prog_clk[0]:492 *C 28.785 50.320 +*N prog_clk[0]:493 *C 28.980 50.320 +*N prog_clk[0]:494 *C 28.980 50.320 +*N prog_clk[0]:495 *C 28.988 50.320 +*N prog_clk[0]:496 *C 30.353 50.320 +*N prog_clk[0]:497 *C 30.360 50.320 +*N prog_clk[0]:498 *C 32.428 58.480 +*N prog_clk[0]:499 *C 30.405 58.480 +*N prog_clk[0]:500 *C 41.205 50.320 +*N prog_clk[0]:501 *C 40.940 50.320 +*N prog_clk[0]:502 *C 40.940 50.365 +*N prog_clk[0]:503 *C 49.907 50.320 +*N prog_clk[0]:504 *C 49.265 50.320 +*N prog_clk[0]:505 *C 49.220 50.365 +*N prog_clk[0]:506 *C 49.220 53.040 +*N prog_clk[0]:507 *C 48.105 53.040 +*N prog_clk[0]:508 *C 48.300 53.040 +*N prog_clk[0]:509 *C 48.300 53.040 +*N prog_clk[0]:510 *C 48.293 53.040 +*N prog_clk[0]:511 *C 40.948 53.040 +*N prog_clk[0]:512 *C 40.940 53.040 +*N prog_clk[0]:513 *C 41.628 58.480 +*N prog_clk[0]:514 *C 40.985 58.480 +*N prog_clk[0]:515 *C 40.940 58.480 +*N prog_clk[0]:516 *C 40.933 58.480 +*N prog_clk[0]:517 *C 30.367 58.480 +*N prog_clk[0]:518 *C 30.360 58.480 +*N prog_clk[0]:519 *C 28.785 63.920 +*N prog_clk[0]:520 *C 28.980 63.920 +*N prog_clk[0]:521 *C 28.980 63.920 +*N prog_clk[0]:522 *C 28.988 63.920 +*N prog_clk[0]:523 *C 30.353 63.920 +*N prog_clk[0]:524 *C 30.360 63.920 +*N prog_clk[0]:525 *C 15.905 72.080 +*N prog_clk[0]:526 *C 15.640 72.080 +*N prog_clk[0]:527 *C 15.640 72.035 +*N prog_clk[0]:528 *C 16.343 44.880 +*N prog_clk[0]:529 *C 15.685 44.880 +*N prog_clk[0]:530 *C 15.640 44.925 +*N prog_clk[0]:531 *C 12.225 55.760 +*N prog_clk[0]:532 *C 12.420 55.760 +*N prog_clk[0]:533 *C 12.420 55.760 +*N prog_clk[0]:534 *C 12.428 55.760 +*N prog_clk[0]:535 *C 15.633 55.760 +*N prog_clk[0]:536 *C 15.640 55.760 +*N prog_clk[0]:537 *C 15.905 61.200 +*N prog_clk[0]:538 *C 15.640 60.860 +*N prog_clk[0]:539 *C 15.640 60.860 +*N prog_clk[0]:540 *C 12.225 66.640 +*N prog_clk[0]:541 *C 12.280 66.640 +*N prog_clk[0]:542 *C 12.288 66.640 +*N prog_clk[0]:543 *C 15.633 66.640 +*N prog_clk[0]:544 *C 15.640 66.640 +*N prog_clk[0]:545 *C 15.640 70.720 +*N prog_clk[0]:546 *C 15.648 70.720 +*N prog_clk[0]:547 *C 26.945 69.360 +*N prog_clk[0]:548 *C 26.680 69.360 +*N prog_clk[0]:549 *C 26.680 69.405 +*N prog_clk[0]:550 *C 26.680 70.663 +*N prog_clk[0]:551 *C 26.680 70.720 +*N prog_clk[0]:552 *C 30.353 70.720 +*N prog_clk[0]:553 *C 30.360 70.720 +*N prog_clk[0]:554 *C 35.188 74.800 +*N prog_clk[0]:555 *C 33.625 74.800 +*N prog_clk[0]:556 *C 33.580 74.800 +*N prog_clk[0]:557 *C 33.573 74.800 +*N prog_clk[0]:558 *C 30.367 74.800 +*N prog_clk[0]:559 *C 30.360 74.800 +*N prog_clk[0]:560 *C 31.508 77.520 +*N prog_clk[0]:561 *C 30.360 77.520 +*N prog_clk[0]:562 *C 30.360 77.180 +*N prog_clk[0]:563 *C 30.360 77.180 +*N prog_clk[0]:564 *C 30.360 82.903 +*N prog_clk[0]:565 *C 30.367 82.960 +*N prog_clk[0]:566 *C 32.653 82.960 +*N prog_clk[0]:567 *C 32.660 82.960 +*N prog_clk[0]:568 *C 43.965 74.800 +*N prog_clk[0]:569 *C 43.700 74.800 +*N prog_clk[0]:570 *C 43.700 74.845 +*N prog_clk[0]:571 *C 50.828 77.520 +*N prog_clk[0]:572 *C 50.185 77.520 +*N prog_clk[0]:573 *C 50.140 77.520 +*N prog_clk[0]:574 *C 50.133 77.520 +*N prog_clk[0]:575 *C 43.708 77.520 +*N prog_clk[0]:576 *C 43.700 77.463 +*N prog_clk[0]:577 *C 42.780 77.520 +*N prog_clk[0]:578 *C 42.585 82.960 +*N prog_clk[0]:579 *C 42.780 82.620 +*N prog_clk[0]:580 *C 42.780 82.620 +*N prog_clk[0]:581 *C 42.780 85.623 +*N prog_clk[0]:582 *C 42.773 85.680 +*N prog_clk[0]:583 *C 35.685 85.680 +*N prog_clk[0]:584 *C 35.420 85.680 +*N prog_clk[0]:585 *C 35.420 85.680 +*N prog_clk[0]:586 *C 35.420 85.680 +*N prog_clk[0]:587 *C 32.668 85.680 +*N prog_clk[0]:588 *C 32.660 85.680 +*N prog_clk[0]:589 *C 32.005 91.120 +*N prog_clk[0]:590 *C 32.200 91.460 +*N prog_clk[0]:591 *C 32.615 91.460 +*N prog_clk[0]:592 *C 32.660 91.460 +*N prog_clk[0]:593 *C 32.660 99.223 +*N prog_clk[0]:594 *C 32.660 99.280 +*N prog_clk[0]:595 *C 30.828 99.280 +*N prog_clk[0]:596 *C 30.820 99.280 + +*CAP +0 prog_clk[0] 9.843634e-05 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +5 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +6 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +7 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +8 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +9 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +10 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +12 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +13 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +14 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +15 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +16 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +17 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +18 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +19 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +20 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +21 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +22 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +23 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +24 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +25 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +26 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +27 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +28 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +29 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +30 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +31 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +32 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +33 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +37 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +39 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +40 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +41 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +42 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +43 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +44 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +45 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +46 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +47 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +49 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +50 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +51 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +52 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +53 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +54 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +55 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +57 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +58 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +59 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +60 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +61 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +62 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +63 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +64 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +65 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +66 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +67 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +68 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +69 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +70 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +71 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +72 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +73 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +74 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +75 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +76 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +77 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +78 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +79 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +80 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +81 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +82 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +83 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +84 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +85 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +86 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +87 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +88 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +89 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +90 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +91 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +92 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +93 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +94 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +95 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +96 prog_clk[0]:96 6.077112e-05 +97 prog_clk[0]:97 6.077112e-05 +98 prog_clk[0]:98 5.519067e-05 +99 prog_clk[0]:99 5.870999e-05 +100 prog_clk[0]:100 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chanx_left_in[13]:26 0.0004263675 +794 prog_clk[0]:511 chanx_left_in[13]:27 0.0004263675 +795 prog_clk[0]:306 chanx_left_in[13]:18 0.0003851567 +796 prog_clk[0]:235 chanx_left_in[13]:15 8.454123e-06 +797 prog_clk[0]:134 chanx_left_in[13]:7 1.332004e-05 +798 prog_clk[0]:217 chanx_left_in[13]:18 3.294113e-06 +799 prog_clk[0]:105 chanx_left_in[13]:8 1.364537e-06 +800 prog_clk[0]:106 chanx_left_in[13]:7 1.364537e-06 +801 prog_clk[0]:236 chanx_left_in[13]:14 8.454123e-06 +802 prog_clk[0]:283 chanx_left_in[13]:19 0.0001370889 +803 prog_clk[0]:242 chanx_left_in[14]:12 1.986931e-06 +804 prog_clk[0]:242 chanx_left_in[14]:13 1.621116e-05 +805 prog_clk[0]:241 chanx_left_in[14]:14 0.0003229805 +806 prog_clk[0]:241 chanx_left_in[14]:15 8.628059e-05 +807 prog_clk[0]:240 chanx_left_in[14]:8 0.0003229805 +808 prog_clk[0]:240 chanx_left_in[14]:14 8.628059e-05 +809 prog_clk[0]:243 chanx_left_in[14]:12 1.621116e-05 +810 prog_clk[0]:417 chanx_left_in[14]:22 4.263904e-06 +811 prog_clk[0]:418 chanx_left_in[14]:21 1.678655e-05 +812 prog_clk[0]:416 chanx_left_in[14]:21 4.263904e-06 +813 prog_clk[0]:411 chanx_left_in[14]:21 1.841263e-05 +814 prog_clk[0]:410 chanx_left_in[14]:22 1.841263e-05 +815 prog_clk[0]:236 chanx_left_in[14]:13 1.986931e-06 +816 prog_clk[0]:413 chanx_left_in[14]:22 1.678655e-05 +817 prog_clk[0]:288 chanx_left_in[16]:26 0.00039539 +818 prog_clk[0]:287 chanx_left_in[16]:25 0.00039539 +819 prog_clk[0]:370 chanx_left_in[16]:33 3.68786e-05 +820 prog_clk[0]:369 chanx_left_in[16]:32 3.68786e-05 +821 prog_clk[0]:235 chanx_left_in[16]:26 8.454123e-06 +822 prog_clk[0]:236 chanx_left_in[16]:25 8.454123e-06 +823 prog_clk[0]:181 chany_top_in[5] 2.098906e-05 +824 prog_clk[0]:178 chany_top_in[5]:17 2.098906e-05 +825 prog_clk[0]:339 chany_top_in[5] 0.0001859833 +826 prog_clk[0]:339 chany_top_in[5]:16 5.796884e-06 +827 prog_clk[0]:175 chany_top_in[5] 2.068575e-05 +828 prog_clk[0]:174 chany_top_in[5]:17 2.068575e-05 +829 prog_clk[0]:323 chany_top_in[5]:16 3.120997e-06 +830 prog_clk[0]:337 chany_top_in[5]:13 1.233031e-06 +831 prog_clk[0]:337 chany_top_in[5]:15 1.630857e-05 +832 prog_clk[0]:338 chany_top_in[5]:17 0.0001891043 +833 prog_clk[0]:338 chany_top_in[5]:16 1.630857e-05 +834 prog_clk[0]:338 chany_top_in[5]:15 5.796884e-06 +835 prog_clk[0]:338 chany_top_in[5]:14 1.233031e-06 +836 prog_clk[0]:341 chany_top_in[13]:8 1.239235e-05 +837 prog_clk[0]:182 chany_top_in[13]:14 2.318916e-07 +838 prog_clk[0]:177 chany_top_in[13]:13 2.325561e-05 +839 prog_clk[0]:320 chany_top_in[13]:7 0.0001453183 +840 prog_clk[0]:339 chany_top_in[13]:12 3.926628e-05 +841 prog_clk[0]:340 chany_top_in[13]:8 0.0001453183 +842 prog_clk[0]:340 chany_top_in[13]:7 1.239235e-05 +843 prog_clk[0]:187 chany_top_in[13]:7 1.055891e-05 +844 prog_clk[0]:171 chany_top_in[13]:14 2.748074e-05 +845 prog_clk[0]:317 chany_top_in[13]:8 7.589805e-06 +846 prog_clk[0]:175 chany_top_in[13] 2.306707e-06 +847 prog_clk[0]:176 chany_top_in[13]:13 2.748074e-05 +848 prog_clk[0]:176 chany_top_in[13]:14 2.325561e-05 +849 prog_clk[0]:174 chany_top_in[13]:15 2.306707e-06 +850 prog_clk[0]:338 chany_top_in[13]:11 3.926628e-05 +851 prog_clk[0]:318 chany_top_in[13]:7 7.589805e-06 +852 prog_clk[0]:183 chany_top_in[13]:13 2.318916e-07 +853 prog_clk[0]:188 chany_top_in[13]:8 1.055891e-05 +854 prog_clk[0]:289 top_left_grid_pin_34_[0]:17 2.806017e-07 +855 prog_clk[0]:594 top_left_grid_pin_34_[0]:42 0.0001196598 +856 prog_clk[0]:360 top_left_grid_pin_34_[0]:42 3.163083e-05 +857 prog_clk[0]:360 top_left_grid_pin_34_[0]:41 0.0001196598 +858 prog_clk[0]:360 top_left_grid_pin_34_[0]:40 0.0004013823 +859 prog_clk[0]:356 top_left_grid_pin_34_[0]:41 3.163083e-05 +860 prog_clk[0]:356 top_left_grid_pin_34_[0]:39 0.0004013823 +861 prog_clk[0]:262 top_left_grid_pin_34_[0]:8 7.753749e-06 +862 prog_clk[0]:265 top_left_grid_pin_34_[0]:9 7.753749e-06 +863 prog_clk[0]:292 top_left_grid_pin_34_[0]:18 2.806017e-07 +864 prog_clk[0]:292 top_left_grid_pin_34_[0]:17 4.310336e-08 +865 prog_clk[0]:298 top_left_grid_pin_34_[0]:18 4.310336e-08 +866 prog_clk[0]:337 top_left_grid_pin_34_[0]:31 1.347082e-06 +867 prog_clk[0]:338 top_left_grid_pin_34_[0]:32 1.347082e-06 +868 prog_clk[0] top_left_grid_pin_37_[0] 3.203321e-05 +869 prog_clk[0]:596 top_left_grid_pin_37_[0]:26 3.203321e-05 +870 prog_clk[0]:593 top_left_grid_pin_37_[0] 0.0001681479 +871 prog_clk[0]:592 top_left_grid_pin_37_[0]:26 0.0001681479 +872 prog_clk[0]:292 top_left_grid_pin_37_[0]:10 1.054373e-05 +873 prog_clk[0]:298 top_left_grid_pin_37_[0]:9 1.054373e-05 +874 prog_clk[0]:331 top_left_grid_pin_37_[0]:12 4.894521e-05 +875 prog_clk[0]:330 top_left_grid_pin_37_[0]:11 4.894521e-05 +876 prog_clk[0]:259 chanx_right_in[7]:7 7.357873e-05 +877 prog_clk[0]:268 chanx_right_in[7]:6 3.853133e-05 +878 prog_clk[0]:253 chanx_right_in[7]:6 0.0003013224 +879 prog_clk[0]:253 chanx_right_in[7]:7 0.0001578866 +880 prog_clk[0]:223 chanx_right_in[7]:7 0.0002430885 +881 prog_clk[0]:254 chanx_right_in[7]:6 0.0001578866 +882 prog_clk[0]:244 chanx_right_in[7]:6 0.0002430885 +883 prog_clk[0]:244 chanx_right_in[7]:7 0.0002284681 +884 prog_clk[0]:248 chanx_right_in[7]:6 0.0002284681 +885 prog_clk[0]:248 chanx_right_in[7]:7 0.0003013224 +886 prog_clk[0]:267 chanx_right_in[7]:6 7.357873e-05 +887 prog_clk[0]:267 chanx_right_in[7]:7 3.853133e-05 +888 prog_clk[0]:292 chanx_right_in[7]:5 4.230829e-05 +889 prog_clk[0]:298 chanx_right_in[7]:4 4.230829e-05 +890 prog_clk[0]:126 right_top_grid_pin_49_[0]:19 0.0001010323 +891 prog_clk[0]:126 right_top_grid_pin_49_[0]:18 0.0005755537 +892 prog_clk[0]:128 right_top_grid_pin_49_[0]:11 2.573178e-05 +893 prog_clk[0]:127 right_top_grid_pin_49_[0]:18 0.0001010323 +894 prog_clk[0]:127 right_top_grid_pin_49_[0]:14 0.0003067129 +895 prog_clk[0]:111 right_top_grid_pin_49_[0]:19 0.0002688408 +896 prog_clk[0]:106 right_top_grid_pin_49_[0]:10 2.573178e-05 +897 prog_clk[0]:575 chanx_left_in[1]:7 0.0003551776 +898 prog_clk[0]:574 chanx_left_in[1]:6 0.0003551776 +899 prog_clk[0]:341 chanx_left_in[1]:7 7.067414e-07 +900 prog_clk[0]:313 chanx_left_in[1]:6 0.0002530274 +901 prog_clk[0]:313 chanx_left_in[1]:7 0.0003269819 +902 prog_clk[0]:558 chanx_left_in[1]:9 0.0001963311 +903 prog_clk[0]:557 chanx_left_in[1]:8 0.0001963311 +904 prog_clk[0]:314 chanx_left_in[1]:7 0.0002530274 +905 prog_clk[0]:320 chanx_left_in[1]:6 8.170623e-07 +906 prog_clk[0]:340 chanx_left_in[1]:6 7.067414e-07 +907 prog_clk[0]:340 chanx_left_in[1]:7 8.170623e-07 +908 prog_clk[0]:550 chanx_left_in[1]:10 9.282558e-07 +909 prog_clk[0]:549 chanx_left_in[1]:11 9.282558e-07 +910 prog_clk[0]:535 chanx_left_in[1]:12 0.0001951114 +911 prog_clk[0]:534 chanx_left_in[1]:13 0.0001951114 +912 prog_clk[0]:197 chanx_left_in[1]:6 0.0003269819 +913 prog_clk[0]:552 chanx_left_in[7]:10 0.0002084124 +914 prog_clk[0]:546 chanx_left_in[7]:11 0.0006339962 +915 prog_clk[0]:586 chanx_left_in[7]:7 5.155337e-05 +916 prog_clk[0]:551 chanx_left_in[7]:10 0.0006339962 +917 prog_clk[0]:551 chanx_left_in[7]:11 0.0002084124 +918 prog_clk[0]:582 chanx_left_in[7]:6 5.155337e-05 +919 prog_clk[0]:518 left_top_grid_pin_43_[0]:16 8.82924e-09 +920 prog_clk[0]:518 left_top_grid_pin_43_[0]:15 1.559832e-07 +921 prog_clk[0]:464 left_top_grid_pin_43_[0]:7 0.0001858508 +922 prog_clk[0]:479 left_top_grid_pin_43_[0]:8 4.1245e-05 +923 prog_clk[0]:588 left_top_grid_pin_43_[0]:22 1.14839e-05 +924 prog_clk[0]:588 left_top_grid_pin_43_[0]:20 2.533648e-07 +925 prog_clk[0]:588 left_top_grid_pin_43_[0]:21 2.996796e-05 +926 prog_clk[0]:593 left_top_grid_pin_43_[0]:22 1.707355e-06 +927 prog_clk[0]:553 left_top_grid_pin_43_[0]:19 0.0001028979 +928 prog_clk[0]:553 left_top_grid_pin_43_[0]:20 0.0001214584 +929 prog_clk[0]:567 left_top_grid_pin_43_[0]:19 2.533648e-07 +930 prog_clk[0]:567 left_top_grid_pin_43_[0]:21 1.14839e-05 +931 prog_clk[0]:564 left_top_grid_pin_43_[0]:20 0.0001688208 +932 prog_clk[0]:478 left_top_grid_pin_43_[0]:8 0.0001858508 +933 prog_clk[0]:478 left_top_grid_pin_43_[0]:7 4.1245e-05 +934 prog_clk[0]:461 left_top_grid_pin_43_[0]:8 7.930815e-07 +935 prog_clk[0]:460 left_top_grid_pin_43_[0]:7 7.930815e-07 +936 prog_clk[0]:559 left_top_grid_pin_43_[0]:19 6.362403e-05 +937 prog_clk[0]:559 left_top_grid_pin_43_[0]:20 0.0001028979 +938 prog_clk[0]:592 left_top_grid_pin_43_[0]:22 2.996796e-05 +939 prog_clk[0]:592 left_top_grid_pin_43_[0]:21 1.707355e-06 +940 prog_clk[0]:550 left_top_grid_pin_43_[0]:20 2.79717e-07 +941 prog_clk[0]:549 left_top_grid_pin_43_[0]:19 2.79717e-07 +942 prog_clk[0]:524 left_top_grid_pin_43_[0]:19 0.0001214584 +943 prog_clk[0]:524 left_top_grid_pin_43_[0]:16 1.559832e-07 +944 prog_clk[0]:563 left_top_grid_pin_43_[0]:19 0.0001688208 +945 prog_clk[0]:563 left_top_grid_pin_43_[0]:20 6.362403e-05 +946 prog_clk[0]:497 left_top_grid_pin_43_[0]:15 8.82924e-09 +947 prog_clk[0]:576 mux_tree_tapbuf_size10_0_sram[0]:12 1.483504e-05 +948 prog_clk[0]:341 mux_tree_tapbuf_size10_0_sram[0]:22 0.0001133073 +949 prog_clk[0]:553 mux_tree_tapbuf_size10_0_sram[0]:14 3.133518e-07 +950 prog_clk[0]:559 mux_tree_tapbuf_size10_0_sram[0]:14 7.532494e-08 +951 prog_clk[0]:559 mux_tree_tapbuf_size10_0_sram[0]:16 4.632403e-07 +952 prog_clk[0]:559 mux_tree_tapbuf_size10_0_sram[0]:15 3.133518e-07 +953 prog_clk[0]:558 mux_tree_tapbuf_size10_0_sram[0]:16 1.266804e-05 +954 prog_clk[0]:557 mux_tree_tapbuf_size10_0_sram[0]:15 1.266804e-05 +955 prog_clk[0]:320 mux_tree_tapbuf_size10_0_sram[0]:23 0.0001391667 +956 prog_clk[0]:340 mux_tree_tapbuf_size10_0_sram[0]:23 0.0001133073 +957 prog_clk[0]:340 mux_tree_tapbuf_size10_0_sram[0]:22 0.0001391667 +958 prog_clk[0]:586 mux_tree_tapbuf_size10_0_sram[0]:22 7.515775e-05 +959 prog_clk[0]:187 mux_tree_tapbuf_size10_0_sram[0]:23 6.555347e-05 +960 prog_clk[0]:563 mux_tree_tapbuf_size10_0_sram[0]:17 4.632403e-07 +961 prog_clk[0]:563 mux_tree_tapbuf_size10_0_sram[0]:15 7.532494e-08 +962 prog_clk[0]:582 mux_tree_tapbuf_size10_0_sram[0]:23 7.515775e-05 +963 prog_clk[0]:577 mux_tree_tapbuf_size10_0_sram[0]:19 1.483504e-05 +964 prog_clk[0]:188 mux_tree_tapbuf_size10_0_sram[0]:22 6.555347e-05 +965 prog_clk[0]:593 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 5.585732e-05 +966 prog_clk[0]:592 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 5.585732e-05 +967 prog_clk[0]:349 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 3.189249e-05 +968 prog_clk[0]:355 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 5.52105e-07 +969 prog_clk[0]:352 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 6.715765e-06 +970 prog_clk[0]:354 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 9.726697e-06 +971 prog_clk[0]:354 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 5.52105e-07 +972 prog_clk[0]:353 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 9.726697e-06 +973 prog_clk[0]:353 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 6.715765e-06 +974 prog_clk[0]:353 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 3.189249e-05 +975 prog_clk[0]:279 mux_tree_tapbuf_size3_0_sram[0]:17 7.188732e-05 +976 prog_clk[0]:308 mux_tree_tapbuf_size3_0_sram[0]:11 1.665547e-06 +977 prog_clk[0]:278 mux_tree_tapbuf_size3_0_sram[0]:17 0.000133978 +978 prog_clk[0]:278 mux_tree_tapbuf_size3_0_sram[0]:18 7.188732e-05 +979 prog_clk[0]:306 mux_tree_tapbuf_size3_0_sram[0]:15 1.205015e-05 +980 prog_clk[0]:124 mux_tree_tapbuf_size3_0_sram[0]:20 1.250687e-05 +981 prog_clk[0]:121 mux_tree_tapbuf_size3_0_sram[0]:19 1.250687e-05 +982 prog_clk[0]:121 mux_tree_tapbuf_size3_0_sram[0]:22 9.813707e-06 +983 prog_clk[0]:114 mux_tree_tapbuf_size3_0_sram[0]:19 2.553867e-06 +984 prog_clk[0]:204 mux_tree_tapbuf_size3_0_sram[0]:11 2.302284e-05 +985 prog_clk[0]:204 mux_tree_tapbuf_size3_0_sram[0]:10 1.665547e-06 +986 prog_clk[0]:201 mux_tree_tapbuf_size3_0_sram[0]:12 7.536129e-07 +987 prog_clk[0]:212 mux_tree_tapbuf_size3_0_sram[0]:18 0.0002024224 +988 prog_clk[0]:217 mux_tree_tapbuf_size3_0_sram[0]:17 0.0002024224 +989 prog_clk[0]:217 mux_tree_tapbuf_size3_0_sram[0]:18 0.000133978 +990 prog_clk[0]:200 mux_tree_tapbuf_size3_0_sram[0]:10 2.302284e-05 +991 prog_clk[0]:202 mux_tree_tapbuf_size3_0_sram[0]:13 7.536129e-07 +992 prog_clk[0]:115 mux_tree_tapbuf_size3_0_sram[0]:21 9.813707e-06 +993 prog_clk[0]:115 mux_tree_tapbuf_size3_0_sram[0]:20 2.553867e-06 +994 prog_clk[0]:283 mux_tree_tapbuf_size3_0_sram[0]:6 1.205015e-05 +995 prog_clk[0]:252 mux_tree_tapbuf_size4_0_sram[0]:10 6.17402e-05 +996 prog_clk[0]:252 mux_tree_tapbuf_size4_0_sram[0]:6 3.55575e-05 +997 prog_clk[0]:251 mux_tree_tapbuf_size4_0_sram[0]:5 3.55575e-05 +998 prog_clk[0]:251 mux_tree_tapbuf_size4_0_sram[0]:9 6.17402e-05 +999 prog_clk[0]:530 mux_tree_tapbuf_size6_1_sram[1]:9 3.90516e-06 +1000 prog_clk[0]:518 mux_tree_tapbuf_size6_1_sram[1]:17 1.808389e-08 +1001 prog_clk[0]:517 mux_tree_tapbuf_size6_1_sram[1]:18 0.0004970907 +1002 prog_clk[0]:516 mux_tree_tapbuf_size6_1_sram[1]:19 0.0004970907 +1003 prog_clk[0]:524 mux_tree_tapbuf_size6_1_sram[1]:16 1.808389e-08 +1004 prog_clk[0]:536 mux_tree_tapbuf_size6_1_sram[1]:12 1.12381e-05 +1005 prog_clk[0]:536 mux_tree_tapbuf_size6_1_sram[1]:9 1.858856e-05 +1006 prog_clk[0]:539 mux_tree_tapbuf_size6_1_sram[1]:12 1.858856e-05 +1007 prog_clk[0]:539 mux_tree_tapbuf_size6_1_sram[1]:13 7.33294e-06 +1008 prog_clk[0]:319 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 4.431223e-05 +1009 prog_clk[0]:320 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 1.369278e-05 +1010 prog_clk[0]:318 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 4.431223e-05 +1011 prog_clk[0]:188 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 1.369278e-05 +1012 prog_clk[0]:126 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 0.0001117121 +1013 prog_clk[0]:128 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 6.751513e-06 +1014 prog_clk[0]:127 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 0.0001117121 +1015 prog_clk[0]:134 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 6.751513e-06 +1016 prog_clk[0]:457 optlc_net_121:11 3.848214e-06 +1017 prog_clk[0]:457 optlc_net_121:10 2.300967e-05 +1018 prog_clk[0]:464 optlc_net_121:15 0.0001363058 +1019 prog_clk[0]:464 optlc_net_121:12 4.954493e-05 +1020 prog_clk[0]:463 optlc_net_121:11 3.275689e-05 +1021 prog_clk[0]:463 optlc_net_121:10 2.83082e-06 +1022 prog_clk[0]:479 optlc_net_121:6 4.1245e-05 +1023 prog_clk[0]:452 optlc_net_121:10 3.848214e-06 +1024 prog_clk[0]:478 optlc_net_121:15 4.954493e-05 +1025 prog_clk[0]:478 optlc_net_121:16 0.0001775508 +1026 prog_clk[0]:462 optlc_net_121:11 2.300967e-05 +1027 prog_clk[0]:462 optlc_net_121:10 3.275689e-05 +1028 prog_clk[0]:441 optlc_net_121:11 2.83082e-06 +1029 prog_clk[0]:545 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.663689e-05 +1030 prog_clk[0]:544 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.663689e-05 +1031 prog_clk[0]:544 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.652539e-05 +1032 prog_clk[0]:539 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.652539e-05 +1033 prog_clk[0]:491 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001719274 +1034 prog_clk[0]:457 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.214219e-06 +1035 prog_clk[0]:518 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001377072 +1036 prog_clk[0]:464 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.058389e-07 +1037 prog_clk[0]:478 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.058389e-07 +1038 prog_clk[0]:461 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.560096e-06 +1039 prog_clk[0]:462 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.214219e-06 +1040 prog_clk[0]:460 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.560096e-06 +1041 prog_clk[0]:497 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001377072 +1042 prog_clk[0]:497 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001719274 +1043 prog_clk[0]:438 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.747937e-05 +1044 prog_clk[0]:439 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.747937e-05 +1045 prog_clk[0]:405 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001243134 +1046 prog_clk[0]:405 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.229106e-05 +1047 prog_clk[0]:374 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001243134 +1048 prog_clk[0]:406 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.229106e-05 +1049 prog_clk[0]:126 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.46397e-06 +1050 prog_clk[0]:127 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.46397e-06 +1051 prog_clk[0]:133 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.031739e-05 +1052 prog_clk[0]:132 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.031739e-05 +1053 prog_clk[0]:140 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.529758e-05 +1054 prog_clk[0]:139 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.529758e-05 +1055 prog_clk[0]:128 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.699038e-05 +1056 prog_clk[0]:144 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.211062e-06 +1057 prog_clk[0]:134 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.36668e-06 +1058 prog_clk[0]:134 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.699038e-05 +1059 prog_clk[0]:134 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.666892e-05 +1060 prog_clk[0]:141 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.211062e-06 +1061 prog_clk[0]:135 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.666892e-05 +1062 prog_clk[0]:135 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.36668e-06 +1063 prog_clk[0]:230 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 2.0212e-07 +1064 prog_clk[0]:230 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:6 1.71068e-05 +1065 prog_clk[0]:242 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 1.644615e-05 +1066 prog_clk[0]:242 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 2.784415e-05 +1067 prog_clk[0]:243 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 2.784415e-05 +1068 prog_clk[0]:226 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 2.0212e-07 +1069 prog_clk[0]:226 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:5 1.71068e-05 +1070 prog_clk[0]:236 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 4.482159e-05 +1071 prog_clk[0]:236 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 1.644615e-05 +1072 prog_clk[0]:233 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 4.482159e-05 +1073 prog_clk[0]:232 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:10 3.983767e-06 +1074 prog_clk[0]:231 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:9 3.983767e-06 +1075 prog_clk[0]:211 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 1.654185e-05 +1076 prog_clk[0]:209 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 2.823827e-05 +1077 prog_clk[0]:210 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 1.654185e-05 +1078 prog_clk[0]:208 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 2.823827e-05 +1079 prog_clk[0]:530 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.784501e-05 +1080 prog_clk[0]:536 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.784501e-05 +1081 prog_clk[0]:126 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002627853 +1082 prog_clk[0]:127 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002627853 + +*RES +0 prog_clk[0] prog_clk[0]:596 0.002491072 +1 prog_clk[0]:281 prog_clk[0]:280 0.005412947 +2 prog_clk[0]:281 prog_clk[0]:207 0.0005669644 +3 prog_clk[0]:282 prog_clk[0]:281 0.00341 +4 prog_clk[0]:528 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +5 prog_clk[0]:529 prog_clk[0]:528 0.0005870537 +6 prog_clk[0]:530 prog_clk[0]:529 0.0045 +7 prog_clk[0]:467 prog_clk[0]:466 0.0045 +8 prog_clk[0]:468 prog_clk[0]:467 0.00341 +9 prog_clk[0]:466 prog_clk[0]:465 0.0001440218 +10 prog_clk[0]:465 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +11 prog_clk[0]:576 prog_clk[0]:575 0.00341 +12 prog_clk[0]:576 prog_clk[0]:570 0.002337054 +13 prog_clk[0]:575 prog_clk[0]:574 0.001006583 +14 prog_clk[0]:573 prog_clk[0]:572 0.0045 +15 prog_clk[0]:574 prog_clk[0]:573 0.00341 +16 prog_clk[0]:572 prog_clk[0]:571 0.0005736608 +17 prog_clk[0]:571 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +18 prog_clk[0]:289 prog_clk[0]:288 0.00341 +19 prog_clk[0]:288 prog_clk[0]:287 0.00107865 +20 prog_clk[0]:286 prog_clk[0]:285 0.0045 +21 prog_clk[0]:287 prog_clk[0]:286 0.00341 +22 prog_clk[0]:285 prog_clk[0]:284 0.000984375 +23 prog_clk[0]:284 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +24 prog_clk[0]:491 prog_clk[0]:490 0.00341 +25 prog_clk[0]:490 prog_clk[0]:489 0.0007194916 +26 prog_clk[0]:490 prog_clk[0]:480 0.0003591583 +27 prog_clk[0]:342 prog_clk[0]:341 0.00341 +28 prog_clk[0]:341 prog_clk[0]:340 0.0009356915 +29 prog_clk[0]:456 prog_clk[0]:455 0.008104911 +30 prog_clk[0]:457 prog_clk[0]:456 0.00341 +31 prog_clk[0]:457 prog_clk[0]:452 0.001151892 +32 prog_clk[0]:454 prog_clk[0]:453 9.51087e-05 +33 prog_clk[0]:455 prog_clk[0]:454 0.0045 +34 prog_clk[0]:453 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +35 prog_clk[0]:518 prog_clk[0]:517 0.00341 +36 prog_clk[0]:518 prog_clk[0]:499 0.0045 +37 prog_clk[0]:518 prog_clk[0]:497 0.007285715 +38 prog_clk[0]:517 prog_clk[0]:516 0.001655183 +39 prog_clk[0]:515 prog_clk[0]:514 0.0045 +40 prog_clk[0]:515 prog_clk[0]:512 0.004857143 +41 prog_clk[0]:516 prog_clk[0]:515 0.00341 +42 prog_clk[0]:596 prog_clk[0]:595 0.00341 +43 prog_clk[0]:596 prog_clk[0]:97 0.0045 +44 prog_clk[0]:595 prog_clk[0]:594 0.0002870917 +45 prog_clk[0]:397 prog_clk[0]:396 0.00341 +46 prog_clk[0]:397 prog_clk[0]:382 0.002337054 +47 prog_clk[0]:396 prog_clk[0]:395 0.001440158 +48 prog_clk[0]:280 prog_clk[0]:279 0.00341 +49 prog_clk[0]:279 prog_clk[0]:278 0.0005753583 +50 prog_clk[0]:464 prog_clk[0]:463 0.00341 +51 prog_clk[0]:463 prog_clk[0]:462 0.0006485999 +52 prog_clk[0]:463 prog_clk[0]:441 0.0007915583 +53 prog_clk[0]:488 prog_clk[0]:487 0.0008214285 +54 prog_clk[0]:488 prog_clk[0]:483 0.001122768 +55 prog_clk[0]:489 prog_clk[0]:488 0.00341 +56 prog_clk[0]:479 prog_clk[0]:478 0.001162947 +57 prog_clk[0]:480 prog_clk[0]:479 0.00341 +58 prog_clk[0]:588 prog_clk[0]:587 0.00341 +59 prog_clk[0]:588 prog_clk[0]:567 0.002428571 +60 prog_clk[0]:587 prog_clk[0]:586 0.000431225 +61 prog_clk[0]:258 prog_clk[0]:257 0.0045 +62 prog_clk[0]:258 prog_clk[0]:255 0.002377232 +63 prog_clk[0]:259 prog_clk[0]:258 0.00341 +64 prog_clk[0]:269 prog_clk[0]:268 0.00341 +65 prog_clk[0]:269 prog_clk[0]:219 0.0045 +66 prog_clk[0]:268 prog_clk[0]:267 0.0005032916 +67 prog_clk[0]:181 prog_clk[0]:180 0.0045 +68 prog_clk[0]:181 prog_clk[0]:178 0.001162947 +69 prog_clk[0]:182 prog_clk[0]:181 0.00341 +70 prog_clk[0]:125 prog_clk[0]:124 0.003591518 +71 prog_clk[0]:126 prog_clk[0]:125 0.00341 +72 prog_clk[0]:126 prog_clk[0]:111 0.0007194916 +73 prog_clk[0]:405 prog_clk[0]:404 0.00341 +74 prog_clk[0]:405 prog_clk[0]:374 0.004209822 +75 prog_clk[0]:404 prog_clk[0]:403 0.001440158 +76 prog_clk[0]:128 prog_clk[0]:127 0.00341 +77 prog_clk[0]:128 prog_clk[0]:106 0.0008214285 +78 prog_clk[0]:127 prog_clk[0]:126 0.003025625 +79 prog_clk[0]:593 prog_clk[0]:592 0.006930804 +80 prog_clk[0]:594 prog_clk[0]:593 0.00341 +81 prog_clk[0]:594 prog_clk[0]:360 0.001225133 +82 prog_clk[0]:252 prog_clk[0]:251 0.009622768 +83 prog_clk[0]:253 prog_clk[0]:252 0.00341 +84 prog_clk[0]:253 prog_clk[0]:248 0.0008648 +85 prog_clk[0]:250 prog_clk[0]:249 0.0001059783 +86 prog_clk[0]:251 prog_clk[0]:250 0.0045 +87 prog_clk[0]:249 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +88 prog_clk[0]:553 prog_clk[0]:552 0.00341 +89 prog_clk[0]:553 prog_clk[0]:524 0.006071429 +90 prog_clk[0]:552 prog_clk[0]:551 0.0005753583 +91 prog_clk[0]:545 prog_clk[0]:544 0.003642857 +92 prog_clk[0]:545 prog_clk[0]:527 0.001174107 +93 prog_clk[0]:546 prog_clk[0]:545 0.00341 +94 prog_clk[0]:308 prog_clk[0]:307 0.00341 +95 prog_clk[0]:308 prog_clk[0]:204 0.0009107144 +96 prog_clk[0]:307 prog_clk[0]:306 0.001079825 +97 prog_clk[0]:451 prog_clk[0]:450 0.001174107 +98 prog_clk[0]:451 prog_clk[0]:447 0.001162946 +99 prog_clk[0]:452 prog_clk[0]:451 0.00341 +100 prog_clk[0]:222 prog_clk[0]:221 0.0045 +101 prog_clk[0]:223 prog_clk[0]:222 0.00341 +102 prog_clk[0]:221 prog_clk[0]:220 0.0005736608 +103 prog_clk[0]:220 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +104 prog_clk[0]:312 prog_clk[0]:311 0.002073661 +105 prog_clk[0]:313 prog_clk[0]:312 0.00341 +106 prog_clk[0]:313 prog_clk[0]:197 0.001441333 +107 prog_clk[0]:567 prog_clk[0]:566 0.00341 +108 prog_clk[0]:567 prog_clk[0]:363 0.0004107143 +109 prog_clk[0]:566 prog_clk[0]:565 0.0003579833 +110 prog_clk[0]:564 prog_clk[0]:563 0.005109375 +111 prog_clk[0]:565 prog_clk[0]:564 0.00341 +112 prog_clk[0]:422 prog_clk[0]:421 0.009015625 +113 prog_clk[0]:423 prog_clk[0]:422 0.00341 +114 prog_clk[0]:423 prog_clk[0]:418 0.0005765333 +115 prog_clk[0]:420 prog_clk[0]:419 0.0001059783 +116 prog_clk[0]:421 prog_clk[0]:420 0.0045 +117 prog_clk[0]:419 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +118 prog_clk[0]:277 prog_clk[0]:276 0.00596875 +119 prog_clk[0]:278 prog_clk[0]:277 0.00341 +120 prog_clk[0]:278 prog_clk[0]:217 0.0009368666 +121 prog_clk[0]:255 prog_clk[0]:254 0.00341 +122 prog_clk[0]:254 prog_clk[0]:253 0.000431225 +123 prog_clk[0]:145 prog_clk[0]:144 0.004502232 +124 prog_clk[0]:146 prog_clk[0]:145 0.00341 +125 prog_clk[0]:146 prog_clk[0]:102 0.0001053583 +126 prog_clk[0]:159 prog_clk[0]:158 0.006323661 +127 prog_clk[0]:160 prog_clk[0]:159 0.00341 +128 prog_clk[0]:160 prog_clk[0]:151 0.0008648 +129 prog_clk[0]:509 prog_clk[0]:508 0.0045 +130 prog_clk[0]:509 prog_clk[0]:506 0.0008214285 +131 prog_clk[0]:510 prog_clk[0]:509 0.00341 +132 prog_clk[0]:512 prog_clk[0]:511 0.00341 +133 prog_clk[0]:512 prog_clk[0]:502 0.002388393 +134 prog_clk[0]:511 prog_clk[0]:510 0.001150717 +135 prog_clk[0]:478 prog_clk[0]:477 0.00341 +136 prog_clk[0]:478 prog_clk[0]:464 0.00602009 +137 prog_clk[0]:477 prog_clk[0]:476 0.0002870916 +138 prog_clk[0]:305 prog_clk[0]:304 0.003591518 +139 prog_clk[0]:306 prog_clk[0]:305 0.00341 +140 prog_clk[0]:306 prog_clk[0]:283 0.0001053583 +141 prog_clk[0]:432 prog_clk[0]:431 0.001729911 +142 prog_clk[0]:433 prog_clk[0]:432 0.00341 +143 prog_clk[0]:433 prog_clk[0]:428 0.0004324 +144 prog_clk[0]:430 prog_clk[0]:429 0.0001440217 +145 prog_clk[0]:431 prog_clk[0]:430 0.0045 +146 prog_clk[0]:429 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +147 prog_clk[0]:461 prog_clk[0]:460 0.003551339 +148 prog_clk[0]:462 prog_clk[0]:461 0.00341 +149 prog_clk[0]:462 prog_clk[0]:457 0.0007206666 +150 prog_clk[0]:459 prog_clk[0]:458 0.0001440218 +151 prog_clk[0]:460 prog_clk[0]:459 0.0045 +152 prog_clk[0]:458 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +153 prog_clk[0]:559 prog_clk[0]:558 0.00341 +154 prog_clk[0]:559 prog_clk[0]:553 0.003642857 +155 prog_clk[0]:558 prog_clk[0]:557 0.0005021166 +156 prog_clk[0]:556 prog_clk[0]:555 0.0045 +157 prog_clk[0]:557 prog_clk[0]:556 0.00341 +158 prog_clk[0]:555 prog_clk[0]:554 0.001395089 +159 prog_clk[0]:554 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +160 prog_clk[0]:178 prog_clk[0]:177 0.00341 +161 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prog_clk[0]:476 prog_clk[0]:475 0.00341 +440 prog_clk[0]:476 prog_clk[0]:472 0.001441333 +441 prog_clk[0]:474 prog_clk[0]:473 0.0001440218 +442 prog_clk[0]:473 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +443 prog_clk[0]:411 prog_clk[0]:410 0.001122768 +444 prog_clk[0]:412 prog_clk[0]:411 0.00341 +445 prog_clk[0]:412 prog_clk[0]:407 0.0006486 +446 prog_clk[0]:409 prog_clk[0]:408 0.0001440218 +447 prog_clk[0]:410 prog_clk[0]:409 0.0045 +448 prog_clk[0]:408 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +449 prog_clk[0]:365 prog_clk[0]:364 0.0001440218 +450 prog_clk[0]:366 prog_clk[0]:365 0.0045 +451 prog_clk[0]:364 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +452 prog_clk[0]:497 prog_clk[0]:496 0.00341 +453 prog_clk[0]:497 prog_clk[0]:491 0.00602009 +454 prog_clk[0]:496 prog_clk[0]:495 0.00021385 +455 prog_clk[0]:494 prog_clk[0]:493 0.0045 +456 prog_clk[0]:495 prog_clk[0]:494 0.00341 +457 prog_clk[0]:493 prog_clk[0]:492 0.0001059783 +458 prog_clk[0]:492 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +459 prog_clk[0]:406 prog_clk[0]:405 0.004198661 +460 prog_clk[0]:407 prog_clk[0]:406 0.00341 +461 prog_clk[0]:407 prog_clk[0]:371 0.0007194916 +462 prog_clk[0]:266 prog_clk[0]:265 0.005109376 +463 prog_clk[0]:267 prog_clk[0]:266 0.00341 +464 prog_clk[0]:267 prog_clk[0]:259 0.0007915584 +465 prog_clk[0]:538 prog_clk[0]:537 0.0001847826 +466 prog_clk[0]:539 prog_clk[0]:538 0.0045 +467 prog_clk[0]:539 prog_clk[0]:536 0.004553571 +468 prog_clk[0]:537 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +469 prog_clk[0]:581 prog_clk[0]:580 0.002680804 +470 prog_clk[0]:582 prog_clk[0]:581 0.00341 +471 prog_clk[0]:257 prog_clk[0]:256 0.0001440217 +472 prog_clk[0]:256 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +473 prog_clk[0]:206 prog_clk[0]:205 0.0001059783 +474 prog_clk[0]:207 prog_clk[0]:206 0.0045 +475 prog_clk[0]:205 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +476 prog_clk[0]:304 prog_clk[0]:303 0.00341 +477 prog_clk[0]:304 prog_clk[0]:298 0.004857143 +478 prog_clk[0]:303 prog_clk[0]:302 0.00021385 +479 prog_clk[0]:301 prog_clk[0]:300 0.0045 +480 prog_clk[0]:302 prog_clk[0]:301 0.00341 +481 prog_clk[0]:300 prog_clk[0]:299 0.0009843751 +482 prog_clk[0]:299 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +483 prog_clk[0]:216 prog_clk[0]:215 0.001122768 +484 prog_clk[0]:217 prog_clk[0]:216 0.00341 +485 prog_clk[0]:217 prog_clk[0]:212 0.001584292 +486 prog_clk[0]:214 prog_clk[0]:213 0.0001086957 +487 prog_clk[0]:215 prog_clk[0]:214 0.0045 +488 prog_clk[0]:213 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +489 prog_clk[0]:264 prog_clk[0]:263 0.0001847826 +490 prog_clk[0]:265 prog_clk[0]:264 0.0045 +491 prog_clk[0]:265 prog_clk[0]:262 0.002084821 +492 prog_clk[0]:263 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +493 prog_clk[0]:104 prog_clk[0]:103 8.695653e-05 +494 prog_clk[0]:105 prog_clk[0]:104 0.0045 +495 prog_clk[0]:103 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +496 prog_clk[0]:390 prog_clk[0]:389 0.0045 +497 prog_clk[0]:391 prog_clk[0]:390 0.00341 +498 prog_clk[0]:391 prog_clk[0]:387 0.0002870917 +499 prog_clk[0]:389 prog_clk[0]:388 0.0001440218 +500 prog_clk[0]:388 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +501 prog_clk[0]:141 prog_clk[0]:140 0.00341 +502 prog_clk[0]:141 prog_clk[0]:135 0.0004107143 +503 prog_clk[0]:140 prog_clk[0]:139 0.0007903833 +504 prog_clk[0]:138 prog_clk[0]:137 0.0045 +505 prog_clk[0]:139 prog_clk[0]:138 0.00341 +506 prog_clk[0]:137 prog_clk[0]:136 0.0001440218 +507 prog_clk[0]:136 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +508 prog_clk[0]:386 prog_clk[0]:385 0.002337054 +509 prog_clk[0]:387 prog_clk[0]:386 0.00341 +510 prog_clk[0]:384 prog_clk[0]:383 0.0001059783 +511 prog_clk[0]:385 prog_clk[0]:384 0.0045 +512 prog_clk[0]:383 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +513 prog_clk[0]:449 prog_clk[0]:448 0.0001440218 +514 prog_clk[0]:450 prog_clk[0]:449 0.0045 +515 prog_clk[0]:448 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +516 prog_clk[0]:291 prog_clk[0]:290 0.0001847826 +517 prog_clk[0]:292 prog_clk[0]:291 0.0045 +518 prog_clk[0]:292 prog_clk[0]:289 0.002680804 +519 prog_clk[0]:290 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +520 prog_clk[0]:298 prog_clk[0]:297 0.00341 +521 prog_clk[0]:298 prog_clk[0]:292 0.01183929 +522 prog_clk[0]:297 prog_clk[0]:296 0.0005021166 +523 prog_clk[0]:295 prog_clk[0]:294 0.0045 +524 prog_clk[0]:296 prog_clk[0]:295 0.00341 +525 prog_clk[0]:294 prog_clk[0]:293 0.0001440218 +526 prog_clk[0]:293 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +527 prog_clk[0]:199 prog_clk[0]:198 0.0001440218 +528 prog_clk[0]:200 prog_clk[0]:199 0.0045 +529 prog_clk[0]:198 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +530 prog_clk[0]:332 prog_clk[0]:331 0.00341 +531 prog_clk[0]:331 prog_clk[0]:330 0.0005741833 +532 prog_clk[0]:329 prog_clk[0]:328 0.0045 +533 prog_clk[0]:330 prog_clk[0]:329 0.00341 +534 prog_clk[0]:328 prog_clk[0]:327 0.000984375 +535 prog_clk[0]:327 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +536 prog_clk[0]:316 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +537 prog_clk[0]:317 prog_clk[0]:316 0.0045 +538 prog_clk[0]:180 prog_clk[0]:179 0.0001440218 +539 prog_clk[0]:179 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +540 prog_clk[0]:175 prog_clk[0]:174 0.001122768 +541 prog_clk[0]:176 prog_clk[0]:175 0.00341 +542 prog_clk[0]:176 prog_clk[0]:171 0.001369267 +543 prog_clk[0]:173 prog_clk[0]:172 0.0001059783 +544 prog_clk[0]:174 prog_clk[0]:173 0.0045 +545 prog_clk[0]:172 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +546 prog_clk[0]:351 prog_clk[0]:350 0.0001847826 +547 prog_clk[0]:352 prog_clk[0]:351 0.0045 +548 prog_clk[0]:350 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +549 prog_clk[0]:344 prog_clk[0]:343 0.0001847826 +550 prog_clk[0]:345 prog_clk[0]:344 0.0045 +551 prog_clk[0]:345 prog_clk[0]:342 0.003287947 +552 prog_clk[0]:343 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +553 prog_clk[0]:322 prog_clk[0]:321 0.0001440218 +554 prog_clk[0]:323 prog_clk[0]:322 0.0045 +555 prog_clk[0]:321 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +556 prog_clk[0]:561 prog_clk[0]:560 0.001024554 +557 prog_clk[0]:590 prog_clk[0]:589 0.0003035715 +558 prog_clk[0]:202 prog_clk[0]:201 0.0003035715 +559 prog_clk[0]:156 prog_clk[0]:155 0.001024554 +560 prog_clk[0]:228 prog_clk[0]:227 0.0006138393 +561 prog_clk[0]:487 prog_clk[0]:486 0.001174107 +562 prog_clk[0]:439 prog_clk[0]:438 0.00603125 +563 prog_clk[0]:439 prog_clk[0]:435 0.0005558036 +564 prog_clk[0]:577 prog_clk[0]:576 0.0008214285 +565 prog_clk[0]:506 prog_clk[0]:505 0.002388393 +566 prog_clk[0]:354 prog_clk[0]:353 0.0003705357 +567 prog_clk[0]:353 prog_clk[0]:352 0.00019375 +568 prog_clk[0]:353 prog_clk[0]:349 0.002984375 +569 prog_clk[0]:336 prog_clk[0]:335 0.0008214285 +570 prog_clk[0]:336 prog_clk[0]:332 0.004805804 +571 prog_clk[0]:337 prog_clk[0]:336 0.002428571 +572 prog_clk[0]:337 prog_clk[0]:326 0.0004107143 +573 prog_clk[0]:338 prog_clk[0]:337 0.009714286 +574 prog_clk[0]:338 prog_clk[0]:323 0.0004107143 +575 prog_clk[0]:318 prog_clk[0]:317 0.001232143 +576 prog_clk[0]:318 prog_clk[0]:315 0.002377232 +577 prog_clk[0]:401 prog_clk[0]:400 0.001232143 +578 prog_clk[0]:401 prog_clk[0]:398 0.002428571 +579 prog_clk[0]:398 prog_clk[0]:397 0.0008214287 +580 prog_clk[0]:270 prog_clk[0]:269 0.002428572 +581 prog_clk[0]:106 prog_clk[0]:105 0.001174107 +582 prog_clk[0]:135 prog_clk[0]:134 0.002428572 +583 prog_clk[0]:236 prog_clk[0]:235 0.0008214285 +584 prog_clk[0]:236 prog_clk[0]:233 0.005464286 +585 prog_clk[0]:233 prog_clk[0]:232 0.0004107143 +586 prog_clk[0]:232 prog_clk[0]:231 0.001517857 +587 prog_clk[0]:231 prog_clk[0]:230 0.0004107143 +588 prog_clk[0]:115 prog_clk[0]:114 0.004816964 +589 prog_clk[0]:183 prog_clk[0]:182 0.000863625 +590 prog_clk[0]:413 prog_clk[0]:412 0.0004324 +591 prog_clk[0]:188 prog_clk[0]:187 0.0001429583 +592 prog_clk[0]:379 prog_clk[0]:378 0.0007194916 +593 prog_clk[0]:283 prog_clk[0]:282 0.001368092 +594 prog_clk[0]:161 prog_clk[0]:160 0.0012972 +595 prog_clk[0]:102 prog_clk[0]:101 0.0007915583 + +*END + +*D_NET mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0] 0.009222956 //LENGTH 72.505 LUMPCC 0.002297004 DR + +*CONN +*I mux_top_track_22\/mux_l2_in_0_:X O *L 0 *C 90.445 29.240 +*I mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 93.095 96.705 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 93.058 96.610 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 91.585 96.560 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 91.540 96.515 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 91.540 90.498 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 91.538 90.440 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 91.095 90.440 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 91.080 90.433 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 91.080 82.475 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 91.080 32.648 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 91.060 32.640 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 90.168 32.640 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 90.160 32.583 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 90.160 29.285 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:15 *C 90.160 29.240 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:16 *C 90.445 29.240 + +*CAP +0 mux_top_track_22\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001042437 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001042437 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000293194 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000293194 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.740606e-05 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.740606e-05 +8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002917633 +9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.002629493 +10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.00233773 +11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001260984 +12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0001260984 +13 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0002100823 +14 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.0002100823 +15 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:15 5.639357e-05 +16 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:16 4.652533e-05 +17 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0009133212 +18 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 1.47117e-05 +19 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001630581 +20 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.855718e-06 +21 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.855718e-06 +22 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 1.47117e-05 +23 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.001076379 +24 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.155498e-05 +25 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.155498e-05 + +*RES +0 mux_top_track_22\/mux_l2_in_0_:X mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:16 0.152 +1 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:16 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.0001548913 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:15 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.0045 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.002944197 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.00341 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.000139825 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.00341 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.007806308 +8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.499219e-05 +9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.005372768 +11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001314732 +13 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +14 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001246675 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001174578 //LENGTH 8.615 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l4_in_0_:X O *L 0 *C 128.625 69.020 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 136.335 69.525 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 136.335 69.525 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 136.335 69.020 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 128.662 69.020 + +*CAP +0 mux_right_track_0\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.58147e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.000571811 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0005349523 + +*RES +0 mux_right_track_0\/mux_l4_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.006850447 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0004508929 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001059583 //LENGTH 7.080 LUMPCC 0.0001724741 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_3_:X O *L 0 *C 94.935 75.140 +*I mux_right_track_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 95.395 80.580 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 95.395 80.580 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 95.680 80.580 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 95.680 80.535 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 95.680 77.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 95.220 77.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 95.220 75.185 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 95.220 75.140 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 94.935 75.140 + +*CAP +0 mux_right_track_2\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.400379e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.744108e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001279882 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001574366 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001853021 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001558537 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 6.436934e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 6.271419e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 prog_clk[0]:135 6.666892e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 prog_clk[0]:144 1.211062e-06 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:128 1.699038e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:134 1.36668e-06 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:134 1.699038e-05 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:135 1.36668e-06 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 prog_clk[0]:134 6.666892e-05 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 prog_clk[0]:141 1.211062e-06 + +*RES +0 mux_right_track_2\/mux_l2_in_3_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_2\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001548913 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.002388393 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001548913 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004107143 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002388393 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008832677 //LENGTH 7.610 LUMPCC 0.0001039379 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_6_:X O *L 0 *C 110.115 50.320 +*I mux_right_track_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 111.320 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 111.320 56.100 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 111.320 56.055 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 111.320 50.365 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 111.275 50.320 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 110.153 50.320 + +*CAP +0 mux_right_track_4\/mux_l1_in_6_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_3_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.491948e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002746929 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002746929 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.651224e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.651224e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_124:35 5.035045e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_124:40 1.618485e-06 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_124:34 5.035045e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_124:39 1.618485e-06 + +*RES +0 mux_right_track_4\/mux_l1_in_6_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_4\/mux_l2_in_3_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.005080357 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001002232 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0] 0.0007107735 //LENGTH 4.750 LUMPCC 8.904804e-05 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_1_:X O *L 0 *C 15.925 44.200 +*I mux_left_track_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.640 42.840 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 18.640 42.840 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 18.400 42.840 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 18.400 42.885 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 18.400 44.155 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 18.355 44.200 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 15.963 44.200 + +*CAP +0 mux_left_track_5\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 4.989883e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 5.441995e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 6.378322e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 6.378322e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0001939201 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.0001939201 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 1.230096e-07 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 1.230096e-07 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 4.440101e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 4.440101e-05 + +*RES +0 mux_left_track_5\/mux_l3_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.002136161 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.001133928 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0001304348 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_left_track_5\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0009339778 //LENGTH 7.055 LUMPCC 0.000126484 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_2_:X O *L 0 *C 12.595 49.980 +*I mux_left_track_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 13.800 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 13.763 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 12.465 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 12.420 45.265 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 12.420 49.935 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 12.420 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 12.595 49.980 + +*CAP +0 mux_left_track_5\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.40951e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 6.40951e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002773923 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002773923 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.33067e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.921224e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:8 1.083288e-06 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:9 3.559676e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:10 2.656195e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:7 1.083288e-06 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:10 3.559676e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:11 2.656195e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.51087e-05 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.004169643 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.001158482 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_5\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0] 0.005879637 //LENGTH 34.710 LUMPCC 0.003061643 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_0_:X O *L 0 *C 35.135 60.520 +*I mux_left_track_33\/mux_l3_in_0_:A1 I *L 0.00198 *C 9.565 52.700 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 9.565 52.700 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 9.660 52.745 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 9.660 54.343 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 9.668 54.400 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 34.492 54.400 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 34.500 54.458 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 34.500 57.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 34.960 57.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 34.960 60.475 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 34.960 60.520 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 35.135 60.520 + +*CAP +0 mux_left_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.846467e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001304566 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001304566 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0007897768 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0007897768 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000170948 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002038032 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002502157 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0002173605 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 5.351998e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:12 5.121547e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[1]:13 0.0008402602 +14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[1]:12 0.0008402602 +15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[3] 0.0004704679 +16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[3]:10 0.0004704679 +17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 left_top_grid_pin_42_[0]:14 0.0002200937 +18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 left_top_grid_pin_42_[0]:15 0.0002200937 + +*RES +0 mux_left_track_33\/mux_l2_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001426339 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00388925 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0045 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.002995536 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 9.51087e-05 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002377232 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004107143 + +*END + +*D_NET ropt_net_175 0.0004656533 //LENGTH 3.585 LUMPCC 0.00010038 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 4.140 29.240 +*I ropt_mt_inst_805:A I *L 0.001766 *C 3.220 31.280 +*N ropt_net_175:2 *C 3.258 31.280 +*N ropt_net_175:3 *C 4.095 31.280 +*N ropt_net_175:4 *C 4.140 31.235 +*N ropt_net_175:5 *C 4.140 29.285 +*N ropt_net_175:6 *C 4.140 29.240 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 ropt_mt_inst_805:A 1e-06 +2 ropt_net_175:2 3.527725e-05 +3 ropt_net_175:3 3.527725e-05 +4 ropt_net_175:4 0.0001309079 +5 ropt_net_175:5 0.0001309079 +6 ropt_net_175:6 3.090291e-05 +7 ropt_net_175:2 left_bottom_grid_pin_1_[0]:20 4.569829e-05 +8 ropt_net_175:3 left_bottom_grid_pin_1_[0]:19 4.569829e-05 +9 ropt_net_175:4 left_bottom_grid_pin_1_[0]:21 4.491728e-06 +10 ropt_net_175:5 left_bottom_grid_pin_1_[0]:22 4.491728e-06 + +*RES +0 ropt_mt_inst_751:X ropt_net_175:6 0.152 +1 ropt_net_175:2 ropt_mt_inst_805:A 0.152 +2 ropt_net_175:3 ropt_net_175:2 0.0007477679 +3 ropt_net_175:4 ropt_net_175:3 0.0045 +4 ropt_net_175:6 ropt_net_175:5 0.0045 +5 ropt_net_175:5 ropt_net_175:4 0.001741072 + +*END + +*D_NET ropt_net_152 0.0004606443 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I FTB_18__17:X O *L 0 *C 135.700 48.280 +*I ropt_mt_inst_775:A I *L 0.001766 *C 134.780 50.320 +*N ropt_net_152:2 *C 134.780 50.320 +*N ropt_net_152:3 *C 134.780 50.275 +*N ropt_net_152:4 *C 134.780 48.325 +*N ropt_net_152:5 *C 134.825 48.280 +*N ropt_net_152:6 *C 135.662 48.280 + +*CAP +0 FTB_18__17:X 1e-06 +1 ropt_mt_inst_775:A 1e-06 +2 ropt_net_152:2 3.601591e-05 +3 ropt_net_152:3 0.0001363429 +4 ropt_net_152:4 0.0001363429 +5 ropt_net_152:5 7.497124e-05 +6 ropt_net_152:6 7.497124e-05 + +*RES +0 FTB_18__17:X ropt_net_152:6 0.152 +1 ropt_net_152:2 ropt_mt_inst_775:A 0.152 +2 ropt_net_152:3 ropt_net_152:2 0.0045 +3 ropt_net_152:5 ropt_net_152:4 0.0045 +4 ropt_net_152:4 ropt_net_152:3 0.001741071 +5 ropt_net_152:6 ropt_net_152:5 0.0007477679 + +*END + +*D_NET ropt_net_174 0.0004644239 //LENGTH 3.585 LUMPCC 0.0001009343 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 4.140 23.800 +*I ropt_mt_inst_804:A I *L 0.001766 *C 3.220 25.840 +*N ropt_net_174:2 *C 3.220 25.840 +*N ropt_net_174:3 *C 3.220 25.795 +*N ropt_net_174:4 *C 3.220 23.845 +*N ropt_net_174:5 *C 3.265 23.800 +*N ropt_net_174:6 *C 4.103 23.800 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 ropt_mt_inst_804:A 1e-06 +2 ropt_net_174:2 3.445172e-05 +3 ropt_net_174:3 9.511076e-05 +4 ropt_net_174:4 9.511076e-05 +5 ropt_net_174:5 6.840817e-05 +6 ropt_net_174:6 6.840817e-05 +7 ropt_net_174:6 chanx_right_in[9]:5 1.035878e-05 +8 ropt_net_174:5 chanx_right_in[9]:4 1.035878e-05 +9 ropt_net_174:4 chanx_right_in[9]:6 4.010835e-05 +10 ropt_net_174:3 chanx_right_in[9]:7 4.010835e-05 + +*RES +0 ropt_mt_inst_761:X ropt_net_174:6 0.152 +1 ropt_net_174:6 ropt_net_174:5 0.000747768 +2 ropt_net_174:5 ropt_net_174:4 0.0045 +3 ropt_net_174:4 ropt_net_174:3 0.001741072 +4 ropt_net_174:2 ropt_mt_inst_804:A 0.152 +5 ropt_net_174:3 ropt_net_174:2 0.0045 + +*END + +*D_NET chanx_left_out[15] 0.0008364505 //LENGTH 7.235 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 4.140 42.840 +*P chanx_left_out[15] O *L 0.7423 *C 1.298 39.440 +*N chanx_left_out[15]:2 *C 1.380 39.440 +*N chanx_left_out[15]:3 *C 1.380 39.440 +*N chanx_left_out[15]:4 *C 2.300 39.440 +*N chanx_left_out[15]:5 *C 2.300 42.795 +*N chanx_left_out[15]:6 *C 2.345 42.840 +*N chanx_left_out[15]:7 *C 4.103 42.840 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 chanx_left_out[15] 3.237836e-05 +2 chanx_left_out[15]:2 3.237836e-05 +3 chanx_left_out[15]:3 8.620517e-05 +4 chanx_left_out[15]:4 0.000236773 +5 chanx_left_out[15]:5 0.0001833196 +6 chanx_left_out[15]:6 0.000132198 +7 chanx_left_out[15]:7 0.000132198 + +*RES +0 ropt_mt_inst_786:X chanx_left_out[15]:7 0.152 +1 chanx_left_out[15]:7 chanx_left_out[15]:6 0.001569197 +2 chanx_left_out[15]:6 chanx_left_out[15]:5 0.0045 +3 chanx_left_out[15]:5 chanx_left_out[15]:4 0.002995536 +4 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +5 chanx_left_out[15]:2 chanx_left_out[15] 2.35e-05 +6 chanx_left_out[15]:4 chanx_left_out[15]:3 0.0008214285 + +*END + +*D_NET ropt_net_170 0.001162594 //LENGTH 10.685 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 138.655 36.040 +*I ropt_mt_inst_797:A I *L 0.001767 *C 134.780 39.440 +*N ropt_net_170:2 *C 134.780 39.440 +*N ropt_net_170:3 *C 134.780 39.100 +*N ropt_net_170:4 *C 139.795 39.100 +*N ropt_net_170:5 *C 139.840 39.055 +*N ropt_net_170:6 *C 139.840 36.085 +*N ropt_net_170:7 *C 139.795 36.040 +*N ropt_net_170:8 *C 138.692 36.040 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_170:2 5.928789e-05 +3 ropt_net_170:3 0.0003389184 +4 ropt_net_170:4 0.0003099615 +5 ropt_net_170:5 0.0001397739 +6 ropt_net_170:6 0.0001397739 +7 ropt_net_170:7 8.643935e-05 +8 ropt_net_170:8 8.643935e-05 + +*RES +0 ropt_mt_inst_771:X ropt_net_170:8 0.152 +1 ropt_net_170:2 ropt_mt_inst_797:A 0.152 +2 ropt_net_170:4 ropt_net_170:3 0.004477679 +3 ropt_net_170:5 ropt_net_170:4 0.0045 +4 ropt_net_170:7 ropt_net_170:6 0.0045 +5 ropt_net_170:6 ropt_net_170:5 0.002651786 +6 ropt_net_170:8 ropt_net_170:7 0.000984375 +7 ropt_net_170:3 ropt_net_170:2 0.0003035715 + +*END + +*D_NET chanx_right_out[15] 0.0006912273 //LENGTH 4.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 136.160 39.440 +*P chanx_right_out[15] O *L 0.7423 *C 140.450 39.440 +*N chanx_right_out[15]:2 *C 136.627 39.440 +*N chanx_right_out[15]:3 *C 136.620 39.440 +*N chanx_right_out[15]:4 *C 136.575 39.440 +*N chanx_right_out[15]:5 *C 136.198 39.440 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chanx_right_out[15] 0.0002732052 +2 chanx_right_out[15]:2 0.0002732052 +3 chanx_right_out[15]:3 3.464594e-05 +4 chanx_right_out[15]:4 5.45855e-05 +5 chanx_right_out[15]:5 5.45855e-05 + +*RES +0 ropt_mt_inst_797:X chanx_right_out[15]:5 0.152 +1 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0003370536 +2 chanx_right_out[15]:4 chanx_right_out[15]:3 0.0045 +3 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +4 chanx_right_out[15]:2 chanx_right_out[15] 0.0005988583 + +*END + +*D_NET ropt_net_147 0.001505226 //LENGTH 12.710 LUMPCC 0.0002674787 DR + +*CONN +*I BUFT_P_96:X O *L 0 *C 133.860 37.060 +*I ropt_mt_inst_770:A I *L 0.001766 *C 134.780 44.880 +*N ropt_net_147:2 *C 134.817 44.880 +*N ropt_net_147:3 *C 135.195 44.880 +*N ropt_net_147:4 *C 135.240 44.835 +*N ropt_net_147:5 *C 135.240 41.480 +*N ropt_net_147:6 *C 136.160 41.480 +*N ropt_net_147:7 *C 136.160 37.105 +*N ropt_net_147:8 *C 136.115 37.060 +*N ropt_net_147:9 *C 133.898 37.060 + +*CAP +0 BUFT_P_96:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_147:2 4.043525e-05 +3 ropt_net_147:3 4.043525e-05 +4 ropt_net_147:4 0.0001715212 +5 ropt_net_147:5 0.000230646 +6 ropt_net_147:6 0.000288933 +7 ropt_net_147:7 0.0002298082 +8 ropt_net_147:8 0.0001169844 +9 ropt_net_147:9 0.0001169844 +10 ropt_net_147:4 chanx_right_out[16]:4 6.293577e-05 +11 ropt_net_147:7 chanx_right_out[16]:3 2.515209e-05 +12 ropt_net_147:5 chanx_right_out[16]:3 6.293577e-05 +13 ropt_net_147:6 chanx_right_out[16]:4 2.515209e-05 +14 ropt_net_147:8 ropt_net_148:2 4.494977e-05 +15 ropt_net_147:7 ropt_net_148:4 7.017242e-07 +16 ropt_net_147:9 ropt_net_148:3 4.494977e-05 +17 ropt_net_147:6 ropt_net_148:5 7.017242e-07 + +*RES +0 BUFT_P_96:X ropt_net_147:9 0.152 +1 ropt_net_147:2 ropt_mt_inst_770:A 0.152 +2 ropt_net_147:3 ropt_net_147:2 0.0003370536 +3 ropt_net_147:4 ropt_net_147:3 0.0045 +4 ropt_net_147:8 ropt_net_147:7 0.0045 +5 ropt_net_147:7 ropt_net_147:6 0.00390625 +6 ropt_net_147:9 ropt_net_147:8 0.001979911 +7 ropt_net_147:5 ropt_net_147:4 0.002995536 +8 ropt_net_147:6 ropt_net_147:5 0.0008214285 + +*END + +*D_NET chanx_right_in[13] 0.02897863 //LENGTH 202.615 LUMPCC 0.00775917 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 140.450 44.880 +*I mux_top_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 59.515 55.080 +*I BUFT_P_107:A I *L 0.001776 *C 10.120 25.840 +*I mux_left_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 24.745 66.980 +*N chanx_right_in[13]:4 *C 24.745 66.980 +*N chanx_right_in[13]:5 *C 24.840 66.640 +*N chanx_right_in[13]:6 *C 24.840 66.640 +*N chanx_right_in[13]:7 *C 10.083 25.840 +*N chanx_right_in[13]:8 *C 8.785 25.840 +*N chanx_right_in[13]:9 *C 8.740 25.885 +*N chanx_right_in[13]:10 *C 8.740 34.635 +*N chanx_right_in[13]:11 *C 8.785 34.680 +*N chanx_right_in[13]:12 *C 13.025 34.680 +*N chanx_right_in[13]:13 *C 12.945 34.635 +*N chanx_right_in[13]:14 *C 12.880 34.045 +*N chanx_right_in[13]:15 *C 12.925 34.000 +*N chanx_right_in[13]:16 *C 15.180 34.000 +*N chanx_right_in[13]:17 *C 15.180 34.000 +*N chanx_right_in[13]:18 *C 15.188 34.000 +*N chanx_right_in[13]:19 *C 24.820 34.000 +*N chanx_right_in[13]:20 *C 24.840 34.008 +*N chanx_right_in[13]:21 *C 24.840 66.633 +*N chanx_right_in[13]:22 *C 24.848 66.640 +*N chanx_right_in[13]:23 *C 46.900 66.640 +*N chanx_right_in[13]:24 *C 46.920 66.633 +*N chanx_right_in[13]:25 *C 46.920 56.448 +*N chanx_right_in[13]:26 *C 46.940 56.440 +*N chanx_right_in[13]:27 *C 59.333 56.440 +*N chanx_right_in[13]:28 *C 59.340 56.383 +*N chanx_right_in[13]:29 *C 59.515 55.080 +*N chanx_right_in[13]:30 *C 59.340 55.080 +*N chanx_right_in[13]:31 *C 59.340 55.080 +*N chanx_right_in[13]:32 *C 59.340 51.058 +*N chanx_right_in[13]:33 *C 59.348 51.000 +*N chanx_right_in[13]:34 *C 92.900 51.000 +*N chanx_right_in[13]:35 *C 92.920 50.992 +*N chanx_right_in[13]:36 *C 92.920 44.888 +*N chanx_right_in[13]:37 *C 92.940 44.880 + +*CAP +0 chanx_right_in[13] 0.001692516 +1 mux_top_track_16\/mux_l1_in_0_:A0 1e-06 +2 BUFT_P_107:A 1e-06 +3 mux_left_track_3\/mux_l2_in_1_:A1 1e-06 +4 chanx_right_in[13]:4 6.210897e-05 +5 chanx_right_in[13]:5 6.632629e-05 +6 chanx_right_in[13]:6 3.636913e-05 +7 chanx_right_in[13]:7 9.517873e-05 +8 chanx_right_in[13]:8 9.517873e-05 +9 chanx_right_in[13]:9 0.0004898399 +10 chanx_right_in[13]:10 0.0004898399 +11 chanx_right_in[13]:11 0.0002988357 +12 chanx_right_in[13]:12 0.0002988357 +13 chanx_right_in[13]:13 4.343369e-05 +14 chanx_right_in[13]:14 4.343369e-05 +15 chanx_right_in[13]:15 0.0001520772 +16 chanx_right_in[13]:16 0.0001842218 +17 chanx_right_in[13]:17 3.442452e-05 +18 chanx_right_in[13]:18 0.0003798433 +19 chanx_right_in[13]:19 0.0003798433 +20 chanx_right_in[13]:20 0.001992721 +21 chanx_right_in[13]:21 0.001992721 +22 chanx_right_in[13]:22 0.00138764 +23 chanx_right_in[13]:23 0.00138764 +24 chanx_right_in[13]:24 0.0006457015 +25 chanx_right_in[13]:25 0.0006457015 +26 chanx_right_in[13]:26 0.0008722895 +27 chanx_right_in[13]:27 0.0008722895 +28 chanx_right_in[13]:28 7.922809e-05 +29 chanx_right_in[13]:29 5.766749e-05 +30 chanx_right_in[13]:30 6.229062e-05 +31 chanx_right_in[13]:31 0.0003530395 +32 chanx_right_in[13]:32 0.000238039 +33 chanx_right_in[13]:33 0.001647353 +34 chanx_right_in[13]:34 0.001647353 +35 chanx_right_in[13]:35 0.000399983 +36 chanx_right_in[13]:36 0.000399983 +37 chanx_right_in[13]:37 0.001692516 +38 chanx_right_in[13]:33 chanx_right_in[5]:21 0.0003708091 +39 chanx_right_in[13]:33 chanx_right_in[5]:25 3.473664e-05 +40 chanx_right_in[13]:34 chanx_right_in[5]:25 0.0003708091 +41 chanx_right_in[13]:34 chanx_right_in[5]:26 3.473664e-05 +42 chanx_right_in[13]:22 chanx_right_in[12]:14 0.0004954466 +43 chanx_right_in[13]:23 chanx_right_in[12]:15 0.0004954466 +44 chanx_right_in[13]:26 chanx_right_in[12]:23 3.604776e-05 +45 chanx_right_in[13]:27 chanx_right_in[12]:24 3.604776e-05 +46 chanx_right_in[13] chanx_left_in[5]:23 0.001209259 +47 chanx_right_in[13]:37 chanx_left_in[5]:27 0.001209259 +48 chanx_right_in[13] chanx_left_in[6]:9 0.0009026685 +49 chanx_right_in[13]:33 chanx_left_in[6]:20 2.738444e-06 +50 chanx_right_in[13]:34 chanx_left_in[6]:19 2.738444e-06 +51 chanx_right_in[13]:37 chanx_left_in[6]:10 0.0009026685 +52 chanx_right_in[13] prog_clk[0]:223 1.715834e-05 +53 chanx_right_in[13]:19 prog_clk[0]:457 0.0001857522 +54 chanx_right_in[13]:19 prog_clk[0]:462 2.542763e-05 +55 chanx_right_in[13]:19 prog_clk[0]:446 1.499097e-05 +56 chanx_right_in[13]:18 prog_clk[0]:457 2.542763e-05 +57 chanx_right_in[13]:18 prog_clk[0]:452 0.0001857522 +58 chanx_right_in[13]:18 prog_clk[0]:445 1.499097e-05 +59 chanx_right_in[13]:14 prog_clk[0]:450 1.379114e-06 +60 chanx_right_in[13]:13 prog_clk[0]:451 1.379114e-06 +61 chanx_right_in[13]:31 prog_clk[0]:332 2.567274e-05 +62 chanx_right_in[13]:26 prog_clk[0]:511 1.517753e-05 +63 chanx_right_in[13]:28 prog_clk[0]:336 2.567274e-05 +64 chanx_right_in[13]:27 prog_clk[0]:510 1.517753e-05 +65 chanx_right_in[13]:33 prog_clk[0]:268 0.0001427162 +66 chanx_right_in[13]:33 prog_clk[0]:275 2.559348e-05 +67 chanx_right_in[13]:34 prog_clk[0]:274 2.559348e-05 +68 chanx_right_in[13]:34 prog_clk[0]:267 0.0001427162 +69 chanx_right_in[13]:37 prog_clk[0]:244 1.715834e-05 +70 chanx_right_in[13]:33 chany_top_in[2]:6 0.0003740106 +71 chanx_right_in[13]:34 chany_top_in[2]:7 0.0003740106 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:37 0.007443232 +1 chanx_right_in[13]:22 chanx_right_in[13]:21 0.00341 +2 chanx_right_in[13]:22 chanx_right_in[13]:6 0.00341 +3 chanx_right_in[13]:21 chanx_right_in[13]:20 0.00511125 +4 chanx_right_in[13]:19 chanx_right_in[13]:18 0.001509092 +5 chanx_right_in[13]:20 chanx_right_in[13]:19 0.00341 +6 chanx_right_in[13]:17 chanx_right_in[13]:16 0.0045 +7 chanx_right_in[13]:18 chanx_right_in[13]:17 0.00341 +8 chanx_right_in[13]:16 chanx_right_in[13]:15 0.002013393 +9 chanx_right_in[13]:15 chanx_right_in[13]:14 0.0045 +10 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0005267857 +11 chanx_right_in[13]:12 chanx_right_in[13]:11 0.003785715 +12 chanx_right_in[13]:13 chanx_right_in[13]:12 0.0045 +13 chanx_right_in[13]:11 chanx_right_in[13]:10 0.0045 +14 chanx_right_in[13]:10 chanx_right_in[13]:9 0.0078125 +15 chanx_right_in[13]:8 chanx_right_in[13]:7 0.001158482 +16 chanx_right_in[13]:9 chanx_right_in[13]:8 0.0045 +17 chanx_right_in[13]:7 BUFT_P_107:A 0.152 +18 chanx_right_in[13]:30 chanx_right_in[13]:29 9.51087e-05 +19 chanx_right_in[13]:31 chanx_right_in[13]:30 0.0045 +20 chanx_right_in[13]:31 chanx_right_in[13]:28 0.001162947 +21 chanx_right_in[13]:29 mux_top_track_16\/mux_l1_in_0_:A0 0.152 +22 chanx_right_in[13]:6 chanx_right_in[13]:5 0.0045 +23 chanx_right_in[13]:5 chanx_right_in[13]:4 0.0001847826 +24 chanx_right_in[13]:4 mux_left_track_3\/mux_l2_in_1_:A1 0.152 +25 chanx_right_in[13]:23 chanx_right_in[13]:22 0.003454891 +26 chanx_right_in[13]:24 chanx_right_in[13]:23 0.00341 +27 chanx_right_in[13]:26 chanx_right_in[13]:25 0.00341 +28 chanx_right_in[13]:25 chanx_right_in[13]:24 0.00159565 +29 chanx_right_in[13]:28 chanx_right_in[13]:27 0.00341 +30 chanx_right_in[13]:27 chanx_right_in[13]:26 0.001941492 +31 chanx_right_in[13]:32 chanx_right_in[13]:31 0.003591518 +32 chanx_right_in[13]:33 chanx_right_in[13]:32 0.00341 +33 chanx_right_in[13]:34 chanx_right_in[13]:33 0.005256558 +34 chanx_right_in[13]:35 chanx_right_in[13]:34 0.00341 +35 chanx_right_in[13]:37 chanx_right_in[13]:36 0.00341 +36 chanx_right_in[13]:36 chanx_right_in[13]:35 0.0009564499 + +*END + +*D_NET top_left_grid_pin_34_[0] 0.02306169 //LENGTH 146.850 LUMPCC 0.01015422 DR + +*CONN +*P top_left_grid_pin_34_[0] I *L 0.29796 *C 33.120 102.070 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 62.465 66.980 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.920 39.780 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 99.460 39.780 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 66.700 50.660 +*N top_left_grid_pin_34_[0]:5 *C 66.663 50.660 +*N top_left_grid_pin_34_[0]:6 *C 99.422 39.780 +*N top_left_grid_pin_34_[0]:7 *C 93.425 39.780 +*N top_left_grid_pin_34_[0]:8 *C 93.380 39.825 +*N top_left_grid_pin_34_[0]:9 *C 93.380 42.102 +*N top_left_grid_pin_34_[0]:10 *C 93.373 42.160 +*N top_left_grid_pin_34_[0]:11 *C 82.808 42.160 +*N top_left_grid_pin_34_[0]:12 *C 82.800 42.218 +*N top_left_grid_pin_34_[0]:13 *C 82.800 46.183 +*N top_left_grid_pin_34_[0]:14 *C 82.793 46.240 +*N top_left_grid_pin_34_[0]:15 *C 76.883 39.780 +*N top_left_grid_pin_34_[0]:16 *C 75.945 39.780 +*N top_left_grid_pin_34_[0]:17 *C 75.900 39.825 +*N top_left_grid_pin_34_[0]:18 *C 75.900 46.183 +*N top_left_grid_pin_34_[0]:19 *C 75.900 46.240 +*N top_left_grid_pin_34_[0]:20 *C 75.900 46.920 +*N top_left_grid_pin_34_[0]:21 *C 66.248 46.920 +*N top_left_grid_pin_34_[0]:22 *C 66.240 46.977 +*N top_left_grid_pin_34_[0]:23 *C 66.240 50.615 +*N top_left_grid_pin_34_[0]:24 *C 66.240 50.660 +*N top_left_grid_pin_34_[0]:25 *C 64.445 50.660 +*N top_left_grid_pin_34_[0]:26 *C 64.400 50.705 +*N top_left_grid_pin_34_[0]:27 *C 64.400 66.935 +*N top_left_grid_pin_34_[0]:28 *C 64.355 66.980 +*N top_left_grid_pin_34_[0]:29 *C 62.503 66.980 +*N top_left_grid_pin_34_[0]:30 *C 63.020 66.980 +*N top_left_grid_pin_34_[0]:31 *C 63.020 67.025 +*N top_left_grid_pin_34_[0]:32 *C 63.020 69.983 +*N top_left_grid_pin_34_[0]:33 *C 63.013 70.040 +*N top_left_grid_pin_34_[0]:34 *C 60.740 70.040 +*N top_left_grid_pin_34_[0]:35 *C 60.720 70.047 +*N top_left_grid_pin_34_[0]:36 *C 60.720 101.312 +*N top_left_grid_pin_34_[0]:37 *C 60.700 101.320 +*N top_left_grid_pin_34_[0]:38 *C 56.580 101.320 +*N top_left_grid_pin_34_[0]:39 *C 56.580 99.960 +*N top_left_grid_pin_34_[0]:40 *C 44.160 99.960 +*N top_left_grid_pin_34_[0]:41 *C 44.160 101.320 +*N top_left_grid_pin_34_[0]:42 *C 33.128 101.320 +*N top_left_grid_pin_34_[0]:43 *C 33.120 101.378 + +*CAP +0 top_left_grid_pin_34_[0] 5.990133e-05 +1 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_34_[0]:5 3.760195e-05 +6 top_left_grid_pin_34_[0]:6 0.0003739365 +7 top_left_grid_pin_34_[0]:7 0.0003739365 +8 top_left_grid_pin_34_[0]:8 0.0001586319 +9 top_left_grid_pin_34_[0]:9 0.0001586319 +10 top_left_grid_pin_34_[0]:10 0.0003959873 +11 top_left_grid_pin_34_[0]:11 0.0003959873 +12 top_left_grid_pin_34_[0]:12 0.0002492913 +13 top_left_grid_pin_34_[0]:13 0.0002492913 +14 top_left_grid_pin_34_[0]:14 0.0002240391 +15 top_left_grid_pin_34_[0]:15 9.05015e-05 +16 top_left_grid_pin_34_[0]:16 9.05015e-05 +17 top_left_grid_pin_34_[0]:17 0.0003650679 +18 top_left_grid_pin_34_[0]:18 0.0003650679 +19 top_left_grid_pin_34_[0]:19 0.0002870597 +20 top_left_grid_pin_34_[0]:20 0.0004545964 +21 top_left_grid_pin_34_[0]:21 0.0003915757 +22 top_left_grid_pin_34_[0]:22 0.0002742507 +23 top_left_grid_pin_34_[0]:23 0.0002742507 +24 top_left_grid_pin_34_[0]:24 0.0001970568 +25 top_left_grid_pin_34_[0]:25 0.000124304 +26 top_left_grid_pin_34_[0]:26 0.000714308 +27 top_left_grid_pin_34_[0]:27 0.000714308 +28 top_left_grid_pin_34_[0]:28 0.0001192179 +29 top_left_grid_pin_34_[0]:29 5.580546e-05 +30 top_left_grid_pin_34_[0]:30 0.0002102957 +31 top_left_grid_pin_34_[0]:31 0.000213162 +32 top_left_grid_pin_34_[0]:32 0.000213162 +33 top_left_grid_pin_34_[0]:33 8.405883e-05 +34 top_left_grid_pin_34_[0]:34 8.405883e-05 +35 top_left_grid_pin_34_[0]:35 0.001166516 +36 top_left_grid_pin_34_[0]:36 0.001166516 +37 top_left_grid_pin_34_[0]:37 0.0002716896 +38 top_left_grid_pin_34_[0]:38 0.0003367937 +39 top_left_grid_pin_34_[0]:39 0.0006246892 +40 top_left_grid_pin_34_[0]:40 0.0006364917 +41 top_left_grid_pin_34_[0]:41 0.0003589666 +42 top_left_grid_pin_34_[0]:42 0.00028206 +43 top_left_grid_pin_34_[0]:43 5.990133e-05 +44 top_left_grid_pin_34_[0]:42 top_left_grid_pin_35_[0]:33 0.0006415492 +45 top_left_grid_pin_34_[0]:42 top_left_grid_pin_35_[0]:35 1.481916e-05 +46 top_left_grid_pin_34_[0]:41 top_left_grid_pin_35_[0]:32 0.0006429192 +47 top_left_grid_pin_34_[0]:41 top_left_grid_pin_35_[0]:36 1.481916e-05 +48 top_left_grid_pin_34_[0]:40 top_left_grid_pin_35_[0]:28 1.595555e-05 +49 top_left_grid_pin_34_[0]:40 top_left_grid_pin_35_[0]:31 1.369984e-06 +50 top_left_grid_pin_34_[0]:40 top_left_grid_pin_35_[0]:33 1.087396e-06 +51 top_left_grid_pin_34_[0]:39 top_left_grid_pin_35_[0]:27 1.595555e-05 +52 top_left_grid_pin_34_[0]:39 top_left_grid_pin_35_[0]:32 1.087396e-06 +53 top_left_grid_pin_34_[0]:21 chanx_left_in[5]:27 8.170622e-05 +54 top_left_grid_pin_34_[0]:21 chanx_left_in[5]:28 8.607983e-05 +55 top_left_grid_pin_34_[0]:14 chanx_left_in[5]:23 0.0003886042 +56 top_left_grid_pin_34_[0]:11 chanx_left_in[5]:27 2.543746e-05 +57 top_left_grid_pin_34_[0]:10 chanx_left_in[5]:23 2.543746e-05 +58 top_left_grid_pin_34_[0]:19 chanx_left_in[5]:27 0.0003886042 +59 top_left_grid_pin_34_[0]:20 chanx_left_in[5]:23 8.170622e-05 +60 top_left_grid_pin_34_[0]:20 chanx_left_in[5]:27 8.607983e-05 +61 top_left_grid_pin_34_[0]:21 chanx_left_in[6]:20 0.0005318035 +62 top_left_grid_pin_34_[0]:13 chanx_left_in[6]:18 5.641701e-07 +63 top_left_grid_pin_34_[0]:14 chanx_left_in[6]:19 0.0001376853 +64 top_left_grid_pin_34_[0]:12 chanx_left_in[6]:17 5.641701e-07 +65 top_left_grid_pin_34_[0]:11 chanx_left_in[6]:10 7.551476e-05 +66 top_left_grid_pin_34_[0]:10 chanx_left_in[6]:9 7.551476e-05 +67 top_left_grid_pin_34_[0]:19 chanx_left_in[6]:20 0.0001376853 +68 top_left_grid_pin_34_[0]:20 chanx_left_in[6]:19 0.0005318035 +69 top_left_grid_pin_34_[0]:11 chanx_left_in[14]:15 0.0005909223 +70 top_left_grid_pin_34_[0]:10 chanx_left_in[14]:14 0.0005909223 +71 top_left_grid_pin_34_[0]:9 prog_clk[0]:265 7.753749e-06 +72 top_left_grid_pin_34_[0]:8 prog_clk[0]:262 7.753749e-06 +73 top_left_grid_pin_34_[0]:31 prog_clk[0]:337 1.347082e-06 +74 top_left_grid_pin_34_[0]:32 prog_clk[0]:338 1.347082e-06 +75 top_left_grid_pin_34_[0]:42 prog_clk[0]:360 3.163083e-05 +76 top_left_grid_pin_34_[0]:42 prog_clk[0]:594 0.0001196598 +77 top_left_grid_pin_34_[0]:18 prog_clk[0]:292 2.806017e-07 +78 top_left_grid_pin_34_[0]:18 prog_clk[0]:298 4.310336e-08 +79 top_left_grid_pin_34_[0]:17 prog_clk[0]:289 2.806017e-07 +80 top_left_grid_pin_34_[0]:17 prog_clk[0]:292 4.310336e-08 +81 top_left_grid_pin_34_[0]:41 prog_clk[0]:356 3.163083e-05 +82 top_left_grid_pin_34_[0]:41 prog_clk[0]:360 0.0001196598 +83 top_left_grid_pin_34_[0]:40 prog_clk[0]:360 0.0004013823 +84 top_left_grid_pin_34_[0]:39 prog_clk[0]:356 0.0004013823 +85 top_left_grid_pin_34_[0]:33 chany_top_in[1]:6 5.737386e-05 +86 top_left_grid_pin_34_[0]:34 chany_top_in[1]:11 5.737386e-05 +87 top_left_grid_pin_34_[0]:35 chany_top_in[1]:12 0.0003357381 +88 top_left_grid_pin_34_[0]:37 chany_top_in[1]:14 1.709164e-05 +89 top_left_grid_pin_34_[0]:36 chany_top_in[1]:13 0.0003357381 +90 top_left_grid_pin_34_[0]:39 chany_top_in[1]:12 1.984227e-05 +91 top_left_grid_pin_34_[0]:39 chany_top_in[1]:16 1.395534e-05 +92 top_left_grid_pin_34_[0]:38 chany_top_in[1] 1.395534e-05 +93 top_left_grid_pin_34_[0]:38 chany_top_in[1]:13 1.984227e-05 +94 top_left_grid_pin_34_[0]:38 chany_top_in[1]:15 1.709164e-05 +95 top_left_grid_pin_34_[0]:33 chany_top_in[12]:6 5.737386e-05 +96 top_left_grid_pin_34_[0]:34 chany_top_in[12]:14 5.737386e-05 +97 top_left_grid_pin_34_[0]:41 chany_top_in[12]:16 1.458253e-05 +98 top_left_grid_pin_34_[0]:40 chany_top_in[12]:15 1.458253e-05 +99 top_left_grid_pin_34_[0]:40 chany_top_in[12]:17 0.0004552857 +100 top_left_grid_pin_34_[0]:39 chany_top_in[12]:18 0.0004552857 +101 top_left_grid_pin_34_[0]:39 chany_top_in[12]:19 5.538967e-06 +102 top_left_grid_pin_34_[0]:38 chany_top_in[12] 5.538967e-06 +103 top_left_grid_pin_34_[0]:35 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0005334934 +104 top_left_grid_pin_34_[0]:36 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0005334934 +105 top_left_grid_pin_34_[0]:22 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.774401e-07 +106 top_left_grid_pin_34_[0]:23 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.774401e-07 +107 top_left_grid_pin_34_[0]:27 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004106623 +108 top_left_grid_pin_34_[0]:26 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004106623 + +*RES +0 top_left_grid_pin_34_[0] top_left_grid_pin_34_[0]:43 0.0006183037 +1 top_left_grid_pin_34_[0]:5 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_34_[0]:22 top_left_grid_pin_34_[0]:21 0.00341 +3 top_left_grid_pin_34_[0]:21 top_left_grid_pin_34_[0]:20 0.001512225 +4 top_left_grid_pin_34_[0]:24 top_left_grid_pin_34_[0]:23 0.0045 +5 top_left_grid_pin_34_[0]:24 top_left_grid_pin_34_[0]:5 0.0003772322 +6 top_left_grid_pin_34_[0]:23 top_left_grid_pin_34_[0]:22 0.003247768 +7 top_left_grid_pin_34_[0]:28 top_left_grid_pin_34_[0]:27 0.0045 +8 top_left_grid_pin_34_[0]:27 top_left_grid_pin_34_[0]:26 0.01449107 +9 top_left_grid_pin_34_[0]:25 top_left_grid_pin_34_[0]:24 0.001602679 +10 top_left_grid_pin_34_[0]:26 top_left_grid_pin_34_[0]:25 0.0045 +11 top_left_grid_pin_34_[0]:13 top_left_grid_pin_34_[0]:12 0.003540179 +12 top_left_grid_pin_34_[0]:14 top_left_grid_pin_34_[0]:13 0.00341 +13 top_left_grid_pin_34_[0]:12 top_left_grid_pin_34_[0]:11 0.00341 +14 top_left_grid_pin_34_[0]:11 top_left_grid_pin_34_[0]:10 0.001655183 +15 top_left_grid_pin_34_[0]:9 top_left_grid_pin_34_[0]:8 0.002033482 +16 top_left_grid_pin_34_[0]:10 top_left_grid_pin_34_[0]:9 0.00341 +17 top_left_grid_pin_34_[0]:7 top_left_grid_pin_34_[0]:6 0.005354911 +18 top_left_grid_pin_34_[0]:8 top_left_grid_pin_34_[0]:7 0.0045 +19 top_left_grid_pin_34_[0]:6 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +20 top_left_grid_pin_34_[0]:30 top_left_grid_pin_34_[0]:29 0.0004620536 +21 top_left_grid_pin_34_[0]:30 top_left_grid_pin_34_[0]:28 0.001191964 +22 top_left_grid_pin_34_[0]:31 top_left_grid_pin_34_[0]:30 0.0045 +23 top_left_grid_pin_34_[0]:32 top_left_grid_pin_34_[0]:31 0.002640625 +24 top_left_grid_pin_34_[0]:33 top_left_grid_pin_34_[0]:32 0.00341 +25 top_left_grid_pin_34_[0]:34 top_left_grid_pin_34_[0]:33 0.000356025 +26 top_left_grid_pin_34_[0]:35 top_left_grid_pin_34_[0]:34 0.00341 +27 top_left_grid_pin_34_[0]:37 top_left_grid_pin_34_[0]:36 0.00341 +28 top_left_grid_pin_34_[0]:36 top_left_grid_pin_34_[0]:35 0.004898183 +29 top_left_grid_pin_34_[0]:43 top_left_grid_pin_34_[0]:42 0.00341 +30 top_left_grid_pin_34_[0]:42 top_left_grid_pin_34_[0]:41 0.001728425 +31 top_left_grid_pin_34_[0]:18 top_left_grid_pin_34_[0]:17 0.005676339 +32 top_left_grid_pin_34_[0]:19 top_left_grid_pin_34_[0]:18 0.00341 +33 top_left_grid_pin_34_[0]:19 top_left_grid_pin_34_[0]:14 0.001079825 +34 top_left_grid_pin_34_[0]:16 top_left_grid_pin_34_[0]:15 0.0008370536 +35 top_left_grid_pin_34_[0]:17 top_left_grid_pin_34_[0]:16 0.0045 +36 top_left_grid_pin_34_[0]:15 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +37 top_left_grid_pin_34_[0]:29 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +38 top_left_grid_pin_34_[0]:41 top_left_grid_pin_34_[0]:40 0.0002130666 +39 top_left_grid_pin_34_[0]:40 top_left_grid_pin_34_[0]:39 0.0019458 +40 top_left_grid_pin_34_[0]:39 top_left_grid_pin_34_[0]:38 0.0002130666 +41 top_left_grid_pin_34_[0]:38 top_left_grid_pin_34_[0]:37 0.0006454666 +42 top_left_grid_pin_34_[0]:20 top_left_grid_pin_34_[0]:19 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[0] 0.01385588 //LENGTH 101.480 LUMPCC 0.005380057 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 118.985 28.560 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 61.740 66.640 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 59.980 60.860 +*N mux_tree_tapbuf_size8_0_sram[0]:3 *C 62.160 57.120 +*N mux_tree_tapbuf_size8_0_sram[0]:4 *C 60.018 60.860 +*N mux_tree_tapbuf_size8_0_sram[0]:5 *C 61.640 66.640 +*N mux_tree_tapbuf_size8_0_sram[0]:6 *C 61.640 66.595 +*N mux_tree_tapbuf_size8_0_sram[0]:7 *C 61.640 60.905 +*N mux_tree_tapbuf_size8_0_sram[0]:8 *C 61.640 60.860 +*N mux_tree_tapbuf_size8_0_sram[0]:9 *C 62.515 60.860 +*N mux_tree_tapbuf_size8_0_sram[0]:10 *C 62.560 60.815 +*N mux_tree_tapbuf_size8_0_sram[0]:11 *C 62.560 57.178 +*N mux_tree_tapbuf_size8_0_sram[0]:12 *C 62.560 57.120 +*N mux_tree_tapbuf_size8_0_sram[0]:13 *C 62.560 57.113 +*N mux_tree_tapbuf_size8_0_sram[0]:14 *C 62.560 27.888 +*N mux_tree_tapbuf_size8_0_sram[0]:15 *C 62.580 27.880 +*N mux_tree_tapbuf_size8_0_sram[0]:16 *C 112.370 27.880 +*N mux_tree_tapbuf_size8_0_sram[0]:17 *C 118.213 27.880 +*N mux_tree_tapbuf_size8_0_sram[0]:18 *C 118.220 27.938 +*N mux_tree_tapbuf_size8_0_sram[0]:19 *C 118.220 28.515 +*N mux_tree_tapbuf_size8_0_sram[0]:20 *C 118.265 28.560 +*N mux_tree_tapbuf_size8_0_sram[0]:21 *C 118.948 28.560 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_0_sram[0]:3 8.920955e-05 +4 mux_tree_tapbuf_size8_0_sram[0]:4 8.212122e-05 +5 mux_tree_tapbuf_size8_0_sram[0]:5 3.315751e-05 +6 mux_tree_tapbuf_size8_0_sram[0]:6 0.0003542945 +7 mux_tree_tapbuf_size8_0_sram[0]:7 0.0003542945 +8 mux_tree_tapbuf_size8_0_sram[0]:8 0.000165351 +9 mux_tree_tapbuf_size8_0_sram[0]:9 4.913624e-05 +10 mux_tree_tapbuf_size8_0_sram[0]:10 0.0002623693 +11 mux_tree_tapbuf_size8_0_sram[0]:11 0.0002623693 +12 mux_tree_tapbuf_size8_0_sram[0]:12 8.920955e-05 +13 mux_tree_tapbuf_size8_0_sram[0]:13 0.001400354 +14 mux_tree_tapbuf_size8_0_sram[0]:14 0.001400354 +15 mux_tree_tapbuf_size8_0_sram[0]:15 0.001693607 +16 mux_tree_tapbuf_size8_0_sram[0]:16 0.001819183 +17 mux_tree_tapbuf_size8_0_sram[0]:17 0.0001255752 +18 mux_tree_tapbuf_size8_0_sram[0]:18 6.668944e-05 +19 mux_tree_tapbuf_size8_0_sram[0]:19 6.668944e-05 +20 mux_tree_tapbuf_size8_0_sram[0]:20 7.943077e-05 +21 mux_tree_tapbuf_size8_0_sram[0]:21 7.943077e-05 +22 mux_tree_tapbuf_size8_0_sram[0]:8 chanx_right_in[10]:18 3.920731e-05 +23 mux_tree_tapbuf_size8_0_sram[0]:8 chanx_right_in[10]:19 6.552703e-05 +24 mux_tree_tapbuf_size8_0_sram[0]:9 chanx_right_in[10]:19 3.920731e-05 +25 mux_tree_tapbuf_size8_0_sram[0]:15 chanx_right_in[10]:31 0.0009491743 +26 mux_tree_tapbuf_size8_0_sram[0]:17 chanx_right_in[10]:32 0.0001596061 +27 mux_tree_tapbuf_size8_0_sram[0]:4 chanx_right_in[10]:18 6.552703e-05 +28 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_right_in[10]:31 0.0001596061 +29 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_right_in[10]:32 0.0009491743 +30 mux_tree_tapbuf_size8_0_sram[0]:13 chanx_right_in[12]:25 0.0002444696 +31 mux_tree_tapbuf_size8_0_sram[0]:15 chanx_right_in[12]:27 1.887177e-05 +32 mux_tree_tapbuf_size8_0_sram[0]:14 chanx_right_in[12]:26 0.0002444696 +33 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_right_in[12]:28 1.887177e-05 +34 mux_tree_tapbuf_size8_0_sram[0]:15 chanx_left_in[16]:35 0.0002909279 +35 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_left_in[16]:34 0.0002909279 +36 mux_tree_tapbuf_size8_0_sram[0]:15 chany_top_in[17]:7 8.151526e-05 +37 mux_tree_tapbuf_size8_0_sram[0]:15 chany_top_in[17]:9 0.0005498166 +38 mux_tree_tapbuf_size8_0_sram[0]:16 chany_top_in[17]:8 8.151526e-05 +39 mux_tree_tapbuf_size8_0_sram[0]:16 chany_top_in[17]:10 0.0005498166 +40 mux_tree_tapbuf_size8_0_sram[0]:15 chanx_right_in[11]:10 0.0002125957 +41 mux_tree_tapbuf_size8_0_sram[0]:17 chanx_right_in[11]:11 7.831665e-05 +42 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_right_in[11]:10 7.831665e-05 +43 mux_tree_tapbuf_size8_0_sram[0]:16 chanx_right_in[11]:11 0.0002125957 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_0_sram[0]:21 0.152 +1 mux_tree_tapbuf_size8_0_sram[0]:5 mux_top_track_0\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[0]:6 mux_tree_tapbuf_size8_0_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size8_0_sram[0]:8 mux_tree_tapbuf_size8_0_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size8_0_sram[0]:8 mux_tree_tapbuf_size8_0_sram[0]:4 0.001448661 +5 mux_tree_tapbuf_size8_0_sram[0]:7 mux_tree_tapbuf_size8_0_sram[0]:6 0.005080358 +6 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:8 0.00078125 +7 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size8_0_sram[0]:11 mux_tree_tapbuf_size8_0_sram[0]:10 0.003247768 +9 mux_tree_tapbuf_size8_0_sram[0]:12 mux_tree_tapbuf_size8_0_sram[0]:11 0.00341 +10 mux_tree_tapbuf_size8_0_sram[0]:12 mux_tree_tapbuf_size8_0_sram[0]:3 5.69697e-05 +11 mux_tree_tapbuf_size8_0_sram[0]:13 mux_tree_tapbuf_size8_0_sram[0]:12 0.00341 +12 mux_tree_tapbuf_size8_0_sram[0]:15 mux_tree_tapbuf_size8_0_sram[0]:14 0.00341 +13 mux_tree_tapbuf_size8_0_sram[0]:14 mux_tree_tapbuf_size8_0_sram[0]:13 0.004578583 +14 mux_tree_tapbuf_size8_0_sram[0]:18 mux_tree_tapbuf_size8_0_sram[0]:17 0.00341 +15 mux_tree_tapbuf_size8_0_sram[0]:17 mux_tree_tapbuf_size8_0_sram[0]:16 0.000915325 +16 mux_tree_tapbuf_size8_0_sram[0]:20 mux_tree_tapbuf_size8_0_sram[0]:19 0.0045 +17 mux_tree_tapbuf_size8_0_sram[0]:19 mux_tree_tapbuf_size8_0_sram[0]:18 0.000515625 +18 mux_tree_tapbuf_size8_0_sram[0]:21 mux_tree_tapbuf_size8_0_sram[0]:20 0.000609375 +19 mux_tree_tapbuf_size8_0_sram[0]:4 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size8_0_sram[0]:16 mux_tree_tapbuf_size8_0_sram[0]:15 0.007800432 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009054282 //LENGTH 7.070 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 60.895 66.640 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 56.945 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 56.983 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.675 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 60.720 68.975 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 60.720 66.685 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 60.720 66.640 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 60.895 66.640 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002472545 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002472545 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001498526 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001498526 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.477595e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.443791e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003296875 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009303823 //LENGTH 6.325 LUMPCC 0.0002848749 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_1_:X O *L 0 *C 23.175 66.300 +*I mux_left_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 20.990 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 21.027 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.955 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 23.000 69.655 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 23.000 66.345 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 23.000 66.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 23.175 66.300 + +*CAP +0 mux_left_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.805578e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.805578e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002070991 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002070991 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.840624e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.47914e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[4]:9 8.54047e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[4]:14 8.54047e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:13 5.13684e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:14 5.13684e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size8_2_sram[2]:16 5.664361e-06 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_2_sram[2]:15 5.664361e-06 + +*RES +0 mux_left_track_3\/mux_l2_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001720982 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002955357 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001051284 //LENGTH 7.505 LUMPCC 0.000235306 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 68.825 51.000 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 73.700 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 73.663 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 69.505 52.700 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 69.460 52.655 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 69.460 51.045 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 69.415 51.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 68.862 51.000 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002461312 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002461312 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.770292e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.770292e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.315491e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.315491e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[3]:8 5.198288e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[3]:9 5.198288e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_1_sram[1]:11 6.567012e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_1_sram[1]:12 6.567012e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003712054 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002098147 //LENGTH 15.645 LUMPCC 0.0005124825 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 91.365 59.160 +*I mux_right_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 97.980 66.980 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 97.943 66.980 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 95.680 66.980 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 95.680 66.300 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 92.045 66.300 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 92.000 66.255 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 92.000 59.205 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 91.955 59.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 91.403 59.160 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.578288e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.243223e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003208883 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002742389 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003654222 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003654222 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.973902e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.973902e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[10]:16 8.252812e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[10]:17 8.252812e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_4_sram[2]:9 2.915404e-06 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_4_sram[2]:8 9.217947e-05 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_4_sram[2]:8 2.915404e-06 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_4_sram[2]:9 9.217947e-05 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 7.861827e-05 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 7.861827e-05 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0004933036 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.006294644 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003245536 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A1 0.152 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0006071429 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002020089 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004049961 //LENGTH 2.935 LUMPCC 0.0001362629 DR + +*CONN +*I mux_top_track_10\/mux_l2_in_1_:X O *L 0 *C 123.915 60.860 +*I mux_top_track_10\/mux_l3_in_0_:A0 I *L 0.001631 *C 121.270 60.860 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 121.308 60.860 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 123.878 60.860 + +*CAP +0 mux_top_track_10\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_10\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001333666 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001333666 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size4_1_sram[2]:12 6.813145e-05 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size4_1_sram[2]:13 6.813145e-05 + +*RES +0 mux_top_track_10\/mux_l2_in_1_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_10\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002294643 + +*END + +*D_NET mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006524359 //LENGTH 4.730 LUMPCC 9.694987e-05 DR + +*CONN +*I mux_top_track_20\/mux_l1_in_1_:X O *L 0 *C 71.125 39.780 +*I mux_top_track_20\/mux_l2_in_0_:A0 I *L 0.001631 *C 72.395 42.500 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 72.395 42.500 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 72.220 42.500 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 72.220 42.455 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 72.220 39.825 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 72.175 39.780 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 71.163 39.780 + +*CAP +0 mux_top_track_20\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_20\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.907856e-05 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.393888e-05 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001500194 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001500194 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.521488e-05 +7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.521488e-05 +8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[16]:27 7.998252e-06 +9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[16]:29 4.047668e-05 +10 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[16]:28 7.998252e-06 +11 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[16]:30 4.047668e-05 + +*RES +0 mux_top_track_20\/mux_l1_in_1_:X mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_20\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009040178 + +*END + +*D_NET mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001186473 //LENGTH 8.880 LUMPCC 0.000339018 DR + +*CONN +*I mux_top_track_30\/mux_l1_in_0_:X O *L 0 *C 51.695 79.560 +*I mux_top_track_30\/mux_l2_in_0_:A1 I *L 0.00198 *C 49.320 85.340 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 49.220 85.340 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.220 85.295 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.220 79.605 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.265 79.560 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 51.658 79.560 + +*CAP +0 mux_top_track_30\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_30\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.648206e-05 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002839704 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002839704 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001205161 +6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001205161 +7 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_37_[0]:22 6.508986e-05 +8 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_37_[0]:18 0.0001044191 +9 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_37_[0]:19 6.508986e-05 +10 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_37_[0]:17 0.0001044191 + +*RES +0 mux_top_track_30\/mux_l1_in_0_:X mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_30\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005080357 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002136161 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000567792 //LENGTH 4.700 LUMPCC 6.625283e-05 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_1_:X O *L 0 *C 116.205 72.080 +*I mux_right_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 117.935 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 117.898 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 117.345 70.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 117.300 70.085 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 117.300 72.035 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 117.255 72.080 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 116.243 72.080 + +*CAP +0 mux_right_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.70016e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.70016e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001197479 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001197479 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.302006e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.302006e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:18 7.673243e-06 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size9_0_sram[1]:20 2.545317e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:19 7.673243e-06 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size9_0_sram[1]:21 2.545317e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004933036 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001741071 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0] 0.001095342 //LENGTH 8.430 LUMPCC 0.0001731894 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_0_:X O *L 0 *C 108.385 60.520 +*I mux_right_track_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 108.200 52.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 108.100 52.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 108.100 52.745 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 108.100 60.475 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 108.100 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 108.385 60.520 + +*CAP +0 mux_right_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 3.428844e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0003794559 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0003794559 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 6.448763e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 6.246448e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 3.796998e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 3.796998e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 4.862472e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 4.862472e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_right_track_4\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.006901786 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0001548913 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001624537 //LENGTH 11.255 LUMPCC 0.000836328 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_1_:X O *L 0 *C 39.735 55.080 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 31.110 53.380 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 31.148 53.380 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 35.835 53.380 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 35.880 53.425 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 35.880 55.035 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 35.925 55.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 39.698 55.080 + +*CAP +0 mux_left_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001148067 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001148067 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.63537e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.63537e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002119443 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002119443 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[18]:12 7.742755e-07 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[18]:11 0.0001925982 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[18]:13 7.742755e-07 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_right_in[18]:10 0.0001925982 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_top_grid_pin_44_[0]:17 5.197489e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 left_top_grid_pin_44_[0]:16 5.197489e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001112876 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001112876 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.222541e-05 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.930362e-05 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.222541e-05 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.930362e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003368304 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004185268 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001018421 //LENGTH 5.890 LUMPCC 0.0005192364 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_3_:X O *L 0 *C 23.285 58.480 +*I mux_left_track_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 26.375 60.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 26.375 60.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 26.220 60.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 26.220 60.475 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 26.220 58.525 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 26.175 58.480 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 23.323 58.480 + +*CAP +0 mux_left_track_1\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.4162e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.89704e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001048128 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001048128 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.721324e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.721324e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 left_top_grid_pin_43_[0]:15 5.868921e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 left_top_grid_pin_43_[0]:16 5.868921e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size6_1_sram[1]:14 0.0001165005 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size6_1_sram[1]:15 0.0001165005 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 ropt_net_129:7 8.442848e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 ropt_net_129:8 8.442848e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_3_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002546875 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001741072 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.423914e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_1\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET ropt_net_158 0.0007737034 //LENGTH 7.120 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_756:X O *L 0 *C 7.030 18.020 +*I ropt_mt_inst_784:A I *L 0.001767 *C 3.220 20.400 +*N ropt_net_158:2 *C 3.258 20.400 +*N ropt_net_158:3 *C 6.395 20.400 +*N ropt_net_158:4 *C 6.440 20.355 +*N ropt_net_158:5 *C 6.440 18.065 +*N ropt_net_158:6 *C 6.485 18.020 +*N ropt_net_158:7 *C 6.993 18.020 + +*CAP +0 ropt_mt_inst_756:X 1e-06 +1 ropt_mt_inst_784:A 1e-06 +2 ropt_net_158:2 0.0001913429 +3 ropt_net_158:3 0.0001913429 +4 ropt_net_158:4 0.0001454219 +5 ropt_net_158:5 0.0001454219 +6 ropt_net_158:6 4.908701e-05 +7 ropt_net_158:7 4.908701e-05 + +*RES +0 ropt_mt_inst_756:X ropt_net_158:7 0.152 +1 ropt_net_158:2 ropt_mt_inst_784:A 0.152 +2 ropt_net_158:3 ropt_net_158:2 0.002801339 +3 ropt_net_158:4 ropt_net_158:3 0.0045 +4 ropt_net_158:6 ropt_net_158:5 0.0045 +5 ropt_net_158:5 ropt_net_158:4 0.002044643 +6 ropt_net_158:7 ropt_net_158:6 0.000453125 + +*END + +*D_NET ropt_net_157 0.00112118 //LENGTH 9.215 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 11.695 44.540 +*I ropt_mt_inst_783:A I *L 0.001767 *C 3.220 44.880 +*N ropt_net_157:2 *C 3.220 44.880 +*N ropt_net_157:3 *C 3.220 44.540 +*N ropt_net_157:4 *C 11.658 44.540 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 ropt_mt_inst_783:A 1e-06 +2 ropt_net_157:2 5.930939e-05 +3 ropt_net_157:3 0.0005443657 +4 ropt_net_157:4 0.000515505 + +*RES +0 ropt_mt_inst_766:X ropt_net_157:4 0.152 +1 ropt_net_157:2 ropt_mt_inst_783:A 0.152 +2 ropt_net_157:4 ropt_net_157:3 0.007533482 +3 ropt_net_157:3 ropt_net_157:2 0.0003035714 + +*END + +*D_NET chanx_left_out[13] 0.001621009 //LENGTH 12.160 LUMPCC 0.0002358296 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 9.855 68.680 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 65.960 +*N chanx_left_out[13]:2 *C 1.833 65.960 +*N chanx_left_out[13]:3 *C 1.840 66.017 +*N chanx_left_out[13]:4 *C 1.840 68.635 +*N chanx_left_out[13]:5 *C 1.885 68.680 +*N chanx_left_out[13]:6 *C 9.818 68.680 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 chanx_left_out[13] 6.8219e-05 +2 chanx_left_out[13]:2 6.8219e-05 +3 chanx_left_out[13]:3 0.0001455991 +4 chanx_left_out[13]:4 0.0001455991 +5 chanx_left_out[13]:5 0.0004782715 +6 chanx_left_out[13]:6 0.0004782715 +7 chanx_left_out[13]:6 ropt_net_150:3 0.0001065104 +8 chanx_left_out[13]:5 ropt_net_150:4 0.0001065104 +9 chanx_left_out[13]:4 ropt_net_150:6 1.140438e-05 +10 chanx_left_out[13]:3 ropt_net_150:7 1.140438e-05 + +*RES +0 ropt_mt_inst_773:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:6 chanx_left_out[13]:5 0.007082589 +2 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.002337054 +4 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +5 chanx_left_out[13]:2 chanx_left_out[13] 9.439165e-05 + +*END + +*D_NET ropt_net_129 0.003769624 //LENGTH 24.060 LUMPCC 0.001324529 DR + +*CONN +*I BUFT_P_99:X O *L 0 *C 25.300 58.140 +*I ropt_mt_inst_752:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_129:2 *C 3.220 58.480 +*N ropt_net_129:3 *C 3.220 58.140 +*N ropt_net_129:4 *C 5.980 58.140 +*N ropt_net_129:5 *C 5.980 58.480 +*N ropt_net_129:6 *C 22.540 58.480 +*N ropt_net_129:7 *C 22.540 58.140 +*N ropt_net_129:8 *C 25.263 58.140 + +*CAP +0 BUFT_P_99:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_129:2 5.735863e-05 +3 ropt_net_129:3 0.0001581124 +4 ropt_net_129:4 0.0001516095 +5 ropt_net_129:5 0.0008857297 +6 ropt_net_129:6 0.0008903838 +7 ropt_net_129:7 0.0001629228 +8 ropt_net_129:8 0.0001369773 +9 ropt_net_129:3 mux_tree_tapbuf_size14_1_sram[0]:32 7.673333e-05 +10 ropt_net_129:4 mux_tree_tapbuf_size14_1_sram[0]:31 7.673333e-05 +11 ropt_net_129:5 mux_tree_tapbuf_size14_1_sram[0]:32 3.241711e-05 +12 ropt_net_129:6 mux_tree_tapbuf_size14_1_sram[0]:31 3.241711e-05 +13 ropt_net_129:8 mux_tree_tapbuf_size6_1_sram[1]:15 6.662554e-06 +14 ropt_net_129:5 mux_tree_tapbuf_size6_1_sram[1]:10 9.168083e-05 +15 ropt_net_129:5 mux_tree_tapbuf_size6_1_sram[1]:14 0.0002236536 +16 ropt_net_129:6 mux_tree_tapbuf_size6_1_sram[1]:11 9.168083e-05 +17 ropt_net_129:6 mux_tree_tapbuf_size6_1_sram[1]:15 0.0002236536 +18 ropt_net_129:7 mux_tree_tapbuf_size6_1_sram[1]:14 6.662554e-06 +19 ropt_net_129:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.706902e-05 +20 ropt_net_129:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.706902e-05 +21 ropt_net_129:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.442848e-05 +22 ropt_net_129:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.442848e-05 +23 ropt_net_129:2 ropt_net_163:11 2.759449e-07 +24 ropt_net_129:3 ropt_net_163:10 2.759449e-07 +25 ropt_net_129:3 ropt_net_163:11 2.361737e-06 +26 ropt_net_129:4 ropt_net_163:10 5.201113e-06 +27 ropt_net_129:4 ropt_net_163:12 2.361737e-06 +28 ropt_net_129:5 ropt_net_163:11 4.698214e-05 +29 ropt_net_129:6 ropt_net_163:12 4.178103e-05 + +*RES +0 BUFT_P_99:X ropt_net_129:8 0.152 +1 ropt_net_129:8 ropt_net_129:7 0.002430804 +2 ropt_net_129:2 ropt_mt_inst_752:A 0.152 +3 ropt_net_129:3 ropt_net_129:2 0.0003035715 +4 ropt_net_129:4 ropt_net_129:3 0.002464286 +5 ropt_net_129:5 ropt_net_129:4 0.0003035715 +6 ropt_net_129:6 ropt_net_129:5 0.01478572 +7 ropt_net_129:7 ropt_net_129:6 0.0003035715 + +*END + +*D_NET chanx_right_in[14] 0.02398304 //LENGTH 176.035 LUMPCC 0.01058707 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 140.450 17.680 +*I mux_top_track_18\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.070 44.540 +*I FTB_11__10:A I *L 0.001776 *C 12.880 36.720 +*I mux_left_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 21.720 52.700 +*N chanx_right_in[14]:4 *C 21.620 52.700 +*N chanx_right_in[14]:5 *C 21.620 52.655 +*N chanx_right_in[14]:6 *C 12.918 36.720 +*N chanx_right_in[14]:7 *C 13.295 36.720 +*N chanx_right_in[14]:8 *C 13.340 36.765 +*N chanx_right_in[14]:9 *C 13.340 37.343 +*N chanx_right_in[14]:10 *C 13.348 37.400 +*N chanx_right_in[14]:11 *C 21.613 37.400 +*N chanx_right_in[14]:12 *C 21.620 37.458 +*N chanx_right_in[14]:13 *C 21.620 46.920 +*N chanx_right_in[14]:14 *C 21.628 46.920 +*N chanx_right_in[14]:15 *C 65.312 46.920 +*N chanx_right_in[14]:16 *C 65.320 46.863 +*N chanx_right_in[14]:17 *C 66.032 44.540 +*N chanx_right_in[14]:18 *C 65.365 44.540 +*N chanx_right_in[14]:19 *C 65.320 44.540 +*N chanx_right_in[14]:20 *C 65.320 17.738 +*N chanx_right_in[14]:21 *C 65.328 17.680 +*N chanx_right_in[14]:22 *C 115.155 17.680 + +*CAP +0 chanx_right_in[14] 0.0007581856 +1 mux_top_track_18\/mux_l1_in_0_:A0 1e-06 +2 FTB_11__10:A 1e-06 +3 mux_left_track_5\/mux_l1_in_2_:A1 1e-06 +4 chanx_right_in[14]:4 3.543633e-05 +5 chanx_right_in[14]:5 0.0003352228 +6 chanx_right_in[14]:6 6.150656e-05 +7 chanx_right_in[14]:7 6.150656e-05 +8 chanx_right_in[14]:8 5.085892e-05 +9 chanx_right_in[14]:9 5.085892e-05 +10 chanx_right_in[14]:10 0.0006289766 +11 chanx_right_in[14]:11 0.0006289766 +12 chanx_right_in[14]:12 0.0004630087 +13 chanx_right_in[14]:13 0.0008388899 +14 chanx_right_in[14]:14 0.001126331 +15 chanx_right_in[14]:15 0.001126331 +16 chanx_right_in[14]:16 0.0001569967 +17 chanx_right_in[14]:17 7.983025e-05 +18 chanx_right_in[14]:18 7.983025e-05 +19 chanx_right_in[14]:19 0.001316857 +20 chanx_right_in[14]:20 0.00112807 +21 chanx_right_in[14]:21 0.001853555 +22 chanx_right_in[14]:22 0.002611741 +23 chanx_right_in[14] chanx_right_in[8] 0.0003217938 +24 chanx_right_in[14]:21 chanx_right_in[8]:23 0.0002234731 +25 chanx_right_in[14]:22 chanx_right_in[8] 0.0002234731 +26 chanx_right_in[14]:22 chanx_right_in[8]:23 0.0003217938 +27 chanx_right_in[14] chanx_right_in[12] 2.397464e-05 +28 chanx_right_in[14] chanx_right_in[12]:29 0.000134359 +29 chanx_right_in[14]:21 chanx_right_in[12]:27 0.000218928 +30 chanx_right_in[14]:21 chanx_right_in[12]:28 4.180806e-05 +31 chanx_right_in[14]:22 chanx_right_in[12]:28 0.000353287 +32 chanx_right_in[14]:22 chanx_right_in[12]:29 4.180806e-05 +33 chanx_right_in[14]:22 chanx_right_in[12]:32 2.397464e-05 +34 chanx_right_in[14]:11 chanx_right_in[16]:15 2.875502e-05 +35 chanx_right_in[14]:10 chanx_right_in[16]:10 2.875502e-05 +36 chanx_right_in[14]:19 chanx_right_in[16]:22 0.0002901742 +37 chanx_right_in[14]:19 chanx_right_in[16]:6 1.132727e-05 +38 chanx_right_in[14]:20 chanx_right_in[16]:22 1.132727e-05 +39 chanx_right_in[14]:20 chanx_right_in[16]:23 0.0002901742 +40 chanx_right_in[14]:14 chanx_left_in[5]:29 0.0007147481 +41 chanx_right_in[14]:14 chanx_left_in[5]:28 0.0002432275 +42 chanx_right_in[14]:15 chanx_left_in[5]:27 0.0002432275 +43 chanx_right_in[14]:15 chanx_left_in[5]:28 0.0007147481 +44 chanx_right_in[14]:14 chanx_left_in[6] 0.001661054 +45 chanx_right_in[14]:14 chanx_left_in[6]:20 0.000770913 +46 chanx_right_in[14]:15 chanx_left_in[6]:19 0.000770913 +47 chanx_right_in[14]:15 chanx_left_in[6]:20 0.001661054 +48 chanx_right_in[14] chanx_right_in[1]:15 5.618421e-05 +49 chanx_right_in[14] chanx_right_in[1]:14 1.281201e-05 +50 chanx_right_in[14]:21 chanx_right_in[1]:10 0.0002484336 +51 chanx_right_in[14]:21 chanx_right_in[1]:13 0.0001208696 +52 chanx_right_in[14]:22 chanx_right_in[1]:11 0.0002484336 +53 chanx_right_in[14]:22 chanx_right_in[1]:13 1.281201e-05 +54 chanx_right_in[14]:22 chanx_right_in[1]:14 0.0001770538 +55 chanx_right_in[14]:19 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 9.257792e-05 +56 chanx_right_in[14]:20 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 9.257792e-05 +57 chanx_right_in[14]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.478877e-05 +58 chanx_right_in[14]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.333349e-05 +59 chanx_right_in[14]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.333349e-05 +60 chanx_right_in[14]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.478877e-05 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:22 0.003962883 +1 chanx_right_in[14]:12 chanx_right_in[14]:11 0.00341 +2 chanx_right_in[14]:11 chanx_right_in[14]:10 0.00129485 +3 chanx_right_in[14]:9 chanx_right_in[14]:8 0.0005156251 +4 chanx_right_in[14]:10 chanx_right_in[14]:9 0.00341 +5 chanx_right_in[14]:7 chanx_right_in[14]:6 0.0003370536 +6 chanx_right_in[14]:8 chanx_right_in[14]:7 0.0045 +7 chanx_right_in[14]:6 FTB_11__10:A 0.152 +8 chanx_right_in[14]:18 chanx_right_in[14]:17 0.0005959822 +9 chanx_right_in[14]:19 chanx_right_in[14]:18 0.0045 +10 chanx_right_in[14]:19 chanx_right_in[14]:16 0.002073661 +11 chanx_right_in[14]:17 mux_top_track_18\/mux_l1_in_0_:A0 0.152 +12 chanx_right_in[14]:4 mux_left_track_5\/mux_l1_in_2_:A1 0.152 +13 chanx_right_in[14]:5 chanx_right_in[14]:4 0.0045 +14 chanx_right_in[14]:13 chanx_right_in[14]:12 0.00844866 +15 chanx_right_in[14]:13 chanx_right_in[14]:5 0.005120536 +16 chanx_right_in[14]:14 chanx_right_in[14]:13 0.00341 +17 chanx_right_in[14]:16 chanx_right_in[14]:15 0.00341 +18 chanx_right_in[14]:15 chanx_right_in[14]:14 0.006843983 +19 chanx_right_in[14]:20 chanx_right_in[14]:19 0.02393081 +20 chanx_right_in[14]:21 chanx_right_in[14]:20 0.00341 +21 chanx_right_in[14]:22 chanx_right_in[14]:21 0.007806308 + +*END + +*D_NET chanx_left_in[7] 0.008911856 //LENGTH 63.680 LUMPCC 0.002546786 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.305 70.720 +*I mux_top_track_34\/mux_l1_in_0_:A0 I *L 0.001631 *C 42.495 91.460 +*N chanx_left_in[7]:2 *C 42.458 91.460 +*N chanx_left_in[7]:3 *C 40.525 91.460 +*N chanx_left_in[7]:4 *C 40.480 91.415 +*N chanx_left_in[7]:5 *C 40.480 87.098 +*N chanx_left_in[7]:6 *C 40.473 87.040 +*N chanx_left_in[7]:7 *C 38.660 87.040 +*N chanx_left_in[7]:8 *C 38.640 87.032 +*N chanx_left_in[7]:9 *C 38.640 71.407 +*N chanx_left_in[7]:10 *C 38.620 71.400 +*N chanx_left_in[7]:11 *C 1.380 71.400 + +*CAP +0 chanx_left_in[7] 5.162711e-05 +1 mux_top_track_34\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[7]:2 0.0001441847 +3 chanx_left_in[7]:3 0.0001441847 +4 chanx_left_in[7]:4 0.0002438753 +5 chanx_left_in[7]:5 0.0002438753 +6 chanx_left_in[7]:6 0.0001041492 +7 chanx_left_in[7]:7 0.0001041492 +8 chanx_left_in[7]:8 0.0008404675 +9 chanx_left_in[7]:9 0.0008404675 +10 chanx_left_in[7]:10 0.001797732 +11 chanx_left_in[7]:11 0.001849359 +12 chanx_left_in[7]:6 prog_clk[0]:582 5.155337e-05 +13 chanx_left_in[7]:7 prog_clk[0]:586 5.155337e-05 +14 chanx_left_in[7]:10 prog_clk[0]:551 0.0006339962 +15 chanx_left_in[7]:10 prog_clk[0]:552 0.0002084124 +16 chanx_left_in[7]:11 prog_clk[0]:546 0.0006339962 +17 chanx_left_in[7]:11 prog_clk[0]:551 0.0002084124 +18 chanx_left_in[7]:8 left_top_grid_pin_44_[0]:21 4.83293e-05 +19 chanx_left_in[7]:10 left_top_grid_pin_44_[0]:22 0.0003311016 +20 chanx_left_in[7]:9 left_top_grid_pin_44_[0]:20 4.83293e-05 +21 chanx_left_in[7]:11 left_top_grid_pin_44_[0]:23 0.0003311016 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:11 0.0001065333 +1 chanx_left_in[7]:2 mux_top_track_34\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[7]:3 chanx_left_in[7]:2 0.001725447 +3 chanx_left_in[7]:4 chanx_left_in[7]:3 0.0045 +4 chanx_left_in[7]:5 chanx_left_in[7]:4 0.003854911 +5 chanx_left_in[7]:6 chanx_left_in[7]:5 0.00341 +6 chanx_left_in[7]:7 chanx_left_in[7]:6 0.0002839583 +7 chanx_left_in[7]:8 chanx_left_in[7]:7 0.00341 +8 chanx_left_in[7]:10 chanx_left_in[7]:9 0.00341 +9 chanx_left_in[7]:9 chanx_left_in[7]:8 0.002447917 +10 chanx_left_in[7]:11 chanx_left_in[7]:10 0.005834267 + +*END + +*D_NET ccff_head[0] 0.00637509 //LENGTH 52.520 LUMPCC 0.0007920503 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 138.460 1.290 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 113.335 28.220 +*N ccff_head[0]:2 *C 113.373 28.220 +*N ccff_head[0]:3 *C 138.415 28.220 +*N ccff_head[0]:4 *C 138.460 28.175 + +*CAP +0 ccff_head[0] 0.001338565 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 0.001452455 +3 ccff_head[0]:3 0.001452455 +4 ccff_head[0]:4 0.001338565 +5 ccff_head[0]:2 chanx_left_in[13]:11 0.0002747511 +6 ccff_head[0]:3 chanx_left_in[13]:10 0.0002747511 +7 ccff_head[0] ropt_net_168:5 8.164756e-05 +8 ccff_head[0]:4 ropt_net_168:4 8.164756e-05 +9 ccff_head[0]:2 ropt_net_135:3 3.962651e-05 +10 ccff_head[0]:3 ropt_net_135:2 3.962651e-05 + +*RES +0 ccff_head[0] ccff_head[0]:4 0.02400447 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.02235938 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 + +*END + +*D_NET chany_top_out[9] 0.001044016 //LENGTH 8.200 LUMPCC 0 DR + +*CONN +*I mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 62.100 98.940 +*P chany_top_out[9] O *L 0.7423 *C 58.420 102.035 +*N chany_top_out[9]:2 *C 58.420 98.645 +*N chany_top_out[9]:3 *C 58.465 98.600 +*N chany_top_out[9]:4 *C 61.640 98.600 +*N chany_top_out[9]:5 *C 61.640 98.940 +*N chany_top_out[9]:6 *C 62.062 98.940 + +*CAP +0 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[9] 0.0002098563 +2 chany_top_out[9]:2 0.0002098563 +3 chany_top_out[9]:3 0.000231682 +4 chany_top_out[9]:4 0.0002590501 +5 chany_top_out[9]:5 7.996983e-05 +6 chany_top_out[9]:6 5.260169e-05 + +*RES +0 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[9]:6 0.152 +1 chany_top_out[9]:3 chany_top_out[9]:2 0.0045 +2 chany_top_out[9]:2 chany_top_out[9] 0.003026786 +3 chany_top_out[9]:6 chany_top_out[9]:5 0.0003772322 +4 chany_top_out[9]:4 chany_top_out[9]:3 0.002834822 +5 chany_top_out[9]:5 chany_top_out[9]:4 0.0003035715 + +*END + +*D_NET chanx_right_out[0] 0.001736208 //LENGTH 13.765 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 138.060 69.360 +*P chanx_right_out[0] O *L 0.7423 *C 140.450 59.840 +*N chanx_right_out[0]:2 *C 137.548 59.840 +*N chanx_right_out[0]:3 *C 137.540 59.898 +*N chanx_right_out[0]:4 *C 137.540 69.315 +*N chanx_right_out[0]:5 *C 137.585 69.360 +*N chanx_right_out[0]:6 *C 138.023 69.360 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 0.0002227378 +2 chanx_right_out[0]:2 0.0002227378 +3 chanx_right_out[0]:3 0.0005917051 +4 chanx_right_out[0]:4 0.0005917051 +5 chanx_right_out[0]:5 5.316125e-05 +6 chanx_right_out[0]:6 5.316125e-05 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:6 0.152 +1 chanx_right_out[0]:6 chanx_right_out[0]:5 0.000390625 +2 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +3 chanx_right_out[0]:4 chanx_right_out[0]:3 0.008408482 +4 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +5 chanx_right_out[0]:2 chanx_right_out[0] 0.0004547249 + +*END + +*D_NET chanx_left_out[16] 0.000956316 //LENGTH 8.650 LUMPCC 0 DR + +*CONN +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 36.720 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 31.280 +*N chanx_left_out[16]:2 *C 3.213 31.280 +*N chanx_left_out[16]:3 *C 3.220 31.338 +*N chanx_left_out[16]:4 *C 3.220 36.675 +*N chanx_left_out[16]:5 *C 3.243 36.720 +*N chanx_left_out[16]:6 *C 3.610 36.720 + +*CAP +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[16] 0.0001451167 +2 chanx_left_out[16]:2 0.0001451167 +3 chanx_left_out[16]:3 0.0002808452 +4 chanx_left_out[16]:4 0.0002808452 +5 chanx_left_out[16]:5 5.169608e-05 +6 chanx_left_out[16]:6 5.169608e-05 + +*RES +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:6 chanx_left_out[16]:5 0.0001997283 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.004765625 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 0.0003105917 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[1] 0.00567961 //LENGTH 41.275 LUMPCC 0.0003212428 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 101.895 68.680 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 103.400 61.495 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 98.160 58.820 +*I mux_right_track_4\/mux_l2_in_3_:S I *L 0.00357 *C 110.040 56.440 +*I mux_right_track_4\/mux_l2_in_2_:S I *L 0.00357 *C 110.040 63.630 +*I mux_right_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 108.660 68.680 +*N mux_tree_tapbuf_size14_0_sram[1]:6 *C 110.040 63.630 +*N mux_tree_tapbuf_size14_0_sram[1]:7 *C 109.953 63.920 +*N mux_tree_tapbuf_size14_0_sram[1]:8 *C 110.055 56.440 +*N mux_tree_tapbuf_size14_0_sram[1]:9 *C 110.378 56.440 +*N mux_tree_tapbuf_size14_0_sram[1]:10 *C 110.400 56.485 +*N mux_tree_tapbuf_size14_0_sram[1]:11 *C 110.400 63.920 +*N mux_tree_tapbuf_size14_0_sram[1]:12 *C 109.940 63.920 +*N mux_tree_tapbuf_size14_0_sram[1]:13 *C 109.998 63.890 +*N mux_tree_tapbuf_size14_0_sram[1]:14 *C 98.198 58.820 +*N mux_tree_tapbuf_size14_0_sram[1]:15 *C 101.200 58.820 +*N mux_tree_tapbuf_size14_0_sram[1]:16 *C 101.200 59.160 +*N mux_tree_tapbuf_size14_0_sram[1]:17 *C 103.455 59.160 +*N mux_tree_tapbuf_size14_0_sram[1]:18 *C 103.500 59.205 +*N mux_tree_tapbuf_size14_0_sram[1]:19 *C 103.400 61.495 +*N mux_tree_tapbuf_size14_0_sram[1]:20 *C 103.500 61.880 +*N mux_tree_tapbuf_size14_0_sram[1]:21 *C 103.500 61.880 +*N mux_tree_tapbuf_size14_0_sram[1]:22 *C 103.500 63.875 +*N mux_tree_tapbuf_size14_0_sram[1]:23 *C 103.545 63.920 +*N mux_tree_tapbuf_size14_0_sram[1]:24 *C 108.560 63.920 +*N mux_tree_tapbuf_size14_0_sram[1]:25 *C 108.560 63.965 +*N mux_tree_tapbuf_size14_0_sram[1]:26 *C 108.560 68.635 +*N mux_tree_tapbuf_size14_0_sram[1]:27 *C 108.560 68.680 +*N mux_tree_tapbuf_size14_0_sram[1]:28 *C 108.560 69.020 +*N mux_tree_tapbuf_size14_0_sram[1]:29 *C 107.180 69.020 +*N mux_tree_tapbuf_size14_0_sram[1]:30 *C 107.180 68.680 +*N mux_tree_tapbuf_size14_0_sram[1]:31 *C 101.933 68.680 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_4\/mux_l2_in_3_:S 1e-06 +4 mux_right_track_4\/mux_l2_in_2_:S 1e-06 +5 mux_right_track_4\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size14_0_sram[1]:6 5.400803e-05 +7 mux_tree_tapbuf_size14_0_sram[1]:7 2.25256e-05 +8 mux_tree_tapbuf_size14_0_sram[1]:8 5.125611e-05 +9 mux_tree_tapbuf_size14_0_sram[1]:9 5.125611e-05 +10 mux_tree_tapbuf_size14_0_sram[1]:10 0.0004297855 +11 mux_tree_tapbuf_size14_0_sram[1]:11 0.0004647908 +12 mux_tree_tapbuf_size14_0_sram[1]:12 6.83306e-05 +13 mux_tree_tapbuf_size14_0_sram[1]:13 0.000137221 +14 mux_tree_tapbuf_size14_0_sram[1]:14 0.000210661 +15 mux_tree_tapbuf_size14_0_sram[1]:15 0.000235283 +16 mux_tree_tapbuf_size14_0_sram[1]:16 0.0002275953 +17 mux_tree_tapbuf_size14_0_sram[1]:17 0.0002029732 +18 mux_tree_tapbuf_size14_0_sram[1]:18 0.0001849989 +19 mux_tree_tapbuf_size14_0_sram[1]:19 6.528623e-05 +20 mux_tree_tapbuf_size14_0_sram[1]:20 7.028248e-05 +21 mux_tree_tapbuf_size14_0_sram[1]:21 0.0003700418 +22 mux_tree_tapbuf_size14_0_sram[1]:22 0.0001511084 +23 mux_tree_tapbuf_size14_0_sram[1]:23 0.0003276099 +24 mux_tree_tapbuf_size14_0_sram[1]:24 0.0004550371 +25 mux_tree_tapbuf_size14_0_sram[1]:25 0.0002695853 +26 mux_tree_tapbuf_size14_0_sram[1]:26 0.0002695853 +27 mux_tree_tapbuf_size14_0_sram[1]:27 6.296799e-05 +28 mux_tree_tapbuf_size14_0_sram[1]:28 9.023637e-05 +29 mux_tree_tapbuf_size14_0_sram[1]:29 9.666702e-05 +30 mux_tree_tapbuf_size14_0_sram[1]:30 0.000408745 +31 mux_tree_tapbuf_size14_0_sram[1]:31 0.0003745294 +32 mux_tree_tapbuf_size14_0_sram[1]:10 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 5.000287e-05 +33 mux_tree_tapbuf_size14_0_sram[1]:11 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 5.000287e-05 +34 mux_tree_tapbuf_size14_0_sram[1]:27 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.149877e-06 +35 mux_tree_tapbuf_size14_0_sram[1]:30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.175581e-08 +36 mux_tree_tapbuf_size14_0_sram[1]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.801886e-05 +37 mux_tree_tapbuf_size14_0_sram[1]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.175581e-08 +38 mux_tree_tapbuf_size14_0_sram[1]:28 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.016874e-05 +39 mux_tree_tapbuf_size14_0_sram[1]:26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.666356e-05 +40 mux_tree_tapbuf_size14_0_sram[1]:25 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.666356e-05 +41 mux_tree_tapbuf_size14_0_sram[1]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.218818e-07 +42 mux_tree_tapbuf_size14_0_sram[1]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 1.354258e-05 +43 mux_tree_tapbuf_size14_0_sram[1]:28 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.354258e-05 +44 mux_tree_tapbuf_size14_0_sram[1]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.218818e-07 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size14_0_sram[1]:31 0.152 +1 mux_tree_tapbuf_size14_0_sram[1]:14 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size14_0_sram[1]:17 mux_tree_tapbuf_size14_0_sram[1]:16 0.002013393 +3 mux_tree_tapbuf_size14_0_sram[1]:18 mux_tree_tapbuf_size14_0_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size14_0_sram[1]:20 mux_tree_tapbuf_size14_0_sram[1]:19 0.00034375 +5 mux_tree_tapbuf_size14_0_sram[1]:21 mux_tree_tapbuf_size14_0_sram[1]:20 0.0045 +6 mux_tree_tapbuf_size14_0_sram[1]:21 mux_tree_tapbuf_size14_0_sram[1]:18 0.002388393 +7 mux_tree_tapbuf_size14_0_sram[1]:19 mux_right_track_4\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size14_0_sram[1]:27 mux_tree_tapbuf_size14_0_sram[1]:26 0.0045 +9 mux_tree_tapbuf_size14_0_sram[1]:27 mux_right_track_4\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size14_0_sram[1]:26 mux_tree_tapbuf_size14_0_sram[1]:25 0.004169643 +11 mux_tree_tapbuf_size14_0_sram[1]:24 mux_tree_tapbuf_size14_0_sram[1]:23 0.004477679 +12 mux_tree_tapbuf_size14_0_sram[1]:24 mux_tree_tapbuf_size14_0_sram[1]:13 0.001283482 +13 mux_tree_tapbuf_size14_0_sram[1]:25 mux_tree_tapbuf_size14_0_sram[1]:24 0.0045 +14 mux_tree_tapbuf_size14_0_sram[1]:23 mux_tree_tapbuf_size14_0_sram[1]:22 0.0045 +15 mux_tree_tapbuf_size14_0_sram[1]:22 mux_tree_tapbuf_size14_0_sram[1]:21 0.00178125 +16 mux_tree_tapbuf_size14_0_sram[1]:31 mux_tree_tapbuf_size14_0_sram[1]:30 0.004685268 +17 mux_tree_tapbuf_size14_0_sram[1]:6 mux_right_track_4\/mux_l2_in_2_:S 0.152 +18 mux_tree_tapbuf_size14_0_sram[1]:13 mux_tree_tapbuf_size14_0_sram[1]:12 0.0045 +19 mux_tree_tapbuf_size14_0_sram[1]:13 mux_tree_tapbuf_size14_0_sram[1]:7 4.017857e-05 +20 mux_tree_tapbuf_size14_0_sram[1]:13 mux_tree_tapbuf_size14_0_sram[1]:6 0.0001511628 +21 mux_tree_tapbuf_size14_0_sram[1]:12 mux_tree_tapbuf_size14_0_sram[1]:11 0.0004107143 +22 mux_tree_tapbuf_size14_0_sram[1]:9 mux_tree_tapbuf_size14_0_sram[1]:8 0.0001752718 +23 mux_tree_tapbuf_size14_0_sram[1]:10 mux_tree_tapbuf_size14_0_sram[1]:9 0.0045 +24 mux_tree_tapbuf_size14_0_sram[1]:8 mux_right_track_4\/mux_l2_in_3_:S 0.152 +25 mux_tree_tapbuf_size14_0_sram[1]:15 mux_tree_tapbuf_size14_0_sram[1]:14 0.002680804 +26 mux_tree_tapbuf_size14_0_sram[1]:16 mux_tree_tapbuf_size14_0_sram[1]:15 0.0003035715 +27 mux_tree_tapbuf_size14_0_sram[1]:30 mux_tree_tapbuf_size14_0_sram[1]:29 0.0003035715 +28 mux_tree_tapbuf_size14_0_sram[1]:29 mux_tree_tapbuf_size14_0_sram[1]:28 0.001232143 +29 mux_tree_tapbuf_size14_0_sram[1]:28 mux_tree_tapbuf_size14_0_sram[1]:27 0.0003035715 +30 mux_tree_tapbuf_size14_0_sram[1]:11 mux_tree_tapbuf_size14_0_sram[1]:10 0.006638392 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[0] 0.002669357 //LENGTH 18.270 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 55.045 53.040 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 51.235 49.980 +*I mux_top_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 56.020 56.055 +*I mux_top_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 60.620 56.440 +*N mux_tree_tapbuf_size3_2_sram[0]:4 *C 60.583 56.440 +*N mux_tree_tapbuf_size3_2_sram[0]:5 *C 56.020 56.055 +*N mux_tree_tapbuf_size3_2_sram[0]:6 *C 56.020 56.395 +*N mux_tree_tapbuf_size3_2_sram[0]:7 *C 55.690 56.410 +*N mux_tree_tapbuf_size3_2_sram[0]:8 *C 55.660 56.395 +*N mux_tree_tapbuf_size3_2_sram[0]:9 *C 55.660 53.040 +*N mux_tree_tapbuf_size3_2_sram[0]:10 *C 51.235 49.980 +*N mux_tree_tapbuf_size3_2_sram[0]:11 *C 51.520 49.980 +*N mux_tree_tapbuf_size3_2_sram[0]:12 *C 51.520 50.025 +*N mux_tree_tapbuf_size3_2_sram[0]:13 *C 51.520 52.983 +*N mux_tree_tapbuf_size3_2_sram[0]:14 *C 51.528 53.040 +*N mux_tree_tapbuf_size3_2_sram[0]:15 *C 54.733 53.040 +*N mux_tree_tapbuf_size3_2_sram[0]:16 *C 54.740 53.040 +*N mux_tree_tapbuf_size3_2_sram[0]:17 *C 54.740 53.040 +*N mux_tree_tapbuf_size3_2_sram[0]:18 *C 55.045 53.040 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:S 1e-06 +3 mux_top_track_16\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_2_sram[0]:4 0.0003405512 +5 mux_tree_tapbuf_size3_2_sram[0]:5 6.413672e-05 +6 mux_tree_tapbuf_size3_2_sram[0]:6 0.0004179553 +7 mux_tree_tapbuf_size3_2_sram[0]:7 4.474505e-05 +8 mux_tree_tapbuf_size3_2_sram[0]:8 0.0002176228 +9 mux_tree_tapbuf_size3_2_sram[0]:9 0.0002693589 +10 mux_tree_tapbuf_size3_2_sram[0]:10 5.033623e-05 +11 mux_tree_tapbuf_size3_2_sram[0]:11 5.480361e-05 +12 mux_tree_tapbuf_size3_2_sram[0]:12 0.0001814363 +13 mux_tree_tapbuf_size3_2_sram[0]:13 0.0001814363 +14 mux_tree_tapbuf_size3_2_sram[0]:14 0.0003325463 +15 mux_tree_tapbuf_size3_2_sram[0]:15 0.0003325463 +16 mux_tree_tapbuf_size3_2_sram[0]:16 8.319579e-05 +17 mux_tree_tapbuf_size3_2_sram[0]:17 4.947108e-05 +18 mux_tree_tapbuf_size3_2_sram[0]:18 4.521542e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_2_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_2_sram[0]:4 mux_top_track_16\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_2_sram[0]:7 mux_tree_tapbuf_size3_2_sram[0]:6 0.00020625 +3 mux_tree_tapbuf_size3_2_sram[0]:8 mux_tree_tapbuf_size3_2_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size3_2_sram[0]:17 mux_tree_tapbuf_size3_2_sram[0]:16 0.0045 +5 mux_tree_tapbuf_size3_2_sram[0]:16 mux_tree_tapbuf_size3_2_sram[0]:15 0.00341 +6 mux_tree_tapbuf_size3_2_sram[0]:16 mux_tree_tapbuf_size3_2_sram[0]:9 0.0008214285 +7 mux_tree_tapbuf_size3_2_sram[0]:18 mux_tree_tapbuf_size3_2_sram[0]:17 0.0001657609 +8 mux_tree_tapbuf_size3_2_sram[0]:15 mux_tree_tapbuf_size3_2_sram[0]:14 0.0005021166 +9 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:12 0.002640625 +10 mux_tree_tapbuf_size3_2_sram[0]:14 mux_tree_tapbuf_size3_2_sram[0]:13 0.00341 +11 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:10 0.0001548913 +12 mux_tree_tapbuf_size3_2_sram[0]:12 mux_tree_tapbuf_size3_2_sram[0]:11 0.0045 +13 mux_tree_tapbuf_size3_2_sram[0]:10 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size3_2_sram[0]:5 mux_top_track_16\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size3_2_sram[0]:6 mux_tree_tapbuf_size3_2_sram[0]:5 0.0003035715 +16 mux_tree_tapbuf_size3_2_sram[0]:6 mux_tree_tapbuf_size3_2_sram[0]:4 0.004073661 +17 mux_tree_tapbuf_size3_2_sram[0]:9 mux_tree_tapbuf_size3_2_sram[0]:8 0.002995536 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_4_ccff_tail[0] 0.001255131 //LENGTH 9.400 LUMPCC 0.0004008978 DR + +*CONN +*I mem_top_track_20\/FTB_18__44:X O *L 0 *C 75.215 31.280 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 75.155 22.780 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 *C 75.155 22.780 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 *C 74.980 22.780 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 *C 74.980 22.825 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 *C 74.980 31.235 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 *C 74.980 31.280 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 *C 75.215 31.280 + +*CAP +0 mem_top_track_20\/FTB_18__44:X 1e-06 +1 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 5.138112e-05 +3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 5.368383e-05 +4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 0.0003102086 +5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 0.0003102086 +6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 6.360384e-05 +7 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 6.314756e-05 +8 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 chanx_right_in[4]:24 6.522876e-05 +9 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 chanx_right_in[4]:23 6.522876e-05 +10 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 chanx_left_in[18]:24 5.535899e-05 +11 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 chanx_left_in[18]:23 5.535899e-05 +12 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size3_6_sram[0]:10 7.986114e-05 +13 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size3_6_sram[0]:11 7.986114e-05 + +*RES +0 mem_top_track_20\/FTB_18__44:X mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 0.007508929 +6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.003196645 //LENGTH 25.950 LUMPCC 7.47016e-05 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 87.705 77.520 +*I mux_right_track_32\/mux_l3_in_0_:S I *L 0.00357 *C 86.840 68.680 +*I mem_right_track_32\/FTB_31__57:A I *L 0.001746 *C 78.660 80.240 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 78.660 80.240 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 78.660 80.285 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 78.660 82.235 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 78.705 82.280 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 86.895 82.280 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 86.940 82.235 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 86.840 68.680 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 86.940 68.725 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 86.940 77.520 +*N mux_tree_tapbuf_size6_0_sram[2]:12 *C 86.985 77.520 +*N mux_tree_tapbuf_size6_0_sram[2]:13 *C 87.668 77.520 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_32\/FTB_31__57:A 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 3.350813e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 0.0001230175 +5 mux_tree_tapbuf_size6_0_sram[2]:5 0.0001230175 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0005784925 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0005784925 +8 mux_tree_tapbuf_size6_0_sram[2]:8 0.0002713286 +9 mux_tree_tapbuf_size6_0_sram[2]:9 2.916407e-05 +10 mux_tree_tapbuf_size6_0_sram[2]:10 0.0004740054 +11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0007757912 +12 mux_tree_tapbuf_size6_0_sram[2]:12 6.606282e-05 +13 mux_tree_tapbuf_size6_0_sram[2]:13 6.606282e-05 +14 mux_tree_tapbuf_size6_0_sram[2]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.73508e-05 +15 mux_tree_tapbuf_size6_0_sram[2]:11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.73508e-05 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:9 mux_right_track_32\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.0045 +3 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.0073125 +4 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size6_0_sram[2]:6 mux_tree_tapbuf_size6_0_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.001741071 +7 mux_tree_tapbuf_size6_0_sram[2]:3 mem_right_track_32\/FTB_31__57:A 0.152 +8 mux_tree_tapbuf_size6_0_sram[2]:4 mux_tree_tapbuf_size6_0_sram[2]:3 0.0045 +9 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.007852679 +11 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:8 0.004209822 +12 mux_tree_tapbuf_size6_0_sram[2]:13 mux_tree_tapbuf_size6_0_sram[2]:12 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[0] 0.007584497 //LENGTH 57.705 LUMPCC 0.001033814 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.525 80.580 +*I mux_top_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 67.500 52.360 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 67.980 50.320 +*I mux_top_track_4\/mux_l1_in_3_:S I *L 0.00357 *C 72.580 44.880 +*I mux_top_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 76.920 50.320 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.955 55.420 +*N mux_tree_tapbuf_size7_1_sram[0]:6 *C 65.993 55.420 +*N mux_tree_tapbuf_size7_1_sram[0]:7 *C 76.920 50.320 +*N mux_tree_tapbuf_size7_1_sram[0]:8 *C 76.820 49.980 +*N mux_tree_tapbuf_size7_1_sram[0]:9 *C 72.543 44.880 +*N mux_tree_tapbuf_size7_1_sram[0]:10 *C 70.425 44.880 +*N mux_tree_tapbuf_size7_1_sram[0]:11 *C 70.380 44.925 +*N mux_tree_tapbuf_size7_1_sram[0]:12 *C 70.380 49.935 +*N mux_tree_tapbuf_size7_1_sram[0]:13 *C 70.380 49.980 +*N mux_tree_tapbuf_size7_1_sram[0]:14 *C 70.380 50.320 +*N mux_tree_tapbuf_size7_1_sram[0]:15 *C 68.017 50.320 +*N mux_tree_tapbuf_size7_1_sram[0]:16 *C 67.642 50.320 +*N mux_tree_tapbuf_size7_1_sram[0]:17 *C 67.620 50.365 +*N mux_tree_tapbuf_size7_1_sram[0]:18 *C 67.500 52.360 +*N mux_tree_tapbuf_size7_1_sram[0]:19 *C 67.620 52.315 +*N mux_tree_tapbuf_size7_1_sram[0]:20 *C 67.160 52.360 +*N mux_tree_tapbuf_size7_1_sram[0]:21 *C 67.160 55.375 +*N mux_tree_tapbuf_size7_1_sram[0]:22 *C 67.160 55.420 +*N mux_tree_tapbuf_size7_1_sram[0]:23 *C 69.875 55.420 +*N mux_tree_tapbuf_size7_1_sram[0]:24 *C 69.920 55.465 +*N mux_tree_tapbuf_size7_1_sram[0]:25 *C 69.920 80.535 +*N mux_tree_tapbuf_size7_1_sram[0]:26 *C 69.965 80.580 +*N mux_tree_tapbuf_size7_1_sram[0]:27 *C 72.487 80.580 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_4\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +3 mux_top_track_4\/mux_l1_in_3_:S 1e-06 +4 mux_top_track_4\/mux_l1_in_2_:S 1e-06 +5 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_1_sram[0]:6 0.0001054568 +7 mux_tree_tapbuf_size7_1_sram[0]:7 5.825426e-05 +8 mux_tree_tapbuf_size7_1_sram[0]:8 0.0004893395 +9 mux_tree_tapbuf_size7_1_sram[0]:9 0.0001716695 +10 mux_tree_tapbuf_size7_1_sram[0]:10 0.0001716695 +11 mux_tree_tapbuf_size7_1_sram[0]:11 0.0003600834 +12 mux_tree_tapbuf_size7_1_sram[0]:12 0.0003600834 +13 mux_tree_tapbuf_size7_1_sram[0]:13 0.0004909949 +14 mux_tree_tapbuf_size7_1_sram[0]:14 0.0002005197 +15 mux_tree_tapbuf_size7_1_sram[0]:15 0.0002197847 +16 mux_tree_tapbuf_size7_1_sram[0]:16 4.974148e-05 +17 mux_tree_tapbuf_size7_1_sram[0]:17 0.0001116982 +18 mux_tree_tapbuf_size7_1_sram[0]:18 2.990098e-05 +19 mux_tree_tapbuf_size7_1_sram[0]:19 0.0001459732 +20 mux_tree_tapbuf_size7_1_sram[0]:20 0.0002641419 +21 mux_tree_tapbuf_size7_1_sram[0]:21 0.0002298669 +22 mux_tree_tapbuf_size7_1_sram[0]:22 0.0004030018 +23 mux_tree_tapbuf_size7_1_sram[0]:23 0.0002616352 +24 mux_tree_tapbuf_size7_1_sram[0]:24 0.0009898577 +25 mux_tree_tapbuf_size7_1_sram[0]:25 0.0009898577 +26 mux_tree_tapbuf_size7_1_sram[0]:26 0.0002205763 +27 mux_tree_tapbuf_size7_1_sram[0]:27 0.0002205763 +28 mux_tree_tapbuf_size7_1_sram[0]:19 chany_top_in[16]:12 1.298603e-05 +29 mux_tree_tapbuf_size7_1_sram[0]:21 chany_top_in[16]:12 2.331875e-06 +30 mux_tree_tapbuf_size7_1_sram[0]:17 chany_top_in[16]:5 1.298603e-05 +31 mux_tree_tapbuf_size7_1_sram[0]:24 chany_top_in[16]:5 2.511905e-05 +32 mux_tree_tapbuf_size7_1_sram[0]:24 chany_top_in[16]:12 0.0002638416 +33 mux_tree_tapbuf_size7_1_sram[0]:25 chany_top_in[16]:12 2.511905e-05 +34 mux_tree_tapbuf_size7_1_sram[0]:25 chany_top_in[16]:13 0.0002638416 +35 mux_tree_tapbuf_size7_1_sram[0]:20 chany_top_in[16]:5 2.331875e-06 +36 mux_tree_tapbuf_size7_1_sram[0]:24 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002126284 +37 mux_tree_tapbuf_size7_1_sram[0]:25 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002126284 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_1_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_1_sram[0]:18 mux_top_track_4\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:18 0.0045 +3 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:17 0.001741072 +4 mux_tree_tapbuf_size7_1_sram[0]:13 mux_tree_tapbuf_size7_1_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size7_1_sram[0]:13 mux_tree_tapbuf_size7_1_sram[0]:8 0.00575 +6 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:11 0.004473215 +7 mux_tree_tapbuf_size7_1_sram[0]:10 mux_tree_tapbuf_size7_1_sram[0]:9 0.001890625 +8 mux_tree_tapbuf_size7_1_sram[0]:11 mux_tree_tapbuf_size7_1_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size7_1_sram[0]:9 mux_top_track_4\/mux_l1_in_3_:S 0.152 +10 mux_tree_tapbuf_size7_1_sram[0]:22 mux_tree_tapbuf_size7_1_sram[0]:21 0.0045 +11 mux_tree_tapbuf_size7_1_sram[0]:22 mux_tree_tapbuf_size7_1_sram[0]:6 0.001042411 +12 mux_tree_tapbuf_size7_1_sram[0]:21 mux_tree_tapbuf_size7_1_sram[0]:20 0.002691964 +13 mux_tree_tapbuf_size7_1_sram[0]:16 mux_tree_tapbuf_size7_1_sram[0]:15 0.0002038044 +14 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size7_1_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size7_1_sram[0]:15 mux_top_track_4\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:14 0.002109375 +17 mux_tree_tapbuf_size7_1_sram[0]:6 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:22 0.002424107 +19 mux_tree_tapbuf_size7_1_sram[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 0.0045 +20 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:25 0.0045 +21 mux_tree_tapbuf_size7_1_sram[0]:25 mux_tree_tapbuf_size7_1_sram[0]:24 0.02238393 +22 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:26 0.002252232 +23 mux_tree_tapbuf_size7_1_sram[0]:7 mux_top_track_4\/mux_l1_in_2_:S 0.152 +24 mux_tree_tapbuf_size7_1_sram[0]:14 mux_tree_tapbuf_size7_1_sram[0]:13 0.0003035715 +25 mux_tree_tapbuf_size7_1_sram[0]:8 mux_tree_tapbuf_size7_1_sram[0]:7 0.0003035715 +26 mux_tree_tapbuf_size7_1_sram[0]:20 mux_tree_tapbuf_size7_1_sram[0]:19 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_5_ccff_tail[0] 0.0009918142 //LENGTH 8.360 LUMPCC 0 DR + +*CONN +*I mem_left_track_17\/FTB_10__36:X O *L 0 *C 41.165 31.280 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 39.275 37.060 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 *C 39.312 37.060 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 *C 40.895 37.060 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 *C 40.940 37.015 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 *C 40.940 31.325 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 *C 40.940 31.280 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 *C 41.165 31.280 + +*CAP +0 mem_left_track_17\/FTB_10__36:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 0.0001182253 +3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 0.0001182253 +4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 0.000328048 +5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 0.000328048 +6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 5.077701e-05 +7 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 4.649061e-05 + +*RES +0 mem_left_track_17\/FTB_10__36:X mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 0.005080357 +4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[2] 0.001943862 //LENGTH 15.900 LUMPCC 0.0001041572 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.765 34.000 +*I mux_left_track_9\/mux_l3_in_1_:S I *L 0.00357 *C 22.180 31.280 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 25.475 26.180 +*I mux_left_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 26.320 34.340 +*N mux_tree_tapbuf_size8_3_sram[2]:4 *C 26.283 34.340 +*N mux_tree_tapbuf_size8_3_sram[2]:5 *C 24.840 34.340 +*N mux_tree_tapbuf_size8_3_sram[2]:6 *C 25.475 26.180 +*N mux_tree_tapbuf_size8_3_sram[2]:7 *C 25.300 26.180 +*N mux_tree_tapbuf_size8_3_sram[2]:8 *C 25.300 26.225 +*N mux_tree_tapbuf_size8_3_sram[2]:9 *C 25.300 31.280 +*N mux_tree_tapbuf_size8_3_sram[2]:10 *C 22.218 31.280 +*N mux_tree_tapbuf_size8_3_sram[2]:11 *C 24.795 31.280 +*N mux_tree_tapbuf_size8_3_sram[2]:12 *C 24.840 31.280 +*N mux_tree_tapbuf_size8_3_sram[2]:13 *C 24.840 33.955 +*N mux_tree_tapbuf_size8_3_sram[2]:14 *C 24.840 34.030 +*N mux_tree_tapbuf_size8_3_sram[2]:15 *C 23.803 34.000 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_9\/mux_l3_in_1_:S 1e-06 +2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_9\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_3_sram[2]:4 0.0001129948 +5 mux_tree_tapbuf_size8_3_sram[2]:5 0.0001451328 +6 mux_tree_tapbuf_size8_3_sram[2]:6 4.797312e-05 +7 mux_tree_tapbuf_size8_3_sram[2]:7 5.180747e-05 +8 mux_tree_tapbuf_size8_3_sram[2]:8 0.0002852318 +9 mux_tree_tapbuf_size8_3_sram[2]:9 0.0003199539 +10 mux_tree_tapbuf_size8_3_sram[2]:10 0.0001352269 +11 mux_tree_tapbuf_size8_3_sram[2]:11 0.0001352269 +12 mux_tree_tapbuf_size8_3_sram[2]:12 0.0001983404 +13 mux_tree_tapbuf_size8_3_sram[2]:13 0.0001636183 +14 mux_tree_tapbuf_size8_3_sram[2]:14 0.0001361681 +15 mux_tree_tapbuf_size8_3_sram[2]:15 0.0001040301 +16 mux_tree_tapbuf_size8_3_sram[2]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.207859e-05 +17 mux_tree_tapbuf_size8_3_sram[2]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.207859e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_3_sram[2]:15 0.152 +1 mux_tree_tapbuf_size8_3_sram[2]:14 mux_tree_tapbuf_size8_3_sram[2]:13 0.0045 +2 mux_tree_tapbuf_size8_3_sram[2]:14 mux_tree_tapbuf_size8_3_sram[2]:5 0.0002767858 +3 mux_tree_tapbuf_size8_3_sram[2]:13 mux_tree_tapbuf_size8_3_sram[2]:12 0.002388393 +4 mux_tree_tapbuf_size8_3_sram[2]:11 mux_tree_tapbuf_size8_3_sram[2]:10 0.00230134 +5 mux_tree_tapbuf_size8_3_sram[2]:12 mux_tree_tapbuf_size8_3_sram[2]:11 0.0045 +6 mux_tree_tapbuf_size8_3_sram[2]:12 mux_tree_tapbuf_size8_3_sram[2]:9 0.0004107143 +7 mux_tree_tapbuf_size8_3_sram[2]:10 mux_left_track_9\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size8_3_sram[2]:4 mux_left_track_9\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_3_sram[2]:7 mux_tree_tapbuf_size8_3_sram[2]:6 9.51087e-05 +10 mux_tree_tapbuf_size8_3_sram[2]:8 mux_tree_tapbuf_size8_3_sram[2]:7 0.0045 +11 mux_tree_tapbuf_size8_3_sram[2]:6 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +12 mux_tree_tapbuf_size8_3_sram[2]:15 mux_tree_tapbuf_size8_3_sram[2]:14 0.0009263393 +13 mux_tree_tapbuf_size8_3_sram[2]:5 mux_tree_tapbuf_size8_3_sram[2]:4 0.001287946 +14 mux_tree_tapbuf_size8_3_sram[2]:9 mux_tree_tapbuf_size8_3_sram[2]:8 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size9_mem_1_ccff_tail[0] 0.001547693 //LENGTH 12.260 LUMPCC 0.0002263272 DR + +*CONN +*I mem_right_track_2\/FTB_28__54:X O *L 0 *C 110.125 85.000 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 103.215 80.580 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:2 *C 103.253 80.580 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:3 *C 104.835 80.580 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 *C 104.880 80.625 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 *C 104.880 84.955 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 *C 104.925 85.000 +*N mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 *C 110.088 85.000 + +*CAP +0 mem_right_track_2\/FTB_28__54:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:2 0.0001174753 +3 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:3 0.0001174753 +4 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 0.0002142724 +5 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 0.0002142724 +6 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 0.0003279351 +7 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 0.0003279351 +8 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size9_1_sram[3]:7 1.815916e-05 +9 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size9_1_sram[3]:8 1.815916e-05 +10 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size9_1_sram[3]:9 4.340595e-05 +11 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size9_1_sram[3]:5 4.340595e-05 +12 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.159849e-05 +13 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.159849e-05 + +*RES +0 mem_right_track_2\/FTB_28__54:X mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 0.004609375 +2 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 0.003866072 +4 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001705475 //LENGTH 14.735 LUMPCC 0.0003043262 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_0_:X O *L 0 *C 126.325 49.640 +*I mux_right_track_8\/mux_l4_in_0_:A1 I *L 0.00198 *C 127.060 36.380 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 127.023 36.380 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 126.545 36.380 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 126.500 36.425 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 126.500 49.595 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 126.500 49.640 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 126.325 49.640 + +*CAP +0 mux_right_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.411908e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.411908e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0005842136 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0005842136 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.295012e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 4.953364e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_1_sram[3]:10 7.569791e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_1_sram[3]:11 7.569791e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.646518e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.646518e-05 + +*RES +0 mux_right_track_8\/mux_l3_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_8\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004263392 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01175893 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001619093 //LENGTH 12.700 LUMPCC 0.000306403 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_0_:X O *L 0 *C 25.475 33.660 +*I mux_left_track_9\/mux_l4_in_0_:A1 I *L 0.005458 *C 21.160 26.010 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 21.160 26.010 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 21.620 26.010 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 21.620 33.615 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 21.665 33.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 25.438 33.660 + +*CAP +0 mux_left_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.193991e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0004553822 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004234621 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001849529 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001849529 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[8]:20 0.0001532015 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[8]:21 0.0001532015 + +*RES +0 mux_left_track_9\/mux_l3_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.003368304 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.006790179 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_9\/mux_l4_in_0_:A1 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004107143 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005842227 //LENGTH 4.190 LUMPCC 8.283582e-05 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_2_:X O *L 0 *C 88.955 42.500 +*I mux_top_track_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 88.225 45.220 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 88.263 45.220 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 88.735 45.220 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 88.780 45.175 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 88.780 42.545 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 88.780 42.500 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 88.955 42.500 + +*CAP +0 mux_top_track_6\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.947239e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.947239e-05 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001552126 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001552126 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.52183e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.479865e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[6]:16 3.118456e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[6]:13 3.118456e-05 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[6]:12 1.023335e-05 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_left_in[6]:11 1.023335e-05 + +*RES +0 mux_top_track_6\/mux_l1_in_2_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_6\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.000421875 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0] 0.008910626 //LENGTH 52.570 LUMPCC 0.004351942 DR + +*CONN +*I mux_right_track_24\/mux_l3_in_0_:X O *L 0 *C 100.105 66.640 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 129.095 69.525 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 129.095 69.525 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 131.515 69.700 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 131.560 69.655 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 131.560 65.338 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 131.553 65.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 120.540 65.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 120.520 65.273 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 120.520 63.928 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 120.500 63.920 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 96.148 63.920 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 96.140 63.978 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 96.140 66.595 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 96.185 66.640 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 100.068 66.640 + +*CAP +0 mux_right_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002274455 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001896278 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002233688 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002233688 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0003772347 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003772347 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 9.618403e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 9.618403e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001013378 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.001013378 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001547338 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0001547338 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0002049061 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.0002049061 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[2]:7 4.554639e-05 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[2]:6 4.554639e-05 +18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_left_in[2]:13 0.0001444674 +19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_left_in[2]:14 0.0001444674 +20 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_left_in[2]:13 9.238493e-05 +21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_left_in[2]:14 9.238493e-05 +22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_left_in[10]:14 0.0001455387 +23 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_left_in[10]:15 0.0001455387 +24 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_left_in[10]:14 0.001174646 +25 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 chanx_left_in[10]:16 4.730296e-07 +26 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_left_in[10]:15 0.001174646 +27 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 chanx_left_in[10]:17 4.730296e-07 +28 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 right_top_grid_pin_48_[0]:9 0.0004124122 +29 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 right_top_grid_pin_48_[0]:8 0.0004124122 +30 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.861827e-05 +31 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.861827e-05 +32 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.049552e-05 +33 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.138877e-05 +34 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.049552e-05 +35 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.138877e-05 + +*RES +0 mux_right_track_24\/mux_l3_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002160714 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003854911 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001725291 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002107167 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.003815225 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.002337054 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.003466518 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006707906 //LENGTH 4.235 LUMPCC 0.0001152847 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_0_:X O *L 0 *C 61.465 56.100 +*I mux_top_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 59.900 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 59.938 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 61.135 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.180 58.095 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 61.180 56.145 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.180 56.100 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 61.465 56.100 + +*CAP +0 mux_top_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.916913e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.916913e-05 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001329349 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001329349 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.375535e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.554253e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[12]:18 5.764236e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[12]:17 5.764236e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001069196 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741072 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005657244 //LENGTH 3.975 LUMPCC 0.0001009126 DR + +*CONN +*I mux_top_track_38\/mux_l1_in_1_:X O *L 0 *C 80.325 86.020 +*I mux_top_track_38\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.010 86.020 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.973 86.020 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 80.362 86.020 + +*CAP +0 mux_top_track_38\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_38\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002314059 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002314059 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_7_sram[1]:5 5.045628e-05 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_7_sram[1]:4 5.045628e-05 + +*RES +0 mux_top_track_38\/mux_l1_in_1_:X mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_38\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003223215 + +*END + +*D_NET mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002597061 //LENGTH 18.388 LUMPCC 0.0002626428 DR + +*CONN +*I mux_top_track_36\/mux_l1_in_0_:X O *L 0 *C 56.865 93.500 +*I mux_top_track_36\/mux_l2_in_0_:A1 I *L 0.005458 *C 70.108 96.838 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 69.920 96.900 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 69.920 97.240 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.545 97.240 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.500 97.195 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 57.500 93.545 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 57.455 93.500 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 56.903 93.500 + +*CAP +0 mux_top_track_36\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_36\/mux_l2_in_0_:A1 2.390819e-05 +2 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.844388e-05 +3 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0008540161 +4 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0008294805 +5 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002284024 +6 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002284024 +7 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.038237e-05 +8 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:8 6.038237e-05 +9 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001313214 +10 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001313214 + +*RES +0 mux_top_track_36\/mux_l1_in_0_:X mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004933035 +2 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.003258929 +4 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.01104911 +5 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 +7 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_36\/mux_l2_in_0_:A1 0.0001674107 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000846783 //LENGTH 6.085 LUMPCC 0.0003510846 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_0_:X O *L 0 *C 87.685 90.780 +*I mux_right_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 93.480 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 93.443 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.723 90.780 + +*CAP +0 mux_right_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002468492 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002468492 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size9_1_sram[1]:23 0.0001348199 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size9_1_sram[1]:22 0.0001348199 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.072239e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.072239e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005107143 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0008791529 //LENGTH 6.330 LUMPCC 0.0002447154 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_3_:X O *L 0 *C 109.195 55.420 +*I mux_right_track_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 107.355 58.820 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 107.355 58.820 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 107.180 58.820 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 107.180 58.775 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 107.180 55.465 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 107.225 55.420 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 109.157 55.420 + +*CAP +0 mux_right_track_4\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.736437e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 6.12299e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001682322 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001682322 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 8.868938e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 8.868938e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 optlc_net_124:37 8.438774e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 optlc_net_124:38 8.438774e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 3.796998e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 3.796998e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_3_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_right_track_4\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 9.51087e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.002955357 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.001725446 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0] 0.001039426 //LENGTH 7.800 LUMPCC 0.0002093079 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_0_:X O *L 0 *C 16.785 46.920 +*I mux_left_track_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 18.860 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 18.860 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 18.860 41.865 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 18.860 46.875 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 18.815 46.920 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 16.823 46.920 + +*CAP +0 mux_left_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 3.322225e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0002198108 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002198108 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.000177637 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.000177637 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 left_top_grid_pin_47_[0]:12 6.012993e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 left_top_grid_pin_47_[0]:11 6.012993e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 1.230096e-07 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 1.230096e-07 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 4.440101e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 4.440101e-05 + +*RES +0 mux_left_track_5\/mux_l3_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.001779018 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.004473214 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_left_track_5\/mux_l4_in_0_:A1 0.152 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002695232 //LENGTH 20.000 LUMPCC 0.0005639475 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_0_:X O *L 0 *C 50.775 66.300 +*I mux_left_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 36.705 61.540 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 36.705 61.540 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.800 61.585 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.800 63.535 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.845 63.580 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 44.575 63.580 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 44.620 63.625 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 44.620 66.255 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 44.665 66.300 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 50.738 66.300 + +*CAP +0 mux_left_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.961712e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001427789 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001427789 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003129517 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003129517 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001709531 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001709531 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004231501 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0004231501 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[12]:19 0.0002819737 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[12]:18 0.0002819737 + +*RES +0 mux_left_track_33\/mux_l1_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.005421876 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.002348214 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.006901786 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001741071 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_33\/mux_l2_in_0_:A1 0.152 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_140 0.001963293 //LENGTH 14.770 LUMPCC 0.0001116134 DR + +*CONN +*I FTB_1__0:X O *L 0 *C 55.200 99.620 +*I ropt_mt_inst_763:A I *L 0.001766 *C 64.400 96.560 +*N ropt_net_140:2 *C 64.400 96.560 +*N ropt_net_140:3 *C 64.400 96.220 +*N ropt_net_140:4 *C 58.925 96.220 +*N ropt_net_140:5 *C 58.880 96.265 +*N ropt_net_140:6 *C 58.880 99.915 +*N ropt_net_140:7 *C 58.835 99.960 +*N ropt_net_140:8 *C 55.200 99.960 +*N ropt_net_140:9 *C 55.200 99.620 + +*CAP +0 FTB_1__0:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_140:2 6.553189e-05 +3 ropt_net_140:3 0.0003817469 +4 ropt_net_140:4 0.000350023 +5 ropt_net_140:5 0.0002723425 +6 ropt_net_140:6 0.0002723425 +7 ropt_net_140:7 0.0002145293 +8 ropt_net_140:8 0.0002405292 +9 ropt_net_140:9 5.263493e-05 +10 ropt_net_140:7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.58067e-05 +11 ropt_net_140:8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.58067e-05 + +*RES +0 FTB_1__0:X ropt_net_140:9 0.152 +1 ropt_net_140:9 ropt_net_140:8 0.0003035715 +2 ropt_net_140:7 ropt_net_140:6 0.0045 +3 ropt_net_140:6 ropt_net_140:5 0.003258929 +4 ropt_net_140:4 ropt_net_140:3 0.004888393 +5 ropt_net_140:5 ropt_net_140:4 0.0045 +6 ropt_net_140:2 ropt_mt_inst_763:A 0.152 +7 ropt_net_140:8 ropt_net_140:7 0.003245536 +8 ropt_net_140:3 ropt_net_140:2 0.0003035715 + +*END + +*D_NET ropt_net_159 0.0008921839 //LENGTH 7.275 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 7.095 10.200 +*I ropt_mt_inst_785:A I *L 0.001767 *C 3.220 12.240 +*N ropt_net_159:2 *C 3.258 12.240 +*N ropt_net_159:3 *C 4.555 12.240 +*N ropt_net_159:4 *C 4.600 12.195 +*N ropt_net_159:5 *C 4.600 11.605 +*N ropt_net_159:6 *C 4.645 11.560 +*N ropt_net_159:7 *C 6.855 11.560 +*N ropt_net_159:8 *C 6.900 11.515 +*N ropt_net_159:9 *C 6.900 10.245 +*N ropt_net_159:10 *C 6.900 10.200 +*N ropt_net_159:11 *C 7.095 10.200 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_159:2 9.102521e-05 +3 ropt_net_159:3 9.102521e-05 +4 ropt_net_159:4 5.931885e-05 +5 ropt_net_159:5 5.931885e-05 +6 ropt_net_159:6 0.0001546398 +7 ropt_net_159:7 0.0001546398 +8 ropt_net_159:8 8.192698e-05 +9 ropt_net_159:9 8.192698e-05 +10 ropt_net_159:10 5.730766e-05 +11 ropt_net_159:11 5.905451e-05 + +*RES +0 ropt_mt_inst_757:X ropt_net_159:11 0.152 +1 ropt_net_159:11 ropt_net_159:10 0.0001059783 +2 ropt_net_159:10 ropt_net_159:9 0.0045 +3 ropt_net_159:9 ropt_net_159:8 0.001133929 +4 ropt_net_159:7 ropt_net_159:6 0.001973214 +5 ropt_net_159:8 ropt_net_159:7 0.0045 +6 ropt_net_159:6 ropt_net_159:5 0.0045 +7 ropt_net_159:5 ropt_net_159:4 0.0005267857 +8 ropt_net_159:3 ropt_net_159:2 0.001158482 +9 ropt_net_159:4 ropt_net_159:3 0.0045 +10 ropt_net_159:2 ropt_mt_inst_785:A 0.152 + +*END + +*D_NET chanx_left_out[7] 0.0006670735 //LENGTH 5.425 LUMPCC 9.230788e-05 DR + +*CONN +*I ropt_mt_inst_787:X O *L 0 *C 4.140 50.660 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 48.960 +*N chanx_left_out[7]:2 *C 2.752 48.960 +*N chanx_left_out[7]:3 *C 2.760 49.018 +*N chanx_left_out[7]:4 *C 2.760 50.615 +*N chanx_left_out[7]:5 *C 2.805 50.660 +*N chanx_left_out[7]:6 *C 4.103 50.660 + +*CAP +0 ropt_mt_inst_787:X 1e-06 +1 chanx_left_out[7] 0.0001308358 +2 chanx_left_out[7]:2 0.0001308358 +3 chanx_left_out[7]:3 6.048533e-05 +4 chanx_left_out[7]:4 6.048533e-05 +5 chanx_left_out[7]:5 9.556167e-05 +6 chanx_left_out[7]:6 9.556167e-05 +7 chanx_left_out[7]:4 ropt_net_161:3 4.615394e-05 +8 chanx_left_out[7]:3 ropt_net_161:4 4.615394e-05 + +*RES +0 ropt_mt_inst_787:X chanx_left_out[7]:6 0.152 +1 chanx_left_out[7]:6 chanx_left_out[7]:5 0.001158482 +2 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +3 chanx_left_out[7]:4 chanx_left_out[7]:3 0.001426339 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 0.000238525 + +*END + +*D_NET ropt_net_162 0.001285552 //LENGTH 8.635 LUMPCC 0.0004386007 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 7.095 65.960 +*I ropt_mt_inst_788:A I *L 0.001767 *C 3.220 63.920 +*N ropt_net_162:2 *C 3.258 63.920 +*N ropt_net_162:3 *C 4.095 63.920 +*N ropt_net_162:4 *C 4.140 63.875 +*N ropt_net_162:5 *C 4.140 63.285 +*N ropt_net_162:6 *C 4.185 63.240 +*N ropt_net_162:7 *C 6.855 63.240 +*N ropt_net_162:8 *C 6.900 63.285 +*N ropt_net_162:9 *C 6.900 65.915 +*N ropt_net_162:10 *C 6.900 65.960 +*N ropt_net_162:11 *C 7.095 65.960 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_162:2 3.587536e-05 +3 ropt_net_162:3 3.587536e-05 +4 ropt_net_162:4 6.856707e-05 +5 ropt_net_162:5 6.856707e-05 +6 ropt_net_162:6 0.000128592 +7 ropt_net_162:7 0.000128592 +8 ropt_net_162:8 0.0001261129 +9 ropt_net_162:9 0.0001261129 +10 ropt_net_162:10 6.28663e-05 +11 ropt_net_162:11 6.37902e-05 +12 ropt_net_162:9 ropt_net_153:4 7.294387e-06 +13 ropt_net_162:9 ropt_net_153:6 4.289117e-05 +14 ropt_net_162:7 ropt_net_153:6 1.469204e-05 +15 ropt_net_162:8 ropt_net_153:5 7.294387e-06 +16 ropt_net_162:8 ropt_net_153:7 4.289117e-05 +17 ropt_net_162:6 ropt_net_153:5 1.469204e-05 +18 ropt_net_162:7 chanx_left_out[5]:7 0.0001079198 +19 ropt_net_162:6 chanx_left_out[5]:6 0.0001079198 +20 ropt_net_162:5 chanx_left_out[5]:4 6.392504e-07 +21 ropt_net_162:3 chanx_left_out[5]:7 4.586371e-05 +22 ropt_net_162:4 chanx_left_out[5]:5 6.392504e-07 +23 ropt_net_162:2 chanx_left_out[5]:6 4.586371e-05 + +*RES +0 ropt_mt_inst_776:X ropt_net_162:11 0.152 +1 ropt_net_162:11 ropt_net_162:10 0.0001059783 +2 ropt_net_162:10 ropt_net_162:9 0.0045 +3 ropt_net_162:9 ropt_net_162:8 0.002348215 +4 ropt_net_162:7 ropt_net_162:6 0.002383929 +5 ropt_net_162:8 ropt_net_162:7 0.0045 +6 ropt_net_162:6 ropt_net_162:5 0.0045 +7 ropt_net_162:5 ropt_net_162:4 0.0005267857 +8 ropt_net_162:3 ropt_net_162:2 0.0007477679 +9 ropt_net_162:4 ropt_net_162:3 0.0045 +10 ropt_net_162:2 ropt_mt_inst_788:A 0.152 + +*END + +*D_NET chanx_right_in[16] 0.0181222 //LENGTH 168.580 LUMPCC 0.00296766 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 140.450 4.080 +*I mux_left_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 28.350 37.400 +*I FTB_12__11:A I *L 0.001776 *C 17.480 39.440 +*I mux_top_track_20\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.415 42.500 +*N chanx_right_in[16]:4 *C 66.415 42.500 +*N chanx_right_in[16]:5 *C 66.240 42.500 +*N chanx_right_in[16]:6 *C 66.240 42.455 +*N chanx_right_in[16]:7 *C 17.480 39.440 +*N chanx_right_in[16]:8 *C 17.720 39.440 +*N chanx_right_in[16]:9 *C 17.720 39.440 +*N chanx_right_in[16]:10 *C 17.727 39.440 +*N chanx_right_in[16]:11 *C 28.350 37.400 +*N chanx_right_in[16]:12 *C 28.520 37.400 +*N chanx_right_in[16]:13 *C 28.520 37.445 +*N chanx_right_in[16]:14 *C 28.520 39.383 +*N chanx_right_in[16]:15 *C 28.520 39.448 +*N chanx_right_in[16]:16 *C 28.520 40.120 +*N chanx_right_in[16]:17 *C 57.033 40.120 +*N chanx_right_in[16]:18 *C 57.040 40.178 +*N chanx_right_in[16]:19 *C 57.040 41.435 +*N chanx_right_in[16]:20 *C 57.085 41.480 +*N chanx_right_in[16]:21 *C 66.195 41.480 +*N chanx_right_in[16]:22 *C 66.240 41.480 +*N chanx_right_in[16]:23 *C 66.240 4.138 +*N chanx_right_in[16]:24 *C 66.248 4.080 +*N chanx_right_in[16]:25 *C 116.075 4.080 + +*CAP +0 chanx_right_in[16] 0.00100311 +1 mux_left_track_9\/mux_l2_in_1_:A0 1e-06 +2 FTB_12__11:A 1e-06 +3 mux_top_track_20\/mux_l1_in_0_:A0 1e-06 +4 chanx_right_in[16]:4 5.244583e-05 +5 chanx_right_in[16]:5 5.327109e-05 +6 chanx_right_in[16]:6 6.488011e-05 +7 chanx_right_in[16]:7 4.627793e-05 +8 chanx_right_in[16]:8 5.262532e-05 +9 chanx_right_in[16]:9 3.562844e-05 +10 chanx_right_in[16]:10 0.0005113192 +11 chanx_right_in[16]:11 5.315042e-05 +12 chanx_right_in[16]:12 5.850511e-05 +13 chanx_right_in[16]:13 0.0001271341 +14 chanx_right_in[16]:14 0.0001271341 +15 chanx_right_in[16]:15 0.000556412 +16 chanx_right_in[16]:16 0.001230598 +17 chanx_right_in[16]:17 0.001185505 +18 chanx_right_in[16]:18 9.139359e-05 +19 chanx_right_in[16]:19 9.139359e-05 +20 chanx_right_in[16]:20 0.0006442635 +21 chanx_right_in[16]:21 0.0006442635 +22 chanx_right_in[16]:22 0.001725372 +23 chanx_right_in[16]:23 0.001628656 +24 chanx_right_in[16]:24 0.002082543 +25 chanx_right_in[16]:25 0.003085653 +26 chanx_right_in[16] chanx_right_in[5] 3.734316e-05 +27 chanx_right_in[16] chanx_right_in[5]:30 7.719901e-05 +28 chanx_right_in[16]:24 chanx_right_in[5]:29 0.0001944671 +29 chanx_right_in[16]:25 chanx_right_in[5]:29 7.719901e-05 +30 chanx_right_in[16]:25 chanx_right_in[5]:30 0.0002318103 +31 chanx_right_in[16]:17 chanx_right_in[6]:20 0.0002817453 +32 chanx_right_in[16]:14 chanx_right_in[6]:12 1.98773e-06 +33 chanx_right_in[16]:14 chanx_right_in[6]:18 1.429379e-07 +34 chanx_right_in[16]:15 chanx_right_in[6]:11 0.0002252394 +35 chanx_right_in[16]:15 chanx_right_in[6]:20 1.113296e-05 +36 chanx_right_in[16]:13 chanx_right_in[6]:17 1.429379e-07 +37 chanx_right_in[16]:13 chanx_right_in[6]:18 1.98773e-06 +38 chanx_right_in[16]:10 chanx_right_in[6]:10 0.0002252394 +39 chanx_right_in[16]:10 chanx_right_in[6]:19 1.113296e-05 +40 chanx_right_in[16]:16 chanx_right_in[6]:19 0.0002817453 +41 chanx_right_in[16]:22 chanx_right_in[14]:19 0.0002901742 +42 chanx_right_in[16]:22 chanx_right_in[14]:20 1.132727e-05 +43 chanx_right_in[16]:15 chanx_right_in[14]:11 2.875502e-05 +44 chanx_right_in[16]:10 chanx_right_in[14]:10 2.875502e-05 +45 chanx_right_in[16]:6 chanx_right_in[14]:19 1.132727e-05 +46 chanx_right_in[16]:23 chanx_right_in[14]:20 0.0002901742 +47 chanx_right_in[16]:17 prog_clk[0]:468 0.0001376062 +48 chanx_right_in[16]:17 prog_clk[0]:490 5.235512e-06 +49 chanx_right_in[16]:17 prog_clk[0]:480 5.240594e-06 +50 chanx_right_in[16]:17 prog_clk[0]:472 0.0001319811 +51 chanx_right_in[16]:17 prog_clk[0]:476 3.364004e-05 +52 chanx_right_in[16]:15 prog_clk[0]:490 1.173973e-06 +53 chanx_right_in[16]:15 prog_clk[0]:457 1.714553e-06 +54 chanx_right_in[16]:15 prog_clk[0]:464 7.724389e-06 +55 chanx_right_in[16]:10 prog_clk[0]:489 1.173973e-06 +56 chanx_right_in[16]:10 prog_clk[0]:452 1.714553e-06 +57 chanx_right_in[16]:16 prog_clk[0]:490 5.240594e-06 +58 chanx_right_in[16]:16 prog_clk[0]:489 5.235512e-06 +59 chanx_right_in[16]:16 prog_clk[0]:478 7.724389e-06 +60 chanx_right_in[16]:16 prog_clk[0]:477 3.364004e-05 +61 chanx_right_in[16]:16 prog_clk[0]:472 0.0001376062 +62 chanx_right_in[16]:16 prog_clk[0]:476 0.0001319811 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:25 0.00381875 +1 chanx_right_in[16]:21 chanx_right_in[16]:20 0.008133929 +2 chanx_right_in[16]:22 chanx_right_in[16]:21 0.0045 +3 chanx_right_in[16]:22 chanx_right_in[16]:6 0.0008705358 +4 chanx_right_in[16]:20 chanx_right_in[16]:19 0.0045 +5 chanx_right_in[16]:19 chanx_right_in[16]:18 0.001122768 +6 chanx_right_in[16]:18 chanx_right_in[16]:17 0.00341 +7 chanx_right_in[16]:17 chanx_right_in[16]:16 0.004466958 +8 chanx_right_in[16]:14 chanx_right_in[16]:13 0.001729911 +9 chanx_right_in[16]:15 chanx_right_in[16]:14 0.00341 +10 chanx_right_in[16]:15 chanx_right_in[16]:10 0.001690825 +11 chanx_right_in[16]:12 chanx_right_in[16]:11 9.239131e-05 +12 chanx_right_in[16]:13 chanx_right_in[16]:12 0.0045 +13 chanx_right_in[16]:11 mux_left_track_9\/mux_l2_in_1_:A0 0.152 +14 chanx_right_in[16]:9 chanx_right_in[16]:8 0.0045 +15 chanx_right_in[16]:10 chanx_right_in[16]:9 0.00341 +16 chanx_right_in[16]:8 chanx_right_in[16]:7 0.0001304348 +17 chanx_right_in[16]:7 FTB_12__11:A 0.152 +18 chanx_right_in[16]:5 chanx_right_in[16]:4 9.51087e-05 +19 chanx_right_in[16]:6 chanx_right_in[16]:5 0.0045 +20 chanx_right_in[16]:4 mux_top_track_20\/mux_l1_in_0_:A0 0.152 +21 chanx_right_in[16]:23 chanx_right_in[16]:22 0.03334152 +22 chanx_right_in[16]:24 chanx_right_in[16]:23 0.00341 +23 chanx_right_in[16]:16 chanx_right_in[16]:15 0.0001053583 +24 chanx_right_in[16]:25 chanx_right_in[16]:24 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[2] 0.003052984 //LENGTH 24.455 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 103.805 58.480 +*I mux_right_track_4\/mux_l3_in_1_:S I *L 0.00357 *C 108.460 57.800 +*I mux_right_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 105.340 61.380 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 100.455 49.980 +*N mux_tree_tapbuf_size14_0_sram[2]:4 *C 100.493 49.980 +*N mux_tree_tapbuf_size14_0_sram[2]:5 *C 101.615 49.980 +*N mux_tree_tapbuf_size14_0_sram[2]:6 *C 101.660 50.025 +*N mux_tree_tapbuf_size14_0_sram[2]:7 *C 101.660 58.775 +*N mux_tree_tapbuf_size14_0_sram[2]:8 *C 101.705 58.820 +*N mux_tree_tapbuf_size14_0_sram[2]:9 *C 105.303 61.268 +*N mux_tree_tapbuf_size14_0_sram[2]:10 *C 104.465 61.200 +*N mux_tree_tapbuf_size14_0_sram[2]:11 *C 104.420 61.155 +*N mux_tree_tapbuf_size14_0_sram[2]:12 *C 108.422 57.800 +*N mux_tree_tapbuf_size14_0_sram[2]:13 *C 106.260 57.800 +*N mux_tree_tapbuf_size14_0_sram[2]:14 *C 106.260 58.140 +*N mux_tree_tapbuf_size14_0_sram[2]:15 *C 104.465 58.140 +*N mux_tree_tapbuf_size14_0_sram[2]:16 *C 104.420 58.185 +*N mux_tree_tapbuf_size14_0_sram[2]:17 *C 104.420 58.820 +*N mux_tree_tapbuf_size14_0_sram[2]:18 *C 104.420 58.790 +*N mux_tree_tapbuf_size14_0_sram[2]:19 *C 104.420 58.480 +*N mux_tree_tapbuf_size14_0_sram[2]:20 *C 103.843 58.480 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_4\/mux_l3_in_1_:S 1e-06 +2 mux_right_track_4\/mux_l3_in_0_:S 1e-06 +3 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size14_0_sram[2]:4 0.0001004813 +5 mux_tree_tapbuf_size14_0_sram[2]:5 0.0001004813 +6 mux_tree_tapbuf_size14_0_sram[2]:6 0.0004985895 +7 mux_tree_tapbuf_size14_0_sram[2]:7 0.0004985895 +8 mux_tree_tapbuf_size14_0_sram[2]:8 0.0002152804 +9 mux_tree_tapbuf_size14_0_sram[2]:9 8.234769e-05 +10 mux_tree_tapbuf_size14_0_sram[2]:10 8.234769e-05 +11 mux_tree_tapbuf_size14_0_sram[2]:11 0.0001679498 +12 mux_tree_tapbuf_size14_0_sram[2]:12 0.0001652918 +13 mux_tree_tapbuf_size14_0_sram[2]:13 0.0001920043 +14 mux_tree_tapbuf_size14_0_sram[2]:14 0.000155459 +15 mux_tree_tapbuf_size14_0_sram[2]:15 0.0001287465 +16 mux_tree_tapbuf_size14_0_sram[2]:16 5.535239e-05 +17 mux_tree_tapbuf_size14_0_sram[2]:17 0.0002572367 +18 mux_tree_tapbuf_size14_0_sram[2]:18 0.0002361237 +19 mux_tree_tapbuf_size14_0_sram[2]:19 6.677291e-05 +20 mux_tree_tapbuf_size14_0_sram[2]:20 4.592963e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size14_0_sram[2]:20 0.152 +1 mux_tree_tapbuf_size14_0_sram[2]:9 mux_right_track_4\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size14_0_sram[2]:10 mux_tree_tapbuf_size14_0_sram[2]:9 0.0007477679 +3 mux_tree_tapbuf_size14_0_sram[2]:11 mux_tree_tapbuf_size14_0_sram[2]:10 0.0045 +4 mux_tree_tapbuf_size14_0_sram[2]:18 mux_tree_tapbuf_size14_0_sram[2]:17 0.0045 +5 mux_tree_tapbuf_size14_0_sram[2]:18 mux_tree_tapbuf_size14_0_sram[2]:8 0.002424107 +6 mux_tree_tapbuf_size14_0_sram[2]:17 mux_tree_tapbuf_size14_0_sram[2]:16 0.0005669643 +7 mux_tree_tapbuf_size14_0_sram[2]:17 mux_tree_tapbuf_size14_0_sram[2]:11 0.002084821 +8 mux_tree_tapbuf_size14_0_sram[2]:8 mux_tree_tapbuf_size14_0_sram[2]:7 0.0045 +9 mux_tree_tapbuf_size14_0_sram[2]:7 mux_tree_tapbuf_size14_0_sram[2]:6 0.0078125 +10 mux_tree_tapbuf_size14_0_sram[2]:5 mux_tree_tapbuf_size14_0_sram[2]:4 0.001002232 +11 mux_tree_tapbuf_size14_0_sram[2]:6 mux_tree_tapbuf_size14_0_sram[2]:5 0.0045 +12 mux_tree_tapbuf_size14_0_sram[2]:4 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size14_0_sram[2]:20 mux_tree_tapbuf_size14_0_sram[2]:19 0.000515625 +14 mux_tree_tapbuf_size14_0_sram[2]:15 mux_tree_tapbuf_size14_0_sram[2]:14 0.001602679 +15 mux_tree_tapbuf_size14_0_sram[2]:16 mux_tree_tapbuf_size14_0_sram[2]:15 0.0045 +16 mux_tree_tapbuf_size14_0_sram[2]:12 mux_right_track_4\/mux_l3_in_1_:S 0.152 +17 mux_tree_tapbuf_size14_0_sram[2]:19 mux_tree_tapbuf_size14_0_sram[2]:18 0.0002767857 +18 mux_tree_tapbuf_size14_0_sram[2]:14 mux_tree_tapbuf_size14_0_sram[2]:13 0.0003035715 +19 mux_tree_tapbuf_size14_0_sram[2]:13 mux_tree_tapbuf_size14_0_sram[2]:12 0.001930804 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.001391846 //LENGTH 12.320 LUMPCC 0 DR + +*CONN +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.485 98.940 +*I mux_top_track_34\/mux_l1_in_0_:S I *L 0.00357 *C 41.740 90.780 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.035 98.940 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 41.910 98.940 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 41.740 90.780 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 41.860 90.825 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 41.860 98.895 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 41.815 98.940 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 38.523 98.940 + +*CAP +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_34\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 2.244038e-05 +4 mux_tree_tapbuf_size2_3_sram[0]:4 2.924131e-05 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0004624714 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.0004624714 +7 mux_tree_tapbuf_size2_3_sram[0]:7 0.000217331 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.0001948906 + +*RES +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:8 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:4 mux_top_track_34\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:3 8.482143e-05 +5 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.007205358 +6 mux_tree_tapbuf_size2_3_sram[0]:3 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.002939732 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001855508 //LENGTH 13.295 LUMPCC 0.0002906796 DR + +*CONN +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.045 64.260 +*I mem_top_track_12\/FTB_14__40:A I *L 0.001746 *C 68.540 66.640 +*I mux_top_track_12\/mux_l2_in_0_:S I *L 0.00357 *C 72.580 66.935 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 72.580 66.935 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 68.578 66.640 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 72.580 66.640 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 73.555 66.640 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 73.600 66.595 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 73.600 64.305 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 73.645 64.260 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 78.008 64.260 + +*CAP +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_12\/FTB_14__40:A 1e-06 +2 mux_top_track_12\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 6.201644e-05 +4 mux_tree_tapbuf_size3_0_sram[1]:4 0.0001862742 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0002734244 +6 mux_tree_tapbuf_size3_0_sram[1]:6 5.548226e-05 +7 mux_tree_tapbuf_size3_0_sram[1]:7 0.0001784572 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0001784572 +9 mux_tree_tapbuf_size3_0_sram[1]:9 0.0003138584 +10 mux_tree_tapbuf_size3_0_sram[1]:10 0.0003138584 +11 mux_tree_tapbuf_size3_0_sram[1]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.398191e-05 +12 mux_tree_tapbuf_size3_0_sram[1]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.398191e-05 +13 mux_tree_tapbuf_size3_0_sram[1]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.951367e-05 +14 mux_tree_tapbuf_size3_0_sram[1]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.184419e-05 +15 mux_tree_tapbuf_size3_0_sram[1]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.951367e-05 +16 mux_tree_tapbuf_size3_0_sram[1]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.184419e-05 + +*RES +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:6 mux_tree_tapbuf_size3_0_sram[1]:5 0.0008705358 +2 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.002044643 +5 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.003895089 +6 mux_tree_tapbuf_size3_0_sram[1]:4 mem_top_track_12\/FTB_14__40:A 0.152 +7 mux_tree_tapbuf_size3_0_sram[1]:3 mux_top_track_12\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.003573661 +9 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:3 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size3_5_sram[0] 0.002130998 //LENGTH 17.360 LUMPCC 0 DR + +*CONN +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.805 23.120 +*I mux_top_track_22\/mux_l1_in_1_:S I *L 0.00357 *C 82.700 29.240 +*I mux_top_track_22\/mux_l1_in_0_:S I *L 0.00357 *C 84.060 34.340 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 83.895 26.180 +*N mux_tree_tapbuf_size3_5_sram[0]:4 *C 83.770 26.180 +*N mux_tree_tapbuf_size3_5_sram[0]:5 *C 84.045 34.340 +*N mux_tree_tapbuf_size3_5_sram[0]:6 *C 83.743 34.340 +*N mux_tree_tapbuf_size3_5_sram[0]:7 *C 83.720 34.295 +*N mux_tree_tapbuf_size3_5_sram[0]:8 *C 82.737 29.240 +*N mux_tree_tapbuf_size3_5_sram[0]:9 *C 83.675 29.240 +*N mux_tree_tapbuf_size3_5_sram[0]:10 *C 83.720 29.240 +*N mux_tree_tapbuf_size3_5_sram[0]:11 *C 83.720 26.225 +*N mux_tree_tapbuf_size3_5_sram[0]:12 *C 83.675 26.180 +*N mux_tree_tapbuf_size3_5_sram[0]:13 *C 81.005 26.180 +*N mux_tree_tapbuf_size3_5_sram[0]:14 *C 80.960 26.135 +*N mux_tree_tapbuf_size3_5_sram[0]:15 *C 80.960 23.165 +*N mux_tree_tapbuf_size3_5_sram[0]:16 *C 80.960 23.120 +*N mux_tree_tapbuf_size3_5_sram[0]:17 *C 80.805 23.120 + +*CAP +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_22\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_22\/mux_l1_in_0_:S 1e-06 +3 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_5_sram[0]:4 2.337088e-05 +5 mux_tree_tapbuf_size3_5_sram[0]:5 6.23745e-05 +6 mux_tree_tapbuf_size3_5_sram[0]:6 6.23745e-05 +7 mux_tree_tapbuf_size3_5_sram[0]:7 0.0002892807 +8 mux_tree_tapbuf_size3_5_sram[0]:8 0.0001019851 +9 mux_tree_tapbuf_size3_5_sram[0]:9 0.0001019851 +10 mux_tree_tapbuf_size3_5_sram[0]:10 0.0004946036 +11 mux_tree_tapbuf_size3_5_sram[0]:11 0.0001709484 +12 mux_tree_tapbuf_size3_5_sram[0]:12 0.0002074565 +13 mux_tree_tapbuf_size3_5_sram[0]:13 0.0001840857 +14 mux_tree_tapbuf_size3_5_sram[0]:14 0.0001665655 +15 mux_tree_tapbuf_size3_5_sram[0]:15 0.0001665655 +16 mux_tree_tapbuf_size3_5_sram[0]:16 4.882016e-05 +17 mux_tree_tapbuf_size3_5_sram[0]:17 4.658219e-05 + +*RES +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_5_sram[0]:17 0.152 +1 mux_tree_tapbuf_size3_5_sram[0]:8 mux_top_track_22\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_5_sram[0]:9 mux_tree_tapbuf_size3_5_sram[0]:8 0.0008370536 +3 mux_tree_tapbuf_size3_5_sram[0]:10 mux_tree_tapbuf_size3_5_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size3_5_sram[0]:10 mux_tree_tapbuf_size3_5_sram[0]:7 0.004513393 +5 mux_tree_tapbuf_size3_5_sram[0]:5 mux_top_track_22\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size3_5_sram[0]:6 mux_tree_tapbuf_size3_5_sram[0]:5 0.0001644022 +7 mux_tree_tapbuf_size3_5_sram[0]:7 mux_tree_tapbuf_size3_5_sram[0]:6 0.0045 +8 mux_tree_tapbuf_size3_5_sram[0]:4 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size3_5_sram[0]:13 mux_tree_tapbuf_size3_5_sram[0]:12 0.002383929 +10 mux_tree_tapbuf_size3_5_sram[0]:14 mux_tree_tapbuf_size3_5_sram[0]:13 0.0045 +11 mux_tree_tapbuf_size3_5_sram[0]:16 mux_tree_tapbuf_size3_5_sram[0]:15 0.0045 +12 mux_tree_tapbuf_size3_5_sram[0]:15 mux_tree_tapbuf_size3_5_sram[0]:14 0.002651786 +13 mux_tree_tapbuf_size3_5_sram[0]:17 mux_tree_tapbuf_size3_5_sram[0]:16 8.423914e-05 +14 mux_tree_tapbuf_size3_5_sram[0]:12 mux_tree_tapbuf_size3_5_sram[0]:11 0.0045 +15 mux_tree_tapbuf_size3_5_sram[0]:12 mux_tree_tapbuf_size3_5_sram[0]:4 8.482143e-05 +16 mux_tree_tapbuf_size3_5_sram[0]:11 mux_tree_tapbuf_size3_5_sram[0]:10 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_7_ccff_tail[0] 0.001398825 //LENGTH 9.680 LUMPCC 0.0004343426 DR + +*CONN +*I mem_top_track_38\/FTB_21__47:X O *L 0 *C 91.315 88.400 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 88.495 82.620 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:2 *C 88.495 82.620 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:3 *C 88.780 82.620 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 *C 88.780 82.665 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 *C 88.780 83.583 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 *C 88.788 83.640 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 *C 91.073 83.640 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 *C 91.080 83.698 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 *C 91.080 88.355 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:10 *C 91.080 88.400 +*N mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:11 *C 91.315 88.400 + +*CAP +0 mem_top_track_38\/FTB_21__47:X 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:2 6.411388e-05 +3 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:3 6.552353e-05 +4 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 6.335057e-05 +5 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 6.335057e-05 +6 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 0.0001043647 +7 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 0.0001043647 +8 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 0.0001993836 +9 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 0.0001993836 +10 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:10 4.998966e-05 +11 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:11 4.865751e-05 +12 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 chanx_right_in[0]:7 0.0001427393 +13 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 chanx_right_in[0]:6 0.0001427393 +14 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 mux_tree_tapbuf_size9_1_sram[1]:21 3.507688e-05 +15 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 mux_tree_tapbuf_size9_1_sram[1]:20 3.077491e-05 +16 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 mux_tree_tapbuf_size9_1_sram[1]:17 3.077491e-05 +17 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 mux_tree_tapbuf_size9_1_sram[1]:20 3.507688e-05 +18 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size9_1_sram[1]:17 1.005741e-06 +19 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size9_1_sram[1]:20 7.574487e-06 +20 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size9_1_sram[1]:17 7.574487e-06 +21 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size9_1_sram[1]:9 1.005741e-06 + +*RES +0 mem_top_track_38\/FTB_21__47:X mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:11 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:10 0.0001277174 +2 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:10 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 0.004158483 +4 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 0.00341 +5 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 0.0003579833 +6 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 0.0008191965 +7 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 0.00341 +8 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:2 0.0001548913 +9 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.002105316 //LENGTH 15.395 LUMPCC 0.0002444824 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 18.995 55.080 +*I mux_left_track_33\/mux_l3_in_0_:S I *L 0.00357 *C 8.840 52.750 +*I mem_left_track_33\/FTB_32__58:A I *L 0.001743 *C 7.360 53.040 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 7.360 53.040 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 7.360 52.700 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 8.753 52.703 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 8.740 52.745 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 8.740 55.035 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 8.785 55.080 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 18.957 55.080 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_33\/FTB_32__58:A 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 5.796379e-05 +4 mux_tree_tapbuf_size6_1_sram[2]:4 0.0001276061 +5 mux_tree_tapbuf_size6_1_sram[2]:5 9.916482e-05 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0001450981 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0001450981 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0006414515 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.0006414515 +10 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0001222412 +11 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.0001222412 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:9 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:3 mem_left_track_33\/FTB_32__58:A 0.152 +2 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.009082589 +3 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.002044643 +5 mux_tree_tapbuf_size6_1_sram[2]:5 mux_left_track_33\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_1_sram[2]:5 mux_tree_tapbuf_size6_1_sram[2]:4 0.001243304 +7 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.0045 +8 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[2] 0.002151929 //LENGTH 17.330 LUMPCC 0 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 93.685 39.100 +*I mem_top_track_6\/FTB_7__33:A I *L 0.001746 *C 92.000 47.600 +*I mux_top_track_6\/mux_l3_in_0_:S I *L 0.00357 *C 89.240 50.485 +*N mux_tree_tapbuf_size7_2_sram[2]:3 *C 89.240 50.485 +*N mux_tree_tapbuf_size7_2_sram[2]:4 *C 89.240 50.320 +*N mux_tree_tapbuf_size7_2_sram[2]:5 *C 89.240 50.275 +*N mux_tree_tapbuf_size7_2_sram[2]:6 *C 89.240 47.645 +*N mux_tree_tapbuf_size7_2_sram[2]:7 *C 89.285 47.600 +*N mux_tree_tapbuf_size7_2_sram[2]:8 *C 92.000 47.600 +*N mux_tree_tapbuf_size7_2_sram[2]:9 *C 92.460 47.600 +*N mux_tree_tapbuf_size7_2_sram[2]:10 *C 92.460 47.260 +*N mux_tree_tapbuf_size7_2_sram[2]:11 *C 92.460 47.215 +*N mux_tree_tapbuf_size7_2_sram[2]:12 *C 92.460 39.145 +*N mux_tree_tapbuf_size7_2_sram[2]:13 *C 92.505 39.100 +*N mux_tree_tapbuf_size7_2_sram[2]:14 *C 93.648 39.100 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_6\/FTB_7__33:A 1e-06 +2 mux_top_track_6\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_2_sram[2]:3 4.070189e-05 +4 mux_tree_tapbuf_size7_2_sram[2]:4 4.49347e-05 +5 mux_tree_tapbuf_size7_2_sram[2]:5 0.0001679373 +6 mux_tree_tapbuf_size7_2_sram[2]:6 0.0001679373 +7 mux_tree_tapbuf_size7_2_sram[2]:7 0.000212005 +8 mux_tree_tapbuf_size7_2_sram[2]:8 0.0002764092 +9 mux_tree_tapbuf_size7_2_sram[2]:9 6.54325e-05 +10 mux_tree_tapbuf_size7_2_sram[2]:10 5.944793e-05 +11 mux_tree_tapbuf_size7_2_sram[2]:11 0.0004641147 +12 mux_tree_tapbuf_size7_2_sram[2]:12 0.0004641147 +13 mux_tree_tapbuf_size7_2_sram[2]:13 9.294692e-05 +14 mux_tree_tapbuf_size7_2_sram[2]:14 9.294692e-05 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_2_sram[2]:14 0.152 +1 mux_tree_tapbuf_size7_2_sram[2]:3 mux_top_track_6\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[2]:4 mux_tree_tapbuf_size7_2_sram[2]:3 7.11207e-05 +3 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:4 0.0045 +4 mux_tree_tapbuf_size7_2_sram[2]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size7_2_sram[2]:6 mux_tree_tapbuf_size7_2_sram[2]:5 0.002348215 +6 mux_tree_tapbuf_size7_2_sram[2]:10 mux_tree_tapbuf_size7_2_sram[2]:9 0.0003035715 +7 mux_tree_tapbuf_size7_2_sram[2]:11 mux_tree_tapbuf_size7_2_sram[2]:10 0.0045 +8 mux_tree_tapbuf_size7_2_sram[2]:13 mux_tree_tapbuf_size7_2_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size7_2_sram[2]:12 mux_tree_tapbuf_size7_2_sram[2]:11 0.007205358 +10 mux_tree_tapbuf_size7_2_sram[2]:14 mux_tree_tapbuf_size7_2_sram[2]:13 0.001020089 +11 mux_tree_tapbuf_size7_2_sram[2]:8 mem_top_track_6\/FTB_7__33:A 0.152 +12 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:7 0.002424107 +13 mux_tree_tapbuf_size7_2_sram[2]:9 mux_tree_tapbuf_size7_2_sram[2]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[0] 0.006645461 //LENGTH 49.865 LUMPCC 0.0002016666 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 35.725 31.620 +*I mux_left_track_17\/mux_l1_in_2_:S I *L 0.00357 *C 34.400 34.295 +*I mux_left_track_17\/mux_l1_in_3_:S I *L 0.00357 *C 34.400 36.040 +*I mux_left_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 67.720 30.600 +*I mux_left_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 54.380 28.855 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 46.175 33.660 +*N mux_tree_tapbuf_size7_5_sram[0]:6 *C 46.175 33.660 +*N mux_tree_tapbuf_size7_5_sram[0]:7 *C 46.460 33.660 +*N mux_tree_tapbuf_size7_5_sram[0]:8 *C 46.460 33.615 +*N mux_tree_tapbuf_size7_5_sram[0]:9 *C 54.380 28.855 +*N mux_tree_tapbuf_size7_5_sram[0]:10 *C 67.683 30.600 +*N mux_tree_tapbuf_size7_5_sram[0]:11 *C 67.205 30.600 +*N mux_tree_tapbuf_size7_5_sram[0]:12 *C 67.160 30.555 +*N mux_tree_tapbuf_size7_5_sram[0]:13 *C 67.160 29.285 +*N mux_tree_tapbuf_size7_5_sram[0]:14 *C 67.115 29.240 +*N mux_tree_tapbuf_size7_5_sram[0]:15 *C 54.330 29.240 +*N mux_tree_tapbuf_size7_5_sram[0]:16 *C 46.505 29.240 +*N mux_tree_tapbuf_size7_5_sram[0]:17 *C 46.460 29.285 +*N mux_tree_tapbuf_size7_5_sram[0]:18 *C 46.460 31.960 +*N mux_tree_tapbuf_size7_5_sram[0]:19 *C 46.415 31.960 +*N mux_tree_tapbuf_size7_5_sram[0]:20 *C 34.438 36.040 +*N mux_tree_tapbuf_size7_5_sram[0]:21 *C 36.295 36.040 +*N mux_tree_tapbuf_size7_5_sram[0]:22 *C 36.340 35.995 +*N mux_tree_tapbuf_size7_5_sram[0]:23 *C 34.438 34.340 +*N mux_tree_tapbuf_size7_5_sram[0]:24 *C 36.295 34.340 +*N mux_tree_tapbuf_size7_5_sram[0]:25 *C 36.340 34.340 +*N mux_tree_tapbuf_size7_5_sram[0]:26 *C 36.340 32.005 +*N mux_tree_tapbuf_size7_5_sram[0]:27 *C 36.340 31.960 +*N mux_tree_tapbuf_size7_5_sram[0]:28 *C 36.340 31.620 +*N mux_tree_tapbuf_size7_5_sram[0]:29 *C 35.763 31.620 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_17\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_17\/mux_l1_in_3_:S 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:S 1e-06 +4 mux_left_track_17\/mux_l1_in_1_:S 1e-06 +5 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_5_sram[0]:6 5.446268e-05 +7 mux_tree_tapbuf_size7_5_sram[0]:7 5.838751e-05 +8 mux_tree_tapbuf_size7_5_sram[0]:8 9.601424e-05 +9 mux_tree_tapbuf_size7_5_sram[0]:9 6.13579e-05 +10 mux_tree_tapbuf_size7_5_sram[0]:10 6.11151e-05 +11 mux_tree_tapbuf_size7_5_sram[0]:11 6.11151e-05 +12 mux_tree_tapbuf_size7_5_sram[0]:12 0.000107722 +13 mux_tree_tapbuf_size7_5_sram[0]:13 0.000107722 +14 mux_tree_tapbuf_size7_5_sram[0]:14 0.0008959039 +15 mux_tree_tapbuf_size7_5_sram[0]:15 0.00148018 +16 mux_tree_tapbuf_size7_5_sram[0]:16 0.0005510289 +17 mux_tree_tapbuf_size7_5_sram[0]:17 0.0001524075 +18 mux_tree_tapbuf_size7_5_sram[0]:18 0.0002804846 +19 mux_tree_tapbuf_size7_5_sram[0]:19 0.0006791204 +20 mux_tree_tapbuf_size7_5_sram[0]:20 0.0001547403 +21 mux_tree_tapbuf_size7_5_sram[0]:21 0.0001547403 +22 mux_tree_tapbuf_size7_5_sram[0]:22 8.252812e-05 +23 mux_tree_tapbuf_size7_5_sram[0]:23 8.245782e-05 +24 mux_tree_tapbuf_size7_5_sram[0]:24 8.245782e-05 +25 mux_tree_tapbuf_size7_5_sram[0]:25 0.0002524399 +26 mux_tree_tapbuf_size7_5_sram[0]:26 0.0001354136 +27 mux_tree_tapbuf_size7_5_sram[0]:27 0.0007112065 +28 mux_tree_tapbuf_size7_5_sram[0]:28 8.34373e-05 +29 mux_tree_tapbuf_size7_5_sram[0]:29 5.135123e-05 +30 mux_tree_tapbuf_size7_5_sram[0]:24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.110841e-05 +31 mux_tree_tapbuf_size7_5_sram[0]:23 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.110841e-05 +32 mux_tree_tapbuf_size7_5_sram[0]:20 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.384689e-06 +33 mux_tree_tapbuf_size7_5_sram[0]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.384689e-06 +34 mux_tree_tapbuf_size7_5_sram[0]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.133106e-05 +35 mux_tree_tapbuf_size7_5_sram[0]:24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 1.766075e-05 +36 mux_tree_tapbuf_size7_5_sram[0]:25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.34838e-06 +37 mux_tree_tapbuf_size7_5_sram[0]:25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.133106e-05 +38 mux_tree_tapbuf_size7_5_sram[0]:23 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 1.766075e-05 +39 mux_tree_tapbuf_size7_5_sram[0]:26 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.34838e-06 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_5_sram[0]:29 0.152 +1 mux_tree_tapbuf_size7_5_sram[0]:20 mux_left_track_17\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size7_5_sram[0]:21 mux_tree_tapbuf_size7_5_sram[0]:20 0.001658482 +3 mux_tree_tapbuf_size7_5_sram[0]:22 mux_tree_tapbuf_size7_5_sram[0]:21 0.0045 +4 mux_tree_tapbuf_size7_5_sram[0]:19 mux_tree_tapbuf_size7_5_sram[0]:18 0.0045 +5 mux_tree_tapbuf_size7_5_sram[0]:18 mux_tree_tapbuf_size7_5_sram[0]:17 0.002388393 +6 mux_tree_tapbuf_size7_5_sram[0]:18 mux_tree_tapbuf_size7_5_sram[0]:8 0.001477678 +7 mux_tree_tapbuf_size7_5_sram[0]:7 mux_tree_tapbuf_size7_5_sram[0]:6 0.0001548913 +8 mux_tree_tapbuf_size7_5_sram[0]:8 mux_tree_tapbuf_size7_5_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size7_5_sram[0]:6 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size7_5_sram[0]:24 mux_tree_tapbuf_size7_5_sram[0]:23 0.001658482 +11 mux_tree_tapbuf_size7_5_sram[0]:25 mux_tree_tapbuf_size7_5_sram[0]:24 0.0045 +12 mux_tree_tapbuf_size7_5_sram[0]:25 mux_tree_tapbuf_size7_5_sram[0]:22 0.001477679 +13 mux_tree_tapbuf_size7_5_sram[0]:23 mux_left_track_17\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size7_5_sram[0]:27 mux_tree_tapbuf_size7_5_sram[0]:26 0.0045 +15 mux_tree_tapbuf_size7_5_sram[0]:27 mux_tree_tapbuf_size7_5_sram[0]:19 0.008995537 +16 mux_tree_tapbuf_size7_5_sram[0]:26 mux_tree_tapbuf_size7_5_sram[0]:25 0.002084821 +17 mux_tree_tapbuf_size7_5_sram[0]:16 mux_tree_tapbuf_size7_5_sram[0]:15 0.006986608 +18 mux_tree_tapbuf_size7_5_sram[0]:17 mux_tree_tapbuf_size7_5_sram[0]:16 0.0045 +19 mux_tree_tapbuf_size7_5_sram[0]:9 mux_left_track_17\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size7_5_sram[0]:14 mux_tree_tapbuf_size7_5_sram[0]:13 0.0045 +21 mux_tree_tapbuf_size7_5_sram[0]:13 mux_tree_tapbuf_size7_5_sram[0]:12 0.001133929 +22 mux_tree_tapbuf_size7_5_sram[0]:11 mux_tree_tapbuf_size7_5_sram[0]:10 0.0004263393 +23 mux_tree_tapbuf_size7_5_sram[0]:12 mux_tree_tapbuf_size7_5_sram[0]:11 0.0045 +24 mux_tree_tapbuf_size7_5_sram[0]:10 mux_left_track_17\/mux_l1_in_0_:S 0.152 +25 mux_tree_tapbuf_size7_5_sram[0]:29 mux_tree_tapbuf_size7_5_sram[0]:28 0.000515625 +26 mux_tree_tapbuf_size7_5_sram[0]:28 mux_tree_tapbuf_size7_5_sram[0]:27 0.0003035715 +27 mux_tree_tapbuf_size7_5_sram[0]:15 mux_tree_tapbuf_size7_5_sram[0]:14 0.01141518 +28 mux_tree_tapbuf_size7_5_sram[0]:15 mux_tree_tapbuf_size7_5_sram[0]:9 0.0002005209 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[0] 0.004351242 //LENGTH 31.450 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 40.325 82.620 +*I mux_left_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 57.600 80.240 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 77.180 +*N mux_tree_tapbuf_size8_2_sram[0]:3 *C 32.873 77.180 +*N mux_tree_tapbuf_size8_2_sram[0]:4 *C 39.975 77.180 +*N mux_tree_tapbuf_size8_2_sram[0]:5 *C 40.020 77.225 +*N mux_tree_tapbuf_size8_2_sram[0]:6 *C 57.600 80.240 +*N mux_tree_tapbuf_size8_2_sram[0]:7 *C 57.600 80.240 +*N mux_tree_tapbuf_size8_2_sram[0]:8 *C 57.593 80.240 +*N mux_tree_tapbuf_size8_2_sram[0]:9 *C 40.028 80.240 +*N mux_tree_tapbuf_size8_2_sram[0]:10 *C 40.020 80.240 +*N mux_tree_tapbuf_size8_2_sram[0]:11 *C 40.020 82.575 +*N mux_tree_tapbuf_size8_2_sram[0]:12 *C 40.020 82.620 +*N mux_tree_tapbuf_size8_2_sram[0]:13 *C 40.325 82.620 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_3\/mux_l1_in_0_:S 1e-06 +2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_2_sram[0]:3 0.0004584139 +4 mux_tree_tapbuf_size8_2_sram[0]:4 0.0004584139 +5 mux_tree_tapbuf_size8_2_sram[0]:5 0.0001646389 +6 mux_tree_tapbuf_size8_2_sram[0]:6 3.339929e-05 +7 mux_tree_tapbuf_size8_2_sram[0]:7 3.55892e-05 +8 mux_tree_tapbuf_size8_2_sram[0]:8 0.00131773 +9 mux_tree_tapbuf_size8_2_sram[0]:9 0.00131773 +10 mux_tree_tapbuf_size8_2_sram[0]:10 0.0003298073 +11 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001290285 +12 mux_tree_tapbuf_size8_2_sram[0]:12 5.547133e-05 +13 mux_tree_tapbuf_size8_2_sram[0]:13 4.801949e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_2_sram[0]:4 mux_tree_tapbuf_size8_2_sram[0]:3 0.006341518 +2 mux_tree_tapbuf_size8_2_sram[0]:5 mux_tree_tapbuf_size8_2_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size8_2_sram[0]:3 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:9 0.00341 +5 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:5 0.002691964 +6 mux_tree_tapbuf_size8_2_sram[0]:9 mux_tree_tapbuf_size8_2_sram[0]:8 0.00275185 +7 mux_tree_tapbuf_size8_2_sram[0]:7 mux_tree_tapbuf_size8_2_sram[0]:6 0.0045 +8 mux_tree_tapbuf_size8_2_sram[0]:8 mux_tree_tapbuf_size8_2_sram[0]:7 0.00341 +9 mux_tree_tapbuf_size8_2_sram[0]:6 mux_left_track_3\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size8_2_sram[0]:11 mux_tree_tapbuf_size8_2_sram[0]:10 0.002084821 +12 mux_tree_tapbuf_size8_2_sram[0]:13 mux_tree_tapbuf_size8_2_sram[0]:12 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_3_ccff_tail[0] 0.0008506686 //LENGTH 7.270 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/FTB_4__30:X O *L 0 *C 33.355 28.560 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 30.075 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 *C 30.113 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 *C 31.235 31.620 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 *C 31.280 31.575 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 *C 31.280 28.605 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 *C 31.325 28.560 +*N mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 *C 33.318 28.560 + +*CAP +0 mem_left_track_9\/FTB_4__30:X 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 0.0001110505 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 0.0001110505 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.000185089 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.000185089 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.0001281948 +7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.0001281948 + +*RES +0 mem_left_track_9\/FTB_4__30:X mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 0.001779018 +2 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 0.001002232 +5 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_3_ccff_tail[0]:2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size9_1_sram[0] 0.003815677 //LENGTH 28.540 LUMPCC 0.0001603413 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 108.855 93.500 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 94.475 93.500 +*I mux_right_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 86.840 91.120 +*I mux_right_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 90.060 94.135 +*N mux_tree_tapbuf_size9_1_sram[0]:4 *C 90.060 94.135 +*N mux_tree_tapbuf_size9_1_sram[0]:5 *C 90.118 93.840 +*N mux_tree_tapbuf_size9_1_sram[0]:6 *C 92.000 93.840 +*N mux_tree_tapbuf_size9_1_sram[0]:7 *C 86.840 91.120 +*N mux_tree_tapbuf_size9_1_sram[0]:8 *C 86.940 91.165 +*N mux_tree_tapbuf_size9_1_sram[0]:9 *C 86.940 93.455 +*N mux_tree_tapbuf_size9_1_sram[0]:10 *C 86.985 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:11 *C 92.000 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:12 *C 94.475 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:13 *C 102.535 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:14 *C 102.580 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:15 *C 103.960 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:16 *C 104.005 93.500 +*N mux_tree_tapbuf_size9_1_sram[0]:17 *C 108.818 93.500 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:S 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size9_1_sram[0]:4 5.752046e-05 +5 mux_tree_tapbuf_size9_1_sram[0]:5 0.0002008203 +6 mux_tree_tapbuf_size9_1_sram[0]:6 0.0001964128 +7 mux_tree_tapbuf_size9_1_sram[0]:7 2.902448e-05 +8 mux_tree_tapbuf_size9_1_sram[0]:8 0.0001686607 +9 mux_tree_tapbuf_size9_1_sram[0]:9 0.0001686607 +10 mux_tree_tapbuf_size9_1_sram[0]:10 0.0002875199 +11 mux_tree_tapbuf_size9_1_sram[0]:11 0.0004904894 +12 mux_tree_tapbuf_size9_1_sram[0]:12 0.0007359488 +13 mux_tree_tapbuf_size9_1_sram[0]:13 0.0005302154 +14 mux_tree_tapbuf_size9_1_sram[0]:14 0.0001117326 +15 mux_tree_tapbuf_size9_1_sram[0]:15 0.0001126491 +16 mux_tree_tapbuf_size9_1_sram[0]:16 0.0002808408 +17 mux_tree_tapbuf_size9_1_sram[0]:17 0.0002808408 +18 mux_tree_tapbuf_size9_1_sram[0]:17 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 8.017064e-05 +19 mux_tree_tapbuf_size9_1_sram[0]:16 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 8.017064e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size9_1_sram[0]:17 0.152 +1 mux_tree_tapbuf_size9_1_sram[0]:17 mux_tree_tapbuf_size9_1_sram[0]:16 0.004296876 +2 mux_tree_tapbuf_size9_1_sram[0]:16 mux_tree_tapbuf_size9_1_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size9_1_sram[0]:15 mux_tree_tapbuf_size9_1_sram[0]:14 0.001232143 +4 mux_tree_tapbuf_size9_1_sram[0]:13 mux_tree_tapbuf_size9_1_sram[0]:12 0.007196429 +5 mux_tree_tapbuf_size9_1_sram[0]:14 mux_tree_tapbuf_size9_1_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size9_1_sram[0]:12 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size9_1_sram[0]:12 mux_tree_tapbuf_size9_1_sram[0]:11 0.002209821 +8 mux_tree_tapbuf_size9_1_sram[0]:4 mux_right_track_2\/mux_l1_in_1_:S 0.152 +9 mux_tree_tapbuf_size9_1_sram[0]:10 mux_tree_tapbuf_size9_1_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size9_1_sram[0]:9 mux_tree_tapbuf_size9_1_sram[0]:8 0.002044643 +11 mux_tree_tapbuf_size9_1_sram[0]:7 mux_right_track_2\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size9_1_sram[0]:8 mux_tree_tapbuf_size9_1_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size9_1_sram[0]:11 mux_tree_tapbuf_size9_1_sram[0]:10 0.004477679 +14 mux_tree_tapbuf_size9_1_sram[0]:11 mux_tree_tapbuf_size9_1_sram[0]:6 0.0003035715 +15 mux_tree_tapbuf_size9_1_sram[0]:5 mux_tree_tapbuf_size9_1_sram[0]:4 0.0001715117 +16 mux_tree_tapbuf_size9_1_sram[0]:6 mux_tree_tapbuf_size9_1_sram[0]:5 0.001680804 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006612873 //LENGTH 4.385 LUMPCC 0.0001529304 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_3_:X O *L 0 *C 125.755 47.260 +*I mux_right_track_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 126.790 44.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 126.753 44.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 126.085 44.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 126.040 44.585 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 126.040 47.215 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 126.040 47.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 125.755 47.260 + +*CAP +0 mux_right_track_8\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.055605e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.055605e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001211202 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001211202 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.221611e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.078839e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.646518e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.646518e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_3_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_8\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0005959822 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET optlc_net_122 0.01081641 //LENGTH 74.285 LUMPCC 0.001826804 DR + +*CONN +*I optlc_114:HI O *L 0 *C 72.680 77.180 +*I mux_top_track_2\/mux_l1_in_3_:A0 I *L 0.001631 *C 66.530 76.840 +*I mux_right_track_32\/mux_l2_in_1_:A0 I *L 0.001631 *C 89.530 71.740 +*I mux_right_track_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 96.890 75.480 +*I mux_top_track_12\/mux_l1_in_1_:A0 I *L 0.001631 *C 76.650 66.300 +*I mux_top_track_36\/mux_l2_in_0_:A0 I *L 0.005103 *C 72.680 97.400 +*I mux_top_track_38\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.375 86.020 +*N optlc_net_122:7 *C 78.338 86.020 +*N optlc_net_122:8 *C 72.718 97.400 +*N optlc_net_122:9 *C 74.475 97.350 +*N optlc_net_122:10 *C 74.520 97.195 +*N optlc_net_122:11 *C 74.520 86.065 +*N optlc_net_122:12 *C 74.565 86.020 +*N optlc_net_122:13 *C 76.820 86.020 +*N optlc_net_122:14 *C 76.820 85.975 +*N optlc_net_122:15 *C 76.650 66.300 +*N optlc_net_122:16 *C 76.820 66.300 +*N optlc_net_122:17 *C 76.820 66.345 +*N optlc_net_122:18 *C 96.853 75.480 +*N optlc_net_122:19 *C 91.585 75.480 +*N optlc_net_122:20 *C 91.540 75.480 +*N optlc_net_122:21 *C 91.532 75.480 +*N optlc_net_122:22 *C 89.530 71.740 +*N optlc_net_122:23 *C 89.700 71.740 +*N optlc_net_122:24 *C 89.700 71.785 +*N optlc_net_122:25 *C 89.700 75.422 +*N optlc_net_122:26 *C 89.700 75.480 +*N optlc_net_122:27 *C 76.828 75.480 +*N optlc_net_122:28 *C 76.820 75.480 +*N optlc_net_122:29 *C 76.820 76.840 +*N optlc_net_122:30 *C 76.775 76.840 +*N optlc_net_122:31 *C 66.568 76.840 +*N optlc_net_122:32 *C 72.680 76.840 +*N optlc_net_122:33 *C 72.680 77.180 + +*CAP +0 optlc_114:HI 1e-06 +1 mux_top_track_2\/mux_l1_in_3_:A0 1e-06 +2 mux_right_track_32\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_2\/mux_l2_in_3_:A0 1e-06 +4 mux_top_track_12\/mux_l1_in_1_:A0 1e-06 +5 mux_top_track_36\/mux_l2_in_0_:A0 1e-06 +6 mux_top_track_38\/mux_l1_in_1_:A0 1e-06 +7 optlc_net_122:7 0.0001025948 +8 optlc_net_122:8 0.00016173 +9 optlc_net_122:9 0.00016173 +10 optlc_net_122:10 0.0005381998 +11 optlc_net_122:11 0.0005381998 +12 optlc_net_122:12 0.0001450649 +13 optlc_net_122:13 0.0002814446 +14 optlc_net_122:14 0.0005129058 +15 optlc_net_122:15 4.763176e-05 +16 optlc_net_122:16 5.200823e-05 +17 optlc_net_122:17 0.0005057948 +18 optlc_net_122:18 0.0003266214 +19 optlc_net_122:19 0.0003266214 +20 optlc_net_122:20 4.10395e-05 +21 optlc_net_122:21 4.591231e-05 +22 optlc_net_122:22 5.639735e-05 +23 optlc_net_122:23 6.095764e-05 +24 optlc_net_122:24 0.0002365966 +25 optlc_net_122:25 0.0002365966 +26 optlc_net_122:26 0.0009788527 +27 optlc_net_122:27 0.0009329405 +28 optlc_net_122:28 0.0006171689 +29 optlc_net_122:29 0.00061665 +30 optlc_net_122:30 0.0002800676 +31 optlc_net_122:31 0.0004038014 +32 optlc_net_122:32 0.0007137994 +33 optlc_net_122:33 6.127619e-05 +34 optlc_net_122:27 right_top_grid_pin_45_[0]:13 0.0003215166 +35 optlc_net_122:26 right_top_grid_pin_45_[0]:13 0.0001083795 +36 optlc_net_122:26 right_top_grid_pin_45_[0]:14 0.0003215166 +37 optlc_net_122:21 right_top_grid_pin_45_[0]:14 0.0001083795 +38 optlc_net_122:27 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 5.077261e-06 +39 optlc_net_122:26 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 5.077261e-06 +40 optlc_net_122:19 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 0.0001125916 +41 optlc_net_122:18 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 0.0001125916 +42 optlc_net_122:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.000250441 +43 optlc_net_122:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.000250441 +44 optlc_net_122:27 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.016786e-06 +45 optlc_net_122:26 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.016786e-06 +46 optlc_net_122:26 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001083795 +47 optlc_net_122:21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001083795 + +*RES +0 optlc_114:HI optlc_net_122:33 0.152 +1 optlc_net_122:28 optlc_net_122:27 0.00341 +2 optlc_net_122:28 optlc_net_122:17 0.00815625 +3 optlc_net_122:27 optlc_net_122:26 0.002016691 +4 optlc_net_122:30 optlc_net_122:29 0.0045 +5 optlc_net_122:29 optlc_net_122:28 0.001214286 +6 optlc_net_122:29 optlc_net_122:14 0.00815625 +7 optlc_net_122:12 optlc_net_122:11 0.0045 +8 optlc_net_122:11 optlc_net_122:10 0.009937501 +9 optlc_net_122:9 optlc_net_122:8 0.001569196 +10 optlc_net_122:10 optlc_net_122:9 0.0045 +11 optlc_net_122:8 mux_top_track_36\/mux_l2_in_0_:A0 0.152 +12 optlc_net_122:13 optlc_net_122:12 0.002013393 +13 optlc_net_122:13 optlc_net_122:7 0.001354911 +14 optlc_net_122:14 optlc_net_122:13 0.0045 +15 optlc_net_122:25 optlc_net_122:24 0.003247768 +16 optlc_net_122:26 optlc_net_122:25 0.00341 +17 optlc_net_122:26 optlc_net_122:21 0.0002870917 +18 optlc_net_122:23 optlc_net_122:22 9.239132e-05 +19 optlc_net_122:24 optlc_net_122:23 0.0045 +20 optlc_net_122:22 mux_right_track_32\/mux_l2_in_1_:A0 0.152 +21 optlc_net_122:33 optlc_net_122:32 0.0003035715 +22 optlc_net_122:16 optlc_net_122:15 9.239131e-05 +23 optlc_net_122:17 optlc_net_122:16 0.0045 +24 optlc_net_122:15 mux_top_track_12\/mux_l1_in_1_:A0 0.152 +25 optlc_net_122:7 mux_top_track_38\/mux_l1_in_1_:A0 0.152 +26 optlc_net_122:20 optlc_net_122:19 0.0045 +27 optlc_net_122:21 optlc_net_122:20 0.00341 +28 optlc_net_122:19 optlc_net_122:18 0.004703125 +29 optlc_net_122:18 mux_right_track_2\/mux_l2_in_3_:A0 0.152 +30 optlc_net_122:31 mux_top_track_2\/mux_l1_in_3_:A0 0.152 +31 optlc_net_122:32 optlc_net_122:31 0.005457589 +32 optlc_net_122:32 optlc_net_122:30 0.00365625 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001087641 //LENGTH 8.690 LUMPCC 0.0001720629 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_1_:X O *L 0 *C 100.455 26.520 +*I mux_right_track_16\/mux_l3_in_0_:A0 I *L 0.001631 *C 99.535 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 99.535 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 99.820 33.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 99.820 33.615 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 99.820 26.565 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 99.865 26.520 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 100.418 26.520 + +*CAP +0 mux_right_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.062424e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.467048e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003403102 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003403102 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.383163e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.383163e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size7_3_sram[2]:7 2.136157e-06 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size7_3_sram[2]:6 2.136157e-06 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:8 8.389529e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:9 8.389529e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001548913 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006294644 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001123137 //LENGTH 8.100 LUMPCC 0.0001637686 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_1_:X O *L 0 *C 95.965 61.200 +*I mux_right_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 98.105 65.960 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 98.068 65.960 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 95.725 65.960 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 95.680 65.915 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 95.680 61.245 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 95.680 61.200 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 95.965 61.200 + +*CAP +0 mux_right_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001765651 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001765651 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002381256 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002381256 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.999585e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.799076e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:15 2.138877e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:14 2.138877e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:13 6.049552e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 6.049552e-05 + +*RES +0 mux_right_track_24\/mux_l2_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002091518 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002258117 //LENGTH 18.920 LUMPCC 0.0001714116 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 61.355 52.360 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 50.505 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 50.543 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 56.535 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 56.580 45.265 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 56.580 52.315 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 56.625 52.360 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 61.318 52.360 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000385105 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000385105 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003301042 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003301042 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003271434 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003271434 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_2_sram[1]:8 5.442167e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_2_sram[1]:9 3.128414e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_2_sram[1]:5 3.128414e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_2_sram[1]:9 5.442167e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005350447 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294644 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.004189732 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009336287 //LENGTH 7.805 LUMPCC 0.0001054777 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_1_:X O *L 0 *C 106.085 39.780 +*I mux_top_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 107.930 44.540 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 107.892 44.540 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 105.845 44.540 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 105.800 44.495 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 105.800 39.825 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 105.800 39.780 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 106.085 39.780 + +*CAP +0 mux_top_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001004271 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001004271 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002568698 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002568698 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.693155e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.462558e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size4_0_sram[2]:5 5.273887e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size4_0_sram[2]:4 5.273887e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001828125 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004169643 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001443842 //LENGTH 10.865 LUMPCC 0.0005532206 DR + +*CONN +*I mux_top_track_12\/mux_l1_in_0_:X O *L 0 *C 69.745 59.160 +*I mux_top_track_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 71.860 66.980 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 71.823 66.980 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 70.425 66.980 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 70.380 66.935 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 70.380 59.205 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 70.335 59.160 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 69.782 59.160 + +*CAP +0 mux_top_track_12\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_12\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.70823e-05 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.70823e-05 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003131893 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003131893 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.403894e-05 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.403894e-05 +8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_0_sram[1]:4 6.398191e-05 +9 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_0_sram[1]:5 6.398191e-05 +10 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:24 0.0002126284 +11 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:25 0.0002126284 + +*RES +0 mux_top_track_12\/mux_l1_in_0_:X mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_12\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000986282 //LENGTH 6.570 LUMPCC 0.0001805845 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_1_:X O *L 0 *C 56.865 56.100 +*I mux_top_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 59.515 58.820 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 59.478 58.820 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 56.625 58.820 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 56.580 58.775 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 56.580 56.145 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 56.580 56.100 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 56.865 56.100 + +*CAP +0 mux_top_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001606296 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001606296 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000169652 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000169652 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.090646e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.222766e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_2_sram[1]:3 7.104085e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_2_sram[1]:4 7.104085e-05 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_2_sram[1]:5 1.92514e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_2_sram[1]:9 1.92514e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002546875 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006170205 //LENGTH 5.240 LUMPCC 9.56045e-05 DR + +*CONN +*I mux_top_track_22\/mux_l1_in_1_:X O *L 0 *C 83.545 28.220 +*I mux_top_track_22\/mux_l2_in_0_:A0 I *L 0.001631 *C 88.495 28.220 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 88.458 28.220 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 83.583 28.220 + +*CAP +0 mux_top_track_22\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_22\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000259708 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000259708 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[17]:12 4.780225e-05 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[17]:11 4.780225e-05 + +*RES +0 mux_top_track_22\/mux_l1_in_1_:X mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_22\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004352679 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006243547 //LENGTH 4.380 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_1_:X O *L 0 *C 80.325 34.340 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 79.295 37.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 79.333 37.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 79.995 37.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 80.040 37.015 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 80.040 34.385 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 80.040 34.340 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 80.325 34.340 + +*CAP +0 mux_top_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.124534e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.124534e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001794076 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001794076 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.145507e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.959369e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005915179 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008138946 //LENGTH 6.420 LUMPCC 0 DR + +*CONN +*I mux_top_track_30\/mux_l2_in_0_:X O *L 0 *C 50.885 86.360 +*I mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 50.025 91.270 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 50.025 91.270 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 50.140 91.120 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 50.140 91.075 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 50.140 86.405 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 50.185 86.360 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 50.848 86.360 + +*CAP +0 mux_top_track_30\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.552367e-05 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.907942e-05 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002780066 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002780066 +6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.063918e-05 +7 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.063918e-05 + +*RES +0 mux_top_track_30\/mux_l2_in_0_:X mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.250001e-05 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_30/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 + +*END + +*D_NET optlc_net_126 0.01300382 //LENGTH 95.743 LUMPCC 0.001257449 DR + +*CONN +*I optlc_122:HI O *L 0 *C 69.460 42.160 +*I mux_top_track_28\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.575 31.620 +*I mux_top_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 54.915 55.420 +*I mux_top_track_14\/mux_l1_in_1_:A0 I *L 0.001631 *C 52.270 58.820 +*I mux_top_track_18\/mux_l1_in_1_:A0 I *L 0.001631 *C 62.390 38.760 +*I mux_top_track_20\/mux_l1_in_1_:A0 I *L 0.001631 *C 69.175 38.760 +*I mux_top_track_22\/mux_l1_in_1_:A0 I *L 0.001631 *C 81.595 28.220 +*I mux_top_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 78.375 33.660 +*I mux_top_track_4\/mux_l1_in_3_:A0 I *L 0.001631 *C 71.475 44.200 +*I mux_top_track_6\/mux_l1_in_3_:A0 I *L 0.001631 *C 84.355 44.200 +*N optlc_net_126:10 *C 84.318 44.200 +*N optlc_net_126:11 *C 71.513 44.200 +*N optlc_net_126:12 *C 71.300 44.540 +*N optlc_net_126:13 *C 69.045 44.540 +*N optlc_net_126:14 *C 69.000 44.495 +*N optlc_net_126:15 *C 78.338 33.660 +*N optlc_net_126:16 *C 81.558 28.220 +*N optlc_net_126:17 *C 77.785 28.220 +*N optlc_net_126:18 *C 77.740 28.265 +*N optlc_net_126:19 *C 77.740 33.615 +*N optlc_net_126:20 *C 77.740 33.660 +*N optlc_net_126:21 *C 69.045 33.660 +*N optlc_net_126:22 *C 69.000 33.705 +*N optlc_net_126:23 *C 69.050 38.760 +*N optlc_net_126:24 *C 62.390 38.760 +*N optlc_net_126:25 *C 52.308 58.820 +*N optlc_net_126:26 *C 54.695 58.820 +*N optlc_net_126:27 *C 54.740 58.775 +*N optlc_net_126:28 *C 54.740 55.465 +*N optlc_net_126:29 *C 54.740 55.420 +*N optlc_net_126:30 *C 54.953 55.420 +*N optlc_net_126:31 *C 62.515 55.420 +*N optlc_net_126:32 *C 62.560 55.375 +*N optlc_net_126:33 *C 64.538 31.620 +*N optlc_net_126:34 *C 62.605 31.620 +*N optlc_net_126:35 *C 62.560 31.665 +*N optlc_net_126:36 *C 62.560 38.760 +*N optlc_net_126:37 *C 62.605 38.760 +*N optlc_net_126:38 *C 68.955 38.760 +*N optlc_net_126:39 *C 69.000 38.760 +*N optlc_net_126:40 *C 69.000 42.160 +*N optlc_net_126:41 *C 69.045 42.160 +*N optlc_net_126:42 *C 69.422 42.160 + +*CAP +0 optlc_122:HI 1e-06 +1 mux_top_track_28\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_14\/mux_l1_in_1_:A0 1e-06 +4 mux_top_track_18\/mux_l1_in_1_:A0 1e-06 +5 mux_top_track_20\/mux_l1_in_1_:A0 1e-06 +6 mux_top_track_22\/mux_l1_in_1_:A0 1e-06 +7 mux_top_track_24\/mux_l1_in_1_:A0 1e-06 +8 mux_top_track_4\/mux_l1_in_3_:A0 1e-06 +9 mux_top_track_6\/mux_l1_in_3_:A0 1e-06 +10 optlc_net_126:10 0.0009301901 +11 optlc_net_126:11 0.0009555577 +12 optlc_net_126:12 0.0001999348 +13 optlc_net_126:13 0.0001745671 +14 optlc_net_126:14 0.0001378914 +15 optlc_net_126:15 4.373323e-05 +16 optlc_net_126:16 0.0002417253 +17 optlc_net_126:17 0.0002417253 +18 optlc_net_126:18 0.0003462522 +19 optlc_net_126:19 0.0003462522 +20 optlc_net_126:20 0.0004769107 +21 optlc_net_126:21 0.0003985517 +22 optlc_net_126:22 0.0003156727 +23 optlc_net_126:23 2.96229e-05 +24 optlc_net_126:24 5.04808e-05 +25 optlc_net_126:25 0.0001962677 +26 optlc_net_126:26 0.0001962677 +27 optlc_net_126:27 0.0002660497 +28 optlc_net_126:28 0.0002660497 +29 optlc_net_126:29 5.69027e-05 +30 optlc_net_126:30 0.0005385479 +31 optlc_net_126:31 0.0005189415 +32 optlc_net_126:32 0.0008995763 +33 optlc_net_126:33 0.0001401373 +34 optlc_net_126:34 0.0001401373 +35 optlc_net_126:35 0.000389648 +36 optlc_net_126:36 0.001320024 +37 optlc_net_126:37 0.0004545877 +38 optlc_net_126:38 0.0004622669 +39 optlc_net_126:39 0.0005372263 +40 optlc_net_126:40 0.0003581762 +41 optlc_net_126:41 5.325069e-05 +42 optlc_net_126:42 5.325069e-05 +43 optlc_net_126:21 chanx_left_in[8]:20 0.0003244225 +44 optlc_net_126:15 chanx_left_in[8]:19 2.866454e-05 +45 optlc_net_126:20 chanx_left_in[8]:19 0.0003244225 +46 optlc_net_126:20 chanx_left_in[8]:20 2.866454e-05 +47 optlc_net_126:32 mux_tree_tapbuf_size3_3_sram[1]:9 0.0001555588 +48 optlc_net_126:36 mux_tree_tapbuf_size3_3_sram[1]:9 4.595855e-05 +49 optlc_net_126:36 mux_tree_tapbuf_size3_3_sram[1]:10 0.0001555588 +50 optlc_net_126:35 mux_tree_tapbuf_size3_3_sram[1]:10 4.595855e-05 +51 optlc_net_126:34 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.412021e-05 +52 optlc_net_126:33 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.412021e-05 + +*RES +0 optlc_122:HI optlc_net_126:42 0.152 +1 optlc_net_126:31 optlc_net_126:30 0.006752232 +2 optlc_net_126:32 optlc_net_126:31 0.0045 +3 optlc_net_126:38 optlc_net_126:37 0.005669643 +4 optlc_net_126:38 optlc_net_126:23 8.482143e-05 +5 optlc_net_126:39 optlc_net_126:38 0.0045 +6 optlc_net_126:39 optlc_net_126:22 0.004513393 +7 optlc_net_126:13 optlc_net_126:12 0.002013393 +8 optlc_net_126:14 optlc_net_126:13 0.0045 +9 optlc_net_126:21 optlc_net_126:20 0.007763393 +10 optlc_net_126:22 optlc_net_126:21 0.0045 +11 optlc_net_126:37 optlc_net_126:36 0.0045 +12 optlc_net_126:37 optlc_net_126:24 0.0001168478 +13 optlc_net_126:36 optlc_net_126:35 0.006334822 +14 optlc_net_126:36 optlc_net_126:32 0.01483482 +15 optlc_net_126:10 mux_top_track_6\/mux_l1_in_3_:A0 0.152 +16 optlc_net_126:41 optlc_net_126:40 0.0045 +17 optlc_net_126:40 optlc_net_126:39 0.003035714 +18 optlc_net_126:40 optlc_net_126:14 0.002084821 +19 optlc_net_126:42 optlc_net_126:41 0.0003370536 +20 optlc_net_126:15 mux_top_track_24\/mux_l1_in_1_:A0 0.152 +21 optlc_net_126:20 optlc_net_126:19 0.0045 +22 optlc_net_126:20 optlc_net_126:15 0.0005334822 +23 optlc_net_126:19 optlc_net_126:18 0.004776786 +24 optlc_net_126:17 optlc_net_126:16 0.003368304 +25 optlc_net_126:18 optlc_net_126:17 0.0045 +26 optlc_net_126:16 mux_top_track_22\/mux_l1_in_1_:A0 0.152 +27 optlc_net_126:34 optlc_net_126:33 0.001725446 +28 optlc_net_126:35 optlc_net_126:34 0.0045 +29 optlc_net_126:33 mux_top_track_28\/mux_l2_in_0_:A0 0.152 +30 optlc_net_126:23 mux_top_track_20\/mux_l1_in_1_:A0 0.152 +31 optlc_net_126:24 mux_top_track_18\/mux_l1_in_1_:A0 0.152 +32 optlc_net_126:11 mux_top_track_4\/mux_l1_in_3_:A0 0.152 +33 optlc_net_126:11 optlc_net_126:10 0.01143304 +34 optlc_net_126:30 mux_top_track_16\/mux_l1_in_1_:A0 0.152 +35 optlc_net_126:30 optlc_net_126:29 0.0001154891 +36 optlc_net_126:29 optlc_net_126:28 0.0045 +37 optlc_net_126:28 optlc_net_126:27 0.002955358 +38 optlc_net_126:26 optlc_net_126:25 0.002131697 +39 optlc_net_126:27 optlc_net_126:26 0.0045 +40 optlc_net_126:25 mux_top_track_14\/mux_l1_in_1_:A0 0.152 +41 optlc_net_126:12 optlc_net_126:11 0.0003035715 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0004011616 //LENGTH 2.755 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 104.245 61.880 +*I mux_right_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 106.260 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 106.260 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 106.260 61.880 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 104.282 61.880 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.964083e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001843743 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001551465 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.001765625 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A1 0.152 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003206322 //LENGTH 24.160 LUMPCC 0.0008538786 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 39.735 65.960 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 30.725 52.700 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 30.763 52.700 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 32.660 52.700 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 32.660 52.360 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 38.135 52.360 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 38.180 52.405 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 38.180 65.915 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 38.225 65.960 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 39.698 65.960 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001277972 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001516519 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003647892 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003409346 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005581729 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0005581729 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001244624 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001244624 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size8_3_sram[0]:6 0.0002398757 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size8_3_sram[0]:5 0.0002398757 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001255347 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001255347 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.222541e-05 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.930362e-05 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.222541e-05 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.930362e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004888393 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0120625 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.001314732 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001694196 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005371202 //LENGTH 3.970 LUMPCC 0.0001124688 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_1_:X O *L 0 *C 81.595 71.740 +*I mux_right_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 77.915 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 77.953 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.558 71.740 + +*CAP +0 mux_right_track_32\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002113257 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002113257 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.623439e-05 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.623439e-05 + +*RES +0 mux_right_track_32\/mux_l1_in_1_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00321875 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00102314 //LENGTH 6.890 LUMPCC 0.0002502073 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_1_:X O *L 0 *C 11.675 57.800 +*I mux_left_track_33\/mux_l3_in_0_:A0 I *L 0.001631 *C 9.955 53.380 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 9.955 53.380 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 10.120 53.380 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 10.120 53.425 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 10.120 57.755 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 10.165 57.800 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 11.638 57.800 + +*CAP +0 mux_left_track_33\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.768177e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.213548e-05 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000196747 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000196747 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.000128811 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.000128811 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 optlc_net_123:10 5.958009e-06 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_123:15 5.958009e-06 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 optlc_net_123:15 0.0001191456 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_123:19 0.0001191456 + +*RES +0 mux_left_track_33\/mux_l2_in_1_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001314732 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866071 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.967391e-05 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005018776 //LENGTH 38.225 LUMPCC 0.00108648 DR + +*CONN +*I mux_left_track_1\/mux_l4_in_0_:X O *L 0 *C 28.695 60.520 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 14.415 39.310 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 14.415 39.310 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 14.260 39.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 14.260 39.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 14.258 39.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 13.815 39.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 13.800 39.448 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 13.800 57.113 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 13.820 57.120 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 28.513 57.120 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 28.520 57.178 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 28.520 60.475 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 28.520 60.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 28.695 60.520 + +*CAP +0 mux_left_track_1\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.071103e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.245487e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.562844e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.606463e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.606463e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0009488437 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0009488437 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0006184897 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0006184897 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0002225917 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0002225917 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 6.009408e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.942774e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[12]:23 0.0001353025 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_left_in[12]:24 0.0001353025 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_left_in[1]:12 0.0001294692 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[1]:13 0.0001294692 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 left_top_grid_pin_46_[0]:12 0.0001081095 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 left_top_grid_pin_46_[0]:17 0.000170359 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 left_top_grid_pin_46_[0]:17 0.0001081095 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 left_top_grid_pin_46_[0]:18 0.000170359 + +*RES +0 mux_left_track_1\/mux_l4_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 9.51087e-05 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.002944197 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.002301825 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00341 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.002767517 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 6.499219e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.00341 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.065218e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ropt_net_167 0.00113676 //LENGTH 7.650 LUMPCC 0.0001275706 DR + +*CONN +*I ropt_mt_inst_760:X O *L 0 *C 138.655 53.040 +*I ropt_mt_inst_794:A I *L 0.001767 *C 134.780 55.760 +*N ropt_net_167:2 *C 134.780 55.760 +*N ropt_net_167:3 *C 134.780 55.715 +*N ropt_net_167:4 *C 134.780 55.125 +*N ropt_net_167:5 *C 134.825 55.080 +*N ropt_net_167:6 *C 138.415 55.080 +*N ropt_net_167:7 *C 138.460 55.035 +*N ropt_net_167:8 *C 138.460 53.085 +*N ropt_net_167:9 *C 138.460 53.040 +*N ropt_net_167:10 *C 138.655 53.040 + +*CAP +0 ropt_mt_inst_760:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_167:2 3.971875e-05 +3 ropt_net_167:3 6.642036e-05 +4 ropt_net_167:4 6.642036e-05 +5 ropt_net_167:5 0.0002253324 +6 ropt_net_167:6 0.0002253324 +7 ropt_net_167:7 0.0001400867 +8 ropt_net_167:8 0.0001400867 +9 ropt_net_167:9 5.198779e-05 +10 ropt_net_167:10 5.180425e-05 +11 ropt_net_167:3 chanx_right_in[19]:5 1.270759e-06 +12 ropt_net_167:5 chanx_right_in[19]:2 6.251453e-05 +13 ropt_net_167:4 chanx_right_in[19]:4 1.270759e-06 +14 ropt_net_167:6 chanx_right_in[19]:3 6.251453e-05 + +*RES +0 ropt_mt_inst_760:X ropt_net_167:10 0.152 +1 ropt_net_167:2 ropt_mt_inst_794:A 0.152 +2 ropt_net_167:3 ropt_net_167:2 0.0045 +3 ropt_net_167:5 ropt_net_167:4 0.0045 +4 ropt_net_167:4 ropt_net_167:3 0.0005267857 +5 ropt_net_167:6 ropt_net_167:5 0.003205357 +6 ropt_net_167:7 ropt_net_167:6 0.0045 +7 ropt_net_167:9 ropt_net_167:8 0.0045 +8 ropt_net_167:8 ropt_net_167:7 0.001741071 +9 ropt_net_167:10 ropt_net_167:9 0.0001059783 + +*END + +*D_NET ropt_net_142 0.001168672 //LENGTH 11.730 LUMPCC 0 DR + +*CONN +*I BUFT_RR_76:X O *L 0 *C 127.420 19.720 +*I ropt_mt_inst_765:A I *L 0.001766 *C 134.780 20.400 +*N ropt_net_142:2 *C 134.743 20.400 +*N ropt_net_142:3 *C 126.085 20.400 +*N ropt_net_142:4 *C 126.040 20.355 +*N ropt_net_142:5 *C 126.040 19.765 +*N ropt_net_142:6 *C 126.085 19.720 +*N ropt_net_142:7 *C 127.383 19.720 + +*CAP +0 BUFT_RR_76:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_142:2 0.0004601157 +3 ropt_net_142:3 0.0004601157 +4 ropt_net_142:4 4.849032e-05 +5 ropt_net_142:5 4.849032e-05 +6 ropt_net_142:6 7.47298e-05 +7 ropt_net_142:7 7.47298e-05 + +*RES +0 BUFT_RR_76:X ropt_net_142:7 0.152 +1 ropt_net_142:7 ropt_net_142:6 0.001158482 +2 ropt_net_142:6 ropt_net_142:5 0.0045 +3 ropt_net_142:5 ropt_net_142:4 0.0005267857 +4 ropt_net_142:3 ropt_net_142:2 0.007729911 +5 ropt_net_142:4 ropt_net_142:3 0.0045 +6 ropt_net_142:2 ropt_mt_inst_765:A 0.152 + +*END + +*D_NET ropt_net_141 0.002533882 //LENGTH 17.185 LUMPCC 0.0007494885 DR + +*CONN +*I BUFT_P_94:X O *L 0 *C 12.420 42.500 +*I ropt_mt_inst_764:A I *L 0.001766 *C 3.220 47.600 +*N ropt_net_141:2 *C 3.183 47.600 +*N ropt_net_141:3 *C 2.805 47.600 +*N ropt_net_141:4 *C 2.760 47.555 +*N ropt_net_141:5 *C 2.760 46.977 +*N ropt_net_141:6 *C 2.768 46.920 +*N ropt_net_141:7 *C 5.973 46.920 +*N ropt_net_141:8 *C 5.980 46.920 +*N ropt_net_141:9 *C 5.980 42.885 +*N ropt_net_141:10 *C 6.025 42.840 +*N ropt_net_141:11 *C 12.420 42.840 +*N ropt_net_141:12 *C 12.420 42.500 + +*CAP +0 BUFT_P_94:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_141:2 4.159216e-05 +3 ropt_net_141:3 4.159216e-05 +4 ropt_net_141:4 5.077072e-05 +5 ropt_net_141:5 5.077072e-05 +6 ropt_net_141:6 9.087939e-05 +7 ropt_net_141:7 9.087939e-05 +8 ropt_net_141:8 0.0003042386 +9 ropt_net_141:9 0.0002664629 +10 ropt_net_141:10 0.0003750672 +11 ropt_net_141:11 0.0004060805 +12 ropt_net_141:12 6.405939e-05 +13 ropt_net_141:7 chanx_left_in[5]:28 5.856343e-05 +14 ropt_net_141:5 chanx_left_in[5]:30 7.372444e-06 +15 ropt_net_141:6 chanx_left_in[5]:29 5.856343e-05 +16 ropt_net_141:4 chanx_left_in[5]:31 7.372444e-06 +17 ropt_net_141:7 chanx_left_in[6]:20 0.0001976113 +18 ropt_net_141:6 chanx_left_in[6] 0.0001976113 +19 ropt_net_141:10 ropt_net_160:3 6.597456e-06 +20 ropt_net_141:10 ropt_net_160:7 0.0001045996 +21 ropt_net_141:11 ropt_net_160:4 6.597456e-06 +22 ropt_net_141:11 ropt_net_160:8 0.0001045996 + +*RES +0 BUFT_P_94:X ropt_net_141:12 0.152 +1 ropt_net_141:12 ropt_net_141:11 0.0003035715 +2 ropt_net_141:10 ropt_net_141:9 0.0045 +3 ropt_net_141:9 ropt_net_141:8 0.003602679 +4 ropt_net_141:8 ropt_net_141:7 0.00341 +5 ropt_net_141:7 ropt_net_141:6 0.0005021166 +6 ropt_net_141:5 ropt_net_141:4 0.000515625 +7 ropt_net_141:6 ropt_net_141:5 0.00341 +8 ropt_net_141:3 ropt_net_141:2 0.0003370536 +9 ropt_net_141:4 ropt_net_141:3 0.0045 +10 ropt_net_141:2 ropt_mt_inst_764:A 0.152 +11 ropt_net_141:11 ropt_net_141:10 0.005709821 + +*END + +*D_NET chanx_right_in[17] 0.02185823 //LENGTH 178.745 LUMPCC 0.004593416 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 140.450 63.920 +*I mux_top_track_22\/mux_l1_in_0_:A0 I *L 0.001631 *C 84.815 33.660 +*I mux_left_track_17\/mux_l1_in_2_:A1 I *L 0.00198 *C 33.580 34.340 +*I BUFT_P_108:A I *L 0.001776 *C 16.100 14.960 +*N chanx_right_in[17]:4 *C 16.137 14.960 +*N chanx_right_in[17]:5 *C 17.435 14.960 +*N chanx_right_in[17]:6 *C 17.480 15.005 +*N chanx_right_in[17]:7 *C 17.480 19.675 +*N chanx_right_in[17]:8 *C 17.525 19.720 +*N chanx_right_in[17]:9 *C 28.665 19.720 +*N chanx_right_in[17]:10 *C 28.585 19.765 +*N chanx_right_in[17]:11 *C 28.520 20.355 +*N chanx_right_in[17]:12 *C 28.565 20.400 +*N chanx_right_in[17]:13 *C 33.995 20.400 +*N chanx_right_in[17]:14 *C 34.040 20.445 +*N chanx_right_in[17]:15 *C 33.580 34.340 +*N chanx_right_in[17]:16 *C 33.580 34.295 +*N chanx_right_in[17]:17 *C 33.580 33.320 +*N chanx_right_in[17]:18 *C 34.040 33.263 +*N chanx_right_in[17]:19 *C 34.047 33.320 +*N chanx_right_in[17]:20 *C 84.815 33.660 +*N chanx_right_in[17]:21 *C 85.100 33.660 +*N chanx_right_in[17]:22 *C 85.100 33.660 +*N chanx_right_in[17]:23 *C 85.100 33.320 +*N chanx_right_in[17]:24 *C 85.100 33.320 +*N chanx_right_in[17]:25 *C 138.900 33.320 +*N chanx_right_in[17]:26 *C 138.920 33.328 +*N chanx_right_in[17]:27 *C 138.920 63.913 +*N chanx_right_in[17]:28 *C 138.940 63.920 + +*CAP +0 chanx_right_in[17] 0.0001110356 +1 mux_top_track_22\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_17\/mux_l1_in_2_:A1 1e-06 +3 BUFT_P_108:A 1e-06 +4 chanx_right_in[17]:4 9.206343e-05 +5 chanx_right_in[17]:5 9.206343e-05 +6 chanx_right_in[17]:6 0.000236748 +7 chanx_right_in[17]:7 0.000236748 +8 chanx_right_in[17]:8 0.0006505828 +9 chanx_right_in[17]:9 0.0006505828 +10 chanx_right_in[17]:10 4.595106e-05 +11 chanx_right_in[17]:11 4.595106e-05 +12 chanx_right_in[17]:12 0.00029325 +13 chanx_right_in[17]:13 0.00029325 +14 chanx_right_in[17]:14 0.0006602841 +15 chanx_right_in[17]:15 3.292222e-05 +16 chanx_right_in[17]:16 7.934251e-05 +17 chanx_right_in[17]:17 8.814369e-05 +18 chanx_right_in[17]:18 0.0006690852 +19 chanx_right_in[17]:19 0.002513645 +20 chanx_right_in[17]:20 4.270037e-05 +21 chanx_right_in[17]:21 4.710727e-05 +22 chanx_right_in[17]:22 5.653374e-05 +23 chanx_right_in[17]:23 6.077456e-05 +24 chanx_right_in[17]:24 0.00473914 +25 chanx_right_in[17]:25 0.002225495 +26 chanx_right_in[17]:26 0.00159369 +27 chanx_right_in[17]:27 0.00159369 +28 chanx_right_in[17]:28 0.0001110356 +29 chanx_right_in[17]:25 chanx_right_in[6] 0.0005051129 +30 chanx_right_in[17]:25 chanx_right_in[6]:21 5.269885e-06 +31 chanx_right_in[17]:25 chanx_right_in[6]:27 5.680431e-06 +32 chanx_right_in[17]:24 chanx_right_in[6]:20 1.967811e-05 +33 chanx_right_in[17]:24 chanx_right_in[6]:21 2.088537e-06 +34 chanx_right_in[17]:24 chanx_right_in[6]:26 5.680431e-06 +35 chanx_right_in[17]:24 chanx_right_in[6]:29 0.0005051129 +36 chanx_right_in[17]:19 chanx_right_in[6]:19 1.440822e-05 +37 chanx_right_in[17]:19 chanx_right_in[6]:20 2.088537e-06 +38 chanx_right_in[17]:25 chanx_left_in[8]:9 0.0002035983 +39 chanx_right_in[17]:25 chanx_left_in[8]:19 5.100426e-06 +40 chanx_right_in[17]:24 chanx_left_in[8]:10 0.0002035983 +41 chanx_right_in[17]:24 chanx_left_in[8]:19 5.166171e-06 +42 chanx_right_in[17]:24 chanx_left_in[8]:20 5.100426e-06 +43 chanx_right_in[17]:21 chanx_left_in[8]:19 1.289695e-05 +44 chanx_right_in[17]:20 chanx_left_in[8]:20 1.289695e-05 +45 chanx_right_in[17]:18 chanx_left_in[8]:20 2.63093e-05 +46 chanx_right_in[17]:19 chanx_left_in[8]:20 5.166171e-06 +47 chanx_right_in[17]:17 chanx_left_in[8]:21 2.63093e-05 +48 chanx_right_in[17]:24 prog_clk[0]:423 6.010215e-05 +49 chanx_right_in[17]:24 prog_clk[0]:433 3.567945e-05 +50 chanx_right_in[17]:24 prog_clk[0]:403 6.873019e-05 +51 chanx_right_in[17]:24 prog_clk[0]:428 3.313301e-05 +52 chanx_right_in[17]:24 prog_clk[0]:371 4.555016e-05 +53 chanx_right_in[17]:24 prog_clk[0]:378 6.017816e-05 +54 chanx_right_in[17]:24 prog_clk[0]:418 2.590567e-05 +55 chanx_right_in[17]:24 prog_clk[0]:441 6.275823e-05 +56 chanx_right_in[17]:24 prog_clk[0]:412 3.797585e-05 +57 chanx_right_in[17]:24 prog_clk[0]:407 4.873692e-05 +58 chanx_right_in[17]:19 prog_clk[0]:463 6.275823e-05 +59 chanx_right_in[17]:19 prog_clk[0]:404 6.873019e-05 +60 chanx_right_in[17]:19 prog_clk[0]:423 2.590567e-05 +61 chanx_right_in[17]:19 prog_clk[0]:433 3.313301e-05 +62 chanx_right_in[17]:19 prog_clk[0]:434 3.567945e-05 +63 chanx_right_in[17]:19 prog_clk[0]:428 6.010215e-05 +64 chanx_right_in[17]:19 prog_clk[0]:412 4.873692e-05 +65 chanx_right_in[17]:19 prog_clk[0]:407 4.555016e-05 +66 chanx_right_in[17]:19 prog_clk[0]:413 3.797585e-05 +67 chanx_right_in[17]:19 prog_clk[0]:379 6.017816e-05 +68 chanx_right_in[17]:24 chany_top_in[3]:7 0.0002056266 +69 chanx_right_in[17]:24 chany_top_in[3]:12 0.0001063263 +70 chanx_right_in[17]:19 chany_top_in[3]:11 0.0001063263 +71 chanx_right_in[17]:19 chany_top_in[3]:12 0.0002056266 +72 chanx_right_in[17]:25 chanx_right_out[8] 0.0007203743 +73 chanx_right_in[17]:24 chanx_right_out[8]:2 0.0007203743 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:28 0.0002365667 +1 chanx_right_in[17]:25 chanx_right_in[17]:24 0.008428666 +2 chanx_right_in[17]:26 chanx_right_in[17]:25 0.00341 +3 chanx_right_in[17]:28 chanx_right_in[17]:27 0.00341 +4 chanx_right_in[17]:27 chanx_right_in[17]:26 0.00479165 +5 chanx_right_in[17]:13 chanx_right_in[17]:12 0.004848214 +6 chanx_right_in[17]:14 chanx_right_in[17]:13 0.0045 +7 chanx_right_in[17]:12 chanx_right_in[17]:11 0.0045 +8 chanx_right_in[17]:11 chanx_right_in[17]:10 0.0005267857 +9 chanx_right_in[17]:9 chanx_right_in[17]:8 0.009946428 +10 chanx_right_in[17]:10 chanx_right_in[17]:9 0.0045 +11 chanx_right_in[17]:8 chanx_right_in[17]:7 0.0045 +12 chanx_right_in[17]:7 chanx_right_in[17]:6 0.004169643 +13 chanx_right_in[17]:5 chanx_right_in[17]:4 0.001158482 +14 chanx_right_in[17]:6 chanx_right_in[17]:5 0.0045 +15 chanx_right_in[17]:4 BUFT_P_108:A 0.152 +16 chanx_right_in[17]:15 mux_left_track_17\/mux_l1_in_2_:A1 0.152 +17 chanx_right_in[17]:16 chanx_right_in[17]:15 0.0045 +18 chanx_right_in[17]:23 chanx_right_in[17]:22 0.0001634615 +19 chanx_right_in[17]:24 chanx_right_in[17]:23 0.00341 +20 chanx_right_in[17]:24 chanx_right_in[17]:19 0.007998224 +21 chanx_right_in[17]:21 chanx_right_in[17]:20 0.0001548913 +22 chanx_right_in[17]:22 chanx_right_in[17]:21 0.0045 +23 chanx_right_in[17]:20 mux_top_track_22\/mux_l1_in_0_:A0 0.152 +24 chanx_right_in[17]:18 chanx_right_in[17]:17 0.0004107143 +25 chanx_right_in[17]:18 chanx_right_in[17]:14 0.0114442 +26 chanx_right_in[17]:19 chanx_right_in[17]:18 0.00341 +27 chanx_right_in[17]:17 chanx_right_in[17]:16 0.0008705358 + +*END + +*D_NET right_top_grid_pin_48_[0] 0.007811469 //LENGTH 55.112 LUMPCC 0.002718905 DR + +*CONN +*P right_top_grid_pin_48_[0] I *L 0.29796 *C 135.700 74.835 +*I mux_right_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 114.255 71.400 +*I mux_right_track_4\/mux_l1_in_4_:A0 I *L 0.001631 *C 106.435 66.300 +*I mux_right_track_24\/mux_l1_in_2_:A1 I *L 0.00198 *C 97.885 61.540 +*N right_top_grid_pin_48_[0]:4 *C 97.922 61.540 +*N right_top_grid_pin_48_[0]:5 *C 98.855 61.540 +*N right_top_grid_pin_48_[0]:6 *C 98.900 61.585 +*N right_top_grid_pin_48_[0]:7 *C 98.900 64.543 +*N right_top_grid_pin_48_[0]:8 *C 98.907 64.600 +*N right_top_grid_pin_48_[0]:9 *C 106.253 64.600 +*N right_top_grid_pin_48_[0]:10 *C 106.260 64.657 +*N right_top_grid_pin_48_[0]:11 *C 106.260 66.255 +*N right_top_grid_pin_48_[0]:12 *C 106.260 66.300 +*N right_top_grid_pin_48_[0]:13 *C 106.473 66.300 +*N right_top_grid_pin_48_[0]:14 *C 110.400 66.300 +*N right_top_grid_pin_48_[0]:15 *C 110.400 66.640 +*N right_top_grid_pin_48_[0]:16 *C 114.495 66.640 +*N right_top_grid_pin_48_[0]:17 *C 114.540 66.685 +*N right_top_grid_pin_48_[0]:18 *C 114.255 71.400 +*N right_top_grid_pin_48_[0]:19 *C 114.540 71.400 +*N right_top_grid_pin_48_[0]:20 *C 114.540 71.400 +*N right_top_grid_pin_48_[0]:21 *C 114.540 74.415 +*N right_top_grid_pin_48_[0]:22 *C 114.540 74.460 +*N right_top_grid_pin_48_[0]:23 *C 114.540 74.800 +*N right_top_grid_pin_48_[0]:24 *C 128.340 74.800 +*N right_top_grid_pin_48_[0]:25 *C 128.340 74.460 +*N right_top_grid_pin_48_[0]:26 *C 135.655 74.460 +*N right_top_grid_pin_48_[0]:27 *C 135.700 74.505 + +*CAP +0 right_top_grid_pin_48_[0] 3.692746e-05 +1 mux_right_track_0\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_4\/mux_l1_in_4_:A0 1e-06 +3 mux_right_track_24\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_48_[0]:4 9.285148e-05 +5 right_top_grid_pin_48_[0]:5 9.285148e-05 +6 right_top_grid_pin_48_[0]:6 0.0001951703 +7 right_top_grid_pin_48_[0]:7 0.0001951703 +8 right_top_grid_pin_48_[0]:8 0.0003494439 +9 right_top_grid_pin_48_[0]:9 0.0003494439 +10 right_top_grid_pin_48_[0]:10 0.0001242314 +11 right_top_grid_pin_48_[0]:11 0.0001242314 +12 right_top_grid_pin_48_[0]:12 5.270083e-05 +13 right_top_grid_pin_48_[0]:13 0.0002278176 +14 right_top_grid_pin_48_[0]:14 0.00023634 +15 right_top_grid_pin_48_[0]:15 0.0002955476 +16 right_top_grid_pin_48_[0]:16 0.0002678377 +17 right_top_grid_pin_48_[0]:17 0.0003180219 +18 right_top_grid_pin_48_[0]:18 5.131616e-05 +19 right_top_grid_pin_48_[0]:19 5.593308e-05 +20 right_top_grid_pin_48_[0]:20 0.000532348 +21 right_top_grid_pin_48_[0]:21 0.0001814894 +22 right_top_grid_pin_48_[0]:22 6.396563e-05 +23 right_top_grid_pin_48_[0]:23 0.0004157892 +24 right_top_grid_pin_48_[0]:24 0.0004091263 +25 right_top_grid_pin_48_[0]:25 0.0002033747 +26 right_top_grid_pin_48_[0]:26 0.000180707 +27 right_top_grid_pin_48_[0]:27 3.692746e-05 +28 right_top_grid_pin_48_[0]:26 right_top_grid_pin_44_[0]:15 8.151316e-05 +29 right_top_grid_pin_48_[0]:23 right_top_grid_pin_44_[0]:14 0.0002550397 +30 right_top_grid_pin_48_[0]:24 right_top_grid_pin_44_[0]:15 0.0002550397 +31 right_top_grid_pin_48_[0]:25 right_top_grid_pin_44_[0]:14 8.151316e-05 +32 right_top_grid_pin_48_[0] right_top_grid_pin_45_[0] 2.835458e-07 +33 right_top_grid_pin_48_[0]:26 right_top_grid_pin_45_[0]:23 0.0002904494 +34 right_top_grid_pin_48_[0]:27 right_top_grid_pin_45_[0]:24 2.835458e-07 +35 right_top_grid_pin_48_[0]:23 right_top_grid_pin_45_[0]:22 0.0002344913 +36 right_top_grid_pin_48_[0]:24 right_top_grid_pin_45_[0]:23 0.0002344913 +37 right_top_grid_pin_48_[0]:25 right_top_grid_pin_45_[0]:22 0.0002904494 +38 right_top_grid_pin_48_[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0004124122 +39 right_top_grid_pin_48_[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0004124122 +40 right_top_grid_pin_48_[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.144304e-05 +41 right_top_grid_pin_48_[0]:16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.820098e-06 +42 right_top_grid_pin_48_[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.144304e-05 +43 right_top_grid_pin_48_[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.820098e-06 + +*RES +0 right_top_grid_pin_48_[0] right_top_grid_pin_48_[0]:27 0.0002946429 +1 right_top_grid_pin_48_[0]:22 right_top_grid_pin_48_[0]:21 0.0045 +2 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:20 0.002691964 +3 right_top_grid_pin_48_[0]:26 right_top_grid_pin_48_[0]:25 0.00653125 +4 right_top_grid_pin_48_[0]:27 right_top_grid_pin_48_[0]:26 0.0045 +5 right_top_grid_pin_48_[0]:12 right_top_grid_pin_48_[0]:11 0.0045 +6 right_top_grid_pin_48_[0]:11 right_top_grid_pin_48_[0]:10 0.001426339 +7 right_top_grid_pin_48_[0]:10 right_top_grid_pin_48_[0]:9 0.00341 +8 right_top_grid_pin_48_[0]:9 right_top_grid_pin_48_[0]:8 0.001150717 +9 right_top_grid_pin_48_[0]:7 right_top_grid_pin_48_[0]:6 0.002640625 +10 right_top_grid_pin_48_[0]:8 right_top_grid_pin_48_[0]:7 0.00341 +11 right_top_grid_pin_48_[0]:5 right_top_grid_pin_48_[0]:4 0.0008325893 +12 right_top_grid_pin_48_[0]:6 right_top_grid_pin_48_[0]:5 0.0045 +13 right_top_grid_pin_48_[0]:4 mux_right_track_24\/mux_l1_in_2_:A1 0.152 +14 right_top_grid_pin_48_[0]:13 mux_right_track_4\/mux_l1_in_4_:A0 0.152 +15 right_top_grid_pin_48_[0]:13 right_top_grid_pin_48_[0]:12 0.0001154891 +16 right_top_grid_pin_48_[0]:19 right_top_grid_pin_48_[0]:18 0.0001548913 +17 right_top_grid_pin_48_[0]:20 right_top_grid_pin_48_[0]:19 0.0045 +18 right_top_grid_pin_48_[0]:20 right_top_grid_pin_48_[0]:17 0.004209822 +19 right_top_grid_pin_48_[0]:18 mux_right_track_0\/mux_l2_in_1_:A0 0.152 +20 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:15 0.00365625 +21 right_top_grid_pin_48_[0]:17 right_top_grid_pin_48_[0]:16 0.0045 +22 right_top_grid_pin_48_[0]:14 right_top_grid_pin_48_[0]:13 0.003506696 +23 right_top_grid_pin_48_[0]:15 right_top_grid_pin_48_[0]:14 0.0003035715 +24 right_top_grid_pin_48_[0]:23 right_top_grid_pin_48_[0]:22 0.0003035714 +25 right_top_grid_pin_48_[0]:24 right_top_grid_pin_48_[0]:23 0.01232143 +26 right_top_grid_pin_48_[0]:25 right_top_grid_pin_48_[0]:24 0.0003035715 + +*END + +*D_NET chanx_left_in[11] 0.007054039 //LENGTH 52.900 LUMPCC 0.00226515 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 69.360 +*I mux_top_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 34.205 87.720 +*N chanx_left_in[11]:2 *C 34.168 87.720 +*N chanx_left_in[11]:3 *C 29.945 87.720 +*N chanx_left_in[11]:4 *C 29.900 87.720 +*N chanx_left_in[11]:5 *C 28.980 87.720 +*N chanx_left_in[11]:6 *C 28.980 74.505 +*N chanx_left_in[11]:7 *C 28.935 74.460 +*N chanx_left_in[11]:8 *C 17.985 74.460 +*N chanx_left_in[11]:9 *C 17.940 74.415 +*N chanx_left_in[11]:10 *C 17.940 69.418 +*N chanx_left_in[11]:11 *C 17.933 69.360 + +*CAP +0 chanx_left_in[11] 0.0007488769 +1 mux_top_track_32\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[11]:2 0.0002781644 +3 chanx_left_in[11]:3 0.0002781644 +4 chanx_left_in[11]:4 6.873748e-05 +5 chanx_left_in[11]:5 0.0006796268 +6 chanx_left_in[11]:6 0.0006349618 +7 chanx_left_in[11]:7 0.0003700359 +8 chanx_left_in[11]:8 0.0003700359 +9 chanx_left_in[11]:9 0.0003052042 +10 chanx_left_in[11]:10 0.0003052042 +11 chanx_left_in[11]:11 0.0007488769 +12 chanx_left_in[11]:7 chanx_left_in[9]:28 0.0004305048 +13 chanx_left_in[11]:8 chanx_left_in[9]:29 0.0004305048 +14 chanx_left_in[11] chanx_left_in[0] 7.3478e-05 +15 chanx_left_in[11] chanx_left_in[0]:7 0.0006285923 +16 chanx_left_in[11]:11 chanx_left_in[0]:6 0.0006285923 +17 chanx_left_in[11]:11 chanx_left_in[0]:10 7.3478e-05 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:11 0.002616725 +1 chanx_left_in[11]:2 mux_top_track_32\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[11]:3 chanx_left_in[11]:2 0.00377009 +3 chanx_left_in[11]:4 chanx_left_in[11]:3 0.0045 +4 chanx_left_in[11]:7 chanx_left_in[11]:6 0.0045 +5 chanx_left_in[11]:6 chanx_left_in[11]:5 0.01179911 +6 chanx_left_in[11]:8 chanx_left_in[11]:7 0.009776787 +7 chanx_left_in[11]:9 chanx_left_in[11]:8 0.0045 +8 chanx_left_in[11]:10 chanx_left_in[11]:9 0.004462053 +9 chanx_left_in[11]:11 chanx_left_in[11]:10 0.00341 +10 chanx_left_in[11]:5 chanx_left_in[11]:4 0.0008214285 + +*END + +*D_NET left_top_grid_pin_43_[0] 0.009083881 //LENGTH 74.650 LUMPCC 0.001731034 DR + +*CONN +*P left_top_grid_pin_43_[0] I *L 0.29796 *C 29.825 91.800 +*I mux_left_track_5\/mux_l1_in_3_:A1 I *L 0.00198 *C 25.665 50.660 +*I mux_left_track_17\/mux_l1_in_2_:A0 I *L 0.001631 *C 33.295 33.660 +*I mux_left_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.130 65.960 +*N left_top_grid_pin_43_[0]:4 *C 25.168 65.960 +*N left_top_grid_pin_43_[0]:5 *C 33.258 33.660 +*N left_top_grid_pin_43_[0]:6 *C 32.245 33.660 +*N left_top_grid_pin_43_[0]:7 *C 32.200 33.705 +*N left_top_grid_pin_43_[0]:8 *C 32.200 47.555 +*N left_top_grid_pin_43_[0]:9 *C 32.155 47.600 +*N left_top_grid_pin_43_[0]:10 *C 26.725 47.600 +*N left_top_grid_pin_43_[0]:11 *C 26.680 47.645 +*N left_top_grid_pin_43_[0]:12 *C 25.703 50.660 +*N left_top_grid_pin_43_[0]:13 *C 26.680 50.660 +*N left_top_grid_pin_43_[0]:14 *C 26.680 51.000 +*N left_top_grid_pin_43_[0]:15 *C 26.680 51.000 +*N left_top_grid_pin_43_[0]:16 *C 26.680 65.915 +*N left_top_grid_pin_43_[0]:17 *C 26.680 65.960 +*N left_top_grid_pin_43_[0]:18 *C 29.855 65.960 +*N left_top_grid_pin_43_[0]:19 *C 29.900 66.005 +*N left_top_grid_pin_43_[0]:20 *C 29.900 83.640 +*N left_top_grid_pin_43_[0]:21 *C 30.360 83.640 +*N left_top_grid_pin_43_[0]:22 *C 30.360 91.743 +*N left_top_grid_pin_43_[0]:23 *C 30.353 91.800 + +*CAP +0 left_top_grid_pin_43_[0] 5.199261e-05 +1 mux_left_track_5\/mux_l1_in_3_:A1 1e-06 +2 mux_left_track_17\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_3\/mux_l2_in_1_:A0 1e-06 +4 left_top_grid_pin_43_[0]:4 0.0001139037 +5 left_top_grid_pin_43_[0]:5 0.0001062039 +6 left_top_grid_pin_43_[0]:6 0.0001062039 +7 left_top_grid_pin_43_[0]:7 0.0006296215 +8 left_top_grid_pin_43_[0]:8 0.0006296215 +9 left_top_grid_pin_43_[0]:9 0.0003213059 +10 left_top_grid_pin_43_[0]:10 0.0003213059 +11 left_top_grid_pin_43_[0]:11 0.0002025003 +12 left_top_grid_pin_43_[0]:12 0.0001071813 +13 left_top_grid_pin_43_[0]:13 0.0001377324 +14 left_top_grid_pin_43_[0]:14 6.66279e-05 +15 left_top_grid_pin_43_[0]:15 0.001040537 +16 left_top_grid_pin_43_[0]:16 0.0008039772 +17 left_top_grid_pin_43_[0]:17 0.0003582842 +18 left_top_grid_pin_43_[0]:18 0.00021221 +19 left_top_grid_pin_43_[0]:19 0.0006768811 +20 left_top_grid_pin_43_[0]:20 0.0007026768 +21 left_top_grid_pin_43_[0]:21 0.0003674419 +22 left_top_grid_pin_43_[0]:22 0.0003416462 +23 left_top_grid_pin_43_[0]:23 5.199261e-05 +24 left_top_grid_pin_43_[0]:19 prog_clk[0]:524 0.0001214584 +25 left_top_grid_pin_43_[0]:19 prog_clk[0]:549 2.79717e-07 +26 left_top_grid_pin_43_[0]:19 prog_clk[0]:553 0.0001028979 +27 left_top_grid_pin_43_[0]:19 prog_clk[0]:559 6.362403e-05 +28 left_top_grid_pin_43_[0]:19 prog_clk[0]:563 0.0001688208 +29 left_top_grid_pin_43_[0]:19 prog_clk[0]:567 2.533648e-07 +30 left_top_grid_pin_43_[0]:22 prog_clk[0]:588 1.14839e-05 +31 left_top_grid_pin_43_[0]:22 prog_clk[0]:592 2.996796e-05 +32 left_top_grid_pin_43_[0]:22 prog_clk[0]:593 1.707355e-06 +33 left_top_grid_pin_43_[0]:8 prog_clk[0]:461 7.930815e-07 +34 left_top_grid_pin_43_[0]:8 prog_clk[0]:478 0.0001858508 +35 left_top_grid_pin_43_[0]:8 prog_clk[0]:479 4.1245e-05 +36 left_top_grid_pin_43_[0]:7 prog_clk[0]:460 7.930815e-07 +37 left_top_grid_pin_43_[0]:7 prog_clk[0]:464 0.0001858508 +38 left_top_grid_pin_43_[0]:7 prog_clk[0]:478 4.1245e-05 +39 left_top_grid_pin_43_[0]:16 prog_clk[0]:518 8.82924e-09 +40 left_top_grid_pin_43_[0]:16 prog_clk[0]:524 1.559832e-07 +41 left_top_grid_pin_43_[0]:15 prog_clk[0]:497 8.82924e-09 +42 left_top_grid_pin_43_[0]:15 prog_clk[0]:518 1.559832e-07 +43 left_top_grid_pin_43_[0]:20 prog_clk[0]:550 2.79717e-07 +44 left_top_grid_pin_43_[0]:20 prog_clk[0]:553 0.0001214584 +45 left_top_grid_pin_43_[0]:20 prog_clk[0]:559 0.0001028979 +46 left_top_grid_pin_43_[0]:20 prog_clk[0]:563 6.362403e-05 +47 left_top_grid_pin_43_[0]:20 prog_clk[0]:564 0.0001688208 +48 left_top_grid_pin_43_[0]:20 prog_clk[0]:588 2.533648e-07 +49 left_top_grid_pin_43_[0]:21 prog_clk[0]:567 1.14839e-05 +50 left_top_grid_pin_43_[0]:21 prog_clk[0]:588 2.996796e-05 +51 left_top_grid_pin_43_[0]:21 prog_clk[0]:592 1.707355e-06 +52 left_top_grid_pin_43_[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 7.828039e-05 +53 left_top_grid_pin_43_[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.828039e-05 +54 left_top_grid_pin_43_[0]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.868921e-05 +55 left_top_grid_pin_43_[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.868921e-05 + +*RES +0 left_top_grid_pin_43_[0] left_top_grid_pin_43_[0]:23 8.264167e-05 +1 left_top_grid_pin_43_[0]:18 left_top_grid_pin_43_[0]:17 0.002834822 +2 left_top_grid_pin_43_[0]:19 left_top_grid_pin_43_[0]:18 0.0045 +3 left_top_grid_pin_43_[0]:22 left_top_grid_pin_43_[0]:21 0.007234375 +4 left_top_grid_pin_43_[0]:23 left_top_grid_pin_43_[0]:22 0.00341 +5 left_top_grid_pin_43_[0]:10 left_top_grid_pin_43_[0]:9 0.004848214 +6 left_top_grid_pin_43_[0]:11 left_top_grid_pin_43_[0]:10 0.0045 +7 left_top_grid_pin_43_[0]:9 left_top_grid_pin_43_[0]:8 0.0045 +8 left_top_grid_pin_43_[0]:8 left_top_grid_pin_43_[0]:7 0.01236607 +9 left_top_grid_pin_43_[0]:6 left_top_grid_pin_43_[0]:5 0.0009040179 +10 left_top_grid_pin_43_[0]:7 left_top_grid_pin_43_[0]:6 0.0045 +11 left_top_grid_pin_43_[0]:5 mux_left_track_17\/mux_l1_in_2_:A0 0.152 +12 left_top_grid_pin_43_[0]:17 left_top_grid_pin_43_[0]:16 0.0045 +13 left_top_grid_pin_43_[0]:17 left_top_grid_pin_43_[0]:4 0.001350446 +14 left_top_grid_pin_43_[0]:16 left_top_grid_pin_43_[0]:15 0.01331696 +15 left_top_grid_pin_43_[0]:14 left_top_grid_pin_43_[0]:13 0.0003035715 +16 left_top_grid_pin_43_[0]:15 left_top_grid_pin_43_[0]:14 0.0045 +17 left_top_grid_pin_43_[0]:15 left_top_grid_pin_43_[0]:11 0.002995536 +18 left_top_grid_pin_43_[0]:12 mux_left_track_5\/mux_l1_in_3_:A1 0.152 +19 left_top_grid_pin_43_[0]:4 mux_left_track_3\/mux_l2_in_1_:A0 0.152 +20 left_top_grid_pin_43_[0]:13 left_top_grid_pin_43_[0]:12 0.0008727679 +21 left_top_grid_pin_43_[0]:20 left_top_grid_pin_43_[0]:19 0.01574554 +22 left_top_grid_pin_43_[0]:21 left_top_grid_pin_43_[0]:20 0.0004107143 + +*END + +*D_NET chany_top_out[3] 0.002321539 //LENGTH 19.580 LUMPCC 0 DR + +*CONN +*I mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 84.640 96.900 +*P chany_top_out[3] O *L 0.7423 *C 71.300 102.035 +*N chany_top_out[3]:2 *C 71.300 101.705 +*N chany_top_out[3]:3 *C 71.345 101.660 +*N chany_top_out[3]:4 *C 84.135 101.660 +*N chany_top_out[3]:5 *C 84.180 101.615 +*N chany_top_out[3]:6 *C 84.180 96.945 +*N chany_top_out[3]:7 *C 84.225 96.900 +*N chany_top_out[3]:8 *C 84.603 96.900 + +*CAP +0 mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[3] 3.588196e-05 +2 chany_top_out[3]:2 3.588196e-05 +3 chany_top_out[3]:3 0.0007817619 +4 chany_top_out[3]:4 0.0007817619 +5 chany_top_out[3]:5 0.0002980594 +6 chany_top_out[3]:6 0.0002980594 +7 chany_top_out[3]:7 4.456608e-05 +8 chany_top_out[3]:8 4.456608e-05 + +*RES +0 mux_top_track_6\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[3]:8 0.152 +1 chany_top_out[3]:8 chany_top_out[3]:7 0.0003370536 +2 chany_top_out[3]:7 chany_top_out[3]:6 0.0045 +3 chany_top_out[3]:6 chany_top_out[3]:5 0.004169643 +4 chany_top_out[3]:4 chany_top_out[3]:3 0.01141964 +5 chany_top_out[3]:5 chany_top_out[3]:4 0.0045 +6 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +7 chany_top_out[3]:2 chany_top_out[3] 0.0002946429 + +*END + +*D_NET chany_top_out[7] 0.001885342 //LENGTH 14.865 LUMPCC 0.0005185225 DR + +*CONN +*I mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 46.405 91.460 +*P chany_top_out[7] O *L 0.7423 *C 50.140 102.070 +*N chany_top_out[7]:2 *C 50.140 91.845 +*N chany_top_out[7]:3 *C 50.095 91.800 +*N chany_top_out[7]:4 *C 46.460 91.800 +*N chany_top_out[7]:5 *C 46.405 91.460 + +*CAP +0 mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[7] 0.0003733027 +2 chany_top_out[7]:2 0.0003733027 +3 chany_top_out[7]:3 0.0002615893 +4 chany_top_out[7]:4 0.0002929473 +5 chany_top_out[7]:5 6.46776e-05 +6 chany_top_out[7] chany_top_out[15] 4.266215e-06 +7 chany_top_out[7] chany_top_out[15]:3 0.000254995 +8 chany_top_out[7]:2 chany_top_out[15]:4 0.000254995 +9 chany_top_out[7]:2 chany_top_out[15]:2 4.266215e-06 + +*RES +0 mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[7]:5 0.152 +1 chany_top_out[7]:5 chany_top_out[7]:4 0.0003035715 +2 chany_top_out[7]:3 chany_top_out[7]:2 0.0045 +3 chany_top_out[7]:2 chany_top_out[7] 0.009129465 +4 chany_top_out[7]:4 chany_top_out[7]:3 0.003245536 + +*END + +*D_NET chany_top_out[11] 0.0006493771 //LENGTH 6.615 LUMPCC 0 DR + +*CONN +*I mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 94.820 96.900 +*P chany_top_out[11] O *L 0.7423 *C 93.840 102.070 +*N chany_top_out[11]:2 *C 93.840 96.945 +*N chany_top_out[11]:3 *C 93.885 96.900 +*N chany_top_out[11]:4 *C 94.782 96.900 + +*CAP +0 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[11] 0.0002508577 +2 chany_top_out[11]:2 0.0002508577 +3 chany_top_out[11]:3 7.333083e-05 +4 chany_top_out[11]:4 7.333083e-05 + +*RES +0 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[11]:4 0.152 +1 chany_top_out[11]:4 chany_top_out[11]:3 0.0008013393 +2 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +3 chany_top_out[11]:2 chany_top_out[11] 0.004575893 + +*END + +*D_NET chany_top_out[15] 0.001697806 //LENGTH 12.795 LUMPCC 0.0005185225 DR + +*CONN +*I mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 51.580 91.460 +*P chany_top_out[15] O *L 0.7423 *C 51.060 102.070 +*N chany_top_out[15]:2 *C 51.060 101.320 +*N chany_top_out[15]:3 *C 50.600 101.320 +*N chany_top_out[15]:4 *C 50.600 91.505 +*N chany_top_out[15]:5 *C 50.645 91.460 +*N chany_top_out[15]:6 *C 51.543 91.460 + +*CAP +0 mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[15] 5.132071e-05 +2 chany_top_out[15]:2 7.970772e-05 +3 chany_top_out[15]:3 0.0004542224 +4 chany_top_out[15]:4 0.0004258354 +5 chany_top_out[15]:5 8.359845e-05 +6 chany_top_out[15]:6 8.359845e-05 +7 chany_top_out[15] chany_top_out[7] 4.266215e-06 +8 chany_top_out[15]:4 chany_top_out[7]:2 0.000254995 +9 chany_top_out[15]:3 chany_top_out[7] 0.000254995 +10 chany_top_out[15]:2 chany_top_out[7]:2 4.266215e-06 + +*RES +0 mux_top_track_30\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[15]:6 0.152 +1 chany_top_out[15]:6 chany_top_out[15]:5 0.0008013393 +2 chany_top_out[15]:5 chany_top_out[15]:4 0.0045 +3 chany_top_out[15]:4 chany_top_out[15]:3 0.008763393 +4 chany_top_out[15]:3 chany_top_out[15]:2 0.0004107143 +5 chany_top_out[15]:2 chany_top_out[15] 0.0006696429 + +*END + +*D_NET chanx_right_out[2] 0.003942736 //LENGTH 34.825 LUMPCC 0.0004184842 DR + +*CONN +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 122.420 22.780 +*P chanx_right_out[2] O *L 0.7423 *C 140.450 6.800 +*N chanx_right_out[2]:2 *C 136.168 6.800 +*N chanx_right_out[2]:3 *C 136.160 6.857 +*N chanx_right_out[2]:4 *C 136.160 22.735 +*N chanx_right_out[2]:5 *C 136.115 22.780 +*N chanx_right_out[2]:6 *C 122.458 22.780 + +*CAP +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[2] 0.0002698395 +2 chanx_right_out[2]:2 0.0002698395 +3 chanx_right_out[2]:3 0.0008163546 +4 chanx_right_out[2]:4 0.0008163546 +5 chanx_right_out[2]:5 0.0006754317 +6 chanx_right_out[2]:6 0.0006754317 +7 chanx_right_out[2]:6 ropt_net_144:2 0.0001465556 +8 chanx_right_out[2]:5 ropt_net_144:3 0.0001465556 +9 chanx_right_out[2]:6 ropt_net_168:2 6.268643e-05 +10 chanx_right_out[2]:5 ropt_net_168:3 6.268643e-05 + +*RES +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[2]:6 0.152 +1 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0121942 +2 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0045 +3 chanx_right_out[2]:4 chanx_right_out[2]:3 0.01417634 +4 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +5 chanx_right_out[2]:2 chanx_right_out[2] 0.000670925 + +*END + +*D_NET chanx_left_out[8] 0.001513582 //LENGTH 12.985 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 12.365 22.780 +*P chanx_left_out[8] O *L 0.7423 *C 1.298 21.760 +*N chanx_left_out[8]:2 *C 1.380 21.760 +*N chanx_left_out[8]:3 *C 1.380 21.818 +*N chanx_left_out[8]:4 *C 1.380 22.735 +*N chanx_left_out[8]:5 *C 1.425 22.780 +*N chanx_left_out[8]:6 *C 12.328 22.780 + +*CAP +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[8] 3.002675e-05 +2 chanx_left_out[8]:2 3.002675e-05 +3 chanx_left_out[8]:3 8.03756e-05 +4 chanx_left_out[8]:4 8.03756e-05 +5 chanx_left_out[8]:5 0.0006458886 +6 chanx_left_out[8]:6 0.0006458886 + +*RES +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[8]:6 0.152 +1 chanx_left_out[8]:6 chanx_left_out[8]:5 0.009734375 +2 chanx_left_out[8]:5 chanx_left_out[8]:4 0.0045 +3 chanx_left_out[8]:4 chanx_left_out[8]:3 0.0008191965 +4 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +5 chanx_left_out[8]:2 chanx_left_out[8] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.003554859 //LENGTH 21.525 LUMPCC 0.001127968 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 35.725 64.260 +*I mux_left_track_1\/mux_l3_in_1_:S I *L 0.00357 *C 27.500 61.880 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 28.235 69.700 +*I mux_left_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 36.440 66.640 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 36.340 66.640 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 36.340 66.595 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 28.235 69.700 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 28.520 69.700 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 28.520 69.655 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 27.538 61.880 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 28.475 61.880 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 28.520 61.925 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 28.520 65.280 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 28.527 65.280 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 36.333 65.280 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 36.340 65.280 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 36.340 64.305 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 36.295 64.260 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 35.763 64.260 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_1\/mux_l3_in_1_:S 1e-06 +2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_1\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 3.414967e-05 +5 mux_tree_tapbuf_size10_0_sram[2]:5 8.735762e-05 +6 mux_tree_tapbuf_size10_0_sram[2]:6 6.237726e-05 +7 mux_tree_tapbuf_size10_0_sram[2]:7 6.679779e-05 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0002566492 +9 mux_tree_tapbuf_size10_0_sram[2]:9 9.414077e-05 +10 mux_tree_tapbuf_size10_0_sram[2]:10 9.414077e-05 +11 mux_tree_tapbuf_size10_0_sram[2]:11 0.0001973281 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0004912731 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0003220316 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.0003220316 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.0001918143 +16 mux_tree_tapbuf_size10_0_sram[2]:16 6.781197e-05 +17 mux_tree_tapbuf_size10_0_sram[2]:17 6.749368e-05 +18 mux_tree_tapbuf_size10_0_sram[2]:18 6.749368e-05 +19 mux_tree_tapbuf_size10_0_sram[2]:13 chanx_right_in[12]:14 0.0002928565 +20 mux_tree_tapbuf_size10_0_sram[2]:15 chanx_right_in[12]:16 1.418001e-07 +21 mux_tree_tapbuf_size10_0_sram[2]:15 chanx_right_in[12]:17 4.996065e-08 +22 mux_tree_tapbuf_size10_0_sram[2]:14 chanx_right_in[12]:15 0.0002928565 +23 mux_tree_tapbuf_size10_0_sram[2]:17 chanx_right_in[12]:19 1.883205e-06 +24 mux_tree_tapbuf_size10_0_sram[2]:16 chanx_right_in[12]:17 8.669642e-08 +25 mux_tree_tapbuf_size10_0_sram[2]:18 chanx_right_in[12]:18 1.883205e-06 +26 mux_tree_tapbuf_size10_0_sram[2]:5 chanx_right_in[12]:9 5.510366e-08 +27 mux_tree_tapbuf_size10_0_sram[2]:5 chanx_right_in[12]:16 4.996065e-08 +28 mux_tree_tapbuf_size10_0_sram[2]:13 left_top_grid_pin_42_[0]:19 0.0002690524 +29 mux_tree_tapbuf_size10_0_sram[2]:14 left_top_grid_pin_42_[0]:18 0.0002690524 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:18 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.002995536 +2 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:8 0.00390625 +3 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.00341 +4 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.00341 +5 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:5 0.001174107 +6 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.001222783 +7 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.0001548913 +8 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.0045 +9 mux_tree_tapbuf_size10_0_sram[2]:6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.0045 +11 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.0008705358 +12 mux_tree_tapbuf_size10_0_sram[2]:18 mux_tree_tapbuf_size10_0_sram[2]:17 0.0004754464 +13 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.0008370537 +14 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.0045 +15 mux_tree_tapbuf_size10_0_sram[2]:9 mux_left_track_1\/mux_l3_in_1_:S 0.152 +16 mux_tree_tapbuf_size10_0_sram[2]:4 mux_left_track_1\/mux_l3_in_0_:S 0.152 +17 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.00206858 //LENGTH 16.040 LUMPCC 0.0001577301 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 42.625 86.020 +*I mux_top_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 35.320 89.080 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 33.295 91.460 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 33.295 91.460 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 33.580 91.460 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 33.580 91.415 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 33.580 89.125 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 33.625 89.080 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 35.320 89.080 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 41.815 89.080 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 41.860 89.035 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 41.860 86.065 +*N mux_tree_tapbuf_size2_2_sram[0]:12 *C 41.905 86.020 +*N mux_tree_tapbuf_size2_2_sram[0]:13 *C 42.587 86.020 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_32\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 4.898311e-05 +4 mux_tree_tapbuf_size2_2_sram[0]:4 5.508796e-05 +5 mux_tree_tapbuf_size2_2_sram[0]:5 0.0001565909 +6 mux_tree_tapbuf_size2_2_sram[0]:6 0.0001565909 +7 mux_tree_tapbuf_size2_2_sram[0]:7 0.0001304632 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.0005258298 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.000366873 +10 mux_tree_tapbuf_size2_2_sram[0]:10 0.0001734737 +11 mux_tree_tapbuf_size2_2_sram[0]:11 0.0001734737 +12 mux_tree_tapbuf_size2_2_sram[0]:12 6.024174e-05 +13 mux_tree_tapbuf_size2_2_sram[0]:13 6.024174e-05 +14 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 7.886506e-05 +15 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 7.886506e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size2_2_sram[0]:6 mux_tree_tapbuf_size2_2_sram[0]:5 0.002044643 +3 mux_tree_tapbuf_size2_2_sram[0]:4 mux_tree_tapbuf_size2_2_sram[0]:3 0.0001548913 +4 mux_tree_tapbuf_size2_2_sram[0]:5 mux_tree_tapbuf_size2_2_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size2_2_sram[0]:3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.005799107 +7 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_2_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.002651786 +10 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_2_sram[0]:12 0.000609375 +11 mux_tree_tapbuf_size2_2_sram[0]:8 mux_top_track_32\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.001513393 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[1] 0.002340127 //LENGTH 19.030 LUMPCC 0.0003519961 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 56.885 50.320 +*I mem_top_track_16\/FTB_16__42:A I *L 0.001746 *C 57.960 44.880 +*I mux_top_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 60.620 58.480 +*N mux_tree_tapbuf_size3_2_sram[1]:3 *C 60.583 58.480 +*N mux_tree_tapbuf_size3_2_sram[1]:4 *C 57.545 58.480 +*N mux_tree_tapbuf_size3_2_sram[1]:5 *C 57.500 58.435 +*N mux_tree_tapbuf_size3_2_sram[1]:6 *C 57.922 44.880 +*N mux_tree_tapbuf_size3_2_sram[1]:7 *C 57.545 44.880 +*N mux_tree_tapbuf_size3_2_sram[1]:8 *C 57.500 44.925 +*N mux_tree_tapbuf_size3_2_sram[1]:9 *C 57.500 50.320 +*N mux_tree_tapbuf_size3_2_sram[1]:10 *C 57.455 50.320 +*N mux_tree_tapbuf_size3_2_sram[1]:11 *C 56.922 50.320 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_16\/FTB_16__42:A 1e-06 +2 mux_top_track_16\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_2_sram[1]:3 0.0001932946 +4 mux_tree_tapbuf_size3_2_sram[1]:4 0.0001932946 +5 mux_tree_tapbuf_size3_2_sram[1]:5 0.0004075257 +6 mux_tree_tapbuf_size3_2_sram[1]:6 5.810154e-05 +7 mux_tree_tapbuf_size3_2_sram[1]:7 5.810154e-05 +8 mux_tree_tapbuf_size3_2_sram[1]:8 0.0002618606 +9 mux_tree_tapbuf_size3_2_sram[1]:9 0.0006975327 +10 mux_tree_tapbuf_size3_2_sram[1]:10 5.77098e-05 +11 mux_tree_tapbuf_size3_2_sram[1]:11 5.77098e-05 +12 mux_tree_tapbuf_size3_2_sram[1]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.442167e-05 +13 mux_tree_tapbuf_size3_2_sram[1]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.128414e-05 +14 mux_tree_tapbuf_size3_2_sram[1]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.442167e-05 +15 mux_tree_tapbuf_size3_2_sram[1]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.128414e-05 +16 mux_tree_tapbuf_size3_2_sram[1]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.92514e-05 +17 mux_tree_tapbuf_size3_2_sram[1]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.104085e-05 +18 mux_tree_tapbuf_size3_2_sram[1]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.92514e-05 +19 mux_tree_tapbuf_size3_2_sram[1]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.104085e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_2_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_2_sram[1]:7 mux_tree_tapbuf_size3_2_sram[1]:6 0.0003370536 +2 mux_tree_tapbuf_size3_2_sram[1]:8 mux_tree_tapbuf_size3_2_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size3_2_sram[1]:6 mem_top_track_16\/FTB_16__42:A 0.152 +4 mux_tree_tapbuf_size3_2_sram[1]:10 mux_tree_tapbuf_size3_2_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:8 0.004816964 +6 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:5 0.007245536 +7 mux_tree_tapbuf_size3_2_sram[1]:11 mux_tree_tapbuf_size3_2_sram[1]:10 0.0004754465 +8 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size3_2_sram[1]:3 0.002712054 +9 mux_tree_tapbuf_size3_2_sram[1]:5 mux_tree_tapbuf_size3_2_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_2_sram[1]:3 mux_top_track_16\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.0008052514 //LENGTH 6.000 LUMPCC 0 DR + +*CONN +*I mem_top_track_12\/FTB_14__40:X O *L 0 *C 65.545 66.300 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.275 64.260 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 62.312 64.260 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 65.275 64.260 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 65.320 64.305 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 65.320 66.255 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 65.320 66.300 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 65.545 66.300 + +*CAP +0 mem_top_track_12\/FTB_14__40:X 1e-06 +1 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0002127751 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0002127751 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.0001330968 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0001330968 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 5.698395e-05 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 5.452362e-05 + +*RES +0 mem_top_track_12\/FTB_14__40:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.001741072 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.00264509 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.002617847 //LENGTH 18.370 LUMPCC 0.0004244126 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.965 74.800 +*I mux_right_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 79.020 72.760 +*I mux_right_track_32\/mux_l2_in_1_:S I *L 0.00357 *C 88.420 72.760 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 82.055 77.180 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 82.055 77.180 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 81.880 77.180 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 81.880 77.135 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 81.880 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 88.383 72.760 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 79.058 72.760 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 81.420 72.760 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 81.420 72.805 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 81.420 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 81.375 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 79.002 74.800 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:S 1e-06 +2 mux_right_track_32\/mux_l2_in_1_:S 1e-06 +3 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 4.9318e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 5.360788e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 0.0001783971 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.0002059844 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.0004115661 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.0001073235 +10 mux_tree_tapbuf_size6_0_sram[1]:10 0.0005545557 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0001385779 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0001661652 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0001619693 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.0001619693 +15 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[0]:15 4.234733e-05 +16 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[0]:17 6.692793e-05 +17 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[0]:14 4.234733e-05 +18 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[0]:15 9.408365e-05 +19 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[0]:16 6.692793e-05 +20 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[0]:14 9.408365e-05 +21 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[0]:14 8.847397e-06 +22 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[0]:15 8.847397e-06 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:14 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:8 mux_right_track_32\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.002109375 +3 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:8 0.006216518 +4 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size6_0_sram[1]:9 mux_right_track_32\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_0_sram[1]:5 mux_tree_tapbuf_size6_0_sram[1]:4 9.51087e-05 +7 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0045 +8 mux_tree_tapbuf_size6_0_sram[1]:4 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:11 0.00178125 +11 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:7 0.0004107143 +12 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.002118304 +13 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[1]:6 0.002084822 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[1] 0.003246521 //LENGTH 24.510 LUMPCC 0.0006620149 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 99.665 23.120 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 92.635 26.180 +*I mux_right_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 92.820 34.000 +*I mux_right_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 101.300 25.160 +*N mux_tree_tapbuf_size7_3_sram[1]:4 *C 101.200 25.160 +*N mux_tree_tapbuf_size7_3_sram[1]:5 *C 101.200 25.115 +*N mux_tree_tapbuf_size7_3_sram[1]:6 *C 101.200 23.165 +*N mux_tree_tapbuf_size7_3_sram[1]:7 *C 101.155 23.120 +*N mux_tree_tapbuf_size7_3_sram[1]:8 *C 92.858 34.000 +*N mux_tree_tapbuf_size7_3_sram[1]:9 *C 93.840 34.000 +*N mux_tree_tapbuf_size7_3_sram[1]:10 *C 93.840 33.660 +*N mux_tree_tapbuf_size7_3_sram[1]:11 *C 93.840 33.615 +*N mux_tree_tapbuf_size7_3_sram[1]:12 *C 92.672 26.180 +*N mux_tree_tapbuf_size7_3_sram[1]:13 *C 93.795 26.180 +*N mux_tree_tapbuf_size7_3_sram[1]:14 *C 93.840 26.180 +*N mux_tree_tapbuf_size7_3_sram[1]:15 *C 93.840 23.178 +*N mux_tree_tapbuf_size7_3_sram[1]:16 *C 93.848 23.120 +*N mux_tree_tapbuf_size7_3_sram[1]:17 *C 99.353 23.120 +*N mux_tree_tapbuf_size7_3_sram[1]:18 *C 99.360 23.120 +*N mux_tree_tapbuf_size7_3_sram[1]:19 *C 99.360 23.120 +*N mux_tree_tapbuf_size7_3_sram[1]:20 *C 99.703 23.120 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_16\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_16\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_3_sram[1]:4 3.057914e-05 +5 mux_tree_tapbuf_size7_3_sram[1]:5 0.0001126832 +6 mux_tree_tapbuf_size7_3_sram[1]:6 0.0001126832 +7 mux_tree_tapbuf_size7_3_sram[1]:7 9.683931e-05 +8 mux_tree_tapbuf_size7_3_sram[1]:8 9.85448e-05 +9 mux_tree_tapbuf_size7_3_sram[1]:9 0.0001291326 +10 mux_tree_tapbuf_size7_3_sram[1]:10 6.697839e-05 +11 mux_tree_tapbuf_size7_3_sram[1]:11 0.0003914541 +12 mux_tree_tapbuf_size7_3_sram[1]:12 0.0001025516 +13 mux_tree_tapbuf_size7_3_sram[1]:13 0.0001025516 +14 mux_tree_tapbuf_size7_3_sram[1]:14 0.0005856334 +15 mux_tree_tapbuf_size7_3_sram[1]:15 0.0001646672 +16 mux_tree_tapbuf_size7_3_sram[1]:16 0.0001953463 +17 mux_tree_tapbuf_size7_3_sram[1]:17 0.0001953463 +18 mux_tree_tapbuf_size7_3_sram[1]:18 3.194284e-05 +19 mux_tree_tapbuf_size7_3_sram[1]:19 4.986077e-05 +20 mux_tree_tapbuf_size7_3_sram[1]:20 0.0001137109 +21 mux_tree_tapbuf_size7_3_sram[1]:17 chanx_right_in[12]:28 0.0003310074 +22 mux_tree_tapbuf_size7_3_sram[1]:16 chanx_right_in[12]:27 0.0003310074 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_3_sram[1]:20 0.152 +1 mux_tree_tapbuf_size7_3_sram[1]:8 mux_right_track_16\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_3_sram[1]:10 mux_tree_tapbuf_size7_3_sram[1]:9 0.0003035715 +3 mux_tree_tapbuf_size7_3_sram[1]:11 mux_tree_tapbuf_size7_3_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size7_3_sram[1]:19 mux_tree_tapbuf_size7_3_sram[1]:18 0.0045 +5 mux_tree_tapbuf_size7_3_sram[1]:18 mux_tree_tapbuf_size7_3_sram[1]:17 0.00341 +6 mux_tree_tapbuf_size7_3_sram[1]:17 mux_tree_tapbuf_size7_3_sram[1]:16 0.00086245 +7 mux_tree_tapbuf_size7_3_sram[1]:15 mux_tree_tapbuf_size7_3_sram[1]:14 0.002680804 +8 mux_tree_tapbuf_size7_3_sram[1]:16 mux_tree_tapbuf_size7_3_sram[1]:15 0.00341 +9 mux_tree_tapbuf_size7_3_sram[1]:7 mux_tree_tapbuf_size7_3_sram[1]:6 0.0045 +10 mux_tree_tapbuf_size7_3_sram[1]:6 mux_tree_tapbuf_size7_3_sram[1]:5 0.001741072 +11 mux_tree_tapbuf_size7_3_sram[1]:4 mux_right_track_16\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size7_3_sram[1]:5 mux_tree_tapbuf_size7_3_sram[1]:4 0.0045 +13 mux_tree_tapbuf_size7_3_sram[1]:13 mux_tree_tapbuf_size7_3_sram[1]:12 0.001002232 +14 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:13 0.0045 +15 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:11 0.006638393 +16 mux_tree_tapbuf_size7_3_sram[1]:12 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size7_3_sram[1]:20 mux_tree_tapbuf_size7_3_sram[1]:19 0.0001861413 +18 mux_tree_tapbuf_size7_3_sram[1]:20 mux_tree_tapbuf_size7_3_sram[1]:7 0.001296875 +19 mux_tree_tapbuf_size7_3_sram[1]:9 mux_tree_tapbuf_size7_3_sram[1]:8 0.0008772322 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_3_ccff_tail[0] 0.001038054 //LENGTH 8.380 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/FTB_8__34:X O *L 0 *C 94.985 37.060 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.935 44.540 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 *C 94.935 44.540 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 *C 94.760 44.540 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 *C 94.760 44.495 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 *C 94.760 37.105 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 *C 94.760 37.060 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 *C 94.985 37.060 + +*CAP +0 mem_right_track_16\/FTB_8__34:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 5.936945e-05 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 5.505254e-05 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.0004031259 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.0004031259 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 5.780679e-05 +7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 5.7573e-05 + +*RES +0 mem_right_track_16\/FTB_8__34:X mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.006598215 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_0_ccff_tail[0] 0.0006660736 //LENGTH 4.790 LUMPCC 0.0001366257 DR + +*CONN +*I mem_top_track_0\/FTB_1__27:X O *L 0 *C 63.255 72.420 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 61.815 75.140 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 *C 61.815 75.140 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 *C 62.100 75.140 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 *C 62.100 75.095 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 *C 62.100 72.465 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 *C 62.145 72.420 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 *C 63.218 72.420 + +*CAP +0 mem_top_track_0\/FTB_1__27:X 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 5.386875e-05 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 5.848668e-05 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0001521089 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0001521089 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 5.543728e-05 +7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 5.543728e-05 +8 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 chany_top_in[5]:11 5.291809e-05 +9 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 chany_top_in[5]:12 5.291809e-05 +10 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 chany_top_in[5]:13 6.007679e-06 +11 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 chany_top_in[5]:15 9.387103e-06 +12 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 chany_top_in[5]:14 6.007679e-06 +13 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 chany_top_in[5]:16 9.387103e-06 + +*RES +0 mem_top_track_0\/FTB_1__27:X mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 0.0009575894 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size9_1_sram[1] 0.005958889 //LENGTH 45.585 LUMPCC 0.0004185039 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 100.125 93.840 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 89.875 86.020 +*I mux_right_track_2\/mux_l2_in_3_:S I *L 0.00357 *C 95.780 74.800 +*I mux_right_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 97.060 83.135 +*I mux_right_track_2\/mux_l2_in_2_:S I *L 0.00357 *C 92.360 80.240 +*I mux_right_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 94.200 90.830 +*N mux_tree_tapbuf_size9_1_sram[1]:6 *C 94.200 90.830 +*N mux_tree_tapbuf_size9_1_sram[1]:7 *C 92.323 80.240 +*N mux_tree_tapbuf_size9_1_sram[1]:8 *C 90.205 80.240 +*N mux_tree_tapbuf_size9_1_sram[1]:9 *C 90.160 80.285 +*N mux_tree_tapbuf_size9_1_sram[1]:10 *C 97.060 83.135 +*N mux_tree_tapbuf_size9_1_sram[1]:11 *C 95.818 74.800 +*N mux_tree_tapbuf_size9_1_sram[1]:12 *C 97.015 74.800 +*N mux_tree_tapbuf_size9_1_sram[1]:13 *C 97.060 74.845 +*N mux_tree_tapbuf_size9_1_sram[1]:14 *C 97.060 82.575 +*N mux_tree_tapbuf_size9_1_sram[1]:15 *C 97.060 82.650 +*N mux_tree_tapbuf_size9_1_sram[1]:16 *C 90.205 82.620 +*N mux_tree_tapbuf_size9_1_sram[1]:17 *C 90.160 82.620 +*N mux_tree_tapbuf_size9_1_sram[1]:18 *C 89.875 86.020 +*N mux_tree_tapbuf_size9_1_sram[1]:19 *C 90.160 86.020 +*N mux_tree_tapbuf_size9_1_sram[1]:20 *C 90.160 86.020 +*N mux_tree_tapbuf_size9_1_sram[1]:21 *C 90.160 90.395 +*N mux_tree_tapbuf_size9_1_sram[1]:22 *C 90.205 90.440 +*N mux_tree_tapbuf_size9_1_sram[1]:23 *C 94.200 90.440 +*N mux_tree_tapbuf_size9_1_sram[1]:24 *C 99.775 90.440 +*N mux_tree_tapbuf_size9_1_sram[1]:25 *C 99.820 90.485 +*N mux_tree_tapbuf_size9_1_sram[1]:26 *C 99.820 93.795 +*N mux_tree_tapbuf_size9_1_sram[1]:27 *C 99.820 93.840 +*N mux_tree_tapbuf_size9_1_sram[1]:28 *C 100.125 93.840 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_2\/mux_l2_in_3_:S 1e-06 +3 mux_right_track_2\/mux_l2_in_1_:S 1e-06 +4 mux_right_track_2\/mux_l2_in_2_:S 1e-06 +5 mux_right_track_2\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size9_1_sram[1]:6 5.290923e-05 +7 mux_tree_tapbuf_size9_1_sram[1]:7 0.0001769458 +8 mux_tree_tapbuf_size9_1_sram[1]:8 0.0001769458 +9 mux_tree_tapbuf_size9_1_sram[1]:9 0.0001414349 +10 mux_tree_tapbuf_size9_1_sram[1]:10 7.344115e-05 +11 mux_tree_tapbuf_size9_1_sram[1]:11 0.0001233798 +12 mux_tree_tapbuf_size9_1_sram[1]:12 0.0001233798 +13 mux_tree_tapbuf_size9_1_sram[1]:13 0.0004861967 +14 mux_tree_tapbuf_size9_1_sram[1]:14 0.0004861967 +15 mux_tree_tapbuf_size9_1_sram[1]:15 0.0005405093 +16 mux_tree_tapbuf_size9_1_sram[1]:16 0.0004978842 +17 mux_tree_tapbuf_size9_1_sram[1]:17 0.0003184974 +18 mux_tree_tapbuf_size9_1_sram[1]:18 4.642349e-05 +19 mux_tree_tapbuf_size9_1_sram[1]:19 5.244703e-05 +20 mux_tree_tapbuf_size9_1_sram[1]:20 0.0003765256 +21 mux_tree_tapbuf_size9_1_sram[1]:21 0.0002035709 +22 mux_tree_tapbuf_size9_1_sram[1]:22 0.0002055219 +23 mux_tree_tapbuf_size9_1_sram[1]:23 0.0005957036 +24 mux_tree_tapbuf_size9_1_sram[1]:24 0.0003627084 +25 mux_tree_tapbuf_size9_1_sram[1]:25 0.000192671 +26 mux_tree_tapbuf_size9_1_sram[1]:26 0.000192671 +27 mux_tree_tapbuf_size9_1_sram[1]:27 5.62155e-05 +28 mux_tree_tapbuf_size9_1_sram[1]:28 5.220586e-05 +29 mux_tree_tapbuf_size9_1_sram[1]:17 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 7.574487e-06 +30 mux_tree_tapbuf_size9_1_sram[1]:17 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 1.005741e-06 +31 mux_tree_tapbuf_size9_1_sram[1]:17 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 3.077491e-05 +32 mux_tree_tapbuf_size9_1_sram[1]:21 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 3.507688e-05 +33 mux_tree_tapbuf_size9_1_sram[1]:20 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:5 7.574487e-06 +34 mux_tree_tapbuf_size9_1_sram[1]:20 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:8 3.507688e-05 +35 mux_tree_tapbuf_size9_1_sram[1]:20 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:9 3.077491e-05 +36 mux_tree_tapbuf_size9_1_sram[1]:9 mux_tree_tapbuf_size3_mem_7_ccff_tail[0]:4 1.005741e-06 +37 mux_tree_tapbuf_size9_1_sram[1]:22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001348199 +38 mux_tree_tapbuf_size9_1_sram[1]:23 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001348199 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size9_1_sram[1]:28 0.152 +1 mux_tree_tapbuf_size9_1_sram[1]:10 mux_right_track_2\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size9_1_sram[1]:16 mux_tree_tapbuf_size9_1_sram[1]:15 0.006120536 +3 mux_tree_tapbuf_size9_1_sram[1]:17 mux_tree_tapbuf_size9_1_sram[1]:16 0.0045 +4 mux_tree_tapbuf_size9_1_sram[1]:17 mux_tree_tapbuf_size9_1_sram[1]:9 0.002084821 +5 mux_tree_tapbuf_size9_1_sram[1]:22 mux_tree_tapbuf_size9_1_sram[1]:21 0.0045 +6 mux_tree_tapbuf_size9_1_sram[1]:21 mux_tree_tapbuf_size9_1_sram[1]:20 0.00390625 +7 mux_tree_tapbuf_size9_1_sram[1]:19 mux_tree_tapbuf_size9_1_sram[1]:18 0.0001548913 +8 mux_tree_tapbuf_size9_1_sram[1]:20 mux_tree_tapbuf_size9_1_sram[1]:19 0.0045 +9 mux_tree_tapbuf_size9_1_sram[1]:20 mux_tree_tapbuf_size9_1_sram[1]:17 0.003035714 +10 mux_tree_tapbuf_size9_1_sram[1]:18 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size9_1_sram[1]:24 mux_tree_tapbuf_size9_1_sram[1]:23 0.004977679 +12 mux_tree_tapbuf_size9_1_sram[1]:25 mux_tree_tapbuf_size9_1_sram[1]:24 0.0045 +13 mux_tree_tapbuf_size9_1_sram[1]:27 mux_tree_tapbuf_size9_1_sram[1]:26 0.0045 +14 mux_tree_tapbuf_size9_1_sram[1]:26 mux_tree_tapbuf_size9_1_sram[1]:25 0.002955357 +15 mux_tree_tapbuf_size9_1_sram[1]:28 mux_tree_tapbuf_size9_1_sram[1]:27 0.0001657609 +16 mux_tree_tapbuf_size9_1_sram[1]:15 mux_tree_tapbuf_size9_1_sram[1]:14 0.0045 +17 mux_tree_tapbuf_size9_1_sram[1]:15 mux_tree_tapbuf_size9_1_sram[1]:10 0.0004330357 +18 mux_tree_tapbuf_size9_1_sram[1]:14 mux_tree_tapbuf_size9_1_sram[1]:13 0.006901786 +19 mux_tree_tapbuf_size9_1_sram[1]:12 mux_tree_tapbuf_size9_1_sram[1]:11 0.001069197 +20 mux_tree_tapbuf_size9_1_sram[1]:13 mux_tree_tapbuf_size9_1_sram[1]:12 0.0045 +21 mux_tree_tapbuf_size9_1_sram[1]:11 mux_right_track_2\/mux_l2_in_3_:S 0.152 +22 mux_tree_tapbuf_size9_1_sram[1]:8 mux_tree_tapbuf_size9_1_sram[1]:7 0.001890625 +23 mux_tree_tapbuf_size9_1_sram[1]:9 mux_tree_tapbuf_size9_1_sram[1]:8 0.0045 +24 mux_tree_tapbuf_size9_1_sram[1]:7 mux_right_track_2\/mux_l2_in_2_:S 0.152 +25 mux_tree_tapbuf_size9_1_sram[1]:6 mux_right_track_2\/mux_l2_in_0_:S 0.152 +26 mux_tree_tapbuf_size9_1_sram[1]:23 mux_tree_tapbuf_size9_1_sram[1]:22 0.003566965 +27 mux_tree_tapbuf_size9_1_sram[1]:23 mux_tree_tapbuf_size9_1_sram[1]:6 0.0003482143 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.007079096 //LENGTH 50.790 LUMPCC 0.003071475 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_0_:X O *L 0 *C 77.565 55.760 +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 77.205 99.150 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 77.205 99.150 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 77.280 99.235 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 77.280 97.978 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 77.288 97.920 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 80.020 97.920 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 80.040 97.913 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 80.040 57.128 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 80.020 57.120 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 78.208 57.120 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 78.200 57.062 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 78.200 55.805 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 78.155 55.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 77.603 55.760 + +*CAP +0 mux_top_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.598865e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.000111532 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000111532 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002364036 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002364036 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.001322211 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001322211 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001508991 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001508991 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0001107952 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001107952 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 5.29751e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 5.29751e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 top_left_grid_pin_35_[0]:13 6.004905e-05 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 top_left_grid_pin_35_[0]:14 5.869659e-05 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 top_left_grid_pin_35_[0]:9 6.004905e-05 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 top_left_grid_pin_35_[0]:13 5.869659e-05 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 top_left_grid_pin_35_[0]:15 0.0006203783 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 top_left_grid_pin_35_[0]:16 0.0006203783 +21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_top_in[17]:18 0.000562335 +22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_top_in[17]:19 0.0002342786 +23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chany_top_in[17]:19 0.000562335 +24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chany_top_in[17]:20 0.0002342786 + +*RES +0 mux_top_track_4\/mux_l3_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0004933036 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.001122768 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.00341 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0002839583 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.00341 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00638965 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004280916 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.00341 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.001122768 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.00341 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001054909 //LENGTH 7.610 LUMPCC 0.0002301237 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_3_:X O *L 0 *C 34.785 46.920 +*I mux_left_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 39.275 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 39.238 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 35.005 44.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 34.960 44.585 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 34.960 46.875 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 34.960 46.920 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 34.785 46.920 + +*CAP +0 mux_left_track_25\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002014151 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002014151 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001490977 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001490977 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.232178e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.943819e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_3_sram[0]:7 0.0001149154 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_3_sram[0]:8 0.0001149154 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_3_sram[0]:6 1.464264e-07 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_3_sram[0]:5 1.464264e-07 + +*RES +0 mux_left_track_25\/mux_l1_in_3_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_25\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003779018 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003474926 //LENGTH 27.420 LUMPCC 0.001068243 DR + +*CONN +*I mux_top_track_14\/mux_l2_in_0_:X O *L 0 *C 48.015 64.600 +*I mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 48.000 91.255 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 48.000 91.255 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 47.840 91.120 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 47.840 91.075 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 47.840 64.645 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 47.840 64.600 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 48.015 64.600 + +*CAP +0 mux_top_track_14\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.42957e-05 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.647142e-05 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001093619 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001093619 +6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.400171e-05 +7 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.267663e-05 +8 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_37_[0]:19 0.0002175343 +9 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_37_[0]:22 8.477655e-05 +10 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_37_[0]:22 0.0002175343 +11 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_37_[0]:23 8.477655e-05 +12 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.565623e-05 +13 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.565623e-05 +14 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 optlc_net_125:11 2.302769e-05 +15 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 optlc_net_125:18 4.838174e-06 +16 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 optlc_net_125:14 0.0001151281 +17 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 optlc_net_125:19 1.316035e-05 +18 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 optlc_net_125:11 1.316035e-05 +19 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 optlc_net_125:15 0.0001151281 +20 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 optlc_net_125:8 2.302769e-05 +21 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 optlc_net_125:19 4.838174e-06 + +*RES +0 mux_top_track_14\/mux_l2_in_0_:X mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.510871e-05 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.02359822 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.695653e-05 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_14\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET optlc_net_125 0.006334688 //LENGTH 48.015 LUMPCC 0.001608101 DR + +*CONN +*I optlc_120:HI O *L 0 *C 41.400 80.580 +*I mux_top_track_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 47.555 65.960 +*I mux_top_track_30\/mux_l2_in_0_:A0 I *L 0.001631 *C 48.935 86.360 +*I mux_top_track_34\/mux_l2_in_0_:A0 I *L 0.001631 *C 45.255 96.900 +*I mux_top_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 40.195 96.900 +*N optlc_net_125:5 *C 40.233 96.900 +*N optlc_net_125:6 *C 45.255 96.900 +*N optlc_net_125:7 *C 45.955 96.900 +*N optlc_net_125:8 *C 46.000 96.855 +*N optlc_net_125:9 *C 48.898 86.360 +*N optlc_net_125:10 *C 46.045 86.360 +*N optlc_net_125:11 *C 46.000 86.360 +*N optlc_net_125:12 *C 47.518 65.960 +*N optlc_net_125:13 *C 46.965 65.960 +*N optlc_net_125:14 *C 46.920 66.005 +*N optlc_net_125:15 *C 46.920 77.135 +*N optlc_net_125:16 *C 46.875 77.180 +*N optlc_net_125:17 *C 46.045 77.180 +*N optlc_net_125:18 *C 46.000 77.225 +*N optlc_net_125:19 *C 46.000 80.580 +*N optlc_net_125:20 *C 45.955 80.580 +*N optlc_net_125:21 *C 41.438 80.580 + +*CAP +0 optlc_120:HI 1e-06 +1 mux_top_track_0\/mux_l2_in_3_:A0 1e-06 +2 mux_top_track_30\/mux_l2_in_0_:A0 1e-06 +3 mux_top_track_34\/mux_l2_in_0_:A0 1e-06 +4 mux_top_track_32\/mux_l2_in_0_:A0 1e-06 +5 optlc_net_125:5 0.0003169615 +6 optlc_net_125:6 0.0004040026 +7 optlc_net_125:7 5.808157e-05 +8 optlc_net_125:8 0.0003758545 +9 optlc_net_125:9 0.0001533201 +10 optlc_net_125:10 0.0001533201 +11 optlc_net_125:11 0.0006136612 +12 optlc_net_125:12 7.700928e-05 +13 optlc_net_125:13 7.700928e-05 +14 optlc_net_125:14 0.0005422488 +15 optlc_net_125:15 0.0005422488 +16 optlc_net_125:16 7.023126e-05 +17 optlc_net_125:17 7.023126e-05 +18 optlc_net_125:18 0.000131277 +19 optlc_net_125:19 0.0003730004 +20 optlc_net_125:20 0.0003815646 +21 optlc_net_125:21 0.0003815646 +22 optlc_net_125:11 chany_top_in[15]:11 0.0002796927 +23 optlc_net_125:11 chany_top_in[15]:12 0.00014958 +24 optlc_net_125:18 chany_top_in[15]:11 9.110117e-05 +25 optlc_net_125:15 chany_top_in[15]:11 1.024859e-05 +26 optlc_net_125:15 chany_top_in[15]:12 1.370254e-06 +27 optlc_net_125:14 chany_top_in[15]:4 1.024859e-05 +28 optlc_net_125:14 chany_top_in[15]:11 1.370254e-06 +29 optlc_net_125:8 chany_top_in[15]:12 0.0002796927 +30 optlc_net_125:19 chany_top_in[15]:11 0.00014958 +31 optlc_net_125:19 chany_top_in[15]:12 9.110117e-05 +32 optlc_net_125:10 mux_tree_tapbuf_size2_1_sram[1]:6 0.0001159035 +33 optlc_net_125:9 mux_tree_tapbuf_size2_1_sram[1]:7 0.0001159035 +34 optlc_net_125:11 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.316035e-05 +35 optlc_net_125:11 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.302769e-05 +36 optlc_net_125:18 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.838174e-06 +37 optlc_net_125:15 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001151281 +38 optlc_net_125:14 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001151281 +39 optlc_net_125:8 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.302769e-05 +40 optlc_net_125:19 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.838174e-06 +41 optlc_net_125:19 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.316035e-05 + +*RES +0 optlc_120:HI optlc_net_125:21 0.152 +1 optlc_net_125:10 optlc_net_125:9 0.002546875 +2 optlc_net_125:11 optlc_net_125:10 0.0045 +3 optlc_net_125:11 optlc_net_125:8 0.009370536 +4 optlc_net_125:9 mux_top_track_30\/mux_l2_in_0_:A0 0.152 +5 optlc_net_125:17 optlc_net_125:16 0.0007410714 +6 optlc_net_125:18 optlc_net_125:17 0.0045 +7 optlc_net_125:16 optlc_net_125:15 0.0045 +8 optlc_net_125:15 optlc_net_125:14 0.009937502 +9 optlc_net_125:13 optlc_net_125:12 0.0004933036 +10 optlc_net_125:14 optlc_net_125:13 0.0045 +11 optlc_net_125:12 mux_top_track_0\/mux_l2_in_3_:A0 0.152 +12 optlc_net_125:7 optlc_net_125:6 0.0006250001 +13 optlc_net_125:8 optlc_net_125:7 0.0045 +14 optlc_net_125:20 optlc_net_125:19 0.0045 +15 optlc_net_125:19 optlc_net_125:18 0.002995536 +16 optlc_net_125:19 optlc_net_125:11 0.005160714 +17 optlc_net_125:21 optlc_net_125:20 0.004033482 +18 optlc_net_125:6 mux_top_track_34\/mux_l2_in_0_:A0 0.152 +19 optlc_net_125:6 optlc_net_125:5 0.004484375 +20 optlc_net_125:5 mux_top_track_32\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001323865 //LENGTH 9.940 LUMPCC 0.0002104163 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_1_:X O *L 0 *C 107.815 68.680 +*I mux_right_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 106.435 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 106.473 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 107.595 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 107.640 60.905 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 107.640 68.635 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 107.640 68.680 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 107.815 68.680 + +*CAP +0 mux_right_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 7.457699e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.457699e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004290579 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004290579 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 4.814998e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.602847e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 prog_clk[0]:209 2.823827e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 prog_clk[0]:208 2.823827e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:211 1.654185e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:210 1.654185e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size14_0_sram[1]:10 2.218818e-07 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size14_0_sram[1]:25 4.666356e-05 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size14_0_sram[1]:29 1.354258e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size14_0_sram[1]:11 2.218818e-07 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size14_0_sram[1]:26 4.666356e-05 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size14_0_sram[1]:28 1.354258e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001002232 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.006901787 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0] 0.01051174 //LENGTH 69.655 LUMPCC 0.004580623 DR + +*CONN +*I mux_right_track_32\/mux_l3_in_0_:X O *L 0 *C 87.685 69.360 +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 131.840 44.730 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 131.803 44.828 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 130.225 44.880 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 130.180 44.925 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 130.180 69.303 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 130.173 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 87.868 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 87.860 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 87.860 69.360 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 87.685 69.360 + +*CAP +0 mux_right_track_32\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001046993 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001046993 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001348845 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001348845 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001432903 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001432903 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 3.706581e-05 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.913436e-05 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 6.002399e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[2]:14 0.0003801698 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[2]:18 2.159918e-05 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[2]:7 1.780928e-06 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[2]:13 0.0003801698 +15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[2]:14 2.159918e-05 +16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_left_in[2]:6 1.780928e-06 +17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:127 0.0002627853 +18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:126 0.0002627853 +19 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_49_[0]:14 0.0003067129 +20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_49_[0]:18 0.000816609 +21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_49_[0]:22 8.017751e-06 +22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_49_[0]:18 0.0003067129 +23 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_49_[0]:19 0.000816609 +24 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_49_[0]:23 8.017751e-06 +25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0004926364 +26 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0004926364 + +*RES +0 mux_right_track_32\/mux_l3_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 9.51087e-05 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0045 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.006627783 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.02176563 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001408482 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chanx_left_out[11] 0.00159358 //LENGTH 11.650 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 4.140 40.120 +*P chanx_left_out[11] O *L 0.7423 *C 1.230 38.080 +*N chanx_left_out[11]:2 *C 1.820 38.080 +*N chanx_left_out[11]:3 *C 1.840 38.087 +*N chanx_left_out[11]:4 *C 1.840 40.113 +*N chanx_left_out[11]:5 *C 1.860 40.120 +*N chanx_left_out[11]:6 *C 6.893 40.120 +*N chanx_left_out[11]:7 *C 6.900 40.120 +*N chanx_left_out[11]:8 *C 6.855 40.120 +*N chanx_left_out[11]:9 *C 4.178 40.120 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 chanx_left_out[11] 6.652337e-05 +2 chanx_left_out[11]:2 6.652337e-05 +3 chanx_left_out[11]:3 0.0001373749 +4 chanx_left_out[11]:4 0.0001373749 +5 chanx_left_out[11]:5 0.00037725 +6 chanx_left_out[11]:6 0.00037725 +7 chanx_left_out[11]:7 3.604465e-05 +8 chanx_left_out[11]:8 0.0001971193 +9 chanx_left_out[11]:9 0.0001971193 + +*RES +0 ropt_mt_inst_782:X chanx_left_out[11]:9 0.152 +1 chanx_left_out[11]:9 chanx_left_out[11]:8 0.002390625 +2 chanx_left_out[11]:8 chanx_left_out[11]:7 0.0045 +3 chanx_left_out[11]:7 chanx_left_out[11]:6 0.00341 +4 chanx_left_out[11]:6 chanx_left_out[11]:5 0.000788425 +5 chanx_left_out[11]:5 chanx_left_out[11]:4 0.00341 +6 chanx_left_out[11]:4 chanx_left_out[11]:3 0.00031725 +7 chanx_left_out[11]:2 chanx_left_out[11] 9.243333e-05 +8 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 + +*END + +*D_NET ropt_net_161 0.0008807526 //LENGTH 6.525 LUMPCC 0.0003361222 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 7.080 48.280 +*I ropt_mt_inst_787:A I *L 0.001767 *C 3.220 50.320 +*N ropt_net_161:2 *C 3.220 50.320 +*N ropt_net_161:3 *C 3.220 50.275 +*N ropt_net_161:4 *C 3.220 48.325 +*N ropt_net_161:5 *C 3.265 48.280 +*N ropt_net_161:6 *C 7.043 48.280 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 ropt_mt_inst_787:A 1e-06 +2 ropt_net_161:2 2.906226e-05 +3 ropt_net_161:3 4.221636e-05 +4 ropt_net_161:4 4.221636e-05 +5 ropt_net_161:5 0.0002145677 +6 ropt_net_161:6 0.0002145677 +7 ropt_net_161:4 chanx_left_in[5]:30 5.886623e-05 +8 ropt_net_161:3 chanx_left_in[5]:31 5.886623e-05 +9 ropt_net_161:6 mux_tree_tapbuf_size14_1_sram[0]:35 1.420341e-05 +10 ropt_net_161:6 mux_tree_tapbuf_size14_1_sram[0]:38 4.581848e-05 +11 ropt_net_161:5 mux_tree_tapbuf_size14_1_sram[0]:34 1.420341e-05 +12 ropt_net_161:5 mux_tree_tapbuf_size14_1_sram[0]:37 4.581848e-05 +13 ropt_net_161:4 mux_tree_tapbuf_size14_1_sram[0]:36 3.019059e-06 +14 ropt_net_161:3 mux_tree_tapbuf_size14_1_sram[0]:35 3.019059e-06 +15 ropt_net_161:4 chanx_left_out[7]:3 4.615394e-05 +16 ropt_net_161:3 chanx_left_out[7]:4 4.615394e-05 + +*RES +0 ropt_mt_inst_764:X ropt_net_161:6 0.152 +1 ropt_net_161:6 ropt_net_161:5 0.003372768 +2 ropt_net_161:5 ropt_net_161:4 0.0045 +3 ropt_net_161:4 ropt_net_161:3 0.001741071 +4 ropt_net_161:2 ropt_mt_inst_787:A 0.152 +5 ropt_net_161:3 ropt_net_161:2 0.0045 + +*END + +*D_NET ropt_net_172 0.00123095 //LENGTH 10.245 LUMPCC 0.0001917294 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 138.655 63.240 +*I ropt_mt_inst_799:A I *L 0.001767 *C 134.780 61.200 +*N ropt_net_172:2 *C 134.780 61.200 +*N ropt_net_172:3 *C 134.780 61.540 +*N ropt_net_172:4 *C 140.255 61.540 +*N ropt_net_172:5 *C 140.300 61.585 +*N ropt_net_172:6 *C 140.300 63.195 +*N ropt_net_172:7 *C 140.255 63.240 +*N ropt_net_172:8 *C 138.692 63.240 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_172:2 6.328106e-05 +3 ropt_net_172:3 0.0003337319 +4 ropt_net_172:4 0.0003030238 +5 ropt_net_172:5 5.430796e-05 +6 ropt_net_172:6 5.430796e-05 +7 ropt_net_172:7 0.000114284 +8 ropt_net_172:8 0.000114284 +9 ropt_net_172:4 chanx_right_out[5]:6 4.528657e-05 +10 ropt_net_172:3 chanx_right_out[5]:7 4.528657e-05 +11 ropt_net_172:5 chanx_right_out[13]:3 5.057814e-05 +12 ropt_net_172:6 chanx_right_out[13]:4 5.057814e-05 + +*RES +0 ropt_mt_inst_778:X ropt_net_172:8 0.152 +1 ropt_net_172:2 ropt_mt_inst_799:A 0.152 +2 ropt_net_172:4 ropt_net_172:3 0.004888393 +3 ropt_net_172:5 ropt_net_172:4 0.0045 +4 ropt_net_172:7 ropt_net_172:6 0.0045 +5 ropt_net_172:6 ropt_net_172:5 0.0014375 +6 ropt_net_172:8 ropt_net_172:7 0.001395089 +7 ropt_net_172:3 ropt_net_172:2 0.0003035715 + +*END + +*D_NET chanx_right_in[18] 0.02061334 //LENGTH 142.060 LUMPCC 0.006249906 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 140.450 50.320 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 76.535 39.100 +*I BUFT_P_99:A I *L 0.001776 *C 27.600 58.480 +*I mux_left_track_25\/mux_l1_in_2_:A1 I *L 0.00198 *C 37.720 47.260 +*N chanx_right_in[18]:4 *C 37.720 47.260 +*N chanx_right_in[18]:5 *C 27.623 58.508 +*N chanx_right_in[18]:6 *C 27.635 58.820 +*N chanx_right_in[18]:7 *C 28.015 58.820 +*N chanx_right_in[18]:8 *C 28.060 58.775 +*N chanx_right_in[18]:9 *C 28.060 53.765 +*N chanx_right_in[18]:10 *C 28.105 53.720 +*N chanx_right_in[18]:11 *C 36.755 53.720 +*N chanx_right_in[18]:12 *C 36.800 53.675 +*N chanx_right_in[18]:13 *C 36.800 47.985 +*N chanx_right_in[18]:14 *C 36.845 47.940 +*N chanx_right_in[18]:15 *C 37.720 47.940 +*N chanx_right_in[18]:16 *C 39.100 47.940 +*N chanx_right_in[18]:17 *C 39.100 48.280 +*N chanx_right_in[18]:18 *C 77.235 48.280 +*N chanx_right_in[18]:19 *C 77.280 48.235 +*N chanx_right_in[18]:20 *C 76.573 39.100 +*N chanx_right_in[18]:21 *C 77.235 39.100 +*N chanx_right_in[18]:22 *C 77.280 39.145 +*N chanx_right_in[18]:23 *C 77.280 46.920 +*N chanx_right_in[18]:24 *C 77.325 46.920 +*N chanx_right_in[18]:25 *C 103.455 46.920 +*N chanx_right_in[18]:26 *C 103.500 46.965 +*N chanx_right_in[18]:27 *C 103.500 50.263 +*N chanx_right_in[18]:28 *C 103.508 50.320 + +*CAP +0 chanx_right_in[18] 0.001132712 +1 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +2 BUFT_P_99:A 1e-06 +3 mux_left_track_25\/mux_l1_in_2_:A1 1e-06 +4 chanx_right_in[18]:4 8.293331e-05 +5 chanx_right_in[18]:5 3.19044e-05 +6 chanx_right_in[18]:6 8.937674e-05 +7 chanx_right_in[18]:7 5.747233e-05 +8 chanx_right_in[18]:8 0.0003420844 +9 chanx_right_in[18]:9 0.0003420844 +10 chanx_right_in[18]:10 0.0005171115 +11 chanx_right_in[18]:11 0.0005171115 +12 chanx_right_in[18]:12 0.0004305959 +13 chanx_right_in[18]:13 0.0004305959 +14 chanx_right_in[18]:14 7.89893e-05 +15 chanx_right_in[18]:15 0.0002300069 +16 chanx_right_in[18]:16 0.0001287978 +17 chanx_right_in[18]:17 0.001958208 +18 chanx_right_in[18]:18 0.001930301 +19 chanx_right_in[18]:19 8.40443e-05 +20 chanx_right_in[18]:20 6.337221e-05 +21 chanx_right_in[18]:21 6.337221e-05 +22 chanx_right_in[18]:22 0.0004289513 +23 chanx_right_in[18]:23 0.0005491694 +24 chanx_right_in[18]:24 0.001619045 +25 chanx_right_in[18]:25 0.001619045 +26 chanx_right_in[18]:26 0.0002502167 +27 chanx_right_in[18]:27 0.0002502167 +28 chanx_right_in[18]:28 0.001132712 +29 chanx_right_in[18]:24 chanx_right_in[9]:20 8.376945e-05 +30 chanx_right_in[18]:25 chanx_right_in[9]:21 8.376945e-05 +31 chanx_right_in[18]:18 chanx_right_in[9]:20 0.0002038732 +32 chanx_right_in[18]:18 chanx_right_in[9]:21 0.0006234781 +33 chanx_right_in[18]:17 chanx_right_in[9]:19 0.0002038732 +34 chanx_right_in[18]:17 chanx_right_in[9]:20 0.0006234781 +35 chanx_right_in[18] chanx_right_in[7]:8 0.0001833646 +36 chanx_right_in[18] chanx_right_in[7]:7 0.0003874587 +37 chanx_right_in[18]:24 chanx_right_in[7]:6 5.465669e-06 +38 chanx_right_in[18]:23 chanx_right_in[7]:5 3.167986e-06 +39 chanx_right_in[18]:25 chanx_right_in[7]:7 5.465669e-06 +40 chanx_right_in[18]:28 chanx_right_in[7]:6 0.0003874587 +41 chanx_right_in[18]:28 chanx_right_in[7]:7 0.0001833646 +42 chanx_right_in[18]:19 chanx_right_in[7]:4 3.167986e-06 +43 chanx_right_in[18]:18 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 4.013308e-05 +44 chanx_right_in[18]:17 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 4.013308e-05 +45 chanx_right_in[18] mux_tree_tapbuf_size8_1_sram[1]:22 5.753399e-06 +46 chanx_right_in[18] mux_tree_tapbuf_size8_1_sram[1]:26 0.0002923552 +47 chanx_right_in[18]:28 mux_tree_tapbuf_size8_1_sram[1]:27 0.0002923552 +48 chanx_right_in[18]:28 mux_tree_tapbuf_size8_1_sram[1]:21 5.753399e-06 +49 chanx_right_in[18]:18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.222246e-05 +50 chanx_right_in[18]:17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.222246e-05 +51 chanx_right_in[18] optlc_net_124:33 7.088273e-05 +52 chanx_right_in[18] optlc_net_124:20 0.0009596564 +53 chanx_right_in[18]:28 optlc_net_124:32 7.088273e-05 +54 chanx_right_in[18]:28 optlc_net_124:33 0.0009596564 +55 chanx_right_in[18]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.742755e-07 +56 chanx_right_in[18]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001925982 +57 chanx_right_in[18]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.742755e-07 +58 chanx_right_in[18]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001925982 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:28 0.005787658 +1 chanx_right_in[18]:24 chanx_right_in[18]:23 0.0045 +2 chanx_right_in[18]:23 chanx_right_in[18]:22 0.006941965 +3 chanx_right_in[18]:23 chanx_right_in[18]:19 0.001174107 +4 chanx_right_in[18]:25 chanx_right_in[18]:24 0.02333036 +5 chanx_right_in[18]:26 chanx_right_in[18]:25 0.0045 +6 chanx_right_in[18]:27 chanx_right_in[18]:26 0.002944197 +7 chanx_right_in[18]:28 chanx_right_in[18]:27 0.00341 +8 chanx_right_in[18]:21 chanx_right_in[18]:20 0.0005915179 +9 chanx_right_in[18]:22 chanx_right_in[18]:21 0.0045 +10 chanx_right_in[18]:20 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +11 chanx_right_in[18]:14 chanx_right_in[18]:13 0.0045 +12 chanx_right_in[18]:13 chanx_right_in[18]:12 0.005080357 +13 chanx_right_in[18]:11 chanx_right_in[18]:10 0.007723215 +14 chanx_right_in[18]:12 chanx_right_in[18]:11 0.0045 +15 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0045 +16 chanx_right_in[18]:9 chanx_right_in[18]:8 0.004473215 +17 chanx_right_in[18]:7 chanx_right_in[18]:6 0.0003392857 +18 chanx_right_in[18]:8 chanx_right_in[18]:7 0.0045 +19 chanx_right_in[18]:5 BUFT_P_99:A 0.152 +20 chanx_right_in[18]:4 mux_left_track_25\/mux_l1_in_2_:A1 0.152 +21 chanx_right_in[18]:18 chanx_right_in[18]:17 0.03404911 +22 chanx_right_in[18]:19 chanx_right_in[18]:18 0.0045 +23 chanx_right_in[18]:6 chanx_right_in[18]:5 0.0002111487 +24 chanx_right_in[18]:15 chanx_right_in[18]:14 0.00078125 +25 chanx_right_in[18]:15 chanx_right_in[18]:4 0.0006071429 +26 chanx_right_in[18]:16 chanx_right_in[18]:15 0.001232143 +27 chanx_right_in[18]:17 chanx_right_in[18]:16 0.0003035715 + +*END + +*D_NET chanx_right_in[11] 0.009559968 //LENGTH 64.170 LUMPCC 0.004061358 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 140.375 29.920 +*I mux_top_track_6\/mux_l1_in_2_:A0 I *L 0.001631 *C 90.910 42.500 +*N chanx_right_in[11]:2 *C 90.948 42.500 +*N chanx_right_in[11]:3 *C 91.495 42.500 +*N chanx_right_in[11]:4 *C 91.540 42.455 +*N chanx_right_in[11]:5 *C 91.540 35.418 +*N chanx_right_in[11]:6 *C 91.543 35.360 +*N chanx_right_in[11]:7 *C 91.985 35.360 +*N chanx_right_in[11]:8 *C 92.000 35.352 +*N chanx_right_in[11]:9 *C 92.000 30.608 +*N chanx_right_in[11]:10 *C 92.020 30.600 +*N chanx_right_in[11]:11 *C 136.160 30.600 +*N chanx_right_in[11]:12 *C 136.160 29.920 + +*CAP +0 chanx_right_in[11] 0.0002185688 +1 mux_top_track_6\/mux_l1_in_2_:A0 1e-06 +2 chanx_right_in[11]:2 5.602784e-05 +3 chanx_right_in[11]:3 5.602784e-05 +4 chanx_right_in[11]:4 0.0003391944 +5 chanx_right_in[11]:5 0.0003391944 +6 chanx_right_in[11]:6 5.511819e-05 +7 chanx_right_in[11]:7 5.511819e-05 +8 chanx_right_in[11]:8 0.0003522653 +9 chanx_right_in[11]:9 0.0003522653 +10 chanx_right_in[11]:10 0.001670827 +11 chanx_right_in[11]:11 0.00172763 +12 chanx_right_in[11]:12 0.0002753714 +13 chanx_right_in[11] chanx_right_in[6] 8.395441e-05 +14 chanx_right_in[11]:4 chanx_right_in[6]:5 5.177253e-05 +15 chanx_right_in[11]:4 chanx_right_in[6]:22 1.587425e-05 +16 chanx_right_in[11]:4 chanx_right_in[6]:24 2.406471e-05 +17 chanx_right_in[11]:5 chanx_right_in[6]:22 5.177253e-05 +18 chanx_right_in[11]:5 chanx_right_in[6]:23 1.587425e-05 +19 chanx_right_in[11]:5 chanx_right_in[6]:25 2.406471e-05 +20 chanx_right_in[11]:10 chanx_right_in[6]:26 1.63589e-05 +21 chanx_right_in[11]:10 chanx_right_in[6]:29 0.001547742 +22 chanx_right_in[11]:11 chanx_right_in[6] 0.001547742 +23 chanx_right_in[11]:11 chanx_right_in[6]:27 1.63589e-05 +24 chanx_right_in[11]:12 chanx_right_in[6]:29 8.395441e-05 +25 chanx_right_in[11]:10 mux_tree_tapbuf_size8_0_sram[0]:15 0.0002125957 +26 chanx_right_in[11]:10 mux_tree_tapbuf_size8_0_sram[0]:16 7.831665e-05 +27 chanx_right_in[11]:11 mux_tree_tapbuf_size8_0_sram[0]:17 7.831665e-05 +28 chanx_right_in[11]:11 mux_tree_tapbuf_size8_0_sram[0]:16 0.0002125957 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:12 0.00066035 +1 chanx_right_in[11]:2 mux_top_track_6\/mux_l1_in_2_:A0 0.152 +2 chanx_right_in[11]:3 chanx_right_in[11]:2 0.0004888393 +3 chanx_right_in[11]:4 chanx_right_in[11]:3 0.0045 +4 chanx_right_in[11]:5 chanx_right_in[11]:4 0.006283483 +5 chanx_right_in[11]:6 chanx_right_in[11]:5 0.00341 +6 chanx_right_in[11]:7 chanx_right_in[11]:6 6.499218e-05 +7 chanx_right_in[11]:8 chanx_right_in[11]:7 0.00341 +8 chanx_right_in[11]:10 chanx_right_in[11]:9 0.00341 +9 chanx_right_in[11]:9 chanx_right_in[11]:8 0.0007433833 +10 chanx_right_in[11]:11 chanx_right_in[11]:10 0.006915266 +11 chanx_right_in[11]:12 chanx_right_in[11]:11 0.0001065333 + +*END + +*D_NET right_top_grid_pin_46_[0] 0.004673475 //LENGTH 37.010 LUMPCC 0.0002720884 DR + +*CONN +*P right_top_grid_pin_46_[0] I *L 0.29796 *C 111.855 91.800 +*I mux_right_track_4\/mux_l1_in_3_:A0 I *L 0.001631 *C 110.230 71.740 +*I mux_right_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 115.630 64.260 +*I mux_right_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 114.080 72.420 +*N right_top_grid_pin_46_[0]:4 *C 114.080 72.420 +*N right_top_grid_pin_46_[0]:5 *C 115.593 64.260 +*N right_top_grid_pin_46_[0]:6 *C 114.125 64.260 +*N right_top_grid_pin_46_[0]:7 *C 114.080 64.305 +*N right_top_grid_pin_46_[0]:8 *C 114.080 72.035 +*N right_top_grid_pin_46_[0]:9 *C 114.080 72.080 +*N right_top_grid_pin_46_[0]:10 *C 110.267 71.740 +*N right_top_grid_pin_46_[0]:11 *C 111.780 71.740 +*N right_top_grid_pin_46_[0]:12 *C 111.780 72.080 +*N right_top_grid_pin_46_[0]:13 *C 111.780 72.125 +*N right_top_grid_pin_46_[0]:14 *C 111.780 77.860 +*N right_top_grid_pin_46_[0]:15 *C 111.320 77.860 +*N right_top_grid_pin_46_[0]:16 *C 111.320 91.743 +*N right_top_grid_pin_46_[0]:17 *C 111.328 91.800 + +*CAP +0 right_top_grid_pin_46_[0] 6.894777e-05 +1 mux_right_track_4\/mux_l1_in_3_:A0 1e-06 +2 mux_right_track_8\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_0\/mux_l2_in_1_:A1 1e-06 +4 right_top_grid_pin_46_[0]:4 6.616727e-05 +5 right_top_grid_pin_46_[0]:5 0.000134799 +6 right_top_grid_pin_46_[0]:6 0.000134799 +7 right_top_grid_pin_46_[0]:7 0.0005103835 +8 right_top_grid_pin_46_[0]:8 0.0005103835 +9 right_top_grid_pin_46_[0]:9 0.0002066102 +10 right_top_grid_pin_46_[0]:10 0.0001151316 +11 right_top_grid_pin_46_[0]:11 0.0001449492 +12 right_top_grid_pin_46_[0]:12 0.0001993867 +13 right_top_grid_pin_46_[0]:13 0.000320931 +14 right_top_grid_pin_46_[0]:14 0.0003474762 +15 right_top_grid_pin_46_[0]:15 0.0007980098 +16 right_top_grid_pin_46_[0]:16 0.0007714645 +17 right_top_grid_pin_46_[0]:17 6.894777e-05 +18 right_top_grid_pin_46_[0]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 7.162052e-05 +19 right_top_grid_pin_46_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:13 3.302863e-05 +20 right_top_grid_pin_46_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 3.110606e-05 +21 right_top_grid_pin_46_[0]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:10 3.110606e-05 +22 right_top_grid_pin_46_[0]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:12 3.331763e-05 +23 right_top_grid_pin_46_[0]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:11 7.190951e-05 + +*RES +0 right_top_grid_pin_46_[0] right_top_grid_pin_46_[0]:17 8.264167e-05 +1 right_top_grid_pin_46_[0]:4 mux_right_track_0\/mux_l2_in_1_:A1 0.152 +2 right_top_grid_pin_46_[0]:5 mux_right_track_8\/mux_l2_in_1_:A0 0.152 +3 right_top_grid_pin_46_[0]:6 right_top_grid_pin_46_[0]:5 0.001310268 +4 right_top_grid_pin_46_[0]:7 right_top_grid_pin_46_[0]:6 0.0045 +5 right_top_grid_pin_46_[0]:9 right_top_grid_pin_46_[0]:8 0.0045 +6 right_top_grid_pin_46_[0]:9 right_top_grid_pin_46_[0]:4 0.0001465517 +7 right_top_grid_pin_46_[0]:8 right_top_grid_pin_46_[0]:7 0.006901787 +8 right_top_grid_pin_46_[0]:12 right_top_grid_pin_46_[0]:11 0.0003035714 +9 right_top_grid_pin_46_[0]:12 right_top_grid_pin_46_[0]:9 0.002053571 +10 right_top_grid_pin_46_[0]:13 right_top_grid_pin_46_[0]:12 0.0045 +11 right_top_grid_pin_46_[0]:16 right_top_grid_pin_46_[0]:15 0.01239509 +12 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:16 0.00341 +13 right_top_grid_pin_46_[0]:10 mux_right_track_4\/mux_l1_in_3_:A0 0.152 +14 right_top_grid_pin_46_[0]:11 right_top_grid_pin_46_[0]:10 0.001350446 +15 right_top_grid_pin_46_[0]:15 right_top_grid_pin_46_[0]:14 0.0004107143 +16 right_top_grid_pin_46_[0]:14 right_top_grid_pin_46_[0]:13 0.005120535 + +*END + +*D_NET chanx_left_in[0] 0.006729629 //LENGTH 47.000 LUMPCC 0.00140414 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.230 67.320 +*I mux_top_track_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 44.335 69.700 +*N chanx_left_in[0]:2 *C 44.297 69.700 +*N chanx_left_in[0]:3 *C 41.905 69.700 +*N chanx_left_in[0]:4 *C 41.860 69.655 +*N chanx_left_in[0]:5 *C 41.860 68.737 +*N chanx_left_in[0]:6 *C 41.852 68.680 +*N chanx_left_in[0]:7 *C 6.908 68.680 +*N chanx_left_in[0]:8 *C 6.900 68.623 +*N chanx_left_in[0]:9 *C 6.900 67.377 +*N chanx_left_in[0]:10 *C 6.893 67.320 + +*CAP +0 chanx_left_in[0] 0.0002964629 +1 mux_top_track_0\/mux_l2_in_2_:A0 1e-06 +2 chanx_left_in[0]:2 0.0002046324 +3 chanx_left_in[0]:3 0.0002046324 +4 chanx_left_in[0]:4 7.670259e-05 +5 chanx_left_in[0]:5 7.670259e-05 +6 chanx_left_in[0]:6 0.001977196 +7 chanx_left_in[0]:7 0.001977196 +8 chanx_left_in[0]:8 0.0001072504 +9 chanx_left_in[0]:9 0.0001072504 +10 chanx_left_in[0]:10 0.0002964629 +11 chanx_left_in[0] chanx_left_in[11] 7.3478e-05 +12 chanx_left_in[0]:6 chanx_left_in[11]:11 0.0006285923 +13 chanx_left_in[0]:7 chanx_left_in[11] 0.0006285923 +14 chanx_left_in[0]:10 chanx_left_in[11]:11 7.3478e-05 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:10 0.000887125 +1 chanx_left_in[0]:2 mux_top_track_0\/mux_l2_in_2_:A0 0.152 +2 chanx_left_in[0]:3 chanx_left_in[0]:2 0.002136161 +3 chanx_left_in[0]:4 chanx_left_in[0]:3 0.0045 +4 chanx_left_in[0]:5 chanx_left_in[0]:4 0.0008191965 +5 chanx_left_in[0]:6 chanx_left_in[0]:5 0.00341 +6 chanx_left_in[0]:8 chanx_left_in[0]:7 0.00341 +7 chanx_left_in[0]:7 chanx_left_in[0]:6 0.005474716 +8 chanx_left_in[0]:9 chanx_left_in[0]:8 0.001111607 +9 chanx_left_in[0]:10 chanx_left_in[0]:9 0.00341 + +*END + +*D_NET chanx_left_in[3] 0.01296102 //LENGTH 95.330 LUMPCC 0.003860306 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 53.040 +*I mux_top_track_36\/mux_l1_in_0_:A0 I *L 0.001631 *C 54.915 93.160 +*N chanx_left_in[3]:2 *C 54.878 93.160 +*N chanx_left_in[3]:3 *C 44.205 93.160 +*N chanx_left_in[3]:4 *C 44.160 93.115 +*N chanx_left_in[3]:5 *C 44.160 88.458 +*N chanx_left_in[3]:6 *C 44.153 88.400 +*N chanx_left_in[3]:7 *C 31.300 88.400 +*N chanx_left_in[3]:8 *C 31.280 88.392 +*N chanx_left_in[3]:9 *C 31.280 53.047 +*N chanx_left_in[3]:10 *C 31.260 53.040 + +*CAP +0 chanx_left_in[3] 0.00105833 +1 mux_top_track_36\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[3]:2 0.0007377121 +3 chanx_left_in[3]:3 0.0007377121 +4 chanx_left_in[3]:4 0.0002585404 +5 chanx_left_in[3]:5 0.0002585404 +6 chanx_left_in[3]:6 0.0008159496 +7 chanx_left_in[3]:7 0.0008159496 +8 chanx_left_in[3]:8 0.001679325 +9 chanx_left_in[3]:9 0.001679325 +10 chanx_left_in[3]:10 0.00105833 +11 chanx_left_in[3] chanx_left_in[2] 0.0003511653 +12 chanx_left_in[3]:10 chanx_left_in[2]:28 0.0003511653 +13 chanx_left_in[3] chanx_left_in[13]:27 0.0006708858 +14 chanx_left_in[3]:10 chanx_left_in[13]:26 0.0006708858 +15 chanx_left_in[3]:8 chanx_left_in[15]:12 0.0003945221 +16 chanx_left_in[3]:9 chanx_left_in[15]:13 0.0003945221 +17 chanx_left_in[3]:4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.311203e-05 +18 chanx_left_in[3]:5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.311203e-05 +19 chanx_left_in[3] mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004704679 +20 chanx_left_in[3]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004704679 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:10 0.0047047 +1 chanx_left_in[3]:2 mux_top_track_36\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[3]:3 chanx_left_in[3]:2 0.009529018 +3 chanx_left_in[3]:4 chanx_left_in[3]:3 0.0045 +4 chanx_left_in[3]:5 chanx_left_in[3]:4 0.004158483 +5 chanx_left_in[3]:6 chanx_left_in[3]:5 0.00341 +6 chanx_left_in[3]:7 chanx_left_in[3]:6 0.002013558 +7 chanx_left_in[3]:8 chanx_left_in[3]:7 0.00341 +8 chanx_left_in[3]:10 chanx_left_in[3]:9 0.00341 +9 chanx_left_in[3]:9 chanx_left_in[3]:8 0.005537383 + +*END + +*D_NET left_top_grid_pin_42_[0] 0.009716768 //LENGTH 64.445 LUMPCC 0.003337528 DR + +*CONN +*P left_top_grid_pin_42_[0] I *L 0.29796 *C 7.360 74.835 +*I mux_left_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 21.335 53.380 +*I mux_left_track_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 25.760 52.700 +*I mux_left_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 32.835 65.960 +*N left_top_grid_pin_42_[0]:4 *C 32.835 65.960 +*N left_top_grid_pin_42_[0]:5 *C 33.120 65.960 +*N left_top_grid_pin_42_[0]:6 *C 33.120 65.915 +*N left_top_grid_pin_42_[0]:7 *C 33.120 64.657 +*N left_top_grid_pin_42_[0]:8 *C 25.760 52.700 +*N left_top_grid_pin_42_[0]:9 *C 21.373 53.380 +*N left_top_grid_pin_42_[0]:10 *C 25.760 53.380 +*N left_top_grid_pin_42_[0]:11 *C 29.395 53.380 +*N left_top_grid_pin_42_[0]:12 *C 29.440 53.425 +*N left_top_grid_pin_42_[0]:13 *C 29.440 55.023 +*N left_top_grid_pin_42_[0]:14 *C 29.448 55.080 +*N left_top_grid_pin_42_[0]:15 *C 33.100 55.080 +*N left_top_grid_pin_42_[0]:16 *C 33.120 55.088 +*N left_top_grid_pin_42_[0]:17 *C 33.120 64.593 +*N left_top_grid_pin_42_[0]:18 *C 33.113 64.600 +*N left_top_grid_pin_42_[0]:19 *C 11.060 64.600 +*N left_top_grid_pin_42_[0]:20 *C 11.040 64.608 +*N left_top_grid_pin_42_[0]:21 *C 11.040 72.752 +*N left_top_grid_pin_42_[0]:22 *C 11.020 72.760 +*N left_top_grid_pin_42_[0]:23 *C 7.368 72.760 +*N left_top_grid_pin_42_[0]:24 *C 7.360 72.818 + +*CAP +0 left_top_grid_pin_42_[0] 0.0001217787 +1 mux_left_track_5\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_9\/mux_l2_in_2_:A1 1e-06 +3 mux_left_track_1\/mux_l1_in_2_:A0 1e-06 +4 left_top_grid_pin_42_[0]:4 5.215776e-05 +5 left_top_grid_pin_42_[0]:5 5.573624e-05 +6 left_top_grid_pin_42_[0]:6 6.785138e-05 +7 left_top_grid_pin_42_[0]:7 6.785138e-05 +8 left_top_grid_pin_42_[0]:8 7.770822e-05 +9 left_top_grid_pin_42_[0]:9 0.0003322714 +10 left_top_grid_pin_42_[0]:10 0.0006658155 +11 left_top_grid_pin_42_[0]:11 0.0002858757 +12 left_top_grid_pin_42_[0]:12 0.0001151843 +13 left_top_grid_pin_42_[0]:13 0.0001151843 +14 left_top_grid_pin_42_[0]:14 0.0001520159 +15 left_top_grid_pin_42_[0]:15 0.0001520159 +16 left_top_grid_pin_42_[0]:16 0.0006082612 +17 left_top_grid_pin_42_[0]:17 0.0006082612 +18 left_top_grid_pin_42_[0]:18 0.000698323 +19 left_top_grid_pin_42_[0]:19 0.000698323 +20 left_top_grid_pin_42_[0]:20 0.0005074211 +21 left_top_grid_pin_42_[0]:21 0.0005074211 +22 left_top_grid_pin_42_[0]:22 0.0001825016 +23 left_top_grid_pin_42_[0]:23 0.0001825016 +24 left_top_grid_pin_42_[0]:24 0.0001217787 +25 left_top_grid_pin_42_[0]:19 chanx_right_in[2]:23 0.0004613201 +26 left_top_grid_pin_42_[0]:18 chanx_right_in[2]:24 0.0004613201 +27 left_top_grid_pin_42_[0]:19 chanx_right_in[12]:14 0.0003938644 +28 left_top_grid_pin_42_[0]:18 chanx_right_in[12]:15 0.0003938644 +29 left_top_grid_pin_42_[0]:7 chanx_right_in[12]:16 3.995525e-06 +30 left_top_grid_pin_42_[0]:7 chanx_right_in[12]:17 3.858179e-05 +31 left_top_grid_pin_42_[0]:6 chanx_right_in[12]:9 3.995525e-06 +32 left_top_grid_pin_42_[0]:6 chanx_right_in[12]:16 3.858179e-05 +33 left_top_grid_pin_42_[0]:23 left_top_grid_pin_44_[0]:23 0.0002243893 +34 left_top_grid_pin_42_[0]:22 left_top_grid_pin_44_[0]:22 0.0002243893 +35 left_top_grid_pin_42_[0]:16 left_top_grid_pin_44_[0]:20 5.746676e-05 +36 left_top_grid_pin_42_[0]:17 left_top_grid_pin_44_[0]:21 5.746676e-05 +37 left_top_grid_pin_42_[0]:19 mux_tree_tapbuf_size10_0_sram[2]:13 0.0002690524 +38 left_top_grid_pin_42_[0]:18 mux_tree_tapbuf_size10_0_sram[2]:14 0.0002690524 +39 left_top_grid_pin_42_[0]:14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002200937 +40 left_top_grid_pin_42_[0]:15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002200937 + +*RES +0 left_top_grid_pin_42_[0] left_top_grid_pin_42_[0]:24 0.001801339 +1 left_top_grid_pin_42_[0]:8 mux_left_track_9\/mux_l2_in_2_:A1 0.152 +2 left_top_grid_pin_42_[0]:24 left_top_grid_pin_42_[0]:23 0.00341 +3 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:22 0.000572225 +4 left_top_grid_pin_42_[0]:22 left_top_grid_pin_42_[0]:21 0.00341 +5 left_top_grid_pin_42_[0]:21 left_top_grid_pin_42_[0]:20 0.00127605 +6 left_top_grid_pin_42_[0]:19 left_top_grid_pin_42_[0]:18 0.003454892 +7 left_top_grid_pin_42_[0]:20 left_top_grid_pin_42_[0]:19 0.00341 +8 left_top_grid_pin_42_[0]:9 mux_left_track_5\/mux_l1_in_2_:A0 0.152 +9 left_top_grid_pin_42_[0]:11 left_top_grid_pin_42_[0]:10 0.003245536 +10 left_top_grid_pin_42_[0]:12 left_top_grid_pin_42_[0]:11 0.0045 +11 left_top_grid_pin_42_[0]:13 left_top_grid_pin_42_[0]:12 0.001426339 +12 left_top_grid_pin_42_[0]:14 left_top_grid_pin_42_[0]:13 0.00341 +13 left_top_grid_pin_42_[0]:15 left_top_grid_pin_42_[0]:14 0.000572225 +14 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:15 0.00341 +15 left_top_grid_pin_42_[0]:18 left_top_grid_pin_42_[0]:17 0.00341 +16 left_top_grid_pin_42_[0]:18 left_top_grid_pin_42_[0]:7 0.00341 +17 left_top_grid_pin_42_[0]:17 left_top_grid_pin_42_[0]:16 0.001489117 +18 left_top_grid_pin_42_[0]:7 left_top_grid_pin_42_[0]:6 0.001122768 +19 left_top_grid_pin_42_[0]:5 left_top_grid_pin_42_[0]:4 0.0001548913 +20 left_top_grid_pin_42_[0]:6 left_top_grid_pin_42_[0]:5 0.0045 +21 left_top_grid_pin_42_[0]:4 mux_left_track_1\/mux_l1_in_2_:A0 0.152 +22 left_top_grid_pin_42_[0]:10 left_top_grid_pin_42_[0]:9 0.003917411 +23 left_top_grid_pin_42_[0]:10 left_top_grid_pin_42_[0]:8 0.0006071429 + +*END + +*D_NET left_bottom_grid_pin_1_[0] 0.01071685 //LENGTH 93.975 LUMPCC 0.0004528412 DR + +*CONN +*P left_bottom_grid_pin_1_[0] I *L 0.29796 *C 2.300 1.290 +*I mux_left_track_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 18.400 30.940 +*I mux_left_track_5\/mux_l1_in_6_:A0 I *L 0.001631 *C 9.410 48.280 +*I mux_left_track_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 21.720 58.140 +*N left_bottom_grid_pin_1_[0]:4 *C 21.683 58.140 +*N left_bottom_grid_pin_1_[0]:5 *C 20.745 58.140 +*N left_bottom_grid_pin_1_[0]:6 *C 20.700 58.095 +*N left_bottom_grid_pin_1_[0]:7 *C 20.700 49.698 +*N left_bottom_grid_pin_1_[0]:8 *C 20.693 49.640 +*N left_bottom_grid_pin_1_[0]:9 *C 9.410 48.280 +*N left_bottom_grid_pin_1_[0]:10 *C 9.660 48.280 +*N left_bottom_grid_pin_1_[0]:11 *C 9.660 48.325 +*N left_bottom_grid_pin_1_[0]:12 *C 9.660 49.583 +*N left_bottom_grid_pin_1_[0]:13 *C 9.660 49.640 +*N left_bottom_grid_pin_1_[0]:14 *C 7.368 49.640 +*N left_bottom_grid_pin_1_[0]:15 *C 7.360 49.583 +*N left_bottom_grid_pin_1_[0]:16 *C 7.360 31.325 +*N left_bottom_grid_pin_1_[0]:17 *C 7.360 31.280 +*N left_bottom_grid_pin_1_[0]:18 *C 18.363 30.940 +*N left_bottom_grid_pin_1_[0]:19 *C 7.360 30.940 +*N left_bottom_grid_pin_1_[0]:20 *C 1.885 30.940 +*N left_bottom_grid_pin_1_[0]:21 *C 1.840 30.895 +*N left_bottom_grid_pin_1_[0]:22 *C 1.840 28.220 +*N left_bottom_grid_pin_1_[0]:23 *C 1.380 28.220 +*N left_bottom_grid_pin_1_[0]:24 *C 1.380 25.500 +*N left_bottom_grid_pin_1_[0]:25 *C 1.840 25.500 +*N left_bottom_grid_pin_1_[0]:26 *C 1.840 9.860 +*N left_bottom_grid_pin_1_[0]:27 *C 2.300 9.860 + +*CAP +0 left_bottom_grid_pin_1_[0] 0.0004066497 +1 mux_left_track_9\/mux_l2_in_3_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_6_:A0 1e-06 +3 mux_left_track_1\/mux_l2_in_3_:A1 1e-06 +4 left_bottom_grid_pin_1_[0]:4 0.0001022092 +5 left_bottom_grid_pin_1_[0]:5 0.0001022092 +6 left_bottom_grid_pin_1_[0]:6 0.0004701815 +7 left_bottom_grid_pin_1_[0]:7 0.0004701815 +8 left_bottom_grid_pin_1_[0]:8 0.0007762273 +9 left_bottom_grid_pin_1_[0]:9 4.911971e-05 +10 left_bottom_grid_pin_1_[0]:10 5.321798e-05 +11 left_bottom_grid_pin_1_[0]:11 6.307464e-05 +12 left_bottom_grid_pin_1_[0]:12 6.307464e-05 +13 left_bottom_grid_pin_1_[0]:13 0.0009518111 +14 left_bottom_grid_pin_1_[0]:14 0.0001755838 +15 left_bottom_grid_pin_1_[0]:15 0.0009160616 +16 left_bottom_grid_pin_1_[0]:16 0.0009160616 +17 left_bottom_grid_pin_1_[0]:17 6.150545e-05 +18 left_bottom_grid_pin_1_[0]:18 0.0006256002 +19 left_bottom_grid_pin_1_[0]:19 0.0009611947 +20 left_bottom_grid_pin_1_[0]:20 0.0003071231 +21 left_bottom_grid_pin_1_[0]:21 0.0001596192 +22 left_bottom_grid_pin_1_[0]:22 0.0001906805 +23 left_bottom_grid_pin_1_[0]:23 0.0001886955 +24 left_bottom_grid_pin_1_[0]:24 0.0001829728 +25 left_bottom_grid_pin_1_[0]:25 0.0008161976 +26 left_bottom_grid_pin_1_[0]:26 0.0008179802 +27 left_bottom_grid_pin_1_[0]:27 0.0004337709 +28 left_bottom_grid_pin_1_[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.95321e-05 +29 left_bottom_grid_pin_1_[0]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.95321e-05 +30 left_bottom_grid_pin_1_[0]:20 ropt_net_175:2 4.569829e-05 +31 left_bottom_grid_pin_1_[0]:21 ropt_net_175:4 4.491728e-06 +32 left_bottom_grid_pin_1_[0]:19 ropt_net_175:3 4.569829e-05 +33 left_bottom_grid_pin_1_[0]:22 ropt_net_175:5 4.491728e-06 +34 left_bottom_grid_pin_1_[0]:15 ropt_net_143:3 9.601449e-05 +35 left_bottom_grid_pin_1_[0]:16 ropt_net_143:4 9.601449e-05 +36 left_bottom_grid_pin_1_[0]:15 ropt_net_164:4 4.068397e-05 +37 left_bottom_grid_pin_1_[0]:16 ropt_net_164:5 4.068397e-05 + +*RES +0 left_bottom_grid_pin_1_[0] left_bottom_grid_pin_1_[0]:27 0.007651785 +1 left_bottom_grid_pin_1_[0]:9 mux_left_track_5\/mux_l1_in_6_:A0 0.152 +2 left_bottom_grid_pin_1_[0]:10 left_bottom_grid_pin_1_[0]:9 0.0001358696 +3 left_bottom_grid_pin_1_[0]:11 left_bottom_grid_pin_1_[0]:10 0.0045 +4 left_bottom_grid_pin_1_[0]:12 left_bottom_grid_pin_1_[0]:11 0.001122768 +5 left_bottom_grid_pin_1_[0]:13 left_bottom_grid_pin_1_[0]:12 0.00341 +6 left_bottom_grid_pin_1_[0]:13 left_bottom_grid_pin_1_[0]:8 0.001728425 +7 left_bottom_grid_pin_1_[0]:15 left_bottom_grid_pin_1_[0]:14 0.00341 +8 left_bottom_grid_pin_1_[0]:14 left_bottom_grid_pin_1_[0]:13 0.0003591584 +9 left_bottom_grid_pin_1_[0]:17 left_bottom_grid_pin_1_[0]:16 0.0045 +10 left_bottom_grid_pin_1_[0]:16 left_bottom_grid_pin_1_[0]:15 0.01630134 +11 left_bottom_grid_pin_1_[0]:7 left_bottom_grid_pin_1_[0]:6 0.007497768 +12 left_bottom_grid_pin_1_[0]:8 left_bottom_grid_pin_1_[0]:7 0.00341 +13 left_bottom_grid_pin_1_[0]:5 left_bottom_grid_pin_1_[0]:4 0.0008370536 +14 left_bottom_grid_pin_1_[0]:6 left_bottom_grid_pin_1_[0]:5 0.0045 +15 left_bottom_grid_pin_1_[0]:4 mux_left_track_1\/mux_l2_in_3_:A1 0.152 +16 left_bottom_grid_pin_1_[0]:18 mux_left_track_9\/mux_l2_in_3_:A1 0.152 +17 left_bottom_grid_pin_1_[0]:20 left_bottom_grid_pin_1_[0]:19 0.004888393 +18 left_bottom_grid_pin_1_[0]:21 left_bottom_grid_pin_1_[0]:20 0.0045 +19 left_bottom_grid_pin_1_[0]:19 left_bottom_grid_pin_1_[0]:18 0.009823661 +20 left_bottom_grid_pin_1_[0]:19 left_bottom_grid_pin_1_[0]:17 0.0003035715 +21 left_bottom_grid_pin_1_[0]:24 left_bottom_grid_pin_1_[0]:23 0.002428571 +22 left_bottom_grid_pin_1_[0]:23 left_bottom_grid_pin_1_[0]:22 0.0004107143 +23 left_bottom_grid_pin_1_[0]:25 left_bottom_grid_pin_1_[0]:24 0.0004107143 +24 left_bottom_grid_pin_1_[0]:22 left_bottom_grid_pin_1_[0]:21 0.002388393 +25 left_bottom_grid_pin_1_[0]:26 left_bottom_grid_pin_1_[0]:25 0.01396429 +26 left_bottom_grid_pin_1_[0]:27 left_bottom_grid_pin_1_[0]:26 0.0004107143 + +*END + +*D_NET ropt_net_132 0.0005762519 //LENGTH 3.510 LUMPCC 0.0002603587 DR + +*CONN +*I mux_top_track_20\/BUFT_P_101:X O *L 0 *C 93.840 99.280 +*I ropt_mt_inst_755:A I *L 0.001766 *C 97.060 99.280 +*N ropt_net_132:2 *C 97.023 99.280 +*N ropt_net_132:3 *C 93.877 99.280 + +*CAP +0 mux_top_track_20\/BUFT_P_101:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_132:2 0.0001569466 +3 ropt_net_132:3 0.0001569466 +4 ropt_net_132:2 chany_top_out[14]:3 0.0001301793 +5 ropt_net_132:3 chany_top_out[14]:4 0.0001301793 + +*RES +0 mux_top_track_20\/BUFT_P_101:X ropt_net_132:3 0.152 +1 ropt_net_132:2 ropt_mt_inst_755:A 0.152 +2 ropt_net_132:3 ropt_net_132:2 0.002808036 + +*END + +*D_NET chany_top_out[14] 0.001221611 //LENGTH 10.035 LUMPCC 0.0002603587 DR + +*CONN +*I mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 91.080 98.940 +*P chany_top_out[14] O *L 0.7423 *C 97.520 102.070 +*N chany_top_out[14]:2 *C 97.520 98.985 +*N chany_top_out[14]:3 *C 97.475 98.940 +*N chany_top_out[14]:4 *C 91.118 98.940 + +*CAP +0 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[14] 0.0001677887 +2 chany_top_out[14]:2 0.0001677887 +3 chany_top_out[14]:3 0.0003123377 +4 chany_top_out[14]:4 0.0003123377 +5 chany_top_out[14]:3 ropt_net_132:2 0.0001301793 +6 chany_top_out[14]:4 ropt_net_132:3 0.0001301793 + +*RES +0 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[14]:4 0.152 +1 chany_top_out[14]:3 chany_top_out[14]:2 0.0045 +2 chany_top_out[14]:2 chany_top_out[14] 0.002754464 +3 chany_top_out[14]:4 chany_top_out[14]:3 0.005676339 + +*END + +*D_NET chany_top_out[18] 0.002952095 //LENGTH 24.815 LUMPCC 0 DR + +*CONN +*I mux_top_track_36\/mux_l2_in_0_:X O *L 0 *C 77.520 95.880 +*P chany_top_out[18] O *L 0.7423 *C 95.680 102.070 +*N chany_top_out[18]:2 *C 95.680 95.925 +*N chany_top_out[18]:3 *C 95.635 95.880 +*N chany_top_out[18]:4 *C 77.558 95.880 + +*CAP +0 mux_top_track_36\/mux_l2_in_0_:X 1e-06 +1 chany_top_out[18] 0.0003156642 +2 chany_top_out[18]:2 0.0003156642 +3 chany_top_out[18]:3 0.001159883 +4 chany_top_out[18]:4 0.001159883 + +*RES +0 mux_top_track_36\/mux_l2_in_0_:X chany_top_out[18]:4 0.152 +1 chany_top_out[18]:4 chany_top_out[18]:3 0.01614063 +2 chany_top_out[18]:3 chany_top_out[18]:2 0.0045 +3 chany_top_out[18]:2 chany_top_out[18] 0.005486608 + +*END + +*D_NET chanx_right_out[4] 0.0005899495 //LENGTH 4.320 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 138.060 34.000 +*P chanx_right_out[4] O *L 0.7423 *C 140.450 35.360 +*N chanx_right_out[4]:2 *C 138.007 35.360 +*N chanx_right_out[4]:3 *C 138.000 35.303 +*N chanx_right_out[4]:4 *C 138.000 34.045 +*N chanx_right_out[4]:5 *C 138.000 34.000 + +*CAP +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[4] 0.0001896561 +2 chanx_right_out[4]:2 0.0001896561 +3 chanx_right_out[4]:3 9.005265e-05 +4 chanx_right_out[4]:4 9.005265e-05 +5 chanx_right_out[4]:5 2.953196e-05 + +*RES +0 mux_right_track_8\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[4]:5 0.152 +1 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +2 chanx_right_out[4]:4 chanx_right_out[4]:3 0.001122768 +3 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +4 chanx_right_out[4]:2 chanx_right_out[4] 0.0003826583 + +*END + +*D_NET chanx_left_out[2] 0.002312558 //LENGTH 20.530 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.180 28.220 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 15.640 +*N chanx_left_out[2]:2 *C 5.513 15.640 +*N chanx_left_out[2]:3 *C 5.520 15.698 +*N chanx_left_out[2]:4 *C 5.520 28.175 +*N chanx_left_out[2]:5 *C 5.543 28.220 +*N chanx_left_out[2]:6 *C 5.948 28.220 +*N chanx_left_out[2]:7 *C 8.143 28.220 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 0.0002588642 +2 chanx_left_out[2]:2 0.0002588642 +3 chanx_left_out[2]:3 0.0006948808 +4 chanx_left_out[2]:4 0.0006948808 +5 chanx_left_out[2]:5 4.770317e-05 +6 chanx_left_out[2]:6 0.000202034 +7 chanx_left_out[2]:7 0.0001543308 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:7 0.152 +1 chanx_left_out[2]:7 chanx_left_out[2]:6 0.001959821 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.01114063 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.000670925 +6 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0002201087 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.006238841 //LENGTH 46.340 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.165 75.140 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 40.580 72.080 +*I mux_left_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 38.540 69.360 +*I mux_left_track_1\/mux_l2_in_2_:S I *L 0.00357 *C 23.820 63.240 +*I mux_left_track_1\/mux_l2_in_3_:S I *L 0.00357 *C 22.440 57.800 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 30.075 64.260 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 30.113 64.260 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 22.478 57.800 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 22.955 57.800 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 23.000 57.845 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 23.000 59.115 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 23.045 59.160 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 23.820 63.240 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 23.920 63.195 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 23.920 59.205 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 23.920 59.160 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 30.775 59.160 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 30.820 59.205 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 30.820 64.215 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 30.820 64.290 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 30.820 64.600 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 39.055 64.600 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 39.100 64.645 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 38.578 69.360 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 39.055 69.360 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 39.100 69.360 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 39.100 72.035 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 39.145 72.080 +*N mux_tree_tapbuf_size10_0_sram[1]:28 *C 40.492 72.080 +*N mux_tree_tapbuf_size10_0_sram[1]:29 *C 40.480 72.125 +*N mux_tree_tapbuf_size10_0_sram[1]:30 *C 40.480 75.095 +*N mux_tree_tapbuf_size10_0_sram[1]:31 *C 40.525 75.140 +*N mux_tree_tapbuf_size10_0_sram[1]:32 *C 42.128 75.140 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_1\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_1\/mux_l2_in_2_:S 1e-06 +4 mux_left_track_1\/mux_l2_in_3_:S 1e-06 +5 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 6.303658e-05 +7 mux_tree_tapbuf_size10_0_sram[1]:7 6.706859e-05 +8 mux_tree_tapbuf_size10_0_sram[1]:8 6.706859e-05 +9 mux_tree_tapbuf_size10_0_sram[1]:9 0.000104926 +10 mux_tree_tapbuf_size10_0_sram[1]:10 0.000104926 +11 mux_tree_tapbuf_size10_0_sram[1]:11 8.974445e-05 +12 mux_tree_tapbuf_size10_0_sram[1]:12 2.769805e-05 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.0003121253 +14 mux_tree_tapbuf_size10_0_sram[1]:14 0.0003121253 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0006608598 +16 mux_tree_tapbuf_size10_0_sram[1]:16 0.0005363824 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0003547152 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.0003547152 +19 mux_tree_tapbuf_size10_0_sram[1]:19 9.0988e-05 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0006064852 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0005785337 +22 mux_tree_tapbuf_size10_0_sram[1]:22 0.000278259 +23 mux_tree_tapbuf_size10_0_sram[1]:23 6.253588e-05 +24 mux_tree_tapbuf_size10_0_sram[1]:24 6.253588e-05 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0004788473 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.0001659623 +27 mux_tree_tapbuf_size10_0_sram[1]:27 0.00012082 +28 mux_tree_tapbuf_size10_0_sram[1]:28 0.00012082 +29 mux_tree_tapbuf_size10_0_sram[1]:29 0.0001814629 +30 mux_tree_tapbuf_size10_0_sram[1]:30 0.0001814629 +31 mux_tree_tapbuf_size10_0_sram[1]:31 0.0001243684 +32 mux_tree_tapbuf_size10_0_sram[1]:32 0.0001243684 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:7 mux_left_track_1\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:7 0.0004263393 +3 mux_tree_tapbuf_size10_0_sram[1]:9 mux_tree_tapbuf_size10_0_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.001133929 +6 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0045 +7 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:11 0.00078125 +8 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:13 0.0035625 +9 mux_tree_tapbuf_size10_0_sram[1]:12 mux_left_track_1\/mux_l2_in_2_:S 0.152 +10 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +11 mux_tree_tapbuf_size10_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:26 0.0045 +12 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.002388393 +13 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.0045 +14 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:6 0.0006316965 +15 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.004473215 +16 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.006120536 +17 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +18 mux_tree_tapbuf_size10_0_sram[1]:6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +19 mux_tree_tapbuf_size10_0_sram[1]:28 mux_left_track_1\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size10_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:27 0.001203125 +21 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:28 0.0045 +22 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:30 0.0045 +23 mux_tree_tapbuf_size10_0_sram[1]:30 mux_tree_tapbuf_size10_0_sram[1]:29 0.002651786 +24 mux_tree_tapbuf_size10_0_sram[1]:32 mux_tree_tapbuf_size10_0_sram[1]:31 0.001430804 +25 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.007352679 +26 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.0045 +27 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.0004263393 +28 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0045 +29 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:22 0.004209821 +30 mux_tree_tapbuf_size10_0_sram[1]:23 mux_left_track_1\/mux_l2_in_1_:S 0.152 +31 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[1] 0.00544879 //LENGTH 37.925 LUMPCC 0.0001999959 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 35.615 49.640 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 30.000 52.360 +*I mux_left_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 20.800 50.615 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.640 44.540 +*I mux_left_track_5\/mux_l2_in_3_:S I *L 0.00357 *C 11.400 50.320 +*I mux_left_track_5\/mux_l2_in_2_:S I *L 0.00357 *C 13.440 50.615 +*N mux_tree_tapbuf_size14_1_sram[1]:6 *C 13.440 50.615 +*N mux_tree_tapbuf_size14_1_sram[1]:7 *C 11.438 50.320 +*N mux_tree_tapbuf_size14_1_sram[1]:8 *C 13.440 50.320 +*N mux_tree_tapbuf_size14_1_sram[1]:9 *C 17.640 44.540 +*N mux_tree_tapbuf_size14_1_sram[1]:10 *C 17.480 44.540 +*N mux_tree_tapbuf_size14_1_sram[1]:11 *C 17.480 44.585 +*N mux_tree_tapbuf_size14_1_sram[1]:12 *C 17.480 50.275 +*N mux_tree_tapbuf_size14_1_sram[1]:13 *C 17.480 50.320 +*N mux_tree_tapbuf_size14_1_sram[1]:14 *C 20.742 50.320 +*N mux_tree_tapbuf_size14_1_sram[1]:15 *C 20.800 50.615 +*N mux_tree_tapbuf_size14_1_sram[1]:16 *C 20.800 51.000 +*N mux_tree_tapbuf_size14_1_sram[1]:17 *C 24.335 51.000 +*N mux_tree_tapbuf_size14_1_sram[1]:18 *C 24.380 51.045 +*N mux_tree_tapbuf_size14_1_sram[1]:19 *C 24.380 52.315 +*N mux_tree_tapbuf_size14_1_sram[1]:20 *C 24.425 52.360 +*N mux_tree_tapbuf_size14_1_sram[1]:21 *C 30.000 52.360 +*N mux_tree_tapbuf_size14_1_sram[1]:22 *C 31.235 52.360 +*N mux_tree_tapbuf_size14_1_sram[1]:23 *C 31.280 52.315 +*N mux_tree_tapbuf_size14_1_sram[1]:24 *C 31.280 49.685 +*N mux_tree_tapbuf_size14_1_sram[1]:25 *C 31.325 49.640 +*N mux_tree_tapbuf_size14_1_sram[1]:26 *C 35.578 49.640 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_5\/mux_l2_in_1_:S 1e-06 +3 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_left_track_5\/mux_l2_in_3_:S 1e-06 +5 mux_left_track_5\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size14_1_sram[1]:6 6.113219e-05 +7 mux_tree_tapbuf_size14_1_sram[1]:7 0.0001494609 +8 mux_tree_tapbuf_size14_1_sram[1]:8 0.0004419055 +9 mux_tree_tapbuf_size14_1_sram[1]:9 5.602613e-05 +10 mux_tree_tapbuf_size14_1_sram[1]:10 5.91589e-05 +11 mux_tree_tapbuf_size14_1_sram[1]:11 0.0003309751 +12 mux_tree_tapbuf_size14_1_sram[1]:12 0.0003309751 +13 mux_tree_tapbuf_size14_1_sram[1]:13 0.0004875219 +14 mux_tree_tapbuf_size14_1_sram[1]:14 0.0002186333 +15 mux_tree_tapbuf_size14_1_sram[1]:15 8.947659e-05 +16 mux_tree_tapbuf_size14_1_sram[1]:16 0.0002834394 +17 mux_tree_tapbuf_size14_1_sram[1]:17 0.0002523406 +18 mux_tree_tapbuf_size14_1_sram[1]:18 0.0001022814 +19 mux_tree_tapbuf_size14_1_sram[1]:19 0.0001022814 +20 mux_tree_tapbuf_size14_1_sram[1]:20 0.0004386171 +21 mux_tree_tapbuf_size14_1_sram[1]:21 0.0005827 +22 mux_tree_tapbuf_size14_1_sram[1]:22 0.0001136525 +23 mux_tree_tapbuf_size14_1_sram[1]:23 0.0001962907 +24 mux_tree_tapbuf_size14_1_sram[1]:24 0.0001962907 +25 mux_tree_tapbuf_size14_1_sram[1]:25 0.0003748176 +26 mux_tree_tapbuf_size14_1_sram[1]:26 0.0003748176 +27 mux_tree_tapbuf_size14_1_sram[1]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.490471e-05 +28 mux_tree_tapbuf_size14_1_sram[1]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.490471e-05 +29 mux_tree_tapbuf_size14_1_sram[1]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.385096e-06 +30 mux_tree_tapbuf_size14_1_sram[1]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.070815e-05 +31 mux_tree_tapbuf_size14_1_sram[1]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.385096e-06 +32 mux_tree_tapbuf_size14_1_sram[1]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.070815e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size14_1_sram[1]:26 0.152 +1 mux_tree_tapbuf_size14_1_sram[1]:9 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size14_1_sram[1]:10 mux_tree_tapbuf_size14_1_sram[1]:9 8.695652e-05 +3 mux_tree_tapbuf_size14_1_sram[1]:11 mux_tree_tapbuf_size14_1_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size14_1_sram[1]:13 mux_tree_tapbuf_size14_1_sram[1]:12 0.0045 +5 mux_tree_tapbuf_size14_1_sram[1]:13 mux_tree_tapbuf_size14_1_sram[1]:8 0.003607143 +6 mux_tree_tapbuf_size14_1_sram[1]:12 mux_tree_tapbuf_size14_1_sram[1]:11 0.005080357 +7 mux_tree_tapbuf_size14_1_sram[1]:20 mux_tree_tapbuf_size14_1_sram[1]:19 0.0045 +8 mux_tree_tapbuf_size14_1_sram[1]:19 mux_tree_tapbuf_size14_1_sram[1]:18 0.001133929 +9 mux_tree_tapbuf_size14_1_sram[1]:17 mux_tree_tapbuf_size14_1_sram[1]:16 0.00315625 +10 mux_tree_tapbuf_size14_1_sram[1]:18 mux_tree_tapbuf_size14_1_sram[1]:17 0.0045 +11 mux_tree_tapbuf_size14_1_sram[1]:7 mux_left_track_5\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size14_1_sram[1]:21 mux_left_track_5\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size14_1_sram[1]:21 mux_tree_tapbuf_size14_1_sram[1]:20 0.004977679 +14 mux_tree_tapbuf_size14_1_sram[1]:22 mux_tree_tapbuf_size14_1_sram[1]:21 0.001102679 +15 mux_tree_tapbuf_size14_1_sram[1]:23 mux_tree_tapbuf_size14_1_sram[1]:22 0.0045 +16 mux_tree_tapbuf_size14_1_sram[1]:25 mux_tree_tapbuf_size14_1_sram[1]:24 0.0045 +17 mux_tree_tapbuf_size14_1_sram[1]:24 mux_tree_tapbuf_size14_1_sram[1]:23 0.002348214 +18 mux_tree_tapbuf_size14_1_sram[1]:26 mux_tree_tapbuf_size14_1_sram[1]:25 0.003796875 +19 mux_tree_tapbuf_size14_1_sram[1]:6 mux_left_track_5\/mux_l2_in_2_:S 0.152 +20 mux_tree_tapbuf_size14_1_sram[1]:15 mux_left_track_5\/mux_l2_in_1_:S 0.152 +21 mux_tree_tapbuf_size14_1_sram[1]:15 mux_tree_tapbuf_size14_1_sram[1]:14 0.0001715117 +22 mux_tree_tapbuf_size14_1_sram[1]:8 mux_tree_tapbuf_size14_1_sram[1]:7 0.001787947 +23 mux_tree_tapbuf_size14_1_sram[1]:8 mux_tree_tapbuf_size14_1_sram[1]:6 0.0001271552 +24 mux_tree_tapbuf_size14_1_sram[1]:14 mux_tree_tapbuf_size14_1_sram[1]:13 0.002912946 +25 mux_tree_tapbuf_size14_1_sram[1]:16 mux_tree_tapbuf_size14_1_sram[1]:15 0.0003437501 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.001698821 //LENGTH 12.960 LUMPCC 0.0003371106 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.945 91.460 +*I mem_top_track_32\/FTB_24__50:A I *L 0.001746 *C 36.340 93.840 +*I mux_top_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 41.300 95.880 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 41.263 95.880 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 36.378 93.840 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 37.215 93.840 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 37.260 93.885 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 37.260 95.835 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 37.305 95.880 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 38.640 95.880 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 38.640 95.835 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 38.640 91.505 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 38.640 91.460 +*N mux_tree_tapbuf_size2_2_sram[1]:13 *C 38.945 91.460 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_32\/FTB_24__50:A 1e-06 +2 mux_top_track_32\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_2_sram[1]:3 0.0001355722 +4 mux_tree_tapbuf_size2_2_sram[1]:4 8.264928e-05 +5 mux_tree_tapbuf_size2_2_sram[1]:5 8.264928e-05 +6 mux_tree_tapbuf_size2_2_sram[1]:6 8.738863e-05 +7 mux_tree_tapbuf_size2_2_sram[1]:7 8.738863e-05 +8 mux_tree_tapbuf_size2_2_sram[1]:8 6.809135e-05 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.0002392268 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.0002405151 +11 mux_tree_tapbuf_size2_2_sram[1]:11 0.0002405151 +12 mux_tree_tapbuf_size2_2_sram[1]:12 4.947496e-05 +13 mux_tree_tapbuf_size2_2_sram[1]:13 4.523861e-05 +14 mux_tree_tapbuf_size2_2_sram[1]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.753697e-05 +15 mux_tree_tapbuf_size2_2_sram[1]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.488624e-05 +16 mux_tree_tapbuf_size2_2_sram[1]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.488624e-05 +17 mux_tree_tapbuf_size2_2_sram[1]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.753697e-05 +18 mux_tree_tapbuf_size2_2_sram[1]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.78742e-05 +19 mux_tree_tapbuf_size2_2_sram[1]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.257894e-06 +20 mux_tree_tapbuf_size2_2_sram[1]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.257894e-06 +21 mux_tree_tapbuf_size2_2_sram[1]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.78742e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.0045 +2 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.001741071 +3 mux_tree_tapbuf_size2_2_sram[1]:5 mux_tree_tapbuf_size2_2_sram[1]:4 0.0007477679 +4 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size2_2_sram[1]:4 mem_top_track_32\/FTB_24__50:A 0.152 +6 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.001191964 +7 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:3 0.002341518 +8 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 0.0045 +10 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.003866071 +11 mux_tree_tapbuf_size2_2_sram[1]:13 mux_tree_tapbuf_size2_2_sram[1]:12 0.0001657609 +12 mux_tree_tapbuf_size2_2_sram[1]:3 mux_top_track_32\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.01115639 //LENGTH 67.400 LUMPCC 0.004121576 DR + +*CONN +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 115.765 60.860 +*I mux_top_track_12\/mux_l1_in_0_:S I *L 0.00357 *C 68.900 58.480 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 72.395 64.260 +*I mux_top_track_12\/mux_l1_in_1_:S I *L 0.00357 *C 75.540 66.980 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 75.502 66.980 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 75.025 66.980 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 74.980 66.935 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 72.395 64.260 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 68.938 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 72.635 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 72.680 58.525 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 72.680 64.215 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 72.680 64.260 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 72.680 64.600 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 74.935 64.600 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 74.980 64.600 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 74.980 58.538 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 74.987 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:18 *C 114.073 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:19 *C 114.080 58.538 +*N mux_tree_tapbuf_size3_0_sram[0]:20 *C 114.080 60.815 +*N mux_tree_tapbuf_size3_0_sram[0]:21 *C 114.125 60.860 +*N mux_tree_tapbuf_size3_0_sram[0]:22 *C 115.728 60.860 + +*CAP +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_12\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_12\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 6.405878e-05 +5 mux_tree_tapbuf_size3_0_sram[0]:5 6.405878e-05 +6 mux_tree_tapbuf_size3_0_sram[0]:6 0.0001350153 +7 mux_tree_tapbuf_size3_0_sram[0]:7 3.62022e-05 +8 mux_tree_tapbuf_size3_0_sram[0]:8 0.0002623833 +9 mux_tree_tapbuf_size3_0_sram[0]:9 0.0002623833 +10 mux_tree_tapbuf_size3_0_sram[0]:10 0.0003446275 +11 mux_tree_tapbuf_size3_0_sram[0]:11 0.0003446275 +12 mux_tree_tapbuf_size3_0_sram[0]:12 8.945799e-05 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0002366242 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0002074049 +15 mux_tree_tapbuf_size3_0_sram[0]:15 0.0005326726 +16 mux_tree_tapbuf_size3_0_sram[0]:16 0.0003634808 +17 mux_tree_tapbuf_size3_0_sram[0]:17 0.001802669 +18 mux_tree_tapbuf_size3_0_sram[0]:18 0.001802669 +19 mux_tree_tapbuf_size3_0_sram[0]:19 0.0001343879 +20 mux_tree_tapbuf_size3_0_sram[0]:20 0.0001343879 +21 mux_tree_tapbuf_size3_0_sram[0]:21 0.0001068515 +22 mux_tree_tapbuf_size3_0_sram[0]:22 0.0001068515 +23 mux_tree_tapbuf_size3_0_sram[0]:6 prog_clk[0]:283 1.205015e-05 +24 mux_tree_tapbuf_size3_0_sram[0]:17 prog_clk[0]:217 0.0002024224 +25 mux_tree_tapbuf_size3_0_sram[0]:17 prog_clk[0]:278 0.000133978 +26 mux_tree_tapbuf_size3_0_sram[0]:17 prog_clk[0]:279 7.188732e-05 +27 mux_tree_tapbuf_size3_0_sram[0]:19 prog_clk[0]:114 2.553867e-06 +28 mux_tree_tapbuf_size3_0_sram[0]:19 prog_clk[0]:121 1.250687e-05 +29 mux_tree_tapbuf_size3_0_sram[0]:18 prog_clk[0]:212 0.0002024224 +30 mux_tree_tapbuf_size3_0_sram[0]:18 prog_clk[0]:217 0.000133978 +31 mux_tree_tapbuf_size3_0_sram[0]:18 prog_clk[0]:278 7.188732e-05 +32 mux_tree_tapbuf_size3_0_sram[0]:21 prog_clk[0]:115 9.813707e-06 +33 mux_tree_tapbuf_size3_0_sram[0]:20 prog_clk[0]:115 2.553867e-06 +34 mux_tree_tapbuf_size3_0_sram[0]:20 prog_clk[0]:124 1.250687e-05 +35 mux_tree_tapbuf_size3_0_sram[0]:22 prog_clk[0]:121 9.813707e-06 +36 mux_tree_tapbuf_size3_0_sram[0]:12 prog_clk[0]:201 7.536129e-07 +37 mux_tree_tapbuf_size3_0_sram[0]:11 prog_clk[0]:204 2.302284e-05 +38 mux_tree_tapbuf_size3_0_sram[0]:11 prog_clk[0]:308 1.665547e-06 +39 mux_tree_tapbuf_size3_0_sram[0]:10 prog_clk[0]:200 2.302284e-05 +40 mux_tree_tapbuf_size3_0_sram[0]:10 prog_clk[0]:204 1.665547e-06 +41 mux_tree_tapbuf_size3_0_sram[0]:15 prog_clk[0]:306 1.205015e-05 +42 mux_tree_tapbuf_size3_0_sram[0]:13 prog_clk[0]:202 7.536129e-07 +43 mux_tree_tapbuf_size3_0_sram[0]:17 chany_top_in[16]:11 0.001036044 +44 mux_tree_tapbuf_size3_0_sram[0]:18 chany_top_in[16]:10 0.001036044 +45 mux_tree_tapbuf_size3_0_sram[0]:17 chany_top_in[18]:11 0.0005540893 +46 mux_tree_tapbuf_size3_0_sram[0]:18 chany_top_in[18]:12 0.0005540893 + +*RES +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:4 mux_top_track_12\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 0.0004263393 +3 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.005412946 +5 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.00341 +6 mux_tree_tapbuf_size3_0_sram[0]:19 mux_tree_tapbuf_size3_0_sram[0]:18 0.00341 +7 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:17 0.006123316 +8 mux_tree_tapbuf_size3_0_sram[0]:21 mux_tree_tapbuf_size3_0_sram[0]:20 0.0045 +9 mux_tree_tapbuf_size3_0_sram[0]:20 mux_tree_tapbuf_size3_0_sram[0]:19 0.002033482 +10 mux_tree_tapbuf_size3_0_sram[0]:22 mux_tree_tapbuf_size3_0_sram[0]:21 0.001430804 +11 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.0045 +12 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:7 0.0001548913 +13 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.005080358 +14 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.003301339 +15 mux_tree_tapbuf_size3_0_sram[0]:10 mux_tree_tapbuf_size3_0_sram[0]:9 0.0045 +16 mux_tree_tapbuf_size3_0_sram[0]:8 mux_top_track_12\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size3_0_sram[0]:7 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.002013393 +19 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.0045 +20 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:6 0.002084821 +21 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size3_6_sram[1] 0.003363937 //LENGTH 26.510 LUMPCC 0.0006411743 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 77.965 28.900 +*I mem_top_track_24\/FTB_20__46:A I *L 0.001746 *C 69.460 23.120 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 80.400 36.040 +*N mux_tree_tapbuf_size3_6_sram[1]:3 *C 80.362 36.040 +*N mux_tree_tapbuf_size3_6_sram[1]:4 *C 78.705 36.040 +*N mux_tree_tapbuf_size3_6_sram[1]:5 *C 78.660 35.995 +*N mux_tree_tapbuf_size3_6_sram[1]:6 *C 78.660 28.995 +*N mux_tree_tapbuf_size3_6_sram[1]:7 *C 69.460 23.120 +*N mux_tree_tapbuf_size3_6_sram[1]:8 *C 69.460 23.165 +*N mux_tree_tapbuf_size3_6_sram[1]:9 *C 69.460 23.742 +*N mux_tree_tapbuf_size3_6_sram[1]:10 *C 69.468 23.800 +*N mux_tree_tapbuf_size3_6_sram[1]:11 *C 78.193 23.800 +*N mux_tree_tapbuf_size3_6_sram[1]:12 *C 78.200 23.858 +*N mux_tree_tapbuf_size3_6_sram[1]:13 *C 78.200 28.560 +*N mux_tree_tapbuf_size3_6_sram[1]:14 *C 78.615 28.560 +*N mux_tree_tapbuf_size3_6_sram[1]:15 *C 78.660 29.025 +*N mux_tree_tapbuf_size3_6_sram[1]:16 *C 78.615 28.900 +*N mux_tree_tapbuf_size3_6_sram[1]:17 *C 78.002 28.900 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_24\/FTB_20__46:A 1e-06 +2 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_6_sram[1]:3 9.696613e-05 +4 mux_tree_tapbuf_size3_6_sram[1]:4 9.696613e-05 +5 mux_tree_tapbuf_size3_6_sram[1]:5 0.0003959913 +6 mux_tree_tapbuf_size3_6_sram[1]:6 1.3819e-05 +7 mux_tree_tapbuf_size3_6_sram[1]:7 3.311102e-05 +8 mux_tree_tapbuf_size3_6_sram[1]:8 6.318195e-05 +9 mux_tree_tapbuf_size3_6_sram[1]:9 6.318195e-05 +10 mux_tree_tapbuf_size3_6_sram[1]:10 0.0004059318 +11 mux_tree_tapbuf_size3_6_sram[1]:11 0.0004059318 +12 mux_tree_tapbuf_size3_6_sram[1]:12 0.0002546165 +13 mux_tree_tapbuf_size3_6_sram[1]:13 0.0002863144 +14 mux_tree_tapbuf_size3_6_sram[1]:14 5.248708e-05 +15 mux_tree_tapbuf_size3_6_sram[1]:15 0.0004305996 +16 mux_tree_tapbuf_size3_6_sram[1]:16 6.03321e-05 +17 mux_tree_tapbuf_size3_6_sram[1]:17 6.03321e-05 +18 mux_tree_tapbuf_size3_6_sram[1]:11 chanx_right_in[12]:28 0.0002069679 +19 mux_tree_tapbuf_size3_6_sram[1]:10 chanx_right_in[12]:27 0.0002069679 +20 mux_tree_tapbuf_size3_6_sram[1]:15 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 4.460675e-06 +21 mux_tree_tapbuf_size3_6_sram[1]:15 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 3.214712e-05 +22 mux_tree_tapbuf_size3_6_sram[1]:12 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 2.792257e-05 +23 mux_tree_tapbuf_size3_6_sram[1]:5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 2.953645e-05 +24 mux_tree_tapbuf_size3_6_sram[1]:13 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 2.792257e-05 +25 mux_tree_tapbuf_size3_6_sram[1]:14 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 4.460675e-06 +26 mux_tree_tapbuf_size3_6_sram[1]:6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 2.610669e-06 +27 mux_tree_tapbuf_size3_6_sram[1]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.908883e-05 +28 mux_tree_tapbuf_size3_6_sram[1]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.908883e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_6_sram[1]:17 0.152 +1 mux_tree_tapbuf_size3_6_sram[1]:17 mux_tree_tapbuf_size3_6_sram[1]:16 0.000546875 +2 mux_tree_tapbuf_size3_6_sram[1]:16 mux_tree_tapbuf_size3_6_sram[1]:15 0.0045 +3 mux_tree_tapbuf_size3_6_sram[1]:15 mux_tree_tapbuf_size3_6_sram[1]:14 0.000290625 +4 mux_tree_tapbuf_size3_6_sram[1]:15 mux_tree_tapbuf_size3_6_sram[1]:6 1.875e-05 +5 mux_tree_tapbuf_size3_6_sram[1]:15 mux_tree_tapbuf_size3_6_sram[1]:5 0.006223214 +6 mux_tree_tapbuf_size3_6_sram[1]:12 mux_tree_tapbuf_size3_6_sram[1]:11 0.00341 +7 mux_tree_tapbuf_size3_6_sram[1]:11 mux_tree_tapbuf_size3_6_sram[1]:10 0.001366917 +8 mux_tree_tapbuf_size3_6_sram[1]:9 mux_tree_tapbuf_size3_6_sram[1]:8 0.000515625 +9 mux_tree_tapbuf_size3_6_sram[1]:10 mux_tree_tapbuf_size3_6_sram[1]:9 0.00341 +10 mux_tree_tapbuf_size3_6_sram[1]:7 mem_top_track_24\/FTB_20__46:A 0.152 +11 mux_tree_tapbuf_size3_6_sram[1]:8 mux_tree_tapbuf_size3_6_sram[1]:7 0.0045 +12 mux_tree_tapbuf_size3_6_sram[1]:4 mux_tree_tapbuf_size3_6_sram[1]:3 0.001479911 +13 mux_tree_tapbuf_size3_6_sram[1]:5 mux_tree_tapbuf_size3_6_sram[1]:4 0.0045 +14 mux_tree_tapbuf_size3_6_sram[1]:3 mux_top_track_24\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size3_6_sram[1]:13 mux_tree_tapbuf_size3_6_sram[1]:12 0.004198661 +16 mux_tree_tapbuf_size3_6_sram[1]:14 mux_tree_tapbuf_size3_6_sram[1]:13 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_6_ccff_tail[0] 0.0007660587 //LENGTH 5.580 LUMPCC 0.0002787967 DR + +*CONN +*I mem_top_track_24\/FTB_20__46:X O *L 0 *C 66.465 23.120 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 64.575 26.180 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 *C 64.575 26.180 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 *C 64.860 26.180 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 *C 64.860 26.135 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 *C 64.860 23.165 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 *C 64.905 23.120 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 *C 66.428 23.120 + +*CAP +0 mem_top_track_24\/FTB_20__46:X 1e-06 +1 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 5.156043e-05 +3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 5.744382e-05 +4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 7.456604e-05 +5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 7.456604e-05 +6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 0.0001135629 +7 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 0.0001135629 +8 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 chanx_right_in[14]:20 9.257792e-05 +9 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 chanx_right_in[14]:19 9.257792e-05 +10 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.682044e-05 +11 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.682044e-05 + +*RES +0 mem_top_track_24\/FTB_20__46:X mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 0.001359375 +2 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[2] 0.002580931 //LENGTH 18.200 LUMPCC 0.001026793 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 117.145 39.440 +*I mux_top_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 106.820 44.880 +*I mem_top_track_8\/FTB_12__38:A I *L 0.001746 *C 118.680 44.880 +*N mux_tree_tapbuf_size4_0_sram[2]:3 *C 118.643 44.880 +*N mux_tree_tapbuf_size4_0_sram[2]:4 *C 106.858 44.880 +*N mux_tree_tapbuf_size4_0_sram[2]:5 *C 117.300 44.880 +*N mux_tree_tapbuf_size4_0_sram[2]:6 *C 117.300 44.835 +*N mux_tree_tapbuf_size4_0_sram[2]:7 *C 117.300 39.485 +*N mux_tree_tapbuf_size4_0_sram[2]:8 *C 117.300 39.440 +*N mux_tree_tapbuf_size4_0_sram[2]:9 *C 117.145 39.440 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_8\/FTB_12__38:A 1e-06 +3 mux_tree_tapbuf_size4_0_sram[2]:3 8.110792e-05 +4 mux_tree_tapbuf_size4_0_sram[2]:4 0.0003358799 +5 mux_tree_tapbuf_size4_0_sram[2]:5 0.0004479809 +6 mux_tree_tapbuf_size4_0_sram[2]:6 0.0002995763 +7 mux_tree_tapbuf_size4_0_sram[2]:7 0.0002995763 +8 mux_tree_tapbuf_size4_0_sram[2]:8 4.4293e-05 +9 mux_tree_tapbuf_size4_0_sram[2]:9 4.272325e-05 +10 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.0002754013 +11 mux_tree_tapbuf_size4_0_sram[2]:4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.0002754013 +12 mux_tree_tapbuf_size4_0_sram[2]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001852565 +13 mux_tree_tapbuf_size4_0_sram[2]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001852565 +14 mux_tree_tapbuf_size4_0_sram[2]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.273887e-05 +15 mux_tree_tapbuf_size4_0_sram[2]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.273887e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_0_sram[2]:9 0.152 +1 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:4 0.00932366 +2 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:3 0.001198661 +3 mux_tree_tapbuf_size4_0_sram[2]:6 mux_tree_tapbuf_size4_0_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size4_0_sram[2]:8 mux_tree_tapbuf_size4_0_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size4_0_sram[2]:7 mux_tree_tapbuf_size4_0_sram[2]:6 0.004776786 +6 mux_tree_tapbuf_size4_0_sram[2]:9 mux_tree_tapbuf_size4_0_sram[2]:8 8.423914e-05 +7 mux_tree_tapbuf_size4_0_sram[2]:4 mux_top_track_8\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_0_sram[2]:3 mem_top_track_8\/FTB_12__38:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.007319714 //LENGTH 39.485 LUMPCC 0.003536381 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 39.405 58.820 +*I mux_left_track_33\/mux_l2_in_1_:S I *L 0.00357 *C 14.380 58.140 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 13.515 55.420 +*I mux_left_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 35.980 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 36.017 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 39.055 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 39.100 61.155 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 13.553 55.420 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 16.515 55.420 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 16.560 55.465 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 14.418 58.140 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 16.515 58.140 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 16.560 58.140 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 16.560 58.775 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 16.605 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 27.095 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 27.140 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:17 *C 27.140 59.160 +*N mux_tree_tapbuf_size6_1_sram[1]:18 *C 27.148 59.160 +*N mux_tree_tapbuf_size6_1_sram[1]:19 *C 39.093 59.160 +*N mux_tree_tapbuf_size6_1_sram[1]:20 *C 39.100 59.218 +*N mux_tree_tapbuf_size6_1_sram[1]:21 *C 39.100 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:22 *C 39.100 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:23 *C 39.405 58.820 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_33\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_33\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 0.0002160385 +5 mux_tree_tapbuf_size6_1_sram[1]:5 0.0002160385 +6 mux_tree_tapbuf_size6_1_sram[1]:6 0.0001515781 +7 mux_tree_tapbuf_size6_1_sram[1]:7 0.000152286 +8 mux_tree_tapbuf_size6_1_sram[1]:8 0.000152286 +9 mux_tree_tapbuf_size6_1_sram[1]:9 0.0001451906 +10 mux_tree_tapbuf_size6_1_sram[1]:10 9.587627e-05 +11 mux_tree_tapbuf_size6_1_sram[1]:11 9.587627e-05 +12 mux_tree_tapbuf_size6_1_sram[1]:12 0.0002221314 +13 mux_tree_tapbuf_size6_1_sram[1]:13 4.063765e-05 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0004582486 +15 mux_tree_tapbuf_size6_1_sram[1]:15 0.0004582486 +16 mux_tree_tapbuf_size6_1_sram[1]:16 5.988145e-05 +17 mux_tree_tapbuf_size6_1_sram[1]:17 6.429626e-05 +18 mux_tree_tapbuf_size6_1_sram[1]:18 0.0004605348 +19 mux_tree_tapbuf_size6_1_sram[1]:19 0.0004605348 +20 mux_tree_tapbuf_size6_1_sram[1]:20 0.0001756667 +21 mux_tree_tapbuf_size6_1_sram[1]:21 5.913942e-05 +22 mux_tree_tapbuf_size6_1_sram[1]:22 4.728765e-05 +23 mux_tree_tapbuf_size6_1_sram[1]:23 4.755638e-05 +24 mux_tree_tapbuf_size6_1_sram[1]:12 prog_clk[0]:536 1.12381e-05 +25 mux_tree_tapbuf_size6_1_sram[1]:12 prog_clk[0]:539 1.858856e-05 +26 mux_tree_tapbuf_size6_1_sram[1]:9 prog_clk[0]:530 3.90516e-06 +27 mux_tree_tapbuf_size6_1_sram[1]:9 prog_clk[0]:536 1.858856e-05 +28 mux_tree_tapbuf_size6_1_sram[1]:13 prog_clk[0]:539 7.33294e-06 +29 mux_tree_tapbuf_size6_1_sram[1]:16 prog_clk[0]:524 1.808389e-08 +30 mux_tree_tapbuf_size6_1_sram[1]:17 prog_clk[0]:518 1.808389e-08 +31 mux_tree_tapbuf_size6_1_sram[1]:18 prog_clk[0]:517 0.0004970907 +32 mux_tree_tapbuf_size6_1_sram[1]:19 prog_clk[0]:516 0.0004970907 +33 mux_tree_tapbuf_size6_1_sram[1]:22 mux_tree_tapbuf_size6_1_sram[0]:22 1.335036e-05 +34 mux_tree_tapbuf_size6_1_sram[1]:23 mux_tree_tapbuf_size6_1_sram[0]:23 1.335036e-05 +35 mux_tree_tapbuf_size6_1_sram[1]:18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0003941611 +36 mux_tree_tapbuf_size6_1_sram[1]:19 mux_tree_tapbuf_size6_1_sram[0]:19 0.0003941611 +37 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[2]:9 0.0001222412 +38 mux_tree_tapbuf_size6_1_sram[1]:7 mux_tree_tapbuf_size6_1_sram[2]:8 0.0001222412 +39 mux_tree_tapbuf_size6_1_sram[1]:14 optlc_net_123:12 0.0001893699 +40 mux_tree_tapbuf_size6_1_sram[1]:15 optlc_net_123:11 0.0001893699 +41 mux_tree_tapbuf_size6_1_sram[1]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.363481e-05 +42 mux_tree_tapbuf_size6_1_sram[1]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.363481e-05 +43 mux_tree_tapbuf_size6_1_sram[1]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001165005 +44 mux_tree_tapbuf_size6_1_sram[1]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001165005 +45 mux_tree_tapbuf_size6_1_sram[1]:10 ropt_net_129:5 9.168083e-05 +46 mux_tree_tapbuf_size6_1_sram[1]:11 ropt_net_129:6 9.168083e-05 +47 mux_tree_tapbuf_size6_1_sram[1]:14 ropt_net_129:5 0.0002236536 +48 mux_tree_tapbuf_size6_1_sram[1]:14 ropt_net_129:7 6.662554e-06 +49 mux_tree_tapbuf_size6_1_sram[1]:15 ropt_net_129:8 6.662554e-06 +50 mux_tree_tapbuf_size6_1_sram[1]:15 ropt_net_129:6 0.0002236536 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:23 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:10 mux_left_track_33\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.001872768 +3 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:9 0.002388393 +5 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.002645089 +6 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size6_1_sram[1]:7 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size6_1_sram[1]:22 mux_tree_tapbuf_size6_1_sram[1]:21 0.0045 +9 mux_tree_tapbuf_size6_1_sram[1]:21 mux_tree_tapbuf_size6_1_sram[1]:20 0.0001911058 +10 mux_tree_tapbuf_size6_1_sram[1]:23 mux_tree_tapbuf_size6_1_sram[1]:22 0.0001657609 +11 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.0045 +12 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.0005669643 +13 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.009366073 +14 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.0045 +15 mux_tree_tapbuf_size6_1_sram[1]:17 mux_tree_tapbuf_size6_1_sram[1]:16 0.0001634615 +16 mux_tree_tapbuf_size6_1_sram[1]:18 mux_tree_tapbuf_size6_1_sram[1]:17 0.00341 +17 mux_tree_tapbuf_size6_1_sram[1]:20 mux_tree_tapbuf_size6_1_sram[1]:19 0.00341 +18 mux_tree_tapbuf_size6_1_sram[1]:20 mux_tree_tapbuf_size6_1_sram[1]:6 0.001729911 +19 mux_tree_tapbuf_size6_1_sram[1]:19 mux_tree_tapbuf_size6_1_sram[1]:18 0.001871383 +20 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.002712054 +21 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +22 mux_tree_tapbuf_size6_1_sram[1]:4 mux_left_track_33\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[1] 0.00255019 //LENGTH 19.990 LUMPCC 0 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 85.405 42.160 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 88.035 39.100 +*I mux_top_track_6\/mux_l2_in_1_:S I *L 0.00357 *C 87.500 44.880 +*I mux_top_track_6\/mux_l2_in_0_:S I *L 0.00357 *C 84.080 50.320 +*N mux_tree_tapbuf_size7_2_sram[1]:4 *C 84.080 50.320 +*N mux_tree_tapbuf_size7_2_sram[1]:5 *C 84.180 50.275 +*N mux_tree_tapbuf_size7_2_sram[1]:6 *C 84.180 47.645 +*N mux_tree_tapbuf_size7_2_sram[1]:7 *C 84.225 47.600 +*N mux_tree_tapbuf_size7_2_sram[1]:8 *C 87.815 47.600 +*N mux_tree_tapbuf_size7_2_sram[1]:9 *C 87.860 47.555 +*N mux_tree_tapbuf_size7_2_sram[1]:10 *C 87.860 44.880 +*N mux_tree_tapbuf_size7_2_sram[1]:11 *C 87.400 44.880 +*N mux_tree_tapbuf_size7_2_sram[1]:12 *C 87.400 44.880 +*N mux_tree_tapbuf_size7_2_sram[1]:13 *C 87.998 39.100 +*N mux_tree_tapbuf_size7_2_sram[1]:14 *C 87.445 39.100 +*N mux_tree_tapbuf_size7_2_sram[1]:15 *C 87.400 39.145 +*N mux_tree_tapbuf_size7_2_sram[1]:16 *C 87.400 42.160 +*N mux_tree_tapbuf_size7_2_sram[1]:17 *C 87.355 42.160 +*N mux_tree_tapbuf_size7_2_sram[1]:18 *C 85.443 42.160 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_top_track_6\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_6\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_2_sram[1]:4 2.686926e-05 +5 mux_tree_tapbuf_size7_2_sram[1]:5 0.0001652599 +6 mux_tree_tapbuf_size7_2_sram[1]:6 0.0001652599 +7 mux_tree_tapbuf_size7_2_sram[1]:7 0.0003120794 +8 mux_tree_tapbuf_size7_2_sram[1]:8 0.0003120794 +9 mux_tree_tapbuf_size7_2_sram[1]:9 0.0001739643 +10 mux_tree_tapbuf_size7_2_sram[1]:10 0.0002108219 +11 mux_tree_tapbuf_size7_2_sram[1]:11 3.478103e-05 +12 mux_tree_tapbuf_size7_2_sram[1]:12 0.0001880974 +13 mux_tree_tapbuf_size7_2_sram[1]:13 6.48092e-05 +14 mux_tree_tapbuf_size7_2_sram[1]:14 6.48092e-05 +15 mux_tree_tapbuf_size7_2_sram[1]:15 0.0001718058 +16 mux_tree_tapbuf_size7_2_sram[1]:16 0.0003542707 +17 mux_tree_tapbuf_size7_2_sram[1]:17 0.0001506412 +18 mux_tree_tapbuf_size7_2_sram[1]:18 0.0001506412 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_2_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_2_sram[1]:11 mux_top_track_6\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:10 0.0004107143 +4 mux_tree_tapbuf_size7_2_sram[1]:8 mux_tree_tapbuf_size7_2_sram[1]:7 0.003205357 +5 mux_tree_tapbuf_size7_2_sram[1]:9 mux_tree_tapbuf_size7_2_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size7_2_sram[1]:7 mux_tree_tapbuf_size7_2_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size7_2_sram[1]:6 mux_tree_tapbuf_size7_2_sram[1]:5 0.002348215 +8 mux_tree_tapbuf_size7_2_sram[1]:4 mux_top_track_6\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size7_2_sram[1]:5 mux_tree_tapbuf_size7_2_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size7_2_sram[1]:14 mux_tree_tapbuf_size7_2_sram[1]:13 0.0004933036 +11 mux_tree_tapbuf_size7_2_sram[1]:15 mux_tree_tapbuf_size7_2_sram[1]:14 0.0045 +12 mux_tree_tapbuf_size7_2_sram[1]:13 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size7_2_sram[1]:17 mux_tree_tapbuf_size7_2_sram[1]:16 0.0045 +14 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:15 0.002691964 +15 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:12 0.002428571 +16 mux_tree_tapbuf_size7_2_sram[1]:18 mux_tree_tapbuf_size7_2_sram[1]:17 0.001707589 +17 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:9 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[0] 0.006437206 //LENGTH 49.345 LUMPCC 0.0002546719 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 100.585 44.540 +*I mux_right_track_24\/mux_l1_in_3_:S I *L 0.00357 *C 99.000 55.760 +*I mux_right_track_24\/mux_l1_in_2_:S I *L 0.00357 *C 97.160 61.495 +*I mux_right_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 91.640 63.240 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 85.000 63.630 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 82.515 60.860 +*N mux_tree_tapbuf_size7_4_sram[0]:6 *C 82.553 60.860 +*N mux_tree_tapbuf_size7_4_sram[0]:7 *C 85.000 63.630 +*N mux_tree_tapbuf_size7_4_sram[0]:8 *C 91.603 63.240 +*N mux_tree_tapbuf_size7_4_sram[0]:9 *C 85.000 63.240 +*N mux_tree_tapbuf_size7_4_sram[0]:10 *C 83.765 63.240 +*N mux_tree_tapbuf_size7_4_sram[0]:11 *C 83.720 63.195 +*N mux_tree_tapbuf_size7_4_sram[0]:12 *C 83.720 60.905 +*N mux_tree_tapbuf_size7_4_sram[0]:13 *C 83.720 60.860 +*N mux_tree_tapbuf_size7_4_sram[0]:14 *C 97.060 60.860 +*N mux_tree_tapbuf_size7_4_sram[0]:15 *C 97.160 61.495 +*N mux_tree_tapbuf_size7_4_sram[0]:16 *C 97.130 61.270 +*N mux_tree_tapbuf_size7_4_sram[0]:17 *C 97.015 61.130 +*N mux_tree_tapbuf_size7_4_sram[0]:18 *C 99.315 61.200 +*N mux_tree_tapbuf_size7_4_sram[0]:19 *C 99.360 61.155 +*N mux_tree_tapbuf_size7_4_sram[0]:20 *C 99.015 55.760 +*N mux_tree_tapbuf_size7_4_sram[0]:21 *C 99.338 55.760 +*N mux_tree_tapbuf_size7_4_sram[0]:22 *C 99.360 55.760 +*N mux_tree_tapbuf_size7_4_sram[0]:23 *C 99.360 55.080 +*N mux_tree_tapbuf_size7_4_sram[0]:24 *C 99.820 55.080 +*N mux_tree_tapbuf_size7_4_sram[0]:25 *C 99.820 44.585 +*N mux_tree_tapbuf_size7_4_sram[0]:26 *C 99.865 44.540 +*N mux_tree_tapbuf_size7_4_sram[0]:27 *C 100.547 44.540 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_24\/mux_l1_in_3_:S 1e-06 +2 mux_right_track_24\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_24\/mux_l1_in_1_:S 1e-06 +4 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +5 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_4_sram[0]:6 8.642047e-05 +7 mux_tree_tapbuf_size7_4_sram[0]:7 5.598895e-05 +8 mux_tree_tapbuf_size7_4_sram[0]:8 0.0004548105 +9 mux_tree_tapbuf_size7_4_sram[0]:9 0.0005864569 +10 mux_tree_tapbuf_size7_4_sram[0]:10 0.0001026984 +11 mux_tree_tapbuf_size7_4_sram[0]:11 0.0001492955 +12 mux_tree_tapbuf_size7_4_sram[0]:12 0.0001492955 +13 mux_tree_tapbuf_size7_4_sram[0]:13 0.0009015544 +14 mux_tree_tapbuf_size7_4_sram[0]:14 0.0008082542 +15 mux_tree_tapbuf_size7_4_sram[0]:15 5.87841e-05 +16 mux_tree_tapbuf_size7_4_sram[0]:16 3.985779e-05 +17 mux_tree_tapbuf_size7_4_sram[0]:17 0.0002389963 +18 mux_tree_tapbuf_size7_4_sram[0]:18 0.000203311 +19 mux_tree_tapbuf_size7_4_sram[0]:19 0.0003271091 +20 mux_tree_tapbuf_size7_4_sram[0]:20 6.095833e-05 +21 mux_tree_tapbuf_size7_4_sram[0]:21 6.095833e-05 +22 mux_tree_tapbuf_size7_4_sram[0]:22 0.0004024039 +23 mux_tree_tapbuf_size7_4_sram[0]:23 7.311778e-05 +24 mux_tree_tapbuf_size7_4_sram[0]:24 0.0006661328 +25 mux_tree_tapbuf_size7_4_sram[0]:25 0.0006335663 +26 mux_tree_tapbuf_size7_4_sram[0]:26 5.828164e-05 +27 mux_tree_tapbuf_size7_4_sram[0]:27 5.828164e-05 +28 mux_tree_tapbuf_size7_4_sram[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.311476e-08 +29 mux_tree_tapbuf_size7_4_sram[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.458887e-05 +30 mux_tree_tapbuf_size7_4_sram[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.311476e-08 +31 mux_tree_tapbuf_size7_4_sram[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.458887e-05 +32 mux_tree_tapbuf_size7_4_sram[0]:22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.96662e-07 +33 mux_tree_tapbuf_size7_4_sram[0]:19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.96662e-07 +34 mux_tree_tapbuf_size7_4_sram[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.185732e-05 +35 mux_tree_tapbuf_size7_4_sram[0]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.185732e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_4_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_4_sram[0]:21 mux_tree_tapbuf_size7_4_sram[0]:20 0.0001752718 +2 mux_tree_tapbuf_size7_4_sram[0]:22 mux_tree_tapbuf_size7_4_sram[0]:21 0.0045 +3 mux_tree_tapbuf_size7_4_sram[0]:22 mux_tree_tapbuf_size7_4_sram[0]:19 0.004816964 +4 mux_tree_tapbuf_size7_4_sram[0]:20 mux_right_track_24\/mux_l1_in_3_:S 0.152 +5 mux_tree_tapbuf_size7_4_sram[0]:18 mux_tree_tapbuf_size7_4_sram[0]:17 0.002053571 +6 mux_tree_tapbuf_size7_4_sram[0]:19 mux_tree_tapbuf_size7_4_sram[0]:18 0.0045 +7 mux_tree_tapbuf_size7_4_sram[0]:13 mux_tree_tapbuf_size7_4_sram[0]:12 0.0045 +8 mux_tree_tapbuf_size7_4_sram[0]:13 mux_tree_tapbuf_size7_4_sram[0]:6 0.001042411 +9 mux_tree_tapbuf_size7_4_sram[0]:12 mux_tree_tapbuf_size7_4_sram[0]:11 0.002044643 +10 mux_tree_tapbuf_size7_4_sram[0]:10 mux_tree_tapbuf_size7_4_sram[0]:9 0.001102679 +11 mux_tree_tapbuf_size7_4_sram[0]:11 mux_tree_tapbuf_size7_4_sram[0]:10 0.0045 +12 mux_tree_tapbuf_size7_4_sram[0]:15 mux_right_track_24\/mux_l1_in_2_:S 0.152 +13 mux_tree_tapbuf_size7_4_sram[0]:26 mux_tree_tapbuf_size7_4_sram[0]:25 0.0045 +14 mux_tree_tapbuf_size7_4_sram[0]:25 mux_tree_tapbuf_size7_4_sram[0]:24 0.009370536 +15 mux_tree_tapbuf_size7_4_sram[0]:27 mux_tree_tapbuf_size7_4_sram[0]:26 0.000609375 +16 mux_tree_tapbuf_size7_4_sram[0]:7 mux_right_track_24\/mux_l1_in_0_:S 0.152 +17 mux_tree_tapbuf_size7_4_sram[0]:6 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size7_4_sram[0]:8 mux_right_track_24\/mux_l1_in_1_:S 0.152 +19 mux_tree_tapbuf_size7_4_sram[0]:14 mux_tree_tapbuf_size7_4_sram[0]:13 0.01191071 +20 mux_tree_tapbuf_size7_4_sram[0]:9 mux_tree_tapbuf_size7_4_sram[0]:8 0.00589509 +21 mux_tree_tapbuf_size7_4_sram[0]:9 mux_tree_tapbuf_size7_4_sram[0]:7 0.0003482143 +22 mux_tree_tapbuf_size7_4_sram[0]:17 mux_tree_tapbuf_size7_4_sram[0]:16 0.0001026786 +23 mux_tree_tapbuf_size7_4_sram[0]:17 mux_tree_tapbuf_size7_4_sram[0]:14 0.0002410715 +24 mux_tree_tapbuf_size7_4_sram[0]:16 mux_tree_tapbuf_size7_4_sram[0]:15 9.698277e-05 +25 mux_tree_tapbuf_size7_4_sram[0]:23 mux_tree_tapbuf_size7_4_sram[0]:22 0.0006071429 +26 mux_tree_tapbuf_size7_4_sram[0]:24 mux_tree_tapbuf_size7_4_sram[0]:23 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[2] 0.001748493 //LENGTH 14.155 LUMPCC 0.0001261941 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 50.445 42.500 +*I mem_left_track_25\/FTB_11__37:A I *L 0.001746 *C 43.240 47.600 +*I mux_left_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 43.800 44.880 +*N mux_tree_tapbuf_size7_6_sram[2]:3 *C 43.278 47.600 +*N mux_tree_tapbuf_size7_6_sram[2]:4 *C 43.655 47.600 +*N mux_tree_tapbuf_size7_6_sram[2]:5 *C 43.700 47.555 +*N mux_tree_tapbuf_size7_6_sram[2]:6 *C 43.700 44.925 +*N mux_tree_tapbuf_size7_6_sram[2]:7 *C 43.837 44.880 +*N mux_tree_tapbuf_size7_6_sram[2]:8 *C 44.620 44.880 +*N mux_tree_tapbuf_size7_6_sram[2]:9 *C 44.620 44.540 +*N mux_tree_tapbuf_size7_6_sram[2]:10 *C 47.335 44.540 +*N mux_tree_tapbuf_size7_6_sram[2]:11 *C 47.380 44.495 +*N mux_tree_tapbuf_size7_6_sram[2]:12 *C 47.380 42.545 +*N mux_tree_tapbuf_size7_6_sram[2]:13 *C 47.425 42.500 +*N mux_tree_tapbuf_size7_6_sram[2]:14 *C 50.407 42.500 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_25\/FTB_11__37:A 1e-06 +2 mux_left_track_25\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_6_sram[2]:3 4.693541e-05 +4 mux_tree_tapbuf_size7_6_sram[2]:4 4.693541e-05 +5 mux_tree_tapbuf_size7_6_sram[2]:5 0.0001719899 +6 mux_tree_tapbuf_size7_6_sram[2]:6 0.0001719899 +7 mux_tree_tapbuf_size7_6_sram[2]:7 6.048091e-05 +8 mux_tree_tapbuf_size7_6_sram[2]:8 8.430779e-05 +9 mux_tree_tapbuf_size7_6_sram[2]:9 0.0001632339 +10 mux_tree_tapbuf_size7_6_sram[2]:10 0.000139407 +11 mux_tree_tapbuf_size7_6_sram[2]:11 0.0001235157 +12 mux_tree_tapbuf_size7_6_sram[2]:12 0.0001235157 +13 mux_tree_tapbuf_size7_6_sram[2]:13 0.0002434934 +14 mux_tree_tapbuf_size7_6_sram[2]:14 0.0002434934 +15 mux_tree_tapbuf_size7_6_sram[2]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.162721e-05 +16 mux_tree_tapbuf_size7_6_sram[2]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.146983e-05 +17 mux_tree_tapbuf_size7_6_sram[2]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.162721e-05 +18 mux_tree_tapbuf_size7_6_sram[2]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.146983e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_6_sram[2]:14 0.152 +1 mux_tree_tapbuf_size7_6_sram[2]:3 mem_left_track_25\/FTB_11__37:A 0.152 +2 mux_tree_tapbuf_size7_6_sram[2]:4 mux_tree_tapbuf_size7_6_sram[2]:3 0.0003370536 +3 mux_tree_tapbuf_size7_6_sram[2]:5 mux_tree_tapbuf_size7_6_sram[2]:4 0.0045 +4 mux_tree_tapbuf_size7_6_sram[2]:7 mux_tree_tapbuf_size7_6_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size7_6_sram[2]:7 mux_left_track_25\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size7_6_sram[2]:6 mux_tree_tapbuf_size7_6_sram[2]:5 0.002348214 +7 mux_tree_tapbuf_size7_6_sram[2]:10 mux_tree_tapbuf_size7_6_sram[2]:9 0.002424107 +8 mux_tree_tapbuf_size7_6_sram[2]:11 mux_tree_tapbuf_size7_6_sram[2]:10 0.0045 +9 mux_tree_tapbuf_size7_6_sram[2]:13 mux_tree_tapbuf_size7_6_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size7_6_sram[2]:12 mux_tree_tapbuf_size7_6_sram[2]:11 0.001741072 +11 mux_tree_tapbuf_size7_6_sram[2]:14 mux_tree_tapbuf_size7_6_sram[2]:13 0.002662946 +12 mux_tree_tapbuf_size7_6_sram[2]:8 mux_tree_tapbuf_size7_6_sram[2]:7 0.0006986608 +13 mux_tree_tapbuf_size7_6_sram[2]:9 mux_tree_tapbuf_size7_6_sram[2]:8 0.0003035714 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[1] 0.00670934 //LENGTH 39.575 LUMPCC 0.001969483 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 65.625 61.200 +*I mux_top_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 56.220 66.640 +*I mux_top_track_0\/mux_l2_in_3_:S I *L 0.00357 *C 48.660 67.320 +*I mux_top_track_0\/mux_l2_in_2_:S I *L 0.00357 *C 45.440 68.680 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 45.255 75.140 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 56.220 68.680 +*N mux_tree_tapbuf_size8_0_sram[1]:6 *C 56.120 68.680 +*N mux_tree_tapbuf_size8_0_sram[1]:7 *C 56.120 68.635 +*N mux_tree_tapbuf_size8_0_sram[1]:8 *C 45.293 75.140 +*N mux_tree_tapbuf_size8_0_sram[1]:9 *C 45.955 75.140 +*N mux_tree_tapbuf_size8_0_sram[1]:10 *C 46.000 75.095 +*N mux_tree_tapbuf_size8_0_sram[1]:11 *C 45.477 68.680 +*N mux_tree_tapbuf_size8_0_sram[1]:12 *C 45.955 68.680 +*N mux_tree_tapbuf_size8_0_sram[1]:13 *C 46.000 68.680 +*N mux_tree_tapbuf_size8_0_sram[1]:14 *C 46.000 67.365 +*N mux_tree_tapbuf_size8_0_sram[1]:15 *C 46.045 67.320 +*N mux_tree_tapbuf_size8_0_sram[1]:16 *C 48.660 67.320 +*N mux_tree_tapbuf_size8_0_sram[1]:17 *C 56.075 67.320 +*N mux_tree_tapbuf_size8_0_sram[1]:18 *C 56.120 67.320 +*N mux_tree_tapbuf_size8_0_sram[1]:19 *C 56.220 66.640 +*N mux_tree_tapbuf_size8_0_sram[1]:20 *C 56.120 66.300 +*N mux_tree_tapbuf_size8_0_sram[1]:21 *C 56.150 66.330 +*N mux_tree_tapbuf_size8_0_sram[1]:22 *C 56.120 66.640 +*N mux_tree_tapbuf_size8_0_sram[1]:23 *C 56.580 66.640 +*N mux_tree_tapbuf_size8_0_sram[1]:24 *C 56.580 61.258 +*N mux_tree_tapbuf_size8_0_sram[1]:25 *C 56.588 61.200 +*N mux_tree_tapbuf_size8_0_sram[1]:26 *C 65.312 61.200 +*N mux_tree_tapbuf_size8_0_sram[1]:27 *C 65.320 61.200 +*N mux_tree_tapbuf_size8_0_sram[1]:28 *C 65.320 61.200 +*N mux_tree_tapbuf_size8_0_sram[1]:29 *C 65.625 61.200 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_0\/mux_l2_in_3_:S 1e-06 +3 mux_top_track_0\/mux_l2_in_2_:S 1e-06 +4 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_0_sram[1]:6 3.406672e-05 +7 mux_tree_tapbuf_size8_0_sram[1]:7 9.946922e-05 +8 mux_tree_tapbuf_size8_0_sram[1]:8 6.35787e-05 +9 mux_tree_tapbuf_size8_0_sram[1]:9 6.35787e-05 +10 mux_tree_tapbuf_size8_0_sram[1]:10 0.0004398652 +11 mux_tree_tapbuf_size8_0_sram[1]:11 5.662955e-05 +12 mux_tree_tapbuf_size8_0_sram[1]:12 5.662955e-05 +13 mux_tree_tapbuf_size8_0_sram[1]:13 0.0005747927 +14 mux_tree_tapbuf_size8_0_sram[1]:14 0.0001007279 +15 mux_tree_tapbuf_size8_0_sram[1]:15 0.0002004731 +16 mux_tree_tapbuf_size8_0_sram[1]:16 0.0007587772 +17 mux_tree_tapbuf_size8_0_sram[1]:17 0.0005275479 +18 mux_tree_tapbuf_size8_0_sram[1]:18 0.0001801485 +19 mux_tree_tapbuf_size8_0_sram[1]:19 7.042006e-05 +20 mux_tree_tapbuf_size8_0_sram[1]:20 7.631312e-05 +21 mux_tree_tapbuf_size8_0_sram[1]:21 2.494324e-05 +22 mux_tree_tapbuf_size8_0_sram[1]:22 0.0001010293 +23 mux_tree_tapbuf_size8_0_sram[1]:23 0.0003894888 +24 mux_tree_tapbuf_size8_0_sram[1]:24 0.000358596 +25 mux_tree_tapbuf_size8_0_sram[1]:25 0.0002021512 +26 mux_tree_tapbuf_size8_0_sram[1]:26 0.0002021512 +27 mux_tree_tapbuf_size8_0_sram[1]:27 3.80047e-05 +28 mux_tree_tapbuf_size8_0_sram[1]:28 5.745672e-05 +29 mux_tree_tapbuf_size8_0_sram[1]:29 5.701831e-05 +30 mux_tree_tapbuf_size8_0_sram[1]:25 chanx_left_in[4]:26 0.0004923707 +31 mux_tree_tapbuf_size8_0_sram[1]:26 chanx_left_in[4]:25 0.0004923707 +32 mux_tree_tapbuf_size8_0_sram[1]:25 chanx_left_in[10]:28 0.0004923707 +33 mux_tree_tapbuf_size8_0_sram[1]:26 chanx_left_in[10]:27 0.0004923707 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_0_sram[1]:29 0.152 +1 mux_tree_tapbuf_size8_0_sram[1]:17 mux_tree_tapbuf_size8_0_sram[1]:16 0.006620537 +2 mux_tree_tapbuf_size8_0_sram[1]:18 mux_tree_tapbuf_size8_0_sram[1]:17 0.0045 +3 mux_tree_tapbuf_size8_0_sram[1]:18 mux_tree_tapbuf_size8_0_sram[1]:7 0.001174107 +4 mux_tree_tapbuf_size8_0_sram[1]:15 mux_tree_tapbuf_size8_0_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size8_0_sram[1]:14 mux_tree_tapbuf_size8_0_sram[1]:13 0.001174107 +6 mux_tree_tapbuf_size8_0_sram[1]:6 mux_top_track_0\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_0_sram[1]:7 mux_tree_tapbuf_size8_0_sram[1]:6 0.0045 +8 mux_tree_tapbuf_size8_0_sram[1]:9 mux_tree_tapbuf_size8_0_sram[1]:8 0.0005915179 +9 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size8_0_sram[1]:8 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size8_0_sram[1]:23 0.004805804 +12 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:24 0.00341 +13 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size8_0_sram[1]:26 0.00341 +14 mux_tree_tapbuf_size8_0_sram[1]:26 mux_tree_tapbuf_size8_0_sram[1]:25 0.001366917 +15 mux_tree_tapbuf_size8_0_sram[1]:28 mux_tree_tapbuf_size8_0_sram[1]:27 0.0045 +16 mux_tree_tapbuf_size8_0_sram[1]:29 mux_tree_tapbuf_size8_0_sram[1]:28 0.0001657609 +17 mux_tree_tapbuf_size8_0_sram[1]:16 mux_top_track_0\/mux_l2_in_3_:S 0.152 +18 mux_tree_tapbuf_size8_0_sram[1]:16 mux_tree_tapbuf_size8_0_sram[1]:15 0.002334822 +19 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:19 0.0001847826 +20 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:20 0.0045 +21 mux_tree_tapbuf_size8_0_sram[1]:19 mux_top_track_0\/mux_l2_in_1_:S 0.152 +22 mux_tree_tapbuf_size8_0_sram[1]:11 mux_top_track_0\/mux_l2_in_2_:S 0.152 +23 mux_tree_tapbuf_size8_0_sram[1]:12 mux_tree_tapbuf_size8_0_sram[1]:11 0.0004263393 +24 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:12 0.0045 +25 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:10 0.005727679 +26 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:21 0.00019375 +27 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:18 0.0006071429 +28 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size8_0_sram[1]:22 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_3_sram[1] 0.006844797 //LENGTH 53.140 LUMPCC 0.000536464 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 32.505 44.540 +*I mux_left_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 27.240 36.430 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 18.115 33.660 +*I mux_left_track_9\/mux_l2_in_3_:S I *L 0.00357 *C 19.680 31.280 +*I mux_left_track_9\/mux_l2_in_2_:S I *L 0.00357 *C 26.340 52.700 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 34.140 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:6 *C 34.140 55.760 +*N mux_tree_tapbuf_size8_3_sram[1]:7 *C 34.040 56.100 +*N mux_tree_tapbuf_size8_3_sram[1]:8 *C 27.645 56.100 +*N mux_tree_tapbuf_size8_3_sram[1]:9 *C 27.600 56.055 +*N mux_tree_tapbuf_size8_3_sram[1]:10 *C 26.378 52.700 +*N mux_tree_tapbuf_size8_3_sram[1]:11 *C 27.555 52.700 +*N mux_tree_tapbuf_size8_3_sram[1]:12 *C 27.600 52.700 +*N mux_tree_tapbuf_size8_3_sram[1]:13 *C 19.643 31.280 +*N mux_tree_tapbuf_size8_3_sram[1]:14 *C 18.905 31.280 +*N mux_tree_tapbuf_size8_3_sram[1]:15 *C 18.860 31.325 +*N mux_tree_tapbuf_size8_3_sram[1]:16 *C 18.152 33.660 +*N mux_tree_tapbuf_size8_3_sram[1]:17 *C 18.815 33.660 +*N mux_tree_tapbuf_size8_3_sram[1]:18 *C 18.860 33.660 +*N mux_tree_tapbuf_size8_3_sram[1]:19 *C 18.860 37.015 +*N mux_tree_tapbuf_size8_3_sram[1]:20 *C 18.905 37.060 +*N mux_tree_tapbuf_size8_3_sram[1]:21 *C 27.600 37.060 +*N mux_tree_tapbuf_size8_3_sram[1]:22 *C 27.240 36.430 +*N mux_tree_tapbuf_size8_3_sram[1]:23 *C 27.283 36.690 +*N mux_tree_tapbuf_size8_3_sram[1]:24 *C 27.600 36.750 +*N mux_tree_tapbuf_size8_3_sram[1]:25 *C 27.600 36.765 +*N mux_tree_tapbuf_size8_3_sram[1]:26 *C 27.600 44.200 +*N mux_tree_tapbuf_size8_3_sram[1]:27 *C 27.645 44.200 +*N mux_tree_tapbuf_size8_3_sram[1]:28 *C 31.740 44.200 +*N mux_tree_tapbuf_size8_3_sram[1]:29 *C 31.740 44.540 +*N mux_tree_tapbuf_size8_3_sram[1]:30 *C 32.468 44.540 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_9\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_9\/mux_l2_in_3_:S 1e-06 +4 mux_left_track_9\/mux_l2_in_2_:S 1e-06 +5 mux_left_track_9\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_3_sram[1]:6 5.526345e-05 +7 mux_tree_tapbuf_size8_3_sram[1]:7 0.0003716423 +8 mux_tree_tapbuf_size8_3_sram[1]:8 0.0003443309 +9 mux_tree_tapbuf_size8_3_sram[1]:9 0.0002252265 +10 mux_tree_tapbuf_size8_3_sram[1]:10 0.0001260862 +11 mux_tree_tapbuf_size8_3_sram[1]:11 0.0001260862 +12 mux_tree_tapbuf_size8_3_sram[1]:12 0.0007516955 +13 mux_tree_tapbuf_size8_3_sram[1]:13 8.007685e-05 +14 mux_tree_tapbuf_size8_3_sram[1]:14 8.007685e-05 +15 mux_tree_tapbuf_size8_3_sram[1]:15 0.0001456028 +16 mux_tree_tapbuf_size8_3_sram[1]:16 8.197517e-05 +17 mux_tree_tapbuf_size8_3_sram[1]:17 8.197517e-05 +18 mux_tree_tapbuf_size8_3_sram[1]:18 0.0003767011 +19 mux_tree_tapbuf_size8_3_sram[1]:19 0.0001956197 +20 mux_tree_tapbuf_size8_3_sram[1]:20 0.0005151422 +21 mux_tree_tapbuf_size8_3_sram[1]:21 0.0005463951 +22 mux_tree_tapbuf_size8_3_sram[1]:22 5.454067e-05 +23 mux_tree_tapbuf_size8_3_sram[1]:23 4.763209e-05 +24 mux_tree_tapbuf_size8_3_sram[1]:24 5.712211e-05 +25 mux_tree_tapbuf_size8_3_sram[1]:25 0.0004546154 +26 mux_tree_tapbuf_size8_3_sram[1]:26 0.0009801004 +27 mux_tree_tapbuf_size8_3_sram[1]:27 0.0002409597 +28 mux_tree_tapbuf_size8_3_sram[1]:28 0.0002615352 +29 mux_tree_tapbuf_size8_3_sram[1]:29 6.125368e-05 +30 mux_tree_tapbuf_size8_3_sram[1]:30 4.067815e-05 +31 mux_tree_tapbuf_size8_3_sram[1]:27 mux_tree_tapbuf_size8_3_sram[0]:8 2.395196e-06 +32 mux_tree_tapbuf_size8_3_sram[1]:27 mux_tree_tapbuf_size8_3_sram[0]:9 0.0001175257 +33 mux_tree_tapbuf_size8_3_sram[1]:30 mux_tree_tapbuf_size8_3_sram[0]:7 3.58035e-05 +34 mux_tree_tapbuf_size8_3_sram[1]:28 mux_tree_tapbuf_size8_3_sram[0]:7 2.395196e-06 +35 mux_tree_tapbuf_size8_3_sram[1]:28 mux_tree_tapbuf_size8_3_sram[0]:10 0.0001228394 +36 mux_tree_tapbuf_size8_3_sram[1]:29 mux_tree_tapbuf_size8_3_sram[0]:8 4.111714e-05 +37 mux_tree_tapbuf_size8_3_sram[1]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.874795e-07 +38 mux_tree_tapbuf_size8_3_sram[1]:25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.34758e-06 +39 mux_tree_tapbuf_size8_3_sram[1]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001034589 +40 mux_tree_tapbuf_size8_3_sram[1]:26 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.874795e-07 +41 mux_tree_tapbuf_size8_3_sram[1]:26 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.34758e-06 +42 mux_tree_tapbuf_size8_3_sram[1]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001034589 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_3_sram[1]:30 0.152 +1 mux_tree_tapbuf_size8_3_sram[1]:10 mux_left_track_9\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size8_3_sram[1]:11 mux_tree_tapbuf_size8_3_sram[1]:10 0.001051339 +3 mux_tree_tapbuf_size8_3_sram[1]:12 mux_tree_tapbuf_size8_3_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size8_3_sram[1]:12 mux_tree_tapbuf_size8_3_sram[1]:9 0.002995536 +5 mux_tree_tapbuf_size8_3_sram[1]:20 mux_tree_tapbuf_size8_3_sram[1]:19 0.0045 +6 mux_tree_tapbuf_size8_3_sram[1]:19 mux_tree_tapbuf_size8_3_sram[1]:18 0.002995536 +7 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:23 0.0001984375 +8 mux_tree_tapbuf_size8_3_sram[1]:24 mux_tree_tapbuf_size8_3_sram[1]:21 0.0002767857 +9 mux_tree_tapbuf_size8_3_sram[1]:25 mux_tree_tapbuf_size8_3_sram[1]:24 0.0045 +10 mux_tree_tapbuf_size8_3_sram[1]:14 mux_tree_tapbuf_size8_3_sram[1]:13 0.0006584821 +11 mux_tree_tapbuf_size8_3_sram[1]:15 mux_tree_tapbuf_size8_3_sram[1]:14 0.0045 +12 mux_tree_tapbuf_size8_3_sram[1]:13 mux_left_track_9\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size8_3_sram[1]:22 mux_left_track_9\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size8_3_sram[1]:8 mux_tree_tapbuf_size8_3_sram[1]:7 0.005709822 +15 mux_tree_tapbuf_size8_3_sram[1]:9 mux_tree_tapbuf_size8_3_sram[1]:8 0.0045 +16 mux_tree_tapbuf_size8_3_sram[1]:6 mux_left_track_9\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size8_3_sram[1]:17 mux_tree_tapbuf_size8_3_sram[1]:16 0.0005915179 +18 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:17 0.0045 +19 mux_tree_tapbuf_size8_3_sram[1]:18 mux_tree_tapbuf_size8_3_sram[1]:15 0.002084822 +20 mux_tree_tapbuf_size8_3_sram[1]:16 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +21 mux_tree_tapbuf_size8_3_sram[1]:27 mux_tree_tapbuf_size8_3_sram[1]:26 0.0045 +22 mux_tree_tapbuf_size8_3_sram[1]:26 mux_tree_tapbuf_size8_3_sram[1]:25 0.006638393 +23 mux_tree_tapbuf_size8_3_sram[1]:26 mux_tree_tapbuf_size8_3_sram[1]:12 0.007589286 +24 mux_tree_tapbuf_size8_3_sram[1]:30 mux_tree_tapbuf_size8_3_sram[1]:29 0.0006495535 +25 mux_tree_tapbuf_size8_3_sram[1]:21 mux_tree_tapbuf_size8_3_sram[1]:20 0.007763393 +26 mux_tree_tapbuf_size8_3_sram[1]:23 mux_tree_tapbuf_size8_3_sram[1]:22 0.0001511628 +27 mux_tree_tapbuf_size8_3_sram[1]:28 mux_tree_tapbuf_size8_3_sram[1]:27 0.00365625 +28 mux_tree_tapbuf_size8_3_sram[1]:7 mux_tree_tapbuf_size8_3_sram[1]:6 0.0003035715 +29 mux_tree_tapbuf_size8_3_sram[1]:29 mux_tree_tapbuf_size8_3_sram[1]:28 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size9_1_sram[2] 0.002380685 //LENGTH 18.520 LUMPCC 0.0004091463 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 95.525 86.020 +*I mux_right_track_2\/mux_l3_in_1_:S I *L 0.00357 *C 96.500 80.240 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 98.155 88.060 +*I mux_right_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 101.560 85.680 +*N mux_tree_tapbuf_size9_1_sram[2]:4 *C 101.523 85.680 +*N mux_tree_tapbuf_size9_1_sram[2]:5 *C 101.200 85.680 +*N mux_tree_tapbuf_size9_1_sram[2]:6 *C 101.200 86.020 +*N mux_tree_tapbuf_size9_1_sram[2]:7 *C 98.155 88.060 +*N mux_tree_tapbuf_size9_1_sram[2]:8 *C 97.980 88.060 +*N mux_tree_tapbuf_size9_1_sram[2]:9 *C 97.980 88.015 +*N mux_tree_tapbuf_size9_1_sram[2]:10 *C 97.980 86.065 +*N mux_tree_tapbuf_size9_1_sram[2]:11 *C 97.980 86.020 +*N mux_tree_tapbuf_size9_1_sram[2]:12 *C 96.463 80.240 +*N mux_tree_tapbuf_size9_1_sram[2]:13 *C 94.805 80.240 +*N mux_tree_tapbuf_size9_1_sram[2]:14 *C 94.760 80.285 +*N mux_tree_tapbuf_size9_1_sram[2]:15 *C 94.760 85.975 +*N mux_tree_tapbuf_size9_1_sram[2]:16 *C 94.805 86.020 +*N mux_tree_tapbuf_size9_1_sram[2]:17 *C 95.525 86.020 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_2\/mux_l3_in_1_:S 1e-06 +2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_right_track_2\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size9_1_sram[2]:4 3.897451e-05 +5 mux_tree_tapbuf_size9_1_sram[2]:5 6.233576e-05 +6 mux_tree_tapbuf_size9_1_sram[2]:6 0.0001587439 +7 mux_tree_tapbuf_size9_1_sram[2]:7 5.29061e-05 +8 mux_tree_tapbuf_size9_1_sram[2]:8 5.360364e-05 +9 mux_tree_tapbuf_size9_1_sram[2]:9 0.0001115342 +10 mux_tree_tapbuf_size9_1_sram[2]:10 0.0001115342 +11 mux_tree_tapbuf_size9_1_sram[2]:11 0.0002727773 +12 mux_tree_tapbuf_size9_1_sram[2]:12 9.949336e-05 +13 mux_tree_tapbuf_size9_1_sram[2]:13 9.949336e-05 +14 mux_tree_tapbuf_size9_1_sram[2]:14 0.0003404656 +15 mux_tree_tapbuf_size9_1_sram[2]:15 0.0003404656 +16 mux_tree_tapbuf_size9_1_sram[2]:16 4.665721e-05 +17 mux_tree_tapbuf_size9_1_sram[2]:17 0.0001785544 +18 mux_tree_tapbuf_size9_1_sram[2]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.962085e-06 +19 mux_tree_tapbuf_size9_1_sram[2]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.533771e-05 +20 mux_tree_tapbuf_size9_1_sram[2]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.533771e-05 +21 mux_tree_tapbuf_size9_1_sram[2]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.962085e-06 +22 mux_tree_tapbuf_size9_1_sram[2]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.203638e-05 +23 mux_tree_tapbuf_size9_1_sram[2]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.203638e-05 +24 mux_tree_tapbuf_size9_1_sram[2]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.242936e-05 +25 mux_tree_tapbuf_size9_1_sram[2]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.242936e-05 +26 mux_tree_tapbuf_size9_1_sram[2]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.523461e-05 +27 mux_tree_tapbuf_size9_1_sram[2]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.801341e-06 +28 mux_tree_tapbuf_size9_1_sram[2]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.801341e-06 +29 mux_tree_tapbuf_size9_1_sram[2]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.523461e-05 +30 mux_tree_tapbuf_size9_1_sram[2]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.777165e-05 +31 mux_tree_tapbuf_size9_1_sram[2]:12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.777165e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size9_1_sram[2]:17 0.152 +1 mux_tree_tapbuf_size9_1_sram[2]:16 mux_tree_tapbuf_size9_1_sram[2]:15 0.0045 +2 mux_tree_tapbuf_size9_1_sram[2]:15 mux_tree_tapbuf_size9_1_sram[2]:14 0.005080358 +3 mux_tree_tapbuf_size9_1_sram[2]:13 mux_tree_tapbuf_size9_1_sram[2]:12 0.001479911 +4 mux_tree_tapbuf_size9_1_sram[2]:14 mux_tree_tapbuf_size9_1_sram[2]:13 0.0045 +5 mux_tree_tapbuf_size9_1_sram[2]:12 mux_right_track_2\/mux_l3_in_1_:S 0.152 +6 mux_tree_tapbuf_size9_1_sram[2]:17 mux_tree_tapbuf_size9_1_sram[2]:16 0.0006428572 +7 mux_tree_tapbuf_size9_1_sram[2]:17 mux_tree_tapbuf_size9_1_sram[2]:11 0.002191964 +8 mux_tree_tapbuf_size9_1_sram[2]:4 mux_right_track_2\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size9_1_sram[2]:11 mux_tree_tapbuf_size9_1_sram[2]:10 0.0045 +10 mux_tree_tapbuf_size9_1_sram[2]:11 mux_tree_tapbuf_size9_1_sram[2]:6 0.002875 +11 mux_tree_tapbuf_size9_1_sram[2]:10 mux_tree_tapbuf_size9_1_sram[2]:9 0.001741072 +12 mux_tree_tapbuf_size9_1_sram[2]:8 mux_tree_tapbuf_size9_1_sram[2]:7 9.51087e-05 +13 mux_tree_tapbuf_size9_1_sram[2]:9 mux_tree_tapbuf_size9_1_sram[2]:8 0.0045 +14 mux_tree_tapbuf_size9_1_sram[2]:7 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +15 mux_tree_tapbuf_size9_1_sram[2]:6 mux_tree_tapbuf_size9_1_sram[2]:5 0.0003035715 +16 mux_tree_tapbuf_size9_1_sram[2]:5 mux_tree_tapbuf_size9_1_sram[2]:4 0.0002879465 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001110956 //LENGTH 7.155 LUMPCC 0.0004304775 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_0_:X O *L 0 *C 54.565 69.700 +*I mux_top_track_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 56.220 74.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 56.183 74.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 54.785 74.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 54.740 74.415 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 54.740 69.745 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 54.740 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 54.565 69.700 + +*CAP +0 mux_top_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001227631 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001227631 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001513232 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001513232 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.301625e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.729009e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 top_left_grid_pin_37_[0]:15 0.0001292553 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 top_left_grid_pin_37_[0]:14 0.0001292553 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 top_left_grid_pin_40_[0]:16 7.973962e-06 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 top_left_grid_pin_40_[0]:17 7.973962e-06 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 top_left_grid_pin_40_[0]:16 1.572904e-06 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 top_left_grid_pin_40_[0]:18 7.643658e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 top_left_grid_pin_40_[0]:15 1.572904e-06 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 top_left_grid_pin_40_[0]:17 7.643658e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001247768 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007765035 //LENGTH 6.120 LUMPCC 9.115366e-05 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_2_:X O *L 0 *C 129.895 46.920 +*I mux_right_track_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 126.405 45.220 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 126.443 45.220 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 128.295 45.220 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 128.340 45.265 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 128.340 46.875 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 128.385 46.920 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 129.858 46.920 + +*CAP +0 mux_right_track_8\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001277164 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001277164 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001134929 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001134929 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001004656 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001004656 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[16]:20 4.557683e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[16]:19 4.557683e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_2_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_8\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005842834 //LENGTH 4.340 LUMPCC 0.0001130319 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_3_:X O *L 0 *C 10.865 71.400 +*I mux_left_track_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 13.025 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 12.880 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 12.880 69.745 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 12.880 71.355 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 12.835 71.400 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 10.902 71.400 + +*CAP +0 mux_left_track_3\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.414018e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001079272 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001079272 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001096285 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001096285 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_2_sram[1]:9 1.451045e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_2_sram[1]:11 4.200548e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_2_sram[1]:10 1.451045e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_2_sram[1]:12 4.200548e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_3_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001725447 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0014375 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_3\/mux_l3_in_1_:A0 0.152 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001618135 //LENGTH 11.135 LUMPCC 0.0004736446 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 39.275 60.520 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.865 56.100 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.865 56.100 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.960 55.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 38.595 55.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 38.640 55.465 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 38.640 60.475 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 38.685 60.520 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 39.238 60.520 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.029886e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002404551 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001971274 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002421304 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002421304 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.517434e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.517434e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001255347 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001255347 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001112876 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001112876 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003245536 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.004473215 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004933036 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006071429 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001332144 //LENGTH 10.080 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_1_:X O *L 0 *C 21.335 30.600 +*I mux_left_track_9\/mux_l4_in_0_:A0 I *L 0.005103 *C 19.780 26.685 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 19.742 26.685 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 17.985 26.685 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 17.940 26.730 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 17.940 30.555 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 17.985 30.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 21.297 30.600 + +*CAP +0 mux_left_track_9\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001862605 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001862605 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002277509 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002277509 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002510605 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002510605 + +*RES +0 mux_left_track_9\/mux_l3_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002957589 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003415179 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001569197 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_9\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005589809 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_2_:X O *L 0 *C 76.075 50.660 +*I mux_top_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 72.780 50.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 72.818 50.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 76.038 50.660 + +*CAP +0 mux_top_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002784904 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002784904 + +*RES +0 mux_top_track_4\/mux_l1_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002875 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007716022 //LENGTH 6.280 LUMPCC 9.645865e-05 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_1_:X O *L 0 *C 74.345 51.000 +*I mux_top_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 75.615 55.080 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 75.578 55.080 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 75.025 55.080 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 74.980 55.035 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 74.980 51.045 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 74.935 51.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 74.383 51.000 + +*CAP +0 mux_top_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.031032e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.031032e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001981342 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001981342 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.812727e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.812727e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[4]:23 4.822933e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[4]:24 4.822933e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004933036 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0035625 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001778631 //LENGTH 12.115 LUMPCC 0.0003895895 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_0_:X O *L 0 *C 85.845 38.760 +*I mux_right_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 92.100 34.340 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 92.062 34.340 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 89.285 34.340 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 89.240 34.385 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 89.240 35.303 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 89.233 35.360 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 86.028 35.360 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 86.020 35.418 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 86.020 38.715 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 86.020 38.760 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 85.845 38.760 + +*CAP +0 mux_right_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001361023 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001361023 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.578287e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.578287e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002173926 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002173926 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002106265 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002106265 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.495505e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 5.22778e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[18]:20 0.0001168995 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[18]:21 0.0001168995 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[18]:20 6.163014e-06 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[18]:21 6.163014e-06 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[17]:16 6.768966e-05 +17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_top_in[17]:15 4.042555e-06 +18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[17]:17 6.768966e-05 +19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_top_in[17]:14 4.042555e-06 + +*RES +0 mux_right_track_16\/mux_l1_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002479911 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0008191965 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005021166 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.002944197 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001170099 //LENGTH 9.450 LUMPCC 0.0002817924 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_3_:X O *L 0 *C 98.155 56.100 +*I mux_right_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 94.055 60.520 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 94.093 60.520 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 95.635 60.520 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 95.680 60.475 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 95.680 56.145 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 95.725 56.100 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 98.118 56.100 + +*CAP +0 mux_right_track_24\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.986479e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.986479e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002456245 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002456245 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001176639 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001176639 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_4_sram[0]:22 7.96662e-07 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size7_4_sram[0]:14 7.185732e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_4_sram[0]:19 7.96662e-07 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size7_4_sram[0]:13 7.185732e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size8_1_sram[1]:7 6.406537e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size8_1_sram[1]:6 6.406537e-05 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size8_1_sram[1]:28 4.176853e-06 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size8_1_sram[1]:8 4.176853e-06 + +*RES +0 mux_right_track_24\/mux_l1_in_3_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002136161 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003866071 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001377232 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_24\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001147073 //LENGTH 9.485 LUMPCC 0.0001149587 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_1_:X O *L 0 *C 36.975 34.000 +*I mux_left_track_17\/mux_l3_in_0_:A0 I *L 0.001631 *C 38.010 26.180 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 37.973 26.180 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 37.305 26.180 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 37.260 26.225 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 37.260 33.955 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 37.260 34.000 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 36.975 34.000 + +*CAP +0 mux_left_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.929053e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.929053e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003877686 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003877686 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.693239e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.906413e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 prog_clk[0]:438 5.747937e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 prog_clk[0]:439 5.747937e-05 + +*RES +0 mux_left_track_17\/mux_l2_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0005959822 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006901786 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004309975 //LENGTH 2.650 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_2_:X O *L 0 *C 39.385 47.260 +*I mux_left_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 39.660 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.560 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.560 45.265 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 39.560 47.215 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.560 47.260 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.385 47.260 + +*CAP +0 mux_left_track_25\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.580555e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001323046 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001323046 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.293855e-05 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.564419e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_2_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_25\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001741072 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.006516065 //LENGTH 58.005 LUMPCC 0.0001032803 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_0_:X O *L 0 *C 105.975 45.560 +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 103.745 99.125 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 103.782 99.225 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 104.375 99.280 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 104.420 99.235 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 104.420 91.800 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 103.960 91.800 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 103.960 45.605 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 104.005 45.560 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 105.938 45.560 + +*CAP +0 mux_top_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.304348e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.304348e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000382982 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004130592 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002629141 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002599064 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001502262 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001502262 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.164013e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.164013e-05 + +*RES +0 mux_top_track_8\/mux_l3_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001725447 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.04124554 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005290179 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004107143 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006638393 + +*END + +*D_NET mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003914051 //LENGTH 34.670 LUMPCC 0.000136937 DR + +*CONN +*I mux_top_track_12\/mux_l2_in_0_:X O *L 0 *C 73.425 67.320 +*I mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 73.765 99.135 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 73.765 99.135 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.725 99.280 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.680 99.235 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.680 79.560 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 73.140 79.560 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 73.140 67.365 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 73.140 67.320 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 73.425 67.320 + +*CAP +0 mux_top_track_12\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001194468 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.358234e-05 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00103106 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00102571 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006978249 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000703175 +8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.718925e-05 +9 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.712497e-05 +10 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 3.162325e-05 +11 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 3.162325e-05 +12 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 3.684526e-05 +13 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 3.684526e-05 + +*RES +0 mux_top_track_12\/mux_l2_in_0_:X mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0009285714 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01088839 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001548913 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01756697 +8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004107143 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.007107551 //LENGTH 49.750 LUMPCC 0.002602474 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_0_:X O *L 0 *C 61.465 59.160 +*I mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 68.785 99.135 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 68.785 99.135 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 65.365 99.280 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 65.320 99.235 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 65.320 97.978 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 65.312 97.920 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 62.580 97.920 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 62.560 97.913 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 62.560 62.568 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 62.545 62.560 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 62.103 62.560 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 62.100 62.503 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 62.100 59.205 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 62.055 59.160 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:15 *C 61.503 59.160 + +*CAP +0 mux_top_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002080564 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001686561 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.767911e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.767911e-05 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000233966 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000233966 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001300606 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001300606 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001076388 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001076388 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0002545244 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0002545244 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:14 6.876823e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:15 6.876823e-05 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[9]:10 0.0006551254 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[9]:11 0.0006551254 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 top_left_grid_pin_34_[0]:35 0.0005334934 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 top_left_grid_pin_34_[0]:36 0.0005334934 +20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 ropt_net_166:3 0.000112618 +21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 ropt_net_166:4 0.000112618 + +*RES +0 mux_top_track_16\/mux_l2_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.0004933036 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.002944197 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.00341 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 6.499219e-05 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.00341 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.005537383 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004280916 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001122768 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003053572 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006558859 //LENGTH 4.775 LUMPCC 9.817767e-05 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 78.485 38.760 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 79.680 36.380 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 79.642 36.380 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 78.245 36.380 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 78.200 36.425 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 78.200 38.715 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.200 38.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 78.485 38.760 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.899556e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.899556e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001522638 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001522638 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.773724e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.545229e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_6_sram[1]:3 4.908883e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_6_sram[1]:4 4.908883e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01230617 //LENGTH 93.250 LUMPCC 0.003900473 DR + +*CONN +*I mux_top_track_28\/mux_l2_in_0_:X O *L 0 *C 66.525 31.280 +*I mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 89.560 99.090 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 88.840 94.520 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 89.523 99.023 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 89.270 98.970 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 89.240 98.895 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 89.240 94.578 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 89.240 94.520 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 89.240 94.513 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 89.240 81.795 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 89.240 31.968 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 89.220 31.960 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 79.127 31.960 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 79.120 31.960 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 79.120 31.620 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 79.075 31.620 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:16 *C 71.760 31.620 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:17 *C 71.760 31.280 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:18 *C 66.562 31.280 + +*CAP +0 mux_top_track_28\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.051761e-05 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.552046e-05 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.552046e-05 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002360538 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002360538 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.051761e-05 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000312619 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.002131158 +10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001818538 +11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0007603146 +12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0007603146 +13 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:13 6.560644e-05 +14 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:14 6.111602e-05 +15 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0005359725 +16 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.0005611936 +17 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:17 0.0003689495 +18 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:18 0.0003437285 +19 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.687569e-06 +20 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.687569e-06 +21 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002833124 +22 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0005682899 +23 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0005682899 +24 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0002833124 +25 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.855718e-06 +26 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.855718e-06 +27 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001630581 +28 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 1.47117e-05 +29 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0009133212 +30 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001076379 +31 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_2_X[0]:10 1.47117e-05 + +*RES +0 mux_top_track_28\/mux_l2_in_0_:X mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:18 0.152 +1 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001578125 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.003854911 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.69697e-05 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.00341 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.007806308 +10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.00341 +11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.001581158 +12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0045 +13 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0001634615 +14 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:18 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:17 0.004640626 +15 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:17 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.0003035714 +16 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:16 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.00653125 +17 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001992408 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006025415 //LENGTH 4.270 LUMPCC 7.807191e-05 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_1_:X O *L 0 *C 100.105 83.640 +*I mux_right_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 100.455 86.360 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 100.418 86.360 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 99.865 86.360 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 99.820 86.315 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 99.820 83.685 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 99.820 83.640 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 100.105 83.640 + +*CAP +0 mux_right_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.376859e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.376859e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001735795 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001735795 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.39292e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.384424e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size9_1_sram[2]:6 3.523461e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size9_1_sram[2]:11 3.523461e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size9_1_sram[2]:9 3.801341e-06 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size9_1_sram[2]:10 3.801341e-06 + +*RES +0 mux_right_track_2\/mux_l2_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004933036 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006509725 //LENGTH 4.340 LUMPCC 0.0002064773 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_0_:X O *L 0 *C 102.405 85.000 +*I mux_right_track_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 104.420 83.300 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 104.420 83.300 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 104.420 83.345 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 104.420 84.955 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 104.375 85.000 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 102.443 85.000 + +*CAP +0 mux_right_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.482435e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.611059e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.611059e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001577249 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001577249 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:5 5.159849e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size9_mem_1_ccff_tail[0]:4 5.159849e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.164013e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.164013e-05 + +*RES +0 mux_right_track_2\/mux_l3_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001725447 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0014375 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_2\/mux_l4_in_0_:A1 0.152 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004378834 //LENGTH 2.755 LUMPCC 0.0002714303 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_2_:X O *L 0 *C 107.465 69.360 +*I mux_right_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 109.480 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 109.480 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 109.480 69.360 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 107.503 69.360 + +*CAP +0 mux_right_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.357895e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.703928e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.383493e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:31 6.233079e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:32 1.944955e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:20 3.721009e-06 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:22 2.33028e-08 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:21 2.317055e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:23 2.33028e-08 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:32 6.233079e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size14_0_sram[1]:29 4.801886e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size14_0_sram[1]:27 2.149877e-06 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size14_0_sram[1]:30 2.175581e-08 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_0_sram[1]:28 5.016874e-05 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size14_0_sram[1]:29 2.175581e-08 + +*RES +0 mux_right_track_4\/mux_l1_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001765625 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A1 0.152 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035714 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0] 0.002816399 //LENGTH 22.440 LUMPCC 0.000736015 DR + +*CONN +*I mux_left_track_5\/mux_l4_in_0_:X O *L 0 *C 16.735 41.480 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.910 28.390 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 9.910 28.390 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 9.660 28.560 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 *C 9.660 28.605 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 *C 9.660 41.775 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 *C 9.705 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 *C 17.020 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 *C 17.020 41.515 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 *C 16.762 41.503 + +*CAP +0 mux_left_track_5\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 4.727353e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 4.92026e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0007021615 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0007021615 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0002462236 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.0002711004 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 4.256888e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 1.769211e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 chanx_right_in[6]:6 2.386367e-06 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 chanx_right_in[6]:6 9.507647e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 chanx_right_in[6]:7 9.507647e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 chanx_right_in[6]:7 2.386367e-06 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 ropt_net_143:5 0.0002190137 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 ropt_net_143:3 1.74102e-06 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 ropt_net_143:4 1.74102e-06 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 ropt_net_143:6 0.0002190137 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 ropt_net_160:7 4.160959e-05 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 ropt_net_160:6 8.180304e-06 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 ropt_net_160:5 8.180304e-06 +21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 ropt_net_160:8 4.160959e-05 + +*RES +0 mux_left_track_5\/mux_l4_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 0.0001739865 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.01175893 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0001358696 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.006531251 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.0002723215 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006025983 //LENGTH 3.320 LUMPCC 0.0003796248 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_2_:X O *L 0 *C 92.175 72.420 +*I mux_right_track_32\/mux_l2_in_1_:A1 I *L 0.00198 *C 89.145 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 89.183 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.138 72.420 + +*CAP +0 mux_right_track_32\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001104867 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001104867 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 right_top_grid_pin_49_[0]:9 6.79919e-05 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 right_top_grid_pin_49_[0]:10 6.79919e-05 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size6_0_sram[0]:16 0.0001218205 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_0_sram[0]:17 0.0001218205 + +*RES +0 mux_right_track_32\/mux_l1_in_2_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_32\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002638393 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001070614 //LENGTH 7.075 LUMPCC 0.0003852262 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_1_:X O *L 0 *C 43.875 60.860 +*I mux_left_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 37.090 60.860 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 37.128 60.860 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 43.837 60.860 + +*CAP +0 mux_left_track_33\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003416939 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003416939 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[11]:9 0.0001089783 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_top_in[11]:8 0.0001089783 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_1_sram[1]:5 8.363481e-05 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_1_sram[1]:4 8.363481e-05 + +*RES +0 mux_left_track_33\/mux_l1_in_1_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.005991071 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_33\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.007647157 //LENGTH 49.630 LUMPCC 0.001627173 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 71.935 89.080 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.305 72.420 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.343 72.420 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.815 72.420 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 41.860 72.465 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 41.860 75.422 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 41.867 75.480 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 47.820 75.480 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 47.840 75.487 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 47.840 85.672 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 47.860 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 63.013 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 63.020 85.737 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 63.020 89.035 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 63.065 89.080 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 *C 71.898 89.080 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.656642e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.656642e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001887502 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001887502 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004872088 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004872088 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0006887782 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0006887782 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0007790915 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0007790915 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001927328 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0001927328 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.0005958641 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 0.0005958641 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 top_left_grid_pin_41_[0] 3.167828e-06 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 top_left_grid_pin_41_[0]:20 0.0002868753 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 top_left_grid_pin_41_[0]:19 0.0002868753 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 top_left_grid_pin_41_[0]:28 3.167828e-06 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size7_0_sram[0]:15 0.000426976 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_tree_tapbuf_size7_0_sram[0]:18 2.381601e-05 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_tree_tapbuf_size7_0_sram[0]:16 0.000426976 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_tree_tapbuf_size7_0_sram[0]:17 2.381601e-05 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.275127e-05 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.275127e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002640625 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009325583 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.00341 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.00159565 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.00341 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002373892 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0045 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.002944197 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.007886162 + +*END + +*D_NET chanx_left_out[5] 0.001689313 //LENGTH 12.655 LUMPCC 0.0003088455 DR + +*CONN +*I FTB_3__2:X O *L 0 *C 10.580 63.580 +*P chanx_left_out[5] O *L 0.7423 *C 1.298 61.200 +*N chanx_left_out[5]:2 *C 1.380 61.200 +*N chanx_left_out[5]:3 *C 1.380 61.200 +*N chanx_left_out[5]:4 *C 2.300 61.200 +*N chanx_left_out[5]:5 *C 2.300 63.535 +*N chanx_left_out[5]:6 *C 2.345 63.580 +*N chanx_left_out[5]:7 *C 10.543 63.580 + +*CAP +0 FTB_3__2:X 1e-06 +1 chanx_left_out[5] 3.269513e-05 +2 chanx_left_out[5]:2 3.269513e-05 +3 chanx_left_out[5]:3 9.195154e-05 +4 chanx_left_out[5]:4 0.0002060331 +5 chanx_left_out[5]:5 0.0001492386 +6 chanx_left_out[5]:6 0.0004334271 +7 chanx_left_out[5]:7 0.0004334271 +8 chanx_left_out[5]:7 ropt_net_162:7 0.0001079198 +9 chanx_left_out[5]:7 ropt_net_162:3 4.586371e-05 +10 chanx_left_out[5]:6 ropt_net_162:6 0.0001079198 +11 chanx_left_out[5]:6 ropt_net_162:2 4.586371e-05 +12 chanx_left_out[5]:5 ropt_net_162:4 6.392504e-07 +13 chanx_left_out[5]:4 ropt_net_162:5 6.392504e-07 + +*RES +0 FTB_3__2:X chanx_left_out[5]:7 0.152 +1 chanx_left_out[5]:7 chanx_left_out[5]:6 0.007319197 +2 chanx_left_out[5]:6 chanx_left_out[5]:5 0.0045 +3 chanx_left_out[5]:5 chanx_left_out[5]:4 0.002084821 +4 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +5 chanx_left_out[5]:2 chanx_left_out[5] 2.35e-05 +6 chanx_left_out[5]:4 chanx_left_out[5]:3 0.0008214285 + +*END + +*D_NET chany_top_out[10] 0.0009376825 //LENGTH 7.205 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 100.925 99.620 +*P chany_top_out[10] O *L 0.7423 *C 96.600 102.035 +*N chany_top_out[10]:2 *C 96.600 99.665 +*N chany_top_out[10]:3 *C 96.645 99.620 +*N chany_top_out[10]:4 *C 100.888 99.620 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 chany_top_out[10] 0.0001409992 +2 chany_top_out[10]:2 0.0001409992 +3 chany_top_out[10]:3 0.000327342 +4 chany_top_out[10]:4 0.000327342 + +*RES +0 ropt_mt_inst_755:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +2 chany_top_out[10]:2 chany_top_out[10] 0.002116072 +3 chany_top_out[10]:4 chany_top_out[10]:3 0.003787946 + +*END + +*D_NET ropt_net_144 0.001676051 //LENGTH 13.350 LUMPCC 0.0004497792 DR + +*CONN +*I FTB_20__19:X O *L 0 *C 134.780 30.940 +*I ropt_mt_inst_767:A I *L 0.001766 *C 130.180 23.120 +*N ropt_net_144:2 *C 130.218 23.120 +*N ropt_net_144:3 *C 133.815 23.120 +*N ropt_net_144:4 *C 133.860 23.165 +*N ropt_net_144:5 *C 133.860 30.895 +*N ropt_net_144:6 *C 133.905 30.940 +*N ropt_net_144:7 *C 134.743 30.940 + +*CAP +0 FTB_20__19:X 1e-06 +1 ropt_mt_inst_767:A 1e-06 +2 ropt_net_144:2 0.0001499739 +3 ropt_net_144:3 0.0001499739 +4 ropt_net_144:4 0.0003932483 +5 ropt_net_144:5 0.0003932483 +6 ropt_net_144:6 6.891378e-05 +7 ropt_net_144:7 6.891378e-05 +8 ropt_net_144:2 chanx_right_out[2]:6 0.0001465556 +9 ropt_net_144:3 chanx_right_out[2]:5 0.0001465556 +10 ropt_net_144:4 ropt_net_155:8 7.833396e-05 +11 ropt_net_144:5 ropt_net_155:9 7.833396e-05 + +*RES +0 FTB_20__19:X ropt_net_144:7 0.152 +1 ropt_net_144:2 ropt_mt_inst_767:A 0.152 +2 ropt_net_144:3 ropt_net_144:2 0.003212054 +3 ropt_net_144:4 ropt_net_144:3 0.0045 +4 ropt_net_144:6 ropt_net_144:5 0.0045 +5 ropt_net_144:5 ropt_net_144:4 0.006901786 +6 ropt_net_144:7 ropt_net_144:6 0.0007477679 + +*END + +*D_NET chanx_right_out[17] 0.001925066 //LENGTH 15.515 LUMPCC 0.0001219694 DR + +*CONN +*I ropt_mt_inst_759:X O *L 0 *C 133.400 69.360 +*P chanx_right_out[17] O *L 0.7423 *C 140.375 62.560 +*N chanx_right_out[17]:2 *C 140.300 62.560 +*N chanx_right_out[17]:3 *C 138.468 62.560 +*N chanx_right_out[17]:4 *C 138.460 62.617 +*N chanx_right_out[17]:5 *C 138.460 65.222 +*N chanx_right_out[17]:6 *C 138.453 65.280 +*N chanx_right_out[17]:7 *C 134.328 65.280 +*N chanx_right_out[17]:8 *C 134.320 65.338 +*N chanx_right_out[17]:9 *C 134.320 69.315 +*N chanx_right_out[17]:10 *C 134.275 69.360 +*N chanx_right_out[17]:11 *C 133.438 69.360 + +*CAP +0 ropt_mt_inst_759:X 1e-06 +1 chanx_right_out[17] 1.837175e-05 +2 chanx_right_out[17]:2 0.0001421078 +3 chanx_right_out[17]:3 0.0001237361 +4 chanx_right_out[17]:4 0.0001779151 +5 chanx_right_out[17]:5 0.0001779151 +6 chanx_right_out[17]:6 0.0002866096 +7 chanx_right_out[17]:7 0.0002866096 +8 chanx_right_out[17]:8 0.0001952297 +9 chanx_right_out[17]:9 0.0001952297 +10 chanx_right_out[17]:10 9.91862e-05 +11 chanx_right_out[17]:11 9.91862e-05 +12 chanx_right_out[17]:9 ropt_net_151:3 6.09847e-05 +13 chanx_right_out[17]:8 ropt_net_151:4 6.09847e-05 + +*RES +0 ropt_mt_inst_759:X chanx_right_out[17]:11 0.152 +1 chanx_right_out[17]:11 chanx_right_out[17]:10 0.0007477679 +2 chanx_right_out[17]:10 chanx_right_out[17]:9 0.0045 +3 chanx_right_out[17]:9 chanx_right_out[17]:8 0.003551339 +4 chanx_right_out[17]:8 chanx_right_out[17]:7 0.00341 +5 chanx_right_out[17]:7 chanx_right_out[17]:6 0.00064625 +6 chanx_right_out[17]:5 chanx_right_out[17]:4 0.002325893 +7 chanx_right_out[17]:6 chanx_right_out[17]:5 0.00341 +8 chanx_right_out[17]:4 chanx_right_out[17]:3 0.00341 +9 chanx_right_out[17]:3 chanx_right_out[17]:2 0.0002870917 +10 chanx_right_out[17]:2 chanx_right_out[17] 1.175e-05 + +*END + +*D_NET chanx_left_out[17] 0.0005969027 //LENGTH 4.405 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 4.140 44.200 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 43.520 +*N chanx_left_out[17]:2 *C 3.213 43.520 +*N chanx_left_out[17]:3 *C 3.220 43.578 +*N chanx_left_out[17]:4 *C 3.220 44.155 +*N chanx_left_out[17]:5 *C 3.265 44.200 +*N chanx_left_out[17]:6 *C 4.103 44.200 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 chanx_left_out[17] 0.00016256 +2 chanx_left_out[17]:2 0.00016256 +3 chanx_left_out[17]:3 5.447837e-05 +4 chanx_left_out[17]:4 5.447837e-05 +5 chanx_left_out[17]:5 8.091301e-05 +6 chanx_left_out[17]:6 8.091301e-05 + +*RES +0 ropt_mt_inst_783:X chanx_left_out[17]:6 0.152 +1 chanx_left_out[17]:6 chanx_left_out[17]:5 0.0007477679 +2 chanx_left_out[17]:5 chanx_left_out[17]:4 0.0045 +3 chanx_left_out[17]:4 chanx_left_out[17]:3 0.000515625 +4 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +5 chanx_left_out[17]:2 chanx_left_out[17] 0.0003105917 + +*END + +*D_NET ropt_net_146 0.00104147 //LENGTH 7.250 LUMPCC 0.000421855 DR + +*CONN +*I BUFT_RR_73:X O *L 0 *C 130.640 56.440 +*I ropt_mt_inst_769:A I *L 0.001766 *C 134.780 58.480 +*N ropt_net_146:2 *C 134.757 58.453 +*N ropt_net_146:3 *C 134.745 58.140 +*N ropt_net_146:4 *C 132.065 58.140 +*N ropt_net_146:5 *C 132.020 58.095 +*N ropt_net_146:6 *C 132.020 56.485 +*N ropt_net_146:7 *C 131.975 56.440 +*N ropt_net_146:8 *C 130.678 56.440 + +*CAP +0 BUFT_RR_73:X 1e-06 +1 ropt_mt_inst_769:A 1e-06 +2 ropt_net_146:2 3.539812e-05 +3 ropt_net_146:3 0.0001498524 +4 ropt_net_146:4 0.0001144542 +5 ropt_net_146:5 4.61066e-05 +6 ropt_net_146:6 4.61066e-05 +7 ropt_net_146:7 0.0001128485 +8 ropt_net_146:8 0.0001128485 +9 ropt_net_146:5 chanx_left_in[9]:9 5.218683e-05 +10 ropt_net_146:6 chanx_left_in[9]:8 5.218683e-05 +11 ropt_net_146:5 right_bottom_grid_pin_1_[0]:13 5.145044e-05 +12 ropt_net_146:6 right_bottom_grid_pin_1_[0]:15 5.145044e-05 +13 ropt_net_146:4 chanx_right_out[11]:7 0.0001072903 +14 ropt_net_146:3 chanx_right_out[11]:6 0.0001072903 + +*RES +0 BUFT_RR_73:X ropt_net_146:8 0.152 +1 ropt_net_146:2 ropt_mt_inst_769:A 0.152 +2 ropt_net_146:4 ropt_net_146:3 0.002392857 +3 ropt_net_146:5 ropt_net_146:4 0.0045 +4 ropt_net_146:7 ropt_net_146:6 0.0045 +5 ropt_net_146:6 ropt_net_146:5 0.0014375 +6 ropt_net_146:8 ropt_net_146:7 0.001158482 +7 ropt_net_146:3 ropt_net_146:2 0.0002111487 + +*END + +*D_NET chanx_right_out[3] 0.001028115 //LENGTH 7.320 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 138.655 71.400 +*P chanx_right_out[3] O *L 0.7423 *C 140.450 68.000 +*N chanx_right_out[3]:2 *C 138.007 68.000 +*N chanx_right_out[3]:3 *C 138.000 68.058 +*N chanx_right_out[3]:4 *C 138.000 71.355 +*N chanx_right_out[3]:5 *C 138.045 71.400 +*N chanx_right_out[3]:6 *C 138.618 71.400 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 chanx_right_out[3] 0.0001739216 +2 chanx_right_out[3]:2 0.0001739216 +3 chanx_right_out[3]:3 0.0002603419 +4 chanx_right_out[3]:4 0.0002603419 +5 chanx_right_out[3]:5 7.929398e-05 +6 chanx_right_out[3]:6 7.929398e-05 + +*RES +0 ropt_mt_inst_774:X chanx_right_out[3]:6 0.152 +1 chanx_right_out[3]:6 chanx_right_out[3]:5 0.0005111608 +2 chanx_right_out[3]:5 chanx_right_out[3]:4 0.0045 +3 chanx_right_out[3]:4 chanx_right_out[3]:3 0.002944197 +4 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +5 chanx_right_out[3]:2 chanx_right_out[3] 0.0003826583 + +*END + +*D_NET chanx_right_out[9] 0.0008841953 //LENGTH 6.465 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 136.160 42.160 +*P chanx_right_out[9] O *L 0.7423 *C 140.450 40.800 +*N chanx_right_out[9]:2 *C 136.627 40.800 +*N chanx_right_out[9]:3 *C 136.620 40.858 +*N chanx_right_out[9]:4 *C 136.620 42.115 +*N chanx_right_out[9]:5 *C 136.575 42.160 +*N chanx_right_out[9]:6 *C 136.198 42.160 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 chanx_right_out[9] 0.0002962149 +2 chanx_right_out[9]:2 0.0002962149 +3 chanx_right_out[9]:3 9.977491e-05 +4 chanx_right_out[9]:4 9.977491e-05 +5 chanx_right_out[9]:5 4.560778e-05 +6 chanx_right_out[9]:6 4.560778e-05 + +*RES +0 ropt_mt_inst_791:X chanx_right_out[9]:6 0.152 +1 chanx_right_out[9]:6 chanx_right_out[9]:5 0.0003370536 +2 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0045 +3 chanx_right_out[9]:4 chanx_right_out[9]:3 0.001122768 +4 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +5 chanx_right_out[9]:2 chanx_right_out[9] 0.0005988583 + +*END + +*D_NET ropt_net_151 0.001166308 //LENGTH 9.065 LUMPCC 0.0001219694 DR + +*CONN +*I BUFT_P_95:X O *L 0 *C 131.100 67.320 +*I ropt_mt_inst_774:A I *L 0.001766 *C 134.780 72.080 +*N ropt_net_151:2 *C 134.780 72.080 +*N ropt_net_151:3 *C 134.780 72.035 +*N ropt_net_151:4 *C 134.780 67.365 +*N ropt_net_151:5 *C 134.735 67.320 +*N ropt_net_151:6 *C 131.138 67.320 + +*CAP +0 BUFT_P_95:X 1e-06 +1 ropt_mt_inst_774:A 1e-06 +2 ropt_net_151:2 3.730069e-05 +3 ropt_net_151:3 0.000244468 +4 ropt_net_151:4 0.000244468 +5 ropt_net_151:5 0.0002580511 +6 ropt_net_151:6 0.0002580511 +7 ropt_net_151:3 chanx_right_out[17]:9 6.09847e-05 +8 ropt_net_151:4 chanx_right_out[17]:8 6.09847e-05 + +*RES +0 BUFT_P_95:X ropt_net_151:6 0.152 +1 ropt_net_151:2 ropt_mt_inst_774:A 0.152 +2 ropt_net_151:3 ropt_net_151:2 0.0045 +3 ropt_net_151:5 ropt_net_151:4 0.0045 +4 ropt_net_151:4 ropt_net_151:3 0.004169643 +5 ropt_net_151:6 ropt_net_151:5 0.003212054 + +*END + +*D_NET chanx_right_out[11] 0.001573968 //LENGTH 12.315 LUMPCC 0.0002145805 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 131.100 57.800 +*P chanx_right_out[11] O *L 0.7423 *C 140.382 55.760 +*N chanx_right_out[11]:2 *C 140.300 55.760 +*N chanx_right_out[11]:3 *C 140.300 55.760 +*N chanx_right_out[11]:4 *C 138.920 55.760 +*N chanx_right_out[11]:5 *C 138.920 57.755 +*N chanx_right_out[11]:6 *C 138.875 57.800 +*N chanx_right_out[11]:7 *C 131.138 57.800 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 chanx_right_out[11] 2.966815e-05 +2 chanx_right_out[11]:2 2.966815e-05 +3 chanx_right_out[11]:3 0.0001000876 +4 chanx_right_out[11]:4 0.0001834372 +5 chanx_right_out[11]:5 0.000113354 +6 chanx_right_out[11]:6 0.0004510862 +7 chanx_right_out[11]:7 0.0004510862 +8 chanx_right_out[11]:7 ropt_net_146:4 0.0001072903 +9 chanx_right_out[11]:6 ropt_net_146:3 0.0001072903 + +*RES +0 ropt_mt_inst_798:X chanx_right_out[11]:7 0.152 +1 chanx_right_out[11]:7 chanx_right_out[11]:6 0.006908482 +2 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0045 +3 chanx_right_out[11]:5 chanx_right_out[11]:4 0.00178125 +4 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +5 chanx_right_out[11]:2 chanx_right_out[11] 2.35e-05 +6 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001232143 + +*END + +*D_NET chanx_left_in[2] 0.02282892 //LENGTH 152.565 LUMPCC 0.004738199 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 51.680 +*I mux_top_track_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 47.380 66.980 +*I BUFT_P_95:A I *L 0.001767 *C 130.180 66.640 +*I mux_right_track_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 132.275 64.260 +*N chanx_left_in[2]:4 *C 132.275 64.260 +*N chanx_left_in[2]:5 *C 132.020 64.260 +*N chanx_left_in[2]:6 *C 132.020 64.305 +*N chanx_left_in[2]:7 *C 132.020 66.595 +*N chanx_left_in[2]:8 *C 131.975 66.640 +*N chanx_left_in[2]:9 *C 130.180 66.640 +*N chanx_left_in[2]:10 *C 129.305 66.640 +*N chanx_left_in[2]:11 *C 129.260 66.640 +*N chanx_left_in[2]:12 *C 129.260 66.648 +*N chanx_left_in[2]:13 *C 129.260 67.320 +*N chanx_left_in[2]:14 *C 97.380 67.320 +*N chanx_left_in[2]:15 *C 47.380 66.980 +*N chanx_left_in[2]:16 *C 47.380 66.980 +*N chanx_left_in[2]:17 *C 47.380 67.320 +*N chanx_left_in[2]:18 *C 47.380 67.320 +*N chanx_left_in[2]:19 *C 44.168 67.320 +*N chanx_left_in[2]:20 *C 44.160 67.320 +*N chanx_left_in[2]:21 *C 44.115 67.320 +*N chanx_left_in[2]:22 *C 23.505 67.320 +*N chanx_left_in[2]:23 *C 23.460 67.320 +*N chanx_left_in[2]:24 *C 23.453 67.320 +*N chanx_left_in[2]:25 *C 16.580 67.320 +*N chanx_left_in[2]:26 *C 16.560 67.312 +*N chanx_left_in[2]:27 *C 16.560 51.688 +*N chanx_left_in[2]:28 *C 16.540 51.680 + +*CAP +0 chanx_left_in[2] 0.0006089371 +1 mux_top_track_0\/mux_l2_in_3_:A1 1e-06 +2 BUFT_P_95:A 1e-06 +3 mux_right_track_0\/mux_l2_in_2_:A0 1e-06 +4 chanx_left_in[2]:4 5.799564e-05 +5 chanx_left_in[2]:5 6.258581e-05 +6 chanx_left_in[2]:6 0.0001447421 +7 chanx_left_in[2]:7 0.0001447421 +8 chanx_left_in[2]:8 0.0001184048 +9 chanx_left_in[2]:9 0.0002355809 +10 chanx_left_in[2]:10 8.557169e-05 +11 chanx_left_in[2]:11 3.751703e-05 +12 chanx_left_in[2]:12 5.177753e-05 +13 chanx_left_in[2]:13 0.001514776 +14 chanx_left_in[2]:14 0.004393062 +15 chanx_left_in[2]:15 3.390714e-05 +16 chanx_left_in[2]:16 5.591352e-05 +17 chanx_left_in[2]:17 6.24919e-05 +18 chanx_left_in[2]:18 0.003245984 +19 chanx_left_in[2]:19 0.000315921 +20 chanx_left_in[2]:20 3.877322e-05 +21 chanx_left_in[2]:21 0.001463438 +22 chanx_left_in[2]:22 0.001463438 +23 chanx_left_in[2]:23 3.806881e-05 +24 chanx_left_in[2]:24 0.0006102927 +25 chanx_left_in[2]:25 0.0006102927 +26 chanx_left_in[2]:26 0.001042284 +27 chanx_left_in[2]:27 0.001042284 +28 chanx_left_in[2]:28 0.0006089371 +29 chanx_left_in[2]:18 chanx_left_in[10]:24 5.839212e-06 +30 chanx_left_in[2]:18 chanx_left_in[10]:19 0.0003584521 +31 chanx_left_in[2]:13 chanx_left_in[10]:14 2.216709e-05 +32 chanx_left_in[2]:14 chanx_left_in[10]:15 2.216709e-05 +33 chanx_left_in[2]:14 chanx_left_in[10]:18 0.0003584521 +34 chanx_left_in[2]:14 chanx_left_in[10]:22 5.839212e-06 +35 chanx_left_in[2] chanx_left_in[12]:22 0.0003231234 +36 chanx_left_in[2]:28 chanx_left_in[12]:21 0.0003231234 +37 chanx_left_in[2]:18 chany_top_in[1]:11 0.0004483522 +38 chanx_left_in[2]:18 chany_top_in[1]:10 2.16599e-05 +39 chanx_left_in[2]:14 chany_top_in[1]:11 2.16599e-05 +40 chanx_left_in[2]:14 chany_top_in[1]:6 0.0004483522 +41 chanx_left_in[2] chanx_left_in[3] 0.0003511653 +42 chanx_left_in[2]:28 chanx_left_in[3]:10 0.0003511653 +43 chanx_left_in[2]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.554639e-05 +44 chanx_left_in[2]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.554639e-05 +45 chanx_left_in[2]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001444674 +46 chanx_left_in[2]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 9.238493e-05 +47 chanx_left_in[2]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001444674 +48 chanx_left_in[2]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 9.238493e-05 +49 chanx_left_in[2]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001523913 +50 chanx_left_in[2]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001523913 +51 chanx_left_in[2]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.780928e-06 +52 chanx_left_in[2]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.780928e-06 +53 chanx_left_in[2]:18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.159918e-05 +54 chanx_left_in[2]:13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003801698 +55 chanx_left_in[2]:14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003801698 +56 chanx_left_in[2]:14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.159918e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:28 0.002398567 +1 chanx_left_in[2]:10 chanx_left_in[2]:9 0.00078125 +2 chanx_left_in[2]:11 chanx_left_in[2]:10 0.0045 +3 chanx_left_in[2]:12 chanx_left_in[2]:11 0.00341 +4 chanx_left_in[2]:20 chanx_left_in[2]:19 0.00341 +5 chanx_left_in[2]:19 chanx_left_in[2]:18 0.0005032917 +6 chanx_left_in[2]:21 chanx_left_in[2]:20 0.0045 +7 chanx_left_in[2]:22 chanx_left_in[2]:21 0.01840179 +8 chanx_left_in[2]:23 chanx_left_in[2]:22 0.0045 +9 chanx_left_in[2]:24 chanx_left_in[2]:23 0.00341 +10 chanx_left_in[2]:25 chanx_left_in[2]:24 0.001076692 +11 chanx_left_in[2]:26 chanx_left_in[2]:25 0.00341 +12 chanx_left_in[2]:28 chanx_left_in[2]:27 0.00341 +13 chanx_left_in[2]:27 chanx_left_in[2]:26 0.002447916 +14 chanx_left_in[2]:9 BUFT_P_95:A 0.152 +15 chanx_left_in[2]:9 chanx_left_in[2]:8 0.001602679 +16 chanx_left_in[2]:8 chanx_left_in[2]:7 0.0045 +17 chanx_left_in[2]:7 chanx_left_in[2]:6 0.002044643 +18 chanx_left_in[2]:5 chanx_left_in[2]:4 0.000138587 +19 chanx_left_in[2]:6 chanx_left_in[2]:5 0.0045 +20 chanx_left_in[2]:4 mux_right_track_0\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[2]:17 chanx_left_in[2]:16 0.0001057692 +22 chanx_left_in[2]:18 chanx_left_in[2]:17 0.00341 +23 chanx_left_in[2]:18 chanx_left_in[2]:14 0.007833333 +24 chanx_left_in[2]:15 mux_top_track_0\/mux_l2_in_3_:A1 0.152 +25 chanx_left_in[2]:16 chanx_left_in[2]:15 0.0045 +26 chanx_left_in[2]:13 chanx_left_in[2]:12 0.0001053583 +27 chanx_left_in[2]:14 chanx_left_in[2]:13 0.004994533 + +*END + +*D_NET chanx_right_out[16] 0.002024643 //LENGTH 15.490 LUMPCC 0.0001761757 DR + +*CONN +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 133.400 44.540 +*P chanx_right_out[16] O *L 0.7423 *C 140.450 36.720 +*N chanx_right_out[16]:2 *C 134.787 36.720 +*N chanx_right_out[16]:3 *C 134.780 36.778 +*N chanx_right_out[16]:4 *C 134.780 44.540 +*N chanx_right_out[16]:5 *C 133.400 44.540 +*N chanx_right_out[16]:6 *C 133.400 44.540 + +*CAP +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[16] 0.0003895537 +2 chanx_right_out[16]:2 0.0003895537 +3 chanx_right_out[16]:3 0.0004187057 +4 chanx_right_out[16]:4 0.000499626 +5 chanx_right_out[16]:5 0.0001116739 +6 chanx_right_out[16]:6 3.835434e-05 +7 chanx_right_out[16]:3 ropt_net_147:7 2.515209e-05 +8 chanx_right_out[16]:3 ropt_net_147:5 6.293577e-05 +9 chanx_right_out[16]:4 ropt_net_147:4 6.293577e-05 +10 chanx_right_out[16]:4 ropt_net_147:6 2.515209e-05 + +*RES +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +2 chanx_right_out[16]:2 chanx_right_out[16] 0.000887125 +3 chanx_right_out[16]:6 chanx_right_out[16]:5 0.0045 +4 chanx_right_out[16]:5 chanx_right_out[16]:4 0.001232143 +5 chanx_right_out[16]:4 chanx_right_out[16]:3 0.006930804 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.001421839 //LENGTH 11.100 LUMPCC 0.0002597483 DR + +*CONN +*I mem_left_track_1\/FTB_33__59:X O *L 0 *C 34.735 72.420 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 34.675 82.620 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 34.675 82.620 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 34.500 82.620 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 34.500 82.575 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 34.500 72.465 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 34.500 72.420 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 34.735 72.420 + +*CAP +0 mem_left_track_1\/FTB_33__59:X 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 5.133949e-05 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 5.676441e-05 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.000465594 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.000465594 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 6.013719e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 6.066147e-05 +8 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_0_sram[0]:10 2.011414e-05 +9 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_0_sram[0]:14 8.354712e-05 +10 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_0_sram[0]:16 1.692572e-05 +11 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_0_sram[0]:20 9.287144e-06 +12 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_0_sram[0]:11 2.011414e-05 +13 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_0_sram[0]:15 8.354712e-05 +14 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_0_sram[0]:17 1.692572e-05 +15 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_0_sram[0]:21 9.287144e-06 + +*RES +0 mem_left_track_1\/FTB_33__59:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.009026786 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size14_mem_0_ccff_tail[0] 0.00184567 //LENGTH 10.095 LUMPCC 0.0007642922 DR + +*CONN +*I mem_right_track_4\/FTB_29__55:X O *L 0 *C 102.345 52.360 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.015 53.380 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 *C 94.015 53.380 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 *C 94.300 53.380 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 *C 94.300 53.335 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 *C 94.300 52.418 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 *C 94.308 52.360 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 *C 102.113 52.360 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:8 *C 102.120 52.360 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:9 *C 102.120 52.360 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:10 *C 102.345 52.360 + +*CAP +0 mem_right_track_4\/FTB_29__55:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 4.918737e-05 +3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 5.331617e-05 +4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 7.424936e-05 +5 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 7.424936e-05 +6 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 0.0003429123 +7 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 0.0003429123 +8 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:8 3.472598e-05 +9 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:9 5.434873e-05 +10 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:10 5.34767e-05 +11 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 chanx_right_in[9]:29 5.120382e-05 +12 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 chanx_right_in[9]:24 5.120382e-05 +13 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 chanx_left_in[18]:8 0.0001072021 +14 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 chanx_left_in[18]:12 0.0001328132 +15 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 chanx_left_in[18]:12 0.0001072021 +16 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 chanx_left_in[18]:13 0.0001328132 +17 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size8_1_sram[1]:26 9.073714e-05 +18 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size8_1_sram[1]:28 1.897301e-07 +19 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size8_1_sram[1]:27 9.073714e-05 +20 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_1_sram[1]:8 1.897301e-07 + +*RES +0 mem_right_track_4\/FTB_29__55:X mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:10 0.152 +1 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:10 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:9 0.0001222826 +2 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:8 0.0045 +3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 0.00341 +4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 0.001222783 +5 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 0.0008191965 +6 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 0.00341 +7 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 0.0001548913 +8 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 0.0045 +9 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.001861762 //LENGTH 13.125 LUMPCC 0.000379256 DR + +*CONN +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.545 93.840 +*I mux_top_track_36\/mux_l2_in_0_:S I *L 0.008363 *C 69.460 96.335 +*I mem_top_track_36\/FTB_26__52:A I *L 0.001746 *C 76.360 93.840 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 76.323 93.840 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 69.460 96.220 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 69.460 96.175 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 69.460 93.885 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 69.460 93.840 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 66.583 93.840 + +*CAP +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_36\/mux_l2_in_0_:S 2.495302e-05 +2 mem_top_track_36\/FTB_26__52:A 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 0.0003349199 +4 mux_tree_tapbuf_size2_4_sram[1]:4 2.495302e-05 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.0001655818 +6 mux_tree_tapbuf_size2_4_sram[1]:6 0.0001655818 +7 mux_tree_tapbuf_size2_4_sram[1]:7 0.0005675715 +8 mux_tree_tapbuf_size2_4_sram[1]:8 0.0001969453 +9 mux_tree_tapbuf_size2_4_sram[1]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.000189628 +10 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.000189628 + +*RES +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:3 mem_top_track_36\/FTB_26__52:A 0.152 +2 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.002569197 +3 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:3 0.006127232 +5 mux_tree_tapbuf_size2_4_sram[1]:6 mux_tree_tapbuf_size2_4_sram[1]:5 0.002044643 +6 mux_tree_tapbuf_size2_4_sram[1]:4 mux_top_track_36\/mux_l2_in_0_:S 5.078125e-05 +7 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.005911041 //LENGTH 34.195 LUMPCC 0.00200068 DR + +*CONN +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.925 63.920 +*I mux_top_track_14\/mux_l1_in_1_:S I *L 0.00357 *C 51.160 58.190 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.955 58.820 +*I mux_top_track_14\/mux_l1_in_0_:S I *L 0.00357 *C 53.920 63.580 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 53.820 63.580 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 53.790 63.550 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 53.775 63.240 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 42.992 58.820 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 51.060 58.820 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 51.160 58.190 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 51.130 58.550 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 51.015 58.410 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 53.315 58.480 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 53.360 58.525 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 53.360 63.240 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 53.367 63.240 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 67.612 63.240 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 67.620 63.298 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 67.620 63.875 +*N mux_tree_tapbuf_size3_1_sram[0]:19 *C 67.620 63.920 +*N mux_tree_tapbuf_size3_1_sram[0]:20 *C 67.925 63.920 + +*CAP +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_14\/mux_l1_in_1_:S 1e-06 +2 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_14\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 3.487894e-05 +5 mux_tree_tapbuf_size3_1_sram[0]:5 4.227779e-05 +6 mux_tree_tapbuf_size3_1_sram[0]:6 7.691224e-05 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0006381973 +8 mux_tree_tapbuf_size3_1_sram[0]:8 0.0006635644 +9 mux_tree_tapbuf_size3_1_sram[0]:9 6.079001e-05 +10 mux_tree_tapbuf_size3_1_sram[0]:10 3.585761e-05 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.000220937 +12 mux_tree_tapbuf_size3_1_sram[0]:12 0.0001904221 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0002778933 +14 mux_tree_tapbuf_size3_1_sram[0]:14 0.0003125278 +15 mux_tree_tapbuf_size3_1_sram[0]:15 0.0005632655 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.0005632655 +17 mux_tree_tapbuf_size3_1_sram[0]:17 5.988431e-05 +18 mux_tree_tapbuf_size3_1_sram[0]:18 5.988431e-05 +19 mux_tree_tapbuf_size3_1_sram[0]:19 5.523673e-05 +20 mux_tree_tapbuf_size3_1_sram[0]:20 5.056512e-05 +21 mux_tree_tapbuf_size3_1_sram[0]:15 chanx_left_in[4]:26 0.0002550271 +22 mux_tree_tapbuf_size3_1_sram[0]:16 chanx_left_in[4]:25 0.0002550271 +23 mux_tree_tapbuf_size3_1_sram[0]:15 chany_top_in[4]:11 0.0007453128 +24 mux_tree_tapbuf_size3_1_sram[0]:16 chany_top_in[4]:6 0.0007453128 + +*RES +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:4 mux_top_track_14\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[0]:5 mux_tree_tapbuf_size3_1_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size3_1_sram[0]:7 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.002053572 +5 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.004209822 +7 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:6 0.0003705357 +8 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.00341 +9 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.00341 +10 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.002231717 +11 mux_tree_tapbuf_size3_1_sram[0]:19 mux_tree_tapbuf_size3_1_sram[0]:18 0.0045 +12 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.0005156249 +13 mux_tree_tapbuf_size3_1_sram[0]:20 mux_tree_tapbuf_size3_1_sram[0]:19 0.0001657609 +14 mux_tree_tapbuf_size3_1_sram[0]:9 mux_top_track_14\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size3_1_sram[0]:8 mux_tree_tapbuf_size3_1_sram[0]:7 0.007203125 +16 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.0001026786 +17 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:8 0.0003660714 +18 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0001551724 +19 mux_tree_tapbuf_size3_1_sram[0]:6 mux_tree_tapbuf_size3_1_sram[0]:5 0.00019375 + +*END + +*D_NET mux_tree_tapbuf_size3_7_sram[0] 0.001956355 //LENGTH 15.715 LUMPCC 0 DR + +*CONN +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 77.125 91.120 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 80.215 88.060 +*I mux_top_track_38\/mux_l1_in_1_:S I *L 0.00357 *C 79.480 85.680 +*I mux_top_track_38\/mux_l1_in_0_:S I *L 0.00357 *C 82.240 83.640 +*N mux_tree_tapbuf_size3_7_sram[0]:4 *C 82.203 83.640 +*N mux_tree_tapbuf_size3_7_sram[0]:5 *C 81.465 83.640 +*N mux_tree_tapbuf_size3_7_sram[0]:6 *C 81.420 83.685 +*N mux_tree_tapbuf_size3_7_sram[0]:7 *C 81.420 85.680 +*N mux_tree_tapbuf_size3_7_sram[0]:8 *C 79.480 85.680 +*N mux_tree_tapbuf_size3_7_sram[0]:9 *C 79.580 85.680 +*N mux_tree_tapbuf_size3_7_sram[0]:10 *C 80.960 85.680 +*N mux_tree_tapbuf_size3_7_sram[0]:11 *C 80.960 88.015 +*N mux_tree_tapbuf_size3_7_sram[0]:12 *C 80.915 88.060 +*N mux_tree_tapbuf_size3_7_sram[0]:13 *C 80.215 88.060 +*N mux_tree_tapbuf_size3_7_sram[0]:14 *C 77.325 88.060 +*N mux_tree_tapbuf_size3_7_sram[0]:15 *C 77.280 88.105 +*N mux_tree_tapbuf_size3_7_sram[0]:16 *C 77.280 91.075 +*N mux_tree_tapbuf_size3_7_sram[0]:17 *C 77.280 91.120 +*N mux_tree_tapbuf_size3_7_sram[0]:18 *C 77.125 91.120 + +*CAP +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_38\/mux_l1_in_1_:S 1e-06 +3 mux_top_track_38\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_7_sram[0]:4 7.820458e-05 +5 mux_tree_tapbuf_size3_7_sram[0]:5 7.820458e-05 +6 mux_tree_tapbuf_size3_7_sram[0]:6 0.0001356442 +7 mux_tree_tapbuf_size3_7_sram[0]:7 0.0001618489 +8 mux_tree_tapbuf_size3_7_sram[0]:8 2.6828e-05 +9 mux_tree_tapbuf_size3_7_sram[0]:9 0.0001048704 +10 mux_tree_tapbuf_size3_7_sram[0]:10 0.0002392849 +11 mux_tree_tapbuf_size3_7_sram[0]:11 0.0001387572 +12 mux_tree_tapbuf_size3_7_sram[0]:12 5.580576e-05 +13 mux_tree_tapbuf_size3_7_sram[0]:13 0.0002784132 +14 mux_tree_tapbuf_size3_7_sram[0]:14 0.0001900757 +15 mux_tree_tapbuf_size3_7_sram[0]:15 0.0001833734 +16 mux_tree_tapbuf_size3_7_sram[0]:16 0.0001833734 +17 mux_tree_tapbuf_size3_7_sram[0]:17 5.129477e-05 +18 mux_tree_tapbuf_size3_7_sram[0]:18 4.637594e-05 + +*RES +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_7_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_7_sram[0]:12 mux_tree_tapbuf_size3_7_sram[0]:11 0.0045 +2 mux_tree_tapbuf_size3_7_sram[0]:11 mux_tree_tapbuf_size3_7_sram[0]:10 0.002084821 +3 mux_tree_tapbuf_size3_7_sram[0]:13 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size3_7_sram[0]:13 mux_tree_tapbuf_size3_7_sram[0]:12 0.000625 +5 mux_tree_tapbuf_size3_7_sram[0]:14 mux_tree_tapbuf_size3_7_sram[0]:13 0.002580357 +6 mux_tree_tapbuf_size3_7_sram[0]:15 mux_tree_tapbuf_size3_7_sram[0]:14 0.0045 +7 mux_tree_tapbuf_size3_7_sram[0]:17 mux_tree_tapbuf_size3_7_sram[0]:16 0.0045 +8 mux_tree_tapbuf_size3_7_sram[0]:16 mux_tree_tapbuf_size3_7_sram[0]:15 0.002651786 +9 mux_tree_tapbuf_size3_7_sram[0]:18 mux_tree_tapbuf_size3_7_sram[0]:17 8.423914e-05 +10 mux_tree_tapbuf_size3_7_sram[0]:8 mux_top_track_38\/mux_l1_in_1_:S 0.152 +11 mux_tree_tapbuf_size3_7_sram[0]:9 mux_tree_tapbuf_size3_7_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size3_7_sram[0]:5 mux_tree_tapbuf_size3_7_sram[0]:4 0.0006584821 +13 mux_tree_tapbuf_size3_7_sram[0]:6 mux_tree_tapbuf_size3_7_sram[0]:5 0.0045 +14 mux_tree_tapbuf_size3_7_sram[0]:4 mux_top_track_38\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size3_7_sram[0]:10 mux_tree_tapbuf_size3_7_sram[0]:9 0.001232143 +16 mux_tree_tapbuf_size3_7_sram[0]:10 mux_tree_tapbuf_size3_7_sram[0]:7 0.0004107143 +17 mux_tree_tapbuf_size3_7_sram[0]:7 mux_tree_tapbuf_size3_7_sram[0]:6 0.00178125 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[2] 0.002135464 //LENGTH 17.825 LUMPCC 0.0001362629 DR + +*CONN +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 124.045 58.820 +*I mux_top_track_10\/mux_l3_in_0_:S I *L 0.00357 *C 120.160 61.495 +*I mem_top_track_10\/FTB_13__39:A I *L 0.001746 *C 114.540 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:3 *C 120.230 61.600 +*N mux_tree_tapbuf_size4_1_sram[2]:4 *C 120.090 61.470 +*N mux_tree_tapbuf_size4_1_sram[2]:5 *C 120.060 61.540 +*N mux_tree_tapbuf_size4_1_sram[2]:6 *C 114.578 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:7 *C 116.335 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:8 *C 116.380 58.525 +*N mux_tree_tapbuf_size4_1_sram[2]:9 *C 116.380 61.495 +*N mux_tree_tapbuf_size4_1_sram[2]:10 *C 116.425 61.540 +*N mux_tree_tapbuf_size4_1_sram[2]:11 *C 120.198 61.490 +*N mux_tree_tapbuf_size4_1_sram[2]:12 *C 120.218 61.200 +*N mux_tree_tapbuf_size4_1_sram[2]:13 *C 122.775 61.200 +*N mux_tree_tapbuf_size4_1_sram[2]:14 *C 122.820 61.155 +*N mux_tree_tapbuf_size4_1_sram[2]:15 *C 122.820 58.865 +*N mux_tree_tapbuf_size4_1_sram[2]:16 *C 122.865 58.820 +*N mux_tree_tapbuf_size4_1_sram[2]:17 *C 124.008 58.820 + +*CAP +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_10\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_10\/FTB_13__39:A 1e-06 +3 mux_tree_tapbuf_size4_1_sram[2]:3 1.533932e-05 +4 mux_tree_tapbuf_size4_1_sram[2]:4 1.293264e-05 +5 mux_tree_tapbuf_size4_1_sram[2]:5 1.81873e-05 +6 mux_tree_tapbuf_size4_1_sram[2]:6 0.0001188521 +7 mux_tree_tapbuf_size4_1_sram[2]:7 0.0001188521 +8 mux_tree_tapbuf_size4_1_sram[2]:8 0.0001920552 +9 mux_tree_tapbuf_size4_1_sram[2]:9 0.0001920552 +10 mux_tree_tapbuf_size4_1_sram[2]:10 0.0002383317 +11 mux_tree_tapbuf_size4_1_sram[2]:11 0.0002706852 +12 mux_tree_tapbuf_size4_1_sram[2]:12 0.0001801725 +13 mux_tree_tapbuf_size4_1_sram[2]:13 0.0001600134 +14 mux_tree_tapbuf_size4_1_sram[2]:14 0.0001507176 +15 mux_tree_tapbuf_size4_1_sram[2]:15 0.0001507176 +16 mux_tree_tapbuf_size4_1_sram[2]:16 8.86444e-05 +17 mux_tree_tapbuf_size4_1_sram[2]:17 8.86444e-05 +18 mux_tree_tapbuf_size4_1_sram[2]:13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.813145e-05 +19 mux_tree_tapbuf_size4_1_sram[2]:12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.813145e-05 + +*RES +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_1_sram[2]:17 0.152 +1 mux_tree_tapbuf_size4_1_sram[2]:10 mux_tree_tapbuf_size4_1_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size4_1_sram[2]:9 mux_tree_tapbuf_size4_1_sram[2]:8 0.002651786 +3 mux_tree_tapbuf_size4_1_sram[2]:7 mux_tree_tapbuf_size4_1_sram[2]:6 0.001569197 +4 mux_tree_tapbuf_size4_1_sram[2]:8 mux_tree_tapbuf_size4_1_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size4_1_sram[2]:6 mem_top_track_10\/FTB_13__39:A 0.152 +6 mux_tree_tapbuf_size4_1_sram[2]:11 mux_top_track_10\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size4_1_sram[2]:11 mux_tree_tapbuf_size4_1_sram[2]:10 0.003368304 +8 mux_tree_tapbuf_size4_1_sram[2]:11 mux_tree_tapbuf_size4_1_sram[2]:5 0.0001227679 +9 mux_tree_tapbuf_size4_1_sram[2]:13 mux_tree_tapbuf_size4_1_sram[2]:12 0.002283482 +10 mux_tree_tapbuf_size4_1_sram[2]:14 mux_tree_tapbuf_size4_1_sram[2]:13 0.0045 +11 mux_tree_tapbuf_size4_1_sram[2]:16 mux_tree_tapbuf_size4_1_sram[2]:15 0.0045 +12 mux_tree_tapbuf_size4_1_sram[2]:15 mux_tree_tapbuf_size4_1_sram[2]:14 0.002044643 +13 mux_tree_tapbuf_size4_1_sram[2]:17 mux_tree_tapbuf_size4_1_sram[2]:16 0.001020089 +14 mux_tree_tapbuf_size4_1_sram[2]:5 mux_tree_tapbuf_size4_1_sram[2]:4 3.645834e-05 +15 mux_tree_tapbuf_size4_1_sram[2]:4 mux_tree_tapbuf_size4_1_sram[2]:3 0.000125 +16 mux_tree_tapbuf_size4_1_sram[2]:12 mux_tree_tapbuf_size4_1_sram[2]:11 0.0001686047 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[2] 0.001287398 //LENGTH 9.845 LUMPCC 0.0001639237 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 67.925 91.120 +*I mem_top_track_2\/FTB_5__31:A I *L 0.001746 *C 68.540 85.680 +*I mux_top_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 66.140 88.400 +*N mux_tree_tapbuf_size7_0_sram[2]:3 *C 66.178 88.400 +*N mux_tree_tapbuf_size7_0_sram[2]:4 *C 67.620 88.400 +*N mux_tree_tapbuf_size7_0_sram[2]:5 *C 68.540 85.680 +*N mux_tree_tapbuf_size7_0_sram[2]:6 *C 68.540 85.725 +*N mux_tree_tapbuf_size7_0_sram[2]:7 *C 68.540 88.015 +*N mux_tree_tapbuf_size7_0_sram[2]:8 *C 68.495 88.060 +*N mux_tree_tapbuf_size7_0_sram[2]:9 *C 67.620 88.060 +*N mux_tree_tapbuf_size7_0_sram[2]:10 *C 67.620 88.105 +*N mux_tree_tapbuf_size7_0_sram[2]:11 *C 67.620 91.075 +*N mux_tree_tapbuf_size7_0_sram[2]:12 *C 67.620 91.120 +*N mux_tree_tapbuf_size7_0_sram[2]:13 *C 67.925 91.120 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_2\/FTB_5__31:A 1e-06 +2 mux_top_track_2\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_0_sram[2]:3 0.000107821 +4 mux_tree_tapbuf_size7_0_sram[2]:4 0.0001359542 +5 mux_tree_tapbuf_size7_0_sram[2]:5 3.007549e-05 +6 mux_tree_tapbuf_size7_0_sram[2]:6 0.000168902 +7 mux_tree_tapbuf_size7_0_sram[2]:7 0.000168902 +8 mux_tree_tapbuf_size7_0_sram[2]:8 6.341851e-05 +9 mux_tree_tapbuf_size7_0_sram[2]:9 9.155169e-05 +10 mux_tree_tapbuf_size7_0_sram[2]:10 0.0001249407 +11 mux_tree_tapbuf_size7_0_sram[2]:11 0.0001249407 +12 mux_tree_tapbuf_size7_0_sram[2]:12 5.321811e-05 +13 mux_tree_tapbuf_size7_0_sram[2]:13 5.074993e-05 +14 mux_tree_tapbuf_size7_0_sram[2]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.132606e-05 +15 mux_tree_tapbuf_size7_0_sram[2]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.132606e-05 +16 mux_tree_tapbuf_size7_0_sram[2]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 1.063579e-05 +17 mux_tree_tapbuf_size7_0_sram[2]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 1.063579e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size7_0_sram[2]:8 mux_tree_tapbuf_size7_0_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size7_0_sram[2]:7 mux_tree_tapbuf_size7_0_sram[2]:6 0.002044643 +3 mux_tree_tapbuf_size7_0_sram[2]:5 mem_top_track_2\/FTB_5__31:A 0.152 +4 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_0_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:8 0.00078125 +6 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:4 0.0003035715 +7 mux_tree_tapbuf_size7_0_sram[2]:10 mux_tree_tapbuf_size7_0_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size7_0_sram[2]:12 mux_tree_tapbuf_size7_0_sram[2]:11 0.0045 +9 mux_tree_tapbuf_size7_0_sram[2]:11 mux_tree_tapbuf_size7_0_sram[2]:10 0.002651786 +10 mux_tree_tapbuf_size7_0_sram[2]:13 mux_tree_tapbuf_size7_0_sram[2]:12 0.0001657609 +11 mux_tree_tapbuf_size7_0_sram[2]:3 mux_top_track_2\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[2]:3 0.001287946 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[2] 0.001800964 //LENGTH 15.050 LUMPCC 0.0005346469 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 98.285 26.180 +*I mux_right_track_16\/mux_l3_in_0_:S I *L 0.00357 *C 100.640 34.680 +*I mem_right_track_16\/FTB_8__34:A I *L 0.001746 *C 97.980 36.720 +*N mux_tree_tapbuf_size7_3_sram[2]:3 *C 98.017 36.720 +*N mux_tree_tapbuf_size7_3_sram[2]:4 *C 98.855 36.720 +*N mux_tree_tapbuf_size7_3_sram[2]:5 *C 98.900 36.675 +*N mux_tree_tapbuf_size7_3_sram[2]:6 *C 100.603 34.680 +*N mux_tree_tapbuf_size7_3_sram[2]:7 *C 98.945 34.680 +*N mux_tree_tapbuf_size7_3_sram[2]:8 *C 98.900 34.680 +*N mux_tree_tapbuf_size7_3_sram[2]:9 *C 98.900 26.225 +*N mux_tree_tapbuf_size7_3_sram[2]:10 *C 98.855 26.180 +*N mux_tree_tapbuf_size7_3_sram[2]:11 *C 98.323 26.180 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_16\/FTB_8__34:A 1e-06 +3 mux_tree_tapbuf_size7_3_sram[2]:3 7.82297e-05 +4 mux_tree_tapbuf_size7_3_sram[2]:4 7.82297e-05 +5 mux_tree_tapbuf_size7_3_sram[2]:5 9.047671e-05 +6 mux_tree_tapbuf_size7_3_sram[2]:6 9.15254e-05 +7 mux_tree_tapbuf_size7_3_sram[2]:7 9.15254e-05 +8 mux_tree_tapbuf_size7_3_sram[2]:8 0.0004228626 +9 mux_tree_tapbuf_size7_3_sram[2]:9 0.0003000209 +10 mux_tree_tapbuf_size7_3_sram[2]:10 5.522329e-05 +11 mux_tree_tapbuf_size7_3_sram[2]:11 5.522329e-05 +12 mux_tree_tapbuf_size7_3_sram[2]:5 chanx_right_in[8]:6 2.798882e-05 +13 mux_tree_tapbuf_size7_3_sram[2]:8 chanx_right_in[8]:6 0.0001040296 +14 mux_tree_tapbuf_size7_3_sram[2]:8 chanx_right_in[8]:21 2.798882e-05 +15 mux_tree_tapbuf_size7_3_sram[2]:9 chanx_right_in[8]:21 0.0001040296 +16 mux_tree_tapbuf_size7_3_sram[2]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.927355e-05 +17 mux_tree_tapbuf_size7_3_sram[2]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.927355e-05 +18 mux_tree_tapbuf_size7_3_sram[2]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.136157e-06 +19 mux_tree_tapbuf_size7_3_sram[2]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.389529e-05 +20 mux_tree_tapbuf_size7_3_sram[2]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.136157e-06 +21 mux_tree_tapbuf_size7_3_sram[2]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.389529e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_3_sram[2]:11 0.152 +1 mux_tree_tapbuf_size7_3_sram[2]:4 mux_tree_tapbuf_size7_3_sram[2]:3 0.0007477679 +2 mux_tree_tapbuf_size7_3_sram[2]:5 mux_tree_tapbuf_size7_3_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size7_3_sram[2]:3 mem_right_track_16\/FTB_8__34:A 0.152 +4 mux_tree_tapbuf_size7_3_sram[2]:7 mux_tree_tapbuf_size7_3_sram[2]:6 0.001479911 +5 mux_tree_tapbuf_size7_3_sram[2]:8 mux_tree_tapbuf_size7_3_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size7_3_sram[2]:8 mux_tree_tapbuf_size7_3_sram[2]:5 0.00178125 +7 mux_tree_tapbuf_size7_3_sram[2]:6 mux_right_track_16\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_3_sram[2]:10 mux_tree_tapbuf_size7_3_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size7_3_sram[2]:9 mux_tree_tapbuf_size7_3_sram[2]:8 0.007549107 +10 mux_tree_tapbuf_size7_3_sram[2]:11 mux_tree_tapbuf_size7_3_sram[2]:10 0.0004754465 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[2] 0.002110571 //LENGTH 15.535 LUMPCC 0.000288469 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 45.385 28.560 +*I mux_left_track_17\/mux_l3_in_0_:S I *L 0.00357 *C 36.900 25.160 +*I mem_left_track_17\/FTB_10__36:A I *L 0.001746 *C 44.160 31.280 +*N mux_tree_tapbuf_size7_5_sram[2]:3 *C 44.160 31.280 +*N mux_tree_tapbuf_size7_5_sram[2]:4 *C 44.160 31.235 +*N mux_tree_tapbuf_size7_5_sram[2]:5 *C 36.938 25.160 +*N mux_tree_tapbuf_size7_5_sram[2]:6 *C 44.115 25.160 +*N mux_tree_tapbuf_size7_5_sram[2]:7 *C 44.160 25.205 +*N mux_tree_tapbuf_size7_5_sram[2]:8 *C 44.160 28.560 +*N mux_tree_tapbuf_size7_5_sram[2]:9 *C 44.205 28.560 +*N mux_tree_tapbuf_size7_5_sram[2]:10 *C 45.348 28.560 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_17\/FTB_10__36:A 1e-06 +3 mux_tree_tapbuf_size7_5_sram[2]:3 3.474883e-05 +4 mux_tree_tapbuf_size7_5_sram[2]:4 0.0001627149 +5 mux_tree_tapbuf_size7_5_sram[2]:5 0.0004169215 +6 mux_tree_tapbuf_size7_5_sram[2]:6 0.0004169215 +7 mux_tree_tapbuf_size7_5_sram[2]:7 0.0001769775 +8 mux_tree_tapbuf_size7_5_sram[2]:8 0.00037547 +9 mux_tree_tapbuf_size7_5_sram[2]:9 0.0001176739 +10 mux_tree_tapbuf_size7_5_sram[2]:10 0.0001176739 +11 mux_tree_tapbuf_size7_5_sram[2]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.449258e-06 +12 mux_tree_tapbuf_size7_5_sram[2]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.491304e-06 +13 mux_tree_tapbuf_size7_5_sram[2]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.449258e-06 +14 mux_tree_tapbuf_size7_5_sram[2]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001362939 +15 mux_tree_tapbuf_size7_5_sram[2]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.491304e-06 +16 mux_tree_tapbuf_size7_5_sram[2]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001362939 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_5_sram[2]:10 0.152 +1 mux_tree_tapbuf_size7_5_sram[2]:3 mem_left_track_17\/FTB_10__36:A 0.152 +2 mux_tree_tapbuf_size7_5_sram[2]:4 mux_tree_tapbuf_size7_5_sram[2]:3 0.0045 +3 mux_tree_tapbuf_size7_5_sram[2]:9 mux_tree_tapbuf_size7_5_sram[2]:8 0.0045 +4 mux_tree_tapbuf_size7_5_sram[2]:8 mux_tree_tapbuf_size7_5_sram[2]:7 0.002995536 +5 mux_tree_tapbuf_size7_5_sram[2]:8 mux_tree_tapbuf_size7_5_sram[2]:4 0.002388393 +6 mux_tree_tapbuf_size7_5_sram[2]:10 mux_tree_tapbuf_size7_5_sram[2]:9 0.001020089 +7 mux_tree_tapbuf_size7_5_sram[2]:6 mux_tree_tapbuf_size7_5_sram[2]:5 0.006408482 +8 mux_tree_tapbuf_size7_5_sram[2]:7 mux_tree_tapbuf_size7_5_sram[2]:6 0.0045 +9 mux_tree_tapbuf_size7_5_sram[2]:5 mux_left_track_17\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_6_ccff_tail[0] 0.0006986354 //LENGTH 5.370 LUMPCC 8.026615e-05 DR + +*CONN +*I mem_left_track_25\/FTB_11__37:X O *L 0 *C 40.245 47.600 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 42.495 49.980 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 *C 42.495 49.980 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 *C 42.320 49.980 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 *C 42.320 49.935 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 *C 42.320 47.645 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 *C 42.275 47.600 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 *C 40.282 47.600 + +*CAP +0 mem_left_track_25\/FTB_11__37:X 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 4.732948e-05 +3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 5.14797e-05 +4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.0001479093 +5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0001479093 +6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 0.0001108708 +7 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 0.0001108708 +8 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 chanx_right_in[18]:17 4.013308e-05 +9 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 chanx_right_in[18]:18 4.013308e-05 + +*RES +0 mem_left_track_25\/FTB_11__37:X mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 0.001779018 +2 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[3] 0.001170036 //LENGTH 9.140 LUMPCC 0.000157552 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 18.970 65.960 +*I mem_left_track_3\/FTB_3__29:A I *L 0.001746 *C 17.480 63.920 +*I mux_left_track_3\/mux_l4_in_0_:S I *L 0.00357 *C 14.840 63.240 +*N mux_tree_tapbuf_size8_2_sram[3]:3 *C 14.878 63.240 +*N mux_tree_tapbuf_size8_2_sram[3]:4 *C 17.020 63.240 +*N mux_tree_tapbuf_size8_2_sram[3]:5 *C 17.020 64.260 +*N mux_tree_tapbuf_size8_2_sram[3]:6 *C 17.445 64.260 +*N mux_tree_tapbuf_size8_2_sram[3]:7 *C 17.480 63.920 +*N mux_tree_tapbuf_size8_2_sram[3]:8 *C 17.895 63.920 +*N mux_tree_tapbuf_size8_2_sram[3]:9 *C 17.940 63.965 +*N mux_tree_tapbuf_size8_2_sram[3]:10 *C 17.940 65.915 +*N mux_tree_tapbuf_size8_2_sram[3]:11 *C 17.985 65.960 +*N mux_tree_tapbuf_size8_2_sram[3]:12 *C 18.933 65.960 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_track_3\/FTB_3__29:A 1e-06 +2 mux_left_track_3\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_2_sram[3]:3 0.0001620408 +4 mux_tree_tapbuf_size8_2_sram[3]:4 0.0002121901 +5 mux_tree_tapbuf_size8_2_sram[3]:5 7.153274e-05 +6 mux_tree_tapbuf_size8_2_sram[3]:6 5.608771e-05 +7 mux_tree_tapbuf_size8_2_sram[3]:7 7.861909e-05 +8 mux_tree_tapbuf_size8_2_sram[3]:8 4.391489e-05 +9 mux_tree_tapbuf_size8_2_sram[3]:9 0.0001077656 +10 mux_tree_tapbuf_size8_2_sram[3]:10 0.0001077656 +11 mux_tree_tapbuf_size8_2_sram[3]:11 8.478403e-05 +12 mux_tree_tapbuf_size8_2_sram[3]:12 8.478403e-05 +13 mux_tree_tapbuf_size8_2_sram[3]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 3.643595e-05 +14 mux_tree_tapbuf_size8_2_sram[3]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.470052e-06 +15 mux_tree_tapbuf_size8_2_sram[3]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.643595e-05 +16 mux_tree_tapbuf_size8_2_sram[3]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.470052e-06 +17 mux_tree_tapbuf_size8_2_sram[3]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.628672e-05 +18 mux_tree_tapbuf_size8_2_sram[3]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.786091e-05 +19 mux_tree_tapbuf_size8_2_sram[3]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.358327e-05 +20 mux_tree_tapbuf_size8_2_sram[3]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.200908e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_2_sram[3]:12 0.152 +1 mux_tree_tapbuf_size8_2_sram[3]:12 mux_tree_tapbuf_size8_2_sram[3]:11 0.0008459822 +2 mux_tree_tapbuf_size8_2_sram[3]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.0045 +3 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.001741072 +4 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size8_2_sram[3]:7 0.0003705358 +5 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:8 0.0045 +6 mux_tree_tapbuf_size8_2_sram[3]:7 mem_left_track_3\/FTB_3__29:A 0.152 +7 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size8_2_sram[3]:6 0.0002297297 +8 mux_tree_tapbuf_size8_2_sram[3]:3 mux_left_track_3\/mux_l4_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_2_sram[3]:4 mux_tree_tapbuf_size8_2_sram[3]:3 0.001912947 +10 mux_tree_tapbuf_size8_2_sram[3]:5 mux_tree_tapbuf_size8_2_sram[3]:4 0.0009107143 +11 mux_tree_tapbuf_size8_2_sram[3]:6 mux_tree_tapbuf_size8_2_sram[3]:5 0.0003794643 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[0] 0.003912864 //LENGTH 28.670 LUMPCC 0.000106022 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 94.145 82.960 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 100.915 77.180 +*I mux_right_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 101.200 74.630 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 86.840 79.560 +*N mux_tree_tapbuf_size9_0_sram[0]:4 *C 86.877 79.560 +*N mux_tree_tapbuf_size9_0_sram[0]:5 *C 94.255 79.560 +*N mux_tree_tapbuf_size9_0_sram[0]:6 *C 94.300 79.605 +*N mux_tree_tapbuf_size9_0_sram[0]:7 *C 101.200 74.630 +*N mux_tree_tapbuf_size9_0_sram[0]:8 *C 101.200 75.140 +*N mux_tree_tapbuf_size9_0_sram[0]:9 *C 100.915 77.180 +*N mux_tree_tapbuf_size9_0_sram[0]:10 *C 100.740 77.180 +*N mux_tree_tapbuf_size9_0_sram[0]:11 *C 100.740 77.135 +*N mux_tree_tapbuf_size9_0_sram[0]:12 *C 100.740 75.185 +*N mux_tree_tapbuf_size9_0_sram[0]:13 *C 100.740 75.140 +*N mux_tree_tapbuf_size9_0_sram[0]:14 *C 98.025 75.140 +*N mux_tree_tapbuf_size9_0_sram[0]:15 *C 97.980 75.185 +*N mux_tree_tapbuf_size9_0_sram[0]:16 *C 97.980 80.875 +*N mux_tree_tapbuf_size9_0_sram[0]:17 *C 97.935 80.920 +*N mux_tree_tapbuf_size9_0_sram[0]:18 *C 94.345 80.920 +*N mux_tree_tapbuf_size9_0_sram[0]:19 *C 94.300 80.920 +*N mux_tree_tapbuf_size9_0_sram[0]:20 *C 94.300 82.915 +*N mux_tree_tapbuf_size9_0_sram[0]:21 *C 94.300 82.960 +*N mux_tree_tapbuf_size9_0_sram[0]:22 *C 94.145 82.960 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size9_0_sram[0]:4 0.0005104194 +5 mux_tree_tapbuf_size9_0_sram[0]:5 0.0005104194 +6 mux_tree_tapbuf_size9_0_sram[0]:6 8.309896e-05 +7 mux_tree_tapbuf_size9_0_sram[0]:7 6.550366e-05 +8 mux_tree_tapbuf_size9_0_sram[0]:8 6.736467e-05 +9 mux_tree_tapbuf_size9_0_sram[0]:9 5.285972e-05 +10 mux_tree_tapbuf_size9_0_sram[0]:10 5.502771e-05 +11 mux_tree_tapbuf_size9_0_sram[0]:11 0.0001320918 +12 mux_tree_tapbuf_size9_0_sram[0]:12 0.0001320918 +13 mux_tree_tapbuf_size9_0_sram[0]:13 0.0002376137 +14 mux_tree_tapbuf_size9_0_sram[0]:14 0.0001844982 +15 mux_tree_tapbuf_size9_0_sram[0]:15 0.0003414411 +16 mux_tree_tapbuf_size9_0_sram[0]:16 0.0003414411 +17 mux_tree_tapbuf_size9_0_sram[0]:17 0.0002940623 +18 mux_tree_tapbuf_size9_0_sram[0]:18 0.0002940623 +19 mux_tree_tapbuf_size9_0_sram[0]:19 0.0002516434 +20 mux_tree_tapbuf_size9_0_sram[0]:20 0.0001365723 +21 mux_tree_tapbuf_size9_0_sram[0]:21 5.852064e-05 +22 mux_tree_tapbuf_size9_0_sram[0]:22 5.411017e-05 +23 mux_tree_tapbuf_size9_0_sram[0]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.506243e-06 +24 mux_tree_tapbuf_size9_0_sram[0]:18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.506243e-06 +25 mux_tree_tapbuf_size9_0_sram[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.150474e-05 +26 mux_tree_tapbuf_size9_0_sram[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.150474e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size9_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size9_0_sram[0]:7 mux_right_track_0\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size9_0_sram[0]:14 mux_tree_tapbuf_size9_0_sram[0]:13 0.002424107 +3 mux_tree_tapbuf_size9_0_sram[0]:15 mux_tree_tapbuf_size9_0_sram[0]:14 0.0045 +4 mux_tree_tapbuf_size9_0_sram[0]:17 mux_tree_tapbuf_size9_0_sram[0]:16 0.0045 +5 mux_tree_tapbuf_size9_0_sram[0]:16 mux_tree_tapbuf_size9_0_sram[0]:15 0.005080357 +6 mux_tree_tapbuf_size9_0_sram[0]:18 mux_tree_tapbuf_size9_0_sram[0]:17 0.003205357 +7 mux_tree_tapbuf_size9_0_sram[0]:19 mux_tree_tapbuf_size9_0_sram[0]:18 0.0045 +8 mux_tree_tapbuf_size9_0_sram[0]:19 mux_tree_tapbuf_size9_0_sram[0]:6 0.001174107 +9 mux_tree_tapbuf_size9_0_sram[0]:13 mux_tree_tapbuf_size9_0_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size9_0_sram[0]:13 mux_tree_tapbuf_size9_0_sram[0]:8 0.0004107143 +11 mux_tree_tapbuf_size9_0_sram[0]:12 mux_tree_tapbuf_size9_0_sram[0]:11 0.001741072 +12 mux_tree_tapbuf_size9_0_sram[0]:10 mux_tree_tapbuf_size9_0_sram[0]:9 9.51087e-05 +13 mux_tree_tapbuf_size9_0_sram[0]:11 mux_tree_tapbuf_size9_0_sram[0]:10 0.0045 +14 mux_tree_tapbuf_size9_0_sram[0]:9 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size9_0_sram[0]:21 mux_tree_tapbuf_size9_0_sram[0]:20 0.0045 +16 mux_tree_tapbuf_size9_0_sram[0]:20 mux_tree_tapbuf_size9_0_sram[0]:19 0.00178125 +17 mux_tree_tapbuf_size9_0_sram[0]:22 mux_tree_tapbuf_size9_0_sram[0]:21 8.423914e-05 +18 mux_tree_tapbuf_size9_0_sram[0]:5 mux_tree_tapbuf_size9_0_sram[0]:4 0.006587054 +19 mux_tree_tapbuf_size9_0_sram[0]:6 mux_tree_tapbuf_size9_0_sram[0]:5 0.0045 +20 mux_tree_tapbuf_size9_0_sram[0]:4 mux_right_track_0\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size9_0_sram[0]:8 mux_tree_tapbuf_size9_0_sram[0]:7 0.0004553572 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001278184 //LENGTH 9.560 LUMPCC 0.0001934692 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_1_:X O *L 0 *C 49.965 72.080 +*I mux_top_track_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 55.835 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 55.835 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 55.660 74.800 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 50.185 74.800 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 50.140 74.755 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 50.140 72.125 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 50.140 72.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 49.965 72.080 + +*CAP +0 mux_top_track_0\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.531701e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003501754 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003242283 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001336032 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001336032 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.38407e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 4.194746e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_0_sram[2]:16 3.85539e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_0_sram[2]:17 1.080254e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_0_sram[2]:14 5.534608e-06 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_0_sram[2]:15 2.811581e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size8_0_sram[2]:13 1.372773e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size8_0_sram[2]:11 5.534608e-06 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size8_0_sram[2]:14 2.811581e-05 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_tree_tapbuf_size8_0_sram[2]:12 1.372773e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_0_sram[2]:8 3.85539e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_0_sram[2]:16 1.080254e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.004888393 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.002348215 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 9.51087e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001603358 //LENGTH 11.885 LUMPCC 0.0002946586 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_0_:X O *L 0 *C 19.035 69.020 +*I mux_left_track_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 13.800 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 13.838 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 15.180 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 15.180 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 17.435 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 17.480 64.645 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 17.480 68.975 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 17.525 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 18.998 69.020 + +*CAP +0 mux_left_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001081181 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001704821 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002211794 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001588154 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002528145 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002528145 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 7.123753e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 7.123753e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size8_2_sram[2]:11 6.855332e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size8_2_sram[2]:10 6.855332e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size8_2_sram[3]:10 3.643595e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_2_sram[3]:6 2.200908e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size8_2_sram[3]:8 2.470052e-06 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size8_2_sram[3]:9 3.643595e-05 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size8_2_sram[3]:3 1.628672e-05 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size8_2_sram[3]:4 1.786091e-05 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_2_sram[3]:5 2.358327e-05 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size8_2_sram[3]:7 2.470052e-06 + +*RES +0 mux_left_track_3\/mux_l3_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.001314732 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.003866072 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002013393 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_3\/mux_l4_in_0_:A1 0.152 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001198661 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0009107144 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001048617 //LENGTH 9.360 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_3_:X O *L 0 *C 64.575 76.840 +*I mux_top_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 63.195 82.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 63.158 82.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 62.605 82.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 62.560 82.575 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 62.560 76.885 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 62.605 76.840 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 64.538 76.840 + +*CAP +0 mux_top_track_2\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.453044e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.453044e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003169665 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003169665 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001518115 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001518115 + +*RES +0 mux_top_track_2\/mux_l1_in_3_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_2\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004933036 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005080357 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001725446 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003369709 //LENGTH 2.595 LUMPCC 0 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_3_:X O *L 0 *C 86.305 44.200 +*I mux_top_track_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 88.610 44.200 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 88.573 44.200 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 86.343 44.200 + +*CAP +0 mux_top_track_6\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001674854 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001674854 + +*RES +0 mux_top_track_6\/mux_l1_in_3_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_6\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001991072 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002895292 //LENGTH 23.200 LUMPCC 0.0008613656 DR + +*CONN +*I mux_right_track_16\/mux_l3_in_0_:X O *L 0 *C 101.485 33.660 +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 124.470 33.810 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 124.433 33.712 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 101.523 33.660 + +*CAP +0 mux_right_track_16\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001015963 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.001015963 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[5]:18 8.349986e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[5]:17 8.349986e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[8]:10 6.40284e-06 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[8]:13 2.610156e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[8]:18 1.670171e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[8]:20 8.645884e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[8]:9 6.40284e-06 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[8]:12 2.610156e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[8]:14 1.670171e-05 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[8]:19 8.645884e-05 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.000211518 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.000211518 + +*RES +0 mux_right_track_16\/mux_l3_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.02045536 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0] 0.003140273 //LENGTH 28.225 LUMPCC 0.00113148 DR + +*CONN +*I mux_left_track_17\/mux_l3_in_0_:X O *L 0 *C 36.055 25.160 +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 13.955 22.950 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 13.993 23.058 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 27.555 23.120 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 27.600 23.075 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 27.600 21.818 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 27.608 21.760 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 35.873 21.760 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 35.880 21.818 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 35.880 25.115 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 35.880 25.160 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 36.055 25.160 + +*CAP +0 mux_left_track_17\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005035805 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0005035805 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.975713e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.975713e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001882096 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001882096 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001749311 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001749311 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.792631e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.590989e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[5]:13 0.0001876018 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_right_in[5]:11 3.077105e-06 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[5]:12 0.0001876018 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_right_in[5]:9 0.0002591126 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_right_in[5]:10 3.077105e-06 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_right_in[5]:8 0.0002591126 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_left_in[17]:19 0.0001159484 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_left_in[17] 0.0001159484 + +*RES +0 mux_left_track_17\/mux_l3_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 9.51087e-05 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.002944197 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.00129485 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001122768 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.01210938 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001086993 //LENGTH 8.365 LUMPCC 0.0001188395 DR + +*CONN +*I mux_top_track_10\/mux_l2_in_0_:X O *L 0 *C 123.455 56.440 +*I mux_top_track_10\/mux_l3_in_0_:A1 I *L 0.00198 *C 120.885 61.540 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 120.885 61.540 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 120.980 61.495 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 120.980 56.498 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 120.988 56.440 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 123.273 56.440 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 123.280 56.440 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 123.280 56.440 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 123.455 56.440 + +*CAP +0 mux_top_track_10\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_10\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.916391e-05 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002393965 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002393965 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001451909 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001451909 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.567024e-05 +8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 6.402233e-05 +9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.812232e-05 +10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_1_sram[1]:7 3.01669e-05 +11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_1_sram[1]:10 2.925284e-05 +12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_1_sram[1]:10 3.01669e-05 +13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_1_sram[1]:13 2.925284e-05 + +*RES +0 mux_top_track_10\/mux_l2_in_0_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_10\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.004462054 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00341 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003579833 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.51087e-05 + +*END + +*D_NET mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00724906 //LENGTH 54.620 LUMPCC 0.002926372 DR + +*CONN +*I mux_top_track_18\/mux_l2_in_0_:X O *L 0 *C 63.765 45.560 +*I mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 63.670 99.110 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.670 99.110 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 63.940 99.280 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 63.940 99.235 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 63.940 45.605 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 63.940 45.560 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 63.765 45.560 + +*CAP +0 mux_top_track_18\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.340674e-05 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.495777e-05 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002047899 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002047899 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.680032e-05 +7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.972473e-05 +8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[13] 0.0002368757 +9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[13]:15 0.0002368757 +10 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_34_[0]:23 9.774401e-07 +11 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_34_[0]:27 0.0004106623 +12 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_34_[0]:22 9.774401e-07 +13 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_34_[0]:26 0.0004106623 +14 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_36_[0]:14 4.558479e-06 +15 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_36_[0]:20 0.0001994914 +16 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_36_[0]:21 0.0002998108 +17 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_36_[0]:13 4.558479e-06 +18 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_36_[0]:17 0.0001994914 +19 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_36_[0]:20 0.0002998108 +20 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002695756 +21 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002695756 +22 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.123434e-05 +23 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.123434e-05 + +*RES +0 mux_top_track_18\/mux_l2_in_0_:X mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001467391 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.04788393 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001577755 //LENGTH 12.635 LUMPCC 0.0003371106 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_0_:X O *L 0 *C 36.165 88.740 +*I mux_top_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 40.580 96.220 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 40.543 96.220 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.385 96.220 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.340 96.175 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.340 88.785 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 36.340 88.740 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 36.165 88.740 + +*CAP +0 mux_top_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001842 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001842001 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003750077 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003750077 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.036349e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.986507e-05 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_2_sram[1]:3 7.78742e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_2_sram[1]:9 5.753697e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_2_sram[1]:8 5.753697e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_2_sram[1]:9 7.78742e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_2_sram[1]:7 2.488624e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_2_sram[1]:10 8.257894e-06 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_2_sram[1]:6 2.488624e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_2_sram[1]:11 8.257894e-06 + +*RES +0 mux_top_track_32\/mux_l1_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003712054 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006598215 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004467625 //LENGTH 2.710 LUMPCC 8.550219e-05 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_1_:X O *L 0 *C 104.245 74.800 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 106.435 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 106.435 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 106.260 74.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 104.282 74.800 + +*CAP +0 mux_right_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.741471e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001640741 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001377715 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.275109e-05 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.275109e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001765625 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001442062 //LENGTH 11.975 LUMPCC 0.0002355311 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_0_:X O *L 0 *C 95.045 90.780 +*I mux_right_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 100.840 85.340 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 100.803 85.340 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 95.265 85.340 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 95.220 85.385 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 95.220 90.735 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 95.220 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 95.045 90.780 + +*CAP +0 mux_right_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002744083 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002744083 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002734583 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002734583 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.430042e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.449713e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size9_1_sram[2]:6 4.242936e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size9_1_sram[2]:11 4.203638e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size9_1_sram[2]:17 7.962085e-06 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size9_1_sram[2]:11 4.242936e-05 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size9_1_sram[2]:16 7.962085e-06 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size9_1_sram[2]:17 4.203638e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size9_1_sram[2]:14 2.533771e-05 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size9_1_sram[2]:15 2.533771e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004944196 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000944882 //LENGTH 7.870 LUMPCC 0.0001473467 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_1_:X O *L 0 *C 100.455 65.960 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 102.295 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 102.258 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 101.245 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 101.200 60.905 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 101.200 65.915 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 101.155 65.960 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 100.493 65.960 + +*CAP +0 mux_right_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.49703e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.49703e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002552168 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002552168 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.758052e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.758052e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.155015e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.212322e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.155015e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.212322e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915179 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000904018 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0009850702 //LENGTH 7.570 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_3_:X O *L 0 *C 12.245 49.565 +*I mux_left_track_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 13.975 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 13.975 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 13.800 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 13.800 44.585 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 13.800 49.595 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 13.755 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 12.283 49.625 + +*CAP +0 mux_left_track_5\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.414943e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 5.795333e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0003019146 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0003019146 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0001335691 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0001335691 + +*RES +0 mux_left_track_5\/mux_l2_in_3_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_5\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 9.510869e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.004473215 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0005765918 //LENGTH 3.710 LUMPCC 0.0002104325 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_1_:X O *L 0 *C 19.955 49.980 +*I mux_left_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 18.690 48.280 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 18.690 48.280 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 18.860 48.280 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 18.860 48.325 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 18.860 49.935 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 18.905 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 19.918 49.980 + +*CAP +0 mux_left_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.513021e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.788428e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.256654e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.256654e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.300589e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.300589e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 left_top_grid_pin_48_[0]:12 5.0123e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 left_top_grid_pin_48_[0]:15 5.0123e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size14_1_sram[1]:11 4.385096e-06 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size14_1_sram[1]:13 5.070815e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size14_1_sram[1]:12 4.385096e-06 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size14_1_sram[1]:14 5.070815e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0014375 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002542474 //LENGTH 20.510 LUMPCC 0.0005920191 DR + +*CONN +*I mux_left_track_33\/mux_l3_in_0_:X O *L 0 *C 7.995 53.380 +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.250 36.885 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 5.250 36.885 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 5.060 36.720 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 5.060 36.765 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 5.060 53.335 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 5.105 53.380 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 7.958 53.380 + +*CAP +0 mux_left_track_33\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.529451e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.368015e-05 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0007836624 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0007836624 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001360775 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001360775 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 left_top_grid_pin_47_[0]:17 0.0001183882 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 left_top_grid_pin_47_[0]:18 0.0001183882 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size14_1_sram[0]:33 1.571694e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size14_1_sram[0]:35 9.212501e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size14_1_sram[0]:34 1.571694e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size14_1_sram[0]:36 9.212501e-05 +14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 ropt_net_145:4 6.977945e-05 +15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 ropt_net_145:5 6.977945e-05 + +*RES +0 mux_left_track_33\/mux_l3_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.002546875 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01479464 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.967393e-05 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ropt_net_150 0.001948386 //LENGTH 13.990 LUMPCC 0.0004990026 DR + +*CONN +*I FTB_9__8:X O *L 0 *C 10.580 67.320 +*I ropt_mt_inst_773:A I *L 0.001766 *C 5.980 69.360 +*N ropt_net_150:2 *C 5.980 69.360 +*N ropt_net_150:3 *C 5.980 69.020 +*N ropt_net_150:4 *C 3.220 69.020 +*N ropt_net_150:5 *C 3.220 69.360 +*N ropt_net_150:6 *C 3.220 69.315 +*N ropt_net_150:7 *C 3.220 67.365 +*N ropt_net_150:8 *C 3.265 67.320 +*N ropt_net_150:9 *C 10.543 67.320 + +*CAP +0 FTB_9__8:X 1e-06 +1 ropt_mt_inst_773:A 1e-06 +2 ropt_net_150:2 6.407798e-05 +3 ropt_net_150:3 0.0001543585 +4 ropt_net_150:4 0.0001523626 +5 ropt_net_150:5 6.372292e-05 +6 ropt_net_150:6 6.795004e-05 +7 ropt_net_150:7 6.795004e-05 +8 ropt_net_150:8 0.000438481 +9 ropt_net_150:9 0.000438481 +10 ropt_net_150:6 chanx_left_out[1]:4 5.749372e-05 +11 ropt_net_150:7 chanx_left_out[1]:3 5.749372e-05 +12 ropt_net_150:8 ropt_net_153:2 5.045429e-05 +13 ropt_net_150:8 ropt_net_153:5 2.363846e-05 +14 ropt_net_150:9 ropt_net_153:3 5.045429e-05 +15 ropt_net_150:9 ropt_net_153:6 2.363846e-05 +16 ropt_net_150:6 chanx_left_out[13]:4 1.140438e-05 +17 ropt_net_150:7 chanx_left_out[13]:3 1.140438e-05 +18 ropt_net_150:4 chanx_left_out[13]:5 0.0001065104 +19 ropt_net_150:3 chanx_left_out[13]:6 0.0001065104 + +*RES +0 FTB_9__8:X ropt_net_150:9 0.152 +1 ropt_net_150:2 ropt_mt_inst_773:A 0.152 +2 ropt_net_150:5 ropt_net_150:4 0.0003035715 +3 ropt_net_150:6 ropt_net_150:5 0.0045 +4 ropt_net_150:8 ropt_net_150:7 0.0045 +5 ropt_net_150:7 ropt_net_150:6 0.001741072 +6 ropt_net_150:9 ropt_net_150:8 0.006497769 +7 ropt_net_150:4 ropt_net_150:3 0.002464286 +8 ropt_net_150:3 ropt_net_150:2 0.0003035715 + +*END + +*D_NET ropt_net_155 0.001349087 //LENGTH 10.015 LUMPCC 0.0001566679 DR + +*CONN +*I ropt_mt_inst_758:X O *L 0 *C 134.055 27.880 +*I ropt_mt_inst_781:A I *L 0.001767 *C 130.180 25.840 +*N ropt_net_155:2 *C 130.143 25.840 +*N ropt_net_155:3 *C 129.765 25.840 +*N ropt_net_155:4 *C 129.720 25.795 +*N ropt_net_155:5 *C 129.720 25.205 +*N ropt_net_155:6 *C 129.765 25.160 +*N ropt_net_155:7 *C 134.275 25.160 +*N ropt_net_155:8 *C 134.320 25.205 +*N ropt_net_155:9 *C 134.320 27.835 +*N ropt_net_155:10 *C 134.320 27.880 +*N ropt_net_155:11 *C 134.055 27.880 + +*CAP +0 ropt_mt_inst_758:X 1e-06 +1 ropt_mt_inst_781:A 1e-06 +2 ropt_net_155:2 4.258742e-05 +3 ropt_net_155:3 4.258742e-05 +4 ropt_net_155:4 4.40327e-05 +5 ropt_net_155:5 4.40327e-05 +6 ropt_net_155:6 0.0003202722 +7 ropt_net_155:7 0.0003202722 +8 ropt_net_155:8 0.000123995 +9 ropt_net_155:9 0.000123995 +10 ropt_net_155:10 6.045719e-05 +11 ropt_net_155:11 6.818737e-05 +12 ropt_net_155:9 ropt_net_144:5 7.833396e-05 +13 ropt_net_155:8 ropt_net_144:4 7.833396e-05 + +*RES +0 ropt_mt_inst_758:X ropt_net_155:11 0.152 +1 ropt_net_155:11 ropt_net_155:10 0.0001440218 +2 ropt_net_155:10 ropt_net_155:9 0.0045 +3 ropt_net_155:9 ropt_net_155:8 0.002348214 +4 ropt_net_155:7 ropt_net_155:6 0.004026786 +5 ropt_net_155:8 ropt_net_155:7 0.0045 +6 ropt_net_155:6 ropt_net_155:5 0.0045 +7 ropt_net_155:5 ropt_net_155:4 0.0005267857 +8 ropt_net_155:3 ropt_net_155:2 0.0003370536 +9 ropt_net_155:4 ropt_net_155:3 0.0045 +10 ropt_net_155:2 ropt_mt_inst_781:A 0.152 + +*END + +*D_NET chanx_left_out[3] 0.002377966 //LENGTH 15.230 LUMPCC 0.000105316 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 4.140 64.600 +*P chanx_left_out[3] O *L 0.7423 *C 1.305 59.840 +*N chanx_left_out[3]:2 *C 4.600 59.840 +*N chanx_left_out[3]:3 *C 4.600 61.200 +*N chanx_left_out[3]:4 *C 5.973 61.200 +*N chanx_left_out[3]:5 *C 5.980 61.258 +*N chanx_left_out[3]:6 *C 5.980 63.863 +*N chanx_left_out[3]:7 *C 5.973 63.920 +*N chanx_left_out[3]:8 *C 3.228 63.920 +*N chanx_left_out[3]:9 *C 3.220 63.978 +*N chanx_left_out[3]:10 *C 3.220 64.555 +*N chanx_left_out[3]:11 *C 3.265 64.600 +*N chanx_left_out[3]:12 *C 4.103 64.600 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 chanx_left_out[3] 0.0002739147 +2 chanx_left_out[3]:2 0.0003851181 +3 chanx_left_out[3]:3 0.0003263435 +4 chanx_left_out[3]:4 0.0002151402 +5 chanx_left_out[3]:5 0.000153429 +6 chanx_left_out[3]:6 0.000153429 +7 chanx_left_out[3]:7 0.0002448536 +8 chanx_left_out[3]:8 0.0002448536 +9 chanx_left_out[3]:9 5.976894e-05 +10 chanx_left_out[3]:10 5.976894e-05 +11 chanx_left_out[3]:11 7.751526e-05 +12 chanx_left_out[3]:12 7.751526e-05 +13 chanx_left_out[3]:6 ropt_net_153:6 5.265798e-05 +14 chanx_left_out[3]:5 ropt_net_153:7 5.265798e-05 + +*RES +0 ropt_mt_inst_788:X chanx_left_out[3]:12 0.152 +1 chanx_left_out[3]:12 chanx_left_out[3]:11 0.0007477679 +2 chanx_left_out[3]:11 chanx_left_out[3]:10 0.0045 +3 chanx_left_out[3]:10 chanx_left_out[3]:9 0.000515625 +4 chanx_left_out[3]:9 chanx_left_out[3]:8 0.00341 +5 chanx_left_out[3]:8 chanx_left_out[3]:7 0.00043005 +6 chanx_left_out[3]:6 chanx_left_out[3]:5 0.002325893 +7 chanx_left_out[3]:7 chanx_left_out[3]:6 0.00341 +8 chanx_left_out[3]:5 chanx_left_out[3]:4 0.00341 +9 chanx_left_out[3]:4 chanx_left_out[3]:3 0.000215025 +10 chanx_left_out[3]:2 chanx_left_out[3] 0.0005162167 +11 chanx_left_out[3]:3 chanx_left_out[3]:2 0.0002130667 + +*END + +*D_NET chany_top_out[13] 0.0004143719 //LENGTH 3.565 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 65.320 99.960 +*P chany_top_out[13] O *L 0.7423 *C 64.400 102.035 +*N chany_top_out[13]:2 *C 64.860 102.000 +*N chany_top_out[13]:3 *C 64.860 100.005 +*N chany_top_out[13]:4 *C 64.905 99.960 +*N chany_top_out[13]:5 *C 65.282 99.960 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 chany_top_out[13] 3.127372e-05 +2 chany_top_out[13]:2 0.0001560501 +3 chany_top_out[13]:3 0.0001247764 +4 chany_top_out[13]:4 5.063585e-05 +5 chany_top_out[13]:5 5.063585e-05 + +*RES +0 ropt_mt_inst_792:X chany_top_out[13]:5 0.152 +1 chany_top_out[13]:5 chany_top_out[13]:4 0.0003370536 +2 chany_top_out[13]:4 chany_top_out[13]:3 0.0045 +3 chany_top_out[13]:3 chany_top_out[13]:2 0.00178125 +4 chany_top_out[13]:2 chany_top_out[13] 0.0004107143 + +*END + +*D_NET ropt_net_137 0.0009933048 //LENGTH 8.260 LUMPCC 0.0002568076 DR + +*CONN +*I BUFT_P_97:X O *L 0 *C 129.720 53.040 +*I ropt_mt_inst_760:A I *L 0.001766 *C 134.780 53.040 +*N ropt_net_137:2 *C 134.780 53.040 +*N ropt_net_137:3 *C 134.780 53.380 +*N ropt_net_137:4 *C 128.800 53.380 +*N ropt_net_137:5 *C 128.800 53.040 +*N ropt_net_137:6 *C 129.683 53.040 + +*CAP +0 BUFT_P_97:X 1e-06 +1 ropt_mt_inst_760:A 1e-06 +2 ropt_net_137:2 6.002716e-05 +3 ropt_net_137:3 0.0003279796 +4 ropt_net_137:4 0.000322848 +5 ropt_net_137:5 2.364243e-05 +6 ropt_net_137:6 1e-09 +7 ropt_net_137:6 chanx_left_in[16]:15 2.853094e-05 +8 ropt_net_137:2 chanx_left_in[16]:15 4.307264e-07 +9 ropt_net_137:5 chanx_left_in[16]:16 2.853094e-05 +10 ropt_net_137:4 chanx_left_in[16]:14 6.20467e-05 +11 ropt_net_137:4 chanx_left_in[16]:16 3.739543e-05 +12 ropt_net_137:3 chanx_left_in[16]:13 6.20467e-05 +13 ropt_net_137:3 chanx_left_in[16]:14 4.307264e-07 +14 ropt_net_137:3 chanx_left_in[16]:15 3.739543e-05 + +*RES +0 BUFT_P_97:X ropt_net_137:6 0.152 +1 ropt_net_137:6 ropt_net_137:5 0.0007879465 +2 ropt_net_137:2 ropt_mt_inst_760:A 0.152 +3 ropt_net_137:5 ropt_net_137:4 0.0003035715 +4 ropt_net_137:4 ropt_net_137:3 0.005339286 +5 ropt_net_137:3 ropt_net_137:2 0.0003035715 + +*END + +*D_NET chanx_left_in[4] 0.0324334 //LENGTH 210.615 LUMPCC 0.01128368 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 62.560 +*I FTB_16__15:A I *L 0.001776 *C 131.560 55.760 +*I mux_right_track_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 91.255 80.580 +*I mux_top_track_2\/mux_l1_in_3_:A1 I *L 0.00198 *C 66.145 77.860 +*N chanx_left_in[4]:4 *C 66.183 77.860 +*N chanx_left_in[4]:5 *C 74.015 77.860 +*N chanx_left_in[4]:6 *C 74.060 77.905 +*N chanx_left_in[4]:7 *C 74.060 80.875 +*N chanx_left_in[4]:8 *C 74.105 80.920 +*N chanx_left_in[4]:9 *C 91.080 80.920 +*N chanx_left_in[4]:10 *C 91.255 80.580 +*N chanx_left_in[4]:11 *C 91.080 80.580 +*N chanx_left_in[4]:12 *C 131.597 55.760 +*N chanx_left_in[4]:13 *C 132.895 55.760 +*N chanx_left_in[4]:14 *C 132.940 55.805 +*N chanx_left_in[4]:15 *C 132.940 59.103 +*N chanx_left_in[4]:16 *C 132.933 59.160 +*N chanx_left_in[4]:17 *C 107.660 59.160 +*N chanx_left_in[4]:18 *C 107.640 59.168 +*N chanx_left_in[4]:19 *C 107.640 80.913 +*N chanx_left_in[4]:20 *C 107.620 80.920 +*N chanx_left_in[4]:21 *C 91.093 80.920 +*N chanx_left_in[4]:22 *C 91.088 80.585 +*N chanx_left_in[4]:23 *C 91.080 80.580 +*N chanx_left_in[4]:24 *C 91.080 61.938 +*N chanx_left_in[4]:25 *C 91.073 61.880 +*N chanx_left_in[4]:26 *C 52.610 61.880 +*N chanx_left_in[4]:27 *C 2.760 61.880 +*N chanx_left_in[4]:28 *C 2.760 62.560 + +*CAP +0 chanx_left_in[4] 0.0001398486 +1 FTB_16__15:A 1e-06 +2 mux_right_track_2\/mux_l2_in_2_:A0 1e-06 +3 mux_top_track_2\/mux_l1_in_3_:A1 1e-06 +4 chanx_left_in[4]:4 0.0004426665 +5 chanx_left_in[4]:5 0.0004426665 +6 chanx_left_in[4]:6 0.0001900169 +7 chanx_left_in[4]:7 0.0001900169 +8 chanx_left_in[4]:8 0.001153765 +9 chanx_left_in[4]:9 0.001172464 +10 chanx_left_in[4]:10 5.056669e-05 +11 chanx_left_in[4]:11 7.343895e-05 +12 chanx_left_in[4]:12 0.0001315528 +13 chanx_left_in[4]:13 0.0001315528 +14 chanx_left_in[4]:14 0.00018237 +15 chanx_left_in[4]:15 0.00018237 +16 chanx_left_in[4]:16 0.001340065 +17 chanx_left_in[4]:17 0.001340065 +18 chanx_left_in[4]:18 0.0009569284 +19 chanx_left_in[4]:19 0.0009569284 +20 chanx_left_in[4]:20 0.0008672037 +21 chanx_left_in[4]:21 0.0009043219 +22 chanx_left_in[4]:22 3.711823e-05 +23 chanx_left_in[4]:23 0.001119839 +24 chanx_left_in[4]:24 0.001085161 +25 chanx_left_in[4]:25 0.002085743 +26 chanx_left_in[4]:26 0.003898415 +27 chanx_left_in[4]:27 0.00187223 +28 chanx_left_in[4]:28 0.0001994068 +29 chanx_left_in[4]:27 chanx_right_in[2]:20 7.024099e-05 +30 chanx_left_in[4]:27 chanx_right_in[2]:23 0.0008852142 +31 chanx_left_in[4]:26 chanx_right_in[2]:17 7.024099e-05 +32 chanx_left_in[4]:26 chanx_right_in[2]:24 0.0008852142 +33 chanx_left_in[4]:23 chanx_left_in[10]:6 2.048032e-05 +34 chanx_left_in[4]:23 chanx_left_in[10]:17 8.238151e-06 +35 chanx_left_in[4]:17 chanx_left_in[10]:11 1.074318e-05 +36 chanx_left_in[4]:16 chanx_left_in[10]:7 1.074318e-05 +37 chanx_left_in[4]:24 chanx_left_in[10]:16 8.238151e-06 +38 chanx_left_in[4]:24 chanx_left_in[10]:17 2.048032e-05 +39 chanx_left_in[4]:25 chanx_left_in[10]:27 0.0002974628 +40 chanx_left_in[4]:27 chanx_left_in[10] 1.981515e-07 +41 chanx_left_in[4]:27 chanx_left_in[10]:36 4.966517e-05 +42 chanx_left_in[4]:27 chanx_left_in[10]:34 0.00118771 +43 chanx_left_in[4]:27 chanx_left_in[10]:32 0.0002131328 +44 chanx_left_in[4]:27 chanx_left_in[10]:30 0.0002928076 +45 chanx_left_in[4]:27 chanx_left_in[10]:28 7.633596e-05 +46 chanx_left_in[4]:26 chanx_left_in[10]:27 7.633596e-05 +47 chanx_left_in[4]:26 chanx_left_in[10]:39 1.981515e-07 +48 chanx_left_in[4]:26 chanx_left_in[10]:35 4.966517e-05 +49 chanx_left_in[4]:26 chanx_left_in[10]:33 0.00118771 +50 chanx_left_in[4]:26 chanx_left_in[10]:31 0.0002131328 +51 chanx_left_in[4]:26 chanx_left_in[10]:29 0.0002928076 +52 chanx_left_in[4]:26 chanx_left_in[10]:28 0.0002974628 +53 chanx_left_in[4]:17 chanx_left_in[12]:14 0.0004382575 +54 chanx_left_in[4]:16 chanx_left_in[12]:13 0.0004382575 +55 chanx_left_in[4]:7 prog_clk[0]:312 1.582491e-09 +56 chanx_left_in[4]:5 prog_clk[0]:313 6.978043e-06 +57 chanx_left_in[4]:5 prog_clk[0]:318 3.306493e-05 +58 chanx_left_in[4]:6 prog_clk[0]:311 1.582491e-09 +59 chanx_left_in[4]:4 prog_clk[0]:314 6.978043e-06 +60 chanx_left_in[4]:4 prog_clk[0]:317 3.306493e-05 +61 chanx_left_in[4]:23 prog_clk[0]:281 1.861456e-07 +62 chanx_left_in[4]:23 prog_clk[0]:207 4.825996e-08 +63 chanx_left_in[4]:20 prog_clk[0]:132 1.120937e-05 +64 chanx_left_in[4]:20 prog_clk[0]:139 0.0002973368 +65 chanx_left_in[4]:17 prog_clk[0]:120 0.0001224552 +66 chanx_left_in[4]:16 prog_clk[0]:119 0.0001224552 +67 chanx_left_in[4]:24 prog_clk[0]:281 4.825996e-08 +68 chanx_left_in[4]:24 prog_clk[0]:280 1.861456e-07 +69 chanx_left_in[4]:25 prog_clk[0]:278 3.644234e-05 +70 chanx_left_in[4]:25 prog_clk[0]:302 8.973647e-05 +71 chanx_left_in[4]:25 prog_clk[0]:217 1.671684e-06 +72 chanx_left_in[4]:27 prog_clk[0]:517 4.663419e-07 +73 chanx_left_in[4]:21 prog_clk[0]:133 1.120937e-05 +74 chanx_left_in[4]:21 prog_clk[0]:140 0.0002973368 +75 chanx_left_in[4]:26 prog_clk[0]:516 4.663419e-07 +76 chanx_left_in[4]:26 prog_clk[0]:279 3.644234e-05 +77 chanx_left_in[4]:26 prog_clk[0]:278 1.671684e-06 +78 chanx_left_in[4]:26 prog_clk[0]:303 8.973647e-05 +79 chanx_left_in[4]:19 right_top_grid_pin_47_[0]:16 0.0002985059 +80 chanx_left_in[4]:18 right_top_grid_pin_47_[0]:15 0.0002985059 +81 chanx_left_in[4]:25 mux_tree_tapbuf_size3_1_sram[0]:16 0.0002550271 +82 chanx_left_in[4]:26 mux_tree_tapbuf_size3_1_sram[0]:15 0.0002550271 +83 chanx_left_in[4]:25 mux_tree_tapbuf_size8_0_sram[1]:26 0.0004923707 +84 chanx_left_in[4]:26 mux_tree_tapbuf_size8_0_sram[1]:25 0.0004923707 +85 chanx_left_in[4]:19 mux_tree_tapbuf_size9_0_sram[3]:8 0.0003667713 +86 chanx_left_in[4]:18 mux_tree_tapbuf_size9_0_sram[3]:9 0.0003667713 +87 chanx_left_in[4]:15 ropt_net_154:4 7.907965e-05 +88 chanx_left_in[4]:14 ropt_net_154:5 7.907965e-05 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:28 0.0002397 +1 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0045 +2 chanx_left_in[4]:7 chanx_left_in[4]:6 0.002651786 +3 chanx_left_in[4]:5 chanx_left_in[4]:4 0.006993304 +4 chanx_left_in[4]:6 chanx_left_in[4]:5 0.0045 +5 chanx_left_in[4]:4 mux_top_track_2\/mux_l1_in_3_:A1 0.152 +6 chanx_left_in[4]:23 chanx_left_in[4]:22 0.00341 +7 chanx_left_in[4]:23 chanx_left_in[4]:11 0.0045 +8 chanx_left_in[4]:22 chanx_left_in[4]:21 4.998413e-05 +9 chanx_left_in[4]:20 chanx_left_in[4]:19 0.00341 +10 chanx_left_in[4]:19 chanx_left_in[4]:18 0.003406716 +11 chanx_left_in[4]:17 chanx_left_in[4]:16 0.003959358 +12 chanx_left_in[4]:18 chanx_left_in[4]:17 0.00341 +13 chanx_left_in[4]:15 chanx_left_in[4]:14 0.002944197 +14 chanx_left_in[4]:16 chanx_left_in[4]:15 0.00341 +15 chanx_left_in[4]:13 chanx_left_in[4]:12 0.001158482 +16 chanx_left_in[4]:14 chanx_left_in[4]:13 0.0045 +17 chanx_left_in[4]:12 FTB_16__15:A 0.152 +18 chanx_left_in[4]:11 chanx_left_in[4]:10 9.51087e-05 +19 chanx_left_in[4]:11 chanx_left_in[4]:9 0.0003035715 +20 chanx_left_in[4]:10 mux_right_track_2\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[4]:24 chanx_left_in[4]:23 0.01664509 +22 chanx_left_in[4]:25 chanx_left_in[4]:24 0.00341 +23 chanx_left_in[4]:9 chanx_left_in[4]:8 0.01515625 +24 chanx_left_in[4]:28 chanx_left_in[4]:27 0.0001065333 +25 chanx_left_in[4]:27 chanx_left_in[4]:26 0.007809833 +26 chanx_left_in[4]:21 chanx_left_in[4]:20 0.002589308 +27 chanx_left_in[4]:26 chanx_left_in[4]:25 0.006025792 + +*END + +*D_NET chany_top_out[5] 0.003463318 //LENGTH 29.890 LUMPCC 0 DR + +*CONN +*I mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 107.585 96.900 +*P chany_top_out[5] O *L 0.7423 *C 83.720 102.070 +*N chany_top_out[5]:2 *C 83.720 101.365 +*N chany_top_out[5]:3 *C 83.765 101.320 +*N chany_top_out[5]:4 *C 107.595 101.320 +*N chany_top_out[5]:5 *C 107.640 101.275 +*N chany_top_out[5]:6 *C 107.640 96.945 +*N chany_top_out[5]:7 *C 107.585 96.900 + +*CAP +0 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[5] 6.027104e-05 +2 chany_top_out[5]:2 6.027104e-05 +3 chany_top_out[5]:3 0.001456298 +4 chany_top_out[5]:4 0.001456298 +5 chany_top_out[5]:5 0.0002015524 +6 chany_top_out[5]:6 0.0002015524 +7 chany_top_out[5]:7 2.607528e-05 + +*RES +0 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[5]:7 0.152 +1 chany_top_out[5]:7 chany_top_out[5]:6 0.0045 +2 chany_top_out[5]:6 chany_top_out[5]:5 0.003866071 +3 chany_top_out[5]:4 chany_top_out[5]:3 0.02127679 +4 chany_top_out[5]:5 chany_top_out[5]:4 0.0045 +5 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +6 chany_top_out[5]:2 chany_top_out[5] 0.0006294643 + +*END + +*D_NET chany_top_out[19] 0.0006458983 //LENGTH 5.170 LUMPCC 0 DR + +*CONN +*I mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 80.500 99.280 +*P chany_top_out[19] O *L 0.7423 *C 78.660 102.035 +*N chany_top_out[19]:2 *C 78.660 100.005 +*N chany_top_out[19]:3 *C 78.705 99.960 +*N chany_top_out[19]:4 *C 80.500 99.960 +*N chany_top_out[19]:5 *C 80.500 99.280 + +*CAP +0 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[19] 0.000123969 +2 chany_top_out[19]:2 0.000123969 +3 chany_top_out[19]:3 0.0001362981 +4 chany_top_out[19]:4 0.0001835596 +5 chany_top_out[19]:5 7.71026e-05 + +*RES +0 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[19]:5 0.152 +1 chany_top_out[19]:3 chany_top_out[19]:2 0.0045 +2 chany_top_out[19]:2 chany_top_out[19] 0.0018125 +3 chany_top_out[19]:5 chany_top_out[19]:4 0.0006071429 +4 chany_top_out[19]:4 chany_top_out[19]:3 0.001602679 + +*END + +*D_NET chanx_left_out[12] 0.001913758 //LENGTH 17.620 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 10.985 28.220 +*P chanx_left_out[12] O *L 0.7423 *C 1.230 23.120 +*N chanx_left_out[12]:2 *C 11.953 23.120 +*N chanx_left_out[12]:3 *C 11.960 23.178 +*N chanx_left_out[12]:4 *C 11.960 28.175 +*N chanx_left_out[12]:5 *C 11.915 28.220 +*N chanx_left_out[12]:6 *C 11.023 28.220 + +*CAP +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[12] 0.0006244879 +2 chanx_left_out[12]:2 0.0006244879 +3 chanx_left_out[12]:3 0.0002638806 +4 chanx_left_out[12]:4 0.0002638806 +5 chanx_left_out[12]:5 6.801068e-05 +6 chanx_left_out[12]:6 6.801068e-05 + +*RES +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[12]:6 0.152 +1 chanx_left_out[12]:6 chanx_left_out[12]:5 0.000796875 +2 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0045 +3 chanx_left_out[12]:4 chanx_left_out[12]:3 0.004462054 +4 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +5 chanx_left_out[12]:2 chanx_left_out[12] 0.001679858 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[3] 0.001069797 //LENGTH 8.170 LUMPCC 0 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 21.005 36.720 +*I mux_left_track_5\/mux_l4_in_0_:S I *L 0.00357 *C 19.440 41.480 +*I mem_left_track_5\/FTB_30__56:A I *L 0.001746 *C 21.065 42.160 +*N mux_tree_tapbuf_size14_1_sram[3]:3 *C 21.065 42.160 +*N mux_tree_tapbuf_size14_1_sram[3]:4 *C 21.160 41.480 +*N mux_tree_tapbuf_size14_1_sram[3]:5 *C 19.478 41.480 +*N mux_tree_tapbuf_size14_1_sram[3]:6 *C 20.700 41.480 +*N mux_tree_tapbuf_size14_1_sram[3]:7 *C 20.700 41.435 +*N mux_tree_tapbuf_size14_1_sram[3]:8 *C 20.700 36.765 +*N mux_tree_tapbuf_size14_1_sram[3]:9 *C 20.700 36.720 +*N mux_tree_tapbuf_size14_1_sram[3]:10 *C 21.005 36.720 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_5\/mux_l4_in_0_:S 1e-06 +2 mem_left_track_5\/FTB_30__56:A 1e-06 +3 mux_tree_tapbuf_size14_1_sram[3]:3 8.056419e-05 +4 mux_tree_tapbuf_size14_1_sram[3]:4 8.447276e-05 +5 mux_tree_tapbuf_size14_1_sram[3]:5 9.437713e-05 +6 mux_tree_tapbuf_size14_1_sram[3]:6 0.000150781 +7 mux_tree_tapbuf_size14_1_sram[3]:7 0.0002716247 +8 mux_tree_tapbuf_size14_1_sram[3]:8 0.0002716247 +9 mux_tree_tapbuf_size14_1_sram[3]:9 5.87668e-05 +10 mux_tree_tapbuf_size14_1_sram[3]:10 5.458584e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size14_1_sram[3]:10 0.152 +1 mux_tree_tapbuf_size14_1_sram[3]:6 mux_tree_tapbuf_size14_1_sram[3]:5 0.001091518 +2 mux_tree_tapbuf_size14_1_sram[3]:6 mux_tree_tapbuf_size14_1_sram[3]:4 0.0004107142 +3 mux_tree_tapbuf_size14_1_sram[3]:7 mux_tree_tapbuf_size14_1_sram[3]:6 0.0045 +4 mux_tree_tapbuf_size14_1_sram[3]:9 mux_tree_tapbuf_size14_1_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size14_1_sram[3]:8 mux_tree_tapbuf_size14_1_sram[3]:7 0.004169643 +6 mux_tree_tapbuf_size14_1_sram[3]:10 mux_tree_tapbuf_size14_1_sram[3]:9 0.0001657609 +7 mux_tree_tapbuf_size14_1_sram[3]:5 mux_left_track_5\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size14_1_sram[3]:3 mem_left_track_5\/FTB_30__56:A 0.152 +9 mux_tree_tapbuf_size14_1_sram[3]:4 mux_tree_tapbuf_size14_1_sram[3]:3 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.001726677 //LENGTH 13.235 LUMPCC 0.0002318069 DR + +*CONN +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 49.525 82.960 +*I mux_top_track_30\/mux_l2_in_0_:S I *L 0.00357 *C 50.040 85.390 +*I mem_top_track_30\/FTB_23__49:A I *L 0.001746 *C 45.080 88.400 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 45.080 88.400 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 45.080 88.355 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 45.080 86.065 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 45.125 86.020 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 50.140 86.020 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 50.110 85.750 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 50.070 85.610 +*N mux_tree_tapbuf_size2_1_sram[1]:10 *C 50.040 85.390 +*N mux_tree_tapbuf_size2_1_sram[1]:11 *C 50.140 85.000 +*N mux_tree_tapbuf_size2_1_sram[1]:12 *C 50.140 84.955 +*N mux_tree_tapbuf_size2_1_sram[1]:13 *C 50.140 83.005 +*N mux_tree_tapbuf_size2_1_sram[1]:14 *C 50.095 82.960 +*N mux_tree_tapbuf_size2_1_sram[1]:15 *C 49.562 82.960 + +*CAP +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_30\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_30\/FTB_23__49:A 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 3.980008e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:4 0.0001662628 +5 mux_tree_tapbuf_size2_1_sram[1]:5 0.0001662628 +6 mux_tree_tapbuf_size2_1_sram[1]:6 0.0002592544 +7 mux_tree_tapbuf_size2_1_sram[1]:7 0.0002849644 +8 mux_tree_tapbuf_size2_1_sram[1]:8 3.115771e-05 +9 mux_tree_tapbuf_size2_1_sram[1]:9 2.069712e-05 +10 mux_tree_tapbuf_size2_1_sram[1]:10 8.074985e-05 +11 mux_tree_tapbuf_size2_1_sram[1]:11 6.216893e-05 +12 mux_tree_tapbuf_size2_1_sram[1]:12 0.0001294858 +13 mux_tree_tapbuf_size2_1_sram[1]:13 0.0001294858 +14 mux_tree_tapbuf_size2_1_sram[1]:14 6.079035e-05 +15 mux_tree_tapbuf_size2_1_sram[1]:15 6.079035e-05 +16 mux_tree_tapbuf_size2_1_sram[1]:6 optlc_net_125:10 0.0001159035 +17 mux_tree_tapbuf_size2_1_sram[1]:7 optlc_net_125:9 0.0001159035 + +*RES +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:10 mux_top_track_30\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:9 0.0001964286 +3 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:8 1.881721e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:11 mux_tree_tapbuf_size2_1_sram[1]:10 0.0003482143 +5 mux_tree_tapbuf_size2_1_sram[1]:12 mux_tree_tapbuf_size2_1_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size2_1_sram[1]:14 mux_tree_tapbuf_size2_1_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size2_1_sram[1]:13 mux_tree_tapbuf_size2_1_sram[1]:12 0.001741072 +8 mux_tree_tapbuf_size2_1_sram[1]:15 mux_tree_tapbuf_size2_1_sram[1]:14 0.0004754465 +9 mux_tree_tapbuf_size2_1_sram[1]:3 mem_top_track_30\/FTB_23__49:A 0.152 +10 mux_tree_tapbuf_size2_1_sram[1]:4 mux_tree_tapbuf_size2_1_sram[1]:3 0.0045 +11 mux_tree_tapbuf_size2_1_sram[1]:6 mux_tree_tapbuf_size2_1_sram[1]:5 0.0045 +12 mux_tree_tapbuf_size2_1_sram[1]:5 mux_tree_tapbuf_size2_1_sram[1]:4 0.002044643 +13 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.004477679 +14 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.0002410715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.0008179052 //LENGTH 6.420 LUMPCC 0.0001995534 DR + +*CONN +*I mem_top_track_32\/FTB_24__50:X O *L 0 *C 33.345 94.180 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 32.835 98.940 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 32.873 98.940 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 33.535 98.940 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 33.580 98.895 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 33.580 94.225 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 33.580 94.180 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 33.345 94.180 + +*CAP +0 mem_top_track_32\/FTB_24__50:X 1e-06 +1 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 6.476811e-05 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 6.476811e-05 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.0001846181 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0001846181 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 6.003794e-05 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 5.75414e-05 +8 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 prog_clk[0]:592 5.585732e-05 +9 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 prog_clk[0]:593 5.585732e-05 +10 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 top_left_grid_pin_38_[0]:31 4.39194e-05 +11 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 top_left_grid_pin_38_[0]:32 4.39194e-05 + +*RES +0 mem_top_track_32\/FTB_24__50:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.004169643 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_5_sram[1] 0.001029214 //LENGTH 8.655 LUMPCC 0 DR + +*CONN +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 89.545 25.840 +*I mem_top_track_22\/FTB_19__45:A I *L 0.001746 *C 87.400 23.120 +*I mux_top_track_22\/mux_l2_in_0_:S I *L 0.00357 *C 89.600 28.560 +*N mux_tree_tapbuf_size3_5_sram[1]:3 *C 89.600 28.560 +*N mux_tree_tapbuf_size3_5_sram[1]:4 *C 89.700 28.515 +*N mux_tree_tapbuf_size3_5_sram[1]:5 *C 87.438 23.120 +*N mux_tree_tapbuf_size3_5_sram[1]:6 *C 89.655 23.120 +*N mux_tree_tapbuf_size3_5_sram[1]:7 *C 89.700 23.165 +*N mux_tree_tapbuf_size3_5_sram[1]:8 *C 89.700 25.840 +*N mux_tree_tapbuf_size3_5_sram[1]:9 *C 89.700 25.840 +*N mux_tree_tapbuf_size3_5_sram[1]:10 *C 89.545 25.840 + +*CAP +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_22\/FTB_19__45:A 1e-06 +2 mux_top_track_22\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_5_sram[1]:3 2.677714e-05 +4 mux_tree_tapbuf_size3_5_sram[1]:4 0.0001561062 +5 mux_tree_tapbuf_size3_5_sram[1]:5 0.0001384642 +6 mux_tree_tapbuf_size3_5_sram[1]:6 0.0001384642 +7 mux_tree_tapbuf_size3_5_sram[1]:7 0.0001378792 +8 mux_tree_tapbuf_size3_5_sram[1]:8 0.0003234492 +9 mux_tree_tapbuf_size3_5_sram[1]:9 5.547217e-05 +10 mux_tree_tapbuf_size3_5_sram[1]:10 4.960126e-05 + +*RES +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_5_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_5_sram[1]:9 mux_tree_tapbuf_size3_5_sram[1]:8 0.0045 +2 mux_tree_tapbuf_size3_5_sram[1]:8 mux_tree_tapbuf_size3_5_sram[1]:7 0.002388393 +3 mux_tree_tapbuf_size3_5_sram[1]:8 mux_tree_tapbuf_size3_5_sram[1]:4 0.002388393 +4 mux_tree_tapbuf_size3_5_sram[1]:10 mux_tree_tapbuf_size3_5_sram[1]:9 8.423914e-05 +5 mux_tree_tapbuf_size3_5_sram[1]:6 mux_tree_tapbuf_size3_5_sram[1]:5 0.001979911 +6 mux_tree_tapbuf_size3_5_sram[1]:7 mux_tree_tapbuf_size3_5_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size3_5_sram[1]:5 mem_top_track_22\/FTB_19__45:A 0.152 +8 mux_tree_tapbuf_size3_5_sram[1]:3 mux_top_track_22\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size3_5_sram[1]:4 mux_tree_tapbuf_size3_5_sram[1]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_3_ccff_tail[0] 0.0008992979 //LENGTH 6.310 LUMPCC 0.0001380366 DR + +*CONN +*I mem_top_track_18\/FTB_17__43:X O *L 0 *C 60.025 28.900 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 60.895 33.660 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 *C 60.858 33.660 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 *C 60.305 33.660 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 *C 60.260 33.615 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 *C 60.260 28.945 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 *C 60.260 28.900 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 *C 60.025 28.900 + +*CAP +0 mem_top_track_18\/FTB_17__43:X 1e-06 +1 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 7.902824e-05 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 7.902824e-05 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.000237758 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.000237758 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 6.326747e-05 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 6.242131e-05 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_0_sram[1]:5 6.901832e-05 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_0_sram[1]:6 6.901832e-05 + +*RES +0 mem_top_track_18\/FTB_17__43:X mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.004169643 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[0] 0.001312596 //LENGTH 10.655 LUMPCC 0 DR + +*CONN +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 114.325 48.280 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 116.095 53.380 +*I mux_top_track_10\/mux_l1_in_0_:S I *L 0.00357 *C 116.280 55.760 +*N mux_tree_tapbuf_size4_1_sram[0]:3 *C 116.265 55.760 +*N mux_tree_tapbuf_size4_1_sram[0]:4 *C 115.943 55.760 +*N mux_tree_tapbuf_size4_1_sram[0]:5 *C 115.920 55.715 +*N mux_tree_tapbuf_size4_1_sram[0]:6 *C 116.095 53.380 +*N mux_tree_tapbuf_size4_1_sram[0]:7 *C 115.920 53.380 +*N mux_tree_tapbuf_size4_1_sram[0]:8 *C 115.920 53.380 +*N mux_tree_tapbuf_size4_1_sram[0]:9 *C 115.920 48.325 +*N mux_tree_tapbuf_size4_1_sram[0]:10 *C 115.875 48.280 +*N mux_tree_tapbuf_size4_1_sram[0]:11 *C 114.363 48.280 + +*CAP +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_10\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_1_sram[0]:3 5.496855e-05 +4 mux_tree_tapbuf_size4_1_sram[0]:4 5.496855e-05 +5 mux_tree_tapbuf_size4_1_sram[0]:5 0.0001351546 +6 mux_tree_tapbuf_size4_1_sram[0]:6 4.642077e-05 +7 mux_tree_tapbuf_size4_1_sram[0]:7 5.054287e-05 +8 mux_tree_tapbuf_size4_1_sram[0]:8 0.0004462267 +9 mux_tree_tapbuf_size4_1_sram[0]:9 0.0002790171 +10 mux_tree_tapbuf_size4_1_sram[0]:10 0.0001211483 +11 mux_tree_tapbuf_size4_1_sram[0]:11 0.0001211483 + +*RES +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_1_sram[0]:11 0.152 +1 mux_tree_tapbuf_size4_1_sram[0]:3 mux_top_track_10\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_1_sram[0]:4 mux_tree_tapbuf_size4_1_sram[0]:3 0.0001752718 +3 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[0]:6 9.51087e-05 +5 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:5 0.002084821 +7 mux_tree_tapbuf_size4_1_sram[0]:6 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size4_1_sram[0]:11 mux_tree_tapbuf_size4_1_sram[0]:10 0.001350446 +9 mux_tree_tapbuf_size4_1_sram[0]:10 mux_tree_tapbuf_size4_1_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size4_1_sram[0]:9 mux_tree_tapbuf_size4_1_sram[0]:8 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[0] 0.00547552 //LENGTH 36.210 LUMPCC 0.001361812 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.465 75.140 +*I mux_top_track_2\/mux_l1_in_2_:S I *L 0.00357 *C 65.420 72.760 +*I mux_top_track_2\/mux_l1_in_3_:S I *L 0.00357 *C 65.420 77.520 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 54.915 86.020 +*I mux_top_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 50.040 88.400 +*I mux_top_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 54.640 88.695 +*N mux_tree_tapbuf_size7_0_sram[0]:6 *C 54.640 88.695 +*N mux_tree_tapbuf_size7_0_sram[0]:7 *C 54.583 88.400 +*N mux_tree_tapbuf_size7_0_sram[0]:8 *C 50.078 88.400 +*N mux_tree_tapbuf_size7_0_sram[0]:9 *C 54.683 88.430 +*N mux_tree_tapbuf_size7_0_sram[0]:10 *C 54.740 88.355 +*N mux_tree_tapbuf_size7_0_sram[0]:11 *C 54.915 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:12 *C 54.740 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:13 *C 54.740 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:14 *C 54.740 86.418 +*N mux_tree_tapbuf_size7_0_sram[0]:15 *C 54.748 86.360 +*N mux_tree_tapbuf_size7_0_sram[0]:16 *C 62.553 86.360 +*N mux_tree_tapbuf_size7_0_sram[0]:17 *C 62.560 86.303 +*N mux_tree_tapbuf_size7_0_sram[0]:18 *C 62.560 85.385 +*N mux_tree_tapbuf_size7_0_sram[0]:19 *C 62.605 85.340 +*N mux_tree_tapbuf_size7_0_sram[0]:20 *C 65.275 85.340 +*N mux_tree_tapbuf_size7_0_sram[0]:21 *C 65.320 85.295 +*N mux_tree_tapbuf_size7_0_sram[0]:22 *C 65.320 77.520 +*N mux_tree_tapbuf_size7_0_sram[0]:23 *C 65.320 77.520 +*N mux_tree_tapbuf_size7_0_sram[0]:24 *C 65.320 72.760 +*N mux_tree_tapbuf_size7_0_sram[0]:25 *C 65.320 72.805 +*N mux_tree_tapbuf_size7_0_sram[0]:26 *C 65.320 75.140 +*N mux_tree_tapbuf_size7_0_sram[0]:27 *C 65.365 75.140 +*N mux_tree_tapbuf_size7_0_sram[0]:28 *C 67.428 75.140 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_2\/mux_l1_in_2_:S 1e-06 +2 mux_top_track_2\/mux_l1_in_3_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_2\/mux_l1_in_0_:S 1e-06 +5 mux_top_track_2\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_0_sram[0]:6 5.468102e-05 +7 mux_tree_tapbuf_size7_0_sram[0]:7 2.120154e-05 +8 mux_tree_tapbuf_size7_0_sram[0]:8 0.0003481676 +9 mux_tree_tapbuf_size7_0_sram[0]:9 0.0003941058 +10 mux_tree_tapbuf_size7_0_sram[0]:10 0.0001572294 +11 mux_tree_tapbuf_size7_0_sram[0]:11 5.062211e-05 +12 mux_tree_tapbuf_size7_0_sram[0]:12 5.546184e-05 +13 mux_tree_tapbuf_size7_0_sram[0]:13 5.894538e-05 +14 mux_tree_tapbuf_size7_0_sram[0]:14 0.0001824515 +15 mux_tree_tapbuf_size7_0_sram[0]:15 0.0003874286 +16 mux_tree_tapbuf_size7_0_sram[0]:16 0.0003874286 +17 mux_tree_tapbuf_size7_0_sram[0]:17 6.431699e-05 +18 mux_tree_tapbuf_size7_0_sram[0]:18 6.431699e-05 +19 mux_tree_tapbuf_size7_0_sram[0]:19 0.000176739 +20 mux_tree_tapbuf_size7_0_sram[0]:20 0.000176739 +21 mux_tree_tapbuf_size7_0_sram[0]:21 0.0003379477 +22 mux_tree_tapbuf_size7_0_sram[0]:22 3.438801e-05 +23 mux_tree_tapbuf_size7_0_sram[0]:23 0.0004733788 +24 mux_tree_tapbuf_size7_0_sram[0]:24 3.343335e-05 +25 mux_tree_tapbuf_size7_0_sram[0]:25 0.0001138265 +26 mux_tree_tapbuf_size7_0_sram[0]:26 0.0002511945 +27 mux_tree_tapbuf_size7_0_sram[0]:27 0.0001418516 +28 mux_tree_tapbuf_size7_0_sram[0]:28 0.0001418516 +29 mux_tree_tapbuf_size7_0_sram[0]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.186093e-05 +30 mux_tree_tapbuf_size7_0_sram[0]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.186093e-05 +31 mux_tree_tapbuf_size7_0_sram[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:9 3.532331e-06 +32 mux_tree_tapbuf_size7_0_sram[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 3.532331e-06 +33 mux_tree_tapbuf_size7_0_sram[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.747102e-05 +34 mux_tree_tapbuf_size7_0_sram[0]:25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.714533e-05 +35 mux_tree_tapbuf_size7_0_sram[0]:26 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.714533e-05 +36 mux_tree_tapbuf_size7_0_sram[0]:26 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.733539e-05 +37 mux_tree_tapbuf_size7_0_sram[0]:23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.733539e-05 +38 mux_tree_tapbuf_size7_0_sram[0]:23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.747102e-05 +39 mux_tree_tapbuf_size7_0_sram[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.276905e-05 +40 mux_tree_tapbuf_size7_0_sram[0]:23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.276905e-05 +41 mux_tree_tapbuf_size7_0_sram[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.000426976 +42 mux_tree_tapbuf_size7_0_sram[0]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:13 2.381601e-05 +43 mux_tree_tapbuf_size7_0_sram[0]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.000426976 +44 mux_tree_tapbuf_size7_0_sram[0]:18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:12 2.381601e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_0_sram[0]:28 0.152 +1 mux_tree_tapbuf_size7_0_sram[0]:14 mux_tree_tapbuf_size7_0_sram[0]:13 0.0001911058 +2 mux_tree_tapbuf_size7_0_sram[0]:14 mux_tree_tapbuf_size7_0_sram[0]:10 0.001729911 +3 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:14 0.00341 +4 mux_tree_tapbuf_size7_0_sram[0]:17 mux_tree_tapbuf_size7_0_sram[0]:16 0.00341 +5 mux_tree_tapbuf_size7_0_sram[0]:16 mux_tree_tapbuf_size7_0_sram[0]:15 0.001222783 +6 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:18 0.0045 +7 mux_tree_tapbuf_size7_0_sram[0]:18 mux_tree_tapbuf_size7_0_sram[0]:17 0.0008191965 +8 mux_tree_tapbuf_size7_0_sram[0]:20 mux_tree_tapbuf_size7_0_sram[0]:19 0.002383929 +9 mux_tree_tapbuf_size7_0_sram[0]:21 mux_tree_tapbuf_size7_0_sram[0]:20 0.0045 +10 mux_tree_tapbuf_size7_0_sram[0]:8 mux_top_track_2\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size7_0_sram[0]:24 mux_top_track_2\/mux_l1_in_2_:S 0.152 +12 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_0_sram[0]:24 0.0045 +13 mux_tree_tapbuf_size7_0_sram[0]:12 mux_tree_tapbuf_size7_0_sram[0]:11 9.51087e-05 +14 mux_tree_tapbuf_size7_0_sram[0]:13 mux_tree_tapbuf_size7_0_sram[0]:12 0.0045 +15 mux_tree_tapbuf_size7_0_sram[0]:11 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:26 0.0045 +17 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:25 0.002084821 +18 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:23 0.002125 +19 mux_tree_tapbuf_size7_0_sram[0]:28 mux_tree_tapbuf_size7_0_sram[0]:27 0.001841518 +20 mux_tree_tapbuf_size7_0_sram[0]:22 mux_top_track_2\/mux_l1_in_3_:S 0.152 +21 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:22 0.0045 +22 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:21 0.006941964 +23 mux_tree_tapbuf_size7_0_sram[0]:6 mux_top_track_2\/mux_l1_in_1_:S 0.152 +24 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:8 0.004111608 +25 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:7 8.928572e-05 +26 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:6 0.0001142241 +27 mux_tree_tapbuf_size7_0_sram[0]:10 mux_tree_tapbuf_size7_0_sram[0]:9 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[0] 0.007367873 //LENGTH 56.125 LUMPCC 0.0002549093 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.925 37.060 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.055 42.500 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 62.200 52.360 +*I mux_left_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 59.440 47.310 +*I mux_left_track_25\/mux_l1_in_2_:S I *L 0.00357 *C 38.540 47.310 +*I mux_left_track_25\/mux_l1_in_3_:S I *L 0.00357 *C 33.940 47.260 +*N mux_tree_tapbuf_size7_6_sram[0]:6 *C 33.977 47.260 +*N mux_tree_tapbuf_size7_6_sram[0]:7 *C 37.260 47.260 +*N mux_tree_tapbuf_size7_6_sram[0]:8 *C 38.540 47.310 +*N mux_tree_tapbuf_size7_6_sram[0]:9 *C 59.440 47.310 +*N mux_tree_tapbuf_size7_6_sram[0]:10 *C 62.100 52.360 +*N mux_tree_tapbuf_size7_6_sram[0]:11 *C 62.100 52.315 +*N mux_tree_tapbuf_size7_6_sram[0]:12 *C 62.100 46.965 +*N mux_tree_tapbuf_size7_6_sram[0]:13 *C 62.055 46.920 +*N mux_tree_tapbuf_size7_6_sram[0]:14 *C 59.440 46.920 +*N mux_tree_tapbuf_size7_6_sram[0]:15 *C 38.540 46.920 +*N mux_tree_tapbuf_size7_6_sram[0]:16 *C 37.260 46.920 +*N mux_tree_tapbuf_size7_6_sram[0]:17 *C 37.260 46.875 +*N mux_tree_tapbuf_size7_6_sram[0]:18 *C 36.093 42.500 +*N mux_tree_tapbuf_size7_6_sram[0]:19 *C 37.215 42.500 +*N mux_tree_tapbuf_size7_6_sram[0]:20 *C 37.260 42.500 +*N mux_tree_tapbuf_size7_6_sram[0]:21 *C 37.260 39.145 +*N mux_tree_tapbuf_size7_6_sram[0]:22 *C 37.305 39.100 +*N mux_tree_tapbuf_size7_6_sram[0]:23 *C 44.575 39.100 +*N mux_tree_tapbuf_size7_6_sram[0]:24 *C 44.620 39.055 +*N mux_tree_tapbuf_size7_6_sram[0]:25 *C 44.620 37.105 +*N mux_tree_tapbuf_size7_6_sram[0]:26 *C 44.620 37.060 +*N mux_tree_tapbuf_size7_6_sram[0]:27 *C 44.925 37.060 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_left_track_25\/mux_l1_in_2_:S 1e-06 +5 mux_left_track_25\/mux_l1_in_3_:S 1e-06 +6 mux_tree_tapbuf_size7_6_sram[0]:6 0.0002686326 +7 mux_tree_tapbuf_size7_6_sram[0]:7 0.0002956058 +8 mux_tree_tapbuf_size7_6_sram[0]:8 6.134841e-05 +9 mux_tree_tapbuf_size7_6_sram[0]:9 6.568155e-05 +10 mux_tree_tapbuf_size7_6_sram[0]:10 3.082002e-05 +11 mux_tree_tapbuf_size7_6_sram[0]:11 0.0003941427 +12 mux_tree_tapbuf_size7_6_sram[0]:12 0.0003941427 +13 mux_tree_tapbuf_size7_6_sram[0]:13 0.0002174586 +14 mux_tree_tapbuf_size7_6_sram[0]:14 0.001501237 +15 mux_tree_tapbuf_size7_6_sram[0]:15 0.001380106 +16 mux_tree_tapbuf_size7_6_sram[0]:16 0.0001264067 +17 mux_tree_tapbuf_size7_6_sram[0]:17 0.0002792325 +18 mux_tree_tapbuf_size7_6_sram[0]:18 8.667889e-05 +19 mux_tree_tapbuf_size7_6_sram[0]:19 8.667889e-05 +20 mux_tree_tapbuf_size7_6_sram[0]:20 0.0004980378 +21 mux_tree_tapbuf_size7_6_sram[0]:21 0.0001868632 +22 mux_tree_tapbuf_size7_6_sram[0]:22 0.0004479869 +23 mux_tree_tapbuf_size7_6_sram[0]:23 0.0004479869 +24 mux_tree_tapbuf_size7_6_sram[0]:24 0.0001220112 +25 mux_tree_tapbuf_size7_6_sram[0]:25 0.0001220112 +26 mux_tree_tapbuf_size7_6_sram[0]:26 4.991219e-05 +27 mux_tree_tapbuf_size7_6_sram[0]:27 4.398267e-05 +28 mux_tree_tapbuf_size7_6_sram[0]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001274547 +29 mux_tree_tapbuf_size7_6_sram[0]:14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001274547 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_6_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_6_sram[0]:13 mux_tree_tapbuf_size7_6_sram[0]:12 0.0045 +2 mux_tree_tapbuf_size7_6_sram[0]:12 mux_tree_tapbuf_size7_6_sram[0]:11 0.004776786 +3 mux_tree_tapbuf_size7_6_sram[0]:10 mux_left_track_25\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size7_6_sram[0]:11 mux_tree_tapbuf_size7_6_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size7_6_sram[0]:16 mux_tree_tapbuf_size7_6_sram[0]:15 0.001142857 +6 mux_tree_tapbuf_size7_6_sram[0]:16 mux_tree_tapbuf_size7_6_sram[0]:7 0.0003035715 +7 mux_tree_tapbuf_size7_6_sram[0]:17 mux_tree_tapbuf_size7_6_sram[0]:16 0.0045 +8 mux_tree_tapbuf_size7_6_sram[0]:6 mux_left_track_25\/mux_l1_in_3_:S 0.152 +9 mux_tree_tapbuf_size7_6_sram[0]:19 mux_tree_tapbuf_size7_6_sram[0]:18 0.001002232 +10 mux_tree_tapbuf_size7_6_sram[0]:20 mux_tree_tapbuf_size7_6_sram[0]:19 0.0045 +11 mux_tree_tapbuf_size7_6_sram[0]:20 mux_tree_tapbuf_size7_6_sram[0]:17 0.00390625 +12 mux_tree_tapbuf_size7_6_sram[0]:18 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size7_6_sram[0]:22 mux_tree_tapbuf_size7_6_sram[0]:21 0.0045 +14 mux_tree_tapbuf_size7_6_sram[0]:21 mux_tree_tapbuf_size7_6_sram[0]:20 0.002995536 +15 mux_tree_tapbuf_size7_6_sram[0]:23 mux_tree_tapbuf_size7_6_sram[0]:22 0.006491072 +16 mux_tree_tapbuf_size7_6_sram[0]:24 mux_tree_tapbuf_size7_6_sram[0]:23 0.0045 +17 mux_tree_tapbuf_size7_6_sram[0]:26 mux_tree_tapbuf_size7_6_sram[0]:25 0.0045 +18 mux_tree_tapbuf_size7_6_sram[0]:25 mux_tree_tapbuf_size7_6_sram[0]:24 0.001741072 +19 mux_tree_tapbuf_size7_6_sram[0]:27 mux_tree_tapbuf_size7_6_sram[0]:26 0.0001657609 +20 mux_tree_tapbuf_size7_6_sram[0]:8 mux_left_track_25\/mux_l1_in_2_:S 0.152 +21 mux_tree_tapbuf_size7_6_sram[0]:9 mux_left_track_25\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_6_sram[0]:7 mux_tree_tapbuf_size7_6_sram[0]:6 0.002930804 +23 mux_tree_tapbuf_size7_6_sram[0]:15 mux_tree_tapbuf_size7_6_sram[0]:14 0.01866072 +24 mux_tree_tapbuf_size7_6_sram[0]:15 mux_tree_tapbuf_size7_6_sram[0]:8 0.0003482143 +25 mux_tree_tapbuf_size7_6_sram[0]:14 mux_tree_tapbuf_size7_6_sram[0]:13 0.002334822 +26 mux_tree_tapbuf_size7_6_sram[0]:14 mux_tree_tapbuf_size7_6_sram[0]:9 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[3] 0.001592289 //LENGTH 13.580 LUMPCC 0.0003368557 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 125.425 42.160 +*I mem_right_track_8\/FTB_2__28:A I *L 0.001746 *C 122.360 34.000 +*I mux_right_track_8\/mux_l4_in_0_:S I *L 0.00357 *C 125.920 36.380 +*N mux_tree_tapbuf_size8_1_sram[3]:3 *C 125.905 36.380 +*N mux_tree_tapbuf_size8_1_sram[3]:4 *C 122.398 34.000 +*N mux_tree_tapbuf_size8_1_sram[3]:5 *C 122.775 34.000 +*N mux_tree_tapbuf_size8_1_sram[3]:6 *C 122.820 34.045 +*N mux_tree_tapbuf_size8_1_sram[3]:7 *C 122.820 36.335 +*N mux_tree_tapbuf_size8_1_sram[3]:8 *C 122.865 36.380 +*N mux_tree_tapbuf_size8_1_sram[3]:9 *C 125.603 36.380 +*N mux_tree_tapbuf_size8_1_sram[3]:10 *C 125.580 36.425 +*N mux_tree_tapbuf_size8_1_sram[3]:11 *C 125.580 42.115 +*N mux_tree_tapbuf_size8_1_sram[3]:12 *C 125.580 42.160 +*N mux_tree_tapbuf_size8_1_sram[3]:13 *C 125.425 42.160 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_8\/FTB_2__28:A 1e-06 +2 mux_right_track_8\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_1_sram[3]:3 4.944206e-05 +4 mux_tree_tapbuf_size8_1_sram[3]:4 6.798873e-05 +5 mux_tree_tapbuf_size8_1_sram[3]:5 6.798873e-05 +6 mux_tree_tapbuf_size8_1_sram[3]:6 0.0001288761 +7 mux_tree_tapbuf_size8_1_sram[3]:7 0.0001288761 +8 mux_tree_tapbuf_size8_1_sram[3]:8 0.0001488608 +9 mux_tree_tapbuf_size8_1_sram[3]:9 0.0001983028 +10 mux_tree_tapbuf_size8_1_sram[3]:10 0.0001831533 +11 mux_tree_tapbuf_size8_1_sram[3]:11 0.0001831533 +12 mux_tree_tapbuf_size8_1_sram[3]:12 4.941976e-05 +13 mux_tree_tapbuf_size8_1_sram[3]:13 4.637114e-05 +14 mux_tree_tapbuf_size8_1_sram[3]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.569791e-05 +15 mux_tree_tapbuf_size8_1_sram[3]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.569791e-05 +16 mux_tree_tapbuf_size8_1_sram[3]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.826015e-06 +17 mux_tree_tapbuf_size8_1_sram[3]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.990494e-05 +18 mux_tree_tapbuf_size8_1_sram[3]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.826015e-06 +19 mux_tree_tapbuf_size8_1_sram[3]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.899898e-05 +20 mux_tree_tapbuf_size8_1_sram[3]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.899898e-05 +21 mux_tree_tapbuf_size8_1_sram[3]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.990494e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_1_sram[3]:13 0.152 +1 mux_tree_tapbuf_size8_1_sram[3]:3 mux_right_track_8\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[3]:9 mux_tree_tapbuf_size8_1_sram[3]:8 0.002444197 +3 mux_tree_tapbuf_size8_1_sram[3]:9 mux_tree_tapbuf_size8_1_sram[3]:3 0.0001644022 +4 mux_tree_tapbuf_size8_1_sram[3]:10 mux_tree_tapbuf_size8_1_sram[3]:9 0.0045 +5 mux_tree_tapbuf_size8_1_sram[3]:12 mux_tree_tapbuf_size8_1_sram[3]:11 0.0045 +6 mux_tree_tapbuf_size8_1_sram[3]:11 mux_tree_tapbuf_size8_1_sram[3]:10 0.005080357 +7 mux_tree_tapbuf_size8_1_sram[3]:13 mux_tree_tapbuf_size8_1_sram[3]:12 8.423914e-05 +8 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:7 0.0045 +9 mux_tree_tapbuf_size8_1_sram[3]:7 mux_tree_tapbuf_size8_1_sram[3]:6 0.002044643 +10 mux_tree_tapbuf_size8_1_sram[3]:5 mux_tree_tapbuf_size8_1_sram[3]:4 0.0003370536 +11 mux_tree_tapbuf_size8_1_sram[3]:6 mux_tree_tapbuf_size8_1_sram[3]:5 0.0045 +12 mux_tree_tapbuf_size8_1_sram[3]:4 mem_right_track_8\/FTB_2__28:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_1_ccff_tail[0] 0.001341407 //LENGTH 8.580 LUMPCC 0.000776324 DR + +*CONN +*I mem_right_track_8\/FTB_2__28:X O *L 0 *C 119.365 34.000 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 114.255 31.620 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 *C 114.255 31.620 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 *C 114.080 31.620 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 *C 114.080 31.665 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 *C 114.080 33.955 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 *C 114.125 34.000 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 *C 119.328 34.000 + +*CAP +0 mem_right_track_8\/FTB_2__28:X 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 5.02506e-05 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 5.40474e-05 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.0001357005 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0001357005 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 9.369224e-05 +7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 9.369224e-05 +8 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 chanx_left_in[5]:17 0.000176644 +9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 chanx_left_in[5]:18 0.000176644 +10 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000211518 +11 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.000211518 + +*RES +0 mem_right_track_8\/FTB_2__28:X mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.00464509 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[2] 0.002421103 //LENGTH 18.680 LUMPCC 0.0001538275 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 124.050 66.640 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 121.615 71.740 +*I mux_right_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 119.040 69.360 +*I mux_right_track_0\/mux_l3_in_1_:S I *L 0.00357 *C 127.300 63.580 +*N mux_tree_tapbuf_size9_0_sram[2]:4 *C 127.263 63.580 +*N mux_tree_tapbuf_size9_0_sram[2]:5 *C 124.705 63.580 +*N mux_tree_tapbuf_size9_0_sram[2]:6 *C 124.660 63.625 +*N mux_tree_tapbuf_size9_0_sram[2]:7 *C 124.660 66.640 +*N mux_tree_tapbuf_size9_0_sram[2]:8 *C 119.078 69.360 +*N mux_tree_tapbuf_size9_0_sram[2]:9 *C 121.615 71.740 +*N mux_tree_tapbuf_size9_0_sram[2]:10 *C 121.440 71.740 +*N mux_tree_tapbuf_size9_0_sram[2]:11 *C 121.440 71.695 +*N mux_tree_tapbuf_size9_0_sram[2]:12 *C 121.440 69.405 +*N mux_tree_tapbuf_size9_0_sram[2]:13 *C 121.440 69.360 +*N mux_tree_tapbuf_size9_0_sram[2]:14 *C 124.155 69.360 +*N mux_tree_tapbuf_size9_0_sram[2]:15 *C 124.200 69.315 +*N mux_tree_tapbuf_size9_0_sram[2]:16 *C 124.200 66.640 +*N mux_tree_tapbuf_size9_0_sram[2]:17 *C 124.200 66.640 +*N mux_tree_tapbuf_size9_0_sram[2]:18 *C 124.050 66.640 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_track_0\/mux_l3_in_0_:S 1e-06 +3 mux_right_track_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size9_0_sram[2]:4 0.0002021185 +5 mux_tree_tapbuf_size9_0_sram[2]:5 0.0002021185 +6 mux_tree_tapbuf_size9_0_sram[2]:6 0.0001894588 +7 mux_tree_tapbuf_size9_0_sram[2]:7 0.0002110567 +8 mux_tree_tapbuf_size9_0_sram[2]:8 0.0001723432 +9 mux_tree_tapbuf_size9_0_sram[2]:9 4.46408e-05 +10 mux_tree_tapbuf_size9_0_sram[2]:10 4.854194e-05 +11 mux_tree_tapbuf_size9_0_sram[2]:11 0.0001419885 +12 mux_tree_tapbuf_size9_0_sram[2]:12 0.0001419885 +13 mux_tree_tapbuf_size9_0_sram[2]:13 0.0003307023 +14 mux_tree_tapbuf_size9_0_sram[2]:14 0.0001276926 +15 mux_tree_tapbuf_size9_0_sram[2]:15 0.0001618305 +16 mux_tree_tapbuf_size9_0_sram[2]:16 0.0001834284 +17 mux_tree_tapbuf_size9_0_sram[2]:17 5.463415e-05 +18 mux_tree_tapbuf_size9_0_sram[2]:18 5.073237e-05 +19 mux_tree_tapbuf_size9_0_sram[2]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.164837e-05 +20 mux_tree_tapbuf_size9_0_sram[2]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.508277e-05 +21 mux_tree_tapbuf_size9_0_sram[2]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.508277e-05 +22 mux_tree_tapbuf_size9_0_sram[2]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.018259e-05 +23 mux_tree_tapbuf_size9_0_sram[2]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.018259e-05 +24 mux_tree_tapbuf_size9_0_sram[2]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.164837e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size9_0_sram[2]:18 0.152 +1 mux_tree_tapbuf_size9_0_sram[2]:18 mux_tree_tapbuf_size9_0_sram[2]:17 8.152174e-05 +2 mux_tree_tapbuf_size9_0_sram[2]:17 mux_tree_tapbuf_size9_0_sram[2]:16 0.0045 +3 mux_tree_tapbuf_size9_0_sram[2]:16 mux_tree_tapbuf_size9_0_sram[2]:15 0.002388393 +4 mux_tree_tapbuf_size9_0_sram[2]:16 mux_tree_tapbuf_size9_0_sram[2]:7 0.0004107143 +5 mux_tree_tapbuf_size9_0_sram[2]:14 mux_tree_tapbuf_size9_0_sram[2]:13 0.002424107 +6 mux_tree_tapbuf_size9_0_sram[2]:15 mux_tree_tapbuf_size9_0_sram[2]:14 0.0045 +7 mux_tree_tapbuf_size9_0_sram[2]:13 mux_tree_tapbuf_size9_0_sram[2]:12 0.0045 +8 mux_tree_tapbuf_size9_0_sram[2]:13 mux_tree_tapbuf_size9_0_sram[2]:8 0.002109375 +9 mux_tree_tapbuf_size9_0_sram[2]:12 mux_tree_tapbuf_size9_0_sram[2]:11 0.002044643 +10 mux_tree_tapbuf_size9_0_sram[2]:10 mux_tree_tapbuf_size9_0_sram[2]:9 9.51087e-05 +11 mux_tree_tapbuf_size9_0_sram[2]:11 mux_tree_tapbuf_size9_0_sram[2]:10 0.0045 +12 mux_tree_tapbuf_size9_0_sram[2]:9 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size9_0_sram[2]:5 mux_tree_tapbuf_size9_0_sram[2]:4 0.002283482 +14 mux_tree_tapbuf_size9_0_sram[2]:6 mux_tree_tapbuf_size9_0_sram[2]:5 0.0045 +15 mux_tree_tapbuf_size9_0_sram[2]:4 mux_right_track_0\/mux_l3_in_1_:S 0.152 +16 mux_tree_tapbuf_size9_0_sram[2]:8 mux_right_track_0\/mux_l3_in_0_:S 0.152 +17 mux_tree_tapbuf_size9_0_sram[2]:7 mux_tree_tapbuf_size9_0_sram[2]:6 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size9_mem_0_ccff_tail[0] 0.000795907 //LENGTH 5.985 LUMPCC 0.0001603413 DR + +*CONN +*I mem_right_track_0\/FTB_27__53:X O *L 0 *C 106.430 91.800 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 103.215 93.500 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 *C 103.238 93.473 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 *C 103.250 93.160 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 *C 105.755 93.160 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 *C 105.800 93.115 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 *C 105.800 91.845 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 *C 105.845 91.800 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:8 *C 106.392 91.800 + +*CAP +0 mem_right_track_0\/FTB_27__53:X 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 3.03072e-05 +3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 0.0001731949 +4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 0.0001428877 +5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 8.682487e-05 +6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 8.682487e-05 +7 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 5.676308e-05 +8 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:8 5.676308e-05 +9 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size9_1_sram[0]:17 8.017064e-05 +10 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size9_1_sram[0]:16 8.017064e-05 + +*RES +0 mem_right_track_0\/FTB_27__53:X mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 0.002236607 +3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 0.0045 +4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 0.0045 +5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 0.001133929 +6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 0.0004888393 +7 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 0.0002111487 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000786907 //LENGTH 5.360 LUMPCC 0.0003170143 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_2_:X O *L 0 *C 46.285 69.700 +*I mux_top_track_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 48.400 72.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 48.300 72.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 48.300 72.375 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 48.300 69.745 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 48.255 69.700 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 46.323 69.700 + +*CAP +0 mux_top_track_0\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.416586e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000124614 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000124614 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.224944e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.224944e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_right_in[4]:19 8.285091e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[4]:14 8.285091e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.565623e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.565623e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001725447 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001386218 //LENGTH 11.625 LUMPCC 0.0001228111 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 86.765 53.040 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 94.400 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 94.363 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 88.365 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 88.320 56.055 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 88.320 53.085 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 88.275 53.040 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 86.803 53.040 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003814306 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003814306 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001839532 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001839532 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.531982e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.531982e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size8_1_sram[0]:5 1.798677e-06 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size8_1_sram[0]:7 5.960687e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size8_1_sram[0]:4 1.798677e-06 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 5.960687e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005354911 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001148951 //LENGTH 8.980 LUMPCC 0.0001313624 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_0_:X O *L 0 *C 25.935 71.740 +*I mux_left_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 20.605 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 20.643 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 25.255 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 25.300 69.065 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 25.300 71.695 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 25.345 71.740 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 25.898 71.740 + +*CAP +0 mux_left_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002681629 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002681629 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001686957 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001686957 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.093561e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.093561e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:13 6.554533e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:14 6.554533e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size8_2_sram[2]:15 1.35847e-07 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_2_sram[2]:16 1.35847e-07 + +*RES +0 mux_left_track_3\/mux_l2_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004118304 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003726702 //LENGTH 29.295 LUMPCC 0.0008550175 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 33.295 55.760 +*I mux_left_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 27.045 34.340 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 27.045 34.340 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 27.140 34.000 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 30.775 34.000 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 30.820 34.045 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 30.820 55.715 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 30.865 55.760 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 33.258 55.760 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.307629e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002617806 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002356017 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001060521 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001060521 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.909162e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.909162e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:462 5.214219e-06 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:460 4.560096e-06 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:464 9.058389e-07 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:491 0.0001719274 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:497 0.0001377072 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:461 4.560096e-06 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:478 9.058389e-07 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:497 0.0001719274 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:518 0.0001377072 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 prog_clk[0]:457 5.214219e-06 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:25 3.34758e-06 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size8_3_sram[1]:26 3.874795e-07 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size8_3_sram[1]:8 0.0001034589 +22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_3_sram[1]:12 3.874795e-07 +23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size8_3_sram[1]:26 3.34758e-06 +24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size8_3_sram[1]:7 0.0001034589 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003245536 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.01934822 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.002136161 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001806792 //LENGTH 12.395 LUMPCC 0.000776176 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_0_:X O *L 0 *C 66.985 88.740 +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 63.765 96.745 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 63.803 96.845 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 67.115 96.900 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 67.160 96.855 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 67.160 88.785 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 67.160 88.740 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 66.985 88.740 + +*CAP +0 mux_top_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001610847 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001610847 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003014897 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003014897 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.383038e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.963698e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[7]:14 0.0001748047 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[7] 0.0001748047 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size7_0_sram[2]:3 1.063579e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size7_0_sram[2]:4 1.063579e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size7_0_sram[2]:10 7.132606e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size7_0_sram[2]:11 7.132606e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001313214 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001313214 + +*RES +0 mux_top_track_2\/mux_l3_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.007205358 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002957589 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003979204 //LENGTH 3.130 LUMPCC 0 DR + +*CONN +*I mux_top_track_6\/mux_l2_in_0_:X O *L 0 *C 84.925 50.660 +*I mux_top_track_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 87.765 50.660 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 87.728 50.660 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 84.963 50.660 + +*CAP +0 mux_top_track_6\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_6\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001979602 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001979602 + +*RES +0 mux_top_track_6\/mux_l2_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_6\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.00246875 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005472716 //LENGTH 4.190 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_2_:X O *L 0 *C 102.865 28.220 +*I mux_right_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 102.025 25.500 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 102.062 25.500 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 102.535 25.500 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 102.580 25.545 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 102.580 28.175 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 102.580 28.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 102.865 28.220 + +*CAP +0 mux_right_track_16\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.366086e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.366086e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001559667 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001559667 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.371859e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.22978e-05 + +*RES +0 mux_right_track_16\/mux_l1_in_2_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_16\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004218751 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002916711 //LENGTH 22.200 LUMPCC 0.0001482404 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_0_:X O *L 0 *C 66.875 31.960 +*I mux_left_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 48.665 28.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 48.703 28.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.635 28.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.680 28.945 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.680 31.915 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 49.725 31.960 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 66.838 31.960 + +*CAP +0 mux_left_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001085495 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001085495 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001860099 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001860099 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001088676 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.001088676 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_126:33 7.412021e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_126:34 7.412021e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01527902 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325894 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001969693 //LENGTH 15.930 LUMPCC 0.0005772636 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 101.025 39.780 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 113.985 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 113.948 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 103.085 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 103.040 41.775 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 103.040 39.825 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 102.995 39.780 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 101.062 39.780 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004976056 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004976056 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.534164e-05 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.534164e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001022677 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001022677 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_0_sram[0]:6 1.411082e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_0_sram[0]:10 1.925783e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size4_0_sram[0]:8 5.202673e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_0_sram[0]:5 1.411082e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_0_sram[0]:9 1.925783e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size4_0_sram[0]:7 5.202673e-05 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size4_0_sram[1]:4 0.0002032364 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size4_0_sram[1]:5 0.0002032364 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.009698661 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741071 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET optlc_net_124 0.01377041 //LENGTH 94.690 LUMPCC 0.003659211 DR + +*CONN +*I optlc_118:HI O *L 0 *C 110.400 58.820 +*I mux_right_track_24\/mux_l1_in_3_:A0 I *L 0.001631 *C 100.110 55.080 +*I mux_right_track_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 111.150 55.080 +*I mux_right_track_16\/mux_l1_in_3_:A0 I *L 0.001631 *C 106.550 26.520 +*I mux_top_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 104.135 39.100 +*I mux_right_track_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 127.710 48.280 +*I mux_top_track_10\/mux_l2_in_1_:A0 I *L 0.001631 *C 125.870 60.520 +*I mux_right_track_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 127.695 65.960 +*N optlc_net_124:8 *C 127.695 65.960 +*N optlc_net_124:9 *C 127.880 65.960 +*N optlc_net_124:10 *C 127.880 65.915 +*N optlc_net_124:11 *C 127.880 60.520 +*N optlc_net_124:12 *C 125.908 60.520 +*N optlc_net_124:13 *C 126.915 60.520 +*N optlc_net_124:14 *C 126.960 60.520 +*N optlc_net_124:15 *C 127.710 48.280 +*N optlc_net_124:16 *C 127.420 48.280 +*N optlc_net_124:17 *C 127.420 48.325 +*N optlc_net_124:18 *C 127.420 51.000 +*N optlc_net_124:19 *C 126.960 51.000 +*N optlc_net_124:20 *C 126.953 51.000 +*N optlc_net_124:21 *C 104.172 39.100 +*N optlc_net_124:22 *C 106.675 39.100 +*N optlc_net_124:23 *C 106.720 39.055 +*N optlc_net_124:24 *C 106.550 26.520 +*N optlc_net_124:25 *C 106.720 26.520 +*N optlc_net_124:26 *C 106.720 26.565 +*N optlc_net_124:27 *C 106.720 37.400 +*N optlc_net_124:28 *C 106.728 37.400 +*N optlc_net_124:29 *C 109.460 37.400 +*N optlc_net_124:30 *C 109.480 37.407 +*N optlc_net_124:31 *C 109.480 50.992 +*N optlc_net_124:32 *C 109.495 51.000 +*N optlc_net_124:33 *C 110.407 51.000 +*N optlc_net_124:34 *C 110.400 51.058 +*N optlc_net_124:35 *C 110.400 55.080 +*N optlc_net_124:36 *C 111.113 55.080 +*N optlc_net_124:37 *C 100.148 55.080 +*N optlc_net_124:38 *C 109.940 55.080 +*N optlc_net_124:39 *C 109.940 55.080 +*N optlc_net_124:40 *C 109.940 58.775 +*N optlc_net_124:41 *C 109.985 58.820 +*N optlc_net_124:42 *C 110.363 58.820 + +*CAP +0 optlc_118:HI 1e-06 +1 mux_right_track_24\/mux_l1_in_3_:A0 1e-06 +2 mux_right_track_4\/mux_l2_in_3_:A0 1e-06 +3 mux_right_track_16\/mux_l1_in_3_:A0 1e-06 +4 mux_top_track_8\/mux_l2_in_1_:A0 1e-06 +5 mux_right_track_8\/mux_l2_in_3_:A0 1e-06 +6 mux_top_track_10\/mux_l2_in_1_:A0 1e-06 +7 mux_right_track_0\/mux_l2_in_3_:A0 1e-06 +8 optlc_net_124:8 5.811046e-05 +9 optlc_net_124:9 6.277765e-05 +10 optlc_net_124:10 0.0003199774 +11 optlc_net_124:11 0.0003770104 +12 optlc_net_124:12 9.18057e-05 +13 optlc_net_124:13 9.18057e-05 +14 optlc_net_124:14 0.0005745126 +15 optlc_net_124:15 5.124117e-05 +16 optlc_net_124:16 5.453762e-05 +17 optlc_net_124:17 0.0001678533 +18 optlc_net_124:18 0.0001992704 +19 optlc_net_124:19 0.0005488968 +20 optlc_net_124:20 0.0004802117 +21 optlc_net_124:21 0.0001691176 +22 optlc_net_124:22 0.0001691176 +23 optlc_net_124:23 9.754174e-05 +24 optlc_net_124:24 4.965308e-05 +25 optlc_net_124:25 5.360162e-05 +26 optlc_net_124:26 0.0005598313 +27 optlc_net_124:27 0.0006930865 +28 optlc_net_124:28 0.0003077638 +29 optlc_net_124:29 0.0003077638 +30 optlc_net_124:30 0.0008858192 +31 optlc_net_124:31 0.0008858192 +32 optlc_net_124:32 1.574968e-05 +33 optlc_net_124:33 0.0004959614 +34 optlc_net_124:34 0.0002176514 +35 optlc_net_124:35 0.0002522422 +36 optlc_net_124:36 9.835599e-05 +37 optlc_net_124:37 0.0005223479 +38 optlc_net_124:38 0.0006562636 +39 optlc_net_124:39 0.0002539625 +40 optlc_net_124:40 0.0002193717 +41 optlc_net_124:41 5.708221e-05 +42 optlc_net_124:42 5.708221e-05 +43 optlc_net_124:32 chanx_right_in[18]:28 7.088273e-05 +44 optlc_net_124:33 chanx_right_in[18] 7.088273e-05 +45 optlc_net_124:33 chanx_right_in[18]:28 0.0009596564 +46 optlc_net_124:20 chanx_right_in[18] 0.0009596564 +47 optlc_net_124:32 mux_tree_tapbuf_size8_1_sram[1]:25 7.290413e-05 +48 optlc_net_124:33 mux_tree_tapbuf_size8_1_sram[1]:24 7.290413e-05 +49 optlc_net_124:33 mux_tree_tapbuf_size8_1_sram[1]:25 0.0004340464 +50 optlc_net_124:20 mux_tree_tapbuf_size8_1_sram[1]:24 0.0004340464 +51 optlc_net_124:16 mux_tree_tapbuf_size8_1_sram[1]:15 1.762777e-06 +52 optlc_net_124:15 mux_tree_tapbuf_size8_1_sram[1]:14 1.762777e-06 +53 optlc_net_124:38 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001185816 +54 optlc_net_124:37 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001185816 +55 optlc_net_124:38 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 8.438774e-05 +56 optlc_net_124:37 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 8.438774e-05 +57 optlc_net_124:34 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 1.942037e-06 +58 optlc_net_124:39 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 3.347237e-05 +59 optlc_net_124:40 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 3.347237e-05 +60 optlc_net_124:35 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 1.942037e-06 +61 optlc_net_124:34 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.035045e-05 +62 optlc_net_124:39 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.618485e-06 +63 optlc_net_124:40 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.618485e-06 +64 optlc_net_124:35 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.035045e-05 + +*RES +0 optlc_118:HI optlc_net_124:42 0.152 +1 optlc_net_124:8 mux_right_track_0\/mux_l2_in_3_:A0 0.152 +2 optlc_net_124:9 optlc_net_124:8 0.0001005435 +3 optlc_net_124:10 optlc_net_124:9 0.0045 +4 optlc_net_124:32 optlc_net_124:31 0.00341 +5 optlc_net_124:31 optlc_net_124:30 0.002128317 +6 optlc_net_124:29 optlc_net_124:28 0.0004280916 +7 optlc_net_124:30 optlc_net_124:29 0.00341 +8 optlc_net_124:27 optlc_net_124:26 0.009674109 +9 optlc_net_124:27 optlc_net_124:23 0.001477679 +10 optlc_net_124:28 optlc_net_124:27 0.00341 +11 optlc_net_124:34 optlc_net_124:33 0.00341 +12 optlc_net_124:33 optlc_net_124:32 0.0001340234 +13 optlc_net_124:33 optlc_net_124:20 0.00259205 +14 optlc_net_124:38 optlc_net_124:37 0.008743304 +15 optlc_net_124:38 optlc_net_124:36 0.001046875 +16 optlc_net_124:39 optlc_net_124:38 0.0045 +17 optlc_net_124:39 optlc_net_124:35 0.0004107143 +18 optlc_net_124:25 optlc_net_124:24 9.239132e-05 +19 optlc_net_124:26 optlc_net_124:25 0.0045 +20 optlc_net_124:24 mux_right_track_16\/mux_l1_in_3_:A0 0.152 +21 optlc_net_124:41 optlc_net_124:40 0.0045 +22 optlc_net_124:40 optlc_net_124:39 0.003299107 +23 optlc_net_124:42 optlc_net_124:41 0.0003370536 +24 optlc_net_124:36 mux_right_track_4\/mux_l2_in_3_:A0 0.152 +25 optlc_net_124:37 mux_right_track_24\/mux_l1_in_3_:A0 0.152 +26 optlc_net_124:13 optlc_net_124:12 0.0008995536 +27 optlc_net_124:14 optlc_net_124:13 0.0045 +28 optlc_net_124:14 optlc_net_124:11 0.0008214285 +29 optlc_net_124:12 mux_top_track_10\/mux_l2_in_1_:A0 0.152 +30 optlc_net_124:22 optlc_net_124:21 0.002234375 +31 optlc_net_124:23 optlc_net_124:22 0.0045 +32 optlc_net_124:21 mux_top_track_8\/mux_l2_in_1_:A0 0.152 +33 optlc_net_124:19 optlc_net_124:18 0.0004107143 +34 optlc_net_124:19 optlc_net_124:14 0.0085 +35 optlc_net_124:20 optlc_net_124:19 0.00341 +36 optlc_net_124:16 optlc_net_124:15 0.0001576087 +37 optlc_net_124:17 optlc_net_124:16 0.0045 +38 optlc_net_124:15 mux_right_track_8\/mux_l2_in_3_:A0 0.152 +39 optlc_net_124:35 optlc_net_124:34 0.003591518 +40 optlc_net_124:18 optlc_net_124:17 0.002388393 +41 optlc_net_124:11 optlc_net_124:10 0.004816964 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.005058447 //LENGTH 28.790 LUMPCC 0.002550673 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 83.085 69.020 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 102.680 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 102.642 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 101.705 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 101.660 61.585 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 101.660 63.875 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 101.615 63.920 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 96.645 63.920 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 96.600 63.965 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 96.600 68.623 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 96.593 68.680 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 83.267 68.680 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 83.260 68.680 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 83.260 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 83.260 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:15 *C 83.085 69.020 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.96735e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.96735e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001045815 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001045815 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001980649 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001980649 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003149349 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003149349 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0004450497 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0004450497 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:12 5.77284e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:13 5.371178e-05 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:14 6.378665e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:15 6.59377e-05 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chanx_left_in[2]:14 0.0001523913 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chanx_left_in[2]:18 0.0001523913 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chanx_left_in[10]:18 0.000358452 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chanx_left_in[10]:19 0.000358452 +20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_44_[0]:6 0.0001981836 +21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_44_[0]:5 0.0001981836 +22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.212322e-05 +23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.212322e-05 +24 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.155015e-05 +25 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.155015e-05 +26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004926364 +27 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0004926364 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:15 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370537 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0044375 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004158483 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.00341 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.00341 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002087583 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0045 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001634616 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:14 9.51087e-05 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002399163 //LENGTH 17.220 LUMPCC 0.0005982787 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 29.155 52.700 +*I mux_left_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 18.305 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 18.343 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 28.475 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 28.520 47.305 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 28.520 52.655 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 28.565 52.700 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 29.117 52.700 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004875512 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0004875512 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003382752 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003382752 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.361579e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.361579e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 left_top_grid_pin_43_[0]:10 7.828039e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 left_top_grid_pin_43_[0]:9 7.828039e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 left_top_grid_pin_48_[0]:7 0.000113626 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 left_top_grid_pin_48_[0]:6 0.000113626 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:15 0.0001072329 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:16 0.0001072329 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.009046875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004776786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006161741 //LENGTH 5.085 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_2_:X O *L 0 *C 24.665 63.580 +*I mux_left_track_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 26.780 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 26.742 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 25.805 61.540 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 25.760 61.585 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 25.760 63.535 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 25.715 63.580 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 24.703 63.580 + +*CAP +0 mux_left_track_1\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 7.968524e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.968524e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001379979 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001379979 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.940397e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.940397e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_1\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008370536 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001741071 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET ropt_net_163 0.001121477 //LENGTH 8.615 LUMPCC 9.923964e-05 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 7.095 58.820 +*I ropt_mt_inst_789:A I *L 0.001767 *C 3.220 61.200 +*N ropt_net_163:2 *C 3.258 61.200 +*N ropt_net_163:3 *C 3.635 61.200 +*N ropt_net_163:4 *C 3.680 61.155 +*N ropt_net_163:5 *C 3.680 60.565 +*N ropt_net_163:6 *C 3.725 60.520 +*N ropt_net_163:7 *C 5.475 60.520 +*N ropt_net_163:8 *C 5.520 60.475 +*N ropt_net_163:9 *C 5.520 58.525 +*N ropt_net_163:10 *C 5.520 58.480 +*N ropt_net_163:11 *C 5.520 58.820 +*N ropt_net_163:12 *C 7.058 58.820 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_163:2 4.355994e-05 +3 ropt_net_163:3 4.355994e-05 +4 ropt_net_163:4 5.517147e-05 +5 ropt_net_163:5 5.517147e-05 +6 ropt_net_163:6 0.0001334849 +7 ropt_net_163:7 0.0001334849 +8 ropt_net_163:8 0.0001487365 +9 ropt_net_163:9 0.0001487365 +10 ropt_net_163:10 5.878273e-05 +11 ropt_net_163:11 0.0001118402 +12 ropt_net_163:12 8.770847e-05 +13 ropt_net_163:10 ropt_net_129:3 2.759449e-07 +14 ropt_net_163:10 ropt_net_129:4 5.201113e-06 +15 ropt_net_163:12 ropt_net_129:4 2.361737e-06 +16 ropt_net_163:12 ropt_net_129:6 4.178103e-05 +17 ropt_net_163:11 ropt_net_129:2 2.759449e-07 +18 ropt_net_163:11 ropt_net_129:3 2.361737e-06 +19 ropt_net_163:11 ropt_net_129:5 4.698214e-05 + +*RES +0 ropt_mt_inst_752:X ropt_net_163:12 0.152 +1 ropt_net_163:2 ropt_mt_inst_789:A 0.152 +2 ropt_net_163:3 ropt_net_163:2 0.0003370536 +3 ropt_net_163:4 ropt_net_163:3 0.0045 +4 ropt_net_163:6 ropt_net_163:5 0.0045 +5 ropt_net_163:5 ropt_net_163:4 0.0005267857 +6 ropt_net_163:7 ropt_net_163:6 0.0015625 +7 ropt_net_163:8 ropt_net_163:7 0.0045 +8 ropt_net_163:10 ropt_net_163:9 0.0045 +9 ropt_net_163:9 ropt_net_163:8 0.001741072 +10 ropt_net_163:12 ropt_net_163:11 0.001372768 +11 ropt_net_163:11 ropt_net_163:10 0.0003035715 + +*END + +*D_NET chanx_right_out[6] 0.0007208567 //LENGTH 5.545 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 136.160 28.560 +*P chanx_right_out[6] O *L 0.7423 *C 140.382 28.560 +*N chanx_right_out[6]:2 *C 140.300 28.560 +*N chanx_right_out[6]:3 *C 140.300 28.560 +*N chanx_right_out[6]:4 *C 140.300 28.900 +*N chanx_right_out[6]:5 *C 140.255 28.900 +*N chanx_right_out[6]:6 *C 136.160 28.900 +*N chanx_right_out[6]:7 *C 136.160 28.560 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 chanx_right_out[6] 2.533276e-05 +2 chanx_right_out[6]:2 2.533276e-05 +3 chanx_right_out[6]:3 4.782937e-05 +4 chanx_right_out[6]:4 4.448426e-05 +5 chanx_right_out[6]:5 0.0002510737 +6 chanx_right_out[6]:6 0.0002758927 +7 chanx_right_out[6]:7 4.991108e-05 + +*RES +0 ropt_mt_inst_762:X chanx_right_out[6]:7 0.152 +1 chanx_right_out[6]:7 chanx_right_out[6]:6 0.0003035715 +2 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +3 chanx_right_out[6]:4 chanx_right_out[6]:3 0.0001634615 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 2.35e-05 +6 chanx_right_out[6]:6 chanx_right_out[6]:5 0.00365625 + +*END + +*D_NET ropt_net_169 0.0004845807 //LENGTH 3.600 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_767:X O *L 0 *C 134.120 23.800 +*I ropt_mt_inst_796:A I *L 0.001767 *C 134.780 25.840 +*N ropt_net_169:2 *C 134.780 25.825 +*N ropt_net_169:3 *C 134.780 25.500 +*N ropt_net_169:4 *C 134.780 25.455 +*N ropt_net_169:5 *C 134.780 23.845 +*N ropt_net_169:6 *C 134.735 23.800 +*N ropt_net_169:7 *C 134.157 23.800 + +*CAP +0 ropt_mt_inst_767:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_169:2 3.810092e-05 +3 ropt_net_169:3 7.354694e-05 +4 ropt_net_169:4 0.0001211608 +5 ropt_net_169:5 0.0001211608 +6 ropt_net_169:6 6.430567e-05 +7 ropt_net_169:7 6.430567e-05 + +*RES +0 ropt_mt_inst_767:X ropt_net_169:7 0.152 +1 ropt_net_169:2 ropt_mt_inst_796:A 0.152 +2 ropt_net_169:3 ropt_net_169:2 0.0001766304 +3 ropt_net_169:4 ropt_net_169:3 0.0045 +4 ropt_net_169:6 ropt_net_169:5 0.0045 +5 ropt_net_169:5 ropt_net_169:4 0.0014375 +6 ropt_net_169:7 ropt_net_169:6 0.000515625 + +*END + +*D_NET chanx_left_out[9] 0.001126742 //LENGTH 8.540 LUMPCC 0.000225762 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 6.900 36.040 +*P chanx_left_out[9] O *L 0.7423 *C 1.298 34.000 +*N chanx_left_out[9]:2 *C 1.380 34.000 +*N chanx_left_out[9]:3 *C 1.380 34.058 +*N chanx_left_out[9]:4 *C 1.380 35.995 +*N chanx_left_out[9]:5 *C 1.425 36.040 +*N chanx_left_out[9]:6 *C 6.863 36.040 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 chanx_left_out[9] 2.801801e-05 +2 chanx_left_out[9]:2 2.801801e-05 +3 chanx_left_out[9]:3 0.0001133756 +4 chanx_left_out[9]:4 0.0001133756 +5 chanx_left_out[9]:5 0.0003085965 +6 chanx_left_out[9]:6 0.0003085965 +7 chanx_left_out[9]:6 ropt_net_145:7 0.000112881 +8 chanx_left_out[9]:5 ropt_net_145:6 0.000112881 + +*RES +0 ropt_mt_inst_790:X chanx_left_out[9]:6 0.152 +1 chanx_left_out[9]:6 chanx_left_out[9]:5 0.004854911 +2 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +3 chanx_left_out[9]:4 chanx_left_out[9]:3 0.001729911 +4 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +5 chanx_left_out[9]:2 chanx_left_out[9] 2.35e-05 + +*END + +*D_NET chanx_left_out[10] 0.001581958 //LENGTH 12.030 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 7.095 25.500 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 20.400 +*N chanx_left_out[10]:2 *C 7.353 20.400 +*N chanx_left_out[10]:3 *C 7.360 20.457 +*N chanx_left_out[10]:4 *C 7.360 25.455 +*N chanx_left_out[10]:5 *C 7.360 25.500 +*N chanx_left_out[10]:6 *C 7.095 25.500 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chanx_left_out[10] 0.0004369008 +2 chanx_left_out[10]:2 0.0004369008 +3 chanx_left_out[10]:3 0.0002871184 +4 chanx_left_out[10]:4 0.0002871184 +5 chanx_left_out[10]:5 6.463494e-05 +6 chanx_left_out[10]:6 6.828521e-05 + +*RES +0 ropt_mt_inst_804:X chanx_left_out[10]:6 0.152 +1 chanx_left_out[10]:6 chanx_left_out[10]:5 0.0001440218 +2 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0045 +3 chanx_left_out[10]:4 chanx_left_out[10]:3 0.004462054 +4 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +5 chanx_left_out[10]:2 chanx_left_out[10] 0.0009591916 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..916ff30 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,47140 @@ +*SPEF "1481-1998" +*DESIGN "sb_1__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 2.300 27.880 +chany_top_in[0] I *C 80.500 129.880 +chany_top_in[1] I *C 57.500 129.880 +chany_top_in[2] I *C 82.340 129.880 +chany_top_in[3] I *C 74.060 129.880 +chany_top_in[4] I *C 51.980 129.880 +chany_top_in[5] I *C 60.260 129.880 +chany_top_in[6] I *C 74.980 129.880 +chany_top_in[7] I *C 66.700 129.880 +chany_top_in[8] I *C 72.220 129.880 +chany_top_in[9] I *C 67.620 129.880 +chany_top_in[10] I *C 73.140 129.880 +chany_top_in[11] I *C 75.900 129.880 +chany_top_in[12] I *C 52.900 129.880 +chany_top_in[13] I *C 63.480 129.880 +chany_top_in[14] I *C 54.740 129.880 +chany_top_in[15] I *C 53.820 129.880 +chany_top_in[16] I *C 69.460 129.880 +chany_top_in[17] I *C 81.420 129.880 +chany_top_in[18] I *C 84.640 129.880 +chany_top_in[19] I *C 59.340 129.880 +top_left_grid_pin_34_[0] I *C 31.740 129.880 +top_left_grid_pin_35_[0] I *C 32.660 129.880 +top_left_grid_pin_36_[0] I *C 29.210 127.160 +top_left_grid_pin_37_[0] I *C 30.820 129.880 +top_left_grid_pin_38_[0] I *C 29.210 125.120 +top_left_grid_pin_39_[0] I *C 29.210 123.760 +top_left_grid_pin_40_[0] I *C 29.210 122.400 +top_left_grid_pin_41_[0] I *C 29.210 117.640 +chanx_right_in[0] I *C 140.990 48.960 +chanx_right_in[1] I *C 140.990 99.280 +chanx_right_in[2] I *C 140.990 55.760 +chanx_right_in[3] I *C 140.990 38.080 +chanx_right_in[4] I *C 140.990 93.840 +chanx_right_in[5] I *C 140.990 95.200 +chanx_right_in[6] I *C 140.990 77.520 +chanx_right_in[7] I *C 140.990 69.360 +chanx_right_in[8] I *C 140.990 44.880 +chanx_right_in[9] I *C 140.990 51.000 +chanx_right_in[10] I *C 140.990 36.720 +chanx_right_in[11] I *C 140.990 43.520 +chanx_right_in[12] I *C 140.990 96.560 +chanx_right_in[13] I *C 140.990 32.640 +chanx_right_in[14] I *C 140.990 91.120 +chanx_right_in[15] I *C 140.990 57.120 +chanx_right_in[16] I *C 140.990 39.440 +chanx_right_in[17] I *C 140.990 34.000 +chanx_right_in[18] I *C 140.990 65.280 +chanx_right_in[19] I *C 140.990 31.280 +right_top_grid_pin_42_[0] I *C 138.460 102.680 +right_top_grid_pin_43_[0] I *C 112.470 126.480 +right_top_grid_pin_44_[0] I *C 139.380 102.680 +right_top_grid_pin_45_[0] I *C 137.540 102.680 +right_top_grid_pin_46_[0] I *C 112.470 119.000 +right_top_grid_pin_47_[0] I *C 112.470 117.640 +right_top_grid_pin_48_[0] I *C 135.700 102.680 +right_top_grid_pin_49_[0] I *C 136.620 102.680 +chany_bottom_in[0] I *C 82.340 0.680 +chany_bottom_in[1] I *C 67.160 0.680 +chany_bottom_in[2] I *C 81.420 0.680 +chany_bottom_in[3] I *C 88.320 0.680 +chany_bottom_in[4] I *C 65.320 0.680 +chany_bottom_in[5] I *C 75.900 0.680 +chany_bottom_in[6] I *C 94.300 0.680 +chany_bottom_in[7] I *C 87.400 0.680 +chany_bottom_in[8] I *C 77.740 0.680 +chany_bottom_in[9] I *C 84.180 0.680 +chany_bottom_in[10] I *C 62.560 0.680 +chany_bottom_in[11] I *C 86.480 0.680 +chany_bottom_in[12] I *C 79.580 0.680 +chany_bottom_in[13] I *C 68.080 0.680 +chany_bottom_in[14] I *C 66.240 0.680 +chany_bottom_in[15] I *C 53.360 0.680 +chany_bottom_in[16] I *C 76.820 0.680 +chany_bottom_in[17] I *C 69.920 0.680 +chany_bottom_in[18] I *C 57.500 0.680 +chany_bottom_in[19] I *C 78.660 0.680 +bottom_left_grid_pin_34_[0] I *C 29.210 10.200 +bottom_left_grid_pin_35_[0] I *C 29.210 8.160 +bottom_left_grid_pin_36_[0] I *C 29.210 6.800 +bottom_left_grid_pin_37_[0] I *C 29.210 3.400 +bottom_left_grid_pin_38_[0] I *C 29.210 4.760 +bottom_left_grid_pin_39_[0] I *C 29.210 11.560 +bottom_left_grid_pin_40_[0] I *C 29.210 12.920 +bottom_left_grid_pin_41_[0] I *C 29.210 14.280 +chanx_left_in[0] I *C 0.690 76.160 +chanx_left_in[1] I *C 0.690 38.080 +chanx_left_in[2] I *C 0.690 35.360 +chanx_left_in[3] I *C 0.690 39.440 +chanx_left_in[4] I *C 0.690 85.680 +chanx_left_in[5] I *C 0.690 87.040 +chanx_left_in[6] I *C 0.690 34.000 +chanx_left_in[7] I *C 0.690 42.160 +chanx_left_in[8] I *C 0.690 43.520 +chanx_left_in[9] I *C 0.690 72.080 +chanx_left_in[10] I *C 0.690 59.160 +chanx_left_in[11] I *C 0.690 36.720 +chanx_left_in[12] I *C 0.690 97.920 +chanx_left_in[13] I *C 0.690 93.840 +chanx_left_in[14] I *C 0.690 92.480 +chanx_left_in[15] I *C 0.690 77.520 +chanx_left_in[16] I *C 0.690 51.680 +chanx_left_in[17] I *C 0.690 55.760 +chanx_left_in[18] I *C 0.690 68.000 +chanx_left_in[19] I *C 0.690 46.240 +left_top_grid_pin_42_[0] I *C 7.360 102.680 +left_top_grid_pin_43_[0] I *C 29.210 119.000 +left_top_grid_pin_44_[0] I *C 4.140 102.680 +left_top_grid_pin_45_[0] I *C 5.060 102.680 +left_top_grid_pin_46_[0] I *C 2.300 102.680 +left_top_grid_pin_47_[0] I *C 3.220 102.680 +left_top_grid_pin_48_[0] I *C 11.500 102.680 +left_top_grid_pin_49_[0] I *C 10.580 102.680 +ccff_head[0] I *C 140.990 88.400 +chany_top_out[0] O *C 76.820 129.880 +chany_top_out[1] O *C 61.180 129.880 +chany_top_out[2] O *C 77.740 129.880 +chany_top_out[3] O *C 71.300 129.880 +chany_top_out[4] O *C 98.900 129.880 +chany_top_out[5] O *C 83.720 129.880 +chany_top_out[6] O *C 70.380 129.880 +chany_top_out[7] O *C 50.140 129.880 +chany_top_out[8] O *C 68.540 129.880 +chany_top_out[9] O *C 58.420 129.880 +chany_top_out[10] O *C 96.600 129.880 +chany_top_out[11] O *C 93.840 129.880 +chany_top_out[12] O *C 79.580 129.880 +chany_top_out[13] O *C 64.400 129.880 +chany_top_out[14] O *C 97.520 129.880 +chany_top_out[15] O *C 51.060 129.880 +chany_top_out[16] O *C 86.940 129.880 +chany_top_out[17] O *C 62.100 129.880 +chany_top_out[18] O *C 95.680 129.880 +chany_top_out[19] O *C 78.660 129.880 +chanx_right_out[0] O *C 140.990 84.320 +chanx_right_out[1] O *C 140.990 82.960 +chanx_right_out[2] O *C 140.990 62.560 +chanx_right_out[3] O *C 140.990 74.120 +chanx_right_out[4] O *C 140.990 80.240 +chanx_right_out[5] O *C 140.990 72.080 +chanx_right_out[6] O *C 140.990 58.480 +chanx_right_out[7] O *C 140.990 35.360 +chanx_right_out[8] O *C 140.990 46.240 +chanx_right_out[9] O *C 140.990 63.920 +chanx_right_out[10] O *C 140.990 61.200 +chanx_right_out[11] O *C 140.990 78.880 +chanx_right_out[12] O *C 140.990 42.160 +chanx_right_out[13] O *C 140.990 85.680 +chanx_right_out[14] O *C 140.990 47.600 +chanx_right_out[15] O *C 140.990 68.000 +chanx_right_out[16] O *C 140.990 40.800 +chanx_right_out[17] O *C 140.990 66.640 +chanx_right_out[18] O *C 140.990 52.360 +chanx_right_out[19] O *C 140.990 89.760 +chany_bottom_out[0] O *C 83.260 0.680 +chany_bottom_out[1] O *C 59.800 0.680 +chany_bottom_out[2] O *C 52.440 0.680 +chany_bottom_out[3] O *C 69.000 0.680 +chany_bottom_out[4] O *C 96.600 0.680 +chany_bottom_out[5] O *C 71.760 0.680 +chany_bottom_out[6] O *C 74.980 0.680 +chany_bottom_out[7] O *C 60.720 0.680 +chany_bottom_out[8] O *C 63.480 0.680 +chany_bottom_out[9] O *C 54.280 0.680 +chany_bottom_out[10] O *C 93.380 0.680 +chany_bottom_out[11] O *C 74.060 0.680 +chany_bottom_out[12] O *C 80.500 0.680 +chany_bottom_out[13] O *C 61.640 0.680 +chany_bottom_out[14] O *C 97.520 0.680 +chany_bottom_out[15] O *C 55.200 0.680 +chany_bottom_out[16] O *C 64.400 0.680 +chany_bottom_out[17] O *C 58.880 0.680 +chany_bottom_out[18] O *C 73.140 0.680 +chany_bottom_out[19] O *C 70.840 0.680 +chanx_left_out[0] O *C 0.690 61.200 +chanx_left_out[1] O *C 0.690 81.600 +chanx_left_out[2] O *C 0.690 82.960 +chanx_left_out[3] O *C 0.690 74.800 +chanx_left_out[4] O *C 0.690 80.240 +chanx_left_out[5] O *C 0.690 47.600 +chanx_left_out[6] O *C 0.690 50.320 +chanx_left_out[7] O *C 0.690 65.960 +chanx_left_out[8] O *C 0.690 48.960 +chanx_left_out[9] O *C 0.690 69.360 +chanx_left_out[10] O *C 0.690 53.040 +chanx_left_out[11] O *C 0.690 96.560 +chanx_left_out[12] O *C 0.690 44.880 +chanx_left_out[13] O *C 0.690 99.280 +chanx_left_out[14] O *C 0.690 54.400 +chanx_left_out[15] O *C 0.690 40.800 +chanx_left_out[16] O *C 0.690 31.960 +chanx_left_out[17] O *C 0.690 88.400 +chanx_left_out[18] O *C 0.690 70.720 +chanx_left_out[19] O *C 0.690 91.120 +ccff_tail[0] O *C 0.690 64.600 +VDD I *C 70.840 65.280 +VSS I *C 70.840 65.280 + +*D_NET chany_top_in[2] 0.02469542 //LENGTH 176.305 LUMPCC 0.006814743 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 82.340 129.270 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 81.520 99.620 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 79.580 25.500 +*I ropt_mt_inst_797:A I *L 0.001767 *C 67.915 4.080 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 80.815 91.460 +*N chany_top_in[2]:5 *C 80.815 91.460 +*N chany_top_in[2]:6 *C 80.815 91.120 +*N chany_top_in[2]:7 *C 80.085 91.120 +*N chany_top_in[2]:8 *C 80.040 91.165 +*N chany_top_in[2]:9 *C 67.953 4.080 +*N chany_top_in[2]:10 *C 68.955 4.080 +*N chany_top_in[2]:11 *C 69.000 4.125 +*N chany_top_in[2]:12 *C 69.000 10.155 +*N chany_top_in[2]:13 *C 69.045 10.200 +*N chany_top_in[2]:14 *C 79.995 10.200 +*N chany_top_in[2]:15 *C 80.040 10.245 +*N chany_top_in[2]:16 *C 79.618 25.500 +*N chany_top_in[2]:17 *C 79.995 25.500 +*N chany_top_in[2]:18 *C 80.040 25.500 +*N chany_top_in[2]:19 *C 80.040 25.103 +*N chany_top_in[2]:20 *C 80.047 25.160 +*N chany_top_in[2]:21 *C 92.900 25.160 +*N chany_top_in[2]:22 *C 92.920 25.168 +*N chany_top_in[2]:23 *C 92.920 74.995 +*N chany_top_in[2]:24 *C 92.920 94.513 +*N chany_top_in[2]:25 *C 92.900 94.520 +*N chany_top_in[2]:26 *C 80.047 94.520 +*N chany_top_in[2]:27 *C 80.040 94.520 +*N chany_top_in[2]:28 *C 81.483 99.620 +*N chany_top_in[2]:29 *C 80.085 99.620 +*N chany_top_in[2]:30 *C 80.040 99.620 +*N chany_top_in[2]:31 *C 80.040 102.635 +*N chany_top_in[2]:32 *C 80.085 102.680 +*N chany_top_in[2]:33 *C 82.295 102.680 +*N chany_top_in[2]:34 *C 82.340 102.725 + +*CAP +0 chany_top_in[2] 0.001584059 +1 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +3 ropt_mt_inst_797:A 1e-06 +4 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +5 chany_top_in[2]:5 5.375805e-05 +6 chany_top_in[2]:6 7.767185e-05 +7 chany_top_in[2]:7 5.520241e-05 +8 chany_top_in[2]:8 0.0001475153 +9 chany_top_in[2]:9 9.207052e-05 +10 chany_top_in[2]:10 9.207052e-05 +11 chany_top_in[2]:11 0.0003540082 +12 chany_top_in[2]:12 0.0003540082 +13 chany_top_in[2]:13 0.0007845486 +14 chany_top_in[2]:14 0.0007845486 +15 chany_top_in[2]:15 0.0005591348 +16 chany_top_in[2]:16 4.539983e-05 +17 chany_top_in[2]:17 4.539983e-05 +18 chany_top_in[2]:18 4.488918e-05 +19 chany_top_in[2]:19 0.0005743859 +20 chany_top_in[2]:20 0.0007878728 +21 chany_top_in[2]:21 0.0007878728 +22 chany_top_in[2]:22 0.001827618 +23 chany_top_in[2]:23 0.003147403 +24 chany_top_in[2]:24 0.001319785 +25 chany_top_in[2]:25 0.0007166327 +26 chany_top_in[2]:26 0.0007166327 +27 chany_top_in[2]:27 0.0003499673 +28 chany_top_in[2]:28 0.0001282374 +29 chany_top_in[2]:29 0.0001282374 +30 chany_top_in[2]:30 0.0003106133 +31 chany_top_in[2]:31 0.0001161626 +32 chany_top_in[2]:32 0.0001534547 +33 chany_top_in[2]:33 0.0001534547 +34 chany_top_in[2]:34 0.001584059 +35 chany_top_in[2]:17 chany_top_in[12]:19 2.618177e-08 +36 chany_top_in[2]:17 chany_top_in[12]:21 3.613084e-06 +37 chany_top_in[2]:18 chany_top_in[12]:18 8.733944e-06 +38 chany_top_in[2]:16 chany_top_in[12]:8 2.618177e-08 +39 chany_top_in[2]:16 chany_top_in[12]:20 3.613084e-06 +40 chany_top_in[2]:29 chany_top_in[12]:6 1.446515e-06 +41 chany_top_in[2]:30 chany_top_in[12]:42 9.608717e-06 +42 chany_top_in[2]:28 chany_top_in[12]:5 1.446515e-06 +43 chany_top_in[2]:19 chany_top_in[12]:18 0.0004073959 +44 chany_top_in[2]:19 chany_top_in[12]:17 8.733944e-06 +45 chany_top_in[2]:32 chany_top_in[12]:41 1.962716e-05 +46 chany_top_in[2]:31 chany_top_in[12]:43 9.608717e-06 +47 chany_top_in[2]:33 chany_top_in[12]:40 1.962716e-05 +48 chany_top_in[2]:15 chany_top_in[12]:17 0.0004073959 +49 chany_top_in[2]:12 chany_top_in[12]:11 7.193657e-06 +50 chany_top_in[2]:10 chany_top_in[12]:14 1.726653e-05 +51 chany_top_in[2]:11 chany_top_in[12]:12 7.193657e-06 +52 chany_top_in[2]:9 chany_top_in[12]:13 1.726653e-05 +53 chany_top_in[2]:20 chany_top_in[13]:11 8.855393e-05 +54 chany_top_in[2]:21 chany_top_in[13]:10 8.855393e-05 +55 chany_top_in[2]:25 chany_top_in[13]:26 0.0006464703 +56 chany_top_in[2]:26 chany_top_in[13]:27 0.0006464703 +57 chany_top_in[2]:22 chany_bottom_in[16]:29 0.0004583438 +58 chany_top_in[2]:22 chany_bottom_in[16]:30 0.0004279682 +59 chany_top_in[2]:24 chany_bottom_in[16]:19 9.597983e-06 +60 chany_top_in[2]:23 chany_bottom_in[16]:29 0.0004375662 +61 chany_top_in[2]:23 chany_bottom_in[16]:19 0.0004583438 +62 chany_top_in[2] chany_top_in[0] 1.23305e-05 +63 chany_top_in[2]:30 chany_top_in[0] 0.0001284423 +64 chany_top_in[2]:30 chany_top_in[0]:9 8.439695e-05 +65 chany_top_in[2]:27 chany_top_in[0] 8.885298e-05 +66 chany_top_in[2]:27 chany_top_in[0]:9 0.0001284423 +67 chany_top_in[2]:7 chany_top_in[0]:8 1.939454e-05 +68 chany_top_in[2]:8 chany_top_in[0]:9 8.885298e-05 +69 chany_top_in[2]:5 chany_top_in[0] 7.520107e-06 +70 chany_top_in[2]:31 chany_top_in[0] 8.439695e-05 +71 chany_top_in[2]:34 chany_top_in[0]:9 1.23305e-05 +72 chany_top_in[2]:6 chany_top_in[0]:7 1.939454e-05 +73 chany_top_in[2]:6 chany_top_in[0]:9 7.520107e-06 +74 chany_top_in[2]:22 chany_bottom_in[3]:27 0.0007637984 +75 chany_top_in[2]:22 chany_bottom_in[3]:26 7.16236e-05 +76 chany_top_in[2]:23 chany_bottom_in[3]:19 7.16236e-05 +77 chany_top_in[2]:23 chany_bottom_in[3]:26 0.0007637984 +78 chany_top_in[2]:30 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.950011e-05 +79 chany_top_in[2]:27 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.950011e-05 +80 chany_top_in[2]:12 ropt_net_207:9 6.56664e-05 +81 chany_top_in[2]:11 ropt_net_207:8 6.56664e-05 + +*RES +0 chany_top_in[2] chany_top_in[2]:34 0.02370089 +1 chany_top_in[2]:17 chany_top_in[2]:16 0.0003370536 +2 chany_top_in[2]:18 chany_top_in[2]:17 0.0045 +3 chany_top_in[2]:16 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +4 chany_top_in[2]:29 chany_top_in[2]:28 0.001247768 +5 chany_top_in[2]:30 chany_top_in[2]:29 0.0045 +6 chany_top_in[2]:30 chany_top_in[2]:27 0.004553571 +7 chany_top_in[2]:28 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +8 chany_top_in[2]:19 chany_top_in[2]:18 0.0001911058 +9 chany_top_in[2]:19 chany_top_in[2]:15 0.01326563 +10 chany_top_in[2]:20 chany_top_in[2]:19 0.00341 +11 chany_top_in[2]:21 chany_top_in[2]:20 0.002013558 +12 chany_top_in[2]:22 chany_top_in[2]:21 0.00341 +13 chany_top_in[2]:25 chany_top_in[2]:24 0.00341 +14 chany_top_in[2]:24 chany_top_in[2]:23 0.003057742 +15 chany_top_in[2]:27 chany_top_in[2]:26 0.00341 +16 chany_top_in[2]:27 chany_top_in[2]:8 0.002995536 +17 chany_top_in[2]:26 chany_top_in[2]:25 0.002013558 +18 chany_top_in[2]:7 chany_top_in[2]:6 0.0006517858 +19 chany_top_in[2]:8 chany_top_in[2]:7 0.0045 +20 chany_top_in[2]:5 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[2]:32 chany_top_in[2]:31 0.0045 +22 chany_top_in[2]:31 chany_top_in[2]:30 0.002691964 +23 chany_top_in[2]:33 chany_top_in[2]:32 0.001973214 +24 chany_top_in[2]:34 chany_top_in[2]:33 0.0045 +25 chany_top_in[2]:14 chany_top_in[2]:13 0.009776786 +26 chany_top_in[2]:15 chany_top_in[2]:14 0.0045 +27 chany_top_in[2]:13 chany_top_in[2]:12 0.0045 +28 chany_top_in[2]:12 chany_top_in[2]:11 0.005383928 +29 chany_top_in[2]:10 chany_top_in[2]:9 0.0008950893 +30 chany_top_in[2]:11 chany_top_in[2]:10 0.0045 +31 chany_top_in[2]:9 ropt_mt_inst_797:A 0.152 +32 chany_top_in[2]:6 chany_top_in[2]:5 0.0003035715 +33 chany_top_in[2]:23 chany_top_in[2]:22 0.007806308 + +*END + +*D_NET chanx_right_in[17] 0.0250247 //LENGTH 166.700 LUMPCC 0.0104281 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 140.450 34.000 +*I mux_bottom_track_17\/mux_l1_in_2_:A1 I *L 0.00198 *C 61.085 34.340 +*I mux_top_track_16\/mux_l1_in_2_:A1 I *L 0.00198 *C 56.025 58.140 +*I BUFT_P_133:A I *L 0.001776 *C 6.900 61.200 +*I mux_left_track_17\/mux_l1_in_2_:A1 I *L 0.00198 *C 61.640 50.660 +*N chanx_right_in[17]:5 *C 61.603 50.660 +*N chanx_right_in[17]:6 *C 61.180 50.660 +*N chanx_right_in[17]:7 *C 6.900 61.200 +*N chanx_right_in[17]:8 *C 6.900 61.155 +*N chanx_right_in[17]:9 *C 6.900 58.538 +*N chanx_right_in[17]:10 *C 6.908 58.480 +*N chanx_right_in[17]:11 *C 56.573 58.480 +*N chanx_right_in[17]:12 *C 56.580 58.480 +*N chanx_right_in[17]:13 *C 56.062 58.140 +*N chanx_right_in[17]:14 *C 56.535 58.140 +*N chanx_right_in[17]:15 *C 56.580 58.140 +*N chanx_right_in[17]:16 *C 57.040 58.140 +*N chanx_right_in[17]:17 *C 57.040 50.365 +*N chanx_right_in[17]:18 *C 57.085 50.320 +*N chanx_right_in[17]:19 *C 61.180 50.350 +*N chanx_right_in[17]:20 *C 61.180 50.275 +*N chanx_right_in[17]:21 *C 61.085 34.340 +*N chanx_right_in[17]:22 *C 61.180 34.340 +*N chanx_right_in[17]:23 *C 61.180 33.378 +*N chanx_right_in[17]:24 *C 61.188 33.320 +*N chanx_right_in[17]:25 *C 98.440 33.320 +*N chanx_right_in[17]:26 *C 98.440 34.000 + +*CAP +0 chanx_right_in[17] 0.001478091 +1 mux_bottom_track_17\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_16\/mux_l1_in_2_:A1 1e-06 +3 BUFT_P_133:A 1e-06 +4 mux_left_track_17\/mux_l1_in_2_:A1 1e-06 +5 chanx_right_in[17]:5 6.130184e-05 +6 chanx_right_in[17]:6 9.136946e-05 +7 chanx_right_in[17]:7 3.765919e-05 +8 chanx_right_in[17]:8 0.0001570123 +9 chanx_right_in[17]:9 0.0001570123 +10 chanx_right_in[17]:10 0.001790744 +11 chanx_right_in[17]:11 0.001790745 +12 chanx_right_in[17]:12 6.08517e-05 +13 chanx_right_in[17]:13 5.568166e-05 +14 chanx_right_in[17]:14 5.568166e-05 +15 chanx_right_in[17]:15 8.81809e-05 +16 chanx_right_in[17]:16 0.000517233 +17 chanx_right_in[17]:17 0.0004844207 +18 chanx_right_in[17]:18 0.0003454929 +19 chanx_right_in[17]:19 0.0003755605 +20 chanx_right_in[17]:20 0.0008732522 +21 chanx_right_in[17]:21 2.753157e-05 +22 chanx_right_in[17]:22 0.0009680741 +23 chanx_right_in[17]:23 6.112378e-05 +24 chanx_right_in[17]:24 0.001751811 +25 chanx_right_in[17]:25 0.001818747 +26 chanx_right_in[17]:26 0.001545027 +27 chanx_right_in[17] chanx_right_in[13] 4.943007e-05 +28 chanx_right_in[17] chanx_right_in[13]:35 0.0002275048 +29 chanx_right_in[17] chanx_right_in[13]:36 0.0004537681 +30 chanx_right_in[17]:23 chanx_right_in[13]:33 3.827572e-06 +31 chanx_right_in[17]:24 chanx_right_in[13]:34 0.0006232625 +32 chanx_right_in[17]:22 chanx_right_in[13]:29 3.827572e-06 +33 chanx_right_in[17]:22 chanx_right_in[13]:33 2.148792e-05 +34 chanx_right_in[17]:20 chanx_right_in[13]:29 2.148792e-05 +35 chanx_right_in[17]:25 chanx_right_in[13]:35 0.0006232625 +36 chanx_right_in[17]:26 chanx_right_in[13]:34 0.0002275048 +37 chanx_right_in[17]:26 chanx_right_in[13]:35 0.0004537681 +38 chanx_right_in[17]:26 chanx_right_in[13]:37 4.943007e-05 +39 chanx_right_in[17] chanx_left_in[6]:30 4.193445e-05 +40 chanx_right_in[17] chanx_left_in[6]:16 4.644439e-05 +41 chanx_right_in[17]:24 chanx_left_in[6]:32 0.0004852014 +42 chanx_right_in[17]:24 chanx_left_in[6]:31 0.0001929841 +43 chanx_right_in[17]:25 chanx_left_in[6]:30 0.0001929841 +44 chanx_right_in[17]:25 chanx_left_in[6]:31 0.0004852014 +45 chanx_right_in[17]:26 chanx_left_in[6]:26 4.644439e-05 +46 chanx_right_in[17]:26 chanx_left_in[6]:31 4.193445e-05 +47 chanx_right_in[17]:11 chanx_left_in[10]:28 7.143147e-05 +48 chanx_right_in[17]:11 chanx_left_in[10]:33 0.0007672836 +49 chanx_right_in[17]:10 chanx_left_in[10] 0.0007672836 +50 chanx_right_in[17]:10 chanx_left_in[10]:29 7.143147e-05 +51 chanx_right_in[17]:11 mux_tree_tapbuf_size10_11_sram[1]:26 3.811777e-05 +52 chanx_right_in[17]:11 mux_tree_tapbuf_size10_11_sram[1]:27 0.0005210789 +53 chanx_right_in[17]:10 mux_tree_tapbuf_size10_11_sram[1]:26 0.0005210789 +54 chanx_right_in[17]:10 mux_tree_tapbuf_size10_11_sram[1]:19 3.811777e-05 +55 chanx_right_in[17]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.001664885 +56 chanx_right_in[17]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001664885 +57 chanx_right_in[17]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.406566e-06 +58 chanx_right_in[17]:16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.406566e-06 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:26 0.006581566 +1 chanx_right_in[17]:5 mux_left_track_17\/mux_l1_in_2_:A1 0.152 +2 chanx_right_in[17]:12 chanx_right_in[17]:11 0.00341 +3 chanx_right_in[17]:11 chanx_right_in[17]:10 0.007780849 +4 chanx_right_in[17]:9 chanx_right_in[17]:8 0.002337054 +5 chanx_right_in[17]:10 chanx_right_in[17]:9 0.00341 +6 chanx_right_in[17]:7 BUFT_P_133:A 0.152 +7 chanx_right_in[17]:8 chanx_right_in[17]:7 0.0045 +8 chanx_right_in[17]:14 chanx_right_in[17]:13 0.000421875 +9 chanx_right_in[17]:15 chanx_right_in[17]:14 0.0045 +10 chanx_right_in[17]:15 chanx_right_in[17]:12 0.0001634616 +11 chanx_right_in[17]:13 mux_top_track_16\/mux_l1_in_2_:A1 0.152 +12 chanx_right_in[17]:23 chanx_right_in[17]:22 0.0008593751 +13 chanx_right_in[17]:24 chanx_right_in[17]:23 0.00341 +14 chanx_right_in[17]:21 mux_bottom_track_17\/mux_l1_in_2_:A1 0.152 +15 chanx_right_in[17]:22 chanx_right_in[17]:21 0.0045 +16 chanx_right_in[17]:22 chanx_right_in[17]:20 0.01422768 +17 chanx_right_in[17]:19 chanx_right_in[17]:18 0.00365625 +18 chanx_right_in[17]:19 chanx_right_in[17]:6 0.0002767857 +19 chanx_right_in[17]:20 chanx_right_in[17]:19 0.0045 +20 chanx_right_in[17]:18 chanx_right_in[17]:17 0.0045 +21 chanx_right_in[17]:17 chanx_right_in[17]:16 0.006941964 +22 chanx_right_in[17]:6 chanx_right_in[17]:5 0.0003772322 +23 chanx_right_in[17]:16 chanx_right_in[17]:15 0.0004107143 +24 chanx_right_in[17]:25 chanx_right_in[17]:24 0.005836224 +25 chanx_right_in[17]:26 chanx_right_in[17]:25 0.0001065333 + +*END + +*D_NET chany_bottom_in[4] 0.02108362 //LENGTH 157.180 LUMPCC 0.003187673 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 65.320 1.290 +*I mux_top_track_2\/mux_l1_in_3_:A0 I *L 0.001631 *C 63.310 91.800 +*I mux_left_track_3\/mux_l1_in_3_:A1 I *L 0.00198 *C 67.065 96.220 +*I BUFT_RR_90:A I *L 0.001776 *C 86.020 99.280 +*I mux_right_track_2\/mux_l1_in_3_:A0 I *L 0.001631 *C 111.035 97.240 +*N chany_bottom_in[4]:5 *C 110.998 97.240 +*N chany_bottom_in[4]:6 *C 106.305 97.240 +*N chany_bottom_in[4]:7 *C 106.260 97.285 +*N chany_bottom_in[4]:8 *C 106.260 98.543 +*N chany_bottom_in[4]:9 *C 106.253 98.600 +*N chany_bottom_in[4]:10 *C 86.028 98.600 +*N chany_bottom_in[4]:11 *C 86.020 98.657 +*N chany_bottom_in[4]:12 *C 86.020 99.280 +*N chany_bottom_in[4]:13 *C 86.020 99.280 +*N chany_bottom_in[4]:14 *C 86.020 101.943 +*N chany_bottom_in[4]:15 *C 86.013 102.000 +*N chany_bottom_in[4]:16 *C 65.788 102.000 +*N chany_bottom_in[4]:17 *C 65.780 101.943 +*N chany_bottom_in[4]:18 *C 67.028 96.220 +*N chany_bottom_in[4]:19 *C 65.825 96.220 +*N chany_bottom_in[4]:20 *C 65.780 96.265 +*N chany_bottom_in[4]:21 *C 65.320 96.220 +*N chany_bottom_in[4]:22 *C 63.348 91.800 +*N chany_bottom_in[4]:23 *C 65.275 91.800 +*N chany_bottom_in[4]:24 *C 65.320 91.800 +*N chany_bottom_in[4]:25 *C 65.320 51.290 + +*CAP +0 chany_bottom_in[4] 0.002599089 +1 mux_top_track_2\/mux_l1_in_3_:A0 1e-06 +2 mux_left_track_3\/mux_l1_in_3_:A1 1e-06 +3 BUFT_RR_90:A 1e-06 +4 mux_right_track_2\/mux_l1_in_3_:A0 1e-06 +5 chany_bottom_in[4]:5 0.0003441257 +6 chany_bottom_in[4]:6 0.0003441257 +7 chany_bottom_in[4]:7 9.656634e-05 +8 chany_bottom_in[4]:8 9.656634e-05 +9 chany_bottom_in[4]:9 0.001297168 +10 chany_bottom_in[4]:10 0.001297168 +11 chany_bottom_in[4]:11 4.691219e-05 +12 chany_bottom_in[4]:12 3.482484e-05 +13 chany_bottom_in[4]:13 0.0002293952 +14 chany_bottom_in[4]:14 0.0001521145 +15 chany_bottom_in[4]:15 0.001077797 +16 chany_bottom_in[4]:16 0.001077797 +17 chany_bottom_in[4]:17 0.0003985957 +18 chany_bottom_in[4]:18 0.0001191687 +19 chany_bottom_in[4]:19 0.0001191687 +20 chany_bottom_in[4]:20 0.0003762268 +21 chany_bottom_in[4]:21 0.0002794464 +22 chany_bottom_in[4]:22 0.0001613235 +23 chany_bottom_in[4]:23 0.0001613235 +24 chany_bottom_in[4]:24 0.002659862 +25 chany_bottom_in[4]:25 0.004923183 +26 chany_bottom_in[4]:16 chanx_right_in[5]:28 0.001065653 +27 chany_bottom_in[4]:15 chanx_right_in[5]:29 0.001065653 +28 chany_bottom_in[4]:10 chanx_right_in[5]:28 2.38331e-05 +29 chany_bottom_in[4]:10 chanx_right_in[5]:29 0.0001348352 +30 chany_bottom_in[4]:9 chanx_right_in[5]:29 2.38331e-05 +31 chany_bottom_in[4]:9 chanx_right_in[5]:30 0.0001348352 +32 chany_bottom_in[4] prog_clk[0]:350 0.0001341172 +33 chany_bottom_in[4]:10 prog_clk[0]:249 0.0001374097 +34 chany_bottom_in[4]:9 prog_clk[0]:248 0.0001374097 +35 chany_bottom_in[4]:25 prog_clk[0]:351 0.0001341172 +36 chany_bottom_in[4]:20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.567338e-05 +37 chany_bottom_in[4]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.567338e-05 +38 chany_bottom_in[4]:24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.231496e-05 +39 chany_bottom_in[4]:25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.231496e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:25 0.04464286 +1 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.00341 +2 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.003168583 +3 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.002377232 +4 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.00341 +5 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.00341 +6 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.003168583 +7 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.001122768 +8 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.00341 +9 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.004189732 +10 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.0045 +11 chany_bottom_in[4]:5 mux_right_track_2\/mux_l1_in_3_:A0 0.152 +12 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.001073661 +13 chany_bottom_in[4]:20 chany_bottom_in[4]:19 0.0045 +14 chany_bottom_in[4]:20 chany_bottom_in[4]:17 0.005069197 +15 chany_bottom_in[4]:18 mux_left_track_3\/mux_l1_in_3_:A1 0.152 +16 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.001720982 +17 chany_bottom_in[4]:24 chany_bottom_in[4]:23 0.0045 +18 chany_bottom_in[4]:24 chany_bottom_in[4]:21 0.003946429 +19 chany_bottom_in[4]:22 mux_top_track_2\/mux_l1_in_3_:A0 0.152 +20 chany_bottom_in[4]:12 BUFT_RR_90:A 0.152 +21 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.0045 +22 chany_bottom_in[4]:13 chany_bottom_in[4]:11 0.0005558036 +23 chany_bottom_in[4]:21 chany_bottom_in[4]:20 0.0004107143 +24 chany_bottom_in[4]:25 chany_bottom_in[4]:24 0.03616964 + +*END + +*D_NET chany_bottom_in[12] 0.0233618 //LENGTH 145.695 LUMPCC 0.012645 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 79.580 1.290 +*I mux_right_track_0\/mux_l1_in_4_:A1 I *L 0.00198 *C 77.380 77.860 +*I mux_left_track_1\/mux_l1_in_3_:A1 I *L 0.00198 *C 70.285 79.900 +*I mux_top_track_0\/mux_l1_in_4_:A1 I *L 0.00198 *C 73.700 96.220 +*I FTB_34__33:A I *L 0.001776 *C 67.620 126.480 +*N chany_bottom_in[12]:5 *C 67.657 126.480 +*N chany_bottom_in[12]:6 *C 68.080 126.480 +*N chany_bottom_in[12]:7 *C 68.080 126.140 +*N chany_bottom_in[12]:8 *C 69.875 126.140 +*N chany_bottom_in[12]:9 *C 69.920 126.095 +*N chany_bottom_in[12]:10 *C 69.920 118.320 +*N chany_bottom_in[12]:11 *C 71.300 118.320 +*N chany_bottom_in[12]:12 *C 73.663 96.220 +*N chany_bottom_in[12]:13 *C 71.345 96.220 +*N chany_bottom_in[12]:14 *C 71.300 96.220 +*N chany_bottom_in[12]:15 *C 71.300 80.240 +*N chany_bottom_in[12]:16 *C 70.840 80.240 +*N chany_bottom_in[12]:17 *C 70.840 80.240 +*N chany_bottom_in[12]:18 *C 70.323 79.900 +*N chany_bottom_in[12]:19 *C 70.840 79.900 +*N chany_bottom_in[12]:20 *C 77.235 79.900 +*N chany_bottom_in[12]:21 *C 77.280 79.855 +*N chany_bottom_in[12]:22 *C 77.280 77.860 +*N chany_bottom_in[12]:23 *C 77.280 77.905 +*N chany_bottom_in[12]:24 *C 77.280 78.880 +*N chany_bottom_in[12]:25 *C 77.288 78.880 +*N chany_bottom_in[12]:26 *C 78.180 78.880 +*N chany_bottom_in[12]:27 *C 78.200 78.873 +*N chany_bottom_in[12]:28 *C 78.200 52.555 +*N chany_bottom_in[12]:29 *C 78.200 2.728 +*N chany_bottom_in[12]:30 *C 78.220 2.720 +*N chany_bottom_in[12]:31 *C 79.573 2.720 +*N chany_bottom_in[12]:32 *C 79.580 2.663 + +*CAP +0 chany_bottom_in[12] 9.876343e-05 +1 mux_right_track_0\/mux_l1_in_4_:A1 1e-06 +2 mux_left_track_1\/mux_l1_in_3_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_4_:A1 1e-06 +4 FTB_34__33:A 1e-06 +5 chany_bottom_in[12]:5 5.830484e-05 +6 chany_bottom_in[12]:6 8.606006e-05 +7 chany_bottom_in[12]:7 0.0001933286 +8 chany_bottom_in[12]:8 0.0001655734 +9 chany_bottom_in[12]:9 0.0004438093 +10 chany_bottom_in[12]:10 0.0005211885 +11 chany_bottom_in[12]:11 0.0009541916 +12 chany_bottom_in[12]:12 0.0001791811 +13 chany_bottom_in[12]:13 0.0001791811 +14 chany_bottom_in[12]:14 0.00169201 +15 chany_bottom_in[12]:15 0.0007821982 +16 chany_bottom_in[12]:16 3.374125e-05 +17 chany_bottom_in[12]:17 6.565053e-05 +18 chany_bottom_in[12]:18 2.850654e-05 +19 chany_bottom_in[12]:19 0.0003441782 +20 chany_bottom_in[12]:20 0.0002855047 +21 chany_bottom_in[12]:21 7.650812e-05 +22 chany_bottom_in[12]:22 3.43993e-05 +23 chany_bottom_in[12]:23 7.650812e-05 +24 chany_bottom_in[12]:24 0.0001905086 +25 chany_bottom_in[12]:25 0.0001361089 +26 chany_bottom_in[12]:26 0.0001361089 +27 chany_bottom_in[12]:27 0.0007856792 +28 chany_bottom_in[12]:28 0.00182648 +29 chany_bottom_in[12]:29 0.001040801 +30 chany_bottom_in[12]:30 9.97808e-05 +31 chany_bottom_in[12]:31 9.97808e-05 +32 chany_bottom_in[12]:32 9.876343e-05 +33 chany_bottom_in[12]:9 chany_top_in[8]:35 1.269591e-06 +34 chany_bottom_in[12]:14 chany_top_in[8]:29 3.158874e-05 +35 chany_bottom_in[12]:14 chany_top_in[8]:31 2.311086e-06 +36 chany_bottom_in[12]:14 chany_top_in[8]:32 8.979392e-05 +37 chany_bottom_in[12]:14 chany_top_in[8]:33 8.082739e-05 +38 chany_bottom_in[12]:14 chany_top_in[8]:34 0.0003412662 +39 chany_bottom_in[12]:10 chany_top_in[8]:34 1.269591e-06 +40 chany_bottom_in[12]:11 chany_top_in[8]:33 8.979392e-05 +41 chany_bottom_in[12]:11 chany_top_in[8]:35 0.0003412662 +42 chany_bottom_in[12]:15 chany_top_in[8]:28 3.158874e-05 +43 chany_bottom_in[12]:15 chany_top_in[8]:30 2.311086e-06 +44 chany_bottom_in[12]:15 chany_top_in[8]:32 8.082739e-05 +45 chany_bottom_in[12]:27 chanx_left_in[12]:12 0.00114559 +46 chany_bottom_in[12]:29 chanx_left_in[12]:11 0.0005082255 +47 chany_bottom_in[12]:28 chanx_left_in[12]:11 0.00114559 +48 chany_bottom_in[12]:28 chanx_left_in[12]:12 0.0005082255 +49 chany_bottom_in[12]:29 chany_bottom_in[0]:18 0.0007580462 +50 chany_bottom_in[12]:28 chany_bottom_in[0]:17 0.0007580462 +51 chany_bottom_in[12] chany_bottom_in[19] 1.227523e-05 +52 chany_bottom_in[12]:27 chany_bottom_in[19]:16 0.0005445902 +53 chany_bottom_in[12]:27 chany_bottom_in[19]:17 0.0001179545 +54 chany_bottom_in[12]:30 chany_bottom_in[19]:19 5.34126e-06 +55 chany_bottom_in[12]:29 chany_bottom_in[19]:18 0.002097627 +56 chany_bottom_in[12]:32 chany_bottom_in[19]:21 1.227523e-05 +57 chany_bottom_in[12]:31 chany_bottom_in[19]:20 5.34126e-06 +58 chany_bottom_in[12]:14 chany_bottom_in[19]:6 7.914725e-06 +59 chany_bottom_in[12]:15 chany_bottom_in[19]:7 7.914725e-06 +60 chany_bottom_in[12]:28 chany_bottom_in[19]:18 0.0001179545 +61 chany_bottom_in[12]:28 chany_bottom_in[19]:17 0.002642217 +62 chany_bottom_in[12]:17 mux_tree_tapbuf_size7_0_sram[0]:29 7.386698e-08 +63 chany_bottom_in[12]:18 mux_tree_tapbuf_size7_0_sram[0]:28 2.528756e-05 +64 chany_bottom_in[12]:20 mux_tree_tapbuf_size7_0_sram[0]:27 0.0002359729 +65 chany_bottom_in[12]:19 mux_tree_tapbuf_size7_0_sram[0]:27 2.528756e-05 +66 chany_bottom_in[12]:19 mux_tree_tapbuf_size7_0_sram[0]:28 0.0002360467 +67 chany_bottom_in[12]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.668604e-05 +68 chany_bottom_in[12]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.668604e-05 +69 chany_bottom_in[12]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 3.749617e-05 +70 chany_bottom_in[12]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 6.835744e-05 +71 chany_bottom_in[12]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 3.749617e-05 +72 chany_bottom_in[12]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 6.835744e-05 +73 chany_bottom_in[12]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.0001440064 +74 chany_bottom_in[12]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0001440064 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:32 0.001225446 +1 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.001602679 +2 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.0045 +3 chany_bottom_in[12]:5 FTB_34__33:A 0.152 +4 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.0045 +5 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.0004107143 +6 chany_bottom_in[12]:22 mux_right_track_0\/mux_l1_in_4_:A1 0.152 +7 chany_bottom_in[12]:23 chany_bottom_in[12]:22 0.0045 +8 chany_bottom_in[12]:24 chany_bottom_in[12]:23 0.0008705358 +9 chany_bottom_in[12]:24 chany_bottom_in[12]:21 0.0008705358 +10 chany_bottom_in[12]:25 chany_bottom_in[12]:24 0.00341 +11 chany_bottom_in[12]:26 chany_bottom_in[12]:25 0.000139825 +12 chany_bottom_in[12]:27 chany_bottom_in[12]:26 0.00341 +13 chany_bottom_in[12]:30 chany_bottom_in[12]:29 0.00341 +14 chany_bottom_in[12]:29 chany_bottom_in[12]:28 0.007806308 +15 chany_bottom_in[12]:32 chany_bottom_in[12]:31 0.00341 +16 chany_bottom_in[12]:31 chany_bottom_in[12]:30 0.0002118917 +17 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.002069196 +18 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.0045 +19 chany_bottom_in[12]:14 chany_bottom_in[12]:11 0.01973214 +20 chany_bottom_in[12]:12 mux_top_track_0\/mux_l1_in_4_:A1 0.152 +21 chany_bottom_in[12]:18 mux_left_track_1\/mux_l1_in_3_:A1 0.152 +22 chany_bottom_in[12]:20 chany_bottom_in[12]:19 0.005709822 +23 chany_bottom_in[12]:21 chany_bottom_in[12]:20 0.0045 +24 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.0003772322 +25 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.0003035715 +26 chany_bottom_in[12]:19 chany_bottom_in[12]:18 0.0004620536 +27 chany_bottom_in[12]:19 chany_bottom_in[12]:17 0.0003035715 +28 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.006941965 +29 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.001232143 +30 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.01426786 +31 chany_bottom_in[12]:28 chany_bottom_in[12]:27 0.004123075 + +*END + +*D_NET chanx_left_in[2] 0.04115579 //LENGTH 230.305 LUMPCC 0.02078582 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 35.360 +*I mux_top_track_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 75.155 91.800 +*I mux_right_track_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 97.235 91.800 +*I BUFT_P_123:A I *L 0.001776 *C 131.560 82.960 +*I mux_bottom_track_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 76.535 33.660 +*N chanx_left_in[2]:5 *C 76.535 33.660 +*N chanx_left_in[2]:6 *C 76.820 33.660 +*N chanx_left_in[2]:7 *C 76.820 33.705 +*N chanx_left_in[2]:8 *C 131.597 82.960 +*N chanx_left_in[2]:9 *C 132.895 82.960 +*N chanx_left_in[2]:10 *C 132.940 82.960 +*N chanx_left_in[2]:11 *C 132.933 82.960 +*N chanx_left_in[2]:12 *C 113.160 82.960 +*N chanx_left_in[2]:13 *C 113.160 83.640 +*N chanx_left_in[2]:14 *C 103.960 83.640 +*N chanx_left_in[2]:15 *C 103.960 82.960 +*N chanx_left_in[2]:16 *C 97.198 91.800 +*N chanx_left_in[2]:17 *C 75.193 91.800 +*N chanx_left_in[2]:18 *C 89.700 91.800 +*N chanx_left_in[2]:19 *C 89.700 91.755 +*N chanx_left_in[2]:20 *C 89.700 83.017 +*N chanx_left_in[2]:21 *C 89.708 82.960 +*N chanx_left_in[2]:22 *C 96.600 82.960 +*N chanx_left_in[2]:23 *C 96.600 82.953 +*N chanx_left_in[2]:24 *C 96.600 35.367 +*N chanx_left_in[2]:25 *C 96.580 35.360 +*N chanx_left_in[2]:26 *C 76.828 35.360 +*N chanx_left_in[2]:27 *C 76.820 35.360 +*N chanx_left_in[2]:28 *C 76.820 37.343 +*N chanx_left_in[2]:29 *C 76.812 37.400 +*N chanx_left_in[2]:30 *C 40.488 37.400 +*N chanx_left_in[2]:31 *C 40.480 37.343 +*N chanx_left_in[2]:32 *C 40.480 35.418 +*N chanx_left_in[2]:33 *C 40.473 35.360 + +*CAP +0 chanx_left_in[2] 0.0006952491 +1 mux_top_track_0\/mux_l2_in_2_:A0 1e-06 +2 mux_right_track_0\/mux_l2_in_2_:A0 1e-06 +3 BUFT_P_123:A 1e-06 +4 mux_bottom_track_1\/mux_l2_in_2_:A0 1e-06 +5 chanx_left_in[2]:5 6.17023e-05 +6 chanx_left_in[2]:6 6.446565e-05 +7 chanx_left_in[2]:7 0.000138831 +8 chanx_left_in[2]:8 0.0001263387 +9 chanx_left_in[2]:9 0.0001263387 +10 chanx_left_in[2]:10 3.375002e-05 +11 chanx_left_in[2]:11 0.0009839721 +12 chanx_left_in[2]:12 0.001043067 +13 chanx_left_in[2]:13 0.0006016358 +14 chanx_left_in[2]:14 0.0005976695 +15 chanx_left_in[2]:15 0.0004827436 +16 chanx_left_in[2]:16 0.0005110843 +17 chanx_left_in[2]:17 0.001000704 +18 chanx_left_in[2]:18 0.001546694 +19 chanx_left_in[2]:19 0.0005634 +20 chanx_left_in[2]:20 0.0005634 +21 chanx_left_in[2]:21 0.000422525 +22 chanx_left_in[2]:22 0.0008501402 +23 chanx_left_in[2]:23 0.002089065 +24 chanx_left_in[2]:24 0.002089065 +25 chanx_left_in[2]:25 0.0006486804 +26 chanx_left_in[2]:26 0.0006486805 +27 chanx_left_in[2]:27 0.0003233109 +28 chanx_left_in[2]:28 0.0001460254 +29 chanx_left_in[2]:29 0.001518451 +30 chanx_left_in[2]:30 0.001518451 +31 chanx_left_in[2]:31 0.0001376421 +32 chanx_left_in[2]:32 0.0001376421 +33 chanx_left_in[2]:33 0.0006952491 +34 chanx_left_in[2]:23 chany_bottom_in[2]:32 0.001327298 +35 chanx_left_in[2]:23 chany_bottom_in[2]:33 0.000699713 +36 chanx_left_in[2]:24 chany_bottom_in[2]:33 0.001327298 +37 chanx_left_in[2]:24 chany_bottom_in[2]:34 0.000699713 +38 chanx_left_in[2] chanx_left_in[6] 0.0008788861 +39 chanx_left_in[2] chanx_left_in[6]:32 0.00013345 +40 chanx_left_in[2]:33 chanx_left_in[6]:33 0.0008788861 +41 chanx_left_in[2]:33 chanx_left_in[6]:31 0.00013345 +42 chanx_left_in[2]:25 chanx_left_in[6]:30 0.000366287 +43 chanx_left_in[2]:25 chanx_left_in[6]:31 0.0005973163 +44 chanx_left_in[2]:26 chanx_left_in[6]:32 0.0005973163 +45 chanx_left_in[2]:26 chanx_left_in[6]:31 0.000366287 +46 chanx_left_in[2]:29 chanx_right_in[19]:15 0.001099865 +47 chanx_left_in[2]:30 chanx_right_in[19]:14 0.001099865 +48 chanx_left_in[2]:20 right_top_grid_pin_43_[0]:7 1.605322e-06 +49 chanx_left_in[2]:21 right_top_grid_pin_43_[0]:8 0.0001299446 +50 chanx_left_in[2]:21 right_top_grid_pin_43_[0]:13 3.253301e-05 +51 chanx_left_in[2]:19 right_top_grid_pin_43_[0]:6 1.605322e-06 +52 chanx_left_in[2]:22 right_top_grid_pin_43_[0]:17 3.253301e-05 +53 chanx_left_in[2]:22 right_top_grid_pin_43_[0]:13 0.0004414696 +54 chanx_left_in[2]:15 right_top_grid_pin_43_[0]:17 0.000311525 +55 chanx_left_in[2]:14 right_top_grid_pin_43_[0]:17 7.637979e-06 +56 chanx_left_in[2]:14 right_top_grid_pin_43_[0]:13 0.0001566457 +57 chanx_left_in[2]:13 right_top_grid_pin_43_[0]:21 6.742936e-06 +58 chanx_left_in[2]:13 right_top_grid_pin_43_[0]:17 0.0001566457 +59 chanx_left_in[2]:13 right_top_grid_pin_43_[0]:18 7.637979e-06 +60 chanx_left_in[2]:12 right_top_grid_pin_43_[0]:20 6.742936e-06 +61 chanx_left_in[2]:20 right_top_grid_pin_48_[0]:8 1.425316e-07 +62 chanx_left_in[2]:19 right_top_grid_pin_48_[0]:9 1.425316e-07 +63 chanx_left_in[2]:22 right_top_grid_pin_48_[0]:11 1.857709e-06 +64 chanx_left_in[2]:11 right_top_grid_pin_48_[0]:12 1.552966e-05 +65 chanx_left_in[2]:11 right_top_grid_pin_48_[0]:19 0.0002945706 +66 chanx_left_in[2]:15 right_top_grid_pin_48_[0]:12 1.857709e-06 +67 chanx_left_in[2]:14 right_top_grid_pin_48_[0]:11 3.123219e-05 +68 chanx_left_in[2]:13 right_top_grid_pin_48_[0]:12 3.123219e-05 +69 chanx_left_in[2]:12 right_top_grid_pin_48_[0]:11 1.552966e-05 +70 chanx_left_in[2]:12 right_top_grid_pin_48_[0]:18 0.0002945706 +71 chanx_left_in[2] chanx_left_in[1] 8.442116e-06 +72 chanx_left_in[2]:29 chanx_left_in[1]:18 0.000293651 +73 chanx_left_in[2]:29 chanx_left_in[1]:11 1.8438e-05 +74 chanx_left_in[2]:29 chanx_left_in[1]:19 0.0002949454 +75 chanx_left_in[2]:30 chanx_left_in[1]:12 1.8438e-05 +76 chanx_left_in[2]:30 chanx_left_in[1]:20 0.0002949454 +77 chanx_left_in[2]:30 chanx_left_in[1]:19 0.000293651 +78 chanx_left_in[2]:33 chanx_left_in[1]:21 8.442116e-06 +79 chanx_left_in[2] chanx_left_in[11]:12 0.002245463 +80 chanx_left_in[2]:29 chanx_left_in[11]:10 0.0002734752 +81 chanx_left_in[2]:30 chanx_left_in[11]:11 0.0002734752 +82 chanx_left_in[2]:33 chanx_left_in[11]:11 0.002245463 +83 chanx_left_in[2]:25 chanx_left_in[11]:10 0.001058414 +84 chanx_left_in[2]:26 chanx_left_in[11]:11 0.001058414 +85 chanx_left_in[2]:21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.871374e-05 +86 chanx_left_in[2]:22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.871374e-05 +87 chanx_left_in[2]:22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.858492e-05 +88 chanx_left_in[2]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.858492e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:33 0.006147991 +1 chanx_left_in[2]:28 chanx_left_in[2]:27 0.001770089 +2 chanx_left_in[2]:29 chanx_left_in[2]:28 0.00341 +3 chanx_left_in[2]:31 chanx_left_in[2]:30 0.00341 +4 chanx_left_in[2]:30 chanx_left_in[2]:29 0.005690916 +5 chanx_left_in[2]:32 chanx_left_in[2]:31 0.00171875 +6 chanx_left_in[2]:33 chanx_left_in[2]:32 0.00341 +7 chanx_left_in[2]:6 chanx_left_in[2]:5 0.0001548913 +8 chanx_left_in[2]:7 chanx_left_in[2]:6 0.0045 +9 chanx_left_in[2]:5 mux_bottom_track_1\/mux_l2_in_2_:A0 0.152 +10 chanx_left_in[2]:17 mux_top_track_0\/mux_l2_in_2_:A0 0.152 +11 chanx_left_in[2]:20 chanx_left_in[2]:19 0.007801339 +12 chanx_left_in[2]:21 chanx_left_in[2]:20 0.00341 +13 chanx_left_in[2]:18 chanx_left_in[2]:17 0.01295312 +14 chanx_left_in[2]:18 chanx_left_in[2]:16 0.006694197 +15 chanx_left_in[2]:19 chanx_left_in[2]:18 0.0045 +16 chanx_left_in[2]:16 mux_right_track_0\/mux_l2_in_2_:A0 0.152 +17 chanx_left_in[2]:22 chanx_left_in[2]:21 0.001079825 +18 chanx_left_in[2]:22 chanx_left_in[2]:15 0.001153067 +19 chanx_left_in[2]:23 chanx_left_in[2]:22 0.00341 +20 chanx_left_in[2]:25 chanx_left_in[2]:24 0.00341 +21 chanx_left_in[2]:24 chanx_left_in[2]:23 0.007454982 +22 chanx_left_in[2]:27 chanx_left_in[2]:26 0.00341 +23 chanx_left_in[2]:27 chanx_left_in[2]:7 0.001477679 +24 chanx_left_in[2]:26 chanx_left_in[2]:25 0.003094558 +25 chanx_left_in[2]:10 chanx_left_in[2]:9 0.0045 +26 chanx_left_in[2]:11 chanx_left_in[2]:10 0.00341 +27 chanx_left_in[2]:9 chanx_left_in[2]:8 0.001158482 +28 chanx_left_in[2]:8 BUFT_P_123:A 0.152 +29 chanx_left_in[2]:15 chanx_left_in[2]:14 0.0001065333 +30 chanx_left_in[2]:14 chanx_left_in[2]:13 0.001441333 +31 chanx_left_in[2]:13 chanx_left_in[2]:12 0.0001065333 +32 chanx_left_in[2]:12 chanx_left_in[2]:11 0.003097691 + +*END + +*D_NET chanx_left_in[10] 0.02898153 //LENGTH 171.855 LUMPCC 0.01234755 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 59.160 +*I mux_right_track_32\/mux_l1_in_3_:A1 I *L 0.00198 *C 86.020 74.460 +*I mux_top_track_32\/mux_l1_in_3_:A1 I *L 0.00198 *C 86.845 79.900 +*I BUFT_P_125:A I *L 0.001767 *C 132.940 77.520 +*I mux_bottom_track_33\/mux_l1_in_3_:A1 I *L 0.00198 *C 21.160 52.700 +*N chanx_left_in[10]:5 *C 21.123 52.700 +*N chanx_left_in[10]:6 *C 20.745 52.700 +*N chanx_left_in[10]:7 *C 20.700 52.745 +*N chanx_left_in[10]:8 *C 132.940 77.520 +*N chanx_left_in[10]:9 *C 132.940 77.180 +*N chanx_left_in[10]:10 *C 128.845 77.180 +*N chanx_left_in[10]:11 *C 128.800 77.225 +*N chanx_left_in[10]:12 *C 128.800 80.862 +*N chanx_left_in[10]:13 *C 128.793 80.920 +*N chanx_left_in[10]:14 *C 86.948 80.920 +*N chanx_left_in[10]:15 *C 86.940 80.862 +*N chanx_left_in[10]:16 *C 86.845 79.900 +*N chanx_left_in[10]:17 *C 86.940 79.945 +*N chanx_left_in[10]:18 *C 86.480 79.900 +*N chanx_left_in[10]:19 *C 86.020 74.460 +*N chanx_left_in[10]:20 *C 86.020 74.460 +*N chanx_left_in[10]:21 *C 86.480 74.460 +*N chanx_left_in[10]:22 *C 86.480 69.418 +*N chanx_left_in[10]:23 *C 86.473 69.360 +*N chanx_left_in[10]:24 *C 77.410 69.360 +*N chanx_left_in[10]:25 *C 27.620 69.360 +*N chanx_left_in[10]:26 *C 27.600 69.353 +*N chanx_left_in[10]:27 *C 27.600 56.448 +*N chanx_left_in[10]:28 *C 27.580 56.440 +*N chanx_left_in[10]:29 *C 20.707 56.440 +*N chanx_left_in[10]:30 *C 20.700 56.383 +*N chanx_left_in[10]:31 *C 20.240 56.440 +*N chanx_left_in[10]:32 *C 20.240 59.103 +*N chanx_left_in[10]:33 *C 20.233 59.160 + +*CAP +0 chanx_left_in[10] 0.0009599696 +1 mux_right_track_32\/mux_l1_in_3_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_3_:A1 1e-06 +3 BUFT_P_125:A 1e-06 +4 mux_bottom_track_33\/mux_l1_in_3_:A1 1e-06 +5 chanx_left_in[10]:5 4.586707e-05 +6 chanx_left_in[10]:6 4.586707e-05 +7 chanx_left_in[10]:7 0.0001632544 +8 chanx_left_in[10]:8 5.45251e-05 +9 chanx_left_in[10]:9 0.0003166965 +10 chanx_left_in[10]:10 0.0002898303 +11 chanx_left_in[10]:11 0.0002312736 +12 chanx_left_in[10]:12 0.0002312736 +13 chanx_left_in[10]:13 0.001713633 +14 chanx_left_in[10]:14 0.001713633 +15 chanx_left_in[10]:15 8.135723e-05 +16 chanx_left_in[10]:16 2.775236e-05 +17 chanx_left_in[10]:17 0.0001157963 +18 chanx_left_in[10]:18 0.0003670488 +19 chanx_left_in[10]:19 3.672805e-05 +20 chanx_left_in[10]:20 7.641281e-05 +21 chanx_left_in[10]:21 0.0007019959 +22 chanx_left_in[10]:22 0.0003305181 +23 chanx_left_in[10]:23 0.0004986986 +24 chanx_left_in[10]:24 0.002769739 +25 chanx_left_in[10]:25 0.00227104 +26 chanx_left_in[10]:26 0.0006152518 +27 chanx_left_in[10]:27 0.0006152518 +28 chanx_left_in[10]:28 0.0004358588 +29 chanx_left_in[10]:29 0.0004358588 +30 chanx_left_in[10]:30 0.0001974618 +31 chanx_left_in[10]:31 0.0001808074 +32 chanx_left_in[10]:32 0.0001466001 +33 chanx_left_in[10]:33 0.0009599696 +34 chanx_left_in[10]:25 chany_top_in[16]:20 0.0001797358 +35 chanx_left_in[10]:23 chany_top_in[16]:19 0.0004773485 +36 chanx_left_in[10]:24 chany_top_in[16]:19 0.0001797358 +37 chanx_left_in[10]:24 chany_top_in[16]:20 0.0004773485 +38 chanx_left_in[10]:14 chanx_right_in[6]:33 2.951916e-05 +39 chanx_left_in[10]:13 chanx_right_in[6]:34 2.951916e-05 +40 chanx_left_in[10]:25 chanx_right_in[6]:20 0.001703558 +41 chanx_left_in[10]:25 chanx_right_in[6]:21 0.0006208469 +42 chanx_left_in[10]:24 chanx_right_in[6]:21 0.001703558 +43 chanx_left_in[10]:24 chanx_right_in[6]:22 0.0006208469 +44 chanx_left_in[10] chanx_right_in[17]:10 0.0007672836 +45 chanx_left_in[10]:29 chanx_right_in[17]:10 7.143147e-05 +46 chanx_left_in[10]:28 chanx_right_in[17]:11 7.143147e-05 +47 chanx_left_in[10]:33 chanx_right_in[17]:11 0.0007672836 +48 chanx_left_in[10]:14 chanx_left_in[14]:21 0.0006029588 +49 chanx_left_in[10]:13 chanx_left_in[14]:20 0.0006029588 +50 chanx_left_in[10]:14 prog_clk[0]:165 1.791062e-05 +51 chanx_left_in[10]:14 prog_clk[0]:269 0.0004086275 +52 chanx_left_in[10]:13 prog_clk[0]:164 1.791062e-05 +53 chanx_left_in[10]:13 prog_clk[0]:268 0.0004086275 +54 chanx_left_in[10]:14 right_top_grid_pin_43_[0]:8 4.655867e-05 +55 chanx_left_in[10]:14 right_top_grid_pin_43_[0]:17 1.290046e-05 +56 chanx_left_in[10]:14 right_top_grid_pin_43_[0]:13 0.0003803437 +57 chanx_left_in[10]:13 right_top_grid_pin_43_[0]:17 0.0003803437 +58 chanx_left_in[10]:13 right_top_grid_pin_43_[0]:13 4.655867e-05 +59 chanx_left_in[10]:13 right_top_grid_pin_43_[0]:18 1.290046e-05 +60 chanx_left_in[10]:23 right_top_grid_pin_43_[0]:10 6.433597e-06 +61 chanx_left_in[10]:24 right_top_grid_pin_43_[0]:9 6.433597e-06 +62 chanx_left_in[10]:7 mux_tree_tapbuf_size12_6_sram[0]:48 0.000106861 +63 chanx_left_in[10]:30 mux_tree_tapbuf_size12_6_sram[0]:47 0.000106861 +64 chanx_left_in[10]:25 mux_tree_tapbuf_size12_6_sram[0]:46 0.0004713822 +65 chanx_left_in[10]:32 mux_tree_tapbuf_size12_6_sram[0]:47 1.967463e-05 +66 chanx_left_in[10]:31 mux_tree_tapbuf_size12_6_sram[0]:48 1.967463e-05 +67 chanx_left_in[10]:24 mux_tree_tapbuf_size12_6_sram[0]:45 0.0004713822 +68 chanx_left_in[10]:27 mux_tree_tapbuf_size16_3_sram[1]:36 0.0002504028 +69 chanx_left_in[10]:26 mux_tree_tapbuf_size16_3_sram[1]:37 0.0002504028 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:33 0.002977058 +1 chanx_left_in[10]:6 chanx_left_in[10]:5 0.0003370536 +2 chanx_left_in[10]:7 chanx_left_in[10]:6 0.0045 +3 chanx_left_in[10]:5 mux_bottom_track_33\/mux_l1_in_3_:A1 0.152 +4 chanx_left_in[10]:15 chanx_left_in[10]:14 0.00341 +5 chanx_left_in[10]:14 chanx_left_in[10]:13 0.006555716 +6 chanx_left_in[10]:12 chanx_left_in[10]:11 0.003247768 +7 chanx_left_in[10]:13 chanx_left_in[10]:12 0.00341 +8 chanx_left_in[10]:10 chanx_left_in[10]:9 0.00365625 +9 chanx_left_in[10]:11 chanx_left_in[10]:10 0.0045 +10 chanx_left_in[10]:8 BUFT_P_125:A 0.152 +11 chanx_left_in[10]:16 mux_top_track_32\/mux_l1_in_3_:A1 0.152 +12 chanx_left_in[10]:17 chanx_left_in[10]:16 0.0045 +13 chanx_left_in[10]:17 chanx_left_in[10]:15 0.0008191965 +14 chanx_left_in[10]:30 chanx_left_in[10]:29 0.00341 +15 chanx_left_in[10]:30 chanx_left_in[10]:7 0.003247768 +16 chanx_left_in[10]:29 chanx_left_in[10]:28 0.001076692 +17 chanx_left_in[10]:28 chanx_left_in[10]:27 0.00341 +18 chanx_left_in[10]:27 chanx_left_in[10]:26 0.002021783 +19 chanx_left_in[10]:25 chanx_left_in[10]:24 0.007800433 +20 chanx_left_in[10]:26 chanx_left_in[10]:25 0.00341 +21 chanx_left_in[10]:22 chanx_left_in[10]:21 0.004502232 +22 chanx_left_in[10]:23 chanx_left_in[10]:22 0.00341 +23 chanx_left_in[10]:19 mux_right_track_32\/mux_l1_in_3_:A1 0.152 +24 chanx_left_in[10]:20 chanx_left_in[10]:19 0.0045 +25 chanx_left_in[10]:32 chanx_left_in[10]:31 0.002377232 +26 chanx_left_in[10]:33 chanx_left_in[10]:32 0.00341 +27 chanx_left_in[10]:9 chanx_left_in[10]:8 0.0003035715 +28 chanx_left_in[10]:31 chanx_left_in[10]:30 0.0004107143 +29 chanx_left_in[10]:21 chanx_left_in[10]:20 0.0004107143 +30 chanx_left_in[10]:21 chanx_left_in[10]:18 0.004857143 +31 chanx_left_in[10]:18 chanx_left_in[10]:17 0.0004107143 +32 chanx_left_in[10]:24 chanx_left_in[10]:23 0.001419791 + +*END + +*D_NET chany_top_in[1] 0.01608866 //LENGTH 121.905 LUMPCC 0.001551259 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 57.500 129.270 +*I mux_left_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 26.125 77.860 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 67.260 88.740 +*N chany_top_in[1]:3 *C 67.222 88.740 +*N chany_top_in[1]:4 *C 66.285 88.740 +*N chany_top_in[1]:5 *C 66.240 88.785 +*N chany_top_in[1]:6 *C 66.240 113.503 +*N chany_top_in[1]:7 *C 66.233 113.560 +*N chany_top_in[1]:8 *C 60.740 113.560 +*N chany_top_in[1]:9 *C 60.720 113.568 +*N chany_top_in[1]:10 *C 60.720 114.913 +*N chany_top_in[1]:11 *C 60.700 114.920 +*N chany_top_in[1]:12 *C 26.125 77.860 +*N chany_top_in[1]:13 *C 26.220 77.860 +*N chany_top_in[1]:14 *C 26.220 78.200 +*N chany_top_in[1]:15 *C 26.228 78.200 +*N chany_top_in[1]:16 *C 28.500 78.200 +*N chany_top_in[1]:17 *C 28.520 78.208 +*N chany_top_in[1]:18 *C 28.520 100.633 +*N chany_top_in[1]:19 *C 28.540 100.640 +*N chany_top_in[1]:20 *C 33.100 100.640 +*N chany_top_in[1]:21 *C 33.120 100.648 +*N chany_top_in[1]:22 *C 33.120 114.913 +*N chany_top_in[1]:23 *C 33.140 114.920 +*N chany_top_in[1]:24 *C 57.500 114.920 +*N chany_top_in[1]:25 *C 57.500 114.978 + +*CAP +0 chany_top_in[1] 0.000729871 +1 mux_left_track_33\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[1]:3 8.418944e-05 +4 chany_top_in[1]:4 8.418944e-05 +5 chany_top_in[1]:5 0.001236483 +6 chany_top_in[1]:6 0.001236483 +7 chany_top_in[1]:7 0.0004242136 +8 chany_top_in[1]:8 0.0004242136 +9 chany_top_in[1]:9 9.857668e-05 +10 chany_top_in[1]:10 9.857668e-05 +11 chany_top_in[1]:11 0.0002270356 +12 chany_top_in[1]:12 2.978742e-05 +13 chany_top_in[1]:13 5.452718e-05 +14 chany_top_in[1]:14 5.883114e-05 +15 chany_top_in[1]:15 0.0003488809 +16 chany_top_in[1]:16 0.0003488809 +17 chany_top_in[1]:17 0.001420977 +18 chany_top_in[1]:18 0.001420977 +19 chany_top_in[1]:19 0.0003086652 +20 chany_top_in[1]:20 0.0003086652 +21 chany_top_in[1]:21 0.0007663941 +22 chany_top_in[1]:22 0.0007663941 +23 chany_top_in[1]:23 0.001550838 +24 chany_top_in[1]:24 0.001777874 +25 chany_top_in[1]:25 0.000729871 +26 chany_top_in[1]:24 chany_top_in[4]:34 7.987866e-06 +27 chany_top_in[1]:11 chany_top_in[4]:33 7.987866e-06 +28 chany_top_in[1]:8 chany_top_in[4]:34 1.802397e-06 +29 chany_top_in[1]:6 chany_top_in[4]:32 0.0003230083 +30 chany_top_in[1]:7 chany_top_in[4]:33 1.802397e-06 +31 chany_top_in[1]:5 chany_top_in[4]:31 0.0003230083 +32 chany_top_in[1]:20 chanx_left_in[12]:36 0.0002756139 +33 chany_top_in[1]:19 chanx_left_in[12]:37 0.0002756139 +34 chany_top_in[1]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.940874e-05 +35 chany_top_in[1]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.940874e-05 +36 chany_top_in[1] ropt_net_201:7 0.0001070568 +37 chany_top_in[1] ropt_net_201:5 7.515512e-07 +38 chany_top_in[1]:25 ropt_net_201:4 7.515512e-07 +39 chany_top_in[1]:25 ropt_net_201:6 0.0001070568 + +*RES +0 chany_top_in[1] chany_top_in[1]:25 0.01276116 +1 chany_top_in[1]:23 chany_top_in[1]:22 0.00341 +2 chany_top_in[1]:22 chany_top_in[1]:21 0.00223485 +3 chany_top_in[1]:20 chany_top_in[1]:19 0.0007144 +4 chany_top_in[1]:21 chany_top_in[1]:20 0.00341 +5 chany_top_in[1]:19 chany_top_in[1]:18 0.00341 +6 chany_top_in[1]:18 chany_top_in[1]:17 0.00351325 +7 chany_top_in[1]:16 chany_top_in[1]:15 0.000356025 +8 chany_top_in[1]:17 chany_top_in[1]:16 0.00341 +9 chany_top_in[1]:14 chany_top_in[1]:13 0.0001634615 +10 chany_top_in[1]:15 chany_top_in[1]:14 0.00341 +11 chany_top_in[1]:12 mux_left_track_33\/mux_l1_in_0_:A1 0.152 +12 chany_top_in[1]:13 chany_top_in[1]:12 0.0045 +13 chany_top_in[1]:25 chany_top_in[1]:24 0.00341 +14 chany_top_in[1]:24 chany_top_in[1]:23 0.0038164 +15 chany_top_in[1]:24 chany_top_in[1]:11 0.0005013333 +16 chany_top_in[1]:11 chany_top_in[1]:10 0.00341 +17 chany_top_in[1]:10 chany_top_in[1]:9 0.0002107167 +18 chany_top_in[1]:8 chany_top_in[1]:7 0.0008604916 +19 chany_top_in[1]:9 chany_top_in[1]:8 0.00341 +20 chany_top_in[1]:6 chany_top_in[1]:5 0.0220692 +21 chany_top_in[1]:7 chany_top_in[1]:6 0.00341 +22 chany_top_in[1]:4 chany_top_in[1]:3 0.0008370536 +23 chany_top_in[1]:5 chany_top_in[1]:4 0.0045 +24 chany_top_in[1]:3 mux_right_track_4\/mux_l1_in_0_:A1 0.152 + +*END + +*D_NET chany_top_in[11] 0.007976338 //LENGTH 61.972 LUMPCC 0.001665998 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 75.900 129.270 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.775 87.720 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.890 71.740 +*N chany_top_in[11]:3 *C 73.928 71.740 +*N chany_top_in[11]:4 *C 74.935 71.740 +*N chany_top_in[11]:5 *C 74.980 71.785 +*N chany_top_in[11]:6 *C 73.812 87.720 +*N chany_top_in[11]:7 *C 74.935 87.720 +*N chany_top_in[11]:8 *C 74.980 87.720 +*N chany_top_in[11]:9 *C 74.987 87.720 +*N chany_top_in[11]:10 *C 75.892 87.720 +*N chany_top_in[11]:11 *C 75.900 87.778 + +*CAP +0 chany_top_in[11] 0.002054455 +1 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[11]:3 0.0001023693 +4 chany_top_in[11]:4 0.0001023693 +5 chany_top_in[11]:5 0.0007060939 +6 chany_top_in[11]:6 0.0001020406 +7 chany_top_in[11]:7 0.0001020406 +8 chany_top_in[11]:8 0.0007471038 +9 chany_top_in[11]:9 0.0001687056 +10 chany_top_in[11]:10 0.0001687056 +11 chany_top_in[11]:11 0.002054455 +12 chany_top_in[11] chany_top_in[6] 1.56919e-06 +13 chany_top_in[11] chany_top_in[6]:23 0.0003037096 +14 chany_top_in[11] chany_top_in[6]:31 2.540131e-05 +15 chany_top_in[11]:8 chany_top_in[6]:16 1.450049e-05 +16 chany_top_in[11]:8 chany_top_in[6]:20 5.999233e-06 +17 chany_top_in[11]:8 chany_top_in[6]:21 0.000100887 +18 chany_top_in[11]:8 chany_top_in[6]:23 0.0001024713 +19 chany_top_in[11]:4 chany_top_in[6]:19 1.427172e-05 +20 chany_top_in[11]:5 chany_top_in[6]:15 1.450049e-05 +21 chany_top_in[11]:5 chany_top_in[6]:17 5.999233e-06 +22 chany_top_in[11]:5 chany_top_in[6]:20 0.000100887 +23 chany_top_in[11]:5 chany_top_in[6]:22 0.0001024713 +24 chany_top_in[11]:3 chany_top_in[6]:18 1.427172e-05 +25 chany_top_in[11]:11 chany_top_in[6]:22 0.0003037096 +26 chany_top_in[11]:11 chany_top_in[6]:30 2.540131e-05 +27 chany_top_in[11]:11 chany_top_in[6]:32 1.56919e-06 +28 chany_top_in[11] mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.555133e-06 +29 chany_top_in[11] mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001140992 +30 chany_top_in[11]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001140992 +31 chany_top_in[11]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.555133e-06 +32 chany_top_in[11]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.359378e-05 +33 chany_top_in[11]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.359378e-05 +34 chany_top_in[11] ropt_net_208:5 4.949281e-05 +35 chany_top_in[11] ropt_net_208:7 4.448613e-06 +36 chany_top_in[11]:11 ropt_net_208:8 4.448613e-06 +37 chany_top_in[11]:11 ropt_net_208:6 4.949281e-05 + +*RES +0 chany_top_in[11] chany_top_in[11]:11 0.03704688 +1 chany_top_in[11]:7 chany_top_in[11]:6 0.001002232 +2 chany_top_in[11]:8 chany_top_in[11]:7 0.0045 +3 chany_top_in[11]:8 chany_top_in[11]:5 0.01422768 +4 chany_top_in[11]:6 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +5 chany_top_in[11]:4 chany_top_in[11]:3 0.0008995536 +6 chany_top_in[11]:5 chany_top_in[11]:4 0.0045 +7 chany_top_in[11]:3 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +8 chany_top_in[11]:9 chany_top_in[11]:8 0.00341 +9 chany_top_in[11]:11 chany_top_in[11]:10 0.00341 +10 chany_top_in[11]:10 chany_top_in[11]:9 0.0001417833 + +*END + +*D_NET top_left_grid_pin_39_[0] 0.006859941 //LENGTH 57.125 LUMPCC 0.0002442171 DR + +*CONN +*P top_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 123.760 +*I mux_top_track_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 33.580 112.540 +*I mux_top_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 45.640 107.100 +*I mux_top_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 51.695 91.460 +*N top_left_grid_pin_39_[0]:4 *C 51.658 91.460 +*N top_left_grid_pin_39_[0]:5 *C 48.805 91.460 +*N top_left_grid_pin_39_[0]:6 *C 48.760 91.505 +*N top_left_grid_pin_39_[0]:7 *C 48.760 105.343 +*N top_left_grid_pin_39_[0]:8 *C 48.753 105.400 +*N top_left_grid_pin_39_[0]:9 *C 45.547 105.400 +*N top_left_grid_pin_39_[0]:10 *C 45.540 105.458 +*N top_left_grid_pin_39_[0]:11 *C 45.540 107.100 +*N top_left_grid_pin_39_[0]:12 *C 45.540 107.100 +*N top_left_grid_pin_39_[0]:13 *C 45.540 109.422 +*N top_left_grid_pin_39_[0]:14 *C 45.532 109.480 +*N top_left_grid_pin_39_[0]:15 *C 33.587 109.480 +*N top_left_grid_pin_39_[0]:16 *C 33.580 109.538 +*N top_left_grid_pin_39_[0]:17 *C 33.580 112.540 +*N top_left_grid_pin_39_[0]:18 *C 33.580 112.495 +*N top_left_grid_pin_39_[0]:19 *C 33.580 112.880 +*N top_left_grid_pin_39_[0]:20 *C 33.573 112.880 +*N top_left_grid_pin_39_[0]:21 *C 31.300 112.880 +*N top_left_grid_pin_39_[0]:22 *C 31.280 112.888 +*N top_left_grid_pin_39_[0]:23 *C 31.280 123.753 +*N top_left_grid_pin_39_[0]:24 *C 31.260 123.760 + +*CAP +0 top_left_grid_pin_39_[0] 0.00012167 +1 mux_top_track_4\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_16\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_39_[0]:4 0.0002603349 +5 top_left_grid_pin_39_[0]:5 0.0002603349 +6 top_left_grid_pin_39_[0]:6 0.0007604305 +7 top_left_grid_pin_39_[0]:7 0.0007604305 +8 top_left_grid_pin_39_[0]:8 0.0002345352 +9 top_left_grid_pin_39_[0]:9 0.0002345352 +10 top_left_grid_pin_39_[0]:10 8.974979e-05 +11 top_left_grid_pin_39_[0]:11 3.800104e-05 +12 top_left_grid_pin_39_[0]:12 0.0002398603 +13 top_left_grid_pin_39_[0]:13 0.0001156672 +14 top_left_grid_pin_39_[0]:14 0.0007823748 +15 top_left_grid_pin_39_[0]:15 0.0007823748 +16 top_left_grid_pin_39_[0]:16 0.0001850005 +17 top_left_grid_pin_39_[0]:17 3.510328e-05 +18 top_left_grid_pin_39_[0]:18 0.0002058197 +19 top_left_grid_pin_39_[0]:19 5.700936e-05 +20 top_left_grid_pin_39_[0]:20 0.0001665943 +21 top_left_grid_pin_39_[0]:21 0.0001665943 +22 top_left_grid_pin_39_[0]:22 0.0004973171 +23 top_left_grid_pin_39_[0]:23 0.0004973171 +24 top_left_grid_pin_39_[0]:24 0.00012167 +25 top_left_grid_pin_39_[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.357801e-05 +26 top_left_grid_pin_39_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.357801e-05 +27 top_left_grid_pin_39_[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 2.011554e-05 +28 top_left_grid_pin_39_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 2.011554e-05 +29 top_left_grid_pin_39_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 2.841497e-05 +30 top_left_grid_pin_39_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 2.841497e-05 + +*RES +0 top_left_grid_pin_39_[0] top_left_grid_pin_39_[0]:24 0.0002365666 +1 top_left_grid_pin_39_[0]:17 mux_top_track_4\/mux_l2_in_2_:A1 0.152 +2 top_left_grid_pin_39_[0]:18 top_left_grid_pin_39_[0]:17 0.0045 +3 top_left_grid_pin_39_[0]:18 top_left_grid_pin_39_[0]:16 0.002640625 +4 top_left_grid_pin_39_[0]:19 top_left_grid_pin_39_[0]:18 0.0001850962 +5 top_left_grid_pin_39_[0]:20 top_left_grid_pin_39_[0]:19 0.00341 +6 top_left_grid_pin_39_[0]:21 top_left_grid_pin_39_[0]:20 0.000356025 +7 top_left_grid_pin_39_[0]:22 top_left_grid_pin_39_[0]:21 0.00341 +8 top_left_grid_pin_39_[0]:24 top_left_grid_pin_39_[0]:23 0.00341 +9 top_left_grid_pin_39_[0]:23 top_left_grid_pin_39_[0]:22 0.001702183 +10 top_left_grid_pin_39_[0]:10 top_left_grid_pin_39_[0]:9 0.00341 +11 top_left_grid_pin_39_[0]:9 top_left_grid_pin_39_[0]:8 0.0005021166 +12 top_left_grid_pin_39_[0]:7 top_left_grid_pin_39_[0]:6 0.01235491 +13 top_left_grid_pin_39_[0]:8 top_left_grid_pin_39_[0]:7 0.00341 +14 top_left_grid_pin_39_[0]:5 top_left_grid_pin_39_[0]:4 0.002546875 +15 top_left_grid_pin_39_[0]:6 top_left_grid_pin_39_[0]:5 0.0045 +16 top_left_grid_pin_39_[0]:4 mux_top_track_16\/mux_l1_in_0_:A0 0.152 +17 top_left_grid_pin_39_[0]:11 mux_top_track_2\/mux_l1_in_1_:A1 0.152 +18 top_left_grid_pin_39_[0]:12 top_left_grid_pin_39_[0]:11 0.0045 +19 top_left_grid_pin_39_[0]:12 top_left_grid_pin_39_[0]:10 0.001466518 +20 top_left_grid_pin_39_[0]:13 top_left_grid_pin_39_[0]:12 0.002073661 +21 top_left_grid_pin_39_[0]:14 top_left_grid_pin_39_[0]:13 0.00341 +22 top_left_grid_pin_39_[0]:16 top_left_grid_pin_39_[0]:15 0.00341 +23 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:14 0.001871383 + +*END + +*D_NET right_top_grid_pin_43_[0] 0.01450043 //LENGTH 110.885 LUMPCC 0.002805223 DR + +*CONN +*P right_top_grid_pin_43_[0] I *L 0.29796 *C 111.930 126.480 +*I mux_right_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 112.820 82.280 +*I mux_right_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 82.630 69.700 +*I mux_right_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 92.175 96.900 +*N right_top_grid_pin_43_[0]:4 *C 92.138 96.900 +*N right_top_grid_pin_43_[0]:5 *C 91.585 96.900 +*N right_top_grid_pin_43_[0]:6 *C 91.540 96.855 +*N right_top_grid_pin_43_[0]:7 *C 91.540 82.338 +*N right_top_grid_pin_43_[0]:8 *C 91.547 82.280 +*N right_top_grid_pin_43_[0]:9 *C 82.668 69.700 +*N right_top_grid_pin_43_[0]:10 *C 93.795 69.700 +*N right_top_grid_pin_43_[0]:11 *C 93.840 69.745 +*N right_top_grid_pin_43_[0]:12 *C 93.840 82.223 +*N right_top_grid_pin_43_[0]:13 *C 93.840 82.280 +*N right_top_grid_pin_43_[0]:14 *C 112.782 82.280 +*N right_top_grid_pin_43_[0]:15 *C 111.825 82.280 +*N right_top_grid_pin_43_[0]:16 *C 111.780 82.280 +*N right_top_grid_pin_43_[0]:17 *C 111.785 82.295 +*N right_top_grid_pin_43_[0]:18 *C 112.213 82.280 +*N right_top_grid_pin_43_[0]:19 *C 112.220 82.620 +*N right_top_grid_pin_43_[0]:20 *C 112.240 82.627 +*N right_top_grid_pin_43_[0]:21 *C 112.240 93.153 +*N right_top_grid_pin_43_[0]:22 *C 112.220 93.160 +*N right_top_grid_pin_43_[0]:23 *C 110.868 93.160 +*N right_top_grid_pin_43_[0]:24 *C 110.860 93.218 +*N right_top_grid_pin_43_[0]:25 *C 110.860 126.422 +*N right_top_grid_pin_43_[0]:26 *C 110.868 126.480 + +*CAP +0 right_top_grid_pin_43_[0] 6.203078e-05 +1 mux_right_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_43_[0]:4 6.979069e-05 +5 right_top_grid_pin_43_[0]:5 6.979069e-05 +6 right_top_grid_pin_43_[0]:6 0.0009192078 +7 right_top_grid_pin_43_[0]:7 0.0009192078 +8 right_top_grid_pin_43_[0]:8 8.489231e-05 +9 right_top_grid_pin_43_[0]:9 0.0007873644 +10 right_top_grid_pin_43_[0]:10 0.0007873644 +11 right_top_grid_pin_43_[0]:11 0.0008171495 +12 right_top_grid_pin_43_[0]:12 0.0008171495 +13 right_top_grid_pin_43_[0]:13 0.0007023537 +14 right_top_grid_pin_43_[0]:14 0.000103875 +15 right_top_grid_pin_43_[0]:15 0.000103875 +16 right_top_grid_pin_43_[0]:16 3.769723e-05 +17 right_top_grid_pin_43_[0]:17 0.0006523885 +18 right_top_grid_pin_43_[0]:18 7.196584e-05 +19 right_top_grid_pin_43_[0]:19 3.703865e-05 +20 right_top_grid_pin_43_[0]:20 0.0006822762 +21 right_top_grid_pin_43_[0]:21 0.0006822762 +22 right_top_grid_pin_43_[0]:22 0.0001357112 +23 right_top_grid_pin_43_[0]:23 0.0001357112 +24 right_top_grid_pin_43_[0]:24 0.001475532 +25 right_top_grid_pin_43_[0]:25 0.001475532 +26 right_top_grid_pin_43_[0]:26 6.203078e-05 +27 right_top_grid_pin_43_[0]:6 chanx_left_in[2]:19 1.605322e-06 +28 right_top_grid_pin_43_[0]:7 chanx_left_in[2]:20 1.605322e-06 +29 right_top_grid_pin_43_[0]:8 chanx_left_in[2]:21 0.0001299446 +30 right_top_grid_pin_43_[0]:20 chanx_left_in[2]:12 6.742936e-06 +31 right_top_grid_pin_43_[0]:21 chanx_left_in[2]:13 6.742936e-06 +32 right_top_grid_pin_43_[0]:17 chanx_left_in[2]:13 0.0001566457 +33 right_top_grid_pin_43_[0]:17 chanx_left_in[2]:14 7.637979e-06 +34 right_top_grid_pin_43_[0]:17 chanx_left_in[2]:15 0.000311525 +35 right_top_grid_pin_43_[0]:17 chanx_left_in[2]:22 3.253301e-05 +36 right_top_grid_pin_43_[0]:13 chanx_left_in[2]:14 0.0001566457 +37 right_top_grid_pin_43_[0]:13 chanx_left_in[2]:21 3.253301e-05 +38 right_top_grid_pin_43_[0]:13 chanx_left_in[2]:22 0.0004414696 +39 right_top_grid_pin_43_[0]:18 chanx_left_in[2]:13 7.637979e-06 +40 right_top_grid_pin_43_[0]:8 chanx_left_in[10]:14 4.655867e-05 +41 right_top_grid_pin_43_[0]:17 chanx_left_in[10]:13 0.0003803437 +42 right_top_grid_pin_43_[0]:17 chanx_left_in[10]:14 1.290046e-05 +43 right_top_grid_pin_43_[0]:13 chanx_left_in[10]:13 4.655867e-05 +44 right_top_grid_pin_43_[0]:13 chanx_left_in[10]:14 0.0003803437 +45 right_top_grid_pin_43_[0]:10 chanx_left_in[10]:23 6.433597e-06 +46 right_top_grid_pin_43_[0]:9 chanx_left_in[10]:24 6.433597e-06 +47 right_top_grid_pin_43_[0]:18 chanx_left_in[10]:13 1.290046e-05 +48 right_top_grid_pin_43_[0]:19 right_top_grid_pin_47_[0]:17 8.305917e-06 +49 right_top_grid_pin_43_[0]:24 right_top_grid_pin_47_[0]:20 7.391894e-06 +50 right_top_grid_pin_43_[0]:24 right_top_grid_pin_47_[0]:18 0.0002940426 +51 right_top_grid_pin_43_[0]:25 right_top_grid_pin_47_[0] 7.391894e-06 +52 right_top_grid_pin_43_[0]:25 right_top_grid_pin_47_[0]:19 0.0002940426 +53 right_top_grid_pin_43_[0]:18 right_top_grid_pin_47_[0]:13 8.305917e-06 + +*RES +0 right_top_grid_pin_43_[0] right_top_grid_pin_43_[0]:26 0.0001664583 +1 right_top_grid_pin_43_[0]:4 mux_right_track_2\/mux_l1_in_1_:A0 0.152 +2 right_top_grid_pin_43_[0]:5 right_top_grid_pin_43_[0]:4 0.0004933036 +3 right_top_grid_pin_43_[0]:6 right_top_grid_pin_43_[0]:5 0.0045 +4 right_top_grid_pin_43_[0]:7 right_top_grid_pin_43_[0]:6 0.01296205 +5 right_top_grid_pin_43_[0]:8 right_top_grid_pin_43_[0]:7 0.00341 +6 right_top_grid_pin_43_[0]:19 right_top_grid_pin_43_[0]:18 4.699999e-05 +7 right_top_grid_pin_43_[0]:20 right_top_grid_pin_43_[0]:19 0.00341 +8 right_top_grid_pin_43_[0]:22 right_top_grid_pin_43_[0]:21 0.00341 +9 right_top_grid_pin_43_[0]:21 right_top_grid_pin_43_[0]:20 0.001648917 +10 right_top_grid_pin_43_[0]:24 right_top_grid_pin_43_[0]:23 0.00341 +11 right_top_grid_pin_43_[0]:23 right_top_grid_pin_43_[0]:22 0.0002118917 +12 right_top_grid_pin_43_[0]:25 right_top_grid_pin_43_[0]:24 0.02964732 +13 right_top_grid_pin_43_[0]:26 right_top_grid_pin_43_[0]:25 0.00341 +14 right_top_grid_pin_43_[0]:14 mux_right_track_4\/mux_l2_in_1_:A0 0.152 +15 right_top_grid_pin_43_[0]:15 right_top_grid_pin_43_[0]:14 0.0008549108 +16 right_top_grid_pin_43_[0]:16 right_top_grid_pin_43_[0]:15 0.0045 +17 right_top_grid_pin_43_[0]:17 right_top_grid_pin_43_[0]:16 0.00341 +18 right_top_grid_pin_43_[0]:17 right_top_grid_pin_43_[0]:13 0.002811383 +19 right_top_grid_pin_43_[0]:12 right_top_grid_pin_43_[0]:11 0.01114063 +20 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:12 0.00341 +21 right_top_grid_pin_43_[0]:13 right_top_grid_pin_43_[0]:8 0.0003591583 +22 right_top_grid_pin_43_[0]:10 right_top_grid_pin_43_[0]:9 0.009935267 +23 right_top_grid_pin_43_[0]:11 right_top_grid_pin_43_[0]:10 0.0045 +24 right_top_grid_pin_43_[0]:9 mux_right_track_16\/mux_l1_in_1_:A0 0.152 +25 right_top_grid_pin_43_[0]:18 right_top_grid_pin_43_[0]:17 6.6975e-05 + +*END + +*D_NET chany_bottom_in[19] 0.01588917 //LENGTH 91.835 LUMPCC 0.009418353 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 78.660 1.290 +*I mux_right_track_32\/mux_l1_in_2_:A0 I *L 0.001631 *C 76.535 70.040 +*I mux_left_track_1\/mux_l1_in_3_:A0 I *L 0.001631 *C 70.670 80.920 +*N chany_bottom_in[19]:3 *C 76.880 67.320 +*N chany_bottom_in[19]:4 *C 70.670 80.920 +*N chany_bottom_in[19]:5 *C 70.380 80.920 +*N chany_bottom_in[19]:6 *C 70.380 80.875 +*N chany_bottom_in[19]:7 *C 70.380 71.445 +*N chany_bottom_in[19]:8 *C 70.425 71.400 +*N chany_bottom_in[19]:9 *C 77.235 71.400 +*N chany_bottom_in[19]:10 *C 77.280 71.355 +*N chany_bottom_in[19]:11 *C 76.573 70.040 +*N chany_bottom_in[19]:12 *C 77.235 70.040 +*N chany_bottom_in[19]:13 *C 77.280 70.040 +*N chany_bottom_in[19]:14 *C 77.280 67.377 +*N chany_bottom_in[19]:15 *C 77.280 67.320 +*N chany_bottom_in[19]:16 *C 77.280 67.312 +*N chany_bottom_in[19]:17 *C 77.280 55.275 +*N chany_bottom_in[19]:18 *C 77.280 5.448 +*N chany_bottom_in[19]:19 *C 77.300 5.440 +*N chany_bottom_in[19]:20 *C 78.653 5.440 +*N chany_bottom_in[19]:21 *C 78.660 5.383 + +*CAP +0 chany_bottom_in[19] 0.0002619598 +1 mux_right_track_32\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_1\/mux_l1_in_3_:A0 1e-06 +3 chany_bottom_in[19]:3 0.0001073724 +4 chany_bottom_in[19]:4 6.419147e-05 +5 chany_bottom_in[19]:5 6.620643e-05 +6 chany_bottom_in[19]:6 0.0006582469 +7 chany_bottom_in[19]:7 0.0006582469 +8 chany_bottom_in[19]:8 0.0005148951 +9 chany_bottom_in[19]:9 0.0005148951 +10 chany_bottom_in[19]:10 8.161477e-05 +11 chany_bottom_in[19]:11 7.212688e-05 +12 chany_bottom_in[19]:12 7.212688e-05 +13 chany_bottom_in[19]:13 0.0002756324 +14 chany_bottom_in[19]:14 0.0001565474 +15 chany_bottom_in[19]:15 0.0001073724 +16 chany_bottom_in[19]:16 0.000179421 +17 chany_bottom_in[19]:17 0.001172172 +18 chany_bottom_in[19]:18 0.0009927505 +19 chany_bottom_in[19]:19 0.0001255396 +20 chany_bottom_in[19]:20 0.0001255396 +21 chany_bottom_in[19]:21 0.0002619598 +22 chany_bottom_in[19]:10 chany_bottom_in[5]:27 9.740587e-06 +23 chany_bottom_in[19]:13 chany_bottom_in[5]:27 1.823213e-05 +24 chany_bottom_in[19]:13 chany_bottom_in[5]:28 9.740587e-06 +25 chany_bottom_in[19]:14 chany_bottom_in[5]:28 1.823213e-05 +26 chany_bottom_in[19]:18 chany_bottom_in[5]:32 0.0006942847 +27 chany_bottom_in[19]:17 chany_bottom_in[5]:31 0.0006942847 +28 chany_bottom_in[19] chany_bottom_in[12] 1.227523e-05 +29 chany_bottom_in[19]:7 chany_bottom_in[12]:15 7.914725e-06 +30 chany_bottom_in[19]:6 chany_bottom_in[12]:14 7.914725e-06 +31 chany_bottom_in[19]:16 chany_bottom_in[12]:27 0.0005445902 +32 chany_bottom_in[19]:19 chany_bottom_in[12]:30 5.34126e-06 +33 chany_bottom_in[19]:18 chany_bottom_in[12]:28 0.0001179545 +34 chany_bottom_in[19]:18 chany_bottom_in[12]:29 0.002097627 +35 chany_bottom_in[19]:21 chany_bottom_in[12]:32 1.227523e-05 +36 chany_bottom_in[19]:20 chany_bottom_in[12]:31 5.34126e-06 +37 chany_bottom_in[19]:17 chany_bottom_in[12]:27 0.0001179545 +38 chany_bottom_in[19]:17 chany_bottom_in[12]:28 0.002642217 +39 chany_bottom_in[19]:16 chanx_left_in[1]:9 0.0005445902 +40 chany_bottom_in[19]:18 chanx_left_in[1]:10 0.0006566262 +41 chany_bottom_in[19]:17 chanx_left_in[1]:9 0.0006566262 +42 chany_bottom_in[19]:17 chanx_left_in[1]:10 0.0005445902 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:21 0.003654018 +1 chany_bottom_in[19]:9 chany_bottom_in[19]:8 0.006080357 +2 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.0045 +3 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.0045 +4 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.008419643 +5 chany_bottom_in[19]:5 chany_bottom_in[19]:4 0.0001576087 +6 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.0045 +7 chany_bottom_in[19]:4 mux_left_track_1\/mux_l1_in_3_:A0 0.152 +8 chany_bottom_in[19]:12 chany_bottom_in[19]:11 0.0005915179 +9 chany_bottom_in[19]:13 chany_bottom_in[19]:12 0.0045 +10 chany_bottom_in[19]:13 chany_bottom_in[19]:10 0.001174107 +11 chany_bottom_in[19]:11 mux_right_track_32\/mux_l1_in_2_:A0 0.152 +12 chany_bottom_in[19]:14 chany_bottom_in[19]:13 0.002377232 +13 chany_bottom_in[19]:15 chany_bottom_in[19]:14 0.00341 +14 chany_bottom_in[19]:15 chany_bottom_in[19]:3 5.69697e-05 +15 chany_bottom_in[19]:16 chany_bottom_in[19]:15 0.00341 +16 chany_bottom_in[19]:19 chany_bottom_in[19]:18 0.00341 +17 chany_bottom_in[19]:18 chany_bottom_in[19]:17 0.007806308 +18 chany_bottom_in[19]:21 chany_bottom_in[19]:20 0.00341 +19 chany_bottom_in[19]:20 chany_bottom_in[19]:19 0.0002118917 +20 chany_bottom_in[19]:17 chany_bottom_in[19]:16 0.001885875 + +*END + +*D_NET bottom_left_grid_pin_41_[0] 0.006432807 //LENGTH 55.920 LUMPCC 0.0004117222 DR + +*CONN +*P bottom_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 14.280 +*I mux_bottom_track_5\/mux_l2_in_5_:A0 I *L 0.001631 *C 33.755 15.300 +*I mux_bottom_track_33\/mux_l1_in_2_:A1 I *L 0.00198 *C 24.380 39.780 +*I mux_bottom_track_3\/mux_l1_in_4_:A1 I *L 0.00198 *C 41.500 28.900 +*N bottom_left_grid_pin_41_[0]:4 *C 41.462 28.900 +*N bottom_left_grid_pin_41_[0]:5 *C 24.343 39.780 +*N bottom_left_grid_pin_41_[0]:6 *C 23.965 39.780 +*N bottom_left_grid_pin_41_[0]:7 *C 23.920 39.735 +*N bottom_left_grid_pin_41_[0]:8 *C 23.920 28.945 +*N bottom_left_grid_pin_41_[0]:9 *C 23.965 28.900 +*N bottom_left_grid_pin_41_[0]:10 *C 39.560 28.900 +*N bottom_left_grid_pin_41_[0]:11 *C 39.560 28.855 +*N bottom_left_grid_pin_41_[0]:12 *C 39.560 17.738 +*N bottom_left_grid_pin_41_[0]:13 *C 39.553 17.680 +*N bottom_left_grid_pin_41_[0]:14 *C 34.047 17.680 +*N bottom_left_grid_pin_41_[0]:15 *C 34.040 17.623 +*N bottom_left_grid_pin_41_[0]:16 *C 34.040 15.368 +*N bottom_left_grid_pin_41_[0]:17 *C 33.755 15.300 +*N bottom_left_grid_pin_41_[0]:18 *C 33.755 15.300 +*N bottom_left_grid_pin_41_[0]:19 *C 33.755 14.338 +*N bottom_left_grid_pin_41_[0]:20 *C 33.748 14.280 + +*CAP +0 bottom_left_grid_pin_41_[0] 0.0002831886 +1 mux_bottom_track_5\/mux_l2_in_5_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_3\/mux_l1_in_4_:A1 1e-06 +4 bottom_left_grid_pin_41_[0]:4 0.00013035 +5 bottom_left_grid_pin_41_[0]:5 4.460846e-05 +6 bottom_left_grid_pin_41_[0]:6 4.460846e-05 +7 bottom_left_grid_pin_41_[0]:7 0.0005212071 +8 bottom_left_grid_pin_41_[0]:8 0.0005212071 +9 bottom_left_grid_pin_41_[0]:9 0.0008432023 +10 bottom_left_grid_pin_41_[0]:10 0.001022754 +11 bottom_left_grid_pin_41_[0]:11 0.0005100124 +12 bottom_left_grid_pin_41_[0]:12 0.0005100124 +13 bottom_left_grid_pin_41_[0]:13 0.0003603696 +14 bottom_left_grid_pin_41_[0]:14 0.0003603696 +15 bottom_left_grid_pin_41_[0]:15 0.0001643349 +16 bottom_left_grid_pin_41_[0]:16 0.0001908878 +17 bottom_left_grid_pin_41_[0]:17 3.282363e-05 +18 bottom_left_grid_pin_41_[0]:18 0.0001107567 +19 bottom_left_grid_pin_41_[0]:19 8.420384e-05 +20 bottom_left_grid_pin_41_[0]:20 0.0002831886 +21 bottom_left_grid_pin_41_[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0001337698 +22 bottom_left_grid_pin_41_[0]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0001337698 +23 bottom_left_grid_pin_41_[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.209128e-05 +24 bottom_left_grid_pin_41_[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.209128e-05 + +*RES +0 bottom_left_grid_pin_41_[0] bottom_left_grid_pin_41_[0]:20 0.000626275 +1 bottom_left_grid_pin_41_[0]:10 bottom_left_grid_pin_41_[0]:9 0.01392411 +2 bottom_left_grid_pin_41_[0]:10 bottom_left_grid_pin_41_[0]:4 0.001698661 +3 bottom_left_grid_pin_41_[0]:11 bottom_left_grid_pin_41_[0]:10 0.0045 +4 bottom_left_grid_pin_41_[0]:12 bottom_left_grid_pin_41_[0]:11 0.009926341 +5 bottom_left_grid_pin_41_[0]:13 bottom_left_grid_pin_41_[0]:12 0.00341 +6 bottom_left_grid_pin_41_[0]:15 bottom_left_grid_pin_41_[0]:14 0.00341 +7 bottom_left_grid_pin_41_[0]:14 bottom_left_grid_pin_41_[0]:13 0.00086245 +8 bottom_left_grid_pin_41_[0]:17 mux_bottom_track_5\/mux_l2_in_5_:A0 0.152 +9 bottom_left_grid_pin_41_[0]:18 bottom_left_grid_pin_41_[0]:17 0.0045 +10 bottom_left_grid_pin_41_[0]:18 bottom_left_grid_pin_41_[0]:16 0.0001548913 +11 bottom_left_grid_pin_41_[0]:19 bottom_left_grid_pin_41_[0]:18 0.0008593751 +12 bottom_left_grid_pin_41_[0]:20 bottom_left_grid_pin_41_[0]:19 0.00341 +13 bottom_left_grid_pin_41_[0]:4 mux_bottom_track_3\/mux_l1_in_4_:A1 0.152 +14 bottom_left_grid_pin_41_[0]:9 bottom_left_grid_pin_41_[0]:8 0.0045 +15 bottom_left_grid_pin_41_[0]:8 bottom_left_grid_pin_41_[0]:7 0.009633929 +16 bottom_left_grid_pin_41_[0]:6 bottom_left_grid_pin_41_[0]:5 0.0003370536 +17 bottom_left_grid_pin_41_[0]:7 bottom_left_grid_pin_41_[0]:6 0.0045 +18 bottom_left_grid_pin_41_[0]:5 mux_bottom_track_33\/mux_l1_in_2_:A1 0.152 +19 bottom_left_grid_pin_41_[0]:16 bottom_left_grid_pin_41_[0]:15 0.002013393 + +*END + +*D_NET left_top_grid_pin_47_[0] 0.008579556 //LENGTH 63.175 LUMPCC 0.001774615 DR + +*CONN +*P left_top_grid_pin_47_[0] I *L 0.29796 *C 3.220 102.070 +*I mux_left_track_5\/mux_l2_in_6_:A1 I *L 0.00198 *C 13.440 96.220 +*I mux_left_track_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 22.255 98.600 +*I mux_left_track_17\/mux_l2_in_3_:A1 I *L 0.00198 *C 26.780 66.980 +*N left_top_grid_pin_47_[0]:4 *C 26.742 66.980 +*N left_top_grid_pin_47_[0]:5 *C 26.265 66.980 +*N left_top_grid_pin_47_[0]:6 *C 26.220 66.980 +*N left_top_grid_pin_47_[0]:7 *C 26.220 67.320 +*N left_top_grid_pin_47_[0]:8 *C 26.213 67.320 +*N left_top_grid_pin_47_[0]:9 *C 22.100 67.320 +*N left_top_grid_pin_47_[0]:10 *C 22.080 67.328 +*N left_top_grid_pin_47_[0]:11 *C 22.080 98.593 +*N left_top_grid_pin_47_[0]:12 *C 22.255 98.600 +*N left_top_grid_pin_47_[0]:13 *C 22.080 98.600 +*N left_top_grid_pin_47_[0]:14 *C 22.080 98.600 +*N left_top_grid_pin_47_[0]:15 *C 22.073 98.600 +*N left_top_grid_pin_47_[0]:16 *C 13.340 96.220 +*N left_top_grid_pin_47_[0]:17 *C 13.340 96.265 +*N left_top_grid_pin_47_[0]:18 *C 13.340 98.543 +*N left_top_grid_pin_47_[0]:19 *C 13.340 98.600 +*N left_top_grid_pin_47_[0]:20 *C 3.228 98.600 +*N left_top_grid_pin_47_[0]:21 *C 3.220 98.657 + +*CAP +0 left_top_grid_pin_47_[0] 0.0001967642 +1 mux_left_track_5\/mux_l2_in_6_:A1 1e-06 +2 mux_left_track_3\/mux_l2_in_2_:A0 1e-06 +3 mux_left_track_17\/mux_l2_in_3_:A1 1e-06 +4 left_top_grid_pin_47_[0]:4 5.714603e-05 +5 left_top_grid_pin_47_[0]:5 5.714603e-05 +6 left_top_grid_pin_47_[0]:6 5.33959e-05 +7 left_top_grid_pin_47_[0]:7 5.967305e-05 +8 left_top_grid_pin_47_[0]:8 0.000394999 +9 left_top_grid_pin_47_[0]:9 0.000394999 +10 left_top_grid_pin_47_[0]:10 0.001690079 +11 left_top_grid_pin_47_[0]:11 0.001690079 +12 left_top_grid_pin_47_[0]:12 5.071073e-05 +13 left_top_grid_pin_47_[0]:13 5.393526e-05 +14 left_top_grid_pin_47_[0]:14 3.509143e-05 +15 left_top_grid_pin_47_[0]:15 0.000321311 +16 left_top_grid_pin_47_[0]:16 3.140201e-05 +17 left_top_grid_pin_47_[0]:17 0.0001464236 +18 left_top_grid_pin_47_[0]:18 0.0001464236 +19 left_top_grid_pin_47_[0]:19 0.0007734546 +20 left_top_grid_pin_47_[0]:20 0.0004521437 +21 left_top_grid_pin_47_[0]:21 0.0001967642 +22 left_top_grid_pin_47_[0]:15 chanx_left_in[12]:36 0.0002269089 +23 left_top_grid_pin_47_[0]:19 chanx_left_in[12]:36 0.000184694 +24 left_top_grid_pin_47_[0]:19 chanx_left_in[12]:37 0.0002269089 +25 left_top_grid_pin_47_[0]:19 chanx_left_in[12]:40 0.0001510612 +26 left_top_grid_pin_47_[0]:20 chanx_left_in[12] 0.0001510612 +27 left_top_grid_pin_47_[0]:20 chanx_left_in[12]:37 0.000184694 +28 left_top_grid_pin_47_[0]:11 chanx_left_in[0]:9 0.0003246435 +29 left_top_grid_pin_47_[0]:10 chanx_left_in[0]:10 0.0003246435 + +*RES +0 left_top_grid_pin_47_[0] left_top_grid_pin_47_[0]:21 0.003046875 +1 left_top_grid_pin_47_[0]:14 left_top_grid_pin_47_[0]:13 0.0045 +2 left_top_grid_pin_47_[0]:15 left_top_grid_pin_47_[0]:14 0.00341 +3 left_top_grid_pin_47_[0]:15 left_top_grid_pin_47_[0]:11 0.00341 +4 left_top_grid_pin_47_[0]:13 left_top_grid_pin_47_[0]:12 9.51087e-05 +5 left_top_grid_pin_47_[0]:12 mux_left_track_3\/mux_l2_in_2_:A0 0.152 +6 left_top_grid_pin_47_[0]:18 left_top_grid_pin_47_[0]:17 0.002033482 +7 left_top_grid_pin_47_[0]:19 left_top_grid_pin_47_[0]:18 0.00341 +8 left_top_grid_pin_47_[0]:19 left_top_grid_pin_47_[0]:15 0.001368092 +9 left_top_grid_pin_47_[0]:16 mux_left_track_5\/mux_l2_in_6_:A1 0.152 +10 left_top_grid_pin_47_[0]:17 left_top_grid_pin_47_[0]:16 0.0045 +11 left_top_grid_pin_47_[0]:11 left_top_grid_pin_47_[0]:10 0.004898183 +12 left_top_grid_pin_47_[0]:9 left_top_grid_pin_47_[0]:8 0.0006442916 +13 left_top_grid_pin_47_[0]:10 left_top_grid_pin_47_[0]:9 0.00341 +14 left_top_grid_pin_47_[0]:7 left_top_grid_pin_47_[0]:6 0.0001057692 +15 left_top_grid_pin_47_[0]:8 left_top_grid_pin_47_[0]:7 0.00341 +16 left_top_grid_pin_47_[0]:5 left_top_grid_pin_47_[0]:4 0.0004263393 +17 left_top_grid_pin_47_[0]:6 left_top_grid_pin_47_[0]:5 0.0045 +18 left_top_grid_pin_47_[0]:4 mux_left_track_17\/mux_l2_in_3_:A1 0.152 +19 left_top_grid_pin_47_[0]:21 left_top_grid_pin_47_[0]:20 0.00341 +20 left_top_grid_pin_47_[0]:20 left_top_grid_pin_47_[0]:19 0.001584292 + +*END + +*D_NET chanx_right_out[0] 0.002383213 //LENGTH 22.610 LUMPCC 0.0002982104 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 131.160 96.900 +*P chanx_right_out[0] O *L 0.7423 *C 140.375 84.320 +*N chanx_right_out[0]:2 *C 138.928 84.320 +*N chanx_right_out[0]:3 *C 138.920 84.377 +*N chanx_right_out[0]:4 *C 138.920 96.855 +*N chanx_right_out[0]:5 *C 138.875 96.900 +*N chanx_right_out[0]:6 *C 131.198 96.900 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 0.0001117597 +2 chanx_right_out[0]:2 0.0001117597 +3 chanx_right_out[0]:3 0.0004911487 +4 chanx_right_out[0]:4 0.0004911487 +5 chanx_right_out[0]:5 0.0004390931 +6 chanx_right_out[0]:6 0.0004390931 +7 chanx_right_out[0]:3 ropt_net_178:4 0.0001491052 +8 chanx_right_out[0]:4 ropt_net_178:5 0.0001491052 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:6 0.152 +1 chanx_right_out[0]:3 chanx_right_out[0]:2 0.00341 +2 chanx_right_out[0]:2 chanx_right_out[0] 0.000226775 +3 chanx_right_out[0]:5 chanx_right_out[0]:4 0.0045 +4 chanx_right_out[0]:4 chanx_right_out[0]:3 0.01114062 +5 chanx_right_out[0]:6 chanx_right_out[0]:5 0.006854911 + +*END + +*D_NET chany_bottom_out[4] 0.001325721 //LENGTH 13.830 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 96.545 14.960 +*P chany_bottom_out[4] O *L 0.7423 *C 96.600 1.290 +*N chany_bottom_out[4]:2 *C 96.600 14.915 +*N chany_bottom_out[4]:3 *C 96.545 14.960 + +*CAP +0 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[4] 0.0006493478 +2 chany_bottom_out[4]:2 0.0006493478 +3 chany_bottom_out[4]:3 2.602561e-05 + +*RES +0 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[4]:3 0.152 +1 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +2 chany_bottom_out[4]:2 chany_bottom_out[4] 0.01216518 + +*END + +*D_NET chanx_left_out[4] 0.001230442 //LENGTH 8.965 LUMPCC 0.0001344879 DR + +*CONN +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.440 77.520 +*P chanx_left_out[4] O *L 0.7423 *C 1.305 80.240 +*N chanx_left_out[4]:2 *C 5.060 80.240 +*N chanx_left_out[4]:3 *C 5.060 79.560 +*N chanx_left_out[4]:4 *C 6.433 79.560 +*N chanx_left_out[4]:5 *C 6.440 79.502 +*N chanx_left_out[4]:6 *C 6.440 77.565 +*N chanx_left_out[4]:7 *C 6.440 77.520 + +*CAP +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[4] 0.0002587717 +2 chanx_left_out[4]:2 0.000315295 +3 chanx_left_out[4]:3 0.0001802094 +4 chanx_left_out[4]:4 0.0001236862 +5 chanx_left_out[4]:5 9.031389e-05 +6 chanx_left_out[4]:6 9.031389e-05 +7 chanx_left_out[4]:7 3.636358e-05 +8 chanx_left_out[4]:5 BUF_net_89:3 6.203974e-05 +9 chanx_left_out[4]:6 BUF_net_89:4 6.203974e-05 +10 chanx_left_out[4]:2 BUF_net_89:3 5.204225e-06 +11 chanx_left_out[4]:3 BUF_net_89:4 5.204225e-06 + +*RES +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[4]:7 0.152 +1 chanx_left_out[4]:5 chanx_left_out[4]:4 0.00341 +2 chanx_left_out[4]:4 chanx_left_out[4]:3 0.000215025 +3 chanx_left_out[4]:7 chanx_left_out[4]:6 0.0045 +4 chanx_left_out[4]:6 chanx_left_out[4]:5 0.001729911 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.0005882833 +6 chanx_left_out[4]:3 chanx_left_out[4]:2 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size10_11_sram[1] 0.01127294 //LENGTH 70.820 LUMPCC 0.003380438 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 47.225 61.200 +*I mux_left_track_25\/mux_l2_in_3_:S I *L 0.00357 *C 19.220 67.320 +*I mux_left_track_25\/mux_l2_in_2_:S I *L 0.00357 *C 21.260 66.935 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.655 55.420 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 62.220 58.140 +*I mux_left_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 65.420 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:6 *C 65.383 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:7 *C 62.100 58.140 +*N mux_tree_tapbuf_size10_11_sram[1]:8 *C 62.100 58.185 +*N mux_tree_tapbuf_size10_11_sram[1]:9 *C 62.100 61.155 +*N mux_tree_tapbuf_size10_11_sram[1]:10 *C 62.100 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:11 *C 54.280 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:12 *C 54.280 60.860 +*N mux_tree_tapbuf_size10_11_sram[1]:13 *C 53.360 60.860 +*N mux_tree_tapbuf_size10_11_sram[1]:14 *C 53.360 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:15 *C 17.655 55.420 +*N mux_tree_tapbuf_size10_11_sram[1]:16 *C 17.940 55.420 +*N mux_tree_tapbuf_size10_11_sram[1]:17 *C 17.940 55.465 +*N mux_tree_tapbuf_size10_11_sram[1]:18 *C 17.940 59.783 +*N mux_tree_tapbuf_size10_11_sram[1]:19 *C 17.948 59.840 +*N mux_tree_tapbuf_size10_11_sram[1]:20 *C 21.260 66.935 +*N mux_tree_tapbuf_size10_11_sram[1]:21 *C 19.258 67.320 +*N mux_tree_tapbuf_size10_11_sram[1]:22 *C 21.260 67.305 +*N mux_tree_tapbuf_size10_11_sram[1]:23 *C 21.590 67.290 +*N mux_tree_tapbuf_size10_11_sram[1]:24 *C 21.620 67.275 +*N mux_tree_tapbuf_size10_11_sram[1]:25 *C 21.620 59.898 +*N mux_tree_tapbuf_size10_11_sram[1]:26 *C 21.620 59.840 +*N mux_tree_tapbuf_size10_11_sram[1]:27 *C 47.373 59.840 +*N mux_tree_tapbuf_size10_11_sram[1]:28 *C 47.380 59.898 +*N mux_tree_tapbuf_size10_11_sram[1]:29 *C 47.380 61.155 +*N mux_tree_tapbuf_size10_11_sram[1]:30 *C 47.425 61.200 +*N mux_tree_tapbuf_size10_11_sram[1]:31 *C 47.225 61.200 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_25\/mux_l2_in_3_:S 1e-06 +2 mux_left_track_25\/mux_l2_in_2_:S 1e-06 +3 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +5 mux_left_track_25\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_11_sram[1]:6 0.0002431879 +7 mux_tree_tapbuf_size10_11_sram[1]:7 3.193027e-05 +8 mux_tree_tapbuf_size10_11_sram[1]:8 0.0001828293 +9 mux_tree_tapbuf_size10_11_sram[1]:9 0.0001828293 +10 mux_tree_tapbuf_size10_11_sram[1]:10 0.0007980063 +11 mux_tree_tapbuf_size10_11_sram[1]:11 0.0005484692 +12 mux_tree_tapbuf_size10_11_sram[1]:12 0.0001110705 +13 mux_tree_tapbuf_size10_11_sram[1]:13 0.0001061202 +14 mux_tree_tapbuf_size10_11_sram[1]:14 0.0004588625 +15 mux_tree_tapbuf_size10_11_sram[1]:15 4.772248e-05 +16 mux_tree_tapbuf_size10_11_sram[1]:16 5.366551e-05 +17 mux_tree_tapbuf_size10_11_sram[1]:17 0.0002504822 +18 mux_tree_tapbuf_size10_11_sram[1]:18 0.0002504822 +19 mux_tree_tapbuf_size10_11_sram[1]:19 0.0002971378 +20 mux_tree_tapbuf_size10_11_sram[1]:20 6.059972e-05 +21 mux_tree_tapbuf_size10_11_sram[1]:21 0.0001590364 +22 mux_tree_tapbuf_size10_11_sram[1]:22 0.0002364777 +23 mux_tree_tapbuf_size10_11_sram[1]:23 4.656762e-05 +24 mux_tree_tapbuf_size10_11_sram[1]:24 0.000507718 +25 mux_tree_tapbuf_size10_11_sram[1]:25 0.000507718 +26 mux_tree_tapbuf_size10_11_sram[1]:26 0.001199511 +27 mux_tree_tapbuf_size10_11_sram[1]:27 0.0009023731 +28 mux_tree_tapbuf_size10_11_sram[1]:28 9.564605e-05 +29 mux_tree_tapbuf_size10_11_sram[1]:29 9.564605e-05 +30 mux_tree_tapbuf_size10_11_sram[1]:30 0.0004579043 +31 mux_tree_tapbuf_size10_11_sram[1]:31 5.451205e-05 +32 mux_tree_tapbuf_size10_11_sram[1]:26 chanx_right_in[17]:10 0.0005210789 +33 mux_tree_tapbuf_size10_11_sram[1]:26 chanx_right_in[17]:11 3.811777e-05 +34 mux_tree_tapbuf_size10_11_sram[1]:19 chanx_right_in[17]:10 3.811777e-05 +35 mux_tree_tapbuf_size10_11_sram[1]:27 chanx_right_in[17]:11 0.0005210789 +36 mux_tree_tapbuf_size10_11_sram[1]:30 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 6.024343e-06 +37 mux_tree_tapbuf_size10_11_sram[1]:10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 4.01371e-05 +38 mux_tree_tapbuf_size10_11_sram[1]:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 6.024343e-06 +39 mux_tree_tapbuf_size10_11_sram[1]:13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 4.645022e-07 +40 mux_tree_tapbuf_size10_11_sram[1]:12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 4.645022e-07 +41 mux_tree_tapbuf_size10_11_sram[1]:11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 4.01371e-05 +42 mux_tree_tapbuf_size10_11_sram[1]:26 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001078867 +43 mux_tree_tapbuf_size10_11_sram[1]:27 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001078867 +44 mux_tree_tapbuf_size10_11_sram[1]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.529015e-06 +45 mux_tree_tapbuf_size10_11_sram[1]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.529015e-06 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_11_sram[1]:31 0.152 +1 mux_tree_tapbuf_size10_11_sram[1]:25 mux_tree_tapbuf_size10_11_sram[1]:24 0.006587054 +2 mux_tree_tapbuf_size10_11_sram[1]:26 mux_tree_tapbuf_size10_11_sram[1]:25 0.00341 +3 mux_tree_tapbuf_size10_11_sram[1]:26 mux_tree_tapbuf_size10_11_sram[1]:19 0.0005753583 +4 mux_tree_tapbuf_size10_11_sram[1]:23 mux_tree_tapbuf_size10_11_sram[1]:22 0.00020625 +5 mux_tree_tapbuf_size10_11_sram[1]:24 mux_tree_tapbuf_size10_11_sram[1]:23 0.0045 +6 mux_tree_tapbuf_size10_11_sram[1]:18 mux_tree_tapbuf_size10_11_sram[1]:17 0.003854911 +7 mux_tree_tapbuf_size10_11_sram[1]:19 mux_tree_tapbuf_size10_11_sram[1]:18 0.00341 +8 mux_tree_tapbuf_size10_11_sram[1]:16 mux_tree_tapbuf_size10_11_sram[1]:15 0.0001440218 +9 mux_tree_tapbuf_size10_11_sram[1]:17 mux_tree_tapbuf_size10_11_sram[1]:16 0.0045 +10 mux_tree_tapbuf_size10_11_sram[1]:15 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size10_11_sram[1]:21 mux_left_track_25\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_11_sram[1]:30 mux_tree_tapbuf_size10_11_sram[1]:29 0.0045 +13 mux_tree_tapbuf_size10_11_sram[1]:30 mux_tree_tapbuf_size10_11_sram[1]:14 0.005299107 +14 mux_tree_tapbuf_size10_11_sram[1]:29 mux_tree_tapbuf_size10_11_sram[1]:28 0.001122768 +15 mux_tree_tapbuf_size10_11_sram[1]:28 mux_tree_tapbuf_size10_11_sram[1]:27 0.00341 +16 mux_tree_tapbuf_size10_11_sram[1]:27 mux_tree_tapbuf_size10_11_sram[1]:26 0.004034558 +17 mux_tree_tapbuf_size10_11_sram[1]:31 mux_tree_tapbuf_size10_11_sram[1]:30 0.0001086957 +18 mux_tree_tapbuf_size10_11_sram[1]:20 mux_left_track_25\/mux_l2_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_11_sram[1]:7 mux_left_track_25\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size10_11_sram[1]:8 mux_tree_tapbuf_size10_11_sram[1]:7 0.0045 +21 mux_tree_tapbuf_size10_11_sram[1]:10 mux_tree_tapbuf_size10_11_sram[1]:9 0.0045 +22 mux_tree_tapbuf_size10_11_sram[1]:10 mux_tree_tapbuf_size10_11_sram[1]:6 0.002930804 +23 mux_tree_tapbuf_size10_11_sram[1]:9 mux_tree_tapbuf_size10_11_sram[1]:8 0.002651786 +24 mux_tree_tapbuf_size10_11_sram[1]:6 mux_left_track_25\/mux_l2_in_1_:S 0.152 +25 mux_tree_tapbuf_size10_11_sram[1]:22 mux_tree_tapbuf_size10_11_sram[1]:21 0.001787947 +26 mux_tree_tapbuf_size10_11_sram[1]:22 mux_tree_tapbuf_size10_11_sram[1]:20 0.0003303571 +27 mux_tree_tapbuf_size10_11_sram[1]:14 mux_tree_tapbuf_size10_11_sram[1]:13 0.0003035715 +28 mux_tree_tapbuf_size10_11_sram[1]:13 mux_tree_tapbuf_size10_11_sram[1]:12 0.0008214286 +29 mux_tree_tapbuf_size10_11_sram[1]:12 mux_tree_tapbuf_size10_11_sram[1]:11 0.0003035715 +30 mux_tree_tapbuf_size10_11_sram[1]:11 mux_tree_tapbuf_size10_11_sram[1]:10 0.006982143 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[0] 0.01077587 //LENGTH 71.680 LUMPCC 0.003338609 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 126.345 60.860 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 82.975 60.860 +*I mux_right_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 74.420 58.480 +*I mux_right_track_16\/mux_l1_in_2_:S I *L 0.00357 *C 82.000 63.580 +*I mux_right_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 81.520 69.360 +*N mux_tree_tapbuf_size10_4_sram[0]:5 *C 81.558 69.360 +*N mux_tree_tapbuf_size10_4_sram[0]:6 *C 84.135 69.360 +*N mux_tree_tapbuf_size10_4_sram[0]:7 *C 84.180 69.315 +*N mux_tree_tapbuf_size10_4_sram[0]:8 *C 82.038 63.580 +*N mux_tree_tapbuf_size10_4_sram[0]:9 *C 84.135 63.580 +*N mux_tree_tapbuf_size10_4_sram[0]:10 *C 84.180 63.580 +*N mux_tree_tapbuf_size10_4_sram[0]:11 *C 74.420 58.480 +*N mux_tree_tapbuf_size10_4_sram[0]:12 *C 74.520 58.820 +*N mux_tree_tapbuf_size10_4_sram[0]:13 *C 84.135 58.820 +*N mux_tree_tapbuf_size10_4_sram[0]:14 *C 84.180 58.865 +*N mux_tree_tapbuf_size10_4_sram[0]:15 *C 83.013 60.860 +*N mux_tree_tapbuf_size10_4_sram[0]:16 *C 84.135 60.860 +*N mux_tree_tapbuf_size10_4_sram[0]:17 *C 84.180 60.815 +*N mux_tree_tapbuf_size10_4_sram[0]:18 *C 84.180 61.258 +*N mux_tree_tapbuf_size10_4_sram[0]:19 *C 84.188 61.200 +*N mux_tree_tapbuf_size10_4_sram[0]:20 *C 125.573 61.200 +*N mux_tree_tapbuf_size10_4_sram[0]:21 *C 125.580 61.200 +*N mux_tree_tapbuf_size10_4_sram[0]:22 *C 125.580 60.860 +*N mux_tree_tapbuf_size10_4_sram[0]:23 *C 125.625 60.860 +*N mux_tree_tapbuf_size10_4_sram[0]:24 *C 126.308 60.860 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_16\/mux_l1_in_0_:S 1e-06 +3 mux_right_track_16\/mux_l1_in_2_:S 1e-06 +4 mux_right_track_16\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_4_sram[0]:5 0.00022597 +6 mux_tree_tapbuf_size10_4_sram[0]:6 0.00022597 +7 mux_tree_tapbuf_size10_4_sram[0]:7 0.0002480756 +8 mux_tree_tapbuf_size10_4_sram[0]:8 0.0001458085 +9 mux_tree_tapbuf_size10_4_sram[0]:9 0.0001458085 +10 mux_tree_tapbuf_size10_4_sram[0]:10 0.000405047 +11 mux_tree_tapbuf_size10_4_sram[0]:11 6.46253e-05 +12 mux_tree_tapbuf_size10_4_sram[0]:12 0.0007084424 +13 mux_tree_tapbuf_size10_4_sram[0]:13 0.0006775995 +14 mux_tree_tapbuf_size10_4_sram[0]:14 0.0001203364 +15 mux_tree_tapbuf_size10_4_sram[0]:15 9.853566e-05 +16 mux_tree_tapbuf_size10_4_sram[0]:16 9.853566e-05 +17 mux_tree_tapbuf_size10_4_sram[0]:17 0.0001405708 +18 mux_tree_tapbuf_size10_4_sram[0]:18 0.0001438193 +19 mux_tree_tapbuf_size10_4_sram[0]:19 0.001877653 +20 mux_tree_tapbuf_size10_4_sram[0]:20 0.001877653 +21 mux_tree_tapbuf_size10_4_sram[0]:21 5.605841e-05 +22 mux_tree_tapbuf_size10_4_sram[0]:22 5.24492e-05 +23 mux_tree_tapbuf_size10_4_sram[0]:23 5.965218e-05 +24 mux_tree_tapbuf_size10_4_sram[0]:24 5.965218e-05 +25 mux_tree_tapbuf_size10_4_sram[0]:10 chanx_right_in[12]:14 0.0001470837 +26 mux_tree_tapbuf_size10_4_sram[0]:10 chanx_right_in[12]:15 5.669545e-05 +27 mux_tree_tapbuf_size10_4_sram[0]:18 chanx_right_in[12]:14 6.47749e-05 +28 mux_tree_tapbuf_size10_4_sram[0]:17 chanx_right_in[12]:15 5.908097e-05 +29 mux_tree_tapbuf_size10_4_sram[0]:7 chanx_right_in[12]:15 0.0001470837 +30 mux_tree_tapbuf_size10_4_sram[0]:13 chanx_right_in[12]:12 2.791096e-05 +31 mux_tree_tapbuf_size10_4_sram[0]:14 chanx_right_in[12]:14 5.100152e-05 +32 mux_tree_tapbuf_size10_4_sram[0]:12 chanx_right_in[12]:13 2.791096e-05 +33 mux_tree_tapbuf_size10_4_sram[0]:19 chany_bottom_in[11]:12 0.0003337995 +34 mux_tree_tapbuf_size10_4_sram[0]:20 chany_bottom_in[11]:13 0.0003337995 +35 mux_tree_tapbuf_size10_4_sram[0]:19 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004095896 +36 mux_tree_tapbuf_size10_4_sram[0]:21 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.906208e-07 +37 mux_tree_tapbuf_size10_4_sram[0]:20 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0004095896 +38 mux_tree_tapbuf_size10_4_sram[0]:22 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.906208e-07 +39 mux_tree_tapbuf_size10_4_sram[0]:19 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0006347537 +40 mux_tree_tapbuf_size10_4_sram[0]:20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0006347537 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_4_sram[0]:24 0.152 +1 mux_tree_tapbuf_size10_4_sram[0]:8 mux_right_track_16\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_4_sram[0]:9 mux_tree_tapbuf_size10_4_sram[0]:8 0.001872768 +3 mux_tree_tapbuf_size10_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size10_4_sram[0]:10 mux_tree_tapbuf_size10_4_sram[0]:7 0.005120536 +5 mux_tree_tapbuf_size10_4_sram[0]:18 mux_tree_tapbuf_size10_4_sram[0]:17 0.0002127404 +6 mux_tree_tapbuf_size10_4_sram[0]:18 mux_tree_tapbuf_size10_4_sram[0]:10 0.002073661 +7 mux_tree_tapbuf_size10_4_sram[0]:19 mux_tree_tapbuf_size10_4_sram[0]:18 0.00341 +8 mux_tree_tapbuf_size10_4_sram[0]:21 mux_tree_tapbuf_size10_4_sram[0]:20 0.00341 +9 mux_tree_tapbuf_size10_4_sram[0]:20 mux_tree_tapbuf_size10_4_sram[0]:19 0.006483649 +10 mux_tree_tapbuf_size10_4_sram[0]:23 mux_tree_tapbuf_size10_4_sram[0]:22 0.0045 +11 mux_tree_tapbuf_size10_4_sram[0]:22 mux_tree_tapbuf_size10_4_sram[0]:21 0.0001634615 +12 mux_tree_tapbuf_size10_4_sram[0]:24 mux_tree_tapbuf_size10_4_sram[0]:23 0.000609375 +13 mux_tree_tapbuf_size10_4_sram[0]:16 mux_tree_tapbuf_size10_4_sram[0]:15 0.001002232 +14 mux_tree_tapbuf_size10_4_sram[0]:17 mux_tree_tapbuf_size10_4_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size10_4_sram[0]:17 mux_tree_tapbuf_size10_4_sram[0]:14 0.001741072 +16 mux_tree_tapbuf_size10_4_sram[0]:15 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +17 mux_tree_tapbuf_size10_4_sram[0]:6 mux_tree_tapbuf_size10_4_sram[0]:5 0.00230134 +18 mux_tree_tapbuf_size10_4_sram[0]:7 mux_tree_tapbuf_size10_4_sram[0]:6 0.0045 +19 mux_tree_tapbuf_size10_4_sram[0]:5 mux_right_track_16\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_4_sram[0]:13 mux_tree_tapbuf_size10_4_sram[0]:12 0.008584823 +21 mux_tree_tapbuf_size10_4_sram[0]:14 mux_tree_tapbuf_size10_4_sram[0]:13 0.0045 +22 mux_tree_tapbuf_size10_4_sram[0]:11 mux_right_track_16\/mux_l1_in_0_:S 0.152 +23 mux_tree_tapbuf_size10_4_sram[0]:12 mux_tree_tapbuf_size10_4_sram[0]:11 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[2] 0.004570786 //LENGTH 31.730 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 39.865 47.600 +*I mux_bottom_track_25\/mux_l3_in_1_:S I *L 0.00357 *C 32.080 52.360 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 30.075 44.540 +*I mux_bottom_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 42.880 44.880 +*N mux_tree_tapbuf_size10_8_sram[2]:4 *C 42.880 44.880 +*N mux_tree_tapbuf_size10_8_sram[2]:5 *C 30.075 44.540 +*N mux_tree_tapbuf_size10_8_sram[2]:6 *C 32.043 52.360 +*N mux_tree_tapbuf_size10_8_sram[2]:7 *C 30.865 52.360 +*N mux_tree_tapbuf_size10_8_sram[2]:8 *C 30.820 52.315 +*N mux_tree_tapbuf_size10_8_sram[2]:9 *C 30.820 47.260 +*N mux_tree_tapbuf_size10_8_sram[2]:10 *C 30.360 47.260 +*N mux_tree_tapbuf_size10_8_sram[2]:11 *C 30.360 44.585 +*N mux_tree_tapbuf_size10_8_sram[2]:12 *C 30.405 44.540 +*N mux_tree_tapbuf_size10_8_sram[2]:13 *C 33.580 44.540 +*N mux_tree_tapbuf_size10_8_sram[2]:14 *C 33.580 44.200 +*N mux_tree_tapbuf_size10_8_sram[2]:15 *C 42.780 44.200 +*N mux_tree_tapbuf_size10_8_sram[2]:16 *C 42.780 44.540 +*N mux_tree_tapbuf_size10_8_sram[2]:17 *C 42.780 44.585 +*N mux_tree_tapbuf_size10_8_sram[2]:18 *C 42.780 47.555 +*N mux_tree_tapbuf_size10_8_sram[2]:19 *C 42.735 47.600 +*N mux_tree_tapbuf_size10_8_sram[2]:20 *C 39.903 47.600 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_25\/mux_l3_in_1_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_track_25\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_8_sram[2]:4 6.764835e-05 +5 mux_tree_tapbuf_size10_8_sram[2]:5 5.31312e-05 +6 mux_tree_tapbuf_size10_8_sram[2]:6 0.0001141255 +7 mux_tree_tapbuf_size10_8_sram[2]:7 0.0001141255 +8 mux_tree_tapbuf_size10_8_sram[2]:8 0.0003892972 +9 mux_tree_tapbuf_size10_8_sram[2]:9 0.0004232685 +10 mux_tree_tapbuf_size10_8_sram[2]:10 0.0002379235 +11 mux_tree_tapbuf_size10_8_sram[2]:11 0.0002039521 +12 mux_tree_tapbuf_size10_8_sram[2]:12 0.0002711672 +13 mux_tree_tapbuf_size10_8_sram[2]:13 0.0002714328 +14 mux_tree_tapbuf_size10_8_sram[2]:14 0.0006887327 +15 mux_tree_tapbuf_size10_8_sram[2]:15 0.0006956664 +16 mux_tree_tapbuf_size10_8_sram[2]:16 0.0001068189 +17 mux_tree_tapbuf_size10_8_sram[2]:17 0.0002235295 +18 mux_tree_tapbuf_size10_8_sram[2]:18 0.0002235295 +19 mux_tree_tapbuf_size10_8_sram[2]:19 0.0002412184 +20 mux_tree_tapbuf_size10_8_sram[2]:20 0.0002412184 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_8_sram[2]:20 0.152 +1 mux_tree_tapbuf_size10_8_sram[2]:4 mux_bottom_track_25\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_8_sram[2]:6 mux_bottom_track_25\/mux_l3_in_1_:S 0.152 +3 mux_tree_tapbuf_size10_8_sram[2]:7 mux_tree_tapbuf_size10_8_sram[2]:6 0.001051339 +4 mux_tree_tapbuf_size10_8_sram[2]:8 mux_tree_tapbuf_size10_8_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size10_8_sram[2]:12 mux_tree_tapbuf_size10_8_sram[2]:11 0.0045 +6 mux_tree_tapbuf_size10_8_sram[2]:12 mux_tree_tapbuf_size10_8_sram[2]:5 0.0001793479 +7 mux_tree_tapbuf_size10_8_sram[2]:11 mux_tree_tapbuf_size10_8_sram[2]:10 0.002388393 +8 mux_tree_tapbuf_size10_8_sram[2]:16 mux_tree_tapbuf_size10_8_sram[2]:15 0.0003035715 +9 mux_tree_tapbuf_size10_8_sram[2]:16 mux_tree_tapbuf_size10_8_sram[2]:4 0.0001847826 +10 mux_tree_tapbuf_size10_8_sram[2]:17 mux_tree_tapbuf_size10_8_sram[2]:16 0.0045 +11 mux_tree_tapbuf_size10_8_sram[2]:19 mux_tree_tapbuf_size10_8_sram[2]:18 0.0045 +12 mux_tree_tapbuf_size10_8_sram[2]:18 mux_tree_tapbuf_size10_8_sram[2]:17 0.002651786 +13 mux_tree_tapbuf_size10_8_sram[2]:20 mux_tree_tapbuf_size10_8_sram[2]:19 0.002529018 +14 mux_tree_tapbuf_size10_8_sram[2]:5 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +15 mux_tree_tapbuf_size10_8_sram[2]:13 mux_tree_tapbuf_size10_8_sram[2]:12 0.002834821 +16 mux_tree_tapbuf_size10_8_sram[2]:14 mux_tree_tapbuf_size10_8_sram[2]:13 0.0003035715 +17 mux_tree_tapbuf_size10_8_sram[2]:15 mux_tree_tapbuf_size10_8_sram[2]:14 0.008214287 +18 mux_tree_tapbuf_size10_8_sram[2]:10 mux_tree_tapbuf_size10_8_sram[2]:9 0.0004107143 +19 mux_tree_tapbuf_size10_8_sram[2]:9 mux_tree_tapbuf_size10_8_sram[2]:8 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_10_ccff_tail[0] 0.0009655723 //LENGTH 6.005 LUMPCC 0.0004736894 DR + +*CONN +*I mem_left_track_17\/FTB_23__74:X O *L 0 *C 33.790 56.440 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 32.845 60.860 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:2 *C 32.845 60.860 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:3 *C 33.120 60.860 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 *C 33.120 60.815 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 *C 33.120 56.485 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:6 *C 33.165 56.440 +*N mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:7 *C 33.753 56.440 + +*CAP +0 mem_left_track_17\/FTB_23__74:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:2 5.729685e-05 +3 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:3 5.33385e-05 +4 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 0.0001139967 +5 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 0.0001139967 +6 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:6 7.562707e-05 +7 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:7 7.562707e-05 +8 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 prog_clk[0]:476 0.0001184224 +9 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 prog_clk[0]:466 0.0001184224 +10 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001184224 +11 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001184224 + +*RES +0 mem_left_track_17\/FTB_23__74:X mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:6 0.0005245536 +2 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 0.003866071 +4 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:2 1e-05 +5 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_5_ccff_tail[0] 0.0005312377 //LENGTH 3.930 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/FTB_18__69:X O *L 0 *C 102.805 82.960 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 103.215 80.580 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 *C 103.178 80.580 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 *C 102.625 80.580 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 *C 102.580 80.625 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 *C 102.580 82.915 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 *C 102.580 82.960 +*N mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 *C 102.805 82.960 + +*CAP +0 mem_right_track_24\/FTB_18__69:X 1e-06 +1 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 5.687382e-05 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 5.687382e-05 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.0001502719 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0001502719 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 5.523504e-05 +7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 5.971118e-05 + +*RES +0 mem_right_track_24\/FTB_18__69:X mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_5_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size12_2_sram[3] 0.001631116 //LENGTH 16.065 LUMPCC 0 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 107.485 115.260 +*I mem_right_track_0\/FTB_3__54:A I *L 0.001746 *C 108.100 110.160 +*I mux_right_track_0\/mux_l4_in_0_:S I *L 0.00357 *C 107.520 101.320 +*N mux_tree_tapbuf_size12_2_sram[3]:3 *C 107.558 101.320 +*N mux_tree_tapbuf_size12_2_sram[3]:4 *C 108.055 101.320 +*N mux_tree_tapbuf_size12_2_sram[3]:5 *C 108.100 101.365 +*N mux_tree_tapbuf_size12_2_sram[3]:6 *C 108.100 110.160 +*N mux_tree_tapbuf_size12_2_sram[3]:7 *C 108.100 110.160 +*N mux_tree_tapbuf_size12_2_sram[3]:8 *C 108.100 115.215 +*N mux_tree_tapbuf_size12_2_sram[3]:9 *C 108.055 115.260 +*N mux_tree_tapbuf_size12_2_sram[3]:10 *C 107.523 115.260 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_0\/FTB_3__54:A 1e-06 +2 mux_right_track_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_2_sram[3]:3 6.681999e-05 +4 mux_tree_tapbuf_size12_2_sram[3]:4 6.681999e-05 +5 mux_tree_tapbuf_size12_2_sram[3]:5 0.0004428479 +6 mux_tree_tapbuf_size12_2_sram[3]:6 3.554653e-05 +7 mux_tree_tapbuf_size12_2_sram[3]:7 0.0006944368 +8 mux_tree_tapbuf_size12_2_sram[3]:8 0.0002234046 +9 mux_tree_tapbuf_size12_2_sram[3]:9 4.912018e-05 +10 mux_tree_tapbuf_size12_2_sram[3]:10 4.912018e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_2_sram[3]:10 0.152 +1 mux_tree_tapbuf_size12_2_sram[3]:3 mux_right_track_0\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_2_sram[3]:4 mux_tree_tapbuf_size12_2_sram[3]:3 0.0004441965 +3 mux_tree_tapbuf_size12_2_sram[3]:5 mux_tree_tapbuf_size12_2_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size12_2_sram[3]:9 mux_tree_tapbuf_size12_2_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size12_2_sram[3]:8 mux_tree_tapbuf_size12_2_sram[3]:7 0.004513393 +6 mux_tree_tapbuf_size12_2_sram[3]:10 mux_tree_tapbuf_size12_2_sram[3]:9 0.0004754465 +7 mux_tree_tapbuf_size12_2_sram[3]:6 mem_right_track_0\/FTB_3__54:A 0.152 +8 mux_tree_tapbuf_size12_2_sram[3]:7 mux_tree_tapbuf_size12_2_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size12_2_sram[3]:7 mux_tree_tapbuf_size12_2_sram[3]:5 0.007852679 + +*END + +*D_NET mux_tree_tapbuf_size12_4_sram[0] 0.009920618 //LENGTH 78.910 LUMPCC 0.001052055 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 99.665 61.200 +*I mux_bottom_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 80.860 36.430 +*I mux_bottom_track_1\/mux_l1_in_3_:S I *L 0.00357 *C 74.400 23.460 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 71.935 20.740 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 78.200 25.670 +*I mux_bottom_track_1\/mux_l1_in_4_:S I *L 0.00357 *C 73.500 36.040 +*I mux_bottom_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 85.920 58.480 +*N mux_tree_tapbuf_size12_4_sram[0]:7 *C 80.880 36.720 +*N mux_tree_tapbuf_size12_4_sram[0]:8 *C 73.538 36.040 +*N mux_tree_tapbuf_size12_4_sram[0]:9 *C 78.163 25.777 +*N mux_tree_tapbuf_size12_4_sram[0]:10 *C 71.972 20.740 +*N mux_tree_tapbuf_size12_4_sram[0]:11 *C 72.635 20.740 +*N mux_tree_tapbuf_size12_4_sram[0]:12 *C 72.680 20.785 +*N mux_tree_tapbuf_size12_4_sram[0]:13 *C 72.680 23.460 +*N mux_tree_tapbuf_size12_4_sram[0]:14 *C 74.362 23.460 +*N mux_tree_tapbuf_size12_4_sram[0]:15 *C 73.185 23.460 +*N mux_tree_tapbuf_size12_4_sram[0]:16 *C 73.140 23.505 +*N mux_tree_tapbuf_size12_4_sram[0]:17 *C 73.140 25.455 +*N mux_tree_tapbuf_size12_4_sram[0]:18 *C 73.185 25.500 +*N mux_tree_tapbuf_size12_4_sram[0]:19 *C 77.280 25.500 +*N mux_tree_tapbuf_size12_4_sram[0]:20 *C 77.280 25.840 +*N mux_tree_tapbuf_size12_4_sram[0]:21 *C 77.280 25.885 +*N mux_tree_tapbuf_size12_4_sram[0]:22 *C 77.280 35.995 +*N mux_tree_tapbuf_size12_4_sram[0]:23 *C 77.280 36.040 +*N mux_tree_tapbuf_size12_4_sram[0]:24 *C 80.860 36.040 +*N mux_tree_tapbuf_size12_4_sram[0]:25 *C 80.860 36.430 +*N mux_tree_tapbuf_size12_4_sram[0]:26 *C 80.935 36.720 +*N mux_tree_tapbuf_size12_4_sram[0]:27 *C 85.975 36.720 +*N mux_tree_tapbuf_size12_4_sram[0]:28 *C 86.020 36.765 +*N mux_tree_tapbuf_size12_4_sram[0]:29 *C 86.020 58.435 +*N mux_tree_tapbuf_size12_4_sram[0]:30 *C 85.920 58.480 +*N mux_tree_tapbuf_size12_4_sram[0]:31 *C 86.020 59.160 +*N mux_tree_tapbuf_size12_4_sram[0]:32 *C 97.935 59.160 +*N mux_tree_tapbuf_size12_4_sram[0]:33 *C 97.980 59.205 +*N mux_tree_tapbuf_size12_4_sram[0]:34 *C 97.980 61.155 +*N mux_tree_tapbuf_size12_4_sram[0]:35 *C 98.025 61.200 +*N mux_tree_tapbuf_size12_4_sram[0]:36 *C 99.627 61.200 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_1\/mux_l1_in_2_:S 1e-06 +2 mux_bottom_track_1\/mux_l1_in_3_:S 1e-06 +3 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +5 mux_bottom_track_1\/mux_l1_in_4_:S 1e-06 +6 mux_bottom_track_1\/mux_l1_in_1_:S 1e-06 +7 mux_tree_tapbuf_size12_4_sram[0]:7 2.727568e-05 +8 mux_tree_tapbuf_size12_4_sram[0]:8 0.0002757828 +9 mux_tree_tapbuf_size12_4_sram[0]:9 8.244219e-05 +10 mux_tree_tapbuf_size12_4_sram[0]:10 6.60634e-05 +11 mux_tree_tapbuf_size12_4_sram[0]:11 6.60634e-05 +12 mux_tree_tapbuf_size12_4_sram[0]:12 0.0001913023 +13 mux_tree_tapbuf_size12_4_sram[0]:13 0.00022079 +14 mux_tree_tapbuf_size12_4_sram[0]:14 9.675066e-05 +15 mux_tree_tapbuf_size12_4_sram[0]:15 9.675066e-05 +16 mux_tree_tapbuf_size12_4_sram[0]:16 0.0001831879 +17 mux_tree_tapbuf_size12_4_sram[0]:17 0.0001537003 +18 mux_tree_tapbuf_size12_4_sram[0]:18 0.0002524526 +19 mux_tree_tapbuf_size12_4_sram[0]:19 0.0002826327 +20 mux_tree_tapbuf_size12_4_sram[0]:20 0.0001126222 +21 mux_tree_tapbuf_size12_4_sram[0]:21 0.000448558 +22 mux_tree_tapbuf_size12_4_sram[0]:22 0.000448558 +23 mux_tree_tapbuf_size12_4_sram[0]:23 0.0005484131 +24 mux_tree_tapbuf_size12_4_sram[0]:24 0.0002616524 +25 mux_tree_tapbuf_size12_4_sram[0]:25 9.25286e-05 +26 mux_tree_tapbuf_size12_4_sram[0]:26 0.0003700253 +27 mux_tree_tapbuf_size12_4_sram[0]:27 0.0003368985 +28 mux_tree_tapbuf_size12_4_sram[0]:28 0.001130866 +29 mux_tree_tapbuf_size12_4_sram[0]:29 0.001130866 +30 mux_tree_tapbuf_size12_4_sram[0]:30 7.171711e-05 +31 mux_tree_tapbuf_size12_4_sram[0]:31 0.0007458373 +32 mux_tree_tapbuf_size12_4_sram[0]:32 0.0007015457 +33 mux_tree_tapbuf_size12_4_sram[0]:33 0.0001458145 +34 mux_tree_tapbuf_size12_4_sram[0]:34 0.0001458145 +35 mux_tree_tapbuf_size12_4_sram[0]:35 8.732635e-05 +36 mux_tree_tapbuf_size12_4_sram[0]:36 8.732635e-05 +37 mux_tree_tapbuf_size12_4_sram[0]:21 chany_bottom_in[8] 0.0002689463 +38 mux_tree_tapbuf_size12_4_sram[0]:22 chany_bottom_in[8]:35 0.0002689463 +39 mux_tree_tapbuf_size12_4_sram[0]:35 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 7.434293e-05 +40 mux_tree_tapbuf_size12_4_sram[0]:36 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 7.434293e-05 +41 mux_tree_tapbuf_size12_4_sram[0]:29 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001138527 +42 mux_tree_tapbuf_size12_4_sram[0]:28 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001138527 +43 mux_tree_tapbuf_size12_4_sram[0]:32 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.214543e-06 +44 mux_tree_tapbuf_size12_4_sram[0]:31 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.214543e-06 +45 mux_tree_tapbuf_size12_4_sram[0]:32 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.067087e-05 +46 mux_tree_tapbuf_size12_4_sram[0]:31 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.067087e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_4_sram[0]:36 0.152 +1 mux_tree_tapbuf_size12_4_sram[0]:9 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_4_sram[0]:14 mux_bottom_track_1\/mux_l1_in_3_:S 0.152 +3 mux_tree_tapbuf_size12_4_sram[0]:15 mux_tree_tapbuf_size12_4_sram[0]:14 0.001051339 +4 mux_tree_tapbuf_size12_4_sram[0]:16 mux_tree_tapbuf_size12_4_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size12_4_sram[0]:16 mux_tree_tapbuf_size12_4_sram[0]:13 0.0004107143 +6 mux_tree_tapbuf_size12_4_sram[0]:30 mux_tree_tapbuf_size12_4_sram[0]:29 0.0045 +7 mux_tree_tapbuf_size12_4_sram[0]:30 mux_bottom_track_1\/mux_l1_in_1_:S 0.152 +8 mux_tree_tapbuf_size12_4_sram[0]:29 mux_tree_tapbuf_size12_4_sram[0]:28 0.01934822 +9 mux_tree_tapbuf_size12_4_sram[0]:27 mux_tree_tapbuf_size12_4_sram[0]:26 0.0045 +10 mux_tree_tapbuf_size12_4_sram[0]:28 mux_tree_tapbuf_size12_4_sram[0]:27 0.0045 +11 mux_tree_tapbuf_size12_4_sram[0]:8 mux_bottom_track_1\/mux_l1_in_4_:S 0.152 +12 mux_tree_tapbuf_size12_4_sram[0]:25 mux_bottom_track_1\/mux_l1_in_2_:S 0.152 +13 mux_tree_tapbuf_size12_4_sram[0]:25 mux_tree_tapbuf_size12_4_sram[0]:24 0.0003482143 +14 mux_tree_tapbuf_size12_4_sram[0]:25 mux_tree_tapbuf_size12_4_sram[0]:7 0.0002589286 +15 mux_tree_tapbuf_size12_4_sram[0]:11 mux_tree_tapbuf_size12_4_sram[0]:10 0.0005915179 +16 mux_tree_tapbuf_size12_4_sram[0]:12 mux_tree_tapbuf_size12_4_sram[0]:11 0.0045 +17 mux_tree_tapbuf_size12_4_sram[0]:10 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size12_4_sram[0]:32 mux_tree_tapbuf_size12_4_sram[0]:31 0.01063839 +19 mux_tree_tapbuf_size12_4_sram[0]:33 mux_tree_tapbuf_size12_4_sram[0]:32 0.0045 +20 mux_tree_tapbuf_size12_4_sram[0]:35 mux_tree_tapbuf_size12_4_sram[0]:34 0.0045 +21 mux_tree_tapbuf_size12_4_sram[0]:34 mux_tree_tapbuf_size12_4_sram[0]:33 0.001741072 +22 mux_tree_tapbuf_size12_4_sram[0]:36 mux_tree_tapbuf_size12_4_sram[0]:35 0.001430804 +23 mux_tree_tapbuf_size12_4_sram[0]:18 mux_tree_tapbuf_size12_4_sram[0]:17 0.0045 +24 mux_tree_tapbuf_size12_4_sram[0]:17 mux_tree_tapbuf_size12_4_sram[0]:16 0.001741072 +25 mux_tree_tapbuf_size12_4_sram[0]:20 mux_tree_tapbuf_size12_4_sram[0]:19 0.0003035715 +26 mux_tree_tapbuf_size12_4_sram[0]:20 mux_tree_tapbuf_size12_4_sram[0]:9 0.0007879465 +27 mux_tree_tapbuf_size12_4_sram[0]:21 mux_tree_tapbuf_size12_4_sram[0]:20 0.0045 +28 mux_tree_tapbuf_size12_4_sram[0]:23 mux_tree_tapbuf_size12_4_sram[0]:22 0.0045 +29 mux_tree_tapbuf_size12_4_sram[0]:23 mux_tree_tapbuf_size12_4_sram[0]:8 0.003341518 +30 mux_tree_tapbuf_size12_4_sram[0]:22 mux_tree_tapbuf_size12_4_sram[0]:21 0.009026786 +31 mux_tree_tapbuf_size12_4_sram[0]:19 mux_tree_tapbuf_size12_4_sram[0]:18 0.00365625 +32 mux_tree_tapbuf_size12_4_sram[0]:24 mux_tree_tapbuf_size12_4_sram[0]:23 0.003196429 +33 mux_tree_tapbuf_size12_4_sram[0]:26 mux_tree_tapbuf_size12_4_sram[0]:25 0.0002589286 +34 mux_tree_tapbuf_size12_4_sram[0]:31 mux_tree_tapbuf_size12_4_sram[0]:30 0.0006071429 +35 mux_tree_tapbuf_size12_4_sram[0]:13 mux_tree_tapbuf_size12_4_sram[0]:12 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_2_ccff_tail[0] 0.0006441649 //LENGTH 5.020 LUMPCC 0.0001286952 DR + +*CONN +*I mem_right_track_0\/FTB_3__54:X O *L 0 *C 105.105 109.820 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 103.215 107.780 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:2 *C 103.215 107.780 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:3 *C 103.040 107.780 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 *C 103.040 107.825 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 *C 103.040 109.775 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:6 *C 103.085 109.820 +*N mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:7 *C 105.068 109.820 + +*CAP +0 mem_right_track_0\/FTB_3__54:X 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:2 4.937049e-05 +3 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:3 5.455634e-05 +4 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 7.89268e-05 +5 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 7.89268e-05 +6 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:6 0.0001258446 +7 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:7 0.0001258446 +8 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 right_top_grid_pin_46_[0]:15 6.434762e-05 +9 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 right_top_grid_pin_46_[0]:16 6.434762e-05 + +*RES +0 mem_right_track_0\/FTB_3__54:X mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size16_0_sram[3] 0.001992271 //LENGTH 16.275 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 38.485 104.380 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D I *L 0.001695 *C 39.275 109.820 +*I mux_top_track_4\/mux_l4_in_0_:S I *L 0.00357 *C 39.460 112.200 +*I mux_top_track_4\/mux_l4_in_1_:S I *L 0.00357 *C 42.200 101.660 +*N mux_tree_tapbuf_size16_0_sram[3]:4 *C 42.200 101.660 +*N mux_tree_tapbuf_size16_0_sram[3]:5 *C 42.320 101.705 +*N mux_tree_tapbuf_size16_0_sram[3]:6 *C 42.320 104.335 +*N mux_tree_tapbuf_size16_0_sram[3]:7 *C 42.275 104.380 +*N mux_tree_tapbuf_size16_0_sram[3]:8 *C 39.445 112.200 +*N mux_tree_tapbuf_size16_0_sram[3]:9 *C 39.123 112.200 +*N mux_tree_tapbuf_size16_0_sram[3]:10 *C 39.100 112.155 +*N mux_tree_tapbuf_size16_0_sram[3]:11 *C 39.275 109.820 +*N mux_tree_tapbuf_size16_0_sram[3]:12 *C 39.100 109.820 +*N mux_tree_tapbuf_size16_0_sram[3]:13 *C 39.100 109.820 +*N mux_tree_tapbuf_size16_0_sram[3]:14 *C 39.100 104.425 +*N mux_tree_tapbuf_size16_0_sram[3]:15 *C 39.100 104.380 +*N mux_tree_tapbuf_size16_0_sram[3]:16 *C 38.523 104.380 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D 1e-06 +2 mux_top_track_4\/mux_l4_in_0_:S 1e-06 +3 mux_top_track_4\/mux_l4_in_1_:S 1e-06 +4 mux_tree_tapbuf_size16_0_sram[3]:4 3.158786e-05 +5 mux_tree_tapbuf_size16_0_sram[3]:5 0.0001817696 +6 mux_tree_tapbuf_size16_0_sram[3]:6 0.0001817696 +7 mux_tree_tapbuf_size16_0_sram[3]:7 0.0001839943 +8 mux_tree_tapbuf_size16_0_sram[3]:8 5.214407e-05 +9 mux_tree_tapbuf_size16_0_sram[3]:9 5.214407e-05 +10 mux_tree_tapbuf_size16_0_sram[3]:10 0.0001341561 +11 mux_tree_tapbuf_size16_0_sram[3]:11 4.911497e-05 +12 mux_tree_tapbuf_size16_0_sram[3]:12 5.357799e-05 +13 mux_tree_tapbuf_size16_0_sram[3]:13 0.0004676988 +14 mux_tree_tapbuf_size16_0_sram[3]:14 0.0003017267 +15 mux_tree_tapbuf_size16_0_sram[3]:15 0.0002565248 +16 mux_tree_tapbuf_size16_0_sram[3]:16 4.206254e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size16_0_sram[3]:16 0.152 +1 mux_tree_tapbuf_size16_0_sram[3]:8 mux_top_track_4\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size16_0_sram[3]:9 mux_tree_tapbuf_size16_0_sram[3]:8 0.0001752718 +3 mux_tree_tapbuf_size16_0_sram[3]:10 mux_tree_tapbuf_size16_0_sram[3]:9 0.0045 +4 mux_tree_tapbuf_size16_0_sram[3]:15 mux_tree_tapbuf_size16_0_sram[3]:14 0.0045 +5 mux_tree_tapbuf_size16_0_sram[3]:15 mux_tree_tapbuf_size16_0_sram[3]:7 0.002834822 +6 mux_tree_tapbuf_size16_0_sram[3]:14 mux_tree_tapbuf_size16_0_sram[3]:13 0.004816965 +7 mux_tree_tapbuf_size16_0_sram[3]:4 mux_top_track_4\/mux_l4_in_1_:S 0.152 +8 mux_tree_tapbuf_size16_0_sram[3]:5 mux_tree_tapbuf_size16_0_sram[3]:4 0.0045 +9 mux_tree_tapbuf_size16_0_sram[3]:7 mux_tree_tapbuf_size16_0_sram[3]:6 0.0045 +10 mux_tree_tapbuf_size16_0_sram[3]:6 mux_tree_tapbuf_size16_0_sram[3]:5 0.002348214 +11 mux_tree_tapbuf_size16_0_sram[3]:12 mux_tree_tapbuf_size16_0_sram[3]:11 9.51087e-05 +12 mux_tree_tapbuf_size16_0_sram[3]:13 mux_tree_tapbuf_size16_0_sram[3]:12 0.0045 +13 mux_tree_tapbuf_size16_0_sram[3]:13 mux_tree_tapbuf_size16_0_sram[3]:10 0.002084821 +14 mux_tree_tapbuf_size16_0_sram[3]:11 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D 0.152 +15 mux_tree_tapbuf_size16_0_sram[3]:16 mux_tree_tapbuf_size16_0_sram[3]:15 0.000515625 + +*END + +*D_NET mux_tree_tapbuf_size16_2_sram[3] 0.002998912 //LENGTH 25.660 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 43.545 22.780 +*I mux_bottom_track_5\/mux_l4_in_1_:S I *L 0.00357 *C 40.840 14.960 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D I *L 0.001695 *C 39.735 17.340 +*I mux_bottom_track_5\/mux_l4_in_0_:S I *L 0.00357 *C 42.220 25.550 +*N mux_tree_tapbuf_size16_2_sram[3]:4 *C 42.220 25.550 +*N mux_tree_tapbuf_size16_2_sram[3]:5 *C 39.773 17.340 +*N mux_tree_tapbuf_size16_2_sram[3]:6 *C 40.435 17.340 +*N mux_tree_tapbuf_size16_2_sram[3]:7 *C 40.480 17.385 +*N mux_tree_tapbuf_size16_2_sram[3]:8 *C 40.480 25.115 +*N mux_tree_tapbuf_size16_2_sram[3]:9 *C 40.525 25.160 +*N mux_tree_tapbuf_size16_2_sram[3]:10 *C 42.220 25.160 +*N mux_tree_tapbuf_size16_2_sram[3]:11 *C 42.225 25.190 +*N mux_tree_tapbuf_size16_2_sram[3]:12 *C 42.320 25.115 +*N mux_tree_tapbuf_size16_2_sram[3]:13 *C 40.878 14.960 +*N mux_tree_tapbuf_size16_2_sram[3]:14 *C 42.275 14.960 +*N mux_tree_tapbuf_size16_2_sram[3]:15 *C 42.320 15.005 +*N mux_tree_tapbuf_size16_2_sram[3]:16 *C 42.320 22.780 +*N mux_tree_tapbuf_size16_2_sram[3]:17 *C 42.365 22.780 +*N mux_tree_tapbuf_size16_2_sram[3]:18 *C 43.508 22.780 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_track_5\/mux_l4_in_1_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D 1e-06 +3 mux_bottom_track_5\/mux_l4_in_0_:S 1e-06 +4 mux_tree_tapbuf_size16_2_sram[3]:4 5.407021e-05 +5 mux_tree_tapbuf_size16_2_sram[3]:5 6.838374e-05 +6 mux_tree_tapbuf_size16_2_sram[3]:6 6.838374e-05 +7 mux_tree_tapbuf_size16_2_sram[3]:7 0.0004335089 +8 mux_tree_tapbuf_size16_2_sram[3]:8 0.0004335089 +9 mux_tree_tapbuf_size16_2_sram[3]:9 0.0001450572 +10 mux_tree_tapbuf_size16_2_sram[3]:10 0.0001649071 +11 mux_tree_tapbuf_size16_2_sram[3]:11 4.510782e-05 +12 mux_tree_tapbuf_size16_2_sram[3]:12 0.0001300453 +13 mux_tree_tapbuf_size16_2_sram[3]:13 9.872569e-05 +14 mux_tree_tapbuf_size16_2_sram[3]:14 9.872569e-05 +15 mux_tree_tapbuf_size16_2_sram[3]:15 0.0004576211 +16 mux_tree_tapbuf_size16_2_sram[3]:16 0.0006183758 +17 mux_tree_tapbuf_size16_2_sram[3]:17 8.924563e-05 +18 mux_tree_tapbuf_size16_2_sram[3]:18 8.924563e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size16_2_sram[3]:18 0.152 +1 mux_tree_tapbuf_size16_2_sram[3]:11 mux_tree_tapbuf_size16_2_sram[3]:10 1e-05 +2 mux_tree_tapbuf_size16_2_sram[3]:11 mux_tree_tapbuf_size16_2_sram[3]:4 0.0003214286 +3 mux_tree_tapbuf_size16_2_sram[3]:12 mux_tree_tapbuf_size16_2_sram[3]:11 0.0045 +4 mux_tree_tapbuf_size16_2_sram[3]:14 mux_tree_tapbuf_size16_2_sram[3]:13 0.001247768 +5 mux_tree_tapbuf_size16_2_sram[3]:15 mux_tree_tapbuf_size16_2_sram[3]:14 0.0045 +6 mux_tree_tapbuf_size16_2_sram[3]:13 mux_bottom_track_5\/mux_l4_in_1_:S 0.152 +7 mux_tree_tapbuf_size16_2_sram[3]:4 mux_bottom_track_5\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size16_2_sram[3]:9 mux_tree_tapbuf_size16_2_sram[3]:8 0.0045 +9 mux_tree_tapbuf_size16_2_sram[3]:8 mux_tree_tapbuf_size16_2_sram[3]:7 0.006901786 +10 mux_tree_tapbuf_size16_2_sram[3]:6 mux_tree_tapbuf_size16_2_sram[3]:5 0.0005915178 +11 mux_tree_tapbuf_size16_2_sram[3]:7 mux_tree_tapbuf_size16_2_sram[3]:6 0.0045 +12 mux_tree_tapbuf_size16_2_sram[3]:5 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D 0.152 +13 mux_tree_tapbuf_size16_2_sram[3]:17 mux_tree_tapbuf_size16_2_sram[3]:16 0.0045 +14 mux_tree_tapbuf_size16_2_sram[3]:16 mux_tree_tapbuf_size16_2_sram[3]:15 0.006941965 +15 mux_tree_tapbuf_size16_2_sram[3]:16 mux_tree_tapbuf_size16_2_sram[3]:12 0.002084821 +16 mux_tree_tapbuf_size16_2_sram[3]:18 mux_tree_tapbuf_size16_2_sram[3]:17 0.001020089 +17 mux_tree_tapbuf_size16_2_sram[3]:10 mux_tree_tapbuf_size16_2_sram[3]:9 0.001513393 + +*END + +*D_NET mux_tree_tapbuf_size16_mem_0_ccff_tail[0] 0.0008827973 //LENGTH 7.390 LUMPCC 0.0001297848 DR + +*CONN +*I mem_top_track_4\/FTB_9__60:X O *L 0 *C 44.855 117.640 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 48.935 115.260 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:2 *C 48.898 115.260 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:3 *C 45.585 115.260 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:4 *C 45.540 115.305 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:5 *C 45.540 117.595 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:6 *C 45.495 117.640 +*N mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:7 *C 44.893 117.640 + +*CAP +0 mem_top_track_4\/FTB_9__60:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:2 0.0001790342 +3 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:3 0.0001790342 +4 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:4 0.0001317897 +5 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:5 0.0001317897 +6 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:6 6.468237e-05 +7 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:7 6.468237e-05 +8 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:2 prog_clk[0]:577 5.580219e-05 +9 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:3 prog_clk[0]:578 5.580219e-05 +10 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:4 prog_clk[0]:582 9.090217e-06 +11 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:5 prog_clk[0]:579 9.090217e-06 + +*RES +0 mem_top_track_4\/FTB_9__60:X mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:2 0.00295759 +3 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size16_mem_0_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[2] 0.00106844 //LENGTH 9.175 LUMPCC 0 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 95.065 63.920 +*I mux_right_track_32\/mux_l3_in_0_:S I *L 0.00357 *C 94.640 66.980 +*I mem_right_track_32\/FTB_26__77:A I *L 0.001746 *C 100.280 63.920 +*N mux_tree_tapbuf_size7_1_sram[2]:3 *C 100.243 63.920 +*N mux_tree_tapbuf_size7_1_sram[2]:4 *C 94.640 66.980 +*N mux_tree_tapbuf_size7_1_sram[2]:5 *C 94.760 66.935 +*N mux_tree_tapbuf_size7_1_sram[2]:6 *C 94.760 63.965 +*N mux_tree_tapbuf_size7_1_sram[2]:7 *C 94.760 63.920 +*N mux_tree_tapbuf_size7_1_sram[2]:8 *C 95.180 63.920 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_32\/FTB_26__77:A 1e-06 +3 mux_tree_tapbuf_size7_1_sram[2]:3 0.0003025154 +4 mux_tree_tapbuf_size7_1_sram[2]:4 2.806411e-05 +5 mux_tree_tapbuf_size7_1_sram[2]:5 0.0001824862 +6 mux_tree_tapbuf_size7_1_sram[2]:6 0.0001824862 +7 mux_tree_tapbuf_size7_1_sram[2]:7 4.989675e-05 +8 mux_tree_tapbuf_size7_1_sram[2]:8 0.0003199913 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_1_sram[2]:8 0.152 +1 mux_tree_tapbuf_size7_1_sram[2]:4 mux_right_track_32\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[2]:5 mux_tree_tapbuf_size7_1_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size7_1_sram[2]:7 mux_tree_tapbuf_size7_1_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size7_1_sram[2]:6 mux_tree_tapbuf_size7_1_sram[2]:5 0.002651786 +5 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:7 0.0002282609 +6 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:3 0.004520089 +7 mux_tree_tapbuf_size7_1_sram[2]:3 mem_right_track_32\/FTB_26__77:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[2] 0.00198237 //LENGTH 14.895 LUMPCC 8.614936e-05 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 14.565 69.360 +*I mem_left_track_33\/FTB_28__79:A I *L 0.001766 *C 6.900 63.920 +*I mux_left_track_33\/mux_l3_in_0_:S I *L 0.00357 *C 12.980 66.935 +*N mux_tree_tapbuf_size7_3_sram[2]:3 *C 12.980 66.935 +*N mux_tree_tapbuf_size7_3_sram[2]:4 *C 6.900 63.935 +*N mux_tree_tapbuf_size7_3_sram[2]:5 *C 6.900 64.260 +*N mux_tree_tapbuf_size7_3_sram[2]:6 *C 6.900 64.305 +*N mux_tree_tapbuf_size7_3_sram[2]:7 *C 6.900 67.275 +*N mux_tree_tapbuf_size7_3_sram[2]:8 *C 6.945 67.320 +*N mux_tree_tapbuf_size7_3_sram[2]:9 *C 12.980 67.320 +*N mux_tree_tapbuf_size7_3_sram[2]:10 *C 14.215 67.320 +*N mux_tree_tapbuf_size7_3_sram[2]:11 *C 14.260 67.365 +*N mux_tree_tapbuf_size7_3_sram[2]:12 *C 14.260 69.315 +*N mux_tree_tapbuf_size7_3_sram[2]:13 *C 14.260 69.360 +*N mux_tree_tapbuf_size7_3_sram[2]:14 *C 14.565 69.360 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_33\/FTB_28__79:A 1e-06 +2 mux_left_track_33\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_3_sram[2]:3 6.267594e-05 +4 mux_tree_tapbuf_size7_3_sram[2]:4 4.437236e-05 +5 mux_tree_tapbuf_size7_3_sram[2]:5 8.642007e-05 +6 mux_tree_tapbuf_size7_3_sram[2]:6 0.0001756668 +7 mux_tree_tapbuf_size7_3_sram[2]:7 0.0001756668 +8 mux_tree_tapbuf_size7_3_sram[2]:8 0.0004072789 +9 mux_tree_tapbuf_size7_3_sram[2]:9 0.0005122721 +10 mux_tree_tapbuf_size7_3_sram[2]:10 7.31356e-05 +11 mux_tree_tapbuf_size7_3_sram[2]:11 0.0001202147 +12 mux_tree_tapbuf_size7_3_sram[2]:12 0.0001202147 +13 mux_tree_tapbuf_size7_3_sram[2]:13 6.149268e-05 +14 mux_tree_tapbuf_size7_3_sram[2]:14 5.380985e-05 +15 mux_tree_tapbuf_size7_3_sram[2]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.300074e-05 +16 mux_tree_tapbuf_size7_3_sram[2]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.007394e-05 +17 mux_tree_tapbuf_size7_3_sram[2]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.007394e-05 +18 mux_tree_tapbuf_size7_3_sram[2]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.300074e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_3_sram[2]:14 0.152 +1 mux_tree_tapbuf_size7_3_sram[2]:8 mux_tree_tapbuf_size7_3_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size7_3_sram[2]:7 mux_tree_tapbuf_size7_3_sram[2]:6 0.002651786 +3 mux_tree_tapbuf_size7_3_sram[2]:5 mux_tree_tapbuf_size7_3_sram[2]:4 0.0001766304 +4 mux_tree_tapbuf_size7_3_sram[2]:6 mux_tree_tapbuf_size7_3_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size7_3_sram[2]:4 mem_left_track_33\/FTB_28__79:A 0.152 +6 mux_tree_tapbuf_size7_3_sram[2]:10 mux_tree_tapbuf_size7_3_sram[2]:9 0.001102678 +7 mux_tree_tapbuf_size7_3_sram[2]:11 mux_tree_tapbuf_size7_3_sram[2]:10 0.0045 +8 mux_tree_tapbuf_size7_3_sram[2]:13 mux_tree_tapbuf_size7_3_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size7_3_sram[2]:12 mux_tree_tapbuf_size7_3_sram[2]:11 0.001741072 +10 mux_tree_tapbuf_size7_3_sram[2]:14 mux_tree_tapbuf_size7_3_sram[2]:13 0.0001657609 +11 mux_tree_tapbuf_size7_3_sram[2]:3 mux_left_track_33\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_3_sram[2]:9 mux_tree_tapbuf_size7_3_sram[2]:8 0.005388393 +13 mux_tree_tapbuf_size7_3_sram[2]:9 mux_tree_tapbuf_size7_3_sram[2]:3 0.00034375 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001778962 //LENGTH 11.235 LUMPCC 0.0009403676 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_3_:X O *L 0 *C 82.975 96.900 +*I mux_top_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 74.710 99.015 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 74.710 99.015 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 79.535 98.940 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 79.580 98.895 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 79.580 96.945 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 79.625 96.900 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 82.938 96.900 + +*CAP +0 mux_top_track_0\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002375405 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001885593 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000100951 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000100951 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001042962 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001042962 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[2]:30 5.950011e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[2]:27 5.950011e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size12_0_sram[0]:28 4.751631e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size12_0_sram[0]:29 5.124316e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size12_0_sram[0]:8 5.124316e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size12_0_sram[0]:29 4.751631e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.002473e-06 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001067826 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.002473e-06 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001067826 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 6.711049e-05 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 6.711049e-05 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 optlc_net_151:8 0.0001310286 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 optlc_net_151:9 0.0001310286 + +*RES +0 mux_top_track_0\/mux_l1_in_3_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004308037 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001741071 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002957589 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001658012 //LENGTH 12.240 LUMPCC 0.0004857824 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_2_:X O *L 0 *C 67.795 91.800 +*I mux_top_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 61.545 96.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 61.583 96.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 62.515 96.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 62.560 96.175 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 62.560 93.885 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 62.605 93.840 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 66.655 93.840 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 66.700 93.795 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 66.700 91.845 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 66.745 91.800 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 67.758 91.800 + +*CAP +0 mux_top_track_2\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.303341e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.303341e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001232524 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001232524 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002075192 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002075192 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.756033e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.756033e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001037495 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001037495 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[4]:21 5.567338e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[4]:20 5.567338e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[1]:6 5.940874e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[1]:5 5.940874e-05 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_7_sram[0]:18 3.036074e-05 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size12_7_sram[0]:21 3.80396e-05 +18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size12_7_sram[0]:19 3.036074e-05 +19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size12_7_sram[0]:20 3.80396e-05 +20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size7_0_sram[0]:11 5.940874e-05 +21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size7_0_sram[0]:32 5.940874e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_2_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_2\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008325893 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003616072 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001741072 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0009040179 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.002387349 //LENGTH 17.455 LUMPCC 0.0007172747 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_0_:X O *L 0 *C 100.565 106.760 +*I mux_right_track_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 108.660 101.660 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 108.623 101.660 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 98.945 101.660 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 98.900 101.705 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 98.900 106.715 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 98.945 106.760 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 100.528 106.760 + +*CAP +0 mux_right_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0005205263 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0005205263 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001911902 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001911902 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001223207 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001223207 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_2_sram[2]:15 0.0001360495 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_2_sram[2]:9 1.513421e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_2_sram[2]:16 0.0001360495 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size12_2_sram[2]:8 1.513421e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 2.13963e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001437823 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 2.13963e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001437823 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 3.624125e-08 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 3.624125e-08 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.217107e-05 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.768464e-08 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.217107e-05 +21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.768464e-08 + +*RES +0 mux_right_track_0\/mux_l3_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_0\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.008640626 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.004473215 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001412946 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009022629 //LENGTH 5.240 LUMPCC 0.0006465317 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_3_:X O *L 0 *C 77.105 22.780 +*I mux_bottom_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 82.055 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 82.017 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 77.142 22.780 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001268656 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001268656 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 bottom_left_grid_pin_38_[0]:4 0.0001894436 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 bottom_left_grid_pin_38_[0]:6 0.0001894436 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size12_4_sram[1]:23 0.0001338222 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size12_4_sram[1]:24 0.0001338222 + +*RES +0 mux_bottom_track_1\/mux_l1_in_3_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004352679 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0] 0.0005140263 //LENGTH 3.590 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/mux_l4_in_0_:X O *L 0 *C 62.275 8.840 +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 61.530 6.665 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 61.530 6.665 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 61.640 6.800 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 61.640 6.845 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 61.640 8.795 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 61.685 8.840 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 62.238 8.840 + +*CAP +0 mux_bottom_track_3\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 5.880001e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 6.204231e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0001317611 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0001317611 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 6.383088e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 6.383088e-05 + +*RES +0 mux_bottom_track_3\/mux_l4_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0004933036 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.001741072 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 5.978261e-05 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001188276 //LENGTH 8.950 LUMPCC 0.0002520925 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_3_:X O *L 0 *C 56.405 22.440 +*I mux_bottom_track_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 59.515 17.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 59.515 17.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 59.340 17.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 59.340 17.385 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 59.340 22.395 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 59.295 22.440 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 56.443 22.440 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.65068e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.064469e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002055668 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002055668 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.000212949 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.000212949 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 1.894885e-06 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 1.894885e-06 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001239674 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.839679e-07 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001239674 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.839679e-07 + +*RES +0 mux_bottom_track_3\/mux_l2_in_3_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_3\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.002546875 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0008620737 //LENGTH 7.210 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_2_:X O *L 0 *C 20.065 80.920 +*I mux_left_track_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 18.960 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 18.860 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 18.890 85.370 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 18.905 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 19.320 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 19.320 80.965 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 19.365 80.920 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 20.027 80.920 + +*CAP +0 mux_left_track_1\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.384803e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 1.799033e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.943968e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003197766 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002883273 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.534592e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 7.534592e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0005915179 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.004209822 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_1\/mux_l3_in_1_:A1 0.152 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.00019375 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003705357 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002906401 //LENGTH 18.925 LUMPCC 0.0008806189 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_0_:X O *L 0 *C 60.435 98.600 +*I mux_left_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 45.445 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 45.483 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 45.955 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 46.000 96.265 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 46.000 98.543 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 46.008 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 60.713 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 60.720 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 60.720 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 60.435 98.600 + +*CAP +0 mux_left_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.462049e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.462049e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001744982 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001744982 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0007098942 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0007098942 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 3.315616e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.721385e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:10 5.538672e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[12]:10 0.0001500628 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[12]:11 0.0001500628 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[12]:36 0.000104839 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[12]:37 0.0001854077 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[12]:35 0.000104839 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[12]:36 0.0001854077 + +*RES +0 mux_left_track_3\/mux_l2_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002033482 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.002303783 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0045 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001548913 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008260628 //LENGTH 5.720 LUMPCC 0.0003446419 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_1_:X O *L 0 *C 35.705 123.080 +*I mux_top_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 34.675 119.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 34.675 119.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 34.960 119.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 34.960 119.045 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 34.960 120.360 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 35.420 120.360 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 35.420 123.035 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 35.420 123.080 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 35.705 123.080 + +*CAP +0 mux_top_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.972403e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.418138e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.62223e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.550417e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.928588e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000110004 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.203565e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 6.246343e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_left_grid_pin_36_[0]:12 1.0088e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 top_left_grid_pin_36_[0]:13 3.148822e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_36_[0]:13 1.0088e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 top_left_grid_pin_36_[0]:12 3.148822e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 top_left_grid_pin_38_[0]:11 2.728752e-09 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 top_left_grid_pin_38_[0]:10 2.728752e-09 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_left_grid_pin_38_[0]:11 6.072849e-05 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 top_left_grid_pin_38_[0]:10 6.072849e-05 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size16_0_sram[1]:45 4.184134e-05 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size16_0_sram[1]:41 2.817215e-05 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size16_0_sram[1]:41 4.184134e-05 +21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size16_0_sram[1]:45 2.817215e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001548913 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002388393 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001548913 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001174107 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004107143 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001800453 //LENGTH 14.145 LUMPCC 0.0005956857 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_4_:X O *L 0 *C 116.555 85.680 +*I mux_right_track_4\/mux_l3_in_2_:A1 I *L 0.00198 *C 116.840 72.420 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 116.840 72.435 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 116.840 72.760 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 116.840 72.805 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 116.840 85.635 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 116.840 85.680 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 116.555 85.680 + +*CAP +0 mux_right_track_4\/mux_l2_in_4_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_2_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.54633e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 7.39638e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004859577 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004859577 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.180543e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.961931e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_left_in[13]:14 0.0001543679 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[13]:15 0.0001543679 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size16_1_sram[2]:23 5.688926e-06 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size16_1_sram[2]:24 5.688926e-06 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_1_sram[2]:11 6.292351e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_1_sram[2]:18 1.606462e-05 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_1_sram[2]:22 1.942662e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_1_sram[2]:26 3.522693e-05 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_1_sram[2]:27 4.144345e-06 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_1_sram[2]:8 6.292351e-05 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_1_sram[2]:11 1.606462e-05 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_1_sram[2]:19 1.942662e-05 +20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_1_sram[2]:22 3.522693e-05 +21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_1_sram[2]:26 4.144345e-06 + +*RES +0 mux_right_track_4\/mux_l2_in_4_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_4\/mux_l3_in_2_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001766304 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01145536 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005700511 //LENGTH 3.945 LUMPCC 8.751261e-05 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 39.275 39.440 +*I mux_bottom_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 39.560 36.380 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 39.560 36.395 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 39.560 36.720 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 39.560 36.765 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 39.560 39.395 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 39.560 39.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 39.275 39.440 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.621866e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.966083e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001314435 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001314435 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.550275e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.626924e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.375631e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.375631e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001766305 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0] 0.0003280205 //LENGTH 2.475 LUMPCC 7.652918e-05 DR + +*CONN +*I mux_left_track_5\/mux_l4_in_1_:X O *L 0 *C 12.135 87.720 +*I mux_left_track_5\/mux_l5_in_0_:A0 I *L 0.001631 *C 9.950 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 *C 9.988 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 *C 12.098 87.720 + +*CAP +0 mux_left_track_5\/mux_l4_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l5_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.0001247456 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0001247456 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 3.826459e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 3.826459e-05 + +*RES +0 mux_left_track_5\/mux_l4_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_left_track_5\/mux_l5_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.001883929 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0005603923 //LENGTH 3.510 LUMPCC 0.0001204387 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_6_:X O *L 0 *C 15.005 96.220 +*I mux_left_track_5\/mux_l3_in_3_:A1 I *L 0.00198 *C 14.625 94.180 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 14.663 94.180 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 15.135 94.180 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 15.180 94.225 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 15.180 96.175 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 15.180 96.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 15.005 96.220 + +*CAP +0 mux_left_track_5\/mux_l2_in_6_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_3_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.073705e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.073705e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 9.057646e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 9.057646e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.74066e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.791994e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 optlc_net_150:24 1.7895e-06 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 optlc_net_150:29 5.842985e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 optlc_net_150:25 1.7895e-06 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 optlc_net_150:28 5.842985e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_6_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_5\/mux_l3_in_3_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.000421875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.001741071 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0] 0.009456175 //LENGTH 81.590 LUMPCC 0.001461658 DR + +*CONN +*I mux_top_track_8\/mux_l4_in_0_:X O *L 0 *C 110.575 48.280 +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 104.155 120.855 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 106.010 116.960 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 104.193 120.755 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 106.675 120.700 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 106.720 120.655 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 106.720 117.018 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 106.718 116.960 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 106.720 116.953 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 106.720 104.915 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 106.720 55.088 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 106.740 55.080 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 110.392 55.080 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 110.400 55.023 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 110.400 48.325 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 110.400 48.280 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 *C 110.575 48.280 + +*CAP +0 mux_top_track_8\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.711402e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001469509 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001469509 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001931074 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001931074 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.711402e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004216728 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.002829621 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.002407948 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0002951925 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0002951925 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0004130229 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0004130229 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.340912e-05 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 4.908889e-05 +17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_right_in[1]:9 0.0003234702 +18 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_right_in[1]:20 0.0001496196 +19 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_right_in[1]:20 0.0003234702 +20 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_right_in[1]:21 0.0001496196 +21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001784746 +22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.926479e-05 +23 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.926479e-05 +24 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001784746 + +*RES +0 mux_top_track_8\/mux_l4_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 9.51087e-05 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.00597991 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.00341 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.000572225 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.00341 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.007806308 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001039141 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.003247768 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.002216518 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001885875 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0] 0.009545706 //LENGTH 60.865 LUMPCC 0.003492071 DR + +*CONN +*I mux_top_track_24\/mux_l4_in_0_:X O *L 0 *C 67.445 78.200 +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.675 123.910 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 80.675 123.910 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 77.785 123.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 77.740 123.715 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 77.740 119.738 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 77.733 119.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 76.380 119.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 76.360 119.672 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 76.360 85.688 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 76.340 85.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 67.627 85.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 67.620 85.623 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 67.620 78.245 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 67.620 78.200 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 67.445 78.200 + +*CAP +0 mux_top_track_24\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001570035 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001242424 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002502833 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002502833 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.38805e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.38805e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001467143 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001467143 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0005894642 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0005894642 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0004359105 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0004359105 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:14 5.877708e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:15 5.825137e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_top_in[18]:38 1.620843e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_top_in[18]:37 1.620843e-05 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_top_in[18]:36 0.00123919 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chany_top_in[18]:35 0.00123919 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chany_bottom_in[10]:27 4.559518e-05 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chany_bottom_in[10]:29 0.000273996 +22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 chany_bottom_in[10]:31 1.159724e-05 +23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 chany_bottom_in[10]:28 4.559518e-05 +24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 chany_bottom_in[10]:30 0.000273996 +25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 chany_bottom_in[10]:30 1.159724e-05 +26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.529409e-05 +27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.529409e-05 +28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 ropt_net_208:10 0.0001041544 +29 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 ropt_net_208:9 0.0001041544 + +*RES +0 mux_top_track_24\/mux_l4_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.002580357 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.003551339 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002118917 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.005324316 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.001364958 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.006587054 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:14 9.51087e-05 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001720255 //LENGTH 12.380 LUMPCC 0.0005137787 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 75.725 87.720 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.100 85.340 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.100 85.340 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 85.100 85.385 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 85.100 87.675 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 85.055 87.720 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 75.763 87.720 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.828441e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00012316 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00012316 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004599357 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004599357 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_5_sram[0]:6 0.0001494229 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_5_sram[0]:7 0.0001494229 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.131968e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.131968e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.614678e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.614678e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.008296875 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008449443 //LENGTH 7.275 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 96.885 27.880 +*I mux_bottom_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 99.000 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 98.963 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 97.105 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 97.060 23.505 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 97.060 27.835 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 97.060 27.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 96.885 27.880 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001392059 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001392059 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002306518 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002306518 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.371375e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.95153e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001658482 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003866072 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002867178 //LENGTH 22.095 LUMPCC 0.0005363335 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_1_:X O *L 0 *C 75.615 42.840 +*I mux_bottom_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 65.610 31.960 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 65.648 31.960 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.655 31.960 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 66.700 32.005 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 66.700 41.775 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 66.745 41.820 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 67.620 41.820 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 67.620 42.840 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 75.578 42.840 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.464655e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.464655e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004641908 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004641908 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.447939e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001362213 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0005311054 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004793635 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[17]:21 6.842775e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[17]:24 6.842775e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[17]:21 1.286319e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_top_in[17]:24 1.286319e-05 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_right_in[11]:4 0.0001290283 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[11]:3 0.0001290283 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.738351e-06 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.738351e-06 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.110917e-05 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.110917e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008995536 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.008723215 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.007104911 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0007812501 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0009107144 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003798599 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_1_:X O *L 0 *C 46.635 44.540 +*I mux_bottom_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 43.990 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 44.028 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 46.598 44.540 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001889299 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001889299 + +*RES +0 mux_bottom_track_25\/mux_l2_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002294643 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002185314 //LENGTH 16.400 LUMPCC 0.0004042769 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 52.615 75.480 +*I mux_left_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 43.605 69.020 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 43.643 69.020 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 44.115 69.020 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 44.160 69.065 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 44.160 75.435 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 44.205 75.480 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 52.578 75.480 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.892575e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.892575e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003828381 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003828381 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004477548 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004477548 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_9_sram[1]:15 5.741025e-06 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_9_sram[1]:11 1.659984e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_9_sram[1]:17 0.0001797976 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_9_sram[1]:14 5.741025e-06 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_9_sram[1]:6 1.659984e-05 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_9_sram[1]:12 0.0001797976 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000421875 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0056875 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.007475447 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006399313 //LENGTH 3.970 LUMPCC 0.0002158948 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_2_:X O *L 0 *C 59.975 50.660 +*I mux_left_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 59.245 52.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 59.283 52.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 60.215 52.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 60.260 52.655 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 60.260 50.705 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 60.260 50.660 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 59.975 50.660 + +*CAP +0 mux_left_track_17\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.479517e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.479517e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.929271e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.929271e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.830728e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.55535e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_bottom_in[8]:24 3.377081e-07 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_bottom_in[8]:25 3.377081e-07 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[8]:25 3.377081e-07 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[8]:26 3.377081e-07 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[8]:27 5.957162e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[8]:28 5.957162e-05 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_10_sram[1]:23 4.770038e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_10_sram[1]:24 4.770038e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_2_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_17\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008325893 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001176723 //LENGTH 8.215 LUMPCC 0.0002323325 DR + +*CONN +*I mux_left_track_25\/mux_l3_in_0_:X O *L 0 *C 22.255 60.520 +*I mux_left_track_25\/mux_l4_in_0_:A1 I *L 0.00198 *C 16.100 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 16.137 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 18.355 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 18.400 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 18.860 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 18.860 60.565 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 18.905 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 22.218 60.520 + +*CAP +0 mux_left_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001338729 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001338729 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.771475e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001077257 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.301226e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002130958 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0002130958 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size10_11_sram[2]:11 3.728035e-06 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_tree_tapbuf_size10_11_sram[2]:12 4.516658e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_11_sram[2]:10 3.728035e-06 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size10_11_sram[2]:11 4.516658e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_11_sram[2]:9 2.482205e-05 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_11_sram[2]:11 4.244958e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_11_sram[2]:8 2.482205e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_11_sram[2]:10 4.244958e-05 + +*RES +0 mux_left_track_25\/mux_l3_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.002957589 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0008705358 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001979911 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_25\/mux_l4_in_0_:A1 0.152 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004107143 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001528799 //LENGTH 10.575 LUMPCC 0.0001333678 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_2_:X O *L 0 *C 78.485 68.680 +*I mux_right_track_32\/mux_l2_in_1_:A1 I *L 0.00198 *C 88.320 69.020 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 88.320 69.020 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 88.320 68.680 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 78.523 68.680 + +*CAP +0 mux_right_track_32\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.70448e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0006822115 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0006541745 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[10]:12 6.668392e-05 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[10]:13 6.668392e-05 + +*RES +0 mux_right_track_32\/mux_l1_in_2_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.008747769 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_32\/mux_l2_in_1_:A1 0.152 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.000306559 //LENGTH 2.305 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_2_:X O *L 0 *C 22.715 39.780 +*I mux_bottom_track_33\/mux_l2_in_1_:A1 I *L 0.00198 *C 20.700 39.780 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 20.738 39.780 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.678 39.780 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001522795 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001522795 + +*RES +0 mux_bottom_track_33\/mux_l1_in_2_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001732143 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_33\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001620842 //LENGTH 13.285 LUMPCC 0.0004398084 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_0_:X O *L 0 *C 24.555 77.520 +*I mux_left_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 20.700 69.020 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 20.738 69.020 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 22.955 69.020 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 23.000 69.065 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 23.000 77.475 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 23.045 77.520 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 24.518 77.520 + +*CAP +0 mux_left_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001267699 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001267699 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003251428 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003251428 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001376042 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001376042 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:622 5.759682e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:628 3.523901e-05 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:628 5.759682e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:633 3.523901e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 left_top_grid_pin_44_[0]:9 8.569815e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 left_top_grid_pin_44_[0]:10 4.687418e-06 +14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 left_top_grid_pin_44_[0]:4 2.087337e-08 +15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 left_top_grid_pin_44_[0]:6 8.569815e-05 +16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 left_top_grid_pin_44_[0]:9 4.687418e-06 +17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 left_top_grid_pin_44_[0]:5 2.087337e-08 +18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.666192e-05 +19 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.666192e-05 + +*RES +0 mux_left_track_33\/mux_l1_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007508929 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001979911 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_33\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET ropt_net_203 0.001679886 //LENGTH 11.190 LUMPCC 0.0008374487 DR + +*CONN +*I FTB_12__11:X O *L 0 *C 74.980 3.400 +*I ropt_mt_inst_844:A I *L 0.001766 *C 79.120 9.520 +*N ropt_net_203:2 *C 79.083 9.520 +*N ropt_net_203:3 *C 77.325 9.520 +*N ropt_net_203:4 *C 77.280 9.475 +*N ropt_net_203:5 *C 77.280 3.445 +*N ropt_net_203:6 *C 77.235 3.400 +*N ropt_net_203:7 *C 75.017 3.400 + +*CAP +0 FTB_12__11:X 1e-06 +1 ropt_mt_inst_844:A 1e-06 +2 ropt_net_203:2 0.0001415012 +3 ropt_net_203:3 0.0001415012 +4 ropt_net_203:4 0.0001558434 +5 ropt_net_203:5 0.0001558434 +6 ropt_net_203:6 0.000122874 +7 ropt_net_203:7 0.000122874 +8 ropt_net_203:5 chany_bottom_in[8] 0.0001639234 +9 ropt_net_203:4 chany_bottom_in[8]:35 0.0001639234 +10 ropt_net_203:5 chany_bottom_in[16] 0.0001613416 +11 ropt_net_203:4 chany_bottom_in[16]:33 0.0001613416 +12 ropt_net_203:7 ropt_net_170:5 9.345935e-05 +13 ropt_net_203:6 ropt_net_170:4 9.345935e-05 + +*RES +0 FTB_12__11:X ropt_net_203:7 0.152 +1 ropt_net_203:7 ropt_net_203:6 0.001979911 +2 ropt_net_203:6 ropt_net_203:5 0.0045 +3 ropt_net_203:5 ropt_net_203:4 0.005383929 +4 ropt_net_203:3 ropt_net_203:2 0.001569197 +5 ropt_net_203:4 ropt_net_203:3 0.0045 +6 ropt_net_203:2 ropt_mt_inst_844:A 0.152 + +*END + +*D_NET ropt_net_194 0.001735924 //LENGTH 14.110 LUMPCC 0.0002137133 DR + +*CONN +*I FTB_21__20:X O *L 0 *C 13.340 99.620 +*I ropt_mt_inst_834:A I *L 0.001766 *C 3.220 96.560 +*N ropt_net_194:2 *C 3.258 96.560 +*N ropt_net_194:3 *C 4.555 96.560 +*N ropt_net_194:4 *C 4.600 96.605 +*N ropt_net_194:5 *C 4.600 99.575 +*N ropt_net_194:6 *C 4.645 99.620 +*N ropt_net_194:7 *C 13.303 99.620 + +*CAP +0 FTB_21__20:X 1e-06 +1 ropt_mt_inst_834:A 1e-06 +2 ropt_net_194:2 9.927939e-05 +3 ropt_net_194:3 9.927939e-05 +4 ropt_net_194:4 0.0001942558 +5 ropt_net_194:5 0.0001942558 +6 ropt_net_194:6 0.0004665703 +7 ropt_net_194:7 0.0004665703 +8 ropt_net_194:7 left_top_grid_pin_49_[0]:23 0.0001068566 +9 ropt_net_194:6 left_top_grid_pin_49_[0]:24 0.0001068566 + +*RES +0 FTB_21__20:X ropt_net_194:7 0.152 +1 ropt_net_194:7 ropt_net_194:6 0.007729911 +2 ropt_net_194:6 ropt_net_194:5 0.0045 +3 ropt_net_194:5 ropt_net_194:4 0.002651786 +4 ropt_net_194:3 ropt_net_194:2 0.001158482 +5 ropt_net_194:4 ropt_net_194:3 0.0045 +6 ropt_net_194:2 ropt_mt_inst_834:A 0.152 + +*END + +*D_NET ropt_net_195 0.000133967 //LENGTH 1.210 LUMPCC 0 DR + +*CONN +*I FTB_33__32:X O *L 0 *C 93.380 121.040 +*I ropt_mt_inst_835:A I *L 0.001766 *C 94.300 121.040 +*N ropt_net_195:2 *C 94.263 121.040 +*N ropt_net_195:3 *C 93.418 121.040 + +*CAP +0 FTB_33__32:X 1e-06 +1 ropt_mt_inst_835:A 1e-06 +2 ropt_net_195:2 6.598348e-05 +3 ropt_net_195:3 6.598348e-05 + +*RES +0 FTB_33__32:X ropt_net_195:3 0.152 +1 ropt_net_195:2 ropt_mt_inst_835:A 0.152 +2 ropt_net_195:3 ropt_net_195:2 0.0007544643 + +*END + +*D_NET chanx_left_out[9] 0.0008393262 //LENGTH 5.385 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 4.140 71.400 +*P chanx_left_out[9] O *L 0.7423 *C 1.305 69.360 +*N chanx_left_out[9]:2 *C 4.133 69.360 +*N chanx_left_out[9]:3 *C 4.140 69.418 +*N chanx_left_out[9]:4 *C 4.140 71.355 +*N chanx_left_out[9]:5 *C 4.140 71.400 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chanx_left_out[9] 0.0002524593 +2 chanx_left_out[9]:2 0.0002524593 +3 chanx_left_out[9]:3 0.0001494256 +4 chanx_left_out[9]:4 0.0001494256 +5 chanx_left_out[9]:5 3.455644e-05 + +*RES +0 ropt_mt_inst_804:X chanx_left_out[9]:5 0.152 +1 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +2 chanx_left_out[9]:2 chanx_left_out[9] 0.000442975 +3 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +4 chanx_left_out[9]:4 chanx_left_out[9]:3 0.001729911 + +*END + +*D_NET ropt_net_209 0.001628616 //LENGTH 9.780 LUMPCC 0.0006255966 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 87.595 3.400 +*I ropt_mt_inst_848:A I *L 0.001766 *C 79.120 4.080 +*N ropt_net_209:2 *C 79.120 4.080 +*N ropt_net_209:3 *C 79.120 4.035 +*N ropt_net_209:4 *C 79.120 3.445 +*N ropt_net_209:5 *C 79.165 3.400 +*N ropt_net_209:6 *C 87.558 3.400 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 ropt_mt_inst_848:A 1e-06 +2 ropt_net_209:2 3.452414e-05 +3 ropt_net_209:3 7.32003e-05 +4 ropt_net_209:4 7.32003e-05 +5 ropt_net_209:5 0.0004100473 +6 ropt_net_209:6 0.0004100473 +7 ropt_net_209:6 chany_top_in[9]:8 0.0002551299 +8 ropt_net_209:5 chany_top_in[9]:9 0.0002551299 +9 ropt_net_209:6 ropt_net_170:4 5.766841e-05 +10 ropt_net_209:5 ropt_net_170:5 5.766841e-05 + +*RES +0 ropt_mt_inst_808:X ropt_net_209:6 0.152 +1 ropt_net_209:6 ropt_net_209:5 0.007493304 +2 ropt_net_209:5 ropt_net_209:4 0.0045 +3 ropt_net_209:4 ropt_net_209:3 0.0005267857 +4 ropt_net_209:2 ropt_mt_inst_848:A 0.152 +5 ropt_net_209:3 ropt_net_209:2 0.0045 + +*END + +*D_NET ropt_net_216 0.0008506184 //LENGTH 6.635 LUMPCC 9.070242e-05 DR + +*CONN +*I ropt_mt_inst_813:X O *L 0 *C 7.095 86.360 +*I ropt_mt_inst_858:A I *L 0.001767 *C 3.220 88.400 +*N ropt_net_216:2 *C 3.258 88.400 +*N ropt_net_216:3 *C 6.855 88.400 +*N ropt_net_216:4 *C 6.900 88.355 +*N ropt_net_216:5 *C 6.900 86.405 +*N ropt_net_216:6 *C 6.900 86.360 +*N ropt_net_216:7 *C 7.095 86.360 + +*CAP +0 ropt_mt_inst_813:X 1e-06 +1 ropt_mt_inst_858:A 1e-06 +2 ropt_net_216:2 0.0002239789 +3 ropt_net_216:3 0.0002239789 +4 ropt_net_216:4 9.608878e-05 +5 ropt_net_216:5 9.608878e-05 +6 ropt_net_216:6 5.932732e-05 +7 ropt_net_216:7 5.845318e-05 +8 ropt_net_216:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 4.535121e-05 +9 ropt_net_216:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 4.535121e-05 + +*RES +0 ropt_mt_inst_813:X ropt_net_216:7 0.152 +1 ropt_net_216:7 ropt_net_216:6 0.0001059783 +2 ropt_net_216:6 ropt_net_216:5 0.0045 +3 ropt_net_216:5 ropt_net_216:4 0.001741072 +4 ropt_net_216:3 ropt_net_216:2 0.003212054 +5 ropt_net_216:4 ropt_net_216:3 0.0045 +6 ropt_net_216:2 ropt_mt_inst_858:A 0.152 + +*END + +*D_NET ropt_net_213 0.001765645 //LENGTH 11.195 LUMPCC 0.0007444102 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 75.635 124.100 +*I ropt_mt_inst_854:A I *L 0.001766 *C 68.540 126.480 +*N ropt_net_213:2 *C 68.540 126.480 +*N ropt_net_213:3 *C 68.540 126.820 +*N ropt_net_213:4 *C 74.935 126.820 +*N ropt_net_213:5 *C 74.980 126.775 +*N ropt_net_213:6 *C 74.980 124.145 +*N ropt_net_213:7 *C 75.025 124.100 +*N ropt_net_213:8 *C 75.597 124.100 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 ropt_mt_inst_854:A 1e-06 +2 ropt_net_213:2 6.703804e-05 +3 ropt_net_213:3 0.0003707497 +4 ropt_net_213:4 0.0003383406 +5 ropt_net_213:5 5.92928e-05 +6 ropt_net_213:6 5.92928e-05 +7 ropt_net_213:7 6.226016e-05 +8 ropt_net_213:8 6.226016e-05 +9 ropt_net_213:6 chany_top_in[6]:30 7.752684e-05 +10 ropt_net_213:5 chany_top_in[6]:31 7.752684e-05 +11 ropt_net_213:8 chany_bottom_in[2]:6 1.45462e-05 +12 ropt_net_213:7 chany_bottom_in[2]:7 1.45462e-05 +13 ropt_net_213:6 chany_bottom_in[2]:9 7.752684e-05 +14 ropt_net_213:5 chany_bottom_in[2]:10 7.752684e-05 +15 ropt_net_213:4 chany_bottom_in[18]:5 5.957258e-05 +16 ropt_net_213:4 chany_bottom_in[18]:9 3.878967e-06 +17 ropt_net_213:3 chany_bottom_in[18]:6 5.957258e-05 +18 ropt_net_213:3 chany_bottom_in[18]:10 3.878967e-06 +19 ropt_net_213:4 chany_top_out[3]:4 0.0001391537 +20 ropt_net_213:3 chany_top_out[3]:3 0.0001391537 + +*RES +0 ropt_mt_inst_821:X ropt_net_213:8 0.152 +1 ropt_net_213:8 ropt_net_213:7 0.0005111608 +2 ropt_net_213:7 ropt_net_213:6 0.0045 +3 ropt_net_213:6 ropt_net_213:5 0.002348214 +4 ropt_net_213:4 ropt_net_213:3 0.005709822 +5 ropt_net_213:5 ropt_net_213:4 0.0045 +6 ropt_net_213:2 ropt_mt_inst_854:A 0.152 +7 ropt_net_213:3 ropt_net_213:2 0.0003035715 + +*END + +*D_NET chany_bottom_out[11] 0.001751422 //LENGTH 13.290 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_861:X O *L 0 *C 80.695 7.480 +*P chany_bottom_out[11] O *L 0.7423 *C 74.060 1.290 +*N chany_bottom_out[11]:2 *C 74.060 7.435 +*N chany_bottom_out[11]:3 *C 74.105 7.480 +*N chany_bottom_out[11]:4 *C 80.657 7.480 + +*CAP +0 ropt_mt_inst_861:X 1e-06 +1 chany_bottom_out[11] 0.0004070272 +2 chany_bottom_out[11]:2 0.0004070272 +3 chany_bottom_out[11]:3 0.0004681839 +4 chany_bottom_out[11]:4 0.0004681839 + +*RES +0 ropt_mt_inst_861:X chany_bottom_out[11]:4 0.152 +1 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.005850446 +2 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +3 chany_bottom_out[11]:2 chany_bottom_out[11] 0.005486608 + +*END + +*D_NET chany_top_out[8] 0.001248674 //LENGTH 8.625 LUMPCC 0.0001072993 DR + +*CONN +*I ropt_mt_inst_865:X O *L 0 *C 68.080 123.080 +*P chany_top_out[8] O *L 0.7423 *C 68.540 129.270 +*N chany_top_out[8]:2 *C 68.540 127.840 +*N chany_top_out[8]:3 *C 69.000 127.840 +*N chany_top_out[8]:4 *C 69.000 123.125 +*N chany_top_out[8]:5 *C 69.000 123.080 +*N chany_top_out[8]:6 *C 68.118 123.080 + +*CAP +0 ropt_mt_inst_865:X 1e-06 +1 chany_top_out[8] 9.161527e-05 +2 chany_top_out[8]:2 0.0001207164 +3 chany_top_out[8]:3 0.0003859308 +4 chany_top_out[8]:4 0.0003568297 +5 chany_top_out[8]:5 0.0001112526 +6 chany_top_out[8]:6 7.403022e-05 +7 chany_top_out[8]:6 ropt_net_182:5 5.364966e-05 +8 chany_top_out[8]:5 ropt_net_182:4 5.364966e-05 + +*RES +0 ropt_mt_inst_865:X chany_top_out[8]:6 0.152 +1 chany_top_out[8]:6 chany_top_out[8]:5 0.0007879465 +2 chany_top_out[8]:5 chany_top_out[8]:4 0.0045 +3 chany_top_out[8]:4 chany_top_out[8]:3 0.004209821 +4 chany_top_out[8]:2 chany_top_out[8] 0.001276786 +5 chany_top_out[8]:3 chany_top_out[8]:2 0.0004107143 + +*END + +*D_NET chany_top_out[9] 0.00116585 //LENGTH 8.740 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_842:X O *L 0 *C 58.615 121.720 +*P chany_top_out[9] O *L 0.7423 *C 58.420 129.270 +*N chany_top_out[9]:2 *C 58.420 127.840 +*N chany_top_out[9]:3 *C 58.880 127.840 +*N chany_top_out[9]:4 *C 58.880 121.765 +*N chany_top_out[9]:5 *C 58.880 121.720 +*N chany_top_out[9]:6 *C 58.615 121.720 + +*CAP +0 ropt_mt_inst_842:X 1e-06 +1 chany_top_out[9] 8.713702e-05 +2 chany_top_out[9]:2 0.0001133553 +3 chany_top_out[9]:3 0.0004312524 +4 chany_top_out[9]:4 0.0004050341 +5 chany_top_out[9]:5 6.103118e-05 +6 chany_top_out[9]:6 6.703987e-05 + +*RES +0 ropt_mt_inst_842:X chany_top_out[9]:6 0.152 +1 chany_top_out[9]:6 chany_top_out[9]:5 0.0001440218 +2 chany_top_out[9]:5 chany_top_out[9]:4 0.0045 +3 chany_top_out[9]:4 chany_top_out[9]:3 0.005424107 +4 chany_top_out[9]:2 chany_top_out[9] 0.001276786 +5 chany_top_out[9]:3 chany_top_out[9]:2 0.0004107143 + +*END + +*D_NET chany_bottom_out[9] 0.0004830607 //LENGTH 3.665 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_876:X O *L 0 *C 53.555 3.400 +*P chany_bottom_out[9] O *L 0.7423 *C 54.280 1.325 +*N chany_bottom_out[9]:2 *C 54.280 3.355 +*N chany_bottom_out[9]:3 *C 54.235 3.400 +*N chany_bottom_out[9]:4 *C 53.555 3.400 + +*CAP +0 ropt_mt_inst_876:X 1e-06 +1 chany_bottom_out[9] 0.0001316214 +2 chany_bottom_out[9]:2 0.0001316214 +3 chany_bottom_out[9]:3 9.471222e-05 +4 chany_bottom_out[9]:4 0.0001241056 + +*RES +0 ropt_mt_inst_876:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.0006071429 +2 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +3 chany_bottom_out[9]:2 chany_bottom_out[9] 0.0018125 + +*END + +*D_NET chanx_right_out[17] 0.0006499422 //LENGTH 4.830 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_898:X O *L 0 *C 138.655 64.600 +*P chanx_right_out[17] O *L 0.7423 *C 140.450 66.640 +*N chanx_right_out[17]:2 *C 138.468 66.640 +*N chanx_right_out[17]:3 *C 138.460 66.583 +*N chanx_right_out[17]:4 *C 138.460 64.645 +*N chanx_right_out[17]:5 *C 138.460 64.600 +*N chanx_right_out[17]:6 *C 138.655 64.600 + +*CAP +0 ropt_mt_inst_898:X 1e-06 +1 chanx_right_out[17] 0.0001530171 +2 chanx_right_out[17]:2 0.0001530171 +3 chanx_right_out[17]:3 0.00012052 +4 chanx_right_out[17]:4 0.00012052 +5 chanx_right_out[17]:5 4.966257e-05 +6 chanx_right_out[17]:6 5.220544e-05 + +*RES +0 ropt_mt_inst_898:X chanx_right_out[17]:6 0.152 +1 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0001059783 +2 chanx_right_out[17]:5 chanx_right_out[17]:4 0.0045 +3 chanx_right_out[17]:4 chanx_right_out[17]:3 0.001729911 +4 chanx_right_out[17]:3 chanx_right_out[17]:2 0.00341 +5 chanx_right_out[17]:2 chanx_right_out[17] 0.0003105916 + +*END + +*D_NET chany_top_in[4] 0.02696579 //LENGTH 170.900 LUMPCC 0.009213142 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 51.980 129.270 +*I mux_left_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 68.540 99.620 +*I FTB_2__1:A I *L 0.001776 *C 68.540 12.240 +*I mux_bottom_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 70.840 28.900 +*I mux_right_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 88.035 93.500 +*N chany_top_in[4]:5 *C 88.035 93.500 +*N chany_top_in[4]:6 *C 87.860 93.500 +*N chany_top_in[4]:7 *C 87.860 93.545 +*N chany_top_in[4]:8 *C 87.860 101.275 +*N chany_top_in[4]:9 *C 87.815 101.320 +*N chany_top_in[4]:10 *C 67.370 97.240 +*N chany_top_in[4]:11 *C 70.840 28.900 +*N chany_top_in[4]:12 *C 70.840 28.900 +*N chany_top_in[4]:13 *C 69.972 28.900 +*N chany_top_in[4]:14 *C 68.578 12.240 +*N chany_top_in[4]:15 *C 69.875 12.240 +*N chany_top_in[4]:16 *C 69.920 12.285 +*N chany_top_in[4]:17 *C 69.920 28.543 +*N chany_top_in[4]:18 *C 69.913 28.560 +*N chany_top_in[4]:19 *C 68.100 28.560 +*N chany_top_in[4]:20 *C 68.080 28.568 +*N chany_top_in[4]:21 *C 68.080 78.395 +*N chany_top_in[4]:22 *C 68.080 97.233 +*N chany_top_in[4]:23 *C 68.078 97.240 +*N chany_top_in[4]:24 *C 68.080 97.297 +*N chany_top_in[4]:25 *C 68.540 99.620 +*N chany_top_in[4]:26 *C 68.125 99.620 +*N chany_top_in[4]:27 *C 68.080 99.620 +*N chany_top_in[4]:28 *C 68.080 101.275 +*N chany_top_in[4]:29 *C 68.080 101.320 +*N chany_top_in[4]:30 *C 66.745 101.320 +*N chany_top_in[4]:31 *C 66.700 101.365 +*N chany_top_in[4]:32 *C 66.700 118.943 +*N chany_top_in[4]:33 *C 66.693 119.000 +*N chany_top_in[4]:34 *C 51.988 119.000 +*N chany_top_in[4]:35 *C 51.980 119.058 + +*CAP +0 chany_top_in[4] 0.0006134887 +1 mux_left_track_3\/mux_l1_in_0_:A1 1e-06 +2 FTB_2__1:A 1e-06 +3 mux_bottom_track_3\/mux_l1_in_0_:A1 1e-06 +4 mux_right_track_2\/mux_l1_in_0_:A0 1e-06 +5 chany_top_in[4]:5 6.128574e-05 +6 chany_top_in[4]:6 6.176186e-05 +7 chany_top_in[4]:7 0.0005060559 +8 chany_top_in[4]:8 0.0005060559 +9 chany_top_in[4]:9 0.001308572 +10 chany_top_in[4]:10 0.000137138 +11 chany_top_in[4]:11 3.654258e-05 +12 chany_top_in[4]:12 9.610037e-05 +13 chany_top_in[4]:13 8.90536e-05 +14 chany_top_in[4]:14 0.0001089469 +15 chany_top_in[4]:15 0.0001089469 +16 chany_top_in[4]:16 0.0008138043 +17 chany_top_in[4]:17 0.0008413953 +18 chany_top_in[4]:18 0.0002307826 +19 chany_top_in[4]:19 0.0002307826 +20 chany_top_in[4]:20 0.001558244 +21 chany_top_in[4]:21 0.002488161 +22 chany_top_in[4]:22 0.0009299176 +23 chany_top_in[4]:23 0.000137138 +24 chany_top_in[4]:24 0.0001484897 +25 chany_top_in[4]:25 8.254517e-05 +26 chany_top_in[4]:26 4.662792e-05 +27 chany_top_in[4]:27 0.0002935367 +28 chany_top_in[4]:28 0.0001140264 +29 chany_top_in[4]:29 0.001449901 +30 chany_top_in[4]:30 0.0001060529 +31 chany_top_in[4]:31 0.0008644708 +32 chany_top_in[4]:32 0.0008644708 +33 chany_top_in[4]:33 0.00115043 +34 chany_top_in[4]:34 0.00115043 +35 chany_top_in[4]:35 0.0006134887 +36 chany_top_in[4]:20 chany_bottom_in[14]:40 0.0003267948 +37 chany_top_in[4]:20 chany_bottom_in[14]:44 0.001181937 +38 chany_top_in[4]:21 chany_bottom_in[14]:39 0.0003267948 +39 chany_top_in[4]:21 chany_bottom_in[14]:43 0.001181937 +40 chany_top_in[4]:16 chany_bottom_in[17]:38 1.341017e-05 +41 chany_top_in[4]:17 chany_bottom_in[17]:37 1.341017e-05 +42 chany_top_in[4]:20 chany_bottom_in[17]:38 0.001049834 +43 chany_top_in[4]:21 chany_bottom_in[17]:37 0.001049834 +44 chany_top_in[4]:31 chany_top_in[1]:5 0.0003230083 +45 chany_top_in[4]:32 chany_top_in[1]:6 0.0003230083 +46 chany_top_in[4]:33 chany_top_in[1]:11 7.987866e-06 +47 chany_top_in[4]:33 chany_top_in[1]:7 1.802397e-06 +48 chany_top_in[4]:34 chany_top_in[1]:24 7.987866e-06 +49 chany_top_in[4]:34 chany_top_in[1]:8 1.802397e-06 +50 chany_top_in[4]:20 chany_top_in[7]:11 0.0007038747 +51 chany_top_in[4]:22 chany_top_in[7]:12 0.0008165798 +52 chany_top_in[4]:21 chany_top_in[7]:11 0.0008165798 +53 chany_top_in[4]:21 chany_top_in[7]:12 0.0007038747 +54 chany_top_in[4]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000166438 +55 chany_top_in[4]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000166438 +56 chany_top_in[4]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.490394e-05 +57 chany_top_in[4]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.490394e-05 + +*RES +0 chany_top_in[4] chany_top_in[4]:35 0.009118304 +1 chany_top_in[4]:14 FTB_2__1:A 0.152 +2 chany_top_in[4]:15 chany_top_in[4]:14 0.001158482 +3 chany_top_in[4]:16 chany_top_in[4]:15 0.0045 +4 chany_top_in[4]:30 chany_top_in[4]:29 0.001191964 +5 chany_top_in[4]:31 chany_top_in[4]:30 0.0045 +6 chany_top_in[4]:32 chany_top_in[4]:31 0.0156942 +7 chany_top_in[4]:33 chany_top_in[4]:32 0.00341 +8 chany_top_in[4]:35 chany_top_in[4]:34 0.00341 +9 chany_top_in[4]:34 chany_top_in[4]:33 0.002303783 +10 chany_top_in[4]:29 chany_top_in[4]:28 0.0045 +11 chany_top_in[4]:29 chany_top_in[4]:9 0.01762054 +12 chany_top_in[4]:28 chany_top_in[4]:27 0.001477679 +13 chany_top_in[4]:11 mux_bottom_track_3\/mux_l1_in_0_:A1 0.152 +14 chany_top_in[4]:12 chany_top_in[4]:11 0.0045 +15 chany_top_in[4]:17 chany_top_in[4]:16 0.01451563 +16 chany_top_in[4]:17 chany_top_in[4]:13 0.0002127976 +17 chany_top_in[4]:18 chany_top_in[4]:17 0.00341 +18 chany_top_in[4]:19 chany_top_in[4]:18 0.0002839583 +19 chany_top_in[4]:20 chany_top_in[4]:19 0.00341 +20 chany_top_in[4]:23 chany_top_in[4]:22 0.00341 +21 chany_top_in[4]:23 chany_top_in[4]:10 0.0001039141 +22 chany_top_in[4]:22 chany_top_in[4]:21 0.002951208 +23 chany_top_in[4]:24 chany_top_in[4]:23 0.00341 +24 chany_top_in[4]:26 chany_top_in[4]:25 0.0003705357 +25 chany_top_in[4]:27 chany_top_in[4]:26 0.0045 +26 chany_top_in[4]:27 chany_top_in[4]:24 0.002073661 +27 chany_top_in[4]:25 mux_left_track_3\/mux_l1_in_0_:A1 0.152 +28 chany_top_in[4]:9 chany_top_in[4]:8 0.0045 +29 chany_top_in[4]:8 chany_top_in[4]:7 0.006901786 +30 chany_top_in[4]:6 chany_top_in[4]:5 9.51087e-05 +31 chany_top_in[4]:7 chany_top_in[4]:6 0.0045 +32 chany_top_in[4]:5 mux_right_track_2\/mux_l1_in_0_:A0 0.152 +33 chany_top_in[4]:13 chany_top_in[4]:12 0.0007745536 +34 chany_top_in[4]:21 chany_top_in[4]:20 0.007806308 + +*END + +*D_NET chanx_left_in[4] 0.03680293 //LENGTH 236.480 LUMPCC 0.009194628 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 85.680 +*I mux_bottom_track_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 55.425 26.180 +*I mux_right_track_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 111.495 87.720 +*I ropt_mt_inst_796:A I *L 0.001767 *C 130.180 72.080 +*I mux_top_track_2\/mux_l1_in_4_:A0 I *L 0.001631 *C 62.390 86.360 +*N chanx_left_in[4]:5 *C 62.353 86.360 +*N chanx_left_in[4]:6 *C 61.685 86.360 +*N chanx_left_in[4]:7 *C 61.640 86.315 +*N chanx_left_in[4]:8 *C 61.640 85.737 +*N chanx_left_in[4]:9 *C 61.633 85.680 +*N chanx_left_in[4]:10 *C 130.180 72.080 +*N chanx_left_in[4]:11 *C 130.180 72.125 +*N chanx_left_in[4]:12 *C 130.180 73.383 +*N chanx_left_in[4]:13 *C 130.173 73.440 +*N chanx_left_in[4]:14 *C 127.888 73.440 +*N chanx_left_in[4]:15 *C 127.880 73.498 +*N chanx_left_in[4]:16 *C 127.880 80.195 +*N chanx_left_in[4]:17 *C 127.835 80.240 +*N chanx_left_in[4]:18 *C 126.040 80.240 +*N chanx_left_in[4]:19 *C 126.040 80.285 +*N chanx_left_in[4]:20 *C 126.040 87.675 +*N chanx_left_in[4]:21 *C 125.995 87.720 +*N chanx_left_in[4]:22 *C 111.495 87.720 +*N chanx_left_in[4]:23 *C 109.525 87.720 +*N chanx_left_in[4]:24 *C 109.480 87.765 +*N chanx_left_in[4]:25 *C 109.480 93.103 +*N chanx_left_in[4]:26 *C 109.473 93.160 +*N chanx_left_in[4]:27 *C 57.980 93.160 +*N chanx_left_in[4]:28 *C 57.960 93.153 +*N chanx_left_in[4]:29 *C 57.560 27.200 +*N chanx_left_in[4]:30 *C 55.463 26.180 +*N chanx_left_in[4]:31 *C 57.915 26.180 +*N chanx_left_in[4]:32 *C 57.960 26.225 +*N chanx_left_in[4]:33 *C 57.960 27.143 +*N chanx_left_in[4]:34 *C 57.960 27.200 +*N chanx_left_in[4]:35 *C 57.960 27.207 +*N chanx_left_in[4]:36 *C 57.960 77.035 +*N chanx_left_in[4]:37 *C 57.960 85.680 +*N chanx_left_in[4]:38 *C 57.960 85.680 +*N chanx_left_in[4]:39 *C 53.820 85.680 +*N chanx_left_in[4]:40 *C 53.820 86.360 +*N chanx_left_in[4]:41 *C 32.208 86.360 +*N chanx_left_in[4]:42 *C 32.200 86.303 +*N chanx_left_in[4]:43 *C 32.200 84.377 +*N chanx_left_in[4]:44 *C 32.193 84.320 +*N chanx_left_in[4]:45 *C 6.900 84.320 +*N chanx_left_in[4]:46 *C 6.900 85.000 +*N chanx_left_in[4]:47 *C 3.680 85.000 +*N chanx_left_in[4]:48 *C 3.680 85.680 + +*CAP +0 chanx_left_in[4] 0.0001392037 +1 mux_bottom_track_3\/mux_l2_in_2_:A0 1e-06 +2 mux_right_track_2\/mux_l2_in_2_:A0 1e-06 +3 ropt_mt_inst_796:A 1e-06 +4 mux_top_track_2\/mux_l1_in_4_:A0 1e-06 +5 chanx_left_in[4]:5 6.948929e-05 +6 chanx_left_in[4]:6 6.948929e-05 +7 chanx_left_in[4]:7 5.71744e-05 +8 chanx_left_in[4]:8 5.71744e-05 +9 chanx_left_in[4]:9 0.000204374 +10 chanx_left_in[4]:10 3.660701e-05 +11 chanx_left_in[4]:11 0.0001083255 +12 chanx_left_in[4]:12 0.0001083255 +13 chanx_left_in[4]:13 0.000229714 +14 chanx_left_in[4]:14 0.000229714 +15 chanx_left_in[4]:15 0.0003768534 +16 chanx_left_in[4]:16 0.0003768534 +17 chanx_left_in[4]:17 0.0001229336 +18 chanx_left_in[4]:18 0.0001569557 +19 chanx_left_in[4]:19 0.000402452 +20 chanx_left_in[4]:20 0.000402452 +21 chanx_left_in[4]:21 0.001011847 +22 chanx_left_in[4]:22 0.001181287 +23 chanx_left_in[4]:23 0.0001409237 +24 chanx_left_in[4]:24 0.0003047362 +25 chanx_left_in[4]:25 0.0003047362 +26 chanx_left_in[4]:26 0.002693417 +27 chanx_left_in[4]:27 0.002693417 +28 chanx_left_in[4]:28 0.0003777516 +29 chanx_left_in[4]:29 6.915067e-05 +30 chanx_left_in[4]:30 0.000158753 +31 chanx_left_in[4]:31 0.000158753 +32 chanx_left_in[4]:32 8.863129e-05 +33 chanx_left_in[4]:33 8.863129e-05 +34 chanx_left_in[4]:34 6.915067e-05 +35 chanx_left_in[4]:35 0.002857488 +36 chanx_left_in[4]:36 0.003295442 +37 chanx_left_in[4]:37 0.0008157054 +38 chanx_left_in[4]:38 0.0004849665 +39 chanx_left_in[4]:39 0.0003629697 +40 chanx_left_in[4]:40 0.001634234 +41 chanx_left_in[4]:41 0.001551857 +42 chanx_left_in[4]:42 0.0001387994 +43 chanx_left_in[4]:43 0.0001387994 +44 chanx_left_in[4]:44 0.001471397 +45 chanx_left_in[4]:45 0.001533561 +46 chanx_left_in[4]:46 0.0003318171 +47 chanx_left_in[4]:47 0.0003142183 +48 chanx_left_in[4]:48 0.0001837684 +49 chanx_left_in[4]:27 chanx_right_in[14]:25 9.027471e-05 +50 chanx_left_in[4]:27 chanx_right_in[14]:37 2.618085e-06 +51 chanx_left_in[4]:27 chanx_right_in[14]:39 0.0002592398 +52 chanx_left_in[4]:26 chanx_right_in[14]:26 9.027471e-05 +53 chanx_left_in[4]:26 chanx_right_in[14]:38 2.618085e-06 +54 chanx_left_in[4]:26 chanx_right_in[14]:40 0.0002592398 +55 chanx_left_in[4]:35 chany_bottom_in[8]:19 0.000642902 +56 chanx_left_in[4]:37 chany_bottom_in[8]:18 0.000358511 +57 chanx_left_in[4]:37 chany_bottom_in[8]:19 0.000319249 +58 chanx_left_in[4]:28 chany_bottom_in[8]:18 0.000319249 +59 chanx_left_in[4]:36 chany_bottom_in[8]:18 0.000642902 +60 chanx_left_in[4]:36 chany_bottom_in[8]:19 0.000358511 +61 chanx_left_in[4]:34 prog_clk[0]:323 8.20978e-06 +62 chanx_left_in[4]:20 prog_clk[0]:152 8.495151e-07 +63 chanx_left_in[4]:19 prog_clk[0]:153 8.495151e-07 +64 chanx_left_in[4]:27 prog_clk[0]:253 0.0001575628 +65 chanx_left_in[4]:27 prog_clk[0]:252 0.0001292144 +66 chanx_left_in[4]:26 prog_clk[0]:252 0.0001575628 +67 chanx_left_in[4]:26 prog_clk[0]:233 0.0001292144 +68 chanx_left_in[4]:44 prog_clk[0]:617 0.0001899644 +69 chanx_left_in[4]:44 prog_clk[0]:492 3.289961e-05 +70 chanx_left_in[4]:48 prog_clk[0]:653 5.537891e-06 +71 chanx_left_in[4]:47 prog_clk[0]:657 5.537891e-06 +72 chanx_left_in[4]:45 prog_clk[0]:618 0.0001899644 +73 chanx_left_in[4]:45 prog_clk[0]:493 3.289961e-05 +74 chanx_left_in[4]:29 prog_clk[0]:303 8.20978e-06 +75 chanx_left_in[4]:27 chanx_right_in[3]:7 0.0003104311 +76 chanx_left_in[4]:26 chanx_right_in[3]:8 0.0003104311 +77 chanx_left_in[4]:35 chanx_right_in[19]:17 7.174649e-05 +78 chanx_left_in[4]:35 chanx_right_in[19]:16 0.000196036 +79 chanx_left_in[4]:36 chanx_right_in[19]:9 0.000196036 +80 chanx_left_in[4]:36 chanx_right_in[19]:16 7.174649e-05 +81 chanx_left_in[4]:27 chanx_left_in[0]:8 0.000597338 +82 chanx_left_in[4]:26 chanx_left_in[0]:7 0.000597338 +83 chanx_left_in[4]:38 mux_tree_tapbuf_size12_6_sram[1]:27 0.0002060084 +84 chanx_left_in[4]:38 mux_tree_tapbuf_size12_6_sram[1]:26 0.0001680097 +85 chanx_left_in[4]:9 mux_tree_tapbuf_size12_6_sram[1]:26 0.0002060084 +86 chanx_left_in[4]:41 mux_tree_tapbuf_size12_6_sram[1]:33 3.192787e-06 +87 chanx_left_in[4]:44 mux_tree_tapbuf_size12_6_sram[1]:32 5.381788e-07 +88 chanx_left_in[4]:45 mux_tree_tapbuf_size12_6_sram[1]:33 5.381788e-07 +89 chanx_left_in[4]:40 mux_tree_tapbuf_size12_6_sram[1]:32 3.192787e-06 +90 chanx_left_in[4]:39 mux_tree_tapbuf_size12_6_sram[1]:27 0.0001680097 +91 chanx_left_in[4]:41 mux_tree_tapbuf_size12_6_sram[2]:12 6.166386e-06 +92 chanx_left_in[4]:44 mux_tree_tapbuf_size12_6_sram[2]:8 0.0002849341 +93 chanx_left_in[4]:45 mux_tree_tapbuf_size12_6_sram[2]:7 0.0002849341 +94 chanx_left_in[4]:40 mux_tree_tapbuf_size12_6_sram[2]:13 6.166386e-06 +95 chanx_left_in[4]:21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.178877e-05 +96 chanx_left_in[4]:22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 5.178877e-05 +97 chanx_left_in[4]:27 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003028212 +98 chanx_left_in[4]:25 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.99712e-05 +99 chanx_left_in[4]:26 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003028212 +100 chanx_left_in[4]:24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.99712e-05 +101 chanx_left_in[4]:31 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001045338 +102 chanx_left_in[4]:30 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001045338 +103 chanx_left_in[4] ropt_net_232:6 7.624023e-05 +104 chanx_left_in[4]:48 ropt_net_232:7 7.624023e-05 +105 chanx_left_in[4]:47 ropt_net_232:6 5.255086e-07 +106 chanx_left_in[4]:46 ropt_net_232:7 5.255086e-07 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:48 0.0003838333 +1 chanx_left_in[4]:34 chanx_left_in[4]:33 0.00341 +2 chanx_left_in[4]:34 chanx_left_in[4]:29 5.69697e-05 +3 chanx_left_in[4]:35 chanx_left_in[4]:34 0.00341 +4 chanx_left_in[4]:33 chanx_left_in[4]:32 0.0008191965 +5 chanx_left_in[4]:31 chanx_left_in[4]:30 0.002189732 +6 chanx_left_in[4]:32 chanx_left_in[4]:31 0.0045 +7 chanx_left_in[4]:30 mux_bottom_track_3\/mux_l2_in_2_:A0 0.152 +8 chanx_left_in[4]:21 chanx_left_in[4]:20 0.0045 +9 chanx_left_in[4]:20 chanx_left_in[4]:19 0.006598215 +10 chanx_left_in[4]:18 chanx_left_in[4]:17 0.001602679 +11 chanx_left_in[4]:19 chanx_left_in[4]:18 0.0045 +12 chanx_left_in[4]:17 chanx_left_in[4]:16 0.0045 +13 chanx_left_in[4]:16 chanx_left_in[4]:15 0.005979911 +14 chanx_left_in[4]:15 chanx_left_in[4]:14 0.00341 +15 chanx_left_in[4]:14 chanx_left_in[4]:13 0.0003579833 +16 chanx_left_in[4]:12 chanx_left_in[4]:11 0.001122768 +17 chanx_left_in[4]:13 chanx_left_in[4]:12 0.00341 +18 chanx_left_in[4]:10 ropt_mt_inst_796:A 0.152 +19 chanx_left_in[4]:11 chanx_left_in[4]:10 0.0045 +20 chanx_left_in[4]:38 chanx_left_in[4]:37 0.00341 +21 chanx_left_in[4]:38 chanx_left_in[4]:9 0.0005753583 +22 chanx_left_in[4]:37 chanx_left_in[4]:36 0.001354383 +23 chanx_left_in[4]:37 chanx_left_in[4]:28 0.001170692 +24 chanx_left_in[4]:27 chanx_left_in[4]:26 0.008067158 +25 chanx_left_in[4]:28 chanx_left_in[4]:27 0.00341 +26 chanx_left_in[4]:25 chanx_left_in[4]:24 0.004765625 +27 chanx_left_in[4]:26 chanx_left_in[4]:25 0.00341 +28 chanx_left_in[4]:23 chanx_left_in[4]:22 0.001758929 +29 chanx_left_in[4]:24 chanx_left_in[4]:23 0.0045 +30 chanx_left_in[4]:22 mux_right_track_2\/mux_l2_in_2_:A0 0.152 +31 chanx_left_in[4]:22 chanx_left_in[4]:21 0.01294643 +32 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0005156249 +33 chanx_left_in[4]:9 chanx_left_in[4]:8 0.00341 +34 chanx_left_in[4]:6 chanx_left_in[4]:5 0.0005959822 +35 chanx_left_in[4]:7 chanx_left_in[4]:6 0.0045 +36 chanx_left_in[4]:5 mux_top_track_2\/mux_l1_in_4_:A0 0.152 +37 chanx_left_in[4]:42 chanx_left_in[4]:41 0.00341 +38 chanx_left_in[4]:41 chanx_left_in[4]:40 0.003385958 +39 chanx_left_in[4]:43 chanx_left_in[4]:42 0.00171875 +40 chanx_left_in[4]:44 chanx_left_in[4]:43 0.00341 +41 chanx_left_in[4]:48 chanx_left_in[4]:47 0.0001065333 +42 chanx_left_in[4]:47 chanx_left_in[4]:46 0.0005044666 +43 chanx_left_in[4]:46 chanx_left_in[4]:45 0.0001065333 +44 chanx_left_in[4]:45 chanx_left_in[4]:44 0.003962492 +45 chanx_left_in[4]:40 chanx_left_in[4]:39 0.0001065333 +46 chanx_left_in[4]:39 chanx_left_in[4]:38 0.0006485999 +47 chanx_left_in[4]:36 chanx_left_in[4]:35 0.007806308 + +*END + +*D_NET chany_top_in[0] 0.006730644 //LENGTH 50.915 LUMPCC 0.001296879 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 80.500 129.270 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 80.500 90.780 +*I mux_right_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 88.420 94.180 +*N chany_top_in[0]:3 *C 88.383 94.180 +*N chany_top_in[0]:4 *C 86.065 94.180 +*N chany_top_in[0]:5 *C 86.020 94.135 +*N chany_top_in[0]:6 *C 86.020 90.825 +*N chany_top_in[0]:7 *C 85.975 90.780 +*N chany_top_in[0]:8 *C 80.538 90.780 +*N chany_top_in[0]:9 *C 80.500 90.825 + +*CAP +0 chany_top_in[0] 0.001916029 +1 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[0]:3 0.0002398756 +4 chany_top_in[0]:4 0.0002398756 +5 chany_top_in[0]:5 0.0002123856 +6 chany_top_in[0]:6 0.0002123856 +7 chany_top_in[0]:7 0.0003475927 +8 chany_top_in[0]:8 0.0003475927 +9 chany_top_in[0]:9 0.001916029 +10 chany_top_in[0] chany_top_in[2] 1.23305e-05 +11 chany_top_in[0] chany_top_in[2]:5 7.520107e-06 +12 chany_top_in[0] chany_top_in[2]:27 8.885298e-05 +13 chany_top_in[0] chany_top_in[2]:30 0.0001284423 +14 chany_top_in[0] chany_top_in[2]:31 8.439695e-05 +15 chany_top_in[0]:8 chany_top_in[2]:7 1.939454e-05 +16 chany_top_in[0]:7 chany_top_in[2]:6 1.939454e-05 +17 chany_top_in[0]:9 chany_top_in[2]:6 7.520107e-06 +18 chany_top_in[0]:9 chany_top_in[2]:8 8.885298e-05 +19 chany_top_in[0]:9 chany_top_in[2]:27 0.0001284423 +20 chany_top_in[0]:9 chany_top_in[2]:30 8.439695e-05 +21 chany_top_in[0]:9 chany_top_in[2]:34 1.23305e-05 +22 chany_top_in[0] mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001000239 +23 chany_top_in[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001000239 +24 chany_top_in[0] mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002074782 +25 chany_top_in[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0002074782 + +*RES +0 chany_top_in[0] chany_top_in[0]:9 0.0343259 +1 chany_top_in[0]:8 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[0]:8 chany_top_in[0]:7 0.004854911 +3 chany_top_in[0]:7 chany_top_in[0]:6 0.0045 +4 chany_top_in[0]:6 chany_top_in[0]:5 0.002955357 +5 chany_top_in[0]:4 chany_top_in[0]:3 0.002069197 +6 chany_top_in[0]:5 chany_top_in[0]:4 0.0045 +7 chany_top_in[0]:3 mux_right_track_2\/mux_l1_in_0_:A1 0.152 +8 chany_top_in[0]:9 chany_top_in[0]:8 0.0045 + +*END + +*D_NET chany_top_in[7] 0.0146889 //LENGTH 83.880 LUMPCC 0.008201636 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 66.700 129.270 +*I mux_right_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.700 58.140 +*I mux_left_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 71.665 56.100 +*N chany_top_in[7]:3 *C 71.703 56.100 +*N chany_top_in[7]:4 *C 73.555 56.100 +*N chany_top_in[7]:5 *C 73.600 56.145 +*N chany_top_in[7]:6 *C 73.600 58.140 +*N chany_top_in[7]:7 *C 73.600 58.140 +*N chany_top_in[7]:8 *C 73.600 61.823 +*N chany_top_in[7]:9 *C 73.593 61.880 +*N chany_top_in[7]:10 *C 67.180 61.880 +*N chany_top_in[7]:11 *C 67.160 61.888 +*N chany_top_in[7]:12 *C 67.160 111.715 +*N chany_top_in[7]:13 *C 67.160 126.473 +*N chany_top_in[7]:14 *C 67.145 126.480 +*N chany_top_in[7]:15 *C 66.703 126.480 +*N chany_top_in[7]:16 *C 66.700 126.538 + +*CAP +0 chany_top_in[7] 0.0001199925 +1 mux_right_track_16\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_17\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[7]:3 0.000168498 +4 chany_top_in[7]:4 0.000168498 +5 chany_top_in[7]:5 0.000140149 +6 chany_top_in[7]:6 3.828361e-05 +7 chany_top_in[7]:7 0.0004447048 +8 chany_top_in[7]:8 0.0002719135 +9 chany_top_in[7]:9 0.0005919863 +10 chany_top_in[7]:10 0.0005919863 +11 chany_top_in[7]:11 0.001245064 +12 chany_top_in[7]:12 0.001860253 +13 chany_top_in[7]:13 0.0006151896 +14 chany_top_in[7]:14 5.437804e-05 +15 chany_top_in[7]:15 5.437804e-05 +16 chany_top_in[7]:16 0.0001199925 +17 chany_top_in[7]:11 chany_top_in[4]:20 0.0007038747 +18 chany_top_in[7]:11 chany_top_in[4]:21 0.0008165798 +19 chany_top_in[7]:12 chany_top_in[4]:21 0.0007038747 +20 chany_top_in[7]:12 chany_top_in[4]:22 0.0008165798 +21 chany_top_in[7] chany_top_in[9] 3.880563e-05 +22 chany_top_in[7]:11 chany_top_in[9]:36 0.0002879494 +23 chany_top_in[7]:13 chany_top_in[9]:37 0.0001994244 +24 chany_top_in[7]:16 chany_top_in[9]:40 3.880563e-05 +25 chany_top_in[7]:12 chany_top_in[9]:36 0.0001994244 +26 chany_top_in[7]:12 chany_top_in[9]:37 0.0002879494 +27 chany_top_in[7]:11 chany_bottom_in[18]:16 0.001815727 +28 chany_top_in[7]:13 chany_bottom_in[18]:15 0.0002384571 +29 chany_top_in[7]:12 chany_bottom_in[18]:15 0.001815727 +30 chany_top_in[7]:12 chany_bottom_in[18]:16 0.0002384571 + +*RES +0 chany_top_in[7] chany_top_in[7]:16 0.002439732 +1 chany_top_in[7]:4 chany_top_in[7]:3 0.001654018 +2 chany_top_in[7]:5 chany_top_in[7]:4 0.0045 +3 chany_top_in[7]:3 mux_left_track_17\/mux_l1_in_0_:A1 0.152 +4 chany_top_in[7]:6 mux_right_track_16\/mux_l1_in_0_:A1 0.152 +5 chany_top_in[7]:7 chany_top_in[7]:6 0.0045 +6 chany_top_in[7]:7 chany_top_in[7]:5 0.00178125 +7 chany_top_in[7]:8 chany_top_in[7]:7 0.003287946 +8 chany_top_in[7]:9 chany_top_in[7]:8 0.00341 +9 chany_top_in[7]:10 chany_top_in[7]:9 0.001004625 +10 chany_top_in[7]:11 chany_top_in[7]:10 0.00341 +11 chany_top_in[7]:14 chany_top_in[7]:13 0.00341 +12 chany_top_in[7]:13 chany_top_in[7]:12 0.002312009 +13 chany_top_in[7]:16 chany_top_in[7]:15 0.00341 +14 chany_top_in[7]:15 chany_top_in[7]:14 6.499219e-05 +15 chany_top_in[7]:12 chany_top_in[7]:11 0.007806308 + +*END + +*D_NET top_left_grid_pin_37_[0] 0.007267028 //LENGTH 57.215 LUMPCC 0.0003300548 DR + +*CONN +*P top_left_grid_pin_37_[0] I *L 0.29796 *C 30.820 129.235 +*I mux_top_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 33.580 123.420 +*I mux_top_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 60.820 107.100 +*I mux_top_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 54.915 107.780 +*N top_left_grid_pin_37_[0]:4 *C 54.953 107.780 +*N top_left_grid_pin_37_[0]:5 *C 56.580 107.780 +*N top_left_grid_pin_37_[0]:6 *C 60.858 107.100 +*N top_left_grid_pin_37_[0]:7 *C 61.180 107.100 +*N top_left_grid_pin_37_[0]:8 *C 61.180 107.440 +*N top_left_grid_pin_37_[0]:9 *C 56.580 107.440 +*N top_left_grid_pin_37_[0]:10 *C 49.725 107.440 +*N top_left_grid_pin_37_[0]:11 *C 49.680 107.485 +*N top_left_grid_pin_37_[0]:12 *C 49.680 123.023 +*N top_left_grid_pin_37_[0]:13 *C 49.672 123.080 +*N top_left_grid_pin_37_[0]:14 *C 34.047 123.080 +*N top_left_grid_pin_37_[0]:15 *C 34.040 123.080 +*N top_left_grid_pin_37_[0]:16 *C 34.040 123.420 +*N top_left_grid_pin_37_[0]:17 *C 33.995 123.420 +*N top_left_grid_pin_37_[0]:18 *C 33.580 123.420 +*N top_left_grid_pin_37_[0]:19 *C 31.325 123.420 +*N top_left_grid_pin_37_[0]:20 *C 31.280 123.465 +*N top_left_grid_pin_37_[0]:21 *C 31.280 126.820 +*N top_left_grid_pin_37_[0]:22 *C 30.820 126.820 + +*CAP +0 top_left_grid_pin_37_[0] 0.0001181322 +1 mux_top_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_2\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_37_[0]:4 0.0001426185 +5 top_left_grid_pin_37_[0]:5 0.000170829 +6 top_left_grid_pin_37_[0]:6 1.968123e-05 +7 top_left_grid_pin_37_[0]:7 4.507362e-05 +8 top_left_grid_pin_37_[0]:8 0.0003350917 +9 top_left_grid_pin_37_[0]:9 0.0007973756 +10 top_left_grid_pin_37_[0]:10 0.0004594658 +11 top_left_grid_pin_37_[0]:11 0.0008249787 +12 top_left_grid_pin_37_[0]:12 0.0008249787 +13 top_left_grid_pin_37_[0]:13 0.0009929547 +14 top_left_grid_pin_37_[0]:14 0.0009929547 +15 top_left_grid_pin_37_[0]:15 6.541752e-05 +16 top_left_grid_pin_37_[0]:16 6.113864e-05 +17 top_left_grid_pin_37_[0]:17 5.082057e-05 +18 top_left_grid_pin_37_[0]:18 0.0002756249 +19 top_left_grid_pin_37_[0]:19 0.0001948298 +20 top_left_grid_pin_37_[0]:20 0.0001987733 +21 top_left_grid_pin_37_[0]:21 0.0002219375 +22 top_left_grid_pin_37_[0]:22 0.0001412964 +23 top_left_grid_pin_37_[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 0.0001479363 +24 top_left_grid_pin_37_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 1.709116e-05 +25 top_left_grid_pin_37_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 0.0001479363 +26 top_left_grid_pin_37_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 1.709116e-05 + +*RES +0 top_left_grid_pin_37_[0] top_left_grid_pin_37_[0]:22 0.00215625 +1 top_left_grid_pin_37_[0]:19 top_left_grid_pin_37_[0]:18 0.002013393 +2 top_left_grid_pin_37_[0]:20 top_left_grid_pin_37_[0]:19 0.0045 +3 top_left_grid_pin_37_[0]:18 mux_top_track_4\/mux_l2_in_1_:A1 0.152 +4 top_left_grid_pin_37_[0]:18 top_left_grid_pin_37_[0]:17 0.0003705357 +5 top_left_grid_pin_37_[0]:6 mux_top_track_32\/mux_l1_in_0_:A1 0.152 +6 top_left_grid_pin_37_[0]:4 mux_top_track_2\/mux_l1_in_0_:A0 0.152 +7 top_left_grid_pin_37_[0]:17 top_left_grid_pin_37_[0]:16 0.0045 +8 top_left_grid_pin_37_[0]:16 top_left_grid_pin_37_[0]:15 0.0001634615 +9 top_left_grid_pin_37_[0]:15 top_left_grid_pin_37_[0]:14 0.00341 +10 top_left_grid_pin_37_[0]:14 top_left_grid_pin_37_[0]:13 0.002447917 +11 top_left_grid_pin_37_[0]:12 top_left_grid_pin_37_[0]:11 0.01387277 +12 top_left_grid_pin_37_[0]:13 top_left_grid_pin_37_[0]:12 0.00341 +13 top_left_grid_pin_37_[0]:10 top_left_grid_pin_37_[0]:9 0.006120536 +14 top_left_grid_pin_37_[0]:11 top_left_grid_pin_37_[0]:10 0.0045 +15 top_left_grid_pin_37_[0]:9 top_left_grid_pin_37_[0]:8 0.004107144 +16 top_left_grid_pin_37_[0]:9 top_left_grid_pin_37_[0]:5 0.0003035714 +17 top_left_grid_pin_37_[0]:8 top_left_grid_pin_37_[0]:7 0.0003035715 +18 top_left_grid_pin_37_[0]:5 top_left_grid_pin_37_[0]:4 0.001453125 +19 top_left_grid_pin_37_[0]:7 top_left_grid_pin_37_[0]:6 0.0002879465 +20 top_left_grid_pin_37_[0]:22 top_left_grid_pin_37_[0]:21 0.0004107143 +21 top_left_grid_pin_37_[0]:21 top_left_grid_pin_37_[0]:20 0.002995536 + +*END + +*D_NET right_top_grid_pin_42_[0] 0.01367323 //LENGTH 103.890 LUMPCC 0.003180888 DR + +*CONN +*P right_top_grid_pin_42_[0] I *L 0.29796 *C 138.460 102.035 +*I mux_right_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 104.595 69.700 +*I mux_right_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 113.160 83.300 +*I mux_right_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 89.875 104.040 +*N right_top_grid_pin_42_[0]:4 *C 89.913 104.040 +*N right_top_grid_pin_42_[0]:5 *C 91.955 104.040 +*N right_top_grid_pin_42_[0]:6 *C 92.000 103.995 +*N right_top_grid_pin_42_[0]:7 *C 92.000 102.738 +*N right_top_grid_pin_42_[0]:8 *C 92.008 102.680 +*N right_top_grid_pin_42_[0]:9 *C 113.198 83.300 +*N right_top_grid_pin_42_[0]:10 *C 113.575 83.300 +*N right_top_grid_pin_42_[0]:11 *C 113.620 83.255 +*N right_top_grid_pin_42_[0]:12 *C 104.633 69.700 +*N right_top_grid_pin_42_[0]:13 *C 113.575 69.700 +*N right_top_grid_pin_42_[0]:14 *C 113.620 69.745 +*N right_top_grid_pin_42_[0]:15 *C 113.620 82.280 +*N right_top_grid_pin_42_[0]:16 *C 113.628 82.280 +*N right_top_grid_pin_42_[0]:17 *C 114.980 82.280 +*N right_top_grid_pin_42_[0]:18 *C 115.000 82.288 +*N right_top_grid_pin_42_[0]:19 *C 115.000 95.193 +*N right_top_grid_pin_42_[0]:20 *C 114.980 95.200 +*N right_top_grid_pin_42_[0]:21 *C 112.708 95.200 +*N right_top_grid_pin_42_[0]:22 *C 112.700 95.258 +*N right_top_grid_pin_42_[0]:23 *C 112.700 102.623 +*N right_top_grid_pin_42_[0]:24 *C 112.700 102.680 +*N right_top_grid_pin_42_[0]:25 *C 115.000 102.680 +*N right_top_grid_pin_42_[0]:26 *C 115.000 102.000 +*N right_top_grid_pin_42_[0]:27 *C 131.100 102.000 +*N right_top_grid_pin_42_[0]:28 *C 131.100 101.320 +*N right_top_grid_pin_42_[0]:29 *C 138.453 101.320 +*N right_top_grid_pin_42_[0]:30 *C 138.460 101.378 + +*CAP +0 right_top_grid_pin_42_[0] 5.14183e-05 +1 mux_right_track_8\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_4\/mux_l2_in_1_:A1 1e-06 +3 mux_right_track_0\/mux_l1_in_1_:A0 1e-06 +4 right_top_grid_pin_42_[0]:4 0.0001786366 +5 right_top_grid_pin_42_[0]:5 0.0001786366 +6 right_top_grid_pin_42_[0]:6 9.282408e-05 +7 right_top_grid_pin_42_[0]:7 9.282408e-05 +8 right_top_grid_pin_42_[0]:8 0.0007018 +9 right_top_grid_pin_42_[0]:9 6.033883e-05 +10 right_top_grid_pin_42_[0]:10 6.033883e-05 +11 right_top_grid_pin_42_[0]:11 7.146146e-05 +12 right_top_grid_pin_42_[0]:12 0.0003262194 +13 right_top_grid_pin_42_[0]:13 0.0003262194 +14 right_top_grid_pin_42_[0]:14 0.0007421222 +15 right_top_grid_pin_42_[0]:15 0.0008504854 +16 right_top_grid_pin_42_[0]:16 0.0001744605 +17 right_top_grid_pin_42_[0]:17 0.0001744605 +18 right_top_grid_pin_42_[0]:18 0.0008171307 +19 right_top_grid_pin_42_[0]:19 0.0008171307 +20 right_top_grid_pin_42_[0]:20 0.0001812855 +21 right_top_grid_pin_42_[0]:21 0.0001812855 +22 right_top_grid_pin_42_[0]:22 0.0004310065 +23 right_top_grid_pin_42_[0]:23 0.0004310065 +24 right_top_grid_pin_42_[0]:24 0.0008211462 +25 right_top_grid_pin_42_[0]:25 0.0001628196 +26 right_top_grid_pin_42_[0]:26 0.0007564566 +27 right_top_grid_pin_42_[0]:27 0.0007522992 +28 right_top_grid_pin_42_[0]:28 0.0005217125 +29 right_top_grid_pin_42_[0]:29 0.0004823966 +30 right_top_grid_pin_42_[0]:30 5.14183e-05 +31 right_top_grid_pin_42_[0]:24 chanx_right_in[4]:26 0.0003315769 +32 right_top_grid_pin_42_[0]:8 chanx_right_in[4]:25 0.0003315769 +33 right_top_grid_pin_42_[0]:24 chanx_right_in[5]:29 4.19486e-05 +34 right_top_grid_pin_42_[0]:24 chanx_right_in[5]:30 0.0004533113 +35 right_top_grid_pin_42_[0]:8 chanx_right_in[5]:29 0.0004533113 +36 right_top_grid_pin_42_[0]:25 chanx_right_in[5]:30 4.19486e-05 +37 right_top_grid_pin_42_[0]:26 chanx_right_in[5]:29 0.0004157338 +38 right_top_grid_pin_42_[0]:27 chanx_right_in[5]:30 0.0004157338 +39 right_top_grid_pin_42_[0]:13 chanx_left_in[9]:16 0.0003478731 +40 right_top_grid_pin_42_[0]:12 chanx_left_in[9]:21 0.0003478731 + +*RES +0 right_top_grid_pin_42_[0] right_top_grid_pin_42_[0]:30 0.0005870535 +1 right_top_grid_pin_42_[0]:9 mux_right_track_4\/mux_l2_in_1_:A1 0.152 +2 right_top_grid_pin_42_[0]:10 right_top_grid_pin_42_[0]:9 0.0003370536 +3 right_top_grid_pin_42_[0]:11 right_top_grid_pin_42_[0]:10 0.0045 +4 right_top_grid_pin_42_[0]:30 right_top_grid_pin_42_[0]:29 0.00341 +5 right_top_grid_pin_42_[0]:29 right_top_grid_pin_42_[0]:28 0.001151892 +6 right_top_grid_pin_42_[0]:13 right_top_grid_pin_42_[0]:12 0.007984376 +7 right_top_grid_pin_42_[0]:14 right_top_grid_pin_42_[0]:13 0.0045 +8 right_top_grid_pin_42_[0]:12 mux_right_track_8\/mux_l1_in_1_:A0 0.152 +9 right_top_grid_pin_42_[0]:23 right_top_grid_pin_42_[0]:22 0.006575893 +10 right_top_grid_pin_42_[0]:24 right_top_grid_pin_42_[0]:23 0.00341 +11 right_top_grid_pin_42_[0]:24 right_top_grid_pin_42_[0]:8 0.003241825 +12 right_top_grid_pin_42_[0]:22 right_top_grid_pin_42_[0]:21 0.00341 +13 right_top_grid_pin_42_[0]:21 right_top_grid_pin_42_[0]:20 0.000356025 +14 right_top_grid_pin_42_[0]:20 right_top_grid_pin_42_[0]:19 0.00341 +15 right_top_grid_pin_42_[0]:19 right_top_grid_pin_42_[0]:18 0.002021783 +16 right_top_grid_pin_42_[0]:17 right_top_grid_pin_42_[0]:16 0.0002118917 +17 right_top_grid_pin_42_[0]:18 right_top_grid_pin_42_[0]:17 0.00341 +18 right_top_grid_pin_42_[0]:15 right_top_grid_pin_42_[0]:14 0.01119197 +19 right_top_grid_pin_42_[0]:15 right_top_grid_pin_42_[0]:11 0.0008705358 +20 right_top_grid_pin_42_[0]:16 right_top_grid_pin_42_[0]:15 0.00341 +21 right_top_grid_pin_42_[0]:7 right_top_grid_pin_42_[0]:6 0.001122768 +22 right_top_grid_pin_42_[0]:8 right_top_grid_pin_42_[0]:7 0.00341 +23 right_top_grid_pin_42_[0]:5 right_top_grid_pin_42_[0]:4 0.001823661 +24 right_top_grid_pin_42_[0]:6 right_top_grid_pin_42_[0]:5 0.0045 +25 right_top_grid_pin_42_[0]:4 mux_right_track_0\/mux_l1_in_1_:A0 0.152 +26 right_top_grid_pin_42_[0]:25 right_top_grid_pin_42_[0]:24 0.0003603333 +27 right_top_grid_pin_42_[0]:26 right_top_grid_pin_42_[0]:25 0.0001065333 +28 right_top_grid_pin_42_[0]:27 right_top_grid_pin_42_[0]:26 0.002522333 +29 right_top_grid_pin_42_[0]:28 right_top_grid_pin_42_[0]:27 0.0001065333 + +*END + +*D_NET bottom_left_grid_pin_35_[0] 0.008295033 //LENGTH 65.315 LUMPCC 0.001325275 DR + +*CONN +*P bottom_left_grid_pin_35_[0] I *L 0.29796 *C 29.750 8.160 +*I mux_bottom_track_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 34.330 20.740 +*I mux_bottom_track_3\/mux_l1_in_2_:A0 I *L 0.001631 *C 62.850 26.180 +*I mux_bottom_track_17\/mux_l1_in_2_:A0 I *L 0.001631 *C 61.470 33.660 +*N bottom_left_grid_pin_35_[0]:4 *C 61.508 33.660 +*N bottom_left_grid_pin_35_[0]:5 *C 63.435 33.660 +*N bottom_left_grid_pin_35_[0]:6 *C 63.480 33.615 +*N bottom_left_grid_pin_35_[0]:7 *C 62.888 26.180 +*N bottom_left_grid_pin_35_[0]:8 *C 63.435 26.180 +*N bottom_left_grid_pin_35_[0]:9 *C 63.480 26.180 +*N bottom_left_grid_pin_35_[0]:10 *C 63.480 23.858 +*N bottom_left_grid_pin_35_[0]:11 *C 63.473 23.800 +*N bottom_left_grid_pin_35_[0]:12 *C 44.628 23.800 +*N bottom_left_grid_pin_35_[0]:13 *C 44.620 23.742 +*N bottom_left_grid_pin_35_[0]:14 *C 44.620 20.785 +*N bottom_left_grid_pin_35_[0]:15 *C 44.575 20.740 +*N bottom_left_grid_pin_35_[0]:16 *C 34.367 20.740 +*N bottom_left_grid_pin_35_[0]:17 *C 34.960 20.740 +*N bottom_left_grid_pin_35_[0]:18 *C 34.960 20.400 +*N bottom_left_grid_pin_35_[0]:19 *C 30.865 20.400 +*N bottom_left_grid_pin_35_[0]:20 *C 30.820 20.355 +*N bottom_left_grid_pin_35_[0]:21 *C 30.820 8.218 +*N bottom_left_grid_pin_35_[0]:22 *C 30.812 8.160 + +*CAP +0 bottom_left_grid_pin_35_[0] 4.907528e-05 +1 mux_bottom_track_5\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_2_:A0 1e-06 +3 mux_bottom_track_17\/mux_l1_in_2_:A0 1e-06 +4 bottom_left_grid_pin_35_[0]:4 0.0001477718 +5 bottom_left_grid_pin_35_[0]:5 0.0001477718 +6 bottom_left_grid_pin_35_[0]:6 0.0004910402 +7 bottom_left_grid_pin_35_[0]:7 5.319291e-05 +8 bottom_left_grid_pin_35_[0]:8 5.319291e-05 +9 bottom_left_grid_pin_35_[0]:9 0.0006549774 +10 bottom_left_grid_pin_35_[0]:10 0.0001353819 +11 bottom_left_grid_pin_35_[0]:11 0.0009782428 +12 bottom_left_grid_pin_35_[0]:12 0.0009782428 +13 bottom_left_grid_pin_35_[0]:13 0.0001820401 +14 bottom_left_grid_pin_35_[0]:14 0.0001820401 +15 bottom_left_grid_pin_35_[0]:15 0.0005719522 +16 bottom_left_grid_pin_35_[0]:16 6.160461e-05 +17 bottom_left_grid_pin_35_[0]:17 0.0006578648 +18 bottom_left_grid_pin_35_[0]:18 0.000289206 +19 bottom_left_grid_pin_35_[0]:19 0.0002648979 +20 bottom_left_grid_pin_35_[0]:20 0.0005095939 +21 bottom_left_grid_pin_35_[0]:21 0.0005095939 +22 bottom_left_grid_pin_35_[0]:22 4.907528e-05 +23 bottom_left_grid_pin_35_[0]:11 chanx_left_in[13]:27 0.0003185006 +24 bottom_left_grid_pin_35_[0]:12 chanx_left_in[13]:28 0.0003185006 +25 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_36_[0] 3.617592e-05 +26 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_36_[0]:11 0.0001913836 +27 bottom_left_grid_pin_35_[0]:12 bottom_left_grid_pin_36_[0]:12 0.0001913836 +28 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_36_[0]:24 0.0001165773 +29 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_36_[0]:25 0.0001165773 +30 bottom_left_grid_pin_35_[0]:22 bottom_left_grid_pin_36_[0]:26 3.617592e-05 + +*RES +0 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_35_[0]:22 0.0001664583 +1 bottom_left_grid_pin_35_[0]:5 bottom_left_grid_pin_35_[0]:4 0.001720982 +2 bottom_left_grid_pin_35_[0]:6 bottom_left_grid_pin_35_[0]:5 0.0045 +3 bottom_left_grid_pin_35_[0]:4 mux_bottom_track_17\/mux_l1_in_2_:A0 0.152 +4 bottom_left_grid_pin_35_[0]:10 bottom_left_grid_pin_35_[0]:9 0.002073661 +5 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_35_[0]:10 0.00341 +6 bottom_left_grid_pin_35_[0]:13 bottom_left_grid_pin_35_[0]:12 0.00341 +7 bottom_left_grid_pin_35_[0]:12 bottom_left_grid_pin_35_[0]:11 0.002952383 +8 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:14 0.0045 +9 bottom_left_grid_pin_35_[0]:14 bottom_left_grid_pin_35_[0]:13 0.002640625 +10 bottom_left_grid_pin_35_[0]:16 mux_bottom_track_5\/mux_l2_in_2_:A0 0.152 +11 bottom_left_grid_pin_35_[0]:8 bottom_left_grid_pin_35_[0]:7 0.0004888393 +12 bottom_left_grid_pin_35_[0]:9 bottom_left_grid_pin_35_[0]:8 0.0045 +13 bottom_left_grid_pin_35_[0]:9 bottom_left_grid_pin_35_[0]:6 0.006638393 +14 bottom_left_grid_pin_35_[0]:7 mux_bottom_track_3\/mux_l1_in_2_:A0 0.152 +15 bottom_left_grid_pin_35_[0]:19 bottom_left_grid_pin_35_[0]:18 0.00365625 +16 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_35_[0]:19 0.0045 +17 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_35_[0]:20 0.01083705 +18 bottom_left_grid_pin_35_[0]:22 bottom_left_grid_pin_35_[0]:21 0.00341 +19 bottom_left_grid_pin_35_[0]:18 bottom_left_grid_pin_35_[0]:17 0.0003035715 +20 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_35_[0]:16 0.0005290179 +21 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_35_[0]:15 0.008584822 + +*END + +*D_NET chanx_left_in[15] 0.01201134 //LENGTH 81.295 LUMPCC 0.003217819 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 77.520 +*I mux_bottom_track_17\/mux_l2_in_2_:A0 I *L 0.001631 *C 44.335 42.500 +*I mux_top_track_4\/mux_l2_in_7_:A1 I *L 0.00198 *C 39.925 79.900 +*N chanx_left_in[15]:3 *C 39.925 79.900 +*N chanx_left_in[15]:4 *C 40.020 79.855 +*N chanx_left_in[15]:5 *C 44.297 42.500 +*N chanx_left_in[15]:6 *C 40.065 42.500 +*N chanx_left_in[15]:7 *C 40.020 42.545 +*N chanx_left_in[15]:8 *C 40.020 77.520 +*N chanx_left_in[15]:9 *C 40.013 77.520 + +*CAP +0 chanx_left_in[15] 0.002030907 +1 mux_bottom_track_17\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_4\/mux_l2_in_7_:A1 1e-06 +3 chanx_left_in[15]:3 2.881073e-05 +4 chanx_left_in[15]:4 0.0001421483 +5 chanx_left_in[15]:5 0.0002617364 +6 chanx_left_in[15]:6 0.0002617364 +7 chanx_left_in[15]:7 0.001927163 +8 chanx_left_in[15]:8 0.002108116 +9 chanx_left_in[15]:9 0.002030907 +10 chanx_left_in[15] chanx_left_in[5]:26 0.0002911511 +11 chanx_left_in[15]:9 chanx_left_in[5]:25 0.0002911511 +12 chanx_left_in[15] chanx_left_in[0]:24 0.0007589634 +13 chanx_left_in[15] chanx_left_in[0]:25 0.0004903292 +14 chanx_left_in[15]:9 chanx_left_in[0]:11 0.0007589634 +15 chanx_left_in[15]:9 chanx_left_in[0]:24 0.0004903292 +16 chanx_left_in[15]:8 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 6.846568e-05 +17 chanx_left_in[15]:7 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 6.846568e-05 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:9 0.006075925 +1 chanx_left_in[15]:8 chanx_left_in[15]:7 0.03122768 +2 chanx_left_in[15]:8 chanx_left_in[15]:4 0.002084821 +3 chanx_left_in[15]:9 chanx_left_in[15]:8 0.00341 +4 chanx_left_in[15]:6 chanx_left_in[15]:5 0.003779018 +5 chanx_left_in[15]:7 chanx_left_in[15]:6 0.0045 +6 chanx_left_in[15]:5 mux_bottom_track_17\/mux_l2_in_2_:A0 0.152 +7 chanx_left_in[15]:3 mux_top_track_4\/mux_l2_in_7_:A1 0.152 +8 chanx_left_in[15]:4 chanx_left_in[15]:3 0.0045 + +*END + +*D_NET left_top_grid_pin_46_[0] 0.007736734 //LENGTH 58.760 LUMPCC 0.0002333482 DR + +*CONN +*P left_top_grid_pin_46_[0] I *L 0.29796 *C 2.300 102.070 +*I mux_left_track_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 18.115 80.580 +*I mux_left_track_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 30.920 77.860 +*I mux_left_track_5\/mux_l2_in_5_:A0 I *L 0.001631 *C 19.955 91.460 +*N left_top_grid_pin_46_[0]:4 *C 19.918 91.460 +*N left_top_grid_pin_46_[0]:5 *C 30.883 77.860 +*N left_top_grid_pin_46_[0]:6 *C 28.565 77.860 +*N left_top_grid_pin_46_[0]:7 *C 28.520 77.860 +*N left_top_grid_pin_46_[0]:8 *C 28.520 80.183 +*N left_top_grid_pin_46_[0]:9 *C 28.513 80.240 +*N left_top_grid_pin_46_[0]:10 *C 17.948 80.240 +*N left_top_grid_pin_46_[0]:11 *C 17.940 80.240 +*N left_top_grid_pin_46_[0]:12 *C 18.115 80.580 +*N left_top_grid_pin_46_[0]:13 *C 17.940 80.580 +*N left_top_grid_pin_46_[0]:14 *C 17.940 80.625 +*N left_top_grid_pin_46_[0]:15 *C 17.940 91.415 +*N left_top_grid_pin_46_[0]:16 *C 17.940 91.460 +*N left_top_grid_pin_46_[0]:17 *C 17.940 91.800 +*N left_top_grid_pin_46_[0]:18 *C 1.885 91.800 +*N left_top_grid_pin_46_[0]:19 *C 1.840 91.845 +*N left_top_grid_pin_46_[0]:20 *C 1.840 97.240 +*N left_top_grid_pin_46_[0]:21 *C 2.300 97.240 + +*CAP +0 left_top_grid_pin_46_[0] 0.0002527518 +1 mux_left_track_1\/mux_l2_in_2_:A0 1e-06 +2 mux_left_track_9\/mux_l2_in_3_:A1 1e-06 +3 mux_left_track_5\/mux_l2_in_5_:A0 1e-06 +4 left_top_grid_pin_46_[0]:4 0.0001438169 +5 left_top_grid_pin_46_[0]:5 0.0001639363 +6 left_top_grid_pin_46_[0]:6 0.0001639363 +7 left_top_grid_pin_46_[0]:7 0.0002088944 +8 left_top_grid_pin_46_[0]:8 0.0001754276 +9 left_top_grid_pin_46_[0]:9 0.0009639719 +10 left_top_grid_pin_46_[0]:10 0.0009639719 +11 left_top_grid_pin_46_[0]:11 5.884886e-05 +12 left_top_grid_pin_46_[0]:12 5.406723e-05 +13 left_top_grid_pin_46_[0]:13 5.786883e-05 +14 left_top_grid_pin_46_[0]:14 0.0006237627 +15 left_top_grid_pin_46_[0]:15 0.0006022489 +16 left_top_grid_pin_46_[0]:16 0.0001745558 +17 left_top_grid_pin_46_[0]:17 0.000980885 +18 left_top_grid_pin_46_[0]:18 0.0009501462 +19 left_top_grid_pin_46_[0]:19 0.0003244662 +20 left_top_grid_pin_46_[0]:20 0.0003542715 +21 left_top_grid_pin_46_[0]:21 0.0002825572 +22 left_top_grid_pin_46_[0] ropt_net_183:5 3.938094e-06 +23 left_top_grid_pin_46_[0]:18 ropt_net_183:7 0.0001007718 +24 left_top_grid_pin_46_[0]:18 ropt_net_183:9 8.067064e-06 +25 left_top_grid_pin_46_[0]:19 ropt_net_183:6 3.897127e-06 +26 left_top_grid_pin_46_[0]:17 ropt_net_183:10 8.067064e-06 +27 left_top_grid_pin_46_[0]:17 ropt_net_183:8 0.0001007718 +28 left_top_grid_pin_46_[0]:20 ropt_net_183:5 3.897127e-06 +29 left_top_grid_pin_46_[0]:21 ropt_net_183:6 3.938094e-06 + +*RES +0 left_top_grid_pin_46_[0] left_top_grid_pin_46_[0]:21 0.0043125 +1 left_top_grid_pin_46_[0]:16 left_top_grid_pin_46_[0]:15 0.0045 +2 left_top_grid_pin_46_[0]:16 left_top_grid_pin_46_[0]:4 0.001765625 +3 left_top_grid_pin_46_[0]:15 left_top_grid_pin_46_[0]:14 0.009633929 +4 left_top_grid_pin_46_[0]:4 mux_left_track_5\/mux_l2_in_5_:A0 0.152 +5 left_top_grid_pin_46_[0]:11 left_top_grid_pin_46_[0]:10 0.00341 +6 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:9 0.001655183 +7 left_top_grid_pin_46_[0]:8 left_top_grid_pin_46_[0]:7 0.002073661 +8 left_top_grid_pin_46_[0]:9 left_top_grid_pin_46_[0]:8 0.00341 +9 left_top_grid_pin_46_[0]:6 left_top_grid_pin_46_[0]:5 0.002069197 +10 left_top_grid_pin_46_[0]:7 left_top_grid_pin_46_[0]:6 0.0045 +11 left_top_grid_pin_46_[0]:5 mux_left_track_9\/mux_l2_in_3_:A1 0.152 +12 left_top_grid_pin_46_[0]:13 left_top_grid_pin_46_[0]:12 9.510869e-05 +13 left_top_grid_pin_46_[0]:14 left_top_grid_pin_46_[0]:13 0.0045 +14 left_top_grid_pin_46_[0]:14 left_top_grid_pin_46_[0]:11 0.0001850962 +15 left_top_grid_pin_46_[0]:12 mux_left_track_1\/mux_l2_in_2_:A0 0.152 +16 left_top_grid_pin_46_[0]:18 left_top_grid_pin_46_[0]:17 0.01433482 +17 left_top_grid_pin_46_[0]:19 left_top_grid_pin_46_[0]:18 0.0045 +18 left_top_grid_pin_46_[0]:17 left_top_grid_pin_46_[0]:16 0.0003035715 +19 left_top_grid_pin_46_[0]:20 left_top_grid_pin_46_[0]:19 0.004816964 +20 left_top_grid_pin_46_[0]:21 left_top_grid_pin_46_[0]:20 0.0004107143 + +*END + +*D_NET chanx_right_out[12] 0.003425585 //LENGTH 30.235 LUMPCC 0.0005608101 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 129.780 60.860 +*P chanx_right_out[12] O *L 0.7423 *C 140.450 42.160 +*N chanx_right_out[12]:2 *C 136.168 42.160 +*N chanx_right_out[12]:3 *C 136.160 42.160 +*N chanx_right_out[12]:4 *C 136.115 42.160 +*N chanx_right_out[12]:5 *C 129.765 42.160 +*N chanx_right_out[12]:6 *C 129.720 42.205 +*N chanx_right_out[12]:7 *C 129.720 60.815 +*N chanx_right_out[12]:8 *C 129.720 60.860 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 0.0001727662 +2 chanx_right_out[12]:2 0.0001727662 +3 chanx_right_out[12]:3 3.743016e-05 +4 chanx_right_out[12]:4 0.0003277402 +5 chanx_right_out[12]:5 0.0003277402 +6 chanx_right_out[12]:6 0.0008955792 +7 chanx_right_out[12]:7 0.0008955792 +8 chanx_right_out[12]:8 3.417356e-05 +9 chanx_right_out[12] chanx_right_out[16]:2 0.0002499137 +10 chanx_right_out[12]:7 chanx_right_out[16]:5 2.045998e-05 +11 chanx_right_out[12]:5 chanx_right_out[16]:3 1.003134e-05 +12 chanx_right_out[12]:6 chanx_right_out[16]:4 2.045998e-05 +13 chanx_right_out[12]:4 chanx_right_out[16]:2 1.003134e-05 +14 chanx_right_out[12]:2 chanx_right_out[16]:3 0.0002499137 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:8 0.152 +1 chanx_right_out[12]:8 chanx_right_out[12]:7 0.0045 +2 chanx_right_out[12]:7 chanx_right_out[12]:6 0.01661607 +3 chanx_right_out[12]:5 chanx_right_out[12]:4 0.005669643 +4 chanx_right_out[12]:6 chanx_right_out[12]:5 0.0045 +5 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0045 +6 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +7 chanx_right_out[12]:2 chanx_right_out[12] 0.000670925 + +*END + +*D_NET ropt_net_155 0.0005433153 //LENGTH 3.415 LUMPCC 0.0002585461 DR + +*CONN +*I mem_left_track_33\/FTB_28__79:X O *L 0 *C 3.005 64.600 +*I ropt_mt_inst_793:A I *L 0.001767 *C 3.220 66.640 +*N ropt_net_155:2 *C 3.183 66.640 +*N ropt_net_155:3 *C 2.805 66.640 +*N ropt_net_155:4 *C 2.760 66.595 +*N ropt_net_155:5 *C 2.760 64.645 +*N ropt_net_155:6 *C 2.760 64.600 +*N ropt_net_155:7 *C 3.005 64.600 + +*CAP +0 mem_left_track_33\/FTB_28__79:X 1e-06 +1 ropt_mt_inst_793:A 1e-06 +2 ropt_net_155:2 4.457781e-05 +3 ropt_net_155:3 4.457781e-05 +4 ropt_net_155:4 4.188021e-05 +5 ropt_net_155:5 4.188021e-05 +6 ropt_net_155:6 5.513099e-05 +7 ropt_net_155:7 5.472219e-05 +8 ropt_net_155:4 chanx_right_in[8]:7 6.463652e-05 +9 ropt_net_155:5 chanx_right_in[8]:8 6.463652e-05 +10 ropt_net_155:4 chanx_left_out[0]:4 6.463652e-05 +11 ropt_net_155:5 chanx_left_out[0]:3 6.463652e-05 + +*RES +0 mem_left_track_33\/FTB_28__79:X ropt_net_155:7 0.152 +1 ropt_net_155:2 ropt_mt_inst_793:A 0.152 +2 ropt_net_155:3 ropt_net_155:2 0.0003370536 +3 ropt_net_155:4 ropt_net_155:3 0.0045 +4 ropt_net_155:6 ropt_net_155:5 0.0045 +5 ropt_net_155:5 ropt_net_155:4 0.001741072 +6 ropt_net_155:7 ropt_net_155:6 0.0001331522 + +*END + +*D_NET mux_tree_tapbuf_size10_10_sram[2] 0.00393884 //LENGTH 29.735 LUMPCC 0 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 37.565 63.920 +*I mux_left_track_17\/mux_l3_in_1_:S I *L 0.00357 *C 29.340 61.880 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 24.080 58.820 +*I mux_left_track_17\/mux_l3_in_0_:S I *L 0.00357 *C 35.060 56.440 +*N mux_tree_tapbuf_size10_10_sram[2]:4 *C 35.075 56.440 +*N mux_tree_tapbuf_size10_10_sram[2]:5 *C 35.398 56.440 +*N mux_tree_tapbuf_size10_10_sram[2]:6 *C 35.420 56.485 +*N mux_tree_tapbuf_size10_10_sram[2]:7 *C 24.080 58.820 +*N mux_tree_tapbuf_size10_10_sram[2]:8 *C 26.680 58.820 +*N mux_tree_tapbuf_size10_10_sram[2]:9 *C 29.303 61.880 +*N mux_tree_tapbuf_size10_10_sram[2]:10 *C 26.725 61.880 +*N mux_tree_tapbuf_size10_10_sram[2]:11 *C 26.680 61.835 +*N mux_tree_tapbuf_size10_10_sram[2]:12 *C 26.680 59.205 +*N mux_tree_tapbuf_size10_10_sram[2]:13 *C 26.680 59.160 +*N mux_tree_tapbuf_size10_10_sram[2]:14 *C 35.375 59.160 +*N mux_tree_tapbuf_size10_10_sram[2]:15 *C 35.420 59.160 +*N mux_tree_tapbuf_size10_10_sram[2]:16 *C 35.880 59.160 +*N mux_tree_tapbuf_size10_10_sram[2]:17 *C 35.880 63.875 +*N mux_tree_tapbuf_size10_10_sram[2]:18 *C 35.925 63.920 +*N mux_tree_tapbuf_size10_10_sram[2]:19 *C 37.528 63.920 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_17\/mux_l3_in_1_:S 1e-06 +2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_17\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_10_sram[2]:4 6.109267e-05 +5 mux_tree_tapbuf_size10_10_sram[2]:5 6.109267e-05 +6 mux_tree_tapbuf_size10_10_sram[2]:6 0.0001678272 +7 mux_tree_tapbuf_size10_10_sram[2]:7 0.0002137608 +8 mux_tree_tapbuf_size10_10_sram[2]:8 0.0002068883 +9 mux_tree_tapbuf_size10_10_sram[2]:9 0.0002183727 +10 mux_tree_tapbuf_size10_10_sram[2]:10 0.0002183727 +11 mux_tree_tapbuf_size10_10_sram[2]:11 0.0001985021 +12 mux_tree_tapbuf_size10_10_sram[2]:12 0.0001985021 +13 mux_tree_tapbuf_size10_10_sram[2]:13 0.0006574663 +14 mux_tree_tapbuf_size10_10_sram[2]:14 0.0006269517 +15 mux_tree_tapbuf_size10_10_sram[2]:15 0.0002042477 +16 mux_tree_tapbuf_size10_10_sram[2]:16 0.0003177151 +17 mux_tree_tapbuf_size10_10_sram[2]:17 0.0002812945 +18 mux_tree_tapbuf_size10_10_sram[2]:18 0.0001513769 +19 mux_tree_tapbuf_size10_10_sram[2]:19 0.0001513769 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_10_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_10_sram[2]:7 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size10_10_sram[2]:5 mux_tree_tapbuf_size10_10_sram[2]:4 0.0001752718 +3 mux_tree_tapbuf_size10_10_sram[2]:6 mux_tree_tapbuf_size10_10_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size10_10_sram[2]:4 mux_left_track_17\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_10_sram[2]:14 mux_tree_tapbuf_size10_10_sram[2]:13 0.007763393 +6 mux_tree_tapbuf_size10_10_sram[2]:15 mux_tree_tapbuf_size10_10_sram[2]:14 0.0045 +7 mux_tree_tapbuf_size10_10_sram[2]:15 mux_tree_tapbuf_size10_10_sram[2]:6 0.002388393 +8 mux_tree_tapbuf_size10_10_sram[2]:18 mux_tree_tapbuf_size10_10_sram[2]:17 0.0045 +9 mux_tree_tapbuf_size10_10_sram[2]:17 mux_tree_tapbuf_size10_10_sram[2]:16 0.004209822 +10 mux_tree_tapbuf_size10_10_sram[2]:19 mux_tree_tapbuf_size10_10_sram[2]:18 0.001430804 +11 mux_tree_tapbuf_size10_10_sram[2]:13 mux_tree_tapbuf_size10_10_sram[2]:12 0.0045 +12 mux_tree_tapbuf_size10_10_sram[2]:13 mux_tree_tapbuf_size10_10_sram[2]:8 0.0003035715 +13 mux_tree_tapbuf_size10_10_sram[2]:12 mux_tree_tapbuf_size10_10_sram[2]:11 0.002348214 +14 mux_tree_tapbuf_size10_10_sram[2]:10 mux_tree_tapbuf_size10_10_sram[2]:9 0.00230134 +15 mux_tree_tapbuf_size10_10_sram[2]:11 mux_tree_tapbuf_size10_10_sram[2]:10 0.0045 +16 mux_tree_tapbuf_size10_10_sram[2]:9 mux_left_track_17\/mux_l3_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_10_sram[2]:8 mux_tree_tapbuf_size10_10_sram[2]:7 0.002321429 +18 mux_tree_tapbuf_size10_10_sram[2]:16 mux_tree_tapbuf_size10_10_sram[2]:15 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[2] 0.003301 //LENGTH 21.995 LUMPCC 0.0009262455 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 57.805 77.520 +*I mux_top_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 60.140 72.420 +*I mux_top_track_24\/mux_l3_in_1_:S I *L 0.00357 *C 56.940 68.680 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 52.155 80.580 +*N mux_tree_tapbuf_size10_2_sram[2]:4 *C 52.193 80.580 +*N mux_tree_tapbuf_size10_2_sram[2]:5 *C 57.455 80.580 +*N mux_tree_tapbuf_size10_2_sram[2]:6 *C 57.500 80.535 +*N mux_tree_tapbuf_size10_2_sram[2]:7 *C 56.940 68.680 +*N mux_tree_tapbuf_size10_2_sram[2]:8 *C 57.040 68.725 +*N mux_tree_tapbuf_size10_2_sram[2]:9 *C 57.040 72.420 +*N mux_tree_tapbuf_size10_2_sram[2]:10 *C 60.103 72.420 +*N mux_tree_tapbuf_size10_2_sram[2]:11 *C 57.545 72.420 +*N mux_tree_tapbuf_size10_2_sram[2]:12 *C 57.500 72.465 +*N mux_tree_tapbuf_size10_2_sram[2]:13 *C 57.500 77.520 +*N mux_tree_tapbuf_size10_2_sram[2]:14 *C 57.500 77.520 +*N mux_tree_tapbuf_size10_2_sram[2]:15 *C 57.805 77.520 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:S 1e-06 +2 mux_top_track_24\/mux_l3_in_1_:S 1e-06 +3 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_2_sram[2]:4 0.0003752062 +5 mux_tree_tapbuf_size10_2_sram[2]:5 0.0003752062 +6 mux_tree_tapbuf_size10_2_sram[2]:6 0.0001618546 +7 mux_tree_tapbuf_size10_2_sram[2]:7 2.952339e-05 +8 mux_tree_tapbuf_size10_2_sram[2]:8 0.0001447622 +9 mux_tree_tapbuf_size10_2_sram[2]:9 0.0001458022 +10 mux_tree_tapbuf_size10_2_sram[2]:10 0.0001684375 +11 mux_tree_tapbuf_size10_2_sram[2]:11 0.0001684375 +12 mux_tree_tapbuf_size10_2_sram[2]:12 0.0002450087 +13 mux_tree_tapbuf_size10_2_sram[2]:13 0.000440856 +14 mux_tree_tapbuf_size10_2_sram[2]:14 6.004763e-05 +15 mux_tree_tapbuf_size10_2_sram[2]:15 5.561181e-05 +16 mux_tree_tapbuf_size10_2_sram[2]:12 optlc_net_148:6 0.0001289975 +17 mux_tree_tapbuf_size10_2_sram[2]:6 optlc_net_148:7 7.932229e-05 +18 mux_tree_tapbuf_size10_2_sram[2]:13 optlc_net_148:7 0.0001289975 +19 mux_tree_tapbuf_size10_2_sram[2]:13 optlc_net_148:6 7.932229e-05 +20 mux_tree_tapbuf_size10_2_sram[2]:8 optlc_net_148:6 3.506344e-05 +21 mux_tree_tapbuf_size10_2_sram[2]:9 optlc_net_148:7 3.506344e-05 +22 mux_tree_tapbuf_size10_2_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.165019e-05 +23 mux_tree_tapbuf_size10_2_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.031909e-05 +24 mux_tree_tapbuf_size10_2_sram[2]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.165019e-05 +25 mux_tree_tapbuf_size10_2_sram[2]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.561412e-05 +26 mux_tree_tapbuf_size10_2_sram[2]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.561412e-05 +27 mux_tree_tapbuf_size10_2_sram[2]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.031909e-05 +28 mux_tree_tapbuf_size10_2_sram[2]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001065225 +29 mux_tree_tapbuf_size10_2_sram[2]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001065225 +30 mux_tree_tapbuf_size10_2_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.563361e-05 +31 mux_tree_tapbuf_size10_2_sram[2]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.563361e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_2_sram[2]:15 0.152 +1 mux_tree_tapbuf_size10_2_sram[2]:10 mux_top_track_24\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[2]:11 mux_tree_tapbuf_size10_2_sram[2]:10 0.002283482 +3 mux_tree_tapbuf_size10_2_sram[2]:12 mux_tree_tapbuf_size10_2_sram[2]:11 0.0045 +4 mux_tree_tapbuf_size10_2_sram[2]:12 mux_tree_tapbuf_size10_2_sram[2]:9 0.0004107143 +5 mux_tree_tapbuf_size10_2_sram[2]:5 mux_tree_tapbuf_size10_2_sram[2]:4 0.004698661 +6 mux_tree_tapbuf_size10_2_sram[2]:6 mux_tree_tapbuf_size10_2_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size10_2_sram[2]:4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_2_sram[2]:14 mux_tree_tapbuf_size10_2_sram[2]:13 0.0045 +9 mux_tree_tapbuf_size10_2_sram[2]:13 mux_tree_tapbuf_size10_2_sram[2]:12 0.004513393 +10 mux_tree_tapbuf_size10_2_sram[2]:13 mux_tree_tapbuf_size10_2_sram[2]:6 0.002691964 +11 mux_tree_tapbuf_size10_2_sram[2]:15 mux_tree_tapbuf_size10_2_sram[2]:14 0.0001657609 +12 mux_tree_tapbuf_size10_2_sram[2]:7 mux_top_track_24\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_2_sram[2]:8 mux_tree_tapbuf_size10_2_sram[2]:7 0.0045 +14 mux_tree_tapbuf_size10_2_sram[2]:9 mux_tree_tapbuf_size10_2_sram[2]:8 0.003299107 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[1] 0.004353313 //LENGTH 33.355 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 96.905 77.180 +*I mux_right_track_24\/mux_l2_in_3_:S I *L 0.00357 *C 98.340 74.460 +*I mux_right_track_24\/mux_l2_in_2_:S I *L 0.00357 *C 98.780 72.760 +*I mux_right_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 94.660 79.560 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 95.855 86.020 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 85.920 85.680 +*N mux_tree_tapbuf_size10_5_sram[1]:6 *C 85.920 85.680 +*N mux_tree_tapbuf_size10_5_sram[1]:7 *C 86.020 85.725 +*N mux_tree_tapbuf_size10_5_sram[1]:8 *C 86.020 86.315 +*N mux_tree_tapbuf_size10_5_sram[1]:9 *C 86.065 86.360 +*N mux_tree_tapbuf_size10_5_sram[1]:10 *C 96.140 86.360 +*N mux_tree_tapbuf_size10_5_sram[1]:11 *C 95.855 86.020 +*N mux_tree_tapbuf_size10_5_sram[1]:12 *C 96.140 86.020 +*N mux_tree_tapbuf_size10_5_sram[1]:13 *C 96.140 85.975 +*N mux_tree_tapbuf_size10_5_sram[1]:14 *C 96.140 84.320 +*N mux_tree_tapbuf_size10_5_sram[1]:15 *C 96.600 84.320 +*N mux_tree_tapbuf_size10_5_sram[1]:16 *C 94.698 79.560 +*N mux_tree_tapbuf_size10_5_sram[1]:17 *C 96.555 79.560 +*N mux_tree_tapbuf_size10_5_sram[1]:18 *C 96.600 79.560 +*N mux_tree_tapbuf_size10_5_sram[1]:19 *C 97.060 79.560 +*N mux_tree_tapbuf_size10_5_sram[1]:20 *C 98.743 72.760 +*N mux_tree_tapbuf_size10_5_sram[1]:21 *C 97.565 72.760 +*N mux_tree_tapbuf_size10_5_sram[1]:22 *C 97.520 72.805 +*N mux_tree_tapbuf_size10_5_sram[1]:23 *C 98.303 74.460 +*N mux_tree_tapbuf_size10_5_sram[1]:24 *C 97.565 74.460 +*N mux_tree_tapbuf_size10_5_sram[1]:25 *C 97.520 74.460 +*N mux_tree_tapbuf_size10_5_sram[1]:26 *C 97.520 75.480 +*N mux_tree_tapbuf_size10_5_sram[1]:27 *C 97.060 75.480 +*N mux_tree_tapbuf_size10_5_sram[1]:28 *C 97.060 77.180 +*N mux_tree_tapbuf_size10_5_sram[1]:29 *C 97.060 77.180 +*N mux_tree_tapbuf_size10_5_sram[1]:30 *C 96.905 77.180 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_24\/mux_l2_in_3_:S 1e-06 +2 mux_right_track_24\/mux_l2_in_2_:S 1e-06 +3 mux_right_track_24\/mux_l2_in_1_:S 1e-06 +4 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_5_sram[1]:6 2.828691e-05 +7 mux_tree_tapbuf_size10_5_sram[1]:7 5.804651e-05 +8 mux_tree_tapbuf_size10_5_sram[1]:8 5.804651e-05 +9 mux_tree_tapbuf_size10_5_sram[1]:9 0.00066845 +10 mux_tree_tapbuf_size10_5_sram[1]:10 0.0007004936 +11 mux_tree_tapbuf_size10_5_sram[1]:11 2.941019e-05 +12 mux_tree_tapbuf_size10_5_sram[1]:12 8.114348e-05 +13 mux_tree_tapbuf_size10_5_sram[1]:13 0.0001176071 +14 mux_tree_tapbuf_size10_5_sram[1]:14 0.0001487584 +15 mux_tree_tapbuf_size10_5_sram[1]:15 0.0003113855 +16 mux_tree_tapbuf_size10_5_sram[1]:16 0.0001504114 +17 mux_tree_tapbuf_size10_5_sram[1]:17 0.0001504114 +18 mux_tree_tapbuf_size10_5_sram[1]:18 0.0003142068 +19 mux_tree_tapbuf_size10_5_sram[1]:19 0.0001702295 +20 mux_tree_tapbuf_size10_5_sram[1]:20 0.0001110486 +21 mux_tree_tapbuf_size10_5_sram[1]:21 0.0001110486 +22 mux_tree_tapbuf_size10_5_sram[1]:22 0.0001294538 +23 mux_tree_tapbuf_size10_5_sram[1]:23 7.879306e-05 +24 mux_tree_tapbuf_size10_5_sram[1]:24 7.879306e-05 +25 mux_tree_tapbuf_size10_5_sram[1]:25 0.0002366868 +26 mux_tree_tapbuf_size10_5_sram[1]:26 0.0001094206 +27 mux_tree_tapbuf_size10_5_sram[1]:27 0.0001349201 +28 mux_tree_tapbuf_size10_5_sram[1]:28 0.0002688146 +29 mux_tree_tapbuf_size10_5_sram[1]:29 5.3042e-05 +30 mux_tree_tapbuf_size10_5_sram[1]:30 4.840449e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_5_sram[1]:30 0.152 +1 mux_tree_tapbuf_size10_5_sram[1]:23 mux_right_track_24\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size10_5_sram[1]:24 mux_tree_tapbuf_size10_5_sram[1]:23 0.0006584821 +3 mux_tree_tapbuf_size10_5_sram[1]:25 mux_tree_tapbuf_size10_5_sram[1]:24 0.0045 +4 mux_tree_tapbuf_size10_5_sram[1]:25 mux_tree_tapbuf_size10_5_sram[1]:22 0.001477679 +5 mux_tree_tapbuf_size10_5_sram[1]:12 mux_tree_tapbuf_size10_5_sram[1]:11 0.0001548913 +6 mux_tree_tapbuf_size10_5_sram[1]:12 mux_tree_tapbuf_size10_5_sram[1]:10 0.0003035714 +7 mux_tree_tapbuf_size10_5_sram[1]:13 mux_tree_tapbuf_size10_5_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size10_5_sram[1]:20 mux_right_track_24\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size10_5_sram[1]:21 mux_tree_tapbuf_size10_5_sram[1]:20 0.001051339 +10 mux_tree_tapbuf_size10_5_sram[1]:22 mux_tree_tapbuf_size10_5_sram[1]:21 0.0045 +11 mux_tree_tapbuf_size10_5_sram[1]:11 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size10_5_sram[1]:29 mux_tree_tapbuf_size10_5_sram[1]:28 0.0045 +13 mux_tree_tapbuf_size10_5_sram[1]:28 mux_tree_tapbuf_size10_5_sram[1]:27 0.001517857 +14 mux_tree_tapbuf_size10_5_sram[1]:28 mux_tree_tapbuf_size10_5_sram[1]:19 0.002125 +15 mux_tree_tapbuf_size10_5_sram[1]:30 mux_tree_tapbuf_size10_5_sram[1]:29 8.423914e-05 +16 mux_tree_tapbuf_size10_5_sram[1]:17 mux_tree_tapbuf_size10_5_sram[1]:16 0.001658482 +17 mux_tree_tapbuf_size10_5_sram[1]:18 mux_tree_tapbuf_size10_5_sram[1]:17 0.0045 +18 mux_tree_tapbuf_size10_5_sram[1]:18 mux_tree_tapbuf_size10_5_sram[1]:15 0.00425 +19 mux_tree_tapbuf_size10_5_sram[1]:16 mux_right_track_24\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_5_sram[1]:6 mux_right_track_24\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_5_sram[1]:7 mux_tree_tapbuf_size10_5_sram[1]:6 0.0045 +22 mux_tree_tapbuf_size10_5_sram[1]:9 mux_tree_tapbuf_size10_5_sram[1]:8 0.0045 +23 mux_tree_tapbuf_size10_5_sram[1]:8 mux_tree_tapbuf_size10_5_sram[1]:7 0.0005267857 +24 mux_tree_tapbuf_size10_5_sram[1]:10 mux_tree_tapbuf_size10_5_sram[1]:9 0.008995536 +25 mux_tree_tapbuf_size10_5_sram[1]:14 mux_tree_tapbuf_size10_5_sram[1]:13 0.001477679 +26 mux_tree_tapbuf_size10_5_sram[1]:15 mux_tree_tapbuf_size10_5_sram[1]:14 0.0004107143 +27 mux_tree_tapbuf_size10_5_sram[1]:19 mux_tree_tapbuf_size10_5_sram[1]:18 0.0004107143 +28 mux_tree_tapbuf_size10_5_sram[1]:27 mux_tree_tapbuf_size10_5_sram[1]:26 0.0004107143 +29 mux_tree_tapbuf_size10_5_sram[1]:26 mux_tree_tapbuf_size10_5_sram[1]:25 0.0009107143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.001858864 //LENGTH 14.860 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/FTB_13__64:X O *L 0 *C 114.765 48.280 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 102.295 49.980 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 102.333 49.980 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 114.495 49.980 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 114.540 49.935 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 114.540 48.325 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 114.540 48.280 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 114.765 48.280 + +*CAP +0 mem_top_track_8\/FTB_13__64:X 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0007676683 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0007676683 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0001058709 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0001058709 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 5.56636e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 5.412146e-05 + +*RES +0 mem_top_track_8\/FTB_13__64:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.01085938 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_8_ccff_tail[0] 0.0008969111 //LENGTH 6.500 LUMPCC 0.0001734193 DR + +*CONN +*I mem_bottom_track_25\/FTB_21__72:X O *L 0 *C 24.145 41.480 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 21.335 44.540 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 *C 21.335 44.540 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 *C 21.620 44.540 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 *C 21.620 44.495 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 *C 21.620 41.525 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 *C 21.665 41.480 +*N mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 *C 24.108 41.480 + +*CAP +0 mem_bottom_track_25\/FTB_21__72:X 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 5.171446e-05 +3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 5.605585e-05 +4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 0.0001281617 +5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 0.0001281617 +6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 0.0001786991 +7 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 0.0001786991 +8 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 prog_clk[0]:640 8.670967e-05 +9 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 prog_clk[0]:646 8.670967e-05 + +*RES +0 mem_bottom_track_25\/FTB_21__72:X mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_8_ccff_tail[0]:6 0.002180804 + +*END + +*D_NET mux_tree_tapbuf_size12_2_sram[0] 0.01008268 //LENGTH 77.865 LUMPCC 0.002377619 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 94.605 118.320 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 91.715 115.260 +*I mux_right_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 90.980 104.720 +*I mux_right_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 101.760 104.720 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 82.240 99.960 +*I mux_right_track_0\/mux_l1_in_4_:S I *L 0.00357 *C 78.100 78.200 +*I mux_right_track_0\/mux_l1_in_3_:S I *L 0.00357 *C 93.280 99.960 +*N mux_tree_tapbuf_size12_2_sram[0]:7 *C 93.280 99.960 +*N mux_tree_tapbuf_size12_2_sram[0]:8 *C 93.380 100.005 +*N mux_tree_tapbuf_size12_2_sram[0]:9 *C 78.100 78.200 +*N mux_tree_tapbuf_size12_2_sram[0]:10 *C 78.200 78.245 +*N mux_tree_tapbuf_size12_2_sram[0]:11 *C 78.200 79.855 +*N mux_tree_tapbuf_size12_2_sram[0]:12 *C 78.245 79.900 +*N mux_tree_tapbuf_size12_2_sram[0]:13 *C 80.040 79.900 +*N mux_tree_tapbuf_size12_2_sram[0]:14 *C 80.040 80.240 +*N mux_tree_tapbuf_size12_2_sram[0]:15 *C 83.675 80.240 +*N mux_tree_tapbuf_size12_2_sram[0]:16 *C 83.720 80.285 +*N mux_tree_tapbuf_size12_2_sram[0]:17 *C 82.278 99.960 +*N mux_tree_tapbuf_size12_2_sram[0]:18 *C 83.675 99.960 +*N mux_tree_tapbuf_size12_2_sram[0]:19 *C 83.720 99.960 +*N mux_tree_tapbuf_size12_2_sram[0]:20 *C 83.720 101.955 +*N mux_tree_tapbuf_size12_2_sram[0]:21 *C 83.765 102.000 +*N mux_tree_tapbuf_size12_2_sram[0]:22 *C 93.335 102.000 +*N mux_tree_tapbuf_size12_2_sram[0]:23 *C 93.380 102.000 +*N mux_tree_tapbuf_size12_2_sram[0]:24 *C 101.723 104.720 +*N mux_tree_tapbuf_size12_2_sram[0]:25 *C 90.980 104.720 +*N mux_tree_tapbuf_size12_2_sram[0]:26 *C 91.080 104.380 +*N mux_tree_tapbuf_size12_2_sram[0]:27 *C 93.380 104.380 +*N mux_tree_tapbuf_size12_2_sram[0]:28 *C 93.380 104.720 +*N mux_tree_tapbuf_size12_2_sram[0]:29 *C 93.380 104.720 +*N mux_tree_tapbuf_size12_2_sram[0]:30 *C 93.380 113.220 +*N mux_tree_tapbuf_size12_2_sram[0]:31 *C 92.920 113.220 +*N mux_tree_tapbuf_size12_2_sram[0]:32 *C 91.752 115.260 +*N mux_tree_tapbuf_size12_2_sram[0]:33 *C 92.875 115.260 +*N mux_tree_tapbuf_size12_2_sram[0]:34 *C 92.920 115.260 +*N mux_tree_tapbuf_size12_2_sram[0]:35 *C 93.380 115.260 +*N mux_tree_tapbuf_size12_2_sram[0]:36 *C 93.380 118.275 +*N mux_tree_tapbuf_size12_2_sram[0]:37 *C 93.425 118.320 +*N mux_tree_tapbuf_size12_2_sram[0]:38 *C 94.568 118.320 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:S 1e-06 +4 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +5 mux_right_track_0\/mux_l1_in_4_:S 1e-06 +6 mux_right_track_0\/mux_l1_in_3_:S 1e-06 +7 mux_tree_tapbuf_size12_2_sram[0]:7 2.658539e-05 +8 mux_tree_tapbuf_size12_2_sram[0]:8 0.0001102864 +9 mux_tree_tapbuf_size12_2_sram[0]:9 2.890693e-05 +10 mux_tree_tapbuf_size12_2_sram[0]:10 0.0001109938 +11 mux_tree_tapbuf_size12_2_sram[0]:11 0.0001109938 +12 mux_tree_tapbuf_size12_2_sram[0]:12 0.000158056 +13 mux_tree_tapbuf_size12_2_sram[0]:13 0.0001835784 +14 mux_tree_tapbuf_size12_2_sram[0]:14 0.0003003429 +15 mux_tree_tapbuf_size12_2_sram[0]:15 0.0002748205 +16 mux_tree_tapbuf_size12_2_sram[0]:16 0.0005137539 +17 mux_tree_tapbuf_size12_2_sram[0]:17 0.0001232241 +18 mux_tree_tapbuf_size12_2_sram[0]:18 0.0001232241 +19 mux_tree_tapbuf_size12_2_sram[0]:19 0.0006211523 +20 mux_tree_tapbuf_size12_2_sram[0]:20 7.672373e-05 +21 mux_tree_tapbuf_size12_2_sram[0]:21 0.0005788882 +22 mux_tree_tapbuf_size12_2_sram[0]:22 0.0005788882 +23 mux_tree_tapbuf_size12_2_sram[0]:23 0.0002836311 +24 mux_tree_tapbuf_size12_2_sram[0]:24 0.0004238973 +25 mux_tree_tapbuf_size12_2_sram[0]:25 5.420493e-05 +26 mux_tree_tapbuf_size12_2_sram[0]:26 0.0002079411 +27 mux_tree_tapbuf_size12_2_sram[0]:27 0.000211469 +28 mux_tree_tapbuf_size12_2_sram[0]:28 0.0004542233 +29 mux_tree_tapbuf_size12_2_sram[0]:29 0.000620565 +30 mux_tree_tapbuf_size12_2_sram[0]:30 0.0004694169 +31 mux_tree_tapbuf_size12_2_sram[0]:31 0.0001439082 +32 mux_tree_tapbuf_size12_2_sram[0]:32 9.687342e-05 +33 mux_tree_tapbuf_size12_2_sram[0]:33 9.687342e-05 +34 mux_tree_tapbuf_size12_2_sram[0]:34 0.0001492235 +35 mux_tree_tapbuf_size12_2_sram[0]:35 0.0002084757 +36 mux_tree_tapbuf_size12_2_sram[0]:36 0.0001762395 +37 mux_tree_tapbuf_size12_2_sram[0]:37 9.034891e-05 +38 mux_tree_tapbuf_size12_2_sram[0]:38 9.034891e-05 +39 mux_tree_tapbuf_size12_2_sram[0]:15 chanx_right_in[12]:15 2.869147e-05 +40 mux_tree_tapbuf_size12_2_sram[0]:16 chanx_right_in[12]:16 0.0001430122 +41 mux_tree_tapbuf_size12_2_sram[0]:16 chanx_right_in[12]:21 0.0002751062 +42 mux_tree_tapbuf_size12_2_sram[0]:16 chanx_right_in[12]:28 1.825705e-05 +43 mux_tree_tapbuf_size12_2_sram[0]:19 chanx_right_in[12]:21 0.0001430122 +44 mux_tree_tapbuf_size12_2_sram[0]:19 chanx_right_in[12]:22 0.0002751062 +45 mux_tree_tapbuf_size12_2_sram[0]:19 chanx_right_in[12]:29 1.825705e-05 +46 mux_tree_tapbuf_size12_2_sram[0]:14 chanx_right_in[12]:16 2.869147e-05 +47 mux_tree_tapbuf_size12_2_sram[0]:28 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001652213 +48 mux_tree_tapbuf_size12_2_sram[0]:24 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001652213 +49 mux_tree_tapbuf_size12_2_sram[0]:20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.893835e-05 +50 mux_tree_tapbuf_size12_2_sram[0]:16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004995829 +51 mux_tree_tapbuf_size12_2_sram[0]:19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.893835e-05 +52 mux_tree_tapbuf_size12_2_sram[0]:19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004995829 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_2_sram[0]:38 0.152 +1 mux_tree_tapbuf_size12_2_sram[0]:22 mux_tree_tapbuf_size12_2_sram[0]:21 0.008544643 +2 mux_tree_tapbuf_size12_2_sram[0]:23 mux_tree_tapbuf_size12_2_sram[0]:22 0.0045 +3 mux_tree_tapbuf_size12_2_sram[0]:23 mux_tree_tapbuf_size12_2_sram[0]:8 0.00178125 +4 mux_tree_tapbuf_size12_2_sram[0]:21 mux_tree_tapbuf_size12_2_sram[0]:20 0.0045 +5 mux_tree_tapbuf_size12_2_sram[0]:20 mux_tree_tapbuf_size12_2_sram[0]:19 0.00178125 +6 mux_tree_tapbuf_size12_2_sram[0]:28 mux_tree_tapbuf_size12_2_sram[0]:27 0.0003035714 +7 mux_tree_tapbuf_size12_2_sram[0]:28 mux_tree_tapbuf_size12_2_sram[0]:24 0.007448661 +8 mux_tree_tapbuf_size12_2_sram[0]:29 mux_tree_tapbuf_size12_2_sram[0]:28 0.0045 +9 mux_tree_tapbuf_size12_2_sram[0]:29 mux_tree_tapbuf_size12_2_sram[0]:23 0.002428571 +10 mux_tree_tapbuf_size12_2_sram[0]:7 mux_right_track_0\/mux_l1_in_3_:S 0.152 +11 mux_tree_tapbuf_size12_2_sram[0]:8 mux_tree_tapbuf_size12_2_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size12_2_sram[0]:33 mux_tree_tapbuf_size12_2_sram[0]:32 0.001002232 +13 mux_tree_tapbuf_size12_2_sram[0]:34 mux_tree_tapbuf_size12_2_sram[0]:33 0.0045 +14 mux_tree_tapbuf_size12_2_sram[0]:34 mux_tree_tapbuf_size12_2_sram[0]:31 0.001821429 +15 mux_tree_tapbuf_size12_2_sram[0]:32 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size12_2_sram[0]:37 mux_tree_tapbuf_size12_2_sram[0]:36 0.0045 +17 mux_tree_tapbuf_size12_2_sram[0]:36 mux_tree_tapbuf_size12_2_sram[0]:35 0.002691964 +18 mux_tree_tapbuf_size12_2_sram[0]:38 mux_tree_tapbuf_size12_2_sram[0]:37 0.001020089 +19 mux_tree_tapbuf_size12_2_sram[0]:15 mux_tree_tapbuf_size12_2_sram[0]:14 0.003245536 +20 mux_tree_tapbuf_size12_2_sram[0]:16 mux_tree_tapbuf_size12_2_sram[0]:15 0.0045 +21 mux_tree_tapbuf_size12_2_sram[0]:12 mux_tree_tapbuf_size12_2_sram[0]:11 0.0045 +22 mux_tree_tapbuf_size12_2_sram[0]:11 mux_tree_tapbuf_size12_2_sram[0]:10 0.0014375 +23 mux_tree_tapbuf_size12_2_sram[0]:9 mux_right_track_0\/mux_l1_in_4_:S 0.152 +24 mux_tree_tapbuf_size12_2_sram[0]:10 mux_tree_tapbuf_size12_2_sram[0]:9 0.0045 +25 mux_tree_tapbuf_size12_2_sram[0]:24 mux_right_track_0\/mux_l1_in_2_:S 0.152 +26 mux_tree_tapbuf_size12_2_sram[0]:25 mux_right_track_0\/mux_l1_in_1_:S 0.152 +27 mux_tree_tapbuf_size12_2_sram[0]:18 mux_tree_tapbuf_size12_2_sram[0]:17 0.001247768 +28 mux_tree_tapbuf_size12_2_sram[0]:19 mux_tree_tapbuf_size12_2_sram[0]:18 0.0045 +29 mux_tree_tapbuf_size12_2_sram[0]:19 mux_tree_tapbuf_size12_2_sram[0]:16 0.01756697 +30 mux_tree_tapbuf_size12_2_sram[0]:17 mux_right_track_0\/mux_l1_in_0_:S 0.152 +31 mux_tree_tapbuf_size12_2_sram[0]:13 mux_tree_tapbuf_size12_2_sram[0]:12 0.001602679 +32 mux_tree_tapbuf_size12_2_sram[0]:14 mux_tree_tapbuf_size12_2_sram[0]:13 0.0003035715 +33 mux_tree_tapbuf_size12_2_sram[0]:26 mux_tree_tapbuf_size12_2_sram[0]:25 0.0003035715 +34 mux_tree_tapbuf_size12_2_sram[0]:27 mux_tree_tapbuf_size12_2_sram[0]:26 0.002053572 +35 mux_tree_tapbuf_size12_2_sram[0]:31 mux_tree_tapbuf_size12_2_sram[0]:30 0.0004107143 +36 mux_tree_tapbuf_size12_2_sram[0]:30 mux_tree_tapbuf_size12_2_sram[0]:29 0.007589286 +37 mux_tree_tapbuf_size12_2_sram[0]:35 mux_tree_tapbuf_size12_2_sram[0]:34 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size12_6_sram[3] 0.002571212 //LENGTH 18.740 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 30.665 85.680 +*I mux_left_track_1\/mux_l4_in_0_:S I *L 0.00357 *C 23.120 83.640 +*I mem_left_track_1\/FTB_7__58:A I *L 0.001746 *C 27.140 91.120 +*N mux_tree_tapbuf_size12_6_sram[3]:3 *C 27.178 91.120 +*N mux_tree_tapbuf_size12_6_sram[3]:4 *C 28.015 91.120 +*N mux_tree_tapbuf_size12_6_sram[3]:5 *C 28.060 91.075 +*N mux_tree_tapbuf_size12_6_sram[3]:6 *C 23.158 83.640 +*N mux_tree_tapbuf_size12_6_sram[3]:7 *C 28.015 83.640 +*N mux_tree_tapbuf_size12_6_sram[3]:8 *C 28.060 83.685 +*N mux_tree_tapbuf_size12_6_sram[3]:9 *C 28.060 85.680 +*N mux_tree_tapbuf_size12_6_sram[3]:10 *C 28.068 85.680 +*N mux_tree_tapbuf_size12_6_sram[3]:11 *C 31.273 85.680 +*N mux_tree_tapbuf_size12_6_sram[3]:12 *C 31.280 85.680 +*N mux_tree_tapbuf_size12_6_sram[3]:13 *C 31.235 85.680 +*N mux_tree_tapbuf_size12_6_sram[3]:14 *C 30.703 85.680 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:S 1e-06 +2 mem_left_track_1\/FTB_7__58:A 1e-06 +3 mux_tree_tapbuf_size12_6_sram[3]:3 9.390464e-05 +4 mux_tree_tapbuf_size12_6_sram[3]:4 9.390464e-05 +5 mux_tree_tapbuf_size12_6_sram[3]:5 0.0003125973 +6 mux_tree_tapbuf_size12_6_sram[3]:6 0.0003833265 +7 mux_tree_tapbuf_size12_6_sram[3]:7 0.0003833265 +8 mux_tree_tapbuf_size12_6_sram[3]:8 0.0001249642 +9 mux_tree_tapbuf_size12_6_sram[3]:9 0.0004757456 +10 mux_tree_tapbuf_size12_6_sram[3]:10 0.0002506272 +11 mux_tree_tapbuf_size12_6_sram[3]:11 0.0002506272 +12 mux_tree_tapbuf_size12_6_sram[3]:12 3.797987e-05 +13 mux_tree_tapbuf_size12_6_sram[3]:13 8.060414e-05 +14 mux_tree_tapbuf_size12_6_sram[3]:14 8.060414e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_6_sram[3]:14 0.152 +1 mux_tree_tapbuf_size12_6_sram[3]:6 mux_left_track_1\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_6_sram[3]:7 mux_tree_tapbuf_size12_6_sram[3]:6 0.004337054 +3 mux_tree_tapbuf_size12_6_sram[3]:8 mux_tree_tapbuf_size12_6_sram[3]:7 0.0045 +4 mux_tree_tapbuf_size12_6_sram[3]:4 mux_tree_tapbuf_size12_6_sram[3]:3 0.0007477679 +5 mux_tree_tapbuf_size12_6_sram[3]:5 mux_tree_tapbuf_size12_6_sram[3]:4 0.0045 +6 mux_tree_tapbuf_size12_6_sram[3]:3 mem_left_track_1\/FTB_7__58:A 0.152 +7 mux_tree_tapbuf_size12_6_sram[3]:9 mux_tree_tapbuf_size12_6_sram[3]:8 0.00178125 +8 mux_tree_tapbuf_size12_6_sram[3]:9 mux_tree_tapbuf_size12_6_sram[3]:5 0.004816964 +9 mux_tree_tapbuf_size12_6_sram[3]:10 mux_tree_tapbuf_size12_6_sram[3]:9 0.00341 +10 mux_tree_tapbuf_size12_6_sram[3]:12 mux_tree_tapbuf_size12_6_sram[3]:11 0.00341 +11 mux_tree_tapbuf_size12_6_sram[3]:11 mux_tree_tapbuf_size12_6_sram[3]:10 0.0005021166 +12 mux_tree_tapbuf_size12_6_sram[3]:13 mux_tree_tapbuf_size12_6_sram[3]:12 0.0045 +13 mux_tree_tapbuf_size12_6_sram[3]:14 mux_tree_tapbuf_size12_6_sram[3]:13 0.0004754465 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_3_ccff_tail[0] 0.0004452553 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mem_right_track_2\/FTB_4__55:X O *L 0 *C 121.665 93.160 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 122.075 91.460 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:2 *C 122.075 91.460 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:3 *C 121.900 91.460 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:4 *C 121.900 91.505 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:5 *C 121.900 93.115 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:6 *C 121.900 93.160 +*N mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:7 *C 121.665 93.160 + +*CAP +0 mem_right_track_2\/FTB_4__55:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:2 4.911179e-05 +3 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:3 5.471109e-05 +4 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:4 0.0001147291 +5 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:5 0.0001147291 +6 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:6 5.61904e-05 +7 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:7 5.378369e-05 + +*RES +0 mem_right_track_2\/FTB_4__55:X mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size12_mem_3_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size16_1_sram[0] 0.0130324 //LENGTH 72.955 LUMPCC 0.006104787 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 127.725 91.120 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 67.980 88.400 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 126.220 86.020 +*N mux_tree_tapbuf_size16_1_sram[0]:3 *C 126.243 86.047 +*N mux_tree_tapbuf_size16_1_sram[0]:4 *C 126.255 86.360 +*N mux_tree_tapbuf_size16_1_sram[0]:5 *C 126.915 86.360 +*N mux_tree_tapbuf_size16_1_sram[0]:6 *C 126.960 86.405 +*N mux_tree_tapbuf_size16_1_sram[0]:7 *C 67.943 88.400 +*N mux_tree_tapbuf_size16_1_sram[0]:8 *C 67.620 88.400 +*N mux_tree_tapbuf_size16_1_sram[0]:9 *C 67.620 88.060 +*N mux_tree_tapbuf_size16_1_sram[0]:10 *C 68.080 88.060 +*N mux_tree_tapbuf_size16_1_sram[0]:11 *C 68.080 87.720 +*N mux_tree_tapbuf_size16_1_sram[0]:12 *C 71.715 87.720 +*N mux_tree_tapbuf_size16_1_sram[0]:13 *C 71.760 87.765 +*N mux_tree_tapbuf_size16_1_sram[0]:14 *C 71.760 89.035 +*N mux_tree_tapbuf_size16_1_sram[0]:15 *C 71.805 89.080 +*N mux_tree_tapbuf_size16_1_sram[0]:16 *C 78.155 89.080 +*N mux_tree_tapbuf_size16_1_sram[0]:17 *C 78.200 89.035 +*N mux_tree_tapbuf_size16_1_sram[0]:18 *C 78.200 87.778 +*N mux_tree_tapbuf_size16_1_sram[0]:19 *C 78.208 87.720 +*N mux_tree_tapbuf_size16_1_sram[0]:20 *C 126.953 87.720 +*N mux_tree_tapbuf_size16_1_sram[0]:21 *C 126.960 87.720 +*N mux_tree_tapbuf_size16_1_sram[0]:22 *C 126.960 91.075 +*N mux_tree_tapbuf_size16_1_sram[0]:23 *C 127.005 91.120 +*N mux_tree_tapbuf_size16_1_sram[0]:24 *C 127.688 91.120 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size16_1_sram[0]:3 3.417766e-05 +4 mux_tree_tapbuf_size16_1_sram[0]:4 9.695886e-05 +5 mux_tree_tapbuf_size16_1_sram[0]:5 6.27812e-05 +6 mux_tree_tapbuf_size16_1_sram[0]:6 6.265956e-05 +7 mux_tree_tapbuf_size16_1_sram[0]:7 4.891076e-05 +8 mux_tree_tapbuf_size16_1_sram[0]:8 7.398591e-05 +9 mux_tree_tapbuf_size16_1_sram[0]:9 5.183829e-05 +10 mux_tree_tapbuf_size16_1_sram[0]:10 5.578643e-05 +11 mux_tree_tapbuf_size16_1_sram[0]:11 0.0002564428 +12 mux_tree_tapbuf_size16_1_sram[0]:12 0.0002274195 +13 mux_tree_tapbuf_size16_1_sram[0]:13 0.0001184368 +14 mux_tree_tapbuf_size16_1_sram[0]:14 0.0001184368 +15 mux_tree_tapbuf_size16_1_sram[0]:15 0.0005038865 +16 mux_tree_tapbuf_size16_1_sram[0]:16 0.0005038865 +17 mux_tree_tapbuf_size16_1_sram[0]:17 0.0001126426 +18 mux_tree_tapbuf_size16_1_sram[0]:18 0.0001126426 +19 mux_tree_tapbuf_size16_1_sram[0]:19 0.001961153 +20 mux_tree_tapbuf_size16_1_sram[0]:20 0.001961153 +21 mux_tree_tapbuf_size16_1_sram[0]:21 0.0002668792 +22 mux_tree_tapbuf_size16_1_sram[0]:22 0.000169097 +23 mux_tree_tapbuf_size16_1_sram[0]:23 6.271887e-05 +24 mux_tree_tapbuf_size16_1_sram[0]:24 6.271887e-05 +25 mux_tree_tapbuf_size16_1_sram[0]:20 chanx_left_in[13]:16 0.0005178457 +26 mux_tree_tapbuf_size16_1_sram[0]:20 chanx_left_in[13]:17 0.001519533 +27 mux_tree_tapbuf_size16_1_sram[0]:19 chanx_left_in[13]:17 0.0005178457 +28 mux_tree_tapbuf_size16_1_sram[0]:19 chanx_left_in[13]:22 0.001519533 +29 mux_tree_tapbuf_size16_1_sram[0]:6 prog_clk[0]:153 1.815109e-05 +30 mux_tree_tapbuf_size16_1_sram[0]:21 prog_clk[0]:152 1.815109e-05 +31 mux_tree_tapbuf_size16_1_sram[0]:21 prog_clk[0]:153 1.003087e-05 +32 mux_tree_tapbuf_size16_1_sram[0]:20 prog_clk[0]:147 1.100479e-06 +33 mux_tree_tapbuf_size16_1_sram[0]:20 prog_clk[0]:154 1.225785e-05 +34 mux_tree_tapbuf_size16_1_sram[0]:20 prog_clk[0]:158 7.453733e-05 +35 mux_tree_tapbuf_size16_1_sram[0]:20 prog_clk[0]:259 0.0001449629 +36 mux_tree_tapbuf_size16_1_sram[0]:19 prog_clk[0]:148 1.100479e-06 +37 mux_tree_tapbuf_size16_1_sram[0]:19 prog_clk[0]:158 1.225785e-05 +38 mux_tree_tapbuf_size16_1_sram[0]:19 prog_clk[0]:159 7.453733e-05 +39 mux_tree_tapbuf_size16_1_sram[0]:19 prog_clk[0]:260 0.0001449629 +40 mux_tree_tapbuf_size16_1_sram[0]:22 prog_clk[0]:152 1.003087e-05 +41 mux_tree_tapbuf_size16_1_sram[0]:6 right_top_grid_pin_48_[0]:20 4.07492e-07 +42 mux_tree_tapbuf_size16_1_sram[0]:21 right_top_grid_pin_48_[0]:20 6.013627e-06 +43 mux_tree_tapbuf_size16_1_sram[0]:21 right_top_grid_pin_48_[0]:21 4.07492e-07 +44 mux_tree_tapbuf_size16_1_sram[0]:20 right_top_grid_pin_48_[0]:12 0.0004708981 +45 mux_tree_tapbuf_size16_1_sram[0]:20 right_top_grid_pin_48_[0]:19 6.262031e-06 +46 mux_tree_tapbuf_size16_1_sram[0]:19 right_top_grid_pin_48_[0]:11 0.0004708981 +47 mux_tree_tapbuf_size16_1_sram[0]:19 right_top_grid_pin_48_[0]:18 6.262031e-06 +48 mux_tree_tapbuf_size16_1_sram[0]:22 right_top_grid_pin_48_[0]:21 6.013627e-06 +49 mux_tree_tapbuf_size16_1_sram[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 1.403792e-06 +50 mux_tree_tapbuf_size16_1_sram[0]:21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 1.403792e-06 +51 mux_tree_tapbuf_size16_1_sram[0]:20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0002022177 +52 mux_tree_tapbuf_size16_1_sram[0]:19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0002022177 +53 mux_tree_tapbuf_size16_1_sram[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.677155e-05 +54 mux_tree_tapbuf_size16_1_sram[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.677155e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size16_1_sram[0]:24 0.152 +1 mux_tree_tapbuf_size16_1_sram[0]:5 mux_tree_tapbuf_size16_1_sram[0]:4 0.0005892857 +2 mux_tree_tapbuf_size16_1_sram[0]:6 mux_tree_tapbuf_size16_1_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size16_1_sram[0]:3 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size16_1_sram[0]:21 mux_tree_tapbuf_size16_1_sram[0]:20 0.00341 +5 mux_tree_tapbuf_size16_1_sram[0]:21 mux_tree_tapbuf_size16_1_sram[0]:6 0.001174107 +6 mux_tree_tapbuf_size16_1_sram[0]:20 mux_tree_tapbuf_size16_1_sram[0]:19 0.007636716 +7 mux_tree_tapbuf_size16_1_sram[0]:18 mux_tree_tapbuf_size16_1_sram[0]:17 0.001122768 +8 mux_tree_tapbuf_size16_1_sram[0]:19 mux_tree_tapbuf_size16_1_sram[0]:18 0.00341 +9 mux_tree_tapbuf_size16_1_sram[0]:16 mux_tree_tapbuf_size16_1_sram[0]:15 0.005669643 +10 mux_tree_tapbuf_size16_1_sram[0]:17 mux_tree_tapbuf_size16_1_sram[0]:16 0.0045 +11 mux_tree_tapbuf_size16_1_sram[0]:15 mux_tree_tapbuf_size16_1_sram[0]:14 0.0045 +12 mux_tree_tapbuf_size16_1_sram[0]:14 mux_tree_tapbuf_size16_1_sram[0]:13 0.001133929 +13 mux_tree_tapbuf_size16_1_sram[0]:12 mux_tree_tapbuf_size16_1_sram[0]:11 0.003245536 +14 mux_tree_tapbuf_size16_1_sram[0]:13 mux_tree_tapbuf_size16_1_sram[0]:12 0.0045 +15 mux_tree_tapbuf_size16_1_sram[0]:7 mux_right_track_4\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size16_1_sram[0]:23 mux_tree_tapbuf_size16_1_sram[0]:22 0.0045 +17 mux_tree_tapbuf_size16_1_sram[0]:22 mux_tree_tapbuf_size16_1_sram[0]:21 0.002995536 +18 mux_tree_tapbuf_size16_1_sram[0]:24 mux_tree_tapbuf_size16_1_sram[0]:23 0.000609375 +19 mux_tree_tapbuf_size16_1_sram[0]:9 mux_tree_tapbuf_size16_1_sram[0]:8 0.0003035715 +20 mux_tree_tapbuf_size16_1_sram[0]:10 mux_tree_tapbuf_size16_1_sram[0]:9 0.0004107143 +21 mux_tree_tapbuf_size16_1_sram[0]:8 mux_tree_tapbuf_size16_1_sram[0]:7 0.0002879465 +22 mux_tree_tapbuf_size16_1_sram[0]:11 mux_tree_tapbuf_size16_1_sram[0]:10 0.0003035715 +23 mux_tree_tapbuf_size16_1_sram[0]:4 mux_tree_tapbuf_size16_1_sram[0]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[0] 0.01201052 //LENGTH 89.430 LUMPCC 0.000641486 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.730 83.300 +*I mux_top_track_32\/mux_l1_in_1_:S I *L 0.00357 *C 83.820 53.040 +*I mux_top_track_32\/mux_l1_in_2_:S I *L 0.00357 *C 83.160 77.815 +*I mux_top_track_32\/mux_l1_in_3_:S I *L 0.00357 *C 86.120 79.560 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 66.875 107.780 +*I mux_top_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 61.540 107.440 +*N mux_tree_tapbuf_size7_0_sram[0]:6 *C 61.578 107.440 +*N mux_tree_tapbuf_size7_0_sram[0]:7 *C 62.100 107.440 +*N mux_tree_tapbuf_size7_0_sram[0]:8 *C 62.100 107.780 +*N mux_tree_tapbuf_size7_0_sram[0]:9 *C 66.838 107.780 +*N mux_tree_tapbuf_size7_0_sram[0]:10 *C 67.160 107.780 +*N mux_tree_tapbuf_size7_0_sram[0]:11 *C 67.160 107.735 +*N mux_tree_tapbuf_size7_0_sram[0]:12 *C 86.083 79.560 +*N mux_tree_tapbuf_size7_0_sram[0]:13 *C 83.160 77.815 +*N mux_tree_tapbuf_size7_0_sram[0]:14 *C 83.305 77.590 +*N mux_tree_tapbuf_size7_0_sram[0]:15 *C 83.190 77.450 +*N mux_tree_tapbuf_size7_0_sram[0]:16 *C 83.858 53.040 +*N mux_tree_tapbuf_size7_0_sram[0]:17 *C 85.055 53.040 +*N mux_tree_tapbuf_size7_0_sram[0]:18 *C 85.100 53.085 +*N mux_tree_tapbuf_size7_0_sram[0]:19 *C 85.100 77.135 +*N mux_tree_tapbuf_size7_0_sram[0]:20 *C 85.055 77.180 +*N mux_tree_tapbuf_size7_0_sram[0]:21 *C 83.260 77.180 +*N mux_tree_tapbuf_size7_0_sram[0]:22 *C 83.190 77.520 +*N mux_tree_tapbuf_size7_0_sram[0]:23 *C 83.103 77.520 +*N mux_tree_tapbuf_size7_0_sram[0]:24 *C 81.465 77.520 +*N mux_tree_tapbuf_size7_0_sram[0]:25 *C 81.420 77.565 +*N mux_tree_tapbuf_size7_0_sram[0]:26 *C 81.420 79.515 +*N mux_tree_tapbuf_size7_0_sram[0]:27 *C 81.420 79.560 +*N mux_tree_tapbuf_size7_0_sram[0]:28 *C 68.080 79.560 +*N mux_tree_tapbuf_size7_0_sram[0]:29 *C 68.080 79.900 +*N mux_tree_tapbuf_size7_0_sram[0]:30 *C 67.205 79.900 +*N mux_tree_tapbuf_size7_0_sram[0]:31 *C 67.160 79.945 +*N mux_tree_tapbuf_size7_0_sram[0]:32 *C 67.160 83.300 +*N mux_tree_tapbuf_size7_0_sram[0]:33 *C 67.205 83.300 +*N mux_tree_tapbuf_size7_0_sram[0]:34 *C 67.693 83.300 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_32\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:S 1e-06 +3 mux_top_track_32\/mux_l1_in_3_:S 1e-06 +4 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_top_track_32\/mux_l1_in_0_:S 1e-06 +6 mux_tree_tapbuf_size7_0_sram[0]:6 4.381192e-05 +7 mux_tree_tapbuf_size7_0_sram[0]:7 6.977934e-05 +8 mux_tree_tapbuf_size7_0_sram[0]:8 0.0003853301 +9 mux_tree_tapbuf_size7_0_sram[0]:9 0.0003821232 +10 mux_tree_tapbuf_size7_0_sram[0]:10 5.985786e-05 +11 mux_tree_tapbuf_size7_0_sram[0]:11 0.001477979 +12 mux_tree_tapbuf_size7_0_sram[0]:12 0.0003295474 +13 mux_tree_tapbuf_size7_0_sram[0]:13 6.243181e-05 +14 mux_tree_tapbuf_size7_0_sram[0]:14 1.39236e-05 +15 mux_tree_tapbuf_size7_0_sram[0]:15 4.419438e-05 +16 mux_tree_tapbuf_size7_0_sram[0]:16 9.936572e-05 +17 mux_tree_tapbuf_size7_0_sram[0]:17 9.936572e-05 +18 mux_tree_tapbuf_size7_0_sram[0]:18 0.001479169 +19 mux_tree_tapbuf_size7_0_sram[0]:19 0.001479169 +20 mux_tree_tapbuf_size7_0_sram[0]:20 0.0001390603 +21 mux_tree_tapbuf_size7_0_sram[0]:21 0.00016351 +22 mux_tree_tapbuf_size7_0_sram[0]:22 4.303605e-05 +23 mux_tree_tapbuf_size7_0_sram[0]:23 0.0001805097 +24 mux_tree_tapbuf_size7_0_sram[0]:24 0.0001610745 +25 mux_tree_tapbuf_size7_0_sram[0]:25 0.0001672178 +26 mux_tree_tapbuf_size7_0_sram[0]:26 0.0001672178 +27 mux_tree_tapbuf_size7_0_sram[0]:27 0.001171526 +28 mux_tree_tapbuf_size7_0_sram[0]:28 0.0008342764 +29 mux_tree_tapbuf_size7_0_sram[0]:29 0.0001162682 +30 mux_tree_tapbuf_size7_0_sram[0]:30 8.811481e-05 +31 mux_tree_tapbuf_size7_0_sram[0]:31 0.0002270083 +32 mux_tree_tapbuf_size7_0_sram[0]:32 0.001738586 +33 mux_tree_tapbuf_size7_0_sram[0]:33 6.97898e-05 +34 mux_tree_tapbuf_size7_0_sram[0]:34 6.97898e-05 +35 mux_tree_tapbuf_size7_0_sram[0]:27 chany_bottom_in[12]:19 2.528756e-05 +36 mux_tree_tapbuf_size7_0_sram[0]:27 chany_bottom_in[12]:20 0.0002359729 +37 mux_tree_tapbuf_size7_0_sram[0]:29 chany_bottom_in[12]:17 7.386698e-08 +38 mux_tree_tapbuf_size7_0_sram[0]:28 chany_bottom_in[12]:18 2.528756e-05 +39 mux_tree_tapbuf_size7_0_sram[0]:28 chany_bottom_in[12]:19 0.0002360467 +40 mux_tree_tapbuf_size7_0_sram[0]:32 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.940874e-05 +41 mux_tree_tapbuf_size7_0_sram[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.940874e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_0_sram[0]:34 0.152 +1 mux_tree_tapbuf_size7_0_sram[0]:34 mux_tree_tapbuf_size7_0_sram[0]:33 0.0004352679 +2 mux_tree_tapbuf_size7_0_sram[0]:33 mux_tree_tapbuf_size7_0_sram[0]:32 0.0045 +3 mux_tree_tapbuf_size7_0_sram[0]:32 mux_tree_tapbuf_size7_0_sram[0]:31 0.002995536 +4 mux_tree_tapbuf_size7_0_sram[0]:32 mux_tree_tapbuf_size7_0_sram[0]:11 0.02181697 +5 mux_tree_tapbuf_size7_0_sram[0]:10 mux_tree_tapbuf_size7_0_sram[0]:9 0.0001752718 +6 mux_tree_tapbuf_size7_0_sram[0]:11 mux_tree_tapbuf_size7_0_sram[0]:10 0.0045 +7 mux_tree_tapbuf_size7_0_sram[0]:20 mux_tree_tapbuf_size7_0_sram[0]:19 0.0045 +8 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:18 0.02147322 +9 mux_tree_tapbuf_size7_0_sram[0]:17 mux_tree_tapbuf_size7_0_sram[0]:16 0.001069196 +10 mux_tree_tapbuf_size7_0_sram[0]:18 mux_tree_tapbuf_size7_0_sram[0]:17 0.0045 +11 mux_tree_tapbuf_size7_0_sram[0]:16 mux_top_track_32\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size7_0_sram[0]:30 mux_tree_tapbuf_size7_0_sram[0]:29 0.00078125 +13 mux_tree_tapbuf_size7_0_sram[0]:31 mux_tree_tapbuf_size7_0_sram[0]:30 0.0045 +14 mux_tree_tapbuf_size7_0_sram[0]:13 mux_top_track_32\/mux_l1_in_2_:S 0.152 +15 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:26 0.0045 +16 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:12 0.004162947 +17 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:25 0.001741072 +18 mux_tree_tapbuf_size7_0_sram[0]:24 mux_tree_tapbuf_size7_0_sram[0]:23 0.001462053 +19 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_0_sram[0]:24 0.0045 +20 mux_tree_tapbuf_size7_0_sram[0]:6 mux_top_track_32\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size7_0_sram[0]:9 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:8 0.004229911 +23 mux_tree_tapbuf_size7_0_sram[0]:12 mux_top_track_32\/mux_l1_in_3_:S 0.152 +24 mux_tree_tapbuf_size7_0_sram[0]:7 mux_tree_tapbuf_size7_0_sram[0]:6 0.0004665179 +25 mux_tree_tapbuf_size7_0_sram[0]:8 mux_tree_tapbuf_size7_0_sram[0]:7 0.0003035714 +26 mux_tree_tapbuf_size7_0_sram[0]:29 mux_tree_tapbuf_size7_0_sram[0]:28 0.0003035715 +27 mux_tree_tapbuf_size7_0_sram[0]:28 mux_tree_tapbuf_size7_0_sram[0]:27 0.01191071 +28 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:22 7.8125e-05 +29 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:15 3.017242e-05 +30 mux_tree_tapbuf_size7_0_sram[0]:22 mux_tree_tapbuf_size7_0_sram[0]:21 0.0003035715 +31 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:14 0.0001026786 +32 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:13 0.0001573276 +33 mux_tree_tapbuf_size7_0_sram[0]:21 mux_tree_tapbuf_size7_0_sram[0]:20 0.001602678 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001618851 //LENGTH 11.635 LUMPCC 0.0006253977 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 70.205 117.640 +*I mux_top_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 76.000 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 75.963 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 70.425 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 70.380 112.585 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 70.380 117.595 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 70.380 117.640 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 70.205 117.640 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002554584 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002554584 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001825218 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001825218 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.00463e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.544685e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[16]:30 5.909715e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[16] 5.909715e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[12]:14 6.668604e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[12]:11 6.668604e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size12_0_sram[3]:5 0.0001869157 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size12_0_sram[3]:4 0.0001869157 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.004944196 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004473215 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00103308 //LENGTH 7.555 LUMPCC 0.0001680303 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_1_:X O *L 0 *C 59.975 95.880 +*I mux_top_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 56.410 98.940 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 56.448 98.940 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 57.455 98.940 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 57.500 98.895 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 57.500 95.925 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 57.545 95.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 59.938 95.880 + +*CAP +0 mux_top_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.246667e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.246667e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001387356 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001387356 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002103224 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002103224 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:20 8.401516e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size10_2_sram[0]:21 8.401516e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0008995537 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002651786 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002136161 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005713 //LENGTH 3.280 LUMPCC 8.447751e-05 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_1_:X O *L 0 *C 98.265 105.400 +*I mux_right_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 98.615 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 98.615 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 98.440 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 98.440 107.735 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 98.440 105.445 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 98.440 105.400 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 98.265 105.400 + +*CAP +0 mux_right_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.749122e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.245594e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001282179 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001282179 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.74778e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.096168e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.768464e-08 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.768464e-08 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.217107e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.217107e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002044643 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008071784 //LENGTH 5.300 LUMPCC 0.0001534497 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_3_:X O *L 0 *C 118.505 88.740 +*I mux_right_track_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 117.015 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 117.053 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 118.635 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 118.680 91.415 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 118.680 88.785 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 118.680 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 118.505 88.740 + +*CAP +0 mux_right_track_2\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001437633 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001437633 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001288331 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001288331 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.424913e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.228676e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:143 1.257207e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:149 6.415276e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:149 1.257207e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:160 6.415276e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_3_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_2\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001412946 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002348214 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007941645 //LENGTH 6.140 LUMPCC 0.0002593362 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_0_:X O *L 0 *C 69.175 27.880 +*I mux_bottom_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 67.985 23.460 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 67.985 23.460 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.080 23.505 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 68.080 27.835 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 68.125 27.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 69.138 27.880 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.916212e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001563942 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001563942 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.543888e-05 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.543888e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[8]:13 0.0001296681 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[8]:10 0.0001296681 + +*RES +0 mux_bottom_track_3\/mux_l1_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0009040179 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001659585 //LENGTH 12.350 LUMPCC 0.000595094 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_0_:X O *L 0 *C 62.735 19.720 +*I mux_bottom_track_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 63.940 9.180 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 63.940 9.180 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 63.940 9.225 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 63.940 14.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 63.020 14.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 63.020 19.675 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 63.020 19.720 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 62.735 19.720 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.555123e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0002495651 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003022288 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002019278 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001492641 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.371341e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.024028e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 chany_bottom_out[8] 7.501284e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chany_bottom_out[8]:2 7.501284e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size12_5_sram[2]:11 5.456927e-06 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_5_sram[2]:5 4.7719e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_5_sram[2]:12 9.266714e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_5_sram[2]:15 7.669109e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_5_sram[2]:11 9.266714e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_5_sram[2]:15 4.7719e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_5_sram[2]:16 7.669109e-05 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_5_sram[2]:12 5.456927e-06 + +*RES +0 mux_bottom_track_3\/mux_l3_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_3\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.004513393 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001548913 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0008214285 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.004816964 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009654366 //LENGTH 7.315 LUMPCC 0.0001258042 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_4_:X O *L 0 *C 21.335 94.520 +*I mux_left_track_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 22.640 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 22.603 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 22.080 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 22.080 99.280 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 21.665 99.280 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 21.620 99.235 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 21.620 94.565 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 21.620 94.520 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 21.335 94.520 + +*CAP +0 mux_left_track_3\/mux_l1_in_4_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_2_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.834319e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.206598e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.371556e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.999277e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00023789 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00023789 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.042191e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.731297e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 left_top_grid_pin_45_[0]:7 5.05826e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 left_top_grid_pin_45_[0]:22 1.231953e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 left_top_grid_pin_45_[0]:6 5.05826e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 left_top_grid_pin_45_[0]:21 1.231953e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_4_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_3\/mux_l2_in_2_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003705357 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.004169643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001548913 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004665179 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00064391 //LENGTH 3.970 LUMPCC 0.0002743089 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_3_:X O *L 0 *C 37.895 107.780 +*I mux_top_track_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 34.215 107.780 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 34.253 107.780 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 37.858 107.780 + +*CAP +0 mux_top_track_4\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001838006 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001838006 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 top_left_grid_pin_41_[0]:18 0.0001371544 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 top_left_grid_pin_41_[0]:17 0.0001371544 + +*RES +0 mux_top_track_4\/mux_l2_in_3_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.00321875 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0] 0.0008413669 //LENGTH 6.350 LUMPCC 0.000101718 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_3_:X O *L 0 *C 120.275 74.460 +*I mux_right_track_4\/mux_l4_in_1_:A0 I *L 0.001631 *C 119.350 69.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 119.350 69.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 119.600 69.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 119.600 69.745 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 119.600 74.415 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 119.645 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 120.238 74.460 + +*CAP +0 mux_right_track_4\/mux_l3_in_3_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_1_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 5.298361e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 5.60409e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0002467942 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0002467942 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 6.751803e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 6.751803e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 2.651461e-06 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 2.651461e-06 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 4.820752e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 4.820752e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_3_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_right_track_4\/mux_l4_in_1_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0001358696 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.004169643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0005290179 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0] 0.001917201 //LENGTH 17.225 LUMPCC 0.0002056145 DR + +*CONN +*I mux_bottom_track_5\/mux_l4_in_0_:X O *L 0 *C 43.065 25.840 +*I mux_bottom_track_5\/mux_l5_in_0_:A1 I *L 0.00198 *C 46.100 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 46.062 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 43.745 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 *C 43.700 12.625 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 *C 43.700 25.795 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 *C 43.655 25.840 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 *C 43.102 25.840 + +*CAP +0 mux_bottom_track_5\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l5_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0001339278 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0001339278 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0006564725 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0006564725 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 6.439303e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 6.439303e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 bottom_left_grid_pin_38_[0]:14 6.123858e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 bottom_left_grid_pin_38_[0]:13 6.123858e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 4.140911e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 4.140911e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 1.595745e-07 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 1.595745e-07 + +*RES +0 mux_bottom_track_5\/mux_l4_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_bottom_track_5\/mux_l5_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.002069197 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.01175893 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0] 0.001263114 //LENGTH 7.620 LUMPCC 0.0004262007 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_2_:X O *L 0 *C 20.415 89.080 +*I mux_left_track_5\/mux_l4_in_1_:A1 I *L 0.00198 *C 13.705 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 13.743 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 17.480 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 17.480 89.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 20.378 89.080 + +*CAP +0 mux_left_track_5\/mux_l3_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0001388786 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001645494 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.000278578 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002529072 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_tree_tapbuf_size16_3_sram[3]:8 0.0001084529 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_tree_tapbuf_size16_3_sram[3]:7 0.0001084529 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0001046475 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0001046475 + +*RES +0 mux_left_track_5\/mux_l3_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_left_track_5\/mux_l4_in_1_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.002587054 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.003337054 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.002508808 //LENGTH 18.660 LUMPCC 0.0007722453 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_0_:X O *L 0 *C 35.595 88.400 +*I mux_left_track_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 17.845 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 17.883 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 18.400 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 18.400 88.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 35.558 88.400 + +*CAP +0 mux_left_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.10957e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 9.642783e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0007961856 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0007708535 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size16_3_sram[2]:8 3.340816e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size16_3_sram[2]:9 1.906191e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size16_3_sram[2]:21 0.000129355 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size16_3_sram[2]:9 3.340816e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size16_3_sram[2]:20 0.000129355 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size16_3_sram[2]:21 1.906191e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 2.362792e-07 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0002040613 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 2.362792e-07 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0002040613 + +*RES +0 mux_left_track_5\/mux_l3_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_5\/mux_l4_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0153192 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004620536 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0003035714 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008307163 //LENGTH 6.120 LUMPCC 7.694496e-05 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_3_:X O *L 0 *C 47.095 48.280 +*I mux_top_track_16\/mux_l3_in_1_:A0 I *L 0.001631 *C 43.415 49.980 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 43.453 49.980 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 46.875 49.980 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 46.920 49.935 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 46.920 48.325 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 46.920 48.280 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 47.095 48.280 + +*CAP +0 mux_top_track_16\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002071067 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002071067 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001094578 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001094578 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.808088e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.056139e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chanx_left_in[8]:32 3.832188e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chanx_left_in[8]:31 3.832188e-05 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[8]:30 1.506074e-07 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[8]:29 1.506074e-07 + +*RES +0 mux_top_track_16\/mux_l2_in_3_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_16\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.003055804 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0014375 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.006034358 //LENGTH 35.435 LUMPCC 0.002340532 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 77.565 66.980 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 107.280 63.580 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 107.280 63.580 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 107.180 63.240 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 99.865 63.240 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 99.820 63.285 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 99.820 65.903 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 99.812 65.960 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 81.428 65.960 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 81.420 66.017 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 81.420 66.935 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 81.375 66.980 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 77.603 66.980 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.85423e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005192168 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004909872 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000160027 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000160027 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0009650681 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0009650681 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.650063e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 7.650063e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001099447 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001099447 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[18] 0.0007152003 +14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[18]:31 0.0007152003 +15 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chany_bottom_in[9]:16 0.0001269832 +16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 chany_bottom_in[9]:17 0.0001269832 +17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[18]:24 5.875731e-06 +18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[18]:25 5.875731e-06 +19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 chany_bottom_in[18]:24 0.0001491106 +20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 chany_bottom_in[18]:25 0.0001491106 +21 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[3]:22 3.754332e-06 +22 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[3]:23 3.754332e-06 +23 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[3]:24 0.0001693417 +24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[3]:25 0.0001693417 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00653125 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002337054 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00341 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.00341 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.002880316 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0045 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0008191965 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.003368304 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002790455 //LENGTH 15.085 LUMPCC 0.001228643 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 86.765 85.000 +*I mux_right_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 99.000 83.300 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 98.900 83.300 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 98.900 83.345 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 98.900 84.943 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 98.892 85.000 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 86.487 85.000 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 86.480 85.000 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 86.480 85.000 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 86.765 85.000 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.250857e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001108755 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001108755 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005727536 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005727536 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.632387e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 6.110865e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.261207e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[2]:15 2.858492e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[2]:22 7.871374e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[2]:21 7.871374e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[2]:22 2.858492e-05 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0005070228 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005070228 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.001426339 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00194345 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001548913 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0012078 //LENGTH 11.175 LUMPCC 0.0001037138 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_1_:X O *L 0 *C 101.025 27.880 +*I mux_bottom_track_9\/mux_l4_in_0_:A0 I *L 0.001631 *C 102.870 20.740 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 102.907 20.740 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 103.455 20.740 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 103.500 20.785 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 103.500 27.835 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 103.455 27.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 101.062 27.880 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.661328e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 3.661328e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0003220651 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0003220651 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001923648 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001923648 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_6_sram[3]:5 2.987487e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_6_sram[3]:6 2.987487e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[3]:7 1.833697e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_6_sram[3]:8 3.645044e-06 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[3]:4 3.645044e-06 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_6_sram[3]:8 1.833697e-05 + +*RES +0 mux_bottom_track_9\/mux_l3_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_9\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0004888393 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.006294643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.002136161 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006592392 //LENGTH 5.320 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_2_:X O *L 0 *C 52.615 45.560 +*I mux_bottom_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 48.205 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 48.242 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 48.760 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 48.760 45.560 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 52.578 45.560 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.136093e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.812857e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002872587 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000260491 + +*RES +0 mux_bottom_track_25\/mux_l1_in_2_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_25\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003408482 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004620536 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002517189 //LENGTH 16.095 LUMPCC 0.001320424 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_2_:X O *L 0 *C 65.035 72.080 +*I mux_left_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 49.680 72.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 49.680 72.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 49.680 72.080 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 64.998 72.080 + +*CAP +0 mux_left_track_9\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.193534e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000581544 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005512855 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[16]:10 0.000154759 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[16]:28 0.000154759 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[6]:18 7.351799e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[6]:17 7.351799e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_2_sram[2]:10 0.0001065225 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_2_sram[2]:12 2.563361e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_2_sram[2]:9 2.563361e-05 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_2_sram[2]:11 0.0001065225 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[0]:35 0.0001751771 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[0]:37 3.180488e-05 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[0]:39 7.136882e-05 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[0]:41 2.142812e-05 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_6_sram[0]:36 0.0001751771 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_6_sram[0]:38 3.180488e-05 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_6_sram[0]:40 7.136882e-05 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_6_sram[0]:42 2.142812e-05 + +*RES +0 mux_left_track_9\/mux_l1_in_2_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.01367634 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_9\/mux_l2_in_1_:A1 0.152 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003360881 //LENGTH 25.755 LUMPCC 0.0009012196 DR + +*CONN +*I mux_left_track_17\/mux_l4_in_0_:X O *L 0 *C 26.395 55.420 +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.945 47.795 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 9.945 47.795 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 9.945 48.280 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 17.895 48.280 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 17.940 48.325 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 17.940 49.935 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 17.985 49.980 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 25.715 49.980 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 25.760 50.025 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 25.760 55.375 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 25.805 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 26.358 55.420 + +*CAP +0 mux_left_track_17\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.085799e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0004876236 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0004481579 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 8.488471e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.488471e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002837573 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0002837573 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0002987907 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0002987907 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.807825e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:12 5.807825e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chanx_left_in[19]:19 2.272178e-05 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_left_in[19]:17 0.0001225689 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_left_in[19]:18 2.272178e-05 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[19]:16 0.0001225689 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[19]:14 2.058474e-06 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_left_in[19]:15 2.058474e-06 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.0001394041 +20 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0001394041 +21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 optlc_net_147:11 0.0001638565 +22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 optlc_net_147:12 0.0001638565 + +*RES +0 mux_left_track_17\/mux_l4_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.007098215 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0014375 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.006901786 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0045 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0045 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.004776786 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0004933036 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004330357 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008511327 //LENGTH 5.660 LUMPCC 0 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_3_:X O *L 0 *C 88.145 74.800 +*I mux_right_track_32\/mux_l2_in_1_:A0 I *L 0.001631 *C 88.495 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 88.495 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 88.320 70.040 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 88.320 70.085 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 88.320 74.755 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 88.320 74.800 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 88.145 74.800 + +*CAP +0 mux_right_track_32\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.8711e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.214868e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002953082 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002953082 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.799906e-05 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.965744e-05 + +*RES +0 mux_right_track_32\/mux_l1_in_3_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_32\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004169643 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005644207 //LENGTH 4.440 LUMPCC 0.0001034323 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_0_:X O *L 0 *C 19.955 33.660 +*I mux_bottom_track_33\/mux_l3_in_0_:A1 I *L 0.00198 *C 18.960 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 18.860 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 18.860 30.985 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 18.860 33.615 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 18.905 33.660 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 19.918 33.660 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.261221e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001309482 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001309482 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.223992e-05 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.223992e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.171616e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.171616e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_33\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002348214 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0009040179 + +*END + +*D_NET ropt_net_202 0.001068867 //LENGTH 6.430 LUMPCC 0.0006126687 DR + +*CONN +*I FTB_2__1:X O *L 0 *C 70.840 12.580 +*I ropt_mt_inst_843:A I *L 0.001766 *C 76.360 12.240 +*N ropt_net_202:2 *C 76.323 12.240 +*N ropt_net_202:3 *C 72.220 12.240 +*N ropt_net_202:4 *C 72.220 12.580 +*N ropt_net_202:5 *C 70.877 12.580 + +*CAP +0 FTB_2__1:X 1e-06 +1 ropt_mt_inst_843:A 1e-06 +2 ropt_net_202:2 0.0001430726 +3 ropt_net_202:3 0.0001667975 +4 ropt_net_202:4 8.402643e-05 +5 ropt_net_202:5 6.030154e-05 +6 ropt_net_202:2 chany_top_in[6]:7 1.883703e-05 +7 ropt_net_202:5 chany_top_in[6]:6 5.400496e-05 +8 ropt_net_202:4 chany_top_in[6]:7 5.400496e-05 +9 ropt_net_202:3 chany_top_in[6]:6 1.883703e-05 +10 ropt_net_202:2 ropt_net_236:5 0.0001596102 +11 ropt_net_202:5 ropt_net_236:4 2.006115e-06 +12 ropt_net_202:5 ropt_net_236:3 2.474783e-05 +13 ropt_net_202:4 ropt_net_236:2 2.474783e-05 +14 ropt_net_202:4 ropt_net_236:5 2.006115e-06 +15 ropt_net_202:4 ropt_net_236:3 1.582178e-06 +16 ropt_net_202:3 ropt_net_236:4 0.0001611924 +17 ropt_net_202:2 chany_bottom_out[5]:7 4.554602e-05 +18 ropt_net_202:3 chany_bottom_out[5]:8 4.554602e-05 + +*RES +0 FTB_2__1:X ropt_net_202:5 0.152 +1 ropt_net_202:2 ropt_mt_inst_843:A 0.152 +2 ropt_net_202:5 ropt_net_202:4 0.001198661 +3 ropt_net_202:4 ropt_net_202:3 0.0003035715 +4 ropt_net_202:3 ropt_net_202:2 0.003662947 + +*END + +*D_NET ropt_net_183 0.002078168 //LENGTH 17.210 LUMPCC 0.0006192449 DR + +*CONN +*I FTB_20__19:X O *L 0 *C 10.580 90.780 +*I ropt_mt_inst_822:A I *L 0.001766 *C 3.220 99.280 +*N ropt_net_183:2 *C 3.243 99.252 +*N ropt_net_183:3 *C 3.255 98.940 +*N ropt_net_183:4 *C 3.635 98.940 +*N ropt_net_183:5 *C 3.680 98.895 +*N ropt_net_183:6 *C 3.680 91.165 +*N ropt_net_183:7 *C 3.725 91.120 +*N ropt_net_183:8 *C 9.200 91.120 +*N ropt_net_183:9 *C 9.200 90.780 +*N ropt_net_183:10 *C 10.543 90.780 + +*CAP +0 FTB_20__19:X 1e-06 +1 ropt_mt_inst_822:A 1e-06 +2 ropt_net_183:2 3.062905e-05 +3 ropt_net_183:3 6.78923e-05 +4 ropt_net_183:4 3.726326e-05 +5 ropt_net_183:5 0.0003629175 +6 ropt_net_183:6 0.0003629175 +7 ropt_net_183:7 0.0001819587 +8 ropt_net_183:8 0.0002060138 +9 ropt_net_183:9 0.0001156929 +10 ropt_net_183:10 9.163786e-05 +11 ropt_net_183:5 left_top_grid_pin_46_[0] 3.938094e-06 +12 ropt_net_183:5 left_top_grid_pin_46_[0]:20 3.897127e-06 +13 ropt_net_183:7 left_top_grid_pin_46_[0]:18 0.0001007718 +14 ropt_net_183:6 left_top_grid_pin_46_[0]:19 3.897127e-06 +15 ropt_net_183:6 left_top_grid_pin_46_[0]:21 3.938094e-06 +16 ropt_net_183:10 left_top_grid_pin_46_[0]:17 8.067064e-06 +17 ropt_net_183:8 left_top_grid_pin_46_[0]:17 0.0001007718 +18 ropt_net_183:9 left_top_grid_pin_46_[0]:18 8.067064e-06 +19 ropt_net_183:5 chanx_left_out[1]:4 0.0001279106 +20 ropt_net_183:6 chanx_left_out[1]:3 0.0001279106 +21 ropt_net_183:7 chanx_left_out[19]:5 6.503781e-05 +22 ropt_net_183:8 chanx_left_out[19]:6 6.503781e-05 + +*RES +0 FTB_20__19:X ropt_net_183:10 0.152 +1 ropt_net_183:2 ropt_mt_inst_822:A 0.152 +2 ropt_net_183:4 ropt_net_183:3 0.0003392857 +3 ropt_net_183:5 ropt_net_183:4 0.0045 +4 ropt_net_183:7 ropt_net_183:6 0.0045 +5 ropt_net_183:6 ropt_net_183:5 0.006901786 +6 ropt_net_183:10 ropt_net_183:9 0.001198661 +7 ropt_net_183:3 ropt_net_183:2 0.0002111487 +8 ropt_net_183:8 ropt_net_183:7 0.004888393 +9 ropt_net_183:9 ropt_net_183:8 0.0003035715 + +*END + +*D_NET ropt_net_243 0.0004203431 //LENGTH 3.125 LUMPCC 0.0001297471 DR + +*CONN +*I ropt_mt_inst_805:X O *L 0 *C 94.760 4.760 +*I ropt_mt_inst_897:A I *L 0.001766 *C 94.300 6.800 +*N ropt_net_243:2 *C 94.300 6.800 +*N ropt_net_243:3 *C 94.300 6.755 +*N ropt_net_243:4 *C 94.300 4.805 +*N ropt_net_243:5 *C 94.345 4.760 +*N ropt_net_243:6 *C 94.723 4.760 + +*CAP +0 ropt_mt_inst_805:X 1e-06 +1 ropt_mt_inst_897:A 1e-06 +2 ropt_net_243:2 3.199141e-05 +3 ropt_net_243:3 8.134179e-05 +4 ropt_net_243:4 8.134179e-05 +5 ropt_net_243:5 4.696047e-05 +6 ropt_net_243:6 4.696047e-05 +7 ropt_net_243:3 chany_bottom_in[6]:27 6.487355e-05 +8 ropt_net_243:4 chany_bottom_in[6]:28 6.487355e-05 + +*RES +0 ropt_mt_inst_805:X ropt_net_243:6 0.152 +1 ropt_net_243:2 ropt_mt_inst_897:A 0.152 +2 ropt_net_243:3 ropt_net_243:2 0.0045 +3 ropt_net_243:5 ropt_net_243:4 0.0045 +4 ropt_net_243:4 ropt_net_243:3 0.001741072 +5 ropt_net_243:6 ropt_net_243:5 0.0003370536 + +*END + +*D_NET ropt_net_237 0.0008679791 //LENGTH 6.335 LUMPCC 0.0002430083 DR + +*CONN +*I ropt_mt_inst_809:X O *L 0 *C 60.985 7.140 +*I ropt_mt_inst_885:A I *L 0.001767 *C 57.960 9.520 +*N ropt_net_237:2 *C 57.998 9.520 +*N ropt_net_237:3 *C 58.375 9.520 +*N ropt_net_237:4 *C 58.420 9.475 +*N ropt_net_237:5 *C 58.420 7.185 +*N ropt_net_237:6 *C 58.465 7.140 +*N ropt_net_237:7 *C 60.948 7.140 + +*CAP +0 ropt_mt_inst_809:X 1e-06 +1 ropt_mt_inst_885:A 1e-06 +2 ropt_net_237:2 4.524213e-05 +3 ropt_net_237:3 4.524213e-05 +4 ropt_net_237:4 0.000148217 +5 ropt_net_237:5 0.000148217 +6 ropt_net_237:6 0.0001180263 +7 ropt_net_237:7 0.0001180263 +8 ropt_net_237:7 ropt_net_171:7 0.0001043349 +9 ropt_net_237:6 ropt_net_171:6 0.0001043349 +10 ropt_net_237:5 ropt_net_171:4 1.716923e-05 +11 ropt_net_237:4 ropt_net_171:5 1.716923e-05 + +*RES +0 ropt_mt_inst_809:X ropt_net_237:7 0.152 +1 ropt_net_237:7 ropt_net_237:6 0.002216518 +2 ropt_net_237:6 ropt_net_237:5 0.0045 +3 ropt_net_237:5 ropt_net_237:4 0.002044643 +4 ropt_net_237:3 ropt_net_237:2 0.0003370536 +5 ropt_net_237:4 ropt_net_237:3 0.0045 +6 ropt_net_237:2 ropt_mt_inst_885:A 0.152 + +*END + +*D_NET ropt_net_225 0.001080157 //LENGTH 7.715 LUMPCC 0.0003098735 DR + +*CONN +*I ropt_mt_inst_820:X O *L 0 *C 138.635 56.440 +*I ropt_mt_inst_872:A I *L 0.001767 *C 134.780 58.480 +*N ropt_net_225:2 *C 134.780 58.480 +*N ropt_net_225:3 *C 134.365 58.480 +*N ropt_net_225:4 *C 134.320 58.435 +*N ropt_net_225:5 *C 134.320 56.485 +*N ropt_net_225:6 *C 134.365 56.440 +*N ropt_net_225:7 *C 138.597 56.440 + +*CAP +0 ropt_mt_inst_820:X 1e-06 +1 ropt_mt_inst_872:A 1e-06 +2 ropt_net_225:2 6.934376e-05 +3 ropt_net_225:3 4.164054e-05 +4 ropt_net_225:4 0.0001212216 +5 ropt_net_225:5 0.0001212216 +6 ropt_net_225:6 0.0002074278 +7 ropt_net_225:7 0.0002074278 +8 ropt_net_225:7 ropt_net_181:4 0.0001549367 +9 ropt_net_225:6 ropt_net_181:3 0.0001549367 + +*RES +0 ropt_mt_inst_820:X ropt_net_225:7 0.152 +1 ropt_net_225:7 ropt_net_225:6 0.003779018 +2 ropt_net_225:6 ropt_net_225:5 0.0045 +3 ropt_net_225:5 ropt_net_225:4 0.001741071 +4 ropt_net_225:3 ropt_net_225:2 0.0003705357 +5 ropt_net_225:4 ropt_net_225:3 0.0045 +6 ropt_net_225:2 ropt_mt_inst_872:A 0.152 + +*END + +*D_NET ropt_net_226 0.001589081 //LENGTH 10.715 LUMPCC 0.00026045 DR + +*CONN +*I ropt_mt_inst_838:X O *L 0 *C 87.595 124.440 +*I ropt_mt_inst_873:A I *L 0.001766 *C 80.960 126.480 +*N ropt_net_226:2 *C 80.960 126.480 +*N ropt_net_226:3 *C 80.960 126.820 +*N ropt_net_226:4 *C 80.960 126.775 +*N ropt_net_226:5 *C 80.960 125.858 +*N ropt_net_226:6 *C 80.968 125.800 +*N ropt_net_226:7 *C 87.392 125.800 +*N ropt_net_226:8 *C 87.400 125.743 +*N ropt_net_226:9 *C 87.400 124.485 +*N ropt_net_226:10 *C 87.400 124.440 +*N ropt_net_226:11 *C 87.595 124.440 + +*CAP +0 ropt_mt_inst_838:X 1e-06 +1 ropt_mt_inst_873:A 1e-06 +2 ropt_net_226:2 7.205788e-05 +3 ropt_net_226:3 7.71874e-05 +4 ropt_net_226:4 9.692819e-05 +5 ropt_net_226:5 9.692819e-05 +6 ropt_net_226:6 0.0003469257 +7 ropt_net_226:7 0.0003469257 +8 ropt_net_226:8 9.324453e-05 +9 ropt_net_226:9 9.324453e-05 +10 ropt_net_226:10 5.376293e-05 +11 ropt_net_226:11 4.942604e-05 +12 ropt_net_226:7 chany_bottom_in[17]:9 0.000130225 +13 ropt_net_226:6 chany_bottom_in[17]:10 0.000130225 + +*RES +0 ropt_mt_inst_838:X ropt_net_226:11 0.152 +1 ropt_net_226:11 ropt_net_226:10 0.0001059783 +2 ropt_net_226:10 ropt_net_226:9 0.0045 +3 ropt_net_226:9 ropt_net_226:8 0.001122768 +4 ropt_net_226:8 ropt_net_226:7 0.00341 +5 ropt_net_226:7 ropt_net_226:6 0.001006583 +6 ropt_net_226:5 ropt_net_226:4 0.0008191965 +7 ropt_net_226:6 ropt_net_226:5 0.00341 +8 ropt_net_226:3 ropt_net_226:2 0.0001465517 +9 ropt_net_226:4 ropt_net_226:3 0.0045 +10 ropt_net_226:2 ropt_mt_inst_873:A 0.152 + +*END + +*D_NET ropt_net_176 0.002810606 //LENGTH 24.130 LUMPCC 0.0004748093 DR + +*CONN +*I BUFT_P_133:X O *L 0 *C 4.600 61.540 +*I ropt_mt_inst_814:A I *L 0.001766 *C 7.820 74.800 +*N ropt_net_176:2 *C 7.783 74.800 +*N ropt_net_176:3 *C 5.980 74.800 +*N ropt_net_176:4 *C 5.980 74.460 +*N ropt_net_176:5 *C 1.425 74.460 +*N ropt_net_176:6 *C 1.380 74.415 +*N ropt_net_176:7 *C 1.380 61.585 +*N ropt_net_176:8 *C 1.425 61.540 +*N ropt_net_176:9 *C 4.562 61.540 + +*CAP +0 BUFT_P_133:X 1e-06 +1 ropt_mt_inst_814:A 1e-06 +2 ropt_net_176:2 0.0001127831 +3 ropt_net_176:3 0.0001392001 +4 ropt_net_176:4 0.0002720152 +5 ropt_net_176:5 0.0002455981 +6 ropt_net_176:6 0.0005937126 +7 ropt_net_176:7 0.0005937126 +8 ropt_net_176:8 0.0001883874 +9 ropt_net_176:9 0.0001883874 +10 ropt_net_176:6 chanx_right_in[8]:7 0.0001048222 +11 ropt_net_176:7 chanx_right_in[8]:8 0.0001048222 +12 ropt_net_176:2 ropt_net_206:7 2.089879e-05 +13 ropt_net_176:5 ropt_net_206:2 3.617772e-05 +14 ropt_net_176:5 ropt_net_206:6 7.550594e-05 +15 ropt_net_176:4 ropt_net_206:3 3.617772e-05 +16 ropt_net_176:4 ropt_net_206:7 7.550594e-05 +17 ropt_net_176:3 ropt_net_206:6 2.089879e-05 + +*RES +0 BUFT_P_133:X ropt_net_176:9 0.152 +1 ropt_net_176:2 ropt_mt_inst_814:A 0.152 +2 ropt_net_176:5 ropt_net_176:4 0.004066965 +3 ropt_net_176:6 ropt_net_176:5 0.0045 +4 ropt_net_176:8 ropt_net_176:7 0.0045 +5 ropt_net_176:7 ropt_net_176:6 0.01145536 +6 ropt_net_176:9 ropt_net_176:8 0.002801339 +7 ropt_net_176:4 ropt_net_176:3 0.0003035715 +8 ropt_net_176:3 ropt_net_176:2 0.001609375 + +*END + +*D_NET chany_top_out[10] 0.0008094118 //LENGTH 6.255 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_879:X O *L 0 *C 100.280 127.160 +*P chany_top_out[10] O *L 0.7423 *C 96.600 129.270 +*N chany_top_out[10]:2 *C 96.600 127.205 +*N chany_top_out[10]:3 *C 96.645 127.160 +*N chany_top_out[10]:4 *C 100.243 127.160 + +*CAP +0 ropt_mt_inst_879:X 1e-06 +1 chany_top_out[10] 0.000141415 +2 chany_top_out[10]:2 0.000141415 +3 chany_top_out[10]:3 0.0002627908 +4 chany_top_out[10]:4 0.0002627908 + +*RES +0 ropt_mt_inst_879:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.003212054 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.00184375 + +*END + +*D_NET chany_top_in[5] 0.02022956 //LENGTH 156.920 LUMPCC 0.00325698 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 60.260 129.270 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.440 14.620 +*I BUFT_P_115:A I *L 0.001776 *C 64.400 6.800 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.725 88.740 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.860 88.060 +*N chany_top_in[5]:5 *C 66.823 88.060 +*N chany_top_in[5]:6 *C 61.180 88.060 +*N chany_top_in[5]:7 *C 61.180 89.080 +*N chany_top_in[5]:8 *C 53.688 88.740 +*N chany_top_in[5]:9 *C 53.360 88.740 +*N chany_top_in[5]:10 *C 51.120 16.320 +*N chany_top_in[5]:11 *C 64.362 6.800 +*N chany_top_in[5]:12 *C 63.985 6.800 +*N chany_top_in[5]:13 *C 63.940 6.800 +*N chany_top_in[5]:14 *C 63.933 6.800 +*N chany_top_in[5]:15 *C 54.748 6.800 +*N chany_top_in[5]:16 *C 54.740 6.857 +*N chany_top_in[5]:17 *C 54.740 14.575 +*N chany_top_in[5]:18 *C 54.695 14.620 +*N chany_top_in[5]:19 *C 52.440 14.620 +*N chany_top_in[5]:20 *C 51.565 14.620 +*N chany_top_in[5]:21 *C 51.520 14.665 +*N chany_top_in[5]:22 *C 51.520 16.262 +*N chany_top_in[5]:23 *C 51.520 16.320 +*N chany_top_in[5]:24 *C 51.520 16.328 +*N chany_top_in[5]:25 *C 51.520 70.713 +*N chany_top_in[5]:26 *C 51.540 70.720 +*N chany_top_in[5]:27 *C 52.893 70.720 +*N chany_top_in[5]:28 *C 52.900 70.778 +*N chany_top_in[5]:29 *C 52.900 89.035 +*N chany_top_in[5]:30 *C 52.945 89.080 +*N chany_top_in[5]:31 *C 53.360 89.080 +*N chany_top_in[5]:32 *C 60.260 89.080 +*N chany_top_in[5]:33 *C 60.260 89.125 + +*CAP +0 chany_top_in[5] 0.002126563 +1 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +2 BUFT_P_115:A 1e-06 +3 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +4 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +5 chany_top_in[5]:5 0.0003738591 +6 chany_top_in[5]:6 0.0004323894 +7 chany_top_in[5]:7 0.0001159614 +8 chany_top_in[5]:8 3.380428e-05 +9 chany_top_in[5]:9 5.954082e-05 +10 chany_top_in[5]:10 9.487644e-05 +11 chany_top_in[5]:11 5.187413e-05 +12 chany_top_in[5]:12 5.187413e-05 +13 chany_top_in[5]:13 3.651415e-05 +14 chany_top_in[5]:14 0.0006036133 +15 chany_top_in[5]:15 0.0006036133 +16 chany_top_in[5]:16 0.0004225538 +17 chany_top_in[5]:17 0.0004225538 +18 chany_top_in[5]:18 0.0001691303 +19 chany_top_in[5]:19 0.0002706027 +20 chany_top_in[5]:20 7.372443e-05 +21 chany_top_in[5]:21 0.0001076207 +22 chany_top_in[5]:22 0.0001076207 +23 chany_top_in[5]:23 9.487644e-05 +24 chany_top_in[5]:24 0.002690139 +25 chany_top_in[5]:25 0.002690139 +26 chany_top_in[5]:26 0.0001870581 +27 chany_top_in[5]:27 0.0001870581 +28 chany_top_in[5]:28 0.0008803291 +29 chany_top_in[5]:29 0.0008803291 +30 chany_top_in[5]:30 4.511558e-05 +31 chany_top_in[5]:31 0.0005070862 +32 chany_top_in[5]:32 0.0005215986 +33 chany_top_in[5]:33 0.002126563 +34 chany_top_in[5]:19 chany_top_in[14]:12 3.270681e-06 +35 chany_top_in[5]:19 chany_top_in[14]:11 1.121376e-05 +36 chany_top_in[5]:20 chany_top_in[14]:11 3.270681e-06 +37 chany_top_in[5]:21 chany_top_in[14]:9 4.625733e-06 +38 chany_top_in[5]:21 chany_top_in[14]:13 2.616271e-06 +39 chany_top_in[5]:22 chany_top_in[14]:10 4.625733e-06 +40 chany_top_in[5]:22 chany_top_in[14]:14 2.616271e-06 +41 chany_top_in[5]:28 chany_top_in[14]:26 1.260259e-05 +42 chany_top_in[5]:28 chany_top_in[14]:23 4.15633e-05 +43 chany_top_in[5]:28 chany_top_in[14]:16 1.449003e-05 +44 chany_top_in[5]:28 chany_top_in[14]:14 0.0002762452 +45 chany_top_in[5]:29 chany_top_in[14]:26 4.15633e-05 +46 chany_top_in[5]:29 chany_top_in[14]:23 1.449003e-05 +47 chany_top_in[5]:29 chany_top_in[14]:15 0.0002762452 +48 chany_top_in[5]:29 chany_top_in[14]:27 1.260259e-05 +49 chany_top_in[5]:18 chany_top_in[14]:12 1.121376e-05 +50 chany_top_in[5]:17 chany_top_in[14]:10 9.681086e-06 +51 chany_top_in[5]:16 chany_top_in[14]:9 9.681086e-06 +52 chany_top_in[5]:32 chany_top_in[14]:24 3.690669e-07 +53 chany_top_in[5]:31 chany_top_in[14]:25 3.690669e-07 +54 chany_top_in[5] chanx_right_in[13]:22 3.69297e-05 +55 chany_top_in[5]:24 chanx_right_in[13]:26 0.0004947767 +56 chany_top_in[5]:25 chanx_right_in[13]:25 0.0004947767 +57 chany_top_in[5]:32 chanx_right_in[13]:17 1.929834e-05 +58 chany_top_in[5]:32 chanx_right_in[13]:16 1.709282e-05 +59 chany_top_in[5]:33 chanx_right_in[13]:18 3.69297e-05 +60 chany_top_in[5]:31 chanx_right_in[13]:16 1.929834e-05 +61 chany_top_in[5]:7 chanx_right_in[13]:17 1.709282e-05 +62 chany_top_in[5]:24 chany_bottom_in[18]:43 0.0002728384 +63 chany_top_in[5]:25 chany_bottom_in[18]:42 0.0002728384 +64 chany_top_in[5]:17 chany_bottom_in[18]:42 5.038483e-06 +65 chany_top_in[5]:16 chany_bottom_in[18]:43 5.038483e-06 +66 chany_top_in[5]:15 chany_bottom_in[18]:44 1.512127e-05 +67 chany_top_in[5]:14 chany_bottom_in[18]:45 1.512127e-05 +68 chany_top_in[5] mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002099848 +69 chany_top_in[5]:33 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002099848 +70 chany_top_in[5]:32 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.860279e-05 +71 chany_top_in[5]:31 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.860279e-05 +72 chany_top_in[5]:17 ropt_net_199:9 2.751185e-06 +73 chany_top_in[5]:17 ropt_net_199:4 7.937794e-05 +74 chany_top_in[5]:16 ropt_net_199:8 2.751185e-06 +75 chany_top_in[5]:16 ropt_net_199:5 7.937794e-05 + +*RES +0 chany_top_in[5] chany_top_in[5]:33 0.03584375 +1 chany_top_in[5]:19 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[5]:19 chany_top_in[5]:18 0.002013393 +3 chany_top_in[5]:20 chany_top_in[5]:19 0.00078125 +4 chany_top_in[5]:21 chany_top_in[5]:20 0.0045 +5 chany_top_in[5]:22 chany_top_in[5]:21 0.001426339 +6 chany_top_in[5]:23 chany_top_in[5]:22 0.00341 +7 chany_top_in[5]:23 chany_top_in[5]:10 5.69697e-05 +8 chany_top_in[5]:24 chany_top_in[5]:23 0.00341 +9 chany_top_in[5]:26 chany_top_in[5]:25 0.00341 +10 chany_top_in[5]:25 chany_top_in[5]:24 0.008520316 +11 chany_top_in[5]:28 chany_top_in[5]:27 0.00341 +12 chany_top_in[5]:27 chany_top_in[5]:26 0.0002118916 +13 chany_top_in[5]:30 chany_top_in[5]:29 0.0045 +14 chany_top_in[5]:29 chany_top_in[5]:28 0.01630134 +15 chany_top_in[5]:18 chany_top_in[5]:17 0.0045 +16 chany_top_in[5]:17 chany_top_in[5]:16 0.006890626 +17 chany_top_in[5]:16 chany_top_in[5]:15 0.00341 +18 chany_top_in[5]:15 chany_top_in[5]:14 0.001438983 +19 chany_top_in[5]:13 chany_top_in[5]:12 0.0045 +20 chany_top_in[5]:14 chany_top_in[5]:13 0.00341 +21 chany_top_in[5]:12 chany_top_in[5]:11 0.0003370536 +22 chany_top_in[5]:11 BUFT_P_115:A 0.152 +23 chany_top_in[5]:32 chany_top_in[5]:31 0.006160715 +24 chany_top_in[5]:32 chany_top_in[5]:7 0.0008214285 +25 chany_top_in[5]:33 chany_top_in[5]:32 0.0045 +26 chany_top_in[5]:8 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +27 chany_top_in[5]:5 mux_right_track_4\/mux_l1_in_0_:A0 0.152 +28 chany_top_in[5]:31 chany_top_in[5]:30 0.0003705357 +29 chany_top_in[5]:31 chany_top_in[5]:9 0.0003035714 +30 chany_top_in[5]:7 chany_top_in[5]:6 0.0009107143 +31 chany_top_in[5]:9 chany_top_in[5]:8 0.0002924107 +32 chany_top_in[5]:6 chany_top_in[5]:5 0.005037947 + +*END + +*D_NET chanx_right_in[6] 0.0298478 //LENGTH 187.575 LUMPCC 0.01200257 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 140.450 77.520 +*I BUFT_P_118:A I *L 0.001776 *C 10.120 72.080 +*I mux_left_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 71.130 69.700 +*I mux_bottom_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 88.955 37.060 +*I mux_top_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 91.640 56.100 +*N chanx_right_in[6]:5 *C 91.603 56.100 +*N chanx_right_in[6]:6 *C 88.993 37.060 +*N chanx_right_in[6]:7 *C 91.035 37.060 +*N chanx_right_in[6]:8 *C 91.080 37.105 +*N chanx_right_in[6]:9 *C 91.080 56.055 +*N chanx_right_in[6]:10 *C 91.080 56.100 +*N chanx_right_in[6]:11 *C 89.745 56.100 +*N chanx_right_in[6]:12 *C 89.700 56.145 +*N chanx_right_in[6]:13 *C 71.130 69.700 +*N chanx_right_in[6]:14 *C 71.300 69.700 +*N chanx_right_in[6]:15 *C 71.300 69.655 +*N chanx_right_in[6]:16 *C 10.083 72.080 +*N chanx_right_in[6]:17 *C 9.705 72.080 +*N chanx_right_in[6]:18 *C 9.660 72.035 +*N chanx_right_in[6]:19 *C 9.660 68.737 +*N chanx_right_in[6]:20 *C 9.668 68.680 +*N chanx_right_in[6]:21 *C 59.495 68.680 +*N chanx_right_in[6]:22 *C 71.293 68.680 +*N chanx_right_in[6]:23 *C 71.300 68.680 +*N chanx_right_in[6]:24 *C 71.300 66.005 +*N chanx_right_in[6]:25 *C 71.345 65.960 +*N chanx_right_in[6]:26 *C 89.655 65.960 +*N chanx_right_in[6]:27 *C 89.700 65.960 +*N chanx_right_in[6]:28 *C 89.700 69.983 +*N chanx_right_in[6]:29 *C 89.708 70.040 +*N chanx_right_in[6]:30 *C 112.220 70.040 +*N chanx_right_in[6]:31 *C 112.240 70.047 +*N chanx_right_in[6]:32 *C 112.240 76.833 +*N chanx_right_in[6]:33 *C 112.260 76.840 +*N chanx_right_in[6]:34 *C 138.920 76.840 +*N chanx_right_in[6]:35 *C 138.920 77.520 + +*CAP +0 chanx_right_in[6] 0.0001123849 +1 BUFT_P_118:A 1e-06 +2 mux_left_track_9\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_9\/mux_l1_in_1_:A0 1e-06 +4 mux_top_track_8\/mux_l1_in_1_:A1 1e-06 +5 chanx_right_in[6]:5 4.744298e-05 +6 chanx_right_in[6]:6 0.0001494813 +7 chanx_right_in[6]:7 0.0001494813 +8 chanx_right_in[6]:8 0.0007471026 +9 chanx_right_in[6]:9 0.0007471026 +10 chanx_right_in[6]:10 0.0001915335 +11 chanx_right_in[6]:11 0.0001063083 +12 chanx_right_in[6]:12 0.0005504219 +13 chanx_right_in[6]:13 5.799229e-05 +14 chanx_right_in[6]:14 6.282509e-05 +15 chanx_right_in[6]:15 6.894532e-05 +16 chanx_right_in[6]:16 4.578483e-05 +17 chanx_right_in[6]:17 4.578483e-05 +18 chanx_right_in[6]:18 0.0002397882 +19 chanx_right_in[6]:19 0.0002397882 +20 chanx_right_in[6]:20 0.00196919 +21 chanx_right_in[6]:21 0.0024741 +22 chanx_right_in[6]:22 0.0005049106 +23 chanx_right_in[6]:23 0.0002643778 +24 chanx_right_in[6]:24 0.0001566947 +25 chanx_right_in[6]:25 0.0009997399 +26 chanx_right_in[6]:26 0.0009997399 +27 chanx_right_in[6]:27 0.0008641788 +28 chanx_right_in[6]:28 0.0002801113 +29 chanx_right_in[6]:29 0.001068577 +30 chanx_right_in[6]:30 0.001068577 +31 chanx_right_in[6]:31 0.0003995941 +32 chanx_right_in[6]:32 0.0003995941 +33 chanx_right_in[6]:33 0.00131531 +34 chanx_right_in[6]:34 0.00135865 +35 chanx_right_in[6]:35 0.000155725 +36 chanx_right_in[6]:29 chany_top_in[16]:20 0.0002912218 +37 chanx_right_in[6]:30 chany_top_in[16]:19 0.0002912218 +38 chanx_right_in[6]:14 chany_top_in[16]:22 2.054851e-06 +39 chanx_right_in[6]:13 chany_top_in[16]:21 2.054851e-06 +40 chanx_right_in[6]:19 chanx_left_in[9]:47 7.396848e-06 +41 chanx_right_in[6]:20 chanx_left_in[9] 7.01161e-06 +42 chanx_right_in[6]:20 chanx_left_in[9]:33 0.0002551295 +43 chanx_right_in[6]:20 chanx_left_in[9]:47 9.132471e-05 +44 chanx_right_in[6]:18 chanx_left_in[9]:48 7.396848e-06 +45 chanx_right_in[6]:27 chanx_left_in[9]:23 3.053246e-06 +46 chanx_right_in[6]:28 chanx_left_in[9]:24 3.053246e-06 +47 chanx_right_in[6]:29 chanx_left_in[9]:22 9.558765e-06 +48 chanx_right_in[6]:29 chanx_left_in[9]:21 8.054712e-06 +49 chanx_right_in[6]:30 chanx_left_in[9]:21 9.558765e-06 +50 chanx_right_in[6]:30 chanx_left_in[9]:16 8.054712e-06 +51 chanx_right_in[6]:21 chanx_left_in[9]:32 0.0002551295 +52 chanx_right_in[6]:21 chanx_left_in[9]:46 9.132471e-05 +53 chanx_right_in[6]:21 chanx_left_in[9]:48 7.01161e-06 +54 chanx_right_in[6]:22 chanx_left_in[10]:24 0.0006208469 +55 chanx_right_in[6]:20 chanx_left_in[10]:25 0.001703558 +56 chanx_right_in[6]:33 chanx_left_in[10]:14 2.951916e-05 +57 chanx_right_in[6]:34 chanx_left_in[10]:13 2.951916e-05 +58 chanx_right_in[6]:21 chanx_left_in[10]:25 0.0006208469 +59 chanx_right_in[6]:21 chanx_left_in[10]:24 0.001703558 +60 chanx_right_in[6]:23 chanx_left_in[18]:20 8.829885e-06 +61 chanx_right_in[6]:22 chanx_left_in[18]:21 0.0001935091 +62 chanx_right_in[6]:20 chanx_left_in[18] 0.0008765344 +63 chanx_right_in[6]:20 chanx_left_in[18]:28 5.72783e-05 +64 chanx_right_in[6]:20 chanx_left_in[18]:22 4.349302e-05 +65 chanx_right_in[6]:24 chanx_left_in[18]:21 8.829885e-06 +66 chanx_right_in[6]:29 chanx_left_in[18]:16 4.423975e-06 +67 chanx_right_in[6]:30 chanx_left_in[18]:15 4.423975e-06 +68 chanx_right_in[6]:33 chanx_left_in[18]:16 7.558014e-05 +69 chanx_right_in[6]:33 chanx_left_in[18]:12 0.000109822 +70 chanx_right_in[6]:34 chanx_left_in[18]:15 7.558014e-05 +71 chanx_right_in[6]:34 chanx_left_in[18]:11 0.000109822 +72 chanx_right_in[6]:21 chanx_left_in[18]:27 5.72783e-05 +73 chanx_right_in[6]:21 chanx_left_in[18]:22 0.0001935091 +74 chanx_right_in[6]:21 chanx_left_in[18]:40 0.0008765344 +75 chanx_right_in[6]:21 chanx_left_in[18]:21 4.349302e-05 +76 chanx_right_in[6]:27 prog_clk[0]:284 8.868221e-07 +77 chanx_right_in[6]:12 prog_clk[0]:285 8.868221e-07 +78 chanx_right_in[6]:33 prog_clk[0]:165 0.0003295421 +79 chanx_right_in[6]:9 prog_clk[0]:218 0.0001323995 +80 chanx_right_in[6]:9 prog_clk[0]:222 2.27425e-05 +81 chanx_right_in[6]:8 prog_clk[0]:221 0.0001323995 +82 chanx_right_in[6]:8 prog_clk[0]:223 2.27425e-05 +83 chanx_right_in[6]:34 prog_clk[0]:164 0.0003295421 +84 chanx_right_in[6]:5 chanx_right_in[11]:9 1.59195e-06 +85 chanx_right_in[6]:10 chanx_right_in[11]:8 1.59195e-06 +86 chanx_right_in[6]:9 chanx_right_in[11]:10 0.0003201596 +87 chanx_right_in[6]:9 chanx_right_in[11]:5 1.10321e-07 +88 chanx_right_in[6]:8 chanx_right_in[11]:11 0.0003201596 +89 chanx_right_in[6]:8 chanx_right_in[11]:6 1.10321e-07 +90 chanx_right_in[6]:25 mux_tree_tapbuf_size10_3_sram[0]:6 5.898832e-06 +91 chanx_right_in[6]:25 mux_tree_tapbuf_size10_3_sram[0]:8 0.0004468804 +92 chanx_right_in[6]:26 mux_tree_tapbuf_size10_3_sram[0]:7 5.898832e-06 +93 chanx_right_in[6]:26 mux_tree_tapbuf_size10_3_sram[0]:9 0.0004468804 +94 chanx_right_in[6]:29 mux_tree_tapbuf_size10_3_sram[0]:21 1.503422e-05 +95 chanx_right_in[6]:30 mux_tree_tapbuf_size10_3_sram[0]:22 1.503422e-05 +96 chanx_right_in[6]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.59181e-05 +97 chanx_right_in[6]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0002283573 +98 chanx_right_in[6]:29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 4.356183e-05 +99 chanx_right_in[6]:30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 4.356183e-05 +100 chanx_right_in[6]:30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.59181e-05 +101 chanx_right_in[6]:30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002283573 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:35 0.0002397 +1 chanx_right_in[6]:23 chanx_right_in[6]:22 0.00341 +2 chanx_right_in[6]:23 chanx_right_in[6]:15 0.0008705358 +3 chanx_right_in[6]:22 chanx_right_in[6]:21 0.001848275 +4 chanx_right_in[6]:19 chanx_right_in[6]:18 0.002944196 +5 chanx_right_in[6]:20 chanx_right_in[6]:19 0.00341 +6 chanx_right_in[6]:17 chanx_right_in[6]:16 0.0003370536 +7 chanx_right_in[6]:18 chanx_right_in[6]:17 0.0045 +8 chanx_right_in[6]:16 BUFT_P_118:A 0.152 +9 chanx_right_in[6]:25 chanx_right_in[6]:24 0.0045 +10 chanx_right_in[6]:24 chanx_right_in[6]:23 0.002388393 +11 chanx_right_in[6]:26 chanx_right_in[6]:25 0.01634821 +12 chanx_right_in[6]:27 chanx_right_in[6]:26 0.0045 +13 chanx_right_in[6]:27 chanx_right_in[6]:12 0.008763393 +14 chanx_right_in[6]:11 chanx_right_in[6]:10 0.001191964 +15 chanx_right_in[6]:12 chanx_right_in[6]:11 0.0045 +16 chanx_right_in[6]:5 mux_top_track_8\/mux_l1_in_1_:A1 0.152 +17 chanx_right_in[6]:28 chanx_right_in[6]:27 0.003591518 +18 chanx_right_in[6]:29 chanx_right_in[6]:28 0.00341 +19 chanx_right_in[6]:30 chanx_right_in[6]:29 0.003526958 +20 chanx_right_in[6]:31 chanx_right_in[6]:30 0.00341 +21 chanx_right_in[6]:33 chanx_right_in[6]:32 0.00341 +22 chanx_right_in[6]:32 chanx_right_in[6]:31 0.001062983 +23 chanx_right_in[6]:10 chanx_right_in[6]:9 0.0045 +24 chanx_right_in[6]:10 chanx_right_in[6]:5 0.0004665179 +25 chanx_right_in[6]:9 chanx_right_in[6]:8 0.01691964 +26 chanx_right_in[6]:7 chanx_right_in[6]:6 0.001823661 +27 chanx_right_in[6]:8 chanx_right_in[6]:7 0.0045 +28 chanx_right_in[6]:6 mux_bottom_track_9\/mux_l1_in_1_:A0 0.152 +29 chanx_right_in[6]:14 chanx_right_in[6]:13 9.239131e-05 +30 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0045 +31 chanx_right_in[6]:13 mux_left_track_9\/mux_l1_in_1_:A0 0.152 +32 chanx_right_in[6]:34 chanx_right_in[6]:33 0.004176733 +33 chanx_right_in[6]:35 chanx_right_in[6]:34 0.0001065333 +34 chanx_right_in[6]:21 chanx_right_in[6]:20 0.007806308 + +*END + +*D_NET chanx_right_in[8] 0.02655693 //LENGTH 171.550 LUMPCC 0.01035442 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 140.450 44.880 +*I mux_bottom_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 77.570 42.840 +*I mux_top_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.445 50.660 +*I mux_left_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 66.990 53.720 +*I ropt_mt_inst_804:A I *L 0.001767 *C 3.220 72.080 +*N chanx_right_in[8]:5 *C 3.183 72.080 +*N chanx_right_in[8]:6 *C 2.345 72.080 +*N chanx_right_in[8]:7 *C 2.300 72.035 +*N chanx_right_in[8]:8 *C 2.300 55.138 +*N chanx_right_in[8]:9 *C 2.308 55.080 +*N chanx_right_in[8]:10 *C 52.135 55.080 +*N chanx_right_in[8]:11 *C 67.153 55.080 +*N chanx_right_in[8]:12 *C 67.160 55.023 +*N chanx_right_in[8]:13 *C 66.990 53.720 +*N chanx_right_in[8]:14 *C 67.160 53.720 +*N chanx_right_in[8]:15 *C 67.160 53.720 +*N chanx_right_in[8]:16 *C 67.160 50.705 +*N chanx_right_in[8]:17 *C 67.205 50.660 +*N chanx_right_in[8]:18 *C 68.448 50.660 +*N chanx_right_in[8]:19 *C 68.540 50.615 +*N chanx_right_in[8]:20 *C 68.540 46.965 +*N chanx_right_in[8]:21 *C 68.585 46.920 +*N chanx_right_in[8]:22 *C 77.235 46.920 +*N chanx_right_in[8]:23 *C 77.280 46.875 +*N chanx_right_in[8]:24 *C 77.570 42.840 +*N chanx_right_in[8]:25 *C 77.280 42.840 +*N chanx_right_in[8]:26 *C 77.280 42.885 +*N chanx_right_in[8]:27 *C 77.280 44.880 +*N chanx_right_in[8]:28 *C 77.288 44.880 +*N chanx_right_in[8]:29 *C 127.115 44.880 + +*CAP +0 chanx_right_in[8] 0.0005745588 +1 mux_bottom_track_17\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A1 1e-06 +3 mux_left_track_17\/mux_l1_in_1_:A0 1e-06 +4 ropt_mt_inst_804:A 1e-06 +5 chanx_right_in[8]:5 6.695459e-05 +6 chanx_right_in[8]:6 6.695459e-05 +7 chanx_right_in[8]:7 0.0008019692 +8 chanx_right_in[8]:8 0.0008019692 +9 chanx_right_in[8]:9 0.002385831 +10 chanx_right_in[8]:10 0.003264606 +11 chanx_right_in[8]:11 0.0008787748 +12 chanx_right_in[8]:12 7.669716e-05 +13 chanx_right_in[8]:13 4.966547e-05 +14 chanx_right_in[8]:14 5.492287e-05 +15 chanx_right_in[8]:15 0.0002700658 +16 chanx_right_in[8]:16 0.0001615734 +17 chanx_right_in[8]:17 0.000103054 +18 chanx_right_in[8]:18 0.000103054 +19 chanx_right_in[8]:19 0.000183478 +20 chanx_right_in[8]:20 0.000183478 +21 chanx_right_in[8]:21 0.0006023715 +22 chanx_right_in[8]:22 0.0006023715 +23 chanx_right_in[8]:23 0.0001480364 +24 chanx_right_in[8]:24 4.49923e-05 +25 chanx_right_in[8]:25 4.957056e-05 +26 chanx_right_in[8]:26 0.0001374909 +27 chanx_right_in[8]:27 0.000325863 +28 chanx_right_in[8]:28 0.001842823 +29 chanx_right_in[8]:29 0.002417381 +30 chanx_right_in[8]:12 chanx_right_in[9]:12 3.877005e-05 +31 chanx_right_in[8]:11 chanx_right_in[9]:18 2.396712e-05 +32 chanx_right_in[8]:11 chanx_right_in[9]:17 6.078778e-05 +33 chanx_right_in[8]:9 chanx_right_in[9]:16 0.000469979 +34 chanx_right_in[8]:16 chanx_right_in[9]:19 1.772932e-05 +35 chanx_right_in[8]:16 chanx_right_in[9]:20 5.801139e-05 +36 chanx_right_in[8]:15 chanx_right_in[9]:19 9.678144e-05 +37 chanx_right_in[8]:15 chanx_right_in[9]:12 1.772932e-05 +38 chanx_right_in[8]:10 chanx_right_in[9]:16 6.078778e-05 +39 chanx_right_in[8]:10 chanx_right_in[9]:17 0.0004939461 +40 chanx_right_in[8]:9 chanx_left_in[17] 4.462871e-05 +41 chanx_right_in[8]:28 chanx_left_in[17]:25 4.945088e-05 +42 chanx_right_in[8]:28 chanx_left_in[17]:17 0.0003134895 +43 chanx_right_in[8]:10 chanx_left_in[17]:34 4.462871e-05 +44 chanx_right_in[8]:29 chanx_left_in[17]:13 0.0003134895 +45 chanx_right_in[8]:29 chanx_left_in[17]:17 4.945088e-05 +46 chanx_right_in[8]:8 prog_clk[0]:706 5.837762e-06 +47 chanx_right_in[8]:9 prog_clk[0]:475 0.0001206616 +48 chanx_right_in[8]:9 prog_clk[0]:692 0.0001939095 +49 chanx_right_in[8]:9 prog_clk[0]:691 8.76862e-05 +50 chanx_right_in[8]:7 prog_clk[0]:679 5.837762e-06 +51 chanx_right_in[8]:28 prog_clk[0]:297 5.192407e-06 +52 chanx_right_in[8]:10 prog_clk[0]:474 0.0001206616 +53 chanx_right_in[8]:10 prog_clk[0]:692 8.76862e-05 +54 chanx_right_in[8]:10 prog_clk[0]:686 0.0001939095 +55 chanx_right_in[8]:29 prog_clk[0]:298 5.192407e-06 +56 chanx_right_in[8] chanx_right_in[11] 0.0002223958 +57 chanx_right_in[8] chanx_right_in[11]:13 5.958203e-05 +58 chanx_right_in[8]:25 chanx_right_in[11]:3 1.268457e-05 +59 chanx_right_in[8]:24 chanx_right_in[11]:4 1.268457e-05 +60 chanx_right_in[8]:28 chanx_right_in[11]:12 0.0005330659 +61 chanx_right_in[8]:28 chanx_right_in[11]:7 2.607471e-05 +62 chanx_right_in[8]:29 chanx_right_in[11]:12 8.565673e-05 +63 chanx_right_in[8]:29 chanx_right_in[11]:13 0.0005330659 +64 chanx_right_in[8]:29 chanx_right_in[11]:14 0.0002223958 +65 chanx_right_in[8]:19 chanx_right_in[15]:5 7.457371e-05 +66 chanx_right_in[8]:20 chanx_right_in[15]:6 7.457371e-05 +67 chanx_right_in[8]:28 chanx_right_in[15]:11 0.0002599392 +68 chanx_right_in[8]:28 chanx_right_in[15]:7 0.0001471859 +69 chanx_right_in[8]:29 chanx_right_in[15]:12 0.0002599392 +70 chanx_right_in[8]:29 chanx_right_in[15]:11 0.0001471859 +71 chanx_right_in[8]:11 chany_bottom_in[7]:9 0.0002850622 +72 chanx_right_in[8]:10 chany_bottom_in[7]:8 0.0002850622 +73 chanx_right_in[8]:8 ropt_net_155:5 6.463652e-05 +74 chanx_right_in[8]:7 ropt_net_155:4 6.463652e-05 +75 chanx_right_in[8]:28 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00075715 +76 chanx_right_in[8]:29 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.00075715 +77 chanx_right_in[8]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002821543 +78 chanx_right_in[8]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0008577827 +79 chanx_right_in[8]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0008577827 +80 chanx_right_in[8]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002821543 +81 chanx_right_in[8]:8 ropt_net_176:7 0.0001048222 +82 chanx_right_in[8]:7 ropt_net_176:6 0.0001048222 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:29 0.00208915 +1 chanx_right_in[8]:18 mux_top_track_16\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[8]:18 chanx_right_in[8]:17 0.001109375 +3 chanx_right_in[8]:19 chanx_right_in[8]:18 0.0045 +4 chanx_right_in[8]:21 chanx_right_in[8]:20 0.0045 +5 chanx_right_in[8]:20 chanx_right_in[8]:19 0.003258929 +6 chanx_right_in[8]:22 chanx_right_in[8]:21 0.007723215 +7 chanx_right_in[8]:23 chanx_right_in[8]:22 0.0045 +8 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00341 +9 chanx_right_in[8]:11 chanx_right_in[8]:10 0.002352742 +10 chanx_right_in[8]:8 chanx_right_in[8]:7 0.01508706 +11 chanx_right_in[8]:9 chanx_right_in[8]:8 0.00341 +12 chanx_right_in[8]:6 chanx_right_in[8]:5 0.0007477679 +13 chanx_right_in[8]:7 chanx_right_in[8]:6 0.0045 +14 chanx_right_in[8]:5 ropt_mt_inst_804:A 0.152 +15 chanx_right_in[8]:17 chanx_right_in[8]:16 0.0045 +16 chanx_right_in[8]:16 chanx_right_in[8]:15 0.002691964 +17 chanx_right_in[8]:14 chanx_right_in[8]:13 9.239131e-05 +18 chanx_right_in[8]:15 chanx_right_in[8]:14 0.0045 +19 chanx_right_in[8]:15 chanx_right_in[8]:12 0.001162946 +20 chanx_right_in[8]:13 mux_left_track_17\/mux_l1_in_1_:A0 0.152 +21 chanx_right_in[8]:25 chanx_right_in[8]:24 0.0001576087 +22 chanx_right_in[8]:26 chanx_right_in[8]:25 0.0045 +23 chanx_right_in[8]:24 mux_bottom_track_17\/mux_l1_in_1_:A0 0.152 +24 chanx_right_in[8]:27 chanx_right_in[8]:26 0.00178125 +25 chanx_right_in[8]:27 chanx_right_in[8]:23 0.00178125 +26 chanx_right_in[8]:28 chanx_right_in[8]:27 0.00341 +27 chanx_right_in[8]:10 chanx_right_in[8]:9 0.007806308 +28 chanx_right_in[8]:29 chanx_right_in[8]:28 0.007806308 + +*END + +*D_NET chanx_right_in[9] 0.02549309 //LENGTH 157.035 LUMPCC 0.01262779 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 140.450 51.000 +*I mux_bottom_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 74.350 49.640 +*I FTB_19__18:A I *L 0.001776 *C 14.720 53.040 +*I mux_top_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 61.180 61.540 +*I mux_left_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 67.910 59.160 +*N chanx_right_in[9]:5 *C 67.873 59.160 +*N chanx_right_in[9]:6 *C 61.218 61.540 +*N chanx_right_in[9]:7 *C 63.895 61.540 +*N chanx_right_in[9]:8 *C 63.940 61.495 +*N chanx_right_in[9]:9 *C 63.940 59.205 +*N chanx_right_in[9]:10 *C 63.985 59.160 +*N chanx_right_in[9]:11 *C 66.700 59.160 +*N chanx_right_in[9]:12 *C 66.700 59.115 +*N chanx_right_in[9]:13 *C 14.683 53.040 +*N chanx_right_in[9]:14 *C 10.165 53.040 +*N chanx_right_in[9]:15 *C 10.120 53.040 +*N chanx_right_in[9]:16 *C 10.128 53.040 +*N chanx_right_in[9]:17 *C 59.955 53.040 +*N chanx_right_in[9]:18 *C 66.693 53.040 +*N chanx_right_in[9]:19 *C 66.700 53.040 +*N chanx_right_in[9]:20 *C 66.700 51.058 +*N chanx_right_in[9]:21 *C 66.708 51.000 +*N chanx_right_in[9]:22 *C 74.312 49.640 +*N chanx_right_in[9]:23 *C 73.645 49.640 +*N chanx_right_in[9]:24 *C 73.600 49.685 +*N chanx_right_in[9]:25 *C 73.600 50.943 +*N chanx_right_in[9]:26 *C 73.600 51.000 +*N chanx_right_in[9]:27 *C 123.600 51.000 + +*CAP +0 chanx_right_in[9] 0.0006305799 +1 mux_bottom_track_25\/mux_l1_in_1_:A0 1e-06 +2 FTB_19__18:A 1e-06 +3 mux_top_track_24\/mux_l1_in_1_:A1 1e-06 +4 mux_left_track_25\/mux_l1_in_1_:A0 1e-06 +5 chanx_right_in[9]:5 9.535308e-05 +6 chanx_right_in[9]:6 0.0002711155 +7 chanx_right_in[9]:7 0.0002711155 +8 chanx_right_in[9]:8 0.0001777172 +9 chanx_right_in[9]:9 0.0001777172 +10 chanx_right_in[9]:10 0.000145108 +11 chanx_right_in[9]:11 0.0002750409 +12 chanx_right_in[9]:12 0.0003232603 +13 chanx_right_in[9]:13 0.0002777672 +14 chanx_right_in[9]:14 0.0002777672 +15 chanx_right_in[9]:15 3.307516e-05 +16 chanx_right_in[9]:16 0.001677124 +17 chanx_right_in[9]:17 0.002016453 +18 chanx_right_in[9]:18 0.0003393282 +19 chanx_right_in[9]:19 0.0004440377 +20 chanx_right_in[9]:20 8.514232e-05 +21 chanx_right_in[9]:21 0.0003682729 +22 chanx_right_in[9]:22 6.672805e-05 +23 chanx_right_in[9]:23 6.672805e-05 +24 chanx_right_in[9]:24 0.0001068212 +25 chanx_right_in[9]:25 0.0001068212 +26 chanx_right_in[9]:26 0.002182964 +27 chanx_right_in[9]:27 0.002445271 +28 chanx_right_in[9]:19 chanx_right_in[8]:15 9.678144e-05 +29 chanx_right_in[9]:19 chanx_right_in[8]:16 1.772932e-05 +30 chanx_right_in[9]:18 chanx_right_in[8]:11 2.396712e-05 +31 chanx_right_in[9]:16 chanx_right_in[8]:9 0.000469979 +32 chanx_right_in[9]:16 chanx_right_in[8]:10 6.078778e-05 +33 chanx_right_in[9]:12 chanx_right_in[8]:12 3.877005e-05 +34 chanx_right_in[9]:12 chanx_right_in[8]:15 1.772932e-05 +35 chanx_right_in[9]:20 chanx_right_in[8]:16 5.801139e-05 +36 chanx_right_in[9]:17 chanx_right_in[8]:10 0.0004939461 +37 chanx_right_in[9]:17 chanx_right_in[8]:11 6.078778e-05 +38 chanx_right_in[9] chanx_right_in[10]:34 0.0001413184 +39 chanx_right_in[9]:26 chanx_right_in[10]:27 4.051748e-06 +40 chanx_right_in[9]:26 chanx_right_in[10]:33 0.0002020508 +41 chanx_right_in[9]:26 chanx_right_in[10]:28 1.963597e-05 +42 chanx_right_in[9]:27 chanx_right_in[10]:34 0.0002020508 +43 chanx_right_in[9]:27 chanx_right_in[10]:33 0.0001609544 +44 chanx_right_in[9]:27 chanx_right_in[10]:28 4.051748e-06 +45 chanx_right_in[9]:26 chanx_right_in[16]:39 0.0004067456 +46 chanx_right_in[9]:26 chanx_right_in[16]:40 0.0003599807 +47 chanx_right_in[9]:26 chanx_right_in[16]:41 0.000136248 +48 chanx_right_in[9]:21 chanx_right_in[16]:39 0.0003599807 +49 chanx_right_in[9]:27 chanx_right_in[16]:42 0.000136248 +50 chanx_right_in[9]:27 chanx_right_in[16]:40 0.0004067456 +51 chanx_right_in[9]:26 chanx_left_in[16]:19 1.165929e-05 +52 chanx_right_in[9]:26 chanx_left_in[16]:40 1.165159e-05 +53 chanx_right_in[9]:26 chanx_left_in[16]:39 8.421345e-05 +54 chanx_right_in[9]:26 chanx_left_in[16]:38 0.0006339292 +55 chanx_right_in[9]:26 chanx_left_in[16]:36 0.0004183963 +56 chanx_right_in[9]:18 chanx_left_in[16]:39 0.0003620988 +57 chanx_right_in[9]:16 chanx_left_in[16] 0.0006472813 +58 chanx_right_in[9]:16 chanx_left_in[16]:40 0.001086959 +59 chanx_right_in[9]:21 chanx_left_in[16]:40 8.421345e-05 +60 chanx_right_in[9]:17 chanx_left_in[16]:41 0.0006472813 +61 chanx_right_in[9]:17 chanx_left_in[16]:40 0.0003620988 +62 chanx_right_in[9]:17 chanx_left_in[16]:39 0.001086959 +63 chanx_right_in[9]:27 chanx_left_in[16]:18 1.165929e-05 +64 chanx_right_in[9]:27 chanx_left_in[16]:35 0.0004183963 +65 chanx_right_in[9]:27 chanx_left_in[16]:39 1.165159e-05 +66 chanx_right_in[9]:27 chanx_left_in[16]:37 0.0006339292 +67 chanx_right_in[9]:26 prog_clk[0]:213 0.0003566321 +68 chanx_right_in[9]:16 prog_clk[0]:475 0.0003157789 +69 chanx_right_in[9]:17 prog_clk[0]:474 0.0003157789 +70 chanx_right_in[9]:27 prog_clk[0]:212 0.0003566321 +71 chanx_right_in[9] chanx_right_in[0]:13 3.134701e-05 +72 chanx_right_in[9] chanx_right_in[0]:12 0.0001452398 +73 chanx_right_in[9]:26 chanx_right_in[0]:11 0.0001799875 +74 chanx_right_in[9]:26 chanx_right_in[0]:7 1.561849e-06 +75 chanx_right_in[9]:23 chanx_right_in[0]:3 3.513975e-06 +76 chanx_right_in[9]:22 chanx_right_in[0]:4 3.513975e-06 +77 chanx_right_in[9]:27 chanx_right_in[0]:11 0.0001468016 +78 chanx_right_in[9]:27 chanx_right_in[0]:12 0.0002113345 +79 chanx_right_in[9]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.436672e-05 +80 chanx_right_in[9]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.436672e-05 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:27 0.002639833 +1 chanx_right_in[9]:25 chanx_right_in[9]:24 0.001122768 +2 chanx_right_in[9]:26 chanx_right_in[9]:25 0.00341 +3 chanx_right_in[9]:26 chanx_right_in[9]:21 0.001079825 +4 chanx_right_in[9]:23 chanx_right_in[9]:22 0.0005959822 +5 chanx_right_in[9]:24 chanx_right_in[9]:23 0.0045 +6 chanx_right_in[9]:22 mux_bottom_track_25\/mux_l1_in_1_:A0 0.152 +7 chanx_right_in[9]:19 chanx_right_in[9]:18 0.00341 +8 chanx_right_in[9]:19 chanx_right_in[9]:12 0.005424107 +9 chanx_right_in[9]:18 chanx_right_in[9]:17 0.001055542 +10 chanx_right_in[9]:15 chanx_right_in[9]:14 0.0045 +11 chanx_right_in[9]:16 chanx_right_in[9]:15 0.00341 +12 chanx_right_in[9]:14 chanx_right_in[9]:13 0.004033483 +13 chanx_right_in[9]:13 FTB_19__18:A 0.152 +14 chanx_right_in[9]:11 chanx_right_in[9]:10 0.002424107 +15 chanx_right_in[9]:11 chanx_right_in[9]:5 0.001046875 +16 chanx_right_in[9]:12 chanx_right_in[9]:11 0.0045 +17 chanx_right_in[9]:20 chanx_right_in[9]:19 0.001770089 +18 chanx_right_in[9]:21 chanx_right_in[9]:20 0.00341 +19 chanx_right_in[9]:5 mux_left_track_25\/mux_l1_in_1_:A0 0.152 +20 chanx_right_in[9]:10 chanx_right_in[9]:9 0.0045 +21 chanx_right_in[9]:9 chanx_right_in[9]:8 0.002044643 +22 chanx_right_in[9]:7 chanx_right_in[9]:6 0.002390625 +23 chanx_right_in[9]:8 chanx_right_in[9]:7 0.0045 +24 chanx_right_in[9]:6 mux_top_track_24\/mux_l1_in_1_:A1 0.152 +25 chanx_right_in[9]:17 chanx_right_in[9]:16 0.007806308 +26 chanx_right_in[9]:27 chanx_right_in[9]:26 0.007833333 + +*END + +*D_NET chanx_right_in[10] 0.03034979 //LENGTH 216.560 LUMPCC 0.008935549 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 140.450 36.720 +*I mux_top_track_32\/mux_l1_in_1_:A0 I *L 0.001631 *C 84.930 53.720 +*I mux_left_track_33\/mux_l1_in_1_:A1 I *L 0.00198 *C 24.285 69.020 +*I FTB_20__19:A I *L 0.001767 *C 11.500 91.120 +*I mux_bottom_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 25.590 53.380 +*N chanx_right_in[10]:5 *C 25.628 53.380 +*N chanx_right_in[10]:6 *C 11.463 91.120 +*N chanx_right_in[10]:7 *C 10.165 91.120 +*N chanx_right_in[10]:8 *C 10.120 91.075 +*N chanx_right_in[10]:9 *C 10.120 64.657 +*N chanx_right_in[10]:10 *C 10.128 64.600 +*N chanx_right_in[10]:11 *C 18.852 64.600 +*N chanx_right_in[10]:12 *C 18.860 64.543 +*N chanx_right_in[10]:13 *C 18.860 63.965 +*N chanx_right_in[10]:14 *C 18.905 63.920 +*N chanx_right_in[10]:15 *C 24.323 69.020 +*N chanx_right_in[10]:16 *C 24.795 69.020 +*N chanx_right_in[10]:17 *C 24.840 68.975 +*N chanx_right_in[10]:18 *C 24.840 63.965 +*N chanx_right_in[10]:19 *C 24.840 63.920 +*N chanx_right_in[10]:20 *C 27.095 63.920 +*N chanx_right_in[10]:21 *C 27.140 63.875 +*N chanx_right_in[10]:22 *C 27.140 53.425 +*N chanx_right_in[10]:23 *C 27.140 53.380 +*N chanx_right_in[10]:24 *C 37.675 53.380 +*N chanx_right_in[10]:25 *C 37.720 53.335 +*N chanx_right_in[10]:26 *C 37.720 48.338 +*N chanx_right_in[10]:27 *C 37.727 48.280 +*N chanx_right_in[10]:28 *C 87.555 48.280 +*N chanx_right_in[10]:29 *C 84.968 53.720 +*N chanx_right_in[10]:30 *C 97.935 53.720 +*N chanx_right_in[10]:31 *C 97.980 53.675 +*N chanx_right_in[10]:32 *C 97.980 48.338 +*N chanx_right_in[10]:33 *C 97.980 48.280 +*N chanx_right_in[10]:34 *C 134.312 48.280 +*N chanx_right_in[10]:35 *C 134.320 48.223 +*N chanx_right_in[10]:36 *C 134.320 36.778 +*N chanx_right_in[10]:37 *C 134.328 36.720 + +*CAP +0 chanx_right_in[10] 0.0004278857 +1 mux_top_track_32\/mux_l1_in_1_:A0 1e-06 +2 mux_left_track_33\/mux_l1_in_1_:A1 1e-06 +3 FTB_20__19:A 1e-06 +4 mux_bottom_track_33\/mux_l1_in_0_:A0 1e-06 +5 chanx_right_in[10]:5 0.0001046866 +6 chanx_right_in[10]:6 0.0001097724 +7 chanx_right_in[10]:7 0.0001097724 +8 chanx_right_in[10]:8 0.001391887 +9 chanx_right_in[10]:9 0.001391887 +10 chanx_right_in[10]:10 0.0005570526 +11 chanx_right_in[10]:11 0.0005570526 +12 chanx_right_in[10]:12 6.631542e-05 +13 chanx_right_in[10]:13 6.631542e-05 +14 chanx_right_in[10]:14 0.0003459589 +15 chanx_right_in[10]:15 5.003688e-05 +16 chanx_right_in[10]:16 5.003688e-05 +17 chanx_right_in[10]:17 0.0002404182 +18 chanx_right_in[10]:18 0.0002404182 +19 chanx_right_in[10]:19 0.0004938396 +20 chanx_right_in[10]:20 0.000116041 +21 chanx_right_in[10]:21 0.0006283731 +22 chanx_right_in[10]:22 0.0006283731 +23 chanx_right_in[10]:23 0.0007623138 +24 chanx_right_in[10]:24 0.0006194385 +25 chanx_right_in[10]:25 0.0002372602 +26 chanx_right_in[10]:26 0.0002372602 +27 chanx_right_in[10]:27 0.002325421 +28 chanx_right_in[10]:28 0.002831277 +29 chanx_right_in[10]:29 0.0009398547 +30 chanx_right_in[10]:30 0.0009398547 +31 chanx_right_in[10]:31 0.0003299653 +32 chanx_right_in[10]:32 0.0003299653 +33 chanx_right_in[10]:33 0.001618847 +34 chanx_right_in[10]:34 0.001112991 +35 chanx_right_in[10]:35 0.0005608899 +36 chanx_right_in[10]:36 0.0005608899 +37 chanx_right_in[10]:37 0.0004278857 +38 chanx_right_in[10]:34 chanx_right_in[9] 0.0001413184 +39 chanx_right_in[10]:34 chanx_right_in[9]:27 0.0002020508 +40 chanx_right_in[10]:27 chanx_right_in[9]:26 4.051748e-06 +41 chanx_right_in[10]:33 chanx_right_in[9]:26 0.0002020508 +42 chanx_right_in[10]:33 chanx_right_in[9]:27 0.0001609544 +43 chanx_right_in[10]:28 chanx_right_in[9]:26 1.963597e-05 +44 chanx_right_in[10]:28 chanx_right_in[9]:27 4.051748e-06 +45 chanx_right_in[10] chanx_right_in[16]:55 3.604823e-06 +46 chanx_right_in[10]:9 chanx_right_in[16]:14 1.40227e-06 +47 chanx_right_in[10]:8 chanx_right_in[16]:13 1.40227e-06 +48 chanx_right_in[10]:37 chanx_right_in[16]:54 3.604823e-06 +49 chanx_right_in[10]:27 chanx_right_in[16]:39 1.090152e-05 +50 chanx_right_in[10]:27 chanx_right_in[16]:31 0.0001608121 +51 chanx_right_in[10]:27 chanx_right_in[16]:33 1.899083e-05 +52 chanx_right_in[10]:27 chanx_right_in[16]:41 0.0001083567 +53 chanx_right_in[10]:33 chanx_right_in[16]:42 2.417302e-05 +54 chanx_right_in[10]:30 chanx_right_in[16]:5 7.937121e-06 +55 chanx_right_in[10]:29 chanx_right_in[16]:6 7.937121e-06 +56 chanx_right_in[10]:28 chanx_right_in[16]:42 0.0001083567 +57 chanx_right_in[10]:28 chanx_right_in[16]:34 1.899083e-05 +58 chanx_right_in[10]:28 chanx_right_in[16]:32 0.0001608121 +59 chanx_right_in[10]:28 chanx_right_in[16]:40 1.090152e-05 +60 chanx_right_in[10]:28 chanx_right_in[16]:41 2.417302e-05 +61 chanx_right_in[10]:27 chany_bottom_in[8]:29 0.0003427826 +62 chanx_right_in[10]:28 chany_bottom_in[8]:30 0.0003427826 +63 chanx_right_in[10]:34 chany_bottom_in[16]:24 0.000493383 +64 chanx_right_in[10]:33 chany_bottom_in[16]:28 0.000493383 +65 chanx_right_in[10]:33 chany_bottom_in[16]:24 0.0001775929 +66 chanx_right_in[10]:28 chany_bottom_in[16]:28 0.0001775929 +67 chanx_right_in[10]:34 chanx_left_in[17]:13 0.0005002934 +68 chanx_right_in[10]:34 chanx_left_in[17]:9 6.086899e-06 +69 chanx_right_in[10]:27 chanx_left_in[17]:25 0.0006957432 +70 chanx_right_in[10]:27 chanx_left_in[17]:29 1.596879e-05 +71 chanx_right_in[10]:27 chanx_left_in[17]:27 0.0005852912 +72 chanx_right_in[10]:33 chanx_left_in[17]:13 9.455971e-05 +73 chanx_right_in[10]:33 chanx_left_in[17]:10 6.086899e-06 +74 chanx_right_in[10]:33 chanx_left_in[17]:17 0.0005221204 +75 chanx_right_in[10]:28 chanx_left_in[17]:25 2.182699e-05 +76 chanx_right_in[10]:28 chanx_left_in[17]:17 0.0007903029 +77 chanx_right_in[10]:28 chanx_left_in[17]:28 1.596879e-05 +78 chanx_right_in[10]:28 chanx_left_in[17]:26 0.0005852912 +79 chanx_right_in[10]:9 prog_clk[0]:667 3.616401e-06 +80 chanx_right_in[10]:9 prog_clk[0]:666 1.345685e-05 +81 chanx_right_in[10]:8 prog_clk[0]:662 1.345685e-05 +82 chanx_right_in[10]:8 prog_clk[0]:666 3.616401e-06 +83 chanx_right_in[10]:34 prog_clk[0]:212 3.56031e-07 +84 chanx_right_in[10]:18 prog_clk[0]:633 6.355447e-05 +85 chanx_right_in[10]:17 prog_clk[0]:628 6.355447e-05 +86 chanx_right_in[10]:24 prog_clk[0]:474 5.979846e-06 +87 chanx_right_in[10]:24 prog_clk[0]:476 2.254748e-05 +88 chanx_right_in[10]:25 prog_clk[0]:473 1.679317e-05 +89 chanx_right_in[10]:26 prog_clk[0]:472 1.679317e-05 +90 chanx_right_in[10]:33 prog_clk[0]:216 0.000204618 +91 chanx_right_in[10]:33 prog_clk[0]:213 3.56031e-07 +92 chanx_right_in[10]:33 prog_clk[0]:212 2.36024e-06 +93 chanx_right_in[10]:23 prog_clk[0]:475 5.979846e-06 +94 chanx_right_in[10]:23 prog_clk[0]:477 2.254748e-05 +95 chanx_right_in[10]:22 prog_clk[0]:463 9.272244e-08 +96 chanx_right_in[10]:22 prog_clk[0]:636 1.653162e-06 +97 chanx_right_in[10]:22 prog_clk[0]:462 9.272244e-08 +98 chanx_right_in[10]:22 prog_clk[0]:633 1.681678e-07 +99 chanx_right_in[10]:21 prog_clk[0]:463 9.272244e-08 +100 chanx_right_in[10]:21 prog_clk[0]:459 9.272244e-08 +101 chanx_right_in[10]:21 prog_clk[0]:628 1.681678e-07 +102 chanx_right_in[10]:21 prog_clk[0]:633 1.653162e-06 +103 chanx_right_in[10]:28 prog_clk[0]:217 0.000204618 +104 chanx_right_in[10]:28 prog_clk[0]:213 2.36024e-06 +105 chanx_right_in[10]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.0002513286 +106 chanx_right_in[10]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 0.0002513286 +107 chanx_right_in[10]:24 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.569924e-05 +108 chanx_right_in[10]:25 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.000111104 +109 chanx_right_in[10]:26 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.000111104 +110 chanx_right_in[10]:23 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 1.569924e-05 +111 chanx_right_in[10]:19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.838833e-05 +112 chanx_right_in[10]:18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.093875e-05 +113 chanx_right_in[10]:17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 1.093875e-05 +114 chanx_right_in[10]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.7264e-05 +115 chanx_right_in[10]:20 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.838833e-05 +116 chanx_right_in[10]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.7264e-05 +117 chanx_right_in[10]:35 ropt_net_220:4 6.099857e-05 +118 chanx_right_in[10]:36 ropt_net_220:5 6.099857e-05 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:37 0.0009591917 +1 chanx_right_in[10]:14 chanx_right_in[10]:13 0.0045 +2 chanx_right_in[10]:13 chanx_right_in[10]:12 0.000515625 +3 chanx_right_in[10]:12 chanx_right_in[10]:11 0.00341 +4 chanx_right_in[10]:11 chanx_right_in[10]:10 0.001366917 +5 chanx_right_in[10]:9 chanx_right_in[10]:8 0.02358706 +6 chanx_right_in[10]:10 chanx_right_in[10]:9 0.00341 +7 chanx_right_in[10]:7 chanx_right_in[10]:6 0.001158482 +8 chanx_right_in[10]:8 chanx_right_in[10]:7 0.0045 +9 chanx_right_in[10]:6 FTB_20__19:A 0.152 +10 chanx_right_in[10]:35 chanx_right_in[10]:34 0.00341 +11 chanx_right_in[10]:34 chanx_right_in[10]:33 0.005692091 +12 chanx_right_in[10]:36 chanx_right_in[10]:35 0.01021875 +13 chanx_right_in[10]:37 chanx_right_in[10]:36 0.00341 +14 chanx_right_in[10]:19 chanx_right_in[10]:18 0.0045 +15 chanx_right_in[10]:19 chanx_right_in[10]:14 0.005299107 +16 chanx_right_in[10]:18 chanx_right_in[10]:17 0.004473215 +17 chanx_right_in[10]:16 chanx_right_in[10]:15 0.000421875 +18 chanx_right_in[10]:17 chanx_right_in[10]:16 0.0045 +19 chanx_right_in[10]:15 mux_left_track_33\/mux_l1_in_1_:A1 0.152 +20 chanx_right_in[10]:5 mux_bottom_track_33\/mux_l1_in_0_:A0 0.152 +21 chanx_right_in[10]:24 chanx_right_in[10]:23 0.00940625 +22 chanx_right_in[10]:25 chanx_right_in[10]:24 0.0045 +23 chanx_right_in[10]:26 chanx_right_in[10]:25 0.004462054 +24 chanx_right_in[10]:27 chanx_right_in[10]:26 0.00341 +25 chanx_right_in[10]:32 chanx_right_in[10]:31 0.004765625 +26 chanx_right_in[10]:33 chanx_right_in[10]:32 0.00341 +27 chanx_right_in[10]:33 chanx_right_in[10]:28 0.00163325 +28 chanx_right_in[10]:30 chanx_right_in[10]:29 0.01157812 +29 chanx_right_in[10]:31 chanx_right_in[10]:30 0.0045 +30 chanx_right_in[10]:29 mux_top_track_32\/mux_l1_in_1_:A0 0.152 +31 chanx_right_in[10]:23 chanx_right_in[10]:22 0.0045 +32 chanx_right_in[10]:23 chanx_right_in[10]:5 0.001350446 +33 chanx_right_in[10]:22 chanx_right_in[10]:21 0.009330358 +34 chanx_right_in[10]:20 chanx_right_in[10]:19 0.002013393 +35 chanx_right_in[10]:21 chanx_right_in[10]:20 0.0045 +36 chanx_right_in[10]:28 chanx_right_in[10]:27 0.007806308 + +*END + +*D_NET chanx_right_in[12] 0.02905968 //LENGTH 182.200 LUMPCC 0.01143137 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 140.450 96.560 +*I mux_top_track_0\/mux_l1_in_3_:A1 I *L 0.00198 *C 84.640 96.220 +*I mux_left_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 79.580 85.340 +*I mux_bottom_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 84.780 59.160 +*I FTB_21__20:A I *L 0.001767 *C 14.260 99.280 +*N chanx_right_in[12]:5 *C 14.260 99.280 +*N chanx_right_in[12]:6 *C 14.260 98.940 +*N chanx_right_in[12]:7 *C 12.465 98.940 +*N chanx_right_in[12]:8 *C 12.420 98.895 +*N chanx_right_in[12]:9 *C 12.420 96.618 +*N chanx_right_in[12]:10 *C 12.428 96.560 +*N chanx_right_in[12]:11 *C 62.255 96.560 +*N chanx_right_in[12]:12 *C 84.743 59.160 +*N chanx_right_in[12]:13 *C 83.765 59.160 +*N chanx_right_in[12]:14 *C 83.720 59.205 +*N chanx_right_in[12]:15 *C 83.720 78.880 +*N chanx_right_in[12]:16 *C 83.260 78.880 +*N chanx_right_in[12]:17 *C 79.618 85.340 +*N chanx_right_in[12]:18 *C 81.420 85.340 +*N chanx_right_in[12]:19 *C 81.420 85.680 +*N chanx_right_in[12]:20 *C 83.215 85.680 +*N chanx_right_in[12]:21 *C 83.260 85.680 +*N chanx_right_in[12]:22 *C 83.260 96.502 +*N chanx_right_in[12]:23 *C 83.260 96.560 +*N chanx_right_in[12]:24 *C 84.640 96.205 +*N chanx_right_in[12]:25 *C 84.640 95.880 +*N chanx_right_in[12]:26 *C 84.640 95.925 +*N chanx_right_in[12]:27 *C 84.640 96.502 +*N chanx_right_in[12]:28 *C 84.640 96.568 +*N chanx_right_in[12]:29 *C 84.640 97.240 +*N chanx_right_in[12]:30 *C 94.300 97.240 +*N chanx_right_in[12]:31 *C 94.300 96.560 + +*CAP +0 chanx_right_in[12] 0.001770461 +1 mux_top_track_0\/mux_l1_in_3_:A1 1e-06 +2 mux_left_track_1\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_1\/mux_l1_in_1_:A0 1e-06 +4 FTB_21__20:A 1e-06 +5 chanx_right_in[12]:5 5.366064e-05 +6 chanx_right_in[12]:6 0.0001591373 +7 chanx_right_in[12]:7 0.0001327598 +8 chanx_right_in[12]:8 0.0001455827 +9 chanx_right_in[12]:9 0.0001455827 +10 chanx_right_in[12]:10 0.00225945 +11 chanx_right_in[12]:11 0.0037357 +12 chanx_right_in[12]:12 8.238688e-05 +13 chanx_right_in[12]:13 8.238688e-05 +14 chanx_right_in[12]:14 0.001030259 +15 chanx_right_in[12]:15 0.001035959 +16 chanx_right_in[12]:16 0.0003200505 +17 chanx_right_in[12]:17 0.0001423972 +18 chanx_right_in[12]:18 0.0001708541 +19 chanx_right_in[12]:19 0.0001607567 +20 chanx_right_in[12]:20 0.0001322998 +21 chanx_right_in[12]:21 0.0006788831 +22 chanx_right_in[12]:22 0.0003314433 +23 chanx_right_in[12]:23 0.001546829 +24 chanx_right_in[12]:24 4.025302e-05 +25 chanx_right_in[12]:25 7.766154e-05 +26 chanx_right_in[12]:26 5.332076e-05 +27 chanx_right_in[12]:27 5.332076e-05 +28 chanx_right_in[12]:28 0.0001019396 +29 chanx_right_in[12]:29 0.0006686332 +30 chanx_right_in[12]:30 0.00068958 +31 chanx_right_in[12]:31 0.001822768 +32 chanx_right_in[12] chanx_right_in[4] 1.018085e-05 +33 chanx_right_in[12] chanx_right_in[4]:30 0.0004897476 +34 chanx_right_in[12]:31 chanx_right_in[4]:29 0.0004897476 +35 chanx_right_in[12]:31 chanx_right_in[4]:35 1.018085e-05 +36 chanx_right_in[12] chanx_right_in[5]:30 4.019818e-06 +37 chanx_right_in[12] chanx_right_in[5]:34 0.001055936 +38 chanx_right_in[12]:23 chanx_right_in[5]:28 1.386688e-06 +39 chanx_right_in[12]:23 chanx_right_in[5]:29 4.163569e-06 +40 chanx_right_in[12]:28 chanx_right_in[5]:29 1.386688e-06 +41 chanx_right_in[12]:29 chanx_right_in[5]:28 2.960649e-06 +42 chanx_right_in[12]:29 chanx_right_in[5]:29 1.106917e-07 +43 chanx_right_in[12]:30 chanx_right_in[5]:29 2.960649e-06 +44 chanx_right_in[12]:30 chanx_right_in[5]:30 1.106917e-07 +45 chanx_right_in[12]:31 chanx_right_in[5]:29 4.019818e-06 +46 chanx_right_in[12]:31 chanx_right_in[5]:33 0.001055936 +47 chanx_right_in[12]:11 chanx_right_in[5]:28 4.163569e-06 +48 chanx_right_in[12] chany_bottom_in[2]:31 3.552847e-05 +49 chanx_right_in[12]:22 chany_bottom_in[2]:17 0.0001881363 +50 chanx_right_in[12]:27 chany_bottom_in[2]:23 2.432016e-05 +51 chanx_right_in[12]:28 chany_bottom_in[2]:23 6.91472e-06 +52 chanx_right_in[12]:28 chany_bottom_in[2]:20 1.174669e-05 +53 chanx_right_in[12]:26 chany_bottom_in[2]:20 2.432016e-05 +54 chanx_right_in[12]:20 chany_bottom_in[2]:15 1.951272e-05 +55 chanx_right_in[12]:21 chany_bottom_in[2]:16 0.0001881363 +56 chanx_right_in[12]:17 chany_bottom_in[2]:14 4.48762e-06 +57 chanx_right_in[12]:18 chany_bottom_in[2]:15 4.48762e-06 +58 chanx_right_in[12]:19 chany_bottom_in[2]:14 1.951272e-05 +59 chanx_right_in[12]:29 chany_bottom_in[2]:30 6.750648e-05 +60 chanx_right_in[12]:29 chany_bottom_in[2]:23 1.174669e-05 +61 chanx_right_in[12]:29 chany_bottom_in[2]:24 6.91472e-06 +62 chanx_right_in[12]:30 chany_bottom_in[2]:31 6.750648e-05 +63 chanx_right_in[12]:30 chany_bottom_in[2]:32 6.211303e-06 +64 chanx_right_in[12]:31 chany_bottom_in[2]:30 3.552847e-05 +65 chanx_right_in[12]:31 chany_bottom_in[2]:33 6.211303e-06 +66 chanx_right_in[12]:23 chanx_left_in[12]:27 0.0002231245 +67 chanx_right_in[12]:23 chanx_left_in[12]:32 7.906854e-05 +68 chanx_right_in[12]:23 chanx_left_in[12]:35 4.192278e-05 +69 chanx_right_in[12]:28 chanx_left_in[12]:26 6.733032e-06 +70 chanx_right_in[12]:28 chanx_left_in[12]:27 7.906854e-05 +71 chanx_right_in[12]:10 chanx_left_in[12]:37 7.629396e-05 +72 chanx_right_in[12]:10 chanx_left_in[12]:36 7.66038e-06 +73 chanx_right_in[12]:29 chanx_left_in[12]:25 6.733032e-06 +74 chanx_right_in[12]:29 chanx_left_in[12]:32 2.943618e-05 +75 chanx_right_in[12]:30 chanx_left_in[12]:27 2.943618e-05 +76 chanx_right_in[12]:11 chanx_left_in[12]:32 0.0002231245 +77 chanx_right_in[12]:11 chanx_left_in[12]:35 7.66038e-06 +78 chanx_right_in[12]:11 chanx_left_in[12]:36 0.0001182167 +79 chanx_right_in[12]:13 mux_tree_tapbuf_size10_4_sram[0]:12 2.791096e-05 +80 chanx_right_in[12]:14 mux_tree_tapbuf_size10_4_sram[0]:10 0.0001470837 +81 chanx_right_in[12]:14 mux_tree_tapbuf_size10_4_sram[0]:18 6.47749e-05 +82 chanx_right_in[12]:14 mux_tree_tapbuf_size10_4_sram[0]:14 5.100152e-05 +83 chanx_right_in[12]:12 mux_tree_tapbuf_size10_4_sram[0]:13 2.791096e-05 +84 chanx_right_in[12]:15 mux_tree_tapbuf_size10_4_sram[0]:10 5.669545e-05 +85 chanx_right_in[12]:15 mux_tree_tapbuf_size10_4_sram[0]:17 5.908097e-05 +86 chanx_right_in[12]:15 mux_tree_tapbuf_size10_4_sram[0]:7 0.0001470837 +87 chanx_right_in[12]:22 mux_tree_tapbuf_size12_2_sram[0]:19 0.0002751062 +88 chanx_right_in[12]:28 mux_tree_tapbuf_size12_2_sram[0]:16 1.825705e-05 +89 chanx_right_in[12]:21 mux_tree_tapbuf_size12_2_sram[0]:16 0.0002751062 +90 chanx_right_in[12]:21 mux_tree_tapbuf_size12_2_sram[0]:19 0.0001430122 +91 chanx_right_in[12]:16 mux_tree_tapbuf_size12_2_sram[0]:16 0.0001430122 +92 chanx_right_in[12]:16 mux_tree_tapbuf_size12_2_sram[0]:14 2.869147e-05 +93 chanx_right_in[12]:15 mux_tree_tapbuf_size12_2_sram[0]:15 2.869147e-05 +94 chanx_right_in[12]:29 mux_tree_tapbuf_size12_2_sram[0]:19 1.825705e-05 +95 chanx_right_in[12] mux_tree_tapbuf_size12_3_sram[0]:27 0.0005359435 +96 chanx_right_in[12]:29 mux_tree_tapbuf_size12_3_sram[0]:25 8.844846e-05 +97 chanx_right_in[12]:29 mux_tree_tapbuf_size12_3_sram[0]:26 1.702493e-05 +98 chanx_right_in[12]:30 mux_tree_tapbuf_size12_3_sram[0]:27 1.702493e-05 +99 chanx_right_in[12]:30 mux_tree_tapbuf_size12_3_sram[0]:18 7.916623e-07 +100 chanx_right_in[12]:30 mux_tree_tapbuf_size12_3_sram[0]:26 8.844846e-05 +101 chanx_right_in[12]:31 mux_tree_tapbuf_size12_3_sram[0]:26 0.0005367352 +102 chanx_right_in[12]:10 mux_tree_tapbuf_size12_7_sram[1]:27 0.00118794 +103 chanx_right_in[12]:11 mux_tree_tapbuf_size12_7_sram[1]:26 0.00118794 +104 chanx_right_in[12]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001500628 +105 chanx_right_in[12]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001500628 +106 chanx_right_in[12]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0005825261 +107 chanx_right_in[12]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0005825261 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:31 0.007230166 +1 chanx_right_in[12]:22 chanx_right_in[12]:21 0.009662947 +2 chanx_right_in[12]:23 chanx_right_in[12]:22 0.00341 +3 chanx_right_in[12]:23 chanx_right_in[12]:11 0.003290783 +4 chanx_right_in[12]:13 chanx_right_in[12]:12 0.0008727679 +5 chanx_right_in[12]:14 chanx_right_in[12]:13 0.0045 +6 chanx_right_in[12]:12 mux_bottom_track_1\/mux_l1_in_1_:A0 0.152 +7 chanx_right_in[12]:27 chanx_right_in[12]:26 0.000515625 +8 chanx_right_in[12]:28 chanx_right_in[12]:27 0.00341 +9 chanx_right_in[12]:28 chanx_right_in[12]:23 0.0002162 +10 chanx_right_in[12]:25 chanx_right_in[12]:24 0.0001766304 +11 chanx_right_in[12]:26 chanx_right_in[12]:25 0.0045 +12 chanx_right_in[12]:24 mux_top_track_0\/mux_l1_in_3_:A1 0.152 +13 chanx_right_in[12]:20 chanx_right_in[12]:19 0.001602679 +14 chanx_right_in[12]:21 chanx_right_in[12]:20 0.0045 +15 chanx_right_in[12]:21 chanx_right_in[12]:16 0.006071429 +16 chanx_right_in[12]:17 mux_left_track_1\/mux_l1_in_2_:A1 0.152 +17 chanx_right_in[12]:9 chanx_right_in[12]:8 0.002033482 +18 chanx_right_in[12]:10 chanx_right_in[12]:9 0.00341 +19 chanx_right_in[12]:7 chanx_right_in[12]:6 0.001602679 +20 chanx_right_in[12]:8 chanx_right_in[12]:7 0.0045 +21 chanx_right_in[12]:5 FTB_21__20:A 0.152 +22 chanx_right_in[12]:6 chanx_right_in[12]:5 0.0003035715 +23 chanx_right_in[12]:18 chanx_right_in[12]:17 0.001609375 +24 chanx_right_in[12]:19 chanx_right_in[12]:18 0.0003035715 +25 chanx_right_in[12]:16 chanx_right_in[12]:15 0.0004107143 +26 chanx_right_in[12]:15 chanx_right_in[12]:14 0.01756696 +27 chanx_right_in[12]:29 chanx_right_in[12]:28 0.0001053583 +28 chanx_right_in[12]:30 chanx_right_in[12]:29 0.0015134 +29 chanx_right_in[12]:31 chanx_right_in[12]:30 0.0001065333 +30 chanx_right_in[12]:11 chanx_right_in[12]:10 0.007806308 + +*END + +*D_NET chanx_right_in[13] 0.03971062 //LENGTH 243.262 LUMPCC 0.01968802 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 140.450 32.640 +*I mux_bottom_track_3\/mux_l1_in_2_:A1 I *L 0.00198 *C 62.465 25.500 +*I mux_top_track_2\/mux_l1_in_3_:A1 I *L 0.00198 *C 63.020 90.780 +*I mux_left_track_3\/mux_l1_in_2_:A1 I *L 0.00198 *C 59.705 88.740 +*I ropt_mt_inst_798:A I *L 0.001767 *C 3.220 55.760 +*N chanx_right_in[13]:5 *C 3.183 55.760 +*N chanx_right_in[13]:6 *C 1.425 55.760 +*N chanx_right_in[13]:7 *C 1.380 55.715 +*N chanx_right_in[13]:8 *C 1.380 54.400 +*N chanx_right_in[13]:9 *C 2.300 54.400 +*N chanx_right_in[13]:10 *C 2.300 41.865 +*N chanx_right_in[13]:11 *C 2.345 41.820 +*N chanx_right_in[13]:12 *C 11.915 41.820 +*N chanx_right_in[13]:13 *C 11.960 41.865 +*N chanx_right_in[13]:14 *C 11.960 42.782 +*N chanx_right_in[13]:15 *C 11.968 42.840 +*N chanx_right_in[13]:16 *C 59.742 88.740 +*N chanx_right_in[13]:17 *C 60.675 88.740 +*N chanx_right_in[13]:18 *C 60.720 88.785 +*N chanx_right_in[13]:19 *C 63.020 90.780 +*N chanx_right_in[13]:20 *C 63.020 90.440 +*N chanx_right_in[13]:21 *C 60.765 90.440 +*N chanx_right_in[13]:22 *C 60.720 90.440 +*N chanx_right_in[13]:23 *C 60.713 90.440 +*N chanx_right_in[13]:24 *C 49.700 90.440 +*N chanx_right_in[13]:25 *C 49.680 90.433 +*N chanx_right_in[13]:26 *C 49.680 42.848 +*N chanx_right_in[13]:27 *C 49.680 42.840 +*N chanx_right_in[13]:28 *C 63.013 42.840 +*N chanx_right_in[13]:29 *C 63.020 42.782 +*N chanx_right_in[13]:30 *C 62.503 25.500 +*N chanx_right_in[13]:31 *C 62.975 25.500 +*N chanx_right_in[13]:32 *C 63.020 25.545 +*N chanx_right_in[13]:33 *C 63.020 31.960 +*N chanx_right_in[13]:34 *C 63.028 31.960 +*N chanx_right_in[13]:35 *C 112.855 31.960 +*N chanx_right_in[13]:36 *C 138.920 31.960 +*N chanx_right_in[13]:37 *C 138.920 32.640 + +*CAP +0 chanx_right_in[13] 3.019625e-05 +1 mux_bottom_track_3\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_3_:A1 1e-06 +3 mux_left_track_3\/mux_l1_in_2_:A1 1e-06 +4 ropt_mt_inst_798:A 1e-06 +5 chanx_right_in[13]:5 0.0001184152 +6 chanx_right_in[13]:6 0.0001184152 +7 chanx_right_in[13]:7 8.166914e-05 +8 chanx_right_in[13]:8 0.0001343135 +9 chanx_right_in[13]:9 0.0007191997 +10 chanx_right_in[13]:10 0.0006665554 +11 chanx_right_in[13]:11 0.0004650132 +12 chanx_right_in[13]:12 0.0004650132 +13 chanx_right_in[13]:13 6.775099e-05 +14 chanx_right_in[13]:14 6.775099e-05 +15 chanx_right_in[13]:15 0.00112005 +16 chanx_right_in[13]:16 6.595846e-05 +17 chanx_right_in[13]:17 6.595846e-05 +18 chanx_right_in[13]:18 7.213542e-05 +19 chanx_right_in[13]:19 6.238016e-05 +20 chanx_right_in[13]:20 0.0001998825 +21 chanx_right_in[13]:21 0.0001693987 +22 chanx_right_in[13]:22 0.0001093145 +23 chanx_right_in[13]:23 0.0008727243 +24 chanx_right_in[13]:24 0.0008727243 +25 chanx_right_in[13]:25 0.002209651 +26 chanx_right_in[13]:26 0.002209651 +27 chanx_right_in[13]:27 0.001846316 +28 chanx_right_in[13]:28 0.0007262672 +29 chanx_right_in[13]:29 0.0006081403 +30 chanx_right_in[13]:30 6.359539e-05 +31 chanx_right_in[13]:31 6.359539e-05 +32 chanx_right_in[13]:32 0.0004208891 +33 chanx_right_in[13]:33 0.001066933 +34 chanx_right_in[13]:34 0.001657011 +35 chanx_right_in[13]:35 0.002070898 +36 chanx_right_in[13]:36 0.0004572578 +37 chanx_right_in[13]:37 7.356751e-05 +38 chanx_right_in[13]:17 chany_top_in[5]:7 1.709282e-05 +39 chanx_right_in[13]:17 chany_top_in[5]:32 1.929834e-05 +40 chanx_right_in[13]:18 chany_top_in[5]:33 3.69297e-05 +41 chanx_right_in[13]:16 chany_top_in[5]:31 1.929834e-05 +42 chanx_right_in[13]:16 chany_top_in[5]:32 1.709282e-05 +43 chanx_right_in[13]:22 chany_top_in[5] 3.69297e-05 +44 chanx_right_in[13]:25 chany_top_in[5]:25 0.0004947767 +45 chanx_right_in[13]:26 chany_top_in[5]:24 0.0004947767 +46 chanx_right_in[13] chanx_right_in[17] 4.943007e-05 +47 chanx_right_in[13]:33 chanx_right_in[17]:23 3.827572e-06 +48 chanx_right_in[13]:33 chanx_right_in[17]:22 2.148792e-05 +49 chanx_right_in[13]:34 chanx_right_in[17]:24 0.0006232625 +50 chanx_right_in[13]:34 chanx_right_in[17]:26 0.0002275048 +51 chanx_right_in[13]:29 chanx_right_in[17]:22 3.827572e-06 +52 chanx_right_in[13]:29 chanx_right_in[17]:20 2.148792e-05 +53 chanx_right_in[13]:36 chanx_right_in[17] 0.0004537681 +54 chanx_right_in[13]:37 chanx_right_in[17]:26 4.943007e-05 +55 chanx_right_in[13]:35 chanx_right_in[17] 0.0002275048 +56 chanx_right_in[13]:35 chanx_right_in[17]:25 0.0006232625 +57 chanx_right_in[13]:35 chanx_right_in[17]:26 0.0004537681 +58 chanx_right_in[13]:15 chanx_left_in[8]:27 1.466897e-05 +59 chanx_right_in[13]:15 chanx_left_in[8]:37 0.00059773 +60 chanx_right_in[13]:28 chanx_left_in[8]:26 0.0002019436 +61 chanx_right_in[13]:27 chanx_left_in[8]:36 0.00059773 +62 chanx_right_in[13]:27 chanx_left_in[8]:27 0.0002019436 +63 chanx_right_in[13]:27 chanx_left_in[8]:26 1.466897e-05 +64 chanx_right_in[13] chanx_right_in[19] 4.390141e-05 +65 chanx_right_in[13]:34 chanx_right_in[19]:18 0.002543444 +66 chanx_right_in[13]:34 chanx_right_in[19]:19 0.000134247 +67 chanx_right_in[13]:36 chanx_right_in[19] 0.001514567 +68 chanx_right_in[13]:37 chanx_right_in[19]:19 4.390141e-05 +69 chanx_right_in[13]:35 chanx_right_in[19] 0.000134247 +70 chanx_right_in[13]:35 chanx_right_in[19]:19 0.004058011 +71 chanx_right_in[13]:25 chany_bottom_in[15]:9 4.16058e-05 +72 chanx_right_in[13]:25 chany_bottom_in[15]:18 0.000405652 +73 chanx_right_in[13]:25 chany_bottom_in[15]:19 0.0001659648 +74 chanx_right_in[13]:26 chany_bottom_in[15]:20 0.0001659648 +75 chanx_right_in[13]:26 chany_bottom_in[15]:18 4.16058e-05 +76 chanx_right_in[13]:26 chany_bottom_in[15]:19 0.000405652 +77 chanx_right_in[13]:15 chanx_left_in[7] 0.0009610616 +78 chanx_right_in[13]:12 chanx_left_in[7]:14 6.735513e-06 +79 chanx_right_in[13]:11 chanx_left_in[7] 6.735513e-06 +80 chanx_right_in[13]:27 chanx_left_in[7]:14 0.0009610616 +81 chanx_right_in[13]:15 mux_tree_tapbuf_size10_8_sram[1]:31 7.689642e-05 +82 chanx_right_in[13]:28 mux_tree_tapbuf_size10_8_sram[1]:32 0.0002510295 +83 chanx_right_in[13]:27 mux_tree_tapbuf_size10_8_sram[1]:32 7.689642e-05 +84 chanx_right_in[13]:27 mux_tree_tapbuf_size10_8_sram[1]:31 0.0002510295 +85 chanx_right_in[13]:15 optlc_net_147:29 0.000788347 +86 chanx_right_in[13]:27 optlc_net_147:28 0.000788347 +87 chanx_right_in[13]:12 ropt_net_217:3 0.0001488388 +88 chanx_right_in[13]:11 ropt_net_217:2 0.0001488388 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:37 0.0002397 +1 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0008191965 +2 chanx_right_in[13]:15 chanx_right_in[13]:14 0.00341 +3 chanx_right_in[13]:12 chanx_right_in[13]:11 0.008544643 +4 chanx_right_in[13]:13 chanx_right_in[13]:12 0.0045 +5 chanx_right_in[13]:11 chanx_right_in[13]:10 0.0045 +6 chanx_right_in[13]:10 chanx_right_in[13]:9 0.01119196 +7 chanx_right_in[13]:6 chanx_right_in[13]:5 0.001569197 +8 chanx_right_in[13]:7 chanx_right_in[13]:6 0.0045 +9 chanx_right_in[13]:5 ropt_mt_inst_798:A 0.152 +10 chanx_right_in[13]:33 chanx_right_in[13]:32 0.005727679 +11 chanx_right_in[13]:33 chanx_right_in[13]:29 0.009662947 +12 chanx_right_in[13]:34 chanx_right_in[13]:33 0.00341 +13 chanx_right_in[13]:31 chanx_right_in[13]:30 0.000421875 +14 chanx_right_in[13]:32 chanx_right_in[13]:31 0.0045 +15 chanx_right_in[13]:30 mux_bottom_track_3\/mux_l1_in_2_:A1 0.152 +16 chanx_right_in[13]:29 chanx_right_in[13]:28 0.00341 +17 chanx_right_in[13]:28 chanx_right_in[13]:27 0.002088758 +18 chanx_right_in[13]:17 chanx_right_in[13]:16 0.0008325893 +19 chanx_right_in[13]:18 chanx_right_in[13]:17 0.0045 +20 chanx_right_in[13]:16 mux_left_track_3\/mux_l1_in_2_:A1 0.152 +21 chanx_right_in[13]:21 chanx_right_in[13]:20 0.002013393 +22 chanx_right_in[13]:22 chanx_right_in[13]:21 0.0045 +23 chanx_right_in[13]:22 chanx_right_in[13]:18 0.001477679 +24 chanx_right_in[13]:19 mux_top_track_2\/mux_l1_in_3_:A1 0.152 +25 chanx_right_in[13]:23 chanx_right_in[13]:22 0.00341 +26 chanx_right_in[13]:24 chanx_right_in[13]:23 0.001725292 +27 chanx_right_in[13]:25 chanx_right_in[13]:24 0.00341 +28 chanx_right_in[13]:27 chanx_right_in[13]:26 0.00341 +29 chanx_right_in[13]:27 chanx_right_in[13]:15 0.005908291 +30 chanx_right_in[13]:26 chanx_right_in[13]:25 0.007454983 +31 chanx_right_in[13]:20 chanx_right_in[13]:19 0.0003035714 +32 chanx_right_in[13]:8 chanx_right_in[13]:7 0.001174107 +33 chanx_right_in[13]:9 chanx_right_in[13]:8 0.0008214285 +34 chanx_right_in[13]:36 chanx_right_in[13]:35 0.004083517 +35 chanx_right_in[13]:37 chanx_right_in[13]:36 0.0001065333 +36 chanx_right_in[13]:35 chanx_right_in[13]:34 0.007806307 + +*END + +*D_NET chanx_right_in[14] 0.03024283 //LENGTH 194.550 LUMPCC 0.01107439 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 140.450 91.120 +*I mux_left_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 41.705 88.060 +*I mux_bottom_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 36.975 39.100 +*I BUFT_P_120:A I *L 0.001776 *C 11.960 39.440 +*I mux_top_track_4\/mux_l2_in_4_:A0 I *L 0.001631 *C 38.355 86.020 +*N chanx_right_in[14]:5 *C 38.355 86.020 +*N chanx_right_in[14]:6 *C 11.923 39.440 +*N chanx_right_in[14]:7 *C 11.545 39.440 +*N chanx_right_in[14]:8 *C 11.500 39.440 +*N chanx_right_in[14]:9 *C 11.508 39.440 +*N chanx_right_in[14]:10 *C 36.975 39.100 +*N chanx_right_in[14]:11 *C 36.800 39.100 +*N chanx_right_in[14]:12 *C 36.800 39.100 +*N chanx_right_in[14]:13 *C 36.800 39.440 +*N chanx_right_in[14]:14 *C 36.800 39.440 +*N chanx_right_in[14]:15 *C 38.633 39.440 +*N chanx_right_in[14]:16 *C 38.640 39.498 +*N chanx_right_in[14]:17 *C 38.640 85.975 +*N chanx_right_in[14]:18 *C 38.685 86.020 +*N chanx_right_in[14]:19 *C 40.435 86.020 +*N chanx_right_in[14]:20 *C 40.480 86.065 +*N chanx_right_in[14]:21 *C 41.668 88.060 +*N chanx_right_in[14]:22 *C 40.525 88.060 +*N chanx_right_in[14]:23 *C 40.480 88.060 +*N chanx_right_in[14]:24 *C 40.480 91.743 +*N chanx_right_in[14]:25 *C 40.488 91.800 +*N chanx_right_in[14]:26 *C 62.553 91.800 +*N chanx_right_in[14]:27 *C 62.560 91.743 +*N chanx_right_in[14]:28 *C 62.560 91.165 +*N chanx_right_in[14]:29 *C 62.605 91.120 +*N chanx_right_in[14]:30 *C 67.620 91.120 +*N chanx_right_in[14]:31 *C 67.620 91.460 +*N chanx_right_in[14]:32 *C 70.840 91.460 +*N chanx_right_in[14]:33 *C 70.840 91.120 +*N chanx_right_in[14]:34 *C 78.155 91.120 +*N chanx_right_in[14]:35 *C 78.200 91.075 +*N chanx_right_in[14]:36 *C 78.200 89.818 +*N chanx_right_in[14]:37 *C 78.208 89.760 +*N chanx_right_in[14]:38 *C 92.000 89.760 +*N chanx_right_in[14]:39 *C 92.000 91.800 +*N chanx_right_in[14]:40 *C 131.560 91.800 +*N chanx_right_in[14]:41 *C 131.560 91.120 + +*CAP +0 chanx_right_in[14] 0.0005046736 +1 mux_left_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_5\/mux_l2_in_1_:A0 1e-06 +3 BUFT_P_120:A 1e-06 +4 mux_top_track_4\/mux_l2_in_4_:A0 1e-06 +5 chanx_right_in[14]:5 4.767887e-05 +6 chanx_right_in[14]:6 4.590491e-05 +7 chanx_right_in[14]:7 4.590491e-05 +8 chanx_right_in[14]:8 3.198096e-05 +9 chanx_right_in[14]:9 0.0009250168 +10 chanx_right_in[14]:10 4.990525e-05 +11 chanx_right_in[14]:11 5.20699e-05 +12 chanx_right_in[14]:12 5.196278e-05 +13 chanx_right_in[14]:13 5.58846e-05 +14 chanx_right_in[14]:14 0.001002507 +15 chanx_right_in[14]:15 7.749043e-05 +16 chanx_right_in[14]:16 0.002498027 +17 chanx_right_in[14]:17 0.002498027 +18 chanx_right_in[14]:18 0.000142289 +19 chanx_right_in[14]:19 0.000123407 +20 chanx_right_in[14]:20 8.694308e-05 +21 chanx_right_in[14]:21 0.0001087472 +22 chanx_right_in[14]:22 0.0001087472 +23 chanx_right_in[14]:23 0.0002761999 +24 chanx_right_in[14]:24 0.0001553824 +25 chanx_right_in[14]:25 0.001361001 +26 chanx_right_in[14]:26 0.001361001 +27 chanx_right_in[14]:27 5.68858e-05 +28 chanx_right_in[14]:28 5.68858e-05 +29 chanx_right_in[14]:29 0.0004104322 +30 chanx_right_in[14]:30 0.0004379185 +31 chanx_right_in[14]:31 0.0002658208 +32 chanx_right_in[14]:32 0.0002646612 +33 chanx_right_in[14]:33 0.0005424913 +34 chanx_right_in[14]:34 0.0005161646 +35 chanx_right_in[14]:35 0.0001219857 +36 chanx_right_in[14]:36 0.0001219857 +37 chanx_right_in[14]:37 0.0005679195 +38 chanx_right_in[14]:38 0.0006840184 +39 chanx_right_in[14]:39 0.001513242 +40 chanx_right_in[14]:40 0.001442872 +41 chanx_right_in[14]:41 0.0005504013 +42 chanx_right_in[14]:37 chany_top_in[18]:34 0.0004204595 +43 chanx_right_in[14]:38 chany_top_in[18]:8 0.0004204595 +44 chanx_right_in[14]:37 chany_bottom_in[13]:23 0.0006890473 +45 chanx_right_in[14]:37 chany_bottom_in[13]:19 8.574038e-06 +46 chanx_right_in[14]:38 chany_bottom_in[13]:22 0.0006890473 +47 chanx_right_in[14]:38 chany_bottom_in[13]:20 3.082961e-05 +48 chanx_right_in[14]:38 chany_bottom_in[13]:15 8.574038e-06 +49 chanx_right_in[14]:39 chany_bottom_in[13]:14 3.082961e-05 +50 chanx_right_in[14]:25 chanx_left_in[4]:27 9.027471e-05 +51 chanx_right_in[14]:26 chanx_left_in[4]:26 9.027471e-05 +52 chanx_right_in[14]:37 chanx_left_in[4]:27 2.618085e-06 +53 chanx_right_in[14]:38 chanx_left_in[4]:26 2.618085e-06 +54 chanx_right_in[14]:39 chanx_left_in[4]:27 0.0002592398 +55 chanx_right_in[14]:40 chanx_left_in[4]:26 0.0002592398 +56 chanx_right_in[14]:17 prog_clk[0]:454 2.444656e-05 +57 chanx_right_in[14]:17 prog_clk[0]:473 2.137312e-05 +58 chanx_right_in[14]:17 prog_clk[0]:469 5.605675e-05 +59 chanx_right_in[14]:17 prog_clk[0]:448 3.565887e-05 +60 chanx_right_in[14]:17 prog_clk[0]:440 1.948754e-05 +61 chanx_right_in[14]:16 prog_clk[0]:455 2.444656e-05 +62 chanx_right_in[14]:16 prog_clk[0]:451 3.565887e-05 +63 chanx_right_in[14]:16 prog_clk[0]:473 5.605675e-05 +64 chanx_right_in[14]:16 prog_clk[0]:472 2.137312e-05 +65 chanx_right_in[14]:16 prog_clk[0]:441 1.948754e-05 +66 chanx_right_in[14]:39 prog_clk[0]:253 0.0001294129 +67 chanx_right_in[14]:39 prog_clk[0]:252 4.247768e-05 +68 chanx_right_in[14]:39 prog_clk[0]:148 0.0001220043 +69 chanx_right_in[14]:40 prog_clk[0]:252 0.0001294129 +70 chanx_right_in[14]:40 prog_clk[0]:147 0.0001220043 +71 chanx_right_in[14]:40 prog_clk[0]:233 4.247768e-05 +72 chanx_right_in[14] right_top_grid_pin_45_[0]:16 5.51981e-05 +73 chanx_right_in[14]:39 right_top_grid_pin_45_[0]:15 0.0002307189 +74 chanx_right_in[14]:40 right_top_grid_pin_45_[0]:16 0.0002307189 +75 chanx_right_in[14]:41 right_top_grid_pin_45_[0]:15 5.51981e-05 +76 chanx_right_in[14]:9 chanx_left_in[1]:20 0.001437953 +77 chanx_right_in[14]:14 chanx_left_in[1]:20 0.0001130373 +78 chanx_right_in[14]:14 chanx_left_in[1]:19 0.001437953 +79 chanx_right_in[14]:15 chanx_left_in[1]:19 0.0001130373 +80 chanx_right_in[14]:25 chanx_left_in[19]:9 0.0005580803 +81 chanx_right_in[14]:26 chanx_left_in[19]:8 0.0005580803 +82 chanx_right_in[14] mux_tree_tapbuf_size12_0_sram[0]:41 2.03459e-05 +83 chanx_right_in[14]:38 mux_tree_tapbuf_size12_0_sram[0]:37 1.164795e-05 +84 chanx_right_in[14]:39 mux_tree_tapbuf_size12_0_sram[0]:36 1.164795e-05 +85 chanx_right_in[14]:39 mux_tree_tapbuf_size12_0_sram[0]:38 0.0004848115 +86 chanx_right_in[14]:39 mux_tree_tapbuf_size12_0_sram[0]:40 0.0001591935 +87 chanx_right_in[14]:40 mux_tree_tapbuf_size12_0_sram[0]:41 0.0001591935 +88 chanx_right_in[14]:40 mux_tree_tapbuf_size12_0_sram[0]:39 0.0004848115 +89 chanx_right_in[14]:41 mux_tree_tapbuf_size12_0_sram[0]:40 2.03459e-05 +90 chanx_right_in[14]:23 mux_tree_tapbuf_size16_0_sram[1]:24 9.860122e-05 +91 chanx_right_in[14]:23 mux_tree_tapbuf_size16_0_sram[1]:29 5.542402e-05 +92 chanx_right_in[14]:19 mux_tree_tapbuf_size16_0_sram[1]:18 6.244349e-06 +93 chanx_right_in[14]:20 mux_tree_tapbuf_size16_0_sram[1]:24 5.542402e-05 +94 chanx_right_in[14]:24 mux_tree_tapbuf_size16_0_sram[1]:29 9.860122e-05 +95 chanx_right_in[14]:18 mux_tree_tapbuf_size16_0_sram[1]:19 6.244349e-06 +96 chanx_right_in[14]:17 mux_tree_tapbuf_size16_0_sram[1]:29 1.144353e-07 +97 chanx_right_in[14]:17 mux_tree_tapbuf_size16_0_sram[1]:19 0.0001314064 +98 chanx_right_in[14]:16 mux_tree_tapbuf_size16_0_sram[1]:24 1.144353e-07 +99 chanx_right_in[14]:16 mux_tree_tapbuf_size16_0_sram[1]:20 0.0001314064 +100 chanx_right_in[14]:39 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002224594 +101 chanx_right_in[14]:40 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002224594 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:41 0.001392767 +1 chanx_right_in[14]:21 mux_left_track_5\/mux_l2_in_1_:A0 0.152 +2 chanx_right_in[14]:22 chanx_right_in[14]:21 0.001020089 +3 chanx_right_in[14]:23 chanx_right_in[14]:22 0.0045 +4 chanx_right_in[14]:23 chanx_right_in[14]:20 0.00178125 +5 chanx_right_in[14]:19 chanx_right_in[14]:18 0.0015625 +6 chanx_right_in[14]:20 chanx_right_in[14]:19 0.0045 +7 chanx_right_in[14]:8 chanx_right_in[14]:7 0.0045 +8 chanx_right_in[14]:9 chanx_right_in[14]:8 0.00341 +9 chanx_right_in[14]:7 chanx_right_in[14]:6 0.0003370536 +10 chanx_right_in[14]:6 BUFT_P_120:A 0.152 +11 chanx_right_in[14]:24 chanx_right_in[14]:23 0.003287947 +12 chanx_right_in[14]:25 chanx_right_in[14]:24 0.00341 +13 chanx_right_in[14]:27 chanx_right_in[14]:26 0.00341 +14 chanx_right_in[14]:26 chanx_right_in[14]:25 0.00345685 +15 chanx_right_in[14]:29 chanx_right_in[14]:28 0.0045 +16 chanx_right_in[14]:28 chanx_right_in[14]:27 0.000515625 +17 chanx_right_in[14]:34 chanx_right_in[14]:33 0.006531251 +18 chanx_right_in[14]:35 chanx_right_in[14]:34 0.0045 +19 chanx_right_in[14]:36 chanx_right_in[14]:35 0.001122768 +20 chanx_right_in[14]:37 chanx_right_in[14]:36 0.00341 +21 chanx_right_in[14]:13 chanx_right_in[14]:12 0.0001634616 +22 chanx_right_in[14]:14 chanx_right_in[14]:13 0.00341 +23 chanx_right_in[14]:14 chanx_right_in[14]:9 0.003962492 +24 chanx_right_in[14]:11 chanx_right_in[14]:10 9.51087e-05 +25 chanx_right_in[14]:12 chanx_right_in[14]:11 0.0045 +26 chanx_right_in[14]:10 mux_bottom_track_5\/mux_l2_in_1_:A0 0.152 +27 chanx_right_in[14]:5 mux_top_track_4\/mux_l2_in_4_:A0 0.152 +28 chanx_right_in[14]:18 chanx_right_in[14]:17 0.0045 +29 chanx_right_in[14]:18 chanx_right_in[14]:5 0.0001793478 +30 chanx_right_in[14]:17 chanx_right_in[14]:16 0.04149777 +31 chanx_right_in[14]:16 chanx_right_in[14]:15 0.00341 +32 chanx_right_in[14]:15 chanx_right_in[14]:14 0.0002870916 +33 chanx_right_in[14]:30 chanx_right_in[14]:29 0.004477679 +34 chanx_right_in[14]:31 chanx_right_in[14]:30 0.0003035714 +35 chanx_right_in[14]:32 chanx_right_in[14]:31 0.002875 +36 chanx_right_in[14]:33 chanx_right_in[14]:32 0.0003035715 +37 chanx_right_in[14]:38 chanx_right_in[14]:37 0.002160825 +38 chanx_right_in[14]:39 chanx_right_in[14]:38 0.0003196 +39 chanx_right_in[14]:40 chanx_right_in[14]:39 0.006197733 +40 chanx_right_in[14]:41 chanx_right_in[14]:40 0.0001065333 + +*END + +*D_NET chanx_right_in[18] 0.02520988 //LENGTH 167.723 LUMPCC 0.008316471 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 140.450 65.280 +*I BUFT_RR_89:A I *L 0.001776 *C 13.340 72.080 +*I mux_bottom_track_25\/mux_l1_in_2_:A1 I *L 0.00198 *C 54.280 45.220 +*I mux_top_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 60.895 60.860 +*I mux_left_track_25\/mux_l1_in_2_:A1 I *L 0.00198 *C 71.300 63.580 +*N chanx_right_in[18]:5 *C 71.300 63.565 +*N chanx_right_in[18]:6 *C 60.770 60.860 +*N chanx_right_in[18]:7 *C 54.303 45.248 +*N chanx_right_in[18]:8 *C 54.315 45.560 +*N chanx_right_in[18]:9 *C 58.375 45.560 +*N chanx_right_in[18]:10 *C 58.420 45.605 +*N chanx_right_in[18]:11 *C 58.420 60.815 +*N chanx_right_in[18]:12 *C 58.465 60.860 +*N chanx_right_in[18]:13 *C 60.675 60.860 +*N chanx_right_in[18]:14 *C 60.720 60.905 +*N chanx_right_in[18]:15 *C 13.303 72.080 +*N chanx_right_in[18]:16 *C 12.925 72.080 +*N chanx_right_in[18]:17 *C 12.880 72.035 +*N chanx_right_in[18]:18 *C 12.880 63.298 +*N chanx_right_in[18]:19 *C 12.888 63.240 +*N chanx_right_in[18]:20 *C 60.713 63.240 +*N chanx_right_in[18]:21 *C 60.720 63.240 +*N chanx_right_in[18]:22 *C 60.765 63.240 +*N chanx_right_in[18]:23 *C 71.300 63.240 +*N chanx_right_in[18]:24 *C 73.555 63.240 +*N chanx_right_in[18]:25 *C 73.600 63.285 +*N chanx_right_in[18]:26 *C 73.600 64.555 +*N chanx_right_in[18]:27 *C 73.645 64.600 +*N chanx_right_in[18]:28 *C 86.435 64.600 +*N chanx_right_in[18]:29 *C 86.480 64.645 +*N chanx_right_in[18]:30 *C 86.480 65.222 +*N chanx_right_in[18]:31 *C 86.487 65.280 + +*CAP +0 chanx_right_in[18] 0.002226393 +1 BUFT_RR_89:A 1e-06 +2 mux_bottom_track_25\/mux_l1_in_2_:A1 1e-06 +3 mux_top_track_24\/mux_l1_in_1_:A0 1e-06 +4 mux_left_track_25\/mux_l1_in_2_:A1 1e-06 +5 chanx_right_in[18]:5 3.45919e-05 +6 chanx_right_in[18]:6 2.772248e-05 +7 chanx_right_in[18]:7 3.337642e-05 +8 chanx_right_in[18]:8 0.0003064705 +9 chanx_right_in[18]:9 0.000273094 +10 chanx_right_in[18]:10 0.0008891248 +11 chanx_right_in[18]:11 0.0008891248 +12 chanx_right_in[18]:12 0.0001834241 +13 chanx_right_in[18]:13 0.0002111465 +14 chanx_right_in[18]:14 0.0001405235 +15 chanx_right_in[18]:15 4.182524e-05 +16 chanx_right_in[18]:16 4.182524e-05 +17 chanx_right_in[18]:17 0.0004200303 +18 chanx_right_in[18]:18 0.0004200303 +19 chanx_right_in[18]:19 0.002250955 +20 chanx_right_in[18]:20 0.002250955 +21 chanx_right_in[18]:21 0.0001786685 +22 chanx_right_in[18]:22 0.0008171728 +23 chanx_right_in[18]:23 0.001011768 +24 chanx_right_in[18]:24 0.0001600035 +25 chanx_right_in[18]:25 0.0001146555 +26 chanx_right_in[18]:26 0.0001146555 +27 chanx_right_in[18]:27 0.0007563743 +28 chanx_right_in[18]:28 0.0007563743 +29 chanx_right_in[18]:29 5.636699e-05 +30 chanx_right_in[18]:30 5.636699e-05 +31 chanx_right_in[18]:31 0.002226393 +32 chanx_right_in[18]:20 chany_bottom_in[18]:41 0.0003800541 +33 chanx_right_in[18]:20 chany_bottom_in[18]:37 0.0003033422 +34 chanx_right_in[18]:19 chany_bottom_in[18]:40 0.0003800541 +35 chanx_right_in[18]:19 chany_bottom_in[18]:36 0.0003033422 +36 chanx_right_in[18]:20 prog_clk[0]:465 3.902367e-05 +37 chanx_right_in[18]:20 prog_clk[0]:456 0.0001057615 +38 chanx_right_in[18]:20 prog_clk[0]:452 0.0001082803 +39 chanx_right_in[18]:20 prog_clk[0]:445 0.0005791106 +40 chanx_right_in[18]:20 prog_clk[0]:414 1.115989e-05 +41 chanx_right_in[18]:19 prog_clk[0]:465 0.0001057615 +42 chanx_right_in[18]:19 prog_clk[0]:464 3.902367e-05 +43 chanx_right_in[18]:19 prog_clk[0]:453 0.0001082803 +44 chanx_right_in[18]:19 prog_clk[0]:452 0.0005791106 +45 chanx_right_in[18]:19 prog_clk[0]:415 1.115989e-05 +46 chanx_right_in[18]:11 prog_clk[0]:309 1.442031e-06 +47 chanx_right_in[18]:10 prog_clk[0]:310 1.442031e-06 +48 chanx_right_in[18] right_top_grid_pin_47_[0]:8 0.0004791241 +49 chanx_right_in[18]:31 right_top_grid_pin_47_[0]:7 0.0004791241 +50 chanx_right_in[18]:21 chany_bottom_in[1]:16 3.945284e-08 +51 chanx_right_in[18]:20 chany_bottom_in[1]:9 0.0005179699 +52 chanx_right_in[18]:19 chany_bottom_in[1]:8 0.0005179699 +53 chanx_right_in[18]:14 chany_bottom_in[1]:17 3.945284e-08 +54 chanx_right_in[18]:27 chany_bottom_in[1]:11 0.0002357528 +55 chanx_right_in[18]:28 chany_bottom_in[1]:10 0.0002357528 +56 chanx_right_in[18] mux_tree_tapbuf_size10_3_sram[0]:22 0.0003623946 +57 chanx_right_in[18]:31 mux_tree_tapbuf_size10_3_sram[0]:21 0.0003623946 +58 chanx_right_in[18] mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0007152003 +59 chanx_right_in[18]:31 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0007152003 +60 chanx_right_in[18] mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001717148 +61 chanx_right_in[18]:31 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001717148 +62 chanx_right_in[18]:18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001434545 +63 chanx_right_in[18]:16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 4.411676e-06 +64 chanx_right_in[18]:17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001434545 +65 chanx_right_in[18]:15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 4.411676e-06 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:31 0.008454124 +1 chanx_right_in[18]:21 chanx_right_in[18]:20 0.00341 +2 chanx_right_in[18]:21 chanx_right_in[18]:14 0.002084821 +3 chanx_right_in[18]:20 chanx_right_in[18]:19 0.007492583 +4 chanx_right_in[18]:18 chanx_right_in[18]:17 0.00780134 +5 chanx_right_in[18]:19 chanx_right_in[18]:18 0.00341 +6 chanx_right_in[18]:16 chanx_right_in[18]:15 0.0003370536 +7 chanx_right_in[18]:17 chanx_right_in[18]:16 0.0045 +8 chanx_right_in[18]:15 BUFT_RR_89:A 0.152 +9 chanx_right_in[18]:12 chanx_right_in[18]:11 0.0045 +10 chanx_right_in[18]:11 chanx_right_in[18]:10 0.01358036 +11 chanx_right_in[18]:9 chanx_right_in[18]:8 0.003625 +12 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0045 +13 chanx_right_in[18]:7 mux_bottom_track_25\/mux_l1_in_2_:A1 0.152 +14 chanx_right_in[18]:13 chanx_right_in[18]:12 0.001973214 +15 chanx_right_in[18]:13 chanx_right_in[18]:6 8.482143e-05 +16 chanx_right_in[18]:14 chanx_right_in[18]:13 0.0045 +17 chanx_right_in[18]:22 chanx_right_in[18]:21 0.0045 +18 chanx_right_in[18]:5 mux_left_track_25\/mux_l1_in_2_:A1 0.152 +19 chanx_right_in[18]:6 mux_top_track_24\/mux_l1_in_1_:A0 0.152 +20 chanx_right_in[18]:24 chanx_right_in[18]:23 0.002013393 +21 chanx_right_in[18]:25 chanx_right_in[18]:24 0.0045 +22 chanx_right_in[18]:27 chanx_right_in[18]:26 0.0045 +23 chanx_right_in[18]:26 chanx_right_in[18]:25 0.001133929 +24 chanx_right_in[18]:28 chanx_right_in[18]:27 0.01141964 +25 chanx_right_in[18]:29 chanx_right_in[18]:28 0.0045 +26 chanx_right_in[18]:30 chanx_right_in[18]:29 0.000515625 +27 chanx_right_in[18]:31 chanx_right_in[18]:30 0.00341 +28 chanx_right_in[18]:8 chanx_right_in[18]:7 0.0002111487 +29 chanx_right_in[18]:23 chanx_right_in[18]:22 0.00940625 +30 chanx_right_in[18]:23 chanx_right_in[18]:5 0.0001766304 + +*END + +*D_NET chany_bottom_in[6] 0.02535006 //LENGTH 187.565 LUMPCC 0.006193115 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 94.300 1.290 +*I mux_left_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 49.510 71.740 +*I FTB_30__29:A I *L 0.001776 *C 51.980 118.320 +*I mux_top_track_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 94.475 53.380 +*I mux_right_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 108.220 60.520 +*N chany_bottom_in[6]:5 *C 108.183 60.520 +*N chany_bottom_in[6]:6 *C 104.925 60.520 +*N chany_bottom_in[6]:7 *C 104.880 60.475 +*N chany_bottom_in[6]:8 *C 104.880 53.425 +*N chany_bottom_in[6]:9 *C 104.835 53.380 +*N chany_bottom_in[6]:10 *C 94.475 53.380 +*N chany_bottom_in[6]:11 *C 93.885 53.380 +*N chany_bottom_in[6]:12 *C 93.840 53.380 +*N chany_bottom_in[6]:13 *C 51.980 118.320 +*N chany_bottom_in[6]:14 *C 51.980 117.980 +*N chany_bottom_in[6]:15 *C 51.565 117.980 +*N chany_bottom_in[6]:16 *C 51.520 117.935 +*N chany_bottom_in[6]:17 *C 49.547 71.740 +*N chany_bottom_in[6]:18 *C 51.475 71.740 +*N chany_bottom_in[6]:19 *C 51.520 71.740 +*N chany_bottom_in[6]:20 *C 51.520 56.485 +*N chany_bottom_in[6]:21 *C 51.565 56.440 +*N chany_bottom_in[6]:22 *C 79.995 56.440 +*N chany_bottom_in[6]:23 *C 80.040 56.395 +*N chany_bottom_in[6]:24 *C 80.040 53.098 +*N chany_bottom_in[6]:25 *C 80.047 53.040 +*N chany_bottom_in[6]:26 *C 93.833 53.040 +*N chany_bottom_in[6]:27 *C 93.840 52.983 +*N chany_bottom_in[6]:28 *C 93.840 2.040 +*N chany_bottom_in[6]:29 *C 94.300 2.040 + +*CAP +0 chany_bottom_in[6] 5.079173e-05 +1 mux_left_track_9\/mux_l2_in_1_:A0 1e-06 +2 FTB_30__29:A 1e-06 +3 mux_top_track_8\/mux_l1_in_2_:A0 1e-06 +4 mux_right_track_8\/mux_l2_in_1_:A0 1e-06 +5 chany_bottom_in[6]:5 0.0002682866 +6 chany_bottom_in[6]:6 0.0002682866 +7 chany_bottom_in[6]:7 0.0004051196 +8 chany_bottom_in[6]:8 0.0004051196 +9 chany_bottom_in[6]:9 0.0007444142 +10 chany_bottom_in[6]:10 0.000840583 +11 chany_bottom_in[6]:11 6.550447e-05 +12 chany_bottom_in[6]:12 4.764338e-05 +13 chany_bottom_in[6]:13 5.828742e-05 +14 chany_bottom_in[6]:14 7.922479e-05 +15 chany_bottom_in[6]:15 5.066733e-05 +16 chany_bottom_in[6]:16 0.001965619 +17 chany_bottom_in[6]:17 0.0001361467 +18 chany_bottom_in[6]:18 0.0001361467 +19 chany_bottom_in[6]:19 0.002895335 +20 chany_bottom_in[6]:20 0.0008955355 +21 chany_bottom_in[6]:21 0.001685503 +22 chany_bottom_in[6]:22 0.001685503 +23 chany_bottom_in[6]:23 8.63263e-05 +24 chany_bottom_in[6]:24 8.63263e-05 +25 chany_bottom_in[6]:25 0.0004738164 +26 chany_bottom_in[6]:26 0.0004738165 +27 chany_bottom_in[6]:27 0.00262841 +28 chany_bottom_in[6]:28 0.002641283 +29 chany_bottom_in[6]:29 7.924666e-05 +30 chany_bottom_in[6]:26 chanx_left_in[16]:35 0.0003947149 +31 chany_bottom_in[6]:26 chanx_left_in[16]:37 0.0001067369 +32 chany_bottom_in[6]:25 chanx_left_in[16]:38 0.0001067369 +33 chany_bottom_in[6]:25 chanx_left_in[16]:36 0.0003947149 +34 chany_bottom_in[6]:16 prog_clk[0]:426 7.98152e-05 +35 chany_bottom_in[6]:16 prog_clk[0]:429 6.121058e-05 +36 chany_bottom_in[6]:12 prog_clk[0]:208 1.033314e-05 +37 chany_bottom_in[6]:8 prog_clk[0]:196 1.524801e-05 +38 chany_bottom_in[6]:7 prog_clk[0]:195 1.524801e-05 +39 chany_bottom_in[6]:19 prog_clk[0]:430 6.121058e-05 +40 chany_bottom_in[6]:19 prog_clk[0]:429 7.98152e-05 +41 chany_bottom_in[6]:27 prog_clk[0]:208 7.510286e-05 +42 chany_bottom_in[6]:27 prog_clk[0]:214 8.3579e-05 +43 chany_bottom_in[6]:28 prog_clk[0]:215 7.324586e-05 +44 chany_bottom_in[6]:28 prog_clk[0]:214 7.510286e-05 +45 chany_bottom_in[6]:16 top_left_grid_pin_35_[0]:9 0.0004115157 +46 chany_bottom_in[6]:16 top_left_grid_pin_35_[0]:10 0.0001112172 +47 chany_bottom_in[6]:19 top_left_grid_pin_35_[0]:9 0.0001112172 +48 chany_bottom_in[6]:19 top_left_grid_pin_35_[0]:5 0.0004115157 +49 chany_bottom_in[6]:10 chanx_right_in[0]:11 6.016502e-06 +50 chany_bottom_in[6]:9 chanx_right_in[0]:12 6.016502e-06 +51 chany_bottom_in[6]:26 chanx_right_in[0]:11 0.0002512786 +52 chany_bottom_in[6]:26 chanx_right_in[0]:12 0.0004829694 +53 chany_bottom_in[6]:25 chanx_right_in[0]:11 0.0004829694 +54 chany_bottom_in[6]:25 chanx_right_in[0]:7 0.0002512786 +55 chany_bottom_in[6]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002936558 +56 chany_bottom_in[6]:19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002936558 +57 chany_bottom_in[6]:24 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.535351e-05 +58 chany_bottom_in[6]:23 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.535351e-05 +59 chany_bottom_in[6]:24 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.535351e-05 +60 chany_bottom_in[6]:23 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.535351e-05 +61 chany_bottom_in[6]:18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.351799e-05 +62 chany_bottom_in[6]:17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.351799e-05 +63 chany_bottom_in[6]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001873434 +64 chany_bottom_in[6]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001873434 +65 chany_bottom_in[6]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001338593 +66 chany_bottom_in[6]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.31956e-05 +67 chany_bottom_in[6]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.31956e-05 +68 chany_bottom_in[6]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001338593 +69 chany_bottom_in[6]:27 ropt_net_243:3 6.487355e-05 +70 chany_bottom_in[6]:28 ropt_net_243:4 6.487355e-05 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:29 0.0006696429 +1 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.0003705357 +2 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.0045 +3 chany_bottom_in[6]:13 FTB_30__29:A 0.152 +4 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.0005267857 +5 chany_bottom_in[6]:12 chany_bottom_in[6]:11 0.0045 +6 chany_bottom_in[6]:10 mux_top_track_8\/mux_l1_in_2_:A0 0.152 +7 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.00925 +8 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.0045 +9 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.006294644 +10 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.002908482 +11 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.0045 +12 chany_bottom_in[6]:5 mux_right_track_8\/mux_l2_in_1_:A0 0.152 +13 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.001720982 +14 chany_bottom_in[6]:19 chany_bottom_in[6]:18 0.0045 +15 chany_bottom_in[6]:19 chany_bottom_in[6]:16 0.04124554 +16 chany_bottom_in[6]:17 mux_left_track_9\/mux_l2_in_1_:A0 0.152 +17 chany_bottom_in[6]:27 chany_bottom_in[6]:26 0.00341 +18 chany_bottom_in[6]:27 chany_bottom_in[6]:12 0.0001911058 +19 chany_bottom_in[6]:26 chany_bottom_in[6]:25 0.00215965 +20 chany_bottom_in[6]:24 chany_bottom_in[6]:23 0.002944197 +21 chany_bottom_in[6]:25 chany_bottom_in[6]:24 0.00341 +22 chany_bottom_in[6]:22 chany_bottom_in[6]:21 0.02538393 +23 chany_bottom_in[6]:23 chany_bottom_in[6]:22 0.0045 +24 chany_bottom_in[6]:21 chany_bottom_in[6]:20 0.0045 +25 chany_bottom_in[6]:20 chany_bottom_in[6]:19 0.01362054 +26 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.0003035715 +27 chany_bottom_in[6]:28 chany_bottom_in[6]:27 0.04548438 +28 chany_bottom_in[6]:29 chany_bottom_in[6]:28 0.0004107143 + +*END + +*D_NET chany_bottom_in[14] 0.03557042 //LENGTH 207.545 LUMPCC 0.01683322 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 66.240 1.290 +*I mux_top_track_4\/mux_l2_in_5_:A0 I *L 0.001631 *C 55.950 86.020 +*I FTB_36__35:A I *L 0.001776 *C 43.240 126.480 +*I mux_left_track_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 45.445 90.780 +*I mux_right_track_4\/mux_l2_in_6_:A1 I *L 0.00198 *C 112.340 74.460 +*N chany_bottom_in[14]:5 *C 112.303 74.460 +*N chany_bottom_in[14]:6 *C 111.825 74.460 +*N chany_bottom_in[14]:7 *C 111.780 74.460 +*N chany_bottom_in[14]:8 *C 111.780 74.800 +*N chany_bottom_in[14]:9 *C 111.773 74.800 +*N chany_bottom_in[14]:10 *C 45.483 90.780 +*N chany_bottom_in[14]:11 *C 45.955 90.780 +*N chany_bottom_in[14]:12 *C 46.000 90.780 +*N chany_bottom_in[14]:13 *C 43.278 126.480 +*N chany_bottom_in[14]:14 *C 45.035 126.480 +*N chany_bottom_in[14]:15 *C 45.080 126.435 +*N chany_bottom_in[14]:16 *C 45.080 121.098 +*N chany_bottom_in[14]:17 *C 45.088 121.040 +*N chany_bottom_in[14]:18 *C 46.900 121.040 +*N chany_bottom_in[14]:19 *C 46.920 121.032 +*N chany_bottom_in[14]:20 *C 46.920 90.448 +*N chany_bottom_in[14]:21 *C 46.900 90.440 +*N chany_bottom_in[14]:22 *C 46.008 90.440 +*N chany_bottom_in[14]:23 *C 46.000 90.383 +*N chany_bottom_in[14]:24 *C 46.000 86.405 +*N chany_bottom_in[14]:25 *C 46.045 86.360 +*N chany_bottom_in[14]:26 *C 55.660 86.360 +*N chany_bottom_in[14]:27 *C 55.950 86.020 +*N chany_bottom_in[14]:28 *C 55.660 86.020 +*N chany_bottom_in[14]:29 *C 55.660 85.975 +*N chany_bottom_in[14]:30 *C 55.660 85.045 +*N chany_bottom_in[14]:31 *C 55.705 85.000 +*N chany_bottom_in[14]:32 *C 60.675 85.000 +*N chany_bottom_in[14]:33 *C 60.720 84.955 +*N chany_bottom_in[14]:34 *C 60.720 82.620 +*N chany_bottom_in[14]:35 *C 61.180 82.620 +*N chany_bottom_in[14]:36 *C 61.180 74.858 +*N chany_bottom_in[14]:37 *C 61.188 74.800 +*N chany_bottom_in[14]:38 *C 69.920 74.800 +*N chany_bottom_in[14]:39 *C 69.920 74.793 +*N chany_bottom_in[14]:40 *C 69.920 55.768 +*N chany_bottom_in[14]:41 *C 69.900 55.760 +*N chany_bottom_in[14]:42 *C 67.180 55.760 +*N chany_bottom_in[14]:43 *C 67.160 55.753 +*N chany_bottom_in[14]:44 *C 67.160 10.888 +*N chany_bottom_in[14]:45 *C 67.140 10.880 +*N chany_bottom_in[14]:46 *C 66.248 10.880 +*N chany_bottom_in[14]:47 *C 66.240 10.822 + +*CAP +0 chany_bottom_in[14] 0.0004720983 +1 mux_top_track_4\/mux_l2_in_5_:A0 1e-06 +2 FTB_36__35:A 1e-06 +3 mux_left_track_5\/mux_l2_in_3_:A1 1e-06 +4 mux_right_track_4\/mux_l2_in_6_:A1 1e-06 +5 chany_bottom_in[14]:5 6.832999e-05 +6 chany_bottom_in[14]:6 6.832999e-05 +7 chany_bottom_in[14]:7 5.870415e-05 +8 chany_bottom_in[14]:8 6.29619e-05 +9 chany_bottom_in[14]:9 0.001461338 +10 chany_bottom_in[14]:10 6.191574e-05 +11 chany_bottom_in[14]:11 6.191574e-05 +12 chany_bottom_in[14]:12 5.887519e-05 +13 chany_bottom_in[14]:13 0.0001385165 +14 chany_bottom_in[14]:14 0.0001385165 +15 chany_bottom_in[14]:15 0.0003031848 +16 chany_bottom_in[14]:16 0.0003031848 +17 chany_bottom_in[14]:17 0.0001166439 +18 chany_bottom_in[14]:18 0.0001166439 +19 chany_bottom_in[14]:19 0.001306203 +20 chany_bottom_in[14]:20 0.001306203 +21 chany_bottom_in[14]:21 9.316312e-05 +22 chany_bottom_in[14]:22 9.316312e-05 +23 chany_bottom_in[14]:23 0.0003098734 +24 chany_bottom_in[14]:24 0.0002851097 +25 chany_bottom_in[14]:25 0.0004668538 +26 chany_bottom_in[14]:26 0.0004941782 +27 chany_bottom_in[14]:27 5.86336e-05 +28 chany_bottom_in[14]:28 8.623079e-05 +29 chany_bottom_in[14]:29 9.002947e-05 +30 chany_bottom_in[14]:30 9.002947e-05 +31 chany_bottom_in[14]:31 0.0003237482 +32 chany_bottom_in[14]:32 0.0003237482 +33 chany_bottom_in[14]:33 0.0001666972 +34 chany_bottom_in[14]:34 0.0001915838 +35 chany_bottom_in[14]:35 0.0005024892 +36 chany_bottom_in[14]:36 0.0004776026 +37 chany_bottom_in[14]:37 0.000271496 +38 chany_bottom_in[14]:38 0.001732834 +39 chany_bottom_in[14]:39 0.001623257 +40 chany_bottom_in[14]:40 0.001623257 +41 chany_bottom_in[14]:41 0.0001856687 +42 chany_bottom_in[14]:42 0.0001856687 +43 chany_bottom_in[14]:43 0.00114593 +44 chany_bottom_in[14]:44 0.00114593 +45 chany_bottom_in[14]:45 9.517733e-05 +46 chany_bottom_in[14]:46 9.517733e-05 +47 chany_bottom_in[14]:47 0.0004720983 +48 chany_bottom_in[14]:39 chany_top_in[4]:21 0.0003267948 +49 chany_bottom_in[14]:40 chany_top_in[4]:20 0.0003267948 +50 chany_bottom_in[14]:43 chany_top_in[4]:21 0.001181937 +51 chany_bottom_in[14]:44 chany_top_in[4]:20 0.001181937 +52 chany_bottom_in[14]:37 chany_bottom_in[16]:17 0.0004599123 +53 chany_bottom_in[14]:38 chany_bottom_in[16]:18 0.0004599123 +54 chany_bottom_in[14]:38 chany_bottom_in[16]:17 0.001297957 +55 chany_bottom_in[14]:20 chany_bottom_in[16]:16 0.0005735382 +56 chany_bottom_in[14]:18 chany_bottom_in[16]:13 7.778935e-06 +57 chany_bottom_in[14]:19 chany_bottom_in[16]:15 0.0005735382 +58 chany_bottom_in[14]:16 chany_bottom_in[16]:12 2.147914e-06 +59 chany_bottom_in[14]:17 chany_bottom_in[16]:14 7.778935e-06 +60 chany_bottom_in[14]:15 chany_bottom_in[16]:11 2.147914e-06 +61 chany_bottom_in[14]:9 chany_bottom_in[16]:18 0.001297957 +62 chany_bottom_in[14] chany_bottom_in[17] 2.021247e-07 +63 chany_bottom_in[14]:41 chany_bottom_in[17]:29 0.0001609172 +64 chany_bottom_in[14]:42 chany_bottom_in[17]:28 0.0001609172 +65 chany_bottom_in[14]:43 chany_bottom_in[17]:37 0.0003704628 +66 chany_bottom_in[14]:44 chany_bottom_in[17]:38 0.0003704628 +67 chany_bottom_in[14]:47 chany_bottom_in[17]:41 2.021247e-07 +68 chany_bottom_in[14]:37 chanx_left_in[9]:26 0.0004599123 +69 chany_bottom_in[14]:38 chanx_left_in[9]:25 0.0004599123 +70 chany_bottom_in[14]:38 chanx_left_in[9]:26 0.001079466 +71 chany_bottom_in[14]:9 chanx_left_in[9]:25 0.001079466 +72 chany_bottom_in[14]:38 chanx_left_in[18]:16 0.000814721 +73 chany_bottom_in[14]:9 chanx_left_in[18]:15 0.000814721 +74 chany_bottom_in[14] chany_bottom_in[1] 1.398434e-05 +75 chany_bottom_in[14] chany_bottom_in[1]:22 6.025631e-06 +76 chany_bottom_in[14]:43 chany_bottom_in[1]:20 6.11287e-05 +77 chany_bottom_in[14]:43 chany_bottom_in[1]:21 0.0008169981 +78 chany_bottom_in[14]:44 chany_bottom_in[1]:22 0.0008169981 +79 chany_bottom_in[14]:44 chany_bottom_in[1]:21 6.11287e-05 +80 chany_bottom_in[14]:47 chany_bottom_in[1]:25 1.398434e-05 +81 chany_bottom_in[14]:47 chany_bottom_in[1]:21 6.025631e-06 +82 chany_bottom_in[14]:28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 1.031935e-05 +83 chany_bottom_in[14]:31 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 6.365735e-05 +84 chany_bottom_in[14]:32 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 6.365735e-05 +85 chany_bottom_in[14]:27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 1.031935e-05 +86 chany_bottom_in[14]:25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 2.207165e-05 +87 chany_bottom_in[14]:26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 2.207165e-05 +88 chany_bottom_in[14]:34 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.823912e-06 +89 chany_bottom_in[14]:35 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.823912e-06 +90 chany_bottom_in[14]:25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003051427 +91 chany_bottom_in[14]:26 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003051427 +92 chany_bottom_in[14]:38 optlc_net_151:24 0.000287951 +93 chany_bottom_in[14]:38 optlc_net_151:19 6.373401e-06 +94 chany_bottom_in[14]:9 optlc_net_151:25 0.000287951 +95 chany_bottom_in[14]:9 optlc_net_151:20 6.373401e-06 +96 chany_bottom_in[14] ropt_net_170:6 7.938847e-05 +97 chany_bottom_in[14]:47 ropt_net_170:7 7.938847e-05 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:47 0.008511161 +1 chany_bottom_in[14]:28 chany_bottom_in[14]:27 0.0001576087 +2 chany_bottom_in[14]:28 chany_bottom_in[14]:26 0.0003035715 +3 chany_bottom_in[14]:29 chany_bottom_in[14]:28 0.0045 +4 chany_bottom_in[14]:31 chany_bottom_in[14]:30 0.0045 +5 chany_bottom_in[14]:30 chany_bottom_in[14]:29 0.0008303572 +6 chany_bottom_in[14]:32 chany_bottom_in[14]:31 0.004437501 +7 chany_bottom_in[14]:33 chany_bottom_in[14]:32 0.0045 +8 chany_bottom_in[14]:36 chany_bottom_in[14]:35 0.006930804 +9 chany_bottom_in[14]:37 chany_bottom_in[14]:36 0.00341 +10 chany_bottom_in[14]:38 chany_bottom_in[14]:37 0.001368092 +11 chany_bottom_in[14]:38 chany_bottom_in[14]:9 0.006556891 +12 chany_bottom_in[14]:39 chany_bottom_in[14]:38 0.00341 +13 chany_bottom_in[14]:41 chany_bottom_in[14]:40 0.00341 +14 chany_bottom_in[14]:40 chany_bottom_in[14]:39 0.002980583 +15 chany_bottom_in[14]:42 chany_bottom_in[14]:41 0.0004261333 +16 chany_bottom_in[14]:43 chany_bottom_in[14]:42 0.00341 +17 chany_bottom_in[14]:45 chany_bottom_in[14]:44 0.00341 +18 chany_bottom_in[14]:44 chany_bottom_in[14]:43 0.007028849 +19 chany_bottom_in[14]:47 chany_bottom_in[14]:46 0.00341 +20 chany_bottom_in[14]:46 chany_bottom_in[14]:45 0.000139825 +21 chany_bottom_in[14]:27 mux_top_track_4\/mux_l2_in_5_:A0 0.152 +22 chany_bottom_in[14]:23 chany_bottom_in[14]:22 0.00341 +23 chany_bottom_in[14]:23 chany_bottom_in[14]:12 0.0001911058 +24 chany_bottom_in[14]:22 chany_bottom_in[14]:21 0.000139825 +25 chany_bottom_in[14]:21 chany_bottom_in[14]:20 0.00341 +26 chany_bottom_in[14]:20 chany_bottom_in[14]:19 0.00479165 +27 chany_bottom_in[14]:18 chany_bottom_in[14]:17 0.0002839583 +28 chany_bottom_in[14]:19 chany_bottom_in[14]:18 0.00341 +29 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.004765625 +30 chany_bottom_in[14]:17 chany_bottom_in[14]:16 0.00341 +31 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.001569197 +32 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.0045 +33 chany_bottom_in[14]:13 FTB_36__35:A 0.152 +34 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.0004218751 +35 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.0045 +36 chany_bottom_in[14]:10 mux_left_track_5\/mux_l2_in_3_:A1 0.152 +37 chany_bottom_in[14]:25 chany_bottom_in[14]:24 0.0045 +38 chany_bottom_in[14]:24 chany_bottom_in[14]:23 0.003551339 +39 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.0001634615 +40 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.00341 +41 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.0004263393 +42 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.0045 +43 chany_bottom_in[14]:5 mux_right_track_4\/mux_l2_in_6_:A1 0.152 +44 chany_bottom_in[14]:26 chany_bottom_in[14]:25 0.008584823 +45 chany_bottom_in[14]:34 chany_bottom_in[14]:33 0.002084822 +46 chany_bottom_in[14]:35 chany_bottom_in[14]:34 0.0004107143 + +*END + +*D_NET chanx_left_in[12] 0.03525706 //LENGTH 217.320 LUMPCC 0.01514936 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 97.920 +*I mux_top_track_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 78.565 96.220 +*I mux_right_track_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 99.265 96.220 +*I FTB_47__46:A I *L 0.001776 *C 134.320 93.840 +*I mux_bottom_track_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 83.720 34.340 +*N chanx_left_in[12]:5 *C 83.683 34.340 +*N chanx_left_in[12]:6 *C 82.385 34.340 +*N chanx_left_in[12]:7 *C 82.340 34.385 +*N chanx_left_in[12]:8 *C 82.340 40.742 +*N chanx_left_in[12]:9 *C 82.333 40.800 +*N chanx_left_in[12]:10 *C 79.140 40.800 +*N chanx_left_in[12]:11 *C 79.120 40.808 +*N chanx_left_in[12]:12 *C 79.120 90.635 +*N chanx_left_in[12]:13 *C 134.320 93.840 +*N chanx_left_in[12]:14 *C 134.320 94.180 +*N chanx_left_in[12]:15 *C 115.000 94.180 +*N chanx_left_in[12]:16 *C 115.000 93.500 +*N chanx_left_in[12]:17 *C 107.225 93.500 +*N chanx_left_in[12]:18 *C 107.180 93.545 +*N chanx_left_in[12]:19 *C 107.180 96.175 +*N chanx_left_in[12]:20 *C 107.135 96.220 +*N chanx_left_in[12]:21 *C 99.265 96.220 +*N chanx_left_in[12]:22 *C 93.840 96.220 +*N chanx_left_in[12]:23 *C 93.840 97.240 +*N chanx_left_in[12]:24 *C 86.525 97.240 +*N chanx_left_in[12]:25 *C 86.480 97.195 +*N chanx_left_in[12]:26 *C 86.480 95.938 +*N chanx_left_in[12]:27 *C 86.473 95.880 +*N chanx_left_in[12]:28 *C 78.650 96.220 +*N chanx_left_in[12]:29 *C 79.120 96.220 +*N chanx_left_in[12]:30 *C 79.120 95.880 +*N chanx_left_in[12]:31 *C 79.120 95.880 +*N chanx_left_in[12]:32 *C 79.127 95.880 +*N chanx_left_in[12]:33 *C 79.120 95.880 +*N chanx_left_in[12]:34 *C 79.120 99.953 +*N chanx_left_in[12]:35 *C 79.100 99.960 +*N chanx_left_in[12]:36 *C 55.355 99.960 +*N chanx_left_in[12]:37 *C 5.527 99.960 +*N chanx_left_in[12]:38 *C 5.520 99.903 +*N chanx_left_in[12]:39 *C 5.520 97.978 +*N chanx_left_in[12]:40 *C 5.513 97.920 + +*CAP +0 chanx_left_in[12] 0.0002287191 +1 mux_top_track_0\/mux_l2_in_3_:A1 1e-06 +2 mux_right_track_0\/mux_l2_in_3_:A1 1e-06 +3 FTB_47__46:A 1e-06 +4 mux_bottom_track_1\/mux_l2_in_3_:A1 1e-06 +5 chanx_left_in[12]:5 0.0001285986 +6 chanx_left_in[12]:6 0.0001285986 +7 chanx_left_in[12]:7 0.0003753091 +8 chanx_left_in[12]:8 0.0003753091 +9 chanx_left_in[12]:9 0.0002864568 +10 chanx_left_in[12]:10 0.0002864568 +11 chanx_left_in[12]:11 0.001371688 +12 chanx_left_in[12]:12 0.001725485 +13 chanx_left_in[12]:13 5.170424e-05 +14 chanx_left_in[12]:14 0.00111002 +15 chanx_left_in[12]:15 0.001130897 +16 chanx_left_in[12]:16 0.0005945602 +17 chanx_left_in[12]:17 0.000548055 +18 chanx_left_in[12]:18 0.0001707362 +19 chanx_left_in[12]:19 0.0001707362 +20 chanx_left_in[12]:20 0.0005493507 +21 chanx_left_in[12]:21 0.0009445358 +22 chanx_left_in[12]:22 0.0004333856 +23 chanx_left_in[12]:23 0.0006020616 +24 chanx_left_in[12]:24 0.0005363802 +25 chanx_left_in[12]:25 9.553198e-05 +26 chanx_left_in[12]:26 9.553198e-05 +27 chanx_left_in[12]:27 0.0002575795 +28 chanx_left_in[12]:28 6.208869e-05 +29 chanx_left_in[12]:29 9.444964e-05 +30 chanx_left_in[12]:30 7.097465e-05 +31 chanx_left_in[12]:31 3.892762e-05 +32 chanx_left_in[12]:32 0.0002575795 +33 chanx_left_in[12]:33 0.0006301704 +34 chanx_left_in[12]:34 0.0002763742 +35 chanx_left_in[12]:35 0.001432555 +36 chanx_left_in[12]:36 0.002996051 +37 chanx_left_in[12]:37 0.001563495 +38 chanx_left_in[12]:38 0.0001273137 +39 chanx_left_in[12]:39 0.0001273137 +40 chanx_left_in[12]:40 0.0002287191 +41 chanx_left_in[12]:27 chany_top_in[13]:26 0.0003992005 +42 chanx_left_in[12]:32 chany_top_in[13]:27 0.0003992005 +43 chanx_left_in[12]:35 chany_top_in[13]:29 9.935405e-05 +44 chanx_left_in[12]:35 chany_top_in[13]:30 3.302345e-05 +45 chanx_left_in[12]:23 chany_top_in[13]:22 1.532898e-07 +46 chanx_left_in[12]:22 chany_top_in[13]:23 1.532898e-07 +47 chanx_left_in[12]:36 chany_top_in[13]:35 3.302345e-05 +48 chanx_left_in[12]:36 chany_top_in[13]:36 9.935405e-05 +49 chanx_left_in[12]:35 chanx_right_in[5]:29 0.0003420913 +50 chanx_left_in[12]:37 chanx_right_in[5]:28 0.0002954243 +51 chanx_left_in[12]:15 chanx_right_in[5]:33 5.073609e-06 +52 chanx_left_in[12]:14 chanx_right_in[5]:34 5.073609e-06 +53 chanx_left_in[12]:36 chanx_right_in[5]:28 0.0003420913 +54 chanx_left_in[12]:36 chanx_right_in[5]:29 0.0002954243 +55 chanx_left_in[12]:25 chanx_right_in[12]:29 6.733032e-06 +56 chanx_left_in[12]:26 chanx_right_in[12]:28 6.733032e-06 +57 chanx_left_in[12]:27 chanx_right_in[12]:23 0.0002231245 +58 chanx_left_in[12]:27 chanx_right_in[12]:28 7.906854e-05 +59 chanx_left_in[12]:27 chanx_right_in[12]:30 2.943618e-05 +60 chanx_left_in[12]:32 chanx_right_in[12]:11 0.0002231245 +61 chanx_left_in[12]:32 chanx_right_in[12]:23 7.906854e-05 +62 chanx_left_in[12]:32 chanx_right_in[12]:29 2.943618e-05 +63 chanx_left_in[12]:35 chanx_right_in[12]:11 7.66038e-06 +64 chanx_left_in[12]:35 chanx_right_in[12]:23 4.192278e-05 +65 chanx_left_in[12]:37 chanx_right_in[12]:10 7.629396e-05 +66 chanx_left_in[12]:36 chanx_right_in[12]:10 7.66038e-06 +67 chanx_left_in[12]:36 chanx_right_in[12]:11 0.0001182167 +68 chanx_left_in[12]:11 chany_bottom_in[12]:28 0.00114559 +69 chanx_left_in[12]:11 chany_bottom_in[12]:29 0.0005082255 +70 chanx_left_in[12]:12 chany_bottom_in[12]:27 0.00114559 +71 chanx_left_in[12]:12 chany_bottom_in[12]:28 0.0005082255 +72 chanx_left_in[12]:37 chany_top_in[1]:19 0.0002756139 +73 chanx_left_in[12]:36 chany_top_in[1]:20 0.0002756139 +74 chanx_left_in[12]:11 chany_bottom_in[0]:16 0.0002651012 +75 chanx_left_in[12]:11 chany_bottom_in[0]:18 0.0005653842 +76 chanx_left_in[12]:11 chany_bottom_in[0]:17 0.001170562 +77 chanx_left_in[12]:12 chany_bottom_in[0]:16 0.001170562 +78 chanx_left_in[12]:12 chany_bottom_in[0]:9 0.0002651012 +79 chanx_left_in[12]:12 chany_bottom_in[0]:17 0.0005653842 +80 chanx_left_in[12]:38 left_top_grid_pin_42_[0]:24 3.616666e-06 +81 chanx_left_in[12]:37 left_top_grid_pin_42_[0]:23 0.0005046774 +82 chanx_left_in[12]:37 left_top_grid_pin_42_[0]:19 4.013532e-05 +83 chanx_left_in[12]:39 left_top_grid_pin_42_[0]:10 3.616666e-06 +84 chanx_left_in[12]:36 left_top_grid_pin_42_[0]:22 0.0005046774 +85 chanx_left_in[12]:36 left_top_grid_pin_42_[0]:18 4.013532e-05 +86 chanx_left_in[12] left_top_grid_pin_47_[0]:20 0.0001510612 +87 chanx_left_in[12]:37 left_top_grid_pin_47_[0]:19 0.0002269089 +88 chanx_left_in[12]:37 left_top_grid_pin_47_[0]:20 0.000184694 +89 chanx_left_in[12]:40 left_top_grid_pin_47_[0]:19 0.0001510612 +90 chanx_left_in[12]:36 left_top_grid_pin_47_[0]:15 0.0002269089 +91 chanx_left_in[12]:36 left_top_grid_pin_47_[0]:19 0.000184694 +92 chanx_left_in[12]:37 mux_tree_tapbuf_size12_7_sram[2]:9 0.0003401015 +93 chanx_left_in[12]:37 mux_tree_tapbuf_size12_7_sram[2]:14 0.0002642014 +94 chanx_left_in[12]:36 mux_tree_tapbuf_size12_7_sram[2]:15 0.0002642014 +95 chanx_left_in[12]:36 mux_tree_tapbuf_size12_7_sram[2]:14 0.0003401015 +96 chanx_left_in[12]:35 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000104839 +97 chanx_left_in[12]:37 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001854077 +98 chanx_left_in[12]:36 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000104839 +99 chanx_left_in[12]:36 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001854077 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:40 0.0006709249 +1 chanx_left_in[12]:24 chanx_left_in[12]:23 0.00653125 +2 chanx_left_in[12]:25 chanx_left_in[12]:24 0.0045 +3 chanx_left_in[12]:26 chanx_left_in[12]:25 0.001122768 +4 chanx_left_in[12]:27 chanx_left_in[12]:26 0.00341 +5 chanx_left_in[12]:20 chanx_left_in[12]:19 0.0045 +6 chanx_left_in[12]:19 chanx_left_in[12]:18 0.002348214 +7 chanx_left_in[12]:17 chanx_left_in[12]:16 0.006941965 +8 chanx_left_in[12]:18 chanx_left_in[12]:17 0.0045 +9 chanx_left_in[12]:13 FTB_47__46:A 0.152 +10 chanx_left_in[12]:10 chanx_left_in[12]:9 0.0005001583 +11 chanx_left_in[12]:11 chanx_left_in[12]:10 0.00341 +12 chanx_left_in[12]:8 chanx_left_in[12]:7 0.005676339 +13 chanx_left_in[12]:9 chanx_left_in[12]:8 0.00341 +14 chanx_left_in[12]:6 chanx_left_in[12]:5 0.001158482 +15 chanx_left_in[12]:7 chanx_left_in[12]:6 0.0045 +16 chanx_left_in[12]:5 mux_bottom_track_1\/mux_l2_in_3_:A1 0.152 +17 chanx_left_in[12]:31 chanx_left_in[12]:30 0.0045 +18 chanx_left_in[12]:32 chanx_left_in[12]:31 0.00341 +19 chanx_left_in[12]:32 chanx_left_in[12]:27 0.001150717 +20 chanx_left_in[12]:30 chanx_left_in[12]:29 0.0003035715 +21 chanx_left_in[12]:28 mux_top_track_0\/mux_l2_in_3_:A1 0.152 +22 chanx_left_in[12]:35 chanx_left_in[12]:34 0.00341 +23 chanx_left_in[12]:34 chanx_left_in[12]:33 0.0006380249 +24 chanx_left_in[12]:38 chanx_left_in[12]:37 0.00341 +25 chanx_left_in[12]:37 chanx_left_in[12]:36 0.007806308 +26 chanx_left_in[12]:39 chanx_left_in[12]:38 0.00171875 +27 chanx_left_in[12]:40 chanx_left_in[12]:39 0.00341 +28 chanx_left_in[12]:21 mux_right_track_0\/mux_l2_in_3_:A1 0.152 +29 chanx_left_in[12]:21 chanx_left_in[12]:20 0.007026786 +30 chanx_left_in[12]:33 chanx_left_in[12]:32 0.00341 +31 chanx_left_in[12]:33 chanx_left_in[12]:12 0.0008217166 +32 chanx_left_in[12]:29 chanx_left_in[12]:28 0.0004196428 +33 chanx_left_in[12]:23 chanx_left_in[12]:22 0.0009107143 +34 chanx_left_in[12]:22 chanx_left_in[12]:21 0.00484375 +35 chanx_left_in[12]:16 chanx_left_in[12]:15 0.0006071429 +36 chanx_left_in[12]:15 chanx_left_in[12]:14 0.01725 +37 chanx_left_in[12]:14 chanx_left_in[12]:13 0.0003035715 +38 chanx_left_in[12]:36 chanx_left_in[12]:35 0.00372005 +39 chanx_left_in[12]:12 chanx_left_in[12]:11 0.007806308 + +*END + +*D_NET chany_top_in[15] 0.01322366 //LENGTH 82.735 LUMPCC 0.00539066 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 53.820 129.270 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 48.590 87.720 +*I mux_right_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.935 77.180 +*N chany_top_in[15]:3 *C 71.935 77.180 +*N chany_top_in[15]:4 *C 71.760 77.520 +*N chany_top_in[15]:5 *C 68.125 77.520 +*N chany_top_in[15]:6 *C 68.080 77.520 +*N chany_top_in[15]:7 *C 68.073 77.520 +*N chany_top_in[15]:8 *C 48.768 77.520 +*N chany_top_in[15]:9 *C 48.760 77.578 +*N chany_top_in[15]:10 *C 48.590 87.720 +*N chany_top_in[15]:11 *C 48.760 87.720 +*N chany_top_in[15]:12 *C 48.760 87.720 +*N chany_top_in[15]:13 *C 48.768 87.720 +*N chany_top_in[15]:14 *C 51.500 87.720 +*N chany_top_in[15]:15 *C 51.520 87.728 +*N chany_top_in[15]:16 *C 51.520 126.473 +*N chany_top_in[15]:17 *C 51.540 126.480 +*N chany_top_in[15]:18 *C 53.812 126.480 +*N chany_top_in[15]:19 *C 53.820 126.538 + +*CAP +0 chany_top_in[15] 0.0001767577 +1 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_32\/mux_l1_in_0_:A0 1e-06 +3 chany_top_in[15]:3 5.910863e-05 +4 chany_top_in[15]:4 0.0002667145 +5 chany_top_in[15]:5 0.0002391859 +6 chany_top_in[15]:6 3.923399e-05 +7 chany_top_in[15]:7 0.0005919384 +8 chany_top_in[15]:8 0.0005919384 +9 chany_top_in[15]:9 0.0006493188 +10 chany_top_in[15]:10 5.406466e-05 +11 chany_top_in[15]:11 5.805126e-05 +12 chany_top_in[15]:12 0.0006867867 +13 chany_top_in[15]:13 0.0003278468 +14 chany_top_in[15]:14 0.0003278468 +15 chany_top_in[15]:15 0.001642348 +16 chany_top_in[15]:16 0.001642348 +17 chany_top_in[15]:17 0.0001503765 +18 chany_top_in[15]:18 0.0001503765 +19 chany_top_in[15]:19 0.0001767577 +20 chany_top_in[15]:8 chanx_left_in[5]:26 0.001019746 +21 chany_top_in[15]:7 chanx_left_in[5]:25 0.001019746 +22 chany_top_in[15]:8 chany_bottom_in[15]:8 0.0009902797 +23 chany_top_in[15]:7 chany_bottom_in[15]:7 0.0009902797 +24 chany_top_in[15]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004623978 +25 chany_top_in[15]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0002224785 +26 chany_top_in[15]:17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.279559e-07 +27 chany_top_in[15]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002224785 +28 chany_top_in[15]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0004623978 +29 chany_top_in[15]:18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.279559e-07 + +*RES +0 chany_top_in[15] chany_top_in[15]:19 0.002439732 +1 chany_top_in[15]:9 chany_top_in[15]:8 0.00341 +2 chany_top_in[15]:8 chany_top_in[15]:7 0.00302445 +3 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +4 chany_top_in[15]:7 chany_top_in[15]:6 0.00341 +5 chany_top_in[15]:5 chany_top_in[15]:4 0.003245536 +6 chany_top_in[15]:3 mux_right_track_32\/mux_l1_in_0_:A0 0.152 +7 chany_top_in[15]:11 chany_top_in[15]:10 9.239131e-05 +8 chany_top_in[15]:12 chany_top_in[15]:11 0.0045 +9 chany_top_in[15]:12 chany_top_in[15]:9 0.009055804 +10 chany_top_in[15]:10 mux_left_track_5\/mux_l2_in_0_:A0 0.152 +11 chany_top_in[15]:13 chany_top_in[15]:12 0.00341 +12 chany_top_in[15]:14 chany_top_in[15]:13 0.0004280917 +13 chany_top_in[15]:15 chany_top_in[15]:14 0.00341 +14 chany_top_in[15]:17 chany_top_in[15]:16 0.00341 +15 chany_top_in[15]:16 chany_top_in[15]:15 0.006070049 +16 chany_top_in[15]:19 chany_top_in[15]:18 0.00341 +17 chany_top_in[15]:18 chany_top_in[15]:17 0.000356025 +18 chany_top_in[15]:4 chany_top_in[15]:3 0.0003035715 + +*END + +*D_NET chanx_right_in[0] 0.01097834 //LENGTH 77.200 LUMPCC 0.004350305 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 140.382 48.960 +*I mux_top_track_32\/mux_l1_in_1_:A1 I *L 0.00198 *C 84.545 52.700 +*I mux_bottom_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 73.965 50.660 +*N chanx_right_in[0]:3 *C 74.002 50.660 +*N chanx_right_in[0]:4 *C 74.935 50.660 +*N chanx_right_in[0]:5 *C 74.980 50.705 +*N chanx_right_in[0]:6 *C 74.980 53.663 +*N chanx_right_in[0]:7 *C 74.987 53.720 +*N chanx_right_in[0]:8 *C 84.545 52.700 +*N chanx_right_in[0]:9 *C 84.640 52.745 +*N chanx_right_in[0]:10 *C 84.640 53.663 +*N chanx_right_in[0]:11 *C 84.640 53.720 +*N chanx_right_in[0]:12 *C 134.640 53.720 +*N chanx_right_in[0]:13 *C 140.293 53.720 +*N chanx_right_in[0]:14 *C 140.300 53.663 +*N chanx_right_in[0]:15 *C 140.300 49.018 +*N chanx_right_in[0]:16 *C 140.300 48.960 + +*CAP +0 chanx_right_in[0] 1.105286e-05 +1 mux_top_track_32\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_25\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[0]:3 8.421121e-05 +4 chanx_right_in[0]:4 8.421121e-05 +5 chanx_right_in[0]:5 0.0002370591 +6 chanx_right_in[0]:6 0.0002370591 +7 chanx_right_in[0]:7 0.0004503901 +8 chanx_right_in[0]:8 2.800783e-05 +9 chanx_right_in[0]:9 7.616013e-05 +10 chanx_right_in[0]:10 7.616013e-05 +11 chanx_right_in[0]:11 0.002405649 +12 chanx_right_in[0]:12 0.002269147 +13 chanx_right_in[0]:13 0.0003138887 +14 chanx_right_in[0]:14 0.0001709916 +15 chanx_right_in[0]:15 0.0001709916 +16 chanx_right_in[0]:16 1.105286e-05 +17 chanx_right_in[0]:11 chanx_right_in[9]:26 0.0001799875 +18 chanx_right_in[0]:11 chanx_right_in[9]:27 0.0001468016 +19 chanx_right_in[0]:7 chanx_right_in[9]:26 1.561849e-06 +20 chanx_right_in[0]:4 chanx_right_in[9]:22 3.513975e-06 +21 chanx_right_in[0]:3 chanx_right_in[9]:23 3.513975e-06 +22 chanx_right_in[0]:13 chanx_right_in[9] 3.134701e-05 +23 chanx_right_in[0]:12 chanx_right_in[9] 0.0001452398 +24 chanx_right_in[0]:12 chanx_right_in[9]:27 0.0002113345 +25 chanx_right_in[0]:11 chany_bottom_in[6]:10 6.016502e-06 +26 chanx_right_in[0]:11 chany_bottom_in[6]:25 0.0004829694 +27 chanx_right_in[0]:11 chany_bottom_in[6]:26 0.0002512786 +28 chanx_right_in[0]:7 chany_bottom_in[6]:25 0.0002512786 +29 chanx_right_in[0]:12 chany_bottom_in[6]:9 6.016502e-06 +30 chanx_right_in[0]:12 chany_bottom_in[6]:26 0.0004829694 +31 chanx_right_in[0]:11 chanx_left_in[13]:13 0.0002911013 +32 chanx_right_in[0]:12 chanx_left_in[13]:12 0.0002911013 +33 chanx_right_in[0]:11 chanx_left_in[16]:19 5.927877e-06 +34 chanx_right_in[0]:11 chanx_left_in[16]:36 0.000330202 +35 chanx_right_in[0]:11 chanx_left_in[16]:37 2.709563e-05 +36 chanx_right_in[0]:6 chanx_left_in[16]:39 1.320167e-05 +37 chanx_right_in[0]:7 chanx_left_in[16]:38 2.709563e-05 +38 chanx_right_in[0]:5 chanx_left_in[16]:38 1.320167e-05 +39 chanx_right_in[0]:12 chanx_left_in[16]:18 5.927877e-06 +40 chanx_right_in[0]:12 chanx_left_in[16]:35 0.000330202 +41 chanx_right_in[0]:11 chany_bottom_in[7]:15 9.159333e-05 +42 chanx_right_in[0]:11 chany_bottom_in[7]:14 4.143743e-05 +43 chanx_right_in[0]:11 chany_bottom_in[7]:9 0.0002024669 +44 chanx_right_in[0]:7 chany_bottom_in[7]:8 0.0002024669 +45 chanx_right_in[0]:7 chany_bottom_in[7]:14 9.159333e-05 +46 chanx_right_in[0]:12 chany_bottom_in[7]:15 4.143743e-05 +47 chanx_right_in[0] ropt_net_174:7 1.581914e-05 +48 chanx_right_in[0]:14 ropt_net_174:7 4.774889e-05 +49 chanx_right_in[0]:13 ropt_net_174:8 6.64364e-06 +50 chanx_right_in[0]:15 ropt_net_174:6 4.774889e-05 +51 chanx_right_in[0]:16 ropt_net_174:6 1.581914e-05 +52 chanx_right_in[0]:12 ropt_net_174:9 6.64364e-06 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:16 2.35e-05 +1 chanx_right_in[0]:10 chanx_right_in[0]:9 0.0008191965 +2 chanx_right_in[0]:11 chanx_right_in[0]:10 0.00341 +3 chanx_right_in[0]:11 chanx_right_in[0]:7 0.001512225 +4 chanx_right_in[0]:8 mux_top_track_32\/mux_l1_in_1_:A1 0.152 +5 chanx_right_in[0]:9 chanx_right_in[0]:8 0.0045 +6 chanx_right_in[0]:6 chanx_right_in[0]:5 0.002640625 +7 chanx_right_in[0]:7 chanx_right_in[0]:6 0.00341 +8 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0008325894 +9 chanx_right_in[0]:5 chanx_right_in[0]:4 0.0045 +10 chanx_right_in[0]:3 mux_bottom_track_25\/mux_l1_in_1_:A1 0.152 +11 chanx_right_in[0]:14 chanx_right_in[0]:13 0.00341 +12 chanx_right_in[0]:13 chanx_right_in[0]:12 0.0008855583 +13 chanx_right_in[0]:15 chanx_right_in[0]:14 0.004147322 +14 chanx_right_in[0]:16 chanx_right_in[0]:15 0.00341 +15 chanx_right_in[0]:12 chanx_right_in[0]:11 0.007833333 + +*END + +*D_NET right_top_grid_pin_49_[0] 0.007384855 //LENGTH 56.405 LUMPCC 0.0006426824 DR + +*CONN +*P right_top_grid_pin_49_[0] I *L 0.29796 *C 136.620 102.070 +*I mux_right_track_4\/mux_l2_in_4_:A0 I *L 0.001631 *C 118.510 86.020 +*I mux_right_track_32\/mux_l1_in_1_:A0 I *L 0.001631 *C 108.850 82.620 +*I mux_right_track_2\/mux_l1_in_3_:A1 I *L 0.00198 *C 111.420 96.220 +*N right_top_grid_pin_49_[0]:4 *C 111.420 96.220 +*N right_top_grid_pin_49_[0]:5 *C 108.888 82.620 +*N right_top_grid_pin_49_[0]:6 *C 111.275 82.620 +*N right_top_grid_pin_49_[0]:7 *C 111.320 82.665 +*N right_top_grid_pin_49_[0]:8 *C 118.473 86.020 +*N right_top_grid_pin_49_[0]:9 *C 111.365 86.020 +*N right_top_grid_pin_49_[0]:10 *C 111.320 86.020 +*N right_top_grid_pin_49_[0]:11 *C 111.320 95.835 +*N right_top_grid_pin_49_[0]:12 *C 111.388 95.880 +*N right_top_grid_pin_49_[0]:13 *C 136.575 95.880 +*N right_top_grid_pin_49_[0]:14 *C 136.620 95.925 + +*CAP +0 right_top_grid_pin_49_[0] 0.0002768156 +1 mux_right_track_4\/mux_l2_in_4_:A0 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_2\/mux_l1_in_3_:A1 1e-06 +4 right_top_grid_pin_49_[0]:4 6.637401e-05 +5 right_top_grid_pin_49_[0]:5 0.0001476606 +6 right_top_grid_pin_49_[0]:6 0.0001476606 +7 right_top_grid_pin_49_[0]:7 0.0002013393 +8 right_top_grid_pin_49_[0]:8 0.0003394483 +9 right_top_grid_pin_49_[0]:9 0.0003394483 +10 right_top_grid_pin_49_[0]:10 0.0008474293 +11 right_top_grid_pin_49_[0]:11 0.0006147955 +12 right_top_grid_pin_49_[0]:12 0.001758737 +13 right_top_grid_pin_49_[0]:13 0.001722649 +14 right_top_grid_pin_49_[0]:14 0.0002768156 +15 right_top_grid_pin_49_[0] right_top_grid_pin_45_[0] 7.875366e-05 +16 right_top_grid_pin_49_[0]:14 right_top_grid_pin_45_[0]:17 7.875366e-05 +17 right_top_grid_pin_49_[0]:6 right_top_grid_pin_45_[0]:8 4.135483e-05 +18 right_top_grid_pin_49_[0]:5 right_top_grid_pin_45_[0]:7 4.135483e-05 +19 right_top_grid_pin_49_[0]:11 right_top_grid_pin_45_[0]:6 6.760301e-08 +20 right_top_grid_pin_49_[0]:11 right_top_grid_pin_45_[0]:14 1.19432e-06 +21 right_top_grid_pin_49_[0]:9 right_top_grid_pin_45_[0]:10 1.047177e-05 +22 right_top_grid_pin_49_[0]:9 right_top_grid_pin_45_[0]:12 0.000189499 +23 right_top_grid_pin_49_[0]:10 right_top_grid_pin_45_[0]:13 1.19432e-06 +24 right_top_grid_pin_49_[0]:10 right_top_grid_pin_45_[0]:14 6.760301e-08 +25 right_top_grid_pin_49_[0]:8 right_top_grid_pin_45_[0]:11 0.000189499 +26 right_top_grid_pin_49_[0]:8 right_top_grid_pin_45_[0]:13 1.047177e-05 + +*RES +0 right_top_grid_pin_49_[0] right_top_grid_pin_49_[0]:14 0.005486608 +1 right_top_grid_pin_49_[0]:13 right_top_grid_pin_49_[0]:12 0.02248884 +2 right_top_grid_pin_49_[0]:14 right_top_grid_pin_49_[0]:13 0.0045 +3 right_top_grid_pin_49_[0]:6 right_top_grid_pin_49_[0]:5 0.002131696 +4 right_top_grid_pin_49_[0]:7 right_top_grid_pin_49_[0]:6 0.0045 +5 right_top_grid_pin_49_[0]:5 mux_right_track_32\/mux_l1_in_1_:A0 0.152 +6 right_top_grid_pin_49_[0]:4 mux_right_track_2\/mux_l1_in_3_:A1 0.152 +7 right_top_grid_pin_49_[0]:12 right_top_grid_pin_49_[0]:11 0.0045 +8 right_top_grid_pin_49_[0]:12 right_top_grid_pin_49_[0]:4 0.0001847826 +9 right_top_grid_pin_49_[0]:11 right_top_grid_pin_49_[0]:10 0.008763393 +10 right_top_grid_pin_49_[0]:9 right_top_grid_pin_49_[0]:8 0.006345983 +11 right_top_grid_pin_49_[0]:10 right_top_grid_pin_49_[0]:9 0.0045 +12 right_top_grid_pin_49_[0]:10 right_top_grid_pin_49_[0]:7 0.002995536 +13 right_top_grid_pin_49_[0]:8 mux_right_track_4\/mux_l2_in_4_:A0 0.152 + +*END + +*D_NET bottom_left_grid_pin_38_[0] 0.01126268 //LENGTH 85.465 LUMPCC 0.001590719 DR + +*CONN +*P bottom_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 4.760 +*I mux_bottom_track_5\/mux_l2_in_4_:A1 I *L 0.00198 *C 34.600 7.140 +*I mux_bottom_track_1\/mux_l1_in_3_:A0 I *L 0.001631 *C 75.155 22.440 +*I mux_bottom_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 94.475 22.440 +*N bottom_left_grid_pin_38_[0]:4 *C 94.438 22.440 +*N bottom_left_grid_pin_38_[0]:5 *C 75.155 22.440 +*N bottom_left_grid_pin_38_[0]:6 *C 75.485 22.440 +*N bottom_left_grid_pin_38_[0]:7 *C 75.440 22.395 +*N bottom_left_grid_pin_38_[0]:8 *C 75.440 17.738 +*N bottom_left_grid_pin_38_[0]:9 *C 75.433 17.680 +*N bottom_left_grid_pin_38_[0]:10 *C 62.560 17.680 +*N bottom_left_grid_pin_38_[0]:11 *C 62.560 17.000 +*N bottom_left_grid_pin_38_[0]:12 *C 42.788 17.000 +*N bottom_left_grid_pin_38_[0]:13 *C 42.780 16.943 +*N bottom_left_grid_pin_38_[0]:14 *C 42.780 7.538 +*N bottom_left_grid_pin_38_[0]:15 *C 42.773 7.480 +*N bottom_left_grid_pin_38_[0]:16 *C 34.508 7.480 +*N bottom_left_grid_pin_38_[0]:17 *C 34.500 7.480 +*N bottom_left_grid_pin_38_[0]:18 *C 34.500 7.140 +*N bottom_left_grid_pin_38_[0]:19 *C 34.500 7.095 +*N bottom_left_grid_pin_38_[0]:20 *C 34.500 4.817 +*N bottom_left_grid_pin_38_[0]:21 *C 34.492 4.760 + +*CAP +0 bottom_left_grid_pin_38_[0] 0.0002629638 +1 mux_bottom_track_5\/mux_l2_in_4_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_3_:A0 1e-06 +3 mux_bottom_track_9\/mux_l2_in_1_:A0 1e-06 +4 bottom_left_grid_pin_38_[0]:4 0.001104587 +5 bottom_left_grid_pin_38_[0]:5 5.340926e-05 +6 bottom_left_grid_pin_38_[0]:6 0.001125944 +7 bottom_left_grid_pin_38_[0]:7 0.0003249797 +8 bottom_left_grid_pin_38_[0]:8 0.0003249797 +9 bottom_left_grid_pin_38_[0]:9 0.0008589978 +10 bottom_left_grid_pin_38_[0]:10 0.0009103641 +11 bottom_left_grid_pin_38_[0]:11 0.001085249 +12 bottom_left_grid_pin_38_[0]:12 0.001033883 +13 bottom_left_grid_pin_38_[0]:13 0.0004773607 +14 bottom_left_grid_pin_38_[0]:14 0.0004773607 +15 bottom_left_grid_pin_38_[0]:15 0.0004891221 +16 bottom_left_grid_pin_38_[0]:16 0.0004891221 +17 bottom_left_grid_pin_38_[0]:17 5.257051e-05 +18 bottom_left_grid_pin_38_[0]:18 3.621662e-05 +19 bottom_left_grid_pin_38_[0]:19 0.000158848 +20 bottom_left_grid_pin_38_[0]:20 0.0001400399 +21 bottom_left_grid_pin_38_[0]:21 0.0002629638 +22 bottom_left_grid_pin_38_[0]:16 prog_clk[0]:389 5.669257e-05 +23 bottom_left_grid_pin_38_[0]:14 prog_clk[0]:387 4.863646e-06 +24 bottom_left_grid_pin_38_[0]:15 prog_clk[0]:388 5.669257e-05 +25 bottom_left_grid_pin_38_[0]:13 prog_clk[0]:386 4.863646e-06 +26 bottom_left_grid_pin_38_[0]:12 prog_clk[0]:361 6.467789e-05 +27 bottom_left_grid_pin_38_[0]:12 prog_clk[0]:362 6.884774e-05 +28 bottom_left_grid_pin_38_[0]:8 prog_clk[0]:341 1.163867e-05 +29 bottom_left_grid_pin_38_[0]:9 prog_clk[0]:336 1.37487e-05 +30 bottom_left_grid_pin_38_[0]:9 prog_clk[0]:342 1.821461e-05 +31 bottom_left_grid_pin_38_[0]:9 prog_clk[0]:346 1.972862e-05 +32 bottom_left_grid_pin_38_[0]:9 prog_clk[0]:352 2.556542e-05 +33 bottom_left_grid_pin_38_[0]:7 prog_clk[0]:342 1.163867e-05 +34 bottom_left_grid_pin_38_[0]:11 prog_clk[0]:352 6.467789e-05 +35 bottom_left_grid_pin_38_[0]:11 prog_clk[0]:361 6.884774e-05 +36 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:341 1.37487e-05 +37 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:346 1.821461e-05 +38 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:347 1.972862e-05 +39 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:361 2.556542e-05 +40 bottom_left_grid_pin_38_[0]:12 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 0.0001359603 +41 bottom_left_grid_pin_38_[0]:9 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 2.194933e-05 +42 bottom_left_grid_pin_38_[0]:11 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 0.0001359603 +43 bottom_left_grid_pin_38_[0]:10 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 2.194933e-05 +44 bottom_left_grid_pin_38_[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001894436 +45 bottom_left_grid_pin_38_[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001894436 +46 bottom_left_grid_pin_38_[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001027896 +47 bottom_left_grid_pin_38_[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001027896 +48 bottom_left_grid_pin_38_[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 6.123858e-05 +49 bottom_left_grid_pin_38_[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 6.123858e-05 + +*RES +0 bottom_left_grid_pin_38_[0] bottom_left_grid_pin_38_[0]:21 0.0007429916 +1 bottom_left_grid_pin_38_[0]:4 mux_bottom_track_9\/mux_l2_in_1_:A0 0.152 +2 bottom_left_grid_pin_38_[0]:5 mux_bottom_track_1\/mux_l1_in_3_:A0 0.152 +3 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_38_[0]:16 0.00341 +4 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_38_[0]:15 0.00129485 +5 bottom_left_grid_pin_38_[0]:14 bottom_left_grid_pin_38_[0]:13 0.008397321 +6 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_38_[0]:14 0.00341 +7 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:12 0.00341 +8 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_38_[0]:11 0.003097692 +9 bottom_left_grid_pin_38_[0]:8 bottom_left_grid_pin_38_[0]:7 0.004158482 +10 bottom_left_grid_pin_38_[0]:9 bottom_left_grid_pin_38_[0]:8 0.00341 +11 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_38_[0]:5 0.0001793478 +12 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_38_[0]:4 0.01692188 +13 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_38_[0]:6 0.0045 +14 bottom_left_grid_pin_38_[0]:18 mux_bottom_track_5\/mux_l2_in_4_:A1 0.152 +15 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_38_[0]:18 0.0045 +16 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_38_[0]:17 0.0001850962 +17 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_38_[0]:19 0.002033482 +18 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_38_[0]:20 0.00341 +19 bottom_left_grid_pin_38_[0]:11 bottom_left_grid_pin_38_[0]:10 0.0001065333 +20 bottom_left_grid_pin_38_[0]:10 bottom_left_grid_pin_38_[0]:9 0.002016691 + +*END + +*D_NET left_top_grid_pin_48_[0] 0.00617602 //LENGTH 46.310 LUMPCC 0.001316551 DR + +*CONN +*P left_top_grid_pin_48_[0] I *L 0.29796 *C 11.500 102.070 +*I mux_left_track_5\/mux_l2_in_6_:A0 I *L 0.001631 *C 13.055 96.900 +*I mux_left_track_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 16.100 83.300 +*I mux_left_track_25\/mux_l2_in_3_:A1 I *L 0.00198 *C 18.500 66.980 +*N left_top_grid_pin_48_[0]:4 *C 18.463 66.980 +*N left_top_grid_pin_48_[0]:5 *C 17.525 66.980 +*N left_top_grid_pin_48_[0]:6 *C 17.480 66.980 +*N left_top_grid_pin_48_[0]:7 *C 17.480 67.320 +*N left_top_grid_pin_48_[0]:8 *C 17.473 67.320 +*N left_top_grid_pin_48_[0]:9 *C 15.660 67.320 +*N left_top_grid_pin_48_[0]:10 *C 15.640 67.328 +*N left_top_grid_pin_48_[0]:11 *C 15.640 82.953 +*N left_top_grid_pin_48_[0]:12 *C 15.620 82.960 +*N left_top_grid_pin_48_[0]:13 *C 14.268 82.960 +*N left_top_grid_pin_48_[0]:14 *C 14.260 82.960 +*N left_top_grid_pin_48_[0]:15 *C 16.100 83.300 +*N left_top_grid_pin_48_[0]:16 *C 14.305 83.300 +*N left_top_grid_pin_48_[0]:17 *C 14.260 83.345 +*N left_top_grid_pin_48_[0]:18 *C 14.260 96.855 +*N left_top_grid_pin_48_[0]:19 *C 14.215 96.900 +*N left_top_grid_pin_48_[0]:20 *C 13.055 96.900 +*N left_top_grid_pin_48_[0]:21 *C 11.545 96.900 +*N left_top_grid_pin_48_[0]:22 *C 11.500 96.945 + +*CAP +0 left_top_grid_pin_48_[0] 0.0002629672 +1 mux_left_track_5\/mux_l2_in_6_:A0 1e-06 +2 mux_left_track_1\/mux_l2_in_3_:A1 1e-06 +3 mux_left_track_25\/mux_l2_in_3_:A1 1e-06 +4 left_top_grid_pin_48_[0]:4 9.043354e-05 +5 left_top_grid_pin_48_[0]:5 9.043354e-05 +6 left_top_grid_pin_48_[0]:6 4.119252e-05 +7 left_top_grid_pin_48_[0]:7 4.958491e-05 +8 left_top_grid_pin_48_[0]:8 0.0002077138 +9 left_top_grid_pin_48_[0]:9 0.0002077138 +10 left_top_grid_pin_48_[0]:10 0.0009245565 +11 left_top_grid_pin_48_[0]:11 0.0009245565 +12 left_top_grid_pin_48_[0]:12 0.0001141875 +13 left_top_grid_pin_48_[0]:13 0.0001141875 +14 left_top_grid_pin_48_[0]:14 5.605156e-05 +15 left_top_grid_pin_48_[0]:15 0.0001449676 +16 left_top_grid_pin_48_[0]:16 0.0001016218 +17 left_top_grid_pin_48_[0]:17 0.0004947542 +18 left_top_grid_pin_48_[0]:18 0.0004775081 +19 left_top_grid_pin_48_[0]:19 5.73277e-05 +20 left_top_grid_pin_48_[0]:20 0.0001601303 +21 left_top_grid_pin_48_[0]:21 7.361361e-05 +22 left_top_grid_pin_48_[0]:22 0.0002629672 +23 left_top_grid_pin_48_[0] mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 2.740731e-05 +24 left_top_grid_pin_48_[0]:17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 5.982604e-08 +25 left_top_grid_pin_48_[0]:19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 4.486677e-05 +26 left_top_grid_pin_48_[0]:18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 5.982604e-08 +27 left_top_grid_pin_48_[0]:20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 4.486677e-05 +28 left_top_grid_pin_48_[0]:20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 5.086006e-05 +29 left_top_grid_pin_48_[0]:21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 5.086006e-05 +30 left_top_grid_pin_48_[0]:22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 2.740731e-05 +31 left_top_grid_pin_48_[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 7.785728e-05 +32 left_top_grid_pin_48_[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 2.5354e-05 +33 left_top_grid_pin_48_[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 2.5354e-05 +34 left_top_grid_pin_48_[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 7.785728e-05 +35 left_top_grid_pin_48_[0] optlc_net_150:28 3.583396e-07 +36 left_top_grid_pin_48_[0]:15 optlc_net_150:19 3.568592e-05 +37 left_top_grid_pin_48_[0]:15 optlc_net_150:16 1.8086e-05 +38 left_top_grid_pin_48_[0]:16 optlc_net_150:17 1.8086e-05 +39 left_top_grid_pin_48_[0]:16 optlc_net_150:18 3.568592e-05 +40 left_top_grid_pin_48_[0]:17 optlc_net_150:28 9.991279e-06 +41 left_top_grid_pin_48_[0]:17 optlc_net_150:29 0.0003613565 +42 left_top_grid_pin_48_[0]:18 optlc_net_150:28 0.0003613565 +43 left_top_grid_pin_48_[0]:14 optlc_net_150:29 9.991279e-06 +44 left_top_grid_pin_48_[0]:7 optlc_net_150:35 5.171756e-06 +45 left_top_grid_pin_48_[0]:5 optlc_net_150:34 1.220357e-06 +46 left_top_grid_pin_48_[0]:6 optlc_net_150:36 5.171756e-06 +47 left_top_grid_pin_48_[0]:4 optlc_net_150:32 1.220357e-06 +48 left_top_grid_pin_48_[0]:22 optlc_net_150:29 3.583396e-07 + +*RES +0 left_top_grid_pin_48_[0] left_top_grid_pin_48_[0]:22 0.004575893 +1 left_top_grid_pin_48_[0]:15 mux_left_track_1\/mux_l2_in_3_:A1 0.152 +2 left_top_grid_pin_48_[0]:16 left_top_grid_pin_48_[0]:15 0.001602679 +3 left_top_grid_pin_48_[0]:17 left_top_grid_pin_48_[0]:16 0.0045 +4 left_top_grid_pin_48_[0]:17 left_top_grid_pin_48_[0]:14 0.0001850962 +5 left_top_grid_pin_48_[0]:19 left_top_grid_pin_48_[0]:18 0.0045 +6 left_top_grid_pin_48_[0]:18 left_top_grid_pin_48_[0]:17 0.0120625 +7 left_top_grid_pin_48_[0]:20 mux_left_track_5\/mux_l2_in_6_:A0 0.152 +8 left_top_grid_pin_48_[0]:20 left_top_grid_pin_48_[0]:19 0.001035714 +9 left_top_grid_pin_48_[0]:14 left_top_grid_pin_48_[0]:13 0.00341 +10 left_top_grid_pin_48_[0]:13 left_top_grid_pin_48_[0]:12 0.0002118916 +11 left_top_grid_pin_48_[0]:12 left_top_grid_pin_48_[0]:11 0.00341 +12 left_top_grid_pin_48_[0]:11 left_top_grid_pin_48_[0]:10 0.002447917 +13 left_top_grid_pin_48_[0]:9 left_top_grid_pin_48_[0]:8 0.0002839583 +14 left_top_grid_pin_48_[0]:10 left_top_grid_pin_48_[0]:9 0.00341 +15 left_top_grid_pin_48_[0]:7 left_top_grid_pin_48_[0]:6 0.0001057692 +16 left_top_grid_pin_48_[0]:8 left_top_grid_pin_48_[0]:7 0.00341 +17 left_top_grid_pin_48_[0]:5 left_top_grid_pin_48_[0]:4 0.0008370536 +18 left_top_grid_pin_48_[0]:6 left_top_grid_pin_48_[0]:5 0.0045 +19 left_top_grid_pin_48_[0]:4 mux_left_track_25\/mux_l2_in_3_:A1 0.152 +20 left_top_grid_pin_48_[0]:21 left_top_grid_pin_48_[0]:20 0.001348214 +21 left_top_grid_pin_48_[0]:22 left_top_grid_pin_48_[0]:21 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.01668435 //LENGTH 115.380 LUMPCC 0.002825614 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 54.585 115.600 +*I mux_top_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 92.360 55.760 +*I mux_top_track_8\/mux_l1_in_2_:S I *L 0.00357 *C 95.580 52.750 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 98.155 55.420 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 62.000 115.600 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 61.963 115.600 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 98.155 55.420 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 98.440 55.420 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 98.440 55.375 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 98.440 52.745 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 98.395 52.700 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 95.580 52.708 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 95.523 53.040 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 93.425 53.040 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 93.380 53.085 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 92.398 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 93.335 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 93.380 55.760 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 93.380 57.742 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 93.373 57.800 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 87.420 57.800 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 87.400 57.808 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 87.400 112.193 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 87.380 112.200 +*N mux_tree_tapbuf_size10_0_sram[0]:24 *C 60.728 112.200 +*N mux_tree_tapbuf_size10_0_sram[0]:25 *C 60.720 112.258 +*N mux_tree_tapbuf_size10_0_sram[0]:26 *C 60.720 115.555 +*N mux_tree_tapbuf_size10_0_sram[0]:27 *C 60.720 115.600 +*N mux_tree_tapbuf_size10_0_sram[0]:28 *C 54.623 115.600 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_8\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_8\/mux_l1_in_2_:S 1e-06 +3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 9.15928e-05 +6 mux_tree_tapbuf_size10_0_sram[0]:6 4.877384e-05 +7 mux_tree_tapbuf_size10_0_sram[0]:7 5.284951e-05 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.0001758973 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0001758973 +10 mux_tree_tapbuf_size10_0_sram[0]:10 0.0002606809 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.0002878777 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0002339994 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0002068025 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0001632497 +15 mux_tree_tapbuf_size10_0_sram[0]:15 9.213476e-05 +16 mux_tree_tapbuf_size10_0_sram[0]:16 9.213476e-05 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0002768077 +18 mux_tree_tapbuf_size10_0_sram[0]:18 7.994635e-05 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.0003539739 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.0003539739 +21 mux_tree_tapbuf_size10_0_sram[0]:21 0.003189176 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.003189176 +23 mux_tree_tapbuf_size10_0_sram[0]:23 0.001598177 +24 mux_tree_tapbuf_size10_0_sram[0]:24 0.001598177 +25 mux_tree_tapbuf_size10_0_sram[0]:25 0.0002304872 +26 mux_tree_tapbuf_size10_0_sram[0]:26 0.0002304872 +27 mux_tree_tapbuf_size10_0_sram[0]:27 0.0004986814 +28 mux_tree_tapbuf_size10_0_sram[0]:28 0.0003727813 +29 mux_tree_tapbuf_size10_0_sram[0]:18 prog_clk[0]:204 5.655151e-05 +30 mux_tree_tapbuf_size10_0_sram[0]:18 prog_clk[0]:208 2.028446e-06 +31 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:537 3.967521e-06 +32 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:542 9.523922e-05 +33 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:549 0.0001549489 +34 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:562 0.0001522066 +35 mux_tree_tapbuf_size10_0_sram[0]:23 prog_clk[0]:569 4.164692e-06 +36 mux_tree_tapbuf_size10_0_sram[0]:24 prog_clk[0]:542 3.967521e-06 +37 mux_tree_tapbuf_size10_0_sram[0]:24 prog_clk[0]:543 9.523922e-05 +38 mux_tree_tapbuf_size10_0_sram[0]:24 prog_clk[0]:562 0.0001549489 +39 mux_tree_tapbuf_size10_0_sram[0]:24 prog_clk[0]:563 0.0001522066 +40 mux_tree_tapbuf_size10_0_sram[0]:24 prog_clk[0]:570 4.164692e-06 +41 mux_tree_tapbuf_size10_0_sram[0]:14 prog_clk[0]:205 4.702036e-06 +42 mux_tree_tapbuf_size10_0_sram[0]:14 prog_clk[0]:214 2.192915e-05 +43 mux_tree_tapbuf_size10_0_sram[0]:17 prog_clk[0]:204 4.702036e-06 +44 mux_tree_tapbuf_size10_0_sram[0]:17 prog_clk[0]:205 5.655151e-05 +45 mux_tree_tapbuf_size10_0_sram[0]:17 prog_clk[0]:208 2.192915e-05 +46 mux_tree_tapbuf_size10_0_sram[0]:17 prog_clk[0]:214 2.028446e-06 +47 mux_tree_tapbuf_size10_0_sram[0]:21 chanx_right_in[3]:10 0.0005888396 +48 mux_tree_tapbuf_size10_0_sram[0]:22 chanx_right_in[3]:9 0.0005888396 +49 mux_tree_tapbuf_size10_0_sram[0]:19 chanx_right_in[15]:16 0.0003282294 +50 mux_tree_tapbuf_size10_0_sram[0]:20 chanx_right_in[15]:15 0.0003282294 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:28 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:11 mux_top_track_8\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.002513393 +3 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.00177009 +4 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.00341 +5 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.0009325583 +6 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.00341 +7 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.00341 +8 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.008520315 +9 mux_tree_tapbuf_size10_0_sram[0]:25 mux_tree_tapbuf_size10_0_sram[0]:24 0.00341 +10 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:23 0.004175558 +11 mux_tree_tapbuf_size10_0_sram[0]:27 mux_tree_tapbuf_size10_0_sram[0]:26 0.0045 +12 mux_tree_tapbuf_size10_0_sram[0]:27 mux_tree_tapbuf_size10_0_sram[0]:5 0.001109375 +13 mux_tree_tapbuf_size10_0_sram[0]:26 mux_tree_tapbuf_size10_0_sram[0]:25 0.002944197 +14 mux_tree_tapbuf_size10_0_sram[0]:10 mux_tree_tapbuf_size10_0_sram[0]:9 0.0045 +15 mux_tree_tapbuf_size10_0_sram[0]:9 mux_tree_tapbuf_size10_0_sram[0]:8 0.002348215 +16 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0001548913 +17 mux_tree_tapbuf_size10_0_sram[0]:8 mux_tree_tapbuf_size10_0_sram[0]:7 0.0045 +18 mux_tree_tapbuf_size10_0_sram[0]:6 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size10_0_sram[0]:28 mux_tree_tapbuf_size10_0_sram[0]:27 0.005444196 +20 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.001872768 +21 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +22 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.0008370537 +23 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.0045 +24 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:14 0.002388393 +25 mux_tree_tapbuf_size10_0_sram[0]:15 mux_top_track_8\/mux_l1_in_1_:S 0.152 +26 mux_tree_tapbuf_size10_0_sram[0]:5 mux_top_track_8\/mux_l1_in_0_:S 0.152 +27 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:11 0.000193314 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[1] 0.004916574 //LENGTH 36.100 LUMPCC 0.0004084386 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.545 74.800 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 63.140 69.020 +*I mux_top_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 63.120 66.980 +*I mux_top_track_24\/mux_l2_in_2_:S I *L 0.00357 *C 51.880 69.020 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 52.155 77.180 +*I mux_top_track_24\/mux_l2_in_3_:S I *L 0.00357 *C 56.220 66.935 +*N mux_tree_tapbuf_size10_2_sram[1]:6 *C 56.220 66.935 +*N mux_tree_tapbuf_size10_2_sram[1]:7 *C 52.155 77.180 +*N mux_tree_tapbuf_size10_2_sram[1]:8 *C 52.440 77.180 +*N mux_tree_tapbuf_size10_2_sram[1]:9 *C 52.440 77.135 +*N mux_tree_tapbuf_size10_2_sram[1]:10 *C 51.880 69.020 +*N mux_tree_tapbuf_size10_2_sram[1]:11 *C 51.980 69.020 +*N mux_tree_tapbuf_size10_2_sram[1]:12 *C 52.440 69.020 +*N mux_tree_tapbuf_size10_2_sram[1]:13 *C 52.440 66.685 +*N mux_tree_tapbuf_size10_2_sram[1]:14 *C 52.485 66.640 +*N mux_tree_tapbuf_size10_2_sram[1]:15 *C 56.220 66.640 +*N mux_tree_tapbuf_size10_2_sram[1]:16 *C 58.420 66.640 +*N mux_tree_tapbuf_size10_2_sram[1]:17 *C 58.420 66.980 +*N mux_tree_tapbuf_size10_2_sram[1]:18 *C 63.033 66.980 +*N mux_tree_tapbuf_size10_2_sram[1]:19 *C 63.020 67.025 +*N mux_tree_tapbuf_size10_2_sram[1]:20 *C 63.020 68.975 +*N mux_tree_tapbuf_size10_2_sram[1]:21 *C 63.178 69.020 +*N mux_tree_tapbuf_size10_2_sram[1]:22 *C 66.195 69.020 +*N mux_tree_tapbuf_size10_2_sram[1]:23 *C 66.240 69.065 +*N mux_tree_tapbuf_size10_2_sram[1]:24 *C 66.240 74.755 +*N mux_tree_tapbuf_size10_2_sram[1]:25 *C 66.240 74.800 +*N mux_tree_tapbuf_size10_2_sram[1]:26 *C 66.545 74.800 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_24\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_24\/mux_l2_in_2_:S 1e-06 +4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_top_track_24\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_2_sram[1]:6 5.650664e-05 +7 mux_tree_tapbuf_size10_2_sram[1]:7 6.010687e-05 +8 mux_tree_tapbuf_size10_2_sram[1]:8 6.309104e-05 +9 mux_tree_tapbuf_size10_2_sram[1]:9 0.0005366548 +10 mux_tree_tapbuf_size10_2_sram[1]:10 3.110709e-05 +11 mux_tree_tapbuf_size10_2_sram[1]:11 6.953848e-05 +12 mux_tree_tapbuf_size10_2_sram[1]:12 0.0007258606 +13 mux_tree_tapbuf_size10_2_sram[1]:13 0.0001536139 +14 mux_tree_tapbuf_size10_2_sram[1]:14 0.0002708762 +15 mux_tree_tapbuf_size10_2_sram[1]:15 0.0004646064 +16 mux_tree_tapbuf_size10_2_sram[1]:16 0.0001901435 +17 mux_tree_tapbuf_size10_2_sram[1]:17 0.000256621 +18 mux_tree_tapbuf_size10_2_sram[1]:18 0.0002313532 +19 mux_tree_tapbuf_size10_2_sram[1]:19 8.927609e-05 +20 mux_tree_tapbuf_size10_2_sram[1]:20 8.927609e-05 +21 mux_tree_tapbuf_size10_2_sram[1]:21 0.0001950137 +22 mux_tree_tapbuf_size10_2_sram[1]:22 0.0001950137 +23 mux_tree_tapbuf_size10_2_sram[1]:23 0.000348757 +24 mux_tree_tapbuf_size10_2_sram[1]:24 0.000348757 +25 mux_tree_tapbuf_size10_2_sram[1]:25 6.577053e-05 +26 mux_tree_tapbuf_size10_2_sram[1]:26 6.019155e-05 +27 mux_tree_tapbuf_size10_2_sram[1]:21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.292008e-05 +28 mux_tree_tapbuf_size10_2_sram[1]:20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.928046e-05 +29 mux_tree_tapbuf_size10_2_sram[1]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.928046e-05 +30 mux_tree_tapbuf_size10_2_sram[1]:22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.292008e-05 +31 mux_tree_tapbuf_size10_2_sram[1]:18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001320187 +32 mux_tree_tapbuf_size10_2_sram[1]:17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001320187 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_2_sram[1]:26 0.152 +1 mux_tree_tapbuf_size10_2_sram[1]:10 mux_top_track_24\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_2_sram[1]:11 mux_tree_tapbuf_size10_2_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size10_2_sram[1]:21 mux_top_track_24\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_2_sram[1]:21 mux_tree_tapbuf_size10_2_sram[1]:20 0.0045 +5 mux_tree_tapbuf_size10_2_sram[1]:14 mux_tree_tapbuf_size10_2_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size10_2_sram[1]:13 mux_tree_tapbuf_size10_2_sram[1]:12 0.002084821 +7 mux_tree_tapbuf_size10_2_sram[1]:8 mux_tree_tapbuf_size10_2_sram[1]:7 0.0001548913 +8 mux_tree_tapbuf_size10_2_sram[1]:9 mux_tree_tapbuf_size10_2_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size10_2_sram[1]:7 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_2_sram[1]:20 mux_tree_tapbuf_size10_2_sram[1]:19 0.001741072 +11 mux_tree_tapbuf_size10_2_sram[1]:18 mux_top_track_24\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_2_sram[1]:18 mux_tree_tapbuf_size10_2_sram[1]:17 0.004118304 +13 mux_tree_tapbuf_size10_2_sram[1]:19 mux_tree_tapbuf_size10_2_sram[1]:18 0.0045 +14 mux_tree_tapbuf_size10_2_sram[1]:6 mux_top_track_24\/mux_l2_in_3_:S 0.152 +15 mux_tree_tapbuf_size10_2_sram[1]:22 mux_tree_tapbuf_size10_2_sram[1]:21 0.002694197 +16 mux_tree_tapbuf_size10_2_sram[1]:23 mux_tree_tapbuf_size10_2_sram[1]:22 0.0045 +17 mux_tree_tapbuf_size10_2_sram[1]:25 mux_tree_tapbuf_size10_2_sram[1]:24 0.0045 +18 mux_tree_tapbuf_size10_2_sram[1]:24 mux_tree_tapbuf_size10_2_sram[1]:23 0.005080357 +19 mux_tree_tapbuf_size10_2_sram[1]:26 mux_tree_tapbuf_size10_2_sram[1]:25 0.0001657609 +20 mux_tree_tapbuf_size10_2_sram[1]:15 mux_tree_tapbuf_size10_2_sram[1]:14 0.003334821 +21 mux_tree_tapbuf_size10_2_sram[1]:15 mux_tree_tapbuf_size10_2_sram[1]:6 0.0001271552 +22 mux_tree_tapbuf_size10_2_sram[1]:16 mux_tree_tapbuf_size10_2_sram[1]:15 0.001964286 +23 mux_tree_tapbuf_size10_2_sram[1]:17 mux_tree_tapbuf_size10_2_sram[1]:16 0.0003035715 +24 mux_tree_tapbuf_size10_2_sram[1]:12 mux_tree_tapbuf_size10_2_sram[1]:11 0.0004107143 +25 mux_tree_tapbuf_size10_2_sram[1]:12 mux_tree_tapbuf_size10_2_sram[1]:9 0.007245536 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[3] 0.001599135 //LENGTH 14.035 LUMPCC 0.0001037138 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 106.565 26.180 +*I mux_bottom_track_9\/mux_l4_in_0_:S I *L 0.00357 *C 101.760 20.400 +*I mem_bottom_track_9\/FTB_19__70:A I *L 0.001746 *C 106.720 28.560 +*N mux_tree_tapbuf_size10_6_sram[3]:3 *C 106.720 28.560 +*N mux_tree_tapbuf_size10_6_sram[3]:4 *C 106.720 28.515 +*N mux_tree_tapbuf_size10_6_sram[3]:5 *C 101.797 20.400 +*N mux_tree_tapbuf_size10_6_sram[3]:6 *C 106.675 20.400 +*N mux_tree_tapbuf_size10_6_sram[3]:7 *C 106.720 20.445 +*N mux_tree_tapbuf_size10_6_sram[3]:8 *C 106.720 26.180 +*N mux_tree_tapbuf_size10_6_sram[3]:9 *C 106.720 26.180 +*N mux_tree_tapbuf_size10_6_sram[3]:10 *C 106.565 26.180 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_track_9\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_track_9\/FTB_19__70:A 1e-06 +3 mux_tree_tapbuf_size10_6_sram[3]:3 2.972031e-05 +4 mux_tree_tapbuf_size10_6_sram[3]:4 0.0001262399 +5 mux_tree_tapbuf_size10_6_sram[3]:5 0.0003063518 +6 mux_tree_tapbuf_size10_6_sram[3]:6 0.0003063518 +7 mux_tree_tapbuf_size10_6_sram[3]:7 0.0002397713 +8 mux_tree_tapbuf_size10_6_sram[3]:8 0.0003909844 +9 mux_tree_tapbuf_size10_6_sram[3]:9 4.852329e-05 +10 mux_tree_tapbuf_size10_6_sram[3]:10 4.447801e-05 +11 mux_tree_tapbuf_size10_6_sram[3]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 3.645044e-06 +12 mux_tree_tapbuf_size10_6_sram[3]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 1.833697e-05 +13 mux_tree_tapbuf_size10_6_sram[3]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 2.987487e-05 +14 mux_tree_tapbuf_size10_6_sram[3]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 1.833697e-05 +15 mux_tree_tapbuf_size10_6_sram[3]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 2.987487e-05 +16 mux_tree_tapbuf_size10_6_sram[3]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 3.645044e-06 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_6_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_6_sram[3]:9 mux_tree_tapbuf_size10_6_sram[3]:8 0.0045 +2 mux_tree_tapbuf_size10_6_sram[3]:8 mux_tree_tapbuf_size10_6_sram[3]:7 0.005120536 +3 mux_tree_tapbuf_size10_6_sram[3]:8 mux_tree_tapbuf_size10_6_sram[3]:4 0.002084821 +4 mux_tree_tapbuf_size10_6_sram[3]:10 mux_tree_tapbuf_size10_6_sram[3]:9 8.423912e-05 +5 mux_tree_tapbuf_size10_6_sram[3]:6 mux_tree_tapbuf_size10_6_sram[3]:5 0.004354911 +6 mux_tree_tapbuf_size10_6_sram[3]:7 mux_tree_tapbuf_size10_6_sram[3]:6 0.0045 +7 mux_tree_tapbuf_size10_6_sram[3]:5 mux_bottom_track_9\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_6_sram[3]:3 mem_bottom_track_9\/FTB_19__70:A 0.152 +9 mux_tree_tapbuf_size10_6_sram[3]:4 mux_tree_tapbuf_size10_6_sram[3]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_9_sram[3] 0.002684578 //LENGTH 18.755 LUMPCC 0.0005387026 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 43.085 71.740 +*I mem_left_track_9\/FTB_22__73:A I *L 0.001746 *C 34.960 69.360 +*I mux_left_track_9\/mux_l4_in_0_:S I *L 0.00357 *C 33.220 74.510 +*N mux_tree_tapbuf_size10_9_sram[3]:3 *C 33.220 74.510 +*N mux_tree_tapbuf_size10_9_sram[3]:4 *C 33.220 74.120 +*N mux_tree_tapbuf_size10_9_sram[3]:5 *C 34.960 69.360 +*N mux_tree_tapbuf_size10_9_sram[3]:6 *C 34.960 69.405 +*N mux_tree_tapbuf_size10_9_sram[3]:7 *C 34.960 74.075 +*N mux_tree_tapbuf_size10_9_sram[3]:8 *C 34.960 74.120 +*N mux_tree_tapbuf_size10_9_sram[3]:9 *C 38.135 74.120 +*N mux_tree_tapbuf_size10_9_sram[3]:10 *C 38.180 74.075 +*N mux_tree_tapbuf_size10_9_sram[3]:11 *C 38.180 71.785 +*N mux_tree_tapbuf_size10_9_sram[3]:12 *C 38.225 71.740 +*N mux_tree_tapbuf_size10_9_sram[3]:13 *C 43.047 71.740 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_track_9\/FTB_22__73:A 1e-06 +2 mux_left_track_9\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_9_sram[3]:3 6.363523e-05 +4 mux_tree_tapbuf_size10_9_sram[3]:4 0.0001596779 +5 mux_tree_tapbuf_size10_9_sram[3]:5 3.437167e-05 +6 mux_tree_tapbuf_size10_9_sram[3]:6 0.0001856289 +7 mux_tree_tapbuf_size10_9_sram[3]:7 0.0001856289 +8 mux_tree_tapbuf_size10_9_sram[3]:8 0.0003931802 +9 mux_tree_tapbuf_size10_9_sram[3]:9 0.0002266808 +10 mux_tree_tapbuf_size10_9_sram[3]:10 0.0002011648 +11 mux_tree_tapbuf_size10_9_sram[3]:11 0.0002011648 +12 mux_tree_tapbuf_size10_9_sram[3]:12 0.0002458707 +13 mux_tree_tapbuf_size10_9_sram[3]:13 0.0002458707 +14 mux_tree_tapbuf_size10_9_sram[3]:7 chanx_right_in[16]:21 1.716433e-05 +15 mux_tree_tapbuf_size10_9_sram[3]:6 chanx_right_in[16]:22 1.716433e-05 +16 mux_tree_tapbuf_size10_9_sram[3]:13 chanx_right_in[16]:24 0.0001125336 +17 mux_tree_tapbuf_size10_9_sram[3]:13 chanx_right_in[16]:28 1.889096e-05 +18 mux_tree_tapbuf_size10_9_sram[3]:12 chanx_right_in[16]:23 0.0001125336 +19 mux_tree_tapbuf_size10_9_sram[3]:12 chanx_right_in[16]:27 1.889096e-05 +20 mux_tree_tapbuf_size10_9_sram[3]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001205539 +21 mux_tree_tapbuf_size10_9_sram[3]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001205539 +22 mux_tree_tapbuf_size10_9_sram[3]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.085451e-07 +23 mux_tree_tapbuf_size10_9_sram[3]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.085451e-07 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_9_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_9_sram[3]:8 mux_tree_tapbuf_size10_9_sram[3]:7 0.0045 +2 mux_tree_tapbuf_size10_9_sram[3]:8 mux_tree_tapbuf_size10_9_sram[3]:4 0.001553571 +3 mux_tree_tapbuf_size10_9_sram[3]:7 mux_tree_tapbuf_size10_9_sram[3]:6 0.004169643 +4 mux_tree_tapbuf_size10_9_sram[3]:5 mem_left_track_9\/FTB_22__73:A 0.152 +5 mux_tree_tapbuf_size10_9_sram[3]:6 mux_tree_tapbuf_size10_9_sram[3]:5 0.0045 +6 mux_tree_tapbuf_size10_9_sram[3]:13 mux_tree_tapbuf_size10_9_sram[3]:12 0.004305804 +7 mux_tree_tapbuf_size10_9_sram[3]:12 mux_tree_tapbuf_size10_9_sram[3]:11 0.0045 +8 mux_tree_tapbuf_size10_9_sram[3]:11 mux_tree_tapbuf_size10_9_sram[3]:10 0.002044643 +9 mux_tree_tapbuf_size10_9_sram[3]:9 mux_tree_tapbuf_size10_9_sram[3]:8 0.002834821 +10 mux_tree_tapbuf_size10_9_sram[3]:10 mux_tree_tapbuf_size10_9_sram[3]:9 0.0045 +11 mux_tree_tapbuf_size10_9_sram[3]:3 mux_left_track_9\/mux_l4_in_0_:S 0.152 +12 mux_tree_tapbuf_size10_9_sram[3]:4 mux_tree_tapbuf_size10_9_sram[3]:3 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_9_ccff_tail[0] 0.0009090616 //LENGTH 5.820 LUMPCC 0.0003433014 DR + +*CONN +*I mem_left_track_9\/FTB_22__73:X O *L 0 *C 37.955 68.680 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 40.655 66.300 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:2 *C 40.655 66.300 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:3 *C 40.480 66.300 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 *C 40.480 66.345 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 *C 40.480 68.635 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 *C 40.435 68.680 +*N mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 *C 37.992 68.680 + +*CAP +0 mem_left_track_9\/FTB_22__73:X 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:2 5.161576e-05 +3 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:3 5.614508e-05 +4 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 0.0001154174 +5 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 0.0001154174 +6 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 0.0001125823 +7 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 0.0001125823 +8 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 chanx_left_in[15]:7 6.846568e-05 +9 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 chanx_left_in[15]:8 6.846568e-05 +10 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 mux_tree_tapbuf_size10_9_sram[2]:12 0.000103185 +11 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 mux_tree_tapbuf_size10_9_sram[2]:11 0.000103185 + +*RES +0 mem_left_track_9\/FTB_22__73:X mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 0.002180804 + +*END + +*D_NET mux_tree_tapbuf_size12_3_sram[1] 0.0056532 //LENGTH 43.500 LUMPCC 0.0006682669 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 109.785 99.280 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 103.215 93.500 +*I mux_right_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 109.840 90.830 +*I mux_right_track_2\/mux_l2_in_2_:S I *L 0.00357 *C 112.600 88.695 +*I mux_right_track_2\/mux_l2_in_3_:S I *L 0.00357 *C 117.660 88.400 +*I mux_right_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 116.740 96.560 +*N mux_tree_tapbuf_size12_3_sram[1]:6 *C 116.740 96.560 +*N mux_tree_tapbuf_size12_3_sram[1]:7 *C 116.840 96.605 +*N mux_tree_tapbuf_size12_3_sram[1]:8 *C 116.840 99.575 +*N mux_tree_tapbuf_size12_3_sram[1]:9 *C 116.795 99.620 +*N mux_tree_tapbuf_size12_3_sram[1]:10 *C 117.623 88.400 +*N mux_tree_tapbuf_size12_3_sram[1]:11 *C 112.675 88.400 +*N mux_tree_tapbuf_size12_3_sram[1]:12 *C 112.620 88.400 +*N mux_tree_tapbuf_size12_3_sram[1]:13 *C 112.600 88.695 +*N mux_tree_tapbuf_size12_3_sram[1]:14 *C 112.600 89.080 +*N mux_tree_tapbuf_size12_3_sram[1]:15 *C 110.445 89.080 +*N mux_tree_tapbuf_size12_3_sram[1]:16 *C 110.400 89.125 +*N mux_tree_tapbuf_size12_3_sram[1]:17 *C 109.840 90.830 +*N mux_tree_tapbuf_size12_3_sram[1]:18 *C 103.253 93.500 +*N mux_tree_tapbuf_size12_3_sram[1]:19 *C 104.375 93.500 +*N mux_tree_tapbuf_size12_3_sram[1]:20 *C 104.420 93.455 +*N mux_tree_tapbuf_size12_3_sram[1]:21 *C 104.420 91.165 +*N mux_tree_tapbuf_size12_3_sram[1]:22 *C 104.465 91.120 +*N mux_tree_tapbuf_size12_3_sram[1]:23 *C 109.803 91.120 +*N mux_tree_tapbuf_size12_3_sram[1]:24 *C 110.400 91.120 +*N mux_tree_tapbuf_size12_3_sram[1]:25 *C 110.400 90.780 +*N mux_tree_tapbuf_size12_3_sram[1]:26 *C 110.400 90.780 +*N mux_tree_tapbuf_size12_3_sram[1]:27 *C 110.400 99.575 +*N mux_tree_tapbuf_size12_3_sram[1]:28 *C 110.445 99.620 +*N mux_tree_tapbuf_size12_3_sram[1]:29 *C 110.860 99.620 +*N mux_tree_tapbuf_size12_3_sram[1]:30 *C 110.860 99.280 +*N mux_tree_tapbuf_size12_3_sram[1]:31 *C 109.823 99.280 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_2\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_2\/mux_l2_in_2_:S 1e-06 +4 mux_right_track_2\/mux_l2_in_3_:S 1e-06 +5 mux_right_track_2\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size12_3_sram[1]:6 2.960782e-05 +7 mux_tree_tapbuf_size12_3_sram[1]:7 0.0001571592 +8 mux_tree_tapbuf_size12_3_sram[1]:8 0.0001571592 +9 mux_tree_tapbuf_size12_3_sram[1]:9 0.000276309 +10 mux_tree_tapbuf_size12_3_sram[1]:10 0.0003853748 +11 mux_tree_tapbuf_size12_3_sram[1]:11 0.0004211643 +12 mux_tree_tapbuf_size12_3_sram[1]:12 2.95481e-05 +13 mux_tree_tapbuf_size12_3_sram[1]:13 0.0001007121 +14 mux_tree_tapbuf_size12_3_sram[1]:14 0.0001960036 +15 mux_tree_tapbuf_size12_3_sram[1]:15 0.0001711502 +16 mux_tree_tapbuf_size12_3_sram[1]:16 0.0001090768 +17 mux_tree_tapbuf_size12_3_sram[1]:17 2.338765e-05 +18 mux_tree_tapbuf_size12_3_sram[1]:18 9.576767e-05 +19 mux_tree_tapbuf_size12_3_sram[1]:19 9.576767e-05 +20 mux_tree_tapbuf_size12_3_sram[1]:20 0.0001522796 +21 mux_tree_tapbuf_size12_3_sram[1]:21 0.0001522796 +22 mux_tree_tapbuf_size12_3_sram[1]:22 0.0003051338 +23 mux_tree_tapbuf_size12_3_sram[1]:23 0.0003758055 +24 mux_tree_tapbuf_size12_3_sram[1]:24 8.738927e-05 +25 mux_tree_tapbuf_size12_3_sram[1]:25 6.722912e-05 +26 mux_tree_tapbuf_size12_3_sram[1]:26 0.0006233283 +27 mux_tree_tapbuf_size12_3_sram[1]:27 0.0004800708 +28 mux_tree_tapbuf_size12_3_sram[1]:28 3.438982e-05 +29 mux_tree_tapbuf_size12_3_sram[1]:29 0.000337698 +30 mux_tree_tapbuf_size12_3_sram[1]:30 7.106981e-05 +31 mux_tree_tapbuf_size12_3_sram[1]:31 4.407064e-05 +32 mux_tree_tapbuf_size12_3_sram[1]:26 mux_tree_tapbuf_size12_3_sram[2]:17 0.0001307101 +33 mux_tree_tapbuf_size12_3_sram[1]:9 mux_tree_tapbuf_size12_3_sram[2]:14 7.238237e-05 +34 mux_tree_tapbuf_size12_3_sram[1]:8 mux_tree_tapbuf_size12_3_sram[2]:13 2.308112e-05 +35 mux_tree_tapbuf_size12_3_sram[1]:8 mux_tree_tapbuf_size12_3_sram[2]:12 2.470081e-06 +36 mux_tree_tapbuf_size12_3_sram[1]:7 mux_tree_tapbuf_size12_3_sram[2]:11 2.470081e-06 +37 mux_tree_tapbuf_size12_3_sram[1]:7 mux_tree_tapbuf_size12_3_sram[2]:12 2.308112e-05 +38 mux_tree_tapbuf_size12_3_sram[1]:31 mux_tree_tapbuf_size12_3_sram[2]:15 1.970802e-05 +39 mux_tree_tapbuf_size12_3_sram[1]:28 mux_tree_tapbuf_size12_3_sram[2]:15 4.327057e-06 +40 mux_tree_tapbuf_size12_3_sram[1]:27 mux_tree_tapbuf_size12_3_sram[2]:16 0.0001307101 +41 mux_tree_tapbuf_size12_3_sram[1]:30 mux_tree_tapbuf_size12_3_sram[2]:14 1.970802e-05 +42 mux_tree_tapbuf_size12_3_sram[1]:29 mux_tree_tapbuf_size12_3_sram[2]:15 7.238237e-05 +43 mux_tree_tapbuf_size12_3_sram[1]:29 mux_tree_tapbuf_size12_3_sram[2]:14 4.327057e-06 +44 mux_tree_tapbuf_size12_3_sram[1]:25 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.073512e-06 +45 mux_tree_tapbuf_size12_3_sram[1]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.412322e-06 +46 mux_tree_tapbuf_size12_3_sram[1]:22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.796887e-05 +47 mux_tree_tapbuf_size12_3_sram[1]:23 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.412322e-06 +48 mux_tree_tapbuf_size12_3_sram[1]:23 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.796887e-05 +49 mux_tree_tapbuf_size12_3_sram[1]:24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.073512e-06 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_3_sram[1]:31 0.152 +1 mux_tree_tapbuf_size12_3_sram[1]:25 mux_tree_tapbuf_size12_3_sram[1]:24 0.0003035715 +2 mux_tree_tapbuf_size12_3_sram[1]:26 mux_tree_tapbuf_size12_3_sram[1]:25 0.0045 +3 mux_tree_tapbuf_size12_3_sram[1]:26 mux_tree_tapbuf_size12_3_sram[1]:16 0.001477679 +4 mux_tree_tapbuf_size12_3_sram[1]:15 mux_tree_tapbuf_size12_3_sram[1]:14 0.001924107 +5 mux_tree_tapbuf_size12_3_sram[1]:16 mux_tree_tapbuf_size12_3_sram[1]:15 0.0045 +6 mux_tree_tapbuf_size12_3_sram[1]:13 mux_right_track_2\/mux_l2_in_2_:S 0.152 +7 mux_tree_tapbuf_size12_3_sram[1]:13 mux_tree_tapbuf_size12_3_sram[1]:12 0.0002633929 +8 mux_tree_tapbuf_size12_3_sram[1]:13 mux_tree_tapbuf_size12_3_sram[1]:11 0.0002633929 +9 mux_tree_tapbuf_size12_3_sram[1]:9 mux_tree_tapbuf_size12_3_sram[1]:8 0.0045 +10 mux_tree_tapbuf_size12_3_sram[1]:8 mux_tree_tapbuf_size12_3_sram[1]:7 0.002651786 +11 mux_tree_tapbuf_size12_3_sram[1]:6 mux_right_track_2\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size12_3_sram[1]:7 mux_tree_tapbuf_size12_3_sram[1]:6 0.0045 +13 mux_tree_tapbuf_size12_3_sram[1]:17 mux_right_track_2\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size12_3_sram[1]:10 mux_right_track_2\/mux_l2_in_3_:S 0.152 +15 mux_tree_tapbuf_size12_3_sram[1]:31 mux_tree_tapbuf_size12_3_sram[1]:30 0.0009263393 +16 mux_tree_tapbuf_size12_3_sram[1]:28 mux_tree_tapbuf_size12_3_sram[1]:27 0.0045 +17 mux_tree_tapbuf_size12_3_sram[1]:27 mux_tree_tapbuf_size12_3_sram[1]:26 0.007852679 +18 mux_tree_tapbuf_size12_3_sram[1]:22 mux_tree_tapbuf_size12_3_sram[1]:21 0.0045 +19 mux_tree_tapbuf_size12_3_sram[1]:21 mux_tree_tapbuf_size12_3_sram[1]:20 0.002044643 +20 mux_tree_tapbuf_size12_3_sram[1]:19 mux_tree_tapbuf_size12_3_sram[1]:18 0.001002232 +21 mux_tree_tapbuf_size12_3_sram[1]:20 mux_tree_tapbuf_size12_3_sram[1]:19 0.0045 +22 mux_tree_tapbuf_size12_3_sram[1]:18 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +23 mux_tree_tapbuf_size12_3_sram[1]:23 mux_tree_tapbuf_size12_3_sram[1]:22 0.004765625 +24 mux_tree_tapbuf_size12_3_sram[1]:23 mux_tree_tapbuf_size12_3_sram[1]:17 0.000125 +25 mux_tree_tapbuf_size12_3_sram[1]:30 mux_tree_tapbuf_size12_3_sram[1]:29 0.0003035715 +26 mux_tree_tapbuf_size12_3_sram[1]:24 mux_tree_tapbuf_size12_3_sram[1]:23 0.0005334822 +27 mux_tree_tapbuf_size12_3_sram[1]:14 mux_tree_tapbuf_size12_3_sram[1]:13 0.00034375 +28 mux_tree_tapbuf_size12_3_sram[1]:29 mux_tree_tapbuf_size12_3_sram[1]:28 0.0003705357 +29 mux_tree_tapbuf_size12_3_sram[1]:29 mux_tree_tapbuf_size12_3_sram[1]:9 0.005299107 +30 mux_tree_tapbuf_size12_3_sram[1]:11 mux_tree_tapbuf_size12_3_sram[1]:10 0.004417411 + +*END + +*D_NET mux_tree_tapbuf_size12_7_sram[2] 0.003930843 //LENGTH 25.555 LUMPCC 0.001652112 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 39.865 97.075 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 32.835 102.340 +*I mux_left_track_3\/mux_l3_in_1_:S I *L 0.00357 *C 27.500 99.280 +*I mux_left_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 44.720 96.560 +*N mux_tree_tapbuf_size12_7_sram[2]:4 *C 44.683 96.560 +*N mux_tree_tapbuf_size12_7_sram[2]:5 *C 43.700 96.560 +*N mux_tree_tapbuf_size12_7_sram[2]:6 *C 43.700 96.900 +*N mux_tree_tapbuf_size12_7_sram[2]:7 *C 27.500 99.280 +*N mux_tree_tapbuf_size12_7_sram[2]:8 *C 27.600 99.280 +*N mux_tree_tapbuf_size12_7_sram[2]:9 *C 27.608 99.280 +*N mux_tree_tapbuf_size12_7_sram[2]:10 *C 32.873 102.340 +*N mux_tree_tapbuf_size12_7_sram[2]:11 *C 33.535 102.340 +*N mux_tree_tapbuf_size12_7_sram[2]:12 *C 33.580 102.295 +*N mux_tree_tapbuf_size12_7_sram[2]:13 *C 33.580 99.338 +*N mux_tree_tapbuf_size12_7_sram[2]:14 *C 33.580 99.280 +*N mux_tree_tapbuf_size12_7_sram[2]:15 *C 38.172 99.280 +*N mux_tree_tapbuf_size12_7_sram[2]:16 *C 38.180 99.223 +*N mux_tree_tapbuf_size12_7_sram[2]:17 *C 38.180 96.945 +*N mux_tree_tapbuf_size12_7_sram[2]:18 *C 38.225 96.900 +*N mux_tree_tapbuf_size12_7_sram[2]:19 *C 39.865 97.075 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_left_track_3\/mux_l3_in_1_:S 1e-06 +3 mux_left_track_3\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size12_7_sram[2]:4 8.769231e-05 +5 mux_tree_tapbuf_size12_7_sram[2]:5 0.0001156671 +6 mux_tree_tapbuf_size12_7_sram[2]:6 0.0002406875 +7 mux_tree_tapbuf_size12_7_sram[2]:7 2.640582e-05 +8 mux_tree_tapbuf_size12_7_sram[2]:8 3.270085e-05 +9 mux_tree_tapbuf_size12_7_sram[2]:9 0.0001734411 +10 mux_tree_tapbuf_size12_7_sram[2]:10 6.743085e-05 +11 mux_tree_tapbuf_size12_7_sram[2]:11 6.743085e-05 +12 mux_tree_tapbuf_size12_7_sram[2]:12 0.0001784851 +13 mux_tree_tapbuf_size12_7_sram[2]:13 0.0001784851 +14 mux_tree_tapbuf_size12_7_sram[2]:14 0.0002895751 +15 mux_tree_tapbuf_size12_7_sram[2]:15 0.000116134 +16 mux_tree_tapbuf_size12_7_sram[2]:16 0.0001381085 +17 mux_tree_tapbuf_size12_7_sram[2]:17 0.0001381085 +18 mux_tree_tapbuf_size12_7_sram[2]:18 9.084336e-05 +19 mux_tree_tapbuf_size12_7_sram[2]:19 0.0003335348 +20 mux_tree_tapbuf_size12_7_sram[2]:9 chanx_left_in[12]:37 0.0003401015 +21 mux_tree_tapbuf_size12_7_sram[2]:15 chanx_left_in[12]:36 0.0002642014 +22 mux_tree_tapbuf_size12_7_sram[2]:14 chanx_left_in[12]:36 0.0003401015 +23 mux_tree_tapbuf_size12_7_sram[2]:14 chanx_left_in[12]:37 0.0002642014 +24 mux_tree_tapbuf_size12_7_sram[2]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.939477e-05 +25 mux_tree_tapbuf_size12_7_sram[2]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.708596e-06 +26 mux_tree_tapbuf_size12_7_sram[2]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 7.12544e-05 +27 mux_tree_tapbuf_size12_7_sram[2]:18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 1.532935e-05 +28 mux_tree_tapbuf_size12_7_sram[2]:17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 6.708596e-06 +29 mux_tree_tapbuf_size12_7_sram[2]:19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 4.491979e-05 +30 mux_tree_tapbuf_size12_7_sram[2]:19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 1.532935e-05 +31 mux_tree_tapbuf_size12_7_sram[2]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 7.12544e-05 +32 mux_tree_tapbuf_size12_7_sram[2]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.939477e-05 +33 mux_tree_tapbuf_size12_7_sram[2]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 1.414601e-05 +34 mux_tree_tapbuf_size12_7_sram[2]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 4.491979e-05 +35 mux_tree_tapbuf_size12_7_sram[2]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 1.414601e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_7_sram[2]:19 0.152 +1 mux_tree_tapbuf_size12_7_sram[2]:8 mux_tree_tapbuf_size12_7_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size12_7_sram[2]:9 mux_tree_tapbuf_size12_7_sram[2]:8 0.00341 +3 mux_tree_tapbuf_size12_7_sram[2]:7 mux_left_track_3\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size12_7_sram[2]:16 mux_tree_tapbuf_size12_7_sram[2]:15 0.00341 +5 mux_tree_tapbuf_size12_7_sram[2]:15 mux_tree_tapbuf_size12_7_sram[2]:14 0.0007194916 +6 mux_tree_tapbuf_size12_7_sram[2]:18 mux_tree_tapbuf_size12_7_sram[2]:17 0.0045 +7 mux_tree_tapbuf_size12_7_sram[2]:17 mux_tree_tapbuf_size12_7_sram[2]:16 0.002033482 +8 mux_tree_tapbuf_size12_7_sram[2]:19 mux_tree_tapbuf_size12_7_sram[2]:18 0.001464286 +9 mux_tree_tapbuf_size12_7_sram[2]:19 mux_tree_tapbuf_size12_7_sram[2]:6 0.003424107 +10 mux_tree_tapbuf_size12_7_sram[2]:13 mux_tree_tapbuf_size12_7_sram[2]:12 0.002640625 +11 mux_tree_tapbuf_size12_7_sram[2]:14 mux_tree_tapbuf_size12_7_sram[2]:13 0.00341 +12 mux_tree_tapbuf_size12_7_sram[2]:14 mux_tree_tapbuf_size12_7_sram[2]:9 0.0009356916 +13 mux_tree_tapbuf_size12_7_sram[2]:11 mux_tree_tapbuf_size12_7_sram[2]:10 0.0005915179 +14 mux_tree_tapbuf_size12_7_sram[2]:12 mux_tree_tapbuf_size12_7_sram[2]:11 0.0045 +15 mux_tree_tapbuf_size12_7_sram[2]:10 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +16 mux_tree_tapbuf_size12_7_sram[2]:4 mux_left_track_3\/mux_l3_in_0_:S 0.152 +17 mux_tree_tapbuf_size12_7_sram[2]:6 mux_tree_tapbuf_size12_7_sram[2]:5 0.0003035715 +18 mux_tree_tapbuf_size12_7_sram[2]:5 mux_tree_tapbuf_size12_7_sram[2]:4 0.0008772322 + +*END + +*D_NET mux_tree_tapbuf_size16_2_sram[2] 0.004482176 //LENGTH 36.325 LUMPCC 0.0008438096 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 32.965 36.720 +*I mux_bottom_track_5\/mux_l3_in_3_:S I *L 0.00357 *C 35.780 34.000 +*I mux_bottom_track_5\/mux_l3_in_1_:S I *L 0.00357 *C 35.320 25.160 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 37.860 22.780 +*I mux_bottom_track_5\/mux_l3_in_2_:S I *L 0.00357 *C 35.780 12.920 +*I mux_bottom_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 38.520 36.380 +*N mux_tree_tapbuf_size16_2_sram[2]:6 *C 38.483 36.380 +*N mux_tree_tapbuf_size16_2_sram[2]:7 *C 35.818 12.920 +*N mux_tree_tapbuf_size16_2_sram[2]:8 *C 36.295 12.920 +*N mux_tree_tapbuf_size16_2_sram[2]:9 *C 36.340 12.965 +*N mux_tree_tapbuf_size16_2_sram[2]:10 *C 37.837 22.753 +*N mux_tree_tapbuf_size16_2_sram[2]:11 *C 37.825 22.440 +*N mux_tree_tapbuf_size16_2_sram[2]:12 *C 36.385 22.440 +*N mux_tree_tapbuf_size16_2_sram[2]:13 *C 36.340 22.440 +*N mux_tree_tapbuf_size16_2_sram[2]:14 *C 36.340 25.500 +*N mux_tree_tapbuf_size16_2_sram[2]:15 *C 35.358 25.160 +*N mux_tree_tapbuf_size16_2_sram[2]:16 *C 35.835 25.160 +*N mux_tree_tapbuf_size16_2_sram[2]:17 *C 35.910 25.190 +*N mux_tree_tapbuf_size16_2_sram[2]:18 *C 35.880 25.500 +*N mux_tree_tapbuf_size16_2_sram[2]:19 *C 35.780 34.000 +*N mux_tree_tapbuf_size16_2_sram[2]:20 *C 35.880 33.660 +*N mux_tree_tapbuf_size16_2_sram[2]:21 *C 35.880 33.660 +*N mux_tree_tapbuf_size16_2_sram[2]:22 *C 35.880 36.335 +*N mux_tree_tapbuf_size16_2_sram[2]:23 *C 35.880 36.380 +*N mux_tree_tapbuf_size16_2_sram[2]:24 *C 35.880 36.720 +*N mux_tree_tapbuf_size16_2_sram[2]:25 *C 33.003 36.720 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_5\/mux_l3_in_3_:S 1e-06 +2 mux_bottom_track_5\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_bottom_track_5\/mux_l3_in_2_:S 1e-06 +5 mux_bottom_track_5\/mux_l3_in_0_:S 1e-06 +6 mux_tree_tapbuf_size16_2_sram[2]:6 0.0001789973 +7 mux_tree_tapbuf_size16_2_sram[2]:7 5.600475e-05 +8 mux_tree_tapbuf_size16_2_sram[2]:8 5.600475e-05 +9 mux_tree_tapbuf_size16_2_sram[2]:9 0.0003689273 +10 mux_tree_tapbuf_size16_2_sram[2]:10 3.45015e-05 +11 mux_tree_tapbuf_size16_2_sram[2]:11 0.0001493973 +12 mux_tree_tapbuf_size16_2_sram[2]:12 0.0001148958 +13 mux_tree_tapbuf_size16_2_sram[2]:13 0.0005669667 +14 mux_tree_tapbuf_size16_2_sram[2]:14 0.0001603093 +15 mux_tree_tapbuf_size16_2_sram[2]:15 6.171533e-05 +16 mux_tree_tapbuf_size16_2_sram[2]:16 6.171533e-05 +17 mux_tree_tapbuf_size16_2_sram[2]:17 1.180957e-05 +18 mux_tree_tapbuf_size16_2_sram[2]:18 0.0003636933 +19 mux_tree_tapbuf_size16_2_sram[2]:19 6.135918e-05 +20 mux_tree_tapbuf_size16_2_sram[2]:20 6.632651e-05 +21 mux_tree_tapbuf_size16_2_sram[2]:21 0.0005428942 +22 mux_tree_tapbuf_size16_2_sram[2]:22 0.0001505815 +23 mux_tree_tapbuf_size16_2_sram[2]:23 0.0002082451 +24 mux_tree_tapbuf_size16_2_sram[2]:24 0.0002236346 +25 mux_tree_tapbuf_size16_2_sram[2]:25 0.0001943869 +26 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[1]:33 1.910399e-05 +27 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[1]:36 1.970655e-05 +28 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[1]:37 0.0001484234 +29 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[1]:40 4.01725e-05 +30 mux_tree_tapbuf_size16_2_sram[2]:21 mux_tree_tapbuf_size16_2_sram[1]:33 0.0001430949 +31 mux_tree_tapbuf_size16_2_sram[2]:9 mux_tree_tapbuf_size16_2_sram[1]:36 1.910399e-05 +32 mux_tree_tapbuf_size16_2_sram[2]:9 mux_tree_tapbuf_size16_2_sram[1]:40 0.0001484234 +33 mux_tree_tapbuf_size16_2_sram[2]:9 mux_tree_tapbuf_size16_2_sram[1]:41 4.01725e-05 +34 mux_tree_tapbuf_size16_2_sram[2]:17 mux_tree_tapbuf_size16_2_sram[1]:36 1.485083e-05 +35 mux_tree_tapbuf_size16_2_sram[2]:18 mux_tree_tapbuf_size16_2_sram[1]:33 1.485083e-05 +36 mux_tree_tapbuf_size16_2_sram[2]:18 mux_tree_tapbuf_size16_2_sram[1]:36 0.0001430949 +37 mux_tree_tapbuf_size16_2_sram[2]:14 mux_tree_tapbuf_size16_2_sram[1]:33 1.970655e-05 +38 mux_tree_tapbuf_size16_2_sram[2]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 1.780411e-07 +39 mux_tree_tapbuf_size16_2_sram[2]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 1.780411e-07 +40 mux_tree_tapbuf_size16_2_sram[2]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 3.637469e-05 +41 mux_tree_tapbuf_size16_2_sram[2]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 3.637469e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size16_2_sram[2]:25 0.152 +1 mux_tree_tapbuf_size16_2_sram[2]:10 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size16_2_sram[2]:12 mux_tree_tapbuf_size16_2_sram[2]:11 0.001285714 +3 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[2]:12 0.0045 +4 mux_tree_tapbuf_size16_2_sram[2]:13 mux_tree_tapbuf_size16_2_sram[2]:9 0.008459821 +5 mux_tree_tapbuf_size16_2_sram[2]:23 mux_tree_tapbuf_size16_2_sram[2]:22 0.0045 +6 mux_tree_tapbuf_size16_2_sram[2]:23 mux_tree_tapbuf_size16_2_sram[2]:6 0.002323661 +7 mux_tree_tapbuf_size16_2_sram[2]:22 mux_tree_tapbuf_size16_2_sram[2]:21 0.002388393 +8 mux_tree_tapbuf_size16_2_sram[2]:19 mux_bottom_track_5\/mux_l3_in_3_:S 0.152 +9 mux_tree_tapbuf_size16_2_sram[2]:20 mux_tree_tapbuf_size16_2_sram[2]:19 0.0001847826 +10 mux_tree_tapbuf_size16_2_sram[2]:21 mux_tree_tapbuf_size16_2_sram[2]:20 0.0045 +11 mux_tree_tapbuf_size16_2_sram[2]:21 mux_tree_tapbuf_size16_2_sram[2]:18 0.007285715 +12 mux_tree_tapbuf_size16_2_sram[2]:8 mux_tree_tapbuf_size16_2_sram[2]:7 0.0004263393 +13 mux_tree_tapbuf_size16_2_sram[2]:9 mux_tree_tapbuf_size16_2_sram[2]:8 0.0045 +14 mux_tree_tapbuf_size16_2_sram[2]:7 mux_bottom_track_5\/mux_l3_in_2_:S 0.152 +15 mux_tree_tapbuf_size16_2_sram[2]:16 mux_tree_tapbuf_size16_2_sram[2]:15 0.0004263393 +16 mux_tree_tapbuf_size16_2_sram[2]:17 mux_tree_tapbuf_size16_2_sram[2]:16 0.0045 +17 mux_tree_tapbuf_size16_2_sram[2]:15 mux_bottom_track_5\/mux_l3_in_1_:S 0.152 +18 mux_tree_tapbuf_size16_2_sram[2]:25 mux_tree_tapbuf_size16_2_sram[2]:24 0.002569196 +19 mux_tree_tapbuf_size16_2_sram[2]:6 mux_bottom_track_5\/mux_l3_in_0_:S 0.152 +20 mux_tree_tapbuf_size16_2_sram[2]:24 mux_tree_tapbuf_size16_2_sram[2]:23 0.0003035715 +21 mux_tree_tapbuf_size16_2_sram[2]:11 mux_tree_tapbuf_size16_2_sram[2]:10 0.0002111487 +22 mux_tree_tapbuf_size16_2_sram[2]:18 mux_tree_tapbuf_size16_2_sram[2]:17 0.00019375 +23 mux_tree_tapbuf_size16_2_sram[2]:18 mux_tree_tapbuf_size16_2_sram[2]:14 0.0004107143 +24 mux_tree_tapbuf_size16_2_sram[2]:14 mux_tree_tapbuf_size16_2_sram[2]:13 0.002732143 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[1] 0.002518734 //LENGTH 18.155 LUMPCC 0 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 90.005 71.565 +*I mux_right_track_32\/mux_l2_in_1_:S I *L 0.00357 *C 89.600 68.680 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 89.415 64.260 +*I mux_right_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 95.580 72.420 +*N mux_tree_tapbuf_size7_1_sram[1]:4 *C 95.543 72.420 +*N mux_tree_tapbuf_size7_1_sram[1]:5 *C 95.220 72.420 +*N mux_tree_tapbuf_size7_1_sram[1]:6 *C 95.220 72.760 +*N mux_tree_tapbuf_size7_1_sram[1]:7 *C 91.080 72.760 +*N mux_tree_tapbuf_size7_1_sram[1]:8 *C 91.080 72.080 +*N mux_tree_tapbuf_size7_1_sram[1]:9 *C 89.415 64.260 +*N mux_tree_tapbuf_size7_1_sram[1]:10 *C 89.240 64.260 +*N mux_tree_tapbuf_size7_1_sram[1]:11 *C 89.240 64.305 +*N mux_tree_tapbuf_size7_1_sram[1]:12 *C 89.585 68.680 +*N mux_tree_tapbuf_size7_1_sram[1]:13 *C 89.263 68.680 +*N mux_tree_tapbuf_size7_1_sram[1]:14 *C 89.240 68.680 +*N mux_tree_tapbuf_size7_1_sram[1]:15 *C 89.240 72.035 +*N mux_tree_tapbuf_size7_1_sram[1]:16 *C 89.285 72.080 +*N mux_tree_tapbuf_size7_1_sram[1]:17 *C 90.005 72.080 +*N mux_tree_tapbuf_size7_1_sram[1]:18 *C 90.005 72.035 +*N mux_tree_tapbuf_size7_1_sram[1]:19 *C 90.005 71.610 +*N mux_tree_tapbuf_size7_1_sram[1]:20 *C 90.005 71.565 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_32\/mux_l2_in_1_:S 1e-06 +2 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_32\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_1_sram[1]:4 3.52828e-05 +5 mux_tree_tapbuf_size7_1_sram[1]:5 6.343214e-05 +6 mux_tree_tapbuf_size7_1_sram[1]:6 0.0003280859 +7 mux_tree_tapbuf_size7_1_sram[1]:7 0.0003453984 +8 mux_tree_tapbuf_size7_1_sram[1]:8 0.0001129732 +9 mux_tree_tapbuf_size7_1_sram[1]:9 5.009912e-05 +10 mux_tree_tapbuf_size7_1_sram[1]:10 5.414203e-05 +11 mux_tree_tapbuf_size7_1_sram[1]:11 0.0002916883 +12 mux_tree_tapbuf_size7_1_sram[1]:12 4.932416e-05 +13 mux_tree_tapbuf_size7_1_sram[1]:13 4.932416e-05 +14 mux_tree_tapbuf_size7_1_sram[1]:14 0.0005427289 +15 mux_tree_tapbuf_size7_1_sram[1]:15 0.0002161307 +16 mux_tree_tapbuf_size7_1_sram[1]:16 6.730488e-05 +17 mux_tree_tapbuf_size7_1_sram[1]:17 0.0001661763 +18 mux_tree_tapbuf_size7_1_sram[1]:18 5.355465e-05 +19 mux_tree_tapbuf_size7_1_sram[1]:19 5.355465e-05 +20 mux_tree_tapbuf_size7_1_sram[1]:20 3.553429e-05 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_1_sram[1]:20 0.152 +1 mux_tree_tapbuf_size7_1_sram[1]:12 mux_right_track_32\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:12 0.0001752718 +3 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:11 0.00390625 +5 mux_tree_tapbuf_size7_1_sram[1]:10 mux_tree_tapbuf_size7_1_sram[1]:9 9.51087e-05 +6 mux_tree_tapbuf_size7_1_sram[1]:11 mux_tree_tapbuf_size7_1_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size7_1_sram[1]:9 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size7_1_sram[1]:4 mux_right_track_32\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size7_1_sram[1]:16 mux_tree_tapbuf_size7_1_sram[1]:15 0.0045 +10 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:14 0.002995535 +11 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:16 0.0006428572 +12 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:8 0.0009598215 +13 mux_tree_tapbuf_size7_1_sram[1]:18 mux_tree_tapbuf_size7_1_sram[1]:17 0.0045 +14 mux_tree_tapbuf_size7_1_sram[1]:20 mux_tree_tapbuf_size7_1_sram[1]:19 0.0045 +15 mux_tree_tapbuf_size7_1_sram[1]:19 mux_tree_tapbuf_size7_1_sram[1]:18 0.0003794643 +16 mux_tree_tapbuf_size7_1_sram[1]:8 mux_tree_tapbuf_size7_1_sram[1]:7 0.0006071429 +17 mux_tree_tapbuf_size7_1_sram[1]:7 mux_tree_tapbuf_size7_1_sram[1]:6 0.003696429 +18 mux_tree_tapbuf_size7_1_sram[1]:6 mux_tree_tapbuf_size7_1_sram[1]:5 0.0003035715 +19 mux_tree_tapbuf_size7_1_sram[1]:5 mux_tree_tapbuf_size7_1_sram[1]:4 0.0002879465 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0] 0.002140676 //LENGTH 16.040 LUMPCC 0.0005802901 DR + +*CONN +*I mux_top_track_0\/mux_l4_in_0_:X O *L 0 *C 83.545 113.560 +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 85.250 120.880 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 85.250 120.880 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 85.100 121.380 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 81.005 121.380 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 80.960 121.335 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 80.960 113.605 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 81.005 113.560 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:8 *C 83.508 113.560 + +*CAP +0 mux_top_track_0\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 7.350891e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0002589508 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002222357 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002962079 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0002962079 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0002056372 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.0002056372 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 chany_top_in[0] 0.0002074782 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 chany_top_in[0]:9 0.0002074782 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 chany_top_out[0]:7 7.547557e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 chany_top_out[0]:5 7.191346e-06 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 chany_top_out[0]:6 7.191346e-06 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 chany_top_out[0]:8 7.547557e-05 + +*RES +0 mux_top_track_0\/mux_l4_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.00365625 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.006901786 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.002234375 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0004464286 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0] 0.002219946 //LENGTH 15.490 LUMPCC 0.0009029933 DR + +*CONN +*I mux_top_track_2\/mux_l4_in_0_:X O *L 0 *C 55.485 112.880 +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 62.300 120.890 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 62.300 120.890 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 59.845 120.700 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 59.800 120.655 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 59.800 112.925 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 59.755 112.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 55.523 112.880 + +*CAP +0 mux_top_track_2\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0001790281 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001407448 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002247458 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002247458 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.000272844 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.000272844 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 chany_top_in[5] 0.0002099848 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 chany_top_in[5]:33 0.0002099848 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 top_left_grid_pin_38_[0]:10 8.249078e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 top_left_grid_pin_38_[0]:11 8.249078e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 top_left_grid_pin_40_[0]:11 2.947903e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 top_left_grid_pin_40_[0]:15 0.000129542 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 top_left_grid_pin_40_[0]:14 0.000129542 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 top_left_grid_pin_40_[0]:15 2.947903e-05 + +*RES +0 mux_top_track_2\/mux_l4_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.002191964 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.006901787 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.003779018 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0007328486 //LENGTH 5.740 LUMPCC 0.000120415 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_3_:X O *L 0 *C 97.695 97.240 +*I mux_right_track_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 99.535 98.940 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 99.498 98.940 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 97.105 98.940 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 97.060 98.895 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 97.060 97.285 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 97.105 97.240 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 97.657 97.240 + +*CAP +0 mux_right_track_0\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.000182238 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.000182238 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.006242e-05 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.006242e-05 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.291641e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.291641e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size12_2_sram[1]:14 5.174131e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size12_2_sram[1]:10 8.466175e-06 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size12_2_sram[1]:11 5.174131e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size12_2_sram[1]:9 8.466175e-06 + +*RES +0 mux_right_track_0\/mux_l2_in_3_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_0\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002136161 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0014375 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001483163 //LENGTH 11.395 LUMPCC 0.0002013008 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 81.245 25.840 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 87.860 28.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 87.860 28.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.860 29.240 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 83.305 29.240 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 83.260 29.195 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 83.260 25.885 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 83.215 25.840 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 81.282 25.840 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.640572e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002910855 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002633081 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001904664 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001904664 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000144065 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.000144065 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size12_4_sram[1]:14 6.088039e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size12_4_sram[1]:12 8.197415e-06 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size12_4_sram[1]:15 3.157258e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size12_4_sram[1]:15 8.197415e-06 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size12_4_sram[1]:19 3.157258e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_4_sram[1]:13 6.088039e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004066965 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002955357 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.001725447 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002275775 //LENGTH 15.660 LUMPCC 0.0009909265 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_3_:X O *L 0 *C 49.965 25.840 +*I mux_bottom_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 61.355 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 61.318 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 60.720 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 60.720 23.120 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 58.465 23.120 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 58.420 23.165 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 58.420 25.795 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 58.375 25.840 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 50.003 25.840 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.948026e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.481529e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002012477 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001759126 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001258443 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001258443 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000254852 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.000254852 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_left_in[4]:31 0.0001045338 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chanx_left_in[4]:30 0.0001045338 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size12_5_sram[0]:25 9.333182e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size12_5_sram[0]:24 9.333182e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002262549 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002262549 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.171561e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.62718e-06 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.171561e-05 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.62718e-06 + +*RES +0 mux_bottom_track_3\/mux_l1_in_3_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3\/mux_l2_in_1_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002013393 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002348214 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.007475447 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005334821 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0009464041 //LENGTH 7.330 LUMPCC 8.25953e-05 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_3_:X O *L 0 *C 18.225 83.640 +*I mux_left_track_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 18.575 86.360 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 18.538 86.360 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 16.605 86.360 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 16.560 86.315 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 16.560 83.685 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 16.605 83.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 18.188 83.640 + +*CAP +0 mux_left_track_1\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001474205 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001474205 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001707598 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001707598 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001127241 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001127241 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size12_6_sram[1]:6 4.129765e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size12_6_sram[1]:7 4.129765e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_3_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_1\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001725446 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002348215 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.001412946 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0003397265 //LENGTH 2.305 LUMPCC 0.0001724585 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_2_:X O *L 0 *C 24.205 99.620 +*I mux_left_track_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 26.220 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 26.183 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 24.242 99.620 + +*CAP +0 mux_left_track_3\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.263398e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.263398e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size12_7_sram[1]:9 8.622924e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size12_7_sram[1]:10 8.622924e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_2_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001732143 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_3\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001240685 //LENGTH 10.215 LUMPCC 0.0002923956 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 33.295 125.800 +*I mux_top_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 35.060 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 35.023 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 33.625 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 33.580 118.025 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 33.580 125.755 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.580 125.800 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 33.295 125.800 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001057618 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001057618 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003237537 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003237537 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.675831e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.050039e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_40_[0]:18 5.538618e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_40_[0]:19 5.538618e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_0_sram[1]:35 2.575747e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_0_sram[1]:45 5.895746e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size16_0_sram[1]:32 6.096709e-06 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size16_0_sram[1]:34 2.575747e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size16_0_sram[1]:41 5.895746e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size16_0_sram[1]:33 6.096709e-06 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001247768 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001237411 //LENGTH 10.605 LUMPCC 0.0001350121 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_2_:X O *L 0 *C 120.695 85.340 +*I mux_right_track_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 118.780 77.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 118.818 77.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 119.140 77.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 119.140 78.200 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 120.015 78.200 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 120.060 78.245 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 120.060 85.295 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 120.105 85.340 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 120.657 85.340 + +*CAP +0 mux_right_track_4\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.980506e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.686688e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000107959 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.089721e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003675562 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003675562 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 3.487936e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 3.487936e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size16_1_sram[1]:46 3.325705e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size16_1_sram[1]:49 3.424903e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size16_1_sram[1]:51 3.325705e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size16_1_sram[1]:50 3.424903e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00078125 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.006294643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004933036 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002879464 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000727613 //LENGTH 5.630 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_3_:X O *L 0 *C 33.405 30.600 +*I mux_bottom_track_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 34.215 26.520 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 34.178 26.520 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 33.625 26.520 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 33.580 26.565 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 33.580 30.555 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 33.580 30.600 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 33.405 30.600 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.843275e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.843275e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002384239 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002384239 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.512754e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.677221e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_3_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_5\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004933036 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0035625 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001615074 //LENGTH 10.115 LUMPCC 0.0003786964 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 46.635 89.080 +*I mux_left_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 37.165 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 37.165 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.260 89.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 46.598 89.080 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.552393e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006031165 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0005757377 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_3_sram[1]:43 3.281897e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_3_sram[1]:44 8.763181e-06 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_3_sram[1]:46 4.104219e-06 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size16_3_sram[1]:48 0.0001436618 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size16_3_sram[1]:42 3.281897e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size16_3_sram[1]:43 8.763181e-06 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size16_3_sram[1]:45 4.104219e-06 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size16_3_sram[1]:47 0.0001436618 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.008337054 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001587312 //LENGTH 10.545 LUMPCC 0.0002711096 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_2_:X O *L 0 *C 105.165 40.120 +*I mux_top_track_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 113.065 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 113.065 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 113.160 41.480 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 105.385 41.480 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 105.340 41.435 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 105.340 40.165 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 105.340 40.120 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 105.165 40.120 + +*CAP +0 mux_top_track_8\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.264643e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0004983377 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004722492 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.94175e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.94175e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.742207e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.471191e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:10 0.0001353626 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:11 1.921724e-07 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:14 1.921724e-07 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:9 0.0001353626 + +*RES +0 mux_top_track_8\/mux_l2_in_2_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_8\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.006941965 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001133929 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.51087e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001351285 //LENGTH 10.475 LUMPCC 0.0003496895 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_1_:X O *L 0 *C 62.845 61.880 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 62.390 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 62.428 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 63.435 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 63.480 69.655 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 63.480 61.925 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 63.435 61.880 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.883 61.880 + +*CAP +0 mux_top_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.383317e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.383317e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003799565 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003799565 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.600791e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.600791e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_2_sram[1]:21 1.292008e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_2_sram[1]:22 1.292008e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_2_sram[1]:20 5.928046e-05 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_2_sram[1]:19 5.928046e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.174199e-05 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.174199e-05 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.090224e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.090224e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008995536 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001171142 //LENGTH 10.050 LUMPCC 0.0002316107 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_1_:X O *L 0 *C 116.665 55.760 +*I mux_right_track_8\/mux_l4_in_0_:A0 I *L 0.00199 *C 117.475 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 117.475 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 117.300 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 117.300 64.215 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 117.300 55.805 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 117.255 55.760 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 116.703 55.760 + +*CAP +0 mux_right_track_8\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.371913e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.808729e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0003593297 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0003593297 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.353293e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.353293e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chanx_left_in[13]:15 4.741499e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chanx_left_in[13]:14 4.741499e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:172 3.992352e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:176 2.846684e-05 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:176 3.992352e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:177 2.846684e-05 + +*RES +0 mux_right_track_8\/mux_l3_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_8\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.007508929 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006974612 //LENGTH 5.425 LUMPCC 0.0001962029 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_2_:X O *L 0 *C 91.825 82.280 +*I mux_right_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 93.940 79.900 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 93.903 79.900 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.505 79.900 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.460 79.945 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.460 82.235 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.415 82.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 91.863 82.280 + +*CAP +0 mux_right_track_24\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.87953e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.87953e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001230494 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001230494 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.778453e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.778453e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[12]:24 4.496751e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[12]:26 8.322771e-06 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[12]:25 4.496751e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[12]:27 8.322771e-06 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_bottom_in[9]:11 3.497977e-06 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[9]:12 3.497977e-06 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[9]:13 1.827568e-05 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[9]:15 2.30375e-05 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[9]:10 1.827568e-05 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[9]:14 2.30375e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_2_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_24\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001247768 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933035 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007156641 //LENGTH 5.760 LUMPCC 0.000115695 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_0_:X O *L 0 *C 67.335 33.660 +*I mux_bottom_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 65.225 30.940 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 65.263 30.940 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 66.195 30.940 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 66.240 30.985 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 66.240 33.615 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 66.285 33.660 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 67.297 33.660 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.127771e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.127771e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001423998 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001423998 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.530708e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.530708e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.738351e-06 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.738351e-06 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.110917e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.110917e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325893 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.005465284 //LENGTH 23.150 LUMPCC 0.003829666 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 65.495 44.880 +*I mux_bottom_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 43.605 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 43.643 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 45.035 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 45.080 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 45.080 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 45.088 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 63.013 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 63.020 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 63.065 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 65.458 44.880 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001119454 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001119454 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.238153e-05 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.676845e-05 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004595653 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004595653 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 3.810346e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001716715 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001716715 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[4]:18 0.0009799374 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[4]:17 0.0009799374 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_8_sram[1]:32 0.0009310106 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_8_sram[1]:29 1.94257e-06 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_8_sram[1]:30 1.94257e-06 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_8_sram[1]:31 0.0009310106 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_8_sram[1]:26 1.94257e-06 +18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_8_sram[1]:29 1.94257e-06 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00213616 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00280825 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001634615 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001243304 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004679601 //LENGTH 3.025 LUMPCC 8.462992e-05 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_1_:X O *L 0 *C 65.035 53.720 +*I mux_left_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 65.610 55.080 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 65.573 55.080 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 64.905 55.080 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 64.860 55.035 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 64.860 53.765 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 64.860 53.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 65.035 53.720 + +*CAP +0 mux_left_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.86194e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.86194e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.67561e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.67561e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.569695e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.488218e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[4]:24 4.231496e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[4]:25 4.231496e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005959822 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001133929 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001109241 //LENGTH 8.155 LUMPCC 0.0001366642 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_2_:X O *L 0 *C 20.415 66.715 +*I mux_left_track_25\/mux_l3_in_1_:A1 I *L 0.00198 *C 20.240 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 20.240 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 20.240 61.880 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 19.365 61.880 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 19.320 61.925 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 19.320 66.595 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 19.365 66.640 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 20.415 66.715 + +*CAP +0 mux_left_track_25\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.807593e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001138983 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.539765e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002297827 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002297827 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.904813e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001545919 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.763306e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 1.069904e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.763306e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 1.069904e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_2_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_25\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.00078125 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.004169643 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0009375 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003532961 //LENGTH 24.100 LUMPCC 0.0009429652 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_1_:X O *L 0 *C 106.895 82.280 +*I mux_right_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 94.475 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 94.475 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 94.760 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 94.760 71.785 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 94.760 78.142 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 94.767 78.200 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 106.713 78.200 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 106.720 78.258 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 106.720 82.235 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 106.720 82.280 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 106.895 82.280 + +*CAP +0 mux_right_track_32\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.607487e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.658644e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004133288 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004133288 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005146192 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005146192 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002532827 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002532827 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.712748e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.574517e-05 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[5]:25 0.0002448404 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[5]:24 0.0002448404 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[14]:21 0.0002266422 +15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[14]:20 0.0002266422 + +*RES +0 mux_right_track_32\/mux_l1_in_1_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005676339 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001871383 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.003551339 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001546881 //LENGTH 10.775 LUMPCC 0.0001381765 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_2_:X O *L 0 *C 25.015 74.460 +*I mux_left_track_33\/mux_l2_in_1_:A1 I *L 0.00198 *C 17.020 72.420 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 17.058 72.420 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 24.795 72.420 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 24.840 72.465 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 24.840 74.415 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 24.840 74.460 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 25.015 74.460 + +*CAP +0 mux_left_track_33\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0005430834 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0005430834 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000102105 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000102105 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.607713e-05 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.025034e-05 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:13 1.044071e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:14 1.044071e-05 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_3_sram[0]:8 1.242533e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_3_sram[0]:11 4.622223e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_3_sram[0]:10 4.622223e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_3_sram[0]:11 1.242533e-05 + +*RES +0 mux_left_track_33\/mux_l1_in_2_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.006908483 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_33\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET ropt_net_180 0.0009416831 //LENGTH 7.670 LUMPCC 0.000171812 DR + +*CONN +*I FTB_15__14:X O *L 0 *C 8.740 45.560 +*I ropt_mt_inst_819:A I *L 0.001766 *C 7.820 50.320 +*N ropt_net_180:2 *C 7.798 50.293 +*N ropt_net_180:3 *C 7.785 49.980 +*N ropt_net_180:4 *C 7.405 49.980 +*N ropt_net_180:5 *C 7.360 49.935 +*N ropt_net_180:6 *C 7.360 45.605 +*N ropt_net_180:7 *C 7.405 45.560 +*N ropt_net_180:8 *C 8.703 45.560 + +*CAP +0 FTB_15__14:X 1e-06 +1 ropt_mt_inst_819:A 1e-06 +2 ropt_net_180:2 3.441898e-05 +3 ropt_net_180:3 5.687998e-05 +4 ropt_net_180:4 2.2461e-05 +5 ropt_net_180:5 0.0002165425 +6 ropt_net_180:6 0.0002165425 +7 ropt_net_180:7 0.0001105131 +8 ropt_net_180:8 0.0001105131 +9 ropt_net_180:4 ropt_net_214:6 2.50298e-05 +10 ropt_net_180:5 ropt_net_214:5 6.087619e-05 +11 ropt_net_180:6 ropt_net_214:4 6.087619e-05 +12 ropt_net_180:3 ropt_net_214:7 2.50298e-05 + +*RES +0 FTB_15__14:X ropt_net_180:8 0.152 +1 ropt_net_180:2 ropt_mt_inst_819:A 0.152 +2 ropt_net_180:4 ropt_net_180:3 0.0003392857 +3 ropt_net_180:5 ropt_net_180:4 0.0045 +4 ropt_net_180:7 ropt_net_180:6 0.0045 +5 ropt_net_180:6 ropt_net_180:5 0.003866072 +6 ropt_net_180:8 ropt_net_180:7 0.001158482 +7 ropt_net_180:3 ropt_net_180:2 0.0002111487 + +*END + +*D_NET ropt_net_185 0.0009387104 //LENGTH 7.145 LUMPCC 0.0002853981 DR + +*CONN +*I FTB_30__29:X O *L 0 *C 54.280 118.660 +*I ropt_mt_inst_824:A I *L 0.001766 *C 50.140 121.040 +*N ropt_net_185:2 *C 50.178 121.040 +*N ropt_net_185:3 *C 54.235 121.040 +*N ropt_net_185:4 *C 54.280 120.995 +*N ropt_net_185:5 *C 54.280 118.705 +*N ropt_net_185:6 *C 54.280 118.660 + +*CAP +0 FTB_30__29:X 1e-06 +1 ropt_mt_inst_824:A 1e-06 +2 ropt_net_185:2 0.0001952933 +3 ropt_net_185:3 0.0001952933 +4 ropt_net_185:4 0.0001117015 +5 ropt_net_185:5 0.0001117015 +6 ropt_net_185:6 3.732265e-05 +7 ropt_net_185:4 chany_top_in[14] 6.808632e-05 +8 ropt_net_185:5 chany_top_in[14]:30 6.808632e-05 +9 ropt_net_185:2 top_left_grid_pin_38_[0]:11 7.461273e-05 +10 ropt_net_185:3 top_left_grid_pin_38_[0]:10 7.461273e-05 + +*RES +0 FTB_30__29:X ropt_net_185:6 0.152 +1 ropt_net_185:2 ropt_mt_inst_824:A 0.152 +2 ropt_net_185:3 ropt_net_185:2 0.003622768 +3 ropt_net_185:4 ropt_net_185:3 0.0045 +4 ropt_net_185:6 ropt_net_185:5 0.0045 +5 ropt_net_185:5 ropt_net_185:4 0.002044643 + +*END + +*D_NET chany_top_out[13] 0.001189726 //LENGTH 8.775 LUMPCC 0.0003659983 DR + +*CONN +*I ropt_mt_inst_849:X O *L 0 *C 63.480 123.080 +*P chany_top_out[13] O *L 0.7423 *C 64.400 129.270 +*N chany_top_out[13]:2 *C 64.400 127.840 +*N chany_top_out[13]:3 *C 64.860 127.840 +*N chany_top_out[13]:4 *C 64.860 123.125 +*N chany_top_out[13]:5 *C 64.815 123.080 +*N chany_top_out[13]:6 *C 63.518 123.080 + +*CAP +0 ropt_mt_inst_849:X 1e-06 +1 chany_top_out[13] 8.841851e-05 +2 chany_top_out[13]:2 0.0001053002 +3 chany_top_out[13]:3 0.0002455976 +4 chany_top_out[13]:4 0.0002287159 +5 chany_top_out[13]:5 7.734773e-05 +6 chany_top_out[13]:6 7.734773e-05 +7 chany_top_out[13]:4 ropt_net_186:3 2.412699e-05 +8 chany_top_out[13]:4 ropt_net_186:7 8.748242e-05 +9 chany_top_out[13]:2 ropt_net_186:9 9.791961e-06 +10 chany_top_out[13]:3 ropt_net_186:4 2.412699e-05 +11 chany_top_out[13]:3 ropt_net_186:8 8.748242e-05 +12 chany_top_out[13]:3 ropt_net_186:10 9.791961e-06 +13 chany_top_out[13]:6 ropt_net_182:5 6.159778e-05 +14 chany_top_out[13]:5 ropt_net_182:4 6.159778e-05 + +*RES +0 ropt_mt_inst_849:X chany_top_out[13]:6 0.152 +1 chany_top_out[13]:6 chany_top_out[13]:5 0.001158482 +2 chany_top_out[13]:5 chany_top_out[13]:4 0.0045 +3 chany_top_out[13]:4 chany_top_out[13]:3 0.004209821 +4 chany_top_out[13]:2 chany_top_out[13] 0.001276786 +5 chany_top_out[13]:3 chany_top_out[13]:2 0.0004107143 + +*END + +*D_NET ropt_net_163 0.0009177829 //LENGTH 7.540 LUMPCC 0 DR + +*CONN +*I BUFT_RR_86:X O *L 0 *C 12.420 51.000 +*I ropt_mt_inst_801:A I *L 0.001766 *C 7.820 53.040 +*N ropt_net_163:2 *C 7.820 53.040 +*N ropt_net_163:3 *C 8.235 53.040 +*N ropt_net_163:4 *C 8.280 52.995 +*N ropt_net_163:5 *C 8.280 51.045 +*N ropt_net_163:6 *C 8.325 51.000 +*N ropt_net_163:7 *C 12.383 51.000 + +*CAP +0 BUFT_RR_86:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_163:2 8.223228e-05 +3 ropt_net_163:3 4.658948e-05 +4 ropt_net_163:4 0.0001202056 +5 ropt_net_163:5 0.0001202056 +6 ropt_net_163:6 0.000273275 +7 ropt_net_163:7 0.000273275 + +*RES +0 BUFT_RR_86:X ropt_net_163:7 0.152 +1 ropt_net_163:7 ropt_net_163:6 0.003622768 +2 ropt_net_163:6 ropt_net_163:5 0.0045 +3 ropt_net_163:5 ropt_net_163:4 0.001741072 +4 ropt_net_163:3 ropt_net_163:2 0.0003705357 +5 ropt_net_163:4 ropt_net_163:3 0.0045 +6 ropt_net_163:2 ropt_mt_inst_801:A 0.152 + +*END + +*D_NET ropt_net_219 0.001039404 //LENGTH 7.275 LUMPCC 0.0002224745 DR + +*CONN +*I ropt_mt_inst_824:X O *L 0 *C 54.015 121.720 +*I ropt_mt_inst_862:A I *L 0.001767 *C 50.140 123.760 +*N ropt_net_219:2 *C 50.178 123.760 +*N ropt_net_219:3 *C 50.555 123.760 +*N ropt_net_219:4 *C 50.600 123.715 +*N ropt_net_219:5 *C 50.600 123.125 +*N ropt_net_219:6 *C 50.645 123.080 +*N ropt_net_219:7 *C 53.775 123.080 +*N ropt_net_219:8 *C 53.820 123.035 +*N ropt_net_219:9 *C 53.820 121.765 +*N ropt_net_219:10 *C 53.820 121.720 +*N ropt_net_219:11 *C 54.015 121.720 + +*CAP +0 ropt_mt_inst_824:X 1e-06 +1 ropt_mt_inst_862:A 1e-06 +2 ropt_net_219:2 2.556099e-05 +3 ropt_net_219:3 2.556099e-05 +4 ropt_net_219:4 6.019938e-05 +5 ropt_net_219:5 6.019938e-05 +6 ropt_net_219:6 0.0001937315 +7 ropt_net_219:7 0.0001937315 +8 ropt_net_219:8 7.311889e-05 +9 ropt_net_219:9 7.311889e-05 +10 ropt_net_219:10 5.721653e-05 +11 ropt_net_219:11 5.249151e-05 +12 ropt_net_219:8 top_left_grid_pin_34_[0]:15 4.164482e-05 +13 ropt_net_219:9 top_left_grid_pin_34_[0]:14 4.164482e-05 +14 ropt_net_219:2 ropt_net_191:5 2.753067e-05 +15 ropt_net_219:3 ropt_net_191:4 2.753067e-05 +16 ropt_net_219:6 ropt_net_191:3 4.134565e-05 +17 ropt_net_219:6 ropt_net_191:5 7.160925e-07 +18 ropt_net_219:7 ropt_net_191:2 4.134565e-05 +19 ropt_net_219:7 ropt_net_191:4 7.160925e-07 + +*RES +0 ropt_mt_inst_824:X ropt_net_219:11 0.152 +1 ropt_net_219:2 ropt_mt_inst_862:A 0.152 +2 ropt_net_219:3 ropt_net_219:2 0.0003370536 +3 ropt_net_219:4 ropt_net_219:3 0.0045 +4 ropt_net_219:6 ropt_net_219:5 0.0045 +5 ropt_net_219:5 ropt_net_219:4 0.0005267857 +6 ropt_net_219:7 ropt_net_219:6 0.002794643 +7 ropt_net_219:8 ropt_net_219:7 0.0045 +8 ropt_net_219:10 ropt_net_219:9 0.0045 +9 ropt_net_219:9 ropt_net_219:8 0.001133929 +10 ropt_net_219:11 ropt_net_219:10 0.0001059783 + +*END + +*D_NET ropt_net_181 0.002334246 //LENGTH 19.630 LUMPCC 0.0003098735 DR + +*CONN +*I BUFT_P_124:X O *L 0 *C 133.860 63.240 +*I ropt_mt_inst_820:A I *L 0.001766 *C 134.780 55.760 +*N ropt_net_181:2 *C 134.803 55.788 +*N ropt_net_181:3 *C 134.815 56.100 +*N ropt_net_181:4 *C 139.335 56.100 +*N ropt_net_181:5 *C 139.380 56.145 +*N ropt_net_181:6 *C 139.380 63.535 +*N ropt_net_181:7 *C 139.335 63.580 +*N ropt_net_181:8 *C 135.700 63.580 +*N ropt_net_181:9 *C 135.700 63.240 +*N ropt_net_181:10 *C 133.898 63.240 + +*CAP +0 BUFT_P_124:X 1e-06 +1 ropt_mt_inst_820:A 1e-06 +2 ropt_net_181:2 3.367408e-05 +3 ropt_net_181:3 0.0002127816 +4 ropt_net_181:4 0.0001791075 +5 ropt_net_181:5 0.0003787784 +6 ropt_net_181:6 0.0003787784 +7 ropt_net_181:7 0.0002424409 +8 ropt_net_181:8 0.0002664708 +9 ropt_net_181:9 0.0001771855 +10 ropt_net_181:10 0.0001531555 +11 ropt_net_181:4 ropt_net_225:7 0.0001549367 +12 ropt_net_181:3 ropt_net_225:6 0.0001549367 + +*RES +0 BUFT_P_124:X ropt_net_181:10 0.152 +1 ropt_net_181:10 ropt_net_181:9 0.001609375 +2 ropt_net_181:7 ropt_net_181:6 0.0045 +3 ropt_net_181:6 ropt_net_181:5 0.006598215 +4 ropt_net_181:4 ropt_net_181:3 0.004035715 +5 ropt_net_181:5 ropt_net_181:4 0.0045 +6 ropt_net_181:2 ropt_mt_inst_820:A 0.152 +7 ropt_net_181:9 ropt_net_181:8 0.0003035715 +8 ropt_net_181:3 ropt_net_181:2 0.0002111487 +9 ropt_net_181:8 ropt_net_181:7 0.003245536 + +*END + +*D_NET chanx_right_out[6] 0.0008408669 //LENGTH 6.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_872:X O *L 0 *C 136.160 58.480 +*P chanx_right_out[6] O *L 0.7423 *C 140.450 58.480 +*N chanx_right_out[6]:2 *C 139.840 58.480 +*N chanx_right_out[6]:3 *C 139.840 59.160 +*N chanx_right_out[6]:4 *C 136.168 59.160 +*N chanx_right_out[6]:5 *C 136.160 59.103 +*N chanx_right_out[6]:6 *C 136.160 58.525 +*N chanx_right_out[6]:7 *C 136.160 58.480 + +*CAP +0 ropt_mt_inst_872:X 1e-06 +1 chanx_right_out[6] 4.242741e-05 +2 chanx_right_out[6]:2 8.503119e-05 +3 chanx_right_out[6]:3 0.0003094502 +4 chanx_right_out[6]:4 0.0002668464 +5 chanx_right_out[6]:5 5.318334e-05 +6 chanx_right_out[6]:6 5.318334e-05 +7 chanx_right_out[6]:7 2.974486e-05 + +*RES +0 ropt_mt_inst_872:X chanx_right_out[6]:7 0.152 +1 chanx_right_out[6]:7 chanx_right_out[6]:6 0.0045 +2 chanx_right_out[6]:6 chanx_right_out[6]:5 0.000515625 +3 chanx_right_out[6]:5 chanx_right_out[6]:4 0.00341 +4 chanx_right_out[6]:4 chanx_right_out[6]:3 0.0005753583 +5 chanx_right_out[6]:3 chanx_right_out[6]:2 0.0001065333 +6 chanx_right_out[6]:2 chanx_right_out[6] 9.556666e-05 + +*END + +*D_NET chanx_right_out[9] 0.000529479 //LENGTH 4.650 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_895:X O *L 0 *C 138.655 65.960 +*P chanx_right_out[9] O *L 0.7423 *C 140.450 63.920 +*N chanx_right_out[9]:2 *C 139.847 63.920 +*N chanx_right_out[9]:3 *C 139.840 63.978 +*N chanx_right_out[9]:4 *C 139.840 65.915 +*N chanx_right_out[9]:5 *C 139.795 65.960 +*N chanx_right_out[9]:6 *C 138.692 65.960 + +*CAP +0 ropt_mt_inst_895:X 1e-06 +1 chanx_right_out[9] 6.237277e-05 +2 chanx_right_out[9]:2 6.237277e-05 +3 chanx_right_out[9]:3 0.0001159889 +4 chanx_right_out[9]:4 0.0001159889 +5 chanx_right_out[9]:5 8.58778e-05 +6 chanx_right_out[9]:6 8.58778e-05 + +*RES +0 ropt_mt_inst_895:X chanx_right_out[9]:6 0.152 +1 chanx_right_out[9]:6 chanx_right_out[9]:5 0.000984375 +2 chanx_right_out[9]:5 chanx_right_out[9]:4 0.0045 +3 chanx_right_out[9]:4 chanx_right_out[9]:3 0.001729911 +4 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +5 chanx_right_out[9]:2 chanx_right_out[9] 9.439166e-05 + +*END + +*D_NET chany_top_in[6] 0.01892246 //LENGTH 136.880 LUMPCC 0.005398394 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 74.980 129.270 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.505 72.420 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 75.615 66.300 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.460 30.940 +*I FTB_4__3:A I *L 0.001767 *C 67.620 12.240 +*N chany_top_in[6]:5 *C 67.620 12.240 +*N chany_top_in[6]:6 *C 67.620 12.920 +*N chany_top_in[6]:7 *C 74.935 12.920 +*N chany_top_in[6]:8 *C 74.980 12.965 +*N chany_top_in[6]:9 *C 74.980 30.940 +*N chany_top_in[6]:10 *C 76.422 30.940 +*N chany_top_in[6]:11 *C 75.485 30.940 +*N chany_top_in[6]:12 *C 75.440 30.985 +*N chany_top_in[6]:13 *C 75.615 66.300 +*N chany_top_in[6]:14 *C 75.440 66.300 +*N chany_top_in[6]:15 *C 75.440 66.300 +*N chany_top_in[6]:16 *C 75.440 72.080 +*N chany_top_in[6]:17 *C 75.855 72.080 +*N chany_top_in[6]:18 *C 73.543 72.420 +*N chany_top_in[6]:19 *C 75.855 72.420 +*N chany_top_in[6]:20 *C 75.900 72.465 +*N chany_top_in[6]:21 *C 75.900 83.640 +*N chany_top_in[6]:22 *C 75.440 83.640 +*N chany_top_in[6]:23 *C 75.440 99.223 +*N chany_top_in[6]:24 *C 75.433 99.280 +*N chany_top_in[6]:25 *C 73.620 99.280 +*N chany_top_in[6]:26 *C 73.600 99.288 +*N chany_top_in[6]:27 *C 73.600 116.273 +*N chany_top_in[6]:28 *C 73.620 116.280 +*N chany_top_in[6]:29 *C 74.513 116.280 +*N chany_top_in[6]:30 *C 74.520 116.338 +*N chany_top_in[6]:31 *C 74.520 128.520 +*N chany_top_in[6]:32 *C 74.980 128.520 + +*CAP +0 chany_top_in[6] 6.009739e-05 +1 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +4 FTB_4__3:A 1e-06 +5 chany_top_in[6]:5 7.510248e-05 +6 chany_top_in[6]:6 0.0005372966 +7 chany_top_in[6]:7 0.000491193 +8 chany_top_in[6]:8 0.0009670609 +9 chany_top_in[6]:9 0.001002333 +10 chany_top_in[6]:10 8.36456e-05 +11 chany_top_in[6]:11 8.36456e-05 +12 chany_top_in[6]:12 0.002028411 +13 chany_top_in[6]:13 5.106976e-05 +14 chany_top_in[6]:14 5.570916e-05 +15 chany_top_in[6]:15 0.002300344 +16 chany_top_in[6]:16 0.0003060355 +17 chany_top_in[6]:17 5.120397e-05 +18 chany_top_in[6]:18 0.0001652513 +19 chany_top_in[6]:19 0.0001652513 +20 chany_top_in[6]:20 0.0005464217 +21 chany_top_in[6]:21 0.0005590998 +22 chany_top_in[6]:22 0.0006119476 +23 chany_top_in[6]:23 0.0005796797 +24 chany_top_in[6]:24 0.0002387281 +25 chany_top_in[6]:25 0.0002387281 +26 chany_top_in[6]:26 0.0005468034 +27 chany_top_in[6]:27 0.0005468034 +28 chany_top_in[6]:28 0.0001132718 +29 chany_top_in[6]:29 0.0001132718 +30 chany_top_in[6]:30 0.0004417516 +31 chany_top_in[6]:31 0.0004707822 +32 chany_top_in[6]:32 8.912801e-05 +33 chany_top_in[6]:8 chany_bottom_in[5]:32 5.175602e-06 +34 chany_top_in[6]:20 chany_bottom_in[5]:27 1.519516e-05 +35 chany_top_in[6]:20 chany_bottom_in[5]:28 8.614894e-05 +36 chany_top_in[6]:12 chany_bottom_in[5]:28 0.0001240791 +37 chany_top_in[6]:15 chany_bottom_in[5]:27 0.0001240791 +38 chany_top_in[6]:15 chany_bottom_in[5]:28 5.791374e-05 +39 chany_top_in[6]:9 chany_bottom_in[5]:31 5.175602e-06 +40 chany_top_in[6]:16 chany_bottom_in[5]:27 5.791374e-05 +41 chany_top_in[6]:17 chany_bottom_in[5]:28 1.519516e-05 +42 chany_top_in[6]:21 chany_bottom_in[5]:27 8.614894e-05 +43 chany_top_in[6]:8 prog_clk[0]:339 0.0001314606 +44 chany_top_in[6]:8 prog_clk[0]:341 9.899456e-06 +45 chany_top_in[6]:28 prog_clk[0]:558 3.454608e-06 +46 chany_top_in[6]:30 prog_clk[0]:557 8.177887e-05 +47 chany_top_in[6]:30 prog_clk[0]:561 3.139304e-05 +48 chany_top_in[6]:29 prog_clk[0]:559 3.454608e-06 +49 chany_top_in[6]:31 prog_clk[0]:556 8.177887e-05 +50 chany_top_in[6]:31 prog_clk[0]:560 3.139304e-05 +51 chany_top_in[6]:9 prog_clk[0]:340 0.0001314606 +52 chany_top_in[6]:9 prog_clk[0]:342 9.899456e-06 +53 chany_top_in[6] chany_top_in[3] 2.888599e-06 +54 chany_top_in[6]:26 chany_top_in[3]:9 0.0007622098 +55 chany_top_in[6]:27 chany_top_in[3]:10 0.0007622098 +56 chany_top_in[6]:30 chany_top_in[3]:14 0.0001313711 +57 chany_top_in[6]:14 chany_top_in[3]:6 5.426396e-06 +58 chany_top_in[6]:13 chany_top_in[3]:4 5.426396e-06 +59 chany_top_in[6]:31 chany_top_in[3] 0.0001313711 +60 chany_top_in[6]:32 chany_top_in[3]:14 2.888599e-06 +61 chany_top_in[6] chany_top_in[11] 1.56919e-06 +62 chany_top_in[6]:23 chany_top_in[11] 0.0003037096 +63 chany_top_in[6]:23 chany_top_in[11]:8 0.0001024713 +64 chany_top_in[6]:30 chany_top_in[11]:11 2.540131e-05 +65 chany_top_in[6]:19 chany_top_in[11]:4 1.427172e-05 +66 chany_top_in[6]:20 chany_top_in[11]:8 5.999233e-06 +67 chany_top_in[6]:20 chany_top_in[11]:5 0.000100887 +68 chany_top_in[6]:18 chany_top_in[11]:3 1.427172e-05 +69 chany_top_in[6]:15 chany_top_in[11]:5 1.450049e-05 +70 chany_top_in[6]:31 chany_top_in[11] 2.540131e-05 +71 chany_top_in[6]:32 chany_top_in[11]:11 1.56919e-06 +72 chany_top_in[6]:16 chany_top_in[11]:8 1.450049e-05 +73 chany_top_in[6]:17 chany_top_in[11]:5 5.999233e-06 +74 chany_top_in[6]:22 chany_top_in[11]:5 0.0001024713 +75 chany_top_in[6]:22 chany_top_in[11]:11 0.0003037096 +76 chany_top_in[6]:21 chany_top_in[11]:8 0.000100887 +77 chany_top_in[6]:26 mux_tree_tapbuf_size12_0_sram[1]:24 0.000371455 +78 chany_top_in[6]:27 mux_tree_tapbuf_size12_0_sram[1]:25 0.000371455 +79 chany_top_in[6]:30 mux_tree_tapbuf_size12_0_sram[1]:11 1.003558e-05 +80 chany_top_in[6]:30 mux_tree_tapbuf_size12_0_sram[1]:29 9.501288e-06 +81 chany_top_in[6]:31 mux_tree_tapbuf_size12_0_sram[1]:11 9.501288e-06 +82 chany_top_in[6]:31 mux_tree_tapbuf_size12_0_sram[1]:8 1.003558e-05 +83 chany_top_in[6]:23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001406306 +84 chany_top_in[6]:22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001406306 +85 chany_top_in[6]:7 ropt_net_202:2 1.883703e-05 +86 chany_top_in[6]:7 ropt_net_202:4 5.400496e-05 +87 chany_top_in[6]:6 ropt_net_202:5 5.400496e-05 +88 chany_top_in[6]:6 ropt_net_202:3 1.883703e-05 +89 chany_top_in[6]:30 ropt_net_213:6 7.752684e-05 +90 chany_top_in[6]:31 ropt_net_213:5 7.752684e-05 + +*RES +0 chany_top_in[6] chany_top_in[6]:32 0.0006696429 +1 chany_top_in[6]:5 FTB_4__3:A 0.152 +2 chany_top_in[6]:7 chany_top_in[6]:6 0.00653125 +3 chany_top_in[6]:8 chany_top_in[6]:7 0.0045 +4 chany_top_in[6]:23 chany_top_in[6]:22 0.01391295 +5 chany_top_in[6]:24 chany_top_in[6]:23 0.00341 +6 chany_top_in[6]:25 chany_top_in[6]:24 0.0002839583 +7 chany_top_in[6]:26 chany_top_in[6]:25 0.00341 +8 chany_top_in[6]:28 chany_top_in[6]:27 0.00341 +9 chany_top_in[6]:27 chany_top_in[6]:26 0.002660983 +10 chany_top_in[6]:30 chany_top_in[6]:29 0.00341 +11 chany_top_in[6]:29 chany_top_in[6]:28 0.000139825 +12 chany_top_in[6]:19 chany_top_in[6]:18 0.002064732 +13 chany_top_in[6]:20 chany_top_in[6]:19 0.0045 +14 chany_top_in[6]:20 chany_top_in[6]:17 0.000240625 +15 chany_top_in[6]:18 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[6]:11 chany_top_in[6]:10 0.0008370536 +17 chany_top_in[6]:12 chany_top_in[6]:11 0.0045 +18 chany_top_in[6]:12 chany_top_in[6]:9 0.0004107143 +19 chany_top_in[6]:10 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +20 chany_top_in[6]:14 chany_top_in[6]:13 9.51087e-05 +21 chany_top_in[6]:15 chany_top_in[6]:14 0.0045 +22 chany_top_in[6]:15 chany_top_in[6]:12 0.03153125 +23 chany_top_in[6]:13 mux_right_track_8\/mux_l1_in_0_:A0 0.152 +24 chany_top_in[6]:6 chany_top_in[6]:5 0.0006071429 +25 chany_top_in[6]:31 chany_top_in[6]:30 0.01087723 +26 chany_top_in[6]:32 chany_top_in[6]:31 0.0004107143 +27 chany_top_in[6]:9 chany_top_in[6]:8 0.01604911 +28 chany_top_in[6]:16 chany_top_in[6]:15 0.005160714 +29 chany_top_in[6]:17 chany_top_in[6]:16 0.0003705357 +30 chany_top_in[6]:22 chany_top_in[6]:21 0.0004107143 +31 chany_top_in[6]:21 chany_top_in[6]:20 0.009977679 + +*END + +*D_NET chany_bottom_in[8] 0.02300479 //LENGTH 158.710 LUMPCC 0.007883796 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 77.740 1.290 +*I mux_left_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.630 53.380 +*I FTB_31__30:A I *L 0.001767 *C 56.120 126.480 +*I mux_top_track_16\/mux_l1_in_2_:A0 I *L 0.001631 *C 56.410 58.820 +*I mux_right_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 80.785 49.640 +*N chany_bottom_in[8]:5 *C 80.748 49.640 +*N chany_bottom_in[8]:6 *C 79.625 49.640 +*N chany_bottom_in[8]:7 *C 79.580 49.640 +*N chany_bottom_in[8]:8 *C 56.448 58.820 +*N chany_bottom_in[8]:9 *C 58.835 58.820 +*N chany_bottom_in[8]:10 *C 58.480 58.820 +*N chany_bottom_in[8]:11 *C 56.158 126.480 +*N chany_bottom_in[8]:12 *C 58.375 126.480 +*N chany_bottom_in[8]:13 *C 58.420 126.435 +*N chany_bottom_in[8]:14 *C 58.420 121.098 +*N chany_bottom_in[8]:15 *C 58.422 121.040 +*N chany_bottom_in[8]:16 *C 58.865 121.040 +*N chany_bottom_in[8]:17 *C 58.880 121.032 +*N chany_bottom_in[8]:18 *C 58.880 108.655 +*N chany_bottom_in[8]:19 *C 58.880 58.828 +*N chany_bottom_in[8]:20 *C 58.880 58.820 +*N chany_bottom_in[8]:21 *C 58.880 58.820 +*N chany_bottom_in[8]:22 *C 59.340 58.820 +*N chany_bottom_in[8]:23 *C 59.340 53.425 +*N chany_bottom_in[8]:24 *C 59.340 53.380 +*N chany_bottom_in[8]:25 *C 59.630 53.380 +*N chany_bottom_in[8]:26 *C 59.800 53.380 +*N chany_bottom_in[8]:27 *C 59.800 53.335 +*N chany_bottom_in[8]:28 *C 59.800 49.698 +*N chany_bottom_in[8]:29 *C 59.808 49.640 +*N chany_bottom_in[8]:30 *C 79.112 49.640 +*N chany_bottom_in[8]:31 *C 79.120 49.640 +*N chany_bottom_in[8]:32 *C 79.120 39.145 +*N chany_bottom_in[8]:33 *C 79.075 39.100 +*N chany_bottom_in[8]:34 *C 77.785 39.100 +*N chany_bottom_in[8]:35 *C 77.740 39.055 + +*CAP +0 chany_bottom_in[8] 0.001794734 +1 mux_left_track_17\/mux_l2_in_1_:A0 1e-06 +2 FTB_31__30:A 1e-06 +3 mux_top_track_16\/mux_l1_in_2_:A0 1e-06 +4 mux_right_track_16\/mux_l2_in_1_:A0 1e-06 +5 chany_bottom_in[8]:5 0.0001155008 +6 chany_bottom_in[8]:6 0.0001155008 +7 chany_bottom_in[8]:7 7.277685e-05 +8 chany_bottom_in[8]:8 0.0001620527 +9 chany_bottom_in[8]:9 0.0001620527 +10 chany_bottom_in[8]:10 0.0001000594 +11 chany_bottom_in[8]:11 0.0001125881 +12 chany_bottom_in[8]:12 0.0001125881 +13 chany_bottom_in[8]:13 0.0003676211 +14 chany_bottom_in[8]:14 0.0003676211 +15 chany_bottom_in[8]:15 5.021226e-05 +16 chany_bottom_in[8]:16 5.021226e-05 +17 chany_bottom_in[8]:17 0.0006752124 +18 chany_bottom_in[8]:18 0.002613267 +19 chany_bottom_in[8]:19 0.001938055 +20 chany_bottom_in[8]:20 0.0001000594 +21 chany_bottom_in[8]:21 7.762579e-05 +22 chany_bottom_in[8]:22 0.0003664146 +23 chany_bottom_in[8]:23 0.0003289223 +24 chany_bottom_in[8]:24 4.41963e-05 +25 chany_bottom_in[8]:25 8.263342e-05 +26 chany_bottom_in[8]:26 5.895992e-05 +27 chany_bottom_in[8]:27 0.000190472 +28 chany_bottom_in[8]:28 0.000190472 +29 chany_bottom_in[8]:29 0.0008017828 +30 chany_bottom_in[8]:30 0.0008017828 +31 chany_bottom_in[8]:31 0.0006605235 +32 chany_bottom_in[8]:32 0.0006214184 +33 chany_bottom_in[8]:33 9.347262e-05 +34 chany_bottom_in[8]:34 9.347262e-05 +35 chany_bottom_in[8]:35 0.001794734 +36 chany_bottom_in[8]:29 chanx_right_in[10]:27 0.0003427826 +37 chany_bottom_in[8]:30 chanx_right_in[10]:28 0.0003427826 +38 chany_bottom_in[8]:27 chanx_right_in[16]:33 1.922091e-05 +39 chany_bottom_in[8]:28 chanx_right_in[16]:32 1.922091e-05 +40 chany_bottom_in[8]:29 chanx_right_in[16]:33 0.0002595953 +41 chany_bottom_in[8]:29 chanx_right_in[16]:39 0.0006734167 +42 chany_bottom_in[8]:30 chanx_right_in[16]:34 0.0002595953 +43 chany_bottom_in[8]:30 chanx_right_in[16]:40 0.0006734167 +44 chany_bottom_in[8]:19 chanx_left_in[4]:35 0.000642902 +45 chany_bottom_in[8]:19 chanx_left_in[4]:37 0.000319249 +46 chany_bottom_in[8]:19 chanx_left_in[4]:36 0.000358511 +47 chany_bottom_in[8]:18 chanx_left_in[4]:37 0.000358511 +48 chany_bottom_in[8]:18 chanx_left_in[4]:28 0.000319249 +49 chany_bottom_in[8]:18 chanx_left_in[4]:36 0.000642902 +50 chany_bottom_in[8] mux_tree_tapbuf_size12_4_sram[0]:21 0.0002689463 +51 chany_bottom_in[8]:35 mux_tree_tapbuf_size12_4_sram[0]:22 0.0002689463 +52 chany_bottom_in[8]:19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0007377357 +53 chany_bottom_in[8]:18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0007377357 +54 chany_bottom_in[8]:24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.377081e-07 +55 chany_bottom_in[8]:25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.377081e-07 +56 chany_bottom_in[8]:25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.377081e-07 +57 chany_bottom_in[8]:26 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.377081e-07 +58 chany_bottom_in[8]:27 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.957162e-05 +59 chany_bottom_in[8]:28 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.957162e-05 +60 chany_bottom_in[8] ropt_net_203:5 0.0001639234 +61 chany_bottom_in[8]:35 ropt_net_203:4 0.0001639234 +62 chany_bottom_in[8]:12 ropt_net_172:4 9.53679e-05 +63 chany_bottom_in[8]:11 ropt_net_172:5 9.53679e-05 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:35 0.03371875 +1 chany_bottom_in[8]:24 chany_bottom_in[8]:23 0.0045 +2 chany_bottom_in[8]:23 chany_bottom_in[8]:22 0.004816965 +3 chany_bottom_in[8]:33 chany_bottom_in[8]:32 0.0045 +4 chany_bottom_in[8]:32 chany_bottom_in[8]:31 0.009370537 +5 chany_bottom_in[8]:34 chany_bottom_in[8]:33 0.001151786 +6 chany_bottom_in[8]:35 chany_bottom_in[8]:34 0.0045 +7 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.001002232 +8 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.0045 +9 chany_bottom_in[8]:5 mux_right_track_16\/mux_l2_in_1_:A0 0.152 +10 chany_bottom_in[8]:25 mux_left_track_17\/mux_l2_in_1_:A0 0.152 +11 chany_bottom_in[8]:25 chany_bottom_in[8]:24 0.0001576087 +12 chany_bottom_in[8]:21 chany_bottom_in[8]:20 0.00341 +13 chany_bottom_in[8]:21 chany_bottom_in[8]:9 0.0045 +14 chany_bottom_in[8]:20 chany_bottom_in[8]:19 0.00341 +15 chany_bottom_in[8]:20 chany_bottom_in[8]:10 5.69697e-05 +16 chany_bottom_in[8]:19 chany_bottom_in[8]:18 0.007806308 +17 chany_bottom_in[8]:16 chany_bottom_in[8]:15 6.499219e-05 +18 chany_bottom_in[8]:17 chany_bottom_in[8]:16 0.00341 +19 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.004765625 +20 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.00341 +21 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.001979911 +22 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.0045 +23 chany_bottom_in[8]:11 FTB_31__30:A 0.152 +24 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.002131697 +25 chany_bottom_in[8]:8 mux_top_track_16\/mux_l1_in_2_:A0 0.152 +26 chany_bottom_in[8]:26 chany_bottom_in[8]:25 9.239131e-05 +27 chany_bottom_in[8]:27 chany_bottom_in[8]:26 0.0045 +28 chany_bottom_in[8]:28 chany_bottom_in[8]:27 0.003247768 +29 chany_bottom_in[8]:29 chany_bottom_in[8]:28 0.00341 +30 chany_bottom_in[8]:31 chany_bottom_in[8]:30 0.00341 +31 chany_bottom_in[8]:31 chany_bottom_in[8]:7 0.0004107143 +32 chany_bottom_in[8]:30 chany_bottom_in[8]:29 0.00302445 +33 chany_bottom_in[8]:22 chany_bottom_in[8]:21 0.0004107143 +34 chany_bottom_in[8]:18 chany_bottom_in[8]:17 0.001939142 + +*END + +*D_NET chany_bottom_in[16] 0.03722492 //LENGTH 223.590 LUMPCC 0.01786066 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 76.820 1.290 +*I mux_top_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 94.885 47.940 +*I mux_right_track_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 107.280 52.700 +*I BUFT_RR_92:A I *L 0.001767 *C 46.920 126.480 +*I mux_left_track_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 44.065 77.860 +*N chany_bottom_in[16]:5 *C 44.102 77.860 +*N chany_bottom_in[16]:6 *C 45.035 77.860 +*N chany_bottom_in[16]:7 *C 45.080 77.815 +*N chany_bottom_in[16]:8 *C 45.080 75.538 +*N chany_bottom_in[16]:9 *C 46.958 126.480 +*N chany_bottom_in[16]:10 *C 48.715 126.480 +*N chany_bottom_in[16]:11 *C 48.760 126.435 +*N chany_bottom_in[16]:12 *C 48.760 118.378 +*N chany_bottom_in[16]:13 *C 48.753 118.320 +*N chany_bottom_in[16]:14 *C 45.100 118.320 +*N chany_bottom_in[16]:15 *C 45.080 118.312 +*N chany_bottom_in[16]:16 *C 45.080 75.487 +*N chany_bottom_in[16]:17 *C 45.088 75.480 +*N chany_bottom_in[16]:18 *C 94.740 75.480 +*N chany_bottom_in[16]:19 *C 94.760 75.472 +*N chany_bottom_in[16]:20 *C 107.243 52.700 +*N chany_bottom_in[16]:21 *C 106.765 52.700 +*N chany_bottom_in[16]:22 *C 106.720 52.655 +*N chany_bottom_in[16]:23 *C 106.720 49.018 +*N chany_bottom_in[16]:24 *C 106.713 48.960 +*N chany_bottom_in[16]:25 *C 94.760 47.940 +*N chany_bottom_in[16]:26 *C 94.760 47.985 +*N chany_bottom_in[16]:27 *C 94.760 48.903 +*N chany_bottom_in[16]:28 *C 94.767 48.960 +*N chany_bottom_in[16]:29 *C 94.760 48.960 +*N chany_bottom_in[16]:30 *C 94.760 17.688 +*N chany_bottom_in[16]:31 *C 94.740 17.680 +*N chany_bottom_in[16]:32 *C 76.828 17.680 +*N chany_bottom_in[16]:33 *C 76.820 17.623 + +*CAP +0 chany_bottom_in[16] 0.0009132617 +1 mux_top_track_8\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_8\/mux_l2_in_2_:A1 1e-06 +3 BUFT_RR_92:A 1e-06 +4 mux_left_track_9\/mux_l2_in_2_:A1 1e-06 +5 chany_bottom_in[16]:5 8.000497e-05 +6 chany_bottom_in[16]:6 8.000497e-05 +7 chany_bottom_in[16]:7 0.0001632407 +8 chany_bottom_in[16]:8 0.0001632407 +9 chany_bottom_in[16]:9 7.892866e-05 +10 chany_bottom_in[16]:10 7.892866e-05 +11 chany_bottom_in[16]:11 0.0004304863 +12 chany_bottom_in[16]:12 0.0004304863 +13 chany_bottom_in[16]:13 0.0003740586 +14 chany_bottom_in[16]:14 0.0003740586 +15 chany_bottom_in[16]:15 0.001873743 +16 chany_bottom_in[16]:16 0.001873743 +17 chany_bottom_in[16]:17 0.002266012 +18 chany_bottom_in[16]:18 0.002266012 +19 chany_bottom_in[16]:19 0.0007707989 +20 chany_bottom_in[16]:20 5.683458e-05 +21 chany_bottom_in[16]:21 5.683458e-05 +22 chany_bottom_in[16]:22 0.0002145946 +23 chany_bottom_in[16]:23 0.0002145946 +24 chany_bottom_in[16]:24 0.0004490222 +25 chany_bottom_in[16]:25 3.281557e-05 +26 chany_bottom_in[16]:26 5.545076e-05 +27 chany_bottom_in[16]:27 5.545076e-05 +28 chany_bottom_in[16]:28 0.0004490222 +29 chany_bottom_in[16]:29 0.001618146 +30 chany_bottom_in[16]:30 0.0008473474 +31 chany_bottom_in[16]:31 0.001089938 +32 chany_bottom_in[16]:32 0.001089938 +33 chany_bottom_in[16]:33 0.0009132617 +34 chany_bottom_in[16]:29 chany_top_in[2]:22 0.0004583438 +35 chany_bottom_in[16]:29 chany_top_in[2]:23 0.0004375662 +36 chany_bottom_in[16]:19 chany_top_in[2]:23 0.0004583438 +37 chany_bottom_in[16]:19 chany_top_in[2]:24 9.597983e-06 +38 chany_bottom_in[16]:30 chany_top_in[2]:22 0.0004279682 +39 chany_bottom_in[16]:28 chanx_right_in[10]:28 0.0001775929 +40 chany_bottom_in[16]:28 chanx_right_in[10]:33 0.000493383 +41 chany_bottom_in[16]:24 chanx_right_in[10]:33 0.0001775929 +42 chany_bottom_in[16]:24 chanx_right_in[10]:34 0.000493383 +43 chany_bottom_in[16]:29 chany_bottom_in[2]:33 0.002398089 +44 chany_bottom_in[16]:29 chany_bottom_in[2]:34 0.0001237447 +45 chany_bottom_in[16]:19 chany_bottom_in[2]:32 0.001014172 +46 chany_bottom_in[16]:19 chany_bottom_in[2]:33 0.0001237447 +47 chany_bottom_in[16]:30 chany_bottom_in[2]:34 0.001383916 +48 chany_bottom_in[16]:18 chany_bottom_in[14]:9 0.001297957 +49 chany_bottom_in[16]:18 chany_bottom_in[14]:38 0.0004599123 +50 chany_bottom_in[16]:17 chany_bottom_in[14]:37 0.0004599123 +51 chany_bottom_in[16]:17 chany_bottom_in[14]:38 0.001297957 +52 chany_bottom_in[16]:16 chany_bottom_in[14]:20 0.0005735382 +53 chany_bottom_in[16]:14 chany_bottom_in[14]:17 7.778935e-06 +54 chany_bottom_in[16]:15 chany_bottom_in[14]:19 0.0005735382 +55 chany_bottom_in[16]:12 chany_bottom_in[14]:16 2.147914e-06 +56 chany_bottom_in[16]:13 chany_bottom_in[14]:18 7.778935e-06 +57 chany_bottom_in[16]:11 chany_bottom_in[14]:15 2.147914e-06 +58 chany_bottom_in[16]:18 chanx_left_in[5]:24 0.0001611345 +59 chany_bottom_in[16]:18 chanx_left_in[5]:25 0.0005930801 +60 chany_bottom_in[16]:17 chanx_left_in[5]:26 0.0005930801 +61 chany_bottom_in[16]:17 chanx_left_in[5]:25 0.0001611345 +62 chany_bottom_in[16]:16 chanx_left_in[13]:30 0.0004365791 +63 chany_bottom_in[16]:15 chanx_left_in[13]:31 0.0004365791 +64 chany_bottom_in[16]:28 prog_clk[0]:213 0.0001202039 +65 chany_bottom_in[16]:18 prog_clk[0]:423 0.0004312325 +66 chany_bottom_in[16]:18 prog_clk[0]:431 0.0003282735 +67 chany_bottom_in[16]:17 prog_clk[0]:431 0.0004312325 +68 chany_bottom_in[16]:17 prog_clk[0]:435 0.0003282735 +69 chany_bottom_in[16]:27 prog_clk[0]:214 3.228131e-05 +70 chany_bottom_in[16]:26 prog_clk[0]:215 3.228131e-05 +71 chany_bottom_in[16]:24 prog_clk[0]:212 0.0001202039 +72 chany_bottom_in[16]:31 prog_clk[0]:336 7.020842e-05 +73 chany_bottom_in[16]:31 prog_clk[0]:327 5.345966e-05 +74 chany_bottom_in[16]:32 prog_clk[0]:341 7.020842e-05 +75 chany_bottom_in[16]:32 prog_clk[0]:328 5.345966e-05 +76 chany_bottom_in[16] ropt_net_203:5 0.0001613416 +77 chany_bottom_in[16]:33 ropt_net_203:4 0.0001613416 +78 chany_bottom_in[16]:12 ropt_net_191:6 3.158096e-05 +79 chany_bottom_in[16]:10 ropt_net_191:8 8.089988e-05 +80 chany_bottom_in[16]:11 ropt_net_191:7 3.158096e-05 +81 chany_bottom_in[16]:9 ropt_net_191:9 8.089988e-05 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:33 0.01458259 +1 chany_bottom_in[16]:28 chany_bottom_in[16]:27 0.00341 +2 chany_bottom_in[16]:28 chany_bottom_in[16]:24 0.001871383 +3 chany_bottom_in[16]:29 chany_bottom_in[16]:28 0.00341 +4 chany_bottom_in[16]:29 chany_bottom_in[16]:19 0.004153625 +5 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.007778891 +6 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.00341 +7 chany_bottom_in[16]:17 chany_bottom_in[16]:16 0.00341 +8 chany_bottom_in[16]:17 chany_bottom_in[16]:8 0.00341 +9 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.00670925 +10 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.000572225 +11 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.00341 +12 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.007194198 +13 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.00341 +14 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.001569197 +15 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.0045 +16 chany_bottom_in[16]:9 BUFT_RR_92:A 0.152 +17 chany_bottom_in[16]:27 chany_bottom_in[16]:26 0.0008191965 +18 chany_bottom_in[16]:25 mux_top_track_8\/mux_l2_in_1_:A0 0.152 +19 chany_bottom_in[16]:26 chany_bottom_in[16]:25 0.0045 +20 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.003247768 +21 chany_bottom_in[16]:24 chany_bottom_in[16]:23 0.00341 +22 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.0004263393 +23 chany_bottom_in[16]:22 chany_bottom_in[16]:21 0.0045 +24 chany_bottom_in[16]:20 mux_right_track_8\/mux_l2_in_2_:A1 0.152 +25 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.002033482 +26 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.0008325893 +27 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.0045 +28 chany_bottom_in[16]:5 mux_left_track_9\/mux_l2_in_2_:A1 0.152 +29 chany_bottom_in[16]:31 chany_bottom_in[16]:30 0.00341 +30 chany_bottom_in[16]:30 chany_bottom_in[16]:29 0.004899358 +31 chany_bottom_in[16]:33 chany_bottom_in[16]:32 0.00341 +32 chany_bottom_in[16]:32 chany_bottom_in[16]:31 0.002806291 + +*END + +*D_NET chanx_left_in[8] 0.02518801 //LENGTH 178.428 LUMPCC 0.004370813 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 43.520 +*I mux_top_track_16\/mux_l2_in_2_:A0 I *L 0.001631 *C 36.515 49.640 +*I ropt_mt_inst_799:A I *L 0.001767 *C 130.180 66.640 +*I mux_right_track_16\/mux_l2_in_2_:A0 I *L 0.001631 *C 77.455 53.380 +*I mux_bottom_track_17\/mux_l2_in_2_:A1 I *L 0.00198 *C 44.720 41.820 +*N chanx_left_in[8]:5 *C 44.620 41.820 +*N chanx_left_in[8]:6 *C 44.620 41.820 +*N chanx_left_in[8]:7 *C 77.418 53.380 +*N chanx_left_in[8]:8 *C 76.865 53.380 +*N chanx_left_in[8]:9 *C 76.820 53.335 +*N chanx_left_in[8]:10 *C 130.218 66.640 +*N chanx_left_in[8]:11 *C 131.515 66.640 +*N chanx_left_in[8]:12 *C 131.560 66.595 +*N chanx_left_in[8]:13 *C 131.560 58.865 +*N chanx_left_in[8]:14 *C 131.560 58.820 +*N chanx_left_in[8]:15 *C 127.005 58.820 +*N chanx_left_in[8]:16 *C 126.960 58.775 +*N chanx_left_in[8]:17 *C 126.960 55.125 +*N chanx_left_in[8]:18 *C 126.915 55.080 +*N chanx_left_in[8]:19 *C 100.785 55.080 +*N chanx_left_in[8]:20 *C 100.740 55.035 +*N chanx_left_in[8]:21 *C 100.740 52.405 +*N chanx_left_in[8]:22 *C 100.695 52.360 +*N chanx_left_in[8]:23 *C 76.865 52.360 +*N chanx_left_in[8]:24 *C 76.820 52.360 +*N chanx_left_in[8]:25 *C 76.820 41.538 +*N chanx_left_in[8]:26 *C 76.812 41.480 +*N chanx_left_in[8]:27 *C 44.628 41.480 +*N chanx_left_in[8]:28 *C 44.620 41.480 +*N chanx_left_in[8]:29 *C 44.160 41.480 +*N chanx_left_in[8]:30 *C 44.160 49.595 +*N chanx_left_in[8]:31 *C 44.115 49.640 +*N chanx_left_in[8]:32 *C 36.553 49.640 +*N chanx_left_in[8]:33 *C 36.340 49.640 +*N chanx_left_in[8]:34 *C 36.340 49.595 +*N chanx_left_in[8]:35 *C 36.340 44.258 +*N chanx_left_in[8]:36 *C 36.333 44.200 +*N chanx_left_in[8]:37 *C 5.520 44.200 +*N chanx_left_in[8]:38 *C 5.520 43.520 + +*CAP +0 chanx_left_in[8] 0.0003311598 +1 mux_top_track_16\/mux_l2_in_2_:A0 1e-06 +2 ropt_mt_inst_799:A 1e-06 +3 mux_right_track_16\/mux_l2_in_2_:A0 1e-06 +4 mux_bottom_track_17\/mux_l2_in_2_:A1 1e-06 +5 chanx_left_in[8]:5 3.330577e-05 +6 chanx_left_in[8]:6 6.178652e-05 +7 chanx_left_in[8]:7 6.939374e-05 +8 chanx_left_in[8]:8 6.939374e-05 +9 chanx_left_in[8]:9 6.759411e-05 +10 chanx_left_in[8]:10 0.0001200698 +11 chanx_left_in[8]:11 0.0001200698 +12 chanx_left_in[8]:12 0.0004428497 +13 chanx_left_in[8]:13 0.0004428497 +14 chanx_left_in[8]:14 0.0003298286 +15 chanx_left_in[8]:15 0.0002974102 +16 chanx_left_in[8]:16 0.0002119349 +17 chanx_left_in[8]:17 0.0002119349 +18 chanx_left_in[8]:18 0.00171519 +19 chanx_left_in[8]:19 0.00171519 +20 chanx_left_in[8]:20 0.0001744373 +21 chanx_left_in[8]:21 0.0001744373 +22 chanx_left_in[8]:22 0.001726191 +23 chanx_left_in[8]:23 0.001726191 +24 chanx_left_in[8]:24 0.0007388892 +25 chanx_left_in[8]:25 0.000637155 +26 chanx_left_in[8]:26 0.00202834 +27 chanx_left_in[8]:27 0.00202834 +28 chanx_left_in[8]:28 9.898853e-05 +29 chanx_left_in[8]:29 0.0005074596 +30 chanx_left_in[8]:30 0.0004722723 +31 chanx_left_in[8]:31 0.000535456 +32 chanx_left_in[8]:32 0.000561592 +33 chanx_left_in[8]:33 6.53534e-05 +34 chanx_left_in[8]:34 0.0003265225 +35 chanx_left_in[8]:35 0.0003265225 +36 chanx_left_in[8]:36 0.001008641 +37 chanx_left_in[8]:37 0.001056964 +38 chanx_left_in[8]:38 0.0003794827 +39 chanx_left_in[8]:36 chanx_right_in[4]:18 0.0003608905 +40 chanx_left_in[8]:27 chanx_right_in[4]:17 3.253159e-07 +41 chanx_left_in[8]:27 chanx_right_in[4]:18 1.6123e-06 +42 chanx_left_in[8]:26 chanx_right_in[4]:18 3.253159e-07 +43 chanx_left_in[8]:26 chanx_right_in[4]:19 1.6123e-06 +44 chanx_left_in[8]:37 chanx_right_in[4]:17 0.0003608905 +45 chanx_left_in[8]:36 chanx_right_in[13]:27 0.00059773 +46 chanx_left_in[8]:27 chanx_right_in[13]:15 1.466897e-05 +47 chanx_left_in[8]:27 chanx_right_in[13]:27 0.0002019436 +48 chanx_left_in[8]:26 chanx_right_in[13]:27 1.466897e-05 +49 chanx_left_in[8]:26 chanx_right_in[13]:28 0.0002019436 +50 chanx_left_in[8]:37 chanx_right_in[13]:15 0.00059773 +51 chanx_left_in[8]:34 prog_clk[0]:409 8.70368e-07 +52 chanx_left_in[8]:35 prog_clk[0]:410 8.70368e-07 +53 chanx_left_in[8]:36 prog_clk[0]:485 0.0002703072 +54 chanx_left_in[8]:36 prog_clk[0]:638 0.0001662336 +55 chanx_left_in[8]:27 prog_clk[0]:315 0.0001897185 +56 chanx_left_in[8]:26 prog_clk[0]:314 0.0001897185 +57 chanx_left_in[8]:38 prog_clk[0]:706 1.081324e-05 +58 chanx_left_in[8]:37 prog_clk[0]:639 0.0001662336 +59 chanx_left_in[8]:37 prog_clk[0]:679 1.081324e-05 +60 chanx_left_in[8]:37 prog_clk[0]:638 0.0002703072 +61 chanx_left_in[8]:6 bottom_left_grid_pin_40_[0]:11 1.907628e-08 +62 chanx_left_in[8]:28 bottom_left_grid_pin_40_[0]:12 1.907628e-08 +63 chanx_left_in[8]:27 bottom_left_grid_pin_40_[0]:13 0.0002303374 +64 chanx_left_in[8]:27 bottom_left_grid_pin_40_[0]:14 4.274502e-05 +65 chanx_left_in[8]:26 bottom_left_grid_pin_40_[0]:8 0.0002303374 +66 chanx_left_in[8]:26 bottom_left_grid_pin_40_[0]:13 4.274502e-05 +67 chanx_left_in[8]:31 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.832188e-05 +68 chanx_left_in[8]:30 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.506074e-07 +69 chanx_left_in[8]:32 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.832188e-05 +70 chanx_left_in[8]:29 mux_top_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.506074e-07 +71 chanx_left_in[8]:24 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.871877e-05 +72 chanx_left_in[8]:25 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.871877e-05 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:38 0.0006720999 +1 chanx_left_in[8]:23 chanx_left_in[8]:22 0.02127679 +2 chanx_left_in[8]:24 chanx_left_in[8]:23 0.0045 +3 chanx_left_in[8]:24 chanx_left_in[8]:9 0.0008705358 +4 chanx_left_in[8]:22 chanx_left_in[8]:21 0.0045 +5 chanx_left_in[8]:21 chanx_left_in[8]:20 0.002348214 +6 chanx_left_in[8]:19 chanx_left_in[8]:18 0.02333036 +7 chanx_left_in[8]:20 chanx_left_in[8]:19 0.0045 +8 chanx_left_in[8]:18 chanx_left_in[8]:17 0.0045 +9 chanx_left_in[8]:17 chanx_left_in[8]:16 0.003258929 +10 chanx_left_in[8]:15 chanx_left_in[8]:14 0.004066965 +11 chanx_left_in[8]:16 chanx_left_in[8]:15 0.0045 +12 chanx_left_in[8]:14 chanx_left_in[8]:13 0.0045 +13 chanx_left_in[8]:13 chanx_left_in[8]:12 0.006901786 +14 chanx_left_in[8]:11 chanx_left_in[8]:10 0.001158482 +15 chanx_left_in[8]:12 chanx_left_in[8]:11 0.0045 +16 chanx_left_in[8]:10 ropt_mt_inst_799:A 0.152 +17 chanx_left_in[8]:31 chanx_left_in[8]:30 0.0045 +18 chanx_left_in[8]:30 chanx_left_in[8]:29 0.007245536 +19 chanx_left_in[8]:33 chanx_left_in[8]:32 0.0001154891 +20 chanx_left_in[8]:34 chanx_left_in[8]:33 0.0045 +21 chanx_left_in[8]:35 chanx_left_in[8]:34 0.004765625 +22 chanx_left_in[8]:36 chanx_left_in[8]:35 0.00341 +23 chanx_left_in[8]:5 mux_bottom_track_17\/mux_l2_in_2_:A1 0.152 +24 chanx_left_in[8]:6 chanx_left_in[8]:5 0.0045 +25 chanx_left_in[8]:8 chanx_left_in[8]:7 0.0004933036 +26 chanx_left_in[8]:9 chanx_left_in[8]:8 0.0045 +27 chanx_left_in[8]:7 mux_right_track_16\/mux_l2_in_2_:A0 0.152 +28 chanx_left_in[8]:28 chanx_left_in[8]:27 0.00341 +29 chanx_left_in[8]:28 chanx_left_in[8]:6 0.0001634616 +30 chanx_left_in[8]:27 chanx_left_in[8]:26 0.005042316 +31 chanx_left_in[8]:25 chanx_left_in[8]:24 0.009662947 +32 chanx_left_in[8]:26 chanx_left_in[8]:25 0.00341 +33 chanx_left_in[8]:32 mux_top_track_16\/mux_l2_in_2_:A0 0.152 +34 chanx_left_in[8]:32 chanx_left_in[8]:31 0.006752232 +35 chanx_left_in[8]:29 chanx_left_in[8]:28 0.0004107143 +36 chanx_left_in[8]:38 chanx_left_in[8]:37 0.0001065333 +37 chanx_left_in[8]:37 chanx_left_in[8]:36 0.004827291 + +*END + +*D_NET prog_clk[0] 0.1752564 //LENGTH 1144.165 LUMPCC 0.05045065 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 2.300 28.490 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 12.685 36.720 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 13.605 42.160 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 11.765 58.480 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.365 55.760 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 14.525 47.600 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.585 63.920 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 7.540 69.360 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 12.225 74.800 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 11.745 77.520 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:CLK I *L 0.001922 *C 7.545 85.680 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 4.440 93.840 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 26.025 36.720 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 24.185 47.600 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 22.785 58.480 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 26.025 72.080 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 24.185 80.240 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 25.565 93.840 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 30.625 91.120 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 32.925 96.560 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 41.665 93.840 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 41.665 99.280 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 46.355 104.720 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 46.725 110.160 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 47.645 115.600 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 61.905 102.000 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 65.585 107.440 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 74.365 121.040 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 77.085 118.320 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 82.605 110.160 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 87.665 118.320 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 90.425 115.600 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 94.105 112.880 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.505 115.600 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 63.285 110.160 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 31.545 102.000 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 31.545 104.720 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:CLK I *L 0.001922 *C 37.985 110.160 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 37.985 121.040 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 41.150 123.760 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.545 115.600 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 28.785 82.960 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 23.725 85.680 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 28.785 44.880 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 38.445 53.040 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 40.285 55.760 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 31.570 61.200 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 30.625 63.920 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 40.285 63.920 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 39.365 66.640 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 50.865 63.920 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 36.205 72.080 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 41.205 74.800 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 50.865 77.520 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 50.865 80.240 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.605 74.800 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.985 82.960 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 40.285 61.200 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 32.925 47.600 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 20.045 44.880 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 36.670 23.120 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.650 9.520 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 44.345 9.520 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:CLK I *L 0.001922 *C 38.445 17.680 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 39.365 31.280 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 42.125 34.000 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 48.565 20.400 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 57.305 14.960 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 55.005 12.240 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.045 14.960 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 70.645 20.400 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 74.745 14.960 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 83.065 17.680 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 83.525 14.960 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 91.345 20.400 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 55.925 39.440 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 60.065 42.160 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 55.925 47.600 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 58.225 36.720 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 79.325 44.880 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 81.720 61.200 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 88.125 63.920 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 83.065 72.080 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.965 77.520 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.925 80.240 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 94.565 85.680 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 96.405 88.400 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 102.845 99.280 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 100.545 115.600 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.925 107.440 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 101.925 93.840 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 83.065 39.440 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 90.885 42.160 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.005 50.320 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 92.725 61.200 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 96.865 55.760 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 106.030 72.080 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 108.365 66.640 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 113.425 58.480 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 119.405 61.200 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 117.195 66.640 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:CLK I *L 0.001922 *C 120.280 72.080 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 124.005 77.520 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 124.930 85.680 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 128.145 88.400 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 120.785 91.120 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 118.025 99.280 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 104.685 58.480 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 86.745 31.280 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 99.625 25.840 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 102.845 36.720 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 106.985 39.440 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.465 31.280 +*N prog_clk[0]:113 *C 101.465 31.280 +*N prog_clk[0]:114 *C 101.593 31.620 +*N prog_clk[0]:115 *C 106.948 39.440 +*N prog_clk[0]:116 *C 106.305 39.440 +*N prog_clk[0]:117 *C 106.260 39.440 +*N prog_clk[0]:118 *C 106.253 39.440 +*N prog_clk[0]:119 *C 101.668 39.440 +*N prog_clk[0]:120 *C 101.660 39.383 +*N prog_clk[0]:121 *C 102.808 36.720 +*N prog_clk[0]:122 *C 101.660 36.720 +*N prog_clk[0]:123 *C 101.660 37.060 +*N prog_clk[0]:124 *C 101.660 37.060 +*N prog_clk[0]:125 *C 101.660 31.665 +*N prog_clk[0]:126 *C 101.615 31.613 +*N prog_clk[0]:127 *C 99.865 31.620 +*N prog_clk[0]:128 *C 99.820 31.575 +*N prog_clk[0]:129 *C 99.625 25.840 +*N prog_clk[0]:130 *C 99.820 25.840 +*N prog_clk[0]:131 *C 99.820 25.885 +*N prog_clk[0]:132 *C 99.820 29.240 +*N prog_clk[0]:133 *C 99.812 29.240 +*N prog_clk[0]:134 *C 86.745 31.280 +*N prog_clk[0]:135 *C 86.480 31.280 +*N prog_clk[0]:136 *C 86.480 31.235 +*N prog_clk[0]:137 *C 86.480 29.298 +*N prog_clk[0]:138 *C 86.480 29.240 +*N prog_clk[0]:139 *C 104.648 58.480 +*N prog_clk[0]:140 *C 104.005 58.480 +*N prog_clk[0]:141 *C 118.025 99.280 +*N prog_clk[0]:142 *C 118.220 99.280 +*N prog_clk[0]:143 *C 118.220 99.235 +*N prog_clk[0]:144 *C 120.748 91.120 +*N prog_clk[0]:145 *C 120.105 91.120 +*N prog_clk[0]:146 *C 120.060 91.120 +*N prog_clk[0]:147 *C 120.053 91.120 +*N prog_clk[0]:148 *C 118.228 91.120 +*N prog_clk[0]:149 *C 118.220 91.120 +*N prog_clk[0]:150 *C 128.145 88.400 +*N prog_clk[0]:151 *C 127.880 88.400 +*N prog_clk[0]:152 *C 127.880 88.355 +*N prog_clk[0]:153 *C 127.880 85.737 +*N prog_clk[0]:154 *C 127.873 85.680 +*N prog_clk[0]:155 *C 124.930 85.680 +*N prog_clk[0]:156 *C 125.120 85.680 +*N prog_clk[0]:157 *C 125.120 85.680 +*N prog_clk[0]:158 *C 125.120 85.680 +*N prog_clk[0]:159 *C 118.228 85.680 +*N prog_clk[0]:160 *C 118.220 85.680 +*N prog_clk[0]:161 *C 124.005 77.520 +*N prog_clk[0]:162 *C 123.740 77.520 +*N prog_clk[0]:163 *C 123.740 77.520 +*N prog_clk[0]:164 *C 123.733 77.520 +*N prog_clk[0]:165 *C 118.228 77.520 +*N prog_clk[0]:166 *C 118.220 77.520 +*N prog_clk[0]:167 *C 120.243 72.080 +*N prog_clk[0]:168 *C 118.265 72.080 +*N prog_clk[0]:169 *C 118.220 72.080 +*N prog_clk[0]:170 *C 117.195 66.640 +*N prog_clk[0]:171 *C 117.300 66.640 +*N prog_clk[0]:172 *C 118.220 66.640 +*N prog_clk[0]:173 *C 119.368 61.200 +*N prog_clk[0]:174 *C 118.220 61.200 +*N prog_clk[0]:175 *C 118.220 60.860 +*N prog_clk[0]:176 *C 118.220 60.860 +*N prog_clk[0]:177 *C 118.220 58.538 +*N prog_clk[0]:178 *C 118.213 58.480 +*N prog_clk[0]:179 *C 113.425 58.480 +*N prog_clk[0]:180 *C 113.620 58.480 +*N prog_clk[0]:181 *C 113.620 58.480 +*N prog_clk[0]:182 *C 113.620 58.480 +*N prog_clk[0]:183 *C 108.365 66.640 +*N prog_clk[0]:184 *C 106.030 72.080 +*N prog_clk[0]:185 *C 106.260 72.080 +*N prog_clk[0]:186 *C 106.260 72.035 +*N prog_clk[0]:187 *C 106.260 66.345 +*N prog_clk[0]:188 *C 106.305 66.300 +*N prog_clk[0]:189 *C 108.145 66.308 +*N prog_clk[0]:190 *C 108.100 66.255 +*N prog_clk[0]:191 *C 108.100 58.538 +*N prog_clk[0]:192 *C 108.100 58.480 +*N prog_clk[0]:193 *C 103.968 58.480 +*N prog_clk[0]:194 *C 103.960 58.480 +*N prog_clk[0]:195 *C 103.500 58.480 +*N prog_clk[0]:196 *C 103.500 55.818 +*N prog_clk[0]:197 *C 103.493 55.760 +*N prog_clk[0]:198 *C 96.865 55.760 +*N prog_clk[0]:199 *C 97.060 55.760 +*N prog_clk[0]:200 *C 97.060 55.760 +*N prog_clk[0]:201 *C 97.060 55.760 +*N prog_clk[0]:202 *C 92.725 61.200 +*N prog_clk[0]:203 *C 92.920 61.200 +*N prog_clk[0]:204 *C 92.920 61.155 +*N prog_clk[0]:205 *C 92.920 55.818 +*N prog_clk[0]:206 *C 92.928 55.760 +*N prog_clk[0]:207 *C 94.300 55.760 +*N prog_clk[0]:208 *C 94.300 55.703 +*N prog_clk[0]:209 *C 101.005 50.320 +*N prog_clk[0]:210 *C 100.740 50.320 +*N prog_clk[0]:211 *C 100.740 50.320 +*N prog_clk[0]:212 *C 100.733 50.320 +*N prog_clk[0]:213 *C 94.308 50.320 +*N prog_clk[0]:214 *C 94.300 50.320 +*N prog_clk[0]:215 *C 94.300 47.657 +*N prog_clk[0]:216 *C 94.293 47.600 +*N prog_clk[0]:217 *C 90.627 47.600 +*N prog_clk[0]:218 *C 90.620 47.543 +*N prog_clk[0]:219 *C 90.885 42.160 +*N prog_clk[0]:220 *C 90.620 42.500 +*N prog_clk[0]:221 *C 90.620 42.545 +*N prog_clk[0]:222 *C 90.160 42.500 +*N prog_clk[0]:223 *C 90.160 39.498 +*N prog_clk[0]:224 *C 90.153 39.440 +*N prog_clk[0]:225 *C 83.065 39.440 +*N prog_clk[0]:226 *C 82.800 39.440 +*N prog_clk[0]:227 *C 82.800 39.440 +*N prog_clk[0]:228 *C 82.800 39.440 +*N prog_clk[0]:229 *C 101.925 93.840 +*N prog_clk[0]:230 *C 101.660 93.840 +*N prog_clk[0]:231 *C 101.660 93.795 +*N prog_clk[0]:232 *C 101.660 92.538 +*N prog_clk[0]:233 *C 101.653 92.480 +*N prog_clk[0]:234 *C 101.925 107.440 +*N prog_clk[0]:235 *C 101.660 107.440 +*N prog_clk[0]:236 *C 101.660 107.440 +*N prog_clk[0]:237 *C 101.653 107.440 +*N prog_clk[0]:238 *C 100.508 115.600 +*N prog_clk[0]:239 *C 99.865 115.600 +*N prog_clk[0]:240 *C 99.820 115.555 +*N prog_clk[0]:241 *C 99.820 107.498 +*N prog_clk[0]:242 *C 99.828 107.440 +*N prog_clk[0]:243 *C 99.375 107.440 +*N prog_clk[0]:244 *C 99.360 107.433 +*N prog_clk[0]:245 *C 102.808 99.280 +*N prog_clk[0]:246 *C 101.705 99.280 +*N prog_clk[0]:247 *C 101.660 99.280 +*N prog_clk[0]:248 *C 101.653 99.280 +*N prog_clk[0]:249 *C 99.380 99.280 +*N prog_clk[0]:250 *C 99.360 99.280 +*N prog_clk[0]:251 *C 99.360 92.488 +*N prog_clk[0]:252 *C 99.360 92.480 +*N prog_clk[0]:253 *C 96.608 92.480 +*N prog_clk[0]:254 *C 96.600 92.422 +*N prog_clk[0]:255 *C 96.405 88.400 +*N prog_clk[0]:256 *C 96.600 88.060 +*N prog_clk[0]:257 *C 96.600 88.060 +*N prog_clk[0]:258 *C 96.600 87.098 +*N prog_clk[0]:259 *C 96.593 87.040 +*N prog_clk[0]:260 *C 94.308 87.040 +*N prog_clk[0]:261 *C 94.300 86.983 +*N prog_clk[0]:262 *C 94.565 85.680 +*N prog_clk[0]:263 *C 94.300 86.020 +*N prog_clk[0]:264 *C 94.300 86.020 +*N prog_clk[0]:265 *C 101.925 80.240 +*N prog_clk[0]:266 *C 101.660 80.240 +*N prog_clk[0]:267 *C 101.660 80.240 +*N prog_clk[0]:268 *C 101.653 80.240 +*N prog_clk[0]:269 *C 94.308 80.240 +*N prog_clk[0]:270 *C 94.300 80.240 +*N prog_clk[0]:271 *C 94.300 77.578 +*N prog_clk[0]:272 *C 94.293 77.520 +*N prog_clk[0]:273 *C 89.965 77.520 +*N prog_clk[0]:274 *C 90.160 77.520 +*N prog_clk[0]:275 *C 90.160 77.520 +*N prog_clk[0]:276 *C 90.160 77.520 +*N prog_clk[0]:277 *C 82.808 77.520 +*N prog_clk[0]:278 *C 82.800 77.463 +*N prog_clk[0]:279 *C 83.065 72.080 +*N prog_clk[0]:280 *C 82.800 71.740 +*N prog_clk[0]:281 *C 82.800 71.740 +*N prog_clk[0]:282 *C 88.088 63.920 +*N prog_clk[0]:283 *C 87.445 63.920 +*N prog_clk[0]:284 *C 87.400 63.875 +*N prog_clk[0]:285 *C 87.400 62.617 +*N prog_clk[0]:286 *C 87.392 62.560 +*N prog_clk[0]:287 *C 82.808 62.560 +*N prog_clk[0]:288 *C 82.800 62.617 +*N prog_clk[0]:289 *C 81.420 62.560 +*N prog_clk[0]:290 *C 81.720 61.200 +*N prog_clk[0]:291 *C 81.420 61.200 +*N prog_clk[0]:292 *C 81.420 61.245 +*N prog_clk[0]:293 *C 81.375 60.860 +*N prog_clk[0]:294 *C 80.960 60.860 +*N prog_clk[0]:295 *C 79.325 44.880 +*N prog_clk[0]:296 *C 79.580 44.880 +*N prog_clk[0]:297 *C 79.580 44.880 +*N prog_clk[0]:298 *C 80.960 44.880 +*N prog_clk[0]:299 *C 80.960 39.498 +*N prog_clk[0]:300 *C 80.968 39.440 +*N prog_clk[0]:301 *C 80.960 39.433 +*N prog_clk[0]:302 *C 80.960 29.248 +*N prog_clk[0]:303 *C 80.960 29.240 +*N prog_clk[0]:304 *C 58.188 36.720 +*N prog_clk[0]:305 *C 57.545 36.720 +*N prog_clk[0]:306 *C 57.500 36.720 +*N prog_clk[0]:307 *C 55.925 47.600 +*N prog_clk[0]:308 *C 55.660 47.600 +*N prog_clk[0]:309 *C 55.660 47.555 +*N prog_clk[0]:310 *C 55.660 42.160 +*N prog_clk[0]:311 *C 60.065 42.160 +*N prog_clk[0]:312 *C 60.260 42.160 +*N prog_clk[0]:313 *C 60.260 42.160 +*N prog_clk[0]:314 *C 60.253 42.160 +*N prog_clk[0]:315 *C 57.047 42.160 +*N prog_clk[0]:316 *C 57.040 42.102 +*N prog_clk[0]:317 *C 55.925 39.440 +*N prog_clk[0]:318 *C 56.120 39.440 +*N prog_clk[0]:319 *C 56.120 39.440 +*N prog_clk[0]:320 *C 57.040 39.440 +*N prog_clk[0]:321 *C 57.040 36.720 +*N prog_clk[0]:322 *C 57.040 29.298 +*N prog_clk[0]:323 *C 57.040 29.240 +*N prog_clk[0]:324 *C 91.345 20.400 +*N prog_clk[0]:325 *C 91.080 20.400 +*N prog_clk[0]:326 *C 91.080 20.400 +*N prog_clk[0]:327 *C 91.073 20.400 +*N prog_clk[0]:328 *C 83.260 20.400 +*N prog_clk[0]:329 *C 83.525 14.960 +*N prog_clk[0]:330 *C 83.260 14.960 +*N prog_clk[0]:331 *C 83.260 15.005 +*N prog_clk[0]:332 *C 83.065 17.680 +*N prog_clk[0]:333 *C 83.260 17.340 +*N prog_clk[0]:334 *C 83.260 17.340 +*N prog_clk[0]:335 *C 83.260 19.663 +*N prog_clk[0]:336 *C 83.260 19.728 +*N prog_clk[0]:337 *C 74.745 14.960 +*N prog_clk[0]:338 *C 74.520 14.960 +*N prog_clk[0]:339 *C 74.520 15.005 +*N prog_clk[0]:340 *C 74.520 19.663 +*N prog_clk[0]:341 *C 74.520 19.720 +*N prog_clk[0]:342 *C 74.520 20.400 +*N prog_clk[0]:343 *C 70.645 20.400 +*N prog_clk[0]:344 *C 70.380 20.400 +*N prog_clk[0]:345 *C 70.380 20.400 +*N prog_clk[0]:346 *C 70.380 20.400 +*N prog_clk[0]:347 *C 64.860 20.400 +*N prog_clk[0]:348 *C 66.008 14.960 +*N prog_clk[0]:349 *C 64.905 14.960 +*N prog_clk[0]:350 *C 64.860 15.005 +*N prog_clk[0]:351 *C 64.860 19.663 +*N prog_clk[0]:352 *C 64.860 19.728 +*N prog_clk[0]:353 *C 55.005 12.240 +*N prog_clk[0]:354 *C 55.200 12.240 +*N prog_clk[0]:355 *C 55.200 12.285 +*N prog_clk[0]:356 *C 57.268 14.960 +*N prog_clk[0]:357 *C 55.200 14.960 +*N prog_clk[0]:358 *C 55.200 15.300 +*N prog_clk[0]:359 *C 55.200 15.300 +*N prog_clk[0]:360 *C 55.200 19.663 +*N prog_clk[0]:361 *C 55.200 19.720 +*N prog_clk[0]:362 *C 48.308 19.720 +*N prog_clk[0]:363 *C 48.300 19.777 +*N prog_clk[0]:364 *C 48.565 20.400 +*N prog_clk[0]:365 *C 48.300 20.400 +*N prog_clk[0]:366 *C 48.300 20.400 +*N prog_clk[0]:367 *C 48.300 29.183 +*N prog_clk[0]:368 *C 48.300 29.240 +*N prog_clk[0]:369 *C 42.125 34.000 +*N prog_clk[0]:370 *C 41.860 34.000 +*N prog_clk[0]:371 *C 41.860 34.000 +*N prog_clk[0]:372 *C 41.852 34.000 +*N prog_clk[0]:373 *C 39.108 34.000 +*N prog_clk[0]:374 *C 39.100 33.943 +*N prog_clk[0]:375 *C 39.365 31.280 +*N prog_clk[0]:376 *C 39.100 31.620 +*N prog_clk[0]:377 *C 39.100 31.620 +*N prog_clk[0]:378 *C 39.100 29.298 +*N prog_clk[0]:379 *C 39.100 29.240 +*N prog_clk[0]:380 *C 38.445 17.680 +*N prog_clk[0]:381 *C 38.180 17.680 +*N prog_clk[0]:382 *C 38.180 17.680 +*N prog_clk[0]:383 *C 44.323 9.492 +*N prog_clk[0]:384 *C 44.310 9.180 +*N prog_clk[0]:385 *C 41.905 9.180 +*N prog_clk[0]:386 *C 41.860 9.180 +*N prog_clk[0]:387 *C 41.860 9.520 +*N prog_clk[0]:388 *C 41.852 9.520 +*N prog_clk[0]:389 *C 37.727 9.520 +*N prog_clk[0]:390 *C 37.720 9.578 +*N prog_clk[0]:391 *C 35.678 9.543 +*N prog_clk[0]:392 *C 35.880 9.555 +*N prog_clk[0]:393 *C 35.880 10.200 +*N prog_clk[0]:394 *C 37.675 10.200 +*N prog_clk[0]:395 *C 37.720 10.200 +*N prog_clk[0]:396 *C 37.720 17.680 +*N prog_clk[0]:397 *C 36.670 23.120 +*N prog_clk[0]:398 *C 36.800 23.120 +*N prog_clk[0]:399 *C 37.720 23.120 +*N prog_clk[0]:400 *C 37.720 29.183 +*N prog_clk[0]:401 *C 37.720 29.240 +*N prog_clk[0]:402 *C 20.045 44.880 +*N prog_clk[0]:403 *C 20.240 44.540 +*N prog_clk[0]:404 *C 20.655 44.540 +*N prog_clk[0]:405 *C 20.730 44.570 +*N prog_clk[0]:406 *C 20.745 44.880 +*N prog_clk[0]:407 *C 32.925 47.600 +*N prog_clk[0]:408 *C 33.120 47.600 +*N prog_clk[0]:409 *C 33.120 47.555 +*N prog_clk[0]:410 *C 33.120 46.240 +*N prog_clk[0]:411 *C 40.248 61.200 +*N prog_clk[0]:412 *C 39.145 61.200 +*N prog_clk[0]:413 *C 39.100 61.200 +*N prog_clk[0]:414 *C 39.093 61.200 +*N prog_clk[0]:415 *C 37.720 61.200 +*N prog_clk[0]:416 *C 60.948 82.960 +*N prog_clk[0]:417 *C 60.305 82.960 +*N prog_clk[0]:418 *C 60.260 82.915 +*N prog_clk[0]:419 *C 60.260 74.800 +*N prog_clk[0]:420 *C 59.605 74.800 +*N prog_clk[0]:421 *C 59.340 74.800 +*N prog_clk[0]:422 *C 59.340 74.800 +*N prog_clk[0]:423 *C 59.333 74.800 +*N prog_clk[0]:424 *C 50.865 80.240 +*N prog_clk[0]:425 *C 51.060 80.240 +*N prog_clk[0]:426 *C 51.060 80.195 +*N prog_clk[0]:427 *C 50.865 77.520 +*N prog_clk[0]:428 *C 51.060 77.180 +*N prog_clk[0]:429 *C 51.060 77.180 +*N prog_clk[0]:430 *C 51.060 74.858 +*N prog_clk[0]:431 *C 51.060 74.800 +*N prog_clk[0]:432 *C 41.205 74.800 +*N prog_clk[0]:433 *C 40.940 74.800 +*N prog_clk[0]:434 *C 40.940 74.800 +*N prog_clk[0]:435 *C 40.940 74.800 +*N prog_clk[0]:436 *C 37.267 74.800 +*N prog_clk[0]:437 *C 37.260 74.743 +*N prog_clk[0]:438 *C 36.205 72.080 +*N prog_clk[0]:439 *C 36.340 72.080 +*N prog_clk[0]:440 *C 37.260 72.080 +*N prog_clk[0]:441 *C 37.260 63.920 +*N prog_clk[0]:442 *C 50.828 63.920 +*N prog_clk[0]:443 *C 50.185 63.920 +*N prog_clk[0]:444 *C 50.140 63.920 +*N prog_clk[0]:445 *C 50.133 63.920 +*N prog_clk[0]:446 *C 39.365 66.640 +*N prog_clk[0]:447 *C 39.560 66.640 +*N prog_clk[0]:448 *C 39.560 66.595 +*N prog_clk[0]:449 *C 40.248 63.920 +*N prog_clk[0]:450 *C 39.605 63.920 +*N prog_clk[0]:451 *C 39.560 63.920 +*N prog_clk[0]:452 *C 39.560 63.920 +*N prog_clk[0]:453 *C 37.727 63.920 +*N prog_clk[0]:454 *C 37.720 63.863 +*N prog_clk[0]:455 *C 37.720 61.938 +*N prog_clk[0]:456 *C 37.720 61.873 +*N prog_clk[0]:457 *C 30.625 63.920 +*N prog_clk[0]:458 *C 30.820 63.920 +*N prog_clk[0]:459 *C 30.820 63.875 +*N prog_clk[0]:460 *C 31.533 61.200 +*N prog_clk[0]:461 *C 30.865 61.200 +*N prog_clk[0]:462 *C 30.820 61.245 +*N prog_clk[0]:463 *C 30.820 61.880 +*N prog_clk[0]:464 *C 30.828 61.880 +*N prog_clk[0]:465 *C 32.660 61.880 +*N prog_clk[0]:466 *C 32.660 61.823 +*N prog_clk[0]:467 *C 40.248 55.760 +*N prog_clk[0]:468 *C 38.225 55.760 +*N prog_clk[0]:469 *C 38.180 55.715 +*N prog_clk[0]:470 *C 38.445 53.040 +*N prog_clk[0]:471 *C 38.180 53.040 +*N prog_clk[0]:472 *C 38.180 53.085 +*N prog_clk[0]:473 *C 38.180 53.720 +*N prog_clk[0]:474 *C 38.172 53.720 +*N prog_clk[0]:475 *C 32.668 53.720 +*N prog_clk[0]:476 *C 32.660 53.778 +*N prog_clk[0]:477 *C 32.200 53.720 +*N prog_clk[0]:478 *C 32.200 46.240 +*N prog_clk[0]:479 *C 32.193 46.240 +*N prog_clk[0]:480 *C 28.527 46.240 +*N prog_clk[0]:481 *C 28.520 46.183 +*N prog_clk[0]:482 *C 28.785 44.880 +*N prog_clk[0]:483 *C 28.520 44.880 +*N prog_clk[0]:484 *C 28.520 44.880 +*N prog_clk[0]:485 *C 28.513 44.880 +*N prog_clk[0]:486 *C 23.725 85.680 +*N prog_clk[0]:487 *C 23.920 85.680 +*N prog_clk[0]:488 *C 23.920 85.635 +*N prog_clk[0]:489 *C 28.785 82.960 +*N prog_clk[0]:490 *C 28.520 82.960 +*N prog_clk[0]:491 *C 28.520 82.960 +*N prog_clk[0]:492 *C 28.513 82.960 +*N prog_clk[0]:493 *C 27.140 82.960 +*N prog_clk[0]:494 *C 31.508 115.600 +*N prog_clk[0]:495 *C 30.865 115.600 +*N prog_clk[0]:496 *C 30.820 115.555 +*N prog_clk[0]:497 *C 41.113 123.760 +*N prog_clk[0]:498 *C 39.605 123.760 +*N prog_clk[0]:499 *C 39.560 123.760 +*N prog_clk[0]:500 *C 39.553 123.760 +*N prog_clk[0]:501 *C 37.727 123.760 +*N prog_clk[0]:502 *C 37.720 123.703 +*N prog_clk[0]:503 *C 37.985 121.040 +*N prog_clk[0]:504 *C 37.720 120.700 +*N prog_clk[0]:505 *C 37.720 120.700 +*N prog_clk[0]:506 *C 37.985 110.160 +*N prog_clk[0]:507 *C 37.720 110.160 +*N prog_clk[0]:508 *C 37.720 110.205 +*N prog_clk[0]:509 *C 37.720 110.840 +*N prog_clk[0]:510 *C 37.712 110.840 +*N prog_clk[0]:511 *C 30.828 110.840 +*N prog_clk[0]:512 *C 30.820 110.898 +*N prog_clk[0]:513 *C 30.360 110.840 +*N prog_clk[0]:514 *C 31.508 104.720 +*N prog_clk[0]:515 *C 30.360 104.720 +*N prog_clk[0]:516 *C 30.360 104.380 +*N prog_clk[0]:517 *C 30.360 104.380 +*N prog_clk[0]:518 *C 31.508 102.000 +*N prog_clk[0]:519 *C 30.360 102.000 +*N prog_clk[0]:520 *C 30.360 102.340 +*N prog_clk[0]:521 *C 30.360 102.340 +*N prog_clk[0]:522 *C 63.285 110.160 +*N prog_clk[0]:523 *C 63.480 110.160 +*N prog_clk[0]:524 *C 63.480 110.115 +*N prog_clk[0]:525 *C 66.468 115.600 +*N prog_clk[0]:526 *C 65.365 115.600 +*N prog_clk[0]:527 *C 65.320 115.555 +*N prog_clk[0]:528 *C 94.105 112.880 +*N prog_clk[0]:529 *C 93.840 112.880 +*N prog_clk[0]:530 *C 93.840 112.880 +*N prog_clk[0]:531 *C 93.833 112.880 +*N prog_clk[0]:532 *C 90.160 112.880 +*N prog_clk[0]:533 *C 90.425 115.600 +*N prog_clk[0]:534 *C 90.160 115.600 +*N prog_clk[0]:535 *C 90.160 115.555 +*N prog_clk[0]:536 *C 90.160 113.618 +*N prog_clk[0]:537 *C 90.160 113.553 +*N prog_clk[0]:538 *C 87.665 118.320 +*N prog_clk[0]:539 *C 87.400 118.320 +*N prog_clk[0]:540 *C 87.400 118.275 +*N prog_clk[0]:541 *C 87.400 113.618 +*N prog_clk[0]:542 *C 87.400 113.560 +*N prog_clk[0]:543 *C 82.808 113.560 +*N prog_clk[0]:544 *C 82.800 113.503 +*N prog_clk[0]:545 *C 82.605 110.160 +*N prog_clk[0]:546 *C 82.800 110.160 +*N prog_clk[0]:547 *C 82.800 110.205 +*N prog_clk[0]:548 *C 82.800 110.840 +*N prog_clk[0]:549 *C 82.793 110.840 +*N prog_clk[0]:550 *C 77.047 118.320 +*N prog_clk[0]:551 *C 76.405 118.320 +*N prog_clk[0]:552 *C 76.360 118.320 +*N prog_clk[0]:553 *C 76.353 118.320 +*N prog_clk[0]:554 *C 74.365 121.040 +*N prog_clk[0]:555 *C 74.060 121.040 +*N prog_clk[0]:556 *C 74.060 120.995 +*N prog_clk[0]:557 *C 74.060 118.378 +*N prog_clk[0]:558 *C 74.068 118.320 +*N prog_clk[0]:559 *C 75.440 118.320 +*N prog_clk[0]:560 *C 75.440 118.263 +*N prog_clk[0]:561 *C 75.440 110.898 +*N prog_clk[0]:562 *C 75.440 110.840 +*N prog_clk[0]:563 *C 65.328 110.840 +*N prog_clk[0]:564 *C 65.320 110.840 +*N prog_clk[0]:565 *C 65.585 107.440 +*N prog_clk[0]:566 *C 65.320 107.440 +*N prog_clk[0]:567 *C 65.320 107.485 +*N prog_clk[0]:568 *C 65.320 108.120 +*N prog_clk[0]:569 *C 65.312 108.120 +*N prog_clk[0]:570 *C 63.488 108.120 +*N prog_clk[0]:571 *C 63.480 108.120 +*N prog_clk[0]:572 *C 63.480 102.000 +*N prog_clk[0]:573 *C 61.905 102.000 +*N prog_clk[0]:574 *C 62.100 102.000 +*N prog_clk[0]:575 *C 62.100 102.000 +*N prog_clk[0]:576 *C 62.093 102.000 +*N prog_clk[0]:577 *C 47.608 115.600 +*N prog_clk[0]:578 *C 46.505 115.600 +*N prog_clk[0]:579 *C 46.460 115.555 +*N prog_clk[0]:580 *C 46.725 110.160 +*N prog_clk[0]:581 *C 46.460 109.820 +*N prog_clk[0]:582 *C 46.460 109.820 +*N prog_clk[0]:583 *C 46.355 104.720 +*N prog_clk[0]:584 *C 46.460 104.720 +*N prog_clk[0]:585 *C 46.460 102.058 +*N prog_clk[0]:586 *C 46.460 102.000 +*N prog_clk[0]:587 *C 41.867 102.000 +*N prog_clk[0]:588 *C 41.860 101.943 +*N prog_clk[0]:589 *C 41.665 99.280 +*N prog_clk[0]:590 *C 41.860 98.940 +*N prog_clk[0]:591 *C 41.860 98.940 +*N prog_clk[0]:592 *C 41.665 93.840 +*N prog_clk[0]:593 *C 41.860 93.840 +*N prog_clk[0]:594 *C 41.860 93.885 +*N prog_clk[0]:595 *C 41.860 94.520 +*N prog_clk[0]:596 *C 41.852 94.520 +*N prog_clk[0]:597 *C 32.925 96.560 +*N prog_clk[0]:598 *C 33.120 96.560 +*N prog_clk[0]:599 *C 33.120 96.515 +*N prog_clk[0]:600 *C 33.120 94.578 +*N prog_clk[0]:601 *C 33.120 94.520 +*N prog_clk[0]:602 *C 30.367 94.520 +*N prog_clk[0]:603 *C 30.360 94.520 +*N prog_clk[0]:604 *C 30.625 91.120 +*N prog_clk[0]:605 *C 30.360 91.120 +*N prog_clk[0]:606 *C 30.360 91.165 +*N prog_clk[0]:607 *C 30.360 91.800 +*N prog_clk[0]:608 *C 30.353 91.800 +*N prog_clk[0]:609 *C 25.565 93.840 +*N prog_clk[0]:610 *C 25.760 93.840 +*N prog_clk[0]:611 *C 25.760 93.795 +*N prog_clk[0]:612 *C 25.760 91.858 +*N prog_clk[0]:613 *C 25.768 91.800 +*N prog_clk[0]:614 *C 27.140 91.800 +*N prog_clk[0]:615 *C 27.140 91.743 +*N prog_clk[0]:616 *C 27.140 83.698 +*N prog_clk[0]:617 *C 27.140 83.633 +*N prog_clk[0]:618 *C 23.928 83.640 +*N prog_clk[0]:619 *C 23.920 83.640 +*N prog_clk[0]:620 *C 24.185 80.240 +*N prog_clk[0]:621 *C 23.920 80.580 +*N prog_clk[0]:622 *C 23.920 80.580 +*N prog_clk[0]:623 *C 26.025 72.080 +*N prog_clk[0]:624 *C 25.760 72.080 +*N prog_clk[0]:625 *C 25.760 72.080 +*N prog_clk[0]:626 *C 25.753 72.080 +*N prog_clk[0]:627 *C 23.928 72.080 +*N prog_clk[0]:628 *C 23.920 72.080 +*N prog_clk[0]:629 *C 22.785 58.480 +*N prog_clk[0]:630 *C 23.000 58.820 +*N prog_clk[0]:631 *C 23.415 58.820 +*N prog_clk[0]:632 *C 23.460 58.820 +*N prog_clk[0]:633 *C 23.920 58.820 +*N prog_clk[0]:634 *C 24.185 47.600 +*N prog_clk[0]:635 *C 23.920 47.940 +*N prog_clk[0]:636 *C 23.920 47.940 +*N prog_clk[0]:637 *C 23.920 44.938 +*N prog_clk[0]:638 *C 23.920 44.880 +*N prog_clk[0]:639 *C 21.168 44.880 +*N prog_clk[0]:640 *C 21.160 44.823 +*N prog_clk[0]:641 *C 26.025 36.720 +*N prog_clk[0]:642 *C 25.760 36.720 +*N prog_clk[0]:643 *C 25.760 36.720 +*N prog_clk[0]:644 *C 25.753 36.720 +*N prog_clk[0]:645 *C 21.168 36.720 +*N prog_clk[0]:646 *C 21.160 36.720 +*N prog_clk[0]:647 *C 21.160 29.298 +*N prog_clk[0]:648 *C 21.160 29.240 +*N prog_clk[0]:649 *C 4.440 93.840 +*N prog_clk[0]:650 *C 4.600 93.840 +*N prog_clk[0]:651 *C 4.600 93.795 +*N prog_clk[0]:652 *C 4.600 89.080 +*N prog_clk[0]:653 *C 5.060 89.080 +*N prog_clk[0]:654 *C 7.545 85.680 +*N prog_clk[0]:655 *C 7.545 85.000 +*N prog_clk[0]:656 *C 5.105 85.000 +*N prog_clk[0]:657 *C 5.060 85.000 +*N prog_clk[0]:658 *C 11.718 77.498 +*N prog_clk[0]:659 *C 11.500 77.485 +*N prog_clk[0]:660 *C 11.500 76.840 +*N prog_clk[0]:661 *C 9.245 76.840 +*N prog_clk[0]:662 *C 9.200 76.795 +*N prog_clk[0]:663 *C 12.188 74.800 +*N prog_clk[0]:664 *C 9.178 74.800 +*N prog_clk[0]:665 *C 9.200 75.140 +*N prog_clk[0]:666 *C 9.200 75.185 +*N prog_clk[0]:667 *C 9.200 74.800 +*N prog_clk[0]:668 *C 9.193 74.800 +*N prog_clk[0]:669 *C 5.067 74.800 +*N prog_clk[0]:670 *C 5.060 74.800 +*N prog_clk[0]:671 *C 7.540 69.360 +*N prog_clk[0]:672 *C 7.360 70.040 +*N prog_clk[0]:673 *C 5.105 70.040 +*N prog_clk[0]:674 *C 5.060 70.040 +*N prog_clk[0]:675 *C 7.558 63.898 +*N prog_clk[0]:676 *C 7.360 63.885 +*N prog_clk[0]:677 *C 7.360 63.240 +*N prog_clk[0]:678 *C 5.105 63.240 +*N prog_clk[0]:679 *C 5.060 63.240 +*N prog_clk[0]:680 *C 14.488 47.600 +*N prog_clk[0]:681 *C 13.845 47.600 +*N prog_clk[0]:682 *C 13.800 47.600 +*N prog_clk[0]:683 *C 16.365 55.760 +*N prog_clk[0]:684 *C 16.560 55.760 +*N prog_clk[0]:685 *C 16.560 55.760 +*N prog_clk[0]:686 *C 16.553 55.760 +*N prog_clk[0]:687 *C 11.765 58.480 +*N prog_clk[0]:688 *C 11.960 58.480 +*N prog_clk[0]:689 *C 11.960 58.435 +*N prog_clk[0]:690 *C 11.960 55.818 +*N prog_clk[0]:691 *C 11.968 55.760 +*N prog_clk[0]:692 *C 13.340 55.760 +*N prog_clk[0]:693 *C 13.340 55.703 +*N prog_clk[0]:694 *C 13.340 47.600 +*N prog_clk[0]:695 *C 13.340 42.205 +*N prog_clk[0]:696 *C 13.340 42.160 +*N prog_clk[0]:697 *C 13.605 42.160 +*N prog_clk[0]:698 *C 13.800 42.160 +*N prog_clk[0]:699 *C 13.800 42.115 +*N prog_clk[0]:700 *C 13.800 36.720 +*N prog_clk[0]:701 *C 12.685 36.720 +*N prog_clk[0]:702 *C 12.880 36.720 +*N prog_clk[0]:703 *C 12.880 36.720 +*N prog_clk[0]:704 *C 12.873 36.720 +*N prog_clk[0]:705 *C 5.067 36.720 +*N prog_clk[0]:706 *C 5.060 36.720 +*N prog_clk[0]:707 *C 5.060 29.298 +*N prog_clk[0]:708 *C 5.060 29.240 +*N prog_clk[0]:709 *C 2.308 29.240 +*N prog_clk[0]:710 *C 2.300 29.183 + +*CAP +0 prog_clk[0] 5.040281e-05 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +3 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +4 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +5 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +6 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +7 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +8 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +9 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:CLK 1e-06 +11 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +12 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +13 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +14 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +15 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +16 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +18 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +19 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +20 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +21 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +22 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +23 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +24 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +25 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +27 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +28 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +29 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +30 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +31 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +32 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +33 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +35 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +36 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +37 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:CLK 1e-06 +38 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +39 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +40 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +41 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +42 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +43 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +44 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +45 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +46 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +47 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +48 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +49 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +50 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +51 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +52 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +54 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +55 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +57 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +58 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +59 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +60 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +61 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +63 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:CLK 1e-06 +64 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +65 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +66 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +67 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +68 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +69 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +70 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +71 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +72 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +73 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +74 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +75 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +76 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +77 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +78 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +79 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +80 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +81 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +82 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +83 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +84 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +85 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +86 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +87 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +88 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +89 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +90 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +91 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +92 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +93 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +94 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +95 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +96 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +97 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +98 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +99 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +100 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +101 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:CLK 1e-06 +102 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +103 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +104 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +105 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +106 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +107 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +108 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +109 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +110 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +111 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +112 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +113 prog_clk[0]:113 7.057164e-05 +114 prog_clk[0]:114 1.626588e-05 +115 prog_clk[0]:115 7.012828e-05 +116 prog_clk[0]:116 7.012828e-05 +117 prog_clk[0]:117 3.724569e-05 +118 prog_clk[0]:118 0.0002127512 +119 prog_clk[0]:119 0.0002127512 +120 prog_clk[0]:120 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mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 1.416406e-06 +1302 prog_clk[0]:132 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.612174e-07 +1303 prog_clk[0]:125 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.051077e-05 +1304 prog_clk[0]:131 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.612174e-07 +1305 prog_clk[0]:124 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.051077e-05 +1306 prog_clk[0]:322 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.823711e-05 +1307 prog_clk[0]:321 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.823711e-05 +1308 prog_clk[0]:322 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 2.302552e-05 +1309 prog_clk[0]:360 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001163906 +1310 prog_clk[0]:358 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.608342e-06 +1311 prog_clk[0]:359 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001163906 +1312 prog_clk[0]:356 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 5.331556e-06 +1313 prog_clk[0]:357 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.608342e-06 +1314 prog_clk[0]:357 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.331556e-06 +1315 prog_clk[0]:321 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 2.302552e-05 +1316 prog_clk[0]:466 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.817686e-06 +1317 prog_clk[0]:478 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.080163e-05 +1318 prog_clk[0]:476 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.817686e-06 +1319 prog_clk[0]:477 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.080163e-05 +1320 prog_clk[0]:466 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.537603e-05 +1321 prog_clk[0]:476 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.537603e-05 +1322 prog_clk[0]:461 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.449689e-05 +1323 prog_clk[0]:460 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 1.449689e-05 +1324 prog_clk[0]:465 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.872237e-05 +1325 prog_clk[0]:465 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.902367e-05 +1326 prog_clk[0]:464 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.902367e-05 +1327 prog_clk[0]:456 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.872237e-05 +1328 prog_clk[0]:414 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.177227e-05 +1329 prog_clk[0]:415 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.177227e-05 +1330 prog_clk[0]:706 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001302315 +1331 prog_clk[0]:679 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001302315 +1332 prog_clk[0]:693 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 7.992179e-06 +1333 prog_clk[0]:692 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.955436e-06 +1334 prog_clk[0]:690 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 3.888726e-06 +1335 prog_clk[0]:691 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.955436e-06 +1336 prog_clk[0]:689 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 3.888726e-06 +1337 prog_clk[0]:694 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 7.992179e-06 +1338 prog_clk[0]:563 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.365228e-05 +1339 prog_clk[0]:569 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.244412e-05 +1340 prog_clk[0]:571 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.931635e-06 +1341 prog_clk[0]:570 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.244412e-05 +1342 prog_clk[0]:549 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.402805e-05 +1343 prog_clk[0]:562 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.402805e-05 +1344 prog_clk[0]:562 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.365228e-05 +1345 prog_clk[0]:572 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.931635e-06 +1346 prog_clk[0]:193 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 9.559841e-05 +1347 prog_clk[0]:192 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001284752 +1348 prog_clk[0]:192 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.559841e-05 +1349 prog_clk[0]:178 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001152589 +1350 prog_clk[0]:182 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001152589 +1351 prog_clk[0]:182 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001284752 +1352 prog_clk[0]:640 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.864278e-05 +1353 prog_clk[0]:647 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.72759e-06 +1354 prog_clk[0]:636 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.026386e-05 +1355 prog_clk[0]:636 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.042354e-05 +1356 prog_clk[0]:646 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.864278e-05 +1357 prog_clk[0]:646 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.72759e-06 +1358 prog_clk[0]:405 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.544112e-07 +1359 prog_clk[0]:637 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.042354e-05 +1360 prog_clk[0]:406 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.544112e-07 +1361 prog_clk[0]:633 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.026386e-05 +1362 prog_clk[0]:708 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 1.597288e-05 +1363 prog_clk[0]:648 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0002680813 +1364 prog_clk[0]:648 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 1.597288e-05 +1365 prog_clk[0]:401 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0002680813 +1366 prog_clk[0]:622 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.759682e-05 +1367 prog_clk[0]:628 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.523901e-05 +1368 prog_clk[0]:628 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.759682e-05 +1369 prog_clk[0]:633 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.523901e-05 +1370 prog_clk[0]:706 ropt_net_212:4 6.344336e-05 +1371 prog_clk[0]:679 ropt_net_212:5 6.344336e-05 +1372 prog_clk[0]:670 ropt_net_193:5 1.883915e-06 +1373 prog_clk[0]:674 ropt_net_193:5 3.836718e-05 +1374 prog_clk[0]:674 ropt_net_193:4 1.883915e-06 +1375 prog_clk[0]:671 ropt_net_193:8 5.41102e-06 +1376 prog_clk[0]:671 ropt_net_193:4 5.41102e-06 +1377 prog_clk[0]:679 ropt_net_193:4 3.836718e-05 +1378 prog_clk[0]:672 ropt_net_193:9 5.41102e-06 +1379 prog_clk[0]:672 ropt_net_193:5 5.41102e-06 + +*RES +0 prog_clk[0] prog_clk[0]:710 0.0006183035 +1 prog_clk[0]:394 prog_clk[0]:393 0.001602679 +2 prog_clk[0]:395 prog_clk[0]:394 0.0045 +3 prog_clk[0]:395 prog_clk[0]:390 0.0005558036 +4 prog_clk[0]:391 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +5 prog_clk[0]:658 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +6 prog_clk[0]:661 prog_clk[0]:660 0.002013393 +7 prog_clk[0]:662 prog_clk[0]:661 0.0045 +8 prog_clk[0]:616 prog_clk[0]:615 0.007183037 +9 prog_clk[0]:617 prog_clk[0]:616 0.00341 +10 prog_clk[0]:617 prog_clk[0]:493 0.0001053583 +11 prog_clk[0]:615 prog_clk[0]:614 0.00341 +12 prog_clk[0]:614 prog_clk[0]:613 0.000215025 +13 prog_clk[0]:614 prog_clk[0]:608 0.0005032916 +14 prog_clk[0]:348 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +15 prog_clk[0]:349 prog_clk[0]:348 0.000984375 +16 prog_clk[0]:350 prog_clk[0]:349 0.0045 +17 prog_clk[0]:351 prog_clk[0]:350 0.004158482 +18 prog_clk[0]:352 prog_clk[0]:351 0.00341 +19 prog_clk[0]:352 prog_clk[0]:347 0.0001053583 +20 prog_clk[0]:218 prog_clk[0]:217 0.00341 +21 prog_clk[0]:217 prog_clk[0]:216 0.0005741833 +22 prog_clk[0]:215 prog_clk[0]:214 0.002377232 +23 prog_clk[0]:216 prog_clk[0]:215 0.00341 +24 prog_clk[0]:466 prog_clk[0]:465 0.00341 +25 prog_clk[0]:465 prog_clk[0]:464 0.0002870917 +26 prog_clk[0]:465 prog_clk[0]:456 0.0007927333 +27 prog_clk[0]:495 prog_clk[0]:494 0.0005736607 +28 prog_clk[0]:496 prog_clk[0]:495 0.0045 +29 prog_clk[0]:494 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +30 prog_clk[0]:564 prog_clk[0]:563 0.00341 +31 prog_clk[0]:564 prog_clk[0]:527 0.004209822 +32 prog_clk[0]:563 prog_clk[0]:562 0.001584292 +33 prog_clk[0]:463 prog_clk[0]:462 0.0005669643 +34 prog_clk[0]:463 prog_clk[0]:459 0.00178125 +35 prog_clk[0]:464 prog_clk[0]:463 0.00341 +36 prog_clk[0]:194 prog_clk[0]:193 0.00341 +37 prog_clk[0]:194 prog_clk[0]:140 0.0045 +38 prog_clk[0]:193 prog_clk[0]:192 0.000647425 +39 prog_clk[0]:191 prog_clk[0]:190 0.006890625 +40 prog_clk[0]:192 prog_clk[0]:191 0.00341 +41 prog_clk[0]:192 prog_clk[0]:182 0.0008647999 +42 prog_clk[0]:189 prog_clk[0]:188 0.001642857 +43 prog_clk[0]:189 prog_clk[0]:183 0.0001807066 +44 prog_clk[0]:190 prog_clk[0]:189 0.0045 +45 prog_clk[0]:667 prog_clk[0]:666 0.0001850962 +46 prog_clk[0]:668 prog_clk[0]:667 0.00341 +47 prog_clk[0]:670 prog_clk[0]:669 0.00341 +48 prog_clk[0]:670 prog_clk[0]:657 0.009107144 +49 prog_clk[0]:669 prog_clk[0]:668 0.00064625 +50 prog_clk[0]:568 prog_clk[0]:567 0.0005669643 +51 prog_clk[0]:568 prog_clk[0]:564 0.002428572 +52 prog_clk[0]:569 prog_clk[0]:568 0.00341 +53 prog_clk[0]:571 prog_clk[0]:570 0.00341 +54 prog_clk[0]:571 prog_clk[0]:524 0.00178125 +55 prog_clk[0]:570 prog_clk[0]:569 0.0002859167 +56 prog_clk[0]:698 prog_clk[0]:697 0.0001059783 +57 prog_clk[0]:699 prog_clk[0]:698 0.0045 +58 prog_clk[0]:497 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +59 prog_clk[0]:498 prog_clk[0]:497 0.001345982 +60 prog_clk[0]:499 prog_clk[0]:498 0.0045 +61 prog_clk[0]:500 prog_clk[0]:499 0.00341 +62 prog_clk[0]:502 prog_clk[0]:501 0.00341 +63 prog_clk[0]:501 prog_clk[0]:500 0.0002859167 +64 prog_clk[0]:703 prog_clk[0]:702 0.0045 +65 prog_clk[0]:703 prog_clk[0]:700 0.0008214286 +66 prog_clk[0]:704 prog_clk[0]:703 0.00341 +67 prog_clk[0]:706 prog_clk[0]:705 0.00341 +68 prog_clk[0]:706 prog_clk[0]:679 0.02367857 +69 prog_clk[0]:705 prog_clk[0]:704 0.001222783 +70 prog_clk[0]:455 prog_clk[0]:454 0.00171875 +71 prog_clk[0]:456 prog_clk[0]:455 0.00341 +72 prog_clk[0]:456 prog_clk[0]:415 0.0001053583 +73 prog_clk[0]:454 prog_clk[0]:453 0.00341 +74 prog_clk[0]:454 prog_clk[0]:441 0.0004107143 +75 prog_clk[0]:453 prog_clk[0]:452 0.0002870917 +76 prog_clk[0]:451 prog_clk[0]:450 0.0045 +77 prog_clk[0]:451 prog_clk[0]:448 0.002388393 +78 prog_clk[0]:452 prog_clk[0]:451 0.00341 +79 prog_clk[0]:452 prog_clk[0]:445 0.001656358 +80 prog_clk[0]:619 prog_clk[0]:618 0.00341 +81 prog_clk[0]:619 prog_clk[0]:488 0.00178125 +82 prog_clk[0]:618 prog_clk[0]:617 0.0005032916 +83 prog_clk[0]:607 prog_clk[0]:606 0.0005669643 +84 prog_clk[0]:607 prog_clk[0]:603 0.002428571 +85 prog_clk[0]:608 prog_clk[0]:607 0.00341 +86 prog_clk[0]:478 prog_clk[0]:477 0.006678571 +87 prog_clk[0]:478 prog_clk[0]:410 0.0008214285 +88 prog_clk[0]:479 prog_clk[0]:478 0.00341 +89 prog_clk[0]:481 prog_clk[0]:480 0.00341 +90 prog_clk[0]:480 prog_clk[0]:479 0.0005741833 +91 prog_clk[0]:484 prog_clk[0]:483 0.0045 +92 prog_clk[0]:484 prog_clk[0]:481 0.001162947 +93 prog_clk[0]:485 prog_clk[0]:484 0.00341 +94 prog_clk[0]:640 prog_clk[0]:639 0.00341 +95 prog_clk[0]:640 prog_clk[0]:406 0.0003705357 +96 prog_clk[0]:639 prog_clk[0]:638 0.000431225 +97 prog_clk[0]:422 prog_clk[0]:421 0.0045 +98 prog_clk[0]:422 prog_clk[0]:419 0.0008214285 +99 prog_clk[0]:423 prog_clk[0]:422 0.00341 +100 prog_clk[0]:127 prog_clk[0]:126 0.0015625 +101 prog_clk[0]:128 prog_clk[0]:127 0.0045 +102 prog_clk[0]:575 prog_clk[0]:574 0.0045 +103 prog_clk[0]:575 prog_clk[0]:572 0.001232143 +104 prog_clk[0]:576 prog_clk[0]:575 0.00341 +105 prog_clk[0]:548 prog_clk[0]:547 0.0005669643 +106 prog_clk[0]:548 prog_clk[0]:544 0.002377232 +107 prog_clk[0]:549 prog_clk[0]:548 0.00341 +108 prog_clk[0]:554 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +109 prog_clk[0]:555 prog_clk[0]:554 0.0001657609 +110 prog_clk[0]:556 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prog_clk[0]:504 0.0045 +415 prog_clk[0]:505 prog_clk[0]:502 0.002680804 +416 prog_clk[0]:503 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +417 prog_clk[0]:697 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +418 prog_clk[0]:697 prog_clk[0]:696 8.967391e-05 +419 prog_clk[0]:702 prog_clk[0]:701 0.0001059783 +420 prog_clk[0]:701 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +421 prog_clk[0]:696 prog_clk[0]:695 0.0045 +422 prog_clk[0]:695 prog_clk[0]:694 0.004816964 +423 prog_clk[0]:520 prog_clk[0]:519 0.0003035715 +424 prog_clk[0]:521 prog_clk[0]:520 0.0045 +425 prog_clk[0]:521 prog_clk[0]:517 0.001821429 +426 prog_clk[0]:518 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +427 prog_clk[0]:404 prog_clk[0]:403 0.0003705357 +428 prog_clk[0]:405 prog_clk[0]:404 0.0045 +429 prog_clk[0]:402 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +430 prog_clk[0]:600 prog_clk[0]:599 0.001729911 +431 prog_clk[0]:601 prog_clk[0]:600 0.00341 +432 prog_clk[0]:601 prog_clk[0]:596 0.001368092 +433 prog_clk[0]:598 prog_clk[0]:597 0.0001059783 +434 prog_clk[0]:599 prog_clk[0]:598 0.0045 +435 prog_clk[0]:597 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +436 prog_clk[0]:612 prog_clk[0]:611 0.001729911 +437 prog_clk[0]:613 prog_clk[0]:612 0.00341 +438 prog_clk[0]:610 prog_clk[0]:609 0.0001059783 +439 prog_clk[0]:611 prog_clk[0]:610 0.0045 +440 prog_clk[0]:609 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +441 prog_clk[0]:280 prog_clk[0]:279 0.0001847826 +442 prog_clk[0]:281 prog_clk[0]:280 0.0045 +443 prog_clk[0]:281 prog_clk[0]:278 0.005109375 +444 prog_clk[0]:279 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +445 prog_clk[0]:605 prog_clk[0]:604 0.0001440218 +446 prog_clk[0]:606 prog_clk[0]:605 0.0045 +447 prog_clk[0]:604 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +448 prog_clk[0]:270 prog_clk[0]:269 0.00341 +449 prog_clk[0]:270 prog_clk[0]:264 0.005160714 +450 prog_clk[0]:269 prog_clk[0]:268 0.001150717 +451 prog_clk[0]:267 prog_clk[0]:266 0.0045 +452 prog_clk[0]:268 prog_clk[0]:267 0.00341 +453 prog_clk[0]:266 prog_clk[0]:265 0.0001440218 +454 prog_clk[0]:265 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +455 prog_clk[0]:546 prog_clk[0]:545 0.0001059783 +456 prog_clk[0]:547 prog_clk[0]:546 0.0045 +457 prog_clk[0]:545 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +458 prog_clk[0]:491 prog_clk[0]:490 0.0045 +459 prog_clk[0]:492 prog_clk[0]:491 0.00341 +460 prog_clk[0]:490 prog_clk[0]:489 0.0001440218 +461 prog_clk[0]:489 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +462 prog_clk[0]:566 prog_clk[0]:565 0.0001440218 +463 prog_clk[0]:567 prog_clk[0]:566 0.0045 +464 prog_clk[0]:565 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +465 prog_clk[0]:621 prog_clk[0]:620 0.0001847826 +466 prog_clk[0]:622 prog_clk[0]:621 0.0045 +467 prog_clk[0]:622 prog_clk[0]:619 0.002732143 +468 prog_clk[0]:620 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +469 prog_clk[0]:417 prog_clk[0]:416 0.0005736608 +470 prog_clk[0]:418 prog_clk[0]:417 0.0045 +471 prog_clk[0]:416 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +472 prog_clk[0]:681 prog_clk[0]:680 0.0005736608 +473 prog_clk[0]:682 prog_clk[0]:681 0.0045 +474 prog_clk[0]:680 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +475 prog_clk[0]:354 prog_clk[0]:353 0.0001059783 +476 prog_clk[0]:355 prog_clk[0]:354 0.0045 +477 prog_clk[0]:353 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +478 prog_clk[0]:358 prog_clk[0]:357 0.0003035715 +479 prog_clk[0]:359 prog_clk[0]:358 0.0045 +480 prog_clk[0]:359 prog_clk[0]:355 0.002691964 +481 prog_clk[0]:356 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +482 prog_clk[0]:365 prog_clk[0]:364 0.0001440218 +483 prog_clk[0]:366 prog_clk[0]:365 0.0045 +484 prog_clk[0]:366 prog_clk[0]:363 0.0005558036 +485 prog_clk[0]:364 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +486 prog_clk[0]:383 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +487 prog_clk[0]:385 prog_clk[0]:384 0.002147322 +488 prog_clk[0]:386 prog_clk[0]:385 0.0045 +489 prog_clk[0]:387 prog_clk[0]:386 0.0001634615 +490 prog_clk[0]:388 prog_clk[0]:387 0.00341 +491 prog_clk[0]:390 prog_clk[0]:389 0.00341 +492 prog_clk[0]:389 prog_clk[0]:388 0.00064625 +493 prog_clk[0]:330 prog_clk[0]:329 0.0001440217 +494 prog_clk[0]:331 prog_clk[0]:330 0.0045 +495 prog_clk[0]:329 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +496 prog_clk[0]:333 prog_clk[0]:332 0.0001847826 +497 prog_clk[0]:334 prog_clk[0]:333 0.0045 +498 prog_clk[0]:334 prog_clk[0]:331 0.002084822 +499 prog_clk[0]:332 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +500 prog_clk[0]:345 prog_clk[0]:344 0.0045 +501 prog_clk[0]:346 prog_clk[0]:345 0.00341 +502 prog_clk[0]:346 prog_clk[0]:342 0.0006485999 +503 prog_clk[0]:344 prog_clk[0]:343 0.0001440218 +504 prog_clk[0]:343 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +505 prog_clk[0]:205 prog_clk[0]:204 0.004765625 +506 prog_clk[0]:206 prog_clk[0]:205 0.00341 +507 prog_clk[0]:203 prog_clk[0]:202 0.0001059783 +508 prog_clk[0]:204 prog_clk[0]:203 0.0045 +509 prog_clk[0]:202 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +510 prog_clk[0]:142 prog_clk[0]:141 0.0001059783 +511 prog_clk[0]:143 prog_clk[0]:142 0.0045 +512 prog_clk[0]:141 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +513 prog_clk[0]:232 prog_clk[0]:231 0.001122768 +514 prog_clk[0]:233 prog_clk[0]:232 0.00341 +515 prog_clk[0]:230 prog_clk[0]:229 0.0001440218 +516 prog_clk[0]:231 prog_clk[0]:230 0.0045 +517 prog_clk[0]:229 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +518 prog_clk[0]:249 prog_clk[0]:248 0.000356025 +519 prog_clk[0]:250 prog_clk[0]:249 0.00341 +520 prog_clk[0]:250 prog_clk[0]:244 0.001277225 +521 prog_clk[0]:247 prog_clk[0]:246 0.0045 +522 prog_clk[0]:248 prog_clk[0]:247 0.00341 +523 prog_clk[0]:246 prog_clk[0]:245 0.000984375 +524 prog_clk[0]:245 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +525 prog_clk[0]:236 prog_clk[0]:235 0.0045 +526 prog_clk[0]:237 prog_clk[0]:236 0.00341 +527 prog_clk[0]:235 prog_clk[0]:234 0.0001440218 +528 prog_clk[0]:234 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +529 prog_clk[0]:530 prog_clk[0]:529 0.0045 +530 prog_clk[0]:531 prog_clk[0]:530 0.00341 +531 prog_clk[0]:529 prog_clk[0]:528 0.0001440217 +532 prog_clk[0]:528 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +533 prog_clk[0]:536 prog_clk[0]:535 0.001729911 +534 prog_clk[0]:537 prog_clk[0]:536 0.00341 +535 prog_clk[0]:537 prog_clk[0]:532 0.0001053583 +536 prog_clk[0]:534 prog_clk[0]:533 0.0001440218 +537 prog_clk[0]:535 prog_clk[0]:534 0.0045 +538 prog_clk[0]:533 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +539 prog_clk[0]:541 prog_clk[0]:540 0.004158482 +540 prog_clk[0]:542 prog_clk[0]:541 0.00341 +541 prog_clk[0]:542 prog_clk[0]:537 0.0004323999 +542 prog_clk[0]:539 prog_clk[0]:538 0.0001440218 +543 prog_clk[0]:540 prog_clk[0]:539 0.0045 +544 prog_clk[0]:538 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +545 prog_clk[0]:581 prog_clk[0]:580 0.0001847826 +546 prog_clk[0]:582 prog_clk[0]:581 0.0045 +547 prog_clk[0]:582 prog_clk[0]:579 0.005120536 +548 prog_clk[0]:580 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +549 prog_clk[0]:301 prog_clk[0]:300 0.00341 +550 prog_clk[0]:303 prog_clk[0]:302 0.00341 +551 prog_clk[0]:303 prog_clk[0]:138 0.0008647999 +552 prog_clk[0]:302 prog_clk[0]:301 0.00159565 +553 prog_clk[0]:574 prog_clk[0]:573 0.0001059783 +554 prog_clk[0]:573 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +555 prog_clk[0]:523 prog_clk[0]:522 0.0001059783 +556 prog_clk[0]:524 prog_clk[0]:523 0.0045 +557 prog_clk[0]:522 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +558 prog_clk[0]:693 prog_clk[0]:692 0.00341 +559 prog_clk[0]:692 prog_clk[0]:691 0.000215025 +560 prog_clk[0]:692 prog_clk[0]:686 0.0005032917 +561 prog_clk[0]:595 prog_clk[0]:594 0.0005669643 +562 prog_clk[0]:595 prog_clk[0]:591 0.003946429 +563 prog_clk[0]:596 prog_clk[0]:595 0.00341 +564 prog_clk[0]:153 prog_clk[0]:152 0.002337054 +565 prog_clk[0]:154 prog_clk[0]:153 0.00341 +566 prog_clk[0]:151 prog_clk[0]:150 0.0001440218 +567 prog_clk[0]:152 prog_clk[0]:151 0.0045 +568 prog_clk[0]:150 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +569 prog_clk[0]:690 prog_clk[0]:689 0.002337054 +570 prog_clk[0]:691 prog_clk[0]:690 0.00341 +571 prog_clk[0]:688 prog_clk[0]:687 0.0001059783 +572 prog_clk[0]:689 prog_clk[0]:688 0.0045 +573 prog_clk[0]:687 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +574 prog_clk[0]:685 prog_clk[0]:684 0.0045 +575 prog_clk[0]:686 prog_clk[0]:685 0.00341 +576 prog_clk[0]:684 prog_clk[0]:683 0.0001059783 +577 prog_clk[0]:683 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +578 prog_clk[0]:413 prog_clk[0]:412 0.0045 +579 prog_clk[0]:414 prog_clk[0]:413 0.00341 +580 prog_clk[0]:412 prog_clk[0]:411 0.000984375 +581 prog_clk[0]:411 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +582 prog_clk[0]:461 prog_clk[0]:460 0.0005959821 +583 prog_clk[0]:462 prog_clk[0]:461 0.0045 +584 prog_clk[0]:460 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +585 prog_clk[0]:631 prog_clk[0]:630 0.0003705357 +586 prog_clk[0]:632 prog_clk[0]:631 0.0045 +587 prog_clk[0]:629 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +588 prog_clk[0]:458 prog_clk[0]:457 0.0001059783 +589 prog_clk[0]:459 prog_clk[0]:458 0.0045 +590 prog_clk[0]:457 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +591 prog_clk[0]:450 prog_clk[0]:449 0.0005736608 +592 prog_clk[0]:449 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +593 prog_clk[0]:447 prog_clk[0]:446 0.0001059783 +594 prog_clk[0]:448 prog_clk[0]:447 0.0045 +595 prog_clk[0]:446 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +596 prog_clk[0]:438 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +597 prog_clk[0]:439 prog_clk[0]:438 0.0045 +598 prog_clk[0]:434 prog_clk[0]:433 0.0045 +599 prog_clk[0]:435 prog_clk[0]:434 0.00341 +600 prog_clk[0]:435 prog_clk[0]:431 0.001585467 +601 prog_clk[0]:433 prog_clk[0]:432 0.0001440218 +602 prog_clk[0]:432 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +603 prog_clk[0]:628 prog_clk[0]:627 0.00341 +604 prog_clk[0]:628 prog_clk[0]:622 0.007589286 +605 prog_clk[0]:627 prog_clk[0]:626 0.0002859167 +606 prog_clk[0]:625 prog_clk[0]:624 0.0045 +607 prog_clk[0]:626 prog_clk[0]:625 0.00341 +608 prog_clk[0]:624 prog_clk[0]:623 0.0001440218 +609 prog_clk[0]:623 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +610 prog_clk[0]:483 prog_clk[0]:482 0.0001440218 +611 prog_clk[0]:482 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +612 prog_clk[0]:326 prog_clk[0]:325 0.0045 +613 prog_clk[0]:327 prog_clk[0]:326 0.00341 +614 prog_clk[0]:325 prog_clk[0]:324 0.0001440218 +615 prog_clk[0]:324 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +616 prog_clk[0]:316 prog_clk[0]:315 0.00341 +617 prog_clk[0]:316 prog_clk[0]:310 0.001232143 +618 prog_clk[0]:315 prog_clk[0]:314 0.0005021166 +619 prog_clk[0]:313 prog_clk[0]:312 0.0045 +620 prog_clk[0]:314 prog_clk[0]:313 0.00341 +621 prog_clk[0]:312 prog_clk[0]:311 0.0001059783 +622 prog_clk[0]:311 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +623 prog_clk[0]:318 prog_clk[0]:317 0.0001059783 +624 prog_clk[0]:319 prog_clk[0]:318 0.0045 +625 prog_clk[0]:317 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +626 prog_clk[0]:374 prog_clk[0]:373 0.00341 +627 prog_clk[0]:373 prog_clk[0]:372 0.00043005 +628 prog_clk[0]:371 prog_clk[0]:370 0.0045 +629 prog_clk[0]:372 prog_clk[0]:371 0.00341 +630 prog_clk[0]:370 prog_clk[0]:369 0.0001440218 +631 prog_clk[0]:369 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +632 prog_clk[0]:376 prog_clk[0]:375 0.0001847826 +633 prog_clk[0]:377 prog_clk[0]:376 0.0045 +634 prog_clk[0]:377 prog_clk[0]:374 0.002073661 +635 prog_clk[0]:375 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +636 prog_clk[0]:305 prog_clk[0]:304 0.0005736608 +637 prog_clk[0]:306 prog_clk[0]:305 0.0045 +638 prog_clk[0]:304 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +639 prog_clk[0]:710 prog_clk[0]:709 0.00341 +640 prog_clk[0]:709 prog_clk[0]:708 0.000431225 +641 prog_clk[0]:637 prog_clk[0]:636 0.002680804 +642 prog_clk[0]:638 prog_clk[0]:637 0.00341 +643 prog_clk[0]:638 prog_clk[0]:485 0.0007194916 +644 prog_clk[0]:408 prog_clk[0]:407 0.0001059783 +645 prog_clk[0]:409 prog_clk[0]:408 0.0045 +646 prog_clk[0]:407 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +647 prog_clk[0]:337 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +648 prog_clk[0]:338 prog_clk[0]:337 0.0001222826 +649 prog_clk[0]:339 prog_clk[0]:338 0.0045 +650 prog_clk[0]:340 prog_clk[0]:339 0.004158482 +651 prog_clk[0]:341 prog_clk[0]:340 0.00341 +652 prog_clk[0]:341 prog_clk[0]:336 0.001369267 +653 prog_clk[0]:677 prog_clk[0]:676 0.0005758929 +654 prog_clk[0]:672 prog_clk[0]:671 0.0006071429 +655 prog_clk[0]:655 prog_clk[0]:654 0.0006071429 +656 prog_clk[0]:676 prog_clk[0]:675 0.000133446 +657 prog_clk[0]:664 prog_clk[0]:663 0.0026875 +658 prog_clk[0]:660 prog_clk[0]:659 0.0005758929 +659 prog_clk[0]:659 prog_clk[0]:658 0.0001469595 +660 prog_clk[0]:403 prog_clk[0]:402 0.0003035714 +661 prog_clk[0]:630 prog_clk[0]:629 0.0003035715 +662 prog_clk[0]:519 prog_clk[0]:518 0.001024554 +663 prog_clk[0]:515 prog_clk[0]:514 0.001024554 +664 prog_clk[0]:392 prog_clk[0]:391 0.0001368243 +665 prog_clk[0]:393 prog_clk[0]:392 0.0005758929 +666 prog_clk[0]:384 prog_clk[0]:383 0.0002111487 +667 prog_clk[0]:357 prog_clk[0]:356 0.001845982 +668 prog_clk[0]:122 prog_clk[0]:121 0.001024554 +669 prog_clk[0]:174 prog_clk[0]:173 0.001024554 +670 prog_clk[0]:652 prog_clk[0]:651 0.004209822 +671 prog_clk[0]:653 prog_clk[0]:652 0.0004107143 +672 prog_clk[0]:700 prog_clk[0]:699 0.004816964 +673 prog_clk[0]:694 prog_clk[0]:693 0.007234375 +674 prog_clk[0]:694 prog_clk[0]:682 0.0004107143 +675 prog_clk[0]:406 prog_clk[0]:405 0.00019375 +676 prog_clk[0]:633 prog_clk[0]:632 0.0004107143 +677 prog_clk[0]:633 prog_clk[0]:628 0.01183929 +678 prog_clk[0]:513 prog_clk[0]:512 0.0004107143 +679 prog_clk[0]:477 prog_clk[0]:476 0.0004107143 +680 prog_clk[0]:410 prog_clk[0]:409 0.001174107 +681 prog_clk[0]:440 prog_clk[0]:439 0.0008214285 +682 prog_clk[0]:440 prog_clk[0]:437 0.002377232 +683 prog_clk[0]:399 prog_clk[0]:398 0.0008214285 +684 prog_clk[0]:399 prog_clk[0]:396 0.004857143 +685 prog_clk[0]:441 prog_clk[0]:440 0.007285714 +686 prog_clk[0]:396 prog_clk[0]:395 0.006678571 +687 prog_clk[0]:396 prog_clk[0]:382 0.0004107143 +688 prog_clk[0]:310 prog_clk[0]:309 0.004816964 +689 prog_clk[0]:320 prog_clk[0]:319 0.0008214285 +690 prog_clk[0]:320 prog_clk[0]:316 0.002377232 +691 prog_clk[0]:321 prog_clk[0]:320 0.002428572 +692 prog_clk[0]:321 prog_clk[0]:306 0.0004107143 +693 prog_clk[0]:419 prog_clk[0]:418 0.007245536 +694 prog_clk[0]:572 prog_clk[0]:571 0.005464286 +695 prog_clk[0]:298 prog_clk[0]:297 0.001232143 +696 prog_clk[0]:298 prog_clk[0]:294 0.01426786 +697 prog_clk[0]:294 prog_clk[0]:293 0.0003705357 +698 prog_clk[0]:293 prog_clk[0]:292 0.000240625 +699 prog_clk[0]:289 prog_clk[0]:288 0.001232143 +700 prog_clk[0]:222 prog_clk[0]:221 0.0004107143 +701 prog_clk[0]:195 prog_clk[0]:194 0.0004107143 +702 prog_clk[0]:172 prog_clk[0]:171 0.0008214285 +703 prog_clk[0]:172 prog_clk[0]:169 0.004857143 +704 prog_clk[0]:493 prog_clk[0]:492 0.000215025 +705 prog_clk[0]:415 prog_clk[0]:414 0.000215025 +706 prog_clk[0]:347 prog_clk[0]:346 0.0008647999 +707 prog_clk[0]:342 prog_clk[0]:341 0.0001065333 +708 prog_clk[0]:328 prog_clk[0]:327 0.001223958 +709 prog_clk[0]:532 prog_clk[0]:531 0.0005753583 + +*END + +*D_NET ropt_net_224 0.001747148 //LENGTH 15.450 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_837:X O *L 0 *C 107.835 127.160 +*I ropt_mt_inst_871:A I *L 0.001766 *C 100.565 123.760 +*N ropt_net_224:2 *C 100.565 123.760 +*N ropt_net_224:3 *C 100.740 123.760 +*N ropt_net_224:4 *C 100.740 123.805 +*N ropt_net_224:5 *C 100.740 128.815 +*N ropt_net_224:6 *C 100.785 128.860 +*N ropt_net_224:7 *C 104.375 128.860 +*N ropt_net_224:8 *C 104.420 128.815 +*N ropt_net_224:9 *C 104.420 127.205 +*N ropt_net_224:10 *C 104.465 127.160 +*N ropt_net_224:11 *C 107.797 127.160 + +*CAP +0 ropt_mt_inst_837:X 1e-06 +1 ropt_mt_inst_871:A 1e-06 +2 ropt_net_224:2 4.980303e-05 +3 ropt_net_224:3 5.411664e-05 +4 ropt_net_224:4 0.0003 +5 ropt_net_224:5 0.0003 +6 ropt_net_224:6 0.0002136681 +7 ropt_net_224:7 0.0002136681 +8 ropt_net_224:8 8.589606e-05 +9 ropt_net_224:9 8.589606e-05 +10 ropt_net_224:10 0.0002210501 +11 ropt_net_224:11 0.0002210501 + +*RES +0 ropt_mt_inst_837:X ropt_net_224:11 0.152 +1 ropt_net_224:2 ropt_mt_inst_871:A 0.152 +2 ropt_net_224:3 ropt_net_224:2 9.51087e-05 +3 ropt_net_224:4 ropt_net_224:3 0.0045 +4 ropt_net_224:6 ropt_net_224:5 0.0045 +5 ropt_net_224:5 ropt_net_224:4 0.004473215 +6 ropt_net_224:7 ropt_net_224:6 0.003205357 +7 ropt_net_224:8 ropt_net_224:7 0.0045 +8 ropt_net_224:10 ropt_net_224:9 0.0045 +9 ropt_net_224:9 ropt_net_224:8 0.0014375 +10 ropt_net_224:11 ropt_net_224:10 0.002975447 + +*END + +*D_NET chanx_right_out[14] 0.0008406746 //LENGTH 5.160 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_863:X O *L 0 *C 135.700 47.260 +*P chanx_right_out[14] O *L 0.7423 *C 140.375 47.600 +*N chanx_right_out[14]:2 *C 135.708 47.600 +*N chanx_right_out[14]:3 *C 135.700 47.600 +*N chanx_right_out[14]:4 *C 135.700 47.260 +*N chanx_right_out[14]:5 *C 135.700 47.260 + +*CAP +0 ropt_mt_inst_863:X 1e-06 +1 chanx_right_out[14] 0.0003428202 +2 chanx_right_out[14]:2 0.0003428202 +3 chanx_right_out[14]:3 6.327641e-05 +4 chanx_right_out[14]:4 5.879126e-05 +5 chanx_right_out[14]:5 3.196653e-05 + +*RES +0 ropt_mt_inst_863:X chanx_right_out[14]:5 0.152 +1 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +2 chanx_right_out[14]:2 chanx_right_out[14] 0.0007312417 +3 chanx_right_out[14]:5 chanx_right_out[14]:4 0.0045 +4 chanx_right_out[14]:4 chanx_right_out[14]:3 0.0001634615 + +*END + +*D_NET ropt_net_218 0.001537118 //LENGTH 10.085 LUMPCC 0.0004135854 DR + +*CONN +*I ropt_mt_inst_841:X O *L 0 *C 85.295 6.120 +*I ropt_mt_inst_861:A I *L 0.001766 *C 76.820 6.800 +*N ropt_net_218:2 *C 76.858 6.800 +*N ropt_net_218:3 *C 78.155 6.800 +*N ropt_net_218:4 *C 78.200 6.755 +*N ropt_net_218:5 *C 78.200 6.165 +*N ropt_net_218:6 *C 78.245 6.120 +*N ropt_net_218:7 *C 85.258 6.120 + +*CAP +0 ropt_mt_inst_841:X 1e-06 +1 ropt_mt_inst_861:A 1e-06 +2 ropt_net_218:2 0.0001253145 +3 ropt_net_218:3 0.0001253145 +4 ropt_net_218:4 5.499932e-05 +5 ropt_net_218:5 5.499932e-05 +6 ropt_net_218:6 0.0003804524 +7 ropt_net_218:7 0.0003804524 +8 ropt_net_218:7 chany_bottom_out[0]:4 8.08183e-05 +9 ropt_net_218:6 chany_bottom_out[0]:3 8.08183e-05 +10 ropt_net_218:7 ropt_net_200:3 9.026083e-05 +11 ropt_net_218:7 ropt_net_200:7 2.015182e-05 +12 ropt_net_218:6 ropt_net_200:4 9.026083e-05 +13 ropt_net_218:6 ropt_net_200:6 2.015182e-05 +14 ropt_net_218:5 ropt_net_200:6 1.426915e-05 +15 ropt_net_218:5 ropt_net_200:8 1.292593e-06 +16 ropt_net_218:4 ropt_net_200:5 1.426915e-05 +17 ropt_net_218:4 ropt_net_200:7 1.292593e-06 + +*RES +0 ropt_mt_inst_841:X ropt_net_218:7 0.152 +1 ropt_net_218:7 ropt_net_218:6 0.006261161 +2 ropt_net_218:6 ropt_net_218:5 0.0045 +3 ropt_net_218:5 ropt_net_218:4 0.0005267857 +4 ropt_net_218:3 ropt_net_218:2 0.001158482 +5 ropt_net_218:4 ropt_net_218:3 0.0045 +6 ropt_net_218:2 ropt_mt_inst_861:A 0.152 + +*END + +*D_NET chany_bottom_out[17] 0.001157168 //LENGTH 9.215 LUMPCC 0.0001363422 DR + +*CONN +*I ropt_mt_inst_885:X O *L 0 *C 58.880 8.840 +*P chany_bottom_out[17] O *L 0.7423 *C 58.880 1.290 +*N chany_bottom_out[17]:2 *C 58.880 7.480 +*N chany_bottom_out[17]:3 *C 59.340 7.480 +*N chany_bottom_out[17]:4 *C 59.340 8.795 +*N chany_bottom_out[17]:5 *C 59.295 8.840 +*N chany_bottom_out[17]:6 *C 58.918 8.840 + +*CAP +0 ropt_mt_inst_885:X 1e-06 +1 chany_bottom_out[17] 0.0003264893 +2 chany_bottom_out[17]:2 0.0003583221 +3 chany_bottom_out[17]:3 0.0001314762 +4 chany_bottom_out[17]:4 9.96434e-05 +5 chany_bottom_out[17]:5 5.194747e-05 +6 chany_bottom_out[17]:6 5.194747e-05 +7 chany_bottom_out[17] ropt_net_230:4 6.817111e-05 +8 chany_bottom_out[17]:2 ropt_net_230:5 6.817111e-05 + +*RES +0 ropt_mt_inst_885:X chany_bottom_out[17]:6 0.152 +1 chany_bottom_out[17]:6 chany_bottom_out[17]:5 0.0003370536 +2 chany_bottom_out[17]:5 chany_bottom_out[17]:4 0.0045 +3 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.001174107 +4 chany_bottom_out[17]:2 chany_bottom_out[17] 0.005526786 +5 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0004107143 + +*END + +*D_NET chany_top_in[8] 0.01910838 //LENGTH 153.350 LUMPCC 0.003219549 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 72.220 129.270 +*I mux_right_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.315 58.820 +*I mux_left_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.050 55.420 +*I mux_bottom_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 69.000 34.340 +*I FTB_5__4:A I *L 0.001776 *C 51.520 6.800 +*N chany_top_in[8]:5 *C 51.520 6.800 +*N chany_top_in[8]:6 *C 51.520 6.460 +*N chany_top_in[8]:7 *C 55.660 6.460 +*N chany_top_in[8]:8 *C 55.660 6.120 +*N chany_top_in[8]:9 *C 68.495 6.120 +*N chany_top_in[8]:10 *C 68.540 6.165 +*N chany_top_in[8]:11 *C 68.963 34.340 +*N chany_top_in[8]:12 *C 68.585 34.340 +*N chany_top_in[8]:13 *C 68.540 34.340 +*N chany_top_in[8]:14 *C 68.540 40.075 +*N chany_top_in[8]:15 *C 68.585 40.120 +*N chany_top_in[8]:16 *C 71.715 40.120 +*N chany_top_in[8]:17 *C 71.760 40.165 +*N chany_top_in[8]:18 *C 71.760 55.420 +*N chany_top_in[8]:19 *C 72.050 55.420 +*N chany_top_in[8]:20 *C 72.220 55.420 +*N chany_top_in[8]:21 *C 72.220 55.465 +*N chany_top_in[8]:22 *C 73.278 58.820 +*N chany_top_in[8]:23 *C 72.265 58.820 +*N chany_top_in[8]:24 *C 72.220 58.820 +*N chany_top_in[8]:25 *C 72.220 61.540 +*N chany_top_in[8]:26 *C 72.680 61.540 +*N chany_top_in[8]:27 *C 72.680 63.920 +*N chany_top_in[8]:28 *C 72.220 63.920 +*N chany_top_in[8]:29 *C 72.220 86.020 +*N chany_top_in[8]:30 *C 72.680 86.020 +*N chany_top_in[8]:31 *C 72.680 88.060 +*N chany_top_in[8]:32 *C 72.220 88.060 +*N chany_top_in[8]:33 *C 72.220 105.400 +*N chany_top_in[8]:34 *C 71.760 105.400 +*N chany_top_in[8]:35 *C 71.760 127.160 +*N chany_top_in[8]:36 *C 72.220 127.160 + +*CAP +0 chany_top_in[8] 0.0001038957 +1 mux_right_track_16\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_17\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_17\/mux_l1_in_0_:A1 1e-06 +4 FTB_5__4:A 1e-06 +5 chany_top_in[8]:5 5.871068e-05 +6 chany_top_in[8]:6 0.0002983098 +7 chany_top_in[8]:7 0.0002952058 +8 chany_top_in[8]:8 0.0009011579 +9 chany_top_in[8]:9 0.0008756281 +10 chany_top_in[8]:10 0.00135389 +11 chany_top_in[8]:11 6.410359e-05 +12 chany_top_in[8]:12 6.410359e-05 +13 chany_top_in[8]:13 0.001650134 +14 chany_top_in[8]:14 0.0002621004 +15 chany_top_in[8]:15 0.0002344683 +16 chany_top_in[8]:16 0.0002344683 +17 chany_top_in[8]:17 0.0009522885 +18 chany_top_in[8]:18 0.000986554 +19 chany_top_in[8]:19 5.070445e-05 +20 chany_top_in[8]:20 5.628598e-05 +21 chany_top_in[8]:21 0.0002408855 +22 chany_top_in[8]:22 9.008079e-05 +23 chany_top_in[8]:23 9.008079e-05 +24 chany_top_in[8]:24 0.000398288 +25 chany_top_in[8]:25 0.0001896952 +26 chany_top_in[8]:26 0.0002007182 +27 chany_top_in[8]:27 0.0002010279 +28 chany_top_in[8]:28 0.001179525 +29 chany_top_in[8]:29 0.001179685 +30 chany_top_in[8]:30 0.0001288075 +31 chany_top_in[8]:31 0.0001300382 +32 chany_top_in[8]:32 0.0006883033 +33 chany_top_in[8]:33 0.0006879715 +34 chany_top_in[8]:34 0.0009540934 +35 chany_top_in[8]:35 0.0009506941 +36 chany_top_in[8]:36 0.0001329263 +37 chany_top_in[8] chany_top_in[10] 2.931139e-05 +38 chany_top_in[8]:34 chany_top_in[10]:35 1.286662e-05 +39 chany_top_in[8]:34 chany_top_in[10]:37 9.836131e-06 +40 chany_top_in[8]:34 chany_top_in[10]:33 2.797803e-05 +41 chany_top_in[8]:34 chany_top_in[10]:39 1.421636e-05 +42 chany_top_in[8]:34 chany_top_in[10]:31 4.284038e-05 +43 chany_top_in[8]:33 chany_top_in[10]:32 0.0001922828 +44 chany_top_in[8]:35 chany_top_in[10] 1.421636e-05 +45 chany_top_in[8]:35 chany_top_in[10]:36 1.286662e-05 +46 chany_top_in[8]:35 chany_top_in[10]:34 2.797803e-05 +47 chany_top_in[8]:35 chany_top_in[10]:32 4.284038e-05 +48 chany_top_in[8]:35 chany_top_in[10]:38 9.836131e-06 +49 chany_top_in[8]:36 chany_top_in[10]:39 2.931139e-05 +50 chany_top_in[8]:28 chany_top_in[10]:26 3.406496e-05 +51 chany_top_in[8]:28 chany_top_in[10]:29 1.449032e-05 +52 chany_top_in[8]:28 chany_top_in[10]:31 6.635222e-05 +53 chany_top_in[8]:29 chany_top_in[10]:29 3.406496e-05 +54 chany_top_in[8]:29 chany_top_in[10]:30 1.449032e-05 +55 chany_top_in[8]:29 chany_top_in[10]:32 6.635222e-05 +56 chany_top_in[8]:30 chany_top_in[10]:31 5.428793e-05 +57 chany_top_in[8]:32 chany_top_in[10]:31 0.0001922828 +58 chany_top_in[8]:31 chany_top_in[10]:32 5.428793e-05 +59 chany_top_in[8]:34 chany_bottom_in[12]:14 0.0003412662 +60 chany_top_in[8]:34 chany_bottom_in[12]:10 1.269591e-06 +61 chany_top_in[8]:33 chany_bottom_in[12]:14 8.082739e-05 +62 chany_top_in[8]:33 chany_bottom_in[12]:11 8.979392e-05 +63 chany_top_in[8]:35 chany_bottom_in[12]:9 1.269591e-06 +64 chany_top_in[8]:35 chany_bottom_in[12]:11 0.0003412662 +65 chany_top_in[8]:28 chany_bottom_in[12]:15 3.158874e-05 +66 chany_top_in[8]:29 chany_bottom_in[12]:14 3.158874e-05 +67 chany_top_in[8]:30 chany_bottom_in[12]:15 2.311086e-06 +68 chany_top_in[8]:32 chany_bottom_in[12]:14 8.979392e-05 +69 chany_top_in[8]:32 chany_bottom_in[12]:15 8.082739e-05 +70 chany_top_in[8]:31 chany_bottom_in[12]:14 2.311086e-06 +71 chany_top_in[8]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001296681 +72 chany_top_in[8]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001296681 +73 chany_top_in[8]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.77838e-05 +74 chany_top_in[8]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001365324 +75 chany_top_in[8]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.77838e-05 +76 chany_top_in[8]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001365324 +77 chany_top_in[8]:34 ropt_net_221:6 5.493501e-05 +78 chany_top_in[8]:35 ropt_net_221:5 5.493501e-05 +79 chany_top_in[8]:9 ropt_net_230:6 8.168253e-05 +80 chany_top_in[8]:8 ropt_net_230:7 8.168253e-05 +81 chany_top_in[8]:6 ropt_net_192:7 6.454397e-05 +82 chany_top_in[8]:6 ropt_net_192:3 2.904479e-05 +83 chany_top_in[8]:7 ropt_net_192:6 6.454397e-05 +84 chany_top_in[8]:7 ropt_net_192:2 2.904479e-05 + +*RES +0 chany_top_in[8] chany_top_in[8]:36 0.001883929 +1 chany_top_in[8]:15 chany_top_in[8]:14 0.0045 +2 chany_top_in[8]:14 chany_top_in[8]:13 0.005120536 +3 chany_top_in[8]:16 chany_top_in[8]:15 0.002794643 +4 chany_top_in[8]:17 chany_top_in[8]:16 0.0045 +5 chany_top_in[8]:12 chany_top_in[8]:11 0.0003370536 +6 chany_top_in[8]:13 chany_top_in[8]:12 0.0045 +7 chany_top_in[8]:13 chany_top_in[8]:10 0.02515625 +8 chany_top_in[8]:11 mux_bottom_track_17\/mux_l1_in_0_:A1 0.152 +9 chany_top_in[8]:9 chany_top_in[8]:8 0.01145982 +10 chany_top_in[8]:10 chany_top_in[8]:9 0.0045 +11 chany_top_in[8]:5 FTB_5__4:A 0.152 +12 chany_top_in[8]:23 chany_top_in[8]:22 0.0009040179 +13 chany_top_in[8]:24 chany_top_in[8]:23 0.0045 +14 chany_top_in[8]:24 chany_top_in[8]:21 0.002995536 +15 chany_top_in[8]:22 mux_right_track_16\/mux_l1_in_0_:A0 0.152 +16 chany_top_in[8]:20 chany_top_in[8]:19 9.239131e-05 +17 chany_top_in[8]:21 chany_top_in[8]:20 0.0045 +18 chany_top_in[8]:21 chany_top_in[8]:18 0.0004107143 +19 chany_top_in[8]:19 mux_left_track_17\/mux_l1_in_0_:A0 0.152 +20 chany_top_in[8]:6 chany_top_in[8]:5 0.0003035715 +21 chany_top_in[8]:7 chany_top_in[8]:6 0.003696429 +22 chany_top_in[8]:8 chany_top_in[8]:7 0.0003035715 +23 chany_top_in[8]:18 chany_top_in[8]:17 0.01362054 +24 chany_top_in[8]:34 chany_top_in[8]:33 0.0004107143 +25 chany_top_in[8]:33 chany_top_in[8]:32 0.01548214 +26 chany_top_in[8]:35 chany_top_in[8]:34 0.01942857 +27 chany_top_in[8]:36 chany_top_in[8]:35 0.0004107143 +28 chany_top_in[8]:25 chany_top_in[8]:24 0.002428572 +29 chany_top_in[8]:26 chany_top_in[8]:25 0.0004107143 +30 chany_top_in[8]:28 chany_top_in[8]:27 0.0004107143 +31 chany_top_in[8]:29 chany_top_in[8]:28 0.01973214 +32 chany_top_in[8]:27 chany_top_in[8]:26 0.002125 +33 chany_top_in[8]:30 chany_top_in[8]:29 0.0004107143 +34 chany_top_in[8]:32 chany_top_in[8]:31 0.0004107143 +35 chany_top_in[8]:31 chany_top_in[8]:30 0.001821429 + +*END + +*D_NET chanx_left_in[13] 0.0432207 //LENGTH 252.470 LUMPCC 0.01949984 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 93.840 +*I mux_bottom_track_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 54.840 23.460 +*I mux_top_track_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 56.870 91.460 +*I BUFT_P_126:A I *L 0.001776 *C 131.560 55.760 +*I mux_right_track_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 116.940 88.740 +*N chanx_left_in[13]:5 *C 116.903 88.740 +*N chanx_left_in[13]:6 *C 116.425 88.740 +*N chanx_left_in[13]:7 *C 116.350 88.710 +*N chanx_left_in[13]:8 *C 116.335 88.400 +*N chanx_left_in[13]:9 *C 131.597 55.760 +*N chanx_left_in[13]:10 *C 131.975 55.760 +*N chanx_left_in[13]:11 *C 132.020 55.760 +*N chanx_left_in[13]:12 *C 132.013 55.760 +*N chanx_left_in[13]:13 *C 115.928 55.760 +*N chanx_left_in[13]:14 *C 115.920 55.818 +*N chanx_left_in[13]:15 *C 115.920 88.400 +*N chanx_left_in[13]:16 *C 115.913 88.400 +*N chanx_left_in[13]:17 *C 106.580 88.400 +*N chanx_left_in[13]:18 *C 56.870 91.460 +*N chanx_left_in[13]:19 *C 56.580 91.460 +*N chanx_left_in[13]:20 *C 56.580 91.415 +*N chanx_left_in[13]:21 *C 56.580 88.458 +*N chanx_left_in[13]:22 *C 56.580 88.400 +*N chanx_left_in[13]:23 *C 54.840 23.460 +*N chanx_left_in[13]:24 *C 54.740 23.120 +*N chanx_left_in[13]:25 *C 51.565 23.120 +*N chanx_left_in[13]:26 *C 51.520 23.120 +*N chanx_left_in[13]:27 *C 51.513 23.120 +*N chanx_left_in[13]:28 *C 46.020 23.120 +*N chanx_left_in[13]:29 *C 46.000 23.128 +*N chanx_left_in[13]:30 *C 46.000 72.955 +*N chanx_left_in[13]:31 *C 46.000 88.392 +*N chanx_left_in[13]:32 *C 46.000 88.400 +*N chanx_left_in[13]:33 *C 11.980 88.400 +*N chanx_left_in[13]:34 *C 11.960 88.407 +*N chanx_left_in[13]:35 *C 11.960 93.833 +*N chanx_left_in[13]:36 *C 11.940 93.840 + +*CAP +0 chanx_left_in[13] 0.0004986955 +1 mux_bottom_track_3\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_2\/mux_l2_in_2_:A0 1e-06 +3 BUFT_P_126:A 1e-06 +4 mux_right_track_2\/mux_l2_in_3_:A1 1e-06 +5 chanx_left_in[13]:5 6.247188e-05 +6 chanx_left_in[13]:6 6.247188e-05 +7 chanx_left_in[13]:7 4.239814e-05 +8 chanx_left_in[13]:8 7.974262e-05 +9 chanx_left_in[13]:9 4.022631e-05 +10 chanx_left_in[13]:10 4.022631e-05 +11 chanx_left_in[13]:11 3.512455e-05 +12 chanx_left_in[13]:12 0.0002746096 +13 chanx_left_in[13]:13 0.0002746096 +14 chanx_left_in[13]:14 0.00163985 +15 chanx_left_in[13]:15 0.001677194 +16 chanx_left_in[13]:16 0.0003690738 +17 chanx_left_in[13]:17 0.002939119 +18 chanx_left_in[13]:18 5.996216e-05 +19 chanx_left_in[13]:19 6.495802e-05 +20 chanx_left_in[13]:20 0.0002290672 +21 chanx_left_in[13]:21 0.0002290672 +22 chanx_left_in[13]:22 0.00347142 +23 chanx_left_in[13]:23 5.555426e-05 +24 chanx_left_in[13]:24 0.000220138 +25 chanx_left_in[13]:25 0.0001927943 +26 chanx_left_in[13]:26 3.354608e-05 +27 chanx_left_in[13]:27 0.0002578336 +28 chanx_left_in[13]:28 0.0002578336 +29 chanx_left_in[13]:29 0.002222677 +30 chanx_left_in[13]:30 0.002978074 +31 chanx_left_in[13]:31 0.0007553968 +32 chanx_left_in[13]:32 0.00225247 +33 chanx_left_in[13]:33 0.001351095 +34 chanx_left_in[13]:34 0.0002752297 +35 chanx_left_in[13]:35 0.0002752297 +36 chanx_left_in[13]:36 0.0004986955 +37 chanx_left_in[13]:22 chany_top_in[18]:33 0.0001023476 +38 chanx_left_in[13]:22 chany_top_in[18]:34 0.0005558341 +39 chanx_left_in[13]:17 chany_top_in[18]:8 0.0005558341 +40 chanx_left_in[13]:17 chany_top_in[18]:34 0.0001023476 +41 chanx_left_in[13]:32 chanx_right_in[2]:21 1.956339e-07 +42 chanx_left_in[13]:22 chanx_right_in[2]:22 1.956339e-07 +43 chanx_left_in[13]:22 chanx_right_in[2]:25 1.78776e-07 +44 chanx_left_in[13]:13 chanx_right_in[2]:47 0.0009387748 +45 chanx_left_in[13]:12 chanx_right_in[2]:48 0.0009387748 +46 chanx_left_in[13]:17 chanx_right_in[2]:26 1.78776e-07 +47 chanx_left_in[13]:31 chany_bottom_in[16]:15 0.0004365791 +48 chanx_left_in[13]:30 chany_bottom_in[16]:16 0.0004365791 +49 chanx_left_in[13]:32 chanx_left_in[5]:35 0.0010527 +50 chanx_left_in[13]:33 chanx_left_in[5]:36 0.0010527 +51 chanx_left_in[13] chanx_left_in[14]:31 2.319499e-05 +52 chanx_left_in[13] chanx_left_in[14]:35 0.0003978043 +53 chanx_left_in[13]:32 chanx_left_in[14]:30 0.0001286687 +54 chanx_left_in[13]:33 chanx_left_in[14]:31 0.0001286687 +55 chanx_left_in[13]:34 chanx_left_in[14]:32 2.565019e-05 +56 chanx_left_in[13]:36 chanx_left_in[14]:30 2.319499e-05 +57 chanx_left_in[13]:36 chanx_left_in[14]:34 0.0003978043 +58 chanx_left_in[13]:35 chanx_left_in[14]:33 2.565019e-05 +59 chanx_left_in[13]:13 chanx_right_in[0]:11 0.0002911013 +60 chanx_left_in[13]:12 chanx_right_in[0]:12 0.0002911013 +61 chanx_left_in[13]:31 chany_bottom_in[15]:9 4.16058e-05 +62 chanx_left_in[13]:31 chany_bottom_in[15]:18 5.476272e-05 +63 chanx_left_in[13]:29 chany_bottom_in[15]:20 0.0005376984 +64 chanx_left_in[13]:29 chany_bottom_in[15]:19 0.0003508893 +65 chanx_left_in[13]:30 chany_bottom_in[15]:18 0.0003924951 +66 chanx_left_in[13]:30 chany_bottom_in[15]:19 0.0005924611 +67 chanx_left_in[13]:28 bottom_left_grid_pin_35_[0]:12 0.0003185006 +68 chanx_left_in[13]:27 bottom_left_grid_pin_35_[0]:11 0.0003185006 +69 chanx_left_in[13]:22 mux_tree_tapbuf_size16_1_sram[0]:19 0.001519533 +70 chanx_left_in[13]:16 mux_tree_tapbuf_size16_1_sram[0]:20 0.0005178457 +71 chanx_left_in[13]:17 mux_tree_tapbuf_size16_1_sram[0]:20 0.001519533 +72 chanx_left_in[13]:17 mux_tree_tapbuf_size16_1_sram[0]:19 0.0005178457 +73 chanx_left_in[13]:32 mux_tree_tapbuf_size16_3_sram[1]:38 0.0002804286 +74 chanx_left_in[13]:32 mux_tree_tapbuf_size16_3_sram[1]:39 0.00076501 +75 chanx_left_in[13]:33 mux_tree_tapbuf_size16_3_sram[1]:30 0.0002804286 +76 chanx_left_in[13]:33 mux_tree_tapbuf_size16_3_sram[1]:38 0.00076501 +77 chanx_left_in[13]:22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0007278301 +78 chanx_left_in[13]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001187706 +79 chanx_left_in[13]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0007278301 +80 chanx_left_in[13]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001187706 +81 chanx_left_in[13]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001543679 +82 chanx_left_in[13]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001543679 +83 chanx_left_in[13]:15 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.741499e-05 +84 chanx_left_in[13]:14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.741499e-05 +85 chanx_left_in[13]:29 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0003622321 +86 chanx_left_in[13]:30 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0003622321 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:36 0.0016779 +1 chanx_left_in[13]:32 chanx_left_in[13]:31 0.00341 +2 chanx_left_in[13]:32 chanx_left_in[13]:22 0.001657533 +3 chanx_left_in[13]:31 chanx_left_in[13]:30 0.002418542 +4 chanx_left_in[13]:28 chanx_left_in[13]:27 0.0008604917 +5 chanx_left_in[13]:29 chanx_left_in[13]:28 0.00341 +6 chanx_left_in[13]:26 chanx_left_in[13]:25 0.0045 +7 chanx_left_in[13]:27 chanx_left_in[13]:26 0.00341 +8 chanx_left_in[13]:25 chanx_left_in[13]:24 0.002834822 +9 chanx_left_in[13]:23 mux_bottom_track_3\/mux_l2_in_3_:A1 0.152 +10 chanx_left_in[13]:5 mux_right_track_2\/mux_l2_in_3_:A1 0.152 +11 chanx_left_in[13]:6 chanx_left_in[13]:5 0.0004263393 +12 chanx_left_in[13]:7 chanx_left_in[13]:6 0.0045 +13 chanx_left_in[13]:21 chanx_left_in[13]:20 0.002640625 +14 chanx_left_in[13]:22 chanx_left_in[13]:21 0.00341 +15 chanx_left_in[13]:22 chanx_left_in[13]:17 0.007833333 +16 chanx_left_in[13]:19 chanx_left_in[13]:18 0.0001576087 +17 chanx_left_in[13]:20 chanx_left_in[13]:19 0.0045 +18 chanx_left_in[13]:18 mux_top_track_2\/mux_l2_in_2_:A0 0.152 +19 chanx_left_in[13]:33 chanx_left_in[13]:32 0.0053298 +20 chanx_left_in[13]:34 chanx_left_in[13]:33 0.00341 +21 chanx_left_in[13]:36 chanx_left_in[13]:35 0.00341 +22 chanx_left_in[13]:35 chanx_left_in[13]:34 0.0008499167 +23 chanx_left_in[13]:15 chanx_left_in[13]:14 0.02909152 +24 chanx_left_in[13]:15 chanx_left_in[13]:8 0.0003705357 +25 chanx_left_in[13]:16 chanx_left_in[13]:15 0.00341 +26 chanx_left_in[13]:14 chanx_left_in[13]:13 0.00341 +27 chanx_left_in[13]:13 chanx_left_in[13]:12 0.002519983 +28 chanx_left_in[13]:11 chanx_left_in[13]:10 0.0045 +29 chanx_left_in[13]:12 chanx_left_in[13]:11 0.00341 +30 chanx_left_in[13]:10 chanx_left_in[13]:9 0.0003370536 +31 chanx_left_in[13]:9 BUFT_P_126:A 0.152 +32 chanx_left_in[13]:24 chanx_left_in[13]:23 0.0003035715 +33 chanx_left_in[13]:8 chanx_left_in[13]:7 0.00019375 +34 chanx_left_in[13]:17 chanx_left_in[13]:16 0.001462092 +35 chanx_left_in[13]:30 chanx_left_in[13]:29 0.007806308 + +*END + +*D_NET top_left_grid_pin_35_[0] 0.008341202 //LENGTH 63.760 LUMPCC 0.001585477 DR + +*CONN +*P top_left_grid_pin_35_[0] I *L 0.29796 *C 32.660 129.270 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 39.850 126.140 +*I mux_top_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.740 107.100 +*I mux_top_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.080 90.780 +*N top_left_grid_pin_35_[0]:4 *C 51.980 90.780 +*N top_left_grid_pin_35_[0]:5 *C 51.980 90.825 +*N top_left_grid_pin_35_[0]:6 *C 54.740 107.100 +*N top_left_grid_pin_35_[0]:7 *C 54.740 106.760 +*N top_left_grid_pin_35_[0]:8 *C 52.025 106.760 +*N top_left_grid_pin_35_[0]:9 *C 51.980 106.760 +*N top_left_grid_pin_35_[0]:10 *C 51.980 110.782 +*N top_left_grid_pin_35_[0]:11 *C 51.973 110.840 +*N top_left_grid_pin_35_[0]:12 *C 40.488 110.840 +*N top_left_grid_pin_35_[0]:13 *C 40.480 110.898 +*N top_left_grid_pin_35_[0]:14 *C 39.888 126.140 +*N top_left_grid_pin_35_[0]:15 *C 40.435 126.140 +*N top_left_grid_pin_35_[0]:16 *C 40.480 126.140 +*N top_left_grid_pin_35_[0]:17 *C 40.480 128.475 +*N top_left_grid_pin_35_[0]:18 *C 40.435 128.520 +*N top_left_grid_pin_35_[0]:19 *C 32.705 128.520 +*N top_left_grid_pin_35_[0]:20 *C 32.660 128.565 + +*CAP +0 top_left_grid_pin_35_[0] 5.171148e-05 +1 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_2\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_16\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_35_[0]:4 3.376078e-05 +5 top_left_grid_pin_35_[0]:5 0.0006604363 +6 top_left_grid_pin_35_[0]:6 5.796225e-05 +7 top_left_grid_pin_35_[0]:7 0.0002670628 +8 top_left_grid_pin_35_[0]:8 0.0002385848 +9 top_left_grid_pin_35_[0]:9 0.0008867888 +10 top_left_grid_pin_35_[0]:10 0.0001922838 +11 top_left_grid_pin_35_[0]:11 0.0008283687 +12 top_left_grid_pin_35_[0]:12 0.0008283687 +13 top_left_grid_pin_35_[0]:13 0.0006535648 +14 top_left_grid_pin_35_[0]:14 6.762325e-05 +15 top_left_grid_pin_35_[0]:15 6.762325e-05 +16 top_left_grid_pin_35_[0]:16 0.0007965883 +17 top_left_grid_pin_35_[0]:17 0.0001156855 +18 top_left_grid_pin_35_[0]:18 0.0004772993 +19 top_left_grid_pin_35_[0]:19 0.0004772993 +20 top_left_grid_pin_35_[0]:20 5.171148e-05 +21 top_left_grid_pin_35_[0]:9 chany_bottom_in[6]:16 0.0004115157 +22 top_left_grid_pin_35_[0]:9 chany_bottom_in[6]:19 0.0001112172 +23 top_left_grid_pin_35_[0]:10 chany_bottom_in[6]:16 0.0001112172 +24 top_left_grid_pin_35_[0]:5 chany_bottom_in[6]:19 0.0004115157 +25 top_left_grid_pin_35_[0]:13 mux_tree_tapbuf_size16_0_sram[1]:29 0.0001149538 +26 top_left_grid_pin_35_[0]:13 mux_tree_tapbuf_size16_0_sram[1]:48 0.000155052 +27 top_left_grid_pin_35_[0]:16 mux_tree_tapbuf_size16_0_sram[1]:48 0.0001149538 +28 top_left_grid_pin_35_[0]:16 mux_tree_tapbuf_size16_0_sram[1]:49 0.000155052 + +*RES +0 top_left_grid_pin_35_[0] top_left_grid_pin_35_[0]:20 0.0006294642 +1 top_left_grid_pin_35_[0]:6 mux_top_track_2\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_35_[0]:8 top_left_grid_pin_35_[0]:7 0.002424107 +3 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:8 0.0045 +4 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:5 0.01422768 +5 top_left_grid_pin_35_[0]:18 top_left_grid_pin_35_[0]:17 0.0045 +6 top_left_grid_pin_35_[0]:17 top_left_grid_pin_35_[0]:16 0.002084821 +7 top_left_grid_pin_35_[0]:19 top_left_grid_pin_35_[0]:18 0.006901786 +8 top_left_grid_pin_35_[0]:20 top_left_grid_pin_35_[0]:19 0.0045 +9 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:12 0.00341 +10 top_left_grid_pin_35_[0]:12 top_left_grid_pin_35_[0]:11 0.001799317 +11 top_left_grid_pin_35_[0]:10 top_left_grid_pin_35_[0]:9 0.003591518 +12 top_left_grid_pin_35_[0]:11 top_left_grid_pin_35_[0]:10 0.00341 +13 top_left_grid_pin_35_[0]:4 mux_top_track_16\/mux_l1_in_0_:A1 0.152 +14 top_left_grid_pin_35_[0]:5 top_left_grid_pin_35_[0]:4 0.0045 +15 top_left_grid_pin_35_[0]:15 top_left_grid_pin_35_[0]:14 0.0004888392 +16 top_left_grid_pin_35_[0]:16 top_left_grid_pin_35_[0]:15 0.0045 +17 top_left_grid_pin_35_[0]:16 top_left_grid_pin_35_[0]:13 0.01360938 +18 top_left_grid_pin_35_[0]:14 mux_top_track_4\/mux_l1_in_0_:A0 0.152 +19 top_left_grid_pin_35_[0]:7 top_left_grid_pin_35_[0]:6 0.0003035715 + +*END + +*D_NET chanx_right_in[3] 0.02004908 //LENGTH 129.395 LUMPCC 0.009936221 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 140.450 38.080 +*I mux_bottom_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 89.240 36.380 +*I mux_top_track_2\/mux_l1_in_2_:A1 I *L 0.00198 *C 69.365 90.780 +*N chanx_right_in[3]:3 *C 69.403 90.780 +*N chanx_right_in[3]:4 *C 70.335 90.780 +*N chanx_right_in[3]:5 *C 70.380 90.825 +*N chanx_right_in[3]:6 *C 70.380 91.743 +*N chanx_right_in[3]:7 *C 70.388 91.800 +*N chanx_right_in[3]:8 *C 89.220 91.800 +*N chanx_right_in[3]:9 *C 89.240 91.793 +*N chanx_right_in[3]:10 *C 89.240 38.087 +*N chanx_right_in[3]:11 *C 89.240 36.380 +*N chanx_right_in[3]:12 *C 89.240 36.425 +*N chanx_right_in[3]:13 *C 89.240 38.023 +*N chanx_right_in[3]:14 *C 89.248 38.080 + +*CAP +0 chanx_right_in[3] 0.002017736 +1 mux_bottom_track_9\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_2_:A1 1e-06 +3 chanx_right_in[3]:3 9.116356e-05 +4 chanx_right_in[3]:4 9.116356e-05 +5 chanx_right_in[3]:5 9.245882e-05 +6 chanx_right_in[3]:6 9.245882e-05 +7 chanx_right_in[3]:7 0.0009638016 +8 chanx_right_in[3]:8 0.0009638016 +9 chanx_right_in[3]:9 0.001769259 +10 chanx_right_in[3]:10 0.001769259 +11 chanx_right_in[3]:11 3.240113e-05 +12 chanx_right_in[3]:12 0.0001048114 +13 chanx_right_in[3]:13 0.0001048114 +14 chanx_right_in[3]:14 0.002017736 +15 chanx_right_in[3] chanx_right_in[16]:54 1.733523e-05 +16 chanx_right_in[3] chanx_right_in[16]:55 0.0006647045 +17 chanx_right_in[3]:14 chanx_right_in[16]:49 1.733523e-05 +18 chanx_right_in[3]:14 chanx_right_in[16]:54 0.0006647045 +19 chanx_right_in[3]:10 chany_bottom_in[13]:20 2.682523e-06 +20 chanx_right_in[3]:10 chany_bottom_in[13]:21 6.294634e-06 +21 chanx_right_in[3]:8 chany_bottom_in[13]:22 0.0003366751 +22 chanx_right_in[3]:9 chany_bottom_in[13]:14 2.682523e-06 +23 chanx_right_in[3]:9 chany_bottom_in[13]:20 6.294634e-06 +24 chanx_right_in[3]:7 chany_bottom_in[13]:23 0.0003366751 +25 chanx_right_in[3]:8 chanx_left_in[4]:26 0.0003104311 +26 chanx_right_in[3]:7 chanx_left_in[4]:27 0.0003104311 +27 chanx_right_in[3]:10 chany_bottom_in[7]:17 0.0002973683 +28 chanx_right_in[3]:9 chany_bottom_in[7]:16 0.0002973683 +29 chanx_right_in[3]:10 chany_bottom_in[11]:16 0.000615907 +30 chanx_right_in[3]:10 chany_bottom_in[11]:14 0.001123884 +31 chanx_right_in[3]:10 chany_bottom_in[11]:15 0.0003412684 +32 chanx_right_in[3]:9 chany_bottom_in[11]:14 0.0003412684 +33 chanx_right_in[3]:9 chany_bottom_in[11]:8 0.001123884 +34 chanx_right_in[3]:9 chany_bottom_in[11]:15 0.000615907 +35 chanx_right_in[3]:10 mux_tree_tapbuf_size10_0_sram[0]:21 0.0005888396 +36 chanx_right_in[3]:9 mux_tree_tapbuf_size10_0_sram[0]:22 0.0005888396 +37 chanx_right_in[3] optlc_net_152:21 0.0001601101 +38 chanx_right_in[3] optlc_net_152:29 0.0004691185 +39 chanx_right_in[3] optlc_net_152:27 2.625714e-05 +40 chanx_right_in[3]:12 optlc_net_152:27 7.234563e-06 +41 chanx_right_in[3]:13 optlc_net_152:28 7.234563e-06 +42 chanx_right_in[3]:14 optlc_net_152:29 0.0001601101 +43 chanx_right_in[3]:14 optlc_net_152:26 2.625714e-05 +44 chanx_right_in[3]:14 optlc_net_152:28 0.0004691185 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:14 0.008021724 +1 chanx_right_in[3]:11 mux_bottom_track_9\/mux_l1_in_1_:A1 0.152 +2 chanx_right_in[3]:12 chanx_right_in[3]:11 0.0045 +3 chanx_right_in[3]:13 chanx_right_in[3]:12 0.001426339 +4 chanx_right_in[3]:14 chanx_right_in[3]:13 0.00341 +5 chanx_right_in[3]:14 chanx_right_in[3]:10 0.00341 +6 chanx_right_in[3]:10 chanx_right_in[3]:9 0.008413782 +7 chanx_right_in[3]:8 chanx_right_in[3]:7 0.002950425 +8 chanx_right_in[3]:9 chanx_right_in[3]:8 0.00341 +9 chanx_right_in[3]:6 chanx_right_in[3]:5 0.0008191965 +10 chanx_right_in[3]:7 chanx_right_in[3]:6 0.00341 +11 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0008325893 +12 chanx_right_in[3]:5 chanx_right_in[3]:4 0.0045 +13 chanx_right_in[3]:3 mux_top_track_2\/mux_l1_in_2_:A1 0.152 + +*END + +*D_NET right_top_grid_pin_45_[0] 0.00814313 //LENGTH 59.285 LUMPCC 0.002900892 DR + +*CONN +*P right_top_grid_pin_45_[0] I *L 0.29796 *C 137.540 102.070 +*I mux_right_track_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 122.650 86.360 +*I mux_right_track_32\/mux_l1_in_1_:A1 I *L 0.00198 *C 109.020 83.300 +*I mux_right_track_2\/mux_l1_in_2_:A1 I *L 0.00198 *C 113.620 94.180 +*N right_top_grid_pin_45_[0]:4 *C 113.620 94.195 +*N right_top_grid_pin_45_[0]:5 *C 113.620 94.520 +*N right_top_grid_pin_45_[0]:6 *C 113.620 94.475 +*N right_top_grid_pin_45_[0]:7 *C 109.058 83.300 +*N right_top_grid_pin_45_[0]:8 *C 112.655 83.300 +*N right_top_grid_pin_45_[0]:9 *C 112.700 83.345 +*N right_top_grid_pin_45_[0]:10 *C 112.700 86.360 +*N right_top_grid_pin_45_[0]:11 *C 122.613 86.360 +*N right_top_grid_pin_45_[0]:12 *C 113.665 86.360 +*N right_top_grid_pin_45_[0]:13 *C 113.620 86.405 +*N right_top_grid_pin_45_[0]:14 *C 113.620 93.840 +*N right_top_grid_pin_45_[0]:15 *C 113.628 93.840 +*N right_top_grid_pin_45_[0]:16 *C 137.532 93.840 +*N right_top_grid_pin_45_[0]:17 *C 137.540 93.898 + +*CAP +0 right_top_grid_pin_45_[0] 0.0003749086 +1 mux_right_track_4\/mux_l2_in_2_:A0 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:A1 1e-06 +3 mux_right_track_2\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_45_[0]:4 3.662219e-05 +5 right_top_grid_pin_45_[0]:5 7.050388e-05 +6 right_top_grid_pin_45_[0]:6 5.161106e-05 +7 right_top_grid_pin_45_[0]:7 0.0001224482 +8 right_top_grid_pin_45_[0]:8 0.0001224482 +9 right_top_grid_pin_45_[0]:9 0.0002145421 +10 right_top_grid_pin_45_[0]:10 0.0002343567 +11 right_top_grid_pin_45_[0]:11 0.0005049038 +12 right_top_grid_pin_45_[0]:12 0.0005049038 +13 right_top_grid_pin_45_[0]:13 0.0004321269 +14 right_top_grid_pin_45_[0]:14 0.0005024605 +15 right_top_grid_pin_45_[0]:15 0.0008462465 +16 right_top_grid_pin_45_[0]:16 0.0008462465 +17 right_top_grid_pin_45_[0]:17 0.0003749086 +18 right_top_grid_pin_45_[0] chanx_right_in[4]:34 6.443307e-06 +19 right_top_grid_pin_45_[0]:15 chanx_right_in[4]:33 0.0005694862 +20 right_top_grid_pin_45_[0]:17 chanx_right_in[4]:35 6.443307e-06 +21 right_top_grid_pin_45_[0]:16 chanx_right_in[4]:34 0.0005694862 +22 right_top_grid_pin_45_[0]:15 chanx_right_in[14]:39 0.0002307189 +23 right_top_grid_pin_45_[0]:15 chanx_right_in[14]:41 5.51981e-05 +24 right_top_grid_pin_45_[0]:16 chanx_right_in[14] 5.51981e-05 +25 right_top_grid_pin_45_[0]:16 chanx_right_in[14]:40 0.0002307189 +26 right_top_grid_pin_45_[0] right_top_grid_pin_49_[0] 7.875366e-05 +27 right_top_grid_pin_45_[0]:6 right_top_grid_pin_49_[0]:11 6.760301e-08 +28 right_top_grid_pin_45_[0]:12 right_top_grid_pin_49_[0]:9 0.000189499 +29 right_top_grid_pin_45_[0]:13 right_top_grid_pin_49_[0]:10 1.19432e-06 +30 right_top_grid_pin_45_[0]:13 right_top_grid_pin_49_[0]:8 1.047177e-05 +31 right_top_grid_pin_45_[0]:11 right_top_grid_pin_49_[0]:8 0.000189499 +32 right_top_grid_pin_45_[0]:14 right_top_grid_pin_49_[0]:11 1.19432e-06 +33 right_top_grid_pin_45_[0]:14 right_top_grid_pin_49_[0]:10 6.760301e-08 +34 right_top_grid_pin_45_[0]:17 right_top_grid_pin_49_[0]:14 7.875366e-05 +35 right_top_grid_pin_45_[0]:7 right_top_grid_pin_49_[0]:5 4.135483e-05 +36 right_top_grid_pin_45_[0]:8 right_top_grid_pin_49_[0]:6 4.135483e-05 +37 right_top_grid_pin_45_[0]:10 right_top_grid_pin_49_[0]:9 1.047177e-05 +38 right_top_grid_pin_45_[0]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 1.453706e-06 +39 right_top_grid_pin_45_[0]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.453706e-06 +40 right_top_grid_pin_45_[0]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.771051e-05 +41 right_top_grid_pin_45_[0]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.771051e-05 +42 right_top_grid_pin_45_[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.93684e-05 +43 right_top_grid_pin_45_[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001487257 +44 right_top_grid_pin_45_[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001487257 +45 right_top_grid_pin_45_[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.93684e-05 + +*RES +0 right_top_grid_pin_45_[0] right_top_grid_pin_45_[0]:17 0.007296875 +1 right_top_grid_pin_45_[0]:5 right_top_grid_pin_45_[0]:4 0.0001766305 +2 right_top_grid_pin_45_[0]:6 right_top_grid_pin_45_[0]:5 0.0045 +3 right_top_grid_pin_45_[0]:4 mux_right_track_2\/mux_l1_in_2_:A1 0.152 +4 right_top_grid_pin_45_[0]:12 right_top_grid_pin_45_[0]:11 0.00798884 +5 right_top_grid_pin_45_[0]:13 right_top_grid_pin_45_[0]:12 0.0045 +6 right_top_grid_pin_45_[0]:13 right_top_grid_pin_45_[0]:10 0.0008214285 +7 right_top_grid_pin_45_[0]:11 mux_right_track_4\/mux_l2_in_2_:A0 0.152 +8 right_top_grid_pin_45_[0]:14 right_top_grid_pin_45_[0]:13 0.006638393 +9 right_top_grid_pin_45_[0]:14 right_top_grid_pin_45_[0]:6 0.0005669643 +10 right_top_grid_pin_45_[0]:15 right_top_grid_pin_45_[0]:14 0.00341 +11 right_top_grid_pin_45_[0]:17 right_top_grid_pin_45_[0]:16 0.00341 +12 right_top_grid_pin_45_[0]:16 right_top_grid_pin_45_[0]:15 0.003745117 +13 right_top_grid_pin_45_[0]:7 mux_right_track_32\/mux_l1_in_1_:A1 0.152 +14 right_top_grid_pin_45_[0]:8 right_top_grid_pin_45_[0]:7 0.003212054 +15 right_top_grid_pin_45_[0]:9 right_top_grid_pin_45_[0]:8 0.0045 +16 right_top_grid_pin_45_[0]:10 right_top_grid_pin_45_[0]:9 0.002691964 + +*END + +*D_NET bottom_left_grid_pin_37_[0] 0.006482509 //LENGTH 57.480 LUMPCC 0 DR + +*CONN +*P bottom_left_grid_pin_37_[0] I *L 0.29796 *C 29.818 3.400 +*I mux_bottom_track_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 31.455 31.620 +*I mux_bottom_track_33\/mux_l1_in_1_:A0 I *L 0.001631 *C 26.050 33.320 +*I mux_bottom_track_3\/mux_l1_in_3_:A1 I *L 0.00198 *C 48.400 25.500 +*N bottom_left_grid_pin_37_[0]:4 *C 48.363 25.500 +*N bottom_left_grid_pin_37_[0]:5 *C 47.885 25.500 +*N bottom_left_grid_pin_37_[0]:6 *C 47.840 25.500 +*N bottom_left_grid_pin_37_[0]:7 *C 47.840 25.160 +*N bottom_left_grid_pin_37_[0]:8 *C 47.833 25.160 +*N bottom_left_grid_pin_37_[0]:9 *C 30.367 25.160 +*N bottom_left_grid_pin_37_[0]:10 *C 30.360 25.218 +*N bottom_left_grid_pin_37_[0]:11 *C 30.360 26.180 +*N bottom_left_grid_pin_37_[0]:12 *C 26.088 33.320 +*N bottom_left_grid_pin_37_[0]:13 *C 29.855 33.320 +*N bottom_left_grid_pin_37_[0]:14 *C 29.900 33.275 +*N bottom_left_grid_pin_37_[0]:15 *C 31.418 31.620 +*N bottom_left_grid_pin_37_[0]:16 *C 29.945 31.620 +*N bottom_left_grid_pin_37_[0]:17 *C 29.900 31.620 +*N bottom_left_grid_pin_37_[0]:18 *C 29.900 26.180 +*N bottom_left_grid_pin_37_[0]:19 *C 29.900 3.458 +*N bottom_left_grid_pin_37_[0]:20 *C 29.900 3.400 + +*CAP +0 bottom_left_grid_pin_37_[0] 2.512663e-05 +1 mux_bottom_track_5\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_3\/mux_l1_in_3_:A1 1e-06 +4 bottom_left_grid_pin_37_[0]:4 6.849136e-05 +5 bottom_left_grid_pin_37_[0]:5 6.849136e-05 +6 bottom_left_grid_pin_37_[0]:6 5.415418e-05 +7 bottom_left_grid_pin_37_[0]:7 5.777329e-05 +8 bottom_left_grid_pin_37_[0]:8 0.001206355 +9 bottom_left_grid_pin_37_[0]:9 0.001206355 +10 bottom_left_grid_pin_37_[0]:10 7.211111e-05 +11 bottom_left_grid_pin_37_[0]:11 9.55169e-05 +12 bottom_left_grid_pin_37_[0]:12 0.00026204 +13 bottom_left_grid_pin_37_[0]:13 0.00026204 +14 bottom_left_grid_pin_37_[0]:14 9.773725e-05 +15 bottom_left_grid_pin_37_[0]:15 0.000101779 +16 bottom_left_grid_pin_37_[0]:16 0.000101779 +17 bottom_left_grid_pin_37_[0]:17 0.0004072129 +18 bottom_left_grid_pin_37_[0]:18 0.00133392 +19 bottom_left_grid_pin_37_[0]:19 0.0010335 +20 bottom_left_grid_pin_37_[0]:20 2.512663e-05 + +*RES +0 bottom_left_grid_pin_37_[0] bottom_left_grid_pin_37_[0]:20 2.35e-05 +1 bottom_left_grid_pin_37_[0]:19 bottom_left_grid_pin_37_[0]:18 0.02028795 +2 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_37_[0]:19 0.00341 +3 bottom_left_grid_pin_37_[0]:16 bottom_left_grid_pin_37_[0]:15 0.001314732 +4 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:16 0.0045 +5 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:14 0.001477679 +6 bottom_left_grid_pin_37_[0]:15 mux_bottom_track_5\/mux_l2_in_3_:A0 0.152 +7 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_37_[0]:12 0.00336384 +8 bottom_left_grid_pin_37_[0]:14 bottom_left_grid_pin_37_[0]:13 0.0045 +9 bottom_left_grid_pin_37_[0]:12 mux_bottom_track_33\/mux_l1_in_1_:A0 0.152 +10 bottom_left_grid_pin_37_[0]:10 bottom_left_grid_pin_37_[0]:9 0.00341 +11 bottom_left_grid_pin_37_[0]:9 bottom_left_grid_pin_37_[0]:8 0.002736183 +12 bottom_left_grid_pin_37_[0]:7 bottom_left_grid_pin_37_[0]:6 0.0001634615 +13 bottom_left_grid_pin_37_[0]:8 bottom_left_grid_pin_37_[0]:7 0.00341 +14 bottom_left_grid_pin_37_[0]:5 bottom_left_grid_pin_37_[0]:4 0.0004263392 +15 bottom_left_grid_pin_37_[0]:6 bottom_left_grid_pin_37_[0]:5 0.0045 +16 bottom_left_grid_pin_37_[0]:4 mux_bottom_track_3\/mux_l1_in_3_:A1 0.152 +17 bottom_left_grid_pin_37_[0]:18 bottom_left_grid_pin_37_[0]:17 0.004857143 +18 bottom_left_grid_pin_37_[0]:18 bottom_left_grid_pin_37_[0]:11 0.0004107143 +19 bottom_left_grid_pin_37_[0]:11 bottom_left_grid_pin_37_[0]:10 0.0008593751 + +*END + +*D_NET chanx_left_in[7] 0.007521197 //LENGTH 50.345 LUMPCC 0.001935594 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 42.160 +*I mux_bottom_track_5\/mux_l2_in_6_:A0 I *L 0.001631 *C 28.695 39.100 +*I mux_top_track_16\/mux_l2_in_2_:A1 I *L 0.00198 *C 36.900 50.660 +*N chanx_left_in[7]:3 *C 36.863 50.660 +*N chanx_left_in[7]:4 *C 35.420 50.660 +*N chanx_left_in[7]:5 *C 35.420 51.000 +*N chanx_left_in[7]:6 *C 29.025 51.000 +*N chanx_left_in[7]:7 *C 28.980 50.955 +*N chanx_left_in[7]:8 *C 28.980 41.480 +*N chanx_left_in[7]:9 *C 28.695 39.100 +*N chanx_left_in[7]:10 *C 28.520 39.100 +*N chanx_left_in[7]:11 *C 28.520 39.145 +*N chanx_left_in[7]:12 *C 28.520 41.480 +*N chanx_left_in[7]:13 *C 28.520 42.102 +*N chanx_left_in[7]:14 *C 28.513 42.160 + +*CAP +0 chanx_left_in[7] 0.00124428 +1 mux_bottom_track_5\/mux_l2_in_6_:A0 1e-06 +2 mux_top_track_16\/mux_l2_in_2_:A1 1e-06 +3 chanx_left_in[7]:3 0.0001169179 +4 chanx_left_in[7]:4 0.0001429757 +5 chanx_left_in[7]:5 0.0005144759 +6 chanx_left_in[7]:6 0.0004884182 +7 chanx_left_in[7]:7 0.0006644166 +8 chanx_left_in[7]:8 0.0006947698 +9 chanx_left_in[7]:9 4.78119e-05 +10 chanx_left_in[7]:10 5.183757e-05 +11 chanx_left_in[7]:11 0.0001423816 +12 chanx_left_in[7]:12 0.0002018869 +13 chanx_left_in[7]:13 2.915209e-05 +14 chanx_left_in[7]:14 0.00124428 +15 chanx_left_in[7] chanx_right_in[13]:11 6.735513e-06 +16 chanx_left_in[7] chanx_right_in[13]:15 0.0009610616 +17 chanx_left_in[7]:14 chanx_right_in[13]:12 6.735513e-06 +18 chanx_left_in[7]:14 chanx_right_in[13]:27 0.0009610616 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:14 0.004274258 +1 chanx_left_in[7]:6 chanx_left_in[7]:5 0.005709821 +2 chanx_left_in[7]:7 chanx_left_in[7]:6 0.0045 +3 chanx_left_in[7]:3 mux_top_track_16\/mux_l2_in_2_:A1 0.152 +4 chanx_left_in[7]:10 chanx_left_in[7]:9 9.51087e-05 +5 chanx_left_in[7]:11 chanx_left_in[7]:10 0.0045 +6 chanx_left_in[7]:9 mux_bottom_track_5\/mux_l2_in_6_:A0 0.152 +7 chanx_left_in[7]:13 chanx_left_in[7]:12 0.0005558036 +8 chanx_left_in[7]:14 chanx_left_in[7]:13 0.00341 +9 chanx_left_in[7]:5 chanx_left_in[7]:4 0.0003035715 +10 chanx_left_in[7]:4 chanx_left_in[7]:3 0.001287946 +11 chanx_left_in[7]:12 chanx_left_in[7]:11 0.002084821 +12 chanx_left_in[7]:12 chanx_left_in[7]:8 0.0004107143 +13 chanx_left_in[7]:8 chanx_left_in[7]:7 0.008459821 + +*END + +*D_NET left_top_grid_pin_43_[0] 0.007399976 //LENGTH 62.205 LUMPCC 0.001206272 DR + +*CONN +*P left_top_grid_pin_43_[0] I *L 0.29796 *C 29.818 119.000 +*I mux_left_track_3\/mux_l1_in_4_:A1 I *L 0.00198 *C 23.460 94.180 +*I mux_left_track_5\/mux_l2_in_4_:A1 I *L 0.00198 *C 24.285 90.780 +*I mux_left_track_17\/mux_l2_in_2_:A0 I *L 0.001631 *C 28.810 69.700 +*N left_top_grid_pin_43_[0]:4 *C 28.848 69.700 +*N left_top_grid_pin_43_[0]:5 *C 29.395 69.700 +*N left_top_grid_pin_43_[0]:6 *C 29.440 69.745 +*N left_top_grid_pin_43_[0]:7 *C 23.498 94.180 +*N left_top_grid_pin_43_[0]:8 *C 24.335 94.180 +*N left_top_grid_pin_43_[0]:9 *C 24.380 94.135 +*N left_top_grid_pin_43_[0]:10 *C 24.380 90.825 +*N left_top_grid_pin_43_[0]:11 *C 24.425 90.780 +*N left_top_grid_pin_43_[0]:12 *C 29.395 90.780 +*N left_top_grid_pin_43_[0]:13 *C 29.440 90.780 +*N left_top_grid_pin_43_[0]:14 *C 29.900 90.780 +*N left_top_grid_pin_43_[0]:15 *C 29.900 118.943 +*N left_top_grid_pin_43_[0]:16 *C 29.900 119.000 + +*CAP +0 left_top_grid_pin_43_[0] 2.988167e-05 +1 mux_left_track_3\/mux_l1_in_4_:A1 1e-06 +2 mux_left_track_5\/mux_l2_in_4_:A1 1e-06 +3 mux_left_track_17\/mux_l2_in_2_:A0 1e-06 +4 left_top_grid_pin_43_[0]:4 7.23447e-05 +5 left_top_grid_pin_43_[0]:5 7.23447e-05 +6 left_top_grid_pin_43_[0]:6 0.001251894 +7 left_top_grid_pin_43_[0]:7 9.806412e-05 +8 left_top_grid_pin_43_[0]:8 9.806412e-05 +9 left_top_grid_pin_43_[0]:9 0.0002207955 +10 left_top_grid_pin_43_[0]:10 0.0002207955 +11 left_top_grid_pin_43_[0]:11 0.0003639177 +12 left_top_grid_pin_43_[0]:12 0.0003639177 +13 left_top_grid_pin_43_[0]:13 0.001287202 +14 left_top_grid_pin_43_[0]:14 0.001058455 +15 left_top_grid_pin_43_[0]:15 0.001023147 +16 left_top_grid_pin_43_[0]:16 2.988167e-05 +17 left_top_grid_pin_43_[0]:9 prog_clk[0]:611 1.542844e-06 +18 left_top_grid_pin_43_[0]:10 prog_clk[0]:612 1.542844e-06 +19 left_top_grid_pin_43_[0]:15 prog_clk[0]:496 6.230142e-05 +20 left_top_grid_pin_43_[0]:15 prog_clk[0]:513 0.0001809228 +21 left_top_grid_pin_43_[0]:15 prog_clk[0]:517 5.511465e-05 +22 left_top_grid_pin_43_[0]:15 prog_clk[0]:521 0.0002011514 +23 left_top_grid_pin_43_[0]:15 prog_clk[0]:603 6.834767e-05 +24 left_top_grid_pin_43_[0]:15 prog_clk[0]:607 2.118255e-05 +25 left_top_grid_pin_43_[0]:15 prog_clk[0]:615 6.373504e-07 +26 left_top_grid_pin_43_[0]:13 prog_clk[0]:615 3.105815e-06 +27 left_top_grid_pin_43_[0]:13 prog_clk[0]:617 8.82935e-06 +28 left_top_grid_pin_43_[0]:6 prog_clk[0]:493 8.82935e-06 +29 left_top_grid_pin_43_[0]:6 prog_clk[0]:616 3.105815e-06 +30 left_top_grid_pin_43_[0]:14 prog_clk[0]:512 6.230142e-05 +31 left_top_grid_pin_43_[0]:14 prog_clk[0]:517 0.0001809228 +32 left_top_grid_pin_43_[0]:14 prog_clk[0]:521 5.511465e-05 +33 left_top_grid_pin_43_[0]:14 prog_clk[0]:603 0.0002011514 +34 left_top_grid_pin_43_[0]:14 prog_clk[0]:606 2.118255e-05 +35 left_top_grid_pin_43_[0]:14 prog_clk[0]:607 6.834767e-05 +36 left_top_grid_pin_43_[0]:14 prog_clk[0]:616 6.373504e-07 + +*RES +0 left_top_grid_pin_43_[0] left_top_grid_pin_43_[0]:16 2.35e-05 +1 left_top_grid_pin_43_[0]:7 mux_left_track_3\/mux_l1_in_4_:A1 0.152 +2 left_top_grid_pin_43_[0]:8 left_top_grid_pin_43_[0]:7 0.0007477678 +3 left_top_grid_pin_43_[0]:9 left_top_grid_pin_43_[0]:8 0.0045 +4 left_top_grid_pin_43_[0]:11 left_top_grid_pin_43_[0]:10 0.0045 +5 left_top_grid_pin_43_[0]:11 mux_left_track_5\/mux_l2_in_4_:A1 0.152 +6 left_top_grid_pin_43_[0]:10 left_top_grid_pin_43_[0]:9 0.002955357 +7 left_top_grid_pin_43_[0]:15 left_top_grid_pin_43_[0]:14 0.02514509 +8 left_top_grid_pin_43_[0]:16 left_top_grid_pin_43_[0]:15 0.00341 +9 left_top_grid_pin_43_[0]:12 left_top_grid_pin_43_[0]:11 0.0044375 +10 left_top_grid_pin_43_[0]:13 left_top_grid_pin_43_[0]:12 0.0045 +11 left_top_grid_pin_43_[0]:13 left_top_grid_pin_43_[0]:6 0.01878125 +12 left_top_grid_pin_43_[0]:5 left_top_grid_pin_43_[0]:4 0.0004888393 +13 left_top_grid_pin_43_[0]:6 left_top_grid_pin_43_[0]:5 0.0045 +14 left_top_grid_pin_43_[0]:4 mux_left_track_17\/mux_l2_in_2_:A0 0.152 +15 left_top_grid_pin_43_[0]:14 left_top_grid_pin_43_[0]:13 0.0004107143 + +*END + +*D_NET chany_top_out[16] 0.001020506 //LENGTH 9.100 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 90.160 124.100 +*P chany_top_out[16] O *L 0.7423 *C 86.940 129.235 +*N chany_top_out[16]:2 *C 86.940 127.160 +*N chany_top_out[16]:3 *C 89.240 127.160 +*N chany_top_out[16]:4 *C 89.240 124.145 +*N chany_top_out[16]:5 *C 89.285 124.100 +*N chany_top_out[16]:6 *C 90.123 124.100 + +*CAP +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[16] 0.0001109448 +2 chany_top_out[16]:2 0.0002203881 +3 chany_top_out[16]:3 0.0003101458 +4 chany_top_out[16]:4 0.0002007025 +5 chany_top_out[16]:5 8.866216e-05 +6 chany_top_out[16]:6 8.866216e-05 + +*RES +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[16]:6 0.152 +1 chany_top_out[16]:5 chany_top_out[16]:4 0.0045 +2 chany_top_out[16]:4 chany_top_out[16]:3 0.002691964 +3 chany_top_out[16]:6 chany_top_out[16]:5 0.0007477679 +4 chany_top_out[16]:2 chany_top_out[16] 0.001852679 +5 chany_top_out[16]:3 chany_top_out[16]:2 0.002053572 + +*END + +*D_NET chany_bottom_out[0] 0.001077974 //LENGTH 8.800 LUMPCC 0.0001616366 DR + +*CONN +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 86.425 6.460 +*P chany_bottom_out[0] O *L 0.7423 *C 83.260 1.290 +*N chany_bottom_out[0]:2 *C 83.260 6.415 +*N chany_bottom_out[0]:3 *C 83.305 6.460 +*N chany_bottom_out[0]:4 *C 86.388 6.460 + +*CAP +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[0] 0.0002966412 +2 chany_bottom_out[0]:2 0.0002966412 +3 chany_bottom_out[0]:3 0.0001610274 +4 chany_bottom_out[0]:4 0.0001610274 +5 chany_bottom_out[0]:4 ropt_net_218:7 8.08183e-05 +6 chany_bottom_out[0]:3 ropt_net_218:6 8.08183e-05 + +*RES +0 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[0]:4 0.152 +1 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002752232 +2 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +3 chany_bottom_out[0]:2 chany_bottom_out[0] 0.004575893 + +*END + +*D_NET chanx_left_out[0] 0.002340711 //LENGTH 19.355 LUMPCC 0.0003122969 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.680 77.180 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 61.200 +*N chanx_left_out[0]:2 *C 3.213 61.200 +*N chanx_left_out[0]:3 *C 3.220 61.258 +*N chanx_left_out[0]:4 *C 3.220 76.795 +*N chanx_left_out[0]:5 *C 3.265 76.840 +*N chanx_left_out[0]:6 *C 3.680 76.840 +*N chanx_left_out[0]:7 *C 3.680 77.180 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 0.0001226592 +2 chanx_left_out[0]:2 0.0001226592 +3 chanx_left_out[0]:3 0.000813294 +4 chanx_left_out[0]:4 0.000813294 +5 chanx_left_out[0]:5 4.138725e-05 +6 chanx_left_out[0]:6 6.557302e-05 +7 chanx_left_out[0]:7 4.85472e-05 +8 chanx_left_out[0]:3 ropt_net_155:5 6.463652e-05 +9 chanx_left_out[0]:4 ropt_net_155:4 6.463652e-05 +10 chanx_left_out[0] ropt_net_222:6 2.09982e-06 +11 chanx_left_out[0]:3 ropt_net_222:5 8.941213e-05 +12 chanx_left_out[0]:2 ropt_net_222:7 2.09982e-06 +13 chanx_left_out[0]:4 ropt_net_222:4 8.941213e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:7 0.152 +1 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +2 chanx_left_out[0]:2 chanx_left_out[0] 0.0003105917 +3 chanx_left_out[0]:5 chanx_left_out[0]:4 0.0045 +4 chanx_left_out[0]:4 chanx_left_out[0]:3 0.01387277 +5 chanx_left_out[0]:7 chanx_left_out[0]:6 0.0003035715 +6 chanx_left_out[0]:6 chanx_left_out[0]:5 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size10_10_sram[0] 0.007896924 //LENGTH 59.120 LUMPCC 0.0001419884 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 46.305 66.300 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 41.585 64.260 +*I mux_left_track_17\/mux_l1_in_2_:S I *L 0.00357 *C 60.820 51.000 +*I mux_left_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 70.940 55.760 +*I mux_left_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 65.880 52.750 +*N mux_tree_tapbuf_size10_10_sram[0]:5 *C 65.880 52.750 +*N mux_tree_tapbuf_size10_10_sram[0]:6 *C 70.940 55.760 +*N mux_tree_tapbuf_size10_10_sram[0]:7 *C 70.840 55.420 +*N mux_tree_tapbuf_size10_10_sram[0]:8 *C 70.425 55.420 +*N mux_tree_tapbuf_size10_10_sram[0]:9 *C 70.380 55.375 +*N mux_tree_tapbuf_size10_10_sram[0]:10 *C 70.380 53.765 +*N mux_tree_tapbuf_size10_10_sram[0]:11 *C 70.335 53.720 +*N mux_tree_tapbuf_size10_10_sram[0]:12 *C 68.585 53.720 +*N mux_tree_tapbuf_size10_10_sram[0]:13 *C 68.540 53.675 +*N mux_tree_tapbuf_size10_10_sram[0]:14 *C 68.540 52.405 +*N mux_tree_tapbuf_size10_10_sram[0]:15 *C 68.495 52.360 +*N mux_tree_tapbuf_size10_10_sram[0]:16 *C 65.880 52.360 +*N mux_tree_tapbuf_size10_10_sram[0]:17 *C 64.445 52.360 +*N mux_tree_tapbuf_size10_10_sram[0]:18 *C 64.400 52.315 +*N mux_tree_tapbuf_size10_10_sram[0]:19 *C 64.400 51.000 +*N mux_tree_tapbuf_size10_10_sram[0]:20 *C 63.020 51.000 +*N mux_tree_tapbuf_size10_10_sram[0]:21 *C 62.975 51.000 +*N mux_tree_tapbuf_size10_10_sram[0]:22 *C 60.820 51.000 +*N mux_tree_tapbuf_size10_10_sram[0]:23 *C 47.885 51.000 +*N mux_tree_tapbuf_size10_10_sram[0]:24 *C 47.840 50.955 +*N mux_tree_tapbuf_size10_10_sram[0]:25 *C 47.840 50.378 +*N mux_tree_tapbuf_size10_10_sram[0]:26 *C 47.833 50.320 +*N mux_tree_tapbuf_size10_10_sram[0]:27 *C 44.180 50.320 +*N mux_tree_tapbuf_size10_10_sram[0]:28 *C 44.160 50.328 +*N mux_tree_tapbuf_size10_10_sram[0]:29 *C 44.160 54.393 +*N mux_tree_tapbuf_size10_10_sram[0]:30 *C 44.175 54.400 +*N mux_tree_tapbuf_size10_10_sram[0]:31 *C 44.617 54.400 +*N mux_tree_tapbuf_size10_10_sram[0]:32 *C 44.620 54.458 +*N mux_tree_tapbuf_size10_10_sram[0]:33 *C 41.608 64.288 +*N mux_tree_tapbuf_size10_10_sram[0]:34 *C 41.620 64.600 +*N mux_tree_tapbuf_size10_10_sram[0]:35 *C 44.575 64.600 +*N mux_tree_tapbuf_size10_10_sram[0]:36 *C 44.620 64.600 +*N mux_tree_tapbuf_size10_10_sram[0]:37 *C 44.620 66.255 +*N mux_tree_tapbuf_size10_10_sram[0]:38 *C 44.665 66.300 +*N mux_tree_tapbuf_size10_10_sram[0]:39 *C 46.268 66.300 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_17\/mux_l1_in_2_:S 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:S 1e-06 +4 mux_left_track_17\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_10_sram[0]:5 6.153122e-05 +6 mux_tree_tapbuf_size10_10_sram[0]:6 6.398193e-05 +7 mux_tree_tapbuf_size10_10_sram[0]:7 7.549653e-05 +8 mux_tree_tapbuf_size10_10_sram[0]:8 4.465204e-05 +9 mux_tree_tapbuf_size10_10_sram[0]:9 0.0001414381 +10 mux_tree_tapbuf_size10_10_sram[0]:10 0.0001414381 +11 mux_tree_tapbuf_size10_10_sram[0]:11 0.0001413074 +12 mux_tree_tapbuf_size10_10_sram[0]:12 0.0001413074 +13 mux_tree_tapbuf_size10_10_sram[0]:13 9.583629e-05 +14 mux_tree_tapbuf_size10_10_sram[0]:14 9.583629e-05 +15 mux_tree_tapbuf_size10_10_sram[0]:15 0.0001974687 +16 mux_tree_tapbuf_size10_10_sram[0]:16 0.0003416707 +17 mux_tree_tapbuf_size10_10_sram[0]:17 0.0001114495 +18 mux_tree_tapbuf_size10_10_sram[0]:18 8.669792e-05 +19 mux_tree_tapbuf_size10_10_sram[0]:19 0.0001669866 +20 mux_tree_tapbuf_size10_10_sram[0]:20 0.0001119805 +21 mux_tree_tapbuf_size10_10_sram[0]:21 0.0001804859 +22 mux_tree_tapbuf_size10_10_sram[0]:22 0.001054706 +23 mux_tree_tapbuf_size10_10_sram[0]:23 0.0008423994 +24 mux_tree_tapbuf_size10_10_sram[0]:24 5.445535e-05 +25 mux_tree_tapbuf_size10_10_sram[0]:25 5.445535e-05 +26 mux_tree_tapbuf_size10_10_sram[0]:26 0.0002924552 +27 mux_tree_tapbuf_size10_10_sram[0]:27 0.0002924552 +28 mux_tree_tapbuf_size10_10_sram[0]:28 0.0002969263 +29 mux_tree_tapbuf_size10_10_sram[0]:29 0.0002969263 +30 mux_tree_tapbuf_size10_10_sram[0]:30 8.642027e-05 +31 mux_tree_tapbuf_size10_10_sram[0]:31 8.642027e-05 +32 mux_tree_tapbuf_size10_10_sram[0]:32 0.0005923257 +33 mux_tree_tapbuf_size10_10_sram[0]:33 3.176523e-05 +34 mux_tree_tapbuf_size10_10_sram[0]:34 0.0002580308 +35 mux_tree_tapbuf_size10_10_sram[0]:35 0.0002262656 +36 mux_tree_tapbuf_size10_10_sram[0]:36 0.0007322093 +37 mux_tree_tapbuf_size10_10_sram[0]:37 0.0001041637 +38 mux_tree_tapbuf_size10_10_sram[0]:38 0.000123996 +39 mux_tree_tapbuf_size10_10_sram[0]:39 0.000123996 +40 mux_tree_tapbuf_size10_10_sram[0]:23 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.099421e-05 +41 mux_tree_tapbuf_size10_10_sram[0]:22 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.099421e-05 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_10_sram[0]:39 0.152 +1 mux_tree_tapbuf_size10_10_sram[0]:35 mux_tree_tapbuf_size10_10_sram[0]:34 0.002638393 +2 mux_tree_tapbuf_size10_10_sram[0]:36 mux_tree_tapbuf_size10_10_sram[0]:35 0.0045 +3 mux_tree_tapbuf_size10_10_sram[0]:36 mux_tree_tapbuf_size10_10_sram[0]:32 0.009055804 +4 mux_tree_tapbuf_size10_10_sram[0]:33 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +5 mux_tree_tapbuf_size10_10_sram[0]:38 mux_tree_tapbuf_size10_10_sram[0]:37 0.0045 +6 mux_tree_tapbuf_size10_10_sram[0]:37 mux_tree_tapbuf_size10_10_sram[0]:36 0.001477679 +7 mux_tree_tapbuf_size10_10_sram[0]:39 mux_tree_tapbuf_size10_10_sram[0]:38 0.001430804 +8 mux_tree_tapbuf_size10_10_sram[0]:23 mux_tree_tapbuf_size10_10_sram[0]:22 0.01154911 +9 mux_tree_tapbuf_size10_10_sram[0]:24 mux_tree_tapbuf_size10_10_sram[0]:23 0.0045 +10 mux_tree_tapbuf_size10_10_sram[0]:25 mux_tree_tapbuf_size10_10_sram[0]:24 0.000515625 +11 mux_tree_tapbuf_size10_10_sram[0]:26 mux_tree_tapbuf_size10_10_sram[0]:25 0.00341 +12 mux_tree_tapbuf_size10_10_sram[0]:27 mux_tree_tapbuf_size10_10_sram[0]:26 0.000572225 +13 mux_tree_tapbuf_size10_10_sram[0]:28 mux_tree_tapbuf_size10_10_sram[0]:27 0.00341 +14 mux_tree_tapbuf_size10_10_sram[0]:30 mux_tree_tapbuf_size10_10_sram[0]:29 0.00341 +15 mux_tree_tapbuf_size10_10_sram[0]:29 mux_tree_tapbuf_size10_10_sram[0]:28 0.00063685 +16 mux_tree_tapbuf_size10_10_sram[0]:32 mux_tree_tapbuf_size10_10_sram[0]:31 0.00341 +17 mux_tree_tapbuf_size10_10_sram[0]:31 mux_tree_tapbuf_size10_10_sram[0]:30 6.499219e-05 +18 mux_tree_tapbuf_size10_10_sram[0]:22 mux_left_track_17\/mux_l1_in_2_:S 0.152 +19 mux_tree_tapbuf_size10_10_sram[0]:22 mux_tree_tapbuf_size10_10_sram[0]:21 0.001924107 +20 mux_tree_tapbuf_size10_10_sram[0]:21 mux_tree_tapbuf_size10_10_sram[0]:20 0.0045 +21 mux_tree_tapbuf_size10_10_sram[0]:20 mux_tree_tapbuf_size10_10_sram[0]:19 0.001232143 +22 mux_tree_tapbuf_size10_10_sram[0]:17 mux_tree_tapbuf_size10_10_sram[0]:16 0.00128125 +23 mux_tree_tapbuf_size10_10_sram[0]:18 mux_tree_tapbuf_size10_10_sram[0]:17 0.0045 +24 mux_tree_tapbuf_size10_10_sram[0]:5 mux_left_track_17\/mux_l1_in_1_:S 0.152 +25 mux_tree_tapbuf_size10_10_sram[0]:15 mux_tree_tapbuf_size10_10_sram[0]:14 0.0045 +26 mux_tree_tapbuf_size10_10_sram[0]:14 mux_tree_tapbuf_size10_10_sram[0]:13 0.001133929 +27 mux_tree_tapbuf_size10_10_sram[0]:12 mux_tree_tapbuf_size10_10_sram[0]:11 0.0015625 +28 mux_tree_tapbuf_size10_10_sram[0]:13 mux_tree_tapbuf_size10_10_sram[0]:12 0.0045 +29 mux_tree_tapbuf_size10_10_sram[0]:11 mux_tree_tapbuf_size10_10_sram[0]:10 0.0045 +30 mux_tree_tapbuf_size10_10_sram[0]:10 mux_tree_tapbuf_size10_10_sram[0]:9 0.0014375 +31 mux_tree_tapbuf_size10_10_sram[0]:8 mux_tree_tapbuf_size10_10_sram[0]:7 0.0003705357 +32 mux_tree_tapbuf_size10_10_sram[0]:9 mux_tree_tapbuf_size10_10_sram[0]:8 0.0045 +33 mux_tree_tapbuf_size10_10_sram[0]:6 mux_left_track_17\/mux_l1_in_0_:S 0.152 +34 mux_tree_tapbuf_size10_10_sram[0]:34 mux_tree_tapbuf_size10_10_sram[0]:33 0.0002111487 +35 mux_tree_tapbuf_size10_10_sram[0]:16 mux_tree_tapbuf_size10_10_sram[0]:15 0.002334822 +36 mux_tree_tapbuf_size10_10_sram[0]:16 mux_tree_tapbuf_size10_10_sram[0]:5 0.0003482143 +37 mux_tree_tapbuf_size10_10_sram[0]:7 mux_tree_tapbuf_size10_10_sram[0]:6 0.0003035715 +38 mux_tree_tapbuf_size10_10_sram[0]:19 mux_tree_tapbuf_size10_10_sram[0]:18 0.001174107 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[0] 0.01091487 //LENGTH 83.680 LUMPCC 0.0008207477 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 57.805 63.920 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 60.160 110.160 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.825 75.140 +*I mux_top_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 62.000 61.880 +*I mux_top_track_24\/mux_l1_in_2_:S I *L 0.00357 *C 75.540 61.880 +*N mux_tree_tapbuf_size10_2_sram[0]:5 *C 75.502 61.880 +*N mux_tree_tapbuf_size10_2_sram[0]:6 *C 66.745 61.880 +*N mux_tree_tapbuf_size10_2_sram[0]:7 *C 66.700 61.925 +*N mux_tree_tapbuf_size10_2_sram[0]:8 *C 66.700 63.535 +*N mux_tree_tapbuf_size10_2_sram[0]:9 *C 66.655 63.580 +*N mux_tree_tapbuf_size10_2_sram[0]:10 *C 59.340 63.580 +*N mux_tree_tapbuf_size10_2_sram[0]:11 *C 61.963 61.880 +*N mux_tree_tapbuf_size10_2_sram[0]:12 *C 59.385 61.880 +*N mux_tree_tapbuf_size10_2_sram[0]:13 *C 59.340 61.925 +*N mux_tree_tapbuf_size10_2_sram[0]:14 *C 60.803 75.168 +*N mux_tree_tapbuf_size10_2_sram[0]:15 *C 60.790 75.480 +*N mux_tree_tapbuf_size10_2_sram[0]:16 *C 58.925 75.480 +*N mux_tree_tapbuf_size10_2_sram[0]:17 *C 58.880 75.435 +*N mux_tree_tapbuf_size10_2_sram[0]:18 *C 60.123 110.160 +*N mux_tree_tapbuf_size10_2_sram[0]:19 *C 58.005 110.160 +*N mux_tree_tapbuf_size10_2_sram[0]:20 *C 57.960 110.115 +*N mux_tree_tapbuf_size10_2_sram[0]:21 *C 57.960 93.545 +*N mux_tree_tapbuf_size10_2_sram[0]:22 *C 57.915 93.500 +*N mux_tree_tapbuf_size10_2_sram[0]:23 *C 57.085 93.500 +*N mux_tree_tapbuf_size10_2_sram[0]:24 *C 57.040 93.455 +*N mux_tree_tapbuf_size10_2_sram[0]:25 *C 57.040 74.505 +*N mux_tree_tapbuf_size10_2_sram[0]:26 *C 57.085 74.460 +*N mux_tree_tapbuf_size10_2_sram[0]:27 *C 58.835 74.460 +*N mux_tree_tapbuf_size10_2_sram[0]:28 *C 58.880 74.460 +*N mux_tree_tapbuf_size10_2_sram[0]:29 *C 58.880 63.920 +*N mux_tree_tapbuf_size10_2_sram[0]:30 *C 59.340 63.875 +*N mux_tree_tapbuf_size10_2_sram[0]:31 *C 59.340 63.890 +*N mux_tree_tapbuf_size10_2_sram[0]:32 *C 57.843 63.920 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_24\/mux_l1_in_1_:S 1e-06 +4 mux_top_track_24\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_2_sram[0]:5 0.0005888935 +6 mux_tree_tapbuf_size10_2_sram[0]:6 0.0005888935 +7 mux_tree_tapbuf_size10_2_sram[0]:7 0.0001118248 +8 mux_tree_tapbuf_size10_2_sram[0]:8 0.0001118248 +9 mux_tree_tapbuf_size10_2_sram[0]:9 0.0005492386 +10 mux_tree_tapbuf_size10_2_sram[0]:10 0.0005769298 +11 mux_tree_tapbuf_size10_2_sram[0]:11 0.0002179027 +12 mux_tree_tapbuf_size10_2_sram[0]:12 0.0002179027 +13 mux_tree_tapbuf_size10_2_sram[0]:13 9.376205e-05 +14 mux_tree_tapbuf_size10_2_sram[0]:14 3.19181e-05 +15 mux_tree_tapbuf_size10_2_sram[0]:15 0.0001878938 +16 mux_tree_tapbuf_size10_2_sram[0]:16 0.0001559757 +17 mux_tree_tapbuf_size10_2_sram[0]:17 5.298258e-05 +18 mux_tree_tapbuf_size10_2_sram[0]:18 0.0001622765 +19 mux_tree_tapbuf_size10_2_sram[0]:19 0.0001622765 +20 mux_tree_tapbuf_size10_2_sram[0]:20 0.0008659553 +21 mux_tree_tapbuf_size10_2_sram[0]:21 0.0008659553 +22 mux_tree_tapbuf_size10_2_sram[0]:22 7.278606e-05 +23 mux_tree_tapbuf_size10_2_sram[0]:23 7.278606e-05 +24 mux_tree_tapbuf_size10_2_sram[0]:24 0.001244942 +25 mux_tree_tapbuf_size10_2_sram[0]:25 0.001244942 +26 mux_tree_tapbuf_size10_2_sram[0]:26 0.0001591919 +27 mux_tree_tapbuf_size10_2_sram[0]:27 0.0001591919 +28 mux_tree_tapbuf_size10_2_sram[0]:28 0.0006186594 +29 mux_tree_tapbuf_size10_2_sram[0]:29 0.0005526653 +30 mux_tree_tapbuf_size10_2_sram[0]:30 0.0001288011 +31 mux_tree_tapbuf_size10_2_sram[0]:31 0.000160223 +32 mux_tree_tapbuf_size10_2_sram[0]:32 0.0001325318 +33 mux_tree_tapbuf_size10_2_sram[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.459323e-05 +34 mux_tree_tapbuf_size10_2_sram[0]:20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.459323e-05 +35 mux_tree_tapbuf_size10_2_sram[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.401516e-05 +36 mux_tree_tapbuf_size10_2_sram[0]:20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.401516e-05 +37 mux_tree_tapbuf_size10_2_sram[0]:27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.47016e-08 +38 mux_tree_tapbuf_size10_2_sram[0]:28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.000120174 +39 mux_tree_tapbuf_size10_2_sram[0]:28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.831387e-05 +40 mux_tree_tapbuf_size10_2_sram[0]:26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.47016e-08 +41 mux_tree_tapbuf_size10_2_sram[0]:17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.831387e-05 +42 mux_tree_tapbuf_size10_2_sram[0]:29 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.000120174 +43 mux_tree_tapbuf_size10_2_sram[0]:28 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.129346e-05 +44 mux_tree_tapbuf_size10_2_sram[0]:30 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.462951e-05 +45 mux_tree_tapbuf_size10_2_sram[0]:13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.462951e-05 +46 mux_tree_tapbuf_size10_2_sram[0]:29 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.129346e-05 +47 mux_tree_tapbuf_size10_2_sram[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.864362e-05 +48 mux_tree_tapbuf_size10_2_sram[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.867118e-05 +49 mux_tree_tapbuf_size10_2_sram[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.867118e-05 +50 mux_tree_tapbuf_size10_2_sram[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.864362e-05 +51 mux_tree_tapbuf_size10_2_sram[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.51032e-08 +52 mux_tree_tapbuf_size10_2_sram[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.51032e-08 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_2_sram[0]:32 0.152 +1 mux_tree_tapbuf_size10_2_sram[0]:27 mux_tree_tapbuf_size10_2_sram[0]:26 0.0015625 +2 mux_tree_tapbuf_size10_2_sram[0]:28 mux_tree_tapbuf_size10_2_sram[0]:27 0.0045 +3 mux_tree_tapbuf_size10_2_sram[0]:28 mux_tree_tapbuf_size10_2_sram[0]:17 0.0008705358 +4 mux_tree_tapbuf_size10_2_sram[0]:26 mux_tree_tapbuf_size10_2_sram[0]:25 0.0045 +5 mux_tree_tapbuf_size10_2_sram[0]:25 mux_tree_tapbuf_size10_2_sram[0]:24 0.01691964 +6 mux_tree_tapbuf_size10_2_sram[0]:23 mux_tree_tapbuf_size10_2_sram[0]:22 0.0007410714 +7 mux_tree_tapbuf_size10_2_sram[0]:24 mux_tree_tapbuf_size10_2_sram[0]:23 0.0045 +8 mux_tree_tapbuf_size10_2_sram[0]:22 mux_tree_tapbuf_size10_2_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size10_2_sram[0]:21 mux_tree_tapbuf_size10_2_sram[0]:20 0.01479464 +10 mux_tree_tapbuf_size10_2_sram[0]:19 mux_tree_tapbuf_size10_2_sram[0]:18 0.001890625 +11 mux_tree_tapbuf_size10_2_sram[0]:20 mux_tree_tapbuf_size10_2_sram[0]:19 0.0045 +12 mux_tree_tapbuf_size10_2_sram[0]:18 mux_top_track_24\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_2_sram[0]:31 mux_tree_tapbuf_size10_2_sram[0]:30 0.0045 +14 mux_tree_tapbuf_size10_2_sram[0]:31 mux_tree_tapbuf_size10_2_sram[0]:10 0.0002767857 +15 mux_tree_tapbuf_size10_2_sram[0]:30 mux_tree_tapbuf_size10_2_sram[0]:29 0.0004107143 +16 mux_tree_tapbuf_size10_2_sram[0]:30 mux_tree_tapbuf_size10_2_sram[0]:13 0.001741071 +17 mux_tree_tapbuf_size10_2_sram[0]:32 mux_tree_tapbuf_size10_2_sram[0]:31 0.001337054 +18 mux_tree_tapbuf_size10_2_sram[0]:16 mux_tree_tapbuf_size10_2_sram[0]:15 0.001665179 +19 mux_tree_tapbuf_size10_2_sram[0]:17 mux_tree_tapbuf_size10_2_sram[0]:16 0.0045 +20 mux_tree_tapbuf_size10_2_sram[0]:14 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +21 mux_tree_tapbuf_size10_2_sram[0]:12 mux_tree_tapbuf_size10_2_sram[0]:11 0.002301339 +22 mux_tree_tapbuf_size10_2_sram[0]:13 mux_tree_tapbuf_size10_2_sram[0]:12 0.0045 +23 mux_tree_tapbuf_size10_2_sram[0]:11 mux_top_track_24\/mux_l1_in_1_:S 0.152 +24 mux_tree_tapbuf_size10_2_sram[0]:5 mux_top_track_24\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size10_2_sram[0]:6 mux_tree_tapbuf_size10_2_sram[0]:5 0.007819196 +26 mux_tree_tapbuf_size10_2_sram[0]:7 mux_tree_tapbuf_size10_2_sram[0]:6 0.0045 +27 mux_tree_tapbuf_size10_2_sram[0]:9 mux_tree_tapbuf_size10_2_sram[0]:8 0.0045 +28 mux_tree_tapbuf_size10_2_sram[0]:8 mux_tree_tapbuf_size10_2_sram[0]:7 0.0014375 +29 mux_tree_tapbuf_size10_2_sram[0]:15 mux_tree_tapbuf_size10_2_sram[0]:14 0.0002111487 +30 mux_tree_tapbuf_size10_2_sram[0]:10 mux_tree_tapbuf_size10_2_sram[0]:9 0.006531251 +31 mux_tree_tapbuf_size10_2_sram[0]:29 mux_tree_tapbuf_size10_2_sram[0]:28 0.009410716 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[1] 0.004009904 //LENGTH 30.965 LUMPCC 0.0005117731 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 93.685 31.280 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 96.040 29.240 +*I mux_bottom_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 95.580 23.120 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 92.635 20.740 +*I mux_bottom_track_9\/mux_l2_in_2_:S I *L 0.00357 *C 98.080 34.000 +*I mux_bottom_track_9\/mux_l2_in_3_:S I *L 0.00357 *C 102.680 34.000 +*N mux_tree_tapbuf_size10_6_sram[1]:6 *C 102.642 34.000 +*N mux_tree_tapbuf_size10_6_sram[1]:7 *C 98.080 34.000 +*N mux_tree_tapbuf_size10_6_sram[1]:8 *C 96.645 34.000 +*N mux_tree_tapbuf_size10_6_sram[1]:9 *C 96.600 33.955 +*N mux_tree_tapbuf_size10_6_sram[1]:10 *C 96.600 31.325 +*N mux_tree_tapbuf_size10_6_sram[1]:11 *C 96.555 31.280 +*N mux_tree_tapbuf_size10_6_sram[1]:12 *C 92.635 20.740 +*N mux_tree_tapbuf_size10_6_sram[1]:13 *C 92.920 20.740 +*N mux_tree_tapbuf_size10_6_sram[1]:14 *C 92.920 20.785 +*N mux_tree_tapbuf_size10_6_sram[1]:15 *C 95.543 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:16 *C 92.965 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:17 *C 92.920 23.120 +*N mux_tree_tapbuf_size10_6_sram[1]:18 *C 96.002 29.240 +*N mux_tree_tapbuf_size10_6_sram[1]:19 *C 92.965 29.240 +*N mux_tree_tapbuf_size10_6_sram[1]:20 *C 92.920 29.240 +*N mux_tree_tapbuf_size10_6_sram[1]:21 *C 92.920 31.235 +*N mux_tree_tapbuf_size10_6_sram[1]:22 *C 92.965 31.280 +*N mux_tree_tapbuf_size10_6_sram[1]:23 *C 93.685 31.280 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_track_9\/mux_l2_in_1_:S 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_track_9\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_track_9\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size10_6_sram[1]:6 0.0003142428 +7 mux_tree_tapbuf_size10_6_sram[1]:7 0.0004515702 +8 mux_tree_tapbuf_size10_6_sram[1]:8 0.0001050115 +9 mux_tree_tapbuf_size10_6_sram[1]:9 0.0001711163 +10 mux_tree_tapbuf_size10_6_sram[1]:10 0.0001711163 +11 mux_tree_tapbuf_size10_6_sram[1]:11 0.000165704 +12 mux_tree_tapbuf_size10_6_sram[1]:12 5.772897e-05 +13 mux_tree_tapbuf_size10_6_sram[1]:13 6.04106e-05 +14 mux_tree_tapbuf_size10_6_sram[1]:14 0.0001363563 +15 mux_tree_tapbuf_size10_6_sram[1]:15 0.0001199109 +16 mux_tree_tapbuf_size10_6_sram[1]:16 0.0001199109 +17 mux_tree_tapbuf_size10_6_sram[1]:17 0.0004318934 +18 mux_tree_tapbuf_size10_6_sram[1]:18 0.0001821101 +19 mux_tree_tapbuf_size10_6_sram[1]:19 0.0001821101 +20 mux_tree_tapbuf_size10_6_sram[1]:20 0.0004111479 +21 mux_tree_tapbuf_size10_6_sram[1]:21 0.0001086063 +22 mux_tree_tapbuf_size10_6_sram[1]:22 5.416741e-05 +23 mux_tree_tapbuf_size10_6_sram[1]:23 0.0002490168 +24 mux_tree_tapbuf_size10_6_sram[1]:19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.86306e-05 +25 mux_tree_tapbuf_size10_6_sram[1]:18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.86306e-05 +26 mux_tree_tapbuf_size10_6_sram[1]:21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.118415e-05 +27 mux_tree_tapbuf_size10_6_sram[1]:16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.316012e-05 +28 mux_tree_tapbuf_size10_6_sram[1]:17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.291169e-05 +29 mux_tree_tapbuf_size10_6_sram[1]:15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.316012e-05 +30 mux_tree_tapbuf_size10_6_sram[1]:20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.118415e-05 +31 mux_tree_tapbuf_size10_6_sram[1]:20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.291169e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_6_sram[1]:23 0.152 +1 mux_tree_tapbuf_size10_6_sram[1]:22 mux_tree_tapbuf_size10_6_sram[1]:21 0.0045 +2 mux_tree_tapbuf_size10_6_sram[1]:21 mux_tree_tapbuf_size10_6_sram[1]:20 0.00178125 +3 mux_tree_tapbuf_size10_6_sram[1]:11 mux_tree_tapbuf_size10_6_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size10_6_sram[1]:10 mux_tree_tapbuf_size10_6_sram[1]:9 0.002348214 +5 mux_tree_tapbuf_size10_6_sram[1]:8 mux_tree_tapbuf_size10_6_sram[1]:7 0.00128125 +6 mux_tree_tapbuf_size10_6_sram[1]:9 mux_tree_tapbuf_size10_6_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size10_6_sram[1]:13 mux_tree_tapbuf_size10_6_sram[1]:12 0.0001548913 +8 mux_tree_tapbuf_size10_6_sram[1]:14 mux_tree_tapbuf_size10_6_sram[1]:13 0.0045 +9 mux_tree_tapbuf_size10_6_sram[1]:12 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size10_6_sram[1]:23 mux_tree_tapbuf_size10_6_sram[1]:22 0.0006428572 +11 mux_tree_tapbuf_size10_6_sram[1]:23 mux_tree_tapbuf_size10_6_sram[1]:11 0.0025625 +12 mux_tree_tapbuf_size10_6_sram[1]:6 mux_bottom_track_9\/mux_l2_in_3_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[1]:7 mux_bottom_track_9\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_6_sram[1]:7 mux_tree_tapbuf_size10_6_sram[1]:6 0.00407366 +15 mux_tree_tapbuf_size10_6_sram[1]:16 mux_tree_tapbuf_size10_6_sram[1]:15 0.00230134 +16 mux_tree_tapbuf_size10_6_sram[1]:17 mux_tree_tapbuf_size10_6_sram[1]:16 0.0045 +17 mux_tree_tapbuf_size10_6_sram[1]:17 mux_tree_tapbuf_size10_6_sram[1]:14 0.002084821 +18 mux_tree_tapbuf_size10_6_sram[1]:15 mux_bottom_track_9\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size10_6_sram[1]:19 mux_tree_tapbuf_size10_6_sram[1]:18 0.002712054 +20 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:19 0.0045 +21 mux_tree_tapbuf_size10_6_sram[1]:20 mux_tree_tapbuf_size10_6_sram[1]:17 0.005464286 +22 mux_tree_tapbuf_size10_6_sram[1]:18 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_9_sram[2] 0.003989096 //LENGTH 28.180 LUMPCC 0.0003523615 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 48.145 74.800 +*I mux_left_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 42.880 69.070 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 37.445 71.740 +*I mux_left_track_9\/mux_l3_in_1_:S I *L 0.00357 *C 37.820 78.200 +*N mux_tree_tapbuf_size10_9_sram[2]:4 *C 37.720 78.200 +*N mux_tree_tapbuf_size10_9_sram[2]:5 *C 37.720 78.155 +*N mux_tree_tapbuf_size10_9_sram[2]:6 *C 37.445 71.740 +*N mux_tree_tapbuf_size10_9_sram[2]:7 *C 37.720 71.740 +*N mux_tree_tapbuf_size10_9_sram[2]:8 *C 37.720 71.740 +*N mux_tree_tapbuf_size10_9_sram[2]:9 *C 37.720 69.405 +*N mux_tree_tapbuf_size10_9_sram[2]:10 *C 37.720 69.360 +*N mux_tree_tapbuf_size10_9_sram[2]:11 *C 37.720 69.020 +*N mux_tree_tapbuf_size10_9_sram[2]:12 *C 42.880 69.023 +*N mux_tree_tapbuf_size10_9_sram[2]:13 *C 42.880 68.680 +*N mux_tree_tapbuf_size10_9_sram[2]:14 *C 46.415 68.680 +*N mux_tree_tapbuf_size10_9_sram[2]:15 *C 46.460 68.725 +*N mux_tree_tapbuf_size10_9_sram[2]:16 *C 46.460 74.755 +*N mux_tree_tapbuf_size10_9_sram[2]:17 *C 46.505 74.800 +*N mux_tree_tapbuf_size10_9_sram[2]:18 *C 48.108 74.800 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_9\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_9_sram[2]:4 3.792724e-05 +5 mux_tree_tapbuf_size10_9_sram[2]:5 0.0004363249 +6 mux_tree_tapbuf_size10_9_sram[2]:6 6.047021e-05 +7 mux_tree_tapbuf_size10_9_sram[2]:7 6.572572e-05 +8 mux_tree_tapbuf_size10_9_sram[2]:8 0.000645798 +9 mux_tree_tapbuf_size10_9_sram[2]:9 0.0001713811 +10 mux_tree_tapbuf_size10_9_sram[2]:10 7.203608e-05 +11 mux_tree_tapbuf_size10_9_sram[2]:11 0.0002369937 +12 mux_tree_tapbuf_size10_9_sram[2]:12 0.0002347693 +13 mux_tree_tapbuf_size10_9_sram[2]:13 0.0003348523 +14 mux_tree_tapbuf_size10_9_sram[2]:14 0.0003044479 +15 mux_tree_tapbuf_size10_9_sram[2]:15 0.0003507672 +16 mux_tree_tapbuf_size10_9_sram[2]:16 0.0003507672 +17 mux_tree_tapbuf_size10_9_sram[2]:17 0.0001652366 +18 mux_tree_tapbuf_size10_9_sram[2]:18 0.0001652366 +19 mux_tree_tapbuf_size10_9_sram[2]:12 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:6 0.000103185 +20 mux_tree_tapbuf_size10_9_sram[2]:11 mux_tree_tapbuf_size10_mem_9_ccff_tail[0]:7 0.000103185 +21 mux_tree_tapbuf_size10_9_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.299575e-05 +22 mux_tree_tapbuf_size10_9_sram[2]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.299575e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_9_sram[2]:18 0.152 +1 mux_tree_tapbuf_size10_9_sram[2]:6 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size10_9_sram[2]:7 mux_tree_tapbuf_size10_9_sram[2]:6 0.0001494565 +3 mux_tree_tapbuf_size10_9_sram[2]:8 mux_tree_tapbuf_size10_9_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size10_9_sram[2]:8 mux_tree_tapbuf_size10_9_sram[2]:5 0.005727679 +5 mux_tree_tapbuf_size10_9_sram[2]:14 mux_tree_tapbuf_size10_9_sram[2]:13 0.00315625 +6 mux_tree_tapbuf_size10_9_sram[2]:15 mux_tree_tapbuf_size10_9_sram[2]:14 0.0045 +7 mux_tree_tapbuf_size10_9_sram[2]:17 mux_tree_tapbuf_size10_9_sram[2]:16 0.0045 +8 mux_tree_tapbuf_size10_9_sram[2]:16 mux_tree_tapbuf_size10_9_sram[2]:15 0.005383928 +9 mux_tree_tapbuf_size10_9_sram[2]:18 mux_tree_tapbuf_size10_9_sram[2]:17 0.001430804 +10 mux_tree_tapbuf_size10_9_sram[2]:10 mux_tree_tapbuf_size10_9_sram[2]:9 0.0045 +11 mux_tree_tapbuf_size10_9_sram[2]:9 mux_tree_tapbuf_size10_9_sram[2]:8 0.002084822 +12 mux_tree_tapbuf_size10_9_sram[2]:4 mux_left_track_9\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_9_sram[2]:5 mux_tree_tapbuf_size10_9_sram[2]:4 0.0045 +14 mux_tree_tapbuf_size10_9_sram[2]:12 mux_left_track_9\/mux_l3_in_0_:S 0.152 +15 mux_tree_tapbuf_size10_9_sram[2]:12 mux_tree_tapbuf_size10_9_sram[2]:11 0.004607143 +16 mux_tree_tapbuf_size10_9_sram[2]:11 mux_tree_tapbuf_size10_9_sram[2]:10 0.0003035715 +17 mux_tree_tapbuf_size10_9_sram[2]:13 mux_tree_tapbuf_size10_9_sram[2]:12 0.0003058036 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_7_ccff_tail[0] 0.001123774 //LENGTH 8.595 LUMPCC 0.0001562713 DR + +*CONN +*I mem_bottom_track_17\/FTB_20__71:X O *L 0 *C 51.785 37.400 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 57.220 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 *C 57.220 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 *C 57.485 39.100 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 *C 57.500 39.055 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 *C 57.500 37.445 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 *C 57.455 37.400 +*N mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 *C 51.823 37.400 + +*CAP +0 mem_bottom_track_17\/FTB_20__71:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 7.480004e-05 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 4.028956e-05 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 7.468866e-05 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 7.468866e-05 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.0003505176 +7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.0003505176 +8 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 prog_clk[0]:305 5.646621e-06 +9 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 prog_clk[0]:321 2.072323e-05 +10 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 prog_clk[0]:304 5.646621e-06 +11 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 prog_clk[0]:306 2.072323e-05 +12 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 prog_clk[0]:321 5.17658e-05 +13 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 prog_clk[0]:320 5.17658e-05 + +*RES +0 mem_bottom_track_17\/FTB_20__71:X mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 0.005029018 +2 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 0.0001274039 +5 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_7_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size12_1_sram[2] 0.003455615 //LENGTH 25.370 LUMPCC 0.0004156671 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 53.205 104.720 +*I mux_top_track_2\/mux_l3_in_1_:S I *L 0.00357 *C 50.020 101.660 +*I mux_top_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 55.300 99.960 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 48.015 109.820 +*N mux_tree_tapbuf_size12_1_sram[2]:4 *C 48.053 109.820 +*N mux_tree_tapbuf_size12_1_sram[2]:5 *C 52.395 109.820 +*N mux_tree_tapbuf_size12_1_sram[2]:6 *C 52.440 109.775 +*N mux_tree_tapbuf_size12_1_sram[2]:7 *C 55.263 99.960 +*N mux_tree_tapbuf_size12_1_sram[2]:8 *C 52.900 99.960 +*N mux_tree_tapbuf_size12_1_sram[2]:9 *C 52.900 99.620 +*N mux_tree_tapbuf_size12_1_sram[2]:10 *C 50.645 99.620 +*N mux_tree_tapbuf_size12_1_sram[2]:11 *C 50.600 99.665 +*N mux_tree_tapbuf_size12_1_sram[2]:12 *C 50.058 101.660 +*N mux_tree_tapbuf_size12_1_sram[2]:13 *C 50.555 101.660 +*N mux_tree_tapbuf_size12_1_sram[2]:14 *C 50.600 101.660 +*N mux_tree_tapbuf_size12_1_sram[2]:15 *C 50.600 103.983 +*N mux_tree_tapbuf_size12_1_sram[2]:16 *C 50.608 104.040 +*N mux_tree_tapbuf_size12_1_sram[2]:17 *C 52.433 104.040 +*N mux_tree_tapbuf_size12_1_sram[2]:18 *C 52.440 104.098 +*N mux_tree_tapbuf_size12_1_sram[2]:19 *C 52.440 104.720 +*N mux_tree_tapbuf_size12_1_sram[2]:20 *C 52.485 104.720 +*N mux_tree_tapbuf_size12_1_sram[2]:21 *C 53.168 104.720 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:S 1e-06 +2 mux_top_track_2\/mux_l3_in_0_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size12_1_sram[2]:4 0.000303747 +5 mux_tree_tapbuf_size12_1_sram[2]:5 0.000303747 +6 mux_tree_tapbuf_size12_1_sram[2]:6 0.0002515163 +7 mux_tree_tapbuf_size12_1_sram[2]:7 0.0001975169 +8 mux_tree_tapbuf_size12_1_sram[2]:8 0.0002241293 +9 mux_tree_tapbuf_size12_1_sram[2]:9 0.0001778428 +10 mux_tree_tapbuf_size12_1_sram[2]:10 0.0001512303 +11 mux_tree_tapbuf_size12_1_sram[2]:11 0.0001116262 +12 mux_tree_tapbuf_size12_1_sram[2]:12 4.019371e-05 +13 mux_tree_tapbuf_size12_1_sram[2]:13 4.019371e-05 +14 mux_tree_tapbuf_size12_1_sram[2]:14 0.0002867548 +15 mux_tree_tapbuf_size12_1_sram[2]:15 0.0001432743 +16 mux_tree_tapbuf_size12_1_sram[2]:16 0.000148459 +17 mux_tree_tapbuf_size12_1_sram[2]:17 0.000148459 +18 mux_tree_tapbuf_size12_1_sram[2]:18 4.280785e-05 +19 mux_tree_tapbuf_size12_1_sram[2]:19 0.0003283909 +20 mux_tree_tapbuf_size12_1_sram[2]:20 6.802945e-05 +21 mux_tree_tapbuf_size12_1_sram[2]:21 6.802945e-05 +22 mux_tree_tapbuf_size12_1_sram[2]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001355993 +23 mux_tree_tapbuf_size12_1_sram[2]:19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 2.195937e-05 +24 mux_tree_tapbuf_size12_1_sram[2]:19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001355993 +25 mux_tree_tapbuf_size12_1_sram[2]:18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 2.195937e-05 +26 mux_tree_tapbuf_size12_1_sram[2]:12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.379594e-05 +27 mux_tree_tapbuf_size12_1_sram[2]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.379594e-05 +28 mux_tree_tapbuf_size12_1_sram[2]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.639926e-05 +29 mux_tree_tapbuf_size12_1_sram[2]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 1.007972e-05 +30 mux_tree_tapbuf_size12_1_sram[2]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.639926e-05 +31 mux_tree_tapbuf_size12_1_sram[2]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 1.007972e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_1_sram[2]:21 0.152 +1 mux_tree_tapbuf_size12_1_sram[2]:12 mux_top_track_2\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size12_1_sram[2]:13 mux_tree_tapbuf_size12_1_sram[2]:12 0.0004441965 +3 mux_tree_tapbuf_size12_1_sram[2]:14 mux_tree_tapbuf_size12_1_sram[2]:13 0.0045 +4 mux_tree_tapbuf_size12_1_sram[2]:14 mux_tree_tapbuf_size12_1_sram[2]:11 0.00178125 +5 mux_tree_tapbuf_size12_1_sram[2]:10 mux_tree_tapbuf_size12_1_sram[2]:9 0.002013393 +6 mux_tree_tapbuf_size12_1_sram[2]:11 mux_tree_tapbuf_size12_1_sram[2]:10 0.0045 +7 mux_tree_tapbuf_size12_1_sram[2]:7 mux_top_track_2\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_1_sram[2]:5 mux_tree_tapbuf_size12_1_sram[2]:4 0.003877232 +9 mux_tree_tapbuf_size12_1_sram[2]:6 mux_tree_tapbuf_size12_1_sram[2]:5 0.0045 +10 mux_tree_tapbuf_size12_1_sram[2]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size12_1_sram[2]:20 mux_tree_tapbuf_size12_1_sram[2]:19 0.0045 +12 mux_tree_tapbuf_size12_1_sram[2]:19 mux_tree_tapbuf_size12_1_sram[2]:18 0.0005558036 +13 mux_tree_tapbuf_size12_1_sram[2]:19 mux_tree_tapbuf_size12_1_sram[2]:6 0.004513393 +14 mux_tree_tapbuf_size12_1_sram[2]:21 mux_tree_tapbuf_size12_1_sram[2]:20 0.000609375 +15 mux_tree_tapbuf_size12_1_sram[2]:15 mux_tree_tapbuf_size12_1_sram[2]:14 0.002073661 +16 mux_tree_tapbuf_size12_1_sram[2]:16 mux_tree_tapbuf_size12_1_sram[2]:15 0.00341 +17 mux_tree_tapbuf_size12_1_sram[2]:18 mux_tree_tapbuf_size12_1_sram[2]:17 0.00341 +18 mux_tree_tapbuf_size12_1_sram[2]:17 mux_tree_tapbuf_size12_1_sram[2]:16 0.0002859167 +19 mux_tree_tapbuf_size12_1_sram[2]:9 mux_tree_tapbuf_size12_1_sram[2]:8 0.0003035715 +20 mux_tree_tapbuf_size12_1_sram[2]:8 mux_tree_tapbuf_size12_1_sram[2]:7 0.002109375 + +*END + +*D_NET mux_tree_tapbuf_size12_4_sram[1] 0.005571401 //LENGTH 42.595 LUMPCC 0.000800614 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 77.585 20.740 +*I mux_bottom_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 83.160 23.415 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 84.355 17.340 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 88.680 28.560 +*I mux_bottom_track_1\/mux_l2_in_2_:S I *L 0.00357 *C 77.640 34.000 +*I mux_bottom_track_1\/mux_l2_in_3_:S I *L 0.00357 *C 85.000 34.680 +*N mux_tree_tapbuf_size12_4_sram[1]:6 *C 84.963 34.680 +*N mux_tree_tapbuf_size12_4_sram[1]:7 *C 84.640 34.680 +*N mux_tree_tapbuf_size12_4_sram[1]:8 *C 84.640 34.340 +*N mux_tree_tapbuf_size12_4_sram[1]:9 *C 77.678 34.000 +*N mux_tree_tapbuf_size12_4_sram[1]:10 *C 84.180 34.000 +*N mux_tree_tapbuf_size12_4_sram[1]:11 *C 84.180 34.340 +*N mux_tree_tapbuf_size12_4_sram[1]:12 *C 84.180 34.295 +*N mux_tree_tapbuf_size12_4_sram[1]:13 *C 88.642 28.560 +*N mux_tree_tapbuf_size12_4_sram[1]:14 *C 84.225 28.560 +*N mux_tree_tapbuf_size12_4_sram[1]:15 *C 84.180 28.560 +*N mux_tree_tapbuf_size12_4_sram[1]:16 *C 84.355 17.340 +*N mux_tree_tapbuf_size12_4_sram[1]:17 *C 84.180 17.340 +*N mux_tree_tapbuf_size12_4_sram[1]:18 *C 84.180 17.385 +*N mux_tree_tapbuf_size12_4_sram[1]:19 *C 84.180 23.460 +*N mux_tree_tapbuf_size12_4_sram[1]:20 *C 84.180 23.460 +*N mux_tree_tapbuf_size12_4_sram[1]:21 *C 84.180 23.120 +*N mux_tree_tapbuf_size12_4_sram[1]:22 *C 83.160 23.415 +*N mux_tree_tapbuf_size12_4_sram[1]:23 *C 83.123 23.120 +*N mux_tree_tapbuf_size12_4_sram[1]:24 *C 78.705 23.120 +*N mux_tree_tapbuf_size12_4_sram[1]:25 *C 78.660 23.075 +*N mux_tree_tapbuf_size12_4_sram[1]:26 *C 78.660 20.785 +*N mux_tree_tapbuf_size12_4_sram[1]:27 *C 78.615 20.740 +*N mux_tree_tapbuf_size12_4_sram[1]:28 *C 77.623 20.740 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:S 1e-06 +2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_track_1\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_track_1\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size12_4_sram[1]:6 4.426629e-05 +7 mux_tree_tapbuf_size12_4_sram[1]:7 7.147769e-05 +8 mux_tree_tapbuf_size12_4_sram[1]:8 7.36514e-05 +9 mux_tree_tapbuf_size12_4_sram[1]:9 0.0003973556 +10 mux_tree_tapbuf_size12_4_sram[1]:10 0.0004224126 +11 mux_tree_tapbuf_size12_4_sram[1]:11 7.149702e-05 +12 mux_tree_tapbuf_size12_4_sram[1]:12 0.0003096133 +13 mux_tree_tapbuf_size12_4_sram[1]:13 0.0002742411 +14 mux_tree_tapbuf_size12_4_sram[1]:14 0.0002742411 +15 mux_tree_tapbuf_size12_4_sram[1]:15 0.0005529358 +16 mux_tree_tapbuf_size12_4_sram[1]:16 5.161414e-05 +17 mux_tree_tapbuf_size12_4_sram[1]:17 5.446759e-05 +18 mux_tree_tapbuf_size12_4_sram[1]:18 0.000323168 +19 mux_tree_tapbuf_size12_4_sram[1]:19 0.0005616248 +20 mux_tree_tapbuf_size12_4_sram[1]:20 6.252504e-05 +21 mux_tree_tapbuf_size12_4_sram[1]:21 0.0001283024 +22 mux_tree_tapbuf_size12_4_sram[1]:22 4.208846e-05 +23 mux_tree_tapbuf_size12_4_sram[1]:23 0.0003581474 +24 mux_tree_tapbuf_size12_4_sram[1]:24 0.0002360129 +25 mux_tree_tapbuf_size12_4_sram[1]:25 0.0001482781 +26 mux_tree_tapbuf_size12_4_sram[1]:26 0.0001482781 +27 mux_tree_tapbuf_size12_4_sram[1]:27 7.929403e-05 +28 mux_tree_tapbuf_size12_4_sram[1]:28 7.929403e-05 +29 mux_tree_tapbuf_size12_4_sram[1]:19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.157258e-05 +30 mux_tree_tapbuf_size12_4_sram[1]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.088039e-05 +31 mux_tree_tapbuf_size12_4_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.157258e-05 +32 mux_tree_tapbuf_size12_4_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.197415e-06 +33 mux_tree_tapbuf_size12_4_sram[1]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.088039e-05 +34 mux_tree_tapbuf_size12_4_sram[1]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.197415e-06 +35 mux_tree_tapbuf_size12_4_sram[1]:24 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001338222 +36 mux_tree_tapbuf_size12_4_sram[1]:23 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001338222 +37 mux_tree_tapbuf_size12_4_sram[1]:19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 3.587294e-05 +38 mux_tree_tapbuf_size12_4_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.571545e-05 +39 mux_tree_tapbuf_size12_4_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 3.587294e-05 +40 mux_tree_tapbuf_size12_4_sram[1]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.177189e-07 +41 mux_tree_tapbuf_size12_4_sram[1]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.288519e-05 +42 mux_tree_tapbuf_size12_4_sram[1]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.143067e-06 +43 mux_tree_tapbuf_size12_4_sram[1]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 4.571545e-05 +44 mux_tree_tapbuf_size12_4_sram[1]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.288519e-05 +45 mux_tree_tapbuf_size12_4_sram[1]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.143067e-06 +46 mux_tree_tapbuf_size12_4_sram[1]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 2.177189e-07 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_4_sram[1]:28 0.152 +1 mux_tree_tapbuf_size12_4_sram[1]:20 mux_tree_tapbuf_size12_4_sram[1]:19 0.0045 +2 mux_tree_tapbuf_size12_4_sram[1]:19 mux_tree_tapbuf_size12_4_sram[1]:18 0.005424107 +3 mux_tree_tapbuf_size12_4_sram[1]:19 mux_tree_tapbuf_size12_4_sram[1]:15 0.004553571 +4 mux_tree_tapbuf_size12_4_sram[1]:14 mux_tree_tapbuf_size12_4_sram[1]:13 0.003944197 +5 mux_tree_tapbuf_size12_4_sram[1]:15 mux_tree_tapbuf_size12_4_sram[1]:14 0.0045 +6 mux_tree_tapbuf_size12_4_sram[1]:15 mux_tree_tapbuf_size12_4_sram[1]:12 0.005120536 +7 mux_tree_tapbuf_size12_4_sram[1]:13 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_4_sram[1]:24 mux_tree_tapbuf_size12_4_sram[1]:23 0.003944197 +9 mux_tree_tapbuf_size12_4_sram[1]:25 mux_tree_tapbuf_size12_4_sram[1]:24 0.0045 +10 mux_tree_tapbuf_size12_4_sram[1]:27 mux_tree_tapbuf_size12_4_sram[1]:26 0.0045 +11 mux_tree_tapbuf_size12_4_sram[1]:26 mux_tree_tapbuf_size12_4_sram[1]:25 0.002044643 +12 mux_tree_tapbuf_size12_4_sram[1]:28 mux_tree_tapbuf_size12_4_sram[1]:27 0.0008861608 +13 mux_tree_tapbuf_size12_4_sram[1]:6 mux_bottom_track_1\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size12_4_sram[1]:9 mux_bottom_track_1\/mux_l2_in_2_:S 0.152 +15 mux_tree_tapbuf_size12_4_sram[1]:11 mux_tree_tapbuf_size12_4_sram[1]:10 0.0003035715 +16 mux_tree_tapbuf_size12_4_sram[1]:11 mux_tree_tapbuf_size12_4_sram[1]:8 0.0004107143 +17 mux_tree_tapbuf_size12_4_sram[1]:12 mux_tree_tapbuf_size12_4_sram[1]:11 0.0045 +18 mux_tree_tapbuf_size12_4_sram[1]:22 mux_bottom_track_1\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size12_4_sram[1]:17 mux_tree_tapbuf_size12_4_sram[1]:16 9.510869e-05 +20 mux_tree_tapbuf_size12_4_sram[1]:18 mux_tree_tapbuf_size12_4_sram[1]:17 0.0045 +21 mux_tree_tapbuf_size12_4_sram[1]:16 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +22 mux_tree_tapbuf_size12_4_sram[1]:10 mux_tree_tapbuf_size12_4_sram[1]:9 0.005805804 +23 mux_tree_tapbuf_size12_4_sram[1]:23 mux_tree_tapbuf_size12_4_sram[1]:22 0.0001271552 +24 mux_tree_tapbuf_size12_4_sram[1]:23 mux_tree_tapbuf_size12_4_sram[1]:21 0.0009441964 +25 mux_tree_tapbuf_size12_4_sram[1]:21 mux_tree_tapbuf_size12_4_sram[1]:20 0.0003035715 +26 mux_tree_tapbuf_size12_4_sram[1]:8 mux_tree_tapbuf_size12_4_sram[1]:7 0.0003035715 +27 mux_tree_tapbuf_size12_4_sram[1]:7 mux_tree_tapbuf_size12_4_sram[1]:6 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size12_7_sram[0] 0.01064105 //LENGTH 77.480 LUMPCC 0.0005059719 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 37.565 91.460 +*I mux_left_track_3\/mux_l1_in_4_:S I *L 0.00357 *C 22.180 94.520 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 26.855 93.500 +*I mux_left_track_3\/mux_l1_in_2_:S I *L 0.00357 *C 58.980 88.400 +*I mux_left_track_3\/mux_l1_in_3_:S I *L 0.00357 *C 66.340 96.560 +*I mux_left_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 70.480 104.720 +*I mux_left_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 67.720 99.205 +*N mux_tree_tapbuf_size12_7_sram[0]:7 *C 70.443 104.720 +*N mux_tree_tapbuf_size12_7_sram[0]:8 *C 67.665 104.720 +*N mux_tree_tapbuf_size12_7_sram[0]:9 *C 67.620 104.675 +*N mux_tree_tapbuf_size12_7_sram[0]:10 *C 67.620 99.325 +*N mux_tree_tapbuf_size12_7_sram[0]:11 *C 67.633 99.265 +*N mux_tree_tapbuf_size12_7_sram[0]:12 *C 66.700 99.280 +*N mux_tree_tapbuf_size12_7_sram[0]:13 *C 66.700 98.940 +*N mux_tree_tapbuf_size12_7_sram[0]:14 *C 63.525 98.940 +*N mux_tree_tapbuf_size12_7_sram[0]:15 *C 63.480 98.895 +*N mux_tree_tapbuf_size12_7_sram[0]:16 *C 66.303 96.560 +*N mux_tree_tapbuf_size12_7_sram[0]:17 *C 63.525 96.560 +*N mux_tree_tapbuf_size12_7_sram[0]:18 *C 63.480 96.560 +*N mux_tree_tapbuf_size12_7_sram[0]:19 *C 63.480 93.545 +*N mux_tree_tapbuf_size12_7_sram[0]:20 *C 63.435 93.500 +*N mux_tree_tapbuf_size12_7_sram[0]:21 *C 58.925 93.500 +*N mux_tree_tapbuf_size12_7_sram[0]:22 *C 58.880 93.455 +*N mux_tree_tapbuf_size12_7_sram[0]:23 *C 58.880 88.400 +*N mux_tree_tapbuf_size12_7_sram[0]:24 *C 58.880 88.445 +*N mux_tree_tapbuf_size12_7_sram[0]:25 *C 58.880 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:26 *C 58.835 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:27 *C 26.818 93.500 +*N mux_tree_tapbuf_size12_7_sram[0]:28 *C 25.300 93.500 +*N mux_tree_tapbuf_size12_7_sram[0]:29 *C 22.218 94.520 +*N mux_tree_tapbuf_size12_7_sram[0]:30 *C 25.255 94.520 +*N mux_tree_tapbuf_size12_7_sram[0]:31 *C 25.300 94.475 +*N mux_tree_tapbuf_size12_7_sram[0]:32 *C 25.300 93.205 +*N mux_tree_tapbuf_size12_7_sram[0]:33 *C 25.300 93.160 +*N mux_tree_tapbuf_size12_7_sram[0]:34 *C 31.235 93.160 +*N mux_tree_tapbuf_size12_7_sram[0]:35 *C 31.280 93.115 +*N mux_tree_tapbuf_size12_7_sram[0]:36 *C 31.280 91.858 +*N mux_tree_tapbuf_size12_7_sram[0]:37 *C 31.288 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:38 *C 37.253 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:39 *C 37.260 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:40 *C 37.328 91.800 +*N mux_tree_tapbuf_size12_7_sram[0]:41 *C 37.565 91.460 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_3\/mux_l1_in_4_:S 1e-06 +2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_3\/mux_l1_in_2_:S 1e-06 +4 mux_left_track_3\/mux_l1_in_3_:S 1e-06 +5 mux_left_track_3\/mux_l1_in_1_:S 1e-06 +6 mux_left_track_3\/mux_l1_in_0_:S 1e-06 +7 mux_tree_tapbuf_size12_7_sram[0]:7 0.0001996524 +8 mux_tree_tapbuf_size12_7_sram[0]:8 0.0001996524 +9 mux_tree_tapbuf_size12_7_sram[0]:9 0.0004184308 +10 mux_tree_tapbuf_size12_7_sram[0]:10 0.0004184308 +11 mux_tree_tapbuf_size12_7_sram[0]:11 7.504816e-05 +12 mux_tree_tapbuf_size12_7_sram[0]:12 0.0001030745 +13 mux_tree_tapbuf_size12_7_sram[0]:13 0.0002015664 +14 mux_tree_tapbuf_size12_7_sram[0]:14 0.0001735401 +15 mux_tree_tapbuf_size12_7_sram[0]:15 0.0001616579 +16 mux_tree_tapbuf_size12_7_sram[0]:16 0.0001966729 +17 mux_tree_tapbuf_size12_7_sram[0]:17 0.0001966729 +18 mux_tree_tapbuf_size12_7_sram[0]:18 0.0003714738 +19 mux_tree_tapbuf_size12_7_sram[0]:19 0.0001761298 +20 mux_tree_tapbuf_size12_7_sram[0]:20 0.0002881888 +21 mux_tree_tapbuf_size12_7_sram[0]:21 0.0002881888 +22 mux_tree_tapbuf_size12_7_sram[0]:22 0.0001177368 +23 mux_tree_tapbuf_size12_7_sram[0]:23 3.103814e-05 +24 mux_tree_tapbuf_size12_7_sram[0]:24 0.0002151831 +25 mux_tree_tapbuf_size12_7_sram[0]:25 0.0003659708 +26 mux_tree_tapbuf_size12_7_sram[0]:26 0.001516155 +27 mux_tree_tapbuf_size12_7_sram[0]:27 0.0001355385 +28 mux_tree_tapbuf_size12_7_sram[0]:28 0.0001639631 +29 mux_tree_tapbuf_size12_7_sram[0]:29 0.0002602076 +30 mux_tree_tapbuf_size12_7_sram[0]:30 0.0002602076 +31 mux_tree_tapbuf_size12_7_sram[0]:31 0.000110056 +32 mux_tree_tapbuf_size12_7_sram[0]:32 0.000110056 +33 mux_tree_tapbuf_size12_7_sram[0]:33 0.0004078285 +34 mux_tree_tapbuf_size12_7_sram[0]:34 0.000379404 +35 mux_tree_tapbuf_size12_7_sram[0]:35 9.42097e-05 +36 mux_tree_tapbuf_size12_7_sram[0]:36 9.42097e-05 +37 mux_tree_tapbuf_size12_7_sram[0]:37 0.0003772763 +38 mux_tree_tapbuf_size12_7_sram[0]:38 0.0003772763 +39 mux_tree_tapbuf_size12_7_sram[0]:39 3.676006e-05 +40 mux_tree_tapbuf_size12_7_sram[0]:40 0.001547267 +41 mux_tree_tapbuf_size12_7_sram[0]:41 5.93532e-05 +42 mux_tree_tapbuf_size12_7_sram[0]:18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.036074e-05 +43 mux_tree_tapbuf_size12_7_sram[0]:20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.80396e-05 +44 mux_tree_tapbuf_size12_7_sram[0]:19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.036074e-05 +45 mux_tree_tapbuf_size12_7_sram[0]:21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.80396e-05 +46 mux_tree_tapbuf_size12_7_sram[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.384357e-05 +47 mux_tree_tapbuf_size12_7_sram[0]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.530275e-05 +48 mux_tree_tapbuf_size12_7_sram[0]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.530275e-05 +49 mux_tree_tapbuf_size12_7_sram[0]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.384357e-05 +50 mux_tree_tapbuf_size12_7_sram[0]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.514376e-05 +51 mux_tree_tapbuf_size12_7_sram[0]:17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.514376e-05 +52 mux_tree_tapbuf_size12_7_sram[0]:40 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 1.97894e-05 +53 mux_tree_tapbuf_size12_7_sram[0]:38 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.050612e-05 +54 mux_tree_tapbuf_size12_7_sram[0]:37 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.050612e-05 +55 mux_tree_tapbuf_size12_7_sram[0]:26 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 1.97894e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_7_sram[0]:41 0.152 +1 mux_tree_tapbuf_size12_7_sram[0]:16 mux_left_track_3\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size12_7_sram[0]:17 mux_tree_tapbuf_size12_7_sram[0]:16 0.00247991 +3 mux_tree_tapbuf_size12_7_sram[0]:18 mux_tree_tapbuf_size12_7_sram[0]:17 0.0045 +4 mux_tree_tapbuf_size12_7_sram[0]:18 mux_tree_tapbuf_size12_7_sram[0]:15 0.002084821 +5 mux_tree_tapbuf_size12_7_sram[0]:20 mux_tree_tapbuf_size12_7_sram[0]:19 0.0045 +6 mux_tree_tapbuf_size12_7_sram[0]:19 mux_tree_tapbuf_size12_7_sram[0]:18 0.002691964 +7 mux_tree_tapbuf_size12_7_sram[0]:21 mux_tree_tapbuf_size12_7_sram[0]:20 0.004026786 +8 mux_tree_tapbuf_size12_7_sram[0]:22 mux_tree_tapbuf_size12_7_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size12_7_sram[0]:7 mux_left_track_3\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size12_7_sram[0]:8 mux_tree_tapbuf_size12_7_sram[0]:7 0.002479911 +11 mux_tree_tapbuf_size12_7_sram[0]:9 mux_tree_tapbuf_size12_7_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size12_7_sram[0]:11 mux_tree_tapbuf_size12_7_sram[0]:10 0.0045 +13 mux_tree_tapbuf_size12_7_sram[0]:11 mux_left_track_3\/mux_l1_in_0_:S 0.152 +14 mux_tree_tapbuf_size12_7_sram[0]:10 mux_tree_tapbuf_size12_7_sram[0]:9 0.004776786 +15 mux_tree_tapbuf_size12_7_sram[0]:40 mux_tree_tapbuf_size12_7_sram[0]:39 0.0045 +16 mux_tree_tapbuf_size12_7_sram[0]:40 mux_tree_tapbuf_size12_7_sram[0]:26 0.01920313 +17 mux_tree_tapbuf_size12_7_sram[0]:39 mux_tree_tapbuf_size12_7_sram[0]:38 0.00341 +18 mux_tree_tapbuf_size12_7_sram[0]:38 mux_tree_tapbuf_size12_7_sram[0]:37 0.0009345167 +19 mux_tree_tapbuf_size12_7_sram[0]:36 mux_tree_tapbuf_size12_7_sram[0]:35 0.001122768 +20 mux_tree_tapbuf_size12_7_sram[0]:37 mux_tree_tapbuf_size12_7_sram[0]:36 0.00341 +21 mux_tree_tapbuf_size12_7_sram[0]:34 mux_tree_tapbuf_size12_7_sram[0]:33 0.005299107 +22 mux_tree_tapbuf_size12_7_sram[0]:35 mux_tree_tapbuf_size12_7_sram[0]:34 0.0045 +23 mux_tree_tapbuf_size12_7_sram[0]:26 mux_tree_tapbuf_size12_7_sram[0]:25 0.0045 +24 mux_tree_tapbuf_size12_7_sram[0]:25 mux_tree_tapbuf_size12_7_sram[0]:24 0.002995536 +25 mux_tree_tapbuf_size12_7_sram[0]:25 mux_tree_tapbuf_size12_7_sram[0]:22 0.001477679 +26 mux_tree_tapbuf_size12_7_sram[0]:27 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +27 mux_tree_tapbuf_size12_7_sram[0]:41 mux_tree_tapbuf_size12_7_sram[0]:40 0.0001847826 +28 mux_tree_tapbuf_size12_7_sram[0]:33 mux_tree_tapbuf_size12_7_sram[0]:32 0.0045 +29 mux_tree_tapbuf_size12_7_sram[0]:33 mux_tree_tapbuf_size12_7_sram[0]:28 0.0003035715 +30 mux_tree_tapbuf_size12_7_sram[0]:32 mux_tree_tapbuf_size12_7_sram[0]:31 0.001133929 +31 mux_tree_tapbuf_size12_7_sram[0]:30 mux_tree_tapbuf_size12_7_sram[0]:29 0.002712054 +32 mux_tree_tapbuf_size12_7_sram[0]:31 mux_tree_tapbuf_size12_7_sram[0]:30 0.0045 +33 mux_tree_tapbuf_size12_7_sram[0]:29 mux_left_track_3\/mux_l1_in_4_:S 0.152 +34 mux_tree_tapbuf_size12_7_sram[0]:14 mux_tree_tapbuf_size12_7_sram[0]:13 0.002834822 +35 mux_tree_tapbuf_size12_7_sram[0]:15 mux_tree_tapbuf_size12_7_sram[0]:14 0.0045 +36 mux_tree_tapbuf_size12_7_sram[0]:23 mux_left_track_3\/mux_l1_in_2_:S 0.152 +37 mux_tree_tapbuf_size12_7_sram[0]:24 mux_tree_tapbuf_size12_7_sram[0]:23 0.0045 +38 mux_tree_tapbuf_size12_7_sram[0]:28 mux_tree_tapbuf_size12_7_sram[0]:27 0.001354911 +39 mux_tree_tapbuf_size12_7_sram[0]:13 mux_tree_tapbuf_size12_7_sram[0]:12 0.0003035715 +40 mux_tree_tapbuf_size12_7_sram[0]:12 mux_tree_tapbuf_size12_7_sram[0]:11 0.0008325893 + +*END + +*D_NET mux_tree_tapbuf_size16_3_sram[1] 0.01615777 //LENGTH 108.217 LUMPCC 0.004087215 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 48.605 93.500 +*I mux_left_track_5\/mux_l2_in_3_:S I *L 0.00357 *C 44.720 91.120 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 47.480 88.740 +*I mux_left_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 40.580 88.740 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 25.475 47.940 +*I mux_left_track_5\/mux_l2_in_5_:S I *L 0.00357 *C 21.060 90.780 +*I mux_left_track_5\/mux_l2_in_4_:S I *L 0.00357 *C 23.560 91.120 +*I mux_left_track_5\/mux_l2_in_7_:S I *L 0.00357 *C 18.040 94.135 +*I mux_left_track_5\/mux_l2_in_6_:S I *L 0.00357 *C 14.160 95.880 +*I mux_left_track_5\/mux_l2_in_2_:S I *L 0.00357 *C 49.320 83.300 +*N mux_tree_tapbuf_size16_3_sram[1]:10 *C 49.282 83.300 +*N mux_tree_tapbuf_size16_3_sram[1]:11 *C 47.425 83.300 +*N mux_tree_tapbuf_size16_3_sram[1]:12 *C 47.380 83.345 +*N mux_tree_tapbuf_size16_3_sram[1]:13 *C 14.198 95.880 +*N mux_tree_tapbuf_size16_3_sram[1]:14 *C 16.515 95.880 +*N mux_tree_tapbuf_size16_3_sram[1]:15 *C 16.560 95.835 +*N mux_tree_tapbuf_size16_3_sram[1]:16 *C 16.560 94.565 +*N mux_tree_tapbuf_size16_3_sram[1]:17 *C 16.605 94.520 +*N mux_tree_tapbuf_size16_3_sram[1]:18 *C 18.040 94.520 +*N mux_tree_tapbuf_size16_3_sram[1]:19 *C 18.060 93.840 +*N mux_tree_tapbuf_size16_3_sram[1]:20 *C 18.040 94.135 +*N mux_tree_tapbuf_size16_3_sram[1]:21 *C 18.115 93.840 +*N mux_tree_tapbuf_size16_3_sram[1]:22 *C 20.655 93.840 +*N mux_tree_tapbuf_size16_3_sram[1]:23 *C 20.700 93.795 +*N mux_tree_tapbuf_size16_3_sram[1]:24 *C 23.560 91.120 +*N mux_tree_tapbuf_size16_3_sram[1]:25 *C 23.460 90.780 +*N mux_tree_tapbuf_size16_3_sram[1]:26 *C 21.098 90.780 +*N mux_tree_tapbuf_size16_3_sram[1]:27 *C 20.723 90.780 +*N mux_tree_tapbuf_size16_3_sram[1]:28 *C 20.700 90.780 +*N mux_tree_tapbuf_size16_3_sram[1]:29 *C 20.700 89.138 +*N mux_tree_tapbuf_size16_3_sram[1]:30 *C 20.707 89.080 +*N mux_tree_tapbuf_size16_3_sram[1]:31 *C 25.050 47.940 +*N mux_tree_tapbuf_size16_3_sram[1]:32 *C 25.475 47.940 +*N mux_tree_tapbuf_size16_3_sram[1]:33 *C 25.760 47.940 +*N mux_tree_tapbuf_size16_3_sram[1]:34 *C 25.760 47.940 +*N mux_tree_tapbuf_size16_3_sram[1]:35 *C 25.758 47.940 +*N mux_tree_tapbuf_size16_3_sram[1]:36 *C 25.760 47.948 +*N mux_tree_tapbuf_size16_3_sram[1]:37 *C 25.760 89.073 +*N mux_tree_tapbuf_size16_3_sram[1]:38 *C 25.760 89.080 +*N mux_tree_tapbuf_size16_3_sram[1]:39 *C 39.553 89.080 +*N mux_tree_tapbuf_size16_3_sram[1]:40 *C 39.560 89.080 +*N mux_tree_tapbuf_size16_3_sram[1]:41 *C 39.560 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:42 *C 39.605 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:43 *C 40.480 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:44 *C 40.492 88.718 +*N mux_tree_tapbuf_size16_3_sram[1]:45 *C 40.480 88.400 +*N mux_tree_tapbuf_size16_3_sram[1]:46 *C 42.320 88.400 +*N mux_tree_tapbuf_size16_3_sram[1]:47 *C 42.320 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:48 *C 47.393 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:49 *C 47.380 88.740 +*N mux_tree_tapbuf_size16_3_sram[1]:50 *C 44.758 91.120 +*N mux_tree_tapbuf_size16_3_sram[1]:51 *C 47.335 91.120 +*N mux_tree_tapbuf_size16_3_sram[1]:52 *C 47.380 91.120 +*N mux_tree_tapbuf_size16_3_sram[1]:53 *C 47.380 93.455 +*N mux_tree_tapbuf_size16_3_sram[1]:54 *C 47.425 93.500 +*N mux_tree_tapbuf_size16_3_sram[1]:55 *C 48.568 93.500 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_5\/mux_l2_in_3_:S 1e-06 +2 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +3 mux_left_track_5\/mux_l2_in_1_:S 1e-06 +4 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_left_track_5\/mux_l2_in_5_:S 1e-06 +6 mux_left_track_5\/mux_l2_in_4_:S 1e-06 +7 mux_left_track_5\/mux_l2_in_7_:S 1e-06 +8 mux_left_track_5\/mux_l2_in_6_:S 1e-06 +9 mux_left_track_5\/mux_l2_in_2_:S 1e-06 +10 mux_tree_tapbuf_size16_3_sram[1]:10 0.0001894406 +11 mux_tree_tapbuf_size16_3_sram[1]:11 0.0001894406 +12 mux_tree_tapbuf_size16_3_sram[1]:12 0.0003133757 +13 mux_tree_tapbuf_size16_3_sram[1]:13 0.0001995963 +14 mux_tree_tapbuf_size16_3_sram[1]:14 0.0001995963 +15 mux_tree_tapbuf_size16_3_sram[1]:15 9.056982e-05 +16 mux_tree_tapbuf_size16_3_sram[1]:16 9.056982e-05 +17 mux_tree_tapbuf_size16_3_sram[1]:17 0.0001206968 +18 mux_tree_tapbuf_size16_3_sram[1]:18 0.0001458954 +19 mux_tree_tapbuf_size16_3_sram[1]:19 3.115024e-05 +20 mux_tree_tapbuf_size16_3_sram[1]:20 0.0001058098 +21 mux_tree_tapbuf_size16_3_sram[1]:21 0.0002449308 +22 mux_tree_tapbuf_size16_3_sram[1]:22 0.0002074922 +23 mux_tree_tapbuf_size16_3_sram[1]:23 0.0002085597 +24 mux_tree_tapbuf_size16_3_sram[1]:24 5.670432e-05 +25 mux_tree_tapbuf_size16_3_sram[1]:25 0.0001941964 +26 mux_tree_tapbuf_size16_3_sram[1]:26 0.0002143208 +27 mux_tree_tapbuf_size16_3_sram[1]:27 4.808682e-05 +28 mux_tree_tapbuf_size16_3_sram[1]:28 0.0003561336 +29 mux_tree_tapbuf_size16_3_sram[1]:29 0.0001163249 +30 mux_tree_tapbuf_size16_3_sram[1]:30 0.0001628413 +31 mux_tree_tapbuf_size16_3_sram[1]:31 0.0001176871 +32 mux_tree_tapbuf_size16_3_sram[1]:32 5.015699e-05 +33 mux_tree_tapbuf_size16_3_sram[1]:33 5.599315e-05 +34 mux_tree_tapbuf_size16_3_sram[1]:34 3.972187e-05 +35 mux_tree_tapbuf_size16_3_sram[1]:35 0.0001176871 +36 mux_tree_tapbuf_size16_3_sram[1]:36 0.002134905 +37 mux_tree_tapbuf_size16_3_sram[1]:37 0.002134905 +38 mux_tree_tapbuf_size16_3_sram[1]:38 0.0006390099 +39 mux_tree_tapbuf_size16_3_sram[1]:39 0.0004761686 +40 mux_tree_tapbuf_size16_3_sram[1]:40 5.706e-05 +41 mux_tree_tapbuf_size16_3_sram[1]:41 5.298674e-05 +42 mux_tree_tapbuf_size16_3_sram[1]:42 5.068196e-05 +43 mux_tree_tapbuf_size16_3_sram[1]:43 6.322817e-05 +44 mux_tree_tapbuf_size16_3_sram[1]:44 3.41659e-05 +45 mux_tree_tapbuf_size16_3_sram[1]:45 0.0001637193 +46 mux_tree_tapbuf_size16_3_sram[1]:46 0.0001689976 +47 mux_tree_tapbuf_size16_3_sram[1]:47 0.0003564054 +48 mux_tree_tapbuf_size16_3_sram[1]:48 0.0003295074 +49 mux_tree_tapbuf_size16_3_sram[1]:49 0.0004796046 +50 mux_tree_tapbuf_size16_3_sram[1]:50 0.0002058573 +51 mux_tree_tapbuf_size16_3_sram[1]:51 0.0002058573 +52 mux_tree_tapbuf_size16_3_sram[1]:52 0.0003099173 +53 mux_tree_tapbuf_size16_3_sram[1]:53 0.0001425959 +54 mux_tree_tapbuf_size16_3_sram[1]:54 9.399964e-05 +55 mux_tree_tapbuf_size16_3_sram[1]:55 9.399964e-05 +56 mux_tree_tapbuf_size16_3_sram[1]:37 chanx_left_in[10]:26 0.0002504028 +57 mux_tree_tapbuf_size16_3_sram[1]:36 chanx_left_in[10]:27 0.0002504028 +58 mux_tree_tapbuf_size16_3_sram[1]:30 chanx_left_in[13]:33 0.0002804286 +59 mux_tree_tapbuf_size16_3_sram[1]:38 chanx_left_in[13]:32 0.0002804286 +60 mux_tree_tapbuf_size16_3_sram[1]:38 chanx_left_in[13]:33 0.00076501 +61 mux_tree_tapbuf_size16_3_sram[1]:39 chanx_left_in[13]:32 0.00076501 +62 mux_tree_tapbuf_size16_3_sram[1]:30 chanx_left_in[14]:31 0.0001051847 +63 mux_tree_tapbuf_size16_3_sram[1]:38 chanx_left_in[14]:30 0.0001051847 +64 mux_tree_tapbuf_size16_3_sram[1]:38 chanx_left_in[14]:31 0.0001614058 +65 mux_tree_tapbuf_size16_3_sram[1]:37 chanx_left_in[14]:28 7.999596e-07 +66 mux_tree_tapbuf_size16_3_sram[1]:36 chanx_left_in[14]:10 7.999596e-07 +67 mux_tree_tapbuf_size16_3_sram[1]:39 chanx_left_in[14]:30 0.0001614058 +68 mux_tree_tapbuf_size16_3_sram[1]:37 chanx_left_in[0]:9 0.0002104896 +69 mux_tree_tapbuf_size16_3_sram[1]:37 chanx_left_in[0]:19 7.650271e-05 +70 mux_tree_tapbuf_size16_3_sram[1]:35 chanx_left_in[0]:17 4.034823e-06 +71 mux_tree_tapbuf_size16_3_sram[1]:36 chanx_left_in[0]:10 0.0002104896 +72 mux_tree_tapbuf_size16_3_sram[1]:36 chanx_left_in[0]:18 7.650271e-05 +73 mux_tree_tapbuf_size16_3_sram[1]:31 chanx_left_in[0]:16 4.034823e-06 +74 mux_tree_tapbuf_size16_3_sram[1]:44 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.763181e-06 +75 mux_tree_tapbuf_size16_3_sram[1]:48 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001436618 +76 mux_tree_tapbuf_size16_3_sram[1]:42 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.281897e-05 +77 mux_tree_tapbuf_size16_3_sram[1]:43 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.281897e-05 +78 mux_tree_tapbuf_size16_3_sram[1]:43 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.763181e-06 +79 mux_tree_tapbuf_size16_3_sram[1]:45 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.104219e-06 +80 mux_tree_tapbuf_size16_3_sram[1]:46 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.104219e-06 +81 mux_tree_tapbuf_size16_3_sram[1]:47 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001436618 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size16_3_sram[1]:55 0.152 +1 mux_tree_tapbuf_size16_3_sram[1]:10 mux_left_track_5\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size16_3_sram[1]:11 mux_tree_tapbuf_size16_3_sram[1]:10 0.001658482 +3 mux_tree_tapbuf_size16_3_sram[1]:12 mux_tree_tapbuf_size16_3_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size16_3_sram[1]:26 mux_left_track_5\/mux_l2_in_5_:S 0.152 +5 mux_tree_tapbuf_size16_3_sram[1]:26 mux_tree_tapbuf_size16_3_sram[1]:25 0.002109375 +6 mux_tree_tapbuf_size16_3_sram[1]:20 mux_left_track_5\/mux_l2_in_7_:S 0.152 +7 mux_tree_tapbuf_size16_3_sram[1]:20 mux_tree_tapbuf_size16_3_sram[1]:19 0.0002633929 +8 mux_tree_tapbuf_size16_3_sram[1]:20 mux_tree_tapbuf_size16_3_sram[1]:18 0.00034375 +9 mux_tree_tapbuf_size16_3_sram[1]:29 mux_tree_tapbuf_size16_3_sram[1]:28 0.001466518 +10 mux_tree_tapbuf_size16_3_sram[1]:30 mux_tree_tapbuf_size16_3_sram[1]:29 0.00341 +11 mux_tree_tapbuf_size16_3_sram[1]:44 mux_left_track_5\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size16_3_sram[1]:44 mux_tree_tapbuf_size16_3_sram[1]:43 1.116072e-05 +13 mux_tree_tapbuf_size16_3_sram[1]:48 mux_left_track_5\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size16_3_sram[1]:48 mux_tree_tapbuf_size16_3_sram[1]:47 0.004529018 +15 mux_tree_tapbuf_size16_3_sram[1]:17 mux_tree_tapbuf_size16_3_sram[1]:16 0.0045 +16 mux_tree_tapbuf_size16_3_sram[1]:16 mux_tree_tapbuf_size16_3_sram[1]:15 0.001133929 +17 mux_tree_tapbuf_size16_3_sram[1]:14 mux_tree_tapbuf_size16_3_sram[1]:13 0.002069197 +18 mux_tree_tapbuf_size16_3_sram[1]:15 mux_tree_tapbuf_size16_3_sram[1]:14 0.0045 +19 mux_tree_tapbuf_size16_3_sram[1]:13 mux_left_track_5\/mux_l2_in_6_:S 0.152 +20 mux_tree_tapbuf_size16_3_sram[1]:22 mux_tree_tapbuf_size16_3_sram[1]:21 0.002267857 +21 mux_tree_tapbuf_size16_3_sram[1]:23 mux_tree_tapbuf_size16_3_sram[1]:22 0.0045 +22 mux_tree_tapbuf_size16_3_sram[1]:24 mux_left_track_5\/mux_l2_in_4_:S 0.152 +23 mux_tree_tapbuf_size16_3_sram[1]:27 mux_tree_tapbuf_size16_3_sram[1]:26 0.0002038044 +24 mux_tree_tapbuf_size16_3_sram[1]:28 mux_tree_tapbuf_size16_3_sram[1]:27 0.0045 +25 mux_tree_tapbuf_size16_3_sram[1]:28 mux_tree_tapbuf_size16_3_sram[1]:23 0.002691964 +26 mux_tree_tapbuf_size16_3_sram[1]:38 mux_tree_tapbuf_size16_3_sram[1]:37 0.00341 +27 mux_tree_tapbuf_size16_3_sram[1]:38 mux_tree_tapbuf_size16_3_sram[1]:30 0.0007915583 +28 mux_tree_tapbuf_size16_3_sram[1]:37 mux_tree_tapbuf_size16_3_sram[1]:36 0.006442917 +29 mux_tree_tapbuf_size16_3_sram[1]:35 mux_tree_tapbuf_size16_3_sram[1]:34 0.00341 +30 mux_tree_tapbuf_size16_3_sram[1]:35 mux_tree_tapbuf_size16_3_sram[1]:31 0.0001039141 +31 mux_tree_tapbuf_size16_3_sram[1]:36 mux_tree_tapbuf_size16_3_sram[1]:35 0.00341 +32 mux_tree_tapbuf_size16_3_sram[1]:34 mux_tree_tapbuf_size16_3_sram[1]:33 0.0045 +33 mux_tree_tapbuf_size16_3_sram[1]:33 mux_tree_tapbuf_size16_3_sram[1]:32 0.0001548913 +34 mux_tree_tapbuf_size16_3_sram[1]:32 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +35 mux_tree_tapbuf_size16_3_sram[1]:40 mux_tree_tapbuf_size16_3_sram[1]:39 0.00341 +36 mux_tree_tapbuf_size16_3_sram[1]:39 mux_tree_tapbuf_size16_3_sram[1]:38 0.002160825 +37 mux_tree_tapbuf_size16_3_sram[1]:42 mux_tree_tapbuf_size16_3_sram[1]:41 0.0045 +38 mux_tree_tapbuf_size16_3_sram[1]:41 mux_tree_tapbuf_size16_3_sram[1]:40 0.0001634615 +39 mux_tree_tapbuf_size16_3_sram[1]:51 mux_tree_tapbuf_size16_3_sram[1]:50 0.00230134 +40 mux_tree_tapbuf_size16_3_sram[1]:52 mux_tree_tapbuf_size16_3_sram[1]:51 0.0045 +41 mux_tree_tapbuf_size16_3_sram[1]:52 mux_tree_tapbuf_size16_3_sram[1]:49 0.002125 +42 mux_tree_tapbuf_size16_3_sram[1]:50 mux_left_track_5\/mux_l2_in_3_:S 0.152 +43 mux_tree_tapbuf_size16_3_sram[1]:54 mux_tree_tapbuf_size16_3_sram[1]:53 0.0045 +44 mux_tree_tapbuf_size16_3_sram[1]:53 mux_tree_tapbuf_size16_3_sram[1]:52 0.002084821 +45 mux_tree_tapbuf_size16_3_sram[1]:55 mux_tree_tapbuf_size16_3_sram[1]:54 0.001020089 +46 mux_tree_tapbuf_size16_3_sram[1]:49 mux_tree_tapbuf_size16_3_sram[1]:48 0.0045 +47 mux_tree_tapbuf_size16_3_sram[1]:49 mux_tree_tapbuf_size16_3_sram[1]:12 0.004816965 +48 mux_tree_tapbuf_size16_3_sram[1]:18 mux_tree_tapbuf_size16_3_sram[1]:17 0.00128125 +49 mux_tree_tapbuf_size16_3_sram[1]:21 mux_tree_tapbuf_size16_3_sram[1]:20 0.0002633929 +50 mux_tree_tapbuf_size16_3_sram[1]:25 mux_tree_tapbuf_size16_3_sram[1]:24 0.0003035715 +51 mux_tree_tapbuf_size16_3_sram[1]:43 mux_tree_tapbuf_size16_3_sram[1]:42 0.0007812501 +52 mux_tree_tapbuf_size16_3_sram[1]:45 mux_tree_tapbuf_size16_3_sram[1]:44 0.0002834822 +53 mux_tree_tapbuf_size16_3_sram[1]:46 mux_tree_tapbuf_size16_3_sram[1]:45 0.001642857 +54 mux_tree_tapbuf_size16_3_sram[1]:47 mux_tree_tapbuf_size16_3_sram[1]:46 0.0003035715 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006330541 //LENGTH 4.320 LUMPCC 0.0002971 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_1_:X O *L 0 *C 64.225 118.660 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 68.255 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 68.218 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 64.263 118.660 + +*CAP +0 mux_top_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000166977 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000166977 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00014855 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00014855 + +*RES +0 mux_top_track_0\/mux_l1_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00353125 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007716113 //LENGTH 5.710 LUMPCC 0.0001091865 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_0_:X O *L 0 *C 56.865 106.760 +*I mux_top_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.040 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.040 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.040 101.705 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.040 106.715 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.040 106.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 56.865 106.760 + +*CAP +0 mux_top_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.406531e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002554183 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002554183 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.992488e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.559809e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:20 5.459323e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_2_sram[0]:21 5.459323e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004473215 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A1 0.152 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002281678 //LENGTH 15.700 LUMPCC 0.0009670549 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_2_:X O *L 0 *C 54.915 90.440 +*I mux_top_track_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 51.160 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 51.060 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 51.060 101.615 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 51.060 90.485 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 51.105 90.440 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 54.878 90.440 + +*CAP +0 mux_top_track_2\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.509931e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0004178504 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0004178504 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002209117 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002209117 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chany_bottom_in[6]:19 0.0002936558 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chany_bottom_in[6]:16 0.0002936558 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chanx_left_in[19]:7 0.0001027076 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chanx_left_in[19]:6 0.0001027076 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_1_sram[0]:6 8.716408e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:5 8.716408e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_2_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.003368304 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.009937501 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_2\/mux_l3_in_1_:A1 0.152 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00507956 //LENGTH 32.480 LUMPCC 0.001552488 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_4_:X O *L 0 *C 78.945 78.200 +*I mux_right_track_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 97.620 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 97.520 90.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 97.520 90.735 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 97.520 85.737 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 97.513 85.680 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 88.328 85.680 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 88.320 85.623 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 88.320 78.245 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 88.275 78.200 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 78.983 78.200 + +*CAP +0 mux_right_track_0\/mux_l1_in_4_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_2_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.41843e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003052356 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003052356 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003246218 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003246218 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004260573 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0004260573 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0006895294 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0006895294 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 right_top_grid_pin_48_[0]:12 0.0002692212 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 right_top_grid_pin_48_[0]:11 0.0002692212 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005070228 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005070228 + +*RES +0 mux_right_track_0\/mux_l1_in_4_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_0\/mux_l2_in_2_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.004462053 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00341 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00341 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001438983 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.006587054 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.008296875 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0003345966 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_1_:X O *L 0 *C 117.585 96.900 +*I mux_right_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 119.775 96.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 119.738 96.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 117.623 96.900 + +*CAP +0 mux_right_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001662983 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001662983 + +*RES +0 mux_right_track_2\/mux_l2_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008576025 //LENGTH 5.355 LUMPCC 0.0003074349 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_4_:X O *L 0 *C 74.345 36.380 +*I mux_bottom_track_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 76.920 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 76.883 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 74.565 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 74.520 34.385 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 74.520 36.335 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 74.520 36.380 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 74.345 36.380 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_4_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001199286 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001199286 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.8648e-05 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.8648e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.6924e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.409035e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[16]:15 5.549837e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[16]:24 5.549837e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_7_sram[0]:19 5.605213e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_7_sram[0]:20 4.216695e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_7_sram[0]:14 5.605213e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_7_sram[0]:19 4.216695e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_4_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_1\/mux_l2_in_2_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002069196 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001741071 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002307439 //LENGTH 16.285 LUMPCC 0.0004525097 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_4_:X O *L 0 *C 43.065 27.880 +*I mux_bottom_track_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 55.760 25.500 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 55.723 25.500 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 48.760 25.500 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 48.760 25.840 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 44.665 25.840 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 44.620 25.885 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 44.620 27.835 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 44.575 27.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 43.102 27.880 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_4_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003719117 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003963292 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003061726 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002817552 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001272714 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001272714 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001211091 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001211091 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002262549 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002262549 + +*RES +0 mux_bottom_track_3\/mux_l1_in_4_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3\/mux_l2_in_2_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00365625 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001741071 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.001314732 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.006216518 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006322448 //LENGTH 4.340 LUMPCC 0.0001331796 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_4_:X O *L 0 *C 20.415 78.200 +*I mux_left_track_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 18.400 79.900 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 18.400 79.900 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 18.400 79.855 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 18.400 78.245 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 18.445 78.200 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 20.378 78.200 + +*CAP +0 mux_left_track_1\/mux_l1_in_4_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_2_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.468964e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.810457e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.810457e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001330832 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001330832 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 left_top_grid_pin_42_[0]:4 5.060572e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 left_top_grid_pin_42_[0]:5 5.060572e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 left_top_grid_pin_42_[0]:6 1.598409e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 left_top_grid_pin_42_[0]:7 1.598409e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_4_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001725447 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0014375 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1\/mux_l2_in_2_:A1 0.152 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001971362 //LENGTH 15.115 LUMPCC 0.0002910979 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_1_:X O *L 0 *C 69.635 104.040 +*I mux_left_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 62.390 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 62.353 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 61.685 98.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 61.640 98.645 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 61.640 103.995 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 61.685 104.040 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 69.597 104.040 + +*CAP +0 mux_left_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.029589e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.029589e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003011593 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003011593 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004676767 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004676767 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size12_1_sram[1]:30 0.0001455489 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size12_1_sram[1]:31 0.0001455489 + +*RES +0 mux_left_track_3\/mux_l1_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005959822 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.007064733 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0] 0.002128319 //LENGTH 17.840 LUMPCC 0.0002555634 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_2_:X O *L 0 *C 41.605 86.360 +*I mux_top_track_4\/mux_l4_in_1_:A1 I *L 0.00198 *C 43.340 101.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 43.240 101.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 43.240 101.615 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 43.240 93.840 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 42.780 93.840 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 42.780 86.405 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 42.735 86.360 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:8 *C 41.643 86.360 + +*CAP +0 mux_top_track_4\/mux_l3_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 3.459181e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0004367691 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0004692046 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0003717747 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0003393392 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.000109538 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.000109538 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_tree_tapbuf_size16_0_sram[2]:13 0.0001277817 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:14 0.0001277817 + +*RES +0 mux_top_track_4\/mux_l3_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_top_track_4\/mux_l4_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.006638393 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0009754464 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0004107143 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.006941965 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001006807 //LENGTH 7.280 LUMPCC 0.0004810198 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_0_:X O *L 0 *C 36.625 117.640 +*I mux_top_track_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 38.180 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 38.180 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 38.180 112.585 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 38.180 117.595 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 38.135 117.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 36.663 117.640 + +*CAP +0 mux_top_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.182285e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001554503 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001554503 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 9.053176e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.053176e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:505 0.0001445207 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 prog_clk[0]:509 0.0001445207 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size16_0_sram[2]:6 3.175538e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:7 3.175538e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size16_0_sram[2]:8 6.423383e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size16_0_sram[2]:9 6.423383e-05 + +*RES +0 mux_top_track_4\/mux_l3_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.001314732 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.004473214 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_4\/mux_l4_in_0_:A1 0.152 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003596602 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_1_:X O *L 0 *C 114.825 82.620 +*I mux_right_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 117.015 82.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 116.978 82.620 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 114.863 82.620 + +*CAP +0 mux_right_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001788301 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001788301 + +*RES +0 mux_right_track_4\/mux_l2_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003835065 //LENGTH 34.540 LUMPCC 0.0004991344 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 50.315 15.640 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 40.845 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 40.883 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 49.175 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 49.220 39.735 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 49.220 15.685 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 49.265 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 50.278 15.640 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004806891 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004806891 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001088273 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001088273 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.800308e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.800308e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:366 1.161093e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:367 0.0001116176 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:363 1.161093e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:366 0.0001116176 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:12 9.133559e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:16 4.912858e-06 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_7_sram[1]:22 3.009022e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:17 4.912858e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:21 3.009022e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:22 9.133559e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.007404018 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.02147322 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0007805617 //LENGTH 6.000 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_7_:X O *L 0 *C 34.785 38.760 +*I mux_bottom_track_5\/mux_l3_in_3_:A0 I *L 0.001631 *C 34.675 33.660 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 34.675 33.660 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 34.500 33.660 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 34.500 33.705 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 34.500 38.715 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 34.500 38.760 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 34.785 38.760 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_7_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_3_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.837581e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.039202e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002813318 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002813318 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.072336e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.64069e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_7_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_5\/mux_l3_in_3_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.003341919 //LENGTH 23.580 LUMPCC 0.0006414478 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_2_:X O *L 0 *C 48.475 82.960 +*I mux_left_track_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 32.565 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 32.602 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 33.535 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 33.580 88.695 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 33.580 82.665 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 33.625 82.620 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 47.380 82.620 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 47.380 82.960 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 48.438 82.960 + +*CAP +0 mux_left_track_5\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001236035 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001236035 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003524634 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003524634 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0007372202 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000766769 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001359483 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001063996 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[2]:17 0.0002327215 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[2]:18 0.0002327215 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 8.80024e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 8.80024e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_5\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005383929 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0009441964 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.01228125 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003035715 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0007636189 //LENGTH 5.515 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_0_:X O *L 0 *C 107.465 46.920 +*I mux_top_track_8\/mux_l4_in_0_:A1 I *L 0.00198 *C 112.145 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 112.145 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 112.240 46.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 107.503 46.920 + +*CAP +0 mux_top_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.285149e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003674547 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003413127 + +*RES +0 mux_top_track_8\/mux_l3_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_8\/mux_l4_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.004229911 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003747357 //LENGTH 2.590 LUMPCC 0.000191117 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_1_:X O *L 0 *C 51.695 53.380 +*I mux_top_track_16\/mux_l3_in_0_:A0 I *L 0.001631 *C 49.395 53.380 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 49.433 53.380 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 51.658 53.380 + +*CAP +0 mux_top_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.080934e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.080934e-05 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:17 9.544472e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:19 1.137728e-07 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:16 9.544472e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:20 1.137728e-07 + +*RES +0 mux_top_track_16\/mux_l2_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001986607 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008494105 //LENGTH 6.200 LUMPCC 0.0001102053 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_1_:X O *L 0 *C 62.275 67.320 +*I mux_top_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 60.895 71.400 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 60.933 71.400 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 62.055 71.400 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 62.100 71.355 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 62.100 67.365 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 62.100 67.320 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 62.275 67.320 + +*CAP +0 mux_top_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.193953e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.193953e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002457984 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002457984 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.221891e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.951029e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size12_6_sram[0]:36 5.510267e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size12_6_sram[0]:35 5.510267e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001002232 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003562501 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001387509 //LENGTH 9.500 LUMPCC 0.0005362076 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_2_:X O *L 0 *C 108.845 53.380 +*I mux_right_track_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 115.100 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 115.000 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 115.000 56.055 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 115.000 53.425 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 114.955 53.380 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 108.883 53.380 + +*CAP +0 mux_right_track_8\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.293282e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001584415 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001584415 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002497428 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002497428 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[16]:18 0.0001640464 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[16]:19 5.631147e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[16]:19 0.0001640464 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[16]:20 5.631147e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.134723e-05 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.639862e-05 +13 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 1.134723e-05 +14 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 3.639862e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_2_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_8\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002348214 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.005421875 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001506435 //LENGTH 11.170 LUMPCC 0.0003657979 DR + +*CONN +*I mux_right_track_16\/mux_l3_in_1_:X O *L 0 *C 89.525 47.260 +*I mux_right_track_16\/mux_l4_in_0_:A0 I *L 0.001631 *C 97.235 44.540 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 97.198 44.540 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 89.745 44.540 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 89.700 44.585 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 89.700 47.215 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 89.700 47.260 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 89.525 47.260 + +*CAP +0 mux_right_track_16\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0003661251 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0003661251 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001444743 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001444743 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.824304e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.919521e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 prog_clk[0]:221 4.317756e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 prog_clk[0]:222 4.317756e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:221 2.882329e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:218 2.882329e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_5_sram[0]:20 0.0001108981 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_5_sram[0]:19 0.0001108981 + +*RES +0 mux_right_track_16\/mux_l3_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_16\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.006654019 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002348215 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002994733 //LENGTH 22.025 LUMPCC 0.0007127156 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 78.025 30.940 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 94.760 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 94.723 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 90.160 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 90.160 27.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 82.845 27.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 82.800 27.925 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 82.800 30.895 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 82.755 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 78.062 30.940 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001734021 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002353407 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0006041018 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005421632 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001813915 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001813915 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001811134 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001811134 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_6_sram[0]:21 4.879414e-06 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_6_sram[0]:22 2.810542e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size10_6_sram[0]:16 1.944345e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size10_6_sram[0]:20 0.0001512962 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_6_sram[0]:18 4.879414e-06 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_6_sram[0]:21 2.810542e-05 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size10_6_sram[0]:17 1.944345e-05 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size10_6_sram[0]:19 0.0001512962 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_6_sram[1]:18 7.86306e-05 +19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_6_sram[1]:19 7.86306e-05 +20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.603401e-05 +21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.968643e-06 +22 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.603401e-05 +23 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.968643e-06 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006531251 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002651786 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004189732 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0009107143 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004073661 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001479012 //LENGTH 11.640 LUMPCC 0.000117824 DR + +*CONN +*I mux_bottom_track_17\/mux_l3_in_1_:X O *L 0 *C 46.285 36.380 +*I mux_bottom_track_17\/mux_l4_in_0_:A0 I *L 0.001631 *C 53.995 33.660 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 53.958 33.660 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 51.980 33.660 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 51.980 34.000 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 51.105 34.000 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 51.060 34.045 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 51.060 36.335 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 51.015 36.380 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 46.323 36.380 + +*CAP +0 mux_bottom_track_17\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001214841 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001479718 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.602121e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.953351e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001424689 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001424689 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0003396199 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0003396199 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_7_sram[3]:3 1.664383e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_7_sram[3]:8 4.226815e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_7_sram[3]:3 4.226815e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_7_sram[3]:8 1.664383e-05 + +*RES +0 mux_bottom_track_17\/mux_l3_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_17\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.00078125 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.002044643 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.004189732 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0003035715 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001765625 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005963777 //LENGTH 46.165 LUMPCC 0.001378163 DR + +*CONN +*I mux_bottom_track_25\/mux_l4_in_0_:X O *L 0 *C 41.685 44.880 +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 44.025 4.275 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 44.062 4.275 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 44.575 4.317 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 44.620 4.465 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 44.620 5.383 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 44.617 5.440 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 44.175 5.440 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 44.160 5.448 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 44.160 44.873 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 44.140 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 41.407 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 41.400 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 41.400 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 41.685 44.880 + +*CAP +0 mux_bottom_track_25\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.946466e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.946466e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.726958e-05 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 6.726958e-05 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.948994e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.948994e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001893313 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001893313 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001461091 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001461091 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:12 4.098754e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:13 6.451132e-05 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:14 6.682271e-05 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 chanx_right_in[4]:18 0.0001668834 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 chanx_right_in[4]:17 0.0001668834 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chanx_left_in[13]:29 0.0003622321 +18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chanx_left_in[13]:30 0.0003622321 +19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_bottom_in[15]:20 0.0001599661 +20 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chany_bottom_in[15]:19 0.0001599661 + +*RES +0 mux_bottom_track_25\/mux_l4_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004575893 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0008191965 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.499219e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.006176583 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0004280916 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0045 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0001548913 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001494511 //LENGTH 10.975 LUMPCC 0.0005157872 DR + +*CONN +*I mux_left_track_17\/mux_l3_in_1_:X O *L 0 *C 30.185 60.520 +*I mux_left_track_17\/mux_l4_in_0_:A0 I *L 0.001631 *C 28.350 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 28.388 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 31.695 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 31.740 55.465 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 31.740 60.475 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 31.695 60.520 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 30.223 60.520 + +*CAP +0 mux_left_track_17\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002082282 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002082282 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001666245 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001666245 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001135092 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001135092 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chanx_left_in[5]:9 0.0001378693 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chanx_left_in[5]:31 0.0001378693 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:476 5.537603e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 prog_clk[0]:460 1.449689e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:466 5.537603e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 prog_clk[0]:461 1.449689e-05 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_10_sram[3]:4 4.869041e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_10_sram[3]:6 1.46093e-06 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_10_sram[3]:3 4.869041e-05 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_10_sram[3]:7 1.46093e-06 + +*RES +0 mux_left_track_17\/mux_l3_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_17\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002953125 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.008980365 //LENGTH 65.290 LUMPCC 0.001574697 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_1_:X O *L 0 *C 82.975 53.720 +*I mux_top_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 78.375 107.780 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 78.403 107.758 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 78.660 107.745 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 78.660 107.440 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.835 107.440 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.880 107.395 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.880 100.640 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 82.340 100.640 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 82.340 97.240 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 81.880 97.240 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 81.880 88.740 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 82.340 88.740 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 82.340 76.218 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 82.343 76.160 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 82.785 76.160 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 *C 82.800 76.153 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 *C 82.800 65.280 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 *C 81.880 65.280 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 *C 81.880 57.808 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:20 *C 81.900 57.800 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:21 *C 82.793 57.800 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:22 *C 82.800 57.742 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:23 *C 82.800 53.765 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:24 *C 82.800 53.720 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:25 *C 82.975 53.720 + +*CAP +0 mux_top_track_32\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.25823e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.062008e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002665419 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002385041 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004251812 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000454253 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002343427 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002399537 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0005443811 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0004852077 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0006678264 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.000692317 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0001105172 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0001105172 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.0005956655 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 0.0006652652 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 0.0004329837 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 0.000363384 +20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:20 9.702479e-05 +21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:21 9.702479e-05 +22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:22 0.0002282926 +23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:23 0.0002282926 +24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:24 5.505465e-05 +25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:25 5.793411e-05 +26 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 chany_top_in[12]:28 7.395214e-05 +27 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 chany_top_in[12]:31 8.343844e-05 +28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[12]:39 2.041409e-05 +29 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 chany_top_in[12]:31 7.395214e-05 +30 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 chany_top_in[12]:32 8.343844e-05 +31 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_top_in[12]:38 7.215735e-06 +32 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[12]:38 2.041409e-05 +33 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_top_in[12]:39 7.215735e-06 +34 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 chany_top_in[17]:33 0.0003795891 +35 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 chany_top_in[17]:32 0.0003795891 +36 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 chany_bottom_in[0]:17 0.0001600469 +37 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 chany_bottom_in[0]:16 6.545506e-06 +38 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 chany_bottom_in[0]:16 0.0001600469 +39 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 chany_bottom_in[0]:17 6.545506e-06 +40 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.614678e-05 +41 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.614678e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_1_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:25 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:24 9.51087e-05 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:23 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:22 0.003551339 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:21 0.00341 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:20 0.000139825 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 0.00341 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 0.001170692 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:14 6.499219e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.00341 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0111808 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.00341 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002834822 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A0 0.152 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001739865 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002723215 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.007589286 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004107143 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0004107143 +20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.003035714 +21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00603125 +22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004107143 +23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 0.0001441333 +24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.001703358 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008915407 //LENGTH 7.500 LUMPCC 8.614936e-05 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_0_:X O *L 0 *C 18.575 68.680 +*I mux_left_track_33\/mux_l3_in_0_:A1 I *L 0.00198 *C 13.705 66.980 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 13.743 66.980 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 15.595 66.980 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 15.640 67.025 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 15.640 68.635 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 15.685 68.680 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 18.538 68.680 + +*CAP +0 mux_left_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.481674e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.481674e-05 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.459838e-05 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.459838e-05 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002122805 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002122805 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_3_sram[2]:9 3.300074e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_3_sram[2]:10 3.300074e-05 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:11 1.007394e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:12 1.007394e-05 + +*RES +0 mux_left_track_33\/mux_l2_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001654018 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002546875 + +*END + +*D_NET ropt_net_239 0.0005165909 //LENGTH 3.235 LUMPCC 0.0001658583 DR + +*CONN +*I FTB_13__12:X O *L 0 *C 72.680 8.840 +*I ropt_mt_inst_893:A I *L 0.001766 *C 72.220 6.800 +*N ropt_net_239:2 *C 72.258 6.800 +*N ropt_net_239:3 *C 72.680 6.800 +*N ropt_net_239:4 *C 72.680 7.480 +*N ropt_net_239:5 *C 72.680 7.525 +*N ropt_net_239:6 *C 72.680 8.795 +*N ropt_net_239:7 *C 72.680 8.840 + +*CAP +0 FTB_13__12:X 1e-06 +1 ropt_mt_inst_893:A 1e-06 +2 ropt_net_239:2 4.645446e-05 +3 ropt_net_239:3 9.644374e-05 +4 ropt_net_239:4 8.619516e-05 +5 ropt_net_239:5 4.176234e-05 +6 ropt_net_239:6 4.176234e-05 +7 ropt_net_239:7 3.611456e-05 +8 ropt_net_239:5 chany_top_in[17]:11 4.316695e-05 +9 ropt_net_239:6 chany_top_in[17]:12 4.316695e-05 +10 ropt_net_239:5 chany_bottom_out[18] 3.976221e-05 +11 ropt_net_239:6 chany_bottom_out[18]:2 3.976221e-05 + +*RES +0 FTB_13__12:X ropt_net_239:7 0.152 +1 ropt_net_239:2 ropt_mt_inst_893:A 0.152 +2 ropt_net_239:4 ropt_net_239:3 0.000607143 +3 ropt_net_239:5 ropt_net_239:4 0.0045 +4 ropt_net_239:7 ropt_net_239:6 0.0045 +5 ropt_net_239:6 ropt_net_239:5 0.001133929 +6 ropt_net_239:3 ropt_net_239:2 0.0003772322 + +*END + +*D_NET chany_top_out[3] 0.001222898 //LENGTH 8.125 LUMPCC 0.0002783074 DR + +*CONN +*I ropt_mt_inst_847:X O *L 0 *C 76.885 127.160 +*P chany_top_out[3] O *L 0.7423 *C 71.300 129.235 +*N chany_top_out[3]:2 *C 71.300 127.205 +*N chany_top_out[3]:3 *C 71.345 127.160 +*N chany_top_out[3]:4 *C 76.847 127.160 + +*CAP +0 ropt_mt_inst_847:X 1e-06 +1 chany_top_out[3] 0.0001442237 +2 chany_top_out[3]:2 0.0001442237 +3 chany_top_out[3]:3 0.0003275714 +4 chany_top_out[3]:4 0.0003275714 +5 chany_top_out[3]:3 ropt_net_213:3 0.0001391537 +6 chany_top_out[3]:4 ropt_net_213:4 0.0001391537 + +*RES +0 ropt_mt_inst_847:X chany_top_out[3]:4 0.152 +1 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +2 chany_top_out[3]:2 chany_top_out[3] 0.0018125 +3 chany_top_out[3]:4 chany_top_out[3]:3 0.004912947 + +*END + +*D_NET ropt_net_212 0.001445785 //LENGTH 11.275 LUMPCC 0.0001268867 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 11.525 52.360 +*I ropt_mt_inst_852:A I *L 0.001767 *C 3.220 50.320 +*N ropt_net_212:2 *C 3.258 50.320 +*N ropt_net_212:3 *C 4.555 50.320 +*N ropt_net_212:4 *C 4.600 50.365 +*N ropt_net_212:5 *C 4.600 52.315 +*N ropt_net_212:6 *C 4.645 52.360 +*N ropt_net_212:7 *C 11.488 52.360 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 ropt_mt_inst_852:A 1e-06 +2 ropt_net_212:2 9.748687e-05 +3 ropt_net_212:3 9.748687e-05 +4 ropt_net_212:4 8.211664e-05 +5 ropt_net_212:5 8.211664e-05 +6 ropt_net_212:6 0.0004788458 +7 ropt_net_212:7 0.0004788458 +8 ropt_net_212:5 prog_clk[0]:679 6.344336e-05 +9 ropt_net_212:4 prog_clk[0]:706 6.344336e-05 + +*RES +0 ropt_mt_inst_801:X ropt_net_212:7 0.152 +1 ropt_net_212:7 ropt_net_212:6 0.006109376 +2 ropt_net_212:6 ropt_net_212:5 0.0045 +3 ropt_net_212:5 ropt_net_212:4 0.001741072 +4 ropt_net_212:3 ropt_net_212:2 0.001158482 +5 ropt_net_212:4 ropt_net_212:3 0.0045 +6 ropt_net_212:2 ropt_mt_inst_852:A 0.152 + +*END + +*D_NET ropt_net_207 0.002390806 //LENGTH 16.665 LUMPCC 0.0004829208 DR + +*CONN +*I ropt_mt_inst_807:X O *L 0 *C 71.495 6.460 +*I ropt_mt_inst_846:A I *L 0.001766 *C 63.480 4.080 +*N ropt_net_207:2 *C 63.518 4.080 +*N ropt_net_207:3 *C 63.895 4.080 +*N ropt_net_207:4 *C 63.940 4.035 +*N ropt_net_207:5 *C 63.940 1.745 +*N ropt_net_207:6 *C 63.985 1.700 +*N ropt_net_207:7 *C 69.460 1.700 +*N ropt_net_207:8 *C 69.460 1.700 +*N ropt_net_207:9 *C 69.460 6.415 +*N ropt_net_207:10 *C 69.505 6.460 +*N ropt_net_207:11 *C 71.458 6.460 + +*CAP +0 ropt_mt_inst_807:X 1e-06 +1 ropt_mt_inst_846:A 1e-06 +2 ropt_net_207:2 4.936275e-05 +3 ropt_net_207:3 4.936275e-05 +4 ropt_net_207:4 0.000118785 +5 ropt_net_207:5 0.000118785 +6 ropt_net_207:6 0.0003787452 +7 ropt_net_207:7 0.0004199739 +8 ropt_net_207:8 0.0002404899 +9 ropt_net_207:9 0.0001887697 +10 ropt_net_207:10 0.0001708052 +11 ropt_net_207:11 0.0001708052 +12 ropt_net_207:8 chany_top_in[2]:11 6.56664e-05 +13 ropt_net_207:9 chany_top_in[2]:12 6.56664e-05 +14 ropt_net_207:8 chany_bottom_in[17] 0.0001042507 +15 ropt_net_207:9 chany_bottom_in[17]:41 0.0001042507 +16 ropt_net_207:4 chany_bottom_out[8]:2 7.154333e-05 +17 ropt_net_207:5 chany_bottom_out[8] 7.154333e-05 + +*RES +0 ropt_mt_inst_807:X ropt_net_207:11 0.152 +1 ropt_net_207:2 ropt_mt_inst_846:A 0.152 +2 ropt_net_207:3 ropt_net_207:2 0.0003370536 +3 ropt_net_207:4 ropt_net_207:3 0.0045 +4 ropt_net_207:6 ropt_net_207:5 0.0045 +5 ropt_net_207:5 ropt_net_207:4 0.002044643 +6 ropt_net_207:7 ropt_net_207:6 0.004888393 +7 ropt_net_207:8 ropt_net_207:7 0.0045 +8 ropt_net_207:10 ropt_net_207:9 0.0045 +9 ropt_net_207:9 ropt_net_207:8 0.004209822 +10 ropt_net_207:11 ropt_net_207:10 0.001743304 + +*END + +*D_NET ropt_net_223 0.001110816 //LENGTH 8.755 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 138.655 83.640 +*I ropt_mt_inst_869:A I *L 0.001767 *C 134.780 85.680 +*N ropt_net_223:2 *C 134.743 85.680 +*N ropt_net_223:3 *C 133.860 85.680 +*N ropt_net_223:4 *C 133.860 85.340 +*N ropt_net_223:5 *C 138.415 85.340 +*N ropt_net_223:6 *C 138.460 85.295 +*N ropt_net_223:7 *C 138.460 83.685 +*N ropt_net_223:8 *C 138.460 83.640 +*N ropt_net_223:9 *C 138.655 83.640 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 ropt_mt_inst_869:A 1e-06 +2 ropt_net_223:2 7.449382e-05 +3 ropt_net_223:3 0.0001003111 +4 ropt_net_223:4 0.000301158 +5 ropt_net_223:5 0.0002753407 +6 ropt_net_223:6 0.0001203867 +7 ropt_net_223:7 0.0001203867 +8 ropt_net_223:8 5.639683e-05 +9 ropt_net_223:9 6.034245e-05 + +*RES +0 ropt_mt_inst_816:X ropt_net_223:9 0.152 +1 ropt_net_223:2 ropt_mt_inst_869:A 0.152 +2 ropt_net_223:5 ropt_net_223:4 0.004066965 +3 ropt_net_223:6 ropt_net_223:5 0.0045 +4 ropt_net_223:8 ropt_net_223:7 0.0045 +5 ropt_net_223:7 ropt_net_223:6 0.0014375 +6 ropt_net_223:9 ropt_net_223:8 0.0001059783 +7 ropt_net_223:4 ropt_net_223:3 0.0003035715 +8 ropt_net_223:3 ropt_net_223:2 0.0007879465 + +*END + +*D_NET ropt_net_228 0.001109512 //LENGTH 8.790 LUMPCC 0.0001123227 DR + +*CONN +*I ropt_mt_inst_828:X O *L 0 *C 102.775 6.120 +*I ropt_mt_inst_875:A I *L 0.001767 *C 98.440 4.080 +*N ropt_net_228:2 *C 98.440 4.080 +*N ropt_net_228:3 *C 98.440 4.035 +*N ropt_net_228:4 *C 98.440 3.445 +*N ropt_net_228:5 *C 98.485 3.400 +*N ropt_net_228:6 *C 102.535 3.400 +*N ropt_net_228:7 *C 102.580 3.445 +*N ropt_net_228:8 *C 102.580 6.075 +*N ropt_net_228:9 *C 102.580 6.120 +*N ropt_net_228:10 *C 102.775 6.120 + +*CAP +0 ropt_mt_inst_828:X 1e-06 +1 ropt_mt_inst_875:A 1e-06 +2 ropt_net_228:2 3.188692e-05 +3 ropt_net_228:3 3.953965e-05 +4 ropt_net_228:4 3.953965e-05 +5 ropt_net_228:5 0.0002430473 +6 ropt_net_228:6 0.0002430473 +7 ropt_net_228:7 0.0001460704 +8 ropt_net_228:8 0.0001460704 +9 ropt_net_228:9 5.254209e-05 +10 ropt_net_228:10 5.344554e-05 +11 ropt_net_228:3 chany_bottom_out[14]:2 9.754792e-06 +12 ropt_net_228:5 chany_bottom_out[14]:3 4.640656e-05 +13 ropt_net_228:4 chany_bottom_out[14] 9.754792e-06 +14 ropt_net_228:6 chany_bottom_out[14]:4 4.640656e-05 + +*RES +0 ropt_mt_inst_828:X ropt_net_228:10 0.152 +1 ropt_net_228:2 ropt_mt_inst_875:A 0.152 +2 ropt_net_228:3 ropt_net_228:2 0.0045 +3 ropt_net_228:5 ropt_net_228:4 0.0045 +4 ropt_net_228:4 ropt_net_228:3 0.0005267857 +5 ropt_net_228:6 ropt_net_228:5 0.003616072 +6 ropt_net_228:7 ropt_net_228:6 0.0045 +7 ropt_net_228:9 ropt_net_228:8 0.0045 +8 ropt_net_228:8 ropt_net_228:7 0.002348214 +9 ropt_net_228:10 ropt_net_228:9 0.0001059783 + +*END + +*D_NET ropt_net_182 0.001793955 //LENGTH 11.030 LUMPCC 0.0004673253 DR + +*CONN +*I BUFT_P_122:X O *L 0 *C 61.640 123.420 +*I ropt_mt_inst_821:A I *L 0.001766 *C 71.760 123.760 +*N ropt_net_182:2 *C 71.722 123.760 +*N ropt_net_182:3 *C 71.300 123.760 +*N ropt_net_182:4 *C 71.300 123.420 +*N ropt_net_182:5 *C 61.678 123.420 + +*CAP +0 BUFT_P_122:X 1e-06 +1 ropt_mt_inst_821:A 1e-06 +2 ropt_net_182:2 5.122759e-05 +3 ropt_net_182:3 7.263527e-05 +4 ropt_net_182:4 0.0006110872 +5 ropt_net_182:5 0.0005896796 +6 ropt_net_182:5 ropt_net_221:2 0.0001116612 +7 ropt_net_182:4 ropt_net_221:3 0.0001116612 +8 ropt_net_182:4 ropt_net_221:6 6.75404e-06 +9 ropt_net_182:3 ropt_net_221:5 6.75404e-06 +10 ropt_net_182:5 chany_top_out[13]:6 6.159778e-05 +11 ropt_net_182:4 chany_top_out[13]:5 6.159778e-05 +12 ropt_net_182:5 chany_top_out[8]:6 5.364966e-05 +13 ropt_net_182:4 chany_top_out[8]:5 5.364966e-05 + +*RES +0 BUFT_P_122:X ropt_net_182:5 0.152 +1 ropt_net_182:5 ropt_net_182:4 0.008591518 +2 ropt_net_182:2 ropt_mt_inst_821:A 0.152 +3 ropt_net_182:4 ropt_net_182:3 0.0003035715 +4 ropt_net_182:3 ropt_net_182:2 0.0003772322 + +*END + +*D_NET chanx_right_out[13] 0.0008517394 //LENGTH 6.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_869:X O *L 0 *C 136.160 85.680 +*P chanx_right_out[13] O *L 0.7423 *C 140.450 85.680 +*N chanx_right_out[13]:2 *C 139.840 85.680 +*N chanx_right_out[13]:3 *C 139.840 86.360 +*N chanx_right_out[13]:4 *C 136.168 86.360 +*N chanx_right_out[13]:5 *C 136.160 86.303 +*N chanx_right_out[13]:6 *C 136.160 85.725 +*N chanx_right_out[13]:7 *C 136.160 85.680 + +*CAP +0 ropt_mt_inst_869:X 1e-06 +1 chanx_right_out[13] 4.320858e-05 +2 chanx_right_out[13]:2 8.700906e-05 +3 chanx_right_out[13]:3 0.0003136223 +4 chanx_right_out[13]:4 0.0002698218 +5 chanx_right_out[13]:5 5.30833e-05 +6 chanx_right_out[13]:6 5.30833e-05 +7 chanx_right_out[13]:7 3.0911e-05 + +*RES +0 ropt_mt_inst_869:X chanx_right_out[13]:7 0.152 +1 chanx_right_out[13]:7 chanx_right_out[13]:6 0.0045 +2 chanx_right_out[13]:6 chanx_right_out[13]:5 0.000515625 +3 chanx_right_out[13]:5 chanx_right_out[13]:4 0.00341 +4 chanx_right_out[13]:4 chanx_right_out[13]:3 0.0005753583 +5 chanx_right_out[13]:3 chanx_right_out[13]:2 0.0001065333 +6 chanx_right_out[13]:2 chanx_right_out[13] 9.556664e-05 + +*END + +*D_NET chany_top_out[11] 0.0007452929 //LENGTH 6.540 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_874:X O *L 0 *C 92.595 124.440 +*P chany_top_out[11] O *L 0.7423 *C 93.840 129.270 +*N chany_top_out[11]:2 *C 93.840 124.485 +*N chany_top_out[11]:3 *C 93.795 124.440 +*N chany_top_out[11]:4 *C 92.633 124.440 + +*CAP +0 ropt_mt_inst_874:X 1e-06 +1 chany_top_out[11] 0.0002662269 +2 chany_top_out[11]:2 0.0002662269 +3 chany_top_out[11]:3 0.0001059195 +4 chany_top_out[11]:4 0.0001059195 + +*RES +0 ropt_mt_inst_874:X chany_top_out[11]:4 0.152 +1 chany_top_out[11]:4 chany_top_out[11]:3 0.001037947 +2 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +3 chany_top_out[11]:2 chany_top_out[11] 0.004272322 + +*END + +*D_NET chanx_right_out[18] 0.0006115777 //LENGTH 4.150 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_896:X O *L 0 *C 138.655 51.000 +*P chanx_right_out[18] O *L 0.7423 *C 140.450 52.360 +*N chanx_right_out[18]:2 *C 138.468 52.360 +*N chanx_right_out[18]:3 *C 138.460 52.303 +*N chanx_right_out[18]:4 *C 138.460 51.045 +*N chanx_right_out[18]:5 *C 138.460 51.000 +*N chanx_right_out[18]:6 *C 138.655 51.000 + +*CAP +0 ropt_mt_inst_896:X 1e-06 +1 chanx_right_out[18] 0.0001512426 +2 chanx_right_out[18]:2 0.0001512426 +3 chanx_right_out[18]:3 0.0001028366 +4 chanx_right_out[18]:4 0.0001028366 +5 chanx_right_out[18]:5 5.116566e-05 +6 chanx_right_out[18]:6 5.125363e-05 + +*RES +0 ropt_mt_inst_896:X chanx_right_out[18]:6 0.152 +1 chanx_right_out[18]:6 chanx_right_out[18]:5 0.0001059783 +2 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +3 chanx_right_out[18]:4 chanx_right_out[18]:3 0.001122768 +4 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +5 chanx_right_out[18]:2 chanx_right_out[18] 0.0003105917 + +*END + +*D_NET chany_top_in[9] 0.02331062 //LENGTH 163.405 LUMPCC 0.007651398 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 67.620 129.270 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.600 88.740 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 69.290 66.300 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 73.045 45.220 +*I ropt_mt_inst_805:A I *L 0.001767 *C 93.840 4.080 +*N chany_top_in[9]:5 *C 68.600 92.480 +*N chany_top_in[9]:6 *C 93.803 4.080 +*N chany_top_in[9]:7 *C 92.920 4.080 +*N chany_top_in[9]:8 *C 92.920 3.740 +*N chany_top_in[9]:9 *C 81.005 3.740 +*N chany_top_in[9]:10 *C 80.960 3.785 +*N chany_top_in[9]:11 *C 80.960 6.755 +*N chany_top_in[9]:12 *C 80.915 6.800 +*N chany_top_in[9]:13 *C 79.165 6.800 +*N chany_top_in[9]:14 *C 79.120 6.845 +*N chany_top_in[9]:15 *C 79.120 8.103 +*N chany_top_in[9]:16 *C 79.112 8.160 +*N chany_top_in[9]:17 *C 73.620 8.160 +*N chany_top_in[9]:18 *C 73.600 8.168 +*N chany_top_in[9]:19 *C 73.600 44.873 +*N chany_top_in[9]:20 *C 73.585 44.880 +*N chany_top_in[9]:21 *C 73.045 45.220 +*N chany_top_in[9]:22 *C 73.140 45.220 +*N chany_top_in[9]:23 *C 73.140 44.880 +*N chany_top_in[9]:24 *C 73.142 44.880 +*N chany_top_in[9]:25 *C 69.468 44.880 +*N chany_top_in[9]:26 *C 69.460 44.938 +*N chany_top_in[9]:27 *C 69.460 66.300 +*N chany_top_in[9]:28 *C 69.290 66.300 +*N chany_top_in[9]:29 *C 69.000 66.300 +*N chany_top_in[9]:30 *C 69.000 66.300 +*N chany_top_in[9]:31 *C 73.562 88.740 +*N chany_top_in[9]:32 *C 69.045 88.740 +*N chany_top_in[9]:33 *C 69.000 88.740 +*N chany_top_in[9]:34 *C 69.000 92.422 +*N chany_top_in[9]:35 *C 69.000 92.480 +*N chany_top_in[9]:36 *C 69.000 92.488 +*N chany_top_in[9]:37 *C 69.000 121.713 +*N chany_top_in[9]:38 *C 68.980 121.720 +*N chany_top_in[9]:39 *C 67.627 121.720 +*N chany_top_in[9]:40 *C 67.620 121.778 + +*CAP +0 chany_top_in[9] 0.0004408257 +1 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +4 ropt_mt_inst_805:A 1e-06 +5 chany_top_in[9]:5 0.0001139857 +6 chany_top_in[9]:6 7.75995e-05 +7 chany_top_in[9]:7 0.0001011723 +8 chany_top_in[9]:8 0.0005431953 +9 chany_top_in[9]:9 0.0005196225 +10 chany_top_in[9]:10 0.000185837 +11 chany_top_in[9]:11 0.000185837 +12 chany_top_in[9]:12 8.010907e-05 +13 chany_top_in[9]:13 8.010907e-05 +14 chany_top_in[9]:14 0.0001233572 +15 chany_top_in[9]:15 0.0001233572 +16 chany_top_in[9]:16 0.0004514168 +17 chany_top_in[9]:17 0.0004514168 +18 chany_top_in[9]:18 0.00124012 +19 chany_top_in[9]:19 0.00124012 +20 chany_top_in[9]:20 4.242408e-05 +21 chany_top_in[9]:21 3.068348e-05 +22 chany_top_in[9]:22 5.57574e-05 +23 chany_top_in[9]:23 6.007141e-05 +24 chany_top_in[9]:24 0.0003231545 +25 chany_top_in[9]:25 0.0002807304 +26 chany_top_in[9]:26 0.0007662337 +27 chany_top_in[9]:27 0.0007945169 +28 chany_top_in[9]:28 5.81842e-05 +29 chany_top_in[9]:29 6.021674e-05 +30 chany_top_in[9]:30 0.001032672 +31 chany_top_in[9]:31 0.0003726001 +32 chany_top_in[9]:32 0.0003726001 +33 chany_top_in[9]:33 0.001217633 +34 chany_top_in[9]:34 0.0001797734 +35 chany_top_in[9]:35 0.0001139857 +36 chany_top_in[9]:36 0.001610846 +37 chany_top_in[9]:37 0.001610846 +38 chany_top_in[9]:38 0.0001366937 +39 chany_top_in[9]:39 0.0001366937 +40 chany_top_in[9]:40 0.0004408257 +41 chany_top_in[9]:19 chany_top_in[13]:21 0.0007387484 +42 chany_top_in[9]:18 chany_top_in[13]:20 0.0007387484 +43 chany_top_in[9]:38 chany_top_in[13]:38 1.48638e-05 +44 chany_top_in[9]:39 chany_top_in[13]:39 1.48638e-05 +45 chany_top_in[9]:26 chanx_right_in[4]:11 5.17922e-07 +46 chany_top_in[9]:26 chanx_right_in[4]:20 0.0005305372 +47 chany_top_in[9]:25 chanx_right_in[4]:18 3.904373e-05 +48 chany_top_in[9]:30 chanx_right_in[4]:20 0.0002269905 +49 chany_top_in[9]:34 chanx_right_in[4]:23 3.280902e-05 +50 chany_top_in[9]:34 chanx_right_in[4]:24 9.20444e-06 +51 chany_top_in[9]:33 chanx_right_in[4]:23 0.0002361949 +52 chany_top_in[9]:33 chanx_right_in[4]:20 3.280902e-05 +53 chany_top_in[9]:24 chanx_right_in[4]:19 3.904373e-05 +54 chany_top_in[9]:27 chanx_right_in[4]:23 0.0005305372 +55 chany_top_in[9]:27 chanx_right_in[4]:12 5.17922e-07 +56 chany_top_in[9]:19 chany_bottom_in[5]:31 0.0007396323 +57 chany_top_in[9]:17 chany_bottom_in[5]:33 7.084285e-06 +58 chany_top_in[9]:18 chany_bottom_in[5]:32 0.0007396323 +59 chany_top_in[9]:16 chany_bottom_in[5]:34 7.084285e-06 +60 chany_top_in[9] chany_top_in[7] 3.880563e-05 +61 chany_top_in[9]:36 chany_top_in[7]:11 0.0002879494 +62 chany_top_in[9]:36 chany_top_in[7]:12 0.0001994244 +63 chany_top_in[9]:37 chany_top_in[7]:13 0.0001994244 +64 chany_top_in[9]:37 chany_top_in[7]:12 0.0002879494 +65 chany_top_in[9]:40 chany_top_in[7]:16 3.880563e-05 +66 chany_top_in[9]:26 chanx_right_in[15]:6 0.0001171586 +67 chany_top_in[9]:25 chanx_right_in[15]:7 0.0001250322 +68 chany_top_in[9]:20 chanx_right_in[15]:11 4.304997e-05 +69 chany_top_in[9]:24 chanx_right_in[15]:11 0.0001250322 +70 chany_top_in[9]:24 chanx_right_in[15]:7 4.304997e-05 +71 chany_top_in[9]:27 chanx_right_in[15]:5 0.0001171586 +72 chany_top_in[9]:30 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001372541 +73 chany_top_in[9]:33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001372541 +74 chany_top_in[9]:26 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.600634e-05 +75 chany_top_in[9]:30 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 7.169758e-06 +76 chany_top_in[9]:27 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.600634e-05 +77 chany_top_in[9]:27 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 7.169758e-06 +78 chany_top_in[9]:13 ropt_net_200:4 7.741282e-05 +79 chany_top_in[9]:12 ropt_net_200:3 7.741282e-05 +80 chany_top_in[9]:9 ropt_net_209:5 0.0002551299 +81 chany_top_in[9]:8 ropt_net_209:6 0.0002551299 +82 chany_top_in[9]:9 ropt_net_170:3 0.0001118744 +83 chany_top_in[9]:8 ropt_net_170:2 0.0001118744 + +*RES +0 chany_top_in[9] chany_top_in[9]:40 0.006689733 +1 chany_top_in[9]:26 chany_top_in[9]:25 0.00341 +2 chany_top_in[9]:25 chany_top_in[9]:24 0.00057575 +3 chany_top_in[9]:20 chany_top_in[9]:19 0.00341 +4 chany_top_in[9]:19 chany_top_in[9]:18 0.00575045 +5 chany_top_in[9]:17 chany_top_in[9]:16 0.0008604916 +6 chany_top_in[9]:18 chany_top_in[9]:17 0.00341 +7 chany_top_in[9]:15 chany_top_in[9]:14 0.001122768 +8 chany_top_in[9]:16 chany_top_in[9]:15 0.00341 +9 chany_top_in[9]:13 chany_top_in[9]:12 0.0015625 +10 chany_top_in[9]:14 chany_top_in[9]:13 0.0045 +11 chany_top_in[9]:12 chany_top_in[9]:11 0.0045 +12 chany_top_in[9]:11 chany_top_in[9]:10 0.002651786 +13 chany_top_in[9]:9 chany_top_in[9]:8 0.01063839 +14 chany_top_in[9]:10 chany_top_in[9]:9 0.0045 +15 chany_top_in[9]:6 ropt_mt_inst_805:A 0.152 +16 chany_top_in[9]:29 chany_top_in[9]:28 0.0001576087 +17 chany_top_in[9]:30 chany_top_in[9]:29 0.0045 +18 chany_top_in[9]:30 chany_top_in[9]:27 0.0004107143 +19 chany_top_in[9]:28 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +20 chany_top_in[9]:34 chany_top_in[9]:33 0.003287946 +21 chany_top_in[9]:35 chany_top_in[9]:34 0.00341 +22 chany_top_in[9]:35 chany_top_in[9]:5 5.696969e-05 +23 chany_top_in[9]:36 chany_top_in[9]:35 0.00341 +24 chany_top_in[9]:38 chany_top_in[9]:37 0.00341 +25 chany_top_in[9]:37 chany_top_in[9]:36 0.004578583 +26 chany_top_in[9]:40 chany_top_in[9]:39 0.00341 +27 chany_top_in[9]:39 chany_top_in[9]:38 0.0002118917 +28 chany_top_in[9]:32 chany_top_in[9]:31 0.004033482 +29 chany_top_in[9]:33 chany_top_in[9]:32 0.0045 +30 chany_top_in[9]:33 chany_top_in[9]:30 0.02003572 +31 chany_top_in[9]:31 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +32 chany_top_in[9]:23 chany_top_in[9]:22 0.0001634615 +33 chany_top_in[9]:24 chany_top_in[9]:23 0.00341 +34 chany_top_in[9]:24 chany_top_in[9]:20 6.499219e-05 +35 chany_top_in[9]:21 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +36 chany_top_in[9]:22 chany_top_in[9]:21 0.0045 +37 chany_top_in[9]:8 chany_top_in[9]:7 0.0003035715 +38 chany_top_in[9]:7 chany_top_in[9]:6 0.0007879465 +39 chany_top_in[9]:27 chany_top_in[9]:26 0.01907366 + +*END + +*D_NET chanx_right_in[16] 0.03186044 //LENGTH 217.115 LUMPCC 0.01067638 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 140.375 39.440 +*I mux_bottom_track_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 94.205 34.340 +*I BUFT_P_121:A I *L 0.001776 *C 10.120 82.960 +*I mux_left_track_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 66.605 72.420 +*I mux_top_track_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 94.860 52.700 +*N chanx_right_in[16]:5 *C 94.823 52.700 +*N chanx_right_in[16]:6 *C 92.965 52.700 +*N chanx_right_in[16]:7 *C 92.920 52.655 +*N chanx_right_in[16]:8 *C 66.568 72.420 +*N chanx_right_in[16]:9 *C 65.780 72.420 +*N chanx_right_in[16]:10 *C 65.780 72.760 +*N chanx_right_in[16]:11 *C 10.158 82.960 +*N chanx_right_in[16]:12 *C 12.375 82.960 +*N chanx_right_in[16]:13 *C 12.420 82.915 +*N chanx_right_in[16]:14 *C 12.420 82.338 +*N chanx_right_in[16]:15 *C 12.418 82.280 +*N chanx_right_in[16]:16 *C 11.975 82.280 +*N chanx_right_in[16]:17 *C 11.960 82.273 +*N chanx_right_in[16]:18 *C 11.960 72.767 +*N chanx_right_in[16]:19 *C 11.980 72.760 +*N chanx_right_in[16]:20 *C 35.873 72.760 +*N chanx_right_in[16]:21 *C 35.880 72.703 +*N chanx_right_in[16]:22 *C 35.880 71.445 +*N chanx_right_in[16]:23 *C 35.925 71.400 +*N chanx_right_in[16]:24 *C 40.895 71.400 +*N chanx_right_in[16]:25 *C 40.940 71.445 +*N chanx_right_in[16]:26 *C 40.940 72.715 +*N chanx_right_in[16]:27 *C 40.985 72.760 +*N chanx_right_in[16]:28 *C 48.760 72.760 +*N chanx_right_in[16]:29 *C 48.760 72.715 +*N chanx_right_in[16]:30 *C 48.760 49.698 +*N chanx_right_in[16]:31 *C 48.768 49.640 +*N chanx_right_in[16]:32 *C 57.500 49.640 +*N chanx_right_in[16]:33 *C 57.500 50.320 +*N chanx_right_in[16]:34 *C 64.392 50.320 +*N chanx_right_in[16]:35 *C 64.400 50.320 +*N chanx_right_in[16]:36 *C 64.445 50.320 +*N chanx_right_in[16]:37 *C 66.195 50.320 +*N chanx_right_in[16]:38 *C 66.240 50.320 +*N chanx_right_in[16]:39 *C 66.248 50.320 +*N chanx_right_in[16]:40 *C 81.420 50.320 +*N chanx_right_in[16]:41 *C 81.420 49.640 +*N chanx_right_in[16]:42 *C 89.233 49.640 +*N chanx_right_in[16]:43 *C 89.240 49.698 +*N chanx_right_in[16]:44 *C 89.240 50.275 +*N chanx_right_in[16]:45 *C 89.285 50.320 +*N chanx_right_in[16]:46 *C 92.875 50.320 +*N chanx_right_in[16]:47 *C 92.920 50.320 +*N chanx_right_in[16]:48 *C 92.920 40.178 +*N chanx_right_in[16]:49 *C 92.928 40.120 +*N chanx_right_in[16]:50 *C 94.243 34.340 +*N chanx_right_in[16]:51 *C 94.715 34.340 +*N chanx_right_in[16]:52 *C 94.760 34.385 +*N chanx_right_in[16]:53 *C 94.760 40.062 +*N chanx_right_in[16]:54 *C 94.760 40.120 +*N chanx_right_in[16]:55 *C 140.300 40.120 + +*CAP +0 chanx_right_in[16] 4.306537e-05 +1 mux_bottom_track_9\/mux_l1_in_2_:A1 1e-06 +2 BUFT_P_121:A 1e-06 +3 mux_left_track_9\/mux_l1_in_2_:A1 1e-06 +4 mux_top_track_8\/mux_l1_in_2_:A1 1e-06 +5 chanx_right_in[16]:5 0.0001769093 +6 chanx_right_in[16]:6 0.0001769093 +7 chanx_right_in[16]:7 0.0001486989 +8 chanx_right_in[16]:8 4.911453e-05 +9 chanx_right_in[16]:9 7.519108e-05 +10 chanx_right_in[16]:10 0.001125148 +11 chanx_right_in[16]:11 0.0001273685 +12 chanx_right_in[16]:12 0.0001273685 +13 chanx_right_in[16]:13 4.432682e-05 +14 chanx_right_in[16]:14 4.432682e-05 +15 chanx_right_in[16]:15 4.822174e-05 +16 chanx_right_in[16]:16 4.822174e-05 +17 chanx_right_in[16]:17 0.0005941973 +18 chanx_right_in[16]:18 0.0005941973 +19 chanx_right_in[16]:19 0.001001304 +20 chanx_right_in[16]:20 0.001001304 +21 chanx_right_in[16]:21 7.90489e-05 +22 chanx_right_in[16]:22 7.90489e-05 +23 chanx_right_in[16]:23 0.0002985568 +24 chanx_right_in[16]:24 0.0002985568 +25 chanx_right_in[16]:25 9.026588e-05 +26 chanx_right_in[16]:26 9.026588e-05 +27 chanx_right_in[16]:27 0.0004909048 +28 chanx_right_in[16]:28 0.001622527 +29 chanx_right_in[16]:29 0.001158585 +30 chanx_right_in[16]:30 0.001158585 +31 chanx_right_in[16]:31 0.0005693926 +32 chanx_right_in[16]:32 0.0006229851 +33 chanx_right_in[16]:33 0.0004690313 +34 chanx_right_in[16]:34 0.0004154388 +35 chanx_right_in[16]:35 3.723417e-05 +36 chanx_right_in[16]:36 0.0001352013 +37 chanx_right_in[16]:37 0.0001352013 +38 chanx_right_in[16]:38 3.723417e-05 +39 chanx_right_in[16]:39 0.0005546613 +40 chanx_right_in[16]:40 0.0006182175 +41 chanx_right_in[16]:41 0.0004810587 +42 chanx_right_in[16]:42 0.0004175025 +43 chanx_right_in[16]:43 5.890143e-05 +44 chanx_right_in[16]:44 5.890143e-05 +45 chanx_right_in[16]:45 0.0002498026 +46 chanx_right_in[16]:46 0.0002498026 +47 chanx_right_in[16]:47 0.0007269242 +48 chanx_right_in[16]:48 0.0005461634 +49 chanx_right_in[16]:49 0.0001065107 +50 chanx_right_in[16]:50 5.854552e-05 +51 chanx_right_in[16]:51 5.854552e-05 +52 chanx_right_in[16]:52 0.000357184 +53 chanx_right_in[16]:53 0.000357184 +54 chanx_right_in[16]:54 0.001564829 +55 chanx_right_in[16]:55 0.001501384 +56 chanx_right_in[16]:42 chanx_right_in[9]:27 0.000136248 +57 chanx_right_in[16]:39 chanx_right_in[9]:21 0.0003599807 +58 chanx_right_in[16]:39 chanx_right_in[9]:26 0.0004067456 +59 chanx_right_in[16]:40 chanx_right_in[9]:26 0.0003599807 +60 chanx_right_in[16]:40 chanx_right_in[9]:27 0.0004067456 +61 chanx_right_in[16]:41 chanx_right_in[9]:26 0.000136248 +62 chanx_right_in[16]:54 chanx_right_in[10]:37 3.604823e-06 +63 chanx_right_in[16]:14 chanx_right_in[10]:9 1.40227e-06 +64 chanx_right_in[16]:13 chanx_right_in[10]:8 1.40227e-06 +65 chanx_right_in[16]:6 chanx_right_in[10]:29 7.937121e-06 +66 chanx_right_in[16]:5 chanx_right_in[10]:30 7.937121e-06 +67 chanx_right_in[16]:42 chanx_right_in[10]:28 0.0001083567 +68 chanx_right_in[16]:42 chanx_right_in[10]:33 2.417302e-05 +69 chanx_right_in[16]:39 chanx_right_in[10]:27 1.090152e-05 +70 chanx_right_in[16]:34 chanx_right_in[10]:28 1.899083e-05 +71 chanx_right_in[16]:31 chanx_right_in[10]:27 0.0001608121 +72 chanx_right_in[16]:32 chanx_right_in[10]:28 0.0001608121 +73 chanx_right_in[16]:33 chanx_right_in[10]:27 1.899083e-05 +74 chanx_right_in[16]:40 chanx_right_in[10]:28 1.090152e-05 +75 chanx_right_in[16]:41 chanx_right_in[10]:27 0.0001083567 +76 chanx_right_in[16]:41 chanx_right_in[10]:28 2.417302e-05 +77 chanx_right_in[16]:55 chanx_right_in[10] 3.604823e-06 +78 chanx_right_in[16]:39 chany_bottom_in[8]:29 0.0006734167 +79 chanx_right_in[16]:34 chany_bottom_in[8]:30 0.0002595953 +80 chanx_right_in[16]:32 chany_bottom_in[8]:28 1.922091e-05 +81 chanx_right_in[16]:33 chany_bottom_in[8]:27 1.922091e-05 +82 chanx_right_in[16]:33 chany_bottom_in[8]:29 0.0002595953 +83 chanx_right_in[16]:40 chany_bottom_in[8]:30 0.0006734167 +84 chanx_right_in[16]:20 chanx_left_in[9]:46 0.000243956 +85 chanx_right_in[16]:19 chanx_left_in[9]:47 0.000243956 +86 chanx_right_in[16]:30 chanx_left_in[9]:31 3.22716e-05 +87 chanx_right_in[16]:30 chanx_left_in[9]:30 3.033004e-05 +88 chanx_right_in[16]:29 chanx_left_in[9]:27 3.033004e-05 +89 chanx_right_in[16]:29 chanx_left_in[9]:30 3.22716e-05 +90 chanx_right_in[16]:54 prog_clk[0]:119 0.0002748921 +91 chanx_right_in[16]:22 prog_clk[0]:440 2.334038e-06 +92 chanx_right_in[16]:22 prog_clk[0]:441 3.226079e-06 +93 chanx_right_in[16]:21 prog_clk[0]:437 2.334038e-06 +94 chanx_right_in[16]:21 prog_clk[0]:440 3.226079e-06 +95 chanx_right_in[16]:20 prog_clk[0]:626 0.000117188 +96 chanx_right_in[16]:19 prog_clk[0]:627 0.000117188 +97 chanx_right_in[16]:55 prog_clk[0]:118 0.0002748921 +98 chanx_right_in[16]:49 chanx_right_in[1]:7 3.638021e-05 +99 chanx_right_in[16]:54 chanx_right_in[1]:8 3.638021e-05 +100 chanx_right_in[16]:54 chanx_right_in[1]:7 0.0003014329 +101 chanx_right_in[16]:55 chanx_right_in[1]:8 0.0003014329 +102 chanx_right_in[16]:49 chanx_right_in[3]:14 1.733523e-05 +103 chanx_right_in[16]:54 chanx_right_in[3] 1.733523e-05 +104 chanx_right_in[16]:54 chanx_right_in[3]:14 0.0006647045 +105 chanx_right_in[16]:55 chanx_right_in[3] 0.0006647045 +106 chanx_right_in[16]:54 chanx_right_out[16]:3 0.0003025988 +107 chanx_right_in[16]:55 chanx_right_out[16]:2 0.0003025988 +108 chanx_right_in[16]:26 mux_tree_tapbuf_size10_9_sram[0]:19 6.316046e-06 +109 chanx_right_in[16]:26 mux_tree_tapbuf_size10_9_sram[0]:16 5.473907e-06 +110 chanx_right_in[16]:25 mux_tree_tapbuf_size10_9_sram[0]:18 6.316046e-06 +111 chanx_right_in[16]:25 mux_tree_tapbuf_size10_9_sram[0]:17 5.473907e-06 +112 chanx_right_in[16]:20 mux_tree_tapbuf_size10_9_sram[0]:21 0.0001576352 +113 chanx_right_in[16]:20 mux_tree_tapbuf_size10_9_sram[0]:19 4.153689e-05 +114 chanx_right_in[16]:19 mux_tree_tapbuf_size10_9_sram[0]:22 0.0001576352 +115 chanx_right_in[16]:19 mux_tree_tapbuf_size10_9_sram[0]:20 4.153689e-05 +116 chanx_right_in[16]:30 mux_tree_tapbuf_size10_9_sram[0]:14 5.158616e-06 +117 chanx_right_in[16]:28 mux_tree_tapbuf_size10_9_sram[0]:6 1.128274e-06 +118 chanx_right_in[16]:29 mux_tree_tapbuf_size10_9_sram[0]:15 5.158616e-06 +119 chanx_right_in[16]:8 mux_tree_tapbuf_size10_9_sram[0]:7 3.688475e-05 +120 chanx_right_in[16]:10 mux_tree_tapbuf_size10_9_sram[0]:7 1.128274e-06 +121 chanx_right_in[16]:9 mux_tree_tapbuf_size10_9_sram[0]:6 3.688475e-05 +122 chanx_right_in[16]:27 mux_tree_tapbuf_size10_9_sram[3]:12 1.889096e-05 +123 chanx_right_in[16]:24 mux_tree_tapbuf_size10_9_sram[3]:13 0.0001125336 +124 chanx_right_in[16]:23 mux_tree_tapbuf_size10_9_sram[3]:12 0.0001125336 +125 chanx_right_in[16]:22 mux_tree_tapbuf_size10_9_sram[3]:6 1.716433e-05 +126 chanx_right_in[16]:21 mux_tree_tapbuf_size10_9_sram[3]:7 1.716433e-05 +127 chanx_right_in[16]:28 mux_tree_tapbuf_size10_9_sram[3]:13 1.889096e-05 +128 chanx_right_in[16]:48 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 7.03913e-05 +129 chanx_right_in[16]:47 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 7.03913e-05 +130 chanx_right_in[16]:14 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 7.966294e-06 +131 chanx_right_in[16]:12 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 3.695698e-05 +132 chanx_right_in[16]:13 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 7.966294e-06 +133 chanx_right_in[16]:11 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 3.695698e-05 +134 chanx_right_in[16]:20 optlc_net_150:38 1.930336e-05 +135 chanx_right_in[16]:20 optlc_net_150:15 0.0001856402 +136 chanx_right_in[16]:20 optlc_net_150:37 8.66187e-05 +137 chanx_right_in[16]:19 optlc_net_150:38 0.0001856402 +138 chanx_right_in[16]:19 optlc_net_150:31 8.66187e-05 +139 chanx_right_in[16]:19 optlc_net_150:37 1.930336e-05 +140 chanx_right_in[16]:14 optlc_net_150:30 5.310031e-07 +141 chanx_right_in[16]:14 optlc_net_150:29 9.822023e-08 +142 chanx_right_in[16]:13 optlc_net_150:28 9.822023e-08 +143 chanx_right_in[16]:13 optlc_net_150:29 5.310031e-07 +144 chanx_right_in[16]:30 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001551693 +145 chanx_right_in[16]:29 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001551693 +146 chanx_right_in[16]:28 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000154759 +147 chanx_right_in[16]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000154759 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:55 0.0001065333 +1 chanx_right_in[16]:48 chanx_right_in[16]:47 0.009055804 +2 chanx_right_in[16]:49 chanx_right_in[16]:48 0.00341 +3 chanx_right_in[16]:53 chanx_right_in[16]:52 0.005069196 +4 chanx_right_in[16]:54 chanx_right_in[16]:53 0.00341 +5 chanx_right_in[16]:54 chanx_right_in[16]:49 0.0002870917 +6 chanx_right_in[16]:51 chanx_right_in[16]:50 0.000421875 +7 chanx_right_in[16]:52 chanx_right_in[16]:51 0.0045 +8 chanx_right_in[16]:50 mux_bottom_track_9\/mux_l1_in_2_:A1 0.152 +9 chanx_right_in[16]:27 chanx_right_in[16]:26 0.0045 +10 chanx_right_in[16]:26 chanx_right_in[16]:25 0.001133929 +11 chanx_right_in[16]:24 chanx_right_in[16]:23 0.0044375 +12 chanx_right_in[16]:25 chanx_right_in[16]:24 0.0045 +13 chanx_right_in[16]:23 chanx_right_in[16]:22 0.0045 +14 chanx_right_in[16]:22 chanx_right_in[16]:21 0.001122768 +15 chanx_right_in[16]:21 chanx_right_in[16]:20 0.00341 +16 chanx_right_in[16]:20 chanx_right_in[16]:19 0.003743158 +17 chanx_right_in[16]:19 chanx_right_in[16]:18 0.00341 +18 chanx_right_in[16]:18 chanx_right_in[16]:17 0.001489117 +19 chanx_right_in[16]:16 chanx_right_in[16]:15 6.499219e-05 +20 chanx_right_in[16]:17 chanx_right_in[16]:16 0.00341 +21 chanx_right_in[16]:14 chanx_right_in[16]:13 0.000515625 +22 chanx_right_in[16]:15 chanx_right_in[16]:14 0.00341 +23 chanx_right_in[16]:12 chanx_right_in[16]:11 0.001979911 +24 chanx_right_in[16]:13 chanx_right_in[16]:12 0.0045 +25 chanx_right_in[16]:11 BUFT_P_121:A 0.152 +26 chanx_right_in[16]:6 chanx_right_in[16]:5 0.001658482 +27 chanx_right_in[16]:7 chanx_right_in[16]:6 0.0045 +28 chanx_right_in[16]:5 mux_top_track_8\/mux_l1_in_2_:A1 0.152 +29 chanx_right_in[16]:46 chanx_right_in[16]:45 0.003205357 +30 chanx_right_in[16]:47 chanx_right_in[16]:46 0.0045 +31 chanx_right_in[16]:47 chanx_right_in[16]:7 0.002084821 +32 chanx_right_in[16]:45 chanx_right_in[16]:44 0.0045 +33 chanx_right_in[16]:44 chanx_right_in[16]:43 0.0005156251 +34 chanx_right_in[16]:43 chanx_right_in[16]:42 0.00341 +35 chanx_right_in[16]:42 chanx_right_in[16]:41 0.001223958 +36 chanx_right_in[16]:38 chanx_right_in[16]:37 0.0045 +37 chanx_right_in[16]:39 chanx_right_in[16]:38 0.00341 +38 chanx_right_in[16]:37 chanx_right_in[16]:36 0.0015625 +39 chanx_right_in[16]:36 chanx_right_in[16]:35 0.0045 +40 chanx_right_in[16]:35 chanx_right_in[16]:34 0.00341 +41 chanx_right_in[16]:34 chanx_right_in[16]:33 0.001079825 +42 chanx_right_in[16]:30 chanx_right_in[16]:29 0.02055134 +43 chanx_right_in[16]:31 chanx_right_in[16]:30 0.00341 +44 chanx_right_in[16]:28 chanx_right_in[16]:27 0.006941965 +45 chanx_right_in[16]:28 chanx_right_in[16]:10 0.01519643 +46 chanx_right_in[16]:29 chanx_right_in[16]:28 0.0045 +47 chanx_right_in[16]:8 mux_left_track_9\/mux_l1_in_2_:A1 0.152 +48 chanx_right_in[16]:10 chanx_right_in[16]:9 0.0003035715 +49 chanx_right_in[16]:9 chanx_right_in[16]:8 0.000703125 +50 chanx_right_in[16]:32 chanx_right_in[16]:31 0.001368092 +51 chanx_right_in[16]:33 chanx_right_in[16]:32 0.0001065333 +52 chanx_right_in[16]:40 chanx_right_in[16]:39 0.002377025 +53 chanx_right_in[16]:41 chanx_right_in[16]:40 0.0001065333 +54 chanx_right_in[16]:55 chanx_right_in[16]:54 0.007134599 + +*END + +*D_NET chany_bottom_in[13] 0.02672597 //LENGTH 173.875 LUMPCC 0.01124881 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 68.080 1.325 +*I mux_top_track_2\/mux_l1_in_4_:A1 I *L 0.00198 *C 62.005 85.340 +*I mux_right_track_2\/mux_l1_in_4_:A0 I *L 0.001631 *C 90.795 91.460 +*I FTB_35__34:A I *L 0.001776 *C 96.600 118.320 +*I mux_left_track_3\/mux_l1_in_3_:A0 I *L 0.001631 *C 67.450 97.240 +*N chany_bottom_in[13]:5 *C 64.000 89.080 +*N chany_bottom_in[13]:6 *C 67.413 97.240 +*N chany_bottom_in[13]:7 *C 64.905 97.240 +*N chany_bottom_in[13]:8 *C 64.860 97.195 +*N chany_bottom_in[13]:9 *C 96.562 118.320 +*N chany_bottom_in[13]:10 *C 96.185 118.320 +*N chany_bottom_in[13]:11 *C 96.140 118.320 +*N chany_bottom_in[13]:12 *C 96.133 118.320 +*N chany_bottom_in[13]:13 *C 91.100 118.320 +*N chany_bottom_in[13]:14 *C 91.080 118.312 +*N chany_bottom_in[13]:15 *C 90.370 91.460 +*N chany_bottom_in[13]:16 *C 90.795 91.460 +*N chany_bottom_in[13]:17 *C 91.080 91.460 +*N chany_bottom_in[13]:18 *C 91.080 91.460 +*N chany_bottom_in[13]:19 *C 91.078 91.460 +*N chany_bottom_in[13]:20 *C 91.080 91.460 +*N chany_bottom_in[13]:21 *C 91.080 90.448 +*N chany_bottom_in[13]:22 *C 91.060 90.440 +*N chany_bottom_in[13]:23 *C 64.868 90.440 +*N chany_bottom_in[13]:24 *C 64.860 90.440 +*N chany_bottom_in[13]:25 *C 64.860 89.760 +*N chany_bottom_in[13]:26 *C 64.400 89.760 +*N chany_bottom_in[13]:27 *C 62.043 85.340 +*N chany_bottom_in[13]:28 *C 64.355 85.340 +*N chany_bottom_in[13]:29 *C 64.400 85.385 +*N chany_bottom_in[13]:30 *C 64.400 89.080 +*N chany_bottom_in[13]:31 *C 64.400 89.080 +*N chany_bottom_in[13]:32 *C 64.400 89.073 +*N chany_bottom_in[13]:33 *C 64.400 51.875 +*N chany_bottom_in[13]:34 *C 64.400 2.048 +*N chany_bottom_in[13]:35 *C 64.420 2.040 +*N chany_bottom_in[13]:36 *C 68.073 2.040 +*N chany_bottom_in[13]:37 *C 68.080 1.983 + +*CAP +0 chany_bottom_in[13] 4.739431e-05 +1 mux_top_track_2\/mux_l1_in_4_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_4_:A0 1e-06 +3 FTB_35__34:A 1e-06 +4 mux_left_track_3\/mux_l1_in_3_:A0 1e-06 +5 chany_bottom_in[13]:5 0.0001045419 +6 chany_bottom_in[13]:6 0.0002301132 +7 chany_bottom_in[13]:7 0.0002301132 +8 chany_bottom_in[13]:8 0.0004960685 +9 chany_bottom_in[13]:9 4.150075e-05 +10 chany_bottom_in[13]:10 4.150075e-05 +11 chany_bottom_in[13]:11 3.397834e-05 +12 chany_bottom_in[13]:12 0.0002769352 +13 chany_bottom_in[13]:13 0.0002769352 +14 chany_bottom_in[13]:14 0.001441574 +15 chany_bottom_in[13]:15 0.0001143525 +16 chany_bottom_in[13]:16 5.555108e-05 +17 chany_bottom_in[13]:17 6.030434e-05 +18 chany_bottom_in[13]:18 3.913759e-05 +19 chany_bottom_in[13]:19 0.0001143525 +20 chany_bottom_in[13]:20 0.001516951 +21 chany_bottom_in[13]:21 7.537747e-05 +22 chany_bottom_in[13]:22 0.001417537 +23 chany_bottom_in[13]:23 0.001417537 +24 chany_bottom_in[13]:24 0.0005900724 +25 chany_bottom_in[13]:25 8.745529e-05 +26 chany_bottom_in[13]:26 7.967076e-05 +27 chany_bottom_in[13]:27 0.0001547744 +28 chany_bottom_in[13]:28 0.0001547744 +29 chany_bottom_in[13]:29 0.0002158442 +30 chany_bottom_in[13]:30 0.0002900659 +31 chany_bottom_in[13]:31 0.0001045419 +32 chany_bottom_in[13]:32 0.001487882 +33 chany_bottom_in[13]:33 0.002647349 +34 chany_bottom_in[13]:34 0.001159466 +35 chany_bottom_in[13]:35 0.0002110541 +36 chany_bottom_in[13]:36 0.0002110541 +37 chany_bottom_in[13]:37 4.739431e-05 +38 chany_bottom_in[13]:14 chanx_right_in[14]:39 3.082961e-05 +39 chany_bottom_in[13]:23 chanx_right_in[14]:37 0.0006890473 +40 chany_bottom_in[13]:22 chanx_right_in[14]:38 0.0006890473 +41 chany_bottom_in[13]:19 chanx_right_in[14]:37 8.574038e-06 +42 chany_bottom_in[13]:20 chanx_right_in[14]:38 3.082961e-05 +43 chany_bottom_in[13]:15 chanx_right_in[14]:38 8.574038e-06 +44 chany_bottom_in[13]:30 chany_bottom_in[10]:31 2.251985e-05 +45 chany_bottom_in[13]:30 chany_bottom_in[10]:32 1.480428e-05 +46 chany_bottom_in[13]:32 chany_bottom_in[10]:31 7.400994e-06 +47 chany_bottom_in[13]:32 chany_bottom_in[10]:44 0.0005873766 +48 chany_bottom_in[13]:32 chany_bottom_in[10]:45 1.209272e-05 +49 chany_bottom_in[13]:34 chany_bottom_in[10]:46 0.0009610465 +50 chany_bottom_in[13]:29 chany_bottom_in[10]:30 2.251985e-05 +51 chany_bottom_in[13]:29 chany_bottom_in[10]:43 1.480428e-05 +52 chany_bottom_in[13]:33 chany_bottom_in[10]:30 7.400994e-06 +53 chany_bottom_in[13]:33 chany_bottom_in[10]:45 0.001548423 +54 chany_bottom_in[13]:33 chany_bottom_in[10]:46 1.209272e-05 +55 chany_bottom_in[13]:32 chany_bottom_in[18]:15 0.0003273754 +56 chany_bottom_in[13]:33 chany_bottom_in[18]:16 0.0003273754 +57 chany_bottom_in[13]:14 chanx_right_in[3]:9 2.682523e-06 +58 chany_bottom_in[13]:23 chanx_right_in[3]:7 0.0003366751 +59 chany_bottom_in[13]:22 chanx_right_in[3]:8 0.0003366751 +60 chany_bottom_in[13]:21 chanx_right_in[3]:10 6.294634e-06 +61 chany_bottom_in[13]:20 chanx_right_in[3]:10 2.682523e-06 +62 chany_bottom_in[13]:20 chanx_right_in[3]:9 6.294634e-06 +63 chany_bottom_in[13] chany_bottom_in[1] 1.019082e-05 +64 chany_bottom_in[13]:32 chany_bottom_in[1]:20 0.0002571578 +65 chany_bottom_in[13]:32 chany_bottom_in[1]:9 1.94498e-05 +66 chany_bottom_in[13]:32 chany_bottom_in[1]:21 2.875098e-05 +67 chany_bottom_in[13]:35 chany_bottom_in[1]:23 0.0001179874 +68 chany_bottom_in[13]:34 chany_bottom_in[1]:22 0.002099077 +69 chany_bottom_in[13]:37 chany_bottom_in[1]:25 1.019082e-05 +70 chany_bottom_in[13]:36 chany_bottom_in[1]:24 0.0001179874 +71 chany_bottom_in[13]:33 chany_bottom_in[1]:15 1.94498e-05 +72 chany_bottom_in[13]:33 chany_bottom_in[1]:22 2.875098e-05 +73 chany_bottom_in[13]:33 chany_bottom_in[1]:21 0.002356235 +74 chany_bottom_in[13]:28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.507335e-05 +75 chany_bottom_in[13]:27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.507335e-05 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:37 0.0005870535 +1 chany_bottom_in[13]:30 chany_bottom_in[13]:29 0.003299107 +2 chany_bottom_in[13]:30 chany_bottom_in[13]:26 0.0006071429 +3 chany_bottom_in[13]:31 chany_bottom_in[13]:30 0.00341 +4 chany_bottom_in[13]:31 chany_bottom_in[13]:5 5.69697e-05 +5 chany_bottom_in[13]:32 chany_bottom_in[13]:31 0.00341 +6 chany_bottom_in[13]:35 chany_bottom_in[13]:34 0.00341 +7 chany_bottom_in[13]:34 chany_bottom_in[13]:33 0.007806308 +8 chany_bottom_in[13]:37 chany_bottom_in[13]:36 0.00341 +9 chany_bottom_in[13]:36 chany_bottom_in[13]:35 0.000572225 +10 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.000788425 +11 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.00341 +12 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.0045 +13 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.00341 +14 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.0003370536 +15 chany_bottom_in[13]:9 FTB_35__34:A 0.152 +16 chany_bottom_in[13]:24 chany_bottom_in[13]:23 0.00341 +17 chany_bottom_in[13]:24 chany_bottom_in[13]:8 0.00603125 +18 chany_bottom_in[13]:23 chany_bottom_in[13]:22 0.004103492 +19 chany_bottom_in[13]:22 chany_bottom_in[13]:21 0.00341 +20 chany_bottom_in[13]:21 chany_bottom_in[13]:20 0.000158625 +21 chany_bottom_in[13]:19 chany_bottom_in[13]:18 0.00341 +22 chany_bottom_in[13]:19 chany_bottom_in[13]:15 0.0001039141 +23 chany_bottom_in[13]:20 chany_bottom_in[13]:19 0.00341 +24 chany_bottom_in[13]:20 chany_bottom_in[13]:14 0.004206892 +25 chany_bottom_in[13]:18 chany_bottom_in[13]:17 0.0045 +26 chany_bottom_in[13]:17 chany_bottom_in[13]:16 0.0001548913 +27 chany_bottom_in[13]:16 mux_right_track_2\/mux_l1_in_4_:A0 0.152 +28 chany_bottom_in[13]:28 chany_bottom_in[13]:27 0.002064732 +29 chany_bottom_in[13]:29 chany_bottom_in[13]:28 0.0045 +30 chany_bottom_in[13]:27 mux_top_track_2\/mux_l1_in_4_:A1 0.152 +31 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.002238839 +32 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.0045 +33 chany_bottom_in[13]:6 mux_left_track_3\/mux_l1_in_3_:A0 0.152 +34 chany_bottom_in[13]:26 chany_bottom_in[13]:25 0.0004107143 +35 chany_bottom_in[13]:25 chany_bottom_in[13]:24 0.0006071429 +36 chany_bottom_in[13]:33 chany_bottom_in[13]:32 0.005827608 + +*END + +*D_NET chanx_left_in[5] 0.03283615 //LENGTH 203.565 LUMPCC 0.01320954 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 87.040 +*I mux_right_track_4\/mux_l2_in_6_:A0 I *L 0.001631 *C 111.955 75.140 +*I BUFT_P_124:A I *L 0.001776 *C 131.560 63.920 +*I mux_top_track_4\/mux_l2_in_6_:A1 I *L 0.00198 *C 35.060 79.900 +*I mux_bottom_track_5\/mux_l2_in_6_:A1 I *L 0.00198 *C 29.080 39.780 +*N chanx_left_in[5]:5 *C 29.117 39.780 +*N chanx_left_in[5]:6 *C 29.440 39.780 +*N chanx_left_in[5]:7 *C 29.440 40.120 +*N chanx_left_in[5]:8 *C 31.235 40.120 +*N chanx_left_in[5]:9 *C 31.280 40.165 +*N chanx_left_in[5]:10 *C 35.060 79.900 +*N chanx_left_in[5]:11 *C 131.597 63.920 +*N chanx_left_in[5]:12 *C 131.975 63.920 +*N chanx_left_in[5]:13 *C 132.020 63.965 +*N chanx_left_in[5]:14 *C 132.020 67.943 +*N chanx_left_in[5]:15 *C 132.013 68.000 +*N chanx_left_in[5]:16 *C 112.248 68.000 +*N chanx_left_in[5]:17 *C 112.240 68.058 +*N chanx_left_in[5]:18 *C 112.240 75.095 +*N chanx_left_in[5]:19 *C 112.240 75.140 +*N chanx_left_in[5]:20 *C 111.918 75.140 +*N chanx_left_in[5]:21 *C 110.905 75.140 +*N chanx_left_in[5]:22 *C 110.860 75.185 +*N chanx_left_in[5]:23 *C 110.860 76.782 +*N chanx_left_in[5]:24 *C 110.853 76.840 +*N chanx_left_in[5]:25 *C 84.795 76.840 +*N chanx_left_in[5]:26 *C 34.968 76.840 +*N chanx_left_in[5]:27 *C 34.960 76.898 +*N chanx_left_in[5]:28 *C 34.960 79.515 +*N chanx_left_in[5]:29 *C 35.005 79.568 +*N chanx_left_in[5]:30 *C 31.325 79.560 +*N chanx_left_in[5]:31 *C 31.280 79.545 +*N chanx_left_in[5]:32 *C 31.235 79.900 +*N chanx_left_in[5]:33 *C 30.820 79.900 +*N chanx_left_in[5]:34 *C 30.820 87.663 +*N chanx_left_in[5]:35 *C 30.812 87.720 +*N chanx_left_in[5]:36 *C 5.520 87.720 +*N chanx_left_in[5]:37 *C 5.520 87.040 + +*CAP +0 chanx_left_in[5] 0.0002853664 +1 mux_right_track_4\/mux_l2_in_6_:A0 1e-06 +2 BUFT_P_124:A 1e-06 +3 mux_top_track_4\/mux_l2_in_6_:A1 1e-06 +4 mux_bottom_track_5\/mux_l2_in_6_:A1 1e-06 +5 chanx_left_in[5]:5 3.490339e-05 +6 chanx_left_in[5]:6 5.959446e-05 +7 chanx_left_in[5]:7 0.000162021 +8 chanx_left_in[5]:8 0.0001373299 +9 chanx_left_in[5]:9 0.002113052 +10 chanx_left_in[5]:10 6.299874e-05 +11 chanx_left_in[5]:11 5.382581e-05 +12 chanx_left_in[5]:12 5.382581e-05 +13 chanx_left_in[5]:13 0.0003096193 +14 chanx_left_in[5]:14 0.0003096193 +15 chanx_left_in[5]:15 0.0005456633 +16 chanx_left_in[5]:16 0.0005456633 +17 chanx_left_in[5]:17 0.0004482712 +18 chanx_left_in[5]:18 0.0004482712 +19 chanx_left_in[5]:19 5.626986e-05 +20 chanx_left_in[5]:20 0.0001057046 +21 chanx_left_in[5]:21 8.464357e-05 +22 chanx_left_in[5]:22 0.0001074021 +23 chanx_left_in[5]:23 0.0001074021 +24 chanx_left_in[5]:24 0.001010379 +25 chanx_left_in[5]:25 0.003226715 +26 chanx_left_in[5]:26 0.002216336 +27 chanx_left_in[5]:27 0.0001653237 +28 chanx_left_in[5]:28 0.0001653237 +29 chanx_left_in[5]:29 0.0003065187 +30 chanx_left_in[5]:30 0.0002721887 +31 chanx_left_in[5]:31 0.002151301 +32 chanx_left_in[5]:32 7.018735e-05 +33 chanx_left_in[5]:33 0.0005392496 +34 chanx_left_in[5]:34 0.000507311 +35 chanx_left_in[5]:35 0.001287873 +36 chanx_left_in[5]:36 0.001337485 +37 chanx_left_in[5]:37 0.0003349787 +38 chanx_left_in[5]:24 chany_bottom_in[16]:18 0.0001611345 +39 chanx_left_in[5]:26 chany_bottom_in[16]:17 0.0005930801 +40 chanx_left_in[5]:25 chany_bottom_in[16]:17 0.0001611345 +41 chanx_left_in[5]:25 chany_bottom_in[16]:18 0.0005930801 +42 chanx_left_in[5]:35 chanx_left_in[13]:32 0.0010527 +43 chanx_left_in[5]:36 chanx_left_in[13]:33 0.0010527 +44 chanx_left_in[5]:24 prog_clk[0]:272 0.0002281041 +45 chanx_left_in[5]:24 prog_clk[0]:276 0.0002802371 +46 chanx_left_in[5]:26 prog_clk[0]:277 0.0001136475 +47 chanx_left_in[5]:26 prog_clk[0]:436 3.723371e-06 +48 chanx_left_in[5]:34 prog_clk[0]:617 6.743878e-06 +49 chanx_left_in[5]:9 prog_clk[0]:463 5.756327e-05 +50 chanx_left_in[5]:9 prog_clk[0]:478 7.619688e-05 +51 chanx_left_in[5]:9 prog_clk[0]:476 1.549736e-05 +52 chanx_left_in[5]:9 prog_clk[0]:462 2.129675e-05 +53 chanx_left_in[5]:9 prog_clk[0]:410 8.76943e-07 +54 chanx_left_in[5]:31 prog_clk[0]:466 1.549736e-05 +55 chanx_left_in[5]:31 prog_clk[0]:463 2.129675e-05 +56 chanx_left_in[5]:31 prog_clk[0]:459 5.756327e-05 +57 chanx_left_in[5]:31 prog_clk[0]:409 8.76943e-07 +58 chanx_left_in[5]:31 prog_clk[0]:477 7.619688e-05 +59 chanx_left_in[5]:33 prog_clk[0]:493 6.743878e-06 +60 chanx_left_in[5]:25 prog_clk[0]:277 0.0002802371 +61 chanx_left_in[5]:25 prog_clk[0]:276 0.0003417516 +62 chanx_left_in[5]:25 prog_clk[0]:435 3.723371e-06 +63 chanx_left_in[5]:26 chany_top_in[15]:8 0.001019746 +64 chanx_left_in[5]:25 chany_top_in[15]:7 0.001019746 +65 chanx_left_in[5]:18 chanx_right_in[7]:24 3.156308e-05 +66 chanx_left_in[5]:17 chanx_right_in[7]:25 3.156308e-05 +67 chanx_left_in[5]:16 chanx_right_in[7]:26 0.0004894849 +68 chanx_left_in[5]:15 chanx_right_in[7] 0.0004894849 +69 chanx_left_in[5]:26 chany_bottom_in[15]:8 0.0001542703 +70 chanx_left_in[5]:26 chany_bottom_in[15]:14 8.125293e-05 +71 chanx_left_in[5]:26 chany_bottom_in[15]:16 0.0004653293 +72 chanx_left_in[5]:25 chany_bottom_in[15]:7 0.0001542703 +73 chanx_left_in[5]:25 chany_bottom_in[15]:17 0.0004653293 +74 chanx_left_in[5]:25 chany_bottom_in[15]:15 8.125293e-05 +75 chanx_left_in[5]:26 chanx_left_in[15] 0.0002911511 +76 chanx_left_in[5]:25 chanx_left_in[15]:9 0.0002911511 +77 chanx_left_in[5]:16 mux_tree_tapbuf_size10_3_sram[0]:21 0.0002998859 +78 chanx_left_in[5]:15 mux_tree_tapbuf_size10_3_sram[0]:22 0.0002998859 +79 chanx_left_in[5]:22 optlc_net_151:26 6.314344e-09 +80 chanx_left_in[5]:23 optlc_net_151:27 6.314344e-09 +81 chanx_left_in[5]:24 optlc_net_151:25 0.0006950388 +82 chanx_left_in[5]:25 optlc_net_151:24 0.0006950388 +83 chanx_left_in[5]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001378693 +84 chanx_left_in[5]:31 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001378693 +85 chanx_left_in[5]:24 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002448404 +86 chanx_left_in[5]:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002448404 +87 chanx_left_in[5] ropt_net_232:6 7.170558e-05 +88 chanx_left_in[5]:37 ropt_net_232:5 1.182395e-05 +89 chanx_left_in[5]:37 ropt_net_232:7 7.170558e-05 +90 chanx_left_in[5]:36 ropt_net_232:4 1.182395e-05 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:37 0.0006721 +1 chanx_left_in[5]:21 chanx_left_in[5]:20 0.0009040179 +2 chanx_left_in[5]:22 chanx_left_in[5]:21 0.0045 +3 chanx_left_in[5]:23 chanx_left_in[5]:22 0.001426339 +4 chanx_left_in[5]:24 chanx_left_in[5]:23 0.00341 +5 chanx_left_in[5]:27 chanx_left_in[5]:26 0.00341 +6 chanx_left_in[5]:26 chanx_left_in[5]:25 0.007806308 +7 chanx_left_in[5]:29 chanx_left_in[5]:28 0.0045 +8 chanx_left_in[5]:29 chanx_left_in[5]:10 0.0001807065 +9 chanx_left_in[5]:28 chanx_left_in[5]:27 0.002337054 +10 chanx_left_in[5]:19 chanx_left_in[5]:18 0.0045 +11 chanx_left_in[5]:18 chanx_left_in[5]:17 0.006283483 +12 chanx_left_in[5]:17 chanx_left_in[5]:16 0.00341 +13 chanx_left_in[5]:16 chanx_left_in[5]:15 0.003096516 +14 chanx_left_in[5]:14 chanx_left_in[5]:13 0.003551339 +15 chanx_left_in[5]:15 chanx_left_in[5]:14 0.00341 +16 chanx_left_in[5]:12 chanx_left_in[5]:11 0.0003370536 +17 chanx_left_in[5]:13 chanx_left_in[5]:12 0.0045 +18 chanx_left_in[5]:11 BUFT_P_124:A 0.152 +19 chanx_left_in[5]:10 mux_top_track_4\/mux_l2_in_6_:A1 0.152 +20 chanx_left_in[5]:34 chanx_left_in[5]:33 0.006930804 +21 chanx_left_in[5]:35 chanx_left_in[5]:34 0.00341 +22 chanx_left_in[5]:8 chanx_left_in[5]:7 0.001602679 +23 chanx_left_in[5]:9 chanx_left_in[5]:8 0.0045 +24 chanx_left_in[5]:5 mux_bottom_track_5\/mux_l2_in_6_:A1 0.152 +25 chanx_left_in[5]:20 mux_right_track_4\/mux_l2_in_6_:A0 0.152 +26 chanx_left_in[5]:20 chanx_left_in[5]:19 0.0001752717 +27 chanx_left_in[5]:30 chanx_left_in[5]:29 0.003285714 +28 chanx_left_in[5]:31 chanx_left_in[5]:30 0.0045 +29 chanx_left_in[5]:31 chanx_left_in[5]:9 0.03516072 +30 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0002879465 +31 chanx_left_in[5]:7 chanx_left_in[5]:6 0.0003035715 +32 chanx_left_in[5]:33 chanx_left_in[5]:32 0.0003705357 +33 chanx_left_in[5]:32 chanx_left_in[5]:31 0.000221875 +34 chanx_left_in[5]:37 chanx_left_in[5]:36 0.0001065333 +35 chanx_left_in[5]:36 chanx_left_in[5]:35 0.003962492 +36 chanx_left_in[5]:25 chanx_left_in[5]:24 0.004082341 + +*END + +*D_NET chanx_left_in[16] 0.02910034 //LENGTH 183.770 LUMPCC 0.01055883 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 51.680 +*I mux_top_track_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 107.180 41.820 +*I mux_bottom_track_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 103.405 34.340 +*I ropt_mt_inst_795:A I *L 0.001767 *C 130.180 69.360 +*I mux_right_track_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 110.860 52.700 +*N chanx_left_in[16]:5 *C 110.860 52.715 +*N chanx_left_in[16]:6 *C 130.218 69.360 +*N chanx_left_in[16]:7 *C 132.435 69.360 +*N chanx_left_in[16]:8 *C 132.480 69.315 +*N chanx_left_in[16]:9 *C 132.480 61.925 +*N chanx_left_in[16]:10 *C 132.435 61.880 +*N chanx_left_in[16]:11 *C 126.085 61.880 +*N chanx_left_in[16]:12 *C 126.040 61.835 +*N chanx_left_in[16]:13 *C 126.040 55.805 +*N chanx_left_in[16]:14 *C 125.995 55.760 +*N chanx_left_in[16]:15 *C 123.740 55.760 +*N chanx_left_in[16]:16 *C 123.740 55.715 +*N chanx_left_in[16]:17 *C 123.740 53.085 +*N chanx_left_in[16]:18 *C 123.695 53.040 +*N chanx_left_in[16]:19 *C 110.860 53.040 +*N chanx_left_in[16]:20 *C 109.525 53.040 +*N chanx_left_in[16]:21 *C 109.480 52.995 +*N chanx_left_in[16]:22 *C 103.443 34.340 +*N chanx_left_in[16]:23 *C 107.135 34.340 +*N chanx_left_in[16]:24 *C 107.180 34.385 +*N chanx_left_in[16]:25 *C 107.180 41.725 +*N chanx_left_in[16]:26 *C 107.180 41.820 +*N chanx_left_in[16]:27 *C 107.180 42.160 +*N chanx_left_in[16]:28 *C 107.225 42.160 +*N chanx_left_in[16]:29 *C 107.640 42.160 +*N chanx_left_in[16]:30 *C 107.640 45.175 +*N chanx_left_in[16]:31 *C 107.685 45.220 +*N chanx_left_in[16]:32 *C 109.435 45.220 +*N chanx_left_in[16]:33 *C 109.480 45.265 +*N chanx_left_in[16]:34 *C 109.480 52.360 +*N chanx_left_in[16]:35 *C 109.473 52.360 +*N chanx_left_in[16]:36 *C 86.480 52.360 +*N chanx_left_in[16]:37 *C 86.480 51.680 +*N chanx_left_in[16]:38 *C 74.520 51.680 +*N chanx_left_in[16]:39 *C 74.520 52.360 +*N chanx_left_in[16]:40 *C 39.560 52.360 +*N chanx_left_in[16]:41 *C 39.560 51.680 + +*CAP +0 chanx_left_in[16] 0.001468153 +1 mux_top_track_8\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_track_9\/mux_l2_in_3_:A1 1e-06 +3 ropt_mt_inst_795:A 1e-06 +4 mux_right_track_8\/mux_l2_in_3_:A1 1e-06 +5 chanx_left_in[16]:5 3.209989e-05 +6 chanx_left_in[16]:6 0.0001235054 +7 chanx_left_in[16]:7 0.0001235054 +8 chanx_left_in[16]:8 0.0004748498 +9 chanx_left_in[16]:9 0.0004748498 +10 chanx_left_in[16]:10 0.0004256373 +11 chanx_left_in[16]:11 0.0004256373 +12 chanx_left_in[16]:12 0.0003438527 +13 chanx_left_in[16]:13 0.0003438527 +14 chanx_left_in[16]:14 0.0001496327 +15 chanx_left_in[16]:15 0.0001868165 +16 chanx_left_in[16]:16 0.0001624871 +17 chanx_left_in[16]:17 0.0001624871 +18 chanx_left_in[16]:18 0.0005600585 +19 chanx_left_in[16]:19 0.0006637508 +20 chanx_left_in[16]:20 7.159244e-05 +21 chanx_left_in[16]:21 4.439585e-05 +22 chanx_left_in[16]:22 0.0002942246 +23 chanx_left_in[16]:23 0.0002942246 +24 chanx_left_in[16]:24 0.0003989723 +25 chanx_left_in[16]:25 0.0004313276 +26 chanx_left_in[16]:26 7.207863e-05 +27 chanx_left_in[16]:27 7.729928e-05 +28 chanx_left_in[16]:28 6.733407e-05 +29 chanx_left_in[16]:29 0.0002323254 +30 chanx_left_in[16]:30 0.0001973466 +31 chanx_left_in[16]:31 0.0001300939 +32 chanx_left_in[16]:32 0.0001300939 +33 chanx_left_in[16]:33 0.0004187631 +34 chanx_left_in[16]:34 0.0004980332 +35 chanx_left_in[16]:35 0.000926964 +36 chanx_left_in[16]:36 0.0009965356 +37 chanx_left_in[16]:37 0.0006388518 +38 chanx_left_in[16]:38 0.0006269336 +39 chanx_left_in[16]:39 0.002173143 +40 chanx_left_in[16]:40 0.002171568 +41 chanx_left_in[16]:41 0.001524231 +42 chanx_left_in[16] chanx_right_in[5]:12 0.0003474434 +43 chanx_left_in[16]:41 chanx_right_in[5]:13 0.0003474434 +44 chanx_left_in[16]:41 chanx_right_in[5]:14 5.675786e-06 +45 chanx_left_in[16]:40 chanx_right_in[5]:12 1.454578e-05 +46 chanx_left_in[16]:40 chanx_right_in[5]:15 5.675786e-06 +47 chanx_left_in[16]:39 chanx_right_in[5]:13 1.454578e-05 +48 chanx_left_in[16] chanx_right_in[9]:16 0.0006472813 +49 chanx_left_in[16]:18 chanx_right_in[9]:27 1.165929e-05 +50 chanx_left_in[16]:35 chanx_right_in[9]:27 0.0004183963 +51 chanx_left_in[16]:19 chanx_right_in[9]:26 1.165929e-05 +52 chanx_left_in[16]:41 chanx_right_in[9]:17 0.0006472813 +53 chanx_left_in[16]:40 chanx_right_in[9]:16 0.001086959 +54 chanx_left_in[16]:40 chanx_right_in[9]:17 0.0003620988 +55 chanx_left_in[16]:40 chanx_right_in[9]:21 8.421345e-05 +56 chanx_left_in[16]:40 chanx_right_in[9]:26 1.165159e-05 +57 chanx_left_in[16]:39 chanx_right_in[9]:17 0.001086959 +58 chanx_left_in[16]:39 chanx_right_in[9]:18 0.0003620988 +59 chanx_left_in[16]:39 chanx_right_in[9]:26 8.421345e-05 +60 chanx_left_in[16]:39 chanx_right_in[9]:27 1.165159e-05 +61 chanx_left_in[16]:38 chanx_right_in[9]:26 0.0006339292 +62 chanx_left_in[16]:37 chanx_right_in[9]:27 0.0006339292 +63 chanx_left_in[16]:36 chanx_right_in[9]:26 0.0004183963 +64 chanx_left_in[16]:35 chany_bottom_in[6]:26 0.0003947149 +65 chanx_left_in[16]:38 chany_bottom_in[6]:25 0.0001067369 +66 chanx_left_in[16]:37 chany_bottom_in[6]:26 0.0001067369 +67 chanx_left_in[16]:36 chany_bottom_in[6]:25 0.0003947149 +68 chanx_left_in[16]:18 chanx_right_in[0]:12 5.927877e-06 +69 chanx_left_in[16]:35 chanx_right_in[0]:12 0.000330202 +70 chanx_left_in[16]:19 chanx_right_in[0]:11 5.927877e-06 +71 chanx_left_in[16]:39 chanx_right_in[0]:6 1.320167e-05 +72 chanx_left_in[16]:38 chanx_right_in[0]:7 2.709563e-05 +73 chanx_left_in[16]:38 chanx_right_in[0]:5 1.320167e-05 +74 chanx_left_in[16]:37 chanx_right_in[0]:11 2.709563e-05 +75 chanx_left_in[16]:36 chanx_right_in[0]:11 0.000330202 +76 chanx_left_in[16] chanx_left_in[19]:13 0.0004945333 +77 chanx_left_in[16]:41 chanx_left_in[19]:12 0.0004945333 +78 chanx_left_in[16]:18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001640464 +79 chanx_left_in[16]:20 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.631147e-05 +80 chanx_left_in[16]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.631147e-05 +81 chanx_left_in[16]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001640464 +82 chanx_left_in[16]:9 ropt_net_244:4 6.398578e-07 +83 chanx_left_in[16]:7 ropt_net_244:6 6.215069e-05 +84 chanx_left_in[16]:8 ropt_net_244:5 6.398578e-07 +85 chanx_left_in[16]:6 ropt_net_244:7 6.215069e-05 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:41 0.006005032 +1 chanx_left_in[16]:18 chanx_left_in[16]:17 0.0045 +2 chanx_left_in[16]:17 chanx_left_in[16]:16 0.002348214 +3 chanx_left_in[16]:15 chanx_left_in[16]:14 0.002013393 +4 chanx_left_in[16]:16 chanx_left_in[16]:15 0.0045 +5 chanx_left_in[16]:14 chanx_left_in[16]:13 0.0045 +6 chanx_left_in[16]:13 chanx_left_in[16]:12 0.005383929 +7 chanx_left_in[16]:11 chanx_left_in[16]:10 0.005669643 +8 chanx_left_in[16]:12 chanx_left_in[16]:11 0.0045 +9 chanx_left_in[16]:10 chanx_left_in[16]:9 0.0045 +10 chanx_left_in[16]:9 chanx_left_in[16]:8 0.006598215 +11 chanx_left_in[16]:7 chanx_left_in[16]:6 0.001979911 +12 chanx_left_in[16]:8 chanx_left_in[16]:7 0.0045 +13 chanx_left_in[16]:6 ropt_mt_inst_795:A 0.152 +14 chanx_left_in[16]:34 chanx_left_in[16]:33 0.006334822 +15 chanx_left_in[16]:34 chanx_left_in[16]:21 0.0005669643 +16 chanx_left_in[16]:35 chanx_left_in[16]:34 0.00341 +17 chanx_left_in[16]:23 chanx_left_in[16]:22 0.003296875 +18 chanx_left_in[16]:24 chanx_left_in[16]:23 0.0045 +19 chanx_left_in[16]:22 mux_bottom_track_9\/mux_l2_in_3_:A1 0.152 +20 chanx_left_in[16]:20 chanx_left_in[16]:19 0.001191964 +21 chanx_left_in[16]:21 chanx_left_in[16]:20 0.0045 +22 chanx_left_in[16]:5 mux_right_track_8\/mux_l2_in_3_:A1 0.152 +23 chanx_left_in[16]:27 chanx_left_in[16]:26 0.0001465517 +24 chanx_left_in[16]:28 chanx_left_in[16]:27 0.0045 +25 chanx_left_in[16]:28 chanx_left_in[16]:25 0.000271875 +26 chanx_left_in[16]:26 mux_top_track_8\/mux_l2_in_3_:A1 0.152 +27 chanx_left_in[16]:31 chanx_left_in[16]:30 0.0045 +28 chanx_left_in[16]:30 chanx_left_in[16]:29 0.002691964 +29 chanx_left_in[16]:32 chanx_left_in[16]:31 0.0015625 +30 chanx_left_in[16]:33 chanx_left_in[16]:32 0.0045 +31 chanx_left_in[16]:19 chanx_left_in[16]:18 0.01145982 +32 chanx_left_in[16]:19 chanx_left_in[16]:5 0.0001766304 +33 chanx_left_in[16]:25 chanx_left_in[16]:24 0.006553572 +34 chanx_left_in[16]:29 chanx_left_in[16]:28 0.0003705357 +35 chanx_left_in[16]:41 chanx_left_in[16]:40 0.0001065333 +36 chanx_left_in[16]:40 chanx_left_in[16]:39 0.005477066 +37 chanx_left_in[16]:39 chanx_left_in[16]:38 0.0001065333 +38 chanx_left_in[16]:38 chanx_left_in[16]:37 0.001873733 +39 chanx_left_in[16]:37 chanx_left_in[16]:36 0.0001065333 +40 chanx_left_in[16]:36 chanx_left_in[16]:35 0.003602158 + +*END + +*D_NET top_left_grid_pin_41_[0] 0.006553134 //LENGTH 49.240 LUMPCC 0.0002743089 DR + +*CONN +*P top_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 117.640 +*I mux_top_track_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 39.465 107.100 +*I mux_top_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.435 108.120 +*I mux_top_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 45.255 107.780 +*N top_left_grid_pin_41_[0]:4 *C 45.218 107.780 +*N top_left_grid_pin_41_[0]:5 *C 60.473 108.120 +*N top_left_grid_pin_41_[0]:6 *C 61.135 108.120 +*N top_left_grid_pin_41_[0]:7 *C 61.180 108.120 +*N top_left_grid_pin_41_[0]:8 *C 61.172 108.120 +*N top_left_grid_pin_41_[0]:9 *C 44.168 108.120 +*N top_left_grid_pin_41_[0]:10 *C 44.160 108.120 +*N top_left_grid_pin_41_[0]:11 *C 44.160 107.780 +*N top_left_grid_pin_41_[0]:12 *C 44.160 107.780 +*N top_left_grid_pin_41_[0]:13 *C 44.160 107.440 +*N top_left_grid_pin_41_[0]:14 *C 39.550 107.100 +*N top_left_grid_pin_41_[0]:15 *C 41.860 107.100 +*N top_left_grid_pin_41_[0]:16 *C 41.860 107.440 +*N top_left_grid_pin_41_[0]:17 *C 41.860 108.120 +*N top_left_grid_pin_41_[0]:18 *C 31.785 108.120 +*N top_left_grid_pin_41_[0]:19 *C 31.740 108.165 +*N top_left_grid_pin_41_[0]:20 *C 31.740 117.583 +*N top_left_grid_pin_41_[0]:21 *C 31.733 117.640 + +*CAP +0 top_left_grid_pin_41_[0] 0.0001275998 +1 mux_top_track_4\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_0_:A0 1e-06 +3 mux_top_track_2\/mux_l1_in_1_:A0 1e-06 +4 top_left_grid_pin_41_[0]:4 9.881092e-05 +5 top_left_grid_pin_41_[0]:5 7.117236e-05 +6 top_left_grid_pin_41_[0]:6 7.117236e-05 +7 top_left_grid_pin_41_[0]:7 3.474909e-05 +8 top_left_grid_pin_41_[0]:8 0.001169498 +9 top_left_grid_pin_41_[0]:9 0.001169498 +10 top_left_grid_pin_41_[0]:10 6.20565e-05 +11 top_left_grid_pin_41_[0]:11 5.791234e-05 +12 top_left_grid_pin_41_[0]:12 0.0001272839 +13 top_left_grid_pin_41_[0]:13 0.000184546 +14 top_left_grid_pin_41_[0]:14 0.0001651792 +15 top_left_grid_pin_41_[0]:15 0.0001852297 +16 top_left_grid_pin_41_[0]:16 0.0002156045 +17 top_left_grid_pin_41_[0]:17 0.0006894534 +18 top_left_grid_pin_41_[0]:18 0.0006499725 +19 top_left_grid_pin_41_[0]:19 0.000534244 +20 top_left_grid_pin_41_[0]:20 0.000534244 +21 top_left_grid_pin_41_[0]:21 0.0001275998 +22 top_left_grid_pin_41_[0]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001371544 +23 top_left_grid_pin_41_[0]:17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001371544 + +*RES +0 top_left_grid_pin_41_[0] top_left_grid_pin_41_[0]:21 0.0003105917 +1 top_left_grid_pin_41_[0]:20 top_left_grid_pin_41_[0]:19 0.008408483 +2 top_left_grid_pin_41_[0]:21 top_left_grid_pin_41_[0]:20 0.00341 +3 top_left_grid_pin_41_[0]:18 top_left_grid_pin_41_[0]:17 0.008995536 +4 top_left_grid_pin_41_[0]:19 top_left_grid_pin_41_[0]:18 0.0045 +5 top_left_grid_pin_41_[0]:4 mux_top_track_2\/mux_l1_in_1_:A0 0.152 +6 top_left_grid_pin_41_[0]:12 top_left_grid_pin_41_[0]:11 0.0045 +7 top_left_grid_pin_41_[0]:12 top_left_grid_pin_41_[0]:4 0.0009441965 +8 top_left_grid_pin_41_[0]:11 top_left_grid_pin_41_[0]:10 0.0001634615 +9 top_left_grid_pin_41_[0]:10 top_left_grid_pin_41_[0]:9 0.00341 +10 top_left_grid_pin_41_[0]:9 top_left_grid_pin_41_[0]:8 0.002664116 +11 top_left_grid_pin_41_[0]:7 top_left_grid_pin_41_[0]:6 0.0045 +12 top_left_grid_pin_41_[0]:8 top_left_grid_pin_41_[0]:7 0.00341 +13 top_left_grid_pin_41_[0]:6 top_left_grid_pin_41_[0]:5 0.0005915179 +14 top_left_grid_pin_41_[0]:5 mux_top_track_32\/mux_l1_in_0_:A0 0.152 +15 top_left_grid_pin_41_[0]:14 mux_top_track_4\/mux_l2_in_3_:A1 0.152 +16 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:16 0.0006071428 +17 top_left_grid_pin_41_[0]:15 top_left_grid_pin_41_[0]:14 0.0020625 +18 top_left_grid_pin_41_[0]:16 top_left_grid_pin_41_[0]:15 0.0003035715 +19 top_left_grid_pin_41_[0]:16 top_left_grid_pin_41_[0]:13 0.002053572 +20 top_left_grid_pin_41_[0]:13 top_left_grid_pin_41_[0]:12 0.0003035714 + +*END + +*D_NET right_top_grid_pin_44_[0] 0.01096514 //LENGTH 92.230 LUMPCC 0.0005751973 DR + +*CONN +*P right_top_grid_pin_44_[0] I *L 0.29796 *C 139.380 102.035 +*I mux_right_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 102.485 105.060 +*I mux_right_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 86.310 87.720 +*I mux_right_track_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 122.265 85.340 +*N right_top_grid_pin_44_[0]:4 *C 122.303 85.340 +*N right_top_grid_pin_44_[0]:5 *C 122.775 85.340 +*N right_top_grid_pin_44_[0]:6 *C 122.820 85.385 +*N right_top_grid_pin_44_[0]:7 *C 122.820 101.615 +*N right_top_grid_pin_44_[0]:8 *C 122.820 101.660 +*N right_top_grid_pin_44_[0]:9 *C 86.348 87.720 +*N right_top_grid_pin_44_[0]:10 *C 90.115 87.720 +*N right_top_grid_pin_44_[0]:11 *C 90.160 87.765 +*N right_top_grid_pin_44_[0]:12 *C 90.160 102.635 +*N right_top_grid_pin_44_[0]:13 *C 90.205 102.680 +*N right_top_grid_pin_44_[0]:14 *C 102.485 105.060 +*N right_top_grid_pin_44_[0]:15 *C 102.580 105.015 +*N right_top_grid_pin_44_[0]:16 *C 102.580 102.725 +*N right_top_grid_pin_44_[0]:17 *C 102.580 102.680 +*N right_top_grid_pin_44_[0]:18 *C 122.820 102.680 +*N right_top_grid_pin_44_[0]:19 *C 132.020 102.680 +*N right_top_grid_pin_44_[0]:20 *C 132.020 101.660 +*N right_top_grid_pin_44_[0]:21 *C 139.335 101.660 +*N right_top_grid_pin_44_[0]:22 *C 139.380 101.705 + +*CAP +0 right_top_grid_pin_44_[0] 2.764951e-05 +1 mux_right_track_0\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_24\/mux_l1_in_1_:A0 1e-06 +3 mux_right_track_4\/mux_l2_in_2_:A1 1e-06 +4 right_top_grid_pin_44_[0]:4 5.710178e-05 +5 right_top_grid_pin_44_[0]:5 5.710178e-05 +6 right_top_grid_pin_44_[0]:6 0.0008822758 +7 right_top_grid_pin_44_[0]:7 0.0008822758 +8 right_top_grid_pin_44_[0]:8 8.887374e-05 +9 right_top_grid_pin_44_[0]:9 0.0002761439 +10 right_top_grid_pin_44_[0]:10 0.0002761439 +11 right_top_grid_pin_44_[0]:11 0.000908905 +12 right_top_grid_pin_44_[0]:12 0.000908905 +13 right_top_grid_pin_44_[0]:13 0.0007917282 +14 right_top_grid_pin_44_[0]:14 2.824429e-05 +15 right_top_grid_pin_44_[0]:15 0.0001536492 +16 right_top_grid_pin_44_[0]:16 0.0001536492 +17 right_top_grid_pin_44_[0]:17 0.001879993 +18 right_top_grid_pin_44_[0]:18 0.001605609 +19 right_top_grid_pin_44_[0]:19 0.0005400279 +20 right_top_grid_pin_44_[0]:20 0.0004455144 +21 right_top_grid_pin_44_[0]:21 0.0003955068 +22 right_top_grid_pin_44_[0]:22 2.764951e-05 +23 right_top_grid_pin_44_[0]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 2.821185e-06 +24 right_top_grid_pin_44_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 4.874053e-05 +25 right_top_grid_pin_44_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 2.821185e-06 +26 right_top_grid_pin_44_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 8.199686e-05 +27 right_top_grid_pin_44_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 8.199686e-05 +28 right_top_grid_pin_44_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 4.874053e-05 +29 right_top_grid_pin_44_[0]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0001010777 +30 right_top_grid_pin_44_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 5.296238e-05 +31 right_top_grid_pin_44_[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0001010777 +32 right_top_grid_pin_44_[0]:19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 5.296238e-05 + +*RES +0 right_top_grid_pin_44_[0] right_top_grid_pin_44_[0]:22 0.0002946429 +1 right_top_grid_pin_44_[0]:13 right_top_grid_pin_44_[0]:12 0.0045 +2 right_top_grid_pin_44_[0]:12 right_top_grid_pin_44_[0]:11 0.01327679 +3 right_top_grid_pin_44_[0]:10 right_top_grid_pin_44_[0]:9 0.00336384 +4 right_top_grid_pin_44_[0]:11 right_top_grid_pin_44_[0]:10 0.0045 +5 right_top_grid_pin_44_[0]:9 mux_right_track_24\/mux_l1_in_1_:A0 0.152 +6 right_top_grid_pin_44_[0]:21 right_top_grid_pin_44_[0]:20 0.00653125 +7 right_top_grid_pin_44_[0]:22 right_top_grid_pin_44_[0]:21 0.0045 +8 right_top_grid_pin_44_[0]:4 mux_right_track_4\/mux_l2_in_2_:A1 0.152 +9 right_top_grid_pin_44_[0]:5 right_top_grid_pin_44_[0]:4 0.000421875 +10 right_top_grid_pin_44_[0]:6 right_top_grid_pin_44_[0]:5 0.0045 +11 right_top_grid_pin_44_[0]:8 right_top_grid_pin_44_[0]:7 0.0045 +12 right_top_grid_pin_44_[0]:7 right_top_grid_pin_44_[0]:6 0.01449107 +13 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:16 0.0045 +14 right_top_grid_pin_44_[0]:17 right_top_grid_pin_44_[0]:13 0.01104911 +15 right_top_grid_pin_44_[0]:16 right_top_grid_pin_44_[0]:15 0.002044643 +16 right_top_grid_pin_44_[0]:14 mux_right_track_0\/mux_l1_in_2_:A1 0.152 +17 right_top_grid_pin_44_[0]:15 right_top_grid_pin_44_[0]:14 0.0045 +18 right_top_grid_pin_44_[0]:18 right_top_grid_pin_44_[0]:17 0.01807143 +19 right_top_grid_pin_44_[0]:18 right_top_grid_pin_44_[0]:8 0.0009107144 +20 right_top_grid_pin_44_[0]:19 right_top_grid_pin_44_[0]:18 0.008214286 +21 right_top_grid_pin_44_[0]:20 right_top_grid_pin_44_[0]:19 0.0009107143 + +*END + +*D_NET chany_bottom_in[7] 0.01576442 //LENGTH 108.050 LUMPCC 0.003319622 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 87.400 1.290 +*I mux_right_track_4\/mux_l2_in_5_:A0 I *L 0.001631 *C 78.835 75.140 +*I mux_left_track_17\/mux_l1_in_2_:A0 I *L 0.001631 *C 61.900 49.980 +*N chany_bottom_in[7]:3 *C 86.690 4.080 +*N chany_bottom_in[7]:4 *C 61.900 49.980 +*N chany_bottom_in[7]:5 *C 62.100 49.980 +*N chany_bottom_in[7]:6 *C 62.100 50.025 +*N chany_bottom_in[7]:7 *C 62.100 54.343 +*N chany_bottom_in[7]:8 *C 62.108 54.400 +*N chany_bottom_in[7]:9 *C 78.660 54.400 +*N chany_bottom_in[7]:10 *C 78.835 75.140 +*N chany_bottom_in[7]:11 *C 78.660 75.140 +*N chany_bottom_in[7]:12 *C 78.660 75.095 +*N chany_bottom_in[7]:13 *C 78.660 55.138 +*N chany_bottom_in[7]:14 *C 78.660 55.080 +*N chany_bottom_in[7]:15 *C 87.380 55.080 +*N chany_bottom_in[7]:16 *C 87.400 55.073 +*N chany_bottom_in[7]:17 *C 87.400 4.088 +*N chany_bottom_in[7]:18 *C 87.398 4.080 +*N chany_bottom_in[7]:19 *C 87.400 4.022 + +*CAP +0 chany_bottom_in[7] 0.0001496198 +1 mux_right_track_4\/mux_l2_in_5_:A0 1e-06 +2 mux_left_track_17\/mux_l1_in_2_:A0 1e-06 +3 chany_bottom_in[7]:3 6.626266e-05 +4 chany_bottom_in[7]:4 6.108792e-05 +5 chany_bottom_in[7]:5 6.583388e-05 +6 chany_bottom_in[7]:6 0.0002602009 +7 chany_bottom_in[7]:7 0.0002602009 +8 chany_bottom_in[7]:8 0.001139066 +9 chany_bottom_in[7]:9 0.001219091 +10 chany_bottom_in[7]:10 5.746701e-05 +11 chany_bottom_in[7]:11 6.095842e-05 +12 chany_bottom_in[7]:12 0.001056097 +13 chany_bottom_in[7]:13 0.001056097 +14 chany_bottom_in[7]:14 0.0007513224 +15 chany_bottom_in[7]:15 0.0006712973 +16 chany_bottom_in[7]:16 0.002676156 +17 chany_bottom_in[7]:17 0.002676156 +18 chany_bottom_in[7]:18 6.626266e-05 +19 chany_bottom_in[7]:19 0.0001496198 +20 chany_bottom_in[7]:8 chanx_right_in[8]:10 0.0002850622 +21 chany_bottom_in[7]:9 chanx_right_in[8]:11 0.0002850622 +22 chany_bottom_in[7]:8 chanx_right_in[0]:7 0.0002024669 +23 chany_bottom_in[7]:15 chanx_right_in[0]:11 9.159333e-05 +24 chany_bottom_in[7]:15 chanx_right_in[0]:12 4.143743e-05 +25 chany_bottom_in[7]:14 chanx_right_in[0]:7 9.159333e-05 +26 chany_bottom_in[7]:14 chanx_right_in[0]:11 4.143743e-05 +27 chany_bottom_in[7]:9 chanx_right_in[0]:11 0.0002024669 +28 chany_bottom_in[7]:16 chanx_right_in[3]:9 0.0002973683 +29 chany_bottom_in[7]:17 chanx_right_in[3]:10 0.0002973683 +30 chany_bottom_in[7] chany_bottom_in[11] 1.954849e-05 +31 chany_bottom_in[7]:15 chany_bottom_in[11]:13 2.325856e-06 +32 chany_bottom_in[7]:16 chany_bottom_in[11]:15 0.0004296561 +33 chany_bottom_in[7]:18 chany_bottom_in[11]:18 2.224475e-05 +34 chany_bottom_in[7]:17 chany_bottom_in[11]:16 0.0004296561 +35 chany_bottom_in[7]:19 chany_bottom_in[11]:19 1.954849e-05 +36 chany_bottom_in[7]:14 chany_bottom_in[11]:12 2.325856e-06 +37 chany_bottom_in[7]:3 chany_bottom_in[11]:17 2.224475e-05 +38 chany_bottom_in[7]:13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002681078 +39 chany_bottom_in[7]:12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002681078 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:19 0.002439732 +1 chany_bottom_in[7]:4 mux_left_track_17\/mux_l1_in_2_:A0 0.152 +2 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.0001086957 +3 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.0045 +4 chany_bottom_in[7]:7 chany_bottom_in[7]:6 0.003854911 +5 chany_bottom_in[7]:8 chany_bottom_in[7]:7 0.00341 +6 chany_bottom_in[7]:15 chany_bottom_in[7]:14 0.001366133 +7 chany_bottom_in[7]:16 chany_bottom_in[7]:15 0.00341 +8 chany_bottom_in[7]:18 chany_bottom_in[7]:17 0.00341 +9 chany_bottom_in[7]:18 chany_bottom_in[7]:3 0.0001039141 +10 chany_bottom_in[7]:17 chany_bottom_in[7]:16 0.007987649 +11 chany_bottom_in[7]:19 chany_bottom_in[7]:18 0.00341 +12 chany_bottom_in[7]:13 chany_bottom_in[7]:12 0.0178192 +13 chany_bottom_in[7]:14 chany_bottom_in[7]:13 0.00341 +14 chany_bottom_in[7]:14 chany_bottom_in[7]:9 0.0001065333 +15 chany_bottom_in[7]:11 chany_bottom_in[7]:10 9.510871e-05 +16 chany_bottom_in[7]:12 chany_bottom_in[7]:11 0.0045 +17 chany_bottom_in[7]:10 mux_right_track_4\/mux_l2_in_5_:A0 0.152 +18 chany_bottom_in[7]:9 chany_bottom_in[7]:8 0.002593225 + +*END + +*D_NET bottom_left_grid_pin_39_[0] 0.005860902 //LENGTH 48.115 LUMPCC 0.0003222513 DR + +*CONN +*P bottom_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 11.560 +*I mux_bottom_track_5\/mux_l2_in_4_:A0 I *L 0.001631 *C 34.215 6.120 +*I mux_bottom_track_3\/mux_l1_in_3_:A0 I *L 0.001631 *C 48.015 26.520 +*I mux_bottom_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 48.935 28.220 +*N bottom_left_grid_pin_39_[0]:4 *C 48.898 28.220 +*N bottom_left_grid_pin_39_[0]:5 *C 46.965 28.220 +*N bottom_left_grid_pin_39_[0]:6 *C 46.920 28.175 +*N bottom_left_grid_pin_39_[0]:7 *C 47.977 26.520 +*N bottom_left_grid_pin_39_[0]:8 *C 46.965 26.520 +*N bottom_left_grid_pin_39_[0]:9 *C 46.920 26.520 +*N bottom_left_grid_pin_39_[0]:10 *C 46.920 11.617 +*N bottom_left_grid_pin_39_[0]:11 *C 46.913 11.560 +*N bottom_left_grid_pin_39_[0]:12 *C 34.253 6.120 +*N bottom_left_grid_pin_39_[0]:13 *C 38.135 6.120 +*N bottom_left_grid_pin_39_[0]:14 *C 38.180 6.165 +*N bottom_left_grid_pin_39_[0]:15 *C 38.180 11.503 +*N bottom_left_grid_pin_39_[0]:16 *C 38.180 11.560 + +*CAP +0 bottom_left_grid_pin_39_[0] 0.0005922271 +1 mux_bottom_track_5\/mux_l2_in_4_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_3_:A0 1e-06 +3 mux_bottom_track_17\/mux_l2_in_1_:A0 1e-06 +4 bottom_left_grid_pin_39_[0]:4 0.0001301174 +5 bottom_left_grid_pin_39_[0]:5 0.0001301174 +6 bottom_left_grid_pin_39_[0]:6 0.000107362 +7 bottom_left_grid_pin_39_[0]:7 9.252627e-05 +8 bottom_left_grid_pin_39_[0]:8 9.252627e-05 +9 bottom_left_grid_pin_39_[0]:9 0.0009060763 +10 bottom_left_grid_pin_39_[0]:10 0.0007688461 +11 bottom_left_grid_pin_39_[0]:11 0.0004610279 +12 bottom_left_grid_pin_39_[0]:12 0.00027594 +13 bottom_left_grid_pin_39_[0]:13 0.00027594 +14 bottom_left_grid_pin_39_[0]:14 0.0003248444 +15 bottom_left_grid_pin_39_[0]:15 0.0003248444 +16 bottom_left_grid_pin_39_[0]:16 0.001053255 +17 bottom_left_grid_pin_39_[0]:15 mux_tree_tapbuf_size16_2_sram[0]:8 9.685024e-07 +18 bottom_left_grid_pin_39_[0]:16 mux_tree_tapbuf_size16_2_sram[0]:10 0.0001601572 +19 bottom_left_grid_pin_39_[0]:14 mux_tree_tapbuf_size16_2_sram[0]:9 9.685024e-07 +20 bottom_left_grid_pin_39_[0]:11 mux_tree_tapbuf_size16_2_sram[0]:11 0.0001601572 + +*RES +0 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_39_[0]:16 0.0013207 +1 bottom_left_grid_pin_39_[0]:15 bottom_left_grid_pin_39_[0]:14 0.004765625 +2 bottom_left_grid_pin_39_[0]:16 bottom_left_grid_pin_39_[0]:15 0.00341 +3 bottom_left_grid_pin_39_[0]:16 bottom_left_grid_pin_39_[0]:11 0.001368092 +4 bottom_left_grid_pin_39_[0]:13 bottom_left_grid_pin_39_[0]:12 0.003466518 +5 bottom_left_grid_pin_39_[0]:14 bottom_left_grid_pin_39_[0]:13 0.0045 +6 bottom_left_grid_pin_39_[0]:12 mux_bottom_track_5\/mux_l2_in_4_:A0 0.152 +7 bottom_left_grid_pin_39_[0]:10 bottom_left_grid_pin_39_[0]:9 0.0133058 +8 bottom_left_grid_pin_39_[0]:11 bottom_left_grid_pin_39_[0]:10 0.00341 +9 bottom_left_grid_pin_39_[0]:5 bottom_left_grid_pin_39_[0]:4 0.001725447 +10 bottom_left_grid_pin_39_[0]:6 bottom_left_grid_pin_39_[0]:5 0.0045 +11 bottom_left_grid_pin_39_[0]:4 mux_bottom_track_17\/mux_l2_in_1_:A0 0.152 +12 bottom_left_grid_pin_39_[0]:8 bottom_left_grid_pin_39_[0]:7 0.000904018 +13 bottom_left_grid_pin_39_[0]:9 bottom_left_grid_pin_39_[0]:8 0.0045 +14 bottom_left_grid_pin_39_[0]:9 bottom_left_grid_pin_39_[0]:6 0.001477679 +15 bottom_left_grid_pin_39_[0]:7 mux_bottom_track_3\/mux_l1_in_3_:A0 0.152 + +*END + +*D_NET chanx_left_in[19] 0.0161872 //LENGTH 104.595 LUMPCC 0.007281223 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 46.240 +*I mux_top_track_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 51.060 96.220 +*I mux_bottom_track_25\/mux_l2_in_3_:A1 I *L 0.00198 *C 29.440 50.660 +*N chanx_left_in[19]:3 *C 29.402 50.660 +*N chanx_left_in[19]:4 *C 51.023 96.220 +*N chanx_left_in[19]:5 *C 50.645 96.220 +*N chanx_left_in[19]:6 *C 50.600 96.175 +*N chanx_left_in[19]:7 *C 50.600 92.538 +*N chanx_left_in[19]:8 *C 50.593 92.480 +*N chanx_left_in[19]:9 *C 35.900 92.480 +*N chanx_left_in[19]:10 *C 35.880 92.473 +*N chanx_left_in[19]:11 *C 35.880 51.008 +*N chanx_left_in[19]:12 *C 35.860 51.000 +*N chanx_left_in[19]:13 *C 27.148 51.000 +*N chanx_left_in[19]:14 *C 27.140 51.000 +*N chanx_left_in[19]:15 *C 27.140 50.660 +*N chanx_left_in[19]:16 *C 27.140 50.660 +*N chanx_left_in[19]:17 *C 18.905 50.660 +*N chanx_left_in[19]:18 *C 18.860 50.615 +*N chanx_left_in[19]:19 *C 18.860 46.297 +*N chanx_left_in[19]:20 *C 18.852 46.240 + +*CAP +0 chanx_left_in[19] 0.000681841 +1 mux_top_track_2\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_track_25\/mux_l2_in_3_:A1 1e-06 +3 chanx_left_in[19]:3 0.0001926424 +4 chanx_left_in[19]:4 5.542372e-05 +5 chanx_left_in[19]:5 5.542372e-05 +6 chanx_left_in[19]:6 0.0001606032 +7 chanx_left_in[19]:7 0.0001606032 +8 chanx_left_in[19]:8 0.0006020822 +9 chanx_left_in[19]:9 0.0006020822 +10 chanx_left_in[19]:10 0.001914861 +11 chanx_left_in[19]:11 0.001914861 +12 chanx_left_in[19]:12 0.0001956635 +13 chanx_left_in[19]:13 0.0001956635 +14 chanx_left_in[19]:14 5.496194e-05 +15 chanx_left_in[19]:15 5.079848e-05 +16 chanx_left_in[19]:16 0.0006205797 +17 chanx_left_in[19]:17 0.0003897486 +18 chanx_left_in[19]:18 0.0001871488 +19 chanx_left_in[19]:19 0.0001871488 +20 chanx_left_in[19]:20 0.000681841 +21 chanx_left_in[19] chanx_right_in[4]:17 0.0003078765 +22 chanx_left_in[19]:20 chanx_right_in[4]:18 0.0003078765 +23 chanx_left_in[19]:13 chanx_right_in[5]:12 0.0004945333 +24 chanx_left_in[19]:12 chanx_right_in[5]:13 0.0004945333 +25 chanx_left_in[19]:11 chanx_right_in[5]:20 3.123232e-05 +26 chanx_left_in[19]:10 chanx_right_in[5]:21 3.123232e-05 +27 chanx_left_in[19]:9 chanx_right_in[14]:25 0.0005580803 +28 chanx_left_in[19]:8 chanx_right_in[14]:26 0.0005580803 +29 chanx_left_in[19]:11 chanx_left_in[14]:10 0.0003080034 +30 chanx_left_in[19]:11 chanx_left_in[14]:28 0.0001156335 +31 chanx_left_in[19]:10 chanx_left_in[14]:28 0.0003080034 +32 chanx_left_in[19]:10 chanx_left_in[14]:29 0.0001156335 +33 chanx_left_in[19]:13 chanx_left_in[16] 0.0004945333 +34 chanx_left_in[19]:12 chanx_left_in[16]:41 0.0004945333 +35 chanx_left_in[19] chanx_left_in[17]:31 0.0003935799 +36 chanx_left_in[19]:20 chanx_left_in[17]:30 0.0003935799 +37 chanx_left_in[19]:11 chanx_right_in[7]:15 0.0002087616 +38 chanx_left_in[19]:11 chanx_right_in[7]:16 0.0001202451 +39 chanx_left_in[19]:10 chanx_right_in[7]:9 0.0001202451 +40 chanx_left_in[19]:10 chanx_right_in[7]:16 0.0002087616 +41 chanx_left_in[19]:9 chanx_left_in[0]:8 0.0003053735 +42 chanx_left_in[19]:8 chanx_left_in[0]:7 0.0003053735 +43 chanx_left_in[19]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001027076 +44 chanx_left_in[19]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001027076 +45 chanx_left_in[19]:17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001225689 +46 chanx_left_in[19]:18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 2.272178e-05 +47 chanx_left_in[19]:19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 2.272178e-05 +48 chanx_left_in[19]:16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001225689 +49 chanx_left_in[19]:15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:10 2.058474e-06 +50 chanx_left_in[19]:14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:9 2.058474e-06 +51 chanx_left_in[19]:18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.270218e-05 +52 chanx_left_in[19]:19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.270218e-05 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:20 0.002760858 +1 chanx_left_in[19]:3 mux_bottom_track_25\/mux_l2_in_3_:A1 0.152 +2 chanx_left_in[19]:17 chanx_left_in[19]:16 0.007352679 +3 chanx_left_in[19]:18 chanx_left_in[19]:17 0.0045 +4 chanx_left_in[19]:19 chanx_left_in[19]:18 0.003854911 +5 chanx_left_in[19]:20 chanx_left_in[19]:19 0.00341 +6 chanx_left_in[19]:16 chanx_left_in[19]:15 0.0045 +7 chanx_left_in[19]:16 chanx_left_in[19]:3 0.002020089 +8 chanx_left_in[19]:15 chanx_left_in[19]:14 0.0001634615 +9 chanx_left_in[19]:14 chanx_left_in[19]:13 0.00341 +10 chanx_left_in[19]:13 chanx_left_in[19]:12 0.001364958 +11 chanx_left_in[19]:12 chanx_left_in[19]:11 0.00341 +12 chanx_left_in[19]:11 chanx_left_in[19]:10 0.006496183 +13 chanx_left_in[19]:9 chanx_left_in[19]:8 0.002301825 +14 chanx_left_in[19]:10 chanx_left_in[19]:9 0.00341 +15 chanx_left_in[19]:7 chanx_left_in[19]:6 0.003247768 +16 chanx_left_in[19]:8 chanx_left_in[19]:7 0.00341 +17 chanx_left_in[19]:5 chanx_left_in[19]:4 0.0003370536 +18 chanx_left_in[19]:6 chanx_left_in[19]:5 0.0045 +19 chanx_left_in[19]:4 mux_top_track_2\/mux_l2_in_3_:A1 0.152 + +*END + +*D_NET ropt_net_153 0.003132027 //LENGTH 27.750 LUMPCC 0.0001999306 DR + +*CONN +*I mux_right_track_8\/mux_l4_in_0_:X O *L 0 *C 119.000 64.600 +*I ropt_mt_inst_791:A I *L 0.001766 *C 130.180 80.240 +*N ropt_net_153:2 *C 130.143 80.240 +*N ropt_net_153:3 *C 129.765 80.240 +*N ropt_net_153:4 *C 129.720 80.195 +*N ropt_net_153:5 *C 129.720 64.645 +*N ropt_net_153:6 *C 129.675 64.600 +*N ropt_net_153:7 *C 119.038 64.600 + +*CAP +0 mux_right_track_8\/mux_l4_in_0_:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_153:2 4.42538e-05 +3 ropt_net_153:3 4.42538e-05 +4 ropt_net_153:4 0.0007486607 +5 ropt_net_153:5 0.0007486607 +6 ropt_net_153:6 0.0006721339 +7 ropt_net_153:7 0.0006721339 +8 ropt_net_153:4 mux_tree_tapbuf_size16_1_sram[4]:4 2.84514e-05 +9 ropt_net_153:4 mux_tree_tapbuf_size16_1_sram[4]:7 7.151389e-05 +10 ropt_net_153:5 mux_tree_tapbuf_size16_1_sram[4]:6 7.151389e-05 +11 ropt_net_153:5 mux_tree_tapbuf_size16_1_sram[4]:7 2.84514e-05 + +*RES +0 mux_right_track_8\/mux_l4_in_0_:X ropt_net_153:7 0.152 +1 ropt_net_153:2 ropt_mt_inst_791:A 0.152 +2 ropt_net_153:3 ropt_net_153:2 0.0003370536 +3 ropt_net_153:4 ropt_net_153:3 0.0045 +4 ropt_net_153:6 ropt_net_153:5 0.0045 +5 ropt_net_153:5 ropt_net_153:4 0.01388393 +6 ropt_net_153:7 ropt_net_153:6 0.009497768 + +*END + +*D_NET chany_bottom_out[16] 0.003773368 //LENGTH 30.730 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 37.320 4.080 +*P chany_bottom_out[16] O *L 0.7423 *C 64.400 1.290 +*N chany_bottom_out[16]:2 *C 64.400 1.995 +*N chany_bottom_out[16]:3 *C 64.355 2.040 +*N chany_bottom_out[16]:4 *C 37.305 2.040 +*N chany_bottom_out[16]:5 *C 37.260 2.085 +*N chany_bottom_out[16]:6 *C 37.260 4.035 +*N chany_bottom_out[16]:7 *C 37.260 4.080 + +*CAP +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[16] 6.399641e-05 +2 chany_bottom_out[16]:2 6.399641e-05 +3 chany_bottom_out[16]:3 0.001702185 +4 chany_bottom_out[16]:4 0.001702185 +5 chany_bottom_out[16]:5 0.0001062984 +6 chany_bottom_out[16]:6 0.0001062984 +7 chany_bottom_out[16]:7 2.740765e-05 + +*RES +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[16]:7 0.152 +1 chany_bottom_out[16]:7 chany_bottom_out[16]:6 0.0045 +2 chany_bottom_out[16]:6 chany_bottom_out[16]:5 0.001741072 +3 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.02415179 +4 chany_bottom_out[16]:5 chany_bottom_out[16]:4 0.0045 +5 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0045 +6 chany_bottom_out[16]:2 chany_bottom_out[16] 0.0006294643 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.006431144 //LENGTH 47.405 LUMPCC 0.0007106807 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 62.860 47.940 +*I mux_top_track_16\/mux_l2_in_3_:S I *L 0.00357 *C 47.940 47.600 +*I mux_top_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 52.540 53.040 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 39.735 53.380 +*I mux_top_track_16\/mux_l2_in_2_:S I *L 0.00357 *C 37.620 50.320 +*I mux_top_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 54.380 50.320 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 54.380 50.320 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 37.583 50.320 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 36.800 50.320 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 36.800 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 39.055 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 39.100 50.025 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 39.100 53.335 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 39.145 53.380 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 39.735 53.380 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 48.300 53.380 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 48.300 53.040 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 51.980 53.040 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 52.540 53.040 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 52.440 52.700 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 51.980 52.700 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 51.980 52.655 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 47.977 47.600 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 51.935 47.600 +*N mux_tree_tapbuf_size10_1_sram[1]:24 *C 51.980 47.645 +*N mux_tree_tapbuf_size10_1_sram[1]:25 *C 51.980 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:26 *C 52.025 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:27 *C 54.280 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:28 *C 60.215 49.980 +*N mux_tree_tapbuf_size10_1_sram[1]:29 *C 60.260 49.935 +*N mux_tree_tapbuf_size10_1_sram[1]:30 *C 60.260 47.985 +*N mux_tree_tapbuf_size10_1_sram[1]:31 *C 60.305 47.940 +*N mux_tree_tapbuf_size10_1_sram[1]:32 *C 62.823 47.940 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_16\/mux_l2_in_3_:S 1e-06 +2 mux_top_track_16\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_top_track_16\/mux_l2_in_2_:S 1e-06 +5 mux_top_track_16\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 5.620021e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:7 8.716851e-05 +8 mux_tree_tapbuf_size10_1_sram[1]:8 0.0001141766 +9 mux_tree_tapbuf_size10_1_sram[1]:9 0.000198451 +10 mux_tree_tapbuf_size10_1_sram[1]:10 0.0001714429 +11 mux_tree_tapbuf_size10_1_sram[1]:11 0.0002443322 +12 mux_tree_tapbuf_size10_1_sram[1]:12 0.0002443322 +13 mux_tree_tapbuf_size10_1_sram[1]:13 5.18419e-05 +14 mux_tree_tapbuf_size10_1_sram[1]:14 0.0006325956 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0005742123 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0002200768 +17 mux_tree_tapbuf_size10_1_sram[1]:17 0.0002108428 +18 mux_tree_tapbuf_size10_1_sram[1]:18 5.941371e-05 +19 mux_tree_tapbuf_size10_1_sram[1]:19 7.577558e-05 +20 mux_tree_tapbuf_size10_1_sram[1]:20 6.183358e-05 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.00014686 +22 mux_tree_tapbuf_size10_1_sram[1]:22 0.0002566277 +23 mux_tree_tapbuf_size10_1_sram[1]:23 0.0002566277 +24 mux_tree_tapbuf_size10_1_sram[1]:24 0.0001366656 +25 mux_tree_tapbuf_size10_1_sram[1]:25 0.0003164487 +26 mux_tree_tapbuf_size10_1_sram[1]:26 0.0001174112 +27 mux_tree_tapbuf_size10_1_sram[1]:27 0.0004559364 +28 mux_tree_tapbuf_size10_1_sram[1]:28 0.0003107982 +29 mux_tree_tapbuf_size10_1_sram[1]:29 0.0001450188 +30 mux_tree_tapbuf_size10_1_sram[1]:30 0.0001450188 +31 mux_tree_tapbuf_size10_1_sram[1]:31 0.0002121768 +32 mux_tree_tapbuf_size10_1_sram[1]:32 0.0002121768 +33 mux_tree_tapbuf_size10_1_sram[1]:28 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001853012 +34 mux_tree_tapbuf_size10_1_sram[1]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001853012 +35 mux_tree_tapbuf_size10_1_sram[1]:21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.942813e-06 +36 mux_tree_tapbuf_size10_1_sram[1]:26 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.853783e-05 +37 mux_tree_tapbuf_size10_1_sram[1]:25 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.942813e-06 +38 mux_tree_tapbuf_size10_1_sram[1]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.853783e-05 +39 mux_tree_tapbuf_size10_1_sram[1]:20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.137728e-07 +40 mux_tree_tapbuf_size10_1_sram[1]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.544472e-05 +41 mux_tree_tapbuf_size10_1_sram[1]:17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.544472e-05 +42 mux_tree_tapbuf_size10_1_sram[1]:19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.137728e-07 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:32 mux_tree_tapbuf_size10_1_sram[1]:31 0.002247768 +2 mux_tree_tapbuf_size10_1_sram[1]:31 mux_tree_tapbuf_size10_1_sram[1]:30 0.0045 +3 mux_tree_tapbuf_size10_1_sram[1]:30 mux_tree_tapbuf_size10_1_sram[1]:29 0.001741071 +4 mux_tree_tapbuf_size10_1_sram[1]:28 mux_tree_tapbuf_size10_1_sram[1]:27 0.005299107 +5 mux_tree_tapbuf_size10_1_sram[1]:29 mux_tree_tapbuf_size10_1_sram[1]:28 0.0045 +6 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.0004107143 +7 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:17 0.0003035715 +8 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.0045 +9 mux_tree_tapbuf_size10_1_sram[1]:6 mux_top_track_16\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_1_sram[1]:14 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[1]:13 0.0005267857 +12 mux_tree_tapbuf_size10_1_sram[1]:23 mux_tree_tapbuf_size10_1_sram[1]:22 0.003533482 +13 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:23 0.0045 +14 mux_tree_tapbuf_size10_1_sram[1]:22 mux_top_track_16\/mux_l2_in_3_:S 0.152 +15 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:12 0.0045 +16 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 0.002955357 +17 mux_tree_tapbuf_size10_1_sram[1]:10 mux_tree_tapbuf_size10_1_sram[1]:9 0.002013393 +18 mux_tree_tapbuf_size10_1_sram[1]:11 mux_tree_tapbuf_size10_1_sram[1]:10 0.0045 +19 mux_tree_tapbuf_size10_1_sram[1]:7 mux_top_track_16\/mux_l2_in_2_:S 0.152 +20 mux_tree_tapbuf_size10_1_sram[1]:18 mux_top_track_16\/mux_l2_in_1_:S 0.152 +21 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:25 0.0045 +22 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:24 0.002084821 +23 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:21 0.002388393 +24 mux_tree_tapbuf_size10_1_sram[1]:9 mux_tree_tapbuf_size10_1_sram[1]:8 0.0003035714 +25 mux_tree_tapbuf_size10_1_sram[1]:8 mux_tree_tapbuf_size10_1_sram[1]:7 0.0006986608 +26 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.007647322 +27 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.0003035715 +28 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.003285714 +29 mux_tree_tapbuf_size10_1_sram[1]:27 mux_tree_tapbuf_size10_1_sram[1]:26 0.002013393 +30 mux_tree_tapbuf_size10_1_sram[1]:27 mux_tree_tapbuf_size10_1_sram[1]:6 0.0003035715 +31 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[2] 0.003669452 //LENGTH 29.820 LUMPCC 0.0001381357 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 101.505 85.680 +*I mux_right_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 99.720 82.960 +*I mux_right_track_24\/mux_l3_in_1_:S I *L 0.00357 *C 103.860 74.800 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 97.695 88.060 +*N mux_tree_tapbuf_size10_5_sram[2]:4 *C 97.657 88.060 +*N mux_tree_tapbuf_size10_5_sram[2]:5 *C 97.060 88.060 +*N mux_tree_tapbuf_size10_5_sram[2]:6 *C 97.060 87.720 +*N mux_tree_tapbuf_size10_5_sram[2]:7 *C 103.915 87.720 +*N mux_tree_tapbuf_size10_5_sram[2]:8 *C 103.960 87.675 +*N mux_tree_tapbuf_size10_5_sram[2]:9 *C 103.960 85.725 +*N mux_tree_tapbuf_size10_5_sram[2]:10 *C 103.915 85.680 +*N mux_tree_tapbuf_size10_5_sram[2]:11 *C 103.823 74.800 +*N mux_tree_tapbuf_size10_5_sram[2]:12 *C 101.245 74.800 +*N mux_tree_tapbuf_size10_5_sram[2]:13 *C 101.200 74.845 +*N mux_tree_tapbuf_size10_5_sram[2]:14 *C 99.758 82.960 +*N mux_tree_tapbuf_size10_5_sram[2]:15 *C 101.155 82.960 +*N mux_tree_tapbuf_size10_5_sram[2]:16 *C 101.200 82.960 +*N mux_tree_tapbuf_size10_5_sram[2]:17 *C 101.200 85.635 +*N mux_tree_tapbuf_size10_5_sram[2]:18 *C 101.200 85.680 +*N mux_tree_tapbuf_size10_5_sram[2]:19 *C 101.543 85.680 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:S 1e-06 +2 mux_right_track_24\/mux_l3_in_1_:S 1e-06 +3 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_5_sram[2]:4 5.70162e-05 +5 mux_tree_tapbuf_size10_5_sram[2]:5 8.383419e-05 +6 mux_tree_tapbuf_size10_5_sram[2]:6 0.0004537969 +7 mux_tree_tapbuf_size10_5_sram[2]:7 0.0004269789 +8 mux_tree_tapbuf_size10_5_sram[2]:8 0.0001452032 +9 mux_tree_tapbuf_size10_5_sram[2]:9 0.0001452032 +10 mux_tree_tapbuf_size10_5_sram[2]:10 0.0001616134 +11 mux_tree_tapbuf_size10_5_sram[2]:11 0.0001603567 +12 mux_tree_tapbuf_size10_5_sram[2]:12 0.0001603567 +13 mux_tree_tapbuf_size10_5_sram[2]:13 0.0004618332 +14 mux_tree_tapbuf_size10_5_sram[2]:14 0.0001174564 +15 mux_tree_tapbuf_size10_5_sram[2]:15 0.0001174564 +16 mux_tree_tapbuf_size10_5_sram[2]:16 0.0006488991 +17 mux_tree_tapbuf_size10_5_sram[2]:17 0.0001540186 +18 mux_tree_tapbuf_size10_5_sram[2]:18 5.111793e-05 +19 mux_tree_tapbuf_size10_5_sram[2]:19 0.0001821758 +20 mux_tree_tapbuf_size10_5_sram[2]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.906785e-05 +21 mux_tree_tapbuf_size10_5_sram[2]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.906785e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_5_sram[2]:19 0.152 +1 mux_tree_tapbuf_size10_5_sram[2]:14 mux_right_track_24\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_5_sram[2]:15 mux_tree_tapbuf_size10_5_sram[2]:14 0.001247768 +3 mux_tree_tapbuf_size10_5_sram[2]:16 mux_tree_tapbuf_size10_5_sram[2]:15 0.0045 +4 mux_tree_tapbuf_size10_5_sram[2]:16 mux_tree_tapbuf_size10_5_sram[2]:13 0.007245536 +5 mux_tree_tapbuf_size10_5_sram[2]:12 mux_tree_tapbuf_size10_5_sram[2]:11 0.002301339 +6 mux_tree_tapbuf_size10_5_sram[2]:13 mux_tree_tapbuf_size10_5_sram[2]:12 0.0045 +7 mux_tree_tapbuf_size10_5_sram[2]:11 mux_right_track_24\/mux_l3_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_5_sram[2]:10 mux_tree_tapbuf_size10_5_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size10_5_sram[2]:9 mux_tree_tapbuf_size10_5_sram[2]:8 0.001741072 +10 mux_tree_tapbuf_size10_5_sram[2]:7 mux_tree_tapbuf_size10_5_sram[2]:6 0.006120536 +11 mux_tree_tapbuf_size10_5_sram[2]:8 mux_tree_tapbuf_size10_5_sram[2]:7 0.0045 +12 mux_tree_tapbuf_size10_5_sram[2]:4 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size10_5_sram[2]:19 mux_tree_tapbuf_size10_5_sram[2]:18 0.0001861413 +14 mux_tree_tapbuf_size10_5_sram[2]:19 mux_tree_tapbuf_size10_5_sram[2]:10 0.002118304 +15 mux_tree_tapbuf_size10_5_sram[2]:18 mux_tree_tapbuf_size10_5_sram[2]:17 0.0045 +16 mux_tree_tapbuf_size10_5_sram[2]:17 mux_tree_tapbuf_size10_5_sram[2]:16 0.002388393 +17 mux_tree_tapbuf_size10_5_sram[2]:6 mux_tree_tapbuf_size10_5_sram[2]:5 0.0003035715 +18 mux_tree_tapbuf_size10_5_sram[2]:5 mux_tree_tapbuf_size10_5_sram[2]:4 0.0005334821 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[0] 0.005238511 //LENGTH 41.785 LUMPCC 0.0001561682 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 62.865 39.440 +*I mux_bottom_track_25\/mux_l1_in_2_:S I *L 0.00357 *C 53.460 44.880 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 61.355 42.500 +*I mux_bottom_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 73.240 50.320 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 72.320 44.880 +*N mux_tree_tapbuf_size10_8_sram[0]:5 *C 72.320 44.880 +*N mux_tree_tapbuf_size10_8_sram[0]:6 *C 73.203 50.320 +*N mux_tree_tapbuf_size10_8_sram[0]:7 *C 72.265 50.320 +*N mux_tree_tapbuf_size10_8_sram[0]:8 *C 72.220 50.275 +*N mux_tree_tapbuf_size10_8_sram[0]:9 *C 72.220 45.265 +*N mux_tree_tapbuf_size10_8_sram[0]:10 *C 72.265 45.213 +*N mux_tree_tapbuf_size10_8_sram[0]:11 *C 70.885 45.220 +*N mux_tree_tapbuf_size10_8_sram[0]:12 *C 70.840 45.175 +*N mux_tree_tapbuf_size10_8_sram[0]:13 *C 70.840 44.585 +*N mux_tree_tapbuf_size10_8_sram[0]:14 *C 70.795 44.540 +*N mux_tree_tapbuf_size10_8_sram[0]:15 *C 69.965 44.540 +*N mux_tree_tapbuf_size10_8_sram[0]:16 *C 69.920 44.495 +*N mux_tree_tapbuf_size10_8_sram[0]:17 *C 69.920 39.485 +*N mux_tree_tapbuf_size10_8_sram[0]:18 *C 69.875 39.440 +*N mux_tree_tapbuf_size10_8_sram[0]:19 *C 61.393 42.500 +*N mux_tree_tapbuf_size10_8_sram[0]:20 *C 53.498 44.880 +*N mux_tree_tapbuf_size10_8_sram[0]:21 *C 53.820 44.880 +*N mux_tree_tapbuf_size10_8_sram[0]:22 *C 53.820 44.540 +*N mux_tree_tapbuf_size10_8_sram[0]:23 *C 62.055 44.540 +*N mux_tree_tapbuf_size10_8_sram[0]:24 *C 62.100 44.495 +*N mux_tree_tapbuf_size10_8_sram[0]:25 *C 62.100 42.545 +*N mux_tree_tapbuf_size10_8_sram[0]:26 *C 62.100 42.500 +*N mux_tree_tapbuf_size10_8_sram[0]:27 *C 63.435 42.500 +*N mux_tree_tapbuf_size10_8_sram[0]:28 *C 63.480 42.455 +*N mux_tree_tapbuf_size10_8_sram[0]:29 *C 63.480 39.485 +*N mux_tree_tapbuf_size10_8_sram[0]:30 *C 63.480 39.440 +*N mux_tree_tapbuf_size10_8_sram[0]:31 *C 62.903 39.440 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_8_sram[0]:5 7.188552e-05 +6 mux_tree_tapbuf_size10_8_sram[0]:6 8.875215e-05 +7 mux_tree_tapbuf_size10_8_sram[0]:7 8.875215e-05 +8 mux_tree_tapbuf_size10_8_sram[0]:8 0.0003495481 +9 mux_tree_tapbuf_size10_8_sram[0]:9 0.0003495481 +10 mux_tree_tapbuf_size10_8_sram[0]:10 0.0001261368 +11 mux_tree_tapbuf_size10_8_sram[0]:11 8.673411e-05 +12 mux_tree_tapbuf_size10_8_sram[0]:12 6.303368e-05 +13 mux_tree_tapbuf_size10_8_sram[0]:13 6.303368e-05 +14 mux_tree_tapbuf_size10_8_sram[0]:14 5.008531e-05 +15 mux_tree_tapbuf_size10_8_sram[0]:15 5.008531e-05 +16 mux_tree_tapbuf_size10_8_sram[0]:16 0.0003501389 +17 mux_tree_tapbuf_size10_8_sram[0]:17 0.0003501389 +18 mux_tree_tapbuf_size10_8_sram[0]:18 0.000376468 +19 mux_tree_tapbuf_size10_8_sram[0]:19 5.712369e-05 +20 mux_tree_tapbuf_size10_8_sram[0]:20 3.560501e-05 +21 mux_tree_tapbuf_size10_8_sram[0]:21 6.173305e-05 +22 mux_tree_tapbuf_size10_8_sram[0]:22 0.0005125684 +23 mux_tree_tapbuf_size10_8_sram[0]:23 0.0004864404 +24 mux_tree_tapbuf_size10_8_sram[0]:24 0.0001352961 +25 mux_tree_tapbuf_size10_8_sram[0]:25 0.0001352961 +26 mux_tree_tapbuf_size10_8_sram[0]:26 0.0001839667 +27 mux_tree_tapbuf_size10_8_sram[0]:27 9.566324e-05 +28 mux_tree_tapbuf_size10_8_sram[0]:28 0.0002076659 +29 mux_tree_tapbuf_size10_8_sram[0]:29 0.0002076659 +30 mux_tree_tapbuf_size10_8_sram[0]:30 0.0004518557 +31 mux_tree_tapbuf_size10_8_sram[0]:31 4.212205e-05 +32 mux_tree_tapbuf_size10_8_sram[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.334104e-05 +33 mux_tree_tapbuf_size10_8_sram[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.334104e-05 +34 mux_tree_tapbuf_size10_8_sram[0]:14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.474306e-05 +35 mux_tree_tapbuf_size10_8_sram[0]:15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.474306e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_8_sram[0]:31 0.152 +1 mux_tree_tapbuf_size10_8_sram[0]:10 mux_tree_tapbuf_size10_8_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size10_8_sram[0]:10 mux_tree_tapbuf_size10_8_sram[0]:5 0.0001807065 +3 mux_tree_tapbuf_size10_8_sram[0]:9 mux_tree_tapbuf_size10_8_sram[0]:8 0.004473215 +4 mux_tree_tapbuf_size10_8_sram[0]:7 mux_tree_tapbuf_size10_8_sram[0]:6 0.0008370536 +5 mux_tree_tapbuf_size10_8_sram[0]:8 mux_tree_tapbuf_size10_8_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size10_8_sram[0]:6 mux_bottom_track_25\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size10_8_sram[0]:11 mux_tree_tapbuf_size10_8_sram[0]:10 0.001232143 +8 mux_tree_tapbuf_size10_8_sram[0]:12 mux_tree_tapbuf_size10_8_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size10_8_sram[0]:14 mux_tree_tapbuf_size10_8_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size10_8_sram[0]:13 mux_tree_tapbuf_size10_8_sram[0]:12 0.0005267857 +11 mux_tree_tapbuf_size10_8_sram[0]:15 mux_tree_tapbuf_size10_8_sram[0]:14 0.0007410714 +12 mux_tree_tapbuf_size10_8_sram[0]:16 mux_tree_tapbuf_size10_8_sram[0]:15 0.0045 +13 mux_tree_tapbuf_size10_8_sram[0]:18 mux_tree_tapbuf_size10_8_sram[0]:17 0.0045 +14 mux_tree_tapbuf_size10_8_sram[0]:17 mux_tree_tapbuf_size10_8_sram[0]:16 0.004473215 +15 mux_tree_tapbuf_size10_8_sram[0]:30 mux_tree_tapbuf_size10_8_sram[0]:29 0.0045 +16 mux_tree_tapbuf_size10_8_sram[0]:30 mux_tree_tapbuf_size10_8_sram[0]:18 0.005709822 +17 mux_tree_tapbuf_size10_8_sram[0]:29 mux_tree_tapbuf_size10_8_sram[0]:28 0.002651786 +18 mux_tree_tapbuf_size10_8_sram[0]:27 mux_tree_tapbuf_size10_8_sram[0]:26 0.001191964 +19 mux_tree_tapbuf_size10_8_sram[0]:28 mux_tree_tapbuf_size10_8_sram[0]:27 0.0045 +20 mux_tree_tapbuf_size10_8_sram[0]:26 mux_tree_tapbuf_size10_8_sram[0]:25 0.0045 +21 mux_tree_tapbuf_size10_8_sram[0]:26 mux_tree_tapbuf_size10_8_sram[0]:19 0.0006316964 +22 mux_tree_tapbuf_size10_8_sram[0]:25 mux_tree_tapbuf_size10_8_sram[0]:24 0.001741072 +23 mux_tree_tapbuf_size10_8_sram[0]:23 mux_tree_tapbuf_size10_8_sram[0]:22 0.007352679 +24 mux_tree_tapbuf_size10_8_sram[0]:24 mux_tree_tapbuf_size10_8_sram[0]:23 0.0045 +25 mux_tree_tapbuf_size10_8_sram[0]:20 mux_bottom_track_25\/mux_l1_in_2_:S 0.152 +26 mux_tree_tapbuf_size10_8_sram[0]:19 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +27 mux_tree_tapbuf_size10_8_sram[0]:5 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +28 mux_tree_tapbuf_size10_8_sram[0]:31 mux_tree_tapbuf_size10_8_sram[0]:30 0.000515625 +29 mux_tree_tapbuf_size10_8_sram[0]:21 mux_tree_tapbuf_size10_8_sram[0]:20 0.0002879464 +30 mux_tree_tapbuf_size10_8_sram[0]:22 mux_tree_tapbuf_size10_8_sram[0]:21 0.0003035714 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_4_ccff_tail[0] 0.0009883452 //LENGTH 7.300 LUMPCC 0.0001407826 DR + +*CONN +*I mem_right_track_16\/FTB_17__68:X O *L 0 *C 95.445 39.100 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 92.175 42.500 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 *C 92.175 42.500 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 *C 92.460 42.500 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 *C 92.460 42.455 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 *C 92.460 39.145 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 *C 92.505 39.100 +*N mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 *C 95.407 39.100 + +*CAP +0 mem_right_track_16\/FTB_17__68:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 5.195053e-05 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 5.680798e-05 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.0001576907 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0001576907 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.0002107114 +7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.0002107114 +8 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 chanx_right_in[16]:47 7.03913e-05 +9 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 chanx_right_in[16]:48 7.03913e-05 + +*RES +0 mem_right_track_16\/FTB_17__68:X mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:4 0.002955357 +6 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_4_ccff_tail[0]:6 0.002591518 + +*END + +*D_NET mux_tree_tapbuf_size12_0_sram[3] 0.002760059 //LENGTH 20.030 LUMPCC 0.0008761956 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 84.025 118.320 +*I mem_top_track_0\/FTB_1__52:A I *L 0.001746 *C 70.840 112.880 +*I mux_top_track_0\/mux_l4_in_0_:S I *L 0.00357 *C 82.700 112.590 +*N mux_tree_tapbuf_size12_0_sram[3]:3 *C 82.700 112.590 +*N mux_tree_tapbuf_size12_0_sram[3]:4 *C 70.877 112.880 +*N mux_tree_tapbuf_size12_0_sram[3]:5 *C 82.700 112.880 +*N mux_tree_tapbuf_size12_0_sram[3]:6 *C 83.215 112.880 +*N mux_tree_tapbuf_size12_0_sram[3]:7 *C 83.260 112.925 +*N mux_tree_tapbuf_size12_0_sram[3]:8 *C 83.260 118.275 +*N mux_tree_tapbuf_size12_0_sram[3]:9 *C 83.305 118.320 +*N mux_tree_tapbuf_size12_0_sram[3]:10 *C 83.987 118.320 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_0\/FTB_1__52:A 1e-06 +2 mux_top_track_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_0_sram[3]:3 5.762163e-05 +4 mux_tree_tapbuf_size12_0_sram[3]:4 0.0004650453 +5 mux_tree_tapbuf_size12_0_sram[3]:5 0.0005432238 +6 mux_tree_tapbuf_size12_0_sram[3]:6 5.007071e-05 +7 mux_tree_tapbuf_size12_0_sram[3]:7 0.0003176424 +8 mux_tree_tapbuf_size12_0_sram[3]:8 0.0003176424 +9 mux_tree_tapbuf_size12_0_sram[3]:9 6.480849e-05 +10 mux_tree_tapbuf_size12_0_sram[3]:10 6.480849e-05 +11 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 8.693831e-05 +12 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 8.693831e-05 +13 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001869157 +14 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001869157 +15 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.966366e-05 +16 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.430631e-05 +17 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.966366e-05 +18 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 2.430631e-05 +19 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.866227e-05 +20 mux_tree_tapbuf_size12_0_sram[3]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.924323e-05 +21 mux_tree_tapbuf_size12_0_sram[3]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 2.368482e-06 +22 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.368482e-06 +23 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.866227e-05 +24 mux_tree_tapbuf_size12_0_sram[3]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.924323e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_0_sram[3]:10 0.152 +1 mux_tree_tapbuf_size12_0_sram[3]:4 mem_top_track_0\/FTB_1__52:A 0.152 +2 mux_tree_tapbuf_size12_0_sram[3]:6 mux_tree_tapbuf_size12_0_sram[3]:5 0.0004598215 +3 mux_tree_tapbuf_size12_0_sram[3]:7 mux_tree_tapbuf_size12_0_sram[3]:6 0.0045 +4 mux_tree_tapbuf_size12_0_sram[3]:9 mux_tree_tapbuf_size12_0_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size12_0_sram[3]:8 mux_tree_tapbuf_size12_0_sram[3]:7 0.004776786 +6 mux_tree_tapbuf_size12_0_sram[3]:10 mux_tree_tapbuf_size12_0_sram[3]:9 0.000609375 +7 mux_tree_tapbuf_size12_0_sram[3]:3 mux_top_track_0\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_0_sram[3]:5 mux_tree_tapbuf_size12_0_sram[3]:4 0.0105558 +9 mux_tree_tapbuf_size12_0_sram[3]:5 mux_tree_tapbuf_size12_0_sram[3]:3 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size12_3_sram[2] 0.003531839 //LENGTH 26.985 LUMPCC 0.0009393953 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 108.865 93.840 +*I mux_right_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 118.680 96.385 +*I mux_right_track_2\/mux_l3_in_1_:S I *L 0.00357 *C 118.120 91.120 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 119.315 98.940 +*N mux_tree_tapbuf_size12_3_sram[2]:4 *C 119.278 98.940 +*N mux_tree_tapbuf_size12_3_sram[2]:5 *C 117.760 98.940 +*N mux_tree_tapbuf_size12_3_sram[2]:6 *C 118.105 91.120 +*N mux_tree_tapbuf_size12_3_sram[2]:7 *C 117.782 91.120 +*N mux_tree_tapbuf_size12_3_sram[2]:8 *C 117.760 91.165 +*N mux_tree_tapbuf_size12_3_sram[2]:9 *C 118.643 96.280 +*N mux_tree_tapbuf_size12_3_sram[2]:10 *C 117.805 96.220 +*N mux_tree_tapbuf_size12_3_sram[2]:11 *C 117.760 96.205 +*N mux_tree_tapbuf_size12_3_sram[2]:12 *C 117.760 96.560 +*N mux_tree_tapbuf_size12_3_sram[2]:13 *C 117.760 98.555 +*N mux_tree_tapbuf_size12_3_sram[2]:14 *C 117.760 98.630 +*N mux_tree_tapbuf_size12_3_sram[2]:15 *C 109.985 98.600 +*N mux_tree_tapbuf_size12_3_sram[2]:16 *C 109.940 98.555 +*N mux_tree_tapbuf_size12_3_sram[2]:17 *C 109.940 93.885 +*N mux_tree_tapbuf_size12_3_sram[2]:18 *C 109.895 93.840 +*N mux_tree_tapbuf_size12_3_sram[2]:19 *C 108.903 93.840 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:S 1e-06 +2 mux_right_track_2\/mux_l3_in_1_:S 1e-06 +3 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size12_3_sram[2]:4 0.0001055702 +5 mux_tree_tapbuf_size12_3_sram[2]:5 0.0001312796 +6 mux_tree_tapbuf_size12_3_sram[2]:6 5.866869e-05 +7 mux_tree_tapbuf_size12_3_sram[2]:7 5.866869e-05 +8 mux_tree_tapbuf_size12_3_sram[2]:8 0.0002190992 +9 mux_tree_tapbuf_size12_3_sram[2]:9 9.370662e-05 +10 mux_tree_tapbuf_size12_3_sram[2]:10 9.370662e-05 +11 mux_tree_tapbuf_size12_3_sram[2]:11 0.0002415722 +12 mux_tree_tapbuf_size12_3_sram[2]:12 8.788452e-05 +13 mux_tree_tapbuf_size12_3_sram[2]:13 6.541156e-05 +14 mux_tree_tapbuf_size12_3_sram[2]:14 0.0004332055 +15 mux_tree_tapbuf_size12_3_sram[2]:15 0.0004074961 +16 mux_tree_tapbuf_size12_3_sram[2]:16 0.0001927835 +17 mux_tree_tapbuf_size12_3_sram[2]:17 0.0001927835 +18 mux_tree_tapbuf_size12_3_sram[2]:18 0.0001033034 +19 mux_tree_tapbuf_size12_3_sram[2]:19 0.0001033034 +20 mux_tree_tapbuf_size12_3_sram[2]:8 prog_clk[0]:149 0.0001273151 +21 mux_tree_tapbuf_size12_3_sram[2]:8 prog_clk[0]:160 3.75486e-06 +22 mux_tree_tapbuf_size12_3_sram[2]:11 prog_clk[0]:143 0.0001273151 +23 mux_tree_tapbuf_size12_3_sram[2]:11 prog_clk[0]:149 1.875651e-05 +24 mux_tree_tapbuf_size12_3_sram[2]:4 prog_clk[0]:142 1.324128e-05 +25 mux_tree_tapbuf_size12_3_sram[2]:15 prog_clk[0]:141 4.431706e-07 +26 mux_tree_tapbuf_size12_3_sram[2]:14 prog_clk[0]:142 4.431706e-07 +27 mux_tree_tapbuf_size12_3_sram[2]:13 prog_clk[0]:143 5.726283e-05 +28 mux_tree_tapbuf_size12_3_sram[2]:5 prog_clk[0]:141 1.324128e-05 +29 mux_tree_tapbuf_size12_3_sram[2]:12 prog_clk[0]:143 1.500165e-05 +30 mux_tree_tapbuf_size12_3_sram[2]:12 prog_clk[0]:149 5.726283e-05 +31 mux_tree_tapbuf_size12_3_sram[2]:11 mux_tree_tapbuf_size12_3_sram[1]:7 2.470081e-06 +32 mux_tree_tapbuf_size12_3_sram[2]:15 mux_tree_tapbuf_size12_3_sram[1]:28 4.327057e-06 +33 mux_tree_tapbuf_size12_3_sram[2]:15 mux_tree_tapbuf_size12_3_sram[1]:29 7.238237e-05 +34 mux_tree_tapbuf_size12_3_sram[2]:15 mux_tree_tapbuf_size12_3_sram[1]:31 1.970802e-05 +35 mux_tree_tapbuf_size12_3_sram[2]:16 mux_tree_tapbuf_size12_3_sram[1]:27 0.0001307101 +36 mux_tree_tapbuf_size12_3_sram[2]:17 mux_tree_tapbuf_size12_3_sram[1]:26 0.0001307101 +37 mux_tree_tapbuf_size12_3_sram[2]:14 mux_tree_tapbuf_size12_3_sram[1]:9 7.238237e-05 +38 mux_tree_tapbuf_size12_3_sram[2]:14 mux_tree_tapbuf_size12_3_sram[1]:29 4.327057e-06 +39 mux_tree_tapbuf_size12_3_sram[2]:14 mux_tree_tapbuf_size12_3_sram[1]:30 1.970802e-05 +40 mux_tree_tapbuf_size12_3_sram[2]:13 mux_tree_tapbuf_size12_3_sram[1]:8 2.308112e-05 +41 mux_tree_tapbuf_size12_3_sram[2]:12 mux_tree_tapbuf_size12_3_sram[1]:7 2.308112e-05 +42 mux_tree_tapbuf_size12_3_sram[2]:12 mux_tree_tapbuf_size12_3_sram[1]:8 2.470081e-06 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_3_sram[2]:19 0.152 +1 mux_tree_tapbuf_size12_3_sram[2]:6 mux_right_track_2\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size12_3_sram[2]:7 mux_tree_tapbuf_size12_3_sram[2]:6 0.0001752717 +3 mux_tree_tapbuf_size12_3_sram[2]:8 mux_tree_tapbuf_size12_3_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size12_3_sram[2]:9 mux_right_track_2\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size12_3_sram[2]:10 mux_tree_tapbuf_size12_3_sram[2]:9 0.0007477679 +6 mux_tree_tapbuf_size12_3_sram[2]:11 mux_tree_tapbuf_size12_3_sram[2]:10 0.0045 +7 mux_tree_tapbuf_size12_3_sram[2]:11 mux_tree_tapbuf_size12_3_sram[2]:8 0.0045 +8 mux_tree_tapbuf_size12_3_sram[2]:4 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +9 mux_tree_tapbuf_size12_3_sram[2]:15 mux_tree_tapbuf_size12_3_sram[2]:14 0.006941964 +10 mux_tree_tapbuf_size12_3_sram[2]:16 mux_tree_tapbuf_size12_3_sram[2]:15 0.0045 +11 mux_tree_tapbuf_size12_3_sram[2]:18 mux_tree_tapbuf_size12_3_sram[2]:17 0.0045 +12 mux_tree_tapbuf_size12_3_sram[2]:17 mux_tree_tapbuf_size12_3_sram[2]:16 0.004169643 +13 mux_tree_tapbuf_size12_3_sram[2]:19 mux_tree_tapbuf_size12_3_sram[2]:18 0.0008861608 +14 mux_tree_tapbuf_size12_3_sram[2]:14 mux_tree_tapbuf_size12_3_sram[2]:13 0.0045 +15 mux_tree_tapbuf_size12_3_sram[2]:14 mux_tree_tapbuf_size12_3_sram[2]:5 0.0002767857 +16 mux_tree_tapbuf_size12_3_sram[2]:13 mux_tree_tapbuf_size12_3_sram[2]:12 0.00178125 +17 mux_tree_tapbuf_size12_3_sram[2]:5 mux_tree_tapbuf_size12_3_sram[2]:4 0.001354911 +18 mux_tree_tapbuf_size12_3_sram[2]:12 mux_tree_tapbuf_size12_3_sram[2]:11 0.000221875 + +*END + +*D_NET mux_tree_tapbuf_size12_6_sram[1] 0.01270483 //LENGTH 79.720 LUMPCC 0.002172906 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 31.125 80.580 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 73.240 85.000 +*I mux_left_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 67.260 85.390 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 30.075 82.620 +*I mux_left_track_1\/mux_l2_in_2_:S I *L 0.00357 *C 19.220 79.950 +*I mux_left_track_1\/mux_l2_in_3_:S I *L 0.00357 *C 17.380 83.300 +*N mux_tree_tapbuf_size12_6_sram[1]:6 *C 17.418 83.300 +*N mux_tree_tapbuf_size12_6_sram[1]:7 *C 20.195 83.300 +*N mux_tree_tapbuf_size12_6_sram[1]:8 *C 20.240 83.255 +*N mux_tree_tapbuf_size12_6_sram[1]:9 *C 19.220 79.950 +*N mux_tree_tapbuf_size12_6_sram[1]:10 *C 19.220 79.560 +*N mux_tree_tapbuf_size12_6_sram[1]:11 *C 20.195 79.560 +*N mux_tree_tapbuf_size12_6_sram[1]:12 *C 20.240 79.560 +*N mux_tree_tapbuf_size12_6_sram[1]:13 *C 20.240 78.938 +*N mux_tree_tapbuf_size12_6_sram[1]:14 *C 20.248 78.880 +*N mux_tree_tapbuf_size12_6_sram[1]:15 *C 31.733 78.880 +*N mux_tree_tapbuf_size12_6_sram[1]:16 *C 31.740 78.938 +*N mux_tree_tapbuf_size12_6_sram[1]:17 *C 30.113 82.620 +*N mux_tree_tapbuf_size12_6_sram[1]:18 *C 31.695 82.620 +*N mux_tree_tapbuf_size12_6_sram[1]:19 *C 31.740 82.575 +*N mux_tree_tapbuf_size12_6_sram[1]:20 *C 67.260 85.390 +*N mux_tree_tapbuf_size12_6_sram[1]:21 *C 73.203 85.000 +*N mux_tree_tapbuf_size12_6_sram[1]:22 *C 67.260 85.000 +*N mux_tree_tapbuf_size12_6_sram[1]:23 *C 66.285 85.000 +*N mux_tree_tapbuf_size12_6_sram[1]:24 *C 66.240 85.045 +*N mux_tree_tapbuf_size12_6_sram[1]:25 *C 66.240 86.303 +*N mux_tree_tapbuf_size12_6_sram[1]:26 *C 66.233 86.360 +*N mux_tree_tapbuf_size12_6_sram[1]:27 *C 54.748 86.360 +*N mux_tree_tapbuf_size12_6_sram[1]:28 *C 54.740 86.303 +*N mux_tree_tapbuf_size12_6_sram[1]:29 *C 54.740 84.320 +*N mux_tree_tapbuf_size12_6_sram[1]:30 *C 54.280 84.320 +*N mux_tree_tapbuf_size12_6_sram[1]:31 *C 54.280 80.978 +*N mux_tree_tapbuf_size12_6_sram[1]:32 *C 54.273 80.920 +*N mux_tree_tapbuf_size12_6_sram[1]:33 *C 31.748 80.920 +*N mux_tree_tapbuf_size12_6_sram[1]:34 *C 31.740 80.978 +*N mux_tree_tapbuf_size12_6_sram[1]:35 *C 31.740 80.535 +*N mux_tree_tapbuf_size12_6_sram[1]:36 *C 31.695 80.580 +*N mux_tree_tapbuf_size12_6_sram[1]:37 *C 31.163 80.580 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_1\/mux_l2_in_1_:S 1e-06 +3 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_left_track_1\/mux_l2_in_2_:S 1e-06 +5 mux_left_track_1\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size12_6_sram[1]:6 0.0001659655 +7 mux_tree_tapbuf_size12_6_sram[1]:7 0.0001659655 +8 mux_tree_tapbuf_size12_6_sram[1]:8 0.0002285265 +9 mux_tree_tapbuf_size12_6_sram[1]:9 6.192632e-05 +10 mux_tree_tapbuf_size12_6_sram[1]:10 0.0001163409 +11 mux_tree_tapbuf_size12_6_sram[1]:11 8.455801e-05 +12 mux_tree_tapbuf_size12_6_sram[1]:12 0.0003100868 +13 mux_tree_tapbuf_size12_6_sram[1]:13 4.803303e-05 +14 mux_tree_tapbuf_size12_6_sram[1]:14 0.0009928616 +15 mux_tree_tapbuf_size12_6_sram[1]:15 0.0009928616 +16 mux_tree_tapbuf_size12_6_sram[1]:16 0.0001439089 +17 mux_tree_tapbuf_size12_6_sram[1]:17 0.0001737318 +18 mux_tree_tapbuf_size12_6_sram[1]:18 0.0001737318 +19 mux_tree_tapbuf_size12_6_sram[1]:19 0.0001222636 +20 mux_tree_tapbuf_size12_6_sram[1]:20 6.382096e-05 +21 mux_tree_tapbuf_size12_6_sram[1]:21 0.0003994494 +22 mux_tree_tapbuf_size12_6_sram[1]:22 0.0005159545 +23 mux_tree_tapbuf_size12_6_sram[1]:23 8.857401e-05 +24 mux_tree_tapbuf_size12_6_sram[1]:24 9.585113e-05 +25 mux_tree_tapbuf_size12_6_sram[1]:25 9.585113e-05 +26 mux_tree_tapbuf_size12_6_sram[1]:26 0.0009439212 +27 mux_tree_tapbuf_size12_6_sram[1]:27 0.0009439212 +28 mux_tree_tapbuf_size12_6_sram[1]:28 0.00016568 +29 mux_tree_tapbuf_size12_6_sram[1]:29 0.0001987865 +30 mux_tree_tapbuf_size12_6_sram[1]:30 0.0002746811 +31 mux_tree_tapbuf_size12_6_sram[1]:31 0.0002415747 +32 mux_tree_tapbuf_size12_6_sram[1]:32 0.001136836 +33 mux_tree_tapbuf_size12_6_sram[1]:33 0.001136836 +34 mux_tree_tapbuf_size12_6_sram[1]:34 0.0001482065 +35 mux_tree_tapbuf_size12_6_sram[1]:35 0.0001698518 +36 mux_tree_tapbuf_size12_6_sram[1]:36 6.268173e-05 +37 mux_tree_tapbuf_size12_6_sram[1]:37 6.268173e-05 +38 mux_tree_tapbuf_size12_6_sram[1]:33 chanx_left_in[4]:41 3.192787e-06 +39 mux_tree_tapbuf_size12_6_sram[1]:33 chanx_left_in[4]:45 5.381788e-07 +40 mux_tree_tapbuf_size12_6_sram[1]:32 chanx_left_in[4]:40 3.192787e-06 +41 mux_tree_tapbuf_size12_6_sram[1]:32 chanx_left_in[4]:44 5.381788e-07 +42 mux_tree_tapbuf_size12_6_sram[1]:27 chanx_left_in[4]:38 0.0002060084 +43 mux_tree_tapbuf_size12_6_sram[1]:27 chanx_left_in[4]:39 0.0001680097 +44 mux_tree_tapbuf_size12_6_sram[1]:26 chanx_left_in[4]:9 0.0002060084 +45 mux_tree_tapbuf_size12_6_sram[1]:26 chanx_left_in[4]:38 0.0001680097 +46 mux_tree_tapbuf_size12_6_sram[1]:33 chanx_left_in[14]:26 0.0004090404 +47 mux_tree_tapbuf_size12_6_sram[1]:33 chanx_left_in[14]:27 2.265378e-05 +48 mux_tree_tapbuf_size12_6_sram[1]:32 chanx_left_in[14]:21 0.0004090404 +49 mux_tree_tapbuf_size12_6_sram[1]:32 chanx_left_in[14]:26 2.265378e-05 +50 mux_tree_tapbuf_size12_6_sram[1]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.888919e-06 +51 mux_tree_tapbuf_size12_6_sram[1]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.043825e-05 +52 mux_tree_tapbuf_size12_6_sram[1]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.570468e-05 +53 mux_tree_tapbuf_size12_6_sram[1]:22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.832717e-05 +54 mux_tree_tapbuf_size12_6_sram[1]:22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.570468e-05 +55 mux_tree_tapbuf_size12_6_sram[1]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 4.129765e-05 +56 mux_tree_tapbuf_size12_6_sram[1]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 4.129765e-05 +57 mux_tree_tapbuf_size12_6_sram[1]:33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 4.256824e-05 +58 mux_tree_tapbuf_size12_6_sram[1]:33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 9.82643e-05 +59 mux_tree_tapbuf_size12_6_sram[1]:32 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 9.82643e-05 +60 mux_tree_tapbuf_size12_6_sram[1]:32 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 4.256824e-05 +61 mux_tree_tapbuf_size12_6_sram[1]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 2.084811e-05 +62 mux_tree_tapbuf_size12_6_sram[1]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 2.084811e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_6_sram[1]:37 0.152 +1 mux_tree_tapbuf_size12_6_sram[1]:6 mux_left_track_1\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size12_6_sram[1]:7 mux_tree_tapbuf_size12_6_sram[1]:6 0.002479911 +3 mux_tree_tapbuf_size12_6_sram[1]:8 mux_tree_tapbuf_size12_6_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size12_6_sram[1]:34 mux_tree_tapbuf_size12_6_sram[1]:33 0.00341 +5 mux_tree_tapbuf_size12_6_sram[1]:34 mux_tree_tapbuf_size12_6_sram[1]:19 0.001426339 +6 mux_tree_tapbuf_size12_6_sram[1]:33 mux_tree_tapbuf_size12_6_sram[1]:32 0.003528916 +7 mux_tree_tapbuf_size12_6_sram[1]:31 mux_tree_tapbuf_size12_6_sram[1]:30 0.002984375 +8 mux_tree_tapbuf_size12_6_sram[1]:32 mux_tree_tapbuf_size12_6_sram[1]:31 0.00341 +9 mux_tree_tapbuf_size12_6_sram[1]:28 mux_tree_tapbuf_size12_6_sram[1]:27 0.00341 +10 mux_tree_tapbuf_size12_6_sram[1]:27 mux_tree_tapbuf_size12_6_sram[1]:26 0.001799316 +11 mux_tree_tapbuf_size12_6_sram[1]:25 mux_tree_tapbuf_size12_6_sram[1]:24 0.001122768 +12 mux_tree_tapbuf_size12_6_sram[1]:26 mux_tree_tapbuf_size12_6_sram[1]:25 0.00341 +13 mux_tree_tapbuf_size12_6_sram[1]:23 mux_tree_tapbuf_size12_6_sram[1]:22 0.0008705357 +14 mux_tree_tapbuf_size12_6_sram[1]:24 mux_tree_tapbuf_size12_6_sram[1]:23 0.0045 +15 mux_tree_tapbuf_size12_6_sram[1]:16 mux_tree_tapbuf_size12_6_sram[1]:15 0.00341 +16 mux_tree_tapbuf_size12_6_sram[1]:15 mux_tree_tapbuf_size12_6_sram[1]:14 0.001799317 +17 mux_tree_tapbuf_size12_6_sram[1]:13 mux_tree_tapbuf_size12_6_sram[1]:12 0.0005558036 +18 mux_tree_tapbuf_size12_6_sram[1]:14 mux_tree_tapbuf_size12_6_sram[1]:13 0.00341 +19 mux_tree_tapbuf_size12_6_sram[1]:20 mux_left_track_1\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size12_6_sram[1]:18 mux_tree_tapbuf_size12_6_sram[1]:17 0.001412946 +21 mux_tree_tapbuf_size12_6_sram[1]:19 mux_tree_tapbuf_size12_6_sram[1]:18 0.0045 +22 mux_tree_tapbuf_size12_6_sram[1]:17 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +23 mux_tree_tapbuf_size12_6_sram[1]:36 mux_tree_tapbuf_size12_6_sram[1]:35 0.0045 +24 mux_tree_tapbuf_size12_6_sram[1]:35 mux_tree_tapbuf_size12_6_sram[1]:34 0.0002127404 +25 mux_tree_tapbuf_size12_6_sram[1]:35 mux_tree_tapbuf_size12_6_sram[1]:16 0.001426339 +26 mux_tree_tapbuf_size12_6_sram[1]:37 mux_tree_tapbuf_size12_6_sram[1]:36 0.0004754464 +27 mux_tree_tapbuf_size12_6_sram[1]:11 mux_tree_tapbuf_size12_6_sram[1]:10 0.0008705358 +28 mux_tree_tapbuf_size12_6_sram[1]:12 mux_tree_tapbuf_size12_6_sram[1]:11 0.0045 +29 mux_tree_tapbuf_size12_6_sram[1]:12 mux_tree_tapbuf_size12_6_sram[1]:8 0.003299107 +30 mux_tree_tapbuf_size12_6_sram[1]:9 mux_left_track_1\/mux_l2_in_2_:S 0.152 +31 mux_tree_tapbuf_size12_6_sram[1]:21 mux_left_track_1\/mux_l2_in_0_:S 0.152 +32 mux_tree_tapbuf_size12_6_sram[1]:10 mux_tree_tapbuf_size12_6_sram[1]:9 0.0003482143 +33 mux_tree_tapbuf_size12_6_sram[1]:22 mux_tree_tapbuf_size12_6_sram[1]:21 0.005305804 +34 mux_tree_tapbuf_size12_6_sram[1]:22 mux_tree_tapbuf_size12_6_sram[1]:20 0.0003482143 +35 mux_tree_tapbuf_size12_6_sram[1]:30 mux_tree_tapbuf_size12_6_sram[1]:29 0.0004107143 +36 mux_tree_tapbuf_size12_6_sram[1]:29 mux_tree_tapbuf_size12_6_sram[1]:28 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size16_2_sram[4] 0.001424296 //LENGTH 11.805 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q O *L 0 *C 45.385 17.340 +*I mem_bottom_track_5\/FTB_11__62:A I *L 0.001746 *C 46.920 14.960 +*I mux_bottom_track_5\/mux_l5_in_0_:S I *L 0.00357 *C 46.820 12.535 +*N mux_tree_tapbuf_size16_2_sram[4]:3 *C 46.820 12.535 +*N mux_tree_tapbuf_size16_2_sram[4]:4 *C 46.958 14.960 +*N mux_tree_tapbuf_size16_2_sram[4]:5 *C 47.795 14.960 +*N mux_tree_tapbuf_size16_2_sram[4]:6 *C 47.840 14.915 +*N mux_tree_tapbuf_size16_2_sram[4]:7 *C 47.840 12.965 +*N mux_tree_tapbuf_size16_2_sram[4]:8 *C 47.795 12.920 +*N mux_tree_tapbuf_size16_2_sram[4]:9 *C 46.820 12.920 +*N mux_tree_tapbuf_size16_2_sram[4]:10 *C 45.585 12.920 +*N mux_tree_tapbuf_size16_2_sram[4]:11 *C 45.540 12.965 +*N mux_tree_tapbuf_size16_2_sram[4]:12 *C 45.540 17.295 +*N mux_tree_tapbuf_size16_2_sram[4]:13 *C 45.540 17.340 +*N mux_tree_tapbuf_size16_2_sram[4]:14 *C 45.385 17.340 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q 1e-06 +1 mem_bottom_track_5\/FTB_11__62:A 1e-06 +2 mux_bottom_track_5\/mux_l5_in_0_:S 1e-06 +3 mux_tree_tapbuf_size16_2_sram[4]:3 5.541876e-05 +4 mux_tree_tapbuf_size16_2_sram[4]:4 6.663813e-05 +5 mux_tree_tapbuf_size16_2_sram[4]:5 6.663813e-05 +6 mux_tree_tapbuf_size16_2_sram[4]:6 0.0001269191 +7 mux_tree_tapbuf_size16_2_sram[4]:7 0.0001269191 +8 mux_tree_tapbuf_size16_2_sram[4]:8 8.69267e-05 +9 mux_tree_tapbuf_size16_2_sram[4]:9 0.000221524 +10 mux_tree_tapbuf_size16_2_sram[4]:10 0.00010608 +11 mux_tree_tapbuf_size16_2_sram[4]:11 0.0002348441 +12 mux_tree_tapbuf_size16_2_sram[4]:12 0.0002348441 +13 mux_tree_tapbuf_size16_2_sram[4]:13 4.940918e-05 +14 mux_tree_tapbuf_size16_2_sram[4]:14 4.513458e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q mux_tree_tapbuf_size16_2_sram[4]:14 0.152 +1 mux_tree_tapbuf_size16_2_sram[4]:8 mux_tree_tapbuf_size16_2_sram[4]:7 0.0045 +2 mux_tree_tapbuf_size16_2_sram[4]:7 mux_tree_tapbuf_size16_2_sram[4]:6 0.001741071 +3 mux_tree_tapbuf_size16_2_sram[4]:5 mux_tree_tapbuf_size16_2_sram[4]:4 0.0007477679 +4 mux_tree_tapbuf_size16_2_sram[4]:6 mux_tree_tapbuf_size16_2_sram[4]:5 0.0045 +5 mux_tree_tapbuf_size16_2_sram[4]:4 mem_bottom_track_5\/FTB_11__62:A 0.152 +6 mux_tree_tapbuf_size16_2_sram[4]:3 mux_bottom_track_5\/mux_l5_in_0_:S 0.152 +7 mux_tree_tapbuf_size16_2_sram[4]:10 mux_tree_tapbuf_size16_2_sram[4]:9 0.001102679 +8 mux_tree_tapbuf_size16_2_sram[4]:11 mux_tree_tapbuf_size16_2_sram[4]:10 0.0045 +9 mux_tree_tapbuf_size16_2_sram[4]:13 mux_tree_tapbuf_size16_2_sram[4]:12 0.0045 +10 mux_tree_tapbuf_size16_2_sram[4]:12 mux_tree_tapbuf_size16_2_sram[4]:11 0.003866072 +11 mux_tree_tapbuf_size16_2_sram[4]:14 mux_tree_tapbuf_size16_2_sram[4]:13 8.423914e-05 +12 mux_tree_tapbuf_size16_2_sram[4]:9 mux_tree_tapbuf_size16_2_sram[4]:8 0.0008705358 +13 mux_tree_tapbuf_size16_2_sram[4]:9 mux_tree_tapbuf_size16_2_sram[4]:3 0.0003437501 + +*END + +*D_NET mux_tree_tapbuf_size16_3_sram[4] 0.001786405 //LENGTH 13.233 LUMPCC 0 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q O *L 0 *C 14.565 85.680 +*I mux_left_track_5\/mux_l5_in_0_:S I *L 0.00357 *C 8.840 89.080 +*I mem_left_track_5\/FTB_12__63:A I *L 0.001746 *C 13.800 82.960 +*N mux_tree_tapbuf_size16_3_sram[4]:3 *C 13.800 82.960 +*N mux_tree_tapbuf_size16_3_sram[4]:4 *C 13.800 83.005 +*N mux_tree_tapbuf_size16_3_sram[4]:5 *C 8.878 89.080 +*N mux_tree_tapbuf_size16_3_sram[4]:6 *C 12.375 89.080 +*N mux_tree_tapbuf_size16_3_sram[4]:7 *C 12.420 89.035 +*N mux_tree_tapbuf_size16_3_sram[4]:8 *C 12.420 85.737 +*N mux_tree_tapbuf_size16_3_sram[4]:9 *C 12.428 85.680 +*N mux_tree_tapbuf_size16_3_sram[4]:10 *C 13.793 85.680 +*N mux_tree_tapbuf_size16_3_sram[4]:11 *C 13.800 85.680 +*N mux_tree_tapbuf_size16_3_sram[4]:12 *C 13.845 85.680 +*N mux_tree_tapbuf_size16_3_sram[4]:13 *C 14.527 85.680 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q 1e-06 +1 mux_left_track_5\/mux_l5_in_0_:S 1e-06 +2 mem_left_track_5\/FTB_12__63:A 1e-06 +3 mux_tree_tapbuf_size16_3_sram[4]:3 3.311941e-05 +4 mux_tree_tapbuf_size16_3_sram[4]:4 0.0001732923 +5 mux_tree_tapbuf_size16_3_sram[4]:5 0.0003071953 +6 mux_tree_tapbuf_size16_3_sram[4]:6 0.0003071953 +7 mux_tree_tapbuf_size16_3_sram[4]:7 0.000205295 +8 mux_tree_tapbuf_size16_3_sram[4]:8 0.000205295 +9 mux_tree_tapbuf_size16_3_sram[4]:9 0.0001112445 +10 mux_tree_tapbuf_size16_3_sram[4]:10 0.0001112445 +11 mux_tree_tapbuf_size16_3_sram[4]:11 0.0002081153 +12 mux_tree_tapbuf_size16_3_sram[4]:12 6.070431e-05 +13 mux_tree_tapbuf_size16_3_sram[4]:13 6.070431e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:Q mux_tree_tapbuf_size16_3_sram[4]:13 0.152 +1 mux_tree_tapbuf_size16_3_sram[4]:3 mem_left_track_5\/FTB_12__63:A 0.152 +2 mux_tree_tapbuf_size16_3_sram[4]:4 mux_tree_tapbuf_size16_3_sram[4]:3 0.0045 +3 mux_tree_tapbuf_size16_3_sram[4]:12 mux_tree_tapbuf_size16_3_sram[4]:11 0.0045 +4 mux_tree_tapbuf_size16_3_sram[4]:11 mux_tree_tapbuf_size16_3_sram[4]:10 0.00341 +5 mux_tree_tapbuf_size16_3_sram[4]:11 mux_tree_tapbuf_size16_3_sram[4]:4 0.002388393 +6 mux_tree_tapbuf_size16_3_sram[4]:13 mux_tree_tapbuf_size16_3_sram[4]:12 0.000609375 +7 mux_tree_tapbuf_size16_3_sram[4]:10 mux_tree_tapbuf_size16_3_sram[4]:9 0.00021385 +8 mux_tree_tapbuf_size16_3_sram[4]:8 mux_tree_tapbuf_size16_3_sram[4]:7 0.002944197 +9 mux_tree_tapbuf_size16_3_sram[4]:9 mux_tree_tapbuf_size16_3_sram[4]:8 0.00341 +10 mux_tree_tapbuf_size16_3_sram[4]:6 mux_tree_tapbuf_size16_3_sram[4]:5 0.003122768 +11 mux_tree_tapbuf_size16_3_sram[4]:7 mux_tree_tapbuf_size16_3_sram[4]:6 0.0045 +12 mux_tree_tapbuf_size16_3_sram[4]:5 mux_left_track_5\/mux_l5_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[1] 0.002674905 //LENGTH 19.743 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 72.525 107.440 +*I mux_top_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 77.620 107.100 +*I mux_top_track_32\/mux_l2_in_1_:S I *L 0.00357 *C 82.220 105.400 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 83.895 109.820 +*N mux_tree_tapbuf_size7_0_sram[1]:4 *C 83.858 109.820 +*N mux_tree_tapbuf_size7_0_sram[1]:5 *C 81.005 109.820 +*N mux_tree_tapbuf_size7_0_sram[1]:6 *C 80.960 109.775 +*N mux_tree_tapbuf_size7_0_sram[1]:7 *C 82.183 105.400 +*N mux_tree_tapbuf_size7_0_sram[1]:8 *C 81.005 105.400 +*N mux_tree_tapbuf_size7_0_sram[1]:9 *C 80.960 105.445 +*N mux_tree_tapbuf_size7_0_sram[1]:10 *C 80.960 108.120 +*N mux_tree_tapbuf_size7_0_sram[1]:11 *C 80.915 108.120 +*N mux_tree_tapbuf_size7_0_sram[1]:12 *C 77.740 108.120 +*N mux_tree_tapbuf_size7_0_sram[1]:13 *C 77.680 107.100 +*N mux_tree_tapbuf_size7_0_sram[1]:14 *C 77.718 107.123 +*N mux_tree_tapbuf_size7_0_sram[1]:15 *C 72.680 107.100 +*N mux_tree_tapbuf_size7_0_sram[1]:16 *C 72.525 107.440 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_32\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_0_sram[1]:4 0.0002108779 +5 mux_tree_tapbuf_size7_0_sram[1]:5 0.0002108779 +6 mux_tree_tapbuf_size7_0_sram[1]:6 0.0001176223 +7 mux_tree_tapbuf_size7_0_sram[1]:7 0.0001177179 +8 mux_tree_tapbuf_size7_0_sram[1]:8 0.0001177179 +9 mux_tree_tapbuf_size7_0_sram[1]:9 0.0001902351 +10 mux_tree_tapbuf_size7_0_sram[1]:10 0.0003392909 +11 mux_tree_tapbuf_size7_0_sram[1]:11 0.0002380932 +12 mux_tree_tapbuf_size7_0_sram[1]:12 0.0002950878 +13 mux_tree_tapbuf_size7_0_sram[1]:13 2.278956e-05 +14 mux_tree_tapbuf_size7_0_sram[1]:14 0.0004020302 +15 mux_tree_tapbuf_size7_0_sram[1]:15 0.0003497025 +16 mux_tree_tapbuf_size7_0_sram[1]:16 5.886146e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_0_sram[1]:14 mux_top_track_32\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:13 3.348214e-05 +3 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:12 0.0008906252 +4 mux_tree_tapbuf_size7_0_sram[1]:11 mux_tree_tapbuf_size7_0_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:9 0.002388393 +6 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:6 0.001477679 +7 mux_tree_tapbuf_size7_0_sram[1]:5 mux_tree_tapbuf_size7_0_sram[1]:4 0.002546875 +8 mux_tree_tapbuf_size7_0_sram[1]:6 mux_tree_tapbuf_size7_0_sram[1]:5 0.0045 +9 mux_tree_tapbuf_size7_0_sram[1]:4 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:15 0.0003035715 +11 mux_tree_tapbuf_size7_0_sram[1]:7 mux_top_track_32\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size7_0_sram[1]:8 mux_tree_tapbuf_size7_0_sram[1]:7 0.001051339 +13 mux_tree_tapbuf_size7_0_sram[1]:9 mux_tree_tapbuf_size7_0_sram[1]:8 0.0045 +14 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:14 0.004497768 +15 mux_tree_tapbuf_size7_0_sram[1]:12 mux_tree_tapbuf_size7_0_sram[1]:11 0.002834822 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[1] 0.002754432 //LENGTH 21.225 LUMPCC 0.0001909678 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 19.065 74.460 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 8.915 69.700 +*I mux_left_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 19.420 69.360 +*I mux_left_track_33\/mux_l2_in_1_:S I *L 0.00357 *C 15.740 72.375 +*N mux_tree_tapbuf_size7_3_sram[1]:4 *C 15.740 72.375 +*N mux_tree_tapbuf_size7_3_sram[1]:5 *C 19.420 69.360 +*N mux_tree_tapbuf_size7_3_sram[1]:6 *C 19.320 69.700 +*N mux_tree_tapbuf_size7_3_sram[1]:7 *C 8.953 69.700 +*N mux_tree_tapbuf_size7_3_sram[1]:8 *C 15.640 69.700 +*N mux_tree_tapbuf_size7_3_sram[1]:9 *C 15.640 69.745 +*N mux_tree_tapbuf_size7_3_sram[1]:10 *C 15.640 72.715 +*N mux_tree_tapbuf_size7_3_sram[1]:11 *C 15.740 72.760 +*N mux_tree_tapbuf_size7_3_sram[1]:12 *C 17.435 72.760 +*N mux_tree_tapbuf_size7_3_sram[1]:13 *C 17.480 72.805 +*N mux_tree_tapbuf_size7_3_sram[1]:14 *C 17.480 74.415 +*N mux_tree_tapbuf_size7_3_sram[1]:15 *C 17.525 74.460 +*N mux_tree_tapbuf_size7_3_sram[1]:16 *C 19.027 74.460 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_33\/mux_l2_in_0_:S 1e-06 +3 mux_left_track_33\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_3_sram[1]:4 5.813519e-05 +5 mux_tree_tapbuf_size7_3_sram[1]:5 6.334625e-05 +6 mux_tree_tapbuf_size7_3_sram[1]:6 0.0002523809 +7 mux_tree_tapbuf_size7_3_sram[1]:7 0.000435817 +8 mux_tree_tapbuf_size7_3_sram[1]:8 0.0006955476 +9 mux_tree_tapbuf_size7_3_sram[1]:9 0.000180645 +10 mux_tree_tapbuf_size7_3_sram[1]:10 0.000180645 +11 mux_tree_tapbuf_size7_3_sram[1]:11 0.0001721051 +12 mux_tree_tapbuf_size7_3_sram[1]:12 0.0001406982 +13 mux_tree_tapbuf_size7_3_sram[1]:13 9.111015e-05 +14 mux_tree_tapbuf_size7_3_sram[1]:14 9.111015e-05 +15 mux_tree_tapbuf_size7_3_sram[1]:15 9.89619e-05 +16 mux_tree_tapbuf_size7_3_sram[1]:16 9.89619e-05 +17 mux_tree_tapbuf_size7_3_sram[1]:16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.175703e-05 +18 mux_tree_tapbuf_size7_3_sram[1]:15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.175703e-05 +19 mux_tree_tapbuf_size7_3_sram[1]:14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.604319e-05 +20 mux_tree_tapbuf_size7_3_sram[1]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.578767e-06 +21 mux_tree_tapbuf_size7_3_sram[1]:13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.604319e-05 +22 mux_tree_tapbuf_size7_3_sram[1]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.104917e-06 +23 mux_tree_tapbuf_size7_3_sram[1]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.578767e-06 +24 mux_tree_tapbuf_size7_3_sram[1]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.104917e-06 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_3_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_3_sram[1]:16 mux_tree_tapbuf_size7_3_sram[1]:15 0.001341518 +2 mux_tree_tapbuf_size7_3_sram[1]:15 mux_tree_tapbuf_size7_3_sram[1]:14 0.0045 +3 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:13 0.0014375 +4 mux_tree_tapbuf_size7_3_sram[1]:12 mux_tree_tapbuf_size7_3_sram[1]:11 0.001513393 +5 mux_tree_tapbuf_size7_3_sram[1]:13 mux_tree_tapbuf_size7_3_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size7_3_sram[1]:7 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size7_3_sram[1]:4 mux_left_track_33\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size7_3_sram[1]:8 mux_tree_tapbuf_size7_3_sram[1]:7 0.005970982 +9 mux_tree_tapbuf_size7_3_sram[1]:8 mux_tree_tapbuf_size7_3_sram[1]:6 0.003285714 +10 mux_tree_tapbuf_size7_3_sram[1]:9 mux_tree_tapbuf_size7_3_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size7_3_sram[1]:11 mux_tree_tapbuf_size7_3_sram[1]:10 0.0045 +12 mux_tree_tapbuf_size7_3_sram[1]:11 mux_tree_tapbuf_size7_3_sram[1]:4 0.00034375 +13 mux_tree_tapbuf_size7_3_sram[1]:10 mux_tree_tapbuf_size7_3_sram[1]:9 0.002651786 +14 mux_tree_tapbuf_size7_3_sram[1]:5 mux_left_track_33\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size7_3_sram[1]:6 mux_tree_tapbuf_size7_3_sram[1]:5 0.0003035715 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002135307 //LENGTH 15.625 LUMPCC 0.0005787917 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_2_:X O *L 0 *C 77.105 91.460 +*I mux_top_track_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 77.280 105.060 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 77.318 105.060 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 77.695 105.060 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 77.740 105.015 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 77.740 91.505 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 77.695 91.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 77.142 91.460 + +*CAP +0 mux_top_track_0\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.439007e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.439007e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0006291055 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0006291055 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.37619e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.37619e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001531613 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001531613 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 1.627288e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001199617 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001199617 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 1.627288e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003370536 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0120625 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001026096 //LENGTH 7.790 LUMPCC 0.000347952 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_3_:X O *L 0 *C 49.395 96.560 +*I mux_top_track_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 50.775 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 50.738 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 49.725 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 49.680 102.295 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 49.680 96.605 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 49.680 96.560 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 49.395 96.560 + +*CAP +0 mux_top_track_2\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.337127e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.337127e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002325347 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002325347 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.230547e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.202637e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 top_left_grid_pin_39_[0]:7 7.357801e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 top_left_grid_pin_39_[0]:6 7.357801e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size12_1_sram[2]:13 1.379594e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size12_1_sram[2]:12 1.379594e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size12_1_sram[2]:14 2.639926e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size12_1_sram[2]:15 1.007972e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size12_1_sram[2]:11 2.639926e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size12_1_sram[2]:14 1.007972e-05 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.012306e-05 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.012306e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_3_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_2\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0009040179 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.005080357 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001329571 //LENGTH 9.755 LUMPCC 0.0002820197 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_2_:X O *L 0 *C 99.185 91.800 +*I mux_right_track_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 99.920 99.620 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 99.883 99.620 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 98.945 99.620 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 98.900 99.575 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 98.900 91.845 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 98.900 91.800 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 99.185 91.800 + +*CAP +0 mux_right_track_0\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001081996 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001081996 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003617656 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003617656 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.354823e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 5.207249e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size12_2_sram[1]:8 0.0001271362 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size12_2_sram[1]:14 1.387364e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size12_2_sram[1]:7 0.0001271362 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size12_2_sram[1]:11 1.387364e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_0\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0008370536 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.006901786 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0008253449 //LENGTH 6.025 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_2_:X O *L 0 *C 113.445 89.080 +*I mux_right_track_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 116.840 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 116.803 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 115.965 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 115.920 90.735 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 115.920 89.125 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 115.875 89.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 113.483 89.080 + +*CAP +0 mux_right_track_2\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.049877e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.049877e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001167455 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001167455 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002144282 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0002144282 + +*RES +0 mux_right_track_2\/mux_l2_in_2_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002136161 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0014375 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0007477679 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_2\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008869007 //LENGTH 6.540 LUMPCC 0.0002055791 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_1_:X O *L 0 *C 84.005 22.780 +*I mux_bottom_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 87.575 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 87.538 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 86.525 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 86.480 20.785 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 86.480 22.735 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 86.435 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 84.043 22.780 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.497703e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.497703e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001264273 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001264273 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001182565 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001182565 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 bottom_left_grid_pin_38_[0]:4 0.0001027896 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 bottom_left_grid_pin_38_[0]:6 0.0001027896 + +*RES +0 mux_bottom_track_1\/mux_l2_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000904018 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001741071 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002136161 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007288889 //LENGTH 5.570 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_0_:X O *L 0 *C 66.415 22.780 +*I mux_bottom_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 64.305 20.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 64.343 20.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 66.195 20.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 66.240 20.105 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 66.240 22.735 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 66.240 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 66.415 22.780 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000146281 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000146281 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001645614 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001645614 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.286802e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.233612e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001654018 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001614469 //LENGTH 11.110 LUMPCC 0.0003181624 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_2_:X O *L 0 *C 77.455 85.680 +*I mux_left_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 67.985 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 67.948 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 67.620 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 67.620 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 77.418 85.680 + +*CAP +0 mux_left_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.231078e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.307838e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0006348424 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0006140749 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size12_6_sram[1]:21 2.043825e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size12_6_sram[1]:21 4.570468e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_6_sram[1]:22 2.832717e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[1]:20 7.888919e-06 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_6_sram[1]:22 4.570468e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.504934e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.504934e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.008747769 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002924107 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001471617 //LENGTH 9.995 LUMPCC 0.0001302875 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_3_:X O *L 0 *C 65.495 96.900 +*I mux_left_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 56.410 97.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 56.448 97.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 62.560 97.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 62.560 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 65.458 96.900 + +*CAP +0 mux_left_track_3\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004410655 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004668072 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002285994 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002028577 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size12_7_sram[0]:16 6.514376e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size12_7_sram[0]:17 6.514376e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_3_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_3\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002587054 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.00545759 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0] 0.003089701 //LENGTH 19.390 LUMPCC 0.001608558 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_0_:X O *L 0 *C 43.875 96.220 +*I mux_left_track_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 29.805 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 29.768 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 29.025 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 28.980 96.265 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 28.980 97.183 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 28.988 97.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 39.093 97.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 39.100 97.183 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 39.100 96.265 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 39.145 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 43.837 96.220 + +*CAP +0 mux_left_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.418772e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.418772e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 7.78352e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 7.78352e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002644017 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002644017 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 7.203695e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 7.203695e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0002511101 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0002511101 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_right_in[12]:10 0.0005825261 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_right_in[12]:11 0.0005825261 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_7_sram[2]:9 6.939477e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_7_sram[2]:14 7.12544e-05 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size12_7_sram[2]:16 6.708596e-06 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size12_7_sram[2]:14 6.939477e-05 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size12_7_sram[2]:15 7.12544e-05 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_tree_tapbuf_size12_7_sram[2]:5 1.414601e-05 +20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_tree_tapbuf_size12_7_sram[2]:18 1.532935e-05 +21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_tree_tapbuf_size12_7_sram[2]:19 4.491979e-05 +22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size12_7_sram[2]:17 6.708596e-06 +23 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_tree_tapbuf_size12_7_sram[2]:4 1.414601e-05 +24 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_tree_tapbuf_size12_7_sram[2]:6 4.491979e-05 +25 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_tree_tapbuf_size12_7_sram[2]:19 1.532935e-05 + +*RES +0 mux_left_track_3\/mux_l3_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_3\/mux_l4_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0006629464 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0008191965 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001583117 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0045 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0008191963 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.004189732 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0] 0.001559596 //LENGTH 12.670 LUMPCC 0.0005191022 DR + +*CONN +*I mux_right_track_4\/mux_l4_in_1_:X O *L 0 *C 121.265 69.700 +*I mux_right_track_4\/mux_l5_in_0_:A0 I *L 0.001631 *C 127.565 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 *C 127.528 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 *C 124.705 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 *C 124.660 75.095 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 *C 124.660 69.745 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 *C 124.615 69.700 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 *C 121.303 69.700 + +*CAP +0 mux_right_track_4\/mux_l4_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l5_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.0001380087 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0001380087 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.0002489655 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0002489655 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 0.0001322729 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 0.0001322729 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 chanx_left_in[9]:21 0.0001397925 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 chanx_left_in[9]:16 0.0001397925 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 chanx_left_in[9]:14 3.327397e-07 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 chanx_left_in[9]:15 3.327397e-07 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 chanx_left_in[14]:15 6.554305e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 chanx_left_in[14]:16 6.554305e-05 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 5.388279e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 5.388279e-05 + +*RES +0 mux_right_track_4\/mux_l4_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 0.002957589 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.004776785 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.00252009 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0045 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_right_track_4\/mux_l5_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0] 0.0007850975 //LENGTH 6.740 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_2_:X O *L 0 *C 36.625 11.900 +*I mux_bottom_track_5\/mux_l4_in_1_:A1 I *L 0.00198 *C 40.120 14.620 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 40.020 14.620 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 40.020 14.575 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 40.020 11.945 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 39.975 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 36.663 11.900 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 3.441048e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001657723 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0001657723 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002085712 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0002085712 + +*RES +0 mux_bottom_track_5\/mux_l3_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_bottom_track_5\/mux_l4_in_1_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.002348214 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.002957589 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001158555 //LENGTH 9.765 LUMPCC 0.000206528 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_6_:X O *L 0 *C 30.645 38.760 +*I mux_bottom_track_5\/mux_l3_in_3_:A1 I *L 0.00198 *C 35.060 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 35.023 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 32.245 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 32.200 34.385 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 32.200 38.715 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 32.155 38.760 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 30.683 38.760 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_6_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_3_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001803515 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001803515 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000217434 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000217434 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.722777e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.722777e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size16_2_sram[1]:27 1.805338e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size16_2_sram[1]:28 2.820378e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size16_2_sram[1]:18 8.030122e-06 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size16_2_sram[1]:20 1.970253e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size16_2_sram[1]:23 2.927419e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size16_2_sram[1]:24 1.805338e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size16_2_sram[1]:27 2.820378e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:19 8.030122e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:22 2.927419e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:23 1.970253e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_6_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_5\/mux_l3_in_3_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.002479911 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.003866071 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001948142 //LENGTH 14.930 LUMPCC 0.000236876 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_3_:X O *L 0 *C 43.875 90.440 +*I mux_left_track_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.950 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 32.988 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 34.455 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 34.500 87.765 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 34.500 90.383 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 34.508 90.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 35.873 90.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 35.880 90.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 35.925 90.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 43.837 90.440 + +*CAP +0 mux_left_track_5\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000122812 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000122812 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001667769 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001667769 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.068318e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.068318e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.715245e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0004657846 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0004657846 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size12_7_sram[0]:37 4.050612e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size12_7_sram[0]:38 4.050612e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size12_7_sram[0]:40 1.97894e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size12_7_sram[0]:26 1.97894e-05 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size16_0_sram[2]:16 5.814247e-05 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size16_0_sram[2]:15 5.814247e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_3_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_5\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001310268 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002337054 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00021385 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.007064732 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001744726 //LENGTH 11.675 LUMPCC 0.0003706024 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_1_:X O *L 0 *C 66.875 49.640 +*I mux_top_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 55.490 49.640 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 55.528 49.640 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.838 49.640 + +*CAP +0 mux_top_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0006860619 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006860619 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:27 0.0001853012 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:28 0.0001853012 + +*RES +0 mux_top_track_16\/mux_l1_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.01009821 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.006830086 //LENGTH 49.880 LUMPCC 0.002113753 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 61.005 109.480 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 62.005 69.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 60.010 106.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.320 66.640 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.968 69.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 60.765 69.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 60.720 68.975 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 60.720 66.698 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 60.720 66.640 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 60.720 66.648 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 60.720 106.753 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 60.718 106.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 60.720 106.818 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 60.720 109.435 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 60.720 109.480 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:15 *C 61.005 109.480 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.99247e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.920057e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.39249e-05 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.39249e-05 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001495729 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001495729 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.920057e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.001670718 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.001670718 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 8.99247e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001964167 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0001964167 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:14 5.752723e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:15 5.728998e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[8]:19 0.0007377357 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chany_bottom_in[8]:18 0.0007377357 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[10]:45 0.0003191408 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chany_bottom_in[10]:44 0.0003191408 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:15 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001073661 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002033482 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.69697e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.00341 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.00341 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001039141 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.006283116 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.00341 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0045 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.002337054 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.0001548913 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0002274678 //LENGTH 1.610 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_0_:X O *L 0 *C 115.285 64.600 +*I mux_right_track_8\/mux_l4_in_0_:A1 I *L 0.001811 *C 116.605 64.600 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 116.568 64.600 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 115.323 64.600 + +*CAP +0 mux_right_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001127339 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001127339 + +*RES +0 mux_right_track_8\/mux_l3_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001111607 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_8\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002070808 //LENGTH 15.275 LUMPCC 0.0005409694 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_2_:X O *L 0 *C 79.405 53.040 +*I mux_right_track_16\/mux_l3_in_1_:A1 I *L 0.00198 *C 87.960 47.260 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 87.960 47.260 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 87.860 47.600 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 82.385 47.600 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 82.340 47.645 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 82.340 52.995 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 82.295 53.040 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 79.443 53.040 + +*CAP +0 mux_right_track_16\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.706448e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000218905 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001908332 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003155639 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003155639 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002149543 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002149543 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:21 8.185122e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_1_sram[0]:22 8.185122e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:5 8.642014e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_4_sram[2]:6 6.791382e-05 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_4_sram[2]:4 6.791382e-05 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_4_sram[2]:6 8.642014e-05 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.42995e-05 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.42995e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_2_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_16\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.004888393 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.004776786 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.002546875 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET optlc_net_151 0.01558536 //LENGTH 110.380 LUMPCC 0.003181167 DR + +*CONN +*I optlc_146:HI O *L 0 *C 101.660 91.800 +*I mux_right_track_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 99.650 96.900 +*I mux_right_track_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 116.555 88.060 +*I mux_right_track_4\/mux_l2_in_7_:A0 I *L 0.001631 *C 121.730 80.580 +*I mux_right_track_24\/mux_l2_in_3_:A0 I *L 0.001631 *C 97.235 75.140 +*I mux_right_track_32\/mux_l1_in_3_:A0 I *L 0.001631 *C 86.195 75.140 +*I mux_top_track_32\/mux_l1_in_3_:A0 I *L 0.001631 *C 87.230 80.920 +*I mux_top_track_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 78.950 97.240 +*N optlc_net_151:8 *C 78.987 97.240 +*N optlc_net_151:9 *C 86.020 97.240 +*N optlc_net_151:10 *C 86.020 96.900 +*N optlc_net_151:11 *C 87.355 96.900 +*N optlc_net_151:12 *C 87.400 96.855 +*N optlc_net_151:13 *C 87.230 80.920 +*N optlc_net_151:14 *C 87.400 80.920 +*N optlc_net_151:15 *C 87.400 80.920 +*N optlc_net_151:16 *C 87.400 75.525 +*N optlc_net_151:17 *C 87.400 75.480 +*N optlc_net_151:18 *C 86.233 75.140 +*N optlc_net_151:19 *C 87.400 75.140 +*N optlc_net_151:20 *C 97.235 75.140 +*N optlc_net_151:21 *C 98.395 75.140 +*N optlc_net_151:22 *C 98.440 75.185 +*N optlc_net_151:23 *C 98.440 76.103 +*N optlc_net_151:24 *C 98.448 76.160 +*N optlc_net_151:25 *C 114.532 76.160 +*N optlc_net_151:26 *C 114.540 76.218 +*N optlc_net_151:27 *C 114.540 80.580 +*N optlc_net_151:28 *C 121.693 80.580 +*N optlc_net_151:29 *C 115.045 80.580 +*N optlc_net_151:30 *C 115.000 80.625 +*N optlc_net_151:31 *C 116.518 88.060 +*N optlc_net_151:32 *C 115.045 88.060 +*N optlc_net_151:33 *C 115.000 88.015 +*N optlc_net_151:34 *C 114.540 88.060 +*N optlc_net_151:35 *C 114.540 91.755 +*N optlc_net_151:36 *C 114.495 91.800 +*N optlc_net_151:37 *C 99.688 96.900 +*N optlc_net_151:38 *C 102.535 96.900 +*N optlc_net_151:39 *C 102.580 96.855 +*N optlc_net_151:40 *C 102.580 91.845 +*N optlc_net_151:41 *C 102.580 91.800 +*N optlc_net_151:42 *C 101.698 91.800 + +*CAP +0 optlc_146:HI 1e-06 +1 mux_right_track_0\/mux_l2_in_3_:A0 1e-06 +2 mux_right_track_2\/mux_l2_in_3_:A0 1e-06 +3 mux_right_track_4\/mux_l2_in_7_:A0 1e-06 +4 mux_right_track_24\/mux_l2_in_3_:A0 1e-06 +5 mux_right_track_32\/mux_l1_in_3_:A0 1e-06 +6 mux_top_track_32\/mux_l1_in_3_:A0 1e-06 +7 mux_top_track_0\/mux_l2_in_3_:A0 1e-06 +8 optlc_net_151:8 0.0004424567 +9 optlc_net_151:9 0.0004718789 +10 optlc_net_151:10 0.0001430348 +11 optlc_net_151:11 0.0001136126 +12 optlc_net_151:12 0.0009245527 +13 optlc_net_151:13 6.850423e-05 +14 optlc_net_151:14 6.759928e-05 +15 optlc_net_151:15 0.001288604 +16 optlc_net_151:16 0.0003315496 +17 optlc_net_151:17 6.524455e-05 +18 optlc_net_151:18 8.36531e-05 +19 optlc_net_151:19 0.0006285988 +20 optlc_net_151:20 0.0006353513 +21 optlc_net_151:21 8.525336e-05 +22 optlc_net_151:22 8.344871e-05 +23 optlc_net_151:23 8.344871e-05 +24 optlc_net_151:24 0.0006533888 +25 optlc_net_151:25 0.0006533888 +26 optlc_net_151:26 0.0002003301 +27 optlc_net_151:27 0.0002340025 +28 optlc_net_151:28 0.0003944406 +29 optlc_net_151:29 0.0003944406 +30 optlc_net_151:30 0.0004342913 +31 optlc_net_151:31 0.0001672935 +32 optlc_net_151:32 0.0001672935 +33 optlc_net_151:33 0.0004374362 +34 optlc_net_151:34 0.0002655777 +35 optlc_net_151:35 0.0002287605 +36 optlc_net_151:36 0.000723175 +37 optlc_net_151:37 0.0002140462 +38 optlc_net_151:38 0.0002140462 +39 optlc_net_151:39 0.0003036078 +40 optlc_net_151:40 0.0003036078 +41 optlc_net_151:41 0.0008230321 +42 optlc_net_151:42 6.724062e-05 +43 optlc_net_151:25 chany_bottom_in[14]:9 0.000287951 +44 optlc_net_151:24 chany_bottom_in[14]:38 0.000287951 +45 optlc_net_151:20 chany_bottom_in[14]:9 6.373401e-06 +46 optlc_net_151:19 chany_bottom_in[14]:38 6.373401e-06 +47 optlc_net_151:26 chanx_left_in[5]:22 6.314344e-09 +48 optlc_net_151:25 chanx_left_in[5]:24 0.0006950388 +49 optlc_net_151:24 chanx_left_in[5]:25 0.0006950388 +50 optlc_net_151:27 chanx_left_in[5]:23 6.314344e-09 +51 optlc_net_151:26 mux_tree_tapbuf_size16_1_sram[1]:37 1.786923e-05 +52 optlc_net_151:26 mux_tree_tapbuf_size16_1_sram[1]:41 5.328571e-05 +53 optlc_net_151:26 mux_tree_tapbuf_size16_1_sram[1]:42 2.641416e-05 +54 optlc_net_151:21 mux_tree_tapbuf_size16_1_sram[1]:32 1.617059e-07 +55 optlc_net_151:33 mux_tree_tapbuf_size16_1_sram[1]:11 2.59411e-05 +56 optlc_net_151:20 mux_tree_tapbuf_size16_1_sram[1]:26 0.000121262 +57 optlc_net_151:20 mux_tree_tapbuf_size16_1_sram[1]:27 1.617059e-07 +58 optlc_net_151:29 mux_tree_tapbuf_size16_1_sram[1]:43 3.832351e-05 +59 optlc_net_151:29 mux_tree_tapbuf_size16_1_sram[1]:44 7.590032e-06 +60 optlc_net_151:30 mux_tree_tapbuf_size16_1_sram[1]:42 2.59411e-05 +61 optlc_net_151:28 mux_tree_tapbuf_size16_1_sram[1]:44 3.832351e-05 +62 optlc_net_151:28 mux_tree_tapbuf_size16_1_sram[1]:45 7.590032e-06 +63 optlc_net_151:18 mux_tree_tapbuf_size16_1_sram[1]:23 1.819955e-05 +64 optlc_net_151:18 mux_tree_tapbuf_size16_1_sram[1]:25 2.714385e-06 +65 optlc_net_151:19 mux_tree_tapbuf_size16_1_sram[1]:24 1.819955e-05 +66 optlc_net_151:19 mux_tree_tapbuf_size16_1_sram[1]:25 0.000121262 +67 optlc_net_151:19 mux_tree_tapbuf_size16_1_sram[1]:26 2.714385e-06 +68 optlc_net_151:27 mux_tree_tapbuf_size16_1_sram[1]:11 2.641416e-05 +69 optlc_net_151:27 mux_tree_tapbuf_size16_1_sram[1]:38 1.786923e-05 +70 optlc_net_151:27 mux_tree_tapbuf_size16_1_sram[1]:42 5.328571e-05 +71 optlc_net_151:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001310286 +72 optlc_net_151:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001310286 +73 optlc_net_151:36 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001512258 +74 optlc_net_151:35 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 7.198393e-06 +75 optlc_net_151:41 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0001512258 +76 optlc_net_151:34 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 7.198393e-06 + +*RES +0 optlc_146:HI optlc_net_151:42 0.152 +1 optlc_net_151:17 optlc_net_151:16 0.0045 +2 optlc_net_151:16 optlc_net_151:15 0.004816965 +3 optlc_net_151:26 optlc_net_151:25 0.00341 +4 optlc_net_151:25 optlc_net_151:24 0.002519983 +5 optlc_net_151:23 optlc_net_151:22 0.0008191965 +6 optlc_net_151:24 optlc_net_151:23 0.00341 +7 optlc_net_151:21 optlc_net_151:20 0.001035714 +8 optlc_net_151:22 optlc_net_151:21 0.0045 +9 optlc_net_151:36 optlc_net_151:35 0.0045 +10 optlc_net_151:35 optlc_net_151:34 0.003299107 +11 optlc_net_151:11 optlc_net_151:10 0.001191964 +12 optlc_net_151:12 optlc_net_151:11 0.0045 +13 optlc_net_151:8 mux_top_track_0\/mux_l2_in_3_:A0 0.152 +14 optlc_net_151:32 optlc_net_151:31 0.001314732 +15 optlc_net_151:33 optlc_net_151:32 0.0045 +16 optlc_net_151:33 optlc_net_151:30 0.006598215 +17 optlc_net_151:31 mux_right_track_2\/mux_l2_in_3_:A0 0.152 +18 optlc_net_151:41 optlc_net_151:40 0.0045 +19 optlc_net_151:41 optlc_net_151:36 0.01063839 +20 optlc_net_151:40 optlc_net_151:39 0.004473215 +21 optlc_net_151:38 optlc_net_151:37 0.002542411 +22 optlc_net_151:39 optlc_net_151:38 0.0045 +23 optlc_net_151:37 mux_right_track_0\/mux_l2_in_3_:A0 0.152 +24 optlc_net_151:20 mux_right_track_24\/mux_l2_in_3_:A0 0.152 +25 optlc_net_151:20 optlc_net_151:19 0.008781251 +26 optlc_net_151:42 optlc_net_151:41 0.0007879465 +27 optlc_net_151:29 optlc_net_151:28 0.005935268 +28 optlc_net_151:30 optlc_net_151:29 0.0045 +29 optlc_net_151:30 optlc_net_151:27 0.0004107143 +30 optlc_net_151:28 mux_right_track_4\/mux_l2_in_7_:A0 0.152 +31 optlc_net_151:18 mux_right_track_32\/mux_l1_in_3_:A0 0.152 +32 optlc_net_151:14 optlc_net_151:13 9.239131e-05 +33 optlc_net_151:15 optlc_net_151:14 0.0045 +34 optlc_net_151:15 optlc_net_151:12 0.01422768 +35 optlc_net_151:13 mux_top_track_32\/mux_l1_in_3_:A0 0.152 +36 optlc_net_151:9 optlc_net_151:8 0.006279019 +37 optlc_net_151:10 optlc_net_151:9 0.0003035715 +38 optlc_net_151:19 optlc_net_151:18 0.001042411 +39 optlc_net_151:19 optlc_net_151:17 0.0003035714 +40 optlc_net_151:27 optlc_net_151:26 0.003895089 +41 optlc_net_151:34 optlc_net_151:33 0.0004107143 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002405778 //LENGTH 18.530 LUMPCC 0.0006515271 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 67.335 66.640 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 61.085 58.140 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 61.047 58.140 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.305 58.140 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 60.230 58.170 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 60.215 58.480 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 59.800 58.480 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 59.800 66.595 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 59.845 66.640 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 67.297 66.640 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.311726e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.311726e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.092525e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.450047e-05 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004600614 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004264862 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003020215 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003020215 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[18]:24 2.972276e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[18]:28 1.264118e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[18]:29 7.545787e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[18]:25 2.972276e-05 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[18]:29 1.264118e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[18]:30 7.545787e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_2_sram[0]:28 2.129346e-05 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size10_2_sram[0]:30 5.462951e-05 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_2_sram[0]:13 5.462951e-05 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size10_2_sram[0]:29 2.129346e-05 +20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size10_2_sram[1]:18 0.0001320187 +21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size10_2_sram[1]:17 0.0001320187 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.006654018 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.007245535 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006629465 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003705357 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00019375 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000666267 //LENGTH 3.620 LUMPCC 0.0001533483 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_1_:X O *L 0 *C 84.925 105.060 +*I mux_top_track_32\/mux_l3_in_0_:A0 I *L 0.001631 *C 84.815 107.780 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 84.815 107.780 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 84.640 107.780 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 84.640 107.735 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 84.640 105.105 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 84.640 105.060 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 84.925 105.060 + +*CAP +0 mux_top_track_32\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.204389e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.62382e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001339792 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001339792 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.72355e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.744268e-05 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[2]:13 7.667414e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[2]:24 7.667414e-05 + +*RES +0 mux_top_track_32\/mux_l2_in_1_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002393537 //LENGTH 21.060 LUMPCC 0.0005977013 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_0_:X O *L 0 *C 23.635 52.360 +*I mux_bottom_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 21.525 34.340 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 21.562 34.340 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 22.955 34.340 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 23.000 34.385 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 23.000 52.315 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 23.045 52.360 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 23.598 52.360 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.329982e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.329982e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0007908413 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0007908413 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.277689e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.277689e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:405 1.544112e-07 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:636 5.026386e-05 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:637 3.042354e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:646 1.864278e-05 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:647 9.72759e-06 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:406 1.544112e-07 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:633 5.026386e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:636 3.042354e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:640 1.864278e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:646 9.72759e-06 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_41_[0]:8 7.209128e-05 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_41_[0]:7 7.209128e-05 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_2_sram[0]:10 6.601988e-05 +21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:11 6.601988e-05 +22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:12 1.230159e-06 +23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:15 1.384311e-05 +24 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:20 1.934552e-06 +25 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:17 3.45195e-05 +26 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:15 1.230159e-06 +27 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:19 1.934552e-06 +28 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:21 1.384311e-05 +29 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:18 3.45195e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001243304 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01600893 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET ropt_net_200 0.001172703 //LENGTH 7.500 LUMPCC 0.0005730197 DR + +*CONN +*I FTB_7__6:X O *L 0 *C 78.200 4.760 +*I ropt_mt_inst_841:A I *L 0.001766 *C 81.420 6.800 +*N ropt_net_200:2 *C 81.420 6.800 +*N ropt_net_200:3 *C 81.420 6.460 +*N ropt_net_200:4 *C 78.705 6.460 +*N ropt_net_200:5 *C 78.690 6.430 +*N ropt_net_200:6 *C 78.705 6.120 +*N ropt_net_200:7 *C 79.120 6.120 +*N ropt_net_200:8 *C 79.120 4.805 +*N ropt_net_200:9 *C 79.075 4.760 +*N ropt_net_200:10 *C 78.237 4.760 + +*CAP +0 FTB_7__6:X 1e-06 +1 ropt_mt_inst_841:A 1e-06 +2 ropt_net_200:2 5.551519e-05 +3 ropt_net_200:3 0.0001128477 +4 ropt_net_200:4 8.555462e-05 +5 ropt_net_200:5 2.408734e-05 +6 ropt_net_200:6 2.677394e-05 +7 ropt_net_200:7 7.662752e-05 +8 ropt_net_200:8 7.394092e-05 +9 ropt_net_200:9 7.116824e-05 +10 ropt_net_200:10 7.116824e-05 +11 ropt_net_200:4 chany_top_in[9]:13 7.741282e-05 +12 ropt_net_200:3 chany_top_in[9]:12 7.741282e-05 +13 ropt_net_200:5 chany_top_in[12]:18 9.355807e-07 +14 ropt_net_200:9 chany_top_in[12]:16 3.21773e-05 +15 ropt_net_200:8 chany_top_in[12]:17 3.980342e-05 +16 ropt_net_200:10 chany_top_in[12]:15 3.21773e-05 +17 ropt_net_200:6 chany_top_in[12]:15 1.020631e-05 +18 ropt_net_200:6 chany_top_in[12]:17 9.355807e-07 +19 ropt_net_200:7 chany_top_in[12]:16 1.020631e-05 +20 ropt_net_200:7 chany_top_in[12]:18 3.980342e-05 +21 ropt_net_200:4 ropt_net_218:6 9.026083e-05 +22 ropt_net_200:5 ropt_net_218:4 1.426915e-05 +23 ropt_net_200:8 ropt_net_218:5 1.292593e-06 +24 ropt_net_200:3 ropt_net_218:7 9.026083e-05 +25 ropt_net_200:6 ropt_net_218:6 2.015182e-05 +26 ropt_net_200:6 ropt_net_218:5 1.426915e-05 +27 ropt_net_200:7 ropt_net_218:7 2.015182e-05 +28 ropt_net_200:7 ropt_net_218:4 1.292593e-06 + +*RES +0 FTB_7__6:X ropt_net_200:10 0.152 +1 ropt_net_200:2 ropt_mt_inst_841:A 0.152 +2 ropt_net_200:4 ropt_net_200:3 0.002424107 +3 ropt_net_200:5 ropt_net_200:4 0.0045 +4 ropt_net_200:9 ropt_net_200:8 0.0045 +5 ropt_net_200:8 ropt_net_200:7 0.001174107 +6 ropt_net_200:10 ropt_net_200:9 0.0007477679 +7 ropt_net_200:3 ropt_net_200:2 0.0003035715 +8 ropt_net_200:6 ropt_net_200:5 0.00019375 +9 ropt_net_200:7 ropt_net_200:6 0.0003705357 + +*END + +*D_NET ropt_net_241 0.0005972916 //LENGTH 4.420 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 131.100 66.980 +*I ropt_mt_inst_895:A I *L 0.001766 *C 134.780 66.640 +*N ropt_net_241:2 *C 134.780 66.640 +*N ropt_net_241:3 *C 134.780 66.980 +*N ropt_net_241:4 *C 131.138 66.980 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 ropt_mt_inst_895:A 1e-06 +2 ropt_net_241:2 5.933214e-05 +3 ropt_net_241:3 0.0002824515 +4 ropt_net_241:4 0.000253508 + +*RES +0 ropt_mt_inst_799:X ropt_net_241:4 0.152 +1 ropt_net_241:4 ropt_net_241:3 0.003252232 +2 ropt_net_241:2 ropt_mt_inst_895:A 0.152 +3 ropt_net_241:3 ropt_net_241:2 0.0003035715 + +*END + +*D_NET ropt_net_208 0.00170609 //LENGTH 10.825 LUMPCC 0.0007189877 DR + +*CONN +*I ropt_mt_inst_803:X O *L 0 *C 80.265 124.100 +*I ropt_mt_inst_847:A I *L 0.001766 *C 73.140 126.480 +*N ropt_net_208:2 *C 73.140 126.480 +*N ropt_net_208:3 *C 73.140 126.140 +*N ropt_net_208:4 *C 76.315 126.140 +*N ropt_net_208:5 *C 76.360 126.095 +*N ropt_net_208:6 *C 76.360 124.440 +*N ropt_net_208:7 *C 76.775 124.440 +*N ropt_net_208:8 *C 76.790 124.130 +*N ropt_net_208:9 *C 76.865 124.100 +*N ropt_net_208:10 *C 80.228 124.100 + +*CAP +0 ropt_mt_inst_803:X 1e-06 +1 ropt_mt_inst_847:A 1e-06 +2 ropt_net_208:2 6.690116e-05 +3 ropt_net_208:3 0.0001808724 +4 ropt_net_208:4 0.0001484693 +5 ropt_net_208:5 7.617291e-05 +6 ropt_net_208:6 9.29083e-05 +7 ropt_net_208:7 4.775851e-05 +8 ropt_net_208:8 3.102313e-05 +9 ropt_net_208:9 0.0001704983 +10 ropt_net_208:10 0.0001704983 +11 ropt_net_208:4 chany_bottom_in[18]:5 0.0001083233 +12 ropt_net_208:4 chany_bottom_in[18]:9 2.417946e-05 +13 ropt_net_208:3 chany_bottom_in[18]:6 0.0001083233 +14 ropt_net_208:3 chany_bottom_in[18]:10 2.417946e-05 +15 ropt_net_208:6 chany_bottom_in[18]:6 8.468472e-06 +16 ropt_net_208:7 chany_bottom_in[18]:5 8.468472e-06 +17 ropt_net_208:5 chany_top_in[11] 4.949281e-05 +18 ropt_net_208:8 chany_top_in[11]:11 4.448613e-06 +19 ropt_net_208:6 chany_top_in[11]:11 4.949281e-05 +20 ropt_net_208:7 chany_top_in[11] 4.448613e-06 +21 ropt_net_208:5 chany_top_out[2] 4.807346e-06 +22 ropt_net_208:9 chany_top_out[2]:4 4.563655e-05 +23 ropt_net_208:8 chany_top_out[2]:2 2.379589e-06 +24 ropt_net_208:10 chany_top_out[2]:3 4.563655e-05 +25 ropt_net_208:6 chany_top_out[2]:2 4.807346e-06 +26 ropt_net_208:6 chany_top_out[2]:4 7.603386e-06 +27 ropt_net_208:7 chany_top_out[2] 2.379589e-06 +28 ropt_net_208:7 chany_top_out[2]:3 7.603386e-06 +29 ropt_net_208:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001041544 +30 ropt_net_208:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001041544 + +*RES +0 ropt_mt_inst_803:X ropt_net_208:10 0.152 +1 ropt_net_208:2 ropt_mt_inst_847:A 0.152 +2 ropt_net_208:4 ropt_net_208:3 0.002834822 +3 ropt_net_208:5 ropt_net_208:4 0.0045 +4 ropt_net_208:9 ropt_net_208:8 0.0045 +5 ropt_net_208:8 ropt_net_208:7 0.00019375 +6 ropt_net_208:10 ropt_net_208:9 0.003002232 +7 ropt_net_208:3 ropt_net_208:2 0.0003035715 +8 ropt_net_208:6 ropt_net_208:5 0.001477679 +9 ropt_net_208:7 ropt_net_208:6 0.0003705357 + +*END + +*D_NET ropt_net_234 0.001156374 //LENGTH 9.310 LUMPCC 0.0001041272 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 138.750 75.140 +*I ropt_mt_inst_882:A I *L 0.001767 *C 130.180 74.800 +*N ropt_net_234:2 *C 130.180 74.800 +*N ropt_net_234:3 *C 130.180 75.140 +*N ropt_net_234:4 *C 138.713 75.140 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 ropt_mt_inst_882:A 1e-06 +2 ropt_net_234:2 6.125609e-05 +3 ropt_net_234:3 0.0005094014 +4 ropt_net_234:4 0.0004795893 +5 ropt_net_234:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 5.206362e-05 +6 ropt_net_234:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 5.206362e-05 + +*RES +0 ropt_mt_inst_815:X ropt_net_234:4 0.152 +1 ropt_net_234:4 ropt_net_234:3 0.007618304 +2 ropt_net_234:2 ropt_mt_inst_882:A 0.152 +3 ropt_net_234:3 ropt_net_234:2 0.0003035715 + +*END + +*D_NET ropt_net_217 0.001004705 //LENGTH 7.315 LUMPCC 0.0002976776 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 7.095 39.440 +*I ropt_mt_inst_859:A I *L 0.001767 *C 3.220 42.160 +*N ropt_net_217:2 *C 3.258 42.160 +*N ropt_net_217:3 *C 6.855 42.160 +*N ropt_net_217:4 *C 6.900 42.115 +*N ropt_net_217:5 *C 6.900 39.485 +*N ropt_net_217:6 *C 6.900 39.440 +*N ropt_net_217:7 *C 7.095 39.440 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 ropt_mt_inst_859:A 1e-06 +2 ropt_net_217:2 0.0001303059 +3 ropt_net_217:3 0.0001303059 +4 ropt_net_217:4 0.0001615829 +5 ropt_net_217:5 0.0001615829 +6 ropt_net_217:6 6.080342e-05 +7 ropt_net_217:7 6.044648e-05 +8 ropt_net_217:2 chanx_right_in[13]:11 0.0001488388 +9 ropt_net_217:3 chanx_right_in[13]:12 0.0001488388 + +*RES +0 ropt_mt_inst_823:X ropt_net_217:7 0.152 +1 ropt_net_217:2 ropt_mt_inst_859:A 0.152 +2 ropt_net_217:3 ropt_net_217:2 0.003212054 +3 ropt_net_217:4 ropt_net_217:3 0.0045 +4 ropt_net_217:6 ropt_net_217:5 0.0045 +5 ropt_net_217:5 ropt_net_217:4 0.002348215 +6 ropt_net_217:7 ropt_net_217:6 0.0001059783 + +*END + +*D_NET chanx_left_out[15] 0.0006092365 //LENGTH 4.100 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_859:X O *L 0 *C 4.140 41.480 +*P chanx_left_out[15] O *L 0.7423 *C 1.230 40.800 +*N chanx_left_out[15]:2 *C 4.133 40.800 +*N chanx_left_out[15]:3 *C 4.140 40.858 +*N chanx_left_out[15]:4 *C 4.140 41.435 +*N chanx_left_out[15]:5 *C 4.140 41.480 + +*CAP +0 ropt_mt_inst_859:X 1e-06 +1 chanx_left_out[15] 0.0002254913 +2 chanx_left_out[15]:2 0.0002254913 +3 chanx_left_out[15]:3 6.335669e-05 +4 chanx_left_out[15]:4 6.335669e-05 +5 chanx_left_out[15]:5 3.054048e-05 + +*RES +0 ropt_mt_inst_859:X chanx_left_out[15]:5 0.152 +1 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +2 chanx_left_out[15]:4 chanx_left_out[15]:3 0.000515625 +3 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +4 chanx_left_out[15]:2 chanx_left_out[15] 0.000454725 + +*END + +*D_NET ropt_net_188 0.0005433816 //LENGTH 4.745 LUMPCC 0 DR + +*CONN +*I BUFT_P_125:X O *L 0 *C 133.860 77.860 +*I ropt_mt_inst_827:A I *L 0.001766 *C 134.780 80.240 +*N ropt_net_188:2 *C 134.757 80.267 +*N ropt_net_188:3 *C 134.745 80.580 +*N ropt_net_188:4 *C 133.905 80.580 +*N ropt_net_188:5 *C 133.860 80.535 +*N ropt_net_188:6 *C 133.860 77.905 +*N ropt_net_188:7 *C 133.860 77.860 + +*CAP +0 BUFT_P_125:X 1e-06 +1 ropt_mt_inst_827:A 1e-06 +2 ropt_net_188:2 3.224734e-05 +3 ropt_net_188:3 9.692858e-05 +4 ropt_net_188:4 6.468125e-05 +5 ropt_net_188:5 0.0001566223 +6 ropt_net_188:6 0.0001566223 +7 ropt_net_188:7 3.427991e-05 + +*RES +0 BUFT_P_125:X ropt_net_188:7 0.152 +1 ropt_net_188:7 ropt_net_188:6 0.0045 +2 ropt_net_188:6 ropt_net_188:5 0.002348214 +3 ropt_net_188:4 ropt_net_188:3 0.00075 +4 ropt_net_188:5 ropt_net_188:4 0.0045 +5 ropt_net_188:2 ropt_mt_inst_827:A 0.152 +6 ropt_net_188:3 ropt_net_188:2 0.0002111487 + +*END + +*D_NET ropt_net_231 0.0005106712 //LENGTH 3.645 LUMPCC 0.0002154307 DR + +*CONN +*I ropt_mt_inst_839:X O *L 0 *C 100.000 124.100 +*I ropt_mt_inst_879:A I *L 0.001767 *C 99.360 126.480 +*N ropt_net_231:2 *C 99.360 126.480 +*N ropt_net_231:3 *C 99.360 126.435 +*N ropt_net_231:4 *C 99.360 124.145 +*N ropt_net_231:5 *C 99.405 124.100 +*N ropt_net_231:6 *C 99.963 124.100 + +*CAP +0 ropt_mt_inst_839:X 1e-06 +1 ropt_mt_inst_879:A 1e-06 +2 ropt_net_231:2 3.130307e-05 +3 ropt_net_231:3 9.767248e-05 +4 ropt_net_231:4 9.767248e-05 +5 ropt_net_231:5 3.32962e-05 +6 ropt_net_231:6 3.32962e-05 +7 ropt_net_231:4 chany_top_out[4]:2 7.194589e-05 +8 ropt_net_231:3 chany_top_out[4] 7.194589e-05 +9 ropt_net_231:6 ropt_net_198:6 3.473322e-05 +10 ropt_net_231:5 ropt_net_198:5 3.473322e-05 +11 ropt_net_231:4 ropt_net_198:8 1.036248e-06 +12 ropt_net_231:3 ropt_net_198:7 1.036248e-06 + +*RES +0 ropt_mt_inst_839:X ropt_net_231:6 0.152 +1 ropt_net_231:6 ropt_net_231:5 0.0004977679 +2 ropt_net_231:5 ropt_net_231:4 0.0045 +3 ropt_net_231:4 ropt_net_231:3 0.002044643 +4 ropt_net_231:2 ropt_mt_inst_879:A 0.152 +5 ropt_net_231:3 ropt_net_231:2 0.0045 + +*END + +*D_NET chanx_right_out[15] 0.001110087 //LENGTH 8.890 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_881:X O *L 0 *C 135.700 71.400 +*P chanx_right_out[15] O *L 0.7423 *C 140.375 68.000 +*N chanx_right_out[15]:2 *C 136.627 68.000 +*N chanx_right_out[15]:3 *C 136.620 68.058 +*N chanx_right_out[15]:4 *C 136.620 71.355 +*N chanx_right_out[15]:5 *C 136.575 71.400 +*N chanx_right_out[15]:6 *C 135.738 71.400 + +*CAP +0 ropt_mt_inst_881:X 1e-06 +1 chanx_right_out[15] 0.000271107 +2 chanx_right_out[15]:2 0.000271107 +3 chanx_right_out[15]:3 0.0001985487 +4 chanx_right_out[15]:4 0.0001985487 +5 chanx_right_out[15]:5 8.488769e-05 +6 chanx_right_out[15]:6 8.488769e-05 + +*RES +0 ropt_mt_inst_881:X chanx_right_out[15]:6 0.152 +1 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +2 chanx_right_out[15]:2 chanx_right_out[15] 0.0005871083 +3 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +4 chanx_right_out[15]:4 chanx_right_out[15]:3 0.002944197 +5 chanx_right_out[15]:6 chanx_right_out[15]:5 0.0007477679 + +*END + +*D_NET chany_top_in[10] 0.02960785 //LENGTH 230.010 LUMPCC 0.00479431 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 73.140 129.270 +*I mux_right_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.220 77.860 +*I mux_bottom_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 25.205 52.700 +*I FTB_7__6:A I *L 0.001776 *C 75.900 4.080 +*I mux_left_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 26.510 76.840 +*N chany_top_in[10]:5 *C 26.548 76.840 +*N chany_top_in[10]:6 *C 75.862 4.080 +*N chany_top_in[10]:7 *C 73.645 4.080 +*N chany_top_in[10]:8 *C 73.600 4.080 +*N chany_top_in[10]:9 *C 73.593 4.080 +*N chany_top_in[10]:10 *C 38.660 4.080 +*N chany_top_in[10]:11 *C 38.640 4.088 +*N chany_top_in[10]:12 *C 38.640 22.433 +*N chany_top_in[10]:13 *C 38.620 22.440 +*N chany_top_in[10]:14 *C 30.380 22.440 +*N chany_top_in[10]:15 *C 30.360 22.448 +*N chany_top_in[10]:16 *C 30.360 40.113 +*N chany_top_in[10]:17 *C 30.345 40.120 +*N chany_top_in[10]:18 *C 29.902 40.120 +*N chany_top_in[10]:19 *C 29.900 40.178 +*N chany_top_in[10]:20 *C 25.242 52.700 +*N chany_top_in[10]:21 *C 29.855 52.700 +*N chany_top_in[10]:22 *C 29.900 52.700 +*N chany_top_in[10]:23 *C 29.900 76.795 +*N chany_top_in[10]:24 *C 29.900 76.840 +*N chany_top_in[10]:25 *C 72.635 76.840 +*N chany_top_in[10]:26 *C 72.680 76.885 +*N chany_top_in[10]:27 *C 72.258 77.860 +*N chany_top_in[10]:28 *C 72.635 77.860 +*N chany_top_in[10]:29 *C 72.680 77.845 +*N chany_top_in[10]:30 *C 72.725 78.200 +*N chany_top_in[10]:31 *C 73.140 78.200 +*N chany_top_in[10]:32 *C 73.140 113.560 +*N chany_top_in[10]:33 *C 72.680 113.560 +*N chany_top_in[10]:34 *C 72.680 115.940 +*N chany_top_in[10]:35 *C 72.220 115.940 +*N chany_top_in[10]:36 *C 72.220 116.280 +*N chany_top_in[10]:37 *C 72.680 116.280 +*N chany_top_in[10]:38 *C 72.680 117.980 +*N chany_top_in[10]:39 *C 73.140 117.980 + +*CAP +0 chany_top_in[10] 0.0005660896 +1 mux_right_track_32\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_33\/mux_l1_in_0_:A1 1e-06 +3 FTB_7__6:A 1e-06 +4 mux_left_track_33\/mux_l1_in_0_:A0 1e-06 +5 chany_top_in[10]:5 0.0002781729 +6 chany_top_in[10]:6 0.0001198344 +7 chany_top_in[10]:7 0.0001198344 +8 chany_top_in[10]:8 3.553903e-05 +9 chany_top_in[10]:9 0.002264315 +10 chany_top_in[10]:10 0.002264315 +11 chany_top_in[10]:11 0.0009727249 +12 chany_top_in[10]:12 0.0009727249 +13 chany_top_in[10]:13 0.0005415887 +14 chany_top_in[10]:14 0.0005415887 +15 chany_top_in[10]:15 0.0009282255 +16 chany_top_in[10]:16 0.0009282255 +17 chany_top_in[10]:17 7.89735e-05 +18 chany_top_in[10]:18 7.89735e-05 +19 chany_top_in[10]:19 0.000775299 +20 chany_top_in[10]:20 0.0003252001 +21 chany_top_in[10]:21 0.0003252001 +22 chany_top_in[10]:22 0.001986435 +23 chany_top_in[10]:23 0.001177871 +24 chany_top_in[10]:24 0.002972838 +25 chany_top_in[10]:25 0.00266116 +26 chany_top_in[10]:26 5.769998e-05 +27 chany_top_in[10]:27 5.356732e-05 +28 chany_top_in[10]:28 5.356732e-05 +29 chany_top_in[10]:29 8.169733e-05 +30 chany_top_in[10]:30 5.603451e-05 +31 chany_top_in[10]:31 0.001270666 +32 chany_top_in[10]:32 0.001267766 +33 chany_top_in[10]:33 0.0001254289 +34 chany_top_in[10]:34 0.000105394 +35 chany_top_in[10]:35 2.103528e-05 +36 chany_top_in[10]:36 4.25718e-05 +37 chany_top_in[10]:37 0.0001301991 +38 chany_top_in[10]:38 8.112638e-05 +39 chany_top_in[10]:39 0.0005476557 +40 chany_top_in[10] chany_top_in[8] 2.931139e-05 +41 chany_top_in[10] chany_top_in[8]:35 1.421636e-05 +42 chany_top_in[10]:26 chany_top_in[8]:28 3.406496e-05 +43 chany_top_in[10]:29 chany_top_in[8]:28 1.449032e-05 +44 chany_top_in[10]:29 chany_top_in[8]:29 3.406496e-05 +45 chany_top_in[10]:35 chany_top_in[8]:34 1.286662e-05 +46 chany_top_in[10]:36 chany_top_in[8]:35 1.286662e-05 +47 chany_top_in[10]:34 chany_top_in[8]:35 2.797803e-05 +48 chany_top_in[10]:37 chany_top_in[8]:34 9.836131e-06 +49 chany_top_in[10]:30 chany_top_in[8]:29 1.449032e-05 +50 chany_top_in[10]:33 chany_top_in[8]:34 2.797803e-05 +51 chany_top_in[10]:32 chany_top_in[8]:29 6.635222e-05 +52 chany_top_in[10]:32 chany_top_in[8]:31 5.428793e-05 +53 chany_top_in[10]:32 chany_top_in[8]:33 0.0001922828 +54 chany_top_in[10]:32 chany_top_in[8]:35 4.284038e-05 +55 chany_top_in[10]:38 chany_top_in[8]:35 9.836131e-06 +56 chany_top_in[10]:39 chany_top_in[8]:34 1.421636e-05 +57 chany_top_in[10]:39 chany_top_in[8]:36 2.931139e-05 +58 chany_top_in[10]:31 chany_top_in[8]:28 6.635222e-05 +59 chany_top_in[10]:31 chany_top_in[8]:30 5.428793e-05 +60 chany_top_in[10]:31 chany_top_in[8]:32 0.0001922828 +61 chany_top_in[10]:31 chany_top_in[8]:34 4.284038e-05 +62 chany_top_in[10] chany_top_in[16] 4.455571e-07 +63 chany_top_in[10]:26 chany_top_in[16]:24 2.155906e-06 +64 chany_top_in[10]:29 chany_top_in[16]:24 1.05239e-06 +65 chany_top_in[10]:29 chany_top_in[16]:25 2.155906e-06 +66 chany_top_in[10]:30 chany_top_in[16]:25 1.05239e-06 +67 chany_top_in[10]:32 chany_top_in[16]:27 0.0003746614 +68 chany_top_in[10]:32 chany_top_in[16]:25 0.0001285834 +69 chany_top_in[10]:39 chany_top_in[16]:30 4.455571e-07 +70 chany_top_in[10]:31 chany_top_in[16]:24 0.0001285834 +71 chany_top_in[10]:31 chany_top_in[16]:26 0.0003746614 +72 chany_top_in[10]:23 mux_tree_tapbuf_size10_8_sram[1]:11 0.0003635447 +73 chany_top_in[10]:19 mux_tree_tapbuf_size10_8_sram[1]:12 6.444989e-05 +74 chany_top_in[10]:22 mux_tree_tapbuf_size10_8_sram[1]:12 0.0003635447 +75 chany_top_in[10]:22 mux_tree_tapbuf_size10_8_sram[1]:11 6.444989e-05 +76 chany_top_in[10] mux_tree_tapbuf_size12_0_sram[1]:11 1.881887e-06 +77 chany_top_in[10] mux_tree_tapbuf_size12_0_sram[1]:8 7.742619e-05 +78 chany_top_in[10]:35 mux_tree_tapbuf_size12_0_sram[1]:29 9.35082e-07 +79 chany_top_in[10]:36 mux_tree_tapbuf_size12_0_sram[1]:11 9.35082e-07 +80 chany_top_in[10]:34 mux_tree_tapbuf_size12_0_sram[1]:11 6.405226e-06 +81 chany_top_in[10]:34 mux_tree_tapbuf_size12_0_sram[1]:29 1.511633e-05 +82 chany_top_in[10]:37 mux_tree_tapbuf_size12_0_sram[1]:11 3.049006e-07 +83 chany_top_in[10]:37 mux_tree_tapbuf_size12_0_sram[1]:29 8.839464e-06 +84 chany_top_in[10]:33 mux_tree_tapbuf_size12_0_sram[1]:28 1.511633e-05 +85 chany_top_in[10]:33 mux_tree_tapbuf_size12_0_sram[1]:29 6.405226e-06 +86 chany_top_in[10]:32 mux_tree_tapbuf_size12_0_sram[1]:25 1.066189e-05 +87 chany_top_in[10]:32 mux_tree_tapbuf_size12_0_sram[1]:29 0.0001342676 +88 chany_top_in[10]:38 mux_tree_tapbuf_size12_0_sram[1]:9 4.779844e-05 +89 chany_top_in[10]:38 mux_tree_tapbuf_size12_0_sram[1]:11 8.839464e-06 +90 chany_top_in[10]:38 mux_tree_tapbuf_size12_0_sram[1]:8 3.049006e-07 +91 chany_top_in[10]:39 mux_tree_tapbuf_size12_0_sram[1]:10 4.779844e-05 +92 chany_top_in[10]:39 mux_tree_tapbuf_size12_0_sram[1]:11 7.742619e-05 +93 chany_top_in[10]:39 mux_tree_tapbuf_size12_0_sram[1]:29 1.881887e-06 +94 chany_top_in[10]:31 mux_tree_tapbuf_size12_0_sram[1]:28 0.0001342676 +95 chany_top_in[10]:31 mux_tree_tapbuf_size12_0_sram[1]:24 1.066189e-05 +96 chany_top_in[10]:24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002727807 +97 chany_top_in[10]:25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002727807 +98 chany_top_in[10]:24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.73738e-05 +99 chany_top_in[10]:24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.537424e-05 +100 chany_top_in[10]:25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.537424e-05 +101 chany_top_in[10]:25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.73738e-05 +102 chany_top_in[10]:23 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.720609e-05 +103 chany_top_in[10]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.720609e-05 +104 chany_top_in[10]:16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.579984e-05 +105 chany_top_in[10]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.579984e-05 +106 chany_top_in[10]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 6.795781e-05 +107 chany_top_in[10]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 6.795781e-05 +108 chany_top_in[10]:7 ropt_net_170:5 9.360537e-05 +109 chany_top_in[10]:6 ropt_net_170:4 9.360537e-05 + +*RES +0 chany_top_in[10] chany_top_in[10]:39 0.01008036 +1 chany_top_in[10]:24 chany_top_in[10]:23 0.0045 +2 chany_top_in[10]:24 chany_top_in[10]:5 0.002993304 +3 chany_top_in[10]:23 chany_top_in[10]:22 0.0215134 +4 chany_top_in[10]:25 chany_top_in[10]:24 0.03815625 +5 chany_top_in[10]:26 chany_top_in[10]:25 0.0045 +6 chany_top_in[10]:19 chany_top_in[10]:18 0.00341 +7 chany_top_in[10]:18 chany_top_in[10]:17 6.499219e-05 +8 chany_top_in[10]:17 chany_top_in[10]:16 0.00341 +9 chany_top_in[10]:16 chany_top_in[10]:15 0.002767517 +10 chany_top_in[10]:14 chany_top_in[10]:13 0.001290933 +11 chany_top_in[10]:15 chany_top_in[10]:14 0.00341 +12 chany_top_in[10]:13 chany_top_in[10]:12 0.00341 +13 chany_top_in[10]:12 chany_top_in[10]:11 0.00287405 +14 chany_top_in[10]:10 chany_top_in[10]:9 0.005472758 +15 chany_top_in[10]:11 chany_top_in[10]:10 0.00341 +16 chany_top_in[10]:8 chany_top_in[10]:7 0.0045 +17 chany_top_in[10]:9 chany_top_in[10]:8 0.00341 +18 chany_top_in[10]:7 chany_top_in[10]:6 0.001979911 +19 chany_top_in[10]:6 FTB_7__6:A 0.152 +20 chany_top_in[10]:5 mux_left_track_33\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[10]:21 chany_top_in[10]:20 0.004118304 +22 chany_top_in[10]:22 chany_top_in[10]:21 0.0045 +23 chany_top_in[10]:22 chany_top_in[10]:19 0.01118081 +24 chany_top_in[10]:20 mux_bottom_track_33\/mux_l1_in_0_:A1 0.152 +25 chany_top_in[10]:28 chany_top_in[10]:27 0.0003370536 +26 chany_top_in[10]:29 chany_top_in[10]:28 0.0045 +27 chany_top_in[10]:29 chany_top_in[10]:26 0.0008571429 +28 chany_top_in[10]:27 mux_right_track_32\/mux_l1_in_0_:A1 0.152 +29 chany_top_in[10]:35 chany_top_in[10]:34 0.0004107143 +30 chany_top_in[10]:36 chany_top_in[10]:35 0.0003035715 +31 chany_top_in[10]:34 chany_top_in[10]:33 0.002125 +32 chany_top_in[10]:37 chany_top_in[10]:36 0.0004107143 +33 chany_top_in[10]:30 chany_top_in[10]:29 0.000221875 +34 chany_top_in[10]:33 chany_top_in[10]:32 0.0004107143 +35 chany_top_in[10]:32 chany_top_in[10]:31 0.03157143 +36 chany_top_in[10]:38 chany_top_in[10]:37 0.001517857 +37 chany_top_in[10]:39 chany_top_in[10]:38 0.0004107143 +38 chany_top_in[10]:31 chany_top_in[10]:30 0.0003705357 + +*END + +*D_NET right_top_grid_pin_47_[0] 0.01160133 //LENGTH 91.095 LUMPCC 0.001577729 DR + +*CONN +*P right_top_grid_pin_47_[0] I *L 0.29796 *C 111.863 117.640 +*I mux_right_track_2\/mux_l1_in_2_:A0 I *L 0.001631 *C 113.335 93.160 +*I mux_right_track_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 114.255 76.840 +*I mux_right_track_16\/mux_l1_in_2_:A1 I *L 0.00198 *C 81.420 63.580 +*N right_top_grid_pin_47_[0]:4 *C 81.420 63.580 +*N right_top_grid_pin_47_[0]:5 *C 81.420 63.580 +*N right_top_grid_pin_47_[0]:6 *C 81.420 63.920 +*N right_top_grid_pin_47_[0]:7 *C 81.428 63.920 +*N right_top_grid_pin_47_[0]:8 *C 112.693 63.920 +*N right_top_grid_pin_47_[0]:9 *C 112.700 63.978 +*N right_top_grid_pin_47_[0]:10 *C 114.218 76.840 +*N right_top_grid_pin_47_[0]:11 *C 112.745 76.840 +*N right_top_grid_pin_47_[0]:12 *C 112.700 76.795 +*N right_top_grid_pin_47_[0]:13 *C 112.240 76.840 +*N right_top_grid_pin_47_[0]:14 *C 113.297 93.160 +*N right_top_grid_pin_47_[0]:15 *C 112.745 93.160 +*N right_top_grid_pin_47_[0]:16 *C 112.700 93.160 +*N right_top_grid_pin_47_[0]:17 *C 112.240 93.160 +*N right_top_grid_pin_47_[0]:18 *C 111.780 93.160 +*N right_top_grid_pin_47_[0]:19 *C 111.780 117.583 +*N right_top_grid_pin_47_[0]:20 *C 111.780 117.640 + +*CAP +0 right_top_grid_pin_47_[0] 2.006839e-05 +1 mux_right_track_2\/mux_l1_in_2_:A0 1e-06 +2 mux_right_track_4\/mux_l2_in_3_:A0 1e-06 +3 mux_right_track_16\/mux_l1_in_2_:A1 1e-06 +4 right_top_grid_pin_47_[0]:4 3.361717e-05 +5 right_top_grid_pin_47_[0]:5 5.413831e-05 +6 right_top_grid_pin_47_[0]:6 5.802217e-05 +7 right_top_grid_pin_47_[0]:7 0.001860269 +8 right_top_grid_pin_47_[0]:8 0.001860269 +9 right_top_grid_pin_47_[0]:9 0.0007798602 +10 right_top_grid_pin_47_[0]:10 0.0001287206 +11 right_top_grid_pin_47_[0]:11 0.0001287206 +12 right_top_grid_pin_47_[0]:12 0.0008135326 +13 right_top_grid_pin_47_[0]:13 0.0009844726 +14 right_top_grid_pin_47_[0]:14 7.191786e-05 +15 right_top_grid_pin_47_[0]:15 7.191786e-05 +16 right_top_grid_pin_47_[0]:16 6.486069e-05 +17 right_top_grid_pin_47_[0]:17 0.001010705 +18 right_top_grid_pin_47_[0]:18 0.001043973 +19 right_top_grid_pin_47_[0]:19 0.001015472 +20 right_top_grid_pin_47_[0]:20 2.006839e-05 +21 right_top_grid_pin_47_[0]:7 chanx_right_in[18]:31 0.0004791241 +22 right_top_grid_pin_47_[0]:8 chanx_right_in[18] 0.0004791241 +23 right_top_grid_pin_47_[0] right_top_grid_pin_43_[0]:25 7.391894e-06 +24 right_top_grid_pin_47_[0]:19 right_top_grid_pin_43_[0]:25 0.0002940426 +25 right_top_grid_pin_47_[0]:20 right_top_grid_pin_43_[0]:24 7.391894e-06 +26 right_top_grid_pin_47_[0]:18 right_top_grid_pin_43_[0]:24 0.0002940426 +27 right_top_grid_pin_47_[0]:17 right_top_grid_pin_43_[0]:19 8.305917e-06 +28 right_top_grid_pin_47_[0]:13 right_top_grid_pin_43_[0]:18 8.305917e-06 + +*RES +0 right_top_grid_pin_47_[0] right_top_grid_pin_47_[0]:20 2.35e-05 +1 right_top_grid_pin_47_[0]:15 right_top_grid_pin_47_[0]:14 0.0004933036 +2 right_top_grid_pin_47_[0]:16 right_top_grid_pin_47_[0]:15 0.0045 +3 right_top_grid_pin_47_[0]:14 mux_right_track_2\/mux_l1_in_2_:A0 0.152 +4 right_top_grid_pin_47_[0]:4 mux_right_track_16\/mux_l1_in_2_:A1 0.152 +5 right_top_grid_pin_47_[0]:5 right_top_grid_pin_47_[0]:4 0.0045 +6 right_top_grid_pin_47_[0]:6 right_top_grid_pin_47_[0]:5 0.0001634616 +7 right_top_grid_pin_47_[0]:7 right_top_grid_pin_47_[0]:6 0.00341 +8 right_top_grid_pin_47_[0]:9 right_top_grid_pin_47_[0]:8 0.00341 +9 right_top_grid_pin_47_[0]:8 right_top_grid_pin_47_[0]:7 0.004898183 +10 right_top_grid_pin_47_[0]:11 right_top_grid_pin_47_[0]:10 0.001314732 +11 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:11 0.0045 +12 right_top_grid_pin_47_[0]:12 right_top_grid_pin_47_[0]:9 0.0114442 +13 right_top_grid_pin_47_[0]:10 mux_right_track_4\/mux_l2_in_3_:A0 0.152 +14 right_top_grid_pin_47_[0]:19 right_top_grid_pin_47_[0]:18 0.0218058 +15 right_top_grid_pin_47_[0]:20 right_top_grid_pin_47_[0]:19 0.00341 +16 right_top_grid_pin_47_[0]:18 right_top_grid_pin_47_[0]:17 0.0004107143 +17 right_top_grid_pin_47_[0]:17 right_top_grid_pin_47_[0]:16 0.0004107143 +18 right_top_grid_pin_47_[0]:17 right_top_grid_pin_47_[0]:13 0.01457143 +19 right_top_grid_pin_47_[0]:13 right_top_grid_pin_47_[0]:12 0.0004107143 + +*END + +*D_NET left_top_grid_pin_42_[0] 0.01384826 //LENGTH 109.327 LUMPCC 0.001798135 DR + +*CONN +*P left_top_grid_pin_42_[0] I *L 0.29796 *C 7.360 102.070 +*I mux_left_track_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 45.830 91.460 +*I mux_left_track_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 44.450 77.180 +*I mux_left_track_1\/mux_l1_in_4_:A1 I *L 0.00198 *C 22.080 77.860 +*N left_top_grid_pin_42_[0]:4 *C 22.043 77.860 +*N left_top_grid_pin_42_[0]:5 *C 19.365 77.860 +*N left_top_grid_pin_42_[0]:6 *C 19.320 77.905 +*N left_top_grid_pin_42_[0]:7 *C 19.320 79.502 +*N left_top_grid_pin_42_[0]:8 *C 19.312 79.560 +*N left_top_grid_pin_42_[0]:9 *C 7.828 79.560 +*N left_top_grid_pin_42_[0]:10 *C 7.820 79.618 +*N left_top_grid_pin_42_[0]:11 *C 44.488 77.180 +*N left_top_grid_pin_42_[0]:12 *C 45.495 77.180 +*N left_top_grid_pin_42_[0]:13 *C 45.540 77.225 +*N left_top_grid_pin_42_[0]:14 *C 45.830 91.460 +*N left_top_grid_pin_42_[0]:15 *C 45.540 91.460 +*N left_top_grid_pin_42_[0]:16 *C 45.540 91.460 +*N left_top_grid_pin_42_[0]:17 *C 45.540 103.303 +*N left_top_grid_pin_42_[0]:18 *C 45.532 103.360 +*N left_top_grid_pin_42_[0]:19 *C 31.300 103.360 +*N left_top_grid_pin_42_[0]:20 *C 31.280 103.353 +*N left_top_grid_pin_42_[0]:21 *C 31.280 101.328 +*N left_top_grid_pin_42_[0]:22 *C 31.260 101.320 +*N left_top_grid_pin_42_[0]:23 *C 7.828 101.320 +*N left_top_grid_pin_42_[0]:24 *C 7.820 101.263 +*N left_top_grid_pin_42_[0]:25 *C 7.360 101.320 + +*CAP +0 left_top_grid_pin_42_[0] 5.43061e-05 +1 mux_left_track_5\/mux_l2_in_3_:A0 1e-06 +2 mux_left_track_9\/mux_l2_in_2_:A0 1e-06 +3 mux_left_track_1\/mux_l1_in_4_:A1 1e-06 +4 left_top_grid_pin_42_[0]:4 0.0001822974 +5 left_top_grid_pin_42_[0]:5 0.0001822974 +6 left_top_grid_pin_42_[0]:6 9.746516e-05 +7 left_top_grid_pin_42_[0]:7 9.746516e-05 +8 left_top_grid_pin_42_[0]:8 0.0009504221 +9 left_top_grid_pin_42_[0]:9 0.0009504221 +10 left_top_grid_pin_42_[0]:10 0.001077086 +11 left_top_grid_pin_42_[0]:11 0.0001047064 +12 left_top_grid_pin_42_[0]:12 0.0001047064 +13 left_top_grid_pin_42_[0]:13 0.0007922688 +14 left_top_grid_pin_42_[0]:14 6.263582e-05 +15 left_top_grid_pin_42_[0]:15 6.545109e-05 +16 left_top_grid_pin_42_[0]:16 0.001526422 +17 left_top_grid_pin_42_[0]:17 0.0007000415 +18 left_top_grid_pin_42_[0]:18 0.0008221159 +19 left_top_grid_pin_42_[0]:19 0.0008221159 +20 left_top_grid_pin_42_[0]:20 0.0001447244 +21 left_top_grid_pin_42_[0]:21 0.0001447244 +22 left_top_grid_pin_42_[0]:22 0.0009851314 +23 left_top_grid_pin_42_[0]:23 0.0009851314 +24 left_top_grid_pin_42_[0]:24 0.001108985 +25 left_top_grid_pin_42_[0]:25 8.620584e-05 +26 left_top_grid_pin_42_[0]:10 chanx_left_in[12]:39 3.616666e-06 +27 left_top_grid_pin_42_[0]:24 chanx_left_in[12]:38 3.616666e-06 +28 left_top_grid_pin_42_[0]:23 chanx_left_in[12]:37 0.0005046774 +29 left_top_grid_pin_42_[0]:22 chanx_left_in[12]:36 0.0005046774 +30 left_top_grid_pin_42_[0]:19 chanx_left_in[12]:37 4.013532e-05 +31 left_top_grid_pin_42_[0]:18 chanx_left_in[12]:36 4.013532e-05 +32 left_top_grid_pin_42_[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.598409e-05 +33 left_top_grid_pin_42_[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.060572e-05 +34 left_top_grid_pin_42_[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.598409e-05 +35 left_top_grid_pin_42_[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.060572e-05 +36 left_top_grid_pin_42_[0]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.463433e-05 +37 left_top_grid_pin_42_[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.463433e-05 +38 left_top_grid_pin_42_[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.000199414 +39 left_top_grid_pin_42_[0]:24 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.000199414 + +*RES +0 left_top_grid_pin_42_[0] left_top_grid_pin_42_[0]:25 0.0006696429 +1 left_top_grid_pin_42_[0]:10 left_top_grid_pin_42_[0]:9 0.00341 +2 left_top_grid_pin_42_[0]:9 left_top_grid_pin_42_[0]:8 0.001799317 +3 left_top_grid_pin_42_[0]:7 left_top_grid_pin_42_[0]:6 0.001426339 +4 left_top_grid_pin_42_[0]:8 left_top_grid_pin_42_[0]:7 0.00341 +5 left_top_grid_pin_42_[0]:5 left_top_grid_pin_42_[0]:4 0.002390625 +6 left_top_grid_pin_42_[0]:6 left_top_grid_pin_42_[0]:5 0.0045 +7 left_top_grid_pin_42_[0]:4 mux_left_track_1\/mux_l1_in_4_:A1 0.152 +8 left_top_grid_pin_42_[0]:24 left_top_grid_pin_42_[0]:23 0.00341 +9 left_top_grid_pin_42_[0]:24 left_top_grid_pin_42_[0]:10 0.0193259 +10 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:22 0.003671091 +11 left_top_grid_pin_42_[0]:22 left_top_grid_pin_42_[0]:21 0.00341 +12 left_top_grid_pin_42_[0]:21 left_top_grid_pin_42_[0]:20 0.00031725 +13 left_top_grid_pin_42_[0]:19 left_top_grid_pin_42_[0]:18 0.002229758 +14 left_top_grid_pin_42_[0]:20 left_top_grid_pin_42_[0]:19 0.00341 +15 left_top_grid_pin_42_[0]:17 left_top_grid_pin_42_[0]:16 0.01057366 +16 left_top_grid_pin_42_[0]:18 left_top_grid_pin_42_[0]:17 0.00341 +17 left_top_grid_pin_42_[0]:15 left_top_grid_pin_42_[0]:14 0.0001576087 +18 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:15 0.0045 +19 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:13 0.01270982 +20 left_top_grid_pin_42_[0]:14 mux_left_track_5\/mux_l2_in_3_:A0 0.152 +21 left_top_grid_pin_42_[0]:12 left_top_grid_pin_42_[0]:11 0.0008995536 +22 left_top_grid_pin_42_[0]:13 left_top_grid_pin_42_[0]:12 0.0045 +23 left_top_grid_pin_42_[0]:11 mux_left_track_9\/mux_l2_in_2_:A0 0.152 +24 left_top_grid_pin_42_[0]:25 left_top_grid_pin_42_[0]:24 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[1] 0.0046729 //LENGTH 36.270 LUMPCC 0.0001355252 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 115.305 66.300 +*I mux_right_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 109.380 61.495 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 105.975 58.820 +*I mux_right_track_8\/mux_l2_in_2_:S I *L 0.00357 *C 108.000 52.750 +*I mux_right_track_8\/mux_l2_in_3_:S I *L 0.00357 *C 110.280 52.700 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 108.000 63.920 +*N mux_tree_tapbuf_size10_3_sram[1]:6 *C 107.963 63.920 +*N mux_tree_tapbuf_size10_3_sram[1]:7 *C 105.845 63.920 +*N mux_tree_tapbuf_size10_3_sram[1]:8 *C 105.800 63.875 +*N mux_tree_tapbuf_size10_3_sram[1]:9 *C 110.243 52.700 +*N mux_tree_tapbuf_size10_3_sram[1]:10 *C 108.123 52.703 +*N mux_tree_tapbuf_size10_3_sram[1]:11 *C 107.963 53.040 +*N mux_tree_tapbuf_size10_3_sram[1]:12 *C 105.845 53.040 +*N mux_tree_tapbuf_size10_3_sram[1]:13 *C 105.800 53.085 +*N mux_tree_tapbuf_size10_3_sram[1]:14 *C 105.975 58.820 +*N mux_tree_tapbuf_size10_3_sram[1]:15 *C 105.800 58.820 +*N mux_tree_tapbuf_size10_3_sram[1]:16 *C 105.800 58.820 +*N mux_tree_tapbuf_size10_3_sram[1]:17 *C 105.800 60.860 +*N mux_tree_tapbuf_size10_3_sram[1]:18 *C 105.845 60.860 +*N mux_tree_tapbuf_size10_3_sram[1]:19 *C 109.480 60.860 +*N mux_tree_tapbuf_size10_3_sram[1]:20 *C 109.450 61.270 +*N mux_tree_tapbuf_size10_3_sram[1]:21 *C 109.410 61.130 +*N mux_tree_tapbuf_size10_3_sram[1]:22 *C 109.380 61.495 +*N mux_tree_tapbuf_size10_3_sram[1]:23 *C 109.380 61.880 +*N mux_tree_tapbuf_size10_3_sram[1]:24 *C 114.955 61.880 +*N mux_tree_tapbuf_size10_3_sram[1]:25 *C 115.000 61.925 +*N mux_tree_tapbuf_size10_3_sram[1]:26 *C 115.000 66.255 +*N mux_tree_tapbuf_size10_3_sram[1]:27 *C 115.000 66.300 +*N mux_tree_tapbuf_size10_3_sram[1]:28 *C 115.305 66.300 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_8\/mux_l2_in_1_:S 1e-06 +2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_8\/mux_l2_in_2_:S 1e-06 +4 mux_right_track_8\/mux_l2_in_3_:S 1e-06 +5 mux_right_track_8\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_3_sram[1]:6 0.0001591584 +7 mux_tree_tapbuf_size10_3_sram[1]:7 0.0001591584 +8 mux_tree_tapbuf_size10_3_sram[1]:8 0.0001623034 +9 mux_tree_tapbuf_size10_3_sram[1]:9 0.0001750091 +10 mux_tree_tapbuf_size10_3_sram[1]:10 0.0002050901 +11 mux_tree_tapbuf_size10_3_sram[1]:11 0.0002149001 +12 mux_tree_tapbuf_size10_3_sram[1]:12 0.000184819 +13 mux_tree_tapbuf_size10_3_sram[1]:13 0.0003223256 +14 mux_tree_tapbuf_size10_3_sram[1]:14 6.323378e-05 +15 mux_tree_tapbuf_size10_3_sram[1]:15 6.221122e-05 +16 mux_tree_tapbuf_size10_3_sram[1]:16 0.0004658333 +17 mux_tree_tapbuf_size10_3_sram[1]:17 0.0003040965 +18 mux_tree_tapbuf_size10_3_sram[1]:18 0.0002006729 +19 mux_tree_tapbuf_size10_3_sram[1]:19 0.0002255538 +20 mux_tree_tapbuf_size10_3_sram[1]:20 4.253952e-05 +21 mux_tree_tapbuf_size10_3_sram[1]:21 2.1977e-05 +22 mux_tree_tapbuf_size10_3_sram[1]:22 8.59003e-05 +23 mux_tree_tapbuf_size10_3_sram[1]:23 0.0004255968 +24 mux_tree_tapbuf_size10_3_sram[1]:24 0.0004018352 +25 mux_tree_tapbuf_size10_3_sram[1]:25 0.000270236 +26 mux_tree_tapbuf_size10_3_sram[1]:26 0.000270236 +27 mux_tree_tapbuf_size10_3_sram[1]:27 5.514533e-05 +28 mux_tree_tapbuf_size10_3_sram[1]:28 5.354286e-05 +29 mux_tree_tapbuf_size10_3_sram[1]:18 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.545078e-05 +30 mux_tree_tapbuf_size10_3_sram[1]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.231183e-05 +31 mux_tree_tapbuf_size10_3_sram[1]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.231183e-05 +32 mux_tree_tapbuf_size10_3_sram[1]:19 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.545078e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_3_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_3_sram[1]:9 mux_right_track_8\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size10_3_sram[1]:24 mux_tree_tapbuf_size10_3_sram[1]:23 0.004977679 +3 mux_tree_tapbuf_size10_3_sram[1]:25 mux_tree_tapbuf_size10_3_sram[1]:24 0.0045 +4 mux_tree_tapbuf_size10_3_sram[1]:27 mux_tree_tapbuf_size10_3_sram[1]:26 0.0045 +5 mux_tree_tapbuf_size10_3_sram[1]:26 mux_tree_tapbuf_size10_3_sram[1]:25 0.003866072 +6 mux_tree_tapbuf_size10_3_sram[1]:28 mux_tree_tapbuf_size10_3_sram[1]:27 0.0001657609 +7 mux_tree_tapbuf_size10_3_sram[1]:22 mux_right_track_8\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:21 0.0003258929 +9 mux_tree_tapbuf_size10_3_sram[1]:22 mux_tree_tapbuf_size10_3_sram[1]:20 1.861702e-05 +10 mux_tree_tapbuf_size10_3_sram[1]:15 mux_tree_tapbuf_size10_3_sram[1]:14 9.510871e-05 +11 mux_tree_tapbuf_size10_3_sram[1]:16 mux_tree_tapbuf_size10_3_sram[1]:15 0.0045 +12 mux_tree_tapbuf_size10_3_sram[1]:16 mux_tree_tapbuf_size10_3_sram[1]:13 0.005120536 +13 mux_tree_tapbuf_size10_3_sram[1]:14 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size10_3_sram[1]:12 mux_tree_tapbuf_size10_3_sram[1]:11 0.001890625 +15 mux_tree_tapbuf_size10_3_sram[1]:13 mux_tree_tapbuf_size10_3_sram[1]:12 0.0045 +16 mux_tree_tapbuf_size10_3_sram[1]:10 mux_right_track_8\/mux_l2_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_3_sram[1]:10 mux_tree_tapbuf_size10_3_sram[1]:9 0.001892857 +18 mux_tree_tapbuf_size10_3_sram[1]:18 mux_tree_tapbuf_size10_3_sram[1]:17 0.0045 +19 mux_tree_tapbuf_size10_3_sram[1]:17 mux_tree_tapbuf_size10_3_sram[1]:16 0.001821429 +20 mux_tree_tapbuf_size10_3_sram[1]:17 mux_tree_tapbuf_size10_3_sram[1]:8 0.002691964 +21 mux_tree_tapbuf_size10_3_sram[1]:7 mux_tree_tapbuf_size10_3_sram[1]:6 0.001890625 +22 mux_tree_tapbuf_size10_3_sram[1]:8 mux_tree_tapbuf_size10_3_sram[1]:7 0.0045 +23 mux_tree_tapbuf_size10_3_sram[1]:6 mux_right_track_8\/mux_l2_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_3_sram[1]:11 mux_tree_tapbuf_size10_3_sram[1]:10 0.0001339286 +25 mux_tree_tapbuf_size10_3_sram[1]:19 mux_tree_tapbuf_size10_3_sram[1]:18 0.003245536 +26 mux_tree_tapbuf_size10_3_sram[1]:23 mux_tree_tapbuf_size10_3_sram[1]:22 0.00034375 +27 mux_tree_tapbuf_size10_3_sram[1]:20 mux_tree_tapbuf_size10_3_sram[1]:19 0.0003660714 + +*END + +*D_NET mux_tree_tapbuf_size12_2_sram[2] 0.003554916 //LENGTH 28.065 LUMPCC 0.0003921852 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 101.045 113.220 +*I mux_right_track_0\/mux_l3_in_1_:S I *L 0.00357 *C 100.640 99.960 +*I mux_right_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 99.720 107.440 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 101.830 115.260 +*N mux_tree_tapbuf_size12_2_sram[2]:4 *C 101.793 115.260 +*N mux_tree_tapbuf_size12_2_sram[2]:5 *C 100.740 115.260 +*N mux_tree_tapbuf_size12_2_sram[2]:6 *C 100.740 114.920 +*N mux_tree_tapbuf_size12_2_sram[2]:7 *C 100.740 114.875 +*N mux_tree_tapbuf_size12_2_sram[2]:8 *C 99.683 107.440 +*N mux_tree_tapbuf_size12_2_sram[2]:9 *C 97.565 107.440 +*N mux_tree_tapbuf_size12_2_sram[2]:10 *C 97.520 107.485 +*N mux_tree_tapbuf_size12_2_sram[2]:11 *C 97.520 109.775 +*N mux_tree_tapbuf_size12_2_sram[2]:12 *C 97.565 109.820 +*N mux_tree_tapbuf_size12_2_sram[2]:13 *C 100.603 99.960 +*N mux_tree_tapbuf_size12_2_sram[2]:14 *C 99.405 99.960 +*N mux_tree_tapbuf_size12_2_sram[2]:15 *C 99.360 100.005 +*N mux_tree_tapbuf_size12_2_sram[2]:16 *C 99.360 109.775 +*N mux_tree_tapbuf_size12_2_sram[2]:17 *C 99.360 109.820 +*N mux_tree_tapbuf_size12_2_sram[2]:18 *C 100.695 109.820 +*N mux_tree_tapbuf_size12_2_sram[2]:19 *C 100.740 109.865 +*N mux_tree_tapbuf_size12_2_sram[2]:20 *C 100.740 113.220 +*N mux_tree_tapbuf_size12_2_sram[2]:21 *C 100.740 113.220 +*N mux_tree_tapbuf_size12_2_sram[2]:22 *C 101.045 113.220 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_0\/mux_l3_in_1_:S 1e-06 +2 mux_right_track_0\/mux_l3_in_0_:S 1e-06 +3 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size12_2_sram[2]:4 8.572286e-05 +5 mux_tree_tapbuf_size12_2_sram[2]:5 0.000113283 +6 mux_tree_tapbuf_size12_2_sram[2]:6 5.945063e-05 +7 mux_tree_tapbuf_size12_2_sram[2]:7 9.288105e-05 +8 mux_tree_tapbuf_size12_2_sram[2]:8 0.0001200532 +9 mux_tree_tapbuf_size12_2_sram[2]:9 0.0001200532 +10 mux_tree_tapbuf_size12_2_sram[2]:10 0.0001467064 +11 mux_tree_tapbuf_size12_2_sram[2]:11 0.0001467064 +12 mux_tree_tapbuf_size12_2_sram[2]:12 0.0001082603 +13 mux_tree_tapbuf_size12_2_sram[2]:13 0.0001228173 +14 mux_tree_tapbuf_size12_2_sram[2]:14 0.0001228173 +15 mux_tree_tapbuf_size12_2_sram[2]:15 0.0005093994 +16 mux_tree_tapbuf_size12_2_sram[2]:16 0.0005093994 +17 mux_tree_tapbuf_size12_2_sram[2]:17 0.0002246446 +18 mux_tree_tapbuf_size12_2_sram[2]:18 8.418049e-05 +19 mux_tree_tapbuf_size12_2_sram[2]:19 0.000187403 +20 mux_tree_tapbuf_size12_2_sram[2]:20 0.0003090608 +21 mux_tree_tapbuf_size12_2_sram[2]:21 4.946686e-05 +22 mux_tree_tapbuf_size12_2_sram[2]:22 4.642441e-05 +23 mux_tree_tapbuf_size12_2_sram[2]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.490884e-05 +24 mux_tree_tapbuf_size12_2_sram[2]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.490884e-05 +25 mux_tree_tapbuf_size12_2_sram[2]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001360495 +26 mux_tree_tapbuf_size12_2_sram[2]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001360495 +27 mux_tree_tapbuf_size12_2_sram[2]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 1.513421e-05 +28 mux_tree_tapbuf_size12_2_sram[2]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 1.513421e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_2_sram[2]:22 0.152 +1 mux_tree_tapbuf_size12_2_sram[2]:4 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size12_2_sram[2]:6 mux_tree_tapbuf_size12_2_sram[2]:5 0.0003035715 +3 mux_tree_tapbuf_size12_2_sram[2]:7 mux_tree_tapbuf_size12_2_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size12_2_sram[2]:18 mux_tree_tapbuf_size12_2_sram[2]:17 0.001191964 +5 mux_tree_tapbuf_size12_2_sram[2]:19 mux_tree_tapbuf_size12_2_sram[2]:18 0.0045 +6 mux_tree_tapbuf_size12_2_sram[2]:17 mux_tree_tapbuf_size12_2_sram[2]:16 0.0045 +7 mux_tree_tapbuf_size12_2_sram[2]:17 mux_tree_tapbuf_size12_2_sram[2]:12 0.001602679 +8 mux_tree_tapbuf_size12_2_sram[2]:16 mux_tree_tapbuf_size12_2_sram[2]:15 0.008723214 +9 mux_tree_tapbuf_size12_2_sram[2]:14 mux_tree_tapbuf_size12_2_sram[2]:13 0.001069196 +10 mux_tree_tapbuf_size12_2_sram[2]:15 mux_tree_tapbuf_size12_2_sram[2]:14 0.0045 +11 mux_tree_tapbuf_size12_2_sram[2]:13 mux_right_track_0\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size12_2_sram[2]:21 mux_tree_tapbuf_size12_2_sram[2]:20 0.0045 +13 mux_tree_tapbuf_size12_2_sram[2]:20 mux_tree_tapbuf_size12_2_sram[2]:19 0.002995536 +14 mux_tree_tapbuf_size12_2_sram[2]:20 mux_tree_tapbuf_size12_2_sram[2]:7 0.001477679 +15 mux_tree_tapbuf_size12_2_sram[2]:22 mux_tree_tapbuf_size12_2_sram[2]:21 0.0001657609 +16 mux_tree_tapbuf_size12_2_sram[2]:12 mux_tree_tapbuf_size12_2_sram[2]:11 0.0045 +17 mux_tree_tapbuf_size12_2_sram[2]:11 mux_tree_tapbuf_size12_2_sram[2]:10 0.002044643 +18 mux_tree_tapbuf_size12_2_sram[2]:9 mux_tree_tapbuf_size12_2_sram[2]:8 0.001890625 +19 mux_tree_tapbuf_size12_2_sram[2]:10 mux_tree_tapbuf_size12_2_sram[2]:9 0.0045 +20 mux_tree_tapbuf_size12_2_sram[2]:8 mux_right_track_0\/mux_l3_in_0_:S 0.152 +21 mux_tree_tapbuf_size12_2_sram[2]:5 mux_tree_tapbuf_size12_2_sram[2]:4 0.0009397322 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_4_ccff_tail[0] 0.001010282 //LENGTH 8.305 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/FTB_5__56:X O *L 0 *C 80.725 12.580 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.070 15.300 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:2 *C 76.108 15.300 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:3 *C 78.615 15.300 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:4 *C 78.660 15.255 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:5 *C 78.660 12.625 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:6 *C 78.705 12.580 +*N mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:7 *C 80.688 12.580 + +*CAP +0 mem_bottom_track_1\/FTB_5__56:X 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:2 0.0001815088 +3 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:3 0.0001815088 +4 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:4 0.0001714911 +5 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:5 0.0001714911 +6 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:6 0.000151141 +7 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:7 0.000151141 + +*RES +0 mem_bottom_track_1\/FTB_5__56:X mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:6 0.001770089 +2 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:2 0.002238839 +5 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size12_mem_4_ccff_tail[0]:2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size16_1_sram[3] 0.002705231 //LENGTH 20.855 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 130.800 76.840 +*I mux_right_track_4\/mux_l4_in_0_:S I *L 0.00357 *C 123.640 74.510 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D I *L 0.001695 *C 121.615 71.740 +*I mux_right_track_4\/mux_l4_in_1_:S I *L 0.00357 *C 120.420 69.020 +*N mux_tree_tapbuf_size16_1_sram[3]:4 *C 120.458 69.020 +*N mux_tree_tapbuf_size16_1_sram[3]:5 *C 120.935 69.020 +*N mux_tree_tapbuf_size16_1_sram[3]:6 *C 120.980 69.065 +*N mux_tree_tapbuf_size16_1_sram[3]:7 *C 121.578 71.740 +*N mux_tree_tapbuf_size16_1_sram[3]:8 *C 121.025 71.740 +*N mux_tree_tapbuf_size16_1_sram[3]:9 *C 120.980 71.740 +*N mux_tree_tapbuf_size16_1_sram[3]:10 *C 120.980 74.075 +*N mux_tree_tapbuf_size16_1_sram[3]:11 *C 121.025 74.120 +*N mux_tree_tapbuf_size16_1_sram[3]:12 *C 123.740 74.120 +*N mux_tree_tapbuf_size16_1_sram[3]:13 *C 123.640 74.510 +*N mux_tree_tapbuf_size16_1_sram[3]:14 *C 123.740 74.505 +*N mux_tree_tapbuf_size16_1_sram[3]:15 *C 123.740 76.795 +*N mux_tree_tapbuf_size16_1_sram[3]:16 *C 123.785 76.840 +*N mux_tree_tapbuf_size16_1_sram[3]:17 *C 130.763 76.840 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:S 1e-06 +2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D 1e-06 +3 mux_right_track_4\/mux_l4_in_1_:S 1e-06 +4 mux_tree_tapbuf_size16_1_sram[3]:4 4.981703e-05 +5 mux_tree_tapbuf_size16_1_sram[3]:5 4.981703e-05 +6 mux_tree_tapbuf_size16_1_sram[3]:6 0.0001463065 +7 mux_tree_tapbuf_size16_1_sram[3]:7 6.040685e-05 +8 mux_tree_tapbuf_size16_1_sram[3]:8 6.040685e-05 +9 mux_tree_tapbuf_size16_1_sram[3]:9 0.0003151147 +10 mux_tree_tapbuf_size16_1_sram[3]:10 0.0001360763 +11 mux_tree_tapbuf_size16_1_sram[3]:11 0.0002192443 +12 mux_tree_tapbuf_size16_1_sram[3]:12 0.0002491015 +13 mux_tree_tapbuf_size16_1_sram[3]:13 5.840758e-05 +14 mux_tree_tapbuf_size16_1_sram[3]:14 0.0001491142 +15 mux_tree_tapbuf_size16_1_sram[3]:15 0.0001491142 +16 mux_tree_tapbuf_size16_1_sram[3]:16 0.0005291519 +17 mux_tree_tapbuf_size16_1_sram[3]:17 0.0005291519 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size16_1_sram[3]:17 0.152 +1 mux_tree_tapbuf_size16_1_sram[3]:4 mux_right_track_4\/mux_l4_in_1_:S 0.152 +2 mux_tree_tapbuf_size16_1_sram[3]:5 mux_tree_tapbuf_size16_1_sram[3]:4 0.0004263393 +3 mux_tree_tapbuf_size16_1_sram[3]:6 mux_tree_tapbuf_size16_1_sram[3]:5 0.0045 +4 mux_tree_tapbuf_size16_1_sram[3]:11 mux_tree_tapbuf_size16_1_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size16_1_sram[3]:10 mux_tree_tapbuf_size16_1_sram[3]:9 0.002084821 +6 mux_tree_tapbuf_size16_1_sram[3]:8 mux_tree_tapbuf_size16_1_sram[3]:7 0.0004933036 +7 mux_tree_tapbuf_size16_1_sram[3]:9 mux_tree_tapbuf_size16_1_sram[3]:8 0.0045 +8 mux_tree_tapbuf_size16_1_sram[3]:9 mux_tree_tapbuf_size16_1_sram[3]:6 0.002388393 +9 mux_tree_tapbuf_size16_1_sram[3]:7 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:D 0.152 +10 mux_tree_tapbuf_size16_1_sram[3]:13 mux_right_track_4\/mux_l4_in_0_:S 0.152 +11 mux_tree_tapbuf_size16_1_sram[3]:13 mux_tree_tapbuf_size16_1_sram[3]:12 0.0003482143 +12 mux_tree_tapbuf_size16_1_sram[3]:14 mux_tree_tapbuf_size16_1_sram[3]:13 0.0045 +13 mux_tree_tapbuf_size16_1_sram[3]:16 mux_tree_tapbuf_size16_1_sram[3]:15 0.0045 +14 mux_tree_tapbuf_size16_1_sram[3]:15 mux_tree_tapbuf_size16_1_sram[3]:14 0.002044643 +15 mux_tree_tapbuf_size16_1_sram[3]:17 mux_tree_tapbuf_size16_1_sram[3]:16 0.006229911 +16 mux_tree_tapbuf_size16_1_sram[3]:12 mux_tree_tapbuf_size16_1_sram[3]:11 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size16_3_sram[2] 0.01190793 //LENGTH 89.035 LUMPCC 0.001110949 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 31.125 47.940 +*I mux_left_track_5\/mux_l3_in_2_:S I *L 0.00357 *C 21.260 89.080 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 5.695 93.500 +*I mux_left_track_5\/mux_l3_in_3_:S I *L 0.00357 *C 13.900 93.840 +*I mux_left_track_5\/mux_l3_in_1_:S I *L 0.00357 *C 31.840 89.080 +*I mux_left_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 36.440 89.080 +*N mux_tree_tapbuf_size16_3_sram[2]:6 *C 29.650 47.940 +*N mux_tree_tapbuf_size16_3_sram[2]:7 *C 29.960 82.280 +*N mux_tree_tapbuf_size16_3_sram[2]:8 *C 36.403 89.080 +*N mux_tree_tapbuf_size16_3_sram[2]:9 *C 31.840 89.080 +*N mux_tree_tapbuf_size16_3_sram[2]:10 *C 13.863 93.840 +*N mux_tree_tapbuf_size16_3_sram[2]:11 *C 5.732 93.500 +*N mux_tree_tapbuf_size16_3_sram[2]:12 *C 10.120 93.500 +*N mux_tree_tapbuf_size16_3_sram[2]:13 *C 10.120 93.840 +*N mux_tree_tapbuf_size16_3_sram[2]:14 *C 10.120 93.885 +*N mux_tree_tapbuf_size16_3_sram[2]:15 *C 10.120 95.142 +*N mux_tree_tapbuf_size16_3_sram[2]:16 *C 10.128 95.200 +*N mux_tree_tapbuf_size16_3_sram[2]:17 *C 21.152 95.200 +*N mux_tree_tapbuf_size16_3_sram[2]:18 *C 21.160 95.142 +*N mux_tree_tapbuf_size16_3_sram[2]:19 *C 21.160 89.125 +*N mux_tree_tapbuf_size16_3_sram[2]:20 *C 21.297 89.080 +*N mux_tree_tapbuf_size16_3_sram[2]:21 *C 30.360 89.080 +*N mux_tree_tapbuf_size16_3_sram[2]:22 *C 30.360 89.035 +*N mux_tree_tapbuf_size16_3_sram[2]:23 *C 30.360 82.338 +*N mux_tree_tapbuf_size16_3_sram[2]:24 *C 30.360 82.280 +*N mux_tree_tapbuf_size16_3_sram[2]:25 *C 30.360 82.273 +*N mux_tree_tapbuf_size16_3_sram[2]:26 *C 30.360 47.948 +*N mux_tree_tapbuf_size16_3_sram[2]:27 *C 30.358 47.940 +*N mux_tree_tapbuf_size16_3_sram[2]:28 *C 30.360 47.940 +*N mux_tree_tapbuf_size16_3_sram[2]:29 *C 30.405 47.940 +*N mux_tree_tapbuf_size16_3_sram[2]:30 *C 31.088 47.940 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_5\/mux_l3_in_2_:S 1e-06 +2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_left_track_5\/mux_l3_in_3_:S 1e-06 +4 mux_left_track_5\/mux_l3_in_1_:S 1e-06 +5 mux_left_track_5\/mux_l3_in_0_:S 1e-06 +6 mux_tree_tapbuf_size16_3_sram[2]:6 9.58641e-05 +7 mux_tree_tapbuf_size16_3_sram[2]:7 0.0001103237 +8 mux_tree_tapbuf_size16_3_sram[2]:8 0.0003254638 +9 mux_tree_tapbuf_size16_3_sram[2]:9 0.0004379541 +10 mux_tree_tapbuf_size16_3_sram[2]:10 0.000293914 +11 mux_tree_tapbuf_size16_3_sram[2]:11 0.0003183947 +12 mux_tree_tapbuf_size16_3_sram[2]:12 0.0003455653 +13 mux_tree_tapbuf_size16_3_sram[2]:13 0.0003210847 +14 mux_tree_tapbuf_size16_3_sram[2]:14 9.532217e-05 +15 mux_tree_tapbuf_size16_3_sram[2]:15 9.532217e-05 +16 mux_tree_tapbuf_size16_3_sram[2]:16 0.0006884367 +17 mux_tree_tapbuf_size16_3_sram[2]:17 0.0006884367 +18 mux_tree_tapbuf_size16_3_sram[2]:18 0.0004079503 +19 mux_tree_tapbuf_size16_3_sram[2]:19 0.0004079503 +20 mux_tree_tapbuf_size16_3_sram[2]:20 0.0005318346 +21 mux_tree_tapbuf_size16_3_sram[2]:21 0.0006547076 +22 mux_tree_tapbuf_size16_3_sram[2]:22 0.0004610898 +23 mux_tree_tapbuf_size16_3_sram[2]:23 0.0004610898 +24 mux_tree_tapbuf_size16_3_sram[2]:24 0.0001103237 +25 mux_tree_tapbuf_size16_3_sram[2]:25 0.001835486 +26 mux_tree_tapbuf_size16_3_sram[2]:26 0.001835486 +27 mux_tree_tapbuf_size16_3_sram[2]:27 9.58641e-05 +28 mux_tree_tapbuf_size16_3_sram[2]:28 4.098916e-05 +29 mux_tree_tapbuf_size16_3_sram[2]:29 6.606129e-05 +30 mux_tree_tapbuf_size16_3_sram[2]:30 6.606129e-05 +31 mux_tree_tapbuf_size16_3_sram[2]:25 chanx_left_in[14]:28 0.0003189166 +32 mux_tree_tapbuf_size16_3_sram[2]:25 chanx_left_in[14]:29 2.134297e-05 +33 mux_tree_tapbuf_size16_3_sram[2]:26 chanx_left_in[14]:10 0.0003189166 +34 mux_tree_tapbuf_size16_3_sram[2]:26 chanx_left_in[14]:28 2.134297e-05 +35 mux_tree_tapbuf_size16_3_sram[2]:16 chanx_left_in[14]:31 3.338994e-05 +36 mux_tree_tapbuf_size16_3_sram[2]:17 chanx_left_in[14]:30 3.338994e-05 +37 mux_tree_tapbuf_size16_3_sram[2]:20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.000129355 +38 mux_tree_tapbuf_size16_3_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.340816e-05 +39 mux_tree_tapbuf_size16_3_sram[2]:21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.000129355 +40 mux_tree_tapbuf_size16_3_sram[2]:21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.906191e-05 +41 mux_tree_tapbuf_size16_3_sram[2]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.906191e-05 +42 mux_tree_tapbuf_size16_3_sram[2]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.340816e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size16_3_sram[2]:30 0.152 +1 mux_tree_tapbuf_size16_3_sram[2]:20 mux_left_track_5\/mux_l3_in_2_:S 0.152 +2 mux_tree_tapbuf_size16_3_sram[2]:20 mux_tree_tapbuf_size16_3_sram[2]:19 0.0045 +3 mux_tree_tapbuf_size16_3_sram[2]:8 mux_left_track_5\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size16_3_sram[2]:21 mux_tree_tapbuf_size16_3_sram[2]:20 0.008091519 +5 mux_tree_tapbuf_size16_3_sram[2]:21 mux_tree_tapbuf_size16_3_sram[2]:9 0.001321429 +6 mux_tree_tapbuf_size16_3_sram[2]:22 mux_tree_tapbuf_size16_3_sram[2]:21 0.0045 +7 mux_tree_tapbuf_size16_3_sram[2]:23 mux_tree_tapbuf_size16_3_sram[2]:22 0.00597991 +8 mux_tree_tapbuf_size16_3_sram[2]:24 mux_tree_tapbuf_size16_3_sram[2]:23 0.00341 +9 mux_tree_tapbuf_size16_3_sram[2]:24 mux_tree_tapbuf_size16_3_sram[2]:7 5.69697e-05 +10 mux_tree_tapbuf_size16_3_sram[2]:25 mux_tree_tapbuf_size16_3_sram[2]:24 0.00341 +11 mux_tree_tapbuf_size16_3_sram[2]:27 mux_tree_tapbuf_size16_3_sram[2]:26 0.00341 +12 mux_tree_tapbuf_size16_3_sram[2]:27 mux_tree_tapbuf_size16_3_sram[2]:6 0.0001039141 +13 mux_tree_tapbuf_size16_3_sram[2]:26 mux_tree_tapbuf_size16_3_sram[2]:25 0.005377583 +14 mux_tree_tapbuf_size16_3_sram[2]:28 mux_tree_tapbuf_size16_3_sram[2]:27 0.00341 +15 mux_tree_tapbuf_size16_3_sram[2]:29 mux_tree_tapbuf_size16_3_sram[2]:28 0.0045 +16 mux_tree_tapbuf_size16_3_sram[2]:30 mux_tree_tapbuf_size16_3_sram[2]:29 0.000609375 +17 mux_tree_tapbuf_size16_3_sram[2]:13 mux_tree_tapbuf_size16_3_sram[2]:12 0.0003035715 +18 mux_tree_tapbuf_size16_3_sram[2]:13 mux_tree_tapbuf_size16_3_sram[2]:10 0.003341518 +19 mux_tree_tapbuf_size16_3_sram[2]:14 mux_tree_tapbuf_size16_3_sram[2]:13 0.0045 +20 mux_tree_tapbuf_size16_3_sram[2]:15 mux_tree_tapbuf_size16_3_sram[2]:14 0.001122768 +21 mux_tree_tapbuf_size16_3_sram[2]:16 mux_tree_tapbuf_size16_3_sram[2]:15 0.00341 +22 mux_tree_tapbuf_size16_3_sram[2]:18 mux_tree_tapbuf_size16_3_sram[2]:17 0.00341 +23 mux_tree_tapbuf_size16_3_sram[2]:17 mux_tree_tapbuf_size16_3_sram[2]:16 0.00172725 +24 mux_tree_tapbuf_size16_3_sram[2]:19 mux_tree_tapbuf_size16_3_sram[2]:18 0.005372767 +25 mux_tree_tapbuf_size16_3_sram[2]:10 mux_left_track_5\/mux_l3_in_3_:S 0.152 +26 mux_tree_tapbuf_size16_3_sram[2]:9 mux_left_track_5\/mux_l3_in_1_:S 0.152 +27 mux_tree_tapbuf_size16_3_sram[2]:9 mux_tree_tapbuf_size16_3_sram[2]:8 0.004073661 +28 mux_tree_tapbuf_size16_3_sram[2]:11 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +29 mux_tree_tapbuf_size16_3_sram[2]:12 mux_tree_tapbuf_size16_3_sram[2]:11 0.003917411 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[0] 0.005748461 //LENGTH 41.355 LUMPCC 0.0006112569 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.565 64.260 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 13.515 75.140 +*I mux_left_track_33\/mux_l1_in_3_:S I *L 0.00357 *C 23.920 74.625 +*I mux_left_track_33\/mux_l1_in_1_:S I *L 0.00357 *C 25.420 69.020 +*I mux_left_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 25.400 77.520 +*I mux_left_track_33\/mux_l1_in_2_:S I *L 0.00357 *C 27.720 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:6 *C 27.683 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:7 *C 25.300 77.520 +*N mux_tree_tapbuf_size7_3_sram[0]:8 *C 25.300 77.475 +*N mux_tree_tapbuf_size7_3_sram[0]:9 *C 25.300 69.020 +*N mux_tree_tapbuf_size7_3_sram[0]:10 *C 25.300 69.065 +*N mux_tree_tapbuf_size7_3_sram[0]:11 *C 25.300 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:12 *C 25.760 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:13 *C 25.760 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:14 *C 23.920 74.120 +*N mux_tree_tapbuf_size7_3_sram[0]:15 *C 23.920 74.603 +*N mux_tree_tapbuf_size7_3_sram[0]:16 *C 23.555 74.800 +*N mux_tree_tapbuf_size7_3_sram[0]:17 *C 23.105 74.800 +*N mux_tree_tapbuf_size7_3_sram[0]:18 *C 18.860 74.800 +*N mux_tree_tapbuf_size7_3_sram[0]:19 *C 18.860 75.140 +*N mux_tree_tapbuf_size7_3_sram[0]:20 *C 13.515 75.140 +*N mux_tree_tapbuf_size7_3_sram[0]:21 *C 12.925 75.140 +*N mux_tree_tapbuf_size7_3_sram[0]:22 *C 12.880 75.140 +*N mux_tree_tapbuf_size7_3_sram[0]:23 *C 11.960 75.140 +*N mux_tree_tapbuf_size7_3_sram[0]:24 *C 11.960 64.305 +*N mux_tree_tapbuf_size7_3_sram[0]:25 *C 12.005 64.260 +*N mux_tree_tapbuf_size7_3_sram[0]:26 *C 14.527 64.260 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_33\/mux_l1_in_3_:S 1e-06 +3 mux_left_track_33\/mux_l1_in_1_:S 1e-06 +4 mux_left_track_33\/mux_l1_in_0_:S 1e-06 +5 mux_left_track_33\/mux_l1_in_2_:S 1e-06 +6 mux_tree_tapbuf_size7_3_sram[0]:6 0.000143803 +7 mux_tree_tapbuf_size7_3_sram[0]:7 3.598051e-05 +8 mux_tree_tapbuf_size7_3_sram[0]:8 0.0002016146 +9 mux_tree_tapbuf_size7_3_sram[0]:9 3.567869e-05 +10 mux_tree_tapbuf_size7_3_sram[0]:10 0.0002786451 +11 mux_tree_tapbuf_size7_3_sram[0]:11 0.0005162795 +12 mux_tree_tapbuf_size7_3_sram[0]:12 7.044882e-05 +13 mux_tree_tapbuf_size7_3_sram[0]:13 0.0003140149 +14 mux_tree_tapbuf_size7_3_sram[0]:14 0.0001736635 +15 mux_tree_tapbuf_size7_3_sram[0]:15 7.987661e-05 +16 mux_tree_tapbuf_size7_3_sram[0]:16 9.225038e-05 +17 mux_tree_tapbuf_size7_3_sram[0]:17 0.0004447043 +18 mux_tree_tapbuf_size7_3_sram[0]:18 0.0004198314 +19 mux_tree_tapbuf_size7_3_sram[0]:19 0.0002588301 +20 mux_tree_tapbuf_size7_3_sram[0]:20 0.0003055441 +21 mux_tree_tapbuf_size7_3_sram[0]:21 4.22538e-05 +22 mux_tree_tapbuf_size7_3_sram[0]:22 9.100079e-05 +23 mux_tree_tapbuf_size7_3_sram[0]:23 0.0006753884 +24 mux_tree_tapbuf_size7_3_sram[0]:24 0.0006170413 +25 mux_tree_tapbuf_size7_3_sram[0]:25 0.0001671773 +26 mux_tree_tapbuf_size7_3_sram[0]:26 0.0001671773 +27 mux_tree_tapbuf_size7_3_sram[0]:21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 2.894998e-05 +28 mux_tree_tapbuf_size7_3_sram[0]:20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002009851 +29 mux_tree_tapbuf_size7_3_sram[0]:20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 2.894998e-05 +30 mux_tree_tapbuf_size7_3_sram[0]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.747357e-06 +31 mux_tree_tapbuf_size7_3_sram[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.747357e-06 +32 mux_tree_tapbuf_size7_3_sram[0]:15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.656644e-07 +33 mux_tree_tapbuf_size7_3_sram[0]:19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002009851 +34 mux_tree_tapbuf_size7_3_sram[0]:18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.149127e-07 +35 mux_tree_tapbuf_size7_3_sram[0]:17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.770855e-07 +36 mux_tree_tapbuf_size7_3_sram[0]:17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.149127e-07 +37 mux_tree_tapbuf_size7_3_sram[0]:16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.656644e-07 +38 mux_tree_tapbuf_size7_3_sram[0]:16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.770855e-07 +39 mux_tree_tapbuf_size7_3_sram[0]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.622223e-05 +40 mux_tree_tapbuf_size7_3_sram[0]:13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.044071e-05 +41 mux_tree_tapbuf_size7_3_sram[0]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.242533e-05 +42 mux_tree_tapbuf_size7_3_sram[0]:14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.044071e-05 +43 mux_tree_tapbuf_size7_3_sram[0]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.622223e-05 +44 mux_tree_tapbuf_size7_3_sram[0]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.242533e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_3_sram[0]:26 0.152 +1 mux_tree_tapbuf_size7_3_sram[0]:26 mux_tree_tapbuf_size7_3_sram[0]:25 0.002252232 +2 mux_tree_tapbuf_size7_3_sram[0]:25 mux_tree_tapbuf_size7_3_sram[0]:24 0.0045 +3 mux_tree_tapbuf_size7_3_sram[0]:24 mux_tree_tapbuf_size7_3_sram[0]:23 0.009674108 +4 mux_tree_tapbuf_size7_3_sram[0]:21 mux_tree_tapbuf_size7_3_sram[0]:20 0.0005267857 +5 mux_tree_tapbuf_size7_3_sram[0]:22 mux_tree_tapbuf_size7_3_sram[0]:21 0.0045 +6 mux_tree_tapbuf_size7_3_sram[0]:9 mux_left_track_33\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size7_3_sram[0]:10 mux_tree_tapbuf_size7_3_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size7_3_sram[0]:20 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size7_3_sram[0]:20 mux_tree_tapbuf_size7_3_sram[0]:19 0.004772321 +10 mux_tree_tapbuf_size7_3_sram[0]:13 mux_tree_tapbuf_size7_3_sram[0]:12 0.0045 +11 mux_tree_tapbuf_size7_3_sram[0]:13 mux_tree_tapbuf_size7_3_sram[0]:6 0.001716518 +12 mux_tree_tapbuf_size7_3_sram[0]:12 mux_tree_tapbuf_size7_3_sram[0]:11 0.0004107143 +13 mux_tree_tapbuf_size7_3_sram[0]:6 mux_left_track_33\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size7_3_sram[0]:7 mux_left_track_33\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size7_3_sram[0]:8 mux_tree_tapbuf_size7_3_sram[0]:7 0.0045 +16 mux_tree_tapbuf_size7_3_sram[0]:15 mux_left_track_33\/mux_l1_in_3_:S 0.152 +17 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:14 0.0004308036 +18 mux_tree_tapbuf_size7_3_sram[0]:19 mux_tree_tapbuf_size7_3_sram[0]:18 0.0003035715 +19 mux_tree_tapbuf_size7_3_sram[0]:18 mux_tree_tapbuf_size7_3_sram[0]:17 0.003790179 +20 mux_tree_tapbuf_size7_3_sram[0]:17 mux_tree_tapbuf_size7_3_sram[0]:16 0.00028125 +21 mux_tree_tapbuf_size7_3_sram[0]:16 mux_tree_tapbuf_size7_3_sram[0]:15 0.0003258929 +22 mux_tree_tapbuf_size7_3_sram[0]:14 mux_tree_tapbuf_size7_3_sram[0]:13 0.001642857 +23 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:22 0.0008214285 +24 mux_tree_tapbuf_size7_3_sram[0]:11 mux_tree_tapbuf_size7_3_sram[0]:10 0.004513393 +25 mux_tree_tapbuf_size7_3_sram[0]:11 mux_tree_tapbuf_size7_3_sram[0]:8 0.002995536 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001934842 //LENGTH 14.935 LUMPCC 0.0006137049 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_0_:X O *L 0 *C 54.455 99.620 +*I mux_top_track_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 53.920 112.540 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 53.958 112.540 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 54.280 112.540 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 54.280 112.200 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 54.695 112.200 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 54.740 112.155 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 54.740 99.665 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 54.740 99.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 54.455 99.620 + +*CAP +0 mux_top_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.24123e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 6.683121e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.665795e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.223903e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0004923627 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004923627 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:8 5.794925e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:9 5.832229e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_top_in[14]:27 9.920954e-06 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_top_in[14]:29 0.0002969315 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_top_in[14]:26 9.920954e-06 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_top_in[14]:28 0.0002969315 + +*RES +0 mux_top_track_2\/mux_l3_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_2\/mux_l4_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003705357 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.01115179 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001548913 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0002879465 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0003035715 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000420318 //LENGTH 2.940 LUMPCC 8.320282e-05 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_3_:X O *L 0 *C 112.985 96.900 +*I mux_right_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 115.635 96.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 115.598 96.900 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 113.023 96.900 + +*CAP +0 mux_right_track_2\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001675576 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001675576 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size12_3_sram[0]:12 4.160141e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size12_3_sram[0]:13 4.160141e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_3_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_2\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002299107 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0036064 //LENGTH 31.470 LUMPCC 0.0005098557 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_1_:X O *L 0 *C 86.765 58.140 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 87.575 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 87.575 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 87.400 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 87.400 28.265 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 87.400 58.095 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 87.355 58.140 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 86.803 58.140 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.306809e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.691831e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001433243 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001433243 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.903613e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.903613e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_4_sram[1]:25 8.362964e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_4_sram[1]:26 8.362964e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size12_4_sram[0]:28 0.0001138527 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size12_4_sram[0]:32 8.214543e-06 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size12_4_sram[0]:29 0.0001138527 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size12_4_sram[0]:31 8.214543e-06 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 4.923092e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.923092e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.02663393 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007120327 //LENGTH 5.785 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_1_:X O *L 0 *C 63.305 22.440 +*I mux_bottom_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 64.690 20.740 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 64.653 20.740 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 63.480 20.740 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 63.480 21.080 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 62.605 21.080 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 62.560 21.125 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 62.560 22.395 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 62.605 22.440 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 63.268 22.440 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.379389e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001094935 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001039458 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.824616e-05 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.643581e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 9.643581e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.084086e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.084086e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0007812501 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001133929 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0005915178 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003035715 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001046875 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.003659385 //LENGTH 26.115 LUMPCC 0.001049393 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_1_:X O *L 0 *C 66.415 85.680 +*I mux_left_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 44.910 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 44.948 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 45.955 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 46.000 82.325 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 46.000 85.295 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 46.045 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 51.980 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 51.980 85.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 66.377 85.680 + +*CAP +0 mux_left_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001062227 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001062227 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001340195 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001340195 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002848491 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003097815 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0007789053 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0007539728 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[13]:28 8.507335e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[13]:27 8.507335e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[14]:26 2.207165e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[14]:27 1.031935e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[14]:32 6.365735e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[14]:35 7.823912e-06 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[14]:25 2.207165e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[14]:28 1.031935e-05 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[14]:31 6.365735e-05 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_bottom_in[14]:34 7.823912e-06 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 left_top_grid_pin_42_[0]:13 8.463433e-05 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 left_top_grid_pin_42_[0]:16 8.463433e-05 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size16_0_sram[1]:14 5.81005e-05 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_tree_tapbuf_size16_0_sram[1]:13 2.548798e-05 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size16_0_sram[1]:13 5.81005e-05 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_tree_tapbuf_size16_0_sram[1]:14 2.548798e-05 +26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.489875e-05 +27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.26291e-05 +28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 8.489875e-05 +29 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.26291e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0008995536 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002651786 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.01285491 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.005299107 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003035715 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0] 0.005719085 //LENGTH 43.930 LUMPCC 0.0007543155 DR + +*CONN +*I mux_top_track_4\/mux_l5_in_0_:X O *L 0 *C 46.285 113.220 +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 70.650 118.475 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 *C 70.623 118.498 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 *C 70.380 118.510 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 *C 70.380 119.000 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 *C 70.380 119.045 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 *C 70.380 124.395 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 *C 70.335 124.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 *C 51.565 124.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 *C 51.520 124.395 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:10 *C 51.520 123.818 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 *C 51.513 123.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 *C 47.388 123.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 *C 47.380 123.703 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 *C 47.380 113.265 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:15 *C 47.335 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:16 *C 46.323 113.220 + +*CAP +0 mux_top_track_4\/mux_l5_in_0_:X 1e-06 +1 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 3.530518e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 7.422865e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 7.265757e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.000223513 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.000223513 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.001263969 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 0.001263969 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 6.713902e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:10 6.713902e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 0.0002151944 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 0.0002151944 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 0.0005449349 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 0.0005449349 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:15 7.553927e-05 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:16 7.553927e-05 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 chany_bottom_in[12]:9 0.0001440064 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 chany_bottom_in[12]:10 0.0001440064 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 top_left_grid_pin_37_[0]:11 1.709116e-05 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 top_left_grid_pin_37_[0]:12 1.709116e-05 +21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 top_left_grid_pin_37_[0]:14 0.0001479363 +22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 top_left_grid_pin_37_[0]:13 0.0001479363 +23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 ropt_net_221:2 5.112347e-05 +24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 ropt_net_221:3 5.112347e-05 +25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 ropt_net_221:5 1.700049e-05 +26 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 ropt_net_221:6 1.700049e-05 + +*RES +0 mux_top_track_4\/mux_l5_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:16 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:15 0.0009040179 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 0.009319197 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 0.00341 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 0.00064625 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 0.000515625 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:10 0.00341 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.01675893 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 0.0045 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.0045 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.004776786 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0004375 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.0045 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.0001638514 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001449991 //LENGTH 12.300 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_0_:X O *L 0 *C 118.965 82.280 +*I mux_right_track_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 122.920 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 122.820 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 122.820 74.505 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 122.820 82.235 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 122.775 82.280 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 119.003 82.280 + +*CAP +0 mux_right_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.300817e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0004352556 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0004352556 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002722356 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002722356 + +*RES +0 mux_right_track_4\/mux_l3_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_4\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.006901786 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.003368304 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007233592 //LENGTH 4.820 LUMPCC 0.0002518172 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_5_:X O *L 0 *C 35.705 14.960 +*I mux_bottom_track_5\/mux_l3_in_2_:A0 I *L 0.001631 *C 34.675 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 34.675 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 35.375 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 35.420 11.945 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 35.420 14.915 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 35.420 14.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 35.705 14.960 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_5_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_2_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.669462e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.798773e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001121382 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001121382 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 4.995808e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.06252e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size16_2_sram[1]:40 2.084804e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size16_2_sram[1]:41 6.686563e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size16_2_sram[1]:38 3.847633e-06 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size16_2_sram[1]:37 2.084804e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size16_2_sram[1]:40 6.686563e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:39 3.847633e-06 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.278122e-06 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.278122e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.706917e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.706917e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_5_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_5\/mux_l3_in_2_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000625 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002651786 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003361604 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_7_:X O *L 0 *C 17.195 93.500 +*I mux_left_track_5\/mux_l3_in_3_:A0 I *L 0.001631 *C 15.010 93.500 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 15.048 93.500 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 17.158 93.500 + +*CAP +0 mux_left_track_5\/mux_l2_in_7_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_3_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001670802 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001670802 + +*RES +0 mux_left_track_5\/mux_l2_in_7_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_5\/mux_l3_in_3_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001883929 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0009200489 //LENGTH 7.220 LUMPCC 0.0002277009 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_1_:X O *L 0 *C 111.495 42.840 +*I mux_top_track_8\/mux_l4_in_0_:A0 I *L 0.001631 *C 112.530 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 112.530 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 112.700 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 112.700 47.895 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 112.700 42.885 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 112.655 42.840 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 111.532 42.840 + +*CAP +0 mux_top_track_8\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.048831e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.396286e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002344284 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002344284 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.852003e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.852003e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_0_sram[3]:4 4.900536e-06 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_0_sram[3]:5 4.900536e-06 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:6 5.774515e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[3]:7 5.774515e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.120477e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.120477e-05 + +*RES +0 mux_top_track_8\/mux_l3_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_8\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.239131e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.001002232 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002739861 //LENGTH 17.860 LUMPCC 0.000649049 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_2_:X O *L 0 *C 74.695 61.200 +*I mux_top_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 63.845 66.980 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.845 66.980 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 63.940 66.935 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 63.940 65.338 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 63.948 65.280 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 71.293 65.280 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 71.300 65.222 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 71.300 61.245 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 71.345 61.200 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 74.657 61.200 + +*CAP +0 mux_top_track_24\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.798839e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.649081e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.649081e-05 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004171338 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004171338 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002556131 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002556131 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0002711744 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0002711744 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[17]:26 0.0002022685 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[17]:25 1.354817e-08 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[17]:27 0.0002022685 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[17]:24 1.354817e-08 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_left_in[18]:22 7.050041e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_left_in[18]:21 7.050041e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.174199e-05 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.174199e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_2_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001426339 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00341 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00341 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001150717 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0045 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.003551339 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.002957589 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001958692 //LENGTH 14.525 LUMPCC 0.0004204906 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_2_:X O *L 0 *C 79.295 63.240 +*I mux_right_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 80.500 50.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 80.463 50.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 79.580 50.660 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 79.580 51.000 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 79.580 51.045 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 79.580 63.195 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 79.580 63.240 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 79.295 63.240 + +*CAP +0 mux_right_track_16\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.515133e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001148522 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.439513e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0005771844 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005771844 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.969232e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.774142e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[6]:24 9.535351e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[6]:23 9.535351e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001148918 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001148918 + +*RES +0 mux_right_track_16\/mux_l1_in_2_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_16\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.01084821 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001548913 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0007879465 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005084391 //LENGTH 3.860 LUMPCC 0.0001381357 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_3_:X O *L 0 *C 99.185 75.140 +*I mux_right_track_24\/mux_l3_in_1_:A0 I *L 0.001631 *C 102.755 75.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 102.718 75.140 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 99.223 75.140 + +*CAP +0 mux_right_track_24\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001841518 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001841518 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_5_sram[2]:11 6.906785e-05 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_5_sram[2]:12 6.906785e-05 + +*RES +0 mux_right_track_24\/mux_l2_in_3_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_24\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.003120536 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000959118 //LENGTH 7.275 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_2_:X O *L 0 *C 97.235 33.320 +*I mux_bottom_track_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 99.460 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 99.422 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 97.565 28.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 97.520 28.945 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 97.520 33.275 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 97.520 33.320 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 97.235 33.320 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000148244 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000148244 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002702835 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002702835 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.040031e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.966259e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_2_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_9\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001658482 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003866072 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0] 0.000960725 //LENGTH 8.110 LUMPCC 0.0001026939 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_3_:X O *L 0 *C 47.095 41.480 +*I mux_bottom_track_17\/mux_l3_in_1_:A0 I *L 0.001631 *C 44.335 37.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 44.373 37.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 46.415 37.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 46.460 37.105 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 46.460 41.435 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 46.505 41.480 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 47.058 41.480 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001237509 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001237509 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002267643 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002267643 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.750037e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.750037e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.57671e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.57671e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.557987e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.557987e-05 + +*RES +0 mux_bottom_track_17\/mux_l2_in_3_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_17\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001823661 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003866071 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001862723 //LENGTH 13.590 LUMPCC 0.0004000778 DR + +*CONN +*I mux_bottom_track_25\/mux_l3_in_1_:X O *L 0 *C 34.785 52.360 +*I mux_bottom_track_25\/mux_l4_in_0_:A0 I *L 0.001631 *C 39.735 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 39.735 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 39.560 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 37.305 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 37.260 44.925 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 37.260 52.315 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 37.215 52.360 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 34.823 52.360 + +*CAP +0 mux_bottom_track_25\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.81608e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.000155901 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001295214 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0003736281 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0003736281 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001849027 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0001849027 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chanx_right_in[10]:26 0.000111104 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 chanx_right_in[10]:24 1.569924e-05 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 chanx_right_in[10]:25 0.000111104 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 chanx_right_in[10]:23 1.569924e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_8_sram[3]:4 7.323569e-05 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_8_sram[3]:3 7.323569e-05 + +*RES +0 mux_bottom_track_25\/mux_l3_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_25\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.002013393 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.006598215 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.002136161 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0003035714 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001483242 //LENGTH 10.975 LUMPCC 0.00041465 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_2_:X O *L 0 *C 26.855 69.020 +*I mux_left_track_17\/mux_l3_in_1_:A1 I *L 0.00198 *C 28.620 61.540 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 28.583 61.540 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 28.105 61.540 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 28.060 61.585 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 28.060 64.215 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 28.015 64.260 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 26.725 64.260 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 26.680 64.305 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 26.680 68.975 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 26.680 69.020 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 26.855 69.020 + +*CAP +0 mux_left_track_17\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.066715e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.066715e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001035718 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001035718 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.851513e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.851513e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.00023969 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.00023969 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 5.313435e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 4.856905e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[10]:22 1.7264e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[10]:20 2.838833e-05 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[10]:21 1.7264e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[10]:19 2.838833e-05 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chanx_right_in[10]:18 1.093875e-05 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chanx_right_in[10]:17 1.093875e-05 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size10_10_sram[1]:12 2.79968e-05 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size10_10_sram[1]:11 2.79968e-05 +20 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size10_10_sram[1]:9 2.022342e-05 +21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size10_10_sram[1]:10 1.777227e-05 +22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size10_10_sram[1]:7 2.022342e-05 +23 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size10_10_sram[1]:9 1.777227e-05 +24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.167818e-06 +25 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.167818e-06 +26 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.930653e-05 +27 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.930653e-05 +28 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.267085e-06 +29 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.267085e-06 + +*RES +0 mux_left_track_17\/mux_l2_in_2_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_17\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004263392 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001151786 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.004169643 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.004237946 //LENGTH 27.925 LUMPCC 0.001267236 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_0_:X O *L 0 *C 73.885 76.840 +*I mux_right_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 94.860 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 94.823 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 93.840 72.420 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 93.840 72.080 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 91.585 72.080 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 91.540 72.125 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 91.540 74.075 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 91.495 74.120 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 74.565 74.120 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 74.520 74.165 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 74.520 76.795 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 74.475 76.840 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 73.922 76.840 + +*CAP +0 mux_right_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.200049e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000118117 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001749733 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001488567 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001561798 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001561798 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0007711245 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0007711245 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0002259153 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0002259153 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:12 6.416124e-05 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:13 6.416124e-05 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[2]:33 4.365035e-05 +15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[2]:36 5.61421e-05 +16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chanx_right_in[2]:34 4.365035e-05 +17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chanx_right_in[2]:35 5.61421e-05 +18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[5]:5 0.000111641 +19 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[5]:26 8.836913e-06 +20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[5]:6 0.000111641 +21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[5]:25 8.836913e-06 +22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size16_1_sram[1]:21 1.561159e-05 +23 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size16_1_sram[1]:22 0.000205036 +24 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size16_1_sram[1]:26 0.0001927001 +25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size16_1_sram[1]:20 1.561159e-05 +26 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size16_1_sram[1]:21 0.000205036 +27 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size16_1_sram[1]:25 0.0001927001 + +*RES +0 mux_right_track_32\/mux_l1_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002013393 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001741072 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.01511607 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0045 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002348214 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0004933035 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008772322 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001141267 //LENGTH 8.675 LUMPCC 0.0002957324 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_1_:X O *L 0 *C 14.895 71.400 +*I mux_left_track_33\/mux_l3_in_0_:A0 I *L 0.001631 *C 14.090 65.960 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 14.053 65.960 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 13.385 65.960 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 13.340 66.005 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 13.340 71.355 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 13.385 71.400 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 14.857 71.400 + +*CAP +0 mux_left_track_33\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.535055e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.535055e-05 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002318858 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002318858 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001245311 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001245311 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_right_in[18]:18 0.0001434545 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[18]:16 4.411676e-06 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_right_in[18]:17 0.0001434545 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[18]:15 4.411676e-06 + +*RES +0 mux_left_track_33\/mux_l2_in_1_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0005959821 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004776786 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001314732 + +*END + +*D_NET chanx_right_out[4] 0.001087249 //LENGTH 6.905 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 134.055 79.900 +*P chanx_right_out[4] O *L 0.7423 *C 140.450 80.240 +*N chanx_right_out[4]:2 *C 134.328 80.240 +*N chanx_right_out[4]:3 *C 134.320 80.240 +*N chanx_right_out[4]:4 *C 134.320 79.900 +*N chanx_right_out[4]:5 *C 134.320 79.900 +*N chanx_right_out[4]:6 *C 134.055 79.900 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 chanx_right_out[4] 0.0004363765 +2 chanx_right_out[4]:2 0.0004363765 +3 chanx_right_out[4]:3 5.646664e-05 +4 chanx_right_out[4]:4 5.271648e-05 +5 chanx_right_out[4]:5 5.247528e-05 +6 chanx_right_out[4]:6 5.183729e-05 + +*RES +0 ropt_mt_inst_791:X chanx_right_out[4]:6 0.152 +1 chanx_right_out[4]:6 chanx_right_out[4]:5 0.0001440218 +2 chanx_right_out[4]:5 chanx_right_out[4]:4 0.0045 +3 chanx_right_out[4]:4 chanx_right_out[4]:3 0.0001634615 +4 chanx_right_out[4]:3 chanx_right_out[4]:2 0.00341 +5 chanx_right_out[4]:2 chanx_right_out[4] 0.0009591916 + +*END + +*D_NET ropt_net_240 0.0006176023 //LENGTH 4.440 LUMPCC 0.0001373305 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 4.140 56.100 +*I ropt_mt_inst_894:A I *L 0.001766 *C 7.820 55.760 +*N ropt_net_240:2 *C 7.783 55.760 +*N ropt_net_240:3 *C 4.140 55.760 +*N ropt_net_240:4 *C 4.140 56.100 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 ropt_mt_inst_894:A 1e-06 +2 ropt_net_240:2 0.0001991165 +3 ropt_net_240:3 0.0002255895 +4 ropt_net_240:4 5.356578e-05 +5 ropt_net_240:2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 6.866527e-05 +6 ropt_net_240:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 6.866527e-05 + +*RES +0 ropt_mt_inst_798:X ropt_net_240:4 0.152 +1 ropt_net_240:2 ropt_mt_inst_894:A 0.152 +2 ropt_net_240:4 ropt_net_240:3 0.0003035715 +3 ropt_net_240:3 ropt_net_240:2 0.003252232 + +*END + +*D_NET chany_bottom_out[6] 0.001702225 //LENGTH 12.590 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_848:X O *L 0 *C 82.995 4.760 +*P chany_bottom_out[6] O *L 0.7423 *C 74.980 1.290 +*N chany_bottom_out[6]:2 *C 74.980 1.995 +*N chany_bottom_out[6]:3 *C 75.025 2.040 +*N chany_bottom_out[6]:4 *C 79.995 2.040 +*N chany_bottom_out[6]:5 *C 80.040 2.085 +*N chany_bottom_out[6]:6 *C 80.040 4.715 +*N chany_bottom_out[6]:7 *C 80.085 4.760 +*N chany_bottom_out[6]:8 *C 82.958 4.760 + +*CAP +0 ropt_mt_inst_848:X 1e-06 +1 chany_bottom_out[6] 6.308116e-05 +2 chany_bottom_out[6]:2 6.308116e-05 +3 chany_bottom_out[6]:3 0.0003542438 +4 chany_bottom_out[6]:4 0.0003542438 +5 chany_bottom_out[6]:5 0.0002059204 +6 chany_bottom_out[6]:6 0.0002059204 +7 chany_bottom_out[6]:7 0.0002273672 +8 chany_bottom_out[6]:8 0.0002273672 + +*RES +0 ropt_mt_inst_848:X chany_bottom_out[6]:8 0.152 +1 chany_bottom_out[6]:8 chany_bottom_out[6]:7 0.002564732 +2 chany_bottom_out[6]:7 chany_bottom_out[6]:6 0.0045 +3 chany_bottom_out[6]:6 chany_bottom_out[6]:5 0.002348214 +4 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.0044375 +5 chany_bottom_out[6]:5 chany_bottom_out[6]:4 0.0045 +6 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +7 chany_bottom_out[6]:2 chany_bottom_out[6] 0.0006294643 + +*END + +*D_NET chany_top_out[6] 0.0008142899 //LENGTH 5.910 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_854:X O *L 0 *C 72.415 126.140 +*P chany_top_out[6] O *L 0.7423 *C 70.380 129.270 +*N chany_top_out[6]:2 *C 70.380 127.160 +*N chany_top_out[6]:3 *C 70.840 127.160 +*N chany_top_out[6]:4 *C 70.840 126.185 +*N chany_top_out[6]:5 *C 70.885 126.140 +*N chany_top_out[6]:6 *C 72.377 126.140 + +*CAP +0 ropt_mt_inst_854:X 1e-06 +1 chany_top_out[6] 0.0001399906 +2 chany_top_out[6]:2 0.0001690927 +3 chany_top_out[6]:3 0.0001114342 +4 chany_top_out[6]:4 8.233204e-05 +5 chany_top_out[6]:5 0.0001552202 +6 chany_top_out[6]:6 0.0001552202 + +*RES +0 ropt_mt_inst_854:X chany_top_out[6]:6 0.152 +1 chany_top_out[6]:6 chany_top_out[6]:5 0.001332589 +2 chany_top_out[6]:5 chany_top_out[6]:4 0.0045 +3 chany_top_out[6]:4 chany_top_out[6]:3 0.0008705358 +4 chany_top_out[6]:2 chany_top_out[6] 0.001883929 +5 chany_top_out[6]:3 chany_top_out[6]:2 0.0004107143 + +*END + +*D_NET chanx_left_out[17] 0.0005494905 //LENGTH 4.100 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_858:X O *L 0 *C 4.140 87.720 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 88.400 +*N chanx_left_out[17]:2 *C 4.133 88.400 +*N chanx_left_out[17]:3 *C 4.140 88.343 +*N chanx_left_out[17]:4 *C 4.140 87.765 +*N chanx_left_out[17]:5 *C 4.140 87.720 + +*CAP +0 ropt_mt_inst_858:X 1e-06 +1 chanx_left_out[17] 0.0001987422 +2 chanx_left_out[17]:2 0.0001987422 +3 chanx_left_out[17]:3 5.982752e-05 +4 chanx_left_out[17]:4 5.982752e-05 +5 chanx_left_out[17]:5 3.135116e-05 + +*RES +0 ropt_mt_inst_858:X chanx_left_out[17]:5 0.152 +1 chanx_left_out[17]:5 chanx_left_out[17]:4 0.0045 +2 chanx_left_out[17]:4 chanx_left_out[17]:3 0.0005156249 +3 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +4 chanx_left_out[17]:2 chanx_left_out[17] 0.0004547249 + +*END + +*D_NET ropt_net_211 0.00119317 //LENGTH 9.355 LUMPCC 0.0002270146 DR + +*CONN +*I ropt_mt_inst_829:X O *L 0 *C 7.090 57.800 +*I ropt_mt_inst_851:A I *L 0.001767 *C 3.220 53.040 +*N ropt_net_211:2 *C 3.258 53.040 +*N ropt_net_211:3 *C 6.855 53.040 +*N ropt_net_211:4 *C 6.900 53.085 +*N ropt_net_211:5 *C 6.900 57.755 +*N ropt_net_211:6 *C 6.900 57.800 +*N ropt_net_211:7 *C 7.090 57.800 + +*CAP +0 ropt_mt_inst_829:X 1e-06 +1 ropt_mt_inst_851:A 1e-06 +2 ropt_net_211:2 0.0001437651 +3 ropt_net_211:3 0.0001437651 +4 ropt_net_211:4 0.0002770258 +5 ropt_net_211:5 0.0002770258 +6 ropt_net_211:6 5.978893e-05 +7 ropt_net_211:7 6.278469e-05 +8 ropt_net_211:3 ropt_net_190:6 6.779625e-05 +9 ropt_net_211:2 ropt_net_190:5 6.779625e-05 +10 ropt_net_211:3 chanx_left_out[10]:6 4.571107e-05 +11 ropt_net_211:2 chanx_left_out[10]:5 4.571107e-05 + +*RES +0 ropt_mt_inst_829:X ropt_net_211:7 0.152 +1 ropt_net_211:7 ropt_net_211:6 0.0001032609 +2 ropt_net_211:6 ropt_net_211:5 0.0045 +3 ropt_net_211:5 ropt_net_211:4 0.004169643 +4 ropt_net_211:3 ropt_net_211:2 0.003212054 +5 ropt_net_211:4 ropt_net_211:3 0.0045 +6 ropt_net_211:2 ropt_mt_inst_851:A 0.152 + +*END + +*D_NET ropt_net_184 0.0008473925 //LENGTH 7.180 LUMPCC 0 DR + +*CONN +*I BUFT_P_120:X O *L 0 *C 9.660 39.780 +*I ropt_mt_inst_823:A I *L 0.001766 *C 3.220 39.440 +*N ropt_net_184:2 *C 3.220 39.440 +*N ropt_net_184:3 *C 3.220 39.780 +*N ropt_net_184:4 *C 9.623 39.780 + +*CAP +0 BUFT_P_120:X 1e-06 +1 ropt_mt_inst_823:A 1e-06 +2 ropt_net_184:2 5.005402e-05 +3 ropt_net_184:3 0.0004100628 +4 ropt_net_184:4 0.0003852757 + +*RES +0 BUFT_P_120:X ropt_net_184:4 0.152 +1 ropt_net_184:4 ropt_net_184:3 0.005716518 +2 ropt_net_184:2 ropt_mt_inst_823:A 0.152 +3 ropt_net_184:3 ropt_net_184:2 0.0003035715 + +*END + +*D_NET ropt_net_189 0.0007614311 //LENGTH 6.260 LUMPCC 9.708235e-05 DR + +*CONN +*I BUFT_P_131:X O *L 0 *C 93.380 7.140 +*I ropt_mt_inst_828:A I *L 0.001766 *C 98.900 6.800 +*N ropt_net_189:2 *C 98.900 6.800 +*N ropt_net_189:3 *C 98.900 7.140 +*N ropt_net_189:4 *C 93.418 7.140 + +*CAP +0 BUFT_P_131:X 1e-06 +1 ropt_mt_inst_828:A 1e-06 +2 ropt_net_189:2 5.951311e-05 +3 ropt_net_189:3 0.0003159143 +4 ropt_net_189:4 0.0002869213 +5 ropt_net_189:4 chany_bottom_out[10]:5 4.854117e-05 +6 ropt_net_189:3 chany_bottom_out[10]:6 4.854117e-05 + +*RES +0 BUFT_P_131:X ropt_net_189:4 0.152 +1 ropt_net_189:4 ropt_net_189:3 0.00489509 +2 ropt_net_189:2 ropt_mt_inst_828:A 0.152 +3 ropt_net_189:3 ropt_net_189:2 0.0003035715 + +*END + +*D_NET ropt_net_238 0.001314954 //LENGTH 9.780 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_844:X O *L 0 *C 82.995 8.840 +*I ropt_mt_inst_888:A I *L 0.001767 *C 74.520 9.520 +*N ropt_net_238:2 *C 74.520 9.520 +*N ropt_net_238:3 *C 74.520 9.475 +*N ropt_net_238:4 *C 74.520 8.885 +*N ropt_net_238:5 *C 74.565 8.840 +*N ropt_net_238:6 *C 82.958 8.840 + +*CAP +0 ropt_mt_inst_844:X 1e-06 +1 ropt_mt_inst_888:A 1e-06 +2 ropt_net_238:2 3.596271e-05 +3 ropt_net_238:3 5.731123e-05 +4 ropt_net_238:4 5.731123e-05 +5 ropt_net_238:5 0.0005811846 +6 ropt_net_238:6 0.0005811846 + +*RES +0 ropt_mt_inst_844:X ropt_net_238:6 0.152 +1 ropt_net_238:2 ropt_mt_inst_888:A 0.152 +2 ropt_net_238:3 ropt_net_238:2 0.0045 +3 ropt_net_238:5 ropt_net_238:4 0.0045 +4 ropt_net_238:4 ropt_net_238:3 0.0005267857 +5 ropt_net_238:6 ropt_net_238:5 0.007493304 + +*END + +*D_NET chanx_left_out[3] 0.003119475 //LENGTH 19.540 LUMPCC 0.0002965163 DR + +*CONN +*I ropt_mt_inst_883:X O *L 0 *C 11.500 79.560 +*P chanx_left_out[3] O *L 0.7423 *C 1.305 74.800 +*N chanx_left_out[3]:2 *C 1.380 74.120 +*N chanx_left_out[3]:3 *C 7.353 74.120 +*N chanx_left_out[3]:4 *C 7.360 74.178 +*N chanx_left_out[3]:5 *C 7.360 78.880 +*N chanx_left_out[3]:6 *C 7.368 78.880 +*N chanx_left_out[3]:7 *C 11.953 78.880 +*N chanx_left_out[3]:8 *C 11.960 78.938 +*N chanx_left_out[3]:9 *C 11.960 79.515 +*N chanx_left_out[3]:10 *C 11.915 79.560 +*N chanx_left_out[3]:11 *C 11.538 79.560 + +*CAP +0 ropt_mt_inst_883:X 1e-06 +1 chanx_left_out[3] 5.341349e-05 +2 chanx_left_out[3]:2 0.0005655311 +3 chanx_left_out[3]:3 0.0005121176 +4 chanx_left_out[3]:4 0.0002230126 +5 chanx_left_out[3]:5 0.0002589087 +6 chanx_left_out[3]:6 0.0004900999 +7 chanx_left_out[3]:7 0.0004900999 +8 chanx_left_out[3]:8 6.447865e-05 +9 chanx_left_out[3]:9 6.447865e-05 +10 chanx_left_out[3]:10 4.990883e-05 +11 chanx_left_out[3]:11 4.990883e-05 +12 chanx_left_out[3]:5 BUF_net_89:3 0.0001482582 +13 chanx_left_out[3]:4 BUF_net_89:4 0.0001482582 + +*RES +0 ropt_mt_inst_883:X chanx_left_out[3]:11 0.152 +1 chanx_left_out[3]:11 chanx_left_out[3]:10 0.0003370536 +2 chanx_left_out[3]:10 chanx_left_out[3]:9 0.0045 +3 chanx_left_out[3]:9 chanx_left_out[3]:8 0.000515625 +4 chanx_left_out[3]:8 chanx_left_out[3]:7 0.00341 +5 chanx_left_out[3]:7 chanx_left_out[3]:6 0.0007183166 +6 chanx_left_out[3]:5 chanx_left_out[3]:4 0.004198661 +7 chanx_left_out[3]:6 chanx_left_out[3]:5 0.00341 +8 chanx_left_out[3]:4 chanx_left_out[3]:3 0.00341 +9 chanx_left_out[3]:3 chanx_left_out[3]:2 0.0009356915 +10 chanx_left_out[3]:2 chanx_left_out[3] 0.0001065333 + +*END + +*D_NET chany_top_in[12] 0.02738051 //LENGTH 206.150 LUMPCC 0.005206653 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 52.900 129.270 +*I mux_left_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 80.865 83.300 +*I ropt_mt_inst_807:A I *L 0.001766 *C 67.620 6.800 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 79.295 26.180 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 81.135 98.600 +*N chany_top_in[12]:5 *C 81.135 98.600 +*N chany_top_in[12]:6 *C 80.960 98.600 +*N chany_top_in[12]:7 *C 80.560 98.600 +*N chany_top_in[12]:8 *C 79.295 26.180 +*N chany_top_in[12]:9 *C 67.657 6.800 +*N chany_top_in[12]:10 *C 68.035 6.800 +*N chany_top_in[12]:11 *C 68.080 6.755 +*N chany_top_in[12]:12 *C 68.080 4.805 +*N chany_top_in[12]:13 *C 68.125 4.760 +*N chany_top_in[12]:14 *C 74.980 4.760 +*N chany_top_in[12]:15 *C 74.980 4.420 +*N chany_top_in[12]:16 *C 79.535 4.420 +*N chany_top_in[12]:17 *C 79.580 4.465 +*N chany_top_in[12]:18 *C 79.580 26.135 +*N chany_top_in[12]:19 *C 79.580 26.180 +*N chany_top_in[12]:20 *C 79.580 26.520 +*N chany_top_in[12]:21 *C 95.635 26.520 +*N chany_top_in[12]:22 *C 95.680 26.565 +*N chany_top_in[12]:23 *C 95.680 80.195 +*N chany_top_in[12]:24 *C 95.635 80.240 +*N chany_top_in[12]:25 *C 92.920 80.240 +*N chany_top_in[12]:26 *C 92.920 80.580 +*N chany_top_in[12]:27 *C 81.925 80.580 +*N chany_top_in[12]:28 *C 81.880 80.625 +*N chany_top_in[12]:29 *C 80.903 83.300 +*N chany_top_in[12]:30 *C 81.835 83.300 +*N chany_top_in[12]:31 *C 81.880 83.300 +*N chany_top_in[12]:32 *C 81.880 86.303 +*N chany_top_in[12]:33 *C 81.873 86.360 +*N chany_top_in[12]:34 *C 80.980 86.360 +*N chany_top_in[12]:35 *C 80.960 86.368 +*N chany_top_in[12]:36 *C 80.960 98.593 +*N chany_top_in[12]:37 *C 80.960 98.600 +*N chany_top_in[12]:38 *C 80.960 98.600 +*N chany_top_in[12]:39 *C 80.960 101.955 +*N chany_top_in[12]:40 *C 80.915 102.000 +*N chany_top_in[12]:41 *C 79.165 102.000 +*N chany_top_in[12]:42 *C 79.120 102.045 +*N chany_top_in[12]:43 *C 79.120 123.023 +*N chany_top_in[12]:44 *C 79.112 123.080 +*N chany_top_in[12]:45 *C 52.908 123.080 +*N chany_top_in[12]:46 *C 52.900 123.138 + +*CAP +0 chany_top_in[12] 0.0003990459 +1 mux_left_track_1\/mux_l1_in_1_:A1 1e-06 +2 ropt_mt_inst_807:A 1e-06 +3 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +4 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +5 chany_top_in[12]:5 5.45454e-05 +6 chany_top_in[12]:6 5.808492e-05 +7 chany_top_in[12]:7 7.083983e-05 +8 chany_top_in[12]:8 3.526625e-05 +9 chany_top_in[12]:9 5.259802e-05 +10 chany_top_in[12]:10 5.259802e-05 +11 chany_top_in[12]:11 0.0001499325 +12 chany_top_in[12]:12 0.0001499325 +13 chany_top_in[12]:13 0.000464684 +14 chany_top_in[12]:14 0.0004922407 +15 chany_top_in[12]:15 0.0003714772 +16 chany_top_in[12]:16 0.0003439205 +17 chany_top_in[12]:17 0.000924335 +18 chany_top_in[12]:18 0.0009243351 +19 chany_top_in[12]:19 9.087403e-05 +20 chany_top_in[12]:20 0.001019819 +21 chany_top_in[12]:21 0.000989042 +22 chany_top_in[12]:22 0.002794923 +23 chany_top_in[12]:23 0.002794923 +24 chany_top_in[12]:24 0.0001586325 +25 chany_top_in[12]:25 0.0001844116 +26 chany_top_in[12]:26 0.0007809204 +27 chany_top_in[12]:27 0.0007551413 +28 chany_top_in[12]:28 0.0001160258 +29 chany_top_in[12]:29 0.0001242868 +30 chany_top_in[12]:30 0.0001242868 +31 chany_top_in[12]:31 0.0002747477 +32 chany_top_in[12]:32 0.0001263708 +33 chany_top_in[12]:33 0.0001072771 +34 chany_top_in[12]:34 0.0001072771 +35 chany_top_in[12]:35 0.0006511864 +36 chany_top_in[12]:36 0.0006511864 +37 chany_top_in[12]:37 7.083983e-05 +38 chany_top_in[12]:38 0.0002423252 +39 chany_top_in[12]:39 0.0002084447 +40 chany_top_in[12]:40 0.0001133582 +41 chany_top_in[12]:41 0.0001133582 +42 chany_top_in[12]:42 0.0008787448 +43 chany_top_in[12]:43 0.0008787448 +44 chany_top_in[12]:44 0.001434918 +45 chany_top_in[12]:45 0.001434918 +46 chany_top_in[12]:46 0.0003990459 +47 chany_top_in[12]:19 chany_top_in[2]:17 2.618177e-08 +48 chany_top_in[12]:18 chany_top_in[2]:18 8.733944e-06 +49 chany_top_in[12]:18 chany_top_in[2]:19 0.0004073959 +50 chany_top_in[12]:17 chany_top_in[2]:15 0.0004073959 +51 chany_top_in[12]:17 chany_top_in[2]:19 8.733944e-06 +52 chany_top_in[12]:13 chany_top_in[2]:9 1.726653e-05 +53 chany_top_in[12]:12 chany_top_in[2]:11 7.193657e-06 +54 chany_top_in[12]:11 chany_top_in[2]:12 7.193657e-06 +55 chany_top_in[12]:21 chany_top_in[2]:17 3.613084e-06 +56 chany_top_in[12]:8 chany_top_in[2]:16 2.618177e-08 +57 chany_top_in[12]:6 chany_top_in[2]:29 1.446515e-06 +58 chany_top_in[12]:5 chany_top_in[2]:28 1.446515e-06 +59 chany_top_in[12]:40 chany_top_in[2]:33 1.962716e-05 +60 chany_top_in[12]:41 chany_top_in[2]:32 1.962716e-05 +61 chany_top_in[12]:42 chany_top_in[2]:30 9.608717e-06 +62 chany_top_in[12]:43 chany_top_in[2]:31 9.608717e-06 +63 chany_top_in[12]:14 chany_top_in[2]:10 1.726653e-05 +64 chany_top_in[12]:20 chany_top_in[2]:16 3.613084e-06 +65 chany_top_in[12]:13 chany_top_in[17]:10 8.861263e-06 +66 chany_top_in[12]:36 chany_top_in[17]:33 0.0005249866 +67 chany_top_in[12]:35 chany_top_in[17]:32 0.0005249866 +68 chany_top_in[12]:14 chany_top_in[17]:9 8.861263e-06 +69 chany_top_in[12]:44 chany_bottom_in[17]:9 0.0004894931 +70 chany_top_in[12]:45 chany_bottom_in[17]:10 0.0004894931 +71 chany_top_in[12]:42 mux_tree_tapbuf_size12_0_sram[2]:13 2.794623e-05 +72 chany_top_in[12]:42 mux_tree_tapbuf_size12_0_sram[2]:5 7.817536e-05 +73 chany_top_in[12]:42 mux_tree_tapbuf_size12_0_sram[2]:8 8.484932e-05 +74 chany_top_in[12]:43 mux_tree_tapbuf_size12_0_sram[2]:9 8.484932e-05 +75 chany_top_in[12]:43 mux_tree_tapbuf_size12_0_sram[2]:14 2.794623e-05 +76 chany_top_in[12]:43 mux_tree_tapbuf_size12_0_sram[2]:8 7.817536e-05 +77 chany_top_in[12]:42 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0002140376 +78 chany_top_in[12]:43 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0002140376 +79 chany_top_in[12]:21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.000104489 +80 chany_top_in[12]:20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.000104489 +81 chany_top_in[12]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000143609 +82 chany_top_in[12]:23 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000143609 +83 chany_top_in[12]:24 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.496751e-05 +84 chany_top_in[12]:27 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.322771e-06 +85 chany_top_in[12]:26 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.322771e-06 +86 chany_top_in[12]:25 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.496751e-05 +87 chany_top_in[12]:28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 7.395214e-05 +88 chany_top_in[12]:38 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.215735e-06 +89 chany_top_in[12]:38 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.041409e-05 +90 chany_top_in[12]:32 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 8.343844e-05 +91 chany_top_in[12]:31 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:13 8.343844e-05 +92 chany_top_in[12]:31 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:12 7.395214e-05 +93 chany_top_in[12]:39 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.041409e-05 +94 chany_top_in[12]:39 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.215735e-06 +95 chany_top_in[12]:22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000130534 +96 chany_top_in[12]:23 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000130534 +97 chany_top_in[12]:18 ropt_net_200:5 9.355807e-07 +98 chany_top_in[12]:18 ropt_net_200:7 3.980342e-05 +99 chany_top_in[12]:16 ropt_net_200:9 3.21773e-05 +100 chany_top_in[12]:16 ropt_net_200:7 1.020631e-05 +101 chany_top_in[12]:17 ropt_net_200:8 3.980342e-05 +102 chany_top_in[12]:17 ropt_net_200:6 9.355807e-07 +103 chany_top_in[12]:15 ropt_net_200:10 3.21773e-05 +104 chany_top_in[12]:15 ropt_net_200:6 1.020631e-05 + +*RES +0 chany_top_in[12] chany_top_in[12]:46 0.005475447 +1 chany_top_in[12]:19 chany_top_in[12]:18 0.0045 +2 chany_top_in[12]:19 chany_top_in[12]:8 0.0001548913 +3 chany_top_in[12]:18 chany_top_in[12]:17 0.01934822 +4 chany_top_in[12]:16 chany_top_in[12]:15 0.004066965 +5 chany_top_in[12]:17 chany_top_in[12]:16 0.0045 +6 chany_top_in[12]:13 chany_top_in[12]:12 0.0045 +7 chany_top_in[12]:12 chany_top_in[12]:11 0.001741071 +8 chany_top_in[12]:10 chany_top_in[12]:9 0.0003370536 +9 chany_top_in[12]:11 chany_top_in[12]:10 0.0045 +10 chany_top_in[12]:9 ropt_mt_inst_807:A 0.152 +11 chany_top_in[12]:21 chany_top_in[12]:20 0.01433482 +12 chany_top_in[12]:22 chany_top_in[12]:21 0.0045 +13 chany_top_in[12]:24 chany_top_in[12]:23 0.0045 +14 chany_top_in[12]:23 chany_top_in[12]:22 0.04788394 +15 chany_top_in[12]:27 chany_top_in[12]:26 0.009816965 +16 chany_top_in[12]:28 chany_top_in[12]:27 0.0045 +17 chany_top_in[12]:38 chany_top_in[12]:37 0.00341 +18 chany_top_in[12]:38 chany_top_in[12]:6 0.0045 +19 chany_top_in[12]:37 chany_top_in[12]:36 0.00341 +20 chany_top_in[12]:37 chany_top_in[12]:7 5.69697e-05 +21 chany_top_in[12]:36 chany_top_in[12]:35 0.00191525 +22 chany_top_in[12]:34 chany_top_in[12]:33 0.000139825 +23 chany_top_in[12]:35 chany_top_in[12]:34 0.00341 +24 chany_top_in[12]:32 chany_top_in[12]:31 0.002680804 +25 chany_top_in[12]:33 chany_top_in[12]:32 0.00341 +26 chany_top_in[12]:8 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +27 chany_top_in[12]:6 chany_top_in[12]:5 9.51087e-05 +28 chany_top_in[12]:5 mux_right_track_0\/mux_l1_in_0_:A0 0.152 +29 chany_top_in[12]:30 chany_top_in[12]:29 0.0008325893 +30 chany_top_in[12]:31 chany_top_in[12]:30 0.0045 +31 chany_top_in[12]:31 chany_top_in[12]:28 0.002388393 +32 chany_top_in[12]:29 mux_left_track_1\/mux_l1_in_1_:A1 0.152 +33 chany_top_in[12]:40 chany_top_in[12]:39 0.0045 +34 chany_top_in[12]:39 chany_top_in[12]:38 0.002995536 +35 chany_top_in[12]:41 chany_top_in[12]:40 0.0015625 +36 chany_top_in[12]:42 chany_top_in[12]:41 0.0045 +37 chany_top_in[12]:43 chany_top_in[12]:42 0.01872991 +38 chany_top_in[12]:44 chany_top_in[12]:43 0.00341 +39 chany_top_in[12]:46 chany_top_in[12]:45 0.00341 +40 chany_top_in[12]:45 chany_top_in[12]:44 0.00410545 +41 chany_top_in[12]:14 chany_top_in[12]:13 0.006120536 +42 chany_top_in[12]:15 chany_top_in[12]:14 0.0003035715 +43 chany_top_in[12]:20 chany_top_in[12]:19 0.0003035715 +44 chany_top_in[12]:26 chany_top_in[12]:25 0.0003035715 +45 chany_top_in[12]:25 chany_top_in[12]:24 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size10_10_sram[3] 0.001215401 //LENGTH 7.520 LUMPCC 0.0003105239 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 29.745 58.480 +*I mux_left_track_17\/mux_l4_in_0_:S I *L 0.00357 *C 27.240 56.440 +*I mem_left_track_17\/FTB_23__74:A I *L 0.001746 *C 30.820 55.760 +*N mux_tree_tapbuf_size10_10_sram[3]:3 *C 30.783 55.760 +*N mux_tree_tapbuf_size10_10_sram[3]:4 *C 29.485 55.760 +*N mux_tree_tapbuf_size10_10_sram[3]:5 *C 29.440 55.805 +*N mux_tree_tapbuf_size10_10_sram[3]:6 *C 27.277 56.440 +*N mux_tree_tapbuf_size10_10_sram[3]:7 *C 29.395 56.440 +*N mux_tree_tapbuf_size10_10_sram[3]:8 *C 29.440 56.440 +*N mux_tree_tapbuf_size10_10_sram[3]:9 *C 29.440 58.435 +*N mux_tree_tapbuf_size10_10_sram[3]:10 *C 29.440 58.480 +*N mux_tree_tapbuf_size10_10_sram[3]:11 *C 29.745 58.480 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_17\/mux_l4_in_0_:S 1e-06 +2 mem_left_track_17\/FTB_23__74:A 1e-06 +3 mux_tree_tapbuf_size10_10_sram[3]:3 3.456427e-05 +4 mux_tree_tapbuf_size10_10_sram[3]:4 3.456427e-05 +5 mux_tree_tapbuf_size10_10_sram[3]:5 5.346806e-05 +6 mux_tree_tapbuf_size10_10_sram[3]:6 0.0001506141 +7 mux_tree_tapbuf_size10_10_sram[3]:7 0.0001506141 +8 mux_tree_tapbuf_size10_10_sram[3]:8 0.0002272547 +9 mux_tree_tapbuf_size10_10_sram[3]:9 0.0001405976 +10 mux_tree_tapbuf_size10_10_sram[3]:10 5.662385e-05 +11 mux_tree_tapbuf_size10_10_sram[3]:11 5.357623e-05 +12 mux_tree_tapbuf_size10_10_sram[3]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.086302e-05 +13 mux_tree_tapbuf_size10_10_sram[3]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.086302e-05 +14 mux_tree_tapbuf_size10_10_sram[3]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.424759e-05 +15 mux_tree_tapbuf_size10_10_sram[3]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.424759e-05 +16 mux_tree_tapbuf_size10_10_sram[3]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.869041e-05 +17 mux_tree_tapbuf_size10_10_sram[3]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.869041e-05 +18 mux_tree_tapbuf_size10_10_sram[3]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.46093e-06 +19 mux_tree_tapbuf_size10_10_sram[3]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.46093e-06 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_10_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_10_sram[3]:4 mux_tree_tapbuf_size10_10_sram[3]:3 0.001158482 +2 mux_tree_tapbuf_size10_10_sram[3]:5 mux_tree_tapbuf_size10_10_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size10_10_sram[3]:3 mem_left_track_17\/FTB_23__74:A 0.152 +4 mux_tree_tapbuf_size10_10_sram[3]:7 mux_tree_tapbuf_size10_10_sram[3]:6 0.001890625 +5 mux_tree_tapbuf_size10_10_sram[3]:8 mux_tree_tapbuf_size10_10_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size10_10_sram[3]:8 mux_tree_tapbuf_size10_10_sram[3]:5 0.0005669643 +7 mux_tree_tapbuf_size10_10_sram[3]:6 mux_left_track_17\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_10_sram[3]:10 mux_tree_tapbuf_size10_10_sram[3]:9 0.0045 +9 mux_tree_tapbuf_size10_10_sram[3]:9 mux_tree_tapbuf_size10_10_sram[3]:8 0.00178125 +10 mux_tree_tapbuf_size10_10_sram[3]:11 mux_tree_tapbuf_size10_10_sram[3]:10 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[2] 0.002244553 //LENGTH 16.850 LUMPCC 0.0003086679 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 86.325 44.880 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 84.355 39.100 +*I mux_right_track_16\/mux_l3_in_0_:S I *L 0.00357 *C 81.320 47.260 +*I mux_right_track_16\/mux_l3_in_1_:S I *L 0.00357 *C 86.820 47.260 +*N mux_tree_tapbuf_size10_4_sram[2]:4 *C 86.782 47.260 +*N mux_tree_tapbuf_size10_4_sram[2]:5 *C 81.358 47.260 +*N mux_tree_tapbuf_size10_4_sram[2]:6 *C 85.100 47.260 +*N mux_tree_tapbuf_size10_4_sram[2]:7 *C 85.100 47.215 +*N mux_tree_tapbuf_size10_4_sram[2]:8 *C 84.392 39.100 +*N mux_tree_tapbuf_size10_4_sram[2]:9 *C 85.055 39.100 +*N mux_tree_tapbuf_size10_4_sram[2]:10 *C 85.100 39.145 +*N mux_tree_tapbuf_size10_4_sram[2]:11 *C 85.100 44.880 +*N mux_tree_tapbuf_size10_4_sram[2]:12 *C 85.145 44.880 +*N mux_tree_tapbuf_size10_4_sram[2]:13 *C 86.288 44.880 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_right_track_16\/mux_l3_in_0_:S 1e-06 +3 mux_right_track_16\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_4_sram[2]:4 6.142597e-05 +5 mux_tree_tapbuf_size10_4_sram[2]:5 0.0002279137 +6 mux_tree_tapbuf_size10_4_sram[2]:6 0.0003263156 +7 mux_tree_tapbuf_size10_4_sram[2]:7 0.0001509535 +8 mux_tree_tapbuf_size10_4_sram[2]:8 6.500278e-05 +9 mux_tree_tapbuf_size10_4_sram[2]:9 6.500278e-05 +10 mux_tree_tapbuf_size10_4_sram[2]:10 0.0003357103 +11 mux_tree_tapbuf_size10_4_sram[2]:11 0.0005228479 +12 mux_tree_tapbuf_size10_4_sram[2]:12 8.835625e-05 +13 mux_tree_tapbuf_size10_4_sram[2]:13 8.835625e-05 +14 mux_tree_tapbuf_size10_4_sram[2]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.791382e-05 +15 mux_tree_tapbuf_size10_4_sram[2]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.791382e-05 +16 mux_tree_tapbuf_size10_4_sram[2]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.642014e-05 +17 mux_tree_tapbuf_size10_4_sram[2]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.642014e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_4_sram[2]:13 0.152 +1 mux_tree_tapbuf_size10_4_sram[2]:12 mux_tree_tapbuf_size10_4_sram[2]:11 0.0045 +2 mux_tree_tapbuf_size10_4_sram[2]:11 mux_tree_tapbuf_size10_4_sram[2]:10 0.005120535 +3 mux_tree_tapbuf_size10_4_sram[2]:11 mux_tree_tapbuf_size10_4_sram[2]:7 0.002084821 +4 mux_tree_tapbuf_size10_4_sram[2]:13 mux_tree_tapbuf_size10_4_sram[2]:12 0.001020089 +5 mux_tree_tapbuf_size10_4_sram[2]:4 mux_right_track_16\/mux_l3_in_1_:S 0.152 +6 mux_tree_tapbuf_size10_4_sram[2]:9 mux_tree_tapbuf_size10_4_sram[2]:8 0.0005915179 +7 mux_tree_tapbuf_size10_4_sram[2]:10 mux_tree_tapbuf_size10_4_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size10_4_sram[2]:8 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +9 mux_tree_tapbuf_size10_4_sram[2]:6 mux_tree_tapbuf_size10_4_sram[2]:5 0.003341518 +10 mux_tree_tapbuf_size10_4_sram[2]:6 mux_tree_tapbuf_size10_4_sram[2]:4 0.001502232 +11 mux_tree_tapbuf_size10_4_sram[2]:7 mux_tree_tapbuf_size10_4_sram[2]:6 0.0045 +12 mux_tree_tapbuf_size10_4_sram[2]:5 mux_right_track_16\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[3] 0.002249878 //LENGTH 16.340 LUMPCC 0.0005693577 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 35.725 44.540 +*I mem_bottom_track_25\/FTB_21__72:A I *L 0.001746 *C 27.140 42.160 +*I mux_bottom_track_25\/mux_l4_in_0_:S I *L 0.00357 *C 38.980 45.220 +*N mux_tree_tapbuf_size10_8_sram[3]:3 *C 38.943 45.220 +*N mux_tree_tapbuf_size10_8_sram[3]:4 *C 35.420 45.220 +*N mux_tree_tapbuf_size10_8_sram[3]:5 *C 27.178 42.160 +*N mux_tree_tapbuf_size10_8_sram[3]:6 *C 34.915 42.160 +*N mux_tree_tapbuf_size10_8_sram[3]:7 *C 34.960 42.205 +*N mux_tree_tapbuf_size10_8_sram[3]:8 *C 34.960 44.540 +*N mux_tree_tapbuf_size10_8_sram[3]:9 *C 35.420 44.540 +*N mux_tree_tapbuf_size10_8_sram[3]:10 *C 35.420 44.540 +*N mux_tree_tapbuf_size10_8_sram[3]:11 *C 35.725 44.540 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_25\/FTB_21__72:A 1e-06 +2 mux_bottom_track_25\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_8_sram[3]:3 0.0001960406 +4 mux_tree_tapbuf_size10_8_sram[3]:4 0.0002421901 +5 mux_tree_tapbuf_size10_8_sram[3]:5 0.0003520946 +6 mux_tree_tapbuf_size10_8_sram[3]:6 0.0003520946 +7 mux_tree_tapbuf_size10_8_sram[3]:7 0.0001377844 +8 mux_tree_tapbuf_size10_8_sram[3]:8 0.0001736913 +9 mux_tree_tapbuf_size10_8_sram[3]:9 7.023113e-05 +10 mux_tree_tapbuf_size10_8_sram[3]:10 0.0001025893 +11 mux_tree_tapbuf_size10_8_sram[3]:11 5.080395e-05 +12 mux_tree_tapbuf_size10_8_sram[3]:6 optlc_net_147:34 1.29373e-06 +13 mux_tree_tapbuf_size10_8_sram[3]:6 optlc_net_147:32 5.727161e-05 +14 mux_tree_tapbuf_size10_8_sram[3]:6 optlc_net_147:20 0.0001412925 +15 mux_tree_tapbuf_size10_8_sram[3]:7 optlc_net_147:30 1.000004e-05 +16 mux_tree_tapbuf_size10_8_sram[3]:7 optlc_net_147:18 1.585253e-06 +17 mux_tree_tapbuf_size10_8_sram[3]:5 optlc_net_147:15 0.0001412925 +18 mux_tree_tapbuf_size10_8_sram[3]:5 optlc_net_147:20 5.727161e-05 +19 mux_tree_tapbuf_size10_8_sram[3]:5 optlc_net_147:33 1.29373e-06 +20 mux_tree_tapbuf_size10_8_sram[3]:8 optlc_net_147:31 1.000004e-05 +21 mux_tree_tapbuf_size10_8_sram[3]:8 optlc_net_147:19 1.585253e-06 +22 mux_tree_tapbuf_size10_8_sram[3]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.323569e-05 +23 mux_tree_tapbuf_size10_8_sram[3]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.323569e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_8_sram[3]:11 0.152 +1 mux_tree_tapbuf_size10_8_sram[3]:3 mux_bottom_track_25\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_8_sram[3]:11 mux_tree_tapbuf_size10_8_sram[3]:10 0.0001657609 +3 mux_tree_tapbuf_size10_8_sram[3]:10 mux_tree_tapbuf_size10_8_sram[3]:9 0.0045 +4 mux_tree_tapbuf_size10_8_sram[3]:10 mux_tree_tapbuf_size10_8_sram[3]:4 0.0006071429 +5 mux_tree_tapbuf_size10_8_sram[3]:9 mux_tree_tapbuf_size10_8_sram[3]:8 0.0004107143 +6 mux_tree_tapbuf_size10_8_sram[3]:6 mux_tree_tapbuf_size10_8_sram[3]:5 0.006908482 +7 mux_tree_tapbuf_size10_8_sram[3]:7 mux_tree_tapbuf_size10_8_sram[3]:6 0.0045 +8 mux_tree_tapbuf_size10_8_sram[3]:5 mem_bottom_track_25\/FTB_21__72:A 0.152 +9 mux_tree_tapbuf_size10_8_sram[3]:4 mux_tree_tapbuf_size10_8_sram[3]:3 0.003145089 +10 mux_tree_tapbuf_size10_8_sram[3]:8 mux_tree_tapbuf_size10_8_sram[3]:7 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size12_0_sram[1] 0.007740231 //LENGTH 47.705 LUMPCC 0.002408133 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.445 115.085 +*I mux_top_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 75.800 99.960 +*I mux_top_track_0\/mux_l2_in_3_:S I *L 0.00357 *C 77.840 95.880 +*I mux_top_track_0\/mux_l2_in_2_:S I *L 0.00357 *C 76.260 90.440 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 69.360 117.980 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 75.600 120.700 +*N mux_tree_tapbuf_size12_0_sram[1]:6 *C 75.562 120.700 +*N mux_tree_tapbuf_size12_0_sram[1]:7 *C 73.645 120.700 +*N mux_tree_tapbuf_size12_0_sram[1]:8 *C 73.600 120.655 +*N mux_tree_tapbuf_size12_0_sram[1]:9 *C 69.398 117.980 +*N mux_tree_tapbuf_size12_0_sram[1]:10 *C 73.555 117.980 +*N mux_tree_tapbuf_size12_0_sram[1]:11 *C 73.600 117.980 +*N mux_tree_tapbuf_size12_0_sram[1]:12 *C 76.297 90.440 +*N mux_tree_tapbuf_size12_0_sram[1]:13 *C 76.775 90.440 +*N mux_tree_tapbuf_size12_0_sram[1]:14 *C 76.820 90.485 +*N mux_tree_tapbuf_size12_0_sram[1]:15 *C 77.803 95.880 +*N mux_tree_tapbuf_size12_0_sram[1]:16 *C 76.865 95.880 +*N mux_tree_tapbuf_size12_0_sram[1]:17 *C 76.820 95.880 +*N mux_tree_tapbuf_size12_0_sram[1]:18 *C 75.838 99.960 +*N mux_tree_tapbuf_size12_0_sram[1]:19 *C 76.775 99.960 +*N mux_tree_tapbuf_size12_0_sram[1]:20 *C 76.820 99.960 +*N mux_tree_tapbuf_size12_0_sram[1]:21 *C 76.820 100.583 +*N mux_tree_tapbuf_size12_0_sram[1]:22 *C 76.812 100.640 +*N mux_tree_tapbuf_size12_0_sram[1]:23 *C 72.700 100.640 +*N mux_tree_tapbuf_size12_0_sram[1]:24 *C 72.680 100.648 +*N mux_tree_tapbuf_size12_0_sram[1]:25 *C 72.680 108.793 +*N mux_tree_tapbuf_size12_0_sram[1]:26 *C 72.700 108.800 +*N mux_tree_tapbuf_size12_0_sram[1]:27 *C 73.593 108.800 +*N mux_tree_tapbuf_size12_0_sram[1]:28 *C 73.600 108.858 +*N mux_tree_tapbuf_size12_0_sram[1]:29 *C 73.600 115.260 +*N mux_tree_tapbuf_size12_0_sram[1]:30 *C 73.600 115.260 +*N mux_tree_tapbuf_size12_0_sram[1]:31 *C 73.445 115.085 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_0\/mux_l2_in_3_:S 1e-06 +3 mux_top_track_0\/mux_l2_in_2_:S 1e-06 +4 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +5 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size12_0_sram[1]:6 0.0001655232 +7 mux_tree_tapbuf_size12_0_sram[1]:7 0.0001655232 +8 mux_tree_tapbuf_size12_0_sram[1]:8 0.0001062645 +9 mux_tree_tapbuf_size12_0_sram[1]:9 0.0002510543 +10 mux_tree_tapbuf_size12_0_sram[1]:10 0.0002510543 +11 mux_tree_tapbuf_size12_0_sram[1]:11 0.0002789986 +12 mux_tree_tapbuf_size12_0_sram[1]:12 6.134028e-05 +13 mux_tree_tapbuf_size12_0_sram[1]:13 6.134028e-05 +14 mux_tree_tapbuf_size12_0_sram[1]:14 0.0003417109 +15 mux_tree_tapbuf_size12_0_sram[1]:15 9.508509e-05 +16 mux_tree_tapbuf_size12_0_sram[1]:16 9.508509e-05 +17 mux_tree_tapbuf_size12_0_sram[1]:17 0.0005582876 +18 mux_tree_tapbuf_size12_0_sram[1]:18 9.527989e-05 +19 mux_tree_tapbuf_size12_0_sram[1]:19 9.527989e-05 +20 mux_tree_tapbuf_size12_0_sram[1]:20 0.0002441338 +21 mux_tree_tapbuf_size12_0_sram[1]:21 3.096203e-05 +22 mux_tree_tapbuf_size12_0_sram[1]:22 0.0005555521 +23 mux_tree_tapbuf_size12_0_sram[1]:23 0.0005555521 +24 mux_tree_tapbuf_size12_0_sram[1]:24 0.0001439555 +25 mux_tree_tapbuf_size12_0_sram[1]:25 0.0001439555 +26 mux_tree_tapbuf_size12_0_sram[1]:26 0.0001042834 +27 mux_tree_tapbuf_size12_0_sram[1]:27 0.0001042834 +28 mux_tree_tapbuf_size12_0_sram[1]:28 0.0002689268 +29 mux_tree_tapbuf_size12_0_sram[1]:29 0.0004419685 +30 mux_tree_tapbuf_size12_0_sram[1]:30 5.652048e-05 +31 mux_tree_tapbuf_size12_0_sram[1]:31 5.41768e-05 +32 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[6]:30 1.003558e-05 +33 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[6]:31 9.501288e-06 +34 mux_tree_tapbuf_size12_0_sram[1]:8 chany_top_in[6]:31 1.003558e-05 +35 mux_tree_tapbuf_size12_0_sram[1]:25 chany_top_in[6]:27 0.000371455 +36 mux_tree_tapbuf_size12_0_sram[1]:24 chany_top_in[6]:26 0.000371455 +37 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[6]:30 9.501288e-06 +38 mux_tree_tapbuf_size12_0_sram[1]:9 chany_top_in[10]:38 4.779844e-05 +39 mux_tree_tapbuf_size12_0_sram[1]:10 chany_top_in[10]:39 4.779844e-05 +40 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10] 1.881887e-06 +41 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10]:34 6.405226e-06 +42 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10]:36 9.35082e-07 +43 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10]:37 3.049006e-07 +44 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10]:38 8.839464e-06 +45 mux_tree_tapbuf_size12_0_sram[1]:11 chany_top_in[10]:39 7.742619e-05 +46 mux_tree_tapbuf_size12_0_sram[1]:8 chany_top_in[10] 7.742619e-05 +47 mux_tree_tapbuf_size12_0_sram[1]:8 chany_top_in[10]:38 3.049006e-07 +48 mux_tree_tapbuf_size12_0_sram[1]:28 chany_top_in[10]:31 0.0001342676 +49 mux_tree_tapbuf_size12_0_sram[1]:28 chany_top_in[10]:33 1.511633e-05 +50 mux_tree_tapbuf_size12_0_sram[1]:25 chany_top_in[10]:32 1.066189e-05 +51 mux_tree_tapbuf_size12_0_sram[1]:24 chany_top_in[10]:31 1.066189e-05 +52 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:32 0.0001342676 +53 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:33 6.405226e-06 +54 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:34 1.511633e-05 +55 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:35 9.35082e-07 +56 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:37 8.839464e-06 +57 mux_tree_tapbuf_size12_0_sram[1]:29 chany_top_in[10]:39 1.881887e-06 +58 mux_tree_tapbuf_size12_0_sram[1]:25 chany_top_in[13]:37 0.000371455 +59 mux_tree_tapbuf_size12_0_sram[1]:23 chany_top_in[13]:36 4.419942e-05 +60 mux_tree_tapbuf_size12_0_sram[1]:24 chany_top_in[13]:36 0.000371455 +61 mux_tree_tapbuf_size12_0_sram[1]:22 chany_top_in[13]:29 4.419942e-05 +62 mux_tree_tapbuf_size12_0_sram[1]:21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 2.267185e-05 +63 mux_tree_tapbuf_size12_0_sram[1]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.111122e-05 +64 mux_tree_tapbuf_size12_0_sram[1]:20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 2.267185e-05 +65 mux_tree_tapbuf_size12_0_sram[1]:20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.111122e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_0_sram[1]:31 0.152 +1 mux_tree_tapbuf_size12_0_sram[1]:9 mux_top_track_0\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_0_sram[1]:10 mux_tree_tapbuf_size12_0_sram[1]:9 0.003712054 +3 mux_tree_tapbuf_size12_0_sram[1]:11 mux_tree_tapbuf_size12_0_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size12_0_sram[1]:11 mux_tree_tapbuf_size12_0_sram[1]:8 0.002388393 +5 mux_tree_tapbuf_size12_0_sram[1]:6 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +6 mux_tree_tapbuf_size12_0_sram[1]:7 mux_tree_tapbuf_size12_0_sram[1]:6 0.001712054 +7 mux_tree_tapbuf_size12_0_sram[1]:8 mux_tree_tapbuf_size12_0_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size12_0_sram[1]:28 mux_tree_tapbuf_size12_0_sram[1]:27 0.00341 +9 mux_tree_tapbuf_size12_0_sram[1]:27 mux_tree_tapbuf_size12_0_sram[1]:26 0.000139825 +10 mux_tree_tapbuf_size12_0_sram[1]:26 mux_tree_tapbuf_size12_0_sram[1]:25 0.00341 +11 mux_tree_tapbuf_size12_0_sram[1]:25 mux_tree_tapbuf_size12_0_sram[1]:24 0.00127605 +12 mux_tree_tapbuf_size12_0_sram[1]:23 mux_tree_tapbuf_size12_0_sram[1]:22 0.0006442916 +13 mux_tree_tapbuf_size12_0_sram[1]:24 mux_tree_tapbuf_size12_0_sram[1]:23 0.00341 +14 mux_tree_tapbuf_size12_0_sram[1]:21 mux_tree_tapbuf_size12_0_sram[1]:20 0.0005558036 +15 mux_tree_tapbuf_size12_0_sram[1]:22 mux_tree_tapbuf_size12_0_sram[1]:21 0.00341 +16 mux_tree_tapbuf_size12_0_sram[1]:30 mux_tree_tapbuf_size12_0_sram[1]:29 0.0045 +17 mux_tree_tapbuf_size12_0_sram[1]:29 mux_tree_tapbuf_size12_0_sram[1]:28 0.005716518 +18 mux_tree_tapbuf_size12_0_sram[1]:29 mux_tree_tapbuf_size12_0_sram[1]:11 0.002428571 +19 mux_tree_tapbuf_size12_0_sram[1]:31 mux_tree_tapbuf_size12_0_sram[1]:30 8.423914e-05 +20 mux_tree_tapbuf_size12_0_sram[1]:16 mux_tree_tapbuf_size12_0_sram[1]:15 0.0008370536 +21 mux_tree_tapbuf_size12_0_sram[1]:17 mux_tree_tapbuf_size12_0_sram[1]:16 0.0045 +22 mux_tree_tapbuf_size12_0_sram[1]:17 mux_tree_tapbuf_size12_0_sram[1]:14 0.004816964 +23 mux_tree_tapbuf_size12_0_sram[1]:15 mux_top_track_0\/mux_l2_in_3_:S 0.152 +24 mux_tree_tapbuf_size12_0_sram[1]:13 mux_tree_tapbuf_size12_0_sram[1]:12 0.0004263393 +25 mux_tree_tapbuf_size12_0_sram[1]:14 mux_tree_tapbuf_size12_0_sram[1]:13 0.0045 +26 mux_tree_tapbuf_size12_0_sram[1]:12 mux_top_track_0\/mux_l2_in_2_:S 0.152 +27 mux_tree_tapbuf_size12_0_sram[1]:19 mux_tree_tapbuf_size12_0_sram[1]:18 0.0008370536 +28 mux_tree_tapbuf_size12_0_sram[1]:20 mux_tree_tapbuf_size12_0_sram[1]:19 0.0045 +29 mux_tree_tapbuf_size12_0_sram[1]:20 mux_tree_tapbuf_size12_0_sram[1]:17 0.003642857 +30 mux_tree_tapbuf_size12_0_sram[1]:18 mux_top_track_0\/mux_l2_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_1_ccff_tail[0] 0.001425704 //LENGTH 12.280 LUMPCC 0.0001466258 DR + +*CONN +*I mem_top_track_2\/FTB_2__53:X O *L 0 *C 48.065 118.320 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 42.495 124.100 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:2 *C 42.532 124.100 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:3 *C 44.115 124.100 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:4 *C 44.160 124.055 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:5 *C 44.160 118.365 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 *C 44.205 118.320 +*N mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 *C 48.028 118.320 + +*CAP +0 mem_top_track_2\/FTB_2__53:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:2 0.0001252323 +3 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:3 0.0001252323 +4 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:4 0.0003387752 +5 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:5 0.0003387752 +6 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 0.0001745315 +7 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 0.0001745315 +8 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 top_left_grid_pin_36_[0]:11 7.331291e-05 +9 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 top_left_grid_pin_36_[0]:10 7.331291e-05 + +*RES +0 mem_top_track_2\/FTB_2__53:X mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:2 0.001412947 +3 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:4 0.005080357 +6 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 0.003412947 + +*END + +*D_NET mux_tree_tapbuf_size16_1_sram[2] 0.005263965 //LENGTH 34.365 LUMPCC 0.001437548 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 112.945 71.400 +*I mux_right_track_4\/mux_l3_in_2_:S I *L 0.00357 *C 117.660 72.375 +*I mux_right_track_4\/mux_l3_in_3_:S I *L 0.00357 *C 117.640 74.120 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 125.295 77.180 +*I mux_right_track_4\/mux_l3_in_1_:S I *L 0.00357 *C 119.500 77.520 +*I mux_right_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 118.120 82.960 +*N mux_tree_tapbuf_size16_1_sram[2]:6 *C 118.105 82.960 +*N mux_tree_tapbuf_size16_1_sram[2]:7 *C 117.782 82.960 +*N mux_tree_tapbuf_size16_1_sram[2]:8 *C 117.760 82.915 +*N mux_tree_tapbuf_size16_1_sram[2]:9 *C 119.463 77.520 +*N mux_tree_tapbuf_size16_1_sram[2]:10 *C 117.805 77.520 +*N mux_tree_tapbuf_size16_1_sram[2]:11 *C 117.760 77.520 +*N mux_tree_tapbuf_size16_1_sram[2]:12 *C 125.333 77.180 +*N mux_tree_tapbuf_size16_1_sram[2]:13 *C 125.995 77.180 +*N mux_tree_tapbuf_size16_1_sram[2]:14 *C 126.040 77.135 +*N mux_tree_tapbuf_size16_1_sram[2]:15 *C 126.040 74.858 +*N mux_tree_tapbuf_size16_1_sram[2]:16 *C 126.033 74.800 +*N mux_tree_tapbuf_size16_1_sram[2]:17 *C 117.768 74.800 +*N mux_tree_tapbuf_size16_1_sram[2]:18 *C 117.760 74.858 +*N mux_tree_tapbuf_size16_1_sram[2]:19 *C 117.300 74.800 +*N mux_tree_tapbuf_size16_1_sram[2]:20 *C 117.625 74.120 +*N mux_tree_tapbuf_size16_1_sram[2]:21 *C 117.323 74.120 +*N mux_tree_tapbuf_size16_1_sram[2]:22 *C 117.300 74.120 +*N mux_tree_tapbuf_size16_1_sram[2]:23 *C 117.660 72.375 +*N mux_tree_tapbuf_size16_1_sram[2]:24 *C 117.660 72.715 +*N mux_tree_tapbuf_size16_1_sram[2]:25 *C 117.330 72.730 +*N mux_tree_tapbuf_size16_1_sram[2]:26 *C 117.300 72.760 +*N mux_tree_tapbuf_size16_1_sram[2]:27 *C 117.300 71.445 +*N mux_tree_tapbuf_size16_1_sram[2]:28 *C 117.255 71.400 +*N mux_tree_tapbuf_size16_1_sram[2]:29 *C 112.983 71.400 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_4\/mux_l3_in_2_:S 1e-06 +2 mux_right_track_4\/mux_l3_in_3_:S 1e-06 +3 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_right_track_4\/mux_l3_in_1_:S 1e-06 +5 mux_right_track_4\/mux_l3_in_0_:S 1e-06 +6 mux_tree_tapbuf_size16_1_sram[2]:6 4.776461e-05 +7 mux_tree_tapbuf_size16_1_sram[2]:7 4.776461e-05 +8 mux_tree_tapbuf_size16_1_sram[2]:8 0.0003046209 +9 mux_tree_tapbuf_size16_1_sram[2]:9 0.0001210768 +10 mux_tree_tapbuf_size16_1_sram[2]:10 0.0001210768 +11 mux_tree_tapbuf_size16_1_sram[2]:11 0.0005259829 +12 mux_tree_tapbuf_size16_1_sram[2]:12 8.045467e-05 +13 mux_tree_tapbuf_size16_1_sram[2]:13 8.045467e-05 +14 mux_tree_tapbuf_size16_1_sram[2]:14 0.0001670552 +15 mux_tree_tapbuf_size16_1_sram[2]:15 0.0001670552 +16 mux_tree_tapbuf_size16_1_sram[2]:16 0.0003141935 +17 mux_tree_tapbuf_size16_1_sram[2]:17 0.0003141935 +18 mux_tree_tapbuf_size16_1_sram[2]:18 0.0001953362 +19 mux_tree_tapbuf_size16_1_sram[2]:19 3.164931e-05 +20 mux_tree_tapbuf_size16_1_sram[2]:20 3.342372e-05 +21 mux_tree_tapbuf_size16_1_sram[2]:21 3.342372e-05 +22 mux_tree_tapbuf_size16_1_sram[2]:22 0.0001044423 +23 mux_tree_tapbuf_size16_1_sram[2]:23 5.624136e-05 +24 mux_tree_tapbuf_size16_1_sram[2]:24 6.95825e-05 +25 mux_tree_tapbuf_size16_1_sram[2]:25 4.363632e-05 +26 mux_tree_tapbuf_size16_1_sram[2]:26 0.0001769144 +27 mux_tree_tapbuf_size16_1_sram[2]:27 9.284045e-05 +28 mux_tree_tapbuf_size16_1_sram[2]:28 0.0003456172 +29 mux_tree_tapbuf_size16_1_sram[2]:29 0.0003456172 +30 mux_tree_tapbuf_size16_1_sram[2]:16 chanx_left_in[18]:15 0.0004851948 +31 mux_tree_tapbuf_size16_1_sram[2]:17 chanx_left_in[18]:16 0.0004851948 +32 mux_tree_tapbuf_size16_1_sram[2]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.305185e-05 +33 mux_tree_tapbuf_size16_1_sram[2]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.3774e-05 +34 mux_tree_tapbuf_size16_1_sram[2]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.3774e-05 +35 mux_tree_tapbuf_size16_1_sram[2]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.305185e-05 +36 mux_tree_tapbuf_size16_1_sram[2]:27 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.144345e-06 +37 mux_tree_tapbuf_size16_1_sram[2]:22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.942662e-05 +38 mux_tree_tapbuf_size16_1_sram[2]:22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.522693e-05 +39 mux_tree_tapbuf_size16_1_sram[2]:26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.522693e-05 +40 mux_tree_tapbuf_size16_1_sram[2]:26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.144345e-06 +41 mux_tree_tapbuf_size16_1_sram[2]:23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.688926e-06 +42 mux_tree_tapbuf_size16_1_sram[2]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.606462e-05 +43 mux_tree_tapbuf_size16_1_sram[2]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.292351e-05 +44 mux_tree_tapbuf_size16_1_sram[2]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.606462e-05 +45 mux_tree_tapbuf_size16_1_sram[2]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.292351e-05 +46 mux_tree_tapbuf_size16_1_sram[2]:24 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.688926e-06 +47 mux_tree_tapbuf_size16_1_sram[2]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.942662e-05 +48 mux_tree_tapbuf_size16_1_sram[2]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.955466e-05 +49 mux_tree_tapbuf_size16_1_sram[2]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.955466e-05 +50 mux_tree_tapbuf_size16_1_sram[2]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 1.372385e-05 +51 mux_tree_tapbuf_size16_1_sram[2]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 1.372385e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size16_1_sram[2]:29 0.152 +1 mux_tree_tapbuf_size16_1_sram[2]:29 mux_tree_tapbuf_size16_1_sram[2]:28 0.003814732 +2 mux_tree_tapbuf_size16_1_sram[2]:28 mux_tree_tapbuf_size16_1_sram[2]:27 0.0045 +3 mux_tree_tapbuf_size16_1_sram[2]:27 mux_tree_tapbuf_size16_1_sram[2]:26 0.001174107 +4 mux_tree_tapbuf_size16_1_sram[2]:20 mux_right_track_4\/mux_l3_in_3_:S 0.152 +5 mux_tree_tapbuf_size16_1_sram[2]:21 mux_tree_tapbuf_size16_1_sram[2]:20 0.0001644022 +6 mux_tree_tapbuf_size16_1_sram[2]:22 mux_tree_tapbuf_size16_1_sram[2]:21 0.0045 +7 mux_tree_tapbuf_size16_1_sram[2]:22 mux_tree_tapbuf_size16_1_sram[2]:19 0.0006071429 +8 mux_tree_tapbuf_size16_1_sram[2]:25 mux_tree_tapbuf_size16_1_sram[2]:24 0.00020625 +9 mux_tree_tapbuf_size16_1_sram[2]:26 mux_tree_tapbuf_size16_1_sram[2]:25 0.0045 +10 mux_tree_tapbuf_size16_1_sram[2]:26 mux_tree_tapbuf_size16_1_sram[2]:22 0.001214286 +11 mux_tree_tapbuf_size16_1_sram[2]:23 mux_right_track_4\/mux_l3_in_2_:S 0.152 +12 mux_tree_tapbuf_size16_1_sram[2]:12 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +13 mux_tree_tapbuf_size16_1_sram[2]:13 mux_tree_tapbuf_size16_1_sram[2]:12 0.0005915179 +14 mux_tree_tapbuf_size16_1_sram[2]:14 mux_tree_tapbuf_size16_1_sram[2]:13 0.0045 +15 mux_tree_tapbuf_size16_1_sram[2]:15 mux_tree_tapbuf_size16_1_sram[2]:14 0.002033482 +16 mux_tree_tapbuf_size16_1_sram[2]:16 mux_tree_tapbuf_size16_1_sram[2]:15 0.00341 +17 mux_tree_tapbuf_size16_1_sram[2]:18 mux_tree_tapbuf_size16_1_sram[2]:17 0.00341 +18 mux_tree_tapbuf_size16_1_sram[2]:18 mux_tree_tapbuf_size16_1_sram[2]:11 0.002377233 +19 mux_tree_tapbuf_size16_1_sram[2]:17 mux_tree_tapbuf_size16_1_sram[2]:16 0.00129485 +20 mux_tree_tapbuf_size16_1_sram[2]:10 mux_tree_tapbuf_size16_1_sram[2]:9 0.001479911 +21 mux_tree_tapbuf_size16_1_sram[2]:11 mux_tree_tapbuf_size16_1_sram[2]:10 0.0045 +22 mux_tree_tapbuf_size16_1_sram[2]:11 mux_tree_tapbuf_size16_1_sram[2]:8 0.004816964 +23 mux_tree_tapbuf_size16_1_sram[2]:9 mux_right_track_4\/mux_l3_in_1_:S 0.152 +24 mux_tree_tapbuf_size16_1_sram[2]:6 mux_right_track_4\/mux_l3_in_0_:S 0.152 +25 mux_tree_tapbuf_size16_1_sram[2]:7 mux_tree_tapbuf_size16_1_sram[2]:6 0.0001752718 +26 mux_tree_tapbuf_size16_1_sram[2]:8 mux_tree_tapbuf_size16_1_sram[2]:7 0.0045 +27 mux_tree_tapbuf_size16_1_sram[2]:24 mux_tree_tapbuf_size16_1_sram[2]:23 0.0003035715 +28 mux_tree_tapbuf_size16_1_sram[2]:19 mux_tree_tapbuf_size16_1_sram[2]:18 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_2_ccff_tail[0] 0.00102807 //LENGTH 7.030 LUMPCC 0.0004364007 DR + +*CONN +*I mem_bottom_track_33\/FTB_27__78:X O *L 0 *C 12.645 45.220 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 15.815 47.940 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 *C 15.778 47.940 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 *C 12.465 47.940 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 *C 12.420 47.895 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 *C 12.420 45.265 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 *C 12.420 45.220 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 *C 12.645 45.220 + +*CAP +0 mem_bottom_track_33\/FTB_27__78:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.0001023582 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0001023582 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.0001344195 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0001344195 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 5.892159e-05 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 5.719251e-05 +8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 prog_clk[0]:680 3.908644e-05 +9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 prog_clk[0]:682 6.962851e-06 +10 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 prog_clk[0]:681 3.908644e-05 +11 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 prog_clk[0]:694 6.962851e-06 +12 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 prog_clk[0]:693 5.386012e-06 +13 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 prog_clk[0]:694 2.736094e-05 +14 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 prog_clk[0]:694 5.386012e-06 +15 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 prog_clk[0]:695 2.736094e-05 +16 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001394041 +17 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001394041 + +*RES +0 mem_bottom_track_33\/FTB_27__78:X mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.002957589 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001522382 //LENGTH 10.380 LUMPCC 0.0005975467 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_1_:X O *L 0 *C 101.485 99.960 +*I mux_right_track_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 108.275 102.340 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 108.238 102.340 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 106.260 102.340 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 106.260 102.000 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 102.625 102.000 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 102.580 101.955 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 102.580 100.005 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:8 *C 102.535 99.960 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:9 *C 101.523 99.960 + +*CAP +0 mux_right_track_0\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 8.232822e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0001072644 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001414391 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001165029 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0001291683 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0001291683 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:8 0.0001084822 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:9 0.0001084822 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 right_top_grid_pin_44_[0]:18 8.199686e-05 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 right_top_grid_pin_44_[0]:13 2.821185e-06 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 right_top_grid_pin_44_[0]:17 4.874053e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 right_top_grid_pin_44_[0]:17 2.821185e-06 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 right_top_grid_pin_44_[0]:18 4.874053e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 right_top_grid_pin_44_[0]:17 8.199686e-05 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.13963e-05 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001437823 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.624125e-08 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.624125e-08 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001437823 +21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 2.13963e-05 + +*RES +0 mux_right_track_0\/mux_l3_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:9 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_right_track_0\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.003245536 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.001741071 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:8 0.0009040179 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0003035715 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.001765625 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001342564 //LENGTH 10.430 LUMPCC 0.0002619798 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 89.525 28.220 +*I mux_bottom_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 87.860 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 87.860 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 87.890 20.090 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 87.905 20.400 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 89.240 20.400 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 89.240 28.175 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 89.240 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 89.525 28.220 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.166714e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.222732e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001135362 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004243867 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003430779 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.702387e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 6.666534e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size12_4_sram[2]:10 0.000129063 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size12_4_sram[2]:13 1.77949e-06 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size12_4_sram[2]:13 1.80975e-08 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size12_4_sram[2]:14 1.292678e-07 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:10 1.80975e-08 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:13 1.292678e-07 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:13 0.000129063 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:14 1.77949e-06 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001548913 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.006941964 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.00019375 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001191964 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.004958325 //LENGTH 34.775 LUMPCC 0.0005730254 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 72.395 85.340 +*I mux_left_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 44.525 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 44.525 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 44.620 83.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 58.835 83.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 58.880 83.595 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 58.880 82.325 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 58.925 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 63.480 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 63.480 82.620 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 68.080 82.620 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 68.080 82.960 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 71.715 82.960 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 71.760 83.005 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 71.760 85.295 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 71.805 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 *C 72.358 85.340 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.446656e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0009712685 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000944327 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.347636e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.347636e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003422129 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0003676281 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0003459408 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0003485956 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0002235043 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0001954344 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0001315633 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0001315633 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 7.992079e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 7.992079e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 chany_bottom_in[12]:15 3.749617e-05 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 chany_bottom_in[12]:15 6.835744e-05 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 chany_bottom_in[12]:14 6.835744e-05 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 chany_bottom_in[12]:16 3.749617e-05 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 optlc_net_148:8 4.436472e-05 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 optlc_net_148:17 6.186003e-07 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 optlc_net_148:19 6.572262e-05 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 optlc_net_148:7 1.007378e-05 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 optlc_net_148:6 1.007378e-05 +26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 optlc_net_148:16 6.186003e-07 +27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 optlc_net_148:18 6.572262e-05 +28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 optlc_net_148:19 4.436472e-05 +29 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.987936e-05 +30 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.987936e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.01269196 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001133929 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.003245536 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0045 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0045 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.002044643 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.0004933036 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.004066965 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0003035715 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.004107143 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0003035715 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0] 0.00256688 //LENGTH 21.555 LUMPCC 0.0003413039 DR + +*CONN +*I mux_right_track_4\/mux_l5_in_0_:X O *L 0 *C 129.545 74.460 +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 136.365 61.035 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 *C 136.365 61.035 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 *C 133.905 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 *C 133.860 60.905 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 *C 133.860 68.000 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 *C 133.400 68.000 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 *C 133.400 74.415 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 *C 133.355 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 *C 129.583 74.460 + +*CAP +0 mux_right_track_4\/mux_l5_in_0_:X 1e-06 +1 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.000181582 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0001536163 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.0003231513 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0003557877 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.0004145054 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.000381869 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 0.0002065323 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 0.0002065323 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 ropt_net_244:4 0.0001134062 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 ropt_net_244:5 5.18209e-06 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 ropt_net_244:4 5.18209e-06 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 ropt_net_244:5 0.0001134062 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 ropt_net_234:4 5.206362e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 ropt_net_234:3 5.206362e-05 + +*RES +0 mux_right_track_4\/mux_l5_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.002196429 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.005727679 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 0.003368303 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0004107143 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.006334821 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001561867 //LENGTH 12.015 LUMPCC 0.0002293286 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_0_:X O *L 0 *C 41.225 36.040 +*I mux_bottom_track_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 41.500 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 41.462 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 40.985 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 40.940 25.545 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 40.940 35.995 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 40.940 36.040 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 41.225 36.040 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.908699e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 6.908699e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0005448552 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0005448552 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.248369e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.017031e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chanx_left_in[3]:8 1.530117e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chanx_left_in[3]:11 3.936913e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chanx_left_in[3]:7 1.530117e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chanx_left_in[3]:12 3.936913e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_5_sram[0]:20 5.999398e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_5_sram[0]:19 5.999398e-05 + +*RES +0 mux_bottom_track_5\/mux_l3_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_5\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004263393 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.009330357 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009117436 //LENGTH 6.860 LUMPCC 0.0002909497 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_0_:X O *L 0 *C 53.535 50.320 +*I mux_top_track_16\/mux_l3_in_0_:A1 I *L 0.00198 *C 49.780 52.700 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 49.680 52.700 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 49.680 52.655 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 49.680 50.365 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 49.725 50.320 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 53.498 50.320 + +*CAP +0 mux_top_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.217836e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001526291 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001526291 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001406787 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001406787 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_10_sram[0]:23 7.099421e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_10_sram[0]:22 7.099421e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:21 5.942813e-06 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_1_sram[1]:26 6.853783e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_1_sram[1]:25 5.942813e-06 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_1_sram[1]:27 6.853783e-05 + +*RES +0 mux_top_track_16\/mux_l2_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002044643 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.003368304 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008140156 //LENGTH 6.760 LUMPCC 7.990214e-05 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_1_:X O *L 0 *C 110.225 61.540 +*I mux_right_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 113.335 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 113.297 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 110.905 64.260 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 110.860 64.215 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 110.860 61.585 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 110.815 61.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 110.263 61.540 + +*CAP +0 mux_right_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001426981 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001426981 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001602467 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001602467 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.311194e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.311194e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.995107e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.995107e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002136161 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004949879 //LENGTH 3.880 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_2_:X O *L 0 *C 101.485 72.760 +*I mux_right_track_24\/mux_l3_in_1_:A1 I *L 0.00198 *C 103.140 74.460 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 103.040 74.460 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 103.040 74.415 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 103.040 72.805 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 102.995 72.760 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 101.523 72.760 + +*CAP +0 mux_right_track_24\/mux_l2_in_2_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_1_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.192278e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001127366 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001127366 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000117796 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000117796 + +*RES +0 mux_right_track_24\/mux_l2_in_2_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_24\/mux_l3_in_1_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0014375 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001861326 //LENGTH 15.545 LUMPCC 0.0002908334 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_2_:X O *L 0 *C 59.515 33.320 +*I mux_bottom_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 49.320 28.900 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 49.358 28.900 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 58.375 28.900 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 58.420 28.945 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 58.420 33.275 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 58.465 33.320 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 59.478 33.320 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004563386 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004563386 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002320259 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002320259 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.588194e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.588194e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001186569 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001186569 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.675982e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.675982e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_2_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_17\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.00805134 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007337854 //LENGTH 5.855 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_1_:X O *L 0 *C 47.555 71.400 +*I mux_left_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 43.990 70.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 44.028 70.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 45.495 70.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 45.540 70.085 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 45.540 71.355 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 45.585 71.400 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 47.518 71.400 + +*CAP +0 mux_left_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001278163 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001278163 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.24407e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.24407e-05 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001456358 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001456358 + +*RES +0 mux_left_track_9\/mux_l2_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001310268 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133928 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006567928 //LENGTH 4.775 LUMPCC 0.0001687334 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_1_:X O *L 0 *C 65.955 58.820 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 61.470 58.820 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 61.508 58.820 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 65.918 58.820 + +*CAP +0 mux_left_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002430297 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002430297 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_right_in[9]:10 8.436672e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[9]:11 8.436672e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0039375 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003986877 //LENGTH 28.935 LUMPCC 0.001472291 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_2_:X O *L 0 *C 84.005 77.860 +*I mux_top_track_32\/mux_l2_in_1_:A1 I *L 0.00198 *C 83.360 105.060 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 83.398 105.060 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 84.135 105.060 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 84.180 105.015 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 84.180 77.905 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 84.180 77.860 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 84.005 77.860 + +*CAP +0 mux_top_track_32\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.516919e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.516919e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001092424 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001092424 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.090348e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.649526e-05 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[2]:20 2.407931e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[2]:23 1.012958e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[2]:24 6.618199e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[2]:13 6.618199e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[2]:23 2.407931e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[2]:24 1.012958e-05 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size12_2_sram[0]:16 0.0004995829 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size12_2_sram[0]:19 5.893835e-05 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_2_sram[0]:19 0.0004995829 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size12_2_sram[0]:20 5.893835e-05 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.723358e-05 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.723358e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_2_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.510871e-05 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.02420536 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0006584821 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_32\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET chanx_left_out[18] 0.00118267 //LENGTH 8.410 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_845:X O *L 0 *C 4.140 75.480 +*P chanx_left_out[18] O *L 0.7423 *C 1.305 70.720 +*N chanx_left_out[18]:2 *C 3.673 70.720 +*N chanx_left_out[18]:3 *C 3.680 70.778 +*N chanx_left_out[18]:4 *C 3.680 75.435 +*N chanx_left_out[18]:5 *C 3.725 75.480 +*N chanx_left_out[18]:6 *C 4.103 75.480 + +*CAP +0 ropt_mt_inst_845:X 1e-06 +1 chanx_left_out[18] 0.0002013132 +2 chanx_left_out[18]:2 0.0002013132 +3 chanx_left_out[18]:3 0.0003401368 +4 chanx_left_out[18]:4 0.0003401368 +5 chanx_left_out[18]:5 4.938505e-05 +6 chanx_left_out[18]:6 4.938505e-05 + +*RES +0 ropt_mt_inst_845:X chanx_left_out[18]:6 0.152 +1 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0003370536 +2 chanx_left_out[18]:5 chanx_left_out[18]:4 0.0045 +3 chanx_left_out[18]:4 chanx_left_out[18]:3 0.004158482 +4 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +5 chanx_left_out[18]:2 chanx_left_out[18] 0.0003709083 + +*END + +*D_NET ropt_net_244 0.00138674 //LENGTH 9.710 LUMPCC 0.000679168 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 131.100 69.020 +*I ropt_mt_inst_898:A I *L 0.001766 *C 134.780 63.920 +*N ropt_net_244:2 *C 134.743 63.920 +*N ropt_net_244:3 *C 134.365 63.920 +*N ropt_net_244:4 *C 134.320 63.965 +*N ropt_net_244:5 *C 134.320 68.975 +*N ropt_net_244:6 *C 134.275 69.020 +*N ropt_net_244:7 *C 131.138 69.020 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 ropt_mt_inst_898:A 1e-06 +2 ropt_net_244:2 5.223837e-05 +3 ropt_net_244:3 5.223837e-05 +4 ropt_net_244:4 0.0001939205 +5 ropt_net_244:5 0.0001939205 +6 ropt_net_244:6 0.000106627 +7 ropt_net_244:7 0.000106627 +8 ropt_net_244:4 chanx_left_in[16]:9 6.398578e-07 +9 ropt_net_244:6 chanx_left_in[16]:7 6.215069e-05 +10 ropt_net_244:5 chanx_left_in[16]:8 6.398578e-07 +11 ropt_net_244:7 chanx_left_in[16]:6 6.215069e-05 +12 ropt_net_244:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.0001134062 +13 ropt_net_244:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 5.18209e-06 +14 ropt_net_244:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0001134062 +15 ropt_net_244:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 5.18209e-06 +16 ropt_net_244:4 ropt_net_179:5 1.634488e-05 +17 ropt_net_244:6 ropt_net_179:6 0.0001130515 +18 ropt_net_244:6 ropt_net_179:2 2.880873e-05 +19 ropt_net_244:5 ropt_net_179:4 1.634488e-05 +20 ropt_net_244:7 ropt_net_179:3 2.880873e-05 +21 ropt_net_244:7 ropt_net_179:7 0.0001130515 + +*RES +0 ropt_mt_inst_795:X ropt_net_244:7 0.152 +1 ropt_net_244:2 ropt_mt_inst_898:A 0.152 +2 ropt_net_244:3 ropt_net_244:2 0.0003370536 +3 ropt_net_244:4 ropt_net_244:3 0.0045 +4 ropt_net_244:6 ropt_net_244:5 0.0045 +5 ropt_net_244:5 ropt_net_244:4 0.004473215 +6 ropt_net_244:7 ropt_net_244:6 0.002801339 + +*END + +*D_NET BUF_net_90 0.003214214 //LENGTH 28.405 LUMPCC 0.0006331915 DR + +*CONN +*I BUFT_RR_90:X O *L 0 *C 88.320 99.620 +*I BUFT_P_135:A I *L 0.001766 *C 89.240 126.480 +*N BUF_net_90:2 *C 89.203 126.480 +*N BUF_net_90:3 *C 88.365 126.480 +*N BUF_net_90:4 *C 88.320 126.435 +*N BUF_net_90:5 *C 88.320 99.665 +*N BUF_net_90:6 *C 88.320 99.620 + +*CAP +0 BUFT_RR_90:X 1e-06 +1 BUFT_P_135:A 1e-06 +2 BUF_net_90:2 6.714692e-05 +3 BUF_net_90:3 6.714692e-05 +4 BUF_net_90:4 0.00120614 +5 BUF_net_90:5 0.00120614 +6 BUF_net_90:6 3.244852e-05 +7 BUF_net_90:5 chany_top_in[19]:10 8.199929e-05 +8 BUF_net_90:4 chany_top_in[19]:11 8.199929e-05 +9 BUF_net_90:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0001475343 +10 BUF_net_90:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0001475343 +11 BUF_net_90:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.706211e-05 +12 BUF_net_90:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.706211e-05 + +*RES +0 BUFT_RR_90:X BUF_net_90:6 0.152 +1 BUF_net_90:6 BUF_net_90:5 0.0045 +2 BUF_net_90:5 BUF_net_90:4 0.02390179 +3 BUF_net_90:3 BUF_net_90:2 0.0007477679 +4 BUF_net_90:4 BUF_net_90:3 0.0045 +5 BUF_net_90:2 BUFT_P_135:A 0.152 + +*END + +*D_NET ropt_net_192 0.001235134 //LENGTH 9.060 LUMPCC 0.0003223148 DR + +*CONN +*I BUFT_P_117:X O *L 0 *C 46.000 6.120 +*I ropt_mt_inst_831:A I *L 0.001766 *C 52.440 6.800 +*N ropt_net_192:2 *C 52.403 6.800 +*N ropt_net_192:3 *C 52.025 6.800 +*N ropt_net_192:4 *C 51.980 6.755 +*N ropt_net_192:5 *C 51.980 6.165 +*N ropt_net_192:6 *C 51.980 6.120 +*N ropt_net_192:7 *C 46.038 6.120 + +*CAP +0 BUFT_P_117:X 1e-06 +1 ropt_mt_inst_831:A 1e-06 +2 ropt_net_192:2 9.973191e-07 +3 ropt_net_192:3 9.973191e-07 +4 ropt_net_192:4 5.508839e-05 +5 ropt_net_192:5 5.508839e-05 +6 ropt_net_192:6 0.000414642 +7 ropt_net_192:7 0.000384006 +8 ropt_net_192:7 chany_top_in[8]:6 6.454397e-05 +9 ropt_net_192:6 chany_top_in[8]:7 6.454397e-05 +10 ropt_net_192:3 chany_top_in[8]:6 2.904479e-05 +11 ropt_net_192:2 chany_top_in[8]:7 2.904479e-05 +12 ropt_net_192:7 chany_top_in[14]:5 3.706053e-05 +13 ropt_net_192:7 chany_top_in[14]:7 1.463305e-06 +14 ropt_net_192:6 chany_top_in[14]:6 3.706053e-05 +15 ropt_net_192:6 chany_top_in[14]:8 1.463305e-06 +16 ropt_net_192:3 chany_top_in[14]:7 2.904479e-05 +17 ropt_net_192:2 chany_top_in[14]:8 2.904479e-05 + +*RES +0 BUFT_P_117:X ropt_net_192:7 0.152 +1 ropt_net_192:7 ropt_net_192:6 0.005305803 +2 ropt_net_192:6 ropt_net_192:5 0.0045 +3 ropt_net_192:5 ropt_net_192:4 0.0005267857 +4 ropt_net_192:3 ropt_net_192:2 0.0003370536 +5 ropt_net_192:4 ropt_net_192:3 0.0045 +6 ropt_net_192:2 ropt_mt_inst_831:A 0.152 + +*END + +*D_NET chany_bottom_out[14] 0.0005613982 //LENGTH 4.755 LUMPCC 0.0001123227 DR + +*CONN +*I ropt_mt_inst_875:X O *L 0 *C 99.360 3.740 +*P chany_bottom_out[14] O *L 0.7423 *C 97.520 1.290 +*N chany_bottom_out[14]:2 *C 97.520 3.695 +*N chany_bottom_out[14]:3 *C 97.565 3.740 +*N chany_bottom_out[14]:4 *C 99.323 3.740 + +*CAP +0 ropt_mt_inst_875:X 1e-06 +1 chany_bottom_out[14] 0.0001282053 +2 chany_bottom_out[14]:2 0.0001282053 +3 chany_bottom_out[14]:3 9.583245e-05 +4 chany_bottom_out[14]:4 9.583245e-05 +5 chany_bottom_out[14] ropt_net_228:4 9.754792e-06 +6 chany_bottom_out[14]:4 ropt_net_228:6 4.640656e-05 +7 chany_bottom_out[14]:3 ropt_net_228:5 4.640656e-05 +8 chany_bottom_out[14]:2 ropt_net_228:3 9.754792e-06 + +*RES +0 ropt_mt_inst_875:X chany_bottom_out[14]:4 0.152 +1 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.001569196 +2 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.0045 +3 chany_bottom_out[14]:2 chany_bottom_out[14] 0.002147322 + +*END + +*D_NET chany_top_in[13] 0.03015296 //LENGTH 182.830 LUMPCC 0.008110054 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 63.480 129.270 +*I mux_left_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 68.830 98.600 +*I mux_right_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 92.000 96.220 +*I mux_bottom_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.130 28.220 +*I BUFT_P_131:A I *L 0.001776 *C 91.080 6.800 +*N chany_top_in[13]:5 *C 72.280 28.220 +*N chany_top_in[13]:6 *C 91.118 6.800 +*N chany_top_in[13]:7 *C 91.495 6.800 +*N chany_top_in[13]:8 *C 91.540 6.845 +*N chany_top_in[13]:9 *C 91.540 22.383 +*N chany_top_in[13]:10 *C 91.532 22.440 +*N chany_top_in[13]:11 *C 74.068 22.440 +*N chany_top_in[13]:12 *C 74.060 22.498 +*N chany_top_in[13]:13 *C 74.060 27.835 +*N chany_top_in[13]:14 *C 74.015 27.880 +*N chany_top_in[13]:15 *C 72.680 27.880 +*N chany_top_in[13]:16 *C 71.168 28.220 +*N chany_top_in[13]:17 *C 72.680 28.190 +*N chany_top_in[13]:18 *C 72.680 28.220 +*N chany_top_in[13]:19 *C 72.680 28.220 +*N chany_top_in[13]:20 *C 72.680 28.228 +*N chany_top_in[13]:21 *C 72.680 78.055 +*N chany_top_in[13]:22 *C 92.000 96.220 +*N chany_top_in[13]:23 *C 92.000 95.880 +*N chany_top_in[13]:24 *C 92.000 95.835 +*N chany_top_in[13]:25 *C 92.000 95.258 +*N chany_top_in[13]:26 *C 91.993 95.200 +*N chany_top_in[13]:27 *C 72.700 95.200 +*N chany_top_in[13]:28 *C 72.680 95.200 +*N chany_top_in[13]:29 *C 72.680 98.940 +*N chany_top_in[13]:30 *C 71.050 98.940 +*N chany_top_in[13]:31 *C 68.868 98.600 +*N chany_top_in[13]:32 *C 71.760 98.600 +*N chany_top_in[13]:33 *C 71.760 98.940 +*N chany_top_in[13]:34 *C 71.760 98.940 +*N chany_top_in[13]:35 *C 71.758 98.940 +*N chany_top_in[13]:36 *C 71.760 98.940 +*N chany_top_in[13]:37 *C 71.760 119.672 +*N chany_top_in[13]:38 *C 71.740 119.680 +*N chany_top_in[13]:39 *C 63.488 119.680 +*N chany_top_in[13]:40 *C 63.480 119.738 + +*CAP +0 chany_top_in[13] 0.000547462 +1 mux_left_track_3\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_3\/mux_l1_in_0_:A0 1e-06 +4 BUFT_P_131:A 1e-06 +5 chany_top_in[13]:5 8.338339e-05 +6 chany_top_in[13]:6 4.558834e-05 +7 chany_top_in[13]:7 4.558834e-05 +8 chany_top_in[13]:8 0.0006349158 +9 chany_top_in[13]:9 0.0006349158 +10 chany_top_in[13]:10 0.001194696 +11 chany_top_in[13]:11 0.001194696 +12 chany_top_in[13]:12 0.0003663291 +13 chany_top_in[13]:13 0.0003663291 +14 chany_top_in[13]:14 0.0001029685 +15 chany_top_in[13]:15 0.0001340896 +16 chany_top_in[13]:16 0.0001195459 +17 chany_top_in[13]:17 0.000150667 +18 chany_top_in[13]:18 3.73064e-05 +19 chany_top_in[13]:19 8.338339e-05 +20 chany_top_in[13]:20 0.002546957 +21 chany_top_in[13]:21 0.003525326 +22 chany_top_in[13]:22 6.520485e-05 +23 chany_top_in[13]:23 6.973486e-05 +24 chany_top_in[13]:24 7.547343e-05 +25 chany_top_in[13]:25 7.547343e-05 +26 chany_top_in[13]:26 0.001118694 +27 chany_top_in[13]:27 0.001118694 +28 chany_top_in[13]:28 0.001259633 +29 chany_top_in[13]:29 0.0002230899 +30 chany_top_in[13]:30 7.952e-05 +31 chany_top_in[13]:31 0.000211147 +32 chany_top_in[13]:32 0.0002419734 +33 chany_top_in[13]:33 6.689307e-05 +34 chany_top_in[13]:34 3.528666e-05 +35 chany_top_in[13]:35 7.952e-05 +36 chany_top_in[13]:36 0.001761769 +37 chany_top_in[13]:37 0.001819943 +38 chany_top_in[13]:38 0.0006876239 +39 chany_top_in[13]:39 0.0006876239 +40 chany_top_in[13]:40 0.000547462 +41 chany_top_in[13]:11 chany_top_in[2]:20 8.855393e-05 +42 chany_top_in[13]:10 chany_top_in[2]:21 8.855393e-05 +43 chany_top_in[13]:27 chany_top_in[2]:26 0.0006464703 +44 chany_top_in[13]:26 chany_top_in[2]:25 0.0006464703 +45 chany_top_in[13]:20 chany_top_in[9]:18 0.0007387484 +46 chany_top_in[13]:38 chany_top_in[9]:38 1.48638e-05 +47 chany_top_in[13]:39 chany_top_in[9]:39 1.48638e-05 +48 chany_top_in[13]:21 chany_top_in[9]:19 0.0007387484 +49 chany_top_in[13]:13 chany_top_in[18]:14 1.361272e-07 +50 chany_top_in[13]:12 chany_top_in[18]:13 1.361272e-07 +51 chany_top_in[13]:20 chany_top_in[18]:24 0.0001732709 +52 chany_top_in[13]:20 chany_top_in[18]:31 0.0008055625 +53 chany_top_in[13]:28 chany_top_in[18]:32 0.0004676951 +54 chany_top_in[13]:21 chany_top_in[18]:31 0.000640966 +55 chany_top_in[13]:21 chany_top_in[18]:32 0.0008055625 +56 chany_top_in[13]:35 chanx_left_in[12]:36 3.302345e-05 +57 chany_top_in[13]:36 chanx_left_in[12]:36 9.935405e-05 +58 chany_top_in[13]:27 chanx_left_in[12]:32 0.0003992005 +59 chany_top_in[13]:26 chanx_left_in[12]:27 0.0003992005 +60 chany_top_in[13]:23 chanx_left_in[12]:22 1.532898e-07 +61 chany_top_in[13]:22 chanx_left_in[12]:23 1.532898e-07 +62 chany_top_in[13]:30 chanx_left_in[12]:35 3.302345e-05 +63 chany_top_in[13]:29 chanx_left_in[12]:35 9.935405e-05 +64 chany_top_in[13]:37 mux_tree_tapbuf_size12_0_sram[1]:25 0.000371455 +65 chany_top_in[13]:36 mux_tree_tapbuf_size12_0_sram[1]:23 4.419942e-05 +66 chany_top_in[13]:36 mux_tree_tapbuf_size12_0_sram[1]:24 0.000371455 +67 chany_top_in[13]:29 mux_tree_tapbuf_size12_0_sram[1]:22 4.419942e-05 +68 chany_top_in[13]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001723399 +69 chany_top_in[13]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001723399 + +*RES +0 chany_top_in[13] chany_top_in[13]:40 0.008511161 +1 chany_top_in[13]:14 chany_top_in[13]:13 0.0045 +2 chany_top_in[13]:13 chany_top_in[13]:12 0.004765625 +3 chany_top_in[13]:12 chany_top_in[13]:11 0.00341 +4 chany_top_in[13]:11 chany_top_in[13]:10 0.002736183 +5 chany_top_in[13]:9 chany_top_in[13]:8 0.01387277 +6 chany_top_in[13]:10 chany_top_in[13]:9 0.00341 +7 chany_top_in[13]:7 chany_top_in[13]:6 0.0003370536 +8 chany_top_in[13]:8 chany_top_in[13]:7 0.0045 +9 chany_top_in[13]:6 BUFT_P_131:A 0.152 +10 chany_top_in[13]:17 chany_top_in[13]:16 0.001350446 +11 chany_top_in[13]:17 chany_top_in[13]:15 0.0002767857 +12 chany_top_in[13]:18 chany_top_in[13]:17 0.0045 +13 chany_top_in[13]:19 chany_top_in[13]:18 0.00341 +14 chany_top_in[13]:19 chany_top_in[13]:5 5.69697e-05 +15 chany_top_in[13]:20 chany_top_in[13]:19 0.00341 +16 chany_top_in[13]:38 chany_top_in[13]:37 0.00341 +17 chany_top_in[13]:37 chany_top_in[13]:36 0.003248092 +18 chany_top_in[13]:40 chany_top_in[13]:39 0.00341 +19 chany_top_in[13]:39 chany_top_in[13]:38 0.001292891 +20 chany_top_in[13]:16 mux_bottom_track_3\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[13]:35 chany_top_in[13]:34 0.00341 +22 chany_top_in[13]:35 chany_top_in[13]:30 0.0001039141 +23 chany_top_in[13]:36 chany_top_in[13]:35 0.00341 +24 chany_top_in[13]:36 chany_top_in[13]:29 0.0001441333 +25 chany_top_in[13]:34 chany_top_in[13]:33 0.0045 +26 chany_top_in[13]:33 chany_top_in[13]:32 0.0003035715 +27 chany_top_in[13]:31 mux_left_track_3\/mux_l1_in_0_:A0 0.152 +28 chany_top_in[13]:27 chany_top_in[13]:26 0.003022491 +29 chany_top_in[13]:28 chany_top_in[13]:27 0.00341 +30 chany_top_in[13]:28 chany_top_in[13]:21 0.00268605 +31 chany_top_in[13]:25 chany_top_in[13]:24 0.000515625 +32 chany_top_in[13]:26 chany_top_in[13]:25 0.00341 +33 chany_top_in[13]:23 chany_top_in[13]:22 0.0001465517 +34 chany_top_in[13]:24 chany_top_in[13]:23 0.0045 +35 chany_top_in[13]:22 mux_right_track_2\/mux_l1_in_1_:A1 0.152 +36 chany_top_in[13]:32 chany_top_in[13]:31 0.002582589 +37 chany_top_in[13]:15 chany_top_in[13]:14 0.001191964 +38 chany_top_in[13]:29 chany_top_in[13]:28 0.0005859333 +39 chany_top_in[13]:21 chany_top_in[13]:20 0.007806308 + +*END + +*D_NET chany_bottom_in[5] 0.02354844 //LENGTH 167.915 LUMPCC 0.007493309 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 75.900 1.290 +*I mux_left_track_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 50.430 82.280 +*I mux_top_track_4\/mux_l2_in_5_:A1 I *L 0.00198 *C 56.120 85.340 +*I BUFT_P_122:A I *L 0.001776 *C 59.340 123.760 +*I mux_right_track_4\/mux_l2_in_5_:A1 I *L 0.00198 *C 79.220 74.460 +*N chany_bottom_in[5]:5 *C 79.183 74.460 +*N chany_bottom_in[5]:6 *C 76.360 74.460 +*N chany_bottom_in[5]:7 *C 59.378 123.760 +*N chany_bottom_in[5]:8 *C 62.055 123.760 +*N chany_bottom_in[5]:9 *C 62.100 123.715 +*N chany_bottom_in[5]:10 *C 62.100 121.040 +*N chany_bottom_in[5]:11 *C 63.020 121.040 +*N chany_bottom_in[5]:12 *C 63.020 118.320 +*N chany_bottom_in[5]:13 *C 63.940 118.320 +*N chany_bottom_in[5]:14 *C 56.158 85.340 +*N chany_bottom_in[5]:15 *C 56.535 85.340 +*N chany_bottom_in[5]:16 *C 56.580 85.295 +*N chany_bottom_in[5]:17 *C 50.468 82.280 +*N chany_bottom_in[5]:18 *C 56.535 82.280 +*N chany_bottom_in[5]:19 *C 56.580 82.280 +*N chany_bottom_in[5]:20 *C 56.580 80.978 +*N chany_bottom_in[5]:21 *C 56.588 80.920 +*N chany_bottom_in[5]:22 *C 63.933 80.920 +*N chany_bottom_in[5]:23 *C 63.940 80.920 +*N chany_bottom_in[5]:24 *C 63.940 75.525 +*N chany_bottom_in[5]:25 *C 63.985 75.480 +*N chany_bottom_in[5]:26 *C 76.360 75.450 +*N chany_bottom_in[5]:27 *C 76.360 75.435 +*N chany_bottom_in[5]:28 *C 76.360 55.477 +*N chany_bottom_in[5]:29 *C 76.353 55.420 +*N chany_bottom_in[5]:30 *C 75.460 55.420 +*N chany_bottom_in[5]:31 *C 75.440 55.413 +*N chany_bottom_in[5]:32 *C 75.440 5.448 +*N chany_bottom_in[5]:33 *C 75.455 5.440 +*N chany_bottom_in[5]:34 *C 75.898 5.440 +*N chany_bottom_in[5]:35 *C 75.900 5.383 + +*CAP +0 chany_bottom_in[5] 0.0002475962 +1 mux_left_track_5\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_4\/mux_l2_in_5_:A1 1e-06 +3 BUFT_P_122:A 1e-06 +4 mux_right_track_4\/mux_l2_in_5_:A1 1e-06 +5 chany_bottom_in[5]:5 0.000168111 +6 chany_bottom_in[5]:6 0.0002401385 +7 chany_bottom_in[5]:7 0.0002133606 +8 chany_bottom_in[5]:8 0.0002133606 +9 chany_bottom_in[5]:9 0.0001498129 +10 chany_bottom_in[5]:10 0.0001852197 +11 chany_bottom_in[5]:11 0.0002128953 +12 chany_bottom_in[5]:12 0.0002297967 +13 chany_bottom_in[5]:13 0.001743063 +14 chany_bottom_in[5]:14 7.178186e-05 +15 chany_bottom_in[5]:15 7.178186e-05 +16 chany_bottom_in[5]:16 0.0002165082 +17 chany_bottom_in[5]:17 0.0004427869 +18 chany_bottom_in[5]:18 0.0004427869 +19 chany_bottom_in[5]:19 0.0003554788 +20 chany_bottom_in[5]:20 0.000103908 +21 chany_bottom_in[5]:21 0.0006478354 +22 chany_bottom_in[5]:22 0.0006478354 +23 chany_bottom_in[5]:23 0.002097843 +24 chany_bottom_in[5]:24 0.0003693748 +25 chany_bottom_in[5]:25 0.0006801944 +26 chany_bottom_in[5]:26 0.0007522219 +27 chany_bottom_in[5]:27 0.0009741545 +28 chany_bottom_in[5]:28 0.0009741545 +29 chany_bottom_in[5]:29 0.0001122162 +30 chany_bottom_in[5]:30 0.0001122162 +31 chany_bottom_in[5]:31 0.001516392 +32 chany_bottom_in[5]:32 0.001516392 +33 chany_bottom_in[5]:33 4.715739e-05 +34 chany_bottom_in[5]:34 4.715739e-05 +35 chany_bottom_in[5]:35 0.0002475962 +36 chany_bottom_in[5]:27 chany_top_in[6]:15 0.0001240791 +37 chany_bottom_in[5]:27 chany_top_in[6]:16 5.791374e-05 +38 chany_bottom_in[5]:27 chany_top_in[6]:20 1.519516e-05 +39 chany_bottom_in[5]:27 chany_top_in[6]:21 8.614894e-05 +40 chany_bottom_in[5]:28 chany_top_in[6]:12 0.0001240791 +41 chany_bottom_in[5]:28 chany_top_in[6]:15 5.791374e-05 +42 chany_bottom_in[5]:28 chany_top_in[6]:17 1.519516e-05 +43 chany_bottom_in[5]:28 chany_top_in[6]:20 8.614894e-05 +44 chany_bottom_in[5]:31 chany_top_in[6]:9 5.175602e-06 +45 chany_bottom_in[5]:32 chany_top_in[6]:8 5.175602e-06 +46 chany_bottom_in[5]:31 chany_top_in[9]:19 0.0007396323 +47 chany_bottom_in[5]:33 chany_top_in[9]:17 7.084285e-06 +48 chany_bottom_in[5]:32 chany_top_in[9]:18 0.0007396323 +49 chany_bottom_in[5]:34 chany_top_in[9]:16 7.084285e-06 +50 chany_bottom_in[5]:24 prog_clk[0]:419 1.908928e-08 +51 chany_bottom_in[5]:23 prog_clk[0]:564 2.411611e-05 +52 chany_bottom_in[5]:23 prog_clk[0]:568 6.947588e-06 +53 chany_bottom_in[5]:23 prog_clk[0]:571 5.743335e-05 +54 chany_bottom_in[5]:23 prog_clk[0]:567 2.287437e-06 +55 chany_bottom_in[5]:23 prog_clk[0]:418 1.908928e-08 +56 chany_bottom_in[5]:23 prog_clk[0]:419 2.531005e-08 +57 chany_bottom_in[5]:23 prog_clk[0]:572 0.0001550544 +58 chany_bottom_in[5]:31 prog_clk[0]:342 1.303152e-05 +59 chany_bottom_in[5]:32 prog_clk[0]:341 1.303152e-05 +60 chany_bottom_in[5]:13 prog_clk[0]:564 6.947588e-06 +61 chany_bottom_in[5]:13 prog_clk[0]:568 2.287437e-06 +62 chany_bottom_in[5]:13 prog_clk[0]:571 0.0001550544 +63 chany_bottom_in[5]:13 prog_clk[0]:527 2.411611e-05 +64 chany_bottom_in[5]:13 prog_clk[0]:418 2.531005e-08 +65 chany_bottom_in[5]:13 prog_clk[0]:524 5.743335e-05 +66 chany_bottom_in[5]:27 chany_bottom_in[19]:10 9.740587e-06 +67 chany_bottom_in[5]:27 chany_bottom_in[19]:13 1.823213e-05 +68 chany_bottom_in[5]:28 chany_bottom_in[19]:13 9.740587e-06 +69 chany_bottom_in[5]:28 chany_bottom_in[19]:14 1.823213e-05 +70 chany_bottom_in[5]:31 chany_bottom_in[19]:17 0.0006942847 +71 chany_bottom_in[5]:32 chany_bottom_in[19]:18 0.0006942847 +72 chany_bottom_in[5]:27 chanx_left_in[1]:9 1.479852e-05 +73 chany_bottom_in[5]:28 chanx_left_in[1]:10 1.479852e-05 +74 chany_bottom_in[5]:31 chanx_left_in[1]:9 0.0006674576 +75 chany_bottom_in[5]:32 chanx_left_in[1]:10 0.0006674576 +76 chany_bottom_in[5]:23 mux_tree_tapbuf_size12_1_sram[0]:27 0.0002990881 +77 chany_bottom_in[5]:23 mux_tree_tapbuf_size12_1_sram[0]:31 3.602016e-05 +78 chany_bottom_in[5]:23 mux_tree_tapbuf_size12_1_sram[0]:22 0.0001569165 +79 chany_bottom_in[5]:13 mux_tree_tapbuf_size12_1_sram[0]:32 3.602016e-05 +80 chany_bottom_in[5]:13 mux_tree_tapbuf_size12_1_sram[0]:31 0.0002990881 +81 chany_bottom_in[5]:13 mux_tree_tapbuf_size12_1_sram[0]:23 0.0001569165 +82 chany_bottom_in[5]:23 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 7.449321e-05 +83 chany_bottom_in[5]:13 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 7.449321e-05 +84 chany_bottom_in[5]:25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002799815 +85 chany_bottom_in[5]:26 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0002799815 +86 chany_bottom_in[5]:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 8.836913e-06 +87 chany_bottom_in[5]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.000111641 +88 chany_bottom_in[5]:26 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 8.836913e-06 +89 chany_bottom_in[5]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.000111641 +90 chany_bottom_in[5]:9 ropt_net_210:4 5.867111e-05 +91 chany_bottom_in[5]:10 ropt_net_210:6 2.234799e-05 +92 chany_bottom_in[5]:10 ropt_net_210:5 5.867111e-05 +93 chany_bottom_in[5]:11 ropt_net_210:7 2.234799e-05 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:35 0.003654018 +1 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.002390625 +2 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.0045 +3 chany_bottom_in[5]:7 BUFT_P_122:A 0.152 +4 chany_bottom_in[5]:25 chany_bottom_in[5]:24 0.0045 +5 chany_bottom_in[5]:24 chany_bottom_in[5]:23 0.004816965 +6 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.001162947 +7 chany_bottom_in[5]:21 chany_bottom_in[5]:20 0.00341 +8 chany_bottom_in[5]:23 chany_bottom_in[5]:22 0.00341 +9 chany_bottom_in[5]:23 chany_bottom_in[5]:13 0.03339286 +10 chany_bottom_in[5]:22 chany_bottom_in[5]:21 0.001150717 +11 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.0003370536 +12 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.0045 +13 chany_bottom_in[5]:14 mux_top_track_4\/mux_l2_in_5_:A1 0.152 +14 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.005417411 +15 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.0045 +16 chany_bottom_in[5]:19 chany_bottom_in[5]:16 0.002691964 +17 chany_bottom_in[5]:17 mux_left_track_5\/mux_l2_in_2_:A0 0.152 +18 chany_bottom_in[5]:5 mux_right_track_4\/mux_l2_in_5_:A1 0.152 +19 chany_bottom_in[5]:26 chany_bottom_in[5]:25 0.01104911 +20 chany_bottom_in[5]:26 chany_bottom_in[5]:6 0.0008839286 +21 chany_bottom_in[5]:27 chany_bottom_in[5]:26 0.0045 +22 chany_bottom_in[5]:28 chany_bottom_in[5]:27 0.0178192 +23 chany_bottom_in[5]:29 chany_bottom_in[5]:28 0.00341 +24 chany_bottom_in[5]:30 chany_bottom_in[5]:29 0.000139825 +25 chany_bottom_in[5]:31 chany_bottom_in[5]:30 0.00341 +26 chany_bottom_in[5]:33 chany_bottom_in[5]:32 0.00341 +27 chany_bottom_in[5]:32 chany_bottom_in[5]:31 0.007827849 +28 chany_bottom_in[5]:35 chany_bottom_in[5]:34 0.00341 +29 chany_bottom_in[5]:34 chany_bottom_in[5]:33 6.499219e-05 +30 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.00252009 +31 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.002388393 +32 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.0008214286 +33 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.002428571 +34 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.0008214285 + +*END + +*D_NET chanx_left_in[17] 0.02446642 //LENGTH 165.322 LUMPCC 0.008233319 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 55.760 +*I mux_top_track_16\/mux_l2_in_3_:A1 I *L 0.00198 *C 48.665 47.260 +*I mux_bottom_track_17\/mux_l2_in_3_:A1 I *L 0.00198 *C 48.665 41.820 +*I mux_right_track_16\/mux_l2_in_3_:A1 I *L 0.00198 *C 88.780 50.660 +*I ropt_mt_inst_794:A I *L 0.001767 *C 134.780 53.040 +*N chanx_left_in[17]:5 *C 134.743 53.040 +*N chanx_left_in[17]:6 *C 132.065 53.040 +*N chanx_left_in[17]:7 *C 132.020 52.995 +*N chanx_left_in[17]:8 *C 132.020 50.705 +*N chanx_left_in[17]:9 *C 131.975 50.660 +*N chanx_left_in[17]:10 *C 119.185 50.660 +*N chanx_left_in[17]:11 *C 119.140 50.615 +*N chanx_left_in[17]:12 *C 119.140 46.977 +*N chanx_left_in[17]:13 *C 119.133 46.920 +*N chanx_left_in[17]:14 *C 88.780 50.660 +*N chanx_left_in[17]:15 *C 88.780 50.615 +*N chanx_left_in[17]:16 *C 88.780 46.977 +*N chanx_left_in[17]:17 *C 88.780 46.920 +*N chanx_left_in[17]:18 *C 48.703 41.820 +*N chanx_left_in[17]:19 *C 49.175 41.820 +*N chanx_left_in[17]:20 *C 49.220 41.865 +*N chanx_left_in[17]:21 *C 48.703 47.260 +*N chanx_left_in[17]:22 *C 49.220 47.260 +*N chanx_left_in[17]:23 *C 49.220 46.920 +*N chanx_left_in[17]:24 *C 49.220 46.920 +*N chanx_left_in[17]:25 *C 49.220 46.920 +*N chanx_left_in[17]:26 *C 49.220 47.600 +*N chanx_left_in[17]:27 *C 38.640 47.600 +*N chanx_left_in[17]:28 *C 38.640 46.920 +*N chanx_left_in[17]:29 *C 24.380 46.920 +*N chanx_left_in[17]:30 *C 24.380 47.600 +*N chanx_left_in[17]:31 *C 2.780 47.600 +*N chanx_left_in[17]:32 *C 2.760 47.608 +*N chanx_left_in[17]:33 *C 2.760 55.753 +*N chanx_left_in[17]:34 *C 2.740 55.760 + +*CAP +0 chanx_left_in[17] 0.0001575081 +1 mux_top_track_16\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_track_17\/mux_l2_in_3_:A1 1e-06 +3 mux_right_track_16\/mux_l2_in_3_:A1 1e-06 +4 ropt_mt_inst_794:A 1e-06 +5 chanx_left_in[17]:5 0.0001506347 +6 chanx_left_in[17]:6 0.0001506347 +7 chanx_left_in[17]:7 0.0001161224 +8 chanx_left_in[17]:8 0.0001161224 +9 chanx_left_in[17]:9 0.0006703393 +10 chanx_left_in[17]:10 0.0006703393 +11 chanx_left_in[17]:11 0.000193296 +12 chanx_left_in[17]:12 0.000193296 +13 chanx_left_in[17]:13 0.001045455 +14 chanx_left_in[17]:14 3.397984e-05 +15 chanx_left_in[17]:15 0.0002454581 +16 chanx_left_in[17]:16 0.0002454581 +17 chanx_left_in[17]:17 0.0029919 +18 chanx_left_in[17]:18 5.918006e-05 +19 chanx_left_in[17]:19 5.918006e-05 +20 chanx_left_in[17]:20 0.0003294651 +21 chanx_left_in[17]:21 5.192477e-05 +22 chanx_left_in[17]:22 8.074762e-05 +23 chanx_left_in[17]:23 6.245132e-05 +24 chanx_left_in[17]:24 0.000368265 +25 chanx_left_in[17]:25 0.002010708 +26 chanx_left_in[17]:26 0.0005056524 +27 chanx_left_in[17]:27 0.0005010964 +28 chanx_left_in[17]:28 0.0008568408 +29 chanx_left_in[17]:29 0.0008425761 +30 chanx_left_in[17]:30 0.001164839 +31 chanx_left_in[17]:31 0.001119397 +32 chanx_left_in[17]:32 0.0005393601 +33 chanx_left_in[17]:33 0.0005393601 +34 chanx_left_in[17]:34 0.0001575081 +35 chanx_left_in[17]:25 chanx_right_in[4]:17 0.0002917077 +36 chanx_left_in[17]:25 chanx_right_in[4]:18 9.756529e-05 +37 chanx_left_in[17]:17 chanx_right_in[4]:18 0.0002917077 +38 chanx_left_in[17]:17 chanx_right_in[4]:19 9.756529e-05 +39 chanx_left_in[17]:31 chanx_right_in[4]:17 2.434159e-05 +40 chanx_left_in[17]:30 chanx_right_in[4]:18 2.434159e-05 +41 chanx_left_in[17]:29 chanx_right_in[4]:17 0.0001903564 +42 chanx_left_in[17]:28 chanx_right_in[4]:18 0.0001903564 +43 chanx_left_in[17]:27 chanx_right_in[4]:17 9.405607e-05 +44 chanx_left_in[17]:26 chanx_right_in[4]:18 9.405607e-05 +45 chanx_left_in[17] chanx_right_in[8]:9 4.462871e-05 +46 chanx_left_in[17]:13 chanx_right_in[8]:29 0.0003134895 +47 chanx_left_in[17]:25 chanx_right_in[8]:28 4.945088e-05 +48 chanx_left_in[17]:17 chanx_right_in[8]:28 0.0003134895 +49 chanx_left_in[17]:17 chanx_right_in[8]:29 4.945088e-05 +50 chanx_left_in[17]:34 chanx_right_in[8]:10 4.462871e-05 +51 chanx_left_in[17]:13 chanx_right_in[10]:33 9.455971e-05 +52 chanx_left_in[17]:13 chanx_right_in[10]:34 0.0005002934 +53 chanx_left_in[17]:10 chanx_right_in[10]:33 6.086899e-06 +54 chanx_left_in[17]:9 chanx_right_in[10]:34 6.086899e-06 +55 chanx_left_in[17]:25 chanx_right_in[10]:27 0.0006957432 +56 chanx_left_in[17]:25 chanx_right_in[10]:28 2.182699e-05 +57 chanx_left_in[17]:17 chanx_right_in[10]:28 0.0007903029 +58 chanx_left_in[17]:17 chanx_right_in[10]:33 0.0005221204 +59 chanx_left_in[17]:29 chanx_right_in[10]:27 1.596879e-05 +60 chanx_left_in[17]:28 chanx_right_in[10]:28 1.596879e-05 +61 chanx_left_in[17]:27 chanx_right_in[10]:27 0.0005852912 +62 chanx_left_in[17]:26 chanx_right_in[10]:28 0.0005852912 +63 chanx_left_in[17]:13 prog_clk[0]:216 0.000204618 +64 chanx_left_in[17]:16 prog_clk[0]:221 7.956917e-07 +65 chanx_left_in[17]:17 prog_clk[0]:217 0.000204618 +66 chanx_left_in[17]:15 prog_clk[0]:218 7.956917e-07 +67 chanx_left_in[17]:30 prog_clk[0]:636 1.194712e-05 +68 chanx_left_in[17]:29 prog_clk[0]:480 0.0002219342 +69 chanx_left_in[17]:29 prog_clk[0]:637 1.194712e-05 +70 chanx_left_in[17]:28 prog_clk[0]:479 0.0002219342 +71 chanx_left_in[17]:31 chanx_left_in[19] 0.0003935799 +72 chanx_left_in[17]:30 chanx_left_in[19]:20 0.0003935799 +73 chanx_left_in[17]:13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000152947 +74 chanx_left_in[17]:25 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001054717 +75 chanx_left_in[17]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000152947 +76 chanx_left_in[17]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001054717 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:34 0.0002365667 +1 chanx_left_in[17]:12 chanx_left_in[17]:11 0.003247768 +2 chanx_left_in[17]:13 chanx_left_in[17]:12 0.00341 +3 chanx_left_in[17]:10 chanx_left_in[17]:9 0.01141964 +4 chanx_left_in[17]:11 chanx_left_in[17]:10 0.0045 +5 chanx_left_in[17]:9 chanx_left_in[17]:8 0.0045 +6 chanx_left_in[17]:8 chanx_left_in[17]:7 0.002044643 +7 chanx_left_in[17]:6 chanx_left_in[17]:5 0.002390625 +8 chanx_left_in[17]:7 chanx_left_in[17]:6 0.0045 +9 chanx_left_in[17]:5 ropt_mt_inst_794:A 0.152 +10 chanx_left_in[17]:19 chanx_left_in[17]:18 0.000421875 +11 chanx_left_in[17]:20 chanx_left_in[17]:19 0.0045 +12 chanx_left_in[17]:18 mux_bottom_track_17\/mux_l2_in_3_:A1 0.152 +13 chanx_left_in[17]:24 chanx_left_in[17]:23 0.0045 +14 chanx_left_in[17]:24 chanx_left_in[17]:20 0.004513393 +15 chanx_left_in[17]:25 chanx_left_in[17]:24 0.00341 +16 chanx_left_in[17]:25 chanx_left_in[17]:17 0.006197733 +17 chanx_left_in[17]:16 chanx_left_in[17]:15 0.003247768 +18 chanx_left_in[17]:17 chanx_left_in[17]:16 0.00341 +19 chanx_left_in[17]:17 chanx_left_in[17]:13 0.004755225 +20 chanx_left_in[17]:14 mux_right_track_16\/mux_l2_in_3_:A1 0.152 +21 chanx_left_in[17]:15 chanx_left_in[17]:14 0.0045 +22 chanx_left_in[17]:23 chanx_left_in[17]:22 0.0003035715 +23 chanx_left_in[17]:21 mux_top_track_16\/mux_l2_in_3_:A1 0.152 +24 chanx_left_in[17]:31 chanx_left_in[17]:30 0.003384 +25 chanx_left_in[17]:32 chanx_left_in[17]:31 0.00341 +26 chanx_left_in[17]:34 chanx_left_in[17]:33 0.00341 +27 chanx_left_in[17]:33 chanx_left_in[17]:32 0.00127605 +28 chanx_left_in[17]:22 chanx_left_in[17]:21 0.0004620536 +29 chanx_left_in[17]:30 chanx_left_in[17]:29 0.0001065333 +30 chanx_left_in[17]:29 chanx_left_in[17]:28 0.002234067 +31 chanx_left_in[17]:28 chanx_left_in[17]:27 0.0001065333 +32 chanx_left_in[17]:27 chanx_left_in[17]:26 0.001657533 +33 chanx_left_in[17]:26 chanx_left_in[17]:25 0.0001065333 + +*END + +*D_NET chany_bottom_in[0] 0.01915151 //LENGTH 123.095 LUMPCC 0.008001971 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 82.340 1.290 +*I mux_right_track_24\/mux_l1_in_2_:A0 I *L 0.001631 *C 89.875 82.620 +*I mux_left_track_3\/mux_l1_in_2_:A0 I *L 0.001631 *C 60.090 87.720 +*N chany_bottom_in[0]:3 *C 60.128 87.720 +*N chany_bottom_in[0]:4 *C 62.515 87.720 +*N chany_bottom_in[0]:5 *C 62.560 87.675 +*N chany_bottom_in[0]:6 *C 62.560 87.098 +*N chany_bottom_in[0]:7 *C 62.568 87.040 +*N chany_bottom_in[0]:8 *C 80.020 87.040 +*N chany_bottom_in[0]:9 *C 80.040 87.032 +*N chany_bottom_in[0]:10 *C 89.838 82.620 +*N chany_bottom_in[0]:11 *C 86.065 82.620 +*N chany_bottom_in[0]:12 *C 86.020 82.575 +*N chany_bottom_in[0]:13 *C 86.020 80.978 +*N chany_bottom_in[0]:14 *C 86.013 80.920 +*N chany_bottom_in[0]:15 *C 80.060 80.920 +*N chany_bottom_in[0]:16 *C 80.040 80.920 +*N chany_bottom_in[0]:17 *C 80.040 53.915 +*N chany_bottom_in[0]:18 *C 80.040 4.088 +*N chany_bottom_in[0]:19 *C 80.060 4.080 +*N chany_bottom_in[0]:20 *C 82.333 4.080 +*N chany_bottom_in[0]:21 *C 82.340 4.022 + +*CAP +0 chany_bottom_in[0] 0.0001687935 +1 mux_right_track_24\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_3\/mux_l1_in_2_:A0 1e-06 +3 chany_bottom_in[0]:3 0.000189806 +4 chany_bottom_in[0]:4 0.000189806 +5 chany_bottom_in[0]:5 5.816334e-05 +6 chany_bottom_in[0]:6 5.816334e-05 +7 chany_bottom_in[0]:7 0.001648911 +8 chany_bottom_in[0]:8 0.001648911 +9 chany_bottom_in[0]:9 0.0002352323 +10 chany_bottom_in[0]:10 0.0002553137 +11 chany_bottom_in[0]:11 0.0002553137 +12 chany_bottom_in[0]:12 0.0001184511 +13 chany_bottom_in[0]:13 0.0001184511 +14 chany_bottom_in[0]:14 0.0004888567 +15 chany_bottom_in[0]:15 0.0004888567 +16 chany_bottom_in[0]:16 0.0009791319 +17 chany_bottom_in[0]:17 0.002255745 +18 chany_bottom_in[0]:18 0.001511846 +19 chany_bottom_in[0]:19 0.0001544975 +20 chany_bottom_in[0]:20 0.0001544975 +21 chany_bottom_in[0]:21 0.0001687935 +22 chany_bottom_in[0]:16 chany_top_in[17]:32 8.345894e-05 +23 chany_bottom_in[0]:16 chany_top_in[17]:33 0.0002345975 +24 chany_bottom_in[0]:9 chany_top_in[17]:33 8.345894e-05 +25 chany_bottom_in[0]:17 chany_top_in[17]:32 0.0002345975 +26 chany_bottom_in[0]:16 chany_bottom_in[9]:33 2.758938e-05 +27 chany_bottom_in[0]:18 chany_bottom_in[9]:34 0.0002592 +28 chany_bottom_in[0]:17 chany_bottom_in[9]:33 0.0002592 +29 chany_bottom_in[0]:17 chany_bottom_in[9]:34 2.758938e-05 +30 chany_bottom_in[0]:18 chany_bottom_in[12]:29 0.0007580462 +31 chany_bottom_in[0]:17 chany_bottom_in[12]:28 0.0007580462 +32 chany_bottom_in[0]:16 chanx_left_in[12]:11 0.0002651012 +33 chany_bottom_in[0]:16 chanx_left_in[12]:12 0.001170562 +34 chany_bottom_in[0]:9 chanx_left_in[12]:12 0.0002651012 +35 chany_bottom_in[0]:18 chanx_left_in[12]:11 0.0005653842 +36 chany_bottom_in[0]:17 chanx_left_in[12]:11 0.001170562 +37 chany_bottom_in[0]:17 chanx_left_in[12]:12 0.0005653842 +38 chany_bottom_in[0]:18 prog_clk[0]:302 0.000462536 +39 chany_bottom_in[0]:18 prog_clk[0]:336 7.918605e-06 +40 chany_bottom_in[0]:17 prog_clk[0]:301 0.000462536 +41 chany_bottom_in[0]:17 prog_clk[0]:328 7.918605e-06 +42 chany_bottom_in[0]:16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 6.545506e-06 +43 chany_bottom_in[0]:16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:18 0.0001600469 +44 chany_bottom_in[0]:17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:19 0.0001600469 +45 chany_bottom_in[0]:17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 6.545506e-06 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:21 0.002439732 +1 chany_bottom_in[0]:15 chany_bottom_in[0]:14 0.0009325583 +2 chany_bottom_in[0]:16 chany_bottom_in[0]:15 0.00341 +3 chany_bottom_in[0]:16 chany_bottom_in[0]:9 0.0009576249 +4 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.001426339 +5 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.00341 +6 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.003368304 +7 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.0045 +8 chany_bottom_in[0]:10 mux_right_track_24\/mux_l1_in_2_:A0 0.152 +9 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.002734225 +10 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.00341 +11 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.000515625 +12 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.00341 +13 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.002131697 +14 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.0045 +15 chany_bottom_in[0]:3 mux_left_track_3\/mux_l1_in_2_:A0 0.152 +16 chany_bottom_in[0]:19 chany_bottom_in[0]:18 0.00341 +17 chany_bottom_in[0]:18 chany_bottom_in[0]:17 0.007806308 +18 chany_bottom_in[0]:21 chany_bottom_in[0]:20 0.00341 +19 chany_bottom_in[0]:20 chany_bottom_in[0]:19 0.000356025 +20 chany_bottom_in[0]:17 chany_bottom_in[0]:16 0.004230783 + +*END + +*D_NET chany_top_out[0] 0.002191198 //LENGTH 16.145 LUMPCC 0.0003194563 DR + +*CONN +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 83.665 121.040 +*P chany_top_out[0] O *L 0.7423 *C 76.820 129.235 +*N chany_top_out[0]:2 *C 76.820 126.185 +*N chany_top_out[0]:3 *C 76.865 126.140 +*N chany_top_out[0]:4 *C 81.835 126.140 +*N chany_top_out[0]:5 *C 81.880 126.095 +*N chany_top_out[0]:6 *C 81.880 121.085 +*N chany_top_out[0]:7 *C 81.925 121.040 +*N chany_top_out[0]:8 *C 83.627 121.040 + +*CAP +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[0] 0.0001887691 +2 chany_top_out[0]:2 0.0001887691 +3 chany_top_out[0]:3 0.0003081665 +4 chany_top_out[0]:4 0.0003081665 +5 chany_top_out[0]:5 0.0003472483 +6 chany_top_out[0]:6 0.0003472483 +7 chany_top_out[0]:7 9.118683e-05 +8 chany_top_out[0]:8 9.118683e-05 +9 chany_top_out[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 7.191346e-06 +10 chany_top_out[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 7.547557e-05 +11 chany_top_out[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 7.191346e-06 +12 chany_top_out[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 7.547557e-05 +13 chany_top_out[0]:3 ropt_net_197:6 7.706123e-05 +14 chany_top_out[0]:4 ropt_net_197:5 7.706123e-05 + +*RES +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[0]:8 0.152 +1 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +2 chany_top_out[0]:2 chany_top_out[0] 0.002723215 +3 chany_top_out[0]:4 chany_top_out[0]:3 0.004437501 +4 chany_top_out[0]:5 chany_top_out[0]:4 0.0045 +5 chany_top_out[0]:7 chany_top_out[0]:6 0.0045 +6 chany_top_out[0]:6 chany_top_out[0]:5 0.004473215 +7 chany_top_out[0]:8 chany_top_out[0]:7 0.00152009 + +*END + +*D_NET chanx_left_out[2] 0.0006798866 //LENGTH 5.590 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 80.580 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 82.960 +*N chanx_left_out[2]:2 *C 2.752 82.960 +*N chanx_left_out[2]:3 *C 2.760 82.903 +*N chanx_left_out[2]:4 *C 2.760 80.625 +*N chanx_left_out[2]:5 *C 2.805 80.580 +*N chanx_left_out[2]:6 *C 3.588 80.580 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 0.0001165659 +2 chanx_left_out[2]:2 0.0001165659 +3 chanx_left_out[2]:3 0.0001629836 +4 chanx_left_out[2]:4 0.0001629836 +5 chanx_left_out[2]:5 5.989375e-05 +6 chanx_left_out[2]:6 5.989375e-05 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:6 0.152 +1 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0006986608 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.002033482 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.000238525 + +*END + +*D_NET mux_tree_tapbuf_size10_2_sram[3] 0.001555517 //LENGTH 11.760 LUMPCC 0.0001069367 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 57.810 80.165 +*I mem_top_track_24\/FTB_15__66:A I *L 0.001746 *C 66.240 80.240 +*I mux_top_track_24\/mux_l4_in_0_:S I *L 0.00357 *C 66.600 78.200 +*N mux_tree_tapbuf_size10_2_sram[3]:3 *C 66.585 78.200 +*N mux_tree_tapbuf_size10_2_sram[3]:4 *C 66.263 78.200 +*N mux_tree_tapbuf_size10_2_sram[3]:5 *C 66.240 78.245 +*N mux_tree_tapbuf_size10_2_sram[3]:6 *C 66.240 80.195 +*N mux_tree_tapbuf_size10_2_sram[3]:7 *C 66.203 80.240 +*N mux_tree_tapbuf_size10_2_sram[3]:8 *C 57.848 80.225 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_24\/FTB_15__66:A 1e-06 +2 mux_top_track_24\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_2_sram[3]:3 6.033215e-05 +4 mux_tree_tapbuf_size10_2_sram[3]:4 6.033215e-05 +5 mux_tree_tapbuf_size10_2_sram[3]:5 0.0001357526 +6 mux_tree_tapbuf_size10_2_sram[3]:6 0.0001357526 +7 mux_tree_tapbuf_size10_2_sram[3]:7 0.0005267051 +8 mux_tree_tapbuf_size10_2_sram[3]:8 0.0005267051 +9 mux_tree_tapbuf_size10_2_sram[3]:7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 5.346836e-05 +10 mux_tree_tapbuf_size10_2_sram[3]:8 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 5.346836e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_2_sram[3]:8 0.152 +1 mux_tree_tapbuf_size10_2_sram[3]:7 mem_top_track_24\/FTB_15__66:A 0.152 +2 mux_tree_tapbuf_size10_2_sram[3]:7 mux_tree_tapbuf_size10_2_sram[3]:6 0.0045 +3 mux_tree_tapbuf_size10_2_sram[3]:8 mux_tree_tapbuf_size10_2_sram[3]:7 0.007459822 +4 mux_tree_tapbuf_size10_2_sram[3]:3 mux_top_track_24\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_2_sram[3]:4 mux_tree_tapbuf_size10_2_sram[3]:3 0.0001752718 +6 mux_tree_tapbuf_size10_2_sram[3]:5 mux_tree_tapbuf_size10_2_sram[3]:4 0.0045 +7 mux_tree_tapbuf_size10_2_sram[3]:6 mux_tree_tapbuf_size10_2_sram[3]:5 0.001741072 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[3] 0.001014614 //LENGTH 7.358 LUMPCC 0.000117824 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 48.980 34.340 +*I mem_bottom_track_17\/FTB_20__71:A I *L 0.001746 *C 48.760 36.720 +*I mux_bottom_track_17\/mux_l4_in_0_:S I *L 0.00357 *C 53.240 34.340 +*N mux_tree_tapbuf_size10_7_sram[3]:3 *C 53.203 34.340 +*N mux_tree_tapbuf_size10_7_sram[3]:4 *C 48.760 36.720 +*N mux_tree_tapbuf_size10_7_sram[3]:5 *C 48.760 36.675 +*N mux_tree_tapbuf_size10_7_sram[3]:6 *C 48.760 34.385 +*N mux_tree_tapbuf_size10_7_sram[3]:7 *C 48.760 34.340 +*N mux_tree_tapbuf_size10_7_sram[3]:8 *C 49.018 34.340 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_17\/FTB_20__71:A 1e-06 +2 mux_bottom_track_17\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_7_sram[3]:3 0.0002191998 +4 mux_tree_tapbuf_size10_7_sram[3]:4 3.347176e-05 +5 mux_tree_tapbuf_size10_7_sram[3]:5 0.0001704913 +6 mux_tree_tapbuf_size10_7_sram[3]:6 0.0001704913 +7 mux_tree_tapbuf_size10_7_sram[3]:7 5.735705e-05 +8 mux_tree_tapbuf_size10_7_sram[3]:8 0.000242779 +9 mux_tree_tapbuf_size10_7_sram[3]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.664383e-05 +10 mux_tree_tapbuf_size10_7_sram[3]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.226815e-05 +11 mux_tree_tapbuf_size10_7_sram[3]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.226815e-05 +12 mux_tree_tapbuf_size10_7_sram[3]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.664383e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_7_sram[3]:8 0.152 +1 mux_tree_tapbuf_size10_7_sram[3]:3 mux_bottom_track_17\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[3]:4 mem_bottom_track_17\/FTB_20__71:A 0.152 +3 mux_tree_tapbuf_size10_7_sram[3]:5 mux_tree_tapbuf_size10_7_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size10_7_sram[3]:7 mux_tree_tapbuf_size10_7_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size10_7_sram[3]:6 mux_tree_tapbuf_size10_7_sram[3]:5 0.002044643 +6 mux_tree_tapbuf_size10_7_sram[3]:8 mux_tree_tapbuf_size10_7_sram[3]:7 0.0001399457 +7 mux_tree_tapbuf_size10_7_sram[3]:8 mux_tree_tapbuf_size10_7_sram[3]:3 0.003736607 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_3_ccff_tail[0] 0.000962296 //LENGTH 8.090 LUMPCC 0.000116999 DR + +*CONN +*I mem_right_track_8\/FTB_16__67:X O *L 0 *C 123.055 55.760 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 120.695 60.860 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 *C 120.695 60.860 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 *C 120.980 60.860 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 *C 120.980 60.815 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 *C 120.980 55.805 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 *C 121.025 55.760 +*N mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 *C 123.018 55.760 + +*CAP +0 mem_right_track_8\/FTB_16__67:X 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 5.001325e-05 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 5.126971e-05 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.0002352678 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0002352678 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.0001357392 +7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.0001357392 +8 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_3_sram[3]:11 2.441601e-05 +9 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_3_sram[3]:14 3.408347e-05 +10 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_3_sram[3]:13 3.408347e-05 +11 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_3_sram[3]:14 2.441601e-05 + +*RES +0 mem_right_track_8\/FTB_16__67:X mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:2 0.0001440218 +3 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 0.004473214 +6 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:6 0.001779018 + +*END + +*D_NET mux_tree_tapbuf_size12_3_sram[3] 0.001637157 //LENGTH 13.975 LUMPCC 0 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 124.965 98.940 +*I mem_right_track_2\/FTB_4__55:A I *L 0.001746 *C 124.660 93.840 +*I mux_right_track_2\/mux_l4_in_0_:S I *L 0.00357 *C 121.800 88.740 +*N mux_tree_tapbuf_size12_3_sram[3]:3 *C 121.838 88.740 +*N mux_tree_tapbuf_size12_3_sram[3]:4 *C 124.615 88.740 +*N mux_tree_tapbuf_size12_3_sram[3]:5 *C 124.660 88.785 +*N mux_tree_tapbuf_size12_3_sram[3]:6 *C 124.660 93.840 +*N mux_tree_tapbuf_size12_3_sram[3]:7 *C 124.660 93.840 +*N mux_tree_tapbuf_size12_3_sram[3]:8 *C 124.660 98.895 +*N mux_tree_tapbuf_size12_3_sram[3]:9 *C 124.660 98.940 +*N mux_tree_tapbuf_size12_3_sram[3]:10 *C 124.965 98.940 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_2\/FTB_4__55:A 1e-06 +2 mux_right_track_2\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_3_sram[3]:3 0.0001814623 +4 mux_tree_tapbuf_size12_3_sram[3]:4 0.0001814623 +5 mux_tree_tapbuf_size12_3_sram[3]:5 0.0002781829 +6 mux_tree_tapbuf_size12_3_sram[3]:6 3.241364e-05 +7 mux_tree_tapbuf_size12_3_sram[3]:7 0.0005885694 +8 mux_tree_tapbuf_size12_3_sram[3]:8 0.0002777579 +9 mux_tree_tapbuf_size12_3_sram[3]:9 4.810882e-05 +10 mux_tree_tapbuf_size12_3_sram[3]:10 4.61992e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_3_sram[3]:10 0.152 +1 mux_tree_tapbuf_size12_3_sram[3]:4 mux_tree_tapbuf_size12_3_sram[3]:3 0.002479911 +2 mux_tree_tapbuf_size12_3_sram[3]:5 mux_tree_tapbuf_size12_3_sram[3]:4 0.0045 +3 mux_tree_tapbuf_size12_3_sram[3]:3 mux_right_track_2\/mux_l4_in_0_:S 0.152 +4 mux_tree_tapbuf_size12_3_sram[3]:9 mux_tree_tapbuf_size12_3_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size12_3_sram[3]:8 mux_tree_tapbuf_size12_3_sram[3]:7 0.004513393 +6 mux_tree_tapbuf_size12_3_sram[3]:10 mux_tree_tapbuf_size12_3_sram[3]:9 0.0001657609 +7 mux_tree_tapbuf_size12_3_sram[3]:6 mem_right_track_2\/FTB_4__55:A 0.152 +8 mux_tree_tapbuf_size12_3_sram[3]:7 mux_tree_tapbuf_size12_3_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size12_3_sram[3]:7 mux_tree_tapbuf_size12_3_sram[3]:5 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size12_6_sram[0] 0.01823002 //LENGTH 125.040 LUMPCC 0.00410298 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 21.465 47.940 +*I mux_left_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 78.300 85.680 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 79.680 90.440 +*I mux_left_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 80.140 83.300 +*I mux_left_track_1\/mux_l1_in_3_:S I *L 0.00357 *C 69.560 79.950 +*I mux_left_track_1\/mux_l1_in_4_:S I *L 0.00357 *C 21.260 78.200 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 25.475 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:7 *C 25.438 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:8 *C 24.840 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:9 *C 24.840 80.920 +*N mux_tree_tapbuf_size12_6_sram[0]:10 *C 23.045 80.920 +*N mux_tree_tapbuf_size12_6_sram[0]:11 *C 23.000 80.875 +*N mux_tree_tapbuf_size12_6_sram[0]:12 *C 23.000 78.245 +*N mux_tree_tapbuf_size12_6_sram[0]:13 *C 22.978 78.200 +*N mux_tree_tapbuf_size12_6_sram[0]:14 *C 22.638 78.200 +*N mux_tree_tapbuf_size12_6_sram[0]:15 *C 21.297 78.200 +*N mux_tree_tapbuf_size12_6_sram[0]:16 *C 21.160 78.155 +*N mux_tree_tapbuf_size12_6_sram[0]:17 *C 69.560 79.950 +*N mux_tree_tapbuf_size12_6_sram[0]:18 *C 69.530 80.310 +*N mux_tree_tapbuf_size12_6_sram[0]:19 *C 69.415 80.170 +*N mux_tree_tapbuf_size12_6_sram[0]:20 *C 80.040 83.300 +*N mux_tree_tapbuf_size12_6_sram[0]:21 *C 80.040 83.300 +*N mux_tree_tapbuf_size12_6_sram[0]:22 *C 79.580 90.440 +*N mux_tree_tapbuf_size12_6_sram[0]:23 *C 79.580 90.395 +*N mux_tree_tapbuf_size12_6_sram[0]:24 *C 79.580 85.680 +*N mux_tree_tapbuf_size12_6_sram[0]:25 *C 78.338 85.680 +*N mux_tree_tapbuf_size12_6_sram[0]:26 *C 79.075 85.680 +*N mux_tree_tapbuf_size12_6_sram[0]:27 *C 79.120 85.680 +*N mux_tree_tapbuf_size12_6_sram[0]:28 *C 79.120 83.300 +*N mux_tree_tapbuf_size12_6_sram[0]:29 *C 79.120 80.625 +*N mux_tree_tapbuf_size12_6_sram[0]:30 *C 79.075 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:31 *C 69.460 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:32 *C 64.445 80.580 +*N mux_tree_tapbuf_size12_6_sram[0]:33 *C 64.400 80.535 +*N mux_tree_tapbuf_size12_6_sram[0]:34 *C 64.400 71.785 +*N mux_tree_tapbuf_size12_6_sram[0]:35 *C 64.355 71.740 +*N mux_tree_tapbuf_size12_6_sram[0]:36 *C 59.800 71.740 +*N mux_tree_tapbuf_size12_6_sram[0]:37 *C 59.800 71.400 +*N mux_tree_tapbuf_size12_6_sram[0]:38 *C 55.660 71.400 +*N mux_tree_tapbuf_size12_6_sram[0]:39 *C 55.660 71.740 +*N mux_tree_tapbuf_size12_6_sram[0]:40 *C 53.820 71.740 +*N mux_tree_tapbuf_size12_6_sram[0]:41 *C 53.820 71.400 +*N mux_tree_tapbuf_size12_6_sram[0]:42 *C 50.185 71.400 +*N mux_tree_tapbuf_size12_6_sram[0]:43 *C 50.140 71.355 +*N mux_tree_tapbuf_size12_6_sram[0]:44 *C 50.140 70.778 +*N mux_tree_tapbuf_size12_6_sram[0]:45 *C 50.133 70.720 +*N mux_tree_tapbuf_size12_6_sram[0]:46 *C 21.168 70.720 +*N mux_tree_tapbuf_size12_6_sram[0]:47 *C 21.160 70.720 +*N mux_tree_tapbuf_size12_6_sram[0]:48 *C 21.160 47.985 +*N mux_tree_tapbuf_size12_6_sram[0]:49 *C 21.160 47.940 +*N mux_tree_tapbuf_size12_6_sram[0]:50 *C 21.465 47.940 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_1\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_1\/mux_l1_in_1_:S 1e-06 +4 mux_left_track_1\/mux_l1_in_3_:S 1e-06 +5 mux_left_track_1\/mux_l1_in_4_:S 1e-06 +6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +7 mux_tree_tapbuf_size12_6_sram[0]:7 5.857129e-05 +8 mux_tree_tapbuf_size12_6_sram[0]:8 8.496905e-05 +9 mux_tree_tapbuf_size12_6_sram[0]:9 0.0001768116 +10 mux_tree_tapbuf_size12_6_sram[0]:10 0.0001504138 +11 mux_tree_tapbuf_size12_6_sram[0]:11 0.0001756419 +12 mux_tree_tapbuf_size12_6_sram[0]:12 0.0001756419 +13 mux_tree_tapbuf_size12_6_sram[0]:13 4.808339e-05 +14 mux_tree_tapbuf_size12_6_sram[0]:14 0.0001805887 +15 mux_tree_tapbuf_size12_6_sram[0]:15 0.0001325054 +16 mux_tree_tapbuf_size12_6_sram[0]:16 0.000464151 +17 mux_tree_tapbuf_size12_6_sram[0]:17 6.412019e-05 +18 mux_tree_tapbuf_size12_6_sram[0]:18 3.700082e-05 +19 mux_tree_tapbuf_size12_6_sram[0]:19 3.383891e-05 +20 mux_tree_tapbuf_size12_6_sram[0]:20 3.290458e-05 +21 mux_tree_tapbuf_size12_6_sram[0]:21 8.889863e-05 +22 mux_tree_tapbuf_size12_6_sram[0]:22 3.514921e-05 +23 mux_tree_tapbuf_size12_6_sram[0]:23 0.00025235 +24 mux_tree_tapbuf_size12_6_sram[0]:24 0.0002896562 +25 mux_tree_tapbuf_size12_6_sram[0]:25 8.018086e-05 +26 mux_tree_tapbuf_size12_6_sram[0]:26 8.018086e-05 +27 mux_tree_tapbuf_size12_6_sram[0]:27 0.0001258176 +28 mux_tree_tapbuf_size12_6_sram[0]:28 0.0002999489 +29 mux_tree_tapbuf_size12_6_sram[0]:29 0.0001548226 +30 mux_tree_tapbuf_size12_6_sram[0]:30 0.000629515 +31 mux_tree_tapbuf_size12_6_sram[0]:31 0.00103538 +32 mux_tree_tapbuf_size12_6_sram[0]:32 0.0003781356 +33 mux_tree_tapbuf_size12_6_sram[0]:33 0.0005860523 +34 mux_tree_tapbuf_size12_6_sram[0]:34 0.0005860523 +35 mux_tree_tapbuf_size12_6_sram[0]:35 0.0001789972 +36 mux_tree_tapbuf_size12_6_sram[0]:36 0.0002064561 +37 mux_tree_tapbuf_size12_6_sram[0]:37 0.0003103869 +38 mux_tree_tapbuf_size12_6_sram[0]:38 0.0003099655 +39 mux_tree_tapbuf_size12_6_sram[0]:39 0.0001297269 +40 mux_tree_tapbuf_size12_6_sram[0]:40 0.000128523 +41 mux_tree_tapbuf_size12_6_sram[0]:41 0.0003070654 +42 mux_tree_tapbuf_size12_6_sram[0]:42 0.0002812319 +43 mux_tree_tapbuf_size12_6_sram[0]:43 7.64771e-05 +44 mux_tree_tapbuf_size12_6_sram[0]:44 7.64771e-05 +45 mux_tree_tapbuf_size12_6_sram[0]:45 0.001318762 +46 mux_tree_tapbuf_size12_6_sram[0]:46 0.001318762 +47 mux_tree_tapbuf_size12_6_sram[0]:47 0.001721073 +48 mux_tree_tapbuf_size12_6_sram[0]:48 0.001219061 +49 mux_tree_tapbuf_size12_6_sram[0]:49 5.202346e-05 +50 mux_tree_tapbuf_size12_6_sram[0]:50 4.767062e-05 +51 mux_tree_tapbuf_size12_6_sram[0]:48 chanx_left_in[10]:7 0.000106861 +52 mux_tree_tapbuf_size12_6_sram[0]:48 chanx_left_in[10]:31 1.967463e-05 +53 mux_tree_tapbuf_size12_6_sram[0]:47 chanx_left_in[10]:30 0.000106861 +54 mux_tree_tapbuf_size12_6_sram[0]:47 chanx_left_in[10]:32 1.967463e-05 +55 mux_tree_tapbuf_size12_6_sram[0]:46 chanx_left_in[10]:25 0.0004713822 +56 mux_tree_tapbuf_size12_6_sram[0]:45 chanx_left_in[10]:24 0.0004713822 +57 mux_tree_tapbuf_size12_6_sram[0]:15 mux_tree_tapbuf_size10_9_sram[0]:33 1.171607e-06 +58 mux_tree_tapbuf_size12_6_sram[0]:13 mux_tree_tapbuf_size10_9_sram[0]:32 5.817784e-07 +59 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size10_9_sram[0]:14 0.0001627282 +60 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size10_9_sram[0]:16 4.789946e-05 +61 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size10_9_sram[0]:18 0.0001915778 +62 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size10_9_sram[0]:20 6.413181e-05 +63 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size10_9_sram[0]:22 0.0004406029 +64 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size10_9_sram[0]:13 0.0001627282 +65 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size10_9_sram[0]:15 4.789946e-05 +66 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size10_9_sram[0]:17 0.0001915778 +67 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size10_9_sram[0]:19 6.413181e-05 +68 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size10_9_sram[0]:21 0.0004406029 +69 mux_tree_tapbuf_size12_6_sram[0]:14 mux_tree_tapbuf_size10_9_sram[0]:32 1.171607e-06 +70 mux_tree_tapbuf_size12_6_sram[0]:14 mux_tree_tapbuf_size10_9_sram[0]:33 5.817784e-07 +71 mux_tree_tapbuf_size12_6_sram[0]:35 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.510267e-05 +72 mux_tree_tapbuf_size12_6_sram[0]:36 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.510267e-05 +73 mux_tree_tapbuf_size12_6_sram[0]:42 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.142812e-05 +74 mux_tree_tapbuf_size12_6_sram[0]:35 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001751771 +75 mux_tree_tapbuf_size12_6_sram[0]:41 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.142812e-05 +76 mux_tree_tapbuf_size12_6_sram[0]:40 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.136882e-05 +77 mux_tree_tapbuf_size12_6_sram[0]:39 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.136882e-05 +78 mux_tree_tapbuf_size12_6_sram[0]:38 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.180488e-05 +79 mux_tree_tapbuf_size12_6_sram[0]:37 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.180488e-05 +80 mux_tree_tapbuf_size12_6_sram[0]:36 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001751771 +81 mux_tree_tapbuf_size12_6_sram[0]:48 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.891922e-05 +82 mux_tree_tapbuf_size12_6_sram[0]:47 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.891922e-05 +83 mux_tree_tapbuf_size12_6_sram[0]:29 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 1.295727e-05 +84 mux_tree_tapbuf_size12_6_sram[0]:27 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 6.509944e-05 +85 mux_tree_tapbuf_size12_6_sram[0]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 4.302125e-05 +86 mux_tree_tapbuf_size12_6_sram[0]:28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.295727e-05 +87 mux_tree_tapbuf_size12_6_sram[0]:28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.509944e-05 +88 mux_tree_tapbuf_size12_6_sram[0]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 4.302125e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_6_sram[0]:50 0.152 +1 mux_tree_tapbuf_size12_6_sram[0]:15 mux_left_track_1\/mux_l1_in_4_:S 0.152 +2 mux_tree_tapbuf_size12_6_sram[0]:15 mux_tree_tapbuf_size12_6_sram[0]:14 0.001196429 +3 mux_tree_tapbuf_size12_6_sram[0]:49 mux_tree_tapbuf_size12_6_sram[0]:48 0.0045 +4 mux_tree_tapbuf_size12_6_sram[0]:48 mux_tree_tapbuf_size12_6_sram[0]:47 0.02029911 +5 mux_tree_tapbuf_size12_6_sram[0]:50 mux_tree_tapbuf_size12_6_sram[0]:49 0.0001657609 +6 mux_tree_tapbuf_size12_6_sram[0]:16 mux_tree_tapbuf_size12_6_sram[0]:15 0.0045 +7 mux_tree_tapbuf_size12_6_sram[0]:13 mux_tree_tapbuf_size12_6_sram[0]:12 0.0045 +8 mux_tree_tapbuf_size12_6_sram[0]:12 mux_tree_tapbuf_size12_6_sram[0]:11 0.002348214 +9 mux_tree_tapbuf_size12_6_sram[0]:10 mux_tree_tapbuf_size12_6_sram[0]:9 0.001602679 +10 mux_tree_tapbuf_size12_6_sram[0]:11 mux_tree_tapbuf_size12_6_sram[0]:10 0.0045 +11 mux_tree_tapbuf_size12_6_sram[0]:7 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size12_6_sram[0]:47 mux_tree_tapbuf_size12_6_sram[0]:46 0.00341 +13 mux_tree_tapbuf_size12_6_sram[0]:47 mux_tree_tapbuf_size12_6_sram[0]:16 0.006638393 +14 mux_tree_tapbuf_size12_6_sram[0]:46 mux_tree_tapbuf_size12_6_sram[0]:45 0.00453785 +15 mux_tree_tapbuf_size12_6_sram[0]:44 mux_tree_tapbuf_size12_6_sram[0]:43 0.000515625 +16 mux_tree_tapbuf_size12_6_sram[0]:45 mux_tree_tapbuf_size12_6_sram[0]:44 0.00341 +17 mux_tree_tapbuf_size12_6_sram[0]:42 mux_tree_tapbuf_size12_6_sram[0]:41 0.003245536 +18 mux_tree_tapbuf_size12_6_sram[0]:43 mux_tree_tapbuf_size12_6_sram[0]:42 0.0045 +19 mux_tree_tapbuf_size12_6_sram[0]:35 mux_tree_tapbuf_size12_6_sram[0]:34 0.0045 +20 mux_tree_tapbuf_size12_6_sram[0]:34 mux_tree_tapbuf_size12_6_sram[0]:33 0.0078125 +21 mux_tree_tapbuf_size12_6_sram[0]:32 mux_tree_tapbuf_size12_6_sram[0]:31 0.004477679 +22 mux_tree_tapbuf_size12_6_sram[0]:33 mux_tree_tapbuf_size12_6_sram[0]:32 0.0045 +23 mux_tree_tapbuf_size12_6_sram[0]:30 mux_tree_tapbuf_size12_6_sram[0]:29 0.0045 +24 mux_tree_tapbuf_size12_6_sram[0]:29 mux_tree_tapbuf_size12_6_sram[0]:28 0.002388393 +25 mux_tree_tapbuf_size12_6_sram[0]:17 mux_left_track_1\/mux_l1_in_3_:S 0.152 +26 mux_tree_tapbuf_size12_6_sram[0]:26 mux_tree_tapbuf_size12_6_sram[0]:25 0.0006584823 +27 mux_tree_tapbuf_size12_6_sram[0]:27 mux_tree_tapbuf_size12_6_sram[0]:26 0.0045 +28 mux_tree_tapbuf_size12_6_sram[0]:27 mux_tree_tapbuf_size12_6_sram[0]:24 0.0004107143 +29 mux_tree_tapbuf_size12_6_sram[0]:25 mux_left_track_1\/mux_l1_in_2_:S 0.152 +30 mux_tree_tapbuf_size12_6_sram[0]:20 mux_left_track_1\/mux_l1_in_1_:S 0.152 +31 mux_tree_tapbuf_size12_6_sram[0]:21 mux_tree_tapbuf_size12_6_sram[0]:20 0.0045 +32 mux_tree_tapbuf_size12_6_sram[0]:22 mux_left_track_1\/mux_l1_in_0_:S 0.152 +33 mux_tree_tapbuf_size12_6_sram[0]:23 mux_tree_tapbuf_size12_6_sram[0]:22 0.0045 +34 mux_tree_tapbuf_size12_6_sram[0]:14 mux_tree_tapbuf_size12_6_sram[0]:13 0.0001847826 +35 mux_tree_tapbuf_size12_6_sram[0]:9 mux_tree_tapbuf_size12_6_sram[0]:8 0.0003035714 +36 mux_tree_tapbuf_size12_6_sram[0]:8 mux_tree_tapbuf_size12_6_sram[0]:7 0.0005334822 +37 mux_tree_tapbuf_size12_6_sram[0]:41 mux_tree_tapbuf_size12_6_sram[0]:40 0.0003035714 +38 mux_tree_tapbuf_size12_6_sram[0]:40 mux_tree_tapbuf_size12_6_sram[0]:39 0.001642857 +39 mux_tree_tapbuf_size12_6_sram[0]:39 mux_tree_tapbuf_size12_6_sram[0]:38 0.0003035714 +40 mux_tree_tapbuf_size12_6_sram[0]:38 mux_tree_tapbuf_size12_6_sram[0]:37 0.003696429 +41 mux_tree_tapbuf_size12_6_sram[0]:37 mux_tree_tapbuf_size12_6_sram[0]:36 0.0003035714 +42 mux_tree_tapbuf_size12_6_sram[0]:36 mux_tree_tapbuf_size12_6_sram[0]:35 0.004066965 +43 mux_tree_tapbuf_size12_6_sram[0]:31 mux_tree_tapbuf_size12_6_sram[0]:30 0.008584822 +44 mux_tree_tapbuf_size12_6_sram[0]:31 mux_tree_tapbuf_size12_6_sram[0]:19 0.0003660715 +45 mux_tree_tapbuf_size12_6_sram[0]:19 mux_tree_tapbuf_size12_6_sram[0]:18 0.0001026786 +46 mux_tree_tapbuf_size12_6_sram[0]:18 mux_tree_tapbuf_size12_6_sram[0]:17 0.0002093024 +47 mux_tree_tapbuf_size12_6_sram[0]:28 mux_tree_tapbuf_size12_6_sram[0]:27 0.002125 +48 mux_tree_tapbuf_size12_6_sram[0]:28 mux_tree_tapbuf_size12_6_sram[0]:21 0.0008214285 +49 mux_tree_tapbuf_size12_6_sram[0]:24 mux_tree_tapbuf_size12_6_sram[0]:23 0.004209822 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005200482 //LENGTH 4.210 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_0_:X O *L 0 *C 54.915 102.000 +*I mux_top_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 56.120 99.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 56.120 99.620 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 56.120 99.665 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 56.120 101.955 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 56.075 102.000 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 54.953 102.000 + +*CAP +0 mux_top_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.403282e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001433571 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001433571 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.865064e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.865064e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001002232 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A1 0.152 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002428268 //LENGTH 15.865 LUMPCC 0.0009400955 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_0_:X O *L 0 *C 110.685 91.460 +*I mux_right_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 120.160 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 120.123 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 119.185 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 119.140 96.175 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 119.140 92.538 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 119.133 92.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 115.468 92.480 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 115.460 92.422 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 115.460 91.505 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 115.415 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 110.723 91.460 + +*CAP +0 mux_right_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001079663 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001079663 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002426863 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002426863 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.528611e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.528611e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 7.148775e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 7.148775e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0002256594 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0002256594 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[14]:40 0.0002224594 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[14]:39 0.0002224594 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 right_top_grid_pin_45_[0]:16 8.771051e-05 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 right_top_grid_pin_45_[0]:14 1.453706e-06 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 right_top_grid_pin_45_[0]:15 8.771051e-05 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 right_top_grid_pin_45_[0]:13 1.453706e-06 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 optlc_net_151:35 7.198393e-06 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 optlc_net_151:36 0.0001512258 +20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 optlc_net_151:34 7.198393e-06 +21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 optlc_net_151:41 0.0001512258 + +*RES +0 mux_right_track_2\/mux_l2_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008370536 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003247768 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005741833 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0008191963 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.004189732 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006783777 //LENGTH 5.160 LUMPCC 0.0002051507 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_0_:X O *L 0 *C 66.875 99.620 +*I mux_left_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 62.005 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 62.043 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 66.838 99.620 + +*CAP +0 mux_left_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002356136 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002356136 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 prog_clk[0]:575 4.342901e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 prog_clk[0]:572 4.342901e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size12_7_sram[0]:12 1.384357e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size12_7_sram[0]:14 4.530275e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_7_sram[0]:11 1.384357e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_7_sram[0]:13 4.530275e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00428125 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00167414 //LENGTH 10.755 LUMPCC 0.0009453411 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_5_:X O *L 0 *C 53.995 86.020 +*I mux_top_track_4\/mux_l3_in_2_:A0 I *L 0.001631 *C 43.530 86.020 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 43.568 86.020 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 53.958 86.020 + +*CAP +0 mux_top_track_4\/mux_l2_in_5_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_2_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003633995 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003633995 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chany_bottom_in[14]:25 0.0003051427 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chany_bottom_in[14]:26 0.0003051427 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.489875e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.26291e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.489875e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.26291e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_5_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_4\/mux_l3_in_2_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.009276787 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0] 0.0008884043 //LENGTH 7.150 LUMPCC 8.313737e-05 DR + +*CONN +*I mux_bottom_track_5\/mux_l4_in_1_:X O *L 0 *C 41.685 14.280 +*I mux_bottom_track_5\/mux_l5_in_0_:A0 I *L 0.001631 *C 45.715 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 *C 45.678 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 *C 41.905 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 *C 41.860 11.945 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 *C 41.860 14.235 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:6 *C 41.860 14.280 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:7 *C 41.685 14.280 + +*CAP +0 mux_bottom_track_5\/mux_l4_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l5_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.0001944799 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0001944799 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.0001522147 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0001522147 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:6 5.436478e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:7 5.551293e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 4.140911e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 4.140911e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 1.595745e-07 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 1.595745e-07 + +*RES +0 mux_bottom_track_5\/mux_l4_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_bottom_track_5\/mux_l5_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.003368304 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.002044643 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:6 9.51087e-05 + +*END + +*D_NET optlc_net_150 0.01121344 //LENGTH 85.260 LUMPCC 0.001991337 DR + +*CONN +*I optlc_144:HI O *L 0 *C 20.240 72.080 +*I mux_left_track_25\/mux_l2_in_3_:A0 I *L 0.001631 *C 18.115 66.300 +*I mux_left_track_17\/mux_l2_in_3_:A0 I *L 0.001631 *C 26.395 65.960 +*I mux_left_track_5\/mux_l2_in_7_:A0 I *L 0.001631 *C 19.150 93.500 +*I mux_left_track_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 18.115 98.600 +*I mux_left_track_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 16.275 82.620 +*I mux_left_track_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 30.535 77.180 +*I mux_left_track_33\/mux_l1_in_3_:A0 I *L 0.001631 *C 22.830 75.140 +*N optlc_net_150:8 *C 22.793 75.140 +*N optlc_net_150:9 *C 19.365 75.140 +*N optlc_net_150:10 *C 19.320 75.095 +*N optlc_net_150:11 *C 30.498 77.180 +*N optlc_net_150:12 *C 28.105 77.180 +*N optlc_net_150:13 *C 28.060 77.135 +*N optlc_net_150:14 *C 28.060 74.178 +*N optlc_net_150:15 *C 28.053 74.120 +*N optlc_net_150:16 *C 16.238 82.620 +*N optlc_net_150:17 *C 14.430 82.620 +*N optlc_net_150:18 *C 14.430 82.960 +*N optlc_net_150:19 *C 15.135 82.960 +*N optlc_net_150:20 *C 15.180 82.960 +*N optlc_net_150:21 *C 17.990 98.600 +*N optlc_net_150:22 *C 19.113 93.500 +*N optlc_net_150:23 *C 17.985 93.500 +*N optlc_net_150:24 *C 17.940 93.545 +*N optlc_net_150:25 *C 17.940 98.555 +*N optlc_net_150:26 *C 17.895 98.600 +*N optlc_net_150:27 *C 14.765 98.600 +*N optlc_net_150:28 *C 14.720 98.555 +*N optlc_net_150:29 *C 14.720 82.960 +*N optlc_net_150:30 *C 14.720 74.178 +*N optlc_net_150:31 *C 14.728 74.120 +*N optlc_net_150:32 *C 26.358 65.960 +*N optlc_net_150:33 *C 18.115 66.300 +*N optlc_net_150:34 *C 18.400 65.960 +*N optlc_net_150:35 *C 18.400 66.005 +*N optlc_net_150:36 *C 18.400 74.062 +*N optlc_net_150:37 *C 18.400 74.120 +*N optlc_net_150:38 *C 19.320 74.120 +*N optlc_net_150:39 *C 19.320 74.120 +*N optlc_net_150:40 *C 19.320 72.125 +*N optlc_net_150:41 *C 19.365 72.080 +*N optlc_net_150:42 *C 20.203 72.080 + +*CAP +0 optlc_144:HI 1e-06 +1 mux_left_track_25\/mux_l2_in_3_:A0 1e-06 +2 mux_left_track_17\/mux_l2_in_3_:A0 1e-06 +3 mux_left_track_5\/mux_l2_in_7_:A0 1e-06 +4 mux_left_track_3\/mux_l2_in_3_:A0 1e-06 +5 mux_left_track_1\/mux_l2_in_3_:A0 1e-06 +6 mux_left_track_9\/mux_l2_in_3_:A0 1e-06 +7 mux_left_track_33\/mux_l1_in_3_:A0 1e-06 +8 optlc_net_150:8 0.0002026329 +9 optlc_net_150:9 0.0002026329 +10 optlc_net_150:10 6.455161e-05 +11 optlc_net_150:11 0.0002146551 +12 optlc_net_150:12 0.0002146551 +13 optlc_net_150:13 0.0001990219 +14 optlc_net_150:14 0.0001990219 +15 optlc_net_150:15 0.0004683359 +16 optlc_net_150:16 0.0001181885 +17 optlc_net_150:17 0.0001496353 +18 optlc_net_150:18 7.953942e-05 +19 optlc_net_150:19 4.809263e-05 +20 optlc_net_150:20 7.048371e-05 +21 optlc_net_150:21 2.293058e-05 +22 optlc_net_150:22 0.0001114001 +23 optlc_net_150:23 0.0001114001 +24 optlc_net_150:24 0.000331654 +25 optlc_net_150:25 0.000331654 +26 optlc_net_150:26 0.0002328834 +27 optlc_net_150:27 0.0002099528 +28 optlc_net_150:28 0.000572123 +29 optlc_net_150:29 0.001102684 +30 optlc_net_150:30 0.0004945287 +31 optlc_net_150:31 0.0001719591 +32 optlc_net_150:32 0.0005721122 +33 optlc_net_150:33 6.329163e-05 +34 optlc_net_150:34 0.00060506 +35 optlc_net_150:35 0.0003940819 +36 optlc_net_150:36 0.0003940819 +37 optlc_net_150:37 0.0002194849 +38 optlc_net_150:38 0.0005158617 +39 optlc_net_150:39 0.0002191382 +40 optlc_net_150:40 0.0001166681 +41 optlc_net_150:41 9.485176e-05 +42 optlc_net_150:42 9.485176e-05 +43 optlc_net_150:38 chanx_right_in[16]:19 0.0001856402 +44 optlc_net_150:38 chanx_right_in[16]:20 1.930336e-05 +45 optlc_net_150:30 chanx_right_in[16]:14 5.310031e-07 +46 optlc_net_150:31 chanx_right_in[16]:19 8.66187e-05 +47 optlc_net_150:15 chanx_right_in[16]:20 0.0001856402 +48 optlc_net_150:28 chanx_right_in[16]:13 9.822023e-08 +49 optlc_net_150:37 chanx_right_in[16]:19 1.930336e-05 +50 optlc_net_150:37 chanx_right_in[16]:20 8.66187e-05 +51 optlc_net_150:29 chanx_right_in[16]:13 5.310031e-07 +52 optlc_net_150:29 chanx_right_in[16]:14 9.822023e-08 +53 optlc_net_150:19 left_top_grid_pin_48_[0]:15 3.568592e-05 +54 optlc_net_150:16 left_top_grid_pin_48_[0]:15 1.8086e-05 +55 optlc_net_150:32 left_top_grid_pin_48_[0]:4 1.220357e-06 +56 optlc_net_150:28 left_top_grid_pin_48_[0] 3.583396e-07 +57 optlc_net_150:28 left_top_grid_pin_48_[0]:17 9.991279e-06 +58 optlc_net_150:28 left_top_grid_pin_48_[0]:18 0.0003613565 +59 optlc_net_150:34 left_top_grid_pin_48_[0]:5 1.220357e-06 +60 optlc_net_150:35 left_top_grid_pin_48_[0]:7 5.171756e-06 +61 optlc_net_150:36 left_top_grid_pin_48_[0]:6 5.171756e-06 +62 optlc_net_150:17 left_top_grid_pin_48_[0]:16 1.8086e-05 +63 optlc_net_150:18 left_top_grid_pin_48_[0]:16 3.568592e-05 +64 optlc_net_150:29 left_top_grid_pin_48_[0]:14 9.991279e-06 +65 optlc_net_150:29 left_top_grid_pin_48_[0]:17 0.0003613565 +66 optlc_net_150:29 left_top_grid_pin_48_[0]:22 3.583396e-07 +67 optlc_net_150:25 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.7895e-06 +68 optlc_net_150:24 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.7895e-06 +69 optlc_net_150:28 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.842985e-05 +70 optlc_net_150:29 mux_left_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 5.842985e-05 +71 optlc_net_150:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001375601 +72 optlc_net_150:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001375601 +73 optlc_net_150:39 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.098146e-07 +74 optlc_net_150:39 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.259951e-06 +75 optlc_net_150:30 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.966189e-08 +76 optlc_net_150:40 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.259951e-06 +77 optlc_net_150:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.135424e-06 +78 optlc_net_150:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.098146e-07 +79 optlc_net_150:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.135424e-06 +80 optlc_net_150:35 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.805231e-05 +81 optlc_net_150:36 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.805231e-05 +82 optlc_net_150:29 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.966189e-08 + +*RES +0 optlc_144:HI optlc_net_150:42 0.152 +1 optlc_net_150:39 optlc_net_150:38 0.00341 +2 optlc_net_150:39 optlc_net_150:10 0.0008705358 +3 optlc_net_150:38 optlc_net_150:37 0.0001441333 +4 optlc_net_150:38 optlc_net_150:15 0.001368092 +5 optlc_net_150:30 optlc_net_150:29 0.007841518 +6 optlc_net_150:31 optlc_net_150:30 0.00341 +7 optlc_net_150:19 optlc_net_150:18 0.0006294643 +8 optlc_net_150:20 optlc_net_150:19 0.0045 +9 optlc_net_150:16 mux_left_track_1\/mux_l2_in_3_:A0 0.152 +10 optlc_net_150:41 optlc_net_150:40 0.0045 +11 optlc_net_150:40 optlc_net_150:39 0.00178125 +12 optlc_net_150:42 optlc_net_150:41 0.0007477679 +13 optlc_net_150:33 mux_left_track_25\/mux_l2_in_3_:A0 0.152 +14 optlc_net_150:26 optlc_net_150:25 0.0045 +15 optlc_net_150:26 optlc_net_150:21 8.482143e-05 +16 optlc_net_150:25 optlc_net_150:24 0.004473215 +17 optlc_net_150:23 optlc_net_150:22 0.001006696 +18 optlc_net_150:24 optlc_net_150:23 0.0045 +19 optlc_net_150:22 mux_left_track_5\/mux_l2_in_7_:A0 0.152 +20 optlc_net_150:9 optlc_net_150:8 0.003060268 +21 optlc_net_150:10 optlc_net_150:9 0.0045 +22 optlc_net_150:8 mux_left_track_33\/mux_l1_in_3_:A0 0.152 +23 optlc_net_150:32 mux_left_track_17\/mux_l2_in_3_:A0 0.152 +24 optlc_net_150:14 optlc_net_150:13 0.002640625 +25 optlc_net_150:15 optlc_net_150:14 0.00341 +26 optlc_net_150:12 optlc_net_150:11 0.002136161 +27 optlc_net_150:13 optlc_net_150:12 0.0045 +28 optlc_net_150:11 mux_left_track_9\/mux_l2_in_3_:A0 0.152 +29 optlc_net_150:21 mux_left_track_3\/mux_l2_in_3_:A0 0.152 +30 optlc_net_150:27 optlc_net_150:26 0.002794643 +31 optlc_net_150:28 optlc_net_150:27 0.0045 +32 optlc_net_150:34 optlc_net_150:33 0.0001847826 +33 optlc_net_150:34 optlc_net_150:32 0.007104911 +34 optlc_net_150:35 optlc_net_150:34 0.0045 +35 optlc_net_150:36 optlc_net_150:35 0.007194197 +36 optlc_net_150:37 optlc_net_150:36 0.00341 +37 optlc_net_150:37 optlc_net_150:31 0.0005753583 +38 optlc_net_150:17 optlc_net_150:16 0.00161384 +39 optlc_net_150:18 optlc_net_150:17 0.0003035715 +40 optlc_net_150:29 optlc_net_150:28 0.01392411 +41 optlc_net_150:29 optlc_net_150:20 0.0004107143 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001217316 //LENGTH 8.600 LUMPCC 0.0003422195 DR + +*CONN +*I mux_right_track_32\/mux_l2_in_1_:X O *L 0 *C 90.445 68.680 +*I mux_right_track_32\/mux_l3_in_0_:A0 I *L 0.001631 *C 95.395 65.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 95.358 65.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 91.125 65.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 91.080 66.005 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 91.080 68.635 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 91.035 68.680 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 90.483 68.680 + +*CAP +0 mux_right_track_32\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001972766 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001972766 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001787643 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001787643 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.050729e-05 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.050729e-05 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_3_sram[0]:9 0.0001711097 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_3_sram[0]:8 0.0001711097 + +*RES +0 mux_right_track_32\/mux_l2_in_1_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_32\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003779018 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 + +*END + +*D_NET ropt_net_171 0.002100704 //LENGTH 15.110 LUMPCC 0.0003369126 DR + +*CONN +*I FTB_11__10:X O *L 0 *C 66.700 8.840 +*I ropt_mt_inst_809:A I *L 0.001766 *C 57.040 6.800 +*N ropt_net_171:2 *C 57.078 6.800 +*N ropt_net_171:3 *C 57.915 6.800 +*N ropt_net_171:4 *C 57.960 6.845 +*N ropt_net_171:5 *C 57.960 7.435 +*N ropt_net_171:6 *C 58.005 7.480 +*N ropt_net_171:7 *C 67.575 7.480 +*N ropt_net_171:8 *C 67.620 7.525 +*N ropt_net_171:9 *C 67.620 8.795 +*N ropt_net_171:10 *C 67.575 8.840 +*N ropt_net_171:11 *C 66.737 8.840 + +*CAP +0 FTB_11__10:X 1e-06 +1 ropt_mt_inst_809:A 1e-06 +2 ropt_net_171:2 4.207485e-05 +3 ropt_net_171:3 4.207485e-05 +4 ropt_net_171:4 5.125395e-05 +5 ropt_net_171:5 5.125395e-05 +6 ropt_net_171:6 0.0006008296 +7 ropt_net_171:7 0.0006008296 +8 ropt_net_171:8 0.0001043556 +9 ropt_net_171:9 0.0001043556 +10 ropt_net_171:10 8.238171e-05 +11 ropt_net_171:11 8.238171e-05 +12 ropt_net_171:7 ropt_net_237:7 0.0001043349 +13 ropt_net_171:6 ropt_net_237:6 0.0001043349 +14 ropt_net_171:5 ropt_net_237:4 1.716923e-05 +15 ropt_net_171:4 ropt_net_237:5 1.716923e-05 +16 ropt_net_171:7 ropt_net_230:6 2.475298e-06 +17 ropt_net_171:6 ropt_net_230:7 2.475298e-06 +18 ropt_net_171:3 ropt_net_230:6 4.447683e-05 +19 ropt_net_171:2 ropt_net_230:7 4.447683e-05 + +*RES +0 FTB_11__10:X ropt_net_171:11 0.152 +1 ropt_net_171:11 ropt_net_171:10 0.0007477679 +2 ropt_net_171:10 ropt_net_171:9 0.0045 +3 ropt_net_171:9 ropt_net_171:8 0.001133929 +4 ropt_net_171:7 ropt_net_171:6 0.008544644 +5 ropt_net_171:8 ropt_net_171:7 0.0045 +6 ropt_net_171:6 ropt_net_171:5 0.0045 +7 ropt_net_171:5 ropt_net_171:4 0.0005267857 +8 ropt_net_171:3 ropt_net_171:2 0.0007477679 +9 ropt_net_171:4 ropt_net_171:3 0.0045 +10 ropt_net_171:2 ropt_mt_inst_809:A 0.152 + +*END + +*D_NET chanx_left_out[5] 0.0005805671 //LENGTH 3.625 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_856:X O *L 0 *C 4.140 47.260 +*P chanx_left_out[5] O *L 0.7423 *C 1.305 47.600 +*N chanx_left_out[5]:2 *C 1.833 47.600 +*N chanx_left_out[5]:3 *C 1.840 47.600 +*N chanx_left_out[5]:4 *C 1.840 47.260 +*N chanx_left_out[5]:5 *C 1.885 47.260 +*N chanx_left_out[5]:6 *C 4.103 47.260 + +*CAP +0 ropt_mt_inst_856:X 1e-06 +1 chanx_left_out[5] 6.566645e-05 +2 chanx_left_out[5]:2 6.566645e-05 +3 chanx_left_out[5]:3 6.173376e-05 +4 chanx_left_out[5]:4 5.756673e-05 +5 chanx_left_out[5]:5 0.0001644669 +6 chanx_left_out[5]:6 0.0001644669 + +*RES +0 ropt_mt_inst_856:X chanx_left_out[5]:6 0.152 +1 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +2 chanx_left_out[5]:2 chanx_left_out[5] 8.264167e-05 +3 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +4 chanx_left_out[5]:4 chanx_left_out[5]:3 0.0001634615 +5 chanx_left_out[5]:6 chanx_left_out[5]:5 0.001979911 + +*END + +*D_NET chanx_right_out[11] 0.0006120474 //LENGTH 3.725 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_827:X O *L 0 *C 138.655 79.560 +*P chanx_right_out[11] O *L 0.7423 *C 140.450 78.880 +*N chanx_right_out[11]:2 *C 138.920 78.880 +*N chanx_right_out[11]:3 *C 138.920 79.547 +*N chanx_right_out[11]:4 *C 138.465 79.553 +*N chanx_right_out[11]:5 *C 138.460 79.560 +*N chanx_right_out[11]:6 *C 138.460 79.560 +*N chanx_right_out[11]:7 *C 138.655 79.560 + +*CAP +0 ropt_mt_inst_827:X 1e-06 +1 chanx_right_out[11] 0.0001072198 +2 chanx_right_out[11]:2 0.0001505599 +3 chanx_right_out[11]:3 0.0001286589 +4 chanx_right_out[11]:4 8.531881e-05 +5 chanx_right_out[11]:5 3.58629e-05 +6 chanx_right_out[11]:6 5.232375e-05 +7 chanx_right_out[11]:7 5.110333e-05 + +*RES +0 ropt_mt_inst_827:X chanx_right_out[11]:7 0.152 +1 chanx_right_out[11]:5 chanx_right_out[11]:4 0.00341 +2 chanx_right_out[11]:4 chanx_right_out[11]:3 6.788889e-05 +3 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0045 +4 chanx_right_out[11]:7 chanx_right_out[11]:6 0.0001059783 +5 chanx_right_out[11]:3 chanx_right_out[11]:2 0.000104575 +6 chanx_right_out[11]:2 chanx_right_out[11] 0.0002397 + +*END + +*D_NET chany_top_out[7] 0.0007735783 //LENGTH 6.180 LUMPCC 0.0002244532 DR + +*CONN +*I ropt_mt_inst_862:X O *L 0 *C 51.060 124.440 +*P chany_top_out[7] O *L 0.7423 *C 50.140 129.235 +*N chany_top_out[7]:2 *C 50.140 124.485 +*N chany_top_out[7]:3 *C 50.185 124.440 +*N chany_top_out[7]:4 *C 51.023 124.440 + +*CAP +0 ropt_mt_inst_862:X 1e-06 +1 chany_top_out[7] 0.0002270685 +2 chany_top_out[7]:2 0.0002270685 +3 chany_top_out[7]:3 4.699397e-05 +4 chany_top_out[7]:4 4.699397e-05 +5 chany_top_out[7] ropt_net_191:7 6.879374e-05 +6 chany_top_out[7]:3 ropt_net_191:3 2.046909e-06 +7 chany_top_out[7]:3 ropt_net_191:5 4.138597e-05 +8 chany_top_out[7]:2 ropt_net_191:6 6.879374e-05 +9 chany_top_out[7]:4 ropt_net_191:2 2.046909e-06 +10 chany_top_out[7]:4 ropt_net_191:4 4.138597e-05 + +*RES +0 ropt_mt_inst_862:X chany_top_out[7]:4 0.152 +1 chany_top_out[7]:3 chany_top_out[7]:2 0.0045 +2 chany_top_out[7]:2 chany_top_out[7] 0.004241072 +3 chany_top_out[7]:4 chany_top_out[7]:3 0.0007477679 + +*END + +*D_NET chany_bottom_out[18] 0.001515127 //LENGTH 10.685 LUMPCC 7.952441e-05 DR + +*CONN +*I ropt_mt_inst_888:X O *L 0 *C 75.440 9.180 +*P chany_bottom_out[18] O *L 0.7423 *C 73.140 1.290 +*N chany_bottom_out[18]:2 *C 73.140 8.783 +*N chany_bottom_out[18]:3 *C 73.148 8.840 +*N chany_bottom_out[18]:4 *C 75.433 8.840 +*N chany_bottom_out[18]:5 *C 75.440 8.840 +*N chany_bottom_out[18]:6 *C 75.440 9.180 +*N chany_bottom_out[18]:7 *C 75.440 9.180 + +*CAP +0 ropt_mt_inst_888:X 1e-06 +1 chany_bottom_out[18] 0.0004213199 +2 chany_bottom_out[18]:2 0.0004213199 +3 chany_bottom_out[18]:3 0.0002240754 +4 chany_bottom_out[18]:4 0.0002240754 +5 chany_bottom_out[18]:5 5.789336e-05 +6 chany_bottom_out[18]:6 5.412814e-05 +7 chany_bottom_out[18]:7 3.179051e-05 +8 chany_bottom_out[18] ropt_net_239:5 3.976221e-05 +9 chany_bottom_out[18]:2 ropt_net_239:6 3.976221e-05 + +*RES +0 ropt_mt_inst_888:X chany_bottom_out[18]:7 0.152 +1 chany_bottom_out[18]:7 chany_bottom_out[18]:6 0.0045 +2 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.0001057692 +3 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.00341 +4 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.0003579833 +5 chany_bottom_out[18]:2 chany_bottom_out[18] 0.006689732 +6 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.00341 + +*END + +*D_NET chany_top_in[14] 0.02039907 //LENGTH 156.745 LUMPCC 0.004180387 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 54.740 129.270 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 54.110 88.060 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 75.615 82.280 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.270 15.300 +*I BUFT_P_117:A I *L 0.001776 *C 48.300 6.800 +*N chany_top_in[14]:5 *C 48.338 6.800 +*N chany_top_in[14]:6 *C 51.060 6.800 +*N chany_top_in[14]:7 *C 51.060 7.140 +*N chany_top_in[14]:8 *C 52.855 7.140 +*N chany_top_in[14]:9 *C 52.900 7.185 +*N chany_top_in[14]:10 *C 52.900 15.300 +*N chany_top_in[14]:11 *C 52.308 15.300 +*N chany_top_in[14]:12 *C 53.230 15.300 +*N chany_top_in[14]:13 *C 53.360 15.345 +*N chany_top_in[14]:14 *C 53.360 65.140 +*N chany_top_in[14]:15 *C 53.360 81.600 +*N chany_top_in[14]:16 *C 53.820 81.600 +*N chany_top_in[14]:17 *C 75.578 82.280 +*N chany_top_in[14]:18 *C 73.645 82.280 +*N chany_top_in[14]:19 *C 73.600 82.325 +*N chany_top_in[14]:20 *C 73.600 83.583 +*N chany_top_in[14]:21 *C 73.593 83.640 +*N chany_top_in[14]:22 *C 53.828 83.640 +*N chany_top_in[14]:23 *C 53.820 83.640 +*N chany_top_in[14]:24 *C 54.110 88.060 +*N chany_top_in[14]:25 *C 53.820 88.060 +*N chany_top_in[14]:26 *C 53.820 88.060 +*N chany_top_in[14]:27 *C 53.820 100.980 +*N chany_top_in[14]:28 *C 54.280 100.980 +*N chany_top_in[14]:29 *C 54.280 112.880 +*N chany_top_in[14]:30 *C 54.740 112.880 + +*CAP +0 chany_top_in[14] 0.00087009 +1 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +2 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +4 BUFT_P_117:A 1e-06 +5 chany_top_in[14]:5 0.0001430002 +6 chany_top_in[14]:6 0.0001671042 +7 chany_top_in[14]:7 0.0001027192 +8 chany_top_in[14]:8 7.861515e-05 +9 chany_top_in[14]:9 0.0004056889 +10 chany_top_in[14]:10 0.0004390786 +11 chany_top_in[14]:11 8.61946e-05 +12 chany_top_in[14]:12 8.61946e-05 +13 chany_top_in[14]:13 0.002626772 +14 chany_top_in[14]:14 0.003356871 +15 chany_top_in[14]:15 0.0007972827 +16 chany_top_in[14]:16 0.0001513704 +17 chany_top_in[14]:17 0.0001823452 +18 chany_top_in[14]:18 0.0001823452 +19 chany_top_in[14]:19 0.0001272367 +20 chany_top_in[14]:20 0.0001272367 +21 chany_top_in[14]:21 0.001006456 +22 chany_top_in[14]:22 0.001006456 +23 chany_top_in[14]:23 0.0003955418 +24 chany_top_in[14]:24 5.131009e-05 +25 chany_top_in[14]:25 5.740067e-05 +26 chany_top_in[14]:26 0.00100173 +27 chany_top_in[14]:27 0.000760961 +28 chany_top_in[14]:28 0.0005534312 +29 chany_top_in[14]:29 0.0005518787 +30 chany_top_in[14]:30 0.0008993651 +31 chany_top_in[14]:9 chany_top_in[5]:16 9.681086e-06 +32 chany_top_in[14]:9 chany_top_in[5]:21 4.625733e-06 +33 chany_top_in[14]:12 chany_top_in[5]:18 1.121376e-05 +34 chany_top_in[14]:12 chany_top_in[5]:19 3.270681e-06 +35 chany_top_in[14]:13 chany_top_in[5]:21 2.616271e-06 +36 chany_top_in[14]:11 chany_top_in[5]:19 1.121376e-05 +37 chany_top_in[14]:11 chany_top_in[5]:20 3.270681e-06 +38 chany_top_in[14]:25 chany_top_in[5]:31 3.690669e-07 +39 chany_top_in[14]:26 chany_top_in[5]:28 1.260259e-05 +40 chany_top_in[14]:26 chany_top_in[5]:29 4.15633e-05 +41 chany_top_in[14]:24 chany_top_in[5]:32 3.690669e-07 +42 chany_top_in[14]:23 chany_top_in[5]:28 4.15633e-05 +43 chany_top_in[14]:23 chany_top_in[5]:29 1.449003e-05 +44 chany_top_in[14]:10 chany_top_in[5]:17 9.681086e-06 +45 chany_top_in[14]:10 chany_top_in[5]:22 4.625733e-06 +46 chany_top_in[14]:15 chany_top_in[5]:29 0.0002762452 +47 chany_top_in[14]:16 chany_top_in[5]:28 1.449003e-05 +48 chany_top_in[14]:27 chany_top_in[5]:29 1.260259e-05 +49 chany_top_in[14]:14 chany_top_in[5]:22 2.616271e-06 +50 chany_top_in[14]:14 chany_top_in[5]:28 0.0002762452 +51 chany_top_in[14]:23 chanx_right_in[2]:22 9.395784e-06 +52 chany_top_in[14]:22 chanx_right_in[2]:23 0.000308564 +53 chany_top_in[14]:22 chanx_right_in[2]:25 6.294285e-05 +54 chany_top_in[14]:21 chanx_right_in[2]:24 0.000308564 +55 chany_top_in[14]:21 chanx_right_in[2]:26 6.294285e-05 +56 chany_top_in[14]:16 chanx_right_in[2]:23 9.395784e-06 +57 chany_top_in[14]:22 chany_bottom_in[10]:41 0.0004617758 +58 chany_top_in[14]:22 chany_bottom_in[10]:32 1.246596e-05 +59 chany_top_in[14]:22 chany_bottom_in[10]:30 9.547186e-05 +60 chany_top_in[14]:22 chany_bottom_in[10]:28 6.294285e-05 +61 chany_top_in[14]:21 chany_bottom_in[10]:42 0.0004617758 +62 chany_top_in[14]:21 chany_bottom_in[10]:31 1.246596e-05 +63 chany_top_in[14]:21 chany_bottom_in[10]:29 9.547186e-05 +64 chany_top_in[14]:21 chany_bottom_in[10]:27 6.294285e-05 +65 chany_top_in[14]:13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 6.857105e-05 +66 chany_top_in[14]:14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 6.857105e-05 +67 chany_top_in[14]:26 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 9.920954e-06 +68 chany_top_in[14]:27 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.920954e-06 +69 chany_top_in[14]:28 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002969315 +70 chany_top_in[14]:29 mux_top_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002969315 +71 chany_top_in[14]:13 optlc_net_149:5 5.938856e-05 +72 chany_top_in[14]:14 optlc_net_149:4 5.938856e-05 +73 chany_top_in[14]:5 ropt_net_199:11 2.000198e-05 +74 chany_top_in[14]:8 ropt_net_199:10 7.859178e-05 +75 chany_top_in[14]:9 ropt_net_199:8 1.647102e-05 +76 chany_top_in[14]:9 ropt_net_199:5 1.442529e-05 +77 chany_top_in[14]:6 ropt_net_199:10 2.000198e-05 +78 chany_top_in[14]:7 ropt_net_199:11 7.859178e-05 +79 chany_top_in[14]:10 ropt_net_199:9 1.647102e-05 +80 chany_top_in[14]:10 ropt_net_199:4 1.442529e-05 +81 chany_top_in[14] ropt_net_185:4 6.808632e-05 +82 chany_top_in[14]:30 ropt_net_185:5 6.808632e-05 +83 chany_top_in[14]:5 ropt_net_192:7 3.706053e-05 +84 chany_top_in[14]:8 ropt_net_192:6 1.463305e-06 +85 chany_top_in[14]:8 ropt_net_192:2 2.904479e-05 +86 chany_top_in[14]:6 ropt_net_192:6 3.706053e-05 +87 chany_top_in[14]:7 ropt_net_192:7 1.463305e-06 +88 chany_top_in[14]:7 ropt_net_192:3 2.904479e-05 + +*RES +0 chany_top_in[14] chany_top_in[14]:30 0.01463393 +1 chany_top_in[14]:5 BUFT_P_117:A 0.152 +2 chany_top_in[14]:8 chany_top_in[14]:7 0.001602679 +3 chany_top_in[14]:9 chany_top_in[14]:8 0.0045 +4 chany_top_in[14]:12 chany_top_in[14]:11 0.0008236608 +5 chany_top_in[14]:13 chany_top_in[14]:12 0.0045 +6 chany_top_in[14]:13 chany_top_in[14]:10 0.0004107143 +7 chany_top_in[14]:11 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +8 chany_top_in[14]:25 chany_top_in[14]:24 0.0001576087 +9 chany_top_in[14]:26 chany_top_in[14]:25 0.0045 +10 chany_top_in[14]:26 chany_top_in[14]:23 0.003946428 +11 chany_top_in[14]:24 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +12 chany_top_in[14]:23 chany_top_in[14]:22 0.00341 +13 chany_top_in[14]:23 chany_top_in[14]:16 0.001821429 +14 chany_top_in[14]:22 chany_top_in[14]:21 0.003096517 +15 chany_top_in[14]:20 chany_top_in[14]:19 0.001122768 +16 chany_top_in[14]:21 chany_top_in[14]:20 0.00341 +17 chany_top_in[14]:18 chany_top_in[14]:17 0.001725447 +18 chany_top_in[14]:19 chany_top_in[14]:18 0.0045 +19 chany_top_in[14]:17 mux_right_track_4\/mux_l2_in_0_:A0 0.152 +20 chany_top_in[14]:6 chany_top_in[14]:5 0.002430804 +21 chany_top_in[14]:7 chany_top_in[14]:6 0.0003035715 +22 chany_top_in[14]:10 chany_top_in[14]:9 0.007245536 +23 chany_top_in[14]:15 chany_top_in[14]:14 0.01469643 +24 chany_top_in[14]:16 chany_top_in[14]:15 0.0004107143 +25 chany_top_in[14]:27 chany_top_in[14]:26 0.01153571 +26 chany_top_in[14]:28 chany_top_in[14]:27 0.0004107143 +27 chany_top_in[14]:29 chany_top_in[14]:28 0.010625 +28 chany_top_in[14]:30 chany_top_in[14]:29 0.0004107143 +29 chany_top_in[14]:14 chany_top_in[14]:13 0.04445982 + +*END + +*D_NET chany_bottom_in[18] 0.03952621 //LENGTH 239.415 LUMPCC 0.0114732 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 57.500 1.325 +*I mux_left_track_25\/mux_l2_in_2_:A1 I *L 0.00198 *C 22.540 66.980 +*I mux_top_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 64.230 65.960 +*I mux_right_track_24\/mux_l2_in_2_:A1 I *L 0.00198 *C 99.820 72.420 +*I FTB_39__38:A I *L 0.001776 *C 77.740 126.480 +*N chany_bottom_in[18]:5 *C 77.703 126.480 +*N chany_bottom_in[18]:6 *C 73.645 126.480 +*N chany_bottom_in[18]:7 *C 73.600 126.435 +*N chany_bottom_in[18]:8 *C 73.600 125.845 +*N chany_bottom_in[18]:9 *C 73.555 125.800 +*N chany_bottom_in[18]:10 *C 67.205 125.800 +*N chany_bottom_in[18]:11 *C 67.160 125.755 +*N chany_bottom_in[18]:12 *C 67.160 117.018 +*N chany_bottom_in[18]:13 *C 67.153 116.960 +*N chany_bottom_in[18]:14 *C 66.260 116.960 +*N chany_bottom_in[18]:15 *C 66.240 116.953 +*N chany_bottom_in[18]:16 *C 66.240 70.047 +*N chany_bottom_in[18]:17 *C 66.220 70.040 +*N chany_bottom_in[18]:18 *C 64.868 70.040 +*N chany_bottom_in[18]:19 *C 64.860 69.983 +*N chany_bottom_in[18]:20 *C 99.820 72.435 +*N chany_bottom_in[18]:21 *C 99.820 72.760 +*N chany_bottom_in[18]:22 *C 99.820 72.715 +*N chany_bottom_in[18]:23 *C 99.820 67.365 +*N chany_bottom_in[18]:24 *C 99.775 67.320 +*N chany_bottom_in[18]:25 *C 64.905 67.320 +*N chany_bottom_in[18]:26 *C 64.860 67.320 +*N chany_bottom_in[18]:27 *C 64.860 66.005 +*N chany_bottom_in[18]:28 *C 64.815 65.960 +*N chany_bottom_in[18]:29 *C 64.230 65.960 +*N chany_bottom_in[18]:30 *C 48.345 65.960 +*N chany_bottom_in[18]:31 *C 48.300 65.915 +*N chany_bottom_in[18]:32 *C 22.578 66.980 +*N chany_bottom_in[18]:33 *C 22.955 66.980 +*N chany_bottom_in[18]:34 *C 23.000 66.935 +*N chany_bottom_in[18]:35 *C 23.000 64.657 +*N chany_bottom_in[18]:36 *C 23.008 64.600 +*N chany_bottom_in[18]:37 *C 48.293 64.600 +*N chany_bottom_in[18]:38 *C 48.300 64.600 +*N chany_bottom_in[18]:39 *C 48.300 62.617 +*N chany_bottom_in[18]:40 *C 48.308 62.560 +*N chany_bottom_in[18]:41 *C 55.180 62.560 +*N chany_bottom_in[18]:42 *C 55.200 62.553 +*N chany_bottom_in[18]:43 *C 55.200 9.527 +*N chany_bottom_in[18]:44 *C 55.220 9.520 +*N chany_bottom_in[18]:45 *C 57.033 9.520 +*N chany_bottom_in[18]:46 *C 57.040 9.463 +*N chany_bottom_in[18]:47 *C 57.040 6.120 +*N chany_bottom_in[18]:48 *C 57.500 6.120 + +*CAP +0 chany_bottom_in[18] 0.0002353237 +1 mux_left_track_25\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_24\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_24\/mux_l2_in_2_:A1 1e-06 +4 FTB_39__38:A 1e-06 +5 chany_bottom_in[18]:5 0.0002038151 +6 chany_bottom_in[18]:6 0.0002038151 +7 chany_bottom_in[18]:7 4.667546e-05 +8 chany_bottom_in[18]:8 4.667546e-05 +9 chany_bottom_in[18]:9 0.0005169309 +10 chany_bottom_in[18]:10 0.0005169309 +11 chany_bottom_in[18]:11 0.000570029 +12 chany_bottom_in[18]:12 0.000570029 +13 chany_bottom_in[18]:13 7.994135e-05 +14 chany_bottom_in[18]:14 7.994135e-05 +15 chany_bottom_in[18]:15 0.001594632 +16 chany_bottom_in[18]:16 0.001594632 +17 chany_bottom_in[18]:17 0.000183996 +18 chany_bottom_in[18]:18 0.000183996 +19 chany_bottom_in[18]:19 0.000191436 +20 chany_bottom_in[18]:20 3.79312e-05 +21 chany_bottom_in[18]:21 7.314148e-05 +22 chany_bottom_in[18]:22 0.0003478118 +23 chany_bottom_in[18]:23 0.0003478118 +24 chany_bottom_in[18]:24 0.002167729 +25 chany_bottom_in[18]:25 0.002167729 +26 chany_bottom_in[18]:26 0.0003271362 +27 chany_bottom_in[18]:27 0.0001016924 +28 chany_bottom_in[18]:28 4.03259e-05 +29 chany_bottom_in[18]:29 0.00108414 +30 chany_bottom_in[18]:30 0.001013156 +31 chany_bottom_in[18]:31 9.100079e-05 +32 chany_bottom_in[18]:32 4.983538e-05 +33 chany_bottom_in[18]:33 4.983538e-05 +34 chany_bottom_in[18]:34 0.0001144098 +35 chany_bottom_in[18]:35 0.0001144098 +36 chany_bottom_in[18]:36 0.001086047 +37 chany_bottom_in[18]:37 0.001086047 +38 chany_bottom_in[18]:38 0.0002575077 +39 chany_bottom_in[18]:39 0.0001313753 +40 chany_bottom_in[18]:40 0.0003716861 +41 chany_bottom_in[18]:41 0.0003716861 +42 chany_bottom_in[18]:42 0.004495253 +43 chany_bottom_in[18]:43 0.004495253 +44 chany_bottom_in[18]:44 0.0001377603 +45 chany_bottom_in[18]:45 0.0001377603 +46 chany_bottom_in[18]:46 0.0001598631 +47 chany_bottom_in[18]:47 0.0001482111 +48 chany_bottom_in[18]:48 0.0002236717 +49 chany_bottom_in[18]:42 chany_top_in[5]:17 5.038483e-06 +50 chany_bottom_in[18]:42 chany_top_in[5]:25 0.0002728384 +51 chany_bottom_in[18]:44 chany_top_in[5]:15 1.512127e-05 +52 chany_bottom_in[18]:43 chany_top_in[5]:16 5.038483e-06 +53 chany_bottom_in[18]:43 chany_top_in[5]:24 0.0002728384 +54 chany_bottom_in[18]:45 chany_top_in[5]:14 1.512127e-05 +55 chany_bottom_in[18]:40 chanx_right_in[18]:19 0.0003800541 +56 chany_bottom_in[18]:41 chanx_right_in[18]:20 0.0003800541 +57 chany_bottom_in[18]:37 chanx_right_in[18]:20 0.0003033422 +58 chany_bottom_in[18]:36 chanx_right_in[18]:19 0.0003033422 +59 chany_bottom_in[18]:16 chany_bottom_in[13]:33 0.0003273754 +60 chany_bottom_in[18]:15 chany_bottom_in[13]:32 0.0003273754 +61 chany_bottom_in[18]:37 prog_clk[0]:452 0.0001082803 +62 chany_bottom_in[18]:37 prog_clk[0]:445 0.0004817424 +63 chany_bottom_in[18]:35 prog_clk[0]:633 3.302007e-05 +64 chany_bottom_in[18]:36 prog_clk[0]:453 0.0001082803 +65 chany_bottom_in[18]:36 prog_clk[0]:452 0.0004817424 +66 chany_bottom_in[18]:34 prog_clk[0]:628 3.302007e-05 +67 chany_bottom_in[18]:8 chany_top_in[3]:14 2.667613e-05 +68 chany_bottom_in[18]:7 chany_top_in[3] 2.667613e-05 +69 chany_bottom_in[18]:25 chany_top_in[3]:6 5.869707e-05 +70 chany_bottom_in[18]:25 chany_top_in[3]:5 0.0002067117 +71 chany_bottom_in[18]:24 chany_top_in[3]:4 5.869707e-05 +72 chany_bottom_in[18]:24 chany_top_in[3]:6 0.0002067117 +73 chany_bottom_in[18]:16 chany_top_in[7]:11 0.001815727 +74 chany_bottom_in[18]:16 chany_top_in[7]:12 0.0002384571 +75 chany_bottom_in[18]:15 chany_top_in[7]:13 0.0002384571 +76 chany_bottom_in[18]:15 chany_top_in[7]:12 0.001815727 +77 chany_bottom_in[18]:39 mux_tree_tapbuf_size10_10_sram[1]:29 5.035849e-06 +78 chany_bottom_in[18]:39 mux_tree_tapbuf_size10_10_sram[1]:30 2.532703e-06 +79 chany_bottom_in[18]:38 mux_tree_tapbuf_size10_10_sram[1]:20 2.532703e-06 +80 chany_bottom_in[18]:38 mux_tree_tapbuf_size10_10_sram[1]:30 8.257595e-06 +81 chany_bottom_in[18]:37 mux_tree_tapbuf_size10_10_sram[1]:19 0.0003172248 +82 chany_bottom_in[18]:36 mux_tree_tapbuf_size10_10_sram[1]:18 0.0003172248 +83 chany_bottom_in[18]:31 mux_tree_tapbuf_size10_10_sram[1]:20 3.221747e-06 +84 chany_bottom_in[18]:42 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004817877 +85 chany_bottom_in[18]:43 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0004817877 +86 chany_bottom_in[18]:25 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.875731e-06 +87 chany_bottom_in[18]:25 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001491106 +88 chany_bottom_in[18]:24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.875731e-06 +89 chany_bottom_in[18]:24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001491106 +90 chany_bottom_in[18]:28 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 1.264118e-05 +91 chany_bottom_in[18]:30 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.545787e-05 +92 chany_bottom_in[18]:29 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.545787e-05 +93 chany_bottom_in[18]:29 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 1.264118e-05 +94 chany_bottom_in[18]:25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.972276e-05 +95 chany_bottom_in[18]:24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:9 2.972276e-05 +96 chany_bottom_in[18]:10 ropt_net_208:3 2.417946e-05 +97 chany_bottom_in[18]:9 ropt_net_208:4 2.417946e-05 +98 chany_bottom_in[18]:6 ropt_net_208:3 0.0001083233 +99 chany_bottom_in[18]:6 ropt_net_208:6 8.468472e-06 +100 chany_bottom_in[18]:5 ropt_net_208:4 0.0001083233 +101 chany_bottom_in[18]:5 ropt_net_208:7 8.468472e-06 +102 chany_bottom_in[18]:10 ropt_net_213:3 3.878967e-06 +103 chany_bottom_in[18]:9 ropt_net_213:4 3.878967e-06 +104 chany_bottom_in[18]:6 ropt_net_213:3 5.957258e-05 +105 chany_bottom_in[18]:5 ropt_net_213:4 5.957258e-05 +106 chany_bottom_in[18] ropt_net_230:4 1.848282e-05 +107 chany_bottom_in[18]:46 ropt_net_230:5 1.320909e-06 +108 chany_bottom_in[18]:47 ropt_net_230:7 5.935161e-06 +109 chany_bottom_in[18]:47 ropt_net_230:4 1.320909e-06 +110 chany_bottom_in[18]:47 ropt_net_230:2 3.132507e-05 +111 chany_bottom_in[18]:48 ropt_net_230:6 5.935161e-06 +112 chany_bottom_in[18]:48 ropt_net_230:5 1.848282e-05 +113 chany_bottom_in[18]:48 ropt_net_230:3 3.132507e-05 +114 chany_bottom_in[18] ropt_net_229:7 3.74803e-05 +115 chany_bottom_in[18]:46 ropt_net_229:8 7.675767e-05 +116 chany_bottom_in[18]:47 ropt_net_229:7 7.675767e-05 +117 chany_bottom_in[18]:47 ropt_net_229:9 5.180489e-06 +118 chany_bottom_in[18]:48 ropt_net_229:8 3.74803e-05 +119 chany_bottom_in[18]:48 ropt_net_229:10 5.180489e-06 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:48 0.00428125 +1 chany_bottom_in[18]:39 chany_bottom_in[18]:38 0.001770089 +2 chany_bottom_in[18]:40 chany_bottom_in[18]:39 0.00341 +3 chany_bottom_in[18]:41 chany_bottom_in[18]:40 0.001076692 +4 chany_bottom_in[18]:42 chany_bottom_in[18]:41 0.00341 +5 chany_bottom_in[18]:44 chany_bottom_in[18]:43 0.00341 +6 chany_bottom_in[18]:43 chany_bottom_in[18]:42 0.008307249 +7 chany_bottom_in[18]:46 chany_bottom_in[18]:45 0.00341 +8 chany_bottom_in[18]:45 chany_bottom_in[18]:44 0.0002839583 +9 chany_bottom_in[18]:38 chany_bottom_in[18]:37 0.00341 +10 chany_bottom_in[18]:38 chany_bottom_in[18]:31 0.001174107 +11 chany_bottom_in[18]:37 chany_bottom_in[18]:36 0.003961316 +12 chany_bottom_in[18]:35 chany_bottom_in[18]:34 0.002033482 +13 chany_bottom_in[18]:36 chany_bottom_in[18]:35 0.00341 +14 chany_bottom_in[18]:33 chany_bottom_in[18]:32 0.0003370536 +15 chany_bottom_in[18]:34 chany_bottom_in[18]:33 0.0045 +16 chany_bottom_in[18]:32 mux_left_track_25\/mux_l2_in_2_:A1 0.152 +17 chany_bottom_in[18]:28 chany_bottom_in[18]:27 0.0045 +18 chany_bottom_in[18]:27 chany_bottom_in[18]:26 0.001174107 +19 chany_bottom_in[18]:30 chany_bottom_in[18]:29 0.01418304 +20 chany_bottom_in[18]:31 chany_bottom_in[18]:30 0.0045 +21 chany_bottom_in[18]:19 chany_bottom_in[18]:18 0.00341 +22 chany_bottom_in[18]:18 chany_bottom_in[18]:17 0.0002118916 +23 chany_bottom_in[18]:17 chany_bottom_in[18]:16 0.00341 +24 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.007348449 +25 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.000139825 +26 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.00341 +27 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.007801339 +28 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.00341 +29 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.005669643 +30 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.0045 +31 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.0045 +32 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.0005267857 +33 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.003622768 +34 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.0045 +35 chany_bottom_in[18]:5 FTB_39__38:A 0.152 +36 chany_bottom_in[18]:29 mux_top_track_24\/mux_l2_in_1_:A0 0.152 +37 chany_bottom_in[18]:29 chany_bottom_in[18]:28 0.0005223214 +38 chany_bottom_in[18]:25 chany_bottom_in[18]:24 0.03113393 +39 chany_bottom_in[18]:26 chany_bottom_in[18]:25 0.0045 +40 chany_bottom_in[18]:26 chany_bottom_in[18]:19 0.002377233 +41 chany_bottom_in[18]:24 chany_bottom_in[18]:23 0.0045 +42 chany_bottom_in[18]:23 chany_bottom_in[18]:22 0.004776786 +43 chany_bottom_in[18]:21 chany_bottom_in[18]:20 0.0001766304 +44 chany_bottom_in[18]:22 chany_bottom_in[18]:21 0.0045 +45 chany_bottom_in[18]:20 mux_right_track_24\/mux_l2_in_2_:A1 0.152 +46 chany_bottom_in[18]:47 chany_bottom_in[18]:46 0.002984375 +47 chany_bottom_in[18]:48 chany_bottom_in[18]:47 0.0004107143 + +*END + +*D_NET chanx_left_in[14] 0.02823851 //LENGTH 197.350 LUMPCC 0.008270956 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.305 92.480 +*I mux_top_track_4\/mux_l2_in_6_:A0 I *L 0.001631 *C 34.675 80.580 +*I FTB_49__48:A I *L 0.001776 *C 126.960 69.360 +*I mux_right_track_4\/mux_l2_in_7_:A1 I *L 0.00198 *C 121.900 79.900 +*I mux_bottom_track_5\/mux_l2_in_7_:A1 I *L 0.00198 *C 32.660 39.780 +*N chanx_left_in[14]:5 *C 32.660 39.780 +*N chanx_left_in[14]:6 *C 32.660 39.825 +*N chanx_left_in[14]:7 *C 32.660 41.422 +*N chanx_left_in[14]:8 *C 32.663 41.480 +*N chanx_left_in[14]:9 *C 33.105 41.480 +*N chanx_left_in[14]:10 *C 33.120 41.488 +*N chanx_left_in[14]:11 *C 121.938 79.900 +*N chanx_left_in[14]:12 *C 122.360 79.900 +*N chanx_left_in[14]:13 *C 126.922 69.360 +*N chanx_left_in[14]:14 *C 125.625 69.360 +*N chanx_left_in[14]:15 *C 125.580 69.405 +*N chanx_left_in[14]:16 *C 125.580 79.515 +*N chanx_left_in[14]:17 *C 125.535 79.560 +*N chanx_left_in[14]:18 *C 122.360 79.560 +*N chanx_left_in[14]:19 *C 122.360 79.560 +*N chanx_left_in[14]:20 *C 122.353 79.560 +*N chanx_left_in[14]:21 *C 84.040 79.560 +*N chanx_left_in[14]:22 *C 34.638 80.580 +*N chanx_left_in[14]:23 *C 34.085 80.580 +*N chanx_left_in[14]:24 *C 34.040 80.535 +*N chanx_left_in[14]:25 *C 34.040 79.618 +*N chanx_left_in[14]:26 *C 34.040 79.560 +*N chanx_left_in[14]:27 *C 33.140 79.560 +*N chanx_left_in[14]:28 *C 33.120 79.560 +*N chanx_left_in[14]:29 *C 33.120 90.433 +*N chanx_left_in[14]:30 *C 33.100 90.440 +*N chanx_left_in[14]:31 *C 8.300 90.440 +*N chanx_left_in[14]:32 *C 8.280 90.448 +*N chanx_left_in[14]:33 *C 8.280 93.153 +*N chanx_left_in[14]:34 *C 8.260 93.160 +*N chanx_left_in[14]:35 *C 1.380 93.160 + +*CAP +0 chanx_left_in[14] 5.410229e-05 +1 mux_top_track_4\/mux_l2_in_6_:A0 1e-06 +2 FTB_49__48:A 1e-06 +3 mux_right_track_4\/mux_l2_in_7_:A1 1e-06 +4 mux_bottom_track_5\/mux_l2_in_7_:A1 1e-06 +5 chanx_left_in[14]:5 3.226797e-05 +6 chanx_left_in[14]:6 0.0001264047 +7 chanx_left_in[14]:7 0.0001264047 +8 chanx_left_in[14]:8 6.366649e-05 +9 chanx_left_in[14]:9 6.366649e-05 +10 chanx_left_in[14]:10 0.001758817 +11 chanx_left_in[14]:11 4.958159e-05 +12 chanx_left_in[14]:12 7.740729e-05 +13 chanx_left_in[14]:13 0.0001008856 +14 chanx_left_in[14]:14 0.0001008856 +15 chanx_left_in[14]:15 0.0005241817 +16 chanx_left_in[14]:16 0.0005241817 +17 chanx_left_in[14]:17 0.0002236192 +18 chanx_left_in[14]:18 0.0002514449 +19 chanx_left_in[14]:19 3.549205e-05 +20 chanx_left_in[14]:20 0.001602665 +21 chanx_left_in[14]:21 0.004666691 +22 chanx_left_in[14]:22 7.003386e-05 +23 chanx_left_in[14]:23 7.003386e-05 +24 chanx_left_in[14]:24 7.598924e-05 +25 chanx_left_in[14]:25 7.598924e-05 +26 chanx_left_in[14]:26 0.003125399 +27 chanx_left_in[14]:27 6.137331e-05 +28 chanx_left_in[14]:28 0.002293111 +29 chanx_left_in[14]:29 0.0005342941 +30 chanx_left_in[14]:30 0.001084477 +31 chanx_left_in[14]:31 0.001084477 +32 chanx_left_in[14]:32 0.0001617378 +33 chanx_left_in[14]:33 0.0001617378 +34 chanx_left_in[14]:34 0.0003642166 +35 chanx_left_in[14]:35 0.0004183189 +36 chanx_left_in[14]:20 chanx_left_in[10]:13 0.0006029588 +37 chanx_left_in[14]:21 chanx_left_in[10]:14 0.0006029588 +38 chanx_left_in[14]:30 chanx_left_in[13]:32 0.0001286687 +39 chanx_left_in[14]:30 chanx_left_in[13]:36 2.319499e-05 +40 chanx_left_in[14]:31 chanx_left_in[13] 2.319499e-05 +41 chanx_left_in[14]:31 chanx_left_in[13]:33 0.0001286687 +42 chanx_left_in[14]:32 chanx_left_in[13]:34 2.565019e-05 +43 chanx_left_in[14]:34 chanx_left_in[13]:36 0.0003978043 +44 chanx_left_in[14]:33 chanx_left_in[13]:35 2.565019e-05 +45 chanx_left_in[14]:35 chanx_left_in[13] 0.0003978043 +46 chanx_left_in[14]:20 prog_clk[0]:272 4.233549e-05 +47 chanx_left_in[14]:20 prog_clk[0]:164 6.839347e-05 +48 chanx_left_in[14]:20 prog_clk[0]:276 4.797636e-05 +49 chanx_left_in[14]:20 prog_clk[0]:268 0.0004086275 +50 chanx_left_in[14]:26 prog_clk[0]:277 2.760368e-06 +51 chanx_left_in[14]:30 prog_clk[0]:614 3.294357e-05 +52 chanx_left_in[14]:30 prog_clk[0]:608 7.347285e-05 +53 chanx_left_in[14]:31 prog_clk[0]:614 7.347285e-05 +54 chanx_left_in[14]:31 prog_clk[0]:613 3.294357e-05 +55 chanx_left_in[14]:32 prog_clk[0]:652 5.880189e-06 +56 chanx_left_in[14]:33 prog_clk[0]:651 5.880189e-06 +57 chanx_left_in[14]:21 prog_clk[0]:277 4.797636e-05 +58 chanx_left_in[14]:21 prog_clk[0]:165 6.839347e-05 +59 chanx_left_in[14]:21 prog_clk[0]:276 4.509586e-05 +60 chanx_left_in[14]:21 prog_clk[0]:269 0.0004086275 +61 chanx_left_in[14]:26 chany_bottom_in[15]:8 0.0004862554 +62 chanx_left_in[14]:21 chany_bottom_in[15]:7 0.0004862554 +63 chanx_left_in[14]:28 chanx_left_in[19]:11 0.0001156335 +64 chanx_left_in[14]:28 chanx_left_in[19]:10 0.0003080034 +65 chanx_left_in[14]:29 chanx_left_in[19]:10 0.0001156335 +66 chanx_left_in[14]:10 chanx_left_in[19]:11 0.0003080034 +67 chanx_left_in[14]:27 mux_tree_tapbuf_size12_6_sram[1]:33 2.265378e-05 +68 chanx_left_in[14]:26 mux_tree_tapbuf_size12_6_sram[1]:33 0.0004090404 +69 chanx_left_in[14]:26 mux_tree_tapbuf_size12_6_sram[1]:32 2.265378e-05 +70 chanx_left_in[14]:21 mux_tree_tapbuf_size12_6_sram[1]:32 0.0004090404 +71 chanx_left_in[14]:28 mux_tree_tapbuf_size16_3_sram[1]:37 7.999596e-07 +72 chanx_left_in[14]:30 mux_tree_tapbuf_size16_3_sram[1]:38 0.0001051847 +73 chanx_left_in[14]:30 mux_tree_tapbuf_size16_3_sram[1]:39 0.0001614058 +74 chanx_left_in[14]:31 mux_tree_tapbuf_size16_3_sram[1]:30 0.0001051847 +75 chanx_left_in[14]:31 mux_tree_tapbuf_size16_3_sram[1]:38 0.0001614058 +76 chanx_left_in[14]:10 mux_tree_tapbuf_size16_3_sram[1]:36 7.999596e-07 +77 chanx_left_in[14]:28 mux_tree_tapbuf_size16_3_sram[2]:25 0.0003189166 +78 chanx_left_in[14]:28 mux_tree_tapbuf_size16_3_sram[2]:26 2.134297e-05 +79 chanx_left_in[14]:30 mux_tree_tapbuf_size16_3_sram[2]:17 3.338994e-05 +80 chanx_left_in[14]:29 mux_tree_tapbuf_size16_3_sram[2]:25 2.134297e-05 +81 chanx_left_in[14]:31 mux_tree_tapbuf_size16_3_sram[2]:16 3.338994e-05 +82 chanx_left_in[14]:10 mux_tree_tapbuf_size16_3_sram[2]:26 0.0003189166 +83 chanx_left_in[14]:16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 6.554305e-05 +84 chanx_left_in[14]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 6.554305e-05 +85 chanx_left_in[14]:20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002266422 +86 chanx_left_in[14]:21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002266422 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:35 0.0001065333 +1 chanx_left_in[14]:18 chanx_left_in[14]:17 0.002834822 +2 chanx_left_in[14]:18 chanx_left_in[14]:12 0.0003035715 +3 chanx_left_in[14]:19 chanx_left_in[14]:18 0.0045 +4 chanx_left_in[14]:20 chanx_left_in[14]:19 0.00341 +5 chanx_left_in[14]:27 chanx_left_in[14]:26 0.000141 +6 chanx_left_in[14]:28 chanx_left_in[14]:27 0.00341 +7 chanx_left_in[14]:28 chanx_left_in[14]:10 0.005964691 +8 chanx_left_in[14]:25 chanx_left_in[14]:24 0.0008191965 +9 chanx_left_in[14]:26 chanx_left_in[14]:25 0.00341 +10 chanx_left_in[14]:26 chanx_left_in[14]:21 0.007833333 +11 chanx_left_in[14]:23 chanx_left_in[14]:22 0.0004933036 +12 chanx_left_in[14]:24 chanx_left_in[14]:23 0.0045 +13 chanx_left_in[14]:22 mux_top_track_4\/mux_l2_in_6_:A0 0.152 +14 chanx_left_in[14]:30 chanx_left_in[14]:29 0.00341 +15 chanx_left_in[14]:29 chanx_left_in[14]:28 0.001703358 +16 chanx_left_in[14]:31 chanx_left_in[14]:30 0.003885333 +17 chanx_left_in[14]:32 chanx_left_in[14]:31 0.00341 +18 chanx_left_in[14]:34 chanx_left_in[14]:33 0.00341 +19 chanx_left_in[14]:33 chanx_left_in[14]:32 0.0004237833 +20 chanx_left_in[14]:9 chanx_left_in[14]:8 6.499218e-05 +21 chanx_left_in[14]:10 chanx_left_in[14]:9 0.00341 +22 chanx_left_in[14]:7 chanx_left_in[14]:6 0.001426339 +23 chanx_left_in[14]:8 chanx_left_in[14]:7 0.00341 +24 chanx_left_in[14]:5 mux_bottom_track_5\/mux_l2_in_7_:A1 0.152 +25 chanx_left_in[14]:6 chanx_left_in[14]:5 0.0045 +26 chanx_left_in[14]:11 mux_right_track_4\/mux_l2_in_7_:A1 0.152 +27 chanx_left_in[14]:17 chanx_left_in[14]:16 0.0045 +28 chanx_left_in[14]:16 chanx_left_in[14]:15 0.009026786 +29 chanx_left_in[14]:14 chanx_left_in[14]:13 0.001158482 +30 chanx_left_in[14]:15 chanx_left_in[14]:14 0.0045 +31 chanx_left_in[14]:13 FTB_49__48:A 0.152 +32 chanx_left_in[14]:12 chanx_left_in[14]:11 0.0003772322 +33 chanx_left_in[14]:35 chanx_left_in[14]:34 0.001077867 +34 chanx_left_in[14]:21 chanx_left_in[14]:20 0.006002291 + +*END + +*D_NET chany_top_in[19] 0.00913095 //LENGTH 78.240 LUMPCC 0.0006807516 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 59.340 129.235 +*I mux_left_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 71.205 105.060 +*I mux_right_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 90.260 105.060 +*N chany_top_in[19]:3 *C 90.223 105.060 +*N chany_top_in[19]:4 *C 71.243 105.060 +*N chany_top_in[19]:5 *C 71.760 105.060 +*N chany_top_in[19]:6 *C 71.760 104.720 +*N chany_top_in[19]:7 *C 85.560 104.720 +*N chany_top_in[19]:8 *C 85.560 105.060 +*N chany_top_in[19]:9 *C 89.700 105.060 +*N chany_top_in[19]:10 *C 89.700 105.105 +*N chany_top_in[19]:11 *C 89.700 128.463 +*N chany_top_in[19]:12 *C 89.700 128.528 +*N chany_top_in[19]:13 *C 89.700 129.200 +*N chany_top_in[19]:14 *C 66.700 129.200 +*N chany_top_in[19]:15 *C 66.700 128.520 +*N chany_top_in[19]:16 *C 59.348 128.520 +*N chany_top_in[19]:17 *C 59.340 128.578 + +*CAP +0 chany_top_in[19] 5.786886e-05 +1 mux_left_track_3\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:A1 1e-06 +3 chany_top_in[19]:3 4.487805e-05 +4 chany_top_in[19]:4 5.651263e-05 +5 chany_top_in[19]:5 8.402773e-05 +6 chany_top_in[19]:6 0.00090473 +7 chany_top_in[19]:7 0.0009039948 +8 chany_top_in[19]:8 0.0002710669 +9 chany_top_in[19]:9 0.0003218028 +10 chany_top_in[19]:10 0.001002671 +11 chany_top_in[19]:11 0.001002671 +12 chany_top_in[19]:12 4.585683e-05 +13 chany_top_in[19]:13 0.001414322 +14 chany_top_in[19]:14 0.001418991 +15 chany_top_in[19]:15 0.0004557307 +16 chany_top_in[19]:16 0.0004052051 +17 chany_top_in[19]:17 5.786886e-05 +18 chany_top_in[19]:10 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 7.926962e-05 +19 chany_top_in[19]:11 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 7.926962e-05 +20 chany_top_in[19]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001791069 +21 chany_top_in[19]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001791069 +22 chany_top_in[19]:10 BUF_net_90:5 8.199929e-05 +23 chany_top_in[19]:11 BUF_net_90:4 8.199929e-05 + +*RES +0 chany_top_in[19] chany_top_in[19]:17 0.0005870535 +1 chany_top_in[19]:9 chany_top_in[19]:8 0.003696429 +2 chany_top_in[19]:9 chany_top_in[19]:3 0.0004665179 +3 chany_top_in[19]:10 chany_top_in[19]:9 0.0045 +4 chany_top_in[19]:11 chany_top_in[19]:10 0.02085491 +5 chany_top_in[19]:12 chany_top_in[19]:11 0.00341 +6 chany_top_in[19]:17 chany_top_in[19]:16 0.00341 +7 chany_top_in[19]:16 chany_top_in[19]:15 0.001151892 +8 chany_top_in[19]:4 mux_left_track_3\/mux_l1_in_1_:A1 0.152 +9 chany_top_in[19]:3 mux_right_track_0\/mux_l1_in_1_:A1 0.152 +10 chany_top_in[19]:5 chany_top_in[19]:4 0.0004620536 +11 chany_top_in[19]:6 chany_top_in[19]:5 0.0003035715 +12 chany_top_in[19]:7 chany_top_in[19]:6 0.01232143 +13 chany_top_in[19]:8 chany_top_in[19]:7 0.0003035715 +14 chany_top_in[19]:15 chany_top_in[19]:14 0.0001065333 +15 chany_top_in[19]:14 chany_top_in[19]:13 0.003603333 +16 chany_top_in[19]:13 chany_top_in[19]:12 0.0001053583 + +*END + +*D_NET top_left_grid_pin_40_[0] 0.007290765 //LENGTH 54.660 LUMPCC 0.0006642256 DR + +*CONN +*P top_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 122.400 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 59.055 109.820 +*I mux_top_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 62.275 118.660 +*I mux_top_track_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 33.755 113.220 +*N top_left_grid_pin_40_[0]:4 *C 33.718 113.220 +*N top_left_grid_pin_40_[0]:5 *C 33.120 113.220 +*N top_left_grid_pin_40_[0]:6 *C 33.120 112.880 +*N top_left_grid_pin_40_[0]:7 *C 32.705 112.880 +*N top_left_grid_pin_40_[0]:8 *C 32.660 112.925 +*N top_left_grid_pin_40_[0]:9 *C 62.238 118.660 +*N top_left_grid_pin_40_[0]:10 *C 59.385 118.660 +*N top_left_grid_pin_40_[0]:11 *C 59.340 118.615 +*N top_left_grid_pin_40_[0]:12 *C 59.055 109.820 +*N top_left_grid_pin_40_[0]:13 *C 59.340 109.820 +*N top_left_grid_pin_40_[0]:14 *C 59.340 109.865 +*N top_left_grid_pin_40_[0]:15 *C 59.340 117.640 +*N top_left_grid_pin_40_[0]:16 *C 59.333 117.640 +*N top_left_grid_pin_40_[0]:17 *C 32.668 117.640 +*N top_left_grid_pin_40_[0]:18 *C 32.660 117.640 +*N top_left_grid_pin_40_[0]:19 *C 32.660 122.343 +*N top_left_grid_pin_40_[0]:20 *C 32.653 122.400 + +*CAP +0 top_left_grid_pin_40_[0] 0.0002148522 +1 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_0\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_4\/mux_l2_in_2_:A0 1e-06 +4 top_left_grid_pin_40_[0]:4 5.980133e-05 +5 top_left_grid_pin_40_[0]:5 8.560148e-05 +6 top_left_grid_pin_40_[0]:6 7.229642e-05 +7 top_left_grid_pin_40_[0]:7 4.649627e-05 +8 top_left_grid_pin_40_[0]:8 0.0002682068 +9 top_left_grid_pin_40_[0]:9 0.0001285903 +10 top_left_grid_pin_40_[0]:10 0.0001285903 +11 top_left_grid_pin_40_[0]:11 4.72408e-05 +12 top_left_grid_pin_40_[0]:12 5.118796e-05 +13 top_left_grid_pin_40_[0]:13 5.499554e-05 +14 top_left_grid_pin_40_[0]:14 0.0003395558 +15 top_left_grid_pin_40_[0]:15 0.000425566 +16 top_left_grid_pin_40_[0]:16 0.00187825 +17 top_left_grid_pin_40_[0]:17 0.00187825 +18 top_left_grid_pin_40_[0]:18 0.0005162281 +19 top_left_grid_pin_40_[0]:19 0.0002129768 +20 top_left_grid_pin_40_[0]:20 0.0002148522 +21 top_left_grid_pin_40_[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001177056 +22 top_left_grid_pin_40_[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001177056 +23 top_left_grid_pin_40_[0]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.000129542 +24 top_left_grid_pin_40_[0]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 2.947903e-05 +25 top_left_grid_pin_40_[0]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.000129542 +26 top_left_grid_pin_40_[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 2.947903e-05 +27 top_left_grid_pin_40_[0]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.538618e-05 +28 top_left_grid_pin_40_[0]:19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.538618e-05 + +*RES +0 top_left_grid_pin_40_[0] top_left_grid_pin_40_[0]:20 0.0004547249 +1 top_left_grid_pin_40_[0]:18 top_left_grid_pin_40_[0]:17 0.00341 +2 top_left_grid_pin_40_[0]:18 top_left_grid_pin_40_[0]:8 0.004209822 +3 top_left_grid_pin_40_[0]:17 top_left_grid_pin_40_[0]:16 0.004177517 +4 top_left_grid_pin_40_[0]:15 top_left_grid_pin_40_[0]:14 0.006941965 +5 top_left_grid_pin_40_[0]:15 top_left_grid_pin_40_[0]:11 0.0008705358 +6 top_left_grid_pin_40_[0]:16 top_left_grid_pin_40_[0]:15 0.00341 +7 top_left_grid_pin_40_[0]:13 top_left_grid_pin_40_[0]:12 0.0001548913 +8 top_left_grid_pin_40_[0]:14 top_left_grid_pin_40_[0]:13 0.0045 +9 top_left_grid_pin_40_[0]:12 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +10 top_left_grid_pin_40_[0]:7 top_left_grid_pin_40_[0]:6 0.0003705357 +11 top_left_grid_pin_40_[0]:8 top_left_grid_pin_40_[0]:7 0.0045 +12 top_left_grid_pin_40_[0]:4 mux_top_track_4\/mux_l2_in_2_:A0 0.152 +13 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:9 0.002546875 +14 top_left_grid_pin_40_[0]:11 top_left_grid_pin_40_[0]:10 0.0045 +15 top_left_grid_pin_40_[0]:9 mux_top_track_0\/mux_l1_in_1_:A0 0.152 +16 top_left_grid_pin_40_[0]:19 top_left_grid_pin_40_[0]:18 0.004198661 +17 top_left_grid_pin_40_[0]:20 top_left_grid_pin_40_[0]:19 0.00341 +18 top_left_grid_pin_40_[0]:6 top_left_grid_pin_40_[0]:5 0.0003035715 +19 top_left_grid_pin_40_[0]:5 top_left_grid_pin_40_[0]:4 0.0005334822 + +*END + +*D_NET chanx_right_in[19] 0.03058681 //LENGTH 169.370 LUMPCC 0.0166291 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 140.450 31.280 +*I mux_bottom_track_33\/mux_l1_in_1_:A1 I *L 0.00198 *C 25.665 34.340 +*I mux_top_track_24\/mux_l1_in_2_:A1 I *L 0.00198 *C 76.265 61.540 +*N chanx_right_in[19]:3 *C 76.303 61.540 +*N chanx_right_in[19]:4 *C 78.155 61.540 +*N chanx_right_in[19]:5 *C 78.200 61.495 +*N chanx_right_in[19]:6 *C 78.200 58.538 +*N chanx_right_in[19]:7 *C 78.193 58.480 +*N chanx_right_in[19]:8 *C 60.740 58.480 +*N chanx_right_in[19]:9 *C 60.720 58.473 +*N chanx_right_in[19]:10 *C 25.703 34.340 +*N chanx_right_in[19]:11 *C 27.555 34.340 +*N chanx_right_in[19]:12 *C 27.600 34.385 +*N chanx_right_in[19]:13 *C 27.600 36.663 +*N chanx_right_in[19]:14 *C 27.608 36.720 +*N chanx_right_in[19]:15 *C 60.700 36.720 +*N chanx_right_in[19]:16 *C 60.720 36.720 +*N chanx_right_in[19]:17 *C 60.720 31.288 +*N chanx_right_in[19]:18 *C 60.740 31.280 +*N chanx_right_in[19]:19 *C 110.530 31.280 + +*CAP +0 chanx_right_in[19] 0.0008530322 +1 mux_bottom_track_33\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_2_:A1 1e-06 +3 chanx_right_in[19]:3 0.0001365241 +4 chanx_right_in[19]:4 0.0001365241 +5 chanx_right_in[19]:5 0.0002220345 +6 chanx_right_in[19]:6 0.0002220345 +7 chanx_right_in[19]:7 0.001420628 +8 chanx_right_in[19]:8 0.001420628 +9 chanx_right_in[19]:9 0.000925403 +10 chanx_right_in[19]:10 0.0001411895 +11 chanx_right_in[19]:11 0.0001411895 +12 chanx_right_in[19]:12 0.0001439983 +13 chanx_right_in[19]:13 0.0001439983 +14 chanx_right_in[19]:14 0.0009866103 +15 chanx_right_in[19]:15 0.0009866103 +16 chanx_right_in[19]:16 0.00109 +17 chanx_right_in[19]:17 0.0001645974 +18 chanx_right_in[19]:18 0.001983835 +19 chanx_right_in[19]:19 0.002836867 +20 chanx_right_in[19] chanx_right_in[13] 4.390141e-05 +21 chanx_right_in[19] chanx_right_in[13]:35 0.000134247 +22 chanx_right_in[19] chanx_right_in[13]:36 0.001514567 +23 chanx_right_in[19]:18 chanx_right_in[13]:34 0.002543444 +24 chanx_right_in[19]:19 chanx_right_in[13]:34 0.000134247 +25 chanx_right_in[19]:19 chanx_right_in[13]:35 0.004058011 +26 chanx_right_in[19]:19 chanx_right_in[13]:37 4.390141e-05 +27 chanx_right_in[19]:9 chany_bottom_in[10]:44 0.0001199977 +28 chanx_right_in[19]:9 chany_bottom_in[10]:45 0.0002614167 +29 chanx_right_in[19]:17 chany_bottom_in[10]:46 0.0001146214 +30 chanx_right_in[19]:16 chany_bottom_in[10]:45 0.0002346191 +31 chanx_right_in[19]:16 chany_bottom_in[10]:46 0.0002614167 +32 chanx_right_in[19]:15 chanx_left_in[2]:29 0.001099865 +33 chanx_right_in[19]:14 chanx_left_in[2]:30 0.001099865 +34 chanx_right_in[19]:9 chanx_left_in[4]:36 0.000196036 +35 chanx_right_in[19]:17 chanx_left_in[4]:35 7.174649e-05 +36 chanx_right_in[19]:16 chanx_left_in[4]:35 0.000196036 +37 chanx_right_in[19]:16 chanx_left_in[4]:36 7.174649e-05 +38 chanx_right_in[19]:18 prog_clk[0]:138 0.0001416945 +39 chanx_right_in[19]:18 prog_clk[0]:303 5.821878e-05 +40 chanx_right_in[19]:18 prog_clk[0]:323 0.0001850688 +41 chanx_right_in[19]:15 prog_clk[0]:306 5.154867e-06 +42 chanx_right_in[19]:14 prog_clk[0]:321 5.154867e-06 +43 chanx_right_in[19]:19 prog_clk[0]:133 0.0001416945 +44 chanx_right_in[19]:19 prog_clk[0]:138 5.821878e-05 +45 chanx_right_in[19]:19 prog_clk[0]:303 0.0001850688 +46 chanx_right_in[19]:15 chanx_left_in[11]:10 0.0005165404 +47 chanx_right_in[19]:15 chanx_left_in[11]:11 0.001308032 +48 chanx_right_in[19]:14 chanx_left_in[11]:12 0.001308032 +49 chanx_right_in[19]:14 chanx_left_in[11]:11 0.0005165404 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:19 0.004687466 +1 chanx_right_in[19]:8 chanx_right_in[19]:7 0.002734225 +2 chanx_right_in[19]:9 chanx_right_in[19]:8 0.00341 +3 chanx_right_in[19]:6 chanx_right_in[19]:5 0.002640625 +4 chanx_right_in[19]:7 chanx_right_in[19]:6 0.00341 +5 chanx_right_in[19]:4 chanx_right_in[19]:3 0.001654018 +6 chanx_right_in[19]:5 chanx_right_in[19]:4 0.0045 +7 chanx_right_in[19]:3 mux_top_track_24\/mux_l1_in_2_:A1 0.152 +8 chanx_right_in[19]:18 chanx_right_in[19]:17 0.00341 +9 chanx_right_in[19]:17 chanx_right_in[19]:16 0.0008510916 +10 chanx_right_in[19]:15 chanx_right_in[19]:14 0.005184491 +11 chanx_right_in[19]:16 chanx_right_in[19]:15 0.00341 +12 chanx_right_in[19]:16 chanx_right_in[19]:9 0.003407891 +13 chanx_right_in[19]:13 chanx_right_in[19]:12 0.002033482 +14 chanx_right_in[19]:14 chanx_right_in[19]:13 0.00341 +15 chanx_right_in[19]:11 chanx_right_in[19]:10 0.001654018 +16 chanx_right_in[19]:12 chanx_right_in[19]:11 0.0045 +17 chanx_right_in[19]:10 mux_bottom_track_33\/mux_l1_in_1_:A1 0.152 +18 chanx_right_in[19]:19 chanx_right_in[19]:18 0.007800433 + +*END + +*D_NET chany_bottom_in[11] 0.02049536 //LENGTH 119.765 LUMPCC 0.01048295 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 86.480 1.290 +*I mux_left_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 66.530 60.520 +*I mux_right_track_2\/mux_l1_in_4_:A1 I *L 0.00198 *C 91.180 90.780 +*N chany_bottom_in[11]:3 *C 91.080 90.780 +*N chany_bottom_in[11]:4 *C 91.080 90.735 +*N chany_bottom_in[11]:5 *C 91.080 87.098 +*N chany_bottom_in[11]:6 *C 91.073 87.040 +*N chany_bottom_in[11]:7 *C 90.180 87.040 +*N chany_bottom_in[11]:8 *C 90.160 87.032 +*N chany_bottom_in[11]:9 *C 66.530 60.520 +*N chany_bottom_in[11]:10 *C 66.700 60.520 +*N chany_bottom_in[11]:11 *C 66.700 60.520 +*N chany_bottom_in[11]:12 *C 66.708 60.520 +*N chany_bottom_in[11]:13 *C 90.140 60.520 +*N chany_bottom_in[11]:14 *C 90.160 60.520 +*N chany_bottom_in[11]:15 *C 90.160 52.555 +*N chany_bottom_in[11]:16 *C 90.160 2.728 +*N chany_bottom_in[11]:17 *C 90.140 2.720 +*N chany_bottom_in[11]:18 *C 86.487 2.720 +*N chany_bottom_in[11]:19 *C 86.480 2.663 + +*CAP +0 chany_bottom_in[11] 7.278813e-05 +1 mux_left_track_25\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_2\/mux_l1_in_4_:A1 1e-06 +3 chany_bottom_in[11]:3 3.419465e-05 +4 chany_bottom_in[11]:4 0.0002859566 +5 chany_bottom_in[11]:5 0.0002859566 +6 chany_bottom_in[11]:6 0.0001432005 +7 chany_bottom_in[11]:7 0.0001432005 +8 chany_bottom_in[11]:8 0.001109395 +9 chany_bottom_in[11]:9 5.230337e-05 +10 chany_bottom_in[11]:10 5.66686e-05 +11 chany_bottom_in[11]:11 3.759945e-05 +12 chany_bottom_in[11]:12 0.001705597 +13 chany_bottom_in[11]:13 0.001705597 +14 chany_bottom_in[11]:14 0.001264235 +15 chany_bottom_in[11]:15 0.001455264 +16 chany_bottom_in[11]:16 0.001300423 +17 chany_bottom_in[11]:17 0.0001426175 +18 chany_bottom_in[11]:18 0.0001426175 +19 chany_bottom_in[11]:19 7.278813e-05 +20 chany_bottom_in[11]:17 chany_bottom_in[2]:35 0.000221514 +21 chany_bottom_in[11]:16 chany_bottom_in[2]:34 8.445636e-05 +22 chany_bottom_in[11]:18 chany_bottom_in[2]:36 0.000221514 +23 chany_bottom_in[11]:15 chany_bottom_in[2]:33 8.445636e-05 +24 chany_bottom_in[11]:16 chanx_right_in[3]:10 0.000615907 +25 chany_bottom_in[11]:14 chanx_right_in[3]:9 0.0003412684 +26 chany_bottom_in[11]:14 chanx_right_in[3]:10 0.001123884 +27 chany_bottom_in[11]:8 chanx_right_in[3]:9 0.001123884 +28 chany_bottom_in[11]:15 chanx_right_in[3]:9 0.000615907 +29 chany_bottom_in[11]:15 chanx_right_in[3]:10 0.0003412684 +30 chany_bottom_in[11]:16 chany_bottom_in[3] 1.409075e-05 +31 chany_bottom_in[11]:16 chany_bottom_in[3]:27 0.001514212 +32 chany_bottom_in[11]:14 chany_bottom_in[3]:26 0.0003833601 +33 chany_bottom_in[11]:14 chany_bottom_in[3]:27 0.0001352103 +34 chany_bottom_in[11]:8 chany_bottom_in[3]:19 3.450404e-05 +35 chany_bottom_in[11]:8 chany_bottom_in[3]:26 0.0001352103 +36 chany_bottom_in[11]:15 chany_bottom_in[3]:26 0.001514212 +37 chany_bottom_in[11]:15 chany_bottom_in[3]:27 0.000348856 +38 chany_bottom_in[11]:15 chany_bottom_in[3]:30 1.409075e-05 +39 chany_bottom_in[11] chany_bottom_in[7] 1.954849e-05 +40 chany_bottom_in[11]:17 chany_bottom_in[7]:3 2.224475e-05 +41 chany_bottom_in[11]:16 chany_bottom_in[7]:17 0.0004296561 +42 chany_bottom_in[11]:19 chany_bottom_in[7]:19 1.954849e-05 +43 chany_bottom_in[11]:18 chany_bottom_in[7]:18 2.224475e-05 +44 chany_bottom_in[11]:13 chany_bottom_in[7]:15 2.325856e-06 +45 chany_bottom_in[11]:12 chany_bottom_in[7]:14 2.325856e-06 +46 chany_bottom_in[11]:15 chany_bottom_in[7]:16 0.0004296561 +47 chany_bottom_in[11]:13 mux_tree_tapbuf_size10_4_sram[0]:20 0.0003337995 +48 chany_bottom_in[11]:12 mux_tree_tapbuf_size10_4_sram[0]:19 0.0003337995 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:19 0.001225446 +1 chany_bottom_in[11]:17 chany_bottom_in[11]:16 0.00341 +2 chany_bottom_in[11]:16 chany_bottom_in[11]:15 0.007806308 +3 chany_bottom_in[11]:19 chany_bottom_in[11]:18 0.00341 +4 chany_bottom_in[11]:18 chany_bottom_in[11]:17 0.000572225 +5 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.003671092 +6 chany_bottom_in[11]:14 chany_bottom_in[11]:13 0.00341 +7 chany_bottom_in[11]:14 chany_bottom_in[11]:8 0.004153625 +8 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.0045 +9 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.00341 +10 chany_bottom_in[11]:10 chany_bottom_in[11]:9 9.239132e-05 +11 chany_bottom_in[11]:9 mux_left_track_25\/mux_l2_in_1_:A0 0.152 +12 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.000139825 +13 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.00341 +14 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.003247768 +15 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.00341 +16 chany_bottom_in[11]:3 mux_right_track_2\/mux_l1_in_4_:A1 0.152 +17 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.0045 +18 chany_bottom_in[11]:15 chany_bottom_in[11]:14 0.00124785 + +*END + +*D_NET chanx_left_in[0] 0.02287486 //LENGTH 151.015 LUMPCC 0.007688352 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.305 76.160 +*I mux_bottom_track_33\/mux_l1_in_2_:A0 I *L 0.001631 *C 24.670 39.100 +*I mux_top_track_0\/mux_l1_in_4_:A0 I *L 0.001631 *C 73.315 96.900 +*N chanx_left_in[0]:3 *C 73.278 96.900 +*N chanx_left_in[0]:4 *C 69.045 96.900 +*N chanx_left_in[0]:5 *C 69.000 96.855 +*N chanx_left_in[0]:6 *C 69.000 93.898 +*N chanx_left_in[0]:7 *C 68.993 93.840 +*N chanx_left_in[0]:8 *C 23.940 93.840 +*N chanx_left_in[0]:9 *C 23.920 93.833 +*N chanx_left_in[0]:10 *C 23.920 76.847 +*N chanx_left_in[0]:11 *C 23.900 76.840 +*N chanx_left_in[0]:12 *C 24.707 39.100 +*N chanx_left_in[0]:13 *C 25.715 39.100 +*N chanx_left_in[0]:14 *C 25.760 39.145 +*N chanx_left_in[0]:15 *C 25.760 46.183 +*N chanx_left_in[0]:16 *C 25.753 46.240 +*N chanx_left_in[0]:17 *C 21.180 46.240 +*N chanx_left_in[0]:18 *C 21.160 46.248 +*N chanx_left_in[0]:19 *C 21.160 61.193 +*N chanx_left_in[0]:20 *C 21.140 61.200 +*N chanx_left_in[0]:21 *C 10.140 61.200 +*N chanx_left_in[0]:22 *C 10.120 61.208 +*N chanx_left_in[0]:23 *C 10.120 76.833 +*N chanx_left_in[0]:24 *C 10.120 76.840 +*N chanx_left_in[0]:25 *C 1.380 76.840 + +*CAP +0 chanx_left_in[0] 4.725655e-05 +1 mux_bottom_track_33\/mux_l1_in_2_:A0 1e-06 +2 mux_top_track_0\/mux_l1_in_4_:A0 1e-06 +3 chanx_left_in[0]:3 0.0002880813 +4 chanx_left_in[0]:4 0.0002880813 +5 chanx_left_in[0]:5 0.0001459535 +6 chanx_left_in[0]:6 0.0001459535 +7 chanx_left_in[0]:7 0.002278126 +8 chanx_left_in[0]:8 0.002278126 +9 chanx_left_in[0]:9 0.0006590312 +10 chanx_left_in[0]:10 0.0006590312 +11 chanx_left_in[0]:11 0.0006119565 +12 chanx_left_in[0]:12 8.410928e-05 +13 chanx_left_in[0]:13 8.410928e-05 +14 chanx_left_in[0]:14 0.0004015682 +15 chanx_left_in[0]:15 0.0004015682 +16 chanx_left_in[0]:16 0.0002752666 +17 chanx_left_in[0]:17 0.0002752666 +18 chanx_left_in[0]:18 0.000811721 +19 chanx_left_in[0]:19 0.000811721 +20 chanx_left_in[0]:20 0.0006820706 +21 chanx_left_in[0]:21 0.0006820706 +22 chanx_left_in[0]:22 0.0009157381 +23 chanx_left_in[0]:23 0.0009157381 +24 chanx_left_in[0]:24 0.001003331 +25 chanx_left_in[0]:25 0.0004386314 +26 chanx_left_in[0]:17 chanx_right_in[4]:17 0.0002766527 +27 chanx_left_in[0]:16 chanx_right_in[4]:18 0.0002766527 +28 chanx_left_in[0]:6 chanx_right_in[4]:23 4.089178e-05 +29 chanx_left_in[0]:5 chanx_right_in[4]:24 4.089178e-05 +30 chanx_left_in[0]:8 chanx_left_in[4]:27 0.000597338 +31 chanx_left_in[0]:7 chanx_left_in[4]:26 0.000597338 +32 chanx_left_in[0]:24 prog_clk[0]:668 4.119161e-05 +33 chanx_left_in[0]:15 prog_clk[0]:481 1.152108e-06 +34 chanx_left_in[0]:14 prog_clk[0]:484 1.152108e-06 +35 chanx_left_in[0]:8 prog_clk[0]:601 0.0004884661 +36 chanx_left_in[0]:8 prog_clk[0]:602 0.0001632558 +37 chanx_left_in[0]:8 prog_clk[0]:613 1.989362e-05 +38 chanx_left_in[0]:8 prog_clk[0]:614 4.499739e-05 +39 chanx_left_in[0]:7 prog_clk[0]:596 0.0004884661 +40 chanx_left_in[0]:7 prog_clk[0]:601 0.0001632558 +41 chanx_left_in[0]:7 prog_clk[0]:608 4.499739e-05 +42 chanx_left_in[0]:7 prog_clk[0]:614 1.989362e-05 +43 chanx_left_in[0]:25 prog_clk[0]:669 4.119161e-05 +44 chanx_left_in[0]:24 chanx_left_in[15] 0.0007589634 +45 chanx_left_in[0]:24 chanx_left_in[15]:9 0.0004903292 +46 chanx_left_in[0]:11 chanx_left_in[15]:9 0.0007589634 +47 chanx_left_in[0]:25 chanx_left_in[15] 0.0004903292 +48 chanx_left_in[0]:8 chanx_left_in[19]:9 0.0003053735 +49 chanx_left_in[0]:7 chanx_left_in[19]:8 0.0003053735 +50 chanx_left_in[0]:10 left_top_grid_pin_47_[0]:10 0.0003246435 +51 chanx_left_in[0]:9 left_top_grid_pin_47_[0]:11 0.0003246435 +52 chanx_left_in[0]:19 mux_tree_tapbuf_size16_3_sram[1]:37 7.650271e-05 +53 chanx_left_in[0]:17 mux_tree_tapbuf_size16_3_sram[1]:35 4.034823e-06 +54 chanx_left_in[0]:18 mux_tree_tapbuf_size16_3_sram[1]:36 7.650271e-05 +55 chanx_left_in[0]:16 mux_tree_tapbuf_size16_3_sram[1]:31 4.034823e-06 +56 chanx_left_in[0]:10 mux_tree_tapbuf_size16_3_sram[1]:36 0.0002104896 +57 chanx_left_in[0]:9 mux_tree_tapbuf_size16_3_sram[1]:37 0.0002104896 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:25 0.0001065333 +1 chanx_left_in[0]:24 chanx_left_in[0]:23 0.00341 +2 chanx_left_in[0]:24 chanx_left_in[0]:11 0.002158866 +3 chanx_left_in[0]:23 chanx_left_in[0]:22 0.002447917 +4 chanx_left_in[0]:21 chanx_left_in[0]:20 0.001723333 +5 chanx_left_in[0]:22 chanx_left_in[0]:21 0.00341 +6 chanx_left_in[0]:20 chanx_left_in[0]:19 0.00341 +7 chanx_left_in[0]:19 chanx_left_in[0]:18 0.002341383 +8 chanx_left_in[0]:17 chanx_left_in[0]:16 0.0007163583 +9 chanx_left_in[0]:18 chanx_left_in[0]:17 0.00341 +10 chanx_left_in[0]:15 chanx_left_in[0]:14 0.006283483 +11 chanx_left_in[0]:16 chanx_left_in[0]:15 0.00341 +12 chanx_left_in[0]:13 chanx_left_in[0]:12 0.0008995536 +13 chanx_left_in[0]:14 chanx_left_in[0]:13 0.0045 +14 chanx_left_in[0]:12 mux_bottom_track_33\/mux_l1_in_2_:A0 0.152 +15 chanx_left_in[0]:11 chanx_left_in[0]:10 0.00341 +16 chanx_left_in[0]:10 chanx_left_in[0]:9 0.002660983 +17 chanx_left_in[0]:8 chanx_left_in[0]:7 0.007058224 +18 chanx_left_in[0]:9 chanx_left_in[0]:8 0.00341 +19 chanx_left_in[0]:6 chanx_left_in[0]:5 0.002640625 +20 chanx_left_in[0]:7 chanx_left_in[0]:6 0.00341 +21 chanx_left_in[0]:4 chanx_left_in[0]:3 0.003779018 +22 chanx_left_in[0]:5 chanx_left_in[0]:4 0.0045 +23 chanx_left_in[0]:3 mux_top_track_0\/mux_l1_in_4_:A0 0.152 +24 chanx_left_in[0]:25 chanx_left_in[0]:24 0.001369267 + +*END + +*D_NET chany_top_out[1] 0.001491829 //LENGTH 11.530 LUMPCC 0.0002783499 DR + +*CONN +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 63.940 121.040 +*P chany_top_out[1] O *L 0.7423 *C 61.180 129.235 +*N chany_top_out[1]:2 *C 61.180 121.425 +*N chany_top_out[1]:3 *C 61.225 121.380 +*N chany_top_out[1]:4 *C 63.940 121.380 +*N chany_top_out[1]:5 *C 63.940 121.040 + +*CAP +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[1] 0.0003935351 +2 chany_top_out[1]:2 0.0003935351 +3 chany_top_out[1]:3 0.0001695723 +4 chany_top_out[1]:4 0.0001980297 +5 chany_top_out[1]:5 5.780731e-05 +6 chany_top_out[1] ropt_net_154:8 8.068935e-05 +7 chany_top_out[1]:2 ropt_net_154:9 8.068935e-05 +8 chany_top_out[1]:3 ropt_net_210:6 5.848561e-05 +9 chany_top_out[1]:4 ropt_net_210:7 5.848561e-05 + +*RES +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[1]:5 0.152 +1 chany_top_out[1]:3 chany_top_out[1]:2 0.0045 +2 chany_top_out[1]:2 chany_top_out[1] 0.006973214 +3 chany_top_out[1]:5 chany_top_out[1]:4 0.0003035715 +4 chany_top_out[1]:4 chany_top_out[1]:3 0.002424107 + +*END + +*D_NET ropt_net_154 0.002753248 //LENGTH 17.085 LUMPCC 0.0009534933 DR + +*CONN +*I mux_top_track_16\/BUFT_RR_80:X O *L 0 *C 61.640 121.720 +*I ropt_mt_inst_792:A I *L 0.001766 *C 69.920 121.040 +*N ropt_net_154:2 *C 69.883 121.040 +*N ropt_net_154:3 *C 68.585 121.040 +*N ropt_net_154:4 *C 68.540 121.085 +*N ropt_net_154:5 *C 68.540 125.062 +*N ropt_net_154:6 *C 68.532 125.120 +*N ropt_net_154:7 *C 61.648 125.120 +*N ropt_net_154:8 *C 61.640 125.062 +*N ropt_net_154:9 *C 61.640 121.765 +*N ropt_net_154:10 *C 61.640 121.720 + +*CAP +0 mux_top_track_16\/BUFT_RR_80:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_154:2 0.0001045 +3 ropt_net_154:3 0.0001045 +4 ropt_net_154:4 0.0002831777 +5 ropt_net_154:5 0.0002831777 +6 ropt_net_154:6 0.0003032238 +7 ropt_net_154:7 0.0003032238 +8 ropt_net_154:8 0.000189944 +9 ropt_net_154:9 0.000189944 +10 ropt_net_154:10 3.606339e-05 +11 ropt_net_154:6 chany_bottom_in[17]:9 0.0003960573 +12 ropt_net_154:7 chany_bottom_in[17]:10 0.0003960573 +13 ropt_net_154:8 chany_top_out[1] 8.068935e-05 +14 ropt_net_154:9 chany_top_out[1]:2 8.068935e-05 + +*RES +0 mux_top_track_16\/BUFT_RR_80:X ropt_net_154:10 0.152 +1 ropt_net_154:2 ropt_mt_inst_792:A 0.152 +2 ropt_net_154:3 ropt_net_154:2 0.001158482 +3 ropt_net_154:4 ropt_net_154:3 0.0045 +4 ropt_net_154:5 ropt_net_154:4 0.003551339 +5 ropt_net_154:6 ropt_net_154:5 0.00341 +6 ropt_net_154:8 ropt_net_154:7 0.00341 +7 ropt_net_154:7 ropt_net_154:6 0.00107865 +8 ropt_net_154:10 ropt_net_154:9 0.0045 +9 ropt_net_154:9 ropt_net_154:8 0.002944197 + +*END + +*D_NET chany_bottom_out[1] 0.00155538 //LENGTH 10.140 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 63.080 6.460 +*P chany_bottom_out[1] O *L 0.7423 *C 59.800 1.325 +*N chany_bottom_out[1]:2 *C 59.800 4.703 +*N chany_bottom_out[1]:3 *C 59.808 4.760 +*N chany_bottom_out[1]:4 *C 63.013 4.760 +*N chany_bottom_out[1]:5 *C 63.020 4.817 +*N chany_bottom_out[1]:6 *C 63.020 6.755 +*N chany_bottom_out[1]:7 *C 63.020 6.800 +*N chany_bottom_out[1]:8 *C 63.080 6.460 + +*CAP +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[1] 0.0002132717 +2 chany_bottom_out[1]:2 0.0002132717 +3 chany_bottom_out[1]:3 0.0003436892 +4 chany_bottom_out[1]:4 0.0003436892 +5 chany_bottom_out[1]:5 0.0001518257 +6 chany_bottom_out[1]:6 0.0001518257 +7 chany_bottom_out[1]:7 7.070326e-05 +8 chany_bottom_out[1]:8 6.610375e-05 + +*RES +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0001734694 +2 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +3 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.001729911 +4 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.00341 +5 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.0005021166 +6 chany_bottom_out[1]:2 chany_bottom_out[1] 0.003015625 +7 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.00341 + +*END + +*D_NET chanx_left_out[16] 0.002350539 //LENGTH 18.715 LUMPCC 0.0007140821 DR + +*CONN +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.440 44.540 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 31.960 +*N chanx_left_out[16]:2 *C 4.593 31.960 +*N chanx_left_out[16]:3 *C 4.600 32.017 +*N chanx_left_out[16]:4 *C 4.600 44.155 +*N chanx_left_out[16]:5 *C 4.645 44.200 +*N chanx_left_out[16]:6 *C 6.440 44.200 +*N chanx_left_out[16]:7 *C 6.440 44.540 + +*CAP +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[16] 0.0001583994 +2 chanx_left_out[16]:2 0.0001583994 +3 chanx_left_out[16]:3 0.0004765005 +4 chanx_left_out[16]:4 0.0004765005 +5 chanx_left_out[16]:5 0.0001404651 +6 chanx_left_out[16]:6 0.0001683951 +7 chanx_left_out[16]:7 5.679741e-05 +8 chanx_left_out[16] prog_clk[0]:709 3.452184e-05 +9 chanx_left_out[16]:4 prog_clk[0]:679 0.0001929882 +10 chanx_left_out[16]:4 prog_clk[0]:706 0.0001295309 +11 chanx_left_out[16]:3 prog_clk[0]:706 0.0001929882 +12 chanx_left_out[16]:3 prog_clk[0]:707 0.0001295309 +13 chanx_left_out[16]:2 prog_clk[0]:708 3.452184e-05 + +*RES +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[16]:7 0.152 +1 chanx_left_out[16]:7 chanx_left_out[16]:6 0.0003035715 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.01083705 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 0.0005267916 +6 chanx_left_out[16]:6 chanx_left_out[16]:5 0.001602679 + +*END + +*D_NET mux_tree_tapbuf_size10_10_sram[1] 0.009053471 //LENGTH 62.330 LUMPCC 0.002175672 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 47.225 63.920 +*I mux_left_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 58.520 53.040 +*I mux_left_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 64.500 55.760 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 31.915 64.260 +*I mux_left_track_17\/mux_l2_in_3_:S I *L 0.00357 *C 27.500 66.640 +*I mux_left_track_17\/mux_l2_in_2_:S I *L 0.00357 *C 27.700 68.680 +*N mux_tree_tapbuf_size10_10_sram[1]:6 *C 27.600 68.680 +*N mux_tree_tapbuf_size10_10_sram[1]:7 *C 27.600 68.635 +*N mux_tree_tapbuf_size10_10_sram[1]:8 *C 27.500 66.640 +*N mux_tree_tapbuf_size10_10_sram[1]:9 *C 27.600 66.640 +*N mux_tree_tapbuf_size10_10_sram[1]:10 *C 27.600 64.645 +*N mux_tree_tapbuf_size10_10_sram[1]:11 *C 27.645 64.600 +*N mux_tree_tapbuf_size10_10_sram[1]:12 *C 32.200 64.600 +*N mux_tree_tapbuf_size10_10_sram[1]:13 *C 31.943 64.282 +*N mux_tree_tapbuf_size10_10_sram[1]:14 *C 32.200 64.260 +*N mux_tree_tapbuf_size10_10_sram[1]:15 *C 40.895 64.260 +*N mux_tree_tapbuf_size10_10_sram[1]:16 *C 40.940 64.305 +*N mux_tree_tapbuf_size10_10_sram[1]:17 *C 40.940 65.222 +*N mux_tree_tapbuf_size10_10_sram[1]:18 *C 40.948 65.280 +*N mux_tree_tapbuf_size10_10_sram[1]:19 *C 46.453 65.280 +*N mux_tree_tapbuf_size10_10_sram[1]:20 *C 46.460 65.222 +*N mux_tree_tapbuf_size10_10_sram[1]:21 *C 64.463 55.760 +*N mux_tree_tapbuf_size10_10_sram[1]:22 *C 60.720 55.760 +*N mux_tree_tapbuf_size10_10_sram[1]:23 *C 58.558 53.040 +*N mux_tree_tapbuf_size10_10_sram[1]:24 *C 60.675 53.040 +*N mux_tree_tapbuf_size10_10_sram[1]:25 *C 60.720 53.085 +*N mux_tree_tapbuf_size10_10_sram[1]:26 *C 60.720 55.035 +*N mux_tree_tapbuf_size10_10_sram[1]:27 *C 60.720 55.110 +*N mux_tree_tapbuf_size10_10_sram[1]:28 *C 46.505 55.080 +*N mux_tree_tapbuf_size10_10_sram[1]:29 *C 46.460 55.125 +*N mux_tree_tapbuf_size10_10_sram[1]:30 *C 46.460 63.920 +*N mux_tree_tapbuf_size10_10_sram[1]:31 *C 46.505 63.920 +*N mux_tree_tapbuf_size10_10_sram[1]:32 *C 47.188 63.920 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_17\/mux_l2_in_1_:S 1e-06 +2 mux_left_track_17\/mux_l2_in_0_:S 1e-06 +3 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_left_track_17\/mux_l2_in_3_:S 1e-06 +5 mux_left_track_17\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size10_10_sram[1]:6 3.474289e-05 +7 mux_tree_tapbuf_size10_10_sram[1]:7 0.00010902 +8 mux_tree_tapbuf_size10_10_sram[1]:8 2.981234e-05 +9 mux_tree_tapbuf_size10_10_sram[1]:9 0.0002566875 +10 mux_tree_tapbuf_size10_10_sram[1]:10 0.0001175241 +11 mux_tree_tapbuf_size10_10_sram[1]:11 0.0003322399 +12 mux_tree_tapbuf_size10_10_sram[1]:12 0.0003571677 +13 mux_tree_tapbuf_size10_10_sram[1]:13 1.425412e-05 +14 mux_tree_tapbuf_size10_10_sram[1]:14 0.0006850055 +15 mux_tree_tapbuf_size10_10_sram[1]:15 0.0006458235 +16 mux_tree_tapbuf_size10_10_sram[1]:16 8.457663e-05 +17 mux_tree_tapbuf_size10_10_sram[1]:17 8.457663e-05 +18 mux_tree_tapbuf_size10_10_sram[1]:18 0.0002804381 +19 mux_tree_tapbuf_size10_10_sram[1]:19 0.0002804381 +20 mux_tree_tapbuf_size10_10_sram[1]:20 7.24666e-05 +21 mux_tree_tapbuf_size10_10_sram[1]:21 0.0001795194 +22 mux_tree_tapbuf_size10_10_sram[1]:22 0.0002138208 +23 mux_tree_tapbuf_size10_10_sram[1]:23 0.0001260981 +24 mux_tree_tapbuf_size10_10_sram[1]:24 0.0001260981 +25 mux_tree_tapbuf_size10_10_sram[1]:25 0.0001435541 +26 mux_tree_tapbuf_size10_10_sram[1]:26 0.0001435541 +27 mux_tree_tapbuf_size10_10_sram[1]:27 0.000691038 +28 mux_tree_tapbuf_size10_10_sram[1]:28 0.0006567367 +29 mux_tree_tapbuf_size10_10_sram[1]:29 0.0004897155 +30 mux_tree_tapbuf_size10_10_sram[1]:30 0.0005934784 +31 mux_tree_tapbuf_size10_10_sram[1]:31 6.170529e-05 +32 mux_tree_tapbuf_size10_10_sram[1]:32 6.170529e-05 +33 mux_tree_tapbuf_size10_10_sram[1]:29 chany_bottom_in[18]:39 5.035849e-06 +34 mux_tree_tapbuf_size10_10_sram[1]:18 chany_bottom_in[18]:36 0.0003172248 +35 mux_tree_tapbuf_size10_10_sram[1]:20 chany_bottom_in[18]:31 3.221747e-06 +36 mux_tree_tapbuf_size10_10_sram[1]:20 chany_bottom_in[18]:38 2.532703e-06 +37 mux_tree_tapbuf_size10_10_sram[1]:19 chany_bottom_in[18]:37 0.0003172248 +38 mux_tree_tapbuf_size10_10_sram[1]:30 chany_bottom_in[18]:38 8.257595e-06 +39 mux_tree_tapbuf_size10_10_sram[1]:30 chany_bottom_in[18]:39 2.532703e-06 +40 mux_tree_tapbuf_size10_10_sram[1]:24 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.770038e-05 +41 mux_tree_tapbuf_size10_10_sram[1]:23 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.770038e-05 +42 mux_tree_tapbuf_size10_10_sram[1]:27 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 2.130753e-06 +43 mux_tree_tapbuf_size10_10_sram[1]:27 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0005272213 +44 mux_tree_tapbuf_size10_10_sram[1]:28 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005142312 +45 mux_tree_tapbuf_size10_10_sram[1]:28 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 2.130753e-06 +46 mux_tree_tapbuf_size10_10_sram[1]:21 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001167764 +47 mux_tree_tapbuf_size10_10_sram[1]:22 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001297665 +48 mux_tree_tapbuf_size10_10_sram[1]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.79968e-05 +49 mux_tree_tapbuf_size10_10_sram[1]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.777227e-05 +50 mux_tree_tapbuf_size10_10_sram[1]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 2.022342e-05 +51 mux_tree_tapbuf_size10_10_sram[1]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 1.777227e-05 +52 mux_tree_tapbuf_size10_10_sram[1]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 2.022342e-05 +53 mux_tree_tapbuf_size10_10_sram[1]:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.79968e-05 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_10_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_10_sram[1]:13 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size10_10_sram[1]:11 mux_tree_tapbuf_size10_10_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size10_10_sram[1]:10 mux_tree_tapbuf_size10_10_sram[1]:9 0.00178125 +4 mux_tree_tapbuf_size10_10_sram[1]:27 mux_tree_tapbuf_size10_10_sram[1]:26 0.0045 +5 mux_tree_tapbuf_size10_10_sram[1]:27 mux_tree_tapbuf_size10_10_sram[1]:22 0.0005803572 +6 mux_tree_tapbuf_size10_10_sram[1]:26 mux_tree_tapbuf_size10_10_sram[1]:25 0.001741071 +7 mux_tree_tapbuf_size10_10_sram[1]:24 mux_tree_tapbuf_size10_10_sram[1]:23 0.001890625 +8 mux_tree_tapbuf_size10_10_sram[1]:25 mux_tree_tapbuf_size10_10_sram[1]:24 0.0045 +9 mux_tree_tapbuf_size10_10_sram[1]:23 mux_left_track_17\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size10_10_sram[1]:28 mux_tree_tapbuf_size10_10_sram[1]:27 0.01269196 +11 mux_tree_tapbuf_size10_10_sram[1]:29 mux_tree_tapbuf_size10_10_sram[1]:28 0.0045 +12 mux_tree_tapbuf_size10_10_sram[1]:15 mux_tree_tapbuf_size10_10_sram[1]:14 0.007763393 +13 mux_tree_tapbuf_size10_10_sram[1]:16 mux_tree_tapbuf_size10_10_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size10_10_sram[1]:17 mux_tree_tapbuf_size10_10_sram[1]:16 0.0008191965 +15 mux_tree_tapbuf_size10_10_sram[1]:18 mux_tree_tapbuf_size10_10_sram[1]:17 0.00341 +16 mux_tree_tapbuf_size10_10_sram[1]:20 mux_tree_tapbuf_size10_10_sram[1]:19 0.00341 +17 mux_tree_tapbuf_size10_10_sram[1]:19 mux_tree_tapbuf_size10_10_sram[1]:18 0.0008624499 +18 mux_tree_tapbuf_size10_10_sram[1]:21 mux_left_track_17\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size10_10_sram[1]:31 mux_tree_tapbuf_size10_10_sram[1]:30 0.0045 +20 mux_tree_tapbuf_size10_10_sram[1]:30 mux_tree_tapbuf_size10_10_sram[1]:29 0.007852679 +21 mux_tree_tapbuf_size10_10_sram[1]:30 mux_tree_tapbuf_size10_10_sram[1]:20 0.001162947 +22 mux_tree_tapbuf_size10_10_sram[1]:32 mux_tree_tapbuf_size10_10_sram[1]:31 0.000609375 +23 mux_tree_tapbuf_size10_10_sram[1]:8 mux_left_track_17\/mux_l2_in_3_:S 0.152 +24 mux_tree_tapbuf_size10_10_sram[1]:9 mux_tree_tapbuf_size10_10_sram[1]:8 0.0045 +25 mux_tree_tapbuf_size10_10_sram[1]:9 mux_tree_tapbuf_size10_10_sram[1]:7 0.00178125 +26 mux_tree_tapbuf_size10_10_sram[1]:6 mux_left_track_17\/mux_l2_in_2_:S 0.152 +27 mux_tree_tapbuf_size10_10_sram[1]:7 mux_tree_tapbuf_size10_10_sram[1]:6 0.0045 +28 mux_tree_tapbuf_size10_10_sram[1]:12 mux_tree_tapbuf_size10_10_sram[1]:11 0.004066964 +29 mux_tree_tapbuf_size10_10_sram[1]:14 mux_tree_tapbuf_size10_10_sram[1]:13 0.0001739865 +30 mux_tree_tapbuf_size10_10_sram[1]:14 mux_tree_tapbuf_size10_10_sram[1]:12 0.0003035715 +31 mux_tree_tapbuf_size10_10_sram[1]:22 mux_tree_tapbuf_size10_10_sram[1]:21 0.003341518 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[3] 0.001891389 //LENGTH 15.365 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 90.005 39.440 +*I mux_right_track_16\/mux_l4_in_0_:S I *L 0.00357 *C 98.340 44.880 +*I mem_right_track_16\/FTB_17__68:A I *L 0.001746 *C 98.440 39.440 +*N mux_tree_tapbuf_size10_4_sram[3]:3 *C 98.440 39.440 +*N mux_tree_tapbuf_size10_4_sram[3]:4 *C 98.340 44.880 +*N mux_tree_tapbuf_size10_4_sram[3]:5 *C 98.440 44.835 +*N mux_tree_tapbuf_size10_4_sram[3]:6 *C 98.440 39.825 +*N mux_tree_tapbuf_size10_4_sram[3]:7 *C 98.440 39.780 +*N mux_tree_tapbuf_size10_4_sram[3]:8 *C 92.000 39.780 +*N mux_tree_tapbuf_size10_4_sram[3]:9 *C 92.000 39.440 +*N mux_tree_tapbuf_size10_4_sram[3]:10 *C 90.043 39.440 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_right_track_16\/mux_l4_in_0_:S 1e-06 +2 mem_right_track_16\/FTB_17__68:A 1e-06 +3 mux_tree_tapbuf_size10_4_sram[3]:3 6.210554e-05 +4 mux_tree_tapbuf_size10_4_sram[3]:4 2.820984e-05 +5 mux_tree_tapbuf_size10_4_sram[3]:5 0.0002885791 +6 mux_tree_tapbuf_size10_4_sram[3]:6 0.0002885791 +7 mux_tree_tapbuf_size10_4_sram[3]:7 0.0004489827 +8 mux_tree_tapbuf_size10_4_sram[3]:8 0.000439436 +9 mux_tree_tapbuf_size10_4_sram[3]:9 0.0001788587 +10 mux_tree_tapbuf_size10_4_sram[3]:10 0.0001536382 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_4_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_4_sram[3]:7 mux_tree_tapbuf_size10_4_sram[3]:6 0.0045 +2 mux_tree_tapbuf_size10_4_sram[3]:7 mux_tree_tapbuf_size10_4_sram[3]:3 0.0001465517 +3 mux_tree_tapbuf_size10_4_sram[3]:6 mux_tree_tapbuf_size10_4_sram[3]:5 0.004473215 +4 mux_tree_tapbuf_size10_4_sram[3]:4 mux_right_track_16\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_4_sram[3]:5 mux_tree_tapbuf_size10_4_sram[3]:4 0.0045 +6 mux_tree_tapbuf_size10_4_sram[3]:10 mux_tree_tapbuf_size10_4_sram[3]:9 0.001747768 +7 mux_tree_tapbuf_size10_4_sram[3]:3 mem_right_track_16\/FTB_17__68:A 0.152 +8 mux_tree_tapbuf_size10_4_sram[3]:9 mux_tree_tapbuf_size10_4_sram[3]:8 0.0003035715 +9 mux_tree_tapbuf_size10_4_sram[3]:8 mux_tree_tapbuf_size10_4_sram[3]:7 0.00575 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[2] 0.001561282 //LENGTH 13.120 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 98.285 20.740 +*I mux_bottom_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 99.720 23.120 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 100.915 26.180 +*I mux_bottom_track_9\/mux_l3_in_1_:S I *L 0.00357 *C 100.180 28.900 +*N mux_tree_tapbuf_size10_6_sram[2]:4 *C 100.218 28.900 +*N mux_tree_tapbuf_size10_6_sram[2]:5 *C 100.695 28.900 +*N mux_tree_tapbuf_size10_6_sram[2]:6 *C 100.740 28.855 +*N mux_tree_tapbuf_size10_6_sram[2]:7 *C 100.915 26.180 +*N mux_tree_tapbuf_size10_6_sram[2]:8 *C 100.740 26.180 +*N mux_tree_tapbuf_size10_6_sram[2]:9 *C 100.740 26.180 +*N mux_tree_tapbuf_size10_6_sram[2]:10 *C 100.740 23.165 +*N mux_tree_tapbuf_size10_6_sram[2]:11 *C 100.695 23.120 +*N mux_tree_tapbuf_size10_6_sram[2]:12 *C 99.865 23.120 +*N mux_tree_tapbuf_size10_6_sram[2]:13 *C 99.820 23.075 +*N mux_tree_tapbuf_size10_6_sram[2]:14 *C 99.820 20.785 +*N mux_tree_tapbuf_size10_6_sram[2]:15 *C 99.775 20.740 +*N mux_tree_tapbuf_size10_6_sram[2]:16 *C 98.323 20.740 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_bottom_track_9\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_6_sram[2]:4 5.777009e-05 +5 mux_tree_tapbuf_size10_6_sram[2]:5 5.777009e-05 +6 mux_tree_tapbuf_size10_6_sram[2]:6 0.0001636976 +7 mux_tree_tapbuf_size10_6_sram[2]:7 4.912771e-05 +8 mux_tree_tapbuf_size10_6_sram[2]:8 5.107431e-05 +9 mux_tree_tapbuf_size10_6_sram[2]:9 0.0003530298 +10 mux_tree_tapbuf_size10_6_sram[2]:10 0.0001613946 +11 mux_tree_tapbuf_size10_6_sram[2]:11 7.886203e-05 +12 mux_tree_tapbuf_size10_6_sram[2]:12 7.886203e-05 +13 mux_tree_tapbuf_size10_6_sram[2]:13 0.000134053 +14 mux_tree_tapbuf_size10_6_sram[2]:14 0.000134053 +15 mux_tree_tapbuf_size10_6_sram[2]:15 0.0001187939 +16 mux_tree_tapbuf_size10_6_sram[2]:16 0.0001187939 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_6_sram[2]:16 0.152 +1 mux_tree_tapbuf_size10_6_sram[2]:4 mux_bottom_track_9\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_6_sram[2]:5 mux_tree_tapbuf_size10_6_sram[2]:4 0.0004263393 +3 mux_tree_tapbuf_size10_6_sram[2]:6 mux_tree_tapbuf_size10_6_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size10_6_sram[2]:8 mux_tree_tapbuf_size10_6_sram[2]:7 9.51087e-05 +5 mux_tree_tapbuf_size10_6_sram[2]:9 mux_tree_tapbuf_size10_6_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size10_6_sram[2]:9 mux_tree_tapbuf_size10_6_sram[2]:6 0.002388393 +7 mux_tree_tapbuf_size10_6_sram[2]:7 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_6_sram[2]:12 mux_bottom_track_9\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size10_6_sram[2]:12 mux_tree_tapbuf_size10_6_sram[2]:11 0.0007410714 +10 mux_tree_tapbuf_size10_6_sram[2]:13 mux_tree_tapbuf_size10_6_sram[2]:12 0.0045 +11 mux_tree_tapbuf_size10_6_sram[2]:15 mux_tree_tapbuf_size10_6_sram[2]:14 0.0045 +12 mux_tree_tapbuf_size10_6_sram[2]:14 mux_tree_tapbuf_size10_6_sram[2]:13 0.002044643 +13 mux_tree_tapbuf_size10_6_sram[2]:16 mux_tree_tapbuf_size10_6_sram[2]:15 0.001296875 +14 mux_tree_tapbuf_size10_6_sram[2]:11 mux_tree_tapbuf_size10_6_sram[2]:10 0.0045 +15 mux_tree_tapbuf_size10_6_sram[2]:10 mux_tree_tapbuf_size10_6_sram[2]:9 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size10_9_sram[0] 0.01275377 //LENGTH 74.485 LUMPCC 0.003741692 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 18.645 76.840 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 27.315 71.740 +*I mux_left_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 70.020 69.360 +*I mux_left_track_9\/mux_l1_in_2_:S I *L 0.00357 *C 65.880 72.080 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 72.780 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:5 *C 72.743 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:6 *C 65.918 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:7 *C 68.080 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:8 *C 68.080 72.035 +*N mux_tree_tapbuf_size10_9_sram[0]:9 *C 69.983 69.360 +*N mux_tree_tapbuf_size10_9_sram[0]:10 *C 68.125 69.360 +*N mux_tree_tapbuf_size10_9_sram[0]:11 *C 68.080 69.405 +*N mux_tree_tapbuf_size10_9_sram[0]:12 *C 68.080 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:13 *C 68.073 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:14 *C 47.380 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:15 *C 47.380 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:16 *C 42.780 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:17 *C 42.780 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:18 *C 39.560 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:19 *C 39.560 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:20 *C 35.420 72.080 +*N mux_tree_tapbuf_size10_9_sram[0]:21 *C 35.420 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:22 *C 27.608 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:23 *C 27.600 71.400 +*N mux_tree_tapbuf_size10_9_sram[0]:24 *C 27.600 71.740 +*N mux_tree_tapbuf_size10_9_sram[0]:25 *C 27.600 71.740 +*N mux_tree_tapbuf_size10_9_sram[0]:26 *C 27.315 71.740 +*N mux_tree_tapbuf_size10_9_sram[0]:27 *C 27.140 71.740 +*N mux_tree_tapbuf_size10_9_sram[0]:28 *C 27.140 71.785 +*N mux_tree_tapbuf_size10_9_sram[0]:29 *C 27.140 77.135 +*N mux_tree_tapbuf_size10_9_sram[0]:30 *C 27.095 77.180 +*N mux_tree_tapbuf_size10_9_sram[0]:31 *C 25.760 77.180 +*N mux_tree_tapbuf_size10_9_sram[0]:32 *C 25.760 76.840 +*N mux_tree_tapbuf_size10_9_sram[0]:33 *C 18.683 76.840 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_9\/mux_l1_in_1_:S 1e-06 +3 mux_left_track_9\/mux_l1_in_2_:S 1e-06 +4 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_9_sram[0]:5 0.0003449711 +6 mux_tree_tapbuf_size10_9_sram[0]:6 0.0001330192 +7 mux_tree_tapbuf_size10_9_sram[0]:7 0.0005125846 +8 mux_tree_tapbuf_size10_9_sram[0]:8 4.84827e-05 +9 mux_tree_tapbuf_size10_9_sram[0]:9 0.0001496955 +10 mux_tree_tapbuf_size10_9_sram[0]:10 0.0001496955 +11 mux_tree_tapbuf_size10_9_sram[0]:11 0.0001296273 +12 mux_tree_tapbuf_size10_9_sram[0]:12 0.0002168612 +13 mux_tree_tapbuf_size10_9_sram[0]:13 0.001370692 +14 mux_tree_tapbuf_size10_9_sram[0]:14 0.001428987 +15 mux_tree_tapbuf_size10_9_sram[0]:15 0.0003276113 +16 mux_tree_tapbuf_size10_9_sram[0]:16 0.0003194483 +17 mux_tree_tapbuf_size10_9_sram[0]:17 0.0002112253 +18 mux_tree_tapbuf_size10_9_sram[0]:18 0.0002124753 +19 mux_tree_tapbuf_size10_9_sram[0]:19 0.0003202075 +20 mux_tree_tapbuf_size10_9_sram[0]:20 0.0003270341 +21 mux_tree_tapbuf_size10_9_sram[0]:21 0.0003012996 +22 mux_tree_tapbuf_size10_9_sram[0]:22 0.0002430907 +23 mux_tree_tapbuf_size10_9_sram[0]:23 6.473603e-05 +24 mux_tree_tapbuf_size10_9_sram[0]:24 5.83897e-05 +25 mux_tree_tapbuf_size10_9_sram[0]:25 5.819566e-05 +26 mux_tree_tapbuf_size10_9_sram[0]:26 7.709902e-05 +27 mux_tree_tapbuf_size10_9_sram[0]:27 5.503714e-05 +28 mux_tree_tapbuf_size10_9_sram[0]:28 0.0003116241 +29 mux_tree_tapbuf_size10_9_sram[0]:29 0.0003116241 +30 mux_tree_tapbuf_size10_9_sram[0]:30 0.0001330811 +31 mux_tree_tapbuf_size10_9_sram[0]:31 0.0001581757 +32 mux_tree_tapbuf_size10_9_sram[0]:32 0.0005286006 +33 mux_tree_tapbuf_size10_9_sram[0]:33 0.000503506 +34 mux_tree_tapbuf_size10_9_sram[0]:22 chanx_right_in[16]:19 0.0001576352 +35 mux_tree_tapbuf_size10_9_sram[0]:7 chanx_right_in[16]:8 3.688475e-05 +36 mux_tree_tapbuf_size10_9_sram[0]:7 chanx_right_in[16]:10 1.128274e-06 +37 mux_tree_tapbuf_size10_9_sram[0]:6 chanx_right_in[16]:9 3.688475e-05 +38 mux_tree_tapbuf_size10_9_sram[0]:6 chanx_right_in[16]:28 1.128274e-06 +39 mux_tree_tapbuf_size10_9_sram[0]:21 chanx_right_in[16]:20 0.0001576352 +40 mux_tree_tapbuf_size10_9_sram[0]:20 chanx_right_in[16]:19 4.153689e-05 +41 mux_tree_tapbuf_size10_9_sram[0]:19 chanx_right_in[16]:20 4.153689e-05 +42 mux_tree_tapbuf_size10_9_sram[0]:19 chanx_right_in[16]:26 6.316046e-06 +43 mux_tree_tapbuf_size10_9_sram[0]:18 chanx_right_in[16]:25 6.316046e-06 +44 mux_tree_tapbuf_size10_9_sram[0]:17 chanx_right_in[16]:25 5.473907e-06 +45 mux_tree_tapbuf_size10_9_sram[0]:16 chanx_right_in[16]:26 5.473907e-06 +46 mux_tree_tapbuf_size10_9_sram[0]:15 chanx_right_in[16]:29 5.158616e-06 +47 mux_tree_tapbuf_size10_9_sram[0]:14 chanx_right_in[16]:30 5.158616e-06 +48 mux_tree_tapbuf_size10_9_sram[0]:13 chanx_right_in[7]:18 0.0003449331 +49 mux_tree_tapbuf_size10_9_sram[0]:20 chanx_right_in[7]:17 6.68483e-05 +50 mux_tree_tapbuf_size10_9_sram[0]:19 chanx_right_in[7]:18 6.68483e-05 +51 mux_tree_tapbuf_size10_9_sram[0]:18 chanx_right_in[7]:17 3.236349e-05 +52 mux_tree_tapbuf_size10_9_sram[0]:17 chanx_right_in[7]:18 3.236349e-05 +53 mux_tree_tapbuf_size10_9_sram[0]:16 chanx_right_in[7]:17 0.000263874 +54 mux_tree_tapbuf_size10_9_sram[0]:15 chanx_right_in[7]:18 0.000263874 +55 mux_tree_tapbuf_size10_9_sram[0]:14 chanx_right_in[7]:17 0.0003449331 +56 mux_tree_tapbuf_size10_9_sram[0]:22 mux_tree_tapbuf_size12_6_sram[0]:46 0.0004406029 +57 mux_tree_tapbuf_size10_9_sram[0]:13 mux_tree_tapbuf_size12_6_sram[0]:45 0.0001627282 +58 mux_tree_tapbuf_size10_9_sram[0]:33 mux_tree_tapbuf_size12_6_sram[0]:15 1.171607e-06 +59 mux_tree_tapbuf_size10_9_sram[0]:33 mux_tree_tapbuf_size12_6_sram[0]:14 5.817784e-07 +60 mux_tree_tapbuf_size10_9_sram[0]:32 mux_tree_tapbuf_size12_6_sram[0]:13 5.817784e-07 +61 mux_tree_tapbuf_size10_9_sram[0]:32 mux_tree_tapbuf_size12_6_sram[0]:14 1.171607e-06 +62 mux_tree_tapbuf_size10_9_sram[0]:21 mux_tree_tapbuf_size12_6_sram[0]:45 0.0004406029 +63 mux_tree_tapbuf_size10_9_sram[0]:20 mux_tree_tapbuf_size12_6_sram[0]:46 6.413181e-05 +64 mux_tree_tapbuf_size10_9_sram[0]:19 mux_tree_tapbuf_size12_6_sram[0]:45 6.413181e-05 +65 mux_tree_tapbuf_size10_9_sram[0]:18 mux_tree_tapbuf_size12_6_sram[0]:46 0.0001915778 +66 mux_tree_tapbuf_size10_9_sram[0]:17 mux_tree_tapbuf_size12_6_sram[0]:45 0.0001915778 +67 mux_tree_tapbuf_size10_9_sram[0]:16 mux_tree_tapbuf_size12_6_sram[0]:46 4.789946e-05 +68 mux_tree_tapbuf_size10_9_sram[0]:15 mux_tree_tapbuf_size12_6_sram[0]:45 4.789946e-05 +69 mux_tree_tapbuf_size10_9_sram[0]:14 mux_tree_tapbuf_size12_6_sram[0]:46 0.0001627282 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_9_sram[0]:33 0.152 +1 mux_tree_tapbuf_size10_9_sram[0]:25 mux_tree_tapbuf_size10_9_sram[0]:24 0.0045 +2 mux_tree_tapbuf_size10_9_sram[0]:24 mux_tree_tapbuf_size10_9_sram[0]:23 0.0001634616 +3 mux_tree_tapbuf_size10_9_sram[0]:23 mux_tree_tapbuf_size10_9_sram[0]:22 0.00341 +4 mux_tree_tapbuf_size10_9_sram[0]:22 mux_tree_tapbuf_size10_9_sram[0]:21 0.001223958 +5 mux_tree_tapbuf_size10_9_sram[0]:12 mux_tree_tapbuf_size10_9_sram[0]:11 0.00178125 +6 mux_tree_tapbuf_size10_9_sram[0]:12 mux_tree_tapbuf_size10_9_sram[0]:8 0.0005669643 +7 mux_tree_tapbuf_size10_9_sram[0]:13 mux_tree_tapbuf_size10_9_sram[0]:12 0.00341 +8 mux_tree_tapbuf_size10_9_sram[0]:33 mux_tree_tapbuf_size10_9_sram[0]:32 0.006319197 +9 mux_tree_tapbuf_size10_9_sram[0]:30 mux_tree_tapbuf_size10_9_sram[0]:29 0.0045 +10 mux_tree_tapbuf_size10_9_sram[0]:29 mux_tree_tapbuf_size10_9_sram[0]:28 0.004776786 +11 mux_tree_tapbuf_size10_9_sram[0]:27 mux_tree_tapbuf_size10_9_sram[0]:26 9.51087e-05 +12 mux_tree_tapbuf_size10_9_sram[0]:28 mux_tree_tapbuf_size10_9_sram[0]:27 0.0045 +13 mux_tree_tapbuf_size10_9_sram[0]:7 mux_tree_tapbuf_size10_9_sram[0]:6 0.001930804 +14 mux_tree_tapbuf_size10_9_sram[0]:7 mux_tree_tapbuf_size10_9_sram[0]:5 0.004162947 +15 mux_tree_tapbuf_size10_9_sram[0]:8 mux_tree_tapbuf_size10_9_sram[0]:7 0.0045 +16 mux_tree_tapbuf_size10_9_sram[0]:6 mux_left_track_9\/mux_l1_in_2_:S 0.152 +17 mux_tree_tapbuf_size10_9_sram[0]:10 mux_tree_tapbuf_size10_9_sram[0]:9 0.001658482 +18 mux_tree_tapbuf_size10_9_sram[0]:11 mux_tree_tapbuf_size10_9_sram[0]:10 0.0045 +19 mux_tree_tapbuf_size10_9_sram[0]:9 mux_left_track_9\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size10_9_sram[0]:5 mux_left_track_9\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size10_9_sram[0]:26 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size10_9_sram[0]:26 mux_tree_tapbuf_size10_9_sram[0]:25 0.0001548913 +23 mux_tree_tapbuf_size10_9_sram[0]:32 mux_tree_tapbuf_size10_9_sram[0]:31 0.0003035715 +24 mux_tree_tapbuf_size10_9_sram[0]:31 mux_tree_tapbuf_size10_9_sram[0]:30 0.001191964 +25 mux_tree_tapbuf_size10_9_sram[0]:21 mux_tree_tapbuf_size10_9_sram[0]:20 0.0001065333 +26 mux_tree_tapbuf_size10_9_sram[0]:20 mux_tree_tapbuf_size10_9_sram[0]:19 0.0006485999 +27 mux_tree_tapbuf_size10_9_sram[0]:19 mux_tree_tapbuf_size10_9_sram[0]:18 0.0001065333 +28 mux_tree_tapbuf_size10_9_sram[0]:18 mux_tree_tapbuf_size10_9_sram[0]:17 0.0005044666 +29 mux_tree_tapbuf_size10_9_sram[0]:17 mux_tree_tapbuf_size10_9_sram[0]:16 0.0001065333 +30 mux_tree_tapbuf_size10_9_sram[0]:16 mux_tree_tapbuf_size10_9_sram[0]:15 0.0007206666 +31 mux_tree_tapbuf_size10_9_sram[0]:15 mux_tree_tapbuf_size10_9_sram[0]:14 0.0001065333 +32 mux_tree_tapbuf_size10_9_sram[0]:14 mux_tree_tapbuf_size10_9_sram[0]:13 0.003241825 + +*END + +*D_NET mux_tree_tapbuf_size12_2_sram[1] 0.004510833 //LENGTH 35.315 LUMPCC 0.0007225167 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 97.365 115.260 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 95.395 113.220 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 93.280 106.760 +*I mux_right_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 95.560 105.400 +*I mux_right_track_0\/mux_l2_in_3_:S I *L 0.00357 *C 98.540 96.560 +*I mux_right_track_0\/mux_l2_in_2_:S I *L 0.00357 *C 98.340 91.120 +*N mux_tree_tapbuf_size12_2_sram[1]:6 *C 98.340 91.120 +*N mux_tree_tapbuf_size12_2_sram[1]:7 *C 98.440 91.165 +*N mux_tree_tapbuf_size12_2_sram[1]:8 *C 98.440 96.515 +*N mux_tree_tapbuf_size12_2_sram[1]:9 *C 98.453 96.560 +*N mux_tree_tapbuf_size12_2_sram[1]:10 *C 97.565 96.560 +*N mux_tree_tapbuf_size12_2_sram[1]:11 *C 97.520 96.605 +*N mux_tree_tapbuf_size12_2_sram[1]:12 *C 95.598 105.400 +*N mux_tree_tapbuf_size12_2_sram[1]:13 *C 97.425 105.400 +*N mux_tree_tapbuf_size12_2_sram[1]:14 *C 97.520 105.355 +*N mux_tree_tapbuf_size12_2_sram[1]:15 *C 97.060 105.400 +*N mux_tree_tapbuf_size12_2_sram[1]:16 *C 93.318 106.760 +*N mux_tree_tapbuf_size12_2_sram[1]:17 *C 97.015 106.760 +*N mux_tree_tapbuf_size12_2_sram[1]:18 *C 97.060 106.760 +*N mux_tree_tapbuf_size12_2_sram[1]:19 *C 95.433 113.220 +*N mux_tree_tapbuf_size12_2_sram[1]:20 *C 97.015 113.220 +*N mux_tree_tapbuf_size12_2_sram[1]:21 *C 97.060 113.220 +*N mux_tree_tapbuf_size12_2_sram[1]:22 *C 97.060 115.215 +*N mux_tree_tapbuf_size12_2_sram[1]:23 *C 97.060 115.260 +*N mux_tree_tapbuf_size12_2_sram[1]:24 *C 97.365 115.260 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_0\/mux_l2_in_1_:S 1e-06 +4 mux_right_track_0\/mux_l2_in_3_:S 1e-06 +5 mux_right_track_0\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size12_2_sram[1]:6 2.986525e-05 +7 mux_tree_tapbuf_size12_2_sram[1]:7 0.0002353408 +8 mux_tree_tapbuf_size12_2_sram[1]:8 0.0002353408 +9 mux_tree_tapbuf_size12_2_sram[1]:9 8.458351e-05 +10 mux_tree_tapbuf_size12_2_sram[1]:10 8.458351e-05 +11 mux_tree_tapbuf_size12_2_sram[1]:11 0.0004297425 +12 mux_tree_tapbuf_size12_2_sram[1]:12 0.0001264594 +13 mux_tree_tapbuf_size12_2_sram[1]:13 0.0001264594 +14 mux_tree_tapbuf_size12_2_sram[1]:14 0.0004650248 +15 mux_tree_tapbuf_size12_2_sram[1]:15 0.0001238404 +16 mux_tree_tapbuf_size12_2_sram[1]:16 0.0002099648 +17 mux_tree_tapbuf_size12_2_sram[1]:17 0.0002099648 +18 mux_tree_tapbuf_size12_2_sram[1]:18 0.0004748983 +19 mux_tree_tapbuf_size12_2_sram[1]:19 0.000128556 +20 mux_tree_tapbuf_size12_2_sram[1]:20 0.000128556 +21 mux_tree_tapbuf_size12_2_sram[1]:21 0.0004891515 +22 mux_tree_tapbuf_size12_2_sram[1]:22 0.0001070448 +23 mux_tree_tapbuf_size12_2_sram[1]:23 4.850546e-05 +24 mux_tree_tapbuf_size12_2_sram[1]:24 4.443439e-05 +25 mux_tree_tapbuf_size12_2_sram[1]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.124218e-05 +26 mux_tree_tapbuf_size12_2_sram[1]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.124218e-05 +27 mux_tree_tapbuf_size12_2_sram[1]:16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001187989 +28 mux_tree_tapbuf_size12_2_sram[1]:17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001187989 +29 mux_tree_tapbuf_size12_2_sram[1]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.387364e-05 +30 mux_tree_tapbuf_size12_2_sram[1]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001271362 +31 mux_tree_tapbuf_size12_2_sram[1]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001271362 +32 mux_tree_tapbuf_size12_2_sram[1]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.387364e-05 +33 mux_tree_tapbuf_size12_2_sram[1]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 8.466175e-06 +34 mux_tree_tapbuf_size12_2_sram[1]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.174131e-05 +35 mux_tree_tapbuf_size12_2_sram[1]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 8.466175e-06 +36 mux_tree_tapbuf_size12_2_sram[1]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.174131e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_2_sram[1]:24 0.152 +1 mux_tree_tapbuf_size12_2_sram[1]:10 mux_tree_tapbuf_size12_2_sram[1]:9 0.0007924107 +2 mux_tree_tapbuf_size12_2_sram[1]:11 mux_tree_tapbuf_size12_2_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size12_2_sram[1]:20 mux_tree_tapbuf_size12_2_sram[1]:19 0.001412947 +4 mux_tree_tapbuf_size12_2_sram[1]:21 mux_tree_tapbuf_size12_2_sram[1]:20 0.0045 +5 mux_tree_tapbuf_size12_2_sram[1]:21 mux_tree_tapbuf_size12_2_sram[1]:18 0.005767858 +6 mux_tree_tapbuf_size12_2_sram[1]:19 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size12_2_sram[1]:23 mux_tree_tapbuf_size12_2_sram[1]:22 0.0045 +8 mux_tree_tapbuf_size12_2_sram[1]:22 mux_tree_tapbuf_size12_2_sram[1]:21 0.00178125 +9 mux_tree_tapbuf_size12_2_sram[1]:24 mux_tree_tapbuf_size12_2_sram[1]:23 0.0001657609 +10 mux_tree_tapbuf_size12_2_sram[1]:9 mux_right_track_0\/mux_l2_in_3_:S 0.152 +11 mux_tree_tapbuf_size12_2_sram[1]:9 mux_tree_tapbuf_size12_2_sram[1]:8 0.0045 +12 mux_tree_tapbuf_size12_2_sram[1]:8 mux_tree_tapbuf_size12_2_sram[1]:7 0.004776786 +13 mux_tree_tapbuf_size12_2_sram[1]:6 mux_right_track_0\/mux_l2_in_2_:S 0.152 +14 mux_tree_tapbuf_size12_2_sram[1]:7 mux_tree_tapbuf_size12_2_sram[1]:6 0.0045 +15 mux_tree_tapbuf_size12_2_sram[1]:16 mux_right_track_0\/mux_l2_in_0_:S 0.152 +16 mux_tree_tapbuf_size12_2_sram[1]:17 mux_tree_tapbuf_size12_2_sram[1]:16 0.003301339 +17 mux_tree_tapbuf_size12_2_sram[1]:18 mux_tree_tapbuf_size12_2_sram[1]:17 0.0045 +18 mux_tree_tapbuf_size12_2_sram[1]:18 mux_tree_tapbuf_size12_2_sram[1]:15 0.001214286 +19 mux_tree_tapbuf_size12_2_sram[1]:12 mux_right_track_0\/mux_l2_in_1_:S 0.152 +20 mux_tree_tapbuf_size12_2_sram[1]:13 mux_tree_tapbuf_size12_2_sram[1]:12 0.001631697 +21 mux_tree_tapbuf_size12_2_sram[1]:14 mux_tree_tapbuf_size12_2_sram[1]:13 0.0045 +22 mux_tree_tapbuf_size12_2_sram[1]:14 mux_tree_tapbuf_size12_2_sram[1]:11 0.0078125 +23 mux_tree_tapbuf_size12_2_sram[1]:15 mux_tree_tapbuf_size12_2_sram[1]:14 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size12_5_sram[1] 0.003951011 //LENGTH 31.417 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.505 20.400 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 58.585 15.300 +*I mux_bottom_track_3\/mux_l2_in_2_:S I *L 0.00357 *C 56.480 25.160 +*I mux_bottom_track_3\/mux_l2_in_3_:S I *L 0.00357 *C 55.560 23.415 +*I mux_bottom_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 62.460 23.800 +*I mux_bottom_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 67.260 23.460 +*N mux_tree_tapbuf_size12_5_sram[1]:6 *C 67.222 23.460 +*N mux_tree_tapbuf_size12_5_sram[1]:7 *C 62.560 23.460 +*N mux_tree_tapbuf_size12_5_sram[1]:8 *C 62.510 23.800 +*N mux_tree_tapbuf_size12_5_sram[1]:9 *C 62.548 23.777 +*N mux_tree_tapbuf_size12_5_sram[1]:10 *C 55.560 23.415 +*N mux_tree_tapbuf_size12_5_sram[1]:11 *C 56.443 25.160 +*N mux_tree_tapbuf_size12_5_sram[1]:12 *C 54.325 25.160 +*N mux_tree_tapbuf_size12_5_sram[1]:13 *C 54.280 25.115 +*N mux_tree_tapbuf_size12_5_sram[1]:14 *C 54.280 23.845 +*N mux_tree_tapbuf_size12_5_sram[1]:15 *C 54.325 23.800 +*N mux_tree_tapbuf_size12_5_sram[1]:16 *C 55.560 23.800 +*N mux_tree_tapbuf_size12_5_sram[1]:17 *C 56.580 23.800 +*N mux_tree_tapbuf_size12_5_sram[1]:18 *C 56.580 23.755 +*N mux_tree_tapbuf_size12_5_sram[1]:19 *C 58.547 15.300 +*N mux_tree_tapbuf_size12_5_sram[1]:20 *C 58.005 15.300 +*N mux_tree_tapbuf_size12_5_sram[1]:21 *C 57.960 15.345 +*N mux_tree_tapbuf_size12_5_sram[1]:22 *C 57.960 20.400 +*N mux_tree_tapbuf_size12_5_sram[1]:23 *C 56.580 20.400 +*N mux_tree_tapbuf_size12_5_sram[1]:24 *C 56.120 20.400 +*N mux_tree_tapbuf_size12_5_sram[1]:25 *C 56.075 20.400 +*N mux_tree_tapbuf_size12_5_sram[1]:26 *C 55.543 20.400 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_3\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_track_3\/mux_l2_in_3_:S 1e-06 +4 mux_bottom_track_3\/mux_l2_in_1_:S 1e-06 +5 mux_bottom_track_3\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size12_5_sram[1]:6 0.0002775273 +7 mux_tree_tapbuf_size12_5_sram[1]:7 0.00029779 +8 mux_tree_tapbuf_size12_5_sram[1]:8 2.303801e-05 +9 mux_tree_tapbuf_size12_5_sram[1]:9 0.0004591543 +10 mux_tree_tapbuf_size12_5_sram[1]:10 5.7311e-05 +11 mux_tree_tapbuf_size12_5_sram[1]:11 0.0001966255 +12 mux_tree_tapbuf_size12_5_sram[1]:12 0.0001966255 +13 mux_tree_tapbuf_size12_5_sram[1]:13 0.0001016783 +14 mux_tree_tapbuf_size12_5_sram[1]:14 0.0001016783 +15 mux_tree_tapbuf_size12_5_sram[1]:15 9.60055e-05 +16 mux_tree_tapbuf_size12_5_sram[1]:16 0.0001933401 +17 mux_tree_tapbuf_size12_5_sram[1]:17 0.0005165729 +18 mux_tree_tapbuf_size12_5_sram[1]:18 0.0002016114 +19 mux_tree_tapbuf_size12_5_sram[1]:19 6.280455e-05 +20 mux_tree_tapbuf_size12_5_sram[1]:20 6.280455e-05 +21 mux_tree_tapbuf_size12_5_sram[1]:21 0.0002797282 +22 mux_tree_tapbuf_size12_5_sram[1]:22 0.0003524901 +23 mux_tree_tapbuf_size12_5_sram[1]:23 0.0003039799 +24 mux_tree_tapbuf_size12_5_sram[1]:24 6.086775e-05 +25 mux_tree_tapbuf_size12_5_sram[1]:25 5.168919e-05 +26 mux_tree_tapbuf_size12_5_sram[1]:26 5.168919e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_5_sram[1]:26 0.152 +1 mux_tree_tapbuf_size12_5_sram[1]:17 mux_tree_tapbuf_size12_5_sram[1]:16 0.0009107143 +2 mux_tree_tapbuf_size12_5_sram[1]:17 mux_tree_tapbuf_size12_5_sram[1]:9 0.005328125 +3 mux_tree_tapbuf_size12_5_sram[1]:18 mux_tree_tapbuf_size12_5_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size12_5_sram[1]:10 mux_bottom_track_3\/mux_l2_in_3_:S 0.152 +5 mux_tree_tapbuf_size12_5_sram[1]:15 mux_tree_tapbuf_size12_5_sram[1]:14 0.0045 +6 mux_tree_tapbuf_size12_5_sram[1]:14 mux_tree_tapbuf_size12_5_sram[1]:13 0.001133929 +7 mux_tree_tapbuf_size12_5_sram[1]:12 mux_tree_tapbuf_size12_5_sram[1]:11 0.001890625 +8 mux_tree_tapbuf_size12_5_sram[1]:13 mux_tree_tapbuf_size12_5_sram[1]:12 0.0045 +9 mux_tree_tapbuf_size12_5_sram[1]:11 mux_bottom_track_3\/mux_l2_in_2_:S 0.152 +10 mux_tree_tapbuf_size12_5_sram[1]:9 mux_bottom_track_3\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size12_5_sram[1]:9 mux_tree_tapbuf_size12_5_sram[1]:8 3.348214e-05 +12 mux_tree_tapbuf_size12_5_sram[1]:9 mux_tree_tapbuf_size12_5_sram[1]:7 0.0002834821 +13 mux_tree_tapbuf_size12_5_sram[1]:6 mux_bottom_track_3\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size12_5_sram[1]:25 mux_tree_tapbuf_size12_5_sram[1]:24 0.0045 +15 mux_tree_tapbuf_size12_5_sram[1]:24 mux_tree_tapbuf_size12_5_sram[1]:23 0.0004107143 +16 mux_tree_tapbuf_size12_5_sram[1]:26 mux_tree_tapbuf_size12_5_sram[1]:25 0.0004754465 +17 mux_tree_tapbuf_size12_5_sram[1]:19 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size12_5_sram[1]:20 mux_tree_tapbuf_size12_5_sram[1]:19 0.000484375 +19 mux_tree_tapbuf_size12_5_sram[1]:21 mux_tree_tapbuf_size12_5_sram[1]:20 0.0045 +20 mux_tree_tapbuf_size12_5_sram[1]:16 mux_tree_tapbuf_size12_5_sram[1]:15 0.001102679 +21 mux_tree_tapbuf_size12_5_sram[1]:16 mux_tree_tapbuf_size12_5_sram[1]:10 0.00034375 +22 mux_tree_tapbuf_size12_5_sram[1]:7 mux_tree_tapbuf_size12_5_sram[1]:6 0.004162946 +23 mux_tree_tapbuf_size12_5_sram[1]:23 mux_tree_tapbuf_size12_5_sram[1]:22 0.001232143 +24 mux_tree_tapbuf_size12_5_sram[1]:23 mux_tree_tapbuf_size12_5_sram[1]:18 0.002995536 +25 mux_tree_tapbuf_size12_5_sram[1]:22 mux_tree_tapbuf_size12_5_sram[1]:21 0.004513393 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_0_ccff_tail[0] 0.0009402924 //LENGTH 7.080 LUMPCC 0.0001489864 DR + +*CONN +*I mem_top_track_0\/FTB_1__52:X O *L 0 *C 67.845 112.540 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 64.575 109.820 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:2 *C 64.575 109.820 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:3 *C 64.400 109.820 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 *C 64.400 109.865 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 *C 64.400 112.495 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:6 *C 64.445 112.540 +*N mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:7 *C 67.808 112.540 + +*CAP +0 mem_top_track_0\/FTB_1__52:X 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:2 5.524851e-05 +3 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:3 5.807103e-05 +4 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 0.000122345 +5 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 0.000122345 +6 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:6 0.0002156483 +7 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:7 0.0002156483 +8 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 chany_bottom_in[5]:23 7.449321e-05 +9 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 chany_bottom_in[5]:13 7.449321e-05 + +*RES +0 mem_top_track_0\/FTB_1__52:X mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_0_ccff_tail[0]:6 0.003002232 + +*END + +*D_NET mux_tree_tapbuf_size16_0_sram[4] 0.001736573 //LENGTH 15.000 LUMPCC 0.0001288988 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q O *L 0 *C 44.925 109.820 +*I mux_top_track_4\/mux_l5_in_0_:S I *L 0.00357 *C 45.440 112.200 +*I mem_top_track_4\/FTB_9__60:A I *L 0.001746 *C 41.860 118.320 +*N mux_tree_tapbuf_size16_0_sram[4]:3 *C 41.898 118.320 +*N mux_tree_tapbuf_size16_0_sram[4]:4 *C 43.195 118.320 +*N mux_tree_tapbuf_size16_0_sram[4]:5 *C 43.240 118.275 +*N mux_tree_tapbuf_size16_0_sram[4]:6 *C 45.403 112.200 +*N mux_tree_tapbuf_size16_0_sram[4]:7 *C 43.285 112.200 +*N mux_tree_tapbuf_size16_0_sram[4]:8 *C 43.240 112.200 +*N mux_tree_tapbuf_size16_0_sram[4]:9 *C 43.240 109.865 +*N mux_tree_tapbuf_size16_0_sram[4]:10 *C 43.285 109.820 +*N mux_tree_tapbuf_size16_0_sram[4]:11 *C 44.888 109.820 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q 1e-06 +1 mux_top_track_4\/mux_l5_in_0_:S 1e-06 +2 mem_top_track_4\/FTB_9__60:A 1e-06 +3 mux_tree_tapbuf_size16_0_sram[4]:3 9.956123e-05 +4 mux_tree_tapbuf_size16_0_sram[4]:4 9.956123e-05 +5 mux_tree_tapbuf_size16_0_sram[4]:5 0.0003089682 +6 mux_tree_tapbuf_size16_0_sram[4]:6 0.0001250956 +7 mux_tree_tapbuf_size16_0_sram[4]:7 0.0001250956 +8 mux_tree_tapbuf_size16_0_sram[4]:8 0.0004719234 +9 mux_tree_tapbuf_size16_0_sram[4]:9 0.0001349423 +10 mux_tree_tapbuf_size16_0_sram[4]:10 0.0001197635 +11 mux_tree_tapbuf_size16_0_sram[4]:11 0.0001197635 +12 mux_tree_tapbuf_size16_0_sram[4]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 6.444942e-05 +13 mux_tree_tapbuf_size16_0_sram[4]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 6.444942e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q mux_tree_tapbuf_size16_0_sram[4]:11 0.152 +1 mux_tree_tapbuf_size16_0_sram[4]:4 mux_tree_tapbuf_size16_0_sram[4]:3 0.001158482 +2 mux_tree_tapbuf_size16_0_sram[4]:5 mux_tree_tapbuf_size16_0_sram[4]:4 0.0045 +3 mux_tree_tapbuf_size16_0_sram[4]:3 mem_top_track_4\/FTB_9__60:A 0.152 +4 mux_tree_tapbuf_size16_0_sram[4]:7 mux_tree_tapbuf_size16_0_sram[4]:6 0.001890625 +5 mux_tree_tapbuf_size16_0_sram[4]:8 mux_tree_tapbuf_size16_0_sram[4]:7 0.0045 +6 mux_tree_tapbuf_size16_0_sram[4]:8 mux_tree_tapbuf_size16_0_sram[4]:5 0.005424107 +7 mux_tree_tapbuf_size16_0_sram[4]:6 mux_top_track_4\/mux_l5_in_0_:S 0.152 +8 mux_tree_tapbuf_size16_0_sram[4]:10 mux_tree_tapbuf_size16_0_sram[4]:9 0.0045 +9 mux_tree_tapbuf_size16_0_sram[4]:9 mux_tree_tapbuf_size16_0_sram[4]:8 0.002084821 +10 mux_tree_tapbuf_size16_0_sram[4]:11 mux_tree_tapbuf_size16_0_sram[4]:10 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size16_2_sram[1] 0.008950397 //LENGTH 70.915 LUMPCC 0.001343158 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.495 8.840 +*I mux_bottom_track_5\/mux_l2_in_5_:S I *L 0.00357 *C 34.860 14.280 +*I mux_bottom_track_5\/mux_l2_in_2_:S I *L 0.00357 *C 33.220 19.720 +*I mux_bottom_track_5\/mux_l2_in_3_:S I *L 0.00357 *C 32.560 30.600 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 27.315 37.060 +*I mux_bottom_track_5\/mux_l2_in_6_:S I *L 0.00357 *C 29.800 39.440 +*I mux_bottom_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 38.080 40.120 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 40.120 40.120 +*I mux_bottom_track_5\/mux_l2_in_7_:S I *L 0.00357 *C 33.940 39.735 +*I mux_bottom_track_5\/mux_l2_in_4_:S I *L 0.00357 *C 35.320 6.800 +*N mux_tree_tapbuf_size16_2_sram[1]:10 *C 35.358 6.800 +*N mux_tree_tapbuf_size16_2_sram[1]:11 *C 33.940 39.735 +*N mux_tree_tapbuf_size16_2_sram[1]:12 *C 40.083 40.120 +*N mux_tree_tapbuf_size16_2_sram[1]:13 *C 38.080 40.120 +*N mux_tree_tapbuf_size16_2_sram[1]:14 *C 35.420 40.120 +*N mux_tree_tapbuf_size16_2_sram[1]:15 *C 35.420 39.780 +*N mux_tree_tapbuf_size16_2_sram[1]:16 *C 34.960 39.780 +*N mux_tree_tapbuf_size16_2_sram[1]:17 *C 34.960 39.440 +*N mux_tree_tapbuf_size16_2_sram[1]:18 *C 33.940 39.440 +*N mux_tree_tapbuf_size16_2_sram[1]:19 *C 31.740 39.440 +*N mux_tree_tapbuf_size16_2_sram[1]:20 *C 31.740 39.100 +*N mux_tree_tapbuf_size16_2_sram[1]:21 *C 29.800 39.440 +*N mux_tree_tapbuf_size16_2_sram[1]:22 *C 29.900 39.100 +*N mux_tree_tapbuf_size16_2_sram[1]:23 *C 31.280 39.100 +*N mux_tree_tapbuf_size16_2_sram[1]:24 *C 31.280 39.055 +*N mux_tree_tapbuf_size16_2_sram[1]:25 *C 27.353 37.060 +*N mux_tree_tapbuf_size16_2_sram[1]:26 *C 31.235 37.060 +*N mux_tree_tapbuf_size16_2_sram[1]:27 *C 31.280 37.060 +*N mux_tree_tapbuf_size16_2_sram[1]:28 *C 31.280 30.645 +*N mux_tree_tapbuf_size16_2_sram[1]:29 *C 31.325 30.600 +*N mux_tree_tapbuf_size16_2_sram[1]:30 *C 32.560 30.623 +*N mux_tree_tapbuf_size16_2_sram[1]:31 *C 32.560 30.940 +*N mux_tree_tapbuf_size16_2_sram[1]:32 *C 35.375 30.940 +*N mux_tree_tapbuf_size16_2_sram[1]:33 *C 35.420 30.895 +*N mux_tree_tapbuf_size16_2_sram[1]:34 *C 33.258 19.720 +*N mux_tree_tapbuf_size16_2_sram[1]:35 *C 35.375 19.720 +*N mux_tree_tapbuf_size16_2_sram[1]:36 *C 35.420 19.720 +*N mux_tree_tapbuf_size16_2_sram[1]:37 *C 35.880 19.720 +*N mux_tree_tapbuf_size16_2_sram[1]:38 *C 34.898 14.280 +*N mux_tree_tapbuf_size16_2_sram[1]:39 *C 35.835 14.280 +*N mux_tree_tapbuf_size16_2_sram[1]:40 *C 35.880 14.280 +*N mux_tree_tapbuf_size16_2_sram[1]:41 *C 35.880 6.845 +*N mux_tree_tapbuf_size16_2_sram[1]:42 *C 35.880 6.800 +*N mux_tree_tapbuf_size16_2_sram[1]:43 *C 40.435 6.800 +*N mux_tree_tapbuf_size16_2_sram[1]:44 *C 40.480 6.845 +*N mux_tree_tapbuf_size16_2_sram[1]:45 *C 40.480 8.795 +*N mux_tree_tapbuf_size16_2_sram[1]:46 *C 40.525 8.840 +*N mux_tree_tapbuf_size16_2_sram[1]:47 *C 42.458 8.840 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_5\/mux_l2_in_5_:S 1e-06 +2 mux_bottom_track_5\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_track_5\/mux_l2_in_3_:S 1e-06 +4 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_track_5\/mux_l2_in_6_:S 1e-06 +6 mux_bottom_track_5\/mux_l2_in_1_:S 1e-06 +7 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +8 mux_bottom_track_5\/mux_l2_in_7_:S 1e-06 +9 mux_bottom_track_5\/mux_l2_in_4_:S 1e-06 +10 mux_tree_tapbuf_size16_2_sram[1]:10 3.308106e-05 +11 mux_tree_tapbuf_size16_2_sram[1]:11 4.57325e-05 +12 mux_tree_tapbuf_size16_2_sram[1]:12 0.0001447588 +13 mux_tree_tapbuf_size16_2_sram[1]:13 0.000355492 +14 mux_tree_tapbuf_size16_2_sram[1]:14 0.0002103484 +15 mux_tree_tapbuf_size16_2_sram[1]:15 6.690063e-05 +16 mux_tree_tapbuf_size16_2_sram[1]:16 6.220007e-05 +17 mux_tree_tapbuf_size16_2_sram[1]:17 9.752522e-05 +18 mux_tree_tapbuf_size16_2_sram[1]:18 0.0002558451 +19 mux_tree_tapbuf_size16_2_sram[1]:19 0.0001813119 +20 mux_tree_tapbuf_size16_2_sram[1]:20 3.968508e-05 +21 mux_tree_tapbuf_size16_2_sram[1]:21 5.433881e-05 +22 mux_tree_tapbuf_size16_2_sram[1]:22 8.73867e-05 +23 mux_tree_tapbuf_size16_2_sram[1]:23 9.362549e-05 +24 mux_tree_tapbuf_size16_2_sram[1]:24 0.0001040479 +25 mux_tree_tapbuf_size16_2_sram[1]:25 0.0002470755 +26 mux_tree_tapbuf_size16_2_sram[1]:26 0.0002470755 +27 mux_tree_tapbuf_size16_2_sram[1]:27 0.0004680342 +28 mux_tree_tapbuf_size16_2_sram[1]:28 0.0003303637 +29 mux_tree_tapbuf_size16_2_sram[1]:29 0.0001306554 +30 mux_tree_tapbuf_size16_2_sram[1]:30 0.0001647894 +31 mux_tree_tapbuf_size16_2_sram[1]:31 0.0002529448 +32 mux_tree_tapbuf_size16_2_sram[1]:32 0.0002188107 +33 mux_tree_tapbuf_size16_2_sram[1]:33 0.0004849182 +34 mux_tree_tapbuf_size16_2_sram[1]:34 0.0001719553 +35 mux_tree_tapbuf_size16_2_sram[1]:35 0.0001719553 +36 mux_tree_tapbuf_size16_2_sram[1]:36 0.000519631 +37 mux_tree_tapbuf_size16_2_sram[1]:37 0.0002352338 +38 mux_tree_tapbuf_size16_2_sram[1]:38 8.646034e-05 +39 mux_tree_tapbuf_size16_2_sram[1]:39 8.646034e-05 +40 mux_tree_tapbuf_size16_2_sram[1]:40 0.0005053215 +41 mux_tree_tapbuf_size16_2_sram[1]:41 0.0002747503 +42 mux_tree_tapbuf_size16_2_sram[1]:42 0.000318101 +43 mux_tree_tapbuf_size16_2_sram[1]:43 0.0002511568 +44 mux_tree_tapbuf_size16_2_sram[1]:44 0.0001173989 +45 mux_tree_tapbuf_size16_2_sram[1]:45 0.0001173989 +46 mux_tree_tapbuf_size16_2_sram[1]:46 0.0001822342 +47 mux_tree_tapbuf_size16_2_sram[1]:47 0.0001822342 +48 mux_tree_tapbuf_size16_2_sram[1]:33 mux_tree_tapbuf_size16_2_sram[2]:13 1.910399e-05 +49 mux_tree_tapbuf_size16_2_sram[1]:33 mux_tree_tapbuf_size16_2_sram[2]:21 0.0001430949 +50 mux_tree_tapbuf_size16_2_sram[1]:33 mux_tree_tapbuf_size16_2_sram[2]:18 1.485083e-05 +51 mux_tree_tapbuf_size16_2_sram[1]:33 mux_tree_tapbuf_size16_2_sram[2]:14 1.970655e-05 +52 mux_tree_tapbuf_size16_2_sram[1]:40 mux_tree_tapbuf_size16_2_sram[2]:13 4.01725e-05 +53 mux_tree_tapbuf_size16_2_sram[1]:40 mux_tree_tapbuf_size16_2_sram[2]:9 0.0001484234 +54 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[2]:13 1.970655e-05 +55 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[2]:9 1.910399e-05 +56 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[2]:17 1.485083e-05 +57 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[2]:18 0.0001430949 +58 mux_tree_tapbuf_size16_2_sram[1]:41 mux_tree_tapbuf_size16_2_sram[2]:9 4.01725e-05 +59 mux_tree_tapbuf_size16_2_sram[1]:37 mux_tree_tapbuf_size16_2_sram[2]:13 0.0001484234 +60 mux_tree_tapbuf_size16_2_sram[1]:43 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 8.04063e-06 +61 mux_tree_tapbuf_size16_2_sram[1]:40 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.556334e-05 +62 mux_tree_tapbuf_size16_2_sram[1]:40 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.841515e-05 +63 mux_tree_tapbuf_size16_2_sram[1]:42 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.04063e-06 +64 mux_tree_tapbuf_size16_2_sram[1]:42 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 9.382433e-06 +65 mux_tree_tapbuf_size16_2_sram[1]:41 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 4.841515e-05 +66 mux_tree_tapbuf_size16_2_sram[1]:41 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.556334e-05 +67 mux_tree_tapbuf_size16_2_sram[1]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.382433e-06 +68 mux_tree_tapbuf_size16_2_sram[1]:39 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.847633e-06 +69 mux_tree_tapbuf_size16_2_sram[1]:40 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.084804e-05 +70 mux_tree_tapbuf_size16_2_sram[1]:40 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.686563e-05 +71 mux_tree_tapbuf_size16_2_sram[1]:38 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 3.847633e-06 +72 mux_tree_tapbuf_size16_2_sram[1]:41 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.686563e-05 +73 mux_tree_tapbuf_size16_2_sram[1]:37 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.084804e-05 +74 mux_tree_tapbuf_size16_2_sram[1]:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.927419e-05 +75 mux_tree_tapbuf_size16_2_sram[1]:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 1.970253e-05 +76 mux_tree_tapbuf_size16_2_sram[1]:24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.805338e-05 +77 mux_tree_tapbuf_size16_2_sram[1]:28 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.820378e-05 +78 mux_tree_tapbuf_size16_2_sram[1]:27 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.805338e-05 +79 mux_tree_tapbuf_size16_2_sram[1]:27 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.820378e-05 +80 mux_tree_tapbuf_size16_2_sram[1]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 2.927419e-05 +81 mux_tree_tapbuf_size16_2_sram[1]:20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.970253e-05 +82 mux_tree_tapbuf_size16_2_sram[1]:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 8.030122e-06 +83 mux_tree_tapbuf_size16_2_sram[1]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.030122e-06 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size16_2_sram[1]:47 0.152 +1 mux_tree_tapbuf_size16_2_sram[1]:47 mux_tree_tapbuf_size16_2_sram[1]:46 0.001725447 +2 mux_tree_tapbuf_size16_2_sram[1]:46 mux_tree_tapbuf_size16_2_sram[1]:45 0.0045 +3 mux_tree_tapbuf_size16_2_sram[1]:45 mux_tree_tapbuf_size16_2_sram[1]:44 0.001741072 +4 mux_tree_tapbuf_size16_2_sram[1]:43 mux_tree_tapbuf_size16_2_sram[1]:42 0.004066965 +5 mux_tree_tapbuf_size16_2_sram[1]:44 mux_tree_tapbuf_size16_2_sram[1]:43 0.0045 +6 mux_tree_tapbuf_size16_2_sram[1]:32 mux_tree_tapbuf_size16_2_sram[1]:31 0.002513393 +7 mux_tree_tapbuf_size16_2_sram[1]:33 mux_tree_tapbuf_size16_2_sram[1]:32 0.0045 +8 mux_tree_tapbuf_size16_2_sram[1]:39 mux_tree_tapbuf_size16_2_sram[1]:38 0.0008370536 +9 mux_tree_tapbuf_size16_2_sram[1]:40 mux_tree_tapbuf_size16_2_sram[1]:39 0.0045 +10 mux_tree_tapbuf_size16_2_sram[1]:40 mux_tree_tapbuf_size16_2_sram[1]:37 0.004857143 +11 mux_tree_tapbuf_size16_2_sram[1]:38 mux_bottom_track_5\/mux_l2_in_5_:S 0.152 +12 mux_tree_tapbuf_size16_2_sram[1]:35 mux_tree_tapbuf_size16_2_sram[1]:34 0.001890625 +13 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[1]:35 0.0045 +14 mux_tree_tapbuf_size16_2_sram[1]:36 mux_tree_tapbuf_size16_2_sram[1]:33 0.009977679 +15 mux_tree_tapbuf_size16_2_sram[1]:34 mux_bottom_track_5\/mux_l2_in_2_:S 0.152 +16 mux_tree_tapbuf_size16_2_sram[1]:23 mux_tree_tapbuf_size16_2_sram[1]:22 0.001232143 +17 mux_tree_tapbuf_size16_2_sram[1]:23 mux_tree_tapbuf_size16_2_sram[1]:20 0.0004107143 +18 mux_tree_tapbuf_size16_2_sram[1]:24 mux_tree_tapbuf_size16_2_sram[1]:23 0.0045 +19 mux_tree_tapbuf_size16_2_sram[1]:42 mux_tree_tapbuf_size16_2_sram[1]:41 0.0045 +20 mux_tree_tapbuf_size16_2_sram[1]:42 mux_tree_tapbuf_size16_2_sram[1]:10 0.0004665179 +21 mux_tree_tapbuf_size16_2_sram[1]:41 mux_tree_tapbuf_size16_2_sram[1]:40 0.006638393 +22 mux_tree_tapbuf_size16_2_sram[1]:29 mux_tree_tapbuf_size16_2_sram[1]:28 0.0045 +23 mux_tree_tapbuf_size16_2_sram[1]:28 mux_tree_tapbuf_size16_2_sram[1]:27 0.005727679 +24 mux_tree_tapbuf_size16_2_sram[1]:26 mux_tree_tapbuf_size16_2_sram[1]:25 0.003466518 +25 mux_tree_tapbuf_size16_2_sram[1]:27 mux_tree_tapbuf_size16_2_sram[1]:26 0.0045 +26 mux_tree_tapbuf_size16_2_sram[1]:27 mux_tree_tapbuf_size16_2_sram[1]:24 0.00178125 +27 mux_tree_tapbuf_size16_2_sram[1]:25 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +28 mux_tree_tapbuf_size16_2_sram[1]:11 mux_bottom_track_5\/mux_l2_in_7_:S 0.152 +29 mux_tree_tapbuf_size16_2_sram[1]:21 mux_bottom_track_5\/mux_l2_in_6_:S 0.152 +30 mux_tree_tapbuf_size16_2_sram[1]:10 mux_bottom_track_5\/mux_l2_in_4_:S 0.152 +31 mux_tree_tapbuf_size16_2_sram[1]:30 mux_bottom_track_5\/mux_l2_in_3_:S 0.152 +32 mux_tree_tapbuf_size16_2_sram[1]:30 mux_tree_tapbuf_size16_2_sram[1]:29 0.001102678 +33 mux_tree_tapbuf_size16_2_sram[1]:13 mux_bottom_track_5\/mux_l2_in_1_:S 0.152 +34 mux_tree_tapbuf_size16_2_sram[1]:13 mux_tree_tapbuf_size16_2_sram[1]:12 0.001787947 +35 mux_tree_tapbuf_size16_2_sram[1]:12 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +36 mux_tree_tapbuf_size16_2_sram[1]:22 mux_tree_tapbuf_size16_2_sram[1]:21 0.0003035715 +37 mux_tree_tapbuf_size16_2_sram[1]:20 mux_tree_tapbuf_size16_2_sram[1]:19 0.0003035715 +38 mux_tree_tapbuf_size16_2_sram[1]:19 mux_tree_tapbuf_size16_2_sram[1]:18 0.001964286 +39 mux_tree_tapbuf_size16_2_sram[1]:18 mux_tree_tapbuf_size16_2_sram[1]:17 0.0009107144 +40 mux_tree_tapbuf_size16_2_sram[1]:18 mux_tree_tapbuf_size16_2_sram[1]:11 0.0001271552 +41 mux_tree_tapbuf_size16_2_sram[1]:17 mux_tree_tapbuf_size16_2_sram[1]:16 0.0003035715 +42 mux_tree_tapbuf_size16_2_sram[1]:31 mux_tree_tapbuf_size16_2_sram[1]:30 0.0002834821 +43 mux_tree_tapbuf_size16_2_sram[1]:16 mux_tree_tapbuf_size16_2_sram[1]:15 0.0004107143 +44 mux_tree_tapbuf_size16_2_sram[1]:15 mux_tree_tapbuf_size16_2_sram[1]:14 0.0003035715 +45 mux_tree_tapbuf_size16_2_sram[1]:14 mux_tree_tapbuf_size16_2_sram[1]:13 0.002375 +46 mux_tree_tapbuf_size16_2_sram[1]:37 mux_tree_tapbuf_size16_2_sram[1]:36 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_1_ccff_tail[0] 0.001625204 //LENGTH 13.000 LUMPCC 0.0001486859 DR + +*CONN +*I mem_right_track_32\/FTB_26__77:X O *L 0 *C 103.275 63.920 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 94.015 60.860 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 *C 94.053 60.860 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 *C 102.995 60.860 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 *C 103.040 60.905 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 *C 103.040 63.875 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 *C 103.040 63.920 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 *C 103.275 63.920 + +*CAP +0 mem_right_track_32\/FTB_26__77:X 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 0.0005048184 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0005048184 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.0001789536 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0001789536 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 5.401333e-05 +7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 5.296103e-05 +8 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mux_tree_tapbuf_size12_4_sram[0]:35 7.434293e-05 +9 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size12_4_sram[0]:36 7.434293e-05 + +*RES +0 mem_right_track_32\/FTB_26__77:X mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 0.007984376 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009888185 //LENGTH 6.575 LUMPCC 0.0002812613 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_4_:X O *L 0 *C 75.265 95.880 +*I mux_top_track_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 75.540 90.780 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 75.502 90.780 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 75.025 90.780 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 74.980 90.825 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 74.980 95.835 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 74.980 95.880 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 75.265 95.880 + +*CAP +0 mux_top_track_0\/mux_l1_in_4_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.839455e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.839455e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002187791 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002187791 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.653634e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.467337e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[6]:22 0.0001406306 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[6]:23 0.0001406306 + +*RES +0 mux_top_track_0\/mux_l1_in_4_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_0\/mux_l2_in_2_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004263393 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473215 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001622854 //LENGTH 12.430 LUMPCC 0.0004454042 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_1_:X O *L 0 *C 52.725 102.340 +*I mux_top_track_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 53.535 113.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 53.498 113.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 52.945 113.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 52.900 113.175 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 52.900 102.385 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 52.900 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 52.725 102.340 + +*CAP +0 mux_top_track_2\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 4.161677e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 4.161677e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0004861303 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0004861302 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 6.144233e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 5.851319e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_1_sram[2]:6 0.0001355993 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_1_sram[2]:19 2.195937e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_1_sram[2]:18 2.195937e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_1_sram[2]:19 0.0001355993 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size12_1_sram[3]:8 1.284374e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size12_1_sram[3]:7 1.284374e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_1_sram[3]:6 2.744034e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_1_sram[3]:10 2.485942e-05 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_1_sram[3]:9 2.744034e-05 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_1_sram[3]:11 2.485942e-05 + +*RES +0 mux_top_track_2\/mux_l3_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_top_track_2\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0004933036 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.009633929 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000540292 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_1_:X O *L 0 *C 91.825 105.060 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 92.175 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 92.175 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 107.780 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 107.735 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.000 105.105 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 92.000 105.060 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 91.825 105.060 + +*CAP +0 mux_right_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.684106e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.154591e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001641624 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001641624 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.436793e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.721238e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003177743 //LENGTH 23.135 LUMPCC 0.0004971929 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_0_:X O *L 0 *C 89.985 93.160 +*I mux_right_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 109.120 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 109.120 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 109.020 90.440 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 94.345 90.440 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 94.300 90.485 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 94.300 93.115 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 94.255 93.160 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 90.023 93.160 + +*CAP +0 mux_right_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.74355e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0009365139 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0009102885 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001717331 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001717331 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000215423 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.000215423 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[1]:15 0.0001671417 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chanx_right_in[1]:14 0.0001671417 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size12_3_sram[1]:23 2.412322e-06 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size12_3_sram[1]:24 1.073512e-06 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size12_3_sram[1]:22 7.796887e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_3_sram[1]:17 2.412322e-06 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_3_sram[1]:23 7.796887e-05 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_3_sram[1]:25 1.073512e-06 + +*RES +0 mux_right_track_2\/mux_l1_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.01310268 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002348215 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.003779018 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002214746 //LENGTH 14.855 LUMPCC 0.001088614 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_2_:X O *L 0 *C 81.705 36.380 +*I mux_bottom_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 82.440 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 82.403 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 81.465 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 81.420 23.505 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 81.420 36.335 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 81.420 36.380 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 81.705 36.380 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.681734e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.681734e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004060053 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004060053 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.118205e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.730411e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 bottom_left_grid_pin_34_[0]:14 0.0003293356 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 bottom_left_grid_pin_34_[0]:12 2.406408e-07 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 bottom_left_grid_pin_34_[0]:13 0.0003293356 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 bottom_left_grid_pin_34_[0]:10 2.406408e-07 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[0]:21 2.855601e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[0]:22 0.0001861749 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_6_sram[0]:18 2.855601e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_6_sram[0]:21 0.0001861749 + +*RES +0 mux_bottom_track_1\/mux_l1_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008370536 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01145536 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004895427 //LENGTH 3.175 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_2_:X O *L 0 *C 60.895 25.160 +*I mux_bottom_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 61.740 23.460 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 61.703 23.460 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 61.225 23.460 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 61.180 23.505 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 61.180 25.115 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 61.180 25.160 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 60.895 25.160 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.436131e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.436131e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000113513 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000113513 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.912241e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.267168e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_2_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00142689 //LENGTH 10.455 LUMPCC 0.0001700987 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 78.835 90.440 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 74.520 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 74.558 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 76.775 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 76.820 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 77.280 85.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 77.280 90.395 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 77.325 90.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 78.797 90.440 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000125951 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000125951 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.344144e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003516945 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003143825 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001316856 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001316856 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.504934e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.504934e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.001314732 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.004513393 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001979911 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004107143 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0] 0.000890534 //LENGTH 7.335 LUMPCC 0.0001025045 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_1_:X O *L 0 *C 28.345 99.280 +*I mux_left_track_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 30.190 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 30.228 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 31.235 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 31.280 96.945 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 31.280 99.235 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 31.235 99.280 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 28.383 99.280 + +*CAP +0 mux_left_track_3\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 6.794139e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 6.794139e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.000151181 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.000151181 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0001738924 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0001738924 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size12_7_sram[1]:13 5.114774e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size12_7_sram[1]:14 5.114774e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_7_sram[1]:28 1.045039e-07 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_7_sram[1]:16 1.045039e-07 + +*RES +0 mux_left_track_3\/mux_l3_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_3\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0008995536 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.002044643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.002546875 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001541328 //LENGTH 11.980 LUMPCC 0.0001910104 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_3_:X O *L 0 *C 20.065 99.620 +*I mux_left_track_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 26.395 98.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 26.358 98.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 25.805 98.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 25.760 98.985 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 25.760 101.275 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 25.715 101.320 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 20.745 101.320 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 20.700 101.275 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 20.700 99.665 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 *C 20.655 99.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 *C 20.103 99.620 + +*CAP +0 mux_left_track_3\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.475345e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.475345e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001395176 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001395176 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0003293004 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0003293004 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 7.794644e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 7.794644e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 7.264096e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 7.264096e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 left_top_grid_pin_45_[0]:6 8.772924e-07 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 left_top_grid_pin_45_[0]:8 6.46972e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 left_top_grid_pin_45_[0]:7 8.772924e-07 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 left_top_grid_pin_45_[0]:23 6.46972e-05 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 left_top_grid_pin_45_[0]:7 5.618749e-06 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 left_top_grid_pin_45_[0]:22 2.431195e-05 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 left_top_grid_pin_45_[0]:6 5.618749e-06 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 left_top_grid_pin_45_[0]:21 2.431195e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_3_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_3\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0004933036 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002044643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0044375 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0045 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0045 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0014375 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0004933036 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002070016 //LENGTH 15.995 LUMPCC 0.0004969399 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_6_:X O *L 0 *C 36.625 80.580 +*I mux_top_track_4\/mux_l3_in_3_:A1 I *L 0.00198 *C 38.280 94.180 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 38.242 94.180 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 36.845 94.180 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 36.800 94.135 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 36.800 80.625 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 36.800 80.580 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 36.625 80.580 + +*CAP +0 mux_top_track_4\/mux_l2_in_6_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_3_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.663914e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.663914e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0006527426 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0006527426 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.375743e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.855463e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size12_6_sram[2]:14 6.746253e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size12_6_sram[2]:15 6.746253e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size16_0_sram[2]:20 6.555136e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size16_0_sram[2]:21 6.555136e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size16_0_sram[2]:18 1.063495e-06 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size16_0_sram[2]:25 1.212549e-06 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:17 1.063495e-06 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:22 1.212549e-06 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.219482e-07 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.219482e-07 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001125581 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001125581 + +*RES +0 mux_top_track_4\/mux_l2_in_6_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_4\/mux_l3_in_3_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001247768 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0120625 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.007757663 //LENGTH 42.655 LUMPCC 0.003540709 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_5_:X O *L 0 *C 80.785 74.800 +*I mux_right_track_4\/mux_l3_in_2_:A0 I *L 0.001631 *C 116.555 71.740 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 116.518 71.740 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 114.125 71.740 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 114.080 71.740 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 114.080 72.080 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 114.073 72.080 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 108.560 72.080 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 108.560 71.400 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 97.980 71.400 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 97.980 72.080 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 83.267 72.080 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 83.260 72.138 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 83.260 74.755 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 83.215 74.800 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 80.823 74.800 + +*CAP +0 mux_right_track_4\/mux_l2_in_5_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_2_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002018993 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002018993 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.439931e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.813999e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000351204 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003941328 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0004554759 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0004851048 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0006034716 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0005309139 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0002297772 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0002297772 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0002093786 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.0002093786 +16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[6]:30 4.356183e-05 +17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_right_in[6]:29 5.59181e-05 +18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_right_in[6]:30 5.59181e-05 +19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chanx_right_in[6]:29 0.0002283573 +20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[6]:30 0.0002283573 +21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[6]:29 4.356183e-05 +22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[7] 2.072701e-05 +23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_right_in[7]:17 0.0002786385 +24 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_right_in[7]:18 0.0005044727 +25 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_right_in[7]:18 0.0002786385 +26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_right_in[7]:19 0.0005044727 +27 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chanx_right_in[7]:18 0.0001926118 +28 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chanx_right_in[7]:22 5.463859e-06 +29 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[7]:19 0.0001926118 +30 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[7]:21 6.500462e-06 +31 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[7]:23 5.463859e-06 +32 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chanx_right_in[7]:25 8.200679e-06 +33 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[7]:20 6.500462e-06 +34 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[7]:24 8.200679e-06 +35 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[7]:26 2.072701e-05 +36 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chany_bottom_in[3]:17 0.0004259025 +37 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chany_bottom_in[3]:18 0.0004259025 + +*RES +0 mux_right_track_4\/mux_l2_in_5_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_4\/mux_l3_in_2_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002136161 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001634616 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.002304958 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.002337054 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.002136161 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001065333 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001657533 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001065333 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0008636249 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0] 0.001511363 //LENGTH 10.645 LUMPCC 0.0007531285 DR + +*CONN +*I mux_left_track_5\/mux_l5_in_0_:X O *L 0 *C 7.995 87.720 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.345 80.410 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 *C 5.345 80.410 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 *C 7.315 80.580 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 *C 7.360 80.625 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 *C 7.360 87.675 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 *C 7.405 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 *C 7.958 87.720 + +*CAP +0 mux_left_track_5\/mux_l5_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.000136944 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0001050703 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.0001955234 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0001955234 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 6.158645e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 6.158645e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 left_top_grid_pin_42_[0]:10 0.000199414 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 left_top_grid_pin_42_[0]:24 0.000199414 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 ropt_net_187:2 6.009851e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 ropt_net_187:3 6.009851e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 ropt_net_216:5 4.535121e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 ropt_net_216:4 4.535121e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 BUF_net_89:4 7.170053e-05 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 BUF_net_89:3 7.170053e-05 + +*RES +0 mux_left_track_5\/mux_l5_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.001758929 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.006294644 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002109179 //LENGTH 16.685 LUMPCC 0.0006247782 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 101.025 58.140 +*I mux_top_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 105.900 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 105.863 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 101.705 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 101.660 47.305 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 101.660 58.095 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 101.615 58.140 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 101.062 58.140 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001896004 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001896004 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0005204121 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005204121 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.118784e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.118784e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_0_sram[1]:22 4.639319e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_0_sram[1]:21 4.639319e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:23 9.016444e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:24 2.349811e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_0_sram[1]:7 3.463783e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:8 2.349811e-05 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:24 9.016444e-05 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_0_sram[1]:6 3.463783e-05 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.99285e-06 +17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001087027 +18 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001087027 +19 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.99285e-06 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003712054 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.009633929 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0] 0.01119483 //LENGTH 72.415 LUMPCC 0.004993702 DR + +*CONN +*I mux_top_track_16\/mux_l4_in_0_:X O *L 0 *C 51.345 59.160 +*I mux_top_track_16\/BUFT_RR_80:A I *L 0.001776 *C 59.340 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 59.303 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 57.085 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 57.040 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 57.033 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 53.380 121.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 53.360 121.032 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 53.360 111.035 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 53.360 61.208 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 53.345 61.200 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 52.903 61.200 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 52.900 61.200 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 52.900 60.860 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 52.855 60.860 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 51.105 60.860 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:16 *C 51.060 60.815 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:17 *C 51.060 59.205 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 *C 51.060 59.160 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 *C 51.345 59.160 + +*CAP +0 mux_top_track_16\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_16\/BUFT_RR_80:A 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001818997 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001818997 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.063999e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002886383 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0002886383 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001939734 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.002073355 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001879381 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:10 8.816172e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:11 8.816172e-05 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:12 6.751615e-05 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:13 6.312939e-05 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0002007551 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0002007551 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:16 0.0001309347 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:17 0.0001309347 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 5.156409e-05 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 4.879382e-05 +20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_bottom_in[17]:11 8.633822e-05 +21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_bottom_in[17]:12 0.0001361402 +22 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chany_bottom_in[17]:13 0.0004529703 +23 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 chany_bottom_in[17]:21 1.062495e-05 +24 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 chany_bottom_in[17]:22 1.062495e-05 +25 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_bottom_in[17]:12 0.0005393085 +26 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_bottom_in[17]:13 0.0001361402 +27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chany_top_in[15]:18 4.279559e-07 +28 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chany_top_in[15]:17 4.279559e-07 +29 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chany_top_in[15]:16 0.0002224785 +30 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 chany_top_in[15]:15 0.0004623978 +31 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_top_in[15]:15 0.0002224785 +32 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 chany_top_in[15]:16 0.0004623978 +33 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.001125473 +34 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.001125473 + +*RES +0 mux_top_track_16\/mux_l4_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_16\/BUFT_RR_80:A 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.001979911 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.00341 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.000572225 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00341 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00341 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.007806308 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:10 6.499219e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0001634615 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0015625 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0045 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:17 0.0045 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:16 0.0014375 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 0.0001548913 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.001566275 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001880447 //LENGTH 12.670 LUMPCC 0.0007659991 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_1_:X O *L 0 *C 80.675 69.360 +*I mux_right_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 78.870 59.160 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 78.870 59.160 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 79.120 59.160 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 79.120 59.205 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 79.120 69.315 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 79.165 69.360 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 80.638 69.360 + +*CAP +0 mux_right_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.474818e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.651788e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003508118 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003508118 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001397792 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001397792 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[7]:13 0.0002681078 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[7]:12 0.0002681078 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001148918 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001148918 + +*RES +0 mux_right_track_16\/mux_l1_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001358696 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.009026786 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006987534 //LENGTH 3.620 LUMPCC 0.0002571065 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_1_:X O *L 0 *C 84.355 88.740 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.815 86.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 84.815 86.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 84.640 86.020 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 84.640 86.065 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 84.640 88.695 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 84.640 88.740 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 84.355 88.740 + +*CAP +0 mux_right_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.294965e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.896151e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.68961e-05 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.68961e-05 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.852425e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.541926e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.131968e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.131968e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.723358e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.723358e-05 + +*RES +0 mux_right_track_24\/mux_l1_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.51087e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001300029 //LENGTH 9.340 LUMPCC 0.0001049768 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_3_:X O *L 0 *C 101.835 33.320 +*I mux_bottom_track_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 99.075 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 99.113 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 100.280 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 100.280 28.560 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 102.075 28.560 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 102.120 28.605 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 102.120 33.275 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 102.120 33.320 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 101.835 33.320 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001050633 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001308128 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001772395 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00015149 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002506487 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002506487 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 6.400197e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 6.314676e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:125 5.051077e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:131 5.612174e-07 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:132 1.416406e-06 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:124 5.051077e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:128 1.416406e-06 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:132 5.612174e-07 + +*RES +0 mux_bottom_track_9\/mux_l2_in_3_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_9\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001602679 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.004169643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001548913 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001042411 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0] 0.002554149 //LENGTH 20.235 LUMPCC 0.0004913327 DR + +*CONN +*I mux_bottom_track_17\/mux_l4_in_0_:X O *L 0 *C 55.945 33.320 +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 54.610 15.160 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 54.610 15.160 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 54.610 15.640 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 55.615 15.640 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 55.660 15.685 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 55.660 33.275 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 55.660 33.320 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 55.945 33.320 + +*CAP +0 mux_bottom_track_17\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.165844e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001249917 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 9.47877e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0008294993 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0008294993 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.988459e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 6.04954e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:321 2.302552e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:360 0.0001163906 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:356 5.331556e-06 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:322 2.302552e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:359 0.0001163906 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 prog_clk[0]:357 7.608342e-06 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 prog_clk[0]:357 5.331556e-06 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 prog_clk[0]:358 7.608342e-06 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 bottom_left_grid_pin_36_[0]:6 3.411224e-05 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 bottom_left_grid_pin_36_[0]:14 5.919804e-05 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 bottom_left_grid_pin_36_[0]:13 5.919804e-05 +20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 bottom_left_grid_pin_36_[0]:14 3.411224e-05 + +*RES +0 mux_bottom_track_17\/mux_l4_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001548913 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.01570536 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0008973214 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004285715 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002940508 //LENGTH 20.975 LUMPCC 0.0002769713 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_1_:X O *L 0 *C 69.175 70.040 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 54.570 75.480 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 54.608 75.480 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 56.535 75.480 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 56.580 75.435 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 56.580 70.085 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 56.625 70.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 69.138 70.040 + +*CAP +0 mux_left_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001506785 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001506785 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002964094 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002964094 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0008836806 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0008836806 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_2_sram[2]:9 6.561412e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_2_sram[2]:13 1.165019e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_2_sram[2]:9 1.031909e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_2_sram[2]:8 6.561412e-05 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_2_sram[2]:12 1.165019e-05 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_2_sram[2]:12 1.031909e-05 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.090224e-05 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.090224e-05 + +*RES +0 mux_left_track_9\/mux_l1_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001720982 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.01117188 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.004549685 //LENGTH 30.485 LUMPCC 0.001706367 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_0_:X O *L 0 *C 63.655 56.100 +*I mux_left_track_17\/mux_l3_in_0_:A1 I *L 0.00198 *C 36.340 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 36.378 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 37.720 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 37.720 55.080 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 42.320 55.080 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 42.320 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.260 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 60.260 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 63.617 56.100 + +*CAP +0 mux_left_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001085095 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001772018 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004130907 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003697777 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0008179806 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0008271688 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 8.107854e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 4.651096e-05 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chany_bottom_in[6]:22 0.0001338593 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chany_bottom_in[6]:21 7.31956e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chany_bottom_in[6]:22 7.31956e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chany_bottom_in[6]:21 0.0001338593 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size10_10_sram[1]:21 0.0001167764 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size10_10_sram[1]:27 2.130753e-06 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size10_10_sram[1]:28 0.0005142312 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size10_10_sram[1]:27 0.0005272213 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size10_10_sram[1]:22 0.0001297665 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size10_10_sram[1]:28 2.130753e-06 + +*RES +0 mux_left_track_17\/mux_l2_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.002997768 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001198661 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0009107144 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004107143 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003035715 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.01601786 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0006071429 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0003924801 //LENGTH 2.475 LUMPCC 0.0001432228 DR + +*CONN +*I mux_left_track_25\/mux_l3_in_1_:X O *L 0 *C 18.115 60.520 +*I mux_left_track_25\/mux_l4_in_0_:A0 I *L 0.001631 *C 15.930 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 15.968 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 18.078 60.520 + +*CAP +0 mux_left_track_25\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001236286 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001236286 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_11_sram[2]:8 6.612574e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_11_sram[2]:10 5.485648e-06 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_11_sram[2]:9 6.612574e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_11_sram[2]:11 5.485648e-06 + +*RES +0 mux_left_track_25\/mux_l3_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_25\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001883929 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007945063 //LENGTH 5.785 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_0_:X O *L 0 *C 80.325 106.760 +*I mux_top_track_32\/mux_l3_in_0_:A1 I *L 0.00198 *C 85.200 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 85.163 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 84.640 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 84.640 106.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 80.362 106.760 + +*CAP +0 mux_top_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.798581e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.599549e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003382673 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003102577 + +*RES +0 mux_top_track_32\/mux_l2_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003819196 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004665179 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0] 0.005820747 //LENGTH 44.720 LUMPCC 0.002367516 DR + +*CONN +*I mux_right_track_32\/mux_l3_in_0_:X O *L 0 *C 97.345 65.960 +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 124.855 50.160 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 124.855 50.160 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 124.660 49.980 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 124.660 50.025 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 124.660 59.783 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 124.653 59.840 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 97.528 59.840 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 97.520 59.898 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 97.520 65.915 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 97.520 65.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 97.345 65.960 + +*CAP +0 mux_right_track_32\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.076164e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.849287e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0005231171 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0005231171 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0007318873 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0007318873 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003617089 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0003617089 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.94856e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.906431e-05 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:182 0.0001152589 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:192 0.0001284752 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:193 9.559841e-05 +15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:178 0.0001152589 +16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:182 0.0001284752 +17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:192 9.559841e-05 +18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[15]:15 7.237944e-05 +19 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_right_in[15]:17 0.0001372923 +20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[15]:16 7.237944e-05 +21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_right_in[15]:18 0.0001372923 +22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size10_4_sram[0]:19 0.0006347537 +23 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size10_4_sram[0]:20 0.0006347537 + +*RES +0 mux_right_track_32\/mux_l3_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:10 9.51087e-05 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.005372768 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.004249583 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.008712053 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.782609e-05 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ropt_net_162 0.00195345 //LENGTH 16.450 LUMPCC 0.0002322806 DR + +*CONN +*I FTB_4__3:X O *L 0 *C 66.240 12.240 +*I ropt_mt_inst_800:A I *L 0.001766 *C 58.880 4.080 +*N ropt_net_162:2 *C 58.918 4.080 +*N ropt_net_162:3 *C 60.675 4.080 +*N ropt_net_162:4 *C 60.720 4.125 +*N ropt_net_162:5 *C 60.720 12.195 +*N ropt_net_162:6 *C 60.765 12.240 +*N ropt_net_162:7 *C 66.203 12.240 + +*CAP +0 FTB_4__3:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_162:2 0.0001284614 +3 ropt_net_162:3 0.0001284614 +4 ropt_net_162:4 0.0004069525 +5 ropt_net_162:5 0.0004069525 +6 ropt_net_162:6 0.0003241708 +7 ropt_net_162:7 0.0003241708 +8 ropt_net_162:4 mux_tree_tapbuf_size12_5_sram[3]:9 5.926117e-06 +9 ropt_net_162:4 mux_tree_tapbuf_size12_5_sram[3]:11 7.088173e-05 +10 ropt_net_162:6 mux_tree_tapbuf_size12_5_sram[3]:13 3.933245e-05 +11 ropt_net_162:5 mux_tree_tapbuf_size12_5_sram[3]:8 5.926117e-06 +12 ropt_net_162:5 mux_tree_tapbuf_size12_5_sram[3]:12 7.088173e-05 +13 ropt_net_162:7 mux_tree_tapbuf_size12_5_sram[3]:14 3.933245e-05 + +*RES +0 FTB_4__3:X ropt_net_162:7 0.152 +1 ropt_net_162:2 ropt_mt_inst_800:A 0.152 +2 ropt_net_162:3 ropt_net_162:2 0.001569197 +3 ropt_net_162:4 ropt_net_162:3 0.0045 +4 ropt_net_162:6 ropt_net_162:5 0.0045 +5 ropt_net_162:5 ropt_net_162:4 0.007205358 +6 ropt_net_162:7 ropt_net_162:6 0.004854911 + +*END + +*D_NET ropt_net_221 0.001447534 //LENGTH 9.725 LUMPCC 0.0004829483 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 73.805 121.720 +*I ropt_mt_inst_865:A I *L 0.001767 *C 67.160 123.760 +*N ropt_net_221:2 *C 67.198 123.760 +*N ropt_net_221:3 *C 70.795 123.760 +*N ropt_net_221:4 *C 70.840 123.760 +*N ropt_net_221:5 *C 71.300 123.760 +*N ropt_net_221:6 *C 71.300 121.765 +*N ropt_net_221:7 *C 71.345 121.720 +*N ropt_net_221:8 *C 73.767 121.720 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 ropt_mt_inst_865:A 1e-06 +2 ropt_net_221:2 0.000149838 +3 ropt_net_221:3 0.000149838 +4 ropt_net_221:4 7.356828e-05 +5 ropt_net_221:5 0.0001170723 +6 ropt_net_221:6 7.95614e-05 +7 ropt_net_221:7 0.0001963537 +8 ropt_net_221:8 0.0001963537 +9 ropt_net_221:6 chany_top_in[8]:34 5.493501e-05 +10 ropt_net_221:5 chany_top_in[8]:35 5.493501e-05 +11 ropt_net_221:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:5 1.700049e-05 +12 ropt_net_221:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:7 5.112347e-05 +13 ropt_net_221:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:8 5.112347e-05 +14 ropt_net_221:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_15_X[0]:6 1.700049e-05 +15 ropt_net_221:6 ropt_net_182:4 6.75404e-06 +16 ropt_net_221:3 ropt_net_182:4 0.0001116612 +17 ropt_net_221:2 ropt_net_182:5 0.0001116612 +18 ropt_net_221:5 ropt_net_182:3 6.75404e-06 + +*RES +0 ropt_mt_inst_792:X ropt_net_221:8 0.152 +1 ropt_net_221:8 ropt_net_221:7 0.002162946 +2 ropt_net_221:7 ropt_net_221:6 0.0045 +3 ropt_net_221:6 ropt_net_221:5 0.00178125 +4 ropt_net_221:3 ropt_net_221:2 0.003212054 +5 ropt_net_221:4 ropt_net_221:3 0.0045 +6 ropt_net_221:2 ropt_mt_inst_865:A 0.152 +7 ropt_net_221:5 ropt_net_221:4 0.0004107143 + +*END + +*D_NET ropt_net_198 0.001245318 //LENGTH 9.420 LUMPCC 7.153895e-05 DR + +*CONN +*I FTB_32__31:X O *L 0 *C 101.200 121.720 +*I ropt_mt_inst_839:A I *L 0.001766 *C 96.140 123.760 +*N ropt_net_198:2 *C 96.140 123.760 +*N ropt_net_198:3 *C 96.140 123.805 +*N ropt_net_198:4 *C 96.140 124.395 +*N ropt_net_198:5 *C 96.185 124.440 +*N ropt_net_198:6 *C 101.155 124.440 +*N ropt_net_198:7 *C 101.200 124.395 +*N ropt_net_198:8 *C 101.200 121.765 +*N ropt_net_198:9 *C 101.200 121.720 + +*CAP +0 FTB_32__31:X 1e-06 +1 ropt_mt_inst_839:A 1e-06 +2 ropt_net_198:2 3.523031e-05 +3 ropt_net_198:3 5.295762e-05 +4 ropt_net_198:4 5.295762e-05 +5 ropt_net_198:5 0.0003196116 +6 ropt_net_198:6 0.0003196116 +7 ropt_net_198:7 0.0001797656 +8 ropt_net_198:8 0.0001797656 +9 ropt_net_198:9 3.187903e-05 +10 ropt_net_198:5 ropt_net_231:5 3.473322e-05 +11 ropt_net_198:6 ropt_net_231:6 3.473322e-05 +12 ropt_net_198:7 ropt_net_231:3 1.036248e-06 +13 ropt_net_198:8 ropt_net_231:4 1.036248e-06 + +*RES +0 FTB_32__31:X ropt_net_198:9 0.152 +1 ropt_net_198:2 ropt_mt_inst_839:A 0.152 +2 ropt_net_198:3 ropt_net_198:2 0.0045 +3 ropt_net_198:5 ropt_net_198:4 0.0045 +4 ropt_net_198:4 ropt_net_198:3 0.0005267858 +5 ropt_net_198:6 ropt_net_198:5 0.0044375 +6 ropt_net_198:7 ropt_net_198:6 0.0045 +7 ropt_net_198:9 ropt_net_198:8 0.0045 +8 ropt_net_198:8 ropt_net_198:7 0.002348214 + +*END + +*D_NET chanx_left_out[10] 0.0005660519 //LENGTH 3.700 LUMPCC 9.142215e-05 DR + +*CONN +*I ropt_mt_inst_851:X O *L 0 *C 4.140 52.700 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 53.040 +*N chanx_left_out[10]:2 *C 1.833 53.040 +*N chanx_left_out[10]:3 *C 1.840 53.040 +*N chanx_left_out[10]:4 *C 1.840 52.700 +*N chanx_left_out[10]:5 *C 1.885 52.700 +*N chanx_left_out[10]:6 *C 4.103 52.700 + +*CAP +0 ropt_mt_inst_851:X 1e-06 +1 chanx_left_out[10] 6.739387e-05 +2 chanx_left_out[10]:2 6.739387e-05 +3 chanx_left_out[10]:3 5.511007e-05 +4 chanx_left_out[10]:4 5.149404e-05 +5 chanx_left_out[10]:5 0.000116119 +6 chanx_left_out[10]:6 0.000116119 +7 chanx_left_out[10]:6 ropt_net_211:3 4.571107e-05 +8 chanx_left_out[10]:5 ropt_net_211:2 4.571107e-05 + +*RES +0 ropt_mt_inst_851:X chanx_left_out[10]:6 0.152 +1 chanx_left_out[10]:6 chanx_left_out[10]:5 0.001979911 +2 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0045 +3 chanx_left_out[10]:4 chanx_left_out[10]:3 0.0001634615 +4 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +5 chanx_left_out[10]:2 chanx_left_out[10] 9.439165e-05 + +*END + +*D_NET BUF_net_89 0.001992853 //LENGTH 14.965 LUMPCC 0.0005744053 DR + +*CONN +*I BUFT_RR_89:X O *L 0 *C 11.040 72.760 +*I BUFT_P_134:A I *L 0.001766 *C 6.900 82.960 +*N BUF_net_89:2 *C 6.900 82.960 +*N BUF_net_89:3 *C 6.900 82.915 +*N BUF_net_89:4 *C 6.900 72.805 +*N BUF_net_89:5 *C 6.945 72.760 +*N BUF_net_89:6 *C 11.003 72.760 + +*CAP +0 BUFT_RR_89:X 1e-06 +1 BUFT_P_134:A 1e-06 +2 BUF_net_89:2 3.740433e-05 +3 BUF_net_89:3 0.0004024064 +4 BUF_net_89:4 0.0004024064 +5 BUF_net_89:5 0.0002871151 +6 BUF_net_89:6 0.0002871151 +7 BUF_net_89:4 chanx_left_out[4]:3 5.204225e-06 +8 BUF_net_89:4 chanx_left_out[4]:6 6.203974e-05 +9 BUF_net_89:3 chanx_left_out[4]:2 5.204225e-06 +10 BUF_net_89:3 chanx_left_out[4]:5 6.203974e-05 +11 BUF_net_89:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 7.170053e-05 +12 BUF_net_89:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 7.170053e-05 +13 BUF_net_89:4 chanx_left_out[3]:4 0.0001482582 +14 BUF_net_89:3 chanx_left_out[3]:5 0.0001482582 + +*RES +0 BUFT_RR_89:X BUF_net_89:6 0.152 +1 BUF_net_89:6 BUF_net_89:5 0.003622768 +2 BUF_net_89:5 BUF_net_89:4 0.0045 +3 BUF_net_89:4 BUF_net_89:3 0.009026786 +4 BUF_net_89:2 BUFT_P_134:A 0.152 +5 BUF_net_89:3 BUF_net_89:2 0.0045 + +*END + +*D_NET ropt_net_235 0.0001240694 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_826:X O *L 0 *C 9.855 80.240 +*I ropt_mt_inst_883:A I *L 0.001767 *C 10.580 80.240 +*N ropt_net_235:2 *C 10.543 80.240 +*N ropt_net_235:3 *C 9.893 80.240 + +*CAP +0 ropt_mt_inst_826:X 1e-06 +1 ropt_mt_inst_883:A 1e-06 +2 ropt_net_235:2 6.10347e-05 +3 ropt_net_235:3 6.10347e-05 + +*RES +0 ropt_mt_inst_826:X ropt_net_235:3 0.152 +1 ropt_net_235:2 ropt_mt_inst_883:A 0.152 +2 ropt_net_235:3 ropt_net_235:2 0.0005803572 + +*END + +*D_NET ropt_net_227 0.001411835 //LENGTH 11.605 LUMPCC 0.0001373223 DR + +*CONN +*I ropt_mt_inst_835:X O *L 0 *C 98.175 120.360 +*I ropt_mt_inst_874:A I *L 0.001767 *C 91.540 123.760 +*N ropt_net_227:2 *C 91.578 123.760 +*N ropt_net_227:3 *C 92.415 123.760 +*N ropt_net_227:4 *C 92.460 123.715 +*N ropt_net_227:5 *C 92.460 123.125 +*N ropt_net_227:6 *C 92.505 123.080 +*N ropt_net_227:7 *C 94.255 123.080 +*N ropt_net_227:8 *C 94.300 123.035 +*N ropt_net_227:9 *C 94.300 120.405 +*N ropt_net_227:10 *C 94.345 120.360 +*N ropt_net_227:11 *C 98.138 120.360 + +*CAP +0 ropt_mt_inst_835:X 1e-06 +1 ropt_mt_inst_874:A 1e-06 +2 ropt_net_227:2 7.441475e-05 +3 ropt_net_227:3 7.441475e-05 +4 ropt_net_227:4 5.258996e-05 +5 ropt_net_227:5 5.258996e-05 +6 ropt_net_227:6 0.0001356122 +7 ropt_net_227:7 0.0001356122 +8 ropt_net_227:8 0.0001555305 +9 ropt_net_227:9 0.0001555305 +10 ropt_net_227:10 0.0002181087 +11 ropt_net_227:11 0.0002181087 +12 ropt_net_227:8 chany_bottom_in[9]:8 1.179747e-05 +13 ropt_net_227:10 chany_bottom_in[9]:7 5.68637e-05 +14 ropt_net_227:9 chany_bottom_in[9]:9 1.179747e-05 +15 ropt_net_227:11 chany_bottom_in[9]:6 5.68637e-05 + +*RES +0 ropt_mt_inst_835:X ropt_net_227:11 0.152 +1 ropt_net_227:2 ropt_mt_inst_874:A 0.152 +2 ropt_net_227:3 ropt_net_227:2 0.0007477679 +3 ropt_net_227:4 ropt_net_227:3 0.0045 +4 ropt_net_227:6 ropt_net_227:5 0.0045 +5 ropt_net_227:5 ropt_net_227:4 0.0005267857 +6 ropt_net_227:7 ropt_net_227:6 0.0015625 +7 ropt_net_227:8 ropt_net_227:7 0.0045 +8 ropt_net_227:10 ropt_net_227:9 0.0045 +9 ropt_net_227:9 ropt_net_227:8 0.002348214 +10 ropt_net_227:11 ropt_net_227:10 0.003386161 + +*END + +*D_NET ropt_net_245 0.0006425768 //LENGTH 4.420 LUMPCC 0.000194845 DR + +*CONN +*I BUFT_P_127:X O *L 0 *C 91.080 126.820 +*I ropt_mt_inst_899:A I *L 0.001766 *C 94.760 126.480 +*N ropt_net_245:2 *C 94.760 126.480 +*N ropt_net_245:3 *C 94.760 126.820 +*N ropt_net_245:4 *C 91.118 126.820 + +*CAP +0 BUFT_P_127:X 1e-06 +1 ropt_mt_inst_899:A 1e-06 +2 ropt_net_245:2 5.620049e-05 +3 ropt_net_245:3 0.0002085824 +4 ropt_net_245:4 0.0001809489 +5 ropt_net_245:4 chany_bottom_in[17]:5 9.742248e-05 +6 ropt_net_245:3 chany_bottom_in[17]:6 9.742248e-05 + +*RES +0 BUFT_P_127:X ropt_net_245:4 0.152 +1 ropt_net_245:4 ropt_net_245:3 0.003252232 +2 ropt_net_245:2 ropt_mt_inst_899:A 0.152 +3 ropt_net_245:3 ropt_net_245:2 0.0003035715 + +*END + +*D_NET ropt_net_229 0.00237513 //LENGTH 17.730 LUMPCC 0.0006952386 DR + +*CONN +*I ropt_mt_inst_840:X O *L 0 *C 57.245 8.840 +*I ropt_mt_inst_876:A I *L 0.001766 *C 49.680 4.080 +*N ropt_net_229:2 *C 49.680 4.080 +*N ropt_net_229:3 *C 49.680 4.035 +*N ropt_net_229:4 *C 49.680 2.098 +*N ropt_net_229:5 *C 49.688 2.040 +*N ropt_net_229:6 *C 56.573 2.040 +*N ropt_net_229:7 *C 56.580 2.098 +*N ropt_net_229:8 *C 56.580 8.795 +*N ropt_net_229:9 *C 56.625 8.840 +*N ropt_net_229:10 *C 57.208 8.840 + +*CAP +0 ropt_mt_inst_840:X 1e-06 +1 ropt_mt_inst_876:A 1e-06 +2 ropt_net_229:2 3.181869e-05 +3 ropt_net_229:3 0.0001260377 +4 ropt_net_229:4 0.0001260377 +5 ropt_net_229:5 0.0003267395 +6 ropt_net_229:6 0.0003267395 +7 ropt_net_229:7 0.0003119967 +8 ropt_net_229:8 0.0003119968 +9 ropt_net_229:9 5.826204e-05 +10 ropt_net_229:10 5.826204e-05 +11 ropt_net_229:7 chany_bottom_in[18] 3.74803e-05 +12 ropt_net_229:7 chany_bottom_in[18]:47 7.675767e-05 +13 ropt_net_229:9 chany_bottom_in[18]:47 5.180489e-06 +14 ropt_net_229:8 chany_bottom_in[18]:46 7.675767e-05 +15 ropt_net_229:8 chany_bottom_in[18]:48 3.74803e-05 +16 ropt_net_229:10 chany_bottom_in[18]:48 5.180489e-06 +17 ropt_net_229:5 chany_bottom_in[15]:21 0.0002282009 +18 ropt_net_229:6 chany_bottom_in[15]:22 0.0002282009 + +*RES +0 ropt_mt_inst_840:X ropt_net_229:10 0.152 +1 ropt_net_229:2 ropt_mt_inst_876:A 0.152 +2 ropt_net_229:3 ropt_net_229:2 0.0045 +3 ropt_net_229:4 ropt_net_229:3 0.001729911 +4 ropt_net_229:5 ropt_net_229:4 0.00341 +5 ropt_net_229:7 ropt_net_229:6 0.00341 +6 ropt_net_229:6 ropt_net_229:5 0.00107865 +7 ropt_net_229:9 ropt_net_229:8 0.0045 +8 ropt_net_229:8 ropt_net_229:7 0.005979911 +9 ropt_net_229:10 ropt_net_229:9 0.0005200893 + +*END + +*D_NET chany_bottom_out[19] 0.001528769 //LENGTH 11.625 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_893:X O *L 0 *C 76.190 6.460 +*P chany_bottom_out[19] O *L 0.7423 *C 70.840 1.290 +*N chany_bottom_out[19]:2 *C 70.840 1.995 +*N chany_bottom_out[19]:3 *C 70.885 2.040 +*N chany_bottom_out[19]:4 *C 74.475 2.040 +*N chany_bottom_out[19]:5 *C 74.520 2.085 +*N chany_bottom_out[19]:6 *C 74.520 6.415 +*N chany_bottom_out[19]:7 *C 74.565 6.460 +*N chany_bottom_out[19]:8 *C 76.153 6.460 + +*CAP +0 ropt_mt_inst_893:X 1e-06 +1 chany_bottom_out[19] 5.855492e-05 +2 chany_bottom_out[19]:2 5.855492e-05 +3 chany_bottom_out[19]:3 0.0002667329 +4 chany_bottom_out[19]:4 0.0002667329 +5 chany_bottom_out[19]:5 0.0003111742 +6 chany_bottom_out[19]:6 0.0003111742 +7 chany_bottom_out[19]:7 0.0001274228 +8 chany_bottom_out[19]:8 0.0001274228 + +*RES +0 ropt_mt_inst_893:X chany_bottom_out[19]:8 0.152 +1 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.0045 +2 chany_bottom_out[19]:2 chany_bottom_out[19] 0.0006294643 +3 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.003205357 +4 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.0045 +5 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.0045 +6 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.003866072 +7 chany_bottom_out[19]:8 chany_bottom_out[19]:7 0.001417411 + +*END + +*D_NET chany_top_in[16] 0.02444304 //LENGTH 169.580 LUMPCC 0.00655807 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 69.460 129.270 +*I mux_left_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 70.745 69.020 +*I mux_right_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 104.980 69.020 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 76.075 31.620 +*I FTB_11__10:A I *L 0.001776 *C 69.000 9.520 +*N chany_top_in[16]:5 *C 69.038 9.520 +*N chany_top_in[16]:6 *C 70.335 9.520 +*N chany_top_in[16]:7 *C 70.380 9.565 +*N chany_top_in[16]:8 *C 70.380 16.262 +*N chany_top_in[16]:9 *C 70.388 16.320 +*N chany_top_in[16]:10 *C 73.593 16.320 +*N chany_top_in[16]:11 *C 73.600 16.378 +*N chany_top_in[16]:12 *C 73.600 31.620 +*N chany_top_in[16]:13 *C 76.038 31.620 +*N chany_top_in[16]:14 *C 74.105 31.620 +*N chany_top_in[16]:15 *C 74.060 31.665 +*N chany_top_in[16]:16 *C 104.880 69.020 +*N chany_top_in[16]:17 *C 104.880 69.020 +*N chany_top_in[16]:18 *C 104.880 68.680 +*N chany_top_in[16]:19 *C 104.873 68.680 +*N chany_top_in[16]:20 *C 74.068 68.680 +*N chany_top_in[16]:21 *C 70.782 69.020 +*N chany_top_in[16]:22 *C 74.060 69.020 +*N chany_top_in[16]:23 *C 74.060 68.680 +*N chany_top_in[16]:24 *C 74.060 68.680 +*N chany_top_in[16]:25 *C 74.060 93.500 +*N chany_top_in[16]:26 *C 73.600 93.500 +*N chany_top_in[16]:27 *C 73.600 107.735 +*N chany_top_in[16]:28 *C 73.555 107.780 +*N chany_top_in[16]:29 *C 69.505 107.780 +*N chany_top_in[16]:30 *C 69.460 107.825 + +*CAP +0 chany_top_in[16] 0.001233312 +1 mux_left_track_9\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +4 FTB_11__10:A 1e-06 +5 chany_top_in[16]:5 9.720563e-05 +6 chany_top_in[16]:6 9.720563e-05 +7 chany_top_in[16]:7 0.0004226394 +8 chany_top_in[16]:8 0.0004226394 +9 chany_top_in[16]:9 0.0002718992 +10 chany_top_in[16]:10 0.0002718992 +11 chany_top_in[16]:11 0.0009357891 +12 chany_top_in[16]:12 0.0009714664 +13 chany_top_in[16]:13 0.0001348202 +14 chany_top_in[16]:14 0.0001348202 +15 chany_top_in[16]:15 0.001912026 +16 chany_top_in[16]:16 3.142752e-05 +17 chany_top_in[16]:17 5.356044e-05 +18 chany_top_in[16]:18 5.764819e-05 +19 chany_top_in[16]:19 0.001276189 +20 chany_top_in[16]:20 0.001276189 +21 chany_top_in[16]:21 0.0002479292 +22 chany_top_in[16]:22 0.0002790292 +23 chany_top_in[16]:23 6.808797e-05 +24 chany_top_in[16]:24 0.003287527 +25 chany_top_in[16]:25 0.001403902 +26 chany_top_in[16]:26 0.0006125408 +27 chany_top_in[16]:27 0.0005816577 +28 chany_top_in[16]:28 0.0002831232 +29 chany_top_in[16]:29 0.0002831232 +30 chany_top_in[16]:30 0.001233312 +31 chany_top_in[16] chany_top_in[10] 4.455571e-07 +32 chany_top_in[16]:24 chany_top_in[10]:26 2.155906e-06 +33 chany_top_in[16]:24 chany_top_in[10]:29 1.05239e-06 +34 chany_top_in[16]:24 chany_top_in[10]:31 0.0001285834 +35 chany_top_in[16]:27 chany_top_in[10]:32 0.0003746614 +36 chany_top_in[16]:30 chany_top_in[10]:39 4.455571e-07 +37 chany_top_in[16]:26 chany_top_in[10]:31 0.0003746614 +38 chany_top_in[16]:25 chany_top_in[10]:29 2.155906e-06 +39 chany_top_in[16]:25 chany_top_in[10]:30 1.05239e-06 +40 chany_top_in[16]:25 chany_top_in[10]:32 0.0001285834 +41 chany_top_in[16]:24 chany_top_in[18]:21 0.0002801951 +42 chany_top_in[16]:24 chany_top_in[18]:20 0.0001334599 +43 chany_top_in[16]:11 chany_top_in[18]:13 2.197335e-07 +44 chany_top_in[16]:15 chany_top_in[18]:20 0.0002801951 +45 chany_top_in[16]:15 chany_top_in[18]:17 0.0001334599 +46 chany_top_in[16]:12 chany_top_in[18]:14 2.197335e-07 +47 chany_top_in[16]:21 chanx_right_in[6]:13 2.054851e-06 +48 chany_top_in[16]:20 chanx_right_in[6]:29 0.0002912218 +49 chany_top_in[16]:19 chanx_right_in[6]:30 0.0002912218 +50 chany_top_in[16]:22 chanx_right_in[6]:14 2.054851e-06 +51 chany_top_in[16]:20 chanx_left_in[10]:25 0.0001797358 +52 chany_top_in[16]:20 chanx_left_in[10]:24 0.0004773485 +53 chany_top_in[16]:19 chanx_left_in[10]:23 0.0004773485 +54 chany_top_in[16]:19 chanx_left_in[10]:24 0.0001797358 +55 chany_top_in[16]:20 chanx_left_in[18]:20 0.001205951 +56 chany_top_in[16]:19 chanx_left_in[18]:19 0.001205951 +57 chany_top_in[16] mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.909715e-05 +58 chany_top_in[16]:30 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.909715e-05 +59 chany_top_in[16]:24 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.549837e-05 +60 chany_top_in[16]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.549837e-05 +61 chany_top_in[16]:24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.735419e-05 +62 chany_top_in[16]:25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.735419e-05 + +*RES +0 chany_top_in[16] chany_top_in[16]:30 0.01914732 +1 chany_top_in[16]:23 chany_top_in[16]:22 0.0003035715 +2 chany_top_in[16]:24 chany_top_in[16]:23 0.0045 +3 chany_top_in[16]:24 chany_top_in[16]:20 0.00341 +4 chany_top_in[16]:24 chany_top_in[16]:15 0.03304911 +5 chany_top_in[16]:21 mux_left_track_9\/mux_l1_in_1_:A1 0.152 +6 chany_top_in[16]:20 chany_top_in[16]:19 0.004826116 +7 chany_top_in[16]:18 chany_top_in[16]:17 0.0001634616 +8 chany_top_in[16]:19 chany_top_in[16]:18 0.00341 +9 chany_top_in[16]:16 mux_right_track_8\/mux_l1_in_1_:A1 0.152 +10 chany_top_in[16]:17 chany_top_in[16]:16 0.0045 +11 chany_top_in[16]:11 chany_top_in[16]:10 0.00341 +12 chany_top_in[16]:10 chany_top_in[16]:9 0.0005021166 +13 chany_top_in[16]:8 chany_top_in[16]:7 0.00597991 +14 chany_top_in[16]:9 chany_top_in[16]:8 0.00341 +15 chany_top_in[16]:6 chany_top_in[16]:5 0.001158482 +16 chany_top_in[16]:7 chany_top_in[16]:6 0.0045 +17 chany_top_in[16]:5 FTB_11__10:A 0.152 +18 chany_top_in[16]:28 chany_top_in[16]:27 0.0045 +19 chany_top_in[16]:27 chany_top_in[16]:26 0.01270982 +20 chany_top_in[16]:29 chany_top_in[16]:28 0.003616072 +21 chany_top_in[16]:30 chany_top_in[16]:29 0.0045 +22 chany_top_in[16]:14 chany_top_in[16]:13 0.001725447 +23 chany_top_in[16]:15 chany_top_in[16]:14 0.0045 +24 chany_top_in[16]:15 chany_top_in[16]:12 0.0004107143 +25 chany_top_in[16]:13 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +26 chany_top_in[16]:22 chany_top_in[16]:21 0.002926339 +27 chany_top_in[16]:12 chany_top_in[16]:11 0.01360938 +28 chany_top_in[16]:26 chany_top_in[16]:25 0.0004107143 +29 chany_top_in[16]:25 chany_top_in[16]:24 0.02216072 + +*END + +*D_NET top_left_grid_pin_34_[0] 0.006403734 //LENGTH 46.125 LUMPCC 0.0006498763 DR + +*CONN +*P top_left_grid_pin_34_[0] I *L 0.29796 *C 31.740 129.270 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.280 115.940 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 56.680 117.980 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.465 126.820 +*N top_left_grid_pin_34_[0]:4 *C 39.465 126.820 +*N top_left_grid_pin_34_[0]:5 *C 56.643 117.980 +*N top_left_grid_pin_34_[0]:6 *C 61.280 115.940 +*N top_left_grid_pin_34_[0]:7 *C 61.180 116.280 +*N top_left_grid_pin_34_[0]:8 *C 56.165 116.280 +*N top_left_grid_pin_34_[0]:9 *C 56.120 116.325 +*N top_left_grid_pin_34_[0]:10 *C 56.120 117.935 +*N top_left_grid_pin_34_[0]:11 *C 56.120 117.980 +*N top_left_grid_pin_34_[0]:12 *C 56.120 118.320 +*N top_left_grid_pin_34_[0]:13 *C 53.405 118.320 +*N top_left_grid_pin_34_[0]:14 *C 53.360 118.365 +*N top_left_grid_pin_34_[0]:15 *C 53.360 127.115 +*N top_left_grid_pin_34_[0]:16 *C 53.315 127.160 +*N top_left_grid_pin_34_[0]:17 *C 39.560 127.160 +*N top_left_grid_pin_34_[0]:18 *C 31.785 127.160 +*N top_left_grid_pin_34_[0]:19 *C 31.740 127.205 + +*CAP +0 top_left_grid_pin_34_[0] 0.0001315864 +1 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_34_[0]:4 4.99312e-05 +5 top_left_grid_pin_34_[0]:5 5.361529e-05 +6 top_left_grid_pin_34_[0]:6 5.610883e-05 +7 top_left_grid_pin_34_[0]:7 0.0003865784 +8 top_left_grid_pin_34_[0]:8 0.0003589541 +9 top_left_grid_pin_34_[0]:9 0.0001252724 +10 top_left_grid_pin_34_[0]:10 0.0001252724 +11 top_left_grid_pin_34_[0]:11 8.334104e-05 +12 top_left_grid_pin_34_[0]:12 0.0002406051 +13 top_left_grid_pin_34_[0]:13 0.0002108794 +14 top_left_grid_pin_34_[0]:14 0.0005450542 +15 top_left_grid_pin_34_[0]:15 0.0005450542 +16 top_left_grid_pin_34_[0]:16 0.0008836932 +17 top_left_grid_pin_34_[0]:17 0.001365829 +18 top_left_grid_pin_34_[0]:18 0.0004574953 +19 top_left_grid_pin_34_[0]:19 0.0001315864 +20 top_left_grid_pin_34_[0]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001206198 +21 top_left_grid_pin_34_[0]:17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001206198 +22 top_left_grid_pin_34_[0]:14 ropt_net_191:6 1.899117e-07 +23 top_left_grid_pin_34_[0]:16 ropt_net_191:8 0.0001624836 +24 top_left_grid_pin_34_[0]:15 ropt_net_191:7 1.899117e-07 +25 top_left_grid_pin_34_[0]:17 ropt_net_191:9 0.0001624836 +26 top_left_grid_pin_34_[0]:14 ropt_net_219:9 4.164482e-05 +27 top_left_grid_pin_34_[0]:15 ropt_net_219:8 4.164482e-05 + +*RES +0 top_left_grid_pin_34_[0] top_left_grid_pin_34_[0]:19 0.00184375 +1 top_left_grid_pin_34_[0]:13 top_left_grid_pin_34_[0]:12 0.002424107 +2 top_left_grid_pin_34_[0]:14 top_left_grid_pin_34_[0]:13 0.0045 +3 top_left_grid_pin_34_[0]:16 top_left_grid_pin_34_[0]:15 0.0045 +4 top_left_grid_pin_34_[0]:15 top_left_grid_pin_34_[0]:14 0.0078125 +5 top_left_grid_pin_34_[0]:11 top_left_grid_pin_34_[0]:10 0.0045 +6 top_left_grid_pin_34_[0]:11 top_left_grid_pin_34_[0]:5 0.0004665179 +7 top_left_grid_pin_34_[0]:10 top_left_grid_pin_34_[0]:9 0.0014375 +8 top_left_grid_pin_34_[0]:8 top_left_grid_pin_34_[0]:7 0.004477679 +9 top_left_grid_pin_34_[0]:9 top_left_grid_pin_34_[0]:8 0.0045 +10 top_left_grid_pin_34_[0]:6 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +11 top_left_grid_pin_34_[0]:4 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +12 top_left_grid_pin_34_[0]:5 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +13 top_left_grid_pin_34_[0]:18 top_left_grid_pin_34_[0]:17 0.006941965 +14 top_left_grid_pin_34_[0]:19 top_left_grid_pin_34_[0]:18 0.0045 +15 top_left_grid_pin_34_[0]:17 top_left_grid_pin_34_[0]:16 0.01228125 +16 top_left_grid_pin_34_[0]:17 top_left_grid_pin_34_[0]:4 0.0003035715 +17 top_left_grid_pin_34_[0]:12 top_left_grid_pin_34_[0]:11 0.0003035715 +18 top_left_grid_pin_34_[0]:7 top_left_grid_pin_34_[0]:6 0.0003035715 + +*END + +*D_NET chanx_right_in[7] 0.02413611 //LENGTH 156.735 LUMPCC 0.00822719 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 140.450 69.360 +*I mux_bottom_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 37.260 39.780 +*I mux_top_track_4\/mux_l2_in_4_:A1 I *L 0.00198 *C 38.740 85.340 +*N chanx_right_in[7]:3 *C 38.703 85.340 +*N chanx_right_in[7]:4 *C 38.225 85.340 +*N chanx_right_in[7]:5 *C 38.180 85.295 +*N chanx_right_in[7]:6 *C 38.180 83.698 +*N chanx_right_in[7]:7 *C 38.183 83.640 +*N chanx_right_in[7]:8 *C 38.625 83.640 +*N chanx_right_in[7]:9 *C 38.640 83.633 +*N chanx_right_in[7]:10 *C 37.260 39.780 +*N chanx_right_in[7]:11 *C 37.260 39.825 +*N chanx_right_in[7]:12 *C 37.260 40.742 +*N chanx_right_in[7]:13 *C 37.267 40.800 +*N chanx_right_in[7]:14 *C 38.620 40.800 +*N chanx_right_in[7]:15 *C 38.640 40.808 +*N chanx_right_in[7]:16 *C 38.640 72.760 +*N chanx_right_in[7]:17 *C 38.660 72.760 +*N chanx_right_in[7]:18 *C 88.450 72.760 +*N chanx_right_in[7]:19 *C 108.093 72.760 +*N chanx_right_in[7]:20 *C 108.100 72.703 +*N chanx_right_in[7]:21 *C 108.100 71.785 +*N chanx_right_in[7]:22 *C 108.145 71.740 +*N chanx_right_in[7]:23 *C 111.275 71.740 +*N chanx_right_in[7]:24 *C 111.320 71.695 +*N chanx_right_in[7]:25 *C 111.320 69.418 +*N chanx_right_in[7]:26 *C 111.328 69.360 + +*CAP +0 chanx_right_in[7] 0.001221336 +1 mux_bottom_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_4\/mux_l2_in_4_:A1 1e-06 +3 chanx_right_in[7]:3 5.397136e-05 +4 chanx_right_in[7]:4 5.397136e-05 +5 chanx_right_in[7]:5 9.992087e-05 +6 chanx_right_in[7]:6 9.992087e-05 +7 chanx_right_in[7]:7 6.020947e-05 +8 chanx_right_in[7]:8 6.020947e-05 +9 chanx_right_in[7]:9 0.0005793778 +10 chanx_right_in[7]:10 3.141717e-05 +11 chanx_right_in[7]:11 7.171564e-05 +12 chanx_right_in[7]:12 7.171564e-05 +13 chanx_right_in[7]:13 0.0001250299 +14 chanx_right_in[7]:14 0.0001250299 +15 chanx_right_in[7]:15 0.001899961 +16 chanx_right_in[7]:16 0.002479339 +17 chanx_right_in[7]:17 0.00272315 +18 chanx_right_in[7]:18 0.003432261 +19 chanx_right_in[7]:19 0.0007091118 +20 chanx_right_in[7]:20 7.578282e-05 +21 chanx_right_in[7]:21 7.578282e-05 +22 chanx_right_in[7]:22 0.00020949 +23 chanx_right_in[7]:23 0.00020949 +24 chanx_right_in[7]:24 0.0001086983 +25 chanx_right_in[7]:25 0.0001086983 +26 chanx_right_in[7]:26 0.001221336 +27 chanx_right_in[7] chanx_left_in[5]:15 0.0004894849 +28 chanx_right_in[7]:24 chanx_left_in[5]:18 3.156308e-05 +29 chanx_right_in[7]:25 chanx_left_in[5]:17 3.156308e-05 +30 chanx_right_in[7]:26 chanx_left_in[5]:16 0.0004894849 +31 chanx_right_in[7]:17 chanx_left_in[9]:26 0.0006192823 +32 chanx_right_in[7]:19 chanx_left_in[9]:25 8.146982e-06 +33 chanx_right_in[7]:18 chanx_left_in[9]:25 0.0006192823 +34 chanx_right_in[7]:18 chanx_left_in[9]:26 8.146982e-06 +35 chanx_right_in[7] chanx_left_in[18]:15 8.590391e-05 +36 chanx_right_in[7]:19 chanx_left_in[18]:15 0.0001826541 +37 chanx_right_in[7]:26 chanx_left_in[18]:16 8.590391e-05 +38 chanx_right_in[7]:18 chanx_left_in[18]:16 0.0001826541 +39 chanx_right_in[7]:15 chanx_left_in[19]:11 0.0002087616 +40 chanx_right_in[7]:16 chanx_left_in[19]:11 0.0001202451 +41 chanx_right_in[7]:16 chanx_left_in[19]:10 0.0002087616 +42 chanx_right_in[7]:9 chanx_left_in[19]:10 0.0001202451 +43 chanx_right_in[7]:17 mux_tree_tapbuf_size10_9_sram[0]:20 6.68483e-05 +44 chanx_right_in[7]:17 mux_tree_tapbuf_size10_9_sram[0]:18 3.236349e-05 +45 chanx_right_in[7]:17 mux_tree_tapbuf_size10_9_sram[0]:16 0.000263874 +46 chanx_right_in[7]:17 mux_tree_tapbuf_size10_9_sram[0]:14 0.0003449331 +47 chanx_right_in[7]:18 mux_tree_tapbuf_size10_9_sram[0]:13 0.0003449331 +48 chanx_right_in[7]:18 mux_tree_tapbuf_size10_9_sram[0]:19 6.68483e-05 +49 chanx_right_in[7]:18 mux_tree_tapbuf_size10_9_sram[0]:17 3.236349e-05 +50 chanx_right_in[7]:18 mux_tree_tapbuf_size10_9_sram[0]:15 0.000263874 +51 chanx_right_in[7]:17 mux_tree_tapbuf_size7_1_sram[0]:26 8.692175e-05 +52 chanx_right_in[7]:20 mux_tree_tapbuf_size7_1_sram[0]:33 6.278233e-08 +53 chanx_right_in[7]:19 mux_tree_tapbuf_size7_1_sram[0]:27 0.0005052456 +54 chanx_right_in[7]:21 mux_tree_tapbuf_size7_1_sram[0]:32 6.278233e-08 +55 chanx_right_in[7]:18 mux_tree_tapbuf_size7_1_sram[0]:27 8.692175e-05 +56 chanx_right_in[7]:18 mux_tree_tapbuf_size7_1_sram[0]:26 0.0005052456 +57 chanx_right_in[7]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.068853e-05 +58 chanx_right_in[7]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.068853e-05 +59 chanx_right_in[7] mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 2.072701e-05 +60 chanx_right_in[7]:17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0002786385 +61 chanx_right_in[7]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.500462e-06 +62 chanx_right_in[7]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0005044727 +63 chanx_right_in[7]:19 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001926118 +64 chanx_right_in[7]:22 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 5.463859e-06 +65 chanx_right_in[7]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 6.500462e-06 +66 chanx_right_in[7]:23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 5.463859e-06 +67 chanx_right_in[7]:24 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.200679e-06 +68 chanx_right_in[7]:25 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.200679e-06 +69 chanx_right_in[7]:26 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 2.072701e-05 +70 chanx_right_in[7]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0005044727 +71 chanx_right_in[7]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0002786385 +72 chanx_right_in[7]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001926118 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:26 0.004562525 +1 chanx_right_in[7]:14 chanx_right_in[7]:13 0.0002118916 +2 chanx_right_in[7]:15 chanx_right_in[7]:14 0.00341 +3 chanx_right_in[7]:12 chanx_right_in[7]:11 0.0008191965 +4 chanx_right_in[7]:13 chanx_right_in[7]:12 0.00341 +5 chanx_right_in[7]:10 mux_bottom_track_5\/mux_l2_in_1_:A1 0.152 +6 chanx_right_in[7]:11 chanx_right_in[7]:10 0.0045 +7 chanx_right_in[7]:17 chanx_right_in[7]:16 0.00341 +8 chanx_right_in[7]:16 chanx_right_in[7]:15 0.005005891 +9 chanx_right_in[7]:16 chanx_right_in[7]:9 0.001703358 +10 chanx_right_in[7]:20 chanx_right_in[7]:19 0.00341 +11 chanx_right_in[7]:19 chanx_right_in[7]:18 0.003077325 +12 chanx_right_in[7]:22 chanx_right_in[7]:21 0.0045 +13 chanx_right_in[7]:21 chanx_right_in[7]:20 0.0008191965 +14 chanx_right_in[7]:23 chanx_right_in[7]:22 0.002794643 +15 chanx_right_in[7]:24 chanx_right_in[7]:23 0.0045 +16 chanx_right_in[7]:25 chanx_right_in[7]:24 0.002033482 +17 chanx_right_in[7]:26 chanx_right_in[7]:25 0.00341 +18 chanx_right_in[7]:8 chanx_right_in[7]:7 6.499219e-05 +19 chanx_right_in[7]:9 chanx_right_in[7]:8 0.00341 +20 chanx_right_in[7]:6 chanx_right_in[7]:5 0.001426339 +21 chanx_right_in[7]:7 chanx_right_in[7]:6 0.00341 +22 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0004263393 +23 chanx_right_in[7]:5 chanx_right_in[7]:4 0.0045 +24 chanx_right_in[7]:3 mux_top_track_4\/mux_l2_in_4_:A1 0.152 +25 chanx_right_in[7]:18 chanx_right_in[7]:17 0.007800432 + +*END + +*D_NET chany_bottom_in[3] 0.01952258 //LENGTH 117.635 LUMPCC 0.007944242 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 88.320 1.290 +*I mux_right_track_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 101.835 65.960 +*I mux_left_track_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 66.990 71.740 +*N chany_bottom_in[3]:3 *C 67.028 71.740 +*N chany_bottom_in[3]:4 *C 68.495 71.740 +*N chany_bottom_in[3]:5 *C 68.540 71.695 +*N chany_bottom_in[3]:6 *C 68.540 70.778 +*N chany_bottom_in[3]:7 *C 68.547 70.720 +*N chany_bottom_in[3]:8 *C 71.300 70.720 +*N chany_bottom_in[3]:9 *C 71.300 71.400 +*N chany_bottom_in[3]:10 *C 79.112 71.400 +*N chany_bottom_in[3]:11 *C 79.120 71.458 +*N chany_bottom_in[3]:12 *C 79.120 72.375 +*N chany_bottom_in[3]:13 *C 79.165 72.420 +*N chany_bottom_in[3]:14 *C 82.295 72.420 +*N chany_bottom_in[3]:15 *C 82.340 72.375 +*N chany_bottom_in[3]:16 *C 82.340 71.458 +*N chany_bottom_in[3]:17 *C 82.348 71.400 +*N chany_bottom_in[3]:18 *C 91.060 71.400 +*N chany_bottom_in[3]:19 *C 91.080 71.392 +*N chany_bottom_in[3]:20 *C 101.797 65.960 +*N chany_bottom_in[3]:21 *C 100.785 65.960 +*N chany_bottom_in[3]:22 *C 100.740 66.005 +*N chany_bottom_in[3]:23 *C 100.740 67.263 +*N chany_bottom_in[3]:24 *C 100.733 67.320 +*N chany_bottom_in[3]:25 *C 91.100 67.320 +*N chany_bottom_in[3]:26 *C 91.080 67.320 +*N chany_bottom_in[3]:27 *C 91.080 16.328 +*N chany_bottom_in[3]:28 *C 91.060 16.320 +*N chany_bottom_in[3]:29 *C 88.328 16.320 +*N chany_bottom_in[3]:30 *C 88.320 16.262 + +*CAP +0 chany_bottom_in[3] 0.0006460401 +1 mux_right_track_8\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_9\/mux_l1_in_2_:A0 1e-06 +3 chany_bottom_in[3]:3 0.0001513693 +4 chany_bottom_in[3]:4 0.0001513693 +5 chany_bottom_in[3]:5 9.628425e-05 +6 chany_bottom_in[3]:6 9.628425e-05 +7 chany_bottom_in[3]:7 0.0002643802 +8 chany_bottom_in[3]:8 0.0003422359 +9 chany_bottom_in[3]:9 0.0008309924 +10 chany_bottom_in[3]:10 0.0007531368 +11 chany_bottom_in[3]:11 9.077344e-05 +12 chany_bottom_in[3]:12 9.077344e-05 +13 chany_bottom_in[3]:13 0.000238405 +14 chany_bottom_in[3]:14 0.000238405 +15 chany_bottom_in[3]:15 9.960526e-05 +16 chany_bottom_in[3]:16 9.960526e-05 +17 chany_bottom_in[3]:17 0.0005456908 +18 chany_bottom_in[3]:18 0.0005456908 +19 chany_bottom_in[3]:19 0.0002791233 +20 chany_bottom_in[3]:20 9.235486e-05 +21 chany_bottom_in[3]:21 9.235486e-05 +22 chany_bottom_in[3]:22 9.011507e-05 +23 chany_bottom_in[3]:23 9.011507e-05 +24 chany_bottom_in[3]:24 0.0004858413 +25 chany_bottom_in[3]:25 0.0004858413 +26 chany_bottom_in[3]:26 0.001939954 +27 chany_bottom_in[3]:27 0.00166083 +28 chany_bottom_in[3]:28 0.0002163651 +29 chany_bottom_in[3]:29 0.0002163651 +30 chany_bottom_in[3]:30 0.0006460401 +31 chany_bottom_in[3]:27 chany_top_in[2]:22 0.0007637984 +32 chany_bottom_in[3]:19 chany_top_in[2]:23 7.16236e-05 +33 chany_bottom_in[3]:26 chany_top_in[2]:22 7.16236e-05 +34 chany_bottom_in[3]:26 chany_top_in[2]:23 0.0007637984 +35 chany_bottom_in[3]:25 chanx_left_in[18]:20 0.0003282011 +36 chany_bottom_in[3]:24 chanx_left_in[18]:19 0.0003282011 +37 chany_bottom_in[3] chany_bottom_in[11]:16 1.409075e-05 +38 chany_bottom_in[3]:27 chany_bottom_in[11]:16 0.001514212 +39 chany_bottom_in[3]:27 chany_bottom_in[11]:14 0.0001352103 +40 chany_bottom_in[3]:27 chany_bottom_in[11]:15 0.000348856 +41 chany_bottom_in[3]:30 chany_bottom_in[11]:15 1.409075e-05 +42 chany_bottom_in[3]:19 chany_bottom_in[11]:8 3.450404e-05 +43 chany_bottom_in[3]:26 chany_bottom_in[11]:14 0.0003833601 +44 chany_bottom_in[3]:26 chany_bottom_in[11]:8 0.0001352103 +45 chany_bottom_in[3]:26 chany_bottom_in[11]:15 0.001514212 +46 chany_bottom_in[3] mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 6.473901e-05 +47 chany_bottom_in[3]:30 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 6.473901e-05 +48 chany_bottom_in[3] mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 9.788699e-05 +49 chany_bottom_in[3]:30 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 9.788699e-05 +50 chany_bottom_in[3]:18 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0004259025 +51 chany_bottom_in[3]:17 mux_right_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0004259025 +52 chany_bottom_in[3]:25 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001693417 +53 chany_bottom_in[3]:23 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.754332e-06 +54 chany_bottom_in[3]:24 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001693417 +55 chany_bottom_in[3]:22 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.754332e-06 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:30 0.0133683 +1 chany_bottom_in[3]:28 chany_bottom_in[3]:27 0.00341 +2 chany_bottom_in[3]:27 chany_bottom_in[3]:26 0.007988825 +3 chany_bottom_in[3]:30 chany_bottom_in[3]:29 0.00341 +4 chany_bottom_in[3]:29 chany_bottom_in[3]:28 0.0004280917 +5 chany_bottom_in[3]:18 chany_bottom_in[3]:17 0.001364958 +6 chany_bottom_in[3]:19 chany_bottom_in[3]:18 0.00341 +7 chany_bottom_in[3]:16 chany_bottom_in[3]:15 0.0008191965 +8 chany_bottom_in[3]:17 chany_bottom_in[3]:16 0.00341 +9 chany_bottom_in[3]:14 chany_bottom_in[3]:13 0.002794643 +10 chany_bottom_in[3]:15 chany_bottom_in[3]:14 0.0045 +11 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.0045 +12 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.0008191965 +13 chany_bottom_in[3]:11 chany_bottom_in[3]:10 0.00341 +14 chany_bottom_in[3]:10 chany_bottom_in[3]:9 0.001223958 +15 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.0008191965 +16 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.00341 +17 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.001310268 +18 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.0045 +19 chany_bottom_in[3]:3 mux_left_track_9\/mux_l1_in_2_:A0 0.152 +20 chany_bottom_in[3]:25 chany_bottom_in[3]:24 0.001509092 +21 chany_bottom_in[3]:26 chany_bottom_in[3]:25 0.00341 +22 chany_bottom_in[3]:26 chany_bottom_in[3]:19 0.0006380249 +23 chany_bottom_in[3]:23 chany_bottom_in[3]:22 0.001122768 +24 chany_bottom_in[3]:24 chany_bottom_in[3]:23 0.00341 +25 chany_bottom_in[3]:21 chany_bottom_in[3]:20 0.0009040179 +26 chany_bottom_in[3]:22 chany_bottom_in[3]:21 0.0045 +27 chany_bottom_in[3]:20 mux_right_track_8\/mux_l1_in_2_:A0 0.152 +28 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.000431225 +29 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.0001065333 + +*END + +*D_NET chanx_left_in[1] 0.02297007 //LENGTH 123.845 LUMPCC 0.01197739 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 38.080 +*I mux_bottom_track_1\/mux_l1_in_4_:A0 I *L 0.001631 *C 72.395 37.400 +*I mux_top_track_32\/mux_l1_in_2_:A0 I *L 0.001631 *C 82.055 76.840 +*N chanx_left_in[1]:3 *C 82.055 76.840 +*N chanx_left_in[1]:4 *C 81.880 76.840 +*N chanx_left_in[1]:5 *C 81.880 76.795 +*N chanx_left_in[1]:6 *C 81.880 70.778 +*N chanx_left_in[1]:7 *C 81.873 70.720 +*N chanx_left_in[1]:8 *C 76.380 70.720 +*N chanx_left_in[1]:9 *C 76.360 70.713 +*N chanx_left_in[1]:10 *C 76.360 40.128 +*N chanx_left_in[1]:11 *C 76.340 40.120 +*N chanx_left_in[1]:12 *C 72.228 40.120 +*N chanx_left_in[1]:13 *C 72.220 40.062 +*N chanx_left_in[1]:14 *C 72.395 37.400 +*N chanx_left_in[1]:15 *C 72.220 37.400 +*N chanx_left_in[1]:16 *C 72.220 37.445 +*N chanx_left_in[1]:17 *C 72.220 38.760 +*N chanx_left_in[1]:18 *C 72.213 38.760 +*N chanx_left_in[1]:19 *C 55.370 38.760 +*N chanx_left_in[1]:20 *C 5.520 38.760 +*N chanx_left_in[1]:21 *C 5.520 38.080 + +*CAP +0 chanx_left_in[1] 0.000208585 +1 mux_bottom_track_1\/mux_l1_in_4_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:A0 1e-06 +3 chanx_left_in[1]:3 5.674219e-05 +4 chanx_left_in[1]:4 6.152736e-05 +5 chanx_left_in[1]:5 0.0004154621 +6 chanx_left_in[1]:6 0.0004154621 +7 chanx_left_in[1]:7 0.0005874152 +8 chanx_left_in[1]:8 0.0005874152 +9 chanx_left_in[1]:9 0.001016146 +10 chanx_left_in[1]:10 0.001016146 +11 chanx_left_in[1]:11 0.0003384589 +12 chanx_left_in[1]:12 0.0003384589 +13 chanx_left_in[1]:13 8.223914e-05 +14 chanx_left_in[1]:14 4.785287e-05 +15 chanx_left_in[1]:15 5.352977e-05 +16 chanx_left_in[1]:16 8.09084e-05 +17 chanx_left_in[1]:17 0.0001968814 +18 chanx_left_in[1]:18 0.0006934597 +19 chanx_left_in[1]:19 0.002601711 +20 chanx_left_in[1]:20 0.00194597 +21 chanx_left_in[1]:21 0.000246304 +22 chanx_left_in[1]:20 chanx_right_in[14]:9 0.001437953 +23 chanx_left_in[1]:20 chanx_right_in[14]:14 0.0001130373 +24 chanx_left_in[1]:19 chanx_right_in[14]:14 0.001437953 +25 chanx_left_in[1]:19 chanx_right_in[14]:15 0.0001130373 +26 chanx_left_in[1]:9 chany_bottom_in[5]:27 1.479852e-05 +27 chanx_left_in[1]:9 chany_bottom_in[5]:31 0.0006674576 +28 chanx_left_in[1]:10 chany_bottom_in[5]:28 1.479852e-05 +29 chanx_left_in[1]:10 chany_bottom_in[5]:32 0.0006674576 +30 chanx_left_in[1] chanx_left_in[2] 8.442116e-06 +31 chanx_left_in[1]:18 chanx_left_in[2]:29 0.000293651 +32 chanx_left_in[1]:11 chanx_left_in[2]:29 1.8438e-05 +33 chanx_left_in[1]:12 chanx_left_in[2]:30 1.8438e-05 +34 chanx_left_in[1]:21 chanx_left_in[2]:33 8.442116e-06 +35 chanx_left_in[1]:20 chanx_left_in[2]:30 0.0002949454 +36 chanx_left_in[1]:19 chanx_left_in[2]:29 0.0002949454 +37 chanx_left_in[1]:19 chanx_left_in[2]:30 0.000293651 +38 chanx_left_in[1]:9 chany_bottom_in[19]:16 0.0005445902 +39 chanx_left_in[1]:9 chany_bottom_in[19]:17 0.0006566262 +40 chanx_left_in[1]:10 chany_bottom_in[19]:17 0.0005445902 +41 chanx_left_in[1]:10 chany_bottom_in[19]:18 0.0006566262 +42 chanx_left_in[1]:18 bottom_left_grid_pin_40_[0]:8 0.0008160236 +43 chanx_left_in[1]:15 bottom_left_grid_pin_40_[0]:5 2.947999e-06 +44 chanx_left_in[1]:14 bottom_left_grid_pin_40_[0]:4 2.947999e-06 +45 chanx_left_in[1]:20 bottom_left_grid_pin_40_[0]:13 0.00038321 +46 chanx_left_in[1]:20 bottom_left_grid_pin_40_[0]:14 0.0004248676 +47 chanx_left_in[1]:19 bottom_left_grid_pin_40_[0]:8 0.00038321 +48 chanx_left_in[1]:19 bottom_left_grid_pin_40_[0]:13 0.001240891 +49 chanx_left_in[1] chanx_left_in[3] 9.558913e-05 +50 chanx_left_in[1]:21 chanx_left_in[3]:15 2.350659e-05 +51 chanx_left_in[1]:21 chanx_left_in[3]:17 9.558913e-05 +52 chanx_left_in[1]:20 chanx_left_in[3] 0.000192611 +53 chanx_left_in[1]:20 chanx_left_in[3]:16 2.350659e-05 +54 chanx_left_in[1]:19 chanx_left_in[3]:17 0.000192611 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:21 0.0006721 +1 chanx_left_in[1]:17 chanx_left_in[1]:16 0.001174107 +2 chanx_left_in[1]:17 chanx_left_in[1]:13 0.001162947 +3 chanx_left_in[1]:18 chanx_left_in[1]:17 0.00341 +4 chanx_left_in[1]:15 chanx_left_in[1]:14 9.51087e-05 +5 chanx_left_in[1]:16 chanx_left_in[1]:15 0.0045 +6 chanx_left_in[1]:14 mux_bottom_track_1\/mux_l1_in_4_:A0 0.152 +7 chanx_left_in[1]:3 mux_top_track_32\/mux_l1_in_2_:A0 0.152 +8 chanx_left_in[1]:4 chanx_left_in[1]:3 9.510869e-05 +9 chanx_left_in[1]:5 chanx_left_in[1]:4 0.0045 +10 chanx_left_in[1]:6 chanx_left_in[1]:5 0.005372768 +11 chanx_left_in[1]:7 chanx_left_in[1]:6 0.00341 +12 chanx_left_in[1]:8 chanx_left_in[1]:7 0.0008604916 +13 chanx_left_in[1]:9 chanx_left_in[1]:8 0.00341 +14 chanx_left_in[1]:11 chanx_left_in[1]:10 0.00341 +15 chanx_left_in[1]:10 chanx_left_in[1]:9 0.00479165 +16 chanx_left_in[1]:13 chanx_left_in[1]:12 0.00341 +17 chanx_left_in[1]:12 chanx_left_in[1]:11 0.0006442916 +18 chanx_left_in[1]:21 chanx_left_in[1]:20 0.0001065333 +19 chanx_left_in[1]:20 chanx_left_in[1]:19 0.007809833 +20 chanx_left_in[1]:19 chanx_left_in[1]:18 0.002638658 + +*END + +*D_NET chany_top_out[2] 0.002366125 //LENGTH 17.345 LUMPCC 0.0001208537 DR + +*CONN +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 72.280 118.320 +*P chany_top_out[2] O *L 0.7423 *C 77.740 129.235 +*N chany_top_out[2]:2 *C 77.740 124.485 +*N chany_top_out[2]:3 *C 77.695 124.440 +*N chany_top_out[2]:4 *C 72.220 124.440 +*N chany_top_out[2]:5 *C 72.220 124.100 +*N chany_top_out[2]:6 *C 72.220 124.055 +*N chany_top_out[2]:7 *C 72.220 118.365 +*N chany_top_out[2]:8 *C 72.220 118.320 + +*CAP +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[2] 0.0002616761 +2 chany_top_out[2]:2 0.0002616761 +3 chany_top_out[2]:3 0.0003821904 +4 chany_top_out[2]:4 0.0004145004 +5 chany_top_out[2]:5 7.09093e-05 +6 chany_top_out[2]:6 0.000408288 +7 chany_top_out[2]:7 0.000408288 +8 chany_top_out[2]:8 3.674321e-05 +9 chany_top_out[2] ropt_net_208:5 4.807346e-06 +10 chany_top_out[2] ropt_net_208:7 2.379589e-06 +11 chany_top_out[2]:3 ropt_net_208:10 4.563655e-05 +12 chany_top_out[2]:3 ropt_net_208:7 7.603386e-06 +13 chany_top_out[2]:2 ropt_net_208:8 2.379589e-06 +14 chany_top_out[2]:2 ropt_net_208:6 4.807346e-06 +15 chany_top_out[2]:4 ropt_net_208:9 4.563655e-05 +16 chany_top_out[2]:4 ropt_net_208:6 7.603386e-06 + +*RES +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[2]:8 0.152 +1 chany_top_out[2]:8 chany_top_out[2]:7 0.0045 +2 chany_top_out[2]:7 chany_top_out[2]:6 0.005080357 +3 chany_top_out[2]:5 chany_top_out[2]:4 0.0003035715 +4 chany_top_out[2]:6 chany_top_out[2]:5 0.0045 +5 chany_top_out[2]:3 chany_top_out[2]:2 0.0045 +6 chany_top_out[2]:2 chany_top_out[2] 0.004241072 +7 chany_top_out[2]:4 chany_top_out[2]:3 0.004888393 + +*END + +*D_NET chanx_right_out[2] 0.0005954499 //LENGTH 4.905 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 138.060 60.860 +*P chanx_right_out[2] O *L 0.7423 *C 140.450 62.560 +*N chanx_right_out[2]:2 *C 138.468 62.560 +*N chanx_right_out[2]:3 *C 138.460 62.503 +*N chanx_right_out[2]:4 *C 138.460 60.905 +*N chanx_right_out[2]:5 *C 138.438 60.860 +*N chanx_right_out[2]:6 *C 138.075 60.860 + +*CAP +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[2] 0.000145709 +2 chanx_right_out[2]:2 0.000145709 +3 chanx_right_out[2]:3 0.0001101809 +4 chanx_right_out[2]:4 0.0001101809 +5 chanx_right_out[2]:5 4.1335e-05 +6 chanx_right_out[2]:6 4.1335e-05 + +*RES +0 mux_right_track_4\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[2]:6 0.152 +1 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +2 chanx_right_out[2]:2 chanx_right_out[2] 0.0003105917 +3 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0045 +4 chanx_right_out[2]:4 chanx_right_out[2]:3 0.001426339 +5 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0001970109 + +*END + +*D_NET chany_bottom_out[2] 0.0009073098 //LENGTH 7.645 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 48.360 4.420 +*P chany_bottom_out[2] O *L 0.7423 *C 52.440 1.290 +*N chany_bottom_out[2]:2 *C 52.440 4.375 +*N chany_bottom_out[2]:3 *C 52.395 4.420 +*N chany_bottom_out[2]:4 *C 48.360 4.420 + +*CAP +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[2] 0.0001870936 +2 chany_bottom_out[2]:2 0.0001870936 +3 chany_bottom_out[2]:3 0.0002510623 +4 chany_bottom_out[2]:4 0.0002810603 + +*RES +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[2]:4 0.152 +1 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.003602679 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +3 chany_bottom_out[2]:2 chany_bottom_out[2] 0.002754465 + +*END + +*D_NET chanx_left_out[8] 0.001545777 //LENGTH 10.465 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.235 47.940 +*P chanx_left_out[8] O *L 0.7423 *C 1.305 48.960 +*N chanx_left_out[8]:2 *C 5.520 48.960 +*N chanx_left_out[8]:3 *C 5.520 49.640 +*N chanx_left_out[8]:4 *C 8.273 49.640 +*N chanx_left_out[8]:5 *C 8.280 49.583 +*N chanx_left_out[8]:6 *C 8.280 47.985 +*N chanx_left_out[8]:7 *C 8.235 47.940 + +*CAP +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[8] 0.0003323969 +2 chanx_left_out[8]:2 0.0003921387 +3 chanx_left_out[8]:3 0.0003142628 +4 chanx_left_out[8]:4 0.0002545209 +5 chanx_left_out[8]:5 0.0001106133 +6 chanx_left_out[8]:6 0.0001106133 +7 chanx_left_out[8]:7 3.023149e-05 + +*RES +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[8]:7 0.152 +1 chanx_left_out[8]:7 chanx_left_out[8]:6 0.0045 +2 chanx_left_out[8]:6 chanx_left_out[8]:5 0.001426339 +3 chanx_left_out[8]:5 chanx_left_out[8]:4 0.00341 +4 chanx_left_out[8]:4 chanx_left_out[8]:3 0.000431225 +5 chanx_left_out[8]:2 chanx_left_out[8] 0.00066035 +6 chanx_left_out[8]:3 chanx_left_out[8]:2 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size10_11_sram[2] 0.002650895 //LENGTH 19.760 LUMPCC 0.0003755552 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.305 55.760 +*I mux_left_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 23.100 61.200 +*I mux_left_track_25\/mux_l3_in_1_:S I *L 0.00357 *C 18.960 61.200 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 13.055 58.820 +*N mux_tree_tapbuf_size10_11_sram[2]:4 *C 13.055 58.820 +*N mux_tree_tapbuf_size10_11_sram[2]:5 *C 12.880 58.820 +*N mux_tree_tapbuf_size10_11_sram[2]:6 *C 12.880 58.865 +*N mux_tree_tapbuf_size10_11_sram[2]:7 *C 12.880 60.815 +*N mux_tree_tapbuf_size10_11_sram[2]:8 *C 12.925 60.860 +*N mux_tree_tapbuf_size10_11_sram[2]:9 *C 17.480 60.860 +*N mux_tree_tapbuf_size10_11_sram[2]:10 *C 17.480 61.200 +*N mux_tree_tapbuf_size10_11_sram[2]:11 *C 18.960 61.200 +*N mux_tree_tapbuf_size10_11_sram[2]:12 *C 23.013 61.200 +*N mux_tree_tapbuf_size10_11_sram[2]:13 *C 23.000 61.155 +*N mux_tree_tapbuf_size10_11_sram[2]:14 *C 23.000 55.805 +*N mux_tree_tapbuf_size10_11_sram[2]:15 *C 23.000 55.760 +*N mux_tree_tapbuf_size10_11_sram[2]:16 *C 23.305 55.760 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:S 1e-06 +2 mux_left_track_25\/mux_l3_in_1_:S 1e-06 +3 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_11_sram[2]:4 5.59483e-05 +5 mux_tree_tapbuf_size10_11_sram[2]:5 5.877321e-05 +6 mux_tree_tapbuf_size10_11_sram[2]:6 0.0001214508 +7 mux_tree_tapbuf_size10_11_sram[2]:7 0.0001214508 +8 mux_tree_tapbuf_size10_11_sram[2]:8 0.000239093 +9 mux_tree_tapbuf_size10_11_sram[2]:9 0.0002634276 +10 mux_tree_tapbuf_size10_11_sram[2]:10 8.751162e-05 +11 mux_tree_tapbuf_size10_11_sram[2]:11 0.0003370849 +12 mux_tree_tapbuf_size10_11_sram[2]:12 0.0002446979 +13 mux_tree_tapbuf_size10_11_sram[2]:13 0.0003176455 +14 mux_tree_tapbuf_size10_11_sram[2]:14 0.0003176455 +15 mux_tree_tapbuf_size10_11_sram[2]:15 5.51135e-05 +16 mux_tree_tapbuf_size10_11_sram[2]:16 5.149681e-05 +17 mux_tree_tapbuf_size10_11_sram[2]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.482205e-05 +18 mux_tree_tapbuf_size10_11_sram[2]:12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 4.516658e-05 +19 mux_tree_tapbuf_size10_11_sram[2]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:8 3.728035e-06 +20 mux_tree_tapbuf_size10_11_sram[2]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.516658e-05 +21 mux_tree_tapbuf_size10_11_sram[2]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.244958e-05 +22 mux_tree_tapbuf_size10_11_sram[2]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.482205e-05 +23 mux_tree_tapbuf_size10_11_sram[2]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:7 3.728035e-06 +24 mux_tree_tapbuf_size10_11_sram[2]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.244958e-05 +25 mux_tree_tapbuf_size10_11_sram[2]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.612574e-05 +26 mux_tree_tapbuf_size10_11_sram[2]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.485648e-06 +27 mux_tree_tapbuf_size10_11_sram[2]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.612574e-05 +28 mux_tree_tapbuf_size10_11_sram[2]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.485648e-06 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_11_sram[2]:16 0.152 +1 mux_tree_tapbuf_size10_11_sram[2]:8 mux_tree_tapbuf_size10_11_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size10_11_sram[2]:7 mux_tree_tapbuf_size10_11_sram[2]:6 0.001741072 +3 mux_tree_tapbuf_size10_11_sram[2]:5 mux_tree_tapbuf_size10_11_sram[2]:4 9.51087e-05 +4 mux_tree_tapbuf_size10_11_sram[2]:6 mux_tree_tapbuf_size10_11_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size10_11_sram[2]:4 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size10_11_sram[2]:12 mux_left_track_25\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_11_sram[2]:12 mux_tree_tapbuf_size10_11_sram[2]:11 0.003618304 +8 mux_tree_tapbuf_size10_11_sram[2]:13 mux_tree_tapbuf_size10_11_sram[2]:12 0.0045 +9 mux_tree_tapbuf_size10_11_sram[2]:15 mux_tree_tapbuf_size10_11_sram[2]:14 0.0045 +10 mux_tree_tapbuf_size10_11_sram[2]:14 mux_tree_tapbuf_size10_11_sram[2]:13 0.004776786 +11 mux_tree_tapbuf_size10_11_sram[2]:16 mux_tree_tapbuf_size10_11_sram[2]:15 0.0001657609 +12 mux_tree_tapbuf_size10_11_sram[2]:11 mux_left_track_25\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_11_sram[2]:11 mux_tree_tapbuf_size10_11_sram[2]:10 0.001321429 +14 mux_tree_tapbuf_size10_11_sram[2]:9 mux_tree_tapbuf_size10_11_sram[2]:8 0.004066965 +15 mux_tree_tapbuf_size10_11_sram[2]:10 mux_tree_tapbuf_size10_11_sram[2]:9 0.0003035714 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[3] 0.001890581 //LENGTH 14.340 LUMPCC 0.000116999 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 120.365 58.820 +*I mem_right_track_8\/FTB_16__67:A I *L 0.001746 *C 120.060 55.760 +*I mux_right_track_8\/mux_l4_in_0_:S I *L 0.003425 *C 116.145 63.920 +*N mux_tree_tapbuf_size10_3_sram[3]:3 *C 116.145 63.920 +*N mux_tree_tapbuf_size10_3_sram[3]:4 *C 116.380 63.920 +*N mux_tree_tapbuf_size10_3_sram[3]:5 *C 116.380 63.875 +*N mux_tree_tapbuf_size10_3_sram[3]:6 *C 116.380 63.285 +*N mux_tree_tapbuf_size10_3_sram[3]:7 *C 116.425 63.240 +*N mux_tree_tapbuf_size10_3_sram[3]:8 *C 119.600 63.240 +*N mux_tree_tapbuf_size10_3_sram[3]:9 *C 119.600 63.580 +*N mux_tree_tapbuf_size10_3_sram[3]:10 *C 120.015 63.580 +*N mux_tree_tapbuf_size10_3_sram[3]:11 *C 120.060 63.535 +*N mux_tree_tapbuf_size10_3_sram[3]:12 *C 120.060 55.760 +*N mux_tree_tapbuf_size10_3_sram[3]:13 *C 120.060 55.805 +*N mux_tree_tapbuf_size10_3_sram[3]:14 *C 120.060 58.820 +*N mux_tree_tapbuf_size10_3_sram[3]:15 *C 120.060 58.820 +*N mux_tree_tapbuf_size10_3_sram[3]:16 *C 120.365 58.820 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_8\/FTB_16__67:A 1e-06 +2 mux_right_track_8\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_3_sram[3]:3 5.50649e-05 +4 mux_tree_tapbuf_size10_3_sram[3]:4 6.035414e-05 +5 mux_tree_tapbuf_size10_3_sram[3]:5 6.310768e-05 +6 mux_tree_tapbuf_size10_3_sram[3]:6 6.310768e-05 +7 mux_tree_tapbuf_size10_3_sram[3]:7 0.0002343027 +8 mux_tree_tapbuf_size10_3_sram[3]:8 0.0002591377 +9 mux_tree_tapbuf_size10_3_sram[3]:9 7.568462e-05 +10 mux_tree_tapbuf_size10_3_sram[3]:10 5.08496e-05 +11 mux_tree_tapbuf_size10_3_sram[3]:11 0.0002340685 +12 mux_tree_tapbuf_size10_3_sram[3]:12 3.277671e-05 +13 mux_tree_tapbuf_size10_3_sram[3]:13 0.0001381985 +14 mux_tree_tapbuf_size10_3_sram[3]:14 0.0004038793 +15 mux_tree_tapbuf_size10_3_sram[3]:15 5.224773e-05 +16 mux_tree_tapbuf_size10_3_sram[3]:16 4.780267e-05 +17 mux_tree_tapbuf_size10_3_sram[3]:11 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 2.441601e-05 +18 mux_tree_tapbuf_size10_3_sram[3]:14 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:4 3.408347e-05 +19 mux_tree_tapbuf_size10_3_sram[3]:14 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 2.441601e-05 +20 mux_tree_tapbuf_size10_3_sram[3]:13 mux_tree_tapbuf_size10_mem_3_ccff_tail[0]:5 3.408347e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_3_sram[3]:16 0.152 +1 mux_tree_tapbuf_size10_3_sram[3]:10 mux_tree_tapbuf_size10_3_sram[3]:9 0.0003705357 +2 mux_tree_tapbuf_size10_3_sram[3]:11 mux_tree_tapbuf_size10_3_sram[3]:10 0.0045 +3 mux_tree_tapbuf_size10_3_sram[3]:7 mux_tree_tapbuf_size10_3_sram[3]:6 0.0045 +4 mux_tree_tapbuf_size10_3_sram[3]:6 mux_tree_tapbuf_size10_3_sram[3]:5 0.0005267857 +5 mux_tree_tapbuf_size10_3_sram[3]:4 mux_tree_tapbuf_size10_3_sram[3]:3 0.0001277174 +6 mux_tree_tapbuf_size10_3_sram[3]:5 mux_tree_tapbuf_size10_3_sram[3]:4 0.0045 +7 mux_tree_tapbuf_size10_3_sram[3]:3 mux_right_track_8\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size10_3_sram[3]:15 mux_tree_tapbuf_size10_3_sram[3]:14 0.0045 +9 mux_tree_tapbuf_size10_3_sram[3]:14 mux_tree_tapbuf_size10_3_sram[3]:13 0.002691964 +10 mux_tree_tapbuf_size10_3_sram[3]:14 mux_tree_tapbuf_size10_3_sram[3]:11 0.004209822 +11 mux_tree_tapbuf_size10_3_sram[3]:16 mux_tree_tapbuf_size10_3_sram[3]:15 0.0001657609 +12 mux_tree_tapbuf_size10_3_sram[3]:12 mem_right_track_8\/FTB_16__67:A 0.152 +13 mux_tree_tapbuf_size10_3_sram[3]:13 mux_tree_tapbuf_size10_3_sram[3]:12 0.0045 +14 mux_tree_tapbuf_size10_3_sram[3]:8 mux_tree_tapbuf_size10_3_sram[3]:7 0.002834822 +15 mux_tree_tapbuf_size10_3_sram[3]:9 mux_tree_tapbuf_size10_3_sram[3]:8 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[3] 0.001682291 //LENGTH 14.265 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 103.345 88.400 +*I mem_right_track_24\/FTB_18__69:A I *L 0.001746 *C 105.800 82.960 +*I mux_right_track_24\/mux_l4_in_0_:S I *L 0.00357 *C 106.140 77.860 +*N mux_tree_tapbuf_size10_5_sram[3]:3 *C 106.125 77.860 +*N mux_tree_tapbuf_size10_5_sram[3]:4 *C 105.823 77.860 +*N mux_tree_tapbuf_size10_5_sram[3]:5 *C 105.800 77.905 +*N mux_tree_tapbuf_size10_5_sram[3]:6 *C 105.800 82.960 +*N mux_tree_tapbuf_size10_5_sram[3]:7 *C 105.800 82.960 +*N mux_tree_tapbuf_size10_5_sram[3]:8 *C 105.800 88.355 +*N mux_tree_tapbuf_size10_5_sram[3]:9 *C 105.755 88.400 +*N mux_tree_tapbuf_size10_5_sram[3]:10 *C 103.383 88.400 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_right_track_24\/FTB_18__69:A 1e-06 +2 mux_right_track_24\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_5_sram[3]:3 7.244963e-05 +4 mux_tree_tapbuf_size10_5_sram[3]:4 7.244963e-05 +5 mux_tree_tapbuf_size10_5_sram[3]:5 0.0002985455 +6 mux_tree_tapbuf_size10_5_sram[3]:6 3.649178e-05 +7 mux_tree_tapbuf_size10_5_sram[3]:7 0.0006170746 +8 mux_tree_tapbuf_size10_5_sram[3]:8 0.0002857016 +9 mux_tree_tapbuf_size10_5_sram[3]:9 0.0001482891 +10 mux_tree_tapbuf_size10_5_sram[3]:10 0.0001482891 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_5_sram[3]:10 0.152 +1 mux_tree_tapbuf_size10_5_sram[3]:3 mux_right_track_24\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_5_sram[3]:4 mux_tree_tapbuf_size10_5_sram[3]:3 0.0001644022 +3 mux_tree_tapbuf_size10_5_sram[3]:5 mux_tree_tapbuf_size10_5_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size10_5_sram[3]:9 mux_tree_tapbuf_size10_5_sram[3]:8 0.0045 +5 mux_tree_tapbuf_size10_5_sram[3]:8 mux_tree_tapbuf_size10_5_sram[3]:7 0.004816965 +6 mux_tree_tapbuf_size10_5_sram[3]:10 mux_tree_tapbuf_size10_5_sram[3]:9 0.002118304 +7 mux_tree_tapbuf_size10_5_sram[3]:6 mem_right_track_24\/FTB_18__69:A 0.152 +8 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size10_5_sram[3]:7 mux_tree_tapbuf_size10_5_sram[3]:5 0.004513392 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[2] 0.00244322 //LENGTH 19.845 LUMPCC 0.0001021142 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 46.305 31.280 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 43.415 33.660 +*I mux_bottom_track_17\/mux_l3_in_1_:S I *L 0.00357 *C 45.440 36.040 +*I mux_bottom_track_17\/mux_l3_in_0_:S I *L 0.00357 *C 56.220 31.280 +*N mux_tree_tapbuf_size10_7_sram[2]:4 *C 56.183 31.280 +*N mux_tree_tapbuf_size10_7_sram[2]:5 *C 45.425 36.040 +*N mux_tree_tapbuf_size10_7_sram[2]:6 *C 45.102 36.040 +*N mux_tree_tapbuf_size10_7_sram[2]:7 *C 45.080 35.995 +*N mux_tree_tapbuf_size10_7_sram[2]:8 *C 45.080 33.660 +*N mux_tree_tapbuf_size10_7_sram[2]:9 *C 43.453 33.660 +*N mux_tree_tapbuf_size10_7_sram[2]:10 *C 45.495 33.660 +*N mux_tree_tapbuf_size10_7_sram[2]:11 *C 45.540 33.615 +*N mux_tree_tapbuf_size10_7_sram[2]:12 *C 45.540 31.325 +*N mux_tree_tapbuf_size10_7_sram[2]:13 *C 45.585 31.280 +*N mux_tree_tapbuf_size10_7_sram[2]:14 *C 46.305 31.280 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_track_17\/mux_l3_in_1_:S 1e-06 +3 mux_bottom_track_17\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_7_sram[2]:4 0.000563528 +5 mux_tree_tapbuf_size10_7_sram[2]:5 6.073704e-05 +6 mux_tree_tapbuf_size10_7_sram[2]:6 6.073704e-05 +7 mux_tree_tapbuf_size10_7_sram[2]:7 0.0001484933 +8 mux_tree_tapbuf_size10_7_sram[2]:8 0.0001815408 +9 mux_tree_tapbuf_size10_7_sram[2]:9 0.0001540436 +10 mux_tree_tapbuf_size10_7_sram[2]:10 0.0001540436 +11 mux_tree_tapbuf_size10_7_sram[2]:11 0.0001734554 +12 mux_tree_tapbuf_size10_7_sram[2]:12 0.0001404079 +13 mux_tree_tapbuf_size10_7_sram[2]:13 5.223077e-05 +14 mux_tree_tapbuf_size10_7_sram[2]:14 0.0006478883 +15 mux_tree_tapbuf_size10_7_sram[2]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.105712e-05 +16 mux_tree_tapbuf_size10_7_sram[2]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.105712e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_7_sram[2]:14 0.152 +1 mux_tree_tapbuf_size10_7_sram[2]:10 mux_tree_tapbuf_size10_7_sram[2]:9 0.001823661 +2 mux_tree_tapbuf_size10_7_sram[2]:11 mux_tree_tapbuf_size10_7_sram[2]:10 0.0045 +3 mux_tree_tapbuf_size10_7_sram[2]:11 mux_tree_tapbuf_size10_7_sram[2]:8 0.0004107143 +4 mux_tree_tapbuf_size10_7_sram[2]:9 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +5 mux_tree_tapbuf_size10_7_sram[2]:5 mux_bottom_track_17\/mux_l3_in_1_:S 0.152 +6 mux_tree_tapbuf_size10_7_sram[2]:6 mux_tree_tapbuf_size10_7_sram[2]:5 0.0001752718 +7 mux_tree_tapbuf_size10_7_sram[2]:7 mux_tree_tapbuf_size10_7_sram[2]:6 0.0045 +8 mux_tree_tapbuf_size10_7_sram[2]:14 mux_tree_tapbuf_size10_7_sram[2]:13 0.0006428572 +9 mux_tree_tapbuf_size10_7_sram[2]:14 mux_tree_tapbuf_size10_7_sram[2]:4 0.008819196 +10 mux_tree_tapbuf_size10_7_sram[2]:4 mux_bottom_track_17\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size10_7_sram[2]:13 mux_tree_tapbuf_size10_7_sram[2]:12 0.0045 +12 mux_tree_tapbuf_size10_7_sram[2]:12 mux_tree_tapbuf_size10_7_sram[2]:11 0.002044643 +13 mux_tree_tapbuf_size10_7_sram[2]:8 mux_tree_tapbuf_size10_7_sram[2]:7 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_1_ccff_tail[0] 0.001101211 //LENGTH 7.965 LUMPCC 0.000230394 DR + +*CONN +*I mem_top_track_16\/FTB_14__65:X O *L 0 *C 56.820 61.880 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 52.165 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 *C 52.203 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 *C 52.855 64.260 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 *C 52.900 64.215 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 *C 52.900 61.925 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 *C 52.945 61.880 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 *C 56.783 61.880 + +*CAP +0 mem_top_track_16\/FTB_14__65:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 6.993597e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 6.993597e-05 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0001162058 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0001162058 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.0002482669 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.0002482669 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 chany_top_in[14]:13 6.857105e-05 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 chany_top_in[14]:14 6.857105e-05 +10 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_11_sram[1]:10 4.01371e-05 +11 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_11_sram[1]:12 4.645022e-07 +12 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_11_sram[1]:14 6.024343e-06 +13 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_11_sram[1]:11 4.01371e-05 +14 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_11_sram[1]:13 4.645022e-07 +15 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_11_sram[1]:30 6.024343e-06 + +*RES +0 mem_top_track_16\/FTB_14__65:X mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.003426339 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 0.0005825893 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size12_0_sram[0] 0.01614381 //LENGTH 117.115 LUMPCC 0.002696586 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 135.085 88.060 +*I mux_top_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 61.520 117.640 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 57.860 117.640 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.795 115.260 +*I mux_top_track_0\/mux_l1_in_4_:S I *L 0.00357 *C 74.420 96.560 +*I mux_top_track_0\/mux_l1_in_3_:S I *L 0.00357 *C 83.820 96.560 +*I mux_top_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 80.600 94.520 +*N mux_tree_tapbuf_size12_0_sram[0]:7 *C 80.615 94.520 +*N mux_tree_tapbuf_size12_0_sram[0]:8 *C 83.782 96.560 +*N mux_tree_tapbuf_size12_0_sram[0]:9 *C 74.420 96.560 +*N mux_tree_tapbuf_size12_0_sram[0]:10 *C 67.795 115.260 +*N mux_tree_tapbuf_size12_0_sram[0]:11 *C 57.898 117.640 +*N mux_tree_tapbuf_size12_0_sram[0]:12 *C 61.520 117.640 +*N mux_tree_tapbuf_size12_0_sram[0]:13 *C 63.435 117.640 +*N mux_tree_tapbuf_size12_0_sram[0]:14 *C 63.480 117.595 +*N mux_tree_tapbuf_size12_0_sram[0]:15 *C 63.480 114.965 +*N mux_tree_tapbuf_size12_0_sram[0]:16 *C 63.525 114.920 +*N mux_tree_tapbuf_size12_0_sram[0]:17 *C 67.665 114.928 +*N mux_tree_tapbuf_size12_0_sram[0]:18 *C 67.620 114.875 +*N mux_tree_tapbuf_size12_0_sram[0]:19 *C 67.620 109.865 +*N mux_tree_tapbuf_size12_0_sram[0]:20 *C 67.665 109.820 +*N mux_tree_tapbuf_size12_0_sram[0]:21 *C 74.015 109.820 +*N mux_tree_tapbuf_size12_0_sram[0]:22 *C 74.060 109.775 +*N mux_tree_tapbuf_size12_0_sram[0]:23 *C 74.060 106.760 +*N mux_tree_tapbuf_size12_0_sram[0]:24 *C 74.520 106.760 +*N mux_tree_tapbuf_size12_0_sram[0]:25 *C 74.520 96.945 +*N mux_tree_tapbuf_size12_0_sram[0]:26 *C 74.565 96.900 +*N mux_tree_tapbuf_size12_0_sram[0]:27 *C 77.740 96.900 +*N mux_tree_tapbuf_size12_0_sram[0]:28 *C 77.740 96.560 +*N mux_tree_tapbuf_size12_0_sram[0]:29 *C 80.960 96.560 +*N mux_tree_tapbuf_size12_0_sram[0]:30 *C 80.960 96.515 +*N mux_tree_tapbuf_size12_0_sram[0]:31 *C 80.960 94.565 +*N mux_tree_tapbuf_size12_0_sram[0]:32 *C 81.005 94.520 +*N mux_tree_tapbuf_size12_0_sram[0]:33 *C 92.000 94.520 +*N mux_tree_tapbuf_size12_0_sram[0]:34 *C 92.000 94.180 +*N mux_tree_tapbuf_size12_0_sram[0]:35 *C 95.635 94.180 +*N mux_tree_tapbuf_size12_0_sram[0]:36 *C 95.680 94.135 +*N mux_tree_tapbuf_size12_0_sram[0]:37 *C 95.680 90.498 +*N mux_tree_tapbuf_size12_0_sram[0]:38 *C 95.688 90.440 +*N mux_tree_tapbuf_size12_0_sram[0]:39 *C 120.520 90.440 +*N mux_tree_tapbuf_size12_0_sram[0]:40 *C 120.520 89.760 +*N mux_tree_tapbuf_size12_0_sram[0]:41 *C 132.013 89.760 +*N mux_tree_tapbuf_size12_0_sram[0]:42 *C 132.020 89.703 +*N mux_tree_tapbuf_size12_0_sram[0]:43 *C 132.020 88.105 +*N mux_tree_tapbuf_size12_0_sram[0]:44 *C 132.065 88.060 +*N mux_tree_tapbuf_size12_0_sram[0]:45 *C 135.048 88.060 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_0\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +3 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_0\/mux_l1_in_4_:S 1e-06 +5 mux_top_track_0\/mux_l1_in_3_:S 1e-06 +6 mux_top_track_0\/mux_l1_in_2_:S 1e-06 +7 mux_tree_tapbuf_size12_0_sram[0]:7 5.972175e-05 +8 mux_tree_tapbuf_size12_0_sram[0]:8 0.0001763952 +9 mux_tree_tapbuf_size12_0_sram[0]:9 6.890975e-05 +10 mux_tree_tapbuf_size12_0_sram[0]:10 6.377262e-05 +11 mux_tree_tapbuf_size12_0_sram[0]:11 0.0002259207 +12 mux_tree_tapbuf_size12_0_sram[0]:12 0.0003685264 +13 mux_tree_tapbuf_size12_0_sram[0]:13 0.000113963 +14 mux_tree_tapbuf_size12_0_sram[0]:14 0.0001902747 +15 mux_tree_tapbuf_size12_0_sram[0]:15 0.0001902747 +16 mux_tree_tapbuf_size12_0_sram[0]:16 0.0002858501 +17 mux_tree_tapbuf_size12_0_sram[0]:17 0.0003205884 +18 mux_tree_tapbuf_size12_0_sram[0]:18 0.0003092858 +19 mux_tree_tapbuf_size12_0_sram[0]:19 0.0003092858 +20 mux_tree_tapbuf_size12_0_sram[0]:20 0.0004389461 +21 mux_tree_tapbuf_size12_0_sram[0]:21 0.0004389461 +22 mux_tree_tapbuf_size12_0_sram[0]:22 0.0001998286 +23 mux_tree_tapbuf_size12_0_sram[0]:23 0.0002322315 +24 mux_tree_tapbuf_size12_0_sram[0]:24 0.000475818 +25 mux_tree_tapbuf_size12_0_sram[0]:25 0.0004434151 +26 mux_tree_tapbuf_size12_0_sram[0]:26 0.0002916631 +27 mux_tree_tapbuf_size12_0_sram[0]:27 0.0002824606 +28 mux_tree_tapbuf_size12_0_sram[0]:28 0.0002327124 +29 mux_tree_tapbuf_size12_0_sram[0]:29 0.0004166209 +30 mux_tree_tapbuf_size12_0_sram[0]:30 0.0001593839 +31 mux_tree_tapbuf_size12_0_sram[0]:31 0.0001593839 +32 mux_tree_tapbuf_size12_0_sram[0]:32 0.0009547978 +33 mux_tree_tapbuf_size12_0_sram[0]:33 0.0009205816 +34 mux_tree_tapbuf_size12_0_sram[0]:34 0.0002764578 +35 mux_tree_tapbuf_size12_0_sram[0]:35 0.0002509522 +36 mux_tree_tapbuf_size12_0_sram[0]:36 0.0002568805 +37 mux_tree_tapbuf_size12_0_sram[0]:37 0.0002568805 +38 mux_tree_tapbuf_size12_0_sram[0]:38 0.00118942 +39 mux_tree_tapbuf_size12_0_sram[0]:39 0.001242175 +40 mux_tree_tapbuf_size12_0_sram[0]:40 0.0005503992 +41 mux_tree_tapbuf_size12_0_sram[0]:41 0.0004976445 +42 mux_tree_tapbuf_size12_0_sram[0]:42 0.0001028568 +43 mux_tree_tapbuf_size12_0_sram[0]:43 0.0001028568 +44 mux_tree_tapbuf_size12_0_sram[0]:44 0.0001920707 +45 mux_tree_tapbuf_size12_0_sram[0]:45 0.0001920707 +46 mux_tree_tapbuf_size12_0_sram[0]:36 chanx_right_in[14]:39 1.164795e-05 +47 mux_tree_tapbuf_size12_0_sram[0]:37 chanx_right_in[14]:38 1.164795e-05 +48 mux_tree_tapbuf_size12_0_sram[0]:38 chanx_right_in[14]:39 0.0004848115 +49 mux_tree_tapbuf_size12_0_sram[0]:41 chanx_right_in[14] 2.03459e-05 +50 mux_tree_tapbuf_size12_0_sram[0]:41 chanx_right_in[14]:40 0.0001591935 +51 mux_tree_tapbuf_size12_0_sram[0]:39 chanx_right_in[14]:40 0.0004848115 +52 mux_tree_tapbuf_size12_0_sram[0]:40 chanx_right_in[14]:39 0.0001591935 +53 mux_tree_tapbuf_size12_0_sram[0]:40 chanx_right_in[14]:41 2.03459e-05 +54 mux_tree_tapbuf_size12_0_sram[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.188172e-05 +55 mux_tree_tapbuf_size12_0_sram[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.237525e-05 +56 mux_tree_tapbuf_size12_0_sram[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.237525e-05 +57 mux_tree_tapbuf_size12_0_sram[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.188172e-05 +58 mux_tree_tapbuf_size12_0_sram[0]:29 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.124316e-05 +59 mux_tree_tapbuf_size12_0_sram[0]:29 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.751631e-05 +60 mux_tree_tapbuf_size12_0_sram[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.124316e-05 +61 mux_tree_tapbuf_size12_0_sram[0]:28 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.751631e-05 +62 mux_tree_tapbuf_size12_0_sram[0]:22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 2.217789e-05 +63 mux_tree_tapbuf_size12_0_sram[0]:25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002165933 +64 mux_tree_tapbuf_size12_0_sram[0]:23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 2.217789e-05 +65 mux_tree_tapbuf_size12_0_sram[0]:23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.924622e-08 +66 mux_tree_tapbuf_size12_0_sram[0]:24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002166126 +67 mux_tree_tapbuf_size12_0_sram[0]:38 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0002604871 +68 mux_tree_tapbuf_size12_0_sram[0]:39 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002604871 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_0_sram[0]:45 0.152 +1 mux_tree_tapbuf_size12_0_sram[0]:11 mux_top_track_0\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_0_sram[0]:17 mux_tree_tapbuf_size12_0_sram[0]:16 0.003696429 +3 mux_tree_tapbuf_size12_0_sram[0]:17 mux_tree_tapbuf_size12_0_sram[0]:10 0.0001807065 +4 mux_tree_tapbuf_size12_0_sram[0]:18 mux_tree_tapbuf_size12_0_sram[0]:17 0.0045 +5 mux_tree_tapbuf_size12_0_sram[0]:20 mux_tree_tapbuf_size12_0_sram[0]:19 0.0045 +6 mux_tree_tapbuf_size12_0_sram[0]:19 mux_tree_tapbuf_size12_0_sram[0]:18 0.004473215 +7 mux_tree_tapbuf_size12_0_sram[0]:21 mux_tree_tapbuf_size12_0_sram[0]:20 0.005669643 +8 mux_tree_tapbuf_size12_0_sram[0]:22 mux_tree_tapbuf_size12_0_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size12_0_sram[0]:26 mux_tree_tapbuf_size12_0_sram[0]:25 0.0045 +10 mux_tree_tapbuf_size12_0_sram[0]:26 mux_tree_tapbuf_size12_0_sram[0]:9 0.0001847826 +11 mux_tree_tapbuf_size12_0_sram[0]:25 mux_tree_tapbuf_size12_0_sram[0]:24 0.008763393 +12 mux_tree_tapbuf_size12_0_sram[0]:32 mux_tree_tapbuf_size12_0_sram[0]:31 0.0045 +13 mux_tree_tapbuf_size12_0_sram[0]:32 mux_tree_tapbuf_size12_0_sram[0]:7 0.0002119565 +14 mux_tree_tapbuf_size12_0_sram[0]:31 mux_tree_tapbuf_size12_0_sram[0]:30 0.001741072 +15 mux_tree_tapbuf_size12_0_sram[0]:29 mux_tree_tapbuf_size12_0_sram[0]:28 0.002875 +16 mux_tree_tapbuf_size12_0_sram[0]:29 mux_tree_tapbuf_size12_0_sram[0]:8 0.002520089 +17 mux_tree_tapbuf_size12_0_sram[0]:30 mux_tree_tapbuf_size12_0_sram[0]:29 0.0045 +18 mux_tree_tapbuf_size12_0_sram[0]:16 mux_tree_tapbuf_size12_0_sram[0]:15 0.0045 +19 mux_tree_tapbuf_size12_0_sram[0]:15 mux_tree_tapbuf_size12_0_sram[0]:14 0.002348215 +20 mux_tree_tapbuf_size12_0_sram[0]:13 mux_tree_tapbuf_size12_0_sram[0]:12 0.001709821 +21 mux_tree_tapbuf_size12_0_sram[0]:14 mux_tree_tapbuf_size12_0_sram[0]:13 0.0045 +22 mux_tree_tapbuf_size12_0_sram[0]:10 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +23 mux_tree_tapbuf_size12_0_sram[0]:35 mux_tree_tapbuf_size12_0_sram[0]:34 0.003245536 +24 mux_tree_tapbuf_size12_0_sram[0]:36 mux_tree_tapbuf_size12_0_sram[0]:35 0.0045 +25 mux_tree_tapbuf_size12_0_sram[0]:37 mux_tree_tapbuf_size12_0_sram[0]:36 0.003247768 +26 mux_tree_tapbuf_size12_0_sram[0]:38 mux_tree_tapbuf_size12_0_sram[0]:37 0.00341 +27 mux_tree_tapbuf_size12_0_sram[0]:42 mux_tree_tapbuf_size12_0_sram[0]:41 0.00341 +28 mux_tree_tapbuf_size12_0_sram[0]:41 mux_tree_tapbuf_size12_0_sram[0]:40 0.001800492 +29 mux_tree_tapbuf_size12_0_sram[0]:44 mux_tree_tapbuf_size12_0_sram[0]:43 0.0045 +30 mux_tree_tapbuf_size12_0_sram[0]:43 mux_tree_tapbuf_size12_0_sram[0]:42 0.001426339 +31 mux_tree_tapbuf_size12_0_sram[0]:45 mux_tree_tapbuf_size12_0_sram[0]:44 0.002662946 +32 mux_tree_tapbuf_size12_0_sram[0]:9 mux_top_track_0\/mux_l1_in_4_:S 0.152 +33 mux_tree_tapbuf_size12_0_sram[0]:8 mux_top_track_0\/mux_l1_in_3_:S 0.152 +34 mux_tree_tapbuf_size12_0_sram[0]:7 mux_top_track_0\/mux_l1_in_2_:S 0.152 +35 mux_tree_tapbuf_size12_0_sram[0]:12 mux_top_track_0\/mux_l1_in_1_:S 0.152 +36 mux_tree_tapbuf_size12_0_sram[0]:12 mux_tree_tapbuf_size12_0_sram[0]:11 0.003234375 +37 mux_tree_tapbuf_size12_0_sram[0]:27 mux_tree_tapbuf_size12_0_sram[0]:26 0.002834822 +38 mux_tree_tapbuf_size12_0_sram[0]:28 mux_tree_tapbuf_size12_0_sram[0]:27 0.0003035715 +39 mux_tree_tapbuf_size12_0_sram[0]:33 mux_tree_tapbuf_size12_0_sram[0]:32 0.009816964 +40 mux_tree_tapbuf_size12_0_sram[0]:34 mux_tree_tapbuf_size12_0_sram[0]:33 0.0003035715 +41 mux_tree_tapbuf_size12_0_sram[0]:23 mux_tree_tapbuf_size12_0_sram[0]:22 0.002691964 +42 mux_tree_tapbuf_size12_0_sram[0]:24 mux_tree_tapbuf_size12_0_sram[0]:23 0.0004107143 +43 mux_tree_tapbuf_size12_0_sram[0]:39 mux_tree_tapbuf_size12_0_sram[0]:38 0.003890425 +44 mux_tree_tapbuf_size12_0_sram[0]:40 mux_tree_tapbuf_size12_0_sram[0]:39 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size12_5_sram[3] 0.002159107 //LENGTH 16.235 LUMPCC 0.0003841846 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 61.945 11.900 +*I mem_bottom_track_3\/FTB_6__57:A I *L 0.001746 *C 54.280 12.240 +*I mux_bottom_track_3\/mux_l4_in_0_:S I *L 0.00357 *C 63.120 9.520 +*N mux_tree_tapbuf_size12_5_sram[3]:3 *C 63.083 9.520 +*N mux_tree_tapbuf_size12_5_sram[3]:4 *C 54.280 12.240 +*N mux_tree_tapbuf_size12_5_sram[3]:5 *C 54.280 12.195 +*N mux_tree_tapbuf_size12_5_sram[3]:6 *C 54.280 10.245 +*N mux_tree_tapbuf_size12_5_sram[3]:7 *C 54.325 10.200 +*N mux_tree_tapbuf_size12_5_sram[3]:8 *C 58.880 10.200 +*N mux_tree_tapbuf_size12_5_sram[3]:9 *C 58.880 9.520 +*N mux_tree_tapbuf_size12_5_sram[3]:10 *C 61.180 9.520 +*N mux_tree_tapbuf_size12_5_sram[3]:11 *C 61.180 9.565 +*N mux_tree_tapbuf_size12_5_sram[3]:12 *C 61.180 11.855 +*N mux_tree_tapbuf_size12_5_sram[3]:13 *C 61.225 11.900 +*N mux_tree_tapbuf_size12_5_sram[3]:14 *C 61.908 11.900 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_3\/FTB_6__57:A 1e-06 +2 mux_bottom_track_3\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_5_sram[3]:3 9.471337e-05 +4 mux_tree_tapbuf_size12_5_sram[3]:4 3.543391e-05 +5 mux_tree_tapbuf_size12_5_sram[3]:5 0.0001487582 +6 mux_tree_tapbuf_size12_5_sram[3]:6 0.0001487582 +7 mux_tree_tapbuf_size12_5_sram[3]:7 0.0003105683 +8 mux_tree_tapbuf_size12_5_sram[3]:8 0.0003464375 +9 mux_tree_tapbuf_size12_5_sram[3]:9 0.000172015 +10 mux_tree_tapbuf_size12_5_sram[3]:10 0.000262651 +11 mux_tree_tapbuf_size12_5_sram[3]:11 7.513347e-05 +12 mux_tree_tapbuf_size12_5_sram[3]:12 7.513347e-05 +13 mux_tree_tapbuf_size12_5_sram[3]:13 5.115981e-05 +14 mux_tree_tapbuf_size12_5_sram[3]:14 5.115981e-05 +15 mux_tree_tapbuf_size12_5_sram[3]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 2.999261e-05 +16 mux_tree_tapbuf_size12_5_sram[3]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 2.999261e-05 +17 mux_tree_tapbuf_size12_5_sram[3]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 4.595936e-05 +18 mux_tree_tapbuf_size12_5_sram[3]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 4.595936e-05 +19 mux_tree_tapbuf_size12_5_sram[3]:11 ropt_net_162:4 7.088173e-05 +20 mux_tree_tapbuf_size12_5_sram[3]:13 ropt_net_162:6 3.933245e-05 +21 mux_tree_tapbuf_size12_5_sram[3]:12 ropt_net_162:5 7.088173e-05 +22 mux_tree_tapbuf_size12_5_sram[3]:14 ropt_net_162:7 3.933245e-05 +23 mux_tree_tapbuf_size12_5_sram[3]:8 ropt_net_162:5 5.926117e-06 +24 mux_tree_tapbuf_size12_5_sram[3]:9 ropt_net_162:4 5.926117e-06 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_5_sram[3]:14 0.152 +1 mux_tree_tapbuf_size12_5_sram[3]:3 mux_bottom_track_3\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_5_sram[3]:10 mux_tree_tapbuf_size12_5_sram[3]:9 0.002053572 +3 mux_tree_tapbuf_size12_5_sram[3]:10 mux_tree_tapbuf_size12_5_sram[3]:3 0.001698661 +4 mux_tree_tapbuf_size12_5_sram[3]:11 mux_tree_tapbuf_size12_5_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size12_5_sram[3]:13 mux_tree_tapbuf_size12_5_sram[3]:12 0.0045 +6 mux_tree_tapbuf_size12_5_sram[3]:12 mux_tree_tapbuf_size12_5_sram[3]:11 0.002044643 +7 mux_tree_tapbuf_size12_5_sram[3]:14 mux_tree_tapbuf_size12_5_sram[3]:13 0.000609375 +8 mux_tree_tapbuf_size12_5_sram[3]:7 mux_tree_tapbuf_size12_5_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size12_5_sram[3]:6 mux_tree_tapbuf_size12_5_sram[3]:5 0.001741072 +10 mux_tree_tapbuf_size12_5_sram[3]:4 mem_bottom_track_3\/FTB_6__57:A 0.152 +11 mux_tree_tapbuf_size12_5_sram[3]:5 mux_tree_tapbuf_size12_5_sram[3]:4 0.0045 +12 mux_tree_tapbuf_size12_5_sram[3]:8 mux_tree_tapbuf_size12_5_sram[3]:7 0.004066965 +13 mux_tree_tapbuf_size12_5_sram[3]:9 mux_tree_tapbuf_size12_5_sram[3]:8 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_7_ccff_tail[0] 0.0006304585 //LENGTH 4.600 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/FTB_8__59:X O *L 0 *C 38.875 98.600 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 42.955 98.940 +*N mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:2 *C 42.955 98.940 +*N mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:3 *C 42.780 98.600 +*N mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:4 *C 38.913 98.600 + +*CAP +0 mem_left_track_3\/FTB_8__59:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:2 5.462985e-05 +3 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:3 0.0002998092 +4 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:4 0.0002740194 + +*RES +0 mem_left_track_3\/FTB_8__59:X mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:4 0.152 +1 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:3 0.003453125 +3 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_7_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size16_1_sram[1] 0.01428617 //LENGTH 93.043 LUMPCC 0.003410904 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 131.720 85.340 +*I mux_right_track_4\/mux_l2_in_4_:S I *L 0.00357 *C 119.260 85.000 +*I mux_right_track_4\/mux_l2_in_2_:S I *L 0.00357 *C 121.540 85.390 +*I mux_right_track_4\/mux_l2_in_7_:S I *L 0.00357 *C 120.620 79.560 +*I mux_right_track_4\/mux_l2_in_6_:S I *L 0.00357 *C 113.060 74.510 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 107.355 71.740 +*I mux_right_track_4\/mux_l2_in_5_:S I *L 0.00357 *C 79.940 74.510 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 76.720 83.640 +*I mux_right_track_4\/mux_l2_in_3_:S I *L 0.00357 *C 115.360 77.815 +*I mux_right_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 113.980 82.885 +*N mux_tree_tapbuf_size16_1_sram[1]:10 *C 113.980 82.885 +*N mux_tree_tapbuf_size16_1_sram[1]:11 *C 114.080 82.915 +*N mux_tree_tapbuf_size16_1_sram[1]:12 *C 115.360 77.815 +*N mux_tree_tapbuf_size16_1_sram[1]:13 *C 115.303 77.520 +*N mux_tree_tapbuf_size16_1_sram[1]:14 *C 113.080 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:15 *C 76.720 83.640 +*N mux_tree_tapbuf_size16_1_sram[1]:16 *C 76.820 83.595 +*N mux_tree_tapbuf_size16_1_sram[1]:17 *C 76.820 74.845 +*N mux_tree_tapbuf_size16_1_sram[1]:18 *C 76.865 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:19 *C 79.580 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:20 *C 79.580 74.460 +*N mux_tree_tapbuf_size16_1_sram[1]:21 *C 79.940 74.510 +*N mux_tree_tapbuf_size16_1_sram[1]:22 *C 85.560 74.460 +*N mux_tree_tapbuf_size16_1_sram[1]:23 *C 85.560 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:24 *C 86.480 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:25 *C 86.480 74.460 +*N mux_tree_tapbuf_size16_1_sram[1]:26 *C 96.600 74.460 +*N mux_tree_tapbuf_size16_1_sram[1]:27 *C 96.600 74.120 +*N mux_tree_tapbuf_size16_1_sram[1]:28 *C 107.355 71.740 +*N mux_tree_tapbuf_size16_1_sram[1]:29 *C 107.180 71.740 +*N mux_tree_tapbuf_size16_1_sram[1]:30 *C 107.180 71.785 +*N mux_tree_tapbuf_size16_1_sram[1]:31 *C 107.180 74.075 +*N mux_tree_tapbuf_size16_1_sram[1]:32 *C 107.180 74.120 +*N mux_tree_tapbuf_size16_1_sram[1]:33 *C 113.060 74.120 +*N mux_tree_tapbuf_size16_1_sram[1]:34 *C 113.060 74.510 +*N mux_tree_tapbuf_size16_1_sram[1]:35 *C 113.135 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:36 *C 115.415 74.800 +*N mux_tree_tapbuf_size16_1_sram[1]:37 *C 115.460 74.845 +*N mux_tree_tapbuf_size16_1_sram[1]:38 *C 115.460 77.475 +*N mux_tree_tapbuf_size16_1_sram[1]:39 *C 115.403 77.550 +*N mux_tree_tapbuf_size16_1_sram[1]:40 *C 114.125 77.520 +*N mux_tree_tapbuf_size16_1_sram[1]:41 *C 114.080 77.565 +*N mux_tree_tapbuf_size16_1_sram[1]:42 *C 114.080 79.560 +*N mux_tree_tapbuf_size16_1_sram[1]:43 *C 114.125 79.560 +*N mux_tree_tapbuf_size16_1_sram[1]:44 *C 120.620 79.560 +*N mux_tree_tapbuf_size16_1_sram[1]:45 *C 121.395 79.560 +*N mux_tree_tapbuf_size16_1_sram[1]:46 *C 121.440 79.605 +*N mux_tree_tapbuf_size16_1_sram[1]:47 *C 121.540 85.390 +*N mux_tree_tapbuf_size16_1_sram[1]:48 *C 121.490 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:49 *C 119.297 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:50 *C 121.535 85.030 +*N mux_tree_tapbuf_size16_1_sram[1]:51 *C 121.440 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:52 *C 121.448 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:53 *C 131.553 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:54 *C 131.560 85.000 +*N mux_tree_tapbuf_size16_1_sram[1]:55 *C 131.560 85.340 +*N mux_tree_tapbuf_size16_1_sram[1]:56 *C 131.560 85.340 +*N mux_tree_tapbuf_size16_1_sram[1]:57 *C 131.720 85.340 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_4\/mux_l2_in_4_:S 1e-06 +2 mux_right_track_4\/mux_l2_in_2_:S 1e-06 +3 mux_right_track_4\/mux_l2_in_7_:S 1e-06 +4 mux_right_track_4\/mux_l2_in_6_:S 1e-06 +5 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_right_track_4\/mux_l2_in_5_:S 1e-06 +7 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +8 mux_right_track_4\/mux_l2_in_3_:S 1e-06 +9 mux_right_track_4\/mux_l2_in_1_:S 1e-06 +10 mux_tree_tapbuf_size16_1_sram[1]:10 3.044113e-05 +11 mux_tree_tapbuf_size16_1_sram[1]:11 0.000188278 +12 mux_tree_tapbuf_size16_1_sram[1]:12 6.058928e-05 +13 mux_tree_tapbuf_size16_1_sram[1]:13 2.019264e-05 +14 mux_tree_tapbuf_size16_1_sram[1]:14 3.103648e-05 +15 mux_tree_tapbuf_size16_1_sram[1]:15 3.276645e-05 +16 mux_tree_tapbuf_size16_1_sram[1]:16 0.0005703752 +17 mux_tree_tapbuf_size16_1_sram[1]:17 0.0005703752 +18 mux_tree_tapbuf_size16_1_sram[1]:18 0.0002411122 +19 mux_tree_tapbuf_size16_1_sram[1]:19 0.0002627223 +20 mux_tree_tapbuf_size16_1_sram[1]:20 4.110907e-05 +21 mux_tree_tapbuf_size16_1_sram[1]:21 0.0003613959 +22 mux_tree_tapbuf_size16_1_sram[1]:22 0.0003310756 +23 mux_tree_tapbuf_size16_1_sram[1]:23 0.0001060575 +24 mux_tree_tapbuf_size16_1_sram[1]:24 0.0001092094 +25 mux_tree_tapbuf_size16_1_sram[1]:25 0.0005049728 +26 mux_tree_tapbuf_size16_1_sram[1]:26 0.0005055692 +27 mux_tree_tapbuf_size16_1_sram[1]:27 0.0007888003 +28 mux_tree_tapbuf_size16_1_sram[1]:28 4.829413e-05 +29 mux_tree_tapbuf_size16_1_sram[1]:29 5.201548e-05 +30 mux_tree_tapbuf_size16_1_sram[1]:30 0.0001507344 +31 mux_tree_tapbuf_size16_1_sram[1]:31 0.0001507344 +32 mux_tree_tapbuf_size16_1_sram[1]:32 0.001202423 +33 mux_tree_tapbuf_size16_1_sram[1]:33 0.0004341155 +34 mux_tree_tapbuf_size16_1_sram[1]:34 0.0001005108 +35 mux_tree_tapbuf_size16_1_sram[1]:35 0.0001831719 +36 mux_tree_tapbuf_size16_1_sram[1]:36 0.0001457898 +37 mux_tree_tapbuf_size16_1_sram[1]:37 0.0001774403 +38 mux_tree_tapbuf_size16_1_sram[1]:38 0.0001774403 +39 mux_tree_tapbuf_size16_1_sram[1]:39 0.0001528495 +40 mux_tree_tapbuf_size16_1_sram[1]:40 0.0001052474 +41 mux_tree_tapbuf_size16_1_sram[1]:41 0.0001100301 +42 mux_tree_tapbuf_size16_1_sram[1]:42 0.0003304084 +43 mux_tree_tapbuf_size16_1_sram[1]:43 0.000403301 +44 mux_tree_tapbuf_size16_1_sram[1]:44 0.0004900116 +45 mux_tree_tapbuf_size16_1_sram[1]:45 5.686764e-05 +46 mux_tree_tapbuf_size16_1_sram[1]:46 0.0002578977 +47 mux_tree_tapbuf_size16_1_sram[1]:47 5.201558e-05 +48 mux_tree_tapbuf_size16_1_sram[1]:48 2.32504e-05 +49 mux_tree_tapbuf_size16_1_sram[1]:49 0.0001367201 +50 mux_tree_tapbuf_size16_1_sram[1]:50 0.0001842591 +51 mux_tree_tapbuf_size16_1_sram[1]:51 0.0002932269 +52 mux_tree_tapbuf_size16_1_sram[1]:52 0.0002499203 +53 mux_tree_tapbuf_size16_1_sram[1]:53 0.0002499203 +54 mux_tree_tapbuf_size16_1_sram[1]:54 5.309388e-05 +55 mux_tree_tapbuf_size16_1_sram[1]:55 4.90457e-05 +56 mux_tree_tapbuf_size16_1_sram[1]:56 4.611323e-05 +57 mux_tree_tapbuf_size16_1_sram[1]:57 4.233931e-05 +58 mux_tree_tapbuf_size16_1_sram[1]:31 prog_clk[0]:186 7.132212e-06 +59 mux_tree_tapbuf_size16_1_sram[1]:30 prog_clk[0]:187 7.132212e-06 +60 mux_tree_tapbuf_size16_1_sram[1]:52 prog_clk[0]:158 0.0001674615 +61 mux_tree_tapbuf_size16_1_sram[1]:52 prog_clk[0]:159 0.0002208813 +62 mux_tree_tapbuf_size16_1_sram[1]:53 prog_clk[0]:154 0.0001674615 +63 mux_tree_tapbuf_size16_1_sram[1]:53 prog_clk[0]:158 0.0002208813 +64 mux_tree_tapbuf_size16_1_sram[1]:52 right_top_grid_pin_48_[0]:18 0.0004673173 +65 mux_tree_tapbuf_size16_1_sram[1]:54 right_top_grid_pin_48_[0]:20 8.359169e-07 +66 mux_tree_tapbuf_size16_1_sram[1]:53 right_top_grid_pin_48_[0]:19 0.0004673173 +67 mux_tree_tapbuf_size16_1_sram[1]:55 right_top_grid_pin_48_[0]:21 8.359169e-07 +68 mux_tree_tapbuf_size16_1_sram[1]:49 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 3.424903e-05 +69 mux_tree_tapbuf_size16_1_sram[1]:46 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.325705e-05 +70 mux_tree_tapbuf_size16_1_sram[1]:50 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 3.424903e-05 +71 mux_tree_tapbuf_size16_1_sram[1]:51 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.325705e-05 +72 mux_tree_tapbuf_size16_1_sram[1]:36 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.920895e-05 +73 mux_tree_tapbuf_size16_1_sram[1]:35 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.920895e-05 +74 mux_tree_tapbuf_size16_1_sram[1]:32 optlc_net_151:21 1.617059e-07 +75 mux_tree_tapbuf_size16_1_sram[1]:45 optlc_net_151:28 7.590032e-06 +76 mux_tree_tapbuf_size16_1_sram[1]:41 optlc_net_151:26 5.328571e-05 +77 mux_tree_tapbuf_size16_1_sram[1]:43 optlc_net_151:29 3.832351e-05 +78 mux_tree_tapbuf_size16_1_sram[1]:42 optlc_net_151:26 2.641416e-05 +79 mux_tree_tapbuf_size16_1_sram[1]:42 optlc_net_151:30 2.59411e-05 +80 mux_tree_tapbuf_size16_1_sram[1]:42 optlc_net_151:27 5.328571e-05 +81 mux_tree_tapbuf_size16_1_sram[1]:44 optlc_net_151:29 7.590032e-06 +82 mux_tree_tapbuf_size16_1_sram[1]:44 optlc_net_151:28 3.832351e-05 +83 mux_tree_tapbuf_size16_1_sram[1]:38 optlc_net_151:27 1.786923e-05 +84 mux_tree_tapbuf_size16_1_sram[1]:37 optlc_net_151:26 1.786923e-05 +85 mux_tree_tapbuf_size16_1_sram[1]:11 optlc_net_151:33 2.59411e-05 +86 mux_tree_tapbuf_size16_1_sram[1]:11 optlc_net_151:27 2.641416e-05 +87 mux_tree_tapbuf_size16_1_sram[1]:23 optlc_net_151:18 1.819955e-05 +88 mux_tree_tapbuf_size16_1_sram[1]:24 optlc_net_151:19 1.819955e-05 +89 mux_tree_tapbuf_size16_1_sram[1]:25 optlc_net_151:18 2.714385e-06 +90 mux_tree_tapbuf_size16_1_sram[1]:25 optlc_net_151:19 0.000121262 +91 mux_tree_tapbuf_size16_1_sram[1]:26 optlc_net_151:20 0.000121262 +92 mux_tree_tapbuf_size16_1_sram[1]:26 optlc_net_151:19 2.714385e-06 +93 mux_tree_tapbuf_size16_1_sram[1]:27 optlc_net_151:20 1.617059e-07 +94 mux_tree_tapbuf_size16_1_sram[1]:21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 1.561159e-05 +95 mux_tree_tapbuf_size16_1_sram[1]:21 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.000205036 +96 mux_tree_tapbuf_size16_1_sram[1]:20 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 1.561159e-05 +97 mux_tree_tapbuf_size16_1_sram[1]:22 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.000205036 +98 mux_tree_tapbuf_size16_1_sram[1]:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001927001 +99 mux_tree_tapbuf_size16_1_sram[1]:26 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001927001 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size16_1_sram[1]:57 0.152 +1 mux_tree_tapbuf_size16_1_sram[1]:49 mux_right_track_4\/mux_l2_in_4_:S 0.152 +2 mux_tree_tapbuf_size16_1_sram[1]:15 mux_right_track_4\/mux_l2_in_0_:S 0.152 +3 mux_tree_tapbuf_size16_1_sram[1]:16 mux_tree_tapbuf_size16_1_sram[1]:15 0.0045 +4 mux_tree_tapbuf_size16_1_sram[1]:18 mux_tree_tapbuf_size16_1_sram[1]:17 0.0045 +5 mux_tree_tapbuf_size16_1_sram[1]:17 mux_tree_tapbuf_size16_1_sram[1]:16 0.0078125 +6 mux_tree_tapbuf_size16_1_sram[1]:47 mux_right_track_4\/mux_l2_in_2_:S 0.152 +7 mux_tree_tapbuf_size16_1_sram[1]:34 mux_right_track_4\/mux_l2_in_6_:S 0.152 +8 mux_tree_tapbuf_size16_1_sram[1]:34 mux_tree_tapbuf_size16_1_sram[1]:33 0.0003482143 +9 mux_tree_tapbuf_size16_1_sram[1]:34 mux_tree_tapbuf_size16_1_sram[1]:14 0.0002589286 +10 mux_tree_tapbuf_size16_1_sram[1]:32 mux_tree_tapbuf_size16_1_sram[1]:31 0.0045 +11 mux_tree_tapbuf_size16_1_sram[1]:32 mux_tree_tapbuf_size16_1_sram[1]:27 0.009446429 +12 mux_tree_tapbuf_size16_1_sram[1]:31 mux_tree_tapbuf_size16_1_sram[1]:30 0.002044643 +13 mux_tree_tapbuf_size16_1_sram[1]:29 mux_tree_tapbuf_size16_1_sram[1]:28 9.51087e-05 +14 mux_tree_tapbuf_size16_1_sram[1]:30 mux_tree_tapbuf_size16_1_sram[1]:29 0.0045 +15 mux_tree_tapbuf_size16_1_sram[1]:28 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size16_1_sram[1]:45 mux_tree_tapbuf_size16_1_sram[1]:44 0.0006919643 +17 mux_tree_tapbuf_size16_1_sram[1]:46 mux_tree_tapbuf_size16_1_sram[1]:45 0.0045 +18 mux_tree_tapbuf_size16_1_sram[1]:40 mux_tree_tapbuf_size16_1_sram[1]:39 0.001140625 +19 mux_tree_tapbuf_size16_1_sram[1]:41 mux_tree_tapbuf_size16_1_sram[1]:40 0.0045 +20 mux_tree_tapbuf_size16_1_sram[1]:43 mux_tree_tapbuf_size16_1_sram[1]:42 0.0045 +21 mux_tree_tapbuf_size16_1_sram[1]:42 mux_tree_tapbuf_size16_1_sram[1]:41 0.00178125 +22 mux_tree_tapbuf_size16_1_sram[1]:42 mux_tree_tapbuf_size16_1_sram[1]:11 0.002995536 +23 mux_tree_tapbuf_size16_1_sram[1]:50 mux_tree_tapbuf_size16_1_sram[1]:49 0.001997768 +24 mux_tree_tapbuf_size16_1_sram[1]:50 mux_tree_tapbuf_size16_1_sram[1]:48 4.017857e-05 +25 mux_tree_tapbuf_size16_1_sram[1]:50 mux_tree_tapbuf_size16_1_sram[1]:47 0.0003214286 +26 mux_tree_tapbuf_size16_1_sram[1]:51 mux_tree_tapbuf_size16_1_sram[1]:50 0.0045 +27 mux_tree_tapbuf_size16_1_sram[1]:51 mux_tree_tapbuf_size16_1_sram[1]:46 0.004816964 +28 mux_tree_tapbuf_size16_1_sram[1]:44 mux_right_track_4\/mux_l2_in_7_:S 0.152 +29 mux_tree_tapbuf_size16_1_sram[1]:44 mux_tree_tapbuf_size16_1_sram[1]:43 0.005799107 +30 mux_tree_tapbuf_size16_1_sram[1]:39 mux_tree_tapbuf_size16_1_sram[1]:38 0.0045 +31 mux_tree_tapbuf_size16_1_sram[1]:39 mux_tree_tapbuf_size16_1_sram[1]:13 8.928572e-05 +32 mux_tree_tapbuf_size16_1_sram[1]:39 mux_tree_tapbuf_size16_1_sram[1]:12 0.0001142242 +33 mux_tree_tapbuf_size16_1_sram[1]:38 mux_tree_tapbuf_size16_1_sram[1]:37 0.002348214 +34 mux_tree_tapbuf_size16_1_sram[1]:36 mux_tree_tapbuf_size16_1_sram[1]:35 0.002035714 +35 mux_tree_tapbuf_size16_1_sram[1]:37 mux_tree_tapbuf_size16_1_sram[1]:36 0.0045 +36 mux_tree_tapbuf_size16_1_sram[1]:21 mux_right_track_4\/mux_l2_in_5_:S 0.152 +37 mux_tree_tapbuf_size16_1_sram[1]:21 mux_tree_tapbuf_size16_1_sram[1]:20 0.0003214286 +38 mux_tree_tapbuf_size16_1_sram[1]:52 mux_tree_tapbuf_size16_1_sram[1]:51 0.00341 +39 mux_tree_tapbuf_size16_1_sram[1]:54 mux_tree_tapbuf_size16_1_sram[1]:53 0.00341 +40 mux_tree_tapbuf_size16_1_sram[1]:53 mux_tree_tapbuf_size16_1_sram[1]:52 0.001583117 +41 mux_tree_tapbuf_size16_1_sram[1]:56 mux_tree_tapbuf_size16_1_sram[1]:55 0.0045 +42 mux_tree_tapbuf_size16_1_sram[1]:55 mux_tree_tapbuf_size16_1_sram[1]:54 0.0001057692 +43 mux_tree_tapbuf_size16_1_sram[1]:57 mux_tree_tapbuf_size16_1_sram[1]:56 8.695653e-05 +44 mux_tree_tapbuf_size16_1_sram[1]:12 mux_right_track_4\/mux_l2_in_3_:S 0.152 +45 mux_tree_tapbuf_size16_1_sram[1]:10 mux_right_track_4\/mux_l2_in_1_:S 0.152 +46 mux_tree_tapbuf_size16_1_sram[1]:11 mux_tree_tapbuf_size16_1_sram[1]:10 0.0045 +47 mux_tree_tapbuf_size16_1_sram[1]:19 mux_tree_tapbuf_size16_1_sram[1]:18 0.002424107 +48 mux_tree_tapbuf_size16_1_sram[1]:20 mux_tree_tapbuf_size16_1_sram[1]:19 0.0003035715 +49 mux_tree_tapbuf_size16_1_sram[1]:22 mux_tree_tapbuf_size16_1_sram[1]:21 0.005017857 +50 mux_tree_tapbuf_size16_1_sram[1]:23 mux_tree_tapbuf_size16_1_sram[1]:22 0.0003035715 +51 mux_tree_tapbuf_size16_1_sram[1]:24 mux_tree_tapbuf_size16_1_sram[1]:23 0.0008214285 +52 mux_tree_tapbuf_size16_1_sram[1]:25 mux_tree_tapbuf_size16_1_sram[1]:24 0.0003035715 +53 mux_tree_tapbuf_size16_1_sram[1]:26 mux_tree_tapbuf_size16_1_sram[1]:25 0.009035715 +54 mux_tree_tapbuf_size16_1_sram[1]:27 mux_tree_tapbuf_size16_1_sram[1]:26 0.0003035715 +55 mux_tree_tapbuf_size16_1_sram[1]:33 mux_tree_tapbuf_size16_1_sram[1]:32 0.00525 +56 mux_tree_tapbuf_size16_1_sram[1]:35 mux_tree_tapbuf_size16_1_sram[1]:34 0.0002589286 + +*END + +*D_NET optlc_net_147 0.009005654 //LENGTH 52.790 LUMPCC 0.002327294 DR + +*CONN +*I optlc_139:HI O *L 0 *C 35.420 42.840 +*I mux_bottom_track_17\/mux_l2_in_3_:A0 I *L 0.001631 *C 49.050 42.840 +*I mux_top_track_16\/mux_l2_in_3_:A0 I *L 0.001631 *C 49.050 47.940 +*I mux_bottom_track_5\/mux_l2_in_7_:A0 I *L 0.001631 *C 32.835 39.100 +*I mux_bottom_track_33\/mux_l1_in_3_:A0 I *L 0.001631 *C 21.450 53.380 +*I mux_bottom_track_25\/mux_l2_in_3_:A0 I *L 0.001631 *C 29.615 49.640 +*N optlc_net_147:6 *C 29.490 49.640 +*N optlc_net_147:7 *C 21.450 53.380 +*N optlc_net_147:8 *C 21.620 53.380 +*N optlc_net_147:9 *C 21.620 53.335 +*N optlc_net_147:10 *C 21.620 49.685 +*N optlc_net_147:11 *C 21.665 49.640 +*N optlc_net_147:12 *C 29.395 49.640 +*N optlc_net_147:13 *C 29.440 49.595 +*N optlc_net_147:14 *C 29.440 42.545 +*N optlc_net_147:15 *C 29.485 42.500 +*N optlc_net_147:16 *C 32.835 39.100 +*N optlc_net_147:17 *C 33.120 39.100 +*N optlc_net_147:18 *C 33.120 39.145 +*N optlc_net_147:19 *C 33.120 42.455 +*N optlc_net_147:20 *C 33.120 42.500 +*N optlc_net_147:21 *C 49.050 47.940 +*N optlc_net_147:22 *C 48.760 47.940 +*N optlc_net_147:23 *C 48.760 47.895 +*N optlc_net_147:24 *C 49.050 42.840 +*N optlc_net_147:25 *C 48.760 42.840 +*N optlc_net_147:26 *C 48.760 42.840 +*N optlc_net_147:27 *C 48.760 42.218 +*N optlc_net_147:28 *C 48.753 42.160 +*N optlc_net_147:29 *C 34.508 42.160 +*N optlc_net_147:30 *C 34.500 42.160 +*N optlc_net_147:31 *C 34.500 42.500 +*N optlc_net_147:32 *C 34.500 42.530 +*N optlc_net_147:33 *C 34.500 42.840 +*N optlc_net_147:34 *C 35.383 42.840 + +*CAP +0 optlc_139:HI 1e-06 +1 mux_bottom_track_17\/mux_l2_in_3_:A0 1e-06 +2 mux_top_track_16\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_track_5\/mux_l2_in_7_:A0 1e-06 +4 mux_bottom_track_33\/mux_l1_in_3_:A0 1e-06 +5 mux_bottom_track_25\/mux_l2_in_3_:A0 1e-06 +6 optlc_net_147:6 2.406075e-05 +7 optlc_net_147:7 4.677424e-05 +8 optlc_net_147:8 5.134181e-05 +9 optlc_net_147:9 0.0002527192 +10 optlc_net_147:10 0.0002527192 +11 optlc_net_147:11 0.0004310029 +12 optlc_net_147:12 0.0004550636 +13 optlc_net_147:13 0.0005491069 +14 optlc_net_147:14 0.0005491069 +15 optlc_net_147:15 0.0001607392 +16 optlc_net_147:16 5.520687e-05 +17 optlc_net_147:17 6.000276e-05 +18 optlc_net_147:18 0.0002086728 +19 optlc_net_147:19 0.0002086728 +20 optlc_net_147:20 0.0002516191 +21 optlc_net_147:21 5.419977e-05 +22 optlc_net_147:22 5.80338e-05 +23 optlc_net_147:23 0.000341816 +24 optlc_net_147:24 5.47784e-05 +25 optlc_net_147:25 5.973154e-05 +26 optlc_net_147:26 0.0004386359 +27 optlc_net_147:27 6.239177e-05 +28 optlc_net_147:28 0.0008213662 +29 optlc_net_147:29 0.0008213662 +30 optlc_net_147:30 5.153392e-05 +31 optlc_net_147:31 4.720326e-05 +32 optlc_net_147:32 9.133769e-05 +33 optlc_net_147:33 0.0001213847 +34 optlc_net_147:34 9.177135e-05 +35 optlc_net_147:28 chanx_right_in[13]:27 0.000788347 +36 optlc_net_147:29 chanx_right_in[13]:15 0.000788347 +37 optlc_net_147:34 mux_tree_tapbuf_size10_8_sram[3]:6 1.29373e-06 +38 optlc_net_147:15 mux_tree_tapbuf_size10_8_sram[3]:5 0.0001412925 +39 optlc_net_147:30 mux_tree_tapbuf_size10_8_sram[3]:7 1.000004e-05 +40 optlc_net_147:32 mux_tree_tapbuf_size10_8_sram[3]:6 5.727161e-05 +41 optlc_net_147:31 mux_tree_tapbuf_size10_8_sram[3]:8 1.000004e-05 +42 optlc_net_147:20 mux_tree_tapbuf_size10_8_sram[3]:5 5.727161e-05 +43 optlc_net_147:20 mux_tree_tapbuf_size10_8_sram[3]:6 0.0001412925 +44 optlc_net_147:19 mux_tree_tapbuf_size10_8_sram[3]:8 1.585253e-06 +45 optlc_net_147:18 mux_tree_tapbuf_size10_8_sram[3]:7 1.585253e-06 +46 optlc_net_147:33 mux_tree_tapbuf_size10_8_sram[3]:5 1.29373e-06 +47 optlc_net_147:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001638565 +48 optlc_net_147:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001638565 + +*RES +0 optlc_139:HI optlc_net_147:34 0.152 +1 optlc_net_147:34 optlc_net_147:33 0.0007879465 +2 optlc_net_147:12 optlc_net_147:11 0.006901786 +3 optlc_net_147:12 optlc_net_147:6 8.482144e-05 +4 optlc_net_147:13 optlc_net_147:12 0.0045 +5 optlc_net_147:15 optlc_net_147:14 0.0045 +6 optlc_net_147:14 optlc_net_147:13 0.006294644 +7 optlc_net_147:22 optlc_net_147:21 0.0001576087 +8 optlc_net_147:23 optlc_net_147:22 0.0045 +9 optlc_net_147:21 mux_top_track_16\/mux_l2_in_3_:A0 0.152 +10 optlc_net_147:6 mux_bottom_track_25\/mux_l2_in_3_:A0 0.152 +11 optlc_net_147:25 optlc_net_147:24 0.0001576087 +12 optlc_net_147:26 optlc_net_147:25 0.0045 +13 optlc_net_147:26 optlc_net_147:23 0.004513393 +14 optlc_net_147:24 mux_bottom_track_17\/mux_l2_in_3_:A0 0.152 +15 optlc_net_147:27 optlc_net_147:26 0.0005558036 +16 optlc_net_147:28 optlc_net_147:27 0.00341 +17 optlc_net_147:30 optlc_net_147:29 0.00341 +18 optlc_net_147:29 optlc_net_147:28 0.002231717 +19 optlc_net_147:32 optlc_net_147:31 0.0045 +20 optlc_net_147:32 optlc_net_147:20 0.001232143 +21 optlc_net_147:31 optlc_net_147:30 0.0001634615 +22 optlc_net_147:20 optlc_net_147:19 0.0045 +23 optlc_net_147:20 optlc_net_147:15 0.003245536 +24 optlc_net_147:19 optlc_net_147:18 0.002955357 +25 optlc_net_147:17 optlc_net_147:16 0.0001548913 +26 optlc_net_147:18 optlc_net_147:17 0.0045 +27 optlc_net_147:16 mux_bottom_track_5\/mux_l2_in_7_:A0 0.152 +28 optlc_net_147:11 optlc_net_147:10 0.0045 +29 optlc_net_147:10 optlc_net_147:9 0.003258929 +30 optlc_net_147:8 optlc_net_147:7 9.239132e-05 +31 optlc_net_147:9 optlc_net_147:8 0.0045 +32 optlc_net_147:7 mux_bottom_track_33\/mux_l1_in_3_:A0 0.152 +33 optlc_net_147:33 optlc_net_147:32 0.0002767857 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006961968 //LENGTH 4.605 LUMPCC 0.0003274154 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 94.125 107.100 +*I mux_right_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 98.440 107.100 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 98.403 107.100 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 94.163 107.100 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001833907 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001833907 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size12_2_sram[1]:16 0.0001187989 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size12_2_sram[1]:17 0.0001187989 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size12_2_sram[2]:9 4.490884e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size12_2_sram[2]:8 4.490884e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003785715 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.004194816 //LENGTH 23.155 LUMPCC 0.002214176 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_4_:X O *L 0 *C 92.745 90.440 +*I mux_right_track_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 111.880 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 111.880 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 111.780 88.400 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 108.605 88.400 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 108.560 88.445 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 108.560 89.023 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 108.553 89.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 93.388 89.080 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 93.380 89.138 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 93.380 90.395 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 93.335 90.440 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 92.782 90.440 + +*CAP +0 mux_right_track_2\/mux_l1_in_4_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_2_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.359096e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002323608 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002060318 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.305369e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.305369e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0005298028 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0005298028 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 9.706896e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 9.706896e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 6.340288e-05 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 6.340288e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[13]:16 0.0001187706 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[13]:17 0.0007278301 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chanx_left_in[13]:17 0.0001187706 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chanx_left_in[13]:22 0.0007278301 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size12_0_sram[0]:39 0.0002604871 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size12_0_sram[0]:38 0.0002604871 + +*RES +0 mux_right_track_2\/mux_l1_in_4_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_2\/mux_l2_in_2_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002834822 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0005156249 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00237585 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.001122768 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0004933036 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001548374 //LENGTH 11.210 LUMPCC 0.000552053 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_3_:X O *L 0 *C 85.845 34.000 +*I mux_bottom_track_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 88.495 26.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 88.458 26.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 86.065 26.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 86.020 26.225 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 86.020 33.955 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 86.020 34.000 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 85.845 34.000 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.778106e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.778106e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0003779356 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0003779356 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.052287e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.236459e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 chany_top_in[12]:21 0.000104489 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 chany_top_in[12]:20 0.000104489 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:137 5.647837e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:136 5.647837e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.035285e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.035285e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.470631e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.470631e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_3_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_1\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002136161 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.006901786 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.510869e-05 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0007087148 //LENGTH 5.190 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_1_:X O *L 0 *C 20.525 85.000 +*I mux_left_track_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 22.340 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 22.340 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 22.080 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 22.080 82.325 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 22.080 84.955 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 22.035 85.000 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 20.562 85.000 + +*CAP +0 mux_left_track_1\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 6.142211e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 6.427899e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001660592 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001660592 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0001244477 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0001244477 + +*RES +0 mux_left_track_1\/mux_l3_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.001314732 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.002348214 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0001413044 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_1\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.004192166 //LENGTH 27.200 LUMPCC 0.001169537 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_0_:X O *L 0 *C 42.955 83.300 +*I mux_left_track_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 21.985 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 22.023 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 24.335 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 24.380 83.255 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 24.380 82.338 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 24.388 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 26.680 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 26.680 81.600 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 32.200 81.600 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 32.200 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 37.253 82.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 *C 37.260 82.338 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 *C 37.260 83.255 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 *C 37.305 83.300 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 *C 42.918 83.300 + +*CAP +0 mux_left_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001990892 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001990892 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.21714e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 6.21714e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001504079 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0002173173 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00046403 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004582879 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0003615818 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0003004144 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0001026003 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0001026003 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0001704337 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0001704337 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:619 2.966575e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:622 2.966575e-05 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:618 5.181561e-05 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:617 5.181561e-05 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:619 8.644603e-06 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:493 2.349972e-05 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:618 3.676932e-06 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:622 8.644603e-06 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:492 2.349972e-05 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:617 3.676932e-06 +26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_tree_tapbuf_size12_6_sram[1]:32 9.82643e-05 +27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size12_6_sram[1]:14 2.084811e-05 +28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size12_6_sram[1]:33 4.256824e-05 +29 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size12_6_sram[1]:15 2.084811e-05 +30 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size12_6_sram[1]:32 4.256824e-05 +31 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_tree_tapbuf_size12_6_sram[1]:33 9.82643e-05 +32 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_tree_tapbuf_size12_6_sram[2]:16 0.0002177827 +33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_tree_tapbuf_size12_6_sram[2]:4 0.0002177827 +34 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.80024e-05 +35 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.80024e-05 + +*RES +0 mux_left_track_1\/mux_l3_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_1\/mux_l4_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.002064732 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0008191965 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.00341 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0007915582 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 0.0045 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:12 0.0008191965 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.005011161 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0003591583 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001065333 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0008648 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001065333 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001031538 //LENGTH 7.500 LUMPCC 0.0002872642 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_2_:X O *L 0 *C 35.705 112.200 +*I mux_top_track_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 34.040 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 34.040 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 34.040 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 34.500 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 34.500 112.155 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 34.545 112.200 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 35.668 112.200 + +*CAP +0 mux_top_track_4\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.996537e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.8453e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002321561 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001997973 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001059509 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001059509 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:30 0.0001387189 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size16_0_sram[2]:26 4.913185e-06 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size16_0_sram[2]:29 0.0001436321 + +*RES +0 mux_top_track_4\/mux_l2_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001002232 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004513393 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4\/mux_l3_in_1_:A1 0.152 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004107143 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0] 0.0004934961 //LENGTH 3.785 LUMPCC 0.0001077656 DR + +*CONN +*I mux_right_track_4\/mux_l4_in_0_:X O *L 0 *C 124.485 74.460 +*I mux_right_track_4\/mux_l5_in_0_:A1 I *L 0.00198 *C 127.980 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 127.943 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 124.523 74.460 + +*CAP +0 mux_right_track_4\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l5_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0001918653 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0001918653 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 5.388279e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 5.388279e-05 + +*RES +0 mux_right_track_4\/mux_l4_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_right_track_4\/mux_l5_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.003053572 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0009061322 //LENGTH 7.410 LUMPCC 0.000120395 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_7_:X O *L 0 *C 119.775 80.240 +*I mux_right_track_4\/mux_l3_in_3_:A0 I *L 0.001631 *C 118.395 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 118.433 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 119.095 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 119.140 75.185 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 119.140 80.195 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 119.185 80.240 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 119.738 80.240 + +*CAP +0 mux_right_track_4\/mux_l2_in_7_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_3_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.500572e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.500572e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002527669 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002527669 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.409594e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.409594e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:166 3.145078e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 prog_clk[0]:169 2.87467e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:160 3.145078e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 prog_clk[0]:166 2.87467e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_7_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_4\/mux_l3_in_3_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0005915179 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004298677 //LENGTH 2.260 LUMPCC 8.751261e-05 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_1_:X O *L 0 *C 38.925 38.760 +*I mux_bottom_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 39.275 37.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.275 37.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.100 37.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 39.100 37.445 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.100 38.715 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.100 38.760 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 38.925 38.760 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.499566e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.474038e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.240753e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.240753e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.580804e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.99959e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.375631e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.375631e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.51087e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005256907 //LENGTH 3.170 LUMPCC 0.0001057002 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_4_:X O *L 0 *C 22.715 90.440 +*I mux_left_track_5\/mux_l3_in_2_:A1 I *L 0.00198 *C 21.985 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 22.023 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 22.495 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 22.540 88.785 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 22.540 90.395 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 22.540 90.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 22.715 90.440 + +*CAP +0 mux_left_track_5\/mux_l2_in_4_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_2_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.010284e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.010284e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.549721e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.549721e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.320085e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.358944e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 2.341448e-07 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 2.341448e-07 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.261597e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.261597e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_4_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5\/mux_l3_in_2_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000421875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0014375 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00882129 //LENGTH 44.885 LUMPCC 0.004941275 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_0_:X O *L 0 *C 53.645 91.120 +*I mux_top_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 55.660 50.660 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 53.880 87.720 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 55.660 50.660 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 55.660 50.705 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 55.660 51.623 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 55.653 51.680 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 54.300 51.680 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 54.280 51.688 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 54.280 87.713 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 54.280 87.720 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 54.280 87.778 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 54.280 91.075 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 54.235 91.120 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 53.683 91.120 + +*CAP +0 mux_top_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001132633 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.278122e-05 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.664153e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.664153e-05 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001838576 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001838576 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.001212868 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.001212868 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001132633 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0002521859 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0002521859 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:13 7.380007e-05 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:14 7.380007e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[17]:13 0.0008633768 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[17]:12 0.0008633768 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[18]:43 0.0004817877 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[18]:42 0.0004817877 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.001125473 +20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.001125473 + +*RES +0 mux_top_track_16\/mux_l1_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0008191965 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002118916 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.00341 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.69697e-05 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.005643916 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.00341 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0045 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.002944197 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0004933036 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006399077 //LENGTH 3.620 LUMPCC 0.000154586 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_3_:X O *L 0 *C 55.375 66.980 +*I mux_top_track_24\/mux_l3_in_1_:A0 I *L 0.001631 *C 55.835 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 55.835 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 55.660 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 55.660 69.655 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 55.660 67.025 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 55.660 66.980 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 55.375 66.980 + +*CAP +0 mux_top_track_24\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.43163e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.010077e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001258619 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001258619 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.028543e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.689539e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:8 7.729301e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:11 7.729301e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_3_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_24\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006929482 //LENGTH 4.245 LUMPCC 0.0003226419 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_0_:X O *L 0 *C 75.265 58.140 +*I mux_right_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 79.220 58.140 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 79.183 58.140 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.303 58.140 + +*CAP +0 mux_right_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001841531 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001841531 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[9]:29 9.71878e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[9]:30 9.71878e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_4_sram[1]:7 6.413316e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_4_sram[1]:6 6.413316e-05 + +*RES +0 mux_right_track_16\/mux_l1_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003464286 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0] 0.003761743 //LENGTH 18.280 LUMPCC 0.002031137 DR + +*CONN +*I mux_right_track_16\/mux_l3_in_0_:X O *L 0 *C 82.165 46.920 +*I mux_right_track_16\/mux_l4_in_0_:A1 I *L 0.00198 *C 97.620 45.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 97.620 45.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 97.520 45.560 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 97.520 45.560 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 97.513 45.560 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 83.267 45.560 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 83.260 45.617 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 83.260 46.875 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 83.215 46.920 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 82.203 46.920 + +*CAP +0 mux_right_track_16\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.987027e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.582361e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.170138e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0005587256 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0005587256 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:7 9.713563e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:8 9.713563e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001147442 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001147442 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_right_in[8]:28 0.00075715 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_right_in[8]:29 0.00075715 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_left_in[17]:17 0.000152947 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chanx_left_in[17]:25 0.0001054717 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_left_in[17]:13 0.000152947 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chanx_left_in[17]:17 0.0001054717 + +*RES +0 mux_right_track_16\/mux_l3_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0009040179 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.001122768 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00341 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002231716 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.00341 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001847826 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_16\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001575456 //LENGTH 12.930 LUMPCC 0.0002673356 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_1_:X O *L 0 *C 90.905 36.380 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 94.935 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 94.898 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 91.125 28.220 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 91.080 28.265 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 91.080 36.335 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 91.080 36.380 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 90.905 36.380 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001943259 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001943259 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000400805 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000400805 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.846773e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.739045e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.603401e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.603401e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.968643e-06 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.968643e-06 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.966515e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.966515e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003368304 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.007205358 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001040636 //LENGTH 8.825 LUMPCC 0.0001026939 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_2_:X O *L 0 *C 46.285 42.500 +*I mux_bottom_track_17\/mux_l3_in_1_:A1 I *L 0.00198 *C 44.620 36.380 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 44.620 36.380 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 44.620 36.720 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 45.035 36.720 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 45.080 36.765 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 45.080 42.455 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 45.125 42.500 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 46.248 42.500 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.395746e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.111132e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.443772e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000304102 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000304102 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.911574e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 9.911574e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.557987e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 2.57671e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.557987e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 2.57671e-05 + +*RES +0 mux_bottom_track_17\/mux_l2_in_2_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001002232 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.005080358 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003705358 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_17\/mux_l3_in_1_:A1 0.152 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0003451012 //LENGTH 2.305 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l3_in_0_:X O *L 0 *C 42.035 45.295 +*I mux_bottom_track_25\/mux_l4_in_0_:A1 I *L 0.00198 *C 40.020 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 40.058 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 42.035 45.295 + +*CAP +0 mux_bottom_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001494092 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001936921 + +*RES +0 mux_bottom_track_25\/mux_l3_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001765625 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_25\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001663387 //LENGTH 12.920 LUMPCC 0.0003875164 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_0_:X O *L 0 *C 42.035 69.700 +*I mux_left_track_9\/mux_l4_in_0_:A1 I *L 0.00198 *C 34.500 74.460 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 34.500 74.460 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 34.500 74.415 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 34.500 69.745 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 34.545 69.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 41.998 69.700 + +*CAP +0 mux_left_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.447128e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001831449 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001831449 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0004365545 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004365545 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_9_sram[2]:12 7.299575e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_9_sram[2]:11 7.299575e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_9_sram[3]:6 0.0001205539 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_9_sram[3]:11 2.085451e-07 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_9_sram[3]:7 0.0001205539 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_9_sram[3]:10 2.085451e-07 + +*RES +0 mux_left_track_9\/mux_l3_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.006654018 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.004169643 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_9\/mux_l4_in_0_:A1 0.152 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008919917 //LENGTH 6.340 LUMPCC 0.000243895 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_3_:X O *L 0 *C 28.345 66.300 +*I mux_left_track_17\/mux_l3_in_1_:A0 I *L 0.001631 *C 28.235 60.860 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 28.235 60.860 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 28.520 60.860 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 28.520 60.905 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 28.520 66.255 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 28.520 66.300 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 28.345 66.300 + +*CAP +0 mux_left_track_17\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.161139e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.710445e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002096477 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002096477 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.135266e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.673282e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[10]:22 3.720609e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[10]:23 3.720609e-05 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.167818e-06 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.167818e-06 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.930653e-05 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.267085e-06 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.930653e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 1.267085e-06 + +*RES +0 mux_left_track_17\/mux_l2_in_3_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_17\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001548913 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004776786 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0] 0.00320163 //LENGTH 26.045 LUMPCC 0.0004354662 DR + +*CONN +*I mux_left_track_25\/mux_l4_in_0_:X O *L 0 *C 13.975 60.520 +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.335 44.715 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 5.335 44.715 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 5.935 44.880 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 5.980 44.925 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 5.980 55.375 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 6.025 55.420 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 14.215 55.420 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 14.260 55.465 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 14.260 60.475 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 14.260 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 13.975 60.520 + +*CAP +0 mux_left_track_25\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 8.605445e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.250083e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0004765734 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0004765734 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0004934158 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0004934158 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0002820696 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0002820696 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 6.541526e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.607581e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 prog_clk[0]:706 0.0001302315 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 prog_clk[0]:691 6.955436e-06 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 prog_clk[0]:679 0.0001302315 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 prog_clk[0]:692 6.955436e-06 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:690 3.888726e-06 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 prog_clk[0]:694 7.992179e-06 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:689 3.888726e-06 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 prog_clk[0]:693 7.992179e-06 +20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 ropt_net_240:3 6.866527e-05 +21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 ropt_net_240:2 6.866527e-05 + +*RES +0 mux_left_track_25\/mux_l4_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0005357143 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.009330357 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0073125 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0045 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0045 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.004473215 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003045031 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_1_:X O *L 0 *C 24.095 33.660 +*I mux_bottom_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 21.910 33.660 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 21.948 33.660 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 24.058 33.660 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001512516 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001512516 + +*RES +0 mux_bottom_track_33\/mux_l1_in_1_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001883929 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000309566 //LENGTH 2.475 LUMPCC 7.332384e-05 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_1_:X O *L 0 *C 22.715 69.700 +*I mux_left_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 20.530 69.700 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 20.568 69.700 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.678 69.700 + +*CAP +0 mux_left_track_33\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001171211 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001171211 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.666192e-05 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.666192e-05 + +*RES +0 mux_left_track_33\/mux_l1_in_1_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_33\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001883929 + +*END + +*D_NET chany_bottom_out[13] 0.001205023 //LENGTH 9.650 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_846:X O *L 0 *C 67.355 4.760 +*P chany_bottom_out[13] O *L 0.7423 *C 61.640 1.290 +*N chany_bottom_out[13]:2 *C 61.640 4.715 +*N chany_bottom_out[13]:3 *C 61.685 4.760 +*N chany_bottom_out[13]:4 *C 67.318 4.760 + +*CAP +0 ropt_mt_inst_846:X 1e-06 +1 chany_bottom_out[13] 0.0002096388 +2 chany_bottom_out[13]:2 0.0002096388 +3 chany_bottom_out[13]:3 0.0003923726 +4 chany_bottom_out[13]:4 0.0003923726 + +*RES +0 ropt_mt_inst_846:X chany_bottom_out[13]:4 0.152 +1 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.005029019 +2 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.0045 +3 chany_bottom_out[13]:2 chany_bottom_out[13] 0.003058036 + +*END + +*D_NET ropt_net_187 0.0007222137 //LENGTH 5.425 LUMPCC 0.000120197 DR + +*CONN +*I FTB_14__13:X O *L 0 *C 8.740 78.200 +*I ropt_mt_inst_826:A I *L 0.001766 *C 5.980 80.240 +*N ropt_net_187:2 *C 6.018 80.240 +*N ropt_net_187:3 *C 8.695 80.240 +*N ropt_net_187:4 *C 8.740 80.195 +*N ropt_net_187:5 *C 8.740 78.245 +*N ropt_net_187:6 *C 8.740 78.200 + +*CAP +0 FTB_14__13:X 1e-06 +1 ropt_mt_inst_826:A 1e-06 +2 ropt_net_187:2 0.000146431 +3 ropt_net_187:3 0.000146431 +4 ropt_net_187:4 0.000134513 +5 ropt_net_187:5 0.000134513 +6 ropt_net_187:6 3.81286e-05 +7 ropt_net_187:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 6.009851e-05 +8 ropt_net_187:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 6.009851e-05 + +*RES +0 FTB_14__13:X ropt_net_187:6 0.152 +1 ropt_net_187:2 ropt_mt_inst_826:A 0.152 +2 ropt_net_187:3 ropt_net_187:2 0.002390625 +3 ropt_net_187:4 ropt_net_187:3 0.0045 +4 ropt_net_187:6 ropt_net_187:5 0.0045 +5 ropt_net_187:5 ropt_net_187:4 0.001741072 + +*END + +*D_NET chany_bottom_out[3] 0.0003986162 //LENGTH 2.775 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 69.000 3.400 +*P chany_bottom_out[3] O *L 0.7423 *C 69.000 1.325 +*N chany_bottom_out[3]:2 *C 69.400 3.400 +*N chany_bottom_out[3]:3 *C 69.000 3.355 +*N chany_bottom_out[3]:4 *C 69.038 3.400 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chany_bottom_out[3] 0.0001453459 +2 chany_bottom_out[3]:2 5.346219e-05 +3 chany_bottom_out[3]:3 0.0001453459 +4 chany_bottom_out[3]:4 5.346219e-05 + +*RES +0 ropt_mt_inst_797:X chany_bottom_out[3]:4 0.152 +1 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.0045 +2 chany_bottom_out[3]:4 chany_bottom_out[3]:2 0.0003236607 +3 chany_bottom_out[3]:3 chany_bottom_out[3] 0.0018125 + +*END + +*D_NET ropt_net_186 0.00116214 //LENGTH 8.885 LUMPCC 0.0002428027 DR + +*CONN +*I FTB_34__33:X O *L 0 *C 65.320 126.820 +*I ropt_mt_inst_825:A I *L 0.001766 *C 65.320 121.040 +*N ropt_net_186:2 *C 65.320 121.040 +*N ropt_net_186:3 *C 65.320 121.085 +*N ropt_net_186:4 *C 65.320 123.715 +*N ropt_net_186:5 *C 65.275 123.760 +*N ropt_net_186:6 *C 64.445 123.760 +*N ropt_net_186:7 *C 64.400 123.805 +*N ropt_net_186:8 *C 64.400 126.775 +*N ropt_net_186:9 *C 64.445 126.820 +*N ropt_net_186:10 *C 65.282 126.820 + +*CAP +0 FTB_34__33:X 1e-06 +1 ropt_mt_inst_825:A 1e-06 +2 ropt_net_186:2 3.70533e-05 +3 ropt_net_186:3 0.0001636352 +4 ropt_net_186:4 0.0001636352 +5 ropt_net_186:5 9.684511e-05 +6 ropt_net_186:6 9.684511e-05 +7 ropt_net_186:7 0.0001173111 +8 ropt_net_186:8 0.0001173111 +9 ropt_net_186:9 6.235068e-05 +10 ropt_net_186:10 6.235068e-05 +11 ropt_net_186:10 chany_top_out[13]:3 9.791961e-06 +12 ropt_net_186:9 chany_top_out[13]:2 9.791961e-06 +13 ropt_net_186:8 chany_top_out[13]:3 8.748242e-05 +14 ropt_net_186:7 chany_top_out[13]:4 8.748242e-05 +15 ropt_net_186:4 chany_top_out[13]:3 2.412699e-05 +16 ropt_net_186:3 chany_top_out[13]:4 2.412699e-05 + +*RES +0 FTB_34__33:X ropt_net_186:10 0.152 +1 ropt_net_186:10 ropt_net_186:9 0.0007477679 +2 ropt_net_186:9 ropt_net_186:8 0.0045 +3 ropt_net_186:8 ropt_net_186:7 0.002651786 +4 ropt_net_186:6 ropt_net_186:5 0.0007410714 +5 ropt_net_186:7 ropt_net_186:6 0.0045 +6 ropt_net_186:5 ropt_net_186:4 0.0045 +7 ropt_net_186:4 ropt_net_186:3 0.002348214 +8 ropt_net_186:2 ropt_mt_inst_825:A 0.152 +9 ropt_net_186:3 ropt_net_186:2 0.0045 + +*END + +*D_NET chanx_left_out[6] 0.0006061662 //LENGTH 3.700 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_852:X O *L 0 *C 4.140 50.660 +*P chanx_left_out[6] O *L 0.7423 *C 1.230 50.320 +*N chanx_left_out[6]:2 *C 3.673 50.320 +*N chanx_left_out[6]:3 *C 3.680 50.320 +*N chanx_left_out[6]:4 *C 3.680 50.660 +*N chanx_left_out[6]:5 *C 3.725 50.660 +*N chanx_left_out[6]:6 *C 4.103 50.660 + +*CAP +0 ropt_mt_inst_852:X 1e-06 +1 chanx_left_out[6] 0.0002060456 +2 chanx_left_out[6]:2 0.0002060456 +3 chanx_left_out[6]:3 5.134505e-05 +4 chanx_left_out[6]:4 4.789695e-05 +5 chanx_left_out[6]:5 4.69165e-05 +6 chanx_left_out[6]:6 4.69165e-05 + +*RES +0 ropt_mt_inst_852:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:6 chanx_left_out[6]:5 0.0003370536 +2 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +3 chanx_left_out[6]:4 chanx_left_out[6]:3 0.0001634615 +4 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +5 chanx_left_out[6]:2 chanx_left_out[6] 0.0003826583 + +*END + +*D_NET ropt_net_220 0.001099882 //LENGTH 8.645 LUMPCC 0.0002381341 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 138.645 45.560 +*I ropt_mt_inst_863:A I *L 0.001767 *C 134.780 47.600 +*N ropt_net_220:2 *C 134.780 47.600 +*N ropt_net_220:3 *C 133.905 47.600 +*N ropt_net_220:4 *C 133.860 47.555 +*N ropt_net_220:5 *C 133.860 45.605 +*N ropt_net_220:6 *C 133.905 45.560 +*N ropt_net_220:7 *C 138.608 45.560 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 ropt_mt_inst_863:A 1e-06 +2 ropt_net_220:2 9.470069e-05 +3 ropt_net_220:3 6.400334e-05 +4 ropt_net_220:4 8.134906e-05 +5 ropt_net_220:5 8.134906e-05 +6 ropt_net_220:6 0.000269173 +7 ropt_net_220:7 0.000269173 +8 ropt_net_220:4 chanx_right_in[10]:35 6.099857e-05 +9 ropt_net_220:5 chanx_right_in[10]:36 6.099857e-05 +10 ropt_net_220:6 ropt_net_174:2 4.600804e-05 +11 ropt_net_220:6 ropt_net_174:5 1.206045e-05 +12 ropt_net_220:7 ropt_net_174:3 4.600804e-05 +13 ropt_net_220:7 ropt_net_174:6 1.206045e-05 + +*RES +0 ropt_mt_inst_812:X ropt_net_220:7 0.152 +1 ropt_net_220:2 ropt_mt_inst_863:A 0.152 +2 ropt_net_220:3 ropt_net_220:2 0.00078125 +3 ropt_net_220:4 ropt_net_220:3 0.0045 +4 ropt_net_220:6 ropt_net_220:5 0.0045 +5 ropt_net_220:5 ropt_net_220:4 0.001741072 +6 ropt_net_220:7 ropt_net_220:6 0.004198661 + +*END + +*D_NET chanx_left_out[11] 0.001163929 //LENGTH 8.510 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_822:X O *L 0 *C 7.095 98.600 +*P chanx_left_out[11] O *L 0.7423 *C 1.230 96.560 +*N chanx_left_out[11]:2 *C 6.893 96.560 +*N chanx_left_out[11]:3 *C 6.900 96.618 +*N chanx_left_out[11]:4 *C 6.900 98.555 +*N chanx_left_out[11]:5 *C 6.900 98.600 +*N chanx_left_out[11]:6 *C 7.095 98.600 + +*CAP +0 ropt_mt_inst_822:X 1e-06 +1 chanx_left_out[11] 0.0003873302 +2 chanx_left_out[11]:2 0.0003873302 +3 chanx_left_out[11]:3 0.0001357193 +4 chanx_left_out[11]:4 0.0001357193 +5 chanx_left_out[11]:5 5.831628e-05 +6 chanx_left_out[11]:6 5.85134e-05 + +*RES +0 ropt_mt_inst_822:X chanx_left_out[11]:6 0.152 +1 chanx_left_out[11]:6 chanx_left_out[11]:5 0.0001059783 +2 chanx_left_out[11]:5 chanx_left_out[11]:4 0.0045 +3 chanx_left_out[11]:4 chanx_left_out[11]:3 0.001729911 +4 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 +5 chanx_left_out[11]:2 chanx_left_out[11] 0.0008871249 + +*END + +*D_NET ropt_net_222 0.002083278 //LENGTH 14.090 LUMPCC 0.0004178273 DR + +*CONN +*I ropt_mt_inst_832:X O *L 0 *C 11.695 66.300 +*I ropt_mt_inst_866:A I *L 0.001766 *C 3.220 69.360 +*N ropt_net_222:2 *C 3.258 69.360 +*N ropt_net_222:3 *C 3.635 69.360 +*N ropt_net_222:4 *C 3.680 69.315 +*N ropt_net_222:5 *C 3.680 66.017 +*N ropt_net_222:6 *C 3.680 65.960 +*N ropt_net_222:7 *C 11.492 65.960 +*N ropt_net_222:8 *C 11.500 65.960 +*N ropt_net_222:9 *C 11.500 66.300 +*N ropt_net_222:10 *C 11.500 66.300 +*N ropt_net_222:11 *C 11.695 66.300 + +*CAP +0 ropt_mt_inst_832:X 1e-06 +1 ropt_mt_inst_866:A 1e-06 +2 ropt_net_222:2 4.53506e-05 +3 ropt_net_222:3 4.53506e-05 +4 ropt_net_222:4 0.0001574608 +5 ropt_net_222:5 0.0001574608 +6 ropt_net_222:6 0.0005142954 +7 ropt_net_222:7 0.0005142954 +8 ropt_net_222:8 5.758556e-05 +9 ropt_net_222:9 5.374764e-05 +10 ropt_net_222:10 6.019032e-05 +11 ropt_net_222:11 5.771379e-05 +12 ropt_net_222:6 chanx_left_in[18] 0.0001174017 +13 ropt_net_222:7 chanx_left_in[18]:40 0.0001174017 +14 ropt_net_222:4 chanx_left_out[0]:4 8.941213e-05 +15 ropt_net_222:5 chanx_left_out[0]:3 8.941213e-05 +16 ropt_net_222:6 chanx_left_out[0] 2.09982e-06 +17 ropt_net_222:7 chanx_left_out[0]:2 2.09982e-06 + +*RES +0 ropt_mt_inst_832:X ropt_net_222:11 0.152 +1 ropt_net_222:2 ropt_mt_inst_866:A 0.152 +2 ropt_net_222:3 ropt_net_222:2 0.0003370536 +3 ropt_net_222:4 ropt_net_222:3 0.0045 +4 ropt_net_222:5 ropt_net_222:4 0.002944197 +5 ropt_net_222:6 ropt_net_222:5 0.00341 +6 ropt_net_222:8 ropt_net_222:7 0.00341 +7 ropt_net_222:7 ropt_net_222:6 0.001223958 +8 ropt_net_222:10 ropt_net_222:9 0.0045 +9 ropt_net_222:9 ropt_net_222:8 0.0001634615 +10 ropt_net_222:11 ropt_net_222:10 0.0001059783 + +*END + +*D_NET ropt_net_174 0.002275032 //LENGTH 20.610 LUMPCC 0.0004210373 DR + +*CONN +*I BUFT_P_126:X O *L 0 *C 133.860 55.080 +*I ropt_mt_inst_812:A I *L 0.001766 *C 134.780 44.880 +*N ropt_net_174:2 *C 134.817 44.880 +*N ropt_net_174:3 *C 137.035 44.880 +*N ropt_net_174:4 *C 137.080 44.925 +*N ropt_net_174:5 *C 137.080 45.560 +*N ropt_net_174:6 *C 138.920 45.560 +*N ropt_net_174:7 *C 138.920 55.035 +*N ropt_net_174:8 *C 138.875 55.080 +*N ropt_net_174:9 *C 133.898 55.080 + +*CAP +0 BUFT_P_126:X 1e-06 +1 ropt_mt_inst_812:A 1e-06 +2 ropt_net_174:2 6.349481e-05 +3 ropt_net_174:3 6.349481e-05 +4 ropt_net_174:4 4.284613e-05 +5 ropt_net_174:5 0.0001311251 +6 ropt_net_174:6 0.0004990778 +7 ropt_net_174:7 0.0004107988 +8 ropt_net_174:8 0.0003205787 +9 ropt_net_174:9 0.0003205787 +10 ropt_net_174:8 chanx_right_in[0]:13 6.64364e-06 +11 ropt_net_174:7 chanx_right_in[0] 1.581914e-05 +12 ropt_net_174:7 chanx_right_in[0]:14 4.774889e-05 +13 ropt_net_174:9 chanx_right_in[0]:12 6.64364e-06 +14 ropt_net_174:6 chanx_right_in[0]:15 4.774889e-05 +15 ropt_net_174:6 chanx_right_in[0]:16 1.581914e-05 +16 ropt_net_174:2 chanx_right_out[8]:6 6.422746e-05 +17 ropt_net_174:3 chanx_right_out[8]:5 6.422746e-05 +18 ropt_net_174:4 chanx_right_out[8]:4 7.981685e-06 +19 ropt_net_174:7 chanx_right_out[8]:3 5.592146e-07 +20 ropt_net_174:5 chanx_right_out[8]:2 9.470134e-06 +21 ropt_net_174:5 chanx_right_out[8]:3 7.981685e-06 +22 ropt_net_174:6 chanx_right_out[8] 9.470134e-06 +23 ropt_net_174:6 chanx_right_out[8]:4 5.592146e-07 +24 ropt_net_174:2 ropt_net_220:6 4.600804e-05 +25 ropt_net_174:3 ropt_net_220:7 4.600804e-05 +26 ropt_net_174:5 ropt_net_220:6 1.206045e-05 +27 ropt_net_174:6 ropt_net_220:7 1.206045e-05 + +*RES +0 BUFT_P_126:X ropt_net_174:9 0.152 +1 ropt_net_174:2 ropt_mt_inst_812:A 0.152 +2 ropt_net_174:3 ropt_net_174:2 0.001979911 +3 ropt_net_174:4 ropt_net_174:3 0.0045 +4 ropt_net_174:8 ropt_net_174:7 0.0045 +5 ropt_net_174:7 ropt_net_174:6 0.008459821 +6 ropt_net_174:9 ropt_net_174:8 0.004444197 +7 ropt_net_174:5 ropt_net_174:4 0.0005669644 +8 ropt_net_174:6 ropt_net_174:5 0.001642857 + +*END + +*D_NET chany_bottom_out[15] 0.0003317535 //LENGTH 2.610 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_877:X O *L 0 *C 55.200 3.740 +*P chany_bottom_out[15] O *L 0.7423 *C 55.200 1.290 +*N chany_bottom_out[15]:2 *C 55.200 3.695 +*N chany_bottom_out[15]:3 *C 55.200 3.740 + +*CAP +0 ropt_mt_inst_877:X 1e-06 +1 chany_bottom_out[15] 0.0001491698 +2 chany_bottom_out[15]:2 0.0001491698 +3 chany_bottom_out[15]:3 3.241398e-05 + +*RES +0 ropt_mt_inst_877:X chany_bottom_out[15]:3 0.152 +1 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.0045 +2 chany_bottom_out[15]:2 chany_bottom_out[15] 0.002147322 + +*END + +*D_NET chany_bottom_out[10] 0.001311527 //LENGTH 11.290 LUMPCC 9.708235e-05 DR + +*CONN +*I ropt_mt_inst_897:X O *L 0 *C 98.175 6.120 +*P chany_bottom_out[10] O *L 0.7423 *C 93.380 1.290 +*N chany_bottom_out[10]:2 *C 93.380 1.700 +*N chany_bottom_out[10]:3 *C 92.920 1.700 +*N chany_bottom_out[10]:4 *C 92.920 6.075 +*N chany_bottom_out[10]:5 *C 92.965 6.120 +*N chany_bottom_out[10]:6 *C 98.138 6.120 + +*CAP +0 ropt_mt_inst_897:X 1e-06 +1 chany_bottom_out[10] 3.752693e-05 +2 chany_bottom_out[10]:2 6.641429e-05 +3 chany_bottom_out[10]:3 0.0002703118 +4 chany_bottom_out[10]:4 0.0002414244 +5 chany_bottom_out[10]:5 0.0002988838 +6 chany_bottom_out[10]:6 0.0002988838 +7 chany_bottom_out[10]:6 ropt_net_189:3 4.854117e-05 +8 chany_bottom_out[10]:5 ropt_net_189:4 4.854117e-05 + +*RES +0 ropt_mt_inst_897:X chany_bottom_out[10]:6 0.152 +1 chany_bottom_out[10]:6 chany_bottom_out[10]:5 0.004618304 +2 chany_bottom_out[10]:5 chany_bottom_out[10]:4 0.0045 +3 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.00390625 +4 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0004107143 +5 chany_bottom_out[10]:2 chany_bottom_out[10] 0.0003660715 + +*END + +*D_NET chany_top_in[17] 0.02088801 //LENGTH 154.390 LUMPCC 0.004311534 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 81.420 129.270 +*I mux_left_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 66.605 52.700 +*I mux_bottom_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 69.290 33.660 +*I FTB_12__11:A I *L 0.001776 *C 72.680 4.080 +*I mux_right_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 82.245 69.020 +*N chany_top_in[17]:5 *C 82.245 69.020 +*N chany_top_in[17]:6 *C 82.340 68.975 +*N chany_top_in[17]:7 *C 82.340 67.377 +*N chany_top_in[17]:8 *C 82.338 67.320 +*N chany_top_in[17]:9 *C 72.642 4.080 +*N chany_top_in[17]:10 *C 72.265 4.080 +*N chany_top_in[17]:11 *C 72.220 4.125 +*N chany_top_in[17]:12 *C 72.220 33.955 +*N chany_top_in[17]:13 *C 72.175 34.000 +*N chany_top_in[17]:14 *C 69.328 33.660 +*N chany_top_in[17]:15 *C 69.920 33.660 +*N chany_top_in[17]:16 *C 69.920 34.000 +*N chany_top_in[17]:17 *C 69.920 34.045 +*N chany_top_in[17]:18 *C 69.920 36.335 +*N chany_top_in[17]:19 *C 69.875 36.380 +*N chany_top_in[17]:20 *C 67.665 36.380 +*N chany_top_in[17]:21 *C 67.620 36.425 +*N chany_top_in[17]:22 *C 66.642 52.700 +*N chany_top_in[17]:23 *C 67.575 52.700 +*N chany_top_in[17]:24 *C 67.620 52.700 +*N chany_top_in[17]:25 *C 67.620 64.543 +*N chany_top_in[17]:26 *C 67.627 64.600 +*N chany_top_in[17]:27 *C 80.032 64.600 +*N chany_top_in[17]:28 *C 80.040 64.657 +*N chany_top_in[17]:29 *C 80.040 67.263 +*N chany_top_in[17]:30 *C 80.047 67.320 +*N chany_top_in[17]:31 *C 81.895 67.320 +*N chany_top_in[17]:32 *C 81.880 67.328 +*N chany_top_in[17]:33 *C 81.880 117.155 +*N chany_top_in[17]:34 *C 81.880 127.153 +*N chany_top_in[17]:35 *C 81.865 127.160 +*N chany_top_in[17]:36 *C 81.422 127.160 +*N chany_top_in[17]:37 *C 81.420 127.218 + +*CAP +0 chany_top_in[17] 0.0001487496 +1 mux_left_track_17\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:A0 1e-06 +3 FTB_12__11:A 1e-06 +4 mux_right_track_16\/mux_l1_in_1_:A1 1e-06 +5 chany_top_in[17]:5 3.201902e-05 +6 chany_top_in[17]:6 0.0001410608 +7 chany_top_in[17]:7 0.0001410608 +8 chany_top_in[17]:8 8.805624e-05 +9 chany_top_in[17]:9 5.381875e-05 +10 chany_top_in[17]:10 5.381875e-05 +11 chany_top_in[17]:11 0.001768856 +12 chany_top_in[17]:12 0.001768856 +13 chany_top_in[17]:13 0.0001828254 +14 chany_top_in[17]:14 4.814705e-05 +15 chany_top_in[17]:15 7.84616e-05 +16 chany_top_in[17]:16 0.00021314 +17 chany_top_in[17]:17 0.0001067181 +18 chany_top_in[17]:18 0.0001067181 +19 chany_top_in[17]:19 0.0001491361 +20 chany_top_in[17]:20 0.0001491361 +21 chany_top_in[17]:21 0.000820831 +22 chany_top_in[17]:22 8.965773e-05 +23 chany_top_in[17]:23 8.965773e-05 +24 chany_top_in[17]:24 0.001582395 +25 chany_top_in[17]:25 0.0007295553 +26 chany_top_in[17]:26 0.0009183051 +27 chany_top_in[17]:27 0.0009183051 +28 chany_top_in[17]:28 0.0002038973 +29 chany_top_in[17]:29 0.0002038973 +30 chany_top_in[17]:30 0.0002328645 +31 chany_top_in[17]:31 0.0003209208 +32 chany_top_in[17]:32 0.001999537 +33 chany_top_in[17]:33 0.002485109 +34 chany_top_in[17]:34 0.0004855719 +35 chany_top_in[17]:35 5.631886e-05 +36 chany_top_in[17]:36 5.631886e-05 +37 chany_top_in[17]:37 0.0001487496 +38 chany_top_in[17]:9 chany_top_in[12]:14 8.861263e-06 +39 chany_top_in[17]:10 chany_top_in[12]:13 8.861263e-06 +40 chany_top_in[17]:32 chany_top_in[12]:35 0.0005249866 +41 chany_top_in[17]:33 chany_top_in[12]:36 0.0005249866 +42 chany_top_in[17]:32 chany_bottom_in[10]:24 0.0003533756 +43 chany_top_in[17]:32 chany_bottom_in[10]:23 4.752038e-05 +44 chany_top_in[17]:34 chany_bottom_in[10]:11 3.942445e-05 +45 chany_top_in[17]:33 chany_bottom_in[10]:24 8.694483e-05 +46 chany_top_in[17]:33 chany_bottom_in[10]:11 0.0003533756 +47 chany_top_in[17]:32 chany_bottom_in[0]:16 8.345894e-05 +48 chany_top_in[17]:32 chany_bottom_in[0]:17 0.0002345975 +49 chany_top_in[17]:33 chany_bottom_in[0]:16 0.0002345975 +50 chany_top_in[17]:33 chany_bottom_in[0]:9 8.345894e-05 +51 chany_top_in[17]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.844341e-05 +52 chany_top_in[17]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.844341e-05 +53 chany_top_in[17]:21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.153767e-06 +54 chany_top_in[17]:24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.153767e-06 +55 chany_top_in[17]:24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 1.354817e-08 +56 chany_top_in[17]:25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.354817e-08 +57 chany_top_in[17]:26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002022685 +58 chany_top_in[17]:27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002022685 +59 chany_top_in[17]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.842775e-05 +60 chany_top_in[17]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.286319e-05 +61 chany_top_in[17]:24 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.842775e-05 +62 chany_top_in[17]:24 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 1.286319e-05 +63 chany_top_in[17]:21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.561596e-05 +64 chany_top_in[17]:24 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.561596e-05 +65 chany_top_in[17]:32 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:17 0.0003795891 +66 chany_top_in[17]:33 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.0003795891 +67 chany_top_in[17]:11 ropt_net_239:5 4.316695e-05 +68 chany_top_in[17]:12 ropt_net_239:6 4.316695e-05 + +*RES +0 chany_top_in[17] chany_top_in[17]:37 0.00183259 +1 chany_top_in[17]:9 FTB_12__11:A 0.152 +2 chany_top_in[17]:10 chany_top_in[17]:9 0.0003370536 +3 chany_top_in[17]:11 chany_top_in[17]:10 0.0045 +4 chany_top_in[17]:13 chany_top_in[17]:12 0.0045 +5 chany_top_in[17]:12 chany_top_in[17]:11 0.02663393 +6 chany_top_in[17]:16 chany_top_in[17]:15 0.0003035715 +7 chany_top_in[17]:16 chany_top_in[17]:13 0.002013393 +8 chany_top_in[17]:17 chany_top_in[17]:16 0.0045 +9 chany_top_in[17]:19 chany_top_in[17]:18 0.0045 +10 chany_top_in[17]:18 chany_top_in[17]:17 0.002044643 +11 chany_top_in[17]:20 chany_top_in[17]:19 0.001973214 +12 chany_top_in[17]:21 chany_top_in[17]:20 0.0045 +13 chany_top_in[17]:31 chany_top_in[17]:30 0.0002894417 +14 chany_top_in[17]:31 chany_top_in[17]:8 6.499219e-05 +15 chany_top_in[17]:32 chany_top_in[17]:31 0.00341 +16 chany_top_in[17]:35 chany_top_in[17]:34 0.00341 +17 chany_top_in[17]:34 chany_top_in[17]:33 0.001566275 +18 chany_top_in[17]:37 chany_top_in[17]:36 0.00341 +19 chany_top_in[17]:36 chany_top_in[17]:35 6.499219e-05 +20 chany_top_in[17]:14 mux_bottom_track_17\/mux_l1_in_0_:A0 0.152 +21 chany_top_in[17]:7 chany_top_in[17]:6 0.001426339 +22 chany_top_in[17]:8 chany_top_in[17]:7 0.00341 +23 chany_top_in[17]:5 mux_right_track_16\/mux_l1_in_1_:A1 0.152 +24 chany_top_in[17]:6 chany_top_in[17]:5 0.0045 +25 chany_top_in[17]:23 chany_top_in[17]:22 0.0008325893 +26 chany_top_in[17]:24 chany_top_in[17]:23 0.0045 +27 chany_top_in[17]:24 chany_top_in[17]:21 0.01453125 +28 chany_top_in[17]:22 mux_left_track_17\/mux_l1_in_1_:A1 0.152 +29 chany_top_in[17]:25 chany_top_in[17]:24 0.01057366 +30 chany_top_in[17]:26 chany_top_in[17]:25 0.00341 +31 chany_top_in[17]:28 chany_top_in[17]:27 0.00341 +32 chany_top_in[17]:27 chany_top_in[17]:26 0.00194345 +33 chany_top_in[17]:29 chany_top_in[17]:28 0.002325893 +34 chany_top_in[17]:30 chany_top_in[17]:29 0.00341 +35 chany_top_in[17]:15 chany_top_in[17]:14 0.0005290179 +36 chany_top_in[17]:33 chany_top_in[17]:32 0.007806308 + +*END + +*D_NET chany_bottom_in[10] 0.03692956 //LENGTH 237.605 LUMPCC 0.009043986 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 62.560 1.290 +*I mux_left_track_33\/mux_l1_in_1_:A0 I *L 0.001631 *C 24.670 70.040 +*I mux_top_track_32\/mux_l1_in_2_:A1 I *L 0.00198 *C 82.440 77.860 +*I mux_right_track_32\/mux_l1_in_2_:A1 I *L 0.00198 *C 76.920 69.020 +*I FTB_33__32:A I *L 0.001776 *C 91.080 121.040 +*N chany_bottom_in[10]:5 *C 61.850 2.720 +*N chany_bottom_in[10]:6 *C 91.043 121.040 +*N chany_bottom_in[10]:7 *C 86.525 121.040 +*N chany_bottom_in[10]:8 *C 86.480 121.040 +*N chany_bottom_in[10]:9 *C 86.473 121.040 +*N chany_bottom_in[10]:10 *C 84.660 121.040 +*N chany_bottom_in[10]:11 *C 84.640 121.032 +*N chany_bottom_in[10]:12 *C 76.958 69.020 +*N chany_bottom_in[10]:13 *C 79.995 69.020 +*N chany_bottom_in[10]:14 *C 80.040 69.065 +*N chany_bottom_in[10]:15 *C 80.040 76.160 +*N chany_bottom_in[10]:16 *C 80.500 76.160 +*N chany_bottom_in[10]:17 *C 82.403 77.860 +*N chany_bottom_in[10]:18 *C 80.545 77.860 +*N chany_bottom_in[10]:19 *C 80.500 77.815 +*N chany_bottom_in[10]:20 *C 80.500 78.200 +*N chany_bottom_in[10]:21 *C 80.508 78.200 +*N chany_bottom_in[10]:22 *C 84.620 78.200 +*N chany_bottom_in[10]:23 *C 84.640 78.208 +*N chany_bottom_in[10]:24 *C 84.640 85.000 +*N chany_bottom_in[10]:25 *C 84.620 85.000 +*N chany_bottom_in[10]:26 *C 77.280 85.000 +*N chany_bottom_in[10]:27 *C 77.280 84.320 +*N chany_bottom_in[10]:28 *C 72.680 84.320 +*N chany_bottom_in[10]:29 *C 72.680 85.000 +*N chany_bottom_in[10]:30 *C 65.320 85.000 +*N chany_bottom_in[10]:31 *C 65.320 85.680 +*N chany_bottom_in[10]:32 *C 62.560 85.680 +*N chany_bottom_in[10]:33 *C 24.707 70.040 +*N chany_bottom_in[10]:34 *C 32.615 70.040 +*N chany_bottom_in[10]:35 *C 32.660 70.085 +*N chany_bottom_in[10]:36 *C 32.660 80.875 +*N chany_bottom_in[10]:37 *C 32.705 80.920 +*N chany_bottom_in[10]:38 *C 49.635 80.920 +*N chany_bottom_in[10]:39 *C 49.680 80.965 +*N chany_bottom_in[10]:40 *C 49.680 84.263 +*N chany_bottom_in[10]:41 *C 49.688 84.320 +*N chany_bottom_in[10]:42 *C 62.560 84.320 +*N chany_bottom_in[10]:43 *C 62.560 85.000 +*N chany_bottom_in[10]:44 *C 62.560 84.993 +*N chany_bottom_in[10]:45 *C 62.560 52.555 +*N chany_bottom_in[10]:46 *C 62.560 2.728 +*N chany_bottom_in[10]:47 *C 62.558 2.720 +*N chany_bottom_in[10]:48 *C 62.560 2.663 + +*CAP +0 chany_bottom_in[10] 9.791019e-05 +1 mux_left_track_33\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:A1 1e-06 +3 mux_right_track_32\/mux_l1_in_2_:A1 1e-06 +4 FTB_33__32:A 1e-06 +5 chany_bottom_in[10]:5 8.22732e-05 +6 chany_bottom_in[10]:6 0.0002676536 +7 chany_bottom_in[10]:7 0.0002676536 +8 chany_bottom_in[10]:8 3.629731e-05 +9 chany_bottom_in[10]:9 0.0001353135 +10 chany_bottom_in[10]:10 0.0001353135 +11 chany_bottom_in[10]:11 0.002991188 +12 chany_bottom_in[10]:12 0.0002277046 +13 chany_bottom_in[10]:13 0.0002277046 +14 chany_bottom_in[10]:14 0.0003517343 +15 chany_bottom_in[10]:15 0.0003823629 +16 chany_bottom_in[10]:16 0.000106193 +17 chany_bottom_in[10]:17 0.0001996523 +18 chany_bottom_in[10]:18 0.0001996523 +19 chany_bottom_in[10]:19 9.000396e-05 +20 chany_bottom_in[10]:20 5.194439e-05 +21 chany_bottom_in[10]:21 0.0004183817 +22 chany_bottom_in[10]:22 0.0004183817 +23 chany_bottom_in[10]:23 0.0006075465 +24 chany_bottom_in[10]:24 0.003598734 +25 chany_bottom_in[10]:25 0.0005487817 +26 chany_bottom_in[10]:26 0.0006152214 +27 chany_bottom_in[10]:27 0.0003972403 +28 chany_bottom_in[10]:28 0.0004037672 +29 chany_bottom_in[10]:29 0.0005428192 +30 chany_bottom_in[10]:30 0.000498914 +31 chany_bottom_in[10]:31 0.0003633526 +32 chany_bottom_in[10]:32 0.0003690124 +33 chany_bottom_in[10]:33 0.000598941 +34 chany_bottom_in[10]:34 0.000598941 +35 chany_bottom_in[10]:35 0.0006946056 +36 chany_bottom_in[10]:36 0.0006946056 +37 chany_bottom_in[10]:37 0.001065517 +38 chany_bottom_in[10]:38 0.001065517 +39 chany_bottom_in[10]:39 0.0002216122 +40 chany_bottom_in[10]:40 0.0002216122 +41 chany_bottom_in[10]:41 0.0008164237 +42 chany_bottom_in[10]:42 0.0008742266 +43 chany_bottom_in[10]:43 9.252412e-05 +44 chany_bottom_in[10]:44 0.001228731 +45 chany_bottom_in[10]:45 0.003062078 +46 chany_bottom_in[10]:46 0.001833346 +47 chany_bottom_in[10]:47 8.22732e-05 +48 chany_bottom_in[10]:48 9.791019e-05 +49 chany_bottom_in[10]:41 chany_top_in[14]:22 0.0004617758 +50 chany_bottom_in[10]:42 chany_top_in[14]:21 0.0004617758 +51 chany_bottom_in[10]:32 chany_top_in[14]:22 1.246596e-05 +52 chany_bottom_in[10]:31 chany_top_in[14]:21 1.246596e-05 +53 chany_bottom_in[10]:30 chany_top_in[14]:22 9.547186e-05 +54 chany_bottom_in[10]:29 chany_top_in[14]:21 9.547186e-05 +55 chany_bottom_in[10]:28 chany_top_in[14]:22 6.294285e-05 +56 chany_bottom_in[10]:27 chany_top_in[14]:21 6.294285e-05 +57 chany_bottom_in[10]:24 chany_top_in[17]:32 0.0003533756 +58 chany_bottom_in[10]:24 chany_top_in[17]:33 8.694483e-05 +59 chany_bottom_in[10]:11 chany_top_in[17]:33 0.0003533756 +60 chany_bottom_in[10]:11 chany_top_in[17]:34 3.942445e-05 +61 chany_bottom_in[10]:23 chany_top_in[17]:32 4.752038e-05 +62 chany_bottom_in[10]:25 chanx_right_in[2]:26 4.121133e-06 +63 chany_bottom_in[10]:25 chanx_right_in[2]:28 4.672736e-05 +64 chany_bottom_in[10]:20 chanx_right_in[2]:33 1.019673e-05 +65 chany_bottom_in[10]:41 chanx_right_in[2]:21 5.685098e-05 +66 chany_bottom_in[10]:41 chanx_right_in[2]:23 4.431575e-06 +67 chany_bottom_in[10]:19 chanx_right_in[2]:32 5.941659e-05 +68 chany_bottom_in[10]:14 chanx_right_in[2]:33 2.524146e-06 +69 chany_bottom_in[10]:14 chanx_right_in[2]:35 7.888293e-05 +70 chany_bottom_in[10]:14 chanx_right_in[2]:37 2.352062e-05 +71 chany_bottom_in[10]:15 chanx_right_in[2]:32 2.524146e-06 +72 chany_bottom_in[10]:15 chanx_right_in[2]:34 8.007701e-05 +73 chany_bottom_in[10]:15 chanx_right_in[2]:36 2.352062e-05 +74 chany_bottom_in[10]:16 chanx_right_in[2]:33 5.041392e-05 +75 chany_bottom_in[10]:42 chanx_right_in[2]:22 5.685098e-05 +76 chany_bottom_in[10]:42 chanx_right_in[2]:24 4.431575e-06 +77 chany_bottom_in[10]:30 chanx_right_in[2]:25 2.543397e-07 +78 chany_bottom_in[10]:29 chanx_right_in[2]:26 2.543397e-07 +79 chany_bottom_in[10]:28 chanx_right_in[2]:23 3.179247e-07 +80 chany_bottom_in[10]:28 chanx_right_in[2]:25 4.220443e-05 +81 chany_bottom_in[10]:27 chanx_right_in[2]:24 3.179247e-07 +82 chany_bottom_in[10]:27 chanx_right_in[2]:26 4.220443e-05 +83 chany_bottom_in[10]:26 chanx_right_in[2]:25 4.121133e-06 +84 chany_bottom_in[10]:26 chanx_right_in[2]:27 4.672736e-05 +85 chany_bottom_in[10]:43 chany_bottom_in[13]:29 1.480428e-05 +86 chany_bottom_in[10]:44 chany_bottom_in[13]:32 0.0005873766 +87 chany_bottom_in[10]:46 chany_bottom_in[13]:34 0.0009610465 +88 chany_bottom_in[10]:46 chany_bottom_in[13]:33 1.209272e-05 +89 chany_bottom_in[10]:32 chany_bottom_in[13]:30 1.480428e-05 +90 chany_bottom_in[10]:31 chany_bottom_in[13]:30 2.251985e-05 +91 chany_bottom_in[10]:31 chany_bottom_in[13]:32 7.400994e-06 +92 chany_bottom_in[10]:30 chany_bottom_in[13]:29 2.251985e-05 +93 chany_bottom_in[10]:30 chany_bottom_in[13]:33 7.400994e-06 +94 chany_bottom_in[10]:45 chany_bottom_in[13]:32 1.209272e-05 +95 chany_bottom_in[10]:45 chany_bottom_in[13]:33 0.001548423 +96 chany_bottom_in[10]:44 chanx_right_in[19]:9 0.0001199977 +97 chany_bottom_in[10]:46 chanx_right_in[19]:17 0.0001146214 +98 chany_bottom_in[10]:46 chanx_right_in[19]:16 0.0002614167 +99 chany_bottom_in[10]:45 chanx_right_in[19]:9 0.0002614167 +100 chany_bottom_in[10]:45 chanx_right_in[19]:16 0.0002346191 +101 chany_bottom_in[10]:38 optlc_net_148:13 0.0003102812 +102 chany_bottom_in[10]:37 optlc_net_148:12 0.0003102812 +103 chany_bottom_in[10]:44 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0003191408 +104 chany_bottom_in[10]:45 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003191408 +105 chany_bottom_in[10]:31 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 1.159724e-05 +106 chany_bottom_in[10]:30 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.000273996 +107 chany_bottom_in[10]:30 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 1.159724e-05 +108 chany_bottom_in[10]:29 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.000273996 +109 chany_bottom_in[10]:28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 4.559518e-05 +110 chany_bottom_in[10]:27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 4.559518e-05 +111 chany_bottom_in[10]:13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.668392e-05 +112 chany_bottom_in[10]:12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.668392e-05 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:48 0.001225446 +1 chany_bottom_in[10]:25 chany_bottom_in[10]:24 0.00341 +2 chany_bottom_in[10]:24 chany_bottom_in[10]:23 0.001064158 +3 chany_bottom_in[10]:24 chany_bottom_in[10]:11 0.005645091 +4 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.0002839583 +5 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.00341 +6 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.0045 +7 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.00341 +8 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.004033482 +9 chany_bottom_in[10]:6 FTB_33__32:A 0.152 +10 chany_bottom_in[10]:20 chany_bottom_in[10]:19 0.0001850962 +11 chany_bottom_in[10]:21 chany_bottom_in[10]:20 0.00341 +12 chany_bottom_in[10]:22 chany_bottom_in[10]:21 0.0006442916 +13 chany_bottom_in[10]:23 chany_bottom_in[10]:22 0.00341 +14 chany_bottom_in[10]:43 chany_bottom_in[10]:42 0.0001065333 +15 chany_bottom_in[10]:43 chany_bottom_in[10]:32 0.0001065333 +16 chany_bottom_in[10]:44 chany_bottom_in[10]:43 0.00341 +17 chany_bottom_in[10]:47 chany_bottom_in[10]:46 0.00341 +18 chany_bottom_in[10]:47 chany_bottom_in[10]:5 0.0001039141 +19 chany_bottom_in[10]:46 chany_bottom_in[10]:45 0.007806308 +20 chany_bottom_in[10]:48 chany_bottom_in[10]:47 0.00341 +21 chany_bottom_in[10]:40 chany_bottom_in[10]:39 0.002944197 +22 chany_bottom_in[10]:41 chany_bottom_in[10]:40 0.00341 +23 chany_bottom_in[10]:38 chany_bottom_in[10]:37 0.01511607 +24 chany_bottom_in[10]:39 chany_bottom_in[10]:38 0.0045 +25 chany_bottom_in[10]:37 chany_bottom_in[10]:36 0.0045 +26 chany_bottom_in[10]:36 chany_bottom_in[10]:35 0.009633929 +27 chany_bottom_in[10]:34 chany_bottom_in[10]:33 0.007060268 +28 chany_bottom_in[10]:35 chany_bottom_in[10]:34 0.0045 +29 chany_bottom_in[10]:33 mux_left_track_33\/mux_l1_in_1_:A0 0.152 +30 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.001658482 +31 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.0045 +32 chany_bottom_in[10]:19 chany_bottom_in[10]:16 0.001477679 +33 chany_bottom_in[10]:17 mux_top_track_32\/mux_l1_in_2_:A1 0.152 +34 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.002712054 +35 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.0045 +36 chany_bottom_in[10]:12 mux_right_track_32\/mux_l1_in_2_:A1 0.152 +37 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.006334822 +38 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.0004107143 +39 chany_bottom_in[10]:42 chany_bottom_in[10]:41 0.002016691 +40 chany_bottom_in[10]:32 chany_bottom_in[10]:31 0.0004324 +41 chany_bottom_in[10]:31 chany_bottom_in[10]:30 0.0001065333 +42 chany_bottom_in[10]:30 chany_bottom_in[10]:29 0.001153067 +43 chany_bottom_in[10]:29 chany_bottom_in[10]:28 0.0001065333 +44 chany_bottom_in[10]:28 chany_bottom_in[10]:27 0.0007206665 +45 chany_bottom_in[10]:27 chany_bottom_in[10]:26 0.0001065333 +46 chany_bottom_in[10]:26 chany_bottom_in[10]:25 0.001149933 +47 chany_bottom_in[10]:45 chany_bottom_in[10]:44 0.005081875 + +*END + +*D_NET chanx_left_in[6] 0.02372258 //LENGTH 164.965 LUMPCC 0.007850058 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 34.000 +*I mux_bottom_track_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 98.805 34.340 +*I mux_top_track_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 103.500 39.780 +*I mux_right_track_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 106.895 53.720 +*I ropt_mt_inst_806:A I *L 0.001767 *C 134.780 36.720 +*N chanx_left_in[6]:5 *C 134.780 36.720 +*N chanx_left_in[6]:6 *C 134.780 36.675 +*N chanx_left_in[6]:7 *C 134.780 36.085 +*N chanx_left_in[6]:8 *C 134.735 36.040 +*N chanx_left_in[6]:9 *C 124.325 36.040 +*N chanx_left_in[6]:10 *C 124.210 36.085 +*N chanx_left_in[6]:11 *C 124.200 36.675 +*N chanx_left_in[6]:12 *C 124.155 36.720 +*N chanx_left_in[6]:13 *C 123.280 36.720 +*N chanx_left_in[6]:14 *C 123.280 36.675 +*N chanx_left_in[6]:15 *C 123.280 34.725 +*N chanx_left_in[6]:16 *C 123.235 34.680 +*N chanx_left_in[6]:17 *C 106.858 53.720 +*N chanx_left_in[6]:18 *C 104.005 53.720 +*N chanx_left_in[6]:19 *C 103.960 53.675 +*N chanx_left_in[6]:20 *C 103.538 39.780 +*N chanx_left_in[6]:21 *C 103.915 39.780 +*N chanx_left_in[6]:22 *C 103.960 39.780 +*N chanx_left_in[6]:23 *C 103.960 37.740 +*N chanx_left_in[6]:24 *C 104.420 37.740 +*N chanx_left_in[6]:25 *C 104.420 34.725 +*N chanx_left_in[6]:26 *C 104.420 34.680 +*N chanx_left_in[6]:27 *C 98.805 34.340 +*N chanx_left_in[6]:28 *C 98.945 34.680 +*N chanx_left_in[6]:29 *C 98.900 34.680 +*N chanx_left_in[6]:30 *C 98.892 34.680 +*N chanx_left_in[6]:31 *C 88.030 34.680 +*N chanx_left_in[6]:32 *C 38.180 34.680 +*N chanx_left_in[6]:33 *C 38.180 34.000 + +*CAP +0 chanx_left_in[6] 0.001018304 +1 mux_bottom_track_9\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_8\/mux_l2_in_2_:A1 1e-06 +3 mux_right_track_8\/mux_l2_in_2_:A0 1e-06 +4 ropt_mt_inst_806:A 1e-06 +5 chanx_left_in[6]:5 3.212145e-05 +6 chanx_left_in[6]:6 5.900223e-05 +7 chanx_left_in[6]:7 5.900223e-05 +8 chanx_left_in[6]:8 0.0006102126 +9 chanx_left_in[6]:9 0.0006102126 +10 chanx_left_in[6]:10 4.482297e-05 +11 chanx_left_in[6]:11 4.482297e-05 +12 chanx_left_in[6]:12 6.338829e-05 +13 chanx_left_in[6]:13 9.160444e-05 +14 chanx_left_in[6]:14 9.697657e-05 +15 chanx_left_in[6]:15 9.697657e-05 +16 chanx_left_in[6]:16 0.001110877 +17 chanx_left_in[6]:17 0.0002340183 +18 chanx_left_in[6]:18 0.0002340183 +19 chanx_left_in[6]:19 0.0007653561 +20 chanx_left_in[6]:20 5.602948e-05 +21 chanx_left_in[6]:21 5.602948e-05 +22 chanx_left_in[6]:22 0.0009223291 +23 chanx_left_in[6]:23 0.0001555658 +24 chanx_left_in[6]:24 0.0002196438 +25 chanx_left_in[6]:25 0.0001894965 +26 chanx_left_in[6]:26 0.001546413 +27 chanx_left_in[6]:27 6.566188e-05 +28 chanx_left_in[6]:28 0.0004408275 +29 chanx_left_in[6]:29 3.847986e-05 +30 chanx_left_in[6]:30 0.0004264582 +31 chanx_left_in[6]:31 0.002953877 +32 chanx_left_in[6]:32 0.002567555 +33 chanx_left_in[6]:33 0.00105844 +34 chanx_left_in[6]:30 chanx_right_in[17] 4.193445e-05 +35 chanx_left_in[6]:30 chanx_right_in[17]:25 0.0001929841 +36 chanx_left_in[6]:16 chanx_right_in[17] 4.644439e-05 +37 chanx_left_in[6]:26 chanx_right_in[17]:26 4.644439e-05 +38 chanx_left_in[6]:32 chanx_right_in[17]:24 0.0004852014 +39 chanx_left_in[6]:31 chanx_right_in[17]:24 0.0001929841 +40 chanx_left_in[6]:31 chanx_right_in[17]:25 0.0004852014 +41 chanx_left_in[6]:31 chanx_right_in[17]:26 4.193445e-05 +42 chanx_left_in[6] chanx_left_in[2] 0.0008788861 +43 chanx_left_in[6]:30 chanx_left_in[2]:25 0.000366287 +44 chanx_left_in[6]:33 chanx_left_in[2]:33 0.0008788861 +45 chanx_left_in[6]:32 chanx_left_in[2] 0.00013345 +46 chanx_left_in[6]:32 chanx_left_in[2]:26 0.0005973163 +47 chanx_left_in[6]:31 chanx_left_in[2]:25 0.0005973163 +48 chanx_left_in[6]:31 chanx_left_in[2]:26 0.000366287 +49 chanx_left_in[6]:31 chanx_left_in[2]:33 0.00013345 +50 chanx_left_in[6] chanx_left_in[3]:14 0.0004865633 +51 chanx_left_in[6]:33 chanx_left_in[3]:13 0.0004865633 +52 chanx_left_in[6]:33 chanx_left_in[3]:8 1.037986e-05 +53 chanx_left_in[6]:32 chanx_left_in[3]:14 9.232249e-06 +54 chanx_left_in[6]:32 chanx_left_in[3]:7 1.037986e-05 +55 chanx_left_in[6]:31 chanx_left_in[3]:13 9.232249e-06 +56 chanx_left_in[6]:30 chanx_left_in[11]:10 4.001911e-05 +57 chanx_left_in[6]:21 chanx_left_in[11]:3 2.491647e-08 +58 chanx_left_in[6]:20 chanx_left_in[11]:4 2.491647e-08 +59 chanx_left_in[6]:32 chanx_left_in[11]:12 0.0001888553 +60 chanx_left_in[6]:32 chanx_left_in[11]:11 0.0004474504 +61 chanx_left_in[6]:31 chanx_left_in[11]:10 0.0004474504 +62 chanx_left_in[6]:31 chanx_left_in[11]:11 0.0002288744 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:33 0.005788832 +1 chanx_left_in[6]:28 chanx_left_in[6]:27 0.0001847826 +2 chanx_left_in[6]:28 chanx_left_in[6]:26 0.004888393 +3 chanx_left_in[6]:29 chanx_left_in[6]:28 0.0045 +4 chanx_left_in[6]:30 chanx_left_in[6]:29 0.00341 +5 chanx_left_in[6]:18 chanx_left_in[6]:17 0.002546875 +6 chanx_left_in[6]:19 chanx_left_in[6]:18 0.0045 +7 chanx_left_in[6]:17 mux_right_track_8\/mux_l2_in_2_:A0 0.152 +8 chanx_left_in[6]:16 chanx_left_in[6]:15 0.0045 +9 chanx_left_in[6]:15 chanx_left_in[6]:14 0.001741071 +10 chanx_left_in[6]:13 chanx_left_in[6]:12 0.00078125 +11 chanx_left_in[6]:14 chanx_left_in[6]:13 0.0045 +12 chanx_left_in[6]:12 chanx_left_in[6]:11 0.0045 +13 chanx_left_in[6]:11 chanx_left_in[6]:10 0.0005267858 +14 chanx_left_in[6]:9 chanx_left_in[6]:8 0.009294644 +15 chanx_left_in[6]:10 chanx_left_in[6]:9 0.0045 +16 chanx_left_in[6]:8 chanx_left_in[6]:7 0.0045 +17 chanx_left_in[6]:7 chanx_left_in[6]:6 0.0005267857 +18 chanx_left_in[6]:5 ropt_mt_inst_806:A 0.152 +19 chanx_left_in[6]:6 chanx_left_in[6]:5 0.0045 +20 chanx_left_in[6]:21 chanx_left_in[6]:20 0.0003370536 +21 chanx_left_in[6]:22 chanx_left_in[6]:21 0.0045 +22 chanx_left_in[6]:22 chanx_left_in[6]:19 0.01240625 +23 chanx_left_in[6]:20 mux_top_track_8\/mux_l2_in_2_:A1 0.152 +24 chanx_left_in[6]:27 mux_bottom_track_9\/mux_l2_in_2_:A1 0.152 +25 chanx_left_in[6]:26 chanx_left_in[6]:25 0.0045 +26 chanx_left_in[6]:26 chanx_left_in[6]:16 0.01679911 +27 chanx_left_in[6]:25 chanx_left_in[6]:24 0.002691964 +28 chanx_left_in[6]:23 chanx_left_in[6]:22 0.001821429 +29 chanx_left_in[6]:24 chanx_left_in[6]:23 0.0004107143 +30 chanx_left_in[6]:33 chanx_left_in[6]:32 0.0001065333 +31 chanx_left_in[6]:32 chanx_left_in[6]:31 0.007809833 +32 chanx_left_in[6]:31 chanx_left_in[6]:30 0.001701792 + +*END + +*D_NET chanx_left_in[18] 0.03006519 //LENGTH 170.385 LUMPCC 0.01141036 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 68.000 +*I mux_bottom_track_25\/mux_l2_in_2_:A0 I *L 0.001631 *C 32.375 66.300 +*I mux_top_track_24\/mux_l2_in_3_:A1 I *L 0.00198 *C 56.945 66.980 +*I ropt_mt_inst_802:A I *L 0.001767 *C 134.780 91.120 +*I mux_right_track_24\/mux_l2_in_3_:A1 I *L 0.00198 *C 97.060 74.460 +*N chanx_left_in[18]:5 *C 97.060 74.460 +*N chanx_left_in[18]:6 *C 97.060 74.460 +*N chanx_left_in[18]:7 *C 134.817 91.120 +*N chanx_left_in[18]:8 *C 137.035 91.120 +*N chanx_left_in[18]:9 *C 137.080 91.075 +*N chanx_left_in[18]:10 *C 137.080 78.258 +*N chanx_left_in[18]:11 *C 137.073 78.200 +*N chanx_left_in[18]:12 *C 132.488 78.200 +*N chanx_left_in[18]:13 *C 132.480 78.142 +*N chanx_left_in[18]:14 *C 132.480 74.178 +*N chanx_left_in[18]:15 *C 132.472 74.120 +*N chanx_left_in[18]:16 *C 97.068 74.120 +*N chanx_left_in[18]:17 *C 97.060 74.062 +*N chanx_left_in[18]:18 *C 97.060 68.058 +*N chanx_left_in[18]:19 *C 97.053 68.000 +*N chanx_left_in[18]:20 *C 73.140 68.000 +*N chanx_left_in[18]:21 *C 73.140 67.320 +*N chanx_left_in[18]:22 *C 57.047 67.320 +*N chanx_left_in[18]:23 *C 57.040 67.320 +*N chanx_left_in[18]:24 *C 56.945 66.980 +*N chanx_left_in[18]:25 *C 57.040 66.980 +*N chanx_left_in[18]:26 *C 57.040 66.640 +*N chanx_left_in[18]:27 *C 57.033 66.640 +*N chanx_left_in[18]:28 *C 35.428 66.640 +*N chanx_left_in[18]:29 *C 35.420 66.698 +*N chanx_left_in[18]:30 *C 35.420 67.275 +*N chanx_left_in[18]:31 *C 35.375 67.320 +*N chanx_left_in[18]:32 *C 32.375 66.300 +*N chanx_left_in[18]:33 *C 32.200 66.300 +*N chanx_left_in[18]:34 *C 32.200 66.345 +*N chanx_left_in[18]:35 *C 32.200 67.275 +*N chanx_left_in[18]:36 *C 32.200 67.320 +*N chanx_left_in[18]:37 *C 25.345 67.320 +*N chanx_left_in[18]:38 *C 25.300 67.365 +*N chanx_left_in[18]:39 *C 25.300 67.943 +*N chanx_left_in[18]:40 *C 25.293 68.000 + +*CAP +0 chanx_left_in[18] 0.001288752 +1 mux_bottom_track_25\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_24\/mux_l2_in_3_:A1 1e-06 +3 ropt_mt_inst_802:A 1e-06 +4 mux_right_track_24\/mux_l2_in_3_:A1 1e-06 +5 chanx_left_in[18]:5 3.995692e-05 +6 chanx_left_in[18]:6 5.98701e-05 +7 chanx_left_in[18]:7 0.0001665275 +8 chanx_left_in[18]:8 0.0001665275 +9 chanx_left_in[18]:9 0.0006515199 +10 chanx_left_in[18]:10 0.0006515199 +11 chanx_left_in[18]:11 0.0002464355 +12 chanx_left_in[18]:12 0.0002464355 +13 chanx_left_in[18]:13 0.000227134 +14 chanx_left_in[18]:14 0.000227134 +15 chanx_left_in[18]:15 0.001573194 +16 chanx_left_in[18]:16 0.001573194 +17 chanx_left_in[18]:17 0.0003539668 +18 chanx_left_in[18]:18 0.0003296121 +19 chanx_left_in[18]:19 0.001345166 +20 chanx_left_in[18]:20 0.001409431 +21 chanx_left_in[18]:21 0.001183756 +22 chanx_left_in[18]:22 0.001119491 +23 chanx_left_in[18]:23 6.028816e-05 +24 chanx_left_in[18]:24 2.905965e-05 +25 chanx_left_in[18]:25 7.905185e-05 +26 chanx_left_in[18]:26 6.06281e-05 +27 chanx_left_in[18]:27 0.001262313 +28 chanx_left_in[18]:28 0.001262313 +29 chanx_left_in[18]:29 6.010171e-05 +30 chanx_left_in[18]:30 6.010171e-05 +31 chanx_left_in[18]:31 0.0001525156 +32 chanx_left_in[18]:32 5.146701e-05 +33 chanx_left_in[18]:33 5.597741e-05 +34 chanx_left_in[18]:34 7.619405e-05 +35 chanx_left_in[18]:35 7.619405e-05 +36 chanx_left_in[18]:36 0.000639252 +37 chanx_left_in[18]:37 0.0004545565 +38 chanx_left_in[18]:38 6.122743e-05 +39 chanx_left_in[18]:39 6.122743e-05 +40 chanx_left_in[18]:40 0.001288752 +41 chanx_left_in[18]:19 chany_top_in[16]:19 0.001205951 +42 chanx_left_in[18]:20 chany_top_in[16]:20 0.001205951 +43 chanx_left_in[18] chanx_right_in[6]:20 0.0008765344 +44 chanx_left_in[18]:27 chanx_right_in[6]:21 5.72783e-05 +45 chanx_left_in[18]:28 chanx_right_in[6]:20 5.72783e-05 +46 chanx_left_in[18]:16 chanx_right_in[6]:29 4.423975e-06 +47 chanx_left_in[18]:16 chanx_right_in[6]:33 7.558014e-05 +48 chanx_left_in[18]:15 chanx_right_in[6]:30 4.423975e-06 +49 chanx_left_in[18]:15 chanx_right_in[6]:34 7.558014e-05 +50 chanx_left_in[18]:12 chanx_right_in[6]:33 0.000109822 +51 chanx_left_in[18]:11 chanx_right_in[6]:34 0.000109822 +52 chanx_left_in[18]:22 chanx_right_in[6]:20 4.349302e-05 +53 chanx_left_in[18]:22 chanx_right_in[6]:21 0.0001935091 +54 chanx_left_in[18]:40 chanx_right_in[6]:21 0.0008765344 +55 chanx_left_in[18]:21 chanx_right_in[6]:21 4.349302e-05 +56 chanx_left_in[18]:21 chanx_right_in[6]:22 0.0001935091 +57 chanx_left_in[18]:21 chanx_right_in[6]:24 8.829885e-06 +58 chanx_left_in[18]:20 chanx_right_in[6]:23 8.829885e-06 +59 chanx_left_in[18]:16 chany_bottom_in[14]:38 0.000814721 +60 chanx_left_in[18]:15 chany_bottom_in[14]:9 0.000814721 +61 chanx_left_in[18] chanx_left_in[9] 9.773039e-06 +62 chanx_left_in[18] chanx_left_in[9]:47 1.700031e-06 +63 chanx_left_in[18]:27 chanx_left_in[9]:32 0.0007378361 +64 chanx_left_in[18]:29 chanx_left_in[9]:34 2.351587e-06 +65 chanx_left_in[18]:28 chanx_left_in[9]:33 0.0007378361 +66 chanx_left_in[18]:31 chanx_left_in[9]:36 0.0001040927 +67 chanx_left_in[18]:31 chanx_left_in[9]:37 2.067088e-05 +68 chanx_left_in[18]:30 chanx_left_in[9]:35 2.351587e-06 +69 chanx_left_in[18]:17 chanx_left_in[9]:19 3.043125e-06 +70 chanx_left_in[18]:18 chanx_left_in[9]:20 3.043125e-06 +71 chanx_left_in[18]:36 chanx_left_in[9]:37 0.0001602243 +72 chanx_left_in[18]:36 chanx_left_in[9]:38 2.067088e-05 +73 chanx_left_in[18]:33 chanx_left_in[9]:38 2.344112e-06 +74 chanx_left_in[18]:32 chanx_left_in[9]:37 2.344112e-06 +75 chanx_left_in[18]:37 chanx_left_in[9]:38 5.613166e-05 +76 chanx_left_in[18]:40 chanx_left_in[9]:46 1.700031e-06 +77 chanx_left_in[18]:40 chanx_left_in[9]:48 9.773039e-06 +78 chanx_left_in[18]:16 chanx_right_in[7]:26 8.590391e-05 +79 chanx_left_in[18]:16 chanx_right_in[7]:18 0.0001826541 +80 chanx_left_in[18]:15 chanx_right_in[7] 8.590391e-05 +81 chanx_left_in[18]:15 chanx_right_in[7]:19 0.0001826541 +82 chanx_left_in[18]:19 chany_bottom_in[3]:24 0.0003282011 +83 chanx_left_in[18]:20 chany_bottom_in[3]:25 0.0003282011 +84 chanx_left_in[18]:16 mux_tree_tapbuf_size16_1_sram[2]:17 0.0004851948 +85 chanx_left_in[18]:15 mux_tree_tapbuf_size16_1_sram[2]:16 0.0004851948 +86 chanx_left_in[18]:22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.050041e-05 +87 chanx_left_in[18]:21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.050041e-05 +88 chanx_left_in[18]:17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.594766e-05 +89 chanx_left_in[18]:18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.594766e-05 +90 chanx_left_in[18] ropt_net_222:6 0.0001174017 +91 chanx_left_in[18]:40 ropt_net_222:7 0.0001174017 +92 chanx_left_in[18]:14 ropt_net_177:4 6.319165e-07 +93 chanx_left_in[18]:14 ropt_net_177:5 7.370074e-07 +94 chanx_left_in[18]:13 ropt_net_177:6 7.370074e-07 +95 chanx_left_in[18]:13 ropt_net_177:3 6.319165e-07 +96 chanx_left_in[18]:10 ropt_net_177:5 5.991986e-05 +97 chanx_left_in[18]:9 ropt_net_177:6 5.991986e-05 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:40 0.003769791 +1 chanx_left_in[18]:26 chanx_left_in[18]:25 0.0001634615 +2 chanx_left_in[18]:27 chanx_left_in[18]:26 0.00341 +3 chanx_left_in[18]:29 chanx_left_in[18]:28 0.00341 +4 chanx_left_in[18]:28 chanx_left_in[18]:27 0.003384783 +5 chanx_left_in[18]:31 chanx_left_in[18]:30 0.0045 +6 chanx_left_in[18]:30 chanx_left_in[18]:29 0.000515625 +7 chanx_left_in[18]:17 chanx_left_in[18]:16 0.00341 +8 chanx_left_in[18]:17 chanx_left_in[18]:6 0.0001911058 +9 chanx_left_in[18]:16 chanx_left_in[18]:15 0.005546783 +10 chanx_left_in[18]:14 chanx_left_in[18]:13 0.003540179 +11 chanx_left_in[18]:15 chanx_left_in[18]:14 0.00341 +12 chanx_left_in[18]:13 chanx_left_in[18]:12 0.00341 +13 chanx_left_in[18]:12 chanx_left_in[18]:11 0.0007183166 +14 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0114442 +15 chanx_left_in[18]:11 chanx_left_in[18]:10 0.00341 +16 chanx_left_in[18]:8 chanx_left_in[18]:7 0.001979911 +17 chanx_left_in[18]:9 chanx_left_in[18]:8 0.0045 +18 chanx_left_in[18]:7 ropt_mt_inst_802:A 0.152 +19 chanx_left_in[18]:5 mux_right_track_24\/mux_l2_in_3_:A1 0.152 +20 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0045 +21 chanx_left_in[18]:18 chanx_left_in[18]:17 0.005361607 +22 chanx_left_in[18]:19 chanx_left_in[18]:18 0.00341 +23 chanx_left_in[18]:23 chanx_left_in[18]:22 0.00341 +24 chanx_left_in[18]:22 chanx_left_in[18]:21 0.002521158 +25 chanx_left_in[18]:36 chanx_left_in[18]:35 0.0045 +26 chanx_left_in[18]:36 chanx_left_in[18]:31 0.002834822 +27 chanx_left_in[18]:35 chanx_left_in[18]:34 0.0008303572 +28 chanx_left_in[18]:33 chanx_left_in[18]:32 9.51087e-05 +29 chanx_left_in[18]:34 chanx_left_in[18]:33 0.0045 +30 chanx_left_in[18]:32 mux_bottom_track_25\/mux_l2_in_2_:A0 0.152 +31 chanx_left_in[18]:24 mux_top_track_24\/mux_l2_in_3_:A1 0.152 +32 chanx_left_in[18]:25 chanx_left_in[18]:24 0.0045 +33 chanx_left_in[18]:25 chanx_left_in[18]:23 0.0001057692 +34 chanx_left_in[18]:37 chanx_left_in[18]:36 0.006120536 +35 chanx_left_in[18]:38 chanx_left_in[18]:37 0.0045 +36 chanx_left_in[18]:39 chanx_left_in[18]:38 0.000515625 +37 chanx_left_in[18]:40 chanx_left_in[18]:39 0.00341 +38 chanx_left_in[18]:21 chanx_left_in[18]:20 0.0001065333 +39 chanx_left_in[18]:20 chanx_left_in[18]:19 0.003746291 + +*END + +*D_NET top_left_grid_pin_38_[0] 0.006581298 //LENGTH 49.335 LUMPCC 0.0004356695 DR + +*CONN +*P top_left_grid_pin_38_[0] I *L 0.29796 *C 29.818 125.120 +*I mux_top_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 33.755 124.100 +*I mux_top_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 62.100 117.980 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.945 114.920 +*N top_left_grid_pin_38_[0]:4 *C 60.983 114.920 +*N top_left_grid_pin_38_[0]:5 *C 62.055 114.920 +*N top_left_grid_pin_38_[0]:6 *C 62.100 114.965 +*N top_left_grid_pin_38_[0]:7 *C 62.100 117.980 +*N top_left_grid_pin_38_[0]:8 *C 62.100 117.980 +*N top_left_grid_pin_38_[0]:9 *C 62.100 120.315 +*N top_left_grid_pin_38_[0]:10 *C 62.055 120.360 +*N top_left_grid_pin_38_[0]:11 *C 29.945 120.360 +*N top_left_grid_pin_38_[0]:12 *C 29.900 120.405 +*N top_left_grid_pin_38_[0]:13 *C 33.718 124.100 +*N top_left_grid_pin_38_[0]:14 *C 29.945 124.100 +*N top_left_grid_pin_38_[0]:15 *C 29.900 124.100 +*N top_left_grid_pin_38_[0]:16 *C 29.900 125.062 +*N top_left_grid_pin_38_[0]:17 *C 29.900 125.120 + +*CAP +0 top_left_grid_pin_38_[0] 3.073959e-05 +1 mux_top_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_0\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_38_[0]:4 9.862213e-05 +5 top_left_grid_pin_38_[0]:5 9.862213e-05 +6 top_left_grid_pin_38_[0]:6 0.0001715804 +7 top_left_grid_pin_38_[0]:7 3.315356e-05 +8 top_left_grid_pin_38_[0]:8 0.0003479887 +9 top_left_grid_pin_38_[0]:9 0.0001419894 +10 top_left_grid_pin_38_[0]:10 0.002074633 +11 top_left_grid_pin_38_[0]:11 0.002074633 +12 top_left_grid_pin_38_[0]:12 0.000185333 +13 top_left_grid_pin_38_[0]:13 0.000262009 +14 top_left_grid_pin_38_[0]:14 0.000262009 +15 top_left_grid_pin_38_[0]:15 0.0002725867 +16 top_left_grid_pin_38_[0]:16 5.798882e-05 +17 top_left_grid_pin_38_[0]:17 3.073959e-05 +18 top_left_grid_pin_38_[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 8.249078e-05 +19 top_left_grid_pin_38_[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 8.249078e-05 +20 top_left_grid_pin_38_[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:9 2.728752e-09 +21 top_left_grid_pin_38_[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.072849e-05 +22 top_left_grid_pin_38_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:8 2.728752e-09 +23 top_left_grid_pin_38_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.072849e-05 +24 top_left_grid_pin_38_[0]:10 ropt_net_185:3 7.461273e-05 +25 top_left_grid_pin_38_[0]:11 ropt_net_185:2 7.461273e-05 + +*RES +0 top_left_grid_pin_38_[0] top_left_grid_pin_38_[0]:17 2.35e-05 +1 top_left_grid_pin_38_[0]:7 mux_top_track_0\/mux_l1_in_1_:A1 0.152 +2 top_left_grid_pin_38_[0]:8 top_left_grid_pin_38_[0]:7 0.0045 +3 top_left_grid_pin_38_[0]:8 top_left_grid_pin_38_[0]:6 0.002691964 +4 top_left_grid_pin_38_[0]:4 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +5 top_left_grid_pin_38_[0]:5 top_left_grid_pin_38_[0]:4 0.0009575893 +6 top_left_grid_pin_38_[0]:6 top_left_grid_pin_38_[0]:5 0.0045 +7 top_left_grid_pin_38_[0]:10 top_left_grid_pin_38_[0]:9 0.0045 +8 top_left_grid_pin_38_[0]:9 top_left_grid_pin_38_[0]:8 0.002084821 +9 top_left_grid_pin_38_[0]:11 top_left_grid_pin_38_[0]:10 0.02866965 +10 top_left_grid_pin_38_[0]:12 top_left_grid_pin_38_[0]:11 0.0045 +11 top_left_grid_pin_38_[0]:14 top_left_grid_pin_38_[0]:13 0.003368304 +12 top_left_grid_pin_38_[0]:15 top_left_grid_pin_38_[0]:14 0.0045 +13 top_left_grid_pin_38_[0]:15 top_left_grid_pin_38_[0]:12 0.003299107 +14 top_left_grid_pin_38_[0]:13 mux_top_track_4\/mux_l2_in_1_:A0 0.152 +15 top_left_grid_pin_38_[0]:16 top_left_grid_pin_38_[0]:15 0.0008593751 +16 top_left_grid_pin_38_[0]:17 top_left_grid_pin_38_[0]:16 0.00341 + +*END + +*D_NET chanx_right_in[15] 0.01792528 //LENGTH 103.330 LUMPCC 0.007744406 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 140.375 57.120 +*I mux_bottom_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 80.140 36.380 +*I mux_top_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.830 49.640 +*N chanx_right_in[15]:3 *C 68.830 49.640 +*N chanx_right_in[15]:4 *C 69.000 49.640 +*N chanx_right_in[15]:5 *C 69.000 49.595 +*N chanx_right_in[15]:6 *C 69.000 44.258 +*N chanx_right_in[15]:7 *C 69.008 44.200 +*N chanx_right_in[15]:8 *C 80.040 36.380 +*N chanx_right_in[15]:9 *C 80.040 36.425 +*N chanx_right_in[15]:10 *C 80.040 44.143 +*N chanx_right_in[15]:11 *C 80.040 44.200 +*N chanx_right_in[15]:12 *C 84.620 44.200 +*N chanx_right_in[15]:13 *C 84.640 44.208 +*N chanx_right_in[15]:14 *C 84.640 58.473 +*N chanx_right_in[15]:15 *C 84.660 58.480 +*N chanx_right_in[15]:16 *C 100.740 58.480 +*N chanx_right_in[15]:17 *C 100.740 57.800 +*N chanx_right_in[15]:18 *C 136.160 57.800 +*N chanx_right_in[15]:19 *C 136.160 57.120 + +*CAP +0 chanx_right_in[15] 0.0001917986 +1 mux_bottom_track_1\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[15]:3 5.630295e-05 +4 chanx_right_in[15]:4 5.750459e-05 +5 chanx_right_in[15]:5 0.0002188015 +6 chanx_right_in[15]:6 0.0002188015 +7 chanx_right_in[15]:7 0.0007232547 +8 chanx_right_in[15]:8 3.289985e-05 +9 chanx_right_in[15]:9 0.0003879932 +10 chanx_right_in[15]:10 0.0003879932 +11 chanx_right_in[15]:11 0.0009172814 +12 chanx_right_in[15]:12 0.0001940267 +13 chanx_right_in[15]:13 0.001137801 +14 chanx_right_in[15]:14 0.001137801 +15 chanx_right_in[15]:15 0.0009706291 +16 chanx_right_in[15]:16 0.001020521 +17 chanx_right_in[15]:17 0.001134747 +18 chanx_right_in[15]:18 0.001141885 +19 chanx_right_in[15]:19 0.0002488284 +20 chanx_right_in[15]:11 chany_top_in[9]:20 4.304997e-05 +21 chanx_right_in[15]:11 chany_top_in[9]:24 0.0001250322 +22 chanx_right_in[15]:6 chany_top_in[9]:26 0.0001171586 +23 chanx_right_in[15]:7 chany_top_in[9]:24 4.304997e-05 +24 chanx_right_in[15]:7 chany_top_in[9]:25 0.0001250322 +25 chanx_right_in[15]:5 chany_top_in[9]:27 0.0001171586 +26 chanx_right_in[15] chanx_right_in[2] 4.072137e-05 +27 chanx_right_in[15] chanx_right_in[2]:48 0.0001707317 +28 chanx_right_in[15]:15 chanx_right_in[2]:47 7.872648e-05 +29 chanx_right_in[15]:16 chanx_right_in[2]:48 7.872648e-05 +30 chanx_right_in[15]:17 chanx_right_in[2]:47 0.0008067296 +31 chanx_right_in[15]:18 chanx_right_in[2]:48 0.0008067296 +32 chanx_right_in[15]:19 chanx_right_in[2]:47 0.0001707317 +33 chanx_right_in[15]:19 chanx_right_in[2]:49 4.072137e-05 +34 chanx_right_in[15]:12 chanx_right_in[8]:29 0.0002599392 +35 chanx_right_in[15]:11 chanx_right_in[8]:28 0.0002599392 +36 chanx_right_in[15]:11 chanx_right_in[8]:29 0.0001471859 +37 chanx_right_in[15]:6 chanx_right_in[8]:20 7.457371e-05 +38 chanx_right_in[15]:7 chanx_right_in[8]:28 0.0001471859 +39 chanx_right_in[15]:5 chanx_right_in[8]:19 7.457371e-05 +40 chanx_right_in[15]:13 chany_bottom_in[9]:34 0.0005724113 +41 chanx_right_in[15]:14 chany_bottom_in[9]:33 0.0005724113 +42 chanx_right_in[15]:12 prog_clk[0]:224 3.184016e-06 +43 chanx_right_in[15]:12 prog_clk[0]:228 3.184016e-06 +44 chanx_right_in[15]:10 prog_clk[0]:298 5.845837e-05 +45 chanx_right_in[15]:11 prog_clk[0]:228 3.184016e-06 +46 chanx_right_in[15]:11 prog_clk[0]:300 3.184016e-06 +47 chanx_right_in[15]:9 prog_clk[0]:299 5.845837e-05 +48 chanx_right_in[15]:16 prog_clk[0]:195 1.167001e-05 +49 chanx_right_in[15]:17 prog_clk[0]:182 0.0002717634 +50 chanx_right_in[15]:17 prog_clk[0]:192 0.0003109876 +51 chanx_right_in[15]:17 prog_clk[0]:193 0.0002387938 +52 chanx_right_in[15]:17 prog_clk[0]:196 1.167001e-05 +53 chanx_right_in[15]:18 prog_clk[0]:178 0.0002717634 +54 chanx_right_in[15]:18 prog_clk[0]:182 0.0003109876 +55 chanx_right_in[15]:18 prog_clk[0]:192 0.0002387938 +56 chanx_right_in[15]:15 mux_tree_tapbuf_size10_0_sram[0]:20 0.0003282294 +57 chanx_right_in[15]:16 mux_tree_tapbuf_size10_0_sram[0]:19 0.0003282294 +58 chanx_right_in[15]:15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 7.237944e-05 +59 chanx_right_in[15]:16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.237944e-05 +60 chanx_right_in[15]:17 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001372923 +61 chanx_right_in[15]:18 mux_right_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001372923 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:19 0.00066035 +1 chanx_right_in[15]:12 chanx_right_in[15]:11 0.0007175333 +2 chanx_right_in[15]:13 chanx_right_in[15]:12 0.00341 +3 chanx_right_in[15]:15 chanx_right_in[15]:14 0.00341 +4 chanx_right_in[15]:14 chanx_right_in[15]:13 0.00223485 +5 chanx_right_in[15]:10 chanx_right_in[15]:9 0.006890625 +6 chanx_right_in[15]:11 chanx_right_in[15]:10 0.00341 +7 chanx_right_in[15]:11 chanx_right_in[15]:7 0.001728425 +8 chanx_right_in[15]:8 mux_bottom_track_1\/mux_l1_in_2_:A1 0.152 +9 chanx_right_in[15]:9 chanx_right_in[15]:8 0.0045 +10 chanx_right_in[15]:6 chanx_right_in[15]:5 0.004765626 +11 chanx_right_in[15]:7 chanx_right_in[15]:6 0.00341 +12 chanx_right_in[15]:4 chanx_right_in[15]:3 9.239131e-05 +13 chanx_right_in[15]:5 chanx_right_in[15]:4 0.0045 +14 chanx_right_in[15]:3 mux_top_track_16\/mux_l1_in_1_:A0 0.152 +15 chanx_right_in[15]:16 chanx_right_in[15]:15 0.0025192 +16 chanx_right_in[15]:17 chanx_right_in[15]:16 0.0001065333 +17 chanx_right_in[15]:18 chanx_right_in[15]:17 0.005549133 +18 chanx_right_in[15]:19 chanx_right_in[15]:18 0.0001065333 + +*END + +*D_NET bottom_left_grid_pin_36_[0] 0.01231219 //LENGTH 96.675 LUMPCC 0.001932135 DR + +*CONN +*P bottom_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 6.800 +*I mux_bottom_track_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 31.840 30.940 +*I mux_bottom_track_1\/mux_l1_in_3_:A1 I *L 0.00198 *C 75.440 23.460 +*I mux_bottom_track_25\/mux_l1_in_2_:A0 I *L 0.001631 *C 54.580 44.200 +*N bottom_left_grid_pin_36_[0]:4 *C 54.580 44.200 +*N bottom_left_grid_pin_36_[0]:5 *C 54.740 44.200 +*N bottom_left_grid_pin_36_[0]:6 *C 54.740 44.155 +*N bottom_left_grid_pin_36_[0]:7 *C 75.440 23.475 +*N bottom_left_grid_pin_36_[0]:8 *C 75.440 23.800 +*N bottom_left_grid_pin_36_[0]:9 *C 75.440 23.845 +*N bottom_left_grid_pin_36_[0]:10 *C 75.440 25.103 +*N bottom_left_grid_pin_36_[0]:11 *C 75.433 25.160 +*N bottom_left_grid_pin_36_[0]:12 *C 54.748 25.160 +*N bottom_left_grid_pin_36_[0]:13 *C 54.740 25.218 +*N bottom_left_grid_pin_36_[0]:14 *C 54.740 30.600 +*N bottom_left_grid_pin_36_[0]:15 *C 54.733 30.600 +*N bottom_left_grid_pin_36_[0]:16 *C 37.267 30.600 +*N bottom_left_grid_pin_36_[0]:17 *C 37.260 30.658 +*N bottom_left_grid_pin_36_[0]:18 *C 37.260 31.575 +*N bottom_left_grid_pin_36_[0]:19 *C 37.215 31.620 +*N bottom_left_grid_pin_36_[0]:20 *C 32.200 31.620 +*N bottom_left_grid_pin_36_[0]:21 *C 31.855 30.940 +*N bottom_left_grid_pin_36_[0]:22 *C 32.165 30.940 +*N bottom_left_grid_pin_36_[0]:23 *C 32.200 31.280 +*N bottom_left_grid_pin_36_[0]:24 *C 32.200 31.235 +*N bottom_left_grid_pin_36_[0]:25 *C 32.200 6.857 +*N bottom_left_grid_pin_36_[0]:26 *C 32.193 6.800 + +*CAP +0 bottom_left_grid_pin_36_[0] 0.000135492 +1 mux_bottom_track_5\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_3_:A1 1e-06 +3 mux_bottom_track_25\/mux_l1_in_2_:A0 1e-06 +4 bottom_left_grid_pin_36_[0]:4 6.584737e-05 +5 bottom_left_grid_pin_36_[0]:5 6.207608e-05 +6 bottom_left_grid_pin_36_[0]:6 0.0006229141 +7 bottom_left_grid_pin_36_[0]:7 3.843493e-05 +8 bottom_left_grid_pin_36_[0]:8 7.402686e-05 +9 bottom_left_grid_pin_36_[0]:9 0.0001065843 +10 bottom_left_grid_pin_36_[0]:10 0.0001065843 +11 bottom_left_grid_pin_36_[0]:11 0.001242051 +12 bottom_left_grid_pin_36_[0]:12 0.001242051 +13 bottom_left_grid_pin_36_[0]:13 0.0002758569 +14 bottom_left_grid_pin_36_[0]:14 0.0009386523 +15 bottom_left_grid_pin_36_[0]:15 0.0009636106 +16 bottom_left_grid_pin_36_[0]:16 0.0009636106 +17 bottom_left_grid_pin_36_[0]:17 7.765787e-05 +18 bottom_left_grid_pin_36_[0]:18 7.765787e-05 +19 bottom_left_grid_pin_36_[0]:19 0.0003225072 +20 bottom_left_grid_pin_36_[0]:20 0.000353823 +21 bottom_left_grid_pin_36_[0]:21 4.756287e-05 +22 bottom_left_grid_pin_36_[0]:22 8.542185e-05 +23 bottom_left_grid_pin_36_[0]:23 0.0001050151 +24 bottom_left_grid_pin_36_[0]:24 0.001167059 +25 bottom_left_grid_pin_36_[0]:25 0.001167059 +26 bottom_left_grid_pin_36_[0]:26 0.000135492 +27 bottom_left_grid_pin_36_[0]:18 prog_clk[0]:374 2.467453e-07 +28 bottom_left_grid_pin_36_[0]:18 prog_clk[0]:377 4.009611e-07 +29 bottom_left_grid_pin_36_[0]:17 prog_clk[0]:377 2.467453e-07 +30 bottom_left_grid_pin_36_[0]:17 prog_clk[0]:378 4.009611e-07 +31 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:368 0.0001411354 +32 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:373 3.591828e-06 +33 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:379 0.0001592235 +34 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:401 3.171427e-05 +35 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:648 1.436335e-05 +36 bottom_left_grid_pin_36_[0]:14 prog_clk[0]:310 2.511062e-05 +37 bottom_left_grid_pin_36_[0]:14 prog_clk[0]:320 2.520609e-06 +38 bottom_left_grid_pin_36_[0]:14 prog_clk[0]:321 4.122046e-06 +39 bottom_left_grid_pin_36_[0]:14 prog_clk[0]:322 6.249486e-06 +40 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:323 0.0001411354 +41 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:368 0.0001592235 +42 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:372 3.591828e-06 +43 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:379 3.171427e-05 +44 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:401 1.436335e-05 +45 bottom_left_grid_pin_36_[0]:6 prog_clk[0]:309 2.511062e-05 +46 bottom_left_grid_pin_36_[0]:6 prog_clk[0]:316 2.520609e-06 +47 bottom_left_grid_pin_36_[0]:6 prog_clk[0]:320 4.122046e-06 +48 bottom_left_grid_pin_36_[0]:6 prog_clk[0]:321 6.249486e-06 +49 bottom_left_grid_pin_36_[0]:12 prog_clk[0]:323 5.510588e-05 +50 bottom_left_grid_pin_36_[0]:12 prog_clk[0]:368 4.341486e-06 +51 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:303 5.510588e-05 +52 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:323 4.341486e-06 +53 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_35_[0] 3.617592e-05 +54 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_35_[0]:21 0.0001165773 +55 bottom_left_grid_pin_36_[0]:26 bottom_left_grid_pin_35_[0]:22 3.617592e-05 +56 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_35_[0]:20 0.0001165773 +57 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_35_[0]:12 0.0001913836 +58 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_35_[0]:11 0.0001913836 +59 bottom_left_grid_pin_36_[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.049449e-05 +60 bottom_left_grid_pin_36_[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.049449e-05 +61 bottom_left_grid_pin_36_[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.919804e-05 +62 bottom_left_grid_pin_36_[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.411224e-05 +63 bottom_left_grid_pin_36_[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:6 3.411224e-05 +64 bottom_left_grid_pin_36_[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_9_X[0]:5 5.919804e-05 + +*RES +0 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_36_[0]:26 0.0003826584 +1 bottom_left_grid_pin_36_[0]:21 mux_bottom_track_5\/mux_l2_in_3_:A1 0.152 +2 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_36_[0]:24 0.02176563 +3 bottom_left_grid_pin_36_[0]:26 bottom_left_grid_pin_36_[0]:25 0.00341 +4 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_36_[0]:22 0.0001545455 +5 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_36_[0]:20 0.0003035714 +6 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_36_[0]:23 0.0045 +7 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:18 0.0045 +8 bottom_left_grid_pin_36_[0]:18 bottom_left_grid_pin_36_[0]:17 0.0008191965 +9 bottom_left_grid_pin_36_[0]:17 bottom_left_grid_pin_36_[0]:16 0.00341 +10 bottom_left_grid_pin_36_[0]:16 bottom_left_grid_pin_36_[0]:15 0.002736183 +11 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_36_[0]:13 0.004805804 +12 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_36_[0]:6 0.01210268 +13 bottom_left_grid_pin_36_[0]:15 bottom_left_grid_pin_36_[0]:14 0.00341 +14 bottom_left_grid_pin_36_[0]:5 bottom_left_grid_pin_36_[0]:4 8.695653e-05 +15 bottom_left_grid_pin_36_[0]:6 bottom_left_grid_pin_36_[0]:5 0.0045 +16 bottom_left_grid_pin_36_[0]:4 mux_bottom_track_25\/mux_l1_in_2_:A0 0.152 +17 bottom_left_grid_pin_36_[0]:13 bottom_left_grid_pin_36_[0]:12 0.00341 +18 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_36_[0]:11 0.00324065 +19 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_36_[0]:9 0.001122768 +20 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_36_[0]:10 0.00341 +21 bottom_left_grid_pin_36_[0]:8 bottom_left_grid_pin_36_[0]:7 0.0001766305 +22 bottom_left_grid_pin_36_[0]:9 bottom_left_grid_pin_36_[0]:8 0.0045 +23 bottom_left_grid_pin_36_[0]:7 mux_bottom_track_1\/mux_l1_in_3_:A1 0.152 +24 bottom_left_grid_pin_36_[0]:22 bottom_left_grid_pin_36_[0]:21 0.0001684782 +25 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_36_[0]:19 0.004477679 + +*END + +*D_NET left_top_grid_pin_44_[0] 0.008526055 //LENGTH 65.175 LUMPCC 0.000716027 DR + +*CONN +*P left_top_grid_pin_44_[0] I *L 0.29796 *C 4.140 102.035 +*I mux_left_track_5\/mux_l2_in_4_:A0 I *L 0.001631 *C 24.670 91.460 +*I mux_left_track_1\/mux_l1_in_4_:A0 I *L 0.001631 *C 22.335 77.180 +*I mux_left_track_25\/mux_l2_in_2_:A0 I *L 0.001631 *C 22.330 66.300 +*N left_top_grid_pin_44_[0]:4 *C 22.330 66.300 +*N left_top_grid_pin_44_[0]:5 *C 22.080 66.300 +*N left_top_grid_pin_44_[0]:6 *C 22.080 66.345 +*N left_top_grid_pin_44_[0]:7 *C 22.335 77.180 +*N left_top_grid_pin_44_[0]:8 *C 22.080 77.180 +*N left_top_grid_pin_44_[0]:9 *C 22.080 77.180 +*N left_top_grid_pin_44_[0]:10 *C 22.080 80.862 +*N left_top_grid_pin_44_[0]:11 *C 22.088 80.920 +*N left_top_grid_pin_44_[0]:12 *C 25.293 80.920 +*N left_top_grid_pin_44_[0]:13 *C 25.300 80.978 +*N left_top_grid_pin_44_[0]:14 *C 25.300 91.460 +*N left_top_grid_pin_44_[0]:15 *C 24.670 91.460 +*N left_top_grid_pin_44_[0]:16 *C 24.840 91.460 +*N left_top_grid_pin_44_[0]:17 *C 24.840 91.460 +*N left_top_grid_pin_44_[0]:18 *C 24.840 101.615 +*N left_top_grid_pin_44_[0]:19 *C 24.840 101.660 +*N left_top_grid_pin_44_[0]:20 *C 24.840 102.680 +*N left_top_grid_pin_44_[0]:21 *C 4.140 102.680 +*N left_top_grid_pin_44_[0]:22 *C 4.140 101.660 +*N left_top_grid_pin_44_[0]:23 *C 4.140 101.705 + +*CAP +0 left_top_grid_pin_44_[0] 2.923889e-05 +1 mux_left_track_5\/mux_l2_in_4_:A0 1e-06 +2 mux_left_track_1\/mux_l1_in_4_:A0 1e-06 +3 mux_left_track_25\/mux_l2_in_2_:A0 1e-06 +4 left_top_grid_pin_44_[0]:4 5.924761e-05 +5 left_top_grid_pin_44_[0]:5 6.306465e-05 +6 left_top_grid_pin_44_[0]:6 0.0005843382 +7 left_top_grid_pin_44_[0]:7 5.713509e-05 +8 left_top_grid_pin_44_[0]:8 6.177456e-05 +9 left_top_grid_pin_44_[0]:9 0.0008662323 +10 left_top_grid_pin_44_[0]:10 0.000248488 +11 left_top_grid_pin_44_[0]:11 0.0003808863 +12 left_top_grid_pin_44_[0]:12 0.0003808863 +13 left_top_grid_pin_44_[0]:13 0.000632799 +14 left_top_grid_pin_44_[0]:14 0.000666591 +15 left_top_grid_pin_44_[0]:15 5.032519e-05 +16 left_top_grid_pin_44_[0]:16 5.714242e-05 +17 left_top_grid_pin_44_[0]:17 0.0006054778 +18 left_top_grid_pin_44_[0]:18 0.0005716857 +19 left_top_grid_pin_44_[0]:19 9.288311e-05 +20 left_top_grid_pin_44_[0]:20 0.001137607 +21 left_top_grid_pin_44_[0]:21 0.001138146 +22 left_top_grid_pin_44_[0]:22 9.383964e-05 +23 left_top_grid_pin_44_[0]:23 2.923889e-05 +24 left_top_grid_pin_44_[0] left_top_grid_pin_45_[0] 6.108237e-06 +25 left_top_grid_pin_44_[0]:17 left_top_grid_pin_45_[0]:6 2.387587e-05 +26 left_top_grid_pin_44_[0]:18 left_top_grid_pin_45_[0]:7 2.387587e-05 +27 left_top_grid_pin_44_[0]:23 left_top_grid_pin_45_[0]:28 6.108237e-06 +28 left_top_grid_pin_44_[0]:21 left_top_grid_pin_45_[0]:23 2.24049e-05 +29 left_top_grid_pin_44_[0]:21 left_top_grid_pin_45_[0]:27 7.227217e-05 +30 left_top_grid_pin_44_[0]:21 left_top_grid_pin_45_[0]:25 0.0001429459 +31 left_top_grid_pin_44_[0]:20 left_top_grid_pin_45_[0]:8 2.24049e-05 +32 left_top_grid_pin_44_[0]:20 left_top_grid_pin_45_[0]:26 7.227217e-05 +33 left_top_grid_pin_44_[0]:20 left_top_grid_pin_45_[0]:24 0.0001429459 +34 left_top_grid_pin_44_[0]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.569815e-05 +35 left_top_grid_pin_44_[0]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.687418e-06 +36 left_top_grid_pin_44_[0]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.687418e-06 +37 left_top_grid_pin_44_[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.087337e-08 +38 left_top_grid_pin_44_[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.569815e-05 +39 left_top_grid_pin_44_[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.087337e-08 + +*RES +0 left_top_grid_pin_44_[0] left_top_grid_pin_44_[0]:23 0.0002946429 +1 left_top_grid_pin_44_[0]:7 mux_left_track_1\/mux_l1_in_4_:A0 0.152 +2 left_top_grid_pin_44_[0]:8 left_top_grid_pin_44_[0]:7 0.000138587 +3 left_top_grid_pin_44_[0]:9 left_top_grid_pin_44_[0]:8 0.0045 +4 left_top_grid_pin_44_[0]:9 left_top_grid_pin_44_[0]:6 0.009674108 +5 left_top_grid_pin_44_[0]:10 left_top_grid_pin_44_[0]:9 0.003287946 +6 left_top_grid_pin_44_[0]:11 left_top_grid_pin_44_[0]:10 0.00341 +7 left_top_grid_pin_44_[0]:13 left_top_grid_pin_44_[0]:12 0.00341 +8 left_top_grid_pin_44_[0]:12 left_top_grid_pin_44_[0]:11 0.0005021166 +9 left_top_grid_pin_44_[0]:5 left_top_grid_pin_44_[0]:4 0.0001358696 +10 left_top_grid_pin_44_[0]:6 left_top_grid_pin_44_[0]:5 0.0045 +11 left_top_grid_pin_44_[0]:4 mux_left_track_25\/mux_l2_in_2_:A0 0.152 +12 left_top_grid_pin_44_[0]:16 left_top_grid_pin_44_[0]:15 9.239131e-05 +13 left_top_grid_pin_44_[0]:17 left_top_grid_pin_44_[0]:16 0.0045 +14 left_top_grid_pin_44_[0]:17 left_top_grid_pin_44_[0]:14 0.0004107143 +15 left_top_grid_pin_44_[0]:15 mux_left_track_5\/mux_l2_in_4_:A0 0.152 +16 left_top_grid_pin_44_[0]:19 left_top_grid_pin_44_[0]:18 0.0045 +17 left_top_grid_pin_44_[0]:18 left_top_grid_pin_44_[0]:17 0.009066964 +18 left_top_grid_pin_44_[0]:22 left_top_grid_pin_44_[0]:21 0.0009107143 +19 left_top_grid_pin_44_[0]:23 left_top_grid_pin_44_[0]:22 0.0045 +20 left_top_grid_pin_44_[0]:21 left_top_grid_pin_44_[0]:20 0.01848214 +21 left_top_grid_pin_44_[0]:20 left_top_grid_pin_44_[0]:19 0.0009107143 +22 left_top_grid_pin_44_[0]:14 left_top_grid_pin_44_[0]:13 0.009359375 + +*END + +*D_NET chanx_right_out[8] 0.002249812 //LENGTH 19.165 LUMPCC 0.000164477 DR + +*CONN +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 123.800 44.540 +*P chanx_right_out[8] O *L 0.7423 *C 140.450 46.240 +*N chanx_right_out[8]:2 *C 136.168 46.240 +*N chanx_right_out[8]:3 *C 136.160 46.183 +*N chanx_right_out[8]:4 *C 136.160 44.585 +*N chanx_right_out[8]:5 *C 136.115 44.540 +*N chanx_right_out[8]:6 *C 123.838 44.540 + +*CAP +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[8] 0.0003178465 +2 chanx_right_out[8]:2 0.0003178465 +3 chanx_right_out[8]:3 0.0001085072 +4 chanx_right_out[8]:4 0.0001085072 +5 chanx_right_out[8]:5 0.0006158135 +6 chanx_right_out[8]:6 0.0006158135 +7 chanx_right_out[8] ropt_net_174:6 9.470134e-06 +8 chanx_right_out[8]:6 ropt_net_174:2 6.422746e-05 +9 chanx_right_out[8]:5 ropt_net_174:3 6.422746e-05 +10 chanx_right_out[8]:4 ropt_net_174:4 7.981685e-06 +11 chanx_right_out[8]:4 ropt_net_174:6 5.592146e-07 +12 chanx_right_out[8]:3 ropt_net_174:7 5.592146e-07 +13 chanx_right_out[8]:3 ropt_net_174:5 7.981685e-06 +14 chanx_right_out[8]:2 ropt_net_174:5 9.470134e-06 + +*RES +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[8]:6 0.152 +1 chanx_right_out[8]:6 chanx_right_out[8]:5 0.01096205 +2 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +3 chanx_right_out[8]:4 chanx_right_out[8]:3 0.001426339 +4 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +5 chanx_right_out[8]:2 chanx_right_out[8] 0.000670925 + +*END + +*D_NET chanx_left_out[12] 0.000458117 //LENGTH 2.865 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 44.880 +*P chanx_left_out[12] O *L 0.7423 *C 1.230 44.880 +*N chanx_left_out[12]:2 *C 3.213 44.880 +*N chanx_left_out[12]:3 *C 3.220 44.880 +*N chanx_left_out[12]:4 *C 3.243 44.880 +*N chanx_left_out[12]:5 *C 3.610 44.880 + +*CAP +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[12] 0.0001685414 +2 chanx_left_out[12]:2 0.0001685414 +3 chanx_left_out[12]:3 3.745738e-05 +4 chanx_left_out[12]:4 4.128845e-05 +5 chanx_left_out[12]:5 4.128845e-05 + +*RES +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[12]:5 0.152 +1 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0001997283 +2 chanx_left_out[12]:4 chanx_left_out[12]:3 0.0045 +3 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +4 chanx_left_out[12]:2 chanx_left_out[12] 0.0003105917 + +*END + +*D_NET mux_tree_tapbuf_size10_11_sram[3] 0.001550622 //LENGTH 12.375 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 18.705 58.820 +*I mem_left_track_25\/FTB_24__75:A I *L 0.001746 *C 11.960 61.200 +*I mux_left_track_25\/mux_l4_in_0_:S I *L 0.00357 *C 14.820 61.495 +*N mux_tree_tapbuf_size10_11_sram[3]:3 *C 14.820 61.495 +*N mux_tree_tapbuf_size10_11_sram[3]:4 *C 11.960 61.200 +*N mux_tree_tapbuf_size10_11_sram[3]:5 *C 11.960 61.540 +*N mux_tree_tapbuf_size10_11_sram[3]:6 *C 13.800 61.540 +*N mux_tree_tapbuf_size10_11_sram[3]:7 *C 13.800 61.880 +*N mux_tree_tapbuf_size10_11_sram[3]:8 *C 14.820 61.880 +*N mux_tree_tapbuf_size10_11_sram[3]:9 *C 16.515 61.880 +*N mux_tree_tapbuf_size10_11_sram[3]:10 *C 16.560 61.835 +*N mux_tree_tapbuf_size10_11_sram[3]:11 *C 16.560 58.865 +*N mux_tree_tapbuf_size10_11_sram[3]:12 *C 16.605 58.820 +*N mux_tree_tapbuf_size10_11_sram[3]:13 *C 18.668 58.820 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_track_25\/FTB_24__75:A 1e-06 +2 mux_left_track_25\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_11_sram[3]:3 5.642731e-05 +4 mux_tree_tapbuf_size10_11_sram[3]:4 5.9574e-05 +5 mux_tree_tapbuf_size10_11_sram[3]:5 0.0001441544 +6 mux_tree_tapbuf_size10_11_sram[3]:6 0.000134048 +7 mux_tree_tapbuf_size10_11_sram[3]:7 9.940684e-05 +8 mux_tree_tapbuf_size10_11_sram[3]:8 0.0002501576 +9 mux_tree_tapbuf_size10_11_sram[3]:9 0.0001405194 +10 mux_tree_tapbuf_size10_11_sram[3]:10 0.0001889263 +11 mux_tree_tapbuf_size10_11_sram[3]:11 0.0001889263 +12 mux_tree_tapbuf_size10_11_sram[3]:12 0.0001427411 +13 mux_tree_tapbuf_size10_11_sram[3]:13 0.0001427411 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_11_sram[3]:13 0.152 +1 mux_tree_tapbuf_size10_11_sram[3]:9 mux_tree_tapbuf_size10_11_sram[3]:8 0.001513393 +2 mux_tree_tapbuf_size10_11_sram[3]:10 mux_tree_tapbuf_size10_11_sram[3]:9 0.0045 +3 mux_tree_tapbuf_size10_11_sram[3]:12 mux_tree_tapbuf_size10_11_sram[3]:11 0.0045 +4 mux_tree_tapbuf_size10_11_sram[3]:11 mux_tree_tapbuf_size10_11_sram[3]:10 0.002651786 +5 mux_tree_tapbuf_size10_11_sram[3]:13 mux_tree_tapbuf_size10_11_sram[3]:12 0.001841518 +6 mux_tree_tapbuf_size10_11_sram[3]:3 mux_left_track_25\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_11_sram[3]:4 mem_left_track_25\/FTB_24__75:A 0.152 +8 mux_tree_tapbuf_size10_11_sram[3]:5 mux_tree_tapbuf_size10_11_sram[3]:4 0.0003035715 +9 mux_tree_tapbuf_size10_11_sram[3]:6 mux_tree_tapbuf_size10_11_sram[3]:5 0.001642857 +10 mux_tree_tapbuf_size10_11_sram[3]:7 mux_tree_tapbuf_size10_11_sram[3]:6 0.0003035715 +11 mux_tree_tapbuf_size10_11_sram[3]:8 mux_tree_tapbuf_size10_11_sram[3]:7 0.0009107143 +12 mux_tree_tapbuf_size10_11_sram[3]:8 mux_tree_tapbuf_size10_11_sram[3]:3 0.0003437501 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[0] 0.008275216 //LENGTH 54.115 LUMPCC 0.003677545 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 124.045 66.640 +*I mux_right_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 103.840 68.680 +*I mux_right_track_8\/mux_l1_in_2_:S I *L 0.00357 *C 102.940 66.640 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 76.720 66.640 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 109.655 66.300 +*N mux_tree_tapbuf_size10_3_sram[0]:5 *C 109.655 66.300 +*N mux_tree_tapbuf_size10_3_sram[0]:6 *C 76.758 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:7 *C 77.740 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:8 *C 77.740 66.300 +*N mux_tree_tapbuf_size10_3_sram[0]:9 *C 96.600 66.300 +*N mux_tree_tapbuf_size10_3_sram[0]:10 *C 96.600 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:11 *C 102.940 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:12 *C 103.840 68.680 +*N mux_tree_tapbuf_size10_3_sram[0]:13 *C 103.960 68.635 +*N mux_tree_tapbuf_size10_3_sram[0]:14 *C 103.960 66.685 +*N mux_tree_tapbuf_size10_3_sram[0]:15 *C 103.960 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:16 *C 105.340 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:17 *C 105.340 65.960 +*N mux_tree_tapbuf_size10_3_sram[0]:18 *C 109.525 65.968 +*N mux_tree_tapbuf_size10_3_sram[0]:19 *C 109.480 66.005 +*N mux_tree_tapbuf_size10_3_sram[0]:20 *C 109.480 66.583 +*N mux_tree_tapbuf_size10_3_sram[0]:21 *C 109.488 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:22 *C 123.733 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:23 *C 123.740 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:24 *C 123.740 66.640 +*N mux_tree_tapbuf_size10_3_sram[0]:25 *C 124.045 66.640 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_8\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_8\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +4 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_3_sram[0]:5 6.563619e-05 +6 mux_tree_tapbuf_size10_3_sram[0]:6 0.000100148 +7 mux_tree_tapbuf_size10_3_sram[0]:7 0.0001220364 +8 mux_tree_tapbuf_size10_3_sram[0]:8 0.0005596236 +9 mux_tree_tapbuf_size10_3_sram[0]:9 0.0005628898 +10 mux_tree_tapbuf_size10_3_sram[0]:10 0.000444644 +11 mux_tree_tapbuf_size10_3_sram[0]:11 0.0005112635 +12 mux_tree_tapbuf_size10_3_sram[0]:12 2.711512e-05 +13 mux_tree_tapbuf_size10_3_sram[0]:13 0.0001329865 +14 mux_tree_tapbuf_size10_3_sram[0]:14 0.0001329865 +15 mux_tree_tapbuf_size10_3_sram[0]:15 0.0001981737 +16 mux_tree_tapbuf_size10_3_sram[0]:16 0.0001423901 +17 mux_tree_tapbuf_size10_3_sram[0]:17 0.0003510412 +18 mux_tree_tapbuf_size10_3_sram[0]:18 0.0003406983 +19 mux_tree_tapbuf_size10_3_sram[0]:19 6.473083e-05 +20 mux_tree_tapbuf_size10_3_sram[0]:20 6.473083e-05 +21 mux_tree_tapbuf_size10_3_sram[0]:21 0.0003224425 +22 mux_tree_tapbuf_size10_3_sram[0]:22 0.0003224425 +23 mux_tree_tapbuf_size10_3_sram[0]:23 3.383893e-05 +24 mux_tree_tapbuf_size10_3_sram[0]:24 4.942245e-05 +25 mux_tree_tapbuf_size10_3_sram[0]:25 4.343125e-05 +26 mux_tree_tapbuf_size10_3_sram[0]:6 chanx_right_in[6]:25 5.898832e-06 +27 mux_tree_tapbuf_size10_3_sram[0]:21 chanx_right_in[6]:29 1.503422e-05 +28 mux_tree_tapbuf_size10_3_sram[0]:22 chanx_right_in[6]:30 1.503422e-05 +29 mux_tree_tapbuf_size10_3_sram[0]:7 chanx_right_in[6]:26 5.898832e-06 +30 mux_tree_tapbuf_size10_3_sram[0]:8 chanx_right_in[6]:25 0.0004468804 +31 mux_tree_tapbuf_size10_3_sram[0]:9 chanx_right_in[6]:26 0.0004468804 +32 mux_tree_tapbuf_size10_3_sram[0]:21 chanx_right_in[18]:31 0.0003623946 +33 mux_tree_tapbuf_size10_3_sram[0]:22 chanx_right_in[18] 0.0003623946 +34 mux_tree_tapbuf_size10_3_sram[0]:7 chany_bottom_in[9]:19 5.391469e-06 +35 mux_tree_tapbuf_size10_3_sram[0]:8 chany_bottom_in[9]:17 0.0005321774 +36 mux_tree_tapbuf_size10_3_sram[0]:8 chany_bottom_in[9]:27 5.391469e-06 +37 mux_tree_tapbuf_size10_3_sram[0]:9 chany_bottom_in[9]:16 0.0005321774 +38 mux_tree_tapbuf_size10_3_sram[0]:21 chanx_left_in[5]:16 0.0002998859 +39 mux_tree_tapbuf_size10_3_sram[0]:22 chanx_left_in[5]:15 0.0002998859 +40 mux_tree_tapbuf_size10_3_sram[0]:8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001711097 +41 mux_tree_tapbuf_size10_3_sram[0]:9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001711097 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_3_sram[0]:25 0.152 +1 mux_tree_tapbuf_size10_3_sram[0]:15 mux_tree_tapbuf_size10_3_sram[0]:14 0.0045 +2 mux_tree_tapbuf_size10_3_sram[0]:15 mux_tree_tapbuf_size10_3_sram[0]:11 0.0009107143 +3 mux_tree_tapbuf_size10_3_sram[0]:14 mux_tree_tapbuf_size10_3_sram[0]:13 0.001741071 +4 mux_tree_tapbuf_size10_3_sram[0]:12 mux_right_track_8\/mux_l1_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_3_sram[0]:13 mux_tree_tapbuf_size10_3_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size10_3_sram[0]:6 mux_right_track_8\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_3_sram[0]:5 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size10_3_sram[0]:18 mux_tree_tapbuf_size10_3_sram[0]:17 0.003736607 +9 mux_tree_tapbuf_size10_3_sram[0]:18 mux_tree_tapbuf_size10_3_sram[0]:5 0.0001807065 +10 mux_tree_tapbuf_size10_3_sram[0]:19 mux_tree_tapbuf_size10_3_sram[0]:18 0.0045 +11 mux_tree_tapbuf_size10_3_sram[0]:20 mux_tree_tapbuf_size10_3_sram[0]:19 0.000515625 +12 mux_tree_tapbuf_size10_3_sram[0]:21 mux_tree_tapbuf_size10_3_sram[0]:20 0.00341 +13 mux_tree_tapbuf_size10_3_sram[0]:23 mux_tree_tapbuf_size10_3_sram[0]:22 0.00341 +14 mux_tree_tapbuf_size10_3_sram[0]:22 mux_tree_tapbuf_size10_3_sram[0]:21 0.002231717 +15 mux_tree_tapbuf_size10_3_sram[0]:24 mux_tree_tapbuf_size10_3_sram[0]:23 0.0045 +16 mux_tree_tapbuf_size10_3_sram[0]:25 mux_tree_tapbuf_size10_3_sram[0]:24 0.0001657609 +17 mux_tree_tapbuf_size10_3_sram[0]:11 mux_right_track_8\/mux_l1_in_2_:S 0.152 +18 mux_tree_tapbuf_size10_3_sram[0]:11 mux_tree_tapbuf_size10_3_sram[0]:10 0.005660715 +19 mux_tree_tapbuf_size10_3_sram[0]:7 mux_tree_tapbuf_size10_3_sram[0]:6 0.0008772322 +20 mux_tree_tapbuf_size10_3_sram[0]:8 mux_tree_tapbuf_size10_3_sram[0]:7 0.0003035715 +21 mux_tree_tapbuf_size10_3_sram[0]:9 mux_tree_tapbuf_size10_3_sram[0]:8 0.01683929 +22 mux_tree_tapbuf_size10_3_sram[0]:10 mux_tree_tapbuf_size10_3_sram[0]:9 0.0003035715 +23 mux_tree_tapbuf_size10_3_sram[0]:16 mux_tree_tapbuf_size10_3_sram[0]:15 0.001232143 +24 mux_tree_tapbuf_size10_3_sram[0]:17 mux_tree_tapbuf_size10_3_sram[0]:16 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[1] 0.006841045 //LENGTH 53.507 LUMPCC 0.0004910951 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 65.165 36.720 +*I mux_bottom_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 48.180 29.240 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 40.655 31.620 +*I mux_bottom_track_17\/mux_l2_in_3_:S I *L 0.00357 *C 47.940 41.870 +*I mux_bottom_track_17\/mux_l2_in_2_:S I *L 0.00357 *C 45.440 41.820 +*I mux_bottom_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 64.500 31.280 +*N mux_tree_tapbuf_size10_7_sram[1]:6 *C 64.500 31.280 +*N mux_tree_tapbuf_size10_7_sram[1]:7 *C 45.477 41.820 +*N mux_tree_tapbuf_size10_7_sram[1]:8 *C 47.940 41.823 +*N mux_tree_tapbuf_size10_7_sram[1]:9 *C 47.865 41.820 +*N mux_tree_tapbuf_size10_7_sram[1]:10 *C 47.940 41.480 +*N mux_tree_tapbuf_size10_7_sram[1]:11 *C 50.095 41.480 +*N mux_tree_tapbuf_size10_7_sram[1]:12 *C 50.140 41.435 +*N mux_tree_tapbuf_size10_7_sram[1]:13 *C 40.655 31.620 +*N mux_tree_tapbuf_size10_7_sram[1]:14 *C 40.480 31.960 +*N mux_tree_tapbuf_size10_7_sram[1]:15 *C 47.335 31.960 +*N mux_tree_tapbuf_size10_7_sram[1]:16 *C 47.380 31.915 +*N mux_tree_tapbuf_size10_7_sram[1]:17 *C 47.380 29.285 +*N mux_tree_tapbuf_size10_7_sram[1]:18 *C 47.425 29.240 +*N mux_tree_tapbuf_size10_7_sram[1]:19 *C 48.180 29.240 +*N mux_tree_tapbuf_size10_7_sram[1]:20 *C 50.045 29.240 +*N mux_tree_tapbuf_size10_7_sram[1]:21 *C 50.140 29.285 +*N mux_tree_tapbuf_size10_7_sram[1]:22 *C 50.140 31.960 +*N mux_tree_tapbuf_size10_7_sram[1]:23 *C 50.185 31.960 +*N mux_tree_tapbuf_size10_7_sram[1]:24 *C 64.400 31.930 +*N mux_tree_tapbuf_size10_7_sram[1]:25 *C 64.400 32.005 +*N mux_tree_tapbuf_size10_7_sram[1]:26 *C 64.400 36.675 +*N mux_tree_tapbuf_size10_7_sram[1]:27 *C 64.445 36.720 +*N mux_tree_tapbuf_size10_7_sram[1]:28 *C 65.127 36.720 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_17\/mux_l2_in_1_:S 1e-06 +2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_17\/mux_l2_in_3_:S 1e-06 +4 mux_bottom_track_17\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_track_17\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_7_sram[1]:6 8.346727e-05 +7 mux_tree_tapbuf_size10_7_sram[1]:7 0.0001811351 +8 mux_tree_tapbuf_size10_7_sram[1]:8 0.0001904285 +9 mux_tree_tapbuf_size10_7_sram[1]:9 3.151617e-05 +10 mux_tree_tapbuf_size10_7_sram[1]:10 0.0001979717 +11 mux_tree_tapbuf_size10_7_sram[1]:11 0.000175749 +12 mux_tree_tapbuf_size10_7_sram[1]:12 0.0004222116 +13 mux_tree_tapbuf_size10_7_sram[1]:13 5.281876e-05 +14 mux_tree_tapbuf_size10_7_sram[1]:14 0.0004978758 +15 mux_tree_tapbuf_size10_7_sram[1]:15 0.0004729684 +16 mux_tree_tapbuf_size10_7_sram[1]:16 0.0001689768 +17 mux_tree_tapbuf_size10_7_sram[1]:17 0.0001689768 +18 mux_tree_tapbuf_size10_7_sram[1]:18 6.227438e-05 +19 mux_tree_tapbuf_size10_7_sram[1]:19 0.0002437168 +20 mux_tree_tapbuf_size10_7_sram[1]:20 0.0001543144 +21 mux_tree_tapbuf_size10_7_sram[1]:21 0.0001318316 +22 mux_tree_tapbuf_size10_7_sram[1]:22 0.0005851259 +23 mux_tree_tapbuf_size10_7_sram[1]:23 0.0008843045 +24 mux_tree_tapbuf_size10_7_sram[1]:24 0.0009365993 +25 mux_tree_tapbuf_size10_7_sram[1]:25 0.0002850851 +26 mux_tree_tapbuf_size10_7_sram[1]:26 0.0002850851 +27 mux_tree_tapbuf_size10_7_sram[1]:27 6.575843e-05 +28 mux_tree_tapbuf_size10_7_sram[1]:28 6.575843e-05 +29 mux_tree_tapbuf_size10_7_sram[1]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.009022e-05 +30 mux_tree_tapbuf_size10_7_sram[1]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.009022e-05 +31 mux_tree_tapbuf_size10_7_sram[1]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.133559e-05 +32 mux_tree_tapbuf_size10_7_sram[1]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.912858e-06 +33 mux_tree_tapbuf_size10_7_sram[1]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.912858e-06 +34 mux_tree_tapbuf_size10_7_sram[1]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.133559e-05 +35 mux_tree_tapbuf_size10_7_sram[1]:24 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.831435e-05 +36 mux_tree_tapbuf_size10_7_sram[1]:23 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.831435e-05 +37 mux_tree_tapbuf_size10_7_sram[1]:24 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.089451e-05 +38 mux_tree_tapbuf_size10_7_sram[1]:23 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.089451e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_7_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_7_sram[1]:19 mux_bottom_track_17\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[1]:19 mux_tree_tapbuf_size10_7_sram[1]:18 0.0006741072 +3 mux_tree_tapbuf_size10_7_sram[1]:20 mux_tree_tapbuf_size10_7_sram[1]:19 0.001665179 +4 mux_tree_tapbuf_size10_7_sram[1]:21 mux_tree_tapbuf_size10_7_sram[1]:20 0.0045 +5 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:23 0.01269196 +6 mux_tree_tapbuf_size10_7_sram[1]:24 mux_tree_tapbuf_size10_7_sram[1]:6 0.0005803572 +7 mux_tree_tapbuf_size10_7_sram[1]:25 mux_tree_tapbuf_size10_7_sram[1]:24 0.0045 +8 mux_tree_tapbuf_size10_7_sram[1]:27 mux_tree_tapbuf_size10_7_sram[1]:26 0.0045 +9 mux_tree_tapbuf_size10_7_sram[1]:26 mux_tree_tapbuf_size10_7_sram[1]:25 0.004169643 +10 mux_tree_tapbuf_size10_7_sram[1]:28 mux_tree_tapbuf_size10_7_sram[1]:27 0.0006093751 +11 mux_tree_tapbuf_size10_7_sram[1]:7 mux_bottom_track_17\/mux_l2_in_2_:S 0.152 +12 mux_tree_tapbuf_size10_7_sram[1]:23 mux_tree_tapbuf_size10_7_sram[1]:22 0.0045 +13 mux_tree_tapbuf_size10_7_sram[1]:22 mux_tree_tapbuf_size10_7_sram[1]:21 0.002388393 +14 mux_tree_tapbuf_size10_7_sram[1]:22 mux_tree_tapbuf_size10_7_sram[1]:12 0.008459821 +15 mux_tree_tapbuf_size10_7_sram[1]:18 mux_tree_tapbuf_size10_7_sram[1]:17 0.0045 +16 mux_tree_tapbuf_size10_7_sram[1]:17 mux_tree_tapbuf_size10_7_sram[1]:16 0.002348215 +17 mux_tree_tapbuf_size10_7_sram[1]:15 mux_tree_tapbuf_size10_7_sram[1]:14 0.006120536 +18 mux_tree_tapbuf_size10_7_sram[1]:16 mux_tree_tapbuf_size10_7_sram[1]:15 0.0045 +19 mux_tree_tapbuf_size10_7_sram[1]:13 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +20 mux_tree_tapbuf_size10_7_sram[1]:8 mux_bottom_track_17\/mux_l2_in_3_:S 0.152 +21 mux_tree_tapbuf_size10_7_sram[1]:8 mux_tree_tapbuf_size10_7_sram[1]:7 0.002198661 +22 mux_tree_tapbuf_size10_7_sram[1]:11 mux_tree_tapbuf_size10_7_sram[1]:10 0.001924107 +23 mux_tree_tapbuf_size10_7_sram[1]:12 mux_tree_tapbuf_size10_7_sram[1]:11 0.0045 +24 mux_tree_tapbuf_size10_7_sram[1]:6 mux_bottom_track_17\/mux_l2_in_0_:S 0.152 +25 mux_tree_tapbuf_size10_7_sram[1]:14 mux_tree_tapbuf_size10_7_sram[1]:13 0.0003035715 +26 mux_tree_tapbuf_size10_7_sram[1]:9 mux_tree_tapbuf_size10_7_sram[1]:8 6.696428e-05 +27 mux_tree_tapbuf_size10_7_sram[1]:10 mux_tree_tapbuf_size10_7_sram[1]:9 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_2_ccff_tail[0] 0.0006016599 //LENGTH 4.100 LUMPCC 0.0001069367 DR + +*CONN +*I mem_top_track_24\/FTB_15__66:X O *L 0 *C 63.245 80.580 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.275 82.620 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 *C 62.275 82.620 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 *C 62.100 82.620 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 *C 62.100 82.575 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 *C 62.100 80.625 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 *C 62.145 80.580 +*N mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 *C 63.208 80.580 + +*CAP +0 mem_top_track_24\/FTB_15__66:X 1e-06 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 5.792405e-05 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 6.232474e-05 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.0001310303 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0001310303 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 5.52069e-05 +7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 5.52069e-05 +8 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size10_2_sram[3]:8 5.346836e-05 +9 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size10_2_sram[3]:7 5.346836e-05 + +*RES +0 mem_top_track_24\/FTB_15__66:X mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:4 0.001741071 +6 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_2_ccff_tail[0]:6 0.0009486608 + +*END + +*D_NET mux_tree_tapbuf_size12_1_sram[3] 0.001678723 //LENGTH 13.260 LUMPCC 0.000130287 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 53.665 110.160 +*I mux_top_track_2\/mux_l4_in_0_:S I *L 0.00357 *C 52.780 112.540 +*I mem_top_track_2\/FTB_2__53:A I *L 0.001746 *C 51.060 118.320 +*N mux_tree_tapbuf_size12_1_sram[3]:3 *C 51.060 118.320 +*N mux_tree_tapbuf_size12_1_sram[3]:4 *C 51.060 117.640 +*N mux_tree_tapbuf_size12_1_sram[3]:5 *C 53.315 117.640 +*N mux_tree_tapbuf_size12_1_sram[3]:6 *C 53.360 117.595 +*N mux_tree_tapbuf_size12_1_sram[3]:7 *C 52.818 112.540 +*N mux_tree_tapbuf_size12_1_sram[3]:8 *C 53.315 112.540 +*N mux_tree_tapbuf_size12_1_sram[3]:9 *C 53.360 112.540 +*N mux_tree_tapbuf_size12_1_sram[3]:10 *C 53.820 112.540 +*N mux_tree_tapbuf_size12_1_sram[3]:11 *C 53.820 110.205 +*N mux_tree_tapbuf_size12_1_sram[3]:12 *C 53.820 110.160 +*N mux_tree_tapbuf_size12_1_sram[3]:13 *C 53.665 110.160 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_top_track_2\/mux_l4_in_0_:S 1e-06 +2 mem_top_track_2\/FTB_2__53:A 1e-06 +3 mux_tree_tapbuf_size12_1_sram[3]:3 7.694033e-05 +4 mux_tree_tapbuf_size12_1_sram[3]:4 0.0002181663 +5 mux_tree_tapbuf_size12_1_sram[3]:5 0.0001710181 +6 mux_tree_tapbuf_size12_1_sram[3]:6 0.0002675322 +7 mux_tree_tapbuf_size12_1_sram[3]:7 3.820035e-05 +8 mux_tree_tapbuf_size12_1_sram[3]:8 3.820035e-05 +9 mux_tree_tapbuf_size12_1_sram[3]:9 0.0002989361 +10 mux_tree_tapbuf_size12_1_sram[3]:10 0.0001744978 +11 mux_tree_tapbuf_size12_1_sram[3]:11 0.0001430939 +12 mux_tree_tapbuf_size12_1_sram[3]:12 6.109034e-05 +13 mux_tree_tapbuf_size12_1_sram[3]:13 5.776073e-05 +14 mux_tree_tapbuf_size12_1_sram[3]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 1.284374e-05 +15 mux_tree_tapbuf_size12_1_sram[3]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 2.744034e-05 +16 mux_tree_tapbuf_size12_1_sram[3]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 1.284374e-05 +17 mux_tree_tapbuf_size12_1_sram[3]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 2.744034e-05 +18 mux_tree_tapbuf_size12_1_sram[3]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 2.485942e-05 +19 mux_tree_tapbuf_size12_1_sram[3]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 2.485942e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_1_sram[3]:13 0.152 +1 mux_tree_tapbuf_size12_1_sram[3]:8 mux_tree_tapbuf_size12_1_sram[3]:7 0.0004441965 +2 mux_tree_tapbuf_size12_1_sram[3]:9 mux_tree_tapbuf_size12_1_sram[3]:8 0.0045 +3 mux_tree_tapbuf_size12_1_sram[3]:9 mux_tree_tapbuf_size12_1_sram[3]:6 0.004513393 +4 mux_tree_tapbuf_size12_1_sram[3]:7 mux_top_track_2\/mux_l4_in_0_:S 0.152 +5 mux_tree_tapbuf_size12_1_sram[3]:3 mem_top_track_2\/FTB_2__53:A 0.152 +6 mux_tree_tapbuf_size12_1_sram[3]:5 mux_tree_tapbuf_size12_1_sram[3]:4 0.002013393 +7 mux_tree_tapbuf_size12_1_sram[3]:6 mux_tree_tapbuf_size12_1_sram[3]:5 0.0045 +8 mux_tree_tapbuf_size12_1_sram[3]:12 mux_tree_tapbuf_size12_1_sram[3]:11 0.0045 +9 mux_tree_tapbuf_size12_1_sram[3]:11 mux_tree_tapbuf_size12_1_sram[3]:10 0.002084821 +10 mux_tree_tapbuf_size12_1_sram[3]:13 mux_tree_tapbuf_size12_1_sram[3]:12 8.423913e-05 +11 mux_tree_tapbuf_size12_1_sram[3]:4 mux_tree_tapbuf_size12_1_sram[3]:3 0.000607143 +12 mux_tree_tapbuf_size12_1_sram[3]:10 mux_tree_tapbuf_size12_1_sram[3]:9 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size12_4_sram[2] 0.002281928 //LENGTH 17.625 LUMPCC 0.0006189398 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 90.005 17.340 +*I mux_bottom_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 88.680 20.400 +*I mux_bottom_track_1\/mux_l3_in_1_:S I *L 0.00357 *C 89.600 25.160 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 84.815 15.300 +*N mux_tree_tapbuf_size12_4_sram[2]:4 *C 84.853 15.300 +*N mux_tree_tapbuf_size12_4_sram[2]:5 *C 86.895 15.300 +*N mux_tree_tapbuf_size12_4_sram[2]:6 *C 86.940 15.345 +*N mux_tree_tapbuf_size12_4_sram[2]:7 *C 86.940 17.295 +*N mux_tree_tapbuf_size12_4_sram[2]:8 *C 86.985 17.340 +*N mux_tree_tapbuf_size12_4_sram[2]:9 *C 89.600 25.160 +*N mux_tree_tapbuf_size12_4_sram[2]:10 *C 89.700 25.115 +*N mux_tree_tapbuf_size12_4_sram[2]:11 *C 88.718 20.400 +*N mux_tree_tapbuf_size12_4_sram[2]:12 *C 89.655 20.400 +*N mux_tree_tapbuf_size12_4_sram[2]:13 *C 89.700 20.400 +*N mux_tree_tapbuf_size12_4_sram[2]:14 *C 89.700 17.385 +*N mux_tree_tapbuf_size12_4_sram[2]:15 *C 89.655 17.340 +*N mux_tree_tapbuf_size12_4_sram[2]:16 *C 90.005 17.340 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_track_1\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size12_4_sram[2]:4 0.0001471115 +5 mux_tree_tapbuf_size12_4_sram[2]:5 0.0001471115 +6 mux_tree_tapbuf_size12_4_sram[2]:6 0.0001241683 +7 mux_tree_tapbuf_size12_4_sram[2]:7 0.0001241683 +8 mux_tree_tapbuf_size12_4_sram[2]:8 0.0001906058 +9 mux_tree_tapbuf_size12_4_sram[2]:9 2.82792e-05 +10 mux_tree_tapbuf_size12_4_sram[2]:10 0.0001157479 +11 mux_tree_tapbuf_size12_4_sram[2]:11 8.913896e-05 +12 mux_tree_tapbuf_size12_4_sram[2]:12 8.913896e-05 +13 mux_tree_tapbuf_size12_4_sram[2]:13 0.0002476608 +14 mux_tree_tapbuf_size12_4_sram[2]:14 0.0001004929 +15 mux_tree_tapbuf_size12_4_sram[2]:15 0.0002088083 +16 mux_tree_tapbuf_size12_4_sram[2]:16 4.655579e-05 +17 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 6.577879e-05 +18 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 3.724832e-05 +19 mux_tree_tapbuf_size12_4_sram[2]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 3.724832e-05 +20 mux_tree_tapbuf_size12_4_sram[2]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 6.577879e-05 +21 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.77949e-06 +22 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.80975e-08 +23 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.292678e-07 +24 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000129063 +25 mux_tree_tapbuf_size12_4_sram[2]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.292678e-07 +26 mux_tree_tapbuf_size12_4_sram[2]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.77949e-06 +27 mux_tree_tapbuf_size12_4_sram[2]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000129063 +28 mux_tree_tapbuf_size12_4_sram[2]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.80975e-08 +29 mux_tree_tapbuf_size12_4_sram[2]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.123565e-06 +30 mux_tree_tapbuf_size12_4_sram[2]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.123565e-06 +31 mux_tree_tapbuf_size12_4_sram[2]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 6.885205e-05 +32 mux_tree_tapbuf_size12_4_sram[2]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.477254e-06 +33 mux_tree_tapbuf_size12_4_sram[2]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.477254e-06 +34 mux_tree_tapbuf_size12_4_sram[2]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.885205e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_4_sram[2]:16 0.152 +1 mux_tree_tapbuf_size12_4_sram[2]:11 mux_bottom_track_1\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_4_sram[2]:12 mux_tree_tapbuf_size12_4_sram[2]:11 0.0008370536 +3 mux_tree_tapbuf_size12_4_sram[2]:13 mux_tree_tapbuf_size12_4_sram[2]:12 0.0045 +4 mux_tree_tapbuf_size12_4_sram[2]:13 mux_tree_tapbuf_size12_4_sram[2]:10 0.004209822 +5 mux_tree_tapbuf_size12_4_sram[2]:8 mux_tree_tapbuf_size12_4_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size12_4_sram[2]:7 mux_tree_tapbuf_size12_4_sram[2]:6 0.001741072 +7 mux_tree_tapbuf_size12_4_sram[2]:5 mux_tree_tapbuf_size12_4_sram[2]:4 0.001823661 +8 mux_tree_tapbuf_size12_4_sram[2]:6 mux_tree_tapbuf_size12_4_sram[2]:5 0.0045 +9 mux_tree_tapbuf_size12_4_sram[2]:4 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size12_4_sram[2]:15 mux_tree_tapbuf_size12_4_sram[2]:14 0.0045 +11 mux_tree_tapbuf_size12_4_sram[2]:15 mux_tree_tapbuf_size12_4_sram[2]:8 0.002383929 +12 mux_tree_tapbuf_size12_4_sram[2]:14 mux_tree_tapbuf_size12_4_sram[2]:13 0.002691964 +13 mux_tree_tapbuf_size12_4_sram[2]:9 mux_bottom_track_1\/mux_l3_in_1_:S 0.152 +14 mux_tree_tapbuf_size12_4_sram[2]:10 mux_tree_tapbuf_size12_4_sram[2]:9 0.0045 +15 mux_tree_tapbuf_size12_4_sram[2]:16 mux_tree_tapbuf_size12_4_sram[2]:15 0.0001902174 + +*END + +*D_NET mux_tree_tapbuf_size12_7_sram[1] 0.009325911 //LENGTH 57.130 LUMPCC 0.002650843 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 32.505 93.840 +*I mux_left_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 55.300 95.880 +*I mux_left_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 61.280 99.280 +*I mux_left_track_3\/mux_l2_in_3_:S I *L 0.00357 *C 19.220 99.960 +*I mux_left_track_3\/mux_l2_in_2_:S I *L 0.00357 *C 23.360 99.575 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 34.215 96.900 +*N mux_tree_tapbuf_size12_7_sram[1]:6 *C 34.178 96.900 +*N mux_tree_tapbuf_size12_7_sram[1]:7 *C 23.360 99.575 +*N mux_tree_tapbuf_size12_7_sram[1]:8 *C 19.258 99.960 +*N mux_tree_tapbuf_size12_7_sram[1]:9 *C 23.360 99.960 +*N mux_tree_tapbuf_size12_7_sram[1]:10 *C 27.095 99.960 +*N mux_tree_tapbuf_size12_7_sram[1]:11 *C 27.140 99.915 +*N mux_tree_tapbuf_size12_7_sram[1]:12 *C 27.140 97.285 +*N mux_tree_tapbuf_size12_7_sram[1]:13 *C 27.185 97.240 +*N mux_tree_tapbuf_size12_7_sram[1]:14 *C 33.580 97.240 +*N mux_tree_tapbuf_size12_7_sram[1]:15 *C 33.580 96.900 +*N mux_tree_tapbuf_size12_7_sram[1]:16 *C 33.580 96.855 +*N mux_tree_tapbuf_size12_7_sram[1]:17 *C 61.242 99.280 +*N mux_tree_tapbuf_size12_7_sram[1]:18 *C 58.465 99.280 +*N mux_tree_tapbuf_size12_7_sram[1]:19 *C 58.420 99.235 +*N mux_tree_tapbuf_size12_7_sram[1]:20 *C 58.420 96.605 +*N mux_tree_tapbuf_size12_7_sram[1]:21 *C 58.375 96.560 +*N mux_tree_tapbuf_size12_7_sram[1]:22 *C 55.375 96.560 +*N mux_tree_tapbuf_size12_7_sram[1]:23 *C 55.320 96.560 +*N mux_tree_tapbuf_size12_7_sram[1]:24 *C 55.200 95.880 +*N mux_tree_tapbuf_size12_7_sram[1]:25 *C 55.200 95.880 +*N mux_tree_tapbuf_size12_7_sram[1]:26 *C 55.193 95.880 +*N mux_tree_tapbuf_size12_7_sram[1]:27 *C 33.587 95.880 +*N mux_tree_tapbuf_size12_7_sram[1]:28 *C 33.580 95.880 +*N mux_tree_tapbuf_size12_7_sram[1]:29 *C 33.580 93.885 +*N mux_tree_tapbuf_size12_7_sram[1]:30 *C 33.535 93.840 +*N mux_tree_tapbuf_size12_7_sram[1]:31 *C 32.543 93.840 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:S 1e-06 +2 mux_left_track_3\/mux_l2_in_0_:S 1e-06 +3 mux_left_track_3\/mux_l2_in_3_:S 1e-06 +4 mux_left_track_3\/mux_l2_in_2_:S 1e-06 +5 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size12_7_sram[1]:6 6.479732e-05 +7 mux_tree_tapbuf_size12_7_sram[1]:7 5.404886e-05 +8 mux_tree_tapbuf_size12_7_sram[1]:8 0.0003189111 +9 mux_tree_tapbuf_size12_7_sram[1]:9 0.0005602912 +10 mux_tree_tapbuf_size12_7_sram[1]:10 0.000213495 +11 mux_tree_tapbuf_size12_7_sram[1]:11 0.0001604799 +12 mux_tree_tapbuf_size12_7_sram[1]:12 0.0001604799 +13 mux_tree_tapbuf_size12_7_sram[1]:13 0.0004295056 +14 mux_tree_tapbuf_size12_7_sram[1]:14 0.0004610556 +15 mux_tree_tapbuf_size12_7_sram[1]:15 9.634739e-05 +16 mux_tree_tapbuf_size12_7_sram[1]:16 7.319311e-05 +17 mux_tree_tapbuf_size12_7_sram[1]:17 0.0001967956 +18 mux_tree_tapbuf_size12_7_sram[1]:18 0.0001967956 +19 mux_tree_tapbuf_size12_7_sram[1]:19 0.0002013828 +20 mux_tree_tapbuf_size12_7_sram[1]:20 0.0002013828 +21 mux_tree_tapbuf_size12_7_sram[1]:21 0.0002253285 +22 mux_tree_tapbuf_size12_7_sram[1]:22 0.0002353316 +23 mux_tree_tapbuf_size12_7_sram[1]:23 5.691403e-05 +24 mux_tree_tapbuf_size12_7_sram[1]:24 8.035105e-05 +25 mux_tree_tapbuf_size12_7_sram[1]:25 4.210176e-05 +26 mux_tree_tapbuf_size12_7_sram[1]:26 0.001059417 +27 mux_tree_tapbuf_size12_7_sram[1]:27 0.001059417 +28 mux_tree_tapbuf_size12_7_sram[1]:28 0.0002449554 +29 mux_tree_tapbuf_size12_7_sram[1]:29 0.0001335216 +30 mux_tree_tapbuf_size12_7_sram[1]:30 7.13843e-05 +31 mux_tree_tapbuf_size12_7_sram[1]:31 7.13843e-05 +32 mux_tree_tapbuf_size12_7_sram[1]:27 chanx_right_in[12]:10 0.00118794 +33 mux_tree_tapbuf_size12_7_sram[1]:26 chanx_right_in[12]:11 0.00118794 +34 mux_tree_tapbuf_size12_7_sram[1]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 1.045039e-07 +35 mux_tree_tapbuf_size12_7_sram[1]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.114774e-05 +36 mux_tree_tapbuf_size12_7_sram[1]:28 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 1.045039e-07 +37 mux_tree_tapbuf_size12_7_sram[1]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 5.114774e-05 +38 mux_tree_tapbuf_size12_7_sram[1]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 8.622924e-05 +39 mux_tree_tapbuf_size12_7_sram[1]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.622924e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_7_sram[1]:31 0.152 +1 mux_tree_tapbuf_size12_7_sram[1]:24 mux_left_track_3\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size12_7_sram[1]:24 mux_tree_tapbuf_size12_7_sram[1]:23 0.000607143 +3 mux_tree_tapbuf_size12_7_sram[1]:8 mux_left_track_3\/mux_l2_in_3_:S 0.152 +4 mux_tree_tapbuf_size12_7_sram[1]:15 mux_tree_tapbuf_size12_7_sram[1]:14 0.0003035715 +5 mux_tree_tapbuf_size12_7_sram[1]:15 mux_tree_tapbuf_size12_7_sram[1]:6 0.0005334821 +6 mux_tree_tapbuf_size12_7_sram[1]:16 mux_tree_tapbuf_size12_7_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size12_7_sram[1]:17 mux_left_track_3\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_7_sram[1]:18 mux_tree_tapbuf_size12_7_sram[1]:17 0.002479911 +9 mux_tree_tapbuf_size12_7_sram[1]:19 mux_tree_tapbuf_size12_7_sram[1]:18 0.0045 +10 mux_tree_tapbuf_size12_7_sram[1]:21 mux_tree_tapbuf_size12_7_sram[1]:20 0.0045 +11 mux_tree_tapbuf_size12_7_sram[1]:20 mux_tree_tapbuf_size12_7_sram[1]:19 0.002348214 +12 mux_tree_tapbuf_size12_7_sram[1]:6 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size12_7_sram[1]:30 mux_tree_tapbuf_size12_7_sram[1]:29 0.0045 +14 mux_tree_tapbuf_size12_7_sram[1]:29 mux_tree_tapbuf_size12_7_sram[1]:28 0.00178125 +15 mux_tree_tapbuf_size12_7_sram[1]:31 mux_tree_tapbuf_size12_7_sram[1]:30 0.0008861608 +16 mux_tree_tapbuf_size12_7_sram[1]:7 mux_left_track_3\/mux_l2_in_2_:S 0.152 +17 mux_tree_tapbuf_size12_7_sram[1]:10 mux_tree_tapbuf_size12_7_sram[1]:9 0.003334821 +18 mux_tree_tapbuf_size12_7_sram[1]:11 mux_tree_tapbuf_size12_7_sram[1]:10 0.0045 +19 mux_tree_tapbuf_size12_7_sram[1]:13 mux_tree_tapbuf_size12_7_sram[1]:12 0.0045 +20 mux_tree_tapbuf_size12_7_sram[1]:12 mux_tree_tapbuf_size12_7_sram[1]:11 0.002348214 +21 mux_tree_tapbuf_size12_7_sram[1]:28 mux_tree_tapbuf_size12_7_sram[1]:27 0.00341 +22 mux_tree_tapbuf_size12_7_sram[1]:28 mux_tree_tapbuf_size12_7_sram[1]:16 0.0008705358 +23 mux_tree_tapbuf_size12_7_sram[1]:27 mux_tree_tapbuf_size12_7_sram[1]:26 0.003384783 +24 mux_tree_tapbuf_size12_7_sram[1]:25 mux_tree_tapbuf_size12_7_sram[1]:24 0.0045 +25 mux_tree_tapbuf_size12_7_sram[1]:26 mux_tree_tapbuf_size12_7_sram[1]:25 0.00341 +26 mux_tree_tapbuf_size12_7_sram[1]:9 mux_tree_tapbuf_size12_7_sram[1]:8 0.003662947 +27 mux_tree_tapbuf_size12_7_sram[1]:9 mux_tree_tapbuf_size12_7_sram[1]:7 0.00034375 +28 mux_tree_tapbuf_size12_7_sram[1]:14 mux_tree_tapbuf_size12_7_sram[1]:13 0.005709821 +29 mux_tree_tapbuf_size12_7_sram[1]:23 mux_tree_tapbuf_size12_7_sram[1]:22 4.910714e-05 +30 mux_tree_tapbuf_size12_7_sram[1]:22 mux_tree_tapbuf_size12_7_sram[1]:21 0.002678572 + +*END + +*D_NET mux_tree_tapbuf_size16_2_sram[0] 0.003273217 //LENGTH 24.330 LUMPCC 0.0006830362 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 51.365 9.520 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.975 9.860 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 53.020 14.280 +*N mux_tree_tapbuf_size16_2_sram[0]:3 *C 52.983 14.280 +*N mux_tree_tapbuf_size16_2_sram[0]:4 *C 52.075 14.280 +*N mux_tree_tapbuf_size16_2_sram[0]:5 *C 51.980 14.235 +*N mux_tree_tapbuf_size16_2_sram[0]:6 *C 37.013 9.860 +*N mux_tree_tapbuf_size16_2_sram[0]:7 *C 39.515 9.860 +*N mux_tree_tapbuf_size16_2_sram[0]:8 *C 39.560 9.860 +*N mux_tree_tapbuf_size16_2_sram[0]:9 *C 39.560 10.200 +*N mux_tree_tapbuf_size16_2_sram[0]:10 *C 39.568 10.200 +*N mux_tree_tapbuf_size16_2_sram[0]:11 *C 51.973 10.200 +*N mux_tree_tapbuf_size16_2_sram[0]:12 *C 51.980 10.200 +*N mux_tree_tapbuf_size16_2_sram[0]:13 *C 51.980 10.200 +*N mux_tree_tapbuf_size16_2_sram[0]:14 *C 51.980 9.860 +*N mux_tree_tapbuf_size16_2_sram[0]:15 *C 51.060 9.860 +*N mux_tree_tapbuf_size16_2_sram[0]:16 *C 51.060 9.555 +*N mux_tree_tapbuf_size16_2_sram[0]:17 *C 51.338 9.543 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size16_2_sram[0]:3 0.0001035686 +4 mux_tree_tapbuf_size16_2_sram[0]:4 0.0001035686 +5 mux_tree_tapbuf_size16_2_sram[0]:5 0.0002284633 +6 mux_tree_tapbuf_size16_2_sram[0]:6 0.0001726353 +7 mux_tree_tapbuf_size16_2_sram[0]:7 0.0001726353 +8 mux_tree_tapbuf_size16_2_sram[0]:8 5.335124e-05 +9 mux_tree_tapbuf_size16_2_sram[0]:9 5.747959e-05 +10 mux_tree_tapbuf_size16_2_sram[0]:10 0.0005657376 +11 mux_tree_tapbuf_size16_2_sram[0]:11 0.0005657376 +12 mux_tree_tapbuf_size16_2_sram[0]:12 0.0002596955 +13 mux_tree_tapbuf_size16_2_sram[0]:13 6.049917e-05 +14 mux_tree_tapbuf_size16_2_sram[0]:14 9.926262e-05 +15 mux_tree_tapbuf_size16_2_sram[0]:15 9.582544e-05 +16 mux_tree_tapbuf_size16_2_sram[0]:16 3.665498e-05 +17 mux_tree_tapbuf_size16_2_sram[0]:17 1.206651e-05 +18 mux_tree_tapbuf_size16_2_sram[0]:5 prog_clk[0]:359 1.11214e-07 +19 mux_tree_tapbuf_size16_2_sram[0]:12 prog_clk[0]:355 1.11214e-07 +20 mux_tree_tapbuf_size16_2_sram[0]:11 prog_clk[0]:388 0.0001415159 +21 mux_tree_tapbuf_size16_2_sram[0]:9 prog_clk[0]:390 2.040874e-07 +22 mux_tree_tapbuf_size16_2_sram[0]:10 prog_clk[0]:389 0.0001415159 +23 mux_tree_tapbuf_size16_2_sram[0]:7 prog_clk[0]:394 3.856126e-05 +24 mux_tree_tapbuf_size16_2_sram[0]:8 prog_clk[0]:395 2.040874e-07 +25 mux_tree_tapbuf_size16_2_sram[0]:6 prog_clk[0]:393 3.856126e-05 +26 mux_tree_tapbuf_size16_2_sram[0]:11 bottom_left_grid_pin_39_[0]:11 0.0001601572 +27 mux_tree_tapbuf_size16_2_sram[0]:9 bottom_left_grid_pin_39_[0]:14 9.685024e-07 +28 mux_tree_tapbuf_size16_2_sram[0]:10 bottom_left_grid_pin_39_[0]:16 0.0001601572 +29 mux_tree_tapbuf_size16_2_sram[0]:8 bottom_left_grid_pin_39_[0]:15 9.685024e-07 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size16_2_sram[0]:17 0.152 +1 mux_tree_tapbuf_size16_2_sram[0]:4 mux_tree_tapbuf_size16_2_sram[0]:3 0.0008102679 +2 mux_tree_tapbuf_size16_2_sram[0]:5 mux_tree_tapbuf_size16_2_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size16_2_sram[0]:3 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size16_2_sram[0]:17 mux_tree_tapbuf_size16_2_sram[0]:16 0.0001875 +5 mux_tree_tapbuf_size16_2_sram[0]:13 mux_tree_tapbuf_size16_2_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size16_2_sram[0]:12 mux_tree_tapbuf_size16_2_sram[0]:11 0.00341 +7 mux_tree_tapbuf_size16_2_sram[0]:12 mux_tree_tapbuf_size16_2_sram[0]:5 0.003602679 +8 mux_tree_tapbuf_size16_2_sram[0]:11 mux_tree_tapbuf_size16_2_sram[0]:10 0.00194345 +9 mux_tree_tapbuf_size16_2_sram[0]:9 mux_tree_tapbuf_size16_2_sram[0]:8 0.0001634615 +10 mux_tree_tapbuf_size16_2_sram[0]:10 mux_tree_tapbuf_size16_2_sram[0]:9 0.00341 +11 mux_tree_tapbuf_size16_2_sram[0]:7 mux_tree_tapbuf_size16_2_sram[0]:6 0.002234375 +12 mux_tree_tapbuf_size16_2_sram[0]:8 mux_tree_tapbuf_size16_2_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size16_2_sram[0]:6 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size16_2_sram[0]:16 mux_tree_tapbuf_size16_2_sram[0]:15 0.0002723215 +15 mux_tree_tapbuf_size16_2_sram[0]:15 mux_tree_tapbuf_size16_2_sram[0]:14 0.0008214285 +16 mux_tree_tapbuf_size16_2_sram[0]:14 mux_tree_tapbuf_size16_2_sram[0]:13 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size16_mem_3_ccff_tail[0] 0.001077458 //LENGTH 8.890 LUMPCC 0.00017862 DR + +*CONN +*I mem_left_track_5\/FTB_12__63:X O *L 0 *C 10.805 82.620 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 13.045 77.180 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:2 *C 13.008 77.180 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:3 *C 12.465 77.180 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:4 *C 12.420 77.225 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 *C 12.420 81.260 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 *C 11.500 81.260 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 *C 11.500 82.575 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 *C 11.455 82.620 +*N mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 *C 10.843 82.620 + +*CAP +0 mem_left_track_5\/FTB_12__63:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:2 7.068127e-05 +3 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:3 7.068127e-05 +4 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:4 0.0002420677 +5 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 0.0002815482 +6 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 0.0001153525 +7 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 7.587203e-05 +8 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 2.031763e-05 +9 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 2.031763e-05 +10 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 chanx_right_in[2]:14 2.956558e-05 +11 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 chanx_right_in[2]:13 2.956558e-05 +12 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 chanx_right_in[2]:13 1.482116e-05 +13 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 chanx_right_in[2]:14 1.482116e-05 +14 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 chanx_right_in[16]:12 3.695698e-05 +15 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 chanx_right_in[16]:13 7.966294e-06 +16 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 chanx_right_in[16]:11 3.695698e-05 +17 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 chanx_right_in[16]:14 7.966294e-06 + +*RES +0 mem_left_track_5\/FTB_12__63:X mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:2 0.0004843751 +3 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 0.0045 +5 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 0.001174107 +6 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 0.000546875 +7 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 0.0008214285 +8 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:4 0.003602679 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[0] 0.004933431 //LENGTH 39.620 LUMPCC 0.0002350944 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 26.985 44.540 +*I mux_bottom_track_33\/mux_l1_in_3_:S I *L 0.00357 *C 22.200 52.700 +*I mux_bottom_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 24.480 53.040 +*I mux_bottom_track_33\/mux_l1_in_2_:S I *L 0.00357 *C 25.420 39.780 +*I mux_bottom_track_33\/mux_l1_in_1_:S I *L 0.00357 *C 24.940 34.680 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 13.975 37.060 +*N mux_tree_tapbuf_size7_2_sram[0]:6 *C 14.013 37.060 +*N mux_tree_tapbuf_size7_2_sram[0]:7 *C 14.675 37.060 +*N mux_tree_tapbuf_size7_2_sram[0]:8 *C 14.720 37.015 +*N mux_tree_tapbuf_size7_2_sram[0]:9 *C 14.720 34.725 +*N mux_tree_tapbuf_size7_2_sram[0]:10 *C 14.765 34.680 +*N mux_tree_tapbuf_size7_2_sram[0]:11 *C 24.853 34.680 +*N mux_tree_tapbuf_size7_2_sram[0]:12 *C 24.840 34.725 +*N mux_tree_tapbuf_size7_2_sram[0]:13 *C 25.383 39.780 +*N mux_tree_tapbuf_size7_2_sram[0]:14 *C 24.885 39.780 +*N mux_tree_tapbuf_size7_2_sram[0]:15 *C 24.840 39.780 +*N mux_tree_tapbuf_size7_2_sram[0]:16 *C 24.480 53.040 +*N mux_tree_tapbuf_size7_2_sram[0]:17 *C 22.238 52.700 +*N mux_tree_tapbuf_size7_2_sram[0]:18 *C 24.425 52.708 +*N mux_tree_tapbuf_size7_2_sram[0]:19 *C 24.380 52.655 +*N mux_tree_tapbuf_size7_2_sram[0]:20 *C 24.380 44.540 +*N mux_tree_tapbuf_size7_2_sram[0]:21 *C 24.840 44.495 +*N mux_tree_tapbuf_size7_2_sram[0]:22 *C 24.885 44.540 +*N mux_tree_tapbuf_size7_2_sram[0]:23 *C 26.948 44.540 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_33\/mux_l1_in_3_:S 1e-06 +2 mux_bottom_track_33\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_33\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_track_33\/mux_l1_in_1_:S 1e-06 +5 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_2_sram[0]:6 6.085051e-05 +7 mux_tree_tapbuf_size7_2_sram[0]:7 6.085051e-05 +8 mux_tree_tapbuf_size7_2_sram[0]:8 0.0001461998 +9 mux_tree_tapbuf_size7_2_sram[0]:9 0.0001461998 +10 mux_tree_tapbuf_size7_2_sram[0]:10 0.0006479001 +11 mux_tree_tapbuf_size7_2_sram[0]:11 0.0006479001 +12 mux_tree_tapbuf_size7_2_sram[0]:12 0.000278865 +13 mux_tree_tapbuf_size7_2_sram[0]:13 5.160587e-05 +14 mux_tree_tapbuf_size7_2_sram[0]:14 5.160587e-05 +15 mux_tree_tapbuf_size7_2_sram[0]:15 0.0005533126 +16 mux_tree_tapbuf_size7_2_sram[0]:16 6.171857e-05 +17 mux_tree_tapbuf_size7_2_sram[0]:17 0.0001254516 +18 mux_tree_tapbuf_size7_2_sram[0]:18 0.000159093 +19 mux_tree_tapbuf_size7_2_sram[0]:19 0.0005393692 +20 mux_tree_tapbuf_size7_2_sram[0]:20 0.0005733309 +21 mux_tree_tapbuf_size7_2_sram[0]:21 0.0002784388 +22 mux_tree_tapbuf_size7_2_sram[0]:22 0.0001548221 +23 mux_tree_tapbuf_size7_2_sram[0]:23 0.0001548221 +24 mux_tree_tapbuf_size7_2_sram[0]:17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.45195e-05 +25 mux_tree_tapbuf_size7_2_sram[0]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.384311e-05 +26 mux_tree_tapbuf_size7_2_sram[0]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.230159e-06 +27 mux_tree_tapbuf_size7_2_sram[0]:18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 3.45195e-05 +28 mux_tree_tapbuf_size7_2_sram[0]:19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.934552e-06 +29 mux_tree_tapbuf_size7_2_sram[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.601988e-05 +30 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.601988e-05 +31 mux_tree_tapbuf_size7_2_sram[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.230159e-06 +32 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.384311e-05 +33 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.934552e-06 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_2_sram[0]:23 0.152 +1 mux_tree_tapbuf_size7_2_sram[0]:17 mux_bottom_track_33\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[0]:13 mux_bottom_track_33\/mux_l1_in_2_:S 0.152 +3 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:13 0.0004441965 +4 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:12 0.004513393 +6 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:17 0.001953125 +7 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:16 0.0001807066 +8 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:18 0.0045 +9 mux_tree_tapbuf_size7_2_sram[0]:10 mux_tree_tapbuf_size7_2_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size7_2_sram[0]:9 mux_tree_tapbuf_size7_2_sram[0]:8 0.002044643 +11 mux_tree_tapbuf_size7_2_sram[0]:7 mux_tree_tapbuf_size7_2_sram[0]:6 0.0005915179 +12 mux_tree_tapbuf_size7_2_sram[0]:8 mux_tree_tapbuf_size7_2_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size7_2_sram[0]:6 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_33\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size7_2_sram[0]:11 mux_tree_tapbuf_size7_2_sram[0]:10 0.009006697 +16 mux_tree_tapbuf_size7_2_sram[0]:12 mux_tree_tapbuf_size7_2_sram[0]:11 0.0045 +17 mux_tree_tapbuf_size7_2_sram[0]:22 mux_tree_tapbuf_size7_2_sram[0]:21 0.0045 +18 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:20 0.0004107143 +19 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:15 0.004209822 +20 mux_tree_tapbuf_size7_2_sram[0]:23 mux_tree_tapbuf_size7_2_sram[0]:22 0.001841518 +21 mux_tree_tapbuf_size7_2_sram[0]:16 mux_bottom_track_33\/mux_l1_in_0_:S 0.152 +22 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:19 0.007245536 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001310335 //LENGTH 8.440 LUMPCC 0.0004600353 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_3_:X O *L 0 *C 76.995 97.240 +*I mux_top_track_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 76.995 104.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 76.995 104.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 76.820 104.040 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 76.820 103.995 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 76.820 101.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 77.280 101.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 77.280 97.285 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 77.280 97.240 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 76.995 97.240 + +*CAP +0 mux_top_track_0\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.355731e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.898385e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001372 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001669877 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001600714 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0001302836 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 7.064389e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 7.057226e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size12_0_sram[1]:17 7.111122e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size12_0_sram[1]:20 2.267185e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size12_0_sram[1]:20 7.111122e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size12_0_sram[1]:21 2.267185e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.627288e-05 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001199617 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.627288e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001199617 + +*RES +0 mux_top_track_0\/mux_l2_in_3_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.00390625 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0001548913 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.002084821 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004107143 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002581924 //LENGTH 19.565 LUMPCC 0.0005003188 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 83.085 98.940 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 92.560 107.100 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 92.598 107.100 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 92.920 107.100 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 92.920 106.760 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 89.285 106.760 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 89.240 106.715 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 89.240 98.985 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 89.195 98.940 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 83.123 98.940 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.207264e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.868163e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003012043 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002745953 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003891991 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003891991 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003073269 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003073269 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_bottom_in[2]:26 0.0001630973 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[2]:25 0.0001630973 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 BUF_net_90:4 8.706211e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 BUF_net_90:5 8.706211e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003245536 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.006901786 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.005421875 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002879465 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0] 0.001798169 //LENGTH 12.410 LUMPCC 0.0007172043 DR + +*CONN +*I mux_right_track_2\/mux_l4_in_0_:X O *L 0 *C 122.645 88.060 +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 128.515 82.810 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 128.515 82.810 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 128.340 82.960 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 128.340 83.005 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 128.340 86.983 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 128.333 87.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 123.748 87.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:8 *C 123.740 87.098 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:9 *C 123.740 88.015 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:10 *C 123.695 88.060 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:11 *C 122.683 88.060 + +*CAP +0 mux_right_track_2\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 4.496231e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 4.89548e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002080144 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002080144 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0001024186 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0001024186 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:8 7.458255e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:9 7.458255e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:10 0.0001075083 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:11 0.0001075083 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:153 4.510565e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:152 4.510565e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 prog_clk[0]:154 7.106477e-05 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 prog_clk[0]:158 3.881022e-05 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 prog_clk[0]:158 7.106477e-05 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 prog_clk[0]:159 3.881022e-05 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_tree_tapbuf_size16_1_sram[0]:6 1.403792e-06 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_tree_tapbuf_size16_1_sram[0]:21 1.403792e-06 +20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_tree_tapbuf_size16_1_sram[0]:20 0.0002022177 +21 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_tree_tapbuf_size16_1_sram[0]:19 0.0002022177 + +*RES +0 mux_right_track_2\/mux_l4_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:11 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:2 9.51087e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.003551339 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0007183166 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:9 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.0008191965 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_11_X[0]:10 0.0009040179 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001482798 //LENGTH 12.010 LUMPCC 0.0005316663 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_0_:X O *L 0 *C 89.525 19.720 +*I mux_bottom_track_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 88.685 9.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 88.723 9.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 89.195 9.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 89.240 9.225 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 89.240 19.675 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 89.240 19.720 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 89.525 19.720 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.377936e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 3.377936e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003879524 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0003879524 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.296587e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.270236e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chany_bottom_in[3] 9.788699e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 chany_bottom_in[3]:30 9.788699e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:6 1.477254e-06 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:14 6.885205e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_4_sram[2]:11 5.123565e-06 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:7 1.477254e-06 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:13 6.885205e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size12_4_sram[2]:12 5.123565e-06 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_tree_tapbuf_size12_4_sram[3]:3 2.790246e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size12_4_sram[3]:4 2.790246e-05 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_4_sram[3]:5 3.545043e-05 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_4_sram[3]:8 2.914042e-05 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_4_sram[3]:8 3.545043e-05 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_4_sram[3]:9 2.914042e-05 + +*RES +0 mux_bottom_track_1\/mux_l3_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_1\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.000421875 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.009330358 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001302747 //LENGTH 8.800 LUMPCC 0.0003618959 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_1_:X O *L 0 *C 79.295 82.620 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 74.400 86.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 74.400 86.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 74.520 85.975 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 74.520 82.665 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 74.565 82.620 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 79.258 82.620 + +*CAP +0 mux_left_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.143484e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.443504e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.443504e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003592732 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003592732 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[16]:24 8.735419e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[16]:25 8.735419e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[11]:5 9.359378e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[11]:8 9.359378e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.004189732 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.002955357 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0] 0.00273453 //LENGTH 21.640 LUMPCC 0.0002463879 DR + +*CONN +*I mux_left_track_3\/mux_l4_in_0_:X O *L 0 *C 28.235 96.560 +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.830 99.120 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 9.830 99.120 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 10.535 98.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 10.580 98.895 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 10.580 96.605 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 10.625 96.560 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 28.198 96.560 + +*CAP +0 mux_left_track_3\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 9.384962e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 5.816222e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0001212299 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0001212299 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.001045835 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.001045835 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 left_top_grid_pin_48_[0] 2.740731e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 left_top_grid_pin_48_[0]:18 5.982604e-08 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 left_top_grid_pin_48_[0]:20 4.486677e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 left_top_grid_pin_48_[0]:21 5.086006e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 left_top_grid_pin_48_[0]:17 5.982604e-08 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 left_top_grid_pin_48_[0]:22 2.740731e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 left_top_grid_pin_48_[0]:19 4.486677e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 left_top_grid_pin_48_[0]:20 5.086006e-05 + +*RES +0 mux_left_track_3\/mux_l4_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0006294643 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.002044643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.01568973 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0] 0.001430797 //LENGTH 11.670 LUMPCC 0.0001923047 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_3_:X O *L 0 *C 39.845 94.520 +*I mux_top_track_4\/mux_l4_in_1_:A0 I *L 0.001631 *C 42.955 102.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 42.918 102.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 40.065 102.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 40.020 102.295 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 40.020 94.565 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 40.020 94.520 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 39.845 94.520 + +*CAP +0 mux_top_track_4\/mux_l3_in_3_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_1_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0001955366 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0001955366 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0003665093 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0003665093 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 5.715818e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 5.52421e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_tree_tapbuf_size16_0_sram[1]:29 9.615235e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_tree_tapbuf_size16_0_sram[1]:24 9.615235e-05 + +*RES +0 mux_top_track_4\/mux_l3_in_3_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_top_track_4\/mux_l4_in_1_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.002546875 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.006901787 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0005814981 //LENGTH 4.820 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_1_:X O *L 0 *C 120.345 76.840 +*I mux_right_track_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 122.535 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 122.498 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 121.025 75.140 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 120.980 75.185 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 120.980 76.795 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 120.935 76.840 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 120.383 76.840 + +*CAP +0 mux_right_track_4\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0001099911 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0001099911 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001107929 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001107929 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 6.896506e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 6.896506e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_right_track_4\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.001314732 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0014375 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0007636498 //LENGTH 5.165 LUMPCC 0.0001849749 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_6_:X O *L 0 *C 113.905 74.460 +*I mux_right_track_4\/mux_l3_in_3_:A1 I *L 0.00198 *C 118.780 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 118.743 74.460 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 113.943 74.460 + +*CAP +0 mux_right_track_4\/mux_l2_in_6_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_3_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0002883375 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002883375 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size16_1_sram[1]:36 4.920895e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size16_1_sram[1]:35 4.920895e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size16_1_sram[2]:18 1.372385e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size16_1_sram[2]:20 2.955466e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size16_1_sram[2]:19 1.372385e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size16_1_sram[2]:21 2.955466e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_6_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_4\/mux_l3_in_3_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.004285715 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0] 0.0009756847 //LENGTH 8.625 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l5_in_0_:X O *L 0 *C 47.665 11.560 +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 46.735 4.280 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 *C 46.773 4.373 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 *C 47.335 4.420 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 *C 47.380 4.465 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 *C 47.380 11.515 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 *C 47.380 11.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 *C 47.665 11.560 + +*CAP +0 mux_bottom_track_5\/mux_l5_in_0_:X 1e-06 +1 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 4.843839e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 4.843839e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.0003856135 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0003856135 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 5.358573e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 5.199508e-05 + +*RES +0 mux_bottom_track_5\/mux_l5_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 0.0001548913 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 0.006294644 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 0.0005022322 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_15_X[0]:2 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0] 0.0009996892 //LENGTH 7.080 LUMPCC 0.0002064226 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_3_:X O *L 0 *C 13.055 93.500 +*I mux_left_track_5\/mux_l4_in_1_:A0 I *L 0.001631 *C 14.090 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 14.090 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 13.800 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 13.800 88.105 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 13.800 90.780 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 13.340 90.780 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 13.340 93.455 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:8 *C 13.340 93.500 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:9 *C 13.055 93.500 + +*CAP +0 mux_left_track_5\/mux_l3_in_3_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_1_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 5.309174e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 5.784567e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0001165055 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0001461571 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0001680332 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.0001383816 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:8 5.643082e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:9 5.48212e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 left_top_grid_pin_48_[0]:17 7.785728e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 left_top_grid_pin_48_[0]:18 2.5354e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 left_top_grid_pin_48_[0]:17 2.5354e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 left_top_grid_pin_48_[0]:18 7.785728e-05 + +*RES +0 mux_left_track_5\/mux_l3_in_3_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:9 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_left_track_5\/mux_l4_in_1_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0001576087 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.002388393 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:8 0.0001548913 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0004107143 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.002388393 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001112446 //LENGTH 7.725 LUMPCC 0.0002872181 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_2_:X O *L 0 *C 96.425 53.040 +*I mux_top_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 95.220 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 95.220 47.260 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 95.220 47.600 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 96.095 47.600 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 96.140 47.645 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 96.140 52.995 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 96.140 53.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 96.425 53.040 + +*CAP +0 mux_top_track_8\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.609381e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001038295 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.6187e-05 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000227912 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000227912 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.733232e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.396095e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[12]:23 0.000143609 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[12]:22 0.000143609 + +*RES +0 mux_top_track_8\/mux_l1_in_2_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001548913 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.004776786 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.00078125 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_8\/mux_l2_in_1_:A1 0.152 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000833253 //LENGTH 5.625 LUMPCC 0.0001694192 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_2_:X O *L 0 *C 38.465 50.660 +*I mux_top_track_16\/mux_l3_in_1_:A1 I *L 0.00198 *C 43.800 50.660 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 43.763 50.660 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 38.503 50.660 + +*CAP +0 mux_top_track_16\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003309169 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003309169 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:5 1.886896e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:11 6.584064e-05 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:10 6.584064e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:11 1.886896e-05 + +*RES +0 mux_top_track_16\/mux_l2_in_2_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_16\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.004696429 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005089977 //LENGTH 3.330 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 60.435 69.700 +*I mux_top_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 60.720 72.420 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 60.720 72.420 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 60.720 72.375 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 60.720 69.745 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 60.720 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 60.435 69.700 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.430876e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001751294 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001751294 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.132291e-05 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.110723e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001548913 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A1 0.152 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006702857 //LENGTH 5.165 LUMPCC 7.990214e-05 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 108.845 63.580 +*I mux_right_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 113.720 63.580 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 113.683 63.580 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 108.883 63.580 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002941918 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002941918 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.995107e-05 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.995107e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.004285715 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001374489 //LENGTH 9.300 LUMPCC 0.0004164182 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_1_:X O *L 0 *C 78.835 49.980 +*I mux_right_track_16\/mux_l3_in_0_:A0 I *L 0.001631 *C 80.215 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 80.178 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 76.405 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 76.360 47.985 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 76.360 49.935 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 76.405 49.980 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 78.797 49.980 + +*CAP +0 mux_right_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001662096 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001662096 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.885053e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.885053e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002129753 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002129753 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_left_in[8]:25 5.871877e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[8]:24 5.871877e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_1_sram[0]:22 0.0001494904 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_1_sram[0]:21 0.0001494904 + +*RES +0 mux_right_track_16\/mux_l2_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003368304 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001741071 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002136161 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0] 0.004416345 //LENGTH 36.935 LUMPCC 0.00116339 DR + +*CONN +*I mux_right_track_24\/mux_l4_in_0_:X O *L 0 *C 108.845 77.180 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 128.095 61.010 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 128.095 61.010 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 127.005 60.860 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 126.960 60.905 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 126.960 62.503 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 126.953 62.560 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 109.028 62.560 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 109.020 62.617 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 109.020 77.135 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 109.020 77.180 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 *C 108.845 77.180 + +*CAP +0 mux_right_track_24\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0001064798 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.602033e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001039324 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001039324 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0005602165 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0005602165 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0008193114 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0008193114 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 4.946336e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 5.207089e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 chanx_right_in[18]:31 0.0001717148 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 chanx_right_in[18] 0.0001717148 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size10_4_sram[0]:19 0.0004095896 +15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size10_4_sram[0]:22 3.906208e-07 +16 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size10_4_sram[0]:20 0.0004095896 +17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size10_4_sram[0]:21 3.906208e-07 + +*RES +0 mux_right_track_24\/mux_l4_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 9.51087e-05 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.01296205 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.00341 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00280825 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001426339 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00341 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0009732143 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001438937 //LENGTH 10.930 LUMPCC 0.0004273076 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_1_:X O *L 0 *C 50.885 28.220 +*I mux_bottom_track_17\/mux_l3_in_0_:A0 I *L 0.001631 *C 57.330 31.620 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 57.330 31.620 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 57.500 31.620 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 57.500 31.575 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 57.500 28.265 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 57.455 28.220 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 50.922 28.220 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.421988e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.688681e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001425656 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001425656 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002966957 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002966957 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:321 6.823711e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:322 6.823711e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.675982e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001186569 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.675982e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001186569 + +*RES +0 mux_bottom_track_17\/mux_l2_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002955357 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.005832589 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008965513 //LENGTH 6.550 LUMPCC 9.923864e-05 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_3_:X O *L 0 *C 31.565 49.640 +*I mux_bottom_track_25\/mux_l3_in_1_:A0 I *L 0.001631 *C 32.835 53.720 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 32.835 53.720 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 33.120 53.720 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 33.120 53.675 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 33.120 49.685 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 33.075 49.640 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 31.603 49.640 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.745851e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.207818e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002143213 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002143213 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001235667 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001235667 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:466 8.817686e-06 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:477 4.080163e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:476 8.817686e-06 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:478 4.080163e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_3_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_25\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001548913 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0035625 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0] 0.004083753 //LENGTH 27.165 LUMPCC 0.0009567003 DR + +*CONN +*I mux_left_track_9\/mux_l4_in_0_:X O *L 0 *C 32.375 75.555 +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 8.105 77.390 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 8.143 77.478 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 8.695 77.520 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 8.740 77.475 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 8.740 75.525 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 8.785 75.480 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 32.375 75.555 + +*CAP +0 mux_left_track_9\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.051671e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.051671e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001346791 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001346791 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.001351028 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.001403633 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 left_top_grid_pin_45_[0]:10 0.0001042499 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 left_top_grid_pin_45_[0]:9 0.0001042499 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:13 4.747357e-06 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:16 4.656644e-07 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:17 5.770855e-07 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:18 8.149127e-07 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:20 0.0002009851 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size7_3_sram[0]:21 2.894998e-05 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:6 4.747357e-06 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:15 4.656644e-07 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:16 5.770855e-07 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:17 8.149127e-07 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:19 0.0002009851 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_tree_tapbuf_size7_3_sram[0]:20 2.894998e-05 +22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 optlc_net_150:9 0.0001375601 +23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 optlc_net_150:8 0.0001375601 + +*RES +0 mux_left_track_9\/mux_l4_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004933036 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001741071 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0210625 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009036511 //LENGTH 6.340 LUMPCC 0.0002745026 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_3_:X O *L 0 *C 20.065 66.300 +*I mux_left_track_25\/mux_l3_in_1_:A0 I *L 0.001631 *C 20.070 60.860 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 20.070 60.860 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 20.240 60.860 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 20.240 60.905 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 20.240 66.255 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 20.240 66.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 20.065 66.300 + +*CAP +0 mux_left_track_25\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.38503e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.748288e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001902209 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001902209 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.616104e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.92125e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size12_6_sram[0]:48 6.891922e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size12_6_sram[0]:47 6.891922e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.763306e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.069904e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.763306e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.069904e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_3_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_25\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004776786 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009023013 //LENGTH 6.035 LUMPCC 0.0003529634 DR + +*CONN +*I mux_right_track_32\/mux_l2_in_0_:X O *L 0 *C 96.425 71.740 +*I mux_right_track_32\/mux_l3_in_0_:A1 I *L 0.00198 *C 95.780 66.980 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 95.795 66.980 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 96.118 66.980 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 96.140 67.025 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 96.140 71.695 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 96.140 71.740 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 96.425 71.740 + +*CAP +0 mux_right_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_32\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.744793e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.744793e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001539515 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001539515 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.437477e-05 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.016424e-05 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_top_in[12]:23 0.000130534 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chany_top_in[12]:22 0.000130534 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[18]:17 4.594766e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_left_in[18]:18 4.594766e-05 + +*RES +0 mux_right_track_32\/mux_l2_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004169643 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001752718 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_32\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001007827 //LENGTH 7.700 LUMPCC 0.0001034323 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_1_:X O *L 0 *C 18.575 38.760 +*I mux_bottom_track_33\/mux_l3_in_0_:A0 I *L 0.001631 *C 18.575 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 18.575 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 18.400 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 18.400 32.005 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 18.400 38.715 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 18.400 38.760 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 18.575 38.760 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.717788e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.359619e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003390842 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003390842 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.727197e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.61801e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.171616e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.171616e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_1_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_33\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.510869e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.005991071 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_199 0.001443681 //LENGTH 10.950 LUMPCC 0.0004232384 DR + +*CONN +*I FTB_5__4:X O *L 0 *C 49.220 7.480 +*I ropt_mt_inst_840:A I *L 0.001766 *C 53.360 9.520 +*N ropt_net_199:2 *C 53.398 9.520 +*N ropt_net_199:3 *C 54.235 9.520 +*N ropt_net_199:4 *C 54.280 9.475 +*N ropt_net_199:5 *C 54.280 6.845 +*N ropt_net_199:6 *C 54.235 6.800 +*N ropt_net_199:7 *C 53.405 6.800 +*N ropt_net_199:8 *C 53.360 6.845 +*N ropt_net_199:9 *C 53.360 7.435 +*N ropt_net_199:10 *C 53.315 7.480 +*N ropt_net_199:11 *C 49.258 7.480 + +*CAP +0 FTB_5__4:X 1e-06 +1 ropt_mt_inst_840:A 1e-06 +2 ropt_net_199:2 7.474348e-05 +3 ropt_net_199:3 7.474348e-05 +4 ropt_net_199:4 8.751725e-05 +5 ropt_net_199:5 8.751725e-05 +6 ropt_net_199:6 9.139256e-05 +7 ropt_net_199:7 9.139256e-05 +8 ropt_net_199:8 3.016971e-05 +9 ropt_net_199:9 3.016971e-05 +10 ropt_net_199:10 0.0002253982 +11 ropt_net_199:11 0.0002253982 +12 ropt_net_199:9 chany_top_in[5]:17 2.751185e-06 +13 ropt_net_199:8 chany_top_in[5]:16 2.751185e-06 +14 ropt_net_199:5 chany_top_in[5]:16 7.937794e-05 +15 ropt_net_199:4 chany_top_in[5]:17 7.937794e-05 +16 ropt_net_199:11 chany_top_in[14]:5 2.000198e-05 +17 ropt_net_199:11 chany_top_in[14]:7 7.859178e-05 +18 ropt_net_199:10 chany_top_in[14]:6 2.000198e-05 +19 ropt_net_199:10 chany_top_in[14]:8 7.859178e-05 +20 ropt_net_199:9 chany_top_in[14]:10 1.647102e-05 +21 ropt_net_199:8 chany_top_in[14]:9 1.647102e-05 +22 ropt_net_199:5 chany_top_in[14]:9 1.442529e-05 +23 ropt_net_199:4 chany_top_in[14]:10 1.442529e-05 + +*RES +0 FTB_5__4:X ropt_net_199:11 0.152 +1 ropt_net_199:11 ropt_net_199:10 0.003622768 +2 ropt_net_199:10 ropt_net_199:9 0.0045 +3 ropt_net_199:9 ropt_net_199:8 0.0005267857 +4 ropt_net_199:7 ropt_net_199:6 0.0007410714 +5 ropt_net_199:8 ropt_net_199:7 0.0045 +6 ropt_net_199:6 ropt_net_199:5 0.0045 +7 ropt_net_199:5 ropt_net_199:4 0.002348214 +8 ropt_net_199:3 ropt_net_199:2 0.0007477679 +9 ropt_net_199:4 ropt_net_199:3 0.0045 +10 ropt_net_199:2 ropt_mt_inst_840:A 0.152 + +*END + +*D_NET ropt_net_242 0.000398203 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 135.700 52.360 +*I ropt_mt_inst_896:A I *L 0.001766 *C 134.780 50.320 +*N ropt_net_242:2 *C 134.817 50.320 +*N ropt_net_242:3 *C 135.655 50.320 +*N ropt_net_242:4 *C 135.700 50.365 +*N ropt_net_242:5 *C 135.700 52.315 +*N ropt_net_242:6 *C 135.700 52.360 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 ropt_mt_inst_896:A 1e-06 +2 ropt_net_242:2 6.532163e-05 +3 ropt_net_242:3 6.532163e-05 +4 ropt_net_242:4 0.0001173206 +5 ropt_net_242:5 0.0001173206 +6 ropt_net_242:6 3.091868e-05 + +*RES +0 ropt_mt_inst_794:X ropt_net_242:6 0.152 +1 ropt_net_242:2 ropt_mt_inst_896:A 0.152 +2 ropt_net_242:3 ropt_net_242:2 0.0007477679 +3 ropt_net_242:4 ropt_net_242:3 0.0045 +4 ropt_net_242:6 ropt_net_242:5 0.0045 +5 ropt_net_242:5 ropt_net_242:4 0.001741072 + +*END + +*D_NET chanx_right_out[19] 0.0008247035 //LENGTH 6.170 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 135.700 90.440 +*P chanx_right_out[19] O *L 0.7423 *C 140.375 89.760 +*N chanx_right_out[19]:2 *C 138.007 89.760 +*N chanx_right_out[19]:3 *C 138.000 89.818 +*N chanx_right_out[19]:4 *C 138.000 90.395 +*N chanx_right_out[19]:5 *C 137.955 90.440 +*N chanx_right_out[19]:6 *C 135.738 90.440 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 chanx_right_out[19] 0.0001848442 +2 chanx_right_out[19]:2 0.0001848442 +3 chanx_right_out[19]:3 5.822938e-05 +4 chanx_right_out[19]:4 5.822938e-05 +5 chanx_right_out[19]:5 0.0001687782 +6 chanx_right_out[19]:6 0.0001687782 + +*RES +0 ropt_mt_inst_802:X chanx_right_out[19]:6 0.152 +1 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +2 chanx_right_out[19]:2 chanx_right_out[19] 0.0003709083 +3 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0045 +4 chanx_right_out[19]:4 chanx_right_out[19]:3 0.000515625 +5 chanx_right_out[19]:6 chanx_right_out[19]:5 0.001979911 + +*END + +*D_NET chanx_right_out[7] 0.0007474179 //LENGTH 6.465 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_806:X O *L 0 *C 136.160 36.720 +*P chanx_right_out[7] O *L 0.7423 *C 140.450 35.360 +*N chanx_right_out[7]:2 *C 138.468 35.360 +*N chanx_right_out[7]:3 *C 138.460 35.418 +*N chanx_right_out[7]:4 *C 138.460 36.675 +*N chanx_right_out[7]:5 *C 138.415 36.720 +*N chanx_right_out[7]:6 *C 136.198 36.720 + +*CAP +0 ropt_mt_inst_806:X 1e-06 +1 chanx_right_out[7] 0.0001525557 +2 chanx_right_out[7]:2 0.0001525557 +3 chanx_right_out[7]:3 8.41802e-05 +4 chanx_right_out[7]:4 8.41802e-05 +5 chanx_right_out[7]:5 0.000136473 +6 chanx_right_out[7]:6 0.000136473 + +*RES +0 ropt_mt_inst_806:X chanx_right_out[7]:6 0.152 +1 chanx_right_out[7]:6 chanx_right_out[7]:5 0.001979911 +2 chanx_right_out[7]:5 chanx_right_out[7]:4 0.0045 +3 chanx_right_out[7]:4 chanx_right_out[7]:3 0.001122768 +4 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +5 chanx_right_out[7]:2 chanx_right_out[7] 0.0003105917 + +*END + +*D_NET chanx_right_out[10] 0.0009341719 //LENGTH 7.140 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_811:X O *L 0 *C 133.400 61.200 +*P chanx_right_out[10] O *L 0.7423 *C 140.375 61.200 +*N chanx_right_out[10]:2 *C 133.407 61.200 +*N chanx_right_out[10]:3 *C 133.400 61.200 +*N chanx_right_out[10]:4 *C 133.400 61.200 + +*CAP +0 ropt_mt_inst_811:X 1e-06 +1 chanx_right_out[10] 0.0004345744 +2 chanx_right_out[10]:2 0.0004345744 +3 chanx_right_out[10]:3 3.314373e-05 +4 chanx_right_out[10]:4 3.087936e-05 + +*RES +0 ropt_mt_inst_811:X chanx_right_out[10]:4 0.152 +1 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +2 chanx_right_out[10]:2 chanx_right_out[10] 0.001091575 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.0045 + +*END + +*D_NET ropt_net_233 0.0009812489 //LENGTH 7.775 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_818:X O *L 0 *C 138.655 70.040 +*I ropt_mt_inst_881:A I *L 0.001767 *C 134.780 72.080 +*N ropt_net_233:2 *C 134.817 72.080 +*N ropt_net_233:3 *C 138.920 72.080 +*N ropt_net_233:4 *C 138.920 71.740 +*N ropt_net_233:5 *C 138.920 71.740 +*N ropt_net_233:6 *C 138.460 71.740 +*N ropt_net_233:7 *C 138.460 70.085 +*N ropt_net_233:8 *C 138.460 70.040 +*N ropt_net_233:9 *C 138.655 70.040 + +*CAP +0 ropt_mt_inst_818:X 1e-06 +1 ropt_mt_inst_881:A 1e-06 +2 ropt_net_233:2 0.0002498342 +3 ropt_net_233:3 0.0002724956 +4 ropt_net_233:4 4.79146e-05 +5 ropt_net_233:5 6.112117e-05 +6 ropt_net_233:6 0.0001370095 +7 ropt_net_233:7 0.000104078 +8 ropt_net_233:8 5.076672e-05 +9 ropt_net_233:9 5.602912e-05 + +*RES +0 ropt_mt_inst_818:X ropt_net_233:9 0.152 +1 ropt_net_233:2 ropt_mt_inst_881:A 0.152 +2 ropt_net_233:4 ropt_net_233:3 0.0003035715 +3 ropt_net_233:5 ropt_net_233:4 0.0045 +4 ropt_net_233:8 ropt_net_233:7 0.0045 +5 ropt_net_233:7 ropt_net_233:6 0.001477679 +6 ropt_net_233:9 ropt_net_233:8 0.0001059783 +7 ropt_net_233:3 ropt_net_233:2 0.003662947 +8 ropt_net_233:6 ropt_net_233:5 0.0004107143 + +*END + +*D_NET ropt_net_230 0.00125565 //LENGTH 9.555 LUMPCC 0.0005077394 DR + +*CONN +*I ropt_mt_inst_831:X O *L 0 *C 56.315 6.460 +*I ropt_mt_inst_877:A I *L 0.001767 *C 54.280 4.080 +*N ropt_net_230:2 *C 54.318 4.080 +*N ropt_net_230:3 *C 58.375 4.080 +*N ropt_net_230:4 *C 58.420 4.125 +*N ropt_net_230:5 *C 58.420 6.415 +*N ropt_net_230:6 *C 58.375 6.460 +*N ropt_net_230:7 *C 56.353 6.460 + +*CAP +0 ropt_mt_inst_831:X 1e-06 +1 ropt_mt_inst_877:A 1e-06 +2 ropt_net_230:2 0.000230283 +3 ropt_net_230:3 0.000230283 +4 ropt_net_230:4 8.750253e-05 +5 ropt_net_230:5 8.750253e-05 +6 ropt_net_230:6 5.516982e-05 +7 ropt_net_230:7 5.516982e-05 +8 ropt_net_230:7 chany_top_in[8]:8 8.168253e-05 +9 ropt_net_230:6 chany_top_in[8]:9 8.168253e-05 +10 ropt_net_230:7 chany_bottom_in[18]:47 5.935161e-06 +11 ropt_net_230:6 chany_bottom_in[18]:48 5.935161e-06 +12 ropt_net_230:5 chany_bottom_in[18]:46 1.320909e-06 +13 ropt_net_230:5 chany_bottom_in[18]:48 1.848282e-05 +14 ropt_net_230:3 chany_bottom_in[18]:48 3.132507e-05 +15 ropt_net_230:4 chany_bottom_in[18] 1.848282e-05 +16 ropt_net_230:4 chany_bottom_in[18]:47 1.320909e-06 +17 ropt_net_230:2 chany_bottom_in[18]:47 3.132507e-05 +18 ropt_net_230:7 ropt_net_171:2 4.447683e-05 +19 ropt_net_230:7 ropt_net_171:6 2.475298e-06 +20 ropt_net_230:6 ropt_net_171:3 4.447683e-05 +21 ropt_net_230:6 ropt_net_171:7 2.475298e-06 +22 ropt_net_230:5 chany_bottom_out[17]:2 6.817111e-05 +23 ropt_net_230:4 chany_bottom_out[17] 6.817111e-05 + +*RES +0 ropt_mt_inst_831:X ropt_net_230:7 0.152 +1 ropt_net_230:7 ropt_net_230:6 0.001805804 +2 ropt_net_230:6 ropt_net_230:5 0.0045 +3 ropt_net_230:5 ropt_net_230:4 0.002044643 +4 ropt_net_230:3 ropt_net_230:2 0.003622768 +5 ropt_net_230:4 ropt_net_230:3 0.0045 +6 ropt_net_230:2 ropt_mt_inst_877:A 0.152 + +*END + +*D_NET ropt_net_232 0.00156783 //LENGTH 11.145 LUMPCC 0.0007453198 DR + +*CONN +*I BUFT_P_134:X O *L 0 *C 3.025 83.640 +*I ropt_mt_inst_880:A I *L 0.001766 *C 3.220 91.120 +*N ropt_net_232:2 *C 3.183 91.120 +*N ropt_net_232:3 *C 2.805 91.120 +*N ropt_net_232:4 *C 2.760 91.075 +*N ropt_net_232:5 *C 2.760 86.418 +*N ropt_net_232:6 *C 2.768 86.360 +*N ropt_net_232:7 *C 3.673 86.360 +*N ropt_net_232:8 *C 3.680 86.303 +*N ropt_net_232:9 *C 3.680 83.685 +*N ropt_net_232:10 *C 3.635 83.640 +*N ropt_net_232:11 *C 3.062 83.640 + +*CAP +0 BUFT_P_134:X 1e-06 +1 ropt_mt_inst_880:A 1e-06 +2 ropt_net_232:2 4.608578e-05 +3 ropt_net_232:3 4.608578e-05 +4 ropt_net_232:4 0.0001681552 +5 ropt_net_232:5 0.0001681552 +6 ropt_net_232:6 8.344861e-06 +7 ropt_net_232:7 8.344854e-06 +8 ropt_net_232:8 0.000115756 +9 ropt_net_232:9 0.000115756 +10 ropt_net_232:10 7.191296e-05 +11 ropt_net_232:11 7.191296e-05 +12 ropt_net_232:6 chanx_left_in[4] 7.624023e-05 +13 ropt_net_232:6 chanx_left_in[4]:47 5.255086e-07 +14 ropt_net_232:7 chanx_left_in[4]:46 5.255086e-07 +15 ropt_net_232:7 chanx_left_in[4]:48 7.624023e-05 +16 ropt_net_232:4 chanx_left_in[5]:36 1.182395e-05 +17 ropt_net_232:5 chanx_left_in[5]:37 1.182395e-05 +18 ropt_net_232:6 chanx_left_in[5] 7.170558e-05 +19 ropt_net_232:7 chanx_left_in[5]:37 7.170558e-05 +20 ropt_net_232:4 chanx_left_out[1]:4 0.0001357283 +21 ropt_net_232:5 chanx_left_out[1]:3 0.0001357283 +22 ropt_net_232:8 chanx_left_out[1]:4 7.663626e-05 +23 ropt_net_232:9 chanx_left_out[1]:3 7.663626e-05 + +*RES +0 BUFT_P_134:X ropt_net_232:11 0.152 +1 ropt_net_232:2 ropt_mt_inst_880:A 0.152 +2 ropt_net_232:3 ropt_net_232:2 0.0003370536 +3 ropt_net_232:4 ropt_net_232:3 0.0045 +4 ropt_net_232:5 ropt_net_232:4 0.004158482 +5 ropt_net_232:6 ropt_net_232:5 0.00341 +6 ropt_net_232:8 ropt_net_232:7 0.00341 +7 ropt_net_232:7 ropt_net_232:6 0.0001417833 +8 ropt_net_232:10 ropt_net_232:9 0.0045 +9 ropt_net_232:9 ropt_net_232:8 0.002337053 +10 ropt_net_232:11 ropt_net_232:10 0.0005111608 + +*END + +*D_NET chanx_left_out[14] 0.002319766 //LENGTH 15.390 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_894:X O *L 0 *C 11.695 55.080 +*P chanx_left_out[14] O *L 0.7423 *C 1.230 54.400 +*N chanx_left_out[14]:2 *C 1.820 54.400 +*N chanx_left_out[14]:3 *C 1.840 54.408 +*N chanx_left_out[14]:4 *C 1.840 56.433 +*N chanx_left_out[14]:5 *C 1.860 56.440 +*N chanx_left_out[14]:6 *C 10.572 56.440 +*N chanx_left_out[14]:7 *C 10.580 56.383 +*N chanx_left_out[14]:8 *C 10.580 55.125 +*N chanx_left_out[14]:9 *C 10.625 55.080 +*N chanx_left_out[14]:10 *C 11.658 55.080 + +*CAP +0 ropt_mt_inst_894:X 1e-06 +1 chanx_left_out[14] 8.784557e-05 +2 chanx_left_out[14]:2 8.784557e-05 +3 chanx_left_out[14]:3 0.0001674188 +4 chanx_left_out[14]:4 0.0001674188 +5 chanx_left_out[14]:5 0.0006951545 +6 chanx_left_out[14]:6 0.0006951545 +7 chanx_left_out[14]:7 9.274857e-05 +8 chanx_left_out[14]:8 9.274857e-05 +9 chanx_left_out[14]:9 0.0001162154 +10 chanx_left_out[14]:10 0.0001162154 + +*RES +0 ropt_mt_inst_894:X chanx_left_out[14]:10 0.152 +1 chanx_left_out[14]:10 chanx_left_out[14]:9 0.0009218751 +2 chanx_left_out[14]:9 chanx_left_out[14]:8 0.0045 +3 chanx_left_out[14]:8 chanx_left_out[14]:7 0.001122768 +4 chanx_left_out[14]:7 chanx_left_out[14]:6 0.00341 +5 chanx_left_out[14]:6 chanx_left_out[14]:5 0.001364958 +6 chanx_left_out[14]:5 chanx_left_out[14]:4 0.00341 +7 chanx_left_out[14]:4 chanx_left_out[14]:3 0.00031725 +8 chanx_left_out[14]:2 chanx_left_out[14] 9.243333e-05 +9 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 + +*END + +*D_NET chany_top_in[18] 0.02713549 //LENGTH 159.630 LUMPCC 0.01340207 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 84.640 129.270 +*I mux_left_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.080 58.140 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.430 44.540 +*I FTB_13__12:A I *L 0.001767 *C 73.600 9.520 +*I mux_right_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 86.020 88.740 +*N chany_top_in[18]:5 *C 86.020 88.740 +*N chany_top_in[18]:6 *C 86.020 88.740 +*N chany_top_in[18]:7 *C 86.020 89.080 +*N chany_top_in[18]:8 *C 86.013 89.080 +*N chany_top_in[18]:9 *C 73.638 9.520 +*N chany_top_in[18]:10 *C 74.060 9.520 +*N chany_top_in[18]:11 *C 74.060 9.860 +*N chany_top_in[18]:12 *C 76.315 9.860 +*N chany_top_in[18]:13 *C 76.360 9.905 +*N chany_top_in[18]:14 *C 76.360 39.055 +*N chany_top_in[18]:15 *C 76.315 39.100 +*N chany_top_in[18]:16 *C 74.565 39.100 +*N chany_top_in[18]:17 *C 74.520 39.145 +*N chany_top_in[18]:18 *C 73.468 44.540 +*N chany_top_in[18]:19 *C 74.475 44.540 +*N chany_top_in[18]:20 *C 74.520 44.540 +*N chany_top_in[18]:21 *C 74.520 55.363 +*N chany_top_in[18]:22 *C 74.513 55.420 +*N chany_top_in[18]:23 *C 73.620 55.420 +*N chany_top_in[18]:24 *C 73.600 55.428 +*N chany_top_in[18]:25 *C 68.118 58.140 +*N chany_top_in[18]:26 *C 70.795 58.140 +*N chany_top_in[18]:27 *C 70.840 58.185 +*N chany_top_in[18]:28 *C 70.840 59.103 +*N chany_top_in[18]:29 *C 70.847 59.160 +*N chany_top_in[18]:30 *C 73.580 59.160 +*N chany_top_in[18]:31 *C 73.600 59.160 +*N chany_top_in[18]:32 *C 73.600 89.073 +*N chany_top_in[18]:33 *C 73.620 89.080 +*N chany_top_in[18]:34 *C 75.440 89.080 +*N chany_top_in[18]:35 *C 75.440 89.088 +*N chany_top_in[18]:36 *C 75.440 116.953 +*N chany_top_in[18]:37 *C 75.460 116.960 +*N chany_top_in[18]:38 *C 84.633 116.960 +*N chany_top_in[18]:39 *C 84.640 117.018 + +*CAP +0 chany_top_in[18] 0.0004738019 +1 mux_left_track_25\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +3 FTB_13__12:A 1e-06 +4 mux_right_track_24\/mux_l1_in_1_:A1 1e-06 +5 chany_top_in[18]:5 3.25296e-05 +6 chany_top_in[18]:6 5.435749e-05 +7 chany_top_in[18]:7 5.841465e-05 +8 chany_top_in[18]:8 0.0003938091 +9 chany_top_in[18]:9 4.681122e-05 +10 chany_top_in[18]:10 7.165784e-05 +11 chany_top_in[18]:11 0.0002313182 +12 chany_top_in[18]:12 0.0002064716 +13 chany_top_in[18]:13 0.001768527 +14 chany_top_in[18]:14 0.001768527 +15 chany_top_in[18]:15 0.0001223499 +16 chany_top_in[18]:16 0.0001223499 +17 chany_top_in[18]:17 0.0002314691 +18 chany_top_in[18]:18 8.388384e-05 +19 chany_top_in[18]:19 8.388384e-05 +20 chany_top_in[18]:20 0.0007463268 +21 chany_top_in[18]:21 0.0004819281 +22 chany_top_in[18]:22 0.0001041406 +23 chany_top_in[18]:23 0.0001041406 +24 chany_top_in[18]:24 0.0001534649 +25 chany_top_in[18]:25 0.0001898947 +26 chany_top_in[18]:26 0.0001898947 +27 chany_top_in[18]:27 8.328313e-05 +28 chany_top_in[18]:28 8.328313e-05 +29 chany_top_in[18]:29 0.0003350688 +30 chany_top_in[18]:30 0.0003350688 +31 chany_top_in[18]:31 0.0009966465 +32 chany_top_in[18]:32 0.0008431816 +33 chany_top_in[18]:33 0.0001211189 +34 chany_top_in[18]:34 0.000514928 +35 chany_top_in[18]:35 0.0005010148 +36 chany_top_in[18]:36 0.0005010149 +37 chany_top_in[18]:37 0.000610526 +38 chany_top_in[18]:38 0.000610526 +39 chany_top_in[18]:39 0.0004738019 +40 chany_top_in[18]:24 chany_top_in[13]:20 0.0001732709 +41 chany_top_in[18]:13 chany_top_in[13]:12 1.361272e-07 +42 chany_top_in[18]:14 chany_top_in[13]:13 1.361272e-07 +43 chany_top_in[18]:31 chany_top_in[13]:20 0.0008055625 +44 chany_top_in[18]:31 chany_top_in[13]:21 0.000640966 +45 chany_top_in[18]:32 chany_top_in[13]:21 0.0008055625 +46 chany_top_in[18]:32 chany_top_in[13]:28 0.0004676951 +47 chany_top_in[18]:21 chany_top_in[16]:24 0.0002801951 +48 chany_top_in[18]:20 chany_top_in[16]:15 0.0002801951 +49 chany_top_in[18]:20 chany_top_in[16]:24 0.0001334599 +50 chany_top_in[18]:13 chany_top_in[16]:11 2.197335e-07 +51 chany_top_in[18]:14 chany_top_in[16]:12 2.197335e-07 +52 chany_top_in[18]:17 chany_top_in[16]:15 0.0001334599 +53 chany_top_in[18]:8 chanx_right_in[14]:38 0.0004204595 +54 chany_top_in[18]:34 chanx_right_in[14]:37 0.0004204595 +55 chany_top_in[18] chany_bottom_in[2]:13 0.0003225772 +56 chany_top_in[18]:39 chany_bottom_in[2]:24 0.0003225772 +57 chany_top_in[18]:8 chanx_left_in[13]:17 0.0005558341 +58 chany_top_in[18]:34 chanx_left_in[13]:22 0.0005558341 +59 chany_top_in[18]:34 chanx_left_in[13]:17 0.0001023476 +60 chany_top_in[18]:33 chanx_left_in[13]:22 0.0001023476 +61 chany_top_in[18]:35 chany_top_in[3]:9 0.001225023 +62 chany_top_in[18]:35 chany_top_in[3]:10 1.416665e-05 +63 chany_top_in[18]:36 chany_top_in[3]:11 1.416665e-05 +64 chany_top_in[18]:36 chany_top_in[3]:10 0.001225023 +65 chany_top_in[18]:31 chany_top_in[3]:9 0.0009446891 +66 chany_top_in[18]:32 chany_top_in[3]:10 0.0009446891 +67 chany_top_in[18]:35 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.00123919 +68 chany_top_in[18]:37 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:7 1.620843e-05 +69 chany_top_in[18]:36 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.00123919 +70 chany_top_in[18]:38 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:6 1.620843e-05 + +*RES +0 chany_top_in[18] chany_top_in[18]:39 0.01093973 +1 chany_top_in[18]:7 chany_top_in[18]:6 0.0001634615 +2 chany_top_in[18]:8 chany_top_in[18]:7 0.00341 +3 chany_top_in[18]:5 mux_right_track_24\/mux_l1_in_1_:A1 0.152 +4 chany_top_in[18]:6 chany_top_in[18]:5 0.0045 +5 chany_top_in[18]:23 chany_top_in[18]:22 0.000139825 +6 chany_top_in[18]:24 chany_top_in[18]:23 0.00341 +7 chany_top_in[18]:21 chany_top_in[18]:20 0.009662947 +8 chany_top_in[18]:22 chany_top_in[18]:21 0.00341 +9 chany_top_in[18]:19 chany_top_in[18]:18 0.0008995535 +10 chany_top_in[18]:20 chany_top_in[18]:19 0.0045 +11 chany_top_in[18]:20 chany_top_in[18]:17 0.004816964 +12 chany_top_in[18]:18 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +13 chany_top_in[18]:9 FTB_13__12:A 0.152 +14 chany_top_in[18]:12 chany_top_in[18]:11 0.002013393 +15 chany_top_in[18]:13 chany_top_in[18]:12 0.0045 +16 chany_top_in[18]:15 chany_top_in[18]:14 0.0045 +17 chany_top_in[18]:14 chany_top_in[18]:13 0.02602679 +18 chany_top_in[18]:16 chany_top_in[18]:15 0.0015625 +19 chany_top_in[18]:17 chany_top_in[18]:16 0.0045 +20 chany_top_in[18]:34 chany_top_in[18]:33 0.0002851333 +21 chany_top_in[18]:34 chany_top_in[18]:8 0.001656358 +22 chany_top_in[18]:35 chany_top_in[18]:34 0.00341 +23 chany_top_in[18]:37 chany_top_in[18]:36 0.00341 +24 chany_top_in[18]:36 chany_top_in[18]:35 0.004365516 +25 chany_top_in[18]:39 chany_top_in[18]:38 0.00341 +26 chany_top_in[18]:38 chany_top_in[18]:37 0.001437025 +27 chany_top_in[18]:30 chany_top_in[18]:29 0.0004280917 +28 chany_top_in[18]:31 chany_top_in[18]:30 0.00341 +29 chany_top_in[18]:31 chany_top_in[18]:24 0.0005847583 +30 chany_top_in[18]:28 chany_top_in[18]:27 0.0008191965 +31 chany_top_in[18]:29 chany_top_in[18]:28 0.00341 +32 chany_top_in[18]:26 chany_top_in[18]:25 0.002390625 +33 chany_top_in[18]:27 chany_top_in[18]:26 0.0045 +34 chany_top_in[18]:25 mux_left_track_25\/mux_l1_in_1_:A1 0.152 +35 chany_top_in[18]:33 chany_top_in[18]:32 0.00341 +36 chany_top_in[18]:32 chany_top_in[18]:31 0.004686291 +37 chany_top_in[18]:10 chany_top_in[18]:9 0.0003772322 +38 chany_top_in[18]:11 chany_top_in[18]:10 0.0003035715 + +*END + +*D_NET chanx_right_in[11] 0.01120663 //LENGTH 83.305 LUMPCC 0.004287012 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 140.450 43.520 +*I mux_top_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 91.255 55.080 +*I mux_bottom_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 72.090 42.500 +*N chanx_right_in[11]:3 *C 72.127 42.500 +*N chanx_right_in[11]:4 *C 88.275 42.500 +*N chanx_right_in[11]:5 *C 88.320 42.500 +*N chanx_right_in[11]:6 *C 88.320 42.840 +*N chanx_right_in[11]:7 *C 88.328 42.840 +*N chanx_right_in[11]:8 *C 91.255 55.080 +*N chanx_right_in[11]:9 *C 91.540 55.080 +*N chanx_right_in[11]:10 *C 91.540 55.035 +*N chanx_right_in[11]:11 *C 91.540 42.898 +*N chanx_right_in[11]:12 *C 91.540 42.840 +*N chanx_right_in[11]:13 *C 131.560 42.840 +*N chanx_right_in[11]:14 *C 131.560 43.520 + +*CAP +0 chanx_right_in[11] 0.0004455226 +1 mux_top_track_8\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_1_:A0 1e-06 +3 chanx_right_in[11]:3 0.0007737994 +4 chanx_right_in[11]:4 0.0007737994 +5 chanx_right_in[11]:5 5.036552e-05 +6 chanx_right_in[11]:6 5.417443e-05 +7 chanx_right_in[11]:7 0.000193742 +8 chanx_right_in[11]:8 5.124025e-05 +9 chanx_right_in[11]:9 5.502404e-05 +10 chanx_right_in[11]:10 0.0003248495 +11 chanx_right_in[11]:11 0.0003248495 +12 chanx_right_in[11]:12 0.001765333 +13 chanx_right_in[11]:13 0.001615494 +14 chanx_right_in[11]:14 0.0004894248 +15 chanx_right_in[11]:11 chanx_right_in[6]:8 0.0003201596 +16 chanx_right_in[11]:9 chanx_right_in[6]:5 1.59195e-06 +17 chanx_right_in[11]:10 chanx_right_in[6]:9 0.0003201596 +18 chanx_right_in[11]:8 chanx_right_in[6]:10 1.59195e-06 +19 chanx_right_in[11]:6 chanx_right_in[6]:8 1.10321e-07 +20 chanx_right_in[11]:5 chanx_right_in[6]:9 1.10321e-07 +21 chanx_right_in[11] chanx_right_in[8] 0.0002223958 +22 chanx_right_in[11]:12 chanx_right_in[8]:28 0.0005330659 +23 chanx_right_in[11]:12 chanx_right_in[8]:29 8.565673e-05 +24 chanx_right_in[11]:7 chanx_right_in[8]:28 2.607471e-05 +25 chanx_right_in[11]:4 chanx_right_in[8]:24 1.268457e-05 +26 chanx_right_in[11]:3 chanx_right_in[8]:25 1.268457e-05 +27 chanx_right_in[11]:13 chanx_right_in[8] 5.958203e-05 +28 chanx_right_in[11]:13 chanx_right_in[8]:29 0.0005330659 +29 chanx_right_in[11]:14 chanx_right_in[8]:29 0.0002223958 +30 chanx_right_in[11]:12 chanx_right_in[1]:7 0.0003805585 +31 chanx_right_in[11]:12 chanx_right_in[1]:8 5.901255e-05 +32 chanx_right_in[11]:7 chanx_right_in[1]:7 5.901255e-05 +33 chanx_right_in[11]:4 chanx_right_in[1]:4 0.0001335849 +34 chanx_right_in[11]:3 chanx_right_in[1]:3 0.0001335849 +35 chanx_right_in[11]:13 chanx_right_in[1]:8 0.0003805585 +36 chanx_right_in[11]:11 mux_tree_tapbuf_size10_5_sram[0]:18 0.0002656568 +37 chanx_right_in[11]:10 mux_tree_tapbuf_size10_5_sram[0]:17 0.0002656568 +38 chanx_right_in[11]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001290283 +39 chanx_right_in[11]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001290283 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:14 0.001392767 +1 chanx_right_in[11]:11 chanx_right_in[11]:10 0.01083705 +2 chanx_right_in[11]:12 chanx_right_in[11]:11 0.00341 +3 chanx_right_in[11]:12 chanx_right_in[11]:7 0.0005032917 +4 chanx_right_in[11]:9 chanx_right_in[11]:8 0.0001548913 +5 chanx_right_in[11]:10 chanx_right_in[11]:9 0.0045 +6 chanx_right_in[11]:8 mux_top_track_8\/mux_l1_in_1_:A0 0.152 +7 chanx_right_in[11]:6 chanx_right_in[11]:5 0.0001634616 +8 chanx_right_in[11]:7 chanx_right_in[11]:6 0.00341 +9 chanx_right_in[11]:4 chanx_right_in[11]:3 0.01441741 +10 chanx_right_in[11]:5 chanx_right_in[11]:4 0.0045 +11 chanx_right_in[11]:3 mux_bottom_track_3\/mux_l1_in_1_:A0 0.152 +12 chanx_right_in[11]:13 chanx_right_in[11]:12 0.0062698 +13 chanx_right_in[11]:14 chanx_right_in[11]:13 0.0001065333 + +*END + +*D_NET chany_bottom_in[1] 0.01949964 //LENGTH 120.945 LUMPCC 0.008369026 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 67.160 1.290 +*I mux_right_track_16\/mux_l1_in_2_:A0 I *L 0.001631 *C 81.250 64.260 +*I mux_left_track_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 50.045 83.300 +*N chany_bottom_in[1]:3 *C 50.083 83.300 +*N chany_bottom_in[1]:4 *C 50.555 83.300 +*N chany_bottom_in[1]:5 *C 50.600 83.255 +*N chany_bottom_in[1]:6 *C 50.600 63.920 +*N chany_bottom_in[1]:7 *C 51.060 63.920 +*N chany_bottom_in[1]:8 *C 51.068 63.920 +*N chany_bottom_in[1]:9 *C 64.400 63.920 +*N chany_bottom_in[1]:10 *C 81.213 64.260 +*N chany_bottom_in[1]:11 *C 75.025 64.260 +*N chany_bottom_in[1]:12 *C 74.980 64.215 +*N chany_bottom_in[1]:13 *C 74.980 63.298 +*N chany_bottom_in[1]:14 *C 74.972 63.240 +*N chany_bottom_in[1]:15 *C 64.400 63.240 +*N chany_bottom_in[1]:16 *C 64.400 63.183 +*N chany_bottom_in[1]:17 *C 64.400 59.218 +*N chany_bottom_in[1]:18 *C 64.407 59.160 +*N chany_bottom_in[1]:19 *C 65.300 59.160 +*N chany_bottom_in[1]:20 *C 65.320 59.153 +*N chany_bottom_in[1]:21 *C 65.320 52.555 +*N chany_bottom_in[1]:22 *C 65.320 2.728 +*N chany_bottom_in[1]:23 *C 65.340 2.720 +*N chany_bottom_in[1]:24 *C 67.153 2.720 +*N chany_bottom_in[1]:25 *C 67.160 2.663 + +*CAP +0 chany_bottom_in[1] 7.673682e-05 +1 mux_right_track_16\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_5\/mux_l2_in_2_:A1 1e-06 +3 chany_bottom_in[1]:3 8.034379e-05 +4 chany_bottom_in[1]:4 8.034379e-05 +5 chany_bottom_in[1]:5 0.001191311 +6 chany_bottom_in[1]:6 0.001226103 +7 chany_bottom_in[1]:7 7.134487e-05 +8 chany_bottom_in[1]:8 0.0008135284 +9 chany_bottom_in[1]:9 0.0008612965 +10 chany_bottom_in[1]:10 0.0002520015 +11 chany_bottom_in[1]:11 0.0002520015 +12 chany_bottom_in[1]:12 9.177811e-05 +13 chany_bottom_in[1]:13 9.177811e-05 +14 chany_bottom_in[1]:14 0.0009057469 +15 chany_bottom_in[1]:15 0.0009535151 +16 chany_bottom_in[1]:16 0.0002865993 +17 chany_bottom_in[1]:17 0.0002865993 +18 chany_bottom_in[1]:18 0.0001291696 +19 chany_bottom_in[1]:19 0.0001291696 +20 chany_bottom_in[1]:20 0.0002723552 +21 chany_bottom_in[1]:21 0.001548897 +22 chany_bottom_in[1]:22 0.001276542 +23 chany_bottom_in[1]:23 8.735616e-05 +24 chany_bottom_in[1]:24 8.735616e-05 +25 chany_bottom_in[1]:25 7.673682e-05 +26 chany_bottom_in[1]:16 chanx_right_in[18]:21 3.945284e-08 +27 chany_bottom_in[1]:17 chanx_right_in[18]:14 3.945284e-08 +28 chany_bottom_in[1]:11 chanx_right_in[18]:27 0.0002357528 +29 chany_bottom_in[1]:10 chanx_right_in[18]:28 0.0002357528 +30 chany_bottom_in[1]:8 chanx_right_in[18]:19 0.0005179699 +31 chany_bottom_in[1]:9 chanx_right_in[18]:20 0.0005179699 +32 chany_bottom_in[1] chany_bottom_in[13] 1.019082e-05 +33 chany_bottom_in[1]:15 chany_bottom_in[13]:33 1.94498e-05 +34 chany_bottom_in[1]:20 chany_bottom_in[13]:32 0.0002571578 +35 chany_bottom_in[1]:23 chany_bottom_in[13]:35 0.0001179874 +36 chany_bottom_in[1]:22 chany_bottom_in[13]:33 2.875098e-05 +37 chany_bottom_in[1]:22 chany_bottom_in[13]:34 0.002099077 +38 chany_bottom_in[1]:25 chany_bottom_in[13]:37 1.019082e-05 +39 chany_bottom_in[1]:24 chany_bottom_in[13]:36 0.0001179874 +40 chany_bottom_in[1]:9 chany_bottom_in[13]:32 1.94498e-05 +41 chany_bottom_in[1]:21 chany_bottom_in[13]:32 2.875098e-05 +42 chany_bottom_in[1]:21 chany_bottom_in[13]:33 0.002356235 +43 chany_bottom_in[1] chany_bottom_in[14] 1.398434e-05 +44 chany_bottom_in[1]:20 chany_bottom_in[14]:43 6.11287e-05 +45 chany_bottom_in[1]:22 chany_bottom_in[14] 6.025631e-06 +46 chany_bottom_in[1]:22 chany_bottom_in[14]:44 0.0008169981 +47 chany_bottom_in[1]:25 chany_bottom_in[14]:47 1.398434e-05 +48 chany_bottom_in[1]:21 chany_bottom_in[14]:43 0.0008169981 +49 chany_bottom_in[1]:21 chany_bottom_in[14]:44 6.11287e-05 +50 chany_bottom_in[1]:21 chany_bottom_in[14]:47 6.025631e-06 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:25 0.001225446 +1 chany_bottom_in[1]:16 chany_bottom_in[1]:15 0.00341 +2 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.001656358 +3 chany_bottom_in[1]:15 chany_bottom_in[1]:9 0.0001065333 +4 chany_bottom_in[1]:17 chany_bottom_in[1]:16 0.003540179 +5 chany_bottom_in[1]:18 chany_bottom_in[1]:17 0.00341 +6 chany_bottom_in[1]:19 chany_bottom_in[1]:18 0.000139825 +7 chany_bottom_in[1]:20 chany_bottom_in[1]:19 0.00341 +8 chany_bottom_in[1]:23 chany_bottom_in[1]:22 0.00341 +9 chany_bottom_in[1]:22 chany_bottom_in[1]:21 0.007806308 +10 chany_bottom_in[1]:25 chany_bottom_in[1]:24 0.00341 +11 chany_bottom_in[1]:24 chany_bottom_in[1]:23 0.0002839583 +12 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.0008191965 +13 chany_bottom_in[1]:14 chany_bottom_in[1]:13 0.00341 +14 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.005524554 +15 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.0045 +16 chany_bottom_in[1]:10 mux_right_track_16\/mux_l1_in_2_:A0 0.152 +17 chany_bottom_in[1]:3 mux_left_track_5\/mux_l2_in_2_:A1 0.152 +18 chany_bottom_in[1]:4 chany_bottom_in[1]:3 0.000421875 +19 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.0045 +20 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.0004107143 +21 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.00341 +22 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.0172634 +23 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.002088758 +24 chany_bottom_in[1]:21 chany_bottom_in[1]:20 0.001033608 + +*END + +*D_NET bottom_left_grid_pin_40_[0] 0.01461623 //LENGTH 82.680 LUMPCC 0.003800301 DR + +*CONN +*P bottom_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 12.920 +*I mux_bottom_track_5\/mux_l2_in_5_:A1 I *L 0.00198 *C 33.580 14.620 +*I mux_bottom_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 48.590 44.540 +*I mux_bottom_track_1\/mux_l1_in_4_:A1 I *L 0.00198 *C 72.780 36.380 +*N bottom_left_grid_pin_40_[0]:4 *C 72.743 36.380 +*N bottom_left_grid_pin_40_[0]:5 *C 70.885 36.380 +*N bottom_left_grid_pin_40_[0]:6 *C 70.840 36.425 +*N bottom_left_grid_pin_40_[0]:7 *C 70.840 39.383 +*N bottom_left_grid_pin_40_[0]:8 *C 70.833 39.440 +*N bottom_left_grid_pin_40_[0]:9 *C 48.590 44.540 +*N bottom_left_grid_pin_40_[0]:10 *C 48.300 44.540 +*N bottom_left_grid_pin_40_[0]:11 *C 48.300 44.495 +*N bottom_left_grid_pin_40_[0]:12 *C 48.300 39.498 +*N bottom_left_grid_pin_40_[0]:13 *C 48.300 39.440 +*N bottom_left_grid_pin_40_[0]:14 *C 40.500 39.440 +*N bottom_left_grid_pin_40_[0]:15 *C 40.480 39.433 +*N bottom_left_grid_pin_40_[0]:16 *C 40.480 12.928 +*N bottom_left_grid_pin_40_[0]:17 *C 40.460 12.920 +*N bottom_left_grid_pin_40_[0]:18 *C 33.543 14.620 +*N bottom_left_grid_pin_40_[0]:19 *C 33.165 14.620 +*N bottom_left_grid_pin_40_[0]:20 *C 33.120 14.575 +*N bottom_left_grid_pin_40_[0]:21 *C 33.120 12.978 +*N bottom_left_grid_pin_40_[0]:22 *C 33.120 12.920 + +*CAP +0 bottom_left_grid_pin_40_[0] 0.0002466324 +1 mux_bottom_track_5\/mux_l2_in_5_:A1 1e-06 +2 mux_bottom_track_25\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_track_1\/mux_l1_in_4_:A1 1e-06 +4 bottom_left_grid_pin_40_[0]:4 0.000139045 +5 bottom_left_grid_pin_40_[0]:5 0.000139045 +6 bottom_left_grid_pin_40_[0]:6 0.0002167294 +7 bottom_left_grid_pin_40_[0]:7 0.0002167294 +8 bottom_left_grid_pin_40_[0]:8 0.0008787567 +9 bottom_left_grid_pin_40_[0]:9 4.951115e-05 +10 bottom_left_grid_pin_40_[0]:10 5.759005e-05 +11 bottom_left_grid_pin_40_[0]:11 0.0003387966 +12 bottom_left_grid_pin_40_[0]:12 0.0003387966 +13 bottom_left_grid_pin_40_[0]:13 0.001222988 +14 bottom_left_grid_pin_40_[0]:14 0.0003442316 +15 bottom_left_grid_pin_40_[0]:15 0.00250602 +16 bottom_left_grid_pin_40_[0]:16 0.00250602 +17 bottom_left_grid_pin_40_[0]:17 0.0005199653 +18 bottom_left_grid_pin_40_[0]:18 5.126589e-05 +19 bottom_left_grid_pin_40_[0]:19 5.126589e-05 +20 bottom_left_grid_pin_40_[0]:20 0.0001114716 +21 bottom_left_grid_pin_40_[0]:21 0.0001114716 +22 bottom_left_grid_pin_40_[0]:22 0.0007665977 +23 bottom_left_grid_pin_40_[0]:8 chanx_left_in[8]:26 0.0002303374 +24 bottom_left_grid_pin_40_[0]:12 chanx_left_in[8]:28 1.907628e-08 +25 bottom_left_grid_pin_40_[0]:13 chanx_left_in[8]:26 4.274502e-05 +26 bottom_left_grid_pin_40_[0]:13 chanx_left_in[8]:27 0.0002303374 +27 bottom_left_grid_pin_40_[0]:11 chanx_left_in[8]:6 1.907628e-08 +28 bottom_left_grid_pin_40_[0]:14 chanx_left_in[8]:27 4.274502e-05 +29 bottom_left_grid_pin_40_[0]:8 chanx_left_in[1]:18 0.0008160236 +30 bottom_left_grid_pin_40_[0]:8 chanx_left_in[1]:19 0.00038321 +31 bottom_left_grid_pin_40_[0]:5 chanx_left_in[1]:15 2.947999e-06 +32 bottom_left_grid_pin_40_[0]:4 chanx_left_in[1]:14 2.947999e-06 +33 bottom_left_grid_pin_40_[0]:13 chanx_left_in[1]:20 0.00038321 +34 bottom_left_grid_pin_40_[0]:13 chanx_left_in[1]:19 0.001240891 +35 bottom_left_grid_pin_40_[0]:14 chanx_left_in[1]:20 0.0004248676 + +*RES +0 bottom_left_grid_pin_40_[0] bottom_left_grid_pin_40_[0]:22 0.0005279667 +1 bottom_left_grid_pin_40_[0]:21 bottom_left_grid_pin_40_[0]:20 0.001426339 +2 bottom_left_grid_pin_40_[0]:22 bottom_left_grid_pin_40_[0]:21 0.00341 +3 bottom_left_grid_pin_40_[0]:22 bottom_left_grid_pin_40_[0]:17 0.001149933 +4 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_40_[0]:18 0.0003370536 +5 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_40_[0]:19 0.0045 +6 bottom_left_grid_pin_40_[0]:18 mux_bottom_track_5\/mux_l2_in_5_:A1 0.152 +7 bottom_left_grid_pin_40_[0]:7 bottom_left_grid_pin_40_[0]:6 0.002640625 +8 bottom_left_grid_pin_40_[0]:8 bottom_left_grid_pin_40_[0]:7 0.00341 +9 bottom_left_grid_pin_40_[0]:5 bottom_left_grid_pin_40_[0]:4 0.001658482 +10 bottom_left_grid_pin_40_[0]:6 bottom_left_grid_pin_40_[0]:5 0.0045 +11 bottom_left_grid_pin_40_[0]:4 mux_bottom_track_1\/mux_l1_in_4_:A1 0.152 +12 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_40_[0]:11 0.004462053 +13 bottom_left_grid_pin_40_[0]:13 bottom_left_grid_pin_40_[0]:12 0.00341 +14 bottom_left_grid_pin_40_[0]:13 bottom_left_grid_pin_40_[0]:8 0.003530091 +15 bottom_left_grid_pin_40_[0]:10 bottom_left_grid_pin_40_[0]:9 0.0001576087 +16 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_40_[0]:10 0.0045 +17 bottom_left_grid_pin_40_[0]:9 mux_bottom_track_25\/mux_l2_in_1_:A0 0.152 +18 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_40_[0]:16 0.00341 +19 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_40_[0]:15 0.00415245 +20 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_40_[0]:13 0.001222 +21 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_40_[0]:14 0.00341 + +*END + +*D_NET left_top_grid_pin_45_[0] 0.008232515 //LENGTH 64.655 LUMPCC 0.001060529 DR + +*CONN +*P left_top_grid_pin_45_[0] I *L 0.29796 *C 5.060 102.035 +*I mux_left_track_5\/mux_l2_in_5_:A1 I *L 0.00198 *C 19.780 90.780 +*I mux_left_track_33\/mux_l1_in_2_:A0 I *L 0.001631 *C 26.970 75.140 +*I mux_left_track_3\/mux_l1_in_4_:A0 I *L 0.001631 *C 23.305 93.500 +*N left_top_grid_pin_45_[0]:4 *C 23.268 93.500 +*N left_top_grid_pin_45_[0]:5 *C 22.585 93.500 +*N left_top_grid_pin_45_[0]:6 *C 22.540 93.545 +*N left_top_grid_pin_45_[0]:7 *C 22.540 101.615 +*N left_top_grid_pin_45_[0]:8 *C 22.495 101.660 +*N left_top_grid_pin_45_[0]:9 *C 26.933 75.140 +*N left_top_grid_pin_45_[0]:10 *C 24.425 75.140 +*N left_top_grid_pin_45_[0]:11 *C 24.380 75.140 +*N left_top_grid_pin_45_[0]:12 *C 24.380 75.480 +*N left_top_grid_pin_45_[0]:13 *C 24.373 75.480 +*N left_top_grid_pin_45_[0]:14 *C 20.260 75.480 +*N left_top_grid_pin_45_[0]:15 *C 20.240 75.487 +*N left_top_grid_pin_45_[0]:16 *C 20.240 87.032 +*N left_top_grid_pin_45_[0]:17 *C 20.225 87.040 +*N left_top_grid_pin_45_[0]:18 *C 19.783 87.040 +*N left_top_grid_pin_45_[0]:19 *C 19.780 87.098 +*N left_top_grid_pin_45_[0]:20 *C 19.780 90.780 +*N left_top_grid_pin_45_[0]:21 *C 19.780 90.780 +*N left_top_grid_pin_45_[0]:22 *C 19.780 101.615 +*N left_top_grid_pin_45_[0]:23 *C 19.780 101.660 +*N left_top_grid_pin_45_[0]:24 *C 19.780 102.000 +*N left_top_grid_pin_45_[0]:25 *C 12.420 102.000 +*N left_top_grid_pin_45_[0]:26 *C 12.420 101.660 +*N left_top_grid_pin_45_[0]:27 *C 5.105 101.660 +*N left_top_grid_pin_45_[0]:28 *C 5.060 101.705 + +*CAP +0 left_top_grid_pin_45_[0] 3.185184e-05 +1 mux_left_track_5\/mux_l2_in_5_:A1 1e-06 +2 mux_left_track_33\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_3\/mux_l1_in_4_:A0 1e-06 +4 left_top_grid_pin_45_[0]:4 8.172428e-05 +5 left_top_grid_pin_45_[0]:5 8.172428e-05 +6 left_top_grid_pin_45_[0]:6 0.000375594 +7 left_top_grid_pin_45_[0]:7 0.000375594 +8 left_top_grid_pin_45_[0]:8 0.0001343578 +9 left_top_grid_pin_45_[0]:9 0.0001385762 +10 left_top_grid_pin_45_[0]:10 0.0001385762 +11 left_top_grid_pin_45_[0]:11 6.234943e-05 +12 left_top_grid_pin_45_[0]:12 6.661649e-05 +13 left_top_grid_pin_45_[0]:13 0.0003333328 +14 left_top_grid_pin_45_[0]:14 0.0003333328 +15 left_top_grid_pin_45_[0]:15 0.0008134426 +16 left_top_grid_pin_45_[0]:16 0.0008134426 +17 left_top_grid_pin_45_[0]:17 8.371912e-05 +18 left_top_grid_pin_45_[0]:18 8.371912e-05 +19 left_top_grid_pin_45_[0]:19 0.0002139037 +20 left_top_grid_pin_45_[0]:20 3.466688e-05 +21 left_top_grid_pin_45_[0]:21 0.0007913624 +22 left_top_grid_pin_45_[0]:22 0.0005462097 +23 left_top_grid_pin_45_[0]:23 0.000162738 +24 left_top_grid_pin_45_[0]:24 0.0003457234 +25 left_top_grid_pin_45_[0]:25 0.0003413962 +26 left_top_grid_pin_45_[0]:26 0.0003886171 +27 left_top_grid_pin_45_[0]:27 0.000364564 +28 left_top_grid_pin_45_[0]:28 3.185184e-05 +29 left_top_grid_pin_45_[0] left_top_grid_pin_44_[0] 6.108237e-06 +30 left_top_grid_pin_45_[0]:23 left_top_grid_pin_44_[0]:21 2.24049e-05 +31 left_top_grid_pin_45_[0]:8 left_top_grid_pin_44_[0]:20 2.24049e-05 +32 left_top_grid_pin_45_[0]:7 left_top_grid_pin_44_[0]:18 2.387587e-05 +33 left_top_grid_pin_45_[0]:6 left_top_grid_pin_44_[0]:17 2.387587e-05 +34 left_top_grid_pin_45_[0]:27 left_top_grid_pin_44_[0]:21 7.227217e-05 +35 left_top_grid_pin_45_[0]:28 left_top_grid_pin_44_[0]:23 6.108237e-06 +36 left_top_grid_pin_45_[0]:26 left_top_grid_pin_44_[0]:20 7.227217e-05 +37 left_top_grid_pin_45_[0]:25 left_top_grid_pin_44_[0]:21 0.0001429459 +38 left_top_grid_pin_45_[0]:24 left_top_grid_pin_44_[0]:20 0.0001429459 +39 left_top_grid_pin_45_[0]:22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.231953e-05 +40 left_top_grid_pin_45_[0]:21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.231953e-05 +41 left_top_grid_pin_45_[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.05826e-05 +42 left_top_grid_pin_45_[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.05826e-05 +43 left_top_grid_pin_45_[0]:23 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.46972e-05 +44 left_top_grid_pin_45_[0]:22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 2.431195e-05 +45 left_top_grid_pin_45_[0]:21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 2.431195e-05 +46 left_top_grid_pin_45_[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.46972e-05 +47 left_top_grid_pin_45_[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 8.772924e-07 +48 left_top_grid_pin_45_[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 5.618749e-06 +49 left_top_grid_pin_45_[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 8.772924e-07 +50 left_top_grid_pin_45_[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 5.618749e-06 +51 left_top_grid_pin_45_[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001042499 +52 left_top_grid_pin_45_[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001042499 + +*RES +0 left_top_grid_pin_45_[0] left_top_grid_pin_45_[0]:28 0.0002946429 +1 left_top_grid_pin_45_[0]:23 left_top_grid_pin_45_[0]:22 0.0045 +2 left_top_grid_pin_45_[0]:23 left_top_grid_pin_45_[0]:8 0.002424107 +3 left_top_grid_pin_45_[0]:22 left_top_grid_pin_45_[0]:21 0.009674108 +4 left_top_grid_pin_45_[0]:20 mux_left_track_5\/mux_l2_in_5_:A1 0.152 +5 left_top_grid_pin_45_[0]:21 left_top_grid_pin_45_[0]:20 0.0045 +6 left_top_grid_pin_45_[0]:21 left_top_grid_pin_45_[0]:19 0.003287947 +7 left_top_grid_pin_45_[0]:19 left_top_grid_pin_45_[0]:18 0.00341 +8 left_top_grid_pin_45_[0]:18 left_top_grid_pin_45_[0]:17 6.499219e-05 +9 left_top_grid_pin_45_[0]:17 left_top_grid_pin_45_[0]:16 0.00341 +10 left_top_grid_pin_45_[0]:16 left_top_grid_pin_45_[0]:15 0.001808717 +11 left_top_grid_pin_45_[0]:14 left_top_grid_pin_45_[0]:13 0.0006442916 +12 left_top_grid_pin_45_[0]:15 left_top_grid_pin_45_[0]:14 0.00341 +13 left_top_grid_pin_45_[0]:12 left_top_grid_pin_45_[0]:11 0.0001634615 +14 left_top_grid_pin_45_[0]:13 left_top_grid_pin_45_[0]:12 0.00341 +15 left_top_grid_pin_45_[0]:10 left_top_grid_pin_45_[0]:9 0.002238839 +16 left_top_grid_pin_45_[0]:11 left_top_grid_pin_45_[0]:10 0.0045 +17 left_top_grid_pin_45_[0]:9 mux_left_track_33\/mux_l1_in_2_:A0 0.152 +18 left_top_grid_pin_45_[0]:8 left_top_grid_pin_45_[0]:7 0.0045 +19 left_top_grid_pin_45_[0]:7 left_top_grid_pin_45_[0]:6 0.007205358 +20 left_top_grid_pin_45_[0]:5 left_top_grid_pin_45_[0]:4 0.000609375 +21 left_top_grid_pin_45_[0]:6 left_top_grid_pin_45_[0]:5 0.0045 +22 left_top_grid_pin_45_[0]:4 mux_left_track_3\/mux_l1_in_4_:A0 0.152 +23 left_top_grid_pin_45_[0]:27 left_top_grid_pin_45_[0]:26 0.006531251 +24 left_top_grid_pin_45_[0]:28 left_top_grid_pin_45_[0]:27 0.0045 +25 left_top_grid_pin_45_[0]:26 left_top_grid_pin_45_[0]:25 0.0003035715 +26 left_top_grid_pin_45_[0]:25 left_top_grid_pin_45_[0]:24 0.006571429 +27 left_top_grid_pin_45_[0]:24 left_top_grid_pin_45_[0]:23 0.0003035715 + +*END + +*D_NET chany_bottom_out[12] 0.005140627 //LENGTH 40.775 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 45.540 4.080 +*P chany_bottom_out[12] O *L 0.7423 *C 80.500 1.325 +*N chany_bottom_out[12]:2 *C 80.500 1.655 +*N chany_bottom_out[12]:3 *C 80.500 1.700 +*N chany_bottom_out[12]:4 *C 80.500 0.680 +*N chany_bottom_out[12]:5 *C 45.540 0.680 +*N chany_bottom_out[12]:6 *C 45.540 1.700 +*N chany_bottom_out[12]:7 *C 45.540 1.745 +*N chany_bottom_out[12]:8 *C 45.540 4.035 +*N chany_bottom_out[12]:9 *C 45.540 4.080 + +*CAP +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[12] 4.178498e-05 +2 chany_bottom_out[12]:2 4.178498e-05 +3 chany_bottom_out[12]:3 0.000104705 +4 chany_bottom_out[12]:4 0.002290357 +5 chany_bottom_out[12]:5 0.002277785 +6 chany_bottom_out[12]:6 8.431592e-05 +7 chany_bottom_out[12]:7 0.0001353894 +8 chany_bottom_out[12]:8 0.0001353894 +9 chany_bottom_out[12]:9 2.811593e-05 + +*RES +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[12]:9 0.152 +1 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +2 chany_bottom_out[12]:2 chany_bottom_out[12] 0.0002946429 +3 chany_bottom_out[12]:6 chany_bottom_out[12]:5 0.0009107143 +4 chany_bottom_out[12]:7 chany_bottom_out[12]:6 0.0045 +5 chany_bottom_out[12]:9 chany_bottom_out[12]:8 0.0045 +6 chany_bottom_out[12]:8 chany_bottom_out[12]:7 0.002044643 +7 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.03121429 +8 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.0009107143 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.00176365 //LENGTH 15.400 LUMPCC 0.0001252914 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 113.925 39.440 +*I mux_top_track_8\/mux_l4_in_0_:S I *L 0.00357 *C 111.420 47.600 +*I mem_top_track_8\/FTB_13__64:A I *L 0.001746 *C 117.760 47.600 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 117.723 47.600 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 111.458 47.600 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 113.620 47.600 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 113.620 47.555 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 113.620 39.485 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 113.620 39.440 +*N mux_tree_tapbuf_size10_0_sram[3]:9 *C 113.925 39.440 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:S 1e-06 +2 mem_top_track_8\/FTB_13__64:A 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 0.0002404928 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001383176 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0004119553 +6 mux_tree_tapbuf_size10_0_sram[3]:6 0.0003813512 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0003813512 +8 mux_tree_tapbuf_size10_0_sram[3]:8 4.262289e-05 +9 mux_tree_tapbuf_size10_0_sram[3]:9 3.926739e-05 +10 mux_tree_tapbuf_size10_0_sram[3]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.900536e-06 +11 mux_tree_tapbuf_size10_0_sram[3]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.900536e-06 +12 mux_tree_tapbuf_size10_0_sram[3]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.774515e-05 +13 mux_tree_tapbuf_size10_0_sram[3]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.774515e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:9 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:4 mux_top_track_8\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.001930804 +3 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:3 0.003662946 +4 mux_tree_tapbuf_size10_0_sram[3]:6 mux_tree_tapbuf_size10_0_sram[3]:5 0.0045 +5 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.007205358 +7 mux_tree_tapbuf_size10_0_sram[3]:9 mux_tree_tapbuf_size10_0_sram[3]:8 0.0001657609 +8 mux_tree_tapbuf_size10_0_sram[3]:3 mem_top_track_8\/FTB_13__64:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.002011022 //LENGTH 14.225 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 47.225 55.760 +*I mux_top_track_16\/mux_l4_in_0_:S I *L 0.00357 *C 48.640 57.800 +*I mem_top_track_16\/FTB_14__65:A I *L 0.001746 *C 53.820 61.200 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 53.820 61.200 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 53.820 61.540 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 52.485 61.540 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 52.440 61.495 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 52.440 57.845 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 52.395 57.800 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 48.640 57.800 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 47.425 57.800 +*N mux_tree_tapbuf_size10_1_sram[3]:11 *C 47.380 57.755 +*N mux_tree_tapbuf_size10_1_sram[3]:12 *C 47.380 55.805 +*N mux_tree_tapbuf_size10_1_sram[3]:13 *C 47.380 55.760 +*N mux_tree_tapbuf_size10_1_sram[3]:14 *C 47.225 55.760 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_top_track_16\/mux_l4_in_0_:S 1e-06 +2 mem_top_track_16\/FTB_14__65:A 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 7.22539e-05 +4 mux_tree_tapbuf_size10_1_sram[3]:4 0.0001691752 +5 mux_tree_tapbuf_size10_1_sram[3]:5 0.0001346142 +6 mux_tree_tapbuf_size10_1_sram[3]:6 0.0002473918 +7 mux_tree_tapbuf_size10_1_sram[3]:7 0.0002473918 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.0002613285 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.0003872213 +10 mux_tree_tapbuf_size10_1_sram[3]:10 9.657139e-05 +11 mux_tree_tapbuf_size10_1_sram[3]:11 0.0001309184 +12 mux_tree_tapbuf_size10_1_sram[3]:12 0.0001309184 +13 mux_tree_tapbuf_size10_1_sram[3]:13 6.408022e-05 +14 mux_tree_tapbuf_size10_1_sram[3]:14 6.615705e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:14 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:9 mux_top_track_16\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.003352679 +3 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.001084822 +4 mux_tree_tapbuf_size10_1_sram[3]:11 mux_tree_tapbuf_size10_1_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size10_1_sram[3]:13 mux_tree_tapbuf_size10_1_sram[3]:12 0.0045 +6 mux_tree_tapbuf_size10_1_sram[3]:12 mux_tree_tapbuf_size10_1_sram[3]:11 0.001741072 +7 mux_tree_tapbuf_size10_1_sram[3]:14 mux_tree_tapbuf_size10_1_sram[3]:13 8.423914e-05 +8 mux_tree_tapbuf_size10_1_sram[3]:3 mem_top_track_16\/FTB_14__65:A 0.152 +9 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:4 0.001191964 +10 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.0045 +11 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.0045 +12 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 0.003258929 +13 mux_tree_tapbuf_size10_1_sram[3]:4 mux_tree_tapbuf_size10_1_sram[3]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_3_sram[2] 0.001867545 //LENGTH 14.705 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 111.625 58.820 +*I mux_right_track_8\/mux_l3_in_1_:S I *L 0.00357 *C 115.820 56.440 +*I mux_right_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 114.440 63.240 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 114.715 58.820 +*N mux_tree_tapbuf_size10_3_sram[2]:4 *C 114.590 58.820 +*N mux_tree_tapbuf_size10_3_sram[2]:5 *C 114.440 63.240 +*N mux_tree_tapbuf_size10_3_sram[2]:6 *C 114.540 63.195 +*N mux_tree_tapbuf_size10_3_sram[2]:7 *C 114.540 58.865 +*N mux_tree_tapbuf_size10_3_sram[2]:8 *C 114.495 58.820 +*N mux_tree_tapbuf_size10_3_sram[2]:9 *C 115.782 56.440 +*N mux_tree_tapbuf_size10_3_sram[2]:10 *C 112.285 56.440 +*N mux_tree_tapbuf_size10_3_sram[2]:11 *C 112.240 56.485 +*N mux_tree_tapbuf_size10_3_sram[2]:12 *C 112.240 58.775 +*N mux_tree_tapbuf_size10_3_sram[2]:13 *C 112.240 58.820 +*N mux_tree_tapbuf_size10_3_sram[2]:14 *C 111.663 58.820 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_8\/mux_l3_in_1_:S 1e-06 +2 mux_right_track_8\/mux_l3_in_0_:S 1e-06 +3 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size10_3_sram[2]:4 2.458228e-05 +5 mux_tree_tapbuf_size10_3_sram[2]:5 2.977271e-05 +6 mux_tree_tapbuf_size10_3_sram[2]:6 0.0002686335 +7 mux_tree_tapbuf_size10_3_sram[2]:7 0.0002686335 +8 mux_tree_tapbuf_size10_3_sram[2]:8 0.0001764536 +9 mux_tree_tapbuf_size10_3_sram[2]:9 0.0002593086 +10 mux_tree_tapbuf_size10_3_sram[2]:10 0.0002593086 +11 mux_tree_tapbuf_size10_3_sram[2]:11 0.0001505801 +12 mux_tree_tapbuf_size10_3_sram[2]:12 0.0001505801 +13 mux_tree_tapbuf_size10_3_sram[2]:13 0.0002299061 +14 mux_tree_tapbuf_size10_3_sram[2]:14 4.578583e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_3_sram[2]:14 0.152 +1 mux_tree_tapbuf_size10_3_sram[2]:13 mux_tree_tapbuf_size10_3_sram[2]:12 0.0045 +2 mux_tree_tapbuf_size10_3_sram[2]:13 mux_tree_tapbuf_size10_3_sram[2]:8 0.002013393 +3 mux_tree_tapbuf_size10_3_sram[2]:12 mux_tree_tapbuf_size10_3_sram[2]:11 0.002044643 +4 mux_tree_tapbuf_size10_3_sram[2]:10 mux_tree_tapbuf_size10_3_sram[2]:9 0.003122768 +5 mux_tree_tapbuf_size10_3_sram[2]:11 mux_tree_tapbuf_size10_3_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size10_3_sram[2]:9 mux_right_track_8\/mux_l3_in_1_:S 0.152 +7 mux_tree_tapbuf_size10_3_sram[2]:4 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_3_sram[2]:14 mux_tree_tapbuf_size10_3_sram[2]:13 0.000515625 +9 mux_tree_tapbuf_size10_3_sram[2]:8 mux_tree_tapbuf_size10_3_sram[2]:7 0.0045 +10 mux_tree_tapbuf_size10_3_sram[2]:8 mux_tree_tapbuf_size10_3_sram[2]:4 8.482143e-05 +11 mux_tree_tapbuf_size10_3_sram[2]:7 mux_tree_tapbuf_size10_3_sram[2]:6 0.003866071 +12 mux_tree_tapbuf_size10_3_sram[2]:5 mux_right_track_8\/mux_l3_in_0_:S 0.152 +13 mux_tree_tapbuf_size10_3_sram[2]:6 mux_tree_tapbuf_size10_3_sram[2]:5 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_5_sram[0] 0.00897979 //LENGTH 71.967 LUMPCC 0.001051956 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 97.825 42.500 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 91.255 77.180 +*I mux_right_track_24\/mux_l1_in_2_:S I *L 0.00357 *C 90.980 82.960 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 74.880 88.400 +*I mux_right_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 85.200 88.695 +*N mux_tree_tapbuf_size10_5_sram[0]:5 *C 85.200 88.695 +*N mux_tree_tapbuf_size10_5_sram[0]:6 *C 74.918 88.400 +*N mux_tree_tapbuf_size10_5_sram[0]:7 *C 85.142 88.400 +*N mux_tree_tapbuf_size10_5_sram[0]:8 *C 90.575 88.400 +*N mux_tree_tapbuf_size10_5_sram[0]:9 *C 90.620 88.355 +*N mux_tree_tapbuf_size10_5_sram[0]:10 *C 90.620 82.960 +*N mux_tree_tapbuf_size10_5_sram[0]:11 *C 90.980 82.960 +*N mux_tree_tapbuf_size10_5_sram[0]:12 *C 91.080 82.915 +*N mux_tree_tapbuf_size10_5_sram[0]:13 *C 91.080 77.225 +*N mux_tree_tapbuf_size10_5_sram[0]:14 *C 91.080 77.180 +*N mux_tree_tapbuf_size10_5_sram[0]:15 *C 91.293 77.180 +*N mux_tree_tapbuf_size10_5_sram[0]:16 *C 91.955 77.180 +*N mux_tree_tapbuf_size10_5_sram[0]:17 *C 92.000 77.135 +*N mux_tree_tapbuf_size10_5_sram[0]:18 *C 92.000 44.925 +*N mux_tree_tapbuf_size10_5_sram[0]:19 *C 92.045 44.880 +*N mux_tree_tapbuf_size10_5_sram[0]:20 *C 94.715 44.880 +*N mux_tree_tapbuf_size10_5_sram[0]:21 *C 94.760 44.835 +*N mux_tree_tapbuf_size10_5_sram[0]:22 *C 94.760 42.545 +*N mux_tree_tapbuf_size10_5_sram[0]:23 *C 94.805 42.500 +*N mux_tree_tapbuf_size10_5_sram[0]:24 *C 97.788 42.500 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_24\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +4 mux_right_track_24\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size10_5_sram[0]:5 5.746713e-05 +6 mux_tree_tapbuf_size10_5_sram[0]:6 0.0005502718 +7 mux_tree_tapbuf_size10_5_sram[0]:7 0.0009336108 +8 mux_tree_tapbuf_size10_5_sram[0]:8 0.000353994 +9 mux_tree_tapbuf_size10_5_sram[0]:9 0.0003641963 +10 mux_tree_tapbuf_size10_5_sram[0]:10 0.0003992892 +11 mux_tree_tapbuf_size10_5_sram[0]:11 3.327918e-05 +12 mux_tree_tapbuf_size10_5_sram[0]:12 0.00037928 +13 mux_tree_tapbuf_size10_5_sram[0]:13 0.0003441871 +14 mux_tree_tapbuf_size10_5_sram[0]:14 5.59468e-05 +15 mux_tree_tapbuf_size10_5_sram[0]:15 7.741919e-05 +16 mux_tree_tapbuf_size10_5_sram[0]:16 5.627757e-05 +17 mux_tree_tapbuf_size10_5_sram[0]:17 0.001689931 +18 mux_tree_tapbuf_size10_5_sram[0]:18 0.001689931 +19 mux_tree_tapbuf_size10_5_sram[0]:19 0.0001195423 +20 mux_tree_tapbuf_size10_5_sram[0]:20 0.0001195423 +21 mux_tree_tapbuf_size10_5_sram[0]:21 0.0001562431 +22 mux_tree_tapbuf_size10_5_sram[0]:22 0.0001562431 +23 mux_tree_tapbuf_size10_5_sram[0]:23 0.0001930906 +24 mux_tree_tapbuf_size10_5_sram[0]:24 0.0001930906 +25 mux_tree_tapbuf_size10_5_sram[0]:17 chanx_right_in[11]:10 0.0002656568 +26 mux_tree_tapbuf_size10_5_sram[0]:18 chanx_right_in[11]:11 0.0002656568 +27 mux_tree_tapbuf_size10_5_sram[0]:19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001108981 +28 mux_tree_tapbuf_size10_5_sram[0]:20 mux_right_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001108981 +29 mux_tree_tapbuf_size10_5_sram[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001494229 +30 mux_tree_tapbuf_size10_5_sram[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001494229 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_5_sram[0]:24 0.152 +1 mux_tree_tapbuf_size10_5_sram[0]:8 mux_tree_tapbuf_size10_5_sram[0]:7 0.004850446 +2 mux_tree_tapbuf_size10_5_sram[0]:9 mux_tree_tapbuf_size10_5_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size10_5_sram[0]:11 mux_right_track_24\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size10_5_sram[0]:12 mux_tree_tapbuf_size10_5_sram[0]:10 0.0004107143 +6 mux_tree_tapbuf_size10_5_sram[0]:15 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size10_5_sram[0]:15 mux_tree_tapbuf_size10_5_sram[0]:14 0.0001154891 +8 mux_tree_tapbuf_size10_5_sram[0]:6 mux_right_track_24\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size10_5_sram[0]:14 mux_tree_tapbuf_size10_5_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size10_5_sram[0]:13 mux_tree_tapbuf_size10_5_sram[0]:12 0.005080357 +11 mux_tree_tapbuf_size10_5_sram[0]:5 mux_right_track_24\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_5_sram[0]:16 mux_tree_tapbuf_size10_5_sram[0]:15 0.0005915179 +13 mux_tree_tapbuf_size10_5_sram[0]:17 mux_tree_tapbuf_size10_5_sram[0]:16 0.0045 +14 mux_tree_tapbuf_size10_5_sram[0]:19 mux_tree_tapbuf_size10_5_sram[0]:18 0.0045 +15 mux_tree_tapbuf_size10_5_sram[0]:18 mux_tree_tapbuf_size10_5_sram[0]:17 0.02875893 +16 mux_tree_tapbuf_size10_5_sram[0]:20 mux_tree_tapbuf_size10_5_sram[0]:19 0.002383929 +17 mux_tree_tapbuf_size10_5_sram[0]:21 mux_tree_tapbuf_size10_5_sram[0]:20 0.0045 +18 mux_tree_tapbuf_size10_5_sram[0]:23 mux_tree_tapbuf_size10_5_sram[0]:22 0.0045 +19 mux_tree_tapbuf_size10_5_sram[0]:22 mux_tree_tapbuf_size10_5_sram[0]:21 0.002044643 +20 mux_tree_tapbuf_size10_5_sram[0]:24 mux_tree_tapbuf_size10_5_sram[0]:23 0.002662947 +21 mux_tree_tapbuf_size10_5_sram[0]:7 mux_tree_tapbuf_size10_5_sram[0]:6 0.009129466 +22 mux_tree_tapbuf_size10_5_sram[0]:7 mux_tree_tapbuf_size10_5_sram[0]:5 0.0001271552 +23 mux_tree_tapbuf_size10_5_sram[0]:10 mux_tree_tapbuf_size10_5_sram[0]:9 0.004816965 + +*END + +*D_NET mux_tree_tapbuf_size10_9_sram[1] 0.005651533 //LENGTH 40.125 LUMPCC 0.0004042769 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 32.965 72.080 +*I mux_left_track_9\/mux_l2_in_3_:S I *L 0.00357 *C 31.640 78.200 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 42.495 75.140 +*I mux_left_track_9\/mux_l2_in_2_:S I *L 0.00357 *C 43.340 77.520 +*I mux_left_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 48.400 72.080 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 53.460 74.120 +*N mux_tree_tapbuf_size10_9_sram[1]:6 *C 53.422 74.120 +*N mux_tree_tapbuf_size10_9_sram[1]:7 *C 48.300 72.080 +*N mux_tree_tapbuf_size10_9_sram[1]:8 *C 48.300 72.125 +*N mux_tree_tapbuf_size10_9_sram[1]:9 *C 48.300 74.075 +*N mux_tree_tapbuf_size10_9_sram[1]:10 *C 48.345 74.120 +*N mux_tree_tapbuf_size10_9_sram[1]:11 *C 48.760 74.120 +*N mux_tree_tapbuf_size10_9_sram[1]:12 *C 48.760 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:13 *C 43.240 77.520 +*N mux_tree_tapbuf_size10_9_sram[1]:14 *C 43.240 77.475 +*N mux_tree_tapbuf_size10_9_sram[1]:15 *C 43.240 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:16 *C 42.780 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:17 *C 42.825 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:18 *C 42.495 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:19 *C 42.320 75.480 +*N mux_tree_tapbuf_size10_9_sram[1]:20 *C 31.678 78.200 +*N mux_tree_tapbuf_size10_9_sram[1]:21 *C 32.155 78.200 +*N mux_tree_tapbuf_size10_9_sram[1]:22 *C 32.200 78.155 +*N mux_tree_tapbuf_size10_9_sram[1]:23 *C 32.200 74.845 +*N mux_tree_tapbuf_size10_9_sram[1]:24 *C 32.200 74.800 +*N mux_tree_tapbuf_size10_9_sram[1]:25 *C 32.660 74.800 +*N mux_tree_tapbuf_size10_9_sram[1]:26 *C 32.660 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:27 *C 33.120 75.140 +*N mux_tree_tapbuf_size10_9_sram[1]:28 *C 33.120 75.480 +*N mux_tree_tapbuf_size10_9_sram[1]:29 *C 33.120 75.435 +*N mux_tree_tapbuf_size10_9_sram[1]:30 *C 33.120 72.125 +*N mux_tree_tapbuf_size10_9_sram[1]:31 *C 33.120 72.080 +*N mux_tree_tapbuf_size10_9_sram[1]:32 *C 32.965 72.080 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_9\/mux_l2_in_3_:S 1e-06 +2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_9\/mux_l2_in_2_:S 1e-06 +4 mux_left_track_9\/mux_l2_in_1_:S 1e-06 +5 mux_left_track_9\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_9_sram[1]:6 0.000300343 +7 mux_tree_tapbuf_size10_9_sram[1]:7 3.445918e-05 +8 mux_tree_tapbuf_size10_9_sram[1]:8 0.0001407091 +9 mux_tree_tapbuf_size10_9_sram[1]:9 0.0001407091 +10 mux_tree_tapbuf_size10_9_sram[1]:10 3.923496e-05 +11 mux_tree_tapbuf_size10_9_sram[1]:11 0.0004000006 +12 mux_tree_tapbuf_size10_9_sram[1]:12 0.0003951101 +13 mux_tree_tapbuf_size10_9_sram[1]:13 3.099233e-05 +14 mux_tree_tapbuf_size10_9_sram[1]:14 0.0001374618 +15 mux_tree_tapbuf_size10_9_sram[1]:15 0.0001737163 +16 mux_tree_tapbuf_size10_9_sram[1]:16 7.093813e-05 +17 mux_tree_tapbuf_size10_9_sram[1]:17 0.0003593124 +18 mux_tree_tapbuf_size10_9_sram[1]:18 7.982594e-05 +19 mux_tree_tapbuf_size10_9_sram[1]:19 0.0006767107 +20 mux_tree_tapbuf_size10_9_sram[1]:20 5.799715e-05 +21 mux_tree_tapbuf_size10_9_sram[1]:21 5.799715e-05 +22 mux_tree_tapbuf_size10_9_sram[1]:22 0.0002547091 +23 mux_tree_tapbuf_size10_9_sram[1]:23 0.0002547091 +24 mux_tree_tapbuf_size10_9_sram[1]:24 0.0001095145 +25 mux_tree_tapbuf_size10_9_sram[1]:25 0.0001125115 +26 mux_tree_tapbuf_size10_9_sram[1]:26 7.237977e-05 +27 mux_tree_tapbuf_size10_9_sram[1]:27 7.561094e-05 +28 mux_tree_tapbuf_size10_9_sram[1]:28 0.0006824504 +29 mux_tree_tapbuf_size10_9_sram[1]:29 0.0002376714 +30 mux_tree_tapbuf_size10_9_sram[1]:30 0.0002376714 +31 mux_tree_tapbuf_size10_9_sram[1]:31 5.568315e-05 +32 mux_tree_tapbuf_size10_9_sram[1]:32 5.282634e-05 +33 mux_tree_tapbuf_size10_9_sram[1]:17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001797976 +34 mux_tree_tapbuf_size10_9_sram[1]:14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.741025e-06 +35 mux_tree_tapbuf_size10_9_sram[1]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.659984e-05 +36 mux_tree_tapbuf_size10_9_sram[1]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001797976 +37 mux_tree_tapbuf_size10_9_sram[1]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.659984e-05 +38 mux_tree_tapbuf_size10_9_sram[1]:15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.741025e-06 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_9_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_9_sram[1]:28 mux_tree_tapbuf_size10_9_sram[1]:27 0.0003035715 +2 mux_tree_tapbuf_size10_9_sram[1]:28 mux_tree_tapbuf_size10_9_sram[1]:19 0.008214287 +3 mux_tree_tapbuf_size10_9_sram[1]:29 mux_tree_tapbuf_size10_9_sram[1]:28 0.0045 +4 mux_tree_tapbuf_size10_9_sram[1]:31 mux_tree_tapbuf_size10_9_sram[1]:30 0.0045 +5 mux_tree_tapbuf_size10_9_sram[1]:30 mux_tree_tapbuf_size10_9_sram[1]:29 0.002955357 +6 mux_tree_tapbuf_size10_9_sram[1]:32 mux_tree_tapbuf_size10_9_sram[1]:31 8.423914e-05 +7 mux_tree_tapbuf_size10_9_sram[1]:24 mux_tree_tapbuf_size10_9_sram[1]:23 0.0045 +8 mux_tree_tapbuf_size10_9_sram[1]:23 mux_tree_tapbuf_size10_9_sram[1]:22 0.002955357 +9 mux_tree_tapbuf_size10_9_sram[1]:21 mux_tree_tapbuf_size10_9_sram[1]:20 0.0004263393 +10 mux_tree_tapbuf_size10_9_sram[1]:22 mux_tree_tapbuf_size10_9_sram[1]:21 0.0045 +11 mux_tree_tapbuf_size10_9_sram[1]:20 mux_left_track_9\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_9_sram[1]:17 mux_tree_tapbuf_size10_9_sram[1]:16 0.0045 +13 mux_tree_tapbuf_size10_9_sram[1]:17 mux_tree_tapbuf_size10_9_sram[1]:12 0.005299107 +14 mux_tree_tapbuf_size10_9_sram[1]:16 mux_tree_tapbuf_size10_9_sram[1]:15 0.0004107143 +15 mux_tree_tapbuf_size10_9_sram[1]:13 mux_left_track_9\/mux_l2_in_2_:S 0.152 +16 mux_tree_tapbuf_size10_9_sram[1]:14 mux_tree_tapbuf_size10_9_sram[1]:13 0.0045 +17 mux_tree_tapbuf_size10_9_sram[1]:6 mux_left_track_9\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size10_9_sram[1]:18 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +19 mux_tree_tapbuf_size10_9_sram[1]:18 mux_tree_tapbuf_size10_9_sram[1]:17 0.0001793478 +20 mux_tree_tapbuf_size10_9_sram[1]:10 mux_tree_tapbuf_size10_9_sram[1]:9 0.0045 +21 mux_tree_tapbuf_size10_9_sram[1]:9 mux_tree_tapbuf_size10_9_sram[1]:8 0.001741071 +22 mux_tree_tapbuf_size10_9_sram[1]:7 mux_left_track_9\/mux_l2_in_1_:S 0.152 +23 mux_tree_tapbuf_size10_9_sram[1]:8 mux_tree_tapbuf_size10_9_sram[1]:7 0.0045 +24 mux_tree_tapbuf_size10_9_sram[1]:25 mux_tree_tapbuf_size10_9_sram[1]:24 0.0004107143 +25 mux_tree_tapbuf_size10_9_sram[1]:26 mux_tree_tapbuf_size10_9_sram[1]:25 0.0003035715 +26 mux_tree_tapbuf_size10_9_sram[1]:27 mux_tree_tapbuf_size10_9_sram[1]:26 0.0004107143 +27 mux_tree_tapbuf_size10_9_sram[1]:19 mux_tree_tapbuf_size10_9_sram[1]:18 0.0003035715 +28 mux_tree_tapbuf_size10_9_sram[1]:12 mux_tree_tapbuf_size10_9_sram[1]:11 0.0009107143 +29 mux_tree_tapbuf_size10_9_sram[1]:11 mux_tree_tapbuf_size10_9_sram[1]:10 0.0003705357 +30 mux_tree_tapbuf_size10_9_sram[1]:11 mux_tree_tapbuf_size10_9_sram[1]:6 0.004162947 +31 mux_tree_tapbuf_size10_9_sram[1]:15 mux_tree_tapbuf_size10_9_sram[1]:14 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size12_1_sram[1] 0.007867712 //LENGTH 59.900 LUMPCC 0.0004193299 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 68.845 102.340 +*I mux_top_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 55.760 101.320 +*I mux_top_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 60.820 95.880 +*I mux_top_track_2\/mux_l2_in_3_:S I *L 0.00357 *C 52.100 95.880 +*I mux_top_track_2\/mux_l2_in_2_:S I *L 0.00357 *C 55.760 90.440 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 47.555 104.380 +*N mux_tree_tapbuf_size12_1_sram[1]:6 *C 47.593 104.380 +*N mux_tree_tapbuf_size12_1_sram[1]:7 *C 48.300 104.380 +*N mux_tree_tapbuf_size12_1_sram[1]:8 *C 48.300 104.040 +*N mux_tree_tapbuf_size12_1_sram[1]:9 *C 55.797 90.440 +*N mux_tree_tapbuf_size12_1_sram[1]:10 *C 59.295 90.440 +*N mux_tree_tapbuf_size12_1_sram[1]:11 *C 59.340 90.485 +*N mux_tree_tapbuf_size12_1_sram[1]:12 *C 52.138 95.880 +*N mux_tree_tapbuf_size12_1_sram[1]:13 *C 54.695 95.880 +*N mux_tree_tapbuf_size12_1_sram[1]:14 *C 54.740 95.835 +*N mux_tree_tapbuf_size12_1_sram[1]:15 *C 54.740 94.565 +*N mux_tree_tapbuf_size12_1_sram[1]:16 *C 54.785 94.520 +*N mux_tree_tapbuf_size12_1_sram[1]:17 *C 59.295 94.520 +*N mux_tree_tapbuf_size12_1_sram[1]:18 *C 59.340 94.520 +*N mux_tree_tapbuf_size12_1_sram[1]:19 *C 60.820 95.880 +*N mux_tree_tapbuf_size12_1_sram[1]:20 *C 60.720 96.220 +*N mux_tree_tapbuf_size12_1_sram[1]:21 *C 59.385 96.220 +*N mux_tree_tapbuf_size12_1_sram[1]:22 *C 59.340 96.220 +*N mux_tree_tapbuf_size12_1_sram[1]:23 *C 59.340 101.660 +*N mux_tree_tapbuf_size12_1_sram[1]:24 *C 55.797 101.320 +*N mux_tree_tapbuf_size12_1_sram[1]:25 *C 58.880 101.320 +*N mux_tree_tapbuf_size12_1_sram[1]:26 *C 58.880 101.660 +*N mux_tree_tapbuf_size12_1_sram[1]:27 *C 58.880 101.660 +*N mux_tree_tapbuf_size12_1_sram[1]:28 *C 58.880 103.995 +*N mux_tree_tapbuf_size12_1_sram[1]:29 *C 58.880 104.070 +*N mux_tree_tapbuf_size12_1_sram[1]:30 *C 58.880 104.380 +*N mux_tree_tapbuf_size12_1_sram[1]:31 *C 65.275 104.380 +*N mux_tree_tapbuf_size12_1_sram[1]:32 *C 65.320 104.335 +*N mux_tree_tapbuf_size12_1_sram[1]:33 *C 65.320 102.385 +*N mux_tree_tapbuf_size12_1_sram[1]:34 *C 65.365 102.340 +*N mux_tree_tapbuf_size12_1_sram[1]:35 *C 68.808 102.340 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_2\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_2\/mux_l2_in_3_:S 1e-06 +4 mux_top_track_2\/mux_l2_in_2_:S 1e-06 +5 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size12_1_sram[1]:6 6.812312e-05 +7 mux_tree_tapbuf_size12_1_sram[1]:7 9.393694e-05 +8 mux_tree_tapbuf_size12_1_sram[1]:8 0.0007357187 +9 mux_tree_tapbuf_size12_1_sram[1]:9 0.0002253365 +10 mux_tree_tapbuf_size12_1_sram[1]:10 0.0002253365 +11 mux_tree_tapbuf_size12_1_sram[1]:11 0.0002742842 +12 mux_tree_tapbuf_size12_1_sram[1]:12 0.0002055005 +13 mux_tree_tapbuf_size12_1_sram[1]:13 0.0002055005 +14 mux_tree_tapbuf_size12_1_sram[1]:14 0.0001005726 +15 mux_tree_tapbuf_size12_1_sram[1]:15 0.0001005726 +16 mux_tree_tapbuf_size12_1_sram[1]:16 0.0003146005 +17 mux_tree_tapbuf_size12_1_sram[1]:17 0.0003146005 +18 mux_tree_tapbuf_size12_1_sram[1]:18 0.0004037411 +19 mux_tree_tapbuf_size12_1_sram[1]:19 6.241197e-05 +20 mux_tree_tapbuf_size12_1_sram[1]:20 0.0001436561 +21 mux_tree_tapbuf_size12_1_sram[1]:21 0.0001134726 +22 mux_tree_tapbuf_size12_1_sram[1]:22 0.0004430902 +23 mux_tree_tapbuf_size12_1_sram[1]:23 0.0003467419 +24 mux_tree_tapbuf_size12_1_sram[1]:24 0.0002390434 +25 mux_tree_tapbuf_size12_1_sram[1]:25 0.0002688197 +26 mux_tree_tapbuf_size12_1_sram[1]:26 6.482088e-05 +27 mux_tree_tapbuf_size12_1_sram[1]:27 0.0001887129 +28 mux_tree_tapbuf_size12_1_sram[1]:28 0.0001552879 +29 mux_tree_tapbuf_size12_1_sram[1]:29 0.0007406049 +30 mux_tree_tapbuf_size12_1_sram[1]:30 0.0003372318 +31 mux_tree_tapbuf_size12_1_sram[1]:31 0.0003065318 +32 mux_tree_tapbuf_size12_1_sram[1]:32 0.0001418969 +33 mux_tree_tapbuf_size12_1_sram[1]:33 0.0001418969 +34 mux_tree_tapbuf_size12_1_sram[1]:34 0.0002401686 +35 mux_tree_tapbuf_size12_1_sram[1]:35 0.0002401686 +36 mux_tree_tapbuf_size12_1_sram[1]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.411601e-05 +37 mux_tree_tapbuf_size12_1_sram[1]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.411601e-05 +38 mux_tree_tapbuf_size12_1_sram[1]:31 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001455489 +39 mux_tree_tapbuf_size12_1_sram[1]:30 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001455489 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size12_1_sram[1]:35 0.152 +1 mux_tree_tapbuf_size12_1_sram[1]:12 mux_top_track_2\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size12_1_sram[1]:13 mux_tree_tapbuf_size12_1_sram[1]:12 0.002283482 +3 mux_tree_tapbuf_size12_1_sram[1]:14 mux_tree_tapbuf_size12_1_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size12_1_sram[1]:16 mux_tree_tapbuf_size12_1_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size12_1_sram[1]:15 mux_tree_tapbuf_size12_1_sram[1]:14 0.001133929 +6 mux_tree_tapbuf_size12_1_sram[1]:17 mux_tree_tapbuf_size12_1_sram[1]:16 0.004026786 +7 mux_tree_tapbuf_size12_1_sram[1]:18 mux_tree_tapbuf_size12_1_sram[1]:17 0.0045 +8 mux_tree_tapbuf_size12_1_sram[1]:18 mux_tree_tapbuf_size12_1_sram[1]:11 0.003602679 +9 mux_tree_tapbuf_size12_1_sram[1]:10 mux_tree_tapbuf_size12_1_sram[1]:9 0.003122768 +10 mux_tree_tapbuf_size12_1_sram[1]:11 mux_tree_tapbuf_size12_1_sram[1]:10 0.0045 +11 mux_tree_tapbuf_size12_1_sram[1]:9 mux_top_track_2\/mux_l2_in_2_:S 0.152 +12 mux_tree_tapbuf_size12_1_sram[1]:29 mux_tree_tapbuf_size12_1_sram[1]:28 0.0045 +13 mux_tree_tapbuf_size12_1_sram[1]:29 mux_tree_tapbuf_size12_1_sram[1]:8 0.009446429 +14 mux_tree_tapbuf_size12_1_sram[1]:28 mux_tree_tapbuf_size12_1_sram[1]:27 0.002084821 +15 mux_tree_tapbuf_size12_1_sram[1]:6 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size12_1_sram[1]:31 mux_tree_tapbuf_size12_1_sram[1]:30 0.005709822 +17 mux_tree_tapbuf_size12_1_sram[1]:32 mux_tree_tapbuf_size12_1_sram[1]:31 0.0045 +18 mux_tree_tapbuf_size12_1_sram[1]:34 mux_tree_tapbuf_size12_1_sram[1]:33 0.0045 +19 mux_tree_tapbuf_size12_1_sram[1]:33 mux_tree_tapbuf_size12_1_sram[1]:32 0.001741071 +20 mux_tree_tapbuf_size12_1_sram[1]:35 mux_tree_tapbuf_size12_1_sram[1]:34 0.003073661 +21 mux_tree_tapbuf_size12_1_sram[1]:21 mux_tree_tapbuf_size12_1_sram[1]:20 0.001191964 +22 mux_tree_tapbuf_size12_1_sram[1]:22 mux_tree_tapbuf_size12_1_sram[1]:21 0.0045 +23 mux_tree_tapbuf_size12_1_sram[1]:22 mux_tree_tapbuf_size12_1_sram[1]:18 0.001517857 +24 mux_tree_tapbuf_size12_1_sram[1]:19 mux_top_track_2\/mux_l2_in_1_:S 0.152 +25 mux_tree_tapbuf_size12_1_sram[1]:26 mux_tree_tapbuf_size12_1_sram[1]:25 0.0003035715 +26 mux_tree_tapbuf_size12_1_sram[1]:27 mux_tree_tapbuf_size12_1_sram[1]:26 0.0045 +27 mux_tree_tapbuf_size12_1_sram[1]:27 mux_tree_tapbuf_size12_1_sram[1]:23 0.0004107143 +28 mux_tree_tapbuf_size12_1_sram[1]:24 mux_top_track_2\/mux_l2_in_0_:S 0.152 +29 mux_tree_tapbuf_size12_1_sram[1]:7 mux_tree_tapbuf_size12_1_sram[1]:6 0.0006316964 +30 mux_tree_tapbuf_size12_1_sram[1]:8 mux_tree_tapbuf_size12_1_sram[1]:7 0.0003035715 +31 mux_tree_tapbuf_size12_1_sram[1]:25 mux_tree_tapbuf_size12_1_sram[1]:24 0.002752232 +32 mux_tree_tapbuf_size12_1_sram[1]:30 mux_tree_tapbuf_size12_1_sram[1]:29 0.0002767857 +33 mux_tree_tapbuf_size12_1_sram[1]:20 mux_tree_tapbuf_size12_1_sram[1]:19 0.0003035715 +34 mux_tree_tapbuf_size12_1_sram[1]:23 mux_tree_tapbuf_size12_1_sram[1]:22 0.004857143 + +*END + +*D_NET mux_tree_tapbuf_size12_5_sram[0] 0.01140848 //LENGTH 89.022 LUMPCC 0.0003066516 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 81.625 15.640 +*I mux_bottom_track_3\/mux_l1_in_2_:S I *L 0.00357 *C 61.740 25.550 +*I mux_bottom_track_3\/mux_l1_in_4_:S I *L 0.00357 *C 42.220 28.560 +*I mux_bottom_track_3\/mux_l1_in_3_:S I *L 0.00357 *C 49.120 25.160 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 49.855 20.740 +*I mux_bottom_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 70.020 28.855 +*I mux_bottom_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 70.940 41.480 +*N mux_tree_tapbuf_size12_5_sram[0]:7 *C 70.955 41.480 +*N mux_tree_tapbuf_size12_5_sram[0]:8 *C 71.278 41.480 +*N mux_tree_tapbuf_size12_5_sram[0]:9 *C 71.300 41.435 +*N mux_tree_tapbuf_size12_5_sram[0]:10 *C 70.020 28.855 +*N mux_tree_tapbuf_size12_5_sram[0]:11 *C 49.855 20.740 +*N mux_tree_tapbuf_size12_5_sram[0]:12 *C 50.140 20.740 +*N mux_tree_tapbuf_size12_5_sram[0]:13 *C 50.140 20.785 +*N mux_tree_tapbuf_size12_5_sram[0]:14 *C 49.157 25.160 +*N mux_tree_tapbuf_size12_5_sram[0]:15 *C 50.095 25.160 +*N mux_tree_tapbuf_size12_5_sram[0]:16 *C 50.140 25.160 +*N mux_tree_tapbuf_size12_5_sram[0]:17 *C 42.183 28.560 +*N mux_tree_tapbuf_size12_5_sram[0]:18 *C 40.525 28.560 +*N mux_tree_tapbuf_size12_5_sram[0]:19 *C 40.480 28.515 +*N mux_tree_tapbuf_size12_5_sram[0]:20 *C 40.480 26.578 +*N mux_tree_tapbuf_size12_5_sram[0]:21 *C 40.488 26.520 +*N mux_tree_tapbuf_size12_5_sram[0]:22 *C 50.133 26.520 +*N mux_tree_tapbuf_size12_5_sram[0]:23 *C 50.140 26.520 +*N mux_tree_tapbuf_size12_5_sram[0]:24 *C 50.185 26.520 +*N mux_tree_tapbuf_size12_5_sram[0]:25 *C 61.595 26.520 +*N mux_tree_tapbuf_size12_5_sram[0]:26 *C 61.640 26.475 +*N mux_tree_tapbuf_size12_5_sram[0]:27 *C 61.640 25.885 +*N mux_tree_tapbuf_size12_5_sram[0]:28 *C 61.640 25.840 +*N mux_tree_tapbuf_size12_5_sram[0]:29 *C 61.740 25.550 +*N mux_tree_tapbuf_size12_5_sram[0]:30 *C 61.740 25.160 +*N mux_tree_tapbuf_size12_5_sram[0]:31 *C 66.195 25.160 +*N mux_tree_tapbuf_size12_5_sram[0]:32 *C 66.240 25.205 +*N mux_tree_tapbuf_size12_5_sram[0]:33 *C 66.240 29.195 +*N mux_tree_tapbuf_size12_5_sram[0]:34 *C 66.285 29.240 +*N mux_tree_tapbuf_size12_5_sram[0]:35 *C 70.020 29.240 +*N mux_tree_tapbuf_size12_5_sram[0]:36 *C 71.255 29.240 +*N mux_tree_tapbuf_size12_5_sram[0]:37 *C 71.300 29.240 +*N mux_tree_tapbuf_size12_5_sram[0]:38 *C 71.300 17.385 +*N mux_tree_tapbuf_size12_5_sram[0]:39 *C 71.345 17.340 +*N mux_tree_tapbuf_size12_5_sram[0]:40 *C 80.915 17.340 +*N mux_tree_tapbuf_size12_5_sram[0]:41 *C 80.960 17.295 +*N mux_tree_tapbuf_size12_5_sram[0]:42 *C 80.960 15.685 +*N mux_tree_tapbuf_size12_5_sram[0]:43 *C 81.005 15.640 +*N mux_tree_tapbuf_size12_5_sram[0]:44 *C 81.588 15.640 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_3\/mux_l1_in_2_:S 1e-06 +2 mux_bottom_track_3\/mux_l1_in_4_:S 1e-06 +3 mux_bottom_track_3\/mux_l1_in_3_:S 1e-06 +4 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_bottom_track_3\/mux_l1_in_0_:S 1e-06 +6 mux_bottom_track_3\/mux_l1_in_1_:S 1e-06 +7 mux_tree_tapbuf_size12_5_sram[0]:7 5.193384e-05 +8 mux_tree_tapbuf_size12_5_sram[0]:8 5.193384e-05 +9 mux_tree_tapbuf_size12_5_sram[0]:9 0.0007586708 +10 mux_tree_tapbuf_size12_5_sram[0]:10 6.181906e-05 +11 mux_tree_tapbuf_size12_5_sram[0]:11 4.66987e-05 +12 mux_tree_tapbuf_size12_5_sram[0]:12 5.231283e-05 +13 mux_tree_tapbuf_size12_5_sram[0]:13 0.0002412071 +14 mux_tree_tapbuf_size12_5_sram[0]:14 0.0001063028 +15 mux_tree_tapbuf_size12_5_sram[0]:15 0.0001063028 +16 mux_tree_tapbuf_size12_5_sram[0]:16 0.0003376691 +17 mux_tree_tapbuf_size12_5_sram[0]:17 0.0001310653 +18 mux_tree_tapbuf_size12_5_sram[0]:18 0.0001310653 +19 mux_tree_tapbuf_size12_5_sram[0]:19 9.364232e-05 +20 mux_tree_tapbuf_size12_5_sram[0]:20 9.364232e-05 +21 mux_tree_tapbuf_size12_5_sram[0]:21 0.0007179804 +22 mux_tree_tapbuf_size12_5_sram[0]:22 0.0007179804 +23 mux_tree_tapbuf_size12_5_sram[0]:23 0.0001008612 +24 mux_tree_tapbuf_size12_5_sram[0]:24 0.0007328873 +25 mux_tree_tapbuf_size12_5_sram[0]:25 0.0007328873 +26 mux_tree_tapbuf_size12_5_sram[0]:26 5.769076e-05 +27 mux_tree_tapbuf_size12_5_sram[0]:27 5.769076e-05 +28 mux_tree_tapbuf_size12_5_sram[0]:28 6.132302e-05 +29 mux_tree_tapbuf_size12_5_sram[0]:29 8.646498e-05 +30 mux_tree_tapbuf_size12_5_sram[0]:30 0.0003549748 +31 mux_tree_tapbuf_size12_5_sram[0]:31 0.0003256471 +32 mux_tree_tapbuf_size12_5_sram[0]:32 0.0002384668 +33 mux_tree_tapbuf_size12_5_sram[0]:33 0.0002384668 +34 mux_tree_tapbuf_size12_5_sram[0]:34 0.0002665512 +35 mux_tree_tapbuf_size12_5_sram[0]:35 0.0003985182 +36 mux_tree_tapbuf_size12_5_sram[0]:36 0.0001003757 +37 mux_tree_tapbuf_size12_5_sram[0]:37 0.001468292 +38 mux_tree_tapbuf_size12_5_sram[0]:38 0.0006719409 +39 mux_tree_tapbuf_size12_5_sram[0]:39 0.0005785255 +40 mux_tree_tapbuf_size12_5_sram[0]:40 0.0005785255 +41 mux_tree_tapbuf_size12_5_sram[0]:41 0.0001091068 +42 mux_tree_tapbuf_size12_5_sram[0]:42 0.0001091068 +43 mux_tree_tapbuf_size12_5_sram[0]:43 6.31509e-05 +44 mux_tree_tapbuf_size12_5_sram[0]:44 6.31509e-05 +45 mux_tree_tapbuf_size12_5_sram[0]:24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 9.333182e-05 +46 mux_tree_tapbuf_size12_5_sram[0]:25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.333182e-05 +47 mux_tree_tapbuf_size12_5_sram[0]:20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 5.999398e-05 +48 mux_tree_tapbuf_size12_5_sram[0]:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 5.999398e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_5_sram[0]:44 0.152 +1 mux_tree_tapbuf_size12_5_sram[0]:39 mux_tree_tapbuf_size12_5_sram[0]:38 0.0045 +2 mux_tree_tapbuf_size12_5_sram[0]:38 mux_tree_tapbuf_size12_5_sram[0]:37 0.01058482 +3 mux_tree_tapbuf_size12_5_sram[0]:40 mux_tree_tapbuf_size12_5_sram[0]:39 0.008544643 +4 mux_tree_tapbuf_size12_5_sram[0]:41 mux_tree_tapbuf_size12_5_sram[0]:40 0.0045 +5 mux_tree_tapbuf_size12_5_sram[0]:43 mux_tree_tapbuf_size12_5_sram[0]:42 0.0045 +6 mux_tree_tapbuf_size12_5_sram[0]:42 mux_tree_tapbuf_size12_5_sram[0]:41 0.0014375 +7 mux_tree_tapbuf_size12_5_sram[0]:44 mux_tree_tapbuf_size12_5_sram[0]:43 0.0005200892 +8 mux_tree_tapbuf_size12_5_sram[0]:23 mux_tree_tapbuf_size12_5_sram[0]:22 0.00341 +9 mux_tree_tapbuf_size12_5_sram[0]:23 mux_tree_tapbuf_size12_5_sram[0]:16 0.001214286 +10 mux_tree_tapbuf_size12_5_sram[0]:22 mux_tree_tapbuf_size12_5_sram[0]:21 0.00151105 +11 mux_tree_tapbuf_size12_5_sram[0]:20 mux_tree_tapbuf_size12_5_sram[0]:19 0.001729911 +12 mux_tree_tapbuf_size12_5_sram[0]:21 mux_tree_tapbuf_size12_5_sram[0]:20 0.00341 +13 mux_tree_tapbuf_size12_5_sram[0]:18 mux_tree_tapbuf_size12_5_sram[0]:17 0.001479911 +14 mux_tree_tapbuf_size12_5_sram[0]:19 mux_tree_tapbuf_size12_5_sram[0]:18 0.0045 +15 mux_tree_tapbuf_size12_5_sram[0]:17 mux_bottom_track_3\/mux_l1_in_4_:S 0.152 +16 mux_tree_tapbuf_size12_5_sram[0]:24 mux_tree_tapbuf_size12_5_sram[0]:23 0.0045 +17 mux_tree_tapbuf_size12_5_sram[0]:25 mux_tree_tapbuf_size12_5_sram[0]:24 0.0101875 +18 mux_tree_tapbuf_size12_5_sram[0]:26 mux_tree_tapbuf_size12_5_sram[0]:25 0.0045 +19 mux_tree_tapbuf_size12_5_sram[0]:28 mux_tree_tapbuf_size12_5_sram[0]:27 0.0045 +20 mux_tree_tapbuf_size12_5_sram[0]:27 mux_tree_tapbuf_size12_5_sram[0]:26 0.0005267857 +21 mux_tree_tapbuf_size12_5_sram[0]:31 mux_tree_tapbuf_size12_5_sram[0]:30 0.003977679 +22 mux_tree_tapbuf_size12_5_sram[0]:32 mux_tree_tapbuf_size12_5_sram[0]:31 0.0045 +23 mux_tree_tapbuf_size12_5_sram[0]:34 mux_tree_tapbuf_size12_5_sram[0]:33 0.0045 +24 mux_tree_tapbuf_size12_5_sram[0]:33 mux_tree_tapbuf_size12_5_sram[0]:32 0.0035625 +25 mux_tree_tapbuf_size12_5_sram[0]:36 mux_tree_tapbuf_size12_5_sram[0]:35 0.001102679 +26 mux_tree_tapbuf_size12_5_sram[0]:37 mux_tree_tapbuf_size12_5_sram[0]:36 0.0045 +27 mux_tree_tapbuf_size12_5_sram[0]:37 mux_tree_tapbuf_size12_5_sram[0]:9 0.01088839 +28 mux_tree_tapbuf_size12_5_sram[0]:8 mux_tree_tapbuf_size12_5_sram[0]:7 0.0001752718 +29 mux_tree_tapbuf_size12_5_sram[0]:9 mux_tree_tapbuf_size12_5_sram[0]:8 0.0045 +30 mux_tree_tapbuf_size12_5_sram[0]:7 mux_bottom_track_3\/mux_l1_in_1_:S 0.152 +31 mux_tree_tapbuf_size12_5_sram[0]:15 mux_tree_tapbuf_size12_5_sram[0]:14 0.0008370536 +32 mux_tree_tapbuf_size12_5_sram[0]:16 mux_tree_tapbuf_size12_5_sram[0]:15 0.0045 +33 mux_tree_tapbuf_size12_5_sram[0]:16 mux_tree_tapbuf_size12_5_sram[0]:13 0.00390625 +34 mux_tree_tapbuf_size12_5_sram[0]:14 mux_bottom_track_3\/mux_l1_in_3_:S 0.152 +35 mux_tree_tapbuf_size12_5_sram[0]:29 mux_bottom_track_3\/mux_l1_in_2_:S 0.152 +36 mux_tree_tapbuf_size12_5_sram[0]:29 mux_tree_tapbuf_size12_5_sram[0]:28 0.0001686047 +37 mux_tree_tapbuf_size12_5_sram[0]:10 mux_bottom_track_3\/mux_l1_in_0_:S 0.152 +38 mux_tree_tapbuf_size12_5_sram[0]:12 mux_tree_tapbuf_size12_5_sram[0]:11 0.0001548913 +39 mux_tree_tapbuf_size12_5_sram[0]:13 mux_tree_tapbuf_size12_5_sram[0]:12 0.0045 +40 mux_tree_tapbuf_size12_5_sram[0]:11 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +41 mux_tree_tapbuf_size12_5_sram[0]:30 mux_tree_tapbuf_size12_5_sram[0]:29 0.0003482143 +42 mux_tree_tapbuf_size12_5_sram[0]:35 mux_tree_tapbuf_size12_5_sram[0]:34 0.003334821 +43 mux_tree_tapbuf_size12_5_sram[0]:35 mux_tree_tapbuf_size12_5_sram[0]:10 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size16_0_sram[1] 0.01436782 //LENGTH 106.035 LUMPCC 0.001804724 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 44.925 120.700 +*I mux_top_track_4\/mux_l2_in_2_:S I *L 0.00357 *C 34.860 112.880 +*I mux_top_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 34.860 123.470 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 34.140 126.480 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.835 115.260 +*I mux_top_track_4\/mux_l2_in_3_:S I *L 0.00357 *C 38.740 107.440 +*I mux_top_track_4\/mux_l2_in_5_:S I *L 0.00357 *C 54.840 85.000 +*I mux_top_track_4\/mux_l2_in_4_:S I *L 0.00357 *C 39.460 85.000 +*I mux_top_track_4\/mux_l2_in_7_:S I *L 0.00357 *C 39.200 79.950 +*I mux_top_track_4\/mux_l2_in_6_:S I *L 0.00357 *C 35.780 79.900 +*N mux_tree_tapbuf_size16_0_sram[1]:10 *C 39.150 79.900 +*N mux_tree_tapbuf_size16_0_sram[1]:11 *C 35.818 79.900 +*N mux_tree_tapbuf_size16_0_sram[1]:12 *C 39.460 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:13 *C 54.803 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:14 *C 50.645 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:15 *C 50.600 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:16 *C 50.593 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:17 *C 39.568 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:18 *C 39.560 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:19 *C 39.100 85.000 +*N mux_tree_tapbuf_size16_0_sram[1]:20 *C 39.100 79.945 +*N mux_tree_tapbuf_size16_0_sram[1]:21 *C 39.200 79.903 +*N mux_tree_tapbuf_size16_0_sram[1]:22 *C 39.200 79.560 +*N mux_tree_tapbuf_size16_0_sram[1]:23 *C 40.895 79.560 +*N mux_tree_tapbuf_size16_0_sram[1]:24 *C 40.940 79.605 +*N mux_tree_tapbuf_size16_0_sram[1]:25 *C 38.778 107.440 +*N mux_tree_tapbuf_size16_0_sram[1]:26 *C 40.480 107.440 +*N mux_tree_tapbuf_size16_0_sram[1]:27 *C 40.480 107.780 +*N mux_tree_tapbuf_size16_0_sram[1]:28 *C 40.895 107.780 +*N mux_tree_tapbuf_size16_0_sram[1]:29 *C 40.940 107.780 +*N mux_tree_tapbuf_size16_0_sram[1]:30 *C 32.873 115.260 +*N mux_tree_tapbuf_size16_0_sram[1]:31 *C 34.500 115.260 +*N mux_tree_tapbuf_size16_0_sram[1]:32 *C 34.102 126.480 +*N mux_tree_tapbuf_size16_0_sram[1]:33 *C 32.705 126.480 +*N mux_tree_tapbuf_size16_0_sram[1]:34 *C 32.660 126.435 +*N mux_tree_tapbuf_size16_0_sram[1]:35 *C 32.660 123.805 +*N mux_tree_tapbuf_size16_0_sram[1]:36 *C 32.705 123.760 +*N mux_tree_tapbuf_size16_0_sram[1]:37 *C 34.803 123.760 +*N mux_tree_tapbuf_size16_0_sram[1]:38 *C 34.860 123.470 +*N mux_tree_tapbuf_size16_0_sram[1]:39 *C 34.860 123.125 +*N mux_tree_tapbuf_size16_0_sram[1]:40 *C 34.530 123.110 +*N mux_tree_tapbuf_size16_0_sram[1]:41 *C 34.500 123.035 +*N mux_tree_tapbuf_size16_0_sram[1]:42 *C 34.845 112.880 +*N mux_tree_tapbuf_size16_0_sram[1]:43 *C 34.523 112.880 +*N mux_tree_tapbuf_size16_0_sram[1]:44 *C 34.500 112.925 +*N mux_tree_tapbuf_size16_0_sram[1]:45 *C 34.500 114.920 +*N mux_tree_tapbuf_size16_0_sram[1]:46 *C 34.500 114.920 +*N mux_tree_tapbuf_size16_0_sram[1]:47 *C 40.895 114.920 +*N mux_tree_tapbuf_size16_0_sram[1]:48 *C 40.940 114.920 +*N mux_tree_tapbuf_size16_0_sram[1]:49 *C 40.940 120.655 +*N mux_tree_tapbuf_size16_0_sram[1]:50 *C 40.985 120.700 +*N mux_tree_tapbuf_size16_0_sram[1]:51 *C 44.888 120.700 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_4\/mux_l2_in_2_:S 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +4 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_top_track_4\/mux_l2_in_3_:S 1e-06 +6 mux_top_track_4\/mux_l2_in_5_:S 1e-06 +7 mux_top_track_4\/mux_l2_in_4_:S 1e-06 +8 mux_top_track_4\/mux_l2_in_7_:S 1e-06 +9 mux_top_track_4\/mux_l2_in_6_:S 1e-06 +10 mux_tree_tapbuf_size16_0_sram[1]:10 2.106221e-05 +11 mux_tree_tapbuf_size16_0_sram[1]:11 0.0002209805 +12 mux_tree_tapbuf_size16_0_sram[1]:12 3.114654e-05 +13 mux_tree_tapbuf_size16_0_sram[1]:13 0.0002589994 +14 mux_tree_tapbuf_size16_0_sram[1]:14 0.0002589994 +15 mux_tree_tapbuf_size16_0_sram[1]:15 4.069342e-05 +16 mux_tree_tapbuf_size16_0_sram[1]:16 0.0009152083 +17 mux_tree_tapbuf_size16_0_sram[1]:17 0.0009152083 +18 mux_tree_tapbuf_size16_0_sram[1]:18 7.022873e-05 +19 mux_tree_tapbuf_size16_0_sram[1]:19 0.0002514647 +20 mux_tree_tapbuf_size16_0_sram[1]:20 0.0002206433 +21 mux_tree_tapbuf_size16_0_sram[1]:21 0.0002622856 +22 mux_tree_tapbuf_size16_0_sram[1]:22 0.0001618684 +23 mux_tree_tapbuf_size16_0_sram[1]:23 0.0001416256 +24 mux_tree_tapbuf_size16_0_sram[1]:24 0.001469818 +25 mux_tree_tapbuf_size16_0_sram[1]:25 0.0001354689 +26 mux_tree_tapbuf_size16_0_sram[1]:26 0.0001610266 +27 mux_tree_tapbuf_size16_0_sram[1]:27 7.666109e-05 +28 mux_tree_tapbuf_size16_0_sram[1]:28 5.110344e-05 +29 mux_tree_tapbuf_size16_0_sram[1]:29 0.001809251 +30 mux_tree_tapbuf_size16_0_sram[1]:30 0.0001326794 +31 mux_tree_tapbuf_size16_0_sram[1]:31 0.0001615281 +32 mux_tree_tapbuf_size16_0_sram[1]:32 0.0001073965 +33 mux_tree_tapbuf_size16_0_sram[1]:33 0.0001073965 +34 mux_tree_tapbuf_size16_0_sram[1]:34 0.0001377944 +35 mux_tree_tapbuf_size16_0_sram[1]:35 0.0001377944 +36 mux_tree_tapbuf_size16_0_sram[1]:36 0.0002111007 +37 mux_tree_tapbuf_size16_0_sram[1]:37 0.0002380641 +38 mux_tree_tapbuf_size16_0_sram[1]:38 8.497821e-05 +39 mux_tree_tapbuf_size16_0_sram[1]:39 8.535029e-05 +40 mux_tree_tapbuf_size16_0_sram[1]:40 5.543455e-05 +41 mux_tree_tapbuf_size16_0_sram[1]:41 0.0003585684 +42 mux_tree_tapbuf_size16_0_sram[1]:42 5.584541e-05 +43 mux_tree_tapbuf_size16_0_sram[1]:43 5.584541e-05 +44 mux_tree_tapbuf_size16_0_sram[1]:44 0.0001357482 +45 mux_tree_tapbuf_size16_0_sram[1]:45 0.0005265088 +46 mux_tree_tapbuf_size16_0_sram[1]:46 0.0005283472 +47 mux_tree_tapbuf_size16_0_sram[1]:47 0.0004994984 +48 mux_tree_tapbuf_size16_0_sram[1]:48 0.0005600031 +49 mux_tree_tapbuf_size16_0_sram[1]:49 0.0002256917 +50 mux_tree_tapbuf_size16_0_sram[1]:50 0.0003368928 +51 mux_tree_tapbuf_size16_0_sram[1]:51 0.0003368928 +52 mux_tree_tapbuf_size16_0_sram[1]:24 chanx_right_in[14]:16 1.144353e-07 +53 mux_tree_tapbuf_size16_0_sram[1]:24 chanx_right_in[14]:20 5.542402e-05 +54 mux_tree_tapbuf_size16_0_sram[1]:24 chanx_right_in[14]:23 9.860122e-05 +55 mux_tree_tapbuf_size16_0_sram[1]:20 chanx_right_in[14]:16 0.0001314064 +56 mux_tree_tapbuf_size16_0_sram[1]:18 chanx_right_in[14]:19 6.244349e-06 +57 mux_tree_tapbuf_size16_0_sram[1]:29 chanx_right_in[14]:17 1.144353e-07 +58 mux_tree_tapbuf_size16_0_sram[1]:29 chanx_right_in[14]:23 5.542402e-05 +59 mux_tree_tapbuf_size16_0_sram[1]:29 chanx_right_in[14]:24 9.860122e-05 +60 mux_tree_tapbuf_size16_0_sram[1]:19 chanx_right_in[14]:17 0.0001314064 +61 mux_tree_tapbuf_size16_0_sram[1]:19 chanx_right_in[14]:18 6.244349e-06 +62 mux_tree_tapbuf_size16_0_sram[1]:29 top_left_grid_pin_35_[0]:13 0.0001149538 +63 mux_tree_tapbuf_size16_0_sram[1]:48 top_left_grid_pin_35_[0]:13 0.000155052 +64 mux_tree_tapbuf_size16_0_sram[1]:48 top_left_grid_pin_35_[0]:16 0.0001149538 +65 mux_tree_tapbuf_size16_0_sram[1]:49 top_left_grid_pin_35_[0]:16 0.000155052 +66 mux_tree_tapbuf_size16_0_sram[1]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.81005e-05 +67 mux_tree_tapbuf_size16_0_sram[1]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 2.548798e-05 +68 mux_tree_tapbuf_size16_0_sram[1]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 2.548798e-05 +69 mux_tree_tapbuf_size16_0_sram[1]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.81005e-05 +70 mux_tree_tapbuf_size16_0_sram[1]:24 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 9.615235e-05 +71 mux_tree_tapbuf_size16_0_sram[1]:29 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 9.615235e-05 +72 mux_tree_tapbuf_size16_0_sram[1]:41 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.895746e-05 +73 mux_tree_tapbuf_size16_0_sram[1]:45 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.895746e-05 +74 mux_tree_tapbuf_size16_0_sram[1]:32 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.096709e-06 +75 mux_tree_tapbuf_size16_0_sram[1]:33 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.096709e-06 +76 mux_tree_tapbuf_size16_0_sram[1]:34 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.575747e-05 +77 mux_tree_tapbuf_size16_0_sram[1]:35 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.575747e-05 +78 mux_tree_tapbuf_size16_0_sram[1]:41 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.817215e-05 +79 mux_tree_tapbuf_size16_0_sram[1]:41 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.184134e-05 +80 mux_tree_tapbuf_size16_0_sram[1]:45 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.184134e-05 +81 mux_tree_tapbuf_size16_0_sram[1]:45 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.817215e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size16_0_sram[1]:51 0.152 +1 mux_tree_tapbuf_size16_0_sram[1]:42 mux_top_track_4\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size16_0_sram[1]:43 mux_tree_tapbuf_size16_0_sram[1]:42 0.0001752718 +3 mux_tree_tapbuf_size16_0_sram[1]:44 mux_tree_tapbuf_size16_0_sram[1]:43 0.0045 +4 mux_tree_tapbuf_size16_0_sram[1]:38 mux_top_track_4\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size16_0_sram[1]:38 mux_tree_tapbuf_size16_0_sram[1]:37 0.0001686047 +6 mux_tree_tapbuf_size16_0_sram[1]:23 mux_tree_tapbuf_size16_0_sram[1]:22 0.001513393 +7 mux_tree_tapbuf_size16_0_sram[1]:24 mux_tree_tapbuf_size16_0_sram[1]:23 0.0045 +8 mux_tree_tapbuf_size16_0_sram[1]:21 mux_tree_tapbuf_size16_0_sram[1]:20 0.0045 +9 mux_tree_tapbuf_size16_0_sram[1]:21 mux_top_track_4\/mux_l2_in_7_:S 0.152 +10 mux_tree_tapbuf_size16_0_sram[1]:21 mux_tree_tapbuf_size16_0_sram[1]:11 0.003020089 +11 mux_tree_tapbuf_size16_0_sram[1]:21 mux_tree_tapbuf_size16_0_sram[1]:10 4.464286e-05 +12 mux_tree_tapbuf_size16_0_sram[1]:20 mux_tree_tapbuf_size16_0_sram[1]:19 0.004513393 +13 mux_tree_tapbuf_size16_0_sram[1]:40 mux_tree_tapbuf_size16_0_sram[1]:39 0.00020625 +14 mux_tree_tapbuf_size16_0_sram[1]:41 mux_tree_tapbuf_size16_0_sram[1]:40 0.0045 +15 mux_tree_tapbuf_size16_0_sram[1]:46 mux_tree_tapbuf_size16_0_sram[1]:45 0.0045 +16 mux_tree_tapbuf_size16_0_sram[1]:46 mux_tree_tapbuf_size16_0_sram[1]:31 0.0003035715 +17 mux_tree_tapbuf_size16_0_sram[1]:45 mux_tree_tapbuf_size16_0_sram[1]:44 0.00178125 +18 mux_tree_tapbuf_size16_0_sram[1]:45 mux_tree_tapbuf_size16_0_sram[1]:41 0.007245535 +19 mux_tree_tapbuf_size16_0_sram[1]:11 mux_top_track_4\/mux_l2_in_6_:S 0.152 +20 mux_tree_tapbuf_size16_0_sram[1]:18 mux_tree_tapbuf_size16_0_sram[1]:17 0.00341 +21 mux_tree_tapbuf_size16_0_sram[1]:18 mux_tree_tapbuf_size16_0_sram[1]:12 0.0045 +22 mux_tree_tapbuf_size16_0_sram[1]:17 mux_tree_tapbuf_size16_0_sram[1]:16 0.00172725 +23 mux_tree_tapbuf_size16_0_sram[1]:15 mux_tree_tapbuf_size16_0_sram[1]:14 0.0045 +24 mux_tree_tapbuf_size16_0_sram[1]:16 mux_tree_tapbuf_size16_0_sram[1]:15 0.00341 +25 mux_tree_tapbuf_size16_0_sram[1]:14 mux_tree_tapbuf_size16_0_sram[1]:13 0.003712054 +26 mux_tree_tapbuf_size16_0_sram[1]:13 mux_top_track_4\/mux_l2_in_5_:S 0.152 +27 mux_tree_tapbuf_size16_0_sram[1]:12 mux_top_track_4\/mux_l2_in_4_:S 0.152 +28 mux_tree_tapbuf_size16_0_sram[1]:28 mux_tree_tapbuf_size16_0_sram[1]:27 0.0003705358 +29 mux_tree_tapbuf_size16_0_sram[1]:29 mux_tree_tapbuf_size16_0_sram[1]:28 0.0045 +30 mux_tree_tapbuf_size16_0_sram[1]:29 mux_tree_tapbuf_size16_0_sram[1]:24 0.02515625 +31 mux_tree_tapbuf_size16_0_sram[1]:25 mux_top_track_4\/mux_l2_in_3_:S 0.152 +32 mux_tree_tapbuf_size16_0_sram[1]:32 mux_top_track_4\/mux_l2_in_0_:S 0.152 +33 mux_tree_tapbuf_size16_0_sram[1]:33 mux_tree_tapbuf_size16_0_sram[1]:32 0.001247768 +34 mux_tree_tapbuf_size16_0_sram[1]:34 mux_tree_tapbuf_size16_0_sram[1]:33 0.0045 +35 mux_tree_tapbuf_size16_0_sram[1]:36 mux_tree_tapbuf_size16_0_sram[1]:35 0.0045 +36 mux_tree_tapbuf_size16_0_sram[1]:35 mux_tree_tapbuf_size16_0_sram[1]:34 0.002348214 +37 mux_tree_tapbuf_size16_0_sram[1]:47 mux_tree_tapbuf_size16_0_sram[1]:46 0.005709822 +38 mux_tree_tapbuf_size16_0_sram[1]:48 mux_tree_tapbuf_size16_0_sram[1]:47 0.0045 +39 mux_tree_tapbuf_size16_0_sram[1]:48 mux_tree_tapbuf_size16_0_sram[1]:29 0.006375 +40 mux_tree_tapbuf_size16_0_sram[1]:30 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +41 mux_tree_tapbuf_size16_0_sram[1]:50 mux_tree_tapbuf_size16_0_sram[1]:49 0.0045 +42 mux_tree_tapbuf_size16_0_sram[1]:49 mux_tree_tapbuf_size16_0_sram[1]:48 0.005120536 +43 mux_tree_tapbuf_size16_0_sram[1]:51 mux_tree_tapbuf_size16_0_sram[1]:50 0.003484375 +44 mux_tree_tapbuf_size16_0_sram[1]:37 mux_tree_tapbuf_size16_0_sram[1]:36 0.001872768 +45 mux_tree_tapbuf_size16_0_sram[1]:31 mux_tree_tapbuf_size16_0_sram[1]:30 0.001453125 +46 mux_tree_tapbuf_size16_0_sram[1]:39 mux_tree_tapbuf_size16_0_sram[1]:38 0.0003080358 +47 mux_tree_tapbuf_size16_0_sram[1]:26 mux_tree_tapbuf_size16_0_sram[1]:25 0.001520089 +48 mux_tree_tapbuf_size16_0_sram[1]:22 mux_tree_tapbuf_size16_0_sram[1]:21 0.0003058036 +49 mux_tree_tapbuf_size16_0_sram[1]:27 mux_tree_tapbuf_size16_0_sram[1]:26 0.0003035715 +50 mux_tree_tapbuf_size16_0_sram[1]:19 mux_tree_tapbuf_size16_0_sram[1]:18 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[0] 0.01009536 //LENGTH 67.575 LUMPCC 0.00118446 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 108.865 80.580 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 84.355 71.740 +*I mux_right_track_32\/mux_l1_in_2_:S I *L 0.00357 *C 77.640 69.360 +*I mux_right_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 73.040 77.445 +*I mux_right_track_32\/mux_l1_in_3_:S I *L 0.00357 *C 87.300 74.800 +*I mux_right_track_32\/mux_l1_in_1_:S I *L 0.00357 *C 107.740 82.960 +*N mux_tree_tapbuf_size7_1_sram[0]:6 *C 107.640 82.960 +*N mux_tree_tapbuf_size7_1_sram[0]:7 *C 107.640 82.915 +*N mux_tree_tapbuf_size7_1_sram[0]:8 *C 87.285 74.800 +*N mux_tree_tapbuf_size7_1_sram[0]:9 *C 86.963 74.800 +*N mux_tree_tapbuf_size7_1_sram[0]:10 *C 86.940 74.755 +*N mux_tree_tapbuf_size7_1_sram[0]:11 *C 73.078 77.505 +*N mux_tree_tapbuf_size7_1_sram[0]:12 *C 73.555 77.520 +*N mux_tree_tapbuf_size7_1_sram[0]:13 *C 73.600 77.475 +*N mux_tree_tapbuf_size7_1_sram[0]:14 *C 73.600 69.405 +*N mux_tree_tapbuf_size7_1_sram[0]:15 *C 73.645 69.360 +*N mux_tree_tapbuf_size7_1_sram[0]:16 *C 77.640 69.360 +*N mux_tree_tapbuf_size7_1_sram[0]:17 *C 78.155 69.360 +*N mux_tree_tapbuf_size7_1_sram[0]:18 *C 78.200 69.405 +*N mux_tree_tapbuf_size7_1_sram[0]:19 *C 78.200 71.355 +*N mux_tree_tapbuf_size7_1_sram[0]:20 *C 78.245 71.400 +*N mux_tree_tapbuf_size7_1_sram[0]:21 *C 84.355 71.400 +*N mux_tree_tapbuf_size7_1_sram[0]:22 *C 84.355 71.740 +*N mux_tree_tapbuf_size7_1_sram[0]:23 *C 86.895 71.740 +*N mux_tree_tapbuf_size7_1_sram[0]:24 *C 86.940 71.785 +*N mux_tree_tapbuf_size7_1_sram[0]:25 *C 86.940 73.440 +*N mux_tree_tapbuf_size7_1_sram[0]:26 *C 86.948 73.440 +*N mux_tree_tapbuf_size7_1_sram[0]:27 *C 97.973 73.440 +*N mux_tree_tapbuf_size7_1_sram[0]:28 *C 97.980 73.383 +*N mux_tree_tapbuf_size7_1_sram[0]:29 *C 97.980 71.785 +*N mux_tree_tapbuf_size7_1_sram[0]:30 *C 98.025 71.740 +*N mux_tree_tapbuf_size7_1_sram[0]:31 *C 104.375 71.740 +*N mux_tree_tapbuf_size7_1_sram[0]:32 *C 104.420 71.785 +*N mux_tree_tapbuf_size7_1_sram[0]:33 *C 104.420 74.755 +*N mux_tree_tapbuf_size7_1_sram[0]:34 *C 104.465 74.800 +*N mux_tree_tapbuf_size7_1_sram[0]:35 *C 107.595 74.800 +*N mux_tree_tapbuf_size7_1_sram[0]:36 *C 107.640 74.845 +*N mux_tree_tapbuf_size7_1_sram[0]:37 *C 107.640 80.580 +*N mux_tree_tapbuf_size7_1_sram[0]:38 *C 107.685 80.580 +*N mux_tree_tapbuf_size7_1_sram[0]:39 *C 108.828 80.580 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_32\/mux_l1_in_2_:S 1e-06 +3 mux_right_track_32\/mux_l1_in_0_:S 1e-06 +4 mux_right_track_32\/mux_l1_in_3_:S 1e-06 +5 mux_right_track_32\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_1_sram[0]:6 3.020246e-05 +7 mux_tree_tapbuf_size7_1_sram[0]:7 0.0001375223 +8 mux_tree_tapbuf_size7_1_sram[0]:8 7.623096e-05 +9 mux_tree_tapbuf_size7_1_sram[0]:9 7.623096e-05 +10 mux_tree_tapbuf_size7_1_sram[0]:10 0.0001067218 +11 mux_tree_tapbuf_size7_1_sram[0]:11 6.156913e-05 +12 mux_tree_tapbuf_size7_1_sram[0]:12 6.156913e-05 +13 mux_tree_tapbuf_size7_1_sram[0]:13 0.0005536781 +14 mux_tree_tapbuf_size7_1_sram[0]:14 0.0005536781 +15 mux_tree_tapbuf_size7_1_sram[0]:15 0.0002903089 +16 mux_tree_tapbuf_size7_1_sram[0]:16 0.0003747622 +17 mux_tree_tapbuf_size7_1_sram[0]:17 5.402611e-05 +18 mux_tree_tapbuf_size7_1_sram[0]:18 0.0001610467 +19 mux_tree_tapbuf_size7_1_sram[0]:19 0.0001610467 +20 mux_tree_tapbuf_size7_1_sram[0]:20 0.0004338567 +21 mux_tree_tapbuf_size7_1_sram[0]:21 0.0004691243 +22 mux_tree_tapbuf_size7_1_sram[0]:22 0.0002376461 +23 mux_tree_tapbuf_size7_1_sram[0]:23 0.0002023786 +24 mux_tree_tapbuf_size7_1_sram[0]:24 0.0001297439 +25 mux_tree_tapbuf_size7_1_sram[0]:25 0.0002789333 +26 mux_tree_tapbuf_size7_1_sram[0]:26 0.0007718149 +27 mux_tree_tapbuf_size7_1_sram[0]:27 0.0007718149 +28 mux_tree_tapbuf_size7_1_sram[0]:28 0.0001370558 +29 mux_tree_tapbuf_size7_1_sram[0]:29 0.0001370558 +30 mux_tree_tapbuf_size7_1_sram[0]:30 0.0004050558 +31 mux_tree_tapbuf_size7_1_sram[0]:31 0.0004050558 +32 mux_tree_tapbuf_size7_1_sram[0]:32 0.0001832437 +33 mux_tree_tapbuf_size7_1_sram[0]:33 0.0001832437 +34 mux_tree_tapbuf_size7_1_sram[0]:34 0.0002389945 +35 mux_tree_tapbuf_size7_1_sram[0]:35 0.0002389945 +36 mux_tree_tapbuf_size7_1_sram[0]:36 0.0003260385 +37 mux_tree_tapbuf_size7_1_sram[0]:37 0.00049358 +38 mux_tree_tapbuf_size7_1_sram[0]:38 8.133685e-05 +39 mux_tree_tapbuf_size7_1_sram[0]:39 8.133685e-05 +40 mux_tree_tapbuf_size7_1_sram[0]:33 chanx_right_in[7]:20 6.278233e-08 +41 mux_tree_tapbuf_size7_1_sram[0]:32 chanx_right_in[7]:21 6.278233e-08 +42 mux_tree_tapbuf_size7_1_sram[0]:27 chanx_right_in[7]:18 8.692175e-05 +43 mux_tree_tapbuf_size7_1_sram[0]:27 chanx_right_in[7]:19 0.0005052456 +44 mux_tree_tapbuf_size7_1_sram[0]:26 chanx_right_in[7]:17 8.692175e-05 +45 mux_tree_tapbuf_size7_1_sram[0]:26 chanx_right_in[7]:18 0.0005052456 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_1_sram[0]:39 0.152 +1 mux_tree_tapbuf_size7_1_sram[0]:16 mux_right_track_32\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[0]:16 mux_tree_tapbuf_size7_1_sram[0]:15 0.003566964 +3 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:22 0.002267857 +4 mux_tree_tapbuf_size7_1_sram[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 0.0045 +5 mux_tree_tapbuf_size7_1_sram[0]:8 mux_right_track_32\/mux_l1_in_3_:S 0.152 +6 mux_tree_tapbuf_size7_1_sram[0]:9 mux_tree_tapbuf_size7_1_sram[0]:8 0.0001752718 +7 mux_tree_tapbuf_size7_1_sram[0]:10 mux_tree_tapbuf_size7_1_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size7_1_sram[0]:35 mux_tree_tapbuf_size7_1_sram[0]:34 0.002794643 +9 mux_tree_tapbuf_size7_1_sram[0]:36 mux_tree_tapbuf_size7_1_sram[0]:35 0.0045 +10 mux_tree_tapbuf_size7_1_sram[0]:34 mux_tree_tapbuf_size7_1_sram[0]:33 0.0045 +11 mux_tree_tapbuf_size7_1_sram[0]:33 mux_tree_tapbuf_size7_1_sram[0]:32 0.002651786 +12 mux_tree_tapbuf_size7_1_sram[0]:31 mux_tree_tapbuf_size7_1_sram[0]:30 0.005669644 +13 mux_tree_tapbuf_size7_1_sram[0]:32 mux_tree_tapbuf_size7_1_sram[0]:31 0.0045 +14 mux_tree_tapbuf_size7_1_sram[0]:30 mux_tree_tapbuf_size7_1_sram[0]:29 0.0045 +15 mux_tree_tapbuf_size7_1_sram[0]:29 mux_tree_tapbuf_size7_1_sram[0]:28 0.001426339 +16 mux_tree_tapbuf_size7_1_sram[0]:28 mux_tree_tapbuf_size7_1_sram[0]:27 0.00341 +17 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:26 0.00172725 +18 mux_tree_tapbuf_size7_1_sram[0]:25 mux_tree_tapbuf_size7_1_sram[0]:24 0.001477679 +19 mux_tree_tapbuf_size7_1_sram[0]:25 mux_tree_tapbuf_size7_1_sram[0]:10 0.001174107 +20 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:25 0.00341 +21 mux_tree_tapbuf_size7_1_sram[0]:20 mux_tree_tapbuf_size7_1_sram[0]:19 0.0045 +22 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:18 0.001741072 +23 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size7_1_sram[0]:16 0.0004598214 +24 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size7_1_sram[0]:17 0.0045 +25 mux_tree_tapbuf_size7_1_sram[0]:22 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +26 mux_tree_tapbuf_size7_1_sram[0]:22 mux_tree_tapbuf_size7_1_sram[0]:21 0.0003035714 +27 mux_tree_tapbuf_size7_1_sram[0]:38 mux_tree_tapbuf_size7_1_sram[0]:37 0.0045 +28 mux_tree_tapbuf_size7_1_sram[0]:37 mux_tree_tapbuf_size7_1_sram[0]:36 0.005120535 +29 mux_tree_tapbuf_size7_1_sram[0]:37 mux_tree_tapbuf_size7_1_sram[0]:7 0.002084822 +30 mux_tree_tapbuf_size7_1_sram[0]:39 mux_tree_tapbuf_size7_1_sram[0]:38 0.001020089 +31 mux_tree_tapbuf_size7_1_sram[0]:6 mux_right_track_32\/mux_l1_in_1_:S 0.152 +32 mux_tree_tapbuf_size7_1_sram[0]:7 mux_tree_tapbuf_size7_1_sram[0]:6 0.0045 +33 mux_tree_tapbuf_size7_1_sram[0]:11 mux_right_track_32\/mux_l1_in_0_:S 0.152 +34 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:11 0.0004263393 +35 mux_tree_tapbuf_size7_1_sram[0]:13 mux_tree_tapbuf_size7_1_sram[0]:12 0.0045 +36 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:14 0.0045 +37 mux_tree_tapbuf_size7_1_sram[0]:14 mux_tree_tapbuf_size7_1_sram[0]:13 0.007205358 +38 mux_tree_tapbuf_size7_1_sram[0]:21 mux_tree_tapbuf_size7_1_sram[0]:20 0.005455357 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002489639 //LENGTH 19.000 LUMPCC 0.0009930505 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_1_:X O *L 0 *C 76.595 98.600 +*I mux_top_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 75.615 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 75.578 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 74.565 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 74.520 113.175 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 74.520 110.500 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 74.980 110.500 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 74.980 98.645 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 75.025 98.600 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 76.558 98.600 + +*CAP +0 mux_top_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.873575e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.873575e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000173928 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001792836 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004369679 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004316123 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 7.766284e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 7.766284e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[11] 2.555133e-06 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chany_top_in[11]:11 0.0001140992 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[11]:11 2.555133e-06 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chany_top_in[11] 0.0001140992 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size12_0_sram[0]:23 2.217789e-05 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size12_0_sram[0]:25 0.0002165933 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size12_0_sram[0]:23 1.924622e-08 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size12_0_sram[0]:22 2.217789e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size12_0_sram[0]:24 0.0002166126 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size12_0_sram[3]:5 4.966366e-05 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size12_0_sram[3]:4 4.966366e-05 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size12_0_sram[3]:4 2.430631e-05 +22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size12_0_sram[3]:5 2.430631e-05 +23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.711049e-05 +24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.711049e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0009040179 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.01058482 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001368304 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002388393 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004107143 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0] 0.002863104 //LENGTH 24.500 LUMPCC 0.0003080802 DR + +*CONN +*I mux_right_track_0\/mux_l4_in_0_:X O *L 0 *C 110.225 101.320 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 129.450 96.730 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 129.412 96.838 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 128.845 96.900 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 128.800 96.945 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 128.800 101.275 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 128.755 101.320 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 110.263 101.320 + +*CAP +0 mux_right_track_0\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 4.653046e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 4.653046e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002296417 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002296417 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.00100034 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.00100034 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 right_top_grid_pin_44_[0]:17 0.0001010777 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 right_top_grid_pin_44_[0]:18 5.296238e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 right_top_grid_pin_44_[0]:18 0.0001010777 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 right_top_grid_pin_44_[0]:19 5.296238e-05 + +*RES +0 mux_right_track_0\/mux_l4_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.01651116 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.003866071 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0005066964 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0007175304 //LENGTH 5.380 LUMPCC 0.0001035775 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_1_:X O *L 0 *C 118.965 90.780 +*I mux_right_track_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 120.695 88.060 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 120.657 88.060 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 119.645 88.060 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 119.600 88.105 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 119.600 90.735 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 119.555 90.780 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 119.003 90.780 + +*CAP +0 mux_right_track_2\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 6.17003e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 6.17003e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0001755684 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0001755684 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 6.870769e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 6.870769e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 chanx_left_in[4]:21 5.178877e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 chanx_left_in[4]:22 5.178877e-05 + +*RES +0 mux_right_track_2\/mux_l3_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_right_track_2\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0009040179 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.002348214 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0] 0.002142347 //LENGTH 18.105 LUMPCC 0.0009597485 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_1_:X O *L 0 *C 90.445 25.500 +*I mux_bottom_track_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 89.070 9.860 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 89.108 9.860 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 90.575 9.860 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 90.620 9.905 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 90.620 25.455 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 90.620 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 90.445 25.500 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 6.059607e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 6.059607e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0004788254 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0004788254 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 5.307331e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 4.86822e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 chany_top_in[13]:8 0.0001723399 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 chany_top_in[13]:9 0.0001723399 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:13 6.577879e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_4_sram[2]:14 3.724832e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:10 6.577879e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_4_sram[2]:13 3.724832e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size12_4_sram[3]:3 5.185602e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size12_4_sram[3]:4 5.185602e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_4_sram[3]:5 7.215937e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_4_sram[3]:8 8.049187e-05 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_4_sram[3]:8 7.215937e-05 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_4_sram[3]:9 8.049187e-05 + +*RES +0 mux_bottom_track_1\/mux_l3_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_bottom_track_1\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.001310268 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.01388393 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002629786 //LENGTH 21.355 LUMPCC 0.0009145106 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_1_:X O *L 0 *C 70.095 41.480 +*I mux_bottom_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 68.370 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 68.407 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 69.415 22.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 69.460 22.825 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 69.460 41.435 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 69.505 41.480 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 70.058 41.480 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.144301e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.144301e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0007113623 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0007113623 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.383211e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.383211e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[4]:13 1.490394e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[4]:17 0.000166438 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[4]:16 0.000166438 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[4]:17 1.490394e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[8]:13 0.0001365324 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[8]:14 6.77838e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[8]:10 0.0001365324 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[8]:13 6.77838e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[17]:18 6.844341e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[17]:24 3.153767e-06 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[17]:17 6.844341e-05 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[17]:21 3.153767e-06 + +*RES +0 mux_bottom_track_3\/mux_l1_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01661607 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0008995537 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009701427 //LENGTH 6.000 LUMPCC 0.0003850964 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_3_:X O *L 0 *C 68.715 80.920 +*I mux_left_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 68.370 86.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 68.370 86.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 68.540 86.020 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 68.540 85.975 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 68.540 80.965 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 68.540 80.920 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 68.715 80.920 + +*CAP +0 mux_left_track_1\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.002838e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.549811e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001639963 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001639963 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.677487e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.275236e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[9]:33 0.0001372541 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_top_in[9]:30 0.0001372541 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:12 5.529409e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_9_X[0]:13 5.529409e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_3_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.239131e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004473215 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00152547 //LENGTH 11.150 LUMPCC 0.0003330389 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_2_:X O *L 0 *C 58.135 88.740 +*I mux_left_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 56.120 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 56.120 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 56.120 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 55.660 96.220 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 55.660 88.785 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 55.705 88.740 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 58.098 88.740 + +*CAP +0 mux_left_track_3\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.467883e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.236233e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004469319 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004099963 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001132311 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001132311 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[5]:32 9.860279e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[5]:31 9.860279e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:11 6.791667e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:8 6.791667e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_2_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002136161 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.006638393 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3\/mux_l2_in_1_:A1 0.152 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004107143 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005108992 //LENGTH 3.320 LUMPCC 0.0002412397 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 37.895 126.820 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.865 126.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.903 126.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 37.858 126.820 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001338298 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001338298 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 top_left_grid_pin_34_[0]:18 0.0001206198 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_34_[0]:17 0.0001206198 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002638393 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001794533 //LENGTH 14.130 LUMPCC 0.0003277371 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_7_:X O *L 0 *C 38.355 80.580 +*I mux_top_track_4\/mux_l3_in_3_:A0 I *L 0.001631 *C 37.895 93.160 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 37.895 93.160 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 37.720 93.160 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 37.720 93.115 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 37.720 80.625 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 37.765 80.580 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 38.318 80.580 + +*CAP +0 mux_top_track_4\/mux_l2_in_7_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_3_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.071159e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.641928e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0006056071 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0006056071 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.322553e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.322553e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chanx_right_in[7]:5 5.068853e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chanx_right_in[7]:6 5.068853e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.219482e-07 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.219482e-07 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001125581 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001125581 + +*RES +0 mux_top_track_4\/mux_l2_in_7_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_4\/mux_l3_in_3_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.01115179 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003689772 //LENGTH 2.480 LUMPCC 9.365169e-05 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_3_:X O *L 0 *C 116.205 77.180 +*I mux_right_track_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 118.395 77.180 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 118.358 77.180 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 116.243 77.180 + +*CAP +0 mux_right_track_4\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001366627 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001366627 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size16_1_sram[2]:9 3.3774e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size16_1_sram[2]:18 1.305185e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size16_1_sram[2]:10 3.3774e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size16_1_sram[2]:19 1.305185e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_3_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0] 0.002502847 //LENGTH 21.720 LUMPCC 0.0008441361 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_3_:X O *L 0 *C 36.625 33.320 +*I mux_bottom_track_5\/mux_l4_in_1_:A0 I *L 0.001631 *C 39.735 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 39.698 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 38.685 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 38.640 15.685 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 38.640 33.275 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 38.595 33.320 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 36.663 33.320 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_3_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_1_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 8.892786e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 8.892786e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0005932358 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0005932358 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0001461921 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.0001461921 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 prog_clk[0]:377 4.762852e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 prog_clk[0]:378 6.616009e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 prog_clk[0]:395 2.592602e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 prog_clk[0]:396 6.845324e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 prog_clk[0]:399 8.013034e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 prog_clk[0]:374 4.762852e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 prog_clk[0]:377 6.616009e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 prog_clk[0]:396 2.592602e-05 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 prog_clk[0]:399 6.845324e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 prog_clk[0]:400 8.013034e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 bottom_left_grid_pin_41_[0]:12 0.0001337698 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 bottom_left_grid_pin_41_[0]:11 0.0001337698 + +*RES +0 mux_bottom_track_5\/mux_l3_in_3_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_bottom_track_5\/mux_l4_in_1_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0009040179 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.01570536 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0] 0.00178811 //LENGTH 13.055 LUMPCC 0.0004085951 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_1_:X O *L 0 *C 30.995 87.720 +*I mux_left_track_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 18.230 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 18.268 87.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 30.958 87.720 + +*CAP +0 mux_left_track_5\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0006887572 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0006887572 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.362792e-07 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002040613 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002040613 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 2.362792e-07 + +*RES +0 mux_left_track_5\/mux_l3_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_left_track_5\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.01133036 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006517206 //LENGTH 3.960 LUMPCC 0.0001057002 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_5_:X O *L 0 *C 21.905 91.120 +*I mux_left_track_5\/mux_l3_in_2_:A0 I *L 0.001631 *C 22.370 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 22.370 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 22.080 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 22.080 88.105 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 22.080 91.075 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 22.080 91.120 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 21.905 91.120 + +*CAP +0 mux_left_track_5\/mux_l2_in_5_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_2_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.711415e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.755558e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000140693 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000140693 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.569296e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.227176e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.341448e-07 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.341448e-07 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.261597e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.261597e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_5_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_5\/mux_l3_in_2_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001576087 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002651786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0007070142 //LENGTH 4.895 LUMPCC 0.0003814353 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_3_:X O *L 0 *C 108.845 42.500 +*I mux_top_track_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 113.450 42.500 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 113.413 42.500 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 108.883 42.500 + +*CAP +0 mux_top_track_8\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001617895 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001617895 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_0_sram[2]:9 6.451696e-05 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:10 6.451696e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.120477e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.120477e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 optlc_net_152:14 7.49959e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_152:15 7.49959e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_3_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_8\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.004044643 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001184857 //LENGTH 8.500 LUMPCC 0.0003103386 DR + +*CONN +*I mux_top_track_16\/mux_l3_in_0_:X O *L 0 *C 51.315 52.360 +*I mux_top_track_16\/mux_l4_in_0_:A1 I *L 0.00198 *C 49.220 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 49.220 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 49.220 58.095 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 49.220 52.405 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 49.265 52.360 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 51.278 52.360 + +*CAP +0 mux_top_track_16\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.379961e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002430351 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002430351 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001763241 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001763241 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 chanx_right_in[16]:30 0.0001551693 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 chanx_right_in[16]:29 0.0001551693 + +*RES +0 mux_top_track_16\/mux_l3_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001796875 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.005080357 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_16\/mux_l4_in_0_:A1 0.152 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004685658 //LENGTH 3.785 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_2_:X O *L 0 *C 52.725 69.020 +*I mux_top_track_24\/mux_l3_in_1_:A1 I *L 0.00198 *C 56.220 69.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 56.183 69.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 52.763 69.020 + +*CAP +0 mux_top_track_24\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002332829 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002332829 + +*RES +0 mux_top_track_24\/mux_l2_in_2_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_24\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003053572 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007128526 //LENGTH 5.630 LUMPCC 0.0001057012 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_1_:X O *L 0 *C 106.545 68.680 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 106.895 64.600 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 106.895 64.600 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 107.180 64.600 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 107.180 64.645 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 107.180 68.635 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 107.135 68.680 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 106.583 68.680 + +*CAP +0 mux_right_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.165281e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.537652e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001873196 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001873196 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.174147e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.174147e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:187 3.08884e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:191 2.196222e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:186 3.08884e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:190 2.196222e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0035625 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0005496319 //LENGTH 3.250 LUMPCC 0.0002356599 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_3_:X O *L 0 *C 86.655 49.640 +*I mux_right_track_16\/mux_l3_in_1_:A0 I *L 0.001631 *C 87.575 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 87.538 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 86.985 47.940 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 86.940 47.985 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 86.940 49.595 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 86.940 49.640 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 86.655 49.640 + +*CAP +0 mux_right_track_16\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.310048e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.310048e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.624601e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.624601e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.652262e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.675641e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size10_1_sram[0]:22 3.42995e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size10_1_sram[0]:21 3.42995e-05 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.923092e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.923092e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.42995e-05 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.42995e-05 + +*RES +0 mux_right_track_16\/mux_l2_in_3_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_16\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004933036 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0014375 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001799966 //LENGTH 14.245 LUMPCC 0.0002736044 DR + +*CONN +*I mux_right_track_24\/mux_l3_in_0_:X O *L 0 *C 100.565 82.280 +*I mux_right_track_24\/mux_l4_in_0_:A1 I *L 0.00198 *C 107.280 77.860 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 107.280 77.860 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 107.180 77.520 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 99.865 77.520 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 99.820 77.565 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 99.820 82.235 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 99.865 82.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 100.528 82.280 + +*CAP +0 mux_right_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.493109e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003918355 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003647371 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000281276 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000281276 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 7.51532e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:8 7.51532e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 right_top_grid_pin_46_[0]:10 2.472914e-05 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 right_top_grid_pin_46_[0]:11 4.324506e-05 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 right_top_grid_pin_46_[0]:6 4.324506e-05 +12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 right_top_grid_pin_46_[0]:11 2.472914e-05 +13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.882798e-05 +14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.882798e-05 + +*RES +0 mux_right_track_24\/mux_l3_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_right_track_24\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.006531251 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.004169643 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0005915179 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000799955 //LENGTH 7.000 LUMPCC 0.0001366287 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_0_:X O *L 0 *C 63.655 30.940 +*I mux_bottom_track_17\/mux_l3_in_0_:A1 I *L 0.00198 *C 56.945 30.940 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 56.983 30.940 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 63.617 30.940 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003306631 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003306631 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_7_sram[1]:23 6.831435e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_7_sram[1]:24 6.831435e-05 + +*RES +0 mux_bottom_track_17\/mux_l2_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.005924107 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001627005 //LENGTH 11.890 LUMPCC 0.0002923571 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_1_:X O *L 0 *C 72.395 49.640 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 67.450 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 67.450 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 67.160 44.540 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 67.160 44.585 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 67.160 47.555 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 67.205 47.600 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 70.795 47.600 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 70.840 47.645 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 70.840 49.595 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 70.885 49.640 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 72.358 49.640 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.635867e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.221799e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001442185 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001442185 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001957918 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001957918 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001436639 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001436639 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001233613 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001233613 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[17]:21 8.561596e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[17]:24 8.561596e-05 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size10_1_sram[0]:21 6.05626e-05 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size10_1_sram[0]:22 6.05626e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001358696 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003205357 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001741071 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001314732 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001062788 //LENGTH 7.565 LUMPCC 0.0002254961 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_3_:X O *L 0 *C 32.485 77.520 +*I mux_left_track_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 38.930 77.180 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 38.893 77.180 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 38.180 77.180 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 38.180 77.520 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 32.485 77.520 + +*CAP +0 mux_left_track_9\/mux_l2_in_3_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_1_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.131922e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.791946e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003613832 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003646697 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chany_top_in[10]:25 3.537424e-05 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[10]:24 7.73738e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[10]:25 7.73738e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chany_top_in[10]:24 3.537424e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_3_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_9\/mux_l3_in_1_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005084822 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0003035715 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0006361608 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008242911 //LENGTH 5.160 LUMPCC 0.0003746868 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_0_:X O *L 0 *C 70.095 56.100 +*I mux_left_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 65.225 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 65.263 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 70.058 56.100 + +*CAP +0 mux_left_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002238022 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002238022 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[6]:21 0.0001873434 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[6]:22 0.0001873434 + +*RES +0 mux_left_track_17\/mux_l1_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00428125 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.007625205 //LENGTH 40.715 LUMPCC 0.003729994 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 59.515 57.800 +*I mux_left_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 23.825 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 23.863 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 25.715 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 25.760 61.495 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 25.760 57.858 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 25.768 57.800 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 57.953 57.800 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 57.960 57.800 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 58.005 57.800 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 59.478 57.800 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000151128 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000151128 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002219547 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002219547 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001418102 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.001418102 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 4.364168e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001336002 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001336002 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[17]:10 0.001664885 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[17]:15 5.406566e-06 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[17]:11 0.001664885 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[17]:16 5.406566e-06 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001947055 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001947055 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001654018 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003247768 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.005042316 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001314732 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0] 0.005192644 //LENGTH 35.940 LUMPCC 0.001028726 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_3_:X O *L 0 *C 85.275 80.920 +*I mux_top_track_32\/mux_l2_in_1_:A0 I *L 0.001631 *C 82.975 104.040 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 82.975 104.040 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 82.800 104.040 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 82.800 103.995 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 82.800 103.418 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 82.793 103.360 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 78.668 103.360 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 78.660 103.303 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 78.660 83.005 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 78.705 82.960 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 85.055 82.960 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 85.100 82.915 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 85.100 80.965 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 85.100 80.920 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:15 *C 85.275 80.920 + +*CAP +0 mux_top_track_32\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.668509e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.826074e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.687736e-05 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.687736e-05 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002246877 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002246877 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001039395 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001039395 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0004936928 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0004936928 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0001352626 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0001352626 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 6.707212e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:15 6.007034e-05 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[4]:26 0.0002401236 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[4]:25 0.0002401236 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size12_6_sram[0]:23 4.302125e-05 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size12_6_sram[0]:27 6.509944e-05 +20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size12_6_sram[0]:28 1.295727e-05 +21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size12_6_sram[0]:24 4.302125e-05 +22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size12_6_sram[0]:28 6.509944e-05 +23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size12_6_sram[0]:29 1.295727e-05 +24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001531613 +25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001531613 + +*RES +0 mux_top_track_32\/mux_l1_in_3_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:15 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_32\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000515625 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00064625 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.01812277 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.005669643 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0045 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0045 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.001741072 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:14 8.423914e-05 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00534383 //LENGTH 44.060 LUMPCC 0.001857814 DR + +*CONN +*I mux_bottom_track_33\/mux_l3_in_0_:X O *L 0 *C 20.525 30.600 +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 35.660 4.215 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 32.410 9.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 35.623 4.125 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 33.165 4.080 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 33.120 4.125 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 33.120 9.463 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 33.117 9.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 33.120 9.527 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 33.120 30.593 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 33.100 30.600 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 20.707 30.600 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 20.700 30.600 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 20.700 30.600 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 20.525 30.600 + +*CAP +0 mux_bottom_track_33\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 8.831733e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001306372 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001306372 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002924134 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002924134 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.831733e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0008587828 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0008587828 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0003063597 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0003063597 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:12 3.410458e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:13 4.917969e-05 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:14 4.771042e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_top_in[10]:12 6.795781e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_top_in[10]:16 7.579984e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_top_in[10]:11 6.795781e-05 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 chany_top_in[10]:15 7.579984e-05 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 prog_clk[0]:648 0.0002680813 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 prog_clk[0]:708 1.597288e-05 +21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 prog_clk[0]:401 0.0002680813 +22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 prog_clk[0]:648 1.597288e-05 +23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_left_grid_pin_34_[0]:16 8.883005e-06 +24 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_left_grid_pin_34_[0]:22 0.0001825003 +25 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_left_grid_pin_34_[0]:20 8.883005e-06 +26 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_left_grid_pin_34_[0]:23 0.0001825003 +27 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_left_in[3]:14 0.0003097119 +28 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_left_in[3]:13 0.0003097119 + +*RES +0 mux_bottom_track_33\/mux_l3_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:13 9.51087e-05 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001941492 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.003300183 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.00341 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000103914 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.004765626 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.002194196 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ccff_tail[0] 0.0007172918 //LENGTH 5.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_793:X O *L 0 *C 4.140 65.960 +*P ccff_tail[0] O *L 0.7423 *C 1.230 64.600 +*N ccff_tail[0]:2 *C 1.833 64.600 +*N ccff_tail[0]:3 *C 1.840 64.657 +*N ccff_tail[0]:4 *C 1.840 65.915 +*N ccff_tail[0]:5 *C 1.885 65.960 +*N ccff_tail[0]:6 *C 4.103 65.960 + +*CAP +0 ropt_mt_inst_793:X 1e-06 +1 ccff_tail[0] 6.566349e-05 +2 ccff_tail[0]:2 6.566349e-05 +3 ccff_tail[0]:3 0.000123651 +4 ccff_tail[0]:4 0.000123651 +5 ccff_tail[0]:5 0.0001688315 +6 ccff_tail[0]:6 0.0001688315 + +*RES +0 ropt_mt_inst_793:X ccff_tail[0]:6 0.152 +1 ccff_tail[0]:6 ccff_tail[0]:5 0.001979911 +2 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +3 ccff_tail[0]:4 ccff_tail[0]:3 0.001122768 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 9.439165e-05 + +*END + +*D_NET chanx_right_out[5] 0.001373152 //LENGTH 10.590 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 131.100 71.400 +*P chanx_right_out[5] O *L 0.7423 *C 140.450 72.080 +*N chanx_right_out[5]:2 *C 134.328 72.080 +*N chanx_right_out[5]:3 *C 134.320 72.080 +*N chanx_right_out[5]:4 *C 134.320 71.740 +*N chanx_right_out[5]:5 *C 134.275 71.740 +*N chanx_right_out[5]:6 *C 131.100 71.740 +*N chanx_right_out[5]:7 *C 131.100 71.400 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 chanx_right_out[5] 0.0003801485 +2 chanx_right_out[5]:2 0.0003801485 +3 chanx_right_out[5]:3 5.812039e-05 +4 chanx_right_out[5]:4 5.361745e-05 +5 chanx_right_out[5]:5 0.0002089363 +6 chanx_right_out[5]:6 0.0002360669 +7 chanx_right_out[5]:7 5.511426e-05 + +*RES +0 ropt_mt_inst_796:X chanx_right_out[5]:7 0.152 +1 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +2 chanx_right_out[5]:2 chanx_right_out[5] 0.0009591916 +3 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0045 +4 chanx_right_out[5]:4 chanx_right_out[5]:3 0.0001634615 +5 chanx_right_out[5]:7 chanx_right_out[5]:6 0.0003035715 +6 chanx_right_out[5]:6 chanx_right_out[5]:5 0.002834822 + +*END + +*D_NET ropt_net_197 0.0008842183 //LENGTH 6.345 LUMPCC 0.0001541225 DR + +*CONN +*I FTB_39__38:X O *L 0 *C 80.040 125.800 +*I ropt_mt_inst_838:A I *L 0.001766 *C 83.720 123.760 +*N ropt_net_197:2 *C 83.720 123.760 +*N ropt_net_197:3 *C 83.720 123.805 +*N ropt_net_197:4 *C 83.720 125.755 +*N ropt_net_197:5 *C 83.675 125.800 +*N ropt_net_197:6 *C 80.078 125.800 + +*CAP +0 FTB_39__38:X 1e-06 +1 ropt_mt_inst_838:A 1e-06 +2 ropt_net_197:2 3.817123e-05 +3 ropt_net_197:3 0.0001295771 +4 ropt_net_197:4 0.0001295771 +5 ropt_net_197:5 0.0002153852 +6 ropt_net_197:6 0.0002153852 +7 ropt_net_197:6 chany_top_out[0]:3 7.706123e-05 +8 ropt_net_197:5 chany_top_out[0]:4 7.706123e-05 + +*RES +0 FTB_39__38:X ropt_net_197:6 0.152 +1 ropt_net_197:6 ropt_net_197:5 0.003212054 +2 ropt_net_197:5 ropt_net_197:4 0.0045 +3 ropt_net_197:4 ropt_net_197:3 0.001741071 +4 ropt_net_197:2 ropt_mt_inst_838:A 0.152 +5 ropt_net_197:3 ropt_net_197:2 0.0045 + +*END + +*D_NET ropt_net_179 0.001147692 //LENGTH 7.580 LUMPCC 0.0003164103 DR + +*CONN +*I FTB_49__48:X O *L 0 *C 129.260 69.020 +*I ropt_mt_inst_818:A I *L 0.001766 *C 134.780 69.360 +*N ropt_net_179:2 *C 134.743 69.360 +*N ropt_net_179:3 *C 133.905 69.360 +*N ropt_net_179:4 *C 133.860 69.315 +*N ropt_net_179:5 *C 133.860 68.725 +*N ropt_net_179:6 *C 133.815 68.680 +*N ropt_net_179:7 *C 129.260 68.680 +*N ropt_net_179:8 *C 129.260 69.020 + +*CAP +0 FTB_49__48:X 1e-06 +1 ropt_mt_inst_818:A 1e-06 +2 ropt_net_179:2 5.008563e-05 +3 ropt_net_179:3 5.008563e-05 +4 ropt_net_179:4 5.25165e-05 +5 ropt_net_179:5 5.25165e-05 +6 ropt_net_179:6 0.0002620153 +7 ropt_net_179:7 0.0002945581 +8 ropt_net_179:8 6.750401e-05 +9 ropt_net_179:6 ropt_net_244:6 0.0001130515 +10 ropt_net_179:5 ropt_net_244:4 1.634488e-05 +11 ropt_net_179:3 ropt_net_244:7 2.880873e-05 +12 ropt_net_179:4 ropt_net_244:5 1.634488e-05 +13 ropt_net_179:2 ropt_net_244:6 2.880873e-05 +14 ropt_net_179:7 ropt_net_244:7 0.0001130515 + +*RES +0 FTB_49__48:X ropt_net_179:8 0.152 +1 ropt_net_179:8 ropt_net_179:7 0.0003035715 +2 ropt_net_179:6 ropt_net_179:5 0.0045 +3 ropt_net_179:5 ropt_net_179:4 0.0005267857 +4 ropt_net_179:3 ropt_net_179:2 0.0007477679 +5 ropt_net_179:4 ropt_net_179:3 0.0045 +6 ropt_net_179:2 ropt_mt_inst_818:A 0.152 +7 ropt_net_179:7 ropt_net_179:6 0.004066965 + +*END + +*D_NET ropt_net_172 0.002490646 //LENGTH 17.775 LUMPCC 0.000606606 DR + +*CONN +*I BUFT_RR_92:X O *L 0 *C 47.840 125.800 +*I ropt_mt_inst_810:A I *L 0.001766 *C 60.720 126.480 +*N ropt_net_172:2 *C 60.758 126.480 +*N ropt_net_172:3 *C 61.605 126.480 +*N ropt_net_172:4 *C 61.605 126.140 +*N ropt_net_172:5 *C 49.220 126.140 +*N ropt_net_172:6 *C 49.220 126.480 +*N ropt_net_172:7 *C 49.220 126.480 +*N ropt_net_172:8 *C 49.213 126.480 +*N ropt_net_172:9 *C 48.308 126.480 +*N ropt_net_172:10 *C 48.300 126.422 +*N ropt_net_172:11 *C 48.300 125.845 +*N ropt_net_172:12 *C 48.255 125.800 +*N ropt_net_172:13 *C 47.878 125.800 + +*CAP +0 BUFT_RR_92:X 1e-06 +1 ropt_mt_inst_810:A 1e-06 +2 ropt_net_172:2 8.032531e-05 +3 ropt_net_172:3 0.0001084601 +4 ropt_net_172:4 0.0006407844 +5 ropt_net_172:5 0.000638498 +6 ropt_net_172:6 5.528393e-05 +7 ropt_net_172:7 3.153811e-05 +8 ropt_net_172:8 6.03865e-05 +9 ropt_net_172:9 6.03865e-05 +10 ropt_net_172:10 5.29698e-05 +11 ropt_net_172:11 5.29698e-05 +12 ropt_net_172:12 5.021848e-05 +13 ropt_net_172:13 5.021848e-05 +14 ropt_net_172:5 chany_bottom_in[8]:11 9.53679e-05 +15 ropt_net_172:4 chany_bottom_in[8]:12 9.53679e-05 +16 ropt_net_172:5 ropt_net_215:5 0.0002079351 +17 ropt_net_172:4 ropt_net_215:6 0.0002079351 + +*RES +0 BUFT_RR_92:X ropt_net_172:13 0.152 +1 ropt_net_172:2 ropt_mt_inst_810:A 0.152 +2 ropt_net_172:6 ropt_net_172:5 0.0003035715 +3 ropt_net_172:7 ropt_net_172:6 0.0045 +4 ropt_net_172:8 ropt_net_172:7 0.00341 +5 ropt_net_172:10 ropt_net_172:9 0.00341 +6 ropt_net_172:9 ropt_net_172:8 0.0001417833 +7 ropt_net_172:12 ropt_net_172:11 0.0045 +8 ropt_net_172:11 ropt_net_172:10 0.0005156249 +9 ropt_net_172:13 ropt_net_172:12 0.0003370536 +10 ropt_net_172:5 ropt_net_172:4 0.01105804 +11 ropt_net_172:4 ropt_net_172:3 0.0002297297 +12 ropt_net_172:3 ropt_net_172:2 0.0007566964 + +*END + +*D_NET chanx_left_out[13] 0.001084136 //LENGTH 8.735 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_834:X O *L 0 *C 7.095 97.240 +*P chanx_left_out[13] O *L 0.7423 *C 1.298 99.280 +*N chanx_left_out[13]:2 *C 1.380 99.280 +*N chanx_left_out[13]:3 *C 1.380 99.223 +*N chanx_left_out[13]:4 *C 1.380 97.285 +*N chanx_left_out[13]:5 *C 1.425 97.240 +*N chanx_left_out[13]:6 *C 7.058 97.240 + +*CAP +0 ropt_mt_inst_834:X 1e-06 +1 chanx_left_out[13] 2.888443e-05 +2 chanx_left_out[13]:2 2.888443e-05 +3 chanx_left_out[13]:3 0.0001283787 +4 chanx_left_out[13]:4 0.0001283787 +5 chanx_left_out[13]:5 0.000384305 +6 chanx_left_out[13]:6 0.000384305 + +*RES +0 ropt_mt_inst_834:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:6 chanx_left_out[13]:5 0.005029018 +2 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.001729911 +4 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +5 chanx_left_out[13]:2 chanx_left_out[13] 2.35e-05 + +*END + +*D_NET ropt_net_175 0.001212466 //LENGTH 10.670 LUMPCC 0 DR + +*CONN +*I BUFT_P_121:X O *L 0 *C 7.820 83.300 +*I ropt_mt_inst_813:A I *L 0.001766 *C 3.220 85.680 +*N ropt_net_175:2 *C 3.183 85.680 +*N ropt_net_175:3 *C 1.885 85.680 +*N ropt_net_175:4 *C 1.840 85.635 +*N ropt_net_175:5 *C 1.840 83.345 +*N ropt_net_175:6 *C 1.885 83.300 +*N ropt_net_175:7 *C 7.783 83.300 + +*CAP +0 BUFT_P_121:X 1e-06 +1 ropt_mt_inst_813:A 1e-06 +2 ropt_net_175:2 9.020308e-05 +3 ropt_net_175:3 9.020308e-05 +4 ropt_net_175:4 0.0001361627 +5 ropt_net_175:5 0.0001361627 +6 ropt_net_175:6 0.0003788673 +7 ropt_net_175:7 0.0003788673 + +*RES +0 BUFT_P_121:X ropt_net_175:7 0.152 +1 ropt_net_175:2 ropt_mt_inst_813:A 0.152 +2 ropt_net_175:3 ropt_net_175:2 0.001158482 +3 ropt_net_175:4 ropt_net_175:3 0.0045 +4 ropt_net_175:6 ropt_net_175:5 0.0045 +5 ropt_net_175:5 ropt_net_175:4 0.002044643 +6 ropt_net_175:7 ropt_net_175:6 0.005265625 + +*END + +*D_NET chanx_left_out[7] 0.001507459 //LENGTH 10.140 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_866:X O *L 0 *C 7.095 68.680 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 65.960 +*N chanx_left_out[7]:2 *C 1.440 68.680 +*N chanx_left_out[7]:3 *C 1.820 65.960 +*N chanx_left_out[7]:4 *C 1.840 65.968 +*N chanx_left_out[7]:5 *C 1.840 68.672 +*N chanx_left_out[7]:6 *C 1.840 68.680 +*N chanx_left_out[7]:7 *C 1.840 68.680 +*N chanx_left_out[7]:8 *C 1.885 68.680 +*N chanx_left_out[7]:9 *C 7.058 68.680 + +*CAP +0 ropt_mt_inst_866:X 1e-06 +1 chanx_left_out[7] 6.547816e-05 +2 chanx_left_out[7]:2 0.000126477 +3 chanx_left_out[7]:3 6.547816e-05 +4 chanx_left_out[7]:4 0.0001788957 +5 chanx_left_out[7]:5 0.0001788957 +6 chanx_left_out[7]:6 0.000126477 +7 chanx_left_out[7]:7 3.487208e-05 +8 chanx_left_out[7]:8 0.0003649428 +9 chanx_left_out[7]:9 0.0003649428 + +*RES +0 ropt_mt_inst_866:X chanx_left_out[7]:9 0.152 +1 chanx_left_out[7]:9 chanx_left_out[7]:8 0.004618304 +2 chanx_left_out[7]:8 chanx_left_out[7]:7 0.0045 +3 chanx_left_out[7]:7 chanx_left_out[7]:6 0.00341 +4 chanx_left_out[7]:6 chanx_left_out[7]:5 0.00341 +5 chanx_left_out[7]:6 chanx_left_out[7]:2 5.69697e-05 +6 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0004237833 +7 chanx_left_out[7]:3 chanx_left_out[7] 9.243333e-05 +8 chanx_left_out[7]:4 chanx_left_out[7]:3 0.00341 + +*END + +*D_NET chany_top_out[14] 0.001843096 //LENGTH 14.950 LUMPCC 0.0001997038 DR + +*CONN +*I ropt_mt_inst_871:X O *L 0 *C 104.615 123.080 +*P chany_top_out[14] O *L 0.7423 *C 97.520 129.270 +*N chany_top_out[14]:2 *C 97.520 128.860 +*N chany_top_out[14]:3 *C 97.060 128.860 +*N chany_top_out[14]:4 *C 97.060 123.125 +*N chany_top_out[14]:5 *C 97.105 123.080 +*N chany_top_out[14]:6 *C 104.578 123.080 + +*CAP +0 ropt_mt_inst_871:X 1e-06 +1 chany_top_out[14] 3.388148e-05 +2 chany_top_out[14]:2 5.965984e-05 +3 chany_top_out[14]:3 0.0003019767 +4 chany_top_out[14]:4 0.0002761983 +5 chany_top_out[14]:5 0.000485338 +6 chany_top_out[14]:6 0.000485338 +7 chany_top_out[14]:4 ropt_net_196:8 9.985192e-05 +8 chany_top_out[14]:3 ropt_net_196:7 9.985192e-05 + +*RES +0 ropt_mt_inst_871:X chany_top_out[14]:6 0.152 +1 chany_top_out[14]:6 chany_top_out[14]:5 0.006671875 +2 chany_top_out[14]:5 chany_top_out[14]:4 0.0045 +3 chany_top_out[14]:4 chany_top_out[14]:3 0.005120536 +4 chany_top_out[14]:3 chany_top_out[14]:2 0.0004107143 +5 chany_top_out[14]:2 chany_top_out[14] 0.0003660714 + +*END + +*D_NET chany_bottom_out[5] 0.002140074 //LENGTH 16.570 LUMPCC 9.109204e-05 DR + +*CONN +*I ropt_mt_inst_884:X O *L 0 *C 72.680 11.560 +*P chany_bottom_out[5] O *L 0.7423 *C 71.760 1.290 +*N chany_bottom_out[5]:2 *C 71.760 11.503 +*N chany_bottom_out[5]:3 *C 71.767 11.560 +*N chany_bottom_out[5]:4 *C 73.593 11.560 +*N chany_bottom_out[5]:5 *C 73.600 11.617 +*N chany_bottom_out[5]:6 *C 73.600 12.535 +*N chany_bottom_out[5]:7 *C 73.555 12.580 +*N chany_bottom_out[5]:8 *C 72.725 12.580 +*N chany_bottom_out[5]:9 *C 72.680 12.535 +*N chany_bottom_out[5]:10 *C 72.680 11.605 +*N chany_bottom_out[5]:11 *C 72.680 11.560 + +*CAP +0 ropt_mt_inst_884:X 1e-06 +1 chany_bottom_out[5] 0.000647736 +2 chany_bottom_out[5]:2 0.000647736 +3 chany_bottom_out[5]:3 0.0001429826 +4 chany_bottom_out[5]:4 0.0001429826 +5 chany_bottom_out[5]:5 7.574474e-05 +6 chany_bottom_out[5]:6 7.574474e-05 +7 chany_bottom_out[5]:7 6.822088e-05 +8 chany_bottom_out[5]:8 6.822088e-05 +9 chany_bottom_out[5]:9 7.239086e-05 +10 chany_bottom_out[5]:10 7.239086e-05 +11 chany_bottom_out[5]:11 3.383172e-05 +12 chany_bottom_out[5]:8 ropt_net_202:3 4.554602e-05 +13 chany_bottom_out[5]:7 ropt_net_202:2 4.554602e-05 + +*RES +0 ropt_mt_inst_884:X chany_bottom_out[5]:11 0.152 +1 chany_bottom_out[5]:11 chany_bottom_out[5]:10 0.0045 +2 chany_bottom_out[5]:10 chany_bottom_out[5]:9 0.0008303572 +3 chany_bottom_out[5]:8 chany_bottom_out[5]:7 0.0007410714 +4 chany_bottom_out[5]:9 chany_bottom_out[5]:8 0.0045 +5 chany_bottom_out[5]:7 chany_bottom_out[5]:6 0.0045 +6 chany_bottom_out[5]:6 chany_bottom_out[5]:5 0.0008191963 +7 chany_bottom_out[5]:5 chany_bottom_out[5]:4 0.00341 +8 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.0002859167 +9 chany_bottom_out[5]:2 chany_bottom_out[5] 0.009118304 +10 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.00341 + +*END + +*D_NET chanx_right_in[2] 0.02942716 //LENGTH 188.925 LUMPCC 0.007906034 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 140.450 55.760 +*I mux_bottom_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 85.200 58.140 +*I mux_left_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 81.250 82.620 +*I FTB_14__13:A I *L 0.001776 *C 11.040 77.520 +*I mux_top_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 81.655 93.500 +*N chanx_right_in[2]:5 *C 81.618 93.500 +*N chanx_right_in[2]:6 *C 81.005 93.500 +*N chanx_right_in[2]:7 *C 80.960 93.455 +*N chanx_right_in[2]:8 *C 11.040 77.535 +*N chanx_right_in[2]:9 *C 11.018 77.860 +*N chanx_right_in[2]:10 *C 9.705 77.860 +*N chanx_right_in[2]:11 *C 9.660 77.905 +*N chanx_right_in[2]:12 *C 9.660 82.235 +*N chanx_right_in[2]:13 *C 9.705 82.280 +*N chanx_right_in[2]:14 *C 21.160 82.280 +*N chanx_right_in[2]:15 *C 21.160 82.620 +*N chanx_right_in[2]:16 *C 27.600 82.620 +*N chanx_right_in[2]:17 *C 27.600 82.280 +*N chanx_right_in[2]:18 *C 39.975 82.280 +*N chanx_right_in[2]:19 *C 40.020 82.325 +*N chanx_right_in[2]:20 *C 40.020 82.903 +*N chanx_right_in[2]:21 *C 40.028 82.960 +*N chanx_right_in[2]:22 *C 52.440 82.960 +*N chanx_right_in[2]:23 *C 52.440 82.280 +*N chanx_right_in[2]:24 *C 72.680 82.280 +*N chanx_right_in[2]:25 *C 72.680 82.960 +*N chanx_right_in[2]:26 *C 78.200 82.960 +*N chanx_right_in[2]:27 *C 78.200 83.640 +*N chanx_right_in[2]:28 *C 80.953 83.640 +*N chanx_right_in[2]:29 *C 80.960 83.640 +*N chanx_right_in[2]:30 *C 81.250 82.620 +*N chanx_right_in[2]:31 *C 80.960 82.620 +*N chanx_right_in[2]:32 *C 80.960 82.620 +*N chanx_right_in[2]:33 *C 80.960 75.140 +*N chanx_right_in[2]:34 *C 80.500 75.140 +*N chanx_right_in[2]:35 *C 80.500 72.080 +*N chanx_right_in[2]:36 *C 80.960 72.080 +*N chanx_right_in[2]:37 *C 80.960 66.980 +*N chanx_right_in[2]:38 *C 80.500 66.980 +*N chanx_right_in[2]:39 *C 80.500 61.938 +*N chanx_right_in[2]:40 *C 80.508 61.880 +*N chanx_right_in[2]:41 *C 84.633 61.880 +*N chanx_right_in[2]:42 *C 84.640 61.823 +*N chanx_right_in[2]:43 *C 85.163 58.140 +*N chanx_right_in[2]:44 *C 84.685 58.140 +*N chanx_right_in[2]:45 *C 84.640 58.140 +*N chanx_right_in[2]:46 *C 84.640 56.498 +*N chanx_right_in[2]:47 *C 84.648 56.440 +*N chanx_right_in[2]:48 *C 138.920 56.440 +*N chanx_right_in[2]:49 *C 138.920 55.760 + +*CAP +0 chanx_right_in[2] 5.375773e-05 +1 mux_bottom_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_1\/mux_l1_in_1_:A0 1e-06 +3 FTB_14__13:A 1e-06 +4 mux_top_track_0\/mux_l1_in_2_:A0 1e-06 +5 chanx_right_in[2]:5 6.280906e-05 +6 chanx_right_in[2]:6 6.280906e-05 +7 chanx_right_in[2]:7 0.0005867437 +8 chanx_right_in[2]:8 2.612841e-05 +9 chanx_right_in[2]:9 0.0001423115 +10 chanx_right_in[2]:10 0.0001161831 +11 chanx_right_in[2]:11 0.0003156899 +12 chanx_right_in[2]:12 0.0003156899 +13 chanx_right_in[2]:13 0.0007677788 +14 chanx_right_in[2]:14 0.0007946425 +15 chanx_right_in[2]:15 0.0004683589 +16 chanx_right_in[2]:16 0.0004683196 +17 chanx_right_in[2]:17 0.0008015541 +18 chanx_right_in[2]:18 0.0007747297 +19 chanx_right_in[2]:19 6.180169e-05 +20 chanx_right_in[2]:20 6.180169e-05 +21 chanx_right_in[2]:21 0.0008831566 +22 chanx_right_in[2]:22 0.0009381798 +23 chanx_right_in[2]:23 0.001454073 +24 chanx_right_in[2]:24 0.001472941 +25 chanx_right_in[2]:25 0.0004964881 +26 chanx_right_in[2]:26 0.0004889136 +27 chanx_right_in[2]:27 0.0002987945 +28 chanx_right_in[2]:28 0.0002324775 +29 chanx_right_in[2]:29 0.0006787421 +30 chanx_right_in[2]:30 6.029927e-05 +31 chanx_right_in[2]:31 6.354702e-05 +32 chanx_right_in[2]:32 0.000508519 +33 chanx_right_in[2]:33 0.0004092563 +34 chanx_right_in[2]:34 0.0001242401 +35 chanx_right_in[2]:35 0.0001126498 +36 chanx_right_in[2]:36 0.0002656706 +37 chanx_right_in[2]:37 0.0003216804 +38 chanx_right_in[2]:38 0.0003580479 +39 chanx_right_in[2]:39 0.0003252543 +40 chanx_right_in[2]:40 0.0003099925 +41 chanx_right_in[2]:41 0.0003099925 +42 chanx_right_in[2]:42 0.0002914513 +43 chanx_right_in[2]:43 6.082565e-05 +44 chanx_right_in[2]:44 6.082565e-05 +45 chanx_right_in[2]:45 0.0004406344 +46 chanx_right_in[2]:46 0.0001179872 +47 chanx_right_in[2]:47 0.002205571 +48 chanx_right_in[2]:48 0.002248806 +49 chanx_right_in[2]:49 9.699257e-05 +50 chanx_right_in[2]:22 chany_top_in[14]:23 9.395784e-06 +51 chanx_right_in[2]:23 chany_top_in[14]:16 9.395784e-06 +52 chanx_right_in[2]:23 chany_top_in[14]:22 0.000308564 +53 chanx_right_in[2]:24 chany_top_in[14]:21 0.000308564 +54 chanx_right_in[2]:25 chany_top_in[14]:22 6.294285e-05 +55 chanx_right_in[2]:26 chany_top_in[14]:21 6.294285e-05 +56 chanx_right_in[2]:28 chany_bottom_in[10]:25 4.672736e-05 +57 chanx_right_in[2]:21 chany_bottom_in[10]:41 5.685098e-05 +58 chanx_right_in[2]:32 chany_bottom_in[10]:19 5.941659e-05 +59 chanx_right_in[2]:32 chany_bottom_in[10]:15 2.524146e-06 +60 chanx_right_in[2]:37 chany_bottom_in[10]:14 2.352062e-05 +61 chanx_right_in[2]:35 chany_bottom_in[10]:14 7.888293e-05 +62 chanx_right_in[2]:34 chany_bottom_in[10]:15 8.007701e-05 +63 chanx_right_in[2]:36 chany_bottom_in[10]:15 2.352062e-05 +64 chanx_right_in[2]:33 chany_bottom_in[10]:20 1.019673e-05 +65 chanx_right_in[2]:33 chany_bottom_in[10]:14 2.524146e-06 +66 chanx_right_in[2]:33 chany_bottom_in[10]:16 5.041392e-05 +67 chanx_right_in[2]:22 chany_bottom_in[10]:42 5.685098e-05 +68 chanx_right_in[2]:23 chany_bottom_in[10]:41 4.431575e-06 +69 chanx_right_in[2]:23 chany_bottom_in[10]:28 3.179247e-07 +70 chanx_right_in[2]:24 chany_bottom_in[10]:42 4.431575e-06 +71 chanx_right_in[2]:24 chany_bottom_in[10]:27 3.179247e-07 +72 chanx_right_in[2]:25 chany_bottom_in[10]:30 2.543397e-07 +73 chanx_right_in[2]:25 chany_bottom_in[10]:28 4.220443e-05 +74 chanx_right_in[2]:25 chany_bottom_in[10]:26 4.121133e-06 +75 chanx_right_in[2]:26 chany_bottom_in[10]:25 4.121133e-06 +76 chanx_right_in[2]:26 chany_bottom_in[10]:29 2.543397e-07 +77 chanx_right_in[2]:26 chany_bottom_in[10]:27 4.220443e-05 +78 chanx_right_in[2]:27 chany_bottom_in[10]:26 4.672736e-05 +79 chanx_right_in[2]:21 chanx_left_in[13]:32 1.956339e-07 +80 chanx_right_in[2]:47 chanx_left_in[13]:13 0.0009387748 +81 chanx_right_in[2]:22 chanx_left_in[13]:22 1.956339e-07 +82 chanx_right_in[2]:25 chanx_left_in[13]:22 1.78776e-07 +83 chanx_right_in[2]:26 chanx_left_in[13]:17 1.78776e-07 +84 chanx_right_in[2]:48 chanx_left_in[13]:12 0.0009387748 +85 chanx_right_in[2]:42 prog_clk[0]:294 5.976689e-08 +86 chanx_right_in[2]:41 prog_clk[0]:286 0.0001162251 +87 chanx_right_in[2]:39 prog_clk[0]:292 4.457268e-06 +88 chanx_right_in[2]:39 prog_clk[0]:288 4.151992e-06 +89 chanx_right_in[2]:40 prog_clk[0]:287 0.0001162251 +90 chanx_right_in[2]:18 prog_clk[0]:489 1.949926e-06 +91 chanx_right_in[2]:10 prog_clk[0]:661 4.450686e-06 +92 chanx_right_in[2]:8 prog_clk[0]:660 6.684738e-06 +93 chanx_right_in[2]:47 prog_clk[0]:207 0.0001444144 +94 chanx_right_in[2]:47 prog_clk[0]:201 0.0003575801 +95 chanx_right_in[2]:47 prog_clk[0]:206 7.975133e-05 +96 chanx_right_in[2]:45 prog_clk[0]:298 5.976689e-08 +97 chanx_right_in[2]:9 prog_clk[0]:660 4.450686e-06 +98 chanx_right_in[2]:9 prog_clk[0]:659 6.684738e-06 +99 chanx_right_in[2]:17 prog_clk[0]:490 1.949926e-06 +100 chanx_right_in[2]:38 prog_clk[0]:281 4.151992e-06 +101 chanx_right_in[2]:38 prog_clk[0]:289 4.457268e-06 +102 chanx_right_in[2]:37 prog_clk[0]:288 1.918499e-06 +103 chanx_right_in[2]:36 prog_clk[0]:281 1.918499e-06 +104 chanx_right_in[2]:48 prog_clk[0]:207 7.975133e-05 +105 chanx_right_in[2]:48 prog_clk[0]:197 0.0003575801 +106 chanx_right_in[2]:48 prog_clk[0]:201 0.0001444144 +107 chanx_right_in[2] chanx_right_in[15] 4.072137e-05 +108 chanx_right_in[2]:47 chanx_right_in[15]:15 7.872648e-05 +109 chanx_right_in[2]:47 chanx_right_in[15]:17 0.0008067296 +110 chanx_right_in[2]:47 chanx_right_in[15]:19 0.0001707317 +111 chanx_right_in[2]:48 chanx_right_in[15] 0.0001707317 +112 chanx_right_in[2]:48 chanx_right_in[15]:16 7.872648e-05 +113 chanx_right_in[2]:48 chanx_right_in[15]:18 0.0008067296 +114 chanx_right_in[2]:49 chanx_right_in[15]:19 4.072137e-05 +115 chanx_right_in[2]:13 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:9 2.956558e-05 +116 chanx_right_in[2]:13 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:6 1.482116e-05 +117 chanx_right_in[2]:14 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:8 2.956558e-05 +118 chanx_right_in[2]:14 mux_tree_tapbuf_size16_mem_3_ccff_tail[0]:5 1.482116e-05 +119 chanx_right_in[2]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 0.0001102069 +120 chanx_right_in[2]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 6.858334e-06 +121 chanx_right_in[2]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 6.858334e-06 +122 chanx_right_in[2]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 0.0001102069 +123 chanx_right_in[2]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002327215 +124 chanx_right_in[2]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002327215 +125 chanx_right_in[2]:35 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.61421e-05 +126 chanx_right_in[2]:34 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 4.365035e-05 +127 chanx_right_in[2]:36 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.61421e-05 +128 chanx_right_in[2]:33 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 4.365035e-05 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:49 0.0002397 +1 chanx_right_in[2]:42 chanx_right_in[2]:41 0.00341 +2 chanx_right_in[2]:41 chanx_right_in[2]:40 0.00064625 +3 chanx_right_in[2]:39 chanx_right_in[2]:38 0.004502232 +4 chanx_right_in[2]:40 chanx_right_in[2]:39 0.00341 +5 chanx_right_in[2]:29 chanx_right_in[2]:28 0.00341 +6 chanx_right_in[2]:29 chanx_right_in[2]:7 0.008763393 +7 chanx_right_in[2]:28 chanx_right_in[2]:27 0.0004312249 +8 chanx_right_in[2]:20 chanx_right_in[2]:19 0.000515625 +9 chanx_right_in[2]:21 chanx_right_in[2]:20 0.00341 +10 chanx_right_in[2]:18 chanx_right_in[2]:17 0.01104911 +11 chanx_right_in[2]:19 chanx_right_in[2]:18 0.0045 +12 chanx_right_in[2]:13 chanx_right_in[2]:12 0.0045 +13 chanx_right_in[2]:12 chanx_right_in[2]:11 0.003866071 +14 chanx_right_in[2]:10 chanx_right_in[2]:9 0.001171875 +15 chanx_right_in[2]:11 chanx_right_in[2]:10 0.0045 +16 chanx_right_in[2]:8 FTB_14__13:A 0.152 +17 chanx_right_in[2]:46 chanx_right_in[2]:45 0.001466518 +18 chanx_right_in[2]:47 chanx_right_in[2]:46 0.00341 +19 chanx_right_in[2]:44 chanx_right_in[2]:43 0.0004263393 +20 chanx_right_in[2]:45 chanx_right_in[2]:44 0.0045 +21 chanx_right_in[2]:45 chanx_right_in[2]:42 0.003287946 +22 chanx_right_in[2]:43 mux_bottom_track_1\/mux_l1_in_1_:A1 0.152 +23 chanx_right_in[2]:6 chanx_right_in[2]:5 0.000546875 +24 chanx_right_in[2]:7 chanx_right_in[2]:6 0.0045 +25 chanx_right_in[2]:5 mux_top_track_0\/mux_l1_in_2_:A0 0.152 +26 chanx_right_in[2]:31 chanx_right_in[2]:30 0.0001576087 +27 chanx_right_in[2]:32 chanx_right_in[2]:31 0.0045 +28 chanx_right_in[2]:32 chanx_right_in[2]:29 0.0009107143 +29 chanx_right_in[2]:30 mux_left_track_1\/mux_l1_in_1_:A0 0.152 +30 chanx_right_in[2]:9 chanx_right_in[2]:8 0.0001766305 +31 chanx_right_in[2]:14 chanx_right_in[2]:13 0.01022768 +32 chanx_right_in[2]:15 chanx_right_in[2]:14 0.0003035715 +33 chanx_right_in[2]:16 chanx_right_in[2]:15 0.00575 +34 chanx_right_in[2]:17 chanx_right_in[2]:16 0.0003035714 +35 chanx_right_in[2]:38 chanx_right_in[2]:37 0.0004107143 +36 chanx_right_in[2]:37 chanx_right_in[2]:36 0.004553571 +37 chanx_right_in[2]:35 chanx_right_in[2]:34 0.002732143 +38 chanx_right_in[2]:34 chanx_right_in[2]:33 0.0004107143 +39 chanx_right_in[2]:36 chanx_right_in[2]:35 0.0004107143 +40 chanx_right_in[2]:33 chanx_right_in[2]:32 0.006678571 +41 chanx_right_in[2]:22 chanx_right_in[2]:21 0.001944625 +42 chanx_right_in[2]:23 chanx_right_in[2]:22 0.0001065333 +43 chanx_right_in[2]:24 chanx_right_in[2]:23 0.003170933 +44 chanx_right_in[2]:25 chanx_right_in[2]:24 0.0001065333 +45 chanx_right_in[2]:26 chanx_right_in[2]:25 0.0008647999 +46 chanx_right_in[2]:27 chanx_right_in[2]:26 0.0001065333 +47 chanx_right_in[2]:48 chanx_right_in[2]:47 0.008502691 +48 chanx_right_in[2]:49 chanx_right_in[2]:48 0.0001065333 + +*END + +*D_NET chany_bottom_in[2] 0.02882787 //LENGTH 191.585 LUMPCC 0.01194798 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 81.420 1.325 +*I mux_top_track_0\/mux_l1_in_3_:A0 I *L 0.001631 *C 84.930 96.900 +*I mux_left_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 79.440 86.360 +*I ropt_mt_inst_803:A I *L 0.001766 *C 76.360 123.760 +*I mux_right_track_0\/mux_l1_in_3_:A0 I *L 0.001631 *C 92.175 98.940 +*N chany_bottom_in[2]:5 *C 92.175 98.940 +*N chany_bottom_in[2]:6 *C 76.360 123.760 +*N chany_bottom_in[2]:7 *C 75.440 123.760 +*N chany_bottom_in[2]:8 *C 75.440 123.420 +*N chany_bottom_in[2]:9 *C 75.440 123.465 +*N chany_bottom_in[2]:10 *C 75.440 128.815 +*N chany_bottom_in[2]:11 *C 75.485 128.860 +*N chany_bottom_in[2]:12 *C 85.055 128.860 +*N chany_bottom_in[2]:13 *C 85.100 128.815 +*N chany_bottom_in[2]:14 *C 79.478 86.360 +*N chany_bottom_in[2]:15 *C 82.755 86.360 +*N chany_bottom_in[2]:16 *C 82.800 86.405 +*N chany_bottom_in[2]:17 *C 82.800 93.455 +*N chany_bottom_in[2]:18 *C 82.845 93.500 +*N chany_bottom_in[2]:19 *C 85.055 93.500 +*N chany_bottom_in[2]:20 *C 85.100 93.545 +*N chany_bottom_in[2]:21 *C 84.930 96.900 +*N chany_bottom_in[2]:22 *C 85.100 96.900 +*N chany_bottom_in[2]:23 *C 85.100 96.900 +*N chany_bottom_in[2]:24 *C 85.100 98.600 +*N chany_bottom_in[2]:25 *C 85.145 98.600 +*N chany_bottom_in[2]:26 *C 92.000 98.600 +*N chany_bottom_in[2]:27 *C 93.335 98.600 +*N chany_bottom_in[2]:28 *C 93.380 98.555 +*N chany_bottom_in[2]:29 *C 93.380 97.978 +*N chany_bottom_in[2]:30 *C 93.388 97.920 +*N chany_bottom_in[2]:31 *C 95.660 97.920 +*N chany_bottom_in[2]:32 *C 95.680 97.913 +*N chany_bottom_in[2]:33 *C 95.680 51.875 +*N chany_bottom_in[2]:34 *C 95.680 2.048 +*N chany_bottom_in[2]:35 *C 95.660 2.040 +*N chany_bottom_in[2]:36 *C 81.428 2.040 +*N chany_bottom_in[2]:37 *C 81.420 1.983 + +*CAP +0 chany_bottom_in[2] 5.811404e-05 +1 mux_top_track_0\/mux_l1_in_3_:A0 1e-06 +2 mux_left_track_1\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_803:A 1e-06 +4 mux_right_track_0\/mux_l1_in_3_:A0 1e-06 +5 chany_bottom_in[2]:5 5.314948e-05 +6 chany_bottom_in[2]:6 0.0001071663 +7 chany_bottom_in[2]:7 9.599106e-05 +8 chany_bottom_in[2]:8 6.953726e-05 +9 chany_bottom_in[2]:9 0.000331601 +10 chany_bottom_in[2]:10 0.000331601 +11 chany_bottom_in[2]:11 0.0005785807 +12 chany_bottom_in[2]:12 0.0005785807 +13 chany_bottom_in[2]:13 0.001350464 +14 chany_bottom_in[2]:14 0.0002317357 +15 chany_bottom_in[2]:15 0.0002317357 +16 chany_bottom_in[2]:16 0.0003269197 +17 chany_bottom_in[2]:17 0.0003269197 +18 chany_bottom_in[2]:18 0.0001658272 +19 chany_bottom_in[2]:19 0.0001658272 +20 chany_bottom_in[2]:20 0.0001626917 +21 chany_bottom_in[2]:21 7.042693e-05 +22 chany_bottom_in[2]:22 7.677876e-05 +23 chany_bottom_in[2]:23 0.0002905417 +24 chany_bottom_in[2]:24 0.001471277 +25 chany_bottom_in[2]:25 0.0003707997 +26 chany_bottom_in[2]:26 0.0004927695 +27 chany_bottom_in[2]:27 9.746646e-05 +28 chany_bottom_in[2]:28 5.887946e-05 +29 chany_bottom_in[2]:29 5.887946e-05 +30 chany_bottom_in[2]:30 0.0001952139 +31 chany_bottom_in[2]:31 0.0001952139 +32 chany_bottom_in[2]:32 0.001887235 +33 chany_bottom_in[2]:33 0.003412652 +34 chany_bottom_in[2]:34 0.001525417 +35 chany_bottom_in[2]:35 0.0007238887 +36 chany_bottom_in[2]:36 0.0007238887 +37 chany_bottom_in[2]:37 5.811404e-05 +38 chany_bottom_in[2]:13 chany_top_in[18] 0.0003225772 +39 chany_bottom_in[2]:24 chany_top_in[18]:39 0.0003225772 +40 chany_bottom_in[2]:30 chanx_right_in[12]:29 6.750648e-05 +41 chany_bottom_in[2]:30 chanx_right_in[12]:31 3.552847e-05 +42 chany_bottom_in[2]:31 chanx_right_in[12] 3.552847e-05 +43 chany_bottom_in[2]:31 chanx_right_in[12]:30 6.750648e-05 +44 chany_bottom_in[2]:32 chanx_right_in[12]:30 6.211303e-06 +45 chany_bottom_in[2]:23 chanx_right_in[12]:27 2.432016e-05 +46 chany_bottom_in[2]:23 chanx_right_in[12]:28 6.91472e-06 +47 chany_bottom_in[2]:23 chanx_right_in[12]:29 1.174669e-05 +48 chany_bottom_in[2]:20 chanx_right_in[12]:26 2.432016e-05 +49 chany_bottom_in[2]:20 chanx_right_in[12]:28 1.174669e-05 +50 chany_bottom_in[2]:17 chanx_right_in[12]:22 0.0001881363 +51 chany_bottom_in[2]:15 chanx_right_in[12]:18 4.48762e-06 +52 chany_bottom_in[2]:15 chanx_right_in[12]:20 1.951272e-05 +53 chany_bottom_in[2]:16 chanx_right_in[12]:21 0.0001881363 +54 chany_bottom_in[2]:14 chanx_right_in[12]:17 4.48762e-06 +55 chany_bottom_in[2]:14 chanx_right_in[12]:19 1.951272e-05 +56 chany_bottom_in[2]:24 chanx_right_in[12]:29 6.91472e-06 +57 chany_bottom_in[2]:33 chanx_right_in[12]:31 6.211303e-06 +58 chany_bottom_in[2]:32 chany_bottom_in[16]:19 0.001014172 +59 chany_bottom_in[2]:34 chany_bottom_in[16]:29 0.0001237447 +60 chany_bottom_in[2]:34 chany_bottom_in[16]:30 0.001383916 +61 chany_bottom_in[2]:33 chany_bottom_in[16]:29 0.002398089 +62 chany_bottom_in[2]:33 chany_bottom_in[16]:19 0.0001237447 +63 chany_bottom_in[2]:32 chanx_left_in[2]:23 0.001327298 +64 chany_bottom_in[2]:34 chanx_left_in[2]:24 0.000699713 +65 chany_bottom_in[2]:33 chanx_left_in[2]:23 0.000699713 +66 chany_bottom_in[2]:33 chanx_left_in[2]:24 0.001327298 +67 chany_bottom_in[2]:35 chany_bottom_in[11]:17 0.000221514 +68 chany_bottom_in[2]:34 chany_bottom_in[11]:16 8.445636e-05 +69 chany_bottom_in[2]:36 chany_bottom_in[11]:18 0.000221514 +70 chany_bottom_in[2]:33 chany_bottom_in[11]:15 8.445636e-05 +71 chany_bottom_in[2]:25 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001630973 +72 chany_bottom_in[2]:26 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001630973 +73 chany_bottom_in[2]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.618199e-05 +74 chany_bottom_in[2]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.012958e-05 +75 chany_bottom_in[2]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.407931e-05 +76 chany_bottom_in[2]:20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.407931e-05 +77 chany_bottom_in[2]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.618199e-05 +78 chany_bottom_in[2]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.012958e-05 +79 chany_bottom_in[2]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.667414e-05 +80 chany_bottom_in[2]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.667414e-05 +81 chany_bottom_in[2]:10 ropt_net_213:5 7.752684e-05 +82 chany_bottom_in[2]:9 ropt_net_213:6 7.752684e-05 +83 chany_bottom_in[2]:6 ropt_net_213:8 1.45462e-05 +84 chany_bottom_in[2]:7 ropt_net_213:7 1.45462e-05 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:37 0.0005870535 +1 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.008544642 +2 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.0045 +3 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.0045 +4 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.004776786 +5 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.0003035715 +6 chany_bottom_in[2]:9 chany_bottom_in[2]:8 0.0045 +7 chany_bottom_in[2]:6 ropt_mt_inst_803:A 0.152 +8 chany_bottom_in[2]:27 chany_bottom_in[2]:26 0.001191964 +9 chany_bottom_in[2]:28 chany_bottom_in[2]:27 0.0045 +10 chany_bottom_in[2]:29 chany_bottom_in[2]:28 0.000515625 +11 chany_bottom_in[2]:30 chany_bottom_in[2]:29 0.00341 +12 chany_bottom_in[2]:31 chany_bottom_in[2]:30 0.000356025 +13 chany_bottom_in[2]:32 chany_bottom_in[2]:31 0.00341 +14 chany_bottom_in[2]:35 chany_bottom_in[2]:34 0.00341 +15 chany_bottom_in[2]:34 chany_bottom_in[2]:33 0.007806308 +16 chany_bottom_in[2]:37 chany_bottom_in[2]:36 0.00341 +17 chany_bottom_in[2]:36 chany_bottom_in[2]:35 0.002229758 +18 chany_bottom_in[2]:5 mux_right_track_0\/mux_l1_in_3_:A0 0.152 +19 chany_bottom_in[2]:22 chany_bottom_in[2]:21 9.239131e-05 +20 chany_bottom_in[2]:23 chany_bottom_in[2]:22 0.0045 +21 chany_bottom_in[2]:23 chany_bottom_in[2]:20 0.002995535 +22 chany_bottom_in[2]:21 mux_top_track_0\/mux_l1_in_3_:A0 0.152 +23 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.001973214 +24 chany_bottom_in[2]:20 chany_bottom_in[2]:19 0.0045 +25 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.0045 +26 chany_bottom_in[2]:17 chany_bottom_in[2]:16 0.006294643 +27 chany_bottom_in[2]:15 chany_bottom_in[2]:14 0.002926339 +28 chany_bottom_in[2]:16 chany_bottom_in[2]:15 0.0045 +29 chany_bottom_in[2]:14 mux_left_track_1\/mux_l1_in_2_:A0 0.152 +30 chany_bottom_in[2]:25 chany_bottom_in[2]:24 0.0045 +31 chany_bottom_in[2]:24 chany_bottom_in[2]:23 0.001517857 +32 chany_bottom_in[2]:24 chany_bottom_in[2]:13 0.02697768 +33 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.0008214286 +34 chany_bottom_in[2]:26 chany_bottom_in[2]:25 0.006120536 +35 chany_bottom_in[2]:26 chany_bottom_in[2]:5 0.0003035715 +36 chany_bottom_in[2]:33 chany_bottom_in[2]:32 0.007212541 + +*END + +*D_NET chany_bottom_in[9] 0.02098421 //LENGTH 163.000 LUMPCC 0.00359828 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 84.180 1.290 +*I mux_top_track_24\/mux_l1_in_2_:A0 I *L 0.001631 *C 76.650 60.860 +*I mux_left_track_25\/mux_l1_in_2_:A0 I *L 0.001631 *C 71.590 64.260 +*I mux_right_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 93.555 80.580 +*I FTB_32__31:A I *L 0.001776 *C 98.900 121.040 +*N chany_bottom_in[9]:5 *C 84.070 57.800 +*N chany_bottom_in[9]:6 *C 98.863 121.040 +*N chany_bottom_in[9]:7 *C 95.265 121.040 +*N chany_bottom_in[9]:8 *C 95.220 120.995 +*N chany_bottom_in[9]:9 *C 95.220 87.720 +*N chany_bottom_in[9]:10 *C 93.380 87.720 +*N chany_bottom_in[9]:11 *C 93.555 80.580 +*N chany_bottom_in[9]:12 *C 93.380 80.580 +*N chany_bottom_in[9]:13 *C 93.380 80.625 +*N chany_bottom_in[9]:14 *C 92.920 80.580 +*N chany_bottom_in[9]:15 *C 92.920 66.685 +*N chany_bottom_in[9]:16 *C 92.875 66.640 +*N chany_bottom_in[9]:17 *C 78.245 66.640 +*N chany_bottom_in[9]:18 *C 78.200 66.640 +*N chany_bottom_in[9]:19 *C 76.820 66.640 +*N chany_bottom_in[9]:20 *C 71.627 64.260 +*N chany_bottom_in[9]:21 *C 73.095 64.260 +*N chany_bottom_in[9]:22 *C 73.140 64.215 +*N chany_bottom_in[9]:23 *C 73.140 60.905 +*N chany_bottom_in[9]:24 *C 73.185 60.860 +*N chany_bottom_in[9]:25 *C 76.612 60.860 +*N chany_bottom_in[9]:26 *C 76.690 60.860 +*N chany_bottom_in[9]:27 *C 76.820 60.860 +*N chany_bottom_in[9]:28 *C 76.820 57.845 +*N chany_bottom_in[9]:29 *C 76.865 57.800 +*N chany_bottom_in[9]:30 *C 83.675 57.800 +*N chany_bottom_in[9]:31 *C 83.720 57.800 +*N chany_bottom_in[9]:32 *C 83.723 57.800 +*N chany_bottom_in[9]:33 *C 83.720 57.793 +*N chany_bottom_in[9]:34 *C 83.720 10.888 +*N chany_bottom_in[9]:35 *C 83.735 10.880 +*N chany_bottom_in[9]:36 *C 84.178 10.880 +*N chany_bottom_in[9]:37 *C 84.180 10.822 + +*CAP +0 chany_bottom_in[9] 0.0004981249 +1 mux_top_track_24\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_25\/mux_l1_in_2_:A0 1e-06 +3 mux_right_track_24\/mux_l2_in_1_:A0 1e-06 +4 FTB_32__31:A 1e-06 +5 chany_bottom_in[9]:5 7.223649e-05 +6 chany_bottom_in[9]:6 0.0001714383 +7 chany_bottom_in[9]:7 0.0001714383 +8 chany_bottom_in[9]:8 0.001712298 +9 chany_bottom_in[9]:9 0.001817529 +10 chany_bottom_in[9]:10 0.0005300759 +11 chany_bottom_in[9]:11 4.801524e-05 +12 chany_bottom_in[9]:12 5.255912e-05 +13 chany_bottom_in[9]:13 0.0004601136 +14 chany_bottom_in[9]:14 0.0008344952 +15 chany_bottom_in[9]:15 0.0007992263 +16 chany_bottom_in[9]:16 0.0005457886 +17 chany_bottom_in[9]:17 0.0005457886 +18 chany_bottom_in[9]:18 0.0001184664 +19 chany_bottom_in[9]:19 0.0004555745 +20 chany_bottom_in[9]:20 0.0001301416 +21 chany_bottom_in[9]:21 0.0001301416 +22 chany_bottom_in[9]:22 0.000243322 +23 chany_bottom_in[9]:23 0.000243322 +24 chany_bottom_in[9]:24 0.0002573406 +25 chany_bottom_in[9]:25 0.0002800112 +26 chany_bottom_in[9]:26 2.267067e-05 +27 chany_bottom_in[9]:27 0.0006093932 +28 chany_bottom_in[9]:28 0.0002057754 +29 chany_bottom_in[9]:29 0.0004497853 +30 chany_bottom_in[9]:30 0.0004497853 +31 chany_bottom_in[9]:31 3.502694e-05 +32 chany_bottom_in[9]:32 7.223649e-05 +33 chany_bottom_in[9]:33 0.002419194 +34 chany_bottom_in[9]:34 0.002419194 +35 chany_bottom_in[9]:35 4.16491e-05 +36 chany_bottom_in[9]:36 4.16491e-05 +37 chany_bottom_in[9]:37 0.0004981249 +38 chany_bottom_in[9]:33 chanx_right_in[15]:14 0.0005724113 +39 chany_bottom_in[9]:34 chanx_right_in[15]:13 0.0005724113 +40 chany_bottom_in[9]:33 chany_bottom_in[0]:16 2.758938e-05 +41 chany_bottom_in[9]:33 chany_bottom_in[0]:17 0.0002592 +42 chany_bottom_in[9]:34 chany_bottom_in[0]:18 0.0002592 +43 chany_bottom_in[9]:34 chany_bottom_in[0]:17 2.758938e-05 +44 chany_bottom_in[9]:27 mux_tree_tapbuf_size10_3_sram[0]:8 5.391469e-06 +45 chany_bottom_in[9]:17 mux_tree_tapbuf_size10_3_sram[0]:8 0.0005321774 +46 chany_bottom_in[9]:16 mux_tree_tapbuf_size10_3_sram[0]:9 0.0005321774 +47 chany_bottom_in[9]:19 mux_tree_tapbuf_size10_3_sram[0]:7 5.391469e-06 +48 chany_bottom_in[9]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.472709e-05 +49 chany_bottom_in[9]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.472709e-05 +50 chany_bottom_in[9]:17 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001269832 +51 chany_bottom_in[9]:16 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001269832 +52 chany_bottom_in[9]:29 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.71878e-05 +53 chany_bottom_in[9]:30 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.71878e-05 +54 chany_bottom_in[9]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.497977e-06 +55 chany_bottom_in[9]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.827568e-05 +56 chany_bottom_in[9]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.497977e-06 +57 chany_bottom_in[9]:15 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.30375e-05 +58 chany_bottom_in[9]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.30375e-05 +59 chany_bottom_in[9]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.827568e-05 +60 chany_bottom_in[9]:7 ropt_net_227:10 5.68637e-05 +61 chany_bottom_in[9]:8 ropt_net_227:8 1.179747e-05 +62 chany_bottom_in[9]:6 ropt_net_227:11 5.68637e-05 +63 chany_bottom_in[9]:9 ropt_net_227:9 1.179747e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:37 0.008511161 +1 chany_bottom_in[9]:29 chany_bottom_in[9]:28 0.0045 +2 chany_bottom_in[9]:28 chany_bottom_in[9]:27 0.002691964 +3 chany_bottom_in[9]:30 chany_bottom_in[9]:29 0.006080357 +4 chany_bottom_in[9]:31 chany_bottom_in[9]:30 0.0045 +5 chany_bottom_in[9]:32 chany_bottom_in[9]:31 0.00341 +6 chany_bottom_in[9]:32 chany_bottom_in[9]:5 5.103906e-05 +7 chany_bottom_in[9]:33 chany_bottom_in[9]:32 0.00341 +8 chany_bottom_in[9]:35 chany_bottom_in[9]:34 0.00341 +9 chany_bottom_in[9]:34 chany_bottom_in[9]:33 0.007348449 +10 chany_bottom_in[9]:37 chany_bottom_in[9]:36 0.00341 +11 chany_bottom_in[9]:36 chany_bottom_in[9]:35 6.499218e-05 +12 chany_bottom_in[9]:26 chany_bottom_in[9]:25 6.919643e-05 +13 chany_bottom_in[9]:27 chany_bottom_in[9]:26 0.0045 +14 chany_bottom_in[9]:27 chany_bottom_in[9]:19 0.005160714 +15 chany_bottom_in[9]:12 chany_bottom_in[9]:11 9.51087e-05 +16 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.0045 +17 chany_bottom_in[9]:13 chany_bottom_in[9]:10 0.006334822 +18 chany_bottom_in[9]:11 mux_right_track_24\/mux_l2_in_1_:A0 0.152 +19 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.0130625 +20 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.0045 +21 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.0045 +22 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.01240625 +23 chany_bottom_in[9]:25 mux_top_track_24\/mux_l1_in_2_:A0 0.152 +24 chany_bottom_in[9]:25 chany_bottom_in[9]:24 0.003060268 +25 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.003212054 +26 chany_bottom_in[9]:8 chany_bottom_in[9]:7 0.0045 +27 chany_bottom_in[9]:6 FTB_32__31:A 0.152 +28 chany_bottom_in[9]:24 chany_bottom_in[9]:23 0.0045 +29 chany_bottom_in[9]:23 chany_bottom_in[9]:22 0.002955358 +30 chany_bottom_in[9]:21 chany_bottom_in[9]:20 0.001310268 +31 chany_bottom_in[9]:22 chany_bottom_in[9]:21 0.0045 +32 chany_bottom_in[9]:20 mux_left_track_25\/mux_l1_in_2_:A0 0.152 +33 chany_bottom_in[9]:19 chany_bottom_in[9]:18 0.001232143 +34 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.0004107143 +35 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.001642857 +36 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.02970982 + +*END + +*D_NET chany_bottom_in[17] 0.03854183 //LENGTH 238.970 LUMPCC 0.00977344 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 69.920 1.290 +*I mux_right_track_16\/mux_l2_in_2_:A1 I *L 0.00198 *C 77.280 52.700 +*I mux_top_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 53.650 53.720 +*I mux_left_track_17\/mux_l2_in_2_:A1 I *L 0.00198 *C 28.425 69.020 +*I BUFT_P_127:A I *L 0.001767 *C 90.160 126.480 +*N chany_bottom_in[17]:5 *C 90.198 126.480 +*N chany_bottom_in[17]:6 *C 93.335 126.480 +*N chany_bottom_in[17]:7 *C 93.380 126.435 +*N chany_bottom_in[17]:8 *C 93.380 124.498 +*N chany_bottom_in[17]:9 *C 93.373 124.440 +*N chany_bottom_in[17]:10 *C 55.220 124.440 +*N chany_bottom_in[17]:11 *C 55.200 124.433 +*N chany_bottom_in[17]:12 *C 55.200 117.155 +*N chany_bottom_in[17]:13 *C 55.200 67.328 +*N chany_bottom_in[17]:14 *C 55.180 67.320 +*N chany_bottom_in[17]:15 *C 54.288 67.320 +*N chany_bottom_in[17]:16 *C 54.280 67.263 +*N chany_bottom_in[17]:17 *C 28.463 69.020 +*N chany_bottom_in[17]:18 *C 34.455 69.020 +*N chany_bottom_in[17]:19 *C 34.500 68.975 +*N chany_bottom_in[17]:20 *C 34.500 58.865 +*N chany_bottom_in[17]:21 *C 34.545 58.820 +*N chany_bottom_in[17]:22 *C 54.235 58.820 +*N chany_bottom_in[17]:23 *C 54.280 58.820 +*N chany_bottom_in[17]:24 *C 53.688 53.720 +*N chany_bottom_in[17]:25 *C 54.235 53.720 +*N chany_bottom_in[17]:26 *C 54.280 53.765 +*N chany_bottom_in[17]:27 *C 54.280 56.440 +*N chany_bottom_in[17]:28 *C 54.288 56.440 +*N chany_bottom_in[17]:29 *C 71.293 56.440 +*N chany_bottom_in[17]:30 *C 71.300 56.383 +*N chany_bottom_in[17]:31 *C 77.243 52.700 +*N chany_bottom_in[17]:32 *C 71.345 52.700 +*N chany_bottom_in[17]:33 *C 71.300 52.700 +*N chany_bottom_in[17]:34 *C 71.300 53.098 +*N chany_bottom_in[17]:35 *C 71.293 53.040 +*N chany_bottom_in[17]:36 *C 69.020 53.040 +*N chany_bottom_in[17]:37 *C 69.000 53.033 +*N chany_bottom_in[17]:38 *C 69.000 5.448 +*N chany_bottom_in[17]:39 *C 69.020 5.440 +*N chany_bottom_in[17]:40 *C 69.913 5.440 +*N chany_bottom_in[17]:41 *C 69.920 5.383 + +*CAP +0 chany_bottom_in[17] 0.0001703184 +1 mux_right_track_16\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_16\/mux_l2_in_1_:A0 1e-06 +3 mux_left_track_17\/mux_l2_in_2_:A1 1e-06 +4 BUFT_P_127:A 1e-06 +5 chany_bottom_in[17]:5 0.0001381362 +6 chany_bottom_in[17]:6 0.0001381362 +7 chany_bottom_in[17]:7 0.0001380157 +8 chany_bottom_in[17]:8 0.0001380157 +9 chany_bottom_in[17]:9 0.001853131 +10 chany_bottom_in[17]:10 0.001853131 +11 chany_bottom_in[17]:11 0.0006275884 +12 chany_bottom_in[17]:12 0.004474577 +13 chany_bottom_in[17]:13 0.003846989 +14 chany_bottom_in[17]:14 0.0001319657 +15 chany_bottom_in[17]:15 0.0001319657 +16 chany_bottom_in[17]:16 0.0005085373 +17 chany_bottom_in[17]:17 0.0003942875 +18 chany_bottom_in[17]:18 0.0003942875 +19 chany_bottom_in[17]:19 0.0005271101 +20 chany_bottom_in[17]:20 0.0005271101 +21 chany_bottom_in[17]:21 0.001101661 +22 chany_bottom_in[17]:22 0.001101661 +23 chany_bottom_in[17]:23 0.0006579349 +24 chany_bottom_in[17]:24 5.481284e-05 +25 chany_bottom_in[17]:25 5.481284e-05 +26 chany_bottom_in[17]:26 0.0001247293 +27 chany_bottom_in[17]:27 0.0002796398 +28 chany_bottom_in[17]:28 0.001248234 +29 chany_bottom_in[17]:29 0.001248234 +30 chany_bottom_in[17]:30 0.0002395906 +31 chany_bottom_in[17]:31 0.0004117256 +32 chany_bottom_in[17]:32 0.0004117256 +33 chany_bottom_in[17]:33 5.737428e-05 +34 chany_bottom_in[17]:34 0.0002649559 +35 chany_bottom_in[17]:35 0.0002922988 +36 chany_bottom_in[17]:36 0.0002922988 +37 chany_bottom_in[17]:37 0.002285425 +38 chany_bottom_in[17]:38 0.002285425 +39 chany_bottom_in[17]:39 9.411226e-05 +40 chany_bottom_in[17]:40 9.411226e-05 +41 chany_bottom_in[17]:41 0.0001703184 +42 chany_bottom_in[17]:37 chany_top_in[4]:17 1.341017e-05 +43 chany_bottom_in[17]:37 chany_top_in[4]:21 0.001049834 +44 chany_bottom_in[17]:38 chany_top_in[4]:16 1.341017e-05 +45 chany_bottom_in[17]:38 chany_top_in[4]:20 0.001049834 +46 chany_bottom_in[17]:10 chany_top_in[12]:45 0.0004894931 +47 chany_bottom_in[17]:9 chany_top_in[12]:44 0.0004894931 +48 chany_bottom_in[17] chany_bottom_in[14] 2.021247e-07 +49 chany_bottom_in[17]:29 chany_bottom_in[14]:41 0.0001609172 +50 chany_bottom_in[17]:28 chany_bottom_in[14]:42 0.0001609172 +51 chany_bottom_in[17]:37 chany_bottom_in[14]:43 0.0003704628 +52 chany_bottom_in[17]:38 chany_bottom_in[14]:44 0.0003704628 +53 chany_bottom_in[17]:41 chany_bottom_in[14]:47 2.021247e-07 +54 chany_bottom_in[17]:10 ropt_net_154:7 0.0003960573 +55 chany_bottom_in[17]:9 ropt_net_154:6 0.0003960573 +56 chany_bottom_in[17]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0008633768 +57 chany_bottom_in[17]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0008633768 +58 chany_bottom_in[17]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.349483e-05 +59 chany_bottom_in[17]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.898785e-05 +60 chany_bottom_in[17]:22 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.056659e-06 +61 chany_bottom_in[17]:23 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.349483e-05 +62 chany_bottom_in[17]:21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.056659e-06 +63 chany_bottom_in[17]:25 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.337807e-06 +64 chany_bottom_in[17]:26 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.898785e-05 +65 chany_bottom_in[17]:24 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.337807e-06 +66 chany_bottom_in[17]:22 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001506136 +67 chany_bottom_in[17]:21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001506136 +68 chany_bottom_in[17]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0004529703 +69 chany_bottom_in[17]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001361402 +70 chany_bottom_in[17]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 8.633822e-05 +71 chany_bottom_in[17]:22 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:19 1.062495e-05 +72 chany_bottom_in[17]:21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:18 1.062495e-05 +73 chany_bottom_in[17]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001361402 +74 chany_bottom_in[17]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0005393085 +75 chany_bottom_in[17]:20 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.59003e-05 +76 chany_bottom_in[17]:19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.59003e-05 +77 chany_bottom_in[17]:29 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001766051 +78 chany_bottom_in[17]:28 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001766051 +79 chany_bottom_in[17] ropt_net_207:8 0.0001042507 +80 chany_bottom_in[17]:41 ropt_net_207:9 0.0001042507 +81 chany_bottom_in[17]:10 ropt_net_226:6 0.000130225 +82 chany_bottom_in[17]:9 ropt_net_226:7 0.000130225 +83 chany_bottom_in[17]:6 ropt_net_245:3 9.742248e-05 +84 chany_bottom_in[17]:5 ropt_net_245:4 9.742248e-05 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:41 0.003654018 +1 chany_bottom_in[17]:30 chany_bottom_in[17]:29 0.00341 +2 chany_bottom_in[17]:29 chany_bottom_in[17]:28 0.002664116 +3 chany_bottom_in[17]:27 chany_bottom_in[17]:26 0.002388393 +4 chany_bottom_in[17]:27 chany_bottom_in[17]:23 0.002125 +5 chany_bottom_in[17]:28 chany_bottom_in[17]:27 0.00341 +6 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.00341 +7 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.000139825 +8 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.00341 +9 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.007806308 +10 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.005977225 +11 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.00341 +12 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.001729911 +13 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.00341 +14 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.002801339 +15 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.0045 +16 chany_bottom_in[17]:5 BUFT_P_127:A 0.152 +17 chany_bottom_in[17]:22 chany_bottom_in[17]:21 0.01758036 +18 chany_bottom_in[17]:23 chany_bottom_in[17]:22 0.0045 +19 chany_bottom_in[17]:23 chany_bottom_in[17]:16 0.007537947 +20 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.0045 +21 chany_bottom_in[17]:20 chany_bottom_in[17]:19 0.009026786 +22 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.005350447 +23 chany_bottom_in[17]:19 chany_bottom_in[17]:18 0.0045 +24 chany_bottom_in[17]:17 mux_left_track_17\/mux_l2_in_2_:A1 0.152 +25 chany_bottom_in[17]:25 chany_bottom_in[17]:24 0.0004888393 +26 chany_bottom_in[17]:26 chany_bottom_in[17]:25 0.0045 +27 chany_bottom_in[17]:24 mux_top_track_16\/mux_l2_in_1_:A0 0.152 +28 chany_bottom_in[17]:32 chany_bottom_in[17]:31 0.005265625 +29 chany_bottom_in[17]:33 chany_bottom_in[17]:32 0.0045 +30 chany_bottom_in[17]:31 mux_right_track_16\/mux_l2_in_2_:A1 0.152 +31 chany_bottom_in[17]:34 chany_bottom_in[17]:33 0.0001911058 +32 chany_bottom_in[17]:34 chany_bottom_in[17]:30 0.002933036 +33 chany_bottom_in[17]:35 chany_bottom_in[17]:34 0.00341 +34 chany_bottom_in[17]:36 chany_bottom_in[17]:35 0.000356025 +35 chany_bottom_in[17]:37 chany_bottom_in[17]:36 0.00341 +36 chany_bottom_in[17]:39 chany_bottom_in[17]:38 0.00341 +37 chany_bottom_in[17]:38 chany_bottom_in[17]:37 0.007454983 +38 chany_bottom_in[17]:41 chany_bottom_in[17]:40 0.00341 +39 chany_bottom_in[17]:40 chany_bottom_in[17]:39 0.000139825 +40 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.001140142 + +*END + +*D_NET chanx_left_in[9] 0.02805922 //LENGTH 167.265 LUMPCC 0.009965367 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 72.080 +*I mux_bottom_track_25\/mux_l2_in_2_:A1 I *L 0.00198 *C 32.760 66.980 +*I mux_top_track_24\/mux_l2_in_2_:A0 I *L 0.001631 *C 50.775 70.040 +*I mux_right_track_24\/mux_l2_in_2_:A0 I *L 0.001631 *C 99.535 71.400 +*I ropt_mt_inst_811:A I *L 0.001767 *C 132.020 61.200 +*N chanx_left_in[9]:5 *C 132.058 61.200 +*N chanx_left_in[9]:6 *C 132.895 61.200 +*N chanx_left_in[9]:7 *C 132.940 61.245 +*N chanx_left_in[9]:8 *C 132.940 63.535 +*N chanx_left_in[9]:9 *C 132.895 63.580 +*N chanx_left_in[9]:10 *C 128.800 63.580 +*N chanx_left_in[9]:11 *C 128.800 63.920 +*N chanx_left_in[9]:12 *C 128.363 63.920 +*N chanx_left_in[9]:13 *C 128.340 64.260 +*N chanx_left_in[9]:14 *C 128.340 64.305 +*N chanx_left_in[9]:15 *C 128.340 69.995 +*N chanx_left_in[9]:16 *C 128.295 70.040 +*N chanx_left_in[9]:17 *C 99.535 71.400 +*N chanx_left_in[9]:18 *C 99.360 71.400 +*N chanx_left_in[9]:19 *C 99.360 71.355 +*N chanx_left_in[9]:20 *C 99.360 70.085 +*N chanx_left_in[9]:21 *C 99.360 70.040 +*N chanx_left_in[9]:22 *C 90.665 70.040 +*N chanx_left_in[9]:23 *C 90.620 70.085 +*N chanx_left_in[9]:24 *C 90.620 74.062 +*N chanx_left_in[9]:25 *C 90.613 74.120 +*N chanx_left_in[9]:26 *C 49.688 74.120 +*N chanx_left_in[9]:27 *C 49.680 74.062 +*N chanx_left_in[9]:28 *C 50.738 70.040 +*N chanx_left_in[9]:29 *C 49.725 70.040 +*N chanx_left_in[9]:30 *C 49.680 70.040 +*N chanx_left_in[9]:31 *C 49.680 67.377 +*N chanx_left_in[9]:32 *C 49.672 67.320 +*N chanx_left_in[9]:33 *C 36.348 67.320 +*N chanx_left_in[9]:34 *C 36.340 67.320 +*N chanx_left_in[9]:35 *C 36.340 66.980 +*N chanx_left_in[9]:36 *C 36.295 66.980 +*N chanx_left_in[9]:37 *C 32.760 66.980 +*N chanx_left_in[9]:38 *C 30.865 66.980 +*N chanx_left_in[9]:39 *C 30.820 67.025 +*N chanx_left_in[9]:40 *C 30.820 71.695 +*N chanx_left_in[9]:41 *C 30.775 71.740 +*N chanx_left_in[9]:42 *C 28.520 71.740 +*N chanx_left_in[9]:43 *C 28.520 71.400 +*N chanx_left_in[9]:44 *C 24.885 71.400 +*N chanx_left_in[9]:45 *C 24.840 71.400 +*N chanx_left_in[9]:46 *C 24.832 71.400 +*N chanx_left_in[9]:47 *C 11.500 71.400 +*N chanx_left_in[9]:48 *C 11.500 72.080 + +*CAP +0 chanx_left_in[9] 0.0007312511 +1 mux_bottom_track_25\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_24\/mux_l2_in_2_:A0 1e-06 +3 mux_right_track_24\/mux_l2_in_2_:A0 1e-06 +4 ropt_mt_inst_811:A 1e-06 +5 chanx_left_in[9]:5 7.527616e-05 +6 chanx_left_in[9]:6 7.527616e-05 +7 chanx_left_in[9]:7 0.0001592048 +8 chanx_left_in[9]:8 0.0001592048 +9 chanx_left_in[9]:9 0.000288975 +10 chanx_left_in[9]:10 0.0003145875 +11 chanx_left_in[9]:11 6.621221e-05 +12 chanx_left_in[9]:12 6.800664e-05 +13 chanx_left_in[9]:13 6.001099e-05 +14 chanx_left_in[9]:14 0.000242601 +15 chanx_left_in[9]:15 0.000242601 +16 chanx_left_in[9]:16 0.001620641 +17 chanx_left_in[9]:17 6.196645e-05 +18 chanx_left_in[9]:18 6.230507e-05 +19 chanx_left_in[9]:19 0.0001042826 +20 chanx_left_in[9]:20 0.0001042826 +21 chanx_left_in[9]:21 0.002273562 +22 chanx_left_in[9]:22 0.0006190643 +23 chanx_left_in[9]:23 0.000258095 +24 chanx_left_in[9]:24 0.000258095 +25 chanx_left_in[9]:25 0.00186992 +26 chanx_left_in[9]:26 0.00186992 +27 chanx_left_in[9]:27 0.0002197984 +28 chanx_left_in[9]:28 9.267266e-05 +29 chanx_left_in[9]:29 9.267266e-05 +30 chanx_left_in[9]:30 0.000400653 +31 chanx_left_in[9]:31 0.0001467658 +32 chanx_left_in[9]:32 0.0004621804 +33 chanx_left_in[9]:33 0.0004621804 +34 chanx_left_in[9]:34 5.299407e-05 +35 chanx_left_in[9]:35 4.645947e-05 +36 chanx_left_in[9]:36 0.0001982986 +37 chanx_left_in[9]:37 0.0003245625 +38 chanx_left_in[9]:38 9.773731e-05 +39 chanx_left_in[9]:39 0.0003409234 +40 chanx_left_in[9]:40 0.0003409234 +41 chanx_left_in[9]:41 0.000177403 +42 chanx_left_in[9]:42 0.0002036143 +43 chanx_left_in[9]:43 0.0002941251 +44 chanx_left_in[9]:44 0.0002679138 +45 chanx_left_in[9]:45 3.708832e-05 +46 chanx_left_in[9]:46 0.0007035437 +47 chanx_left_in[9]:47 0.0007571432 +48 chanx_left_in[9]:48 0.0007848506 +49 chanx_left_in[9] chanx_right_in[6]:20 7.01161e-06 +50 chanx_left_in[9]:22 chanx_right_in[6]:29 9.558765e-06 +51 chanx_left_in[9]:23 chanx_right_in[6]:27 3.053246e-06 +52 chanx_left_in[9]:24 chanx_right_in[6]:28 3.053246e-06 +53 chanx_left_in[9]:32 chanx_right_in[6]:21 0.0002551295 +54 chanx_left_in[9]:33 chanx_right_in[6]:20 0.0002551295 +55 chanx_left_in[9]:21 chanx_right_in[6]:29 8.054712e-06 +56 chanx_left_in[9]:21 chanx_right_in[6]:30 9.558765e-06 +57 chanx_left_in[9]:16 chanx_right_in[6]:30 8.054712e-06 +58 chanx_left_in[9]:46 chanx_right_in[6]:21 9.132471e-05 +59 chanx_left_in[9]:48 chanx_right_in[6]:18 7.396848e-06 +60 chanx_left_in[9]:48 chanx_right_in[6]:21 7.01161e-06 +61 chanx_left_in[9]:47 chanx_right_in[6]:19 7.396848e-06 +62 chanx_left_in[9]:47 chanx_right_in[6]:20 9.132471e-05 +63 chanx_left_in[9]:27 chanx_right_in[16]:29 3.033004e-05 +64 chanx_left_in[9]:31 chanx_right_in[16]:30 3.22716e-05 +65 chanx_left_in[9]:30 chanx_right_in[16]:29 3.22716e-05 +66 chanx_left_in[9]:30 chanx_right_in[16]:30 3.033004e-05 +67 chanx_left_in[9]:46 chanx_right_in[16]:20 0.000243956 +68 chanx_left_in[9]:47 chanx_right_in[16]:19 0.000243956 +69 chanx_left_in[9]:25 chany_bottom_in[14]:9 0.001079466 +70 chanx_left_in[9]:25 chany_bottom_in[14]:38 0.0004599123 +71 chanx_left_in[9]:26 chany_bottom_in[14]:37 0.0004599123 +72 chanx_left_in[9]:26 chany_bottom_in[14]:38 0.001079466 +73 chanx_left_in[9] chanx_left_in[18] 9.773039e-06 +74 chanx_left_in[9]:32 chanx_left_in[18]:27 0.0007378361 +75 chanx_left_in[9]:34 chanx_left_in[18]:29 2.351587e-06 +76 chanx_left_in[9]:33 chanx_left_in[18]:28 0.0007378361 +77 chanx_left_in[9]:36 chanx_left_in[18]:31 0.0001040927 +78 chanx_left_in[9]:35 chanx_left_in[18]:30 2.351587e-06 +79 chanx_left_in[9]:20 chanx_left_in[18]:18 3.043125e-06 +80 chanx_left_in[9]:19 chanx_left_in[18]:17 3.043125e-06 +81 chanx_left_in[9]:37 chanx_left_in[18]:31 2.067088e-05 +82 chanx_left_in[9]:37 chanx_left_in[18]:36 0.0001602243 +83 chanx_left_in[9]:37 chanx_left_in[18]:32 2.344112e-06 +84 chanx_left_in[9]:38 chanx_left_in[18]:36 2.067088e-05 +85 chanx_left_in[9]:38 chanx_left_in[18]:33 2.344112e-06 +86 chanx_left_in[9]:38 chanx_left_in[18]:37 5.613166e-05 +87 chanx_left_in[9]:46 chanx_left_in[18]:40 1.700031e-06 +88 chanx_left_in[9]:48 chanx_left_in[18]:40 9.773039e-06 +89 chanx_left_in[9]:47 chanx_left_in[18] 1.700031e-06 +90 chanx_left_in[9] prog_clk[0]:669 1.377565e-05 +91 chanx_left_in[9]:25 prog_clk[0]:423 0.0004312325 +92 chanx_left_in[9]:25 prog_clk[0]:431 8.129885e-05 +93 chanx_left_in[9]:26 prog_clk[0]:431 0.0004312325 +94 chanx_left_in[9]:26 prog_clk[0]:435 8.129885e-05 +95 chanx_left_in[9]:34 prog_clk[0]:441 4.473492e-06 +96 chanx_left_in[9]:35 prog_clk[0]:440 4.473492e-06 +97 chanx_left_in[9]:44 prog_clk[0]:624 5.201346e-06 +98 chanx_left_in[9]:46 prog_clk[0]:626 6.799078e-05 +99 chanx_left_in[9]:43 prog_clk[0]:623 5.201346e-06 +100 chanx_left_in[9]:48 prog_clk[0]:668 1.377565e-05 +101 chanx_left_in[9]:47 prog_clk[0]:627 6.799078e-05 +102 chanx_left_in[9]:25 chanx_right_in[7]:19 8.146982e-06 +103 chanx_left_in[9]:25 chanx_right_in[7]:18 0.0006192823 +104 chanx_left_in[9]:26 chanx_right_in[7]:17 0.0006192823 +105 chanx_left_in[9]:26 chanx_right_in[7]:18 8.146982e-06 +106 chanx_left_in[9]:21 right_top_grid_pin_42_[0]:12 0.0003478731 +107 chanx_left_in[9]:16 right_top_grid_pin_42_[0]:13 0.0003478731 +108 chanx_left_in[9]:15 mux_tree_tapbuf_size16_1_sram[4]:7 9.787412e-05 +109 chanx_left_in[9]:14 mux_tree_tapbuf_size16_1_sram[4]:6 9.787412e-05 +110 chanx_left_in[9]:21 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 0.0001397925 +111 chanx_left_in[9]:16 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 0.0001397925 +112 chanx_left_in[9]:15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 3.327397e-07 +113 chanx_left_in[9]:14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 3.327397e-07 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:48 0.001608967 +1 chanx_left_in[9]:22 chanx_left_in[9]:21 0.007763393 +2 chanx_left_in[9]:23 chanx_left_in[9]:22 0.0045 +3 chanx_left_in[9]:24 chanx_left_in[9]:23 0.00355134 +4 chanx_left_in[9]:25 chanx_left_in[9]:24 0.00341 +5 chanx_left_in[9]:27 chanx_left_in[9]:26 0.00341 +6 chanx_left_in[9]:26 chanx_left_in[9]:25 0.006411583 +7 chanx_left_in[9]:31 chanx_left_in[9]:30 0.002377232 +8 chanx_left_in[9]:32 chanx_left_in[9]:31 0.00341 +9 chanx_left_in[9]:34 chanx_left_in[9]:33 0.00341 +10 chanx_left_in[9]:33 chanx_left_in[9]:32 0.002087583 +11 chanx_left_in[9]:36 chanx_left_in[9]:35 0.0045 +12 chanx_left_in[9]:35 chanx_left_in[9]:34 0.0001057692 +13 chanx_left_in[9]:21 chanx_left_in[9]:20 0.0045 +14 chanx_left_in[9]:21 chanx_left_in[9]:16 0.02583482 +15 chanx_left_in[9]:20 chanx_left_in[9]:19 0.001133929 +16 chanx_left_in[9]:18 chanx_left_in[9]:17 9.51087e-05 +17 chanx_left_in[9]:19 chanx_left_in[9]:18 0.0045 +18 chanx_left_in[9]:17 mux_right_track_24\/mux_l2_in_2_:A0 0.152 +19 chanx_left_in[9]:16 chanx_left_in[9]:15 0.0045 +20 chanx_left_in[9]:15 chanx_left_in[9]:14 0.005080357 +21 chanx_left_in[9]:13 chanx_left_in[9]:12 0.0001847826 +22 chanx_left_in[9]:14 chanx_left_in[9]:13 0.0045 +23 chanx_left_in[9]:9 chanx_left_in[9]:8 0.0045 +24 chanx_left_in[9]:8 chanx_left_in[9]:7 0.002044643 +25 chanx_left_in[9]:6 chanx_left_in[9]:5 0.0007477679 +26 chanx_left_in[9]:7 chanx_left_in[9]:6 0.0045 +27 chanx_left_in[9]:5 ropt_mt_inst_811:A 0.152 +28 chanx_left_in[9]:29 chanx_left_in[9]:28 0.0009040179 +29 chanx_left_in[9]:30 chanx_left_in[9]:29 0.0045 +30 chanx_left_in[9]:30 chanx_left_in[9]:27 0.003591518 +31 chanx_left_in[9]:28 mux_top_track_24\/mux_l2_in_2_:A0 0.152 +32 chanx_left_in[9]:37 mux_bottom_track_25\/mux_l2_in_2_:A1 0.152 +33 chanx_left_in[9]:37 chanx_left_in[9]:36 0.00315625 +34 chanx_left_in[9]:38 chanx_left_in[9]:37 0.001691964 +35 chanx_left_in[9]:39 chanx_left_in[9]:38 0.0045 +36 chanx_left_in[9]:41 chanx_left_in[9]:40 0.0045 +37 chanx_left_in[9]:40 chanx_left_in[9]:39 0.004169643 +38 chanx_left_in[9]:44 chanx_left_in[9]:43 0.003245536 +39 chanx_left_in[9]:45 chanx_left_in[9]:44 0.0045 +40 chanx_left_in[9]:46 chanx_left_in[9]:45 0.00341 +41 chanx_left_in[9]:43 chanx_left_in[9]:42 0.0003035714 +42 chanx_left_in[9]:42 chanx_left_in[9]:41 0.002013393 +43 chanx_left_in[9]:12 chanx_left_in[9]:11 0.000390625 +44 chanx_left_in[9]:11 chanx_left_in[9]:10 0.0003035715 +45 chanx_left_in[9]:10 chanx_left_in[9]:9 0.00365625 +46 chanx_left_in[9]:48 chanx_left_in[9]:47 0.0001065333 +47 chanx_left_in[9]:47 chanx_left_in[9]:46 0.002088758 + +*END + +*D_NET chany_top_in[3] 0.01263745 //LENGTH 71.735 LUMPCC 0.00675572 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 74.060 129.270 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 68.905 66.980 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.000 66.980 +*N chany_top_in[3]:3 *C 74.120 66.980 +*N chany_top_in[3]:4 *C 75.963 66.980 +*N chany_top_in[3]:5 *C 68.943 66.980 +*N chany_top_in[3]:6 *C 74.520 66.980 +*N chany_top_in[3]:7 *C 74.520 66.980 +*N chany_top_in[3]:8 *C 74.520 66.980 +*N chany_top_in[3]:9 *C 74.520 66.987 +*N chany_top_in[3]:10 *C 74.520 116.815 +*N chany_top_in[3]:11 *C 74.520 123.753 +*N chany_top_in[3]:12 *C 74.505 123.760 +*N chany_top_in[3]:13 *C 74.062 123.760 +*N chany_top_in[3]:14 *C 74.060 123.818 + +*CAP +0 chany_top_in[3] 0.000223435 +1 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +3 chany_top_in[3]:3 9.087146e-05 +4 chany_top_in[3]:4 5.969983e-05 +5 chany_top_in[3]:5 0.000247565 +6 chany_top_in[3]:6 0.0003426691 +7 chany_top_in[3]:7 3.686011e-05 +8 chany_top_in[3]:8 9.087146e-05 +9 chany_top_in[3]:9 0.001760331 +10 chany_top_in[3]:10 0.002173235 +11 chany_top_in[3]:11 0.0004129044 +12 chany_top_in[3]:12 0.0001089284 +13 chany_top_in[3]:13 0.0001089284 +14 chany_top_in[3]:14 0.000223435 +15 chany_top_in[3] chany_top_in[6] 2.888599e-06 +16 chany_top_in[3] chany_top_in[6]:31 0.0001313711 +17 chany_top_in[3]:4 chany_top_in[6]:13 5.426396e-06 +18 chany_top_in[3]:6 chany_top_in[6]:14 5.426396e-06 +19 chany_top_in[3]:9 chany_top_in[6]:26 0.0007622098 +20 chany_top_in[3]:14 chany_top_in[6]:30 0.0001313711 +21 chany_top_in[3]:14 chany_top_in[6]:32 2.888599e-06 +22 chany_top_in[3]:10 chany_top_in[6]:27 0.0007622098 +23 chany_top_in[3]:9 chany_top_in[18]:31 0.0009446891 +24 chany_top_in[3]:9 chany_top_in[18]:35 0.001225023 +25 chany_top_in[3]:11 chany_top_in[18]:36 1.416665e-05 +26 chany_top_in[3]:10 chany_top_in[18]:32 0.0009446891 +27 chany_top_in[3]:10 chany_top_in[18]:35 1.416665e-05 +28 chany_top_in[3]:10 chany_top_in[18]:36 0.001225023 +29 chany_top_in[3] chany_bottom_in[18]:7 2.667613e-05 +30 chany_top_in[3]:4 chany_bottom_in[18]:24 5.869707e-05 +31 chany_top_in[3]:6 chany_bottom_in[18]:24 0.0002067117 +32 chany_top_in[3]:6 chany_bottom_in[18]:25 5.869707e-05 +33 chany_top_in[3]:14 chany_bottom_in[18]:8 2.667613e-05 +34 chany_top_in[3]:5 chany_bottom_in[18]:25 0.0002067117 + +*RES +0 chany_top_in[3] chany_top_in[3]:14 0.004868304 +1 chany_top_in[3]:4 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[3]:6 chany_top_in[3]:5 0.004979911 +3 chany_top_in[3]:6 chany_top_in[3]:4 0.001287946 +4 chany_top_in[3]:7 chany_top_in[3]:6 0.0045 +5 chany_top_in[3]:8 chany_top_in[3]:7 0.00341 +6 chany_top_in[3]:8 chany_top_in[3]:3 5.69697e-05 +7 chany_top_in[3]:9 chany_top_in[3]:8 0.00341 +8 chany_top_in[3]:12 chany_top_in[3]:11 0.00341 +9 chany_top_in[3]:11 chany_top_in[3]:10 0.001086875 +10 chany_top_in[3]:14 chany_top_in[3]:13 0.00341 +11 chany_top_in[3]:13 chany_top_in[3]:12 6.499219e-05 +12 chany_top_in[3]:5 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +13 chany_top_in[3]:10 chany_top_in[3]:9 0.007806308 + +*END + +*D_NET top_left_grid_pin_36_[0] 0.006001032 //LENGTH 49.915 LUMPCC 0.0002297782 DR + +*CONN +*P top_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 127.160 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 35.250 125.800 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 59.440 110.500 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 56.715 118.660 +*N top_left_grid_pin_36_[0]:4 *C 56.678 118.660 +*N top_left_grid_pin_36_[0]:5 *C 59.403 110.500 +*N top_left_grid_pin_36_[0]:6 *C 55.705 110.500 +*N top_left_grid_pin_36_[0]:7 *C 55.660 110.545 +*N top_left_grid_pin_36_[0]:8 *C 55.660 118.615 +*N top_left_grid_pin_36_[0]:9 *C 55.660 118.660 +*N top_left_grid_pin_36_[0]:10 *C 55.660 119.000 +*N top_left_grid_pin_36_[0]:11 *C 36.385 119.000 +*N top_left_grid_pin_36_[0]:12 *C 36.340 119.045 +*N top_left_grid_pin_36_[0]:13 *C 36.340 125.755 +*N top_left_grid_pin_36_[0]:14 *C 36.295 125.800 +*N top_left_grid_pin_36_[0]:15 *C 35.250 125.800 +*N top_left_grid_pin_36_[0]:16 *C 34.545 125.800 +*N top_left_grid_pin_36_[0]:17 *C 34.500 125.845 +*N top_left_grid_pin_36_[0]:18 *C 34.500 127.103 +*N top_left_grid_pin_36_[0]:19 *C 34.492 127.160 + +*CAP +0 top_left_grid_pin_36_[0] 0.0002419895 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_36_[0]:4 9.4467e-05 +5 top_left_grid_pin_36_[0]:5 0.0002569864 +6 top_left_grid_pin_36_[0]:6 0.0002569864 +7 top_left_grid_pin_36_[0]:7 0.0004765825 +8 top_left_grid_pin_36_[0]:8 0.0004765825 +9 top_left_grid_pin_36_[0]:9 0.0001262465 +10 top_left_grid_pin_36_[0]:10 0.001253501 +11 top_left_grid_pin_36_[0]:11 0.001221721 +12 top_left_grid_pin_36_[0]:12 0.0003312547 +13 top_left_grid_pin_36_[0]:13 0.0003312547 +14 top_left_grid_pin_36_[0]:14 7.972561e-05 +15 top_left_grid_pin_36_[0]:15 0.0001630617 +16 top_left_grid_pin_36_[0]:16 5.757916e-05 +17 top_left_grid_pin_36_[0]:17 7.916315e-05 +18 top_left_grid_pin_36_[0]:18 7.916315e-05 +19 top_left_grid_pin_36_[0]:19 0.0002419895 +20 top_left_grid_pin_36_[0]:11 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:6 7.331291e-05 +21 top_left_grid_pin_36_[0]:10 mux_tree_tapbuf_size12_mem_1_ccff_tail[0]:7 7.331291e-05 +22 top_left_grid_pin_36_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.148822e-05 +23 top_left_grid_pin_36_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.0088e-05 +24 top_left_grid_pin_36_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.0088e-05 +25 top_left_grid_pin_36_[0]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.148822e-05 + +*RES +0 top_left_grid_pin_36_[0] top_left_grid_pin_36_[0]:19 0.0007429916 +1 top_left_grid_pin_36_[0]:4 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +2 top_left_grid_pin_36_[0]:14 top_left_grid_pin_36_[0]:13 0.0045 +3 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:12 0.005991072 +4 top_left_grid_pin_36_[0]:11 top_left_grid_pin_36_[0]:10 0.01720982 +5 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:11 0.0045 +6 top_left_grid_pin_36_[0]:9 top_left_grid_pin_36_[0]:8 0.0045 +7 top_left_grid_pin_36_[0]:9 top_left_grid_pin_36_[0]:4 0.0009084822 +8 top_left_grid_pin_36_[0]:8 top_left_grid_pin_36_[0]:7 0.007205357 +9 top_left_grid_pin_36_[0]:6 top_left_grid_pin_36_[0]:5 0.00330134 +10 top_left_grid_pin_36_[0]:7 top_left_grid_pin_36_[0]:6 0.0045 +11 top_left_grid_pin_36_[0]:5 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +12 top_left_grid_pin_36_[0]:16 top_left_grid_pin_36_[0]:15 0.0006294643 +13 top_left_grid_pin_36_[0]:17 top_left_grid_pin_36_[0]:16 0.0045 +14 top_left_grid_pin_36_[0]:18 top_left_grid_pin_36_[0]:17 0.001122768 +15 top_left_grid_pin_36_[0]:19 top_left_grid_pin_36_[0]:18 0.00341 +16 top_left_grid_pin_36_[0]:15 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +17 top_left_grid_pin_36_[0]:15 top_left_grid_pin_36_[0]:14 0.0009330357 +18 top_left_grid_pin_36_[0]:10 top_left_grid_pin_36_[0]:9 0.0003035715 + +*END + +*D_NET chanx_right_in[1] 0.02103393 //LENGTH 160.910 LUMPCC 0.003987526 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 140.450 99.280 +*I mux_top_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 81.880 94.180 +*I mux_bottom_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 77.185 41.820 +*N chanx_right_in[1]:3 *C 77.223 41.820 +*N chanx_right_in[1]:4 *C 84.595 41.820 +*N chanx_right_in[1]:5 *C 84.640 41.820 +*N chanx_right_in[1]:6 *C 84.640 41.480 +*N chanx_right_in[1]:7 *C 84.648 41.480 +*N chanx_right_in[1]:8 *C 109.460 41.480 +*N chanx_right_in[1]:9 *C 109.480 41.488 +*N chanx_right_in[1]:10 *C 81.918 94.180 +*N chanx_right_in[1]:11 *C 85.560 94.180 +*N chanx_right_in[1]:12 *C 85.560 93.840 +*N chanx_right_in[1]:13 *C 88.780 93.840 +*N chanx_right_in[1]:14 *C 88.780 93.500 +*N chanx_right_in[1]:15 *C 99.775 93.500 +*N chanx_right_in[1]:16 *C 99.820 93.455 +*N chanx_right_in[1]:17 *C 99.820 85.058 +*N chanx_right_in[1]:18 *C 99.828 85.000 +*N chanx_right_in[1]:19 *C 109.460 85.000 +*N chanx_right_in[1]:20 *C 109.480 85.000 +*N chanx_right_in[1]:21 *C 109.480 99.273 +*N chanx_right_in[1]:22 *C 109.500 99.280 + +*CAP +0 chanx_right_in[1] 0.001389044 +1 mux_top_track_0\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_1_:A1 1e-06 +3 chanx_right_in[1]:3 0.0003401013 +4 chanx_right_in[1]:4 0.0003401013 +5 chanx_right_in[1]:5 5.524987e-05 +6 chanx_right_in[1]:6 5.914765e-05 +7 chanx_right_in[1]:7 0.001169842 +8 chanx_right_in[1]:8 0.001169842 +9 chanx_right_in[1]:9 0.002291524 +10 chanx_right_in[1]:10 0.0003357271 +11 chanx_right_in[1]:11 0.0003625051 +12 chanx_right_in[1]:12 0.0003132544 +13 chanx_right_in[1]:13 0.0003140768 +14 chanx_right_in[1]:14 0.0006293435 +15 chanx_right_in[1]:15 0.0006017431 +16 chanx_right_in[1]:16 0.0004863876 +17 chanx_right_in[1]:17 0.0004863876 +18 chanx_right_in[1]:18 0.000767364 +19 chanx_right_in[1]:19 0.000767364 +20 chanx_right_in[1]:20 0.003033942 +21 chanx_right_in[1]:21 0.0007424173 +22 chanx_right_in[1]:22 0.001389044 +23 chanx_right_in[1] chanx_right_in[4] 1.141405e-06 +24 chanx_right_in[1] chanx_right_in[4]:30 0.0004414209 +25 chanx_right_in[1]:22 chanx_right_in[4]:29 0.0004414209 +26 chanx_right_in[1]:22 chanx_right_in[4]:35 1.141405e-06 +27 chanx_right_in[1]:8 chanx_right_in[16]:54 3.638021e-05 +28 chanx_right_in[1]:8 chanx_right_in[16]:55 0.0003014329 +29 chanx_right_in[1]:7 chanx_right_in[16]:49 3.638021e-05 +30 chanx_right_in[1]:7 chanx_right_in[16]:54 0.0003014329 +31 chanx_right_in[1]:8 chanx_right_in[11]:12 5.901255e-05 +32 chanx_right_in[1]:8 chanx_right_in[11]:13 0.0003805585 +33 chanx_right_in[1]:7 chanx_right_in[11]:12 0.0003805585 +34 chanx_right_in[1]:7 chanx_right_in[11]:7 5.901255e-05 +35 chanx_right_in[1]:4 chanx_right_in[11]:4 0.0001335849 +36 chanx_right_in[1]:3 chanx_right_in[11]:3 0.0001335849 +37 chanx_right_in[1]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001671417 +38 chanx_right_in[1]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001671417 +39 chanx_right_in[1]:20 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001496196 +40 chanx_right_in[1]:20 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0003234702 +41 chanx_right_in[1]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0003234702 +42 chanx_right_in[1]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001496196 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:22 0.004848833 +1 chanx_right_in[1]:10 mux_top_track_0\/mux_l1_in_2_:A1 0.152 +2 chanx_right_in[1]:15 chanx_right_in[1]:14 0.009816964 +3 chanx_right_in[1]:16 chanx_right_in[1]:15 0.0045 +4 chanx_right_in[1]:17 chanx_right_in[1]:16 0.007497768 +5 chanx_right_in[1]:18 chanx_right_in[1]:17 0.00341 +6 chanx_right_in[1]:19 chanx_right_in[1]:18 0.001509092 +7 chanx_right_in[1]:20 chanx_right_in[1]:19 0.00341 +8 chanx_right_in[1]:20 chanx_right_in[1]:9 0.006816958 +9 chanx_right_in[1]:8 chanx_right_in[1]:7 0.003887292 +10 chanx_right_in[1]:9 chanx_right_in[1]:8 0.00341 +11 chanx_right_in[1]:6 chanx_right_in[1]:5 0.0001634615 +12 chanx_right_in[1]:7 chanx_right_in[1]:6 0.00341 +13 chanx_right_in[1]:4 chanx_right_in[1]:3 0.006582589 +14 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0045 +15 chanx_right_in[1]:3 mux_bottom_track_17\/mux_l1_in_1_:A1 0.152 +16 chanx_right_in[1]:22 chanx_right_in[1]:21 0.00341 +17 chanx_right_in[1]:21 chanx_right_in[1]:20 0.002236025 +18 chanx_right_in[1]:11 chanx_right_in[1]:10 0.003252233 +19 chanx_right_in[1]:12 chanx_right_in[1]:11 0.0003035715 +20 chanx_right_in[1]:13 chanx_right_in[1]:12 0.002875 +21 chanx_right_in[1]:14 chanx_right_in[1]:13 0.0003035715 + +*END + +*D_NET right_top_grid_pin_46_[0] 0.008698006 //LENGTH 76.380 LUMPCC 0.0002646436 DR + +*CONN +*P right_top_grid_pin_46_[0] I *L 0.29796 *C 111.930 119.000 +*I mux_right_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 102.870 104.040 +*I mux_right_track_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 102.220 66.980 +*I mux_right_track_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 114.640 77.860 +*N right_top_grid_pin_46_[0]:4 *C 114.678 77.860 +*N right_top_grid_pin_46_[0]:5 *C 115.000 77.860 +*N right_top_grid_pin_46_[0]:6 *C 115.000 78.200 +*N right_top_grid_pin_46_[0]:7 *C 102.120 66.980 +*N right_top_grid_pin_46_[0]:8 *C 102.120 67.025 +*N right_top_grid_pin_46_[0]:9 *C 102.120 78.155 +*N right_top_grid_pin_46_[0]:10 *C 102.165 78.200 +*N right_top_grid_pin_46_[0]:11 *C 103.500 78.200 +*N right_top_grid_pin_46_[0]:12 *C 103.500 78.245 +*N right_top_grid_pin_46_[0]:13 *C 102.907 104.040 +*N right_top_grid_pin_46_[0]:14 *C 103.455 104.040 +*N right_top_grid_pin_46_[0]:15 *C 103.500 104.040 +*N right_top_grid_pin_46_[0]:16 *C 103.500 118.943 +*N right_top_grid_pin_46_[0]:17 *C 103.508 119.000 + +*CAP +0 right_top_grid_pin_46_[0] 0.0004157176 +1 mux_right_track_0\/mux_l1_in_2_:A0 1e-06 +2 mux_right_track_8\/mux_l1_in_2_:A1 1e-06 +3 mux_right_track_4\/mux_l2_in_3_:A1 1e-06 +4 right_top_grid_pin_46_[0]:4 2.776667e-05 +5 right_top_grid_pin_46_[0]:5 5.751241e-05 +6 right_top_grid_pin_46_[0]:6 0.0007722959 +7 right_top_grid_pin_46_[0]:7 3.109498e-05 +8 right_top_grid_pin_46_[0]:8 0.0006367311 +9 right_top_grid_pin_46_[0]:9 0.0006367311 +10 right_top_grid_pin_46_[0]:10 7.97875e-05 +11 right_top_grid_pin_46_[0]:11 0.0008578271 +12 right_top_grid_pin_46_[0]:12 0.001469868 +13 right_top_grid_pin_46_[0]:13 5.866589e-05 +14 right_top_grid_pin_46_[0]:14 5.866589e-05 +15 right_top_grid_pin_46_[0]:15 0.002207377 +16 right_top_grid_pin_46_[0]:16 0.0007046049 +17 right_top_grid_pin_46_[0]:17 0.0004157176 +18 right_top_grid_pin_46_[0]:16 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:5 6.434762e-05 +19 right_top_grid_pin_46_[0]:15 mux_tree_tapbuf_size12_mem_2_ccff_tail[0]:4 6.434762e-05 +20 right_top_grid_pin_46_[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 2.472914e-05 +21 right_top_grid_pin_46_[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.324506e-05 +22 right_top_grid_pin_46_[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 2.472914e-05 +23 right_top_grid_pin_46_[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.324506e-05 + +*RES +0 right_top_grid_pin_46_[0] right_top_grid_pin_46_[0]:17 0.001319525 +1 right_top_grid_pin_46_[0]:16 right_top_grid_pin_46_[0]:15 0.0133058 +2 right_top_grid_pin_46_[0]:17 right_top_grid_pin_46_[0]:16 0.00341 +3 right_top_grid_pin_46_[0]:14 right_top_grid_pin_46_[0]:13 0.0004888393 +4 right_top_grid_pin_46_[0]:15 right_top_grid_pin_46_[0]:14 0.0045 +5 right_top_grid_pin_46_[0]:15 right_top_grid_pin_46_[0]:12 0.02303125 +6 right_top_grid_pin_46_[0]:13 mux_right_track_0\/mux_l1_in_2_:A0 0.152 +7 right_top_grid_pin_46_[0]:4 mux_right_track_4\/mux_l2_in_3_:A1 0.152 +8 right_top_grid_pin_46_[0]:10 right_top_grid_pin_46_[0]:9 0.0045 +9 right_top_grid_pin_46_[0]:9 right_top_grid_pin_46_[0]:8 0.009937502 +10 right_top_grid_pin_46_[0]:7 mux_right_track_8\/mux_l1_in_2_:A1 0.152 +11 right_top_grid_pin_46_[0]:8 right_top_grid_pin_46_[0]:7 0.0045 +12 right_top_grid_pin_46_[0]:11 right_top_grid_pin_46_[0]:10 0.001191964 +13 right_top_grid_pin_46_[0]:11 right_top_grid_pin_46_[0]:6 0.01026786 +14 right_top_grid_pin_46_[0]:12 right_top_grid_pin_46_[0]:11 0.0045 +15 right_top_grid_pin_46_[0]:6 right_top_grid_pin_46_[0]:5 0.0003035715 +16 right_top_grid_pin_46_[0]:5 right_top_grid_pin_46_[0]:4 0.0002879465 + +*END + +*D_NET bottom_left_grid_pin_34_[0] 0.01432684 //LENGTH 100.060 LUMPCC 0.002963116 DR + +*CONN +*P bottom_left_grid_pin_34_[0] I *L 0.29796 *C 29.750 10.200 +*I mux_bottom_track_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 33.945 20.060 +*I mux_bottom_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 79.755 37.400 +*I mux_bottom_track_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 94.590 33.660 +*N bottom_left_grid_pin_34_[0]:4 *C 94.590 33.660 +*N bottom_left_grid_pin_34_[0]:5 *C 94.300 33.660 +*N bottom_left_grid_pin_34_[0]:6 *C 94.300 33.705 +*N bottom_left_grid_pin_34_[0]:7 *C 94.300 35.995 +*N bottom_left_grid_pin_34_[0]:8 *C 94.255 36.040 +*N bottom_left_grid_pin_34_[0]:9 *C 86.480 36.040 +*N bottom_left_grid_pin_34_[0]:10 *C 86.480 37.400 +*N bottom_left_grid_pin_34_[0]:11 *C 79.793 37.400 +*N bottom_left_grid_pin_34_[0]:12 *C 80.960 37.400 +*N bottom_left_grid_pin_34_[0]:13 *C 80.960 37.355 +*N bottom_left_grid_pin_34_[0]:14 *C 80.960 21.137 +*N bottom_left_grid_pin_34_[0]:15 *C 80.953 21.080 +*N bottom_left_grid_pin_34_[0]:16 *C 34.040 21.080 +*N bottom_left_grid_pin_34_[0]:17 *C 33.945 20.060 +*N bottom_left_grid_pin_34_[0]:18 *C 34.040 20.060 +*N bottom_left_grid_pin_34_[0]:19 *C 34.040 20.400 +*N bottom_left_grid_pin_34_[0]:20 *C 34.040 20.408 +*N bottom_left_grid_pin_34_[0]:21 *C 31.300 20.400 +*N bottom_left_grid_pin_34_[0]:22 *C 31.280 20.393 +*N bottom_left_grid_pin_34_[0]:23 *C 31.280 10.208 +*N bottom_left_grid_pin_34_[0]:24 *C 31.260 10.200 + +*CAP +0 bottom_left_grid_pin_34_[0] 0.0001206489 +1 mux_bottom_track_5\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:A0 1e-06 +3 mux_bottom_track_9\/mux_l1_in_2_:A0 1e-06 +4 bottom_left_grid_pin_34_[0]:4 5.694003e-05 +5 bottom_left_grid_pin_34_[0]:5 5.946173e-05 +6 bottom_left_grid_pin_34_[0]:6 0.000185704 +7 bottom_left_grid_pin_34_[0]:7 0.000185704 +8 bottom_left_grid_pin_34_[0]:8 0.0005749008 +9 bottom_left_grid_pin_34_[0]:9 0.0006570638 +10 bottom_left_grid_pin_34_[0]:10 0.0004529296 +11 bottom_left_grid_pin_34_[0]:11 8.523295e-05 +12 bottom_left_grid_pin_34_[0]:12 0.000487479 +13 bottom_left_grid_pin_34_[0]:13 0.0007260035 +14 bottom_left_grid_pin_34_[0]:14 0.0007260035 +15 bottom_left_grid_pin_34_[0]:15 0.00276732 +16 bottom_left_grid_pin_34_[0]:16 0.002804944 +17 bottom_left_grid_pin_34_[0]:17 2.740752e-05 +18 bottom_left_grid_pin_34_[0]:18 5.750018e-05 +19 bottom_left_grid_pin_34_[0]:19 6.020086e-05 +20 bottom_left_grid_pin_34_[0]:20 0.0002545633 +21 bottom_left_grid_pin_34_[0]:21 0.0002169396 +22 bottom_left_grid_pin_34_[0]:22 0.0003665627 +23 bottom_left_grid_pin_34_[0]:23 0.0003665627 +24 bottom_left_grid_pin_34_[0]:24 0.0001206489 +25 bottom_left_grid_pin_34_[0]:15 prog_clk[0]:336 9.476666e-05 +26 bottom_left_grid_pin_34_[0]:15 prog_clk[0]:342 0.0002254882 +27 bottom_left_grid_pin_34_[0]:15 prog_clk[0]:346 0.0002962573 +28 bottom_left_grid_pin_34_[0]:15 prog_clk[0]:352 0.0001790161 +29 bottom_left_grid_pin_34_[0]:15 prog_clk[0]:361 0.0001535673 +30 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:396 1.150309e-05 +31 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:341 9.476666e-05 +32 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:346 0.0002254882 +33 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:347 0.0002962573 +34 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:361 0.0001790161 +35 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:362 0.0001535673 +36 bottom_left_grid_pin_34_[0]:16 prog_clk[0]:399 1.150309e-05 +37 bottom_left_grid_pin_34_[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.406408e-07 +38 bottom_left_grid_pin_34_[0]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003293356 +39 bottom_left_grid_pin_34_[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003293356 +40 bottom_left_grid_pin_34_[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.406408e-07 +41 bottom_left_grid_pin_34_[0]:20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.883005e-06 +42 bottom_left_grid_pin_34_[0]:22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001825003 +43 bottom_left_grid_pin_34_[0]:23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001825003 +44 bottom_left_grid_pin_34_[0]:16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.883005e-06 + +*RES +0 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_34_[0]:24 0.0002365667 +1 bottom_left_grid_pin_34_[0]:4 mux_bottom_track_9\/mux_l1_in_2_:A0 0.152 +2 bottom_left_grid_pin_34_[0]:5 bottom_left_grid_pin_34_[0]:4 0.0001576087 +3 bottom_left_grid_pin_34_[0]:6 bottom_left_grid_pin_34_[0]:5 0.0045 +4 bottom_left_grid_pin_34_[0]:8 bottom_left_grid_pin_34_[0]:7 0.0045 +5 bottom_left_grid_pin_34_[0]:7 bottom_left_grid_pin_34_[0]:6 0.002044643 +6 bottom_left_grid_pin_34_[0]:11 mux_bottom_track_1\/mux_l1_in_2_:A0 0.152 +7 bottom_left_grid_pin_34_[0]:12 bottom_left_grid_pin_34_[0]:11 0.001042411 +8 bottom_left_grid_pin_34_[0]:12 bottom_left_grid_pin_34_[0]:10 0.004928572 +9 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:12 0.0045 +10 bottom_left_grid_pin_34_[0]:14 bottom_left_grid_pin_34_[0]:13 0.01447991 +11 bottom_left_grid_pin_34_[0]:15 bottom_left_grid_pin_34_[0]:14 0.00341 +12 bottom_left_grid_pin_34_[0]:19 bottom_left_grid_pin_34_[0]:18 0.0001634616 +13 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_34_[0]:19 0.00341 +14 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_34_[0]:16 0.0001053583 +15 bottom_left_grid_pin_34_[0]:17 mux_bottom_track_5\/mux_l2_in_2_:A1 0.152 +16 bottom_left_grid_pin_34_[0]:18 bottom_left_grid_pin_34_[0]:17 0.0045 +17 bottom_left_grid_pin_34_[0]:21 bottom_left_grid_pin_34_[0]:20 0.0004292667 +18 bottom_left_grid_pin_34_[0]:22 bottom_left_grid_pin_34_[0]:21 0.00341 +19 bottom_left_grid_pin_34_[0]:24 bottom_left_grid_pin_34_[0]:23 0.00341 +20 bottom_left_grid_pin_34_[0]:23 bottom_left_grid_pin_34_[0]:22 0.00159565 +21 bottom_left_grid_pin_34_[0]:10 bottom_left_grid_pin_34_[0]:9 0.001214286 +22 bottom_left_grid_pin_34_[0]:9 bottom_left_grid_pin_34_[0]:8 0.006941964 +23 bottom_left_grid_pin_34_[0]:16 bottom_left_grid_pin_34_[0]:15 0.007349624 + +*END + +*D_NET chanx_left_in[11] 0.02272419 //LENGTH 109.640 LUMPCC 0.01488181 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.305 36.720 +*I mux_bottom_track_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 99.190 33.660 +*I mux_top_track_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 103.215 38.760 +*N chanx_left_in[11]:3 *C 103.178 38.760 +*N chanx_left_in[11]:4 *C 99.865 38.760 +*N chanx_left_in[11]:5 *C 99.820 38.715 +*N chanx_left_in[11]:6 *C 99.228 33.660 +*N chanx_left_in[11]:7 *C 99.775 33.660 +*N chanx_left_in[11]:8 *C 99.820 33.705 +*N chanx_left_in[11]:9 *C 99.820 36.040 +*N chanx_left_in[11]:10 *C 99.812 36.040 +*N chanx_left_in[11]:11 *C 51.230 36.040 +*N chanx_left_in[11]:12 *C 1.380 36.040 + +*CAP +0 chanx_left_in[11] 4.52155e-05 +1 mux_bottom_track_9\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_8\/mux_l2_in_2_:A0 1e-06 +3 chanx_left_in[11]:3 0.000226566 +4 chanx_left_in[11]:4 0.000226566 +5 chanx_left_in[11]:5 0.0001245447 +6 chanx_left_in[11]:6 7.330046e-05 +7 chanx_left_in[11]:7 7.330046e-05 +8 chanx_left_in[11]:8 0.0001362559 +9 chanx_left_in[11]:9 0.0002949597 +10 chanx_left_in[11]:10 0.002018705 +11 chanx_left_in[11]:11 0.003297225 +12 chanx_left_in[11]:12 0.001323735 +13 chanx_left_in[11]:10 chanx_left_in[2]:25 0.001058414 +14 chanx_left_in[11]:10 chanx_left_in[2]:29 0.0002734752 +15 chanx_left_in[11]:12 chanx_left_in[2] 0.002245463 +16 chanx_left_in[11]:11 chanx_left_in[2]:26 0.001058414 +17 chanx_left_in[11]:11 chanx_left_in[2]:30 0.0002734752 +18 chanx_left_in[11]:11 chanx_left_in[2]:33 0.002245463 +19 chanx_left_in[11]:10 chanx_left_in[6]:30 4.001911e-05 +20 chanx_left_in[11]:10 chanx_left_in[6]:31 0.0004474504 +21 chanx_left_in[11]:4 chanx_left_in[6]:20 2.491647e-08 +22 chanx_left_in[11]:3 chanx_left_in[6]:21 2.491647e-08 +23 chanx_left_in[11]:12 chanx_left_in[6]:32 0.0001888553 +24 chanx_left_in[11]:11 chanx_left_in[6]:31 0.0002288744 +25 chanx_left_in[11]:11 chanx_left_in[6]:32 0.0004474504 +26 chanx_left_in[11]:8 prog_clk[0]:125 5.955054e-06 +27 chanx_left_in[11]:9 prog_clk[0]:124 7.882538e-06 +28 chanx_left_in[11]:9 prog_clk[0]:125 1.057007e-06 +29 chanx_left_in[11]:10 prog_clk[0]:224 8.240989e-06 +30 chanx_left_in[11]:10 prog_clk[0]:228 7.210866e-06 +31 chanx_left_in[11]:4 prog_clk[0]:119 5.479934e-06 +32 chanx_left_in[11]:5 prog_clk[0]:120 1.927484e-06 +33 chanx_left_in[11]:5 prog_clk[0]:124 1.057007e-06 +34 chanx_left_in[11]:3 prog_clk[0]:118 5.479934e-06 +35 chanx_left_in[11]:12 prog_clk[0]:645 0.0002775344 +36 chanx_left_in[11]:12 prog_clk[0]:705 0.0004572171 +37 chanx_left_in[11]:11 prog_clk[0]:228 8.240989e-06 +38 chanx_left_in[11]:11 prog_clk[0]:300 7.210866e-06 +39 chanx_left_in[11]:11 prog_clk[0]:644 0.0002775344 +40 chanx_left_in[11]:11 prog_clk[0]:704 0.0004572171 +41 chanx_left_in[11]:10 chanx_right_in[19]:15 0.0005165404 +42 chanx_left_in[11]:12 chanx_right_in[19]:14 0.001308032 +43 chanx_left_in[11]:11 chanx_right_in[19]:14 0.0005165404 +44 chanx_left_in[11]:11 chanx_right_in[19]:15 0.001308032 +45 chanx_left_in[11]:9 optlc_net_152:30 2.069763e-05 +46 chanx_left_in[11]:10 optlc_net_152:29 0.0001248412 +47 chanx_left_in[11]:10 optlc_net_152:27 0.0004524721 +48 chanx_left_in[11]:5 optlc_net_152:31 2.069763e-05 +49 chanx_left_in[11]:11 optlc_net_152:26 0.0004524721 +50 chanx_left_in[11]:11 optlc_net_152:28 0.0001248412 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:12 0.0001065333 +1 chanx_left_in[11]:7 chanx_left_in[11]:6 0.0004888393 +2 chanx_left_in[11]:8 chanx_left_in[11]:7 0.0045 +3 chanx_left_in[11]:6 mux_bottom_track_9\/mux_l2_in_2_:A0 0.152 +4 chanx_left_in[11]:9 chanx_left_in[11]:8 0.002084821 +5 chanx_left_in[11]:9 chanx_left_in[11]:5 0.002388393 +6 chanx_left_in[11]:10 chanx_left_in[11]:9 0.00341 +7 chanx_left_in[11]:4 chanx_left_in[11]:3 0.002957589 +8 chanx_left_in[11]:5 chanx_left_in[11]:4 0.0045 +9 chanx_left_in[11]:3 mux_top_track_8\/mux_l2_in_2_:A0 0.152 +10 chanx_left_in[11]:12 chanx_left_in[11]:11 0.007809832 +11 chanx_left_in[11]:11 chanx_left_in[11]:10 0.007611257 + +*END + +*D_NET ccff_head[0] 0.001564122 //LENGTH 11.505 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 140.450 88.400 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 129.435 88.060 +*N ccff_head[0]:2 *C 129.435 88.060 +*N ccff_head[0]:3 *C 129.720 88.060 +*N ccff_head[0]:4 *C 129.720 88.060 +*N ccff_head[0]:5 *C 129.720 88.400 +*N ccff_head[0]:6 *C 129.727 88.400 + +*CAP +0 ccff_head[0] 0.0006700846 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 5.287543e-05 +3 ccff_head[0]:3 5.64515e-05 +4 ccff_head[0]:4 5.488779e-05 +5 ccff_head[0]:5 5.873839e-05 +6 ccff_head[0]:6 0.0006700846 + +*RES +0 ccff_head[0] ccff_head[0]:6 0.001679858 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001548913 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:5 ccff_head[0]:4 0.0001634615 +5 ccff_head[0]:6 ccff_head[0]:5 0.00341 + +*END + +*D_NET chany_top_out[4] 0.001431185 //LENGTH 12.450 LUMPCC 0.0001438918 DR + +*CONN +*I mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 102.580 121.040 +*P chany_top_out[4] O *L 0.7423 *C 98.900 129.235 +*N chany_top_out[4]:2 *C 98.900 121.040 +*N chany_top_out[4]:3 *C 99.360 121.040 +*N chany_top_out[4]:4 *C 99.405 121.040 +*N chany_top_out[4]:5 *C 102.543 121.040 + +*CAP +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[4] 0.0003974565 +2 chany_top_out[4]:2 0.000432968 +3 chany_top_out[4]:3 6.938047e-05 +4 chany_top_out[4]:4 0.0001932441 +5 chany_top_out[4]:5 0.0001932441 +6 chany_top_out[4] ropt_net_231:3 7.194589e-05 +7 chany_top_out[4]:2 ropt_net_231:4 7.194589e-05 + +*RES +0 mux_top_track_8\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[4]:5 0.152 +1 chany_top_out[4]:4 chany_top_out[4]:3 0.0045 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0004107143 +3 chany_top_out[4]:5 chany_top_out[4]:4 0.002801339 +4 chany_top_out[4]:2 chany_top_out[4] 0.007316965 + +*END + +*D_NET chanx_right_out[1] 0.001462764 //LENGTH 11.000 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 130.240 82.620 +*P chanx_right_out[1] O *L 0.7423 *C 140.450 82.960 +*N chanx_right_out[1]:2 *C 134.328 82.960 +*N chanx_right_out[1]:3 *C 134.320 82.960 +*N chanx_right_out[1]:4 *C 134.320 82.620 +*N chanx_right_out[1]:5 *C 134.275 82.620 +*N chanx_right_out[1]:6 *C 130.278 82.620 + +*CAP +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[1] 0.0004052599 +2 chanx_right_out[1]:2 0.0004052599 +3 chanx_right_out[1]:3 5.36624e-05 +4 chanx_right_out[1]:4 4.974254e-05 +5 chanx_right_out[1]:5 0.0002739197 +6 chanx_right_out[1]:6 0.0002739197 + +*RES +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[1]:6 0.152 +1 chanx_right_out[1]:6 chanx_right_out[1]:5 0.003569197 +2 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +3 chanx_right_out[1]:4 chanx_right_out[1]:3 0.0001634615 +4 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +5 chanx_right_out[1]:2 chanx_right_out[1] 0.0009591916 + +*END + +*D_NET chany_bottom_out[8] 0.002802188 //LENGTH 22.440 LUMPCC 0.0002931123 DR + +*CONN +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 56.180 15.300 +*P chany_bottom_out[8] O *L 0.7423 *C 63.480 1.325 +*N chany_bottom_out[8]:2 *C 63.480 11.503 +*N chany_bottom_out[8]:3 *C 63.473 11.560 +*N chany_bottom_out[8]:4 *C 56.588 11.560 +*N chany_bottom_out[8]:5 *C 56.580 11.617 +*N chany_bottom_out[8]:6 *C 56.580 15.255 +*N chany_bottom_out[8]:7 *C 56.558 15.300 +*N chany_bottom_out[8]:8 *C 56.195 15.300 + +*CAP +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[8] 0.0005009525 +2 chany_bottom_out[8]:2 0.0005009525 +3 chany_bottom_out[8]:3 0.0004626104 +4 chany_bottom_out[8]:4 0.0004626104 +5 chany_bottom_out[8]:5 0.0002257603 +6 chany_bottom_out[8]:6 0.0002257603 +7 chany_bottom_out[8]:7 6.471463e-05 +8 chany_bottom_out[8]:8 6.471463e-05 +9 chany_bottom_out[8] mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.501284e-05 +10 chany_bottom_out[8]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 7.501284e-05 +11 chany_bottom_out[8] ropt_net_207:5 7.154333e-05 +12 chany_bottom_out[8]:2 ropt_net_207:4 7.154333e-05 + +*RES +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[8]:8 0.152 +1 chany_bottom_out[8]:2 chany_bottom_out[8] 0.009087054 +2 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.00341 +3 chany_bottom_out[8]:5 chany_bottom_out[8]:4 0.00341 +4 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.00107865 +5 chany_bottom_out[8]:7 chany_bottom_out[8]:6 0.0045 +6 chany_bottom_out[8]:6 chany_bottom_out[8]:5 0.003247768 +7 chany_bottom_out[8]:8 chany_bottom_out[8]:7 0.0001970109 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.002458471 //LENGTH 19.590 LUMPCC 0.0004001435 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 109.785 37.060 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 108.275 39.100 +*I mux_top_track_8\/mux_l3_in_1_:S I *L 0.00357 *C 112.340 41.820 +*I mux_top_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 106.620 47.600 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 106.657 47.600 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 108.560 47.600 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 108.560 47.260 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 108.975 47.260 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 109.020 47.215 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 112.303 41.820 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 109.065 41.820 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 109.020 41.820 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 108.312 39.100 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 108.975 39.100 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 109.020 39.100 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 109.020 37.105 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 109.065 37.060 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 109.748 37.060 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_top_track_8\/mux_l3_in_1_:S 1e-06 +3 mux_top_track_8\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 0.0001525923 +5 mux_tree_tapbuf_size10_0_sram[2]:5 0.0001777999 +6 mux_tree_tapbuf_size10_0_sram[2]:6 7.905567e-05 +7 mux_tree_tapbuf_size10_0_sram[2]:7 5.384805e-05 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.000329816 +9 mux_tree_tapbuf_size10_0_sram[2]:9 6.916429e-05 +10 mux_tree_tapbuf_size10_0_sram[2]:10 6.916429e-05 +11 mux_tree_tapbuf_size10_0_sram[2]:11 0.0005046664 +12 mux_tree_tapbuf_size10_0_sram[2]:12 6.159624e-05 +13 mux_tree_tapbuf_size10_0_sram[2]:13 6.159624e-05 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.0002745198 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.0001064664 +16 mux_tree_tapbuf_size10_0_sram[2]:16 5.702078e-05 +17 mux_tree_tapbuf_size10_0_sram[2]:17 5.702078e-05 +18 mux_tree_tapbuf_size10_0_sram[2]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.921724e-07 +19 mux_tree_tapbuf_size10_0_sram[2]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001353626 +20 mux_tree_tapbuf_size10_0_sram[2]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.921724e-07 +21 mux_tree_tapbuf_size10_0_sram[2]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001353626 +22 mux_tree_tapbuf_size10_0_sram[2]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.451696e-05 +23 mux_tree_tapbuf_size10_0_sram[2]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.451696e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:7 mux_tree_tapbuf_size10_0_sram[2]:6 0.0003705357 +2 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size10_0_sram[2]:4 mux_top_track_8\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.0005915179 +5 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.0045 +6 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:11 0.002428572 +7 mux_tree_tapbuf_size10_0_sram[2]:12 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +8 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.0045 +9 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.00178125 +10 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.000609375 +11 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.002890625 +12 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.0045 +13 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:8 0.004816965 +14 mux_tree_tapbuf_size10_0_sram[2]:9 mux_top_track_8\/mux_l3_in_1_:S 0.152 +15 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.001698661 +16 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.002594844 //LENGTH 18.670 LUMPCC 0.0001694192 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 45.385 53.040 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 41.495 55.420 +*I mux_top_track_16\/mux_l3_in_1_:S I *L 0.00357 *C 44.520 51.000 +*I mux_top_track_16\/mux_l3_in_0_:S I *L 0.00357 *C 48.640 52.360 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 48.602 52.360 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 44.483 51.000 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 41.458 55.420 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 40.985 55.420 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 40.940 55.375 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 40.940 51.045 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 40.985 51.000 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 43.240 51.000 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 43.240 51.045 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 43.240 52.315 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 43.285 52.360 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 44.620 52.360 +*N mux_tree_tapbuf_size10_1_sram[2]:16 *C 44.620 53.040 +*N mux_tree_tapbuf_size10_1_sram[2]:17 *C 45.348 53.040 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_top_track_16\/mux_l3_in_1_:S 1e-06 +3 mux_top_track_16\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 0.0002590862 +5 mux_tree_tapbuf_size10_1_sram[2]:5 9.837607e-05 +6 mux_tree_tapbuf_size10_1_sram[2]:6 7.322396e-05 +7 mux_tree_tapbuf_size10_1_sram[2]:7 7.322396e-05 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0002849288 +9 mux_tree_tapbuf_size10_1_sram[2]:9 0.0002849288 +10 mux_tree_tapbuf_size10_1_sram[2]:10 0.0001365613 +11 mux_tree_tapbuf_size10_1_sram[2]:11 0.0002682115 +12 mux_tree_tapbuf_size10_1_sram[2]:12 9.438083e-05 +13 mux_tree_tapbuf_size10_1_sram[2]:13 9.438083e-05 +14 mux_tree_tapbuf_size10_1_sram[2]:14 0.0001282737 +15 mux_tree_tapbuf_size10_1_sram[2]:15 0.0004311842 +16 mux_tree_tapbuf_size10_1_sram[2]:16 0.0001192445 +17 mux_tree_tapbuf_size10_1_sram[2]:17 7.542013e-05 +18 mux_tree_tapbuf_size10_1_sram[2]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.584064e-05 +19 mux_tree_tapbuf_size10_1_sram[2]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.886896e-05 +20 mux_tree_tapbuf_size10_1_sram[2]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.584064e-05 +21 mux_tree_tapbuf_size10_1_sram[2]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.886896e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:17 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:4 mux_top_track_16\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[2]:6 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +3 mux_tree_tapbuf_size10_1_sram[2]:7 mux_tree_tapbuf_size10_1_sram[2]:6 0.000421875 +4 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size10_1_sram[2]:10 mux_tree_tapbuf_size10_1_sram[2]:9 0.0045 +6 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.003866071 +7 mux_tree_tapbuf_size10_1_sram[2]:17 mux_tree_tapbuf_size10_1_sram[2]:16 0.0006495536 +8 mux_tree_tapbuf_size10_1_sram[2]:5 mux_top_track_16\/mux_l3_in_1_:S 0.152 +9 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.0045 +10 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:12 0.001133929 +11 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:10 0.002013393 +12 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:5 0.001109375 +13 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.0045 +14 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:14 0.001191964 +15 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:4 0.003555804 +16 mux_tree_tapbuf_size10_1_sram[2]:16 mux_tree_tapbuf_size10_1_sram[2]:15 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size10_4_sram[1] 0.005579977 //LENGTH 43.980 LUMPCC 0.0002955256 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 88.625 60.860 +*I mux_right_track_16\/mux_l2_in_3_:S I *L 0.00357 *C 87.500 50.660 +*I mux_right_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 79.680 50.320 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 80.670 44.540 +*I mux_right_track_16\/mux_l2_in_2_:S I *L 0.00357 *C 78.560 53.040 +*I mux_right_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 79.940 58.480 +*N mux_tree_tapbuf_size10_4_sram[1]:6 *C 79.903 58.480 +*N mux_tree_tapbuf_size10_4_sram[1]:7 *C 77.785 58.480 +*N mux_tree_tapbuf_size10_4_sram[1]:8 *C 77.740 58.435 +*N mux_tree_tapbuf_size10_4_sram[1]:9 *C 77.740 53.040 +*N mux_tree_tapbuf_size10_4_sram[1]:10 *C 78.545 53.040 +*N mux_tree_tapbuf_size10_4_sram[1]:11 *C 78.223 53.040 +*N mux_tree_tapbuf_size10_4_sram[1]:12 *C 78.200 52.995 +*N mux_tree_tapbuf_size10_4_sram[1]:13 *C 80.648 44.513 +*N mux_tree_tapbuf_size10_4_sram[1]:14 *C 80.635 44.200 +*N mux_tree_tapbuf_size10_4_sram[1]:15 *C 78.245 44.200 +*N mux_tree_tapbuf_size10_4_sram[1]:16 *C 78.200 44.245 +*N mux_tree_tapbuf_size10_4_sram[1]:17 *C 78.200 50.320 +*N mux_tree_tapbuf_size10_4_sram[1]:18 *C 78.245 50.320 +*N mux_tree_tapbuf_size10_4_sram[1]:19 *C 79.680 50.320 +*N mux_tree_tapbuf_size10_4_sram[1]:20 *C 85.560 50.320 +*N mux_tree_tapbuf_size10_4_sram[1]:21 *C 85.560 50.660 +*N mux_tree_tapbuf_size10_4_sram[1]:22 *C 87.515 50.660 +*N mux_tree_tapbuf_size10_4_sram[1]:23 *C 87.838 50.660 +*N mux_tree_tapbuf_size10_4_sram[1]:24 *C 87.860 50.660 +*N mux_tree_tapbuf_size10_4_sram[1]:25 *C 88.320 50.660 +*N mux_tree_tapbuf_size10_4_sram[1]:26 *C 88.320 60.815 +*N mux_tree_tapbuf_size10_4_sram[1]:27 *C 88.320 60.860 +*N mux_tree_tapbuf_size10_4_sram[1]:28 *C 88.625 60.860 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_16\/mux_l2_in_3_:S 1e-06 +2 mux_right_track_16\/mux_l2_in_1_:S 1e-06 +3 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_right_track_16\/mux_l2_in_2_:S 1e-06 +5 mux_right_track_16\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_4_sram[1]:6 0.000163985 +7 mux_tree_tapbuf_size10_4_sram[1]:7 0.000163985 +8 mux_tree_tapbuf_size10_4_sram[1]:8 0.0003282867 +9 mux_tree_tapbuf_size10_4_sram[1]:9 0.000363642 +10 mux_tree_tapbuf_size10_4_sram[1]:10 5.554395e-05 +11 mux_tree_tapbuf_size10_4_sram[1]:11 5.554395e-05 +12 mux_tree_tapbuf_size10_4_sram[1]:12 0.0001862337 +13 mux_tree_tapbuf_size10_4_sram[1]:13 2.872394e-05 +14 mux_tree_tapbuf_size10_4_sram[1]:14 0.0002042934 +15 mux_tree_tapbuf_size10_4_sram[1]:15 0.0001755695 +16 mux_tree_tapbuf_size10_4_sram[1]:16 0.0003650664 +17 mux_tree_tapbuf_size10_4_sram[1]:17 0.0005494706 +18 mux_tree_tapbuf_size10_4_sram[1]:18 0.0001265985 +19 mux_tree_tapbuf_size10_4_sram[1]:19 0.0005235382 +20 mux_tree_tapbuf_size10_4_sram[1]:20 0.0003928482 +21 mux_tree_tapbuf_size10_4_sram[1]:21 0.0001608002 +22 mux_tree_tapbuf_size10_4_sram[1]:22 0.0001824673 +23 mux_tree_tapbuf_size10_4_sram[1]:23 4.752362e-05 +24 mux_tree_tapbuf_size10_4_sram[1]:24 6.69826e-05 +25 mux_tree_tapbuf_size10_4_sram[1]:25 0.0005383154 +26 mux_tree_tapbuf_size10_4_sram[1]:26 0.0005039309 +27 mux_tree_tapbuf_size10_4_sram[1]:27 4.965135e-05 +28 mux_tree_tapbuf_size10_4_sram[1]:28 4.545184e-05 +29 mux_tree_tapbuf_size10_4_sram[1]:26 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.362964e-05 +30 mux_tree_tapbuf_size10_4_sram[1]:25 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.362964e-05 +31 mux_tree_tapbuf_size10_4_sram[1]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.413316e-05 +32 mux_tree_tapbuf_size10_4_sram[1]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.413316e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_4_sram[1]:28 0.152 +1 mux_tree_tapbuf_size10_4_sram[1]:10 mux_right_track_16\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_4_sram[1]:11 mux_tree_tapbuf_size10_4_sram[1]:10 0.0001752718 +3 mux_tree_tapbuf_size10_4_sram[1]:12 mux_tree_tapbuf_size10_4_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size10_4_sram[1]:12 mux_tree_tapbuf_size10_4_sram[1]:9 0.0004107143 +5 mux_tree_tapbuf_size10_4_sram[1]:13 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +6 mux_tree_tapbuf_size10_4_sram[1]:15 mux_tree_tapbuf_size10_4_sram[1]:14 0.002133929 +7 mux_tree_tapbuf_size10_4_sram[1]:16 mux_tree_tapbuf_size10_4_sram[1]:15 0.0045 +8 mux_tree_tapbuf_size10_4_sram[1]:7 mux_tree_tapbuf_size10_4_sram[1]:6 0.001890625 +9 mux_tree_tapbuf_size10_4_sram[1]:8 mux_tree_tapbuf_size10_4_sram[1]:7 0.0045 +10 mux_tree_tapbuf_size10_4_sram[1]:6 mux_right_track_16\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size10_4_sram[1]:22 mux_right_track_16\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_4_sram[1]:22 mux_tree_tapbuf_size10_4_sram[1]:21 0.001745536 +13 mux_tree_tapbuf_size10_4_sram[1]:18 mux_tree_tapbuf_size10_4_sram[1]:17 0.0045 +14 mux_tree_tapbuf_size10_4_sram[1]:17 mux_tree_tapbuf_size10_4_sram[1]:16 0.005424107 +15 mux_tree_tapbuf_size10_4_sram[1]:17 mux_tree_tapbuf_size10_4_sram[1]:12 0.002388393 +16 mux_tree_tapbuf_size10_4_sram[1]:28 mux_tree_tapbuf_size10_4_sram[1]:27 0.0001657609 +17 mux_tree_tapbuf_size10_4_sram[1]:27 mux_tree_tapbuf_size10_4_sram[1]:26 0.0045 +18 mux_tree_tapbuf_size10_4_sram[1]:26 mux_tree_tapbuf_size10_4_sram[1]:25 0.009066964 +19 mux_tree_tapbuf_size10_4_sram[1]:23 mux_tree_tapbuf_size10_4_sram[1]:22 0.0001752718 +20 mux_tree_tapbuf_size10_4_sram[1]:24 mux_tree_tapbuf_size10_4_sram[1]:23 0.0045 +21 mux_tree_tapbuf_size10_4_sram[1]:19 mux_right_track_16\/mux_l2_in_1_:S 0.152 +22 mux_tree_tapbuf_size10_4_sram[1]:19 mux_tree_tapbuf_size10_4_sram[1]:18 0.00128125 +23 mux_tree_tapbuf_size10_4_sram[1]:14 mux_tree_tapbuf_size10_4_sram[1]:13 0.0002111487 +24 mux_tree_tapbuf_size10_4_sram[1]:20 mux_tree_tapbuf_size10_4_sram[1]:19 0.00525 +25 mux_tree_tapbuf_size10_4_sram[1]:21 mux_tree_tapbuf_size10_4_sram[1]:20 0.0003035715 +26 mux_tree_tapbuf_size10_4_sram[1]:9 mux_tree_tapbuf_size10_4_sram[1]:8 0.004816964 +27 mux_tree_tapbuf_size10_4_sram[1]:25 mux_tree_tapbuf_size10_4_sram[1]:24 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size10_8_sram[1] 0.01115106 //LENGTH 71.945 LUMPCC 0.003381632 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 67.005 42.500 +*I mux_bottom_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 47.480 45.175 +*I mux_bottom_track_25\/mux_l2_in_3_:S I *L 0.00357 *C 30.720 50.320 +*I mux_bottom_track_25\/mux_l2_in_2_:S I *L 0.00357 *C 33.480 66.640 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 34.215 47.940 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 66.340 45.220 +*N mux_tree_tapbuf_size10_8_sram[1]:6 *C 66.240 45.220 +*N mux_tree_tapbuf_size10_8_sram[1]:7 *C 66.240 45.175 +*N mux_tree_tapbuf_size10_8_sram[1]:8 *C 34.215 47.940 +*N mux_tree_tapbuf_size10_8_sram[1]:9 *C 33.443 66.640 +*N mux_tree_tapbuf_size10_8_sram[1]:10 *C 30.405 66.640 +*N mux_tree_tapbuf_size10_8_sram[1]:11 *C 30.360 66.595 +*N mux_tree_tapbuf_size10_8_sram[1]:12 *C 30.360 50.365 +*N mux_tree_tapbuf_size10_8_sram[1]:13 *C 30.383 50.320 +*N mux_tree_tapbuf_size10_8_sram[1]:14 *C 30.758 50.320 +*N mux_tree_tapbuf_size10_8_sram[1]:15 *C 34.455 50.320 +*N mux_tree_tapbuf_size10_8_sram[1]:16 *C 34.500 50.275 +*N mux_tree_tapbuf_size10_8_sram[1]:17 *C 34.500 48.325 +*N mux_tree_tapbuf_size10_8_sram[1]:18 *C 34.545 48.280 +*N mux_tree_tapbuf_size10_8_sram[1]:19 *C 35.420 48.280 +*N mux_tree_tapbuf_size10_8_sram[1]:20 *C 35.420 47.940 +*N mux_tree_tapbuf_size10_8_sram[1]:21 *C 39.560 47.940 +*N mux_tree_tapbuf_size10_8_sram[1]:22 *C 39.560 48.280 +*N mux_tree_tapbuf_size10_8_sram[1]:23 *C 40.940 48.280 +*N mux_tree_tapbuf_size10_8_sram[1]:24 *C 40.940 47.940 +*N mux_tree_tapbuf_size10_8_sram[1]:25 *C 45.955 47.940 +*N mux_tree_tapbuf_size10_8_sram[1]:26 *C 46.000 47.895 +*N mux_tree_tapbuf_size10_8_sram[1]:27 *C 47.393 45.220 +*N mux_tree_tapbuf_size10_8_sram[1]:28 *C 46.045 45.220 +*N mux_tree_tapbuf_size10_8_sram[1]:29 *C 46.000 45.220 +*N mux_tree_tapbuf_size10_8_sram[1]:30 *C 46.000 44.258 +*N mux_tree_tapbuf_size10_8_sram[1]:31 *C 46.008 44.200 +*N mux_tree_tapbuf_size10_8_sram[1]:32 *C 66.233 44.200 +*N mux_tree_tapbuf_size10_8_sram[1]:33 *C 66.240 44.200 +*N mux_tree_tapbuf_size10_8_sram[1]:34 *C 66.240 42.545 +*N mux_tree_tapbuf_size10_8_sram[1]:35 *C 66.285 42.500 +*N mux_tree_tapbuf_size10_8_sram[1]:36 *C 66.968 42.500 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_25\/mux_l2_in_1_:S 1e-06 +2 mux_bottom_track_25\/mux_l2_in_3_:S 1e-06 +3 mux_bottom_track_25\/mux_l2_in_2_:S 1e-06 +4 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_8_sram[1]:6 3.129049e-05 +7 mux_tree_tapbuf_size10_8_sram[1]:7 7.038667e-05 +8 mux_tree_tapbuf_size10_8_sram[1]:8 5.195929e-05 +9 mux_tree_tapbuf_size10_8_sram[1]:9 0.0002700957 +10 mux_tree_tapbuf_size10_8_sram[1]:10 0.0002700957 +11 mux_tree_tapbuf_size10_8_sram[1]:11 0.0007340339 +12 mux_tree_tapbuf_size10_8_sram[1]:12 0.0007340339 +13 mux_tree_tapbuf_size10_8_sram[1]:13 5.733363e-05 +14 mux_tree_tapbuf_size10_8_sram[1]:14 0.0003221196 +15 mux_tree_tapbuf_size10_8_sram[1]:15 0.0002647859 +16 mux_tree_tapbuf_size10_8_sram[1]:16 0.0001273324 +17 mux_tree_tapbuf_size10_8_sram[1]:17 0.0001273324 +18 mux_tree_tapbuf_size10_8_sram[1]:18 0.0001008002 +19 mux_tree_tapbuf_size10_8_sram[1]:19 0.0001016582 +20 mux_tree_tapbuf_size10_8_sram[1]:20 0.0003024114 +21 mux_tree_tapbuf_size10_8_sram[1]:21 0.0003021649 +22 mux_tree_tapbuf_size10_8_sram[1]:22 0.0001467358 +23 mux_tree_tapbuf_size10_8_sram[1]:23 0.0001511209 +24 mux_tree_tapbuf_size10_8_sram[1]:24 0.0003940433 +25 mux_tree_tapbuf_size10_8_sram[1]:25 0.0003652826 +26 mux_tree_tapbuf_size10_8_sram[1]:26 0.000158134 +27 mux_tree_tapbuf_size10_8_sram[1]:27 0.0001079073 +28 mux_tree_tapbuf_size10_8_sram[1]:28 0.0001079073 +29 mux_tree_tapbuf_size10_8_sram[1]:29 0.0002605193 +30 mux_tree_tapbuf_size10_8_sram[1]:30 6.771096e-05 +31 mux_tree_tapbuf_size10_8_sram[1]:31 0.0008397234 +32 mux_tree_tapbuf_size10_8_sram[1]:32 0.0008397234 +33 mux_tree_tapbuf_size10_8_sram[1]:33 0.0002168136 +34 mux_tree_tapbuf_size10_8_sram[1]:34 0.000110016 +35 mux_tree_tapbuf_size10_8_sram[1]:35 6.497832e-05 +36 mux_tree_tapbuf_size10_8_sram[1]:36 6.497832e-05 +37 mux_tree_tapbuf_size10_8_sram[1]:12 chany_top_in[10]:19 6.444989e-05 +38 mux_tree_tapbuf_size10_8_sram[1]:12 chany_top_in[10]:22 0.0003635447 +39 mux_tree_tapbuf_size10_8_sram[1]:11 chany_top_in[10]:22 6.444989e-05 +40 mux_tree_tapbuf_size10_8_sram[1]:11 chany_top_in[10]:23 0.0003635447 +41 mux_tree_tapbuf_size10_8_sram[1]:32 chanx_right_in[13]:27 7.689642e-05 +42 mux_tree_tapbuf_size10_8_sram[1]:32 chanx_right_in[13]:28 0.0002510295 +43 mux_tree_tapbuf_size10_8_sram[1]:31 chanx_right_in[13]:15 7.689642e-05 +44 mux_tree_tapbuf_size10_8_sram[1]:31 chanx_right_in[13]:27 0.0002510295 +45 mux_tree_tapbuf_size10_8_sram[1]:29 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.94257e-06 +46 mux_tree_tapbuf_size10_8_sram[1]:29 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.94257e-06 +47 mux_tree_tapbuf_size10_8_sram[1]:32 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0009310106 +48 mux_tree_tapbuf_size10_8_sram[1]:30 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.94257e-06 +49 mux_tree_tapbuf_size10_8_sram[1]:31 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009310106 +50 mux_tree_tapbuf_size10_8_sram[1]:26 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.94257e-06 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_8_sram[1]:36 0.152 +1 mux_tree_tapbuf_size10_8_sram[1]:28 mux_tree_tapbuf_size10_8_sram[1]:27 0.001203125 +2 mux_tree_tapbuf_size10_8_sram[1]:29 mux_tree_tapbuf_size10_8_sram[1]:28 0.0045 +3 mux_tree_tapbuf_size10_8_sram[1]:29 mux_tree_tapbuf_size10_8_sram[1]:26 0.002388393 +4 mux_tree_tapbuf_size10_8_sram[1]:27 mux_bottom_track_25\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size10_8_sram[1]:33 mux_tree_tapbuf_size10_8_sram[1]:32 0.00341 +6 mux_tree_tapbuf_size10_8_sram[1]:33 mux_tree_tapbuf_size10_8_sram[1]:7 0.0008705358 +7 mux_tree_tapbuf_size10_8_sram[1]:32 mux_tree_tapbuf_size10_8_sram[1]:31 0.003168583 +8 mux_tree_tapbuf_size10_8_sram[1]:30 mux_tree_tapbuf_size10_8_sram[1]:29 0.000859375 +9 mux_tree_tapbuf_size10_8_sram[1]:31 mux_tree_tapbuf_size10_8_sram[1]:30 0.00341 +10 mux_tree_tapbuf_size10_8_sram[1]:15 mux_tree_tapbuf_size10_8_sram[1]:14 0.003301339 +11 mux_tree_tapbuf_size10_8_sram[1]:16 mux_tree_tapbuf_size10_8_sram[1]:15 0.0045 +12 mux_tree_tapbuf_size10_8_sram[1]:18 mux_tree_tapbuf_size10_8_sram[1]:17 0.0045 +13 mux_tree_tapbuf_size10_8_sram[1]:18 mux_tree_tapbuf_size10_8_sram[1]:8 0.0001847826 +14 mux_tree_tapbuf_size10_8_sram[1]:17 mux_tree_tapbuf_size10_8_sram[1]:16 0.001741072 +15 mux_tree_tapbuf_size10_8_sram[1]:14 mux_bottom_track_25\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size10_8_sram[1]:14 mux_tree_tapbuf_size10_8_sram[1]:13 0.0002038044 +17 mux_tree_tapbuf_size10_8_sram[1]:35 mux_tree_tapbuf_size10_8_sram[1]:34 0.0045 +18 mux_tree_tapbuf_size10_8_sram[1]:34 mux_tree_tapbuf_size10_8_sram[1]:33 0.001477679 +19 mux_tree_tapbuf_size10_8_sram[1]:36 mux_tree_tapbuf_size10_8_sram[1]:35 0.000609375 +20 mux_tree_tapbuf_size10_8_sram[1]:13 mux_tree_tapbuf_size10_8_sram[1]:12 0.0045 +21 mux_tree_tapbuf_size10_8_sram[1]:12 mux_tree_tapbuf_size10_8_sram[1]:11 0.01449107 +22 mux_tree_tapbuf_size10_8_sram[1]:10 mux_tree_tapbuf_size10_8_sram[1]:9 0.002712054 +23 mux_tree_tapbuf_size10_8_sram[1]:11 mux_tree_tapbuf_size10_8_sram[1]:10 0.0045 +24 mux_tree_tapbuf_size10_8_sram[1]:9 mux_bottom_track_25\/mux_l2_in_2_:S 0.152 +25 mux_tree_tapbuf_size10_8_sram[1]:25 mux_tree_tapbuf_size10_8_sram[1]:24 0.004477679 +26 mux_tree_tapbuf_size10_8_sram[1]:26 mux_tree_tapbuf_size10_8_sram[1]:25 0.0045 +27 mux_tree_tapbuf_size10_8_sram[1]:8 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +28 mux_tree_tapbuf_size10_8_sram[1]:6 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +29 mux_tree_tapbuf_size10_8_sram[1]:7 mux_tree_tapbuf_size10_8_sram[1]:6 0.0045 +30 mux_tree_tapbuf_size10_8_sram[1]:19 mux_tree_tapbuf_size10_8_sram[1]:18 0.00078125 +31 mux_tree_tapbuf_size10_8_sram[1]:20 mux_tree_tapbuf_size10_8_sram[1]:19 0.0003035715 +32 mux_tree_tapbuf_size10_8_sram[1]:21 mux_tree_tapbuf_size10_8_sram[1]:20 0.003696429 +33 mux_tree_tapbuf_size10_8_sram[1]:22 mux_tree_tapbuf_size10_8_sram[1]:21 0.0003035715 +34 mux_tree_tapbuf_size10_8_sram[1]:23 mux_tree_tapbuf_size10_8_sram[1]:22 0.001232143 +35 mux_tree_tapbuf_size10_8_sram[1]:24 mux_tree_tapbuf_size10_8_sram[1]:23 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size12_0_sram[2] 0.002637299 //LENGTH 21.333 LUMPCC 0.0003819418 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 81.265 120.700 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 78.375 118.660 +*I mux_top_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 76.720 112.200 +*I mux_top_track_0\/mux_l3_in_1_:S I *L 0.00357 *C 78.100 105.475 +*N mux_tree_tapbuf_size12_0_sram[2]:4 *C 78.100 105.475 +*N mux_tree_tapbuf_size12_0_sram[2]:5 *C 78.200 105.445 +*N mux_tree_tapbuf_size12_0_sram[2]:6 *C 76.758 112.200 +*N mux_tree_tapbuf_size12_0_sram[2]:7 *C 78.155 112.200 +*N mux_tree_tapbuf_size12_0_sram[2]:8 *C 78.200 112.200 +*N mux_tree_tapbuf_size12_0_sram[2]:9 *C 78.200 118.615 +*N mux_tree_tapbuf_size12_0_sram[2]:10 *C 78.200 118.660 +*N mux_tree_tapbuf_size12_0_sram[2]:11 *C 78.413 118.660 +*N mux_tree_tapbuf_size12_0_sram[2]:12 *C 79.995 118.660 +*N mux_tree_tapbuf_size12_0_sram[2]:13 *C 80.040 118.705 +*N mux_tree_tapbuf_size12_0_sram[2]:14 *C 80.040 120.655 +*N mux_tree_tapbuf_size12_0_sram[2]:15 *C 80.085 120.700 +*N mux_tree_tapbuf_size12_0_sram[2]:16 *C 81.228 120.700 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_top_track_0\/mux_l3_in_0_:S 1e-06 +3 mux_top_track_0\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size12_0_sram[2]:4 3.548193e-05 +5 mux_tree_tapbuf_size12_0_sram[2]:5 0.0003108015 +6 mux_tree_tapbuf_size12_0_sram[2]:6 0.0001276288 +7 mux_tree_tapbuf_size12_0_sram[2]:7 0.0001276288 +8 mux_tree_tapbuf_size12_0_sram[2]:8 0.000608702 +9 mux_tree_tapbuf_size12_0_sram[2]:9 0.0002690488 +10 mux_tree_tapbuf_size12_0_sram[2]:10 5.540059e-05 +11 mux_tree_tapbuf_size12_0_sram[2]:11 0.0001417498 +12 mux_tree_tapbuf_size12_0_sram[2]:12 0.0001193382 +13 mux_tree_tapbuf_size12_0_sram[2]:13 0.0001259872 +14 mux_tree_tapbuf_size12_0_sram[2]:14 0.0001259872 +15 mux_tree_tapbuf_size12_0_sram[2]:15 0.0001018013 +16 mux_tree_tapbuf_size12_0_sram[2]:16 0.0001018013 +17 mux_tree_tapbuf_size12_0_sram[2]:9 chany_top_in[12]:43 8.484932e-05 +18 mux_tree_tapbuf_size12_0_sram[2]:13 chany_top_in[12]:42 2.794623e-05 +19 mux_tree_tapbuf_size12_0_sram[2]:14 chany_top_in[12]:43 2.794623e-05 +20 mux_tree_tapbuf_size12_0_sram[2]:5 chany_top_in[12]:42 7.817536e-05 +21 mux_tree_tapbuf_size12_0_sram[2]:8 chany_top_in[12]:42 8.484932e-05 +22 mux_tree_tapbuf_size12_0_sram[2]:8 chany_top_in[12]:43 7.817536e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_0_sram[2]:16 0.152 +1 mux_tree_tapbuf_size12_0_sram[2]:10 mux_tree_tapbuf_size12_0_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size12_0_sram[2]:9 mux_tree_tapbuf_size12_0_sram[2]:8 0.005727679 +3 mux_tree_tapbuf_size12_0_sram[2]:11 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +4 mux_tree_tapbuf_size12_0_sram[2]:11 mux_tree_tapbuf_size12_0_sram[2]:10 0.0001154891 +5 mux_tree_tapbuf_size12_0_sram[2]:12 mux_tree_tapbuf_size12_0_sram[2]:11 0.001412946 +6 mux_tree_tapbuf_size12_0_sram[2]:13 mux_tree_tapbuf_size12_0_sram[2]:12 0.0045 +7 mux_tree_tapbuf_size12_0_sram[2]:15 mux_tree_tapbuf_size12_0_sram[2]:14 0.0045 +8 mux_tree_tapbuf_size12_0_sram[2]:14 mux_tree_tapbuf_size12_0_sram[2]:13 0.001741072 +9 mux_tree_tapbuf_size12_0_sram[2]:16 mux_tree_tapbuf_size12_0_sram[2]:15 0.001020089 +10 mux_tree_tapbuf_size12_0_sram[2]:4 mux_top_track_0\/mux_l3_in_1_:S 0.152 +11 mux_tree_tapbuf_size12_0_sram[2]:5 mux_tree_tapbuf_size12_0_sram[2]:4 0.0045 +12 mux_tree_tapbuf_size12_0_sram[2]:7 mux_tree_tapbuf_size12_0_sram[2]:6 0.001247768 +13 mux_tree_tapbuf_size12_0_sram[2]:8 mux_tree_tapbuf_size12_0_sram[2]:7 0.0045 +14 mux_tree_tapbuf_size12_0_sram[2]:8 mux_tree_tapbuf_size12_0_sram[2]:5 0.00603125 +15 mux_tree_tapbuf_size12_0_sram[2]:6 mux_top_track_0\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size12_3_sram[0] 0.008717523 //LENGTH 57.990 LUMPCC 0.001744652 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 108.865 107.780 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 104.135 98.940 +*I mux_right_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 89.140 94.180 +*I mux_right_track_2\/mux_l1_in_4_:S I *L 0.00357 *C 91.900 90.440 +*I mux_right_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 93.280 96.270 +*I mux_right_track_2\/mux_l1_in_2_:S I *L 0.00357 *C 114.440 93.840 +*I mux_right_track_2\/mux_l1_in_3_:S I *L 0.00357 *C 112.140 96.270 +*N mux_tree_tapbuf_size12_3_sram[0]:7 *C 112.140 96.270 +*N mux_tree_tapbuf_size12_3_sram[0]:8 *C 114.425 93.840 +*N mux_tree_tapbuf_size12_3_sram[0]:9 *C 114.103 93.840 +*N mux_tree_tapbuf_size12_3_sram[0]:10 *C 114.080 93.885 +*N mux_tree_tapbuf_size12_3_sram[0]:11 *C 114.080 96.515 +*N mux_tree_tapbuf_size12_3_sram[0]:12 *C 114.035 96.560 +*N mux_tree_tapbuf_size12_3_sram[0]:13 *C 112.140 96.560 +*N mux_tree_tapbuf_size12_3_sram[0]:14 *C 104.005 96.560 +*N mux_tree_tapbuf_size12_3_sram[0]:15 *C 103.960 96.515 +*N mux_tree_tapbuf_size12_3_sram[0]:16 *C 93.280 96.270 +*N mux_tree_tapbuf_size12_3_sram[0]:17 *C 93.280 96.270 +*N mux_tree_tapbuf_size12_3_sram[0]:18 *C 93.280 96.270 +*N mux_tree_tapbuf_size12_3_sram[0]:19 *C 91.863 90.440 +*N mux_tree_tapbuf_size12_3_sram[0]:20 *C 89.285 90.440 +*N mux_tree_tapbuf_size12_3_sram[0]:21 *C 89.240 90.485 +*N mux_tree_tapbuf_size12_3_sram[0]:22 *C 89.140 94.180 +*N mux_tree_tapbuf_size12_3_sram[0]:23 *C 89.240 94.180 +*N mux_tree_tapbuf_size12_3_sram[0]:24 *C 89.240 95.823 +*N mux_tree_tapbuf_size12_3_sram[0]:25 *C 89.248 95.880 +*N mux_tree_tapbuf_size12_3_sram[0]:26 *C 93.280 95.880 +*N mux_tree_tapbuf_size12_3_sram[0]:27 *C 103.953 95.880 +*N mux_tree_tapbuf_size12_3_sram[0]:28 *C 103.960 95.880 +*N mux_tree_tapbuf_size12_3_sram[0]:29 *C 104.420 95.880 +*N mux_tree_tapbuf_size12_3_sram[0]:30 *C 104.135 98.940 +*N mux_tree_tapbuf_size12_3_sram[0]:31 *C 104.420 98.940 +*N mux_tree_tapbuf_size12_3_sram[0]:32 *C 104.420 98.940 +*N mux_tree_tapbuf_size12_3_sram[0]:33 *C 104.420 107.735 +*N mux_tree_tapbuf_size12_3_sram[0]:34 *C 104.465 107.780 +*N mux_tree_tapbuf_size12_3_sram[0]:35 *C 108.828 107.780 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:S 1e-06 +3 mux_right_track_2\/mux_l1_in_4_:S 1e-06 +4 mux_right_track_2\/mux_l1_in_1_:S 1e-06 +5 mux_right_track_2\/mux_l1_in_2_:S 1e-06 +6 mux_right_track_2\/mux_l1_in_3_:S 1e-06 +7 mux_tree_tapbuf_size12_3_sram[0]:7 5.954093e-05 +8 mux_tree_tapbuf_size12_3_sram[0]:8 5.946953e-05 +9 mux_tree_tapbuf_size12_3_sram[0]:9 5.946953e-05 +10 mux_tree_tapbuf_size12_3_sram[0]:10 0.0001837098 +11 mux_tree_tapbuf_size12_3_sram[0]:11 0.0001837098 +12 mux_tree_tapbuf_size12_3_sram[0]:12 0.0001251664 +13 mux_tree_tapbuf_size12_3_sram[0]:13 0.0007321974 +14 mux_tree_tapbuf_size12_3_sram[0]:14 0.0005767829 +15 mux_tree_tapbuf_size12_3_sram[0]:15 5.106775e-05 +16 mux_tree_tapbuf_size12_3_sram[0]:16 3.352853e-05 +17 mux_tree_tapbuf_size12_3_sram[0]:17 4.145354e-05 +18 mux_tree_tapbuf_size12_3_sram[0]:18 3.731384e-05 +19 mux_tree_tapbuf_size12_3_sram[0]:19 0.000200425 +20 mux_tree_tapbuf_size12_3_sram[0]:20 0.000200425 +21 mux_tree_tapbuf_size12_3_sram[0]:21 0.0002376144 +22 mux_tree_tapbuf_size12_3_sram[0]:22 3.233323e-05 +23 mux_tree_tapbuf_size12_3_sram[0]:23 0.0003816367 +24 mux_tree_tapbuf_size12_3_sram[0]:24 0.0001085481 +25 mux_tree_tapbuf_size12_3_sram[0]:25 0.0003036018 +26 mux_tree_tapbuf_size12_3_sram[0]:26 0.0007616266 +27 mux_tree_tapbuf_size12_3_sram[0]:27 0.0004207111 +28 mux_tree_tapbuf_size12_3_sram[0]:28 8.860428e-05 +29 mux_tree_tapbuf_size12_3_sram[0]:29 0.0002234355 +30 mux_tree_tapbuf_size12_3_sram[0]:30 4.896925e-05 +31 mux_tree_tapbuf_size12_3_sram[0]:31 5.291109e-05 +32 mux_tree_tapbuf_size12_3_sram[0]:32 0.0007041136 +33 mux_tree_tapbuf_size12_3_sram[0]:33 0.0004863754 +34 mux_tree_tapbuf_size12_3_sram[0]:34 0.0002855652 +35 mux_tree_tapbuf_size12_3_sram[0]:35 0.0002855652 +36 mux_tree_tapbuf_size12_3_sram[0]:25 chanx_right_in[12]:29 8.844846e-05 +37 mux_tree_tapbuf_size12_3_sram[0]:27 chanx_right_in[12] 0.0005359435 +38 mux_tree_tapbuf_size12_3_sram[0]:27 chanx_right_in[12]:30 1.702493e-05 +39 mux_tree_tapbuf_size12_3_sram[0]:18 chanx_right_in[12]:30 7.916623e-07 +40 mux_tree_tapbuf_size12_3_sram[0]:26 chanx_right_in[12]:29 1.702493e-05 +41 mux_tree_tapbuf_size12_3_sram[0]:26 chanx_right_in[12]:30 8.844846e-05 +42 mux_tree_tapbuf_size12_3_sram[0]:26 chanx_right_in[12]:31 0.0005367352 +43 mux_tree_tapbuf_size12_3_sram[0]:27 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001806934 +44 mux_tree_tapbuf_size12_3_sram[0]:18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.82271e-06 +45 mux_tree_tapbuf_size12_3_sram[0]:26 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.82271e-06 +46 mux_tree_tapbuf_size12_3_sram[0]:26 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001806934 +47 mux_tree_tapbuf_size12_3_sram[0]:12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.160141e-05 +48 mux_tree_tapbuf_size12_3_sram[0]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.160141e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_3_sram[0]:35 0.152 +1 mux_tree_tapbuf_size12_3_sram[0]:24 mux_tree_tapbuf_size12_3_sram[0]:23 0.001466518 +2 mux_tree_tapbuf_size12_3_sram[0]:25 mux_tree_tapbuf_size12_3_sram[0]:24 0.00341 +3 mux_tree_tapbuf_size12_3_sram[0]:28 mux_tree_tapbuf_size12_3_sram[0]:27 0.00341 +4 mux_tree_tapbuf_size12_3_sram[0]:28 mux_tree_tapbuf_size12_3_sram[0]:15 0.0005669643 +5 mux_tree_tapbuf_size12_3_sram[0]:27 mux_tree_tapbuf_size12_3_sram[0]:26 0.001672025 +6 mux_tree_tapbuf_size12_3_sram[0]:20 mux_tree_tapbuf_size12_3_sram[0]:19 0.002301339 +7 mux_tree_tapbuf_size12_3_sram[0]:21 mux_tree_tapbuf_size12_3_sram[0]:20 0.0045 +8 mux_tree_tapbuf_size12_3_sram[0]:19 mux_right_track_2\/mux_l1_in_4_:S 0.152 +9 mux_tree_tapbuf_size12_3_sram[0]:16 mux_right_track_2\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size12_3_sram[0]:17 mux_tree_tapbuf_size12_3_sram[0]:16 0.0045 +11 mux_tree_tapbuf_size12_3_sram[0]:18 mux_tree_tapbuf_size12_3_sram[0]:17 0.00341 +12 mux_tree_tapbuf_size12_3_sram[0]:7 mux_right_track_2\/mux_l1_in_3_:S 0.152 +13 mux_tree_tapbuf_size12_3_sram[0]:31 mux_tree_tapbuf_size12_3_sram[0]:30 0.0001548913 +14 mux_tree_tapbuf_size12_3_sram[0]:32 mux_tree_tapbuf_size12_3_sram[0]:31 0.0045 +15 mux_tree_tapbuf_size12_3_sram[0]:32 mux_tree_tapbuf_size12_3_sram[0]:29 0.002732143 +16 mux_tree_tapbuf_size12_3_sram[0]:30 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +17 mux_tree_tapbuf_size12_3_sram[0]:22 mux_right_track_2\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size12_3_sram[0]:23 mux_tree_tapbuf_size12_3_sram[0]:22 0.0045 +19 mux_tree_tapbuf_size12_3_sram[0]:23 mux_tree_tapbuf_size12_3_sram[0]:21 0.003299107 +20 mux_tree_tapbuf_size12_3_sram[0]:14 mux_tree_tapbuf_size12_3_sram[0]:13 0.007263393 +21 mux_tree_tapbuf_size12_3_sram[0]:15 mux_tree_tapbuf_size12_3_sram[0]:14 0.0045 +22 mux_tree_tapbuf_size12_3_sram[0]:34 mux_tree_tapbuf_size12_3_sram[0]:33 0.0045 +23 mux_tree_tapbuf_size12_3_sram[0]:33 mux_tree_tapbuf_size12_3_sram[0]:32 0.007852679 +24 mux_tree_tapbuf_size12_3_sram[0]:35 mux_tree_tapbuf_size12_3_sram[0]:34 0.003895089 +25 mux_tree_tapbuf_size12_3_sram[0]:8 mux_right_track_2\/mux_l1_in_2_:S 0.152 +26 mux_tree_tapbuf_size12_3_sram[0]:9 mux_tree_tapbuf_size12_3_sram[0]:8 0.0001752718 +27 mux_tree_tapbuf_size12_3_sram[0]:10 mux_tree_tapbuf_size12_3_sram[0]:9 0.0045 +28 mux_tree_tapbuf_size12_3_sram[0]:12 mux_tree_tapbuf_size12_3_sram[0]:11 0.0045 +29 mux_tree_tapbuf_size12_3_sram[0]:11 mux_tree_tapbuf_size12_3_sram[0]:10 0.002348214 +30 mux_tree_tapbuf_size12_3_sram[0]:13 mux_tree_tapbuf_size12_3_sram[0]:12 0.001691964 +31 mux_tree_tapbuf_size12_3_sram[0]:13 mux_tree_tapbuf_size12_3_sram[0]:7 0.000125 +32 mux_tree_tapbuf_size12_3_sram[0]:29 mux_tree_tapbuf_size12_3_sram[0]:28 0.0004107143 +33 mux_tree_tapbuf_size12_3_sram[0]:26 mux_tree_tapbuf_size12_3_sram[0]:25 0.0006317583 +34 mux_tree_tapbuf_size12_3_sram[0]:26 mux_tree_tapbuf_size12_3_sram[0]:18 5.554545e-05 + +*END + +*D_NET mux_tree_tapbuf_size12_6_sram[2] 0.004619775 //LENGTH 30.667 LUMPCC 0.001152692 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 35.725 82.960 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 25.015 86.020 +*I mux_left_track_1\/mux_l3_in_1_:S I *L 0.00357 *C 19.680 85.000 +*I mux_left_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 43.800 83.640 +*N mux_tree_tapbuf_size12_6_sram[2]:4 *C 43.763 83.640 +*N mux_tree_tapbuf_size12_6_sram[2]:5 *C 19.680 85.000 +*N mux_tree_tapbuf_size12_6_sram[2]:6 *C 19.780 85.000 +*N mux_tree_tapbuf_size12_6_sram[2]:7 *C 19.788 85.000 +*N mux_tree_tapbuf_size12_6_sram[2]:8 *C 24.832 85.000 +*N mux_tree_tapbuf_size12_6_sram[2]:9 *C 24.840 85.058 +*N mux_tree_tapbuf_size12_6_sram[2]:10 *C 24.840 85.975 +*N mux_tree_tapbuf_size12_6_sram[2]:11 *C 24.840 86.020 +*N mux_tree_tapbuf_size12_6_sram[2]:12 *C 25.053 86.020 +*N mux_tree_tapbuf_size12_6_sram[2]:13 *C 36.295 86.020 +*N mux_tree_tapbuf_size12_6_sram[2]:14 *C 36.340 85.975 +*N mux_tree_tapbuf_size12_6_sram[2]:15 *C 36.340 83.685 +*N mux_tree_tapbuf_size12_6_sram[2]:16 *C 36.340 83.640 +*N mux_tree_tapbuf_size12_6_sram[2]:17 *C 36.340 82.960 +*N mux_tree_tapbuf_size12_6_sram[2]:18 *C 35.763 82.960 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_left_track_1\/mux_l3_in_1_:S 1e-06 +3 mux_left_track_1\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size12_6_sram[2]:4 0.0003872903 +5 mux_tree_tapbuf_size12_6_sram[2]:5 3.242789e-05 +6 mux_tree_tapbuf_size12_6_sram[2]:6 3.820194e-05 +7 mux_tree_tapbuf_size12_6_sram[2]:7 0.0002602446 +8 mux_tree_tapbuf_size12_6_sram[2]:8 0.0002602446 +9 mux_tree_tapbuf_size12_6_sram[2]:9 8.949351e-05 +10 mux_tree_tapbuf_size12_6_sram[2]:10 8.949351e-05 +11 mux_tree_tapbuf_size12_6_sram[2]:11 5.126223e-05 +12 mux_tree_tapbuf_size12_6_sram[2]:12 0.0007152912 +13 mux_tree_tapbuf_size12_6_sram[2]:13 0.0006949084 +14 mux_tree_tapbuf_size12_6_sram[2]:14 0.000106395 +15 mux_tree_tapbuf_size12_6_sram[2]:15 0.000106395 +16 mux_tree_tapbuf_size12_6_sram[2]:16 0.0004398575 +17 mux_tree_tapbuf_size12_6_sram[2]:17 0.0001220726 +18 mux_tree_tapbuf_size12_6_sram[2]:18 6.950537e-05 +19 mux_tree_tapbuf_size12_6_sram[2]:13 chanx_left_in[4]:40 6.166386e-06 +20 mux_tree_tapbuf_size12_6_sram[2]:8 chanx_left_in[4]:44 0.0002849341 +21 mux_tree_tapbuf_size12_6_sram[2]:7 chanx_left_in[4]:45 0.0002849341 +22 mux_tree_tapbuf_size12_6_sram[2]:12 chanx_left_in[4]:41 6.166386e-06 +23 mux_tree_tapbuf_size12_6_sram[2]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:14 0.0002177827 +24 mux_tree_tapbuf_size12_6_sram[2]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:15 0.0002177827 +25 mux_tree_tapbuf_size12_6_sram[2]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.746253e-05 +26 mux_tree_tapbuf_size12_6_sram[2]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.746253e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_6_sram[2]:18 0.152 +1 mux_tree_tapbuf_size12_6_sram[2]:13 mux_tree_tapbuf_size12_6_sram[2]:12 0.01003795 +2 mux_tree_tapbuf_size12_6_sram[2]:14 mux_tree_tapbuf_size12_6_sram[2]:13 0.0045 +3 mux_tree_tapbuf_size12_6_sram[2]:16 mux_tree_tapbuf_size12_6_sram[2]:15 0.0045 +4 mux_tree_tapbuf_size12_6_sram[2]:16 mux_tree_tapbuf_size12_6_sram[2]:4 0.006627232 +5 mux_tree_tapbuf_size12_6_sram[2]:15 mux_tree_tapbuf_size12_6_sram[2]:14 0.002044643 +6 mux_tree_tapbuf_size12_6_sram[2]:11 mux_tree_tapbuf_size12_6_sram[2]:10 0.0045 +7 mux_tree_tapbuf_size12_6_sram[2]:10 mux_tree_tapbuf_size12_6_sram[2]:9 0.0008191965 +8 mux_tree_tapbuf_size12_6_sram[2]:9 mux_tree_tapbuf_size12_6_sram[2]:8 0.00341 +9 mux_tree_tapbuf_size12_6_sram[2]:8 mux_tree_tapbuf_size12_6_sram[2]:7 0.0007903833 +10 mux_tree_tapbuf_size12_6_sram[2]:6 mux_tree_tapbuf_size12_6_sram[2]:5 0.0045 +11 mux_tree_tapbuf_size12_6_sram[2]:7 mux_tree_tapbuf_size12_6_sram[2]:6 0.00341 +12 mux_tree_tapbuf_size12_6_sram[2]:5 mux_left_track_1\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size12_6_sram[2]:12 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +14 mux_tree_tapbuf_size12_6_sram[2]:12 mux_tree_tapbuf_size12_6_sram[2]:11 0.0001154891 +15 mux_tree_tapbuf_size12_6_sram[2]:18 mux_tree_tapbuf_size12_6_sram[2]:17 0.000515625 +16 mux_tree_tapbuf_size12_6_sram[2]:4 mux_left_track_1\/mux_l3_in_0_:S 0.152 +17 mux_tree_tapbuf_size12_6_sram[2]:17 mux_tree_tapbuf_size12_6_sram[2]:16 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_6_ccff_tail[0] 0.0003133158 //LENGTH 2.005 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/FTB_7__58:X O *L 0 *C 30.175 91.535 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 31.890 91.460 +*N mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:2 *C 31.853 91.460 +*N mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:3 *C 30.175 91.535 + +*CAP +0 mem_left_track_1\/FTB_7__58:X 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:2 0.0001316898 +3 mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:3 0.000179626 + +*RES +0 mem_left_track_1\/FTB_7__58:X mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:2 0.001497768 +2 mux_tree_tapbuf_size12_mem_6_ccff_tail[0]:2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size16_0_sram[2] 0.006724313 //LENGTH 53.450 LUMPCC 0.001070072 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.485 115.260 +*I mux_top_track_4\/mux_l3_in_1_:S I *L 0.00357 *C 35.320 106.760 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 32.835 104.380 +*I mux_top_track_4\/mux_l3_in_2_:S I *L 0.00357 *C 42.420 85.680 +*I mux_top_track_4\/mux_l3_in_3_:S I *L 0.00357 *C 39.000 94.135 +*I mux_top_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 35.780 118.320 +*N mux_tree_tapbuf_size16_0_sram[2]:6 *C 35.818 118.320 +*N mux_tree_tapbuf_size16_0_sram[2]:7 *C 38.595 118.320 +*N mux_tree_tapbuf_size16_0_sram[2]:8 *C 38.640 118.275 +*N mux_tree_tapbuf_size16_0_sram[2]:9 *C 38.640 115.305 +*N mux_tree_tapbuf_size16_0_sram[2]:10 *C 38.517 115.260 +*N mux_tree_tapbuf_size16_0_sram[2]:11 *C 39.000 94.135 +*N mux_tree_tapbuf_size16_0_sram[2]:12 *C 42.320 85.680 +*N mux_tree_tapbuf_size16_0_sram[2]:13 *C 42.320 85.725 +*N mux_tree_tapbuf_size16_0_sram[2]:14 *C 42.320 91.075 +*N mux_tree_tapbuf_size16_0_sram[2]:15 *C 42.275 91.120 +*N mux_tree_tapbuf_size16_0_sram[2]:16 *C 39.145 91.120 +*N mux_tree_tapbuf_size16_0_sram[2]:17 *C 39.100 91.165 +*N mux_tree_tapbuf_size16_0_sram[2]:18 *C 39.100 93.795 +*N mux_tree_tapbuf_size16_0_sram[2]:19 *C 39.043 93.870 +*N mux_tree_tapbuf_size16_0_sram[2]:20 *C 38.962 93.840 +*N mux_tree_tapbuf_size16_0_sram[2]:21 *C 34.545 93.840 +*N mux_tree_tapbuf_size16_0_sram[2]:22 *C 34.500 93.885 +*N mux_tree_tapbuf_size16_0_sram[2]:23 *C 32.873 104.380 +*N mux_tree_tapbuf_size16_0_sram[2]:24 *C 34.455 104.380 +*N mux_tree_tapbuf_size16_0_sram[2]:25 *C 34.500 104.380 +*N mux_tree_tapbuf_size16_0_sram[2]:26 *C 34.500 106.760 +*N mux_tree_tapbuf_size16_0_sram[2]:27 *C 35.305 106.760 +*N mux_tree_tapbuf_size16_0_sram[2]:28 *C 34.983 106.760 +*N mux_tree_tapbuf_size16_0_sram[2]:29 *C 34.960 106.805 +*N mux_tree_tapbuf_size16_0_sram[2]:30 *C 34.960 115.215 +*N mux_tree_tapbuf_size16_0_sram[2]:31 *C 35.005 115.260 +*N mux_tree_tapbuf_size16_0_sram[2]:32 *C 38.448 115.260 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_4\/mux_l3_in_1_:S 1e-06 +2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_top_track_4\/mux_l3_in_2_:S 1e-06 +4 mux_top_track_4\/mux_l3_in_3_:S 1e-06 +5 mux_top_track_4\/mux_l3_in_0_:S 1e-06 +6 mux_tree_tapbuf_size16_0_sram[2]:6 0.000159978 +7 mux_tree_tapbuf_size16_0_sram[2]:7 0.000159978 +8 mux_tree_tapbuf_size16_0_sram[2]:8 0.0001361945 +9 mux_tree_tapbuf_size16_0_sram[2]:9 0.0001361945 +10 mux_tree_tapbuf_size16_0_sram[2]:10 2.600767e-05 +11 mux_tree_tapbuf_size16_0_sram[2]:11 5.058727e-05 +12 mux_tree_tapbuf_size16_0_sram[2]:12 3.553836e-05 +13 mux_tree_tapbuf_size16_0_sram[2]:13 0.0002757658 +14 mux_tree_tapbuf_size16_0_sram[2]:14 0.0002757658 +15 mux_tree_tapbuf_size16_0_sram[2]:15 0.0001653539 +16 mux_tree_tapbuf_size16_0_sram[2]:16 0.0001653539 +17 mux_tree_tapbuf_size16_0_sram[2]:17 0.0001608315 +18 mux_tree_tapbuf_size16_0_sram[2]:18 0.0001608315 +19 mux_tree_tapbuf_size16_0_sram[2]:19 4.018175e-05 +20 mux_tree_tapbuf_size16_0_sram[2]:20 0.0002367497 +21 mux_tree_tapbuf_size16_0_sram[2]:21 0.0002196665 +22 mux_tree_tapbuf_size16_0_sram[2]:22 0.0005830661 +23 mux_tree_tapbuf_size16_0_sram[2]:23 0.0001479005 +24 mux_tree_tapbuf_size16_0_sram[2]:24 0.0001479005 +25 mux_tree_tapbuf_size16_0_sram[2]:25 0.0007516276 +26 mux_tree_tapbuf_size16_0_sram[2]:26 0.0001679708 +27 mux_tree_tapbuf_size16_0_sram[2]:27 4.900622e-05 +28 mux_tree_tapbuf_size16_0_sram[2]:28 4.900622e-05 +29 mux_tree_tapbuf_size16_0_sram[2]:29 0.0004107881 +30 mux_tree_tapbuf_size16_0_sram[2]:30 0.0003784294 +31 mux_tree_tapbuf_size16_0_sram[2]:31 0.0002657801 +32 mux_tree_tapbuf_size16_0_sram[2]:32 0.0002917878 +33 mux_tree_tapbuf_size16_0_sram[2]:29 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 4.166293e-05 +34 mux_tree_tapbuf_size16_0_sram[2]:30 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 4.166293e-05 +35 mux_tree_tapbuf_size16_0_sram[2]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0001277817 +36 mux_tree_tapbuf_size16_0_sram[2]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0001277817 +37 mux_tree_tapbuf_size16_0_sram[2]:29 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001436321 +38 mux_tree_tapbuf_size16_0_sram[2]:30 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001387189 +39 mux_tree_tapbuf_size16_0_sram[2]:26 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.913185e-06 +40 mux_tree_tapbuf_size16_0_sram[2]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.063495e-06 +41 mux_tree_tapbuf_size16_0_sram[2]:17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.063495e-06 +42 mux_tree_tapbuf_size16_0_sram[2]:21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.555136e-05 +43 mux_tree_tapbuf_size16_0_sram[2]:22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.212549e-06 +44 mux_tree_tapbuf_size16_0_sram[2]:25 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.212549e-06 +45 mux_tree_tapbuf_size16_0_sram[2]:20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 6.555136e-05 +46 mux_tree_tapbuf_size16_0_sram[2]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 6.423383e-05 +47 mux_tree_tapbuf_size16_0_sram[2]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.175538e-05 +48 mux_tree_tapbuf_size16_0_sram[2]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 6.423383e-05 +49 mux_tree_tapbuf_size16_0_sram[2]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 3.175538e-05 +50 mux_tree_tapbuf_size16_0_sram[2]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.814247e-05 +51 mux_tree_tapbuf_size16_0_sram[2]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.814247e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size16_0_sram[2]:32 0.152 +1 mux_tree_tapbuf_size16_0_sram[2]:19 mux_tree_tapbuf_size16_0_sram[2]:18 0.0045 +2 mux_tree_tapbuf_size16_0_sram[2]:19 mux_tree_tapbuf_size16_0_sram[2]:11 0.0001142242 +3 mux_tree_tapbuf_size16_0_sram[2]:18 mux_tree_tapbuf_size16_0_sram[2]:17 0.002348214 +4 mux_tree_tapbuf_size16_0_sram[2]:16 mux_tree_tapbuf_size16_0_sram[2]:15 0.002794643 +5 mux_tree_tapbuf_size16_0_sram[2]:17 mux_tree_tapbuf_size16_0_sram[2]:16 0.0045 +6 mux_tree_tapbuf_size16_0_sram[2]:15 mux_tree_tapbuf_size16_0_sram[2]:14 0.0045 +7 mux_tree_tapbuf_size16_0_sram[2]:14 mux_tree_tapbuf_size16_0_sram[2]:13 0.004776786 +8 mux_tree_tapbuf_size16_0_sram[2]:12 mux_top_track_4\/mux_l3_in_2_:S 0.152 +9 mux_tree_tapbuf_size16_0_sram[2]:13 mux_tree_tapbuf_size16_0_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size16_0_sram[2]:27 mux_top_track_4\/mux_l3_in_1_:S 0.152 +11 mux_tree_tapbuf_size16_0_sram[2]:28 mux_tree_tapbuf_size16_0_sram[2]:27 0.0001752718 +12 mux_tree_tapbuf_size16_0_sram[2]:29 mux_tree_tapbuf_size16_0_sram[2]:28 0.0045 +13 mux_tree_tapbuf_size16_0_sram[2]:29 mux_tree_tapbuf_size16_0_sram[2]:26 0.0004107143 +14 mux_tree_tapbuf_size16_0_sram[2]:21 mux_tree_tapbuf_size16_0_sram[2]:20 0.003944197 +15 mux_tree_tapbuf_size16_0_sram[2]:22 mux_tree_tapbuf_size16_0_sram[2]:21 0.0045 +16 mux_tree_tapbuf_size16_0_sram[2]:11 mux_top_track_4\/mux_l3_in_3_:S 0.152 +17 mux_tree_tapbuf_size16_0_sram[2]:31 mux_tree_tapbuf_size16_0_sram[2]:30 0.0045 +18 mux_tree_tapbuf_size16_0_sram[2]:30 mux_tree_tapbuf_size16_0_sram[2]:29 0.007508929 +19 mux_tree_tapbuf_size16_0_sram[2]:10 mux_tree_tapbuf_size16_0_sram[2]:9 0.0045 +20 mux_tree_tapbuf_size16_0_sram[2]:9 mux_tree_tapbuf_size16_0_sram[2]:8 0.002651786 +21 mux_tree_tapbuf_size16_0_sram[2]:7 mux_tree_tapbuf_size16_0_sram[2]:6 0.002479911 +22 mux_tree_tapbuf_size16_0_sram[2]:8 mux_tree_tapbuf_size16_0_sram[2]:7 0.0045 +23 mux_tree_tapbuf_size16_0_sram[2]:6 mux_top_track_4\/mux_l3_in_0_:S 0.152 +24 mux_tree_tapbuf_size16_0_sram[2]:24 mux_tree_tapbuf_size16_0_sram[2]:23 0.001412946 +25 mux_tree_tapbuf_size16_0_sram[2]:25 mux_tree_tapbuf_size16_0_sram[2]:24 0.0045 +26 mux_tree_tapbuf_size16_0_sram[2]:25 mux_tree_tapbuf_size16_0_sram[2]:22 0.009370535 +27 mux_tree_tapbuf_size16_0_sram[2]:23 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +28 mux_tree_tapbuf_size16_0_sram[2]:32 mux_tree_tapbuf_size16_0_sram[2]:31 0.003073661 +29 mux_tree_tapbuf_size16_0_sram[2]:32 mux_tree_tapbuf_size16_0_sram[2]:10 6.25e-05 +30 mux_tree_tapbuf_size16_0_sram[2]:20 mux_tree_tapbuf_size16_0_sram[2]:19 7.142857e-05 +31 mux_tree_tapbuf_size16_0_sram[2]:26 mux_tree_tapbuf_size16_0_sram[2]:25 0.002125 + +*END + +*D_NET mux_tree_tapbuf_size16_mem_1_ccff_tail[0] 0.001103898 //LENGTH 8.295 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/FTB_10__61:X O *L 0 *C 125.805 65.960 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 118.390 66.300 +*N mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:2 *C 118.390 66.300 +*N mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:3 *C 118.680 66.243 +*N mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:4 *C 118.680 65.960 +*N mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:5 *C 125.768 65.960 + +*CAP +0 mem_right_track_4\/FTB_10__61:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:2 8.602334e-05 +3 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:3 6.785637e-05 +4 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:4 0.000487102 +5 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:5 0.0004609163 + +*RES +0 mem_right_track_4\/FTB_10__61:X mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:5 0.152 +1 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:4 0.006328125 +3 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:2 0.0001686047 +4 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size16_mem_1_ccff_tail[0]:3 0.0002522322 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[2] 0.001174999 //LENGTH 9.590 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 89.545 109.820 +*I mux_top_track_32\/mux_l3_in_0_:S I *L 0.00357 *C 85.920 107.440 +*I mem_top_track_32\/FTB_25__76:A I *L 0.001746 *C 86.020 112.880 +*N mux_tree_tapbuf_size7_0_sram[2]:3 *C 86.020 112.880 +*N mux_tree_tapbuf_size7_0_sram[2]:4 *C 86.020 112.835 +*N mux_tree_tapbuf_size7_0_sram[2]:5 *C 85.920 107.440 +*N mux_tree_tapbuf_size7_0_sram[2]:6 *C 86.020 107.485 +*N mux_tree_tapbuf_size7_0_sram[2]:7 *C 86.020 109.820 +*N mux_tree_tapbuf_size7_0_sram[2]:8 *C 86.065 109.820 +*N mux_tree_tapbuf_size7_0_sram[2]:9 *C 89.508 109.820 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_32\/FTB_25__76:A 1e-06 +3 mux_tree_tapbuf_size7_0_sram[2]:3 3.449817e-05 +4 mux_tree_tapbuf_size7_0_sram[2]:4 0.0001729003 +5 mux_tree_tapbuf_size7_0_sram[2]:5 3.100036e-05 +6 mux_tree_tapbuf_size7_0_sram[2]:6 0.0001386238 +7 mux_tree_tapbuf_size7_0_sram[2]:7 0.0003420638 +8 mux_tree_tapbuf_size7_0_sram[2]:8 0.0002264564 +9 mux_tree_tapbuf_size7_0_sram[2]:9 0.0002264564 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_0_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_0_sram[2]:3 mem_top_track_32\/FTB_25__76:A 0.152 +2 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[2]:3 0.0045 +3 mux_tree_tapbuf_size7_0_sram[2]:8 mux_tree_tapbuf_size7_0_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size7_0_sram[2]:7 mux_tree_tapbuf_size7_0_sram[2]:6 0.002084822 +5 mux_tree_tapbuf_size7_0_sram[2]:7 mux_tree_tapbuf_size7_0_sram[2]:4 0.002691964 +6 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:8 0.003073661 +7 mux_tree_tapbuf_size7_0_sram[2]:5 mux_top_track_32\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_0_sram[2]:5 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[2] 0.002876223 //LENGTH 26.400 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 20.545 42.500 +*I mux_bottom_track_33\/mux_l3_in_0_:S I *L 0.00357 *C 19.680 31.280 +*I mem_bottom_track_33\/FTB_27__78:A I *L 0.001746 *C 15.640 44.880 +*N mux_tree_tapbuf_size7_2_sram[2]:3 *C 15.640 44.880 +*N mux_tree_tapbuf_size7_2_sram[2]:4 *C 19.643 31.280 +*N mux_tree_tapbuf_size7_2_sram[2]:5 *C 15.685 31.280 +*N mux_tree_tapbuf_size7_2_sram[2]:6 *C 15.640 31.325 +*N mux_tree_tapbuf_size7_2_sram[2]:7 *C 15.640 44.495 +*N mux_tree_tapbuf_size7_2_sram[2]:8 *C 15.678 44.540 +*N mux_tree_tapbuf_size7_2_sram[2]:9 *C 17.435 44.540 +*N mux_tree_tapbuf_size7_2_sram[2]:10 *C 17.480 44.495 +*N mux_tree_tapbuf_size7_2_sram[2]:11 *C 17.480 42.545 +*N mux_tree_tapbuf_size7_2_sram[2]:12 *C 17.525 42.500 +*N mux_tree_tapbuf_size7_2_sram[2]:13 *C 20.508 42.500 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_33\/FTB_27__78:A 1e-06 +3 mux_tree_tapbuf_size7_2_sram[2]:3 6.739963e-05 +4 mux_tree_tapbuf_size7_2_sram[2]:4 0.0002212951 +5 mux_tree_tapbuf_size7_2_sram[2]:5 0.0002212951 +6 mux_tree_tapbuf_size7_2_sram[2]:6 0.0007068894 +7 mux_tree_tapbuf_size7_2_sram[2]:7 0.0007068894 +8 mux_tree_tapbuf_size7_2_sram[2]:8 0.0001672438 +9 mux_tree_tapbuf_size7_2_sram[2]:9 0.0001286839 +10 mux_tree_tapbuf_size7_2_sram[2]:10 0.0001273245 +11 mux_tree_tapbuf_size7_2_sram[2]:11 0.0001273245 +12 mux_tree_tapbuf_size7_2_sram[2]:12 0.0001994389 +13 mux_tree_tapbuf_size7_2_sram[2]:13 0.0001994389 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_2_sram[2]:13 0.152 +1 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:3 0.0001465517 +3 mux_tree_tapbuf_size7_2_sram[2]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.01175893 +4 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:4 0.003533482 +5 mux_tree_tapbuf_size7_2_sram[2]:6 mux_tree_tapbuf_size7_2_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size7_2_sram[2]:4 mux_bottom_track_33\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size7_2_sram[2]:9 mux_tree_tapbuf_size7_2_sram[2]:8 0.001569197 +8 mux_tree_tapbuf_size7_2_sram[2]:10 mux_tree_tapbuf_size7_2_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size7_2_sram[2]:12 mux_tree_tapbuf_size7_2_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size7_2_sram[2]:11 mux_tree_tapbuf_size7_2_sram[2]:10 0.001741072 +11 mux_tree_tapbuf_size7_2_sram[2]:13 mux_tree_tapbuf_size7_2_sram[2]:12 0.002662947 +12 mux_tree_tapbuf_size7_2_sram[2]:3 mem_bottom_track_33\/FTB_27__78:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_0_ccff_tail[0] 0.0009431369 //LENGTH 6.340 LUMPCC 0.0004536079 DR + +*CONN +*I mem_top_track_32\/FTB_25__76:X O *L 0 *C 89.015 113.220 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 88.955 118.660 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 *C 88.955 118.660 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 *C 88.780 118.660 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 *C 88.780 118.615 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 *C 88.780 113.265 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 *C 88.780 113.220 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 *C 89.015 113.220 + +*CAP +0 mem_top_track_32\/FTB_25__76:X 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 5.292855e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 5.514866e-05 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0001366943 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0001366943 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 5.41484e-05 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 5.19148e-05 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 chany_top_in[19]:11 7.926962e-05 +9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 chany_top_in[19]:10 7.926962e-05 +10 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 BUF_net_90:4 0.0001475343 +11 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 BUF_net_90:5 0.0001475343 + +*RES +0 mem_top_track_32\/FTB_25__76:X mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001702929 //LENGTH 12.005 LUMPCC 0.0008402154 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_2_:X O *L 0 *C 79.755 93.500 +*I mux_top_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 75.080 99.620 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 75.118 99.620 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 75.440 99.620 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 75.440 99.280 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 78.155 99.280 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 78.200 99.235 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 78.200 93.545 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 78.245 93.500 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 79.718 93.500 + +*CAP +0 mux_top_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.199092e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.934103e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001421963 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001148462 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001471282 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001471282 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001090412 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001090412 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.002473e-06 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001067826 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.002473e-06 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001067826 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001531613 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001531613 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001531613 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001531613 + +*RES +0 mux_top_track_0\/mux_l1_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002424107 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.005080357 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001314732 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002879465 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035714 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001960475 //LENGTH 14.485 LUMPCC 0.0002076 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_1_:X O *L 0 *C 47.205 106.760 +*I mux_top_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 56.870 102.680 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 56.833 102.680 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 47.425 102.680 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 47.380 102.725 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 47.380 106.715 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 47.380 106.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 47.205 106.760 + +*CAP +0 mux_top_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0006198126 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006198126 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001987259 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001987259 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.828012e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.551831e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 prog_clk[0]:576 5.566458e-06 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 prog_clk[0]:586 5.566458e-06 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:584 2.354218e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:585 2.456827e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:582 2.354218e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:584 2.456827e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.012306e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.012306e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.008399554 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0035625 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007221095 //LENGTH 4.505 LUMPCC 0.0004129269 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_2_:X O *L 0 *C 100.915 105.060 +*I mux_right_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 96.700 105.060 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 96.738 105.060 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 100.878 105.060 + +*CAP +0 mux_right_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001535913 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001535913 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size12_2_sram[0]:28 0.0001652213 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_2_sram[0]:24 0.0001652213 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size12_2_sram[1]:12 4.124218e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size12_2_sram[1]:13 4.124218e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_0\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003696429 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004960503 //LENGTH 3.175 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_2_:X O *L 0 *C 115.285 94.520 +*I mux_right_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 116.020 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 115.983 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 115.505 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 115.460 96.175 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 115.460 94.565 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 115.460 94.520 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 115.285 94.520 + +*CAP +0 mux_right_track_2\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.442709e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.442709e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001133994 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001133994 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.857108e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.982616e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_2_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_2\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0] 0.0005325084 //LENGTH 3.700 LUMPCC 0.000129478 DR + +*CONN +*I mux_bottom_track_1\/mux_l4_in_0_:X O *L 0 *C 87.115 8.840 +*I mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 87.985 6.665 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 87.985 6.665 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 87.860 6.800 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 87.860 6.845 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 87.860 8.795 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 87.815 8.840 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 87.153 8.840 + +*CAP +0 mux_bottom_track_1\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 5.045228e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 5.301766e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 7.709519e-05 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 7.709519e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 7.168501e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 7.168501e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 chany_bottom_in[3] 6.473901e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 chany_bottom_in[3]:30 6.473901e-05 + +*RES +0 mux_bottom_track_1\/mux_l4_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_bottom_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 6.793479e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.001741072 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001299982 //LENGTH 10.305 LUMPCC 0.0002913848 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_1_:X O *L 0 *C 61.465 17.000 +*I mux_bottom_track_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 64.230 10.200 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 64.193 10.200 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 61.685 10.200 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 61.640 10.245 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 61.640 16.955 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 61.640 17.000 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 61.465 17.000 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0001578918 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0001578918 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0002960493 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0002960493 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 5.03565e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 4.835874e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_tree_tapbuf_size12_5_sram[2]:7 2.516158e-06 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_tree_tapbuf_size12_5_sram[2]:13 2.516158e-06 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_5_sram[2]:12 6.722426e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_5_sram[2]:11 6.722426e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size12_5_sram[3]:12 4.595936e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size12_5_sram[3]:10 2.999261e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size12_5_sram[3]:11 4.595936e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size12_5_sram[3]:3 2.999261e-05 + +*RES +0 mux_bottom_track_3\/mux_l3_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 9.51087e-05 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.005991072 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.002238839 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_bottom_track_3\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET optlc_net_148 0.007876278 //LENGTH 57.485 LUMPCC 0.001978164 DR + +*CONN +*I optlc_141:HI O *L 0 *C 55.200 82.960 +*I mux_top_track_4\/mux_l2_in_7_:A0 I *L 0.001631 *C 40.310 80.580 +*I mux_top_track_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 51.350 97.240 +*I mux_top_track_24\/mux_l2_in_3_:A0 I *L 0.001631 *C 57.330 66.300 +*N optlc_net_148:4 *C 57.367 66.300 +*N optlc_net_148:5 *C 57.915 66.300 +*N optlc_net_148:6 *C 57.960 66.345 +*N optlc_net_148:7 *C 57.960 82.915 +*N optlc_net_148:8 *C 57.915 82.960 +*N optlc_net_148:9 *C 51.312 97.240 +*N optlc_net_148:10 *C 48.345 97.240 +*N optlc_net_148:11 *C 48.300 97.195 +*N optlc_net_148:12 *C 40.348 80.580 +*N optlc_net_148:13 *C 48.255 80.580 +*N optlc_net_148:14 *C 48.300 80.625 +*N optlc_net_148:15 *C 48.300 82.280 +*N optlc_net_148:16 *C 48.345 82.280 +*N optlc_net_148:17 *C 49.220 82.280 +*N optlc_net_148:18 *C 49.220 82.960 +*N optlc_net_148:19 *C 55.200 82.960 + +*CAP +0 optlc_141:HI 1e-06 +1 mux_top_track_4\/mux_l2_in_7_:A0 1e-06 +2 mux_top_track_2\/mux_l2_in_3_:A0 1e-06 +3 mux_top_track_24\/mux_l2_in_3_:A0 1e-06 +4 optlc_net_148:4 8.692296e-05 +5 optlc_net_148:5 8.692296e-05 +6 optlc_net_148:6 0.0006733764 +7 optlc_net_148:7 0.0006733764 +8 optlc_net_148:8 0.0001430229 +9 optlc_net_148:9 0.0001533536 +10 optlc_net_148:10 0.0001533536 +11 optlc_net_148:11 0.0009675754 +12 optlc_net_148:12 0.0002867666 +13 optlc_net_148:13 0.0002867666 +14 optlc_net_148:14 0.0001206073 +15 optlc_net_148:15 0.00112243 +16 optlc_net_148:16 8.570631e-05 +17 optlc_net_148:17 0.0001327706 +18 optlc_net_148:18 0.0003954014 +19 optlc_net_148:19 0.0005257612 +20 optlc_net_148:13 chany_bottom_in[10]:38 0.0003102812 +21 optlc_net_148:12 chany_bottom_in[10]:37 0.0003102812 +22 optlc_net_148:7 mux_tree_tapbuf_size10_2_sram[2]:6 7.932229e-05 +23 optlc_net_148:7 mux_tree_tapbuf_size10_2_sram[2]:9 3.506344e-05 +24 optlc_net_148:7 mux_tree_tapbuf_size10_2_sram[2]:13 0.0001289975 +25 optlc_net_148:6 mux_tree_tapbuf_size10_2_sram[2]:8 3.506344e-05 +26 optlc_net_148:6 mux_tree_tapbuf_size10_2_sram[2]:12 0.0001289975 +27 optlc_net_148:6 mux_tree_tapbuf_size10_2_sram[2]:13 7.932229e-05 +28 optlc_net_148:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.186003e-07 +29 optlc_net_148:19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.572262e-05 +30 optlc_net_148:19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.436472e-05 +31 optlc_net_148:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.436472e-05 +32 optlc_net_148:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.007378e-05 +33 optlc_net_148:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.007378e-05 +34 optlc_net_148:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.186003e-07 +35 optlc_net_148:18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.572262e-05 +36 optlc_net_148:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001214471 +37 optlc_net_148:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001214471 +38 optlc_net_148:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001931909 +39 optlc_net_148:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001931909 + +*RES +0 optlc_141:HI optlc_net_148:19 0.152 +1 optlc_net_148:16 optlc_net_148:15 0.0045 +2 optlc_net_148:15 optlc_net_148:14 0.001477679 +3 optlc_net_148:15 optlc_net_148:11 0.01331696 +4 optlc_net_148:19 optlc_net_148:18 0.005339286 +5 optlc_net_148:19 optlc_net_148:8 0.002424107 +6 optlc_net_148:13 optlc_net_148:12 0.007060268 +7 optlc_net_148:14 optlc_net_148:13 0.0045 +8 optlc_net_148:12 mux_top_track_4\/mux_l2_in_7_:A0 0.152 +9 optlc_net_148:10 optlc_net_148:9 0.002649554 +10 optlc_net_148:11 optlc_net_148:10 0.0045 +11 optlc_net_148:9 mux_top_track_2\/mux_l2_in_3_:A0 0.152 +12 optlc_net_148:8 optlc_net_148:7 0.0045 +13 optlc_net_148:7 optlc_net_148:6 0.01479464 +14 optlc_net_148:5 optlc_net_148:4 0.0004888393 +15 optlc_net_148:6 optlc_net_148:5 0.0045 +16 optlc_net_148:4 mux_top_track_24\/mux_l2_in_3_:A0 0.152 +17 optlc_net_148:17 optlc_net_148:16 0.00078125 +18 optlc_net_148:18 optlc_net_148:17 0.0006071429 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001014979 //LENGTH 8.710 LUMPCC 8.332585e-05 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_1_:X O *L 0 *C 36.165 107.440 +*I mux_top_track_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 38.355 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 38.318 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 36.385 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 36.340 113.175 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 36.340 107.485 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 36.340 107.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 36.165 107.440 + +*CAP +0 mux_top_track_4\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0001340813 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0001340813 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0002754912 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0002754912 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 5.598452e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 5.452403e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_tree_tapbuf_size16_0_sram[2]:30 4.166293e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_tree_tapbuf_size16_0_sram[2]:29 4.166293e-05 + +*RES +0 mux_top_track_4\/mux_l3_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_top_track_4\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.001725447 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.005080357 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0003996775 //LENGTH 3.130 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_4_:X O *L 0 *C 40.305 85.340 +*I mux_top_track_4\/mux_l3_in_2_:A1 I *L 0.00198 *C 43.145 85.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 43.108 85.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 40.343 85.340 + +*CAP +0 mux_top_track_4\/mux_l2_in_4_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_2_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001988387 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001988387 + +*RES +0 mux_top_track_4\/mux_l2_in_4_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_4\/mux_l3_in_2_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.00246875 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0] 0.0005603665 //LENGTH 4.505 LUMPCC 0.000186599 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_2_:X O *L 0 *C 118.505 71.400 +*I mux_right_track_4\/mux_l4_in_1_:A1 I *L 0.00198 *C 119.700 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 119.663 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 119.185 69.020 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 119.140 69.065 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 119.140 71.355 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 119.095 71.400 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 118.543 71.400 + +*CAP +0 mux_right_track_4\/mux_l3_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l4_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 4.669259e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 4.669259e-05 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 8.593951e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 8.593951e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 5.325162e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 5.325162e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:172 3.055499e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 prog_clk[0]:167 1.188553e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:169 3.055499e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 prog_clk[0]:168 1.188553e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 2.651461e-06 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 2.651461e-06 +14 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 4.820752e-05 +15 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 4.820752e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_right_track_4\/mux_l4_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0004263393 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.002044643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0] 0.0006250235 //LENGTH 5.240 LUMPCC 7.310546e-05 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_1_:X O *L 0 *C 36.165 26.180 +*I mux_bottom_track_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 41.115 26.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 41.078 26.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 36.203 26.180 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.000274959 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.000274959 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size16_2_sram[2]:14 3.637469e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size16_2_sram[2]:16 1.780411e-07 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size16_2_sram[2]:15 1.780411e-07 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size16_2_sram[2]:18 3.637469e-05 + +*RES +0 mux_bottom_track_5\/mux_l3_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_bottom_track_5\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.004352679 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008602861 //LENGTH 7.210 LUMPCC 0.0002514977 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_4_:X O *L 0 *C 36.165 7.480 +*I mux_bottom_track_5\/mux_l3_in_2_:A1 I *L 0.00198 *C 35.060 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 34.960 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 34.960 12.535 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 34.960 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 35.420 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 35.420 7.525 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 35.465 7.480 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 36.128 7.480 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_4_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_2_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.513009e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001448448 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001660408 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.893301e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.773694e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.205137e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.205137e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size16_2_sram[1]:40 2.556334e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:10 9.382433e-06 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size16_2_sram[1]:42 8.04063e-06 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size16_2_sram[1]:41 4.841515e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size16_2_sram[1]:42 9.382433e-06 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size16_2_sram[1]:43 8.04063e-06 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size16_2_sram[1]:41 2.556334e-05 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size16_2_sram[1]:40 4.841515e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.706917e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 7.278122e-06 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.706917e-05 +20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.278122e-06 + +*RES +0 mux_bottom_track_5\/mux_l2_in_4_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_5\/mux_l3_in_2_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001477679 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0005915179 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002995536 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0004107143 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0002899425 //LENGTH 2.475 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_1_:X O *L 0 *C 39.735 88.060 +*I mux_left_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 37.550 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 37.587 88.060 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.698 88.060 + +*CAP +0 mux_left_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001439713 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001439713 + +*RES +0 mux_left_track_5\/mux_l2_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001883929 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001161382 //LENGTH 9.070 LUMPCC 0.0001213417 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_1_:X O *L 0 *C 93.205 56.440 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 99.075 58.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 99.075 58.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 98.900 58.480 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 94.805 58.480 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 94.760 58.435 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 94.760 56.485 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 94.715 56.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 93.243 56.440 + +*CAP +0 mux_top_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.303855e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000220428 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000195632 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001415984 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001415984 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001428724 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001428724 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size12_4_sram[0]:31 6.067087e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size12_4_sram[0]:32 6.067087e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00365625 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001741071 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001314732 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001198723 //LENGTH 7.830 LUMPCC 0.0005087511 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_2_:X O *L 0 *C 54.455 58.140 +*I mux_top_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 53.265 52.700 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 53.303 52.700 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 54.695 52.700 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 54.740 52.745 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 54.740 58.095 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 54.740 58.140 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 54.455 58.140 + +*CAP +0 mux_top_track_16\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001082552 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001082552 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000181986 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000181986 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.558242e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.190735e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_bottom_in[17]:24 7.337807e-06 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[17]:25 7.337807e-06 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[17]:26 6.898785e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[17]:27 4.349483e-05 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[17]:22 2.056659e-06 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[17]:23 4.349483e-05 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[17]:27 6.898785e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[17]:21 2.056659e-06 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:11 3.609821e-06 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:12 0.0001288886 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:8 3.609821e-06 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:11 0.0001288886 + +*RES +0 mux_top_track_16\/mux_l1_in_2_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_16\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243304 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001144267 //LENGTH 8.655 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l3_in_0_:X O *L 0 *C 62.845 72.420 +*I mux_top_track_24\/mux_l4_in_0_:A1 I *L 0.00198 *C 65.320 77.860 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 65.282 77.860 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 63.065 77.860 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 63.020 77.815 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 63.020 72.465 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 63.020 72.420 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 62.845 72.420 + +*CAP +0 mux_top_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001746886 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001746886 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003317253 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003317253 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.590446e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.353519e-05 + +*RES +0 mux_top_track_24\/mux_l3_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 9.51087e-05 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004776786 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001979911 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_24\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006369078 //LENGTH 4.930 LUMPCC 9.54917e-05 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_3_:X O *L 0 *C 112.985 53.720 +*I mux_right_track_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 114.715 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 114.715 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 114.540 55.760 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 113.665 55.760 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 113.620 55.715 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 113.620 53.765 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 113.575 53.720 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 113.023 53.720 + +*CAP +0 mux_right_track_8\/mux_l2_in_3_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_1_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.146636e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001018319 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.755961e-05 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001195091 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001195091 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 3.477002e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 3.477002e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.134723e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.639862e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.134723e-05 +12 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.639862e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_3_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_right_track_8\/mux_l3_in_1_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.00078125 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001741071 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004933036 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003035715 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0] 0.002509024 //LENGTH 23.180 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l4_in_0_:X O *L 0 *C 99.185 44.540 +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 122.150 44.715 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 122.113 44.605 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 99.223 44.540 + +*CAP +0 mux_right_track_16\/mux_l4_in_0_:X 1e-06 +1 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.001253512 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.001253512 + +*RES +0 mux_right_track_16\/mux_l4_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0204375 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0006429867 //LENGTH 4.820 LUMPCC 0.000137656 DR + +*CONN +*I mux_right_track_24\/mux_l3_in_1_:X O *L 0 *C 104.705 75.480 +*I mux_right_track_24\/mux_l4_in_0_:A0 I *L 0.001631 *C 106.895 77.180 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 106.858 77.180 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 105.385 77.180 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 105.340 77.135 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 105.340 75.525 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 105.295 75.480 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 104.743 75.480 + +*CAP +0 mux_right_track_24\/mux_l3_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l4_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 6.898696e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 6.898696e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001202417 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001202417 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.243672e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.243672e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.882798e-05 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.882798e-05 + +*RES +0 mux_right_track_24\/mux_l3_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_right_track_24\/mux_l4_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.001314732 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0014375 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0005926052 //LENGTH 5.020 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_0_:X O *L 0 *C 100.565 22.440 +*I mux_bottom_track_9\/mux_l4_in_0_:A1 I *L 0.00198 *C 102.580 20.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 102.580 20.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 102.580 20.105 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 102.580 22.395 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 102.535 22.440 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 100.603 22.440 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.947415e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0001344265 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001344265 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000146139 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000146139 + +*RES +0 mux_bottom_track_9\/mux_l3_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001725447 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002044643 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_9\/mux_l4_in_0_:A1 0.152 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0006700017 //LENGTH 4.440 LUMPCC 0.0003648922 DR + +*CONN +*I mux_bottom_track_17\/mux_l3_in_0_:X O *L 0 *C 55.375 31.620 +*I mux_bottom_track_17\/mux_l4_in_0_:A1 I *L 0.00198 *C 54.380 34.340 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 54.280 34.340 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 54.280 34.295 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 54.280 31.665 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 54.325 31.620 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 55.338 31.620 + +*CAP +0 mux_bottom_track_17\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.321818e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000116488 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000116488 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 1.845765e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 1.845765e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 bottom_left_grid_pin_36_[0]:6 8.049449e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 bottom_left_grid_pin_36_[0]:14 8.049449e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_7_sram[1]:23 5.089451e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_7_sram[1]:24 5.089451e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_7_sram[2]:14 5.105712e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_7_sram[2]:4 5.105712e-05 + +*RES +0 mux_bottom_track_17\/mux_l3_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_17\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002348214 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0009040179 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001900317 //LENGTH 15.395 LUMPCC 0.0003886453 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_2_:X O *L 0 *C 34.325 65.960 +*I mux_bottom_track_25\/mux_l3_in_1_:A1 I *L 0.00198 *C 33.120 52.700 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 33.157 52.700 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 33.535 52.700 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 33.580 52.745 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 33.580 65.915 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 33.625 65.960 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 34.288 65.960 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.432885e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.432885e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000628043 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000628043 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.246382e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.246382e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[17]:20 7.59003e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[17]:19 7.59003e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:5 0.0001184224 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_mem_10_ccff_tail[0]:4 0.0001184224 + +*RES +0 mux_bottom_track_25\/mux_l2_in_2_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_25\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003370536 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01175893 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005915179 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0008429148 //LENGTH 6.190 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_1_:X O *L 0 *C 36.975 77.180 +*I mux_left_track_9\/mux_l4_in_0_:A0 I *L 0.001631 *C 34.330 75.140 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 34.330 75.140 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 34.500 74.800 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 36.295 74.800 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 36.340 74.845 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 36.340 77.135 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 36.385 77.180 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 36.938 77.180 + +*CAP +0 mux_left_track_9\/mux_l3_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l4_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.5922e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001691822 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001429382 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001567305 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0001567305 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.970565e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:8 7.970565e-05 + +*RES +0 mux_left_track_9\/mux_l3_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_left_track_9\/mux_l4_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.001602679 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.002044643 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0004933036 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0009088566 //LENGTH 5.985 LUMPCC 0.0002102212 DR + +*CONN +*I mux_left_track_17\/mux_l3_in_0_:X O *L 0 *C 34.215 56.100 +*I mux_left_track_17\/mux_l4_in_0_:A1 I *L 0.00198 *C 28.520 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 28.558 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 34.178 56.100 + +*CAP +0 mux_left_track_17\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l4_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003483177 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0003483177 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_10_sram[3]:3 6.086302e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_10_sram[3]:7 4.424759e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_10_sram[3]:4 6.086302e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_tree_tapbuf_size10_10_sram[3]:6 4.424759e-05 + +*RES +0 mux_left_track_17\/mux_l3_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.005017857 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_left_track_17\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.007492515 //LENGTH 41.575 LUMPCC 0.002607829 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_1_:X O *L 0 *C 64.575 60.520 +*I mux_left_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 24.210 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 24.248 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 27.555 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 27.600 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 27.608 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 64.853 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 64.860 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 64.860 60.520 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 64.575 60.520 + +*CAP +0 mux_left_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002419882 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002419882 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.773789e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.002110729 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002110729 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.759945e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.192786e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 4.998649e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:415 9.177227e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:464 3.902367e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:465 8.872237e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:414 9.177227e-05 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:456 8.872237e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:465 3.902367e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_11_sram[1]:26 0.001078867 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size10_11_sram[1]:27 0.001078867 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size10_11_sram[1]:6 5.529015e-06 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size10_11_sram[1]:10 5.529015e-06 + +*RES +0 mux_left_track_25\/mux_l2_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002953125 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00341 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00341 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.005835049 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001548913 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00263738 //LENGTH 23.440 LUMPCC 0.0003582138 DR + +*CONN +*I mux_top_track_32\/mux_l3_in_0_:X O *L 0 *C 86.765 107.100 +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 88.550 123.900 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 88.588 123.808 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 90.575 123.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 90.620 123.715 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 90.620 107.145 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 90.575 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 86.803 107.100 + +*CAP +0 mux_top_track_32\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001356591 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001356591 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0007334594 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0007334594 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002694648 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002694648 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chany_top_in[19]:10 0.0001791069 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chany_top_in[19]:11 0.0001791069 + +*RES +0 mux_top_track_32\/mux_l3_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.003368304 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.01479464 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001774554 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001723407 //LENGTH 14.925 LUMPCC 0.0001054044 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_3_:X O *L 0 *C 19.495 52.360 +*I mux_bottom_track_33\/mux_l2_in_1_:A0 I *L 0.001631 *C 20.530 39.100 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 20.492 39.100 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 19.825 39.100 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 19.780 39.145 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 19.780 52.315 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 19.780 52.360 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 19.495 52.360 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.612408e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.612408e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0006864348 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0006864348 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.583724e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.50472e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_left_in[19]:19 5.270218e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[19]:18 5.270218e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_3_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_33\/mux_l2_in_1_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005959822 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.01175893 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001048284 //LENGTH 7.350 LUMPCC 0.0003386221 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_3_:X O *L 0 *C 20.875 74.120 +*I mux_left_track_33\/mux_l2_in_1_:A0 I *L 0.001631 *C 16.835 71.740 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 16.873 71.740 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 17.895 71.740 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 17.940 71.785 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 17.940 74.075 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 17.985 74.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 20.838 74.120 + +*CAP +0 mux_left_track_33\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.682396e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.682396e-05 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.736789e-05 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.73679e-05 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001996393 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001996393 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size7_3_sram[1]:11 6.578767e-06 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size7_3_sram[1]:12 6.578767e-06 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_3_sram[1]:9 1.104917e-06 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_3_sram[1]:13 3.604319e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_3_sram[1]:15 5.175703e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_3_sram[1]:10 1.104917e-06 +14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_3_sram[1]:14 3.604319e-05 +15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_3_sram[1]:16 5.175703e-05 +16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_150:30 6.966189e-08 +17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_150:35 6.805231e-05 +18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_150:39 3.098146e-07 +19 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_150:40 4.259951e-06 +20 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 optlc_net_150:9 1.135424e-06 +21 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_150:10 3.098146e-07 +22 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_150:29 6.966189e-08 +23 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_150:36 6.805231e-05 +24 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_150:39 4.259951e-06 +25 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 optlc_net_150:8 1.135424e-06 + +*RES +0 mux_left_track_33\/mux_l1_in_3_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_33\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0009129465 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002546875 + +*END + +*D_NET ropt_net_190 0.00181143 //LENGTH 14.585 LUMPCC 0.0001355925 DR + +*CONN +*I FTB_19__18:X O *L 0 *C 12.420 53.720 +*I ropt_mt_inst_829:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_190:2 *C 3.220 58.480 +*N ropt_net_190:3 *C 3.220 58.435 +*N ropt_net_190:4 *C 3.220 53.765 +*N ropt_net_190:5 *C 3.265 53.720 +*N ropt_net_190:6 *C 12.383 53.720 + +*CAP +0 FTB_19__18:X 1e-06 +1 ropt_mt_inst_829:A 1e-06 +2 ropt_net_190:2 2.94793e-05 +3 ropt_net_190:3 0.0002673699 +4 ropt_net_190:4 0.0002673699 +5 ropt_net_190:5 0.0005548091 +6 ropt_net_190:6 0.0005548091 +7 ropt_net_190:5 ropt_net_211:2 6.779625e-05 +8 ropt_net_190:6 ropt_net_211:3 6.779625e-05 + +*RES +0 FTB_19__18:X ropt_net_190:6 0.152 +1 ropt_net_190:2 ropt_mt_inst_829:A 0.152 +2 ropt_net_190:3 ropt_net_190:2 0.0045 +3 ropt_net_190:5 ropt_net_190:4 0.0045 +4 ropt_net_190:4 ropt_net_190:3 0.004169643 +5 ropt_net_190:6 ropt_net_190:5 0.008140625 + +*END + +*D_NET chany_bottom_out[7] 0.0005841118 //LENGTH 4.610 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 62.755 3.400 +*P chany_bottom_out[7] O *L 0.7423 *C 60.720 1.290 +*N chany_bottom_out[7]:2 *C 60.720 3.355 +*N chany_bottom_out[7]:3 *C 60.765 3.400 +*N chany_bottom_out[7]:4 *C 62.718 3.400 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 chany_bottom_out[7] 0.0001348849 +2 chany_bottom_out[7]:2 0.0001348849 +3 chany_bottom_out[7]:3 0.000156671 +4 chany_bottom_out[7]:4 0.000156671 + +*RES +0 ropt_mt_inst_800:X chany_bottom_out[7]:4 0.152 +1 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.001743304 +2 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0045 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.00184375 + +*END + +*D_NET ropt_net_191 0.00202043 //LENGTH 13.470 LUMPCC 0.0009139467 DR + +*CONN +*I FTB_36__35:X O *L 0 *C 45.540 126.820 +*I ropt_mt_inst_830:A I *L 0.001766 *C 54.740 123.760 +*N ropt_net_191:2 *C 54.703 123.760 +*N ropt_net_191:3 *C 51.060 123.760 +*N ropt_net_191:4 *C 51.060 124.100 +*N ropt_net_191:5 *C 49.725 124.100 +*N ropt_net_191:6 *C 49.680 124.145 +*N ropt_net_191:7 *C 49.680 126.775 +*N ropt_net_191:8 *C 49.635 126.820 +*N ropt_net_191:9 *C 45.578 126.820 + +*CAP +0 FTB_36__35:X 1e-06 +1 ropt_mt_inst_830:A 1e-06 +2 ropt_net_191:2 0.0002142563 +3 ropt_net_191:3 0.0002406566 +4 ropt_net_191:4 0.0001033851 +5 ropt_net_191:5 7.69848e-05 +6 ropt_net_191:6 8.840541e-05 +7 ropt_net_191:7 8.840541e-05 +8 ropt_net_191:8 0.000146195 +9 ropt_net_191:9 0.000146195 +10 ropt_net_191:6 chany_bottom_in[16]:12 3.158096e-05 +11 ropt_net_191:8 chany_bottom_in[16]:10 8.089988e-05 +12 ropt_net_191:7 chany_bottom_in[16]:11 3.158096e-05 +13 ropt_net_191:9 chany_bottom_in[16]:9 8.089988e-05 +14 ropt_net_191:6 top_left_grid_pin_34_[0]:14 1.899117e-07 +15 ropt_net_191:8 top_left_grid_pin_34_[0]:16 0.0001624836 +16 ropt_net_191:7 top_left_grid_pin_34_[0]:15 1.899117e-07 +17 ropt_net_191:9 top_left_grid_pin_34_[0]:17 0.0001624836 +18 ropt_net_191:2 ropt_net_219:7 4.134565e-05 +19 ropt_net_191:5 ropt_net_219:2 2.753067e-05 +20 ropt_net_191:5 ropt_net_219:6 7.160925e-07 +21 ropt_net_191:4 ropt_net_219:3 2.753067e-05 +22 ropt_net_191:4 ropt_net_219:7 7.160925e-07 +23 ropt_net_191:3 ropt_net_219:6 4.134565e-05 +24 ropt_net_191:2 chany_top_out[7]:4 2.046909e-06 +25 ropt_net_191:5 chany_top_out[7]:3 4.138597e-05 +26 ropt_net_191:6 chany_top_out[7]:2 6.879374e-05 +27 ropt_net_191:7 chany_top_out[7] 6.879374e-05 +28 ropt_net_191:4 chany_top_out[7]:4 4.138597e-05 +29 ropt_net_191:3 chany_top_out[7]:3 2.046909e-06 + +*RES +0 FTB_36__35:X ropt_net_191:9 0.152 +1 ropt_net_191:2 ropt_mt_inst_830:A 0.152 +2 ropt_net_191:5 ropt_net_191:4 0.001191964 +3 ropt_net_191:6 ropt_net_191:5 0.0045 +4 ropt_net_191:8 ropt_net_191:7 0.0045 +5 ropt_net_191:7 ropt_net_191:6 0.002348214 +6 ropt_net_191:9 ropt_net_191:8 0.003622768 +7 ropt_net_191:4 ropt_net_191:3 0.0003035715 +8 ropt_net_191:3 ropt_net_191:2 0.003252232 + +*END + +*D_NET chany_top_out[17] 0.0009368482 //LENGTH 8.180 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 64.595 126.140 +*P chany_top_out[17] O *L 0.7423 *C 62.100 129.270 +*N chany_top_out[17]:2 *C 62.100 128.905 +*N chany_top_out[17]:3 *C 62.145 128.860 +*N chany_top_out[17]:4 *C 65.275 128.860 +*N chany_top_out[17]:5 *C 65.320 128.815 +*N chany_top_out[17]:6 *C 65.320 126.185 +*N chany_top_out[17]:7 *C 65.275 126.140 +*N chany_top_out[17]:8 *C 64.633 126.140 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chany_top_out[17] 3.426608e-05 +2 chany_top_out[17]:2 3.426608e-05 +3 chany_top_out[17]:3 0.0002027371 +4 chany_top_out[17]:4 0.0002027371 +5 chany_top_out[17]:5 0.0001677504 +6 chany_top_out[17]:6 0.0001677504 +7 chany_top_out[17]:7 6.317045e-05 +8 chany_top_out[17]:8 6.317045e-05 + +*RES +0 ropt_mt_inst_810:X chany_top_out[17]:8 0.152 +1 chany_top_out[17]:8 chany_top_out[17]:7 0.0005736608 +2 chany_top_out[17]:7 chany_top_out[17]:6 0.0045 +3 chany_top_out[17]:6 chany_top_out[17]:5 0.002348214 +4 chany_top_out[17]:4 chany_top_out[17]:3 0.002794643 +5 chany_top_out[17]:5 chany_top_out[17]:4 0.0045 +6 chany_top_out[17]:3 chany_top_out[17]:2 0.0045 +7 chany_top_out[17]:2 chany_top_out[17] 0.0003258929 + +*END + +*D_NET ropt_net_214 0.001442628 //LENGTH 11.380 LUMPCC 0.000171812 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 11.630 49.640 +*I ropt_mt_inst_856:A I *L 0.001767 *C 3.220 47.600 +*N ropt_net_214:2 *C 3.258 47.600 +*N ropt_net_214:3 *C 6.855 47.600 +*N ropt_net_214:4 *C 6.900 47.645 +*N ropt_net_214:5 *C 6.900 49.595 +*N ropt_net_214:6 *C 6.945 49.640 +*N ropt_net_214:7 *C 11.593 49.640 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 ropt_mt_inst_856:A 1e-06 +2 ropt_net_214:2 0.0002475855 +3 ropt_net_214:3 0.0002475855 +4 ropt_net_214:4 9.042409e-05 +5 ropt_net_214:5 9.042409e-05 +6 ropt_net_214:6 0.0002963983 +7 ropt_net_214:7 0.0002963983 +8 ropt_net_214:4 ropt_net_180:6 6.087619e-05 +9 ropt_net_214:6 ropt_net_180:4 2.50298e-05 +10 ropt_net_214:5 ropt_net_180:5 6.087619e-05 +11 ropt_net_214:7 ropt_net_180:3 2.50298e-05 + +*RES +0 ropt_mt_inst_819:X ropt_net_214:7 0.152 +1 ropt_net_214:2 ropt_mt_inst_856:A 0.152 +2 ropt_net_214:3 ropt_net_214:2 0.003212054 +3 ropt_net_214:4 ropt_net_214:3 0.0045 +4 ropt_net_214:6 ropt_net_214:5 0.0045 +5 ropt_net_214:5 ropt_net_214:4 0.001741071 +6 ropt_net_214:7 ropt_net_214:6 0.004149554 + +*END + +*D_NET ropt_net_215 0.001876637 //LENGTH 12.130 LUMPCC 0.0005908724 DR + +*CONN +*I ropt_mt_inst_830:X O *L 0 *C 58.615 123.080 +*I ropt_mt_inst_857:A I *L 0.001766 *C 51.520 126.480 +*N ropt_net_215:2 *C 51.520 126.480 +*N ropt_net_215:3 *C 51.520 126.435 +*N ropt_net_215:4 *C 51.520 125.845 +*N ropt_net_215:5 *C 51.520 125.800 +*N ropt_net_215:6 *C 56.535 125.800 +*N ropt_net_215:7 *C 56.580 125.755 +*N ropt_net_215:8 *C 56.580 123.125 +*N ropt_net_215:9 *C 56.625 123.080 +*N ropt_net_215:10 *C 58.578 123.080 + +*CAP +0 ropt_mt_inst_830:X 1e-06 +1 ropt_mt_inst_857:A 1e-06 +2 ropt_net_215:2 3.723269e-05 +3 ropt_net_215:3 6.983722e-05 +4 ropt_net_215:4 6.983722e-05 +5 ropt_net_215:5 0.0003046758 +6 ropt_net_215:6 0.0002674431 +7 ropt_net_215:7 0.0001203921 +8 ropt_net_215:8 0.0001203921 +9 ropt_net_215:9 0.0001469772 +10 ropt_net_215:10 0.0001469772 +11 ropt_net_215:10 ropt_net_201:6 1.14255e-05 +12 ropt_net_215:9 ropt_net_201:5 1.14255e-05 +13 ropt_net_215:8 ropt_net_201:6 7.607559e-05 +14 ropt_net_215:7 ropt_net_201:7 7.607559e-05 +15 ropt_net_215:6 ropt_net_172:4 0.0002079351 +16 ropt_net_215:5 ropt_net_172:5 0.0002079351 + +*RES +0 ropt_mt_inst_830:X ropt_net_215:10 0.152 +1 ropt_net_215:10 ropt_net_215:9 0.001743303 +2 ropt_net_215:9 ropt_net_215:8 0.0045 +3 ropt_net_215:8 ropt_net_215:7 0.002348214 +4 ropt_net_215:6 ropt_net_215:5 0.004477679 +5 ropt_net_215:7 ropt_net_215:6 0.0045 +6 ropt_net_215:5 ropt_net_215:4 0.0045 +7 ropt_net_215:4 ropt_net_215:3 0.0005267857 +8 ropt_net_215:2 ropt_mt_inst_857:A 0.152 +9 ropt_net_215:3 ropt_net_215:2 0.0045 + +*END + +*D_NET ropt_net_177 0.001700471 //LENGTH 14.445 LUMPCC 0.0002474146 DR + +*CONN +*I BUFT_P_123:X O *L 0 *C 133.860 83.300 +*I ropt_mt_inst_815:A I *L 0.001766 *C 134.780 74.800 +*N ropt_net_177:2 *C 134.780 74.800 +*N ropt_net_177:3 *C 134.780 74.755 +*N ropt_net_177:4 *C 134.780 74.120 +*N ropt_net_177:5 *C 136.160 74.120 +*N ropt_net_177:6 *C 136.160 83.255 +*N ropt_net_177:7 *C 136.115 83.300 +*N ropt_net_177:8 *C 133.898 83.300 + +*CAP +0 BUFT_P_123:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_177:2 3.565254e-05 +3 ropt_net_177:3 4.652509e-05 +4 ropt_net_177:4 0.0001264448 +5 ropt_net_177:5 0.0005291616 +6 ropt_net_177:6 0.0004492419 +7 ropt_net_177:7 0.0001320155 +8 ropt_net_177:8 0.0001320155 +9 ropt_net_177:6 chanx_left_in[18]:9 5.991986e-05 +10 ropt_net_177:6 chanx_left_in[18]:13 7.370074e-07 +11 ropt_net_177:3 chanx_left_in[18]:13 6.319165e-07 +12 ropt_net_177:4 chanx_left_in[18]:14 6.319165e-07 +13 ropt_net_177:5 chanx_left_in[18]:10 5.991986e-05 +14 ropt_net_177:5 chanx_left_in[18]:14 7.370074e-07 +15 ropt_net_177:8 ropt_net_178:2 6.24185e-05 +16 ropt_net_177:7 ropt_net_178:3 6.24185e-05 + +*RES +0 BUFT_P_123:X ropt_net_177:8 0.152 +1 ropt_net_177:8 ropt_net_177:7 0.001979911 +2 ropt_net_177:7 ropt_net_177:6 0.0045 +3 ropt_net_177:6 ropt_net_177:5 0.00815625 +4 ropt_net_177:2 ropt_mt_inst_815:A 0.152 +5 ropt_net_177:3 ropt_net_177:2 0.0045 +6 ropt_net_177:4 ropt_net_177:3 0.0005669644 +7 ropt_net_177:5 ropt_net_177:4 0.001232143 + +*END + +*D_NET chany_top_out[19] 0.001284117 //LENGTH 9.335 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_873:X O *L 0 *C 84.835 126.820 +*P chany_top_out[19] O *L 0.7423 *C 78.660 129.235 +*N chany_top_out[19]:2 *C 78.660 127.205 +*N chany_top_out[19]:3 *C 78.705 127.160 +*N chany_top_out[19]:4 *C 82.800 127.160 +*N chany_top_out[19]:5 *C 82.800 126.820 +*N chany_top_out[19]:6 *C 84.797 126.820 + +*CAP +0 ropt_mt_inst_873:X 1e-06 +1 chany_top_out[19] 0.0001256826 +2 chany_top_out[19]:2 0.0001256826 +3 chany_top_out[19]:3 0.0003169797 +4 chany_top_out[19]:4 0.0003435062 +5 chany_top_out[19]:5 0.0001988959 +6 chany_top_out[19]:6 0.0001723694 + +*RES +0 ropt_mt_inst_873:X chany_top_out[19]:6 0.152 +1 chany_top_out[19]:6 chany_top_out[19]:5 0.001783482 +2 chany_top_out[19]:3 chany_top_out[19]:2 0.0045 +3 chany_top_out[19]:2 chany_top_out[19] 0.0018125 +4 chany_top_out[19]:4 chany_top_out[19]:3 0.00365625 +5 chany_top_out[19]:5 chany_top_out[19]:4 0.0003035715 + +*END + +*D_NET chanx_right_out[3] 0.001536363 //LENGTH 11.820 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_882:X O *L 0 *C 131.100 75.480 +*P chanx_right_out[3] O *L 0.7423 *C 140.450 74.120 +*N chanx_right_out[3]:2 *C 138.920 74.120 +*N chanx_right_out[3]:3 *C 138.920 74.800 +*N chanx_right_out[3]:4 *C 131.108 74.800 +*N chanx_right_out[3]:5 *C 131.100 74.858 +*N chanx_right_out[3]:6 *C 131.100 75.435 +*N chanx_right_out[3]:7 *C 131.100 75.480 + +*CAP +0 ropt_mt_inst_882:X 1e-06 +1 chanx_right_out[3] 8.251497e-05 +2 chanx_right_out[3]:2 0.0001218711 +3 chanx_right_out[3]:3 0.000614547 +4 chanx_right_out[3]:4 0.0005751909 +5 chanx_right_out[3]:5 5.471335e-05 +6 chanx_right_out[3]:6 5.471335e-05 +7 chanx_right_out[3]:7 3.181237e-05 + +*RES +0 ropt_mt_inst_882:X chanx_right_out[3]:7 0.152 +1 chanx_right_out[3]:7 chanx_right_out[3]:6 0.0045 +2 chanx_right_out[3]:6 chanx_right_out[3]:5 0.0005156249 +3 chanx_right_out[3]:5 chanx_right_out[3]:4 0.00341 +4 chanx_right_out[3]:4 chanx_right_out[3]:3 0.001223958 +5 chanx_right_out[3]:3 chanx_right_out[3]:2 0.0001065333 +6 chanx_right_out[3]:2 chanx_right_out[3] 0.0002397 + +*END + +*D_NET chanx_right_in[4] 0.03249391 //LENGTH 211.275 LUMPCC 0.01378535 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 140.450 93.840 +*I mux_top_track_2\/mux_l1_in_2_:A0 I *L 0.001631 *C 69.750 91.800 +*I FTB_15__14:A I *L 0.001776 *C 11.040 44.880 +*I mux_bottom_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 71.760 41.820 +*I mux_left_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 71.570 104.040 +*N chanx_right_in[4]:5 *C 71.532 104.040 +*N chanx_right_in[4]:6 *C 70.425 104.040 +*N chanx_right_in[4]:7 *C 70.380 104.040 +*N chanx_right_in[4]:8 *C 71.737 41.848 +*N chanx_right_in[4]:9 *C 71.725 42.160 +*N chanx_right_in[4]:10 *C 70.425 42.160 +*N chanx_right_in[4]:11 *C 70.380 42.205 +*N chanx_right_in[4]:12 *C 70.380 45.560 +*N chanx_right_in[4]:13 *C 11.078 44.880 +*N chanx_right_in[4]:14 *C 13.755 44.880 +*N chanx_right_in[4]:15 *C 13.800 44.925 +*N chanx_right_in[4]:16 *C 13.800 45.503 +*N chanx_right_in[4]:17 *C 13.808 45.560 +*N chanx_right_in[4]:18 *C 63.635 45.560 +*N chanx_right_in[4]:19 *C 69.913 45.560 +*N chanx_right_in[4]:20 *C 69.920 45.560 +*N chanx_right_in[4]:21 *C 69.750 91.800 +*N chanx_right_in[4]:22 *C 69.920 91.800 +*N chanx_right_in[4]:23 *C 69.920 91.800 +*N chanx_right_in[4]:24 *C 69.920 104.040 +*N chanx_right_in[4]:25 *C 69.928 104.040 +*N chanx_right_in[4]:26 *C 107.172 104.040 +*N chanx_right_in[4]:27 *C 107.180 103.983 +*N chanx_right_in[4]:28 *C 107.180 97.978 +*N chanx_right_in[4]:29 *C 107.188 97.920 +*N chanx_right_in[4]:30 *C 127.860 97.920 +*N chanx_right_in[4]:31 *C 127.880 97.913 +*N chanx_right_in[4]:32 *C 127.880 94.528 +*N chanx_right_in[4]:33 *C 127.900 94.520 +*N chanx_right_in[4]:34 *C 138.460 94.520 +*N chanx_right_in[4]:35 *C 138.460 93.840 + +*CAP +0 chanx_right_in[4] 0.0001007951 +1 mux_top_track_2\/mux_l1_in_2_:A0 1e-06 +2 FTB_15__14:A 1e-06 +3 mux_bottom_track_3\/mux_l1_in_1_:A1 1e-06 +4 mux_left_track_3\/mux_l1_in_1_:A0 1e-06 +5 chanx_right_in[4]:5 0.0001000858 +6 chanx_right_in[4]:6 0.0001000858 +7 chanx_right_in[4]:7 7.616806e-05 +8 chanx_right_in[4]:8 3.314668e-05 +9 chanx_right_in[4]:9 0.0001387766 +10 chanx_right_in[4]:10 0.0001056299 +11 chanx_right_in[4]:11 0.0002557449 +12 chanx_right_in[4]:12 0.0002940729 +13 chanx_right_in[4]:13 0.0001672679 +14 chanx_right_in[4]:14 0.0001672679 +15 chanx_right_in[4]:15 4.117218e-05 +16 chanx_right_in[4]:16 4.117218e-05 +17 chanx_right_in[4]:17 0.001582663 +18 chanx_right_in[4]:18 0.002048683 +19 chanx_right_in[4]:19 0.0004660193 +20 chanx_right_in[4]:20 0.002111126 +21 chanx_right_in[4]:21 5.636859e-05 +22 chanx_right_in[4]:22 6.086841e-05 +23 chanx_right_in[4]:23 0.002732744 +24 chanx_right_in[4]:24 0.0006667422 +25 chanx_right_in[4]:25 0.002135293 +26 chanx_right_in[4]:26 0.002135293 +27 chanx_right_in[4]:27 0.0003473736 +28 chanx_right_in[4]:28 0.0003473736 +29 chanx_right_in[4]:29 0.0005626476 +30 chanx_right_in[4]:30 0.0005626476 +31 chanx_right_in[4]:31 0.0002289715 +32 chanx_right_in[4]:32 0.0002289715 +33 chanx_right_in[4]:33 0.0003009864 +34 chanx_right_in[4]:34 0.000354298 +35 chanx_right_in[4]:35 0.0001541067 +36 chanx_right_in[4]:11 chany_top_in[9]:26 5.17922e-07 +37 chanx_right_in[4]:23 chany_top_in[9]:27 0.0005305372 +38 chanx_right_in[4]:23 chany_top_in[9]:33 0.0002361949 +39 chanx_right_in[4]:23 chany_top_in[9]:34 3.280902e-05 +40 chanx_right_in[4]:20 chany_top_in[9]:26 0.0005305372 +41 chanx_right_in[4]:20 chany_top_in[9]:30 0.0002269905 +42 chanx_right_in[4]:20 chany_top_in[9]:33 3.280902e-05 +43 chanx_right_in[4]:19 chany_top_in[9]:24 3.904373e-05 +44 chanx_right_in[4]:24 chany_top_in[9]:34 9.20444e-06 +45 chanx_right_in[4]:12 chany_top_in[9]:27 5.17922e-07 +46 chanx_right_in[4]:18 chany_top_in[9]:25 3.904373e-05 +47 chanx_right_in[4] chanx_right_in[5]:34 2.065022e-05 +48 chanx_right_in[4]:17 chanx_right_in[5]:12 1.195992e-06 +49 chanx_right_in[4]:25 chanx_right_in[5]:28 1.549698e-05 +50 chanx_right_in[4]:25 chanx_right_in[5]:29 2.405303e-05 +51 chanx_right_in[4]:26 chanx_right_in[5]:30 2.405303e-05 +52 chanx_right_in[4]:26 chanx_right_in[5]:29 1.549698e-05 +53 chanx_right_in[4]:29 chanx_right_in[5]:29 1.005787e-05 +54 chanx_right_in[4]:30 chanx_right_in[5]:30 1.005787e-05 +55 chanx_right_in[4]:33 chanx_right_in[5]:33 0.0002354071 +56 chanx_right_in[4]:34 chanx_right_in[5]:34 0.0002354071 +57 chanx_right_in[4]:35 chanx_right_in[5]:33 2.065022e-05 +58 chanx_right_in[4]:18 chanx_right_in[5]:13 1.195992e-06 +59 chanx_right_in[4] chanx_right_in[12] 1.018085e-05 +60 chanx_right_in[4]:29 chanx_right_in[12]:31 0.0004897476 +61 chanx_right_in[4]:30 chanx_right_in[12] 0.0004897476 +62 chanx_right_in[4]:35 chanx_right_in[12]:31 1.018085e-05 +63 chanx_right_in[4]:19 chanx_left_in[8]:26 1.6123e-06 +64 chanx_right_in[4]:17 chanx_left_in[8]:27 3.253159e-07 +65 chanx_right_in[4]:17 chanx_left_in[8]:37 0.0003608905 +66 chanx_right_in[4]:18 chanx_left_in[8]:36 0.0003608905 +67 chanx_right_in[4]:18 chanx_left_in[8]:27 1.6123e-06 +68 chanx_right_in[4]:18 chanx_left_in[8]:26 3.253159e-07 +69 chanx_right_in[4]:19 chanx_left_in[17]:17 9.756529e-05 +70 chanx_right_in[4]:17 chanx_left_in[17]:25 0.0002917077 +71 chanx_right_in[4]:17 chanx_left_in[17]:31 2.434159e-05 +72 chanx_right_in[4]:17 chanx_left_in[17]:29 0.0001903564 +73 chanx_right_in[4]:17 chanx_left_in[17]:27 9.405607e-05 +74 chanx_right_in[4]:18 chanx_left_in[17]:25 9.756529e-05 +75 chanx_right_in[4]:18 chanx_left_in[17]:17 0.0002917077 +76 chanx_right_in[4]:18 chanx_left_in[17]:30 2.434159e-05 +77 chanx_right_in[4]:18 chanx_left_in[17]:28 0.0001903564 +78 chanx_right_in[4]:18 chanx_left_in[17]:26 9.405607e-05 +79 chanx_right_in[4]:16 prog_clk[0]:694 2.589189e-05 +80 chanx_right_in[4]:17 prog_clk[0]:480 0.0002219342 +81 chanx_right_in[4]:17 prog_clk[0]:639 0.000163189 +82 chanx_right_in[4]:17 prog_clk[0]:638 0.0002652642 +83 chanx_right_in[4]:14 prog_clk[0]:682 1.21169e-05 +84 chanx_right_in[4]:15 prog_clk[0]:695 2.589189e-05 +85 chanx_right_in[4]:13 prog_clk[0]:694 1.21169e-05 +86 chanx_right_in[4]:25 prog_clk[0]:242 4.5214e-06 +87 chanx_right_in[4]:25 prog_clk[0]:243 1.698129e-06 +88 chanx_right_in[4]:26 prog_clk[0]:242 1.698129e-06 +89 chanx_right_in[4]:26 prog_clk[0]:237 4.5214e-06 +90 chanx_right_in[4]:18 prog_clk[0]:479 0.0002219342 +91 chanx_right_in[4]:18 prog_clk[0]:485 0.0002652642 +92 chanx_right_in[4]:18 prog_clk[0]:638 0.000163189 +93 chanx_right_in[4] chanx_right_in[1] 1.141405e-06 +94 chanx_right_in[4]:29 chanx_right_in[1]:22 0.0004414209 +95 chanx_right_in[4]:30 chanx_right_in[1] 0.0004414209 +96 chanx_right_in[4]:35 chanx_right_in[1]:22 1.141405e-06 +97 chanx_right_in[4]:25 right_top_grid_pin_42_[0]:8 0.0003315769 +98 chanx_right_in[4]:26 right_top_grid_pin_42_[0]:24 0.0003315769 +99 chanx_right_in[4]:33 right_top_grid_pin_45_[0]:15 0.0005694862 +100 chanx_right_in[4]:34 right_top_grid_pin_45_[0] 6.443307e-06 +101 chanx_right_in[4]:34 right_top_grid_pin_45_[0]:16 0.0005694862 +102 chanx_right_in[4]:35 right_top_grid_pin_45_[0]:17 6.443307e-06 +103 chanx_right_in[4]:23 chanx_left_in[0]:6 4.089178e-05 +104 chanx_right_in[4]:17 chanx_left_in[0]:17 0.0002766527 +105 chanx_right_in[4]:24 chanx_left_in[0]:5 4.089178e-05 +106 chanx_right_in[4]:18 chanx_left_in[0]:16 0.0002766527 +107 chanx_right_in[4]:17 chanx_left_in[19] 0.0003078765 +108 chanx_right_in[4]:18 chanx_left_in[19]:20 0.0003078765 +109 chanx_right_in[4]:23 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001288772 +110 chanx_right_in[4]:20 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001288772 +111 chanx_right_in[4]:17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009799374 +112 chanx_right_in[4]:18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0009799374 +113 chanx_right_in[4]:17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:11 0.0001668834 +114 chanx_right_in[4]:18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001668834 +115 chanx_right_in[4]:25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002401236 +116 chanx_right_in[4]:26 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002401236 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:35 0.0003117667 +1 chanx_right_in[4]:10 chanx_right_in[4]:9 0.001160714 +2 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0045 +3 chanx_right_in[4]:8 mux_bottom_track_3\/mux_l1_in_1_:A1 0.152 +4 chanx_right_in[4]:5 mux_left_track_3\/mux_l1_in_1_:A0 0.152 +5 chanx_right_in[4]:6 chanx_right_in[4]:5 0.0009888393 +6 chanx_right_in[4]:7 chanx_right_in[4]:6 0.0045 +7 chanx_right_in[4]:22 chanx_right_in[4]:21 9.239131e-05 +8 chanx_right_in[4]:23 chanx_right_in[4]:22 0.0045 +9 chanx_right_in[4]:23 chanx_right_in[4]:20 0.04128572 +10 chanx_right_in[4]:21 mux_top_track_2\/mux_l1_in_2_:A0 0.152 +11 chanx_right_in[4]:20 chanx_right_in[4]:19 0.00341 +12 chanx_right_in[4]:20 chanx_right_in[4]:12 0.0004107143 +13 chanx_right_in[4]:19 chanx_right_in[4]:18 0.000983475 +14 chanx_right_in[4]:16 chanx_right_in[4]:15 0.000515625 +15 chanx_right_in[4]:17 chanx_right_in[4]:16 0.00341 +16 chanx_right_in[4]:14 chanx_right_in[4]:13 0.002390625 +17 chanx_right_in[4]:15 chanx_right_in[4]:14 0.0045 +18 chanx_right_in[4]:13 FTB_15__14:A 0.152 +19 chanx_right_in[4]:24 chanx_right_in[4]:23 0.01092857 +20 chanx_right_in[4]:24 chanx_right_in[4]:7 0.0004107143 +21 chanx_right_in[4]:25 chanx_right_in[4]:24 0.00341 +22 chanx_right_in[4]:27 chanx_right_in[4]:26 0.00341 +23 chanx_right_in[4]:26 chanx_right_in[4]:25 0.00583505 +24 chanx_right_in[4]:28 chanx_right_in[4]:27 0.005361607 +25 chanx_right_in[4]:29 chanx_right_in[4]:28 0.00341 +26 chanx_right_in[4]:30 chanx_right_in[4]:29 0.003238691 +27 chanx_right_in[4]:31 chanx_right_in[4]:30 0.00341 +28 chanx_right_in[4]:33 chanx_right_in[4]:32 0.00341 +29 chanx_right_in[4]:32 chanx_right_in[4]:31 0.0005303166 +30 chanx_right_in[4]:9 chanx_right_in[4]:8 0.0002111487 +31 chanx_right_in[4]:12 chanx_right_in[4]:11 0.002995536 +32 chanx_right_in[4]:34 chanx_right_in[4]:33 0.0016544 +33 chanx_right_in[4]:35 chanx_right_in[4]:34 0.0001065333 +34 chanx_right_in[4]:18 chanx_right_in[4]:17 0.007806308 + +*END + +*D_NET chany_bottom_in[15] 0.0214971 //LENGTH 139.735 LUMPCC 0.008327468 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 53.360 1.325 +*I mux_left_track_33\/mux_l1_in_2_:A1 I *L 0.00198 *C 26.585 74.460 +*I mux_right_track_0\/mux_l1_in_4_:A0 I *L 0.001631 *C 76.995 77.180 +*N chany_bottom_in[15]:3 *C 76.958 77.180 +*N chany_bottom_in[15]:4 *C 76.405 77.180 +*N chany_bottom_in[15]:5 *C 76.360 77.225 +*N chany_bottom_in[15]:6 *C 76.360 78.142 +*N chany_bottom_in[15]:7 *C 76.353 78.200 +*N chany_bottom_in[15]:8 *C 47.860 78.200 +*N chany_bottom_in[15]:9 *C 47.840 78.193 +*N chany_bottom_in[15]:10 *C 26.570 74.460 +*N chany_bottom_in[15]:11 *C 26.242 74.460 +*N chany_bottom_in[15]:12 *C 26.220 74.505 +*N chany_bottom_in[15]:13 *C 26.220 75.422 +*N chany_bottom_in[15]:14 *C 26.228 75.480 +*N chany_bottom_in[15]:15 *C 39.560 75.480 +*N chany_bottom_in[15]:16 *C 39.560 76.160 +*N chany_bottom_in[15]:17 *C 47.820 76.160 +*N chany_bottom_in[15]:18 *C 47.840 76.160 +*N chany_bottom_in[15]:19 *C 47.840 52.555 +*N chany_bottom_in[15]:20 *C 47.840 2.728 +*N chany_bottom_in[15]:21 *C 47.860 2.720 +*N chany_bottom_in[15]:22 *C 53.352 2.720 +*N chany_bottom_in[15]:23 *C 53.360 2.663 + +*CAP +0 chany_bottom_in[15] 9.694567e-05 +1 mux_left_track_33\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_0\/mux_l1_in_4_:A0 1e-06 +3 chany_bottom_in[15]:3 5.506371e-05 +4 chany_bottom_in[15]:4 5.506371e-05 +5 chany_bottom_in[15]:5 0.0001016157 +6 chany_bottom_in[15]:6 0.0001016157 +7 chany_bottom_in[15]:7 0.001259236 +8 chany_bottom_in[15]:8 0.001259236 +9 chany_bottom_in[15]:9 7.128887e-05 +10 chany_bottom_in[15]:10 7.238494e-05 +11 chany_bottom_in[15]:11 7.238494e-05 +12 chany_bottom_in[15]:12 8.248349e-05 +13 chany_bottom_in[15]:13 8.248349e-05 +14 chany_bottom_in[15]:14 0.0009454685 +15 chany_bottom_in[15]:15 0.001009295 +16 chany_bottom_in[15]:16 0.0006021801 +17 chany_bottom_in[15]:17 0.0005383539 +18 chany_bottom_in[15]:18 0.0009676768 +19 chany_bottom_in[15]:19 0.003021125 +20 chany_bottom_in[15]:20 0.002124737 +21 chany_bottom_in[15]:21 0.000276026 +22 chany_bottom_in[15]:22 0.000276026 +23 chany_bottom_in[15]:23 9.694567e-05 +24 chany_bottom_in[15]:20 chanx_right_in[13]:26 0.0001659648 +25 chany_bottom_in[15]:9 chanx_right_in[13]:25 4.16058e-05 +26 chany_bottom_in[15]:18 chanx_right_in[13]:25 0.000405652 +27 chany_bottom_in[15]:18 chanx_right_in[13]:26 4.16058e-05 +28 chany_bottom_in[15]:19 chanx_right_in[13]:25 0.0001659648 +29 chany_bottom_in[15]:19 chanx_right_in[13]:26 0.000405652 +30 chany_bottom_in[15]:8 chanx_left_in[5]:26 0.0001542703 +31 chany_bottom_in[15]:7 chanx_left_in[5]:25 0.0001542703 +32 chany_bottom_in[15]:17 chanx_left_in[5]:25 0.0004653293 +33 chany_bottom_in[15]:14 chanx_left_in[5]:26 8.125293e-05 +34 chany_bottom_in[15]:15 chanx_left_in[5]:25 8.125293e-05 +35 chany_bottom_in[15]:16 chanx_left_in[5]:26 0.0004653293 +36 chany_bottom_in[15]:20 chanx_left_in[13]:29 0.0005376984 +37 chany_bottom_in[15]:9 chanx_left_in[13]:31 4.16058e-05 +38 chany_bottom_in[15]:18 chanx_left_in[13]:30 0.0003924951 +39 chany_bottom_in[15]:18 chanx_left_in[13]:31 5.476272e-05 +40 chany_bottom_in[15]:19 chanx_left_in[13]:29 0.0003508893 +41 chany_bottom_in[15]:19 chanx_left_in[13]:30 0.0005924611 +42 chany_bottom_in[15]:8 chanx_left_in[14]:26 0.0004862554 +43 chany_bottom_in[15]:7 chanx_left_in[14]:21 0.0004862554 +44 chany_bottom_in[15]:8 chany_top_in[15]:8 0.0009902797 +45 chany_bottom_in[15]:7 chany_top_in[15]:7 0.0009902797 +46 chany_bottom_in[15]:20 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0001599661 +47 chany_bottom_in[15]:19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001599661 +48 chany_bottom_in[15]:21 ropt_net_229:5 0.0002282009 +49 chany_bottom_in[15]:22 ropt_net_229:6 0.0002282009 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:23 0.001194197 +1 chany_bottom_in[15]:21 chany_bottom_in[15]:20 0.00341 +2 chany_bottom_in[15]:20 chany_bottom_in[15]:19 0.007806308 +3 chany_bottom_in[15]:23 chany_bottom_in[15]:22 0.00341 +4 chany_bottom_in[15]:22 chany_bottom_in[15]:21 0.0008604916 +5 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.004463825 +6 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.00341 +7 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.0008191965 +8 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.00341 +9 chany_bottom_in[15]:4 chany_bottom_in[15]:3 0.0004933036 +10 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.0045 +11 chany_bottom_in[15]:3 mux_right_track_0\/mux_l1_in_4_:A0 0.152 +12 chany_bottom_in[15]:17 chany_bottom_in[15]:16 0.001294067 +13 chany_bottom_in[15]:18 chany_bottom_in[15]:17 0.00341 +14 chany_bottom_in[15]:18 chany_bottom_in[15]:9 0.000318425 +15 chany_bottom_in[15]:13 chany_bottom_in[15]:12 0.0008191965 +16 chany_bottom_in[15]:14 chany_bottom_in[15]:13 0.00341 +17 chany_bottom_in[15]:11 chany_bottom_in[15]:10 0.0001779891 +18 chany_bottom_in[15]:12 chany_bottom_in[15]:11 0.0045 +19 chany_bottom_in[15]:10 mux_left_track_33\/mux_l1_in_2_:A1 0.152 +20 chany_bottom_in[15]:15 chany_bottom_in[15]:14 0.002088758 +21 chany_bottom_in[15]:16 chany_bottom_in[15]:15 0.0001065333 +22 chany_bottom_in[15]:19 chany_bottom_in[15]:18 0.003698116 + +*END + +*D_NET chany_top_out[12] 0.0008964692 //LENGTH 7.280 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 81.600 124.440 +*P chany_top_out[12] O *L 0.7423 *C 79.580 129.235 +*N chany_top_out[12]:2 *C 79.580 124.485 +*N chany_top_out[12]:3 *C 79.625 124.440 +*N chany_top_out[12]:4 *C 81.562 124.440 + +*CAP +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[12] 0.0002775973 +2 chany_top_out[12]:2 0.0002775973 +3 chany_top_out[12]:3 0.0001701373 +4 chany_top_out[12]:4 0.0001701373 + +*RES +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[12]:4 0.152 +1 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +2 chany_top_out[12]:2 chany_top_out[12] 0.004241072 +3 chany_top_out[12]:4 chany_top_out[12]:3 0.001729911 + +*END + +*D_NET chanx_left_out[1] 0.003330184 //LENGTH 25.540 LUMPCC 0.0006805504 DR + +*CONN +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.280 98.940 +*P chanx_left_out[1] O *L 0.7423 *C 1.230 81.600 +*N chanx_left_out[1]:2 *C 3.213 81.600 +*N chanx_left_out[1]:3 *C 3.220 81.657 +*N chanx_left_out[1]:4 *C 3.220 95.835 +*N chanx_left_out[1]:5 *C 3.265 95.880 +*N chanx_left_out[1]:6 *C 8.235 95.880 +*N chanx_left_out[1]:7 *C 8.280 95.925 +*N chanx_left_out[1]:8 *C 8.280 98.895 +*N chanx_left_out[1]:9 *C 8.280 98.940 + +*CAP +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[1] 0.0001587323 +2 chanx_left_out[1]:2 0.0001587323 +3 chanx_left_out[1]:3 0.0005973548 +4 chanx_left_out[1]:4 0.0005973548 +5 chanx_left_out[1]:5 0.000340132 +6 chanx_left_out[1]:6 0.000340132 +7 chanx_left_out[1]:7 0.000211986 +8 chanx_left_out[1]:8 0.000211986 +9 chanx_left_out[1]:9 3.222344e-05 +10 chanx_left_out[1]:3 ropt_net_183:6 0.0001279106 +11 chanx_left_out[1]:4 ropt_net_183:5 0.0001279106 +12 chanx_left_out[1]:3 ropt_net_232:5 0.0001357283 +13 chanx_left_out[1]:3 ropt_net_232:9 7.663626e-05 +14 chanx_left_out[1]:4 ropt_net_232:4 0.0001357283 +15 chanx_left_out[1]:4 ropt_net_232:8 7.663626e-05 + +*RES +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[1]:9 0.152 +1 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +2 chanx_left_out[1]:2 chanx_left_out[1] 0.0003105917 +3 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +4 chanx_left_out[1]:4 chanx_left_out[1]:3 0.01265848 +5 chanx_left_out[1]:6 chanx_left_out[1]:5 0.004437501 +6 chanx_left_out[1]:7 chanx_left_out[1]:6 0.0045 +7 chanx_left_out[1]:9 chanx_left_out[1]:8 0.0045 +8 chanx_left_out[1]:8 chanx_left_out[1]:7 0.002651786 + +*END + +*D_NET mux_tree_tapbuf_size10_11_sram[0] 0.006537034 //LENGTH 49.495 LUMPCC 0.0002582816 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.485 60.860 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 41.575 60.860 +*I mux_left_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 68.660 57.800 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 68.180 66.640 +*I mux_left_track_25\/mux_l1_in_2_:S I *L 0.00357 *C 70.480 63.920 +*N mux_tree_tapbuf_size10_11_sram[0]:5 *C 70.443 63.920 +*N mux_tree_tapbuf_size10_11_sram[0]:6 *C 68.080 66.640 +*N mux_tree_tapbuf_size10_11_sram[0]:7 *C 68.080 66.595 +*N mux_tree_tapbuf_size10_11_sram[0]:8 *C 68.540 57.800 +*N mux_tree_tapbuf_size10_11_sram[0]:9 *C 68.540 57.845 +*N mux_tree_tapbuf_size10_11_sram[0]:10 *C 68.540 63.920 +*N mux_tree_tapbuf_size10_11_sram[0]:11 *C 68.080 63.920 +*N mux_tree_tapbuf_size10_11_sram[0]:12 *C 68.080 63.920 +*N mux_tree_tapbuf_size10_11_sram[0]:13 *C 68.080 64.600 +*N mux_tree_tapbuf_size10_11_sram[0]:14 *C 56.625 64.600 +*N mux_tree_tapbuf_size10_11_sram[0]:15 *C 56.580 64.555 +*N mux_tree_tapbuf_size10_11_sram[0]:16 *C 56.580 60.565 +*N mux_tree_tapbuf_size10_11_sram[0]:17 *C 56.535 60.520 +*N mux_tree_tapbuf_size10_11_sram[0]:18 *C 40.940 60.520 +*N mux_tree_tapbuf_size10_11_sram[0]:19 *C 41.538 60.860 +*N mux_tree_tapbuf_size10_11_sram[0]:20 *C 40.940 60.860 +*N mux_tree_tapbuf_size10_11_sram[0]:21 *C 38.523 60.860 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_25\/mux_l1_in_1_:S 1e-06 +3 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +4 mux_left_track_25\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_11_sram[0]:5 0.0001538955 +6 mux_tree_tapbuf_size10_11_sram[0]:6 3.719372e-05 +7 mux_tree_tapbuf_size10_11_sram[0]:7 0.0001806514 +8 mux_tree_tapbuf_size10_11_sram[0]:8 3.780735e-05 +9 mux_tree_tapbuf_size10_11_sram[0]:9 0.0003188277 +10 mux_tree_tapbuf_size10_11_sram[0]:10 0.0003390007 +11 mux_tree_tapbuf_size10_11_sram[0]:11 0.0002008244 +12 mux_tree_tapbuf_size10_11_sram[0]:12 0.0002049681 +13 mux_tree_tapbuf_size10_11_sram[0]:13 0.0008091207 +14 mux_tree_tapbuf_size10_11_sram[0]:14 0.0007580481 +15 mux_tree_tapbuf_size10_11_sram[0]:15 0.000257357 +16 mux_tree_tapbuf_size10_11_sram[0]:16 0.000257357 +17 mux_tree_tapbuf_size10_11_sram[0]:17 0.001097916 +18 mux_tree_tapbuf_size10_11_sram[0]:18 0.001122821 +19 mux_tree_tapbuf_size10_11_sram[0]:19 6.077476e-05 +20 mux_tree_tapbuf_size10_11_sram[0]:20 0.0002614344 +21 mux_tree_tapbuf_size10_11_sram[0]:21 0.0001757551 +22 mux_tree_tapbuf_size10_11_sram[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.513055e-05 +23 mux_tree_tapbuf_size10_11_sram[0]:12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 3.352043e-05 +24 mux_tree_tapbuf_size10_11_sram[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.209729e-06 +25 mux_tree_tapbuf_size10_11_sram[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.528008e-05 +26 mux_tree_tapbuf_size10_11_sram[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 3.352043e-05 +27 mux_tree_tapbuf_size10_11_sram[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.209729e-06 +28 mux_tree_tapbuf_size10_11_sram[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.528008e-05 +29 mux_tree_tapbuf_size10_11_sram[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.513055e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_11_sram[0]:21 0.152 +1 mux_tree_tapbuf_size10_11_sram[0]:8 mux_left_track_25\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_11_sram[0]:9 mux_tree_tapbuf_size10_11_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size10_11_sram[0]:14 mux_tree_tapbuf_size10_11_sram[0]:13 0.01022768 +4 mux_tree_tapbuf_size10_11_sram[0]:15 mux_tree_tapbuf_size10_11_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size10_11_sram[0]:17 mux_tree_tapbuf_size10_11_sram[0]:16 0.0045 +6 mux_tree_tapbuf_size10_11_sram[0]:16 mux_tree_tapbuf_size10_11_sram[0]:15 0.0035625 +7 mux_tree_tapbuf_size10_11_sram[0]:12 mux_tree_tapbuf_size10_11_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size10_11_sram[0]:12 mux_tree_tapbuf_size10_11_sram[0]:5 0.002109375 +9 mux_tree_tapbuf_size10_11_sram[0]:11 mux_tree_tapbuf_size10_11_sram[0]:10 0.0004107143 +10 mux_tree_tapbuf_size10_11_sram[0]:11 mux_tree_tapbuf_size10_11_sram[0]:7 0.002388393 +11 mux_tree_tapbuf_size10_11_sram[0]:19 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size10_11_sram[0]:21 mux_tree_tapbuf_size10_11_sram[0]:20 0.002158482 +13 mux_tree_tapbuf_size10_11_sram[0]:5 mux_left_track_25\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size10_11_sram[0]:6 mux_left_track_25\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size10_11_sram[0]:7 mux_tree_tapbuf_size10_11_sram[0]:6 0.0045 +16 mux_tree_tapbuf_size10_11_sram[0]:20 mux_tree_tapbuf_size10_11_sram[0]:19 0.0005334822 +17 mux_tree_tapbuf_size10_11_sram[0]:20 mux_tree_tapbuf_size10_11_sram[0]:18 0.0003035715 +18 mux_tree_tapbuf_size10_11_sram[0]:18 mux_tree_tapbuf_size10_11_sram[0]:17 0.01392411 +19 mux_tree_tapbuf_size10_11_sram[0]:13 mux_tree_tapbuf_size10_11_sram[0]:12 0.000607143 +20 mux_tree_tapbuf_size10_11_sram[0]:10 mux_tree_tapbuf_size10_11_sram[0]:9 0.005424107 + +*END + +*D_NET mux_tree_tapbuf_size10_7_sram[0] 0.009803127 //LENGTH 72.875 LUMPCC 0.0009912306 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 108.405 31.280 +*I mux_bottom_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 76.460 41.480 +*I mux_bottom_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 70.040 34.680 +*I mux_bottom_track_17\/mux_l1_in_2_:S I *L 0.00357 *C 60.360 34.295 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 59.515 37.060 +*N mux_tree_tapbuf_size10_7_sram[0]:5 *C 60.360 34.370 +*N mux_tree_tapbuf_size10_7_sram[0]:6 *C 59.515 37.060 +*N mux_tree_tapbuf_size10_7_sram[0]:7 *C 59.800 37.060 +*N mux_tree_tapbuf_size10_7_sram[0]:8 *C 59.800 37.015 +*N mux_tree_tapbuf_size10_7_sram[0]:9 *C 59.800 34.045 +*N mux_tree_tapbuf_size10_7_sram[0]:10 *C 59.845 34.000 +*N mux_tree_tapbuf_size10_7_sram[0]:11 *C 60.303 34.000 +*N mux_tree_tapbuf_size10_7_sram[0]:12 *C 60.360 34.295 +*N mux_tree_tapbuf_size10_7_sram[0]:13 *C 60.360 34.680 +*N mux_tree_tapbuf_size10_7_sram[0]:14 *C 70.040 34.680 +*N mux_tree_tapbuf_size10_7_sram[0]:15 *C 76.422 41.480 +*N mux_tree_tapbuf_size10_7_sram[0]:16 *C 75.945 41.480 +*N mux_tree_tapbuf_size10_7_sram[0]:17 *C 75.900 41.435 +*N mux_tree_tapbuf_size10_7_sram[0]:18 *C 75.900 34.725 +*N mux_tree_tapbuf_size10_7_sram[0]:19 *C 75.900 34.680 +*N mux_tree_tapbuf_size10_7_sram[0]:20 *C 79.535 34.680 +*N mux_tree_tapbuf_size10_7_sram[0]:21 *C 79.580 34.635 +*N mux_tree_tapbuf_size10_7_sram[0]:22 *C 79.580 27.938 +*N mux_tree_tapbuf_size10_7_sram[0]:23 *C 79.588 27.880 +*N mux_tree_tapbuf_size10_7_sram[0]:24 *C 108.093 27.880 +*N mux_tree_tapbuf_size10_7_sram[0]:25 *C 108.100 27.938 +*N mux_tree_tapbuf_size10_7_sram[0]:26 *C 108.100 31.235 +*N mux_tree_tapbuf_size10_7_sram[0]:27 *C 108.100 31.280 +*N mux_tree_tapbuf_size10_7_sram[0]:28 *C 108.405 31.280 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_17\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_17\/mux_l1_in_2_:S 1e-06 +4 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size10_7_sram[0]:5 1.316727e-05 +6 mux_tree_tapbuf_size10_7_sram[0]:6 4.802423e-05 +7 mux_tree_tapbuf_size10_7_sram[0]:7 5.214059e-05 +8 mux_tree_tapbuf_size10_7_sram[0]:8 0.0001796205 +9 mux_tree_tapbuf_size10_7_sram[0]:9 0.0001796205 +10 mux_tree_tapbuf_size10_7_sram[0]:10 5.177614e-05 +11 mux_tree_tapbuf_size10_7_sram[0]:11 7.104604e-05 +12 mux_tree_tapbuf_size10_7_sram[0]:12 7.731262e-05 +13 mux_tree_tapbuf_size10_7_sram[0]:13 0.0006694187 +14 mux_tree_tapbuf_size10_7_sram[0]:14 0.001048367 +15 mux_tree_tapbuf_size10_7_sram[0]:15 6.286519e-05 +16 mux_tree_tapbuf_size10_7_sram[0]:16 6.286519e-05 +17 mux_tree_tapbuf_size10_7_sram[0]:17 0.0005024501 +18 mux_tree_tapbuf_size10_7_sram[0]:18 0.0005024501 +19 mux_tree_tapbuf_size10_7_sram[0]:19 0.0006329264 +20 mux_tree_tapbuf_size10_7_sram[0]:20 0.0002320303 +21 mux_tree_tapbuf_size10_7_sram[0]:21 0.0003877805 +22 mux_tree_tapbuf_size10_7_sram[0]:22 0.0003877805 +23 mux_tree_tapbuf_size10_7_sram[0]:23 0.001595159 +24 mux_tree_tapbuf_size10_7_sram[0]:24 0.001595159 +25 mux_tree_tapbuf_size10_7_sram[0]:25 0.0001854708 +26 mux_tree_tapbuf_size10_7_sram[0]:26 0.0001854708 +27 mux_tree_tapbuf_size10_7_sram[0]:27 4.379044e-05 +28 mux_tree_tapbuf_size10_7_sram[0]:28 4.020449e-05 +29 mux_tree_tapbuf_size10_7_sram[0]:23 prog_clk[0]:138 0.0002623933 +30 mux_tree_tapbuf_size10_7_sram[0]:23 prog_clk[0]:303 0.0001054536 +31 mux_tree_tapbuf_size10_7_sram[0]:23 prog_clk[0]:323 2.75228e-05 +32 mux_tree_tapbuf_size10_7_sram[0]:24 prog_clk[0]:133 0.0002623933 +33 mux_tree_tapbuf_size10_7_sram[0]:24 prog_clk[0]:138 0.0001054536 +34 mux_tree_tapbuf_size10_7_sram[0]:24 prog_clk[0]:303 2.75228e-05 +35 mux_tree_tapbuf_size10_7_sram[0]:9 prog_clk[0]:321 2.193344e-07 +36 mux_tree_tapbuf_size10_7_sram[0]:9 prog_clk[0]:322 1.807258e-06 +37 mux_tree_tapbuf_size10_7_sram[0]:8 prog_clk[0]:320 2.193344e-07 +38 mux_tree_tapbuf_size10_7_sram[0]:8 prog_clk[0]:321 1.807258e-06 +39 mux_tree_tapbuf_size10_7_sram[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.605213e-05 +40 mux_tree_tapbuf_size10_7_sram[0]:20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.216695e-05 +41 mux_tree_tapbuf_size10_7_sram[0]:19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.605213e-05 +42 mux_tree_tapbuf_size10_7_sram[0]:19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.216695e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_7_sram[0]:28 0.152 +1 mux_tree_tapbuf_size10_7_sram[0]:14 mux_bottom_track_17\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_7_sram[0]:14 mux_tree_tapbuf_size10_7_sram[0]:13 0.008642858 +3 mux_tree_tapbuf_size10_7_sram[0]:12 mux_bottom_track_17\/mux_l1_in_2_:S 0.152 +4 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:11 0.0001715116 +5 mux_tree_tapbuf_size10_7_sram[0]:12 mux_tree_tapbuf_size10_7_sram[0]:5 4.360465e-05 +6 mux_tree_tapbuf_size10_7_sram[0]:20 mux_tree_tapbuf_size10_7_sram[0]:19 0.003245536 +7 mux_tree_tapbuf_size10_7_sram[0]:21 mux_tree_tapbuf_size10_7_sram[0]:20 0.0045 +8 mux_tree_tapbuf_size10_7_sram[0]:22 mux_tree_tapbuf_size10_7_sram[0]:21 0.005979911 +9 mux_tree_tapbuf_size10_7_sram[0]:23 mux_tree_tapbuf_size10_7_sram[0]:22 0.00341 +10 mux_tree_tapbuf_size10_7_sram[0]:25 mux_tree_tapbuf_size10_7_sram[0]:24 0.00341 +11 mux_tree_tapbuf_size10_7_sram[0]:24 mux_tree_tapbuf_size10_7_sram[0]:23 0.004465783 +12 mux_tree_tapbuf_size10_7_sram[0]:27 mux_tree_tapbuf_size10_7_sram[0]:26 0.0045 +13 mux_tree_tapbuf_size10_7_sram[0]:26 mux_tree_tapbuf_size10_7_sram[0]:25 0.002944197 +14 mux_tree_tapbuf_size10_7_sram[0]:28 mux_tree_tapbuf_size10_7_sram[0]:27 0.0001657609 +15 mux_tree_tapbuf_size10_7_sram[0]:10 mux_tree_tapbuf_size10_7_sram[0]:9 0.0045 +16 mux_tree_tapbuf_size10_7_sram[0]:9 mux_tree_tapbuf_size10_7_sram[0]:8 0.002651786 +17 mux_tree_tapbuf_size10_7_sram[0]:7 mux_tree_tapbuf_size10_7_sram[0]:6 0.0001548913 +18 mux_tree_tapbuf_size10_7_sram[0]:8 mux_tree_tapbuf_size10_7_sram[0]:7 0.0045 +19 mux_tree_tapbuf_size10_7_sram[0]:6 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:18 0.0045 +21 mux_tree_tapbuf_size10_7_sram[0]:19 mux_tree_tapbuf_size10_7_sram[0]:14 0.005232143 +22 mux_tree_tapbuf_size10_7_sram[0]:18 mux_tree_tapbuf_size10_7_sram[0]:17 0.005991072 +23 mux_tree_tapbuf_size10_7_sram[0]:16 mux_tree_tapbuf_size10_7_sram[0]:15 0.0004263393 +24 mux_tree_tapbuf_size10_7_sram[0]:17 mux_tree_tapbuf_size10_7_sram[0]:16 0.0045 +25 mux_tree_tapbuf_size10_7_sram[0]:15 mux_bottom_track_17\/mux_l1_in_1_:S 0.152 +26 mux_tree_tapbuf_size10_7_sram[0]:11 mux_tree_tapbuf_size10_7_sram[0]:10 0.0004084822 +27 mux_tree_tapbuf_size10_7_sram[0]:13 mux_tree_tapbuf_size10_7_sram[0]:12 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size12_4_sram[3] 0.001859154 //LENGTH 15.300 LUMPCC 0.0005940012 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 90.465 14.960 +*I mem_bottom_track_1\/FTB_5__56:A I *L 0.001746 *C 83.720 12.240 +*I mux_bottom_track_1\/mux_l4_in_0_:S I *L 0.00357 *C 87.960 9.520 +*N mux_tree_tapbuf_size12_4_sram[3]:3 *C 87.998 9.520 +*N mux_tree_tapbuf_size12_4_sram[3]:4 *C 90.115 9.520 +*N mux_tree_tapbuf_size12_4_sram[3]:5 *C 90.160 9.565 +*N mux_tree_tapbuf_size12_4_sram[3]:6 *C 83.758 12.240 +*N mux_tree_tapbuf_size12_4_sram[3]:7 *C 90.115 12.240 +*N mux_tree_tapbuf_size12_4_sram[3]:8 *C 90.160 12.240 +*N mux_tree_tapbuf_size12_4_sram[3]:9 *C 90.160 14.915 +*N mux_tree_tapbuf_size12_4_sram[3]:10 *C 90.160 14.960 +*N mux_tree_tapbuf_size12_4_sram[3]:11 *C 90.465 14.960 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_1\/FTB_5__56:A 1e-06 +2 mux_bottom_track_1\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_4_sram[3]:3 7.99999e-05 +4 mux_tree_tapbuf_size12_4_sram[3]:4 7.99999e-05 +5 mux_tree_tapbuf_size12_4_sram[3]:5 6.594541e-05 +6 mux_tree_tapbuf_size12_4_sram[3]:6 0.0003519779 +7 mux_tree_tapbuf_size12_4_sram[3]:7 0.0003519779 +8 mux_tree_tapbuf_size12_4_sram[3]:8 0.0001636974 +9 mux_tree_tapbuf_size12_4_sram[3]:9 7.191312e-05 +10 mux_tree_tapbuf_size12_4_sram[3]:10 5.054926e-05 +11 mux_tree_tapbuf_size12_4_sram[3]:11 4.609158e-05 +12 mux_tree_tapbuf_size12_4_sram[3]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 8.049187e-05 +13 mux_tree_tapbuf_size12_4_sram[3]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 7.215937e-05 +14 mux_tree_tapbuf_size12_4_sram[3]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:3 5.185602e-05 +15 mux_tree_tapbuf_size12_4_sram[3]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:4 7.215937e-05 +16 mux_tree_tapbuf_size12_4_sram[3]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.185602e-05 +17 mux_tree_tapbuf_size12_4_sram[3]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_10_X[0]:5 8.049187e-05 +18 mux_tree_tapbuf_size12_4_sram[3]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 2.914042e-05 +19 mux_tree_tapbuf_size12_4_sram[3]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.545043e-05 +20 mux_tree_tapbuf_size12_4_sram[3]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 2.790246e-05 +21 mux_tree_tapbuf_size12_4_sram[3]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.545043e-05 +22 mux_tree_tapbuf_size12_4_sram[3]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 2.790246e-05 +23 mux_tree_tapbuf_size12_4_sram[3]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 2.914042e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_4_sram[3]:11 0.152 +1 mux_tree_tapbuf_size12_4_sram[3]:7 mux_tree_tapbuf_size12_4_sram[3]:6 0.005676339 +2 mux_tree_tapbuf_size12_4_sram[3]:8 mux_tree_tapbuf_size12_4_sram[3]:7 0.0045 +3 mux_tree_tapbuf_size12_4_sram[3]:8 mux_tree_tapbuf_size12_4_sram[3]:5 0.002388393 +4 mux_tree_tapbuf_size12_4_sram[3]:6 mem_bottom_track_1\/FTB_5__56:A 0.152 +5 mux_tree_tapbuf_size12_4_sram[3]:4 mux_tree_tapbuf_size12_4_sram[3]:3 0.001890625 +6 mux_tree_tapbuf_size12_4_sram[3]:5 mux_tree_tapbuf_size12_4_sram[3]:4 0.0045 +7 mux_tree_tapbuf_size12_4_sram[3]:3 mux_bottom_track_1\/mux_l4_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_4_sram[3]:10 mux_tree_tapbuf_size12_4_sram[3]:9 0.0045 +9 mux_tree_tapbuf_size12_4_sram[3]:9 mux_tree_tapbuf_size12_4_sram[3]:8 0.002388393 +10 mux_tree_tapbuf_size12_4_sram[3]:11 mux_tree_tapbuf_size12_4_sram[3]:10 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size12_mem_5_ccff_tail[0] 0.0009491721 //LENGTH 8.575 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_3\/FTB_6__57:X O *L 0 *C 51.330 11.900 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 45.725 9.860 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:2 *C 45.763 9.860 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:3 *C 49.635 9.860 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:4 *C 49.680 9.905 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:5 *C 49.680 11.855 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:6 *C 49.725 11.900 +*N mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:7 *C 51.293 11.900 + +*CAP +0 mem_bottom_track_3\/FTB_6__57:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:2 0.0002574615 +3 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:3 0.0002574615 +4 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:4 0.0001094474 +5 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:5 0.0001094474 +6 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:6 0.0001066771 +7 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:7 0.0001066771 + +*RES +0 mem_bottom_track_3\/FTB_6__57:X mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:6 0.001399554 +2 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:4 0.001741072 +4 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:2 0.003457589 +5 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size12_mem_5_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size16_3_sram[3] 0.002429927 //LENGTH 17.645 LUMPCC 0.0003545551 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 11.345 93.500 +*I mux_left_track_5\/mux_l4_in_1_:S I *L 0.00357 *C 12.980 88.740 +*I mux_left_track_5\/mux_l4_in_0_:S I *L 0.00357 *C 17.120 89.080 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D I *L 0.001695 *C 8.915 86.020 +*N mux_tree_tapbuf_size16_3_sram[3]:4 *C 8.953 86.020 +*N mux_tree_tapbuf_size16_3_sram[3]:5 *C 11.455 86.020 +*N mux_tree_tapbuf_size16_3_sram[3]:6 *C 11.500 86.065 +*N mux_tree_tapbuf_size16_3_sram[3]:7 *C 17.082 89.080 +*N mux_tree_tapbuf_size16_3_sram[3]:8 *C 12.980 89.080 +*N mux_tree_tapbuf_size16_3_sram[3]:9 *C 12.980 88.763 +*N mux_tree_tapbuf_size16_3_sram[3]:10 *C 11.545 88.740 +*N mux_tree_tapbuf_size16_3_sram[3]:11 *C 11.500 88.740 +*N mux_tree_tapbuf_size16_3_sram[3]:12 *C 11.500 93.455 +*N mux_tree_tapbuf_size16_3_sram[3]:13 *C 11.500 93.500 +*N mux_tree_tapbuf_size16_3_sram[3]:14 *C 11.345 93.500 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_left_track_5\/mux_l4_in_1_:S 1e-06 +2 mux_left_track_5\/mux_l4_in_0_:S 1e-06 +3 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D 1e-06 +4 mux_tree_tapbuf_size16_3_sram[3]:4 0.0001761236 +5 mux_tree_tapbuf_size16_3_sram[3]:5 0.0001761236 +6 mux_tree_tapbuf_size16_3_sram[3]:6 0.0001585163 +7 mux_tree_tapbuf_size16_3_sram[3]:7 0.0002511247 +8 mux_tree_tapbuf_size16_3_sram[3]:8 0.00027842 +9 mux_tree_tapbuf_size16_3_sram[3]:9 0.0001163833 +10 mux_tree_tapbuf_size16_3_sram[3]:10 8.908793e-05 +11 mux_tree_tapbuf_size16_3_sram[3]:11 0.0004506694 +12 mux_tree_tapbuf_size16_3_sram[3]:12 0.0002595476 +13 mux_tree_tapbuf_size16_3_sram[3]:13 6.08815e-05 +14 mux_tree_tapbuf_size16_3_sram[3]:14 5.449335e-05 +15 mux_tree_tapbuf_size16_3_sram[3]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001084529 +16 mux_tree_tapbuf_size16_3_sram[3]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0001084529 +17 mux_tree_tapbuf_size16_3_sram[3]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 6.583898e-05 +18 mux_tree_tapbuf_size16_3_sram[3]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 6.583898e-05 +19 mux_tree_tapbuf_size16_3_sram[3]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 1.564111e-07 +20 mux_tree_tapbuf_size16_3_sram[3]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 2.82933e-06 +21 mux_tree_tapbuf_size16_3_sram[3]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 1.564111e-07 +22 mux_tree_tapbuf_size16_3_sram[3]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 2.82933e-06 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size16_3_sram[3]:14 0.152 +1 mux_tree_tapbuf_size16_3_sram[3]:10 mux_tree_tapbuf_size16_3_sram[3]:9 0.00128125 +2 mux_tree_tapbuf_size16_3_sram[3]:11 mux_tree_tapbuf_size16_3_sram[3]:10 0.0045 +3 mux_tree_tapbuf_size16_3_sram[3]:11 mux_tree_tapbuf_size16_3_sram[3]:6 0.002388393 +4 mux_tree_tapbuf_size16_3_sram[3]:9 mux_left_track_5\/mux_l4_in_1_:S 0.152 +5 mux_tree_tapbuf_size16_3_sram[3]:9 mux_tree_tapbuf_size16_3_sram[3]:8 0.0002834821 +6 mux_tree_tapbuf_size16_3_sram[3]:7 mux_left_track_5\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size16_3_sram[3]:5 mux_tree_tapbuf_size16_3_sram[3]:4 0.002234375 +8 mux_tree_tapbuf_size16_3_sram[3]:6 mux_tree_tapbuf_size16_3_sram[3]:5 0.0045 +9 mux_tree_tapbuf_size16_3_sram[3]:4 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_4_:D 0.152 +10 mux_tree_tapbuf_size16_3_sram[3]:13 mux_tree_tapbuf_size16_3_sram[3]:12 0.0045 +11 mux_tree_tapbuf_size16_3_sram[3]:12 mux_tree_tapbuf_size16_3_sram[3]:11 0.004209822 +12 mux_tree_tapbuf_size16_3_sram[3]:14 mux_tree_tapbuf_size16_3_sram[3]:13 8.423914e-05 +13 mux_tree_tapbuf_size16_3_sram[3]:8 mux_tree_tapbuf_size16_3_sram[3]:7 0.003662946 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001505882 //LENGTH 10.115 LUMPCC 0.0006810252 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 58.705 118.320 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.080 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.080 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.080 118.320 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 58.742 118.320 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.758474e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003967914 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003684803 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_40_[0]:10 0.0001177056 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_40_[0]:9 0.0001177056 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size12_0_sram[0]:11 4.188172e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size12_0_sram[0]:12 3.237525e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_0_sram[0]:12 4.188172e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size12_0_sram[0]:13 3.237525e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00014855 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00014855 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.008337053 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001201867 //LENGTH 9.300 LUMPCC 0.000128232 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_4_:X O *L 0 *C 60.435 86.360 +*I mux_top_track_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 56.485 90.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 56.523 90.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 57.915 90.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 57.960 90.735 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 57.960 86.405 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 58.005 86.360 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 60.398 86.360 + +*CAP +0 mux_top_track_2\/mux_l1_in_4_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.172329e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.172329e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002679177 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002679177 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001861763 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001861763 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size12_1_sram[1]:9 6.411601e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size12_1_sram[1]:10 6.411601e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_4_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_2\/mux_l2_in_2_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001243304 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002136161 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0] 0.001039803 //LENGTH 8.850 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_0_:X O *L 0 *C 121.725 96.220 +*I mux_right_track_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 121.080 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 120.980 88.740 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 120.980 88.785 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 120.980 96.175 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 121.025 96.220 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 121.688 96.220 + +*CAP +0 mux_right_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l4_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.502256e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0004235195 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0004235195 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 7.787097e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 7.787097e-05 + +*RES +0 mux_right_track_2\/mux_l3_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_right_track_2\/mux_l4_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.006598215 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0005915179 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001309168 //LENGTH 10.085 LUMPCC 0.0003947781 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_2_:X O *L 0 *C 57.325 25.160 +*I mux_bottom_track_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 59.340 18.020 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 59.303 18.020 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 58.925 18.020 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 58.880 18.065 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 58.880 25.115 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 58.835 25.160 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 57.363 25.160 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 4.19405e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 4.19405e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002833945 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002833945 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001308601 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001308601 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.171561e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.62718e-06 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.171561e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 9.62718e-06 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.894885e-06 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.894885e-06 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001239674 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 1.839679e-07 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001239674 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.839679e-07 + +*RES +0 mux_bottom_track_3\/mux_l2_in_2_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_3\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0003370536 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.006294643 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0] 0.0005882059 //LENGTH 4.705 LUMPCC 0.0001288988 DR + +*CONN +*I mux_top_track_4\/mux_l4_in_0_:X O *L 0 *C 40.305 112.540 +*I mux_top_track_4\/mux_l5_in_0_:A1 I *L 0.00198 *C 44.720 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 44.683 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 40.343 112.540 + +*CAP +0 mux_top_track_4\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l5_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0002286535 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0002286535 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_tree_tapbuf_size16_0_sram[4]:6 6.444942e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_tree_tapbuf_size16_0_sram[4]:7 6.444942e-05 + +*RES +0 mux_top_track_4\/mux_l4_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_top_track_4\/mux_l5_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.003875001 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005619841 //LENGTH 40.015 LUMPCC 0.0003561882 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 77.565 83.640 +*I mux_right_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 116.840 83.300 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 116.840 83.300 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 116.840 83.640 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 77.603 83.640 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.053309e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.002615347 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002585772 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 right_top_grid_pin_45_[0]:7 0.0001487257 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 right_top_grid_pin_45_[0]:10 2.93684e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 right_top_grid_pin_45_[0]:8 0.0001487257 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 right_top_grid_pin_45_[0]:13 2.93684e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.03503349 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007035122 //LENGTH 4.595 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 52.155 89.080 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 48.205 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 48.205 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 48.300 89.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 52.117 89.080 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.867578e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003357629 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003070736 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003408482 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001346243 //LENGTH 9.540 LUMPCC 0.0007243971 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_1_:X O *L 0 *C 96.885 47.600 +*I mux_top_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 105.515 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 105.478 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 104.420 47.940 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 104.420 47.600 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 96.922 47.600 + +*CAP +0 mux_top_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.342756e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.765174e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002564953 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000232271 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:21 7.005225e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:22 7.005225e-05 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size10_1_sram[0]:22 4.94496e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size10_1_sram[0]:21 0.0001250011 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size10_1_sram[0]:22 0.0001250011 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size10_1_sram[0]:21 4.94496e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.99285e-06 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001087027 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001087027 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.99285e-06 + +*RES +0 mux_top_track_8\/mux_l2_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.006694197 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009441964 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001219171 //LENGTH 10.225 LUMPCC 0.0001355252 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_2_:X O *L 0 *C 103.785 65.960 +*I mux_right_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 108.660 61.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 108.623 61.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 104.465 61.540 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 104.420 61.585 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 104.420 65.915 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 104.375 65.960 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 103.823 65.960 + +*CAP +0 mux_right_track_8\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002216257 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002216257 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002527772 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002527772 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.642016e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.642016e-05 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_3_sram[1]:19 5.545078e-05 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_3_sram[1]:18 5.545078e-05 +10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_3_sram[1]:17 1.231183e-05 +11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_3_sram[1]:8 1.231183e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_2_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_8\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003712054 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001696318 //LENGTH 14.625 LUMPCC 0.0004738422 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_2_:X O *L 0 *C 92.635 33.660 +*I mux_bottom_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 94.860 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 94.823 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.045 23.460 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.000 23.505 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.000 33.615 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.045 33.660 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 92.598 33.660 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001156836 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001156836 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004376807 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004376807 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.687345e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.687345e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_6_sram[1]:15 8.316012e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_6_sram[1]:16 8.316012e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[1]:17 7.291169e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_6_sram[1]:20 2.118415e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_6_sram[1]:20 7.291169e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_6_sram[1]:21 2.118415e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.966515e-05 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.966515e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_2_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002479911 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.009026786 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005668671 //LENGTH 4.240 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_2_:X O *L 0 *C 42.495 77.860 +*I mux_left_track_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 38.545 77.860 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 38.583 77.860 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 42.458 77.860 + +*CAP +0 mux_left_track_9\/mux_l2_in_2_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_1_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002824335 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002824335 + +*RES +0 mux_left_track_9\/mux_l2_in_2_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_9\/mux_l3_in_1_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003459821 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001128589 //LENGTH 8.100 LUMPCC 0.0005393135 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_2_:X O *L 0 *C 69.635 64.260 +*I mux_left_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 66.145 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 66.183 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 67.160 61.540 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 67.160 61.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 68.955 61.200 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 69.000 61.245 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 69.000 64.215 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 69.045 64.260 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 69.597 64.260 + +*CAP +0 mux_left_track_25\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.553804e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000111282 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001062249 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.04809e-05 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.124474e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.124474e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 3.063022e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 3.063022e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_top_in[9]:26 8.600634e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[9]:30 7.169758e-06 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[9]:27 8.600634e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_top_in[9]:27 7.169758e-06 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_11_sram[0]:10 1.528008e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_11_sram[0]:9 7.513055e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_11_sram[0]:11 5.209729e-06 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size10_11_sram[0]:12 3.352043e-05 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_11_sram[0]:7 5.209729e-06 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_11_sram[0]:10 7.513055e-05 +20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size10_11_sram[0]:5 3.352043e-05 +21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_11_sram[0]:11 1.528008e-05 +22 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size10_2_sram[0]:6 1.867118e-05 +23 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size10_2_sram[0]:5 2.864362e-05 +24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size10_2_sram[0]:7 2.51032e-08 +25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size10_2_sram[0]:8 2.51032e-08 +26 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size10_2_sram[0]:5 1.867118e-05 +27 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:6 2.864362e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_2_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_25\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001602679 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002651786 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0004933036 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008727679 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002869066 //LENGTH 26.040 LUMPCC 7.961949e-05 DR + +*CONN +*I mux_left_track_33\/mux_l3_in_0_:X O *L 0 *C 12.135 65.960 +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 8.030 44.735 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 8.068 44.830 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 9.615 44.880 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 9.660 44.925 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 9.660 65.915 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 9.705 65.960 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 12.098 65.960 + +*CAP +0 mux_left_track_33\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001094352 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001094352 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001098729 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001098729 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001855595 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001855595 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 3.980974e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 3.980974e-05 + +*RES +0 mux_left_track_33\/mux_l3_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001381696 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.01874107 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002136161 + +*END + +*D_NET ropt_net_196 0.002053582 //LENGTH 17.945 LUMPCC 0.0001997038 DR + +*CONN +*I FTB_35__34:X O *L 0 *C 98.900 117.640 +*I ropt_mt_inst_837:A I *L 0.001766 *C 103.960 126.480 +*N ropt_net_196:2 *C 103.922 126.480 +*N ropt_net_196:3 *C 101.245 126.480 +*N ropt_net_196:4 *C 101.200 126.480 +*N ropt_net_196:5 *C 101.193 126.480 +*N ropt_net_196:6 *C 97.528 126.480 +*N ropt_net_196:7 *C 97.520 126.422 +*N ropt_net_196:8 *C 97.520 117.685 +*N ropt_net_196:9 *C 97.565 117.640 +*N ropt_net_196:10 *C 98.863 117.640 + +*CAP +0 FTB_35__34:X 1e-06 +1 ropt_mt_inst_837:A 1e-06 +2 ropt_net_196:2 0.0001741313 +3 ropt_net_196:3 0.0001741313 +4 ropt_net_196:4 3.165882e-05 +5 ropt_net_196:5 0.0002279828 +6 ropt_net_196:6 0.0002279828 +7 ropt_net_196:7 0.0004040668 +8 ropt_net_196:8 0.0004040668 +9 ropt_net_196:9 0.0001039287 +10 ropt_net_196:10 0.0001039287 +11 ropt_net_196:7 chany_top_out[14]:3 9.985192e-05 +12 ropt_net_196:8 chany_top_out[14]:4 9.985192e-05 + +*RES +0 FTB_35__34:X ropt_net_196:10 0.152 +1 ropt_net_196:2 ropt_mt_inst_837:A 0.152 +2 ropt_net_196:3 ropt_net_196:2 0.002390625 +3 ropt_net_196:4 ropt_net_196:3 0.0045 +4 ropt_net_196:5 ropt_net_196:4 0.00341 +5 ropt_net_196:7 ropt_net_196:6 0.00341 +6 ropt_net_196:6 ropt_net_196:5 0.0005741833 +7 ropt_net_196:9 ropt_net_196:8 0.0045 +8 ropt_net_196:8 ropt_net_196:7 0.00780134 +9 ropt_net_196:10 ropt_net_196:9 0.001158482 + +*END + +*D_NET chany_top_out[15] 0.001038932 //LENGTH 7.145 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_857:X O *L 0 *C 55.325 126.820 +*P chany_top_out[15] O *L 0.7423 *C 51.060 129.235 +*N chany_top_out[15]:2 *C 51.060 126.865 +*N chany_top_out[15]:3 *C 51.105 126.820 +*N chany_top_out[15]:4 *C 55.288 126.820 + +*CAP +0 ropt_mt_inst_857:X 1e-06 +1 chany_top_out[15] 0.0001569936 +2 chany_top_out[15]:2 0.0001569936 +3 chany_top_out[15]:3 0.0003619724 +4 chany_top_out[15]:4 0.0003619724 + +*RES +0 ropt_mt_inst_857:X chany_top_out[15]:4 0.152 +1 chany_top_out[15]:3 chany_top_out[15]:2 0.0045 +2 chany_top_out[15]:2 chany_top_out[15] 0.002116072 +3 chany_top_out[15]:4 chany_top_out[15]:3 0.003734375 + +*END + +*D_NET ropt_net_170 0.003140359 //LENGTH 20.985 LUMPCC 0.000871992 DR + +*CONN +*I BUFT_P_115:X O *L 0 *C 66.700 6.460 +*I ropt_mt_inst_808:A I *L 0.001766 *C 83.720 4.080 +*N ropt_net_170:2 *C 83.683 4.080 +*N ropt_net_170:3 *C 80.500 4.080 +*N ropt_net_170:4 *C 80.500 3.740 +*N ropt_net_170:5 *C 66.745 3.740 +*N ropt_net_170:6 *C 66.700 3.785 +*N ropt_net_170:7 *C 66.700 6.415 +*N ropt_net_170:8 *C 66.700 6.460 + +*CAP +0 BUFT_P_115:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_170:2 0.0001543198 +3 ropt_net_170:3 0.0001813779 +4 ropt_net_170:4 0.0008381912 +5 ropt_net_170:5 0.0008111331 +6 ropt_net_170:6 0.0001228552 +7 ropt_net_170:7 0.0001228552 +8 ropt_net_170:8 3.563472e-05 +9 ropt_net_170:2 chany_top_in[9]:8 0.0001118744 +10 ropt_net_170:3 chany_top_in[9]:9 0.0001118744 +11 ropt_net_170:5 chany_top_in[10]:7 9.360537e-05 +12 ropt_net_170:4 chany_top_in[10]:6 9.360537e-05 +13 ropt_net_170:7 chany_bottom_in[14]:47 7.938847e-05 +14 ropt_net_170:6 chany_bottom_in[14] 7.938847e-05 +15 ropt_net_170:5 ropt_net_203:7 9.345935e-05 +16 ropt_net_170:4 ropt_net_203:6 9.345935e-05 +17 ropt_net_170:5 ropt_net_209:5 5.766841e-05 +18 ropt_net_170:4 ropt_net_209:6 5.766841e-05 + +*RES +0 BUFT_P_115:X ropt_net_170:8 0.152 +1 ropt_net_170:8 ropt_net_170:7 0.0045 +2 ropt_net_170:7 ropt_net_170:6 0.002348214 +3 ropt_net_170:5 ropt_net_170:4 0.01228125 +4 ropt_net_170:6 ropt_net_170:5 0.0045 +5 ropt_net_170:2 ropt_mt_inst_808:A 0.152 +6 ropt_net_170:4 ropt_net_170:3 0.0003035715 +7 ropt_net_170:3 ropt_net_170:2 0.002841518 + +*END + +*D_NET chanx_left_out[19] 0.0009656656 //LENGTH 7.375 LUMPCC 0.0001300756 DR + +*CONN +*I ropt_mt_inst_880:X O *L 0 *C 7.095 90.440 +*P chanx_left_out[19] O *L 0.7423 *C 1.298 91.120 +*N chanx_left_out[19]:2 *C 1.380 91.120 +*N chanx_left_out[19]:3 *C 1.380 91.062 +*N chanx_left_out[19]:4 *C 1.380 90.485 +*N chanx_left_out[19]:5 *C 1.425 90.440 +*N chanx_left_out[19]:6 *C 7.058 90.440 + +*CAP +0 ropt_mt_inst_880:X 1e-06 +1 chanx_left_out[19] 3.016353e-05 +2 chanx_left_out[19]:2 3.016353e-05 +3 chanx_left_out[19]:3 5.854107e-05 +4 chanx_left_out[19]:4 5.854107e-05 +5 chanx_left_out[19]:5 0.0003285904 +6 chanx_left_out[19]:6 0.0003285904 +7 chanx_left_out[19]:6 ropt_net_183:8 6.503781e-05 +8 chanx_left_out[19]:5 ropt_net_183:7 6.503781e-05 + +*RES +0 ropt_mt_inst_880:X chanx_left_out[19]:6 0.152 +1 chanx_left_out[19]:6 chanx_left_out[19]:5 0.005029018 +2 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0045 +3 chanx_left_out[19]:4 chanx_left_out[19]:3 0.000515625 +4 chanx_left_out[19]:3 chanx_left_out[19]:2 0.00341 +5 chanx_left_out[19]:2 chanx_left_out[19] 2.35e-05 + +*END + +*D_NET chanx_right_in[5] 0.03365653 //LENGTH 211.910 LUMPCC 0.0137446 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 140.375 95.200 +*I mux_top_track_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 39.850 107.780 +*I BUFT_RR_86:A I *L 0.001776 *C 14.720 50.320 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 41.230 39.100 +*I mux_left_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 41.860 88.740 +*N chanx_right_in[5]:5 *C 41.860 88.740 +*N chanx_right_in[5]:6 *C 41.860 88.695 +*N chanx_right_in[5]:7 *C 41.268 39.100 +*N chanx_right_in[5]:8 *C 41.815 39.100 +*N chanx_right_in[5]:9 *C 41.860 39.145 +*N chanx_right_in[5]:10 *C 14.720 50.320 +*N chanx_right_in[5]:11 *C 14.720 50.320 +*N chanx_right_in[5]:12 *C 14.728 50.320 +*N chanx_right_in[5]:13 *C 41.852 50.320 +*N chanx_right_in[5]:14 *C 41.860 50.320 +*N chanx_right_in[5]:15 *C 41.860 87.040 +*N chanx_right_in[5]:16 *C 41.400 87.040 +*N chanx_right_in[5]:17 *C 41.400 87.663 +*N chanx_right_in[5]:18 *C 41.393 87.720 +*N chanx_right_in[5]:19 *C 39.580 87.720 +*N chanx_right_in[5]:20 *C 39.560 87.728 +*N chanx_right_in[5]:21 *C 39.560 101.312 +*N chanx_right_in[5]:22 *C 39.850 107.780 +*N chanx_right_in[5]:23 *C 40.020 107.780 +*N chanx_right_in[5]:24 *C 40.020 107.735 +*N chanx_right_in[5]:25 *C 40.020 103.020 +*N chanx_right_in[5]:26 *C 39.560 103.020 +*N chanx_right_in[5]:27 *C 39.560 101.378 +*N chanx_right_in[5]:28 *C 39.568 101.320 +*N chanx_right_in[5]:29 *C 89.370 101.320 +*N chanx_right_in[5]:30 *C 121.893 101.320 +*N chanx_right_in[5]:31 *C 121.900 101.263 +*N chanx_right_in[5]:32 *C 121.900 95.938 +*N chanx_right_in[5]:33 *C 121.907 95.880 +*N chanx_right_in[5]:34 *C 140.300 95.880 + +*CAP +0 chanx_right_in[5] 4.768283e-05 +1 mux_top_track_4\/mux_l2_in_3_:A0 1e-06 +2 BUFT_RR_86:A 1e-06 +3 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +4 mux_left_track_5\/mux_l2_in_1_:A1 1e-06 +5 chanx_right_in[5]:5 3.639967e-05 +6 chanx_right_in[5]:6 0.0001300047 +7 chanx_right_in[5]:7 5.542282e-05 +8 chanx_right_in[5]:8 5.542282e-05 +9 chanx_right_in[5]:9 0.000486401 +10 chanx_right_in[5]:10 2.799802e-05 +11 chanx_right_in[5]:11 3.070126e-05 +12 chanx_right_in[5]:12 0.001253831 +13 chanx_right_in[5]:13 0.001253831 +14 chanx_right_in[5]:14 0.002378845 +15 chanx_right_in[5]:15 0.00201619 +16 chanx_right_in[5]:16 7.782843e-05 +17 chanx_right_in[5]:17 4.567178e-05 +18 chanx_right_in[5]:18 0.0002290924 +19 chanx_right_in[5]:19 0.0002290924 +20 chanx_right_in[5]:20 0.0008860588 +21 chanx_right_in[5]:21 0.0008860588 +22 chanx_right_in[5]:22 5.909087e-05 +23 chanx_right_in[5]:23 6.539559e-05 +24 chanx_right_in[5]:24 0.0002851771 +25 chanx_right_in[5]:25 0.000312878 +26 chanx_right_in[5]:26 0.0001414266 +27 chanx_right_in[5]:27 0.0001137257 +28 chanx_right_in[5]:28 0.002272727 +29 chanx_right_in[5]:29 0.003532702 +30 chanx_right_in[5]:30 0.001259974 +31 chanx_right_in[5]:31 0.0003091354 +32 chanx_right_in[5]:32 0.0003091354 +33 chanx_right_in[5]:33 0.0005361716 +34 chanx_right_in[5]:34 0.0005838544 +35 chanx_right_in[5]:28 chanx_right_in[4]:25 1.549698e-05 +36 chanx_right_in[5]:13 chanx_right_in[4]:18 1.195992e-06 +37 chanx_right_in[5]:12 chanx_right_in[4]:17 1.195992e-06 +38 chanx_right_in[5]:30 chanx_right_in[4]:26 2.405303e-05 +39 chanx_right_in[5]:30 chanx_right_in[4]:30 1.005787e-05 +40 chanx_right_in[5]:33 chanx_right_in[4]:33 0.0002354071 +41 chanx_right_in[5]:33 chanx_right_in[4]:35 2.065022e-05 +42 chanx_right_in[5]:34 chanx_right_in[4] 2.065022e-05 +43 chanx_right_in[5]:34 chanx_right_in[4]:34 0.0002354071 +44 chanx_right_in[5]:29 chanx_right_in[4]:25 2.405303e-05 +45 chanx_right_in[5]:29 chanx_right_in[4]:26 1.549698e-05 +46 chanx_right_in[5]:29 chanx_right_in[4]:29 1.005787e-05 +47 chanx_right_in[5]:28 chanx_right_in[12]:23 1.386688e-06 +48 chanx_right_in[5]:28 chanx_right_in[12]:29 2.960649e-06 +49 chanx_right_in[5]:28 chanx_right_in[12]:11 4.163569e-06 +50 chanx_right_in[5]:30 chanx_right_in[12] 4.019818e-06 +51 chanx_right_in[5]:30 chanx_right_in[12]:30 1.106917e-07 +52 chanx_right_in[5]:33 chanx_right_in[12]:31 0.001055936 +53 chanx_right_in[5]:34 chanx_right_in[12] 0.001055936 +54 chanx_right_in[5]:29 chanx_right_in[12]:23 4.163569e-06 +55 chanx_right_in[5]:29 chanx_right_in[12]:28 1.386688e-06 +56 chanx_right_in[5]:29 chanx_right_in[12]:29 1.106917e-07 +57 chanx_right_in[5]:29 chanx_right_in[12]:30 2.960649e-06 +58 chanx_right_in[5]:29 chanx_right_in[12]:31 4.019818e-06 +59 chanx_right_in[5]:28 chany_bottom_in[4]:16 0.001065653 +60 chanx_right_in[5]:28 chany_bottom_in[4]:10 2.38331e-05 +61 chanx_right_in[5]:30 chany_bottom_in[4]:9 0.0001348352 +62 chanx_right_in[5]:29 chany_bottom_in[4]:15 0.001065653 +63 chanx_right_in[5]:29 chany_bottom_in[4]:10 0.0001348352 +64 chanx_right_in[5]:29 chany_bottom_in[4]:9 2.38331e-05 +65 chanx_right_in[5]:28 chanx_left_in[12]:37 0.0002954243 +66 chanx_right_in[5]:28 chanx_left_in[12]:36 0.0003420913 +67 chanx_right_in[5]:33 chanx_left_in[12]:15 5.073609e-06 +68 chanx_right_in[5]:34 chanx_left_in[12]:14 5.073609e-06 +69 chanx_right_in[5]:29 chanx_left_in[12]:35 0.0003420913 +70 chanx_right_in[5]:29 chanx_left_in[12]:36 0.0002954243 +71 chanx_right_in[5]:14 chanx_left_in[16]:41 5.675786e-06 +72 chanx_right_in[5]:13 chanx_left_in[16]:41 0.0003474434 +73 chanx_right_in[5]:13 chanx_left_in[16]:39 1.454578e-05 +74 chanx_right_in[5]:12 chanx_left_in[16] 0.0003474434 +75 chanx_right_in[5]:12 chanx_left_in[16]:40 1.454578e-05 +76 chanx_right_in[5]:15 chanx_left_in[16]:40 5.675786e-06 +77 chanx_right_in[5]:28 prog_clk[0]:586 0.000837017 +78 chanx_right_in[5]:28 prog_clk[0]:587 0.0002566065 +79 chanx_right_in[5]:14 prog_clk[0]:415 2.155368e-05 +80 chanx_right_in[5]:31 prog_clk[0]:143 1.427672e-06 +81 chanx_right_in[5]:30 prog_clk[0]:248 1.716104e-05 +82 chanx_right_in[5]:32 prog_clk[0]:149 1.427672e-06 +83 chanx_right_in[5]:15 prog_clk[0]:456 2.155368e-05 +84 chanx_right_in[5]:29 prog_clk[0]:576 0.000837017 +85 chanx_right_in[5]:29 prog_clk[0]:586 0.0002566065 +86 chanx_right_in[5]:29 prog_clk[0]:249 1.716104e-05 +87 chanx_right_in[5]:30 right_top_grid_pin_42_[0]:24 0.0004533113 +88 chanx_right_in[5]:30 right_top_grid_pin_42_[0]:25 4.19486e-05 +89 chanx_right_in[5]:30 right_top_grid_pin_42_[0]:27 0.0004157338 +90 chanx_right_in[5]:29 right_top_grid_pin_42_[0]:24 4.19486e-05 +91 chanx_right_in[5]:29 right_top_grid_pin_42_[0]:8 0.0004533113 +92 chanx_right_in[5]:29 right_top_grid_pin_42_[0]:26 0.0004157338 +93 chanx_right_in[5]:14 chanx_left_in[3]:8 0.0004071351 +94 chanx_right_in[5]:14 chanx_left_in[3]:7 0.0002840839 +95 chanx_right_in[5]:14 chanx_left_in[3]:6 5.419768e-07 +96 chanx_right_in[5]:9 chanx_left_in[3]:8 0.0002840839 +97 chanx_right_in[5]:15 chanx_left_in[3]:5 5.419768e-07 +98 chanx_right_in[5]:15 chanx_left_in[3]:7 0.0004071351 +99 chanx_right_in[5]:21 chanx_left_in[19]:10 3.123232e-05 +100 chanx_right_in[5]:20 chanx_left_in[19]:11 3.123232e-05 +101 chanx_right_in[5]:13 chanx_left_in[19]:12 0.0004945333 +102 chanx_right_in[5]:12 chanx_left_in[19]:13 0.0004945333 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:34 0.0001065333 +1 chanx_right_in[5]:22 mux_top_track_4\/mux_l2_in_3_:A0 0.152 +2 chanx_right_in[5]:23 chanx_right_in[5]:22 9.239131e-05 +3 chanx_right_in[5]:24 chanx_right_in[5]:23 0.0045 +4 chanx_right_in[5]:27 chanx_right_in[5]:26 0.001466518 +5 chanx_right_in[5]:28 chanx_right_in[5]:27 0.00341 +6 chanx_right_in[5]:28 chanx_right_in[5]:21 0.00341 +7 chanx_right_in[5]:21 chanx_right_in[5]:20 0.002128317 +8 chanx_right_in[5]:19 chanx_right_in[5]:18 0.0002839583 +9 chanx_right_in[5]:20 chanx_right_in[5]:19 0.00341 +10 chanx_right_in[5]:17 chanx_right_in[5]:16 0.0005558036 +11 chanx_right_in[5]:18 chanx_right_in[5]:17 0.00341 +12 chanx_right_in[5]:14 chanx_right_in[5]:13 0.00341 +13 chanx_right_in[5]:14 chanx_right_in[5]:9 0.00997768 +14 chanx_right_in[5]:13 chanx_right_in[5]:12 0.004249583 +15 chanx_right_in[5]:11 chanx_right_in[5]:10 0.0045 +16 chanx_right_in[5]:12 chanx_right_in[5]:11 0.00341 +17 chanx_right_in[5]:10 BUFT_RR_86:A 0.152 +18 chanx_right_in[5]:5 mux_left_track_5\/mux_l2_in_1_:A1 0.152 +19 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +20 chanx_right_in[5]:8 chanx_right_in[5]:7 0.0004888393 +21 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0045 +22 chanx_right_in[5]:7 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 +23 chanx_right_in[5]:31 chanx_right_in[5]:30 0.00341 +24 chanx_right_in[5]:30 chanx_right_in[5]:29 0.005095191 +25 chanx_right_in[5]:32 chanx_right_in[5]:31 0.004754465 +26 chanx_right_in[5]:33 chanx_right_in[5]:32 0.00341 +27 chanx_right_in[5]:26 chanx_right_in[5]:25 0.0004107143 +28 chanx_right_in[5]:25 chanx_right_in[5]:24 0.004209822 +29 chanx_right_in[5]:16 chanx_right_in[5]:15 0.0004107143 +30 chanx_right_in[5]:15 chanx_right_in[5]:14 0.03278572 +31 chanx_right_in[5]:15 chanx_right_in[5]:6 0.001477678 +32 chanx_right_in[5]:34 chanx_right_in[5]:33 0.002881491 +33 chanx_right_in[5]:29 chanx_right_in[5]:28 0.007802391 + +*END + +*D_NET right_top_grid_pin_48_[0] 0.01196153 //LENGTH 85.105 LUMPCC 0.003714425 DR + +*CONN +*P right_top_grid_pin_48_[0] I *L 0.29796 *C 135.700 102.070 +*I mux_right_track_4\/mux_l2_in_4_:A1 I *L 0.00198 *C 118.220 85.340 +*I mux_right_track_24\/mux_l1_in_2_:A1 I *L 0.00198 *C 90.160 83.300 +*I mux_right_track_0\/mux_l1_in_3_:A1 I *L 0.00198 *C 92.560 99.620 +*N right_top_grid_pin_48_[0]:4 *C 92.460 99.620 +*N right_top_grid_pin_48_[0]:5 *C 92.460 99.575 +*N right_top_grid_pin_48_[0]:6 *C 90.198 83.300 +*N right_top_grid_pin_48_[0]:7 *C 92.415 83.300 +*N right_top_grid_pin_48_[0]:8 *C 92.460 83.345 +*N right_top_grid_pin_48_[0]:9 *C 92.460 86.360 +*N right_top_grid_pin_48_[0]:10 *C 92.920 86.360 +*N right_top_grid_pin_48_[0]:11 *C 92.928 86.360 +*N right_top_grid_pin_48_[0]:12 *C 117.753 86.360 +*N right_top_grid_pin_48_[0]:13 *C 117.760 86.303 +*N right_top_grid_pin_48_[0]:14 *C 118.183 85.340 +*N right_top_grid_pin_48_[0]:15 *C 117.805 85.340 +*N right_top_grid_pin_48_[0]:16 *C 117.760 85.340 +*N right_top_grid_pin_48_[0]:17 *C 117.760 84.377 +*N right_top_grid_pin_48_[0]:18 *C 117.768 84.320 +*N right_top_grid_pin_48_[0]:19 *C 129.252 84.320 +*N right_top_grid_pin_48_[0]:20 *C 129.260 84.377 +*N right_top_grid_pin_48_[0]:21 *C 129.260 91.415 +*N right_top_grid_pin_48_[0]:22 *C 129.305 91.460 +*N right_top_grid_pin_48_[0]:23 *C 135.655 91.460 +*N right_top_grid_pin_48_[0]:24 *C 135.700 91.505 + +*CAP +0 right_top_grid_pin_48_[0] 0.0005937782 +1 mux_right_track_4\/mux_l2_in_4_:A1 1e-06 +2 mux_right_track_24\/mux_l1_in_2_:A1 1e-06 +3 mux_right_track_0\/mux_l1_in_3_:A1 1e-06 +4 right_top_grid_pin_48_[0]:4 3.215816e-05 +5 right_top_grid_pin_48_[0]:5 0.0007784764 +6 right_top_grid_pin_48_[0]:6 0.0002052598 +7 right_top_grid_pin_48_[0]:7 0.0002052598 +8 right_top_grid_pin_48_[0]:8 0.0001820964 +9 right_top_grid_pin_48_[0]:9 0.0009944146 +10 right_top_grid_pin_48_[0]:10 6.921752e-05 +11 right_top_grid_pin_48_[0]:11 0.001173704 +12 right_top_grid_pin_48_[0]:12 0.001173704 +13 right_top_grid_pin_48_[0]:13 4.869498e-05 +14 right_top_grid_pin_48_[0]:14 5.625874e-05 +15 right_top_grid_pin_48_[0]:15 5.625874e-05 +16 right_top_grid_pin_48_[0]:16 0.0001287405 +17 right_top_grid_pin_48_[0]:17 4.749688e-05 +18 right_top_grid_pin_48_[0]:18 0.0002014936 +19 right_top_grid_pin_48_[0]:19 0.0002014936 +20 right_top_grid_pin_48_[0]:20 0.0003765739 +21 right_top_grid_pin_48_[0]:21 0.0003765739 +22 right_top_grid_pin_48_[0]:22 0.0003743354 +23 right_top_grid_pin_48_[0]:23 0.0003743354 +24 right_top_grid_pin_48_[0]:24 0.0005937782 +25 right_top_grid_pin_48_[0]:8 chanx_left_in[2]:20 1.425316e-07 +26 right_top_grid_pin_48_[0]:12 chanx_left_in[2]:11 1.552966e-05 +27 right_top_grid_pin_48_[0]:12 chanx_left_in[2]:13 3.123219e-05 +28 right_top_grid_pin_48_[0]:12 chanx_left_in[2]:15 1.857709e-06 +29 right_top_grid_pin_48_[0]:11 chanx_left_in[2]:12 1.552966e-05 +30 right_top_grid_pin_48_[0]:11 chanx_left_in[2]:14 3.123219e-05 +31 right_top_grid_pin_48_[0]:11 chanx_left_in[2]:22 1.857709e-06 +32 right_top_grid_pin_48_[0]:19 chanx_left_in[2]:11 0.0002945706 +33 right_top_grid_pin_48_[0]:18 chanx_left_in[2]:12 0.0002945706 +34 right_top_grid_pin_48_[0]:9 chanx_left_in[2]:19 1.425316e-07 +35 right_top_grid_pin_48_[0]:8 prog_clk[0]:264 2.233631e-07 +36 right_top_grid_pin_48_[0]:8 prog_clk[0]:270 5.912553e-07 +37 right_top_grid_pin_48_[0]:13 prog_clk[0]:149 2.052657e-05 +38 right_top_grid_pin_48_[0]:13 prog_clk[0]:160 8.068247e-06 +39 right_top_grid_pin_48_[0]:12 prog_clk[0]:259 0.0001449629 +40 right_top_grid_pin_48_[0]:11 prog_clk[0]:260 0.0001449629 +41 right_top_grid_pin_48_[0]:5 prog_clk[0]:261 5.682621e-07 +42 right_top_grid_pin_48_[0]:16 prog_clk[0]:160 5.120546e-05 +43 right_top_grid_pin_48_[0]:16 prog_clk[0]:166 8.068247e-06 +44 right_top_grid_pin_48_[0]:21 prog_clk[0]:152 9.794589e-06 +45 right_top_grid_pin_48_[0]:20 prog_clk[0]:153 9.794589e-06 +46 right_top_grid_pin_48_[0]:19 prog_clk[0]:154 5.413128e-07 +47 right_top_grid_pin_48_[0]:19 prog_clk[0]:158 7.696883e-05 +48 right_top_grid_pin_48_[0]:17 prog_clk[0]:166 3.067889e-05 +49 right_top_grid_pin_48_[0]:18 prog_clk[0]:158 5.413128e-07 +50 right_top_grid_pin_48_[0]:18 prog_clk[0]:159 7.696883e-05 +51 right_top_grid_pin_48_[0]:9 prog_clk[0]:261 2.233631e-07 +52 right_top_grid_pin_48_[0]:9 prog_clk[0]:264 1.159517e-06 +53 right_top_grid_pin_48_[0]:12 mux_tree_tapbuf_size16_1_sram[0]:20 0.0004708981 +54 right_top_grid_pin_48_[0]:11 mux_tree_tapbuf_size16_1_sram[0]:19 0.0004708981 +55 right_top_grid_pin_48_[0]:21 mux_tree_tapbuf_size16_1_sram[0]:21 4.07492e-07 +56 right_top_grid_pin_48_[0]:21 mux_tree_tapbuf_size16_1_sram[0]:22 6.013627e-06 +57 right_top_grid_pin_48_[0]:20 mux_tree_tapbuf_size16_1_sram[0]:6 4.07492e-07 +58 right_top_grid_pin_48_[0]:20 mux_tree_tapbuf_size16_1_sram[0]:21 6.013627e-06 +59 right_top_grid_pin_48_[0]:19 mux_tree_tapbuf_size16_1_sram[0]:20 6.262031e-06 +60 right_top_grid_pin_48_[0]:18 mux_tree_tapbuf_size16_1_sram[0]:19 6.262031e-06 +61 right_top_grid_pin_48_[0]:21 mux_tree_tapbuf_size16_1_sram[1]:55 8.359169e-07 +62 right_top_grid_pin_48_[0]:20 mux_tree_tapbuf_size16_1_sram[1]:54 8.359169e-07 +63 right_top_grid_pin_48_[0]:19 mux_tree_tapbuf_size16_1_sram[1]:53 0.0004673173 +64 right_top_grid_pin_48_[0]:18 mux_tree_tapbuf_size16_1_sram[1]:52 0.0004673173 +65 right_top_grid_pin_48_[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002692212 +66 right_top_grid_pin_48_[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002692212 + +*RES +0 right_top_grid_pin_48_[0] right_top_grid_pin_48_[0]:24 0.009433037 +1 right_top_grid_pin_48_[0]:7 right_top_grid_pin_48_[0]:6 0.001979911 +2 right_top_grid_pin_48_[0]:8 right_top_grid_pin_48_[0]:7 0.0045 +3 right_top_grid_pin_48_[0]:6 mux_right_track_24\/mux_l1_in_2_:A1 0.152 +4 right_top_grid_pin_48_[0]:13 right_top_grid_pin_48_[0]:12 0.00341 +5 right_top_grid_pin_48_[0]:12 right_top_grid_pin_48_[0]:11 0.00388925 +6 right_top_grid_pin_48_[0]:10 right_top_grid_pin_48_[0]:9 0.0004107143 +7 right_top_grid_pin_48_[0]:11 right_top_grid_pin_48_[0]:10 0.00341 +8 right_top_grid_pin_48_[0]:4 mux_right_track_0\/mux_l1_in_3_:A1 0.152 +9 right_top_grid_pin_48_[0]:5 right_top_grid_pin_48_[0]:4 0.0045 +10 right_top_grid_pin_48_[0]:15 right_top_grid_pin_48_[0]:14 0.0003370536 +11 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:15 0.0045 +12 right_top_grid_pin_48_[0]:16 right_top_grid_pin_48_[0]:13 0.0008593751 +13 right_top_grid_pin_48_[0]:14 mux_right_track_4\/mux_l2_in_4_:A1 0.152 +14 right_top_grid_pin_48_[0]:23 right_top_grid_pin_48_[0]:22 0.005669643 +15 right_top_grid_pin_48_[0]:24 right_top_grid_pin_48_[0]:23 0.0045 +16 right_top_grid_pin_48_[0]:22 right_top_grid_pin_48_[0]:21 0.0045 +17 right_top_grid_pin_48_[0]:21 right_top_grid_pin_48_[0]:20 0.006283483 +18 right_top_grid_pin_48_[0]:20 right_top_grid_pin_48_[0]:19 0.00341 +19 right_top_grid_pin_48_[0]:19 right_top_grid_pin_48_[0]:18 0.001799317 +20 right_top_grid_pin_48_[0]:17 right_top_grid_pin_48_[0]:16 0.000859375 +21 right_top_grid_pin_48_[0]:18 right_top_grid_pin_48_[0]:17 0.00341 +22 right_top_grid_pin_48_[0]:9 right_top_grid_pin_48_[0]:8 0.002691964 +23 right_top_grid_pin_48_[0]:9 right_top_grid_pin_48_[0]:5 0.01179911 + +*END + +*D_NET chanx_left_in[3] 0.01261465 //LENGTH 101.275 LUMPCC 0.00374805 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 39.440 +*I mux_bottom_track_3\/mux_l1_in_4_:A0 I *L 0.001631 *C 41.115 27.880 +*I mux_top_track_24\/mux_l2_in_2_:A1 I *L 0.00198 *C 50.600 69.020 +*N chanx_left_in[3]:3 *C 50.562 69.020 +*N chanx_left_in[3]:4 *C 44.665 69.020 +*N chanx_left_in[3]:5 *C 44.620 68.975 +*N chanx_left_in[3]:6 *C 44.620 66.980 +*N chanx_left_in[3]:7 *C 42.320 66.980 +*N chanx_left_in[3]:8 *C 42.320 31.960 +*N chanx_left_in[3]:9 *C 41.153 27.880 +*N chanx_left_in[3]:10 *C 41.815 27.880 +*N chanx_left_in[3]:11 *C 41.860 27.925 +*N chanx_left_in[3]:12 *C 41.860 31.960 +*N chanx_left_in[3]:13 *C 41.852 31.960 +*N chanx_left_in[3]:14 *C 8.748 31.960 +*N chanx_left_in[3]:15 *C 8.740 32.017 +*N chanx_left_in[3]:16 *C 8.740 39.383 +*N chanx_left_in[3]:17 *C 8.732 39.440 + +*CAP +0 chanx_left_in[3] 0.0003406624 +1 mux_bottom_track_3\/mux_l1_in_4_:A0 1e-06 +2 mux_top_track_24\/mux_l2_in_2_:A1 1e-06 +3 chanx_left_in[3]:3 0.0003959894 +4 chanx_left_in[3]:4 0.0003959894 +5 chanx_left_in[3]:5 0.0001389346 +6 chanx_left_in[3]:6 0.0002768505 +7 chanx_left_in[3]:7 0.001675126 +8 chanx_left_in[3]:8 0.001572596 +9 chanx_left_in[3]:9 6.836806e-05 +10 chanx_left_in[3]:10 6.836806e-05 +11 chanx_left_in[3]:11 0.0002207281 +12 chanx_left_in[3]:12 0.0002561137 +13 chanx_left_in[3]:13 0.001195973 +14 chanx_left_in[3]:14 0.001195973 +15 chanx_left_in[3]:15 0.0003611317 +16 chanx_left_in[3]:16 0.0003611317 +17 chanx_left_in[3]:17 0.0003406624 +18 chanx_left_in[3]:5 chanx_right_in[5]:15 5.419768e-07 +19 chanx_left_in[3]:8 chanx_right_in[5]:9 0.0002840839 +20 chanx_left_in[3]:8 chanx_right_in[5]:14 0.0004071351 +21 chanx_left_in[3]:7 chanx_right_in[5]:14 0.0002840839 +22 chanx_left_in[3]:7 chanx_right_in[5]:15 0.0004071351 +23 chanx_left_in[3]:6 chanx_right_in[5]:14 5.419768e-07 +24 chanx_left_in[3]:13 chanx_left_in[6]:31 9.232249e-06 +25 chanx_left_in[3]:13 chanx_left_in[6]:33 0.0004865633 +26 chanx_left_in[3]:14 chanx_left_in[6] 0.0004865633 +27 chanx_left_in[3]:14 chanx_left_in[6]:32 9.232249e-06 +28 chanx_left_in[3]:8 chanx_left_in[6]:33 1.037986e-05 +29 chanx_left_in[3]:7 chanx_left_in[6]:32 1.037986e-05 +30 chanx_left_in[3] chanx_left_in[1] 9.558913e-05 +31 chanx_left_in[3] chanx_left_in[1]:20 0.000192611 +32 chanx_left_in[3]:15 chanx_left_in[1]:21 2.350659e-05 +33 chanx_left_in[3]:16 chanx_left_in[1]:20 2.350659e-05 +34 chanx_left_in[3]:17 chanx_left_in[1]:19 0.000192611 +35 chanx_left_in[3]:17 chanx_left_in[1]:21 9.558913e-05 +36 chanx_left_in[3]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 3.936913e-05 +37 chanx_left_in[3]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 3.936913e-05 +38 chanx_left_in[3]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 1.530117e-05 +39 chanx_left_in[3]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 1.530117e-05 +40 chanx_left_in[3]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0003097119 +41 chanx_left_in[3]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0003097119 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:17 0.001175392 +1 chanx_left_in[3]:12 chanx_left_in[3]:11 0.003602679 +2 chanx_left_in[3]:12 chanx_left_in[3]:8 0.0004107143 +3 chanx_left_in[3]:13 chanx_left_in[3]:12 0.00341 +4 chanx_left_in[3]:15 chanx_left_in[3]:14 0.00341 +5 chanx_left_in[3]:14 chanx_left_in[3]:13 0.00518645 +6 chanx_left_in[3]:16 chanx_left_in[3]:15 0.006575893 +7 chanx_left_in[3]:17 chanx_left_in[3]:16 0.00341 +8 chanx_left_in[3]:10 chanx_left_in[3]:9 0.0005915179 +9 chanx_left_in[3]:11 chanx_left_in[3]:10 0.0045 +10 chanx_left_in[3]:9 mux_bottom_track_3\/mux_l1_in_4_:A0 0.152 +11 chanx_left_in[3]:4 chanx_left_in[3]:3 0.005265624 +12 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0045 +13 chanx_left_in[3]:3 mux_top_track_24\/mux_l2_in_2_:A1 0.152 +14 chanx_left_in[3]:8 chanx_left_in[3]:7 0.03126786 +15 chanx_left_in[3]:7 chanx_left_in[3]:6 0.002053572 +16 chanx_left_in[3]:6 chanx_left_in[3]:5 0.00178125 + +*END + +*D_NET left_top_grid_pin_49_[0] 0.005798361 //LENGTH 43.730 LUMPCC 0.0002137133 DR + +*CONN +*P left_top_grid_pin_49_[0] I *L 0.29796 *C 10.580 102.035 +*I mux_left_track_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 18.500 99.620 +*I mux_left_track_33\/mux_l1_in_3_:A1 I *L 0.00198 *C 22.540 74.460 +*I mux_left_track_5\/mux_l2_in_7_:A1 I *L 0.00198 *C 18.860 94.180 +*N left_top_grid_pin_49_[0]:4 *C 18.400 99.620 +*N left_top_grid_pin_49_[0]:5 *C 18.860 94.180 +*N left_top_grid_pin_49_[0]:6 *C 18.860 94.180 +*N left_top_grid_pin_49_[0]:7 *C 18.000 94.180 +*N left_top_grid_pin_49_[0]:8 *C 22.503 74.460 +*N left_top_grid_pin_49_[0]:9 *C 21.665 74.460 +*N left_top_grid_pin_49_[0]:10 *C 21.620 74.505 +*N left_top_grid_pin_49_[0]:11 *C 21.620 80.920 +*N left_top_grid_pin_49_[0]:12 *C 20.700 80.920 +*N left_top_grid_pin_49_[0]:13 *C 20.700 81.543 +*N left_top_grid_pin_49_[0]:14 *C 20.693 81.600 +*N left_top_grid_pin_49_[0]:15 *C 18.420 81.600 +*N left_top_grid_pin_49_[0]:16 *C 18.400 81.608 +*N left_top_grid_pin_49_[0]:17 *C 18.400 94.172 +*N left_top_grid_pin_49_[0]:18 *C 18.400 94.180 +*N left_top_grid_pin_49_[0]:19 *C 18.400 94.180 +*N left_top_grid_pin_49_[0]:20 *C 18.400 99.235 +*N left_top_grid_pin_49_[0]:21 *C 18.400 99.280 +*N left_top_grid_pin_49_[0]:22 *C 18.500 99.620 +*N left_top_grid_pin_49_[0]:23 *C 18.400 99.960 +*N left_top_grid_pin_49_[0]:24 *C 10.625 99.960 +*N left_top_grid_pin_49_[0]:25 *C 10.580 100.005 + +*CAP +0 left_top_grid_pin_49_[0] 0.0001246664 +1 mux_left_track_3\/mux_l2_in_3_:A1 1e-06 +2 mux_left_track_33\/mux_l1_in_3_:A1 1e-06 +3 mux_left_track_5\/mux_l2_in_7_:A1 1e-06 +4 left_top_grid_pin_49_[0]:4 1.2312e-05 +5 left_top_grid_pin_49_[0]:5 3.463659e-05 +6 left_top_grid_pin_49_[0]:6 7.074916e-05 +7 left_top_grid_pin_49_[0]:7 6.902164e-05 +8 left_top_grid_pin_49_[0]:8 0.0001084527 +9 left_top_grid_pin_49_[0]:9 0.0001084527 +10 left_top_grid_pin_49_[0]:10 0.0004728165 +11 left_top_grid_pin_49_[0]:11 0.000529187 +12 left_top_grid_pin_49_[0]:12 0.0001119956 +13 left_top_grid_pin_49_[0]:13 5.562502e-05 +14 left_top_grid_pin_49_[0]:14 0.0002114528 +15 left_top_grid_pin_49_[0]:15 0.0002114528 +16 left_top_grid_pin_49_[0]:16 0.0007434959 +17 left_top_grid_pin_49_[0]:17 0.0007434959 +18 left_top_grid_pin_49_[0]:18 6.902164e-05 +19 left_top_grid_pin_49_[0]:19 0.0003796813 +20 left_top_grid_pin_49_[0]:20 0.0003416186 +21 left_top_grid_pin_49_[0]:21 5.490654e-05 +22 left_top_grid_pin_49_[0]:22 8.22763e-05 +23 left_top_grid_pin_49_[0]:23 0.0004704037 +24 left_top_grid_pin_49_[0]:24 0.0004512605 +25 left_top_grid_pin_49_[0]:25 0.0001246664 +26 left_top_grid_pin_49_[0]:24 ropt_net_194:6 0.0001068566 +27 left_top_grid_pin_49_[0]:23 ropt_net_194:7 0.0001068566 + +*RES +0 left_top_grid_pin_49_[0] left_top_grid_pin_49_[0]:25 0.0018125 +1 left_top_grid_pin_49_[0]:19 left_top_grid_pin_49_[0]:18 0.00341 +2 left_top_grid_pin_49_[0]:19 left_top_grid_pin_49_[0]:6 0.0004107143 +3 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:17 0.00341 +4 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:7 5.69697e-05 +5 left_top_grid_pin_49_[0]:17 left_top_grid_pin_49_[0]:16 0.001968517 +6 left_top_grid_pin_49_[0]:15 left_top_grid_pin_49_[0]:14 0.000356025 +7 left_top_grid_pin_49_[0]:16 left_top_grid_pin_49_[0]:15 0.00341 +8 left_top_grid_pin_49_[0]:13 left_top_grid_pin_49_[0]:12 0.0005558037 +9 left_top_grid_pin_49_[0]:14 left_top_grid_pin_49_[0]:13 0.00341 +10 left_top_grid_pin_49_[0]:9 left_top_grid_pin_49_[0]:8 0.0007477679 +11 left_top_grid_pin_49_[0]:10 left_top_grid_pin_49_[0]:9 0.0045 +12 left_top_grid_pin_49_[0]:8 mux_left_track_33\/mux_l1_in_3_:A1 0.152 +13 left_top_grid_pin_49_[0]:21 left_top_grid_pin_49_[0]:20 0.0045 +14 left_top_grid_pin_49_[0]:20 left_top_grid_pin_49_[0]:19 0.004513393 +15 left_top_grid_pin_49_[0]:5 mux_left_track_5\/mux_l2_in_7_:A1 0.152 +16 left_top_grid_pin_49_[0]:6 left_top_grid_pin_49_[0]:5 0.0045 +17 left_top_grid_pin_49_[0]:22 mux_left_track_3\/mux_l2_in_3_:A1 0.152 +18 left_top_grid_pin_49_[0]:22 left_top_grid_pin_49_[0]:21 0.0001847826 +19 left_top_grid_pin_49_[0]:22 left_top_grid_pin_49_[0]:4 1e-05 +20 left_top_grid_pin_49_[0]:24 left_top_grid_pin_49_[0]:23 0.006941965 +21 left_top_grid_pin_49_[0]:25 left_top_grid_pin_49_[0]:24 0.0045 +22 left_top_grid_pin_49_[0]:23 left_top_grid_pin_49_[0]:22 0.0003035715 +23 left_top_grid_pin_49_[0]:12 left_top_grid_pin_49_[0]:11 0.0008214285 +24 left_top_grid_pin_49_[0]:11 left_top_grid_pin_49_[0]:10 0.005727679 + +*END + +*D_NET chanx_right_out[16] 0.003225288 //LENGTH 24.035 LUMPCC 0.001166008 DR + +*CONN +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 126.560 49.980 +*P chanx_right_out[16] O *L 0.7423 *C 140.375 40.800 +*N chanx_right_out[16]:2 *C 140.300 41.480 +*N chanx_right_out[16]:3 *C 126.968 41.480 +*N chanx_right_out[16]:4 *C 126.960 41.538 +*N chanx_right_out[16]:5 *C 126.960 49.935 +*N chanx_right_out[16]:6 *C 126.938 49.980 +*N chanx_right_out[16]:7 *C 126.575 49.980 + +*CAP +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[16] 4.638605e-05 +2 chanx_right_out[16]:2 0.0005738703 +3 chanx_right_out[16]:3 0.0005274842 +4 chanx_right_out[16]:4 0.0004100158 +5 chanx_right_out[16]:5 0.0004100158 +6 chanx_right_out[16]:6 4.525434e-05 +7 chanx_right_out[16]:7 4.525434e-05 +8 chanx_right_out[16]:3 chanx_right_in[16]:54 0.0003025988 +9 chanx_right_out[16]:2 chanx_right_in[16]:55 0.0003025988 +10 chanx_right_out[16]:4 chanx_right_out[12]:6 2.045998e-05 +11 chanx_right_out[16]:3 chanx_right_out[12]:2 0.0002499137 +12 chanx_right_out[16]:3 chanx_right_out[12]:5 1.003134e-05 +13 chanx_right_out[16]:5 chanx_right_out[12]:7 2.045998e-05 +14 chanx_right_out[16]:2 chanx_right_out[12] 0.0002499137 +15 chanx_right_out[16]:2 chanx_right_out[12]:4 1.003134e-05 + +*RES +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[16]:7 0.152 +1 chanx_right_out[16]:4 chanx_right_out[16]:3 0.00341 +2 chanx_right_out[16]:3 chanx_right_out[16]:2 0.002088758 +3 chanx_right_out[16]:6 chanx_right_out[16]:5 0.0045 +4 chanx_right_out[16]:5 chanx_right_out[16]:4 0.007497768 +5 chanx_right_out[16]:7 chanx_right_out[16]:6 0.0001970109 +6 chanx_right_out[16]:2 chanx_right_out[16] 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.005136944 //LENGTH 38.690 LUMPCC 0.0005294917 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 103.805 55.420 +*I mux_top_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 96.040 46.920 +*I mux_top_track_8\/mux_l2_in_3_:S I *L 0.00357 *C 106.140 41.820 +*I mux_top_track_8\/mux_l2_in_2_:S I *L 0.00357 *C 102.460 39.780 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 104.135 37.060 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 100.180 57.725 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 100.218 57.785 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 102.535 57.800 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 102.580 57.755 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 104.135 37.060 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 103.960 37.060 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 103.960 37.060 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 103.960 36.720 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 103.953 36.720 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 102.588 36.720 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 102.580 36.778 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 102.460 39.780 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 102.580 39.780 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 106.103 41.820 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 102.625 41.820 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 102.580 41.820 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 96.078 46.920 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 102.535 46.920 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 102.580 46.920 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 102.580 55.420 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 102.625 55.420 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 103.767 55.420 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_8\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_8\/mux_l2_in_3_:S 1e-06 +3 mux_top_track_8\/mux_l2_in_2_:S 1e-06 +4 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 0.0001661984 +7 mux_tree_tapbuf_size10_0_sram[1]:7 0.0001661984 +8 mux_tree_tapbuf_size10_0_sram[1]:8 0.0001262293 +9 mux_tree_tapbuf_size10_0_sram[1]:9 4.765335e-05 +10 mux_tree_tapbuf_size10_0_sram[1]:10 5.216188e-05 +11 mux_tree_tapbuf_size10_0_sram[1]:11 5.528293e-05 +12 mux_tree_tapbuf_size10_0_sram[1]:12 5.885555e-05 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.000139309 +14 mux_tree_tapbuf_size10_0_sram[1]:14 0.000139309 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0001720351 +16 mux_tree_tapbuf_size10_0_sram[1]:16 3.079973e-05 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0003087222 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.000267585 +19 mux_tree_tapbuf_size10_0_sram[1]:19 0.000267585 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0004127792 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0003674475 +22 mux_tree_tapbuf_size10_0_sram[1]:22 0.0003674475 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0006895484 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0005423866 +25 mux_tree_tapbuf_size10_0_sram[1]:25 0.0001119596 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.0001119596 +27 mux_tree_tapbuf_size10_0_sram[1]:24 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.349811e-05 +28 mux_tree_tapbuf_size10_0_sram[1]:24 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.016444e-05 +29 mux_tree_tapbuf_size10_0_sram[1]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.639319e-05 +30 mux_tree_tapbuf_size10_0_sram[1]:23 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.016444e-05 +31 mux_tree_tapbuf_size10_0_sram[1]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.639319e-05 +32 mux_tree_tapbuf_size10_0_sram[1]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.463783e-05 +33 mux_tree_tapbuf_size10_0_sram[1]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.463783e-05 +34 mux_tree_tapbuf_size10_0_sram[1]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.349811e-05 +35 mux_tree_tapbuf_size10_0_sram[1]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.005225e-05 +36 mux_tree_tapbuf_size10_0_sram[1]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.005225e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:26 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:16 mux_top_track_8\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +3 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:15 0.002680804 +4 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.00341 +5 mux_tree_tapbuf_size10_0_sram[1]:14 mux_tree_tapbuf_size10_0_sram[1]:13 0.00021385 +6 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.0001634616 +7 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.00341 +8 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 9.51087e-05 +9 mux_tree_tapbuf_size10_0_sram[1]:11 mux_tree_tapbuf_size10_0_sram[1]:10 0.0045 +10 mux_tree_tapbuf_size10_0_sram[1]:9 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size10_0_sram[1]:18 mux_top_track_8\/mux_l2_in_3_:S 0.152 +12 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.003104911 +13 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0045 +14 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:17 0.001821429 +15 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0045 +16 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.007589286 +17 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:8 0.002084821 +18 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 0.001020089 +19 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.005765625 +20 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0045 +21 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:20 0.004553571 +22 mux_tree_tapbuf_size10_0_sram[1]:21 mux_top_track_8\/mux_l2_in_1_:S 0.152 +23 mux_tree_tapbuf_size10_0_sram[1]:6 mux_top_track_8\/mux_l2_in_0_:S 0.152 +24 mux_tree_tapbuf_size10_0_sram[1]:7 mux_tree_tapbuf_size10_0_sram[1]:6 0.002069197 +25 mux_tree_tapbuf_size10_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:7 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.01421391 //LENGTH 106.955 LUMPCC 0.001731053 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 107.945 50.320 +*I mux_top_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 67.720 50.320 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 57.215 47.940 +*I mux_top_track_16\/mux_l1_in_2_:S I *L 0.00357 *C 55.300 57.800 +*I mux_top_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 52.800 90.780 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 52.838 90.780 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 55.200 90.780 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 55.200 91.120 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 55.200 91.075 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 55.300 57.800 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 55.200 58.140 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 55.200 58.140 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 55.200 47.985 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 55.245 47.940 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 57.215 47.940 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 59.340 47.940 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 59.340 48.280 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 67.683 50.320 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 66.745 50.320 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 66.700 50.275 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 66.700 48.325 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 66.700 48.280 +*N mux_tree_tapbuf_size10_1_sram[0]:22 *C 107.595 48.280 +*N mux_tree_tapbuf_size10_1_sram[0]:23 *C 107.640 48.325 +*N mux_tree_tapbuf_size10_1_sram[0]:24 *C 107.640 50.275 +*N mux_tree_tapbuf_size10_1_sram[0]:25 *C 107.640 50.320 +*N mux_tree_tapbuf_size10_1_sram[0]:26 *C 107.945 50.320 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_16\/mux_l1_in_1_:S 1e-06 +2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_top_track_16\/mux_l1_in_2_:S 1e-06 +4 mux_top_track_16\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 0.0001174819 +6 mux_tree_tapbuf_size10_1_sram[0]:6 0.000148904 +7 mux_tree_tapbuf_size10_1_sram[0]:7 6.8847e-05 +8 mux_tree_tapbuf_size10_1_sram[0]:8 0.001819422 +9 mux_tree_tapbuf_size10_1_sram[0]:9 6.956451e-05 +10 mux_tree_tapbuf_size10_1_sram[0]:10 7.356184e-05 +11 mux_tree_tapbuf_size10_1_sram[0]:11 0.002384771 +12 mux_tree_tapbuf_size10_1_sram[0]:12 0.0005285197 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0001332579 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.0003056899 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0001684863 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0005597679 +17 mux_tree_tapbuf_size10_1_sram[0]:17 8.633179e-05 +18 mux_tree_tapbuf_size10_1_sram[0]:18 8.633179e-05 +19 mux_tree_tapbuf_size10_1_sram[0]:19 0.0001518588 +20 mux_tree_tapbuf_size10_1_sram[0]:20 0.0001518588 +21 mux_tree_tapbuf_size10_1_sram[0]:21 0.002911648 +22 mux_tree_tapbuf_size10_1_sram[0]:22 0.002346268 +23 mux_tree_tapbuf_size10_1_sram[0]:23 0.000125652 +24 mux_tree_tapbuf_size10_1_sram[0]:24 0.000125652 +25 mux_tree_tapbuf_size10_1_sram[0]:25 6.005738e-05 +26 mux_tree_tapbuf_size10_1_sram[0]:26 5.392262e-05 +27 mux_tree_tapbuf_size10_1_sram[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.716408e-05 +28 mux_tree_tapbuf_size10_1_sram[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.716408e-05 +29 mux_tree_tapbuf_size10_1_sram[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.791667e-05 +30 mux_tree_tapbuf_size10_1_sram[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.791667e-05 +31 mux_tree_tapbuf_size10_1_sram[0]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001250011 +32 mux_tree_tapbuf_size10_1_sram[0]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.94496e-05 +33 mux_tree_tapbuf_size10_1_sram[0]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.94496e-05 +34 mux_tree_tapbuf_size10_1_sram[0]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001250011 +35 mux_tree_tapbuf_size10_1_sram[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.609821e-06 +36 mux_tree_tapbuf_size10_1_sram[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001288886 +37 mux_tree_tapbuf_size10_1_sram[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.609821e-06 +38 mux_tree_tapbuf_size10_1_sram[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001288886 +39 mux_tree_tapbuf_size10_1_sram[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.729301e-05 +40 mux_tree_tapbuf_size10_1_sram[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.729301e-05 +41 mux_tree_tapbuf_size10_1_sram[0]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001494904 +42 mux_tree_tapbuf_size10_1_sram[0]:22 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001494904 +43 mux_tree_tapbuf_size10_1_sram[0]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.185122e-05 +44 mux_tree_tapbuf_size10_1_sram[0]:22 mux_right_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.185122e-05 +45 mux_tree_tapbuf_size10_1_sram[0]:21 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.42995e-05 +46 mux_tree_tapbuf_size10_1_sram[0]:22 mux_right_track_16/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.42995e-05 +47 mux_tree_tapbuf_size10_1_sram[0]:21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.05626e-05 +48 mux_tree_tapbuf_size10_1_sram[0]:22 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.05626e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:26 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:17 mux_top_track_16\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.0008370536 +3 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 0.0045 +4 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.0045 +5 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:16 0.006571429 +6 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.001741071 +7 mux_tree_tapbuf_size10_1_sram[0]:7 mux_tree_tapbuf_size10_1_sram[0]:6 0.0003035715 +8 mux_tree_tapbuf_size10_1_sram[0]:8 mux_tree_tapbuf_size10_1_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size10_1_sram[0]:5 mux_top_track_16\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size10_1_sram[0]:22 mux_tree_tapbuf_size10_1_sram[0]:21 0.0365134 +11 mux_tree_tapbuf_size10_1_sram[0]:23 mux_tree_tapbuf_size10_1_sram[0]:22 0.0045 +12 mux_tree_tapbuf_size10_1_sram[0]:25 mux_tree_tapbuf_size10_1_sram[0]:24 0.0045 +13 mux_tree_tapbuf_size10_1_sram[0]:24 mux_tree_tapbuf_size10_1_sram[0]:23 0.001741071 +14 mux_tree_tapbuf_size10_1_sram[0]:26 mux_tree_tapbuf_size10_1_sram[0]:25 0.0001657609 +15 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.0045 +16 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.009066964 +17 mux_tree_tapbuf_size10_1_sram[0]:14 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:13 0.001758929 +19 mux_tree_tapbuf_size10_1_sram[0]:10 mux_tree_tapbuf_size10_1_sram[0]:9 0.0001847826 +20 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.0045 +21 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:8 0.02940625 +22 mux_tree_tapbuf_size10_1_sram[0]:9 mux_top_track_16\/mux_l1_in_2_:S 0.152 +23 mux_tree_tapbuf_size10_1_sram[0]:6 mux_tree_tapbuf_size10_1_sram[0]:5 0.002109375 +24 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.001897322 +25 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:15 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_6_sram[0] 0.006911735 //LENGTH 52.620 LUMPCC 0.0008369107 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.985 14.960 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 77.180 30.600 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 88.035 31.620 +*I mux_bottom_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 90.060 36.380 +*I mux_bottom_track_9\/mux_l1_in_2_:S I *L 0.00357 *C 93.480 34.680 +*N mux_tree_tapbuf_size10_6_sram[0]:5 *C 93.480 34.680 +*N mux_tree_tapbuf_size10_6_sram[0]:6 *C 93.380 34.340 +*N mux_tree_tapbuf_size10_6_sram[0]:7 *C 90.045 36.380 +*N mux_tree_tapbuf_size10_6_sram[0]:8 *C 89.723 36.380 +*N mux_tree_tapbuf_size10_6_sram[0]:9 *C 89.700 36.335 +*N mux_tree_tapbuf_size10_6_sram[0]:10 *C 89.700 34.385 +*N mux_tree_tapbuf_size10_6_sram[0]:11 *C 89.700 34.340 +*N mux_tree_tapbuf_size10_6_sram[0]:12 *C 88.365 34.340 +*N mux_tree_tapbuf_size10_6_sram[0]:13 *C 88.320 34.295 +*N mux_tree_tapbuf_size10_6_sram[0]:14 *C 88.320 31.665 +*N mux_tree_tapbuf_size10_6_sram[0]:15 *C 88.320 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:16 *C 87.998 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:17 *C 81.925 31.620 +*N mux_tree_tapbuf_size10_6_sram[0]:18 *C 81.880 31.575 +*N mux_tree_tapbuf_size10_6_sram[0]:19 *C 77.218 30.600 +*N mux_tree_tapbuf_size10_6_sram[0]:20 *C 81.835 30.600 +*N mux_tree_tapbuf_size10_6_sram[0]:21 *C 81.880 30.600 +*N mux_tree_tapbuf_size10_6_sram[0]:22 *C 81.880 15.018 +*N mux_tree_tapbuf_size10_6_sram[0]:23 *C 81.873 14.960 +*N mux_tree_tapbuf_size10_6_sram[0]:24 *C 71.767 14.960 +*N mux_tree_tapbuf_size10_6_sram[0]:25 *C 71.760 14.960 +*N mux_tree_tapbuf_size10_6_sram[0]:26 *C 71.805 14.960 +*N mux_tree_tapbuf_size10_6_sram[0]:27 *C 72.948 14.960 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_9\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_9\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_6_sram[0]:5 5.591035e-05 +6 mux_tree_tapbuf_size10_6_sram[0]:6 0.0002487632 +7 mux_tree_tapbuf_size10_6_sram[0]:7 5.919533e-05 +8 mux_tree_tapbuf_size10_6_sram[0]:8 5.919533e-05 +9 mux_tree_tapbuf_size10_6_sram[0]:9 0.0001320022 +10 mux_tree_tapbuf_size10_6_sram[0]:10 0.0001320022 +11 mux_tree_tapbuf_size10_6_sram[0]:11 0.0003485086 +12 mux_tree_tapbuf_size10_6_sram[0]:12 9.448253e-05 +13 mux_tree_tapbuf_size10_6_sram[0]:13 0.0001668858 +14 mux_tree_tapbuf_size10_6_sram[0]:14 0.0001668858 +15 mux_tree_tapbuf_size10_6_sram[0]:15 5.789992e-05 +16 mux_tree_tapbuf_size10_6_sram[0]:16 0.0004460021 +17 mux_tree_tapbuf_size10_6_sram[0]:17 0.0004212616 +18 mux_tree_tapbuf_size10_6_sram[0]:18 4.724233e-05 +19 mux_tree_tapbuf_size10_6_sram[0]:19 0.0002340832 +20 mux_tree_tapbuf_size10_6_sram[0]:20 0.0002340832 +21 mux_tree_tapbuf_size10_6_sram[0]:21 0.0007845331 +22 mux_tree_tapbuf_size10_6_sram[0]:22 0.0007017785 +23 mux_tree_tapbuf_size10_6_sram[0]:23 0.0007267621 +24 mux_tree_tapbuf_size10_6_sram[0]:24 0.0007267621 +25 mux_tree_tapbuf_size10_6_sram[0]:25 3.590805e-05 +26 mux_tree_tapbuf_size10_6_sram[0]:26 9.483795e-05 +27 mux_tree_tapbuf_size10_6_sram[0]:27 9.483795e-05 +28 mux_tree_tapbuf_size10_6_sram[0]:18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.855601e-05 +29 mux_tree_tapbuf_size10_6_sram[0]:22 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001861749 +30 mux_tree_tapbuf_size10_6_sram[0]:21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.855601e-05 +31 mux_tree_tapbuf_size10_6_sram[0]:21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001861749 +32 mux_tree_tapbuf_size10_6_sram[0]:17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 1.944345e-05 +33 mux_tree_tapbuf_size10_6_sram[0]:18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.879414e-06 +34 mux_tree_tapbuf_size10_6_sram[0]:22 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.810542e-05 +35 mux_tree_tapbuf_size10_6_sram[0]:16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 1.944345e-05 +36 mux_tree_tapbuf_size10_6_sram[0]:20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001512962 +37 mux_tree_tapbuf_size10_6_sram[0]:21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.879414e-06 +38 mux_tree_tapbuf_size10_6_sram[0]:21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.810542e-05 +39 mux_tree_tapbuf_size10_6_sram[0]:19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001512962 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_6_sram[0]:27 0.152 +1 mux_tree_tapbuf_size10_6_sram[0]:17 mux_tree_tapbuf_size10_6_sram[0]:16 0.005421875 +2 mux_tree_tapbuf_size10_6_sram[0]:18 mux_tree_tapbuf_size10_6_sram[0]:17 0.0045 +3 mux_tree_tapbuf_size10_6_sram[0]:15 mux_tree_tapbuf_size10_6_sram[0]:14 0.0045 +4 mux_tree_tapbuf_size10_6_sram[0]:14 mux_tree_tapbuf_size10_6_sram[0]:13 0.002348214 +5 mux_tree_tapbuf_size10_6_sram[0]:12 mux_tree_tapbuf_size10_6_sram[0]:11 0.001191964 +6 mux_tree_tapbuf_size10_6_sram[0]:13 mux_tree_tapbuf_size10_6_sram[0]:12 0.0045 +7 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:10 0.0045 +8 mux_tree_tapbuf_size10_6_sram[0]:11 mux_tree_tapbuf_size10_6_sram[0]:6 0.003285714 +9 mux_tree_tapbuf_size10_6_sram[0]:10 mux_tree_tapbuf_size10_6_sram[0]:9 0.001741071 +10 mux_tree_tapbuf_size10_6_sram[0]:8 mux_tree_tapbuf_size10_6_sram[0]:7 0.0001752718 +11 mux_tree_tapbuf_size10_6_sram[0]:9 mux_tree_tapbuf_size10_6_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size10_6_sram[0]:7 mux_bottom_track_9\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size10_6_sram[0]:27 mux_tree_tapbuf_size10_6_sram[0]:26 0.001020089 +14 mux_tree_tapbuf_size10_6_sram[0]:26 mux_tree_tapbuf_size10_6_sram[0]:25 0.0045 +15 mux_tree_tapbuf_size10_6_sram[0]:25 mux_tree_tapbuf_size10_6_sram[0]:24 0.00341 +16 mux_tree_tapbuf_size10_6_sram[0]:24 mux_tree_tapbuf_size10_6_sram[0]:23 0.001583117 +17 mux_tree_tapbuf_size10_6_sram[0]:22 mux_tree_tapbuf_size10_6_sram[0]:21 0.01391295 +18 mux_tree_tapbuf_size10_6_sram[0]:23 mux_tree_tapbuf_size10_6_sram[0]:22 0.00341 +19 mux_tree_tapbuf_size10_6_sram[0]:16 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size10_6_sram[0]:16 mux_tree_tapbuf_size10_6_sram[0]:15 0.0001752718 +21 mux_tree_tapbuf_size10_6_sram[0]:5 mux_bottom_track_9\/mux_l1_in_2_:S 0.152 +22 mux_tree_tapbuf_size10_6_sram[0]:20 mux_tree_tapbuf_size10_6_sram[0]:19 0.004122768 +23 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:20 0.0045 +24 mux_tree_tapbuf_size10_6_sram[0]:21 mux_tree_tapbuf_size10_6_sram[0]:18 0.0008705357 +25 mux_tree_tapbuf_size10_6_sram[0]:19 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +26 mux_tree_tapbuf_size10_6_sram[0]:6 mux_tree_tapbuf_size10_6_sram[0]:5 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_11_ccff_tail[0] 0.0005171538 //LENGTH 3.620 LUMPCC 7.961949e-05 DR + +*CONN +*I mem_left_track_25\/FTB_24__75:X O *L 0 *C 8.965 61.540 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.915 64.260 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:2 *C 8.915 64.260 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:3 *C 8.740 64.260 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 *C 8.740 64.215 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 *C 8.740 61.585 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:6 *C 8.740 61.540 +*N mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:7 *C 8.965 61.540 + +*CAP +0 mem_left_track_25\/FTB_24__75:X 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:2 4.916968e-05 +3 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:3 5.333209e-05 +4 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 0.0001172471 +5 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 0.0001172471 +6 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:6 5.335495e-05 +7 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:7 4.518354e-05 +8 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.980974e-05 +9 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.980974e-05 + +*RES +0 mem_left_track_25\/FTB_24__75:X mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:2 9.510871e-05 +3 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_11_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_6_ccff_tail[0] 0.0006141348 //LENGTH 4.480 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/FTB_19__70:X O *L 0 *C 103.725 28.900 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 102.755 31.620 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 *C 102.755 31.620 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 *C 103.455 31.620 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 *C 103.500 31.575 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 *C 103.500 28.945 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 *C 103.500 28.900 +*N mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 *C 103.725 28.900 + +*CAP +0 mem_bottom_track_9\/FTB_19__70:X 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.0001050337 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 7.247412e-05 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.0001655432 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0001655432 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 5.051152e-05 +7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 5.302903e-05 + +*RES +0 mem_bottom_track_9\/FTB_19__70:X mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:2 0.000625 +3 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_6_ccff_tail[0]:6 0.0001222826 + +*END + +*D_NET mux_tree_tapbuf_size12_1_sram[0] 0.009433771 //LENGTH 66.510 LUMPCC 0.0009840496 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 70.010 109.480 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 63.195 102.340 +*I mux_top_track_2\/mux_l1_in_3_:S I *L 0.00357 *C 64.060 90.780 +*I mux_top_track_2\/mux_l1_in_4_:S I *L 0.00357 *C 61.280 85.000 +*I mux_top_track_2\/mux_l1_in_2_:S I *L 0.00357 *C 68.640 90.440 +*I mux_top_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 46.360 107.440 +*I mux_top_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 54.160 107.100 +*N mux_tree_tapbuf_size12_1_sram[0]:7 *C 54.145 107.100 +*N mux_tree_tapbuf_size12_1_sram[0]:8 *C 46.398 107.440 +*N mux_tree_tapbuf_size12_1_sram[0]:9 *C 48.300 107.440 +*N mux_tree_tapbuf_size12_1_sram[0]:10 *C 48.300 107.100 +*N mux_tree_tapbuf_size12_1_sram[0]:11 *C 53.843 107.100 +*N mux_tree_tapbuf_size12_1_sram[0]:12 *C 53.820 107.055 +*N mux_tree_tapbuf_size12_1_sram[0]:13 *C 53.820 105.458 +*N mux_tree_tapbuf_size12_1_sram[0]:14 *C 53.828 105.400 +*N mux_tree_tapbuf_size12_1_sram[0]:15 *C 57.040 105.400 +*N mux_tree_tapbuf_size12_1_sram[0]:16 *C 57.040 104.040 +*N mux_tree_tapbuf_size12_1_sram[0]:17 *C 68.603 90.440 +*N mux_tree_tapbuf_size12_1_sram[0]:18 *C 68.080 90.440 +*N mux_tree_tapbuf_size12_1_sram[0]:19 *C 68.080 90.780 +*N mux_tree_tapbuf_size12_1_sram[0]:20 *C 61.318 85.000 +*N mux_tree_tapbuf_size12_1_sram[0]:21 *C 63.435 85.000 +*N mux_tree_tapbuf_size12_1_sram[0]:22 *C 63.480 85.045 +*N mux_tree_tapbuf_size12_1_sram[0]:23 *C 63.480 90.735 +*N mux_tree_tapbuf_size12_1_sram[0]:24 *C 63.525 90.780 +*N mux_tree_tapbuf_size12_1_sram[0]:25 *C 64.075 90.780 +*N mux_tree_tapbuf_size12_1_sram[0]:26 *C 64.445 90.780 +*N mux_tree_tapbuf_size12_1_sram[0]:27 *C 64.400 90.825 +*N mux_tree_tapbuf_size12_1_sram[0]:28 *C 63.233 102.340 +*N mux_tree_tapbuf_size12_1_sram[0]:29 *C 64.400 102.340 +*N mux_tree_tapbuf_size12_1_sram[0]:30 *C 64.400 102.680 +*N mux_tree_tapbuf_size12_1_sram[0]:31 *C 64.400 102.680 +*N mux_tree_tapbuf_size12_1_sram[0]:32 *C 64.400 103.983 +*N mux_tree_tapbuf_size12_1_sram[0]:33 *C 64.400 104.040 +*N mux_tree_tapbuf_size12_1_sram[0]:34 *C 68.073 104.040 +*N mux_tree_tapbuf_size12_1_sram[0]:35 *C 68.080 104.098 +*N mux_tree_tapbuf_size12_1_sram[0]:36 *C 68.080 109.435 +*N mux_tree_tapbuf_size12_1_sram[0]:37 *C 68.125 109.480 +*N mux_tree_tapbuf_size12_1_sram[0]:38 *C 69.972 109.480 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_2\/mux_l1_in_3_:S 1e-06 +3 mux_top_track_2\/mux_l1_in_4_:S 1e-06 +4 mux_top_track_2\/mux_l1_in_2_:S 1e-06 +5 mux_top_track_2\/mux_l1_in_1_:S 1e-06 +6 mux_top_track_2\/mux_l1_in_0_:S 1e-06 +7 mux_tree_tapbuf_size12_1_sram[0]:7 6.499457e-05 +8 mux_tree_tapbuf_size12_1_sram[0]:8 0.0001442146 +9 mux_tree_tapbuf_size12_1_sram[0]:9 0.0001700284 +10 mux_tree_tapbuf_size12_1_sram[0]:10 0.0004911853 +11 mux_tree_tapbuf_size12_1_sram[0]:11 0.0005303661 +12 mux_tree_tapbuf_size12_1_sram[0]:12 0.0001368612 +13 mux_tree_tapbuf_size12_1_sram[0]:13 0.0001368612 +14 mux_tree_tapbuf_size12_1_sram[0]:14 0.0002566669 +15 mux_tree_tapbuf_size12_1_sram[0]:15 0.0003735702 +16 mux_tree_tapbuf_size12_1_sram[0]:16 0.0006293112 +17 mux_tree_tapbuf_size12_1_sram[0]:17 5.365565e-05 +18 mux_tree_tapbuf_size12_1_sram[0]:18 8.308339e-05 +19 mux_tree_tapbuf_size12_1_sram[0]:19 0.0003293475 +20 mux_tree_tapbuf_size12_1_sram[0]:20 0.0001817501 +21 mux_tree_tapbuf_size12_1_sram[0]:21 0.0001817501 +22 mux_tree_tapbuf_size12_1_sram[0]:22 0.0002324106 +23 mux_tree_tapbuf_size12_1_sram[0]:23 0.0002324106 +24 mux_tree_tapbuf_size12_1_sram[0]:24 7.00554e-05 +25 mux_tree_tapbuf_size12_1_sram[0]:25 0.0001309436 +26 mux_tree_tapbuf_size12_1_sram[0]:26 0.0003608079 +27 mux_tree_tapbuf_size12_1_sram[0]:27 0.000544849 +28 mux_tree_tapbuf_size12_1_sram[0]:28 9.408527e-05 +29 mux_tree_tapbuf_size12_1_sram[0]:29 0.0001245202 +30 mux_tree_tapbuf_size12_1_sram[0]:30 6.615833e-05 +31 mux_tree_tapbuf_size12_1_sram[0]:31 0.0006433223 +32 mux_tree_tapbuf_size12_1_sram[0]:32 6.546519e-05 +33 mux_tree_tapbuf_size12_1_sram[0]:33 0.0007782337 +34 mux_tree_tapbuf_size12_1_sram[0]:34 0.0002658259 +35 mux_tree_tapbuf_size12_1_sram[0]:35 0.0003506197 +36 mux_tree_tapbuf_size12_1_sram[0]:36 0.0003506197 +37 mux_tree_tapbuf_size12_1_sram[0]:37 0.0001843743 +38 mux_tree_tapbuf_size12_1_sram[0]:38 0.0001843743 +39 mux_tree_tapbuf_size12_1_sram[0]:27 chany_bottom_in[5]:23 0.0002990881 +40 mux_tree_tapbuf_size12_1_sram[0]:32 chany_bottom_in[5]:13 3.602016e-05 +41 mux_tree_tapbuf_size12_1_sram[0]:31 chany_bottom_in[5]:13 0.0002990881 +42 mux_tree_tapbuf_size12_1_sram[0]:31 chany_bottom_in[5]:23 3.602016e-05 +43 mux_tree_tapbuf_size12_1_sram[0]:23 chany_bottom_in[5]:13 0.0001569165 +44 mux_tree_tapbuf_size12_1_sram[0]:22 chany_bottom_in[5]:23 0.0001569165 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size12_1_sram[0]:38 0.152 +1 mux_tree_tapbuf_size12_1_sram[0]:25 mux_top_track_2\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size12_1_sram[0]:25 mux_tree_tapbuf_size12_1_sram[0]:24 0.0004910714 +3 mux_tree_tapbuf_size12_1_sram[0]:26 mux_tree_tapbuf_size12_1_sram[0]:25 0.000201087 +4 mux_tree_tapbuf_size12_1_sram[0]:26 mux_tree_tapbuf_size12_1_sram[0]:19 0.003245536 +5 mux_tree_tapbuf_size12_1_sram[0]:27 mux_tree_tapbuf_size12_1_sram[0]:26 0.0045 +6 mux_tree_tapbuf_size12_1_sram[0]:32 mux_tree_tapbuf_size12_1_sram[0]:31 0.001162946 +7 mux_tree_tapbuf_size12_1_sram[0]:33 mux_tree_tapbuf_size12_1_sram[0]:32 0.00341 +8 mux_tree_tapbuf_size12_1_sram[0]:33 mux_tree_tapbuf_size12_1_sram[0]:16 0.001153067 +9 mux_tree_tapbuf_size12_1_sram[0]:17 mux_top_track_2\/mux_l1_in_2_:S 0.152 +10 mux_tree_tapbuf_size12_1_sram[0]:30 mux_tree_tapbuf_size12_1_sram[0]:29 0.0003035715 +11 mux_tree_tapbuf_size12_1_sram[0]:31 mux_tree_tapbuf_size12_1_sram[0]:30 0.0045 +12 mux_tree_tapbuf_size12_1_sram[0]:31 mux_tree_tapbuf_size12_1_sram[0]:27 0.01058482 +13 mux_tree_tapbuf_size12_1_sram[0]:28 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size12_1_sram[0]:7 mux_top_track_2\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size12_1_sram[0]:24 mux_tree_tapbuf_size12_1_sram[0]:23 0.0045 +16 mux_tree_tapbuf_size12_1_sram[0]:23 mux_tree_tapbuf_size12_1_sram[0]:22 0.005080357 +17 mux_tree_tapbuf_size12_1_sram[0]:21 mux_tree_tapbuf_size12_1_sram[0]:20 0.001890625 +18 mux_tree_tapbuf_size12_1_sram[0]:22 mux_tree_tapbuf_size12_1_sram[0]:21 0.0045 +19 mux_tree_tapbuf_size12_1_sram[0]:20 mux_top_track_2\/mux_l1_in_4_:S 0.152 +20 mux_tree_tapbuf_size12_1_sram[0]:13 mux_tree_tapbuf_size12_1_sram[0]:12 0.001426339 +21 mux_tree_tapbuf_size12_1_sram[0]:14 mux_tree_tapbuf_size12_1_sram[0]:13 0.00341 +22 mux_tree_tapbuf_size12_1_sram[0]:11 mux_tree_tapbuf_size12_1_sram[0]:10 0.004948661 +23 mux_tree_tapbuf_size12_1_sram[0]:11 mux_tree_tapbuf_size12_1_sram[0]:7 0.0001644022 +24 mux_tree_tapbuf_size12_1_sram[0]:12 mux_tree_tapbuf_size12_1_sram[0]:11 0.0045 +25 mux_tree_tapbuf_size12_1_sram[0]:8 mux_top_track_2\/mux_l1_in_1_:S 0.152 +26 mux_tree_tapbuf_size12_1_sram[0]:38 mux_tree_tapbuf_size12_1_sram[0]:37 0.001649554 +27 mux_tree_tapbuf_size12_1_sram[0]:37 mux_tree_tapbuf_size12_1_sram[0]:36 0.0045 +28 mux_tree_tapbuf_size12_1_sram[0]:36 mux_tree_tapbuf_size12_1_sram[0]:35 0.004765625 +29 mux_tree_tapbuf_size12_1_sram[0]:35 mux_tree_tapbuf_size12_1_sram[0]:34 0.00341 +30 mux_tree_tapbuf_size12_1_sram[0]:34 mux_tree_tapbuf_size12_1_sram[0]:33 0.0005753583 +31 mux_tree_tapbuf_size12_1_sram[0]:9 mux_tree_tapbuf_size12_1_sram[0]:8 0.001698661 +32 mux_tree_tapbuf_size12_1_sram[0]:10 mux_tree_tapbuf_size12_1_sram[0]:9 0.0003035715 +33 mux_tree_tapbuf_size12_1_sram[0]:29 mux_tree_tapbuf_size12_1_sram[0]:28 0.001042411 +34 mux_tree_tapbuf_size12_1_sram[0]:19 mux_tree_tapbuf_size12_1_sram[0]:18 0.0003035714 +35 mux_tree_tapbuf_size12_1_sram[0]:18 mux_tree_tapbuf_size12_1_sram[0]:17 0.0004665178 +36 mux_tree_tapbuf_size12_1_sram[0]:15 mux_tree_tapbuf_size12_1_sram[0]:14 0.0005032916 +37 mux_tree_tapbuf_size12_1_sram[0]:16 mux_tree_tapbuf_size12_1_sram[0]:15 0.0002130666 + +*END + +*D_NET mux_tree_tapbuf_size12_5_sram[2] 0.003051186 //LENGTH 23.290 LUMPCC 0.0005845492 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 64.245 15.300 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 56.305 11.900 +*I mux_bottom_track_3\/mux_l3_in_1_:S I *L 0.00357 *C 60.620 17.680 +*I mux_bottom_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 63.580 19.720 +*N mux_tree_tapbuf_size12_5_sram[2]:4 *C 63.480 19.720 +*N mux_tree_tapbuf_size12_5_sram[2]:5 *C 63.480 19.675 +*N mux_tree_tapbuf_size12_5_sram[2]:6 *C 60.620 17.680 +*N mux_tree_tapbuf_size12_5_sram[2]:7 *C 60.655 18.015 +*N mux_tree_tapbuf_size12_5_sram[2]:8 *C 56.305 11.900 +*N mux_tree_tapbuf_size12_5_sram[2]:9 *C 56.305 11.560 +*N mux_tree_tapbuf_size12_5_sram[2]:10 *C 62.515 11.560 +*N mux_tree_tapbuf_size12_5_sram[2]:11 *C 62.560 11.605 +*N mux_tree_tapbuf_size12_5_sram[2]:12 *C 62.560 17.975 +*N mux_tree_tapbuf_size12_5_sram[2]:13 *C 62.560 18.020 +*N mux_tree_tapbuf_size12_5_sram[2]:14 *C 63.435 18.020 +*N mux_tree_tapbuf_size12_5_sram[2]:15 *C 63.480 18.020 +*N mux_tree_tapbuf_size12_5_sram[2]:16 *C 63.480 15.345 +*N mux_tree_tapbuf_size12_5_sram[2]:17 *C 63.525 15.300 +*N mux_tree_tapbuf_size12_5_sram[2]:18 *C 64.207 15.300 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_track_3\/mux_l3_in_1_:S 1e-06 +3 mux_bottom_track_3\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size12_5_sram[2]:4 3.36448e-05 +5 mux_tree_tapbuf_size12_5_sram[2]:5 6.170446e-05 +6 mux_tree_tapbuf_size12_5_sram[2]:6 5.619611e-05 +7 mux_tree_tapbuf_size12_5_sram[2]:7 0.0001466221 +8 mux_tree_tapbuf_size12_5_sram[2]:8 5.637174e-05 +9 mux_tree_tapbuf_size12_5_sram[2]:9 0.0004767546 +10 mux_tree_tapbuf_size12_5_sram[2]:10 0.0004489975 +11 mux_tree_tapbuf_size12_5_sram[2]:11 0.0002334949 +12 mux_tree_tapbuf_size12_5_sram[2]:12 0.0002334949 +13 mux_tree_tapbuf_size12_5_sram[2]:13 0.0002091863 +14 mux_tree_tapbuf_size12_5_sram[2]:14 6.070169e-05 +15 mux_tree_tapbuf_size12_5_sram[2]:15 0.0001990192 +16 mux_tree_tapbuf_size12_5_sram[2]:16 0.0001042026 +17 mux_tree_tapbuf_size12_5_sram[2]:17 7.112308e-05 +18 mux_tree_tapbuf_size12_5_sram[2]:18 7.112308e-05 +19 mux_tree_tapbuf_size12_5_sram[2]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:6 2.516158e-06 +20 mux_tree_tapbuf_size12_5_sram[2]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:5 6.722426e-05 +21 mux_tree_tapbuf_size12_5_sram[2]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:4 6.722426e-05 +22 mux_tree_tapbuf_size12_5_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_10_X[0]:7 2.516158e-06 +23 mux_tree_tapbuf_size12_5_sram[2]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 7.669109e-05 +24 mux_tree_tapbuf_size12_5_sram[2]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 7.669109e-05 +25 mux_tree_tapbuf_size12_5_sram[2]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.7719e-05 +26 mux_tree_tapbuf_size12_5_sram[2]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.7719e-05 +27 mux_tree_tapbuf_size12_5_sram[2]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.266714e-05 +28 mux_tree_tapbuf_size12_5_sram[2]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:4 5.456927e-06 +29 mux_tree_tapbuf_size12_5_sram[2]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:3 5.456927e-06 +30 mux_tree_tapbuf_size12_5_sram[2]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_9_X[0]:5 9.266714e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size12_5_sram[2]:18 0.152 +1 mux_tree_tapbuf_size12_5_sram[2]:17 mux_tree_tapbuf_size12_5_sram[2]:16 0.0045 +2 mux_tree_tapbuf_size12_5_sram[2]:16 mux_tree_tapbuf_size12_5_sram[2]:15 0.002388393 +3 mux_tree_tapbuf_size12_5_sram[2]:18 mux_tree_tapbuf_size12_5_sram[2]:17 0.000609375 +4 mux_tree_tapbuf_size12_5_sram[2]:14 mux_tree_tapbuf_size12_5_sram[2]:13 0.00078125 +5 mux_tree_tapbuf_size12_5_sram[2]:15 mux_tree_tapbuf_size12_5_sram[2]:14 0.0045 +6 mux_tree_tapbuf_size12_5_sram[2]:15 mux_tree_tapbuf_size12_5_sram[2]:5 0.001477679 +7 mux_tree_tapbuf_size12_5_sram[2]:4 mux_bottom_track_3\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size12_5_sram[2]:5 mux_tree_tapbuf_size12_5_sram[2]:4 0.0045 +9 mux_tree_tapbuf_size12_5_sram[2]:13 mux_tree_tapbuf_size12_5_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size12_5_sram[2]:13 mux_tree_tapbuf_size12_5_sram[2]:7 0.001700893 +11 mux_tree_tapbuf_size12_5_sram[2]:12 mux_tree_tapbuf_size12_5_sram[2]:11 0.0056875 +12 mux_tree_tapbuf_size12_5_sram[2]:10 mux_tree_tapbuf_size12_5_sram[2]:9 0.005544643 +13 mux_tree_tapbuf_size12_5_sram[2]:11 mux_tree_tapbuf_size12_5_sram[2]:10 0.0045 +14 mux_tree_tapbuf_size12_5_sram[2]:8 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +15 mux_tree_tapbuf_size12_5_sram[2]:6 mux_bottom_track_3\/mux_l3_in_1_:S 0.152 +16 mux_tree_tapbuf_size12_5_sram[2]:9 mux_tree_tapbuf_size12_5_sram[2]:8 0.0003035715 +17 mux_tree_tapbuf_size12_5_sram[2]:7 mux_tree_tapbuf_size12_5_sram[2]:6 0.0001947675 + +*END + +*D_NET mux_tree_tapbuf_size12_7_sram[3] 0.001698779 //LENGTH 15.235 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 38.485 102.340 +*I mem_left_track_3\/FTB_8__59:A I *L 0.001746 *C 35.880 99.280 +*I mux_left_track_3\/mux_l4_in_0_:S I *L 0.00357 *C 30.940 96.220 +*N mux_tree_tapbuf_size12_7_sram[3]:3 *C 30.978 96.220 +*N mux_tree_tapbuf_size12_7_sram[3]:4 *C 32.155 96.220 +*N mux_tree_tapbuf_size12_7_sram[3]:5 *C 32.200 96.265 +*N mux_tree_tapbuf_size12_7_sram[3]:6 *C 32.200 99.235 +*N mux_tree_tapbuf_size12_7_sram[3]:7 *C 32.245 99.280 +*N mux_tree_tapbuf_size12_7_sram[3]:8 *C 35.843 99.280 +*N mux_tree_tapbuf_size12_7_sram[3]:9 *C 35.880 99.325 +*N mux_tree_tapbuf_size12_7_sram[3]:10 *C 35.880 102.295 +*N mux_tree_tapbuf_size12_7_sram[3]:11 *C 35.925 102.340 +*N mux_tree_tapbuf_size12_7_sram[3]:12 *C 38.448 102.340 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_left_track_3\/FTB_8__59:A 1e-06 +2 mux_left_track_3\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size12_7_sram[3]:3 0.0001214995 +4 mux_tree_tapbuf_size12_7_sram[3]:4 0.0001214995 +5 mux_tree_tapbuf_size12_7_sram[3]:5 0.0001852724 +6 mux_tree_tapbuf_size12_7_sram[3]:6 0.0001852724 +7 mux_tree_tapbuf_size12_7_sram[3]:7 0.0002155812 +8 mux_tree_tapbuf_size12_7_sram[3]:8 0.0002155812 +9 mux_tree_tapbuf_size12_7_sram[3]:9 0.0001613043 +10 mux_tree_tapbuf_size12_7_sram[3]:10 0.0001613043 +11 mux_tree_tapbuf_size12_7_sram[3]:11 0.0001642322 +12 mux_tree_tapbuf_size12_7_sram[3]:12 0.0001642322 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size12_7_sram[3]:12 0.152 +1 mux_tree_tapbuf_size12_7_sram[3]:3 mux_left_track_3\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size12_7_sram[3]:4 mux_tree_tapbuf_size12_7_sram[3]:3 0.001051339 +3 mux_tree_tapbuf_size12_7_sram[3]:5 mux_tree_tapbuf_size12_7_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size12_7_sram[3]:7 mux_tree_tapbuf_size12_7_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size12_7_sram[3]:6 mux_tree_tapbuf_size12_7_sram[3]:5 0.002651786 +6 mux_tree_tapbuf_size12_7_sram[3]:8 mem_left_track_3\/FTB_8__59:A 0.152 +7 mux_tree_tapbuf_size12_7_sram[3]:8 mux_tree_tapbuf_size12_7_sram[3]:7 0.003212054 +8 mux_tree_tapbuf_size12_7_sram[3]:9 mux_tree_tapbuf_size12_7_sram[3]:8 0.0045 +9 mux_tree_tapbuf_size12_7_sram[3]:11 mux_tree_tapbuf_size12_7_sram[3]:10 0.0045 +10 mux_tree_tapbuf_size12_7_sram[3]:10 mux_tree_tapbuf_size12_7_sram[3]:9 0.002651786 +11 mux_tree_tapbuf_size12_7_sram[3]:12 mux_tree_tapbuf_size12_7_sram[3]:11 0.002252232 + +*END + +*D_NET mux_tree_tapbuf_size16_0_sram[0] 0.002555026 //LENGTH 20.975 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 48.145 124.100 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.275 120.700 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 38.740 126.775 +*N mux_tree_tapbuf_size16_0_sram[0]:3 *C 38.740 126.775 +*N mux_tree_tapbuf_size16_0_sram[0]:4 *C 38.595 126.410 +*N mux_tree_tapbuf_size16_0_sram[0]:5 *C 38.710 126.550 +*N mux_tree_tapbuf_size16_0_sram[0]:6 *C 39.238 120.700 +*N mux_tree_tapbuf_size16_0_sram[0]:7 *C 38.685 120.700 +*N mux_tree_tapbuf_size16_0_sram[0]:8 *C 38.640 120.745 +*N mux_tree_tapbuf_size16_0_sram[0]:9 *C 38.640 126.435 +*N mux_tree_tapbuf_size16_0_sram[0]:10 *C 38.640 126.480 +*N mux_tree_tapbuf_size16_0_sram[0]:11 *C 38.640 125.800 +*N mux_tree_tapbuf_size16_0_sram[0]:12 *C 45.955 125.800 +*N mux_tree_tapbuf_size16_0_sram[0]:13 *C 46.000 125.755 +*N mux_tree_tapbuf_size16_0_sram[0]:14 *C 46.000 124.485 +*N mux_tree_tapbuf_size16_0_sram[0]:15 *C 46.045 124.440 +*N mux_tree_tapbuf_size16_0_sram[0]:16 *C 47.840 124.440 +*N mux_tree_tapbuf_size16_0_sram[0]:17 *C 47.840 124.135 +*N mux_tree_tapbuf_size16_0_sram[0]:18 *C 48.117 124.123 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size16_0_sram[0]:3 4.515425e-05 +4 mux_tree_tapbuf_size16_0_sram[0]:4 1.300906e-05 +5 mux_tree_tapbuf_size16_0_sram[0]:5 1.342168e-05 +6 mux_tree_tapbuf_size16_0_sram[0]:6 8.193315e-05 +7 mux_tree_tapbuf_size16_0_sram[0]:7 8.193315e-05 +8 mux_tree_tapbuf_size16_0_sram[0]:8 0.0003179948 +9 mux_tree_tapbuf_size16_0_sram[0]:9 0.0003179948 +10 mux_tree_tapbuf_size16_0_sram[0]:10 9.309085e-05 +11 mux_tree_tapbuf_size16_0_sram[0]:11 0.0005213239 +12 mux_tree_tapbuf_size16_0_sram[0]:12 0.0004870884 +13 mux_tree_tapbuf_size16_0_sram[0]:13 8.794412e-05 +14 mux_tree_tapbuf_size16_0_sram[0]:14 8.794412e-05 +15 mux_tree_tapbuf_size16_0_sram[0]:15 0.0001433421 +16 mux_tree_tapbuf_size16_0_sram[0]:16 0.0001693268 +17 mux_tree_tapbuf_size16_0_sram[0]:17 5.82547e-05 +18 mux_tree_tapbuf_size16_0_sram[0]:18 3.226997e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size16_0_sram[0]:18 0.152 +1 mux_tree_tapbuf_size16_0_sram[0]:18 mux_tree_tapbuf_size16_0_sram[0]:17 0.0001875 +2 mux_tree_tapbuf_size16_0_sram[0]:15 mux_tree_tapbuf_size16_0_sram[0]:14 0.0045 +3 mux_tree_tapbuf_size16_0_sram[0]:14 mux_tree_tapbuf_size16_0_sram[0]:13 0.001133929 +4 mux_tree_tapbuf_size16_0_sram[0]:12 mux_tree_tapbuf_size16_0_sram[0]:11 0.00653125 +5 mux_tree_tapbuf_size16_0_sram[0]:13 mux_tree_tapbuf_size16_0_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size16_0_sram[0]:10 mux_tree_tapbuf_size16_0_sram[0]:9 0.0045 +7 mux_tree_tapbuf_size16_0_sram[0]:10 mux_tree_tapbuf_size16_0_sram[0]:5 4.069768e-05 +8 mux_tree_tapbuf_size16_0_sram[0]:10 mux_tree_tapbuf_size16_0_sram[0]:3 0.0001715117 +9 mux_tree_tapbuf_size16_0_sram[0]:9 mux_tree_tapbuf_size16_0_sram[0]:8 0.005080357 +10 mux_tree_tapbuf_size16_0_sram[0]:7 mux_tree_tapbuf_size16_0_sram[0]:6 0.0004933036 +11 mux_tree_tapbuf_size16_0_sram[0]:8 mux_tree_tapbuf_size16_0_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size16_0_sram[0]:6 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size16_0_sram[0]:3 mux_top_track_4\/mux_l1_in_0_:S 0.152 +14 mux_tree_tapbuf_size16_0_sram[0]:11 mux_tree_tapbuf_size16_0_sram[0]:10 0.000607143 +15 mux_tree_tapbuf_size16_0_sram[0]:5 mux_tree_tapbuf_size16_0_sram[0]:4 0.0001026786 +16 mux_tree_tapbuf_size16_0_sram[0]:16 mux_tree_tapbuf_size16_0_sram[0]:15 0.001602679 +17 mux_tree_tapbuf_size16_0_sram[0]:17 mux_tree_tapbuf_size16_0_sram[0]:16 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size16_1_sram[4] 0.001208846 //LENGTH 9.640 LUMPCC 0.0003956788 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q O *L 0 *C 127.265 72.080 +*I mem_right_track_4\/FTB_10__61:A I *L 0.001746 *C 128.800 66.640 +*I mux_right_track_4\/mux_l5_in_0_:S I *L 0.00357 *C 128.700 74.120 +*N mux_tree_tapbuf_size16_1_sram[4]:3 *C 128.700 74.120 +*N mux_tree_tapbuf_size16_1_sram[4]:4 *C 128.800 74.075 +*N mux_tree_tapbuf_size16_1_sram[4]:5 *C 128.800 66.640 +*N mux_tree_tapbuf_size16_1_sram[4]:6 *C 128.800 66.685 +*N mux_tree_tapbuf_size16_1_sram[4]:7 *C 128.800 72.080 +*N mux_tree_tapbuf_size16_1_sram[4]:8 *C 128.755 72.080 +*N mux_tree_tapbuf_size16_1_sram[4]:9 *C 127.303 72.080 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q 1e-06 +1 mem_right_track_4\/FTB_10__61:A 1e-06 +2 mux_right_track_4\/mux_l5_in_0_:S 1e-06 +3 mux_tree_tapbuf_size16_1_sram[4]:3 2.901771e-05 +4 mux_tree_tapbuf_size16_1_sram[4]:4 8.98787e-05 +5 mux_tree_tapbuf_size16_1_sram[4]:5 3.402564e-05 +6 mux_tree_tapbuf_size16_1_sram[4]:6 0.0001674296 +7 mux_tree_tapbuf_size16_1_sram[4]:7 0.0002873567 +8 mux_tree_tapbuf_size16_1_sram[4]:8 0.0001012292 +9 mux_tree_tapbuf_size16_1_sram[4]:9 0.0001012292 +10 mux_tree_tapbuf_size16_1_sram[4]:6 chanx_left_in[9]:14 9.787412e-05 +11 mux_tree_tapbuf_size16_1_sram[4]:7 chanx_left_in[9]:15 9.787412e-05 +12 mux_tree_tapbuf_size16_1_sram[4]:6 ropt_net_153:5 7.151389e-05 +13 mux_tree_tapbuf_size16_1_sram[4]:4 ropt_net_153:4 2.84514e-05 +14 mux_tree_tapbuf_size16_1_sram[4]:7 ropt_net_153:4 7.151389e-05 +15 mux_tree_tapbuf_size16_1_sram[4]:7 ropt_net_153:5 2.84514e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_4_:Q mux_tree_tapbuf_size16_1_sram[4]:9 0.152 +1 mux_tree_tapbuf_size16_1_sram[4]:5 mem_right_track_4\/FTB_10__61:A 0.152 +2 mux_tree_tapbuf_size16_1_sram[4]:6 mux_tree_tapbuf_size16_1_sram[4]:5 0.0045 +3 mux_tree_tapbuf_size16_1_sram[4]:3 mux_right_track_4\/mux_l5_in_0_:S 0.152 +4 mux_tree_tapbuf_size16_1_sram[4]:4 mux_tree_tapbuf_size16_1_sram[4]:3 0.0045 +5 mux_tree_tapbuf_size16_1_sram[4]:9 mux_tree_tapbuf_size16_1_sram[4]:8 0.001296875 +6 mux_tree_tapbuf_size16_1_sram[4]:8 mux_tree_tapbuf_size16_1_sram[4]:7 0.0045 +7 mux_tree_tapbuf_size16_1_sram[4]:7 mux_tree_tapbuf_size16_1_sram[4]:6 0.004816964 +8 mux_tree_tapbuf_size16_1_sram[4]:7 mux_tree_tapbuf_size16_1_sram[4]:4 0.00178125 + +*END + +*D_NET mux_tree_tapbuf_size16_3_sram[0] 0.00322689 //LENGTH 25.805 LUMPCC 0 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 48.605 98.940 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.955 93.500 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 53.000 88.400 +*N mux_tree_tapbuf_size16_3_sram[0]:3 *C 52.963 88.400 +*N mux_tree_tapbuf_size16_3_sram[0]:4 *C 44.665 88.400 +*N mux_tree_tapbuf_size16_3_sram[0]:5 *C 44.620 88.445 +*N mux_tree_tapbuf_size16_3_sram[0]:6 *C 42.992 93.500 +*N mux_tree_tapbuf_size16_3_sram[0]:7 *C 44.575 93.500 +*N mux_tree_tapbuf_size16_3_sram[0]:8 *C 44.620 93.500 +*N mux_tree_tapbuf_size16_3_sram[0]:9 *C 44.620 98.895 +*N mux_tree_tapbuf_size16_3_sram[0]:10 *C 44.665 98.940 +*N mux_tree_tapbuf_size16_3_sram[0]:11 *C 48.568 98.940 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size16_3_sram[0]:3 0.0005937135 +4 mux_tree_tapbuf_size16_3_sram[0]:4 0.0005937135 +5 mux_tree_tapbuf_size16_3_sram[0]:5 0.0002940437 +6 mux_tree_tapbuf_size16_3_sram[0]:6 0.0001383389 +7 mux_tree_tapbuf_size16_3_sram[0]:7 0.0001383389 +8 mux_tree_tapbuf_size16_3_sram[0]:8 0.0006440217 +9 mux_tree_tapbuf_size16_3_sram[0]:9 0.0003138624 +10 mux_tree_tapbuf_size16_3_sram[0]:10 0.0002539288 +11 mux_tree_tapbuf_size16_3_sram[0]:11 0.0002539288 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size16_3_sram[0]:11 0.152 +1 mux_tree_tapbuf_size16_3_sram[0]:10 mux_tree_tapbuf_size16_3_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size16_3_sram[0]:9 mux_tree_tapbuf_size16_3_sram[0]:8 0.004816965 +3 mux_tree_tapbuf_size16_3_sram[0]:11 mux_tree_tapbuf_size16_3_sram[0]:10 0.003484375 +4 mux_tree_tapbuf_size16_3_sram[0]:3 mux_left_track_5\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size16_3_sram[0]:4 mux_tree_tapbuf_size16_3_sram[0]:3 0.007408483 +6 mux_tree_tapbuf_size16_3_sram[0]:5 mux_tree_tapbuf_size16_3_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size16_3_sram[0]:7 mux_tree_tapbuf_size16_3_sram[0]:6 0.001412947 +8 mux_tree_tapbuf_size16_3_sram[0]:8 mux_tree_tapbuf_size16_3_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size16_3_sram[0]:8 mux_tree_tapbuf_size16_3_sram[0]:5 0.004513393 +10 mux_tree_tapbuf_size16_3_sram[0]:6 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size16_mem_2_ccff_tail[0] 0.002550668 //LENGTH 18.600 LUMPCC 0.0003158192 DR + +*CONN +*I mem_bottom_track_5\/FTB_11__62:X O *L 0 *C 49.915 14.960 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.255 15.300 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:2 *C 67.218 15.300 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:3 *C 66.745 15.300 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:4 *C 66.700 15.300 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:5 *C 66.700 14.960 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 *C 66.693 14.960 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 *C 51.068 14.960 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:8 *C 51.060 14.960 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:9 *C 50.903 14.960 +*N mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:10 *C 49.953 14.960 + +*CAP +0 mem_bottom_track_5\/FTB_11__62:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:2 5.666825e-05 +3 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:3 5.666825e-05 +4 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:4 5.070591e-05 +5 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:5 5.817763e-05 +6 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 0.0008745412 +7 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 0.0008745412 +8 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:8 3.788044e-05 +9 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:9 0.000111833 +10 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:10 0.000111833 +11 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 bottom_left_grid_pin_38_[0]:9 2.194933e-05 +12 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 bottom_left_grid_pin_38_[0]:11 0.0001359603 +13 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 bottom_left_grid_pin_38_[0]:10 2.194933e-05 +14 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 bottom_left_grid_pin_38_[0]:12 0.0001359603 + +*RES +0 mem_bottom_track_5\/FTB_11__62:X mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:10 0.152 +1 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:2 0.000421875 +3 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:4 0.0001634615 +5 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:5 0.00341 +6 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 0.00341 +7 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:6 0.002447917 +8 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:9 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:8 0.0045 +9 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:10 mux_tree_tapbuf_size16_mem_2_ccff_tail[0]:9 0.0008482144 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[1] 0.002223729 //LENGTH 17.285 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 19.625 37.060 +*I mux_bottom_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 20.800 34.340 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 14.895 42.500 +*I mux_bottom_track_33\/mux_l2_in_1_:S I *L 0.00357 *C 19.420 39.735 +*N mux_tree_tapbuf_size7_2_sram[1]:4 *C 19.420 39.735 +*N mux_tree_tapbuf_size7_2_sram[1]:5 *C 14.895 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:6 *C 14.720 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:7 *C 14.720 42.455 +*N mux_tree_tapbuf_size7_2_sram[1]:8 *C 14.720 40.165 +*N mux_tree_tapbuf_size7_2_sram[1]:9 *C 14.765 40.120 +*N mux_tree_tapbuf_size7_2_sram[1]:10 *C 19.420 40.120 +*N mux_tree_tapbuf_size7_2_sram[1]:11 *C 20.195 40.120 +*N mux_tree_tapbuf_size7_2_sram[1]:12 *C 20.240 40.075 +*N mux_tree_tapbuf_size7_2_sram[1]:13 *C 20.762 34.340 +*N mux_tree_tapbuf_size7_2_sram[1]:14 *C 20.285 34.340 +*N mux_tree_tapbuf_size7_2_sram[1]:15 *C 20.240 34.385 +*N mux_tree_tapbuf_size7_2_sram[1]:16 *C 20.240 37.060 +*N mux_tree_tapbuf_size7_2_sram[1]:17 *C 20.195 37.060 +*N mux_tree_tapbuf_size7_2_sram[1]:18 *C 19.663 37.060 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_33\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_2_sram[1]:4 5.863535e-05 +5 mux_tree_tapbuf_size7_2_sram[1]:5 5.036991e-05 +6 mux_tree_tapbuf_size7_2_sram[1]:6 5.475011e-05 +7 mux_tree_tapbuf_size7_2_sram[1]:7 0.0001533586 +8 mux_tree_tapbuf_size7_2_sram[1]:8 0.0001533586 +9 mux_tree_tapbuf_size7_2_sram[1]:9 0.000313882 +10 mux_tree_tapbuf_size7_2_sram[1]:10 0.0004156866 +11 mux_tree_tapbuf_size7_2_sram[1]:11 7.172551e-05 +12 mux_tree_tapbuf_size7_2_sram[1]:12 0.0001816847 +13 mux_tree_tapbuf_size7_2_sram[1]:13 6.555821e-05 +14 mux_tree_tapbuf_size7_2_sram[1]:14 6.555821e-05 +15 mux_tree_tapbuf_size7_2_sram[1]:15 0.0001599151 +16 mux_tree_tapbuf_size7_2_sram[1]:16 0.0003722674 +17 mux_tree_tapbuf_size7_2_sram[1]:17 5.148928e-05 +18 mux_tree_tapbuf_size7_2_sram[1]:18 5.148928e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_2_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_2_sram[1]:5 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_2_sram[1]:6 mux_tree_tapbuf_size7_2_sram[1]:5 9.51087e-05 +3 mux_tree_tapbuf_size7_2_sram[1]:7 mux_tree_tapbuf_size7_2_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size7_2_sram[1]:9 mux_tree_tapbuf_size7_2_sram[1]:8 0.0045 +5 mux_tree_tapbuf_size7_2_sram[1]:8 mux_tree_tapbuf_size7_2_sram[1]:7 0.002044643 +6 mux_tree_tapbuf_size7_2_sram[1]:13 mux_bottom_track_33\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size7_2_sram[1]:14 mux_tree_tapbuf_size7_2_sram[1]:13 0.0004263393 +8 mux_tree_tapbuf_size7_2_sram[1]:15 mux_tree_tapbuf_size7_2_sram[1]:14 0.0045 +9 mux_tree_tapbuf_size7_2_sram[1]:4 mux_bottom_track_33\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size7_2_sram[1]:17 mux_tree_tapbuf_size7_2_sram[1]:16 0.0045 +11 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:15 0.002388393 +12 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:12 0.002691964 +13 mux_tree_tapbuf_size7_2_sram[1]:18 mux_tree_tapbuf_size7_2_sram[1]:17 0.0004754465 +14 mux_tree_tapbuf_size7_2_sram[1]:11 mux_tree_tapbuf_size7_2_sram[1]:10 0.0006919643 +15 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:11 0.0045 +16 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:9 0.00415625 +17 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:4 0.0003437501 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001559905 //LENGTH 11.435 LUMPCC 0.0008019998 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_1_:X O *L 0 *C 78.945 105.400 +*I mux_top_track_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 81.630 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 81.593 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 79.625 113.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 79.580 113.175 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 79.580 105.445 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 79.535 105.400 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 78.983 105.400 + +*CAP +0 mux_top_track_0\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 9.775248e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 9.775248e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0002127304 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0002127304 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 6.746975e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 6.746975e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 chany_top_in[12]:43 0.0002140376 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 chany_top_in[12]:42 0.0002140376 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 chany_top_in[0] 0.0001000239 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 chany_top_in[0]:9 0.0001000239 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_tree_tapbuf_size12_0_sram[3]:5 8.693831e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_tree_tapbuf_size12_0_sram[3]:4 8.693831e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.001756696 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.006901786 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0008369543 //LENGTH 5.675 LUMPCC 0.000180548 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_0_:X O *L 0 *C 77.565 112.540 +*I mux_top_track_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 81.980 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 81.980 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 81.880 112.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 78.660 112.200 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 78.660 112.540 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 77.603 112.540 + +*CAP +0 mux_top_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 5.545155e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0002172405 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002156729 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 9.510381e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 7.093771e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_tree_tapbuf_size12_0_sram[3]:5 2.368482e-06 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size12_0_sram[3]:4 4.866227e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size12_0_sram[3]:5 4.866227e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size12_0_sram[3]:4 3.924323e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size12_0_sram[3]:3 2.368482e-06 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size12_0_sram[3]:5 3.924323e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0009441964 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0003035715 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.002875 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008799456 //LENGTH 6.340 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_3_:X O *L 0 *C 61.355 91.460 +*I mux_top_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 61.930 96.900 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 61.930 96.900 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.640 96.900 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 61.640 96.855 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 61.640 91.505 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 61.640 91.460 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 61.355 91.460 + +*CAP +0 mux_top_track_2\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.881829e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.457808e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003173302 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003173302 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.976231e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.012659e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_3_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_2\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001576087 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009279458 //LENGTH 7.690 LUMPCC 0.0001294542 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_3_:X O *L 0 *C 94.125 99.280 +*I mux_right_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 96.315 104.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 96.315 104.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 96.140 104.040 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 96.140 103.995 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 96.140 99.325 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 96.095 99.280 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 94.163 99.280 + +*CAP +0 mux_right_track_0\/mux_l1_in_3_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.201504e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.538097e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002038849 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002038849 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000140663 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000140663 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_bottom_in[9]:8 6.472709e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_bottom_in[9]:9 6.472709e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_3_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_0\/mux_l2_in_1_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004169643 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003076464 //LENGTH 20.280 LUMPCC 0.001022617 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_1_:X O *L 0 *C 94.125 95.880 +*I mux_right_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 108.735 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 108.735 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 108.560 91.460 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 108.560 91.505 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 108.560 94.463 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 108.553 94.520 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 94.308 94.520 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 94.300 94.578 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 94.300 95.835 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 94.300 95.880 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 94.125 95.880 + +*CAP +0 mux_right_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.442862e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.646193e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001690303 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001690303 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006387605 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006387605 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.817928e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 8.817928e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.302281e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.59936e-05 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[4]:24 1.99712e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[4]:25 1.99712e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[4]:26 0.0003028212 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[4]:27 0.0003028212 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size12_3_sram[0]:27 0.0001806934 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size12_3_sram[0]:26 7.82271e-06 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size12_3_sram[0]:26 0.0001806934 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size12_3_sram[0]:18 7.82271e-06 + +*RES +0 mux_right_track_2\/mux_l1_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.510871e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002640625 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002231717 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001122768 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.002460989 //LENGTH 19.145 LUMPCC 0.000561787 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_2_:X O *L 0 *C 78.485 33.320 +*I mux_bottom_track_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 88.880 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 88.843 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 85.145 25.500 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 85.100 25.545 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 85.100 33.275 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 85.055 33.320 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 78.523 33.320 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0002119207 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002119207 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003364101 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003364101 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0004002704 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0004002704 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size12_4_sram[1]:15 4.571545e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size12_4_sram[1]:19 3.587294e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size12_4_sram[1]:6 2.177189e-07 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size12_4_sram[1]:8 1.143067e-06 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size12_4_sram[1]:10 8.288519e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size12_4_sram[1]:12 4.571545e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size12_4_sram[1]:15 3.587294e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size12_4_sram[1]:7 2.177189e-07 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size12_4_sram[1]:9 8.288519e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_tree_tapbuf_size12_4_sram[1]:11 1.143067e-06 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 5.035285e-05 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 5.035285e-05 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 6.470631e-05 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 6.470631e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_1\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.003301339 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.006901786 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00583259 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0] 0.004613531 //LENGTH 34.430 LUMPCC 0.001085679 DR + +*CONN +*I mux_left_track_1\/mux_l4_in_0_:X O *L 0 *C 20.415 82.620 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.340 77.385 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 5.340 77.385 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 5.520 77.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 5.520 77.475 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 5.520 71.445 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 5.565 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 10.535 71.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 *C 10.580 71.445 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 *C 10.580 80.875 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:10 *C 10.625 80.920 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:11 *C 16.975 80.920 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:12 *C 17.020 80.965 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:13 *C 17.020 82.575 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 *C 17.065 82.620 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 *C 20.378 82.620 + +*CAP +0 mux_left_track_1\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 4.950933e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 5.437769e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0002461314 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0002461314 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0003546778 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0003546778 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.0003649342 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 0.0003649342 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:10 0.0004402116 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:11 0.0004402116 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:12 0.000122353 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:13 0.000122353 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 0.0001826747 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 0.0001826747 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 chanx_right_in[2]:8 6.858334e-06 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 chanx_right_in[2]:9 6.858334e-06 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 chanx_right_in[2]:13 0.0001102069 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 chanx_right_in[2]:14 0.0001102069 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 chanx_right_in[10]:9 0.0002513286 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 chanx_right_in[10]:8 0.0002513286 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:657 7.498752e-05 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:662 3.613702e-08 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:666 9.799871e-09 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 prog_clk[0]:670 9.273175e-05 +26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:666 3.613702e-08 +27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:667 9.799871e-09 +28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:670 7.498752e-05 +29 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 prog_clk[0]:674 9.273175e-05 +30 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 prog_clk[0]:660 6.68055e-06 +31 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 prog_clk[0]:659 6.68055e-06 + +*RES +0 mux_left_track_1\/mux_l4_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:2 9.782609e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.005383929 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:6 0.0044375 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.0045 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 0.0045 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:8 0.008419643 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:10 0.005669643 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:11 0.0045 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:13 0.0045 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:12 0.0014375 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_11_X[0]:14 0.002957589 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001261966 //LENGTH 8.915 LUMPCC 0.0002428942 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_1_:X O *L 0 *C 54.455 96.900 +*I mux_left_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 45.830 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 45.867 96.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 54.418 96.900 + +*CAP +0 mux_left_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005085361 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0005085361 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 optlc_net_148:10 0.0001214471 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 optlc_net_148:9 0.0001214471 + +*RES +0 mux_left_track_3\/mux_l2_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.007633929 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0] 0.001400617 //LENGTH 11.440 LUMPCC 9.706103e-05 DR + +*CONN +*I mux_top_track_4\/mux_l4_in_1_:X O *L 0 *C 44.905 102.680 +*I mux_top_track_4\/mux_l5_in_0_:A0 I *L 0.001631 *C 44.335 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 *C 44.335 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 *C 44.620 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 *C 44.620 113.175 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 *C 44.620 102.725 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 *C 44.620 102.680 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 *C 44.905 102.680 + +*CAP +0 mux_top_track_4\/mux_l4_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l5_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 4.60877e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 5.023054e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.0005500743 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0005500743 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 5.428314e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 5.080591e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 top_left_grid_pin_39_[0]:12 2.011554e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 top_left_grid_pin_39_[0]:13 2.841497e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 top_left_grid_pin_39_[0]:10 2.011554e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 top_left_grid_pin_39_[0]:12 2.841497e-05 + +*RES +0 mux_top_track_4\/mux_l4_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 mux_top_track_4\/mux_l5_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:2 0.0001548913 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:4 0.009330357 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_14_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001771392 //LENGTH 12.865 LUMPCC 0.0005110562 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 68.825 88.060 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 76.000 83.300 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.963 83.300 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 70.425 83.300 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 70.380 83.345 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 70.380 88.015 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 70.335 88.060 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 68.862 88.060 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370781 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003370781 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000211906 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000211906 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.018358e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.018358e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[4]:20 0.0001288772 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[4]:23 0.0001288772 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size16_1_sram[0]:12 6.677155e-05 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size16_1_sram[0]:11 6.677155e-05 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 5.987936e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 5.987936e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004944196 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET optlc_net_149 0.0007133001 //LENGTH 5.370 LUMPCC 0.0001187771 DR + +*CONN +*I optlc_142:HI O *L 0 *C 54.280 17.680 +*I mux_bottom_track_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 54.455 22.440 +*N optlc_net_149:2 *C 54.455 22.440 +*N optlc_net_149:3 *C 54.280 22.440 +*N optlc_net_149:4 *C 54.280 22.395 +*N optlc_net_149:5 *C 54.280 17.725 +*N optlc_net_149:6 *C 54.280 17.680 + +*CAP +0 optlc_142:HI 1e-06 +1 mux_bottom_track_3\/mux_l2_in_3_:A0 1e-06 +2 optlc_net_149:2 5.215359e-05 +3 optlc_net_149:3 5.580304e-05 +4 optlc_net_149:4 0.0002210564 +5 optlc_net_149:5 0.0002210564 +6 optlc_net_149:6 4.245343e-05 +7 optlc_net_149:5 chany_top_in[14]:13 5.938856e-05 +8 optlc_net_149:4 chany_top_in[14]:14 5.938856e-05 + +*RES +0 optlc_142:HI optlc_net_149:6 0.152 +1 optlc_net_149:6 optlc_net_149:5 0.0045 +2 optlc_net_149:5 optlc_net_149:4 0.004169643 +3 optlc_net_149:3 optlc_net_149:2 9.51087e-05 +4 optlc_net_149:4 optlc_net_149:3 0.0045 +5 optlc_net_149:2 mux_bottom_track_3\/mux_l2_in_3_:A0 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007958155 //LENGTH 7.015 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_2_:X O *L 0 *C 32.375 21.080 +*I mux_bottom_track_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 34.040 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 34.003 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 33.625 25.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 33.580 25.455 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 33.580 21.125 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 33.535 21.080 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 32.413 21.080 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.994332e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.994332e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002364638 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002364638 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001105006 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001105006 + +*RES +0 mux_bottom_track_5\/mux_l2_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001002232 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.003866072 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003370536 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_5\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0] 0.001015332 //LENGTH 6.895 LUMPCC 0.0004234736 DR + +*CONN +*I mux_left_track_5\/mux_l4_in_0_:X O *L 0 *C 16.275 88.400 +*I mux_left_track_5\/mux_l5_in_0_:A1 I *L 0.00198 *C 10.120 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 10.120 88.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 10.120 88.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 *C 16.238 88.400 + +*CAP +0 mux_left_track_5\/mux_l4_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l5_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 5.471494e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0002810295 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0002541135 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_tree_tapbuf_size16_3_sram[3]:7 2.82933e-06 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_tree_tapbuf_size16_3_sram[3]:9 6.583898e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_tree_tapbuf_size16_3_sram[3]:8 1.564111e-07 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_tree_tapbuf_size16_3_sram[3]:8 2.82933e-06 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_tree_tapbuf_size16_3_sram[3]:9 1.564111e-07 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_tree_tapbuf_size16_3_sram[3]:10 6.583898e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001046475 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0001046475 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:3 3.826459e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_14_X[0]:2 3.826459e-05 + +*RES +0 mux_left_track_5\/mux_l4_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.005462054 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_left_track_5\/mux_l5_in_0_:A1 0.152 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.01368874 //LENGTH 100.620 LUMPCC 0.0005154788 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 62.845 114.920 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 99.360 58.140 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 99.398 58.140 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 99.775 58.140 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 99.820 58.185 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 99.820 61.823 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 99.828 61.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 102.100 61.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 102.120 61.888 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 102.120 114.913 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 102.100 114.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 63.028 114.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 63.020 114.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 63.020 114.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 62.845 114.920 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.357089e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.357089e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002211533 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002211533 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002831132 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002831132 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.003320185 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.003320185 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002638312 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.002638312 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 3.308976e-05 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:13 5.287874e-05 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:14 5.262731e-05 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.0001784746 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 7.926479e-05 +17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:8 7.926479e-05 +18 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0001784746 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370536 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.003247768 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000356025 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.00341 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.008307249 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.00341 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.006121358 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0045 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:13 9.510871e-05 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001740067 //LENGTH 13.215 LUMPCC 0.0003012273 DR + +*CONN +*I mux_top_track_16\/mux_l3_in_1_:X O *L 0 *C 45.365 50.660 +*I mux_top_track_16\/mux_l4_in_0_:A0 I *L 0.001631 *C 49.340 59.160 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 49.303 59.160 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 45.585 59.160 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 45.540 59.115 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 45.540 50.705 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 45.540 50.660 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 45.365 50.660 + +*CAP +0 mux_top_track_16\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001869099 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001869099 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004789362 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004789362 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 5.464831e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 5.049878e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 chany_bottom_in[17]:21 0.0001506136 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 chany_bottom_in[17]:22 0.0001506136 + +*RES +0 mux_top_track_16\/mux_l3_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 9.51087e-05 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.007508929 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.003319197 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_16\/mux_l4_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0] 0.002383592 //LENGTH 16.120 LUMPCC 0.001228948 DR + +*CONN +*I mux_top_track_24\/mux_l3_in_1_:X O *L 0 *C 57.785 69.700 +*I mux_top_track_24\/mux_l4_in_0_:A0 I *L 0.001631 *C 65.495 77.180 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 65.458 77.180 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 58.465 77.180 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 58.420 77.135 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 58.420 69.745 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 58.375 69.700 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 57.823 69.700 + +*CAP +0 mux_top_track_24\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002739153 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002739153 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002329898 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002329898 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 6.941692e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 6.941692e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 chany_top_in[10]:25 0.0002727807 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 chany_top_in[10]:24 0.0002727807 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_2_sram[0]:27 1.47016e-08 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_2_sram[0]:26 1.47016e-08 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:17 2.831387e-05 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_2_sram[0]:28 0.000120174 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_2_sram[0]:28 2.831387e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_2_sram[0]:29 0.000120174 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 optlc_net_148:7 0.0001931909 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 optlc_net_148:6 0.0001931909 + +*RES +0 mux_top_track_24\/mux_l3_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_24\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.006243304 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.006598214 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001710045 //LENGTH 11.490 LUMPCC 0.00075648 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_0_:X O *L 0 *C 80.785 58.140 +*I mux_right_track_16\/mux_l3_in_0_:A1 I *L 0.00198 *C 80.600 47.260 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 80.500 47.260 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 80.500 47.305 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 80.500 58.095 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 80.500 58.140 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 80.785 58.140 + +*CAP +0 mux_right_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.468268e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004003212 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0004003212 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.986523e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.637489e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chany_bottom_in[6]:24 9.535351e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_bottom_in[6]:23 9.535351e-05 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 prog_clk[0]:298 0.0002828865 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:294 0.0002828865 + +*RES +0 mux_right_track_16\/mux_l2_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.009633929 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.880435e-05 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006868372 //LENGTH 5.740 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_1_:X O *L 0 *C 95.505 80.920 +*I mux_right_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 98.615 82.620 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 98.578 82.620 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 97.565 82.620 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 97.520 82.575 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 97.520 80.965 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 97.475 80.920 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 95.543 80.920 + +*CAP +0 mux_right_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.350257e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.350257e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001096213 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001096213 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001492947 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001492947 + +*RES +0 mux_right_track_24\/mux_l2_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009040179 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725446 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0003102752 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_1_:X O *L 0 *C 96.425 22.440 +*I mux_bottom_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 98.615 22.440 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 98.578 22.440 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 96.463 22.440 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001541376 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001541376 + +*RES +0 mux_bottom_track_9\/mux_l2_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0009292813 //LENGTH 8.150 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l4_in_0_:X O *L 0 *C 100.915 20.060 +*I mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 98.260 15.125 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 98.260 15.125 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 98.440 15.300 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 98.440 15.345 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 98.440 20.015 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 98.485 20.060 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 100.878 20.060 + +*CAP +0 mux_bottom_track_9\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 4.825459e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 4.691276e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002424189 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002424189 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001736381 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0001736381 + +*RES +0 mux_bottom_track_9\/mux_l4_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.782609e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.004169643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.002136161 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008129418 //LENGTH 6.050 LUMPCC 0.0001561682 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 71.475 44.880 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 67.065 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 67.028 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 66.700 45.220 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 66.700 44.880 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 71.438 44.880 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.192947e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.614064e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002854573 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002612461 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_8_sram[0]:10 3.334104e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size10_8_sram[0]:14 4.474306e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_8_sram[0]:11 3.334104e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size10_8_sram[0]:15 4.474306e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004229911 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002924107 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.003297308 //LENGTH 23.235 LUMPCC 0.0005599631 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 71.935 72.420 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 54.740 74.460 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 54.778 74.460 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 56.580 74.460 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 56.580 74.120 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 59.295 74.120 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 59.340 74.120 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 61.640 74.120 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 61.640 75.095 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 61.685 75.140 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 71.255 75.140 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 71.300 75.095 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 71.300 72.465 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 71.345 72.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 71.898 72.420 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001339431 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001603439 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002649335 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002385327 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001828609 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002222367 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.658865e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004795415 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0004795415 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001807573 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0001807573 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:13 6.765417e-05 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:14 6.765417e-05 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_bottom_in[5]:25 0.0002799815 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 chany_bottom_in[5]:26 0.0002799815 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002424107 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0008705357 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.008544643 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0045 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0045 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.002348214 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:13 0.0004933036 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001609375 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002053572 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0] 0.005221446 //LENGTH 24.775 LUMPCC 0.003022495 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_1_:X O *L 0 *C 57.675 53.720 +*I mux_left_track_17\/mux_l3_in_0_:A0 I *L 0.001631 *C 36.170 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 36.170 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 36.340 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 36.340 55.420 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 36.340 55.760 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 36.348 55.760 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 57.492 55.760 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 57.500 55.703 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 57.500 53.765 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 57.500 53.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 57.675 53.720 + +*CAP +0 mux_left_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.688508e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.247302e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.288562e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.702444e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0007676384 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0007676384 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001642401 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001642401 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.425237e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:11 4.967284e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[8]:10 0.0008577827 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[8]:11 0.0002821543 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[8]:9 0.0008577827 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[8]:10 0.0002821543 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chany_bottom_in[17]:29 0.0001766051 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chany_bottom_in[17]:28 0.0001766051 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001947055 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001947055 + +*RES +0 mux_left_track_17\/mux_l2_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:10 9.51087e-05 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.001729911 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.003312716 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001634615 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002810091 //LENGTH 17.550 LUMPCC 0.0001601122 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_0_:X O *L 0 *C 62.385 107.100 +*I mux_top_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 78.760 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 78.660 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 78.660 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 78.660 106.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 78.653 106.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.028 106.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 63.020 106.760 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 63.020 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 62.975 107.100 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 62.423 107.100 + +*CAP +0 mux_top_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.825458e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.247727e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.69119e-05 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001117294 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001117294 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.462602e-05 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.016666e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.047741e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 7.047741e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 prog_clk[0]:571 9.931635e-06 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:572 9.931635e-06 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:562 1.402805e-05 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:563 1.365228e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:570 4.244412e-05 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:549 1.402805e-05 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:562 1.365228e-05 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:569 4.244412e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004933036 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001634615 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00341 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002447916 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001634615 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00341 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A1 0.152 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET optlc_net_152 0.01180972 //LENGTH 79.570 LUMPCC 0.002671454 DR + +*CONN +*I optlc_148:HI O *L 0 *C 100.280 42.500 +*I mux_right_track_16\/mux_l2_in_3_:A0 I *L 0.001631 *C 88.610 49.640 +*I mux_bottom_track_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 83.895 33.660 +*I mux_bottom_track_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 103.790 33.660 +*I mux_top_track_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 106.895 42.840 +*I mux_right_track_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 111.035 53.720 +*N optlc_net_152:6 *C 111.073 53.720 +*N optlc_net_152:7 *C 111.735 53.720 +*N optlc_net_152:8 *C 111.780 53.675 +*N optlc_net_152:9 *C 111.780 50.365 +*N optlc_net_152:10 *C 111.735 50.320 +*N optlc_net_152:11 *C 110.905 50.320 +*N optlc_net_152:12 *C 110.860 50.275 +*N optlc_net_152:13 *C 110.860 42.885 +*N optlc_net_152:14 *C 110.815 42.840 +*N optlc_net_152:15 *C 106.933 42.840 +*N optlc_net_152:16 *C 106.720 42.500 +*N optlc_net_152:17 *C 103.790 33.660 +*N optlc_net_152:18 *C 103.500 33.660 +*N optlc_net_152:19 *C 103.500 33.705 +*N optlc_net_152:20 *C 103.500 37.343 +*N optlc_net_152:21 *C 103.493 37.400 +*N optlc_net_152:22 *C 83.895 33.660 +*N optlc_net_152:23 *C 83.720 33.660 +*N optlc_net_152:24 *C 83.720 33.705 +*N optlc_net_152:25 *C 83.720 36.663 +*N optlc_net_152:26 *C 83.728 36.720 +*N optlc_net_152:27 *C 92.000 36.720 +*N optlc_net_152:28 *C 92.000 37.400 +*N optlc_net_152:29 *C 100.740 37.400 +*N optlc_net_152:30 *C 100.740 37.458 +*N optlc_net_152:31 *C 100.740 42.455 +*N optlc_net_152:32 *C 100.740 42.500 +*N optlc_net_152:33 *C 88.648 49.640 +*N optlc_net_152:34 *C 99.775 49.640 +*N optlc_net_152:35 *C 99.820 49.595 +*N optlc_net_152:36 *C 99.820 42.545 +*N optlc_net_152:37 *C 99.865 42.500 +*N optlc_net_152:38 *C 100.280 42.500 + +*CAP +0 optlc_148:HI 1e-06 +1 mux_right_track_16\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_track_1\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_track_9\/mux_l2_in_3_:A0 1e-06 +4 mux_top_track_8\/mux_l2_in_3_:A0 1e-06 +5 mux_right_track_8\/mux_l2_in_3_:A0 1e-06 +6 optlc_net_152:6 8.311897e-05 +7 optlc_net_152:7 8.311897e-05 +8 optlc_net_152:8 0.0001929338 +9 optlc_net_152:9 0.0001929338 +10 optlc_net_152:10 9.165278e-05 +11 optlc_net_152:11 9.165278e-05 +12 optlc_net_152:12 0.0004435977 +13 optlc_net_152:13 0.0004435977 +14 optlc_net_152:14 0.0002580571 +15 optlc_net_152:15 0.0002844712 +16 optlc_net_152:16 0.0003990262 +17 optlc_net_152:17 4.548255e-05 +18 optlc_net_152:18 4.994107e-05 +19 optlc_net_152:19 0.0002331814 +20 optlc_net_152:20 0.0002331814 +21 optlc_net_152:21 0.0001377027 +22 optlc_net_152:22 6.374942e-05 +23 optlc_net_152:23 6.772595e-05 +24 optlc_net_152:24 0.0002056021 +25 optlc_net_152:25 0.0002056021 +26 optlc_net_152:26 0.0004290498 +27 optlc_net_152:27 0.0004921609 +28 optlc_net_152:28 0.0004447646 +29 optlc_net_152:29 0.0005193562 +30 optlc_net_152:30 0.0002758114 +31 optlc_net_152:31 0.0002758114 +32 optlc_net_152:32 0.0004319279 +33 optlc_net_152:33 0.0007512271 +34 optlc_net_152:34 0.0007512271 +35 optlc_net_152:35 0.0004164908 +36 optlc_net_152:36 0.0004164908 +37 optlc_net_152:37 3.464189e-05 +38 optlc_net_152:38 8.697531e-05 +39 optlc_net_152:21 chanx_right_in[3] 0.0001601101 +40 optlc_net_152:29 chanx_right_in[3] 0.0004691185 +41 optlc_net_152:29 chanx_right_in[3]:14 0.0001601101 +42 optlc_net_152:26 chanx_right_in[3]:14 2.625714e-05 +43 optlc_net_152:27 chanx_right_in[3] 2.625714e-05 +44 optlc_net_152:27 chanx_right_in[3]:12 7.234563e-06 +45 optlc_net_152:28 chanx_right_in[3]:13 7.234563e-06 +46 optlc_net_152:28 chanx_right_in[3]:14 0.0004691185 +47 optlc_net_152:30 chanx_left_in[11]:9 2.069763e-05 +48 optlc_net_152:29 chanx_left_in[11]:10 0.0001248412 +49 optlc_net_152:31 chanx_left_in[11]:5 2.069763e-05 +50 optlc_net_152:26 chanx_left_in[11]:11 0.0004524721 +51 optlc_net_152:27 chanx_left_in[11]:10 0.0004524721 +52 optlc_net_152:28 chanx_left_in[11]:11 0.0001248412 +53 optlc_net_152:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 7.49959e-05 +54 optlc_net_152:15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.49959e-05 + +*RES +0 optlc_148:HI optlc_net_152:38 0.152 +1 optlc_net_152:14 optlc_net_152:13 0.0045 +2 optlc_net_152:13 optlc_net_152:12 0.006598215 +3 optlc_net_152:11 optlc_net_152:10 0.0007410714 +4 optlc_net_152:12 optlc_net_152:11 0.0045 +5 optlc_net_152:10 optlc_net_152:9 0.0045 +6 optlc_net_152:9 optlc_net_152:8 0.002955357 +7 optlc_net_152:7 optlc_net_152:6 0.0005915179 +8 optlc_net_152:8 optlc_net_152:7 0.0045 +9 optlc_net_152:6 mux_right_track_8\/mux_l2_in_3_:A0 0.152 +10 optlc_net_152:20 optlc_net_152:19 0.003247768 +11 optlc_net_152:21 optlc_net_152:20 0.00341 +12 optlc_net_152:18 optlc_net_152:17 0.0001576087 +13 optlc_net_152:19 optlc_net_152:18 0.0045 +14 optlc_net_152:17 mux_bottom_track_9\/mux_l2_in_3_:A0 0.152 +15 optlc_net_152:30 optlc_net_152:29 0.00341 +16 optlc_net_152:29 optlc_net_152:28 0.001369267 +17 optlc_net_152:29 optlc_net_152:21 0.0004312249 +18 optlc_net_152:32 optlc_net_152:31 0.0045 +19 optlc_net_152:32 optlc_net_152:16 0.005339286 +20 optlc_net_152:31 optlc_net_152:30 0.004462054 +21 optlc_net_152:37 optlc_net_152:36 0.0045 +22 optlc_net_152:36 optlc_net_152:35 0.006294644 +23 optlc_net_152:34 optlc_net_152:33 0.009935268 +24 optlc_net_152:35 optlc_net_152:34 0.0045 +25 optlc_net_152:33 mux_right_track_16\/mux_l2_in_3_:A0 0.152 +26 optlc_net_152:25 optlc_net_152:24 0.002640625 +27 optlc_net_152:26 optlc_net_152:25 0.00341 +28 optlc_net_152:23 optlc_net_152:22 9.51087e-05 +29 optlc_net_152:24 optlc_net_152:23 0.0045 +30 optlc_net_152:22 mux_bottom_track_1\/mux_l2_in_3_:A0 0.152 +31 optlc_net_152:38 optlc_net_152:37 0.0003705357 +32 optlc_net_152:38 optlc_net_152:32 0.0004107143 +33 optlc_net_152:15 mux_top_track_8\/mux_l2_in_3_:A0 0.152 +34 optlc_net_152:15 optlc_net_152:14 0.003466518 +35 optlc_net_152:16 optlc_net_152:15 0.0003035715 +36 optlc_net_152:27 optlc_net_152:26 0.001296025 +37 optlc_net_152:28 optlc_net_152:27 0.0001065333 + +*END + +*D_NET ropt_net_201 0.001188102 //LENGTH 8.255 LUMPCC 0.0003906189 DR + +*CONN +*I FTB_31__30:X O *L 0 *C 57.205 125.800 +*I ropt_mt_inst_842:A I *L 0.001766 *C 54.740 121.040 +*N ropt_net_201:2 *C 54.778 121.040 +*N ropt_net_201:3 *C 56.535 121.040 +*N ropt_net_201:4 *C 56.580 121.085 +*N ropt_net_201:5 *C 56.580 121.720 +*N ropt_net_201:6 *C 57.040 121.720 +*N ropt_net_201:7 *C 57.040 125.755 +*N ropt_net_201:8 *C 57.040 125.800 +*N ropt_net_201:9 *C 57.205 125.800 + +*CAP +0 FTB_31__30:X 1e-06 +1 ropt_mt_inst_842:A 1e-06 +2 ropt_net_201:2 0.0001310143 +3 ropt_net_201:3 0.0001310143 +4 ropt_net_201:4 5.692353e-05 +5 ropt_net_201:5 7.921812e-05 +6 ropt_net_201:6 0.0001515286 +7 ropt_net_201:7 0.000129234 +8 ropt_net_201:8 6.043689e-05 +9 ropt_net_201:9 5.611303e-05 +10 ropt_net_201:4 chany_top_in[1]:25 7.515512e-07 +11 ropt_net_201:7 chany_top_in[1] 0.0001070568 +12 ropt_net_201:5 chany_top_in[1] 7.515512e-07 +13 ropt_net_201:6 chany_top_in[1]:25 0.0001070568 +14 ropt_net_201:7 ropt_net_215:7 7.607559e-05 +15 ropt_net_201:5 ropt_net_215:9 1.14255e-05 +16 ropt_net_201:6 ropt_net_215:10 1.14255e-05 +17 ropt_net_201:6 ropt_net_215:8 7.607559e-05 + +*RES +0 FTB_31__30:X ropt_net_201:9 0.152 +1 ropt_net_201:2 ropt_mt_inst_842:A 0.152 +2 ropt_net_201:3 ropt_net_201:2 0.001569197 +3 ropt_net_201:4 ropt_net_201:3 0.0045 +4 ropt_net_201:8 ropt_net_201:7 0.0045 +5 ropt_net_201:7 ropt_net_201:6 0.003602679 +6 ropt_net_201:9 ropt_net_201:8 8.967391e-05 +7 ropt_net_201:5 ropt_net_201:4 0.0005669643 +8 ropt_net_201:6 ropt_net_201:5 0.0004107143 + +*END + +*D_NET ropt_net_178 0.002283202 //LENGTH 21.220 LUMPCC 0.0004230475 DR + +*CONN +*I FTB_47__46:X O *L 0 *C 136.620 94.180 +*I ropt_mt_inst_816:A I *L 0.001766 *C 134.780 82.960 +*N ropt_net_178:2 *C 134.817 82.960 +*N ropt_net_178:3 *C 139.795 82.960 +*N ropt_net_178:4 *C 139.840 83.005 +*N ropt_net_178:5 *C 139.840 94.475 +*N ropt_net_178:6 *C 139.795 94.520 +*N ropt_net_178:7 *C 136.620 94.520 +*N ropt_net_178:8 *C 136.620 94.180 + +*CAP +0 FTB_47__46:X 1e-06 +1 ropt_mt_inst_816:A 1e-06 +2 ropt_net_178:2 0.0002674966 +3 ropt_net_178:3 0.0002674966 +4 ropt_net_178:4 0.000406256 +5 ropt_net_178:5 0.000406256 +6 ropt_net_178:6 0.0002115598 +7 ropt_net_178:7 0.0002403379 +8 ropt_net_178:8 5.875249e-05 +9 ropt_net_178:4 chanx_right_out[0]:3 0.0001491052 +10 ropt_net_178:5 chanx_right_out[0]:4 0.0001491052 +11 ropt_net_178:2 ropt_net_177:8 6.24185e-05 +12 ropt_net_178:3 ropt_net_177:7 6.24185e-05 + +*RES +0 FTB_47__46:X ropt_net_178:8 0.152 +1 ropt_net_178:2 ropt_mt_inst_816:A 0.152 +2 ropt_net_178:3 ropt_net_178:2 0.004444197 +3 ropt_net_178:4 ropt_net_178:3 0.0045 +4 ropt_net_178:6 ropt_net_178:5 0.0045 +5 ropt_net_178:5 ropt_net_178:4 0.01024107 +6 ropt_net_178:8 ropt_net_178:7 0.0003035715 +7 ropt_net_178:7 ropt_net_178:6 0.002834822 + +*END + +*D_NET ropt_net_206 0.001412647 //LENGTH 10.085 LUMPCC 0.0002651649 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 11.695 74.120 +*I ropt_mt_inst_845:A I *L 0.001767 *C 3.220 74.800 +*N ropt_net_206:2 *C 3.258 74.800 +*N ropt_net_206:3 *C 4.095 74.800 +*N ropt_net_206:4 *C 4.140 74.755 +*N ropt_net_206:5 *C 4.140 74.165 +*N ropt_net_206:6 *C 4.185 74.120 +*N ropt_net_206:7 *C 11.658 74.120 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 ropt_mt_inst_845:A 1e-06 +2 ropt_net_206:2 5.360879e-05 +3 ropt_net_206:3 5.360879e-05 +4 ropt_net_206:4 6.352048e-05 +5 ropt_net_206:5 6.352048e-05 +6 ropt_net_206:6 0.0004556119 +7 ropt_net_206:7 0.0004556119 +8 ropt_net_206:2 ropt_net_176:5 3.617772e-05 +9 ropt_net_206:3 ropt_net_176:4 3.617772e-05 +10 ropt_net_206:6 ropt_net_176:5 7.550594e-05 +11 ropt_net_206:6 ropt_net_176:3 2.089879e-05 +12 ropt_net_206:7 ropt_net_176:2 2.089879e-05 +13 ropt_net_206:7 ropt_net_176:4 7.550594e-05 + +*RES +0 ropt_mt_inst_814:X ropt_net_206:7 0.152 +1 ropt_net_206:2 ropt_mt_inst_845:A 0.152 +2 ropt_net_206:3 ropt_net_206:2 0.0007477679 +3 ropt_net_206:4 ropt_net_206:3 0.0045 +4 ropt_net_206:6 ropt_net_206:5 0.0045 +5 ropt_net_206:5 ropt_net_206:4 0.0005267857 +6 ropt_net_206:7 ropt_net_206:6 0.006671876 + +*END + +*D_NET ropt_net_210 0.001455395 //LENGTH 10.160 LUMPCC 0.0002790094 DR + +*CONN +*I ropt_mt_inst_825:X O *L 0 *C 69.130 121.720 +*I ropt_mt_inst_849:A I *L 0.001767 *C 62.560 123.760 +*N ropt_net_210:2 *C 62.560 123.760 +*N ropt_net_210:3 *C 62.560 124.100 +*N ropt_net_210:4 *C 62.560 124.055 +*N ropt_net_210:5 *C 62.560 121.765 +*N ropt_net_210:6 *C 62.605 121.720 +*N ropt_net_210:7 *C 69.093 121.720 + +*CAP +0 ropt_mt_inst_825:X 1e-06 +1 ropt_mt_inst_849:A 1e-06 +2 ropt_net_210:2 7.565456e-05 +3 ropt_net_210:3 8.109989e-05 +4 ropt_net_210:4 0.0001165048 +5 ropt_net_210:5 0.0001165048 +6 ropt_net_210:6 0.0003923109 +7 ropt_net_210:7 0.0003923109 +8 ropt_net_210:7 chany_bottom_in[5]:11 2.234799e-05 +9 ropt_net_210:6 chany_bottom_in[5]:10 2.234799e-05 +10 ropt_net_210:5 chany_bottom_in[5]:10 5.867111e-05 +11 ropt_net_210:4 chany_bottom_in[5]:9 5.867111e-05 +12 ropt_net_210:7 chany_top_out[1]:4 5.848561e-05 +13 ropt_net_210:6 chany_top_out[1]:3 5.848561e-05 + +*RES +0 ropt_mt_inst_825:X ropt_net_210:7 0.152 +1 ropt_net_210:7 ropt_net_210:6 0.005792412 +2 ropt_net_210:6 ropt_net_210:5 0.0045 +3 ropt_net_210:5 ropt_net_210:4 0.002044643 +4 ropt_net_210:3 ropt_net_210:2 0.0001465518 +5 ropt_net_210:4 ropt_net_210:3 0.0045 +6 ropt_net_210:2 ropt_mt_inst_849:A 0.152 + +*END + +*D_NET ropt_net_193 0.001245009 //LENGTH 10.105 LUMPCC 0.0001021463 DR + +*CONN +*I BUFT_P_118:X O *L 0 *C 7.820 71.740 +*I ropt_mt_inst_832:A I *L 0.001766 *C 7.820 66.640 +*N ropt_net_193:2 *C 7.783 66.640 +*N ropt_net_193:3 *C 6.025 66.640 +*N ropt_net_193:4 *C 5.980 66.685 +*N ropt_net_193:5 *C 5.980 69.983 +*N ropt_net_193:6 *C 5.988 70.040 +*N ropt_net_193:7 *C 7.812 70.040 +*N ropt_net_193:8 *C 7.820 70.097 +*N ropt_net_193:9 *C 7.820 71.695 +*N ropt_net_193:10 *C 7.820 71.740 + +*CAP +0 BUFT_P_118:X 1e-06 +1 ropt_mt_inst_832:A 1e-06 +2 ropt_net_193:2 0.0001200782 +3 ropt_net_193:3 0.0001200782 +4 ropt_net_193:4 0.0001673983 +5 ropt_net_193:5 0.0001673983 +6 ropt_net_193:6 0.0001599234 +7 ropt_net_193:7 0.0001599234 +8 ropt_net_193:8 0.0001029554 +9 ropt_net_193:9 0.0001029554 +10 ropt_net_193:10 4.015167e-05 +11 ropt_net_193:9 prog_clk[0]:672 5.41102e-06 +12 ropt_net_193:8 prog_clk[0]:671 5.41102e-06 +13 ropt_net_193:5 prog_clk[0]:670 1.883915e-06 +14 ropt_net_193:5 prog_clk[0]:672 5.41102e-06 +15 ropt_net_193:5 prog_clk[0]:674 3.836718e-05 +16 ropt_net_193:4 prog_clk[0]:671 5.41102e-06 +17 ropt_net_193:4 prog_clk[0]:674 1.883915e-06 +18 ropt_net_193:4 prog_clk[0]:679 3.836718e-05 + +*RES +0 BUFT_P_118:X ropt_net_193:10 0.152 +1 ropt_net_193:10 ropt_net_193:9 0.0045 +2 ropt_net_193:9 ropt_net_193:8 0.001426339 +3 ropt_net_193:8 ropt_net_193:7 0.00341 +4 ropt_net_193:7 ropt_net_193:6 0.0002859167 +5 ropt_net_193:5 ropt_net_193:4 0.002944197 +6 ropt_net_193:6 ropt_net_193:5 0.00341 +7 ropt_net_193:3 ropt_net_193:2 0.001569197 +8 ropt_net_193:4 ropt_net_193:3 0.0045 +9 ropt_net_193:2 ropt_mt_inst_832:A 0.152 + +*END + +*D_NET chany_top_out[5] 0.0005539008 //LENGTH 4.220 LUMPCC 0 DR + +*CONN +*I BUFT_P_135:X O *L 0 *C 85.365 127.160 +*P chany_top_out[5] O *L 0.7423 *C 83.720 129.270 +*N chany_top_out[5]:2 *C 83.720 127.205 +*N chany_top_out[5]:3 *C 83.765 127.160 +*N chany_top_out[5]:4 *C 85.328 127.160 + +*CAP +0 BUFT_P_135:X 1e-06 +1 chany_top_out[5] 0.0001291172 +2 chany_top_out[5]:2 0.0001291172 +3 chany_top_out[5]:3 0.0001473332 +4 chany_top_out[5]:4 0.0001473332 + +*RES +0 BUFT_P_135:X chany_top_out[5]:4 0.152 +1 chany_top_out[5]:4 chany_top_out[5]:3 0.00139509 +2 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +3 chany_top_out[5]:2 chany_top_out[5] 0.00184375 + +*END + +*D_NET ropt_net_236 0.001394138 //LENGTH 10.305 LUMPCC 0.0003758927 DR + +*CONN +*I ropt_mt_inst_843:X O *L 0 *C 80.235 11.900 +*I ropt_mt_inst_884:A I *L 0.001767 *C 71.760 12.240 +*N ropt_net_236:2 *C 71.722 12.240 +*N ropt_net_236:3 *C 71.300 12.240 +*N ropt_net_236:4 *C 71.300 11.900 +*N ropt_net_236:5 *C 80.198 11.900 + +*CAP +0 ropt_mt_inst_843:X 1e-06 +1 ropt_mt_inst_884:A 1e-06 +2 ropt_net_236:2 2.356283e-05 +3 ropt_net_236:3 4.672675e-05 +4 ropt_net_236:4 0.00048456 +5 ropt_net_236:5 0.0004613961 +6 ropt_net_236:2 ropt_net_202:4 2.474783e-05 +7 ropt_net_236:5 ropt_net_202:2 0.0001596102 +8 ropt_net_236:5 ropt_net_202:4 2.006115e-06 +9 ropt_net_236:4 ropt_net_202:3 0.0001611924 +10 ropt_net_236:4 ropt_net_202:5 2.006115e-06 +11 ropt_net_236:3 ropt_net_202:4 1.582178e-06 +12 ropt_net_236:3 ropt_net_202:5 2.474783e-05 + +*RES +0 ropt_mt_inst_843:X ropt_net_236:5 0.152 +1 ropt_net_236:2 ropt_mt_inst_884:A 0.152 +2 ropt_net_236:5 ropt_net_236:4 0.007944196 +3 ropt_net_236:4 ropt_net_236:3 0.0003035715 +4 ropt_net_236:3 ropt_net_236:2 0.0003772322 + +*END + +*D_NET chany_top_out[18] 0.0007136968 //LENGTH 6.550 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_899:X O *L 0 *C 98.635 126.140 +*P chany_top_out[18] O *L 0.7423 *C 95.680 129.270 +*N chany_top_out[18]:2 *C 95.680 126.185 +*N chany_top_out[18]:3 *C 95.725 126.140 +*N chany_top_out[18]:4 *C 98.598 126.140 + +*CAP +0 ropt_mt_inst_899:X 1e-06 +1 chany_top_out[18] 0.0001636552 +2 chany_top_out[18]:2 0.0001636552 +3 chany_top_out[18]:3 0.0001926933 +4 chany_top_out[18]:4 0.0001926933 + +*RES +0 ropt_mt_inst_899:X chany_top_out[18]:4 0.152 +1 chany_top_out[18]:4 chany_top_out[18]:3 0.002564732 +2 chany_top_out[18]:3 chany_top_out[18]:2 0.0045 +3 chany_top_out[18]:2 chany_top_out[18] 0.002754464 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..8b3624c --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef @@ -0,0 +1,26149 @@ +*SPEF "1481-1998" +*DESIGN "sb_1__2_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 30.820 0.680 +chanx_right_in[0] I *C 140.990 87.040 +chanx_right_in[1] I *C 140.990 57.120 +chanx_right_in[2] I *C 140.990 99.280 +chanx_right_in[3] I *C 140.990 96.560 +chanx_right_in[4] I *C 140.990 34.000 +chanx_right_in[5] I *C 140.990 62.560 +chanx_right_in[6] I *C 140.990 31.280 +chanx_right_in[7] I *C 140.990 50.320 +chanx_right_in[8] I *C 140.990 77.520 +chanx_right_in[9] I *C 140.990 35.360 +chanx_right_in[10] I *C 140.990 80.240 +chanx_right_in[11] I *C 140.990 58.480 +chanx_right_in[12] I *C 140.990 74.800 +chanx_right_in[13] I *C 140.990 36.720 +chanx_right_in[14] I *C 140.990 43.520 +chanx_right_in[15] I *C 140.990 55.760 +chanx_right_in[16] I *C 140.990 40.800 +chanx_right_in[17] I *C 140.990 61.200 +chanx_right_in[18] I *C 140.990 39.440 +chanx_right_in[19] I *C 140.990 72.080 +right_top_grid_pin_1_[0] I *C 139.380 102.680 +chany_bottom_in[0] I *C 82.340 0.680 +chany_bottom_in[1] I *C 67.160 0.680 +chany_bottom_in[2] I *C 81.420 0.680 +chany_bottom_in[3] I *C 88.320 0.680 +chany_bottom_in[4] I *C 65.320 0.680 +chany_bottom_in[5] I *C 75.900 0.680 +chany_bottom_in[6] I *C 94.300 0.680 +chany_bottom_in[7] I *C 87.400 0.680 +chany_bottom_in[8] I *C 77.740 0.680 +chany_bottom_in[9] I *C 84.180 0.680 +chany_bottom_in[10] I *C 62.560 0.680 +chany_bottom_in[11] I *C 86.480 0.680 +chany_bottom_in[12] I *C 79.580 0.680 +chany_bottom_in[13] I *C 68.080 0.680 +chany_bottom_in[14] I *C 66.240 0.680 +chany_bottom_in[15] I *C 53.360 0.680 +chany_bottom_in[16] I *C 76.820 0.680 +chany_bottom_in[17] I *C 69.920 0.680 +chany_bottom_in[18] I *C 57.500 0.680 +chany_bottom_in[19] I *C 78.660 0.680 +bottom_left_grid_pin_34_[0] I *C 29.210 10.200 +bottom_left_grid_pin_35_[0] I *C 29.210 8.160 +bottom_left_grid_pin_36_[0] I *C 29.210 6.800 +bottom_left_grid_pin_37_[0] I *C 29.210 3.400 +bottom_left_grid_pin_38_[0] I *C 29.210 4.760 +bottom_left_grid_pin_39_[0] I *C 29.210 11.560 +bottom_left_grid_pin_40_[0] I *C 29.210 12.920 +bottom_left_grid_pin_41_[0] I *C 29.210 14.280 +chanx_left_in[0] I *C 0.690 39.440 +chanx_left_in[1] I *C 0.690 42.160 +chanx_left_in[2] I *C 0.690 68.000 +chanx_left_in[3] I *C 0.690 61.200 +chanx_left_in[4] I *C 0.690 50.320 +chanx_left_in[5] I *C 0.690 46.240 +chanx_left_in[6] I *C 0.690 31.280 +chanx_left_in[7] I *C 0.690 72.080 +chanx_left_in[8] I *C 0.690 76.160 +chanx_left_in[9] I *C 0.690 99.280 +chanx_left_in[10] I *C 0.690 36.720 +chanx_left_in[11] I *C 0.690 63.920 +chanx_left_in[12] I *C 0.690 32.640 +chanx_left_in[13] I *C 0.690 74.800 +chanx_left_in[14] I *C 0.690 59.840 +chanx_left_in[15] I *C 0.690 96.560 +chanx_left_in[16] I *C 0.690 55.760 +chanx_left_in[17] I *C 0.690 53.040 +chanx_left_in[18] I *C 0.690 38.080 +chanx_left_in[19] I *C 0.690 81.600 +left_top_grid_pin_1_[0] I *C 2.300 102.680 +ccff_head[0] I *C 138.460 102.680 +chanx_right_out[0] O *C 140.990 73.440 +chanx_right_out[1] O *C 140.990 47.600 +chanx_right_out[2] O *C 140.990 53.040 +chanx_right_out[3] O *C 140.990 82.960 +chanx_right_out[4] O *C 140.990 78.880 +chanx_right_out[5] O *C 140.990 95.200 +chanx_right_out[6] O *C 140.990 84.320 +chanx_right_out[7] O *C 140.990 93.840 +chanx_right_out[8] O *C 140.990 85.680 +chanx_right_out[9] O *C 140.990 44.880 +chanx_right_out[10] O *C 140.990 51.680 +chanx_right_out[11] O *C 140.990 69.360 +chanx_right_out[12] O *C 140.990 42.160 +chanx_right_out[13] O *C 140.990 66.640 +chanx_right_out[14] O *C 140.990 91.120 +chanx_right_out[15] O *C 140.990 68.000 +chanx_right_out[16] O *C 140.990 63.920 +chanx_right_out[17] O *C 140.990 88.400 +chanx_right_out[18] O *C 140.990 89.760 +chanx_right_out[19] O *C 140.990 46.240 +chany_bottom_out[0] O *C 83.260 0.680 +chany_bottom_out[1] O *C 59.800 0.680 +chany_bottom_out[2] O *C 52.440 0.680 +chany_bottom_out[3] O *C 69.000 0.680 +chany_bottom_out[4] O *C 96.600 0.680 +chany_bottom_out[5] O *C 71.760 0.680 +chany_bottom_out[6] O *C 74.980 0.680 +chany_bottom_out[7] O *C 60.720 0.680 +chany_bottom_out[8] O *C 63.480 0.680 +chany_bottom_out[9] O *C 54.280 0.680 +chany_bottom_out[10] O *C 93.380 0.680 +chany_bottom_out[11] O *C 74.060 0.680 +chany_bottom_out[12] O *C 80.500 0.680 +chany_bottom_out[13] O *C 61.640 0.680 +chany_bottom_out[14] O *C 97.520 0.680 +chany_bottom_out[15] O *C 55.200 0.680 +chany_bottom_out[16] O *C 64.400 0.680 +chany_bottom_out[17] O *C 58.880 0.680 +chany_bottom_out[18] O *C 73.140 0.680 +chany_bottom_out[19] O *C 70.840 0.680 +chanx_left_out[0] O *C 0.690 80.240 +chanx_left_out[1] O *C 0.690 93.840 +chanx_left_out[2] O *C 0.690 34.000 +chanx_left_out[3] O *C 0.690 48.960 +chanx_left_out[4] O *C 0.690 58.480 +chanx_left_out[5] O *C 0.690 70.720 +chanx_left_out[6] O *C 0.690 43.520 +chanx_left_out[7] O *C 0.690 47.600 +chanx_left_out[8] O *C 0.690 85.680 +chanx_left_out[9] O *C 0.690 65.280 +chanx_left_out[10] O *C 0.690 97.920 +chanx_left_out[11] O *C 0.690 92.480 +chanx_left_out[12] O *C 0.690 82.960 +chanx_left_out[13] O *C 0.690 87.040 +chanx_left_out[14] O *C 0.690 69.360 +chanx_left_out[15] O *C 0.690 44.880 +chanx_left_out[16] O *C 0.690 54.400 +chanx_left_out[17] O *C 0.690 91.120 +chanx_left_out[18] O *C 0.690 66.640 +chanx_left_out[19] O *C 0.690 88.400 +ccff_tail[0] O *C 0.690 77.520 +VDD I *C 70.840 51.680 +VSS I *C 70.840 51.680 + +*D_NET chanx_right_in[2] 0.02704049 //LENGTH 227.440 LUMPCC 0.005795144 DR + +*CONN +*P chanx_right_in[2] I *L 0.29796 *C 140.450 99.280 +*I FTB_1__0:A I *L 0.001776 *C 14.720 50.320 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 35.520 30.940 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.180 30.940 +*N chanx_right_in[2]:4 *C 33.640 34.000 +*N chanx_right_in[2]:5 *C 61.143 30.940 +*N chanx_right_in[2]:6 *C 57.960 30.940 +*N chanx_right_in[2]:7 *C 57.960 31.960 +*N chanx_right_in[2]:8 *C 37.765 31.960 +*N chanx_right_in[2]:9 *C 37.720 31.915 +*N chanx_right_in[2]:10 *C 37.720 30.985 +*N chanx_right_in[2]:11 *C 37.675 30.940 +*N chanx_right_in[2]:12 *C 35.520 30.940 +*N chanx_right_in[2]:13 *C 34.085 30.940 +*N chanx_right_in[2]:14 *C 34.040 30.985 +*N chanx_right_in[2]:15 *C 34.040 33.943 +*N chanx_right_in[2]:16 *C 34.040 34.000 +*N chanx_right_in[2]:17 *C 34.040 34.008 +*N chanx_right_in[2]:18 *C 14.758 50.320 +*N chanx_right_in[2]:19 *C 15.135 50.320 +*N chanx_right_in[2]:20 *C 15.180 50.320 +*N chanx_right_in[2]:21 *C 15.188 50.320 +*N chanx_right_in[2]:22 *C 34.020 50.320 +*N chanx_right_in[2]:23 *C 34.040 50.320 +*N chanx_right_in[2]:24 *C 34.040 97.233 +*N chanx_right_in[2]:25 *C 34.060 97.240 +*N chanx_right_in[2]:26 *C 83.850 97.240 +*N chanx_right_in[2]:27 *C 133.850 97.240 +*N chanx_right_in[2]:28 *C 138.900 97.240 +*N chanx_right_in[2]:29 *C 138.920 97.248 +*N chanx_right_in[2]:30 *C 138.920 99.273 +*N chanx_right_in[2]:31 *C 138.940 99.280 + +*CAP +0 chanx_right_in[2] 7.155978e-05 +1 FTB_1__0:A 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +3 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[2]:4 9.647301e-05 +5 chanx_right_in[2]:5 0.0002590436 +6 chanx_right_in[2]:6 0.0003208605 +7 chanx_right_in[2]:7 0.001274011 +8 chanx_right_in[2]:8 0.001212194 +9 chanx_right_in[2]:9 8.035895e-05 +10 chanx_right_in[2]:10 8.035895e-05 +11 chanx_right_in[2]:11 0.0001632689 +12 chanx_right_in[2]:12 0.0002930064 +13 chanx_right_in[2]:13 9.914022e-05 +14 chanx_right_in[2]:14 0.0001903645 +15 chanx_right_in[2]:15 0.0001903645 +16 chanx_right_in[2]:16 9.647301e-05 +17 chanx_right_in[2]:17 0.0008802869 +18 chanx_right_in[2]:18 4.350123e-05 +19 chanx_right_in[2]:19 4.350123e-05 +20 chanx_right_in[2]:20 3.350122e-05 +21 chanx_right_in[2]:21 0.0004363312 +22 chanx_right_in[2]:22 0.0004363312 +23 chanx_right_in[2]:23 0.002834101 +24 chanx_right_in[2]:24 0.001953814 +25 chanx_right_in[2]:25 0.002357936 +26 chanx_right_in[2]:26 0.004522766 +27 chanx_right_in[2]:27 0.002571323 +28 chanx_right_in[2]:28 0.0004064931 +29 chanx_right_in[2]:29 0.0001117091 +30 chanx_right_in[2]:30 0.0001117091 +31 chanx_right_in[2]:31 7.155978e-05 +32 chanx_right_in[2]:22 chanx_right_in[5]:17 0.0003161383 +33 chanx_right_in[2]:22 chanx_right_in[5]:16 0.0007583522 +34 chanx_right_in[2]:21 chanx_right_in[5]:11 0.0007583522 +35 chanx_right_in[2]:21 chanx_right_in[5]:16 0.0003161383 +36 chanx_right_in[2]:24 chanx_left_in[2]:15 0.0002428322 +37 chanx_right_in[2]:24 chanx_left_in[2]:23 0.0001983926 +38 chanx_right_in[2]:23 chanx_left_in[2]:23 0.0003588029 +39 chanx_right_in[2]:23 chanx_left_in[2]:22 0.0001983926 +40 chanx_right_in[2]:17 chanx_left_in[2]:22 0.0001159708 +41 chanx_right_in[2] chanx_right_in[3] 1.880846e-05 +42 chanx_right_in[2]:28 chanx_right_in[3] 7.50887e-05 +43 chanx_right_in[2]:31 chanx_right_in[3]:14 1.880846e-05 +44 chanx_right_in[2]:26 chanx_right_in[3]:11 1.034352e-05 +45 chanx_right_in[2]:26 chanx_right_in[3]:14 0.0004617944 +46 chanx_right_in[2]:27 chanx_right_in[3] 0.0004617944 +47 chanx_right_in[2]:27 chanx_right_in[3]:12 1.034352e-05 +48 chanx_right_in[2]:27 chanx_right_in[3]:14 7.50887e-05 +49 chanx_right_in[2]:22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002864564 +50 chanx_right_in[2]:21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002864564 +51 chanx_right_in[2]:8 optlc_net_165:41 0.0002420248 +52 chanx_right_in[2]:8 optlc_net_165:23 1.35978e-05 +53 chanx_right_in[2]:8 optlc_net_165:42 0.0001577718 +54 chanx_right_in[2]:7 optlc_net_165:23 0.0001577718 +55 chanx_right_in[2]:7 optlc_net_165:9 1.35978e-05 +56 chanx_right_in[2]:7 optlc_net_165:42 0.0002420248 + +*RES +0 chanx_right_in[2] chanx_right_in[2]:31 0.0002365667 +1 chanx_right_in[2]:11 chanx_right_in[2]:10 0.0045 +2 chanx_right_in[2]:10 chanx_right_in[2]:9 0.0008303572 +3 chanx_right_in[2]:8 chanx_right_in[2]:7 0.01803125 +4 chanx_right_in[2]:9 chanx_right_in[2]:8 0.0045 +5 chanx_right_in[2]:5 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +6 chanx_right_in[2]:25 chanx_right_in[2]:24 0.00341 +7 chanx_right_in[2]:24 chanx_right_in[2]:23 0.007349624 +8 chanx_right_in[2]:28 chanx_right_in[2]:27 0.0007911666 +9 chanx_right_in[2]:29 chanx_right_in[2]:28 0.00341 +10 chanx_right_in[2]:31 chanx_right_in[2]:30 0.00341 +11 chanx_right_in[2]:30 chanx_right_in[2]:29 0.00031725 +12 chanx_right_in[2]:22 chanx_right_in[2]:21 0.002950425 +13 chanx_right_in[2]:23 chanx_right_in[2]:22 0.00341 +14 chanx_right_in[2]:23 chanx_right_in[2]:17 0.002555625 +15 chanx_right_in[2]:20 chanx_right_in[2]:19 0.0045 +16 chanx_right_in[2]:21 chanx_right_in[2]:20 0.00341 +17 chanx_right_in[2]:19 chanx_right_in[2]:18 0.0003370536 +18 chanx_right_in[2]:18 FTB_1__0:A 0.152 +19 chanx_right_in[2]:16 chanx_right_in[2]:15 0.00341 +20 chanx_right_in[2]:16 chanx_right_in[2]:4 5.69697e-05 +21 chanx_right_in[2]:17 chanx_right_in[2]:16 0.00341 +22 chanx_right_in[2]:15 chanx_right_in[2]:14 0.002640625 +23 chanx_right_in[2]:13 chanx_right_in[2]:12 0.00128125 +24 chanx_right_in[2]:14 chanx_right_in[2]:13 0.0045 +25 chanx_right_in[2]:12 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +26 chanx_right_in[2]:12 chanx_right_in[2]:11 0.001924107 +27 chanx_right_in[2]:7 chanx_right_in[2]:6 0.0009107143 +28 chanx_right_in[2]:6 chanx_right_in[2]:5 0.002841518 +29 chanx_right_in[2]:26 chanx_right_in[2]:25 0.007800433 +30 chanx_right_in[2]:27 chanx_right_in[2]:26 0.007833333 + +*END + +*D_NET chany_bottom_in[6] 0.007200609 //LENGTH 59.365 LUMPCC 0.0002993389 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 94.300 1.290 +*I mux_left_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 74.425 25.500 +*I mux_right_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 100.840 28.900 +*N chany_bottom_in[6]:3 *C 100.803 28.900 +*N chany_bottom_in[6]:4 *C 97.565 28.900 +*N chany_bottom_in[6]:5 *C 97.520 28.855 +*N chany_bottom_in[6]:6 *C 97.520 27.938 +*N chany_bottom_in[6]:7 *C 97.513 27.880 +*N chany_bottom_in[6]:8 *C 74.463 25.500 +*N chany_bottom_in[6]:9 *C 75.855 25.500 +*N chany_bottom_in[6]:10 *C 75.900 25.545 +*N chany_bottom_in[6]:11 *C 75.900 27.823 +*N chany_bottom_in[6]:12 *C 75.907 27.880 +*N chany_bottom_in[6]:13 *C 94.760 27.880 +*N chany_bottom_in[6]:14 *C 94.760 27.873 +*N chany_bottom_in[6]:15 *C 94.760 2.728 +*N chany_bottom_in[6]:16 *C 94.745 2.720 +*N chany_bottom_in[6]:17 *C 94.303 2.720 +*N chany_bottom_in[6]:18 *C 94.300 2.663 + +*CAP +0 chany_bottom_in[6] 8.642994e-05 +1 mux_left_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_32\/mux_l1_in_0_:A1 1e-06 +3 chany_bottom_in[6]:3 0.0002731333 +4 chany_bottom_in[6]:4 0.0002731333 +5 chany_bottom_in[6]:5 7.840633e-05 +6 chany_bottom_in[6]:6 7.840633e-05 +7 chany_bottom_in[6]:7 0.000107818 +8 chany_bottom_in[6]:8 0.0001568382 +9 chany_bottom_in[6]:9 0.0001568382 +10 chany_bottom_in[6]:10 0.0001757504 +11 chany_bottom_in[6]:11 0.0001757504 +12 chany_bottom_in[6]:12 0.00127666 +13 chany_bottom_in[6]:13 0.001384478 +14 chany_bottom_in[6]:14 0.001252205 +15 chany_bottom_in[6]:15 0.001252205 +16 chany_bottom_in[6]:16 4.239439e-05 +17 chany_bottom_in[6]:17 4.239439e-05 +18 chany_bottom_in[6]:18 8.642994e-05 +19 chany_bottom_in[6]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 7.710191e-05 +20 chany_bottom_in[6]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 7.256756e-05 +21 chany_bottom_in[6]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 7.710191e-05 +22 chany_bottom_in[6]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 7.256756e-05 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:18 0.001225446 +1 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.002033482 +2 chany_bottom_in[6]:12 chany_bottom_in[6]:11 0.00341 +3 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.001243304 +4 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.0045 +5 chany_bottom_in[6]:8 mux_left_track_1\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.0008191965 +7 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.00341 +8 chany_bottom_in[6]:4 chany_bottom_in[6]:3 0.002890625 +9 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.0045 +10 chany_bottom_in[6]:3 mux_right_track_32\/mux_l1_in_0_:A1 0.152 +11 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.002953558 +12 chany_bottom_in[6]:13 chany_bottom_in[6]:7 0.000431225 +13 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.00341 +14 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.00341 +15 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.003939383 +16 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.00341 +17 chany_bottom_in[6]:17 chany_bottom_in[6]:16 6.499219e-05 + +*END + +*D_NET chany_bottom_in[18] 0.01128115 //LENGTH 90.550 LUMPCC 0.0006548815 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 57.500 1.290 +*I mux_left_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 52.540 74.460 +*I mux_right_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 60.360 66.980 +*N chany_bottom_in[18]:3 *C 57.560 62.560 +*N chany_bottom_in[18]:4 *C 60.398 66.980 +*N chany_bottom_in[18]:5 *C 61.180 66.980 +*N chany_bottom_in[18]:6 *C 61.180 66.640 +*N chany_bottom_in[18]:7 *C 57.960 66.640 +*N chany_bottom_in[18]:8 *C 52.440 74.460 +*N chany_bottom_in[18]:9 *C 52.440 74.415 +*N chany_bottom_in[18]:10 *C 52.440 66.345 +*N chany_bottom_in[18]:11 *C 52.485 66.300 +*N chany_bottom_in[18]:12 *C 57.960 66.330 +*N chany_bottom_in[18]:13 *C 57.960 66.255 +*N chany_bottom_in[18]:14 *C 57.960 62.617 +*N chany_bottom_in[18]:15 *C 57.960 62.560 +*N chany_bottom_in[18]:16 *C 57.960 62.553 +*N chany_bottom_in[18]:17 *C 57.960 29.928 +*N chany_bottom_in[18]:18 *C 57.980 29.920 +*N chany_bottom_in[18]:19 *C 59.333 29.920 +*N chany_bottom_in[18]:20 *C 59.340 29.863 +*N chany_bottom_in[18]:21 *C 59.340 7.525 +*N chany_bottom_in[18]:22 *C 59.295 7.480 +*N chany_bottom_in[18]:23 *C 57.545 7.480 +*N chany_bottom_in[18]:24 *C 57.500 7.435 + +*CAP +0 chany_bottom_in[18] 0.0003397883 +1 mux_left_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_2\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[18]:3 9.954247e-05 +4 chany_bottom_in[18]:4 8.345018e-05 +5 chany_bottom_in[18]:5 0.0001077159 +6 chany_bottom_in[18]:6 0.0002018821 +7 chany_bottom_in[18]:7 0.0002052319 +8 chany_bottom_in[18]:8 3.150706e-05 +9 chany_bottom_in[18]:9 0.0004553342 +10 chany_bottom_in[18]:10 0.0004553342 +11 chany_bottom_in[18]:11 0.0004183255 +12 chany_bottom_in[18]:12 0.0004459409 +13 chany_bottom_in[18]:13 0.0002132974 +14 chany_bottom_in[18]:14 0.0002132974 +15 chany_bottom_in[18]:15 9.954247e-05 +16 chany_bottom_in[18]:16 0.002114438 +17 chany_bottom_in[18]:17 0.002114438 +18 chany_bottom_in[18]:18 0.0001756668 +19 chany_bottom_in[18]:19 0.0001756668 +20 chany_bottom_in[18]:20 0.00102619 +21 chany_bottom_in[18]:21 0.00102619 +22 chany_bottom_in[18]:22 0.0001408521 +23 chany_bottom_in[18]:23 0.0001408521 +24 chany_bottom_in[18]:24 0.0003397883 +25 chany_bottom_in[18]:20 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 3.517451e-05 +26 chany_bottom_in[18]:21 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 3.517451e-05 +27 chany_bottom_in[18]:20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002922663 +28 chany_bottom_in[18]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002922663 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:24 0.005486608 +1 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.0045 +2 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.007205358 +3 chany_bottom_in[18]:8 mux_left_track_25\/mux_l2_in_1_:A1 0.152 +4 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.0045 +5 chany_bottom_in[18]:4 mux_right_track_2\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.004888393 +7 chany_bottom_in[18]:12 chany_bottom_in[18]:7 0.0002767858 +8 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.0045 +9 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.003247768 +10 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.00341 +11 chany_bottom_in[18]:15 chany_bottom_in[18]:3 5.69697e-05 +12 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.00341 +13 chany_bottom_in[18]:18 chany_bottom_in[18]:17 0.00341 +14 chany_bottom_in[18]:17 chany_bottom_in[18]:16 0.00511125 +15 chany_bottom_in[18]:20 chany_bottom_in[18]:19 0.00341 +16 chany_bottom_in[18]:19 chany_bottom_in[18]:18 0.0002118917 +17 chany_bottom_in[18]:22 chany_bottom_in[18]:21 0.0045 +18 chany_bottom_in[18]:21 chany_bottom_in[18]:20 0.0199442 +19 chany_bottom_in[18]:23 chany_bottom_in[18]:22 0.0015625 +20 chany_bottom_in[18]:24 chany_bottom_in[18]:23 0.0045 +21 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.002875 +22 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.0003035715 +23 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.0006986608 + +*END + +*D_NET chanx_left_in[3] 0.004105549 //LENGTH 34.190 LUMPCC 0.0004148973 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 61.200 +*I mux_bottom_track_3\/mux_l1_in_2_:A0 I *L 0.001631 *C 13.975 42.500 +*N chanx_left_in[3]:2 *C 13.975 42.500 +*N chanx_left_in[3]:3 *C 13.800 41.480 +*N chanx_left_in[3]:4 *C 3.725 41.480 +*N chanx_left_in[3]:5 *C 3.680 41.525 +*N chanx_left_in[3]:6 *C 3.680 61.143 +*N chanx_left_in[3]:7 *C 3.673 61.200 + +*CAP +0 chanx_left_in[3] 0.0001734352 +1 mux_bottom_track_3\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[3]:2 9.559756e-05 +3 chanx_left_in[3]:3 0.0006677701 +4 chanx_left_in[3]:4 0.0006035383 +5 chanx_left_in[3]:5 0.0009879377 +6 chanx_left_in[3]:6 0.0009879377 +7 chanx_left_in[3]:7 0.0001734352 +8 chanx_left_in[3]:6 ropt_net_199:4 5.846145e-05 +9 chanx_left_in[3]:5 ropt_net_199:3 5.846145e-05 +10 chanx_left_in[3]:6 ropt_net_198:4 9.38438e-05 +11 chanx_left_in[3]:5 ropt_net_198:5 9.38438e-05 +12 chanx_left_in[3]:6 ropt_net_212:4 1.334191e-05 +13 chanx_left_in[3]:4 ropt_net_212:6 4.180149e-05 +14 chanx_left_in[3]:5 ropt_net_212:5 1.334191e-05 +15 chanx_left_in[3]:3 ropt_net_212:7 4.180149e-05 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:7 0.0003826583 +1 chanx_left_in[3]:6 chanx_left_in[3]:5 0.01751563 +2 chanx_left_in[3]:7 chanx_left_in[3]:6 0.00341 +3 chanx_left_in[3]:4 chanx_left_in[3]:3 0.008995536 +4 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0045 +5 chanx_left_in[3]:2 mux_bottom_track_3\/mux_l1_in_2_:A0 0.152 +6 chanx_left_in[3]:3 chanx_left_in[3]:2 0.0009107143 + +*END + +*D_NET chanx_right_out[0] 0.003000577 //LENGTH 22.985 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 120.580 75.140 +*P chanx_right_out[0] O *L 0.7423 *C 140.450 73.440 +*N chanx_right_out[0]:2 *C 138.920 73.440 +*N chanx_right_out[0]:3 *C 138.920 74.120 +*N chanx_right_out[0]:4 *C 136.168 74.120 +*N chanx_right_out[0]:5 *C 136.160 74.178 +*N chanx_right_out[0]:6 *C 136.160 75.095 +*N chanx_right_out[0]:7 *C 136.115 75.140 +*N chanx_right_out[0]:8 *C 120.618 75.140 + +*CAP +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[0] 0.0001044828 +2 chanx_right_out[0]:2 0.0001452125 +3 chanx_right_out[0]:3 0.0003725037 +4 chanx_right_out[0]:4 0.000331774 +5 chanx_right_out[0]:5 7.519806e-05 +6 chanx_right_out[0]:6 7.519806e-05 +7 chanx_right_out[0]:7 0.0009476037 +8 chanx_right_out[0]:8 0.0009476037 + +*RES +0 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[0]:8 0.152 +1 chanx_right_out[0]:8 chanx_right_out[0]:7 0.01383705 +2 chanx_right_out[0]:7 chanx_right_out[0]:6 0.0045 +3 chanx_right_out[0]:6 chanx_right_out[0]:5 0.0008191965 +4 chanx_right_out[0]:5 chanx_right_out[0]:4 0.00341 +5 chanx_right_out[0]:4 chanx_right_out[0]:3 0.000431225 +6 chanx_right_out[0]:3 chanx_right_out[0]:2 0.0001065333 +7 chanx_right_out[0]:2 chanx_right_out[0] 0.0002397 + +*END + +*D_NET ropt_net_180 0.001394329 //LENGTH 9.070 LUMPCC 0.0003954168 DR + +*CONN +*I mux_bottom_track_11\/BUFT_P_136:X O *L 0 *C 65.320 3.400 +*I ropt_mt_inst_800:A I *L 0.001767 *C 73.140 4.080 +*N ropt_net_180:2 *C 73.103 4.080 +*N ropt_net_180:3 *C 70.840 4.080 +*N ropt_net_180:4 *C 70.840 3.400 +*N ropt_net_180:5 *C 65.358 3.400 + +*CAP +0 mux_bottom_track_11\/BUFT_P_136:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_180:2 0.0001864375 +3 ropt_net_180:3 0.0002268829 +4 ropt_net_180:4 0.0003120186 +5 ropt_net_180:5 0.0002715732 +6 ropt_net_180:5 chany_bottom_out[19]:5 0.0001925453 +7 ropt_net_180:4 chany_bottom_out[19]:4 0.0001925453 +8 ropt_net_180:4 chany_bottom_out[19]:2 5.163111e-06 +9 ropt_net_180:3 chany_bottom_out[19]:3 5.163111e-06 + +*RES +0 mux_bottom_track_11\/BUFT_P_136:X ropt_net_180:5 0.152 +1 ropt_net_180:2 ropt_mt_inst_800:A 0.152 +2 ropt_net_180:5 ropt_net_180:4 0.004895089 +3 ropt_net_180:4 ropt_net_180:3 0.000607143 +4 ropt_net_180:3 ropt_net_180:2 0.002020089 + +*END + +*D_NET chany_bottom_out[19] 0.002039113 //LENGTH 13.725 LUMPCC 0.0003954168 DR + +*CONN +*I mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 60.720 4.080 +*P chany_bottom_out[19] O *L 0.7423 *C 70.840 1.325 +*N chany_bottom_out[19]:2 *C 70.380 1.360 +*N chany_bottom_out[19]:3 *C 70.380 3.695 +*N chany_bottom_out[19]:4 *C 70.335 3.740 +*N chany_bottom_out[19]:5 *C 62.560 3.740 +*N chany_bottom_out[19]:6 *C 62.560 4.080 +*N chany_bottom_out[19]:7 *C 60.758 4.080 + +*CAP +0 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[19] 3.631346e-05 +2 chany_bottom_out[19]:2 0.000213099 +3 chany_bottom_out[19]:3 0.0001767855 +4 chany_bottom_out[19]:4 0.00042962 +5 chany_bottom_out[19]:5 0.0004543523 +6 chany_bottom_out[19]:6 0.0001786291 +7 chany_bottom_out[19]:7 0.0001538967 +8 chany_bottom_out[19]:4 ropt_net_180:4 0.0001925453 +9 chany_bottom_out[19]:3 ropt_net_180:3 5.163111e-06 +10 chany_bottom_out[19]:5 ropt_net_180:5 0.0001925453 +11 chany_bottom_out[19]:2 ropt_net_180:4 5.163111e-06 + +*RES +0 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[19]:7 0.152 +1 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.001609375 +2 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.0045 +3 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.002084821 +4 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.0003035715 +5 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.006941964 +6 chany_bottom_out[19]:2 chany_bottom_out[19] 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.002413316 //LENGTH 18.335 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 95.985 20.740 +*I mux_bottom_track_31\/mux_l2_in_0_:S I *L 0.00357 *C 86.580 14.960 +*I mem_bottom_track_31\/FTB_30__55:A I *L 0.001746 *C 88.780 17.680 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 88.780 17.680 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 88.780 17.635 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 86.618 14.960 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 88.735 14.960 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 88.780 15.005 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 88.780 17.000 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 88.825 17.000 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 93.795 17.000 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 93.840 17.045 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 93.840 21.035 +*N mux_tree_tapbuf_size2_2_sram[1]:13 *C 93.885 21.080 +*N mux_tree_tapbuf_size2_2_sram[1]:14 *C 96.140 21.080 +*N mux_tree_tapbuf_size2_2_sram[1]:15 *C 95.985 20.740 + +*CAP +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_31\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_31\/FTB_30__55:A 1e-06 +3 mux_tree_tapbuf_size2_2_sram[1]:3 3.543145e-05 +4 mux_tree_tapbuf_size2_2_sram[1]:4 4.59819e-05 +5 mux_tree_tapbuf_size2_2_sram[1]:5 0.0001887756 +6 mux_tree_tapbuf_size2_2_sram[1]:6 0.0001887756 +7 mux_tree_tapbuf_size2_2_sram[1]:7 0.0001204288 +8 mux_tree_tapbuf_size2_2_sram[1]:8 0.0001987292 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.0003485905 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.0003485905 +11 mux_tree_tapbuf_size2_2_sram[1]:11 0.0002507689 +12 mux_tree_tapbuf_size2_2_sram[1]:12 0.0002507689 +13 mux_tree_tapbuf_size2_2_sram[1]:13 0.0001776201 +14 mux_tree_tapbuf_size2_2_sram[1]:14 0.0002027906 +15 mux_tree_tapbuf_size2_2_sram[1]:15 5.30643e-05 + +*RES +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:3 mem_bottom_track_31\/FTB_30__55:A 0.152 +2 mux_tree_tapbuf_size2_2_sram[1]:4 mux_tree_tapbuf_size2_2_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.00178125 +5 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:4 0.0005669643 +6 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.0044375 +7 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size2_2_sram[1]:13 mux_tree_tapbuf_size2_2_sram[1]:12 0.0045 +9 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 0.0035625 +10 mux_tree_tapbuf_size2_2_sram[1]:15 mux_tree_tapbuf_size2_2_sram[1]:14 0.0003035715 +11 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.001890625 +12 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.0045 +13 mux_tree_tapbuf_size2_2_sram[1]:5 mux_bottom_track_31\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size2_2_sram[1]:14 mux_tree_tapbuf_size2_2_sram[1]:13 0.002013393 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_6_ccff_tail[0] 0.0007186498 //LENGTH 5.420 LUMPCC 7.034903e-05 DR + +*CONN +*I mem_bottom_track_39\/FTB_34__59:X O *L 0 *C 58.585 12.920 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 56.295 15.300 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 *C 56.333 15.300 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 *C 58.375 15.300 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 *C 58.420 15.255 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 *C 58.420 12.965 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 *C 58.420 12.920 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 *C 58.585 12.920 + +*CAP +0 mem_bottom_track_39\/FTB_34__59:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.0001562121 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0001562121 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.0001123095 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0001123095 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 5.556242e-05 +7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 5.369535e-05 +8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chany_bottom_in[18]:20 3.517451e-05 +9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chany_bottom_in[18]:21 3.517451e-05 + +*RES +0 mem_bottom_track_39\/FTB_34__59:X mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.001823661 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 8.967391e-05 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_2_ccff_tail[0] 0.0008732895 //LENGTH 6.290 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_15\/FTB_15__40:X O *L 0 *C 43.465 19.720 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 46.635 17.340 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 *C 46.635 17.340 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 *C 46.460 17.340 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 *C 46.460 17.385 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 *C 46.460 19.675 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 *C 46.415 19.720 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 *C 43.503 19.720 + +*CAP +0 mem_bottom_track_15\/FTB_15__40:X 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 5.526045e-05 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 5.964949e-05 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.0001522415 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0001522415 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.0002259483 +7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.0002259483 + +*RES +0 mem_bottom_track_15\/FTB_15__40:X mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.002600446 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[0] 0.00249327 //LENGTH 20.115 LUMPCC 0.0002718076 DR + +*CONN +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 30.665 74.800 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 30.995 71.740 +*I mux_bottom_track_11\/mux_l1_in_0_:S I *L 0.00357 *C 35.540 61.880 +*N mux_tree_tapbuf_size4_1_sram[0]:3 *C 35.555 61.880 +*N mux_tree_tapbuf_size4_1_sram[0]:4 *C 35.858 61.880 +*N mux_tree_tapbuf_size4_1_sram[0]:5 *C 35.880 61.925 +*N mux_tree_tapbuf_size4_1_sram[0]:6 *C 35.880 71.355 +*N mux_tree_tapbuf_size4_1_sram[0]:7 *C 35.835 71.400 +*N mux_tree_tapbuf_size4_1_sram[0]:8 *C 30.820 71.400 +*N mux_tree_tapbuf_size4_1_sram[0]:9 *C 30.995 71.740 +*N mux_tree_tapbuf_size4_1_sram[0]:10 *C 30.820 71.740 +*N mux_tree_tapbuf_size4_1_sram[0]:11 *C 30.820 71.785 +*N mux_tree_tapbuf_size4_1_sram[0]:12 *C 30.820 74.755 +*N mux_tree_tapbuf_size4_1_sram[0]:13 *C 30.820 74.800 +*N mux_tree_tapbuf_size4_1_sram[0]:14 *C 30.665 74.800 + +*CAP +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_11\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_1_sram[0]:3 5.013597e-05 +4 mux_tree_tapbuf_size4_1_sram[0]:4 5.013597e-05 +5 mux_tree_tapbuf_size4_1_sram[0]:5 0.0004427219 +6 mux_tree_tapbuf_size4_1_sram[0]:6 0.0004427219 +7 mux_tree_tapbuf_size4_1_sram[0]:7 0.0003123653 +8 mux_tree_tapbuf_size4_1_sram[0]:8 0.0003305713 +9 mux_tree_tapbuf_size4_1_sram[0]:9 4.808558e-05 +10 mux_tree_tapbuf_size4_1_sram[0]:10 6.932388e-05 +11 mux_tree_tapbuf_size4_1_sram[0]:11 0.0001847004 +12 mux_tree_tapbuf_size4_1_sram[0]:12 0.0001847004 +13 mux_tree_tapbuf_size4_1_sram[0]:13 5.358008e-05 +14 mux_tree_tapbuf_size4_1_sram[0]:14 4.941988e-05 +15 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[1]:16 1.043313e-05 +16 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[1]:17 1.034932e-05 +17 mux_tree_tapbuf_size4_1_sram[0]:6 mux_tree_tapbuf_size4_1_sram[1]:10 6.597867e-05 +18 mux_tree_tapbuf_size4_1_sram[0]:6 mux_tree_tapbuf_size4_1_sram[1]:15 4.914269e-05 +19 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[1]:14 4.914269e-05 +20 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[1]:9 6.597867e-05 +21 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[1]:11 1.043313e-05 +22 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[1]:16 1.034932e-05 + +*RES +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_1_sram[0]:14 0.152 +1 mux_tree_tapbuf_size4_1_sram[0]:10 mux_tree_tapbuf_size4_1_sram[0]:9 9.51087e-05 +2 mux_tree_tapbuf_size4_1_sram[0]:10 mux_tree_tapbuf_size4_1_sram[0]:8 0.0003035714 +3 mux_tree_tapbuf_size4_1_sram[0]:11 mux_tree_tapbuf_size4_1_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size4_1_sram[0]:13 mux_tree_tapbuf_size4_1_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size4_1_sram[0]:12 mux_tree_tapbuf_size4_1_sram[0]:11 0.002651786 +6 mux_tree_tapbuf_size4_1_sram[0]:14 mux_tree_tapbuf_size4_1_sram[0]:13 8.423914e-05 +7 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[0]:6 0.0045 +8 mux_tree_tapbuf_size4_1_sram[0]:6 mux_tree_tapbuf_size4_1_sram[0]:5 0.008419643 +9 mux_tree_tapbuf_size4_1_sram[0]:4 mux_tree_tapbuf_size4_1_sram[0]:3 0.0001644022 +10 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[0]:4 0.0045 +11 mux_tree_tapbuf_size4_1_sram[0]:3 mux_bottom_track_11\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size4_1_sram[0]:9 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:7 0.004477679 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[2] 0.001065537 //LENGTH 9.070 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 114.385 44.540 +*I mux_right_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 116.740 41.820 +*I mem_right_track_24\/FTB_8__33:A I *L 0.001746 *C 117.300 39.440 +*N mux_tree_tapbuf_size5_2_sram[2]:3 *C 117.300 39.440 +*N mux_tree_tapbuf_size5_2_sram[2]:4 *C 117.300 39.485 +*N mux_tree_tapbuf_size5_2_sram[2]:5 *C 117.300 41.820 +*N mux_tree_tapbuf_size5_2_sram[2]:6 *C 116.740 41.820 +*N mux_tree_tapbuf_size5_2_sram[2]:7 *C 116.840 41.820 +*N mux_tree_tapbuf_size5_2_sram[2]:8 *C 116.840 44.495 +*N mux_tree_tapbuf_size5_2_sram[2]:9 *C 116.795 44.540 +*N mux_tree_tapbuf_size5_2_sram[2]:10 *C 114.422 44.540 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_24\/FTB_8__33:A 1e-06 +3 mux_tree_tapbuf_size5_2_sram[2]:3 3.215086e-05 +4 mux_tree_tapbuf_size5_2_sram[2]:4 0.0001500492 +5 mux_tree_tapbuf_size5_2_sram[2]:5 0.0001835122 +6 mux_tree_tapbuf_size5_2_sram[2]:6 2.764755e-05 +7 mux_tree_tapbuf_size5_2_sram[2]:7 0.0001964479 +8 mux_tree_tapbuf_size5_2_sram[2]:8 0.0001629849 +9 mux_tree_tapbuf_size5_2_sram[2]:9 0.0001548721 +10 mux_tree_tapbuf_size5_2_sram[2]:10 0.0001548721 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_2_sram[2]:10 0.152 +1 mux_tree_tapbuf_size5_2_sram[2]:6 mux_right_track_24\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[2]:5 0.0004107143 +4 mux_tree_tapbuf_size5_2_sram[2]:3 mem_right_track_24\/FTB_8__33:A 0.152 +5 mux_tree_tapbuf_size5_2_sram[2]:4 mux_tree_tapbuf_size5_2_sram[2]:3 0.0045 +6 mux_tree_tapbuf_size5_2_sram[2]:9 mux_tree_tapbuf_size5_2_sram[2]:8 0.0045 +7 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[2]:7 0.002388393 +8 mux_tree_tapbuf_size5_2_sram[2]:10 mux_tree_tapbuf_size5_2_sram[2]:9 0.002118304 +9 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[2]:4 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_2_ccff_tail[0] 0.001231733 //LENGTH 8.580 LUMPCC 0.0006312279 DR + +*CONN +*I mem_right_track_24\/FTB_8__33:X O *L 0 *C 114.305 39.440 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 109.195 37.060 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 *C 109.195 37.060 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 *C 109.020 37.060 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 *C 109.020 37.105 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 *C 109.020 39.395 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 *C 109.065 39.440 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 *C 114.268 39.440 + +*CAP +0 mem_right_track_24\/FTB_8__33:X 1e-06 +1 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 4.602052e-05 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 4.994655e-05 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.0001405339 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0001405339 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.0001107349 +7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.0001107349 +8 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 chanx_right_in[18]:17 0.0001037884 +9 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 chanx_right_in[18]:16 0.0001037884 +10 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 chanx_right_in[19]:3 0.0002118255 +11 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 chanx_right_in[19]:2 0.0002118255 + +*RES +0 mem_right_track_24\/FTB_8__33:X mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.00464509 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[1] 0.001997175 //LENGTH 17.285 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 102.885 53.040 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 109.195 49.980 +*I mux_right_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 107.080 55.760 +*I mux_right_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 111.320 52.870 +*N mux_tree_tapbuf_size6_2_sram[1]:4 *C 111.282 52.977 +*N mux_tree_tapbuf_size6_2_sram[1]:5 *C 107.118 55.760 +*N mux_tree_tapbuf_size6_2_sram[1]:6 *C 108.975 55.760 +*N mux_tree_tapbuf_size6_2_sram[1]:7 *C 109.020 55.715 +*N mux_tree_tapbuf_size6_2_sram[1]:8 *C 109.195 49.980 +*N mux_tree_tapbuf_size6_2_sram[1]:9 *C 109.020 49.980 +*N mux_tree_tapbuf_size6_2_sram[1]:10 *C 109.020 50.025 +*N mux_tree_tapbuf_size6_2_sram[1]:11 *C 109.020 53.040 +*N mux_tree_tapbuf_size6_2_sram[1]:12 *C 109.020 53.040 +*N mux_tree_tapbuf_size6_2_sram[1]:13 *C 102.922 53.040 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_8\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_8\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_2_sram[1]:4 0.000122253 +5 mux_tree_tapbuf_size6_2_sram[1]:5 0.0001668899 +6 mux_tree_tapbuf_size6_2_sram[1]:6 0.0001668899 +7 mux_tree_tapbuf_size6_2_sram[1]:7 0.0001419139 +8 mux_tree_tapbuf_size6_2_sram[1]:8 4.706564e-05 +9 mux_tree_tapbuf_size6_2_sram[1]:9 5.081253e-05 +10 mux_tree_tapbuf_size6_2_sram[1]:10 0.0001577599 +11 mux_tree_tapbuf_size6_2_sram[1]:11 0.0003301082 +12 mux_tree_tapbuf_size6_2_sram[1]:12 0.0004810377 +13 mux_tree_tapbuf_size6_2_sram[1]:13 0.0003284439 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_2_sram[1]:13 0.152 +1 mux_tree_tapbuf_size6_2_sram[1]:5 mux_right_track_8\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[1]:6 mux_tree_tapbuf_size6_2_sram[1]:5 0.001658482 +3 mux_tree_tapbuf_size6_2_sram[1]:7 mux_tree_tapbuf_size6_2_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size6_2_sram[1]:4 mux_right_track_8\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size6_2_sram[1]:9 mux_tree_tapbuf_size6_2_sram[1]:8 9.51087e-05 +6 mux_tree_tapbuf_size6_2_sram[1]:10 mux_tree_tapbuf_size6_2_sram[1]:9 0.0045 +7 mux_tree_tapbuf_size6_2_sram[1]:8 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size6_2_sram[1]:13 mux_tree_tapbuf_size6_2_sram[1]:12 0.005444197 +9 mux_tree_tapbuf_size6_2_sram[1]:12 mux_tree_tapbuf_size6_2_sram[1]:11 0.0045 +10 mux_tree_tapbuf_size6_2_sram[1]:12 mux_tree_tapbuf_size6_2_sram[1]:4 0.002020089 +11 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:10 0.002691964 +12 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:7 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[1] 0.002715585 //LENGTH 21.150 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 20.545 36.720 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 14.895 31.620 +*I mux_bottom_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 23.360 34.680 +*I mux_bottom_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 17.380 39.440 +*N mux_tree_tapbuf_size7_1_sram[1]:4 *C 17.418 39.440 +*N mux_tree_tapbuf_size7_1_sram[1]:5 *C 20.195 39.440 +*N mux_tree_tapbuf_size7_1_sram[1]:6 *C 20.240 39.395 +*N mux_tree_tapbuf_size7_1_sram[1]:7 *C 23.323 34.680 +*N mux_tree_tapbuf_size7_1_sram[1]:8 *C 14.895 31.620 +*N mux_tree_tapbuf_size7_1_sram[1]:9 *C 14.720 31.620 +*N mux_tree_tapbuf_size7_1_sram[1]:10 *C 14.720 31.665 +*N mux_tree_tapbuf_size7_1_sram[1]:11 *C 14.720 34.635 +*N mux_tree_tapbuf_size7_1_sram[1]:12 *C 14.765 34.680 +*N mux_tree_tapbuf_size7_1_sram[1]:13 *C 20.240 34.680 +*N mux_tree_tapbuf_size7_1_sram[1]:14 *C 20.240 34.725 +*N mux_tree_tapbuf_size7_1_sram[1]:15 *C 20.240 36.720 +*N mux_tree_tapbuf_size7_1_sram[1]:16 *C 20.240 36.720 +*N mux_tree_tapbuf_size7_1_sram[1]:17 *C 20.545 36.720 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_3\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_track_3\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_1_sram[1]:4 0.0002052912 +5 mux_tree_tapbuf_size7_1_sram[1]:5 0.0002052912 +6 mux_tree_tapbuf_size7_1_sram[1]:6 0.0001424113 +7 mux_tree_tapbuf_size7_1_sram[1]:7 0.0002162524 +8 mux_tree_tapbuf_size7_1_sram[1]:8 6.21484e-05 +9 mux_tree_tapbuf_size7_1_sram[1]:9 5.855652e-05 +10 mux_tree_tapbuf_size7_1_sram[1]:10 0.0001782415 +11 mux_tree_tapbuf_size7_1_sram[1]:11 0.0001782415 +12 mux_tree_tapbuf_size7_1_sram[1]:12 0.0003518173 +13 mux_tree_tapbuf_size7_1_sram[1]:13 0.0005989767 +14 mux_tree_tapbuf_size7_1_sram[1]:14 0.0001128814 +15 mux_tree_tapbuf_size7_1_sram[1]:15 0.0002857062 +16 mux_tree_tapbuf_size7_1_sram[1]:16 5.818324e-05 +17 mux_tree_tapbuf_size7_1_sram[1]:17 5.758581e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_1_sram[1]:17 0.152 +1 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:12 0.004888393 +2 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:7 0.002752232 +3 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size7_1_sram[1]:5 mux_tree_tapbuf_size7_1_sram[1]:4 0.002479911 +5 mux_tree_tapbuf_size7_1_sram[1]:6 mux_tree_tapbuf_size7_1_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size7_1_sram[1]:4 mux_bottom_track_3\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size7_1_sram[1]:7 mux_bottom_track_3\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_1_sram[1]:12 mux_tree_tapbuf_size7_1_sram[1]:11 0.0045 +9 mux_tree_tapbuf_size7_1_sram[1]:11 mux_tree_tapbuf_size7_1_sram[1]:10 0.002651786 +10 mux_tree_tapbuf_size7_1_sram[1]:9 mux_tree_tapbuf_size7_1_sram[1]:8 9.51087e-05 +11 mux_tree_tapbuf_size7_1_sram[1]:10 mux_tree_tapbuf_size7_1_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size7_1_sram[1]:8 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size7_1_sram[1]:16 mux_tree_tapbuf_size7_1_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:14 0.00178125 +15 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:6 0.002388393 +16 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:16 0.0001657609 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0026841 //LENGTH 19.250 LUMPCC 0.0007703042 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_0_:X O *L 0 *C 96.425 61.880 +*I mux_right_track_4\/mux_l3_in_0_:A1 I *L 0.001811 *C 113.385 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 113.348 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 106.305 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 106.260 60.565 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 106.260 61.835 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 106.215 61.880 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 96.463 61.880 + +*CAP +0 mux_right_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002963363 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002963363 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.887237e-05 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.887237e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005706893 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0005706893 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_1_sram[1]:4 7.488178e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_1_sram[1]:5 7.488178e-05 +10 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000285183 +11 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000285183 +12 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.50873e-05 +13 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.50873e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.006287947 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001133929 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00870759 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004238263 //LENGTH 3.320 LUMPCC 9.573666e-05 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 58.135 52.700 +*I mux_left_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 55.105 52.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 55.143 52.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 58.098 52.700 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001630448 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001630448 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size6_4_sram[0]:24 4.786833e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_4_sram[0]:23 4.786833e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002638393 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0002875119 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_1_:X O *L 0 *C 89.985 53.380 +*I mux_right_track_16\/mux_l3_in_0_:A0 I *L 0.001631 *C 92.175 53.380 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 92.138 53.380 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 90.023 53.380 + +*CAP +0 mux_right_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001427559 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001427559 + +*RES +0 mux_right_track_16\/mux_l2_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001888393 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005767964 //LENGTH 4.180 LUMPCC 0.0001163046 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_0_:X O *L 0 *C 75.270 40.120 +*I mux_left_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 75.900 41.820 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.938 41.820 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 76.315 41.820 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 76.360 41.775 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 76.360 40.165 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 76.315 40.120 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 75.308 40.120 + +*CAP +0 mux_left_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.293555e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.293555e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.312963e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.312963e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.31807e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.31807e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size5_4_sram[0]:6 5.138848e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size5_4_sram[0]:9 4.970014e-06 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size5_4_sram[0]:11 1.7938e-06 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size5_4_sram[0]:14 5.138848e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size5_4_sram[0]:12 1.7938e-06 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size5_4_sram[0]:13 4.970014e-06 + +*RES +0 mux_left_track_3\/mux_l1_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370536 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0008995536 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001000987 //LENGTH 8.040 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_1_:X O *L 0 *C 54.105 75.480 +*I mux_left_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 53.650 82.620 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 53.650 82.620 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 53.820 82.620 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 53.820 82.575 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 53.820 75.525 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 53.820 75.480 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 54.105 75.480 + +*CAP +0 mux_left_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.802783e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.455106e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003891782 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003891782 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.878096e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.927072e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.23913e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006294644 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001674462 //LENGTH 12.590 LUMPCC 0.0004551251 DR + +*CONN +*I mux_bottom_track_21\/mux_l1_in_1_:X O *L 0 *C 81.245 30.600 +*I mux_bottom_track_21\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.815 22.780 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 84.778 22.780 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.005 22.780 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 80.960 22.825 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 80.960 30.555 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 80.960 30.600 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.245 30.600 + +*CAP +0 mux_bottom_track_21\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_21\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002152715 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002152715 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003403574 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003403574 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.423755e-05 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.184142e-05 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_right_in[16]:29 7.206848e-09 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_right_in[16]:30 7.206848e-09 +10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[16]:31 5.403802e-05 +11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[16]:32 5.403802e-05 +12 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_40_[0]:10 3.078072e-05 +13 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_40_[0]:11 6.625681e-05 +14 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_40_[0]:7 6.625681e-05 +15 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_40_[0]:11 3.078072e-05 +16 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.782421e-06 +17 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.369739e-05 +18 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.782421e-06 +19 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.369739e-05 + +*RES +0 mux_bottom_track_21\/mux_l1_in_1_:X mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_21\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003368304 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009987322 //LENGTH 6.940 LUMPCC 0.0003444576 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_2_:X O *L 0 *C 32.025 42.500 +*I mux_bottom_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 33.580 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 33.580 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 33.580 47.215 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 33.580 42.545 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 33.535 42.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 32.062 42.500 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.575143e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002303484 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002303484 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.79132e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.79132e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 bottom_left_grid_pin_35_[0]:14 7.704025e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 bottom_left_grid_pin_35_[0]:13 7.704025e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:20 4.994576e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:21 4.994576e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:26 4.681081e-07 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:22 4.681081e-07 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.468864e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.468864e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.008603e-05 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.008603e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001314732 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.004169643 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A1 0.152 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET optlc_net_168 0.01092015 //LENGTH 88.287 LUMPCC 0.0005217012 DR + +*CONN +*I optlc_161:HI O *L 0 *C 28.980 66.300 +*I mux_bottom_track_7\/mux_l1_in_3_:A0 I *L 0.001631 *C 16.735 55.080 +*I mux_bottom_track_3\/mux_l1_in_3_:A0 I *L 0.001631 *C 13.975 48.280 +*I mux_bottom_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 13.975 69.700 +*I mux_bottom_track_5\/mux_l1_in_3_:A0 I *L 0.001631 *C 28.695 55.080 +*I mux_bottom_track_11\/mux_l2_in_1_:A0 I *L 0.001631 *C 36.975 75.480 +*I mux_left_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 43.530 76.840 +*I mux_left_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 52.155 75.140 +*N optlc_net_168:8 *C 52.117 75.140 +*N optlc_net_168:9 *C 42.320 75.140 +*N optlc_net_168:10 *C 43.492 76.840 +*N optlc_net_168:11 *C 42.365 76.840 +*N optlc_net_168:12 *C 42.320 76.795 +*N optlc_net_168:13 *C 42.320 75.525 +*N optlc_net_168:14 *C 42.320 75.450 +*N optlc_net_168:15 *C 37.013 75.480 +*N optlc_net_168:16 *C 36.800 75.480 +*N optlc_net_168:17 *C 36.800 75.435 +*N optlc_net_168:18 *C 36.800 66.685 +*N optlc_net_168:19 *C 36.755 66.640 +*N optlc_net_168:20 *C 28.658 55.080 +*N optlc_net_168:21 *C 14.013 69.700 +*N optlc_net_168:22 *C 14.675 69.700 +*N optlc_net_168:23 *C 14.720 69.655 +*N optlc_net_168:24 *C 14.013 48.280 +*N optlc_net_168:25 *C 14.675 48.280 +*N optlc_net_168:26 *C 14.720 48.325 +*N optlc_net_168:27 *C 14.720 55.080 +*N optlc_net_168:28 *C 14.765 55.080 +*N optlc_net_168:29 *C 16.735 55.080 +*N optlc_net_168:30 *C 28.060 55.080 +*N optlc_net_168:31 *C 28.060 55.125 +*N optlc_net_168:32 *C 28.060 66.595 +*N optlc_net_168:33 *C 28.105 66.640 +*N optlc_net_168:34 *C 28.980 66.640 +*N optlc_net_168:35 *C 28.980 66.300 + +*CAP +0 optlc_161:HI 1e-06 +1 mux_bottom_track_7\/mux_l1_in_3_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_3_:A0 1e-06 +3 mux_bottom_track_9\/mux_l2_in_1_:A0 1e-06 +4 mux_bottom_track_5\/mux_l1_in_3_:A0 1e-06 +5 mux_bottom_track_11\/mux_l2_in_1_:A0 1e-06 +6 mux_left_track_17\/mux_l2_in_1_:A0 1e-06 +7 mux_left_track_25\/mux_l2_in_1_:A0 1e-06 +8 optlc_net_168:8 0.0005839409 +9 optlc_net_168:9 0.0006156254 +10 optlc_net_168:10 0.0001249027 +11 optlc_net_168:11 0.0001249027 +12 optlc_net_168:12 9.555101e-05 +13 optlc_net_168:13 9.555101e-05 +14 optlc_net_168:14 0.0004055138 +15 optlc_net_168:15 0.0003953092 +16 optlc_net_168:16 5.503718e-05 +17 optlc_net_168:17 0.000578939 +18 optlc_net_168:18 0.000578939 +19 optlc_net_168:19 0.0004323517 +20 optlc_net_168:20 5.192759e-05 +21 optlc_net_168:21 6.33357e-05 +22 optlc_net_168:22 6.33357e-05 +23 optlc_net_168:23 0.000667138 +24 optlc_net_168:24 6.599891e-05 +25 optlc_net_168:25 6.599891e-05 +26 optlc_net_168:26 0.0003324749 +27 optlc_net_168:27 0.001032968 +28 optlc_net_168:28 0.000144833 +29 optlc_net_168:29 0.0009232191 +30 optlc_net_168:30 0.0008375735 +31 optlc_net_168:31 0.0007063593 +32 optlc_net_168:32 0.0007063593 +33 optlc_net_168:33 6.25402e-05 +34 optlc_net_168:34 0.0005228329 +35 optlc_net_168:35 5.698547e-05 +36 optlc_net_168:19 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.77887e-05 +37 optlc_net_168:34 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.77887e-05 +38 optlc_net_168:27 BUF_net_76:8 0.0001106707 +39 optlc_net_168:27 BUF_net_76:7 5.239118e-05 +40 optlc_net_168:26 BUF_net_76:8 5.239118e-05 +41 optlc_net_168:23 BUF_net_76:7 0.0001106707 + +*RES +0 optlc_161:HI optlc_net_168:35 0.152 +1 optlc_net_168:8 mux_left_track_25\/mux_l2_in_1_:A0 0.152 +2 optlc_net_168:16 optlc_net_168:15 0.0001154891 +3 optlc_net_168:17 optlc_net_168:16 0.0045 +4 optlc_net_168:19 optlc_net_168:18 0.0045 +5 optlc_net_168:18 optlc_net_168:17 0.0078125 +6 optlc_net_168:28 optlc_net_168:27 0.0045 +7 optlc_net_168:27 optlc_net_168:26 0.006031251 +8 optlc_net_168:27 optlc_net_168:23 0.01301339 +9 optlc_net_168:30 optlc_net_168:29 0.01011161 +10 optlc_net_168:30 optlc_net_168:20 0.0005334822 +11 optlc_net_168:31 optlc_net_168:30 0.0045 +12 optlc_net_168:33 optlc_net_168:32 0.0045 +13 optlc_net_168:32 optlc_net_168:31 0.01024107 +14 optlc_net_168:29 mux_bottom_track_7\/mux_l1_in_3_:A0 0.152 +15 optlc_net_168:29 optlc_net_168:28 0.001758929 +16 optlc_net_168:14 optlc_net_168:13 0.0045 +17 optlc_net_168:14 optlc_net_168:9 0.0002767857 +18 optlc_net_168:13 optlc_net_168:12 0.001133929 +19 optlc_net_168:11 optlc_net_168:10 0.001006696 +20 optlc_net_168:12 optlc_net_168:11 0.0045 +21 optlc_net_168:10 mux_left_track_17\/mux_l2_in_1_:A0 0.152 +22 optlc_net_168:20 mux_bottom_track_5\/mux_l1_in_3_:A0 0.152 +23 optlc_net_168:25 optlc_net_168:24 0.0005915179 +24 optlc_net_168:26 optlc_net_168:25 0.0045 +25 optlc_net_168:24 mux_bottom_track_3\/mux_l1_in_3_:A0 0.152 +26 optlc_net_168:15 mux_bottom_track_11\/mux_l2_in_1_:A0 0.152 +27 optlc_net_168:15 optlc_net_168:14 0.004738839 +28 optlc_net_168:22 optlc_net_168:21 0.0005915179 +29 optlc_net_168:23 optlc_net_168:22 0.0045 +30 optlc_net_168:21 mux_bottom_track_9\/mux_l2_in_1_:A0 0.152 +31 optlc_net_168:35 optlc_net_168:34 0.0003035715 +32 optlc_net_168:34 optlc_net_168:33 0.00078125 +33 optlc_net_168:34 optlc_net_168:19 0.006941965 +34 optlc_net_168:9 optlc_net_168:8 0.008747769 + +*END + +*D_NET mem_left_track_33/net_net_97 0.0004002235 //LENGTH 3.655 LUMPCC 0 DR + +*CONN +*I mem_left_track_33\/BUFT_RR_98:X O *L 0 *C 14.405 77.520 +*I mem_left_track_33\/BUFT_RR_148:A I *L 0.001746 *C 11.040 77.520 +*N mem_left_track_33/net_net_97:2 *C 11.078 77.520 +*N mem_left_track_33/net_net_97:3 *C 14.368 77.520 + +*CAP +0 mem_left_track_33\/BUFT_RR_98:X 1e-06 +1 mem_left_track_33\/BUFT_RR_148:A 1e-06 +2 mem_left_track_33/net_net_97:2 0.0001991118 +3 mem_left_track_33/net_net_97:3 0.0001991118 + +*RES +0 mem_left_track_33\/BUFT_RR_98:X mem_left_track_33/net_net_97:3 0.152 +1 mem_left_track_33/net_net_97:2 mem_left_track_33\/BUFT_RR_148:A 0.152 +2 mem_left_track_33/net_net_97:3 mem_left_track_33/net_net_97:2 0.0029375 + +*END + +*D_NET chanx_right_in[4] 0.02284166 //LENGTH 148.735 LUMPCC 0.01198414 DR + +*CONN +*P chanx_right_in[4] I *L 0.29796 *C 140.450 34.000 +*I mux_left_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.820 39.780 +*I mux_bottom_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 27.600 36.380 +*I BUFT_RR_76:A I *L 0.001776 *C 17.940 50.320 +*N chanx_right_in[4]:4 *C 17.902 50.320 +*N chanx_right_in[4]:5 *C 17.065 50.320 +*N chanx_right_in[4]:6 *C 17.020 50.275 +*N chanx_right_in[4]:7 *C 17.020 37.458 +*N chanx_right_in[4]:8 *C 17.027 37.400 +*N chanx_right_in[4]:9 *C 27.638 36.380 +*N chanx_right_in[4]:10 *C 28.060 36.380 +*N chanx_right_in[4]:11 *C 28.060 36.720 +*N chanx_right_in[4]:12 *C 28.475 36.720 +*N chanx_right_in[4]:13 *C 28.520 36.765 +*N chanx_right_in[4]:14 *C 28.520 37.343 +*N chanx_right_in[4]:15 *C 28.520 37.400 +*N chanx_right_in[4]:16 *C 76.820 39.795 +*N chanx_right_in[4]:17 *C 76.820 40.120 +*N chanx_right_in[4]:18 *C 76.820 40.075 +*N chanx_right_in[4]:19 *C 76.820 37.458 +*N chanx_right_in[4]:20 *C 76.820 37.400 +*N chanx_right_in[4]:21 *C 126.820 37.400 +*N chanx_right_in[4]:22 *C 137.073 37.400 +*N chanx_right_in[4]:23 *C 137.080 37.343 +*N chanx_right_in[4]:24 *C 137.080 34.058 +*N chanx_right_in[4]:25 *C 137.088 34.000 + +*CAP +0 chanx_right_in[4] 0.0001489759 +1 mux_left_track_3\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:A1 1e-06 +3 BUFT_RR_76:A 1e-06 +4 chanx_right_in[4]:4 6.985923e-05 +5 chanx_right_in[4]:5 6.985923e-05 +6 chanx_right_in[4]:6 0.0006314211 +7 chanx_right_in[4]:7 0.0006314211 +8 chanx_right_in[4]:8 0.0002629642 +9 chanx_right_in[4]:9 4.602538e-05 +10 chanx_right_in[4]:10 7.14602e-05 +11 chanx_right_in[4]:11 7.789529e-05 +12 chanx_right_in[4]:12 5.246047e-05 +13 chanx_right_in[4]:13 6.566715e-05 +14 chanx_right_in[4]:14 6.566715e-05 +15 chanx_right_in[4]:15 0.002287311 +16 chanx_right_in[4]:16 3.732233e-05 +17 chanx_right_in[4]:17 7.183444e-05 +18 chanx_right_in[4]:18 0.0001734807 +19 chanx_right_in[4]:19 0.0001734807 +20 chanx_right_in[4]:20 0.003471597 +21 chanx_right_in[4]:21 0.001715047 +22 chanx_right_in[4]:22 0.0002677965 +23 chanx_right_in[4]:23 0.000156999 +24 chanx_right_in[4]:24 0.000156999 +25 chanx_right_in[4]:25 0.0001489759 +26 chanx_right_in[4] chanx_right_in[9] 4.670518e-05 +27 chanx_right_in[4] chanx_right_in[9]:33 2.059013e-05 +28 chanx_right_in[4]:23 chanx_right_in[9]:33 7.337816e-06 +29 chanx_right_in[4]:22 chanx_right_in[9]:33 0.0002289551 +30 chanx_right_in[4]:24 chanx_right_in[9]:34 7.337816e-06 +31 chanx_right_in[4]:25 chanx_right_in[9]:32 2.059013e-05 +32 chanx_right_in[4]:25 chanx_right_in[9]:34 4.670518e-05 +33 chanx_right_in[4]:20 chanx_right_in[9]:32 2.830853e-05 +34 chanx_right_in[4]:21 chanx_right_in[9]:32 0.0002289551 +35 chanx_right_in[4]:21 chanx_right_in[9]:33 2.830853e-05 +36 chanx_right_in[4] chanx_right_in[13] 5.583568e-06 +37 chanx_right_in[4]:23 chanx_right_in[13]:33 1.526502e-05 +38 chanx_right_in[4]:22 chanx_right_in[13]:33 0.0002462053 +39 chanx_right_in[4]:22 chanx_right_in[13]:32 1.179522e-05 +40 chanx_right_in[4]:24 chanx_right_in[13]:34 1.526502e-05 +41 chanx_right_in[4]:25 chanx_right_in[13]:34 5.583568e-06 +42 chanx_right_in[4]:20 chanx_right_in[13]:27 8.285849e-06 +43 chanx_right_in[4]:20 chanx_right_in[13]:26 1.533721e-05 +44 chanx_right_in[4]:20 chanx_right_in[13]:31 0.001576298 +45 chanx_right_in[4]:15 chanx_right_in[13]:27 0.0004878245 +46 chanx_right_in[4]:15 chanx_right_in[13]:25 1.533721e-05 +47 chanx_right_in[4]:21 chanx_right_in[13]:31 2.008107e-05 +48 chanx_right_in[4]:21 chanx_right_in[13]:32 0.001334679 +49 chanx_right_in[4]:8 chanx_left_in[10] 0.0006607591 +50 chanx_right_in[4]:20 chanx_left_in[10]:20 0.0001230128 +51 chanx_right_in[4]:20 chanx_left_in[10]:40 1.963539e-05 +52 chanx_right_in[4]:20 chanx_left_in[10]:35 7.630202e-06 +53 chanx_right_in[4]:20 chanx_left_in[10]:33 5.091661e-06 +54 chanx_right_in[4]:20 chanx_left_in[10]:47 0.0006547585 +55 chanx_right_in[4]:20 chanx_left_in[10]:15 0.0007492996 +56 chanx_right_in[4]:15 chanx_left_in[10] 0.0006547585 +57 chanx_right_in[4]:15 chanx_left_in[10]:41 1.963539e-05 +58 chanx_right_in[4]:15 chanx_left_in[10]:47 0.0006607591 +59 chanx_right_in[4]:21 chanx_left_in[10]:14 0.0007492996 +60 chanx_right_in[4]:21 chanx_left_in[10]:19 0.0001230128 +61 chanx_right_in[4]:21 chanx_left_in[10]:34 7.630202e-06 +62 chanx_right_in[4]:21 chanx_left_in[10]:32 5.091661e-06 +63 chanx_right_in[4]:8 chanx_left_in[18]:22 0.0001374466 +64 chanx_right_in[4]:20 chanx_left_in[18]:21 0.0001548962 +65 chanx_right_in[4]:15 chanx_left_in[18]:22 0.0001548962 +66 chanx_right_in[4]:15 chanx_left_in[18]:21 0.0001374466 +67 chanx_right_in[4]:20 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.0004920504 +68 chanx_right_in[4]:20 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.0006411636 +69 chanx_right_in[4]:15 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.0005289104 +70 chanx_right_in[4]:21 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 0.0001122532 +71 chanx_right_in[4]:21 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.0004920504 +72 chanx_right_in[4]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.15292e-05 +73 chanx_right_in[4]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.15292e-05 +74 chanx_right_in[4]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.413111e-05 +75 chanx_right_in[4]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.413111e-05 + +*RES +0 chanx_right_in[4] chanx_right_in[4]:25 0.0005267917 +1 chanx_right_in[4]:4 BUFT_RR_76:A 0.152 +2 chanx_right_in[4]:5 chanx_right_in[4]:4 0.0007477679 +3 chanx_right_in[4]:6 chanx_right_in[4]:5 0.0045 +4 chanx_right_in[4]:7 chanx_right_in[4]:6 0.0114442 +5 chanx_right_in[4]:8 chanx_right_in[4]:7 0.00341 +6 chanx_right_in[4]:23 chanx_right_in[4]:22 0.00341 +7 chanx_right_in[4]:22 chanx_right_in[4]:21 0.001606225 +8 chanx_right_in[4]:24 chanx_right_in[4]:23 0.002933036 +9 chanx_right_in[4]:25 chanx_right_in[4]:24 0.00341 +10 chanx_right_in[4]:19 chanx_right_in[4]:18 0.002337054 +11 chanx_right_in[4]:20 chanx_right_in[4]:19 0.00341 +12 chanx_right_in[4]:20 chanx_right_in[4]:15 0.007566999 +13 chanx_right_in[4]:17 chanx_right_in[4]:16 0.0001766305 +14 chanx_right_in[4]:18 chanx_right_in[4]:17 0.0045 +15 chanx_right_in[4]:16 mux_left_track_3\/mux_l1_in_0_:A1 0.152 +16 chanx_right_in[4]:14 chanx_right_in[4]:13 0.000515625 +17 chanx_right_in[4]:15 chanx_right_in[4]:14 0.00341 +18 chanx_right_in[4]:15 chanx_right_in[4]:8 0.001800491 +19 chanx_right_in[4]:12 chanx_right_in[4]:11 0.0003705357 +20 chanx_right_in[4]:13 chanx_right_in[4]:12 0.0045 +21 chanx_right_in[4]:9 mux_bottom_track_3\/mux_l1_in_0_:A1 0.152 +22 chanx_right_in[4]:10 chanx_right_in[4]:9 0.0003772322 +23 chanx_right_in[4]:11 chanx_right_in[4]:10 0.0003035715 +24 chanx_right_in[4]:21 chanx_right_in[4]:20 0.007833333 + +*END + +*D_NET chanx_right_in[19] 0.007774352 //LENGTH 69.355 LUMPCC 0.000423651 DR + +*CONN +*P chanx_right_in[19] I *L 0.29796 *C 140.450 72.080 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 105.170 39.100 +*N chanx_right_in[19]:2 *C 105.208 39.100 +*N chanx_right_in[19]:3 *C 128.755 39.100 +*N chanx_right_in[19]:4 *C 128.800 39.145 +*N chanx_right_in[19]:5 *C 128.800 58.820 +*N chanx_right_in[19]:6 *C 129.260 58.820 +*N chanx_right_in[19]:7 *C 129.260 72.023 +*N chanx_right_in[19]:8 *C 129.268 72.080 + +*CAP +0 chanx_right_in[19] 0.0007315485 +1 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +2 chanx_right_in[19]:2 0.001231841 +3 chanx_right_in[19]:3 0.001231841 +4 chanx_right_in[19]:4 0.0009827366 +5 chanx_right_in[19]:5 0.001011862 +6 chanx_right_in[19]:6 0.0007287247 +7 chanx_right_in[19]:7 0.0006995992 +8 chanx_right_in[19]:8 0.0007315485 +9 chanx_right_in[19]:2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.0002118255 +10 chanx_right_in[19]:3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.0002118255 + +*RES +0 chanx_right_in[19] chanx_right_in[19]:8 0.001751925 +1 chanx_right_in[19]:2 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +2 chanx_right_in[19]:3 chanx_right_in[19]:2 0.02102455 +3 chanx_right_in[19]:4 chanx_right_in[19]:3 0.0045 +4 chanx_right_in[19]:7 chanx_right_in[19]:6 0.01178795 +5 chanx_right_in[19]:8 chanx_right_in[19]:7 0.00341 +6 chanx_right_in[19]:5 chanx_right_in[19]:4 0.01756697 +7 chanx_right_in[19]:6 chanx_right_in[19]:5 0.0004107143 + +*END + +*D_NET chany_bottom_in[5] 0.01211689 //LENGTH 102.745 LUMPCC 0.001413497 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 75.900 1.290 +*I mux_right_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 86.655 86.020 +*I mux_left_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.170 87.720 +*N chany_bottom_in[5]:3 *C 82.170 87.720 +*N chany_bottom_in[5]:4 *C 81.880 87.720 +*N chany_bottom_in[5]:5 *C 81.880 87.675 +*N chany_bottom_in[5]:6 *C 86.618 86.020 +*N chany_bottom_in[5]:7 *C 81.925 86.020 +*N chany_bottom_in[5]:8 *C 81.880 86.065 +*N chany_bottom_in[5]:9 *C 81.880 87.040 +*N chany_bottom_in[5]:10 *C 81.873 87.040 +*N chany_bottom_in[5]:11 *C 75.460 87.040 +*N chany_bottom_in[5]:12 *C 75.440 87.032 +*N chany_bottom_in[5]:13 *C 75.440 65.288 +*N chany_bottom_in[5]:14 *C 75.455 65.280 +*N chany_bottom_in[5]:15 *C 75.898 65.280 +*N chany_bottom_in[5]:16 *C 75.900 65.222 +*N chany_bottom_in[5]:17 *C 75.900 46.920 +*N chany_bottom_in[5]:18 *C 75.440 46.920 +*N chany_bottom_in[5]:19 *C 75.440 23.800 +*N chany_bottom_in[5]:20 *C 75.900 23.800 + +*CAP +0 chany_bottom_in[5] 0.001200006 +1 mux_right_track_0\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_33\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[5]:3 5.037697e-05 +4 chany_bottom_in[5]:4 5.018845e-05 +5 chany_bottom_in[5]:5 4.208326e-05 +6 chany_bottom_in[5]:6 0.0003019664 +7 chany_bottom_in[5]:7 0.0003019664 +8 chany_bottom_in[5]:8 5.911696e-05 +9 chany_bottom_in[5]:9 0.0001338098 +10 chany_bottom_in[5]:10 0.0003487749 +11 chany_bottom_in[5]:11 0.0003487749 +12 chany_bottom_in[5]:12 0.001214924 +13 chany_bottom_in[5]:13 0.001214924 +14 chany_bottom_in[5]:14 7.94189e-05 +15 chany_bottom_in[5]:15 7.94189e-05 +16 chany_bottom_in[5]:16 0.0007628857 +17 chany_bottom_in[5]:17 0.0007803231 +18 chany_bottom_in[5]:18 0.001243958 +19 chany_bottom_in[5]:19 0.001257496 +20 chany_bottom_in[5]:20 0.001230982 +21 chany_bottom_in[5] mux_tree_tapbuf_size2_3_sram[0]:6 0.0001670132 +22 chany_bottom_in[5]:20 mux_tree_tapbuf_size2_3_sram[0]:5 0.0001670132 +23 chany_bottom_in[5]:19 mux_tree_tapbuf_size5_4_sram[0]:15 4.167219e-05 +24 chany_bottom_in[5]:19 mux_tree_tapbuf_size5_4_sram[0]:14 0.0001309667 +25 chany_bottom_in[5]:18 mux_tree_tapbuf_size5_4_sram[0]:14 4.167219e-05 +26 chany_bottom_in[5]:18 mux_tree_tapbuf_size5_4_sram[0]:6 0.0001309667 +27 chany_bottom_in[5]:18 mux_tree_tapbuf_size5_4_sram[0]:4 1.144375e-05 +28 chany_bottom_in[5]:17 mux_tree_tapbuf_size5_4_sram[0]:5 1.144375e-05 +29 chany_bottom_in[5]:16 optlc_net_164:20 6.038888e-05 +30 chany_bottom_in[5]:16 optlc_net_164:42 0.0001133691 +31 chany_bottom_in[5]:16 optlc_net_164:29 1.165316e-05 +32 chany_bottom_in[5]:16 optlc_net_164:23 0.0001648838 +33 chany_bottom_in[5]:18 optlc_net_164:37 5.35769e-06 +34 chany_bottom_in[5]:17 optlc_net_164:41 0.0001133691 +35 chany_bottom_in[5]:17 optlc_net_164:42 1.165316e-05 +36 chany_bottom_in[5]:17 optlc_net_164:29 6.038888e-05 +37 chany_bottom_in[5]:17 optlc_net_164:24 0.0001648838 +38 chany_bottom_in[5]:17 optlc_net_164:38 5.35769e-06 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:20 0.02009822 +1 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.004189732 +2 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.0045 +3 chany_bottom_in[5]:6 mux_right_track_0\/mux_l1_in_0_:A0 0.152 +4 chany_bottom_in[5]:4 chany_bottom_in[5]:3 0.0001576087 +5 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.0045 +6 chany_bottom_in[5]:3 mux_left_track_33\/mux_l1_in_0_:A0 0.152 +7 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.0008705358 +8 chany_bottom_in[5]:9 chany_bottom_in[5]:5 0.0005669643 +9 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.00341 +10 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.001004625 +11 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.00341 +12 chany_bottom_in[5]:14 chany_bottom_in[5]:13 0.00341 +13 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.003406716 +14 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.00341 +15 chany_bottom_in[5]:15 chany_bottom_in[5]:14 6.499219e-05 +16 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.02064286 +17 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.0004107143 +18 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.0004107143 +19 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.01634152 + +*END + +*D_NET bottom_left_grid_pin_36_[0] 0.0181428 //LENGTH 123.175 LUMPCC 0.005879944 DR + +*CONN +*P bottom_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 6.800 +*I mux_bottom_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.980 20.060 +*I mux_bottom_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 34.405 36.380 +*I mux_bottom_track_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.815 42.500 +*I mux_bottom_track_29\/mux_l1_in_0_:A0 I *L 0.001631 *C 106.435 20.740 +*N bottom_left_grid_pin_36_[0]:5 *C 106.398 20.740 +*N bottom_left_grid_pin_36_[0]:6 *C 105.385 20.740 +*N bottom_left_grid_pin_36_[0]:7 *C 105.340 20.740 +*N bottom_left_grid_pin_36_[0]:8 *C 105.340 21.080 +*N bottom_left_grid_pin_36_[0]:9 *C 105.333 21.080 +*N bottom_left_grid_pin_36_[0]:10 *C 87.095 21.080 +*N bottom_left_grid_pin_36_[0]:11 *C 37.267 21.080 +*N bottom_left_grid_pin_36_[0]:12 *C 37.260 21.023 +*N bottom_left_grid_pin_36_[0]:13 *C 38.778 42.500 +*N bottom_left_grid_pin_36_[0]:14 *C 38.225 42.500 +*N bottom_left_grid_pin_36_[0]:15 *C 38.180 42.455 +*N bottom_left_grid_pin_36_[0]:16 *C 38.180 36.425 +*N bottom_left_grid_pin_36_[0]:17 *C 38.135 36.380 +*N bottom_left_grid_pin_36_[0]:18 *C 34.443 36.380 +*N bottom_left_grid_pin_36_[0]:19 *C 34.960 36.380 +*N bottom_left_grid_pin_36_[0]:20 *C 34.960 36.335 +*N bottom_left_grid_pin_36_[0]:21 *C 34.960 20.105 +*N bottom_left_grid_pin_36_[0]:22 *C 35.005 20.060 +*N bottom_left_grid_pin_36_[0]:23 *C 35.980 20.060 +*N bottom_left_grid_pin_36_[0]:24 *C 37.215 20.060 +*N bottom_left_grid_pin_36_[0]:25 *C 37.260 20.060 +*N bottom_left_grid_pin_36_[0]:26 *C 37.260 6.857 +*N bottom_left_grid_pin_36_[0]:27 *C 37.253 6.800 + +*CAP +0 bottom_left_grid_pin_36_[0] 0.0001553516 +1 mux_bottom_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_5\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_13\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_29\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_36_[0]:5 0.0001071678 +6 bottom_left_grid_pin_36_[0]:6 0.0001071678 +7 bottom_left_grid_pin_36_[0]:7 5.626375e-05 +8 bottom_left_grid_pin_36_[0]:8 6.027256e-05 +9 bottom_left_grid_pin_36_[0]:9 0.001077596 +10 bottom_left_grid_pin_36_[0]:10 0.003369627 +11 bottom_left_grid_pin_36_[0]:11 0.002292031 +12 bottom_left_grid_pin_36_[0]:12 6.085445e-05 +13 bottom_left_grid_pin_36_[0]:13 6.864417e-05 +14 bottom_left_grid_pin_36_[0]:14 6.864417e-05 +15 bottom_left_grid_pin_36_[0]:15 0.0003441753 +16 bottom_left_grid_pin_36_[0]:16 0.0003441753 +17 bottom_left_grid_pin_36_[0]:17 0.0001961503 +18 bottom_left_grid_pin_36_[0]:18 4.949461e-05 +19 bottom_left_grid_pin_36_[0]:19 0.0002798598 +20 bottom_left_grid_pin_36_[0]:20 0.0008031947 +21 bottom_left_grid_pin_36_[0]:21 0.0008031946 +22 bottom_left_grid_pin_36_[0]:22 7.370245e-05 +23 bottom_left_grid_pin_36_[0]:23 0.0002042572 +24 bottom_left_grid_pin_36_[0]:24 0.000100135 +25 bottom_left_grid_pin_36_[0]:25 0.0007882098 +26 bottom_left_grid_pin_36_[0]:26 0.0006933409 +27 bottom_left_grid_pin_36_[0]:27 0.0001553516 +28 bottom_left_grid_pin_36_[0] prog_clk[0]:560 0.0002730921 +29 bottom_left_grid_pin_36_[0] prog_clk[0]:561 0.0001205457 +30 bottom_left_grid_pin_36_[0]:16 prog_clk[0]:535 1.122075e-05 +31 bottom_left_grid_pin_36_[0]:15 prog_clk[0]:512 1.122075e-05 +32 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:139 0.000370179 +33 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:201 0.000144784 +34 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:202 0.0001064698 +35 bottom_left_grid_pin_36_[0]:11 prog_clk[0]:310 0.0002205884 +36 bottom_left_grid_pin_36_[0]:9 prog_clk[0]:100 1.717346e-05 +37 bottom_left_grid_pin_36_[0]:9 prog_clk[0]:111 2.224131e-05 +38 bottom_left_grid_pin_36_[0]:9 prog_clk[0]:135 7.380972e-05 +39 bottom_left_grid_pin_36_[0]:25 prog_clk[0]:544 1.783398e-05 +40 bottom_left_grid_pin_36_[0]:20 prog_clk[0]:499 2.54593e-06 +41 bottom_left_grid_pin_36_[0]:20 prog_clk[0]:500 3.619994e-06 +42 bottom_left_grid_pin_36_[0]:21 prog_clk[0]:500 2.54593e-06 +43 bottom_left_grid_pin_36_[0]:21 prog_clk[0]:546 3.619994e-06 +44 bottom_left_grid_pin_36_[0]:26 prog_clk[0]:505 1.783398e-05 +45 bottom_left_grid_pin_36_[0]:27 prog_clk[0]:325 0.0002730921 +46 bottom_left_grid_pin_36_[0]:27 prog_clk[0]:560 0.0001205457 +47 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:111 1.717346e-05 +48 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:112 2.224131e-05 +49 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:135 0.000370179 +50 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:139 0.0002185937 +51 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:201 0.0001064698 +52 bottom_left_grid_pin_36_[0]:10 prog_clk[0]:309 0.0002205884 +53 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_38_[0] 0.0001138151 +54 bottom_left_grid_pin_36_[0]:17 bottom_left_grid_pin_38_[0]:6 8.266172e-06 +55 bottom_left_grid_pin_36_[0]:16 bottom_left_grid_pin_38_[0]:21 4.228961e-07 +56 bottom_left_grid_pin_36_[0]:15 bottom_left_grid_pin_38_[0]:7 4.228961e-07 +57 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_38_[0]:21 2.966168e-06 +58 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_38_[0]:7 2.290056e-06 +59 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_38_[0]:13 0.0005073341 +60 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_38_[0]:16 4.827333e-07 +61 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_38_[0]:18 4.217701e-06 +62 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_38_[0]:21 2.886603e-05 +63 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_38_[0]:22 2.966168e-06 +64 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_38_[0]:6 1.723381e-06 +65 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_38_[0]:5 8.266172e-06 +66 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_38_[0]:21 7.592994e-06 +67 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_38_[0]:7 0.0001750143 +68 bottom_left_grid_pin_36_[0]:22 bottom_left_grid_pin_38_[0]:20 2.31684e-06 +69 bottom_left_grid_pin_36_[0]:22 bottom_left_grid_pin_38_[0]:19 2.280451e-06 +70 bottom_left_grid_pin_36_[0]:21 bottom_left_grid_pin_38_[0]:21 0.0001750143 +71 bottom_left_grid_pin_36_[0]:21 bottom_left_grid_pin_38_[0]:22 7.592994e-06 +72 bottom_left_grid_pin_36_[0]:26 bottom_left_grid_pin_38_[0]:22 2.657597e-05 +73 bottom_left_grid_pin_36_[0]:27 bottom_left_grid_pin_38_[0]:23 0.0001138151 +74 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_38_[0]:20 6.498152e-06 +75 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_38_[0]:18 2.31684e-06 +76 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_38_[0]:17 4.827333e-07 +77 bottom_left_grid_pin_36_[0]:18 bottom_left_grid_pin_38_[0]:5 1.723381e-06 +78 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_38_[0]:12 0.0005073341 +79 bottom_left_grid_pin_36_[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.160402e-05 +80 bottom_left_grid_pin_36_[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.160402e-05 +81 bottom_left_grid_pin_36_[0]:11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0006389648 +82 bottom_left_grid_pin_36_[0]:10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0006389648 + +*RES +0 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_36_[0]:27 0.001175392 +1 bottom_left_grid_pin_36_[0]:17 bottom_left_grid_pin_36_[0]:16 0.0045 +2 bottom_left_grid_pin_36_[0]:16 bottom_left_grid_pin_36_[0]:15 0.005383929 +3 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_36_[0]:13 0.0004933035 +4 bottom_left_grid_pin_36_[0]:15 bottom_left_grid_pin_36_[0]:14 0.0045 +5 bottom_left_grid_pin_36_[0]:13 mux_bottom_track_13\/mux_l1_in_0_:A0 0.152 +6 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_36_[0]:11 0.00341 +7 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_36_[0]:10 0.007806308 +8 bottom_left_grid_pin_36_[0]:8 bottom_left_grid_pin_36_[0]:7 0.0001634615 +9 bottom_left_grid_pin_36_[0]:9 bottom_left_grid_pin_36_[0]:8 0.00341 +10 bottom_left_grid_pin_36_[0]:6 bottom_left_grid_pin_36_[0]:5 0.0009040179 +11 bottom_left_grid_pin_36_[0]:7 bottom_left_grid_pin_36_[0]:6 0.0045 +12 bottom_left_grid_pin_36_[0]:5 mux_bottom_track_29\/mux_l1_in_0_:A0 0.152 +13 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_36_[0]:23 0.001102679 +14 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_36_[0]:24 0.0045 +15 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_36_[0]:12 0.0008593751 +16 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:18 0.0004620536 +17 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:17 0.002834821 +18 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_36_[0]:19 0.0045 +19 bottom_left_grid_pin_36_[0]:22 bottom_left_grid_pin_36_[0]:21 0.0045 +20 bottom_left_grid_pin_36_[0]:21 bottom_left_grid_pin_36_[0]:20 0.01449107 +21 bottom_left_grid_pin_36_[0]:26 bottom_left_grid_pin_36_[0]:25 0.01178795 +22 bottom_left_grid_pin_36_[0]:27 bottom_left_grid_pin_36_[0]:26 0.00341 +23 bottom_left_grid_pin_36_[0]:23 mux_bottom_track_1\/mux_l1_in_1_:A1 0.152 +24 bottom_left_grid_pin_36_[0]:23 bottom_left_grid_pin_36_[0]:22 0.0008705358 +25 bottom_left_grid_pin_36_[0]:18 mux_bottom_track_5\/mux_l1_in_1_:A1 0.152 +26 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_36_[0]:9 0.002857208 + +*END + +*D_NET chanx_left_out[12] 0.003976391 //LENGTH 25.385 LUMPCC 0.002061678 DR + +*CONN +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 26.220 82.960 +*P chanx_left_out[12] O *L 0.7423 *C 1.305 82.960 +*N chanx_left_out[12]:2 *C 21.613 82.960 +*N chanx_left_out[12]:3 *C 21.620 82.960 +*N chanx_left_out[12]:4 *C 21.665 82.960 +*N chanx_left_out[12]:5 *C 26.183 82.960 + +*CAP +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[12] 0.0006622585 +2 chanx_left_out[12]:2 0.0006622585 +3 chanx_left_out[12]:3 3.365467e-05 +4 chanx_left_out[12]:4 0.0002777706 +5 chanx_left_out[12]:5 0.0002777706 +6 chanx_left_out[12] chanx_left_in[19] 9.055948e-05 +7 chanx_left_out[12] chanx_left_in[19]:10 0.0009402797 +8 chanx_left_out[12]:2 chanx_left_in[19]:9 0.0009402797 +9 chanx_left_out[12]:2 chanx_left_in[19]:11 9.055948e-05 + +*RES +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[12]:5 0.152 +1 chanx_left_out[12]:5 chanx_left_out[12]:4 0.004033482 +2 chanx_left_out[12]:4 chanx_left_out[12]:3 0.0045 +3 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +4 chanx_left_out[12]:2 chanx_left_out[12] 0.003181508 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[0] 0.001449889 //LENGTH 10.625 LUMPCC 0.0001667652 DR + +*CONN +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.345 12.240 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 76.535 9.860 +*I mux_bottom_track_37\/mux_l1_in_0_:S I *L 0.00357 *C 81.520 14.280 +*N mux_tree_tapbuf_size2_5_sram[0]:3 *C 81.483 14.280 +*N mux_tree_tapbuf_size2_5_sram[0]:4 *C 80.085 14.280 +*N mux_tree_tapbuf_size2_5_sram[0]:5 *C 80.040 14.235 +*N mux_tree_tapbuf_size2_5_sram[0]:6 *C 76.573 9.860 +*N mux_tree_tapbuf_size2_5_sram[0]:7 *C 79.995 9.860 +*N mux_tree_tapbuf_size2_5_sram[0]:8 *C 80.040 9.905 +*N mux_tree_tapbuf_size2_5_sram[0]:9 *C 80.040 12.240 +*N mux_tree_tapbuf_size2_5_sram[0]:10 *C 80.040 12.240 +*N mux_tree_tapbuf_size2_5_sram[0]:11 *C 80.345 12.240 + +*CAP +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_37\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[0]:3 9.271463e-05 +4 mux_tree_tapbuf_size2_5_sram[0]:4 9.271463e-05 +5 mux_tree_tapbuf_size2_5_sram[0]:5 0.0001152293 +6 mux_tree_tapbuf_size2_5_sram[0]:6 0.0002385026 +7 mux_tree_tapbuf_size2_5_sram[0]:7 0.0002385026 +8 mux_tree_tapbuf_size2_5_sram[0]:8 0.0001194866 +9 mux_tree_tapbuf_size2_5_sram[0]:9 0.0002681481 +10 mux_tree_tapbuf_size2_5_sram[0]:10 5.882489e-05 +11 mux_tree_tapbuf_size2_5_sram[0]:11 5.600028e-05 +12 mux_tree_tapbuf_size2_5_sram[0]:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.002793e-05 +13 mux_tree_tapbuf_size2_5_sram[0]:8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.291069e-05 +14 mux_tree_tapbuf_size2_5_sram[0]:8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.819276e-07 +15 mux_tree_tapbuf_size2_5_sram[0]:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.002793e-05 +16 mux_tree_tapbuf_size2_5_sram[0]:9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.819276e-07 +17 mux_tree_tapbuf_size2_5_sram[0]:9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.008088e-06 +18 mux_tree_tapbuf_size2_5_sram[0]:9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.291069e-05 +19 mux_tree_tapbuf_size2_5_sram[0]:4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 3.485398e-05 +20 mux_tree_tapbuf_size2_5_sram[0]:5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.008088e-06 +21 mux_tree_tapbuf_size2_5_sram[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 3.485398e-05 + +*RES +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_5_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_5_sram[0]:7 mux_tree_tapbuf_size2_5_sram[0]:6 0.003055804 +2 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size2_5_sram[0]:6 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size2_5_sram[0]:10 mux_tree_tapbuf_size2_5_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:8 0.002084821 +6 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:5 0.00178125 +7 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:10 0.0001657609 +8 mux_tree_tapbuf_size2_5_sram[0]:4 mux_tree_tapbuf_size2_5_sram[0]:3 0.001247768 +9 mux_tree_tapbuf_size2_5_sram[0]:5 mux_tree_tapbuf_size2_5_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size2_5_sram[0]:3 mux_bottom_track_37\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_6_sram[0] 0.002421513 //LENGTH 19.745 LUMPCC 0.0001559591 DR + +*CONN +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 91.385 31.620 +*I mux_bottom_track_23\/mux_l1_in_1_:S I *L 0.00357 *C 88.680 41.480 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 88.495 33.660 +*I mux_bottom_track_23\/mux_l1_in_0_:S I *L 0.00357 *C 84.080 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:4 *C 84.043 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:5 *C 83.720 34.000 +*N mux_tree_tapbuf_size3_6_sram[0]:6 *C 83.720 33.660 +*N mux_tree_tapbuf_size3_6_sram[0]:7 *C 88.458 33.660 +*N mux_tree_tapbuf_size3_6_sram[0]:8 *C 88.680 41.480 +*N mux_tree_tapbuf_size3_6_sram[0]:9 *C 88.780 41.435 +*N mux_tree_tapbuf_size3_6_sram[0]:10 *C 88.780 33.705 +*N mux_tree_tapbuf_size3_6_sram[0]:11 *C 88.825 33.660 +*N mux_tree_tapbuf_size3_6_sram[0]:12 *C 91.035 33.660 +*N mux_tree_tapbuf_size3_6_sram[0]:13 *C 91.080 33.615 +*N mux_tree_tapbuf_size3_6_sram[0]:14 *C 91.080 31.665 +*N mux_tree_tapbuf_size3_6_sram[0]:15 *C 91.080 31.620 +*N mux_tree_tapbuf_size3_6_sram[0]:16 *C 91.385 31.620 + +*CAP +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_23\/mux_l1_in_1_:S 1e-06 +2 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_23\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_6_sram[0]:4 3.722955e-05 +5 mux_tree_tapbuf_size3_6_sram[0]:5 6.526642e-05 +6 mux_tree_tapbuf_size3_6_sram[0]:6 0.0003294387 +7 mux_tree_tapbuf_size3_6_sram[0]:7 0.000322441 +8 mux_tree_tapbuf_size3_6_sram[0]:8 3.137275e-05 +9 mux_tree_tapbuf_size3_6_sram[0]:9 0.000399155 +10 mux_tree_tapbuf_size3_6_sram[0]:10 0.000399155 +11 mux_tree_tapbuf_size3_6_sram[0]:11 0.0001807986 +12 mux_tree_tapbuf_size3_6_sram[0]:12 0.0001597594 +13 mux_tree_tapbuf_size3_6_sram[0]:13 0.0001219961 +14 mux_tree_tapbuf_size3_6_sram[0]:14 0.0001219961 +15 mux_tree_tapbuf_size3_6_sram[0]:15 4.858695e-05 +16 mux_tree_tapbuf_size3_6_sram[0]:16 4.435793e-05 +17 mux_tree_tapbuf_size3_6_sram[0]:10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.472404e-05 +18 mux_tree_tapbuf_size3_6_sram[0]:10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.32555e-05 +19 mux_tree_tapbuf_size3_6_sram[0]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.32555e-05 +20 mux_tree_tapbuf_size3_6_sram[0]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.472404e-05 + +*RES +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_6_sram[0]:16 0.152 +1 mux_tree_tapbuf_size3_6_sram[0]:4 mux_bottom_track_23\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_6_sram[0]:7 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +3 mux_tree_tapbuf_size3_6_sram[0]:7 mux_tree_tapbuf_size3_6_sram[0]:6 0.004229911 +4 mux_tree_tapbuf_size3_6_sram[0]:12 mux_tree_tapbuf_size3_6_sram[0]:11 0.001973215 +5 mux_tree_tapbuf_size3_6_sram[0]:13 mux_tree_tapbuf_size3_6_sram[0]:12 0.0045 +6 mux_tree_tapbuf_size3_6_sram[0]:15 mux_tree_tapbuf_size3_6_sram[0]:14 0.0045 +7 mux_tree_tapbuf_size3_6_sram[0]:14 mux_tree_tapbuf_size3_6_sram[0]:13 0.001741072 +8 mux_tree_tapbuf_size3_6_sram[0]:16 mux_tree_tapbuf_size3_6_sram[0]:15 0.0001657609 +9 mux_tree_tapbuf_size3_6_sram[0]:11 mux_tree_tapbuf_size3_6_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size3_6_sram[0]:11 mux_tree_tapbuf_size3_6_sram[0]:7 0.0001997283 +11 mux_tree_tapbuf_size3_6_sram[0]:10 mux_tree_tapbuf_size3_6_sram[0]:9 0.006901786 +12 mux_tree_tapbuf_size3_6_sram[0]:8 mux_bottom_track_23\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_6_sram[0]:9 mux_tree_tapbuf_size3_6_sram[0]:8 0.0045 +14 mux_tree_tapbuf_size3_6_sram[0]:6 mux_tree_tapbuf_size3_6_sram[0]:5 0.0003035715 +15 mux_tree_tapbuf_size3_6_sram[0]:5 mux_tree_tapbuf_size3_6_sram[0]:4 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[1] 0.004308628 //LENGTH 36.800 LUMPCC 0.000680049 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.505 82.960 +*I mux_left_track_33\/mux_l2_in_1_:S I *L 0.00357 *C 72.320 74.510 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 67.335 80.580 +*I mux_left_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 75.080 90.440 +*N mux_tree_tapbuf_size4_3_sram[1]:4 *C 75.118 90.440 +*N mux_tree_tapbuf_size4_3_sram[1]:5 *C 76.775 90.440 +*N mux_tree_tapbuf_size4_3_sram[1]:6 *C 76.820 90.395 +*N mux_tree_tapbuf_size4_3_sram[1]:7 *C 67.335 80.580 +*N mux_tree_tapbuf_size4_3_sram[1]:8 *C 67.620 80.580 +*N mux_tree_tapbuf_size4_3_sram[1]:9 *C 67.620 80.535 +*N mux_tree_tapbuf_size4_3_sram[1]:10 *C 67.620 75.185 +*N mux_tree_tapbuf_size4_3_sram[1]:11 *C 67.665 75.140 +*N mux_tree_tapbuf_size4_3_sram[1]:12 *C 72.220 75.140 +*N mux_tree_tapbuf_size4_3_sram[1]:13 *C 72.320 74.510 +*N mux_tree_tapbuf_size4_3_sram[1]:14 *C 72.290 74.870 +*N mux_tree_tapbuf_size4_3_sram[1]:15 *C 72.175 74.730 +*N mux_tree_tapbuf_size4_3_sram[1]:16 *C 76.775 74.800 +*N mux_tree_tapbuf_size4_3_sram[1]:17 *C 76.820 74.845 +*N mux_tree_tapbuf_size4_3_sram[1]:18 *C 76.820 82.960 +*N mux_tree_tapbuf_size4_3_sram[1]:19 *C 76.865 82.960 +*N mux_tree_tapbuf_size4_3_sram[1]:20 *C 78.468 82.960 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_33\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_33\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_3_sram[1]:4 0.00012618 +5 mux_tree_tapbuf_size4_3_sram[1]:5 0.00012618 +6 mux_tree_tapbuf_size4_3_sram[1]:6 0.0002795885 +7 mux_tree_tapbuf_size4_3_sram[1]:7 4.568653e-05 +8 mux_tree_tapbuf_size4_3_sram[1]:8 4.982847e-05 +9 mux_tree_tapbuf_size4_3_sram[1]:9 0.0002945367 +10 mux_tree_tapbuf_size4_3_sram[1]:10 0.0002945367 +11 mux_tree_tapbuf_size4_3_sram[1]:11 0.00020132 +12 mux_tree_tapbuf_size4_3_sram[1]:12 0.0002274737 +13 mux_tree_tapbuf_size4_3_sram[1]:13 6.377831e-05 +14 mux_tree_tapbuf_size4_3_sram[1]:14 3.73453e-05 +15 mux_tree_tapbuf_size4_3_sram[1]:15 0.000364121 +16 mux_tree_tapbuf_size4_3_sram[1]:16 0.0003330229 +17 mux_tree_tapbuf_size4_3_sram[1]:17 0.0003307035 +18 mux_tree_tapbuf_size4_3_sram[1]:18 0.0006395421 +19 mux_tree_tapbuf_size4_3_sram[1]:19 0.0001053681 +20 mux_tree_tapbuf_size4_3_sram[1]:20 0.0001053681 +21 mux_tree_tapbuf_size4_3_sram[1]:5 chany_bottom_in[12]:4 6.301291e-07 +22 mux_tree_tapbuf_size4_3_sram[1]:6 chany_bottom_in[12]:6 9.952288e-05 +23 mux_tree_tapbuf_size4_3_sram[1]:4 chany_bottom_in[12]:5 6.301291e-07 +24 mux_tree_tapbuf_size4_3_sram[1]:16 chany_bottom_in[12]:9 4.713192e-05 +25 mux_tree_tapbuf_size4_3_sram[1]:17 chany_bottom_in[12]:7 9.632287e-05 +26 mux_tree_tapbuf_size4_3_sram[1]:18 chany_bottom_in[12]:6 9.632287e-05 +27 mux_tree_tapbuf_size4_3_sram[1]:18 chany_bottom_in[12]:7 9.952288e-05 +28 mux_tree_tapbuf_size4_3_sram[1]:15 chany_bottom_in[12]:8 4.713192e-05 +29 mux_tree_tapbuf_size4_3_sram[1]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.195837e-05 +30 mux_tree_tapbuf_size4_3_sram[1]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.445829e-05 +31 mux_tree_tapbuf_size4_3_sram[1]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.445829e-05 +32 mux_tree_tapbuf_size4_3_sram[1]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.195837e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_3_sram[1]:20 0.152 +1 mux_tree_tapbuf_size4_3_sram[1]:5 mux_tree_tapbuf_size4_3_sram[1]:4 0.001479911 +2 mux_tree_tapbuf_size4_3_sram[1]:6 mux_tree_tapbuf_size4_3_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size4_3_sram[1]:4 mux_left_track_33\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size4_3_sram[1]:11 mux_tree_tapbuf_size4_3_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size4_3_sram[1]:10 mux_tree_tapbuf_size4_3_sram[1]:9 0.004776786 +6 mux_tree_tapbuf_size4_3_sram[1]:8 mux_tree_tapbuf_size4_3_sram[1]:7 0.0001548913 +7 mux_tree_tapbuf_size4_3_sram[1]:9 mux_tree_tapbuf_size4_3_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size4_3_sram[1]:7 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size4_3_sram[1]:16 mux_tree_tapbuf_size4_3_sram[1]:15 0.004107143 +10 mux_tree_tapbuf_size4_3_sram[1]:17 mux_tree_tapbuf_size4_3_sram[1]:16 0.0045 +11 mux_tree_tapbuf_size4_3_sram[1]:19 mux_tree_tapbuf_size4_3_sram[1]:18 0.0045 +12 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[1]:17 0.007245536 +13 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[1]:6 0.006638394 +14 mux_tree_tapbuf_size4_3_sram[1]:20 mux_tree_tapbuf_size4_3_sram[1]:19 0.001430804 +15 mux_tree_tapbuf_size4_3_sram[1]:13 mux_left_track_33\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size4_3_sram[1]:12 mux_tree_tapbuf_size4_3_sram[1]:11 0.004066965 +17 mux_tree_tapbuf_size4_3_sram[1]:15 mux_tree_tapbuf_size4_3_sram[1]:14 0.0001026786 +18 mux_tree_tapbuf_size4_3_sram[1]:15 mux_tree_tapbuf_size4_3_sram[1]:12 0.0003660715 +19 mux_tree_tapbuf_size4_3_sram[1]:14 mux_tree_tapbuf_size4_3_sram[1]:13 0.0001551724 + +*END + +*D_NET mux_tree_tapbuf_size5_6_sram[2] 0.001974369 //LENGTH 16.725 LUMPCC 9.902904e-05 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 57.805 86.020 +*I mux_left_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 52.540 82.960 +*I mem_left_track_25\/FTB_12__37:A I *L 0.001746 *C 62.560 88.400 +*N mux_tree_tapbuf_size5_6_sram[2]:3 *C 62.560 88.400 +*N mux_tree_tapbuf_size5_6_sram[2]:4 *C 62.560 88.355 +*N mux_tree_tapbuf_size5_6_sram[2]:5 *C 62.560 86.065 +*N mux_tree_tapbuf_size5_6_sram[2]:6 *C 62.515 86.020 +*N mux_tree_tapbuf_size5_6_sram[2]:7 *C 52.578 82.960 +*N mux_tree_tapbuf_size5_6_sram[2]:8 *C 56.535 82.960 +*N mux_tree_tapbuf_size5_6_sram[2]:9 *C 56.580 83.005 +*N mux_tree_tapbuf_size5_6_sram[2]:10 *C 56.580 85.975 +*N mux_tree_tapbuf_size5_6_sram[2]:11 *C 56.625 86.020 +*N mux_tree_tapbuf_size5_6_sram[2]:12 *C 57.805 86.020 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_25\/FTB_12__37:A 1e-06 +3 mux_tree_tapbuf_size5_6_sram[2]:3 2.965735e-05 +4 mux_tree_tapbuf_size5_6_sram[2]:4 0.0001295475 +5 mux_tree_tapbuf_size5_6_sram[2]:5 0.0001295475 +6 mux_tree_tapbuf_size5_6_sram[2]:6 0.0002639253 +7 mux_tree_tapbuf_size5_6_sram[2]:7 0.0002466207 +8 mux_tree_tapbuf_size5_6_sram[2]:8 0.0002466207 +9 mux_tree_tapbuf_size5_6_sram[2]:9 0.0001874274 +10 mux_tree_tapbuf_size5_6_sram[2]:10 0.0001874274 +11 mux_tree_tapbuf_size5_6_sram[2]:11 8.025167e-05 +12 mux_tree_tapbuf_size5_6_sram[2]:12 0.000371314 +13 mux_tree_tapbuf_size5_6_sram[2]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.367162e-07 +14 mux_tree_tapbuf_size5_6_sram[2]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.89778e-05 +15 mux_tree_tapbuf_size5_6_sram[2]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.367162e-07 +16 mux_tree_tapbuf_size5_6_sram[2]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.89778e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_6_sram[2]:12 0.152 +1 mux_tree_tapbuf_size5_6_sram[2]:11 mux_tree_tapbuf_size5_6_sram[2]:10 0.0045 +2 mux_tree_tapbuf_size5_6_sram[2]:10 mux_tree_tapbuf_size5_6_sram[2]:9 0.002651786 +3 mux_tree_tapbuf_size5_6_sram[2]:8 mux_tree_tapbuf_size5_6_sram[2]:7 0.003533482 +4 mux_tree_tapbuf_size5_6_sram[2]:9 mux_tree_tapbuf_size5_6_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size5_6_sram[2]:7 mux_left_track_25\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size5_6_sram[2]:6 mux_tree_tapbuf_size5_6_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size5_6_sram[2]:5 mux_tree_tapbuf_size5_6_sram[2]:4 0.002044643 +8 mux_tree_tapbuf_size5_6_sram[2]:3 mem_left_track_25\/FTB_12__37:A 0.152 +9 mux_tree_tapbuf_size5_6_sram[2]:4 mux_tree_tapbuf_size5_6_sram[2]:3 0.0045 +10 mux_tree_tapbuf_size5_6_sram[2]:12 mux_tree_tapbuf_size5_6_sram[2]:11 0.001053571 +11 mux_tree_tapbuf_size5_6_sram[2]:12 mux_tree_tapbuf_size5_6_sram[2]:6 0.004205357 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[0] 0.005933654 //LENGTH 46.320 LUMPCC 0.0002446052 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 51.825 53.380 +*I mux_left_track_9\/mux_l1_in_2_:S I *L 0.00357 *C 61.740 50.615 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 64.060 45.560 +*I mux_left_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 80.140 50.320 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.895 58.820 +*N mux_tree_tapbuf_size6_4_sram[0]:5 *C 60.933 58.820 +*N mux_tree_tapbuf_size6_4_sram[0]:6 *C 61.595 58.820 +*N mux_tree_tapbuf_size6_4_sram[0]:7 *C 61.640 58.775 +*N mux_tree_tapbuf_size6_4_sram[0]:8 *C 80.140 50.320 +*N mux_tree_tapbuf_size6_4_sram[0]:9 *C 80.040 50.660 +*N mux_tree_tapbuf_size6_4_sram[0]:10 *C 64.075 45.560 +*N mux_tree_tapbuf_size6_4_sram[0]:11 *C 64.377 45.560 +*N mux_tree_tapbuf_size6_4_sram[0]:12 *C 64.400 45.605 +*N mux_tree_tapbuf_size6_4_sram[0]:13 *C 64.400 50.615 +*N mux_tree_tapbuf_size6_4_sram[0]:14 *C 64.400 50.660 +*N mux_tree_tapbuf_size6_4_sram[0]:15 *C 63.020 50.660 +*N mux_tree_tapbuf_size6_4_sram[0]:16 *C 63.020 50.320 +*N mux_tree_tapbuf_size6_4_sram[0]:17 *C 61.815 50.320 +*N mux_tree_tapbuf_size6_4_sram[0]:18 *C 61.760 50.320 +*N mux_tree_tapbuf_size6_4_sram[0]:19 *C 61.740 50.615 +*N mux_tree_tapbuf_size6_4_sram[0]:20 *C 61.640 51.000 +*N mux_tree_tapbuf_size6_4_sram[0]:21 *C 61.640 51.045 +*N mux_tree_tapbuf_size6_4_sram[0]:22 *C 61.640 53.380 +*N mux_tree_tapbuf_size6_4_sram[0]:23 *C 61.595 53.380 +*N mux_tree_tapbuf_size6_4_sram[0]:24 *C 51.863 53.380 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_9\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_9\/mux_l1_in_1_:S 1e-06 +4 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size6_4_sram[0]:5 8.827421e-05 +6 mux_tree_tapbuf_size6_4_sram[0]:6 8.827421e-05 +7 mux_tree_tapbuf_size6_4_sram[0]:7 0.0003102194 +8 mux_tree_tapbuf_size6_4_sram[0]:8 5.552848e-05 +9 mux_tree_tapbuf_size6_4_sram[0]:9 0.0009773315 +10 mux_tree_tapbuf_size6_4_sram[0]:10 6.224867e-05 +11 mux_tree_tapbuf_size6_4_sram[0]:11 6.224867e-05 +12 mux_tree_tapbuf_size6_4_sram[0]:12 0.0003063777 +13 mux_tree_tapbuf_size6_4_sram[0]:13 0.0003063777 +14 mux_tree_tapbuf_size6_4_sram[0]:14 0.001074671 +15 mux_tree_tapbuf_size6_4_sram[0]:15 0.0001124994 +16 mux_tree_tapbuf_size6_4_sram[0]:16 0.0001276212 +17 mux_tree_tapbuf_size6_4_sram[0]:17 0.0001420188 +18 mux_tree_tapbuf_size6_4_sram[0]:18 3.159111e-05 +19 mux_tree_tapbuf_size6_4_sram[0]:19 0.000100882 +20 mux_tree_tapbuf_size6_4_sram[0]:20 6.234414e-05 +21 mux_tree_tapbuf_size6_4_sram[0]:21 0.0001166184 +22 mux_tree_tapbuf_size6_4_sram[0]:22 0.0004593309 +23 mux_tree_tapbuf_size6_4_sram[0]:23 0.0005997955 +24 mux_tree_tapbuf_size6_4_sram[0]:24 0.0005997955 +25 mux_tree_tapbuf_size6_4_sram[0]:21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.552608e-05 +26 mux_tree_tapbuf_size6_4_sram[0]:23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.890819e-05 +27 mux_tree_tapbuf_size6_4_sram[0]:22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.552608e-05 +28 mux_tree_tapbuf_size6_4_sram[0]:24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.890819e-05 +29 mux_tree_tapbuf_size6_4_sram[0]:23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.786833e-05 +30 mux_tree_tapbuf_size6_4_sram[0]:24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.786833e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_4_sram[0]:24 0.152 +1 mux_tree_tapbuf_size6_4_sram[0]:14 mux_tree_tapbuf_size6_4_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size6_4_sram[0]:14 mux_tree_tapbuf_size6_4_sram[0]:9 0.01396429 +3 mux_tree_tapbuf_size6_4_sram[0]:13 mux_tree_tapbuf_size6_4_sram[0]:12 0.004473215 +4 mux_tree_tapbuf_size6_4_sram[0]:11 mux_tree_tapbuf_size6_4_sram[0]:10 0.0001644022 +5 mux_tree_tapbuf_size6_4_sram[0]:12 mux_tree_tapbuf_size6_4_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size6_4_sram[0]:10 mux_left_track_9\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size6_4_sram[0]:20 mux_tree_tapbuf_size6_4_sram[0]:19 0.00034375 +8 mux_tree_tapbuf_size6_4_sram[0]:21 mux_tree_tapbuf_size6_4_sram[0]:20 0.0045 +9 mux_tree_tapbuf_size6_4_sram[0]:19 mux_left_track_9\/mux_l1_in_2_:S 0.152 +10 mux_tree_tapbuf_size6_4_sram[0]:19 mux_tree_tapbuf_size6_4_sram[0]:18 0.0002633929 +11 mux_tree_tapbuf_size6_4_sram[0]:19 mux_tree_tapbuf_size6_4_sram[0]:17 0.0002633929 +12 mux_tree_tapbuf_size6_4_sram[0]:8 mux_left_track_9\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size6_4_sram[0]:6 mux_tree_tapbuf_size6_4_sram[0]:5 0.0005915179 +14 mux_tree_tapbuf_size6_4_sram[0]:7 mux_tree_tapbuf_size6_4_sram[0]:6 0.0045 +15 mux_tree_tapbuf_size6_4_sram[0]:5 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size6_4_sram[0]:23 mux_tree_tapbuf_size6_4_sram[0]:22 0.0045 +17 mux_tree_tapbuf_size6_4_sram[0]:22 mux_tree_tapbuf_size6_4_sram[0]:21 0.002084821 +18 mux_tree_tapbuf_size6_4_sram[0]:22 mux_tree_tapbuf_size6_4_sram[0]:7 0.004816965 +19 mux_tree_tapbuf_size6_4_sram[0]:24 mux_tree_tapbuf_size6_4_sram[0]:23 0.008689733 +20 mux_tree_tapbuf_size6_4_sram[0]:17 mux_tree_tapbuf_size6_4_sram[0]:16 0.001075893 +21 mux_tree_tapbuf_size6_4_sram[0]:16 mux_tree_tapbuf_size6_4_sram[0]:15 0.0003035715 +22 mux_tree_tapbuf_size6_4_sram[0]:15 mux_tree_tapbuf_size6_4_sram[0]:14 0.001232143 +23 mux_tree_tapbuf_size6_4_sram[0]:9 mux_tree_tapbuf_size6_4_sram[0]:8 0.0003035715 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009860066 //LENGTH 8.560 LUMPCC 8.034256e-05 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_1_:X O *L 0 *C 108.845 75.140 +*I mux_right_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 111.035 80.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 110.998 80.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 109.985 80.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 109.940 80.535 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 109.940 75.185 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 109.895 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 108.883 75.140 + +*CAP +0 mux_right_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001021835 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001021835 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002635566 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002635566 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.609187e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.609187e-05 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_0_sram[0]:18 4.017128e-05 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_0_sram[0]:7 4.017128e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009040179 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004776786 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003161761 //LENGTH 21.195 LUMPCC 0.001399616 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_1_:X O *L 0 *C 66.875 45.220 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 52.270 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 52.308 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 52.855 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 52.900 49.595 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 52.900 45.265 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 52.945 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 62.100 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 62.100 44.880 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 63.480 44.880 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 63.480 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 66.838 45.220 + +*CAP +0 mux_left_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.666932e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.666932e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002398784 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002398784 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002536098 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002760677 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.690949e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 8.612375e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002230056 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002013334 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_right_in[6]:13 0.0003477381 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_right_in[6]:14 0.0003501787 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[6]:4 2.440568e-06 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_right_in[6]:13 2.096391e-06 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_right_in[6]:4 6.591917e-06 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_right_in[6]:14 2.096391e-06 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_right_in[6]:14 6.591917e-06 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_tree_tapbuf_size6_3_sram[0]:5 6.891355e-05 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_tree_tapbuf_size6_3_sram[0]:19 9.926501e-06 +21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size6_3_sram[0]:14 5.827103e-05 +22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size6_3_sram[0]:18 8.744929e-05 +23 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size6_3_sram[0]:18 5.827103e-05 +24 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size6_3_sram[0]:19 8.744929e-05 +25 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size6_3_sram[0]:18 5.64827e-05 +26 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size6_3_sram[0]:19 5.706269e-05 +27 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size6_3_sram[0]:18 9.926501e-06 +28 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size6_3_sram[0]:20 6.949354e-05 +29 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.931809e-05 +30 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.931809e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002997768 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A0 0.152 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.008174108 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003035715 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001232143 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0003035714 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004276616 //LENGTH 3.170 LUMPCC 8.105576e-05 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_1_:X O *L 0 *C 112.985 42.160 +*I mux_right_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 115.635 42.500 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 115.635 42.500 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 115.460 42.160 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 113.023 42.160 + +*CAP +0 mux_right_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.477074e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001575178 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001323174 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_left_in[18]:14 4.052788e-05 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_left_in[18]:13 4.052788e-05 + +*RES +0 mux_right_track_24\/mux_l2_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.00217634 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001352227 //LENGTH 11.780 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_0_:X O *L 0 *C 59.975 61.200 +*I mux_left_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 56.945 69.020 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 56.983 69.020 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 59.295 69.020 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 59.340 68.975 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 59.340 61.245 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 59.385 61.200 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 59.938 61.200 + +*CAP +0 mux_left_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001716808 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001716808 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004313545 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004313545 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.207803e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.207803e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002064732 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901785 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933035 + +*END + +*D_NET mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0] 0.004126444 //LENGTH 34.530 LUMPCC 0.0003882112 DR + +*CONN +*I mux_bottom_track_13\/mux_l2_in_0_:X O *L 0 *C 49.045 37.060 +*I mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 49.855 4.240 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 49.855 4.240 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 49.680 4.080 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 49.680 4.125 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 49.680 37.015 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 49.635 37.060 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 49.083 37.060 + +*CAP +0 mux_bottom_track_13\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.807956e-05 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.190161e-05 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001738083 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001738083 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.504327e-05 +7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.504327e-05 +8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[13]:5 0.0001241509 +9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[13]:6 0.0001241509 +10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.995468e-05 +11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.995468e-05 + +*RES +0 mux_bottom_track_13\/mux_l2_in_0_:X mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.695653e-05 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.02936607 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001055285 //LENGTH 7.440 LUMPCC 0.0002858235 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_3_:X O *L 0 *C 40.305 33.660 +*I mux_bottom_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 39.235 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 39.250 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 39.538 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 39.560 28.265 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 39.560 33.615 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 39.605 33.660 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 40.268 33.660 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.827014e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.827014e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002353431 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002353431 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.011739e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.011739e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:535 5.514343e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:538 8.77683e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:538 5.514343e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:539 8.77683e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_3_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005915179 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.00015625 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008827319 //LENGTH 6.210 LUMPCC 0.0001444569 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_1_:X O *L 0 *C 24.205 38.760 +*I mux_bottom_track_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 25.590 42.500 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 25.590 42.500 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 25.760 42.500 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 25.760 42.455 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 25.760 38.805 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 25.715 38.760 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 24.242 38.760 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.598282e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.05219e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002301787 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002301787 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.970643e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.970643e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_39_[0]:7 1.536457e-06 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 bottom_left_grid_pin_39_[0]:6 7.0692e-05 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_39_[0]:8 1.536457e-06 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 bottom_left_grid_pin_39_[0]:5 7.0692e-05 + +*RES +0 mux_bottom_track_7\/mux_l1_in_1_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_7\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003258929 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002714574 //LENGTH 19.205 LUMPCC 0.0002993389 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_1_:X O *L 0 *C 102.755 30.600 +*I mux_bottom_track_25\/mux_l3_in_0_:A0 I *L 0.005103 *C 93.380 26.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 93.343 26.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.000 26.680 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.000 26.520 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 91.585 26.520 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 91.540 26.565 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 91.540 29.183 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 91.547 29.240 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 100.733 29.240 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 100.740 29.298 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 100.740 30.555 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 100.785 30.600 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 102.718 30.600 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001608506 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001760392 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.250094e-05 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.73123e-05 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002029577 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002029577 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0005354631 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0005354631 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 9.976865e-05 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 9.976865e-05 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0001450767 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0001450767 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_bottom_in[6]:7 7.256756e-05 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 chany_bottom_in[6]:13 7.710191e-05 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_bottom_in[6]:12 7.710191e-05 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_bottom_in[6]:13 7.256756e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.001725447 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.001122768 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.00341 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001438983 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002337054 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003705357 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A0 0.152 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001428571 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001198661 + +*END + +*D_NET ropt_net_197 0.001047408 //LENGTH 8.950 LUMPCC 7.667621e-05 DR + +*CONN +*I FTB_5__4:X O *L 0 *C 9.200 65.960 +*I ropt_mt_inst_817:A I *L 0.001766 *C 3.220 63.920 +*N ropt_net_197:2 *C 3.258 63.920 +*N ropt_net_197:3 *C 5.935 63.920 +*N ropt_net_197:4 *C 5.980 63.965 +*N ropt_net_197:5 *C 5.980 65.915 +*N ropt_net_197:6 *C 6.025 65.960 +*N ropt_net_197:7 *C 9.162 65.960 + +*CAP +0 FTB_5__4:X 1e-06 +1 ropt_mt_inst_817:A 1e-06 +2 ropt_net_197:2 0.0001646463 +3 ropt_net_197:3 0.0001646463 +4 ropt_net_197:4 0.000111448 +5 ropt_net_197:5 0.000111448 +6 ropt_net_197:6 0.0002082718 +7 ropt_net_197:7 0.0002082718 +8 ropt_net_197:4 ropt_net_209:5 1.823605e-05 +9 ropt_net_197:6 ropt_net_209:2 2.010206e-05 +10 ropt_net_197:5 ropt_net_209:4 1.823605e-05 +11 ropt_net_197:7 ropt_net_209:3 2.010206e-05 + +*RES +0 FTB_5__4:X ropt_net_197:7 0.152 +1 ropt_net_197:2 ropt_mt_inst_817:A 0.152 +2 ropt_net_197:3 ropt_net_197:2 0.002390625 +3 ropt_net_197:4 ropt_net_197:3 0.0045 +4 ropt_net_197:6 ropt_net_197:5 0.0045 +5 ropt_net_197:5 ropt_net_197:4 0.001741072 +6 ropt_net_197:7 ropt_net_197:6 0.002801339 + +*END + +*D_NET ropt_net_202 0.001416259 //LENGTH 11.585 LUMPCC 0.0001035585 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 11.695 93.160 +*I ropt_mt_inst_820:A I *L 0.001767 *C 3.220 91.120 +*N ropt_net_202:2 *C 3.220 91.157 +*N ropt_net_202:3 *C 3.220 91.800 +*N ropt_net_202:4 *C 10.995 91.800 +*N ropt_net_202:5 *C 11.040 91.845 +*N ropt_net_202:6 *C 11.040 93.115 +*N ropt_net_202:7 *C 11.085 93.160 +*N ropt_net_202:8 *C 11.658 93.160 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 ropt_mt_inst_820:A 1e-06 +2 ropt_net_202:2 4.588686e-05 +3 ropt_net_202:3 0.0004980243 +4 ropt_net_202:4 0.0004521374 +5 ropt_net_202:5 9.554505e-05 +6 ropt_net_202:6 9.554505e-05 +7 ropt_net_202:7 6.178064e-05 +8 ropt_net_202:8 6.178064e-05 +9 ropt_net_202:4 chanx_right_in[10]:14 5.177923e-05 +10 ropt_net_202:3 chanx_right_in[10]:13 5.177923e-05 + +*RES +0 ropt_mt_inst_808:X ropt_net_202:8 0.152 +1 ropt_net_202:2 ropt_mt_inst_820:A 0.152 +2 ropt_net_202:4 ropt_net_202:3 0.006941964 +3 ropt_net_202:5 ropt_net_202:4 0.0045 +4 ropt_net_202:7 ropt_net_202:6 0.0045 +5 ropt_net_202:6 ropt_net_202:5 0.001133929 +6 ropt_net_202:8 ropt_net_202:7 0.0005111608 +7 ropt_net_202:3 ropt_net_202:2 0.0005736608 + +*END + +*D_NET chany_bottom_out[5] 0.001420607 //LENGTH 10.485 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_831:X O *L 0 *C 76.525 6.120 +*P chany_bottom_out[5] O *L 0.7423 *C 71.760 1.325 +*N chany_bottom_out[5]:2 *C 71.760 1.655 +*N chany_bottom_out[5]:3 *C 71.805 1.700 +*N chany_bottom_out[5]:4 *C 76.315 1.700 +*N chany_bottom_out[5]:5 *C 76.360 1.745 +*N chany_bottom_out[5]:6 *C 76.360 6.075 +*N chany_bottom_out[5]:7 *C 76.360 6.120 +*N chany_bottom_out[5]:8 *C 76.525 6.120 + +*CAP +0 ropt_mt_inst_831:X 1e-06 +1 chany_bottom_out[5] 3.43503e-05 +2 chany_bottom_out[5]:2 3.43503e-05 +3 chany_bottom_out[5]:3 0.0002874107 +4 chany_bottom_out[5]:4 0.0002874107 +5 chany_bottom_out[5]:5 0.0003236274 +6 chany_bottom_out[5]:6 0.0003236274 +7 chany_bottom_out[5]:7 6.516482e-05 +8 chany_bottom_out[5]:8 6.36656e-05 + +*RES +0 ropt_mt_inst_831:X chany_bottom_out[5]:8 0.152 +1 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +2 chany_bottom_out[5]:2 chany_bottom_out[5] 0.0002946428 +3 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.004026786 +4 chany_bottom_out[5]:5 chany_bottom_out[5]:4 0.0045 +5 chany_bottom_out[5]:7 chany_bottom_out[5]:6 0.0045 +6 chany_bottom_out[5]:6 chany_bottom_out[5]:5 0.003866071 +7 chany_bottom_out[5]:8 chany_bottom_out[5]:7 8.967391e-05 + +*END + +*D_NET chanx_right_in[5] 0.02220179 //LENGTH 165.815 LUMPCC 0.004557218 DR + +*CONN +*P chanx_right_in[5] I *L 0.29796 *C 140.382 62.560 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 29.540 50.660 +*I FTB_3__2:A I *L 0.001776 *C 10.120 44.880 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 57.040 47.260 +*N chanx_right_in[5]:4 *C 57.003 47.260 +*N chanx_right_in[5]:5 *C 56.625 47.260 +*N chanx_right_in[5]:6 *C 56.580 47.305 +*N chanx_right_in[5]:7 *C 10.083 44.880 +*N chanx_right_in[5]:8 *C 6.945 44.880 +*N chanx_right_in[5]:9 *C 6.900 44.925 +*N chanx_right_in[5]:10 *C 6.900 49.583 +*N chanx_right_in[5]:11 *C 6.908 49.640 +*N chanx_right_in[5]:12 *C 29.503 50.660 +*N chanx_right_in[5]:13 *C 28.565 50.660 +*N chanx_right_in[5]:14 *C 28.520 50.615 +*N chanx_right_in[5]:15 *C 28.520 49.698 +*N chanx_right_in[5]:16 *C 28.520 49.640 +*N chanx_right_in[5]:17 *C 50.593 49.640 +*N chanx_right_in[5]:18 *C 50.600 49.583 +*N chanx_right_in[5]:19 *C 50.600 48.325 +*N chanx_right_in[5]:20 *C 50.645 48.280 +*N chanx_right_in[5]:21 *C 56.535 48.280 +*N chanx_right_in[5]:22 *C 56.580 48.280 +*N chanx_right_in[5]:23 *C 56.580 63.195 +*N chanx_right_in[5]:24 *C 56.625 63.240 +*N chanx_right_in[5]:25 *C 106.420 63.240 +*N chanx_right_in[5]:26 *C 140.255 63.240 +*N chanx_right_in[5]:27 *C 140.300 63.195 +*N chanx_right_in[5]:28 *C 140.300 62.617 +*N chanx_right_in[5]:29 *C 140.300 62.560 + +*CAP +0 chanx_right_in[5] 2.567829e-05 +1 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +2 FTB_3__2:A 1e-06 +3 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[5]:4 4.814961e-05 +5 chanx_right_in[5]:5 4.814961e-05 +6 chanx_right_in[5]:6 7.339168e-05 +7 chanx_right_in[5]:7 0.0001464154 +8 chanx_right_in[5]:8 0.0001464154 +9 chanx_right_in[5]:9 0.0002690869 +10 chanx_right_in[5]:10 0.0002690869 +11 chanx_right_in[5]:11 0.0007053732 +12 chanx_right_in[5]:12 9.114989e-05 +13 chanx_right_in[5]:13 9.114989e-05 +14 chanx_right_in[5]:14 7.512553e-05 +15 chanx_right_in[5]:15 7.512553e-05 +16 chanx_right_in[5]:16 0.001779925 +17 chanx_right_in[5]:17 0.001074552 +18 chanx_right_in[5]:18 7.912157e-05 +19 chanx_right_in[5]:19 7.912157e-05 +20 chanx_right_in[5]:20 0.0002941911 +21 chanx_right_in[5]:21 0.0002941911 +22 chanx_right_in[5]:22 0.0009088267 +23 chanx_right_in[5]:23 0.0008000916 +24 chanx_right_in[5]:24 0.00307885 +25 chanx_right_in[5]:25 0.005075593 +26 chanx_right_in[5]:26 0.001996743 +27 chanx_right_in[5]:27 4.519252e-05 +28 chanx_right_in[5]:28 4.519252e-05 +29 chanx_right_in[5]:29 2.567829e-05 +30 chanx_right_in[5]:17 chanx_right_in[2]:22 0.0003161383 +31 chanx_right_in[5]:11 chanx_right_in[2]:21 0.0007583522 +32 chanx_right_in[5]:16 chanx_right_in[2]:21 0.0003161383 +33 chanx_right_in[5]:16 chanx_right_in[2]:22 0.0007583522 +34 chanx_right_in[5]:11 chanx_left_in[4] 0.0004071209 +35 chanx_right_in[5]:16 chanx_left_in[4]:38 0.0004071209 +36 chanx_right_in[5]:22 prog_clk[0]:405 8.144957e-07 +37 chanx_right_in[5]:17 prog_clk[0]:481 2.240909e-05 +38 chanx_right_in[5]:17 prog_clk[0]:455 0.0001521943 +39 chanx_right_in[5]:17 prog_clk[0]:460 7.514625e-05 +40 chanx_right_in[5]:17 prog_clk[0]:411 7.329561e-06 +41 chanx_right_in[5]:17 prog_clk[0]:406 2.325422e-06 +42 chanx_right_in[5]:17 prog_clk[0]:364 1.893125e-05 +43 chanx_right_in[5]:11 prog_clk[0]:480 0.000127452 +44 chanx_right_in[5]:23 prog_clk[0]:404 8.144957e-07 +45 chanx_right_in[5]:16 prog_clk[0]:480 2.240909e-05 +46 chanx_right_in[5]:16 prog_clk[0]:481 0.000127452 +47 chanx_right_in[5]:16 prog_clk[0]:460 0.0001521943 +48 chanx_right_in[5]:16 prog_clk[0]:411 2.325422e-06 +49 chanx_right_in[5]:16 prog_clk[0]:415 7.329561e-06 +50 chanx_right_in[5]:16 prog_clk[0]:461 7.514625e-05 +51 chanx_right_in[5]:16 prog_clk[0]:365 1.893125e-05 +52 chanx_right_in[5]:22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.751116e-05 +53 chanx_right_in[5]:23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.751116e-05 +54 chanx_right_in[5]:24 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.026325e-05 +55 chanx_right_in[5]:25 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.026325e-05 +56 chanx_right_in[5]:21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.0001985626 +57 chanx_right_in[5]:20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.0001985626 +58 chanx_right_in[5]:19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 1.709169e-05 +59 chanx_right_in[5]:18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 1.709169e-05 +60 chanx_right_in[5]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 6.101071e-06 +61 chanx_right_in[5]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 6.101071e-06 +62 chanx_right_in[5]:10 ropt_net_198:4 8.063266e-06 +63 chanx_right_in[5]:8 ropt_net_198:6 6.280222e-05 +64 chanx_right_in[5]:9 ropt_net_198:5 8.063266e-06 +65 chanx_right_in[5]:7 ropt_net_198:7 6.280222e-05 + +*RES +0 chanx_right_in[5] chanx_right_in[5]:29 2.35e-05 +1 chanx_right_in[5]:21 chanx_right_in[5]:20 0.005258929 +2 chanx_right_in[5]:22 chanx_right_in[5]:21 0.0045 +3 chanx_right_in[5]:22 chanx_right_in[5]:6 0.0008705358 +4 chanx_right_in[5]:20 chanx_right_in[5]:19 0.0045 +5 chanx_right_in[5]:19 chanx_right_in[5]:18 0.001122768 +6 chanx_right_in[5]:18 chanx_right_in[5]:17 0.00341 +7 chanx_right_in[5]:17 chanx_right_in[5]:16 0.003458025 +8 chanx_right_in[5]:10 chanx_right_in[5]:9 0.004158482 +9 chanx_right_in[5]:11 chanx_right_in[5]:10 0.00341 +10 chanx_right_in[5]:8 chanx_right_in[5]:7 0.002801339 +11 chanx_right_in[5]:9 chanx_right_in[5]:8 0.0045 +12 chanx_right_in[5]:7 FTB_3__2:A 0.152 +13 chanx_right_in[5]:24 chanx_right_in[5]:23 0.0045 +14 chanx_right_in[5]:23 chanx_right_in[5]:22 0.01331696 +15 chanx_right_in[5]:26 chanx_right_in[5]:25 0.03020983 +16 chanx_right_in[5]:27 chanx_right_in[5]:26 0.0045 +17 chanx_right_in[5]:28 chanx_right_in[5]:27 0.000515625 +18 chanx_right_in[5]:29 chanx_right_in[5]:28 0.00341 +19 chanx_right_in[5]:15 chanx_right_in[5]:14 0.0008191965 +20 chanx_right_in[5]:16 chanx_right_in[5]:15 0.00341 +21 chanx_right_in[5]:16 chanx_right_in[5]:11 0.003385958 +22 chanx_right_in[5]:13 chanx_right_in[5]:12 0.0008370536 +23 chanx_right_in[5]:14 chanx_right_in[5]:13 0.0045 +24 chanx_right_in[5]:12 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +25 chanx_right_in[5]:5 chanx_right_in[5]:4 0.0003370536 +26 chanx_right_in[5]:6 chanx_right_in[5]:5 0.0045 +27 chanx_right_in[5]:4 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +28 chanx_right_in[5]:25 chanx_right_in[5]:24 0.04445983 + +*END + +*D_NET chanx_right_in[0] 0.01426365 //LENGTH 131.385 LUMPCC 0.001982441 DR + +*CONN +*P chanx_right_in[0] I *L 0.29796 *C 140.450 87.040 +*I mux_bottom_track_37\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.245 14.620 +*N chanx_right_in[0]:2 *C 82.245 14.620 +*N chanx_right_in[0]:3 *C 82.340 14.620 +*N chanx_right_in[0]:4 *C 82.340 14.960 +*N chanx_right_in[0]:5 *C 82.348 14.960 +*N chanx_right_in[0]:6 *C 109.460 14.960 +*N chanx_right_in[0]:7 *C 109.480 14.968 +*N chanx_right_in[0]:8 *C 109.480 64.795 +*N chanx_right_in[0]:9 *C 109.480 87.032 +*N chanx_right_in[0]:10 *C 109.500 87.040 + +*CAP +0 chanx_right_in[0] 0.001354694 +1 mux_bottom_track_37\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[0]:2 2.865388e-05 +3 chanx_right_in[0]:3 5.57391e-05 +4 chanx_right_in[0]:4 6.017709e-05 +5 chanx_right_in[0]:5 0.001355002 +6 chanx_right_in[0]:6 0.001355002 +7 chanx_right_in[0]:7 0.002249999 +8 chanx_right_in[0]:8 0.003358124 +9 chanx_right_in[0]:9 0.001108125 +10 chanx_right_in[0]:10 0.001354694 +11 chanx_right_in[0]:5 prog_clk[0]:111 0.0001078607 +12 chanx_right_in[0]:5 prog_clk[0]:112 0.0001364476 +13 chanx_right_in[0]:5 prog_clk[0]:125 1.760452e-06 +14 chanx_right_in[0]:5 prog_clk[0]:139 7.073895e-06 +15 chanx_right_in[0]:6 prog_clk[0]:100 0.0001078607 +16 chanx_right_in[0]:6 prog_clk[0]:111 0.0001364476 +17 chanx_right_in[0]:6 prog_clk[0]:124 1.760452e-06 +18 chanx_right_in[0]:6 prog_clk[0]:135 7.073895e-06 +19 chanx_right_in[0]:5 chanx_right_in[15]:5 0.0001562972 +20 chanx_right_in[0]:6 chanx_right_in[15]:6 0.0001562972 +21 chanx_right_in[0]:7 chanx_right_in[15]:7 0.000254254 +22 chanx_right_in[0]:8 chanx_right_in[15]:8 0.000254254 +23 chanx_right_in[0] chanx_right_out[8] 0.0003275266 +24 chanx_right_in[0]:10 chanx_right_out[8]:2 0.0003275266 + +*RES +0 chanx_right_in[0] chanx_right_in[0]:10 0.004848833 +1 chanx_right_in[0]:2 mux_bottom_track_37\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[0]:3 chanx_right_in[0]:2 0.0045 +3 chanx_right_in[0]:4 chanx_right_in[0]:3 0.0001634616 +4 chanx_right_in[0]:5 chanx_right_in[0]:4 0.00341 +5 chanx_right_in[0]:6 chanx_right_in[0]:5 0.004247625 +6 chanx_right_in[0]:7 chanx_right_in[0]:6 0.00341 +7 chanx_right_in[0]:10 chanx_right_in[0]:9 0.00341 +8 chanx_right_in[0]:9 chanx_right_in[0]:8 0.003483875 +9 chanx_right_in[0]:8 chanx_right_in[0]:7 0.007806308 + +*END + +*D_NET chanx_right_in[1] 0.01312694 //LENGTH 106.415 LUMPCC 0.001142634 DR + +*CONN +*P chanx_right_in[1] I *L 0.29796 *C 140.450 57.120 +*I mux_bottom_track_35\/mux_l1_in_0_:A1 I *L 0.00198 *C 69.460 25.500 +*N chanx_right_in[1]:2 *C 69.460 25.500 +*N chanx_right_in[1]:3 *C 69.460 25.840 +*N chanx_right_in[1]:4 *C 81.880 25.840 +*N chanx_right_in[1]:5 *C 81.880 26.180 +*N chanx_right_in[1]:6 *C 85.975 26.180 +*N chanx_right_in[1]:7 *C 86.020 26.225 +*N chanx_right_in[1]:8 *C 86.020 29.195 +*N chanx_right_in[1]:9 *C 86.065 29.240 +*N chanx_right_in[1]:10 *C 131.055 29.240 +*N chanx_right_in[1]:11 *C 131.100 29.285 +*N chanx_right_in[1]:12 *C 131.100 57.742 +*N chanx_right_in[1]:13 *C 131.108 57.800 +*N chanx_right_in[1]:14 *C 138.920 57.800 +*N chanx_right_in[1]:15 *C 138.920 57.120 + +*CAP +0 chanx_right_in[1] 9.97365e-05 +1 mux_bottom_track_35\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[1]:2 5.765296e-05 +3 chanx_right_in[1]:3 0.0008306972 +4 chanx_right_in[1]:4 0.0008304996 +5 chanx_right_in[1]:5 0.0002241805 +6 chanx_right_in[1]:6 0.0001961 +7 chanx_right_in[1]:7 0.0001981309 +8 chanx_right_in[1]:8 0.0001981309 +9 chanx_right_in[1]:9 0.002661154 +10 chanx_right_in[1]:10 0.002661154 +11 chanx_right_in[1]:11 0.001398741 +12 chanx_right_in[1]:12 0.001398741 +13 chanx_right_in[1]:13 0.0005223039 +14 chanx_right_in[1]:14 0.000564324 +15 chanx_right_in[1]:15 0.0001417566 +16 chanx_right_in[1]:6 chany_bottom_in[13]:7 0.0001574111 +17 chanx_right_in[1]:9 chany_bottom_in[13]:4 5.032742e-05 +18 chanx_right_in[1]:10 chany_bottom_in[13]:3 5.032742e-05 +19 chanx_right_in[1]:3 chany_bottom_in[13]:10 8.8085e-06 +20 chanx_right_in[1]:3 chany_bottom_in[13]:8 8.59834e-05 +21 chanx_right_in[1]:4 chany_bottom_in[13]:7 8.59834e-05 +22 chanx_right_in[1]:4 chany_bottom_in[13]:9 8.8085e-06 +23 chanx_right_in[1]:5 chany_bottom_in[13]:8 0.0001574111 +24 chanx_right_in[1]:9 optlc_net_167:24 4.024678e-05 +25 chanx_right_in[1]:9 optlc_net_167:25 0.0002285396 +26 chanx_right_in[1]:10 optlc_net_167:16 0.0002285396 +27 chanx_right_in[1]:10 optlc_net_167:25 4.024678e-05 + +*RES +0 chanx_right_in[1] chanx_right_in[1]:15 0.0002397 +1 chanx_right_in[1]:2 mux_bottom_track_35\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[1]:6 chanx_right_in[1]:5 0.00365625 +3 chanx_right_in[1]:7 chanx_right_in[1]:6 0.0045 +4 chanx_right_in[1]:9 chanx_right_in[1]:8 0.0045 +5 chanx_right_in[1]:8 chanx_right_in[1]:7 0.002651786 +6 chanx_right_in[1]:10 chanx_right_in[1]:9 0.04016965 +7 chanx_right_in[1]:11 chanx_right_in[1]:10 0.0045 +8 chanx_right_in[1]:12 chanx_right_in[1]:11 0.02540849 +9 chanx_right_in[1]:13 chanx_right_in[1]:12 0.00341 +10 chanx_right_in[1]:3 chanx_right_in[1]:2 0.0003035715 +11 chanx_right_in[1]:4 chanx_right_in[1]:3 0.01108929 +12 chanx_right_in[1]:5 chanx_right_in[1]:4 0.0003035715 +13 chanx_right_in[1]:14 chanx_right_in[1]:13 0.001223958 +14 chanx_right_in[1]:15 chanx_right_in[1]:14 0.0001065333 + +*END + +*D_NET chanx_right_in[11] 0.007675008 //LENGTH 73.690 LUMPCC 0.0002621778 DR + +*CONN +*P chanx_right_in[11] I *L 0.29796 *C 140.382 58.480 +*I mux_bottom_track_29\/mux_l1_in_0_:A1 I *L 0.00198 *C 106.820 20.060 +*N chanx_right_in[11]:2 *C 106.720 20.060 +*N chanx_right_in[11]:3 *C 106.720 20.105 +*N chanx_right_in[11]:4 *C 106.720 27.835 +*N chanx_right_in[11]:5 *C 106.765 27.880 +*N chanx_right_in[11]:6 *C 132.480 27.880 +*N chanx_right_in[11]:7 *C 132.480 28.900 +*N chanx_right_in[11]:8 *C 139.795 28.900 +*N chanx_right_in[11]:9 *C 139.840 28.945 +*N chanx_right_in[11]:10 *C 139.840 58.480 +*N chanx_right_in[11]:11 *C 140.300 58.480 +*N chanx_right_in[11]:12 *C 140.300 58.480 + +*CAP +0 chanx_right_in[11] 2.566949e-05 +1 mux_bottom_track_29\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[11]:2 3.190436e-05 +3 chanx_right_in[11]:3 0.0004215399 +4 chanx_right_in[11]:4 0.0004215399 +5 chanx_right_in[11]:5 0.001457041 +6 chanx_right_in[11]:6 0.001510267 +7 chanx_right_in[11]:7 0.000443173 +8 chanx_right_in[11]:8 0.0003899474 +9 chanx_right_in[11]:9 0.001299005 +10 chanx_right_in[11]:10 0.001327855 +11 chanx_right_in[11]:11 5.821881e-05 +12 chanx_right_in[11]:12 2.566949e-05 +13 chanx_right_in[11]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001310889 +14 chanx_right_in[11]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001310889 + +*RES +0 chanx_right_in[11] chanx_right_in[11]:12 2.35e-05 +1 chanx_right_in[11]:2 mux_bottom_track_29\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[11]:3 chanx_right_in[11]:2 0.0045 +3 chanx_right_in[11]:5 chanx_right_in[11]:4 0.0045 +4 chanx_right_in[11]:4 chanx_right_in[11]:3 0.006901786 +5 chanx_right_in[11]:8 chanx_right_in[11]:7 0.006531251 +6 chanx_right_in[11]:9 chanx_right_in[11]:8 0.0045 +7 chanx_right_in[11]:11 chanx_right_in[11]:10 0.0004107143 +8 chanx_right_in[11]:12 chanx_right_in[11]:11 0.00341 +9 chanx_right_in[11]:6 chanx_right_in[11]:5 0.02295982 +10 chanx_right_in[11]:7 chanx_right_in[11]:6 0.0009107144 +11 chanx_right_in[11]:10 chanx_right_in[11]:9 0.02637054 + +*END + +*D_NET chany_bottom_in[3] 0.01299532 //LENGTH 88.815 LUMPCC 0.005302958 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 88.320 1.290 +*I mux_left_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 66.240 56.100 +*I mux_right_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 91.715 55.080 +*N chany_bottom_in[3]:3 *C 91.678 55.080 +*N chany_bottom_in[3]:4 *C 91.125 55.080 +*N chany_bottom_in[3]:5 *C 91.080 55.125 +*N chany_bottom_in[3]:6 *C 91.080 57.062 +*N chany_bottom_in[3]:7 *C 91.073 57.120 +*N chany_bottom_in[3]:8 *C 66.278 56.100 +*N chany_bottom_in[3]:9 *C 69.875 56.100 +*N chany_bottom_in[3]:10 *C 69.920 56.100 +*N chany_bottom_in[3]:11 *C 71.760 56.100 +*N chany_bottom_in[3]:12 *C 71.760 57.062 +*N chany_bottom_in[3]:13 *C 71.767 57.120 +*N chany_bottom_in[3]:14 *C 90.160 57.120 +*N chany_bottom_in[3]:15 *C 90.160 57.113 +*N chany_bottom_in[3]:16 *C 90.160 2.728 +*N chany_bottom_in[3]:17 *C 90.140 2.720 +*N chany_bottom_in[3]:18 *C 88.328 2.720 +*N chany_bottom_in[3]:19 *C 88.320 2.663 + +*CAP +0 chany_bottom_in[3] 9.406542e-05 +1 mux_left_track_17\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[3]:3 7.717389e-05 +4 chany_bottom_in[3]:4 7.717389e-05 +5 chany_bottom_in[3]:5 0.0001581549 +6 chany_bottom_in[3]:6 0.0001581549 +7 chany_bottom_in[3]:7 4.191489e-05 +8 chany_bottom_in[3]:8 0.0002870436 +9 chany_bottom_in[3]:9 0.0002870436 +10 chany_bottom_in[3]:10 0.0001333521 +11 chany_bottom_in[3]:11 0.0001679051 +12 chany_bottom_in[3]:12 6.93698e-05 +13 chany_bottom_in[3]:13 0.0004192988 +14 chany_bottom_in[3]:14 0.0004612136 +15 chany_bottom_in[3]:15 0.002452373 +16 chany_bottom_in[3]:16 0.002452373 +17 chany_bottom_in[3]:17 0.0001298411 +18 chany_bottom_in[3]:18 0.0001298411 +19 chany_bottom_in[3]:19 9.406542e-05 +20 chany_bottom_in[3]:12 chanx_left_in[16]:34 2.857674e-07 +21 chany_bottom_in[3]:13 chanx_left_in[16]:31 0.0008473633 +22 chany_bottom_in[3]:13 chanx_left_in[16]:32 0.000159602 +23 chany_bottom_in[3]:10 chanx_left_in[16]:32 1.381927e-05 +24 chany_bottom_in[3]:7 chanx_left_in[16]:22 5.993462e-05 +25 chany_bottom_in[3]:14 chanx_left_in[16]:22 0.0008473633 +26 chany_bottom_in[3]:14 chanx_left_in[16]:31 0.0002195366 +27 chany_bottom_in[3]:11 chanx_left_in[16]:31 1.381927e-05 +28 chany_bottom_in[3]:11 chanx_left_in[16]:33 2.857674e-07 +29 chany_bottom_in[3]:13 chanx_left_in[17]:31 0.0009687199 +30 chany_bottom_in[3]:14 chanx_left_in[17]:30 0.0009687199 +31 chany_bottom_in[3]:15 chany_bottom_in[2]:15 0.0006017539 +32 chany_bottom_in[3]:16 chany_bottom_in[2]:16 0.0006017539 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:19 0.001225446 +1 chany_bottom_in[3]:12 chany_bottom_in[3]:11 0.0008593751 +2 chany_bottom_in[3]:13 chany_bottom_in[3]:12 0.00341 +3 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.003212054 +4 chany_bottom_in[3]:10 chany_bottom_in[3]:9 0.0045 +5 chany_bottom_in[3]:8 mux_left_track_17\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.001729911 +7 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.00341 +8 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.0004933036 +9 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.0045 +10 chany_bottom_in[3]:3 mux_right_track_4\/mux_l1_in_0_:A0 0.152 +11 chany_bottom_in[3]:14 chany_bottom_in[3]:13 0.002881492 +12 chany_bottom_in[3]:14 chany_bottom_in[3]:7 0.0001429583 +13 chany_bottom_in[3]:15 chany_bottom_in[3]:14 0.00341 +14 chany_bottom_in[3]:17 chany_bottom_in[3]:16 0.00341 +15 chany_bottom_in[3]:16 chany_bottom_in[3]:15 0.008520316 +16 chany_bottom_in[3]:19 chany_bottom_in[3]:18 0.00341 +17 chany_bottom_in[3]:18 chany_bottom_in[3]:17 0.0002839583 +18 chany_bottom_in[3]:11 chany_bottom_in[3]:10 0.001642857 + +*END + +*D_NET chany_bottom_in[16] 0.01598517 //LENGTH 93.175 LUMPCC 0.00264505 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 76.820 1.290 +*I mux_left_track_9\/mux_l1_in_2_:A1 I *L 0.00198 *C 62.560 50.660 +*I mux_right_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 84.355 55.420 +*N chany_bottom_in[16]:3 *C 83.930 10.200 +*N chany_bottom_in[16]:4 *C 84.230 55.420 +*N chany_bottom_in[16]:5 *C 62.560 50.660 +*N chany_bottom_in[16]:6 *C 62.560 50.705 +*N chany_bottom_in[16]:7 *C 62.560 52.303 +*N chany_bottom_in[16]:8 *C 62.568 52.360 +*N chany_bottom_in[16]:9 *C 78.653 52.360 +*N chany_bottom_in[16]:10 *C 78.660 52.418 +*N chany_bottom_in[16]:11 *C 78.660 55.375 +*N chany_bottom_in[16]:12 *C 78.705 55.420 +*N chany_bottom_in[16]:13 *C 84.135 55.420 +*N chany_bottom_in[16]:14 *C 84.180 55.375 +*N chany_bottom_in[16]:15 *C 84.180 51.738 +*N chany_bottom_in[16]:16 *C 84.183 51.680 +*N chany_bottom_in[16]:17 *C 84.625 51.680 +*N chany_bottom_in[16]:18 *C 84.640 51.672 +*N chany_bottom_in[16]:19 *C 84.640 10.208 +*N chany_bottom_in[16]:20 *C 84.638 10.200 +*N chany_bottom_in[16]:21 *C 84.640 10.143 +*N chany_bottom_in[16]:22 *C 84.640 2.085 +*N chany_bottom_in[16]:23 *C 84.595 2.040 +*N chany_bottom_in[16]:24 *C 76.865 2.040 +*N chany_bottom_in[16]:25 *C 76.820 1.995 + +*CAP +0 chany_bottom_in[16] 6.334656e-05 +1 mux_left_track_9\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_1_:A0 1e-06 +3 chany_bottom_in[16]:3 9.908085e-05 +4 chany_bottom_in[16]:4 2.818602e-05 +5 chany_bottom_in[16]:5 3.500994e-05 +6 chany_bottom_in[16]:6 0.0001135924 +7 chany_bottom_in[16]:7 0.0001135924 +8 chany_bottom_in[16]:8 0.001043571 +9 chany_bottom_in[16]:9 0.001043571 +10 chany_bottom_in[16]:10 0.00018595 +11 chany_bottom_in[16]:11 0.00018595 +12 chany_bottom_in[16]:12 0.0004415023 +13 chany_bottom_in[16]:13 0.0004696883 +14 chany_bottom_in[16]:14 0.0001570227 +15 chany_bottom_in[16]:15 0.0001570227 +16 chany_bottom_in[16]:16 4.673446e-05 +17 chany_bottom_in[16]:17 4.673446e-05 +18 chany_bottom_in[16]:18 0.003399309 +19 chany_bottom_in[16]:19 0.003399309 +20 chany_bottom_in[16]:20 9.908085e-05 +21 chany_bottom_in[16]:21 0.0005027272 +22 chany_bottom_in[16]:22 0.0005027272 +23 chany_bottom_in[16]:23 0.0005705362 +24 chany_bottom_in[16]:24 0.0005705362 +25 chany_bottom_in[16]:25 6.334656e-05 +26 chany_bottom_in[16]:8 prog_clk[0]:406 0.0001136811 +27 chany_bottom_in[16]:9 prog_clk[0]:401 0.0001136811 +28 chany_bottom_in[16]:14 prog_clk[0]:263 0.0001056778 +29 chany_bottom_in[16]:15 prog_clk[0]:264 0.0001056778 +30 chany_bottom_in[16]:16 prog_clk[0]:225 1.209991e-07 +31 chany_bottom_in[16]:16 prog_clk[0]:265 1.581261e-05 +32 chany_bottom_in[16]:17 prog_clk[0]:224 1.209991e-07 +33 chany_bottom_in[16]:17 prog_clk[0]:229 1.581261e-05 +34 chany_bottom_in[16]:18 prog_clk[0]:266 7.267312e-05 +35 chany_bottom_in[16]:19 prog_clk[0]:267 7.267312e-05 +36 chany_bottom_in[16]:18 chany_bottom_in[0]:9 0.0005824505 +37 chany_bottom_in[16]:19 chany_bottom_in[0]:10 0.0005824505 +38 chany_bottom_in[16]:21 ropt_net_179:3 9.539266e-05 +39 chany_bottom_in[16]:22 ropt_net_179:4 9.539266e-05 +40 chany_bottom_in[16]:8 mux_tree_tapbuf_size5_4_sram[2]:12 0.0003329184 +41 chany_bottom_in[16]:10 mux_tree_tapbuf_size5_4_sram[2]:14 3.797365e-06 +42 chany_bottom_in[16]:9 mux_tree_tapbuf_size5_4_sram[2]:13 0.0003329184 +43 chany_bottom_in[16]:11 mux_tree_tapbuf_size5_4_sram[2]:15 3.797365e-06 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:25 0.0006294643 +1 chany_bottom_in[16]:5 mux_left_track_9\/mux_l1_in_2_:A1 0.152 +2 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.0045 +3 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.001426339 +4 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.00341 +5 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.00341 +6 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.002519983 +7 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.0045 +8 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.002640625 +9 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.004848215 +10 chany_bottom_in[16]:13 chany_bottom_in[16]:4 8.482143e-05 +11 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.0045 +12 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.003247768 +13 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.00341 +14 chany_bottom_in[16]:17 chany_bottom_in[16]:16 6.499218e-05 +15 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.00341 +16 chany_bottom_in[16]:20 chany_bottom_in[16]:19 0.00341 +17 chany_bottom_in[16]:20 chany_bottom_in[16]:3 0.0001039141 +18 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.006496183 +19 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.00341 +20 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.0045 +21 chany_bottom_in[16]:22 chany_bottom_in[16]:21 0.007194197 +22 chany_bottom_in[16]:24 chany_bottom_in[16]:23 0.006901786 +23 chany_bottom_in[16]:25 chany_bottom_in[16]:24 0.0045 +24 chany_bottom_in[16]:4 mux_right_track_8\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET chanx_left_in[7] 0.005431233 //LENGTH 45.970 LUMPCC 0.001082391 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 72.080 +*I mux_bottom_track_5\/mux_l1_in_3_:A1 I *L 0.00198 *C 29.080 56.100 +*N chanx_left_in[7]:2 *C 29.043 56.100 +*N chanx_left_in[7]:3 *C 28.520 56.100 +*N chanx_left_in[7]:4 *C 28.520 55.760 +*N chanx_left_in[7]:5 *C 27.185 55.760 +*N chanx_left_in[7]:6 *C 27.140 55.760 +*N chanx_left_in[7]:7 *C 27.133 55.760 +*N chanx_left_in[7]:8 *C 11.060 55.760 +*N chanx_left_in[7]:9 *C 11.040 55.768 +*N chanx_left_in[7]:10 *C 11.040 72.073 +*N chanx_left_in[7]:11 *C 11.020 72.080 + +*CAP +0 chanx_left_in[7] 0.0005764275 +1 mux_bottom_track_5\/mux_l1_in_3_:A1 1e-06 +2 chanx_left_in[7]:2 5.261713e-05 +3 chanx_left_in[7]:3 7.845453e-05 +4 chanx_left_in[7]:4 0.0001343285 +5 chanx_left_in[7]:5 0.0001084911 +6 chanx_left_in[7]:6 3.97603e-05 +7 chanx_left_in[7]:7 0.0004911936 +8 chanx_left_in[7]:8 0.0004911936 +9 chanx_left_in[7]:9 0.0008994738 +10 chanx_left_in[7]:10 0.0008994738 +11 chanx_left_in[7]:11 0.0005764275 +12 chanx_left_in[7]:7 chanx_right_in[13]:23 0.0002862325 +13 chanx_left_in[7]:8 chanx_right_in[13]:22 0.0002862325 +14 chanx_left_in[7]:7 chanx_left_in[17]:31 0.0002549632 +15 chanx_left_in[7]:8 chanx_left_in[17]:32 0.0002549632 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:11 0.001533767 +1 chanx_left_in[7]:2 mux_bottom_track_5\/mux_l1_in_3_:A1 0.152 +2 chanx_left_in[7]:5 chanx_left_in[7]:4 0.001191964 +3 chanx_left_in[7]:6 chanx_left_in[7]:5 0.0045 +4 chanx_left_in[7]:7 chanx_left_in[7]:6 0.00341 +5 chanx_left_in[7]:8 chanx_left_in[7]:7 0.002518025 +6 chanx_left_in[7]:9 chanx_left_in[7]:8 0.00341 +7 chanx_left_in[7]:11 chanx_left_in[7]:10 0.00341 +8 chanx_left_in[7]:10 chanx_left_in[7]:9 0.00255445 +9 chanx_left_in[7]:4 chanx_left_in[7]:3 0.0003035715 +10 chanx_left_in[7]:3 chanx_left_in[7]:2 0.0004665179 + +*END + +*D_NET chanx_right_out[8] 0.003706608 //LENGTH 32.580 LUMPCC 0.001364053 DR + +*CONN +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 127.480 66.640 +*P chanx_right_out[8] O *L 0.7423 *C 140.450 85.680 +*N chanx_right_out[8]:2 *C 127.428 85.680 +*N chanx_right_out[8]:3 *C 127.420 85.623 +*N chanx_right_out[8]:4 *C 127.420 66.685 +*N chanx_right_out[8]:5 *C 127.420 66.640 + +*CAP +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[8] 0.0004382217 +2 chanx_right_out[8]:2 0.0004382217 +3 chanx_right_out[8]:3 0.0007172845 +4 chanx_right_out[8]:4 0.0007172845 +5 chanx_right_out[8]:5 3.054334e-05 +6 chanx_right_out[8]:4 chanx_left_in[6]:8 0.0002599902 +7 chanx_right_out[8]:3 chanx_left_in[6]:7 0.0002599902 +8 chanx_right_out[8] chanx_right_in[0] 0.0003275266 +9 chanx_right_out[8]:2 chanx_right_in[0]:10 0.0003275266 +10 chanx_right_out[8] ropt_net_183:5 9.450944e-05 +11 chanx_right_out[8]:2 ropt_net_183:6 9.450944e-05 + +*RES +0 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[8]:5 0.152 +1 chanx_right_out[8]:5 chanx_right_out[8]:4 0.0045 +2 chanx_right_out[8]:4 chanx_right_out[8]:3 0.01690848 +3 chanx_right_out[8]:3 chanx_right_out[8]:2 0.00341 +4 chanx_right_out[8]:2 chanx_right_out[8] 0.002040192 + +*END + +*D_NET chany_bottom_out[12] 0.003957324 //LENGTH 33.355 LUMPCC 0.0001857924 DR + +*CONN +*I mux_bottom_track_25\/mux_l3_in_0_:X O *L 0 *C 88.540 25.500 +*P chany_bottom_out[12] O *L 0.7423 *C 80.500 1.290 +*N chany_bottom_out[12]:2 *C 80.500 9.815 +*N chany_bottom_out[12]:3 *C 80.545 9.860 +*N chany_bottom_out[12]:4 *C 86.435 9.860 +*N chany_bottom_out[12]:5 *C 86.480 9.905 +*N chany_bottom_out[12]:6 *C 86.480 25.455 +*N chany_bottom_out[12]:7 *C 86.525 25.500 +*N chany_bottom_out[12]:8 *C 88.502 25.500 + +*CAP +0 mux_bottom_track_25\/mux_l3_in_0_:X 1e-06 +1 chany_bottom_out[12] 0.0005216434 +2 chany_bottom_out[12]:2 0.0005216434 +3 chany_bottom_out[12]:3 0.0004270761 +4 chany_bottom_out[12]:4 0.0004270761 +5 chany_bottom_out[12]:5 0.0008010105 +6 chany_bottom_out[12]:6 0.0008010105 +7 chany_bottom_out[12]:7 0.0001355357 +8 chany_bottom_out[12]:8 0.0001355357 +9 chany_bottom_out[12]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.28962e-05 +10 chany_bottom_out[12]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.28962e-05 + +*RES +0 mux_bottom_track_25\/mux_l3_in_0_:X chany_bottom_out[12]:8 0.152 +1 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +2 chany_bottom_out[12]:2 chany_bottom_out[12] 0.007611607 +3 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.005258929 +4 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0045 +5 chany_bottom_out[12]:7 chany_bottom_out[12]:6 0.0045 +6 chany_bottom_out[12]:6 chany_bottom_out[12]:5 0.01388393 +7 chany_bottom_out[12]:8 chany_bottom_out[12]:7 0.001765625 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.001312483 //LENGTH 10.715 LUMPCC 0.000252365 DR + +*CONN +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 108.865 17.340 +*I mem_bottom_track_29\/FTB_29__54:A I *L 0.001746 *C 103.500 14.960 +*I mux_bottom_track_29\/mux_l2_in_0_:S I *L 0.00357 *C 106.360 12.920 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 106.260 12.920 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 106.260 12.965 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 103.538 14.960 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 106.215 14.960 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 106.260 14.960 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 106.260 17.295 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 106.305 17.340 +*N mux_tree_tapbuf_size2_1_sram[1]:10 *C 108.828 17.340 + +*CAP +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_29\/FTB_29__54:A 1e-06 +2 mux_bottom_track_29\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 2.956818e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:4 7.375209e-05 +5 mux_tree_tapbuf_size2_1_sram[1]:5 0.0001636554 +6 mux_tree_tapbuf_size2_1_sram[1]:6 0.0001636554 +7 mux_tree_tapbuf_size2_1_sram[1]:7 0.0001965466 +8 mux_tree_tapbuf_size2_1_sram[1]:8 9.192932e-05 +9 mux_tree_tapbuf_size2_1_sram[1]:9 0.0001690055 +10 mux_tree_tapbuf_size2_1_sram[1]:10 0.0001690055 +11 mux_tree_tapbuf_size2_1_sram[1]:7 optlc_net_167:23 5.876407e-05 +12 mux_tree_tapbuf_size2_1_sram[1]:7 optlc_net_167:22 6.741843e-05 +13 mux_tree_tapbuf_size2_1_sram[1]:8 optlc_net_167:23 6.741843e-05 +14 mux_tree_tapbuf_size2_1_sram[1]:4 optlc_net_167:22 5.876407e-05 + +*RES +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:6 mux_tree_tapbuf_size2_1_sram[1]:5 0.002390625 +2 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:4 0.00178125 +4 mux_tree_tapbuf_size2_1_sram[1]:5 mem_bottom_track_29\/FTB_29__54:A 0.152 +5 mux_tree_tapbuf_size2_1_sram[1]:9 mux_tree_tapbuf_size2_1_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.002084821 +7 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:9 0.002252232 +8 mux_tree_tapbuf_size2_1_sram[1]:3 mux_bottom_track_29\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_1_sram[1]:4 mux_tree_tapbuf_size2_1_sram[1]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[1] 0.001493994 //LENGTH 11.895 LUMPCC 0.0001034308 DR + +*CONN +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 48.605 9.860 +*I mux_bottom_track_39\/mux_l2_in_0_:S I *L 0.00357 *C 53.720 9.230 +*I mem_bottom_track_39\/FTB_34__59:A I *L 0.001746 *C 55.660 12.240 +*N mux_tree_tapbuf_size2_6_sram[1]:3 *C 55.660 12.240 +*N mux_tree_tapbuf_size2_6_sram[1]:4 *C 55.660 12.195 +*N mux_tree_tapbuf_size2_6_sram[1]:5 *C 55.660 10.245 +*N mux_tree_tapbuf_size2_6_sram[1]:6 *C 55.615 10.200 +*N mux_tree_tapbuf_size2_6_sram[1]:7 *C 53.360 10.200 +*N mux_tree_tapbuf_size2_6_sram[1]:8 *C 53.720 9.230 +*N mux_tree_tapbuf_size2_6_sram[1]:9 *C 53.750 9.450 +*N mux_tree_tapbuf_size2_6_sram[1]:10 *C 53.865 9.590 +*N mux_tree_tapbuf_size2_6_sram[1]:11 *C 53.820 9.860 +*N mux_tree_tapbuf_size2_6_sram[1]:12 *C 53.360 9.860 +*N mux_tree_tapbuf_size2_6_sram[1]:13 *C 48.643 9.860 + +*CAP +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_39\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_39\/FTB_34__59:A 1e-06 +3 mux_tree_tapbuf_size2_6_sram[1]:3 3.36618e-05 +4 mux_tree_tapbuf_size2_6_sram[1]:4 0.0001266665 +5 mux_tree_tapbuf_size2_6_sram[1]:5 0.0001266665 +6 mux_tree_tapbuf_size2_6_sram[1]:6 0.0001757147 +7 mux_tree_tapbuf_size2_6_sram[1]:7 0.0002006399 +8 mux_tree_tapbuf_size2_6_sram[1]:8 6.158221e-05 +9 mux_tree_tapbuf_size2_6_sram[1]:9 3.223261e-05 +10 mux_tree_tapbuf_size2_6_sram[1]:10 2.998909e-05 +11 mux_tree_tapbuf_size2_6_sram[1]:11 4.31518e-05 +12 mux_tree_tapbuf_size2_6_sram[1]:12 0.0002988654 +13 mux_tree_tapbuf_size2_6_sram[1]:13 0.0002583925 +14 mux_tree_tapbuf_size2_6_sram[1]:13 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.17154e-05 +15 mux_tree_tapbuf_size2_6_sram[1]:12 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.17154e-05 + +*RES +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_6_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_6_sram[1]:8 mux_bottom_track_39\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_6_sram[1]:4 0.001741072 +4 mux_tree_tapbuf_size2_6_sram[1]:3 mem_bottom_track_39\/FTB_34__59:A 0.152 +5 mux_tree_tapbuf_size2_6_sram[1]:4 mux_tree_tapbuf_size2_6_sram[1]:3 0.0045 +6 mux_tree_tapbuf_size2_6_sram[1]:13 mux_tree_tapbuf_size2_6_sram[1]:12 0.004212053 +7 mux_tree_tapbuf_size2_6_sram[1]:12 mux_tree_tapbuf_size2_6_sram[1]:11 0.0004107143 +8 mux_tree_tapbuf_size2_6_sram[1]:12 mux_tree_tapbuf_size2_6_sram[1]:7 0.0003035715 +9 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[1]:10 0.0002410715 +10 mux_tree_tapbuf_size2_6_sram[1]:7 mux_tree_tapbuf_size2_6_sram[1]:6 0.002013393 +11 mux_tree_tapbuf_size2_6_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:8 0.000127907 +12 mux_tree_tapbuf_size2_6_sram[1]:10 mux_tree_tapbuf_size2_6_sram[1]:9 0.0001026786 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[0] 0.002602549 //LENGTH 18.095 LUMPCC 0.0001352664 DR + +*CONN +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.465 23.120 +*I mux_bottom_track_19\/mux_l1_in_1_:S I *L 0.00357 *C 59.800 28.730 +*I mux_bottom_track_19\/mux_l1_in_0_:S I *L 0.00357 *C 62.200 25.550 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.495 28.220 +*N mux_tree_tapbuf_size3_4_sram[0]:4 *C 65.495 28.220 +*N mux_tree_tapbuf_size3_4_sram[0]:5 *C 65.780 28.220 +*N mux_tree_tapbuf_size3_4_sram[0]:6 *C 65.780 28.175 +*N mux_tree_tapbuf_size3_4_sram[0]:7 *C 62.200 25.550 +*N mux_tree_tapbuf_size3_4_sram[0]:8 *C 59.800 28.730 +*N mux_tree_tapbuf_size3_4_sram[0]:9 *C 59.800 28.560 +*N mux_tree_tapbuf_size3_4_sram[0]:10 *C 59.800 28.515 +*N mux_tree_tapbuf_size3_4_sram[0]:11 *C 59.800 25.885 +*N mux_tree_tapbuf_size3_4_sram[0]:12 *C 59.845 25.840 +*N mux_tree_tapbuf_size3_4_sram[0]:13 *C 62.090 25.840 +*N mux_tree_tapbuf_size3_4_sram[0]:14 *C 65.735 25.840 +*N mux_tree_tapbuf_size3_4_sram[0]:15 *C 65.780 25.840 +*N mux_tree_tapbuf_size3_4_sram[0]:16 *C 65.780 23.165 +*N mux_tree_tapbuf_size3_4_sram[0]:17 *C 65.825 23.120 +*N mux_tree_tapbuf_size3_4_sram[0]:18 *C 67.428 23.120 + +*CAP +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_19\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_19\/mux_l1_in_0_:S 1e-06 +3 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_4_sram[0]:4 5.262151e-05 +5 mux_tree_tapbuf_size3_4_sram[0]:5 5.987102e-05 +6 mux_tree_tapbuf_size3_4_sram[0]:6 0.0001387703 +7 mux_tree_tapbuf_size3_4_sram[0]:7 5.961239e-05 +8 mux_tree_tapbuf_size3_4_sram[0]:8 4.349999e-05 +9 mux_tree_tapbuf_size3_4_sram[0]:9 4.807508e-05 +10 mux_tree_tapbuf_size3_4_sram[0]:10 0.0001916609 +11 mux_tree_tapbuf_size3_4_sram[0]:11 0.0001916609 +12 mux_tree_tapbuf_size3_4_sram[0]:12 0.0001276231 +13 mux_tree_tapbuf_size3_4_sram[0]:13 0.0004733106 +14 mux_tree_tapbuf_size3_4_sram[0]:14 0.0003154032 +15 mux_tree_tapbuf_size3_4_sram[0]:15 0.0003211514 +16 mux_tree_tapbuf_size3_4_sram[0]:16 0.0001501346 +17 mux_tree_tapbuf_size3_4_sram[0]:17 0.0001449438 +18 mux_tree_tapbuf_size3_4_sram[0]:18 0.0001449438 +19 mux_tree_tapbuf_size3_4_sram[0]:12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.763321e-05 +20 mux_tree_tapbuf_size3_4_sram[0]:13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.763321e-05 + +*RES +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_4_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_4_sram[0]:14 mux_tree_tapbuf_size3_4_sram[0]:13 0.003254465 +2 mux_tree_tapbuf_size3_4_sram[0]:15 mux_tree_tapbuf_size3_4_sram[0]:14 0.0045 +3 mux_tree_tapbuf_size3_4_sram[0]:15 mux_tree_tapbuf_size3_4_sram[0]:6 0.002084821 +4 mux_tree_tapbuf_size3_4_sram[0]:17 mux_tree_tapbuf_size3_4_sram[0]:16 0.0045 +5 mux_tree_tapbuf_size3_4_sram[0]:16 mux_tree_tapbuf_size3_4_sram[0]:15 0.002388393 +6 mux_tree_tapbuf_size3_4_sram[0]:18 mux_tree_tapbuf_size3_4_sram[0]:17 0.001430804 +7 mux_tree_tapbuf_size3_4_sram[0]:12 mux_tree_tapbuf_size3_4_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:10 0.002348214 +9 mux_tree_tapbuf_size3_4_sram[0]:9 mux_tree_tapbuf_size3_4_sram[0]:8 7.327587e-05 +10 mux_tree_tapbuf_size3_4_sram[0]:10 mux_tree_tapbuf_size3_4_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size3_4_sram[0]:8 mux_bottom_track_19\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size3_4_sram[0]:5 mux_tree_tapbuf_size3_4_sram[0]:4 0.0001548913 +13 mux_tree_tapbuf_size3_4_sram[0]:6 mux_tree_tapbuf_size3_4_sram[0]:5 0.0045 +14 mux_tree_tapbuf_size3_4_sram[0]:4 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size3_4_sram[0]:7 mux_bottom_track_19\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size3_4_sram[0]:13 mux_tree_tapbuf_size3_4_sram[0]:12 0.002004464 +17 mux_tree_tapbuf_size3_4_sram[0]:13 mux_tree_tapbuf_size3_4_sram[0]:7 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_0_ccff_tail[0] 0.0002739551 //LENGTH 2.070 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/FTB_24__49:X O *L 0 *C 23.235 75.140 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 25.015 75.140 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 *C 24.978 75.140 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 *C 23.273 75.140 + +*CAP +0 mem_bottom_track_9\/FTB_24__49:X 1e-06 +1 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 0.0001359775 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.0001359775 + +*RES +0 mem_bottom_track_9\/FTB_24__49:X mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 0.001522322 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[0] 0.002159634 //LENGTH 17.655 LUMPCC 0 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 101.045 44.540 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 97.695 42.500 +*I mux_right_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 92.360 40.120 +*I mux_right_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 91.440 44.880 +*N mux_tree_tapbuf_size5_2_sram[0]:4 *C 91.478 44.880 +*N mux_tree_tapbuf_size5_2_sram[0]:5 *C 92.415 44.880 +*N mux_tree_tapbuf_size5_2_sram[0]:6 *C 92.460 44.835 +*N mux_tree_tapbuf_size5_2_sram[0]:7 *C 92.360 40.120 +*N mux_tree_tapbuf_size5_2_sram[0]:8 *C 92.460 40.165 +*N mux_tree_tapbuf_size5_2_sram[0]:9 *C 92.460 42.500 +*N mux_tree_tapbuf_size5_2_sram[0]:10 *C 92.505 42.500 +*N mux_tree_tapbuf_size5_2_sram[0]:11 *C 97.695 42.500 +*N mux_tree_tapbuf_size5_2_sram[0]:12 *C 100.695 42.500 +*N mux_tree_tapbuf_size5_2_sram[0]:13 *C 100.740 42.545 +*N mux_tree_tapbuf_size5_2_sram[0]:14 *C 100.740 44.495 +*N mux_tree_tapbuf_size5_2_sram[0]:15 *C 100.740 44.540 +*N mux_tree_tapbuf_size5_2_sram[0]:16 *C 101.045 44.540 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:S 1e-06 +3 mux_right_track_24\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_2_sram[0]:4 8.420949e-05 +5 mux_tree_tapbuf_size5_2_sram[0]:5 8.420949e-05 +6 mux_tree_tapbuf_size5_2_sram[0]:6 0.0001276373 +7 mux_tree_tapbuf_size5_2_sram[0]:7 2.736982e-05 +8 mux_tree_tapbuf_size5_2_sram[0]:8 0.0001270696 +9 mux_tree_tapbuf_size5_2_sram[0]:9 0.0002852875 +10 mux_tree_tapbuf_size5_2_sram[0]:10 0.0003253061 +11 mux_tree_tapbuf_size5_2_sram[0]:11 0.0005425633 +12 mux_tree_tapbuf_size5_2_sram[0]:12 0.000190895 +13 mux_tree_tapbuf_size5_2_sram[0]:13 0.000128306 +14 mux_tree_tapbuf_size5_2_sram[0]:14 0.000128306 +15 mux_tree_tapbuf_size5_2_sram[0]:15 5.331894e-05 +16 mux_tree_tapbuf_size5_2_sram[0]:16 5.115556e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_2_sram[0]:16 0.152 +1 mux_tree_tapbuf_size5_2_sram[0]:10 mux_tree_tapbuf_size5_2_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size5_2_sram[0]:9 mux_tree_tapbuf_size5_2_sram[0]:8 0.002084821 +3 mux_tree_tapbuf_size5_2_sram[0]:9 mux_tree_tapbuf_size5_2_sram[0]:6 0.002084822 +4 mux_tree_tapbuf_size5_2_sram[0]:5 mux_tree_tapbuf_size5_2_sram[0]:4 0.0008370536 +5 mux_tree_tapbuf_size5_2_sram[0]:6 mux_tree_tapbuf_size5_2_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size5_2_sram[0]:4 mux_right_track_24\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size5_2_sram[0]:7 mux_right_track_24\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_2_sram[0]:8 mux_tree_tapbuf_size5_2_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size5_2_sram[0]:11 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size5_2_sram[0]:11 mux_tree_tapbuf_size5_2_sram[0]:10 0.004633929 +11 mux_tree_tapbuf_size5_2_sram[0]:12 mux_tree_tapbuf_size5_2_sram[0]:11 0.002678572 +12 mux_tree_tapbuf_size5_2_sram[0]:13 mux_tree_tapbuf_size5_2_sram[0]:12 0.0045 +13 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_2_sram[0]:14 0.0045 +14 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[0]:13 0.001741072 +15 mux_tree_tapbuf_size5_2_sram[0]:16 mux_tree_tapbuf_size5_2_sram[0]:15 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.005439687 //LENGTH 45.375 LUMPCC 0.000307025 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 109.785 82.620 +*I mux_right_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 85.920 74.800 +*I mux_right_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 87.760 85.000 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 94.010 80.580 +*I mux_right_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 112.800 77.520 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 112.763 77.520 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 109.065 77.520 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 109.020 77.565 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 94.010 80.595 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 87.760 85.000 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 87.860 84.955 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 85.958 74.800 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 87.815 74.800 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 87.860 74.845 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 87.860 80.920 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 87.905 80.920 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 94.010 80.920 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 108.975 80.920 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 109.020 80.920 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 109.020 82.575 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 109.065 82.620 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 109.748 82.620 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_0\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_0\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_track_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 0.0002398714 +6 mux_tree_tapbuf_size6_0_sram[0]:6 0.0002398714 +7 mux_tree_tapbuf_size6_0_sram[0]:7 0.0001492527 +8 mux_tree_tapbuf_size6_0_sram[0]:8 3.20947e-05 +9 mux_tree_tapbuf_size6_0_sram[0]:9 2.794342e-05 +10 mux_tree_tapbuf_size6_0_sram[0]:10 0.0001760436 +11 mux_tree_tapbuf_size6_0_sram[0]:11 0.0001155377 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.0001155377 +13 mux_tree_tapbuf_size6_0_sram[0]:13 0.0003136087 +14 mux_tree_tapbuf_size6_0_sram[0]:14 0.0005204652 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0003910539 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.001375898 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0009527499 +18 mux_tree_tapbuf_size6_0_sram[0]:18 0.0002710338 +19 mux_tree_tapbuf_size6_0_sram[0]:19 9.149703e-05 +20 mux_tree_tapbuf_size6_0_sram[0]:20 5.76013e-05 +21 mux_tree_tapbuf_size6_0_sram[0]:21 5.76013e-05 +22 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 6.126694e-05 +23 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 6.126694e-05 +24 mux_tree_tapbuf_size6_0_sram[0]:12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.207429e-05 +25 mux_tree_tapbuf_size6_0_sram[0]:11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.207429e-05 +26 mux_tree_tapbuf_size6_0_sram[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.017128e-05 +27 mux_tree_tapbuf_size6_0_sram[0]:18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.017128e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:21 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.0045 +2 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 0.005424107 +3 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:10 0.003602679 +4 mux_tree_tapbuf_size6_0_sram[0]:8 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +5 mux_tree_tapbuf_size6_0_sram[0]:6 mux_tree_tapbuf_size6_0_sram[0]:5 0.003301339 +6 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.0045 +7 mux_tree_tapbuf_size6_0_sram[0]:5 mux_right_track_0\/mux_l1_in_2_:S 0.152 +8 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.0045 +9 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.001477679 +10 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.000609375 +11 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.01336161 +12 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.0045 +13 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:7 0.002995536 +14 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 0.001658482 +15 mux_tree_tapbuf_size6_0_sram[0]:13 mux_tree_tapbuf_size6_0_sram[0]:12 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:11 mux_right_track_0\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size6_0_sram[0]:9 mux_right_track_0\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0045 +19 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.005450893 +20 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:8 0.0001766305 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[0] 0.004876611 //LENGTH 37.350 LUMPCC 0.0005810035 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 36.645 39.440 +*I mux_bottom_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 33.680 36.720 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 30.260 51.000 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 53.380 +*I mux_bottom_track_5\/mux_l1_in_3_:S I *L 0.00357 *C 29.800 56.100 +*I mux_bottom_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 31.180 42.160 +*N mux_tree_tapbuf_size7_2_sram[0]:6 *C 31.180 42.160 +*N mux_tree_tapbuf_size7_2_sram[0]:7 *C 29.838 56.100 +*N mux_tree_tapbuf_size7_2_sram[0]:8 *C 31.280 56.100 +*N mux_tree_tapbuf_size7_2_sram[0]:9 *C 32.835 53.380 +*N mux_tree_tapbuf_size7_2_sram[0]:10 *C 33.120 53.380 +*N mux_tree_tapbuf_size7_2_sram[0]:11 *C 33.120 53.425 +*N mux_tree_tapbuf_size7_2_sram[0]:12 *C 33.120 55.715 +*N mux_tree_tapbuf_size7_2_sram[0]:13 *C 33.075 55.760 +*N mux_tree_tapbuf_size7_2_sram[0]:14 *C 31.280 55.760 +*N mux_tree_tapbuf_size7_2_sram[0]:15 *C 31.280 55.715 +*N mux_tree_tapbuf_size7_2_sram[0]:16 *C 30.298 51.000 +*N mux_tree_tapbuf_size7_2_sram[0]:17 *C 31.235 51.000 +*N mux_tree_tapbuf_size7_2_sram[0]:18 *C 31.280 51.000 +*N mux_tree_tapbuf_size7_2_sram[0]:19 *C 31.280 42.885 +*N mux_tree_tapbuf_size7_2_sram[0]:20 *C 31.280 42.840 +*N mux_tree_tapbuf_size7_2_sram[0]:21 *C 35.375 42.840 +*N mux_tree_tapbuf_size7_2_sram[0]:22 *C 35.420 42.795 +*N mux_tree_tapbuf_size7_2_sram[0]:23 *C 33.718 36.720 +*N mux_tree_tapbuf_size7_2_sram[0]:24 *C 35.375 36.720 +*N mux_tree_tapbuf_size7_2_sram[0]:25 *C 35.420 36.765 +*N mux_tree_tapbuf_size7_2_sram[0]:26 *C 35.420 39.440 +*N mux_tree_tapbuf_size7_2_sram[0]:27 *C 35.465 39.440 +*N mux_tree_tapbuf_size7_2_sram[0]:28 *C 36.608 39.440 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_5\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +3 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_track_5\/mux_l1_in_3_:S 1e-06 +5 mux_bottom_track_5\/mux_l1_in_2_:S 1e-06 +6 mux_tree_tapbuf_size7_2_sram[0]:6 8.162628e-05 +7 mux_tree_tapbuf_size7_2_sram[0]:7 0.0001118717 +8 mux_tree_tapbuf_size7_2_sram[0]:8 0.0001429788 +9 mux_tree_tapbuf_size7_2_sram[0]:9 5.392062e-05 +10 mux_tree_tapbuf_size7_2_sram[0]:10 5.448476e-05 +11 mux_tree_tapbuf_size7_2_sram[0]:11 0.0001117039 +12 mux_tree_tapbuf_size7_2_sram[0]:12 0.0001117039 +13 mux_tree_tapbuf_size7_2_sram[0]:13 9.710011e-05 +14 mux_tree_tapbuf_size7_2_sram[0]:14 0.0001282072 +15 mux_tree_tapbuf_size7_2_sram[0]:15 0.0002468471 +16 mux_tree_tapbuf_size7_2_sram[0]:16 9.996921e-05 +17 mux_tree_tapbuf_size7_2_sram[0]:17 9.996921e-05 +18 mux_tree_tapbuf_size7_2_sram[0]:18 0.0006732359 +19 mux_tree_tapbuf_size7_2_sram[0]:19 0.0003957398 +20 mux_tree_tapbuf_size7_2_sram[0]:20 0.0003402477 +21 mux_tree_tapbuf_size7_2_sram[0]:21 0.0002886192 +22 mux_tree_tapbuf_size7_2_sram[0]:22 0.0001879728 +23 mux_tree_tapbuf_size7_2_sram[0]:23 0.000155167 +24 mux_tree_tapbuf_size7_2_sram[0]:24 0.000155167 +25 mux_tree_tapbuf_size7_2_sram[0]:25 0.0001624534 +26 mux_tree_tapbuf_size7_2_sram[0]:26 0.000385198 +27 mux_tree_tapbuf_size7_2_sram[0]:27 0.0001027117 +28 mux_tree_tapbuf_size7_2_sram[0]:28 0.0001027117 +29 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.225215e-06 +30 mux_tree_tapbuf_size7_2_sram[0]:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.199859e-05 +31 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.225215e-06 +32 mux_tree_tapbuf_size7_2_sram[0]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.858973e-08 +33 mux_tree_tapbuf_size7_2_sram[0]:26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.858973e-08 +34 mux_tree_tapbuf_size7_2_sram[0]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.792677e-06 +35 mux_tree_tapbuf_size7_2_sram[0]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.199859e-05 +36 mux_tree_tapbuf_size7_2_sram[0]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.792677e-06 +37 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.52414e-05 +38 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.52414e-05 +39 mux_tree_tapbuf_size7_2_sram[0]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.589255e-05 +40 mux_tree_tapbuf_size7_2_sram[0]:26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.100735e-05 +41 mux_tree_tapbuf_size7_2_sram[0]:26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.589255e-05 +42 mux_tree_tapbuf_size7_2_sram[0]:24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.37875e-06 +43 mux_tree_tapbuf_size7_2_sram[0]:25 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.100735e-05 +44 mux_tree_tapbuf_size7_2_sram[0]:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.37875e-06 +45 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.994576e-05 +46 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.994576e-05 +47 mux_tree_tapbuf_size7_2_sram[0]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.681081e-07 +48 mux_tree_tapbuf_size7_2_sram[0]:26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.681081e-07 +49 mux_tree_tapbuf_size7_2_sram[0]:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.471756e-06 +50 mux_tree_tapbuf_size7_2_sram[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.10088e-05 +51 mux_tree_tapbuf_size7_2_sram[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.077051e-05 +52 mux_tree_tapbuf_size7_2_sram[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.10088e-05 +53 mux_tree_tapbuf_size7_2_sram[0]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.202463e-05 +54 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.202463e-05 +55 mux_tree_tapbuf_size7_2_sram[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.207094e-06 +56 mux_tree_tapbuf_size7_2_sram[0]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.077051e-05 +57 mux_tree_tapbuf_size7_2_sram[0]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.471756e-06 +58 mux_tree_tapbuf_size7_2_sram[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.207094e-06 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_2_sram[0]:28 0.152 +1 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:19 0.0045 +2 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:6 0.0006071429 +3 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:18 0.007245536 +4 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:13 0.001602679 +5 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:8 0.0003035715 +6 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:14 0.0045 +7 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:20 0.00365625 +8 mux_tree_tapbuf_size7_2_sram[0]:22 mux_tree_tapbuf_size7_2_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size7_2_sram[0]:13 mux_tree_tapbuf_size7_2_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size7_2_sram[0]:12 mux_tree_tapbuf_size7_2_sram[0]:11 0.002044643 +11 mux_tree_tapbuf_size7_2_sram[0]:10 mux_tree_tapbuf_size7_2_sram[0]:9 0.0001548913 +12 mux_tree_tapbuf_size7_2_sram[0]:11 mux_tree_tapbuf_size7_2_sram[0]:10 0.0045 +13 mux_tree_tapbuf_size7_2_sram[0]:9 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size7_2_sram[0]:27 mux_tree_tapbuf_size7_2_sram[0]:26 0.0045 +15 mux_tree_tapbuf_size7_2_sram[0]:26 mux_tree_tapbuf_size7_2_sram[0]:25 0.002388393 +16 mux_tree_tapbuf_size7_2_sram[0]:26 mux_tree_tapbuf_size7_2_sram[0]:22 0.002995536 +17 mux_tree_tapbuf_size7_2_sram[0]:28 mux_tree_tapbuf_size7_2_sram[0]:27 0.001020089 +18 mux_tree_tapbuf_size7_2_sram[0]:7 mux_bottom_track_5\/mux_l1_in_3_:S 0.152 +19 mux_tree_tapbuf_size7_2_sram[0]:6 mux_bottom_track_5\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size7_2_sram[0]:24 mux_tree_tapbuf_size7_2_sram[0]:23 0.001479911 +21 mux_tree_tapbuf_size7_2_sram[0]:25 mux_tree_tapbuf_size7_2_sram[0]:24 0.0045 +22 mux_tree_tapbuf_size7_2_sram[0]:23 mux_bottom_track_5\/mux_l1_in_1_:S 0.152 +23 mux_tree_tapbuf_size7_2_sram[0]:17 mux_tree_tapbuf_size7_2_sram[0]:16 0.0008370537 +24 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:17 0.0045 +25 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:15 0.004209822 +26 mux_tree_tapbuf_size7_2_sram[0]:16 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +27 mux_tree_tapbuf_size7_2_sram[0]:8 mux_tree_tapbuf_size7_2_sram[0]:7 0.001287946 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002407711 //LENGTH 15.770 LUMPCC 0.0007092977 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_1_:X O *L 0 *C 92.285 45.560 +*I mux_right_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 104.595 48.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 104.558 48.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.505 48.280 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.460 48.235 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.460 45.605 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 92.460 45.560 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 92.285 45.560 + +*CAP +0 mux_right_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0006205187 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006205187 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001716483 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001716483 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.799503e-05 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.4084e-05 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size5_1_sram[0]:13 0.0003546489 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_1_sram[0]:12 0.0003546489 + +*RES +0 mux_right_track_24\/mux_l1_in_1_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.01076116 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009091291 //LENGTH 7.370 LUMPCC 9.864657e-05 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 58.595 83.300 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.865 88.740 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.903 88.740 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 58.835 88.740 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 58.880 88.695 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 58.880 83.345 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 58.880 83.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 58.595 83.300 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.199301e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.199301e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002801302 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002801302 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.066518e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.357092e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[10]:21 4.932329e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[10]:22 4.932329e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325893 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004776786 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00242619 //LENGTH 20.430 LUMPCC 0.0003615137 DR + +*CONN +*I mux_bottom_track_19\/mux_l2_in_0_:X O *L 0 *C 55.425 25.160 +*I mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 56.325 6.655 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 56.325 6.655 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 56.580 6.800 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 56.580 6.845 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 56.580 25.115 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 56.535 25.160 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 55.463 25.160 + +*CAP +0 mux_bottom_track_19\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.938493e-05 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.154678e-05 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00086437 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00086437 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001065022 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001065022 +8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001807568 +9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001807568 + +*RES +0 mux_bottom_track_19\/mux_l2_in_0_:X mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0009575893 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0163125 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.880435e-05 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008840473 //LENGTH 6.225 LUMPCC 0.0004147174 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_0_:X O *L 0 *C 24.205 33.660 +*I mux_bottom_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 26.780 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 26.742 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 26.265 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 26.220 30.985 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 26.220 33.615 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 26.175 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 24.242 33.660 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.917457e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.917457e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001647361 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001647361 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.975428e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.975428e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 bottom_left_grid_pin_41_[0]:24 8.699848e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 bottom_left_grid_pin_41_[0]:23 8.699848e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_1_sram[2]:3 3.336175e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_1_sram[2]:8 3.336175e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_1_sram[2]:4 8.699848e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size7_1_sram[2]:5 8.699848e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004263393 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006514008 //LENGTH 4.935 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_7\/mux_l2_in_0_:X O *L 0 *C 23.635 42.500 +*I mux_bottom_track_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 23.000 45.220 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 23.000 45.235 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.000 45.560 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 23.000 45.515 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 23.000 42.545 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 23.045 42.500 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 23.598 42.500 + +*CAP +0 mux_bottom_track_7\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.573803e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.858134e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001978697 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001978697 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.467097e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.467097e-05 + +*RES +0 mux_bottom_track_7\/mux_l2_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002651786 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001766304 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_7\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002931876 //LENGTH 24.265 LUMPCC 0.0007456214 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_0_:X O *L 0 *C 74.235 90.440 +*I mux_left_track_33\/mux_l3_in_0_:A1 I *L 0.00198 *C 63.480 77.860 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 63.518 77.860 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 73.555 77.860 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 73.600 77.905 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 73.600 90.395 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 73.645 90.440 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 74.198 90.440 + +*CAP +0 mux_left_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004222144 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0004222144 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0006128473 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006128473 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.706546e-05 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.706546e-05 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_3_sram[2]:13 3.35984e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_3_sram[2]:11 0.0003392123 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_3_sram[2]:12 3.35984e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_3_sram[2]:10 0.0003392123 + +*RES +0 mux_left_track_33\/mux_l2_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01115179 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.008962054 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001128623 //LENGTH 8.525 LUMPCC 0.000368441 DR + +*CONN +*I mux_bottom_track_39\/mux_l1_in_0_:X O *L 0 *C 48.125 11.900 +*I mux_bottom_track_39\/mux_l2_in_0_:A1 I *L 0.00198 *C 53.000 9.180 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 52.963 9.180 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 50.185 9.180 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 50.140 9.225 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 50.140 11.855 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 50.095 11.900 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 48.163 11.900 + +*CAP +0 mux_bottom_track_39\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_39\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001416474 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001416474 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001260186 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001260186 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000111425 +7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000111425 +8 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_6_sram[1]:12 5.17154e-05 +9 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_6_sram[1]:13 5.17154e-05 +10 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.995468e-05 +11 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.995468e-05 +12 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.255043e-05 +13 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.255043e-05 + +*RES +0 mux_bottom_track_39\/mux_l1_in_0_:X mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_39\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002479911 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725446 + +*END + +*D_NET chanx_right_out[6] 0.0009837509 //LENGTH 6.990 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_807:X O *L 0 *C 136.160 85.680 +*P chanx_right_out[6] O *L 0.7423 *C 140.450 84.320 +*N chanx_right_out[6]:2 *C 138.468 84.320 +*N chanx_right_out[6]:3 *C 138.460 84.377 +*N chanx_right_out[6]:4 *C 138.460 84.955 +*N chanx_right_out[6]:5 *C 138.460 85.000 +*N chanx_right_out[6]:6 *C 138.655 85.340 +*N chanx_right_out[6]:7 *C 136.620 85.340 +*N chanx_right_out[6]:8 *C 136.620 85.680 +*N chanx_right_out[6]:9 *C 136.198 85.680 + +*CAP +0 ropt_mt_inst_807:X 1e-06 +1 chanx_right_out[6] 0.0001512773 +2 chanx_right_out[6]:2 0.0001512773 +3 chanx_right_out[6]:3 6.65031e-05 +4 chanx_right_out[6]:4 6.65031e-05 +5 chanx_right_out[6]:5 6.594793e-05 +6 chanx_right_out[6]:6 0.0001887628 +7 chanx_right_out[6]:7 0.0001833987 +8 chanx_right_out[6]:8 6.642647e-05 +9 chanx_right_out[6]:9 4.265418e-05 + +*RES +0 ropt_mt_inst_807:X chanx_right_out[6]:9 0.152 +1 chanx_right_out[6]:9 chanx_right_out[6]:8 0.0003772321 +2 chanx_right_out[6]:5 chanx_right_out[6]:4 0.0045 +3 chanx_right_out[6]:4 chanx_right_out[6]:3 0.000515625 +4 chanx_right_out[6]:3 chanx_right_out[6]:2 0.00341 +5 chanx_right_out[6]:2 chanx_right_out[6] 0.0003105917 +6 chanx_right_out[6]:8 chanx_right_out[6]:7 0.0003035715 +7 chanx_right_out[6]:7 chanx_right_out[6]:6 0.001816964 +8 chanx_right_out[6]:6 chanx_right_out[6]:5 0.0003035714 + +*END + +*D_NET BUF_net_76 0.002680542 //LENGTH 23.805 LUMPCC 0.0004700847 DR + +*CONN +*I BUFT_RR_76:X O *L 0 *C 15.640 51.000 +*I BUFT_P_138:A I *L 0.001766 *C 8.740 61.200 +*N BUF_net_76:2 *C 8.740 61.200 +*N BUF_net_76:3 *C 8.740 61.245 +*N BUF_net_76:4 *C 8.740 63.875 +*N BUF_net_76:5 *C 8.785 63.920 +*N BUF_net_76:6 *C 13.755 63.920 +*N BUF_net_76:7 *C 13.800 63.875 +*N BUF_net_76:8 *C 13.800 51.045 +*N BUF_net_76:9 *C 13.845 51.000 +*N BUF_net_76:10 *C 15.603 51.000 + +*CAP +0 BUFT_RR_76:X 1e-06 +1 BUFT_P_138:A 1e-06 +2 BUF_net_76:2 3.336727e-05 +3 BUF_net_76:3 0.0001566515 +4 BUF_net_76:4 0.0001566515 +5 BUF_net_76:5 0.0002901178 +6 BUF_net_76:6 0.0002901178 +7 BUF_net_76:7 0.0005019953 +8 BUF_net_76:8 0.0005019953 +9 BUF_net_76:9 0.0001387803 +10 BUF_net_76:10 0.0001387803 +11 BUF_net_76:8 optlc_net_168:26 5.239118e-05 +12 BUF_net_76:8 optlc_net_168:27 0.0001106707 +13 BUF_net_76:7 optlc_net_168:23 0.0001106707 +14 BUF_net_76:7 optlc_net_168:27 5.239118e-05 +15 BUF_net_76:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.198046e-05 +16 BUF_net_76:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.198046e-05 + +*RES +0 BUFT_RR_76:X BUF_net_76:10 0.152 +1 BUF_net_76:10 BUF_net_76:9 0.001569197 +2 BUF_net_76:9 BUF_net_76:8 0.0045 +3 BUF_net_76:8 BUF_net_76:7 0.01145536 +4 BUF_net_76:6 BUF_net_76:5 0.0044375 +5 BUF_net_76:7 BUF_net_76:6 0.0045 +6 BUF_net_76:5 BUF_net_76:4 0.0045 +7 BUF_net_76:4 BUF_net_76:3 0.002348214 +8 BUF_net_76:2 BUFT_P_138:A 0.152 +9 BUF_net_76:3 BUF_net_76:2 0.0045 + +*END + +*D_NET chanx_right_in[6] 0.02037813 //LENGTH 146.910 LUMPCC 0.005945829 DR + +*CONN +*P chanx_right_in[6] I *L 0.29796 *C 140.450 31.280 +*I mux_bottom_track_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 29.345 45.220 +*I FTB_4__3:A I *L 0.001776 *C 13.340 44.880 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 63.020 45.220 +*N chanx_right_in[6]:4 *C 63.020 45.220 +*N chanx_right_in[6]:5 *C 13.340 44.880 +*N chanx_right_in[6]:6 *C 13.340 44.835 +*N chanx_right_in[6]:7 *C 13.340 44.245 +*N chanx_right_in[6]:8 *C 13.340 44.200 +*N chanx_right_in[6]:9 *C 23.920 44.200 +*N chanx_right_in[6]:10 *C 23.920 45.220 +*N chanx_right_in[6]:11 *C 29.345 45.220 +*N chanx_right_in[6]:12 *C 29.900 45.220 +*N chanx_right_in[6]:13 *C 29.900 45.560 +*N chanx_right_in[6]:14 *C 63.020 45.560 +*N chanx_right_in[6]:15 *C 63.020 45.560 +*N chanx_right_in[6]:16 *C 63.028 45.560 +*N chanx_right_in[6]:17 *C 112.855 45.560 +*N chanx_right_in[6]:18 *C 132.472 45.560 +*N chanx_right_in[6]:19 *C 132.480 45.503 +*N chanx_right_in[6]:20 *C 132.480 31.338 +*N chanx_right_in[6]:21 *C 132.488 31.280 + +*CAP +0 chanx_right_in[6] 0.0004404909 +1 mux_bottom_track_7\/mux_l1_in_0_:A1 1e-06 +2 FTB_4__3:A 1e-06 +3 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[6]:4 5.612815e-05 +5 chanx_right_in[6]:5 3.464475e-05 +6 chanx_right_in[6]:6 4.88442e-05 +7 chanx_right_in[6]:7 4.88442e-05 +8 chanx_right_in[6]:8 0.0007405547 +9 chanx_right_in[6]:9 0.00076431 +10 chanx_right_in[6]:10 0.0004300753 +11 chanx_right_in[6]:11 0.0004254952 +12 chanx_right_in[6]:12 6.194285e-05 +13 chanx_right_in[6]:13 0.001992877 +14 chanx_right_in[6]:14 0.001995429 +15 chanx_right_in[6]:15 3.999054e-05 +16 chanx_right_in[6]:16 0.00230351 +17 chanx_right_in[6]:17 0.002753977 +18 chanx_right_in[6]:18 0.0004504681 +19 chanx_right_in[6]:19 0.0007006123 +20 chanx_right_in[6]:20 0.0007006123 +21 chanx_right_in[6]:21 0.0004404909 +22 chanx_right_in[6]:16 chanx_right_in[14]:20 0.0004578673 +23 chanx_right_in[6]:16 chanx_right_in[14]:22 0.0003705262 +24 chanx_right_in[6]:18 chanx_right_in[14] 0.0003237459 +25 chanx_right_in[6]:8 chanx_right_in[14]:8 5.208155e-06 +26 chanx_right_in[6]:7 chanx_right_in[14]:6 4.337078e-06 +27 chanx_right_in[6]:6 chanx_right_in[14]:7 4.337078e-06 +28 chanx_right_in[6]:9 chanx_right_in[14]:9 5.208155e-06 +29 chanx_right_in[6]:17 chanx_right_in[14] 0.0003705262 +30 chanx_right_in[6]:17 chanx_right_in[14]:21 0.0004578673 +31 chanx_right_in[6]:17 chanx_right_in[14]:22 0.0003237459 +32 chanx_right_in[6]:16 chanx_left_in[8]:15 0.0006362453 +33 chanx_right_in[6]:16 chanx_left_in[8]:16 6.455679e-05 +34 chanx_right_in[6]:19 chanx_left_in[8]:7 6.683024e-07 +35 chanx_right_in[6]:18 chanx_left_in[8]:8 0.0004871922 +36 chanx_right_in[6]:20 chanx_left_in[8]:6 6.683024e-07 +37 chanx_right_in[6]:17 chanx_left_in[8]:15 0.000551749 +38 chanx_right_in[6]:17 chanx_left_in[8]:8 0.0006362453 +39 chanx_right_in[6]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003501787 +40 chanx_right_in[6]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.096391e-06 +41 chanx_right_in[6]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.591917e-06 +42 chanx_right_in[6]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.440568e-06 +43 chanx_right_in[6]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.591917e-06 +44 chanx_right_in[6]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003477381 +45 chanx_right_in[6]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.096391e-06 +46 chanx_right_in[6]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001546415 +47 chanx_right_in[6]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001546415 +48 chanx_right_in[6]:8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001090587 +49 chanx_right_in[6]:9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001090587 + +*RES +0 chanx_right_in[6] chanx_right_in[6]:21 0.001247458 +1 chanx_right_in[6]:14 chanx_right_in[6]:13 0.02957143 +2 chanx_right_in[6]:14 chanx_right_in[6]:4 0.0001465517 +3 chanx_right_in[6]:15 chanx_right_in[6]:14 0.0045 +4 chanx_right_in[6]:16 chanx_right_in[6]:15 0.00341 +5 chanx_right_in[6]:19 chanx_right_in[6]:18 0.00341 +6 chanx_right_in[6]:18 chanx_right_in[6]:17 0.003073408 +7 chanx_right_in[6]:20 chanx_right_in[6]:19 0.01264732 +8 chanx_right_in[6]:21 chanx_right_in[6]:20 0.00341 +9 chanx_right_in[6]:8 chanx_right_in[6]:7 0.0045 +10 chanx_right_in[6]:7 chanx_right_in[6]:6 0.0005267857 +11 chanx_right_in[6]:5 FTB_4__3:A 0.152 +12 chanx_right_in[6]:6 chanx_right_in[6]:5 0.0045 +13 chanx_right_in[6]:11 mux_bottom_track_7\/mux_l1_in_0_:A1 0.152 +14 chanx_right_in[6]:11 chanx_right_in[6]:10 0.00484375 +15 chanx_right_in[6]:4 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +16 chanx_right_in[6]:9 chanx_right_in[6]:8 0.009446429 +17 chanx_right_in[6]:10 chanx_right_in[6]:9 0.0009107143 +18 chanx_right_in[6]:12 chanx_right_in[6]:11 0.0004955357 +19 chanx_right_in[6]:13 chanx_right_in[6]:12 0.0003035715 +20 chanx_right_in[6]:17 chanx_right_in[6]:16 0.007806307 + +*END + +*D_NET chanx_left_in[14] 0.02675733 //LENGTH 194.565 LUMPCC 0.008705527 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 59.840 +*I mux_bottom_track_19\/mux_l1_in_1_:A1 I *L 0.00198 *C 58.325 28.900 +*I ropt_mt_inst_806:A I *L 0.001767 *C 134.780 69.360 +*I mux_right_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 100.455 58.820 +*N chanx_left_in[14]:4 *C 100.455 58.820 +*N chanx_left_in[14]:5 *C 100.280 58.820 +*N chanx_left_in[14]:6 *C 134.780 69.360 +*N chanx_left_in[14]:7 *C 134.780 69.020 +*N chanx_left_in[14]:8 *C 122.865 69.020 +*N chanx_left_in[14]:9 *C 122.820 68.975 +*N chanx_left_in[14]:10 *C 122.820 59.218 +*N chanx_left_in[14]:11 *C 122.812 59.160 +*N chanx_left_in[14]:12 *C 100.293 59.160 +*N chanx_left_in[14]:13 *C 100.288 58.825 +*N chanx_left_in[14]:14 *C 100.280 58.820 +*N chanx_left_in[14]:15 *C 99.820 58.820 +*N chanx_left_in[14]:16 *C 99.820 55.138 +*N chanx_left_in[14]:17 *C 99.812 55.080 +*N chanx_left_in[14]:18 *C 58.363 28.900 +*N chanx_left_in[14]:19 *C 58.835 28.900 +*N chanx_left_in[14]:20 *C 58.880 28.900 +*N chanx_left_in[14]:21 *C 58.880 28.560 +*N chanx_left_in[14]:22 *C 58.888 28.560 +*N chanx_left_in[14]:23 *C 66.220 28.560 +*N chanx_left_in[14]:24 *C 66.240 28.568 +*N chanx_left_in[14]:25 *C 66.240 55.073 +*N chanx_left_in[14]:26 *C 66.240 55.080 +*N chanx_left_in[14]:27 *C 66.240 55.760 +*N chanx_left_in[14]:28 *C 30.380 55.760 +*N chanx_left_in[14]:29 *C 30.360 55.768 +*N chanx_left_in[14]:30 *C 30.360 59.833 +*N chanx_left_in[14]:31 *C 30.340 59.840 +*N chanx_left_in[14]:32 *C 17.480 59.840 +*N chanx_left_in[14]:33 *C 17.480 60.520 +*N chanx_left_in[14]:34 *C 5.520 60.520 +*N chanx_left_in[14]:35 *C 5.520 59.840 + +*CAP +0 chanx_left_in[14] 0.0003282604 +1 mux_bottom_track_19\/mux_l1_in_1_:A1 1e-06 +2 ropt_mt_inst_806:A 1e-06 +3 mux_right_track_4\/mux_l1_in_2_:A0 1e-06 +4 chanx_left_in[14]:4 4.502694e-05 +5 chanx_left_in[14]:5 4.601706e-05 +6 chanx_left_in[14]:6 6.382185e-05 +7 chanx_left_in[14]:7 0.0006697598 +8 chanx_left_in[14]:8 0.0006388158 +9 chanx_left_in[14]:9 0.0004512211 +10 chanx_left_in[14]:10 0.0004512211 +11 chanx_left_in[14]:11 0.0007567696 +12 chanx_left_in[14]:12 0.0007845704 +13 chanx_left_in[14]:13 2.780082e-05 +14 chanx_left_in[14]:14 7.287176e-05 +15 chanx_left_in[14]:15 0.0002600899 +16 chanx_left_in[14]:16 0.0002246313 +17 chanx_left_in[14]:17 0.001462062 +18 chanx_left_in[14]:18 6.374744e-05 +19 chanx_left_in[14]:19 6.374744e-05 +20 chanx_left_in[14]:20 6.355638e-05 +21 chanx_left_in[14]:21 6.803102e-05 +22 chanx_left_in[14]:22 0.000522271 +23 chanx_left_in[14]:23 0.000522271 +24 chanx_left_in[14]:24 0.001045597 +25 chanx_left_in[14]:25 0.001045597 +26 chanx_left_in[14]:26 0.001528959 +27 chanx_left_in[14]:27 0.001778528 +28 chanx_left_in[14]:28 0.001711631 +29 chanx_left_in[14]:29 0.0002594848 +30 chanx_left_in[14]:30 0.0002594848 +31 chanx_left_in[14]:31 0.000474111 +32 chanx_left_in[14]:32 0.0005274295 +33 chanx_left_in[14]:33 0.0007436895 +34 chanx_left_in[14]:34 0.000724919 +35 chanx_left_in[14]:35 0.0003628084 +36 chanx_left_in[14]:28 chanx_right_in[13]:22 0.0004392636 +37 chanx_left_in[14]:35 chanx_right_in[13]:13 2.196028e-05 +38 chanx_left_in[14]:34 chanx_right_in[13]:12 2.196028e-05 +39 chanx_left_in[14]:27 chanx_right_in[13]:23 0.0004392636 +40 chanx_left_in[14]:11 chanx_right_in[17]:30 0.0003614604 +41 chanx_left_in[14]:31 chanx_right_in[17]:12 1.476112e-05 +42 chanx_left_in[14]:31 chanx_right_in[17]:14 5.52541e-06 +43 chanx_left_in[14]:34 chanx_right_in[17]:11 3.253683e-05 +44 chanx_left_in[14]:33 chanx_right_in[17]:12 3.253683e-05 +45 chanx_left_in[14]:32 chanx_right_in[17]:11 1.476112e-05 +46 chanx_left_in[14]:32 chanx_right_in[17]:13 5.52541e-06 +47 chanx_left_in[14]:12 chanx_right_in[17]:29 0.0003614604 +48 chanx_left_in[14]:13 chanx_left_in[5]:29 1.085673e-05 +49 chanx_left_in[14]:16 chanx_left_in[5]:28 2.510613e-06 +50 chanx_left_in[14]:5 chanx_left_in[5]:31 1.362362e-05 +51 chanx_left_in[14]:4 chanx_left_in[5]:30 1.362362e-05 +52 chanx_left_in[14]:31 chanx_left_in[5]:35 0.0003566776 +53 chanx_left_in[14]:15 chanx_left_in[5]:29 2.510613e-06 +54 chanx_left_in[14]:32 chanx_left_in[5]:36 0.0003566776 +55 chanx_left_in[14]:12 chanx_left_in[5]:24 1.085673e-05 +56 chanx_left_in[14]:26 chanx_left_in[16]:32 0.0001358419 +57 chanx_left_in[14]:26 chanx_left_in[16]:31 0.0005559903 +58 chanx_left_in[14]:9 chanx_left_in[16]:15 0.0001308385 +59 chanx_left_in[14]:10 chanx_left_in[16]:16 0.0001308385 +60 chanx_left_in[14]:11 chanx_left_in[16]:22 0.0001730462 +61 chanx_left_in[14]:17 chanx_left_in[16]:31 0.0001358419 +62 chanx_left_in[14]:17 chanx_left_in[16]:22 0.0005559903 +63 chanx_left_in[14]:12 chanx_left_in[16]:31 0.0001730462 +64 chanx_left_in[14] chanx_left_in[17]:32 2.107503e-06 +65 chanx_left_in[14]:26 chanx_left_in[17]:31 8.377438e-06 +66 chanx_left_in[14]:17 chanx_left_in[17]:30 8.377438e-06 +67 chanx_left_in[14]:28 chanx_left_in[17]:32 0.0002611747 +68 chanx_left_in[14]:28 chanx_left_in[17]:31 0.0001807427 +69 chanx_left_in[14]:31 chanx_left_in[17]:31 0.0001383931 +70 chanx_left_in[14]:35 chanx_left_in[17]:31 2.107503e-06 +71 chanx_left_in[14]:34 chanx_left_in[17]:32 8.731282e-05 +72 chanx_left_in[14]:33 chanx_left_in[17]:31 8.731282e-05 +73 chanx_left_in[14]:32 chanx_left_in[17]:32 0.0001383931 +74 chanx_left_in[14]:27 chanx_left_in[17]:30 0.0001807427 +75 chanx_left_in[14]:27 chanx_left_in[17]:31 0.0002611747 +76 chanx_left_in[14]:25 chany_bottom_in[4]:14 5.880085e-05 +77 chanx_left_in[14]:25 chany_bottom_in[4]:15 0.001109367 +78 chanx_left_in[14]:24 chany_bottom_in[4]:16 0.001109367 +79 chanx_left_in[14]:24 chany_bottom_in[4]:15 5.880085e-05 +80 chanx_left_in[14]:26 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002515939 +81 chanx_left_in[14]:17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002515939 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:35 0.0006720999 +1 chanx_left_in[14]:26 chanx_left_in[14]:25 0.00341 +2 chanx_left_in[14]:26 chanx_left_in[14]:17 0.005259691 +3 chanx_left_in[14]:25 chanx_left_in[14]:24 0.00415245 +4 chanx_left_in[14]:23 chanx_left_in[14]:22 0.001148758 +5 chanx_left_in[14]:24 chanx_left_in[14]:23 0.00341 +6 chanx_left_in[14]:21 chanx_left_in[14]:20 0.0001634615 +7 chanx_left_in[14]:22 chanx_left_in[14]:21 0.00341 +8 chanx_left_in[14]:19 chanx_left_in[14]:18 0.000421875 +9 chanx_left_in[14]:20 chanx_left_in[14]:19 0.0045 +10 chanx_left_in[14]:18 mux_bottom_track_19\/mux_l1_in_1_:A1 0.152 +11 chanx_left_in[14]:6 ropt_mt_inst_806:A 0.152 +12 chanx_left_in[14]:8 chanx_left_in[14]:7 0.01063839 +13 chanx_left_in[14]:9 chanx_left_in[14]:8 0.0045 +14 chanx_left_in[14]:10 chanx_left_in[14]:9 0.008712054 +15 chanx_left_in[14]:11 chanx_left_in[14]:10 0.00341 +16 chanx_left_in[14]:14 chanx_left_in[14]:13 0.00341 +17 chanx_left_in[14]:14 chanx_left_in[14]:5 0.0045 +18 chanx_left_in[14]:13 chanx_left_in[14]:12 4.998412e-05 +19 chanx_left_in[14]:16 chanx_left_in[14]:15 0.003287947 +20 chanx_left_in[14]:17 chanx_left_in[14]:16 0.00341 +21 chanx_left_in[14]:5 chanx_left_in[14]:4 9.51087e-05 +22 chanx_left_in[14]:4 mux_right_track_4\/mux_l1_in_2_:A0 0.152 +23 chanx_left_in[14]:28 chanx_left_in[14]:27 0.005618067 +24 chanx_left_in[14]:29 chanx_left_in[14]:28 0.00341 +25 chanx_left_in[14]:31 chanx_left_in[14]:30 0.00341 +26 chanx_left_in[14]:30 chanx_left_in[14]:29 0.00063685 +27 chanx_left_in[14]:7 chanx_left_in[14]:6 0.0003035715 +28 chanx_left_in[14]:15 chanx_left_in[14]:14 0.0004107143 +29 chanx_left_in[14]:35 chanx_left_in[14]:34 0.0001065333 +30 chanx_left_in[14]:34 chanx_left_in[14]:33 0.001873733 +31 chanx_left_in[14]:33 chanx_left_in[14]:32 0.0001065333 +32 chanx_left_in[14]:32 chanx_left_in[14]:31 0.002014733 +33 chanx_left_in[14]:27 chanx_left_in[14]:26 0.0001065333 +34 chanx_left_in[14]:12 chanx_left_in[14]:11 0.003528133 + +*END + +*D_NET chanx_left_in[17] 0.02604094 //LENGTH 195.240 LUMPCC 0.009587243 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 53.040 +*I mux_right_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 88.420 52.700 +*I mux_bottom_track_23\/mux_l1_in_1_:A1 I *L 0.00198 *C 87.860 41.820 +*I ropt_mt_inst_802:A I *L 0.001767 *C 134.780 88.400 +*N chanx_left_in[17]:4 *C 134.743 88.400 +*N chanx_left_in[17]:5 *C 134.365 88.400 +*N chanx_left_in[17]:6 *C 134.320 88.355 +*N chanx_left_in[17]:7 *C 134.320 79.945 +*N chanx_left_in[17]:8 *C 134.275 79.900 +*N chanx_left_in[17]:9 *C 126.040 79.900 +*N chanx_left_in[17]:10 *C 126.120 79.560 +*N chanx_left_in[17]:11 *C 126.050 79.605 +*N chanx_left_in[17]:12 *C 126.040 80.195 +*N chanx_left_in[17]:13 *C 125.995 80.240 +*N chanx_left_in[17]:14 *C 121.945 80.240 +*N chanx_left_in[17]:15 *C 121.900 80.195 +*N chanx_left_in[17]:16 *C 121.900 74.178 +*N chanx_left_in[17]:17 *C 121.893 74.120 +*N chanx_left_in[17]:18 *C 89.248 74.120 +*N chanx_left_in[17]:19 *C 89.240 74.062 +*N chanx_left_in[17]:20 *C 87.898 41.820 +*N chanx_left_in[17]:21 *C 90.115 41.820 +*N chanx_left_in[17]:22 *C 90.160 41.865 +*N chanx_left_in[17]:23 *C 90.160 52.315 +*N chanx_left_in[17]:24 *C 90.115 52.360 +*N chanx_left_in[17]:25 *C 89.240 52.360 +*N chanx_left_in[17]:26 *C 88.458 52.700 +*N chanx_left_in[17]:27 *C 89.240 52.670 +*N chanx_left_in[17]:28 *C 89.240 52.745 +*N chanx_left_in[17]:29 *C 89.240 57.800 +*N chanx_left_in[17]:30 *C 89.233 57.800 +*N chanx_left_in[17]:31 *C 51.650 57.800 +*N chanx_left_in[17]:32 *C 1.860 57.800 +*N chanx_left_in[17]:33 *C 1.840 57.793 +*N chanx_left_in[17]:34 *C 1.840 53.047 +*N chanx_left_in[17]:35 *C 1.820 53.040 + +*CAP +0 chanx_left_in[17] 5.919472e-05 +1 mux_right_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_23\/mux_l1_in_1_:A1 1e-06 +3 ropt_mt_inst_802:A 1e-06 +4 chanx_left_in[17]:4 4.010891e-05 +5 chanx_left_in[17]:5 4.010891e-05 +6 chanx_left_in[17]:6 0.0003753183 +7 chanx_left_in[17]:7 0.0003753183 +8 chanx_left_in[17]:8 0.0004579694 +9 chanx_left_in[17]:9 0.000483897 +10 chanx_left_in[17]:10 5.579337e-05 +11 chanx_left_in[17]:11 4.800313e-05 +12 chanx_left_in[17]:12 4.800313e-05 +13 chanx_left_in[17]:13 0.0002393607 +14 chanx_left_in[17]:14 0.0002393607 +15 chanx_left_in[17]:15 0.0003269988 +16 chanx_left_in[17]:16 0.0003269988 +17 chanx_left_in[17]:17 0.000986123 +18 chanx_left_in[17]:18 0.000986123 +19 chanx_left_in[17]:19 0.0008278425 +20 chanx_left_in[17]:20 0.0001586348 +21 chanx_left_in[17]:21 0.0001586348 +22 chanx_left_in[17]:22 0.0004561912 +23 chanx_left_in[17]:23 0.0004561912 +24 chanx_left_in[17]:24 7.416439e-05 +25 chanx_left_in[17]:25 0.0001017337 +26 chanx_left_in[17]:26 6.725155e-05 +27 chanx_left_in[17]:27 9.482089e-05 +28 chanx_left_in[17]:28 0.0002837946 +29 chanx_left_in[17]:29 0.001152927 +30 chanx_left_in[17]:30 0.001514836 +31 chanx_left_in[17]:31 0.003459112 +32 chanx_left_in[17]:32 0.001944276 +33 chanx_left_in[17]:33 0.0002762073 +34 chanx_left_in[17]:34 0.0002762073 +35 chanx_left_in[17]:35 5.919472e-05 +36 chanx_left_in[17]:18 chanx_right_in[8]:28 0.0002308935 +37 chanx_left_in[17]:18 chanx_right_in[8]:29 6.090011e-05 +38 chanx_left_in[17]:17 chanx_right_in[8] 6.090011e-05 +39 chanx_left_in[17]:17 chanx_right_in[8]:29 0.0002308935 +40 chanx_left_in[17]:18 chanx_right_in[12]:28 0.000241136 +41 chanx_left_in[17]:18 chanx_right_in[12]:29 0.0005344731 +42 chanx_left_in[17]:17 chanx_right_in[12]:29 0.000241136 +43 chanx_left_in[17]:17 chanx_right_in[12]:30 0.0005344731 +44 chanx_left_in[17]:7 chanx_left_in[5]:9 1.656074e-06 +45 chanx_left_in[17]:6 chanx_left_in[5]:8 1.656074e-06 +46 chanx_left_in[17]:30 chanx_left_in[5]:34 0.0001149667 +47 chanx_left_in[17]:30 chanx_left_in[5]:35 0.0001090014 +48 chanx_left_in[17]:32 chanx_left_in[5]:36 0.0001757803 +49 chanx_left_in[17]:31 chanx_left_in[5]:35 0.000290747 +50 chanx_left_in[17]:31 chanx_left_in[5]:36 0.0001090014 +51 chanx_left_in[17]:19 chanx_left_in[9]:18 3.474721e-05 +52 chanx_left_in[17]:28 chanx_left_in[9]:17 1.738998e-05 +53 chanx_left_in[17]:29 chanx_left_in[9]:17 3.474721e-05 +54 chanx_left_in[17]:29 chanx_left_in[9]:18 1.738998e-05 +55 chanx_left_in[17]:23 chanx_left_in[9]:17 0.0001658701 +56 chanx_left_in[17]:23 chanx_left_in[9]:18 4.037204e-05 +57 chanx_left_in[17]:22 chanx_left_in[9]:6 0.0001658701 +58 chanx_left_in[17]:22 chanx_left_in[9]:17 4.037204e-05 +59 chanx_left_in[17]:30 chanx_left_in[14]:17 8.377438e-06 +60 chanx_left_in[17]:30 chanx_left_in[14]:27 0.0001807427 +61 chanx_left_in[17]:32 chanx_left_in[14] 2.107503e-06 +62 chanx_left_in[17]:32 chanx_left_in[14]:28 0.0002611747 +63 chanx_left_in[17]:32 chanx_left_in[14]:32 0.0001383931 +64 chanx_left_in[17]:32 chanx_left_in[14]:34 8.731282e-05 +65 chanx_left_in[17]:31 chanx_left_in[14]:26 8.377438e-06 +66 chanx_left_in[17]:31 chanx_left_in[14]:27 0.0002611747 +67 chanx_left_in[17]:31 chanx_left_in[14]:28 0.0001807427 +68 chanx_left_in[17]:31 chanx_left_in[14]:31 0.0001383931 +69 chanx_left_in[17]:31 chanx_left_in[14]:33 8.731282e-05 +70 chanx_left_in[17]:31 chanx_left_in[14]:35 2.107503e-06 +71 chanx_left_in[17]:19 prog_clk[0]:255 3.718769e-06 +72 chanx_left_in[17]:29 prog_clk[0]:256 3.718769e-06 +73 chanx_left_in[17]:30 prog_clk[0]:401 2.986068e-07 +74 chanx_left_in[17]:30 prog_clk[0]:263 7.878301e-06 +75 chanx_left_in[17]:32 prog_clk[0]:354 0.0003003805 +76 chanx_left_in[17]:32 prog_clk[0]:471 6.256219e-06 +77 chanx_left_in[17]:31 prog_clk[0]:262 7.878301e-06 +78 chanx_left_in[17]:31 prog_clk[0]:355 0.0003003805 +79 chanx_left_in[17]:31 prog_clk[0]:406 2.986068e-07 +80 chanx_left_in[17]:31 prog_clk[0]:472 6.256219e-06 +81 chanx_left_in[17]:30 chany_bottom_in[3]:14 0.0009687199 +82 chanx_left_in[17]:31 chany_bottom_in[3]:13 0.0009687199 +83 chanx_left_in[17]:32 chanx_left_in[7]:8 0.0002549632 +84 chanx_left_in[17]:31 chanx_left_in[7]:7 0.0002549632 +85 chanx_left_in[17]:32 chanx_left_out[4] 0.0002983552 +86 chanx_left_in[17]:31 chanx_left_out[4]:2 0.0002983552 +87 chanx_left_in[17]:30 mux_tree_tapbuf_size6_4_sram[1]:15 0.0004697784 +88 chanx_left_in[17]:31 mux_tree_tapbuf_size6_4_sram[1]:14 0.0004697784 +89 chanx_left_in[17]:7 ropt_net_183:3 7.797738e-05 +90 chanx_left_in[17]:6 ropt_net_183:4 7.797738e-05 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:35 9.243332e-05 +1 chanx_left_in[17]:19 chanx_left_in[17]:18 0.00341 +2 chanx_left_in[17]:18 chanx_left_in[17]:17 0.005114383 +3 chanx_left_in[17]:16 chanx_left_in[17]:15 0.005372768 +4 chanx_left_in[17]:17 chanx_left_in[17]:16 0.00341 +5 chanx_left_in[17]:14 chanx_left_in[17]:13 0.003616072 +6 chanx_left_in[17]:15 chanx_left_in[17]:14 0.0045 +7 chanx_left_in[17]:13 chanx_left_in[17]:12 0.0045 +8 chanx_left_in[17]:12 chanx_left_in[17]:11 0.0005267857 +9 chanx_left_in[17]:10 chanx_left_in[17]:9 0.0003035715 +10 chanx_left_in[17]:11 chanx_left_in[17]:10 0.0045 +11 chanx_left_in[17]:8 chanx_left_in[17]:7 0.0045 +12 chanx_left_in[17]:7 chanx_left_in[17]:6 0.007508929 +13 chanx_left_in[17]:5 chanx_left_in[17]:4 0.0003370536 +14 chanx_left_in[17]:6 chanx_left_in[17]:5 0.0045 +15 chanx_left_in[17]:4 ropt_mt_inst_802:A 0.152 +16 chanx_left_in[17]:27 chanx_left_in[17]:26 0.0006986608 +17 chanx_left_in[17]:27 chanx_left_in[17]:25 0.0002767858 +18 chanx_left_in[17]:28 chanx_left_in[17]:27 0.0045 +19 chanx_left_in[17]:26 mux_right_track_16\/mux_l2_in_1_:A1 0.152 +20 chanx_left_in[17]:29 chanx_left_in[17]:28 0.004513393 +21 chanx_left_in[17]:29 chanx_left_in[17]:19 0.01452009 +22 chanx_left_in[17]:30 chanx_left_in[17]:29 0.00341 +23 chanx_left_in[17]:32 chanx_left_in[17]:31 0.007800433 +24 chanx_left_in[17]:33 chanx_left_in[17]:32 0.00341 +25 chanx_left_in[17]:35 chanx_left_in[17]:34 0.00341 +26 chanx_left_in[17]:34 chanx_left_in[17]:33 0.0007433833 +27 chanx_left_in[17]:24 chanx_left_in[17]:23 0.0045 +28 chanx_left_in[17]:23 chanx_left_in[17]:22 0.009330357 +29 chanx_left_in[17]:21 chanx_left_in[17]:20 0.001979911 +30 chanx_left_in[17]:22 chanx_left_in[17]:21 0.0045 +31 chanx_left_in[17]:20 mux_bottom_track_23\/mux_l1_in_1_:A1 0.152 +32 chanx_left_in[17]:25 chanx_left_in[17]:24 0.0007812501 +33 chanx_left_in[17]:9 chanx_left_in[17]:8 0.007352679 +34 chanx_left_in[17]:31 chanx_left_in[17]:30 0.005887925 + +*END + +*D_NET chanx_right_in[7] 0.009509584 //LENGTH 77.685 LUMPCC 0.001936719 DR + +*CONN +*P chanx_right_in[7] I *L 0.29796 *C 140.450 50.320 +*I mux_bottom_track_31\/mux_l1_in_0_:A1 I *L 0.00198 *C 91.080 23.460 +*N chanx_right_in[7]:2 *C 91.080 23.460 +*N chanx_right_in[7]:3 *C 91.080 23.460 +*N chanx_right_in[7]:4 *C 91.080 23.800 +*N chanx_right_in[7]:5 *C 91.088 23.800 +*N chanx_right_in[7]:6 *C 103.020 23.800 +*N chanx_right_in[7]:7 *C 103.040 23.808 +*N chanx_right_in[7]:8 *C 103.040 49.633 +*N chanx_right_in[7]:9 *C 103.060 49.640 +*N chanx_right_in[7]:10 *C 116.840 49.640 +*N chanx_right_in[7]:11 *C 116.840 50.320 + +*CAP +0 chanx_right_in[7] 0.001099466 +1 mux_bottom_track_31\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[7]:2 3.170453e-05 +3 chanx_right_in[7]:3 5.247404e-05 +4 chanx_right_in[7]:4 5.607583e-05 +5 chanx_right_in[7]:5 0.0006810406 +6 chanx_right_in[7]:6 0.0006810406 +7 chanx_right_in[7]:7 0.001460639 +8 chanx_right_in[7]:8 0.001460639 +9 chanx_right_in[7]:9 0.0004211902 +10 chanx_right_in[7]:10 0.0004746595 +11 chanx_right_in[7]:11 0.001152935 +12 chanx_right_in[7] chanx_left_in[8]:8 0.0001419722 +13 chanx_right_in[7]:9 chanx_left_in[8]:15 0.0001299463 +14 chanx_right_in[7]:10 chanx_left_in[8]:8 0.0001299463 +15 chanx_right_in[7]:11 chanx_left_in[8]:15 0.0001419722 +16 chanx_right_in[7] chanx_left_in[9]:11 5.077192e-06 +17 chanx_right_in[7] chanx_left_in[9]:15 9.543601e-05 +18 chanx_right_in[7]:9 chanx_left_in[9]:16 0.0003261836 +19 chanx_right_in[7]:10 chanx_left_in[9]:15 0.0003261836 +20 chanx_right_in[7]:11 chanx_left_in[9]:12 5.077192e-06 +21 chanx_right_in[7]:11 chanx_left_in[9]:16 9.543601e-05 +22 chanx_right_in[7]:5 mux_tree_tapbuf_size4_2_sram[2]:8 0.0002697443 +23 chanx_right_in[7]:6 mux_tree_tapbuf_size4_2_sram[2]:9 0.0002697443 + +*RES +0 chanx_right_in[7] chanx_right_in[7]:11 0.0036989 +1 chanx_right_in[7]:2 mux_bottom_track_31\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[7]:3 chanx_right_in[7]:2 0.0045 +3 chanx_right_in[7]:4 chanx_right_in[7]:3 0.0001634615 +4 chanx_right_in[7]:5 chanx_right_in[7]:4 0.00341 +5 chanx_right_in[7]:6 chanx_right_in[7]:5 0.001869425 +6 chanx_right_in[7]:7 chanx_right_in[7]:6 0.00341 +7 chanx_right_in[7]:9 chanx_right_in[7]:8 0.00341 +8 chanx_right_in[7]:8 chanx_right_in[7]:7 0.004045917 +9 chanx_right_in[7]:10 chanx_right_in[7]:9 0.002158866 +10 chanx_right_in[7]:11 chanx_right_in[7]:10 0.0001065333 + +*END + +*D_NET right_top_grid_pin_1_[0] 0.0108262 //LENGTH 106.005 LUMPCC 0.0003630917 DR + +*CONN +*P right_top_grid_pin_1_[0] I *L 0.29796 *C 139.380 102.035 +*I mux_right_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 87.040 85.340 +*I mux_right_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 92.100 56.100 +*I mux_right_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 96.700 56.100 +*N right_top_grid_pin_1_[0]:4 *C 96.663 56.100 +*N right_top_grid_pin_1_[0]:5 *C 92.138 56.100 +*N right_top_grid_pin_1_[0]:6 *C 92.000 56.145 +*N right_top_grid_pin_1_[0]:7 *C 87.040 85.340 +*N right_top_grid_pin_1_[0]:8 *C 86.940 85.680 +*N right_top_grid_pin_1_[0]:9 *C 91.955 85.680 +*N right_top_grid_pin_1_[0]:10 *C 92.000 85.680 +*N right_top_grid_pin_1_[0]:11 *C 92.000 101.615 +*N right_top_grid_pin_1_[0]:12 *C 92.000 101.660 +*N right_top_grid_pin_1_[0]:13 *C 92.000 102.000 +*N right_top_grid_pin_1_[0]:14 *C 132.020 102.000 +*N right_top_grid_pin_1_[0]:15 *C 132.020 101.660 +*N right_top_grid_pin_1_[0]:16 *C 139.335 101.660 +*N right_top_grid_pin_1_[0]:17 *C 139.380 101.705 + +*CAP +0 right_top_grid_pin_1_[0] 2.866664e-05 +1 mux_right_track_0\/mux_l1_in_0_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:A1 1e-06 +3 mux_right_track_8\/mux_l1_in_0_:A1 1e-06 +4 right_top_grid_pin_1_[0]:4 0.0004105376 +5 right_top_grid_pin_1_[0]:5 0.0004105376 +6 right_top_grid_pin_1_[0]:6 0.001407785 +7 right_top_grid_pin_1_[0]:7 5.392366e-05 +8 right_top_grid_pin_1_[0]:8 0.0002845774 +9 right_top_grid_pin_1_[0]:9 0.0002582993 +10 right_top_grid_pin_1_[0]:10 0.002160074 +11 right_top_grid_pin_1_[0]:11 0.0007242734 +12 right_top_grid_pin_1_[0]:12 4.759387e-05 +13 right_top_grid_pin_1_[0]:13 0.001917935 +14 right_top_grid_pin_1_[0]:14 0.001915649 +15 right_top_grid_pin_1_[0]:15 0.0004159139 +16 right_top_grid_pin_1_[0]:16 0.0003956765 +17 right_top_grid_pin_1_[0]:17 2.866664e-05 +18 right_top_grid_pin_1_[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001351777 +19 right_top_grid_pin_1_[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.63682e-05 +20 right_top_grid_pin_1_[0]:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001351777 +21 right_top_grid_pin_1_[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.63682e-05 + +*RES +0 right_top_grid_pin_1_[0] right_top_grid_pin_1_[0]:17 0.0002946429 +1 right_top_grid_pin_1_[0]:12 right_top_grid_pin_1_[0]:11 0.0045 +2 right_top_grid_pin_1_[0]:11 right_top_grid_pin_1_[0]:10 0.01422768 +3 right_top_grid_pin_1_[0]:16 right_top_grid_pin_1_[0]:15 0.00653125 +4 right_top_grid_pin_1_[0]:17 right_top_grid_pin_1_[0]:16 0.0045 +5 right_top_grid_pin_1_[0]:5 mux_right_track_4\/mux_l1_in_0_:A1 0.152 +6 right_top_grid_pin_1_[0]:5 right_top_grid_pin_1_[0]:4 0.004040179 +7 right_top_grid_pin_1_[0]:6 right_top_grid_pin_1_[0]:5 0.0045 +8 right_top_grid_pin_1_[0]:4 mux_right_track_8\/mux_l1_in_0_:A1 0.152 +9 right_top_grid_pin_1_[0]:9 right_top_grid_pin_1_[0]:8 0.004477679 +10 right_top_grid_pin_1_[0]:10 right_top_grid_pin_1_[0]:9 0.0045 +11 right_top_grid_pin_1_[0]:10 right_top_grid_pin_1_[0]:6 0.02637054 +12 right_top_grid_pin_1_[0]:7 mux_right_track_0\/mux_l1_in_0_:A1 0.152 +13 right_top_grid_pin_1_[0]:8 right_top_grid_pin_1_[0]:7 0.0003035715 +14 right_top_grid_pin_1_[0]:13 right_top_grid_pin_1_[0]:12 0.0003035715 +15 right_top_grid_pin_1_[0]:14 right_top_grid_pin_1_[0]:13 0.03573214 +16 right_top_grid_pin_1_[0]:15 right_top_grid_pin_1_[0]:14 0.0003035715 + +*END + +*D_NET chany_bottom_in[10] 0.009117606 //LENGTH 65.630 LUMPCC 0.00270529 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 62.560 1.290 +*I mux_left_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 66.070 55.420 +*I mux_right_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 70.380 56.100 +*N chany_bottom_in[10]:3 *C 61.850 4.760 +*N chany_bottom_in[10]:4 *C 62.160 55.080 +*N chany_bottom_in[10]:5 *C 70.358 56.073 +*N chany_bottom_in[10]:6 *C 70.345 55.760 +*N chany_bottom_in[10]:7 *C 66.240 55.760 +*N chany_bottom_in[10]:8 *C 66.070 55.420 +*N chany_bottom_in[10]:9 *C 66.240 55.080 +*N chany_bottom_in[10]:10 *C 62.605 55.080 +*N chany_bottom_in[10]:11 *C 62.560 55.080 +*N chany_bottom_in[10]:12 *C 62.560 55.080 +*N chany_bottom_in[10]:13 *C 62.560 55.073 +*N chany_bottom_in[10]:14 *C 62.560 4.768 +*N chany_bottom_in[10]:15 *C 62.558 4.760 +*N chany_bottom_in[10]:16 *C 62.560 4.703 + +*CAP +0 chany_bottom_in[10] 0.0002091869 +1 mux_left_track_17\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_4\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[10]:3 0.0001231582 +4 chany_bottom_in[10]:4 9.26336e-05 +5 chany_bottom_in[10]:5 3.064022e-05 +6 chany_bottom_in[10]:6 0.0003373931 +7 chany_bottom_in[10]:7 0.0003273394 +8 chany_bottom_in[10]:8 6.810798e-05 +9 chany_bottom_in[10]:9 0.0002702941 +10 chany_bottom_in[10]:10 0.0002497075 +11 chany_bottom_in[10]:11 3.600357e-05 +12 chany_bottom_in[10]:12 9.26336e-05 +13 chany_bottom_in[10]:13 0.002120436 +14 chany_bottom_in[10]:14 0.002120436 +15 chany_bottom_in[10]:15 0.0001231582 +16 chany_bottom_in[10]:16 0.0002091869 +17 chany_bottom_in[10]:13 chanx_left_in[12]:12 0.001020841 +18 chany_bottom_in[10]:14 chanx_left_in[12]:13 0.001020841 +19 chany_bottom_in[10]:13 chany_bottom_in[4]:15 0.0003318042 +20 chany_bottom_in[10]:14 chany_bottom_in[4]:16 0.0003318042 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:16 0.003046875 +1 chany_bottom_in[10]:5 mux_right_track_4\/mux_l1_in_1_:A1 0.152 +2 chany_bottom_in[10]:8 mux_left_track_17\/mux_l1_in_1_:A0 0.152 +3 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.0003035715 +4 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.003245536 +5 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.0045 +6 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.00341 +7 chany_bottom_in[10]:12 chany_bottom_in[10]:4 5.69697e-05 +8 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.00341 +9 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.00341 +10 chany_bottom_in[10]:15 chany_bottom_in[10]:3 0.0001039141 +11 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.007881116 +12 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.00341 +13 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.0003035715 +14 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.003665179 +15 chany_bottom_in[10]:6 chany_bottom_in[10]:5 0.0002111487 + +*END + +*D_NET bottom_left_grid_pin_35_[0] 0.01666394 //LENGTH 125.525 LUMPCC 0.005076018 DR + +*CONN +*P bottom_left_grid_pin_35_[0] I *L 0.29796 *C 29.825 8.160 +*I mux_bottom_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 27.430 37.060 +*I mux_bottom_track_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 29.730 44.540 +*I mux_bottom_track_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 34.790 60.520 +*I mux_bottom_track_27\/mux_l1_in_0_:A0 I *L 0.001631 *C 90.460 9.860 +*N bottom_left_grid_pin_35_[0]:5 *C 90.422 9.860 +*N bottom_left_grid_pin_35_[0]:6 *C 89.285 9.860 +*N bottom_left_grid_pin_35_[0]:7 *C 89.240 9.815 +*N bottom_left_grid_pin_35_[0]:8 *C 89.240 8.898 +*N bottom_left_grid_pin_35_[0]:9 *C 89.233 8.840 +*N bottom_left_grid_pin_35_[0]:10 *C 80.195 8.840 +*N bottom_left_grid_pin_35_[0]:11 *C 34.753 60.520 +*N bottom_left_grid_pin_35_[0]:12 *C 34.085 60.520 +*N bottom_left_grid_pin_35_[0]:13 *C 34.040 60.475 +*N bottom_left_grid_pin_35_[0]:14 *C 34.040 44.585 +*N bottom_left_grid_pin_35_[0]:15 *C 33.995 44.540 +*N bottom_left_grid_pin_35_[0]:16 *C 29.768 44.540 +*N bottom_left_grid_pin_35_[0]:17 *C 29.440 44.540 +*N bottom_left_grid_pin_35_[0]:18 *C 29.440 44.495 +*N bottom_left_grid_pin_35_[0]:19 *C 27.468 37.060 +*N bottom_left_grid_pin_35_[0]:20 *C 29.395 37.060 +*N bottom_left_grid_pin_35_[0]:21 *C 29.440 37.060 +*N bottom_left_grid_pin_35_[0]:22 *C 29.440 31.620 +*N bottom_left_grid_pin_35_[0]:23 *C 30.360 31.620 +*N bottom_left_grid_pin_35_[0]:24 *C 30.360 8.898 +*N bottom_left_grid_pin_35_[0]:25 *C 30.367 8.840 +*N bottom_left_grid_pin_35_[0]:26 *C 29.900 8.828 + +*CAP +0 bottom_left_grid_pin_35_[0] 3.852931e-05 +1 mux_bottom_track_3\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_7\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_11\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_27\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_35_[0]:5 9.903953e-05 +6 bottom_left_grid_pin_35_[0]:6 9.903953e-05 +7 bottom_left_grid_pin_35_[0]:7 8.406217e-05 +8 bottom_left_grid_pin_35_[0]:8 8.406217e-05 +9 bottom_left_grid_pin_35_[0]:9 0.0005181574 +10 bottom_left_grid_pin_35_[0]:10 0.002936925 +11 bottom_left_grid_pin_35_[0]:11 6.870848e-05 +12 bottom_left_grid_pin_35_[0]:12 6.870848e-05 +13 bottom_left_grid_pin_35_[0]:13 0.0008087173 +14 bottom_left_grid_pin_35_[0]:14 0.0008087173 +15 bottom_left_grid_pin_35_[0]:15 0.0002748878 +16 bottom_left_grid_pin_35_[0]:16 0.0002954209 +17 bottom_left_grid_pin_35_[0]:17 5.568723e-05 +18 bottom_left_grid_pin_35_[0]:18 0.0003529619 +19 bottom_left_grid_pin_35_[0]:19 0.0001715481 +20 bottom_left_grid_pin_35_[0]:20 0.0001715481 +21 bottom_left_grid_pin_35_[0]:21 0.0005328634 +22 bottom_left_grid_pin_35_[0]:22 0.0001694199 +23 bottom_left_grid_pin_35_[0]:23 0.0006999577 +24 bottom_left_grid_pin_35_[0]:24 0.0006783285 +25 bottom_left_grid_pin_35_[0]:25 0.002473433 +26 bottom_left_grid_pin_35_[0]:26 9.319392e-05 +27 bottom_left_grid_pin_35_[0] prog_clk[0]:559 1.584735e-05 +28 bottom_left_grid_pin_35_[0]:9 prog_clk[0]:131 0.0001749759 +29 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:218 0.0001322161 +30 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:324 0.0003781361 +31 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:325 0.0002751785 +32 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:557 9.341728e-06 +33 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:560 0.000217655 +34 bottom_left_grid_pin_35_[0]:25 prog_clk[0]:561 4.515592e-05 +35 bottom_left_grid_pin_35_[0]:18 prog_clk[0]:482 4.576787e-05 +36 bottom_left_grid_pin_35_[0]:18 prog_clk[0]:486 6.57484e-05 +37 bottom_left_grid_pin_35_[0]:21 prog_clk[0]:483 4.576787e-05 +38 bottom_left_grid_pin_35_[0]:21 prog_clk[0]:486 0.0001187001 +39 bottom_left_grid_pin_35_[0]:21 prog_clk[0]:487 6.57484e-05 +40 bottom_left_grid_pin_35_[0]:14 prog_clk[0]:356 8.528598e-07 +41 bottom_left_grid_pin_35_[0]:14 prog_clk[0]:360 3.497606e-07 +42 bottom_left_grid_pin_35_[0]:14 prog_clk[0]:459 6.119796e-05 +43 bottom_left_grid_pin_35_[0]:14 prog_clk[0]:483 7.938994e-09 +44 bottom_left_grid_pin_35_[0]:13 prog_clk[0]:350 8.528598e-07 +45 bottom_left_grid_pin_35_[0]:13 prog_clk[0]:356 3.497606e-07 +46 bottom_left_grid_pin_35_[0]:13 prog_clk[0]:458 6.119796e-05 +47 bottom_left_grid_pin_35_[0]:13 prog_clk[0]:482 7.938994e-09 +48 bottom_left_grid_pin_35_[0]:22 prog_clk[0]:487 0.0001187001 +49 bottom_left_grid_pin_35_[0]:22 prog_clk[0]:496 5.232433e-06 +50 bottom_left_grid_pin_35_[0]:23 prog_clk[0]:497 5.232433e-06 +51 bottom_left_grid_pin_35_[0]:26 prog_clk[0]:558 1.584735e-05 +52 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:131 0.0001322161 +53 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:218 0.000553112 +54 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:324 0.0002751785 +55 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:325 0.000217655 +56 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:556 9.341728e-06 +57 bottom_left_grid_pin_35_[0]:10 prog_clk[0]:560 4.515592e-05 +58 bottom_left_grid_pin_35_[0]:24 bottom_left_grid_pin_41_[0]:26 0.0004778961 +59 bottom_left_grid_pin_35_[0]:25 bottom_left_grid_pin_41_[0]:27 1.34528e-05 +60 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_41_[0]:25 2.119453e-06 +61 bottom_left_grid_pin_35_[0]:22 bottom_left_grid_pin_41_[0]:23 2.622661e-05 +62 bottom_left_grid_pin_35_[0]:22 bottom_left_grid_pin_41_[0]:26 2.119453e-06 +63 bottom_left_grid_pin_35_[0]:23 bottom_left_grid_pin_41_[0]:24 2.622661e-05 +64 bottom_left_grid_pin_35_[0]:23 bottom_left_grid_pin_41_[0]:25 0.0004778961 +65 bottom_left_grid_pin_35_[0]:10 bottom_left_grid_pin_41_[0]:17 1.34528e-05 +66 bottom_left_grid_pin_35_[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 8.139396e-06 +67 bottom_left_grid_pin_35_[0]:24 mux_tree_tapbuf_size7_1_sram[0]:26 0.0002001704 +68 bottom_left_grid_pin_35_[0]:24 mux_tree_tapbuf_size7_1_sram[0]:24 5.214785e-05 +69 bottom_left_grid_pin_35_[0]:20 mux_tree_tapbuf_size7_1_sram[0]:18 1.04219e-05 +70 bottom_left_grid_pin_35_[0]:21 mux_tree_tapbuf_size7_1_sram[0]:19 0.0001191097 +71 bottom_left_grid_pin_35_[0]:19 mux_tree_tapbuf_size7_1_sram[0]:17 1.04219e-05 +72 bottom_left_grid_pin_35_[0]:22 mux_tree_tapbuf_size7_1_sram[0]:20 0.0001240303 +73 bottom_left_grid_pin_35_[0]:23 mux_tree_tapbuf_size7_1_sram[0]:23 5.214785e-05 +74 bottom_left_grid_pin_35_[0]:23 mux_tree_tapbuf_size7_1_sram[0]:21 1.306001e-05 +75 bottom_left_grid_pin_35_[0]:23 mux_tree_tapbuf_size7_1_sram[0]:25 0.0002001704 +76 bottom_left_grid_pin_35_[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.704025e-05 +77 bottom_left_grid_pin_35_[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.704025e-05 + +*RES +0 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_35_[0]:26 0.000104575 +1 bottom_left_grid_pin_35_[0]:8 bottom_left_grid_pin_35_[0]:7 0.0008191965 +2 bottom_left_grid_pin_35_[0]:9 bottom_left_grid_pin_35_[0]:8 0.00341 +3 bottom_left_grid_pin_35_[0]:6 bottom_left_grid_pin_35_[0]:5 0.001015625 +4 bottom_left_grid_pin_35_[0]:7 bottom_left_grid_pin_35_[0]:6 0.0045 +5 bottom_left_grid_pin_35_[0]:5 mux_bottom_track_27\/mux_l1_in_0_:A0 0.152 +6 bottom_left_grid_pin_35_[0]:24 bottom_left_grid_pin_35_[0]:23 0.02028795 +7 bottom_left_grid_pin_35_[0]:25 bottom_left_grid_pin_35_[0]:24 0.00341 +8 bottom_left_grid_pin_35_[0]:25 bottom_left_grid_pin_35_[0]:10 0.007806308 +9 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_35_[0]:16 0.0001779891 +10 bottom_left_grid_pin_35_[0]:18 bottom_left_grid_pin_35_[0]:17 0.0045 +11 bottom_left_grid_pin_35_[0]:16 mux_bottom_track_7\/mux_l1_in_0_:A0 0.152 +12 bottom_left_grid_pin_35_[0]:16 bottom_left_grid_pin_35_[0]:15 0.003774554 +13 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_35_[0]:19 0.001720982 +14 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_35_[0]:20 0.0045 +15 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_35_[0]:18 0.006638393 +16 bottom_left_grid_pin_35_[0]:19 mux_bottom_track_3\/mux_l1_in_0_:A0 0.152 +17 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:14 0.0045 +18 bottom_left_grid_pin_35_[0]:14 bottom_left_grid_pin_35_[0]:13 0.0141875 +19 bottom_left_grid_pin_35_[0]:12 bottom_left_grid_pin_35_[0]:11 0.0005959822 +20 bottom_left_grid_pin_35_[0]:13 bottom_left_grid_pin_35_[0]:12 0.0045 +21 bottom_left_grid_pin_35_[0]:11 mux_bottom_track_11\/mux_l1_in_0_:A0 0.152 +22 bottom_left_grid_pin_35_[0]:22 bottom_left_grid_pin_35_[0]:21 0.004857143 +23 bottom_left_grid_pin_35_[0]:23 bottom_left_grid_pin_35_[0]:22 0.0008214285 +24 bottom_left_grid_pin_35_[0]:26 bottom_left_grid_pin_35_[0]:25 6.975397e-05 +25 bottom_left_grid_pin_35_[0]:10 bottom_left_grid_pin_35_[0]:9 0.001415875 + +*END + +*D_NET chanx_left_in[11] 0.003531766 //LENGTH 24.525 LUMPCC 0.0007362427 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 63.920 +*I mux_bottom_track_7\/mux_l1_in_3_:A1 I *L 0.00198 *C 17.120 56.100 +*N chanx_left_in[11]:2 *C 17.082 56.100 +*N chanx_left_in[11]:3 *C 11.545 56.100 +*N chanx_left_in[11]:4 *C 11.500 56.145 +*N chanx_left_in[11]:5 *C 11.500 63.863 +*N chanx_left_in[11]:6 *C 11.492 63.920 + +*CAP +0 chanx_left_in[11] 0.0005246992 +1 mux_bottom_track_7\/mux_l1_in_3_:A1 1e-06 +2 chanx_left_in[11]:2 0.0004400419 +3 chanx_left_in[11]:3 0.0004400419 +4 chanx_left_in[11]:4 0.0004325206 +5 chanx_left_in[11]:5 0.0004325206 +6 chanx_left_in[11]:6 0.0005246992 +7 chanx_left_in[11] chanx_right_in[17]:11 0.0003681214 +8 chanx_left_in[11]:6 chanx_right_in[17]:12 0.0003681214 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:6 0.001607792 +1 chanx_left_in[11]:2 mux_bottom_track_7\/mux_l1_in_3_:A1 0.152 +2 chanx_left_in[11]:3 chanx_left_in[11]:2 0.004944196 +3 chanx_left_in[11]:4 chanx_left_in[11]:3 0.0045 +4 chanx_left_in[11]:5 chanx_left_in[11]:4 0.006890625 +5 chanx_left_in[11]:6 chanx_left_in[11]:5 0.00341 + +*END + +*D_NET chanx_left_in[19] 0.006521329 //LENGTH 47.015 LUMPCC 0.002061678 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 81.600 +*I mux_bottom_track_11\/mux_l2_in_1_:A1 I *L 0.00198 *C 37.360 74.460 +*N chanx_left_in[19]:2 *C 37.360 74.460 +*N chanx_left_in[19]:3 *C 37.260 74.120 +*N chanx_left_in[19]:4 *C 30.405 74.120 +*N chanx_left_in[19]:5 *C 30.330 74.150 +*N chanx_left_in[19]:6 *C 30.315 74.460 +*N chanx_left_in[19]:7 *C 29.900 74.460 +*N chanx_left_in[19]:8 *C 29.900 82.223 +*N chanx_left_in[19]:9 *C 29.893 82.280 +*N chanx_left_in[19]:10 *C 5.520 82.280 +*N chanx_left_in[19]:11 *C 5.520 81.600 + +*CAP +0 chanx_left_in[19] 0.0002458403 +1 mux_bottom_track_11\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[19]:2 5.549462e-05 +3 chanx_left_in[19]:3 0.0004821308 +4 chanx_left_in[19]:4 0.0004548408 +5 chanx_left_in[19]:5 4.383586e-05 +6 chanx_left_in[19]:6 7.446021e-05 +7 chanx_left_in[19]:7 0.0004301309 +8 chanx_left_in[19]:8 0.0003995065 +9 chanx_left_in[19]:9 0.0009578897 +10 chanx_left_in[19]:10 0.001013285 +11 chanx_left_in[19]:11 0.0003012359 +12 chanx_left_in[19] chanx_left_out[12] 9.055948e-05 +13 chanx_left_in[19]:9 chanx_left_out[12]:2 0.0009402797 +14 chanx_left_in[19]:11 chanx_left_out[12]:2 9.055948e-05 +15 chanx_left_in[19]:10 chanx_left_out[12] 0.0009402797 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:11 0.0006720999 +1 chanx_left_in[19]:8 chanx_left_in[19]:7 0.006930804 +2 chanx_left_in[19]:9 chanx_left_in[19]:8 0.00341 +3 chanx_left_in[19]:4 chanx_left_in[19]:3 0.006120536 +4 chanx_left_in[19]:5 chanx_left_in[19]:4 0.0045 +5 chanx_left_in[19]:2 mux_bottom_track_11\/mux_l2_in_1_:A1 0.152 +6 chanx_left_in[19]:3 chanx_left_in[19]:2 0.0003035715 +7 chanx_left_in[19]:7 chanx_left_in[19]:6 0.0003705357 +8 chanx_left_in[19]:6 chanx_left_in[19]:5 0.00019375 +9 chanx_left_in[19]:11 chanx_left_in[19]:10 0.0001065333 +10 chanx_left_in[19]:10 chanx_left_in[19]:9 0.003818358 + +*END + +*D_NET chanx_right_out[12] 0.001965149 //LENGTH 16.520 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 124.720 42.500 +*P chanx_right_out[12] O *L 0.7423 *C 140.450 42.160 +*N chanx_right_out[12]:2 *C 138.007 42.160 +*N chanx_right_out[12]:3 *C 138.000 42.160 +*N chanx_right_out[12]:4 *C 138.000 42.500 +*N chanx_right_out[12]:5 *C 137.955 42.500 +*N chanx_right_out[12]:6 *C 124.758 42.500 + +*CAP +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[12] 0.0002073784 +2 chanx_right_out[12]:2 0.0002073784 +3 chanx_right_out[12]:3 5.669547e-05 +4 chanx_right_out[12]:4 5.263229e-05 +5 chanx_right_out[12]:5 0.000720032 +6 chanx_right_out[12]:6 0.000720032 + +*RES +0 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[12]:6 0.152 +1 chanx_right_out[12]:6 chanx_right_out[12]:5 0.01178348 +2 chanx_right_out[12]:5 chanx_right_out[12]:4 0.0045 +3 chanx_right_out[12]:4 chanx_right_out[12]:3 0.0001634615 +4 chanx_right_out[12]:3 chanx_right_out[12]:2 0.00341 +5 chanx_right_out[12]:2 chanx_right_out[12] 0.0003826583 + +*END + +*D_NET chany_bottom_out[2] 0.001306384 //LENGTH 12.105 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 43.760 4.080 +*P chany_bottom_out[2] O *L 0.7423 *C 52.440 1.290 +*N chany_bottom_out[2]:2 *C 52.440 3.695 +*N chany_bottom_out[2]:3 *C 52.395 3.740 +*N chany_bottom_out[2]:4 *C 43.700 3.740 +*N chany_bottom_out[2]:5 *C 43.760 4.080 + +*CAP +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[2] 0.0001481495 +2 chany_bottom_out[2]:2 0.0001481495 +3 chany_bottom_out[2]:3 0.0004653968 +4 chany_bottom_out[2]:4 0.0004913928 +5 chany_bottom_out[2]:5 5.229512e-05 + +*RES +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[2]:5 0.152 +1 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.0003035715 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +3 chany_bottom_out[2]:2 chany_bottom_out[2] 0.002147322 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.007763393 + +*END + +*D_NET chany_bottom_out[7] 0.001232431 //LENGTH 10.815 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 58.940 9.860 +*P chany_bottom_out[7] O *L 0.7423 *C 60.720 1.290 +*N chany_bottom_out[7]:2 *C 60.720 9.815 +*N chany_bottom_out[7]:3 *C 60.675 9.860 +*N chany_bottom_out[7]:4 *C 58.978 9.860 + +*CAP +0 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[7] 0.0004784859 +2 chany_bottom_out[7]:2 0.0004784859 +3 chany_bottom_out[7]:3 0.0001372298 +4 chany_bottom_out[7]:4 0.0001372298 + +*RES +0 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[7]:4 0.152 +1 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.001515625 +2 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0045 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.007611607 + +*END + +*D_NET chany_bottom_out[13] 0.003101347 //LENGTH 24.075 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_27\/mux_l2_in_0_:X O *L 0 *C 82.100 3.740 +*P chany_bottom_out[13] O *L 0.7423 *C 61.640 1.290 +*N chany_bottom_out[13]:2 *C 61.640 1.983 +*N chany_bottom_out[13]:3 *C 61.648 2.040 +*N chany_bottom_out[13]:4 *C 80.953 2.040 +*N chany_bottom_out[13]:5 *C 80.960 2.098 +*N chany_bottom_out[13]:6 *C 80.960 3.695 +*N chany_bottom_out[13]:7 *C 81.005 3.740 +*N chany_bottom_out[13]:8 *C 82.062 3.740 + +*CAP +0 mux_bottom_track_27\/mux_l2_in_0_:X 1e-06 +1 chany_bottom_out[13] 5.897843e-05 +2 chany_bottom_out[13]:2 5.897843e-05 +3 chany_bottom_out[13]:3 0.0012371 +4 chany_bottom_out[13]:4 0.0012371 +5 chany_bottom_out[13]:5 0.0001457687 +6 chany_bottom_out[13]:6 0.0001457687 +7 chany_bottom_out[13]:7 0.0001083266 +8 chany_bottom_out[13]:8 0.0001083266 + +*RES +0 mux_bottom_track_27\/mux_l2_in_0_:X chany_bottom_out[13]:8 0.152 +1 chany_bottom_out[13]:8 chany_bottom_out[13]:7 0.0009441964 +2 chany_bottom_out[13]:7 chany_bottom_out[13]:6 0.0045 +3 chany_bottom_out[13]:6 chany_bottom_out[13]:5 0.001426339 +4 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.00341 +5 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.00302445 +6 chany_bottom_out[13]:2 chany_bottom_out[13] 0.0006183035 +7 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.00341 + +*END + +*D_NET ropt_net_174 0.002830324 //LENGTH 25.285 LUMPCC 0.0003118972 DR + +*CONN +*I mux_left_track_3\/BUFT_P_132:X O *L 0 *C 18.665 89.080 +*I ropt_mt_inst_794:A I *L 0.001766 *C 3.220 96.560 +*N ropt_net_174:2 *C 3.220 96.560 +*N ropt_net_174:3 *C 3.220 96.900 +*N ropt_net_174:4 *C 10.995 96.900 +*N ropt_net_174:5 *C 11.040 96.855 +*N ropt_net_174:6 *C 11.040 93.885 +*N ropt_net_174:7 *C 11.085 93.840 +*N ropt_net_174:8 *C 17.435 93.840 +*N ropt_net_174:9 *C 17.480 93.795 +*N ropt_net_174:10 *C 17.480 89.125 +*N ropt_net_174:11 *C 17.525 89.080 +*N ropt_net_174:12 *C 18.628 89.080 + +*CAP +0 mux_left_track_3\/BUFT_P_132:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_174:2 5.715609e-05 +3 ropt_net_174:3 0.0003801752 +4 ropt_net_174:4 0.0003521951 +5 ropt_net_174:5 0.0001961384 +6 ropt_net_174:6 0.0001961384 +7 ropt_net_174:7 0.0003454506 +8 ropt_net_174:8 0.0003454506 +9 ropt_net_174:9 0.0002349917 +10 ropt_net_174:10 0.0002349917 +11 ropt_net_174:11 8.686959e-05 +12 ropt_net_174:12 8.686959e-05 +13 ropt_net_174:4 left_top_grid_pin_1_[0]:15 0.0001096301 +14 ropt_net_174:3 left_top_grid_pin_1_[0]:16 0.0001096301 +15 ropt_net_174:4 ropt_net_214:2 4.631851e-05 +16 ropt_net_174:3 ropt_net_214:3 4.631851e-05 + +*RES +0 mux_left_track_3\/BUFT_P_132:X ropt_net_174:12 0.152 +1 ropt_net_174:12 ropt_net_174:11 0.000984375 +2 ropt_net_174:11 ropt_net_174:10 0.0045 +3 ropt_net_174:10 ropt_net_174:9 0.004169643 +4 ropt_net_174:8 ropt_net_174:7 0.005669643 +5 ropt_net_174:9 ropt_net_174:8 0.0045 +6 ropt_net_174:7 ropt_net_174:6 0.0045 +7 ropt_net_174:6 ropt_net_174:5 0.002651786 +8 ropt_net_174:4 ropt_net_174:3 0.006941964 +9 ropt_net_174:5 ropt_net_174:4 0.0045 +10 ropt_net_174:2 ropt_mt_inst_794:A 0.152 +11 ropt_net_174:3 ropt_net_174:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[1] 0.003469072 //LENGTH 25.500 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 82.185 9.520 +*I mem_bottom_track_37\/FTB_33__58:A I *L 0.001746 *C 71.300 9.520 +*I mux_bottom_track_37\/mux_l2_in_0_:S I *L 0.00357 *C 80.500 3.905 +*N mux_tree_tapbuf_size2_5_sram[1]:3 *C 80.500 3.905 +*N mux_tree_tapbuf_size2_5_sram[1]:4 *C 71.300 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:5 *C 71.300 9.475 +*N mux_tree_tapbuf_size2_5_sram[1]:6 *C 71.300 6.165 +*N mux_tree_tapbuf_size2_5_sram[1]:7 *C 71.345 6.120 +*N mux_tree_tapbuf_size2_5_sram[1]:8 *C 75.395 6.120 +*N mux_tree_tapbuf_size2_5_sram[1]:9 *C 75.440 6.075 +*N mux_tree_tapbuf_size2_5_sram[1]:10 *C 75.440 4.805 +*N mux_tree_tapbuf_size2_5_sram[1]:11 *C 75.485 4.760 +*N mux_tree_tapbuf_size2_5_sram[1]:12 *C 80.500 4.760 +*N mux_tree_tapbuf_size2_5_sram[1]:13 *C 83.215 4.760 +*N mux_tree_tapbuf_size2_5_sram[1]:14 *C 83.260 4.805 +*N mux_tree_tapbuf_size2_5_sram[1]:15 *C 83.260 9.475 +*N mux_tree_tapbuf_size2_5_sram[1]:16 *C 83.215 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:17 *C 82.223 9.520 + +*CAP +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_37\/FTB_33__58:A 1e-06 +2 mux_bottom_track_37\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[1]:3 8.932008e-05 +4 mux_tree_tapbuf_size2_5_sram[1]:4 3.37762e-05 +5 mux_tree_tapbuf_size2_5_sram[1]:5 0.0002196577 +6 mux_tree_tapbuf_size2_5_sram[1]:6 0.0002196577 +7 mux_tree_tapbuf_size2_5_sram[1]:7 0.0003152145 +8 mux_tree_tapbuf_size2_5_sram[1]:8 0.0003152145 +9 mux_tree_tapbuf_size2_5_sram[1]:9 0.0001126401 +10 mux_tree_tapbuf_size2_5_sram[1]:10 0.0001126401 +11 mux_tree_tapbuf_size2_5_sram[1]:11 0.000395176 +12 mux_tree_tapbuf_size2_5_sram[1]:12 0.0006445721 +13 mux_tree_tapbuf_size2_5_sram[1]:13 0.0001908997 +14 mux_tree_tapbuf_size2_5_sram[1]:14 0.0003076199 +15 mux_tree_tapbuf_size2_5_sram[1]:15 0.0003076199 +16 mux_tree_tapbuf_size2_5_sram[1]:16 0.0001010318 +17 mux_tree_tapbuf_size2_5_sram[1]:17 0.0001010318 + +*RES +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_5_sram[1]:17 0.152 +1 mux_tree_tapbuf_size2_5_sram[1]:3 mux_bottom_track_37\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_5_sram[1]:13 mux_tree_tapbuf_size2_5_sram[1]:12 0.002424107 +3 mux_tree_tapbuf_size2_5_sram[1]:14 mux_tree_tapbuf_size2_5_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size2_5_sram[1]:16 mux_tree_tapbuf_size2_5_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size2_5_sram[1]:15 mux_tree_tapbuf_size2_5_sram[1]:14 0.004169643 +6 mux_tree_tapbuf_size2_5_sram[1]:17 mux_tree_tapbuf_size2_5_sram[1]:16 0.0008861608 +7 mux_tree_tapbuf_size2_5_sram[1]:11 mux_tree_tapbuf_size2_5_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size2_5_sram[1]:10 mux_tree_tapbuf_size2_5_sram[1]:9 0.001133929 +9 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:7 0.003616071 +10 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:6 0.0045 +12 mux_tree_tapbuf_size2_5_sram[1]:6 mux_tree_tapbuf_size2_5_sram[1]:5 0.002955357 +13 mux_tree_tapbuf_size2_5_sram[1]:4 mem_bottom_track_37\/FTB_33__58:A 0.152 +14 mux_tree_tapbuf_size2_5_sram[1]:5 mux_tree_tapbuf_size2_5_sram[1]:4 0.0045 +15 mux_tree_tapbuf_size2_5_sram[1]:12 mux_tree_tapbuf_size2_5_sram[1]:11 0.004477679 +16 mux_tree_tapbuf_size2_5_sram[1]:12 mux_tree_tapbuf_size2_5_sram[1]:3 0.0007633929 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.003260213 //LENGTH 26.070 LUMPCC 0 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 114.845 36.720 +*I mux_right_track_32\/mux_l1_in_1_:S I *L 0.00357 *C 112.340 34.295 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 103.215 26.180 +*I mux_right_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 101.560 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 112.340 34.370 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 101.560 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 101.660 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 101.668 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 103.215 26.180 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 103.040 26.180 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 103.040 26.225 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 103.040 28.503 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 103.040 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 111.312 28.560 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 111.320 28.617 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 111.320 33.955 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 111.365 34.000 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 112.282 34.000 +*N mux_tree_tapbuf_size3_0_sram[0]:18 *C 112.340 34.295 +*N mux_tree_tapbuf_size3_0_sram[0]:19 *C 112.340 34.680 +*N mux_tree_tapbuf_size3_0_sram[0]:20 *C 114.495 34.680 +*N mux_tree_tapbuf_size3_0_sram[0]:21 *C 114.540 34.725 +*N mux_tree_tapbuf_size3_0_sram[0]:22 *C 114.540 36.675 +*N mux_tree_tapbuf_size3_0_sram[0]:23 *C 114.540 36.720 +*N mux_tree_tapbuf_size3_0_sram[0]:24 *C 114.845 36.720 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_32\/mux_l1_in_1_:S 1e-06 +2 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_right_track_32\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 1.332898e-05 +5 mux_tree_tapbuf_size3_0_sram[0]:5 3.406663e-05 +6 mux_tree_tapbuf_size3_0_sram[0]:6 3.89939e-05 +7 mux_tree_tapbuf_size3_0_sram[0]:7 0.0001278772 +8 mux_tree_tapbuf_size3_0_sram[0]:8 4.659257e-05 +9 mux_tree_tapbuf_size3_0_sram[0]:9 5.075683e-05 +10 mux_tree_tapbuf_size3_0_sram[0]:10 0.0001409742 +11 mux_tree_tapbuf_size3_0_sram[0]:11 0.0001409742 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0006311083 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0005032311 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0003044397 +15 mux_tree_tapbuf_size3_0_sram[0]:15 0.0003044397 +16 mux_tree_tapbuf_size3_0_sram[0]:16 6.948801e-05 +17 mux_tree_tapbuf_size3_0_sram[0]:17 8.954848e-05 +18 mux_tree_tapbuf_size3_0_sram[0]:18 7.991391e-05 +19 mux_tree_tapbuf_size3_0_sram[0]:19 0.0001814828 +20 mux_tree_tapbuf_size3_0_sram[0]:20 0.0001623974 +21 mux_tree_tapbuf_size3_0_sram[0]:21 0.0001183927 +22 mux_tree_tapbuf_size3_0_sram[0]:22 0.0001183927 +23 mux_tree_tapbuf_size3_0_sram[0]:23 5.274903e-05 +24 mux_tree_tapbuf_size3_0_sram[0]:24 4.706453e-05 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:24 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:20 mux_tree_tapbuf_size3_0_sram[0]:19 0.001924107 +2 mux_tree_tapbuf_size3_0_sram[0]:21 mux_tree_tapbuf_size3_0_sram[0]:20 0.0045 +3 mux_tree_tapbuf_size3_0_sram[0]:23 mux_tree_tapbuf_size3_0_sram[0]:22 0.0045 +4 mux_tree_tapbuf_size3_0_sram[0]:22 mux_tree_tapbuf_size3_0_sram[0]:21 0.001741071 +5 mux_tree_tapbuf_size3_0_sram[0]:24 mux_tree_tapbuf_size3_0_sram[0]:23 0.0001657609 +6 mux_tree_tapbuf_size3_0_sram[0]:18 mux_right_track_32\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:17 0.0001715116 +8 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:4 4.360465e-05 +9 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0045 +10 mux_tree_tapbuf_size3_0_sram[0]:7 mux_tree_tapbuf_size3_0_sram[0]:6 0.00341 +11 mux_tree_tapbuf_size3_0_sram[0]:5 mux_right_track_32\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.002033482 +13 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.00341 +14 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:7 0.000215025 +15 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 9.51087e-05 +16 mux_tree_tapbuf_size3_0_sram[0]:10 mux_tree_tapbuf_size3_0_sram[0]:9 0.0045 +17 mux_tree_tapbuf_size3_0_sram[0]:8 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +18 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0045 +19 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.004765625 +20 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.00341 +21 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.001296025 +22 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.0008191965 +23 mux_tree_tapbuf_size3_0_sram[0]:19 mux_tree_tapbuf_size3_0_sram[0]:18 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.01093784 //LENGTH 73.950 LUMPCC 0.003806887 DR + +*CONN +*I mem_right_track_32\/FTB_13__38:X O *L 0 *C 106.025 34.680 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 41.125 31.620 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 41.163 31.620 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 45.540 31.620 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 45.540 30.940 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 50.555 30.940 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 50.600 30.985 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 50.600 35.983 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 *C 50.608 36.040 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 *C 100.435 36.040 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 *C 105.333 36.040 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 *C 105.340 35.983 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:12 *C 105.340 34.725 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:13 *C 105.385 34.680 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:14 *C 105.988 34.680 + +*CAP +0 mem_right_track_32\/FTB_13__38:X 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0003731488 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0004167929 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.0004088779 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0003652338 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0003222175 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.0003222175 +8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.002122224 +9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.002305842 +10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 0.0001836187 +11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 9.374142e-05 +12 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:12 9.374142e-05 +13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:13 6.064669e-05 +14 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:14 6.064669e-05 +15 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 chanx_right_in[4]:21 0.0001122532 +16 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 chanx_right_in[4]:15 0.0005289104 +17 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 chanx_right_in[4]:20 0.0004920504 +18 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 chanx_right_in[4]:20 0.0006411636 +19 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 chanx_right_in[4]:21 0.0004920504 +20 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 chanx_right_in[16]:34 9.796207e-05 +21 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 chanx_right_in[16]:28 0.0002488208 +22 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 chanx_right_in[16]:33 0.0004234466 +23 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 chanx_right_in[16]:33 0.0003467829 +24 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 chanx_right_in[16]:34 0.0004234466 + +*RES +0 mem_right_track_32\/FTB_13__38:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:14 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:14 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:13 0.0005379464 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:12 0.0045 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:12 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 0.001122768 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 0.00341 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.000767275 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.004462054 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.00341 +8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.004477679 +9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0045 +10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.003908482 +12 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0006071429 +13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[0] 0.0015085 //LENGTH 13.200 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 24.225 61.200 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 17.655 64.260 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 26.780 61.200 +*N mux_tree_tapbuf_size4_0_sram[0]:3 *C 26.742 61.200 +*N mux_tree_tapbuf_size4_0_sram[0]:4 *C 17.693 64.260 +*N mux_tree_tapbuf_size4_0_sram[0]:5 *C 24.335 64.260 +*N mux_tree_tapbuf_size4_0_sram[0]:6 *C 24.380 64.215 +*N mux_tree_tapbuf_size4_0_sram[0]:7 *C 24.380 61.245 +*N mux_tree_tapbuf_size4_0_sram[0]:8 *C 24.425 61.200 +*N mux_tree_tapbuf_size4_0_sram[0]:9 *C 24.225 61.200 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_0_sram[0]:3 0.0001328373 +4 mux_tree_tapbuf_size4_0_sram[0]:4 0.0004161106 +5 mux_tree_tapbuf_size4_0_sram[0]:5 0.0004161106 +6 mux_tree_tapbuf_size4_0_sram[0]:6 0.0001719255 +7 mux_tree_tapbuf_size4_0_sram[0]:7 0.0001719255 +8 mux_tree_tapbuf_size4_0_sram[0]:8 0.0001498491 +9 mux_tree_tapbuf_size4_0_sram[0]:9 4.674151e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_0_sram[0]:9 0.152 +1 mux_tree_tapbuf_size4_0_sram[0]:3 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:3 0.002069197 +4 mux_tree_tapbuf_size4_0_sram[0]:7 mux_tree_tapbuf_size4_0_sram[0]:6 0.002651786 +5 mux_tree_tapbuf_size4_0_sram[0]:5 mux_tree_tapbuf_size4_0_sram[0]:4 0.005930804 +6 mux_tree_tapbuf_size4_0_sram[0]:6 mux_tree_tapbuf_size4_0_sram[0]:5 0.0045 +7 mux_tree_tapbuf_size4_0_sram[0]:4 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size4_0_sram[0]:9 mux_tree_tapbuf_size4_0_sram[0]:8 0.0001086957 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[0] 0.001920607 //LENGTH 14.465 LUMPCC 0.0004597768 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 101.965 37.060 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 104.060 39.440 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 97.235 33.660 +*N mux_tree_tapbuf_size4_2_sram[0]:3 *C 97.273 33.660 +*N mux_tree_tapbuf_size4_2_sram[0]:4 *C 98.855 33.660 +*N mux_tree_tapbuf_size4_2_sram[0]:5 *C 98.900 33.705 +*N mux_tree_tapbuf_size4_2_sram[0]:6 *C 98.900 37.015 +*N mux_tree_tapbuf_size4_2_sram[0]:7 *C 98.945 37.060 +*N mux_tree_tapbuf_size4_2_sram[0]:8 *C 104.023 39.440 +*N mux_tree_tapbuf_size4_2_sram[0]:9 *C 101.705 39.440 +*N mux_tree_tapbuf_size4_2_sram[0]:10 *C 101.660 39.395 +*N mux_tree_tapbuf_size4_2_sram[0]:11 *C 101.660 37.105 +*N mux_tree_tapbuf_size4_2_sram[0]:12 *C 101.615 37.060 +*N mux_tree_tapbuf_size4_2_sram[0]:13 *C 101.965 37.060 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size4_2_sram[0]:3 0.0001226876 +4 mux_tree_tapbuf_size4_2_sram[0]:4 0.0001226876 +5 mux_tree_tapbuf_size4_2_sram[0]:5 0.0001589931 +6 mux_tree_tapbuf_size4_2_sram[0]:6 0.0001589931 +7 mux_tree_tapbuf_size4_2_sram[0]:7 0.0001110842 +8 mux_tree_tapbuf_size4_2_sram[0]:8 0.0001628586 +9 mux_tree_tapbuf_size4_2_sram[0]:9 0.0001628586 +10 mux_tree_tapbuf_size4_2_sram[0]:10 0.0001413519 +11 mux_tree_tapbuf_size4_2_sram[0]:11 0.0001413519 +12 mux_tree_tapbuf_size4_2_sram[0]:12 0.000129625 +13 mux_tree_tapbuf_size4_2_sram[0]:13 4.533813e-05 +14 mux_tree_tapbuf_size4_2_sram[0]:7 chanx_left_in[10]:25 2.108582e-05 +15 mux_tree_tapbuf_size4_2_sram[0]:7 chanx_left_in[10]:29 8.130907e-05 +16 mux_tree_tapbuf_size4_2_sram[0]:6 chanx_left_in[10]:27 3.104424e-06 +17 mux_tree_tapbuf_size4_2_sram[0]:5 chanx_left_in[10]:26 3.104424e-06 +18 mux_tree_tapbuf_size4_2_sram[0]:12 chanx_left_in[10]:24 2.108582e-05 +19 mux_tree_tapbuf_size4_2_sram[0]:12 chanx_left_in[10]:25 4.931361e-06 +20 mux_tree_tapbuf_size4_2_sram[0]:12 chanx_left_in[10]:28 8.130907e-05 +21 mux_tree_tapbuf_size4_2_sram[0]:11 chanx_left_in[10]:26 6.090211e-06 +22 mux_tree_tapbuf_size4_2_sram[0]:10 chanx_left_in[10]:27 6.090211e-06 +23 mux_tree_tapbuf_size4_2_sram[0]:13 chanx_left_in[10]:24 4.931361e-06 +24 mux_tree_tapbuf_size4_2_sram[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.29445e-05 +25 mux_tree_tapbuf_size4_2_sram[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.29445e-05 +26 mux_tree_tapbuf_size4_2_sram[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.437026e-07 +27 mux_tree_tapbuf_size4_2_sram[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.987934e-05 +28 mux_tree_tapbuf_size4_2_sram[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.437026e-07 +29 mux_tree_tapbuf_size4_2_sram[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.987934e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size4_2_sram[0]:7 mux_tree_tapbuf_size4_2_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size4_2_sram[0]:6 mux_tree_tapbuf_size4_2_sram[0]:5 0.002955357 +3 mux_tree_tapbuf_size4_2_sram[0]:4 mux_tree_tapbuf_size4_2_sram[0]:3 0.001412946 +4 mux_tree_tapbuf_size4_2_sram[0]:5 mux_tree_tapbuf_size4_2_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size4_2_sram[0]:3 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size4_2_sram[0]:12 mux_tree_tapbuf_size4_2_sram[0]:11 0.0045 +7 mux_tree_tapbuf_size4_2_sram[0]:12 mux_tree_tapbuf_size4_2_sram[0]:7 0.002383929 +8 mux_tree_tapbuf_size4_2_sram[0]:11 mux_tree_tapbuf_size4_2_sram[0]:10 0.002044643 +9 mux_tree_tapbuf_size4_2_sram[0]:9 mux_tree_tapbuf_size4_2_sram[0]:8 0.002069197 +10 mux_tree_tapbuf_size4_2_sram[0]:10 mux_tree_tapbuf_size4_2_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size4_2_sram[0]:8 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size4_2_sram[0]:13 mux_tree_tapbuf_size4_2_sram[0]:12 0.0001902174 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[2] 0.001200012 //LENGTH 9.440 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 94.145 50.320 +*I mux_right_track_16\/mux_l3_in_0_:S I *L 0.00357 *C 93.280 52.360 +*I mem_right_track_16\/FTB_7__32:A I *L 0.001746 *C 95.680 47.600 +*N mux_tree_tapbuf_size5_1_sram[2]:3 *C 95.642 47.600 +*N mux_tree_tapbuf_size5_1_sram[2]:4 *C 95.265 47.600 +*N mux_tree_tapbuf_size5_1_sram[2]:5 *C 95.220 47.645 +*N mux_tree_tapbuf_size5_1_sram[2]:6 *C 95.220 50.320 +*N mux_tree_tapbuf_size5_1_sram[2]:7 *C 93.318 52.360 +*N mux_tree_tapbuf_size5_1_sram[2]:8 *C 94.715 52.360 +*N mux_tree_tapbuf_size5_1_sram[2]:9 *C 94.760 52.315 +*N mux_tree_tapbuf_size5_1_sram[2]:10 *C 94.760 50.320 +*N mux_tree_tapbuf_size5_1_sram[2]:11 *C 94.715 50.320 +*N mux_tree_tapbuf_size5_1_sram[2]:12 *C 94.183 50.320 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_16\/FTB_7__32:A 1e-06 +3 mux_tree_tapbuf_size5_1_sram[2]:3 6.824818e-05 +4 mux_tree_tapbuf_size5_1_sram[2]:4 6.824818e-05 +5 mux_tree_tapbuf_size5_1_sram[2]:5 0.0001919136 +6 mux_tree_tapbuf_size5_1_sram[2]:6 0.0002227844 +7 mux_tree_tapbuf_size5_1_sram[2]:7 0.0001323057 +8 mux_tree_tapbuf_size5_1_sram[2]:8 0.0001323057 +9 mux_tree_tapbuf_size5_1_sram[2]:9 0.0001245703 +10 mux_tree_tapbuf_size5_1_sram[2]:10 0.0001554411 +11 mux_tree_tapbuf_size5_1_sram[2]:11 5.05975e-05 +12 mux_tree_tapbuf_size5_1_sram[2]:12 5.05975e-05 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_1_sram[2]:12 0.152 +1 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:7 0.001247768 +2 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:8 0.0045 +3 mux_tree_tapbuf_size5_1_sram[2]:7 mux_right_track_16\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size5_1_sram[2]:4 mux_tree_tapbuf_size5_1_sram[2]:3 0.0003370536 +5 mux_tree_tapbuf_size5_1_sram[2]:5 mux_tree_tapbuf_size5_1_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size5_1_sram[2]:3 mem_right_track_16\/FTB_7__32:A 0.152 +7 mux_tree_tapbuf_size5_1_sram[2]:11 mux_tree_tapbuf_size5_1_sram[2]:10 0.0045 +8 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:9 0.00178125 +9 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:6 0.0004107143 +10 mux_tree_tapbuf_size5_1_sram[2]:12 mux_tree_tapbuf_size5_1_sram[2]:11 0.0004754465 +11 mux_tree_tapbuf_size5_1_sram[2]:6 mux_tree_tapbuf_size5_1_sram[2]:5 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[1] 0.002084451 //LENGTH 16.605 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 59.185 36.720 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 64.760 34.000 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.515 39.100 +*I mux_left_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 60.160 42.160 +*N mux_tree_tapbuf_size5_3_sram[1]:4 *C 60.160 42.160 +*N mux_tree_tapbuf_size5_3_sram[1]:5 *C 60.260 42.115 +*N mux_tree_tapbuf_size5_3_sram[1]:6 *C 59.553 39.100 +*N mux_tree_tapbuf_size5_3_sram[1]:7 *C 60.215 39.100 +*N mux_tree_tapbuf_size5_3_sram[1]:8 *C 60.260 39.100 +*N mux_tree_tapbuf_size5_3_sram[1]:9 *C 60.720 39.100 +*N mux_tree_tapbuf_size5_3_sram[1]:10 *C 64.722 34.000 +*N mux_tree_tapbuf_size5_3_sram[1]:11 *C 60.765 34.000 +*N mux_tree_tapbuf_size5_3_sram[1]:12 *C 60.720 34.045 +*N mux_tree_tapbuf_size5_3_sram[1]:13 *C 60.720 36.720 +*N mux_tree_tapbuf_size5_3_sram[1]:14 *C 60.675 36.720 +*N mux_tree_tapbuf_size5_3_sram[1]:15 *C 59.223 36.720 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_1\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_3_sram[1]:4 2.840949e-05 +5 mux_tree_tapbuf_size5_3_sram[1]:5 0.0001898712 +6 mux_tree_tapbuf_size5_3_sram[1]:6 6.563418e-05 +7 mux_tree_tapbuf_size5_3_sram[1]:7 6.563418e-05 +8 mux_tree_tapbuf_size5_3_sram[1]:8 0.0002253673 +9 mux_tree_tapbuf_size5_3_sram[1]:9 0.0001759992 +10 mux_tree_tapbuf_size5_3_sram[1]:10 0.000253272 +11 mux_tree_tapbuf_size5_3_sram[1]:11 0.000253272 +12 mux_tree_tapbuf_size5_3_sram[1]:12 0.000152753 +13 mux_tree_tapbuf_size5_3_sram[1]:13 0.0003262077 +14 mux_tree_tapbuf_size5_3_sram[1]:14 0.0001720157 +15 mux_tree_tapbuf_size5_3_sram[1]:15 0.0001720157 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_3_sram[1]:15 0.152 +1 mux_tree_tapbuf_size5_3_sram[1]:11 mux_tree_tapbuf_size5_3_sram[1]:10 0.003533482 +2 mux_tree_tapbuf_size5_3_sram[1]:12 mux_tree_tapbuf_size5_3_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size5_3_sram[1]:10 mux_left_track_1\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size5_3_sram[1]:4 mux_left_track_1\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size5_3_sram[1]:5 mux_tree_tapbuf_size5_3_sram[1]:4 0.0045 +6 mux_tree_tapbuf_size5_3_sram[1]:7 mux_tree_tapbuf_size5_3_sram[1]:6 0.0005915179 +7 mux_tree_tapbuf_size5_3_sram[1]:8 mux_tree_tapbuf_size5_3_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size5_3_sram[1]:8 mux_tree_tapbuf_size5_3_sram[1]:5 0.002691964 +9 mux_tree_tapbuf_size5_3_sram[1]:6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size5_3_sram[1]:14 mux_tree_tapbuf_size5_3_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size5_3_sram[1]:13 mux_tree_tapbuf_size5_3_sram[1]:12 0.002388393 +12 mux_tree_tapbuf_size5_3_sram[1]:13 mux_tree_tapbuf_size5_3_sram[1]:9 0.002125 +13 mux_tree_tapbuf_size5_3_sram[1]:15 mux_tree_tapbuf_size5_3_sram[1]:14 0.001296875 +14 mux_tree_tapbuf_size5_3_sram[1]:9 mux_tree_tapbuf_size5_3_sram[1]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size5_6_sram[1] 0.003605119 //LENGTH 30.520 LUMPCC 0.0003677858 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 57.805 77.180 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 52.155 86.020 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 57.140 88.400 +*I mux_left_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 53.260 74.460 +*N mux_tree_tapbuf_size5_6_sram[1]:4 *C 53.297 74.460 +*N mux_tree_tapbuf_size5_6_sram[1]:5 *C 55.660 74.460 +*N mux_tree_tapbuf_size5_6_sram[1]:6 *C 57.103 88.400 +*N mux_tree_tapbuf_size5_6_sram[1]:7 *C 52.193 86.020 +*N mux_tree_tapbuf_size5_6_sram[1]:8 *C 53.775 86.020 +*N mux_tree_tapbuf_size5_6_sram[1]:9 *C 53.820 86.065 +*N mux_tree_tapbuf_size5_6_sram[1]:10 *C 53.820 88.355 +*N mux_tree_tapbuf_size5_6_sram[1]:11 *C 53.865 88.400 +*N mux_tree_tapbuf_size5_6_sram[1]:12 *C 55.660 88.400 +*N mux_tree_tapbuf_size5_6_sram[1]:13 *C 55.660 88.355 +*N mux_tree_tapbuf_size5_6_sram[1]:14 *C 55.660 74.845 +*N mux_tree_tapbuf_size5_6_sram[1]:15 *C 55.660 74.800 +*N mux_tree_tapbuf_size5_6_sram[1]:16 *C 57.455 74.800 +*N mux_tree_tapbuf_size5_6_sram[1]:17 *C 57.500 74.845 +*N mux_tree_tapbuf_size5_6_sram[1]:18 *C 57.500 77.135 +*N mux_tree_tapbuf_size5_6_sram[1]:19 *C 57.500 77.180 +*N mux_tree_tapbuf_size5_6_sram[1]:20 *C 57.805 77.180 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +3 mux_left_track_25\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_6_sram[1]:4 0.000162346 +5 mux_tree_tapbuf_size5_6_sram[1]:5 0.0001877492 +6 mux_tree_tapbuf_size5_6_sram[1]:6 9.141042e-05 +7 mux_tree_tapbuf_size5_6_sram[1]:7 0.0001184282 +8 mux_tree_tapbuf_size5_6_sram[1]:8 0.0001184282 +9 mux_tree_tapbuf_size5_6_sram[1]:9 9.306628e-05 +10 mux_tree_tapbuf_size5_6_sram[1]:10 9.306628e-05 +11 mux_tree_tapbuf_size5_6_sram[1]:11 8.906474e-05 +12 mux_tree_tapbuf_size5_6_sram[1]:12 0.0002159151 +13 mux_tree_tapbuf_size5_6_sram[1]:13 0.0006955333 +14 mux_tree_tapbuf_size5_6_sram[1]:14 0.0006955333 +15 mux_tree_tapbuf_size5_6_sram[1]:15 0.0001566226 +16 mux_tree_tapbuf_size5_6_sram[1]:16 0.0001312194 +17 mux_tree_tapbuf_size5_6_sram[1]:17 0.0001440491 +18 mux_tree_tapbuf_size5_6_sram[1]:18 0.0001440491 +19 mux_tree_tapbuf_size5_6_sram[1]:19 4.981583e-05 +20 mux_tree_tapbuf_size5_6_sram[1]:20 4.703608e-05 +21 mux_tree_tapbuf_size5_6_sram[1]:12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.88961e-05 +22 mux_tree_tapbuf_size5_6_sram[1]:12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.705128e-05 +23 mux_tree_tapbuf_size5_6_sram[1]:13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.574292e-05 +24 mux_tree_tapbuf_size5_6_sram[1]:14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.574292e-05 +25 mux_tree_tapbuf_size5_6_sram[1]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.705128e-05 +26 mux_tree_tapbuf_size5_6_sram[1]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.22026e-05 +27 mux_tree_tapbuf_size5_6_sram[1]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.22026e-05 +28 mux_tree_tapbuf_size5_6_sram[1]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.88961e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_6_sram[1]:20 0.152 +1 mux_tree_tapbuf_size5_6_sram[1]:12 mux_tree_tapbuf_size5_6_sram[1]:11 0.001602679 +2 mux_tree_tapbuf_size5_6_sram[1]:12 mux_tree_tapbuf_size5_6_sram[1]:6 0.001287946 +3 mux_tree_tapbuf_size5_6_sram[1]:13 mux_tree_tapbuf_size5_6_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size5_6_sram[1]:15 mux_tree_tapbuf_size5_6_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size5_6_sram[1]:15 mux_tree_tapbuf_size5_6_sram[1]:5 0.0003035715 +6 mux_tree_tapbuf_size5_6_sram[1]:14 mux_tree_tapbuf_size5_6_sram[1]:13 0.0120625 +7 mux_tree_tapbuf_size5_6_sram[1]:11 mux_tree_tapbuf_size5_6_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size5_6_sram[1]:10 mux_tree_tapbuf_size5_6_sram[1]:9 0.002044643 +9 mux_tree_tapbuf_size5_6_sram[1]:8 mux_tree_tapbuf_size5_6_sram[1]:7 0.001412946 +10 mux_tree_tapbuf_size5_6_sram[1]:9 mux_tree_tapbuf_size5_6_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size5_6_sram[1]:7 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size5_6_sram[1]:16 mux_tree_tapbuf_size5_6_sram[1]:15 0.001602679 +13 mux_tree_tapbuf_size5_6_sram[1]:17 mux_tree_tapbuf_size5_6_sram[1]:16 0.0045 +14 mux_tree_tapbuf_size5_6_sram[1]:19 mux_tree_tapbuf_size5_6_sram[1]:18 0.0045 +15 mux_tree_tapbuf_size5_6_sram[1]:18 mux_tree_tapbuf_size5_6_sram[1]:17 0.002044643 +16 mux_tree_tapbuf_size5_6_sram[1]:20 mux_tree_tapbuf_size5_6_sram[1]:19 0.0001657609 +17 mux_tree_tapbuf_size5_6_sram[1]:4 mux_left_track_25\/mux_l2_in_1_:S 0.152 +18 mux_tree_tapbuf_size5_6_sram[1]:6 mux_left_track_25\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size5_6_sram[1]:5 mux_tree_tapbuf_size5_6_sram[1]:4 0.002109375 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.00661194 //LENGTH 49.205 LUMPCC 0.0004193934 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 89.085 58.480 +*I mux_right_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 71.660 55.760 +*I mux_right_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 92.820 55.760 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 88.495 69.700 +*I mux_right_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 99.700 58.140 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 99.663 58.140 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 88.495 69.700 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 88.320 69.700 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 88.320 69.655 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 92.782 55.760 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 71.698 55.760 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 88.320 55.760 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 88.320 55.805 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 88.320 58.140 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 88.320 58.140 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 88.320 58.480 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 89.047 58.480 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_4\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_4\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_right_track_4\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 0.0006972491 +6 mux_tree_tapbuf_size6_1_sram[0]:6 5.232281e-05 +7 mux_tree_tapbuf_size6_1_sram[0]:7 5.67335e-05 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0006329453 +9 mux_tree_tapbuf_size6_1_sram[0]:9 0.0002475195 +10 mux_tree_tapbuf_size6_1_sram[0]:10 0.00116904 +11 mux_tree_tapbuf_size6_1_sram[0]:11 0.001449516 +12 mux_tree_tapbuf_size6_1_sram[0]:12 0.0001485052 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0008180441 +14 mux_tree_tapbuf_size6_1_sram[0]:14 0.0007255772 +15 mux_tree_tapbuf_size6_1_sram[0]:15 0.0001092109 +16 mux_tree_tapbuf_size6_1_sram[0]:16 8.088276e-05 +17 mux_tree_tapbuf_size6_1_sram[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.947728e-05 +18 mux_tree_tapbuf_size6_1_sram[0]:11 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001402194 +19 mux_tree_tapbuf_size6_1_sram[0]:10 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.947728e-05 +20 mux_tree_tapbuf_size6_1_sram[0]:9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001402194 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:16 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:5 mux_right_track_4\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 0.01484152 +3 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:9 0.003984375 +4 mux_tree_tapbuf_size6_1_sram[0]:12 mux_tree_tapbuf_size6_1_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size6_1_sram[0]:14 mux_tree_tapbuf_size6_1_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size6_1_sram[0]:14 mux_tree_tapbuf_size6_1_sram[0]:5 0.01012723 +7 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.002084821 +8 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:8 0.01028125 +9 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 9.51087e-05 +10 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size6_1_sram[0]:6 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.0006495535 +13 mux_tree_tapbuf_size6_1_sram[0]:10 mux_right_track_4\/mux_l1_in_1_:S 0.152 +14 mux_tree_tapbuf_size6_1_sram[0]:9 mux_right_track_4\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.0007175747 //LENGTH 5.930 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/FTB_2__27:X O *L 0 *C 107.865 66.300 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 109.655 69.700 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 109.655 69.700 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 109.480 69.700 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 109.480 69.655 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 109.480 66.345 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 109.435 66.300 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 107.903 66.300 + +*CAP +0 mem_right_track_4\/FTB_2__27:X 1e-06 +1 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 5.441367e-05 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 5.624323e-05 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.000184592 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.000184592 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.0001178669 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.0001178669 + +*RES +0 mem_right_track_4\/FTB_2__27:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.001368304 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.002955357 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[0] 0.00480278 //LENGTH 33.905 LUMPCC 0.0005301292 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 46.765 31.280 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 36.240 30.600 +*I mux_bottom_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 35.320 25.160 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 34.675 22.780 +*I mux_bottom_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 36.700 20.400 +*I mux_bottom_track_1\/mux_l1_in_3_:S I *L 0.00357 *C 39.460 34.295 +*N mux_tree_tapbuf_size7_0_sram[0]:6 *C 39.460 34.295 +*N mux_tree_tapbuf_size7_0_sram[0]:7 *C 36.663 20.400 +*N mux_tree_tapbuf_size7_0_sram[0]:8 *C 34.545 20.400 +*N mux_tree_tapbuf_size7_0_sram[0]:9 *C 34.500 20.445 +*N mux_tree_tapbuf_size7_0_sram[0]:10 *C 34.675 22.780 +*N mux_tree_tapbuf_size7_0_sram[0]:11 *C 34.500 22.780 +*N mux_tree_tapbuf_size7_0_sram[0]:12 *C 34.500 22.780 +*N mux_tree_tapbuf_size7_0_sram[0]:13 *C 34.500 25.115 +*N mux_tree_tapbuf_size7_0_sram[0]:14 *C 34.545 25.160 +*N mux_tree_tapbuf_size7_0_sram[0]:15 *C 35.320 25.160 +*N mux_tree_tapbuf_size7_0_sram[0]:16 *C 36.295 25.160 +*N mux_tree_tapbuf_size7_0_sram[0]:17 *C 36.340 25.205 +*N mux_tree_tapbuf_size7_0_sram[0]:18 *C 36.240 30.600 +*N mux_tree_tapbuf_size7_0_sram[0]:19 *C 36.340 30.600 +*N mux_tree_tapbuf_size7_0_sram[0]:20 *C 36.340 33.955 +*N mux_tree_tapbuf_size7_0_sram[0]:21 *C 36.385 34.000 +*N mux_tree_tapbuf_size7_0_sram[0]:22 *C 39.460 34.000 +*N mux_tree_tapbuf_size7_0_sram[0]:23 *C 46.875 34.000 +*N mux_tree_tapbuf_size7_0_sram[0]:24 *C 46.920 33.955 +*N mux_tree_tapbuf_size7_0_sram[0]:25 *C 46.920 31.325 +*N mux_tree_tapbuf_size7_0_sram[0]:26 *C 46.920 31.280 +*N mux_tree_tapbuf_size7_0_sram[0]:27 *C 46.765 31.280 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:S 1e-06 +3 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_track_1\/mux_l1_in_1_:S 1e-06 +5 mux_bottom_track_1\/mux_l1_in_3_:S 1e-06 +6 mux_tree_tapbuf_size7_0_sram[0]:6 6.583046e-05 +7 mux_tree_tapbuf_size7_0_sram[0]:7 0.0001644951 +8 mux_tree_tapbuf_size7_0_sram[0]:8 0.0001644951 +9 mux_tree_tapbuf_size7_0_sram[0]:9 0.0001454447 +10 mux_tree_tapbuf_size7_0_sram[0]:10 5.240508e-05 +11 mux_tree_tapbuf_size7_0_sram[0]:11 5.737531e-05 +12 mux_tree_tapbuf_size7_0_sram[0]:12 0.0003348699 +13 mux_tree_tapbuf_size7_0_sram[0]:13 0.0001574466 +14 mux_tree_tapbuf_size7_0_sram[0]:14 7.831836e-05 +15 mux_tree_tapbuf_size7_0_sram[0]:15 0.0001927438 +16 mux_tree_tapbuf_size7_0_sram[0]:16 8.347887e-05 +17 mux_tree_tapbuf_size7_0_sram[0]:17 0.0002261742 +18 mux_tree_tapbuf_size7_0_sram[0]:18 3.262665e-05 +19 mux_tree_tapbuf_size7_0_sram[0]:19 0.0004162143 +20 mux_tree_tapbuf_size7_0_sram[0]:20 0.0001548275 +21 mux_tree_tapbuf_size7_0_sram[0]:21 0.0002475165 +22 mux_tree_tapbuf_size7_0_sram[0]:22 0.0007286662 +23 mux_tree_tapbuf_size7_0_sram[0]:23 0.0004475341 +24 mux_tree_tapbuf_size7_0_sram[0]:24 0.0001963239 +25 mux_tree_tapbuf_size7_0_sram[0]:25 0.0001963239 +26 mux_tree_tapbuf_size7_0_sram[0]:26 6.38916e-05 +27 mux_tree_tapbuf_size7_0_sram[0]:27 5.964896e-05 +28 mux_tree_tapbuf_size7_0_sram[0]:20 bottom_left_grid_pin_38_[0]:7 8.889497e-05 +29 mux_tree_tapbuf_size7_0_sram[0]:17 bottom_left_grid_pin_38_[0]:21 0.0001425471 +30 mux_tree_tapbuf_size7_0_sram[0]:19 bottom_left_grid_pin_38_[0]:7 0.0001425471 +31 mux_tree_tapbuf_size7_0_sram[0]:19 bottom_left_grid_pin_38_[0]:21 8.889497e-05 +32 mux_tree_tapbuf_size7_0_sram[0]:12 bottom_left_grid_pin_38_[0]:7 3.424731e-06 +33 mux_tree_tapbuf_size7_0_sram[0]:12 bottom_left_grid_pin_38_[0]:21 1.031545e-06 +34 mux_tree_tapbuf_size7_0_sram[0]:8 bottom_left_grid_pin_38_[0]:17 5.493457e-07 +35 mux_tree_tapbuf_size7_0_sram[0]:8 bottom_left_grid_pin_38_[0]:19 8.435812e-06 +36 mux_tree_tapbuf_size7_0_sram[0]:8 bottom_left_grid_pin_38_[0]:20 2.018109e-05 +37 mux_tree_tapbuf_size7_0_sram[0]:9 bottom_left_grid_pin_38_[0]:21 3.424731e-06 +38 mux_tree_tapbuf_size7_0_sram[0]:9 bottom_left_grid_pin_38_[0]:22 1.031545e-06 +39 mux_tree_tapbuf_size7_0_sram[0]:7 bottom_left_grid_pin_38_[0]:16 5.493457e-07 +40 mux_tree_tapbuf_size7_0_sram[0]:7 bottom_left_grid_pin_38_[0]:18 2.018109e-05 +41 mux_tree_tapbuf_size7_0_sram[0]:7 bottom_left_grid_pin_38_[0]:20 8.435812e-06 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_0_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_0_sram[0]:14 mux_tree_tapbuf_size7_0_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size7_0_sram[0]:13 mux_tree_tapbuf_size7_0_sram[0]:12 0.002084821 +3 mux_tree_tapbuf_size7_0_sram[0]:21 mux_tree_tapbuf_size7_0_sram[0]:20 0.0045 +4 mux_tree_tapbuf_size7_0_sram[0]:20 mux_tree_tapbuf_size7_0_sram[0]:19 0.002995536 +5 mux_tree_tapbuf_size7_0_sram[0]:16 mux_tree_tapbuf_size7_0_sram[0]:15 0.0008705357 +6 mux_tree_tapbuf_size7_0_sram[0]:17 mux_tree_tapbuf_size7_0_sram[0]:16 0.0045 +7 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:22 0.006620536 +8 mux_tree_tapbuf_size7_0_sram[0]:24 mux_tree_tapbuf_size7_0_sram[0]:23 0.0045 +9 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:25 0.0045 +10 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_0_sram[0]:24 0.002348214 +11 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:26 8.423914e-05 +12 mux_tree_tapbuf_size7_0_sram[0]:6 mux_bottom_track_1\/mux_l1_in_3_:S 0.152 +13 mux_tree_tapbuf_size7_0_sram[0]:15 mux_bottom_track_1\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:14 0.0006919643 +15 mux_tree_tapbuf_size7_0_sram[0]:18 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:18 0.0045 +17 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:17 0.004816965 +18 mux_tree_tapbuf_size7_0_sram[0]:11 mux_tree_tapbuf_size7_0_sram[0]:10 9.510871e-05 +19 mux_tree_tapbuf_size7_0_sram[0]:12 mux_tree_tapbuf_size7_0_sram[0]:11 0.0045 +20 mux_tree_tapbuf_size7_0_sram[0]:12 mux_tree_tapbuf_size7_0_sram[0]:9 0.002084821 +21 mux_tree_tapbuf_size7_0_sram[0]:10 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +22 mux_tree_tapbuf_size7_0_sram[0]:8 mux_tree_tapbuf_size7_0_sram[0]:7 0.001890625 +23 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:8 0.0045 +24 mux_tree_tapbuf_size7_0_sram[0]:7 mux_bottom_track_1\/mux_l1_in_1_:S 0.152 +25 mux_tree_tapbuf_size7_0_sram[0]:22 mux_tree_tapbuf_size7_0_sram[0]:21 0.002745536 +26 mux_tree_tapbuf_size7_0_sram[0]:22 mux_tree_tapbuf_size7_0_sram[0]:6 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_1_ccff_tail[0] 0.001049697 //LENGTH 7.680 LUMPCC 0.0003198184 DR + +*CONN +*I mem_bottom_track_3\/FTB_21__46:X O *L 0 *C 32.895 34.000 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 30.995 39.100 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 *C 31.033 39.100 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 *C 32.615 39.100 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 *C 32.660 39.055 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 *C 32.660 34.045 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 *C 32.660 34.000 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 *C 32.895 34.000 + +*CAP +0 mem_bottom_track_3\/FTB_21__46:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 0.0001081078 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0001081078 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.000192272 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.000192272 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 5.969695e-05 +7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 6.742265e-05 +8 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 bottom_left_grid_pin_40_[0]:16 7.007632e-07 +9 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 bottom_left_grid_pin_40_[0]:20 0.00013944 +10 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 bottom_left_grid_pin_40_[0]:14 2.659538e-08 +11 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 bottom_left_grid_pin_40_[0]:17 1.974184e-05 +12 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 bottom_left_grid_pin_40_[0]:15 7.007632e-07 +13 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 bottom_left_grid_pin_40_[0]:17 0.00013944 +14 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 bottom_left_grid_pin_40_[0]:13 2.659538e-08 +15 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 bottom_left_grid_pin_40_[0]:16 1.974184e-05 + +*RES +0 mem_bottom_track_3\/FTB_21__46:X mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.004473214 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001920173 //LENGTH 17.265 LUMPCC 0.0004787202 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_0_:X O *L 0 *C 88.605 85.000 +*I mux_right_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 94.400 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 94.363 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 91.125 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 91.080 74.505 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 91.080 84.955 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 91.035 85.000 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 88.642 85.000 + +*CAP +0 mux_right_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001571514 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001571514 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004288611 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004288611 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001337139 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001337139 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 right_top_grid_pin_1_[0]:6 0.0001351777 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 right_top_grid_pin_1_[0]:9 4.63682e-05 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 right_top_grid_pin_1_[0]:10 0.0001351777 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 right_top_grid_pin_1_[0]:8 4.63682e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.781424e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.781424e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002890625 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.009330357 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002136161 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003609725 //LENGTH 28.000 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_1_:X O *L 0 *C 72.505 55.420 +*I mux_right_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 94.475 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 94.438 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 74.565 60.520 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 74.520 60.475 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 74.520 55.465 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 74.475 55.420 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 72.543 55.420 + +*CAP +0 mux_right_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001333726 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001333726 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002934398 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002934398 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001766973 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001766973 + +*RES +0 mux_right_track_4\/mux_l1_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0177433 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473214 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001725447 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002765028 //LENGTH 19.960 LUMPCC 0.0006757057 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_1_:X O *L 0 *C 86.305 55.420 +*I mux_right_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 105.975 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 105.938 55.420 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 86.343 55.420 + +*CAP +0 mux_right_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001043661 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001043661 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_1_sram[0]:9 0.0001402194 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_1_sram[0]:11 6.947728e-05 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_1_sram[0]:10 6.947728e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_1_sram[0]:11 0.0001402194 +8 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001281562 +9 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001281562 + +*RES +0 mux_right_track_8\/mux_l1_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.01749554 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001764376 //LENGTH 14.000 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 50.315 50.320 +*I mux_left_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 42.225 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 42.225 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 42.320 45.265 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 42.320 49.935 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 42.365 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 43.700 49.980 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 43.700 50.320 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 50.278 50.320 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.590797e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002914784 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002914784 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.391947e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001175242 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004778362 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004542315 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.004169643 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.005872768 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001191964 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003035715 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006277894 //LENGTH 4.730 LUMPCC 7.502233e-05 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_1_:X O *L 0 *C 56.755 51.000 +*I mux_left_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 55.490 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 55.490 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 55.660 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 55.660 53.675 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 55.660 51.045 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 55.705 51.000 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 56.718 51.000 + +*CAP +0 mux_left_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.803207e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.337898e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001251789 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001251789 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.949913e-05 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.949913e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[5]:23 3.751116e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[5]:22 3.751116e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.007070175 //LENGTH 54.270 LUMPCC 0.002397772 DR + +*CONN +*I mux_right_track_2\/mux_l3_in_0_:X O *L 0 *C 79.405 60.860 +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 124.835 53.210 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 124.797 53.102 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 117.345 53.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 117.300 53.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 117.293 53.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 79.588 53.040 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 79.580 53.098 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 79.580 60.815 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 79.580 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 79.405 60.860 + +*CAP +0 mux_right_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003824521 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003824521 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.128904e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00142812 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00142812 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004507907 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0004507907 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.821192e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.81764e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[9]:16 0.0003129449 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[9]:15 0.0003129449 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[14]:26 0.0002515939 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[14]:17 0.0002515939 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[16]:31 0.0001440257 +16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[16]:22 0.0001440257 +17 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chany_bottom_in[2]:8 0.0004735752 +18 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chany_bottom_in[2]:13 1.674614e-05 +19 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[2]:7 0.0004735752 +20 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chany_bottom_in[2]:14 1.674614e-05 + +*RES +0 mux_right_track_2\/mux_l3_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 9.51087e-05 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.006890625 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00341 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.005907116 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00341 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.006654018 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001985533 //LENGTH 14.640 LUMPCC 0.0004908745 DR + +*CONN +*I mux_right_track_24\/mux_l2_in_0_:X O *L 0 *C 106.545 46.920 +*I mux_right_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 115.460 41.820 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 115.460 41.820 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 115.460 41.865 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 115.460 46.875 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 115.415 46.920 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 106.583 46.920 + +*CAP +0 mux_right_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.295996e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002102458 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002102458 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0005196037 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005196037 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[6]:17 0.0001386741 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[6]:18 0.0001386741 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.0001067632 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.0001067632 + +*RES +0 mux_right_track_24\/mux_l2_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.007886161 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.004473214 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_24\/mux_l3_in_0_:A1 0.152 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001122114 //LENGTH 9.180 LUMPCC 9.357454e-05 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_0_:X O *L 0 *C 74.235 42.500 +*I mux_left_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 70.745 47.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 70.782 47.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.175 47.260 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.220 47.215 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.220 42.545 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 72.265 42.500 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 74.198 42.500 + +*CAP +0 mux_left_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001215321 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001215321 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000242897 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000242897 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001488407 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001488407 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 prog_clk[0]:280 5.164678e-06 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:279 5.164678e-06 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:275 2.535544e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:279 6.186211e-06 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:280 1.008094e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:278 6.186211e-06 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:279 2.535544e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:281 1.008094e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243304 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004169643 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002124504 //LENGTH 20.135 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_1_:X O *L 0 *C 61.815 72.420 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.250 88.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.288 88.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 61.135 88.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 61.180 88.015 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 61.180 72.465 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 61.225 72.420 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 61.778 72.420 + +*CAP +0 mux_left_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001944078 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001944078 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0007868485 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0007868485 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.999602e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.999602e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002542411 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01388393 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003133097 //LENGTH 26.340 LUMPCC 0.001391746 DR + +*CONN +*I mux_left_track_25\/mux_l3_in_0_:X O *L 0 *C 51.695 82.960 +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 27.850 82.820 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 27.888 82.913 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 45.955 82.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 46.000 83.005 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 46.000 83.640 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 47.840 83.640 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 47.840 83.005 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 47.885 82.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 51.658 82.960 + +*CAP +0 mux_left_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0005520219 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0005520219 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.629144e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001314784 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001348656 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.967861e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001364963 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001364963 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 chanx_right_in[9]:25 6.53778e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chanx_right_in[9]:24 6.53778e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_right_in[9]:25 0.0002279138 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_right_in[9]:24 0.0002279138 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[9]:24 1.407439e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[9]:25 1.407439e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 chanx_right_in[18]:8 6.847346e-05 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chanx_right_in[18]:7 6.847346e-05 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_right_in[18]:8 0.0003200336 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_right_in[18]:7 0.0003200336 + +*RES +0 mux_left_track_25\/mux_l3_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.003368304 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0005669643 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0161317 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0005669643 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001642857 + +*END + +*D_NET mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009616944 //LENGTH 5.975 LUMPCC 0.0003138845 DR + +*CONN +*I mux_bottom_track_21\/mux_l1_in_0_:X O *L 0 *C 82.625 25.160 +*I mux_bottom_track_21\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.200 23.460 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.163 23.460 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.640 23.460 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 84.640 23.120 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 82.845 23.120 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 82.800 23.165 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 82.800 25.115 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 82.800 25.160 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 82.625 25.160 + +*CAP +0 mux_bottom_track_21\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_21\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.528362e-05 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.313965e-05 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000110906 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.304996e-05 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.515334e-05 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.515334e-05 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 6.344356e-05 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.968045e-05 +10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[3]:2 2.777003e-05 +11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[3]:4 5.269242e-05 +12 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[3]:5 5.269242e-05 +13 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[3]:3 2.777003e-05 +14 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.782421e-06 +15 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.369739e-05 +16 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.369739e-05 +17 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.782421e-06 + +*RES +0 mux_bottom_track_21\/mux_l1_in_0_:X mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_21\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001602679 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001741072 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.51087e-05 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004665179 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005610907 //LENGTH 3.400 LUMPCC 0.0002491947 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_1_:X O *L 0 *C 37.545 20.740 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 40.655 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 40.617 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.583 20.740 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000154948 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000154948 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 bottom_left_grid_pin_38_[0]:16 0.0001245973 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 bottom_left_grid_pin_38_[0]:17 0.0001245973 + +*RES +0 mux_bottom_track_1\/mux_l1_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002709822 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006094791 //LENGTH 3.635 LUMPCC 0.0002096549 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_2_:X O *L 0 *C 15.925 41.480 +*I mux_bottom_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 16.660 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 16.623 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 15.685 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 15.640 39.825 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 15.640 41.435 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 15.640 41.480 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 15.925 41.480 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.192416e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.192416e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.086131e-05 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.086131e-05 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.650978e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.574346e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:10 4.009085e-06 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:11 4.731477e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:8 4.009085e-06 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:10 4.731477e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 2.179763e-06 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 2.179763e-06 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.132385e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.132385e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_2_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008370536 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00156493 //LENGTH 12.485 LUMPCC 0.0003625728 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 31.105 49.980 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.500 41.820 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.462 41.820 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 32.245 41.820 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 32.200 41.865 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 32.200 49.935 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 32.155 49.980 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 31.143 49.980 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001567099 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001567099 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003586798 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003586798 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.478905e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.478905e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:16 1.792677e-06 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:17 1.792677e-06 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:18 7.199859e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:22 6.858973e-08 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:20 2.225215e-06 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:19 7.199859e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:26 6.858973e-08 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_2_sram[0]:21 2.225215e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.008603e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.468864e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.008603e-05 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.468864e-05 +20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.042664e-05 +21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.042664e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007205357 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001979911 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009282667 //LENGTH 6.230 LUMPCC 0.0002181174 DR + +*CONN +*I mux_bottom_track_7\/mux_l2_in_1_:X O *L 0 *C 20.065 46.920 +*I mux_bottom_track_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 22.715 44.540 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 22.678 44.540 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 19.825 44.540 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 19.780 44.585 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 19.780 46.875 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 19.780 46.920 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 20.065 46.920 + +*CAP +0 mux_bottom_track_7\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001262468 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001262468 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001606577 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001606577 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.653896e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.780137e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chanx_right_in[6]:9 0.0001090587 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chanx_right_in[6]:8 0.0001090587 + +*RES +0 mux_bottom_track_7\/mux_l2_in_1_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_7\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002546875 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002044643 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001356781 //LENGTH 9.375 LUMPCC 0.0004665028 DR + +*CONN +*I mux_bottom_track_11\/mux_l2_in_0_:X O *L 0 *C 34.325 64.600 +*I mux_bottom_track_11\/mux_l3_in_0_:A1 I *L 0.00198 *C 40.580 66.980 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 40.543 66.980 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 34.545 66.980 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 34.500 66.935 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 34.500 64.645 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 34.500 64.600 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 34.325 64.600 + +*CAP +0 mux_bottom_track_11\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_11\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003201732 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003201732 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.377366e-05 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.377366e-05 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.089716e-05 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.94877e-05 +8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_right_in[9]:22 6.773136e-05 +9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_right_in[9]:8 6.773136e-05 +10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size4_1_sram[1]:10 6.773136e-05 +11 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_1_sram[1]:9 6.773136e-05 +12 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 optlc_net_168:19 9.77887e-05 +13 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 optlc_net_168:34 9.77887e-05 + +*RES +0 mux_bottom_track_11\/mux_l2_in_0_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_11\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.005354912 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0] 0.01139716 //LENGTH 69.710 LUMPCC 0.006549043 DR + +*CONN +*I mux_left_track_33\/mux_l3_in_0_:X O *L 0 *C 61.355 76.840 +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 11.220 58.675 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 11.258 58.770 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 12.835 58.820 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 12.880 58.865 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 12.880 74.062 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 12.888 74.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 60.253 74.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 60.260 74.178 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 60.260 76.795 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 60.305 76.840 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 61.318 76.840 + +*CAP +0 mux_left_track_33\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001032171 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001032171 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00072811 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00072811 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001344984 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.001344984 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001585582 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001585582 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 8.818613e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 8.818613e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[12]:13 5.682372e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_right_in[12]:28 0.0002589988 +14 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[12]:28 5.682372e-05 +15 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[12]:29 0.0002589988 +16 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[13] 0.002381228 +17 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[13]:35 0.0002886391 +18 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[13]:26 0.0002886391 +19 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_left_in[13]:35 0.002381228 +20 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:332 0.0001050368 +21 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:337 0.0001024079 +22 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:348 9.406261e-06 +23 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:337 0.0001050368 +24 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:338 0.0001024079 +25 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:347 9.406261e-06 +26 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 BUF_net_76:8 7.198046e-05 +27 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 BUF_net_76:7 7.198046e-05 + +*RES +0 mux_left_track_33\/mux_l3_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001408482 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0135692 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.00341 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.007420516 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.002337054 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0009040179 + +*END + +*D_NET mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00206035 //LENGTH 15.460 LUMPCC 0.0007705693 DR + +*CONN +*I mux_bottom_track_37\/mux_l1_in_0_:X O *L 0 *C 80.675 14.620 +*I mux_bottom_track_37\/mux_l2_in_0_:A1 I *L 0.00198 *C 79.120 3.740 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 79.120 3.740 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 79.120 3.785 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 79.120 11.560 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 78.200 11.560 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.200 14.235 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 78.245 14.280 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 78.660 14.280 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 78.660 14.620 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 80.638 14.620 + +*CAP +0 mux_bottom_track_37\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_37\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.68719e-05 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003223394 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003571157 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001459633 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000111187 +7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.245404e-05 +8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 6.808899e-05 +9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001146975 +10 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 8.906252e-05 +11 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[19] 0.0001887016 +12 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[19]:20 0.0001887016 +13 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size2_5_sram[0]:3 3.485398e-05 +14 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 5.008088e-06 +15 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_5_sram[0]:9 5.819276e-07 +16 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_5_sram[0]:8 2.291069e-05 +17 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size2_5_sram[0]:4 3.485398e-05 +18 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_5_sram[0]:6 2.002793e-05 +19 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_5_sram[0]:8 5.819276e-07 +20 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_5_sram[0]:9 5.008088e-06 +21 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_5_sram[0]:7 2.002793e-05 +22 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_5_sram[0]:9 2.291069e-05 +23 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 optlc_net_166:6 2.92423e-05 +24 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_166:7 2.476531e-06 +25 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_166:26 7.711217e-05 +26 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_166:25 4.369434e-06 +27 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 optlc_net_166:6 2.476531e-06 +28 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 optlc_net_166:7 2.92423e-05 +29 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_166:25 7.711217e-05 +30 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_166:26 4.369434e-06 + +*RES +0 mux_bottom_track_37\/mux_l1_in_0_:X mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.001765625 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002388393 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_37\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003705357 +7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003035715 +8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0008214285 +9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006941964 + +*END + +*D_NET chanx_left_out[17] 0.001470015 //LENGTH 11.690 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 8.740 90.440 +*P chanx_left_out[17] O *L 0.7423 *C 1.305 91.120 +*N chanx_left_out[17]:2 *C 10.113 91.120 +*N chanx_left_out[17]:3 *C 10.120 91.062 +*N chanx_left_out[17]:4 *C 10.120 90.485 +*N chanx_left_out[17]:5 *C 10.075 90.440 +*N chanx_left_out[17]:6 *C 8.777 90.440 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 chanx_left_out[17] 0.0005445077 +2 chanx_left_out[17]:2 0.0005445077 +3 chanx_left_out[17]:3 5.410743e-05 +4 chanx_left_out[17]:4 5.410743e-05 +5 chanx_left_out[17]:5 0.0001358924 +6 chanx_left_out[17]:6 0.0001358924 + +*RES +0 ropt_mt_inst_797:X chanx_left_out[17]:6 0.152 +1 chanx_left_out[17]:6 chanx_left_out[17]:5 0.001158482 +2 chanx_left_out[17]:5 chanx_left_out[17]:4 0.0045 +3 chanx_left_out[17]:4 chanx_left_out[17]:3 0.000515625 +4 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +5 chanx_left_out[17]:2 chanx_left_out[17] 0.001379842 + +*END + +*D_NET chanx_right_out[5] 0.0008546303 //LENGTH 6.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 136.160 96.560 +*P chanx_right_out[5] O *L 0.7423 *C 140.375 95.200 +*N chanx_right_out[5]:2 *C 136.168 95.200 +*N chanx_right_out[5]:3 *C 136.160 95.258 +*N chanx_right_out[5]:4 *C 136.160 96.515 +*N chanx_right_out[5]:5 *C 136.160 96.560 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 chanx_right_out[5] 0.0003191049 +2 chanx_right_out[5]:2 0.0003191049 +3 chanx_right_out[5]:3 9.253e-05 +4 chanx_right_out[5]:4 9.253e-05 +5 chanx_right_out[5]:5 3.036052e-05 + +*RES +0 ropt_mt_inst_804:X chanx_right_out[5]:5 0.152 +1 chanx_right_out[5]:3 chanx_right_out[5]:2 0.00341 +2 chanx_right_out[5]:2 chanx_right_out[5] 0.000659175 +3 chanx_right_out[5]:5 chanx_right_out[5]:4 0.0045 +4 chanx_right_out[5]:4 chanx_right_out[5]:3 0.001122768 + +*END + +*D_NET ropt_net_211 0.001094497 //LENGTH 8.635 LUMPCC 0.0001781976 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 7.095 82.280 +*I ropt_mt_inst_829:A I *L 0.001767 *C 3.220 80.240 +*N ropt_net_211:2 *C 3.258 80.240 +*N ropt_net_211:3 *C 4.555 80.240 +*N ropt_net_211:4 *C 4.600 80.195 +*N ropt_net_211:5 *C 4.600 79.605 +*N ropt_net_211:6 *C 4.645 79.560 +*N ropt_net_211:7 *C 6.855 79.560 +*N ropt_net_211:8 *C 6.900 79.605 +*N ropt_net_211:9 *C 6.900 82.235 +*N ropt_net_211:10 *C 6.900 82.280 +*N ropt_net_211:11 *C 7.095 82.280 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 ropt_mt_inst_829:A 1e-06 +2 ropt_net_211:2 5.66093e-05 +3 ropt_net_211:3 5.66093e-05 +4 ropt_net_211:4 4.910227e-05 +5 ropt_net_211:5 4.910227e-05 +6 ropt_net_211:6 0.0001331692 +7 ropt_net_211:7 0.0001331692 +8 ropt_net_211:8 0.0001592021 +9 ropt_net_211:9 0.0001592021 +10 ropt_net_211:10 5.732875e-05 +11 ropt_net_211:11 6.080442e-05 +12 ropt_net_211:2 chanx_left_out[8]:5 6.370984e-05 +13 ropt_net_211:3 chanx_left_out[8]:6 6.370984e-05 +14 ropt_net_211:6 chanx_left_out[8]:5 2.538895e-05 +15 ropt_net_211:7 chanx_left_out[8]:6 2.538895e-05 + +*RES +0 ropt_mt_inst_814:X ropt_net_211:11 0.152 +1 ropt_net_211:2 ropt_mt_inst_829:A 0.152 +2 ropt_net_211:3 ropt_net_211:2 0.001158482 +3 ropt_net_211:4 ropt_net_211:3 0.0045 +4 ropt_net_211:6 ropt_net_211:5 0.0045 +5 ropt_net_211:5 ropt_net_211:4 0.0005267857 +6 ropt_net_211:7 ropt_net_211:6 0.001973214 +7 ropt_net_211:8 ropt_net_211:7 0.0045 +8 ropt_net_211:10 ropt_net_211:9 0.0045 +9 ropt_net_211:9 ropt_net_211:8 0.002348214 +10 ropt_net_211:11 ropt_net_211:10 0.0001059783 + +*END + +*D_NET mux_bottom_track_9/BUF_net_72 0.00170265 //LENGTH 13.165 LUMPCC 0.0002506767 DR + +*CONN +*I mux_bottom_track_9\/BUFT_RR_72:X O *L 0 *C 87.400 11.560 +*I mux_bottom_track_9\/BUFT_P_135:A I *L 0.001766 *C 92.460 4.080 +*N mux_bottom_track_9/BUF_net_72:2 *C 92.460 4.080 +*N mux_bottom_track_9/BUF_net_72:3 *C 92.460 4.125 +*N mux_bottom_track_9/BUF_net_72:4 *C 92.460 11.515 +*N mux_bottom_track_9/BUF_net_72:5 *C 92.415 11.560 +*N mux_bottom_track_9/BUF_net_72:6 *C 87.438 11.560 + +*CAP +0 mux_bottom_track_9\/BUFT_RR_72:X 1e-06 +1 mux_bottom_track_9\/BUFT_P_135:A 1e-06 +2 mux_bottom_track_9/BUF_net_72:2 3.122727e-05 +3 mux_bottom_track_9/BUF_net_72:3 0.000349187 +4 mux_bottom_track_9/BUF_net_72:4 0.000349187 +5 mux_bottom_track_9/BUF_net_72:5 0.0003601859 +6 mux_bottom_track_9/BUF_net_72:6 0.0003601859 +7 mux_bottom_track_9/BUF_net_72:6 mux_tree_tapbuf_size2_0_sram[0]:5 1.673402e-07 +8 mux_bottom_track_9/BUF_net_72:5 mux_tree_tapbuf_size2_0_sram[0]:10 1.673402e-07 +9 mux_bottom_track_9/BUF_net_72:4 mux_tree_tapbuf_size2_0_sram[0]:9 7.174787e-05 +10 mux_bottom_track_9/BUF_net_72:3 mux_tree_tapbuf_size2_0_sram[0]:8 7.174787e-05 +11 mux_bottom_track_9/BUF_net_72:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.342313e-05 +12 mux_bottom_track_9/BUF_net_72:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.342313e-05 + +*RES +0 mux_bottom_track_9\/BUFT_RR_72:X mux_bottom_track_9/BUF_net_72:6 0.152 +1 mux_bottom_track_9/BUF_net_72:6 mux_bottom_track_9/BUF_net_72:5 0.004444197 +2 mux_bottom_track_9/BUF_net_72:5 mux_bottom_track_9/BUF_net_72:4 0.0045 +3 mux_bottom_track_9/BUF_net_72:4 mux_bottom_track_9/BUF_net_72:3 0.006598215 +4 mux_bottom_track_9/BUF_net_72:2 mux_bottom_track_9\/BUFT_P_135:A 0.152 +5 mux_bottom_track_9/BUF_net_72:3 mux_bottom_track_9/BUF_net_72:2 0.0045 + +*END + +*D_NET chanx_left_out[10] 0.002430827 //LENGTH 12.325 LUMPCC 0.001152674 DR + +*CONN +*I ropt_mt_inst_835:X O *L 0 *C 11.695 98.940 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 97.920 +*N chanx_left_out[10]:2 *C 1.840 97.920 +*N chanx_left_out[10]:3 *C 1.840 98.600 +*N chanx_left_out[10]:4 *C 11.492 98.600 +*N chanx_left_out[10]:5 *C 11.500 98.600 +*N chanx_left_out[10]:6 *C 11.500 98.940 +*N chanx_left_out[10]:7 *C 11.500 98.940 +*N chanx_left_out[10]:8 *C 11.695 98.940 + +*CAP +0 ropt_mt_inst_835:X 1e-06 +1 chanx_left_out[10] 5.230261e-05 +2 chanx_left_out[10]:2 9.593332e-05 +3 chanx_left_out[10]:3 0.0004903381 +4 chanx_left_out[10]:4 0.0004467074 +5 chanx_left_out[10]:5 4.372904e-05 +6 chanx_left_out[10]:6 4.074676e-05 +7 chanx_left_out[10]:7 5.514846e-05 +8 chanx_left_out[10]:8 5.224707e-05 +9 chanx_left_out[10] chanx_left_in[9] 9.726927e-06 +10 chanx_left_out[10]:4 chanx_left_in[9]:28 0.0005666103 +11 chanx_left_out[10]:2 chanx_left_in[9]:28 9.726927e-06 +12 chanx_left_out[10]:3 chanx_left_in[9] 0.0005666103 + +*RES +0 ropt_mt_inst_835:X chanx_left_out[10]:8 0.152 +1 chanx_left_out[10]:8 chanx_left_out[10]:7 0.0001059783 +2 chanx_left_out[10]:7 chanx_left_out[10]:6 0.0045 +3 chanx_left_out[10]:6 chanx_left_out[10]:5 0.0001634615 +4 chanx_left_out[10]:5 chanx_left_out[10]:4 0.00341 +5 chanx_left_out[10]:4 chanx_left_out[10]:3 0.001512225 +6 chanx_left_out[10]:2 chanx_left_out[10] 9.556666e-05 +7 chanx_left_out[10]:3 chanx_left_out[10]:2 0.0001065333 + +*END + +*D_NET chanx_right_in[8] 0.02261028 //LENGTH 162.520 LUMPCC 0.008618235 DR + +*CONN +*P chanx_right_in[8] I *L 0.29796 *C 140.450 77.520 +*I mux_left_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.640 61.540 +*I FTB_5__4:A I *L 0.001776 *C 11.500 66.640 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 27.505 61.540 +*N chanx_right_in[8]:4 *C 27.505 61.540 +*N chanx_right_in[8]:5 *C 27.600 61.585 +*N chanx_right_in[8]:6 *C 11.463 66.640 +*N chanx_right_in[8]:7 *C 9.245 66.640 +*N chanx_right_in[8]:8 *C 9.200 66.640 +*N chanx_right_in[8]:9 *C 9.207 66.640 +*N chanx_right_in[8]:10 *C 22.060 66.640 +*N chanx_right_in[8]:11 *C 22.080 66.633 +*N chanx_right_in[8]:12 *C 22.080 62.568 +*N chanx_right_in[8]:13 *C 22.100 62.560 +*N chanx_right_in[8]:14 *C 27.593 62.560 +*N chanx_right_in[8]:15 *C 27.600 62.560 +*N chanx_right_in[8]:16 *C 27.600 64.543 +*N chanx_right_in[8]:17 *C 27.608 64.600 +*N chanx_right_in[8]:18 *C 61.172 64.600 +*N chanx_right_in[8]:19 *C 61.180 64.543 +*N chanx_right_in[8]:20 *C 61.640 61.540 +*N chanx_right_in[8]:21 *C 61.640 61.540 +*N chanx_right_in[8]:22 *C 61.180 61.540 +*N chanx_right_in[8]:23 *C 61.180 62.560 +*N chanx_right_in[8]:24 *C 61.188 62.560 +*N chanx_right_in[8]:25 *C 65.300 62.560 +*N chanx_right_in[8]:26 *C 65.320 62.568 +*N chanx_right_in[8]:27 *C 65.320 77.513 +*N chanx_right_in[8]:28 *C 65.340 77.520 +*N chanx_right_in[8]:29 *C 115.130 77.520 + +*CAP +0 chanx_right_in[8] 0.001227615 +1 mux_left_track_17\/mux_l1_in_0_:A1 1e-06 +2 FTB_5__4:A 1e-06 +3 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[8]:4 2.837867e-05 +5 chanx_right_in[8]:5 7.526933e-05 +6 chanx_right_in[8]:6 0.0001388876 +7 chanx_right_in[8]:7 0.0001388876 +8 chanx_right_in[8]:8 3.443769e-05 +9 chanx_right_in[8]:9 0.0007294709 +10 chanx_right_in[8]:10 0.0007294709 +11 chanx_right_in[8]:11 0.0002705405 +12 chanx_right_in[8]:12 0.0002705405 +13 chanx_right_in[8]:13 0.0002140308 +14 chanx_right_in[8]:14 0.0002140308 +15 chanx_right_in[8]:15 0.0002555915 +16 chanx_right_in[8]:16 0.0001429181 +17 chanx_right_in[8]:17 0.0009023355 +18 chanx_right_in[8]:18 0.0009023355 +19 chanx_right_in[8]:19 0.0001229203 +20 chanx_right_in[8]:20 3.206605e-05 +21 chanx_right_in[8]:21 6.915152e-05 +22 chanx_right_in[8]:22 0.0001049618 +23 chanx_right_in[8]:23 0.0002308291 +24 chanx_right_in[8]:24 9.582023e-05 +25 chanx_right_in[8]:25 9.582023e-05 +26 chanx_right_in[8]:26 0.0008837396 +27 chanx_right_in[8]:27 0.0008837396 +28 chanx_right_in[8]:28 0.001983819 +29 chanx_right_in[8]:29 0.003211434 +30 chanx_right_in[8]:17 chanx_right_in[17]:13 0.001420833 +31 chanx_right_in[8]:18 chanx_right_in[17]:14 0.001420833 +32 chanx_right_in[8]:23 chanx_right_in[17]:19 2.374218e-06 +33 chanx_right_in[8]:24 chanx_right_in[17]:20 0.0001945173 +34 chanx_right_in[8]:25 chanx_right_in[17]:21 0.0001945173 +35 chanx_right_in[8]:14 chanx_right_in[17]:14 0.0001452104 +36 chanx_right_in[8]:13 chanx_right_in[17]:13 0.0001452104 +37 chanx_right_in[8]:10 chanx_right_in[17]:12 9.825391e-05 +38 chanx_right_in[8]:9 chanx_right_in[17]:11 9.825391e-05 +39 chanx_right_in[8]:22 chanx_right_in[17]:6 2.374218e-06 +40 chanx_right_in[8]:17 chanx_left_in[8]:21 0.0007385541 +41 chanx_right_in[8]:18 chanx_left_in[8]:20 0.0007385541 +42 chanx_right_in[8]:14 chanx_left_in[8]:20 5.180407e-07 +43 chanx_right_in[8]:13 chanx_left_in[8]:21 5.180407e-07 +44 chanx_right_in[8]:10 chanx_left_in[8]:20 0.000356677 +45 chanx_right_in[8]:9 chanx_left_in[8]:21 0.000356677 +46 chanx_right_in[8]:17 chanx_left_in[9]:25 6.669457e-06 +47 chanx_right_in[8]:17 chanx_left_in[9]:24 1.506806e-05 +48 chanx_right_in[8]:17 chanx_left_in[9]:20 0.0001814364 +49 chanx_right_in[8]:18 chanx_left_in[9]:24 6.669457e-06 +50 chanx_right_in[8]:18 chanx_left_in[9]:23 1.506806e-05 +51 chanx_right_in[8]:18 chanx_left_in[9]:19 0.0001814364 +52 chanx_right_in[8]:24 chanx_left_in[9]:20 0.0002464058 +53 chanx_right_in[8]:25 chanx_left_in[9]:19 0.0002464058 +54 chanx_right_in[8] chanx_left_in[13]:16 6.24567e-05 +55 chanx_right_in[8]:28 chanx_left_in[13]:35 8.17943e-05 +56 chanx_right_in[8]:28 chanx_left_in[13]:26 0.0001098088 +57 chanx_right_in[8]:28 chanx_left_in[13]:17 0.0003567471 +58 chanx_right_in[8]:29 chanx_left_in[13]:26 8.17943e-05 +59 chanx_right_in[8]:29 chanx_left_in[13]:16 0.0003567471 +60 chanx_right_in[8]:29 chanx_left_in[13]:17 6.24567e-05 +61 chanx_right_in[8]:29 chanx_left_in[13]:20 0.0001098088 +62 chanx_right_in[8] chanx_left_in[17]:17 6.090011e-05 +63 chanx_right_in[8]:28 chanx_left_in[17]:18 0.0002308935 +64 chanx_right_in[8]:29 chanx_left_in[17]:18 6.090011e-05 +65 chanx_right_in[8]:29 chanx_left_in[17]:17 0.0002308935 + +*RES +0 chanx_right_in[8] chanx_right_in[8]:29 0.003966799 +1 chanx_right_in[8]:16 chanx_right_in[8]:15 0.001770089 +2 chanx_right_in[8]:17 chanx_right_in[8]:16 0.00341 +3 chanx_right_in[8]:19 chanx_right_in[8]:18 0.00341 +4 chanx_right_in[8]:18 chanx_right_in[8]:17 0.005258516 +5 chanx_right_in[8]:23 chanx_right_in[8]:22 0.0009107143 +6 chanx_right_in[8]:23 chanx_right_in[8]:19 0.001770089 +7 chanx_right_in[8]:24 chanx_right_in[8]:23 0.00341 +8 chanx_right_in[8]:25 chanx_right_in[8]:24 0.0006442916 +9 chanx_right_in[8]:26 chanx_right_in[8]:25 0.00341 +10 chanx_right_in[8]:28 chanx_right_in[8]:27 0.00341 +11 chanx_right_in[8]:27 chanx_right_in[8]:26 0.002341383 +12 chanx_right_in[8]:4 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +13 chanx_right_in[8]:5 chanx_right_in[8]:4 0.0045 +14 chanx_right_in[8]:20 mux_left_track_17\/mux_l1_in_0_:A1 0.152 +15 chanx_right_in[8]:21 chanx_right_in[8]:20 0.0045 +16 chanx_right_in[8]:15 chanx_right_in[8]:14 0.00341 +17 chanx_right_in[8]:15 chanx_right_in[8]:5 0.0008705358 +18 chanx_right_in[8]:14 chanx_right_in[8]:13 0.0008604917 +19 chanx_right_in[8]:13 chanx_right_in[8]:12 0.00341 +20 chanx_right_in[8]:12 chanx_right_in[8]:11 0.00063685 +21 chanx_right_in[8]:10 chanx_right_in[8]:9 0.002013558 +22 chanx_right_in[8]:11 chanx_right_in[8]:10 0.00341 +23 chanx_right_in[8]:8 chanx_right_in[8]:7 0.0045 +24 chanx_right_in[8]:9 chanx_right_in[8]:8 0.00341 +25 chanx_right_in[8]:7 chanx_right_in[8]:6 0.001979911 +26 chanx_right_in[8]:6 FTB_5__4:A 0.152 +27 chanx_right_in[8]:22 chanx_right_in[8]:21 0.0004107143 +28 chanx_right_in[8]:29 chanx_right_in[8]:28 0.007800432 + +*END + +*D_NET chanx_left_in[6] 0.02885881 //LENGTH 201.470 LUMPCC 0.008178284 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 31.280 +*I mux_right_track_8\/mux_l1_in_2_:A1 I *L 0.00198 *C 115.825 58.140 +*I ropt_mt_inst_810:A I *L 0.001767 *C 130.180 93.840 +*I mux_bottom_track_7\/mux_l1_in_2_:A0 I *L 0.001631 *C 19.150 42.500 +*N chanx_left_in[6]:4 *C 19.150 42.500 +*N chanx_left_in[6]:5 *C 130.143 93.840 +*N chanx_left_in[6]:6 *C 128.385 93.840 +*N chanx_left_in[6]:7 *C 128.340 93.795 +*N chanx_left_in[6]:8 *C 128.340 58.140 +*N chanx_left_in[6]:9 *C 127.880 58.140 +*N chanx_left_in[6]:10 *C 127.835 58.140 +*N chanx_left_in[6]:11 *C 115.863 58.140 +*N chanx_left_in[6]:12 *C 116.380 58.140 +*N chanx_left_in[6]:13 *C 116.380 58.095 +*N chanx_left_in[6]:14 *C 116.380 57.178 +*N chanx_left_in[6]:15 *C 116.373 57.120 +*N chanx_left_in[6]:16 *C 115.008 57.120 +*N chanx_left_in[6]:17 *C 115.000 57.062 +*N chanx_left_in[6]:18 *C 115.000 41.538 +*N chanx_left_in[6]:19 *C 114.993 41.480 +*N chanx_left_in[6]:20 *C 79.120 41.480 +*N chanx_left_in[6]:21 *C 79.120 42.160 +*N chanx_left_in[6]:22 *C 69.460 42.160 +*N chanx_left_in[6]:23 *C 69.460 41.480 +*N chanx_left_in[6]:24 *C 33.128 41.480 +*N chanx_left_in[6]:25 *C 33.120 41.480 +*N chanx_left_in[6]:26 *C 33.075 41.480 +*N chanx_left_in[6]:27 *C 19.365 41.480 +*N chanx_left_in[6]:28 *C 19.320 41.525 +*N chanx_left_in[6]:29 *C 19.320 42.455 +*N chanx_left_in[6]:30 *C 19.320 42.500 +*N chanx_left_in[6]:31 *C 19.320 42.840 +*N chanx_left_in[6]:32 *C 9.705 42.840 +*N chanx_left_in[6]:33 *C 9.660 42.795 +*N chanx_left_in[6]:34 *C 9.660 31.338 +*N chanx_left_in[6]:35 *C 9.652 31.280 + +*CAP +0 chanx_left_in[6] 0.0005389595 +1 mux_right_track_8\/mux_l1_in_2_:A1 1e-06 +2 ropt_mt_inst_810:A 1e-06 +3 mux_bottom_track_7\/mux_l1_in_2_:A0 1e-06 +4 chanx_left_in[6]:4 3.668998e-05 +5 chanx_left_in[6]:5 0.000148978 +6 chanx_left_in[6]:6 0.000148978 +7 chanx_left_in[6]:7 0.00157098 +8 chanx_left_in[6]:8 0.001603449 +9 chanx_left_in[6]:9 6.315592e-05 +10 chanx_left_in[6]:10 0.00069821 +11 chanx_left_in[6]:11 5.040628e-05 +12 chanx_left_in[6]:12 0.0007806441 +13 chanx_left_in[6]:13 7.430174e-05 +14 chanx_left_in[6]:14 7.430174e-05 +15 chanx_left_in[6]:15 0.0001566333 +16 chanx_left_in[6]:16 0.0001566333 +17 chanx_left_in[6]:17 0.0006516923 +18 chanx_left_in[6]:18 0.0006516923 +19 chanx_left_in[6]:19 0.00174472 +20 chanx_left_in[6]:20 0.00181098 +21 chanx_left_in[6]:21 0.000879035 +22 chanx_left_in[6]:22 0.0008799714 +23 chanx_left_in[6]:23 0.001362076 +24 chanx_left_in[6]:24 0.001294881 +25 chanx_left_in[6]:25 3.923879e-05 +26 chanx_left_in[6]:26 0.0009639874 +27 chanx_left_in[6]:27 0.0009639874 +28 chanx_left_in[6]:28 7.636956e-05 +29 chanx_left_in[6]:29 7.636956e-05 +30 chanx_left_in[6]:30 6.12017e-05 +31 chanx_left_in[6]:31 0.0007360913 +32 chanx_left_in[6]:32 0.0007161103 +33 chanx_left_in[6]:33 0.000563921 +34 chanx_left_in[6]:34 0.000563921 +35 chanx_left_in[6]:35 0.0005389595 +36 chanx_left_in[6]:33 chanx_right_in[14]:7 8.366202e-07 +37 chanx_left_in[6]:34 chanx_right_in[14]:6 8.366202e-07 +38 chanx_left_in[6]:24 chanx_right_in[14]:20 3.020548e-05 +39 chanx_left_in[6]:19 chanx_right_in[14] 0.0003525692 +40 chanx_left_in[6]:19 chanx_right_in[14]:21 1.137787e-05 +41 chanx_left_in[6]:23 chanx_right_in[14]:21 3.020548e-05 +42 chanx_left_in[6]:22 chanx_right_in[14]:20 1.950226e-06 +43 chanx_left_in[6]:21 chanx_right_in[14]:21 1.950226e-06 +44 chanx_left_in[6]:20 chanx_right_in[14]:20 1.137787e-05 +45 chanx_left_in[6]:20 chanx_right_in[14]:22 0.0003525692 +46 chanx_left_in[6]:24 chanx_left_in[18]:22 0.0003107119 +47 chanx_left_in[6]:24 chanx_left_in[18]:21 0.000275008 +48 chanx_left_in[6]:19 chanx_left_in[18]:20 0.0004930631 +49 chanx_left_in[6]:23 chanx_left_in[18]:20 0.000275008 +50 chanx_left_in[6]:23 chanx_left_in[18]:21 0.0003107119 +51 chanx_left_in[6]:22 chanx_left_in[18]:21 6.720737e-05 +52 chanx_left_in[6]:21 chanx_left_in[18]:20 6.720737e-05 +53 chanx_left_in[6]:20 chanx_left_in[18]:21 0.0004930631 +54 chanx_left_in[6]:7 chanx_right_out[8]:3 0.0002599902 +55 chanx_left_in[6]:8 chanx_right_out[8]:4 0.0002599902 +56 chanx_left_in[6]:18 mux_tree_tapbuf_size6_2_sram[2]:10 0.0001541875 +57 chanx_left_in[6]:18 mux_tree_tapbuf_size6_2_sram[2]:5 2.228173e-05 +58 chanx_left_in[6]:17 mux_tree_tapbuf_size6_2_sram[2]:9 0.0001541875 +59 chanx_left_in[6]:17 mux_tree_tapbuf_size6_2_sram[2]:6 2.228173e-05 +60 chanx_left_in[6]:24 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003192367 +61 chanx_left_in[6]:23 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003192367 +62 chanx_left_in[6]:18 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001386741 +63 chanx_left_in[6]:17 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001386741 +64 chanx_left_in[6]:33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.205117e-05 +65 chanx_left_in[6]:34 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.205117e-05 +66 chanx_left_in[6]:24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001594886 +67 chanx_left_in[6]:23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.001594886 +68 chanx_left_in[6]:27 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.490511e-05 +69 chanx_left_in[6]:26 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.490511e-05 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:35 0.001319525 +1 chanx_left_in[6]:32 chanx_left_in[6]:31 0.008584822 +2 chanx_left_in[6]:33 chanx_left_in[6]:32 0.0045 +3 chanx_left_in[6]:34 chanx_left_in[6]:33 0.01022991 +4 chanx_left_in[6]:35 chanx_left_in[6]:34 0.00341 +5 chanx_left_in[6]:10 chanx_left_in[6]:9 0.0045 +6 chanx_left_in[6]:9 chanx_left_in[6]:8 0.0004107143 +7 chanx_left_in[6]:6 chanx_left_in[6]:5 0.001569197 +8 chanx_left_in[6]:7 chanx_left_in[6]:6 0.0045 +9 chanx_left_in[6]:5 ropt_mt_inst_810:A 0.152 +10 chanx_left_in[6]:11 mux_right_track_8\/mux_l1_in_2_:A1 0.152 +11 chanx_left_in[6]:30 chanx_left_in[6]:29 0.0045 +12 chanx_left_in[6]:30 chanx_left_in[6]:4 9.239131e-05 +13 chanx_left_in[6]:29 chanx_left_in[6]:28 0.0008303572 +14 chanx_left_in[6]:27 chanx_left_in[6]:26 0.01224107 +15 chanx_left_in[6]:28 chanx_left_in[6]:27 0.0045 +16 chanx_left_in[6]:26 chanx_left_in[6]:25 0.0045 +17 chanx_left_in[6]:25 chanx_left_in[6]:24 0.00341 +18 chanx_left_in[6]:24 chanx_left_in[6]:23 0.005692091 +19 chanx_left_in[6]:18 chanx_left_in[6]:17 0.01386161 +20 chanx_left_in[6]:19 chanx_left_in[6]:18 0.00341 +21 chanx_left_in[6]:17 chanx_left_in[6]:16 0.00341 +22 chanx_left_in[6]:16 chanx_left_in[6]:15 0.00021385 +23 chanx_left_in[6]:14 chanx_left_in[6]:13 0.0008191965 +24 chanx_left_in[6]:15 chanx_left_in[6]:14 0.00341 +25 chanx_left_in[6]:12 chanx_left_in[6]:11 0.0004620536 +26 chanx_left_in[6]:12 chanx_left_in[6]:10 0.01022768 +27 chanx_left_in[6]:13 chanx_left_in[6]:12 0.0045 +28 chanx_left_in[6]:4 mux_bottom_track_7\/mux_l1_in_2_:A0 0.152 +29 chanx_left_in[6]:31 chanx_left_in[6]:30 0.0003035715 +30 chanx_left_in[6]:8 chanx_left_in[6]:7 0.03183483 +31 chanx_left_in[6]:23 chanx_left_in[6]:22 0.0001065333 +32 chanx_left_in[6]:22 chanx_left_in[6]:21 0.0015134 +33 chanx_left_in[6]:21 chanx_left_in[6]:20 0.0001065333 +34 chanx_left_in[6]:20 chanx_left_in[6]:19 0.005620025 + +*END + +*D_NET chanx_left_in[8] 0.02708642 //LENGTH 174.700 LUMPCC 0.01174974 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.305 76.160 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 15.815 65.960 +*I mux_right_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 82.055 44.540 +*I ropt_mt_inst_813:A I *L 0.001767 *C 134.780 44.880 +*N chanx_left_in[8]:4 *C 134.780 44.880 +*N chanx_left_in[8]:5 *C 135.655 44.880 +*N chanx_left_in[8]:6 *C 135.700 44.925 +*N chanx_left_in[8]:7 *C 135.700 46.863 +*N chanx_left_in[8]:8 *C 135.692 46.920 +*N chanx_left_in[8]:9 *C 82.055 44.540 +*N chanx_left_in[8]:10 *C 82.340 44.540 +*N chanx_left_in[8]:11 *C 82.340 44.585 +*N chanx_left_in[8]:12 *C 82.340 46.240 +*N chanx_left_in[8]:13 *C 82.800 46.240 +*N chanx_left_in[8]:14 *C 82.800 46.863 +*N chanx_left_in[8]:15 *C 82.800 46.920 +*N chanx_left_in[8]:16 *C 78.220 46.920 +*N chanx_left_in[8]:17 *C 78.200 46.928 +*N chanx_left_in[8]:18 *C 78.200 65.953 +*N chanx_left_in[8]:19 *C 78.180 65.960 +*N chanx_left_in[8]:20 *C 65.935 65.960 +*N chanx_left_in[8]:21 *C 16.108 65.960 +*N chanx_left_in[8]:22 *C 15.815 65.960 +*N chanx_left_in[8]:23 *C 16.100 65.960 +*N chanx_left_in[8]:24 *C 16.100 65.960 +*N chanx_left_in[8]:25 *C 16.100 67.320 +*N chanx_left_in[8]:26 *C 15.640 67.320 +*N chanx_left_in[8]:27 *C 15.640 76.782 +*N chanx_left_in[8]:28 *C 15.633 76.840 +*N chanx_left_in[8]:29 *C 1.380 76.840 + +*CAP +0 chanx_left_in[8] 5.034261e-05 +1 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:A0 1e-06 +3 ropt_mt_inst_813:A 1e-06 +4 chanx_left_in[8]:4 9.056901e-05 +5 chanx_left_in[8]:5 6.242509e-05 +6 chanx_left_in[8]:6 0.000135562 +7 chanx_left_in[8]:7 0.000135562 +8 chanx_left_in[8]:8 0.002008992 +9 chanx_left_in[8]:9 4.93111e-05 +10 chanx_left_in[8]:10 5.384389e-05 +11 chanx_left_in[8]:11 0.0001089108 +12 chanx_left_in[8]:12 0.0001418162 +13 chanx_left_in[8]:13 8.872271e-05 +14 chanx_left_in[8]:14 5.58173e-05 +15 chanx_left_in[8]:15 0.002302849 +16 chanx_left_in[8]:16 0.0002938565 +17 chanx_left_in[8]:17 0.0005540327 +18 chanx_left_in[8]:18 0.0005540327 +19 chanx_left_in[8]:19 0.0006692159 +20 chanx_left_in[8]:20 0.002722086 +21 chanx_left_in[8]:21 0.00205287 +22 chanx_left_in[8]:22 5.784071e-05 +23 chanx_left_in[8]:23 5.496221e-05 +24 chanx_left_in[8]:24 0.0001204793 +25 chanx_left_in[8]:25 0.0001205709 +26 chanx_left_in[8]:26 0.00050729 +27 chanx_left_in[8]:27 0.0004771019 +28 chanx_left_in[8]:28 0.0009071376 +29 chanx_left_in[8]:29 0.0009574802 +30 chanx_left_in[8]:15 chanx_right_in[6]:16 0.0006362453 +31 chanx_left_in[8]:15 chanx_right_in[6]:17 0.000551749 +32 chanx_left_in[8]:16 chanx_right_in[6]:16 6.455679e-05 +33 chanx_left_in[8]:7 chanx_right_in[6]:19 6.683024e-07 +34 chanx_left_in[8]:8 chanx_right_in[6]:17 0.0006362453 +35 chanx_left_in[8]:8 chanx_right_in[6]:18 0.0004871922 +36 chanx_left_in[8]:6 chanx_right_in[6]:20 6.683024e-07 +37 chanx_left_in[8]:21 chanx_right_in[8]:9 0.000356677 +38 chanx_left_in[8]:21 chanx_right_in[8]:13 5.180407e-07 +39 chanx_left_in[8]:21 chanx_right_in[8]:17 0.0007385541 +40 chanx_left_in[8]:20 chanx_right_in[8]:10 0.000356677 +41 chanx_left_in[8]:20 chanx_right_in[8]:14 5.180407e-07 +42 chanx_left_in[8]:20 chanx_right_in[8]:18 0.0007385541 +43 chanx_left_in[8]:15 prog_clk[0]:265 7.816679e-06 +44 chanx_left_in[8]:15 prog_clk[0]:268 7.713687e-05 +45 chanx_left_in[8]:15 prog_clk[0]:169 4.607171e-05 +46 chanx_left_in[8]:15 prog_clk[0]:273 1.449327e-05 +47 chanx_left_in[8]:15 prog_clk[0]:170 2.558385e-05 +48 chanx_left_in[8]:15 prog_clk[0]:225 6.420572e-05 +49 chanx_left_in[8]:21 prog_clk[0]:395 2.476703e-05 +50 chanx_left_in[8]:19 prog_clk[0]:388 0.0002727163 +51 chanx_left_in[8]:19 prog_clk[0]:394 6.313925e-05 +52 chanx_left_in[8]:16 prog_clk[0]:273 7.713687e-05 +53 chanx_left_in[8]:8 prog_clk[0]:268 1.449327e-05 +54 chanx_left_in[8]:8 prog_clk[0]:229 7.816679e-06 +55 chanx_left_in[8]:8 prog_clk[0]:169 2.558385e-05 +56 chanx_left_in[8]:8 prog_clk[0]:224 6.420572e-05 +57 chanx_left_in[8]:8 prog_clk[0]:164 4.607171e-05 +58 chanx_left_in[8]:20 prog_clk[0]:395 6.313925e-05 +59 chanx_left_in[8]:20 prog_clk[0]:394 2.476703e-05 +60 chanx_left_in[8]:20 prog_clk[0]:389 0.0002727163 +61 chanx_left_in[8]:15 chanx_right_in[7]:9 0.0001299463 +62 chanx_left_in[8]:15 chanx_right_in[7]:11 0.0001419722 +63 chanx_left_in[8]:8 chanx_right_in[7] 0.0001419722 +64 chanx_left_in[8]:8 chanx_right_in[7]:10 0.0001299463 +65 chanx_left_in[8]:18 chany_bottom_in[12]:15 0.0004689449 +66 chanx_left_in[8]:18 chany_bottom_in[12]:16 0.000363348 +67 chanx_left_in[8]:17 chany_bottom_in[12]:17 0.000363348 +68 chanx_left_in[8]:17 chany_bottom_in[12]:16 0.0004689449 +69 chanx_left_in[8]:18 chany_bottom_in[19]:15 0.0001429152 +70 chanx_left_in[8]:18 chany_bottom_in[19]:16 0.0005335434 +71 chanx_left_in[8]:17 chany_bottom_in[19]:17 0.0005335434 +72 chanx_left_in[8]:17 chany_bottom_in[19]:16 0.0001429152 +73 chanx_left_in[8]:15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001439221 +74 chanx_left_in[8]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001439221 +75 chanx_left_in[8]:21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.001069934 +76 chanx_left_in[8]:20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001069934 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:29 0.0001065333 +1 chanx_left_in[8]:14 chanx_left_in[8]:13 0.0005558036 +2 chanx_left_in[8]:15 chanx_left_in[8]:14 0.00341 +3 chanx_left_in[8]:15 chanx_left_in[8]:8 0.008286491 +4 chanx_left_in[8]:10 chanx_left_in[8]:9 0.0001548913 +5 chanx_left_in[8]:11 chanx_left_in[8]:10 0.0045 +6 chanx_left_in[8]:9 mux_right_track_16\/mux_l1_in_1_:A0 0.152 +7 chanx_left_in[8]:23 chanx_left_in[8]:22 0.0001548913 +8 chanx_left_in[8]:24 chanx_left_in[8]:23 0.0045 +9 chanx_left_in[8]:24 chanx_left_in[8]:21 0.00341 +10 chanx_left_in[8]:22 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 +11 chanx_left_in[8]:21 chanx_left_in[8]:20 0.007806308 +12 chanx_left_in[8]:19 chanx_left_in[8]:18 0.00341 +13 chanx_left_in[8]:18 chanx_left_in[8]:17 0.002980583 +14 chanx_left_in[8]:16 chanx_left_in[8]:15 0.0007175333 +15 chanx_left_in[8]:17 chanx_left_in[8]:16 0.00341 +16 chanx_left_in[8]:27 chanx_left_in[8]:26 0.008448662 +17 chanx_left_in[8]:28 chanx_left_in[8]:27 0.00341 +18 chanx_left_in[8]:7 chanx_left_in[8]:6 0.001729911 +19 chanx_left_in[8]:8 chanx_left_in[8]:7 0.00341 +20 chanx_left_in[8]:5 chanx_left_in[8]:4 0.00078125 +21 chanx_left_in[8]:6 chanx_left_in[8]:5 0.0045 +22 chanx_left_in[8]:4 ropt_mt_inst_813:A 0.152 +23 chanx_left_in[8]:26 chanx_left_in[8]:25 0.0004107143 +24 chanx_left_in[8]:25 chanx_left_in[8]:24 0.001214286 +25 chanx_left_in[8]:12 chanx_left_in[8]:11 0.001477679 +26 chanx_left_in[8]:13 chanx_left_in[8]:12 0.0004107143 +27 chanx_left_in[8]:29 chanx_left_in[8]:28 0.002232892 +28 chanx_left_in[8]:20 chanx_left_in[8]:19 0.001918383 + +*END + +*D_NET chanx_left_in[9] 0.02523826 //LENGTH 195.500 LUMPCC 0.007693879 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 99.280 +*I mux_bottom_track_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 32.375 64.260 +*I ropt_mt_inst_798:A I *L 0.001767 *C 134.780 53.040 +*I mux_right_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 90.335 44.540 +*N chanx_left_in[9]:4 *C 90.335 44.540 +*N chanx_left_in[9]:5 *C 90.620 44.540 +*N chanx_left_in[9]:6 *C 90.620 44.585 +*N chanx_left_in[9]:7 *C 134.743 53.040 +*N chanx_left_in[9]:8 *C 134.365 53.040 +*N chanx_left_in[9]:9 *C 134.320 52.995 +*N chanx_left_in[9]:10 *C 134.320 50.365 +*N chanx_left_in[9]:11 *C 134.275 50.320 +*N chanx_left_in[9]:12 *C 118.220 50.320 +*N chanx_left_in[9]:13 *C 118.220 50.365 +*N chanx_left_in[9]:14 *C 118.220 50.943 +*N chanx_left_in[9]:15 *C 118.213 51.000 +*N chanx_left_in[9]:16 *C 90.627 51.000 +*N chanx_left_in[9]:17 *C 90.620 51.000 +*N chanx_left_in[9]:18 *C 90.620 63.183 +*N chanx_left_in[9]:19 *C 90.613 63.240 +*N chanx_left_in[9]:20 *C 44.168 63.240 +*N chanx_left_in[9]:21 *C 44.160 63.298 +*N chanx_left_in[9]:22 *C 44.160 64.215 +*N chanx_left_in[9]:23 *C 44.115 64.260 +*N chanx_left_in[9]:24 *C 32.375 64.260 +*N chanx_left_in[9]:25 *C 25.345 64.260 +*N chanx_left_in[9]:26 *C 25.300 64.305 +*N chanx_left_in[9]:27 *C 25.300 99.223 +*N chanx_left_in[9]:28 *C 25.293 99.280 + +*CAP +0 chanx_left_in[9] 0.0008633048 +1 mux_bottom_track_11\/mux_l2_in_0_:A0 1e-06 +2 ropt_mt_inst_798:A 1e-06 +3 mux_right_track_24\/mux_l1_in_1_:A0 1e-06 +4 chanx_left_in[9]:4 4.963869e-05 +5 chanx_left_in[9]:5 5.267753e-05 +6 chanx_left_in[9]:6 0.0002218829 +7 chanx_left_in[9]:7 4.004838e-05 +8 chanx_left_in[9]:8 4.004838e-05 +9 chanx_left_in[9]:9 0.0001496196 +10 chanx_left_in[9]:10 0.0001496196 +11 chanx_left_in[9]:11 0.0008217054 +12 chanx_left_in[9]:12 0.0008475449 +13 chanx_left_in[9]:13 4.742333e-05 +14 chanx_left_in[9]:14 4.742333e-05 +15 chanx_left_in[9]:15 0.001099171 +16 chanx_left_in[9]:16 0.001099171 +17 chanx_left_in[9]:17 0.0008551989 +18 chanx_left_in[9]:18 0.0005988437 +19 chanx_left_in[9]:19 0.001983805 +20 chanx_left_in[9]:20 0.001983805 +21 chanx_left_in[9]:21 7.364477e-05 +22 chanx_left_in[9]:22 7.364477e-05 +23 chanx_left_in[9]:23 0.0006216621 +24 chanx_left_in[9]:24 0.001042949 +25 chanx_left_in[9]:25 0.0003908413 +26 chanx_left_in[9]:26 0.0017622 +27 chanx_left_in[9]:27 0.0017622 +28 chanx_left_in[9]:28 0.0008633049 +29 chanx_left_in[9]:25 chanx_right_in[8]:17 6.669457e-06 +30 chanx_left_in[9]:24 chanx_right_in[8]:17 1.506806e-05 +31 chanx_left_in[9]:24 chanx_right_in[8]:18 6.669457e-06 +32 chanx_left_in[9]:23 chanx_right_in[8]:18 1.506806e-05 +33 chanx_left_in[9]:20 chanx_right_in[8]:17 0.0001814364 +34 chanx_left_in[9]:20 chanx_right_in[8]:24 0.0002464058 +35 chanx_left_in[9]:19 chanx_right_in[8]:18 0.0001814364 +36 chanx_left_in[9]:19 chanx_right_in[8]:25 0.0002464058 +37 chanx_left_in[9]:25 chanx_right_in[17]:13 1.115308e-05 +38 chanx_left_in[9]:24 chanx_right_in[17]:13 2.519627e-05 +39 chanx_left_in[9]:24 chanx_right_in[17]:14 1.115308e-05 +40 chanx_left_in[9]:23 chanx_right_in[17]:14 2.519627e-05 +41 chanx_left_in[9]:20 chanx_right_in[17]:13 0.0004969037 +42 chanx_left_in[9]:20 chanx_right_in[17]:20 0.0003303354 +43 chanx_left_in[9]:20 chanx_right_in[17]:29 0.0001092727 +44 chanx_left_in[9]:19 chanx_right_in[17]:14 0.0004969037 +45 chanx_left_in[9]:19 chanx_right_in[17]:21 0.0003303354 +46 chanx_left_in[9]:19 chanx_right_in[17]:30 0.0001092727 +47 chanx_left_in[9]:17 chanx_left_in[17]:28 1.738998e-05 +48 chanx_left_in[9]:17 chanx_left_in[17]:29 3.474721e-05 +49 chanx_left_in[9]:17 chanx_left_in[17]:23 0.0001658701 +50 chanx_left_in[9]:17 chanx_left_in[17]:22 4.037204e-05 +51 chanx_left_in[9]:18 chanx_left_in[17]:19 3.474721e-05 +52 chanx_left_in[9]:18 chanx_left_in[17]:29 1.738998e-05 +53 chanx_left_in[9]:18 chanx_left_in[17]:23 4.037204e-05 +54 chanx_left_in[9]:6 chanx_left_in[17]:22 0.0001658701 +55 chanx_left_in[9]:16 chanx_right_in[7]:9 0.0003261836 +56 chanx_left_in[9]:16 chanx_right_in[7]:11 9.543601e-05 +57 chanx_left_in[9]:15 chanx_right_in[7] 9.543601e-05 +58 chanx_left_in[9]:15 chanx_right_in[7]:10 0.0003261836 +59 chanx_left_in[9]:12 chanx_right_in[7]:11 5.077192e-06 +60 chanx_left_in[9]:11 chanx_right_in[7] 5.077192e-06 +61 chanx_left_in[9]:20 optlc_net_164:19 0.000779154 +62 chanx_left_in[9]:19 optlc_net_164:18 0.000779154 +63 chanx_left_in[9]:16 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003129449 +64 chanx_left_in[9]:15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003129449 +65 chanx_left_in[9]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.95115e-05 +66 chanx_left_in[9]:17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.331319e-05 +67 chanx_left_in[9]:16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.162073e-06 +68 chanx_left_in[9]:15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.162073e-06 +69 chanx_left_in[9]:18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.331319e-05 +70 chanx_left_in[9]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.95115e-05 +71 chanx_left_in[9] chanx_left_out[10] 9.726927e-06 +72 chanx_left_in[9] chanx_left_out[10]:3 0.0005666103 +73 chanx_left_in[9]:28 chanx_left_out[10]:4 0.0005666103 +74 chanx_left_in[9]:28 chanx_left_out[10]:2 9.726927e-06 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:28 0.003769791 +1 chanx_left_in[9]:17 chanx_left_in[9]:16 0.00341 +2 chanx_left_in[9]:17 chanx_left_in[9]:6 0.005727679 +3 chanx_left_in[9]:16 chanx_left_in[9]:15 0.00432165 +4 chanx_left_in[9]:14 chanx_left_in[9]:13 0.000515625 +5 chanx_left_in[9]:15 chanx_left_in[9]:14 0.00341 +6 chanx_left_in[9]:12 chanx_left_in[9]:11 0.01433482 +7 chanx_left_in[9]:13 chanx_left_in[9]:12 0.0045 +8 chanx_left_in[9]:11 chanx_left_in[9]:10 0.0045 +9 chanx_left_in[9]:10 chanx_left_in[9]:9 0.002348214 +10 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0003370536 +11 chanx_left_in[9]:9 chanx_left_in[9]:8 0.0045 +12 chanx_left_in[9]:7 ropt_mt_inst_798:A 0.152 +13 chanx_left_in[9]:25 chanx_left_in[9]:24 0.006276786 +14 chanx_left_in[9]:26 chanx_left_in[9]:25 0.0045 +15 chanx_left_in[9]:27 chanx_left_in[9]:26 0.03117634 +16 chanx_left_in[9]:28 chanx_left_in[9]:27 0.00341 +17 chanx_left_in[9]:24 mux_bottom_track_11\/mux_l2_in_0_:A0 0.152 +18 chanx_left_in[9]:24 chanx_left_in[9]:23 0.01048214 +19 chanx_left_in[9]:23 chanx_left_in[9]:22 0.0045 +20 chanx_left_in[9]:22 chanx_left_in[9]:21 0.0008191965 +21 chanx_left_in[9]:21 chanx_left_in[9]:20 0.00341 +22 chanx_left_in[9]:20 chanx_left_in[9]:19 0.007276383 +23 chanx_left_in[9]:18 chanx_left_in[9]:17 0.01087723 +24 chanx_left_in[9]:19 chanx_left_in[9]:18 0.00341 +25 chanx_left_in[9]:5 chanx_left_in[9]:4 0.0001548913 +26 chanx_left_in[9]:6 chanx_left_in[9]:5 0.0045 +27 chanx_left_in[9]:4 mux_right_track_24\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET chanx_left_in[10] 0.02617913 //LENGTH 187.365 LUMPCC 0.007246462 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_track_13\/mux_l1_in_1_:A1 I *L 0.00198 *C 43.340 36.380 +*I mux_right_track_32\/mux_l1_in_1_:A1 I *L 0.00198 *C 113.065 34.340 +*I ropt_mt_inst_809:A I *L 0.001767 *C 134.780 72.080 +*N chanx_left_in[10]:4 *C 134.817 72.080 +*N chanx_left_in[10]:5 *C 135.655 72.080 +*N chanx_left_in[10]:6 *C 135.700 72.035 +*N chanx_left_in[10]:7 *C 135.700 69.360 +*N chanx_left_in[10]:8 *C 136.160 69.360 +*N chanx_left_in[10]:9 *C 136.160 58.525 +*N chanx_left_in[10]:10 *C 136.115 58.480 +*N chanx_left_in[10]:11 *C 126.085 58.480 +*N chanx_left_in[10]:12 *C 126.040 58.435 +*N chanx_left_in[10]:13 *C 126.040 36.778 +*N chanx_left_in[10]:14 *C 126.033 36.720 +*N chanx_left_in[10]:15 *C 113.160 36.720 +*N chanx_left_in[10]:16 *C 113.065 34.340 +*N chanx_left_in[10]:17 *C 113.160 34.385 +*N chanx_left_in[10]:18 *C 113.160 35.983 +*N chanx_left_in[10]:19 *C 113.160 36.047 +*N chanx_left_in[10]:20 *C 107.188 36.040 +*N chanx_left_in[10]:21 *C 107.180 36.040 +*N chanx_left_in[10]:22 *C 107.135 36.040 +*N chanx_left_in[10]:23 *C 103.500 36.040 +*N chanx_left_in[10]:24 *C 103.500 36.380 +*N chanx_left_in[10]:25 *C 100.785 36.380 +*N chanx_left_in[10]:26 *C 100.740 36.425 +*N chanx_left_in[10]:27 *C 100.740 37.355 +*N chanx_left_in[10]:28 *C 100.695 37.400 +*N chanx_left_in[10]:29 *C 92.920 37.400 +*N chanx_left_in[10]:30 *C 92.920 37.060 +*N chanx_left_in[10]:31 *C 91.080 37.060 +*N chanx_left_in[10]:32 *C 91.080 36.720 +*N chanx_left_in[10]:33 *C 86.020 36.720 +*N chanx_left_in[10]:34 *C 86.020 37.060 +*N chanx_left_in[10]:35 *C 78.200 37.060 +*N chanx_left_in[10]:36 *C 78.200 36.720 +*N chanx_left_in[10]:37 *C 74.520 36.720 +*N chanx_left_in[10]:38 *C 74.520 37.060 +*N chanx_left_in[10]:39 *C 73.140 37.060 +*N chanx_left_in[10]:40 *C 73.140 37.400 +*N chanx_left_in[10]:41 *C 41.400 37.400 +*N chanx_left_in[10]:42 *C 43.303 36.380 +*N chanx_left_in[10]:43 *C 41.400 36.380 +*N chanx_left_in[10]:44 *C 40.525 36.380 +*N chanx_left_in[10]:45 *C 40.480 36.380 +*N chanx_left_in[10]:46 *C 40.473 36.385 +*N chanx_left_in[10]:47 *C 40.468 36.720 + +*CAP +0 chanx_left_in[10] 0.001503545 +1 mux_bottom_track_13\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_32\/mux_l1_in_1_:A1 1e-06 +3 ropt_mt_inst_809:A 1e-06 +4 chanx_left_in[10]:4 0.0001031562 +5 chanx_left_in[10]:5 0.0001031562 +6 chanx_left_in[10]:6 0.0001706846 +7 chanx_left_in[10]:7 0.0002015302 +8 chanx_left_in[10]:8 0.000583588 +9 chanx_left_in[10]:9 0.0005527424 +10 chanx_left_in[10]:10 0.0005903863 +11 chanx_left_in[10]:11 0.0005903863 +12 chanx_left_in[10]:12 0.001071566 +13 chanx_left_in[10]:13 0.001071566 +14 chanx_left_in[10]:14 0.0003621563 +15 chanx_left_in[10]:15 0.0004069542 +16 chanx_left_in[10]:16 2.744755e-05 +17 chanx_left_in[10]:17 0.0001267078 +18 chanx_left_in[10]:18 0.0001267078 +19 chanx_left_in[10]:19 0.0003849048 +20 chanx_left_in[10]:20 0.0003401069 +21 chanx_left_in[10]:21 3.477895e-05 +22 chanx_left_in[10]:22 0.0002512318 +23 chanx_left_in[10]:23 0.0002759637 +24 chanx_left_in[10]:24 0.0001867669 +25 chanx_left_in[10]:25 0.0001620351 +26 chanx_left_in[10]:26 6.442497e-05 +27 chanx_left_in[10]:27 6.442497e-05 +28 chanx_left_in[10]:28 0.0004969538 +29 chanx_left_in[10]:29 0.00052292 +30 chanx_left_in[10]:30 0.0001321168 +31 chanx_left_in[10]:31 0.0001289059 +32 chanx_left_in[10]:32 0.0002962943 +33 chanx_left_in[10]:33 0.0002995002 +34 chanx_left_in[10]:34 0.0005197545 +35 chanx_left_in[10]:35 0.0005208326 +36 chanx_left_in[10]:36 0.0002919584 +37 chanx_left_in[10]:37 0.0002910206 +38 chanx_left_in[10]:38 0.0001353657 +39 chanx_left_in[10]:39 0.0001355804 +40 chanx_left_in[10]:40 0.001861699 +41 chanx_left_in[10]:41 0.001894594 +42 chanx_left_in[10]:42 0.0001170482 +43 chanx_left_in[10]:43 0.0002437087 +44 chanx_left_in[10]:44 6.744879e-05 +45 chanx_left_in[10]:45 3.669124e-05 +46 chanx_left_in[10]:46 3.840609e-05 +47 chanx_left_in[10]:47 0.001541951 +48 chanx_left_in[10] chanx_right_in[4]:8 0.0006607591 +49 chanx_left_in[10] chanx_right_in[4]:15 0.0006547585 +50 chanx_left_in[10]:14 chanx_right_in[4]:21 0.0007492996 +51 chanx_left_in[10]:19 chanx_right_in[4]:21 0.0001230128 +52 chanx_left_in[10]:20 chanx_right_in[4]:20 0.0001230128 +53 chanx_left_in[10]:41 chanx_right_in[4]:15 1.963539e-05 +54 chanx_left_in[10]:40 chanx_right_in[4]:20 1.963539e-05 +55 chanx_left_in[10]:35 chanx_right_in[4]:20 7.630202e-06 +56 chanx_left_in[10]:34 chanx_right_in[4]:21 7.630202e-06 +57 chanx_left_in[10]:33 chanx_right_in[4]:20 5.091661e-06 +58 chanx_left_in[10]:32 chanx_right_in[4]:21 5.091661e-06 +59 chanx_left_in[10]:47 chanx_right_in[4]:15 0.0006607591 +60 chanx_left_in[10]:47 chanx_right_in[4]:20 0.0006547585 +61 chanx_left_in[10]:15 chanx_right_in[4]:20 0.0007492996 +62 chanx_left_in[10]:14 chanx_right_in[9]:33 0.0003885954 +63 chanx_left_in[10]:15 chanx_right_in[9]:32 0.0003885954 +64 chanx_left_in[10] chanx_left_in[12] 1.904895e-05 +65 chanx_left_in[10] chanx_left_in[12]:30 8.890508e-06 +66 chanx_left_in[10] chanx_left_in[12]:34 0.0002402996 +67 chanx_left_in[10] chanx_left_in[12]:28 4.429442e-07 +68 chanx_left_in[10]:47 chanx_left_in[12]:27 4.429442e-07 +69 chanx_left_in[10]:47 chanx_left_in[12]:33 0.0002402996 +70 chanx_left_in[10]:47 chanx_left_in[12]:35 1.904895e-05 +71 chanx_left_in[10]:47 chanx_left_in[12]:29 8.890508e-06 +72 chanx_left_in[10]:28 mux_tree_tapbuf_size3_6_sram[1]:7 4.932648e-06 +73 chanx_left_in[10]:33 mux_tree_tapbuf_size3_6_sram[1]:6 0.0001069859 +74 chanx_left_in[10]:32 mux_tree_tapbuf_size3_6_sram[1]:7 0.0001069859 +75 chanx_left_in[10]:31 mux_tree_tapbuf_size3_6_sram[1]:6 2.434695e-05 +76 chanx_left_in[10]:30 mux_tree_tapbuf_size3_6_sram[1]:7 2.434695e-05 +77 chanx_left_in[10]:29 mux_tree_tapbuf_size3_6_sram[1]:6 4.932648e-06 +78 chanx_left_in[10]:25 mux_tree_tapbuf_size4_2_sram[0]:7 2.108582e-05 +79 chanx_left_in[10]:25 mux_tree_tapbuf_size4_2_sram[0]:12 4.931361e-06 +80 chanx_left_in[10]:26 mux_tree_tapbuf_size4_2_sram[0]:5 3.104424e-06 +81 chanx_left_in[10]:26 mux_tree_tapbuf_size4_2_sram[0]:11 6.090211e-06 +82 chanx_left_in[10]:28 mux_tree_tapbuf_size4_2_sram[0]:12 8.130907e-05 +83 chanx_left_in[10]:27 mux_tree_tapbuf_size4_2_sram[0]:6 3.104424e-06 +84 chanx_left_in[10]:27 mux_tree_tapbuf_size4_2_sram[0]:10 6.090211e-06 +85 chanx_left_in[10]:29 mux_tree_tapbuf_size4_2_sram[0]:7 8.130907e-05 +86 chanx_left_in[10]:24 mux_tree_tapbuf_size4_2_sram[0]:12 2.108582e-05 +87 chanx_left_in[10]:24 mux_tree_tapbuf_size4_2_sram[0]:13 4.931361e-06 +88 chanx_left_in[10]:41 mux_tree_tapbuf_size5_3_sram[0]:4 0.0003302491 +89 chanx_left_in[10]:40 mux_tree_tapbuf_size5_3_sram[0]:5 0.0003302491 +90 chanx_left_in[10]:41 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 7.244461e-05 +91 chanx_left_in[10]:40 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 7.244461e-05 +92 chanx_left_in[10]:41 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.028627e-05 +93 chanx_left_in[10]:40 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.028627e-05 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:47 0.006147208 +1 chanx_left_in[10]:4 ropt_mt_inst_809:A 0.152 +2 chanx_left_in[10]:5 chanx_left_in[10]:4 0.0007477679 +3 chanx_left_in[10]:6 chanx_left_in[10]:5 0.0045 +4 chanx_left_in[10]:10 chanx_left_in[10]:9 0.0045 +5 chanx_left_in[10]:9 chanx_left_in[10]:8 0.009674108 +6 chanx_left_in[10]:11 chanx_left_in[10]:10 0.008955358 +7 chanx_left_in[10]:12 chanx_left_in[10]:11 0.0045 +8 chanx_left_in[10]:13 chanx_left_in[10]:12 0.01933705 +9 chanx_left_in[10]:14 chanx_left_in[10]:13 0.00341 +10 chanx_left_in[10]:44 chanx_left_in[10]:43 0.00078125 +11 chanx_left_in[10]:45 chanx_left_in[10]:44 0.0045 +12 chanx_left_in[10]:46 chanx_left_in[10]:45 0.00341 +13 chanx_left_in[10]:18 chanx_left_in[10]:17 0.001426339 +14 chanx_left_in[10]:19 chanx_left_in[10]:18 0.00341 +15 chanx_left_in[10]:19 chanx_left_in[10]:15 0.0001053583 +16 chanx_left_in[10]:16 mux_right_track_32\/mux_l1_in_1_:A1 0.152 +17 chanx_left_in[10]:17 chanx_left_in[10]:16 0.0045 +18 chanx_left_in[10]:42 mux_bottom_track_13\/mux_l1_in_1_:A1 0.152 +19 chanx_left_in[10]:21 chanx_left_in[10]:20 0.00341 +20 chanx_left_in[10]:20 chanx_left_in[10]:19 0.0009356916 +21 chanx_left_in[10]:22 chanx_left_in[10]:21 0.0045 +22 chanx_left_in[10]:25 chanx_left_in[10]:24 0.002424107 +23 chanx_left_in[10]:26 chanx_left_in[10]:25 0.0045 +24 chanx_left_in[10]:28 chanx_left_in[10]:27 0.0045 +25 chanx_left_in[10]:27 chanx_left_in[10]:26 0.0008303573 +26 chanx_left_in[10]:43 chanx_left_in[10]:42 0.001698661 +27 chanx_left_in[10]:43 chanx_left_in[10]:41 0.0009107143 +28 chanx_left_in[10]:41 chanx_left_in[10]:40 0.02833929 +29 chanx_left_in[10]:40 chanx_left_in[10]:39 0.0003035715 +30 chanx_left_in[10]:39 chanx_left_in[10]:38 0.001232143 +31 chanx_left_in[10]:38 chanx_left_in[10]:37 0.0003035715 +32 chanx_left_in[10]:37 chanx_left_in[10]:36 0.003285714 +33 chanx_left_in[10]:36 chanx_left_in[10]:35 0.0003035715 +34 chanx_left_in[10]:35 chanx_left_in[10]:34 0.006982143 +35 chanx_left_in[10]:34 chanx_left_in[10]:33 0.0003035715 +36 chanx_left_in[10]:33 chanx_left_in[10]:32 0.004517857 +37 chanx_left_in[10]:32 chanx_left_in[10]:31 0.0003035715 +38 chanx_left_in[10]:31 chanx_left_in[10]:30 0.001642857 +39 chanx_left_in[10]:30 chanx_left_in[10]:29 0.0003035715 +40 chanx_left_in[10]:29 chanx_left_in[10]:28 0.006941964 +41 chanx_left_in[10]:24 chanx_left_in[10]:23 0.0003035715 +42 chanx_left_in[10]:23 chanx_left_in[10]:22 0.003245536 +43 chanx_left_in[10]:7 chanx_left_in[10]:6 0.002388393 +44 chanx_left_in[10]:8 chanx_left_in[10]:7 0.0004107143 +45 chanx_left_in[10]:47 chanx_left_in[10]:46 4.998412e-05 +46 chanx_left_in[10]:15 chanx_left_in[10]:14 0.002016691 + +*END + +*D_NET chanx_left_in[13] 0.03015424 //LENGTH 229.970 LUMPCC 0.008671842 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 74.800 +*I mux_bottom_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 53.360 23.460 +*I mux_right_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 75.440 58.140 +*I ropt_mt_inst_805:A I *L 0.001767 *C 134.780 93.840 +*N chanx_left_in[13]:4 *C 134.780 93.840 +*N chanx_left_in[13]:5 *C 134.780 93.795 +*N chanx_left_in[13]:6 *C 134.780 90.485 +*N chanx_left_in[13]:7 *C 134.735 90.440 +*N chanx_left_in[13]:8 *C 121.485 90.440 +*N chanx_left_in[13]:9 *C 121.440 90.395 +*N chanx_left_in[13]:10 *C 121.440 82.960 +*N chanx_left_in[13]:11 *C 121.440 83.640 +*N chanx_left_in[13]:12 *C 121.433 83.640 +*N chanx_left_in[13]:13 *C 120.528 83.640 +*N chanx_left_in[13]:14 *C 120.520 83.583 +*N chanx_left_in[13]:15 *C 120.520 80.297 +*N chanx_left_in[13]:16 *C 120.513 80.240 +*N chanx_left_in[13]:17 *C 82.808 80.240 +*N chanx_left_in[13]:18 *C 82.800 80.183 +*N chanx_left_in[13]:19 *C 82.800 74.858 +*N chanx_left_in[13]:20 *C 82.793 74.800 +*N chanx_left_in[13]:21 *C 75.418 58.168 +*N chanx_left_in[13]:22 *C 75.405 58.480 +*N chanx_left_in[13]:23 *C 73.185 58.480 +*N chanx_left_in[13]:24 *C 73.140 58.525 +*N chanx_left_in[13]:25 *C 73.140 74.743 +*N chanx_left_in[13]:26 *C 73.140 74.800 +*N chanx_left_in[13]:27 *C 53.398 23.460 +*N chanx_left_in[13]:28 *C 53.775 23.460 +*N chanx_left_in[13]:29 *C 53.820 23.505 +*N chanx_left_in[13]:30 *C 53.820 69.303 +*N chanx_left_in[13]:31 *C 53.828 69.360 +*N chanx_left_in[13]:32 *C 55.180 69.360 +*N chanx_left_in[13]:33 *C 55.200 69.368 +*N chanx_left_in[13]:34 *C 55.200 74.793 +*N chanx_left_in[13]:35 *C 55.200 74.800 + +*CAP +0 chanx_left_in[13] 0.002065269 +1 mux_bottom_track_17\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_2\/mux_l2_in_1_:A1 1e-06 +3 ropt_mt_inst_805:A 1e-06 +4 chanx_left_in[13]:4 3.733058e-05 +5 chanx_left_in[13]:5 0.0002120844 +6 chanx_left_in[13]:6 0.0002120844 +7 chanx_left_in[13]:7 0.0007408192 +8 chanx_left_in[13]:8 0.0007408192 +9 chanx_left_in[13]:9 0.0003273751 +10 chanx_left_in[13]:10 4.448446e-05 +11 chanx_left_in[13]:11 0.000404614 +12 chanx_left_in[13]:12 3.872671e-05 +13 chanx_left_in[13]:13 3.872671e-05 +14 chanx_left_in[13]:14 0.0001776778 +15 chanx_left_in[13]:15 0.0001776778 +16 chanx_left_in[13]:16 0.001423453 +17 chanx_left_in[13]:17 0.001423453 +18 chanx_left_in[13]:18 0.0002944188 +19 chanx_left_in[13]:19 0.0002944188 +20 chanx_left_in[13]:20 0.0003857729 +21 chanx_left_in[13]:21 3.113387e-05 +22 chanx_left_in[13]:22 0.0002161495 +23 chanx_left_in[13]:23 0.0001850157 +24 chanx_left_in[13]:24 0.0009295522 +25 chanx_left_in[13]:25 0.0009295522 +26 chanx_left_in[13]:26 0.001081538 +27 chanx_left_in[13]:27 4.587975e-05 +28 chanx_left_in[13]:28 4.587975e-05 +29 chanx_left_in[13]:29 0.002403769 +30 chanx_left_in[13]:30 0.002403769 +31 chanx_left_in[13]:31 0.0001633406 +32 chanx_left_in[13]:32 0.0001633406 +33 chanx_left_in[13]:33 0.0005401156 +34 chanx_left_in[13]:34 0.0005401156 +35 chanx_left_in[13]:35 0.002761033 +36 chanx_left_in[13]:35 chanx_right_in[8]:28 8.17943e-05 +37 chanx_left_in[13]:26 chanx_right_in[8]:28 0.0001098088 +38 chanx_left_in[13]:26 chanx_right_in[8]:29 8.17943e-05 +39 chanx_left_in[13]:16 chanx_right_in[8] 6.24567e-05 +40 chanx_left_in[13]:16 chanx_right_in[8]:29 0.0003567471 +41 chanx_left_in[13]:17 chanx_right_in[8]:28 0.0003567471 +42 chanx_left_in[13]:17 chanx_right_in[8]:29 6.24567e-05 +43 chanx_left_in[13]:20 chanx_right_in[8]:29 0.0001098088 +44 chanx_left_in[13] chanx_right_in[9]:20 0.0001056963 +45 chanx_left_in[13]:35 chanx_right_in[9]:21 0.0001056963 +46 chanx_left_in[13]:16 chanx_right_in[9]:28 0.0001531351 +47 chanx_left_in[13]:16 chanx_right_in[9]:29 6.173761e-05 +48 chanx_left_in[13]:17 chanx_right_in[9]:27 0.0001531351 +49 chanx_left_in[13]:17 chanx_right_in[9]:28 6.173761e-05 +50 chanx_left_in[13]:35 chanx_right_in[12]:28 0.0001721555 +51 chanx_left_in[13]:32 chanx_right_in[12]:29 7.642603e-06 +52 chanx_left_in[13]:31 chanx_right_in[12]:28 7.642603e-06 +53 chanx_left_in[13]:26 chanx_right_in[12]:28 0.0001283282 +54 chanx_left_in[13]:26 chanx_right_in[12]:29 0.0001721555 +55 chanx_left_in[13]:20 chanx_right_in[12]:29 0.0001283282 +56 chanx_left_in[13]:30 mux_tree_tapbuf_size6_4_sram[2]:7 0.0001367107 +57 chanx_left_in[13]:30 mux_tree_tapbuf_size6_4_sram[2]:10 1.338834e-07 +58 chanx_left_in[13]:29 mux_tree_tapbuf_size6_4_sram[2]:6 0.0001367107 +59 chanx_left_in[13]:29 mux_tree_tapbuf_size6_4_sram[2]:11 1.338834e-07 +60 chanx_left_in[13]:30 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.765513e-05 +61 chanx_left_in[13]:29 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.765513e-05 +62 chanx_left_in[13] mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002381228 +63 chanx_left_in[13]:35 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002886391 +64 chanx_left_in[13]:35 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002381228 +65 chanx_left_in[13]:26 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002886391 +66 chanx_left_in[13]:8 ropt_net_218:5 9.565813e-05 +67 chanx_left_in[13]:8 ropt_net_218:3 1.72236e-05 +68 chanx_left_in[13]:7 ropt_net_218:2 1.72236e-05 +69 chanx_left_in[13]:7 ropt_net_218:4 9.565813e-05 +70 chanx_left_in[13]:12 ropt_net_183:5 7.115601e-05 +71 chanx_left_in[13]:13 ropt_net_183:6 7.115601e-05 +72 chanx_left_in[13]:16 ropt_net_183:5 3.801403e-05 +73 chanx_left_in[13]:17 ropt_net_183:6 3.801403e-05 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:35 0.0084553 +1 chanx_left_in[13]:35 chanx_left_in[13]:34 0.00341 +2 chanx_left_in[13]:35 chanx_left_in[13]:26 0.0028106 +3 chanx_left_in[13]:34 chanx_left_in[13]:33 0.0008499166 +4 chanx_left_in[13]:32 chanx_left_in[13]:31 0.0002118917 +5 chanx_left_in[13]:33 chanx_left_in[13]:32 0.00341 +6 chanx_left_in[13]:30 chanx_left_in[13]:29 0.04089063 +7 chanx_left_in[13]:31 chanx_left_in[13]:30 0.00341 +8 chanx_left_in[13]:28 chanx_left_in[13]:27 0.0003370536 +9 chanx_left_in[13]:29 chanx_left_in[13]:28 0.0045 +10 chanx_left_in[13]:27 mux_bottom_track_17\/mux_l1_in_1_:A1 0.152 +11 chanx_left_in[13]:25 chanx_left_in[13]:24 0.01447991 +12 chanx_left_in[13]:26 chanx_left_in[13]:25 0.00341 +13 chanx_left_in[13]:26 chanx_left_in[13]:20 0.001512225 +14 chanx_left_in[13]:23 chanx_left_in[13]:22 0.001982143 +15 chanx_left_in[13]:24 chanx_left_in[13]:23 0.0045 +16 chanx_left_in[13]:21 mux_right_track_2\/mux_l2_in_1_:A1 0.152 +17 chanx_left_in[13]:11 chanx_left_in[13]:10 0.0006071429 +18 chanx_left_in[13]:11 chanx_left_in[13]:9 0.00603125 +19 chanx_left_in[13]:12 chanx_left_in[13]:11 0.00341 +20 chanx_left_in[13]:14 chanx_left_in[13]:13 0.00341 +21 chanx_left_in[13]:13 chanx_left_in[13]:12 0.0001417833 +22 chanx_left_in[13]:15 chanx_left_in[13]:14 0.002933036 +23 chanx_left_in[13]:16 chanx_left_in[13]:15 0.00341 +24 chanx_left_in[13]:18 chanx_left_in[13]:17 0.00341 +25 chanx_left_in[13]:17 chanx_left_in[13]:16 0.005907116 +26 chanx_left_in[13]:19 chanx_left_in[13]:18 0.004754465 +27 chanx_left_in[13]:20 chanx_left_in[13]:19 0.00341 +28 chanx_left_in[13]:8 chanx_left_in[13]:7 0.01183036 +29 chanx_left_in[13]:9 chanx_left_in[13]:8 0.0045 +30 chanx_left_in[13]:7 chanx_left_in[13]:6 0.0045 +31 chanx_left_in[13]:6 chanx_left_in[13]:5 0.002955357 +32 chanx_left_in[13]:4 ropt_mt_inst_805:A 0.152 +33 chanx_left_in[13]:5 chanx_left_in[13]:4 0.0045 +34 chanx_left_in[13]:22 chanx_left_in[13]:21 0.0002111487 + +*END + +*D_NET chanx_left_in[16] 0.0314524 //LENGTH 231.200 LUMPCC 0.00957837 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.305 55.760 +*I mux_bottom_track_21\/mux_l1_in_1_:A1 I *L 0.00198 *C 79.120 30.940 +*I mux_right_track_8\/mux_l1_in_2_:A0 I *L 0.001631 *C 116.210 58.820 +*I ropt_mt_inst_793:A I *L 0.001767 *C 130.180 91.120 +*N chanx_left_in[16]:4 *C 130.180 91.157 +*N chanx_left_in[16]:5 *C 130.180 91.800 +*N chanx_left_in[16]:6 *C 137.955 91.800 +*N chanx_left_in[16]:7 *C 138.000 91.755 +*N chanx_left_in[16]:8 *C 138.000 87.720 +*N chanx_left_in[16]:9 *C 138.920 87.720 +*N chanx_left_in[16]:10 *C 138.920 72.465 +*N chanx_left_in[16]:11 *C 138.875 72.420 +*N chanx_left_in[16]:12 *C 122.820 72.420 +*N chanx_left_in[16]:13 *C 122.820 72.080 +*N chanx_left_in[16]:14 *C 121.945 72.080 +*N chanx_left_in[16]:15 *C 121.900 72.035 +*N chanx_left_in[16]:16 *C 121.900 58.865 +*N chanx_left_in[16]:17 *C 121.855 58.820 +*N chanx_left_in[16]:18 *C 116.248 58.820 +*N chanx_left_in[16]:19 *C 117.300 58.820 +*N chanx_left_in[16]:20 *C 117.300 58.775 +*N chanx_left_in[16]:21 *C 117.300 56.498 +*N chanx_left_in[16]:22 *C 117.293 56.440 +*N chanx_left_in[16]:23 *C 79.083 30.940 +*N chanx_left_in[16]:24 *C 76.405 30.940 +*N chanx_left_in[16]:25 *C 76.360 30.985 +*N chanx_left_in[16]:26 *C 76.360 31.902 +*N chanx_left_in[16]:27 *C 76.353 31.960 +*N chanx_left_in[16]:28 *C 74.540 31.960 +*N chanx_left_in[16]:29 *C 74.520 31.968 +*N chanx_left_in[16]:30 *C 74.520 56.433 +*N chanx_left_in[16]:31 *C 74.520 56.440 +*N chanx_left_in[16]:32 *C 68.547 56.440 +*N chanx_left_in[16]:33 *C 68.540 56.498 +*N chanx_left_in[16]:34 *C 68.540 59.115 +*N chanx_left_in[16]:35 *C 68.495 59.160 +*N chanx_left_in[16]:36 *C 35.005 59.160 +*N chanx_left_in[16]:37 *C 34.960 59.115 +*N chanx_left_in[16]:38 *C 34.960 53.098 +*N chanx_left_in[16]:39 *C 34.953 53.040 +*N chanx_left_in[16]:40 *C 5.060 53.040 +*N chanx_left_in[16]:41 *C 5.060 55.760 + +*CAP +0 chanx_left_in[16] 0.0002603416 +1 mux_bottom_track_21\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_2_:A0 1e-06 +3 ropt_mt_inst_793:A 1e-06 +4 chanx_left_in[16]:4 4.762089e-05 +5 chanx_left_in[16]:5 0.000491247 +6 chanx_left_in[16]:6 0.0004436262 +7 chanx_left_in[16]:7 0.0002455499 +8 chanx_left_in[16]:8 0.0002984126 +9 chanx_left_in[16]:9 0.0007682099 +10 chanx_left_in[16]:10 0.0007153472 +11 chanx_left_in[16]:11 0.0009492564 +12 chanx_left_in[16]:12 0.0009722499 +13 chanx_left_in[16]:13 0.0001231179 +14 chanx_left_in[16]:14 0.0001001243 +15 chanx_left_in[16]:15 0.0005433362 +16 chanx_left_in[16]:16 0.0005433362 +17 chanx_left_in[16]:17 0.0002720966 +18 chanx_left_in[16]:18 7.209677e-05 +19 chanx_left_in[16]:19 0.00037241 +20 chanx_left_in[16]:20 0.0001418165 +21 chanx_left_in[16]:21 0.0001418165 +22 chanx_left_in[16]:22 0.001567521 +23 chanx_left_in[16]:23 0.0002094811 +24 chanx_left_in[16]:24 0.0002094811 +25 chanx_left_in[16]:25 7.74808e-05 +26 chanx_left_in[16]:26 7.74808e-05 +27 chanx_left_in[16]:27 0.0001781775 +28 chanx_left_in[16]:28 0.0001781775 +29 chanx_left_in[16]:29 0.001027408 +30 chanx_left_in[16]:30 0.001027408 +31 chanx_left_in[16]:31 0.001824653 +32 chanx_left_in[16]:32 0.0002571314 +33 chanx_left_in[16]:33 0.0001507124 +34 chanx_left_in[16]:34 0.0001507124 +35 chanx_left_in[16]:35 0.002165387 +36 chanx_left_in[16]:36 0.002165387 +37 chanx_left_in[16]:37 0.0003068491 +38 chanx_left_in[16]:38 0.0003068491 +39 chanx_left_in[16]:39 0.0009402069 +40 chanx_left_in[16]:40 0.001114187 +41 chanx_left_in[16]:41 0.000434322 +42 chanx_left_in[16]:39 chanx_right_in[13]:23 0.0004560622 +43 chanx_left_in[16]:40 chanx_right_in[13]:22 0.0004560622 +44 chanx_left_in[16]:16 chanx_left_in[14]:10 0.0001308385 +45 chanx_left_in[16]:15 chanx_left_in[14]:9 0.0001308385 +46 chanx_left_in[16]:32 chanx_left_in[14]:26 0.0001358419 +47 chanx_left_in[16]:31 chanx_left_in[14]:12 0.0001730462 +48 chanx_left_in[16]:31 chanx_left_in[14]:17 0.0001358419 +49 chanx_left_in[16]:31 chanx_left_in[14]:26 0.0005559903 +50 chanx_left_in[16]:22 chanx_left_in[14]:11 0.0001730462 +51 chanx_left_in[16]:22 chanx_left_in[14]:17 0.0005559903 +52 chanx_left_in[16]:33 chany_bottom_in[3]:11 2.857674e-07 +53 chanx_left_in[16]:32 chany_bottom_in[3]:13 0.000159602 +54 chanx_left_in[16]:32 chany_bottom_in[3]:10 1.381927e-05 +55 chanx_left_in[16]:34 chany_bottom_in[3]:12 2.857674e-07 +56 chanx_left_in[16]:31 chany_bottom_in[3]:13 0.0008473633 +57 chanx_left_in[16]:31 chany_bottom_in[3]:14 0.0002195366 +58 chanx_left_in[16]:31 chany_bottom_in[3]:11 1.381927e-05 +59 chanx_left_in[16]:22 chany_bottom_in[3]:7 5.993462e-05 +60 chanx_left_in[16]:22 chany_bottom_in[3]:14 0.0008473633 +61 chanx_left_in[16]:33 chany_bottom_in[11]:9 3.293736e-05 +62 chanx_left_in[16]:34 chany_bottom_in[11]:8 3.293736e-05 +63 chanx_left_in[16]:30 chany_bottom_in[11]:12 0.0003936388 +64 chanx_left_in[16]:29 chany_bottom_in[11]:13 0.0003936388 +65 chanx_left_in[16]:30 chany_bottom_in[19]:16 0.000253811 +66 chanx_left_in[16]:29 chany_bottom_in[19]:17 0.000253811 +67 chanx_left_in[16]:35 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 7.901236e-06 +68 chanx_left_in[16]:36 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 7.901236e-06 +69 chanx_left_in[16]:37 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 7.84865e-05 +70 chanx_left_in[16]:38 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 7.84865e-05 +71 chanx_left_in[16]:39 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001251908 +72 chanx_left_in[16]:40 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001251908 +73 chanx_left_in[16]:31 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001440257 +74 chanx_left_in[16]:22 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001440257 +75 chanx_left_in[16]:6 ropt_net_218:2 2.925725e-05 +76 chanx_left_in[16]:6 ropt_net_218:4 2.217808e-05 +77 chanx_left_in[16]:5 ropt_net_218:5 2.217808e-05 +78 chanx_left_in[16]:5 ropt_net_218:3 2.925725e-05 +79 chanx_left_in[16]:10 ropt_net_206:9 4.225602e-05 +80 chanx_left_in[16]:9 ropt_net_206:8 4.225602e-05 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:41 0.0005882833 +1 chanx_left_in[16]:17 chanx_left_in[16]:16 0.0045 +2 chanx_left_in[16]:16 chanx_left_in[16]:15 0.01175893 +3 chanx_left_in[16]:14 chanx_left_in[16]:13 0.00078125 +4 chanx_left_in[16]:15 chanx_left_in[16]:14 0.0045 +5 chanx_left_in[16]:11 chanx_left_in[16]:10 0.0045 +6 chanx_left_in[16]:10 chanx_left_in[16]:9 0.01362054 +7 chanx_left_in[16]:6 chanx_left_in[16]:5 0.006941965 +8 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0045 +9 chanx_left_in[16]:4 ropt_mt_inst_793:A 0.152 +10 chanx_left_in[16]:33 chanx_left_in[16]:32 0.00341 +11 chanx_left_in[16]:32 chanx_left_in[16]:31 0.0009356915 +12 chanx_left_in[16]:35 chanx_left_in[16]:34 0.0045 +13 chanx_left_in[16]:34 chanx_left_in[16]:33 0.002337054 +14 chanx_left_in[16]:36 chanx_left_in[16]:35 0.02990179 +15 chanx_left_in[16]:37 chanx_left_in[16]:36 0.0045 +16 chanx_left_in[16]:38 chanx_left_in[16]:37 0.005372768 +17 chanx_left_in[16]:39 chanx_left_in[16]:38 0.00341 +18 chanx_left_in[16]:31 chanx_left_in[16]:30 0.00341 +19 chanx_left_in[16]:31 chanx_left_in[16]:22 0.006701025 +20 chanx_left_in[16]:30 chanx_left_in[16]:29 0.00383285 +21 chanx_left_in[16]:28 chanx_left_in[16]:27 0.0002839583 +22 chanx_left_in[16]:29 chanx_left_in[16]:28 0.00341 +23 chanx_left_in[16]:26 chanx_left_in[16]:25 0.0008191965 +24 chanx_left_in[16]:27 chanx_left_in[16]:26 0.00341 +25 chanx_left_in[16]:24 chanx_left_in[16]:23 0.002390625 +26 chanx_left_in[16]:25 chanx_left_in[16]:24 0.0045 +27 chanx_left_in[16]:23 mux_bottom_track_21\/mux_l1_in_1_:A1 0.152 +28 chanx_left_in[16]:19 chanx_left_in[16]:18 0.0009397322 +29 chanx_left_in[16]:19 chanx_left_in[16]:17 0.004066965 +30 chanx_left_in[16]:20 chanx_left_in[16]:19 0.0045 +31 chanx_left_in[16]:21 chanx_left_in[16]:20 0.002033482 +32 chanx_left_in[16]:22 chanx_left_in[16]:21 0.00341 +33 chanx_left_in[16]:18 mux_right_track_8\/mux_l1_in_2_:A0 0.152 +34 chanx_left_in[16]:13 chanx_left_in[16]:12 0.0003035715 +35 chanx_left_in[16]:12 chanx_left_in[16]:11 0.01433482 +36 chanx_left_in[16]:5 chanx_left_in[16]:4 0.0005736608 +37 chanx_left_in[16]:8 chanx_left_in[16]:7 0.003602679 +38 chanx_left_in[16]:9 chanx_left_in[16]:8 0.0008214286 +39 chanx_left_in[16]:41 chanx_left_in[16]:40 0.0004261333 +40 chanx_left_in[16]:40 chanx_left_in[16]:39 0.004683158 + +*END + +*D_NET prog_clk[0] 0.1236305 //LENGTH 854.028 LUMPCC 0.02973859 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 30.820 1.290 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 33.845 12.240 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 31.470 14.960 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 39.825 31.280 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 48.105 42.160 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 50.405 34.000 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 52.245 36.720 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 58.225 39.440 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 39.825 39.440 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 43.045 25.840 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.345 17.680 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 13.605 31.280 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 13.605 36.720 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 29.705 39.440 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 20.505 47.600 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 18.665 53.040 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 16.365 63.920 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 17.285 61.200 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 33.385 50.320 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 38.445 55.760 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 42.585 72.080 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 50.865 77.520 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 50.865 85.680 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 43.045 80.240 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 44.885 61.200 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.185 63.920 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 44.885 53.040 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 50.405 55.760 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.605 58.480 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.665 53.040 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 69.725 69.360 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 74.785 66.640 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 66.045 80.240 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.565 82.960 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 79.845 80.240 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.205 85.680 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 42.125 47.600 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 53.040 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 25.105 58.480 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 33.385 69.360 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 29.705 72.080 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 23.725 74.800 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 17.745 72.080 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 33.385 23.120 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 54.085 17.680 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 63.745 14.960 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.505 20.400 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.550 23.120 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 64.205 28.560 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 69.265 34.000 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 69.265 36.720 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 71.565 44.880 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 73.405 53.040 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 82.100 58.480 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 87.205 69.360 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 94.105 66.640 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 108.365 69.360 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 92.670 80.240 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 93.645 82.960 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 102.845 82.960 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 87.205 50.320 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 84.445 47.600 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 55.005 14.960 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 75.245 9.520 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.495 12.240 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 75.705 17.680 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 77.085 28.560 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 84.445 31.280 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 95.025 36.720 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 96.405 42.160 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 94.105 44.880 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 95.945 53.040 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 99.165 50.320 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 95.945 34.000 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 107.905 36.720 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 107.445 44.880 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 107.905 50.320 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 87.205 34.000 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 80.305 20.400 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.045 20.400 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 91.345 6.800 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 101.005 9.520 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 91.805 12.240 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 90.885 14.960 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 97.325 23.120 +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 101.925 25.840 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 101.925 17.680 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 42.125 6.800 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 41.665 9.520 +*N prog_clk[0]:89 *C 41.665 9.520 +*N prog_clk[0]:90 *C 41.860 9.520 +*N prog_clk[0]:91 *C 41.860 9.475 +*N prog_clk[0]:92 *C 42.125 6.800 +*N prog_clk[0]:93 *C 41.860 6.800 +*N prog_clk[0]:94 *C 41.860 6.800 +*N prog_clk[0]:95 *C 41.860 6.808 +*N prog_clk[0]:96 *C 101.925 17.680 +*N prog_clk[0]:97 *C 101.660 17.680 +*N prog_clk[0]:98 *C 101.660 17.635 +*N prog_clk[0]:99 *C 101.660 16.378 +*N prog_clk[0]:100 *C 101.653 16.320 +*N prog_clk[0]:101 *C 101.925 25.840 +*N prog_clk[0]:102 *C 101.660 25.840 +*N prog_clk[0]:103 *C 101.660 25.840 +*N prog_clk[0]:104 *C 101.653 25.840 +*N prog_clk[0]:105 *C 97.068 25.840 +*N prog_clk[0]:106 *C 97.060 25.783 +*N prog_clk[0]:107 *C 97.325 23.120 +*N prog_clk[0]:108 *C 97.060 22.780 +*N prog_clk[0]:109 *C 97.060 22.780 +*N prog_clk[0]:110 *C 97.060 16.378 +*N prog_clk[0]:111 *C 97.060 16.320 +*N prog_clk[0]:112 *C 91.088 16.320 +*N prog_clk[0]:113 *C 91.080 16.262 +*N prog_clk[0]:114 *C 90.885 14.960 +*N prog_clk[0]:115 *C 91.080 15.300 +*N prog_clk[0]:116 *C 91.080 15.300 +*N prog_clk[0]:117 *C 91.767 12.240 +*N prog_clk[0]:118 *C 91.080 12.240 +*N prog_clk[0]:119 *C 91.080 11.900 +*N prog_clk[0]:120 *C 91.080 11.900 +*N prog_clk[0]:121 *C 101.005 9.520 +*N prog_clk[0]:122 *C 100.740 9.520 +*N prog_clk[0]:123 *C 100.740 9.520 +*N prog_clk[0]:124 *C 100.733 9.520 +*N prog_clk[0]:125 *C 91.088 9.520 +*N prog_clk[0]:126 *C 91.080 9.520 +*N prog_clk[0]:127 *C 91.345 6.800 +*N prog_clk[0]:128 *C 91.080 6.800 +*N prog_clk[0]:129 *C 91.080 6.845 +*N prog_clk[0]:130 *C 91.080 7.480 +*N prog_clk[0]:131 *C 91.073 7.480 +*N prog_clk[0]:132 *C 89.008 20.400 +*N prog_clk[0]:133 *C 88.365 20.400 +*N prog_clk[0]:134 *C 88.320 20.400 +*N prog_clk[0]:135 *C 88.312 20.400 +*N prog_clk[0]:136 *C 80.305 20.400 +*N prog_clk[0]:137 *C 80.040 20.400 +*N prog_clk[0]:138 *C 80.040 20.400 +*N prog_clk[0]:139 *C 80.040 20.400 +*N prog_clk[0]:140 *C 87.205 34.000 +*N prog_clk[0]:141 *C 87.400 34.000 +*N prog_clk[0]:142 *C 107.868 50.320 +*N prog_clk[0]:143 *C 106.765 50.320 +*N prog_clk[0]:144 *C 106.720 50.275 +*N prog_clk[0]:145 *C 107.407 44.880 +*N prog_clk[0]:146 *C 106.720 44.880 +*N prog_clk[0]:147 *C 106.720 44.540 +*N prog_clk[0]:148 *C 106.690 44.570 +*N prog_clk[0]:149 *C 106.675 44.880 +*N prog_clk[0]:150 *C 106.260 44.880 +*N prog_clk[0]:151 *C 107.868 36.720 +*N prog_clk[0]:152 *C 106.305 36.720 +*N prog_clk[0]:153 *C 106.260 36.720 +*N prog_clk[0]:154 *C 106.260 34.058 +*N prog_clk[0]:155 *C 106.253 34.000 +*N prog_clk[0]:156 *C 95.945 34.000 +*N prog_clk[0]:157 *C 96.140 34.000 +*N prog_clk[0]:158 *C 96.140 34.000 +*N prog_clk[0]:159 *C 96.140 34.000 +*N prog_clk[0]:160 *C 99.165 50.320 +*N prog_clk[0]:161 *C 98.900 50.320 +*N prog_clk[0]:162 *C 98.900 50.275 +*N prog_clk[0]:163 *C 98.900 49.018 +*N prog_clk[0]:164 *C 98.892 48.960 +*N prog_clk[0]:165 *C 95.945 53.040 +*N prog_clk[0]:166 *C 96.140 53.040 +*N prog_clk[0]:167 *C 96.140 52.995 +*N prog_clk[0]:168 *C 96.140 49.018 +*N prog_clk[0]:169 *C 96.140 48.960 +*N prog_clk[0]:170 *C 94.767 48.960 +*N prog_clk[0]:171 *C 94.760 48.903 +*N prog_clk[0]:172 *C 94.105 44.880 +*N prog_clk[0]:173 *C 94.300 44.540 +*N prog_clk[0]:174 *C 94.715 44.540 +*N prog_clk[0]:175 *C 94.760 44.540 +*N prog_clk[0]:176 *C 96.405 42.160 +*N prog_clk[0]:177 *C 96.140 42.160 +*N prog_clk[0]:178 *C 96.140 42.160 +*N prog_clk[0]:179 *C 96.133 42.160 +*N prog_clk[0]:180 *C 94.767 42.160 +*N prog_clk[0]:181 *C 94.760 42.160 +*N prog_clk[0]:182 *C 95.025 36.720 +*N prog_clk[0]:183 *C 94.760 37.060 +*N prog_clk[0]:184 *C 94.760 37.060 +*N prog_clk[0]:185 *C 94.760 34.058 +*N prog_clk[0]:186 *C 94.760 34.000 +*N prog_clk[0]:187 *C 87.407 34.000 +*N prog_clk[0]:188 *C 87.400 34.000 +*N prog_clk[0]:189 *C 87.400 31.338 +*N prog_clk[0]:190 *C 87.392 31.280 +*N prog_clk[0]:191 *C 84.445 31.280 +*N prog_clk[0]:192 *C 84.640 31.280 +*N prog_clk[0]:193 *C 84.640 31.280 +*N prog_clk[0]:194 *C 84.640 31.280 +*N prog_clk[0]:195 *C 77.288 31.280 +*N prog_clk[0]:196 *C 77.280 31.223 +*N prog_clk[0]:197 *C 77.085 28.560 +*N prog_clk[0]:198 *C 77.280 28.220 +*N prog_clk[0]:199 *C 77.280 28.220 +*N prog_clk[0]:200 *C 77.280 20.457 +*N prog_clk[0]:201 *C 77.280 20.400 +*N prog_clk[0]:202 *C 75.448 20.400 +*N prog_clk[0]:203 *C 75.440 20.343 +*N prog_clk[0]:204 *C 75.440 18.065 +*N prog_clk[0]:205 *C 75.440 18.020 +*N prog_clk[0]:206 *C 75.705 17.680 +*N prog_clk[0]:207 *C 75.440 17.680 +*N prog_clk[0]:208 *C 74.060 17.680 +*N prog_clk[0]:209 *C 74.060 17.340 +*N prog_clk[0]:210 *C 73.645 17.340 +*N prog_clk[0]:211 *C 73.600 17.295 +*N prog_clk[0]:212 *C 73.495 12.240 +*N prog_clk[0]:213 *C 73.600 12.240 +*N prog_clk[0]:214 *C 75.208 9.520 +*N prog_clk[0]:215 *C 73.645 9.520 +*N prog_clk[0]:216 *C 73.600 9.520 +*N prog_clk[0]:217 *C 73.600 7.538 +*N prog_clk[0]:218 *C 73.600 7.480 +*N prog_clk[0]:219 *C 55.005 14.960 +*N prog_clk[0]:220 *C 54.740 14.960 +*N prog_clk[0]:221 *C 84.445 47.600 +*N prog_clk[0]:222 *C 84.640 47.600 +*N prog_clk[0]:223 *C 84.640 47.600 +*N prog_clk[0]:224 *C 84.633 47.600 +*N prog_clk[0]:225 *C 83.720 47.600 +*N prog_clk[0]:226 *C 87.205 50.320 +*N prog_clk[0]:227 *C 87.400 50.320 +*N prog_clk[0]:228 *C 87.400 50.320 +*N prog_clk[0]:229 *C 87.392 50.320 +*N prog_clk[0]:230 *C 102.808 82.960 +*N prog_clk[0]:231 *C 101.705 82.960 +*N prog_clk[0]:232 *C 101.660 82.960 +*N prog_clk[0]:233 *C 101.653 82.960 +*N prog_clk[0]:234 *C 93.848 82.960 +*N prog_clk[0]:235 *C 93.840 82.960 +*N prog_clk[0]:236 *C 93.645 82.960 +*N prog_clk[0]:237 *C 93.840 82.620 +*N prog_clk[0]:238 *C 93.840 82.575 +*N prog_clk[0]:239 *C 92.670 80.240 +*N prog_clk[0]:240 *C 92.920 80.240 +*N prog_clk[0]:241 *C 92.920 80.240 +*N prog_clk[0]:242 *C 93.840 80.240 +*N prog_clk[0]:243 *C 108.328 69.360 +*N prog_clk[0]:244 *C 107.225 69.360 +*N prog_clk[0]:245 *C 107.180 69.360 +*N prog_clk[0]:246 *C 107.172 69.360 +*N prog_clk[0]:247 *C 93.848 69.360 +*N prog_clk[0]:248 *C 93.840 69.360 +*N prog_clk[0]:249 *C 94.105 66.640 +*N prog_clk[0]:250 *C 93.840 66.640 +*N prog_clk[0]:251 *C 93.840 66.640 +*N prog_clk[0]:252 *C 93.833 66.640 +*N prog_clk[0]:253 *C 87.205 69.360 +*N prog_clk[0]:254 *C 87.400 69.360 +*N prog_clk[0]:255 *C 87.400 69.315 +*N prog_clk[0]:256 *C 87.400 66.698 +*N prog_clk[0]:257 *C 87.400 66.640 +*N prog_clk[0]:258 *C 83.728 66.640 +*N prog_clk[0]:259 *C 83.720 66.583 +*N prog_clk[0]:260 *C 82.100 58.480 +*N prog_clk[0]:261 *C 82.340 58.480 +*N prog_clk[0]:262 *C 82.340 58.480 +*N prog_clk[0]:263 *C 83.720 58.480 +*N prog_clk[0]:264 *C 83.720 50.378 +*N prog_clk[0]:265 *C 83.728 50.320 +*N prog_clk[0]:266 *C 83.720 50.312 +*N prog_clk[0]:267 *C 83.720 48.288 +*N prog_clk[0]:268 *C 83.720 48.275 +*N prog_clk[0]:269 *C 73.405 53.040 +*N prog_clk[0]:270 *C 73.600 53.040 +*N prog_clk[0]:271 *C 73.600 52.995 +*N prog_clk[0]:272 *C 73.600 48.338 +*N prog_clk[0]:273 *C 73.600 48.280 +*N prog_clk[0]:274 *C 71.308 48.280 +*N prog_clk[0]:275 *C 71.300 48.223 +*N prog_clk[0]:276 *C 71.565 44.880 +*N prog_clk[0]:277 *C 71.300 44.540 +*N prog_clk[0]:278 *C 71.270 44.570 +*N prog_clk[0]:279 *C 71.255 44.880 +*N prog_clk[0]:280 *C 70.840 44.880 +*N prog_clk[0]:281 *C 70.840 42.898 +*N prog_clk[0]:282 *C 70.833 42.840 +*N prog_clk[0]:283 *C 69.008 42.840 +*N prog_clk[0]:284 *C 69.000 42.782 +*N prog_clk[0]:285 *C 69.265 36.720 +*N prog_clk[0]:286 *C 69.000 37.060 +*N prog_clk[0]:287 *C 69.000 37.060 +*N prog_clk[0]:288 *C 69.265 34.000 +*N prog_clk[0]:289 *C 69.000 33.660 +*N prog_clk[0]:290 *C 69.000 33.660 +*N prog_clk[0]:291 *C 69.000 32.698 +*N prog_clk[0]:292 *C 68.993 32.640 +*N prog_clk[0]:293 *C 64.407 32.640 +*N prog_clk[0]:294 *C 64.400 32.583 +*N prog_clk[0]:295 *C 64.205 28.560 +*N prog_clk[0]:296 *C 64.400 28.220 +*N prog_clk[0]:297 *C 64.400 28.220 +*N prog_clk[0]:298 *C 64.400 27.258 +*N prog_clk[0]:299 *C 64.392 27.200 +*N prog_clk[0]:300 *C 62.568 27.200 +*N prog_clk[0]:301 *C 62.560 27.143 +*N prog_clk[0]:302 *C 60.550 23.120 +*N prog_clk[0]:303 *C 60.720 22.440 +*N prog_clk[0]:304 *C 62.515 22.440 +*N prog_clk[0]:305 *C 62.560 22.440 +*N prog_clk[0]:306 *C 66.505 20.400 +*N prog_clk[0]:307 *C 66.240 20.400 +*N prog_clk[0]:308 *C 66.240 20.400 +*N prog_clk[0]:309 *C 66.233 20.400 +*N prog_clk[0]:310 *C 62.568 20.400 +*N prog_clk[0]:311 *C 62.560 20.400 +*N prog_clk[0]:312 *C 63.745 14.960 +*N prog_clk[0]:313 *C 63.480 14.960 +*N prog_clk[0]:314 *C 63.480 14.960 +*N prog_clk[0]:315 *C 62.560 14.960 +*N prog_clk[0]:316 *C 62.553 14.960 +*N prog_clk[0]:317 *C 54.748 14.960 +*N prog_clk[0]:318 *C 54.740 14.960 +*N prog_clk[0]:319 *C 54.085 17.680 +*N prog_clk[0]:320 *C 54.280 17.680 +*N prog_clk[0]:321 *C 54.280 17.635 +*N prog_clk[0]:322 *C 54.280 14.960 +*N prog_clk[0]:323 *C 54.280 7.538 +*N prog_clk[0]:324 *C 54.280 7.480 +*N prog_clk[0]:325 *C 41.860 7.480 +*N prog_clk[0]:326 *C 33.385 23.120 +*N prog_clk[0]:327 *C 33.120 23.120 +*N prog_clk[0]:328 *C 33.120 23.120 +*N prog_clk[0]:329 *C 17.745 72.080 +*N prog_clk[0]:330 *C 17.940 72.080 +*N prog_clk[0]:331 *C 17.940 72.080 +*N prog_clk[0]:332 *C 17.948 72.080 +*N prog_clk[0]:333 *C 23.725 74.800 +*N prog_clk[0]:334 *C 23.920 74.800 +*N prog_clk[0]:335 *C 23.920 74.755 +*N prog_clk[0]:336 *C 23.920 72.138 +*N prog_clk[0]:337 *C 23.920 72.080 +*N prog_clk[0]:338 *C 29.893 72.080 +*N prog_clk[0]:339 *C 29.900 72.080 +*N prog_clk[0]:340 *C 29.705 72.080 +*N prog_clk[0]:341 *C 29.900 71.740 +*N prog_clk[0]:342 *C 29.900 71.695 +*N prog_clk[0]:343 *C 29.900 68.680 +*N prog_clk[0]:344 *C 33.385 69.360 +*N prog_clk[0]:345 *C 33.120 69.360 +*N prog_clk[0]:346 *C 33.120 69.360 +*N prog_clk[0]:347 *C 33.113 69.360 +*N prog_clk[0]:348 *C 30.360 69.360 +*N prog_clk[0]:349 *C 30.360 68.688 +*N prog_clk[0]:350 *C 30.360 68.623 +*N prog_clk[0]:351 *C 25.105 58.480 +*N prog_clk[0]:352 *C 25.300 58.480 +*N prog_clk[0]:353 *C 25.300 58.480 +*N prog_clk[0]:354 *C 25.308 58.480 +*N prog_clk[0]:355 *C 30.353 58.480 +*N prog_clk[0]:356 *C 30.360 58.480 +*N prog_clk[0]:357 *C 31.508 53.040 +*N prog_clk[0]:358 *C 30.360 53.040 +*N prog_clk[0]:359 *C 30.360 53.380 +*N prog_clk[0]:360 *C 30.360 53.380 +*N prog_clk[0]:361 *C 42.125 47.600 +*N prog_clk[0]:362 *C 41.860 47.600 +*N prog_clk[0]:363 *C 41.860 47.600 +*N prog_clk[0]:364 *C 41.852 47.600 +*N prog_clk[0]:365 *C 40.480 47.600 +*N prog_clk[0]:366 *C 64.205 85.680 +*N prog_clk[0]:367 *C 64.400 85.680 +*N prog_clk[0]:368 *C 64.400 85.635 +*N prog_clk[0]:369 *C 64.400 80.240 +*N prog_clk[0]:370 *C 79.808 80.240 +*N prog_clk[0]:371 *C 79.165 80.240 +*N prog_clk[0]:372 *C 79.120 80.240 +*N prog_clk[0]:373 *C 79.112 80.240 +*N prog_clk[0]:374 *C 71.565 82.960 +*N prog_clk[0]:375 *C 71.760 82.960 +*N prog_clk[0]:376 *C 71.760 82.915 +*N prog_clk[0]:377 *C 71.760 80.297 +*N prog_clk[0]:378 *C 71.760 80.240 +*N prog_clk[0]:379 *C 66.045 80.240 +*N prog_clk[0]:380 *C 66.240 80.240 +*N prog_clk[0]:381 *C 66.240 80.240 +*N prog_clk[0]:382 *C 66.240 80.240 +*N prog_clk[0]:383 *C 64.868 80.240 +*N prog_clk[0]:384 *C 64.860 80.183 +*N prog_clk[0]:385 *C 74.785 66.640 +*N prog_clk[0]:386 *C 74.520 66.640 +*N prog_clk[0]:387 *C 74.520 66.640 +*N prog_clk[0]:388 *C 74.513 66.640 +*N prog_clk[0]:389 *C 69.920 66.640 +*N prog_clk[0]:390 *C 69.725 69.360 +*N prog_clk[0]:391 *C 69.920 69.360 +*N prog_clk[0]:392 *C 69.920 69.315 +*N prog_clk[0]:393 *C 69.920 67.377 +*N prog_clk[0]:394 *C 69.920 67.312 +*N prog_clk[0]:395 *C 64.868 67.320 +*N prog_clk[0]:396 *C 64.860 67.377 +*N prog_clk[0]:397 *C 64.400 67.320 +*N prog_clk[0]:398 *C 64.665 53.040 +*N prog_clk[0]:399 *C 64.400 53.040 +*N prog_clk[0]:400 *C 64.400 53.040 +*N prog_clk[0]:401 *C 64.392 53.040 +*N prog_clk[0]:402 *C 59.605 58.480 +*N prog_clk[0]:403 *C 59.340 58.480 +*N prog_clk[0]:404 *C 59.340 58.435 +*N prog_clk[0]:405 *C 59.340 53.098 +*N prog_clk[0]:406 *C 59.340 53.040 +*N prog_clk[0]:407 *C 50.405 55.760 +*N prog_clk[0]:408 *C 50.140 55.760 +*N prog_clk[0]:409 *C 50.140 55.715 +*N prog_clk[0]:410 *C 50.140 53.098 +*N prog_clk[0]:411 *C 50.140 53.040 +*N prog_clk[0]:412 *C 44.885 53.040 +*N prog_clk[0]:413 *C 44.620 53.040 +*N prog_clk[0]:414 *C 44.620 53.040 +*N prog_clk[0]:415 *C 44.620 53.040 +*N prog_clk[0]:416 *C 43.240 53.040 +*N prog_clk[0]:417 *C 47.148 63.920 +*N prog_clk[0]:418 *C 46.505 63.920 +*N prog_clk[0]:419 *C 46.460 63.875 +*N prog_clk[0]:420 *C 46.460 61.258 +*N prog_clk[0]:421 *C 46.453 61.200 +*N prog_clk[0]:422 *C 44.885 61.200 +*N prog_clk[0]:423 *C 44.620 61.200 +*N prog_clk[0]:424 *C 44.620 61.200 +*N prog_clk[0]:425 *C 44.620 61.200 +*N prog_clk[0]:426 *C 43.045 80.240 +*N prog_clk[0]:427 *C 43.240 80.240 +*N prog_clk[0]:428 *C 43.240 80.195 +*N prog_clk[0]:429 *C 50.865 85.680 +*N prog_clk[0]:430 *C 51.060 85.680 +*N prog_clk[0]:431 *C 51.060 85.635 +*N prog_clk[0]:432 *C 50.865 77.520 +*N prog_clk[0]:433 *C 51.060 77.520 +*N prog_clk[0]:434 *C 51.060 77.520 +*N prog_clk[0]:435 *C 51.053 77.520 +*N prog_clk[0]:436 *C 43.248 77.520 +*N prog_clk[0]:437 *C 43.240 77.520 +*N prog_clk[0]:438 *C 42.585 72.080 +*N prog_clk[0]:439 *C 42.780 71.740 +*N prog_clk[0]:440 *C 43.195 71.740 +*N prog_clk[0]:441 *C 43.240 71.740 +*N prog_clk[0]:442 *C 43.240 61.258 +*N prog_clk[0]:443 *C 43.248 61.200 +*N prog_clk[0]:444 *C 43.240 61.193 +*N prog_clk[0]:445 *C 43.240 53.727 +*N prog_clk[0]:446 *C 43.240 53.715 +*N prog_clk[0]:447 *C 38.445 55.760 +*N prog_clk[0]:448 *C 38.180 55.760 +*N prog_clk[0]:449 *C 38.180 55.715 +*N prog_clk[0]:450 *C 38.180 53.778 +*N prog_clk[0]:451 *C 38.188 53.720 +*N prog_clk[0]:452 *C 40.480 53.720 +*N prog_clk[0]:453 *C 40.480 53.663 +*N prog_clk[0]:454 *C 40.480 48.338 +*N prog_clk[0]:455 *C 40.480 48.273 +*N prog_clk[0]:456 *C 33.385 50.320 +*N prog_clk[0]:457 *C 33.580 50.320 +*N prog_clk[0]:458 *C 33.580 50.275 +*N prog_clk[0]:459 *C 33.580 48.338 +*N prog_clk[0]:460 *C 33.580 48.280 +*N prog_clk[0]:461 *C 30.360 48.280 +*N prog_clk[0]:462 *C 17.285 61.200 +*N prog_clk[0]:463 *C 16.365 63.920 +*N prog_clk[0]:464 *C 16.560 63.920 +*N prog_clk[0]:465 *C 16.560 63.875 +*N prog_clk[0]:466 *C 16.560 60.905 +*N prog_clk[0]:467 *C 16.605 60.860 +*N prog_clk[0]:468 *C 17.480 60.860 +*N prog_clk[0]:469 *C 17.895 60.860 +*N prog_clk[0]:470 *C 17.940 60.815 +*N prog_clk[0]:471 *C 17.940 56.100 +*N prog_clk[0]:472 *C 18.860 56.100 +*N prog_clk[0]:473 *C 18.665 53.040 +*N prog_clk[0]:474 *C 18.860 53.380 +*N prog_clk[0]:475 *C 18.860 53.380 +*N prog_clk[0]:476 *C 18.860 47.600 +*N prog_clk[0]:477 *C 20.505 47.600 +*N prog_clk[0]:478 *C 20.240 47.600 +*N prog_clk[0]:479 *C 20.240 47.600 +*N prog_clk[0]:480 *C 20.248 47.600 +*N prog_clk[0]:481 *C 30.360 47.608 +*N prog_clk[0]:482 *C 30.360 47.600 +*N prog_clk[0]:483 *C 30.360 39.440 +*N prog_clk[0]:484 *C 29.705 39.440 +*N prog_clk[0]:485 *C 29.900 39.440 +*N prog_clk[0]:486 *C 29.900 39.440 +*N prog_clk[0]:487 *C 29.900 32.698 +*N prog_clk[0]:488 *C 29.900 32.633 +*N prog_clk[0]:489 *C 13.605 36.720 +*N prog_clk[0]:490 *C 13.800 36.720 +*N prog_clk[0]:491 *C 13.800 36.675 +*N prog_clk[0]:492 *C 13.605 31.280 +*N prog_clk[0]:493 *C 13.800 31.280 +*N prog_clk[0]:494 *C 13.800 31.325 +*N prog_clk[0]:495 *C 13.800 31.960 +*N prog_clk[0]:496 *C 13.808 31.960 +*N prog_clk[0]:497 *C 29.900 31.960 +*N prog_clk[0]:498 *C 32.653 31.960 +*N prog_clk[0]:499 *C 32.660 31.902 +*N prog_clk[0]:500 *C 32.660 23.120 +*N prog_clk[0]:501 *C 45.308 17.680 +*N prog_clk[0]:502 *C 44.665 17.680 +*N prog_clk[0]:503 *C 44.620 17.680 +*N prog_clk[0]:504 *C 44.613 17.680 +*N prog_clk[0]:505 *C 40.480 17.680 +*N prog_clk[0]:506 *C 43.008 25.840 +*N prog_clk[0]:507 *C 41.905 25.840 +*N prog_clk[0]:508 *C 41.860 25.840 +*N prog_clk[0]:509 *C 41.852 25.840 +*N prog_clk[0]:510 *C 39.825 39.440 +*N prog_clk[0]:511 *C 40.020 39.440 +*N prog_clk[0]:512 *C 40.020 39.395 +*N prog_clk[0]:513 *C 58.188 39.440 +*N prog_clk[0]:514 *C 57.545 39.440 +*N prog_clk[0]:515 *C 57.500 39.440 +*N prog_clk[0]:516 *C 57.492 39.440 +*N prog_clk[0]:517 *C 51.988 39.440 +*N prog_clk[0]:518 *C 51.980 39.383 +*N prog_clk[0]:519 *C 52.245 36.720 +*N prog_clk[0]:520 *C 51.980 37.060 +*N prog_clk[0]:521 *C 51.980 37.060 +*N prog_clk[0]:522 *C 51.980 34.738 +*N prog_clk[0]:523 *C 51.973 34.680 +*N prog_clk[0]:524 *C 50.405 34.000 +*N prog_clk[0]:525 *C 50.140 34.000 +*N prog_clk[0]:526 *C 50.140 34.045 +*N prog_clk[0]:527 *C 50.140 34.623 +*N prog_clk[0]:528 *C 50.140 34.680 +*N prog_clk[0]:529 *C 48.105 42.160 +*N prog_clk[0]:530 *C 48.300 42.160 +*N prog_clk[0]:531 *C 48.300 42.115 +*N prog_clk[0]:532 *C 48.300 34.738 +*N prog_clk[0]:533 *C 48.300 34.680 +*N prog_clk[0]:534 *C 40.028 34.680 +*N prog_clk[0]:535 *C 40.020 34.680 +*N prog_clk[0]:536 *C 39.825 31.280 +*N prog_clk[0]:537 *C 40.020 31.620 +*N prog_clk[0]:538 *C 40.020 31.620 +*N prog_clk[0]:539 *C 40.020 25.898 +*N prog_clk[0]:540 *C 40.023 25.840 +*N prog_clk[0]:541 *C 40.500 25.840 +*N prog_clk[0]:542 *C 40.480 25.832 +*N prog_clk[0]:543 *C 40.480 18.367 +*N prog_clk[0]:544 *C 40.480 18.355 +*N prog_clk[0]:545 *C 32.668 18.360 +*N prog_clk[0]:546 *C 32.660 18.360 +*N prog_clk[0]:547 *C 31.498 14.982 +*N prog_clk[0]:548 *C 31.740 14.995 +*N prog_clk[0]:549 *C 31.740 15.300 +*N prog_clk[0]:550 *C 32.155 15.300 +*N prog_clk[0]:551 *C 32.200 15.300 +*N prog_clk[0]:552 *C 32.660 15.300 +*N prog_clk[0]:553 *C 33.845 12.240 +*N prog_clk[0]:554 *C 33.580 12.240 +*N prog_clk[0]:555 *C 33.580 12.240 +*N prog_clk[0]:556 *C 33.573 12.240 +*N prog_clk[0]:557 *C 32.668 12.240 +*N prog_clk[0]:558 *C 32.660 12.240 +*N prog_clk[0]:559 *C 32.660 7.538 +*N prog_clk[0]:560 *C 32.660 7.480 +*N prog_clk[0]:561 *C 30.828 7.480 +*N prog_clk[0]:562 *C 30.820 7.423 + +*CAP +0 prog_clk[0] 0.0002562603 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +4 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +5 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +7 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +8 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +9 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +10 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +12 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +13 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +14 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +15 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +16 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +18 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +19 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +21 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +22 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +23 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +24 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +25 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +27 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +28 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +29 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +32 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +33 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +35 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +37 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +39 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +40 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +41 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +42 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +43 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +44 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +46 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +47 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +49 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +50 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +51 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +52 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +53 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +54 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +55 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +56 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +57 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +58 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +59 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +60 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +61 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +63 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +64 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +65 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +66 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +67 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +68 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +69 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +70 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +71 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +72 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +73 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +74 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +75 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +76 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +77 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +78 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +79 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +80 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +81 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +82 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +83 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +84 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +85 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +86 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +87 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +88 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +89 prog_clk[0]:89 5.93572e-05 +90 prog_clk[0]:90 6.145915e-05 +91 prog_clk[0]:91 0.0001178127 +92 prog_clk[0]:92 6.316807e-05 +93 prog_clk[0]:93 5.603139e-05 +94 prog_clk[0]:94 0.000155038 +95 prog_clk[0]:95 6.06206e-05 +96 prog_clk[0]:96 4.73125e-05 +97 prog_clk[0]:97 5.137276e-05 +98 prog_clk[0]:98 8.771958e-05 +99 prog_clk[0]:99 8.771958e-05 +100 prog_clk[0]:100 0.000183146 +101 prog_clk[0]:101 4.785935e-05 +102 prog_clk[0]:102 5.446556e-05 +103 prog_clk[0]:103 3.658798e-05 +104 prog_clk[0]:104 0.0003181654 +105 prog_clk[0]:105 0.0003181654 +106 prog_clk[0]:106 0.0001631599 +107 prog_clk[0]:107 6.332263e-05 +108 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bottom_left_grid_pin_34_[0]:23 1.497959e-06 +749 prog_clk[0]:498 bottom_left_grid_pin_34_[0]:25 5.920108e-05 +750 prog_clk[0]:498 bottom_left_grid_pin_34_[0]:26 3.112628e-06 +751 prog_clk[0]:498 bottom_left_grid_pin_34_[0]:29 5.77882e-06 +752 prog_clk[0]:159 bottom_left_grid_pin_34_[0]:19 9.971901e-06 +753 prog_clk[0]:533 bottom_left_grid_pin_34_[0]:25 2.600595e-06 +754 prog_clk[0]:533 bottom_left_grid_pin_34_[0]:20 1.93852e-07 +755 prog_clk[0]:350 bottom_left_grid_pin_34_[0]:8 2.407458e-05 +756 prog_clk[0]:194 bottom_left_grid_pin_34_[0]:19 7.28662e-06 +757 prog_clk[0]:194 bottom_left_grid_pin_34_[0]:20 0.0005394989 +758 prog_clk[0]:356 bottom_left_grid_pin_34_[0]:8 5.116871e-05 +759 prog_clk[0]:356 bottom_left_grid_pin_34_[0]:11 2.407458e-05 +760 prog_clk[0]:360 bottom_left_grid_pin_34_[0]:8 4.273442e-05 +761 prog_clk[0]:360 bottom_left_grid_pin_34_[0]:11 7.868066e-05 +762 prog_clk[0]:528 bottom_left_grid_pin_34_[0]:25 6.063015e-06 +763 prog_clk[0]:528 bottom_left_grid_pin_34_[0]:20 2.600595e-06 +764 prog_clk[0]:523 bottom_left_grid_pin_34_[0]:20 6.063015e-06 +765 prog_clk[0]:483 bottom_left_grid_pin_34_[0]:12 9.635321e-06 +766 prog_clk[0]:500 bottom_left_grid_pin_34_[0]:24 1.497959e-06 +767 prog_clk[0]:497 bottom_left_grid_pin_34_[0]:27 3.112628e-06 +768 prog_clk[0]:497 bottom_left_grid_pin_34_[0]:28 1.628142e-05 +769 prog_clk[0]:497 bottom_left_grid_pin_34_[0]:25 2.871662e-06 +770 prog_clk[0]:497 bottom_left_grid_pin_34_[0]:26 7.184613e-05 +771 prog_clk[0]:497 bottom_left_grid_pin_34_[0]:29 1.195345e-05 +772 prog_clk[0]:461 bottom_left_grid_pin_34_[0]:11 9.160841e-06 +773 prog_clk[0]:482 bottom_left_grid_pin_35_[0]:18 4.576787e-05 +774 prog_clk[0]:482 bottom_left_grid_pin_35_[0]:13 7.938994e-09 +775 prog_clk[0]:487 bottom_left_grid_pin_35_[0]:21 6.57484e-05 +776 prog_clk[0]:487 bottom_left_grid_pin_35_[0]:22 0.0001187001 +777 prog_clk[0]:218 bottom_left_grid_pin_35_[0]:25 0.0001322161 +778 prog_clk[0]:218 bottom_left_grid_pin_35_[0]:10 0.000553112 +779 prog_clk[0]:559 bottom_left_grid_pin_35_[0] 1.584735e-05 +780 prog_clk[0]:560 bottom_left_grid_pin_35_[0]:25 0.000217655 +781 prog_clk[0]:560 bottom_left_grid_pin_35_[0]:10 4.515592e-05 +782 prog_clk[0]:131 bottom_left_grid_pin_35_[0]:9 0.0001749759 +783 prog_clk[0]:131 bottom_left_grid_pin_35_[0]:10 0.0001322161 +784 prog_clk[0]:496 bottom_left_grid_pin_35_[0]:22 5.232433e-06 +785 prog_clk[0]:324 bottom_left_grid_pin_35_[0]:25 0.0003781361 +786 prog_clk[0]:324 bottom_left_grid_pin_35_[0]:10 0.0002751785 +787 prog_clk[0]:350 bottom_left_grid_pin_35_[0]:13 8.528598e-07 +788 prog_clk[0]:356 bottom_left_grid_pin_35_[0]:14 8.528598e-07 +789 prog_clk[0]:356 bottom_left_grid_pin_35_[0]:13 3.497606e-07 +790 prog_clk[0]:459 bottom_left_grid_pin_35_[0]:14 6.119796e-05 +791 prog_clk[0]:458 bottom_left_grid_pin_35_[0]:13 6.119796e-05 +792 prog_clk[0]:360 bottom_left_grid_pin_35_[0]:14 3.497606e-07 +793 prog_clk[0]:486 bottom_left_grid_pin_35_[0]:18 6.57484e-05 +794 prog_clk[0]:486 bottom_left_grid_pin_35_[0]:21 0.0001187001 +795 prog_clk[0]:558 bottom_left_grid_pin_35_[0]:26 1.584735e-05 +796 prog_clk[0]:557 bottom_left_grid_pin_35_[0]:25 9.341728e-06 +797 prog_clk[0]:556 bottom_left_grid_pin_35_[0]:10 9.341728e-06 +798 prog_clk[0]:561 bottom_left_grid_pin_35_[0]:25 4.515592e-05 +799 prog_clk[0]:483 bottom_left_grid_pin_35_[0]:21 4.576787e-05 +800 prog_clk[0]:483 bottom_left_grid_pin_35_[0]:14 7.938994e-09 +801 prog_clk[0]:497 bottom_left_grid_pin_35_[0]:23 5.232433e-06 +802 prog_clk[0]:325 bottom_left_grid_pin_35_[0]:25 0.0002751785 +803 prog_clk[0]:325 bottom_left_grid_pin_35_[0]:10 0.000217655 +804 prog_clk[0]:535 bottom_left_grid_pin_36_[0]:16 1.122075e-05 +805 prog_clk[0]:544 bottom_left_grid_pin_36_[0]:25 1.783398e-05 +806 prog_clk[0]:111 bottom_left_grid_pin_36_[0]:9 2.224131e-05 +807 prog_clk[0]:111 bottom_left_grid_pin_36_[0]:10 1.717346e-05 +808 prog_clk[0]:546 bottom_left_grid_pin_36_[0]:21 3.619994e-06 +809 prog_clk[0]:112 bottom_left_grid_pin_36_[0]:10 2.224131e-05 +810 prog_clk[0]:201 bottom_left_grid_pin_36_[0]:11 0.000144784 +811 prog_clk[0]:201 bottom_left_grid_pin_36_[0]:10 0.0001064698 +812 prog_clk[0]:512 bottom_left_grid_pin_36_[0]:15 1.122075e-05 +813 prog_clk[0]:135 bottom_left_grid_pin_36_[0]:9 7.380972e-05 +814 prog_clk[0]:135 bottom_left_grid_pin_36_[0]:10 0.000370179 +815 prog_clk[0]:560 bottom_left_grid_pin_36_[0] 0.0002730921 +816 prog_clk[0]:560 bottom_left_grid_pin_36_[0]:27 0.0001205457 +817 prog_clk[0]:499 bottom_left_grid_pin_36_[0]:20 2.54593e-06 +818 prog_clk[0]:202 bottom_left_grid_pin_36_[0]:11 0.0001064698 +819 prog_clk[0]:310 bottom_left_grid_pin_36_[0]:11 0.0002205884 +820 prog_clk[0]:309 bottom_left_grid_pin_36_[0]:10 0.0002205884 +821 prog_clk[0]:139 bottom_left_grid_pin_36_[0]:11 0.000370179 +822 prog_clk[0]:139 bottom_left_grid_pin_36_[0]:10 0.0002185937 +823 prog_clk[0]:100 bottom_left_grid_pin_36_[0]:9 1.717346e-05 +824 prog_clk[0]:561 bottom_left_grid_pin_36_[0] 0.0001205457 +825 prog_clk[0]:500 bottom_left_grid_pin_36_[0]:20 3.619994e-06 +826 prog_clk[0]:500 bottom_left_grid_pin_36_[0]:21 2.54593e-06 +827 prog_clk[0]:325 bottom_left_grid_pin_36_[0]:27 0.0002730921 +828 prog_clk[0]:505 bottom_left_grid_pin_36_[0]:26 1.783398e-05 +829 prog_clk[0] bottom_left_grid_pin_37_[0]:27 5.959802e-05 +830 prog_clk[0]:487 bottom_left_grid_pin_37_[0]:13 5.288864e-06 +831 prog_clk[0]:488 bottom_left_grid_pin_37_[0]:10 6.649779e-06 +832 prog_clk[0]:546 bottom_left_grid_pin_37_[0]:26 3.493543e-05 +833 prog_clk[0]:546 bottom_left_grid_pin_37_[0]:27 5.001002e-05 +834 prog_clk[0]:299 bottom_left_grid_pin_37_[0]:20 1.934086e-05 +835 prog_clk[0]:300 bottom_left_grid_pin_37_[0]:21 1.934086e-05 +836 prog_clk[0]:559 bottom_left_grid_pin_37_[0]:27 6.506656e-05 +837 prog_clk[0]:560 bottom_left_grid_pin_37_[0]:28 4.733115e-07 +838 prog_clk[0]:499 bottom_left_grid_pin_37_[0]:26 5.750001e-06 +839 prog_clk[0]:486 bottom_left_grid_pin_37_[0]:8 2.307428e-05 +840 prog_clk[0]:486 bottom_left_grid_pin_37_[0]:10 5.288864e-06 +841 prog_clk[0]:558 bottom_left_grid_pin_37_[0]:26 6.506656e-05 +842 prog_clk[0]:558 bottom_left_grid_pin_37_[0]:27 3.777793e-05 +843 prog_clk[0]:562 bottom_left_grid_pin_37_[0]:26 5.959802e-05 +844 prog_clk[0]:561 bottom_left_grid_pin_37_[0] 4.733115e-07 +845 prog_clk[0]:483 bottom_left_grid_pin_37_[0]:9 2.307428e-05 +846 prog_clk[0]:552 bottom_left_grid_pin_37_[0]:26 3.777793e-05 +847 prog_clk[0]:552 bottom_left_grid_pin_37_[0]:27 3.493543e-05 +848 prog_clk[0]:500 bottom_left_grid_pin_37_[0]:26 5.001002e-05 +849 prog_clk[0]:500 bottom_left_grid_pin_37_[0]:27 5.750001e-06 +850 prog_clk[0]:497 bottom_left_grid_pin_37_[0]:13 6.649779e-06 +851 prog_clk[0]:482 bottom_left_grid_pin_40_[0]:15 1.002414e-05 +852 prog_clk[0]:487 bottom_left_grid_pin_40_[0]:20 2.196817e-06 +853 prog_clk[0]:487 bottom_left_grid_pin_40_[0]:16 1.752705e-06 +854 prog_clk[0]:488 bottom_left_grid_pin_40_[0]:17 7.858656e-06 +855 prog_clk[0]:541 bottom_left_grid_pin_40_[0]:12 8.24815e-06 +856 prog_clk[0]:541 bottom_left_grid_pin_40_[0]:23 8.672239e-06 +857 prog_clk[0]:540 bottom_left_grid_pin_40_[0]:23 8.24815e-06 +858 prog_clk[0]:499 bottom_left_grid_pin_40_[0]:20 5.097573e-05 +859 prog_clk[0]:499 bottom_left_grid_pin_40_[0]:17 0.0001669295 +860 prog_clk[0]:486 bottom_left_grid_pin_40_[0]:15 1.752705e-06 +861 prog_clk[0]:486 bottom_left_grid_pin_40_[0]:17 2.196817e-06 +862 prog_clk[0]:509 bottom_left_grid_pin_40_[0]:12 8.672239e-06 +863 prog_clk[0]:557 bottom_left_grid_pin_40_[0] 4.501121e-05 +864 prog_clk[0]:556 bottom_left_grid_pin_40_[0]:26 4.501121e-05 +865 prog_clk[0]:483 bottom_left_grid_pin_40_[0]:16 1.002414e-05 +866 prog_clk[0]:500 bottom_left_grid_pin_40_[0]:20 0.0001669295 +867 prog_clk[0]:500 bottom_left_grid_pin_40_[0]:21 5.097573e-05 +868 prog_clk[0]:497 bottom_left_grid_pin_40_[0]:20 7.858656e-06 +869 prog_clk[0]:317 bottom_left_grid_pin_41_[0]:17 4.294426e-05 +870 prog_clk[0]:316 bottom_left_grid_pin_41_[0]:12 4.294426e-05 +871 prog_clk[0]:487 bottom_left_grid_pin_41_[0]:26 1.023789e-05 +872 prog_clk[0]:544 bottom_left_grid_pin_41_[0]:17 3.228796e-05 +873 prog_clk[0]:545 bottom_left_grid_pin_41_[0]:27 3.228796e-05 +874 prog_clk[0]:491 bottom_left_grid_pin_41_[0]:21 5.562029e-07 +875 prog_clk[0]:195 bottom_left_grid_pin_41_[0]:9 5.078315e-05 +876 prog_clk[0]:292 bottom_left_grid_pin_41_[0]:8 0.0002593952 +877 prog_clk[0]:293 bottom_left_grid_pin_41_[0]:9 0.0002593952 +878 prog_clk[0]:495 bottom_left_grid_pin_41_[0]:22 5.562029e-07 +879 prog_clk[0]:194 bottom_left_grid_pin_41_[0]:8 5.078315e-05 +880 prog_clk[0]:504 bottom_left_grid_pin_41_[0]:17 3.10132e-05 +881 prog_clk[0]:486 bottom_left_grid_pin_41_[0]:25 1.023789e-05 +882 prog_clk[0]:557 bottom_left_grid_pin_41_[0]:27 9.288247e-06 +883 prog_clk[0]:556 bottom_left_grid_pin_41_[0]:17 9.288247e-06 +884 prog_clk[0]:505 bottom_left_grid_pin_41_[0]:27 3.10132e-05 +885 prog_clk[0]:544 chanx_left_in[0]:5 2.55593e-05 +886 prog_clk[0]:539 chanx_left_in[0]:4 3.992579e-05 +887 prog_clk[0]:496 chanx_left_in[0]:7 0.0001969952 +888 prog_clk[0]:538 chanx_left_in[0]:5 3.992579e-05 +889 prog_clk[0]:497 chanx_left_in[0]:6 0.0001969952 +890 prog_clk[0]:505 chanx_left_in[0]:4 2.55593e-05 +891 prog_clk[0]:323 ropt_net_172:9 0.0001186166 +892 prog_clk[0]:322 ropt_net_172:10 0.0001186166 +893 prog_clk[0]:218 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 0.0001529975 +894 prog_clk[0]:324 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 0.0001529975 +895 prog_clk[0]:532 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 3.167526e-06 +896 prog_clk[0]:531 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 3.167526e-06 +897 prog_clk[0]:518 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 6.66481e-05 +898 prog_clk[0]:521 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 6.674675e-05 +899 prog_clk[0]:521 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 6.66481e-05 +900 prog_clk[0]:522 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 6.674675e-05 +901 prog_clk[0]:301 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 1.626457e-06 +902 prog_clk[0]:311 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 1.404603e-05 +903 prog_clk[0]:304 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 3.781642e-05 +904 prog_clk[0]:305 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 1.404603e-05 +905 prog_clk[0]:305 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 1.626457e-06 +906 prog_clk[0]:303 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 3.781642e-05 +907 prog_clk[0]:480 mux_tree_tapbuf_size7_3_sram[1]:9 3.532093e-05 +908 prog_clk[0]:480 mux_tree_tapbuf_size7_3_sram[1]:14 0.0002438484 +909 prog_clk[0]:481 mux_tree_tapbuf_size7_3_sram[1]:15 0.0002438484 +910 prog_clk[0]:481 mux_tree_tapbuf_size7_3_sram[1]:14 3.532093e-05 +911 prog_clk[0]:475 mux_tree_tapbuf_size7_3_sram[1]:13 6.901325e-07 +912 prog_clk[0]:475 mux_tree_tapbuf_size7_3_sram[1]:12 1.971915e-05 +913 prog_clk[0]:472 mux_tree_tapbuf_size7_3_sram[1]:12 6.901325e-07 +914 prog_clk[0]:476 mux_tree_tapbuf_size7_3_sram[1]:13 1.971915e-05 +915 prog_clk[0]:546 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 4.184569e-06 +916 prog_clk[0]:559 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0001334473 +917 prog_clk[0]:558 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 8.170443e-05 +918 prog_clk[0]:558 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0001334473 +919 prog_clk[0]:552 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 4.184569e-06 +920 prog_clk[0]:552 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 8.170443e-05 +921 prog_clk[0]:274 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001322776 +922 prog_clk[0]:268 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002530607 +923 prog_clk[0]:273 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002530607 +924 prog_clk[0]:273 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001322776 +925 prog_clk[0]:405 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.211515e-05 +926 prog_clk[0]:404 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.211515e-05 +927 prog_clk[0]:452 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.156332e-05 +928 prog_clk[0]:452 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 3.439519e-05 +929 prog_clk[0]:446 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 3.439519e-05 +930 prog_clk[0]:451 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.156332e-05 +931 prog_clk[0]:410 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 2.258611e-07 +932 prog_clk[0]:411 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002038476 +933 prog_clk[0]:409 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 2.258611e-07 +934 prog_clk[0]:415 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.393591e-05 +935 prog_clk[0]:415 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002038476 +936 prog_clk[0]:416 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.393591e-05 +937 prog_clk[0]:275 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.535544e-05 +938 prog_clk[0]:281 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.008094e-05 +939 prog_clk[0]:278 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.186211e-06 +940 prog_clk[0]:280 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.164678e-06 +941 prog_clk[0]:280 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.008094e-05 +942 prog_clk[0]:279 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.164678e-06 +943 prog_clk[0]:279 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.186211e-06 +944 prog_clk[0]:279 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.535544e-05 +945 prog_clk[0]:396 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.737958e-05 +946 prog_clk[0]:400 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001273508 +947 prog_clk[0]:384 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.737958e-05 +948 prog_clk[0]:397 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001273508 +949 prog_clk[0]:111 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.029372e-06 +950 prog_clk[0]:113 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.373411e-05 +951 prog_clk[0]:112 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.029372e-06 +952 prog_clk[0]:116 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.373411e-05 +953 prog_clk[0]:116 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.04214e-05 +954 prog_clk[0]:126 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.74598e-05 +955 prog_clk[0]:120 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.04214e-05 +956 prog_clk[0]:120 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.74598e-05 +957 prog_clk[0]:535 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.514343e-05 +958 prog_clk[0]:539 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.77683e-05 +959 prog_clk[0]:538 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.77683e-05 +960 prog_clk[0]:538 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.514343e-05 +961 prog_clk[0]:216 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 2.218261e-06 +962 prog_clk[0]:216 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.39733e-07 +963 prog_clk[0]:317 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0001200409 +964 prog_clk[0]:315 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.436918e-06 +965 prog_clk[0]:316 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001200409 +966 prog_clk[0]:217 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.39733e-07 +967 prog_clk[0]:213 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.218261e-06 +968 prog_clk[0]:314 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.436918e-06 +969 prog_clk[0]:502 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 3.838246e-06 +970 prog_clk[0]:501 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 3.838246e-06 +971 prog_clk[0]:535 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 9.241498e-06 +972 prog_clk[0]:543 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.968319e-05 +973 prog_clk[0]:542 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 8.968319e-05 +974 prog_clk[0]:512 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 9.241498e-06 +975 prog_clk[0]:94 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.529751e-05 +976 prog_clk[0]:91 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.529751e-05 +977 prog_clk[0]:475 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001378448 +978 prog_clk[0]:475 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.617069e-05 +979 prog_clk[0]:472 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.617069e-05 +980 prog_clk[0]:476 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001378448 +981 prog_clk[0]:446 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 2.103808e-05 +982 prog_clk[0]:218 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.668565e-05 +983 prog_clk[0]:323 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.070065e-07 +984 prog_clk[0]:324 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.571008e-05 +985 prog_clk[0]:324 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.668565e-05 +986 prog_clk[0]:532 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 5.854629e-05 +987 prog_clk[0]:531 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 5.854629e-05 +988 prog_clk[0]:420 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 3.448215e-05 +989 prog_clk[0]:419 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.448215e-05 +990 prog_clk[0]:322 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.070065e-07 +991 prog_clk[0]:325 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.571008e-05 +992 prog_clk[0]:416 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 2.103808e-05 +993 prog_clk[0]:338 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001024079 +994 prog_clk[0]:337 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001024079 +995 prog_clk[0]:337 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001050368 +996 prog_clk[0]:347 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.406261e-06 +997 prog_clk[0]:332 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001050368 +998 prog_clk[0]:348 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.406261e-06 + +*RES +0 prog_clk[0] prog_clk[0]:562 0.005475447 +1 prog_clk[0]:367 prog_clk[0]:366 0.0001059783 +2 prog_clk[0]:368 prog_clk[0]:367 0.0045 +3 prog_clk[0]:366 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +4 prog_clk[0]:430 prog_clk[0]:429 0.0001059783 +5 prog_clk[0]:431 prog_clk[0]:430 0.0045 +6 prog_clk[0]:429 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +7 prog_clk[0]:275 prog_clk[0]:274 0.00341 +8 prog_clk[0]:274 prog_clk[0]:273 0.0003591583 +9 prog_clk[0]:189 prog_clk[0]:188 0.002377232 +10 prog_clk[0]:190 prog_clk[0]:189 0.00341 +11 prog_clk[0]:535 prog_clk[0]:534 0.00341 +12 prog_clk[0]:535 prog_clk[0]:512 0.004209822 +13 prog_clk[0]:534 prog_clk[0]:533 0.001296025 +14 prog_clk[0]:215 prog_clk[0]:214 0.001395089 +15 prog_clk[0]:216 prog_clk[0]:215 0.0045 +16 prog_clk[0]:216 prog_clk[0]:213 0.002428572 +17 prog_clk[0]:214 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +18 prog_clk[0]:318 prog_clk[0]:317 0.00341 +19 prog_clk[0]:318 prog_clk[0]:220 0.0045 +20 prog_clk[0]:317 prog_clk[0]:316 0.001222783 +21 prog_clk[0]:315 prog_clk[0]:314 0.0008214285 +22 prog_clk[0]:315 prog_clk[0]:311 0.004857143 +23 prog_clk[0]:316 prog_clk[0]:315 0.00341 +24 prog_clk[0]:479 prog_clk[0]:478 0.0045 +25 prog_clk[0]:479 prog_clk[0]:476 0.001232143 +26 prog_clk[0]:480 prog_clk[0]:479 0.00341 +27 prog_clk[0]:482 prog_clk[0]:481 0.00341 +28 prog_clk[0]:482 prog_clk[0]:360 0.005160714 +29 prog_clk[0]:481 prog_clk[0]:480 0.001584292 +30 prog_clk[0]:481 prog_clk[0]:461 0.0001053583 +31 prog_clk[0]:265 prog_clk[0]:264 0.00341 +32 prog_clk[0]:265 prog_clk[0]:229 0.0005741834 +33 prog_clk[0]:266 prog_clk[0]:265 0.00341 +34 prog_clk[0]:268 prog_clk[0]:267 0.00341 +35 prog_clk[0]:268 prog_clk[0]:225 0.00010575 +36 prog_clk[0]:267 prog_clk[0]:266 0.00031725 +37 prog_clk[0]:487 prog_clk[0]:486 0.00602009 +38 prog_clk[0]:488 prog_clk[0]:487 0.00341 +39 prog_clk[0]:544 prog_clk[0]:543 0.00341 +40 prog_clk[0]:544 prog_clk[0]:505 0.00010575 +41 prog_clk[0]:543 prog_clk[0]:542 0.001169517 +42 prog_clk[0]:541 prog_clk[0]:540 7.013281e-05 +43 prog_clk[0]:541 prog_clk[0]:509 0.0002118917 +44 prog_clk[0]:542 prog_clk[0]:541 0.00341 +45 prog_clk[0]:453 prog_clk[0]:452 0.00341 +46 prog_clk[0]:452 prog_clk[0]:451 0.0003591583 +47 prog_clk[0]:452 prog_clk[0]:446 0.0004323999 +48 prog_clk[0]:454 prog_clk[0]:453 0.004754464 +49 prog_clk[0]:455 prog_clk[0]:454 0.00341 +50 prog_clk[0]:455 prog_clk[0]:365 0.0001053583 +51 prog_clk[0]:443 prog_clk[0]:442 0.00341 +52 prog_clk[0]:443 prog_clk[0]:425 0.000215025 +53 prog_clk[0]:444 prog_clk[0]:443 0.00341 +54 prog_clk[0]:446 prog_clk[0]:445 0.00341 +55 prog_clk[0]:446 prog_clk[0]:416 0.00010575 +56 prog_clk[0]:445 prog_clk[0]:444 0.001169517 +57 prog_clk[0]:188 prog_clk[0]:187 0.00341 +58 prog_clk[0]:188 prog_clk[0]:141 0.0045 +59 prog_clk[0]:187 prog_clk[0]:186 0.001151892 +60 prog_clk[0]:372 prog_clk[0]:371 0.0045 +61 prog_clk[0]:373 prog_clk[0]:372 0.00341 +62 prog_clk[0]:371 prog_clk[0]:370 0.0005736608 +63 prog_clk[0]:370 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +64 prog_clk[0]:110 prog_clk[0]:109 0.005716518 +65 prog_clk[0]:111 prog_clk[0]:110 0.00341 +66 prog_clk[0]:111 prog_clk[0]:100 0.0007194916 +67 prog_clk[0]:546 prog_clk[0]:545 0.00341 +68 prog_clk[0]:546 prog_clk[0]:500 0.00425 +69 prog_clk[0]:545 prog_clk[0]:544 0.001223958 +70 prog_clk[0]:217 prog_clk[0]:216 0.001770089 +71 prog_clk[0]:218 prog_clk[0]:217 0.00341 +72 prog_clk[0]:218 prog_clk[0]:131 0.002737358 +73 prog_clk[0]:339 prog_clk[0]:338 0.00341 +74 prog_clk[0]:338 prog_clk[0]:337 0.0009356916 +75 prog_clk[0]:442 prog_clk[0]:441 0.009359376 +76 prog_clk[0]:251 prog_clk[0]:250 0.0045 +77 prog_clk[0]:251 prog_clk[0]:248 0.002428572 +78 prog_clk[0]:252 prog_clk[0]:251 0.00341 +79 prog_clk[0]:113 prog_clk[0]:112 0.00341 +80 prog_clk[0]:112 prog_clk[0]:111 0.0009356916 +81 prog_clk[0]:490 prog_clk[0]:489 0.0001059783 +82 prog_clk[0]:491 prog_clk[0]:490 0.0045 +83 prog_clk[0]:489 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +84 prog_clk[0]:196 prog_clk[0]:195 0.00341 +85 prog_clk[0]:195 prog_clk[0]:194 0.001151892 +86 prog_clk[0]:200 prog_clk[0]:199 0.006930804 +87 prog_clk[0]:201 prog_clk[0]:200 0.00341 +88 prog_clk[0]:201 prog_clk[0]:139 0.0004324 +89 prog_clk[0]:291 prog_clk[0]:290 0.0008593751 +90 prog_clk[0]:292 prog_clk[0]:291 0.00341 +91 prog_clk[0]:294 prog_clk[0]:293 0.00341 +92 prog_clk[0]:293 prog_clk[0]:292 0.0007183166 +93 prog_clk[0]:298 prog_clk[0]:297 0.0008593751 +94 prog_clk[0]:299 prog_clk[0]:298 0.00341 +95 prog_clk[0]:301 prog_clk[0]:300 0.00341 +96 prog_clk[0]:300 prog_clk[0]:299 0.0002859166 +97 prog_clk[0]:511 prog_clk[0]:510 0.0001059783 +98 prog_clk[0]:512 prog_clk[0]:511 0.0045 +99 prog_clk[0]:510 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +100 prog_clk[0]:185 prog_clk[0]:184 0.002680804 +101 prog_clk[0]:186 prog_clk[0]:185 0.00341 +102 prog_clk[0]:186 prog_clk[0]:159 0.0002162 +103 prog_clk[0]:134 prog_clk[0]:133 0.0045 +104 prog_clk[0]:135 prog_clk[0]:134 0.00341 +105 prog_clk[0]:133 prog_clk[0]:132 0.0005736608 +106 prog_clk[0]:132 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +107 prog_clk[0]:434 prog_clk[0]:433 0.0045 +108 prog_clk[0]:434 prog_clk[0]:431 0.007245536 +109 prog_clk[0]:435 prog_clk[0]:434 0.00341 +110 prog_clk[0]:437 prog_clk[0]:436 0.00341 +111 prog_clk[0]:437 prog_clk[0]:428 0.002388393 +112 prog_clk[0]:436 prog_clk[0]:435 0.001222783 +113 prog_clk[0]:559 prog_clk[0]:558 0.004198661 +114 prog_clk[0]:560 prog_clk[0]:559 0.00341 +115 prog_clk[0]:560 prog_clk[0]:325 0.001441333 +116 prog_clk[0]:539 prog_clk[0]:538 0.005109375 +117 prog_clk[0]:540 prog_clk[0]:539 0.00341 +118 prog_clk[0]:396 prog_clk[0]:395 0.00341 +119 prog_clk[0]:396 prog_clk[0]:384 0.01143304 +120 prog_clk[0]:395 prog_clk[0]:394 0.0007915583 +121 prog_clk[0]:400 prog_clk[0]:399 0.0045 +122 prog_clk[0]:400 prog_clk[0]:397 0.01275 +123 prog_clk[0]:401 prog_clk[0]:400 0.00341 +124 prog_clk[0]:384 prog_clk[0]:383 0.00341 +125 prog_clk[0]:384 prog_clk[0]:369 0.0004107143 +126 prog_clk[0]:383 prog_clk[0]:382 0.000215025 +127 prog_clk[0]:130 prog_clk[0]:129 0.0005669643 +128 prog_clk[0]:130 prog_clk[0]:126 0.001821429 +129 prog_clk[0]:131 prog_clk[0]:130 0.00341 +130 prog_clk[0]:495 prog_clk[0]:494 0.0005669643 +131 prog_clk[0]:495 prog_clk[0]:491 0.004209822 +132 prog_clk[0]:496 prog_clk[0]:495 0.00341 +133 prog_clk[0]:143 prog_clk[0]:142 0.0009843751 +134 prog_clk[0]:144 prog_clk[0]:143 0.0045 +135 prog_clk[0]:142 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +136 prog_clk[0]:387 prog_clk[0]:386 0.0045 +137 prog_clk[0]:388 prog_clk[0]:387 0.00341 +138 prog_clk[0]:386 prog_clk[0]:385 0.0001440218 +139 prog_clk[0]:385 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +140 prog_clk[0]:94 prog_clk[0]:93 0.0045 +141 prog_clk[0]:94 prog_clk[0]:91 0.002388393 +142 prog_clk[0]:95 prog_clk[0]:94 0.00341 +143 prog_clk[0]:264 prog_clk[0]:263 0.007234375 +144 prog_clk[0]:284 prog_clk[0]:283 0.00341 +145 prog_clk[0]:283 prog_clk[0]:282 0.0002859167 +146 prog_clk[0]:281 prog_clk[0]:280 0.001770089 +147 prog_clk[0]:282 prog_clk[0]:281 0.00341 +148 prog_clk[0]:499 prog_clk[0]:498 0.00341 +149 prog_clk[0]:498 prog_clk[0]:497 0.000431225 +150 prog_clk[0]:323 prog_clk[0]:322 0.006627232 +151 prog_clk[0]:324 prog_clk[0]:323 0.00341 +152 prog_clk[0]:324 prog_clk[0]:218 0.0030268 +153 prog_clk[0]:469 prog_clk[0]:468 0.0003705357 +154 prog_clk[0]:470 prog_clk[0]:469 0.0045 +155 prog_clk[0]:259 prog_clk[0]:258 0.00341 +156 prog_clk[0]:258 prog_clk[0]:257 0.0005753583 +157 prog_clk[0]:203 prog_clk[0]:202 0.00341 +158 prog_clk[0]:202 prog_clk[0]:201 0.0002870917 +159 prog_clk[0]:205 prog_clk[0]:204 0.0045 +160 prog_clk[0]:204 prog_clk[0]:203 0.002033482 +161 prog_clk[0]:377 prog_clk[0]:376 0.002337054 +162 prog_clk[0]:378 prog_clk[0]:377 0.00341 +163 prog_clk[0]:378 prog_clk[0]:373 0.001151892 +164 prog_clk[0]:375 prog_clk[0]:374 0.0001059783 +165 prog_clk[0]:376 prog_clk[0]:375 0.0045 +166 prog_clk[0]:374 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +167 prog_clk[0]:90 prog_clk[0]:89 0.0001059783 +168 prog_clk[0]:91 prog_clk[0]:90 0.0045 +169 prog_clk[0]:89 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +170 prog_clk[0]:108 prog_clk[0]:107 0.0001847826 +171 prog_clk[0]:109 prog_clk[0]:108 0.0045 +172 prog_clk[0]:109 prog_clk[0]:106 0.002680804 +173 prog_clk[0]:107 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +174 prog_clk[0]:336 prog_clk[0]:335 0.002337054 +175 prog_clk[0]:337 prog_clk[0]:336 0.00341 +176 prog_clk[0]:337 prog_clk[0]:332 0.0009356916 +177 prog_clk[0]:334 prog_clk[0]:333 0.0001059783 +178 prog_clk[0]:335 prog_clk[0]:334 0.0045 +179 prog_clk[0]:333 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +180 prog_clk[0]:93 prog_clk[0]:92 0.0001440218 +181 prog_clk[0]:92 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +182 prog_clk[0]:158 prog_clk[0]:157 0.0045 +183 prog_clk[0]:159 prog_clk[0]:158 0.00341 +184 prog_clk[0]:159 prog_clk[0]:155 0.001584292 +185 prog_clk[0]:157 prog_clk[0]:156 0.0001059783 +186 prog_clk[0]:156 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +187 prog_clk[0]:399 prog_clk[0]:398 0.0001440218 +188 prog_clk[0]:398 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +189 prog_clk[0]:183 prog_clk[0]:182 0.0001847826 +190 prog_clk[0]:184 prog_clk[0]:183 0.0045 +191 prog_clk[0]:184 prog_clk[0]:181 0.004553572 +192 prog_clk[0]:182 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +193 prog_clk[0]:228 prog_clk[0]:227 0.0045 +194 prog_clk[0]:229 prog_clk[0]:228 0.00341 +195 prog_clk[0]:227 prog_clk[0]:226 0.0001059783 +196 prog_clk[0]:226 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +197 prog_clk[0]:433 prog_clk[0]:432 0.0001059783 +198 prog_clk[0]:432 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +199 prog_clk[0]:532 prog_clk[0]:531 0.006587053 +200 prog_clk[0]:533 prog_clk[0]:532 0.00341 +201 prog_clk[0]:533 prog_clk[0]:528 0.0002882666 +202 prog_clk[0]:530 prog_clk[0]:529 0.0001059783 +203 prog_clk[0]:531 prog_clk[0]:530 0.0045 +204 prog_clk[0]:529 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +205 prog_clk[0]:350 prog_clk[0]:349 0.00341 +206 prog_clk[0]:350 prog_clk[0]:343 0.0004107143 +207 prog_clk[0]:349 prog_clk[0]:348 0.0001053583 +208 prog_clk[0]:346 prog_clk[0]:345 0.0045 +209 prog_clk[0]:347 prog_clk[0]:346 0.00341 +210 prog_clk[0]:345 prog_clk[0]:344 0.0001440218 +211 prog_clk[0]:344 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +212 prog_clk[0]:212 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +213 prog_clk[0]:213 prog_clk[0]:212 0.0045 +214 prog_clk[0]:213 prog_clk[0]:211 0.004513393 +215 prog_clk[0]:168 prog_clk[0]:167 0.00355134 +216 prog_clk[0]:169 prog_clk[0]:168 0.00341 +217 prog_clk[0]:169 prog_clk[0]:164 0.000431225 +218 prog_clk[0]:166 prog_clk[0]:165 0.0001059783 +219 prog_clk[0]:167 prog_clk[0]:166 0.0045 +220 prog_clk[0]:165 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +221 prog_clk[0]:341 prog_clk[0]:340 0.0001847826 +222 prog_clk[0]:342 prog_clk[0]:341 0.0045 +223 prog_clk[0]:342 prog_clk[0]:339 0.0001850962 +224 prog_clk[0]:340 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +225 prog_clk[0]:427 prog_clk[0]:426 0.0001059783 +226 prog_clk[0]:428 prog_clk[0]:427 0.0045 +227 prog_clk[0]:426 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +228 prog_clk[0]:313 prog_clk[0]:312 0.0001440218 +229 prog_clk[0]:314 prog_clk[0]:313 0.0045 +230 prog_clk[0]:312 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +231 prog_clk[0]:248 prog_clk[0]:247 0.00341 +232 prog_clk[0]:248 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prog_clk[0]:389 0.0001053583 +490 prog_clk[0]:391 prog_clk[0]:390 0.0001059783 +491 prog_clk[0]:392 prog_clk[0]:391 0.0045 +492 prog_clk[0]:390 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +493 prog_clk[0]:405 prog_clk[0]:404 0.004765625 +494 prog_clk[0]:406 prog_clk[0]:405 0.00341 +495 prog_clk[0]:406 prog_clk[0]:401 0.0007915583 +496 prog_clk[0]:403 prog_clk[0]:402 0.0001440218 +497 prog_clk[0]:404 prog_clk[0]:403 0.0045 +498 prog_clk[0]:402 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +499 prog_clk[0]:381 prog_clk[0]:380 0.0045 +500 prog_clk[0]:382 prog_clk[0]:381 0.00341 +501 prog_clk[0]:382 prog_clk[0]:378 0.0008648 +502 prog_clk[0]:380 prog_clk[0]:379 0.0001059783 +503 prog_clk[0]:379 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +504 prog_clk[0]:414 prog_clk[0]:413 0.0045 +505 prog_clk[0]:415 prog_clk[0]:414 0.00341 +506 prog_clk[0]:415 prog_clk[0]:411 0.0008647999 +507 prog_clk[0]:413 prog_clk[0]:412 0.0001440217 +508 prog_clk[0]:412 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +509 prog_clk[0]:363 prog_clk[0]:362 0.0045 +510 prog_clk[0]:364 prog_clk[0]:363 0.00341 +511 prog_clk[0]:362 prog_clk[0]:361 0.0001440218 +512 prog_clk[0]:361 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +513 prog_clk[0]:562 prog_clk[0]:561 0.00341 +514 prog_clk[0]:561 prog_clk[0]:560 0.0002870917 +515 prog_clk[0]:468 prog_clk[0]:467 0.00078125 +516 prog_clk[0]:468 prog_clk[0]:462 0.0003035715 +517 prog_clk[0]:358 prog_clk[0]:357 0.001024554 +518 prog_clk[0]:548 prog_clk[0]:547 0.0001638514 +519 prog_clk[0]:549 prog_clk[0]:548 0.0002723215 +520 prog_clk[0]:439 prog_clk[0]:438 0.0003035715 +521 prog_clk[0]:303 prog_clk[0]:302 0.0006071429 +522 prog_clk[0]:209 prog_clk[0]:208 0.0003035715 +523 prog_clk[0]:208 prog_clk[0]:207 0.001232143 +524 prog_clk[0]:207 prog_clk[0]:206 1e-05 +525 prog_clk[0]:118 prog_clk[0]:117 0.0006138393 +526 prog_clk[0]:173 prog_clk[0]:172 0.0003035715 +527 prog_clk[0]:146 prog_clk[0]:145 0.0006138393 +528 prog_clk[0]:471 prog_clk[0]:470 0.004209821 +529 prog_clk[0]:472 prog_clk[0]:471 0.0008214285 +530 prog_clk[0]:476 prog_clk[0]:475 0.005160714 +531 prog_clk[0]:483 prog_clk[0]:482 0.007285715 +532 prog_clk[0]:343 prog_clk[0]:342 0.002691965 +533 prog_clk[0]:552 prog_clk[0]:551 0.0004107143 +534 prog_clk[0]:552 prog_clk[0]:546 0.002732143 +535 prog_clk[0]:500 prog_clk[0]:499 0.007841518 +536 prog_clk[0]:500 prog_clk[0]:328 0.0004107143 +537 prog_clk[0]:322 prog_clk[0]:321 0.002388393 +538 prog_clk[0]:322 prog_clk[0]:318 0.0004107143 +539 prog_clk[0]:397 prog_clk[0]:396 0.0004107143 +540 prog_clk[0]:369 prog_clk[0]:368 0.004816965 +541 prog_clk[0]:280 prog_clk[0]:279 0.0003705357 +542 prog_clk[0]:279 prog_clk[0]:278 0.00019375 +543 prog_clk[0]:279 prog_clk[0]:275 0.002984375 +544 prog_clk[0]:263 prog_clk[0]:262 0.001232143 +545 prog_clk[0]:263 prog_clk[0]:259 0.007234375 +546 prog_clk[0]:242 prog_clk[0]:241 0.0008214285 +547 prog_clk[0]:242 prog_clk[0]:238 0.002084821 +548 prog_clk[0]:150 prog_clk[0]:149 0.0003705357 +549 prog_clk[0]:149 prog_clk[0]:148 0.00019375 +550 prog_clk[0]:149 prog_clk[0]:144 0.004816964 +551 prog_clk[0]:497 prog_clk[0]:496 0.002521158 +552 prog_clk[0]:497 prog_clk[0]:488 0.0001053583 +553 prog_clk[0]:461 prog_clk[0]:460 0.0005044666 +554 prog_clk[0]:348 prog_clk[0]:347 0.000431225 +555 prog_clk[0]:325 prog_clk[0]:324 0.0019458 +556 prog_clk[0]:325 prog_clk[0]:95 0.0001053583 +557 prog_clk[0]:505 prog_clk[0]:504 0.000647425 +558 prog_clk[0]:365 prog_clk[0]:364 0.000215025 +559 prog_clk[0]:416 prog_clk[0]:415 0.0002162 +560 prog_clk[0]:389 prog_clk[0]:388 0.0007194916 +561 prog_clk[0]:225 prog_clk[0]:224 0.0001429583 + +*END + +*D_NET mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004085344 //LENGTH 2.480 LUMPCC 0.0001805725 DR + +*CONN +*I mux_bottom_track_13\/mux_l1_in_1_:X O *L 0 *C 44.905 37.060 +*I mux_bottom_track_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 47.095 37.060 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 47.058 37.060 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 44.943 37.060 + +*CAP +0 mux_bottom_track_13\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_13\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001129809 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001129809 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_in[10]:40 9.028627e-05 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_in[10]:41 9.028627e-05 + +*RES +0 mux_bottom_track_13\/mux_l1_in_1_:X mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_13\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001715984 //LENGTH 13.665 LUMPCC 0.0005845325 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_0_:X O *L 0 *C 59.165 20.060 +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 61.435 9.690 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 61.398 9.582 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 59.845 9.520 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 59.800 9.565 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 59.800 20.015 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 59.755 20.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 59.203 20.060 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001197197 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001197197 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003757862 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003757862 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.922008e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.922008e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[18]:21 0.0002922663 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_bottom_in[18]:20 0.0002922663 + +*RES +0 mux_bottom_track_17\/mux_l2_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001386161 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.009330358 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008810951 //LENGTH 5.485 LUMPCC 0.0002813906 DR + +*CONN +*I mux_bottom_track_23\/mux_l1_in_0_:X O *L 0 *C 84.925 34.680 +*I mux_bottom_track_23\/mux_l2_in_0_:A1 I *L 0.00198 *C 87.400 36.380 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 87.400 36.380 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.400 36.040 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 84.685 36.040 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 84.640 35.995 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 84.640 34.725 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 84.640 34.680 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 84.925 34.680 + +*CAP +0 mux_bottom_track_23\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.443122e-05 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001953067 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001684319 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.223174e-05 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.223174e-05 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.785385e-05 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.721731e-05 +9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[3]:8 4.428702e-05 +10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[3]:9 4.428702e-05 +11 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.428702e-05 +12 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.212125e-05 +13 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.428702e-05 +14 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.212125e-05 + +*RES +0 mux_bottom_track_23\/mux_l1_in_0_:X mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001548913 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001133929 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002424107 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_23\/mux_l2_in_0_:A1 0.152 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001175731 //LENGTH 8.720 LUMPCC 0.0004348762 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_3_:X O *L 0 *C 15.925 46.920 +*I mux_bottom_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 16.275 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 16.275 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 16.100 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 16.100 39.145 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 16.100 46.875 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 16.100 46.920 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 15.925 46.920 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.88374e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.331648e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002614204 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002614204 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.52174e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.864273e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_right_in[4]:7 9.15292e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_right_in[4]:6 9.15292e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:10 5.098549e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:11 2.141982e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:8 5.098549e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:10 2.141982e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.179763e-06 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.179763e-06 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.132385e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.132385e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_3_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3\/mux_l2_in_1_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006901786 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009964816 //LENGTH 7.870 LUMPCC 0.0001170401 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_1_:X O *L 0 *C 32.835 37.400 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 34.675 42.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 34.638 42.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 34.085 42.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 34.040 42.455 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 34.040 37.445 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 33.995 37.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 32.873 37.400 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.185253e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.185253e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002830596 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002830596 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001038086 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001038086 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_2_sram[0]:21 2.52414e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:20 2.52414e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:22 1.589255e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:26 1.100735e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:24 6.37875e-06 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:25 1.100735e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:26 1.589255e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:23 6.37875e-06 + +*RES +0 mux_bottom_track_5\/mux_l1_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001002232 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001194119 //LENGTH 8.040 LUMPCC 0.000388031 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_3_:X O *L 0 *C 18.685 55.420 +*I mux_bottom_track_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 18.130 48.280 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 18.130 48.280 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 18.400 48.280 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 18.400 48.325 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 18.400 55.375 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 18.400 55.420 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 18.685 55.420 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.536041e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.569925e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002724786 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002724786 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.121818e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.685296e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:472 5.617069e-05 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:475 0.0001378448 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:475 5.617069e-05 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:476 0.0001378448 + +*RES +0 mux_bottom_track_7\/mux_l1_in_3_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006294643 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001467392 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_7\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000456102 //LENGTH 3.330 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_11\/mux_l1_in_0_:X O *L 0 *C 32.835 60.860 +*I mux_bottom_track_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 32.760 63.580 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 32.660 63.580 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 32.660 63.535 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 32.660 60.905 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 32.660 60.860 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 32.835 60.860 + +*CAP +0 mux_bottom_track_11\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_11\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.260286e-05 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001578507 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001578507 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.22937e-05 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.350406e-05 + +*RES +0 mux_bottom_track_11\/mux_l1_in_0_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_11\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002348214 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002002586 //LENGTH 16.625 LUMPCC 0.0004296633 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 103.215 39.100 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 95.680 30.940 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 95.718 30.940 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 97.935 30.940 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 97.980 30.985 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 97.980 39.055 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 98.025 39.100 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 103.178 39.100 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.628643e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.628643e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004071624 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004071624 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002920126 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002920126 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size4_2_sram[0]:8 6.987934e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size4_2_sram[0]:9 6.987934e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_2_sram[0]:6 4.29445e-05 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_2_sram[0]:10 5.437026e-07 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_2_sram[0]:5 4.29445e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_2_sram[0]:11 5.437026e-07 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_2_sram[1]:12 2.326287e-06 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size4_2_sram[1]:10 9.913781e-05 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_2_sram[1]:11 2.326287e-06 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size4_2_sram[1]:9 9.913781e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.004600447 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007205358 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001979911 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001395946 //LENGTH 10.100 LUMPCC 0.0006303538 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_0_:X O *L 0 *C 75.615 22.780 +*I mux_bottom_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 71.205 18.020 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 71.243 18.020 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 71.715 18.020 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 71.760 18.065 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 71.760 22.735 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 71.805 22.780 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 75.578 22.780 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.67564e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.67564e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002164768 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002164768 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001285631 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001285631 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_left_grid_pin_38_[0]:10 0.0001491344 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 bottom_left_grid_pin_38_[0]:9 0.0001491344 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_3_sram[1]:6 3.1142e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_3_sram[1]:7 3.1142e-05 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_3_sram[1]:8 5.716796e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_3_sram[1]:4 7.773258e-05 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_3_sram[1]:5 5.716796e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_3_sram[1]:3 7.773258e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004218751 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004169643 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003368304 + +*END + +*D_NET mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001553038 //LENGTH 9.915 LUMPCC 0.0006238929 DR + +*CONN +*I mux_bottom_track_39\/mux_l2_in_0_:X O *L 0 *C 54.565 8.840 +*I mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 59.055 4.250 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 59.055 4.250 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 54.785 4.080 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 54.740 4.125 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 54.740 8.795 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 54.740 8.840 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 54.565 8.840 + +*CAP +0 mux_bottom_track_39\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001460949 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001073239 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000281243 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000281243 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.617449e-05 +7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.506534e-05 +8 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_bottom_out[6]:3 7.309268e-05 +9 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_out[6]:4 7.309268e-05 +10 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_out[9] 7.048794e-05 +11 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_out[9]:2 7.048794e-05 +12 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0001683658 +13 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0001683658 + +*RES +0 mux_bottom_track_39\/mux_l2_in_0_:X mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0038125 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET chanx_right_out[2] 0.0006244733 //LENGTH 4.830 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 138.655 55.080 +*P chanx_right_out[2] O *L 0.7423 *C 140.450 53.040 +*N chanx_right_out[2]:2 *C 138.468 53.040 +*N chanx_right_out[2]:3 *C 138.460 53.098 +*N chanx_right_out[2]:4 *C 138.460 55.035 +*N chanx_right_out[2]:5 *C 138.460 55.080 +*N chanx_right_out[2]:6 *C 138.655 55.080 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 chanx_right_out[2] 0.0001368327 +2 chanx_right_out[2]:2 0.0001368327 +3 chanx_right_out[2]:3 0.0001240769 +4 chanx_right_out[2]:4 0.0001240769 +5 chanx_right_out[2]:5 4.955406e-05 +6 chanx_right_out[2]:6 5.21e-05 + +*RES +0 ropt_mt_inst_795:X chanx_right_out[2]:6 0.152 +1 chanx_right_out[2]:6 chanx_right_out[2]:5 0.0001059783 +2 chanx_right_out[2]:5 chanx_right_out[2]:4 0.0045 +3 chanx_right_out[2]:4 chanx_right_out[2]:3 0.001729911 +4 chanx_right_out[2]:3 chanx_right_out[2]:2 0.00341 +5 chanx_right_out[2]:2 chanx_right_out[2] 0.0003105917 + +*END + +*D_NET chanx_right_out[18] 0.0007653869 //LENGTH 6.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 136.160 88.400 +*P chanx_right_out[18] O *L 0.7423 *C 140.375 89.760 +*N chanx_right_out[18]:2 *C 136.168 89.760 +*N chanx_right_out[18]:3 *C 136.160 89.703 +*N chanx_right_out[18]:4 *C 136.160 88.445 +*N chanx_right_out[18]:5 *C 136.160 88.400 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 chanx_right_out[18] 0.000275996 +2 chanx_right_out[18]:2 0.000275996 +3 chanx_right_out[18]:3 8.92282e-05 +4 chanx_right_out[18]:4 8.92282e-05 +5 chanx_right_out[18]:5 3.393845e-05 + +*RES +0 ropt_mt_inst_802:X chanx_right_out[18]:5 0.152 +1 chanx_right_out[18]:3 chanx_right_out[18]:2 0.00341 +2 chanx_right_out[18]:2 chanx_right_out[18] 0.000659175 +3 chanx_right_out[18]:5 chanx_right_out[18]:4 0.0045 +4 chanx_right_out[18]:4 chanx_right_out[18]:3 0.001122768 + +*END + +*D_NET chanx_right_out[11] 0.001040139 //LENGTH 8.180 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_809:X O *L 0 *C 136.160 72.080 +*P chanx_right_out[11] O *L 0.7423 *C 140.450 69.360 +*N chanx_right_out[11]:2 *C 138.468 69.360 +*N chanx_right_out[11]:3 *C 138.460 69.418 +*N chanx_right_out[11]:4 *C 138.460 71.355 +*N chanx_right_out[11]:5 *C 138.460 71.400 +*N chanx_right_out[11]:6 *C 138.655 71.740 +*N chanx_right_out[11]:7 *C 136.160 71.740 +*N chanx_right_out[11]:8 *C 136.160 72.080 + +*CAP +0 ropt_mt_inst_809:X 1e-06 +1 chanx_right_out[11] 0.0001340475 +2 chanx_right_out[11]:2 0.0001340475 +3 chanx_right_out[11]:3 0.0001236578 +4 chanx_right_out[11]:4 0.0001236578 +5 chanx_right_out[11]:5 6.234319e-05 +6 chanx_right_out[11]:6 0.0002059297 +7 chanx_right_out[11]:7 0.0002038294 +8 chanx_right_out[11]:8 5.162616e-05 + +*RES +0 ropt_mt_inst_809:X chanx_right_out[11]:8 0.152 +1 chanx_right_out[11]:8 chanx_right_out[11]:7 0.0003035715 +2 chanx_right_out[11]:5 chanx_right_out[11]:4 0.0045 +3 chanx_right_out[11]:4 chanx_right_out[11]:3 0.001729911 +4 chanx_right_out[11]:3 chanx_right_out[11]:2 0.00341 +5 chanx_right_out[11]:2 chanx_right_out[11] 0.0003105916 +6 chanx_right_out[11]:7 chanx_right_out[11]:6 0.002227679 +7 chanx_right_out[11]:6 chanx_right_out[11]:5 0.0003035714 + +*END + +*D_NET ropt_net_203 0.001208646 //LENGTH 9.840 LUMPCC 0.0001774087 DR + +*CONN +*I ropt_mt_inst_818:X O *L 0 *C 7.095 55.080 +*I ropt_mt_inst_821:A I *L 0.001767 *C 3.220 50.320 +*N ropt_net_203:2 *C 3.258 50.320 +*N ropt_net_203:3 *C 5.935 50.320 +*N ropt_net_203:4 *C 5.980 50.320 +*N ropt_net_203:5 *C 5.980 55.035 +*N ropt_net_203:6 *C 6.025 55.080 +*N ropt_net_203:7 *C 7.058 55.080 + +*CAP +0 ropt_mt_inst_818:X 1e-06 +1 ropt_mt_inst_821:A 1e-06 +2 ropt_net_203:2 0.0001682161 +3 ropt_net_203:3 0.0001682161 +4 ropt_net_203:4 0.000269786 +5 ropt_net_203:5 0.0002397171 +6 ropt_net_203:6 9.165103e-05 +7 ropt_net_203:7 9.165103e-05 +8 ropt_net_203:5 ropt_net_210:4 4.294967e-05 +9 ropt_net_203:3 ropt_net_210:7 4.575466e-05 +10 ropt_net_203:4 ropt_net_210:5 4.294967e-05 +11 ropt_net_203:2 ropt_net_210:6 4.575466e-05 + +*RES +0 ropt_mt_inst_818:X ropt_net_203:7 0.152 +1 ropt_net_203:7 ropt_net_203:6 0.0009218751 +2 ropt_net_203:6 ropt_net_203:5 0.0045 +3 ropt_net_203:5 ropt_net_203:4 0.004209822 +4 ropt_net_203:3 ropt_net_203:2 0.002390625 +5 ropt_net_203:4 ropt_net_203:3 0.0045 +6 ropt_net_203:2 ropt_mt_inst_821:A 0.152 + +*END + +*D_NET ccff_tail[0] 0.000704095 //LENGTH 5.875 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_829:X O *L 0 *C 4.140 79.560 +*P ccff_tail[0] O *L 0.7423 *C 1.298 77.520 +*N ccff_tail[0]:2 *C 1.380 77.520 +*N ccff_tail[0]:3 *C 1.380 77.520 +*N ccff_tail[0]:4 *C 2.300 77.520 +*N ccff_tail[0]:5 *C 2.300 79.515 +*N ccff_tail[0]:6 *C 2.345 79.560 +*N ccff_tail[0]:7 *C 4.103 79.560 + +*CAP +0 ropt_mt_inst_829:X 1e-06 +1 ccff_tail[0] 2.796214e-05 +2 ccff_tail[0]:2 2.796214e-05 +3 ccff_tail[0]:3 8.79966e-05 +4 ccff_tail[0]:4 0.0001722332 +5 ccff_tail[0]:5 0.0001177655 +6 ccff_tail[0]:6 0.0001345877 +7 ccff_tail[0]:7 0.0001345877 + +*RES +0 ropt_mt_inst_829:X ccff_tail[0]:7 0.152 +1 ccff_tail[0]:7 ccff_tail[0]:6 0.001569197 +2 ccff_tail[0]:6 ccff_tail[0]:5 0.0045 +3 ccff_tail[0]:5 ccff_tail[0]:4 0.00178125 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 +6 ccff_tail[0]:4 ccff_tail[0]:3 0.0008214285 + +*END + +*D_NET ropt_net_183 0.002712362 //LENGTH 22.000 LUMPCC 0.0008625666 DR + +*CONN +*I BUFT_RR_85:X O *L 0 *C 118.220 82.960 +*I ropt_mt_inst_803:A I *L 0.001766 *C 134.780 80.240 +*N ropt_net_183:2 *C 134.780 80.240 +*N ropt_net_183:3 *C 134.780 80.285 +*N ropt_net_183:4 *C 134.765 82.903 +*N ropt_net_183:5 *C 134.673 82.960 +*N ropt_net_183:6 *C 117.308 82.960 +*N ropt_net_183:7 *C 117.300 82.960 +*N ropt_net_183:8 *C 117.345 82.960 +*N ropt_net_183:9 *C 118.183 82.960 + +*CAP +0 BUFT_RR_85:X 1e-06 +1 ropt_mt_inst_803:A 1e-06 +2 ropt_net_183:2 3.632555e-05 +3 ropt_net_183:3 0.000121563 +4 ropt_net_183:4 0.000121563 +5 ropt_net_183:5 0.0007051885 +6 ropt_net_183:6 0.0007051885 +7 ropt_net_183:7 3.353159e-05 +8 ropt_net_183:8 6.221759e-05 +9 ropt_net_183:9 6.221759e-05 +10 ropt_net_183:6 chanx_right_in[9]:28 0.0001496265 +11 ropt_net_183:5 chanx_right_in[9]:29 0.0001496265 +12 ropt_net_183:6 chanx_left_in[13]:13 7.115601e-05 +13 ropt_net_183:6 chanx_left_in[13]:17 3.801403e-05 +14 ropt_net_183:5 chanx_left_in[13]:12 7.115601e-05 +15 ropt_net_183:5 chanx_left_in[13]:16 3.801403e-05 +16 ropt_net_183:4 chanx_left_in[17]:6 7.797738e-05 +17 ropt_net_183:3 chanx_left_in[17]:7 7.797738e-05 +18 ropt_net_183:6 chanx_right_out[8]:2 9.450944e-05 +19 ropt_net_183:5 chanx_right_out[8] 9.450944e-05 + +*RES +0 BUFT_RR_85:X ropt_net_183:9 0.152 +1 ropt_net_183:9 ropt_net_183:8 0.0007477679 +2 ropt_net_183:8 ropt_net_183:7 0.0045 +3 ropt_net_183:7 ropt_net_183:6 0.00341 +4 ropt_net_183:6 ropt_net_183:5 0.002720516 +5 ropt_net_183:4 ropt_net_183:3 0.002337053 +6 ropt_net_183:5 ropt_net_183:4 0.00341 +7 ropt_net_183:2 ropt_mt_inst_803:A 0.152 +8 ropt_net_183:3 ropt_net_183:2 0.0045 + +*END + +*D_NET chanx_right_in[9] 0.02843037 //LENGTH 235.245 LUMPCC 0.007063279 DR + +*CONN +*P chanx_right_in[9] I *L 0.29796 *C 140.450 35.360 +*I ropt_mt_inst_790:A I *L 0.001767 *C 3.220 99.280 +*I mux_bottom_track_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 34.500 61.540 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 60.165 83.300 +*N chanx_right_in[9]:4 *C 60.165 83.300 +*N chanx_right_in[9]:5 *C 60.193 83.640 +*N chanx_right_in[9]:6 *C 34.462 61.540 +*N chanx_right_in[9]:7 *C 34.085 61.540 +*N chanx_right_in[9]:8 *C 34.040 61.585 +*N chanx_right_in[9]:9 *C 3.220 99.280 +*N chanx_right_in[9]:10 *C 3.220 99.235 +*N chanx_right_in[9]:11 *C 3.220 98.645 +*N chanx_right_in[9]:12 *C 3.265 98.600 +*N chanx_right_in[9]:13 *C 26.175 98.600 +*N chanx_right_in[9]:14 *C 26.220 98.555 +*N chanx_right_in[9]:15 *C 26.220 85.725 +*N chanx_right_in[9]:16 *C 26.265 85.680 +*N chanx_right_in[9]:17 *C 27.555 85.680 +*N chanx_right_in[9]:18 *C 27.600 85.635 +*N chanx_right_in[9]:19 *C 27.600 76.898 +*N chanx_right_in[9]:20 *C 27.608 76.840 +*N chanx_right_in[9]:21 *C 34.032 76.840 +*N chanx_right_in[9]:22 *C 34.040 76.840 +*N chanx_right_in[9]:23 *C 34.040 83.595 +*N chanx_right_in[9]:24 *C 34.085 83.640 +*N chanx_right_in[9]:25 *C 60.215 83.633 +*N chanx_right_in[9]:26 *C 60.260 83.640 +*N chanx_right_in[9]:27 *C 60.268 83.640 +*N chanx_right_in[9]:28 *C 110.095 83.640 +*N chanx_right_in[9]:29 *C 119.580 83.640 +*N chanx_right_in[9]:30 *C 119.600 83.633 +*N chanx_right_in[9]:31 *C 119.600 36.047 +*N chanx_right_in[9]:32 *C 119.620 36.040 +*N chanx_right_in[9]:33 *C 138.920 36.040 +*N chanx_right_in[9]:34 *C 138.920 35.360 + +*CAP +0 chanx_right_in[9] 5.885817e-05 +1 ropt_mt_inst_790:A 1e-06 +2 mux_bottom_track_11\/mux_l1_in_0_:A1 1e-06 +3 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[9]:4 5.535602e-05 +5 chanx_right_in[9]:5 1.668843e-05 +6 chanx_right_in[9]:6 4.718747e-05 +7 chanx_right_in[9]:7 4.718747e-05 +8 chanx_right_in[9]:8 0.0007787935 +9 chanx_right_in[9]:9 2.75759e-05 +10 chanx_right_in[9]:10 4.714274e-05 +11 chanx_right_in[9]:11 4.714274e-05 +12 chanx_right_in[9]:12 0.001280969 +13 chanx_right_in[9]:13 0.001280969 +14 chanx_right_in[9]:14 0.000640193 +15 chanx_right_in[9]:15 0.000640193 +16 chanx_right_in[9]:16 0.0001191201 +17 chanx_right_in[9]:17 0.0001191201 +18 chanx_right_in[9]:18 0.0004468972 +19 chanx_right_in[9]:19 0.0004468972 +20 chanx_right_in[9]:20 0.0002641345 +21 chanx_right_in[9]:21 0.0002641345 +22 chanx_right_in[9]:22 0.001180784 +23 chanx_right_in[9]:23 0.0003672093 +24 chanx_right_in[9]:24 0.001397714 +25 chanx_right_in[9]:25 0.001440572 +26 chanx_right_in[9]:26 3.442728e-05 +27 chanx_right_in[9]:27 0.001585068 +28 chanx_right_in[9]:28 0.001919935 +29 chanx_right_in[9]:29 0.0003348676 +30 chanx_right_in[9]:30 0.002393236 +31 chanx_right_in[9]:31 0.002393236 +32 chanx_right_in[9]:32 0.0007753567 +33 chanx_right_in[9]:33 0.0008148119 +34 chanx_right_in[9]:34 9.831338e-05 +35 chanx_right_in[9] chanx_right_in[4] 4.670518e-05 +36 chanx_right_in[9]:32 chanx_right_in[4]:20 2.830853e-05 +37 chanx_right_in[9]:32 chanx_right_in[4]:21 0.0002289551 +38 chanx_right_in[9]:32 chanx_right_in[4]:25 2.059013e-05 +39 chanx_right_in[9]:33 chanx_right_in[4] 2.059013e-05 +40 chanx_right_in[9]:33 chanx_right_in[4]:21 2.830853e-05 +41 chanx_right_in[9]:33 chanx_right_in[4]:22 0.0002289551 +42 chanx_right_in[9]:33 chanx_right_in[4]:23 7.337816e-06 +43 chanx_right_in[9]:34 chanx_right_in[4]:24 7.337816e-06 +44 chanx_right_in[9]:34 chanx_right_in[4]:25 4.670518e-05 +45 chanx_right_in[9]:27 chanx_left_in[2]:14 0.0006130892 +46 chanx_right_in[9]:27 chanx_left_in[2]:13 0.0005404885 +47 chanx_right_in[9]:29 chanx_left_in[2]:12 0.0001019403 +48 chanx_right_in[9]:28 chanx_left_in[2]:12 0.0005404885 +49 chanx_right_in[9]:28 chanx_left_in[2]:13 0.0007150295 +50 chanx_right_in[9]:32 chanx_left_in[10]:15 0.0003885954 +51 chanx_right_in[9]:33 chanx_left_in[10]:14 0.0003885954 +52 chanx_right_in[9]:21 chanx_left_in[13]:35 0.0001056963 +53 chanx_right_in[9]:20 chanx_left_in[13] 0.0001056963 +54 chanx_right_in[9]:27 chanx_left_in[13]:17 0.0001531351 +55 chanx_right_in[9]:29 chanx_left_in[13]:16 6.173761e-05 +56 chanx_right_in[9]:28 chanx_left_in[13]:16 0.0001531351 +57 chanx_right_in[9]:28 chanx_left_in[13]:17 6.173761e-05 +58 chanx_right_in[9]:8 prog_clk[0]:349 6.652447e-06 +59 chanx_right_in[9]:8 prog_clk[0]:356 4.571321e-06 +60 chanx_right_in[9]:22 prog_clk[0]:350 4.571321e-06 +61 chanx_right_in[9]:22 prog_clk[0]:348 6.652447e-06 +62 chanx_right_in[9]:27 prog_clk[0]:383 1.317259e-05 +63 chanx_right_in[9]:27 prog_clk[0]:378 6.253853e-05 +64 chanx_right_in[9]:27 prog_clk[0]:234 0.000461072 +65 chanx_right_in[9]:27 prog_clk[0]:382 3.813768e-05 +66 chanx_right_in[9]:28 prog_clk[0]:373 6.253853e-05 +67 chanx_right_in[9]:28 prog_clk[0]:378 3.813768e-05 +68 chanx_right_in[9]:28 prog_clk[0]:233 0.000461072 +69 chanx_right_in[9]:28 prog_clk[0]:382 1.317259e-05 +70 chanx_right_in[9]:24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.89778e-05 +71 chanx_right_in[9]:25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.89778e-05 +72 chanx_right_in[9]:24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.53778e-05 +73 chanx_right_in[9]:24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002279138 +74 chanx_right_in[9]:24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.407439e-05 +75 chanx_right_in[9]:25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 6.53778e-05 +76 chanx_right_in[9]:25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002279138 +77 chanx_right_in[9]:25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.407439e-05 +78 chanx_right_in[9]:8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.773136e-05 +79 chanx_right_in[9]:22 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.773136e-05 +80 chanx_right_in[9]:13 ropt_net_217:2 7.521442e-05 +81 chanx_right_in[9]:12 ropt_net_217:3 7.521442e-05 +82 chanx_right_in[9]:29 ropt_net_183:5 0.0001496265 +83 chanx_right_in[9]:28 ropt_net_183:6 0.0001496265 + +*RES +0 chanx_right_in[9] chanx_right_in[9]:34 0.0002397 +1 chanx_right_in[9]:7 chanx_right_in[9]:6 0.0003370536 +2 chanx_right_in[9]:8 chanx_right_in[9]:7 0.0045 +3 chanx_right_in[9]:6 mux_bottom_track_11\/mux_l1_in_0_:A1 0.152 +4 chanx_right_in[9]:22 chanx_right_in[9]:21 0.00341 +5 chanx_right_in[9]:22 chanx_right_in[9]:8 0.01362054 +6 chanx_right_in[9]:21 chanx_right_in[9]:20 0.001006583 +7 chanx_right_in[9]:19 chanx_right_in[9]:18 0.007801339 +8 chanx_right_in[9]:20 chanx_right_in[9]:19 0.00341 +9 chanx_right_in[9]:17 chanx_right_in[9]:16 0.001151786 +10 chanx_right_in[9]:18 chanx_right_in[9]:17 0.0045 +11 chanx_right_in[9]:16 chanx_right_in[9]:15 0.0045 +12 chanx_right_in[9]:15 chanx_right_in[9]:14 0.01145536 +13 chanx_right_in[9]:13 chanx_right_in[9]:12 0.02045536 +14 chanx_right_in[9]:14 chanx_right_in[9]:13 0.0045 +15 chanx_right_in[9]:12 chanx_right_in[9]:11 0.0045 +16 chanx_right_in[9]:11 chanx_right_in[9]:10 0.0005267857 +17 chanx_right_in[9]:9 ropt_mt_inst_790:A 0.152 +18 chanx_right_in[9]:10 chanx_right_in[9]:9 0.0045 +19 chanx_right_in[9]:24 chanx_right_in[9]:23 0.0045 +20 chanx_right_in[9]:23 chanx_right_in[9]:22 0.006031251 +21 chanx_right_in[9]:25 chanx_right_in[9]:24 0.02333036 +22 chanx_right_in[9]:25 chanx_right_in[9]:5 2.008929e-05 +23 chanx_right_in[9]:25 chanx_right_in[9]:4 0.0001807065 +24 chanx_right_in[9]:26 chanx_right_in[9]:25 0.0045 +25 chanx_right_in[9]:27 chanx_right_in[9]:26 0.00341 +26 chanx_right_in[9]:29 chanx_right_in[9]:28 0.001485983 +27 chanx_right_in[9]:30 chanx_right_in[9]:29 0.00341 +28 chanx_right_in[9]:32 chanx_right_in[9]:31 0.00341 +29 chanx_right_in[9]:31 chanx_right_in[9]:30 0.007454982 +30 chanx_right_in[9]:4 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +31 chanx_right_in[9]:33 chanx_right_in[9]:32 0.003023666 +32 chanx_right_in[9]:34 chanx_right_in[9]:33 0.0001065333 +33 chanx_right_in[9]:28 chanx_right_in[9]:27 0.007806308 + +*END + +*D_NET chanx_left_in[12] 0.0246319 //LENGTH 173.155 LUMPCC 0.009196261 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 32.640 +*I mux_bottom_track_15\/mux_l1_in_1_:A1 I *L 0.00198 *C 56.485 30.940 +*I BUFT_RR_91:A I *L 0.001776 *C 112.700 66.640 +*I mux_right_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 113.910 76.840 +*N chanx_left_in[12]:4 *C 113.873 76.840 +*N chanx_left_in[12]:5 *C 112.745 76.840 +*N chanx_left_in[12]:6 *C 112.700 76.795 +*N chanx_left_in[12]:7 *C 112.700 66.640 +*N chanx_left_in[12]:8 *C 112.700 66.685 +*N chanx_left_in[12]:9 *C 112.700 70.040 +*N chanx_left_in[12]:10 *C 112.693 70.040 +*N chanx_left_in[12]:11 *C 63.500 70.040 +*N chanx_left_in[12]:12 *C 63.480 70.032 +*N chanx_left_in[12]:13 *C 63.480 31.968 +*N chanx_left_in[12]:14 *C 63.460 31.960 +*N chanx_left_in[12]:15 *C 56.523 30.940 +*N chanx_left_in[12]:16 *C 57.455 30.940 +*N chanx_left_in[12]:17 *C 57.500 30.985 +*N chanx_left_in[12]:18 *C 57.500 31.902 +*N chanx_left_in[12]:19 *C 57.500 31.960 +*N chanx_left_in[12]:20 *C 53.367 31.960 +*N chanx_left_in[12]:21 *C 53.360 31.902 +*N chanx_left_in[12]:22 *C 53.360 30.645 +*N chanx_left_in[12]:23 *C 53.315 30.600 +*N chanx_left_in[12]:24 *C 49.265 30.600 +*N chanx_left_in[12]:25 *C 49.220 30.645 +*N chanx_left_in[12]:26 *C 49.220 31.223 +*N chanx_left_in[12]:27 *C 49.213 31.280 +*N chanx_left_in[12]:28 *C 39.100 31.280 +*N chanx_left_in[12]:29 *C 39.100 31.960 +*N chanx_left_in[12]:30 *C 35.900 31.960 +*N chanx_left_in[12]:31 *C 35.880 31.968 +*N chanx_left_in[12]:32 *C 35.880 33.312 +*N chanx_left_in[12]:33 *C 35.860 33.320 +*N chanx_left_in[12]:34 *C 5.520 33.320 +*N chanx_left_in[12]:35 *C 5.520 32.640 + +*CAP +0 chanx_left_in[12] 0.0002897086 +1 mux_bottom_track_15\/mux_l1_in_1_:A1 1e-06 +2 BUFT_RR_91:A 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A0 1e-06 +4 chanx_left_in[12]:4 9.590808e-05 +5 chanx_left_in[12]:5 9.590808e-05 +6 chanx_left_in[12]:6 0.0003392022 +7 chanx_left_in[12]:7 3.051091e-05 +8 chanx_left_in[12]:8 0.0001657994 +9 chanx_left_in[12]:9 0.0005369886 +10 chanx_left_in[12]:10 0.001945831 +11 chanx_left_in[12]:11 0.001945831 +12 chanx_left_in[12]:12 0.001446995 +13 chanx_left_in[12]:13 0.001446995 +14 chanx_left_in[12]:14 0.0003522708 +15 chanx_left_in[12]:15 9.10214e-05 +16 chanx_left_in[12]:16 9.10214e-05 +17 chanx_left_in[12]:17 8.033913e-05 +18 chanx_left_in[12]:18 8.033913e-05 +19 chanx_left_in[12]:19 0.0006417687 +20 chanx_left_in[12]:20 0.000289498 +21 chanx_left_in[12]:21 0.0001144469 +22 chanx_left_in[12]:22 0.0001144469 +23 chanx_left_in[12]:23 0.0003660351 +24 chanx_left_in[12]:24 0.0003660351 +25 chanx_left_in[12]:25 6.83948e-05 +26 chanx_left_in[12]:26 6.83948e-05 +27 chanx_left_in[12]:27 0.0004021203 +28 chanx_left_in[12]:28 0.0004629479 +29 chanx_left_in[12]:29 0.0002750663 +30 chanx_left_in[12]:30 0.0002142388 +31 chanx_left_in[12]:31 9.420834e-05 +32 chanx_left_in[12]:32 9.420834e-05 +33 chanx_left_in[12]:33 0.001212781 +34 chanx_left_in[12]:34 0.001268224 +35 chanx_left_in[12]:35 0.0003451513 +36 chanx_left_in[12]:18 chanx_right_in[12]:17 7.434614e-08 +37 chanx_left_in[12]:17 chanx_right_in[12]:18 7.434614e-08 +38 chanx_left_in[12]:10 chanx_right_in[12]:29 0.0003630177 +39 chanx_left_in[12]:10 chanx_right_in[12]:30 0.0001572225 +40 chanx_left_in[12]:11 chanx_right_in[12]:28 0.0003630177 +41 chanx_left_in[12]:11 chanx_right_in[12]:29 0.0001572225 +42 chanx_left_in[12] chanx_left_in[10] 1.904895e-05 +43 chanx_left_in[12]:27 chanx_left_in[10]:47 4.429442e-07 +44 chanx_left_in[12]:30 chanx_left_in[10] 8.890508e-06 +45 chanx_left_in[12]:33 chanx_left_in[10]:47 0.0002402996 +46 chanx_left_in[12]:35 chanx_left_in[10]:47 1.904895e-05 +47 chanx_left_in[12]:34 chanx_left_in[10] 0.0002402996 +48 chanx_left_in[12]:29 chanx_left_in[10]:47 8.890508e-06 +49 chanx_left_in[12]:28 chanx_left_in[10] 4.429442e-07 +50 chanx_left_in[12]:10 prog_clk[0]:252 5.456232e-05 +51 chanx_left_in[12]:10 prog_clk[0]:388 2.543591e-05 +52 chanx_left_in[12]:10 prog_clk[0]:246 0.0007752884 +53 chanx_left_in[12]:10 prog_clk[0]:257 2.728334e-05 +54 chanx_left_in[12]:10 prog_clk[0]:394 1.847566e-05 +55 chanx_left_in[12]:11 prog_clk[0]:395 1.847566e-05 +56 chanx_left_in[12]:11 prog_clk[0]:258 2.728334e-05 +57 chanx_left_in[12]:11 prog_clk[0]:247 0.0007752884 +58 chanx_left_in[12]:11 prog_clk[0]:257 5.456232e-05 +59 chanx_left_in[12]:11 prog_clk[0]:389 2.543591e-05 +60 chanx_left_in[12]:27 prog_clk[0]:533 5.073738e-05 +61 chanx_left_in[12]:27 prog_clk[0]:528 6.065525e-06 +62 chanx_left_in[12]:33 prog_clk[0]:498 5.890626e-05 +63 chanx_left_in[12]:33 prog_clk[0]:497 0.0003879885 +64 chanx_left_in[12]:34 prog_clk[0]:496 0.0003879885 +65 chanx_left_in[12]:34 prog_clk[0]:497 5.890626e-05 +66 chanx_left_in[12]:28 prog_clk[0]:534 5.073738e-05 +67 chanx_left_in[12]:28 prog_clk[0]:533 6.065525e-06 +68 chanx_left_in[12]:12 chany_bottom_in[4]:14 8.911391e-05 +69 chanx_left_in[12]:12 chany_bottom_in[4]:15 0.0004148146 +70 chanx_left_in[12]:13 chany_bottom_in[4]:16 0.0004148146 +71 chanx_left_in[12]:13 chany_bottom_in[4]:15 8.911391e-05 +72 chanx_left_in[12]:12 chany_bottom_in[10]:13 0.001020841 +73 chanx_left_in[12]:13 chany_bottom_in[10]:14 0.001020841 +74 chanx_left_in[12]:19 bottom_left_grid_pin_34_[0]:25 0.0001303144 +75 chanx_left_in[12]:19 bottom_left_grid_pin_34_[0]:20 7.809569e-05 +76 chanx_left_in[12]:14 bottom_left_grid_pin_34_[0]:20 0.0001303144 +77 chanx_left_in[12]:20 bottom_left_grid_pin_34_[0]:25 7.809569e-05 +78 chanx_left_in[12]:27 bottom_left_grid_pin_34_[0]:20 0.0005680347 +79 chanx_left_in[12]:30 bottom_left_grid_pin_34_[0]:25 4.770227e-05 +80 chanx_left_in[12]:33 bottom_left_grid_pin_34_[0]:25 1.471711e-05 +81 chanx_left_in[12]:33 bottom_left_grid_pin_34_[0]:29 3.425692e-05 +82 chanx_left_in[12]:33 bottom_left_grid_pin_34_[0]:20 6.49937e-06 +83 chanx_left_in[12]:34 bottom_left_grid_pin_34_[0]:28 3.425692e-05 +84 chanx_left_in[12]:34 bottom_left_grid_pin_34_[0]:25 6.49937e-06 +85 chanx_left_in[12]:34 bottom_left_grid_pin_34_[0]:26 1.471711e-05 +86 chanx_left_in[12]:29 bottom_left_grid_pin_34_[0]:20 4.770227e-05 +87 chanx_left_in[12]:28 bottom_left_grid_pin_34_[0]:25 0.0005680347 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:35 0.0006720999 +1 chanx_left_in[12]:7 BUFT_RR_91:A 0.152 +2 chanx_left_in[12]:8 chanx_left_in[12]:7 0.0045 +3 chanx_left_in[12]:18 chanx_left_in[12]:17 0.0008191965 +4 chanx_left_in[12]:19 chanx_left_in[12]:18 0.00341 +5 chanx_left_in[12]:19 chanx_left_in[12]:14 0.0009337333 +6 chanx_left_in[12]:16 chanx_left_in[12]:15 0.0008325893 +7 chanx_left_in[12]:17 chanx_left_in[12]:16 0.0045 +8 chanx_left_in[12]:15 mux_bottom_track_15\/mux_l1_in_1_:A1 0.152 +9 chanx_left_in[12]:9 chanx_left_in[12]:8 0.002995536 +10 chanx_left_in[12]:9 chanx_left_in[12]:6 0.006031251 +11 chanx_left_in[12]:10 chanx_left_in[12]:9 0.00341 +12 chanx_left_in[12]:11 chanx_left_in[12]:10 0.007706824 +13 chanx_left_in[12]:12 chanx_left_in[12]:11 0.00341 +14 chanx_left_in[12]:14 chanx_left_in[12]:13 0.00341 +15 chanx_left_in[12]:13 chanx_left_in[12]:12 0.005963516 +16 chanx_left_in[12]:21 chanx_left_in[12]:20 0.00341 +17 chanx_left_in[12]:20 chanx_left_in[12]:19 0.000647425 +18 chanx_left_in[12]:23 chanx_left_in[12]:22 0.0045 +19 chanx_left_in[12]:22 chanx_left_in[12]:21 0.001122768 +20 chanx_left_in[12]:24 chanx_left_in[12]:23 0.003616072 +21 chanx_left_in[12]:25 chanx_left_in[12]:24 0.0045 +22 chanx_left_in[12]:26 chanx_left_in[12]:25 0.000515625 +23 chanx_left_in[12]:27 chanx_left_in[12]:26 0.00341 +24 chanx_left_in[12]:30 chanx_left_in[12]:29 0.0005013333 +25 chanx_left_in[12]:31 chanx_left_in[12]:30 0.00341 +26 chanx_left_in[12]:33 chanx_left_in[12]:32 0.00341 +27 chanx_left_in[12]:32 chanx_left_in[12]:31 0.0002107167 +28 chanx_left_in[12]:5 chanx_left_in[12]:4 0.001006696 +29 chanx_left_in[12]:6 chanx_left_in[12]:5 0.0045 +30 chanx_left_in[12]:4 mux_right_track_0\/mux_l1_in_2_:A0 0.152 +31 chanx_left_in[12]:35 chanx_left_in[12]:34 0.0001065333 +32 chanx_left_in[12]:34 chanx_left_in[12]:33 0.004753266 +33 chanx_left_in[12]:29 chanx_left_in[12]:28 0.0001065333 +34 chanx_left_in[12]:28 chanx_left_in[12]:27 0.001584292 + +*END + +*D_NET chanx_left_in[18] 0.02287941 //LENGTH 155.585 LUMPCC 0.008470887 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 38.080 +*I mux_bottom_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 104.325 30.940 +*I ropt_mt_inst_811:A I *L 0.001767 *C 134.780 47.600 +*I mux_right_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 111.420 41.820 +*N chanx_left_in[18]:4 *C 111.420 41.820 +*N chanx_left_in[18]:5 *C 134.743 47.600 +*N chanx_left_in[18]:6 *C 127.005 47.600 +*N chanx_left_in[18]:7 *C 126.960 47.555 +*N chanx_left_in[18]:8 *C 126.960 44.925 +*N chanx_left_in[18]:9 *C 126.915 44.880 +*N chanx_left_in[18]:10 *C 121.440 44.880 +*N chanx_left_in[18]:11 *C 121.440 44.835 +*N chanx_left_in[18]:12 *C 121.440 41.525 +*N chanx_left_in[18]:13 *C 121.395 41.480 +*N chanx_left_in[18]:14 *C 111.320 41.480 +*N chanx_left_in[18]:15 *C 104.465 41.480 +*N chanx_left_in[18]:16 *C 104.420 41.435 +*N chanx_left_in[18]:17 *C 104.325 30.940 +*N chanx_left_in[18]:18 *C 104.420 30.985 +*N chanx_left_in[18]:19 *C 104.420 40.120 +*N chanx_left_in[18]:20 *C 104.413 40.120 +*N chanx_left_in[18]:21 *C 55.355 40.120 +*N chanx_left_in[18]:22 *C 5.527 40.120 +*N chanx_left_in[18]:23 *C 5.520 40.062 +*N chanx_left_in[18]:24 *C 5.520 38.138 +*N chanx_left_in[18]:25 *C 5.513 38.080 + +*CAP +0 chanx_left_in[18] 0.0003103117 +1 mux_bottom_track_25\/mux_l2_in_1_:A1 1e-06 +2 ropt_mt_inst_811:A 1e-06 +3 mux_right_track_24\/mux_l2_in_1_:A1 1e-06 +4 chanx_left_in[18]:4 5.210797e-05 +5 chanx_left_in[18]:5 0.0004188516 +6 chanx_left_in[18]:6 0.0004188516 +7 chanx_left_in[18]:7 0.0001639099 +8 chanx_left_in[18]:8 0.0001639099 +9 chanx_left_in[18]:9 0.0003065474 +10 chanx_left_in[18]:10 0.0003402721 +11 chanx_left_in[18]:11 0.0001918996 +12 chanx_left_in[18]:12 0.0001918996 +13 chanx_left_in[18]:13 0.000597687 +14 chanx_left_in[18]:14 0.001093718 +15 chanx_left_in[18]:15 0.0004701364 +16 chanx_left_in[18]:16 7.9914e-05 +17 chanx_left_in[18]:17 2.672593e-05 +18 chanx_left_in[18]:18 0.0004598665 +19 chanx_left_in[18]:19 0.0005745594 +20 chanx_left_in[18]:20 0.002011228 +21 chanx_left_in[18]:21 0.003999796 +22 chanx_left_in[18]:22 0.001988568 +23 chanx_left_in[18]:23 0.0001172243 +24 chanx_left_in[18]:24 0.0001172243 +25 chanx_left_in[18]:25 0.0003103117 +26 chanx_left_in[18]:22 chanx_right_in[4]:8 0.0001374466 +27 chanx_left_in[18]:22 chanx_right_in[4]:15 0.0001548962 +28 chanx_left_in[18]:21 chanx_right_in[4]:15 0.0001374466 +29 chanx_left_in[18]:21 chanx_right_in[4]:20 0.0001548962 +30 chanx_left_in[18]:20 chanx_right_in[13]:31 0.0003913729 +31 chanx_left_in[18]:20 chanx_right_in[13]:32 0.0005467659 +32 chanx_left_in[18]:22 chanx_right_in[13]:25 1.533722e-05 +33 chanx_left_in[18]:22 chanx_right_in[13]:27 3.248805e-05 +34 chanx_left_in[18]:21 chanx_right_in[13]:26 1.533722e-05 +35 chanx_left_in[18]:21 chanx_right_in[13]:27 0.0003913729 +36 chanx_left_in[18]:21 chanx_right_in[13]:31 0.000579254 +37 chanx_left_in[18]:20 chanx_left_in[6]:19 0.0004930631 +38 chanx_left_in[18]:20 chanx_left_in[6]:21 6.720737e-05 +39 chanx_left_in[18]:20 chanx_left_in[6]:23 0.000275008 +40 chanx_left_in[18]:22 chanx_left_in[6]:24 0.0003107119 +41 chanx_left_in[18]:21 chanx_left_in[6]:20 0.0004930631 +42 chanx_left_in[18]:21 chanx_left_in[6]:22 6.720737e-05 +43 chanx_left_in[18]:21 chanx_left_in[6]:23 0.0003107119 +44 chanx_left_in[18]:21 chanx_left_in[6]:24 0.000275008 +45 chanx_left_in[18]:19 prog_clk[0]:153 8.889866e-06 +46 chanx_left_in[18]:19 prog_clk[0]:150 1.010365e-05 +47 chanx_left_in[18]:20 prog_clk[0]:282 3.022681e-06 +48 chanx_left_in[18]:20 prog_clk[0]:516 0.0001234903 +49 chanx_left_in[18]:22 prog_clk[0]:517 0.0001884995 +50 chanx_left_in[18]:16 prog_clk[0]:150 5.943323e-07 +51 chanx_left_in[18]:18 prog_clk[0]:154 8.295534e-06 +52 chanx_left_in[18]:18 prog_clk[0]:153 1.010365e-05 +53 chanx_left_in[18]:21 prog_clk[0]:283 3.022681e-06 +54 chanx_left_in[18]:21 prog_clk[0]:517 0.0001234903 +55 chanx_left_in[18]:21 prog_clk[0]:516 0.0001884995 +56 chanx_left_in[18]:22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001371107 +57 chanx_left_in[18]:21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001371107 +58 chanx_left_in[18]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.052788e-05 +59 chanx_left_in[18]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.052788e-05 +60 chanx_left_in[18]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.550647e-05 +61 chanx_left_in[18]:14 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.550647e-05 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:25 0.000670925 +1 chanx_left_in[18]:19 chanx_left_in[18]:18 0.00815625 +2 chanx_left_in[18]:19 chanx_left_in[18]:16 0.001174107 +3 chanx_left_in[18]:20 chanx_left_in[18]:19 0.00341 +4 chanx_left_in[18]:23 chanx_left_in[18]:22 0.00341 +5 chanx_left_in[18]:22 chanx_left_in[18]:21 0.007806308 +6 chanx_left_in[18]:24 chanx_left_in[18]:23 0.00171875 +7 chanx_left_in[18]:25 chanx_left_in[18]:24 0.00341 +8 chanx_left_in[18]:13 chanx_left_in[18]:12 0.0045 +9 chanx_left_in[18]:12 chanx_left_in[18]:11 0.002955357 +10 chanx_left_in[18]:10 chanx_left_in[18]:9 0.004888393 +11 chanx_left_in[18]:11 chanx_left_in[18]:10 0.0045 +12 chanx_left_in[18]:9 chanx_left_in[18]:8 0.0045 +13 chanx_left_in[18]:8 chanx_left_in[18]:7 0.002348214 +14 chanx_left_in[18]:6 chanx_left_in[18]:5 0.006908482 +15 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0045 +16 chanx_left_in[18]:5 ropt_mt_inst_811:A 0.152 +17 chanx_left_in[18]:15 chanx_left_in[18]:14 0.006120536 +18 chanx_left_in[18]:16 chanx_left_in[18]:15 0.0045 +19 chanx_left_in[18]:4 mux_right_track_24\/mux_l2_in_1_:A1 0.152 +20 chanx_left_in[18]:17 mux_bottom_track_25\/mux_l2_in_1_:A1 0.152 +21 chanx_left_in[18]:18 chanx_left_in[18]:17 0.0045 +22 chanx_left_in[18]:14 chanx_left_in[18]:13 0.008995537 +23 chanx_left_in[18]:14 chanx_left_in[18]:4 0.0003035715 +24 chanx_left_in[18]:21 chanx_left_in[18]:20 0.007685674 + +*END + +*D_NET chany_bottom_in[0] 0.006710667 //LENGTH 49.755 LUMPCC 0.002606557 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 82.340 1.290 +*I mux_left_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 82.705 39.780 +*I mux_right_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 91.640 39.780 +*N chany_bottom_in[0]:3 *C 82.400 39.440 +*N chany_bottom_in[0]:4 *C 91.603 39.780 +*N chany_bottom_in[0]:5 *C 82.845 39.780 +*N chany_bottom_in[0]:6 *C 82.800 39.780 +*N chany_bottom_in[0]:7 *C 82.800 39.440 +*N chany_bottom_in[0]:8 *C 82.800 39.440 +*N chany_bottom_in[0]:9 *C 82.800 39.433 +*N chany_bottom_in[0]:10 *C 82.800 2.048 +*N chany_bottom_in[0]:11 *C 82.785 2.040 +*N chany_bottom_in[0]:12 *C 82.343 2.040 +*N chany_bottom_in[0]:13 *C 82.340 1.983 + +*CAP +0 chany_bottom_in[0] 5.652329e-05 +1 mux_left_track_3\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A1 1e-06 +3 chany_bottom_in[0]:3 0.0001308332 +4 chany_bottom_in[0]:4 0.0005722158 +5 chany_bottom_in[0]:5 0.0005722158 +6 chany_bottom_in[0]:6 5.642987e-05 +7 chany_bottom_in[0]:7 6.046368e-05 +8 chany_bottom_in[0]:8 0.0001308332 +9 chany_bottom_in[0]:9 0.001159522 +10 chany_bottom_in[0]:10 0.001159522 +11 chany_bottom_in[0]:11 7.351409e-05 +12 chany_bottom_in[0]:12 7.351409e-05 +13 chany_bottom_in[0]:13 5.652329e-05 +14 chany_bottom_in[0] chany_bottom_in[9] 1.818287e-06 +15 chany_bottom_in[0]:9 chany_bottom_in[9]:13 0.0007173944 +16 chany_bottom_in[0]:11 chany_bottom_in[9]:16 1.615054e-06 +17 chany_bottom_in[0]:10 chany_bottom_in[9]:14 0.0007173944 +18 chany_bottom_in[0]:13 chany_bottom_in[9]:17 1.818287e-06 +19 chany_bottom_in[0]:12 chany_bottom_in[9]:15 1.615054e-06 +20 chany_bottom_in[0]:9 chany_bottom_in[16]:18 0.0005824505 +21 chany_bottom_in[0]:10 chany_bottom_in[16]:19 0.0005824505 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:13 0.0006183035 +1 chany_bottom_in[0]:4 mux_right_track_24\/mux_l1_in_0_:A1 0.152 +2 chany_bottom_in[0]:5 mux_left_track_3\/mux_l1_in_1_:A1 0.152 +3 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.007819197 +4 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.0045 +5 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.0001634616 +6 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.00341 +7 chany_bottom_in[0]:8 chany_bottom_in[0]:3 5.69697e-05 +8 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.00341 +9 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.00341 +10 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.005856983 +11 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.00341 +12 chany_bottom_in[0]:12 chany_bottom_in[0]:11 6.499219e-05 + +*END + +*D_NET chany_bottom_in[11] 0.01308781 //LENGTH 96.545 LUMPCC 0.001589401 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 86.480 1.290 +*I mux_right_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 66.415 64.600 +*I mux_left_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 63.770 71.740 +*N chany_bottom_in[11]:3 *C 63.808 71.740 +*N chany_bottom_in[11]:4 *C 67.575 71.740 +*N chany_bottom_in[11]:5 *C 67.620 71.695 +*N chany_bottom_in[11]:6 *C 66.453 64.600 +*N chany_bottom_in[11]:7 *C 67.575 64.600 +*N chany_bottom_in[11]:8 *C 67.620 64.600 +*N chany_bottom_in[11]:9 *C 67.620 53.778 +*N chany_bottom_in[11]:10 *C 67.627 53.720 +*N chany_bottom_in[11]:11 *C 72.660 53.720 +*N chany_bottom_in[11]:12 *C 72.680 53.713 +*N chany_bottom_in[11]:13 *C 72.680 4.768 +*N chany_bottom_in[11]:14 *C 72.700 4.760 +*N chany_bottom_in[11]:15 *C 86.473 4.760 +*N chany_bottom_in[11]:16 *C 86.480 4.703 + +*CAP +0 chany_bottom_in[11] 0.000202929 +1 mux_right_track_2\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_25\/mux_l1_in_1_:A0 1e-06 +3 chany_bottom_in[11]:3 0.0002892829 +4 chany_bottom_in[11]:4 0.0002892829 +5 chany_bottom_in[11]:5 0.0003112862 +6 chany_bottom_in[11]:6 0.0001008536 +7 chany_bottom_in[11]:7 0.0001008536 +8 chany_bottom_in[11]:8 0.0007609032 +9 chany_bottom_in[11]:9 0.0004178648 +10 chany_bottom_in[11]:10 0.0004074866 +11 chany_bottom_in[11]:11 0.0004074866 +12 chany_bottom_in[11]:12 0.002831342 +13 chany_bottom_in[11]:13 0.002831342 +14 chany_bottom_in[11]:14 0.001171281 +15 chany_bottom_in[11]:15 0.001171281 +16 chany_bottom_in[11]:16 0.000202929 +17 chany_bottom_in[11]:9 chanx_left_in[16]:33 3.293736e-05 +18 chany_bottom_in[11]:12 chanx_left_in[16]:30 0.0003936388 +19 chany_bottom_in[11]:13 chanx_left_in[16]:29 0.0003936388 +20 chany_bottom_in[11]:8 chanx_left_in[16]:34 3.293736e-05 +21 chany_bottom_in[11]:9 chany_bottom_in[17]:11 0.000244857 +22 chany_bottom_in[11]:9 chany_bottom_in[17]:15 5.360953e-06 +23 chany_bottom_in[11]:12 chany_bottom_in[17]:16 6.014337e-06 +24 chany_bottom_in[11]:13 chany_bottom_in[17]:17 6.014337e-06 +25 chany_bottom_in[11]:8 chany_bottom_in[17]:14 5.360953e-06 +26 chany_bottom_in[11]:8 chany_bottom_in[17]:11 0.0001118921 +27 chany_bottom_in[11]:8 chany_bottom_in[17]:10 0.000244857 +28 chany_bottom_in[11]:5 chany_bottom_in[17]:10 0.0001118921 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:16 0.003046875 +1 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.009662947 +2 chany_bottom_in[11]:10 chany_bottom_in[11]:9 0.00341 +3 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.000788425 +4 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.00341 +5 chany_bottom_in[11]:14 chany_bottom_in[11]:13 0.00341 +6 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.007668049 +7 chany_bottom_in[11]:16 chany_bottom_in[11]:15 0.00341 +8 chany_bottom_in[11]:15 chany_bottom_in[11]:14 0.002157692 +9 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.001002232 +10 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.0045 +11 chany_bottom_in[11]:8 chany_bottom_in[11]:5 0.006334822 +12 chany_bottom_in[11]:6 mux_right_track_2\/mux_l1_in_0_:A0 0.152 +13 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.00336384 +14 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.0045 +15 chany_bottom_in[11]:3 mux_left_track_25\/mux_l1_in_1_:A0 0.152 + +*END + +*D_NET bottom_left_grid_pin_41_[0] 0.01914322 //LENGTH 122.725 LUMPCC 0.005843262 DR + +*CONN +*P bottom_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 14.280 +*I mux_bottom_track_3\/mux_l1_in_2_:A1 I *L 0.00198 *C 14.360 41.820 +*I mux_bottom_track_7\/mux_l1_in_2_:A1 I *L 0.00198 *C 18.765 41.820 +*I mux_bottom_track_39\/mux_l1_in_0_:A1 I *L 0.00198 *C 46.560 12.580 +*I mux_bottom_track_23\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.975 33.320 +*N bottom_left_grid_pin_41_[0]:5 *C 82.975 33.320 +*N bottom_left_grid_pin_41_[0]:6 *C 82.800 33.320 +*N bottom_left_grid_pin_41_[0]:7 *C 82.800 33.320 +*N bottom_left_grid_pin_41_[0]:8 *C 82.793 33.320 +*N bottom_left_grid_pin_41_[0]:9 *C 55.220 33.320 +*N bottom_left_grid_pin_41_[0]:10 *C 55.200 33.312 +*N bottom_left_grid_pin_41_[0]:11 *C 55.200 14.288 +*N bottom_left_grid_pin_41_[0]:12 *C 55.180 14.280 +*N bottom_left_grid_pin_41_[0]:13 *C 46.523 12.580 +*N bottom_left_grid_pin_41_[0]:14 *C 46.045 12.580 +*N bottom_left_grid_pin_41_[0]:15 *C 46.000 12.625 +*N bottom_left_grid_pin_41_[0]:16 *C 46.000 14.223 +*N bottom_left_grid_pin_41_[0]:17 *C 46.000 14.280 +*N bottom_left_grid_pin_41_[0]:18 *C 18.727 41.820 +*N bottom_left_grid_pin_41_[0]:19 *C 14.398 41.820 +*N bottom_left_grid_pin_41_[0]:20 *C 17.480 41.820 +*N bottom_left_grid_pin_41_[0]:21 *C 17.480 41.775 +*N bottom_left_grid_pin_41_[0]:22 *C 17.480 33.365 +*N bottom_left_grid_pin_41_[0]:23 *C 17.525 33.320 +*N bottom_left_grid_pin_41_[0]:24 *C 30.775 33.320 +*N bottom_left_grid_pin_41_[0]:25 *C 30.820 33.275 +*N bottom_left_grid_pin_41_[0]:26 *C 30.820 14.338 +*N bottom_left_grid_pin_41_[0]:27 *C 30.820 14.280 + +*CAP +0 bottom_left_grid_pin_41_[0] 7.843228e-05 +1 mux_bottom_track_3\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_7\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_39\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_23\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_41_[0]:5 5.514311e-05 +6 bottom_left_grid_pin_41_[0]:6 5.734278e-05 +7 bottom_left_grid_pin_41_[0]:7 3.498828e-05 +8 bottom_left_grid_pin_41_[0]:8 0.001589729 +9 bottom_left_grid_pin_41_[0]:9 0.001589729 +10 bottom_left_grid_pin_41_[0]:10 0.001466873 +11 bottom_left_grid_pin_41_[0]:11 0.001466873 +12 bottom_left_grid_pin_41_[0]:12 0.0003674348 +13 bottom_left_grid_pin_41_[0]:13 6.092741e-05 +14 bottom_left_grid_pin_41_[0]:14 6.092741e-05 +15 bottom_left_grid_pin_41_[0]:15 9.624449e-05 +16 bottom_left_grid_pin_41_[0]:16 9.624449e-05 +17 bottom_left_grid_pin_41_[0]:17 0.001243724 +18 bottom_left_grid_pin_41_[0]:18 0.0001021319 +19 bottom_left_grid_pin_41_[0]:19 0.0002133661 +20 bottom_left_grid_pin_41_[0]:20 0.0003519192 +21 bottom_left_grid_pin_41_[0]:21 0.0004648153 +22 bottom_left_grid_pin_41_[0]:22 0.0004648153 +23 bottom_left_grid_pin_41_[0]:23 0.0008414524 +24 bottom_left_grid_pin_41_[0]:24 0.0008414524 +25 bottom_left_grid_pin_41_[0]:25 0.0003983357 +26 bottom_left_grid_pin_41_[0]:26 0.0003983357 +27 bottom_left_grid_pin_41_[0]:27 0.0009547217 +28 bottom_left_grid_pin_41_[0]:9 chanx_right_in[16]:28 0.0002736265 +29 bottom_left_grid_pin_41_[0]:9 chanx_right_in[16]:33 5.328385e-05 +30 bottom_left_grid_pin_41_[0]:8 chanx_right_in[16]:33 0.0002736265 +31 bottom_left_grid_pin_41_[0]:8 chanx_right_in[16]:34 5.328385e-05 +32 bottom_left_grid_pin_41_[0]:17 prog_clk[0]:317 4.294426e-05 +33 bottom_left_grid_pin_41_[0]:17 prog_clk[0]:504 3.10132e-05 +34 bottom_left_grid_pin_41_[0]:17 prog_clk[0]:544 3.228796e-05 +35 bottom_left_grid_pin_41_[0]:17 prog_clk[0]:556 9.288247e-06 +36 bottom_left_grid_pin_41_[0]:21 prog_clk[0]:491 5.562029e-07 +37 bottom_left_grid_pin_41_[0]:22 prog_clk[0]:495 5.562029e-07 +38 bottom_left_grid_pin_41_[0]:25 prog_clk[0]:486 1.023789e-05 +39 bottom_left_grid_pin_41_[0]:26 prog_clk[0]:487 1.023789e-05 +40 bottom_left_grid_pin_41_[0]:27 prog_clk[0]:505 3.10132e-05 +41 bottom_left_grid_pin_41_[0]:27 prog_clk[0]:545 3.228796e-05 +42 bottom_left_grid_pin_41_[0]:27 prog_clk[0]:557 9.288247e-06 +43 bottom_left_grid_pin_41_[0]:12 prog_clk[0]:316 4.294426e-05 +44 bottom_left_grid_pin_41_[0]:9 prog_clk[0]:195 5.078315e-05 +45 bottom_left_grid_pin_41_[0]:9 prog_clk[0]:293 0.0002593952 +46 bottom_left_grid_pin_41_[0]:8 prog_clk[0]:194 5.078315e-05 +47 bottom_left_grid_pin_41_[0]:8 prog_clk[0]:292 0.0002593952 +48 bottom_left_grid_pin_41_[0]:11 chany_bottom_in[15]:17 0.000402027 +49 bottom_left_grid_pin_41_[0]:10 chany_bottom_in[15]:16 0.000402027 +50 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_35_[0]:10 1.34528e-05 +51 bottom_left_grid_pin_41_[0]:23 bottom_left_grid_pin_35_[0]:22 2.622661e-05 +52 bottom_left_grid_pin_41_[0]:24 bottom_left_grid_pin_35_[0]:23 2.622661e-05 +53 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_35_[0]:21 2.119453e-06 +54 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_35_[0]:23 0.0004778961 +55 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_35_[0]:22 2.119453e-06 +56 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_35_[0]:24 0.0004778961 +57 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_35_[0]:25 1.34528e-05 +58 bottom_left_grid_pin_41_[0] bottom_left_grid_pin_39_[0] 3.624918e-06 +59 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_39_[0]:22 2.155984e-06 +60 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_39_[0]:12 0.0001346425 +61 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_39_[0]:20 0.0003533006 +62 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_39_[0]:20 0.0001346425 +63 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_39_[0]:21 0.0003533006 +64 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_39_[0] 2.155984e-06 +65 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_39_[0]:22 3.624918e-06 +66 bottom_left_grid_pin_41_[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 1.291931e-05 +67 bottom_left_grid_pin_41_[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.952394e-05 +68 bottom_left_grid_pin_41_[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0005134033 +69 bottom_left_grid_pin_41_[0]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 1.291931e-05 +70 bottom_left_grid_pin_41_[0]:27 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 5.952394e-05 +71 bottom_left_grid_pin_41_[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0005134033 +72 bottom_left_grid_pin_41_[0]:23 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.699848e-05 +73 bottom_left_grid_pin_41_[0]:24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.699848e-05 +74 bottom_left_grid_pin_41_[0]:21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.992357e-05 +75 bottom_left_grid_pin_41_[0]:22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.992357e-05 + +*RES +0 bottom_left_grid_pin_41_[0] bottom_left_grid_pin_41_[0]:27 0.0001676333 +1 bottom_left_grid_pin_41_[0]:16 bottom_left_grid_pin_41_[0]:15 0.001426339 +2 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_41_[0]:16 0.00341 +3 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_41_[0]:12 0.0014382 +4 bottom_left_grid_pin_41_[0]:14 bottom_left_grid_pin_41_[0]:13 0.0004263393 +5 bottom_left_grid_pin_41_[0]:15 bottom_left_grid_pin_41_[0]:14 0.0045 +6 bottom_left_grid_pin_41_[0]:13 mux_bottom_track_39\/mux_l1_in_0_:A1 0.152 +7 bottom_left_grid_pin_41_[0]:20 bottom_left_grid_pin_41_[0]:19 0.002752232 +8 bottom_left_grid_pin_41_[0]:20 bottom_left_grid_pin_41_[0]:18 0.001113839 +9 bottom_left_grid_pin_41_[0]:21 bottom_left_grid_pin_41_[0]:20 0.0045 +10 bottom_left_grid_pin_41_[0]:23 bottom_left_grid_pin_41_[0]:22 0.0045 +11 bottom_left_grid_pin_41_[0]:22 bottom_left_grid_pin_41_[0]:21 0.007508928 +12 bottom_left_grid_pin_41_[0]:24 bottom_left_grid_pin_41_[0]:23 0.01183036 +13 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_41_[0]:24 0.0045 +14 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_41_[0]:25 0.01690848 +15 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_41_[0]:26 0.00341 +16 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_41_[0]:17 0.0023782 +17 bottom_left_grid_pin_41_[0]:12 bottom_left_grid_pin_41_[0]:11 0.00341 +18 bottom_left_grid_pin_41_[0]:11 bottom_left_grid_pin_41_[0]:10 0.002980583 +19 bottom_left_grid_pin_41_[0]:9 bottom_left_grid_pin_41_[0]:8 0.004319692 +20 bottom_left_grid_pin_41_[0]:10 bottom_left_grid_pin_41_[0]:9 0.00341 +21 bottom_left_grid_pin_41_[0]:7 bottom_left_grid_pin_41_[0]:6 0.0045 +22 bottom_left_grid_pin_41_[0]:8 bottom_left_grid_pin_41_[0]:7 0.00341 +23 bottom_left_grid_pin_41_[0]:6 bottom_left_grid_pin_41_[0]:5 9.51087e-05 +24 bottom_left_grid_pin_41_[0]:5 mux_bottom_track_23\/mux_l1_in_0_:A0 0.152 +25 bottom_left_grid_pin_41_[0]:19 mux_bottom_track_3\/mux_l1_in_2_:A1 0.152 +26 bottom_left_grid_pin_41_[0]:18 mux_bottom_track_7\/mux_l1_in_2_:A1 0.152 + +*END + +*D_NET chany_bottom_out[1] 0.002926226 //LENGTH 25.325 LUMPCC 0.000466362 DR + +*CONN +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 39.100 4.080 +*P chany_bottom_out[1] O *L 0.7423 *C 59.800 1.325 +*N chany_bottom_out[1]:2 *C 59.800 1.655 +*N chany_bottom_out[1]:3 *C 59.755 1.700 +*N chany_bottom_out[1]:4 *C 52.440 1.700 +*N chany_bottom_out[1]:5 *C 52.440 1.360 +*N chany_bottom_out[1]:6 *C 39.100 1.360 +*N chany_bottom_out[1]:7 *C 39.100 1.700 +*N chany_bottom_out[1]:8 *C 39.100 1.745 +*N chany_bottom_out[1]:9 *C 39.100 4.035 +*N chany_bottom_out[1]:10 *C 39.100 4.080 + +*CAP +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[1] 3.659475e-05 +2 chany_bottom_out[1]:2 3.659475e-05 +3 chany_bottom_out[1]:3 0.0003135942 +4 chany_bottom_out[1]:4 0.0003373637 +5 chany_bottom_out[1]:5 0.0007036233 +6 chany_bottom_out[1]:6 0.0007063485 +7 chany_bottom_out[1]:7 5.724336e-05 +8 chany_bottom_out[1]:8 0.0001183761 +9 chany_bottom_out[1]:9 0.0001183761 +10 chany_bottom_out[1]:10 3.074876e-05 +11 chany_bottom_out[1]:3 ropt_net_172:7 0.000233181 +12 chany_bottom_out[1]:4 ropt_net_172:8 0.000233181 + +*RES +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[1]:10 0.152 +1 chany_bottom_out[1]:10 chany_bottom_out[1]:9 0.0045 +2 chany_bottom_out[1]:9 chany_bottom_out[1]:8 0.002044643 +3 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0003035715 +4 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0045 +5 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +6 chany_bottom_out[1]:2 chany_bottom_out[1] 0.0002946429 +7 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.01191071 +8 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0003035715 +9 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.00653125 + +*END + +*D_NET chany_bottom_out[9] 0.0008573011 //LENGTH 6.040 LUMPCC 0.0003878766 DR + +*CONN +*I mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 54.685 6.460 +*P chany_bottom_out[9] O *L 0.7423 *C 54.280 1.290 +*N chany_bottom_out[9]:2 *C 54.280 6.415 +*N chany_bottom_out[9]:3 *C 54.303 6.460 +*N chany_bottom_out[9]:4 *C 54.670 6.460 + +*CAP +0 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[9] 0.0001722029 +2 chany_bottom_out[9]:2 0.0001722029 +3 chany_bottom_out[9]:3 6.200931e-05 +4 chany_bottom_out[9]:4 6.200931e-05 +5 chany_bottom_out[9] ropt_net_172:9 0.0001234504 +6 chany_bottom_out[9]:2 ropt_net_172:10 0.0001234504 +7 chany_bottom_out[9] mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.048794e-05 +8 chany_bottom_out[9]:2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.048794e-05 + +*RES +0 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.0001997283 +2 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +3 chany_bottom_out[9]:2 chany_bottom_out[9] 0.004575893 + +*END + +*D_NET chanx_left_out[0] 0.001898638 //LENGTH 16.890 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 9.145 72.080 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 80.240 +*N chanx_left_out[0]:2 *C 8.732 80.240 +*N chanx_left_out[0]:3 *C 8.740 80.183 +*N chanx_left_out[0]:4 *C 8.740 72.125 +*N chanx_left_out[0]:5 *C 8.763 72.080 +*N chanx_left_out[0]:6 *C 9.130 72.080 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 0.0004883181 +2 chanx_left_out[0]:2 0.0004883181 +3 chanx_left_out[0]:3 0.0004183614 +4 chanx_left_out[0]:4 0.0004183614 +5 chanx_left_out[0]:5 4.213931e-05 +6 chanx_left_out[0]:6 4.213931e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:6 0.152 +1 chanx_left_out[0]:6 chanx_left_out[0]:5 0.0001997283 +2 chanx_left_out[0]:5 chanx_left_out[0]:4 0.0045 +3 chanx_left_out[0]:4 chanx_left_out[0]:3 0.007194197 +4 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +5 chanx_left_out[0]:2 chanx_left_out[0] 0.001175392 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.001245114 //LENGTH 8.915 LUMPCC 0.0003225225 DR + +*CONN +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 70.685 14.960 +*I mem_bottom_track_35\/FTB_32__57:A I *L 0.001746 *C 69.460 12.240 +*I mux_bottom_track_35\/mux_l2_in_0_:S I *L 0.00357 *C 65.420 12.240 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 65.458 12.240 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 69.422 12.240 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 69.460 12.285 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 69.460 14.915 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 69.505 14.960 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 70.648 14.960 + +*CAP +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_35\/FTB_32__57:A 1e-06 +2 mux_bottom_track_35\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 0.0001766518 +4 mux_tree_tapbuf_size2_4_sram[1]:4 0.0001766518 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.0001875877 +6 mux_tree_tapbuf_size2_4_sram[1]:6 0.0001875877 +7 mux_tree_tapbuf_size2_4_sram[1]:7 9.555624e-05 +8 mux_tree_tapbuf_size2_4_sram[1]:8 9.555624e-05 +9 mux_tree_tapbuf_size2_4_sram[1]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001612613 +10 mux_tree_tapbuf_size2_4_sram[1]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001612613 + +*RES +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:4 mem_bottom_track_35\/FTB_32__57:A 0.152 +2 mux_tree_tapbuf_size2_4_sram[1]:4 mux_tree_tapbuf_size2_4_sram[1]:3 0.003540179 +3 mux_tree_tapbuf_size2_4_sram[1]:3 mux_bottom_track_35\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_4_sram[1]:6 mux_tree_tapbuf_size2_4_sram[1]:5 0.002348214 +7 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.001020089 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_5_ccff_tail[0] 0.004911719 //LENGTH 35.485 LUMPCC 0.0006427268 DR + +*CONN +*I mem_bottom_track_37\/FTB_33__58:X O *L 0 *C 68.305 8.840 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 43.410 6.460 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 *C 43.448 6.460 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 *C 52.855 6.460 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 *C 52.900 6.415 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 *C 52.900 3.785 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 *C 52.945 3.740 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 *C 60.260 3.740 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 *C 60.260 4.420 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 *C 61.595 4.420 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:10 *C 61.640 4.465 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:11 *C 61.640 6.062 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 *C 61.648 6.120 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 *C 68.532 6.120 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:14 *C 68.540 6.178 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:15 *C 68.540 8.795 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:16 *C 68.540 8.840 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:17 *C 68.305 8.840 + +*CAP +0 mem_bottom_track_37\/FTB_33__58:X 1e-06 +1 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.0006556893 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0006556893 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.0001763274 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0001763274 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0003613816 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0004039953 +8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 0.0001847037 +9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 0.00014209 +10 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:10 0.0001150652 +11 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:11 0.0001150652 +12 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 0.0003613207 +13 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 0.0003613207 +14 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:14 0.0002185832 +15 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:15 0.0002185832 +16 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:16 6.213181e-05 +17 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:17 5.871856e-05 +18 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 prog_clk[0]:324 0.0001529975 +19 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 prog_clk[0]:218 0.0001529975 +20 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001683658 +21 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001683658 + +*RES +0 mem_bottom_track_37\/FTB_33__58:X mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:17 0.152 +1 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.008399554 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 0.001191964 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:10 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:9 0.0045 +8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:11 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:10 0.001426339 +9 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:11 0.00341 +10 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:14 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 0.00341 +11 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:13 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:12 0.00107865 +12 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:16 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:15 0.0045 +13 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:15 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:14 0.002337054 +14 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:17 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:16 0.0001277174 +15 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.006531251 +16 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0006071428 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[1] 0.003336968 //LENGTH 25.535 LUMPCC 9.014861e-05 DR + +*CONN +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 71.145 28.220 +*I mem_bottom_track_19\/FTB_17__42:A I *L 0.001746 *C 66.240 31.280 +*I mux_bottom_track_19\/mux_l2_in_0_:S I *L 0.00357 *C 56.220 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:3 *C 56.258 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:4 *C 58.375 25.840 +*N mux_tree_tapbuf_size3_4_sram[1]:5 *C 58.420 25.885 +*N mux_tree_tapbuf_size3_4_sram[1]:6 *C 58.420 31.235 +*N mux_tree_tapbuf_size3_4_sram[1]:7 *C 58.465 31.280 +*N mux_tree_tapbuf_size3_4_sram[1]:8 *C 66.240 31.258 +*N mux_tree_tapbuf_size3_4_sram[1]:9 *C 66.240 30.940 +*N mux_tree_tapbuf_size3_4_sram[1]:10 *C 71.255 30.940 +*N mux_tree_tapbuf_size3_4_sram[1]:11 *C 71.300 30.895 +*N mux_tree_tapbuf_size3_4_sram[1]:12 *C 71.300 28.265 +*N mux_tree_tapbuf_size3_4_sram[1]:13 *C 71.300 28.220 +*N mux_tree_tapbuf_size3_4_sram[1]:14 *C 71.145 28.220 + +*CAP +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_19\/FTB_17__42:A 1e-06 +2 mux_bottom_track_19\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_4_sram[1]:3 0.0001189558 +4 mux_tree_tapbuf_size3_4_sram[1]:4 0.0001189558 +5 mux_tree_tapbuf_size3_4_sram[1]:5 0.0003374371 +6 mux_tree_tapbuf_size3_4_sram[1]:6 0.0003374371 +7 mux_tree_tapbuf_size3_4_sram[1]:7 0.0006029778 +8 mux_tree_tapbuf_size3_4_sram[1]:8 0.0006313234 +9 mux_tree_tapbuf_size3_4_sram[1]:9 0.0003368778 +10 mux_tree_tapbuf_size3_4_sram[1]:10 0.0003085322 +11 mux_tree_tapbuf_size3_4_sram[1]:11 0.0001753284 +12 mux_tree_tapbuf_size3_4_sram[1]:12 0.0001753284 +13 mux_tree_tapbuf_size3_4_sram[1]:13 5.254843e-05 +14 mux_tree_tapbuf_size3_4_sram[1]:14 4.811736e-05 +15 mux_tree_tapbuf_size3_4_sram[1]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.507431e-05 +16 mux_tree_tapbuf_size3_4_sram[1]:3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.507431e-05 + +*RES +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_4_sram[1]:14 0.152 +1 mux_tree_tapbuf_size3_4_sram[1]:8 mem_bottom_track_19\/FTB_17__42:A 0.152 +2 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size3_4_sram[1]:7 0.006941964 +3 mux_tree_tapbuf_size3_4_sram[1]:10 mux_tree_tapbuf_size3_4_sram[1]:9 0.004477679 +4 mux_tree_tapbuf_size3_4_sram[1]:11 mux_tree_tapbuf_size3_4_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size3_4_sram[1]:13 mux_tree_tapbuf_size3_4_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size3_4_sram[1]:12 mux_tree_tapbuf_size3_4_sram[1]:11 0.002348214 +7 mux_tree_tapbuf_size3_4_sram[1]:14 mux_tree_tapbuf_size3_4_sram[1]:13 8.423914e-05 +8 mux_tree_tapbuf_size3_4_sram[1]:7 mux_tree_tapbuf_size3_4_sram[1]:6 0.0045 +9 mux_tree_tapbuf_size3_4_sram[1]:6 mux_tree_tapbuf_size3_4_sram[1]:5 0.004776786 +10 mux_tree_tapbuf_size3_4_sram[1]:4 mux_tree_tapbuf_size3_4_sram[1]:3 0.001890625 +11 mux_tree_tapbuf_size3_4_sram[1]:5 mux_tree_tapbuf_size3_4_sram[1]:4 0.0045 +12 mux_tree_tapbuf_size3_4_sram[1]:3 mux_bottom_track_19\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size3_4_sram[1]:9 mux_tree_tapbuf_size3_4_sram[1]:8 0.0002834821 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_4_ccff_tail[0] 0.000519035 //LENGTH 3.760 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_19\/FTB_17__42:X O *L 0 *C 69.235 31.960 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 70.555 33.660 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 *C 70.555 33.660 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 *C 70.380 33.660 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 *C 70.380 33.615 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 *C 70.380 32.005 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 *C 70.335 31.960 +*N mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 *C 69.273 31.960 + +*CAP +0 mem_bottom_track_19\/FTB_17__42:X 1e-06 +1 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 5.095407e-05 +3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 5.551751e-05 +4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 0.0001118193 +5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 0.0001118193 +6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 9.346239e-05 +7 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 9.346239e-05 + +*RES +0 mem_bottom_track_19\/FTB_17__42:X mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 0.0009486608 +2 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_4_ccff_tail[0]:2 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[1] 0.002839315 //LENGTH 22.830 LUMPCC 0.0004072704 DR + +*CONN +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 36.645 72.080 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 34.675 69.700 +*I mux_bottom_track_11\/mux_l2_in_0_:S I *L 0.00357 *C 33.480 63.240 +*I mux_bottom_track_11\/mux_l2_in_1_:S I *L 0.00357 *C 38.080 74.800 +*N mux_tree_tapbuf_size4_1_sram[1]:4 *C 38.043 74.800 +*N mux_tree_tapbuf_size4_1_sram[1]:5 *C 35.005 74.800 +*N mux_tree_tapbuf_size4_1_sram[1]:6 *C 34.960 74.755 +*N mux_tree_tapbuf_size4_1_sram[1]:7 *C 33.517 63.240 +*N mux_tree_tapbuf_size4_1_sram[1]:8 *C 34.915 63.240 +*N mux_tree_tapbuf_size4_1_sram[1]:9 *C 34.960 63.285 +*N mux_tree_tapbuf_size4_1_sram[1]:10 *C 34.960 72.080 +*N mux_tree_tapbuf_size4_1_sram[1]:11 *C 35.005 72.080 +*N mux_tree_tapbuf_size4_1_sram[1]:12 *C 34.712 69.700 +*N mux_tree_tapbuf_size4_1_sram[1]:13 *C 35.375 69.700 +*N mux_tree_tapbuf_size4_1_sram[1]:14 *C 35.420 69.745 +*N mux_tree_tapbuf_size4_1_sram[1]:15 *C 35.420 72.035 +*N mux_tree_tapbuf_size4_1_sram[1]:16 *C 35.420 72.080 +*N mux_tree_tapbuf_size4_1_sram[1]:17 *C 36.608 72.080 + +*CAP +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_11\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_track_11\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size4_1_sram[1]:4 0.0002091862 +5 mux_tree_tapbuf_size4_1_sram[1]:5 0.0002091862 +6 mux_tree_tapbuf_size4_1_sram[1]:6 0.0001566136 +7 mux_tree_tapbuf_size4_1_sram[1]:7 0.000125455 +8 mux_tree_tapbuf_size4_1_sram[1]:8 0.000125455 +9 mux_tree_tapbuf_size4_1_sram[1]:9 0.0003551117 +10 mux_tree_tapbuf_size4_1_sram[1]:10 0.0005432587 +11 mux_tree_tapbuf_size4_1_sram[1]:11 3.739085e-05 +12 mux_tree_tapbuf_size4_1_sram[1]:12 7.931894e-05 +13 mux_tree_tapbuf_size4_1_sram[1]:13 7.931894e-05 +14 mux_tree_tapbuf_size4_1_sram[1]:14 0.0001449051 +15 mux_tree_tapbuf_size4_1_sram[1]:15 0.0001449051 +16 mux_tree_tapbuf_size4_1_sram[1]:16 0.0001440397 +17 mux_tree_tapbuf_size4_1_sram[1]:17 7.390004e-05 +18 mux_tree_tapbuf_size4_1_sram[1]:11 mux_tree_tapbuf_size4_1_sram[0]:8 1.043313e-05 +19 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[0]:6 6.597867e-05 +20 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[0]:7 1.043313e-05 +21 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[0]:8 1.034932e-05 +22 mux_tree_tapbuf_size4_1_sram[1]:15 mux_tree_tapbuf_size4_1_sram[0]:6 4.914269e-05 +23 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[0]:5 4.914269e-05 +24 mux_tree_tapbuf_size4_1_sram[1]:9 mux_tree_tapbuf_size4_1_sram[0]:5 6.597867e-05 +25 mux_tree_tapbuf_size4_1_sram[1]:17 mux_tree_tapbuf_size4_1_sram[0]:7 1.034932e-05 +26 mux_tree_tapbuf_size4_1_sram[1]:10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.773136e-05 +27 mux_tree_tapbuf_size4_1_sram[1]:9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.773136e-05 + +*RES +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_1_sram[1]:17 0.152 +1 mux_tree_tapbuf_size4_1_sram[1]:5 mux_tree_tapbuf_size4_1_sram[1]:4 0.002712053 +2 mux_tree_tapbuf_size4_1_sram[1]:6 mux_tree_tapbuf_size4_1_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size4_1_sram[1]:4 mux_bottom_track_11\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size4_1_sram[1]:11 mux_tree_tapbuf_size4_1_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:9 0.007852679 +6 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:6 0.002388393 +7 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[1]:15 0.0045 +8 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[1]:11 0.0003705357 +9 mux_tree_tapbuf_size4_1_sram[1]:15 mux_tree_tapbuf_size4_1_sram[1]:14 0.002044643 +10 mux_tree_tapbuf_size4_1_sram[1]:13 mux_tree_tapbuf_size4_1_sram[1]:12 0.0005915179 +11 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:13 0.0045 +12 mux_tree_tapbuf_size4_1_sram[1]:12 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size4_1_sram[1]:8 mux_tree_tapbuf_size4_1_sram[1]:7 0.001247768 +14 mux_tree_tapbuf_size4_1_sram[1]:9 mux_tree_tapbuf_size4_1_sram[1]:8 0.0045 +15 mux_tree_tapbuf_size4_1_sram[1]:7 mux_bottom_track_11\/mux_l2_in_0_:S 0.152 +16 mux_tree_tapbuf_size4_1_sram[1]:17 mux_tree_tapbuf_size4_1_sram[1]:16 0.001060268 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[1] 0.001973564 //LENGTH 14.450 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 91.225 48.280 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 88.495 49.980 +*I mux_right_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 87.280 52.700 +*I mux_right_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 87.300 44.880 +*N mux_tree_tapbuf_size5_1_sram[1]:4 *C 87.300 44.880 +*N mux_tree_tapbuf_size5_1_sram[1]:5 *C 87.400 44.925 +*N mux_tree_tapbuf_size5_1_sram[1]:6 *C 87.400 48.235 +*N mux_tree_tapbuf_size5_1_sram[1]:7 *C 87.445 48.280 +*N mux_tree_tapbuf_size5_1_sram[1]:8 *C 87.318 52.700 +*N mux_tree_tapbuf_size5_1_sram[1]:9 *C 87.815 52.700 +*N mux_tree_tapbuf_size5_1_sram[1]:10 *C 87.860 52.655 +*N mux_tree_tapbuf_size5_1_sram[1]:11 *C 87.860 49.980 +*N mux_tree_tapbuf_size5_1_sram[1]:12 *C 88.495 49.980 +*N mux_tree_tapbuf_size5_1_sram[1]:13 *C 88.320 49.980 +*N mux_tree_tapbuf_size5_1_sram[1]:14 *C 88.320 49.935 +*N mux_tree_tapbuf_size5_1_sram[1]:15 *C 88.320 48.325 +*N mux_tree_tapbuf_size5_1_sram[1]:16 *C 88.320 48.280 +*N mux_tree_tapbuf_size5_1_sram[1]:17 *C 91.188 48.280 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_16\/mux_l2_in_1_:S 1e-06 +3 mux_right_track_16\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[1]:4 3.015365e-05 +5 mux_tree_tapbuf_size5_1_sram[1]:5 0.0002079957 +6 mux_tree_tapbuf_size5_1_sram[1]:6 0.0002079957 +7 mux_tree_tapbuf_size5_1_sram[1]:7 8.859907e-05 +8 mux_tree_tapbuf_size5_1_sram[1]:8 5.290455e-05 +9 mux_tree_tapbuf_size5_1_sram[1]:9 5.290455e-05 +10 mux_tree_tapbuf_size5_1_sram[1]:10 0.0001628107 +11 mux_tree_tapbuf_size5_1_sram[1]:11 0.0001957102 +12 mux_tree_tapbuf_size5_1_sram[1]:12 4.841635e-05 +13 mux_tree_tapbuf_size5_1_sram[1]:13 5.265323e-05 +14 mux_tree_tapbuf_size5_1_sram[1]:14 0.0001400692 +15 mux_tree_tapbuf_size5_1_sram[1]:15 0.0001071698 +16 mux_tree_tapbuf_size5_1_sram[1]:16 0.000371514 +17 mux_tree_tapbuf_size5_1_sram[1]:17 0.0002506672 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_1_sram[1]:17 0.152 +1 mux_tree_tapbuf_size5_1_sram[1]:17 mux_tree_tapbuf_size5_1_sram[1]:16 0.002560268 +2 mux_tree_tapbuf_size5_1_sram[1]:7 mux_tree_tapbuf_size5_1_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size5_1_sram[1]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.002955357 +4 mux_tree_tapbuf_size5_1_sram[1]:4 mux_right_track_16\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size5_1_sram[1]:5 mux_tree_tapbuf_size5_1_sram[1]:4 0.0045 +6 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:15 0.0045 +7 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:7 0.00078125 +8 mux_tree_tapbuf_size5_1_sram[1]:15 mux_tree_tapbuf_size5_1_sram[1]:14 0.0014375 +9 mux_tree_tapbuf_size5_1_sram[1]:13 mux_tree_tapbuf_size5_1_sram[1]:12 9.51087e-05 +10 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:11 0.0004107143 +12 mux_tree_tapbuf_size5_1_sram[1]:12 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size5_1_sram[1]:8 mux_right_track_16\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:8 0.0004441965 +15 mux_tree_tapbuf_size5_1_sram[1]:10 mux_tree_tapbuf_size5_1_sram[1]:9 0.0045 +16 mux_tree_tapbuf_size5_1_sram[1]:11 mux_tree_tapbuf_size5_1_sram[1]:10 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size5_5_sram[0] 0.003283532 //LENGTH 27.425 LUMPCC 0 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 51.825 60.685 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.470 64.260 +*I mux_left_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 64.960 56.440 +*I mux_left_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 60.820 61.200 +*N mux_tree_tapbuf_size5_5_sram[0]:4 *C 60.820 61.200 +*N mux_tree_tapbuf_size5_5_sram[0]:5 *C 64.922 56.440 +*N mux_tree_tapbuf_size5_5_sram[0]:6 *C 63.020 56.440 +*N mux_tree_tapbuf_size5_5_sram[0]:7 *C 63.020 56.100 +*N mux_tree_tapbuf_size5_5_sram[0]:8 *C 60.765 56.100 +*N mux_tree_tapbuf_size5_5_sram[0]:9 *C 60.720 56.145 +*N mux_tree_tapbuf_size5_5_sram[0]:10 *C 60.720 60.815 +*N mux_tree_tapbuf_size5_5_sram[0]:11 *C 60.765 60.867 +*N mux_tree_tapbuf_size5_5_sram[0]:12 *C 48.508 64.260 +*N mux_tree_tapbuf_size5_5_sram[0]:13 *C 50.555 64.260 +*N mux_tree_tapbuf_size5_5_sram[0]:14 *C 50.600 64.215 +*N mux_tree_tapbuf_size5_5_sram[0]:15 *C 50.600 60.905 +*N mux_tree_tapbuf_size5_5_sram[0]:16 *C 50.645 60.860 +*N mux_tree_tapbuf_size5_5_sram[0]:17 *C 51.825 60.685 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_17\/mux_l1_in_1_:S 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_5_sram[0]:4 6.136056e-05 +5 mux_tree_tapbuf_size5_5_sram[0]:5 0.0001622862 +6 mux_tree_tapbuf_size5_5_sram[0]:6 0.0001917974 +7 mux_tree_tapbuf_size5_5_sram[0]:7 0.0001682759 +8 mux_tree_tapbuf_size5_5_sram[0]:8 0.0001387646 +9 mux_tree_tapbuf_size5_5_sram[0]:9 0.0002922749 +10 mux_tree_tapbuf_size5_5_sram[0]:10 0.0002922749 +11 mux_tree_tapbuf_size5_5_sram[0]:11 0.0005559487 +12 mux_tree_tapbuf_size5_5_sram[0]:12 0.0001518275 +13 mux_tree_tapbuf_size5_5_sram[0]:13 0.0001518275 +14 mux_tree_tapbuf_size5_5_sram[0]:14 0.0002037966 +15 mux_tree_tapbuf_size5_5_sram[0]:15 0.0002037966 +16 mux_tree_tapbuf_size5_5_sram[0]:16 7.781124e-05 +17 mux_tree_tapbuf_size5_5_sram[0]:17 0.0006274896 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_5_sram[0]:17 0.152 +1 mux_tree_tapbuf_size5_5_sram[0]:4 mux_left_track_17\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_5_sram[0]:17 mux_tree_tapbuf_size5_5_sram[0]:16 0.001053571 +3 mux_tree_tapbuf_size5_5_sram[0]:17 mux_tree_tapbuf_size5_5_sram[0]:11 0.007982143 +4 mux_tree_tapbuf_size5_5_sram[0]:11 mux_tree_tapbuf_size5_5_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size5_5_sram[0]:11 mux_tree_tapbuf_size5_5_sram[0]:4 0.0001807065 +6 mux_tree_tapbuf_size5_5_sram[0]:10 mux_tree_tapbuf_size5_5_sram[0]:9 0.004169643 +7 mux_tree_tapbuf_size5_5_sram[0]:8 mux_tree_tapbuf_size5_5_sram[0]:7 0.002013393 +8 mux_tree_tapbuf_size5_5_sram[0]:9 mux_tree_tapbuf_size5_5_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size5_5_sram[0]:5 mux_left_track_17\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size5_5_sram[0]:12 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size5_5_sram[0]:13 mux_tree_tapbuf_size5_5_sram[0]:12 0.001828125 +12 mux_tree_tapbuf_size5_5_sram[0]:14 mux_tree_tapbuf_size5_5_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size5_5_sram[0]:16 mux_tree_tapbuf_size5_5_sram[0]:15 0.0045 +14 mux_tree_tapbuf_size5_5_sram[0]:15 mux_tree_tapbuf_size5_5_sram[0]:14 0.002955358 +15 mux_tree_tapbuf_size5_5_sram[0]:7 mux_tree_tapbuf_size5_5_sram[0]:6 0.0003035715 +16 mux_tree_tapbuf_size5_5_sram[0]:6 mux_tree_tapbuf_size5_5_sram[0]:5 0.001698661 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_6_ccff_tail[0] 0.0003808396 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/FTB_12__37:X O *L 0 *C 65.555 87.720 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.495 86.020 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:2 *C 65.495 86.020 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:3 *C 65.320 86.020 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:4 *C 65.320 86.065 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:5 *C 65.320 87.675 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:6 *C 65.320 87.720 +*N mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:7 *C 65.555 87.720 + +*CAP +0 mem_left_track_25\/FTB_12__37:X 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:2 4.476323e-05 +3 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:3 4.867049e-05 +4 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:4 9.469775e-05 +5 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:5 9.469775e-05 +6 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:6 4.83499e-05 +7 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:7 4.766048e-05 + +*RES +0 mem_left_track_25\/FTB_12__37:X mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_6_ccff_tail[0]:2 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.002187309 //LENGTH 19.720 LUMPCC 0 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 101.045 66.640 +*I mux_right_track_4\/mux_l3_in_0_:S I *L 0.003425 *C 112.925 61.200 +*I mem_right_track_4\/FTB_2__27:A I *L 0.001746 *C 110.860 66.640 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 112.925 61.200 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 112.700 61.200 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 112.700 61.245 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 112.700 63.875 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 112.655 63.920 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 110.905 63.920 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 110.860 63.965 +*N mux_tree_tapbuf_size6_1_sram[2]:10 *C 110.860 66.595 +*N mux_tree_tapbuf_size6_1_sram[2]:11 *C 110.860 66.640 +*N mux_tree_tapbuf_size6_1_sram[2]:12 *C 110.860 66.980 +*N mux_tree_tapbuf_size6_1_sram[2]:13 *C 101.660 66.980 +*N mux_tree_tapbuf_size6_1_sram[2]:14 *C 101.660 66.640 +*N mux_tree_tapbuf_size6_1_sram[2]:15 *C 101.083 66.640 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_4\/FTB_2__27:A 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 5.002047e-05 +4 mux_tree_tapbuf_size6_1_sram[2]:4 5.324694e-05 +5 mux_tree_tapbuf_size6_1_sram[2]:5 0.0001455839 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0001455839 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0001195509 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0001195509 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.0001454606 +10 mux_tree_tapbuf_size6_1_sram[2]:10 0.0001454606 +11 mux_tree_tapbuf_size6_1_sram[2]:11 5.793358e-05 +12 mux_tree_tapbuf_size6_1_sram[2]:12 0.0005481041 +13 mux_tree_tapbuf_size6_1_sram[2]:13 0.000544015 +14 mux_tree_tapbuf_size6_1_sram[2]:14 6.628517e-05 +15 mux_tree_tapbuf_size6_1_sram[2]:15 4.351321e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:15 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:11 mux_tree_tapbuf_size6_1_sram[2]:10 0.0045 +2 mux_tree_tapbuf_size6_1_sram[2]:11 mem_right_track_4\/FTB_2__27:A 0.152 +3 mux_tree_tapbuf_size6_1_sram[2]:10 mux_tree_tapbuf_size6_1_sram[2]:9 0.002348215 +4 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.0015625 +5 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.0045 +7 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.002348214 +8 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.0001222826 +9 mux_tree_tapbuf_size6_1_sram[2]:5 mux_tree_tapbuf_size6_1_sram[2]:4 0.0045 +10 mux_tree_tapbuf_size6_1_sram[2]:3 mux_right_track_4\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size6_1_sram[2]:15 mux_tree_tapbuf_size6_1_sram[2]:14 0.000515625 +12 mux_tree_tapbuf_size6_1_sram[2]:14 mux_tree_tapbuf_size6_1_sram[2]:13 0.0003035715 +13 mux_tree_tapbuf_size6_1_sram[2]:13 mux_tree_tapbuf_size6_1_sram[2]:12 0.008214287 +14 mux_tree_tapbuf_size6_1_sram[2]:12 mux_tree_tapbuf_size6_1_sram[2]:11 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_3_ccff_tail[0] 0.0005669971 //LENGTH 3.620 LUMPCC 7.297977e-05 DR + +*CONN +*I mem_left_track_5\/FTB_4__29:X O *L 0 *C 46.235 50.660 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 46.175 53.380 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 *C 46.175 53.380 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 *C 46.000 53.380 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 *C 46.000 53.335 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 *C 46.000 50.705 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 *C 46.000 50.660 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 *C 46.235 50.660 + +*CAP +0 mem_left_track_5\/FTB_4__29:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 5.293731e-05 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 5.764796e-05 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.0001281331 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0001281331 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 6.398703e-05 +7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 6.117873e-05 +8 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_1_sram[0]:15 3.648988e-05 +9 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_1_sram[0]:16 3.648988e-05 + +*RES +0 mem_left_track_5\/FTB_4__29:X mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[2] 0.002176535 //LENGTH 19.540 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 40.785 12.240 +*I mem_bottom_track_1\/FTB_20__45:A I *L 0.001746 *C 36.800 6.800 +*I mux_bottom_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 42.200 18.020 +*N mux_tree_tapbuf_size7_0_sram[2]:3 *C 42.163 18.020 +*N mux_tree_tapbuf_size7_0_sram[2]:4 *C 39.145 18.020 +*N mux_tree_tapbuf_size7_0_sram[2]:5 *C 39.100 17.975 +*N mux_tree_tapbuf_size7_0_sram[2]:6 *C 36.837 6.800 +*N mux_tree_tapbuf_size7_0_sram[2]:7 *C 39.055 6.800 +*N mux_tree_tapbuf_size7_0_sram[2]:8 *C 39.100 6.845 +*N mux_tree_tapbuf_size7_0_sram[2]:9 *C 39.100 12.240 +*N mux_tree_tapbuf_size7_0_sram[2]:10 *C 39.145 12.240 +*N mux_tree_tapbuf_size7_0_sram[2]:11 *C 40.748 12.240 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_1\/FTB_20__45:A 1e-06 +2 mux_bottom_track_1\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_0_sram[2]:3 0.0002070344 +4 mux_tree_tapbuf_size7_0_sram[2]:4 0.0002070344 +5 mux_tree_tapbuf_size7_0_sram[2]:5 0.000309914 +6 mux_tree_tapbuf_size7_0_sram[2]:6 0.0001394212 +7 mux_tree_tapbuf_size7_0_sram[2]:7 0.0001394212 +8 mux_tree_tapbuf_size7_0_sram[2]:8 0.0002718963 +9 mux_tree_tapbuf_size7_0_sram[2]:9 0.0006110063 +10 mux_tree_tapbuf_size7_0_sram[2]:10 0.0001439035 +11 mux_tree_tapbuf_size7_0_sram[2]:11 0.0001439035 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_0_sram[2]:11 0.152 +1 mux_tree_tapbuf_size7_0_sram[2]:3 mux_bottom_track_1\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[2]:3 0.002694197 +3 mux_tree_tapbuf_size7_0_sram[2]:5 mux_tree_tapbuf_size7_0_sram[2]:4 0.0045 +4 mux_tree_tapbuf_size7_0_sram[2]:10 mux_tree_tapbuf_size7_0_sram[2]:9 0.0045 +5 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:8 0.004816964 +6 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:5 0.005120536 +7 mux_tree_tapbuf_size7_0_sram[2]:11 mux_tree_tapbuf_size7_0_sram[2]:10 0.001430804 +8 mux_tree_tapbuf_size7_0_sram[2]:6 mem_bottom_track_1\/FTB_20__45:A 0.152 +9 mux_tree_tapbuf_size7_0_sram[2]:7 mux_tree_tapbuf_size7_0_sram[2]:6 0.001979911 +10 mux_tree_tapbuf_size7_0_sram[2]:8 mux_tree_tapbuf_size7_0_sram[2]:7 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[2] 0.002215846 //LENGTH 17.005 LUMPCC 0.0004834799 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 40.325 49.980 +*I mux_bottom_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 39.000 47.310 +*I mem_bottom_track_5\/FTB_22__47:A I *L 0.001746 *C 36.800 55.760 +*N mux_tree_tapbuf_size7_2_sram[2]:3 *C 36.837 55.760 +*N mux_tree_tapbuf_size7_2_sram[2]:4 *C 37.675 55.760 +*N mux_tree_tapbuf_size7_2_sram[2]:5 *C 37.720 55.715 +*N mux_tree_tapbuf_size7_2_sram[2]:6 *C 37.720 46.965 +*N mux_tree_tapbuf_size7_2_sram[2]:7 *C 37.765 46.920 +*N mux_tree_tapbuf_size7_2_sram[2]:8 *C 39.000 46.920 +*N mux_tree_tapbuf_size7_2_sram[2]:9 *C 39.000 47.310 +*N mux_tree_tapbuf_size7_2_sram[2]:10 *C 39.100 47.600 +*N mux_tree_tapbuf_size7_2_sram[2]:11 *C 39.100 47.645 +*N mux_tree_tapbuf_size7_2_sram[2]:12 *C 39.100 49.935 +*N mux_tree_tapbuf_size7_2_sram[2]:13 *C 39.145 49.980 +*N mux_tree_tapbuf_size7_2_sram[2]:14 *C 40.288 49.980 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_5\/FTB_22__47:A 1e-06 +3 mux_tree_tapbuf_size7_2_sram[2]:3 8.418169e-05 +4 mux_tree_tapbuf_size7_2_sram[2]:4 8.418169e-05 +5 mux_tree_tapbuf_size7_2_sram[2]:5 0.0003389828 +6 mux_tree_tapbuf_size7_2_sram[2]:6 0.0003389828 +7 mux_tree_tapbuf_size7_2_sram[2]:7 0.0001161565 +8 mux_tree_tapbuf_size7_2_sram[2]:8 0.0001409484 +9 mux_tree_tapbuf_size7_2_sram[2]:9 7.669859e-05 +10 mux_tree_tapbuf_size7_2_sram[2]:10 5.653197e-05 +11 mux_tree_tapbuf_size7_2_sram[2]:11 0.0001540116 +12 mux_tree_tapbuf_size7_2_sram[2]:12 0.0001540116 +13 mux_tree_tapbuf_size7_2_sram[2]:13 9.233955e-05 +14 mux_tree_tapbuf_size7_2_sram[2]:14 9.233955e-05 +15 mux_tree_tapbuf_size7_2_sram[2]:6 chanx_right_in[10]:7 0.000239582 +16 mux_tree_tapbuf_size7_2_sram[2]:5 chanx_right_in[10]:19 0.000239582 +17 mux_tree_tapbuf_size7_2_sram[2]:12 chanx_right_in[10]:19 2.157992e-06 +18 mux_tree_tapbuf_size7_2_sram[2]:11 chanx_right_in[10]:7 2.157992e-06 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_2_sram[2]:14 0.152 +1 mux_tree_tapbuf_size7_2_sram[2]:9 mux_bottom_track_5\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[2]:9 mux_tree_tapbuf_size7_2_sram[2]:8 0.0003482143 +3 mux_tree_tapbuf_size7_2_sram[2]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size7_2_sram[2]:6 mux_tree_tapbuf_size7_2_sram[2]:5 0.0078125 +5 mux_tree_tapbuf_size7_2_sram[2]:4 mux_tree_tapbuf_size7_2_sram[2]:3 0.000747768 +6 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size7_2_sram[2]:3 mem_bottom_track_5\/FTB_22__47:A 0.152 +8 mux_tree_tapbuf_size7_2_sram[2]:14 mux_tree_tapbuf_size7_2_sram[2]:13 0.001020089 +9 mux_tree_tapbuf_size7_2_sram[2]:13 mux_tree_tapbuf_size7_2_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size7_2_sram[2]:12 mux_tree_tapbuf_size7_2_sram[2]:11 0.002044643 +11 mux_tree_tapbuf_size7_2_sram[2]:10 mux_tree_tapbuf_size7_2_sram[2]:9 0.0002589286 +12 mux_tree_tapbuf_size7_2_sram[2]:11 mux_tree_tapbuf_size7_2_sram[2]:10 0.0045 +13 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:7 0.001102679 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009294313 //LENGTH 7.540 LUMPCC 0.0002197771 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_1_:X O *L 0 *C 86.765 75.140 +*I mux_right_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 94.015 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 93.978 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 86.803 75.140 + +*CAP +0 mux_right_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003538271 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003538271 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_0_sram[0]:12 5.207429e-05 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_0_sram[0]:11 5.207429e-05 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.781424e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.781424e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_1_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00640625 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001056103 //LENGTH 8.175 LUMPCC 0.0001364221 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_0_:X O *L 0 *C 93.665 55.760 +*I mux_right_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 94.860 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 94.823 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 93.425 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 93.380 61.495 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 93.380 55.805 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 93.380 55.760 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 93.665 55.760 + +*CAP +0 mux_right_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001232015 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001232015 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002723883 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002723883 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.279169e-05 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.370926e-05 +8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.821107e-05 +9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 6.821107e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_0_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005080357 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008724268 //LENGTH 5.980 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_1_:X O *L 0 *C 114.365 53.720 +*I mux_right_track_8\/mux_l3_in_0_:A0 I *L 0.005103 *C 118.220 54.915 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 118.183 54.915 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 115.505 54.915 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 115.460 54.870 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 115.460 53.765 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 115.415 53.720 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 114.403 53.720 + +*CAP +0 mux_right_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002466111 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002466111 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.494113e-05 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.494113e-05 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.366117e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.366117e-05 + +*RES +0 mux_right_track_8\/mux_l2_in_1_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0009866072 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002390625 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00131652 //LENGTH 10.210 LUMPCC 0.0001488685 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 61.355 44.880 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 59.705 52.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 59.742 52.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 61.135 52.700 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 61.180 52.655 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 61.180 44.925 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.180 44.880 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 61.355 44.880 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.929205e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.929205e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004376342 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004376342 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.570335e-05 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.609594e-05 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size6_4_sram[0]:24 2.890819e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_4_sram[0]:23 2.890819e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_4_sram[0]:22 4.552608e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_4_sram[0]:21 4.552608e-05 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001243304 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004417005 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_1_:X O *L 0 *C 77.565 59.160 +*I mux_right_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 77.455 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 77.455 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 77.740 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 77.740 60.815 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 77.740 59.205 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 77.740 59.160 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 77.565 59.160 + +*CAP +0 mux_right_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.836719e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.844201e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001107401 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001107401 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.282921e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.858196e-05 + +*RES +0 mux_right_track_2\/mux_l2_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001548913 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0] 0.005094949 //LENGTH 45.800 LUMPCC 0.000869363 DR + +*CONN +*I mux_right_track_16\/mux_l3_in_0_:X O *L 0 *C 94.125 53.380 +*I mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 125.805 66.450 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 125.805 66.450 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 125.580 66.300 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 125.580 66.255 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 125.580 65.338 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 125.573 65.280 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 94.308 65.280 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 94.300 65.222 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 94.300 53.425 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 94.300 53.380 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 94.125 53.380 + +*CAP +0 mux_right_track_16\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.021744e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.999926e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.395021e-05 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.395021e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00135911 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00135911 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0005883843 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0005883843 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.133212e-05 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:11 4.914884e-05 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[17]:29 0.0001345571 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[17]:30 0.0001345571 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.821107e-05 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.821107e-05 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 optlc_net_164:19 0.0002319133 +17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_164:18 0.0002319133 + +*RES +0 mux_right_track_16\/mux_l3_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:10 9.51087e-05 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.01053348 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.004898183 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0008191965 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001222826 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005229154 //LENGTH 3.395 LUMPCC 0.0002494653 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_1_:X O *L 0 *C 74.235 47.940 +*I mux_left_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 71.130 47.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 71.168 47.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 74.198 47.940 + +*CAP +0 mux_left_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001357251 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001357251 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 optlc_net_164:37 0.0001247327 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 optlc_net_164:38 0.0001247327 + +*RES +0 mux_left_track_3\/mux_l2_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002705357 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003137416 //LENGTH 25.380 LUMPCC 0.0004285566 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_0_:X O *L 0 *C 55.375 70.040 +*I mux_left_track_17\/mux_l3_in_0_:A1 I *L 0.00198 *C 40.385 79.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 40.385 79.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 40.480 79.855 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 40.480 70.085 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 40.525 70.040 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 55.338 70.040 + +*CAP +0 mux_left_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.988856e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0005174543 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005174543 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0008210309 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0008210309 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_5_sram[1]:12 0.0001649629 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_5_sram[1]:13 0.0001649629 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.931545e-05 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.931545e-05 + +*RES +0 mux_left_track_17\/mux_l2_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.008723215 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.01322545 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002741075 //LENGTH 27.645 LUMPCC 0 DR + +*CONN +*I mux_right_track_32\/mux_l2_in_0_:X O *L 0 *C 111.605 31.280 +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 122.075 47.745 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 122.038 47.650 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 120.105 47.600 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 120.060 47.555 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 120.060 31.325 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 120.015 31.280 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 111.642 31.280 + +*CAP +0 mux_right_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001207121 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001207121 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0008247627 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0008247627 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004240627 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0004240627 + +*RES +0 mux_right_track_32\/mux_l2_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.007475447 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.01449107 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001725447 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006607604 //LENGTH 4.145 LUMPCC 0.000225415 DR + +*CONN +*I mux_bottom_track_19\/mux_l1_in_0_:X O *L 0 *C 61.355 25.500 +*I mux_bottom_track_19\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.500 25.500 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.538 25.500 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 61.318 25.500 + +*CAP +0 mux_bottom_track_19\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_19\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002166727 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002166727 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[0]:13 6.763321e-05 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_4_sram[0]:12 6.763321e-05 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[1]:4 4.507431e-05 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_4_sram[1]:3 4.507431e-05 + +*RES +0 mux_bottom_track_19\/mux_l1_in_0_:X mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003375 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_19\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002670268 //LENGTH 22.185 LUMPCC 0.0005394363 DR + +*CONN +*I mux_bottom_track_21\/mux_l2_in_0_:X O *L 0 *C 86.765 22.780 +*I mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 92.635 9.695 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 92.598 9.800 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 92.045 9.860 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 92.000 9.905 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 92.000 19.663 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 92.008 19.720 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 92.913 19.720 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 92.920 19.777 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 92.920 22.735 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 92.875 22.780 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 86.803 22.780 + +*CAP +0 mux_bottom_track_21\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.22216e-05 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.22216e-05 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003967485 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003967485 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.527496e-05 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.527496e-05 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001896771 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001896771 +10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0003504936 +11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0003504936 +12 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:116 1.373411e-05 +13 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:120 4.04214e-05 +14 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:126 2.74598e-05 +15 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:113 1.373411e-05 +16 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:116 4.04214e-05 +17 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:120 2.74598e-05 +18 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:112 8.029372e-06 +19 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:111 8.029372e-06 +20 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 5.722243e-05 +21 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 5.722243e-05 +22 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.942792e-05 +23 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.942792e-05 +24 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/BUF_net_72:3 5.342313e-05 +25 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/BUF_net_72:4 5.342313e-05 + +*RES +0 mux_bottom_track_21\/mux_l2_in_0_:X mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004933036 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.008712053 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001417833 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002640625 +10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.005421875 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.004860321 //LENGTH 37.630 LUMPCC 0.001313888 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_0_:X O *L 0 *C 28.345 30.600 +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 37.530 4.250 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 37.492 4.357 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 36.845 4.420 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 36.800 4.465 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 36.800 10.143 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 36.793 10.200 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 35.900 10.200 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 35.880 10.208 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 35.880 27.873 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 35.860 27.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 28.988 27.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 28.980 27.938 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 28.980 30.555 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 28.935 30.600 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 28.383 30.600 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.214099e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.214099e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003706988 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003706988 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001115112 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001115112 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0005887457 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0005887457 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0003855765 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0003855765 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001974872 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0001974872 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:14 6.605564e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:15 6.605564e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_left_grid_pin_40_[0]:25 0.0001529674 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_left_grid_pin_40_[0]:24 0.0001529674 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chanx_left_in[0]:6 0.0001487889 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 chanx_left_in[0]:7 0.0001487889 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003551879 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0003551879 + +*RES +0 mux_bottom_track_3\/mux_l3_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.000578125 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005069197 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000139825 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.002767517 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001076692 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.002337054 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0004933036 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001139759 //LENGTH 8.085 LUMPCC 0.0003264906 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 17.765 67.320 +*I mux_bottom_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 24.940 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 24.902 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.080 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 22.080 67.320 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 17.803 67.320 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001683062 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001930643 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002373282 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002125701 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001059803 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001059803 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.945777e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.780718e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.780718e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.945777e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003819196 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003035715 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00252009 + +*END + +*D_NET mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001330895 //LENGTH 12.175 LUMPCC 0.0001557736 DR + +*CONN +*I mux_bottom_track_29\/mux_l2_in_0_:X O *L 0 *C 105.515 12.580 +*I mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 102.355 4.265 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 102.392 4.365 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 102.995 4.420 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 103.040 4.465 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 103.040 12.535 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 103.085 12.580 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 105.478 12.580 + +*CAP +0 mux_bottom_track_29\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.586921e-05 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.586921e-05 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003620219 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003620219 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001786697 +7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001786697 +8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 7.788678e-05 +9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 7.788678e-05 + +*RES +0 mux_bottom_track_29\/mux_l2_in_0_:X mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002136161 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.007205357 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005379464 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chanx_right_out[14] 0.00081662 //LENGTH 7.935 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_805:X O *L 0 *C 136.160 93.840 +*P chanx_right_out[14] O *L 0.7423 *C 140.382 91.120 +*N chanx_right_out[14]:2 *C 140.300 91.120 +*N chanx_right_out[14]:3 *C 140.300 91.120 +*N chanx_right_out[14]:4 *C 139.380 91.120 +*N chanx_right_out[14]:5 *C 139.380 93.795 +*N chanx_right_out[14]:6 *C 139.335 93.840 +*N chanx_right_out[14]:7 *C 136.198 93.840 + +*CAP +0 ropt_mt_inst_805:X 1e-06 +1 chanx_right_out[14] 2.613542e-05 +2 chanx_right_out[14]:2 2.613542e-05 +3 chanx_right_out[14]:3 7.800401e-05 +4 chanx_right_out[14]:4 0.0001830935 +5 chanx_right_out[14]:5 0.0001344452 +6 chanx_right_out[14]:6 0.0001839032 +7 chanx_right_out[14]:7 0.0001839032 + +*RES +0 ropt_mt_inst_805:X chanx_right_out[14]:7 0.152 +1 chanx_right_out[14]:7 chanx_right_out[14]:6 0.002801339 +2 chanx_right_out[14]:6 chanx_right_out[14]:5 0.0045 +3 chanx_right_out[14]:5 chanx_right_out[14]:4 0.002388393 +4 chanx_right_out[14]:3 chanx_right_out[14]:2 0.00341 +5 chanx_right_out[14]:2 chanx_right_out[14] 2.35e-05 +6 chanx_right_out[14]:4 chanx_right_out[14]:3 0.0008214285 + +*END + +*D_NET chanx_left_out[11] 0.002135912 //LENGTH 15.070 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_832:X O *L 0 *C 11.695 95.880 +*P chanx_left_out[11] O *L 0.7423 *C 1.230 92.480 +*N chanx_left_out[11]:2 *C 1.840 92.480 +*N chanx_left_out[11]:3 *C 1.840 93.160 +*N chanx_left_out[11]:4 *C 11.492 93.160 +*N chanx_left_out[11]:5 *C 11.500 93.218 +*N chanx_left_out[11]:6 *C 11.500 95.835 +*N chanx_left_out[11]:7 *C 11.500 95.880 +*N chanx_left_out[11]:8 *C 11.695 95.880 + +*CAP +0 ropt_mt_inst_832:X 1e-06 +1 chanx_left_out[11] 5.819495e-05 +2 chanx_left_out[11]:2 0.000103332 +3 chanx_left_out[11]:3 0.0007341446 +4 chanx_left_out[11]:4 0.0006890076 +5 chanx_left_out[11]:5 0.0002066985 +6 chanx_left_out[11]:6 0.0002066985 +7 chanx_left_out[11]:7 6.679811e-05 +8 chanx_left_out[11]:8 7.003773e-05 + +*RES +0 ropt_mt_inst_832:X chanx_left_out[11]:8 0.152 +1 chanx_left_out[11]:8 chanx_left_out[11]:7 0.0001059783 +2 chanx_left_out[11]:7 chanx_left_out[11]:6 0.0045 +3 chanx_left_out[11]:6 chanx_left_out[11]:5 0.002337054 +4 chanx_left_out[11]:5 chanx_left_out[11]:4 0.00341 +5 chanx_left_out[11]:4 chanx_left_out[11]:3 0.001512225 +6 chanx_left_out[11]:2 chanx_left_out[11] 9.556666e-05 +7 chanx_left_out[11]:3 chanx_left_out[11]:2 0.0001065333 + +*END + +*D_NET chanx_right_in[10] 0.02392706 //LENGTH 205.095 LUMPCC 0.002208246 DR + +*CONN +*P chanx_right_in[10] I *L 0.29796 *C 140.450 80.240 +*I ropt_mt_inst_791:A I *L 0.001767 *C 3.220 93.840 +*I mux_bottom_track_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.200 41.820 +*I mux_left_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 81.785 88.740 +*N chanx_right_in[10]:4 *C 81.785 88.740 +*N chanx_right_in[10]:5 *C 39.163 41.820 +*N chanx_right_in[10]:6 *C 37.305 41.820 +*N chanx_right_in[10]:7 *C 37.260 41.865 +*N chanx_right_in[10]:8 *C 3.243 93.812 +*N chanx_right_in[10]:9 *C 3.255 93.500 +*N chanx_right_in[10]:10 *C 5.935 93.500 +*N chanx_right_in[10]:11 *C 5.980 93.455 +*N chanx_right_in[10]:12 *C 5.980 90.825 +*N chanx_right_in[10]:13 *C 6.025 90.780 +*N chanx_right_in[10]:14 *C 30.315 90.780 +*N chanx_right_in[10]:15 *C 30.360 90.735 +*N chanx_right_in[10]:16 *C 30.360 87.765 +*N chanx_right_in[10]:17 *C 30.405 87.720 +*N chanx_right_in[10]:18 *C 37.215 87.720 +*N chanx_right_in[10]:19 *C 37.260 87.720 +*N chanx_right_in[10]:20 *C 37.260 89.035 +*N chanx_right_in[10]:21 *C 37.305 89.080 +*N chanx_right_in[10]:22 *C 81.880 89.080 +*N chanx_right_in[10]:23 *C 130.595 89.080 +*N chanx_right_in[10]:24 *C 130.640 89.035 +*N chanx_right_in[10]:25 *C 130.640 80.297 +*N chanx_right_in[10]:26 *C 130.648 80.240 + +*CAP +0 chanx_right_in[10] 0.0003959791 +1 ropt_mt_inst_791:A 1e-06 +2 mux_bottom_track_13\/mux_l1_in_0_:A1 1e-06 +3 mux_left_track_33\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[10]:4 5.130627e-05 +5 chanx_right_in[10]:5 0.0001511556 +6 chanx_right_in[10]:6 0.0001511556 +7 chanx_right_in[10]:7 0.00226228 +8 chanx_right_in[10]:8 2.981246e-05 +9 chanx_right_in[10]:9 0.0001516622 +10 chanx_right_in[10]:10 0.0001218497 +11 chanx_right_in[10]:11 0.0001616293 +12 chanx_right_in[10]:12 0.0001616293 +13 chanx_right_in[10]:13 0.001285758 +14 chanx_right_in[10]:14 0.001285758 +15 chanx_right_in[10]:15 0.000155509 +16 chanx_right_in[10]:16 0.000155509 +17 chanx_right_in[10]:17 0.0004219849 +18 chanx_right_in[10]:18 0.0004219849 +19 chanx_right_in[10]:19 0.002353876 +20 chanx_right_in[10]:20 6.534688e-05 +21 chanx_right_in[10]:21 0.00264965 +22 chanx_right_in[10]:22 0.005354496 +23 chanx_right_in[10]:23 0.002679413 +24 chanx_right_in[10]:24 0.000426045 +25 chanx_right_in[10]:25 0.000426045 +26 chanx_right_in[10]:26 0.0003959792 +27 chanx_right_in[10] chanx_right_out[4] 4.32148e-05 +28 chanx_right_in[10] chanx_right_out[4]:3 0.0003241314 +29 chanx_right_in[10]:26 chanx_right_out[4]:4 0.0003241314 +30 chanx_right_in[10]:26 chanx_right_out[4]:2 4.32148e-05 +31 chanx_right_in[10]:23 mux_tree_tapbuf_size6_0_sram[2]:4 0.0001928057 +32 chanx_right_in[10]:22 mux_tree_tapbuf_size6_0_sram[2]:3 0.0001928057 +33 chanx_right_in[10]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.000239582 +34 chanx_right_in[10]:7 mux_tree_tapbuf_size7_2_sram[2]:11 2.157992e-06 +35 chanx_right_in[10]:19 mux_tree_tapbuf_size7_2_sram[2]:5 0.000239582 +36 chanx_right_in[10]:19 mux_tree_tapbuf_size7_2_sram[2]:12 2.157992e-06 +37 chanx_right_in[10]:21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.932329e-05 +38 chanx_right_in[10]:22 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.932329e-05 +39 chanx_right_in[10]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001149294 +40 chanx_right_in[10]:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001149294 +41 chanx_right_in[10]:12 ropt_net_214:5 6.55182e-06 +42 chanx_right_in[10]:10 ropt_net_214:6 7.964741e-05 +43 chanx_right_in[10]:11 ropt_net_214:4 6.55182e-06 +44 chanx_right_in[10]:9 ropt_net_214:7 7.964741e-05 +45 chanx_right_in[10]:14 ropt_net_202:4 5.177923e-05 +46 chanx_right_in[10]:13 ropt_net_202:3 5.177923e-05 + +*RES +0 chanx_right_in[10] chanx_right_in[10]:26 0.001535725 +1 chanx_right_in[10]:23 chanx_right_in[10]:22 0.04349554 +2 chanx_right_in[10]:24 chanx_right_in[10]:23 0.0045 +3 chanx_right_in[10]:25 chanx_right_in[10]:24 0.007801339 +4 chanx_right_in[10]:26 chanx_right_in[10]:25 0.00341 +5 chanx_right_in[10]:6 chanx_right_in[10]:5 0.001658482 +6 chanx_right_in[10]:7 chanx_right_in[10]:6 0.0045 +7 chanx_right_in[10]:5 mux_bottom_track_13\/mux_l1_in_0_:A1 0.152 +8 chanx_right_in[10]:18 chanx_right_in[10]:17 0.006080357 +9 chanx_right_in[10]:19 chanx_right_in[10]:18 0.0045 +10 chanx_right_in[10]:19 chanx_right_in[10]:7 0.04094197 +11 chanx_right_in[10]:17 chanx_right_in[10]:16 0.0045 +12 chanx_right_in[10]:16 chanx_right_in[10]:15 0.002651786 +13 chanx_right_in[10]:14 chanx_right_in[10]:13 0.0216875 +14 chanx_right_in[10]:15 chanx_right_in[10]:14 0.0045 +15 chanx_right_in[10]:13 chanx_right_in[10]:12 0.0045 +16 chanx_right_in[10]:12 chanx_right_in[10]:11 0.002348214 +17 chanx_right_in[10]:10 chanx_right_in[10]:9 0.002392857 +18 chanx_right_in[10]:11 chanx_right_in[10]:10 0.0045 +19 chanx_right_in[10]:8 ropt_mt_inst_791:A 0.152 +20 chanx_right_in[10]:4 mux_left_track_33\/mux_l1_in_0_:A1 0.152 +21 chanx_right_in[10]:21 chanx_right_in[10]:20 0.0045 +22 chanx_right_in[10]:20 chanx_right_in[10]:19 0.001174107 +23 chanx_right_in[10]:9 chanx_right_in[10]:8 0.0002111487 +24 chanx_right_in[10]:22 chanx_right_in[10]:21 0.03979911 +25 chanx_right_in[10]:22 chanx_right_in[10]:4 0.0003035715 + +*END + +*D_NET bottom_left_grid_pin_37_[0] 0.01638879 //LENGTH 117.285 LUMPCC 0.004469667 DR + +*CONN +*P bottom_left_grid_pin_37_[0] I *L 0.29796 *C 29.750 3.400 +*I mux_bottom_track_31\/mux_l1_in_0_:A0 I *L 0.001631 *C 90.910 22.440 +*I mux_bottom_track_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 49.855 28.220 +*I mux_bottom_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 30.820 30.940 +*I mux_bottom_track_7\/mux_l1_in_1_:A1 I *L 0.00198 *C 22.540 39.780 +*N bottom_left_grid_pin_37_[0]:5 *C 22.540 39.780 +*N bottom_left_grid_pin_37_[0]:6 *C 22.540 39.735 +*N bottom_left_grid_pin_37_[0]:7 *C 22.540 37.445 +*N bottom_left_grid_pin_37_[0]:8 *C 22.585 37.400 +*N bottom_left_grid_pin_37_[0]:9 *C 31.695 37.400 +*N bottom_left_grid_pin_37_[0]:10 *C 31.740 37.355 +*N bottom_left_grid_pin_37_[0]:11 *C 30.858 30.940 +*N bottom_left_grid_pin_37_[0]:12 *C 31.695 30.940 +*N bottom_left_grid_pin_37_[0]:13 *C 31.740 30.940 +*N bottom_left_grid_pin_37_[0]:14 *C 49.818 28.220 +*N bottom_left_grid_pin_37_[0]:15 *C 49.220 28.220 +*N bottom_left_grid_pin_37_[0]:16 *C 90.910 22.440 +*N bottom_left_grid_pin_37_[0]:17 *C 90.620 22.440 +*N bottom_left_grid_pin_37_[0]:18 *C 90.620 22.485 +*N bottom_left_grid_pin_37_[0]:19 *C 90.620 25.103 +*N bottom_left_grid_pin_37_[0]:20 *C 90.613 25.160 +*N bottom_left_grid_pin_37_[0]:21 *C 49.227 25.160 +*N bottom_left_grid_pin_37_[0]:22 *C 49.220 25.218 +*N bottom_left_grid_pin_37_[0]:23 *C 49.220 27.835 +*N bottom_left_grid_pin_37_[0]:24 *C 49.220 27.910 +*N bottom_left_grid_pin_37_[0]:25 *C 31.785 27.880 +*N bottom_left_grid_pin_37_[0]:26 *C 31.740 27.880 +*N bottom_left_grid_pin_37_[0]:27 *C 31.740 3.458 +*N bottom_left_grid_pin_37_[0]:28 *C 31.733 3.400 + +*CAP +0 bottom_left_grid_pin_37_[0] 0.0001264178 +1 mux_bottom_track_31\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_15\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_3\/mux_l1_in_1_:A1 1e-06 +4 mux_bottom_track_7\/mux_l1_in_1_:A1 1e-06 +5 bottom_left_grid_pin_37_[0]:5 2.955788e-05 +6 bottom_left_grid_pin_37_[0]:6 0.0001428854 +7 bottom_left_grid_pin_37_[0]:7 0.0001428854 +8 bottom_left_grid_pin_37_[0]:8 0.000691566 +9 bottom_left_grid_pin_37_[0]:9 0.000691566 +10 bottom_left_grid_pin_37_[0]:10 0.0002150559 +11 bottom_left_grid_pin_37_[0]:11 7.249699e-05 +12 bottom_left_grid_pin_37_[0]:12 7.249699e-05 +13 bottom_left_grid_pin_37_[0]:13 0.0003300108 +14 bottom_left_grid_pin_37_[0]:14 6.712519e-05 +15 bottom_left_grid_pin_37_[0]:15 9.518716e-05 +16 bottom_left_grid_pin_37_[0]:16 5.44573e-05 +17 bottom_left_grid_pin_37_[0]:17 5.877901e-05 +18 bottom_left_grid_pin_37_[0]:18 0.0001770832 +19 bottom_left_grid_pin_37_[0]:19 0.0001770832 +20 bottom_left_grid_pin_37_[0]:20 0.002160612 +21 bottom_left_grid_pin_37_[0]:21 0.002160612 +22 bottom_left_grid_pin_37_[0]:22 0.000198763 +23 bottom_left_grid_pin_37_[0]:23 0.000198763 +24 bottom_left_grid_pin_37_[0]:24 0.001191837 +25 bottom_left_grid_pin_37_[0]:25 0.001163775 +26 bottom_left_grid_pin_37_[0]:26 0.0008422174 +27 bottom_left_grid_pin_37_[0]:27 0.0007274689 +28 bottom_left_grid_pin_37_[0]:28 0.0001264178 +29 bottom_left_grid_pin_37_[0] prog_clk[0]:561 4.733115e-07 +30 bottom_left_grid_pin_37_[0]:21 prog_clk[0]:300 1.934086e-05 +31 bottom_left_grid_pin_37_[0]:20 prog_clk[0]:299 1.934086e-05 +32 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:499 5.750001e-06 +33 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:500 5.001002e-05 +34 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:546 3.493543e-05 +35 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:552 3.777793e-05 +36 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:558 6.506656e-05 +37 bottom_left_grid_pin_37_[0]:26 prog_clk[0]:562 5.959802e-05 +38 bottom_left_grid_pin_37_[0]:8 prog_clk[0]:486 2.307428e-05 +39 bottom_left_grid_pin_37_[0]:9 prog_clk[0]:483 2.307428e-05 +40 bottom_left_grid_pin_37_[0]:10 prog_clk[0]:486 5.288864e-06 +41 bottom_left_grid_pin_37_[0]:10 prog_clk[0]:488 6.649779e-06 +42 bottom_left_grid_pin_37_[0]:13 prog_clk[0]:487 5.288864e-06 +43 bottom_left_grid_pin_37_[0]:13 prog_clk[0]:497 6.649779e-06 +44 bottom_left_grid_pin_37_[0]:27 prog_clk[0] 5.959802e-05 +45 bottom_left_grid_pin_37_[0]:27 prog_clk[0]:500 5.750001e-06 +46 bottom_left_grid_pin_37_[0]:27 prog_clk[0]:546 5.001002e-05 +47 bottom_left_grid_pin_37_[0]:27 prog_clk[0]:552 3.493543e-05 +48 bottom_left_grid_pin_37_[0]:27 prog_clk[0]:558 3.777793e-05 +49 bottom_left_grid_pin_37_[0]:27 prog_clk[0]:559 6.506656e-05 +50 bottom_left_grid_pin_37_[0]:28 prog_clk[0]:560 4.733115e-07 +51 bottom_left_grid_pin_37_[0]:21 bottom_left_grid_pin_39_[0]:19 0.0003043996 +52 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_39_[0]:18 0.0003043996 +53 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_39_[0]:20 0.0005065516 +54 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_39_[0]:12 3.584757e-05 +55 bottom_left_grid_pin_37_[0]:10 bottom_left_grid_pin_39_[0]:12 2.142852e-05 +56 bottom_left_grid_pin_37_[0]:11 bottom_left_grid_pin_39_[0]:10 9.919797e-06 +57 bottom_left_grid_pin_37_[0]:12 bottom_left_grid_pin_39_[0]:11 9.919797e-06 +58 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_39_[0]:20 2.142852e-05 +59 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_39_[0]:12 7.736645e-05 +60 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_39_[0]:20 3.584757e-05 +61 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_39_[0]:21 0.0004291851 +62 bottom_left_grid_pin_37_[0]:21 bottom_left_grid_pin_40_[0]:23 0.0005808586 +63 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_40_[0]:12 0.0005808586 +64 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_40_[0]:20 0.0001182909 +65 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_40_[0]:17 5.656281e-05 +66 bottom_left_grid_pin_37_[0]:10 bottom_left_grid_pin_40_[0]:17 0.0001748754 +67 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_40_[0]:20 0.0001748754 +68 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_40_[0]:17 7.411193e-05 +69 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_40_[0]:20 5.656281e-05 +70 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_40_[0]:21 4.417897e-05 +71 bottom_left_grid_pin_37_[0]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.576262e-05 +72 bottom_left_grid_pin_37_[0]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.576262e-05 +73 bottom_left_grid_pin_37_[0]:24 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.237113e-05 +74 bottom_left_grid_pin_37_[0]:25 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.237113e-05 + +*RES +0 bottom_left_grid_pin_37_[0] bottom_left_grid_pin_37_[0]:28 0.0003105917 +1 bottom_left_grid_pin_37_[0]:24 bottom_left_grid_pin_37_[0]:23 0.0045 +2 bottom_left_grid_pin_37_[0]:24 bottom_left_grid_pin_37_[0]:15 0.0002767857 +3 bottom_left_grid_pin_37_[0]:23 bottom_left_grid_pin_37_[0]:22 0.002337054 +4 bottom_left_grid_pin_37_[0]:22 bottom_left_grid_pin_37_[0]:21 0.00341 +5 bottom_left_grid_pin_37_[0]:21 bottom_left_grid_pin_37_[0]:20 0.00648365 +6 bottom_left_grid_pin_37_[0]:19 bottom_left_grid_pin_37_[0]:18 0.002337054 +7 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_37_[0]:19 0.00341 +8 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:16 0.0001576087 +9 bottom_left_grid_pin_37_[0]:18 bottom_left_grid_pin_37_[0]:17 0.0045 +10 bottom_left_grid_pin_37_[0]:16 mux_bottom_track_31\/mux_l1_in_0_:A0 0.152 +11 bottom_left_grid_pin_37_[0]:25 bottom_left_grid_pin_37_[0]:24 0.01556697 +12 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_37_[0]:25 0.0045 +13 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_37_[0]:13 0.002732143 +14 bottom_left_grid_pin_37_[0]:5 mux_bottom_track_7\/mux_l1_in_1_:A1 0.152 +15 bottom_left_grid_pin_37_[0]:6 bottom_left_grid_pin_37_[0]:5 0.0045 +16 bottom_left_grid_pin_37_[0]:8 bottom_left_grid_pin_37_[0]:7 0.0045 +17 bottom_left_grid_pin_37_[0]:7 bottom_left_grid_pin_37_[0]:6 0.002044643 +18 bottom_left_grid_pin_37_[0]:9 bottom_left_grid_pin_37_[0]:8 0.008133929 +19 bottom_left_grid_pin_37_[0]:10 bottom_left_grid_pin_37_[0]:9 0.0045 +20 bottom_left_grid_pin_37_[0]:14 mux_bottom_track_15\/mux_l1_in_0_:A0 0.152 +21 bottom_left_grid_pin_37_[0]:11 mux_bottom_track_3\/mux_l1_in_1_:A1 0.152 +22 bottom_left_grid_pin_37_[0]:12 bottom_left_grid_pin_37_[0]:11 0.0007477679 +23 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_37_[0]:12 0.0045 +24 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_37_[0]:10 0.005727679 +25 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_37_[0]:26 0.02180581 +26 bottom_left_grid_pin_37_[0]:28 bottom_left_grid_pin_37_[0]:27 0.00341 +27 bottom_left_grid_pin_37_[0]:15 bottom_left_grid_pin_37_[0]:14 0.0005334822 + +*END + +*D_NET ropt_net_194 0.001646191 //LENGTH 16.000 LUMPCC 0 DR + +*CONN +*I mem_left_track_33\/BUFT_RR_148:X O *L 0 *C 8.045 78.200 +*I ropt_mt_inst_814:A I *L 0.001766 *C 3.220 82.960 +*N ropt_net_194:2 *C 3.220 82.960 +*N ropt_net_194:3 *C 3.220 82.915 +*N ropt_net_194:4 *C 3.220 77.565 +*N ropt_net_194:5 *C 3.265 77.520 +*N ropt_net_194:6 *C 10.120 77.520 +*N ropt_net_194:7 *C 10.120 78.200 +*N ropt_net_194:8 *C 8.082 78.200 + +*CAP +0 mem_left_track_33\/BUFT_RR_148:X 1e-06 +1 ropt_mt_inst_814:A 1e-06 +2 ropt_net_194:2 3.077026e-05 +3 ropt_net_194:3 0.000284538 +4 ropt_net_194:4 0.000284538 +5 ropt_net_194:5 0.0003344887 +6 ropt_net_194:6 0.000373409 +7 ropt_net_194:7 0.0001876837 +8 ropt_net_194:8 0.0001487634 + +*RES +0 mem_left_track_33\/BUFT_RR_148:X ropt_net_194:8 0.152 +1 ropt_net_194:8 ropt_net_194:7 0.001819196 +2 ropt_net_194:5 ropt_net_194:4 0.0045 +3 ropt_net_194:4 ropt_net_194:3 0.004776786 +4 ropt_net_194:2 ropt_mt_inst_814:A 0.152 +5 ropt_net_194:3 ropt_net_194:2 0.0045 +6 ropt_net_194:6 ropt_net_194:5 0.006120536 +7 ropt_net_194:7 ropt_net_194:6 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.002844624 //LENGTH 21.060 LUMPCC 0.0003320851 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 82.645 17.680 +*I mux_bottom_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 70.480 18.360 +*I mem_bottom_track_33\/FTB_31__56:A I *L 0.001746 *C 74.520 23.120 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 74.483 23.120 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 72.725 23.120 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 72.680 23.075 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 70.517 18.360 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 72.635 18.360 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 72.680 18.360 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 72.688 18.360 +*N mux_tree_tapbuf_size2_3_sram[1]:10 *C 82.333 18.360 +*N mux_tree_tapbuf_size2_3_sram[1]:11 *C 82.340 18.303 +*N mux_tree_tapbuf_size2_3_sram[1]:12 *C 82.340 17.725 +*N mux_tree_tapbuf_size2_3_sram[1]:13 *C 82.340 17.680 +*N mux_tree_tapbuf_size2_3_sram[1]:14 *C 82.645 17.680 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_33\/FTB_31__56:A 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 8.211858e-05 +4 mux_tree_tapbuf_size2_3_sram[1]:4 8.211858e-05 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0002185899 +6 mux_tree_tapbuf_size2_3_sram[1]:6 0.0001468496 +7 mux_tree_tapbuf_size2_3_sram[1]:7 0.0001468496 +8 mux_tree_tapbuf_size2_3_sram[1]:8 0.0002541601 +9 mux_tree_tapbuf_size2_3_sram[1]:9 0.0006811841 +10 mux_tree_tapbuf_size2_3_sram[1]:10 0.0006811841 +11 mux_tree_tapbuf_size2_3_sram[1]:11 5.927643e-05 +12 mux_tree_tapbuf_size2_3_sram[1]:12 5.927643e-05 +13 mux_tree_tapbuf_size2_3_sram[1]:13 5.14929e-05 +14 mux_tree_tapbuf_size2_3_sram[1]:14 4.643913e-05 +15 mux_tree_tapbuf_size2_3_sram[1]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.773258e-05 +16 mux_tree_tapbuf_size2_3_sram[1]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.716796e-05 +17 mux_tree_tapbuf_size2_3_sram[1]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.773258e-05 +18 mux_tree_tapbuf_size2_3_sram[1]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.716796e-05 +19 mux_tree_tapbuf_size2_3_sram[1]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.1142e-05 +20 mux_tree_tapbuf_size2_3_sram[1]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.1142e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:14 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_3_sram[1]:3 0.001569197 +2 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_3_sram[1]:3 mem_bottom_track_33\/FTB_31__56:A 0.152 +4 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:5 0.004209822 +6 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 0.00341 +7 mux_tree_tapbuf_size2_3_sram[1]:11 mux_tree_tapbuf_size2_3_sram[1]:10 0.00341 +8 mux_tree_tapbuf_size2_3_sram[1]:10 mux_tree_tapbuf_size2_3_sram[1]:9 0.00151105 +9 mux_tree_tapbuf_size2_3_sram[1]:13 mux_tree_tapbuf_size2_3_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size2_3_sram[1]:12 mux_tree_tapbuf_size2_3_sram[1]:11 0.0005156251 +11 mux_tree_tapbuf_size2_3_sram[1]:14 mux_tree_tapbuf_size2_3_sram[1]:13 0.0001657609 +12 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.001890625 +13 mux_tree_tapbuf_size2_3_sram[1]:6 mux_bottom_track_33\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.003356816 //LENGTH 27.900 LUMPCC 0.0002592674 DR + +*CONN +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 45.385 55.420 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 41.115 39.100 +*I mux_bottom_track_13\/mux_l1_in_1_:S I *L 0.00357 *C 42.200 36.040 +*I mux_bottom_track_13\/mux_l1_in_0_:S I *L 0.00357 *C 39.920 42.160 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 39.958 42.160 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 42.185 36.040 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 41.883 36.040 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 41.860 36.085 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 41.153 39.100 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 41.815 39.100 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 41.860 39.100 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 41.860 42.115 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 41.860 42.190 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 41.860 42.500 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 45.035 42.500 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 45.080 42.545 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 45.080 55.375 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 45.080 55.420 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 45.385 55.420 + +*CAP +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_13\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_track_13\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 0.0001232395 +5 mux_tree_tapbuf_size3_1_sram[0]:5 6.040951e-05 +6 mux_tree_tapbuf_size3_1_sram[0]:6 6.040951e-05 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0001688687 +8 mux_tree_tapbuf_size3_1_sram[0]:8 6.243504e-05 +9 mux_tree_tapbuf_size3_1_sram[0]:9 6.243504e-05 +10 mux_tree_tapbuf_size3_1_sram[0]:10 0.0003750781 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.0001735834 +12 mux_tree_tapbuf_size3_1_sram[0]:12 0.0001490696 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0002074861 +14 mux_tree_tapbuf_size3_1_sram[0]:14 0.0001816561 +15 mux_tree_tapbuf_size3_1_sram[0]:15 0.0006857375 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.0006857375 +17 mux_tree_tapbuf_size3_1_sram[0]:17 5.156497e-05 +18 mux_tree_tapbuf_size3_1_sram[0]:18 4.583802e-05 +19 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 3.648988e-05 +20 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 3.648988e-05 +21 mux_tree_tapbuf_size3_1_sram[0]:12 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.321222e-05 +22 mux_tree_tapbuf_size3_1_sram[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.321222e-05 +23 mux_tree_tapbuf_size3_1_sram[0]:14 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.993157e-05 +24 mux_tree_tapbuf_size3_1_sram[0]:13 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.993157e-05 + +*RES +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:5 mux_bottom_track_13\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[0]:6 mux_tree_tapbuf_size3_1_sram[0]:5 0.0001644022 +3 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:4 0.001698661 +6 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.002691964 +7 mux_tree_tapbuf_size3_1_sram[0]:4 mux_bottom_track_13\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:8 0.0005915179 +9 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:7 0.002691964 +11 mux_tree_tapbuf_size3_1_sram[0]:8 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.002834822 +13 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.0045 +14 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.01145536 +16 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.0001657609 +17 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[0] 0.00190714 //LENGTH 16.830 LUMPCC 0 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.145 85.680 +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 72.855 82.620 +*I mux_left_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 81.060 88.400 +*N mux_tree_tapbuf_size4_3_sram[0]:3 *C 80.960 88.400 +*N mux_tree_tapbuf_size4_3_sram[0]:4 *C 80.960 88.355 +*N mux_tree_tapbuf_size4_3_sram[0]:5 *C 80.960 85.725 +*N mux_tree_tapbuf_size4_3_sram[0]:6 *C 80.915 85.680 +*N mux_tree_tapbuf_size4_3_sram[0]:7 *C 72.855 82.620 +*N mux_tree_tapbuf_size4_3_sram[0]:8 *C 72.680 82.620 +*N mux_tree_tapbuf_size4_3_sram[0]:9 *C 72.680 82.665 +*N mux_tree_tapbuf_size4_3_sram[0]:10 *C 72.680 85.635 +*N mux_tree_tapbuf_size4_3_sram[0]:11 *C 72.680 85.680 +*N mux_tree_tapbuf_size4_3_sram[0]:12 *C 71.183 85.680 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_33\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_3_sram[0]:3 3.05627e-05 +4 mux_tree_tapbuf_size4_3_sram[0]:4 0.0001539213 +5 mux_tree_tapbuf_size4_3_sram[0]:5 0.0001539213 +6 mux_tree_tapbuf_size4_3_sram[0]:6 0.000430895 +7 mux_tree_tapbuf_size4_3_sram[0]:7 5.885663e-05 +8 mux_tree_tapbuf_size4_3_sram[0]:8 5.942734e-05 +9 mux_tree_tapbuf_size4_3_sram[0]:9 0.0001825725 +10 mux_tree_tapbuf_size4_3_sram[0]:10 0.0001825725 +11 mux_tree_tapbuf_size4_3_sram[0]:11 0.0005563932 +12 mux_tree_tapbuf_size4_3_sram[0]:12 9.501799e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_3_sram[0]:12 0.152 +1 mux_tree_tapbuf_size4_3_sram[0]:11 mux_tree_tapbuf_size4_3_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size4_3_sram[0]:11 mux_tree_tapbuf_size4_3_sram[0]:6 0.007352679 +3 mux_tree_tapbuf_size4_3_sram[0]:10 mux_tree_tapbuf_size4_3_sram[0]:9 0.002651786 +4 mux_tree_tapbuf_size4_3_sram[0]:8 mux_tree_tapbuf_size4_3_sram[0]:7 9.51087e-05 +5 mux_tree_tapbuf_size4_3_sram[0]:9 mux_tree_tapbuf_size4_3_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size4_3_sram[0]:7 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size4_3_sram[0]:6 mux_tree_tapbuf_size4_3_sram[0]:5 0.0045 +8 mux_tree_tapbuf_size4_3_sram[0]:5 mux_tree_tapbuf_size4_3_sram[0]:4 0.002348214 +9 mux_tree_tapbuf_size4_3_sram[0]:3 mux_left_track_33\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size4_3_sram[0]:4 mux_tree_tapbuf_size4_3_sram[0]:3 0.0045 +11 mux_tree_tapbuf_size4_3_sram[0]:12 mux_tree_tapbuf_size4_3_sram[0]:11 0.001337054 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[2] 0.0009212385 //LENGTH 7.235 LUMPCC 0.0001228486 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 65.165 39.440 +*I mux_left_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 64.980 41.480 +*I mem_left_track_1\/FTB_9__34:A I *L 0.001746 *C 69.460 39.440 +*N mux_tree_tapbuf_size5_3_sram[2]:3 *C 69.422 39.440 +*N mux_tree_tapbuf_size5_3_sram[2]:4 *C 64.860 41.480 +*N mux_tree_tapbuf_size5_3_sram[2]:5 *C 64.860 41.435 +*N mux_tree_tapbuf_size5_3_sram[2]:6 *C 64.860 39.485 +*N mux_tree_tapbuf_size5_3_sram[2]:7 *C 64.860 39.440 +*N mux_tree_tapbuf_size5_3_sram[2]:8 *C 65.203 39.440 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_1\/FTB_9__34:A 1e-06 +3 mux_tree_tapbuf_size5_3_sram[2]:3 0.0002636022 +4 mux_tree_tapbuf_size5_3_sram[2]:4 3.635672e-05 +5 mux_tree_tapbuf_size5_3_sram[2]:5 8.041285e-05 +6 mux_tree_tapbuf_size5_3_sram[2]:6 8.041285e-05 +7 mux_tree_tapbuf_size5_3_sram[2]:7 5.099492e-05 +8 mux_tree_tapbuf_size5_3_sram[2]:8 0.0002836104 +9 mux_tree_tapbuf_size5_3_sram[2]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.142429e-05 +10 mux_tree_tapbuf_size5_3_sram[2]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.142429e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_3_sram[2]:8 0.152 +1 mux_tree_tapbuf_size5_3_sram[2]:4 mux_left_track_1\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_3_sram[2]:5 mux_tree_tapbuf_size5_3_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size5_3_sram[2]:7 mux_tree_tapbuf_size5_3_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size5_3_sram[2]:6 mux_tree_tapbuf_size5_3_sram[2]:5 0.001741072 +5 mux_tree_tapbuf_size5_3_sram[2]:3 mem_left_track_1\/FTB_9__34:A 0.152 +6 mux_tree_tapbuf_size5_3_sram[2]:8 mux_tree_tapbuf_size5_3_sram[2]:7 0.0001861413 +7 mux_tree_tapbuf_size5_3_sram[2]:8 mux_tree_tapbuf_size5_3_sram[2]:3 0.003767857 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_1_ccff_tail[0] 0.000897428 //LENGTH 6.930 LUMPCC 0 DR + +*CONN +*I mem_right_track_16\/FTB_7__32:X O *L 0 *C 98.675 47.260 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 95.395 44.540 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 *C 95.433 44.540 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 *C 96.095 44.540 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 *C 96.140 44.585 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 *C 96.140 47.215 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 *C 96.185 47.260 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 *C 98.638 47.260 + +*CAP +0 mem_right_track_16\/FTB_7__32:X 1e-06 +1 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 8.464951e-05 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 8.464951e-05 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.0001712593 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0001712593 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.0001918052 +7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.0001918052 + +*RES +0 mem_right_track_16\/FTB_7__32:X mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.002189732 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[1] 0.00409932 //LENGTH 30.180 LUMPCC 0.0001290598 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.045 42.500 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 43.415 47.940 +*I mux_left_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 46.100 45.175 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 51.160 51.000 +*N mux_tree_tapbuf_size6_3_sram[1]:4 *C 51.123 51.000 +*N mux_tree_tapbuf_size6_3_sram[1]:5 *C 48.345 51.000 +*N mux_tree_tapbuf_size6_3_sram[1]:6 *C 48.300 50.955 +*N mux_tree_tapbuf_size6_3_sram[1]:7 *C 46.100 45.175 +*N mux_tree_tapbuf_size6_3_sram[1]:8 *C 43.453 47.940 +*N mux_tree_tapbuf_size6_3_sram[1]:9 *C 45.955 47.940 +*N mux_tree_tapbuf_size6_3_sram[1]:10 *C 46.000 47.895 +*N mux_tree_tapbuf_size6_3_sram[1]:11 *C 46.000 44.925 +*N mux_tree_tapbuf_size6_3_sram[1]:12 *C 46.157 44.880 +*N mux_tree_tapbuf_size6_3_sram[1]:13 *C 48.255 44.880 +*N mux_tree_tapbuf_size6_3_sram[1]:14 *C 48.300 44.925 +*N mux_tree_tapbuf_size6_3_sram[1]:15 *C 48.300 46.240 +*N mux_tree_tapbuf_size6_3_sram[1]:16 *C 48.308 46.240 +*N mux_tree_tapbuf_size6_3_sram[1]:17 *C 54.733 46.240 +*N mux_tree_tapbuf_size6_3_sram[1]:18 *C 54.740 46.183 +*N mux_tree_tapbuf_size6_3_sram[1]:19 *C 54.740 42.545 +*N mux_tree_tapbuf_size6_3_sram[1]:20 *C 54.740 42.500 +*N mux_tree_tapbuf_size6_3_sram[1]:21 *C 55.045 42.500 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_5\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size6_3_sram[1]:4 0.0002301759 +5 mux_tree_tapbuf_size6_3_sram[1]:5 0.0002301759 +6 mux_tree_tapbuf_size6_3_sram[1]:6 0.0002790158 +7 mux_tree_tapbuf_size6_3_sram[1]:7 6.551699e-05 +8 mux_tree_tapbuf_size6_3_sram[1]:8 0.0001840561 +9 mux_tree_tapbuf_size6_3_sram[1]:9 0.0001840561 +10 mux_tree_tapbuf_size6_3_sram[1]:10 0.0001938073 +11 mux_tree_tapbuf_size6_3_sram[1]:11 0.0001938073 +12 mux_tree_tapbuf_size6_3_sram[1]:12 0.0001678495 +13 mux_tree_tapbuf_size6_3_sram[1]:13 0.0001326117 +14 mux_tree_tapbuf_size6_3_sram[1]:14 8.687545e-05 +15 mux_tree_tapbuf_size6_3_sram[1]:15 0.0004054298 +16 mux_tree_tapbuf_size6_3_sram[1]:16 0.0005217038 +17 mux_tree_tapbuf_size6_3_sram[1]:17 0.0005217038 +18 mux_tree_tapbuf_size6_3_sram[1]:18 0.0002310348 +19 mux_tree_tapbuf_size6_3_sram[1]:19 0.0002310348 +20 mux_tree_tapbuf_size6_3_sram[1]:20 5.41155e-05 +21 mux_tree_tapbuf_size6_3_sram[1]:21 5.328977e-05 +22 mux_tree_tapbuf_size6_3_sram[1]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.452991e-05 +23 mux_tree_tapbuf_size6_3_sram[1]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.452991e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_3_sram[1]:21 0.152 +1 mux_tree_tapbuf_size6_3_sram[1]:7 mux_left_track_5\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_3_sram[1]:5 mux_tree_tapbuf_size6_3_sram[1]:4 0.002479911 +3 mux_tree_tapbuf_size6_3_sram[1]:6 mux_tree_tapbuf_size6_3_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size6_3_sram[1]:4 mux_left_track_5\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_3_sram[1]:13 mux_tree_tapbuf_size6_3_sram[1]:12 0.001872768 +6 mux_tree_tapbuf_size6_3_sram[1]:14 mux_tree_tapbuf_size6_3_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size6_3_sram[1]:12 mux_tree_tapbuf_size6_3_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size6_3_sram[1]:12 mux_tree_tapbuf_size6_3_sram[1]:7 0.0001271552 +9 mux_tree_tapbuf_size6_3_sram[1]:11 mux_tree_tapbuf_size6_3_sram[1]:10 0.002651786 +10 mux_tree_tapbuf_size6_3_sram[1]:9 mux_tree_tapbuf_size6_3_sram[1]:8 0.002234375 +11 mux_tree_tapbuf_size6_3_sram[1]:10 mux_tree_tapbuf_size6_3_sram[1]:9 0.0045 +12 mux_tree_tapbuf_size6_3_sram[1]:8 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size6_3_sram[1]:15 mux_tree_tapbuf_size6_3_sram[1]:14 0.001174107 +14 mux_tree_tapbuf_size6_3_sram[1]:15 mux_tree_tapbuf_size6_3_sram[1]:6 0.004209822 +15 mux_tree_tapbuf_size6_3_sram[1]:16 mux_tree_tapbuf_size6_3_sram[1]:15 0.00341 +16 mux_tree_tapbuf_size6_3_sram[1]:18 mux_tree_tapbuf_size6_3_sram[1]:17 0.00341 +17 mux_tree_tapbuf_size6_3_sram[1]:17 mux_tree_tapbuf_size6_3_sram[1]:16 0.001006583 +18 mux_tree_tapbuf_size6_3_sram[1]:20 mux_tree_tapbuf_size6_3_sram[1]:19 0.0045 +19 mux_tree_tapbuf_size6_3_sram[1]:19 mux_tree_tapbuf_size6_3_sram[1]:18 0.003247768 +20 mux_tree_tapbuf_size6_3_sram[1]:21 mux_tree_tapbuf_size6_3_sram[1]:20 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[1] 0.003540942 //LENGTH 23.480 LUMPCC 0.001495449 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 27.445 47.940 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 19.955 53.380 +*I mux_bottom_track_7\/mux_l2_in_1_:S I *L 0.00357 *C 19.220 46.920 +*I mux_bottom_track_7\/mux_l2_in_0_:S I *L 0.00357 *C 24.480 42.160 +*N mux_tree_tapbuf_size7_3_sram[1]:4 *C 24.495 42.160 +*N mux_tree_tapbuf_size7_3_sram[1]:5 *C 24.818 42.160 +*N mux_tree_tapbuf_size7_3_sram[1]:6 *C 24.840 42.205 +*N mux_tree_tapbuf_size7_3_sram[1]:7 *C 19.220 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:8 *C 19.220 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:9 *C 19.227 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:10 *C 19.992 53.380 +*N mux_tree_tapbuf_size7_3_sram[1]:11 *C 20.655 53.380 +*N mux_tree_tapbuf_size7_3_sram[1]:12 *C 20.700 53.335 +*N mux_tree_tapbuf_size7_3_sram[1]:13 *C 20.700 46.977 +*N mux_tree_tapbuf_size7_3_sram[1]:14 *C 20.700 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:15 *C 24.832 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:16 *C 24.840 46.920 +*N mux_tree_tapbuf_size7_3_sram[1]:17 *C 24.840 47.895 +*N mux_tree_tapbuf_size7_3_sram[1]:18 *C 24.885 47.940 +*N mux_tree_tapbuf_size7_3_sram[1]:19 *C 27.408 47.940 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_7\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_track_7\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_3_sram[1]:4 5.390009e-05 +5 mux_tree_tapbuf_size7_3_sram[1]:5 5.390009e-05 +6 mux_tree_tapbuf_size7_3_sram[1]:6 0.0002152738 +7 mux_tree_tapbuf_size7_3_sram[1]:7 3.514244e-05 +8 mux_tree_tapbuf_size7_3_sram[1]:8 3.89948e-05 +9 mux_tree_tapbuf_size7_3_sram[1]:9 5.494513e-05 +10 mux_tree_tapbuf_size7_3_sram[1]:10 6.721122e-05 +11 mux_tree_tapbuf_size7_3_sram[1]:11 6.721122e-05 +12 mux_tree_tapbuf_size7_3_sram[1]:12 0.0003383602 +13 mux_tree_tapbuf_size7_3_sram[1]:13 0.0003383602 +14 mux_tree_tapbuf_size7_3_sram[1]:14 6.78524e-05 +15 mux_tree_tapbuf_size7_3_sram[1]:15 1.290727e-05 +16 mux_tree_tapbuf_size7_3_sram[1]:16 0.000304056 +17 mux_tree_tapbuf_size7_3_sram[1]:17 4.890303e-05 +18 mux_tree_tapbuf_size7_3_sram[1]:18 0.000172238 +19 mux_tree_tapbuf_size7_3_sram[1]:19 0.000172238 +20 mux_tree_tapbuf_size7_3_sram[1]:16 chanx_left_in[5]:37 1.64157e-05 +21 mux_tree_tapbuf_size7_3_sram[1]:16 chanx_left_in[5]:41 0.0001154549 +22 mux_tree_tapbuf_size7_3_sram[1]:15 chanx_left_in[5]:42 0.0002177537 +23 mux_tree_tapbuf_size7_3_sram[1]:17 chanx_left_in[5]:37 2.848607e-05 +24 mux_tree_tapbuf_size7_3_sram[1]:9 chanx_left_in[5] 9.296468e-05 +25 mux_tree_tapbuf_size7_3_sram[1]:14 chanx_left_in[5] 0.0002177537 +26 mux_tree_tapbuf_size7_3_sram[1]:14 chanx_left_in[5]:42 9.296468e-05 +27 mux_tree_tapbuf_size7_3_sram[1]:5 chanx_left_in[5]:38 5.556792e-06 +28 mux_tree_tapbuf_size7_3_sram[1]:6 chanx_left_in[5]:40 8.696884e-05 +29 mux_tree_tapbuf_size7_3_sram[1]:6 chanx_left_in[5]:41 1.64157e-05 +30 mux_tree_tapbuf_size7_3_sram[1]:4 chanx_left_in[5]:39 5.556792e-06 +31 mux_tree_tapbuf_size7_3_sram[1]:15 prog_clk[0]:481 0.0002438484 +32 mux_tree_tapbuf_size7_3_sram[1]:9 prog_clk[0]:480 3.532093e-05 +33 mux_tree_tapbuf_size7_3_sram[1]:13 prog_clk[0]:475 6.901325e-07 +34 mux_tree_tapbuf_size7_3_sram[1]:13 prog_clk[0]:476 1.971915e-05 +35 mux_tree_tapbuf_size7_3_sram[1]:14 prog_clk[0]:480 0.0002438484 +36 mux_tree_tapbuf_size7_3_sram[1]:14 prog_clk[0]:481 3.532093e-05 +37 mux_tree_tapbuf_size7_3_sram[1]:12 prog_clk[0]:472 6.901325e-07 +38 mux_tree_tapbuf_size7_3_sram[1]:12 prog_clk[0]:475 1.971915e-05 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_3_sram[1]:19 0.152 +1 mux_tree_tapbuf_size7_3_sram[1]:16 mux_tree_tapbuf_size7_3_sram[1]:15 0.00341 +2 mux_tree_tapbuf_size7_3_sram[1]:16 mux_tree_tapbuf_size7_3_sram[1]:6 0.004209822 +3 mux_tree_tapbuf_size7_3_sram[1]:15 mux_tree_tapbuf_size7_3_sram[1]:14 0.000647425 +4 mux_tree_tapbuf_size7_3_sram[1]:18 mux_tree_tapbuf_size7_3_sram[1]:17 0.0045 +5 mux_tree_tapbuf_size7_3_sram[1]:17 mux_tree_tapbuf_size7_3_sram[1]:16 0.0008705358 +6 mux_tree_tapbuf_size7_3_sram[1]:19 mux_tree_tapbuf_size7_3_sram[1]:18 0.002252232 +7 mux_tree_tapbuf_size7_3_sram[1]:8 mux_tree_tapbuf_size7_3_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size7_3_sram[1]:9 mux_tree_tapbuf_size7_3_sram[1]:8 0.00341 +9 mux_tree_tapbuf_size7_3_sram[1]:7 mux_bottom_track_7\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size7_3_sram[1]:13 mux_tree_tapbuf_size7_3_sram[1]:12 0.005676339 +11 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:13 0.00341 +12 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:9 0.0002306917 +13 mux_tree_tapbuf_size7_3_sram[1]:11 mux_tree_tapbuf_size7_3_sram[1]:10 0.0005915179 +14 mux_tree_tapbuf_size7_3_sram[1]:12 mux_tree_tapbuf_size7_3_sram[1]:11 0.0045 +15 mux_tree_tapbuf_size7_3_sram[1]:10 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size7_3_sram[1]:5 mux_tree_tapbuf_size7_3_sram[1]:4 0.0001752718 +17 mux_tree_tapbuf_size7_3_sram[1]:6 mux_tree_tapbuf_size7_3_sram[1]:5 0.0045 +18 mux_tree_tapbuf_size7_3_sram[1]:4 mux_bottom_track_7\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001701917 //LENGTH 15.340 LUMPCC 8.759867e-05 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_1_:X O *L 0 *C 61.925 66.640 +*I mux_right_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 70.555 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 70.517 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 69.045 60.860 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 69.000 60.905 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 69.000 66.595 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 68.955 66.640 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 61.963 66.640 + +*CAP +0 mux_right_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.164635e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.164635e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002995128 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002995128 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004149998 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004149998 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.585436e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.585436e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.794497e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.794497e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_1_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001314732 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005080358 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006243304 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002267565 //LENGTH 17.440 LUMPCC 0.0002858463 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_1_:X O *L 0 *C 72.855 26.520 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.655 33.320 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 63.693 33.320 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 67.115 33.320 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 67.160 33.275 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 67.160 27.258 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 67.168 27.200 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 72.672 27.200 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 72.680 27.143 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 72.680 26.565 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 72.680 26.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 72.855 26.520 + +*CAP +0 mux_left_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002488263 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002488263 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003110951 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003110951 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003178006 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003178006 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.410289e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.410289e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.880071e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.726823e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[1]:13 5.496056e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[1]:14 5.496056e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[1]:15 2.219995e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[1]:3 2.219995e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 bottom_left_grid_pin_37_[0]:21 6.576262e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 bottom_left_grid_pin_37_[0]:20 6.576262e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003055804 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005372768 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00086245 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000515625 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001578432 //LENGTH 12.220 LUMPCC 0.0004927262 DR + +*CONN +*I mux_bottom_track_13\/mux_l1_in_0_:X O *L 0 *C 40.765 41.820 +*I mux_bottom_track_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 46.920 36.380 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 46.920 36.380 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 46.920 36.425 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 46.920 41.775 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 46.875 41.820 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 40.803 41.820 + +*CAP +0 mux_bottom_track_13\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_13\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.345652e-05 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002016617 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002016617 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003234631 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003234631 +7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_1_sram[0]:4 5.321222e-05 +8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_1_sram[0]:13 3.993157e-05 +9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[0]:12 5.321222e-05 +10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[0]:14 3.993157e-05 +11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0001532193 +12 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001532193 + +*RES +0 mux_bottom_track_13\/mux_l1_in_0_:X mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.005421876 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004776786 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_13\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008972128 //LENGTH 7.145 LUMPCC 0.0001539683 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_2_:X O *L 0 *C 36.165 26.180 +*I mux_bottom_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 39.660 28.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.623 28.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 37.765 28.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 37.720 28.855 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 37.720 26.225 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 37.675 26.180 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 36.203 26.180 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.000143735 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000143735 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001211474 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001211474 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001057398 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001057398 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.698417e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.698417e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001658482 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001067336 //LENGTH 6.815 LUMPCC 0.0004670567 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 36.625 42.840 +*I mux_bottom_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 38.280 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 38.242 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 36.845 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 36.800 47.215 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 36.800 42.885 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 36.800 42.840 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 36.625 42.840 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001287191 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001287191 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001092353 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001092353 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.975912e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.261082e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[10]:19 0.0001149294 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[10]:7 0.0001149294 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_2_sram[1]:13 0.0001185228 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_2_sram[1]:5 7.613272e-08 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_2_sram[1]:6 0.0001185228 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size7_2_sram[1]:4 7.613272e-08 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001247768 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001153964 //LENGTH 9.830 LUMPCC 0.0001053584 DR + +*CONN +*I mux_bottom_track_11\/mux_l2_in_1_:X O *L 0 *C 38.925 74.120 +*I mux_bottom_track_11\/mux_l3_in_0_:A0 I *L 0.001631 *C 40.195 66.300 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 40.157 66.300 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 39.145 66.300 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 39.100 66.345 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.100 74.075 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.100 74.120 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 38.925 74.120 + +*CAP +0 mux_bottom_track_11\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_11\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.419462e-05 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.419462e-05 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004066857 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004066857 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.448603e-05 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.035909e-05 +8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_left_in[4]:27 5.267921e-05 +9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_left_in[4]:28 5.267921e-05 + +*RES +0 mux_bottom_track_11\/mux_l2_in_1_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_11\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0009040179 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.006901786 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001793148 //LENGTH 14.850 LUMPCC 0.0002532183 DR + +*CONN +*I mux_bottom_track_35\/mux_l1_in_0_:X O *L 0 *C 67.335 25.500 +*I mux_bottom_track_35\/mux_l2_in_0_:A1 I *L 0.00198 *C 66.145 12.580 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 66.183 12.580 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 67.115 12.580 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 67.160 12.625 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 67.160 25.455 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 67.160 25.500 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 67.335 25.500 + +*CAP +0 mux_bottom_track_35\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_35\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.819305e-05 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.819305e-05 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0006202504 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0006202504 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.145006e-05 +7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.959284e-05 +8 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_166:13 8.595804e-05 +9 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_166:14 4.065114e-05 +10 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_166:10 4.065114e-05 +11 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_166:14 8.595804e-05 + +*RES +0 mux_bottom_track_35\/mux_l1_in_0_:X mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_35\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008325893 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01145536 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_213 0.0006784868 //LENGTH 5.065 LUMPCC 0.0001704363 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 74.060 3.740 +*I ropt_mt_inst_831:A I *L 0.001766 *C 72.680 6.800 +*N ropt_net_213:2 *C 72.680 6.800 +*N ropt_net_213:3 *C 72.680 6.755 +*N ropt_net_213:4 *C 72.680 3.785 +*N ropt_net_213:5 *C 72.725 3.740 +*N ropt_net_213:6 *C 74.023 3.740 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 ropt_mt_inst_831:A 1e-06 +2 ropt_net_213:2 3.567472e-05 +3 ropt_net_213:3 0.0001247851 +4 ropt_net_213:4 0.0001247851 +5 ropt_net_213:5 0.0001104028 +6 ropt_net_213:6 0.0001104028 +7 ropt_net_213:4 chany_bottom_out[18] 8.521817e-05 +8 ropt_net_213:3 chany_bottom_out[18]:2 8.521817e-05 + +*RES +0 ropt_mt_inst_800:X ropt_net_213:6 0.152 +1 ropt_net_213:6 ropt_net_213:5 0.001158482 +2 ropt_net_213:5 ropt_net_213:4 0.0045 +3 ropt_net_213:4 ropt_net_213:3 0.002651786 +4 ropt_net_213:2 ropt_mt_inst_831:A 0.152 +5 ropt_net_213:3 ropt_net_213:2 0.0045 + +*END + +*D_NET ropt_net_209 0.0008164849 //LENGTH 6.635 LUMPCC 7.667621e-05 DR + +*CONN +*I ropt_mt_inst_817:X O *L 0 *C 7.095 64.600 +*I ropt_mt_inst_827:A I *L 0.001767 *C 3.220 66.640 +*N ropt_net_209:2 *C 3.258 66.640 +*N ropt_net_209:3 *C 6.855 66.640 +*N ropt_net_209:4 *C 6.900 66.595 +*N ropt_net_209:5 *C 6.900 64.645 +*N ropt_net_209:6 *C 6.900 64.600 +*N ropt_net_209:7 *C 7.095 64.600 + +*CAP +0 ropt_mt_inst_817:X 1e-06 +1 ropt_mt_inst_827:A 1e-06 +2 ropt_net_209:2 0.0002032414 +3 ropt_net_209:3 0.0002032414 +4 ropt_net_209:4 0.0001071477 +5 ropt_net_209:5 0.0001071477 +6 ropt_net_209:6 5.822055e-05 +7 ropt_net_209:7 5.880992e-05 +8 ropt_net_209:2 ropt_net_197:6 2.010206e-05 +9 ropt_net_209:3 ropt_net_197:7 2.010206e-05 +10 ropt_net_209:4 ropt_net_197:5 1.823605e-05 +11 ropt_net_209:5 ropt_net_197:4 1.823605e-05 + +*RES +0 ropt_mt_inst_817:X ropt_net_209:7 0.152 +1 ropt_net_209:2 ropt_mt_inst_827:A 0.152 +2 ropt_net_209:3 ropt_net_209:2 0.003212054 +3 ropt_net_209:4 ropt_net_209:3 0.0045 +4 ropt_net_209:6 ropt_net_209:5 0.0045 +5 ropt_net_209:5 ropt_net_209:4 0.001741072 +6 ropt_net_209:7 ropt_net_209:6 0.0001059783 + +*END + +*D_NET chanx_right_out[13] 0.001139645 //LENGTH 11.840 LUMPCC 0 DR + +*CONN +*I BUFT_P_147:X O *L 0 *C 134.975 61.200 +*P chanx_right_out[13] O *L 0.7423 *C 140.382 66.640 +*N chanx_right_out[13]:2 *C 140.300 66.640 +*N chanx_right_out[13]:3 *C 140.300 66.640 +*N chanx_right_out[13]:4 *C 138.920 66.640 +*N chanx_right_out[13]:5 *C 138.920 61.245 +*N chanx_right_out[13]:6 *C 138.875 61.200 +*N chanx_right_out[13]:7 *C 135.013 61.200 + +*CAP +0 BUFT_P_147:X 1e-06 +1 chanx_right_out[13] 2.6922e-05 +2 chanx_right_out[13]:2 2.6922e-05 +3 chanx_right_out[13]:3 9.467183e-05 +4 chanx_right_out[13]:4 0.0003136083 +5 chanx_right_out[13]:5 0.0002472035 +6 chanx_right_out[13]:6 0.0002146588 +7 chanx_right_out[13]:7 0.0002146588 + +*RES +0 BUFT_P_147:X chanx_right_out[13]:7 0.152 +1 chanx_right_out[13]:7 chanx_right_out[13]:6 0.003448661 +2 chanx_right_out[13]:6 chanx_right_out[13]:5 0.0045 +3 chanx_right_out[13]:5 chanx_right_out[13]:4 0.004816964 +4 chanx_right_out[13]:3 chanx_right_out[13]:2 0.00341 +5 chanx_right_out[13]:2 chanx_right_out[13] 2.35e-05 +6 chanx_right_out[13]:4 chanx_right_out[13]:3 0.001232143 + +*END + +*D_NET chanx_right_in[12] 0.0254417 //LENGTH 201.753 LUMPCC 0.007007549 DR + +*CONN +*P chanx_right_in[12] I *L 0.29796 *C 140.450 74.800 +*I mux_bottom_track_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 50.240 28.900 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 61.355 31.620 +*I BUFT_P_129:A I *L 0.001776 *C 14.720 82.960 +*N chanx_right_in[12]:4 *C 14.720 82.960 +*N chanx_right_in[12]:5 *C 14.720 82.915 +*N chanx_right_in[12]:6 *C 14.720 78.245 +*N chanx_right_in[12]:7 *C 14.765 78.200 +*N chanx_right_in[12]:8 *C 40.480 78.200 +*N chanx_right_in[12]:9 *C 40.480 77.520 +*N chanx_right_in[12]:10 *C 46.415 77.520 +*N chanx_right_in[12]:11 *C 46.460 77.475 +*N chanx_right_in[12]:12 *C 46.460 72.818 +*N chanx_right_in[12]:13 *C 46.468 72.760 +*N chanx_right_in[12]:14 *C 48.050 28.900 +*N chanx_right_in[12]:15 *C 61.355 31.620 +*N chanx_right_in[12]:16 *C 61.180 31.620 +*N chanx_right_in[12]:17 *C 61.180 31.575 +*N chanx_right_in[12]:18 *C 61.180 29.285 +*N chanx_right_in[12]:19 *C 61.135 29.240 +*N chanx_right_in[12]:20 *C 50.140 29.240 +*N chanx_right_in[12]:21 *C 50.153 28.923 +*N chanx_right_in[12]:22 *C 50.140 28.900 +*N chanx_right_in[12]:23 *C 48.805 28.900 +*N chanx_right_in[12]:24 *C 48.760 28.900 +*N chanx_right_in[12]:25 *C 48.758 28.900 +*N chanx_right_in[12]:26 *C 48.760 28.908 +*N chanx_right_in[12]:27 *C 48.760 72.752 +*N chanx_right_in[12]:28 *C 48.760 72.760 +*N chanx_right_in[12]:29 *C 98.760 72.760 +*N chanx_right_in[12]:30 *C 131.553 72.760 +*N chanx_right_in[12]:31 *C 131.560 72.818 +*N chanx_right_in[12]:32 *C 131.560 74.743 +*N chanx_right_in[12]:33 *C 131.567 74.800 + +*CAP +0 chanx_right_in[12] 0.0006382496 +1 mux_bottom_track_15\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +3 BUFT_P_129:A 1e-06 +4 chanx_right_in[12]:4 3.18582e-05 +5 chanx_right_in[12]:5 0.0002435284 +6 chanx_right_in[12]:6 0.0002435284 +7 chanx_right_in[12]:7 0.001340621 +8 chanx_right_in[12]:8 0.001385981 +9 chanx_right_in[12]:9 0.0003274773 +10 chanx_right_in[12]:10 0.0002821173 +11 chanx_right_in[12]:11 0.0002005464 +12 chanx_right_in[12]:12 0.0002005464 +13 chanx_right_in[12]:13 9.720305e-05 +14 chanx_right_in[12]:14 8.883116e-05 +15 chanx_right_in[12]:15 5.60228e-05 +16 chanx_right_in[12]:16 5.591554e-05 +17 chanx_right_in[12]:17 0.0001550628 +18 chanx_right_in[12]:18 0.0001550628 +19 chanx_right_in[12]:19 0.0007282899 +20 chanx_right_in[12]:20 0.000749152 +21 chanx_right_in[12]:21 3.289015e-05 +22 chanx_right_in[12]:22 0.0001342948 +23 chanx_right_in[12]:23 0.0001222668 +24 chanx_right_in[12]:24 3.950049e-05 +25 chanx_right_in[12]:25 8.883116e-05 +26 chanx_right_in[12]:26 0.001771964 +27 chanx_right_in[12]:27 0.001771964 +28 chanx_right_in[12]:28 0.001995532 +29 chanx_right_in[12]:29 0.003256748 +30 chanx_right_in[12]:30 0.00135842 +31 chanx_right_in[12]:31 0.0001202492 +32 chanx_right_in[12]:32 0.0001202492 +33 chanx_right_in[12]:33 0.0006382496 +34 chanx_right_in[12]:27 chanx_right_in[13]:24 0.0003016437 +35 chanx_right_in[12]:27 chanx_right_in[13]:26 0.0001191872 +36 chanx_right_in[12]:26 chanx_right_in[13]:9 0.0001191872 +37 chanx_right_in[12]:26 chanx_right_in[13]:25 0.0003016437 +38 chanx_right_in[12]:28 chanx_left_in[12]:11 0.0003630177 +39 chanx_right_in[12]:30 chanx_left_in[12]:10 0.0001572225 +40 chanx_right_in[12]:18 chanx_left_in[12]:17 7.434614e-08 +41 chanx_right_in[12]:17 chanx_left_in[12]:18 7.434614e-08 +42 chanx_right_in[12]:29 chanx_left_in[12]:10 0.0003630177 +43 chanx_right_in[12]:29 chanx_left_in[12]:11 0.0001572225 +44 chanx_right_in[12]:28 chanx_left_in[13]:35 0.0001721555 +45 chanx_right_in[12]:28 chanx_left_in[13]:31 7.642603e-06 +46 chanx_right_in[12]:28 chanx_left_in[13]:26 0.0001283282 +47 chanx_right_in[12]:29 chanx_left_in[13]:32 7.642603e-06 +48 chanx_right_in[12]:29 chanx_left_in[13]:26 0.0001721555 +49 chanx_right_in[12]:29 chanx_left_in[13]:20 0.0001283282 +50 chanx_right_in[12]:28 chanx_left_in[17]:18 0.000241136 +51 chanx_right_in[12]:30 chanx_left_in[17]:17 0.0005344731 +52 chanx_right_in[12]:29 chanx_left_in[17]:18 0.0005344731 +53 chanx_right_in[12]:29 chanx_left_in[17]:17 0.000241136 +54 chanx_right_in[12]:12 mux_tree_tapbuf_size5_5_sram[2]:12 0.0001312189 +55 chanx_right_in[12]:11 mux_tree_tapbuf_size5_5_sram[2]:11 0.0001312189 +56 chanx_right_in[12]:19 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001045976 +57 chanx_right_in[12]:20 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001045976 +58 chanx_right_in[12]:27 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004468747 +59 chanx_right_in[12]:26 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0004468747 +60 chanx_right_in[12]:28 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002589988 +61 chanx_right_in[12]:28 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.682372e-05 +62 chanx_right_in[12]:13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.682372e-05 +63 chanx_right_in[12]:29 mux_left_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002589988 +64 chanx_right_in[12]:10 mem_left_track_33/net_net_98:4 0.0002267299 +65 chanx_right_in[12]:7 mem_left_track_33/net_net_98:3 0.0002536498 +66 chanx_right_in[12]:8 mem_left_track_33/net_net_98:4 0.0002536498 +67 chanx_right_in[12]:9 mem_left_track_33/net_net_98:3 0.0002267299 + +*RES +0 chanx_right_in[12] chanx_right_in[12]:33 0.001391592 +1 chanx_right_in[12]:28 chanx_right_in[12]:27 0.00341 +2 chanx_right_in[12]:28 chanx_right_in[12]:13 0.0003591583 +3 chanx_right_in[12]:27 chanx_right_in[12]:26 0.00686905 +4 chanx_right_in[12]:25 chanx_right_in[12]:24 0.00341 +5 chanx_right_in[12]:25 chanx_right_in[12]:14 0.0001039141 +6 chanx_right_in[12]:26 chanx_right_in[12]:25 0.00341 +7 chanx_right_in[12]:24 chanx_right_in[12]:23 0.0045 +8 chanx_right_in[12]:23 chanx_right_in[12]:22 0.001191964 +9 chanx_right_in[12]:31 chanx_right_in[12]:30 0.00341 +10 chanx_right_in[12]:30 chanx_right_in[12]:29 0.005137492 +11 chanx_right_in[12]:32 chanx_right_in[12]:31 0.00171875 +12 chanx_right_in[12]:33 chanx_right_in[12]:32 0.00341 +13 chanx_right_in[12]:21 mux_bottom_track_15\/mux_l1_in_0_:A1 0.152 +14 chanx_right_in[12]:21 chanx_right_in[12]:20 0.0002834821 +15 chanx_right_in[12]:19 chanx_right_in[12]:18 0.0045 +16 chanx_right_in[12]:18 chanx_right_in[12]:17 0.002044643 +17 chanx_right_in[12]:16 chanx_right_in[12]:15 9.51087e-05 +18 chanx_right_in[12]:17 chanx_right_in[12]:16 0.0045 +19 chanx_right_in[12]:15 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +20 chanx_right_in[12]:12 chanx_right_in[12]:11 0.004158482 +21 chanx_right_in[12]:13 chanx_right_in[12]:12 0.00341 +22 chanx_right_in[12]:10 chanx_right_in[12]:9 0.005299108 +23 chanx_right_in[12]:11 chanx_right_in[12]:10 0.0045 +24 chanx_right_in[12]:7 chanx_right_in[12]:6 0.0045 +25 chanx_right_in[12]:6 chanx_right_in[12]:5 0.004169643 +26 chanx_right_in[12]:4 BUFT_P_129:A 0.152 +27 chanx_right_in[12]:5 chanx_right_in[12]:4 0.0045 +28 chanx_right_in[12]:8 chanx_right_in[12]:7 0.02295982 +29 chanx_right_in[12]:9 chanx_right_in[12]:8 0.0006071429 +30 chanx_right_in[12]:22 chanx_right_in[12]:21 1.116072e-05 +31 chanx_right_in[12]:20 chanx_right_in[12]:19 0.009816965 +32 chanx_right_in[12]:29 chanx_right_in[12]:28 0.007833333 + +*END + +*D_NET chany_bottom_in[17] 0.01326658 //LENGTH 107.250 LUMPCC 0.001772145 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 69.920 1.290 +*I mux_left_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 43.145 77.860 +*I mux_right_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 70.555 55.080 +*N chany_bottom_in[17]:3 *C 70.517 55.080 +*N chany_bottom_in[17]:4 *C 43.183 77.860 +*N chany_bottom_in[17]:5 *C 44.115 77.860 +*N chany_bottom_in[17]:6 *C 44.160 77.815 +*N chany_bottom_in[17]:7 *C 44.160 68.737 +*N chany_bottom_in[17]:8 *C 44.168 68.680 +*N chany_bottom_in[17]:9 *C 67.153 68.680 +*N chany_bottom_in[17]:10 *C 67.160 68.623 +*N chany_bottom_in[17]:11 *C 67.160 55.125 +*N chany_bottom_in[17]:12 *C 67.205 55.080 +*N chany_bottom_in[17]:13 *C 69.000 55.080 +*N chany_bottom_in[17]:14 *C 69.000 55.035 +*N chany_bottom_in[17]:15 *C 69.000 49.980 +*N chany_bottom_in[17]:16 *C 69.460 49.980 +*N chany_bottom_in[17]:17 *C 69.460 17.000 +*N chany_bottom_in[17]:18 *C 69.920 17.000 + +*CAP +0 chany_bottom_in[17] 0.0009074658 +1 mux_left_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_4\/mux_l1_in_1_:A0 1e-06 +3 chany_bottom_in[17]:3 0.0001133727 +4 chany_bottom_in[17]:4 0.0001228153 +5 chany_bottom_in[17]:5 0.0001228153 +6 chany_bottom_in[17]:6 0.0004046512 +7 chany_bottom_in[17]:7 0.0004046512 +8 chany_bottom_in[17]:8 0.001443605 +9 chany_bottom_in[17]:9 0.001443605 +10 chany_bottom_in[17]:10 0.0005369396 +11 chany_bottom_in[17]:11 0.0005369396 +12 chany_bottom_in[17]:12 0.000132975 +13 chany_bottom_in[17]:13 0.0002791247 +14 chany_bottom_in[17]:14 0.00028771 +15 chany_bottom_in[17]:15 0.0003182805 +16 chany_bottom_in[17]:16 0.001749257 +17 chany_bottom_in[17]:17 0.001749724 +18 chany_bottom_in[17]:18 0.0009385025 +19 chany_bottom_in[17] prog_clk[0]:213 1.234246e-06 +20 chany_bottom_in[17] prog_clk[0]:216 8.201786e-08 +21 chany_bottom_in[17] prog_clk[0]:217 2.57003e-08 +22 chany_bottom_in[17]:11 prog_clk[0]:389 1.027748e-05 +23 chany_bottom_in[17]:11 prog_clk[0]:400 3.535303e-06 +24 chany_bottom_in[17]:10 prog_clk[0]:394 1.027748e-05 +25 chany_bottom_in[17]:10 prog_clk[0]:397 3.535303e-06 +26 chany_bottom_in[17]:9 prog_clk[0]:394 5.346314e-05 +27 chany_bottom_in[17]:7 prog_clk[0]:437 4.843505e-06 +28 chany_bottom_in[17]:7 prog_clk[0]:441 6.591078e-05 +29 chany_bottom_in[17]:7 prog_clk[0]:442 4.237429e-05 +30 chany_bottom_in[17]:8 prog_clk[0]:395 5.346314e-05 +31 chany_bottom_in[17]:6 prog_clk[0]:428 4.843505e-06 +32 chany_bottom_in[17]:6 prog_clk[0]:437 6.591078e-05 +33 chany_bottom_in[17]:6 prog_clk[0]:441 4.237429e-05 +34 chany_bottom_in[17]:16 prog_clk[0]:275 2.7536e-06 +35 chany_bottom_in[17]:16 prog_clk[0]:279 1.840955e-07 +36 chany_bottom_in[17]:16 prog_clk[0]:280 2.093199e-06 +37 chany_bottom_in[17]:16 prog_clk[0]:284 0.0001528467 +38 chany_bottom_in[17]:16 prog_clk[0]:287 8.861479e-05 +39 chany_bottom_in[17]:16 prog_clk[0]:290 3.144163e-05 +40 chany_bottom_in[17]:17 prog_clk[0]:278 1.840955e-07 +41 chany_bottom_in[17]:17 prog_clk[0]:279 2.7536e-06 +42 chany_bottom_in[17]:17 prog_clk[0]:281 2.093199e-06 +43 chany_bottom_in[17]:17 prog_clk[0]:287 0.0001528467 +44 chany_bottom_in[17]:17 prog_clk[0]:290 8.861479e-05 +45 chany_bottom_in[17]:17 prog_clk[0]:291 3.144163e-05 +46 chany_bottom_in[17]:18 prog_clk[0]:211 1.234246e-06 +47 chany_bottom_in[17]:18 prog_clk[0]:213 8.201786e-08 +48 chany_bottom_in[17]:18 prog_clk[0]:216 2.57003e-08 +49 chany_bottom_in[17]:14 chany_bottom_in[11]:8 5.360953e-06 +50 chany_bottom_in[17]:11 chany_bottom_in[11]:8 0.0001118921 +51 chany_bottom_in[17]:11 chany_bottom_in[11]:9 0.000244857 +52 chany_bottom_in[17]:10 chany_bottom_in[11]:5 0.0001118921 +53 chany_bottom_in[17]:10 chany_bottom_in[11]:8 0.000244857 +54 chany_bottom_in[17]:15 chany_bottom_in[11]:9 5.360953e-06 +55 chany_bottom_in[17]:16 chany_bottom_in[11]:12 6.014337e-06 +56 chany_bottom_in[17]:17 chany_bottom_in[11]:13 6.014337e-06 +57 chany_bottom_in[17] ropt_net_208:5 5.826748e-05 +58 chany_bottom_in[17]:18 ropt_net_208:6 5.826748e-05 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:18 0.01402679 +1 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.001602679 +2 chany_bottom_in[17]:13 chany_bottom_in[17]:3 0.001354911 +3 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.0045 +4 chany_bottom_in[17]:3 mux_right_track_4\/mux_l1_in_1_:A0 0.152 +5 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.0045 +6 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.01205134 +7 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.00341 +8 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.003600983 +9 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.008104911 +10 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.00341 +11 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.0008325893 +12 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.0045 +13 chany_bottom_in[17]:4 mux_left_track_17\/mux_l2_in_1_:A1 0.152 +14 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.004513393 +15 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.0004107143 +16 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.02944643 +17 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.0004107143 + +*END + +*D_NET chanx_right_out[1] 0.002487771 //LENGTH 20.765 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 126.560 53.380 +*P chanx_right_out[1] O *L 0.7423 *C 140.450 47.600 +*N chanx_right_out[1]:2 *C 133.407 47.600 +*N chanx_right_out[1]:3 *C 133.400 47.657 +*N chanx_right_out[1]:4 *C 133.400 52.995 +*N chanx_right_out[1]:5 *C 133.355 53.040 +*N chanx_right_out[1]:6 *C 126.960 53.040 +*N chanx_right_out[1]:7 *C 126.960 53.380 +*N chanx_right_out[1]:8 *C 126.598 53.380 + +*CAP +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[1] 0.0005513328 +2 chanx_right_out[1]:2 0.0005513328 +3 chanx_right_out[1]:3 0.0002818414 +4 chanx_right_out[1]:4 0.0002818414 +5 chanx_right_out[1]:5 0.0003455474 +6 chanx_right_out[1]:6 0.0003692755 +7 chanx_right_out[1]:7 6.466372e-05 +8 chanx_right_out[1]:8 4.093566e-05 + +*RES +0 mux_right_track_2\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[1]:8 0.152 +1 chanx_right_out[1]:8 chanx_right_out[1]:7 0.0003236607 +2 chanx_right_out[1]:5 chanx_right_out[1]:4 0.0045 +3 chanx_right_out[1]:4 chanx_right_out[1]:3 0.004765625 +4 chanx_right_out[1]:3 chanx_right_out[1]:2 0.00341 +5 chanx_right_out[1]:2 chanx_right_out[1] 0.001103325 +6 chanx_right_out[1]:7 chanx_right_out[1]:6 0.0003035715 +7 chanx_right_out[1]:6 chanx_right_out[1]:5 0.005709821 + +*END + +*D_NET chany_bottom_out[4] 0.0003541672 //LENGTH 2.560 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/BUFT_P_135:X O *L 0 *C 96.335 3.400 +*P chany_bottom_out[4] O *L 0.7423 *C 96.600 1.290 +*N chany_bottom_out[4]:2 *C 96.600 3.355 +*N chany_bottom_out[4]:3 *C 96.600 3.400 +*N chany_bottom_out[4]:4 *C 96.335 3.400 + +*CAP +0 mux_bottom_track_9\/BUFT_P_135:X 1e-06 +1 chany_bottom_out[4] 0.0001188707 +2 chany_bottom_out[4]:2 0.0001188707 +3 chany_bottom_out[4]:3 5.872544e-05 +4 chany_bottom_out[4]:4 5.670029e-05 + +*RES +0 mux_bottom_track_9\/BUFT_P_135:X chany_bottom_out[4]:4 0.152 +1 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.0001440218 +2 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +3 chany_bottom_out[4]:2 chany_bottom_out[4] 0.00184375 + +*END + +*D_NET chany_bottom_out[14] 0.0007139524 //LENGTH 6.760 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 100.685 4.420 +*P chany_bottom_out[14] O *L 0.7423 *C 97.520 1.290 +*N chany_bottom_out[14]:2 *C 97.520 4.375 +*N chany_bottom_out[14]:3 *C 97.565 4.420 +*N chany_bottom_out[14]:4 *C 100.648 4.420 + +*CAP +0 mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[14] 0.0001708377 +2 chany_bottom_out[14]:2 0.0001708377 +3 chany_bottom_out[14]:3 0.0001856385 +4 chany_bottom_out[14]:4 0.0001856385 + +*RES +0 mux_bottom_track_29\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[14]:4 0.152 +1 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.002752232 +2 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.0045 +3 chany_bottom_out[14]:2 chany_bottom_out[14] 0.002754464 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.002545668 //LENGTH 19.875 LUMPCC 0.0001438304 DR + +*CONN +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 98.745 11.900 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 92.635 6.460 +*I mux_bottom_track_27\/mux_l1_in_0_:S I *L 0.00357 *C 89.340 9.180 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 89.303 9.180 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 87.960 9.180 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 87.960 8.840 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 92.635 6.460 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 92.920 6.460 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 92.920 6.505 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 92.920 8.795 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 92.920 8.870 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 92.920 9.180 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 98.395 9.180 +*N mux_tree_tapbuf_size2_0_sram[0]:13 *C 98.440 9.225 +*N mux_tree_tapbuf_size2_0_sram[0]:14 *C 98.440 11.855 +*N mux_tree_tapbuf_size2_0_sram[0]:15 *C 98.440 11.900 +*N mux_tree_tapbuf_size2_0_sram[0]:16 *C 98.745 11.900 + +*CAP +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_27\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 0.0001225629 +4 mux_tree_tapbuf_size2_0_sram[0]:4 0.0001521407 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.0003342722 +6 mux_tree_tapbuf_size2_0_sram[0]:6 5.751663e-05 +7 mux_tree_tapbuf_size2_0_sram[0]:7 5.968218e-05 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0001261502 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0001261502 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0003346199 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.0003625127 +12 mux_tree_tapbuf_size2_0_sram[0]:12 0.0003325873 +13 mux_tree_tapbuf_size2_0_sram[0]:13 0.0001502456 +14 mux_tree_tapbuf_size2_0_sram[0]:14 0.0001502456 +15 mux_tree_tapbuf_size2_0_sram[0]:15 4.585937e-05 +16 mux_tree_tapbuf_size2_0_sram[0]:16 4.429194e-05 +17 mux_tree_tapbuf_size2_0_sram[0]:10 mux_bottom_track_9/BUF_net_72:5 1.673402e-07 +18 mux_tree_tapbuf_size2_0_sram[0]:9 mux_bottom_track_9/BUF_net_72:4 7.174787e-05 +19 mux_tree_tapbuf_size2_0_sram[0]:8 mux_bottom_track_9/BUF_net_72:3 7.174787e-05 +20 mux_tree_tapbuf_size2_0_sram[0]:5 mux_bottom_track_9/BUF_net_72:6 1.673402e-07 + +*RES +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:16 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:3 mux_bottom_track_27\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0045 +3 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:5 0.004428572 +4 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.002044643 +5 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.0001548913 +6 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.0045 +7 mux_tree_tapbuf_size2_0_sram[0]:6 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.004888393 +9 mux_tree_tapbuf_size2_0_sram[0]:13 mux_tree_tapbuf_size2_0_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size2_0_sram[0]:15 mux_tree_tapbuf_size2_0_sram[0]:14 0.0045 +11 mux_tree_tapbuf_size2_0_sram[0]:14 mux_tree_tapbuf_size2_0_sram[0]:13 0.002348214 +12 mux_tree_tapbuf_size2_0_sram[0]:16 mux_tree_tapbuf_size2_0_sram[0]:15 0.0001005435 +13 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0003035714 +14 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 0.001198661 +15 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.0008882515 //LENGTH 7.090 LUMPCC 0.0001557736 DR + +*CONN +*I mem_bottom_track_27\/FTB_28__53:X O *L 0 *C 106.035 7.140 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 102.295 9.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 102.295 9.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 102.580 9.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 102.580 9.815 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 102.580 7.185 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 102.625 7.140 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 105.998 7.140 + +*CAP +0 mem_bottom_track_27\/FTB_28__53:X 1e-06 +1 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 4.485867e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 4.893884e-05 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0001020658 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001020658 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0002162744 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0002162744 +8 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.788678e-05 +9 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.788678e-05 + +*RES +0 mem_bottom_track_27\/FTB_28__53:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.003011161 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[0] 0.003113104 //LENGTH 23.235 LUMPCC 6.835646e-05 DR + +*CONN +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 57.345 33.660 +*I mux_bottom_track_15\/mux_l1_in_1_:S I *L 0.00357 *C 55.760 31.280 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 44.335 26.180 +*I mux_bottom_track_15\/mux_l1_in_0_:S I *L 0.00357 *C 50.960 28.855 +*N mux_tree_tapbuf_size3_2_sram[0]:4 *C 50.960 28.855 +*N mux_tree_tapbuf_size3_2_sram[0]:5 *C 50.903 28.560 +*N mux_tree_tapbuf_size3_2_sram[0]:6 *C 44.335 26.180 +*N mux_tree_tapbuf_size3_2_sram[0]:7 *C 44.160 26.180 +*N mux_tree_tapbuf_size3_2_sram[0]:8 *C 44.160 26.225 +*N mux_tree_tapbuf_size3_2_sram[0]:9 *C 44.160 28.515 +*N mux_tree_tapbuf_size3_2_sram[0]:10 *C 44.205 28.560 +*N mux_tree_tapbuf_size3_2_sram[0]:11 *C 51.003 28.590 +*N mux_tree_tapbuf_size3_2_sram[0]:12 *C 51.060 28.605 +*N mux_tree_tapbuf_size3_2_sram[0]:13 *C 51.060 30.895 +*N mux_tree_tapbuf_size3_2_sram[0]:14 *C 51.105 30.940 +*N mux_tree_tapbuf_size3_2_sram[0]:15 *C 55.660 30.940 +*N mux_tree_tapbuf_size3_2_sram[0]:16 *C 55.660 31.280 +*N mux_tree_tapbuf_size3_2_sram[0]:17 *C 55.660 31.325 +*N mux_tree_tapbuf_size3_2_sram[0]:18 *C 55.660 33.615 +*N mux_tree_tapbuf_size3_2_sram[0]:19 *C 55.705 33.660 +*N mux_tree_tapbuf_size3_2_sram[0]:20 *C 57.308 33.660 + +*CAP +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_15\/mux_l1_in_1_:S 1e-06 +2 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_15\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_2_sram[0]:4 5.550669e-05 +5 mux_tree_tapbuf_size3_2_sram[0]:5 2.045258e-05 +6 mux_tree_tapbuf_size3_2_sram[0]:6 4.890898e-05 +7 mux_tree_tapbuf_size3_2_sram[0]:7 5.304982e-05 +8 mux_tree_tapbuf_size3_2_sram[0]:8 0.0001433032 +9 mux_tree_tapbuf_size3_2_sram[0]:9 0.0001433032 +10 mux_tree_tapbuf_size3_2_sram[0]:10 0.0004613094 +11 mux_tree_tapbuf_size3_2_sram[0]:11 0.0005068721 +12 mux_tree_tapbuf_size3_2_sram[0]:12 0.0001535616 +13 mux_tree_tapbuf_size3_2_sram[0]:13 0.0001535616 +14 mux_tree_tapbuf_size3_2_sram[0]:14 0.0003281791 +15 mux_tree_tapbuf_size3_2_sram[0]:15 0.0003598968 +16 mux_tree_tapbuf_size3_2_sram[0]:16 6.912918e-05 +17 mux_tree_tapbuf_size3_2_sram[0]:17 0.0001557655 +18 mux_tree_tapbuf_size3_2_sram[0]:18 0.0001557655 +19 mux_tree_tapbuf_size3_2_sram[0]:19 0.0001160907 +20 mux_tree_tapbuf_size3_2_sram[0]:20 0.0001160907 +21 mux_tree_tapbuf_size3_2_sram[0]:14 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.417823e-05 +22 mux_tree_tapbuf_size3_2_sram[0]:15 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.417823e-05 + +*RES +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_2_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:10 0.006069197 +2 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:5 8.928572e-05 +3 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:4 0.0001142241 +4 mux_tree_tapbuf_size3_2_sram[0]:12 mux_tree_tapbuf_size3_2_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size3_2_sram[0]:14 mux_tree_tapbuf_size3_2_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:12 0.002044643 +7 mux_tree_tapbuf_size3_2_sram[0]:10 mux_tree_tapbuf_size3_2_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size3_2_sram[0]:9 mux_tree_tapbuf_size3_2_sram[0]:8 0.002044643 +9 mux_tree_tapbuf_size3_2_sram[0]:7 mux_tree_tapbuf_size3_2_sram[0]:6 9.51087e-05 +10 mux_tree_tapbuf_size3_2_sram[0]:8 mux_tree_tapbuf_size3_2_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size3_2_sram[0]:6 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size3_2_sram[0]:16 mux_bottom_track_15\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_2_sram[0]:16 mux_tree_tapbuf_size3_2_sram[0]:15 0.0003035715 +14 mux_tree_tapbuf_size3_2_sram[0]:4 mux_bottom_track_15\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size3_2_sram[0]:17 mux_tree_tapbuf_size3_2_sram[0]:16 0.0045 +16 mux_tree_tapbuf_size3_2_sram[0]:19 mux_tree_tapbuf_size3_2_sram[0]:18 0.0045 +17 mux_tree_tapbuf_size3_2_sram[0]:18 mux_tree_tapbuf_size3_2_sram[0]:17 0.002044643 +18 mux_tree_tapbuf_size3_2_sram[0]:20 mux_tree_tapbuf_size3_2_sram[0]:19 0.001430804 +19 mux_tree_tapbuf_size3_2_sram[0]:15 mux_tree_tapbuf_size3_2_sram[0]:14 0.004066964 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_1_ccff_tail[0] 0.000545399 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_11\/FTB_25__50:X O *L 0 *C 39.785 58.140 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 39.735 55.420 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 *C 39.735 55.420 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 *C 39.560 55.420 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 *C 39.560 55.465 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 *C 39.560 58.095 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 *C 39.560 58.140 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 *C 39.785 58.140 + +*CAP +0 mem_bottom_track_11\/FTB_25__50:X 1e-06 +1 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 6.034436e-05 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 6.128122e-05 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.0001577673 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0001577673 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 5.353081e-05 +7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 5.270803e-05 + +*RES +0 mem_bottom_track_11\/FTB_25__50:X mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[1] 0.002310634 //LENGTH 18.350 LUMPCC 0.0001660961 DR + +*CONN +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 103.345 42.160 +*I mux_right_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 105.700 47.260 +*I mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 108.735 44.540 +*I mux_right_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 112.140 42.160 +*N mux_tree_tapbuf_size5_2_sram[1]:4 *C 112.103 42.160 +*N mux_tree_tapbuf_size5_2_sram[1]:5 *C 108.698 44.540 +*N mux_tree_tapbuf_size5_2_sram[1]:6 *C 108.145 44.540 +*N mux_tree_tapbuf_size5_2_sram[1]:7 *C 108.100 44.540 +*N mux_tree_tapbuf_size5_2_sram[1]:8 *C 105.738 47.260 +*N mux_tree_tapbuf_size5_2_sram[1]:9 *C 107.595 47.260 +*N mux_tree_tapbuf_size5_2_sram[1]:10 *C 107.640 47.215 +*N mux_tree_tapbuf_size5_2_sram[1]:11 *C 107.640 44.540 +*N mux_tree_tapbuf_size5_2_sram[1]:12 *C 107.640 42.205 +*N mux_tree_tapbuf_size5_2_sram[1]:13 *C 107.640 42.160 +*N mux_tree_tapbuf_size5_2_sram[1]:14 *C 103.383 42.160 + +*CAP +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_right_track_24\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_2_sram[1]:4 0.0002744389 +5 mux_tree_tapbuf_size5_2_sram[1]:5 7.522965e-05 +6 mux_tree_tapbuf_size5_2_sram[1]:6 7.522965e-05 +7 mux_tree_tapbuf_size5_2_sram[1]:7 6.763556e-05 +8 mux_tree_tapbuf_size5_2_sram[1]:8 9.994899e-05 +9 mux_tree_tapbuf_size5_2_sram[1]:9 9.994899e-05 +10 mux_tree_tapbuf_size5_2_sram[1]:10 0.000163287 +11 mux_tree_tapbuf_size5_2_sram[1]:11 0.0003360562 +12 mux_tree_tapbuf_size5_2_sram[1]:12 0.0001381008 +13 mux_tree_tapbuf_size5_2_sram[1]:13 0.000557751 +14 mux_tree_tapbuf_size5_2_sram[1]:14 0.0002529111 +15 mux_tree_tapbuf_size5_2_sram[1]:8 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 8.304807e-05 +16 mux_tree_tapbuf_size5_2_sram[1]:9 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 8.304807e-05 + +*RES +0 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_2_sram[1]:14 0.152 +1 mux_tree_tapbuf_size5_2_sram[1]:8 mux_right_track_24\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_2_sram[1]:9 mux_tree_tapbuf_size5_2_sram[1]:8 0.001658482 +3 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[1]:9 0.0045 +4 mux_tree_tapbuf_size5_2_sram[1]:5 mem_right_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +5 mux_tree_tapbuf_size5_2_sram[1]:6 mux_tree_tapbuf_size5_2_sram[1]:5 0.0004933036 +6 mux_tree_tapbuf_size5_2_sram[1]:7 mux_tree_tapbuf_size5_2_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[1]:12 0.0045 +8 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[1]:4 0.003984375 +9 mux_tree_tapbuf_size5_2_sram[1]:12 mux_tree_tapbuf_size5_2_sram[1]:11 0.002084821 +10 mux_tree_tapbuf_size5_2_sram[1]:4 mux_right_track_24\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size5_2_sram[1]:14 mux_tree_tapbuf_size5_2_sram[1]:13 0.00380134 +12 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[1]:10 0.002388393 +13 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[1]:7 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_5_ccff_tail[0] 0.0004792094 //LENGTH 2.940 LUMPCC 0 DR + +*CONN +*I mem_left_track_17\/FTB_11__36:X O *L 0 *C 43.925 82.620 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 44.335 80.580 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:2 *C 44.335 80.580 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:3 *C 44.160 80.580 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:4 *C 44.160 80.625 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:5 *C 44.160 82.575 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:6 *C 44.160 82.620 +*N mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:7 *C 43.925 82.620 + +*CAP +0 mem_left_track_17\/FTB_11__36:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:2 5.151944e-05 +3 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:3 5.570573e-05 +4 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:4 0.0001228197 +5 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:5 0.0001228197 +6 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:6 6.203121e-05 +7 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:7 6.231365e-05 + +*RES +0 mem_left_track_17\/FTB_11__36:X mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_5_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[2] 0.001519519 //LENGTH 12.015 LUMPCC 0.0003529385 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 114.845 50.320 +*I mux_right_track_8\/mux_l3_in_0_:S I *L 0.008363 *C 114.540 55.875 +*I mem_right_track_8\/FTB_3__28:A I *L 0.001746 *C 116.840 47.600 +*N mux_tree_tapbuf_size6_2_sram[2]:3 *C 116.803 47.600 +*N mux_tree_tapbuf_size6_2_sram[2]:4 *C 115.965 47.600 +*N mux_tree_tapbuf_size6_2_sram[2]:5 *C 115.920 47.645 +*N mux_tree_tapbuf_size6_2_sram[2]:6 *C 115.920 50.275 +*N mux_tree_tapbuf_size6_2_sram[2]:7 *C 115.875 50.320 +*N mux_tree_tapbuf_size6_2_sram[2]:8 *C 114.540 55.760 +*N mux_tree_tapbuf_size6_2_sram[2]:9 *C 114.540 55.715 +*N mux_tree_tapbuf_size6_2_sram[2]:10 *C 114.540 50.365 +*N mux_tree_tapbuf_size6_2_sram[2]:11 *C 114.540 50.320 +*N mux_tree_tapbuf_size6_2_sram[2]:12 *C 114.883 50.320 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:S 4.046798e-05 +2 mem_right_track_8\/FTB_3__28:A 1e-06 +3 mux_tree_tapbuf_size6_2_sram[2]:3 6.677517e-05 +4 mux_tree_tapbuf_size6_2_sram[2]:4 6.677517e-05 +5 mux_tree_tapbuf_size6_2_sram[2]:5 0.0001482464 +6 mux_tree_tapbuf_size6_2_sram[2]:6 0.0001482464 +7 mux_tree_tapbuf_size6_2_sram[2]:7 8.59262e-05 +8 mux_tree_tapbuf_size6_2_sram[2]:8 4.046798e-05 +9 mux_tree_tapbuf_size6_2_sram[2]:9 0.0002038944 +10 mux_tree_tapbuf_size6_2_sram[2]:10 0.0002038944 +11 mux_tree_tapbuf_size6_2_sram[2]:11 5.350549e-05 +12 mux_tree_tapbuf_size6_2_sram[2]:12 0.000106381 +13 mux_tree_tapbuf_size6_2_sram[2]:10 chanx_left_in[6]:18 0.0001541875 +14 mux_tree_tapbuf_size6_2_sram[2]:9 chanx_left_in[6]:17 0.0001541875 +15 mux_tree_tapbuf_size6_2_sram[2]:6 chanx_left_in[6]:17 2.228173e-05 +16 mux_tree_tapbuf_size6_2_sram[2]:5 chanx_left_in[6]:18 2.228173e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_2_sram[2]:12 0.152 +1 mux_tree_tapbuf_size6_2_sram[2]:11 mux_tree_tapbuf_size6_2_sram[2]:10 0.0045 +2 mux_tree_tapbuf_size6_2_sram[2]:10 mux_tree_tapbuf_size6_2_sram[2]:9 0.004776786 +3 mux_tree_tapbuf_size6_2_sram[2]:8 mux_right_track_8\/mux_l3_in_0_:S 7.692308e-05 +4 mux_tree_tapbuf_size6_2_sram[2]:9 mux_tree_tapbuf_size6_2_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size6_2_sram[2]:7 mux_tree_tapbuf_size6_2_sram[2]:6 0.0045 +6 mux_tree_tapbuf_size6_2_sram[2]:6 mux_tree_tapbuf_size6_2_sram[2]:5 0.002348214 +7 mux_tree_tapbuf_size6_2_sram[2]:4 mux_tree_tapbuf_size6_2_sram[2]:3 0.0007477679 +8 mux_tree_tapbuf_size6_2_sram[2]:5 mux_tree_tapbuf_size6_2_sram[2]:4 0.0045 +9 mux_tree_tapbuf_size6_2_sram[2]:3 mem_right_track_8\/FTB_3__28:A 0.152 +10 mux_tree_tapbuf_size6_2_sram[2]:12 mux_tree_tapbuf_size6_2_sram[2]:11 0.0001861413 +11 mux_tree_tapbuf_size6_2_sram[2]:12 mux_tree_tapbuf_size6_2_sram[2]:7 0.0008861608 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[0] 0.007473812 //LENGTH 59.880 LUMPCC 0.0002000316 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 32.045 58.820 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 21.795 47.940 +*I mux_bottom_track_7\/mux_l1_in_2_:S I *L 0.00357 *C 20.240 41.990 +*I mux_bottom_track_7\/mux_l1_in_1_:S I *L 0.00357 *C 23.360 39.735 +*I mux_bottom_track_7\/mux_l1_in_0_:S I *L 0.00357 *C 28.620 44.880 +*I mux_bottom_track_7\/mux_l1_in_3_:S I *L 0.00357 *C 17.840 55.760 +*N mux_tree_tapbuf_size7_3_sram[0]:6 *C 17.878 55.760 +*N mux_tree_tapbuf_size7_3_sram[0]:7 *C 22.035 55.760 +*N mux_tree_tapbuf_size7_3_sram[0]:8 *C 22.080 55.715 +*N mux_tree_tapbuf_size7_3_sram[0]:9 *C 28.520 44.880 +*N mux_tree_tapbuf_size7_3_sram[0]:10 *C 28.520 44.835 +*N mux_tree_tapbuf_size7_3_sram[0]:11 *C 28.520 39.825 +*N mux_tree_tapbuf_size7_3_sram[0]:12 *C 28.475 39.780 +*N mux_tree_tapbuf_size7_3_sram[0]:13 *C 23.360 39.780 +*N mux_tree_tapbuf_size7_3_sram[0]:14 *C 23.360 40.120 +*N mux_tree_tapbuf_size7_3_sram[0]:15 *C 20.285 40.120 +*N mux_tree_tapbuf_size7_3_sram[0]:16 *C 20.240 40.165 +*N mux_tree_tapbuf_size7_3_sram[0]:17 *C 20.240 41.990 +*N mux_tree_tapbuf_size7_3_sram[0]:18 *C 20.240 42.160 +*N mux_tree_tapbuf_size7_3_sram[0]:19 *C 20.240 42.160 +*N mux_tree_tapbuf_size7_3_sram[0]:20 *C 20.240 43.462 +*N mux_tree_tapbuf_size7_3_sram[0]:21 *C 20.248 43.520 +*N mux_tree_tapbuf_size7_3_sram[0]:22 *C 22.073 43.520 +*N mux_tree_tapbuf_size7_3_sram[0]:23 *C 22.080 43.578 +*N mux_tree_tapbuf_size7_3_sram[0]:24 *C 21.818 47.968 +*N mux_tree_tapbuf_size7_3_sram[0]:25 *C 21.818 48.245 +*N mux_tree_tapbuf_size7_3_sram[0]:26 *C 22.050 48.250 +*N mux_tree_tapbuf_size7_3_sram[0]:27 *C 22.080 48.280 +*N mux_tree_tapbuf_size7_3_sram[0]:28 *C 22.080 50.660 +*N mux_tree_tapbuf_size7_3_sram[0]:29 *C 22.125 50.660 +*N mux_tree_tapbuf_size7_3_sram[0]:30 *C 26.635 50.660 +*N mux_tree_tapbuf_size7_3_sram[0]:31 *C 26.680 50.705 +*N mux_tree_tapbuf_size7_3_sram[0]:32 *C 26.680 52.655 +*N mux_tree_tapbuf_size7_3_sram[0]:33 *C 26.725 52.700 +*N mux_tree_tapbuf_size7_3_sram[0]:34 *C 28.935 52.700 +*N mux_tree_tapbuf_size7_3_sram[0]:35 *C 28.980 52.745 +*N mux_tree_tapbuf_size7_3_sram[0]:36 *C 28.980 59.115 +*N mux_tree_tapbuf_size7_3_sram[0]:37 *C 29.025 59.160 +*N mux_tree_tapbuf_size7_3_sram[0]:38 *C 31.740 59.160 +*N mux_tree_tapbuf_size7_3_sram[0]:39 *C 31.740 58.855 +*N mux_tree_tapbuf_size7_3_sram[0]:40 *C 32.017 58.843 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_7\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_track_7\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_7\/mux_l1_in_0_:S 1e-06 +5 mux_bottom_track_7\/mux_l1_in_3_:S 1e-06 +6 mux_tree_tapbuf_size7_3_sram[0]:6 0.0002950219 +7 mux_tree_tapbuf_size7_3_sram[0]:7 0.0002950219 +8 mux_tree_tapbuf_size7_3_sram[0]:8 0.0002725039 +9 mux_tree_tapbuf_size7_3_sram[0]:9 3.611414e-05 +10 mux_tree_tapbuf_size7_3_sram[0]:10 0.0003102855 +11 mux_tree_tapbuf_size7_3_sram[0]:11 0.0003102855 +12 mux_tree_tapbuf_size7_3_sram[0]:12 0.0003505969 +13 mux_tree_tapbuf_size7_3_sram[0]:13 0.0003788512 +14 mux_tree_tapbuf_size7_3_sram[0]:14 0.00026862 +15 mux_tree_tapbuf_size7_3_sram[0]:15 0.0002403657 +16 mux_tree_tapbuf_size7_3_sram[0]:16 0.0001206269 +17 mux_tree_tapbuf_size7_3_sram[0]:17 4.403884e-05 +18 mux_tree_tapbuf_size7_3_sram[0]:18 4.872071e-05 +19 mux_tree_tapbuf_size7_3_sram[0]:19 0.0002397566 +20 mux_tree_tapbuf_size7_3_sram[0]:20 8.520636e-05 +21 mux_tree_tapbuf_size7_3_sram[0]:21 0.0001503625 +22 mux_tree_tapbuf_size7_3_sram[0]:22 0.0001503625 +23 mux_tree_tapbuf_size7_3_sram[0]:23 0.0002703388 +24 mux_tree_tapbuf_size7_3_sram[0]:24 3.338037e-05 +25 mux_tree_tapbuf_size7_3_sram[0]:25 6.969625e-05 +26 mux_tree_tapbuf_size7_3_sram[0]:26 3.631589e-05 +27 mux_tree_tapbuf_size7_3_sram[0]:27 0.0004294321 +28 mux_tree_tapbuf_size7_3_sram[0]:28 0.0004278911 +29 mux_tree_tapbuf_size7_3_sram[0]:29 0.0002726318 +30 mux_tree_tapbuf_size7_3_sram[0]:30 0.0002726318 +31 mux_tree_tapbuf_size7_3_sram[0]:31 0.0001172531 +32 mux_tree_tapbuf_size7_3_sram[0]:32 0.0001172531 +33 mux_tree_tapbuf_size7_3_sram[0]:33 0.0001624614 +34 mux_tree_tapbuf_size7_3_sram[0]:34 0.0001624614 +35 mux_tree_tapbuf_size7_3_sram[0]:35 0.0004487929 +36 mux_tree_tapbuf_size7_3_sram[0]:36 0.0004487929 +37 mux_tree_tapbuf_size7_3_sram[0]:37 0.0001545314 +38 mux_tree_tapbuf_size7_3_sram[0]:38 0.0001774101 +39 mux_tree_tapbuf_size7_3_sram[0]:39 4.632253e-05 +40 mux_tree_tapbuf_size7_3_sram[0]:40 2.344374e-05 +41 mux_tree_tapbuf_size7_3_sram[0]:40 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 1.67579e-05 +42 mux_tree_tapbuf_size7_3_sram[0]:37 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 7.573973e-05 +43 mux_tree_tapbuf_size7_3_sram[0]:37 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 5.917393e-06 +44 mux_tree_tapbuf_size7_3_sram[0]:38 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 5.917393e-06 +45 mux_tree_tapbuf_size7_3_sram[0]:38 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 7.734052e-05 +46 mux_tree_tapbuf_size7_3_sram[0]:39 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 1.835869e-05 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_3_sram[0]:40 0.152 +1 mux_tree_tapbuf_size7_3_sram[0]:17 mux_bottom_track_7\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size7_3_sram[0]:18 mux_tree_tapbuf_size7_3_sram[0]:17 7.327587e-05 +3 mux_tree_tapbuf_size7_3_sram[0]:19 mux_tree_tapbuf_size7_3_sram[0]:18 0.0045 +4 mux_tree_tapbuf_size7_3_sram[0]:19 mux_tree_tapbuf_size7_3_sram[0]:16 0.00178125 +5 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:22 0.00341 +6 mux_tree_tapbuf_size7_3_sram[0]:22 mux_tree_tapbuf_size7_3_sram[0]:21 0.0002859167 +7 mux_tree_tapbuf_size7_3_sram[0]:20 mux_tree_tapbuf_size7_3_sram[0]:19 0.001162947 +8 mux_tree_tapbuf_size7_3_sram[0]:21 mux_tree_tapbuf_size7_3_sram[0]:20 0.00341 +9 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:14 0.002745536 +10 mux_tree_tapbuf_size7_3_sram[0]:16 mux_tree_tapbuf_size7_3_sram[0]:15 0.0045 +11 mux_tree_tapbuf_size7_3_sram[0]:6 mux_bottom_track_7\/mux_l1_in_3_:S 0.152 +12 mux_tree_tapbuf_size7_3_sram[0]:7 mux_tree_tapbuf_size7_3_sram[0]:6 0.003712054 +13 mux_tree_tapbuf_size7_3_sram[0]:8 mux_tree_tapbuf_size7_3_sram[0]:7 0.0045 +14 mux_tree_tapbuf_size7_3_sram[0]:40 mux_tree_tapbuf_size7_3_sram[0]:39 0.0001875 +15 mux_tree_tapbuf_size7_3_sram[0]:37 mux_tree_tapbuf_size7_3_sram[0]:36 0.0045 +16 mux_tree_tapbuf_size7_3_sram[0]:36 mux_tree_tapbuf_size7_3_sram[0]:35 0.0056875 +17 mux_tree_tapbuf_size7_3_sram[0]:34 mux_tree_tapbuf_size7_3_sram[0]:33 0.001973214 +18 mux_tree_tapbuf_size7_3_sram[0]:35 mux_tree_tapbuf_size7_3_sram[0]:34 0.0045 +19 mux_tree_tapbuf_size7_3_sram[0]:33 mux_tree_tapbuf_size7_3_sram[0]:32 0.0045 +20 mux_tree_tapbuf_size7_3_sram[0]:32 mux_tree_tapbuf_size7_3_sram[0]:31 0.001741072 +21 mux_tree_tapbuf_size7_3_sram[0]:30 mux_tree_tapbuf_size7_3_sram[0]:29 0.004026786 +22 mux_tree_tapbuf_size7_3_sram[0]:31 mux_tree_tapbuf_size7_3_sram[0]:30 0.0045 +23 mux_tree_tapbuf_size7_3_sram[0]:29 mux_tree_tapbuf_size7_3_sram[0]:28 0.0045 +24 mux_tree_tapbuf_size7_3_sram[0]:28 mux_tree_tapbuf_size7_3_sram[0]:27 0.002125 +25 mux_tree_tapbuf_size7_3_sram[0]:28 mux_tree_tapbuf_size7_3_sram[0]:8 0.004513393 +26 mux_tree_tapbuf_size7_3_sram[0]:26 mux_tree_tapbuf_size7_3_sram[0]:25 0.0001453125 +27 mux_tree_tapbuf_size7_3_sram[0]:27 mux_tree_tapbuf_size7_3_sram[0]:26 0.0045 +28 mux_tree_tapbuf_size7_3_sram[0]:27 mux_tree_tapbuf_size7_3_sram[0]:23 0.004198661 +29 mux_tree_tapbuf_size7_3_sram[0]:24 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +30 mux_tree_tapbuf_size7_3_sram[0]:13 mux_bottom_track_7\/mux_l1_in_1_:S 0.152 +31 mux_tree_tapbuf_size7_3_sram[0]:13 mux_tree_tapbuf_size7_3_sram[0]:12 0.004566965 +32 mux_tree_tapbuf_size7_3_sram[0]:12 mux_tree_tapbuf_size7_3_sram[0]:11 0.0045 +33 mux_tree_tapbuf_size7_3_sram[0]:11 mux_tree_tapbuf_size7_3_sram[0]:10 0.004473215 +34 mux_tree_tapbuf_size7_3_sram[0]:9 mux_bottom_track_7\/mux_l1_in_0_:S 0.152 +35 mux_tree_tapbuf_size7_3_sram[0]:10 mux_tree_tapbuf_size7_3_sram[0]:9 0.0045 +36 mux_tree_tapbuf_size7_3_sram[0]:14 mux_tree_tapbuf_size7_3_sram[0]:13 0.0003035715 +37 mux_tree_tapbuf_size7_3_sram[0]:25 mux_tree_tapbuf_size7_3_sram[0]:24 0.0001875 +38 mux_tree_tapbuf_size7_3_sram[0]:38 mux_tree_tapbuf_size7_3_sram[0]:37 0.002424107 +39 mux_tree_tapbuf_size7_3_sram[0]:39 mux_tree_tapbuf_size7_3_sram[0]:38 0.0002723214 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001210335 //LENGTH 9.765 LUMPCC 0.0003086589 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 65.605 34.680 +*I mux_left_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 64.400 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 64.400 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 64.400 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 65.275 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 65.320 42.115 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 65.320 34.725 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 65.320 34.680 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 65.605 34.680 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.452222e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.300389e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.608907e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002826451 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002826451 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.917026e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.160011e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[16]:26 9.290515e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_right_in[16]:27 9.290515e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_3_sram[2]:5 6.142429e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_3_sram[2]:6 6.142429e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0007812501 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.006598215 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001548913 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001184199 //LENGTH 8.720 LUMPCC 0.0005647705 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 56.295 88.060 +*I mux_left_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 53.265 83.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 53.303 83.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 54.235 83.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 54.280 83.345 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 54.280 88.015 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 54.325 88.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 56.258 88.060 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.166368e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.166368e-05 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001991918 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001991918 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.785886e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.785886e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[9]:24 4.89778e-05 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[9]:25 4.89778e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_6_sram[1]:9 6.22026e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_6_sram[1]:14 3.574292e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_6_sram[1]:11 5.705128e-05 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_6_sram[1]:12 2.88961e-05 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_6_sram[1]:10 6.22026e-05 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_6_sram[1]:13 3.574292e-05 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size5_6_sram[1]:6 2.88961e-05 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size5_6_sram[1]:12 5.705128e-05 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_6_sram[2]:7 4.89778e-05 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_6_sram[2]:8 4.89778e-05 +20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_6_sram[2]:9 5.367162e-07 +21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_6_sram[2]:10 5.367162e-07 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_25\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008325893 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004169643 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00211098 //LENGTH 15.935 LUMPCC 0.0005824199 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 37.085 30.600 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.040 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.003 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 40.065 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 40.020 20.105 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 40.020 22.383 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 40.013 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 37.267 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 37.260 22.498 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 37.260 30.555 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 37.260 30.600 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 37.085 30.600 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.835424e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.835424e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001395669 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001395669 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001137234 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001137234 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003942417 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003942417 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 6.511861e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 6.96693e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_left_grid_pin_36_[0]:10 6.160402e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 bottom_left_grid_pin_36_[0]:11 6.160402e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_left_grid_pin_40_[0]:12 6.069187e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 bottom_left_grid_pin_40_[0]:23 6.069187e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_0_sram[1]:13 4.876998e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_0_sram[1]:14 4.876998e-05 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_0_sram[1]:15 1.346518e-05 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_0_sram[1]:16 1.346518e-05 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size7_0_sram[1]:15 4.889981e-06 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size7_0_sram[1]:16 2.480479e-05 +22 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size7_0_sram[1]:5 2.480479e-05 +23 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size7_0_sram[1]:16 4.889981e-06 +24 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.698417e-05 +25 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.698417e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002033482 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00043005 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.007194197 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0] 0.008986214 //LENGTH 61.155 LUMPCC 0.002846889 DR + +*CONN +*I mux_bottom_track_7\/mux_l3_in_0_:X O *L 0 *C 24.665 44.200 +*I mux_bottom_track_7\/BUFT_RR_71:A I *L 0.001776 *C 51.520 12.240 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 51.483 12.240 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 48.805 12.240 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 48.760 12.285 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 48.760 20.343 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 48.753 20.400 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 31.300 20.400 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 31.280 20.408 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 31.280 43.513 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 31.260 43.520 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 25.308 43.520 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 25.300 43.578 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 25.300 44.155 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 25.255 44.200 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 24.703 44.200 + +*CAP +0 mux_bottom_track_7\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_7\/BUFT_RR_71:A 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001281312 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001281312 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0004901486 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004901486 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009178603 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0009178603 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0009205827 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0009205827 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0004724211 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0004724211 +12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:12 7.006724e-05 +13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:13 7.006724e-05 +14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:14 6.945162e-05 +15 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:15 6.945162e-05 +16 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_left_grid_pin_34_[0]:28 0.0002323305 +17 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_left_grid_pin_34_[0]:30 0.0004895987 +18 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_left_grid_pin_34_[0]:14 0.0002323305 +19 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_left_grid_pin_34_[0]:29 0.0004895987 +20 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 bottom_left_grid_pin_36_[0]:10 0.0006389648 +21 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 bottom_left_grid_pin_36_[0]:11 0.0006389648 +22 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.255043e-05 +23 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.255043e-05 + +*RES +0 mux_bottom_track_7\/mux_l3_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_7\/BUFT_RR_71:A 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002390625 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.007194197 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002734225 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.003619783 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0009325583 +12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0005156251 +14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0004933036 + +*END + +*D_NET ropt_net_208 0.001046634 //LENGTH 6.775 LUMPCC 0.00026433 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 71.895 6.460 +*I ropt_mt_inst_826:A I *L 0.001767 *C 68.540 4.080 +*N ropt_net_208:2 *C 68.540 4.080 +*N ropt_net_208:3 *C 68.540 4.420 +*N ropt_net_208:4 *C 70.335 4.420 +*N ropt_net_208:5 *C 70.380 4.465 +*N ropt_net_208:6 *C 70.380 6.415 +*N ropt_net_208:7 *C 70.425 6.460 +*N ropt_net_208:8 *C 71.858 6.460 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 ropt_mt_inst_826:A 1e-06 +2 ropt_net_208:2 6.499271e-05 +3 ropt_net_208:3 0.0001368885 +4 ropt_net_208:4 0.0001053471 +5 ropt_net_208:5 0.0001033607 +6 ropt_net_208:6 0.0001033607 +7 ropt_net_208:7 0.0001331772 +8 ropt_net_208:8 0.0001331772 +9 ropt_net_208:5 chany_bottom_in[17] 5.826748e-05 +10 ropt_net_208:6 chany_bottom_in[17]:18 5.826748e-05 +11 ropt_net_208:4 chany_bottom_out[6]:3 7.389754e-05 +12 ropt_net_208:3 chany_bottom_out[6]:4 7.389754e-05 + +*RES +0 ropt_mt_inst_792:X ropt_net_208:8 0.152 +1 ropt_net_208:2 ropt_mt_inst_826:A 0.152 +2 ropt_net_208:4 ropt_net_208:3 0.001602679 +3 ropt_net_208:5 ropt_net_208:4 0.0045 +4 ropt_net_208:7 ropt_net_208:6 0.0045 +5 ropt_net_208:6 ropt_net_208:5 0.001741072 +6 ropt_net_208:8 ropt_net_208:7 0.001279018 +7 ropt_net_208:3 ropt_net_208:2 0.0003035715 + +*END + +*D_NET ropt_net_215 0.0003755089 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 4.140 72.760 +*I ropt_mt_inst_833:A I *L 0.001766 *C 3.220 74.800 +*N ropt_net_215:2 *C 3.258 74.800 +*N ropt_net_215:3 *C 4.095 74.800 +*N ropt_net_215:4 *C 4.140 74.755 +*N ropt_net_215:5 *C 4.140 72.805 +*N ropt_net_215:6 *C 4.140 72.760 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 ropt_mt_inst_833:A 1e-06 +2 ropt_net_215:2 6.191823e-05 +3 ropt_net_215:3 6.191823e-05 +4 ropt_net_215:4 0.0001105947 +5 ropt_net_215:5 0.0001105947 +6 ropt_net_215:6 2.84831e-05 + +*RES +0 ropt_mt_inst_801:X ropt_net_215:6 0.152 +1 ropt_net_215:2 ropt_mt_inst_833:A 0.152 +2 ropt_net_215:3 ropt_net_215:2 0.0007477679 +3 ropt_net_215:4 ropt_net_215:3 0.0045 +4 ropt_net_215:6 ropt_net_215:5 0.0045 +5 ropt_net_215:5 ropt_net_215:4 0.001741072 + +*END + +*D_NET ropt_net_212 0.0009368748 //LENGTH 8.055 LUMPCC 0.0003242407 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 7.045 42.500 +*I ropt_mt_inst_830:A I *L 0.001767 *C 3.220 44.880 +*N ropt_net_212:2 *C 3.183 44.880 +*N ropt_net_212:3 *C 2.805 44.880 +*N ropt_net_212:4 *C 2.760 44.835 +*N ropt_net_212:5 *C 2.760 42.545 +*N ropt_net_212:6 *C 2.805 42.500 +*N ropt_net_212:7 *C 7.008 42.500 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 ropt_mt_inst_830:A 1e-06 +2 ropt_net_212:2 1.934001e-05 +3 ropt_net_212:3 1.934001e-05 +4 ropt_net_212:4 7.124407e-05 +5 ropt_net_212:5 7.124407e-05 +6 ropt_net_212:6 0.000214733 +7 ropt_net_212:7 0.000214733 +8 ropt_net_212:4 chanx_left_in[3]:6 1.334191e-05 +9 ropt_net_212:6 chanx_left_in[3]:4 4.180149e-05 +10 ropt_net_212:5 chanx_left_in[3]:5 1.334191e-05 +11 ropt_net_212:7 chanx_left_in[3]:3 4.180149e-05 +12 ropt_net_212:2 ropt_net_199:6 5.433067e-06 +13 ropt_net_212:3 ropt_net_199:5 5.433067e-06 +14 ropt_net_212:4 ropt_net_199:4 5.361326e-05 +15 ropt_net_212:5 ropt_net_199:3 5.361326e-05 +16 ropt_net_212:2 chanx_left_out[6]:6 2.814833e-05 +17 ropt_net_212:3 chanx_left_out[6]:5 2.814833e-05 +18 ropt_net_212:4 chanx_left_out[6]:4 1.978229e-05 +19 ropt_net_212:5 chanx_left_out[6]:3 1.978229e-05 + +*RES +0 ropt_mt_inst_819:X ropt_net_212:7 0.152 +1 ropt_net_212:2 ropt_mt_inst_830:A 0.152 +2 ropt_net_212:3 ropt_net_212:2 0.0003370536 +3 ropt_net_212:4 ropt_net_212:3 0.0045 +4 ropt_net_212:6 ropt_net_212:5 0.0045 +5 ropt_net_212:5 ropt_net_212:4 0.002044643 +6 ropt_net_212:7 ropt_net_212:6 0.003752233 + +*END + +*D_NET chanx_right_in[13] 0.0285915 //LENGTH 198.292 LUMPCC 0.01209951 DR + +*CONN +*P chanx_right_in[13] I *L 0.29796 *C 140.375 36.720 +*I mux_left_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 77.110 38.760 +*I ropt_mt_inst_801:A I *L 0.001767 *C 3.220 72.080 +*I mux_bottom_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 49.220 20.060 +*N chanx_right_in[13]:4 *C 49.220 20.060 +*N chanx_right_in[13]:5 *C 49.220 20.105 +*N chanx_right_in[13]:6 *C 49.220 24.422 +*N chanx_right_in[13]:7 *C 49.227 24.480 +*N chanx_right_in[13]:8 *C 51.500 24.480 +*N chanx_right_in[13]:9 *C 51.520 24.488 +*N chanx_right_in[13]:10 *C 3.258 72.080 +*N chanx_right_in[13]:11 *C 4.095 72.080 +*N chanx_right_in[13]:12 *C 4.140 72.035 +*N chanx_right_in[13]:13 *C 4.140 56.485 +*N chanx_right_in[13]:14 *C 4.185 56.440 +*N chanx_right_in[13]:15 *C 13.220 56.440 +*N chanx_right_in[13]:16 *C 13.333 56.395 +*N chanx_right_in[13]:17 *C 13.340 55.805 +*N chanx_right_in[13]:18 *C 13.385 55.760 +*N chanx_right_in[13]:19 *C 15.595 55.760 +*N chanx_right_in[13]:20 *C 15.640 55.715 +*N chanx_right_in[13]:21 *C 15.640 54.458 +*N chanx_right_in[13]:22 *C 15.648 54.400 +*N chanx_right_in[13]:23 *C 50.580 54.400 +*N chanx_right_in[13]:24 *C 50.600 54.393 +*N chanx_right_in[13]:25 *C 50.600 38.760 +*N chanx_right_in[13]:26 *C 51.520 38.753 +*N chanx_right_in[13]:27 *C 51.540 38.760 +*N chanx_right_in[13]:28 *C 77.110 38.760 +*N chanx_right_in[13]:29 *C 77.280 38.760 +*N chanx_right_in[13]:30 *C 77.280 38.760 +*N chanx_right_in[13]:31 *C 77.280 38.760 +*N chanx_right_in[13]:32 *C 127.280 38.760 +*N chanx_right_in[13]:33 *C 138.000 38.760 +*N chanx_right_in[13]:34 *C 138.000 36.720 + +*CAP +0 chanx_right_in[13] 0.0002060317 +1 mux_left_track_3\/mux_l1_in_0_:A0 1e-06 +2 ropt_mt_inst_801:A 1e-06 +3 mux_bottom_track_17\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[13]:4 3.309581e-05 +5 chanx_right_in[13]:5 0.0001984717 +6 chanx_right_in[13]:6 0.0001984717 +7 chanx_right_in[13]:7 0.000339431 +8 chanx_right_in[13]:8 0.000339431 +9 chanx_right_in[13]:9 0.0005053713 +10 chanx_right_in[13]:10 6.292042e-05 +11 chanx_right_in[13]:11 6.292042e-05 +12 chanx_right_in[13]:12 0.0008510185 +13 chanx_right_in[13]:13 0.0008510185 +14 chanx_right_in[13]:14 0.0006420109 +15 chanx_right_in[13]:15 0.0006420109 +16 chanx_right_in[13]:16 6.856659e-05 +17 chanx_right_in[13]:17 6.856659e-05 +18 chanx_right_in[13]:18 0.0001975477 +19 chanx_right_in[13]:19 0.0001975477 +20 chanx_right_in[13]:20 9.341967e-05 +21 chanx_right_in[13]:21 9.341967e-05 +22 chanx_right_in[13]:22 0.001135762 +23 chanx_right_in[13]:23 0.001135762 +24 chanx_right_in[13]:24 0.0005544209 +25 chanx_right_in[13]:25 0.000594962 +26 chanx_right_in[13]:26 0.0005459124 +27 chanx_right_in[13]:27 0.0009435129 +28 chanx_right_in[13]:28 5.532252e-05 +29 chanx_right_in[13]:29 6.045727e-05 +30 chanx_right_in[13]:30 3.622381e-05 +31 chanx_right_in[13]:31 0.002737859 +32 chanx_right_in[13]:32 0.002196959 +33 chanx_right_in[13]:33 0.0005185713 +34 chanx_right_in[13]:34 0.0003219903 +35 chanx_right_in[13] chanx_right_in[4] 5.583568e-06 +36 chanx_right_in[13]:27 chanx_right_in[4]:15 0.0004878245 +37 chanx_right_in[13]:27 chanx_right_in[4]:20 8.285849e-06 +38 chanx_right_in[13]:26 chanx_right_in[4]:20 1.533721e-05 +39 chanx_right_in[13]:31 chanx_right_in[4]:20 0.001576298 +40 chanx_right_in[13]:31 chanx_right_in[4]:21 2.008107e-05 +41 chanx_right_in[13]:33 chanx_right_in[4]:22 0.0002462053 +42 chanx_right_in[13]:33 chanx_right_in[4]:23 1.526502e-05 +43 chanx_right_in[13]:34 chanx_right_in[4]:24 1.526502e-05 +44 chanx_right_in[13]:34 chanx_right_in[4]:25 5.583568e-06 +45 chanx_right_in[13]:25 chanx_right_in[4]:15 1.533721e-05 +46 chanx_right_in[13]:32 chanx_right_in[4]:21 0.001334679 +47 chanx_right_in[13]:32 chanx_right_in[4]:22 1.179522e-05 +48 chanx_right_in[13]:9 chanx_right_in[12]:26 0.0001191872 +49 chanx_right_in[13]:24 chanx_right_in[12]:27 0.0003016437 +50 chanx_right_in[13]:26 chanx_right_in[12]:27 0.0001191872 +51 chanx_right_in[13]:25 chanx_right_in[12]:26 0.0003016437 +52 chanx_right_in[13] chanx_right_in[16] 3.946644e-06 +53 chanx_right_in[13]:24 chanx_right_in[16]:18 0.0001302554 +54 chanx_right_in[13]:31 chanx_right_in[16]:37 0.0001136329 +55 chanx_right_in[13]:33 chanx_right_in[16] 5.981366e-06 +56 chanx_right_in[13]:33 chanx_right_in[16]:38 9.446601e-05 +57 chanx_right_in[13]:34 chanx_right_in[16]:39 3.946644e-06 +58 chanx_right_in[13]:25 chanx_right_in[16]:19 0.0001302554 +59 chanx_right_in[13]:32 chanx_right_in[16]:37 9.446601e-05 +60 chanx_right_in[13]:32 chanx_right_in[16]:38 0.0001136329 +61 chanx_right_in[13]:32 chanx_right_in[16]:39 5.981366e-06 +62 chanx_right_in[13]:23 chanx_left_in[14]:27 0.0004392636 +63 chanx_right_in[13]:22 chanx_left_in[14]:28 0.0004392636 +64 chanx_right_in[13]:13 chanx_left_in[14]:35 2.196028e-05 +65 chanx_right_in[13]:12 chanx_left_in[14]:34 2.196028e-05 +66 chanx_right_in[13]:23 chanx_left_in[16]:39 0.0004560622 +67 chanx_right_in[13]:22 chanx_left_in[16]:40 0.0004560622 +68 chanx_right_in[13]:27 chanx_left_in[18]:22 3.248805e-05 +69 chanx_right_in[13]:27 chanx_left_in[18]:21 0.0003913729 +70 chanx_right_in[13]:26 chanx_left_in[18]:21 1.533722e-05 +71 chanx_right_in[13]:31 chanx_left_in[18]:20 0.0003913729 +72 chanx_right_in[13]:31 chanx_left_in[18]:21 0.000579254 +73 chanx_right_in[13]:25 chanx_left_in[18]:22 1.533722e-05 +74 chanx_right_in[13]:32 chanx_left_in[18]:20 0.0005467659 +75 chanx_right_in[13]:23 prog_clk[0]:452 0.0001347655 +76 chanx_right_in[13]:23 prog_clk[0]:446 0.0001618372 +77 chanx_right_in[13]:23 prog_clk[0]:411 9.228301e-05 +78 chanx_right_in[13]:23 prog_clk[0]:406 4.163091e-06 +79 chanx_right_in[13]:23 prog_clk[0]:415 6.689573e-06 +80 chanx_right_in[13]:21 prog_clk[0]:475 4.931049e-07 +81 chanx_right_in[13]:22 prog_clk[0]:452 0.0001618372 +82 chanx_right_in[13]:22 prog_clk[0]:451 0.0001347655 +83 chanx_right_in[13]:22 prog_clk[0]:411 4.163091e-06 +84 chanx_right_in[13]:22 prog_clk[0]:415 9.228301e-05 +85 chanx_right_in[13]:22 prog_clk[0]:416 6.689573e-06 +86 chanx_right_in[13]:20 prog_clk[0]:472 4.931049e-07 +87 chanx_right_in[13]:27 prog_clk[0]:517 0.0003119898 +88 chanx_right_in[13]:26 prog_clk[0]:523 6.251058e-06 +89 chanx_right_in[13]:31 prog_clk[0]:516 0.0003119898 +90 chanx_right_in[13]:25 prog_clk[0]:528 6.251058e-06 +91 chanx_right_in[13]:9 chany_bottom_in[15]:17 0.0002950278 +92 chanx_right_in[13]:24 chany_bottom_in[15]:16 3.551932e-05 +93 chanx_right_in[13]:24 chany_bottom_in[15]:10 3.92178e-05 +94 chanx_right_in[13]:26 chany_bottom_in[15]:16 0.0002950278 +95 chanx_right_in[13]:25 chany_bottom_in[15]:16 3.92178e-05 +96 chanx_right_in[13]:25 chany_bottom_in[15]:17 3.551932e-05 +97 chanx_right_in[13]:23 chanx_left_in[7]:7 0.0002862325 +98 chanx_right_in[13]:22 chanx_left_in[7]:8 0.0002862325 +99 chanx_right_in[13]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001241509 +100 chanx_right_in[13]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001241509 + +*RES +0 chanx_right_in[13] chanx_right_in[13]:34 0.0003720833 +1 chanx_right_in[13]:8 chanx_right_in[13]:7 0.000356025 +2 chanx_right_in[13]:9 chanx_right_in[13]:8 0.00341 +3 chanx_right_in[13]:6 chanx_right_in[13]:5 0.003854911 +4 chanx_right_in[13]:7 chanx_right_in[13]:6 0.00341 +5 chanx_right_in[13]:4 mux_bottom_track_17\/mux_l1_in_0_:A1 0.152 +6 chanx_right_in[13]:5 chanx_right_in[13]:4 0.0045 +7 chanx_right_in[13]:23 chanx_right_in[13]:22 0.005472758 +8 chanx_right_in[13]:24 chanx_right_in[13]:23 0.00341 +9 chanx_right_in[13]:21 chanx_right_in[13]:20 0.001122768 +10 chanx_right_in[13]:22 chanx_right_in[13]:21 0.00341 +11 chanx_right_in[13]:19 chanx_right_in[13]:18 0.001973214 +12 chanx_right_in[13]:20 chanx_right_in[13]:19 0.0045 +13 chanx_right_in[13]:18 chanx_right_in[13]:17 0.0045 +14 chanx_right_in[13]:17 chanx_right_in[13]:16 0.0005267857 +15 chanx_right_in[13]:15 chanx_right_in[13]:14 0.008066965 +16 chanx_right_in[13]:16 chanx_right_in[13]:15 0.0045 +17 chanx_right_in[13]:14 chanx_right_in[13]:13 0.0045 +18 chanx_right_in[13]:13 chanx_right_in[13]:12 0.01388393 +19 chanx_right_in[13]:11 chanx_right_in[13]:10 0.0007477679 +20 chanx_right_in[13]:12 chanx_right_in[13]:11 0.0045 +21 chanx_right_in[13]:10 ropt_mt_inst_801:A 0.152 +22 chanx_right_in[13]:27 chanx_right_in[13]:26 0.00341 +23 chanx_right_in[13]:26 chanx_right_in[13]:25 0.0001441333 +24 chanx_right_in[13]:26 chanx_right_in[13]:9 0.00223485 +25 chanx_right_in[13]:30 chanx_right_in[13]:29 0.0045 +26 chanx_right_in[13]:31 chanx_right_in[13]:30 0.00341 +27 chanx_right_in[13]:31 chanx_right_in[13]:27 0.0040326 +28 chanx_right_in[13]:29 chanx_right_in[13]:28 9.239131e-05 +29 chanx_right_in[13]:28 mux_left_track_3\/mux_l1_in_0_:A0 0.152 +30 chanx_right_in[13]:33 chanx_right_in[13]:32 0.001679467 +31 chanx_right_in[13]:34 chanx_right_in[13]:33 0.0003196 +32 chanx_right_in[13]:25 chanx_right_in[13]:24 0.002449091 +33 chanx_right_in[13]:32 chanx_right_in[13]:31 0.007833333 + +*END + +*D_NET chany_bottom_in[9] 0.009049029 //LENGTH 64.065 LUMPCC 0.003781601 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 84.180 1.290 +*I mux_left_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 81.250 49.640 +*I mux_right_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 84.740 56.100 +*N chany_bottom_in[9]:3 *C 84.703 56.100 +*N chany_bottom_in[9]:4 *C 82.845 56.100 +*N chany_bottom_in[9]:5 *C 82.800 56.055 +*N chany_bottom_in[9]:6 *C 82.800 49.685 +*N chany_bottom_in[9]:7 *C 82.755 49.640 +*N chany_bottom_in[9]:8 *C 81.250 49.640 +*N chany_bottom_in[9]:9 *C 81.465 49.640 +*N chany_bottom_in[9]:10 *C 81.420 49.640 +*N chany_bottom_in[9]:11 *C 81.418 49.640 +*N chany_bottom_in[9]:12 *C 80.975 49.640 +*N chany_bottom_in[9]:13 *C 80.960 49.633 +*N chany_bottom_in[9]:14 *C 80.960 4.088 +*N chany_bottom_in[9]:15 *C 80.980 4.080 +*N chany_bottom_in[9]:16 *C 84.172 4.080 +*N chany_bottom_in[9]:17 *C 84.180 4.022 + +*CAP +0 chany_bottom_in[9] 0.0001854211 +1 mux_left_track_9\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_8\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[9]:3 0.0001693817 +4 chany_bottom_in[9]:4 0.0001693817 +5 chany_bottom_in[9]:5 0.0003615965 +6 chany_bottom_in[9]:6 0.0003615965 +7 chany_bottom_in[9]:7 9.47958e-05 +8 chany_bottom_in[9]:8 4.959753e-05 +9 chany_bottom_in[9]:9 0.0001157115 +10 chany_bottom_in[9]:10 3.323832e-05 +11 chany_bottom_in[9]:11 7.240996e-05 +12 chany_bottom_in[9]:12 7.240996e-05 +13 chany_bottom_in[9]:13 0.001334766 +14 chany_bottom_in[9]:14 0.001334766 +15 chany_bottom_in[9]:15 0.0003624669 +16 chany_bottom_in[9]:16 0.0003624669 +17 chany_bottom_in[9]:17 0.0001854211 +18 chany_bottom_in[9]:13 chanx_right_in[17]:28 0.0003268414 +19 chany_bottom_in[9]:14 chanx_right_in[17]:27 0.0003268414 +20 chany_bottom_in[9] chany_bottom_in[0] 1.818287e-06 +21 chany_bottom_in[9]:13 chany_bottom_in[0]:9 0.0007173944 +22 chany_bottom_in[9]:15 chany_bottom_in[0]:12 1.615054e-06 +23 chany_bottom_in[9]:14 chany_bottom_in[0]:10 0.0007173944 +24 chany_bottom_in[9]:17 chany_bottom_in[0]:13 1.818287e-06 +25 chany_bottom_in[9]:16 chany_bottom_in[0]:11 1.615054e-06 +26 chany_bottom_in[9]:13 chany_bottom_in[12]:16 0.0008431313 +27 chany_bottom_in[9]:14 chany_bottom_in[12]:17 0.0008431313 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:17 0.002439732 +1 chany_bottom_in[9]:8 mux_left_track_9\/mux_l1_in_1_:A0 0.152 +2 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.0045 +3 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.0056875 +4 chany_bottom_in[9]:4 chany_bottom_in[9]:3 0.001658482 +5 chany_bottom_in[9]:5 chany_bottom_in[9]:4 0.0045 +6 chany_bottom_in[9]:3 mux_right_track_8\/mux_l1_in_1_:A1 0.152 +7 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.0001168478 +8 chany_bottom_in[9]:9 chany_bottom_in[9]:7 0.001151786 +9 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.0045 +10 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.00341 +11 chany_bottom_in[9]:12 chany_bottom_in[9]:11 6.499219e-05 +12 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.00341 +13 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.00341 +14 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.007135383 +15 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.00341 +16 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.0005001583 + +*END + +*D_NET bottom_left_grid_pin_38_[0] 0.0121846 //LENGTH 88.930 LUMPCC 0.003838371 DR + +*CONN +*P bottom_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 4.760 +*I mux_bottom_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 35.595 20.740 +*I mux_bottom_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 77.525 22.440 +*I mux_bottom_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 48.935 21.080 +*I mux_bottom_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 34.790 37.060 +*N bottom_left_grid_pin_38_[0]:5 *C 34.828 37.060 +*N bottom_left_grid_pin_38_[0]:6 *C 35.835 37.060 +*N bottom_left_grid_pin_38_[0]:7 *C 35.880 37.015 +*N bottom_left_grid_pin_38_[0]:8 *C 48.898 21.080 +*N bottom_left_grid_pin_38_[0]:9 *C 77.487 22.440 +*N bottom_left_grid_pin_38_[0]:10 *C 70.425 22.440 +*N bottom_left_grid_pin_38_[0]:11 *C 70.380 22.440 +*N bottom_left_grid_pin_38_[0]:12 *C 70.373 22.440 +*N bottom_left_grid_pin_38_[0]:13 *C 45.547 22.440 +*N bottom_left_grid_pin_38_[0]:14 *C 45.540 22.383 +*N bottom_left_grid_pin_38_[0]:15 *C 45.540 21.125 +*N bottom_left_grid_pin_38_[0]:16 *C 45.540 21.080 +*N bottom_left_grid_pin_38_[0]:17 *C 36.340 21.080 +*N bottom_left_grid_pin_38_[0]:18 *C 36.340 20.740 +*N bottom_left_grid_pin_38_[0]:19 *C 35.595 20.740 +*N bottom_left_grid_pin_38_[0]:20 *C 35.925 20.740 +*N bottom_left_grid_pin_38_[0]:21 *C 35.880 20.740 +*N bottom_left_grid_pin_38_[0]:22 *C 35.880 4.817 +*N bottom_left_grid_pin_38_[0]:23 *C 35.873 4.760 + +*CAP +0 bottom_left_grid_pin_38_[0] 0.0002424167 +1 mux_bottom_track_1\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_17\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_5\/mux_l1_in_1_:A0 1e-06 +5 bottom_left_grid_pin_38_[0]:5 9.759703e-05 +6 bottom_left_grid_pin_38_[0]:6 9.759703e-05 +7 bottom_left_grid_pin_38_[0]:7 0.0006122495 +8 bottom_left_grid_pin_38_[0]:8 0.0002334684 +9 bottom_left_grid_pin_38_[0]:9 0.0004165312 +10 bottom_left_grid_pin_38_[0]:10 0.0004165312 +11 bottom_left_grid_pin_38_[0]:11 3.583634e-05 +12 bottom_left_grid_pin_38_[0]:12 0.0009046619 +13 bottom_left_grid_pin_38_[0]:13 0.0009046619 +14 bottom_left_grid_pin_38_[0]:14 9.426988e-05 +15 bottom_left_grid_pin_38_[0]:15 9.426988e-05 +16 bottom_left_grid_pin_38_[0]:16 0.0008115053 +17 bottom_left_grid_pin_38_[0]:17 0.0005698279 +18 bottom_left_grid_pin_38_[0]:18 5.002333e-05 +19 bottom_left_grid_pin_38_[0]:19 3.717985e-05 +20 bottom_left_grid_pin_38_[0]:20 3.617984e-05 +21 bottom_left_grid_pin_38_[0]:21 0.001545229 +22 bottom_left_grid_pin_38_[0]:22 0.000899777 +23 bottom_left_grid_pin_38_[0]:23 0.0002424167 +24 bottom_left_grid_pin_38_[0] bottom_left_grid_pin_36_[0] 0.0001138151 +25 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_36_[0]:22 2.31684e-06 +26 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_36_[0]:23 6.498152e-06 +27 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_36_[0]:12 2.966168e-06 +28 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_36_[0]:16 4.228961e-07 +29 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_36_[0]:20 7.592994e-06 +30 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_36_[0]:21 0.0001750143 +31 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_36_[0]:25 2.886603e-05 +32 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_36_[0]:22 2.280451e-06 +33 bottom_left_grid_pin_38_[0]:22 bottom_left_grid_pin_36_[0]:21 7.592994e-06 +34 bottom_left_grid_pin_38_[0]:22 bottom_left_grid_pin_36_[0]:25 2.966168e-06 +35 bottom_left_grid_pin_38_[0]:22 bottom_left_grid_pin_36_[0]:26 2.657597e-05 +36 bottom_left_grid_pin_38_[0]:23 bottom_left_grid_pin_36_[0]:27 0.0001138151 +37 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_36_[0]:10 0.0005073341 +38 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_36_[0]:11 0.0005073341 +39 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_36_[0]:24 4.827333e-07 +40 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_36_[0]:17 8.266172e-06 +41 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_36_[0]:19 1.723381e-06 +42 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_36_[0]:12 2.290056e-06 +43 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_36_[0]:15 4.228961e-07 +44 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_36_[0]:20 0.0001750143 +45 bottom_left_grid_pin_38_[0]:5 bottom_left_grid_pin_36_[0]:18 1.723381e-06 +46 bottom_left_grid_pin_38_[0]:5 bottom_left_grid_pin_36_[0]:19 8.266172e-06 +47 bottom_left_grid_pin_38_[0]:18 bottom_left_grid_pin_36_[0]:23 2.31684e-06 +48 bottom_left_grid_pin_38_[0]:18 bottom_left_grid_pin_36_[0]:24 4.217701e-06 +49 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_36_[0]:23 4.827333e-07 +50 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_40_[0]:12 0.0005250907 +51 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_40_[0]:23 0.0005250907 +52 bottom_left_grid_pin_38_[0]:20 mux_tree_tapbuf_size7_0_sram[0]:8 2.018109e-05 +53 bottom_left_grid_pin_38_[0]:20 mux_tree_tapbuf_size7_0_sram[0]:7 8.435812e-06 +54 bottom_left_grid_pin_38_[0]:21 mux_tree_tapbuf_size7_0_sram[0]:17 0.0001425471 +55 bottom_left_grid_pin_38_[0]:21 mux_tree_tapbuf_size7_0_sram[0]:19 8.889497e-05 +56 bottom_left_grid_pin_38_[0]:21 mux_tree_tapbuf_size7_0_sram[0]:12 1.031545e-06 +57 bottom_left_grid_pin_38_[0]:21 mux_tree_tapbuf_size7_0_sram[0]:9 3.424731e-06 +58 bottom_left_grid_pin_38_[0]:19 mux_tree_tapbuf_size7_0_sram[0]:8 8.435812e-06 +59 bottom_left_grid_pin_38_[0]:22 mux_tree_tapbuf_size7_0_sram[0]:9 1.031545e-06 +60 bottom_left_grid_pin_38_[0]:16 mux_tree_tapbuf_size7_0_sram[0]:7 5.493457e-07 +61 bottom_left_grid_pin_38_[0]:7 mux_tree_tapbuf_size7_0_sram[0]:20 8.889497e-05 +62 bottom_left_grid_pin_38_[0]:7 mux_tree_tapbuf_size7_0_sram[0]:19 0.0001425471 +63 bottom_left_grid_pin_38_[0]:7 mux_tree_tapbuf_size7_0_sram[0]:12 3.424731e-06 +64 bottom_left_grid_pin_38_[0]:18 mux_tree_tapbuf_size7_0_sram[0]:7 2.018109e-05 +65 bottom_left_grid_pin_38_[0]:17 mux_tree_tapbuf_size7_0_sram[0]:8 5.493457e-07 +66 bottom_left_grid_pin_38_[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001245973 +67 bottom_left_grid_pin_38_[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001245973 +68 bottom_left_grid_pin_38_[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001491344 +69 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001491344 + +*RES +0 bottom_left_grid_pin_38_[0] bottom_left_grid_pin_38_[0]:23 0.0009591916 +1 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_38_[0]:19 0.0001331522 +2 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_38_[0]:18 0.0003705357 +3 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_38_[0]:20 0.0045 +4 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_38_[0]:7 0.01453125 +5 bottom_left_grid_pin_38_[0]:19 mux_bottom_track_1\/mux_l1_in_1_:A0 0.152 +6 bottom_left_grid_pin_38_[0]:8 mux_bottom_track_17\/mux_l1_in_0_:A0 0.152 +7 bottom_left_grid_pin_38_[0]:22 bottom_left_grid_pin_38_[0]:21 0.01421652 +8 bottom_left_grid_pin_38_[0]:23 bottom_left_grid_pin_38_[0]:22 0.00341 +9 bottom_left_grid_pin_38_[0]:9 mux_bottom_track_33\/mux_l1_in_0_:A0 0.152 +10 bottom_left_grid_pin_38_[0]:10 bottom_left_grid_pin_38_[0]:9 0.006305804 +11 bottom_left_grid_pin_38_[0]:11 bottom_left_grid_pin_38_[0]:10 0.0045 +12 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_38_[0]:11 0.00341 +13 bottom_left_grid_pin_38_[0]:14 bottom_left_grid_pin_38_[0]:13 0.00341 +14 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:12 0.00388925 +15 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_38_[0]:15 0.0045 +16 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_38_[0]:8 0.002997768 +17 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_38_[0]:14 0.001122768 +18 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_38_[0]:5 0.0008995536 +19 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_38_[0]:6 0.0045 +20 bottom_left_grid_pin_38_[0]:5 mux_bottom_track_5\/mux_l1_in_1_:A0 0.152 +21 bottom_left_grid_pin_38_[0]:18 bottom_left_grid_pin_38_[0]:17 0.0003035715 +22 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_38_[0]:16 0.008214287 + +*END + +*D_NET chanx_left_out[16] 0.001439733 //LENGTH 13.625 LUMPCC 0 DR + +*CONN +*I mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 9.605 58.820 +*P chanx_left_out[16] O *L 0.7423 *C 1.298 54.400 +*N chanx_left_out[16]:2 *C 1.380 54.400 +*N chanx_left_out[16]:3 *C 1.380 54.458 +*N chanx_left_out[16]:4 *C 1.380 58.775 +*N chanx_left_out[16]:5 *C 1.425 58.820 +*N chanx_left_out[16]:6 *C 9.568 58.820 + +*CAP +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[16] 3.468144e-05 +2 chanx_left_out[16]:2 3.468144e-05 +3 chanx_left_out[16]:3 0.0002329664 +4 chanx_left_out[16]:4 0.0002329664 +5 chanx_left_out[16]:5 0.0004517188 +6 chanx_left_out[16]:6 0.0004517188 + +*RES +0 mux_left_track_33\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:6 chanx_left_out[16]:5 0.007270089 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.003854911 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.00292136 //LENGTH 22.335 LUMPCC 0.0003340264 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 87.245 20.400 +*I mux_bottom_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 76.460 23.120 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 76.985 17.340 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 76.985 17.325 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 76.360 23.120 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 76.360 23.075 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 76.360 17.000 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 76.820 17.000 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 77.008 17.000 +*N mux_tree_tapbuf_size2_3_sram[0]:9 *C 85.975 17.000 +*N mux_tree_tapbuf_size2_3_sram[0]:10 *C 86.020 17.045 +*N mux_tree_tapbuf_size2_3_sram[0]:11 *C 86.020 20.355 +*N mux_tree_tapbuf_size2_3_sram[0]:12 *C 86.065 20.400 +*N mux_tree_tapbuf_size2_3_sram[0]:13 *C 87.208 20.400 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_33\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 4.16583e-05 +4 mux_tree_tapbuf_size2_3_sram[0]:4 3.385313e-05 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0002437725 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.000278181 +7 mux_tree_tapbuf_size2_3_sram[0]:7 6.707705e-05 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.0006541391 +9 mux_tree_tapbuf_size2_3_sram[0]:9 0.0006124808 +10 mux_tree_tapbuf_size2_3_sram[0]:10 0.0002405733 +11 mux_tree_tapbuf_size2_3_sram[0]:11 0.0002405733 +12 mux_tree_tapbuf_size2_3_sram[0]:12 8.601228e-05 +13 mux_tree_tapbuf_size2_3_sram[0]:13 8.601228e-05 +14 mux_tree_tapbuf_size2_3_sram[0]:5 chany_bottom_in[5]:20 0.0001670132 +15 mux_tree_tapbuf_size2_3_sram[0]:6 chany_bottom_in[5] 0.0001670132 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:3 0.0001766304 +3 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.0004107143 +4 mux_tree_tapbuf_size2_3_sram[0]:4 mux_bottom_track_33\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_3_sram[0]:9 mux_tree_tapbuf_size2_3_sram[0]:8 0.008006697 +7 mux_tree_tapbuf_size2_3_sram[0]:10 mux_tree_tapbuf_size2_3_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size2_3_sram[0]:12 mux_tree_tapbuf_size2_3_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_3_sram[0]:11 mux_tree_tapbuf_size2_3_sram[0]:10 0.002955357 +10 mux_tree_tapbuf_size2_3_sram[0]:13 mux_tree_tapbuf_size2_3_sram[0]:12 0.001020089 +11 mux_tree_tapbuf_size2_3_sram[0]:3 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.005424107 + +*END + +*D_NET mux_tree_tapbuf_size3_6_sram[1] 0.001666299 //LENGTH 12.860 LUMPCC 0.000272531 DR + +*CONN +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 94.145 33.660 +*I mux_bottom_track_23\/mux_l2_in_0_:S I *L 0.00357 *C 88.440 36.380 +*I mem_bottom_track_23\/FTB_19__44:A I *L 0.001746 *C 94.300 39.440 +*N mux_tree_tapbuf_size3_6_sram[1]:3 *C 94.263 39.440 +*N mux_tree_tapbuf_size3_6_sram[1]:4 *C 93.885 39.440 +*N mux_tree_tapbuf_size3_6_sram[1]:5 *C 93.840 39.395 +*N mux_tree_tapbuf_size3_6_sram[1]:6 *C 88.478 36.380 +*N mux_tree_tapbuf_size3_6_sram[1]:7 *C 93.795 36.380 +*N mux_tree_tapbuf_size3_6_sram[1]:8 *C 93.840 36.380 +*N mux_tree_tapbuf_size3_6_sram[1]:9 *C 93.840 33.705 +*N mux_tree_tapbuf_size3_6_sram[1]:10 *C 93.840 33.660 +*N mux_tree_tapbuf_size3_6_sram[1]:11 *C 94.145 33.660 + +*CAP +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_23\/FTB_19__44:A 1e-06 +3 mux_tree_tapbuf_size3_6_sram[1]:3 5.767534e-05 +4 mux_tree_tapbuf_size3_6_sram[1]:4 5.767534e-05 +5 mux_tree_tapbuf_size3_6_sram[1]:5 0.0001751142 +6 mux_tree_tapbuf_size3_6_sram[1]:6 0.0002416406 +7 mux_tree_tapbuf_size3_6_sram[1]:7 0.0002416406 +8 mux_tree_tapbuf_size3_6_sram[1]:8 0.0003589154 +9 mux_tree_tapbuf_size3_6_sram[1]:9 0.0001512299 +10 mux_tree_tapbuf_size3_6_sram[1]:10 5.550397e-05 +11 mux_tree_tapbuf_size3_6_sram[1]:11 5.137263e-05 +12 mux_tree_tapbuf_size3_6_sram[1]:6 chanx_left_in[10]:29 4.932648e-06 +13 mux_tree_tapbuf_size3_6_sram[1]:6 chanx_left_in[10]:31 2.434695e-05 +14 mux_tree_tapbuf_size3_6_sram[1]:6 chanx_left_in[10]:33 0.0001069859 +15 mux_tree_tapbuf_size3_6_sram[1]:7 chanx_left_in[10]:28 4.932648e-06 +16 mux_tree_tapbuf_size3_6_sram[1]:7 chanx_left_in[10]:30 2.434695e-05 +17 mux_tree_tapbuf_size3_6_sram[1]:7 chanx_left_in[10]:32 0.0001069859 + +*RES +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_6_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_6_sram[1]:6 mux_bottom_track_23\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_6_sram[1]:7 mux_tree_tapbuf_size3_6_sram[1]:6 0.004747768 +3 mux_tree_tapbuf_size3_6_sram[1]:8 mux_tree_tapbuf_size3_6_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size3_6_sram[1]:8 mux_tree_tapbuf_size3_6_sram[1]:5 0.002691964 +5 mux_tree_tapbuf_size3_6_sram[1]:10 mux_tree_tapbuf_size3_6_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size3_6_sram[1]:9 mux_tree_tapbuf_size3_6_sram[1]:8 0.002388393 +7 mux_tree_tapbuf_size3_6_sram[1]:11 mux_tree_tapbuf_size3_6_sram[1]:10 0.0001657609 +8 mux_tree_tapbuf_size3_6_sram[1]:4 mux_tree_tapbuf_size3_6_sram[1]:3 0.0003370536 +9 mux_tree_tapbuf_size3_6_sram[1]:5 mux_tree_tapbuf_size3_6_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_6_sram[1]:3 mem_bottom_track_23\/FTB_19__44:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[2] 0.002236855 //LENGTH 15.520 LUMPCC 0.0005394887 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 104.265 23.120 +*I mem_bottom_track_25\/FTB_26__51:A I *L 0.001746 *C 98.440 17.680 +*I mux_bottom_track_25\/mux_l3_in_0_:S I *L 0.008363 *C 97.360 25.562 +*N mux_tree_tapbuf_size4_2_sram[2]:3 *C 98.395 25.500 +*N mux_tree_tapbuf_size4_2_sram[2]:4 *C 98.440 25.455 +*N mux_tree_tapbuf_size4_2_sram[2]:5 *C 98.440 17.680 +*N mux_tree_tapbuf_size4_2_sram[2]:6 *C 98.440 17.725 +*N mux_tree_tapbuf_size4_2_sram[2]:7 *C 98.440 23.120 +*N mux_tree_tapbuf_size4_2_sram[2]:8 *C 98.448 23.120 +*N mux_tree_tapbuf_size4_2_sram[2]:9 *C 103.953 23.120 +*N mux_tree_tapbuf_size4_2_sram[2]:10 *C 103.960 23.120 +*N mux_tree_tapbuf_size4_2_sram[2]:11 *C 103.960 23.120 +*N mux_tree_tapbuf_size4_2_sram[2]:12 *C 104.265 23.120 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_25\/FTB_26__51:A 1e-06 +2 mux_bottom_track_25\/mux_l3_in_0_:S 8.291885e-05 +3 mux_tree_tapbuf_size4_2_sram[2]:3 8.291885e-05 +4 mux_tree_tapbuf_size4_2_sram[2]:4 0.0001257979 +5 mux_tree_tapbuf_size4_2_sram[2]:5 2.983057e-05 +6 mux_tree_tapbuf_size4_2_sram[2]:6 0.0002807068 +7 mux_tree_tapbuf_size4_2_sram[2]:7 0.0004388798 +8 mux_tree_tapbuf_size4_2_sram[2]:8 0.0002661971 +9 mux_tree_tapbuf_size4_2_sram[2]:9 0.0002661971 +10 mux_tree_tapbuf_size4_2_sram[2]:10 3.017904e-05 +11 mux_tree_tapbuf_size4_2_sram[2]:11 4.795247e-05 +12 mux_tree_tapbuf_size4_2_sram[2]:12 4.37882e-05 +13 mux_tree_tapbuf_size4_2_sram[2]:8 chanx_right_in[7]:5 0.0002697443 +14 mux_tree_tapbuf_size4_2_sram[2]:9 chanx_right_in[7]:6 0.0002697443 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_2_sram[2]:12 0.152 +1 mux_tree_tapbuf_size4_2_sram[2]:3 mux_bottom_track_25\/mux_l3_in_0_:S 0.0009241072 +2 mux_tree_tapbuf_size4_2_sram[2]:4 mux_tree_tapbuf_size4_2_sram[2]:3 0.0045 +3 mux_tree_tapbuf_size4_2_sram[2]:5 mem_bottom_track_25\/FTB_26__51:A 0.152 +4 mux_tree_tapbuf_size4_2_sram[2]:6 mux_tree_tapbuf_size4_2_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size4_2_sram[2]:7 mux_tree_tapbuf_size4_2_sram[2]:6 0.004816964 +6 mux_tree_tapbuf_size4_2_sram[2]:7 mux_tree_tapbuf_size4_2_sram[2]:4 0.002084821 +7 mux_tree_tapbuf_size4_2_sram[2]:8 mux_tree_tapbuf_size4_2_sram[2]:7 0.00341 +8 mux_tree_tapbuf_size4_2_sram[2]:10 mux_tree_tapbuf_size4_2_sram[2]:9 0.00341 +9 mux_tree_tapbuf_size4_2_sram[2]:9 mux_tree_tapbuf_size4_2_sram[2]:8 0.00086245 +10 mux_tree_tapbuf_size4_2_sram[2]:11 mux_tree_tapbuf_size4_2_sram[2]:10 0.0045 +11 mux_tree_tapbuf_size4_2_sram[2]:12 mux_tree_tapbuf_size4_2_sram[2]:11 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[2] 0.003060168 //LENGTH 19.735 LUMPCC 0.0009462209 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 80.115 52.360 +*I mux_left_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 70.020 46.920 +*I mem_left_track_3\/FTB_10__35:A I *L 0.001746 *C 68.540 50.320 +*N mux_tree_tapbuf_size5_4_sram[2]:3 *C 68.578 50.320 +*N mux_tree_tapbuf_size5_4_sram[2]:4 *C 69.920 50.320 +*N mux_tree_tapbuf_size5_4_sram[2]:5 *C 69.920 46.920 +*N mux_tree_tapbuf_size5_4_sram[2]:6 *C 69.920 46.965 +*N mux_tree_tapbuf_size5_4_sram[2]:7 *C 69.920 49.935 +*N mux_tree_tapbuf_size5_4_sram[2]:8 *C 69.920 49.980 +*N mux_tree_tapbuf_size5_4_sram[2]:9 *C 72.635 49.980 +*N mux_tree_tapbuf_size5_4_sram[2]:10 *C 72.680 50.025 +*N mux_tree_tapbuf_size5_4_sram[2]:11 *C 72.680 51.623 +*N mux_tree_tapbuf_size5_4_sram[2]:12 *C 72.688 51.680 +*N mux_tree_tapbuf_size5_4_sram[2]:13 *C 79.573 51.680 +*N mux_tree_tapbuf_size5_4_sram[2]:14 *C 79.580 51.738 +*N mux_tree_tapbuf_size5_4_sram[2]:15 *C 79.580 52.315 +*N mux_tree_tapbuf_size5_4_sram[2]:16 *C 79.625 52.360 +*N mux_tree_tapbuf_size5_4_sram[2]:17 *C 80.078 52.360 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_3\/FTB_10__35:A 1e-06 +3 mux_tree_tapbuf_size5_4_sram[2]:3 0.0001311562 +4 mux_tree_tapbuf_size5_4_sram[2]:4 0.0001590254 +5 mux_tree_tapbuf_size5_4_sram[2]:5 3.604692e-05 +6 mux_tree_tapbuf_size5_4_sram[2]:6 0.0002146926 +7 mux_tree_tapbuf_size5_4_sram[2]:7 0.0002146926 +8 mux_tree_tapbuf_size5_4_sram[2]:8 0.0002161696 +9 mux_tree_tapbuf_size5_4_sram[2]:9 0.0001883004 +10 mux_tree_tapbuf_size5_4_sram[2]:10 0.000107581 +11 mux_tree_tapbuf_size5_4_sram[2]:11 0.000107581 +12 mux_tree_tapbuf_size5_4_sram[2]:12 0.0002539713 +13 mux_tree_tapbuf_size5_4_sram[2]:13 0.0002539713 +14 mux_tree_tapbuf_size5_4_sram[2]:14 4.967262e-05 +15 mux_tree_tapbuf_size5_4_sram[2]:15 4.967262e-05 +16 mux_tree_tapbuf_size5_4_sram[2]:16 6.420647e-05 +17 mux_tree_tapbuf_size5_4_sram[2]:17 6.420647e-05 +18 mux_tree_tapbuf_size5_4_sram[2]:12 chany_bottom_in[15]:9 0.0001363947 +19 mux_tree_tapbuf_size5_4_sram[2]:13 chany_bottom_in[15]:8 0.0001363947 +20 mux_tree_tapbuf_size5_4_sram[2]:12 chany_bottom_in[16]:8 0.0003329184 +21 mux_tree_tapbuf_size5_4_sram[2]:14 chany_bottom_in[16]:10 3.797365e-06 +22 mux_tree_tapbuf_size5_4_sram[2]:13 chany_bottom_in[16]:9 0.0003329184 +23 mux_tree_tapbuf_size5_4_sram[2]:15 chany_bottom_in[16]:11 3.797365e-06 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_4_sram[2]:17 0.152 +1 mux_tree_tapbuf_size5_4_sram[2]:9 mux_tree_tapbuf_size5_4_sram[2]:8 0.002424107 +2 mux_tree_tapbuf_size5_4_sram[2]:10 mux_tree_tapbuf_size5_4_sram[2]:9 0.0045 +3 mux_tree_tapbuf_size5_4_sram[2]:11 mux_tree_tapbuf_size5_4_sram[2]:10 0.001426339 +4 mux_tree_tapbuf_size5_4_sram[2]:12 mux_tree_tapbuf_size5_4_sram[2]:11 0.00341 +5 mux_tree_tapbuf_size5_4_sram[2]:14 mux_tree_tapbuf_size5_4_sram[2]:13 0.00341 +6 mux_tree_tapbuf_size5_4_sram[2]:13 mux_tree_tapbuf_size5_4_sram[2]:12 0.00107865 +7 mux_tree_tapbuf_size5_4_sram[2]:16 mux_tree_tapbuf_size5_4_sram[2]:15 0.0045 +8 mux_tree_tapbuf_size5_4_sram[2]:15 mux_tree_tapbuf_size5_4_sram[2]:14 0.000515625 +9 mux_tree_tapbuf_size5_4_sram[2]:17 mux_tree_tapbuf_size5_4_sram[2]:16 0.0004040179 +10 mux_tree_tapbuf_size5_4_sram[2]:8 mux_tree_tapbuf_size5_4_sram[2]:7 0.0045 +11 mux_tree_tapbuf_size5_4_sram[2]:8 mux_tree_tapbuf_size5_4_sram[2]:4 0.0003035715 +12 mux_tree_tapbuf_size5_4_sram[2]:7 mux_tree_tapbuf_size5_4_sram[2]:6 0.002651786 +13 mux_tree_tapbuf_size5_4_sram[2]:5 mux_left_track_3\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size5_4_sram[2]:6 mux_tree_tapbuf_size5_4_sram[2]:5 0.0045 +15 mux_tree_tapbuf_size5_4_sram[2]:3 mem_left_track_3\/FTB_10__35:A 0.152 +16 mux_tree_tapbuf_size5_4_sram[2]:4 mux_tree_tapbuf_size5_4_sram[2]:3 0.001198661 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.001886908 //LENGTH 16.445 LUMPCC 0.0001497636 DR + +*CONN +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 94.145 69.360 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 95.395 66.300 +*I mux_right_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 95.580 61.200 +*I mux_right_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 101.200 61.370 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 101.163 61.263 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 95.725 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 95.680 61.245 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 95.395 66.300 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 95.680 66.300 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 95.680 66.300 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 95.680 69.315 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 95.635 69.360 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 94.183 69.360 + +*CAP +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_4\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_4\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 0.0002867716 +5 mux_tree_tapbuf_size6_1_sram[1]:5 0.0002867716 +6 mux_tree_tapbuf_size6_1_sram[1]:6 0.0002617157 +7 mux_tree_tapbuf_size6_1_sram[1]:7 4.714337e-05 +8 mux_tree_tapbuf_size6_1_sram[1]:8 5.109221e-05 +9 mux_tree_tapbuf_size6_1_sram[1]:9 0.0004518796 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.0001600757 +11 mux_tree_tapbuf_size6_1_sram[1]:11 9.384712e-05 +12 mux_tree_tapbuf_size6_1_sram[1]:12 9.384712e-05 +13 mux_tree_tapbuf_size6_1_sram[1]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.488178e-05 +14 mux_tree_tapbuf_size6_1_sram[1]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.488178e-05 + +*RES +0 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:12 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:4 mux_right_track_4\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:5 mux_right_track_4\/mux_l2_in_0_:S 0.152 +3 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.004854911 +4 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.0001548913 +6 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:6 0.004513393 +8 mux_tree_tapbuf_size6_1_sram[1]:7 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.0045 +10 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:9 0.002691964 +11 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.001296875 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[2] 0.002642354 //LENGTH 18.870 LUMPCC 0.0009408546 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 20.545 31.280 +*I mem_bottom_track_3\/FTB_21__46:A I *L 0.001746 *C 29.900 34.000 +*I mux_bottom_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 27.500 31.280 +*N mux_tree_tapbuf_size7_1_sram[2]:3 *C 27.463 31.280 +*N mux_tree_tapbuf_size7_1_sram[2]:4 *C 29.863 34.000 +*N mux_tree_tapbuf_size7_1_sram[2]:5 *C 21.665 34.000 +*N mux_tree_tapbuf_size7_1_sram[2]:6 *C 21.620 33.955 +*N mux_tree_tapbuf_size7_1_sram[2]:7 *C 21.620 31.325 +*N mux_tree_tapbuf_size7_1_sram[2]:8 *C 21.620 31.280 +*N mux_tree_tapbuf_size7_1_sram[2]:9 *C 20.582 31.280 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_3\/FTB_21__46:A 1e-06 +2 mux_bottom_track_3\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_1_sram[2]:3 0.0002318272 +4 mux_tree_tapbuf_size7_1_sram[2]:4 0.0004187379 +5 mux_tree_tapbuf_size7_1_sram[2]:5 0.0004187379 +6 mux_tree_tapbuf_size7_1_sram[2]:6 0.000144672 +7 mux_tree_tapbuf_size7_1_sram[2]:7 0.000144672 +8 mux_tree_tapbuf_size7_1_sram[2]:8 0.0002995259 +9 mux_tree_tapbuf_size7_1_sram[2]:9 4.032651e-05 +10 mux_tree_tapbuf_size7_1_sram[2]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.943646e-05 +11 mux_tree_tapbuf_size7_1_sram[2]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.943646e-05 +12 mux_tree_tapbuf_size7_1_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.141077e-05 +13 mux_tree_tapbuf_size7_1_sram[2]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.930034e-05 +14 mux_tree_tapbuf_size7_1_sram[2]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.141077e-05 +15 mux_tree_tapbuf_size7_1_sram[2]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.930034e-05 +16 mux_tree_tapbuf_size7_1_sram[2]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 3.336175e-05 +17 mux_tree_tapbuf_size7_1_sram[2]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.699848e-05 +18 mux_tree_tapbuf_size7_1_sram[2]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.699848e-05 +19 mux_tree_tapbuf_size7_1_sram[2]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.336175e-05 +20 mux_tree_tapbuf_size7_1_sram[2]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.701833e-05 +21 mux_tree_tapbuf_size7_1_sram[2]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001903174 +22 mux_tree_tapbuf_size7_1_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.583754e-06 +23 mux_tree_tapbuf_size7_1_sram[2]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.583754e-06 +24 mux_tree_tapbuf_size7_1_sram[2]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001903174 +25 mux_tree_tapbuf_size7_1_sram[2]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.701833e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_1_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:3 0.005216518 +3 mux_tree_tapbuf_size7_1_sram[2]:7 mux_tree_tapbuf_size7_1_sram[2]:6 0.002348214 +4 mux_tree_tapbuf_size7_1_sram[2]:5 mux_tree_tapbuf_size7_1_sram[2]:4 0.007319197 +5 mux_tree_tapbuf_size7_1_sram[2]:6 mux_tree_tapbuf_size7_1_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size7_1_sram[2]:4 mem_bottom_track_3\/FTB_21__46:A 0.152 +7 mux_tree_tapbuf_size7_1_sram[2]:3 mux_bottom_track_3\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size7_1_sram[2]:9 mux_tree_tapbuf_size7_1_sram[2]:8 0.0009263393 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001315824 //LENGTH 12.510 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l3_in_0_:X O *L 0 *C 112.985 80.580 +*I mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 118.950 74.970 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 118.950 74.970 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 119.140 75.140 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 119.140 75.185 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 119.140 80.535 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 119.095 80.580 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 113.023 80.580 + +*CAP +0 mux_right_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.403781e-05 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.641969e-05 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000275525 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000275525 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003361583 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003361583 + +*RES +0 mux_right_track_0\/mux_l3_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001032609 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004776786 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.005421875 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_right_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.006634622 //LENGTH 35.300 LUMPCC 0.004254595 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_0_:X O *L 0 *C 40.655 44.200 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 11.670 39.305 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 11.708 39.395 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 14.215 39.440 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 14.260 39.485 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 14.260 40.742 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 14.268 40.800 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 38.633 40.800 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 38.640 40.858 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 38.640 44.155 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 38.685 44.200 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 40.617 44.200 + +*CAP +0 mux_left_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001739379 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001739379 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 9.529521e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.529521e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005351644 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0005351644 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002301794 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0002301794 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001544368 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0001544368 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[6]:24 0.0003192367 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[6]:23 0.0003192367 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[18]:22 0.001371107 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[18]:21 0.001371107 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004369541 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004369541 + +*RES +0 mux_left_track_5\/mux_l3_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002238839 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001122768 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.003817183 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002944197 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.001725446 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0006910291 //LENGTH 5.700 LUMPCC 0.0001310129 DR + +*CONN +*I mux_right_track_24\/mux_l3_in_0_:X O *L 0 *C 117.585 42.160 +*I mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 123.070 42.325 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 123.032 42.220 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 117.623 42.160 + +*CAP +0 mux_right_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002790081 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002790081 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[18]:13 6.550647e-05 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[18]:14 6.550647e-05 + +*RES +0 mux_right_track_24\/mux_l3_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.004830357 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006148505 //LENGTH 3.930 LUMPCC 9.863091e-05 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_1_:X O *L 0 *C 41.575 78.200 +*I mux_left_track_17\/mux_l3_in_0_:A0 I *L 0.001631 *C 40.780 80.580 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 40.780 80.580 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 40.940 80.580 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 40.940 80.535 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 40.940 78.245 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 40.985 78.200 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 41.538 78.200 + +*CAP +0 mux_left_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.634438e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.830524e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001307278 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001307278 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.905721e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.905721e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.931545e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.931545e-05 + +*RES +0 mux_left_track_17\/mux_l2_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.695653e-05 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_17\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008578838 //LENGTH 7.005 LUMPCC 9.511736e-05 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_0_:X O *L 0 *C 50.885 20.060 +*I mux_bottom_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.600 20.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.562 20.060 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 50.922 20.060 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003803832 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003803832 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[0]:6 3.105174e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[0]:12 4.226415e-06 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[0]:13 1.228052e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:5 3.105174e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:7 4.226415e-06 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[0]:12 1.228052e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005928571 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004481816 //LENGTH 2.585 LUMPCC 8.411733e-05 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 42.605 19.720 +*I mux_bottom_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 42.780 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 42.780 18.035 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 42.780 18.360 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 42.780 18.405 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 42.780 19.675 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 42.780 19.720 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 42.605 19.720 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.869888e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.520409e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.637123e-05 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.637123e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.917804e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.624075e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.205867e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 4.205867e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001133928 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001766305 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00657518 //LENGTH 52.190 LUMPCC 0.00105882 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_0_:X O *L 0 *C 39.845 47.260 +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 42.245 4.265 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 42.245 4.265 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 42.320 4.420 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 42.320 4.465 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 42.320 10.822 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 42.312 10.880 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 37.740 10.880 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 37.720 10.888 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 37.720 28.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 38.640 28.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 38.640 39.433 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 38.660 39.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 39.553 39.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 39.560 39.498 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 39.560 47.215 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:16 *C 39.560 47.260 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:17 *C 39.845 47.260 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.324106e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.878552e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000301719 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.000301719 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.000335635 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.000335635 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0006701907 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0007386962 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0007613747 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0006928692 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001238103 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0001238103 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.00045739 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.00045739 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:16 6.152328e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:17 6.056982e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:94 7.529751e-05 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:91 7.529751e-05 +20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 prog_clk[0]:543 8.968319e-05 +21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 prog_clk[0]:535 9.241498e-06 +22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 prog_clk[0]:512 9.241498e-06 +23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 prog_clk[0]:542 8.968319e-05 +24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003551879 +25 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0003551879 + +*RES +0 mux_bottom_track_5\/mux_l3_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:17 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.076088e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.005676339 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0007163583 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001703358 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.00341 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.000139825 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.0045 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.006890625 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:16 0.0001548913 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.002768691 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001441333 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002002702 //LENGTH 17.015 LUMPCC 0.0005672661 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_0_:X O *L 0 *C 69.635 17.680 +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 64.685 6.655 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 64.685 6.655 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 64.685 7.140 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 65.735 7.140 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 65.780 7.185 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 65.780 17.635 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 65.825 17.680 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 69.597 17.680 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.510442e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001141993 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.82423e-05 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004249807 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004249807 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001629642 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001629642 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[14] 8.671432e-05 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[14]:22 8.671432e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_4_sram[0]:8 3.50319e-05 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size2_4_sram[0]:10 4.47958e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size2_4_sram[0]:9 3.50319e-05 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size2_4_sram[0]:11 4.47958e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_166:13 4.578549e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_166:14 1.972166e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_166:9 5.158388e-05 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_166:10 1.972166e-05 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_166:14 4.578549e-05 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 optlc_net_166:8 5.158388e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0009375 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.009330357 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.003368304 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004330357 + +*END + +*D_NET ropt_net_216 0.0005681056 //LENGTH 4.420 LUMPCC 9.175864e-05 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 4.140 69.020 +*I ropt_mt_inst_834:A I *L 0.001766 *C 7.820 69.360 +*N ropt_net_216:2 *C 7.820 69.360 +*N ropt_net_216:3 *C 7.820 69.020 +*N ropt_net_216:4 *C 4.178 69.020 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 ropt_mt_inst_834:A 1e-06 +2 ropt_net_216:2 7.048144e-05 +3 ropt_net_216:3 0.0002188403 +4 ropt_net_216:4 0.0001850252 +5 ropt_net_216:4 chanx_right_in[17]:7 4.587932e-05 +6 ropt_net_216:3 chanx_right_in[17]:8 4.587932e-05 + +*RES +0 ropt_mt_inst_812:X ropt_net_216:4 0.152 +1 ropt_net_216:4 ropt_net_216:3 0.003252233 +2 ropt_net_216:2 ropt_mt_inst_834:A 0.152 +3 ropt_net_216:3 ropt_net_216:2 0.0003035715 + +*END + +*D_NET chanx_left_out[6] 0.0006881557 //LENGTH 5.425 LUMPCC 9.586125e-05 DR + +*CONN +*I ropt_mt_inst_830:X O *L 0 *C 4.140 45.220 +*P chanx_left_out[6] O *L 0.7423 *C 1.230 43.520 +*N chanx_left_out[6]:2 *C 1.833 43.520 +*N chanx_left_out[6]:3 *C 1.840 43.578 +*N chanx_left_out[6]:4 *C 1.840 45.175 +*N chanx_left_out[6]:5 *C 1.885 45.220 +*N chanx_left_out[6]:6 *C 4.103 45.220 + +*CAP +0 ropt_mt_inst_830:X 1e-06 +1 chanx_left_out[6] 6.926493e-05 +2 chanx_left_out[6]:2 6.926493e-05 +3 chanx_left_out[6]:3 8.957743e-05 +4 chanx_left_out[6]:4 8.957743e-05 +5 chanx_left_out[6]:5 0.0001368048 +6 chanx_left_out[6]:6 0.0001368048 +7 chanx_left_out[6]:6 ropt_net_212:2 2.814833e-05 +8 chanx_left_out[6]:5 ropt_net_212:3 2.814833e-05 +9 chanx_left_out[6]:4 ropt_net_212:4 1.978229e-05 +10 chanx_left_out[6]:3 ropt_net_212:5 1.978229e-05 + +*RES +0 ropt_mt_inst_830:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:6 chanx_left_out[6]:5 0.001979911 +2 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +3 chanx_left_out[6]:4 chanx_left_out[6]:3 0.001426339 +4 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +5 chanx_left_out[6]:2 chanx_left_out[6] 9.439165e-05 + +*END + +*D_NET mem_left_track_33/net_net_98 0.005840507 //LENGTH 48.245 LUMPCC 0.001293223 DR + +*CONN +*I mem_left_track_33\/FTB_27__52:X O *L 0 *C 60.025 80.580 +*I mem_left_track_33\/BUFT_RR_98:A I *L 0.001743 *C 16.560 77.520 +*N mem_left_track_33/net_net_98:2 *C 16.560 77.520 +*N mem_left_track_33/net_net_98:3 *C 16.560 77.180 +*N mem_left_track_33/net_net_98:4 *C 48.255 77.180 +*N mem_left_track_33/net_net_98:5 *C 48.300 77.225 +*N mem_left_track_33/net_net_98:6 *C 48.300 80.535 +*N mem_left_track_33/net_net_98:7 *C 48.345 80.580 +*N mem_left_track_33/net_net_98:8 *C 59.988 80.580 + +*CAP +0 mem_left_track_33\/FTB_27__52:X 1e-06 +1 mem_left_track_33\/BUFT_RR_98:A 1e-06 +2 mem_left_track_33/net_net_98:2 5.151056e-05 +3 mem_left_track_33/net_net_98:3 0.001497153 +4 mem_left_track_33/net_net_98:4 0.00147168 +5 mem_left_track_33/net_net_98:5 0.0002047513 +6 mem_left_track_33/net_net_98:6 0.0002047513 +7 mem_left_track_33/net_net_98:7 0.0005577192 +8 mem_left_track_33/net_net_98:8 0.0005577192 +9 mem_left_track_33/net_net_98:4 chanx_right_in[12]:8 0.0002536498 +10 mem_left_track_33/net_net_98:4 chanx_right_in[12]:10 0.0002267299 +11 mem_left_track_33/net_net_98:3 chanx_right_in[12]:7 0.0002536498 +12 mem_left_track_33/net_net_98:3 chanx_right_in[12]:9 0.0002267299 +13 mem_left_track_33/net_net_98:7 mux_tree_tapbuf_size5_6_sram[0]:10 2.700614e-05 +14 mem_left_track_33/net_net_98:7 mux_tree_tapbuf_size5_6_sram[0]:17 0.00010241 +15 mem_left_track_33/net_net_98:7 mux_tree_tapbuf_size5_6_sram[0]:18 3.681577e-05 +16 mem_left_track_33/net_net_98:8 mux_tree_tapbuf_size5_6_sram[0]:11 2.700614e-05 +17 mem_left_track_33/net_net_98:8 mux_tree_tapbuf_size5_6_sram[0]:12 0.00010241 +18 mem_left_track_33/net_net_98:8 mux_tree_tapbuf_size5_6_sram[0]:17 3.681577e-05 + +*RES +0 mem_left_track_33\/FTB_27__52:X mem_left_track_33/net_net_98:8 0.152 +1 mem_left_track_33/net_net_98:2 mem_left_track_33\/BUFT_RR_98:A 0.152 +2 mem_left_track_33/net_net_98:4 mem_left_track_33/net_net_98:3 0.02829911 +3 mem_left_track_33/net_net_98:5 mem_left_track_33/net_net_98:4 0.0045 +4 mem_left_track_33/net_net_98:7 mem_left_track_33/net_net_98:6 0.0045 +5 mem_left_track_33/net_net_98:6 mem_left_track_33/net_net_98:5 0.002955357 +6 mem_left_track_33/net_net_98:8 mem_left_track_33/net_net_98:7 0.01039509 +7 mem_left_track_33/net_net_98:3 mem_left_track_33/net_net_98:2 0.0003035715 + +*END + +*D_NET chanx_right_in[14] 0.02229167 //LENGTH 164.780 LUMPCC 0.006954777 DR + +*CONN +*P chanx_right_in[14] I *L 0.29796 *C 140.450 43.520 +*I mux_bottom_track_19\/mux_l1_in_0_:A1 I *L 0.00198 *C 63.020 25.500 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.330 48.280 +*I BUFT_RR_81:A I *L 0.001776 *C 11.500 42.160 +*N chanx_right_in[14]:4 *C 11.500 42.175 +*N chanx_right_in[14]:5 *C 11.500 42.500 +*N chanx_right_in[14]:6 *C 11.500 42.545 +*N chanx_right_in[14]:7 *C 11.500 44.823 +*N chanx_right_in[14]:8 *C 11.508 44.880 +*N chanx_right_in[14]:9 *C 58.420 44.880 +*N chanx_right_in[14]:10 *C 57.367 48.280 +*N chanx_right_in[14]:11 *C 58.375 48.280 +*N chanx_right_in[14]:12 *C 58.420 48.235 +*N chanx_right_in[14]:13 *C 63.020 25.500 +*N chanx_right_in[14]:14 *C 63.020 25.545 +*N chanx_right_in[14]:15 *C 63.020 36.335 +*N chanx_right_in[14]:16 *C 62.975 36.380 +*N chanx_right_in[14]:17 *C 58.465 36.380 +*N chanx_right_in[14]:18 *C 58.420 36.425 +*N chanx_right_in[14]:19 *C 58.420 44.200 +*N chanx_right_in[14]:20 *C 58.420 44.200 +*N chanx_right_in[14]:21 *C 86.480 44.200 +*N chanx_right_in[14]:22 *C 86.480 43.520 + +*CAP +0 chanx_right_in[14] 0.001946609 +1 mux_bottom_track_19\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +3 BUFT_RR_81:A 1e-06 +4 chanx_right_in[14]:4 4.03401e-05 +5 chanx_right_in[14]:5 7.815349e-05 +6 chanx_right_in[14]:6 0.0001109691 +7 chanx_right_in[14]:7 0.0001109691 +8 chanx_right_in[14]:8 0.002447769 +9 chanx_right_in[14]:9 0.002503711 +10 chanx_right_in[14]:10 0.0001143394 +11 chanx_right_in[14]:11 0.0001143394 +12 chanx_right_in[14]:12 0.000239156 +13 chanx_right_in[14]:13 3.210097e-05 +14 chanx_right_in[14]:14 0.0006055692 +15 chanx_right_in[14]:15 0.0006055692 +16 chanx_right_in[14]:16 0.0003413178 +17 chanx_right_in[14]:17 0.0003413178 +18 chanx_right_in[14]:18 0.0004340424 +19 chanx_right_in[14]:19 0.0007106204 +20 chanx_right_in[14]:20 0.001268839 +21 chanx_right_in[14]:21 0.001277225 +22 chanx_right_in[14]:22 0.002010938 +23 chanx_right_in[14] chanx_right_in[6]:17 0.0003705262 +24 chanx_right_in[14] chanx_right_in[6]:18 0.0003237459 +25 chanx_right_in[14]:7 chanx_right_in[6]:6 4.337078e-06 +26 chanx_right_in[14]:8 chanx_right_in[6]:8 5.208155e-06 +27 chanx_right_in[14]:6 chanx_right_in[6]:7 4.337078e-06 +28 chanx_right_in[14]:20 chanx_right_in[6]:16 0.0004578673 +29 chanx_right_in[14]:9 chanx_right_in[6]:9 5.208155e-06 +30 chanx_right_in[14]:21 chanx_right_in[6]:17 0.0004578673 +31 chanx_right_in[14]:22 chanx_right_in[6]:16 0.0003705262 +32 chanx_right_in[14]:22 chanx_right_in[6]:17 0.0003237459 +33 chanx_right_in[14] chanx_right_in[16] 1.233876e-05 +34 chanx_right_in[14] chanx_right_in[16]:38 0.0003024589 +35 chanx_right_in[14]:8 chanx_right_in[16]:20 2.619059e-05 +36 chanx_right_in[14]:20 chanx_right_in[16]:20 3.027824e-05 +37 chanx_right_in[14]:9 chanx_right_in[16]:21 2.619059e-05 +38 chanx_right_in[14]:21 chanx_right_in[16]:21 3.027824e-05 +39 chanx_right_in[14]:22 chanx_right_in[16]:37 0.0003024589 +40 chanx_right_in[14]:22 chanx_right_in[16]:39 1.233876e-05 +41 chanx_right_in[14]:8 chanx_left_in[5] 0.000322188 +42 chanx_right_in[14]:9 chanx_left_in[5]:42 0.000322188 +43 chanx_right_in[14] chanx_left_in[6]:19 0.0003525692 +44 chanx_right_in[14]:7 chanx_left_in[6]:33 8.366202e-07 +45 chanx_right_in[14]:6 chanx_left_in[6]:34 8.366202e-07 +46 chanx_right_in[14]:20 chanx_left_in[6]:24 3.020548e-05 +47 chanx_right_in[14]:20 chanx_left_in[6]:22 1.950226e-06 +48 chanx_right_in[14]:20 chanx_left_in[6]:20 1.137787e-05 +49 chanx_right_in[14]:21 chanx_left_in[6]:19 1.137787e-05 +50 chanx_right_in[14]:21 chanx_left_in[6]:23 3.020548e-05 +51 chanx_right_in[14]:21 chanx_left_in[6]:21 1.950226e-06 +52 chanx_right_in[14]:22 chanx_left_in[6]:20 0.0003525692 +53 chanx_right_in[14]:20 chany_bottom_in[1]:12 0.000729231 +54 chanx_right_in[14]:21 chany_bottom_in[1]:11 0.000729231 +55 chanx_right_in[14]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.819692e-05 +56 chanx_right_in[14]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.819692e-05 +57 chanx_right_in[14]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.791112e-05 +58 chanx_right_in[14]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003321797 +59 chanx_right_in[14]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.791112e-05 +60 chanx_right_in[14]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.779056e-05 +61 chanx_right_in[14]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003321797 +62 chanx_right_in[14]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.779056e-05 + +*RES +0 chanx_right_in[14] chanx_right_in[14]:22 0.0084553 +1 chanx_right_in[14]:17 chanx_right_in[14]:16 0.004026786 +2 chanx_right_in[14]:18 chanx_right_in[14]:17 0.0045 +3 chanx_right_in[14]:16 chanx_right_in[14]:15 0.0045 +4 chanx_right_in[14]:15 chanx_right_in[14]:14 0.009633929 +5 chanx_right_in[14]:13 mux_bottom_track_19\/mux_l1_in_0_:A1 0.152 +6 chanx_right_in[14]:14 chanx_right_in[14]:13 0.0045 +7 chanx_right_in[14]:11 chanx_right_in[14]:10 0.0008995536 +8 chanx_right_in[14]:12 chanx_right_in[14]:11 0.0045 +9 chanx_right_in[14]:10 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +10 chanx_right_in[14]:7 chanx_right_in[14]:6 0.002033482 +11 chanx_right_in[14]:8 chanx_right_in[14]:7 0.00341 +12 chanx_right_in[14]:5 chanx_right_in[14]:4 0.0001766304 +13 chanx_right_in[14]:6 chanx_right_in[14]:5 0.0045 +14 chanx_right_in[14]:4 BUFT_RR_81:A 0.152 +15 chanx_right_in[14]:19 chanx_right_in[14]:18 0.006941964 +16 chanx_right_in[14]:19 chanx_right_in[14]:12 0.003602678 +17 chanx_right_in[14]:20 chanx_right_in[14]:19 0.00341 +18 chanx_right_in[14]:20 chanx_right_in[14]:9 0.0001065333 +19 chanx_right_in[14]:9 chanx_right_in[14]:8 0.007349624 +20 chanx_right_in[14]:21 chanx_right_in[14]:20 0.004396066 +21 chanx_right_in[14]:22 chanx_right_in[14]:21 0.0001065333 + +*END + +*D_NET chany_bottom_in[2] 0.01090942 //LENGTH 79.355 LUMPCC 0.002184151 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 81.420 1.325 +*I mux_left_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 80.865 50.660 +*I mux_right_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 96.315 55.080 +*N chany_bottom_in[2]:3 *C 96.278 55.080 +*N chany_bottom_in[2]:4 *C 95.725 55.080 +*N chany_bottom_in[2]:5 *C 95.680 55.035 +*N chany_bottom_in[2]:6 *C 95.680 52.418 +*N chany_bottom_in[2]:7 *C 95.672 52.360 +*N chany_bottom_in[2]:8 *C 87.400 52.360 +*N chany_bottom_in[2]:9 *C 80.903 50.660 +*N chany_bottom_in[2]:10 *C 85.975 50.660 +*N chany_bottom_in[2]:11 *C 86.020 50.705 +*N chany_bottom_in[2]:12 *C 86.020 51.623 +*N chany_bottom_in[2]:13 *C 86.028 51.680 +*N chany_bottom_in[2]:14 *C 87.400 51.685 +*N chany_bottom_in[2]:15 *C 87.400 51.672 +*N chany_bottom_in[2]:16 *C 87.400 2.728 +*N chany_bottom_in[2]:17 *C 87.380 2.720 +*N chany_bottom_in[2]:18 *C 81.428 2.720 +*N chany_bottom_in[2]:19 *C 81.420 2.663 + +*CAP +0 chany_bottom_in[2] 0.0001025779 +1 mux_left_track_9\/mux_l1_in_1_:A1 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[2]:3 7.681314e-05 +4 chany_bottom_in[2]:4 7.681314e-05 +5 chany_bottom_in[2]:5 0.0001815333 +6 chany_bottom_in[2]:6 0.0001815333 +7 chany_bottom_in[2]:7 0.0004126868 +8 chany_bottom_in[2]:8 0.0004733239 +9 chany_bottom_in[2]:9 0.0003271431 +10 chany_bottom_in[2]:10 0.0003271431 +11 chany_bottom_in[2]:11 7.225852e-05 +12 chany_bottom_in[2]:12 7.225852e-05 +13 chany_bottom_in[2]:13 0.0001166479 +14 chany_bottom_in[2]:14 0.0001772851 +15 chany_bottom_in[2]:15 0.002540986 +16 chany_bottom_in[2]:16 0.002540986 +17 chany_bottom_in[2]:17 0.0004703495 +18 chany_bottom_in[2]:18 0.0004703495 +19 chany_bottom_in[2]:19 0.0001025779 +20 chany_bottom_in[2]:15 chany_bottom_in[3]:15 0.0006017539 +21 chany_bottom_in[2]:16 chany_bottom_in[3]:16 0.0006017539 +22 chany_bottom_in[2]:14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.674614e-05 +23 chany_bottom_in[2]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004735752 +24 chany_bottom_in[2]:13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.674614e-05 +25 chany_bottom_in[2]:8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004735752 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:19 0.001194197 +1 chany_bottom_in[2]:14 chany_bottom_in[2]:13 0.000215025 +2 chany_bottom_in[2]:14 chany_bottom_in[2]:8 0.00010575 +3 chany_bottom_in[2]:15 chany_bottom_in[2]:14 0.00341 +4 chany_bottom_in[2]:17 chany_bottom_in[2]:16 0.00341 +5 chany_bottom_in[2]:16 chany_bottom_in[2]:15 0.007668049 +6 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.00341 +7 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.0009325583 +8 chany_bottom_in[2]:6 chany_bottom_in[2]:5 0.002337054 +9 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.00341 +10 chany_bottom_in[2]:4 chany_bottom_in[2]:3 0.0004933036 +11 chany_bottom_in[2]:5 chany_bottom_in[2]:4 0.0045 +12 chany_bottom_in[2]:3 mux_right_track_8\/mux_l1_in_0_:A0 0.152 +13 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.0008191965 +14 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.00341 +15 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.004529018 +16 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.0045 +17 chany_bottom_in[2]:9 mux_left_track_9\/mux_l1_in_1_:A1 0.152 +18 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.001296025 + +*END + +*D_NET chany_bottom_in[15] 0.01209757 //LENGTH 88.745 LUMPCC 0.003249359 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 53.360 1.325 +*I mux_left_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 52.440 45.220 +*I mux_right_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 82.440 45.220 +*N chany_bottom_in[15]:3 *C 52.960 2.720 +*N chany_bottom_in[15]:4 *C 82.403 45.220 +*N chany_bottom_in[15]:5 *C 80.545 45.220 +*N chany_bottom_in[15]:6 *C 80.500 45.265 +*N chany_bottom_in[15]:7 *C 80.500 50.263 +*N chany_bottom_in[15]:8 *C 80.493 50.320 +*N chany_bottom_in[15]:9 *C 53.380 50.320 +*N chany_bottom_in[15]:10 *C 53.360 50.312 +*N chany_bottom_in[15]:11 *C 52.440 45.220 +*N chany_bottom_in[15]:12 *C 52.440 45.175 +*N chany_bottom_in[15]:13 *C 52.440 43.578 +*N chany_bottom_in[15]:14 *C 52.448 43.520 +*N chany_bottom_in[15]:15 *C 53.340 43.520 +*N chany_bottom_in[15]:16 *C 53.360 43.520 +*N chany_bottom_in[15]:17 *C 53.360 2.728 +*N chany_bottom_in[15]:18 *C 53.360 2.720 +*N chany_bottom_in[15]:19 *C 53.360 2.663 + +*CAP +0 chany_bottom_in[15] 0.0001077805 +1 mux_left_track_5\/mux_l1_in_2_:A1 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[15]:3 5.844825e-05 +4 chany_bottom_in[15]:4 0.0001760057 +5 chany_bottom_in[15]:5 0.0001760057 +6 chany_bottom_in[15]:6 0.0002932611 +7 chany_bottom_in[15]:7 0.0002932611 +8 chany_bottom_in[15]:8 0.001367141 +9 chany_bottom_in[15]:9 0.001367141 +10 chany_bottom_in[15]:10 0.0004526664 +11 chany_bottom_in[15]:11 3.296921e-05 +12 chany_bottom_in[15]:12 0.0001064933 +13 chany_bottom_in[15]:13 0.0001064933 +14 chany_bottom_in[15]:14 9.870291e-05 +15 chany_bottom_in[15]:15 9.870291e-05 +16 chany_bottom_in[15]:16 0.00219879 +17 chany_bottom_in[15]:17 0.001746124 +18 chany_bottom_in[15]:18 5.844825e-05 +19 chany_bottom_in[15]:19 0.0001077805 +20 chany_bottom_in[15]:16 chanx_right_in[13]:24 3.551932e-05 +21 chany_bottom_in[15]:16 chanx_right_in[13]:25 3.92178e-05 +22 chany_bottom_in[15]:16 chanx_right_in[13]:26 0.0002950278 +23 chany_bottom_in[15]:10 chanx_right_in[13]:24 3.92178e-05 +24 chany_bottom_in[15]:17 chanx_right_in[13]:9 0.0002950278 +25 chany_bottom_in[15]:17 chanx_right_in[13]:25 3.551932e-05 +26 chany_bottom_in[15]:16 bottom_left_grid_pin_41_[0]:10 0.000402027 +27 chany_bottom_in[15]:17 bottom_left_grid_pin_41_[0]:11 0.000402027 +28 chany_bottom_in[15]:9 mux_tree_tapbuf_size5_4_sram[2]:12 0.0001363947 +29 chany_bottom_in[15]:8 mux_tree_tapbuf_size5_4_sram[2]:13 0.0001363947 +30 chany_bottom_in[15]:12 mux_tree_tapbuf_size6_3_sram[0]:12 1.624423e-05 +31 chany_bottom_in[15]:13 mux_tree_tapbuf_size6_3_sram[0]:11 1.624423e-05 +32 chany_bottom_in[15]:9 mux_tree_tapbuf_size6_3_sram[0]:23 0.0003396097 +33 chany_bottom_in[15]:8 mux_tree_tapbuf_size6_3_sram[0]:24 0.0003396097 +34 chany_bottom_in[15]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003594095 +35 chany_bottom_in[15]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 1.229308e-06 +36 chany_bottom_in[15]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003594095 +37 chany_bottom_in[15]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 1.229308e-06 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:19 0.001194197 +1 chany_bottom_in[15]:11 mux_left_track_5\/mux_l1_in_2_:A1 0.152 +2 chany_bottom_in[15]:12 chany_bottom_in[15]:11 0.0045 +3 chany_bottom_in[15]:13 chany_bottom_in[15]:12 0.001426339 +4 chany_bottom_in[15]:14 chany_bottom_in[15]:13 0.00341 +5 chany_bottom_in[15]:15 chany_bottom_in[15]:14 0.000139825 +6 chany_bottom_in[15]:16 chany_bottom_in[15]:15 0.00341 +7 chany_bottom_in[15]:16 chany_bottom_in[15]:10 0.001064158 +8 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.004247624 +9 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.00341 +10 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.004462054 +11 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.00341 +12 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.001658482 +13 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.0045 +14 chany_bottom_in[15]:4 mux_right_track_16\/mux_l1_in_1_:A1 0.152 +15 chany_bottom_in[15]:19 chany_bottom_in[15]:18 0.00341 +16 chany_bottom_in[15]:18 chany_bottom_in[15]:17 0.00341 +17 chany_bottom_in[15]:18 chany_bottom_in[15]:3 5.69697e-05 +18 chany_bottom_in[15]:17 chany_bottom_in[15]:16 0.006390824 + +*END + +*D_NET chanx_left_in[1] 0.005381476 //LENGTH 50.420 LUMPCC 0 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 42.160 +*I mux_bottom_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 34.215 26.180 +*N chanx_left_in[1]:2 *C 34.178 26.180 +*N chanx_left_in[1]:3 *C 33.625 26.180 +*N chanx_left_in[1]:4 *C 33.580 26.225 +*N chanx_left_in[1]:5 *C 33.580 28.855 +*N chanx_left_in[1]:6 *C 33.535 28.900 +*N chanx_left_in[1]:7 *C 6.945 28.900 +*N chanx_left_in[1]:8 *C 6.900 28.945 +*N chanx_left_in[1]:9 *C 6.900 42.102 +*N chanx_left_in[1]:10 *C 6.893 42.160 + +*CAP +0 chanx_left_in[1] 0.0003604963 +1 mux_bottom_track_1\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[1]:2 5.811026e-05 +3 chanx_left_in[1]:3 5.811026e-05 +4 chanx_left_in[1]:4 0.0001783269 +5 chanx_left_in[1]:5 0.0001783269 +6 chanx_left_in[1]:6 0.001404371 +7 chanx_left_in[1]:7 0.001404371 +8 chanx_left_in[1]:8 0.0006889332 +9 chanx_left_in[1]:9 0.0006889332 +10 chanx_left_in[1]:10 0.0003604963 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:10 0.0008871249 +1 chanx_left_in[1]:2 mux_bottom_track_1\/mux_l1_in_2_:A0 0.152 +2 chanx_left_in[1]:3 chanx_left_in[1]:2 0.0004933036 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.0045 +4 chanx_left_in[1]:6 chanx_left_in[1]:5 0.0045 +5 chanx_left_in[1]:5 chanx_left_in[1]:4 0.002348214 +6 chanx_left_in[1]:7 chanx_left_in[1]:6 0.02374107 +7 chanx_left_in[1]:8 chanx_left_in[1]:7 0.0045 +8 chanx_left_in[1]:9 chanx_left_in[1]:8 0.01174777 +9 chanx_left_in[1]:10 chanx_left_in[1]:9 0.00341 + +*END + +*D_NET chanx_left_in[15] 0.004368267 //LENGTH 41.035 LUMPCC 0 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 96.560 +*I mux_bottom_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 13.800 69.020 +*N chanx_left_in[15]:2 *C 13.800 69.020 +*N chanx_left_in[15]:3 *C 13.800 69.360 +*N chanx_left_in[15]:4 *C 12.005 69.360 +*N chanx_left_in[15]:5 *C 11.960 69.405 +*N chanx_left_in[15]:6 *C 11.960 96.502 +*N chanx_left_in[15]:7 *C 11.953 96.560 + +*CAP +0 chanx_left_in[15] 0.0006331881 +1 mux_bottom_track_9\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[15]:2 5.442418e-05 +3 chanx_left_in[15]:3 0.0001507672 +4 chanx_left_in[15]:4 0.0001239015 +5 chanx_left_in[15]:5 0.001385899 +6 chanx_left_in[15]:6 0.001385899 +7 chanx_left_in[15]:7 0.0006331881 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:7 0.001679858 +1 chanx_left_in[15]:2 mux_bottom_track_9\/mux_l2_in_1_:A1 0.152 +2 chanx_left_in[15]:4 chanx_left_in[15]:3 0.001602679 +3 chanx_left_in[15]:5 chanx_left_in[15]:4 0.0045 +4 chanx_left_in[15]:6 chanx_left_in[15]:5 0.0241942 +5 chanx_left_in[15]:7 chanx_left_in[15]:6 0.00341 +6 chanx_left_in[15]:3 chanx_left_in[15]:2 0.0003035715 + +*END + +*D_NET chanx_right_out[16] 0.003902304 //LENGTH 34.485 LUMPCC 0 DR + +*CONN +*I mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 123.800 47.940 +*P chanx_right_out[16] O *L 0.7423 *C 140.450 63.920 +*N chanx_right_out[16]:2 *C 123.288 63.920 +*N chanx_right_out[16]:3 *C 123.280 63.863 +*N chanx_right_out[16]:4 *C 123.280 47.985 +*N chanx_right_out[16]:5 *C 123.325 47.940 +*N chanx_right_out[16]:6 *C 123.763 47.940 + +*CAP +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_right_out[16] 0.0009550909 +2 chanx_right_out[16]:2 0.0009550909 +3 chanx_right_out[16]:3 0.0009458043 +4 chanx_right_out[16]:4 0.0009458043 +5 chanx_right_out[16]:5 4.975677e-05 +6 chanx_right_out[16]:6 4.975677e-05 + +*RES +0 mux_right_track_32\/sky130_fd_sc_hd__buf_4_0_:X chanx_right_out[16]:6 0.152 +1 chanx_right_out[16]:6 chanx_right_out[16]:5 0.000390625 +2 chanx_right_out[16]:5 chanx_right_out[16]:4 0.0045 +3 chanx_right_out[16]:4 chanx_right_out[16]:3 0.01417634 +4 chanx_right_out[16]:3 chanx_right_out[16]:2 0.00341 +5 chanx_right_out[16]:2 chanx_right_out[16] 0.002688792 + +*END + +*D_NET chany_bottom_out[8] 0.00105281 //LENGTH 9.095 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 63.080 9.520 +*P chany_bottom_out[8] O *L 0.7423 *C 63.480 1.290 +*N chany_bottom_out[8]:2 *C 63.480 9.475 +*N chany_bottom_out[8]:3 *C 63.458 9.520 +*N chany_bottom_out[8]:4 *C 63.095 9.520 + +*CAP +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[8] 0.0004835647 +2 chany_bottom_out[8]:2 0.0004835647 +3 chany_bottom_out[8]:3 4.23403e-05 +4 chany_bottom_out[8]:4 4.23403e-05 + +*RES +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[8]:4 0.152 +1 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0045 +2 chany_bottom_out[8]:2 chany_bottom_out[8] 0.007308036 +3 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.0001970109 + +*END + +*D_NET chanx_left_out[4] 0.00163123 //LENGTH 10.530 LUMPCC 0.0005967104 DR + +*CONN +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.225 55.760 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 58.480 +*N chanx_left_out[4]:2 *C 6.893 58.480 +*N chanx_left_out[4]:3 *C 6.900 58.422 +*N chanx_left_out[4]:4 *C 6.900 55.805 +*N chanx_left_out[4]:5 *C 6.945 55.760 +*N chanx_left_out[4]:6 *C 8.188 55.760 + +*CAP +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[4] 0.0002548416 +2 chanx_left_out[4]:2 0.0002548416 +3 chanx_left_out[4]:3 0.0001664631 +4 chanx_left_out[4]:4 0.0001664631 +5 chanx_left_out[4]:5 9.545518e-05 +6 chanx_left_out[4]:6 9.545518e-05 +7 chanx_left_out[4] chanx_left_in[17]:32 0.0002983552 +8 chanx_left_out[4]:2 chanx_left_in[17]:31 0.0002983552 + +*RES +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[4]:6 0.152 +1 chanx_left_out[4]:6 chanx_left_out[4]:5 0.001109375 +2 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +3 chanx_left_out[4]:4 chanx_left_out[4]:3 0.002337054 +4 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.000887125 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.002232728 //LENGTH 17.327 LUMPCC 0.0002530651 DR + +*CONN +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 97.820 15.300 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.335 20.740 +*I mux_bottom_track_31\/mux_l1_in_0_:S I *L 0.00357 *C 89.800 23.120 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 89.815 23.120 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 90.138 23.120 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 90.160 23.075 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 90.160 20.785 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 90.160 20.740 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 90.373 20.740 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 94.715 20.740 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 94.760 20.695 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 94.760 15.345 +*N mux_tree_tapbuf_size2_2_sram[0]:12 *C 94.805 15.300 +*N mux_tree_tapbuf_size2_2_sram[0]:13 *C 97.782 15.300 + +*CAP +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_31\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 5.682344e-05 +4 mux_tree_tapbuf_size2_2_sram[0]:4 5.682344e-05 +5 mux_tree_tapbuf_size2_2_sram[0]:5 0.0001821227 +6 mux_tree_tapbuf_size2_2_sram[0]:6 0.0001821227 +7 mux_tree_tapbuf_size2_2_sram[0]:7 5.376504e-05 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.000308259 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.0002873617 +10 mux_tree_tapbuf_size2_2_sram[0]:10 0.0003031084 +11 mux_tree_tapbuf_size2_2_sram[0]:11 0.0003031084 +12 mux_tree_tapbuf_size2_2_sram[0]:12 0.0001215839 +13 mux_tree_tapbuf_size2_2_sram[0]:13 0.0001215839 +14 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0001265325 +15 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0001265325 + +*RES +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size2_2_sram[0]:6 mux_tree_tapbuf_size2_2_sram[0]:5 0.002044643 +3 mux_tree_tapbuf_size2_2_sram[0]:4 mux_tree_tapbuf_size2_2_sram[0]:3 0.0001752718 +4 mux_tree_tapbuf_size2_2_sram[0]:5 mux_tree_tapbuf_size2_2_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size2_2_sram[0]:3 mux_bottom_track_31\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_2_sram[0]:8 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.0001154891 +8 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_2_sram[0]:12 0.002658482 +9 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_2_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.004776786 +11 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.003877232 +12 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.0003278198 //LENGTH 2.530 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_35\/FTB_32__57:X O *L 0 *C 72.455 11.900 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 74.695 11.900 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 74.657 11.900 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 72.493 11.900 + +*CAP +0 mem_bottom_track_35\/FTB_32__57:X 1e-06 +1 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 0.0001629099 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0001629099 + +*RES +0 mem_bottom_track_35\/FTB_32__57:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 0.001933036 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[1] 0.002274239 //LENGTH 18.370 LUMPCC 0.000130219 DR + +*CONN +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 49.985 26.180 +*I mem_bottom_track_15\/FTB_15__40:A I *L 0.001746 *C 46.460 20.400 +*I mux_bottom_track_15\/mux_l2_in_0_:S I *L 0.00357 *C 55.100 28.560 +*N mux_tree_tapbuf_size3_2_sram[1]:3 *C 55.062 28.560 +*N mux_tree_tapbuf_size3_2_sram[1]:4 *C 52.945 28.560 +*N mux_tree_tapbuf_size3_2_sram[1]:5 *C 52.900 28.515 +*N mux_tree_tapbuf_size3_2_sram[1]:6 *C 52.900 26.225 +*N mux_tree_tapbuf_size3_2_sram[1]:7 *C 52.855 26.180 +*N mux_tree_tapbuf_size3_2_sram[1]:8 *C 46.498 20.400 +*N mux_tree_tapbuf_size3_2_sram[1]:9 *C 48.255 20.400 +*N mux_tree_tapbuf_size3_2_sram[1]:10 *C 48.300 20.445 +*N mux_tree_tapbuf_size3_2_sram[1]:11 *C 48.300 26.135 +*N mux_tree_tapbuf_size3_2_sram[1]:12 *C 48.345 26.180 +*N mux_tree_tapbuf_size3_2_sram[1]:13 *C 49.985 26.180 + +*CAP +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_15\/FTB_15__40:A 1e-06 +2 mux_bottom_track_15\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_2_sram[1]:3 0.0001332499 +4 mux_tree_tapbuf_size3_2_sram[1]:4 0.0001332499 +5 mux_tree_tapbuf_size3_2_sram[1]:5 0.0001550044 +6 mux_tree_tapbuf_size3_2_sram[1]:6 0.0001550044 +7 mux_tree_tapbuf_size3_2_sram[1]:7 0.000169869 +8 mux_tree_tapbuf_size3_2_sram[1]:8 0.0001381217 +9 mux_tree_tapbuf_size3_2_sram[1]:9 0.0001381217 +10 mux_tree_tapbuf_size3_2_sram[1]:10 0.0003512847 +11 mux_tree_tapbuf_size3_2_sram[1]:11 0.0003512847 +12 mux_tree_tapbuf_size3_2_sram[1]:12 0.000109013 +13 mux_tree_tapbuf_size3_2_sram[1]:13 0.0003068161 +14 mux_tree_tapbuf_size3_2_sram[1]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.510952e-05 +15 mux_tree_tapbuf_size3_2_sram[1]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.510952e-05 + +*RES +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_2_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_2_sram[1]:12 mux_tree_tapbuf_size3_2_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size3_2_sram[1]:11 mux_tree_tapbuf_size3_2_sram[1]:10 0.005080357 +3 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:8 0.001569197 +4 mux_tree_tapbuf_size3_2_sram[1]:10 mux_tree_tapbuf_size3_2_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size3_2_sram[1]:8 mem_bottom_track_15\/FTB_15__40:A 0.152 +6 mux_tree_tapbuf_size3_2_sram[1]:7 mux_tree_tapbuf_size3_2_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size3_2_sram[1]:6 mux_tree_tapbuf_size3_2_sram[1]:5 0.002044643 +8 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size3_2_sram[1]:3 0.001890625 +9 mux_tree_tapbuf_size3_2_sram[1]:5 mux_tree_tapbuf_size3_2_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_2_sram[1]:3 mux_bottom_track_15\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size3_2_sram[1]:13 mux_tree_tapbuf_size3_2_sram[1]:12 0.001464286 +12 mux_tree_tapbuf_size3_2_sram[1]:13 mux_tree_tapbuf_size3_2_sram[1]:7 0.0025625 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[2] 0.001743188 //LENGTH 14.455 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 24.685 71.740 +*I mux_bottom_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 25.660 67.320 +*I mem_bottom_track_9\/FTB_24__49:A I *L 0.001746 *C 20.240 74.800 +*N mux_tree_tapbuf_size4_0_sram[2]:3 *C 20.240 74.800 +*N mux_tree_tapbuf_size4_0_sram[2]:4 *C 20.240 74.755 +*N mux_tree_tapbuf_size4_0_sram[2]:5 *C 20.240 71.785 +*N mux_tree_tapbuf_size4_0_sram[2]:6 *C 20.285 71.740 +*N mux_tree_tapbuf_size4_0_sram[2]:7 *C 25.623 67.320 +*N mux_tree_tapbuf_size4_0_sram[2]:8 *C 24.425 67.320 +*N mux_tree_tapbuf_size4_0_sram[2]:9 *C 24.380 67.365 +*N mux_tree_tapbuf_size4_0_sram[2]:10 *C 24.380 71.695 +*N mux_tree_tapbuf_size4_0_sram[2]:11 *C 24.335 71.740 +*N mux_tree_tapbuf_size4_0_sram[2]:12 *C 24.685 71.740 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_9\/FTB_24__49:A 1e-06 +3 mux_tree_tapbuf_size4_0_sram[2]:3 3.338632e-05 +4 mux_tree_tapbuf_size4_0_sram[2]:4 0.0001767379 +5 mux_tree_tapbuf_size4_0_sram[2]:5 0.0001767379 +6 mux_tree_tapbuf_size4_0_sram[2]:6 0.0002710728 +7 mux_tree_tapbuf_size4_0_sram[2]:7 0.0001197387 +8 mux_tree_tapbuf_size4_0_sram[2]:8 0.0001197387 +9 mux_tree_tapbuf_size4_0_sram[2]:9 0.0002543625 +10 mux_tree_tapbuf_size4_0_sram[2]:10 0.0002543625 +11 mux_tree_tapbuf_size4_0_sram[2]:11 0.0002890891 +12 mux_tree_tapbuf_size4_0_sram[2]:12 4.496233e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_0_sram[2]:12 0.152 +1 mux_tree_tapbuf_size4_0_sram[2]:6 mux_tree_tapbuf_size4_0_sram[2]:5 0.0045 +2 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:4 0.002651786 +3 mux_tree_tapbuf_size4_0_sram[2]:3 mem_bottom_track_9\/FTB_24__49:A 0.152 +4 mux_tree_tapbuf_size4_0_sram[2]:4 mux_tree_tapbuf_size4_0_sram[2]:3 0.0045 +5 mux_tree_tapbuf_size4_0_sram[2]:11 mux_tree_tapbuf_size4_0_sram[2]:10 0.0045 +6 mux_tree_tapbuf_size4_0_sram[2]:11 mux_tree_tapbuf_size4_0_sram[2]:6 0.003616072 +7 mux_tree_tapbuf_size4_0_sram[2]:10 mux_tree_tapbuf_size4_0_sram[2]:9 0.003866072 +8 mux_tree_tapbuf_size4_0_sram[2]:8 mux_tree_tapbuf_size4_0_sram[2]:7 0.001069196 +9 mux_tree_tapbuf_size4_0_sram[2]:9 mux_tree_tapbuf_size4_0_sram[2]:8 0.0045 +10 mux_tree_tapbuf_size4_0_sram[2]:7 mux_bottom_track_9\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size4_0_sram[2]:12 mux_tree_tapbuf_size4_0_sram[2]:11 0.0001902174 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[2] 0.001541254 //LENGTH 13.370 LUMPCC 0 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 81.725 66.640 +*I mux_right_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 78.560 61.880 +*I mem_right_track_2\/FTB_6__31:A I *L 0.001746 *C 85.100 61.200 +*N mux_tree_tapbuf_size5_0_sram[2]:3 *C 85.078 61.228 +*N mux_tree_tapbuf_size5_0_sram[2]:4 *C 85.065 61.540 +*N mux_tree_tapbuf_size5_0_sram[2]:5 *C 78.560 61.880 +*N mux_tree_tapbuf_size5_0_sram[2]:6 *C 78.660 61.540 +*N mux_tree_tapbuf_size5_0_sram[2]:7 *C 81.420 61.540 +*N mux_tree_tapbuf_size5_0_sram[2]:8 *C 81.420 61.585 +*N mux_tree_tapbuf_size5_0_sram[2]:9 *C 81.420 66.595 +*N mux_tree_tapbuf_size5_0_sram[2]:10 *C 81.420 66.640 +*N mux_tree_tapbuf_size5_0_sram[2]:11 *C 81.725 66.640 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_2\/FTB_6__31:A 1e-06 +3 mux_tree_tapbuf_size5_0_sram[2]:3 3.218165e-05 +4 mux_tree_tapbuf_size5_0_sram[2]:4 0.0002411597 +5 mux_tree_tapbuf_size5_0_sram[2]:5 5.42819e-05 +6 mux_tree_tapbuf_size5_0_sram[2]:6 0.0001908585 +7 mux_tree_tapbuf_size5_0_sram[2]:7 0.0004062679 +8 mux_tree_tapbuf_size5_0_sram[2]:8 0.0002615043 +9 mux_tree_tapbuf_size5_0_sram[2]:9 0.0002615043 +10 mux_tree_tapbuf_size5_0_sram[2]:10 4.720331e-05 +11 mux_tree_tapbuf_size5_0_sram[2]:11 4.32929e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_0_sram[2]:11 0.152 +1 mux_tree_tapbuf_size5_0_sram[2]:3 mem_right_track_2\/FTB_6__31:A 0.152 +2 mux_tree_tapbuf_size5_0_sram[2]:5 mux_right_track_2\/mux_l3_in_0_:S 0.152 +3 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:6 0.002464286 +4 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:4 0.003254464 +5 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size5_0_sram[2]:10 mux_tree_tapbuf_size5_0_sram[2]:9 0.0045 +7 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:8 0.004473215 +8 mux_tree_tapbuf_size5_0_sram[2]:11 mux_tree_tapbuf_size5_0_sram[2]:10 0.0001657609 +9 mux_tree_tapbuf_size5_0_sram[2]:6 mux_tree_tapbuf_size5_0_sram[2]:5 0.0003035715 +10 mux_tree_tapbuf_size5_0_sram[2]:4 mux_tree_tapbuf_size5_0_sram[2]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_3_ccff_tail[0] 0.0006339517 //LENGTH 4.280 LUMPCC 0.0001448892 DR + +*CONN +*I mem_left_track_1\/FTB_9__34:X O *L 0 *C 72.455 38.760 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 70.555 37.060 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 *C 70.593 37.060 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 *C 72.175 37.060 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 *C 72.220 37.105 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 *C 72.220 38.715 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 *C 72.220 38.760 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 *C 72.455 38.760 + +*CAP +0 mem_left_track_1\/FTB_9__34:X 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 8.315381e-05 +3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 8.315381e-05 +4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 0.0001046738 +5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 0.0001046738 +6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 5.690208e-05 +7 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 5.450533e-05 +8 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 chanx_left_in[10]:40 7.244461e-05 +9 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 chanx_left_in[10]:41 7.244461e-05 + +*RES +0 mem_left_track_1\/FTB_9__34:X mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[0] 0.006224082 //LENGTH 48.505 LUMPCC 0 DR + +*CONN +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 115.305 69.700 +*I mux_right_track_8\/mux_l1_in_2_:S I *L 0.00357 *C 115.100 58.480 +*I mux_right_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 97.420 56.055 +*I mux_right_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 85.460 56.440 +*I mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 97.235 53.380 +*N mux_tree_tapbuf_size6_2_sram[0]:5 *C 97.235 53.380 +*N mux_tree_tapbuf_size6_2_sram[0]:6 *C 97.520 53.380 +*N mux_tree_tapbuf_size6_2_sram[0]:7 *C 97.520 53.425 +*N mux_tree_tapbuf_size6_2_sram[0]:8 *C 85.498 56.440 +*N mux_tree_tapbuf_size6_2_sram[0]:9 *C 97.420 56.440 +*N mux_tree_tapbuf_size6_2_sram[0]:10 *C 97.420 56.055 +*N mux_tree_tapbuf_size6_2_sram[0]:11 *C 97.520 55.760 +*N mux_tree_tapbuf_size6_2_sram[0]:12 *C 97.520 55.760 +*N mux_tree_tapbuf_size6_2_sram[0]:13 *C 97.520 57.755 +*N mux_tree_tapbuf_size6_2_sram[0]:14 *C 97.565 57.800 +*N mux_tree_tapbuf_size6_2_sram[0]:15 *C 115.000 57.800 +*N mux_tree_tapbuf_size6_2_sram[0]:16 *C 115.000 58.480 +*N mux_tree_tapbuf_size6_2_sram[0]:17 *C 115.000 58.525 +*N mux_tree_tapbuf_size6_2_sram[0]:18 *C 115.000 69.655 +*N mux_tree_tapbuf_size6_2_sram[0]:19 *C 115.000 69.700 +*N mux_tree_tapbuf_size6_2_sram[0]:20 *C 115.305 69.700 + +*CAP +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_8\/mux_l1_in_2_:S 1e-06 +2 mux_right_track_8\/mux_l1_in_0_:S 1e-06 +3 mux_right_track_8\/mux_l1_in_1_:S 1e-06 +4 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +5 mux_tree_tapbuf_size6_2_sram[0]:5 5.231519e-05 +6 mux_tree_tapbuf_size6_2_sram[0]:6 5.277609e-05 +7 mux_tree_tapbuf_size6_2_sram[0]:7 0.000132945 +8 mux_tree_tapbuf_size6_2_sram[0]:8 0.0008967959 +9 mux_tree_tapbuf_size6_2_sram[0]:9 0.0009207197 +10 mux_tree_tapbuf_size6_2_sram[0]:10 7.476656e-05 +11 mux_tree_tapbuf_size6_2_sram[0]:11 5.596124e-05 +12 mux_tree_tapbuf_size6_2_sram[0]:12 0.0002837993 +13 mux_tree_tapbuf_size6_2_sram[0]:13 0.0001173545 +14 mux_tree_tapbuf_size6_2_sram[0]:14 0.001162033 +15 mux_tree_tapbuf_size6_2_sram[0]:15 0.001208225 +16 mux_tree_tapbuf_size6_2_sram[0]:16 7.718104e-05 +17 mux_tree_tapbuf_size6_2_sram[0]:17 0.0005424211 +18 mux_tree_tapbuf_size6_2_sram[0]:18 0.0005424211 +19 mux_tree_tapbuf_size6_2_sram[0]:19 5.066386e-05 +20 mux_tree_tapbuf_size6_2_sram[0]:20 4.870388e-05 + +*RES +0 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_2_sram[0]:20 0.152 +1 mux_tree_tapbuf_size6_2_sram[0]:14 mux_tree_tapbuf_size6_2_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:12 0.00178125 +3 mux_tree_tapbuf_size6_2_sram[0]:10 mux_right_track_8\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size6_2_sram[0]:10 mux_tree_tapbuf_size6_2_sram[0]:9 0.00034375 +5 mux_tree_tapbuf_size6_2_sram[0]:6 mux_tree_tapbuf_size6_2_sram[0]:5 0.0001548913 +6 mux_tree_tapbuf_size6_2_sram[0]:7 mux_tree_tapbuf_size6_2_sram[0]:6 0.0045 +7 mux_tree_tapbuf_size6_2_sram[0]:5 mem_right_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size6_2_sram[0]:16 mux_right_track_8\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size6_2_sram[0]:16 mux_tree_tapbuf_size6_2_sram[0]:15 0.0006071429 +10 mux_tree_tapbuf_size6_2_sram[0]:17 mux_tree_tapbuf_size6_2_sram[0]:16 0.0045 +11 mux_tree_tapbuf_size6_2_sram[0]:19 mux_tree_tapbuf_size6_2_sram[0]:18 0.0045 +12 mux_tree_tapbuf_size6_2_sram[0]:18 mux_tree_tapbuf_size6_2_sram[0]:17 0.009937501 +13 mux_tree_tapbuf_size6_2_sram[0]:20 mux_tree_tapbuf_size6_2_sram[0]:19 0.0001657609 +14 mux_tree_tapbuf_size6_2_sram[0]:8 mux_right_track_8\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size6_2_sram[0]:11 mux_tree_tapbuf_size6_2_sram[0]:10 0.0002633929 +16 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:11 0.0045 +17 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:7 0.002084821 +18 mux_tree_tapbuf_size6_2_sram[0]:9 mux_tree_tapbuf_size6_2_sram[0]:8 0.01064509 +19 mux_tree_tapbuf_size6_2_sram[0]:15 mux_tree_tapbuf_size6_2_sram[0]:14 0.01556697 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[2] 0.001822851 //LENGTH 15.290 LUMPCC 0.0002876959 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 25.605 53.380 +*I mux_bottom_track_7\/mux_l3_in_0_:S I *L 0.00357 *C 23.820 45.560 +*I mem_bottom_track_7\/FTB_23__48:A I *L 0.001746 *C 23.000 55.760 +*N mux_tree_tapbuf_size7_3_sram[2]:3 *C 23.038 55.760 +*N mux_tree_tapbuf_size7_3_sram[2]:4 *C 23.875 55.760 +*N mux_tree_tapbuf_size7_3_sram[2]:5 *C 23.920 55.715 +*N mux_tree_tapbuf_size7_3_sram[2]:6 *C 23.805 45.560 +*N mux_tree_tapbuf_size7_3_sram[2]:7 *C 23.483 45.560 +*N mux_tree_tapbuf_size7_3_sram[2]:8 *C 23.460 45.605 +*N mux_tree_tapbuf_size7_3_sram[2]:9 *C 23.460 53.380 +*N mux_tree_tapbuf_size7_3_sram[2]:10 *C 23.920 53.425 +*N mux_tree_tapbuf_size7_3_sram[2]:11 *C 23.965 53.380 +*N mux_tree_tapbuf_size7_3_sram[2]:12 *C 25.568 53.380 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_7\/FTB_23__48:A 1e-06 +3 mux_tree_tapbuf_size7_3_sram[2]:3 6.893573e-05 +4 mux_tree_tapbuf_size7_3_sram[2]:4 6.893573e-05 +5 mux_tree_tapbuf_size7_3_sram[2]:5 0.00010592 +6 mux_tree_tapbuf_size7_3_sram[2]:6 5.948935e-05 +7 mux_tree_tapbuf_size7_3_sram[2]:7 5.948935e-05 +8 mux_tree_tapbuf_size7_3_sram[2]:8 0.0003834338 +9 mux_tree_tapbuf_size7_3_sram[2]:9 0.000416206 +10 mux_tree_tapbuf_size7_3_sram[2]:10 0.0001386922 +11 mux_tree_tapbuf_size7_3_sram[2]:11 0.0001155266 +12 mux_tree_tapbuf_size7_3_sram[2]:12 0.0001155266 +13 mux_tree_tapbuf_size7_3_sram[2]:8 chanx_left_in[5]:40 7.334616e-06 +14 mux_tree_tapbuf_size7_3_sram[2]:8 chanx_left_in[5]:41 6.69603e-05 +15 mux_tree_tapbuf_size7_3_sram[2]:5 chanx_left_in[5]:37 6.955303e-05 +16 mux_tree_tapbuf_size7_3_sram[2]:10 chanx_left_in[5]:41 6.955303e-05 +17 mux_tree_tapbuf_size7_3_sram[2]:9 chanx_left_in[5]:37 6.69603e-05 +18 mux_tree_tapbuf_size7_3_sram[2]:9 chanx_left_in[5]:41 7.334616e-06 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_3_sram[2]:12 0.152 +1 mux_tree_tapbuf_size7_3_sram[2]:6 mux_bottom_track_7\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_3_sram[2]:7 mux_tree_tapbuf_size7_3_sram[2]:6 0.0001752718 +3 mux_tree_tapbuf_size7_3_sram[2]:8 mux_tree_tapbuf_size7_3_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size7_3_sram[2]:4 mux_tree_tapbuf_size7_3_sram[2]:3 0.0007477679 +5 mux_tree_tapbuf_size7_3_sram[2]:5 mux_tree_tapbuf_size7_3_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size7_3_sram[2]:3 mem_bottom_track_7\/FTB_23__48:A 0.152 +7 mux_tree_tapbuf_size7_3_sram[2]:11 mux_tree_tapbuf_size7_3_sram[2]:10 0.0045 +8 mux_tree_tapbuf_size7_3_sram[2]:10 mux_tree_tapbuf_size7_3_sram[2]:9 0.0004107143 +9 mux_tree_tapbuf_size7_3_sram[2]:10 mux_tree_tapbuf_size7_3_sram[2]:5 0.002044643 +10 mux_tree_tapbuf_size7_3_sram[2]:12 mux_tree_tapbuf_size7_3_sram[2]:11 0.001430804 +11 mux_tree_tapbuf_size7_3_sram[2]:9 mux_tree_tapbuf_size7_3_sram[2]:8 0.006941964 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001005877 //LENGTH 8.385 LUMPCC 0.0002563123 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_0_:X O *L 0 *C 98.265 56.100 +*I mux_right_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 106.360 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 106.323 56.100 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 98.303 56.100 + +*CAP +0 mux_right_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003737825 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003737825 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001281562 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001281562 + +*RES +0 mux_right_track_8\/mux_l1_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.007160715 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004197158 //LENGTH 26.430 LUMPCC 0.001516185 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_1_:X O *L 0 *C 79.295 49.980 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 60.090 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 60.090 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 60.260 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 60.260 53.675 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 60.260 49.018 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 60.268 48.960 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 78.193 48.960 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 78.200 49.018 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 78.200 49.935 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 78.245 49.980 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 79.258 49.980 + +*CAP +0 mux_left_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.601531e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.041777e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002713588 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002713588 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0008498089 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0008498089 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.471583e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.471583e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 8.53867e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 8.53867e-05 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:404 1.211515e-05 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:405 1.211515e-05 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:273 0.0002530607 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:274 0.0001322776 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:268 0.0002530607 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:273 0.0001322776 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[15]:9 0.0003594095 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_bottom_in[15]:6 1.229308e-06 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[15]:8 0.0003594095 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_bottom_in[15]:7 1.229308e-06 + +*RES +0 mux_left_track_9\/mux_l1_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004158482 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00280825 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0008191965 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0009040179 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00118296 //LENGTH 8.405 LUMPCC 0.0002553867 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_1_:X O *L 0 *C 81.135 39.780 +*I mux_left_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 76.190 42.500 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 76.228 42.500 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 80.915 42.500 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 80.960 42.455 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 80.960 39.825 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 80.960 39.780 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.135 39.780 + +*CAP +0 mux_left_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002454988 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002454988 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001629451 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001629451 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.608863e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.259694e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size5_4_sram[1]:12 5.205076e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_4_sram[1]:13 5.205076e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_4_sram[1]:15 4.472712e-08 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_4_sram[1]:14 4.472712e-08 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 optlc_net_163:4 6.012474e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 optlc_net_163:3 6.012474e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_163:5 1.547312e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_163:12 1.547312e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004185268 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001451519 //LENGTH 10.880 LUMPCC 0.0004144292 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_0_:X O *L 0 *C 102.405 28.220 +*I mux_right_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 110.040 30.940 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 109.940 30.940 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 109.940 30.895 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 109.940 28.265 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 109.895 28.220 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 102.443 28.220 + +*CAP +0 mux_right_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.394164e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001676147 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001676147 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003329595 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003329595 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[11]:6 0.0001310889 +8 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[11]:5 0.0001310889 +9 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_167:14 8.119852e-07 +10 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_167:16 5.753356e-05 +11 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_167:25 1.778012e-05 +12 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_167:15 8.119852e-07 +13 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_167:24 1.778012e-05 +14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_167:25 5.753356e-05 + +*RES +0 mux_right_track_32\/mux_l1_in_0_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002348214 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.006654018 + +*END + +*D_NET mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001055119 //LENGTH 7.960 LUMPCC 0.0001559591 DR + +*CONN +*I mux_bottom_track_23\/mux_l1_in_1_:X O *L 0 *C 89.525 42.500 +*I mux_bottom_track_23\/mux_l2_in_0_:A0 I *L 0.001631 *C 87.690 37.400 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 87.690 37.400 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 87.860 37.400 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 87.860 37.445 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 87.860 39.100 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 88.320 39.100 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 88.320 42.455 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 88.365 42.500 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 89.488 42.500 + +*CAP +0 mux_bottom_track_23\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.263951e-05 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.628404e-05 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.372047e-05 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001261733 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001953643 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001629115 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001050335 +9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001050335 +10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size3_6_sram[0]:9 6.32555e-05 +11 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_6_sram[0]:10 1.472404e-05 +12 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_6_sram[0]:9 1.472404e-05 +13 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size3_6_sram[0]:10 6.32555e-05 + +*RES +0 mux_bottom_track_23\/mux_l1_in_1_:X mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001002232 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002995536 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239132e-05 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_23\/mux_l2_in_0_:A0 0.152 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001477679 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004107143 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0003277109 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_1_:X O *L 0 *C 35.705 48.280 +*I mux_bottom_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 37.895 48.280 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 37.858 48.280 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 35.742 48.280 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001628555 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001628555 + +*RES +0 mux_bottom_track_5\/mux_l2_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001888393 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001498242 //LENGTH 11.940 LUMPCC 0.000380052 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_1_:X O *L 0 *C 15.925 68.680 +*I mux_bottom_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 24.555 66.300 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 24.518 66.300 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 18.445 66.300 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 18.400 66.345 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 18.400 68.635 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 18.355 68.680 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 15.963 68.680 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003211154 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003211154 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001169416 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001169416 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001200383 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001200383 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size4_0_sram[1]:15 1.322199e-07 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size4_0_sram[1]:14 1.322199e-07 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size4_0_sram[1]:7 2.887897e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_0_sram[1]:9 6.31627e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_0_sram[1]:14 4.058714e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_0_sram[1]:8 2.887897e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size4_0_sram[1]:4 6.31627e-05 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size4_0_sram[1]:9 4.058714e-05 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.945777e-05 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.780718e-05 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.945777e-05 +19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.780718e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.005421875 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002136161 + +*END + +*D_NET ropt_net_217 0.0005007354 //LENGTH 4.440 LUMPCC 0.0001504288 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 4.140 99.620 +*I ropt_mt_inst_835:A I *L 0.001766 *C 7.820 99.280 +*N ropt_net_217:2 *C 7.783 99.280 +*N ropt_net_217:3 *C 4.140 99.280 +*N ropt_net_217:4 *C 4.140 99.620 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 ropt_mt_inst_835:A 1e-06 +2 ropt_net_217:2 0.0001371347 +3 ropt_net_217:3 0.0001616848 +4 ropt_net_217:4 4.948701e-05 +5 ropt_net_217:2 chanx_right_in[9]:13 7.521442e-05 +6 ropt_net_217:3 chanx_right_in[9]:12 7.521442e-05 + +*RES +0 ropt_mt_inst_790:X ropt_net_217:4 0.152 +1 ropt_net_217:2 ropt_mt_inst_835:A 0.152 +2 ropt_net_217:4 ropt_net_217:3 0.0003035715 +3 ropt_net_217:3 ropt_net_217:2 0.003252232 + +*END + +*D_NET ropt_net_198 0.002342482 //LENGTH 18.950 LUMPCC 0.0004868518 DR + +*CONN +*I FTB_4__3:X O *L 0 *C 11.040 45.560 +*I ropt_mt_inst_818:A I *L 0.001766 *C 3.220 55.760 +*N ropt_net_198:2 *C 3.258 55.760 +*N ropt_net_198:3 *C 4.555 55.760 +*N ropt_net_198:4 *C 4.600 55.715 +*N ropt_net_198:5 *C 4.600 45.605 +*N ropt_net_198:6 *C 4.645 45.560 +*N ropt_net_198:7 *C 11.003 45.560 + +*CAP +0 FTB_4__3:X 1e-06 +1 ropt_mt_inst_818:A 1e-06 +2 ropt_net_198:2 9.170726e-05 +3 ropt_net_198:3 9.170726e-05 +4 ropt_net_198:4 0.0004685296 +5 ropt_net_198:5 0.0004685296 +6 ropt_net_198:6 0.0003665782 +7 ropt_net_198:7 0.0003665782 +8 ropt_net_198:4 chanx_right_in[5]:10 8.063266e-06 +9 ropt_net_198:6 chanx_right_in[5]:8 6.280222e-05 +10 ropt_net_198:5 chanx_right_in[5]:9 8.063266e-06 +11 ropt_net_198:7 chanx_right_in[5]:7 6.280222e-05 +12 ropt_net_198:4 chanx_left_in[3]:6 9.38438e-05 +13 ropt_net_198:5 chanx_left_in[3]:5 9.38438e-05 +14 ropt_net_198:4 ropt_net_210:4 7.871659e-05 +15 ropt_net_198:5 ropt_net_210:5 7.871659e-05 + +*RES +0 FTB_4__3:X ropt_net_198:7 0.152 +1 ropt_net_198:2 ropt_mt_inst_818:A 0.152 +2 ropt_net_198:3 ropt_net_198:2 0.001158482 +3 ropt_net_198:4 ropt_net_198:3 0.0045 +4 ropt_net_198:6 ropt_net_198:5 0.0045 +5 ropt_net_198:5 ropt_net_198:4 0.009026786 +6 ropt_net_198:7 ropt_net_198:6 0.005676339 + +*END + +*D_NET ropt_net_207 0.001262048 //LENGTH 9.780 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 11.695 46.920 +*I ropt_mt_inst_825:A I *L 0.001767 *C 3.220 47.600 +*N ropt_net_207:2 *C 3.220 47.600 +*N ropt_net_207:3 *C 3.220 47.555 +*N ropt_net_207:4 *C 3.220 46.965 +*N ropt_net_207:5 *C 3.265 46.920 +*N ropt_net_207:6 *C 11.658 46.920 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 ropt_mt_inst_825:A 1e-06 +2 ropt_net_207:2 3.256436e-05 +3 ropt_net_207:3 6.639506e-05 +4 ropt_net_207:4 6.639506e-05 +5 ropt_net_207:5 0.0005473467 +6 ropt_net_207:6 0.0005473467 + +*RES +0 ropt_mt_inst_815:X ropt_net_207:6 0.152 +1 ropt_net_207:2 ropt_mt_inst_825:A 0.152 +2 ropt_net_207:3 ropt_net_207:2 0.0045 +3 ropt_net_207:5 ropt_net_207:4 0.0045 +4 ropt_net_207:4 ropt_net_207:3 0.0005267858 +5 ropt_net_207:6 ropt_net_207:5 0.007493304 + +*END + +*D_NET chanx_left_out[14] 0.001431545 //LENGTH 11.230 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_833:X O *L 0 *C 7.095 74.120 +*P chanx_left_out[14] O *L 0.7423 *C 1.230 69.360 +*N chanx_left_out[14]:2 *C 6.893 69.360 +*N chanx_left_out[14]:3 *C 6.900 69.418 +*N chanx_left_out[14]:4 *C 6.900 74.075 +*N chanx_left_out[14]:5 *C 6.900 74.120 +*N chanx_left_out[14]:6 *C 7.095 74.120 + +*CAP +0 ropt_mt_inst_833:X 1e-06 +1 chanx_left_out[14] 0.0003980962 +2 chanx_left_out[14]:2 0.0003980962 +3 chanx_left_out[14]:3 0.0002594167 +4 chanx_left_out[14]:4 0.0002594167 +5 chanx_left_out[14]:5 5.686714e-05 +6 chanx_left_out[14]:6 5.865251e-05 + +*RES +0 ropt_mt_inst_833:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:6 chanx_left_out[14]:5 0.0001059783 +2 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +3 chanx_left_out[14]:4 chanx_left_out[14]:3 0.004158482 +4 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +5 chanx_left_out[14]:2 chanx_left_out[14] 0.0008871249 + +*END + +*D_NET ropt_net_176 0.001522735 //LENGTH 12.590 LUMPCC 0 DR + +*CONN +*I BUFT_P_129:X O *L 0 *C 12.420 83.300 +*I ropt_mt_inst_796:A I *L 0.001766 *C 3.220 85.680 +*N ropt_net_176:2 *C 3.220 85.665 +*N ropt_net_176:3 *C 3.220 85.340 +*N ropt_net_176:4 *C 3.220 85.295 +*N ropt_net_176:5 *C 3.220 83.685 +*N ropt_net_176:6 *C 3.265 83.640 +*N ropt_net_176:7 *C 12.420 83.640 +*N ropt_net_176:8 *C 12.420 83.300 + +*CAP +0 BUFT_P_129:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_176:2 3.557355e-05 +3 ropt_net_176:3 6.845957e-05 +4 ropt_net_176:4 9.972189e-05 +5 ropt_net_176:5 9.972189e-05 +6 ropt_net_176:6 0.0005663572 +7 ropt_net_176:7 0.0005941475 +8 ropt_net_176:8 5.675327e-05 + +*RES +0 BUFT_P_129:X ropt_net_176:8 0.152 +1 ropt_net_176:2 ropt_mt_inst_796:A 0.152 +2 ropt_net_176:3 ropt_net_176:2 0.0001766304 +3 ropt_net_176:4 ropt_net_176:3 0.0045 +4 ropt_net_176:6 ropt_net_176:5 0.0045 +5 ropt_net_176:5 ropt_net_176:4 0.0014375 +6 ropt_net_176:8 ropt_net_176:7 0.0003035715 +7 ropt_net_176:7 ropt_net_176:6 0.008174107 + +*END + +*D_NET chanx_right_in[16] 0.02738473 //LENGTH 199.870 LUMPCC 0.007911068 DR + +*CONN +*P chanx_right_in[16] I *L 0.29796 *C 140.450 40.800 +*I mux_bottom_track_21\/mux_l1_in_0_:A1 I *L 0.00198 *C 81.060 25.500 +*I BUFT_P_143:A I *L 0.001766 *C 19.320 85.680 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 63.310 44.200 +*N chanx_right_in[16]:4 *C 63.310 44.200 +*N chanx_right_in[16]:5 *C 19.320 85.680 +*N chanx_right_in[16]:6 *C 19.320 85.340 +*N chanx_right_in[16]:7 *C 33.075 85.340 +*N chanx_right_in[16]:8 *C 33.120 85.295 +*N chanx_right_in[16]:9 *C 33.120 77.565 +*N chanx_right_in[16]:10 *C 33.165 77.520 +*N chanx_right_in[16]:11 *C 34.960 77.520 +*N chanx_right_in[16]:12 *C 34.990 77.550 +*N chanx_right_in[16]:13 *C 35.005 77.860 +*N chanx_right_in[16]:14 *C 35.420 77.860 +*N chanx_right_in[16]:15 *C 35.420 79.502 +*N chanx_right_in[16]:16 *C 35.428 79.560 +*N chanx_right_in[16]:17 *C 52.420 79.560 +*N chanx_right_in[16]:18 *C 52.440 79.553 +*N chanx_right_in[16]:19 *C 52.440 47.608 +*N chanx_right_in[16]:20 *C 52.460 47.600 +*N chanx_right_in[16]:21 *C 63.473 47.600 +*N chanx_right_in[16]:22 *C 63.480 47.543 +*N chanx_right_in[16]:23 *C 63.480 44.245 +*N chanx_right_in[16]:24 *C 63.525 44.200 +*N chanx_right_in[16]:25 *C 66.195 44.200 +*N chanx_right_in[16]:26 *C 66.240 44.155 +*N chanx_right_in[16]:27 *C 66.240 34.738 +*N chanx_right_in[16]:28 *C 66.248 34.680 +*N chanx_right_in[16]:29 *C 81.023 25.500 +*N chanx_right_in[16]:30 *C 80.085 25.500 +*N chanx_right_in[16]:31 *C 80.040 25.545 +*N chanx_right_in[16]:32 *C 80.040 34.623 +*N chanx_right_in[16]:33 *C 80.040 34.680 +*N chanx_right_in[16]:34 *C 118.213 34.680 +*N chanx_right_in[16]:35 *C 118.220 34.738 +*N chanx_right_in[16]:36 *C 118.220 41.422 +*N chanx_right_in[16]:37 *C 118.228 41.480 +*N chanx_right_in[16]:38 *C 137.080 41.480 +*N chanx_right_in[16]:39 *C 137.080 40.800 + +*CAP +0 chanx_right_in[16] 0.0002441317 +1 mux_bottom_track_21\/mux_l1_in_0_:A1 1e-06 +2 BUFT_P_143:A 1e-06 +3 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +4 chanx_right_in[16]:4 5.272768e-05 +5 chanx_right_in[16]:5 5.413063e-05 +6 chanx_right_in[16]:6 0.0008050749 +7 chanx_right_in[16]:7 0.0007784201 +8 chanx_right_in[16]:8 0.0003862257 +9 chanx_right_in[16]:9 0.0003862257 +10 chanx_right_in[16]:10 0.0001693183 +11 chanx_right_in[16]:11 0.000203432 +12 chanx_right_in[16]:12 3.201416e-05 +13 chanx_right_in[16]:13 5.657569e-05 +14 chanx_right_in[16]:14 0.0001300369 +15 chanx_right_in[16]:15 0.0001054754 +16 chanx_right_in[16]:16 0.0006485842 +17 chanx_right_in[16]:17 0.0006485842 +18 chanx_right_in[16]:18 0.001807045 +19 chanx_right_in[16]:19 0.001807045 +20 chanx_right_in[16]:20 0.0007338662 +21 chanx_right_in[16]:21 0.0007338662 +22 chanx_right_in[16]:22 0.0002169334 +23 chanx_right_in[16]:23 0.0002169334 +24 chanx_right_in[16]:24 0.0002415407 +25 chanx_right_in[16]:25 0.0002158952 +26 chanx_right_in[16]:26 0.0004351633 +27 chanx_right_in[16]:27 0.0004351633 +28 chanx_right_in[16]:28 0.0006050325 +29 chanx_right_in[16]:29 0.0001118543 +30 chanx_right_in[16]:30 0.0001118543 +31 chanx_right_in[16]:31 0.0004678135 +32 chanx_right_in[16]:32 0.0004678135 +33 chanx_right_in[16]:33 0.002175295 +34 chanx_right_in[16]:34 0.001570263 +35 chanx_right_in[16]:35 0.0003593762 +36 chanx_right_in[16]:36 0.0003593762 +37 chanx_right_in[16]:37 0.0006670144 +38 chanx_right_in[16]:38 0.0007267211 +39 chanx_right_in[16]:39 0.0003038384 +40 chanx_right_in[16] chanx_right_in[13] 3.946644e-06 +41 chanx_right_in[16] chanx_right_in[13]:33 5.981366e-06 +42 chanx_right_in[16]:37 chanx_right_in[13]:31 0.0001136329 +43 chanx_right_in[16]:37 chanx_right_in[13]:32 9.446601e-05 +44 chanx_right_in[16]:19 chanx_right_in[13]:25 0.0001302554 +45 chanx_right_in[16]:18 chanx_right_in[13]:24 0.0001302554 +46 chanx_right_in[16]:38 chanx_right_in[13]:32 0.0001136329 +47 chanx_right_in[16]:38 chanx_right_in[13]:33 9.446601e-05 +48 chanx_right_in[16]:39 chanx_right_in[13]:32 5.981366e-06 +49 chanx_right_in[16]:39 chanx_right_in[13]:34 3.946644e-06 +50 chanx_right_in[16] chanx_right_in[14] 1.233876e-05 +51 chanx_right_in[16]:37 chanx_right_in[14]:22 0.0003024589 +52 chanx_right_in[16]:21 chanx_right_in[14]:9 2.619059e-05 +53 chanx_right_in[16]:21 chanx_right_in[14]:21 3.027824e-05 +54 chanx_right_in[16]:20 chanx_right_in[14]:8 2.619059e-05 +55 chanx_right_in[16]:20 chanx_right_in[14]:20 3.027824e-05 +56 chanx_right_in[16]:38 chanx_right_in[14] 0.0003024589 +57 chanx_right_in[16]:39 chanx_right_in[14]:22 1.233876e-05 +58 chanx_right_in[16]:34 prog_clk[0]:190 4.856075e-06 +59 chanx_right_in[16]:34 prog_clk[0]:186 0.0004136071 +60 chanx_right_in[16]:34 prog_clk[0]:159 7.871605e-05 +61 chanx_right_in[16]:34 prog_clk[0]:155 0.0005713875 +62 chanx_right_in[16]:34 prog_clk[0]:194 6.243201e-06 +63 chanx_right_in[16]:21 prog_clk[0]:406 1.301069e-06 +64 chanx_right_in[16]:20 prog_clk[0]:411 1.301069e-06 +65 chanx_right_in[16]:17 prog_clk[0]:435 0.0001120451 +66 chanx_right_in[16]:16 prog_clk[0]:436 0.0001120451 +67 chanx_right_in[16]:32 prog_clk[0]:199 1.459119e-06 +68 chanx_right_in[16]:33 prog_clk[0]:187 0.0004136071 +69 chanx_right_in[16]:33 prog_clk[0]:195 6.243201e-06 +70 chanx_right_in[16]:33 prog_clk[0]:186 7.871605e-05 +71 chanx_right_in[16]:33 prog_clk[0]:159 0.0005713875 +72 chanx_right_in[16]:33 prog_clk[0]:194 4.856075e-06 +73 chanx_right_in[16]:31 prog_clk[0]:200 1.459119e-06 +74 chanx_right_in[16]:34 bottom_left_grid_pin_41_[0]:8 5.328385e-05 +75 chanx_right_in[16]:28 bottom_left_grid_pin_41_[0]:9 0.0002736265 +76 chanx_right_in[16]:33 bottom_left_grid_pin_41_[0]:9 5.328385e-05 +77 chanx_right_in[16]:33 bottom_left_grid_pin_41_[0]:8 0.0002736265 +78 chanx_right_in[16]:34 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 9.796207e-05 +79 chanx_right_in[16]:34 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.0004234466 +80 chanx_right_in[16]:28 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.0002488208 +81 chanx_right_in[16]:33 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.0004234466 +82 chanx_right_in[16]:33 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.0003467829 +83 chanx_right_in[16]:26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.290515e-05 +84 chanx_right_in[16]:27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.290515e-05 +85 chanx_right_in[16]:17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.0007562819 +86 chanx_right_in[16]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0007562819 +87 chanx_right_in[16]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.09535e-05 +88 chanx_right_in[16]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.09535e-05 +89 chanx_right_in[16]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.044435e-06 +90 chanx_right_in[16]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.044435e-06 +91 chanx_right_in[16]:32 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.403802e-05 +92 chanx_right_in[16]:30 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.206848e-09 +93 chanx_right_in[16]:31 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.403802e-05 +94 chanx_right_in[16]:29 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.206848e-09 + +*RES +0 chanx_right_in[16] chanx_right_in[16]:39 0.0005279667 +1 chanx_right_in[16]:35 chanx_right_in[16]:34 0.00341 +2 chanx_right_in[16]:34 chanx_right_in[16]:33 0.005980358 +3 chanx_right_in[16]:36 chanx_right_in[16]:35 0.00596875 +4 chanx_right_in[16]:37 chanx_right_in[16]:36 0.00341 +5 chanx_right_in[16]:24 chanx_right_in[16]:23 0.0045 +6 chanx_right_in[16]:24 chanx_right_in[16]:4 0.0001168478 +7 chanx_right_in[16]:23 chanx_right_in[16]:22 0.002944197 +8 chanx_right_in[16]:22 chanx_right_in[16]:21 0.00341 +9 chanx_right_in[16]:21 chanx_right_in[16]:20 0.001725292 +10 chanx_right_in[16]:20 chanx_right_in[16]:19 0.00341 +11 chanx_right_in[16]:19 chanx_right_in[16]:18 0.005004716 +12 chanx_right_in[16]:17 chanx_right_in[16]:16 0.002662158 +13 chanx_right_in[16]:18 chanx_right_in[16]:17 0.00341 +14 chanx_right_in[16]:15 chanx_right_in[16]:14 0.001466518 +15 chanx_right_in[16]:16 chanx_right_in[16]:15 0.00341 +16 chanx_right_in[16]:11 chanx_right_in[16]:10 0.001602679 +17 chanx_right_in[16]:12 chanx_right_in[16]:11 0.0045 +18 chanx_right_in[16]:10 chanx_right_in[16]:9 0.0045 +19 chanx_right_in[16]:9 chanx_right_in[16]:8 0.006901786 +20 chanx_right_in[16]:7 chanx_right_in[16]:6 0.01228125 +21 chanx_right_in[16]:8 chanx_right_in[16]:7 0.0045 +22 chanx_right_in[16]:5 BUFT_P_143:A 0.152 +23 chanx_right_in[16]:25 chanx_right_in[16]:24 0.002383929 +24 chanx_right_in[16]:26 chanx_right_in[16]:25 0.0045 +25 chanx_right_in[16]:27 chanx_right_in[16]:26 0.008408483 +26 chanx_right_in[16]:28 chanx_right_in[16]:27 0.00341 +27 chanx_right_in[16]:4 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +28 chanx_right_in[16]:32 chanx_right_in[16]:31 0.008104911 +29 chanx_right_in[16]:33 chanx_right_in[16]:32 0.00341 +30 chanx_right_in[16]:33 chanx_right_in[16]:28 0.002160825 +31 chanx_right_in[16]:30 chanx_right_in[16]:29 0.0008370536 +32 chanx_right_in[16]:31 chanx_right_in[16]:30 0.0045 +33 chanx_right_in[16]:29 mux_bottom_track_21\/mux_l1_in_0_:A1 0.152 +34 chanx_right_in[16]:6 chanx_right_in[16]:5 0.0003035715 +35 chanx_right_in[16]:13 chanx_right_in[16]:12 0.00019375 +36 chanx_right_in[16]:14 chanx_right_in[16]:13 0.0003705357 +37 chanx_right_in[16]:38 chanx_right_in[16]:37 0.002953558 +38 chanx_right_in[16]:39 chanx_right_in[16]:38 0.0001065333 + +*END + +*D_NET chanx_right_in[3] 0.01552836 //LENGTH 138.040 LUMPCC 0.001605752 DR + +*CONN +*P chanx_right_in[3] I *L 0.29796 *C 140.375 96.560 +*I mux_bottom_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 77.185 23.460 +*N chanx_right_in[3]:2 *C 77.223 23.460 +*N chanx_right_in[3]:3 *C 83.215 23.460 +*N chanx_right_in[3]:4 *C 83.260 23.505 +*N chanx_right_in[3]:5 *C 83.260 28.855 +*N chanx_right_in[3]:6 *C 83.305 28.900 +*N chanx_right_in[3]:7 *C 85.055 28.900 +*N chanx_right_in[3]:8 *C 85.100 28.945 +*N chanx_right_in[3]:9 *C 85.100 78.740 +*N chanx_right_in[3]:10 *C 85.100 96.515 +*N chanx_right_in[3]:11 *C 85.145 96.560 +*N chanx_right_in[3]:12 *C 125.995 96.560 +*N chanx_right_in[3]:13 *C 126.040 96.560 +*N chanx_right_in[3]:14 *C 126.047 96.560 + +*CAP +0 chanx_right_in[3] 0.0005771063 +1 mux_bottom_track_33\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[3]:2 0.000405438 +3 chanx_right_in[3]:3 0.000405438 +4 chanx_right_in[3]:4 0.0002181966 +5 chanx_right_in[3]:5 0.0002181966 +6 chanx_right_in[3]:6 0.0001432037 +7 chanx_right_in[3]:7 0.0001432037 +8 chanx_right_in[3]:8 0.002733341 +9 chanx_right_in[3]:9 0.003626918 +10 chanx_right_in[3]:10 0.0008935773 +11 chanx_right_in[3]:11 0.001973844 +12 chanx_right_in[3]:12 0.001973844 +13 chanx_right_in[3]:13 3.219387e-05 +14 chanx_right_in[3]:14 0.0005771063 +15 chanx_right_in[3] chanx_right_in[2] 1.880846e-05 +16 chanx_right_in[3] chanx_right_in[2]:27 0.0004617944 +17 chanx_right_in[3] chanx_right_in[2]:28 7.50887e-05 +18 chanx_right_in[3]:11 chanx_right_in[2]:26 1.034352e-05 +19 chanx_right_in[3]:12 chanx_right_in[2]:27 1.034352e-05 +20 chanx_right_in[3]:14 chanx_right_in[2]:26 0.0004617944 +21 chanx_right_in[3]:14 chanx_right_in[2]:27 7.50887e-05 +22 chanx_right_in[3]:14 chanx_right_in[2]:31 1.880846e-05 +23 chanx_right_in[3]:4 mux_tree_tapbuf_size3_5_sram[1]:5 4.20496e-05 +24 chanx_right_in[3]:4 mux_tree_tapbuf_size3_5_sram[1]:9 6.629092e-05 +25 chanx_right_in[3]:6 mux_tree_tapbuf_size3_5_sram[1]:11 3.750758e-06 +26 chanx_right_in[3]:5 mux_tree_tapbuf_size3_5_sram[1]:9 4.20496e-05 +27 chanx_right_in[3]:5 mux_tree_tapbuf_size3_5_sram[1]:10 6.629092e-05 +28 chanx_right_in[3]:7 mux_tree_tapbuf_size3_5_sram[1]:12 3.750758e-06 +29 chanx_right_in[3]:2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.777003e-05 +30 chanx_right_in[3]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.777003e-05 +31 chanx_right_in[3]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.269242e-05 +32 chanx_right_in[3]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.269242e-05 +33 chanx_right_in[3]:8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.428702e-05 +34 chanx_right_in[3]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.428702e-05 + +*RES +0 chanx_right_in[3] chanx_right_in[3]:14 0.002244642 +1 chanx_right_in[3]:2 mux_bottom_track_33\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[3]:3 chanx_right_in[3]:2 0.005350446 +3 chanx_right_in[3]:4 chanx_right_in[3]:3 0.0045 +4 chanx_right_in[3]:6 chanx_right_in[3]:5 0.0045 +5 chanx_right_in[3]:5 chanx_right_in[3]:4 0.004776786 +6 chanx_right_in[3]:7 chanx_right_in[3]:6 0.0015625 +7 chanx_right_in[3]:8 chanx_right_in[3]:7 0.0045 +8 chanx_right_in[3]:11 chanx_right_in[3]:10 0.0045 +9 chanx_right_in[3]:10 chanx_right_in[3]:9 0.01587054 +10 chanx_right_in[3]:12 chanx_right_in[3]:11 0.03647322 +11 chanx_right_in[3]:13 chanx_right_in[3]:12 0.0045 +12 chanx_right_in[3]:14 chanx_right_in[3]:13 0.00341 +13 chanx_right_in[3]:9 chanx_right_in[3]:8 0.04445983 + +*END + +*D_NET chany_bottom_in[1] 0.009029336 //LENGTH 65.060 LUMPCC 0.002214963 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 67.160 1.290 +*I mux_right_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.900 41.820 +*I mux_left_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 68.540 45.220 +*N chany_bottom_in[1]:3 *C 67.680 28.220 +*N chany_bottom_in[1]:4 *C 68.502 45.220 +*N chany_bottom_in[1]:5 *C 68.125 45.220 +*N chany_bottom_in[1]:6 *C 68.080 45.175 +*N chany_bottom_in[1]:7 *C 82.862 41.820 +*N chany_bottom_in[1]:8 *C 81.465 41.820 +*N chany_bottom_in[1]:9 *C 81.420 41.865 +*N chany_bottom_in[1]:10 *C 81.420 43.462 +*N chany_bottom_in[1]:11 *C 81.413 43.520 +*N chany_bottom_in[1]:12 *C 68.088 43.520 +*N chany_bottom_in[1]:13 *C 68.080 43.520 +*N chany_bottom_in[1]:14 *C 68.080 28.277 +*N chany_bottom_in[1]:15 *C 68.080 28.220 +*N chany_bottom_in[1]:16 *C 68.080 28.213 +*N chany_bottom_in[1]:17 *C 68.080 4.088 +*N chany_bottom_in[1]:18 *C 68.060 4.080 +*N chany_bottom_in[1]:19 *C 67.168 4.080 +*N chany_bottom_in[1]:20 *C 67.160 4.022 + +*CAP +0 chany_bottom_in[1] 0.0001738377 +1 mux_right_track_16\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[1]:3 5.674335e-05 +4 chany_bottom_in[1]:4 4.725602e-05 +5 chany_bottom_in[1]:5 4.725602e-05 +6 chany_bottom_in[1]:6 0.0001026056 +7 chany_bottom_in[1]:7 0.0001221822 +8 chany_bottom_in[1]:8 0.0001221822 +9 chany_bottom_in[1]:9 0.000132869 +10 chany_bottom_in[1]:10 0.000132869 +11 chany_bottom_in[1]:11 0.0007439237 +12 chany_bottom_in[1]:12 0.0007439237 +13 chany_bottom_in[1]:13 0.0009392966 +14 chany_bottom_in[1]:14 0.0007988918 +15 chany_bottom_in[1]:15 5.674335e-05 +16 chany_bottom_in[1]:16 0.001121589 +17 chany_bottom_in[1]:17 0.001121589 +18 chany_bottom_in[1]:18 8.73892e-05 +19 chany_bottom_in[1]:19 8.73892e-05 +20 chany_bottom_in[1]:20 0.0001738377 +21 chany_bottom_in[1]:12 chanx_right_in[14]:20 0.000729231 +22 chany_bottom_in[1]:11 chanx_right_in[14]:21 0.000729231 +23 chany_bottom_in[1]:16 chany_bottom_in[4]:15 0.0003010901 +24 chany_bottom_in[1]:17 chany_bottom_in[4]:16 0.0003010901 +25 chany_bottom_in[1]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.496056e-05 +26 chany_bottom_in[1]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.219995e-05 +27 chany_bottom_in[1]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.496056e-05 +28 chany_bottom_in[1]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.219995e-05 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:20 0.002439732 +1 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.0003370536 +2 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.0045 +3 chany_bottom_in[1]:4 mux_left_track_5\/mux_l1_in_1_:A1 0.152 +4 chany_bottom_in[1]:14 chany_bottom_in[1]:13 0.01360938 +5 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.00341 +6 chany_bottom_in[1]:15 chany_bottom_in[1]:3 5.69697e-05 +7 chany_bottom_in[1]:16 chany_bottom_in[1]:15 0.00341 +8 chany_bottom_in[1]:18 chany_bottom_in[1]:17 0.00341 +9 chany_bottom_in[1]:17 chany_bottom_in[1]:16 0.003779583 +10 chany_bottom_in[1]:20 chany_bottom_in[1]:19 0.00341 +11 chany_bottom_in[1]:19 chany_bottom_in[1]:18 0.000139825 +12 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.00341 +13 chany_bottom_in[1]:13 chany_bottom_in[1]:6 0.001477679 +14 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.002087583 +15 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.001426339 +16 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.00341 +17 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.001247768 +18 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.0045 +19 chany_bottom_in[1]:7 mux_right_track_16\/mux_l1_in_0_:A1 0.152 + +*END + +*D_NET chany_bottom_in[12] 0.01541963 //LENGTH 103.220 LUMPCC 0.007808925 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 79.580 1.290 +*I mux_right_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 85.200 74.460 +*I mux_left_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 76.190 91.460 +*N chany_bottom_in[12]:3 *C 78.720 68.000 +*N chany_bottom_in[12]:4 *C 76.190 91.460 +*N chany_bottom_in[12]:5 *C 75.900 91.460 +*N chany_bottom_in[12]:6 *C 75.900 91.415 +*N chany_bottom_in[12]:7 *C 75.900 75.185 +*N chany_bottom_in[12]:8 *C 75.945 75.140 +*N chany_bottom_in[12]:9 *C 79.120 75.140 +*N chany_bottom_in[12]:10 *C 85.163 74.460 +*N chany_bottom_in[12]:11 *C 79.120 74.460 +*N chany_bottom_in[12]:12 *C 79.120 74.415 +*N chany_bottom_in[12]:13 *C 79.120 68.058 +*N chany_bottom_in[12]:14 *C 79.120 68.000 +*N chany_bottom_in[12]:15 *C 79.120 67.993 +*N chany_bottom_in[12]:16 *C 79.120 55.275 +*N chany_bottom_in[12]:17 *C 79.120 5.448 +*N chany_bottom_in[12]:18 *C 79.135 5.440 +*N chany_bottom_in[12]:19 *C 79.578 5.440 +*N chany_bottom_in[12]:20 *C 79.580 5.383 + +*CAP +0 chany_bottom_in[12] 0.0002387385 +1 mux_right_track_0\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_33\/mux_l2_in_0_:A0 1e-06 +3 chany_bottom_in[12]:3 6.200981e-05 +4 chany_bottom_in[12]:4 4.767868e-05 +5 chany_bottom_in[12]:5 4.918578e-05 +6 chany_bottom_in[12]:6 0.0006736441 +7 chany_bottom_in[12]:7 0.0006736441 +8 chany_bottom_in[12]:8 0.0001446123 +9 chany_bottom_in[12]:9 0.0001843174 +10 chany_bottom_in[12]:10 0.0002398162 +11 chany_bottom_in[12]:11 0.0002795212 +12 chany_bottom_in[12]:12 0.0003393941 +13 chany_bottom_in[12]:13 0.0003393941 +14 chany_bottom_in[12]:14 6.200981e-05 +15 chany_bottom_in[12]:15 0.0005179867 +16 chany_bottom_in[12]:16 0.001907171 +17 chany_bottom_in[12]:17 0.001389184 +18 chany_bottom_in[12]:18 0.0001108306 +19 chany_bottom_in[12]:19 0.0001108306 +20 chany_bottom_in[12]:20 0.0002387385 +21 chany_bottom_in[12]:15 chanx_left_in[8]:18 0.0004689449 +22 chany_bottom_in[12]:17 chanx_left_in[8]:17 0.000363348 +23 chany_bottom_in[12]:16 chanx_left_in[8]:17 0.0004689449 +24 chany_bottom_in[12]:16 chanx_left_in[8]:18 0.000363348 +25 chany_bottom_in[12]:17 chany_bottom_in[8]:18 0.001598923 +26 chany_bottom_in[12]:16 chany_bottom_in[8]:17 0.001598923 +27 chany_bottom_in[12]:17 chany_bottom_in[9]:14 0.0008431313 +28 chany_bottom_in[12]:16 chany_bottom_in[9]:13 0.0008431313 +29 chany_bottom_in[12] chany_bottom_in[19] 2.960749e-05 +30 chany_bottom_in[12]:10 chany_bottom_in[19]:8 0.0002219602 +31 chany_bottom_in[12]:10 chany_bottom_in[19]:4 5.77383e-06 +32 chany_bottom_in[12]:8 chany_bottom_in[19]:12 1.037075e-05 +33 chany_bottom_in[12]:8 chany_bottom_in[19]:11 6.601173e-06 +34 chany_bottom_in[12]:11 chany_bottom_in[19]:12 0.0002219602 +35 chany_bottom_in[12]:11 chany_bottom_in[19]:5 5.77383e-06 +36 chany_bottom_in[12]:15 chany_bottom_in[19]:15 3.727232e-05 +37 chany_bottom_in[12]:17 chany_bottom_in[19]:17 7.492171e-05 +38 chany_bottom_in[12]:20 chany_bottom_in[19]:20 2.960749e-05 +39 chany_bottom_in[12]:9 chany_bottom_in[19]:12 6.601173e-06 +40 chany_bottom_in[12]:9 chany_bottom_in[19]:8 1.037075e-05 +41 chany_bottom_in[12]:16 chany_bottom_in[19]:16 0.000112194 +42 chany_bottom_in[12]:8 mux_tree_tapbuf_size4_3_sram[1]:15 4.713192e-05 +43 chany_bottom_in[12]:7 mux_tree_tapbuf_size4_3_sram[1]:17 9.632287e-05 +44 chany_bottom_in[12]:7 mux_tree_tapbuf_size4_3_sram[1]:18 9.952288e-05 +45 chany_bottom_in[12]:5 mux_tree_tapbuf_size4_3_sram[1]:4 6.301291e-07 +46 chany_bottom_in[12]:6 mux_tree_tapbuf_size4_3_sram[1]:6 9.952288e-05 +47 chany_bottom_in[12]:6 mux_tree_tapbuf_size4_3_sram[1]:18 9.632287e-05 +48 chany_bottom_in[12]:4 mux_tree_tapbuf_size4_3_sram[1]:5 6.301291e-07 +49 chany_bottom_in[12]:9 mux_tree_tapbuf_size4_3_sram[1]:16 4.713192e-05 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:20 0.003654018 +1 chany_bottom_in[12]:10 mux_right_track_0\/mux_l1_in_1_:A1 0.152 +2 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.0045 +3 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.01449107 +4 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.0001576087 +5 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.0045 +6 chany_bottom_in[12]:4 mux_left_track_33\/mux_l2_in_0_:A0 0.152 +7 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.005395089 +8 chany_bottom_in[12]:11 chany_bottom_in[12]:9 0.0006071429 +9 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0045 +10 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.005676339 +11 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.00341 +12 chany_bottom_in[12]:14 chany_bottom_in[12]:3 5.69697e-05 +13 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.00341 +14 chany_bottom_in[12]:18 chany_bottom_in[12]:17 0.00341 +15 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.007806308 +16 chany_bottom_in[12]:20 chany_bottom_in[12]:19 0.00341 +17 chany_bottom_in[12]:19 chany_bottom_in[12]:18 6.499219e-05 +18 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.002834821 +19 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.001992408 + +*END + +*D_NET bottom_left_grid_pin_40_[0] 0.01424186 //LENGTH 100.680 LUMPCC 0.004455907 DR + +*CONN +*P bottom_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 12.920 +*I mux_bottom_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 34.040 25.500 +*I mux_bottom_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 30.360 41.820 +*I mux_bottom_track_37\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.630 15.640 +*I mux_bottom_track_21\/mux_l1_in_0_:A0 I *L 0.001631 *C 80.675 26.180 +*N bottom_left_grid_pin_40_[0]:5 *C 80.713 26.180 +*N bottom_left_grid_pin_40_[0]:6 *C 81.375 26.180 +*N bottom_left_grid_pin_40_[0]:7 *C 81.420 26.135 +*N bottom_left_grid_pin_40_[0]:8 *C 82.593 15.640 +*N bottom_left_grid_pin_40_[0]:9 *C 81.465 15.640 +*N bottom_left_grid_pin_40_[0]:10 *C 81.420 15.685 +*N bottom_left_grid_pin_40_[0]:11 *C 81.420 23.800 +*N bottom_left_grid_pin_40_[0]:12 *C 81.413 23.800 +*N bottom_left_grid_pin_40_[0]:13 *C 30.398 41.820 +*N bottom_left_grid_pin_40_[0]:14 *C 31.695 41.820 +*N bottom_left_grid_pin_40_[0]:15 *C 31.740 41.775 +*N bottom_left_grid_pin_40_[0]:16 *C 31.740 39.100 +*N bottom_left_grid_pin_40_[0]:17 *C 32.200 39.100 +*N bottom_left_grid_pin_40_[0]:18 *C 34.003 25.500 +*N bottom_left_grid_pin_40_[0]:19 *C 32.245 25.500 +*N bottom_left_grid_pin_40_[0]:20 *C 32.200 25.500 +*N bottom_left_grid_pin_40_[0]:21 *C 32.200 23.858 +*N bottom_left_grid_pin_40_[0]:22 *C 32.208 23.800 +*N bottom_left_grid_pin_40_[0]:23 *C 33.120 23.800 +*N bottom_left_grid_pin_40_[0]:24 *C 33.120 23.793 +*N bottom_left_grid_pin_40_[0]:25 *C 33.120 12.928 +*N bottom_left_grid_pin_40_[0]:26 *C 33.100 12.920 + +*CAP +0 bottom_left_grid_pin_40_[0] 0.0002231959 +1 mux_bottom_track_1\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_5\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_37\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_21\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_40_[0]:5 8.81181e-05 +6 bottom_left_grid_pin_40_[0]:6 8.81181e-05 +7 bottom_left_grid_pin_40_[0]:7 9.525334e-05 +8 bottom_left_grid_pin_40_[0]:8 0.0001240142 +9 bottom_left_grid_pin_40_[0]:9 0.0001240142 +10 bottom_left_grid_pin_40_[0]:10 0.0004332366 +11 bottom_left_grid_pin_40_[0]:11 0.0005650591 +12 bottom_left_grid_pin_40_[0]:12 0.002475354 +13 bottom_left_grid_pin_40_[0]:13 0.0001254608 +14 bottom_left_grid_pin_40_[0]:14 0.0001254608 +15 bottom_left_grid_pin_40_[0]:15 0.0001758941 +16 bottom_left_grid_pin_40_[0]:16 0.0001874039 +17 bottom_left_grid_pin_40_[0]:17 0.0003661283 +18 bottom_left_grid_pin_40_[0]:18 0.0001548543 +19 bottom_left_grid_pin_40_[0]:19 0.0001548543 +20 bottom_left_grid_pin_40_[0]:20 0.0004269875 +21 bottom_left_grid_pin_40_[0]:21 4.265402e-05 +22 bottom_left_grid_pin_40_[0]:22 7.008329e-05 +23 bottom_left_grid_pin_40_[0]:23 0.002545437 +24 bottom_left_grid_pin_40_[0]:24 0.0004835875 +25 bottom_left_grid_pin_40_[0]:25 0.0004835875 +26 bottom_left_grid_pin_40_[0]:26 0.0002231959 +27 bottom_left_grid_pin_40_[0] prog_clk[0]:557 4.501121e-05 +28 bottom_left_grid_pin_40_[0]:20 prog_clk[0]:487 2.196817e-06 +29 bottom_left_grid_pin_40_[0]:20 prog_clk[0]:497 7.858656e-06 +30 bottom_left_grid_pin_40_[0]:20 prog_clk[0]:499 5.097573e-05 +31 bottom_left_grid_pin_40_[0]:20 prog_clk[0]:500 0.0001669295 +32 bottom_left_grid_pin_40_[0]:12 prog_clk[0]:509 8.672239e-06 +33 bottom_left_grid_pin_40_[0]:12 prog_clk[0]:541 8.24815e-06 +34 bottom_left_grid_pin_40_[0]:21 prog_clk[0]:500 5.097573e-05 +35 bottom_left_grid_pin_40_[0]:15 prog_clk[0]:482 1.002414e-05 +36 bottom_left_grid_pin_40_[0]:15 prog_clk[0]:486 1.752705e-06 +37 bottom_left_grid_pin_40_[0]:23 prog_clk[0]:540 8.24815e-06 +38 bottom_left_grid_pin_40_[0]:23 prog_clk[0]:541 8.672239e-06 +39 bottom_left_grid_pin_40_[0]:26 prog_clk[0]:556 4.501121e-05 +40 bottom_left_grid_pin_40_[0]:16 prog_clk[0]:483 1.002414e-05 +41 bottom_left_grid_pin_40_[0]:16 prog_clk[0]:487 1.752705e-06 +42 bottom_left_grid_pin_40_[0]:17 prog_clk[0]:486 2.196817e-06 +43 bottom_left_grid_pin_40_[0]:17 prog_clk[0]:488 7.858656e-06 +44 bottom_left_grid_pin_40_[0]:17 prog_clk[0]:499 0.0001669295 +45 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_37_[0]:13 0.0001748754 +46 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_37_[0]:26 0.0001182909 +47 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_37_[0]:27 5.656281e-05 +48 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_37_[0]:20 0.0005808586 +49 bottom_left_grid_pin_40_[0]:21 bottom_left_grid_pin_37_[0]:27 4.417897e-05 +50 bottom_left_grid_pin_40_[0]:23 bottom_left_grid_pin_37_[0]:21 0.0005808586 +51 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_37_[0]:10 0.0001748754 +52 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_37_[0]:13 7.411193e-05 +53 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_37_[0]:26 5.656281e-05 +54 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_38_[0]:12 0.0005250907 +55 bottom_left_grid_pin_40_[0]:23 bottom_left_grid_pin_38_[0]:13 0.0005250907 +56 bottom_left_grid_pin_40_[0]:20 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.00013944 +57 bottom_left_grid_pin_40_[0]:14 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 2.659538e-08 +58 bottom_left_grid_pin_40_[0]:15 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 7.007632e-07 +59 bottom_left_grid_pin_40_[0]:13 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 2.659538e-08 +60 bottom_left_grid_pin_40_[0]:16 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 7.007632e-07 +61 bottom_left_grid_pin_40_[0]:16 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 1.974184e-05 +62 bottom_left_grid_pin_40_[0]:17 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 1.974184e-05 +63 bottom_left_grid_pin_40_[0]:17 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.00013944 +64 bottom_left_grid_pin_40_[0]:11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.625681e-05 +65 bottom_left_grid_pin_40_[0]:11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.078072e-05 +66 bottom_left_grid_pin_40_[0]:10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.078072e-05 +67 bottom_left_grid_pin_40_[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.625681e-05 +68 bottom_left_grid_pin_40_[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.069187e-05 +69 bottom_left_grid_pin_40_[0]:23 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.069187e-05 +70 bottom_left_grid_pin_40_[0]:24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001529674 +71 bottom_left_grid_pin_40_[0]:25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001529674 + +*RES +0 bottom_left_grid_pin_40_[0] bottom_left_grid_pin_40_[0]:26 0.0005248333 +1 bottom_left_grid_pin_40_[0]:18 mux_bottom_track_1\/mux_l1_in_2_:A1 0.152 +2 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_40_[0]:18 0.001569197 +3 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_40_[0]:19 0.0045 +4 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_40_[0]:17 0.01214286 +5 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_40_[0]:10 0.007245536 +6 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_40_[0]:7 0.002084821 +7 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_40_[0]:11 0.00341 +8 bottom_left_grid_pin_40_[0]:21 bottom_left_grid_pin_40_[0]:20 0.001466518 +9 bottom_left_grid_pin_40_[0]:22 bottom_left_grid_pin_40_[0]:21 0.00341 +10 bottom_left_grid_pin_40_[0]:9 bottom_left_grid_pin_40_[0]:8 0.001006696 +11 bottom_left_grid_pin_40_[0]:10 bottom_left_grid_pin_40_[0]:9 0.0045 +12 bottom_left_grid_pin_40_[0]:8 mux_bottom_track_37\/mux_l1_in_0_:A0 0.152 +13 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_40_[0]:13 0.001158482 +14 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_40_[0]:14 0.0045 +15 bottom_left_grid_pin_40_[0]:13 mux_bottom_track_5\/mux_l1_in_2_:A1 0.152 +16 bottom_left_grid_pin_40_[0]:6 bottom_left_grid_pin_40_[0]:5 0.0005915179 +17 bottom_left_grid_pin_40_[0]:7 bottom_left_grid_pin_40_[0]:6 0.0045 +18 bottom_left_grid_pin_40_[0]:5 mux_bottom_track_21\/mux_l1_in_0_:A0 0.152 +19 bottom_left_grid_pin_40_[0]:23 bottom_left_grid_pin_40_[0]:22 0.0001429583 +20 bottom_left_grid_pin_40_[0]:23 bottom_left_grid_pin_40_[0]:12 0.007565824 +21 bottom_left_grid_pin_40_[0]:24 bottom_left_grid_pin_40_[0]:23 0.00341 +22 bottom_left_grid_pin_40_[0]:26 bottom_left_grid_pin_40_[0]:25 0.00341 +23 bottom_left_grid_pin_40_[0]:25 bottom_left_grid_pin_40_[0]:24 0.001702183 +24 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_40_[0]:15 0.002388393 +25 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_40_[0]:16 0.0004107143 + +*END + +*D_NET ropt_net_175 0.003294139 //LENGTH 28.710 LUMPCC 0.0001575669 DR + +*CONN +*I mux_right_track_4\/mux_l3_in_0_:X O *L 0 *C 115.780 61.200 +*I ropt_mt_inst_795:A I *L 0.001766 *C 134.780 55.760 +*N ropt_net_175:2 *C 134.780 55.760 +*N ropt_net_175:3 *C 134.780 55.420 +*N ropt_net_175:4 *C 132.020 55.420 +*N ropt_net_175:5 *C 132.020 55.760 +*N ropt_net_175:6 *C 131.090 55.760 +*N ropt_net_175:7 *C 131.065 56.100 +*N ropt_net_175:8 *C 130.225 56.100 +*N ropt_net_175:9 *C 130.180 56.145 +*N ropt_net_175:10 *C 130.180 61.155 +*N ropt_net_175:11 *C 130.135 61.200 +*N ropt_net_175:12 *C 127.880 61.200 +*N ropt_net_175:13 *C 127.880 60.520 +*N ropt_net_175:14 *C 122.360 60.520 +*N ropt_net_175:15 *C 122.360 61.200 +*N ropt_net_175:16 *C 115.818 61.200 + +*CAP +0 mux_right_track_4\/mux_l3_in_0_:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_175:2 6.025532e-05 +3 ropt_net_175:3 0.0001734142 +4 ropt_net_175:4 0.0001670695 +5 ropt_net_175:5 8.353299e-05 +6 ropt_net_175:6 8.366469e-05 +7 ropt_net_175:7 8.894115e-05 +8 ropt_net_175:8 6.581537e-05 +9 ropt_net_175:9 0.0002854394 +10 ropt_net_175:10 0.0002854394 +11 ropt_net_175:11 0.0001357288 +12 ropt_net_175:12 0.0001774095 +13 ropt_net_175:13 0.0003880149 +14 ropt_net_175:14 0.0003883683 +15 ropt_net_175:15 0.0003967562 +16 ropt_net_175:16 0.0003547221 +17 ropt_net_175:10 chanx_right_out[4]:5 3.999179e-06 +18 ropt_net_175:8 chanx_right_out[4]:8 4.650028e-06 +19 ropt_net_175:9 chanx_right_out[4]:6 3.999179e-06 +20 ropt_net_175:7 chanx_right_out[4]:7 4.650028e-06 +21 ropt_net_175:6 chanx_right_out[4]:8 9.446075e-06 +22 ropt_net_175:5 chanx_right_out[4]:7 9.446075e-06 +23 ropt_net_175:4 chanx_right_out[4]:8 6.068817e-05 +24 ropt_net_175:3 chanx_right_out[4]:7 6.068817e-05 + +*RES +0 mux_right_track_4\/mux_l3_in_0_:X ropt_net_175:16 0.152 +1 ropt_net_175:16 ropt_net_175:15 0.005841518 +2 ropt_net_175:11 ropt_net_175:10 0.0045 +3 ropt_net_175:10 ropt_net_175:9 0.004473215 +4 ropt_net_175:8 ropt_net_175:7 0.00075 +5 ropt_net_175:9 ropt_net_175:8 0.0045 +6 ropt_net_175:2 ropt_mt_inst_795:A 0.152 +7 ropt_net_175:15 ropt_net_175:14 0.000607143 +8 ropt_net_175:14 ropt_net_175:13 0.004928572 +9 ropt_net_175:13 ropt_net_175:12 0.0006071429 +10 ropt_net_175:12 ropt_net_175:11 0.002013393 +11 ropt_net_175:7 ropt_net_175:6 0.0002297298 +12 ropt_net_175:6 ropt_net_175:5 0.0008303572 +13 ropt_net_175:5 ropt_net_175:4 0.0003035715 +14 ropt_net_175:4 ropt_net_175:3 0.002464286 +15 ropt_net_175:3 ropt_net_175:2 0.0003035715 + +*END + +*D_NET chany_bottom_out[6] 0.00376284 //LENGTH 27.875 LUMPCC 0.0002939805 DR + +*CONN +*I mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 51.520 4.420 +*P chany_bottom_out[6] O *L 0.7423 *C 74.980 1.290 +*N chany_bottom_out[6]:2 *C 74.980 4.715 +*N chany_bottom_out[6]:3 *C 74.935 4.760 +*N chany_bottom_out[6]:4 *C 51.555 4.760 +*N chany_bottom_out[6]:5 *C 51.543 4.447 + +*CAP +0 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[6] 0.000208474 +2 chany_bottom_out[6]:2 0.000208474 +3 chany_bottom_out[6]:3 0.001494003 +4 chany_bottom_out[6]:4 0.001525456 +5 chany_bottom_out[6]:5 3.145283e-05 +6 chany_bottom_out[6]:3 ropt_net_208:4 7.389754e-05 +7 chany_bottom_out[6]:4 ropt_net_208:3 7.389754e-05 +8 chany_bottom_out[6]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.309268e-05 +9 chany_bottom_out[6]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.309268e-05 + +*RES +0 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[6]:5 0.152 +1 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +2 chany_bottom_out[6]:2 chany_bottom_out[6] 0.003058036 +3 chany_bottom_out[6]:5 chany_bottom_out[6]:4 0.0002111487 +4 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.020875 + +*END + +*D_NET chany_bottom_out[10] 0.001128956 //LENGTH 10.015 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 94.360 9.860 +*P chany_bottom_out[10] O *L 0.7423 *C 93.380 1.290 +*N chany_bottom_out[10]:2 *C 93.380 9.815 +*N chany_bottom_out[10]:3 *C 93.455 9.860 +*N chany_bottom_out[10]:4 *C 94.323 9.860 + +*CAP +0 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[10] 0.0004874615 +2 chany_bottom_out[10]:2 0.0004874615 +3 chany_bottom_out[10]:3 7.651676e-05 +4 chany_bottom_out[10]:4 7.651676e-05 + +*RES +0 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[10]:4 0.152 +1 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.0007745536 +2 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0045 +3 chany_bottom_out[10]:2 chany_bottom_out[10] 0.007611608 + +*END + +*D_NET chany_bottom_out[17] 0.0007776644 //LENGTH 6.840 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 59.745 6.800 +*P chany_bottom_out[17] O *L 0.7423 *C 58.880 1.290 +*N chany_bottom_out[17]:2 *C 58.880 6.755 +*N chany_bottom_out[17]:3 *C 58.925 6.800 +*N chany_bottom_out[17]:4 *C 59.708 6.800 + +*CAP +0 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[17] 0.000318292 +2 chany_bottom_out[17]:2 0.000318292 +3 chany_bottom_out[17]:3 7.004019e-05 +4 chany_bottom_out[17]:4 7.004019e-05 + +*RES +0 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[17]:4 0.152 +1 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.0006986608 +2 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0045 +3 chany_bottom_out[17]:2 chany_bottom_out[17] 0.004879464 + +*END + +*D_NET chanx_left_out[8] 0.002835324 //LENGTH 26.725 LUMPCC 0.0001781976 DR + +*CONN +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 22.025 80.580 +*P chanx_left_out[8] O *L 0.7423 *C 1.298 85.680 +*N chanx_left_out[8]:2 *C 1.380 85.680 +*N chanx_left_out[8]:3 *C 1.380 85.623 +*N chanx_left_out[8]:4 *C 1.380 80.625 +*N chanx_left_out[8]:5 *C 1.425 80.580 +*N chanx_left_out[8]:6 *C 21.988 80.580 + +*CAP +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[8] 2.794855e-05 +2 chanx_left_out[8]:2 2.794855e-05 +3 chanx_left_out[8]:3 0.0002611692 +4 chanx_left_out[8]:4 0.0002611692 +5 chanx_left_out[8]:5 0.001038945 +6 chanx_left_out[8]:6 0.001038945 +7 chanx_left_out[8]:6 ropt_net_211:3 6.370984e-05 +8 chanx_left_out[8]:6 ropt_net_211:7 2.538895e-05 +9 chanx_left_out[8]:5 ropt_net_211:2 6.370984e-05 +10 chanx_left_out[8]:5 ropt_net_211:6 2.538895e-05 + +*RES +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[8]:6 0.152 +1 chanx_left_out[8]:6 chanx_left_out[8]:5 0.01835938 +2 chanx_left_out[8]:5 chanx_left_out[8]:4 0.0045 +3 chanx_left_out[8]:4 chanx_left_out[8]:3 0.004462054 +4 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +5 chanx_left_out[8]:2 chanx_left_out[8] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.002333491 //LENGTH 19.980 LUMPCC 0.0001351134 DR + +*CONN +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 107.945 9.860 +*I mux_bottom_track_29\/mux_l1_in_0_:S I *L 0.00357 *C 107.540 20.110 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 103.215 17.340 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 103.215 17.340 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 103.040 17.340 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 103.040 17.385 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 103.040 20.355 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 103.085 20.400 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 107.483 20.400 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 107.540 20.110 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 107.640 19.720 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 107.640 19.675 +*N mux_tree_tapbuf_size2_1_sram[0]:12 *C 107.640 9.905 +*N mux_tree_tapbuf_size2_1_sram[0]:13 *C 107.640 9.860 +*N mux_tree_tapbuf_size2_1_sram[0]:14 *C 107.945 9.860 + +*CAP +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_29\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 4.941308e-05 +4 mux_tree_tapbuf_size2_1_sram[0]:4 5.326038e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:5 0.0001734877 +6 mux_tree_tapbuf_size2_1_sram[0]:6 0.0001734877 +7 mux_tree_tapbuf_size2_1_sram[0]:7 0.0003315791 +8 mux_tree_tapbuf_size2_1_sram[0]:8 0.0003577381 +9 mux_tree_tapbuf_size2_1_sram[0]:9 8.105508e-05 +10 mux_tree_tapbuf_size2_1_sram[0]:10 5.90292e-05 +11 mux_tree_tapbuf_size2_1_sram[0]:11 0.0004150114 +12 mux_tree_tapbuf_size2_1_sram[0]:12 0.0004150114 +13 mux_tree_tapbuf_size2_1_sram[0]:13 4.400845e-05 +14 mux_tree_tapbuf_size2_1_sram[0]:14 4.229555e-05 +15 mux_tree_tapbuf_size2_1_sram[0]:11 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.755671e-05 +16 mux_tree_tapbuf_size2_1_sram[0]:12 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.755671e-05 + +*RES +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:3 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_1_sram[0]:4 mux_tree_tapbuf_size2_1_sram[0]:3 9.51087e-05 +3 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_1_sram[0]:7 mux_tree_tapbuf_size2_1_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size2_1_sram[0]:6 mux_tree_tapbuf_size2_1_sram[0]:5 0.002651786 +6 mux_tree_tapbuf_size2_1_sram[0]:9 mux_bottom_track_29\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.0001686047 +8 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.0003482143 +9 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_1_sram[0]:13 mux_tree_tapbuf_size2_1_sram[0]:12 0.0045 +11 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:11 0.008723215 +12 mux_tree_tapbuf_size2_1_sram[0]:14 mux_tree_tapbuf_size2_1_sram[0]:13 0.0001657609 +13 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.00392634 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.0009289903 //LENGTH 6.720 LUMPCC 0.000136798 DR + +*CONN +*I mem_bottom_track_33\/FTB_31__56:X O *L 0 *C 71.505 23.195 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.795 20.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 67.795 20.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 68.080 20.740 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 68.080 20.785 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 68.080 23.075 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 68.125 23.120 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 71.505 23.195 + +*CAP +0 mem_bottom_track_33\/FTB_31__56:X 1e-06 +1 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 5.106505e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 5.404665e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0001082102 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0001082102 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.0002146948 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.0002539655 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_4_sram[0]:12 3.992078e-06 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_4_sram[0]:13 6.440692e-05 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_4_sram[0]:5 6.440692e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_4_sram[0]:13 3.992078e-06 + +*RES +0 mem_bottom_track_33\/FTB_31__56:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.003017857 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001041607 //LENGTH 7.800 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 46.765 39.100 +*I mux_bottom_track_13\/mux_l2_in_0_:S I *L 0.00357 *C 48.200 36.720 +*I mem_bottom_track_13\/FTB_14__39:A I *L 0.001746 *C 50.140 39.440 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 50.102 39.440 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 47.840 39.440 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 48.185 36.720 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 47.863 36.720 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 47.840 36.765 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 47.840 39.055 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 47.840 39.130 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 46.803 39.100 + +*CAP +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_13\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_13\/FTB_14__39:A 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 0.0001495987 +4 mux_tree_tapbuf_size3_1_sram[1]:4 0.0001793809 +5 mux_tree_tapbuf_size3_1_sram[1]:5 6.350868e-05 +6 mux_tree_tapbuf_size3_1_sram[1]:6 6.350868e-05 +7 mux_tree_tapbuf_size3_1_sram[1]:7 0.0001978918 +8 mux_tree_tapbuf_size3_1_sram[1]:8 0.0001978918 +9 mux_tree_tapbuf_size3_1_sram[1]:9 0.0001083043 +10 mux_tree_tapbuf_size3_1_sram[1]:10 7.852203e-05 + +*RES +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:3 mem_bottom_track_13\/FTB_14__39:A 0.152 +2 mux_tree_tapbuf_size3_1_sram[1]:5 mux_bottom_track_13\/mux_l2_in_0_:S 0.152 +3 mux_tree_tapbuf_size3_1_sram[1]:6 mux_tree_tapbuf_size3_1_sram[1]:5 0.0001752718 +4 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:4 0.0002767858 +7 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.002044643 +8 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0009263393 +9 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.002020089 + +*END + +*D_NET mux_tree_tapbuf_size3_5_sram[0] 0.002420124 //LENGTH 18.095 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 76.205 33.660 +*I mux_bottom_track_21\/mux_l1_in_1_:S I *L 0.00357 *C 80.400 30.600 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 78.375 28.220 +*I mux_bottom_track_21\/mux_l1_in_0_:S I *L 0.00357 *C 81.780 25.160 +*N mux_tree_tapbuf_size3_5_sram[0]:4 *C 81.743 25.160 +*N mux_tree_tapbuf_size3_5_sram[0]:5 *C 78.245 25.160 +*N mux_tree_tapbuf_size3_5_sram[0]:6 *C 78.200 25.205 +*N mux_tree_tapbuf_size3_5_sram[0]:7 *C 78.375 28.220 +*N mux_tree_tapbuf_size3_5_sram[0]:8 *C 78.200 27.880 +*N mux_tree_tapbuf_size3_5_sram[0]:9 *C 78.200 27.880 +*N mux_tree_tapbuf_size3_5_sram[0]:10 *C 80.362 30.600 +*N mux_tree_tapbuf_size3_5_sram[0]:11 *C 78.245 30.600 +*N mux_tree_tapbuf_size3_5_sram[0]:12 *C 78.200 30.600 +*N mux_tree_tapbuf_size3_5_sram[0]:13 *C 78.200 33.615 +*N mux_tree_tapbuf_size3_5_sram[0]:14 *C 78.155 33.660 +*N mux_tree_tapbuf_size3_5_sram[0]:15 *C 76.243 33.660 + +*CAP +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_21\/mux_l1_in_1_:S 1e-06 +2 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_21\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_5_sram[0]:4 0.0002923014 +5 mux_tree_tapbuf_size3_5_sram[0]:5 0.0002923014 +6 mux_tree_tapbuf_size3_5_sram[0]:6 0.0001569183 +7 mux_tree_tapbuf_size3_5_sram[0]:7 6.689392e-05 +8 mux_tree_tapbuf_size3_5_sram[0]:8 7.09033e-05 +9 mux_tree_tapbuf_size3_5_sram[0]:9 0.0003489629 +10 mux_tree_tapbuf_size3_5_sram[0]:10 0.0001963695 +11 mux_tree_tapbuf_size3_5_sram[0]:11 0.0001963695 +12 mux_tree_tapbuf_size3_5_sram[0]:12 0.0003659398 +13 mux_tree_tapbuf_size3_5_sram[0]:13 0.0001738249 +14 mux_tree_tapbuf_size3_5_sram[0]:14 0.0001276694 +15 mux_tree_tapbuf_size3_5_sram[0]:15 0.0001276694 + +*RES +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_5_sram[0]:15 0.152 +1 mux_tree_tapbuf_size3_5_sram[0]:7 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size3_5_sram[0]:8 mux_tree_tapbuf_size3_5_sram[0]:7 0.0001847826 +3 mux_tree_tapbuf_size3_5_sram[0]:9 mux_tree_tapbuf_size3_5_sram[0]:8 0.0045 +4 mux_tree_tapbuf_size3_5_sram[0]:9 mux_tree_tapbuf_size3_5_sram[0]:6 0.002388393 +5 mux_tree_tapbuf_size3_5_sram[0]:14 mux_tree_tapbuf_size3_5_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size3_5_sram[0]:13 mux_tree_tapbuf_size3_5_sram[0]:12 0.002691964 +7 mux_tree_tapbuf_size3_5_sram[0]:15 mux_tree_tapbuf_size3_5_sram[0]:14 0.001707589 +8 mux_tree_tapbuf_size3_5_sram[0]:11 mux_tree_tapbuf_size3_5_sram[0]:10 0.001890625 +9 mux_tree_tapbuf_size3_5_sram[0]:12 mux_tree_tapbuf_size3_5_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size3_5_sram[0]:12 mux_tree_tapbuf_size3_5_sram[0]:9 0.002428572 +11 mux_tree_tapbuf_size3_5_sram[0]:10 mux_bottom_track_21\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size3_5_sram[0]:5 mux_tree_tapbuf_size3_5_sram[0]:4 0.003122768 +13 mux_tree_tapbuf_size3_5_sram[0]:6 mux_tree_tapbuf_size3_5_sram[0]:5 0.0045 +14 mux_tree_tapbuf_size3_5_sram[0]:4 mux_bottom_track_21\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_5_ccff_tail[0] 0.001165358 //LENGTH 9.640 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_21\/FTB_18__43:X O *L 0 *C 87.635 26.180 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 85.735 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 *C 85.773 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 *C 88.275 31.620 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 *C 88.320 31.575 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 *C 88.320 26.225 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 *C 88.275 26.180 +*N mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 *C 87.672 26.180 + +*CAP +0 mem_bottom_track_21\/FTB_18__43:X 1e-06 +1 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 0.0001858605 +3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 0.0001858605 +4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 0.0003220046 +5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 0.0003220046 +6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 7.381369e-05 +7 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 7.381369e-05 + +*RES +0 mem_bottom_track_21\/FTB_18__43:X mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 0.002234375 +5 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_5_ccff_tail[0]:2 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[1] 0.002634903 //LENGTH 20.830 LUMPCC 0.0005725997 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 23.305 63.920 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 19.035 71.740 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 16.920 66.640 +*I mux_bottom_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 15.080 69.020 +*N mux_tree_tapbuf_size4_0_sram[1]:4 *C 15.118 69.020 +*N mux_tree_tapbuf_size4_0_sram[1]:5 *C 16.957 66.640 +*N mux_tree_tapbuf_size4_0_sram[1]:6 *C 17.435 66.640 +*N mux_tree_tapbuf_size4_0_sram[1]:7 *C 17.480 66.685 +*N mux_tree_tapbuf_size4_0_sram[1]:8 *C 17.480 68.975 +*N mux_tree_tapbuf_size4_0_sram[1]:9 *C 17.480 69.020 +*N mux_tree_tapbuf_size4_0_sram[1]:10 *C 19.035 71.740 +*N mux_tree_tapbuf_size4_0_sram[1]:11 *C 19.320 71.740 +*N mux_tree_tapbuf_size4_0_sram[1]:12 *C 19.320 71.695 +*N mux_tree_tapbuf_size4_0_sram[1]:13 *C 19.320 69.065 +*N mux_tree_tapbuf_size4_0_sram[1]:14 *C 19.320 69.020 +*N mux_tree_tapbuf_size4_0_sram[1]:15 *C 22.955 69.020 +*N mux_tree_tapbuf_size4_0_sram[1]:16 *C 23.000 68.975 +*N mux_tree_tapbuf_size4_0_sram[1]:17 *C 23.000 63.965 +*N mux_tree_tapbuf_size4_0_sram[1]:18 *C 23.000 63.920 +*N mux_tree_tapbuf_size4_0_sram[1]:19 *C 23.305 63.920 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +3 mux_bottom_track_9\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size4_0_sram[1]:4 0.0001068598 +5 mux_tree_tapbuf_size4_0_sram[1]:5 2.290856e-05 +6 mux_tree_tapbuf_size4_0_sram[1]:6 2.290856e-05 +7 mux_tree_tapbuf_size4_0_sram[1]:7 0.0001091641 +8 mux_tree_tapbuf_size4_0_sram[1]:8 0.0001091641 +9 mux_tree_tapbuf_size4_0_sram[1]:9 0.0002185631 +10 mux_tree_tapbuf_size4_0_sram[1]:10 4.83537e-05 +11 mux_tree_tapbuf_size4_0_sram[1]:11 5.502416e-05 +12 mux_tree_tapbuf_size4_0_sram[1]:12 0.0001625953 +13 mux_tree_tapbuf_size4_0_sram[1]:13 0.0001625953 +14 mux_tree_tapbuf_size4_0_sram[1]:14 0.000255194 +15 mux_tree_tapbuf_size4_0_sram[1]:15 0.0001406503 +16 mux_tree_tapbuf_size4_0_sram[1]:16 0.0002653387 +17 mux_tree_tapbuf_size4_0_sram[1]:17 0.0002653387 +18 mux_tree_tapbuf_size4_0_sram[1]:18 5.974921e-05 +19 mux_tree_tapbuf_size4_0_sram[1]:19 5.389627e-05 +20 mux_tree_tapbuf_size4_0_sram[1]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001159826 +21 mux_tree_tapbuf_size4_0_sram[1]:15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001159826 +22 mux_tree_tapbuf_size4_0_sram[1]:16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.614044e-06 +23 mux_tree_tapbuf_size4_0_sram[1]:16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.268772e-07 +24 mux_tree_tapbuf_size4_0_sram[1]:17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.614044e-06 +25 mux_tree_tapbuf_size4_0_sram[1]:17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.268772e-07 +26 mux_tree_tapbuf_size4_0_sram[1]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.060499e-06 +27 mux_tree_tapbuf_size4_0_sram[1]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.215485e-05 +28 mux_tree_tapbuf_size4_0_sram[1]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.060499e-06 +29 mux_tree_tapbuf_size4_0_sram[1]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.215485e-05 +30 mux_tree_tapbuf_size4_0_sram[1]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.322199e-07 +31 mux_tree_tapbuf_size4_0_sram[1]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.058714e-05 +32 mux_tree_tapbuf_size4_0_sram[1]:15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 1.322199e-07 +33 mux_tree_tapbuf_size4_0_sram[1]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.31627e-05 +34 mux_tree_tapbuf_size4_0_sram[1]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.058714e-05 +35 mux_tree_tapbuf_size4_0_sram[1]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.887897e-05 +36 mux_tree_tapbuf_size4_0_sram[1]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.887897e-05 +37 mux_tree_tapbuf_size4_0_sram[1]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.31627e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_0_sram[1]:19 0.152 +1 mux_tree_tapbuf_size4_0_sram[1]:14 mux_tree_tapbuf_size4_0_sram[1]:13 0.0045 +2 mux_tree_tapbuf_size4_0_sram[1]:14 mux_tree_tapbuf_size4_0_sram[1]:9 0.001642857 +3 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:12 0.002348214 +4 mux_tree_tapbuf_size4_0_sram[1]:11 mux_tree_tapbuf_size4_0_sram[1]:10 0.0001548913 +5 mux_tree_tapbuf_size4_0_sram[1]:12 mux_tree_tapbuf_size4_0_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size4_0_sram[1]:10 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size4_0_sram[1]:15 mux_tree_tapbuf_size4_0_sram[1]:14 0.003245536 +8 mux_tree_tapbuf_size4_0_sram[1]:16 mux_tree_tapbuf_size4_0_sram[1]:15 0.0045 +9 mux_tree_tapbuf_size4_0_sram[1]:18 mux_tree_tapbuf_size4_0_sram[1]:17 0.0045 +10 mux_tree_tapbuf_size4_0_sram[1]:17 mux_tree_tapbuf_size4_0_sram[1]:16 0.004473215 +11 mux_tree_tapbuf_size4_0_sram[1]:19 mux_tree_tapbuf_size4_0_sram[1]:18 0.0001657609 +12 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:8 0.0045 +13 mux_tree_tapbuf_size4_0_sram[1]:9 mux_tree_tapbuf_size4_0_sram[1]:4 0.002109375 +14 mux_tree_tapbuf_size4_0_sram[1]:8 mux_tree_tapbuf_size4_0_sram[1]:7 0.002044643 +15 mux_tree_tapbuf_size4_0_sram[1]:6 mux_tree_tapbuf_size4_0_sram[1]:5 0.0004263393 +16 mux_tree_tapbuf_size4_0_sram[1]:7 mux_tree_tapbuf_size4_0_sram[1]:6 0.0045 +17 mux_tree_tapbuf_size4_0_sram[1]:5 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size4_0_sram[1]:4 mux_bottom_track_9\/mux_l2_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[0] 0.005937928 //LENGTH 49.440 LUMPCC 0.000139069 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 86.785 80.240 +*I mux_right_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 61.080 67.320 +*I mux_right_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 67.520 63.630 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 71.015 69.700 +*N mux_tree_tapbuf_size5_0_sram[0]:4 *C 71.053 69.700 +*N mux_tree_tapbuf_size5_0_sram[0]:5 *C 67.520 63.630 +*N mux_tree_tapbuf_size5_0_sram[0]:6 *C 61.117 67.320 +*N mux_tree_tapbuf_size5_0_sram[0]:7 *C 62.055 67.320 +*N mux_tree_tapbuf_size5_0_sram[0]:8 *C 62.100 67.275 +*N mux_tree_tapbuf_size5_0_sram[0]:9 *C 62.100 63.965 +*N mux_tree_tapbuf_size5_0_sram[0]:10 *C 62.145 63.920 +*N mux_tree_tapbuf_size5_0_sram[0]:11 *C 67.520 63.920 +*N mux_tree_tapbuf_size5_0_sram[0]:12 *C 72.635 63.920 +*N mux_tree_tapbuf_size5_0_sram[0]:13 *C 72.680 63.965 +*N mux_tree_tapbuf_size5_0_sram[0]:14 *C 72.680 69.655 +*N mux_tree_tapbuf_size5_0_sram[0]:15 *C 72.680 69.700 +*N mux_tree_tapbuf_size5_0_sram[0]:16 *C 86.435 69.700 +*N mux_tree_tapbuf_size5_0_sram[0]:17 *C 86.480 69.745 +*N mux_tree_tapbuf_size5_0_sram[0]:18 *C 86.480 80.195 +*N mux_tree_tapbuf_size5_0_sram[0]:19 *C 86.480 80.240 +*N mux_tree_tapbuf_size5_0_sram[0]:20 *C 86.785 80.240 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_right_track_2\/mux_l1_in_1_:S 1e-06 +2 mux_right_track_2\/mux_l1_in_0_:S 1e-06 +3 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_0_sram[0]:4 0.0001193331 +5 mux_tree_tapbuf_size5_0_sram[0]:5 5.389693e-05 +6 mux_tree_tapbuf_size5_0_sram[0]:6 9.196761e-05 +7 mux_tree_tapbuf_size5_0_sram[0]:7 9.196761e-05 +8 mux_tree_tapbuf_size5_0_sram[0]:8 0.0001983127 +9 mux_tree_tapbuf_size5_0_sram[0]:9 0.0001983127 +10 mux_tree_tapbuf_size5_0_sram[0]:10 0.0003518276 +11 mux_tree_tapbuf_size5_0_sram[0]:11 0.0006581151 +12 mux_tree_tapbuf_size5_0_sram[0]:12 0.0002789067 +13 mux_tree_tapbuf_size5_0_sram[0]:13 0.0003854645 +14 mux_tree_tapbuf_size5_0_sram[0]:14 0.0003854645 +15 mux_tree_tapbuf_size5_0_sram[0]:15 0.0009606467 +16 mux_tree_tapbuf_size5_0_sram[0]:16 0.0008097731 +17 mux_tree_tapbuf_size5_0_sram[0]:17 0.0005567537 +18 mux_tree_tapbuf_size5_0_sram[0]:18 0.0005567537 +19 mux_tree_tapbuf_size5_0_sram[0]:19 5.008346e-05 +20 mux_tree_tapbuf_size5_0_sram[0]:20 4.728021e-05 +21 mux_tree_tapbuf_size5_0_sram[0]:12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.953452e-05 +22 mux_tree_tapbuf_size5_0_sram[0]:11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.953452e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_0_sram[0]:20 0.152 +1 mux_tree_tapbuf_size5_0_sram[0]:16 mux_tree_tapbuf_size5_0_sram[0]:15 0.01228125 +2 mux_tree_tapbuf_size5_0_sram[0]:17 mux_tree_tapbuf_size5_0_sram[0]:16 0.0045 +3 mux_tree_tapbuf_size5_0_sram[0]:19 mux_tree_tapbuf_size5_0_sram[0]:18 0.0045 +4 mux_tree_tapbuf_size5_0_sram[0]:18 mux_tree_tapbuf_size5_0_sram[0]:17 0.009330357 +5 mux_tree_tapbuf_size5_0_sram[0]:20 mux_tree_tapbuf_size5_0_sram[0]:19 0.0001657609 +6 mux_tree_tapbuf_size5_0_sram[0]:15 mux_tree_tapbuf_size5_0_sram[0]:14 0.0045 +7 mux_tree_tapbuf_size5_0_sram[0]:15 mux_tree_tapbuf_size5_0_sram[0]:4 0.001453125 +8 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:13 0.005080357 +9 mux_tree_tapbuf_size5_0_sram[0]:12 mux_tree_tapbuf_size5_0_sram[0]:11 0.004566964 +10 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:12 0.0045 +11 mux_tree_tapbuf_size5_0_sram[0]:10 mux_tree_tapbuf_size5_0_sram[0]:9 0.0045 +12 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:8 0.002955357 +13 mux_tree_tapbuf_size5_0_sram[0]:7 mux_tree_tapbuf_size5_0_sram[0]:6 0.0008370536 +14 mux_tree_tapbuf_size5_0_sram[0]:8 mux_tree_tapbuf_size5_0_sram[0]:7 0.0045 +15 mux_tree_tapbuf_size5_0_sram[0]:6 mux_right_track_2\/mux_l1_in_1_:S 0.152 +16 mux_tree_tapbuf_size5_0_sram[0]:4 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +17 mux_tree_tapbuf_size5_0_sram[0]:5 mux_right_track_2\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:10 0.004799108 +19 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:5 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[0] 0.006167457 //LENGTH 45.660 LUMPCC 0.0006604983 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.945 15.300 +*I mux_left_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 73.700 25.160 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 62.460 30.940 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 53.535 37.060 +*N mux_tree_tapbuf_size5_3_sram[0]:4 *C 53.573 37.060 +*N mux_tree_tapbuf_size5_3_sram[0]:5 *C 62.055 37.060 +*N mux_tree_tapbuf_size5_3_sram[0]:6 *C 62.100 37.015 +*N mux_tree_tapbuf_size5_3_sram[0]:7 *C 62.445 30.940 +*N mux_tree_tapbuf_size5_3_sram[0]:8 *C 62.123 30.940 +*N mux_tree_tapbuf_size5_3_sram[0]:9 *C 62.100 30.940 +*N mux_tree_tapbuf_size5_3_sram[0]:10 *C 73.663 25.160 +*N mux_tree_tapbuf_size5_3_sram[0]:11 *C 62.145 25.160 +*N mux_tree_tapbuf_size5_3_sram[0]:12 *C 62.100 25.205 +*N mux_tree_tapbuf_size5_3_sram[0]:13 *C 62.100 26.180 +*N mux_tree_tapbuf_size5_3_sram[0]:14 *C 61.640 26.180 +*N mux_tree_tapbuf_size5_3_sram[0]:15 *C 61.640 15.345 +*N mux_tree_tapbuf_size5_3_sram[0]:16 *C 61.640 15.300 +*N mux_tree_tapbuf_size5_3_sram[0]:17 *C 61.945 15.300 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_1\/mux_l1_in_1_:S 1e-06 +2 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +3 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_3_sram[0]:4 0.0003781898 +5 mux_tree_tapbuf_size5_3_sram[0]:5 0.0003781898 +6 mux_tree_tapbuf_size5_3_sram[0]:6 0.0003353833 +7 mux_tree_tapbuf_size5_3_sram[0]:7 6.024071e-05 +8 mux_tree_tapbuf_size5_3_sram[0]:8 6.024071e-05 +9 mux_tree_tapbuf_size5_3_sram[0]:9 0.0006611582 +10 mux_tree_tapbuf_size5_3_sram[0]:10 0.0008932645 +11 mux_tree_tapbuf_size5_3_sram[0]:11 0.0008932645 +12 mux_tree_tapbuf_size5_3_sram[0]:12 8.51626e-05 +13 mux_tree_tapbuf_size5_3_sram[0]:13 0.0004060988 +14 mux_tree_tapbuf_size5_3_sram[0]:14 0.0006396633 +15 mux_tree_tapbuf_size5_3_sram[0]:15 0.0006093174 +16 mux_tree_tapbuf_size5_3_sram[0]:16 5.329704e-05 +17 mux_tree_tapbuf_size5_3_sram[0]:17 4.948847e-05 +18 mux_tree_tapbuf_size5_3_sram[0]:5 chanx_left_in[10]:40 0.0003302491 +19 mux_tree_tapbuf_size5_3_sram[0]:4 chanx_left_in[10]:41 0.0003302491 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_3_sram[0]:17 0.152 +1 mux_tree_tapbuf_size5_3_sram[0]:5 mux_tree_tapbuf_size5_3_sram[0]:4 0.007573661 +2 mux_tree_tapbuf_size5_3_sram[0]:6 mux_tree_tapbuf_size5_3_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size5_3_sram[0]:4 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size5_3_sram[0]:11 mux_tree_tapbuf_size5_3_sram[0]:10 0.01028348 +5 mux_tree_tapbuf_size5_3_sram[0]:12 mux_tree_tapbuf_size5_3_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size5_3_sram[0]:10 mux_left_track_1\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size5_3_sram[0]:7 mux_left_track_1\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_3_sram[0]:8 mux_tree_tapbuf_size5_3_sram[0]:7 0.0001752718 +9 mux_tree_tapbuf_size5_3_sram[0]:9 mux_tree_tapbuf_size5_3_sram[0]:8 0.0045 +10 mux_tree_tapbuf_size5_3_sram[0]:9 mux_tree_tapbuf_size5_3_sram[0]:6 0.005424107 +11 mux_tree_tapbuf_size5_3_sram[0]:16 mux_tree_tapbuf_size5_3_sram[0]:15 0.0045 +12 mux_tree_tapbuf_size5_3_sram[0]:15 mux_tree_tapbuf_size5_3_sram[0]:14 0.009674108 +13 mux_tree_tapbuf_size5_3_sram[0]:17 mux_tree_tapbuf_size5_3_sram[0]:16 0.0001657609 +14 mux_tree_tapbuf_size5_3_sram[0]:14 mux_tree_tapbuf_size5_3_sram[0]:13 0.0004107143 +15 mux_tree_tapbuf_size5_3_sram[0]:13 mux_tree_tapbuf_size5_3_sram[0]:12 0.0008705358 +16 mux_tree_tapbuf_size5_3_sram[0]:13 mux_tree_tapbuf_size5_3_sram[0]:9 0.00425 + +*END + +*D_NET mux_tree_tapbuf_size5_6_sram[0] 0.003598426 //LENGTH 30.535 LUMPCC 0.0003324639 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.985 80.240 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 52.155 77.180 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 59.440 82.960 +*I mux_left_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 62.660 72.080 +*N mux_tree_tapbuf_size5_6_sram[0]:4 *C 62.623 72.080 +*N mux_tree_tapbuf_size5_6_sram[0]:5 *C 58.465 72.080 +*N mux_tree_tapbuf_size5_6_sram[0]:6 *C 58.420 72.125 +*N mux_tree_tapbuf_size5_6_sram[0]:7 *C 59.403 82.960 +*N mux_tree_tapbuf_size5_6_sram[0]:8 *C 58.005 82.960 +*N mux_tree_tapbuf_size5_6_sram[0]:9 *C 57.960 82.915 +*N mux_tree_tapbuf_size5_6_sram[0]:10 *C 57.960 79.900 +*N mux_tree_tapbuf_size5_6_sram[0]:11 *C 58.420 79.855 +*N mux_tree_tapbuf_size5_6_sram[0]:12 *C 58.375 79.900 +*N mux_tree_tapbuf_size5_6_sram[0]:13 *C 52.155 77.180 +*N mux_tree_tapbuf_size5_6_sram[0]:14 *C 52.440 77.180 +*N mux_tree_tapbuf_size5_6_sram[0]:15 *C 52.440 77.225 +*N mux_tree_tapbuf_size5_6_sram[0]:16 *C 52.440 79.855 +*N mux_tree_tapbuf_size5_6_sram[0]:17 *C 52.440 79.900 +*N mux_tree_tapbuf_size5_6_sram[0]:18 *C 50.140 79.900 +*N mux_tree_tapbuf_size5_6_sram[0]:19 *C 49.985 80.240 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_6_sram[0]:4 0.0002779957 +5 mux_tree_tapbuf_size5_6_sram[0]:5 0.0002779957 +6 mux_tree_tapbuf_size5_6_sram[0]:6 0.0003973977 +7 mux_tree_tapbuf_size5_6_sram[0]:7 0.0001161333 +8 mux_tree_tapbuf_size5_6_sram[0]:8 0.0001161333 +9 mux_tree_tapbuf_size5_6_sram[0]:9 0.0001837213 +10 mux_tree_tapbuf_size5_6_sram[0]:10 0.0001874434 +11 mux_tree_tapbuf_size5_6_sram[0]:11 0.0004011197 +12 mux_tree_tapbuf_size5_6_sram[0]:12 0.0002663574 +13 mux_tree_tapbuf_size5_6_sram[0]:13 4.910372e-05 +14 mux_tree_tapbuf_size5_6_sram[0]:14 5.354126e-05 +15 mux_tree_tapbuf_size5_6_sram[0]:15 0.0001659329 +16 mux_tree_tapbuf_size5_6_sram[0]:16 0.0001659329 +17 mux_tree_tapbuf_size5_6_sram[0]:17 0.0004094628 +18 mux_tree_tapbuf_size5_6_sram[0]:18 0.0001372378 +19 mux_tree_tapbuf_size5_6_sram[0]:19 5.645347e-05 +20 mux_tree_tapbuf_size5_6_sram[0]:12 mem_left_track_33/net_net_98:8 0.00010241 +21 mux_tree_tapbuf_size5_6_sram[0]:11 mem_left_track_33/net_net_98:8 2.700614e-05 +22 mux_tree_tapbuf_size5_6_sram[0]:17 mem_left_track_33/net_net_98:7 0.00010241 +23 mux_tree_tapbuf_size5_6_sram[0]:17 mem_left_track_33/net_net_98:8 3.681577e-05 +24 mux_tree_tapbuf_size5_6_sram[0]:18 mem_left_track_33/net_net_98:7 3.681577e-05 +25 mux_tree_tapbuf_size5_6_sram[0]:10 mem_left_track_33/net_net_98:7 2.700614e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_6_sram[0]:19 0.152 +1 mux_tree_tapbuf_size5_6_sram[0]:7 mux_left_track_25\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_6_sram[0]:8 mux_tree_tapbuf_size5_6_sram[0]:7 0.001247768 +3 mux_tree_tapbuf_size5_6_sram[0]:9 mux_tree_tapbuf_size5_6_sram[0]:8 0.0045 +4 mux_tree_tapbuf_size5_6_sram[0]:5 mux_tree_tapbuf_size5_6_sram[0]:4 0.003712054 +5 mux_tree_tapbuf_size5_6_sram[0]:6 mux_tree_tapbuf_size5_6_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size5_6_sram[0]:4 mux_left_track_25\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size5_6_sram[0]:12 mux_tree_tapbuf_size5_6_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size5_6_sram[0]:11 mux_tree_tapbuf_size5_6_sram[0]:10 0.0004107143 +9 mux_tree_tapbuf_size5_6_sram[0]:11 mux_tree_tapbuf_size5_6_sram[0]:6 0.006901787 +10 mux_tree_tapbuf_size5_6_sram[0]:17 mux_tree_tapbuf_size5_6_sram[0]:16 0.0045 +11 mux_tree_tapbuf_size5_6_sram[0]:17 mux_tree_tapbuf_size5_6_sram[0]:12 0.005299107 +12 mux_tree_tapbuf_size5_6_sram[0]:16 mux_tree_tapbuf_size5_6_sram[0]:15 0.002348214 +13 mux_tree_tapbuf_size5_6_sram[0]:14 mux_tree_tapbuf_size5_6_sram[0]:13 0.0001548913 +14 mux_tree_tapbuf_size5_6_sram[0]:15 mux_tree_tapbuf_size5_6_sram[0]:14 0.0045 +15 mux_tree_tapbuf_size5_6_sram[0]:13 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +16 mux_tree_tapbuf_size5_6_sram[0]:19 mux_tree_tapbuf_size5_6_sram[0]:18 0.0003035715 +17 mux_tree_tapbuf_size5_6_sram[0]:18 mux_tree_tapbuf_size5_6_sram[0]:17 0.002053572 +18 mux_tree_tapbuf_size5_6_sram[0]:10 mux_tree_tapbuf_size5_6_sram[0]:9 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.003783165 //LENGTH 32.360 LUMPCC 0.0006552476 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 100.585 82.620 +*I mux_right_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 112.140 79.560 +*I mem_right_track_0\/FTB_1__26:A I *L 0.001746 *C 90.620 88.400 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 90.657 88.400 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 99.775 88.400 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 99.820 88.355 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 112.103 79.560 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 99.865 79.560 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 99.820 79.605 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 99.820 82.620 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 99.865 82.620 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 100.547 82.620 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:S 1e-06 +2 mem_right_track_0\/FTB_1__26:A 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 0.0003133519 +4 mux_tree_tapbuf_size6_0_sram[2]:4 0.0003133519 +5 mux_tree_tapbuf_size6_0_sram[2]:5 0.000292174 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0007013289 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0007013289 +8 mux_tree_tapbuf_size6_0_sram[2]:8 0.0001734353 +9 mux_tree_tapbuf_size6_0_sram[2]:9 0.0004976612 +10 mux_tree_tapbuf_size6_0_sram[2]:10 6.614299e-05 +11 mux_tree_tapbuf_size6_0_sram[2]:11 6.614299e-05 +12 mux_tree_tapbuf_size6_0_sram[2]:4 chanx_right_in[10]:23 0.0001928057 +13 mux_tree_tapbuf_size6_0_sram[2]:3 chanx_right_in[10]:22 0.0001928057 +14 mux_tree_tapbuf_size6_0_sram[2]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.678483e-05 +15 mux_tree_tapbuf_size6_0_sram[2]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.80333e-05 +16 mux_tree_tapbuf_size6_0_sram[2]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.80333e-05 +17 mux_tree_tapbuf_size6_0_sram[2]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.678483e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:11 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:4 mux_tree_tapbuf_size6_0_sram[2]:3 0.008140625 +2 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0045 +3 mux_tree_tapbuf_size6_0_sram[2]:3 mem_right_track_0\/FTB_1__26:A 0.152 +4 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.0045 +5 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:8 0.002691964 +6 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:5 0.005120536 +7 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.000609375 +8 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.01092634 +9 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +10 mux_tree_tapbuf_size6_0_sram[2]:6 mux_right_track_0\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[2] 0.002145426 //LENGTH 17.165 LUMPCC 0.0002736892 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 57.345 55.760 +*I mux_left_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 54.380 53.040 +*I mem_left_track_9\/FTB_5__30:A I *L 0.001746 *C 49.680 58.480 +*N mux_tree_tapbuf_size6_4_sram[2]:3 *C 49.718 58.480 +*N mux_tree_tapbuf_size6_4_sram[2]:4 *C 54.280 58.480 +*N mux_tree_tapbuf_size6_4_sram[2]:5 *C 54.280 53.040 +*N mux_tree_tapbuf_size6_4_sram[2]:6 *C 54.280 53.085 +*N mux_tree_tapbuf_size6_4_sram[2]:7 *C 54.280 58.095 +*N mux_tree_tapbuf_size6_4_sram[2]:8 *C 54.280 58.140 +*N mux_tree_tapbuf_size6_4_sram[2]:9 *C 55.615 58.140 +*N mux_tree_tapbuf_size6_4_sram[2]:10 *C 55.660 58.095 +*N mux_tree_tapbuf_size6_4_sram[2]:11 *C 55.660 55.805 +*N mux_tree_tapbuf_size6_4_sram[2]:12 *C 55.705 55.760 +*N mux_tree_tapbuf_size6_4_sram[2]:13 *C 57.308 55.760 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_9\/FTB_5__30:A 1e-06 +3 mux_tree_tapbuf_size6_4_sram[2]:3 0.0002825293 +4 mux_tree_tapbuf_size6_4_sram[2]:4 0.0003108752 +5 mux_tree_tapbuf_size6_4_sram[2]:5 3.324143e-05 +6 mux_tree_tapbuf_size6_4_sram[2]:6 0.0001966095 +7 mux_tree_tapbuf_size6_4_sram[2]:7 0.0001966095 +8 mux_tree_tapbuf_size6_4_sram[2]:8 0.0001240381 +9 mux_tree_tapbuf_size6_4_sram[2]:9 9.569212e-05 +10 mux_tree_tapbuf_size6_4_sram[2]:10 0.0001559799 +11 mux_tree_tapbuf_size6_4_sram[2]:11 0.0001559799 +12 mux_tree_tapbuf_size6_4_sram[2]:12 0.0001585909 +13 mux_tree_tapbuf_size6_4_sram[2]:13 0.0001585909 +14 mux_tree_tapbuf_size6_4_sram[2]:7 chanx_left_in[13]:30 0.0001367107 +15 mux_tree_tapbuf_size6_4_sram[2]:6 chanx_left_in[13]:29 0.0001367107 +16 mux_tree_tapbuf_size6_4_sram[2]:10 chanx_left_in[13]:30 1.338834e-07 +17 mux_tree_tapbuf_size6_4_sram[2]:11 chanx_left_in[13]:29 1.338834e-07 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_4_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_4_sram[2]:3 mem_left_track_9\/FTB_5__30:A 0.152 +2 mux_tree_tapbuf_size6_4_sram[2]:8 mux_tree_tapbuf_size6_4_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size6_4_sram[2]:8 mux_tree_tapbuf_size6_4_sram[2]:4 0.0003035715 +4 mux_tree_tapbuf_size6_4_sram[2]:7 mux_tree_tapbuf_size6_4_sram[2]:6 0.004473215 +5 mux_tree_tapbuf_size6_4_sram[2]:5 mux_left_track_9\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size6_4_sram[2]:6 mux_tree_tapbuf_size6_4_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size6_4_sram[2]:9 mux_tree_tapbuf_size6_4_sram[2]:8 0.001191964 +8 mux_tree_tapbuf_size6_4_sram[2]:10 mux_tree_tapbuf_size6_4_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size6_4_sram[2]:12 mux_tree_tapbuf_size6_4_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size6_4_sram[2]:11 mux_tree_tapbuf_size6_4_sram[2]:10 0.002044643 +11 mux_tree_tapbuf_size6_4_sram[2]:13 mux_tree_tapbuf_size6_4_sram[2]:12 0.001430804 +12 mux_tree_tapbuf_size6_4_sram[2]:4 mux_tree_tapbuf_size6_4_sram[2]:3 0.004073661 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[1] 0.003462767 //LENGTH 27.725 LUMPCC 0.0001838599 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 40.325 23.120 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 41.760 19.720 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 35.135 11.900 +*I mux_bottom_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 38.520 29.240 +*N mux_tree_tapbuf_size7_0_sram[1]:4 *C 38.520 29.240 +*N mux_tree_tapbuf_size7_0_sram[1]:5 *C 38.640 29.195 +*N mux_tree_tapbuf_size7_0_sram[1]:6 *C 35.172 11.900 +*N mux_tree_tapbuf_size7_0_sram[1]:7 *C 36.295 11.900 +*N mux_tree_tapbuf_size7_0_sram[1]:8 *C 36.340 11.945 +*N mux_tree_tapbuf_size7_0_sram[1]:9 *C 36.340 17.295 +*N mux_tree_tapbuf_size7_0_sram[1]:10 *C 36.385 17.340 +*N mux_tree_tapbuf_size7_0_sram[1]:11 *C 38.595 17.340 +*N mux_tree_tapbuf_size7_0_sram[1]:12 *C 38.640 17.385 +*N mux_tree_tapbuf_size7_0_sram[1]:13 *C 41.723 19.720 +*N mux_tree_tapbuf_size7_0_sram[1]:14 *C 38.685 19.720 +*N mux_tree_tapbuf_size7_0_sram[1]:15 *C 38.640 19.720 +*N mux_tree_tapbuf_size7_0_sram[1]:16 *C 38.640 23.120 +*N mux_tree_tapbuf_size7_0_sram[1]:17 *C 39.100 23.120 +*N mux_tree_tapbuf_size7_0_sram[1]:18 *C 39.145 23.120 +*N mux_tree_tapbuf_size7_0_sram[1]:19 *C 40.288 23.120 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_1\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_0_sram[1]:4 3.164864e-05 +5 mux_tree_tapbuf_size7_0_sram[1]:5 0.0003141865 +6 mux_tree_tapbuf_size7_0_sram[1]:6 9.638045e-05 +7 mux_tree_tapbuf_size7_0_sram[1]:7 9.638045e-05 +8 mux_tree_tapbuf_size7_0_sram[1]:8 0.0003746659 +9 mux_tree_tapbuf_size7_0_sram[1]:9 0.0003746659 +10 mux_tree_tapbuf_size7_0_sram[1]:10 0.0001517049 +11 mux_tree_tapbuf_size7_0_sram[1]:11 0.0001517049 +12 mux_tree_tapbuf_size7_0_sram[1]:12 0.000147073 +13 mux_tree_tapbuf_size7_0_sram[1]:13 0.0001993368 +14 mux_tree_tapbuf_size7_0_sram[1]:14 0.0001993368 +15 mux_tree_tapbuf_size7_0_sram[1]:15 0.0003494187 +16 mux_tree_tapbuf_size7_0_sram[1]:16 0.0005142897 +17 mux_tree_tapbuf_size7_0_sram[1]:17 6.093876e-05 +18 mux_tree_tapbuf_size7_0_sram[1]:18 0.0001065875 +19 mux_tree_tapbuf_size7_0_sram[1]:19 0.0001065875 +20 mux_tree_tapbuf_size7_0_sram[1]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 2.480479e-05 +21 mux_tree_tapbuf_size7_0_sram[1]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.876998e-05 +22 mux_tree_tapbuf_size7_0_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.346518e-05 +23 mux_tree_tapbuf_size7_0_sram[1]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 4.889981e-06 +24 mux_tree_tapbuf_size7_0_sram[1]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.876998e-05 +25 mux_tree_tapbuf_size7_0_sram[1]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.346518e-05 +26 mux_tree_tapbuf_size7_0_sram[1]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.480479e-05 +27 mux_tree_tapbuf_size7_0_sram[1]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 4.889981e-06 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_0_sram[1]:19 0.152 +1 mux_tree_tapbuf_size7_0_sram[1]:4 mux_bottom_track_1\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_0_sram[1]:5 mux_tree_tapbuf_size7_0_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size7_0_sram[1]:18 mux_tree_tapbuf_size7_0_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size7_0_sram[1]:17 mux_tree_tapbuf_size7_0_sram[1]:16 0.0004107143 +5 mux_tree_tapbuf_size7_0_sram[1]:19 mux_tree_tapbuf_size7_0_sram[1]:18 0.001020089 +6 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:13 0.002712054 +7 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:12 0.002084822 +9 mux_tree_tapbuf_size7_0_sram[1]:13 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size7_0_sram[1]:11 mux_tree_tapbuf_size7_0_sram[1]:10 0.001973214 +11 mux_tree_tapbuf_size7_0_sram[1]:12 mux_tree_tapbuf_size7_0_sram[1]:11 0.0045 +12 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:9 0.0045 +13 mux_tree_tapbuf_size7_0_sram[1]:9 mux_tree_tapbuf_size7_0_sram[1]:8 0.004776786 +14 mux_tree_tapbuf_size7_0_sram[1]:7 mux_tree_tapbuf_size7_0_sram[1]:6 0.001002232 +15 mux_tree_tapbuf_size7_0_sram[1]:8 mux_tree_tapbuf_size7_0_sram[1]:7 0.0045 +16 mux_tree_tapbuf_size7_0_sram[1]:6 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +17 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:15 0.003035715 +18 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:5 0.005424107 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_0_ccff_tail[0] 0.00125663 //LENGTH 9.990 LUMPCC 0.0004386726 DR + +*CONN +*I mem_bottom_track_1\/FTB_20__45:X O *L 0 *C 33.765 7.140 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 32.835 15.300 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 *C 32.835 15.300 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 *C 33.105 15.300 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 *C 33.120 15.255 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 *C 33.120 7.185 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 *C 33.165 7.140 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 *C 33.727 7.140 + +*CAP +0 mem_bottom_track_1\/FTB_20__45:X 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 8.117167e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 4.394757e-05 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0002935031 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0002935031 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 5.191584e-05 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 5.191584e-05 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 prog_clk[0]:552 4.184569e-06 +9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 prog_clk[0]:558 8.170443e-05 +10 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 prog_clk[0]:559 0.0001334473 +11 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 prog_clk[0]:546 4.184569e-06 +12 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 prog_clk[0]:552 8.170443e-05 +13 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 prog_clk[0]:558 0.0001334473 + +*RES +0 mem_bottom_track_1\/FTB_20__45:X mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.0005022322 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.007205357 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 0.0001298077 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET optlc_net_163 0.002909767 //LENGTH 21.680 LUMPCC 0.0003001783 DR + +*CONN +*I optlc_151:HI O *L 0 *C 80.040 37.400 +*I mux_bottom_track_21\/mux_l1_in_1_:A0 I *L 0.001631 *C 79.295 31.620 +*I mux_bottom_track_23\/mux_l1_in_1_:A0 I *L 0.001631 *C 87.575 42.840 +*N optlc_net_163:3 *C 87.538 42.840 +*N optlc_net_163:4 *C 79.625 42.840 +*N optlc_net_163:5 *C 79.580 42.795 +*N optlc_net_163:6 *C 79.580 37.495 +*N optlc_net_163:7 *C 79.295 31.620 +*N optlc_net_163:8 *C 79.120 31.620 +*N optlc_net_163:9 *C 79.120 31.665 +*N optlc_net_163:10 *C 79.120 37.060 +*N optlc_net_163:11 *C 79.535 37.060 +*N optlc_net_163:12 *C 79.580 37.525 +*N optlc_net_163:13 *C 79.625 37.400 +*N optlc_net_163:14 *C 80.002 37.400 + +*CAP +0 optlc_151:HI 1e-06 +1 mux_bottom_track_21\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_23\/mux_l1_in_1_:A0 1e-06 +3 optlc_net_163:3 0.0005273124 +4 optlc_net_163:4 0.0005273124 +5 optlc_net_163:5 0.0002827666 +6 optlc_net_163:6 1.542914e-05 +7 optlc_net_163:7 5.59845e-05 +8 optlc_net_163:8 5.524229e-05 +9 optlc_net_163:9 0.0003124402 +10 optlc_net_163:10 0.0003433579 +11 optlc_net_163:11 5.349408e-05 +12 optlc_net_163:12 0.0003207722 +13 optlc_net_163:13 5.623857e-05 +14 optlc_net_163:14 5.623857e-05 +15 optlc_net_163:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.44913e-05 +16 optlc_net_163:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.44913e-05 +17 optlc_net_163:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.012474e-05 +18 optlc_net_163:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.547312e-05 +19 optlc_net_163:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.012474e-05 +20 optlc_net_163:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.547312e-05 + +*RES +0 optlc_151:HI optlc_net_163:14 0.152 +1 optlc_net_163:4 optlc_net_163:3 0.007064732 +2 optlc_net_163:5 optlc_net_163:4 0.0045 +3 optlc_net_163:3 mux_bottom_track_23\/mux_l1_in_1_:A0 0.152 +4 optlc_net_163:13 optlc_net_163:12 0.0045 +5 optlc_net_163:12 optlc_net_163:11 0.0002906251 +6 optlc_net_163:12 optlc_net_163:6 1.875e-05 +7 optlc_net_163:12 optlc_net_163:5 0.004705357 +8 optlc_net_163:14 optlc_net_163:13 0.0003370536 +9 optlc_net_163:8 optlc_net_163:7 9.51087e-05 +10 optlc_net_163:9 optlc_net_163:8 0.0045 +11 optlc_net_163:7 mux_bottom_track_21\/mux_l1_in_1_:A0 0.152 +12 optlc_net_163:10 optlc_net_163:9 0.004816964 +13 optlc_net_163:11 optlc_net_163:10 0.0003705357 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005042008 //LENGTH 3.330 LUMPCC 0 DR + +*CONN +*I mux_right_track_4\/mux_l1_in_2_:X O *L 0 *C 102.405 58.820 +*I mux_right_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 102.680 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 102.580 61.540 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 102.580 61.495 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 102.580 58.865 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 102.580 58.820 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 102.405 58.820 + +*CAP +0 mux_right_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.169265e-05 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000176516 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000176516 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.886471e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.861137e-05 + +*RES +0 mux_right_track_4\/mux_l1_in_2_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002348214 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001117606 //LENGTH 7.840 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l2_in_0_:X O *L 0 *C 107.925 55.420 +*I mux_right_track_8\/mux_l3_in_0_:A1 I *L 0.005458 *C 115.620 55.483 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 107.963 55.420 + +*CAP +0 mux_right_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_8\/mux_l3_in_0_:A1 0.0005583032 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005583032 + +*RES +0 mux_right_track_8\/mux_l2_in_0_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_8\/mux_l3_in_0_:A1 0.006837054 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007095727 //LENGTH 4.240 LUMPCC 0.0004383429 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_2_:X O *L 0 *C 50.775 45.220 +*I mux_left_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 46.825 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 46.863 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 50.738 45.220 + +*CAP +0 mux_left_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001346149 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001346149 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chanx_right_in[6]:13 0.0001546415 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chanx_right_in[6]:14 0.0001546415 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size6_3_sram[1]:12 6.452991e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_3_sram[1]:13 6.452991e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003459821 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0003387523 //LENGTH 2.305 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_2_:X O *L 0 *C 60.895 50.660 +*I mux_left_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 58.880 50.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 58.918 50.660 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 60.858 50.660 + +*CAP +0 mux_left_track_9\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001683762 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001683762 + +*RES +0 mux_left_track_9\/mux_l1_in_2_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001732143 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_9\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007648735 //LENGTH 5.545 LUMPCC 0.0003471942 DR + +*CONN +*I mux_right_track_2\/mux_l1_in_0_:X O *L 0 *C 68.365 63.580 +*I mux_right_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 70.940 61.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 70.903 61.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 69.965 61.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 69.920 61.585 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 69.920 63.535 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 69.875 63.580 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 68.403 63.580 + +*CAP +0 mux_right_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.833681e-05 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.833681e-05 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.739833e-05 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.739833e-05 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.21045e-05 +7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.21045e-05 +8 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_right_in[5]:25 6.026325e-05 +9 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_right_in[5]:24 6.026325e-05 +10 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size5_0_sram[0]:12 6.953452e-05 +11 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size5_0_sram[0]:11 6.953452e-05 +12 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.585436e-05 +13 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.585436e-05 +14 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.794497e-05 +15 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.794497e-05 + +*RES +0 mux_right_track_2\/mux_l1_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741071 +6 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001812284 //LENGTH 13.525 LUMPCC 0.0004298177 DR + +*CONN +*I mux_right_track_16\/mux_l2_in_0_:X O *L 0 *C 88.145 45.220 +*I mux_right_track_16\/mux_l3_in_0_:A1 I *L 0.00198 *C 92.560 52.700 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 92.523 52.700 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 91.585 52.700 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 91.540 52.655 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 91.540 47.657 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 91.532 47.600 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 89.248 47.600 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 89.240 47.543 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 89.240 45.265 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 89.195 45.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 88.183 45.220 + +*CAP +0 mux_right_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 8.868022e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.868022e-05 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002338869 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002338869 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001009254 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001009254 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001579886 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001579886 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001087521 +11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001087521 +12 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_left_in[8]:8 0.0001439221 +13 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[8]:15 0.0001439221 +14 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[9]:17 3.95115e-05 +15 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_left_in[9]:18 2.331319e-05 +16 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_left_in[9]:6 3.95115e-05 +17 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_left_in[9]:17 2.331319e-05 +18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_left_in[9]:15 8.162073e-06 +19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[9]:16 8.162073e-06 + +*RES +0 mux_right_track_16\/mux_l2_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_16\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0008370535 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004462054 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003579833 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002033482 +10 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_right_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0009040179 + +*END + +*D_NET optlc_net_165 0.01143209 //LENGTH 88.485 LUMPCC 0.0008948238 DR + +*CONN +*I optlc_155:HI O *L 0 *C 52.440 31.280 +*I mux_bottom_track_39\/mux_l2_in_0_:A0 I *L 0.001631 *C 52.615 10.200 +*I mux_bottom_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 53.075 22.780 +*I mux_bottom_track_13\/mux_l1_in_1_:A0 I *L 0.001631 *C 42.955 37.060 +*I mux_bottom_track_1\/mux_l1_in_3_:A0 I *L 0.001631 *C 38.355 33.320 +*I mux_bottom_track_19\/mux_l1_in_1_:A0 I *L 0.001631 *C 58.710 27.880 +*I mux_left_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 59.055 42.500 +*I mux_left_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 47.210 44.200 +*I mux_bottom_track_15\/mux_l1_in_1_:A0 I *L 0.001631 *C 56.870 31.620 +*N optlc_net_165:9 *C 56.870 31.620 +*N optlc_net_165:10 *C 47.248 44.200 +*N optlc_net_165:11 *C 50.095 44.200 +*N optlc_net_165:12 *C 50.140 44.155 +*N optlc_net_165:13 *C 50.140 42.885 +*N optlc_net_165:14 *C 50.185 42.840 +*N optlc_net_165:15 *C 56.580 42.840 +*N optlc_net_165:16 *C 59.018 42.500 +*N optlc_net_165:17 *C 56.580 42.500 +*N optlc_net_165:18 *C 56.580 42.455 +*N optlc_net_165:19 *C 58.672 27.880 +*N optlc_net_165:20 *C 56.625 27.880 +*N optlc_net_165:21 *C 56.580 27.925 +*N optlc_net_165:22 *C 56.580 31.620 +*N optlc_net_165:23 *C 56.535 31.620 +*N optlc_net_165:24 *C 38.392 33.320 +*N optlc_net_165:25 *C 42.992 37.060 +*N optlc_net_165:26 *C 43.655 37.060 +*N optlc_net_165:27 *C 43.700 37.015 +*N optlc_net_165:28 *C 43.700 33.365 +*N optlc_net_165:29 *C 43.700 33.320 +*N optlc_net_165:30 *C 45.955 33.320 +*N optlc_net_165:31 *C 46.000 33.275 +*N optlc_net_165:32 *C 53.038 22.780 +*N optlc_net_165:33 *C 52.615 10.200 +*N optlc_net_165:34 *C 52.440 10.200 +*N optlc_net_165:35 *C 52.440 10.245 +*N optlc_net_165:36 *C 52.440 22.735 +*N optlc_net_165:37 *C 52.440 22.780 +*N optlc_net_165:38 *C 46.045 22.780 +*N optlc_net_165:39 *C 46.000 22.825 +*N optlc_net_165:40 *C 46.000 31.620 +*N optlc_net_165:41 *C 46.045 31.620 +*N optlc_net_165:42 *C 52.440 31.620 +*N optlc_net_165:43 *C 52.440 31.280 + +*CAP +0 optlc_155:HI 1e-06 +1 mux_bottom_track_39\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_17\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_13\/mux_l1_in_1_:A0 1e-06 +4 mux_bottom_track_1\/mux_l1_in_3_:A0 1e-06 +5 mux_bottom_track_19\/mux_l1_in_1_:A0 1e-06 +6 mux_left_track_1\/mux_l2_in_1_:A0 1e-06 +7 mux_left_track_5\/mux_l2_in_1_:A0 1e-06 +8 mux_bottom_track_15\/mux_l1_in_1_:A0 1e-06 +9 optlc_net_165:9 4.148326e-05 +10 optlc_net_165:10 0.0002319856 +11 optlc_net_165:11 0.0002319856 +12 optlc_net_165:12 9.477427e-05 +13 optlc_net_165:13 9.477427e-05 +14 optlc_net_165:14 0.0005113317 +15 optlc_net_165:15 0.000542837 +16 optlc_net_165:16 0.0001822278 +17 optlc_net_165:17 0.0002137331 +18 optlc_net_165:18 0.0006249755 +19 optlc_net_165:19 0.0001789782 +20 optlc_net_165:20 0.0001789782 +21 optlc_net_165:21 0.0002111777 +22 optlc_net_165:22 0.0008701516 +23 optlc_net_165:23 0.0001961953 +24 optlc_net_165:24 0.0003795031 +25 optlc_net_165:25 7.635062e-05 +26 optlc_net_165:26 7.635062e-05 +27 optlc_net_165:27 0.0002124718 +28 optlc_net_165:28 0.0002124718 +29 optlc_net_165:29 0.0005735136 +30 optlc_net_165:30 0.0001607274 +31 optlc_net_165:31 9.995876e-05 +32 optlc_net_165:32 4.577413e-05 +33 optlc_net_165:33 5.817355e-05 +34 optlc_net_165:34 6.266462e-05 +35 optlc_net_165:35 0.0006950505 +36 optlc_net_165:36 0.0006950505 +37 optlc_net_165:37 0.000456643 +38 optlc_net_165:38 0.0003788816 +39 optlc_net_165:39 0.0004812171 +40 optlc_net_165:40 0.0006135255 +41 optlc_net_165:41 0.0002845144 +42 optlc_net_165:42 0.0004973486 +43 optlc_net_165:43 6.2488e-05 +44 optlc_net_165:41 chanx_right_in[2]:8 0.0002420248 +45 optlc_net_165:23 chanx_right_in[2]:7 0.0001577718 +46 optlc_net_165:23 chanx_right_in[2]:8 1.35978e-05 +47 optlc_net_165:9 chanx_right_in[2]:7 1.35978e-05 +48 optlc_net_165:42 chanx_right_in[2]:7 0.0002420248 +49 optlc_net_165:42 chanx_right_in[2]:8 0.0001577718 +50 optlc_net_165:22 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.357699e-05 +51 optlc_net_165:20 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.405194e-07 +52 optlc_net_165:21 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.357699e-05 +53 optlc_net_165:19 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.405194e-07 + +*RES +0 optlc_155:HI optlc_net_165:43 0.152 +1 optlc_net_165:38 optlc_net_165:37 0.005709821 +2 optlc_net_165:39 optlc_net_165:38 0.0045 +3 optlc_net_165:41 optlc_net_165:40 0.0045 +4 optlc_net_165:40 optlc_net_165:39 0.007852679 +5 optlc_net_165:40 optlc_net_165:31 0.001477679 +6 optlc_net_165:23 optlc_net_165:22 0.0045 +7 optlc_net_165:23 optlc_net_165:9 0.0001820652 +8 optlc_net_165:22 optlc_net_165:21 0.003299108 +9 optlc_net_165:22 optlc_net_165:18 0.009674108 +10 optlc_net_165:30 optlc_net_165:29 0.002013393 +11 optlc_net_165:31 optlc_net_165:30 0.0045 +12 optlc_net_165:17 optlc_net_165:16 0.002176339 +13 optlc_net_165:17 optlc_net_165:15 0.0003035715 +14 optlc_net_165:18 optlc_net_165:17 0.0045 +15 optlc_net_165:43 optlc_net_165:42 0.0003035714 +16 optlc_net_165:16 mux_left_track_1\/mux_l2_in_1_:A0 0.152 +17 optlc_net_165:37 optlc_net_165:36 0.0045 +18 optlc_net_165:37 optlc_net_165:32 0.0005334821 +19 optlc_net_165:36 optlc_net_165:35 0.01115179 +20 optlc_net_165:34 optlc_net_165:33 9.51087e-05 +21 optlc_net_165:35 optlc_net_165:34 0.0045 +22 optlc_net_165:33 mux_bottom_track_39\/mux_l2_in_0_:A0 0.152 +23 optlc_net_165:32 mux_bottom_track_17\/mux_l1_in_1_:A0 0.152 +24 optlc_net_165:9 mux_bottom_track_15\/mux_l1_in_1_:A0 0.152 +25 optlc_net_165:29 optlc_net_165:28 0.0045 +26 optlc_net_165:29 optlc_net_165:24 0.004738839 +27 optlc_net_165:28 optlc_net_165:27 0.003258929 +28 optlc_net_165:26 optlc_net_165:25 0.0005915178 +29 optlc_net_165:27 optlc_net_165:26 0.0045 +30 optlc_net_165:25 mux_bottom_track_13\/mux_l1_in_1_:A0 0.152 +31 optlc_net_165:24 mux_bottom_track_1\/mux_l1_in_3_:A0 0.152 +32 optlc_net_165:14 optlc_net_165:13 0.0045 +33 optlc_net_165:13 optlc_net_165:12 0.001133929 +34 optlc_net_165:11 optlc_net_165:10 0.002542411 +35 optlc_net_165:12 optlc_net_165:11 0.0045 +36 optlc_net_165:10 mux_left_track_5\/mux_l2_in_1_:A0 0.152 +37 optlc_net_165:20 optlc_net_165:19 0.001828125 +38 optlc_net_165:21 optlc_net_165:20 0.0045 +39 optlc_net_165:19 mux_bottom_track_19\/mux_l1_in_1_:A0 0.152 +40 optlc_net_165:42 optlc_net_165:41 0.005709822 +41 optlc_net_165:42 optlc_net_165:23 0.00365625 +42 optlc_net_165:15 optlc_net_165:14 0.005709822 + +*END + +*D_NET optlc_net_166 0.008093276 //LENGTH 59.725 LUMPCC 0.001105666 DR + +*CONN +*I optlc_157:HI O *L 0 *C 77.740 14.960 +*I mux_bottom_track_37\/mux_l2_in_0_:A0 I *L 0.001631 *C 79.430 4.420 +*I mux_bottom_track_27\/mux_l2_in_0_:A0 I *L 0.005103 *C 86.940 4.920 +*I mux_bottom_track_35\/mux_l2_in_0_:A0 I *L 0.001631 *C 66.530 11.560 +*I mux_bottom_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 71.590 17.000 +*I mux_bottom_track_31\/mux_l2_in_0_:A0 I *L 0.001631 *C 87.690 15.300 +*N optlc_net_166:6 *C 87.653 15.300 +*N optlc_net_166:7 *C 77.740 15.300 +*N optlc_net_166:8 *C 71.553 17.000 +*N optlc_net_166:9 *C 66.745 17.000 +*N optlc_net_166:10 *C 66.700 16.955 +*N optlc_net_166:11 *C 66.530 11.560 +*N optlc_net_166:12 *C 66.700 11.560 +*N optlc_net_166:13 *C 66.700 11.605 +*N optlc_net_166:14 *C 66.700 15.640 +*N optlc_net_166:15 *C 66.745 15.640 +*N optlc_net_166:16 *C 77.740 15.610 +*N optlc_net_166:17 *C 77.740 15.595 +*N optlc_net_166:18 *C 86.903 4.920 +*N optlc_net_166:19 *C 85.100 4.920 +*N optlc_net_166:20 *C 85.100 3.400 +*N optlc_net_166:21 *C 78.660 3.400 +*N optlc_net_166:22 *C 79.392 4.420 +*N optlc_net_166:23 *C 78.660 4.420 +*N optlc_net_166:24 *C 77.785 4.420 +*N optlc_net_166:25 *C 77.740 4.465 +*N optlc_net_166:26 *C 77.740 14.960 +*N optlc_net_166:27 *C 77.280 14.960 +*N optlc_net_166:28 *C 77.325 14.960 +*N optlc_net_166:29 *C 77.703 14.960 + +*CAP +0 optlc_157:HI 1e-06 +1 mux_bottom_track_37\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_27\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_35\/mux_l2_in_0_:A0 1e-06 +4 mux_bottom_track_33\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_track_31\/mux_l2_in_0_:A0 1e-06 +6 optlc_net_166:6 0.0006493332 +7 optlc_net_166:7 0.0006793592 +8 optlc_net_166:8 0.000284053 +9 optlc_net_166:9 0.000284053 +10 optlc_net_166:10 3.784191e-05 +11 optlc_net_166:11 5.529288e-05 +12 optlc_net_166:12 5.971993e-05 +13 optlc_net_166:13 0.0001307188 +14 optlc_net_166:14 0.0002001941 +15 optlc_net_166:15 0.0007828346 +16 optlc_net_166:16 0.0008128606 +17 optlc_net_166:17 4.747131e-05 +18 optlc_net_166:18 0.0001703307 +19 optlc_net_166:19 0.0002600738 +20 optlc_net_166:20 0.0005534063 +21 optlc_net_166:21 0.0005268346 +22 optlc_net_166:22 7.59563e-05 +23 optlc_net_166:23 0.0002007504 +24 optlc_net_166:24 6.162262e-05 +25 optlc_net_166:25 0.000432904 +26 optlc_net_166:26 0.0005147745 +27 optlc_net_166:27 6.706329e-05 +28 optlc_net_166:28 4.707977e-05 +29 optlc_net_166:29 4.707977e-05 +30 optlc_net_166:25 ropt_net_179:7 0.0001098059 +31 optlc_net_166:26 ropt_net_179:8 0.0001098059 +32 optlc_net_166:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.578549e-05 +33 optlc_net_166:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.158388e-05 +34 optlc_net_166:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.972166e-05 +35 optlc_net_166:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.158388e-05 +36 optlc_net_166:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.972166e-05 +37 optlc_net_166:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.578549e-05 +38 optlc_net_166:13 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.595804e-05 +39 optlc_net_166:10 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.065114e-05 +40 optlc_net_166:14 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.065114e-05 +41 optlc_net_166:14 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.595804e-05 +42 optlc_net_166:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:10 2.92423e-05 +43 optlc_net_166:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.476531e-06 +44 optlc_net_166:25 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.369434e-06 +45 optlc_net_166:25 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.711217e-05 +46 optlc_net_166:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.476531e-06 +47 optlc_net_166:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:9 2.92423e-05 +48 optlc_net_166:26 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.711217e-05 +49 optlc_net_166:26 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.369434e-06 +50 optlc_net_166:24 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.803072e-05 +51 optlc_net_166:25 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.809597e-05 +52 optlc_net_166:23 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.803072e-05 +53 optlc_net_166:26 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.809597e-05 + +*RES +0 optlc_157:HI optlc_net_166:29 0.152 +1 optlc_net_166:22 mux_bottom_track_37\/mux_l2_in_0_:A0 0.152 +2 optlc_net_166:18 mux_bottom_track_27\/mux_l2_in_0_:A0 0.152 +3 optlc_net_166:6 mux_bottom_track_31\/mux_l2_in_0_:A0 0.152 +4 optlc_net_166:16 optlc_net_166:15 0.009816964 +5 optlc_net_166:16 optlc_net_166:7 0.0002767858 +6 optlc_net_166:17 optlc_net_166:16 0.0045 +7 optlc_net_166:24 optlc_net_166:23 0.00078125 +8 optlc_net_166:25 optlc_net_166:24 0.0045 +9 optlc_net_166:28 optlc_net_166:27 0.0045 +10 optlc_net_166:27 optlc_net_166:26 0.0004107143 +11 optlc_net_166:29 optlc_net_166:28 0.0003370536 +12 optlc_net_166:12 optlc_net_166:11 9.239131e-05 +13 optlc_net_166:13 optlc_net_166:12 0.0045 +14 optlc_net_166:11 mux_bottom_track_35\/mux_l2_in_0_:A0 0.152 +15 optlc_net_166:9 optlc_net_166:8 0.004292411 +16 optlc_net_166:10 optlc_net_166:9 0.0045 +17 optlc_net_166:8 mux_bottom_track_33\/mux_l2_in_0_:A0 0.152 +18 optlc_net_166:15 optlc_net_166:14 0.0045 +19 optlc_net_166:14 optlc_net_166:13 0.003602679 +20 optlc_net_166:14 optlc_net_166:10 0.001174107 +21 optlc_net_166:23 optlc_net_166:22 0.0006540179 +22 optlc_net_166:23 optlc_net_166:21 0.0009107143 +23 optlc_net_166:7 optlc_net_166:6 0.008850447 +24 optlc_net_166:21 optlc_net_166:20 0.00575 +25 optlc_net_166:20 optlc_net_166:19 0.001357143 +26 optlc_net_166:19 optlc_net_166:18 0.001609375 +27 optlc_net_166:26 optlc_net_166:25 0.009370537 +28 optlc_net_166:26 optlc_net_166:17 0.0005669643 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001387841 //LENGTH 11.180 LUMPCC 0.0003318189 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_3_:X O *L 0 *C 30.645 55.080 +*I mux_bottom_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 33.755 47.940 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 33.718 47.940 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 32.705 47.940 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 32.660 47.985 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 32.660 55.035 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 32.615 55.080 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 30.683 55.080 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.035371e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.035371e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003046136 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003046136 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001320435 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001320435 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:11 5.202463e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:18 2.077051e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:19 8.471756e-06 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:8 3.207094e-06 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:13 2.10088e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:12 5.202463e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:15 2.077051e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:18 8.471756e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:7 3.207094e-06 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:14 2.10088e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.042664e-05 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.042664e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_3_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0009040178 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006294644 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002561691 //LENGTH 20.075 LUMPCC 0.0005190383 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 25.935 61.880 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 16.200 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 16.238 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 20.195 66.980 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 20.240 67.025 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 20.240 68.635 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 20.285 68.680 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 26.175 68.680 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 26.220 68.635 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 26.220 61.925 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 26.220 61.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 25.935 61.880 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001645512 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001645512 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001022559 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001022559 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003322588 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003322588 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0003698934 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0003698934 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.165858e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 5.107576e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size4_0_sram[1]:5 3.215485e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size4_0_sram[1]:6 3.215485e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_0_sram[1]:7 1.060499e-06 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_0_sram[1]:17 3.614044e-06 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size4_0_sram[1]:14 0.0001159826 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_0_sram[1]:8 1.060499e-06 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_0_sram[1]:16 3.614044e-06 +19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size4_0_sram[1]:15 0.0001159826 +20 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size4_0_sram[1]:16 7.268772e-07 +21 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size4_0_sram[1]:17 7.268772e-07 +22 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001059803 +23 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001059803 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003533482 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.005258929 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.005991071 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001548913 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008985939 //LENGTH 6.920 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 93.555 30.600 +*I mux_bottom_track_25\/mux_l3_in_0_:A1 I *L 0.005458 *C 92.125 26.103 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 92.090 26.150 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 26.225 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 30.555 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.045 30.600 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 93.517 30.600 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A1 4.681386e-05 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.681386e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002871676 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002871676 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001148155 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001148155 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001314732 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003866072 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A1 3.365385e-05 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001190875 //LENGTH 10.000 LUMPCC 0.0003246483 DR + +*CONN +*I mux_bottom_track_31\/mux_l1_in_0_:X O *L 0 *C 88.955 22.440 +*I mux_bottom_track_31\/mux_l2_in_0_:A1 I *L 0.00198 *C 87.305 14.620 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 87.305 14.620 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.400 14.665 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 87.400 22.395 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 87.445 22.440 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 88.918 22.440 + +*CAP +0 mux_bottom_track_31\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_31\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.861689e-05 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003464161 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003464161 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.138863e-05 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.138863e-05 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_out[12]:5 9.28962e-05 +8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_out[12]:6 9.28962e-05 +9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 6.942792e-05 +10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 6.942792e-05 + +*RES +0 mux_bottom_track_31\/mux_l1_in_0_:X mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_31\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006901786 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001063621 //LENGTH 8.740 LUMPCC 0.0001722078 DR + +*CONN +*I mux_bottom_track_35\/mux_l2_in_0_:X O *L 0 *C 64.575 11.560 +*I mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 61.450 6.635 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 61.488 6.740 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 62.515 6.800 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 62.560 6.845 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 62.560 11.515 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 62.605 11.560 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 64.538 11.560 + +*CAP +0 mux_bottom_track_35\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.021697e-05 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.021697e-05 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002655518 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002655518 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.893777e-05 +7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.893777e-05 +8 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.610389e-05 +9 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.610389e-05 + +*RES +0 mux_bottom_track_35\/mux_l2_in_0_:X mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009174108 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001725446 + +*END + +*D_NET ropt_net_196 0.000898153 //LENGTH 6.770 LUMPCC 0.000185752 DR + +*CONN +*I FTB_1__0:X O *L 0 *C 12.420 51.000 +*I ropt_mt_inst_816:A I *L 0.001766 *C 7.820 50.320 +*N ropt_net_196:2 *C 7.820 50.320 +*N ropt_net_196:3 *C 7.820 50.660 +*N ropt_net_196:4 *C 12.420 50.660 +*N ropt_net_196:5 *C 12.420 51.000 + +*CAP +0 FTB_1__0:X 1e-06 +1 ropt_mt_inst_816:A 1e-06 +2 ropt_net_196:2 5.893717e-05 +3 ropt_net_196:3 0.0002971389 +4 ropt_net_196:4 0.0002988547 +5 ropt_net_196:5 5.54702e-05 +6 ropt_net_196:2 ropt_net_210:7 7.335813e-07 +7 ropt_net_196:2 ropt_net_210:10 4.956588e-06 +8 ropt_net_196:3 ropt_net_210:6 1.371144e-06 +9 ropt_net_196:3 ropt_net_210:8 2.287294e-05 +10 ropt_net_196:3 ropt_net_210:9 4.956588e-06 +11 ropt_net_196:3 ropt_net_210:10 6.367533e-05 +12 ropt_net_196:4 ropt_net_210:11 6.367533e-05 +13 ropt_net_196:4 ropt_net_210:7 1.371144e-06 +14 ropt_net_196:4 ropt_net_210:9 2.213935e-05 + +*RES +0 FTB_1__0:X ropt_net_196:5 0.152 +1 ropt_net_196:5 ropt_net_196:4 0.0003035715 +2 ropt_net_196:2 ropt_mt_inst_816:A 0.152 +3 ropt_net_196:3 ropt_net_196:2 0.0003035715 +4 ropt_net_196:4 ropt_net_196:3 0.004107143 + +*END + +*D_NET chanx_left_out[19] 0.0009914411 //LENGTH 7.755 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_820:X O *L 0 *C 4.140 90.440 +*P chanx_left_out[19] O *L 0.7423 *C 1.305 88.400 +*N chanx_left_out[19]:2 *C 1.380 89.080 +*N chanx_left_out[19]:3 *C 5.053 89.080 +*N chanx_left_out[19]:4 *C 5.060 89.138 +*N chanx_left_out[19]:5 *C 5.060 90.395 +*N chanx_left_out[19]:6 *C 5.015 90.440 +*N chanx_left_out[19]:7 *C 4.178 90.440 + +*CAP +0 ropt_mt_inst_820:X 1e-06 +1 chanx_left_out[19] 5.034577e-05 +2 chanx_left_out[19]:2 0.0003228071 +3 chanx_left_out[19]:3 0.0002724613 +4 chanx_left_out[19]:4 8.694913e-05 +5 chanx_left_out[19]:5 8.694913e-05 +6 chanx_left_out[19]:6 8.546436e-05 +7 chanx_left_out[19]:7 8.546436e-05 + +*RES +0 ropt_mt_inst_820:X chanx_left_out[19]:7 0.152 +1 chanx_left_out[19]:7 chanx_left_out[19]:6 0.0007477679 +2 chanx_left_out[19]:6 chanx_left_out[19]:5 0.0045 +3 chanx_left_out[19]:5 chanx_left_out[19]:4 0.001122768 +4 chanx_left_out[19]:4 chanx_left_out[19]:3 0.00341 +5 chanx_left_out[19]:3 chanx_left_out[19]:2 0.0005753583 +6 chanx_left_out[19]:2 chanx_left_out[19] 0.0001065333 + +*END + +*D_NET ropt_net_206 0.0009990437 //LENGTH 7.275 LUMPCC 0.0001704069 DR + +*CONN +*I ropt_mt_inst_803:X O *L 0 *C 138.655 80.920 +*I ropt_mt_inst_824:A I *L 0.001767 *C 134.780 82.960 +*N ropt_net_206:2 *C 134.817 82.960 +*N ropt_net_206:3 *C 135.655 82.960 +*N ropt_net_206:4 *C 135.700 82.915 +*N ropt_net_206:5 *C 135.700 82.325 +*N ropt_net_206:6 *C 135.745 82.280 +*N ropt_net_206:7 *C 138.415 82.280 +*N ropt_net_206:8 *C 138.460 82.235 +*N ropt_net_206:9 *C 138.460 80.965 +*N ropt_net_206:10 *C 138.460 80.920 +*N ropt_net_206:11 *C 138.655 80.920 + +*CAP +0 ropt_mt_inst_803:X 1e-06 +1 ropt_mt_inst_824:A 1e-06 +2 ropt_net_206:2 7.176914e-05 +3 ropt_net_206:3 7.176914e-05 +4 ropt_net_206:4 5.765342e-05 +5 ropt_net_206:5 5.765342e-05 +6 ropt_net_206:6 0.0001594757 +7 ropt_net_206:7 0.0001594757 +8 ropt_net_206:8 6.686445e-05 +9 ropt_net_206:9 6.686445e-05 +10 ropt_net_206:10 5.78499e-05 +11 ropt_net_206:11 5.726144e-05 +12 ropt_net_206:8 chanx_left_in[16]:9 4.225602e-05 +13 ropt_net_206:9 chanx_left_in[16]:10 4.225602e-05 +14 ropt_net_206:6 chanx_right_out[3]:5 4.294746e-05 +15 ropt_net_206:7 chanx_right_out[3]:4 4.294746e-05 + +*RES +0 ropt_mt_inst_803:X ropt_net_206:11 0.152 +1 ropt_net_206:2 ropt_mt_inst_824:A 0.152 +2 ropt_net_206:3 ropt_net_206:2 0.0007477679 +3 ropt_net_206:4 ropt_net_206:3 0.0045 +4 ropt_net_206:6 ropt_net_206:5 0.0045 +5 ropt_net_206:5 ropt_net_206:4 0.0005267857 +6 ropt_net_206:7 ropt_net_206:6 0.002383929 +7 ropt_net_206:8 ropt_net_206:7 0.0045 +8 ropt_net_206:10 ropt_net_206:9 0.0045 +9 ropt_net_206:9 ropt_net_206:8 0.001133929 +10 ropt_net_206:11 ropt_net_206:10 0.0001059783 + +*END + +*D_NET chany_bottom_out[0] 0.00112015 //LENGTH 8.115 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_822:X O *L 0 *C 85.100 6.800 +*P chany_bottom_out[0] O *L 0.7423 *C 83.260 1.325 +*N chany_bottom_out[0]:2 *C 83.260 1.655 +*N chany_bottom_out[0]:3 *C 83.305 1.700 +*N chany_bottom_out[0]:4 *C 85.055 1.700 +*N chany_bottom_out[0]:5 *C 85.100 1.745 +*N chany_bottom_out[0]:6 *C 85.100 6.755 +*N chany_bottom_out[0]:7 *C 85.100 6.800 + +*CAP +0 ropt_mt_inst_822:X 1e-06 +1 chany_bottom_out[0] 3.659587e-05 +2 chany_bottom_out[0]:2 3.659587e-05 +3 chany_bottom_out[0]:3 0.0001574575 +4 chany_bottom_out[0]:4 0.0001574575 +5 chany_bottom_out[0]:5 0.0003481428 +6 chany_bottom_out[0]:6 0.0003481428 +7 chany_bottom_out[0]:7 3.475777e-05 + +*RES +0 ropt_mt_inst_822:X chany_bottom_out[0]:7 0.152 +1 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +2 chany_bottom_out[0]:2 chany_bottom_out[0] 0.0002946429 +3 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.0015625 +4 chany_bottom_out[0]:5 chany_bottom_out[0]:4 0.0045 +5 chany_bottom_out[0]:7 chany_bottom_out[0]:6 0.0045 +6 chany_bottom_out[0]:6 chany_bottom_out[0]:5 0.004473215 + +*END + +*D_NET chanx_left_out[15] 0.0008702679 //LENGTH 5.800 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_825:X O *L 0 *C 4.140 47.260 +*P chanx_left_out[15] O *L 0.7423 *C 1.230 44.880 +*N chanx_left_out[15]:2 *C 4.133 44.880 +*N chanx_left_out[15]:3 *C 4.140 44.938 +*N chanx_left_out[15]:4 *C 4.140 47.215 +*N chanx_left_out[15]:5 *C 4.140 47.260 + +*CAP +0 ropt_mt_inst_825:X 1e-06 +1 chanx_left_out[15] 0.0002196993 +2 chanx_left_out[15]:2 0.0002196993 +3 chanx_left_out[15]:3 0.0001986525 +4 chanx_left_out[15]:4 0.0001986525 +5 chanx_left_out[15]:5 3.256436e-05 + +*RES +0 ropt_mt_inst_825:X chanx_left_out[15]:5 0.152 +1 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +2 chanx_left_out[15]:4 chanx_left_out[15]:3 0.002033482 +3 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +4 chanx_left_out[15]:2 chanx_left_out[15] 0.000454725 + +*END + +*D_NET ropt_net_195 0.001059833 //LENGTH 8.875 LUMPCC 0 DR + +*CONN +*I BUFT_RR_81:X O *L 0 *C 9.200 42.500 +*I ropt_mt_inst_815:A I *L 0.001766 *C 7.820 47.600 +*N ropt_net_195:2 *C 7.820 47.600 +*N ropt_net_195:3 *C 7.820 47.940 +*N ropt_net_195:4 *C 9.155 47.940 +*N ropt_net_195:5 *C 9.200 47.895 +*N ropt_net_195:6 *C 9.200 42.545 +*N ropt_net_195:7 *C 9.200 42.500 + +*CAP +0 BUFT_RR_81:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_195:2 6.434563e-05 +3 ropt_net_195:3 0.0001782733 +4 ropt_net_195:4 0.0001471293 +5 ropt_net_195:5 0.00031685 +6 ropt_net_195:6 0.00031685 +7 ropt_net_195:7 3.438462e-05 + +*RES +0 BUFT_RR_81:X ropt_net_195:7 0.152 +1 ropt_net_195:7 ropt_net_195:6 0.0045 +2 ropt_net_195:6 ropt_net_195:5 0.004776786 +3 ropt_net_195:4 ropt_net_195:3 0.001191964 +4 ropt_net_195:5 ropt_net_195:4 0.0045 +5 ropt_net_195:2 ropt_mt_inst_815:A 0.152 +6 ropt_net_195:3 ropt_net_195:2 0.0003035715 + +*END + +*D_NET chanx_right_out[17] 0.0007033197 //LENGTH 4.980 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_836:X O *L 0 *C 138.655 90.440 +*P chanx_right_out[17] O *L 0.7423 *C 140.375 88.400 +*N chanx_right_out[17]:2 *C 140.300 88.400 +*N chanx_right_out[17]:3 *C 138.468 88.400 +*N chanx_right_out[17]:4 *C 138.460 88.458 +*N chanx_right_out[17]:5 *C 138.460 90.395 +*N chanx_right_out[17]:6 *C 138.460 90.440 +*N chanx_right_out[17]:7 *C 138.655 90.440 + +*CAP +0 ropt_mt_inst_836:X 1e-06 +1 chanx_right_out[17] 1.812044e-05 +2 chanx_right_out[17]:2 0.0001486553 +3 chanx_right_out[17]:3 0.0001305349 +4 chanx_right_out[17]:4 0.0001501398 +5 chanx_right_out[17]:5 0.0001501398 +6 chanx_right_out[17]:6 5.132287e-05 +7 chanx_right_out[17]:7 5.340653e-05 + +*RES +0 ropt_mt_inst_836:X chanx_right_out[17]:7 0.152 +1 chanx_right_out[17]:7 chanx_right_out[17]:6 0.0001059783 +2 chanx_right_out[17]:6 chanx_right_out[17]:5 0.0045 +3 chanx_right_out[17]:5 chanx_right_out[17]:4 0.001729911 +4 chanx_right_out[17]:4 chanx_right_out[17]:3 0.00341 +5 chanx_right_out[17]:3 chanx_right_out[17]:2 0.0002870917 +6 chanx_right_out[17]:2 chanx_right_out[17] 1.175e-05 + +*END + +*D_NET chanx_right_in[17] 0.02657533 //LENGTH 179.133 LUMPCC 0.01045895 DR + +*CONN +*P chanx_right_in[17] I *L 0.29796 *C 140.450 61.200 +*I mux_bottom_track_23\/mux_l1_in_0_:A1 I *L 0.00198 *C 83.360 34.340 +*I ropt_mt_inst_812:A I *L 0.001767 *C 3.220 69.360 +*I mux_left_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 61.930 60.860 +*N chanx_right_in[17]:4 *C 61.930 60.860 +*N chanx_right_in[17]:5 *C 62.100 60.860 +*N chanx_right_in[17]:6 *C 62.100 60.905 +*N chanx_right_in[17]:7 *C 3.258 69.360 +*N chanx_right_in[17]:8 *C 5.015 69.360 +*N chanx_right_in[17]:9 *C 5.060 69.315 +*N chanx_right_in[17]:10 *C 5.060 64.657 +*N chanx_right_in[17]:11 *C 5.067 64.600 +*N chanx_right_in[17]:12 *C 21.620 64.600 +*N chanx_right_in[17]:13 *C 21.620 63.920 +*N chanx_right_in[17]:14 *C 52.893 63.920 +*N chanx_right_in[17]:15 *C 52.900 63.863 +*N chanx_right_in[17]:16 *C 52.900 61.925 +*N chanx_right_in[17]:17 *C 52.945 61.880 +*N chanx_right_in[17]:18 *C 62.055 61.880 +*N chanx_right_in[17]:19 *C 62.100 61.880 +*N chanx_right_in[17]:20 *C 62.108 61.880 +*N chanx_right_in[17]:21 *C 81.880 61.880 +*N chanx_right_in[17]:22 *C 83.260 34.340 +*N chanx_right_in[17]:23 *C 83.260 34.385 +*N chanx_right_in[17]:24 *C 83.260 42.102 +*N chanx_right_in[17]:25 *C 83.252 42.160 +*N chanx_right_in[17]:26 *C 81.900 42.160 +*N chanx_right_in[17]:27 *C 81.880 42.168 +*N chanx_right_in[17]:28 *C 81.880 61.193 +*N chanx_right_in[17]:29 *C 81.880 61.200 +*N chanx_right_in[17]:30 *C 131.690 61.200 + +*CAP +0 chanx_right_in[17] 0.0005037513 +1 mux_bottom_track_23\/mux_l1_in_0_:A1 1e-06 +2 ropt_mt_inst_812:A 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:A0 1e-06 +4 chanx_right_in[17]:4 4.736098e-05 +5 chanx_right_in[17]:5 5.159526e-05 +6 chanx_right_in[17]:6 6.252123e-05 +7 chanx_right_in[17]:7 8.206003e-05 +8 chanx_right_in[17]:8 8.206003e-05 +9 chanx_right_in[17]:9 0.0002728973 +10 chanx_right_in[17]:10 0.0002728973 +11 chanx_right_in[17]:11 0.0008400911 +12 chanx_right_in[17]:12 0.0008910439 +13 chanx_right_in[17]:13 0.0009783019 +14 chanx_right_in[17]:14 0.0009273491 +15 chanx_right_in[17]:15 0.0001345022 +16 chanx_right_in[17]:16 0.0001345022 +17 chanx_right_in[17]:17 0.0006259826 +18 chanx_right_in[17]:18 0.0006259826 +19 chanx_right_in[17]:19 0.0001028656 +20 chanx_right_in[17]:20 0.0007462146 +21 chanx_right_in[17]:21 0.0008012402 +22 chanx_right_in[17]:22 3.384129e-05 +23 chanx_right_in[17]:23 0.0004607452 +24 chanx_right_in[17]:24 0.0004607452 +25 chanx_right_in[17]:25 0.0001799273 +26 chanx_right_in[17]:26 0.0001799273 +27 chanx_right_in[17]:27 0.001074144 +28 chanx_right_in[17]:28 0.001074144 +29 chanx_right_in[17]:29 0.00200898 +30 chanx_right_in[17]:30 0.002457706 +31 chanx_right_in[17]:19 chanx_right_in[8]:23 2.374218e-06 +32 chanx_right_in[17]:20 chanx_right_in[8]:24 0.0001945173 +33 chanx_right_in[17]:14 chanx_right_in[8]:14 0.0001452104 +34 chanx_right_in[17]:14 chanx_right_in[8]:18 0.001420833 +35 chanx_right_in[17]:11 chanx_right_in[8]:9 9.825391e-05 +36 chanx_right_in[17]:6 chanx_right_in[8]:22 2.374218e-06 +37 chanx_right_in[17]:12 chanx_right_in[8]:10 9.825391e-05 +38 chanx_right_in[17]:13 chanx_right_in[8]:13 0.0001452104 +39 chanx_right_in[17]:13 chanx_right_in[8]:17 0.001420833 +40 chanx_right_in[17]:21 chanx_right_in[8]:25 0.0001945173 +41 chanx_right_in[17]:20 chanx_left_in[5]:36 0.0002648539 +42 chanx_right_in[17]:20 chanx_left_in[5]:35 0.0001344885 +43 chanx_right_in[17]:14 chanx_left_in[5]:35 0.0001013475 +44 chanx_right_in[17]:29 chanx_left_in[5]:35 0.000605053 +45 chanx_right_in[17]:13 chanx_left_in[5]:36 0.0001013475 +46 chanx_right_in[17]:21 chanx_left_in[5]:34 0.0001344885 +47 chanx_right_in[17]:21 chanx_left_in[5]:35 0.0002648539 +48 chanx_right_in[17]:30 chanx_left_in[5]:34 0.000605053 +49 chanx_right_in[17]:20 chanx_left_in[9]:20 0.0003303354 +50 chanx_right_in[17]:14 chanx_left_in[9]:24 1.115308e-05 +51 chanx_right_in[17]:14 chanx_left_in[9]:23 2.519627e-05 +52 chanx_right_in[17]:14 chanx_left_in[9]:19 0.0004969037 +53 chanx_right_in[17]:29 chanx_left_in[9]:20 0.0001092727 +54 chanx_right_in[17]:13 chanx_left_in[9]:25 1.115308e-05 +55 chanx_right_in[17]:13 chanx_left_in[9]:24 2.519627e-05 +56 chanx_right_in[17]:13 chanx_left_in[9]:20 0.0004969037 +57 chanx_right_in[17]:21 chanx_left_in[9]:19 0.0003303354 +58 chanx_right_in[17]:30 chanx_left_in[9]:19 0.0001092727 +59 chanx_right_in[17]:14 chanx_left_in[14]:31 5.52541e-06 +60 chanx_right_in[17]:11 chanx_left_in[14]:34 3.253683e-05 +61 chanx_right_in[17]:11 chanx_left_in[14]:32 1.476112e-05 +62 chanx_right_in[17]:29 chanx_left_in[14]:12 0.0003614604 +63 chanx_right_in[17]:12 chanx_left_in[14]:31 1.476112e-05 +64 chanx_right_in[17]:12 chanx_left_in[14]:33 3.253683e-05 +65 chanx_right_in[17]:13 chanx_left_in[14]:32 5.52541e-06 +66 chanx_right_in[17]:30 chanx_left_in[14]:11 0.0003614604 +67 chanx_right_in[17]:28 chany_bottom_in[9]:13 0.0003268414 +68 chanx_right_in[17]:27 chany_bottom_in[9]:14 0.0003268414 +69 chanx_right_in[17]:11 chanx_left_in[11] 0.0003681214 +70 chanx_right_in[17]:12 chanx_left_in[11]:6 0.0003681214 +71 chanx_right_in[17]:29 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001345571 +72 chanx_right_in[17]:30 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001345571 +73 chanx_right_in[17]:8 ropt_net_216:3 4.587932e-05 +74 chanx_right_in[17]:7 ropt_net_216:4 4.587932e-05 + +*RES +0 chanx_right_in[17] chanx_right_in[17]:30 0.0013724 +1 chanx_right_in[17]:19 chanx_right_in[17]:18 0.0045 +2 chanx_right_in[17]:19 chanx_right_in[17]:6 0.0008705358 +3 chanx_right_in[17]:20 chanx_right_in[17]:19 0.00341 +4 chanx_right_in[17]:18 chanx_right_in[17]:17 0.008133929 +5 chanx_right_in[17]:17 chanx_right_in[17]:16 0.0045 +6 chanx_right_in[17]:16 chanx_right_in[17]:15 0.001729911 +7 chanx_right_in[17]:15 chanx_right_in[17]:14 0.00341 +8 chanx_right_in[17]:14 chanx_right_in[17]:13 0.004899358 +9 chanx_right_in[17]:10 chanx_right_in[17]:9 0.004158482 +10 chanx_right_in[17]:11 chanx_right_in[17]:10 0.00341 +11 chanx_right_in[17]:8 chanx_right_in[17]:7 0.001569196 +12 chanx_right_in[17]:9 chanx_right_in[17]:8 0.0045 +13 chanx_right_in[17]:7 ropt_mt_inst_812:A 0.152 +14 chanx_right_in[17]:5 chanx_right_in[17]:4 9.239132e-05 +15 chanx_right_in[17]:6 chanx_right_in[17]:5 0.0045 +16 chanx_right_in[17]:4 mux_left_track_17\/mux_l1_in_0_:A0 0.152 +17 chanx_right_in[17]:29 chanx_right_in[17]:28 0.00341 +18 chanx_right_in[17]:29 chanx_right_in[17]:21 0.0001065333 +19 chanx_right_in[17]:28 chanx_right_in[17]:27 0.002980583 +20 chanx_right_in[17]:26 chanx_right_in[17]:25 0.0002118916 +21 chanx_right_in[17]:27 chanx_right_in[17]:26 0.00341 +22 chanx_right_in[17]:24 chanx_right_in[17]:23 0.006890625 +23 chanx_right_in[17]:25 chanx_right_in[17]:24 0.00341 +24 chanx_right_in[17]:22 mux_bottom_track_23\/mux_l1_in_0_:A1 0.152 +25 chanx_right_in[17]:23 chanx_right_in[17]:22 0.0045 +26 chanx_right_in[17]:12 chanx_right_in[17]:11 0.002593225 +27 chanx_right_in[17]:13 chanx_right_in[17]:12 0.0001065333 +28 chanx_right_in[17]:21 chanx_right_in[17]:20 0.003097692 +29 chanx_right_in[17]:30 chanx_right_in[17]:29 0.007803566 + +*END + +*D_NET chany_bottom_in[8] 0.01093273 //LENGTH 61.245 LUMPCC 0.005904376 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 77.740 1.290 +*I mux_left_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 68.830 44.200 +*I mux_right_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.515 42.500 +*N chany_bottom_in[8]:3 *C 77.800 41.480 +*N chany_bottom_in[8]:4 *C 82.478 42.500 +*N chany_bottom_in[8]:5 *C 81.925 42.500 +*N chany_bottom_in[8]:6 *C 81.880 42.455 +*N chany_bottom_in[8]:7 *C 81.880 41.525 +*N chany_bottom_in[8]:8 *C 81.835 41.480 +*N chany_bottom_in[8]:9 *C 68.868 44.200 +*N chany_bottom_in[8]:10 *C 69.875 44.200 +*N chany_bottom_in[8]:11 *C 69.920 44.155 +*N chany_bottom_in[8]:12 *C 69.920 41.525 +*N chany_bottom_in[8]:13 *C 69.965 41.480 +*N chany_bottom_in[8]:14 *C 78.200 41.480 +*N chany_bottom_in[8]:15 *C 78.200 41.480 +*N chany_bottom_in[8]:16 *C 78.200 41.480 +*N chany_bottom_in[8]:17 *C 78.200 41.473 +*N chany_bottom_in[8]:18 *C 78.200 2.728 +*N chany_bottom_in[8]:19 *C 78.185 2.720 +*N chany_bottom_in[8]:20 *C 77.743 2.720 +*N chany_bottom_in[8]:21 *C 77.740 2.663 + +*CAP +0 chany_bottom_in[8] 8.125736e-05 +1 mux_left_track_5\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_16\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[8]:3 9.47701e-05 +4 chany_bottom_in[8]:4 7.420217e-05 +5 chany_bottom_in[8]:5 7.420217e-05 +6 chany_bottom_in[8]:6 8.550026e-05 +7 chany_bottom_in[8]:7 8.550026e-05 +8 chany_bottom_in[8]:8 0.0002620355 +9 chany_bottom_in[8]:9 9.866724e-05 +10 chany_bottom_in[8]:10 9.866724e-05 +11 chany_bottom_in[8]:11 0.0001988209 +12 chany_bottom_in[8]:12 0.0001988209 +13 chany_bottom_in[8]:13 0.0005587371 +14 chany_bottom_in[8]:14 0.0008524281 +15 chany_bottom_in[8]:15 3.848944e-05 +16 chany_bottom_in[8]:16 9.47701e-05 +17 chany_bottom_in[8]:17 0.000944341 +18 chany_bottom_in[8]:18 0.000944341 +19 chany_bottom_in[8]:19 7.977369e-05 +20 chany_bottom_in[8]:20 7.977369e-05 +21 chany_bottom_in[8]:21 8.125736e-05 +22 chany_bottom_in[8]:17 chany_bottom_in[12]:16 0.001598923 +23 chany_bottom_in[8]:18 chany_bottom_in[12]:17 0.001598923 +24 chany_bottom_in[8] chany_bottom_in[19] 1.680095e-05 +25 chany_bottom_in[8]:17 chany_bottom_in[19]:16 0.001336464 +26 chany_bottom_in[8]:18 chany_bottom_in[19]:17 0.001336464 +27 chany_bottom_in[8]:21 chany_bottom_in[19]:20 1.680095e-05 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:21 0.001225446 +1 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.0045 +2 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.002348214 +3 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.0008995536 +4 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.0045 +5 chany_bottom_in[8]:9 mux_left_track_5\/mux_l1_in_1_:A0 0.152 +6 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.0045 +7 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.0008303573 +8 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.0004933035 +9 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.0045 +10 chany_bottom_in[8]:4 mux_right_track_16\/mux_l1_in_0_:A0 0.152 +11 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.007352679 +12 chany_bottom_in[8]:14 chany_bottom_in[8]:8 0.003245536 +13 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.0045 +14 chany_bottom_in[8]:16 chany_bottom_in[8]:15 0.00341 +15 chany_bottom_in[8]:16 chany_bottom_in[8]:3 5.69697e-05 +16 chany_bottom_in[8]:17 chany_bottom_in[8]:16 0.00341 +17 chany_bottom_in[8]:19 chany_bottom_in[8]:18 0.00341 +18 chany_bottom_in[8]:18 chany_bottom_in[8]:17 0.006070049 +19 chany_bottom_in[8]:21 chany_bottom_in[8]:20 0.00341 +20 chany_bottom_in[8]:20 chany_bottom_in[8]:19 6.499219e-05 + +*END + +*D_NET bottom_left_grid_pin_39_[0] 0.01116699 //LENGTH 78.600 LUMPCC 0.002888199 DR + +*CONN +*P bottom_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 11.560 +*I mux_bottom_track_19\/mux_l1_in_0_:A0 I *L 0.001631 *C 63.310 26.180 +*I mux_bottom_track_35\/mux_l1_in_0_:A0 I *L 0.001631 *C 69.290 26.180 +*I mux_bottom_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 30.650 31.620 +*I mux_bottom_track_7\/mux_l1_in_1_:A0 I *L 0.001631 *C 22.255 39.100 +*N bottom_left_grid_pin_39_[0]:5 *C 22.293 39.100 +*N bottom_left_grid_pin_39_[0]:6 *C 28.015 39.100 +*N bottom_left_grid_pin_39_[0]:7 *C 28.060 39.055 +*N bottom_left_grid_pin_39_[0]:8 *C 28.060 31.665 +*N bottom_left_grid_pin_39_[0]:9 *C 28.105 31.620 +*N bottom_left_grid_pin_39_[0]:10 *C 30.650 31.620 +*N bottom_left_grid_pin_39_[0]:11 *C 31.235 31.620 +*N bottom_left_grid_pin_39_[0]:12 *C 31.280 31.575 +*N bottom_left_grid_pin_39_[0]:13 *C 69.252 26.180 +*N bottom_left_grid_pin_39_[0]:14 *C 63.310 26.180 +*N bottom_left_grid_pin_39_[0]:15 *C 63.525 26.180 +*N bottom_left_grid_pin_39_[0]:16 *C 63.480 26.180 +*N bottom_left_grid_pin_39_[0]:17 *C 63.480 26.520 +*N bottom_left_grid_pin_39_[0]:18 *C 63.473 26.520 +*N bottom_left_grid_pin_39_[0]:19 *C 31.288 26.520 +*N bottom_left_grid_pin_39_[0]:20 *C 31.280 26.520 +*N bottom_left_grid_pin_39_[0]:21 *C 31.280 11.617 +*N bottom_left_grid_pin_39_[0]:22 *C 31.273 11.560 + +*CAP +0 bottom_left_grid_pin_39_[0] 0.0001213935 +1 mux_bottom_track_19\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_35\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_3\/mux_l1_in_1_:A0 1e-06 +4 mux_bottom_track_7\/mux_l1_in_1_:A0 1e-06 +5 bottom_left_grid_pin_39_[0]:5 0.0003408508 +6 bottom_left_grid_pin_39_[0]:6 0.0003408508 +7 bottom_left_grid_pin_39_[0]:7 0.0004355629 +8 bottom_left_grid_pin_39_[0]:8 0.0004355629 +9 bottom_left_grid_pin_39_[0]:9 0.0002054655 +10 bottom_left_grid_pin_39_[0]:10 0.0002840732 +11 bottom_left_grid_pin_39_[0]:11 4.801813e-05 +12 bottom_left_grid_pin_39_[0]:12 0.0001200783 +13 bottom_left_grid_pin_39_[0]:13 0.0004093598 +14 bottom_left_grid_pin_39_[0]:14 5.142633e-05 +15 bottom_left_grid_pin_39_[0]:15 0.0004332776 +16 bottom_left_grid_pin_39_[0]:16 5.47572e-05 +17 bottom_left_grid_pin_39_[0]:17 5.875955e-05 +18 bottom_left_grid_pin_39_[0]:18 0.002053777 +19 bottom_left_grid_pin_39_[0]:19 0.002053777 +20 bottom_left_grid_pin_39_[0]:20 0.0004270481 +21 bottom_left_grid_pin_39_[0]:21 0.0002793557 +22 bottom_left_grid_pin_39_[0]:22 0.0001213935 +23 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_37_[0]:13 2.142852e-05 +24 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_37_[0]:26 0.0005065516 +25 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_37_[0]:27 3.584757e-05 +26 bottom_left_grid_pin_39_[0]:19 bottom_left_grid_pin_37_[0]:21 0.0003043996 +27 bottom_left_grid_pin_39_[0]:18 bottom_left_grid_pin_37_[0]:20 0.0003043996 +28 bottom_left_grid_pin_39_[0]:11 bottom_left_grid_pin_37_[0]:12 9.919797e-06 +29 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_37_[0]:10 2.142852e-05 +30 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_37_[0]:13 7.736645e-05 +31 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_37_[0]:26 3.584757e-05 +32 bottom_left_grid_pin_39_[0]:10 bottom_left_grid_pin_37_[0]:11 9.919797e-06 +33 bottom_left_grid_pin_39_[0]:21 bottom_left_grid_pin_37_[0]:27 0.0004291851 +34 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_41_[0] 3.624918e-06 +35 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_41_[0]:27 2.155984e-06 +36 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_41_[0]:25 0.0003533006 +37 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_41_[0]:26 0.0001346425 +38 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_41_[0]:25 0.0001346425 +39 bottom_left_grid_pin_39_[0]:21 bottom_left_grid_pin_41_[0]:26 0.0003533006 +40 bottom_left_grid_pin_39_[0]:22 bottom_left_grid_pin_41_[0]:17 2.155984e-06 +41 bottom_left_grid_pin_39_[0]:22 bottom_left_grid_pin_41_[0]:27 3.624918e-06 +42 bottom_left_grid_pin_39_[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.0692e-05 +43 bottom_left_grid_pin_39_[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.0692e-05 +44 bottom_left_grid_pin_39_[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.536457e-06 +45 bottom_left_grid_pin_39_[0]:8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.536457e-06 + +*RES +0 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_39_[0]:22 0.000238525 +1 bottom_left_grid_pin_39_[0]:5 mux_bottom_track_7\/mux_l1_in_1_:A0 0.152 +2 bottom_left_grid_pin_39_[0]:6 bottom_left_grid_pin_39_[0]:5 0.005109375 +3 bottom_left_grid_pin_39_[0]:7 bottom_left_grid_pin_39_[0]:6 0.0045 +4 bottom_left_grid_pin_39_[0]:9 bottom_left_grid_pin_39_[0]:8 0.0045 +5 bottom_left_grid_pin_39_[0]:8 bottom_left_grid_pin_39_[0]:7 0.006598215 +6 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_39_[0]:19 0.00341 +7 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_39_[0]:12 0.004513393 +8 bottom_left_grid_pin_39_[0]:19 bottom_left_grid_pin_39_[0]:18 0.005042316 +9 bottom_left_grid_pin_39_[0]:17 bottom_left_grid_pin_39_[0]:16 0.0001634615 +10 bottom_left_grid_pin_39_[0]:18 bottom_left_grid_pin_39_[0]:17 0.00341 +11 bottom_left_grid_pin_39_[0]:15 bottom_left_grid_pin_39_[0]:14 0.0001168478 +12 bottom_left_grid_pin_39_[0]:15 bottom_left_grid_pin_39_[0]:13 0.00511384 +13 bottom_left_grid_pin_39_[0]:16 bottom_left_grid_pin_39_[0]:15 0.0045 +14 bottom_left_grid_pin_39_[0]:11 bottom_left_grid_pin_39_[0]:10 0.0005223214 +15 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_39_[0]:11 0.0045 +16 bottom_left_grid_pin_39_[0]:13 mux_bottom_track_35\/mux_l1_in_0_:A0 0.152 +17 bottom_left_grid_pin_39_[0]:10 mux_bottom_track_3\/mux_l1_in_1_:A0 0.152 +18 bottom_left_grid_pin_39_[0]:10 bottom_left_grid_pin_39_[0]:9 0.002272322 +19 bottom_left_grid_pin_39_[0]:14 mux_bottom_track_19\/mux_l1_in_0_:A0 0.152 +20 bottom_left_grid_pin_39_[0]:21 bottom_left_grid_pin_39_[0]:20 0.0133058 +21 bottom_left_grid_pin_39_[0]:22 bottom_left_grid_pin_39_[0]:21 0.00341 + +*END + +*D_NET chany_bottom_out[11] 0.002305526 //LENGTH 15.060 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 82.160 7.140 +*P chany_bottom_out[11] O *L 0.7423 *C 74.060 1.325 +*N chany_bottom_out[11]:2 *C 74.060 6.062 +*N chany_bottom_out[11]:3 *C 74.068 6.120 +*N chany_bottom_out[11]:4 *C 81.413 6.120 +*N chany_bottom_out[11]:5 *C 81.420 6.120 +*N chany_bottom_out[11]:6 *C 81.420 6.460 +*N chany_bottom_out[11]:7 *C 81.465 6.460 +*N chany_bottom_out[11]:8 *C 81.835 6.460 +*N chany_bottom_out[11]:9 *C 81.880 6.505 +*N chany_bottom_out[11]:10 *C 81.880 7.095 +*N chany_bottom_out[11]:11 *C 81.880 7.140 +*N chany_bottom_out[11]:12 *C 82.160 7.140 + +*CAP +0 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[11] 0.0002898979 +2 chany_bottom_out[11]:2 0.0002898979 +3 chany_bottom_out[11]:3 0.0006335064 +4 chany_bottom_out[11]:4 0.0006335064 +5 chany_bottom_out[11]:5 4.995241e-05 +6 chany_bottom_out[11]:6 4.572435e-05 +7 chany_bottom_out[11]:7 6.309991e-05 +8 chany_bottom_out[11]:8 6.309991e-05 +9 chany_bottom_out[11]:9 5.706949e-05 +10 chany_bottom_out[11]:10 5.706949e-05 +11 chany_bottom_out[11]:11 6.30049e-05 +12 chany_bottom_out[11]:12 5.869711e-05 + +*RES +0 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[11]:12 0.152 +1 chany_bottom_out[11]:2 chany_bottom_out[11] 0.004229911 +2 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.00341 +3 chany_bottom_out[11]:5 chany_bottom_out[11]:4 0.00341 +4 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.001150717 +5 chany_bottom_out[11]:7 chany_bottom_out[11]:6 0.0045 +6 chany_bottom_out[11]:6 chany_bottom_out[11]:5 0.0001634615 +7 chany_bottom_out[11]:8 chany_bottom_out[11]:7 0.0003303571 +8 chany_bottom_out[11]:9 chany_bottom_out[11]:8 0.0045 +9 chany_bottom_out[11]:11 chany_bottom_out[11]:10 0.0045 +10 chany_bottom_out[11]:10 chany_bottom_out[11]:9 0.0005267857 +11 chany_bottom_out[11]:12 chany_bottom_out[11]:11 0.0001521739 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.002680338 //LENGTH 21.005 LUMPCC 0.0002964534 DR + +*CONN +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 73.445 20.740 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 65.035 15.300 +*I mux_bottom_track_35\/mux_l1_in_0_:S I *L 0.00357 *C 68.180 25.500 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 68.195 25.500 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 68.517 25.500 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 68.540 25.455 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 65.035 15.300 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 64.860 15.300 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 64.860 15.345 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 64.860 18.315 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 64.905 18.360 +*N mux_tree_tapbuf_size2_4_sram[0]:11 *C 68.495 18.360 +*N mux_tree_tapbuf_size2_4_sram[0]:12 *C 68.540 18.405 +*N mux_tree_tapbuf_size2_4_sram[0]:13 *C 68.540 20.740 +*N mux_tree_tapbuf_size2_4_sram[0]:14 *C 68.585 20.740 +*N mux_tree_tapbuf_size2_4_sram[0]:15 *C 73.407 20.740 + +*CAP +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_35\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 6.819002e-05 +4 mux_tree_tapbuf_size2_4_sram[0]:4 6.819002e-05 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.0002240388 +6 mux_tree_tapbuf_size2_4_sram[0]:6 5.106347e-05 +7 mux_tree_tapbuf_size2_4_sram[0]:7 5.546716e-05 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.000142868 +9 mux_tree_tapbuf_size2_4_sram[0]:9 0.000142868 +10 mux_tree_tapbuf_size2_4_sram[0]:10 0.0002167966 +11 mux_tree_tapbuf_size2_4_sram[0]:11 0.0002167966 +12 mux_tree_tapbuf_size2_4_sram[0]:12 0.0001528175 +13 mux_tree_tapbuf_size2_4_sram[0]:13 0.0004117584 +14 mux_tree_tapbuf_size2_4_sram[0]:14 0.0003150148 +15 mux_tree_tapbuf_size2_4_sram[0]:15 0.0003150148 +16 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 6.440692e-05 +17 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 3.992078e-06 +18 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 6.440692e-05 +19 mux_tree_tapbuf_size2_4_sram[0]:12 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 3.992078e-06 +20 mux_tree_tapbuf_size2_4_sram[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 4.47958e-05 +21 mux_tree_tapbuf_size2_4_sram[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.47958e-05 +22 mux_tree_tapbuf_size2_4_sram[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.50319e-05 +23 mux_tree_tapbuf_size2_4_sram[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.50319e-05 + +*RES +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:14 mux_tree_tapbuf_size2_4_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_4_sram[0]:12 0.002084821 +3 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_4_sram[0]:5 0.004209822 +4 mux_tree_tapbuf_size2_4_sram[0]:15 mux_tree_tapbuf_size2_4_sram[0]:14 0.004305804 +5 mux_tree_tapbuf_size2_4_sram[0]:4 mux_tree_tapbuf_size2_4_sram[0]:3 0.0001752718 +6 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_4_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size2_4_sram[0]:3 mux_bottom_track_35\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_4_sram[0]:11 mux_tree_tapbuf_size2_4_sram[0]:10 0.003205357 +9 mux_tree_tapbuf_size2_4_sram[0]:12 mux_tree_tapbuf_size2_4_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.002651786 +12 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:6 9.51087e-05 +13 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.0045 +14 mux_tree_tapbuf_size2_4_sram[0]:6 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_5_sram[1] 0.001485536 //LENGTH 9.210 LUMPCC 0.0004684146 DR + +*CONN +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 84.025 28.220 +*I mem_bottom_track_21\/FTB_18__43:A I *L 0.001746 *C 84.640 25.840 +*I mux_bottom_track_21\/mux_l2_in_0_:S I *L 0.00357 *C 85.920 23.800 +*N mux_tree_tapbuf_size3_5_sram[1]:3 *C 85.883 23.800 +*N mux_tree_tapbuf_size3_5_sram[1]:4 *C 83.765 23.800 +*N mux_tree_tapbuf_size3_5_sram[1]:5 *C 83.720 23.845 +*N mux_tree_tapbuf_size3_5_sram[1]:6 *C 84.640 25.840 +*N mux_tree_tapbuf_size3_5_sram[1]:7 *C 84.640 25.500 +*N mux_tree_tapbuf_size3_5_sram[1]:8 *C 83.765 25.500 +*N mux_tree_tapbuf_size3_5_sram[1]:9 *C 83.720 25.500 +*N mux_tree_tapbuf_size3_5_sram[1]:10 *C 83.720 28.175 +*N mux_tree_tapbuf_size3_5_sram[1]:11 *C 83.720 28.220 +*N mux_tree_tapbuf_size3_5_sram[1]:12 *C 84.025 28.220 + +*CAP +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_21\/FTB_18__43:A 1e-06 +2 mux_bottom_track_21\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_5_sram[1]:3 0.0001897285 +4 mux_tree_tapbuf_size3_5_sram[1]:4 0.0001897285 +5 mux_tree_tapbuf_size3_5_sram[1]:5 4.506428e-05 +6 mux_tree_tapbuf_size3_5_sram[1]:6 6.248668e-05 +7 mux_tree_tapbuf_size3_5_sram[1]:7 0.0001226694 +8 mux_tree_tapbuf_size3_5_sram[1]:8 9.220187e-05 +9 mux_tree_tapbuf_size3_5_sram[1]:9 0.000143465 +10 mux_tree_tapbuf_size3_5_sram[1]:10 6.58777e-05 +11 mux_tree_tapbuf_size3_5_sram[1]:11 5.560567e-05 +12 mux_tree_tapbuf_size3_5_sram[1]:12 4.729427e-05 +13 mux_tree_tapbuf_size3_5_sram[1]:5 chanx_right_in[3]:4 4.20496e-05 +14 mux_tree_tapbuf_size3_5_sram[1]:9 chanx_right_in[3]:4 6.629092e-05 +15 mux_tree_tapbuf_size3_5_sram[1]:9 chanx_right_in[3]:5 4.20496e-05 +16 mux_tree_tapbuf_size3_5_sram[1]:11 chanx_right_in[3]:6 3.750758e-06 +17 mux_tree_tapbuf_size3_5_sram[1]:10 chanx_right_in[3]:5 6.629092e-05 +18 mux_tree_tapbuf_size3_5_sram[1]:12 chanx_right_in[3]:7 3.750758e-06 +19 mux_tree_tapbuf_size3_5_sram[1]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.851877e-05 +20 mux_tree_tapbuf_size3_5_sram[1]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.851877e-05 +21 mux_tree_tapbuf_size3_5_sram[1]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.359726e-05 +22 mux_tree_tapbuf_size3_5_sram[1]:10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.359726e-05 + +*RES +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_5_sram[1]:12 0.152 +1 mux_tree_tapbuf_size3_5_sram[1]:4 mux_tree_tapbuf_size3_5_sram[1]:3 0.001890625 +2 mux_tree_tapbuf_size3_5_sram[1]:5 mux_tree_tapbuf_size3_5_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size3_5_sram[1]:3 mux_bottom_track_21\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size3_5_sram[1]:8 mux_tree_tapbuf_size3_5_sram[1]:7 0.00078125 +5 mux_tree_tapbuf_size3_5_sram[1]:9 mux_tree_tapbuf_size3_5_sram[1]:8 0.0045 +6 mux_tree_tapbuf_size3_5_sram[1]:9 mux_tree_tapbuf_size3_5_sram[1]:5 0.001477679 +7 mux_tree_tapbuf_size3_5_sram[1]:6 mem_bottom_track_21\/FTB_18__43:A 0.152 +8 mux_tree_tapbuf_size3_5_sram[1]:11 mux_tree_tapbuf_size3_5_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size3_5_sram[1]:10 mux_tree_tapbuf_size3_5_sram[1]:9 0.002388393 +10 mux_tree_tapbuf_size3_5_sram[1]:12 mux_tree_tapbuf_size3_5_sram[1]:11 0.0001657609 +11 mux_tree_tapbuf_size3_5_sram[1]:7 mux_tree_tapbuf_size3_5_sram[1]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[1] 0.002543058 //LENGTH 20.465 LUMPCC 0 DR + +*CONN +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 76.665 69.360 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 76.075 66.300 +*I mux_right_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 71.660 61.880 +*I mux_right_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 74.860 58.140 +*N mux_tree_tapbuf_size5_0_sram[1]:4 *C 74.823 58.140 +*N mux_tree_tapbuf_size5_0_sram[1]:5 *C 71.805 58.140 +*N mux_tree_tapbuf_size5_0_sram[1]:6 *C 71.760 58.185 +*N mux_tree_tapbuf_size5_0_sram[1]:7 *C 71.660 61.880 +*N mux_tree_tapbuf_size5_0_sram[1]:8 *C 71.760 61.880 +*N mux_tree_tapbuf_size5_0_sram[1]:9 *C 71.760 66.255 +*N mux_tree_tapbuf_size5_0_sram[1]:10 *C 71.805 66.300 +*N mux_tree_tapbuf_size5_0_sram[1]:11 *C 76.038 66.300 +*N mux_tree_tapbuf_size5_0_sram[1]:12 *C 76.360 66.300 +*N mux_tree_tapbuf_size5_0_sram[1]:13 *C 76.360 66.345 +*N mux_tree_tapbuf_size5_0_sram[1]:14 *C 76.360 69.315 +*N mux_tree_tapbuf_size5_0_sram[1]:15 *C 76.360 69.360 +*N mux_tree_tapbuf_size5_0_sram[1]:16 *C 76.665 69.360 + +*CAP +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_2\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_2\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[1]:4 0.0002271219 +5 mux_tree_tapbuf_size5_0_sram[1]:5 0.0002271219 +6 mux_tree_tapbuf_size5_0_sram[1]:6 0.0002008112 +7 mux_tree_tapbuf_size5_0_sram[1]:7 2.864191e-05 +8 mux_tree_tapbuf_size5_0_sram[1]:8 0.0004704676 +9 mux_tree_tapbuf_size5_0_sram[1]:9 0.0002386763 +10 mux_tree_tapbuf_size5_0_sram[1]:10 0.0002947901 +11 mux_tree_tapbuf_size5_0_sram[1]:11 0.0003155164 +12 mux_tree_tapbuf_size5_0_sram[1]:12 4.924552e-05 +13 mux_tree_tapbuf_size5_0_sram[1]:13 0.000187302 +14 mux_tree_tapbuf_size5_0_sram[1]:14 0.000187302 +15 mux_tree_tapbuf_size5_0_sram[1]:15 5.702917e-05 +16 mux_tree_tapbuf_size5_0_sram[1]:16 5.503235e-05 + +*RES +0 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:9 0.0045 +2 mux_tree_tapbuf_size5_0_sram[1]:9 mux_tree_tapbuf_size5_0_sram[1]:8 0.00390625 +3 mux_tree_tapbuf_size5_0_sram[1]:4 mux_right_track_2\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size5_0_sram[1]:5 mux_tree_tapbuf_size5_0_sram[1]:4 0.002694197 +5 mux_tree_tapbuf_size5_0_sram[1]:6 mux_tree_tapbuf_size5_0_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size5_0_sram[1]:11 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size5_0_sram[1]:11 mux_tree_tapbuf_size5_0_sram[1]:10 0.003779018 +8 mux_tree_tapbuf_size5_0_sram[1]:7 mux_right_track_2\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:7 0.0045 +10 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:6 0.003299108 +11 mux_tree_tapbuf_size5_0_sram[1]:12 mux_tree_tapbuf_size5_0_sram[1]:11 0.0001752718 +12 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:12 0.0045 +13 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:14 0.0045 +14 mux_tree_tapbuf_size5_0_sram[1]:14 mux_tree_tapbuf_size5_0_sram[1]:13 0.002651786 +15 mux_tree_tapbuf_size5_0_sram[1]:16 mux_tree_tapbuf_size5_0_sram[1]:15 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size5_5_sram[2] 0.003019495 //LENGTH 24.050 LUMPCC 0.0002624377 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 49.525 71.740 +*I mux_left_track_17\/mux_l3_in_0_:S I *L 0.00357 *C 39.660 80.240 +*I mem_left_track_17\/FTB_11__36:A I *L 0.001746 *C 46.920 82.960 +*N mux_tree_tapbuf_size5_5_sram[2]:3 *C 46.920 82.960 +*N mux_tree_tapbuf_size5_5_sram[2]:4 *C 46.920 82.915 +*N mux_tree_tapbuf_size5_5_sram[2]:5 *C 39.698 80.240 +*N mux_tree_tapbuf_size5_5_sram[2]:6 *C 41.815 80.240 +*N mux_tree_tapbuf_size5_5_sram[2]:7 *C 41.860 80.285 +*N mux_tree_tapbuf_size5_5_sram[2]:8 *C 41.860 81.543 +*N mux_tree_tapbuf_size5_5_sram[2]:9 *C 41.867 81.600 +*N mux_tree_tapbuf_size5_5_sram[2]:10 *C 46.913 81.600 +*N mux_tree_tapbuf_size5_5_sram[2]:11 *C 46.920 81.600 +*N mux_tree_tapbuf_size5_5_sram[2]:12 *C 46.920 71.785 +*N mux_tree_tapbuf_size5_5_sram[2]:13 *C 46.965 71.740 +*N mux_tree_tapbuf_size5_5_sram[2]:14 *C 49.488 71.740 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_17\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_17\/FTB_11__36:A 1e-06 +3 mux_tree_tapbuf_size5_5_sram[2]:3 3.320552e-05 +4 mux_tree_tapbuf_size5_5_sram[2]:4 7.89954e-05 +5 mux_tree_tapbuf_size5_5_sram[2]:5 0.000186935 +6 mux_tree_tapbuf_size5_5_sram[2]:6 0.000186935 +7 mux_tree_tapbuf_size5_5_sram[2]:7 9.639708e-05 +8 mux_tree_tapbuf_size5_5_sram[2]:8 9.639708e-05 +9 mux_tree_tapbuf_size5_5_sram[2]:9 0.0003476922 +10 mux_tree_tapbuf_size5_5_sram[2]:10 0.0003476922 +11 mux_tree_tapbuf_size5_5_sram[2]:11 0.0005745086 +12 mux_tree_tapbuf_size5_5_sram[2]:12 0.0004602476 +13 mux_tree_tapbuf_size5_5_sram[2]:13 0.0001725259 +14 mux_tree_tapbuf_size5_5_sram[2]:14 0.0001725259 +15 mux_tree_tapbuf_size5_5_sram[2]:12 chanx_right_in[12]:12 0.0001312189 +16 mux_tree_tapbuf_size5_5_sram[2]:11 chanx_right_in[12]:11 0.0001312189 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_5_sram[2]:14 0.152 +1 mux_tree_tapbuf_size5_5_sram[2]:13 mux_tree_tapbuf_size5_5_sram[2]:12 0.0045 +2 mux_tree_tapbuf_size5_5_sram[2]:12 mux_tree_tapbuf_size5_5_sram[2]:11 0.008763393 +3 mux_tree_tapbuf_size5_5_sram[2]:14 mux_tree_tapbuf_size5_5_sram[2]:13 0.002252232 +4 mux_tree_tapbuf_size5_5_sram[2]:11 mux_tree_tapbuf_size5_5_sram[2]:10 0.00341 +5 mux_tree_tapbuf_size5_5_sram[2]:11 mux_tree_tapbuf_size5_5_sram[2]:4 0.001174107 +6 mux_tree_tapbuf_size5_5_sram[2]:10 mux_tree_tapbuf_size5_5_sram[2]:9 0.0007903833 +7 mux_tree_tapbuf_size5_5_sram[2]:8 mux_tree_tapbuf_size5_5_sram[2]:7 0.001122768 +8 mux_tree_tapbuf_size5_5_sram[2]:9 mux_tree_tapbuf_size5_5_sram[2]:8 0.00341 +9 mux_tree_tapbuf_size5_5_sram[2]:6 mux_tree_tapbuf_size5_5_sram[2]:5 0.001890625 +10 mux_tree_tapbuf_size5_5_sram[2]:7 mux_tree_tapbuf_size5_5_sram[2]:6 0.0045 +11 mux_tree_tapbuf_size5_5_sram[2]:5 mux_left_track_17\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size5_5_sram[2]:3 mem_left_track_17\/FTB_11__36:A 0.152 +13 mux_tree_tapbuf_size5_5_sram[2]:4 mux_tree_tapbuf_size5_5_sram[2]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_2_ccff_tail[0] 0.002218666 //LENGTH 16.860 LUMPCC 0.0005343916 DR + +*CONN +*I mem_right_track_8\/FTB_3__28:X O *L 0 *C 113.845 47.600 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 100.455 49.980 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 *C 100.455 49.980 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 *C 100.280 49.980 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 *C 100.280 49.935 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 *C 100.280 47.645 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 *C 100.325 47.600 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 *C 113.808 47.600 + +*CAP +0 mem_right_track_8\/FTB_3__28:X 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 4.569452e-05 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 4.963582e-05 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.0001300581 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0001300581 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.0006634142 +7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.0006634142 +8 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size5_1_sram[0]:13 6.399684e-05 +9 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size5_1_sram[0]:12 6.399684e-05 +10 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size5_1_sram[0]:14 1.338769e-05 +11 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size5_1_sram[0]:15 1.338769e-05 +12 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size5_2_sram[1]:9 8.304807e-05 +13 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size5_2_sram[1]:8 8.304807e-05 +14 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001067632 +15 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001067632 + +*RES +0 mem_right_track_8\/FTB_3__28:X mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.01203795 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[1] 0.002362795 //LENGTH 19.545 LUMPCC 0.0002371979 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.485 53.380 +*I mux_bottom_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 34.860 47.600 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 34.675 49.980 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 35.780 42.160 +*N mux_tree_tapbuf_size7_2_sram[1]:4 *C 35.818 42.160 +*N mux_tree_tapbuf_size7_2_sram[1]:5 *C 36.295 42.160 +*N mux_tree_tapbuf_size7_2_sram[1]:6 *C 36.340 42.205 +*N mux_tree_tapbuf_size7_2_sram[1]:7 *C 34.675 49.980 +*N mux_tree_tapbuf_size7_2_sram[1]:8 *C 34.860 47.600 +*N mux_tree_tapbuf_size7_2_sram[1]:9 *C 34.960 47.645 +*N mux_tree_tapbuf_size7_2_sram[1]:10 *C 34.960 49.935 +*N mux_tree_tapbuf_size7_2_sram[1]:11 *C 35.005 49.980 +*N mux_tree_tapbuf_size7_2_sram[1]:12 *C 36.295 49.980 +*N mux_tree_tapbuf_size7_2_sram[1]:13 *C 36.340 49.980 +*N mux_tree_tapbuf_size7_2_sram[1]:14 *C 36.340 53.335 +*N mux_tree_tapbuf_size7_2_sram[1]:15 *C 36.385 53.380 +*N mux_tree_tapbuf_size7_2_sram[1]:16 *C 38.448 53.380 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_2_sram[1]:4 6.721875e-05 +5 mux_tree_tapbuf_size7_2_sram[1]:5 6.721875e-05 +6 mux_tree_tapbuf_size7_2_sram[1]:6 0.0003645662 +7 mux_tree_tapbuf_size7_2_sram[1]:7 4.943144e-05 +8 mux_tree_tapbuf_size7_2_sram[1]:8 3.034609e-05 +9 mux_tree_tapbuf_size7_2_sram[1]:9 0.0001323155 +10 mux_tree_tapbuf_size7_2_sram[1]:10 0.0001323155 +11 mux_tree_tapbuf_size7_2_sram[1]:11 0.0001260711 +12 mux_tree_tapbuf_size7_2_sram[1]:12 0.0001054173 +13 mux_tree_tapbuf_size7_2_sram[1]:13 0.0005790153 +14 mux_tree_tapbuf_size7_2_sram[1]:14 0.0001848572 +15 mux_tree_tapbuf_size7_2_sram[1]:15 0.0001414122 +16 mux_tree_tapbuf_size7_2_sram[1]:16 0.0001414122 +17 mux_tree_tapbuf_size7_2_sram[1]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.613272e-08 +18 mux_tree_tapbuf_size7_2_sram[1]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.613272e-08 +19 mux_tree_tapbuf_size7_2_sram[1]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001185228 +20 mux_tree_tapbuf_size7_2_sram[1]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001185228 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_2_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_2_sram[1]:4 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[1]:5 mux_tree_tapbuf_size7_2_sram[1]:4 0.0004263393 +3 mux_tree_tapbuf_size7_2_sram[1]:6 mux_tree_tapbuf_size7_2_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size7_2_sram[1]:15 mux_tree_tapbuf_size7_2_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size7_2_sram[1]:14 mux_tree_tapbuf_size7_2_sram[1]:13 0.002995536 +6 mux_tree_tapbuf_size7_2_sram[1]:16 mux_tree_tapbuf_size7_2_sram[1]:15 0.001841518 +7 mux_tree_tapbuf_size7_2_sram[1]:11 mux_tree_tapbuf_size7_2_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size7_2_sram[1]:11 mux_tree_tapbuf_size7_2_sram[1]:7 0.0001793479 +9 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:9 0.002044643 +10 mux_tree_tapbuf_size7_2_sram[1]:8 mux_bottom_track_5\/mux_l2_in_1_:S 0.152 +11 mux_tree_tapbuf_size7_2_sram[1]:9 mux_tree_tapbuf_size7_2_sram[1]:8 0.0045 +12 mux_tree_tapbuf_size7_2_sram[1]:7 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:11 0.001151786 +14 mux_tree_tapbuf_size7_2_sram[1]:13 mux_tree_tapbuf_size7_2_sram[1]:12 0.0045 +15 mux_tree_tapbuf_size7_2_sram[1]:13 mux_tree_tapbuf_size7_2_sram[1]:6 0.006941965 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001034201 //LENGTH 7.480 LUMPCC 0.0004274182 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 55.375 47.600 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 51.885 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.922 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 52.395 50.660 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 52.440 50.615 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 52.440 47.645 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 52.485 47.600 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 55.338 47.600 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.65151e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.65151e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001120649 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001120649 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001238112 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001238112 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.931809e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.931809e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 3.4816e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.000119575 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 3.4816e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.000119575 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002546875 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0003091333 //LENGTH 2.480 LUMPCC 0 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_1_:X O *L 0 *C 84.005 44.540 +*I mux_right_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.195 44.540 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 86.157 44.540 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 84.043 44.540 + +*CAP +0 mux_right_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001535666 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001535666 + +*RES +0 mux_right_track_16\/mux_l1_in_1_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001888393 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000464081 //LENGTH 3.515 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_1_:X O *L 0 *C 61.005 42.840 +*I mux_left_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 64.230 42.840 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 64.193 42.840 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 61.043 42.840 + +*CAP +0 mux_left_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002310405 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002310405 + +*RES +0 mux_left_track_1\/mux_l2_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0028125 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002383314 //LENGTH 21.315 LUMPCC 0.0002894608 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_1_:X O *L 0 *C 64.115 56.100 +*I mux_left_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.330 69.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 57.367 69.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 63.435 69.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 63.480 69.655 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 63.480 56.145 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 63.525 56.100 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 64.078 56.100 + +*CAP +0 mux_left_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003701213 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003701213 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000610743 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000610743 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.506238e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.506238e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:384 1.737958e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:397 0.0001273508 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:396 1.737958e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:400 0.0001273508 + +*RES +0 mux_left_track_17\/mux_l1_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.005417411 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0120625 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005419187 //LENGTH 4.480 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_1_:X O *L 0 *C 55.025 22.440 +*I mux_bottom_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.215 21.080 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 57.178 21.080 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 55.705 21.080 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 55.660 21.125 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 55.660 22.395 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 55.615 22.440 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 55.062 22.440 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001177559 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001177559 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.397988e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.397988e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.822357e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.822357e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001314732 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001133929 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00074139 //LENGTH 5.805 LUMPCC 0.0001188729 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_0_:X O *L 0 *C 25.475 36.380 +*I mux_bottom_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 22.640 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 22.678 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 23.875 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 23.920 34.385 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 23.920 36.335 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 23.965 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 25.438 36.380 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.57999e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.57999e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001299084 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001299084 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001145503 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001145503 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size7_1_sram[2]:5 5.943646e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_1_sram[2]:4 5.943646e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001069197 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741071 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007266499 //LENGTH 5.665 LUMPCC 8.981023e-05 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_0_:X O *L 0 *C 27.775 44.540 +*I mux_bottom_track_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 25.760 41.820 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 25.798 41.820 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 26.635 41.820 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 26.680 41.865 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 26.680 44.495 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 26.725 44.540 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 27.738 44.540 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.571508e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.571508e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001694064 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001694064 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.229843e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.229843e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[6]:26 4.490511e-05 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[6]:27 4.490511e-05 + +*RES +0 mux_bottom_track_7\/mux_l1_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0007477679 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_7\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0] 0.009975016 //LENGTH 87.200 LUMPCC 0.0006603771 DR + +*CONN +*I mux_bottom_track_11\/mux_l3_in_0_:X O *L 0 *C 42.145 66.640 +*I mux_bottom_track_11\/BUFT_P_136:A I *L 0.001776 *C 63.020 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 63.058 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 63.895 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 63.940 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 63.933 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 51.068 4.080 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 51.060 4.138 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 51.060 14.915 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 51.015 14.960 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 47.425 14.960 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 47.380 15.005 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 47.380 66.595 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 47.335 66.640 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 42.183 66.640 + +*CAP +0 mux_bottom_track_11\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_11\/BUFT_P_136:A 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.611683e-05 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.611683e-05 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.567338e-05 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0007558776 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0007558776 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000578758 +8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.000578758 +9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002167489 +10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0002167489 +11 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.002661973 +12 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.002661973 +13 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0003290086 +14 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.0003290086 +15 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:218 3.668565e-05 +16 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:324 2.571008e-05 +17 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:323 5.070065e-07 +18 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:324 3.668565e-05 +19 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:325 2.571008e-05 +20 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 prog_clk[0]:322 5.070065e-07 +21 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 prog_clk[0]:416 2.103808e-05 +22 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 prog_clk[0]:420 3.448215e-05 +23 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 prog_clk[0]:532 5.854629e-05 +24 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 prog_clk[0]:419 3.448215e-05 +25 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 prog_clk[0]:446 2.103808e-05 +26 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 prog_clk[0]:531 5.854629e-05 +27 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001532193 +28 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001532193 + +*RES +0 mux_bottom_track_11\/mux_l3_in_0_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_11\/BUFT_P_136:A 0.152 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0007477679 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002015517 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.009622768 +9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.003205357 +10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0045 +11 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +12 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.04606251 +13 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.004600447 + +*END + +*D_NET ropt_net_219 0.0004431621 //LENGTH 3.555 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 135.700 52.360 +*I ropt_mt_inst_837:A I *L 0.001766 *C 134.780 50.320 +*N ropt_net_219:2 *C 134.780 50.320 +*N ropt_net_219:3 *C 135.655 50.320 +*N ropt_net_219:4 *C 135.700 50.365 +*N ropt_net_219:5 *C 135.700 52.315 +*N ropt_net_219:6 *C 135.700 52.360 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 ropt_mt_inst_837:A 1e-06 +2 ropt_net_219:2 9.659954e-05 +3 ropt_net_219:3 6.627196e-05 +4 ropt_net_219:4 0.0001236674 +5 ropt_net_219:5 0.0001236674 +6 ropt_net_219:6 3.095586e-05 + +*RES +0 ropt_mt_inst_798:X ropt_net_219:6 0.152 +1 ropt_net_219:6 ropt_net_219:5 0.0045 +2 ropt_net_219:5 ropt_net_219:4 0.001741072 +3 ropt_net_219:3 ropt_net_219:2 0.00078125 +4 ropt_net_219:4 ropt_net_219:3 0.0045 +5 ropt_net_219:2 ropt_mt_inst_837:A 0.152 + +*END + +*D_NET ropt_net_210 0.001680955 //LENGTH 13.705 LUMPCC 0.0005205939 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 11.695 49.980 +*I ropt_mt_inst_828:A I *L 0.001766 *C 3.220 53.040 +*N ropt_net_210:2 *C 3.258 53.040 +*N ropt_net_210:3 *C 5.015 53.040 +*N ropt_net_210:4 *C 5.060 52.995 +*N ropt_net_210:5 *C 5.060 50.025 +*N ropt_net_210:6 *C 5.105 49.980 +*N ropt_net_210:7 *C 6.900 49.980 +*N ropt_net_210:8 *C 6.900 50.320 +*N ropt_net_210:9 *C 7.360 50.320 +*N ropt_net_210:10 *C 7.360 49.980 +*N ropt_net_210:11 *C 11.658 49.980 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 ropt_mt_inst_828:A 1e-06 +2 ropt_net_210:2 0.0001205212 +3 ropt_net_210:3 0.0001205212 +4 ropt_net_210:4 9.43272e-05 +5 ropt_net_210:5 9.43272e-05 +6 ropt_net_210:6 8.910593e-05 +7 ropt_net_210:7 0.000104095 +8 ropt_net_210:8 4.228644e-05 +9 ropt_net_210:9 4.852657e-05 +10 ropt_net_210:10 0.0002329399 +11 ropt_net_210:11 0.0002117107 +12 ropt_net_210:6 ropt_net_196:3 1.371144e-06 +13 ropt_net_210:11 ropt_net_196:4 6.367533e-05 +14 ropt_net_210:7 ropt_net_196:2 7.335813e-07 +15 ropt_net_210:7 ropt_net_196:4 1.371144e-06 +16 ropt_net_210:8 ropt_net_196:3 2.287294e-05 +17 ropt_net_210:9 ropt_net_196:3 4.956588e-06 +18 ropt_net_210:9 ropt_net_196:4 2.213935e-05 +19 ropt_net_210:10 ropt_net_196:2 4.956588e-06 +20 ropt_net_210:10 ropt_net_196:3 6.367533e-05 +21 ropt_net_210:4 ropt_net_198:4 7.871659e-05 +22 ropt_net_210:5 ropt_net_198:5 7.871659e-05 +23 ropt_net_210:4 ropt_net_203:5 4.294967e-05 +24 ropt_net_210:6 ropt_net_203:2 4.575466e-05 +25 ropt_net_210:5 ropt_net_203:4 4.294967e-05 +26 ropt_net_210:7 ropt_net_203:3 4.575466e-05 + +*RES +0 ropt_mt_inst_816:X ropt_net_210:11 0.152 +1 ropt_net_210:2 ropt_mt_inst_828:A 0.152 +2 ropt_net_210:3 ropt_net_210:2 0.001569196 +3 ropt_net_210:4 ropt_net_210:3 0.0045 +4 ropt_net_210:6 ropt_net_210:5 0.0045 +5 ropt_net_210:5 ropt_net_210:4 0.002651786 +6 ropt_net_210:11 ropt_net_210:10 0.003837054 +7 ropt_net_210:7 ropt_net_210:6 0.001602679 +8 ropt_net_210:8 ropt_net_210:7 0.0003035715 +9 ropt_net_210:9 ropt_net_210:8 0.0004107143 +10 ropt_net_210:10 ropt_net_210:9 0.0003035715 + +*END + +*D_NET chanx_right_in[18] 0.01979067 //LENGTH 166.815 LUMPCC 0.001285402 DR + +*CONN +*P chanx_right_in[18] I *L 0.29796 *C 140.450 39.440 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.550 82.280 +*I BUFT_RR_84:A I *L 0.001776 *C 20.700 82.960 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 104.785 39.780 +*N chanx_right_in[18]:4 *C 104.823 39.780 +*N chanx_right_in[18]:5 *C 105.340 39.780 +*N chanx_right_in[18]:6 *C 20.700 82.922 +*N chanx_right_in[18]:7 *C 20.700 82.280 +*N chanx_right_in[18]:8 *C 60.550 82.280 +*N chanx_right_in[18]:9 *C 68.955 82.280 +*N chanx_right_in[18]:10 *C 69.000 82.235 +*N chanx_right_in[18]:11 *C 69.000 77.225 +*N chanx_right_in[18]:12 *C 69.045 77.180 +*N chanx_right_in[18]:13 *C 105.295 77.180 +*N chanx_right_in[18]:14 *C 105.340 77.135 +*N chanx_right_in[18]:15 *C 105.340 40.165 +*N chanx_right_in[18]:16 *C 105.340 40.120 +*N chanx_right_in[18]:17 *C 136.115 40.120 +*N chanx_right_in[18]:18 *C 136.160 40.075 +*N chanx_right_in[18]:19 *C 136.160 39.498 +*N chanx_right_in[18]:20 *C 136.168 39.440 + +*CAP +0 chanx_right_in[18] 0.0003711786 +1 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +2 BUFT_RR_84:A 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +4 chanx_right_in[18]:4 5.047019e-05 +5 chanx_right_in[18]:5 7.764823e-05 +6 chanx_right_in[18]:6 5.278789e-05 +7 chanx_right_in[18]:7 0.002295347 +8 chanx_right_in[18]:8 0.002786641 +9 chanx_right_in[18]:9 0.0005150989 +10 chanx_right_in[18]:10 0.0002853115 +11 chanx_right_in[18]:11 0.0002853115 +12 chanx_right_in[18]:12 0.00189704 +13 chanx_right_in[18]:13 0.00189704 +14 chanx_right_in[18]:14 0.001928429 +15 chanx_right_in[18]:15 0.001928429 +16 chanx_right_in[18]:16 0.001844665 +17 chanx_right_in[18]:17 0.001817487 +18 chanx_right_in[18]:18 4.910338e-05 +19 chanx_right_in[18]:19 4.910338e-05 +20 chanx_right_in[18]:20 0.0003711786 +21 chanx_right_in[18]:10 mux_tree_tapbuf_size4_3_sram[2]:13 1.238438e-06 +22 chanx_right_in[18]:12 mux_tree_tapbuf_size4_3_sram[2]:10 0.0001491672 +23 chanx_right_in[18]:11 mux_tree_tapbuf_size4_3_sram[2]:12 1.238438e-06 +24 chanx_right_in[18]:13 mux_tree_tapbuf_size4_3_sram[2]:11 0.0001491672 +25 chanx_right_in[18]:16 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.0001037884 +26 chanx_right_in[18]:17 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.0001037884 +27 chanx_right_in[18]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:9 6.847346e-05 +28 chanx_right_in[18]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003200336 +29 chanx_right_in[18]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.847346e-05 +30 chanx_right_in[18]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003200336 + +*RES +0 chanx_right_in[18] chanx_right_in[18]:20 0.000670925 +1 chanx_right_in[18]:9 chanx_right_in[18]:8 0.007504465 +2 chanx_right_in[18]:10 chanx_right_in[18]:9 0.0045 +3 chanx_right_in[18]:12 chanx_right_in[18]:11 0.0045 +4 chanx_right_in[18]:11 chanx_right_in[18]:10 0.004473215 +5 chanx_right_in[18]:13 chanx_right_in[18]:12 0.03236607 +6 chanx_right_in[18]:14 chanx_right_in[18]:13 0.0045 +7 chanx_right_in[18]:16 chanx_right_in[18]:15 0.0045 +8 chanx_right_in[18]:16 chanx_right_in[18]:5 0.0003035715 +9 chanx_right_in[18]:15 chanx_right_in[18]:14 0.03300893 +10 chanx_right_in[18]:6 BUFT_RR_84:A 0.152 +11 chanx_right_in[18]:4 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +12 chanx_right_in[18]:17 chanx_right_in[18]:16 0.02747768 +13 chanx_right_in[18]:18 chanx_right_in[18]:17 0.0045 +14 chanx_right_in[18]:19 chanx_right_in[18]:18 0.000515625 +15 chanx_right_in[18]:20 chanx_right_in[18]:19 0.00341 +16 chanx_right_in[18]:8 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +17 chanx_right_in[18]:8 chanx_right_in[18]:7 0.03558036 +18 chanx_right_in[18]:7 chanx_right_in[18]:6 0.0005736608 +19 chanx_right_in[18]:5 chanx_right_in[18]:4 0.0004620536 + +*END + +*D_NET chany_bottom_in[14] 0.01001402 //LENGTH 77.590 LUMPCC 0.0007922254 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 66.240 1.290 +*I mux_right_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 90.720 45.220 +*I mux_left_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 75.805 47.260 +*N chany_bottom_in[14]:3 *C 75.843 47.260 +*N chany_bottom_in[14]:4 *C 78.155 47.260 +*N chany_bottom_in[14]:5 *C 78.200 47.215 +*N chany_bottom_in[14]:6 *C 90.758 45.220 +*N chany_bottom_in[14]:7 *C 91.080 45.220 +*N chany_bottom_in[14]:8 *C 91.080 45.560 +*N chany_bottom_in[14]:9 *C 78.245 45.560 +*N chany_bottom_in[14]:10 *C 78.200 45.605 +*N chany_bottom_in[14]:11 *C 78.200 46.240 +*N chany_bottom_in[14]:12 *C 78.193 46.240 +*N chany_bottom_in[14]:13 *C 74.068 46.240 +*N chany_bottom_in[14]:14 *C 74.060 46.183 +*N chany_bottom_in[14]:15 *C 74.060 15.345 +*N chany_bottom_in[14]:16 *C 74.015 15.300 +*N chany_bottom_in[14]:17 *C 72.725 15.300 +*N chany_bottom_in[14]:18 *C 72.680 15.255 +*N chany_bottom_in[14]:19 *C 72.680 10.245 +*N chany_bottom_in[14]:20 *C 72.635 10.200 +*N chany_bottom_in[14]:21 *C 66.285 10.200 +*N chany_bottom_in[14]:22 *C 66.240 10.155 + +*CAP +0 chany_bottom_in[14] 0.0004450874 +1 mux_right_track_24\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_3\/mux_l2_in_1_:A1 1e-06 +3 chany_bottom_in[14]:3 0.0001847247 +4 chany_bottom_in[14]:4 0.0001847247 +5 chany_bottom_in[14]:5 6.613545e-05 +6 chany_bottom_in[14]:6 2.127199e-05 +7 chany_bottom_in[14]:7 4.63788e-05 +8 chany_bottom_in[14]:8 0.0009702939 +9 chany_bottom_in[14]:9 0.0009451871 +10 chany_bottom_in[14]:10 4.707947e-05 +11 chany_bottom_in[14]:11 0.0001524406 +12 chany_bottom_in[14]:12 0.0004989997 +13 chany_bottom_in[14]:13 0.0004989997 +14 chany_bottom_in[14]:14 0.001520407 +15 chany_bottom_in[14]:15 0.001520407 +16 chany_bottom_in[14]:16 0.0001244898 +17 chany_bottom_in[14]:17 0.0001244898 +18 chany_bottom_in[14]:18 0.0002892774 +19 chany_bottom_in[14]:19 0.0002892774 +20 chany_bottom_in[14]:20 0.0004225185 +21 chany_bottom_in[14]:21 0.0004225185 +22 chany_bottom_in[14]:22 0.0004450874 +23 chany_bottom_in[14] chany_bottom_in[13] 1.599008e-05 +24 chany_bottom_in[14]:14 chany_bottom_in[13]:11 0.0002883946 +25 chany_bottom_in[14]:15 chany_bottom_in[13]:12 0.0002883946 +26 chany_bottom_in[14]:20 chany_bottom_in[13]:13 5.013685e-06 +27 chany_bottom_in[14]:21 chany_bottom_in[13]:14 5.013685e-06 +28 chany_bottom_in[14]:22 chany_bottom_in[13]:15 1.599008e-05 +29 chany_bottom_in[14] mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.671432e-05 +30 chany_bottom_in[14]:22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.671432e-05 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:22 0.007915178 +1 chany_bottom_in[14]:4 chany_bottom_in[14]:3 0.002064732 +2 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.0045 +3 chany_bottom_in[14]:3 mux_left_track_3\/mux_l2_in_1_:A1 0.152 +4 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.01145982 +5 chany_bottom_in[14]:10 chany_bottom_in[14]:9 0.0045 +6 chany_bottom_in[14]:6 mux_right_track_24\/mux_l1_in_1_:A1 0.152 +7 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.0005669643 +8 chany_bottom_in[14]:11 chany_bottom_in[14]:5 0.0008705358 +9 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.00341 +10 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.00341 +11 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.00064625 +12 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.0045 +13 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.02753348 +14 chany_bottom_in[14]:17 chany_bottom_in[14]:16 0.001151786 +15 chany_bottom_in[14]:18 chany_bottom_in[14]:17 0.0045 +16 chany_bottom_in[14]:20 chany_bottom_in[14]:19 0.0045 +17 chany_bottom_in[14]:19 chany_bottom_in[14]:18 0.004473215 +18 chany_bottom_in[14]:21 chany_bottom_in[14]:20 0.005669643 +19 chany_bottom_in[14]:22 chany_bottom_in[14]:21 0.0045 +20 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.0003035715 +21 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.0002879465 + +*END + +*D_NET chanx_left_in[0] 0.008388818 //LENGTH 74.320 LUMPCC 0.001458979 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.230 39.440 +*I mux_bottom_track_39\/mux_l1_in_0_:A0 I *L 0.001631 *C 46.155 11.560 +*N chanx_left_in[0]:2 *C 46.117 11.560 +*N chanx_left_in[0]:3 *C 40.985 11.560 +*N chanx_left_in[0]:4 *C 40.940 11.605 +*N chanx_left_in[0]:5 *C 40.940 29.183 +*N chanx_left_in[0]:6 *C 40.933 29.240 +*N chanx_left_in[0]:7 *C 3.688 29.240 +*N chanx_left_in[0]:8 *C 3.680 29.298 +*N chanx_left_in[0]:9 *C 3.680 39.383 +*N chanx_left_in[0]:10 *C 3.673 39.440 + +*CAP +0 chanx_left_in[0] 0.0001686684 +1 mux_bottom_track_39\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[0]:2 0.0003553093 +3 chanx_left_in[0]:3 0.0003553093 +4 chanx_left_in[0]:4 0.0008577898 +5 chanx_left_in[0]:5 0.0008577898 +6 chanx_left_in[0]:6 0.001591234 +7 chanx_left_in[0]:7 0.001591234 +8 chanx_left_in[0]:8 0.0004914182 +9 chanx_left_in[0]:9 0.0004914182 +10 chanx_left_in[0]:10 0.0001686684 +11 chanx_left_in[0]:4 prog_clk[0]:505 2.55593e-05 +12 chanx_left_in[0]:4 prog_clk[0]:539 3.992579e-05 +13 chanx_left_in[0]:5 prog_clk[0]:538 3.992579e-05 +14 chanx_left_in[0]:5 prog_clk[0]:544 2.55593e-05 +15 chanx_left_in[0]:6 prog_clk[0]:497 0.0001969952 +16 chanx_left_in[0]:7 prog_clk[0]:496 0.0001969952 +17 chanx_left_in[0]:6 bottom_left_grid_pin_34_[0]:20 0.0001290154 +18 chanx_left_in[0]:6 bottom_left_grid_pin_34_[0]:25 7.488217e-05 +19 chanx_left_in[0]:6 bottom_left_grid_pin_34_[0]:26 1.567873e-05 +20 chanx_left_in[0]:6 bottom_left_grid_pin_34_[0]:29 4.017739e-05 +21 chanx_left_in[0]:7 bottom_left_grid_pin_34_[0]:25 0.0001290154 +22 chanx_left_in[0]:7 bottom_left_grid_pin_34_[0]:26 7.488217e-05 +23 chanx_left_in[0]:7 bottom_left_grid_pin_34_[0]:27 1.567873e-05 +24 chanx_left_in[0]:7 bottom_left_grid_pin_34_[0]:28 4.017739e-05 +25 chanx_left_in[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.846678e-05 +26 chanx_left_in[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.846678e-05 +27 chanx_left_in[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001487889 +28 chanx_left_in[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0001487889 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:10 0.0003826583 +1 chanx_left_in[0]:2 mux_bottom_track_39\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[0]:3 chanx_left_in[0]:2 0.004582589 +3 chanx_left_in[0]:4 chanx_left_in[0]:3 0.0045 +4 chanx_left_in[0]:5 chanx_left_in[0]:4 0.0156942 +5 chanx_left_in[0]:6 chanx_left_in[0]:5 0.00341 +6 chanx_left_in[0]:8 chanx_left_in[0]:7 0.00341 +7 chanx_left_in[0]:7 chanx_left_in[0]:6 0.00583505 +8 chanx_left_in[0]:9 chanx_left_in[0]:8 0.009004464 +9 chanx_left_in[0]:10 chanx_left_in[0]:9 0.00341 + +*END + +*D_NET ropt_net_179 0.002645815 //LENGTH 18.405 LUMPCC 0.0004103971 DR + +*CONN +*I mux_bottom_track_1\/BUFT_P_133:X O *L 0 *C 74.520 10.200 +*I ropt_mt_inst_799:A I *L 0.001766 *C 84.180 9.520 +*N ropt_net_179:2 *C 84.180 9.520 +*N ropt_net_179:3 *C 84.180 9.475 +*N ropt_net_179:4 *C 84.180 6.165 +*N ropt_net_179:5 *C 84.135 6.120 +*N ropt_net_179:6 *C 77.325 6.120 +*N ropt_net_179:7 *C 77.280 6.165 +*N ropt_net_179:8 *C 77.280 10.155 +*N ropt_net_179:9 *C 77.235 10.200 +*N ropt_net_179:10 *C 74.558 10.200 + +*CAP +0 mux_bottom_track_1\/BUFT_P_133:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_179:2 3.588754e-05 +3 ropt_net_179:3 0.0001440836 +4 ropt_net_179:4 0.0001440836 +5 ropt_net_179:5 0.0005508172 +6 ropt_net_179:6 0.0005508172 +7 ropt_net_179:7 0.0001779788 +8 ropt_net_179:8 0.0001779788 +9 ropt_net_179:9 0.0002258859 +10 ropt_net_179:10 0.0002258859 +11 ropt_net_179:4 chany_bottom_in[16]:22 9.539266e-05 +12 ropt_net_179:3 chany_bottom_in[16]:21 9.539266e-05 +13 ropt_net_179:8 optlc_net_166:26 0.0001098059 +14 ropt_net_179:7 optlc_net_166:25 0.0001098059 + +*RES +0 mux_bottom_track_1\/BUFT_P_133:X ropt_net_179:10 0.152 +1 ropt_net_179:10 ropt_net_179:9 0.002390625 +2 ropt_net_179:9 ropt_net_179:8 0.0045 +3 ropt_net_179:8 ropt_net_179:7 0.0035625 +4 ropt_net_179:6 ropt_net_179:5 0.006080357 +5 ropt_net_179:7 ropt_net_179:6 0.0045 +6 ropt_net_179:5 ropt_net_179:4 0.0045 +7 ropt_net_179:4 ropt_net_179:3 0.002955357 +8 ropt_net_179:2 ropt_mt_inst_799:A 0.152 +9 ropt_net_179:3 ropt_net_179:2 0.0045 + +*END + +*D_NET chany_bottom_out[16] 0.000887107 //LENGTH 7.090 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 63.020 6.460 +*P chany_bottom_out[16] O *L 0.7423 *C 64.400 1.325 +*N chany_bottom_out[16]:2 *C 64.400 6.460 +*N chany_bottom_out[16]:3 *C 63.940 6.460 +*N chany_bottom_out[16]:4 *C 63.895 6.460 +*N chany_bottom_out[16]:5 *C 63.058 6.460 + +*CAP +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[16] 0.0003060494 +2 chany_bottom_out[16]:2 0.0003415936 +3 chany_bottom_out[16]:3 6.945786e-05 +4 chany_bottom_out[16]:4 8.450304e-05 +5 chany_bottom_out[16]:5 8.450304e-05 + +*RES +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[16]:5 0.152 +1 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.0045 +2 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0004107143 +3 chany_bottom_out[16]:5 chany_bottom_out[16]:4 0.0007477679 +4 chany_bottom_out[16]:2 chany_bottom_out[16] 0.004584821 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.001002032 //LENGTH 8.180 LUMPCC 0.0001851436 DR + +*CONN +*I mem_bottom_track_31\/FTB_30__55:X O *L 0 *C 85.785 17.680 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 81.595 20.740 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 81.633 20.740 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 83.675 20.740 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 83.720 20.695 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 83.720 17.725 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 83.765 17.680 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 85.748 17.680 + +*CAP +0 mem_bottom_track_31\/FTB_30__55:X 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.00014801 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.00014801 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.0001293621 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0001293621 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.000130072 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.000130072 +8 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.65079e-06 +9 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.65079e-06 +10 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.592099e-05 +11 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.592099e-05 + +*RES +0 mem_bottom_track_31\/FTB_30__55:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.001770089 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.001823661 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_3_ccff_tail[0] 0.0006788695 //LENGTH 5.070 LUMPCC 0.0001069778 DR + +*CONN +*I mem_bottom_track_17\/FTB_16__41:X O *L 0 *C 64.120 20.740 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 61.825 22.780 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 *C 61.863 22.780 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 *C 63.895 22.780 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 *C 63.940 22.735 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 *C 63.940 20.785 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 *C 63.940 20.740 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 *C 64.120 20.740 + +*CAP +0 mem_bottom_track_17\/FTB_16__41:X 1e-06 +1 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.000125893 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.000125893 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.0001086552 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0001086552 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 5.035595e-05 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 5.043931e-05 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 prog_clk[0]:303 3.781642e-05 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 prog_clk[0]:304 3.781642e-05 +10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 prog_clk[0]:301 1.626457e-06 +11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 prog_clk[0]:305 1.404603e-05 +12 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 prog_clk[0]:305 1.626457e-06 +13 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 prog_clk[0]:311 1.404603e-05 + +*RES +0 mem_bottom_track_17\/FTB_16__41:X mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.001814732 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.001741071 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 9.782609e-05 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[1] 0.00290995 //LENGTH 23.480 LUMPCC 0.0002029282 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 102.885 33.660 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 94.400 30.600 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 98.615 22.780 +*I mux_bottom_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 103.600 31.280 +*N mux_tree_tapbuf_size4_2_sram[1]:4 *C 103.600 31.280 +*N mux_tree_tapbuf_size4_2_sram[1]:5 *C 103.500 31.620 +*N mux_tree_tapbuf_size4_2_sram[1]:6 *C 98.653 22.780 +*N mux_tree_tapbuf_size4_2_sram[1]:7 *C 99.775 22.780 +*N mux_tree_tapbuf_size4_2_sram[1]:8 *C 99.820 22.825 +*N mux_tree_tapbuf_size4_2_sram[1]:9 *C 94.438 30.600 +*N mux_tree_tapbuf_size4_2_sram[1]:10 *C 99.775 30.600 +*N mux_tree_tapbuf_size4_2_sram[1]:11 *C 99.820 30.600 +*N mux_tree_tapbuf_size4_2_sram[1]:12 *C 99.820 31.575 +*N mux_tree_tapbuf_size4_2_sram[1]:13 *C 99.865 31.620 +*N mux_tree_tapbuf_size4_2_sram[1]:14 *C 103.040 31.620 +*N mux_tree_tapbuf_size4_2_sram[1]:15 *C 103.040 31.665 +*N mux_tree_tapbuf_size4_2_sram[1]:16 *C 103.040 33.615 +*N mux_tree_tapbuf_size4_2_sram[1]:17 *C 103.040 33.660 +*N mux_tree_tapbuf_size4_2_sram[1]:18 *C 102.885 33.660 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_25\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size4_2_sram[1]:4 5.431825e-05 +5 mux_tree_tapbuf_size4_2_sram[1]:5 5.722266e-05 +6 mux_tree_tapbuf_size4_2_sram[1]:6 8.997225e-05 +7 mux_tree_tapbuf_size4_2_sram[1]:7 8.997225e-05 +8 mux_tree_tapbuf_size4_2_sram[1]:8 0.0004381316 +9 mux_tree_tapbuf_size4_2_sram[1]:9 0.0003029375 +10 mux_tree_tapbuf_size4_2_sram[1]:10 0.0003029375 +11 mux_tree_tapbuf_size4_2_sram[1]:11 0.000537323 +12 mux_tree_tapbuf_size4_2_sram[1]:12 6.457601e-05 +13 mux_tree_tapbuf_size4_2_sram[1]:13 0.0001849546 +14 mux_tree_tapbuf_size4_2_sram[1]:14 0.0002376221 +15 mux_tree_tapbuf_size4_2_sram[1]:15 0.0001182192 +16 mux_tree_tapbuf_size4_2_sram[1]:16 0.0001182192 +17 mux_tree_tapbuf_size4_2_sram[1]:17 5.604704e-05 +18 mux_tree_tapbuf_size4_2_sram[1]:18 5.05683e-05 +19 mux_tree_tapbuf_size4_2_sram[1]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.326287e-06 +20 mux_tree_tapbuf_size4_2_sram[1]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.913781e-05 +21 mux_tree_tapbuf_size4_2_sram[1]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.326287e-06 +22 mux_tree_tapbuf_size4_2_sram[1]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.913781e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_2_sram[1]:18 0.152 +1 mux_tree_tapbuf_size4_2_sram[1]:13 mux_tree_tapbuf_size4_2_sram[1]:12 0.0045 +2 mux_tree_tapbuf_size4_2_sram[1]:12 mux_tree_tapbuf_size4_2_sram[1]:11 0.0008705358 +3 mux_tree_tapbuf_size4_2_sram[1]:4 mux_bottom_track_25\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size4_2_sram[1]:10 mux_tree_tapbuf_size4_2_sram[1]:9 0.004765625 +5 mux_tree_tapbuf_size4_2_sram[1]:11 mux_tree_tapbuf_size4_2_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size4_2_sram[1]:11 mux_tree_tapbuf_size4_2_sram[1]:8 0.006941964 +7 mux_tree_tapbuf_size4_2_sram[1]:9 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_2_sram[1]:7 mux_tree_tapbuf_size4_2_sram[1]:6 0.001002232 +9 mux_tree_tapbuf_size4_2_sram[1]:8 mux_tree_tapbuf_size4_2_sram[1]:7 0.0045 +10 mux_tree_tapbuf_size4_2_sram[1]:6 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size4_2_sram[1]:14 mux_tree_tapbuf_size4_2_sram[1]:13 0.002834822 +12 mux_tree_tapbuf_size4_2_sram[1]:14 mux_tree_tapbuf_size4_2_sram[1]:5 0.0004107143 +13 mux_tree_tapbuf_size4_2_sram[1]:15 mux_tree_tapbuf_size4_2_sram[1]:14 0.0045 +14 mux_tree_tapbuf_size4_2_sram[1]:17 mux_tree_tapbuf_size4_2_sram[1]:16 0.0045 +15 mux_tree_tapbuf_size4_2_sram[1]:16 mux_tree_tapbuf_size4_2_sram[1]:15 0.001741072 +16 mux_tree_tapbuf_size4_2_sram[1]:18 mux_tree_tapbuf_size4_2_sram[1]:17 8.423914e-05 +17 mux_tree_tapbuf_size4_2_sram[1]:5 mux_tree_tapbuf_size4_2_sram[1]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_5_sram[1] 0.003766035 //LENGTH 32.310 LUMPCC 0.0003299257 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.125 64.260 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 43.875 71.740 +*I mux_left_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 42.420 78.200 +*I mux_left_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 56.220 68.680 +*N mux_tree_tapbuf_size5_5_sram[1]:4 *C 56.183 68.680 +*N mux_tree_tapbuf_size5_5_sram[1]:5 *C 42.458 78.200 +*N mux_tree_tapbuf_size5_5_sram[1]:6 *C 45.495 78.200 +*N mux_tree_tapbuf_size5_5_sram[1]:7 *C 45.540 78.155 +*N mux_tree_tapbuf_size5_5_sram[1]:8 *C 43.913 71.740 +*N mux_tree_tapbuf_size5_5_sram[1]:9 *C 45.495 71.740 +*N mux_tree_tapbuf_size5_5_sram[1]:10 *C 45.540 71.740 +*N mux_tree_tapbuf_size5_5_sram[1]:11 *C 45.540 69.405 +*N mux_tree_tapbuf_size5_5_sram[1]:12 *C 45.585 69.360 +*N mux_tree_tapbuf_size5_5_sram[1]:13 *C 54.740 69.360 +*N mux_tree_tapbuf_size5_5_sram[1]:14 *C 54.740 68.680 +*N mux_tree_tapbuf_size5_5_sram[1]:15 *C 54.740 68.635 +*N mux_tree_tapbuf_size5_5_sram[1]:16 *C 54.740 64.305 +*N mux_tree_tapbuf_size5_5_sram[1]:17 *C 54.695 64.260 +*N mux_tree_tapbuf_size5_5_sram[1]:18 *C 54.163 64.260 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_17\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_17\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_5_sram[1]:4 0.0001208977 +5 mux_tree_tapbuf_size5_5_sram[1]:5 0.0002446308 +6 mux_tree_tapbuf_size5_5_sram[1]:6 0.0002446308 +7 mux_tree_tapbuf_size5_5_sram[1]:7 0.0003594217 +8 mux_tree_tapbuf_size5_5_sram[1]:8 0.0001210678 +9 mux_tree_tapbuf_size5_5_sram[1]:9 0.0001210678 +10 mux_tree_tapbuf_size5_5_sram[1]:10 0.0005188285 +11 mux_tree_tapbuf_size5_5_sram[1]:11 0.0001271082 +12 mux_tree_tapbuf_size5_5_sram[1]:12 0.0003770257 +13 mux_tree_tapbuf_size5_5_sram[1]:13 0.0004219294 +14 mux_tree_tapbuf_size5_5_sram[1]:14 0.0001658014 +15 mux_tree_tapbuf_size5_5_sram[1]:15 0.0002543358 +16 mux_tree_tapbuf_size5_5_sram[1]:16 0.0002543358 +17 mux_tree_tapbuf_size5_5_sram[1]:17 5.051393e-05 +18 mux_tree_tapbuf_size5_5_sram[1]:18 5.051393e-05 +19 mux_tree_tapbuf_size5_5_sram[1]:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001649629 +20 mux_tree_tapbuf_size5_5_sram[1]:13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001649629 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_5_sram[1]:18 0.152 +1 mux_tree_tapbuf_size5_5_sram[1]:12 mux_tree_tapbuf_size5_5_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size5_5_sram[1]:11 mux_tree_tapbuf_size5_5_sram[1]:10 0.002084822 +3 mux_tree_tapbuf_size5_5_sram[1]:6 mux_tree_tapbuf_size5_5_sram[1]:5 0.002712054 +4 mux_tree_tapbuf_size5_5_sram[1]:7 mux_tree_tapbuf_size5_5_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size5_5_sram[1]:5 mux_left_track_17\/mux_l2_in_1_:S 0.152 +6 mux_tree_tapbuf_size5_5_sram[1]:4 mux_left_track_17\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size5_5_sram[1]:9 mux_tree_tapbuf_size5_5_sram[1]:8 0.001412946 +8 mux_tree_tapbuf_size5_5_sram[1]:10 mux_tree_tapbuf_size5_5_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size5_5_sram[1]:10 mux_tree_tapbuf_size5_5_sram[1]:7 0.005727679 +10 mux_tree_tapbuf_size5_5_sram[1]:8 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size5_5_sram[1]:14 mux_tree_tapbuf_size5_5_sram[1]:13 0.000607143 +12 mux_tree_tapbuf_size5_5_sram[1]:14 mux_tree_tapbuf_size5_5_sram[1]:4 0.001287947 +13 mux_tree_tapbuf_size5_5_sram[1]:15 mux_tree_tapbuf_size5_5_sram[1]:14 0.0045 +14 mux_tree_tapbuf_size5_5_sram[1]:17 mux_tree_tapbuf_size5_5_sram[1]:16 0.0045 +15 mux_tree_tapbuf_size5_5_sram[1]:16 mux_tree_tapbuf_size5_5_sram[1]:15 0.003866072 +16 mux_tree_tapbuf_size5_5_sram[1]:18 mux_tree_tapbuf_size5_5_sram[1]:17 0.0004754465 +17 mux_tree_tapbuf_size5_5_sram[1]:13 mux_tree_tapbuf_size5_5_sram[1]:12 0.008174107 + +*END + +*D_NET mux_tree_tapbuf_size6_4_sram[1] 0.003933631 //LENGTH 25.080 LUMPCC 0.0009395567 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.545 58.480 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 51.695 55.420 +*I mux_left_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 57.600 51.000 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 58.980 52.700 +*N mux_tree_tapbuf_size6_4_sram[1]:4 *C 58.880 52.700 +*N mux_tree_tapbuf_size6_4_sram[1]:5 *C 58.880 52.700 +*N mux_tree_tapbuf_size6_4_sram[1]:6 *C 57.615 51.000 +*N mux_tree_tapbuf_size6_4_sram[1]:7 *C 57.938 51.000 +*N mux_tree_tapbuf_size6_4_sram[1]:8 *C 57.960 51.045 +*N mux_tree_tapbuf_size6_4_sram[1]:9 *C 57.960 52.700 +*N mux_tree_tapbuf_size6_4_sram[1]:10 *C 51.733 55.420 +*N mux_tree_tapbuf_size6_4_sram[1]:11 *C 57.915 55.420 +*N mux_tree_tapbuf_size6_4_sram[1]:12 *C 57.960 55.420 +*N mux_tree_tapbuf_size6_4_sram[1]:13 *C 57.960 58.422 +*N mux_tree_tapbuf_size6_4_sram[1]:14 *C 57.968 58.480 +*N mux_tree_tapbuf_size6_4_sram[1]:15 *C 66.233 58.480 +*N mux_tree_tapbuf_size6_4_sram[1]:16 *C 66.240 58.480 +*N mux_tree_tapbuf_size6_4_sram[1]:17 *C 66.240 58.480 +*N mux_tree_tapbuf_size6_4_sram[1]:18 *C 66.545 58.480 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_9\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_9\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size6_4_sram[1]:4 3.355162e-05 +5 mux_tree_tapbuf_size6_4_sram[1]:5 8.864973e-05 +6 mux_tree_tapbuf_size6_4_sram[1]:6 4.838177e-05 +7 mux_tree_tapbuf_size6_4_sram[1]:7 4.838177e-05 +8 mux_tree_tapbuf_size6_4_sram[1]:8 9.61928e-05 +9 mux_tree_tapbuf_size6_4_sram[1]:9 0.0002986913 +10 mux_tree_tapbuf_size6_4_sram[1]:10 0.0004869239 +11 mux_tree_tapbuf_size6_4_sram[1]:11 0.0004869239 +12 mux_tree_tapbuf_size6_4_sram[1]:12 0.0003568587 +13 mux_tree_tapbuf_size6_4_sram[1]:13 0.0001771573 +14 mux_tree_tapbuf_size6_4_sram[1]:14 0.0003640259 +15 mux_tree_tapbuf_size6_4_sram[1]:15 0.0003640259 +16 mux_tree_tapbuf_size6_4_sram[1]:16 3.707862e-05 +17 mux_tree_tapbuf_size6_4_sram[1]:17 5.380254e-05 +18 mux_tree_tapbuf_size6_4_sram[1]:18 4.942879e-05 +19 mux_tree_tapbuf_size6_4_sram[1]:14 chanx_left_in[17]:31 0.0004697784 +20 mux_tree_tapbuf_size6_4_sram[1]:15 chanx_left_in[17]:30 0.0004697784 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_4_sram[1]:18 0.152 +1 mux_tree_tapbuf_size6_4_sram[1]:4 mux_left_track_9\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_4_sram[1]:5 mux_tree_tapbuf_size6_4_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size6_4_sram[1]:7 mux_tree_tapbuf_size6_4_sram[1]:6 0.0001752718 +4 mux_tree_tapbuf_size6_4_sram[1]:8 mux_tree_tapbuf_size6_4_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size6_4_sram[1]:6 mux_left_track_9\/mux_l2_in_1_:S 0.152 +6 mux_tree_tapbuf_size6_4_sram[1]:11 mux_tree_tapbuf_size6_4_sram[1]:10 0.00552009 +7 mux_tree_tapbuf_size6_4_sram[1]:12 mux_tree_tapbuf_size6_4_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size6_4_sram[1]:12 mux_tree_tapbuf_size6_4_sram[1]:9 0.002428571 +9 mux_tree_tapbuf_size6_4_sram[1]:10 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size6_4_sram[1]:13 mux_tree_tapbuf_size6_4_sram[1]:12 0.002680804 +11 mux_tree_tapbuf_size6_4_sram[1]:14 mux_tree_tapbuf_size6_4_sram[1]:13 0.00341 +12 mux_tree_tapbuf_size6_4_sram[1]:16 mux_tree_tapbuf_size6_4_sram[1]:15 0.00341 +13 mux_tree_tapbuf_size6_4_sram[1]:15 mux_tree_tapbuf_size6_4_sram[1]:14 0.00129485 +14 mux_tree_tapbuf_size6_4_sram[1]:17 mux_tree_tapbuf_size6_4_sram[1]:16 0.0045 +15 mux_tree_tapbuf_size6_4_sram[1]:18 mux_tree_tapbuf_size6_4_sram[1]:17 0.0001657609 +16 mux_tree_tapbuf_size6_4_sram[1]:9 mux_tree_tapbuf_size6_4_sram[1]:8 0.001477679 +17 mux_tree_tapbuf_size6_4_sram[1]:9 mux_tree_tapbuf_size6_4_sram[1]:5 0.0008214286 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_3_ccff_tail[0] 0.0007863548 //LENGTH 6.540 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_7\/FTB_23__48:X O *L 0 *C 20.020 56.440 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 18.575 60.860 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 *C 18.613 60.860 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 *C 19.735 60.860 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 *C 19.780 60.815 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 *C 19.780 56.485 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 *C 19.780 56.440 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 *C 20.020 56.440 + +*CAP +0 mem_bottom_track_7\/FTB_23__48:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 8.86527e-05 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 8.86527e-05 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.0002470192 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.0002470192 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 5.51707e-05 +7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 5.784045e-05 + +*RES +0 mem_bottom_track_7\/FTB_23__48:X mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 0.001002232 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.003866071 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 0.0001304348 + +*END + +*D_NET mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001334944 //LENGTH 10.125 LUMPCC 0.0006205406 DR + +*CONN +*I mux_right_track_4\/mux_l2_in_1_:X O *L 0 *C 104.245 60.860 +*I mux_right_track_4\/mux_l3_in_0_:A0 I *L 0.00199 *C 114.080 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 114.043 60.860 +*N mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 104.282 60.860 + +*CAP +0 mux_right_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_right_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003562016 +3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003562016 +4 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000285183 +5 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.50873e-05 +6 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000285183 +7 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.50873e-05 + +*RES +0 mux_right_track_4\/mux_l2_in_1_:X mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.008714286 +2 mux_right_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_right_track_4\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0004396863 //LENGTH 2.935 LUMPCC 0.0001060444 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_1_:X O *L 0 *C 45.255 44.540 +*I mux_left_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 42.610 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 42.648 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 45.218 44.540 + +*CAP +0 mux_left_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000165821 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000165821 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size6_3_sram[2]:4 2.945677e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size6_3_sram[2]:8 2.356542e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size6_3_sram[2]:8 2.945677e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size6_3_sram[2]:9 2.356542e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002294643 + +*END + +*D_NET mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007127958 //LENGTH 5.360 LUMPCC 0.0001489826 DR + +*CONN +*I mux_right_track_16\/mux_l1_in_0_:X O *L 0 *C 84.465 42.500 +*I mux_right_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 86.580 45.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 86.480 45.220 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 86.480 45.175 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 86.480 42.545 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 86.435 42.500 +*N mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 84.502 42.500 + +*CAP +0 mux_right_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.425853e-05 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001682777 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001682777 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.549962e-05 +6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.549962e-05 +7 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_163:3 7.44913e-05 +8 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_163:4 7.44913e-05 + +*RES +0 mux_right_track_16\/mux_l1_in_0_:X mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002348214 +5 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725446 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.01205107 //LENGTH 82.355 LUMPCC 0.004923546 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_0_:X O *L 0 *C 62.275 42.160 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 10.660 71.930 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 10.660 71.930 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 10.580 71.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 10.580 71.695 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 10.580 42.218 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 10.588 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 62.093 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 62.100 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 62.100 42.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 62.275 42.160 + +*CAP +0 mux_left_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.836248e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.145402e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001494155 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001494155 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00194626 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00194626 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 3.741129e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.429142e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.317326e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[14]:9 0.0003321797 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_right_in[14]:21 5.779056e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[14]:6 2.791112e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[14]:8 0.0003321797 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_right_in[14]:20 5.779056e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[14]:7 2.791112e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[6]:23 0.001594886 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[6]:34 1.205117e-05 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[6]:24 0.001594886 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_left_in[6]:33 1.205117e-05 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0004369541 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004369541 + +*RES +0 mux_left_track_1\/mux_l3_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 9.510871e-05 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.008069116 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0263192 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.347826e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006239185 //LENGTH 3.930 LUMPCC 0.0002036667 DR + +*CONN +*I mux_bottom_track_15\/mux_l1_in_1_:X O *L 0 *C 54.915 30.600 +*I mux_bottom_track_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 53.995 28.220 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 53.995 28.220 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 54.280 28.220 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 54.280 28.265 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 54.280 30.555 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 54.325 30.600 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 54.878 30.600 + +*CAP +0 mux_bottom_track_15\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_15\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.559579e-05 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.16346e-05 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001082782 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001082782 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.223255e-05 +7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.223255e-05 +8 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[13]:29 6.765513e-05 +9 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[13]:30 6.765513e-05 +10 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size3_2_sram[0]:14 3.417823e-05 +11 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size3_2_sram[0]:15 3.417823e-05 + +*RES +0 mux_bottom_track_15\/mux_l1_in_1_:X mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_15\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.005691344 //LENGTH 36.875 LUMPCC 0.002639979 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_0_:X O *L 0 *C 44.905 17.000 +*I mux_bottom_track_1\/BUFT_P_133:A I *L 0.001776 *C 72.220 9.520 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 72.183 9.520 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 71.805 9.520 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 71.760 9.565 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 71.760 11.855 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 71.715 11.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 61.685 11.900 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 61.640 11.945 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 61.640 13.543 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 61.633 13.600 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 45.088 13.600 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 45.080 13.658 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 45.080 16.955 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 45.080 17.000 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 44.905 17.000 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_1\/BUFT_P_133:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.272295e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.272295e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001472852 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001472852 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004755961 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004755961 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.000104372 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.000104372 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.000507437 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.000507437 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0001862858 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0001862858 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 5.212967e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 4.983727e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:216 2.218261e-06 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 prog_clk[0]:217 1.39733e-07 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 prog_clk[0]:314 8.436918e-06 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:213 2.218261e-06 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 prog_clk[0]:216 1.39733e-07 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 prog_clk[0]:315 8.436918e-06 +22 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 prog_clk[0]:316 0.0001200409 +23 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 prog_clk[0]:317 0.0001200409 +24 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 prog_clk[0]:501 3.838246e-06 +25 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 prog_clk[0]:502 3.838246e-06 +26 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 bottom_left_grid_pin_41_[0]:12 0.0005134033 +27 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 bottom_left_grid_pin_41_[0]:17 5.952394e-05 +28 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 bottom_left_grid_pin_41_[0]:15 1.291931e-05 +29 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 bottom_left_grid_pin_41_[0]:17 0.0005134033 +30 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 bottom_left_grid_pin_41_[0]:27 5.952394e-05 +31 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 bottom_left_grid_pin_41_[0]:16 1.291931e-05 +32 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size2_4_sram[1]:4 0.0001612613 +33 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size2_4_sram[1]:3 0.0001612613 +34 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003521037 +35 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003521037 +36 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.610389e-05 +37 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.610389e-05 + +*RES +0 mux_bottom_track_1\/mux_l3_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_1\/BUFT_P_133:A 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003370536 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002044643 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.008955358 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001426339 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.00341 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00341 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.00259205 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.002944197 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:14 9.51087e-05 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008953464 //LENGTH 7.885 LUMPCC 0 DR + +*CONN +*I mux_left_track_33\/mux_l1_in_0_:X O *L 0 *C 80.215 88.740 +*I mux_left_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 75.805 90.780 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.805 90.780 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.900 91.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 79.995 91.120 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 80.040 91.075 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 80.040 88.785 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 80.040 88.740 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 80.215 88.740 + +*CAP +0 mux_left_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.834808e-05 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002545727 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002304685 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001268591 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001268591 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.272968e-05 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.350924e-05 + +*RES +0 mux_left_track_33\/mux_l1_in_0_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_33\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00365625 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002044643 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.51087e-05 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008586134 //LENGTH 5.515 LUMPCC 0.0003063262 DR + +*CONN +*I mux_bottom_track_37\/mux_l2_in_0_:X O *L 0 *C 77.455 4.005 +*I mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 79.265 6.605 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 79.265 6.605 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 78.660 6.605 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 78.660 6.460 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 78.245 6.460 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 78.200 6.415 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 78.200 4.125 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 78.155 4.080 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 77.493 4.065 + +*CAP +0 mux_bottom_track_37\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.914945e-05 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.533016e-05 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.81361e-05 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.172238e-05 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.610519e-05 +7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.610519e-05 +8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.186939e-05 +9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.186939e-05 +10 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[19]:20 6.703642e-05 +11 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[19] 6.703642e-05 +12 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_166:26 5.809597e-05 +13 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 optlc_net_166:23 2.803072e-05 +14 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_166:25 5.809597e-05 +15 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 optlc_net_166:24 2.803072e-05 + +*RES +0 mux_bottom_track_37\/mux_l2_in_0_:X mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003705357 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002044643 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0005915179 +7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001294643 +8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005401786 + +*END + +*D_NET chanx_right_out[7] 0.001372804 //LENGTH 10.270 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 131.100 94.180 +*P chanx_right_out[7] O *L 0.7423 *C 140.450 93.840 +*N chanx_right_out[7]:2 *C 133.868 93.840 +*N chanx_right_out[7]:3 *C 133.860 93.840 +*N chanx_right_out[7]:4 *C 133.815 93.840 +*N chanx_right_out[7]:5 *C 131.100 93.840 +*N chanx_right_out[7]:6 *C 131.100 94.180 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chanx_right_out[7] 0.0004307425 +2 chanx_right_out[7]:2 0.0004307425 +3 chanx_right_out[7]:3 3.716694e-05 +4 chanx_right_out[7]:4 0.0001988422 +5 chanx_right_out[7]:5 0.0002239426 +6 chanx_right_out[7]:6 5.036693e-05 + +*RES +0 ropt_mt_inst_810:X chanx_right_out[7]:6 0.152 +1 chanx_right_out[7]:6 chanx_right_out[7]:5 0.0003035715 +2 chanx_right_out[7]:4 chanx_right_out[7]:3 0.0045 +3 chanx_right_out[7]:3 chanx_right_out[7]:2 0.00341 +4 chanx_right_out[7]:2 chanx_right_out[7] 0.001031258 +5 chanx_right_out[7]:5 chanx_right_out[7]:4 0.002424107 + +*END + +*D_NET chany_bottom_out[3] 0.0006471212 //LENGTH 4.420 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_826:X O *L 0 *C 69.920 4.080 +*P chany_bottom_out[3] O *L 0.7423 *C 69.000 1.325 +*N chany_bottom_out[3]:2 *C 69.000 1.700 +*N chany_bottom_out[3]:3 *C 69.460 1.700 +*N chany_bottom_out[3]:4 *C 69.460 4.035 +*N chany_bottom_out[3]:5 *C 69.505 4.080 +*N chany_bottom_out[3]:6 *C 69.883 4.080 + +*CAP +0 ropt_mt_inst_826:X 1e-06 +1 chany_bottom_out[3] 3.121807e-05 +2 chany_bottom_out[3]:2 6.533368e-05 +3 chany_bottom_out[3]:3 0.000227724 +4 chany_bottom_out[3]:4 0.0001936084 +5 chany_bottom_out[3]:5 6.411851e-05 +6 chany_bottom_out[3]:6 6.411851e-05 + +*RES +0 ropt_mt_inst_826:X chany_bottom_out[3]:6 0.152 +1 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.0045 +2 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.002084821 +3 chany_bottom_out[3]:6 chany_bottom_out[3]:5 0.0003370536 +4 chany_bottom_out[3]:2 chany_bottom_out[3] 0.0003348214 +5 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0004107143 + +*END + +*D_NET chanx_right_out[10] 0.000939157 //LENGTH 7.360 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_837:X O *L 0 *C 138.655 51.000 +*P chanx_right_out[10] O *L 0.7423 *C 140.450 51.680 +*N chanx_right_out[10]:2 *C 136.627 51.680 +*N chanx_right_out[10]:3 *C 136.620 51.623 +*N chanx_right_out[10]:4 *C 136.620 51.045 +*N chanx_right_out[10]:5 *C 136.665 51.000 +*N chanx_right_out[10]:6 *C 138.618 51.000 + +*CAP +0 ropt_mt_inst_837:X 1e-06 +1 chanx_right_out[10] 0.0002710063 +2 chanx_right_out[10]:2 0.0002710063 +3 chanx_right_out[10]:3 5.170051e-05 +4 chanx_right_out[10]:4 5.170051e-05 +5 chanx_right_out[10]:5 0.0001463717 +6 chanx_right_out[10]:6 0.0001463717 + +*RES +0 ropt_mt_inst_837:X chanx_right_out[10]:6 0.152 +1 chanx_right_out[10]:6 chanx_right_out[10]:5 0.001743304 +2 chanx_right_out[10]:5 chanx_right_out[10]:4 0.0045 +3 chanx_right_out[10]:4 chanx_right_out[10]:3 0.000515625 +4 chanx_right_out[10]:3 chanx_right_out[10]:2 0.00341 +5 chanx_right_out[10]:2 chanx_right_out[10] 0.0005988583 + +*END + +*D_NET chanx_left_in[2] 0.02239781 //LENGTH 179.180 LUMPCC 0.005524146 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 68.000 +*I mux_bottom_track_1\/mux_l1_in_3_:A1 I *L 0.00198 *C 38.740 34.340 +*I BUFT_RR_85:A I *L 0.001776 *C 115.920 82.960 +*I mux_right_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 113.525 77.860 +*N chanx_left_in[2]:4 *C 113.562 77.860 +*N chanx_left_in[2]:5 *C 114.495 77.860 +*N chanx_left_in[2]:6 *C 114.540 77.905 +*N chanx_left_in[2]:7 *C 115.883 82.960 +*N chanx_left_in[2]:8 *C 114.585 82.960 +*N chanx_left_in[2]:9 *C 114.540 82.915 +*N chanx_left_in[2]:10 *C 114.080 82.960 +*N chanx_left_in[2]:11 *C 114.080 84.943 +*N chanx_left_in[2]:12 *C 114.073 85.000 +*N chanx_left_in[2]:13 *C 86.610 85.000 +*N chanx_left_in[2]:14 *C 36.820 85.000 +*N chanx_left_in[2]:15 *C 36.800 84.993 +*N chanx_left_in[2]:16 *C 36.090 39.440 +*N chanx_left_in[2]:17 *C 38.703 34.340 +*N chanx_left_in[2]:18 *C 36.845 34.340 +*N chanx_left_in[2]:19 *C 36.800 34.385 +*N chanx_left_in[2]:20 *C 36.800 39.383 +*N chanx_left_in[2]:21 *C 36.797 39.440 +*N chanx_left_in[2]:22 *C 36.800 39.448 +*N chanx_left_in[2]:23 *C 36.800 68.000 +*N chanx_left_in[2]:24 *C 36.780 68.000 + +*CAP +0 chanx_left_in[2] 0.001755377 +1 mux_bottom_track_1\/mux_l1_in_3_:A1 1e-06 +2 BUFT_RR_85:A 1e-06 +3 mux_right_track_0\/mux_l1_in_2_:A1 1e-06 +4 chanx_left_in[2]:4 8.318709e-05 +5 chanx_left_in[2]:5 8.318709e-05 +6 chanx_left_in[2]:6 0.0002711418 +7 chanx_left_in[2]:7 8.560589e-05 +8 chanx_left_in[2]:8 8.560589e-05 +9 chanx_left_in[2]:9 0.0003030917 +10 chanx_left_in[2]:10 0.0001601306 +11 chanx_left_in[2]:11 0.0001281808 +12 chanx_left_in[2]:12 0.00109105 +13 chanx_left_in[2]:13 0.003461329 +14 chanx_left_in[2]:14 0.002370279 +15 chanx_left_in[2]:15 0.0006346881 +16 chanx_left_in[2]:16 0.0001246992 +17 chanx_left_in[2]:17 0.0001702682 +18 chanx_left_in[2]:18 0.0001702682 +19 chanx_left_in[2]:19 0.0002968292 +20 chanx_left_in[2]:20 0.0002968292 +21 chanx_left_in[2]:21 0.0001246992 +22 chanx_left_in[2]:22 0.001392077 +23 chanx_left_in[2]:23 0.002026765 +24 chanx_left_in[2]:24 0.001755377 +25 chanx_left_in[2]:15 chanx_right_in[2]:24 0.0002428322 +26 chanx_left_in[2]:23 chanx_right_in[2]:23 0.0003588029 +27 chanx_left_in[2]:23 chanx_right_in[2]:24 0.0001983926 +28 chanx_left_in[2]:22 chanx_right_in[2]:17 0.0001159708 +29 chanx_left_in[2]:22 chanx_right_in[2]:23 0.0001983926 +30 chanx_left_in[2]:14 chanx_right_in[9]:27 0.0006130892 +31 chanx_left_in[2]:12 chanx_right_in[9]:28 0.0005404885 +32 chanx_left_in[2]:12 chanx_right_in[9]:29 0.0001019403 +33 chanx_left_in[2]:13 chanx_right_in[9]:27 0.0005404885 +34 chanx_left_in[2]:13 chanx_right_in[9]:28 0.0007150295 +35 chanx_left_in[2] chanx_left_in[4]:32 0.0003686402 +36 chanx_left_in[2]:24 chanx_left_in[4]:31 0.0003686402 +37 chanx_left_in[2] chanx_left_out[18]:2 0.0005807196 +38 chanx_left_in[2]:24 chanx_left_out[18]:3 0.0005807196 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:24 0.0055695 +1 chanx_left_in[2]:14 chanx_left_in[2]:13 0.007800432 +2 chanx_left_in[2]:15 chanx_left_in[2]:14 0.00341 +3 chanx_left_in[2]:11 chanx_left_in[2]:10 0.001770089 +4 chanx_left_in[2]:12 chanx_left_in[2]:11 0.00341 +5 chanx_left_in[2]:24 chanx_left_in[2]:23 0.00341 +6 chanx_left_in[2]:23 chanx_left_in[2]:22 0.004473225 +7 chanx_left_in[2]:23 chanx_left_in[2]:15 0.002662158 +8 chanx_left_in[2]:21 chanx_left_in[2]:20 0.00341 +9 chanx_left_in[2]:21 chanx_left_in[2]:16 0.0001039141 +10 chanx_left_in[2]:22 chanx_left_in[2]:21 0.00341 +11 chanx_left_in[2]:20 chanx_left_in[2]:19 0.004462054 +12 chanx_left_in[2]:18 chanx_left_in[2]:17 0.001658482 +13 chanx_left_in[2]:19 chanx_left_in[2]:18 0.0045 +14 chanx_left_in[2]:17 mux_bottom_track_1\/mux_l1_in_3_:A1 0.152 +15 chanx_left_in[2]:8 chanx_left_in[2]:7 0.001158482 +16 chanx_left_in[2]:9 chanx_left_in[2]:8 0.0045 +17 chanx_left_in[2]:9 chanx_left_in[2]:6 0.004473215 +18 chanx_left_in[2]:7 BUFT_RR_85:A 0.152 +19 chanx_left_in[2]:5 chanx_left_in[2]:4 0.0008325893 +20 chanx_left_in[2]:6 chanx_left_in[2]:5 0.0045 +21 chanx_left_in[2]:4 mux_right_track_0\/mux_l1_in_2_:A1 0.152 +22 chanx_left_in[2]:10 chanx_left_in[2]:9 0.0004107143 +23 chanx_left_in[2]:13 chanx_left_in[2]:12 0.004302458 + +*END + +*D_NET chanx_right_in[15] 0.01039167 //LENGTH 98.330 LUMPCC 0.0008211024 DR + +*CONN +*P chanx_right_in[15] I *L 0.29796 *C 140.450 55.760 +*I mux_bottom_track_27\/mux_l1_in_0_:A1 I *L 0.00198 *C 90.620 9.180 +*N chanx_right_in[15]:2 *C 90.620 9.180 +*N chanx_right_in[15]:3 *C 90.620 9.225 +*N chanx_right_in[15]:4 *C 90.620 12.183 +*N chanx_right_in[15]:5 *C 90.627 12.240 +*N chanx_right_in[15]:6 *C 106.700 12.240 +*N chanx_right_in[15]:7 *C 106.720 12.248 +*N chanx_right_in[15]:8 *C 106.720 31.273 +*N chanx_right_in[15]:9 *C 106.740 31.280 +*N chanx_right_in[15]:10 *C 122.812 31.280 +*N chanx_right_in[15]:11 *C 122.820 31.338 +*N chanx_right_in[15]:12 *C 122.820 55.703 +*N chanx_right_in[15]:13 *C 122.828 55.760 + +*CAP +0 chanx_right_in[15] 0.0009472744 +1 mux_bottom_track_27\/mux_l1_in_0_:A1 1e-06 +2 chanx_right_in[15]:2 3.62839e-05 +3 chanx_right_in[15]:3 0.0002199905 +4 chanx_right_in[15]:4 0.0002199905 +5 chanx_right_in[15]:5 0.0007909563 +6 chanx_right_in[15]:6 0.0007909563 +7 chanx_right_in[15]:7 0.0006832575 +8 chanx_right_in[15]:8 0.0006832575 +9 chanx_right_in[15]:9 0.0008343244 +10 chanx_right_in[15]:10 0.0008343244 +11 chanx_right_in[15]:11 0.001290837 +12 chanx_right_in[15]:12 0.001290837 +13 chanx_right_in[15]:13 0.0009472744 +14 chanx_right_in[15]:5 chanx_right_in[0]:5 0.0001562972 +15 chanx_right_in[15]:6 chanx_right_in[0]:6 0.0001562972 +16 chanx_right_in[15]:7 chanx_right_in[0]:7 0.000254254 +17 chanx_right_in[15]:8 chanx_right_in[0]:8 0.000254254 + +*RES +0 chanx_right_in[15] chanx_right_in[15]:13 0.002760858 +1 chanx_right_in[15]:2 mux_bottom_track_27\/mux_l1_in_0_:A1 0.152 +2 chanx_right_in[15]:3 chanx_right_in[15]:2 0.0045 +3 chanx_right_in[15]:4 chanx_right_in[15]:3 0.002640625 +4 chanx_right_in[15]:5 chanx_right_in[15]:4 0.00341 +5 chanx_right_in[15]:6 chanx_right_in[15]:5 0.002518025 +6 chanx_right_in[15]:7 chanx_right_in[15]:6 0.00341 +7 chanx_right_in[15]:9 chanx_right_in[15]:8 0.00341 +8 chanx_right_in[15]:8 chanx_right_in[15]:7 0.002980583 +9 chanx_right_in[15]:11 chanx_right_in[15]:10 0.00341 +10 chanx_right_in[15]:10 chanx_right_in[15]:9 0.002518025 +11 chanx_right_in[15]:12 chanx_right_in[15]:11 0.02175447 +12 chanx_right_in[15]:13 chanx_right_in[15]:12 0.00341 + +*END + +*D_NET chany_bottom_in[4] 0.01096797 //LENGTH 78.335 LUMPCC 0.004609982 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 65.320 1.290 +*I mux_right_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 66.800 63.580 +*I mux_left_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 63.385 72.420 +*N chany_bottom_in[4]:3 *C 64.610 4.080 +*N chany_bottom_in[4]:4 *C 63.385 72.420 +*N chany_bottom_in[4]:5 *C 63.480 72.080 +*N chany_bottom_in[4]:6 *C 66.195 72.080 +*N chany_bottom_in[4]:7 *C 66.240 72.035 +*N chany_bottom_in[4]:8 *C 66.763 63.580 +*N chany_bottom_in[4]:9 *C 66.285 63.580 +*N chany_bottom_in[4]:10 *C 66.240 63.580 +*N chany_bottom_in[4]:11 *C 66.240 59.898 +*N chany_bottom_in[4]:12 *C 66.233 59.840 +*N chany_bottom_in[4]:13 *C 65.340 59.840 +*N chany_bottom_in[4]:14 *C 65.320 59.833 +*N chany_bottom_in[4]:15 *C 65.320 53.915 +*N chany_bottom_in[4]:16 *C 65.320 4.088 +*N chany_bottom_in[4]:17 *C 65.318 4.080 +*N chany_bottom_in[4]:18 *C 65.320 4.022 + +*CAP +0 chany_bottom_in[4] 0.0001738377 +1 mux_right_track_2\/mux_l1_in_0_:A1 1e-06 +2 mux_left_track_25\/mux_l1_in_1_:A1 1e-06 +3 chany_bottom_in[4]:3 8.069384e-05 +4 chany_bottom_in[4]:4 5.11047e-05 +5 chany_bottom_in[4]:5 0.0002776372 +6 chany_bottom_in[4]:6 0.0002522585 +7 chany_bottom_in[4]:7 0.000454717 +8 chany_bottom_in[4]:8 8.031611e-05 +9 chany_bottom_in[4]:9 8.031611e-05 +10 chany_bottom_in[4]:10 0.0007009317 +11 chany_bottom_in[4]:11 0.0002143326 +12 chany_bottom_in[4]:12 0.0001310961 +13 chany_bottom_in[4]:13 0.0001310961 +14 chany_bottom_in[4]:14 0.0002833387 +15 chany_bottom_in[4]:15 0.001736562 +16 chany_bottom_in[4]:16 0.001453223 +17 chany_bottom_in[4]:17 8.069384e-05 +18 chany_bottom_in[4]:18 0.0001738377 +19 chany_bottom_in[4]:14 chanx_left_in[12]:12 8.911391e-05 +20 chany_bottom_in[4]:16 chanx_left_in[12]:13 0.0004148146 +21 chany_bottom_in[4]:15 chanx_left_in[12]:12 0.0004148146 +22 chany_bottom_in[4]:15 chanx_left_in[12]:13 8.911391e-05 +23 chany_bottom_in[4]:14 chanx_left_in[14]:25 5.880085e-05 +24 chany_bottom_in[4]:16 chanx_left_in[14]:24 0.001109367 +25 chany_bottom_in[4]:15 chanx_left_in[14]:24 5.880085e-05 +26 chany_bottom_in[4]:15 chanx_left_in[14]:25 0.001109367 +27 chany_bottom_in[4]:16 chany_bottom_in[1]:17 0.0003010901 +28 chany_bottom_in[4]:15 chany_bottom_in[1]:16 0.0003010901 +29 chany_bottom_in[4]:16 chany_bottom_in[10]:14 0.0003318042 +30 chany_bottom_in[4]:15 chany_bottom_in[10]:13 0.0003318042 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:18 0.002439732 +1 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.003287946 +2 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.00341 +3 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.000139825 +4 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.00341 +5 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.00341 +6 chany_bottom_in[4]:17 chany_bottom_in[4]:3 0.0001039141 +7 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.007806308 +8 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.00341 +9 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.0004263393 +10 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.0045 +11 chany_bottom_in[4]:10 chany_bottom_in[4]:7 0.007549108 +12 chany_bottom_in[4]:8 mux_right_track_2\/mux_l1_in_0_:A1 0.152 +13 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.002424107 +14 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.0045 +15 chany_bottom_in[4]:4 mux_left_track_25\/mux_l1_in_1_:A1 0.152 +16 chany_bottom_in[4]:5 chany_bottom_in[4]:4 0.0003035715 +17 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.000927075 + +*END + +*D_NET chany_bottom_in[19] 0.01375807 //LENGTH 90.690 LUMPCC 0.005851562 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 78.660 1.290 +*I mux_left_track_33\/mux_l2_in_1_:A1 I *L 0.00198 *C 73.045 74.460 +*I mux_right_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 84.815 75.140 +*N chany_bottom_in[19]:3 *C 76.880 74.120 +*N chany_bottom_in[19]:4 *C 84.815 75.140 +*N chany_bottom_in[19]:5 *C 84.640 75.140 +*N chany_bottom_in[19]:6 *C 84.640 75.095 +*N chany_bottom_in[19]:7 *C 84.640 74.165 +*N chany_bottom_in[19]:8 *C 84.595 74.120 +*N chany_bottom_in[19]:9 *C 73.008 74.460 +*N chany_bottom_in[19]:10 *C 72.680 74.460 +*N chany_bottom_in[19]:11 *C 72.680 74.120 +*N chany_bottom_in[19]:12 *C 77.280 74.120 +*N chany_bottom_in[19]:13 *C 77.280 74.120 +*N chany_bottom_in[19]:14 *C 77.280 74.120 +*N chany_bottom_in[19]:15 *C 77.280 74.112 +*N chany_bottom_in[19]:16 *C 77.280 60.715 +*N chany_bottom_in[19]:17 *C 77.280 10.888 +*N chany_bottom_in[19]:18 *C 77.300 10.880 +*N chany_bottom_in[19]:19 *C 78.653 10.880 +*N chany_bottom_in[19]:20 *C 78.660 10.822 + +*CAP +0 chany_bottom_in[19] 0.0003513621 +1 mux_left_track_33\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_0\/mux_l1_in_1_:A0 1e-06 +3 chany_bottom_in[19]:3 9.756103e-05 +4 chany_bottom_in[19]:4 3.938793e-05 +5 chany_bottom_in[19]:5 4.455289e-05 +6 chany_bottom_in[19]:6 8.327888e-05 +7 chany_bottom_in[19]:7 8.327888e-05 +8 chany_bottom_in[19]:8 0.0003356216 +9 chany_bottom_in[19]:9 5.032334e-05 +10 chany_bottom_in[19]:10 7.758877e-05 +11 chany_bottom_in[19]:11 0.0003244494 +12 chany_bottom_in[19]:12 0.0006633847 +13 chany_bottom_in[19]:13 3.597472e-05 +14 chany_bottom_in[19]:14 9.756103e-05 +15 chany_bottom_in[19]:15 0.0006977614 +16 chany_bottom_in[19]:16 0.002499044 +17 chany_bottom_in[19]:17 0.001801283 +18 chany_bottom_in[19]:18 0.0001353685 +19 chany_bottom_in[19]:19 0.0001353685 +20 chany_bottom_in[19]:20 0.0003513621 +21 chany_bottom_in[19]:15 chanx_left_in[8]:18 0.0001429152 +22 chany_bottom_in[19]:17 chanx_left_in[8]:17 0.0005335434 +23 chany_bottom_in[19]:16 chanx_left_in[8]:17 0.0001429152 +24 chany_bottom_in[19]:16 chanx_left_in[8]:18 0.0005335434 +25 chany_bottom_in[19]:17 chanx_left_in[16]:29 0.000253811 +26 chany_bottom_in[19]:16 chanx_left_in[16]:30 0.000253811 +27 chany_bottom_in[19] chany_bottom_in[8] 1.680095e-05 +28 chany_bottom_in[19]:17 chany_bottom_in[8]:18 0.001336464 +29 chany_bottom_in[19]:20 chany_bottom_in[8]:21 1.680095e-05 +30 chany_bottom_in[19]:16 chany_bottom_in[8]:17 0.001336464 +31 chany_bottom_in[19] chany_bottom_in[12] 2.960749e-05 +32 chany_bottom_in[19]:12 chany_bottom_in[12]:8 1.037075e-05 +33 chany_bottom_in[19]:12 chany_bottom_in[12]:9 6.601173e-06 +34 chany_bottom_in[19]:12 chany_bottom_in[12]:11 0.0002219602 +35 chany_bottom_in[19]:15 chany_bottom_in[12]:15 3.727232e-05 +36 chany_bottom_in[19]:17 chany_bottom_in[12]:17 7.492171e-05 +37 chany_bottom_in[19]:20 chany_bottom_in[12]:20 2.960749e-05 +38 chany_bottom_in[19]:8 chany_bottom_in[12]:9 1.037075e-05 +39 chany_bottom_in[19]:8 chany_bottom_in[12]:10 0.0002219602 +40 chany_bottom_in[19]:5 chany_bottom_in[12]:11 5.77383e-06 +41 chany_bottom_in[19]:4 chany_bottom_in[12]:10 5.77383e-06 +42 chany_bottom_in[19]:11 chany_bottom_in[12]:8 6.601173e-06 +43 chany_bottom_in[19]:16 chany_bottom_in[12]:16 0.000112194 +44 chany_bottom_in[19] mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001887016 +45 chany_bottom_in[19]:20 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001887016 +46 chany_bottom_in[19] mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.703642e-05 +47 chany_bottom_in[19]:20 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.703642e-05 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:20 0.008511161 +1 chany_bottom_in[19]:9 mux_left_track_33\/mux_l2_in_1_:A1 0.152 +2 chany_bottom_in[19]:12 chany_bottom_in[19]:11 0.004107143 +3 chany_bottom_in[19]:12 chany_bottom_in[19]:8 0.006531251 +4 chany_bottom_in[19]:13 chany_bottom_in[19]:12 0.0045 +5 chany_bottom_in[19]:14 chany_bottom_in[19]:13 0.00341 +6 chany_bottom_in[19]:14 chany_bottom_in[19]:3 5.69697e-05 +7 chany_bottom_in[19]:15 chany_bottom_in[19]:14 0.00341 +8 chany_bottom_in[19]:18 chany_bottom_in[19]:17 0.00341 +9 chany_bottom_in[19]:17 chany_bottom_in[19]:16 0.007806308 +10 chany_bottom_in[19]:20 chany_bottom_in[19]:19 0.00341 +11 chany_bottom_in[19]:19 chany_bottom_in[19]:18 0.0002118916 +12 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.0045 +13 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.0008303572 +14 chany_bottom_in[19]:5 chany_bottom_in[19]:4 9.51087e-05 +15 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.0045 +16 chany_bottom_in[19]:4 mux_right_track_0\/mux_l1_in_1_:A0 0.152 +17 chany_bottom_in[19]:11 chany_bottom_in[19]:10 0.0003035715 +18 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.0002924107 +19 chany_bottom_in[19]:16 chany_bottom_in[19]:15 0.002098942 + +*END + +*D_NET left_top_grid_pin_1_[0] 0.0144075 //LENGTH 129.140 LUMPCC 0.0003118972 DR + +*CONN +*P left_top_grid_pin_1_[0] I *L 0.29796 *C 2.300 102.070 +*I mux_left_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 52.730 44.200 +*I mux_left_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 59.440 41.820 +*I mux_left_track_9\/mux_l1_in_2_:A0 I *L 0.001631 *C 62.850 49.980 +*N left_top_grid_pin_1_[0]:4 *C 62.812 49.980 +*N left_top_grid_pin_1_[0]:5 *C 59.340 41.820 +*N left_top_grid_pin_1_[0]:6 *C 59.340 41.865 +*N left_top_grid_pin_1_[0]:7 *C 52.768 44.200 +*N left_top_grid_pin_1_[0]:8 *C 59.295 44.200 +*N left_top_grid_pin_1_[0]:9 *C 59.340 44.200 +*N left_top_grid_pin_1_[0]:10 *C 59.340 49.935 +*N left_top_grid_pin_1_[0]:11 *C 59.340 49.980 +*N left_top_grid_pin_1_[0]:12 *C 49.265 49.980 +*N left_top_grid_pin_1_[0]:13 *C 49.220 50.025 +*N left_top_grid_pin_1_[0]:14 *C 49.220 96.175 +*N left_top_grid_pin_1_[0]:15 *C 49.175 96.220 +*N left_top_grid_pin_1_[0]:16 *C 2.345 96.220 +*N left_top_grid_pin_1_[0]:17 *C 2.300 96.265 + +*CAP +0 left_top_grid_pin_1_[0] 0.0002863438 +1 mux_left_track_5\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_1\/mux_l2_in_1_:A1 1e-06 +3 mux_left_track_9\/mux_l1_in_2_:A0 1e-06 +4 left_top_grid_pin_1_[0]:4 0.0002855159 +5 left_top_grid_pin_1_[0]:5 3.2319e-05 +6 left_top_grid_pin_1_[0]:6 0.0001423134 +7 left_top_grid_pin_1_[0]:7 0.0005578686 +8 left_top_grid_pin_1_[0]:8 0.0005578686 +9 left_top_grid_pin_1_[0]:9 0.0005112679 +10 left_top_grid_pin_1_[0]:10 0.000335695 +11 left_top_grid_pin_1_[0]:11 0.0009884542 +12 left_top_grid_pin_1_[0]:12 0.0006693867 +13 left_top_grid_pin_1_[0]:13 0.002327613 +14 left_top_grid_pin_1_[0]:14 0.002327613 +15 left_top_grid_pin_1_[0]:15 0.002391999 +16 left_top_grid_pin_1_[0]:16 0.002391999 +17 left_top_grid_pin_1_[0]:17 0.0002863438 +18 left_top_grid_pin_1_[0]:15 ropt_net_174:4 0.0001096301 +19 left_top_grid_pin_1_[0]:16 ropt_net_174:3 0.0001096301 +20 left_top_grid_pin_1_[0]:15 ropt_net_214:2 4.631851e-05 +21 left_top_grid_pin_1_[0]:16 ropt_net_214:3 4.631851e-05 + +*RES +0 left_top_grid_pin_1_[0] left_top_grid_pin_1_[0]:17 0.005183036 +1 left_top_grid_pin_1_[0]:12 left_top_grid_pin_1_[0]:11 0.008995536 +2 left_top_grid_pin_1_[0]:13 left_top_grid_pin_1_[0]:12 0.0045 +3 left_top_grid_pin_1_[0]:15 left_top_grid_pin_1_[0]:14 0.0045 +4 left_top_grid_pin_1_[0]:14 left_top_grid_pin_1_[0]:13 0.04120536 +5 left_top_grid_pin_1_[0]:16 left_top_grid_pin_1_[0]:15 0.04181251 +6 left_top_grid_pin_1_[0]:17 left_top_grid_pin_1_[0]:16 0.0045 +7 left_top_grid_pin_1_[0]:11 left_top_grid_pin_1_[0]:10 0.0045 +8 left_top_grid_pin_1_[0]:11 left_top_grid_pin_1_[0]:4 0.003100446 +9 left_top_grid_pin_1_[0]:10 left_top_grid_pin_1_[0]:9 0.005120535 +10 left_top_grid_pin_1_[0]:5 mux_left_track_1\/mux_l2_in_1_:A1 0.152 +11 left_top_grid_pin_1_[0]:6 left_top_grid_pin_1_[0]:5 0.0045 +12 left_top_grid_pin_1_[0]:4 mux_left_track_9\/mux_l1_in_2_:A0 0.152 +13 left_top_grid_pin_1_[0]:8 left_top_grid_pin_1_[0]:7 0.005828125 +14 left_top_grid_pin_1_[0]:9 left_top_grid_pin_1_[0]:8 0.0045 +15 left_top_grid_pin_1_[0]:9 left_top_grid_pin_1_[0]:6 0.002084821 +16 left_top_grid_pin_1_[0]:7 mux_left_track_5\/mux_l1_in_2_:A0 0.152 + +*END + +*D_NET chany_bottom_out[18] 0.001578431 //LENGTH 11.535 LUMPCC 0.0005020065 DR + +*CONN +*I mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 77.740 6.800 +*P chany_bottom_out[18] O *L 0.7423 *C 73.140 1.290 +*N chany_bottom_out[18]:2 *C 73.140 7.095 +*N chany_bottom_out[18]:3 *C 73.185 7.140 +*N chany_bottom_out[18]:4 *C 77.280 7.140 +*N chany_bottom_out[18]:5 *C 77.280 6.800 +*N chany_bottom_out[18]:6 *C 77.703 6.800 + +*CAP +0 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[18] 0.0002824698 +2 chany_bottom_out[18]:2 0.0002824698 +3 chany_bottom_out[18]:3 0.0001889554 +4 chany_bottom_out[18]:4 0.0002180439 +5 chany_bottom_out[18]:5 6.628706e-05 +6 chany_bottom_out[18]:6 3.719858e-05 +7 chany_bottom_out[18]:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001582342 +8 chany_bottom_out[18]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.550896e-06 +9 chany_bottom_out[18]:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001582342 +10 chany_bottom_out[18]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.550896e-06 +11 chany_bottom_out[18] ropt_net_213:4 8.521817e-05 +12 chany_bottom_out[18]:2 ropt_net_213:3 8.521817e-05 + +*RES +0 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[18]:6 0.152 +1 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.0045 +2 chany_bottom_out[18]:2 chany_bottom_out[18] 0.005183036 +3 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.0003772322 +4 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.00365625 +5 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.001309226 //LENGTH 9.240 LUMPCC 0.0002530651 DR + +*CONN +*I mem_bottom_track_29\/FTB_29__54:X O *L 0 *C 100.505 15.640 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 92.175 15.300 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 92.203 15.323 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 92.460 15.335 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 92.460 15.640 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 100.468 15.640 + +*CAP +0 mem_bottom_track_29\/FTB_29__54:X 1e-06 +1 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 3.221031e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 5.824229e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0004948704 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0004688383 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_2_sram[0]:13 0.0001265325 +7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_2_sram[0]:12 0.0001265325 + +*RES +0 mem_bottom_track_29\/FTB_29__54:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.007149554 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 0.0001739865 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[0] 0.001942548 //LENGTH 14.335 LUMPCC 9.511736e-05 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.285 17.340 +*I mux_bottom_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 51.980 23.285 +*I mux_bottom_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 50.040 20.400 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 55.375 17.340 +*N mux_tree_tapbuf_size3_3_sram[0]:4 *C 55.338 17.340 +*N mux_tree_tapbuf_size3_3_sram[0]:5 *C 50.078 20.400 +*N mux_tree_tapbuf_size3_3_sram[0]:6 *C 51.520 20.400 +*N mux_tree_tapbuf_size3_3_sram[0]:7 *C 51.520 20.740 +*N mux_tree_tapbuf_size3_3_sram[0]:8 *C 51.980 23.285 +*N mux_tree_tapbuf_size3_3_sram[0]:9 *C 51.980 23.120 +*N mux_tree_tapbuf_size3_3_sram[0]:10 *C 51.980 23.075 +*N mux_tree_tapbuf_size3_3_sram[0]:11 *C 51.980 20.785 +*N mux_tree_tapbuf_size3_3_sram[0]:12 *C 51.980 20.740 +*N mux_tree_tapbuf_size3_3_sram[0]:13 *C 53.315 20.740 +*N mux_tree_tapbuf_size3_3_sram[0]:14 *C 53.360 20.695 +*N mux_tree_tapbuf_size3_3_sram[0]:15 *C 53.360 17.385 +*N mux_tree_tapbuf_size3_3_sram[0]:16 *C 53.360 17.340 +*N mux_tree_tapbuf_size3_3_sram[0]:17 *C 52.323 17.340 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_17\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:S 1e-06 +3 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_3_sram[0]:4 0.0001451321 +5 mux_tree_tapbuf_size3_3_sram[0]:5 0.0001108454 +6 mux_tree_tapbuf_size3_3_sram[0]:6 0.0001391033 +7 mux_tree_tapbuf_size3_3_sram[0]:7 6.082646e-05 +8 mux_tree_tapbuf_size3_3_sram[0]:8 4.149137e-05 +9 mux_tree_tapbuf_size3_3_sram[0]:9 4.581771e-05 +10 mux_tree_tapbuf_size3_3_sram[0]:10 0.00016088 +11 mux_tree_tapbuf_size3_3_sram[0]:11 0.00016088 +12 mux_tree_tapbuf_size3_3_sram[0]:12 0.0001622784 +13 mux_tree_tapbuf_size3_3_sram[0]:13 9.463339e-05 +14 mux_tree_tapbuf_size3_3_sram[0]:14 0.0002016779 +15 mux_tree_tapbuf_size3_3_sram[0]:15 0.0002016779 +16 mux_tree_tapbuf_size3_3_sram[0]:16 0.0002474863 +17 mux_tree_tapbuf_size3_3_sram[0]:17 7.06998e-05 +18 mux_tree_tapbuf_size3_3_sram[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.226415e-06 +19 mux_tree_tapbuf_size3_3_sram[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.228052e-05 +20 mux_tree_tapbuf_size3_3_sram[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.105174e-05 +21 mux_tree_tapbuf_size3_3_sram[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.228052e-05 +22 mux_tree_tapbuf_size3_3_sram[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.105174e-05 +23 mux_tree_tapbuf_size3_3_sram[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.226415e-06 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_3_sram[0]:17 0.152 +1 mux_tree_tapbuf_size3_3_sram[0]:8 mux_bottom_track_17\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_3_sram[0]:9 mux_tree_tapbuf_size3_3_sram[0]:8 7.11207e-05 +3 mux_tree_tapbuf_size3_3_sram[0]:10 mux_tree_tapbuf_size3_3_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size3_3_sram[0]:12 mux_tree_tapbuf_size3_3_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size3_3_sram[0]:12 mux_tree_tapbuf_size3_3_sram[0]:7 0.0004107143 +6 mux_tree_tapbuf_size3_3_sram[0]:11 mux_tree_tapbuf_size3_3_sram[0]:10 0.002044643 +7 mux_tree_tapbuf_size3_3_sram[0]:5 mux_bottom_track_17\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:4 0.001765625 +10 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:14 0.002955357 +11 mux_tree_tapbuf_size3_3_sram[0]:13 mux_tree_tapbuf_size3_3_sram[0]:12 0.001191964 +12 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size3_3_sram[0]:4 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:16 0.0009263393 +15 mux_tree_tapbuf_size3_3_sram[0]:6 mux_tree_tapbuf_size3_3_sram[0]:5 0.001287946 +16 mux_tree_tapbuf_size3_3_sram[0]:7 mux_tree_tapbuf_size3_3_sram[0]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[2] 0.002606934 //LENGTH 18.370 LUMPCC 0.00116118 DR + +*CONN +*I mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 72.985 80.240 +*I mem_left_track_33\/FTB_27__52:A I *L 0.001746 *C 63.020 80.240 +*I mux_left_track_33\/mux_l3_in_0_:S I *L 0.00357 *C 62.200 77.815 +*N mux_tree_tapbuf_size4_3_sram[2]:3 *C 62.655 77.520 +*N mux_tree_tapbuf_size4_3_sram[2]:4 *C 62.200 77.815 +*N mux_tree_tapbuf_size4_3_sram[2]:5 *C 62.242 77.550 +*N mux_tree_tapbuf_size4_3_sram[2]:6 *C 62.983 80.240 +*N mux_tree_tapbuf_size4_3_sram[2]:7 *C 62.605 80.240 +*N mux_tree_tapbuf_size4_3_sram[2]:8 *C 62.560 80.195 +*N mux_tree_tapbuf_size4_3_sram[2]:9 *C 62.560 77.565 +*N mux_tree_tapbuf_size4_3_sram[2]:10 *C 62.685 77.520 +*N mux_tree_tapbuf_size4_3_sram[2]:11 *C 72.635 77.520 +*N mux_tree_tapbuf_size4_3_sram[2]:12 *C 72.680 77.565 +*N mux_tree_tapbuf_size4_3_sram[2]:13 *C 72.680 80.195 +*N mux_tree_tapbuf_size4_3_sram[2]:14 *C 72.680 80.240 +*N mux_tree_tapbuf_size4_3_sram[2]:15 *C 72.985 80.240 + +*CAP +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_33\/FTB_27__52:A 1e-06 +2 mux_left_track_33\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_3_sram[2]:3 1.653989e-05 +4 mux_tree_tapbuf_size4_3_sram[2]:4 5.34848e-05 +5 mux_tree_tapbuf_size4_3_sram[2]:5 5.323582e-05 +6 mux_tree_tapbuf_size4_3_sram[2]:6 4.66968e-05 +7 mux_tree_tapbuf_size4_3_sram[2]:7 4.66968e-05 +8 mux_tree_tapbuf_size4_3_sram[2]:8 0.0001430623 +9 mux_tree_tapbuf_size4_3_sram[2]:9 0.0001430623 +10 mux_tree_tapbuf_size4_3_sram[2]:10 0.0003196655 +11 mux_tree_tapbuf_size4_3_sram[2]:11 0.0002762538 +12 mux_tree_tapbuf_size4_3_sram[2]:12 0.0001237201 +13 mux_tree_tapbuf_size4_3_sram[2]:13 0.0001237201 +14 mux_tree_tapbuf_size4_3_sram[2]:14 4.769391e-05 +15 mux_tree_tapbuf_size4_3_sram[2]:15 4.892206e-05 +16 mux_tree_tapbuf_size4_3_sram[2]:11 chanx_right_in[18]:13 0.0001491672 +17 mux_tree_tapbuf_size4_3_sram[2]:12 chanx_right_in[18]:11 1.238438e-06 +18 mux_tree_tapbuf_size4_3_sram[2]:13 chanx_right_in[18]:10 1.238438e-06 +19 mux_tree_tapbuf_size4_3_sram[2]:10 chanx_right_in[18]:12 0.0001491672 +20 mux_tree_tapbuf_size4_3_sram[2]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003392123 +21 mux_tree_tapbuf_size4_3_sram[2]:12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.35984e-05 +22 mux_tree_tapbuf_size4_3_sram[2]:13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.35984e-05 +23 mux_tree_tapbuf_size4_3_sram[2]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003392123 +24 mux_tree_tapbuf_size4_3_sram[2]:11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.737372e-05 +25 mux_tree_tapbuf_size4_3_sram[2]:10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.737372e-05 + +*RES +0 mem_left_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_3_sram[2]:15 0.152 +1 mux_tree_tapbuf_size4_3_sram[2]:11 mux_tree_tapbuf_size4_3_sram[2]:10 0.00888393 +2 mux_tree_tapbuf_size4_3_sram[2]:12 mux_tree_tapbuf_size4_3_sram[2]:11 0.0045 +3 mux_tree_tapbuf_size4_3_sram[2]:14 mux_tree_tapbuf_size4_3_sram[2]:13 0.0045 +4 mux_tree_tapbuf_size4_3_sram[2]:13 mux_tree_tapbuf_size4_3_sram[2]:12 0.002348214 +5 mux_tree_tapbuf_size4_3_sram[2]:15 mux_tree_tapbuf_size4_3_sram[2]:14 0.0001657609 +6 mux_tree_tapbuf_size4_3_sram[2]:10 mux_tree_tapbuf_size4_3_sram[2]:9 0.0045 +7 mux_tree_tapbuf_size4_3_sram[2]:10 mux_tree_tapbuf_size4_3_sram[2]:5 0.0002765626 +8 mux_tree_tapbuf_size4_3_sram[2]:10 mux_tree_tapbuf_size4_3_sram[2]:3 1.875e-05 +9 mux_tree_tapbuf_size4_3_sram[2]:9 mux_tree_tapbuf_size4_3_sram[2]:8 0.002348214 +10 mux_tree_tapbuf_size4_3_sram[2]:7 mux_tree_tapbuf_size4_3_sram[2]:6 0.0003370536 +11 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_3_sram[2]:7 0.0045 +12 mux_tree_tapbuf_size4_3_sram[2]:6 mem_left_track_33\/FTB_27__52:A 0.152 +13 mux_tree_tapbuf_size4_3_sram[2]:4 mux_left_track_33\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size4_3_sram[2]:5 mux_tree_tapbuf_size4_3_sram[2]:4 0.0001540698 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_4_ccff_tail[0] 0.0005274688 //LENGTH 3.280 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/FTB_10__35:X O *L 0 *C 65.545 51.000 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.955 53.380 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 *C 65.955 53.380 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 *C 65.780 53.380 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 *C 65.780 53.335 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 *C 65.780 51.045 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 *C 65.780 51.000 +*N mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 *C 65.545 51.000 + +*CAP +0 mem_left_track_3\/FTB_10__35:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 4.885957e-05 +3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 5.445198e-05 +4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 0.0001497563 +5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 0.0001497563 +6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 6.232426e-05 +7 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 6.032032e-05 + +*RES +0 mem_left_track_3\/FTB_10__35:X mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_4_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[0] 0.006361674 //LENGTH 41.720 LUMPCC 0.001274954 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.605 53.040 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 56.220 46.845 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 49.395 42.500 +*I mux_left_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 51.620 45.175 +*I mux_left_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 67.720 44.805 +*N mux_tree_tapbuf_size6_3_sram[0]:5 *C 67.683 44.865 +*N mux_tree_tapbuf_size6_3_sram[0]:6 *C 51.620 45.175 +*N mux_tree_tapbuf_size6_3_sram[0]:7 *C 51.475 44.810 +*N mux_tree_tapbuf_size6_3_sram[0]:8 *C 51.590 44.950 +*N mux_tree_tapbuf_size6_3_sram[0]:9 *C 49.433 42.500 +*N mux_tree_tapbuf_size6_3_sram[0]:10 *C 51.475 42.500 +*N mux_tree_tapbuf_size6_3_sram[0]:11 *C 51.520 42.545 +*N mux_tree_tapbuf_size6_3_sram[0]:12 *C 51.520 44.835 +*N mux_tree_tapbuf_size6_3_sram[0]:13 *C 51.520 44.880 +*N mux_tree_tapbuf_size6_3_sram[0]:14 *C 51.520 44.540 +*N mux_tree_tapbuf_size6_3_sram[0]:15 *C 56.120 46.920 +*N mux_tree_tapbuf_size6_3_sram[0]:16 *C 56.120 46.875 +*N mux_tree_tapbuf_size6_3_sram[0]:17 *C 56.120 44.585 +*N mux_tree_tapbuf_size6_3_sram[0]:18 *C 56.120 44.540 +*N mux_tree_tapbuf_size6_3_sram[0]:19 *C 65.320 44.540 +*N mux_tree_tapbuf_size6_3_sram[0]:20 *C 65.320 44.880 +*N mux_tree_tapbuf_size6_3_sram[0]:21 *C 65.320 44.925 +*N mux_tree_tapbuf_size6_3_sram[0]:22 *C 65.320 50.943 +*N mux_tree_tapbuf_size6_3_sram[0]:23 *C 65.328 51.000 +*N mux_tree_tapbuf_size6_3_sram[0]:24 *C 71.293 51.000 +*N mux_tree_tapbuf_size6_3_sram[0]:25 *C 71.300 51.058 +*N mux_tree_tapbuf_size6_3_sram[0]:26 *C 71.300 52.995 +*N mux_tree_tapbuf_size6_3_sram[0]:27 *C 71.300 53.040 +*N mux_tree_tapbuf_size6_3_sram[0]:28 *C 71.605 53.040 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_5\/mux_l1_in_2_:S 1e-06 +4 mux_left_track_5\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_3_sram[0]:5 0.00014834 +6 mux_tree_tapbuf_size6_3_sram[0]:6 5.065141e-05 +7 mux_tree_tapbuf_size6_3_sram[0]:7 1.488177e-05 +8 mux_tree_tapbuf_size6_3_sram[0]:8 1.534636e-05 +9 mux_tree_tapbuf_size6_3_sram[0]:9 0.0001830639 +10 mux_tree_tapbuf_size6_3_sram[0]:10 0.0001830639 +11 mux_tree_tapbuf_size6_3_sram[0]:11 0.0001376307 +12 mux_tree_tapbuf_size6_3_sram[0]:12 0.0001376307 +13 mux_tree_tapbuf_size6_3_sram[0]:13 8.572238e-05 +14 mux_tree_tapbuf_size6_3_sram[0]:14 0.0003109528 +15 mux_tree_tapbuf_size6_3_sram[0]:15 3.280689e-05 +16 mux_tree_tapbuf_size6_3_sram[0]:16 0.0001695563 +17 mux_tree_tapbuf_size6_3_sram[0]:17 0.0001695563 +18 mux_tree_tapbuf_size6_3_sram[0]:18 0.0008777154 +19 mux_tree_tapbuf_size6_3_sram[0]:19 0.0005826322 +20 mux_tree_tapbuf_size6_3_sram[0]:20 0.0001764121 +21 mux_tree_tapbuf_size6_3_sram[0]:21 0.0003750123 +22 mux_tree_tapbuf_size6_3_sram[0]:22 0.0003750123 +23 mux_tree_tapbuf_size6_3_sram[0]:23 0.0003496881 +24 mux_tree_tapbuf_size6_3_sram[0]:24 0.0003496881 +25 mux_tree_tapbuf_size6_3_sram[0]:25 0.0001275955 +26 mux_tree_tapbuf_size6_3_sram[0]:26 0.0001275955 +27 mux_tree_tapbuf_size6_3_sram[0]:27 5.270318e-05 +28 mux_tree_tapbuf_size6_3_sram[0]:28 4.846169e-05 +29 mux_tree_tapbuf_size6_3_sram[0]:23 chany_bottom_in[15]:9 0.0003396097 +30 mux_tree_tapbuf_size6_3_sram[0]:24 chany_bottom_in[15]:8 0.0003396097 +31 mux_tree_tapbuf_size6_3_sram[0]:12 chany_bottom_in[15]:12 1.624423e-05 +32 mux_tree_tapbuf_size6_3_sram[0]:11 chany_bottom_in[15]:13 1.624423e-05 +33 mux_tree_tapbuf_size6_3_sram[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.744929e-05 +34 mux_tree_tapbuf_size6_3_sram[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.827103e-05 +35 mux_tree_tapbuf_size6_3_sram[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.64827e-05 +36 mux_tree_tapbuf_size6_3_sram[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.926501e-06 +37 mux_tree_tapbuf_size6_3_sram[0]:20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.949354e-05 +38 mux_tree_tapbuf_size6_3_sram[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.891355e-05 +39 mux_tree_tapbuf_size6_3_sram[0]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.827103e-05 +40 mux_tree_tapbuf_size6_3_sram[0]:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 9.926501e-06 +41 mux_tree_tapbuf_size6_3_sram[0]:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.744929e-05 +42 mux_tree_tapbuf_size6_3_sram[0]:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.706269e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_3_sram[0]:28 0.152 +1 mux_tree_tapbuf_size6_3_sram[0]:15 mux_left_track_5\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_3_sram[0]:16 mux_tree_tapbuf_size6_3_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size6_3_sram[0]:18 mux_tree_tapbuf_size6_3_sram[0]:17 0.0045 +4 mux_tree_tapbuf_size6_3_sram[0]:18 mux_tree_tapbuf_size6_3_sram[0]:14 0.004107143 +5 mux_tree_tapbuf_size6_3_sram[0]:17 mux_tree_tapbuf_size6_3_sram[0]:16 0.002044643 +6 mux_tree_tapbuf_size6_3_sram[0]:20 mux_tree_tapbuf_size6_3_sram[0]:19 0.0003035714 +7 mux_tree_tapbuf_size6_3_sram[0]:20 mux_tree_tapbuf_size6_3_sram[0]:5 0.002109375 +8 mux_tree_tapbuf_size6_3_sram[0]:21 mux_tree_tapbuf_size6_3_sram[0]:20 0.0045 +9 mux_tree_tapbuf_size6_3_sram[0]:22 mux_tree_tapbuf_size6_3_sram[0]:21 0.005372768 +10 mux_tree_tapbuf_size6_3_sram[0]:23 mux_tree_tapbuf_size6_3_sram[0]:22 0.00341 +11 mux_tree_tapbuf_size6_3_sram[0]:25 mux_tree_tapbuf_size6_3_sram[0]:24 0.00341 +12 mux_tree_tapbuf_size6_3_sram[0]:24 mux_tree_tapbuf_size6_3_sram[0]:23 0.0009345167 +13 mux_tree_tapbuf_size6_3_sram[0]:27 mux_tree_tapbuf_size6_3_sram[0]:26 0.0045 +14 mux_tree_tapbuf_size6_3_sram[0]:26 mux_tree_tapbuf_size6_3_sram[0]:25 0.001729911 +15 mux_tree_tapbuf_size6_3_sram[0]:28 mux_tree_tapbuf_size6_3_sram[0]:27 0.0001657609 +16 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:12 0.0045 +17 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:8 4.069768e-05 +18 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:6 0.0001715116 +19 mux_tree_tapbuf_size6_3_sram[0]:12 mux_tree_tapbuf_size6_3_sram[0]:11 0.002044643 +20 mux_tree_tapbuf_size6_3_sram[0]:10 mux_tree_tapbuf_size6_3_sram[0]:9 0.001823661 +21 mux_tree_tapbuf_size6_3_sram[0]:11 mux_tree_tapbuf_size6_3_sram[0]:10 0.0045 +22 mux_tree_tapbuf_size6_3_sram[0]:9 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +23 mux_tree_tapbuf_size6_3_sram[0]:5 mux_left_track_5\/mux_l1_in_1_:S 0.152 +24 mux_tree_tapbuf_size6_3_sram[0]:6 mux_left_track_5\/mux_l1_in_2_:S 0.152 +25 mux_tree_tapbuf_size6_3_sram[0]:14 mux_tree_tapbuf_size6_3_sram[0]:13 0.0003035714 +26 mux_tree_tapbuf_size6_3_sram[0]:8 mux_tree_tapbuf_size6_3_sram[0]:7 0.0001026786 +27 mux_tree_tapbuf_size6_3_sram[0]:19 mux_tree_tapbuf_size6_3_sram[0]:18 0.008214286 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001007015 //LENGTH 8.135 LUMPCC 0 DR + +*CONN +*I mux_right_track_0\/mux_l1_in_2_:X O *L 0 *C 111.955 77.180 +*I mux_right_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 107.280 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 107.318 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 111.735 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 111.780 74.505 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 111.780 77.135 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 111.780 77.180 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 111.955 77.180 + +*CAP +0 mux_right_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002854284 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002854284 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00016144 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00016144 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.70899e-05 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.418885e-05 + +*RES +0 mux_right_track_0\/mux_l1_in_2_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_0\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003944197 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008847199 //LENGTH 7.825 LUMPCC 0 DR + +*CONN +*I mux_right_track_8\/mux_l1_in_2_:X O *L 0 *C 114.255 58.140 +*I mux_right_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 112.800 52.700 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 112.838 52.700 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 113.575 52.700 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 113.620 52.745 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 113.620 58.095 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 113.665 58.140 +*N mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 114.218 58.140 + +*CAP +0 mux_right_track_8\/mux_l1_in_2_:X 1e-06 +1 mux_right_track_8\/mux_l2_in_1_:A1 1e-06 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.474376e-05 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.474376e-05 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003089278 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003089278 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.768843e-05 +7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.768843e-05 + +*RES +0 mux_right_track_8\/mux_l1_in_2_:X mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_8\/mux_l2_in_1_:A1 0.152 +2 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0006584821 +3 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_right_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006814394 //LENGTH 5.625 LUMPCC 0 DR + +*CONN +*I mux_right_track_2\/mux_l2_in_0_:X O *L 0 *C 72.505 61.540 +*I mux_right_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 77.840 61.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 77.803 61.540 +*N mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.543 61.540 + +*CAP +0 mux_right_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003397197 +3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003397197 + +*RES +0 mux_right_track_2\/mux_l2_in_0_:X mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_right_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_right_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004696429 + +*END + +*D_NET mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002497395 //LENGTH 20.825 LUMPCC 0 DR + +*CONN +*I mux_right_track_24\/mux_l1_in_0_:X O *L 0 *C 93.205 39.780 +*I mux_right_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 104.980 47.260 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 104.943 47.260 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 104.465 47.260 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 104.420 47.215 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 104.420 44.925 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 104.375 44.880 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 102.625 44.880 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 102.580 44.835 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 102.580 39.825 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 102.535 39.780 +*N mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 93.243 39.780 + +*CAP +0 mux_right_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_right_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.925269e-05 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.925269e-05 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001530789 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001530789 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001220718 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001220718 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002854829 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002854829 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.000617811 +11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.000617811 + +*RES +0 mux_right_track_24\/mux_l1_in_0_:X mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_right_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0015625 +7 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +8 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004473215 +10 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_right_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.008296875 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002123975 //LENGTH 16.085 LUMPCC 0.0003606559 DR + +*CONN +*I mux_left_track_17\/mux_l3_in_0_:X O *L 0 *C 38.815 80.920 +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 23.620 80.430 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 23.620 80.430 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.620 80.920 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 38.778 80.920 + +*CAP +0 mux_left_track_17\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.600683e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0008661603 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0008291524 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.785144e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001524765 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.785144e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001524765 + +*RES +0 mux_left_track_17\/mux_l3_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.01353348 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004375001 + +*END + +*D_NET mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002456915 //LENGTH 20.830 LUMPCC 0.0004875116 DR + +*CONN +*I mux_bottom_track_15\/mux_l2_in_0_:X O *L 0 *C 55.945 28.220 +*I mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 57.275 9.720 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 57.275 9.720 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 57.500 9.860 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 57.500 9.905 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 57.500 28.175 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 57.455 28.220 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 55.983 28.220 + +*CAP +0 mux_bottom_track_15\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.364831e-05 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.630682e-05 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0007876793 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0007876793 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001410446 +7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001410446 +8 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.276544e-06 +9 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.276544e-06 +10 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.072241e-05 +11 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.072241e-05 +12 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001807568 +13 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001807568 + +*RES +0 mux_bottom_track_15\/mux_l2_in_0_:X mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0163125 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001222826 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001408605 //LENGTH 9.070 LUMPCC 0.000341918 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_1_:X O *L 0 *C 28.695 31.960 +*I mux_bottom_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 22.255 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 22.293 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.955 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 23.000 33.615 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 23.000 32.005 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 23.045 31.960 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 28.658 31.960 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.345685e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.345685e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001014 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001014 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003774865 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003774865 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_1_sram[2]:5 3.930034e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_1_sram[2]:4 3.930034e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_1_sram[2]:6 1.141077e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_1_sram[2]:7 1.141077e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001202479 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001202479 + +*RES +0 mux_bottom_track_3\/mux_l1_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005915179 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.005011161 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009055798 //LENGTH 6.995 LUMPCC 8.826223e-05 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_2_:X O *L 0 *C 17.195 42.500 +*I mux_bottom_track_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 18.500 47.260 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 18.463 47.260 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.985 47.260 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.940 47.215 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.940 42.545 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 17.895 42.500 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 17.233 42.500 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 6.979968e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.979968e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002575679 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002575679 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.029115e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.029115e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chanx_right_in[4]:6 4.413111e-05 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chanx_right_in[4]:7 4.413111e-05 + +*RES +0 mux_bottom_track_7\/mux_l1_in_2_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_7\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004169643 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005915179 + +*END + +*D_NET mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001326585 //LENGTH 11.475 LUMPCC 0.0003075807 DR + +*CONN +*I mux_left_track_33\/mux_l2_in_1_:X O *L 0 *C 71.475 74.460 +*I mux_left_track_33\/mux_l3_in_0_:A0 I *L 0.001631 *C 63.310 76.840 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.348 76.840 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 66.195 76.840 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 66.240 76.795 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 66.240 74.505 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 66.285 74.460 +*N mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 71.438 74.460 + +*CAP +0 mux_left_track_33\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_33\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001559232 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001559232 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001252053 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001252053 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002273736 +7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002273736 +8 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size4_3_sram[1]:9 1.445829e-05 +9 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_3_sram[1]:11 8.195837e-05 +10 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_3_sram[1]:10 1.445829e-05 +11 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size4_3_sram[1]:12 8.195837e-05 +12 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size4_3_sram[2]:10 5.737372e-05 +13 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size4_3_sram[2]:11 5.737372e-05 + +*RES +0 mux_left_track_33\/mux_l2_in_1_:X mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_33\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002542411 +3 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.004600447 + +*END + +*D_NET ropt_net_218 0.0006316868 //LENGTH 4.590 LUMPCC 0.0003286341 DR + +*CONN +*I ropt_mt_inst_793:X O *L 0 *C 131.100 90.780 +*I ropt_mt_inst_836:A I *L 0.001766 *C 134.780 91.120 +*N ropt_net_218:2 *C 134.743 91.120 +*N ropt_net_218:3 *C 133.400 91.120 +*N ropt_net_218:4 *C 133.400 90.780 +*N ropt_net_218:5 *C 131.138 90.780 + +*CAP +0 ropt_mt_inst_793:X 1e-06 +1 ropt_mt_inst_836:A 1e-06 +2 ropt_net_218:2 5.774475e-05 +3 ropt_net_218:3 8.077692e-05 +4 ropt_net_218:4 9.27816e-05 +5 ropt_net_218:5 6.974941e-05 +6 ropt_net_218:2 chanx_left_in[13]:7 1.72236e-05 +7 ropt_net_218:5 chanx_left_in[13]:8 9.565813e-05 +8 ropt_net_218:4 chanx_left_in[13]:7 9.565813e-05 +9 ropt_net_218:3 chanx_left_in[13]:8 1.72236e-05 +10 ropt_net_218:2 chanx_left_in[16]:6 2.925725e-05 +11 ropt_net_218:5 chanx_left_in[16]:5 2.217808e-05 +12 ropt_net_218:4 chanx_left_in[16]:6 2.217808e-05 +13 ropt_net_218:3 chanx_left_in[16]:5 2.925725e-05 + +*RES +0 ropt_mt_inst_793:X ropt_net_218:5 0.152 +1 ropt_net_218:2 ropt_mt_inst_836:A 0.152 +2 ropt_net_218:5 ropt_net_218:4 0.002020089 +3 ropt_net_218:4 ropt_net_218:3 0.0003035715 +4 ropt_net_218:3 ropt_net_218:2 0.001198661 + +*END + +*D_NET chanx_right_out[19] 0.0007819141 //LENGTH 6.465 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_811:X O *L 0 *C 136.160 47.600 +*P chanx_right_out[19] O *L 0.7423 *C 140.450 46.240 +*N chanx_right_out[19]:2 *C 138.468 46.240 +*N chanx_right_out[19]:3 *C 138.460 46.297 +*N chanx_right_out[19]:4 *C 138.460 47.555 +*N chanx_right_out[19]:5 *C 138.415 47.600 +*N chanx_right_out[19]:6 *C 136.198 47.600 + +*CAP +0 ropt_mt_inst_811:X 1e-06 +1 chanx_right_out[19] 0.0001593454 +2 chanx_right_out[19]:2 0.0001593454 +3 chanx_right_out[19]:3 9.503159e-05 +4 chanx_right_out[19]:4 9.503159e-05 +5 chanx_right_out[19]:5 0.0001360801 +6 chanx_right_out[19]:6 0.0001360801 + +*RES +0 ropt_mt_inst_811:X chanx_right_out[19]:6 0.152 +1 chanx_right_out[19]:3 chanx_right_out[19]:2 0.00341 +2 chanx_right_out[19]:2 chanx_right_out[19] 0.0003105917 +3 chanx_right_out[19]:5 chanx_right_out[19]:4 0.0045 +4 chanx_right_out[19]:4 chanx_right_out[19]:3 0.001122768 +5 chanx_right_out[19]:6 chanx_right_out[19]:5 0.001979911 + +*END + +*D_NET chanx_left_out[9] 0.0005615986 //LENGTH 4.330 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_827:X O *L 0 *C 4.140 65.960 +*P chanx_left_out[9] O *L 0.7423 *C 1.305 65.280 +*N chanx_left_out[9]:2 *C 3.213 65.280 +*N chanx_left_out[9]:3 *C 3.220 65.338 +*N chanx_left_out[9]:4 *C 3.220 65.915 +*N chanx_left_out[9]:5 *C 3.265 65.960 +*N chanx_left_out[9]:6 *C 4.103 65.960 + +*CAP +0 ropt_mt_inst_827:X 1e-06 +1 chanx_left_out[9] 0.0001485847 +2 chanx_left_out[9]:2 0.0001485847 +3 chanx_left_out[9]:3 5.490465e-05 +4 chanx_left_out[9]:4 5.490465e-05 +5 chanx_left_out[9]:5 7.680992e-05 +6 chanx_left_out[9]:6 7.680992e-05 + +*RES +0 ropt_mt_inst_827:X chanx_left_out[9]:6 0.152 +1 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +2 chanx_left_out[9]:2 chanx_left_out[9] 0.0002988417 +3 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +4 chanx_left_out[9]:4 chanx_left_out[9]:3 0.000515625 +5 chanx_left_out[9]:6 chanx_left_out[9]:5 0.0007477678 + +*END + +*D_NET BUF_net_91 0.002372029 //LENGTH 22.505 LUMPCC 0 DR + +*CONN +*I BUFT_RR_91:X O *L 0 *C 115.000 66.980 +*I BUFT_P_147:A I *L 0.001766 *C 131.100 61.200 +*N BUF_net_91:2 *C 131.100 61.200 +*N BUF_net_91:3 *C 131.100 61.245 +*N BUF_net_91:4 *C 131.100 66.935 +*N BUF_net_91:5 *C 131.055 66.980 +*N BUF_net_91:6 *C 115.038 66.980 + +*CAP +0 BUFT_RR_91:X 1e-06 +1 BUFT_P_147:A 1e-06 +2 BUF_net_91:2 3.425339e-05 +3 BUF_net_91:3 0.000291219 +4 BUF_net_91:4 0.000291219 +5 BUF_net_91:5 0.0008766687 +6 BUF_net_91:6 0.0008766687 + +*RES +0 BUFT_RR_91:X BUF_net_91:6 0.152 +1 BUF_net_91:2 BUFT_P_147:A 0.152 +2 BUF_net_91:3 BUF_net_91:2 0.0045 +3 BUF_net_91:5 BUF_net_91:4 0.0045 +4 BUF_net_91:4 BUF_net_91:3 0.005080357 +5 BUF_net_91:6 BUF_net_91:5 0.01430134 + +*END + +*D_NET chanx_left_in[4] 0.02347732 //LENGTH 196.370 LUMPCC 0.002487139 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 50.320 +*I mux_bottom_track_3\/mux_l1_in_3_:A1 I *L 0.00198 *C 13.800 47.260 +*I ropt_mt_inst_804:A I *L 0.001767 *C 134.780 96.560 +*I mux_right_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 59.975 66.300 +*N chanx_left_in[4]:4 *C 59.975 66.300 +*N chanx_left_in[4]:5 *C 134.757 96.588 +*N chanx_left_in[4]:6 *C 134.745 96.900 +*N chanx_left_in[4]:7 *C 132.065 96.900 +*N chanx_left_in[4]:8 *C 132.020 96.855 +*N chanx_left_in[4]:9 *C 132.020 93.545 +*N chanx_left_in[4]:10 *C 131.975 93.500 +*N chanx_left_in[4]:11 *C 123.785 93.500 +*N chanx_left_in[4]:12 *C 123.740 93.455 +*N chanx_left_in[4]:13 *C 123.740 85.737 +*N chanx_left_in[4]:14 *C 123.733 85.680 +*N chanx_left_in[4]:15 *C 122.828 85.680 +*N chanx_left_in[4]:16 *C 122.820 85.623 +*N chanx_left_in[4]:17 *C 122.820 72.420 +*N chanx_left_in[4]:18 *C 122.360 72.420 +*N chanx_left_in[4]:19 *C 122.315 72.420 +*N chanx_left_in[4]:20 *C 114.330 72.420 +*N chanx_left_in[4]:21 *C 64.400 72.420 +*N chanx_left_in[4]:22 *C 64.400 72.760 +*N chanx_left_in[4]:23 *C 60.305 72.760 +*N chanx_left_in[4]:24 *C 60.260 72.715 +*N chanx_left_in[4]:25 *C 60.260 66.005 +*N chanx_left_in[4]:26 *C 60.260 65.960 +*N chanx_left_in[4]:27 *C 59.975 65.960 +*N chanx_left_in[4]:28 *C 28.565 65.960 +*N chanx_left_in[4]:29 *C 28.520 66.005 +*N chanx_left_in[4]:30 *C 28.520 69.303 +*N chanx_left_in[4]:31 *C 28.513 69.360 +*N chanx_left_in[4]:32 *C 13.820 69.360 +*N chanx_left_in[4]:33 *C 13.800 69.353 +*N chanx_left_in[4]:34 *C 13.800 50.328 +*N chanx_left_in[4]:35 *C 13.800 47.260 +*N chanx_left_in[4]:36 *C 13.800 47.305 +*N chanx_left_in[4]:37 *C 13.800 50.263 +*N chanx_left_in[4]:38 *C 13.793 50.320 + +*CAP +0 chanx_left_in[4] 0.0005751394 +1 mux_bottom_track_3\/mux_l1_in_3_:A1 1e-06 +2 ropt_mt_inst_804:A 1e-06 +3 mux_right_track_2\/mux_l1_in_1_:A0 1e-06 +4 chanx_left_in[4]:4 5.532583e-05 +5 chanx_left_in[4]:5 3.362473e-05 +6 chanx_left_in[4]:6 0.0001900472 +7 chanx_left_in[4]:7 0.0001564225 +8 chanx_left_in[4]:8 0.0001903094 +9 chanx_left_in[4]:9 0.0001903094 +10 chanx_left_in[4]:10 0.000535894 +11 chanx_left_in[4]:11 0.000535894 +12 chanx_left_in[4]:12 0.0003778695 +13 chanx_left_in[4]:13 0.0003778695 +14 chanx_left_in[4]:14 7.60866e-05 +15 chanx_left_in[4]:15 7.60866e-05 +16 chanx_left_in[4]:16 0.0006591697 +17 chanx_left_in[4]:17 0.0006908598 +18 chanx_left_in[4]:18 6.147652e-05 +19 chanx_left_in[4]:19 0.0003283304 +20 chanx_left_in[4]:20 0.002841781 +21 chanx_left_in[4]:21 0.002537322 +22 chanx_left_in[4]:22 0.0003444353 +23 chanx_left_in[4]:23 0.0003205643 +24 chanx_left_in[4]:24 0.0003702473 +25 chanx_left_in[4]:25 0.0003702473 +26 chanx_left_in[4]:26 6.864566e-05 +27 chanx_left_in[4]:27 0.002161908 +28 chanx_left_in[4]:28 0.002155892 +29 chanx_left_in[4]:29 0.000198777 +30 chanx_left_in[4]:30 0.000198777 +31 chanx_left_in[4]:31 0.0005516502 +32 chanx_left_in[4]:32 0.0005516502 +33 chanx_left_in[4]:33 0.001118934 +34 chanx_left_in[4]:34 0.001118934 +35 chanx_left_in[4]:35 3.258349e-05 +36 chanx_left_in[4]:36 0.0001794889 +37 chanx_left_in[4]:37 0.0001794889 +38 chanx_left_in[4]:38 0.0005751394 +39 chanx_left_in[4] chanx_right_in[5]:11 0.0004071209 +40 chanx_left_in[4]:38 chanx_right_in[5]:16 0.0004071209 +41 chanx_left_in[4]:32 chanx_left_in[2] 0.0003686402 +42 chanx_left_in[4]:31 chanx_left_in[2]:24 0.0003686402 +43 chanx_left_in[4] chanx_left_in[5] 1.327791e-05 +44 chanx_left_in[4]:38 chanx_left_in[5]:42 1.327791e-05 +45 chanx_left_in[4]:19 chanx_left_in[5]:22 0.0001476162 +46 chanx_left_in[4]:16 chanx_left_in[5]:20 4.999944e-06 +47 chanx_left_in[4]:21 chanx_left_in[5]:23 0.0002492352 +48 chanx_left_in[4]:17 chanx_left_in[5]:21 4.999944e-06 +49 chanx_left_in[4]:20 chanx_left_in[5]:23 0.0001476162 +50 chanx_left_in[4]:20 chanx_left_in[5]:22 0.0002492352 +51 chanx_left_in[4]:28 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.267921e-05 +52 chanx_left_in[4]:27 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.267921e-05 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:38 0.001968125 +1 chanx_left_in[4]:35 mux_bottom_track_3\/mux_l1_in_3_:A1 0.152 +2 chanx_left_in[4]:36 chanx_left_in[4]:35 0.0045 +3 chanx_left_in[4]:37 chanx_left_in[4]:36 0.002640625 +4 chanx_left_in[4]:38 chanx_left_in[4]:37 0.00341 +5 chanx_left_in[4]:38 chanx_left_in[4]:34 0.00341 +6 chanx_left_in[4]:26 chanx_left_in[4]:25 0.0045 +7 chanx_left_in[4]:26 chanx_left_in[4]:4 0.0001976744 +8 chanx_left_in[4]:25 chanx_left_in[4]:24 0.005991072 +9 chanx_left_in[4]:23 chanx_left_in[4]:22 0.00365625 +10 chanx_left_in[4]:24 chanx_left_in[4]:23 0.0045 +11 chanx_left_in[4]:19 chanx_left_in[4]:18 0.0045 +12 chanx_left_in[4]:18 chanx_left_in[4]:17 0.0004107143 +13 chanx_left_in[4]:16 chanx_left_in[4]:15 0.00341 +14 chanx_left_in[4]:15 chanx_left_in[4]:14 0.0001417833 +15 chanx_left_in[4]:13 chanx_left_in[4]:12 0.006890626 +16 chanx_left_in[4]:14 chanx_left_in[4]:13 0.00341 +17 chanx_left_in[4]:11 chanx_left_in[4]:10 0.0073125 +18 chanx_left_in[4]:12 chanx_left_in[4]:11 0.0045 +19 chanx_left_in[4]:10 chanx_left_in[4]:9 0.0045 +20 chanx_left_in[4]:9 chanx_left_in[4]:8 0.002955357 +21 chanx_left_in[4]:7 chanx_left_in[4]:6 0.002392857 +22 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0045 +23 chanx_left_in[4]:5 ropt_mt_inst_804:A 0.152 +24 chanx_left_in[4]:4 mux_right_track_2\/mux_l1_in_1_:A0 0.152 +25 chanx_left_in[4]:34 chanx_left_in[4]:33 0.002980583 +26 chanx_left_in[4]:32 chanx_left_in[4]:31 0.002301825 +27 chanx_left_in[4]:33 chanx_left_in[4]:32 0.00341 +28 chanx_left_in[4]:30 chanx_left_in[4]:29 0.002944197 +29 chanx_left_in[4]:31 chanx_left_in[4]:30 0.00341 +30 chanx_left_in[4]:28 chanx_left_in[4]:27 0.02804465 +31 chanx_left_in[4]:29 chanx_left_in[4]:28 0.0045 +32 chanx_left_in[4]:27 chanx_left_in[4]:26 1e-05 +33 chanx_left_in[4]:22 chanx_left_in[4]:21 0.0003035715 +34 chanx_left_in[4]:21 chanx_left_in[4]:20 0.04458036 +35 chanx_left_in[4]:6 chanx_left_in[4]:5 0.0002111487 +36 chanx_left_in[4]:17 chanx_left_in[4]:16 0.01178795 +37 chanx_left_in[4]:20 chanx_left_in[4]:19 0.007129465 + +*END + +*D_NET chany_bottom_in[7] 0.005505571 //LENGTH 48.630 LUMPCC 0 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 87.400 1.325 +*I mux_left_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 83.090 38.760 +*I mux_right_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 91.255 38.760 +*N chany_bottom_in[7]:3 *C 91.218 38.760 +*N chany_bottom_in[7]:4 *C 83.127 38.760 +*N chany_bottom_in[7]:5 *C 89.700 38.760 +*N chany_bottom_in[7]:6 *C 89.700 38.715 +*N chany_bottom_in[7]:7 *C 89.700 3.740 +*N chany_bottom_in[7]:8 *C 87.400 3.740 + +*CAP +0 chany_bottom_in[7] 0.0001449606 +1 mux_left_track_3\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_24\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[7]:3 0.0001054779 +4 chany_bottom_in[7]:4 0.0004284232 +5 chany_bottom_in[7]:5 0.0005662015 +6 chany_bottom_in[7]:6 0.00193757 +7 chany_bottom_in[7]:7 0.002056774 +8 chany_bottom_in[7]:8 0.0002641642 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:8 0.00215625 +1 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.005868304 +2 chany_bottom_in[7]:5 chany_bottom_in[7]:3 0.001354911 +3 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.0045 +4 chany_bottom_in[7]:4 mux_left_track_3\/mux_l1_in_1_:A0 0.152 +5 chany_bottom_in[7]:3 mux_right_track_24\/mux_l1_in_0_:A0 0.152 +6 chany_bottom_in[7]:8 chany_bottom_in[7]:7 0.002053571 +7 chany_bottom_in[7]:7 chany_bottom_in[7]:6 0.03122768 + +*END + +*D_NET chany_bottom_in[13] 0.008094775 //LENGTH 60.865 LUMPCC 0.001223858 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 68.080 1.290 +*I mux_left_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 74.810 26.180 +*I mux_right_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 100.455 27.880 +*N chany_bottom_in[13]:3 *C 100.418 27.880 +*N chany_bottom_in[13]:4 *C 91.125 27.880 +*N chany_bottom_in[13]:5 *C 91.080 27.835 +*N chany_bottom_in[13]:6 *C 91.080 26.565 +*N chany_bottom_in[13]:7 *C 91.035 26.520 +*N chany_bottom_in[13]:8 *C 74.810 26.520 +*N chany_bottom_in[13]:9 *C 74.810 26.180 +*N chany_bottom_in[13]:10 *C 74.520 26.180 +*N chany_bottom_in[13]:11 *C 74.520 26.135 +*N chany_bottom_in[13]:12 *C 74.520 10.258 +*N chany_bottom_in[13]:13 *C 74.513 10.200 +*N chany_bottom_in[13]:14 *C 68.088 10.200 +*N chany_bottom_in[13]:15 *C 68.080 10.143 + +*CAP +0 chany_bottom_in[13] 0.0005358292 +1 mux_left_track_1\/mux_l1_in_1_:A0 1e-06 +2 mux_right_track_32\/mux_l1_in_0_:A0 1e-06 +3 chany_bottom_in[13]:3 0.0005513515 +4 chany_bottom_in[13]:4 0.0005513515 +5 chany_bottom_in[13]:5 0.0001038968 +6 chany_bottom_in[13]:6 0.0001038968 +7 chany_bottom_in[13]:7 0.0009960391 +8 chany_bottom_in[13]:8 0.001026743 +9 chany_bottom_in[13]:9 7.318771e-05 +10 chany_bottom_in[13]:10 2.356982e-05 +11 chany_bottom_in[13]:11 0.0007025397 +12 chany_bottom_in[13]:12 0.0007025397 +13 chany_bottom_in[13]:13 0.0004810721 +14 chany_bottom_in[13]:14 0.0004810721 +15 chany_bottom_in[13]:15 0.0005358292 +16 chany_bottom_in[13]:7 chanx_right_in[1]:4 8.59834e-05 +17 chany_bottom_in[13]:7 chanx_right_in[1]:6 0.0001574111 +18 chany_bottom_in[13]:4 chanx_right_in[1]:9 5.032742e-05 +19 chany_bottom_in[13]:3 chanx_right_in[1]:10 5.032742e-05 +20 chany_bottom_in[13]:10 chanx_right_in[1]:3 8.8085e-06 +21 chany_bottom_in[13]:9 chanx_right_in[1]:4 8.8085e-06 +22 chany_bottom_in[13]:8 chanx_right_in[1]:3 8.59834e-05 +23 chany_bottom_in[13]:8 chanx_right_in[1]:5 0.0001574111 +24 chany_bottom_in[13] chany_bottom_in[14] 1.599008e-05 +25 chany_bottom_in[13]:11 chany_bottom_in[14]:14 0.0002883946 +26 chany_bottom_in[13]:12 chany_bottom_in[14]:15 0.0002883946 +27 chany_bottom_in[13]:13 chany_bottom_in[14]:20 5.013685e-06 +28 chany_bottom_in[13]:15 chany_bottom_in[14]:22 1.599008e-05 +29 chany_bottom_in[13]:14 chany_bottom_in[14]:21 5.013685e-06 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:15 0.007904017 +1 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.0045 +2 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.001133929 +3 chany_bottom_in[13]:4 chany_bottom_in[13]:3 0.008296875 +4 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.0045 +5 chany_bottom_in[13]:3 mux_right_track_32\/mux_l1_in_0_:A0 0.152 +6 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.0001576087 +7 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.0045 +8 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.01417634 +9 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.00341 +10 chany_bottom_in[13]:15 chany_bottom_in[13]:14 0.00341 +11 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.001006583 +12 chany_bottom_in[13]:9 mux_left_track_1\/mux_l1_in_1_:A0 0.152 +13 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.0003035715 +14 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.01448661 + +*END + +*D_NET bottom_left_grid_pin_34_[0] 0.01855078 //LENGTH 127.010 LUMPCC 0.005687734 DR + +*CONN +*P bottom_left_grid_pin_34_[0] I *L 0.29796 *C 29.825 10.200 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 35.135 31.620 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 95.510 31.620 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 29.155 49.980 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 27.890 60.520 +*N bottom_left_grid_pin_34_[0]:5 *C 29.040 46.920 +*N bottom_left_grid_pin_34_[0]:6 *C 27.928 60.520 +*N bottom_left_grid_pin_34_[0]:7 *C 29.395 60.520 +*N bottom_left_grid_pin_34_[0]:8 *C 29.440 60.475 +*N bottom_left_grid_pin_34_[0]:9 *C 29.155 49.980 +*N bottom_left_grid_pin_34_[0]:10 *C 29.440 49.980 +*N bottom_left_grid_pin_34_[0]:11 *C 29.440 49.980 +*N bottom_left_grid_pin_34_[0]:12 *C 29.440 46.977 +*N bottom_left_grid_pin_34_[0]:13 *C 29.440 46.920 +*N bottom_left_grid_pin_34_[0]:14 *C 29.440 46.913 +*N bottom_left_grid_pin_34_[0]:15 *C 95.510 31.620 +*N bottom_left_grid_pin_34_[0]:16 *C 95.680 31.620 +*N bottom_left_grid_pin_34_[0]:17 *C 95.680 31.575 +*N bottom_left_grid_pin_34_[0]:18 *C 95.680 30.658 +*N bottom_left_grid_pin_34_[0]:19 *C 95.672 30.600 +*N bottom_left_grid_pin_34_[0]:20 *C 84.500 30.600 +*N bottom_left_grid_pin_34_[0]:21 *C 35.098 31.620 +*N bottom_left_grid_pin_34_[0]:22 *C 34.545 31.620 +*N bottom_left_grid_pin_34_[0]:23 *C 34.500 31.575 +*N bottom_left_grid_pin_34_[0]:24 *C 34.500 30.658 +*N bottom_left_grid_pin_34_[0]:25 *C 34.500 30.600 +*N bottom_left_grid_pin_34_[0]:26 *C 29.905 30.600 +*N bottom_left_grid_pin_34_[0]:27 *C 29.455 30.600 +*N bottom_left_grid_pin_34_[0]:28 *C 29.440 30.600 +*N bottom_left_grid_pin_34_[0]:29 *C 30.360 30.600 +*N bottom_left_grid_pin_34_[0]:30 *C 30.360 10.208 +*N bottom_left_grid_pin_34_[0]:31 *C 30.340 10.200 + +*CAP +0 bottom_left_grid_pin_34_[0] 6.375674e-05 +1 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_34_[0]:5 3.209871e-05 +6 bottom_left_grid_pin_34_[0]:6 0.0001169948 +7 bottom_left_grid_pin_34_[0]:7 0.0001169948 +8 bottom_left_grid_pin_34_[0]:8 0.0005394493 +9 bottom_left_grid_pin_34_[0]:9 4.769154e-05 +10 bottom_left_grid_pin_34_[0]:10 5.240457e-05 +11 bottom_left_grid_pin_34_[0]:11 0.0007030883 +12 bottom_left_grid_pin_34_[0]:12 0.0001333736 +13 bottom_left_grid_pin_34_[0]:13 3.209871e-05 +14 bottom_left_grid_pin_34_[0]:14 0.0008116011 +15 bottom_left_grid_pin_34_[0]:15 4.626481e-05 +16 bottom_left_grid_pin_34_[0]:16 5.022672e-05 +17 bottom_left_grid_pin_34_[0]:17 7.511472e-05 +18 bottom_left_grid_pin_34_[0]:18 7.511472e-05 +19 bottom_left_grid_pin_34_[0]:19 0.0006206504 +20 bottom_left_grid_pin_34_[0]:20 0.003380515 +21 bottom_left_grid_pin_34_[0]:21 5.746297e-05 +22 bottom_left_grid_pin_34_[0]:22 5.746297e-05 +23 bottom_left_grid_pin_34_[0]:23 9.224444e-05 +24 bottom_left_grid_pin_34_[0]:24 9.224444e-05 +25 bottom_left_grid_pin_34_[0]:25 0.002956558 +26 bottom_left_grid_pin_34_[0]:26 0.0002299713 +27 bottom_left_grid_pin_34_[0]:27 3.32779e-05 +28 bottom_left_grid_pin_34_[0]:28 0.000787951 +29 bottom_left_grid_pin_34_[0]:29 0.0007835164 +30 bottom_left_grid_pin_34_[0]:30 0.0008071665 +31 bottom_left_grid_pin_34_[0]:31 6.375674e-05 +32 bottom_left_grid_pin_34_[0]:28 chanx_left_in[12]:34 3.425692e-05 +33 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:19 0.0001303144 +34 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:20 7.809569e-05 +35 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:28 0.0005680347 +36 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:30 4.770227e-05 +37 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:33 1.471711e-05 +38 bottom_left_grid_pin_34_[0]:25 chanx_left_in[12]:34 6.49937e-06 +39 bottom_left_grid_pin_34_[0]:26 chanx_left_in[12]:34 1.471711e-05 +40 bottom_left_grid_pin_34_[0]:29 chanx_left_in[12]:33 3.425692e-05 +41 bottom_left_grid_pin_34_[0]:20 chanx_left_in[12]:14 0.0001303144 +42 bottom_left_grid_pin_34_[0]:20 chanx_left_in[12]:19 7.809569e-05 +43 bottom_left_grid_pin_34_[0]:20 chanx_left_in[12]:27 0.0005680347 +44 bottom_left_grid_pin_34_[0]:20 chanx_left_in[12]:29 4.770227e-05 +45 bottom_left_grid_pin_34_[0]:20 chanx_left_in[12]:33 6.49937e-06 +46 bottom_left_grid_pin_34_[0]:27 prog_clk[0]:496 1.264505e-05 +47 bottom_left_grid_pin_34_[0]:27 prog_clk[0]:497 3.112628e-06 +48 bottom_left_grid_pin_34_[0]:28 prog_clk[0]:496 1.195345e-05 +49 bottom_left_grid_pin_34_[0]:28 prog_clk[0]:497 1.628142e-05 +50 bottom_left_grid_pin_34_[0]:24 prog_clk[0]:500 1.497959e-06 +51 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:195 0.0003836496 +52 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:293 4.779959e-05 +53 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:300 1.413592e-06 +54 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:497 2.871662e-06 +55 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:498 5.920108e-05 +56 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:528 6.063015e-06 +57 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:533 2.600595e-06 +58 bottom_left_grid_pin_34_[0]:25 prog_clk[0]:534 1.93852e-07 +59 bottom_left_grid_pin_34_[0]:23 prog_clk[0]:499 1.497959e-06 +60 bottom_left_grid_pin_34_[0]:8 prog_clk[0]:350 2.407458e-05 +61 bottom_left_grid_pin_34_[0]:8 prog_clk[0]:356 5.116871e-05 +62 bottom_left_grid_pin_34_[0]:8 prog_clk[0]:360 4.273442e-05 +63 bottom_left_grid_pin_34_[0]:12 prog_clk[0]:481 9.160841e-06 +64 bottom_left_grid_pin_34_[0]:12 prog_clk[0]:482 2.751195e-05 +65 bottom_left_grid_pin_34_[0]:12 prog_clk[0]:483 9.635321e-06 +66 bottom_left_grid_pin_34_[0]:13 prog_clk[0]:480 5.432768e-05 +67 bottom_left_grid_pin_34_[0]:14 prog_clk[0]:488 1.05026e-05 +68 bottom_left_grid_pin_34_[0]:11 prog_clk[0]:356 2.407458e-05 +69 bottom_left_grid_pin_34_[0]:11 prog_clk[0]:360 7.868066e-05 +70 bottom_left_grid_pin_34_[0]:11 prog_clk[0]:461 9.160841e-06 +71 bottom_left_grid_pin_34_[0]:11 prog_clk[0]:482 5.236974e-05 +72 bottom_left_grid_pin_34_[0]:19 prog_clk[0]:159 9.971901e-06 +73 bottom_left_grid_pin_34_[0]:19 prog_clk[0]:186 4.155887e-05 +74 bottom_left_grid_pin_34_[0]:19 prog_clk[0]:190 0.0001558492 +75 bottom_left_grid_pin_34_[0]:19 prog_clk[0]:194 7.28662e-06 +76 bottom_left_grid_pin_34_[0]:5 prog_clk[0]:481 5.432768e-05 +77 bottom_left_grid_pin_34_[0]:26 prog_clk[0]:496 2.871662e-06 +78 bottom_left_grid_pin_34_[0]:26 prog_clk[0]:497 7.184613e-05 +79 bottom_left_grid_pin_34_[0]:26 prog_clk[0]:498 3.112628e-06 +80 bottom_left_grid_pin_34_[0]:29 prog_clk[0]:497 1.195345e-05 +81 bottom_left_grid_pin_34_[0]:29 prog_clk[0]:498 5.77882e-06 +82 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:186 9.971901e-06 +83 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:187 4.155887e-05 +84 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:194 0.0005394989 +85 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:195 7.28662e-06 +86 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:292 4.779959e-05 +87 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:299 1.413592e-06 +88 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:523 6.063015e-06 +89 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:528 2.600595e-06 +90 bottom_left_grid_pin_34_[0]:20 prog_clk[0]:533 1.93852e-07 +91 bottom_left_grid_pin_34_[0]:27 chanx_left_in[0]:7 1.567873e-05 +92 bottom_left_grid_pin_34_[0]:28 chanx_left_in[0]:7 4.017739e-05 +93 bottom_left_grid_pin_34_[0]:25 chanx_left_in[0]:6 7.488217e-05 +94 bottom_left_grid_pin_34_[0]:25 chanx_left_in[0]:7 0.0001290154 +95 bottom_left_grid_pin_34_[0]:26 chanx_left_in[0]:6 1.567873e-05 +96 bottom_left_grid_pin_34_[0]:26 chanx_left_in[0]:7 7.488217e-05 +97 bottom_left_grid_pin_34_[0]:29 chanx_left_in[0]:6 4.017739e-05 +98 bottom_left_grid_pin_34_[0]:20 chanx_left_in[0]:6 0.0001290154 +99 bottom_left_grid_pin_34_[0]:30 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0004895987 +100 bottom_left_grid_pin_34_[0]:28 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0002323305 +101 bottom_left_grid_pin_34_[0]:14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0002323305 +102 bottom_left_grid_pin_34_[0]:29 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0004895987 + +*RES +0 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_34_[0]:31 8.068333e-05 +1 bottom_left_grid_pin_34_[0]:31 bottom_left_grid_pin_34_[0]:30 0.00341 +2 bottom_left_grid_pin_34_[0]:30 bottom_left_grid_pin_34_[0]:29 0.003194825 +3 bottom_left_grid_pin_34_[0]:27 bottom_left_grid_pin_34_[0]:26 6.609374e-05 +4 bottom_left_grid_pin_34_[0]:28 bottom_left_grid_pin_34_[0]:27 0.00341 +5 bottom_left_grid_pin_34_[0]:28 bottom_left_grid_pin_34_[0]:14 0.002555625 +6 bottom_left_grid_pin_34_[0]:24 bottom_left_grid_pin_34_[0]:23 0.0008191965 +7 bottom_left_grid_pin_34_[0]:25 bottom_left_grid_pin_34_[0]:24 0.00341 +8 bottom_left_grid_pin_34_[0]:25 bottom_left_grid_pin_34_[0]:20 0.007833333 +9 bottom_left_grid_pin_34_[0]:22 bottom_left_grid_pin_34_[0]:21 0.0004933036 +10 bottom_left_grid_pin_34_[0]:23 bottom_left_grid_pin_34_[0]:22 0.0045 +11 bottom_left_grid_pin_34_[0]:21 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +12 bottom_left_grid_pin_34_[0]:7 bottom_left_grid_pin_34_[0]:6 0.001310268 +13 bottom_left_grid_pin_34_[0]:8 bottom_left_grid_pin_34_[0]:7 0.0045 +14 bottom_left_grid_pin_34_[0]:6 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +15 bottom_left_grid_pin_34_[0]:12 bottom_left_grid_pin_34_[0]:11 0.002680804 +16 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:12 0.00341 +17 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:5 5.69697e-05 +18 bottom_left_grid_pin_34_[0]:14 bottom_left_grid_pin_34_[0]:13 0.00341 +19 bottom_left_grid_pin_34_[0]:10 bottom_left_grid_pin_34_[0]:9 0.0001548913 +20 bottom_left_grid_pin_34_[0]:11 bottom_left_grid_pin_34_[0]:10 0.0045 +21 bottom_left_grid_pin_34_[0]:11 bottom_left_grid_pin_34_[0]:8 0.009370536 +22 bottom_left_grid_pin_34_[0]:9 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +23 bottom_left_grid_pin_34_[0]:18 bottom_left_grid_pin_34_[0]:17 0.0008191965 +24 bottom_left_grid_pin_34_[0]:19 bottom_left_grid_pin_34_[0]:18 0.00341 +25 bottom_left_grid_pin_34_[0]:16 bottom_left_grid_pin_34_[0]:15 9.239131e-05 +26 bottom_left_grid_pin_34_[0]:17 bottom_left_grid_pin_34_[0]:16 0.0045 +27 bottom_left_grid_pin_34_[0]:15 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 +28 bottom_left_grid_pin_34_[0]:26 bottom_left_grid_pin_34_[0]:25 0.0007198832 +29 bottom_left_grid_pin_34_[0]:29 bottom_left_grid_pin_34_[0]:28 0.0001441333 +30 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_34_[0]:19 0.001750358 + +*END + +*D_NET ccff_head[0] 0.005251141 //LENGTH 54.580 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 138.460 102.070 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 104.135 82.620 +*N ccff_head[0]:2 *C 104.135 82.620 +*N ccff_head[0]:3 *C 104.420 82.620 +*N ccff_head[0]:4 *C 104.420 82.665 +*N ccff_head[0]:5 *C 104.420 98.895 +*N ccff_head[0]:6 *C 104.465 98.940 +*N ccff_head[0]:7 *C 138.415 98.940 +*N ccff_head[0]:8 *C 138.460 98.985 + +*CAP +0 ccff_head[0] 0.0001554074 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 4.7543e-05 +3 ccff_head[0]:3 5.234249e-05 +4 ccff_head[0]:4 0.0007665782 +5 ccff_head[0]:5 0.0007665782 +6 ccff_head[0]:6 0.001653142 +7 ccff_head[0]:7 0.001653142 +8 ccff_head[0]:8 0.0001554074 + +*RES +0 ccff_head[0] ccff_head[0]:8 0.002754464 +1 ccff_head[0]:2 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0001548913 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:6 ccff_head[0]:5 0.0045 +5 ccff_head[0]:5 ccff_head[0]:4 0.01449107 +6 ccff_head[0]:7 ccff_head[0]:6 0.0303125 +7 ccff_head[0]:8 ccff_head[0]:7 0.0045 + +*END + +*D_NET chanx_right_out[4] 0.005235408 //LENGTH 43.965 LUMPCC 0.0008922594 DR + +*CONN +*I mux_right_track_8\/mux_l3_in_0_:X O *L 0 *C 123.060 55.080 +*P chanx_right_out[4] O *L 0.7423 *C 140.450 78.880 +*N chanx_right_out[4]:2 *C 138.920 78.880 +*N chanx_right_out[4]:3 *C 138.920 79.560 +*N chanx_right_out[4]:4 *C 133.407 79.560 +*N chanx_right_out[4]:5 *C 133.400 79.502 +*N chanx_right_out[4]:6 *C 133.400 55.125 +*N chanx_right_out[4]:7 *C 133.355 55.080 +*N chanx_right_out[4]:8 *C 123.098 55.080 + +*CAP +0 mux_right_track_8\/mux_l3_in_0_:X 1e-06 +1 chanx_right_out[4] 6.245548e-05 +2 chanx_right_out[4]:2 0.0001031248 +3 chanx_right_out[4]:3 0.0003197066 +4 chanx_right_out[4]:4 0.0002790373 +5 chanx_right_out[4]:5 0.001186601 +6 chanx_right_out[4]:6 0.001186601 +7 chanx_right_out[4]:7 0.0006023109 +8 chanx_right_out[4]:8 0.0006023109 +9 chanx_right_out[4] chanx_right_in[10] 4.32148e-05 +10 chanx_right_out[4]:4 chanx_right_in[10]:26 0.0003241314 +11 chanx_right_out[4]:3 chanx_right_in[10] 0.0003241314 +12 chanx_right_out[4]:2 chanx_right_in[10]:26 4.32148e-05 +13 chanx_right_out[4]:5 ropt_net_175:10 3.999179e-06 +14 chanx_right_out[4]:7 ropt_net_175:3 6.068817e-05 +15 chanx_right_out[4]:7 ropt_net_175:5 9.446075e-06 +16 chanx_right_out[4]:7 ropt_net_175:7 4.650028e-06 +17 chanx_right_out[4]:6 ropt_net_175:9 3.999179e-06 +18 chanx_right_out[4]:8 ropt_net_175:4 6.068817e-05 +19 chanx_right_out[4]:8 ropt_net_175:6 9.446075e-06 +20 chanx_right_out[4]:8 ropt_net_175:8 4.650028e-06 + +*RES +0 mux_right_track_8\/mux_l3_in_0_:X chanx_right_out[4]:8 0.152 +1 chanx_right_out[4]:5 chanx_right_out[4]:4 0.00341 +2 chanx_right_out[4]:4 chanx_right_out[4]:3 0.0008636249 +3 chanx_right_out[4]:7 chanx_right_out[4]:6 0.0045 +4 chanx_right_out[4]:6 chanx_right_out[4]:5 0.02176563 +5 chanx_right_out[4]:8 chanx_right_out[4]:7 0.009158483 +6 chanx_right_out[4]:3 chanx_right_out[4]:2 0.0001065333 +7 chanx_right_out[4]:2 chanx_right_out[4] 0.0002397 + +*END + +*D_NET ropt_net_172 0.004415268 //LENGTH 31.725 LUMPCC 0.0009504959 DR + +*CONN +*I mux_bottom_track_7\/BUFT_RR_71:X O *L 0 *C 53.820 11.560 +*I ropt_mt_inst_792:A I *L 0.001766 *C 68.080 6.800 +*N ropt_net_172:2 *C 68.080 6.800 +*N ropt_net_172:3 *C 68.955 6.800 +*N ropt_net_172:4 *C 69.000 6.755 +*N ropt_net_172:5 *C 69.000 2.040 +*N ropt_net_172:6 *C 68.540 2.040 +*N ropt_net_172:7 *C 68.495 2.040 +*N ropt_net_172:8 *C 53.865 2.040 +*N ropt_net_172:9 *C 53.820 2.085 +*N ropt_net_172:10 *C 53.820 11.515 +*N ropt_net_172:11 *C 53.820 11.560 + +*CAP +0 mux_bottom_track_7\/BUFT_RR_71:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_172:2 0.0001236958 +3 ropt_net_172:3 8.330794e-05 +4 ropt_net_172:4 0.0003227657 +5 ropt_net_172:5 0.0003589681 +6 ropt_net_172:6 7.118736e-05 +7 ropt_net_172:7 0.000836438 +8 ropt_net_172:8 0.000836438 +9 ropt_net_172:9 0.0003965131 +10 ropt_net_172:10 0.0003965131 +11 ropt_net_172:11 3.694563e-05 +12 ropt_net_172:9 prog_clk[0]:323 0.0001186166 +13 ropt_net_172:10 prog_clk[0]:322 0.0001186166 +14 ropt_net_172:7 chany_bottom_out[1]:3 0.000233181 +15 ropt_net_172:8 chany_bottom_out[1]:4 0.000233181 +16 ropt_net_172:9 chany_bottom_out[9] 0.0001234504 +17 ropt_net_172:10 chany_bottom_out[9]:2 0.0001234504 + +*RES +0 mux_bottom_track_7\/BUFT_RR_71:X ropt_net_172:11 0.152 +1 ropt_net_172:2 ropt_mt_inst_792:A 0.152 +2 ropt_net_172:3 ropt_net_172:2 0.00078125 +3 ropt_net_172:4 ropt_net_172:3 0.0045 +4 ropt_net_172:7 ropt_net_172:6 0.0045 +5 ropt_net_172:6 ropt_net_172:5 0.0004107143 +6 ropt_net_172:8 ropt_net_172:7 0.0130625 +7 ropt_net_172:9 ropt_net_172:8 0.0045 +8 ropt_net_172:11 ropt_net_172:10 0.0045 +9 ropt_net_172:10 ropt_net_172:9 0.008419643 +10 ropt_net_172:5 ropt_net_172:4 0.004209822 + +*END + +*D_NET chany_bottom_out[15] 0.002221118 //LENGTH 16.290 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 65.780 6.460 +*P chany_bottom_out[15] O *L 0.7423 *C 55.200 1.325 +*N chany_bottom_out[15]:2 *C 55.200 6.075 +*N chany_bottom_out[15]:3 *C 55.245 6.120 +*N chany_bottom_out[15]:4 *C 65.780 6.120 +*N chany_bottom_out[15]:5 *C 65.780 6.460 + +*CAP +0 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[15] 0.0002965542 +2 chany_bottom_out[15]:2 0.0002965542 +3 chany_bottom_out[15]:3 0.0007708192 +4 chany_bottom_out[15]:4 0.000798963 +5 chany_bottom_out[15]:5 5.722711e-05 + +*RES +0 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[15]:5 0.152 +1 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.0045 +2 chany_bottom_out[15]:2 chany_bottom_out[15] 0.004241071 +3 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.0003035715 +4 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.00940625 + +*END + +*D_NET chanx_left_out[2] 0.001543604 //LENGTH 14.860 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 10.065 39.100 +*P chanx_left_out[2] O *L 0.7423 *C 1.298 34.000 +*N chanx_left_out[2]:2 *C 1.380 34.000 +*N chanx_left_out[2]:3 *C 1.380 34.000 +*N chanx_left_out[2]:4 *C 2.300 34.000 +*N chanx_left_out[2]:5 *C 2.300 39.055 +*N chanx_left_out[2]:6 *C 2.345 39.100 +*N chanx_left_out[2]:7 *C 10.027 39.100 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 2.764577e-05 +2 chanx_left_out[2]:2 2.764577e-05 +3 chanx_left_out[2]:3 8.268622e-05 +4 chanx_left_out[2]:4 0.0003003279 +5 chanx_left_out[2]:5 0.0002489491 +6 chanx_left_out[2]:6 0.0004276746 +7 chanx_left_out[2]:7 0.0004276746 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:7 0.152 +1 chanx_left_out[2]:7 chanx_left_out[2]:6 0.006859375 +2 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0045 +3 chanx_left_out[2]:5 chanx_left_out[2]:4 0.004513393 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 2.35e-05 +6 chanx_left_out[2]:4 chanx_left_out[2]:3 0.0008214285 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.001913672 //LENGTH 16.257 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 98.285 6.460 +*I mux_bottom_track_27\/mux_l2_in_0_:S I *L 0.008363 *C 90.868 3.803 +*I mem_bottom_track_27\/FTB_28__53:A I *L 0.001746 *C 103.040 6.800 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 103.003 6.800 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 98.440 6.800 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 98.395 3.740 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 98.440 3.785 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 98.440 6.415 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 98.440 6.460 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 98.285 6.460 + +*CAP +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_27\/mux_l2_in_0_:S 0.0004652374 +2 mem_bottom_track_27\/FTB_28__53:A 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 0.0002782928 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0002966893 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.0004652374 +6 mux_tree_tapbuf_size2_0_sram[1]:6 0.0001473102 +7 mux_tree_tapbuf_size2_0_sram[1]:7 0.0001473102 +8 mux_tree_tapbuf_size2_0_sram[1]:8 6.730911e-05 +9 mux_tree_tapbuf_size2_0_sram[1]:9 4.428528e-05 + +*RES +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:9 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.0045 +2 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:4 0.0003035715 +3 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.002348214 +4 mux_tree_tapbuf_size2_0_sram[1]:5 mux_bottom_track_27\/mux_l2_in_0_:S 0.006720982 +5 mux_tree_tapbuf_size2_0_sram[1]:6 mux_tree_tapbuf_size2_0_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size2_0_sram[1]:3 mem_bottom_track_27\/FTB_28__53:A 0.152 +7 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 8.423914e-05 +8 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.004073661 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[0] 0.001865978 //LENGTH 15.765 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.065 6.800 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.955 9.860 +*I mux_bottom_track_39\/mux_l1_in_0_:S I *L 0.00357 *C 47.280 12.535 +*N mux_tree_tapbuf_size2_6_sram[0]:3 *C 47.280 12.535 +*N mux_tree_tapbuf_size2_6_sram[0]:4 *C 47.223 12.240 +*N mux_tree_tapbuf_size2_6_sram[0]:5 *C 42.992 9.860 +*N mux_tree_tapbuf_size2_6_sram[0]:6 *C 44.575 9.860 +*N mux_tree_tapbuf_size2_6_sram[0]:7 *C 44.620 9.905 +*N mux_tree_tapbuf_size2_6_sram[0]:8 *C 44.620 12.195 +*N mux_tree_tapbuf_size2_6_sram[0]:9 *C 44.665 12.240 +*N mux_tree_tapbuf_size2_6_sram[0]:10 *C 47.323 12.270 +*N mux_tree_tapbuf_size2_6_sram[0]:11 *C 47.380 12.195 +*N mux_tree_tapbuf_size2_6_sram[0]:12 *C 47.380 6.845 +*N mux_tree_tapbuf_size2_6_sram[0]:13 *C 47.425 6.800 +*N mux_tree_tapbuf_size2_6_sram[0]:14 *C 49.028 6.800 + +*CAP +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_39\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_6_sram[0]:3 4.823918e-05 +4 mux_tree_tapbuf_size2_6_sram[0]:4 1.80475e-05 +5 mux_tree_tapbuf_size2_6_sram[0]:5 0.0001232895 +6 mux_tree_tapbuf_size2_6_sram[0]:6 0.0001232895 +7 mux_tree_tapbuf_size2_6_sram[0]:7 0.0001286811 +8 mux_tree_tapbuf_size2_6_sram[0]:8 0.0001286811 +9 mux_tree_tapbuf_size2_6_sram[0]:9 0.0001833191 +10 mux_tree_tapbuf_size2_6_sram[0]:10 0.0002231891 +11 mux_tree_tapbuf_size2_6_sram[0]:11 0.0002929005 +12 mux_tree_tapbuf_size2_6_sram[0]:12 0.0002929005 +13 mux_tree_tapbuf_size2_6_sram[0]:13 0.0001502207 +14 mux_tree_tapbuf_size2_6_sram[0]:14 0.0001502207 + +*RES +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_6_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_6_sram[0]:3 mux_bottom_track_39\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:7 0.002044643 +4 mux_tree_tapbuf_size2_6_sram[0]:6 mux_tree_tapbuf_size2_6_sram[0]:5 0.001412946 +5 mux_tree_tapbuf_size2_6_sram[0]:7 mux_tree_tapbuf_size2_6_sram[0]:6 0.0045 +6 mux_tree_tapbuf_size2_6_sram[0]:5 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:9 0.002372768 +8 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:4 8.928572e-05 +9 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:3 0.0001142241 +10 mux_tree_tapbuf_size2_6_sram[0]:11 mux_tree_tapbuf_size2_6_sram[0]:10 0.0045 +11 mux_tree_tapbuf_size2_6_sram[0]:13 mux_tree_tapbuf_size2_6_sram[0]:12 0.0045 +12 mux_tree_tapbuf_size2_6_sram[0]:12 mux_tree_tapbuf_size2_6_sram[0]:11 0.004776786 +13 mux_tree_tapbuf_size2_6_sram[0]:14 mux_tree_tapbuf_size2_6_sram[0]:13 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.00132876 //LENGTH 11.700 LUMPCC 0 DR + +*CONN +*I mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 108.865 26.180 +*I mux_right_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 110.760 31.280 +*I mem_right_track_32\/FTB_13__38:A I *L 0.001746 *C 109.020 34.000 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 108.983 34.000 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 108.605 34.000 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 108.560 33.955 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 110.723 31.280 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 108.605 31.280 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 108.560 31.280 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 108.560 26.225 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 108.560 26.180 +*N mux_tree_tapbuf_size3_0_sram[1]:11 *C 108.865 26.180 + +*CAP +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:S 1e-06 +2 mem_right_track_32\/FTB_13__38:A 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 4.199401e-05 +4 mux_tree_tapbuf_size3_0_sram[1]:4 4.199401e-05 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0001407422 +6 mux_tree_tapbuf_size3_0_sram[1]:6 0.0001446069 +7 mux_tree_tapbuf_size3_0_sram[1]:7 0.0001446069 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0004529646 +9 mux_tree_tapbuf_size3_0_sram[1]:9 0.0002777227 +10 mux_tree_tapbuf_size3_0_sram[1]:10 4.229454e-05 +11 mux_tree_tapbuf_size3_0_sram[1]:11 3.883394e-05 + +*RES +0 mem_right_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.0003370536 +2 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size3_0_sram[1]:3 mem_right_track_32\/FTB_13__38:A 0.152 +4 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.001890625 +5 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:5 0.002388393 +7 mux_tree_tapbuf_size3_0_sram[1]:6 mux_right_track_32\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.004513392 +10 mux_tree_tapbuf_size3_0_sram[1]:11 mux_tree_tapbuf_size3_0_sram[1]:10 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[1] 0.0008738168 //LENGTH 6.495 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.025 17.680 +*I mem_bottom_track_17\/FTB_16__41:A I *L 0.001746 *C 61.180 20.400 +*I mux_bottom_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 58.320 20.400 +*N mux_tree_tapbuf_size3_3_sram[1]:3 *C 58.358 20.400 +*N mux_tree_tapbuf_size3_3_sram[1]:4 *C 61.143 20.400 +*N mux_tree_tapbuf_size3_3_sram[1]:5 *C 61.180 20.355 +*N mux_tree_tapbuf_size3_3_sram[1]:6 *C 61.180 17.725 +*N mux_tree_tapbuf_size3_3_sram[1]:7 *C 61.180 17.680 +*N mux_tree_tapbuf_size3_3_sram[1]:8 *C 61.025 17.680 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_17\/FTB_16__41:A 1e-06 +2 mux_bottom_track_17\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_3_sram[1]:3 0.0001971233 +4 mux_tree_tapbuf_size3_3_sram[1]:4 0.0001971233 +5 mux_tree_tapbuf_size3_3_sram[1]:5 0.0001882534 +6 mux_tree_tapbuf_size3_3_sram[1]:6 0.0001882534 +7 mux_tree_tapbuf_size3_3_sram[1]:7 5.235232e-05 +8 mux_tree_tapbuf_size3_3_sram[1]:8 4.7711e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_3_sram[1]:8 0.152 +1 mux_tree_tapbuf_size3_3_sram[1]:4 mem_bottom_track_17\/FTB_16__41:A 0.152 +2 mux_tree_tapbuf_size3_3_sram[1]:4 mux_tree_tapbuf_size3_3_sram[1]:3 0.002486607 +3 mux_tree_tapbuf_size3_3_sram[1]:3 mux_bottom_track_17\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size3_3_sram[1]:5 mux_tree_tapbuf_size3_3_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size3_3_sram[1]:7 mux_tree_tapbuf_size3_3_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size3_3_sram[1]:6 mux_tree_tapbuf_size3_3_sram[1]:5 0.002348214 +7 mux_tree_tapbuf_size3_3_sram[1]:8 mux_tree_tapbuf_size3_3_sram[1]:7 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.00106752 //LENGTH 8.310 LUMPCC 0.0002731248 DR + +*CONN +*I mem_bottom_track_13\/FTB_14__39:X O *L 0 *C 53.135 39.440 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 51.695 33.660 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 51.695 33.660 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 51.520 33.660 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 51.520 33.705 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 51.520 39.395 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 51.565 39.440 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 53.098 39.440 + +*CAP +0 mem_bottom_track_13\/FTB_14__39:X 1e-06 +1 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 5.799707e-05 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 6.10612e-05 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.0002322217 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0002322217 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0001044466 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0001044466 +8 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 prog_clk[0]:518 6.66481e-05 +9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 prog_clk[0]:521 6.674675e-05 +10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 prog_clk[0]:531 3.167526e-06 +11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 prog_clk[0]:521 6.66481e-05 +12 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 prog_clk[0]:522 6.674675e-05 +13 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 prog_clk[0]:532 3.167526e-06 + +*RES +0 mem_bottom_track_13\/FTB_14__39:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.001368304 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.005080357 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_6_ccff_tail[0] 0.0004649377 //LENGTH 3.275 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_23\/FTB_19__44:X O *L 0 *C 97.260 38.760 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 96.315 37.060 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 *C 96.315 37.060 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 *C 96.600 37.060 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 *C 96.600 37.105 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 *C 96.600 38.715 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 *C 96.645 38.760 +*N mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 *C 97.223 38.760 + +*CAP +0 mem_bottom_track_23\/FTB_19__44:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 5.592555e-05 +3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 6.040531e-05 +4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 0.0001084074 +5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 0.0001084074 +6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 6.489607e-05 +7 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 6.489607e-05 + +*RES +0 mem_bottom_track_23\/FTB_19__44:X mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_6_ccff_tail[0]:6 0.000515625 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[2] 0.001674938 //LENGTH 14.915 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 40.200 69.020 +*I mux_bottom_track_11\/mux_l3_in_0_:S I *L 0.00357 *C 41.300 67.320 +*I mem_bottom_track_11\/FTB_25__50:A I *L 0.001746 *C 42.780 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:3 *C 42.742 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:4 *C 41.905 58.480 +*N mux_tree_tapbuf_size4_1_sram[2]:5 *C 41.860 58.525 +*N mux_tree_tapbuf_size4_1_sram[2]:6 *C 41.337 67.320 +*N mux_tree_tapbuf_size4_1_sram[2]:7 *C 41.815 67.320 +*N mux_tree_tapbuf_size4_1_sram[2]:8 *C 41.860 67.320 +*N mux_tree_tapbuf_size4_1_sram[2]:9 *C 41.860 68.975 +*N mux_tree_tapbuf_size4_1_sram[2]:10 *C 41.815 69.020 +*N mux_tree_tapbuf_size4_1_sram[2]:11 *C 40.238 69.020 + +*CAP +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_11\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_11\/FTB_25__50:A 1e-06 +3 mux_tree_tapbuf_size4_1_sram[2]:3 6.911309e-05 +4 mux_tree_tapbuf_size4_1_sram[2]:4 6.911309e-05 +5 mux_tree_tapbuf_size4_1_sram[2]:5 0.0004768176 +6 mux_tree_tapbuf_size4_1_sram[2]:6 5.839399e-05 +7 mux_tree_tapbuf_size4_1_sram[2]:7 5.839399e-05 +8 mux_tree_tapbuf_size4_1_sram[2]:8 0.0006049663 +9 mux_tree_tapbuf_size4_1_sram[2]:9 9.793971e-05 +10 mux_tree_tapbuf_size4_1_sram[2]:10 0.0001186003 +11 mux_tree_tapbuf_size4_1_sram[2]:11 0.0001186003 + +*RES +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_1_sram[2]:11 0.152 +1 mux_tree_tapbuf_size4_1_sram[2]:11 mux_tree_tapbuf_size4_1_sram[2]:10 0.001408482 +2 mux_tree_tapbuf_size4_1_sram[2]:10 mux_tree_tapbuf_size4_1_sram[2]:9 0.0045 +3 mux_tree_tapbuf_size4_1_sram[2]:9 mux_tree_tapbuf_size4_1_sram[2]:8 0.001477679 +4 mux_tree_tapbuf_size4_1_sram[2]:4 mux_tree_tapbuf_size4_1_sram[2]:3 0.0007477679 +5 mux_tree_tapbuf_size4_1_sram[2]:5 mux_tree_tapbuf_size4_1_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size4_1_sram[2]:3 mem_bottom_track_11\/FTB_25__50:A 0.152 +7 mux_tree_tapbuf_size4_1_sram[2]:6 mux_bottom_track_11\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_1_sram[2]:7 mux_tree_tapbuf_size4_1_sram[2]:6 0.0004263393 +9 mux_tree_tapbuf_size4_1_sram[2]:8 mux_tree_tapbuf_size4_1_sram[2]:7 0.0045 +10 mux_tree_tapbuf_size4_1_sram[2]:8 mux_tree_tapbuf_size4_1_sram[2]:5 0.007852679 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_2_ccff_tail[0] 0.001133464 //LENGTH 9.220 LUMPCC 0.0001144449 DR + +*CONN +*I mem_bottom_track_25\/FTB_26__51:X O *L 0 *C 95.445 17.680 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 93.095 11.900 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 *C 93.095 11.900 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 *C 92.920 11.900 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 *C 92.920 11.945 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 *C 92.920 17.635 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 *C 92.965 17.680 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 *C 95.407 17.680 + +*CAP +0 mem_bottom_track_25\/FTB_26__51:X 1e-06 +1 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 5.700619e-05 +3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 6.228154e-05 +4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 0.0002921671 +5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 0.0002921671 +6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 0.0001566985 +7 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 0.0001566985 +8 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.722243e-05 +9 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.722243e-05 + +*RES +0 mem_bottom_track_25\/FTB_26__51:X mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 0.002180804 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 0.005080357 +4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 9.510871e-05 +5 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[0] 0.004619202 //LENGTH 32.785 LUMPCC 0.0008640668 DR + +*CONN +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 106.105 49.980 +*I mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 85.735 47.940 +*I mux_right_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 83.160 44.880 +*I mux_right_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 83.620 42.160 +*N mux_tree_tapbuf_size5_1_sram[0]:4 *C 83.620 42.160 +*N mux_tree_tapbuf_size5_1_sram[0]:5 *C 83.720 42.205 +*N mux_tree_tapbuf_size5_1_sram[0]:6 *C 83.198 44.880 +*N mux_tree_tapbuf_size5_1_sram[0]:7 *C 83.720 44.880 +*N mux_tree_tapbuf_size5_1_sram[0]:8 *C 83.720 45.220 +*N mux_tree_tapbuf_size5_1_sram[0]:9 *C 83.720 45.220 +*N mux_tree_tapbuf_size5_1_sram[0]:10 *C 83.720 47.895 +*N mux_tree_tapbuf_size5_1_sram[0]:11 *C 83.765 47.940 +*N mux_tree_tapbuf_size5_1_sram[0]:12 *C 85.735 47.940 +*N mux_tree_tapbuf_size5_1_sram[0]:13 *C 101.615 47.940 +*N mux_tree_tapbuf_size5_1_sram[0]:14 *C 101.660 47.985 +*N mux_tree_tapbuf_size5_1_sram[0]:15 *C 101.660 49.935 +*N mux_tree_tapbuf_size5_1_sram[0]:16 *C 101.705 49.980 +*N mux_tree_tapbuf_size5_1_sram[0]:17 *C 106.068 49.980 + +*CAP +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_right_track_16\/mux_l1_in_1_:S 1e-06 +3 mux_right_track_16\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[0]:4 3.00334e-05 +5 mux_tree_tapbuf_size5_1_sram[0]:5 0.0001906813 +6 mux_tree_tapbuf_size5_1_sram[0]:6 5.91252e-05 +7 mux_tree_tapbuf_size5_1_sram[0]:7 9.22402e-05 +8 mux_tree_tapbuf_size5_1_sram[0]:8 7.338995e-05 +9 mux_tree_tapbuf_size5_1_sram[0]:9 0.0003860996 +10 mux_tree_tapbuf_size5_1_sram[0]:10 0.0001606802 +11 mux_tree_tapbuf_size5_1_sram[0]:11 0.0001372637 +12 mux_tree_tapbuf_size5_1_sram[0]:12 0.0009935694 +13 mux_tree_tapbuf_size5_1_sram[0]:13 0.0008280732 +14 mux_tree_tapbuf_size5_1_sram[0]:14 0.000111551 +15 mux_tree_tapbuf_size5_1_sram[0]:15 0.000111551 +16 mux_tree_tapbuf_size5_1_sram[0]:16 0.0002884385 +17 mux_tree_tapbuf_size5_1_sram[0]:17 0.0002884385 +18 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 6.399684e-05 +19 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 6.399684e-05 +20 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 1.338769e-05 +21 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 1.338769e-05 +22 mux_tree_tapbuf_size5_1_sram[0]:12 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003546489 +23 mux_tree_tapbuf_size5_1_sram[0]:13 mux_right_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003546489 + +*RES +0 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_1_sram[0]:17 0.152 +1 mux_tree_tapbuf_size5_1_sram[0]:11 mux_tree_tapbuf_size5_1_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size5_1_sram[0]:9 0.002388393 +3 mux_tree_tapbuf_size5_1_sram[0]:8 mux_tree_tapbuf_size5_1_sram[0]:7 0.0003035715 +4 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:5 0.002691964 +6 mux_tree_tapbuf_size5_1_sram[0]:6 mux_right_track_16\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size5_1_sram[0]:4 mux_right_track_16\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_1_sram[0]:5 mux_tree_tapbuf_size5_1_sram[0]:4 0.0045 +9 mux_tree_tapbuf_size5_1_sram[0]:12 mem_right_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size5_1_sram[0]:11 0.001758929 +11 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:12 0.01417857 +12 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size5_1_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:15 0.0045 +14 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:14 0.001741071 +15 mux_tree_tapbuf_size5_1_sram[0]:17 mux_tree_tapbuf_size5_1_sram[0]:16 0.003895089 +16 mux_tree_tapbuf_size5_1_sram[0]:7 mux_tree_tapbuf_size5_1_sram[0]:6 0.0004665179 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[0] 0.002678029 //LENGTH 18.975 LUMPCC 0.0004844699 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 76.020 37.400 +*I mux_left_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 76.000 39.735 +*I mux_left_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 81.980 39.440 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 72.855 44.540 +*N mux_tree_tapbuf_size5_4_sram[0]:4 *C 72.892 44.540 +*N mux_tree_tapbuf_size5_4_sram[0]:5 *C 75.855 44.540 +*N mux_tree_tapbuf_size5_4_sram[0]:6 *C 75.900 44.495 +*N mux_tree_tapbuf_size5_4_sram[0]:7 *C 81.943 39.440 +*N mux_tree_tapbuf_size5_4_sram[0]:8 *C 77.280 39.440 +*N mux_tree_tapbuf_size5_4_sram[0]:9 *C 77.280 39.100 +*N mux_tree_tapbuf_size5_4_sram[0]:10 *C 76.000 39.735 +*N mux_tree_tapbuf_size5_4_sram[0]:11 *C 75.970 39.510 +*N mux_tree_tapbuf_size5_4_sram[0]:12 *C 75.855 39.370 +*N mux_tree_tapbuf_size5_4_sram[0]:13 *C 75.900 39.100 +*N mux_tree_tapbuf_size5_4_sram[0]:14 *C 75.900 39.100 +*N mux_tree_tapbuf_size5_4_sram[0]:15 *C 75.900 37.445 +*N mux_tree_tapbuf_size5_4_sram[0]:16 *C 75.900 37.400 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_3\/mux_l1_in_0_:S 1e-06 +2 mux_left_track_3\/mux_l1_in_1_:S 1e-06 +3 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_4_sram[0]:4 0.0002641343 +5 mux_tree_tapbuf_size5_4_sram[0]:5 0.0002641343 +6 mux_tree_tapbuf_size5_4_sram[0]:6 0.0001972796 +7 mux_tree_tapbuf_size5_4_sram[0]:7 0.0003178274 +8 mux_tree_tapbuf_size5_4_sram[0]:8 0.0003453518 +9 mux_tree_tapbuf_size5_4_sram[0]:9 0.000127903 +10 mux_tree_tapbuf_size5_4_sram[0]:10 5.64035e-05 +11 mux_tree_tapbuf_size5_4_sram[0]:11 3.25205e-05 +12 mux_tree_tapbuf_size5_4_sram[0]:12 3.177345e-05 +13 mux_tree_tapbuf_size5_4_sram[0]:13 0.0001269173 +14 mux_tree_tapbuf_size5_4_sram[0]:14 0.000310721 +15 mux_tree_tapbuf_size5_4_sram[0]:15 8.105628e-05 +16 mux_tree_tapbuf_size5_4_sram[0]:16 3.353638e-05 +17 mux_tree_tapbuf_size5_4_sram[0]:15 chany_bottom_in[5]:19 4.167219e-05 +18 mux_tree_tapbuf_size5_4_sram[0]:14 chany_bottom_in[5]:18 4.167219e-05 +19 mux_tree_tapbuf_size5_4_sram[0]:14 chany_bottom_in[5]:19 0.0001309667 +20 mux_tree_tapbuf_size5_4_sram[0]:5 chany_bottom_in[5]:17 1.144375e-05 +21 mux_tree_tapbuf_size5_4_sram[0]:6 chany_bottom_in[5]:18 0.0001309667 +22 mux_tree_tapbuf_size5_4_sram[0]:4 chany_bottom_in[5]:18 1.144375e-05 +23 mux_tree_tapbuf_size5_4_sram[0]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.970014e-06 +24 mux_tree_tapbuf_size5_4_sram[0]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.138848e-05 +25 mux_tree_tapbuf_size5_4_sram[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.138848e-05 +26 mux_tree_tapbuf_size5_4_sram[0]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.7938e-06 +27 mux_tree_tapbuf_size5_4_sram[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.7938e-06 +28 mux_tree_tapbuf_size5_4_sram[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.970014e-06 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_4_sram[0]:16 0.152 +1 mux_tree_tapbuf_size5_4_sram[0]:16 mux_tree_tapbuf_size5_4_sram[0]:15 0.0045 +2 mux_tree_tapbuf_size5_4_sram[0]:15 mux_tree_tapbuf_size5_4_sram[0]:14 0.001477679 +3 mux_tree_tapbuf_size5_4_sram[0]:10 mux_left_track_3\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size5_4_sram[0]:7 mux_left_track_3\/mux_l1_in_1_:S 0.152 +5 mux_tree_tapbuf_size5_4_sram[0]:13 mux_tree_tapbuf_size5_4_sram[0]:12 0.0002410715 +6 mux_tree_tapbuf_size5_4_sram[0]:13 mux_tree_tapbuf_size5_4_sram[0]:9 0.001232143 +7 mux_tree_tapbuf_size5_4_sram[0]:14 mux_tree_tapbuf_size5_4_sram[0]:13 0.0045 +8 mux_tree_tapbuf_size5_4_sram[0]:14 mux_tree_tapbuf_size5_4_sram[0]:6 0.004816965 +9 mux_tree_tapbuf_size5_4_sram[0]:5 mux_tree_tapbuf_size5_4_sram[0]:4 0.002645089 +10 mux_tree_tapbuf_size5_4_sram[0]:6 mux_tree_tapbuf_size5_4_sram[0]:5 0.0045 +11 mux_tree_tapbuf_size5_4_sram[0]:4 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size5_4_sram[0]:12 mux_tree_tapbuf_size5_4_sram[0]:11 0.0001026786 +13 mux_tree_tapbuf_size5_4_sram[0]:11 mux_tree_tapbuf_size5_4_sram[0]:10 0.000130814 +14 mux_tree_tapbuf_size5_4_sram[0]:9 mux_tree_tapbuf_size5_4_sram[0]:8 0.0003035715 +15 mux_tree_tapbuf_size5_4_sram[0]:8 mux_tree_tapbuf_size5_4_sram[0]:7 0.004162947 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_0_ccff_tail[0] 0.001023162 //LENGTH 7.575 LUMPCC 0 DR + +*CONN +*I mem_right_track_2\/FTB_6__31:X O *L 0 *C 88.065 60.860 +*I mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 83.430 58.820 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 *C 83.430 58.820 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 *C 87.355 58.820 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 *C 87.400 58.865 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 *C 87.400 60.815 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 *C 87.445 60.860 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 *C 88.028 60.860 + +*CAP +0 mem_right_track_2\/FTB_6__31:X 1e-06 +1 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 0.0003277631 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0002931289 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0001288124 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0001288124 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 7.132239e-05 +7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 7.132239e-05 + +*RES +0 mem_right_track_2\/FTB_6__31:X mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 mem_right_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 0.003504464 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.0005200893 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.003685465 //LENGTH 30.785 LUMPCC 0.00022556 DR + +*CONN +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 99.665 80.240 +*I mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 94.935 82.620 +*I mux_right_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 95.120 74.800 +*I mux_right_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 108.000 74.120 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 108.000 74.120 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 108.100 74.165 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 108.100 75.435 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 108.055 75.480 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 95.120 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 94.935 82.620 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 95.220 82.620 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 95.220 82.575 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 95.220 75.185 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 95.265 75.140 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 100.740 75.140 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 100.740 75.480 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 100.740 75.525 +*N mux_tree_tapbuf_size6_0_sram[1]:17 *C 100.740 80.195 +*N mux_tree_tapbuf_size6_0_sram[1]:18 *C 100.695 80.240 +*N mux_tree_tapbuf_size6_0_sram[1]:19 *C 99.703 80.240 + +*CAP +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_right_track_0\/mux_l2_in_0_:S 1e-06 +3 mux_right_track_0\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 2.558179e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 8.192312e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 8.192312e-05 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.0005026072 +8 mux_tree_tapbuf_size6_0_sram[1]:8 5.668518e-05 +9 mux_tree_tapbuf_size6_0_sram[1]:9 4.645747e-05 +10 mux_tree_tapbuf_size6_0_sram[1]:10 5.043312e-05 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0004021545 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0004021545 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.000288919 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.0002826404 +15 mux_tree_tapbuf_size6_0_sram[1]:15 0.0005271669 +16 mux_tree_tapbuf_size6_0_sram[1]:16 0.0002712454 +17 mux_tree_tapbuf_size6_0_sram[1]:17 0.0002712454 +18 mux_tree_tapbuf_size6_0_sram[1]:18 8.238421e-05 +19 mux_tree_tapbuf_size6_0_sram[1]:19 8.238421e-05 +20 mux_tree_tapbuf_size6_0_sram[1]:13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 8.705376e-05 +21 mux_tree_tapbuf_size6_0_sram[1]:15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 2.127852e-05 +22 mux_tree_tapbuf_size6_0_sram[1]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 2.127852e-05 +23 mux_tree_tapbuf_size6_0_sram[1]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.447691e-06 +24 mux_tree_tapbuf_size6_0_sram[1]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 4.447691e-06 +25 mux_tree_tapbuf_size6_0_sram[1]:14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 8.705376e-05 + +*RES +0 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:19 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0045 +2 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:8 0.0001847826 +3 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:11 0.006598215 +4 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.0001548913 +5 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size6_0_sram[1]:9 mem_right_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.0003035715 +8 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:7 0.00653125 +9 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.0045 +10 mux_tree_tapbuf_size6_0_sram[1]:18 mux_tree_tapbuf_size6_0_sram[1]:17 0.0045 +11 mux_tree_tapbuf_size6_0_sram[1]:17 mux_tree_tapbuf_size6_0_sram[1]:16 0.004169643 +12 mux_tree_tapbuf_size6_0_sram[1]:19 mux_tree_tapbuf_size6_0_sram[1]:18 0.0008861608 +13 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[1]:6 0.0045 +14 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.001133929 +15 mux_tree_tapbuf_size6_0_sram[1]:4 mux_right_track_0\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size6_0_sram[1]:5 mux_tree_tapbuf_size6_0_sram[1]:4 0.0045 +17 mux_tree_tapbuf_size6_0_sram[1]:8 mux_right_track_0\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.004888393 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[2] 0.002511986 //LENGTH 17.875 LUMPCC 0.0001060444 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 49.065 47.600 +*I mem_left_track_5\/FTB_4__29:A I *L 0.001746 *C 43.240 50.320 +*I mux_left_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 41.500 45.175 +*N mux_tree_tapbuf_size6_3_sram[2]:3 *C 41.500 45.175 +*N mux_tree_tapbuf_size6_3_sram[2]:4 *C 41.558 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:5 *C 43.240 50.320 +*N mux_tree_tapbuf_size6_3_sram[2]:6 *C 43.240 50.275 +*N mux_tree_tapbuf_size6_3_sram[2]:7 *C 43.240 44.925 +*N mux_tree_tapbuf_size6_3_sram[2]:8 *C 43.240 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:9 *C 43.655 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:10 *C 43.700 44.925 +*N mux_tree_tapbuf_size6_3_sram[2]:11 *C 43.700 47.543 +*N mux_tree_tapbuf_size6_3_sram[2]:12 *C 43.708 47.600 +*N mux_tree_tapbuf_size6_3_sram[2]:13 *C 49.213 47.600 +*N mux_tree_tapbuf_size6_3_sram[2]:14 *C 49.220 47.600 +*N mux_tree_tapbuf_size6_3_sram[2]:15 *C 49.220 47.600 +*N mux_tree_tapbuf_size6_3_sram[2]:16 *C 49.065 47.600 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_5\/FTB_4__29:A 1e-06 +2 mux_left_track_5\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_3_sram[2]:3 7.172964e-05 +4 mux_tree_tapbuf_size6_3_sram[2]:4 0.0001428874 +5 mux_tree_tapbuf_size6_3_sram[2]:5 2.985398e-05 +6 mux_tree_tapbuf_size6_3_sram[2]:6 0.0002931215 +7 mux_tree_tapbuf_size6_3_sram[2]:7 0.0002931215 +8 mux_tree_tapbuf_size6_3_sram[2]:8 0.0001632088 +9 mux_tree_tapbuf_size6_3_sram[2]:9 2.333762e-05 +10 mux_tree_tapbuf_size6_3_sram[2]:10 0.0002002811 +11 mux_tree_tapbuf_size6_3_sram[2]:11 0.0002002811 +12 mux_tree_tapbuf_size6_3_sram[2]:12 0.000413399 +13 mux_tree_tapbuf_size6_3_sram[2]:13 0.000413399 +14 mux_tree_tapbuf_size6_3_sram[2]:14 3.957516e-05 +15 mux_tree_tapbuf_size6_3_sram[2]:15 6.069854e-05 +16 mux_tree_tapbuf_size6_3_sram[2]:16 5.804699e-05 +17 mux_tree_tapbuf_size6_3_sram[2]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.356542e-05 +18 mux_tree_tapbuf_size6_3_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.356542e-05 +19 mux_tree_tapbuf_size6_3_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.945677e-05 +20 mux_tree_tapbuf_size6_3_sram[2]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.945677e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_3_sram[2]:16 0.152 +1 mux_tree_tapbuf_size6_3_sram[2]:9 mux_tree_tapbuf_size6_3_sram[2]:8 0.0003705357 +2 mux_tree_tapbuf_size6_3_sram[2]:10 mux_tree_tapbuf_size6_3_sram[2]:9 0.0045 +3 mux_tree_tapbuf_size6_3_sram[2]:11 mux_tree_tapbuf_size6_3_sram[2]:10 0.002337054 +4 mux_tree_tapbuf_size6_3_sram[2]:12 mux_tree_tapbuf_size6_3_sram[2]:11 0.00341 +5 mux_tree_tapbuf_size6_3_sram[2]:14 mux_tree_tapbuf_size6_3_sram[2]:13 0.00341 +6 mux_tree_tapbuf_size6_3_sram[2]:13 mux_tree_tapbuf_size6_3_sram[2]:12 0.00086245 +7 mux_tree_tapbuf_size6_3_sram[2]:15 mux_tree_tapbuf_size6_3_sram[2]:14 0.0045 +8 mux_tree_tapbuf_size6_3_sram[2]:16 mux_tree_tapbuf_size6_3_sram[2]:15 8.423914e-05 +9 mux_tree_tapbuf_size6_3_sram[2]:3 mux_left_track_5\/mux_l3_in_0_:S 0.152 +10 mux_tree_tapbuf_size6_3_sram[2]:8 mux_tree_tapbuf_size6_3_sram[2]:7 0.0045 +11 mux_tree_tapbuf_size6_3_sram[2]:8 mux_tree_tapbuf_size6_3_sram[2]:4 0.001502232 +12 mux_tree_tapbuf_size6_3_sram[2]:7 mux_tree_tapbuf_size6_3_sram[2]:6 0.004776786 +13 mux_tree_tapbuf_size6_3_sram[2]:5 mem_left_track_5\/FTB_4__29:A 0.152 +14 mux_tree_tapbuf_size6_3_sram[2]:6 mux_tree_tapbuf_size6_3_sram[2]:5 0.0045 +15 mux_tree_tapbuf_size6_3_sram[2]:4 mux_tree_tapbuf_size6_3_sram[2]:3 0.0001715116 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_4_ccff_tail[0] 0.0005339683 //LENGTH 3.980 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/FTB_5__30:X O *L 0 *C 46.685 58.480 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 46.175 60.860 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 *C 46.175 60.860 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 *C 46.000 60.860 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 *C 46.000 60.815 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 *C 46.000 58.525 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 *C 46.045 58.480 +*N mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 *C 46.648 58.480 + +*CAP +0 mem_left_track_9\/FTB_5__30:X 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 5.181648e-05 +3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 5.53682e-05 +4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 0.0001548051 +5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 0.0001548051 +6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 5.758673e-05 +7 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 5.758673e-05 + +*RES +0 mem_left_track_9\/FTB_5__30:X mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_4_ccff_tail[0]:2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[0] 0.007459423 //LENGTH 58.470 LUMPCC 0.001037278 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.485 15.300 +*I mux_bottom_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 29.540 30.600 +*I mux_bottom_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 26.320 36.430 +*I mux_bottom_track_3\/mux_l1_in_2_:S I *L 0.00357 *C 15.080 41.480 +*I mux_bottom_track_3\/mux_l1_in_3_:S I *L 0.00357 *C 15.080 46.920 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 14.895 37.060 +*N mux_tree_tapbuf_size7_1_sram[0]:6 *C 14.895 37.060 +*N mux_tree_tapbuf_size7_1_sram[0]:7 *C 15.080 46.920 +*N mux_tree_tapbuf_size7_1_sram[0]:8 *C 15.180 46.875 +*N mux_tree_tapbuf_size7_1_sram[0]:9 *C 15.080 41.480 +*N mux_tree_tapbuf_size7_1_sram[0]:10 *C 15.180 41.480 +*N mux_tree_tapbuf_size7_1_sram[0]:11 *C 15.180 37.105 +*N mux_tree_tapbuf_size7_1_sram[0]:12 *C 15.225 37.060 +*N mux_tree_tapbuf_size7_1_sram[0]:13 *C 25.760 37.060 +*N mux_tree_tapbuf_size7_1_sram[0]:14 *C 25.760 36.720 +*N mux_tree_tapbuf_size7_1_sram[0]:15 *C 26.263 36.720 +*N mux_tree_tapbuf_size7_1_sram[0]:16 *C 26.320 36.430 +*N mux_tree_tapbuf_size7_1_sram[0]:17 *C 26.320 36.040 +*N mux_tree_tapbuf_size7_1_sram[0]:18 *C 28.935 36.040 +*N mux_tree_tapbuf_size7_1_sram[0]:19 *C 28.980 35.995 +*N mux_tree_tapbuf_size7_1_sram[0]:20 *C 28.980 31.280 +*N mux_tree_tapbuf_size7_1_sram[0]:21 *C 29.440 31.280 +*N mux_tree_tapbuf_size7_1_sram[0]:22 *C 29.440 30.600 +*N mux_tree_tapbuf_size7_1_sram[0]:23 *C 29.440 30.600 +*N mux_tree_tapbuf_size7_1_sram[0]:24 *C 29.440 25.160 +*N mux_tree_tapbuf_size7_1_sram[0]:25 *C 29.900 25.160 +*N mux_tree_tapbuf_size7_1_sram[0]:26 *C 29.900 18.405 +*N mux_tree_tapbuf_size7_1_sram[0]:27 *C 29.945 18.360 +*N mux_tree_tapbuf_size7_1_sram[0]:28 *C 35.375 18.360 +*N mux_tree_tapbuf_size7_1_sram[0]:29 *C 35.420 18.315 +*N mux_tree_tapbuf_size7_1_sram[0]:30 *C 35.420 15.345 +*N mux_tree_tapbuf_size7_1_sram[0]:31 *C 35.465 15.300 +*N mux_tree_tapbuf_size7_1_sram[0]:32 *C 38.448 15.300 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_3\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_3\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_track_3\/mux_l1_in_3_:S 1e-06 +5 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_1_sram[0]:6 5.048502e-05 +7 mux_tree_tapbuf_size7_1_sram[0]:7 2.874567e-05 +8 mux_tree_tapbuf_size7_1_sram[0]:8 0.0002677929 +9 mux_tree_tapbuf_size7_1_sram[0]:9 2.978596e-05 +10 mux_tree_tapbuf_size7_1_sram[0]:10 0.0004883066 +11 mux_tree_tapbuf_size7_1_sram[0]:11 0.000187067 +12 mux_tree_tapbuf_size7_1_sram[0]:12 0.0007621349 +13 mux_tree_tapbuf_size7_1_sram[0]:13 0.0007623326 +14 mux_tree_tapbuf_size7_1_sram[0]:14 7.509381e-05 +15 mux_tree_tapbuf_size7_1_sram[0]:15 7.837395e-05 +16 mux_tree_tapbuf_size7_1_sram[0]:16 8.000826e-05 +17 mux_tree_tapbuf_size7_1_sram[0]:17 0.0002166696 +18 mux_tree_tapbuf_size7_1_sram[0]:18 0.000188449 +19 mux_tree_tapbuf_size7_1_sram[0]:19 0.000203905 +20 mux_tree_tapbuf_size7_1_sram[0]:20 0.0002342113 +21 mux_tree_tapbuf_size7_1_sram[0]:21 7.077417e-05 +22 mux_tree_tapbuf_size7_1_sram[0]:22 3.42662e-05 +23 mux_tree_tapbuf_size7_1_sram[0]:23 0.0003419931 +24 mux_tree_tapbuf_size7_1_sram[0]:24 0.0002985449 +25 mux_tree_tapbuf_size7_1_sram[0]:25 0.0002419953 +26 mux_tree_tapbuf_size7_1_sram[0]:26 0.0002188273 +27 mux_tree_tapbuf_size7_1_sram[0]:27 0.000362642 +28 mux_tree_tapbuf_size7_1_sram[0]:28 0.000362642 +29 mux_tree_tapbuf_size7_1_sram[0]:29 0.0002166109 +30 mux_tree_tapbuf_size7_1_sram[0]:30 0.0002166109 +31 mux_tree_tapbuf_size7_1_sram[0]:31 0.0001989376 +32 mux_tree_tapbuf_size7_1_sram[0]:32 0.0001989376 +33 mux_tree_tapbuf_size7_1_sram[0]:23 bottom_left_grid_pin_35_[0]:23 5.214785e-05 +34 mux_tree_tapbuf_size7_1_sram[0]:23 bottom_left_grid_pin_35_[0]:24 8.139396e-06 +35 mux_tree_tapbuf_size7_1_sram[0]:18 bottom_left_grid_pin_35_[0]:20 1.04219e-05 +36 mux_tree_tapbuf_size7_1_sram[0]:19 bottom_left_grid_pin_35_[0]:21 0.0001191097 +37 mux_tree_tapbuf_size7_1_sram[0]:26 bottom_left_grid_pin_35_[0]:24 0.0002001704 +38 mux_tree_tapbuf_size7_1_sram[0]:17 bottom_left_grid_pin_35_[0]:19 1.04219e-05 +39 mux_tree_tapbuf_size7_1_sram[0]:20 bottom_left_grid_pin_35_[0]:22 0.0001240303 +40 mux_tree_tapbuf_size7_1_sram[0]:21 bottom_left_grid_pin_35_[0]:23 1.306001e-05 +41 mux_tree_tapbuf_size7_1_sram[0]:24 bottom_left_grid_pin_35_[0]:24 5.214785e-05 +42 mux_tree_tapbuf_size7_1_sram[0]:25 bottom_left_grid_pin_35_[0]:23 0.0002001704 +43 mux_tree_tapbuf_size7_1_sram[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.009085e-06 +44 mux_tree_tapbuf_size7_1_sram[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.731477e-05 +45 mux_tree_tapbuf_size7_1_sram[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.009085e-06 +46 mux_tree_tapbuf_size7_1_sram[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.731477e-05 +47 mux_tree_tapbuf_size7_1_sram[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.098549e-05 +48 mux_tree_tapbuf_size7_1_sram[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.141982e-05 +49 mux_tree_tapbuf_size7_1_sram[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.098549e-05 +50 mux_tree_tapbuf_size7_1_sram[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.141982e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_1_sram[0]:32 0.152 +1 mux_tree_tapbuf_size7_1_sram[0]:22 mux_bottom_track_3\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:22 0.0045 +3 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:21 0.0006071429 +4 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size7_1_sram[0]:17 0.002334822 +5 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:18 0.0045 +6 mux_tree_tapbuf_size7_1_sram[0]:7 mux_bottom_track_3\/mux_l1_in_3_:S 0.152 +7 mux_tree_tapbuf_size7_1_sram[0]:8 mux_tree_tapbuf_size7_1_sram[0]:7 0.0045 +8 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:6 0.0001793479 +10 mux_tree_tapbuf_size7_1_sram[0]:11 mux_tree_tapbuf_size7_1_sram[0]:10 0.00390625 +11 mux_tree_tapbuf_size7_1_sram[0]:16 mux_bottom_track_3\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_1_sram[0]:16 mux_tree_tapbuf_size7_1_sram[0]:15 0.0001686047 +13 mux_tree_tapbuf_size7_1_sram[0]:32 mux_tree_tapbuf_size7_1_sram[0]:31 0.002662946 +14 mux_tree_tapbuf_size7_1_sram[0]:31 mux_tree_tapbuf_size7_1_sram[0]:30 0.0045 +15 mux_tree_tapbuf_size7_1_sram[0]:30 mux_tree_tapbuf_size7_1_sram[0]:29 0.002651786 +16 mux_tree_tapbuf_size7_1_sram[0]:28 mux_tree_tapbuf_size7_1_sram[0]:27 0.004848215 +17 mux_tree_tapbuf_size7_1_sram[0]:29 mux_tree_tapbuf_size7_1_sram[0]:28 0.0045 +18 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:26 0.0045 +19 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:25 0.00603125 +20 mux_tree_tapbuf_size7_1_sram[0]:9 mux_bottom_track_3\/mux_l1_in_2_:S 0.152 +21 mux_tree_tapbuf_size7_1_sram[0]:10 mux_tree_tapbuf_size7_1_sram[0]:9 0.0045 +22 mux_tree_tapbuf_size7_1_sram[0]:10 mux_tree_tapbuf_size7_1_sram[0]:8 0.004816964 +23 mux_tree_tapbuf_size7_1_sram[0]:6 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +24 mux_tree_tapbuf_size7_1_sram[0]:13 mux_tree_tapbuf_size7_1_sram[0]:12 0.00940625 +25 mux_tree_tapbuf_size7_1_sram[0]:14 mux_tree_tapbuf_size7_1_sram[0]:13 0.0003035715 +26 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:14 0.0004486607 +27 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size7_1_sram[0]:16 0.0003482143 +28 mux_tree_tapbuf_size7_1_sram[0]:20 mux_tree_tapbuf_size7_1_sram[0]:19 0.004209822 +29 mux_tree_tapbuf_size7_1_sram[0]:21 mux_tree_tapbuf_size7_1_sram[0]:20 0.0004107143 +30 mux_tree_tapbuf_size7_1_sram[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 0.004857143 +31 mux_tree_tapbuf_size7_1_sram[0]:25 mux_tree_tapbuf_size7_1_sram[0]:24 0.0004107143 + +*END + +*D_NET mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002810046 //LENGTH 22.785 LUMPCC 0.0006793672 DR + +*CONN +*I mux_right_track_0\/mux_l2_in_0_:X O *L 0 *C 95.965 74.460 +*I mux_right_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 111.420 79.900 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 111.383 79.900 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 109.020 79.900 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 109.020 80.240 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 106.305 80.240 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 106.260 80.195 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 106.260 74.505 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 106.215 74.460 +*N mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 96.002 74.460 + +*CAP +0 mux_right_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_right_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001054998 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001311225 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001936588 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001680361 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003081302 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003081302 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0004570503 +9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0004570503 +10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_0_sram[1]:6 4.447691e-06 +11 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_0_sram[1]:7 2.127852e-05 +12 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_0_sram[1]:14 8.705376e-05 +13 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_0_sram[1]:5 4.447691e-06 +14 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size6_0_sram[1]:13 8.705376e-05 +15 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size6_0_sram[1]:15 2.127852e-05 +16 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size6_0_sram[2]:6 9.80333e-05 +17 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_0_sram[2]:7 3.678483e-05 +18 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_0_sram[2]:6 3.678483e-05 +19 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_0_sram[2]:7 9.80333e-05 +20 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 optlc_net_164:9 9.208549e-05 +21 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 optlc_net_164:10 9.208549e-05 + +*RES +0 mux_right_track_0\/mux_l2_in_0_:X mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_right_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002424107 +3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.005080357 +6 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.009118304 +7 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 +8 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002109375 + +*END + +*D_NET optlc_net_164 0.01652706 //LENGTH 125.062 LUMPCC 0.003712467 DR + +*CONN +*I optlc_153:HI O *L 0 *C 80.040 55.080 +*I mux_right_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 88.035 53.380 +*I mux_left_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 58.710 49.640 +*I mux_left_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 76.190 48.280 +*I mux_right_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 75.615 59.160 +*I mux_left_track_33\/mux_l2_in_1_:A0 I *L 0.001631 *C 73.430 75.140 +*I mux_right_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 102.295 60.860 +*I mux_right_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 106.895 75.140 +*N optlc_net_164:8 *C 106.895 75.140 +*N optlc_net_164:9 *C 106.720 74.800 +*N optlc_net_164:10 *C 103.545 74.800 +*N optlc_net_164:11 *C 103.500 74.755 +*N optlc_net_164:12 *C 102.333 60.860 +*N optlc_net_164:13 *C 102.995 60.860 +*N optlc_net_164:14 *C 103.040 60.905 +*N optlc_net_164:15 *C 103.040 61.880 +*N optlc_net_164:16 *C 103.500 61.880 +*N optlc_net_164:17 *C 103.500 63.920 +*N optlc_net_164:18 *C 103.493 63.920 +*N optlc_net_164:19 *C 76.828 63.920 +*N optlc_net_164:20 *C 76.820 63.863 +*N optlc_net_164:21 *C 73.468 75.140 +*N optlc_net_164:22 *C 75.395 75.140 +*N optlc_net_164:23 *C 75.440 75.095 +*N optlc_net_164:24 *C 75.440 59.205 +*N optlc_net_164:25 *C 75.440 59.160 +*N optlc_net_164:26 *C 75.653 59.160 +*N optlc_net_164:27 *C 76.820 59.160 +*N optlc_net_164:28 *C 76.820 58.820 +*N optlc_net_164:29 *C 76.820 58.820 +*N optlc_net_164:30 *C 76.163 48.235 +*N optlc_net_164:31 *C 58.748 49.640 +*N optlc_net_164:32 *C 62.055 49.640 +*N optlc_net_164:33 *C 62.100 49.595 +*N optlc_net_164:34 *C 62.100 47.645 +*N optlc_net_164:35 *C 62.145 47.600 +*N optlc_net_164:36 *C 70.380 47.600 +*N optlc_net_164:37 *C 70.380 48.280 +*N optlc_net_164:38 *C 75.900 48.268 +*N optlc_net_164:39 *C 75.900 47.600 +*N optlc_net_164:40 *C 76.775 47.600 +*N optlc_net_164:41 *C 76.820 47.645 +*N optlc_net_164:42 *C 76.820 57.800 +*N optlc_net_164:43 *C 76.865 57.800 +*N optlc_net_164:44 *C 80.455 57.800 +*N optlc_net_164:45 *C 80.500 57.755 +*N optlc_net_164:46 *C 87.998 53.380 +*N optlc_net_164:47 *C 80.545 53.380 +*N optlc_net_164:48 *C 80.500 53.425 +*N optlc_net_164:49 *C 80.500 55.080 +*N optlc_net_164:50 *C 80.455 55.080 +*N optlc_net_164:51 *C 80.078 55.080 + +*CAP +0 optlc_153:HI 1e-06 +1 mux_right_track_16\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_9\/mux_l2_in_1_:A0 1e-06 +3 mux_left_track_3\/mux_l2_in_1_:A0 1e-06 +4 mux_right_track_2\/mux_l2_in_1_:A0 1e-06 +5 mux_left_track_33\/mux_l2_in_1_:A0 1e-06 +6 mux_right_track_4\/mux_l2_in_1_:A0 1e-06 +7 mux_right_track_0\/mux_l2_in_1_:A0 1e-06 +8 optlc_net_164:8 5.241554e-05 +9 optlc_net_164:9 0.0002037524 +10 optlc_net_164:10 0.0001787639 +11 optlc_net_164:11 0.0005473077 +12 optlc_net_164:12 7.061174e-05 +13 optlc_net_164:13 7.061174e-05 +14 optlc_net_164:14 7.405409e-05 +15 optlc_net_164:15 0.0001040388 +16 optlc_net_164:16 0.0001380045 +17 optlc_net_164:17 0.0006873366 +18 optlc_net_164:18 0.00113091 +19 optlc_net_164:19 0.00113091 +20 optlc_net_164:20 0.0002337351 +21 optlc_net_164:21 0.0001673895 +22 optlc_net_164:22 0.0001673895 +23 optlc_net_164:23 0.0007736717 +24 optlc_net_164:24 0.0007736717 +25 optlc_net_164:25 5.365636e-05 +26 optlc_net_164:26 0.0001024635 +27 optlc_net_164:27 0.0001079702 +28 optlc_net_164:28 5.944935e-05 +29 optlc_net_164:29 0.0003123127 +30 optlc_net_164:30 3.090088e-05 +31 optlc_net_164:31 0.0003053907 +32 optlc_net_164:32 0.0003053907 +33 optlc_net_164:33 0.0001400421 +34 optlc_net_164:34 0.0001400421 +35 optlc_net_164:35 0.0003534205 +36 optlc_net_164:36 0.0003980634 +37 optlc_net_164:37 0.0003415823 +38 optlc_net_164:38 0.0003731394 +39 optlc_net_164:39 0.0001229343 +40 optlc_net_164:40 7.763512e-05 +41 optlc_net_164:41 0.0004668793 +42 optlc_net_164:42 0.0005472481 +43 optlc_net_164:43 0.0002485654 +44 optlc_net_164:44 0.0002485654 +45 optlc_net_164:45 0.0001628448 +46 optlc_net_164:46 0.0004428328 +47 optlc_net_164:47 0.0004428328 +48 optlc_net_164:48 0.0001024796 +49 optlc_net_164:49 0.0003001409 +50 optlc_net_164:50 5.761987e-05 +51 optlc_net_164:51 5.761987e-05 +52 optlc_net_164:18 chanx_left_in[9]:19 0.000779154 +53 optlc_net_164:19 chanx_left_in[9]:20 0.000779154 +54 optlc_net_164:41 chany_bottom_in[5]:17 0.0001133691 +55 optlc_net_164:20 chany_bottom_in[5]:16 6.038888e-05 +56 optlc_net_164:42 chany_bottom_in[5]:16 0.0001133691 +57 optlc_net_164:42 chany_bottom_in[5]:17 1.165316e-05 +58 optlc_net_164:29 chany_bottom_in[5]:16 1.165316e-05 +59 optlc_net_164:29 chany_bottom_in[5]:17 6.038888e-05 +60 optlc_net_164:24 chany_bottom_in[5]:17 0.0001648838 +61 optlc_net_164:23 chany_bottom_in[5]:16 0.0001648838 +62 optlc_net_164:37 chany_bottom_in[5]:18 5.35769e-06 +63 optlc_net_164:38 chany_bottom_in[5]:17 5.35769e-06 +64 optlc_net_164:10 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 9.208549e-05 +65 optlc_net_164:9 mux_right_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.208549e-05 +66 optlc_net_164:18 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002319133 +67 optlc_net_164:19 mux_right_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002319133 +68 optlc_net_164:37 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001247327 +69 optlc_net_164:38 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001247327 +70 optlc_net_164:35 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.0002726954 +71 optlc_net_164:36 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.0002726954 + +*RES +0 optlc_153:HI optlc_net_164:51 0.152 +1 optlc_net_164:40 optlc_net_164:39 0.00078125 +2 optlc_net_164:41 optlc_net_164:40 0.0045 +3 optlc_net_164:17 optlc_net_164:16 0.001821429 +4 optlc_net_164:17 optlc_net_164:11 0.009674108 +5 optlc_net_164:18 optlc_net_164:17 0.00341 +6 optlc_net_164:20 optlc_net_164:19 0.00341 +7 optlc_net_164:19 optlc_net_164:18 0.004177516 +8 optlc_net_164:47 optlc_net_164:46 0.006654019 +9 optlc_net_164:48 optlc_net_164:47 0.0045 +10 optlc_net_164:46 mux_right_track_16\/mux_l2_in_1_:A0 0.152 +11 optlc_net_164:44 optlc_net_164:43 0.003205357 +12 optlc_net_164:45 optlc_net_164:44 0.0045 +13 optlc_net_164:43 optlc_net_164:42 0.0045 +14 optlc_net_164:42 optlc_net_164:41 0.009066965 +15 optlc_net_164:42 optlc_net_164:29 0.0009107143 +16 optlc_net_164:10 optlc_net_164:9 0.002834822 +17 optlc_net_164:11 optlc_net_164:10 0.0045 +18 optlc_net_164:8 mux_right_track_0\/mux_l2_in_1_:A0 0.152 +19 optlc_net_164:28 optlc_net_164:27 0.0003035715 +20 optlc_net_164:29 optlc_net_164:28 0.0045 +21 optlc_net_164:29 optlc_net_164:20 0.004502233 +22 optlc_net_164:30 mux_left_track_3\/mux_l2_in_1_:A0 0.152 +23 optlc_net_164:25 optlc_net_164:24 0.0045 +24 optlc_net_164:24 optlc_net_164:23 0.0141875 +25 optlc_net_164:22 optlc_net_164:21 0.001720982 +26 optlc_net_164:23 optlc_net_164:22 0.0045 +27 optlc_net_164:21 mux_left_track_33\/mux_l2_in_1_:A0 0.152 +28 optlc_net_164:31 mux_left_track_9\/mux_l2_in_1_:A0 0.152 +29 optlc_net_164:32 optlc_net_164:31 0.002953125 +30 optlc_net_164:33 optlc_net_164:32 0.0045 +31 optlc_net_164:35 optlc_net_164:34 0.0045 +32 optlc_net_164:34 optlc_net_164:33 0.001741071 +33 optlc_net_164:26 mux_right_track_2\/mux_l2_in_1_:A0 0.152 +34 optlc_net_164:26 optlc_net_164:25 0.0001154891 +35 optlc_net_164:50 optlc_net_164:49 0.0045 +36 optlc_net_164:49 optlc_net_164:48 0.001477679 +37 optlc_net_164:49 optlc_net_164:45 0.002388393 +38 optlc_net_164:51 optlc_net_164:50 0.0003370536 +39 optlc_net_164:13 optlc_net_164:12 0.0005915179 +40 optlc_net_164:14 optlc_net_164:13 0.0045 +41 optlc_net_164:12 mux_right_track_4\/mux_l2_in_1_:A0 0.152 +42 optlc_net_164:36 optlc_net_164:35 0.007352679 +43 optlc_net_164:37 optlc_net_164:36 0.0006071429 +44 optlc_net_164:38 optlc_net_164:37 0.004928572 +45 optlc_net_164:38 optlc_net_164:30 0.000234375 +46 optlc_net_164:27 optlc_net_164:26 0.001042411 +47 optlc_net_164:39 optlc_net_164:38 0.0005959822 +48 optlc_net_164:9 optlc_net_164:8 0.0003035715 +49 optlc_net_164:15 optlc_net_164:14 0.0008705358 +50 optlc_net_164:16 optlc_net_164:15 0.0004107143 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006272391 //LENGTH 4.195 LUMPCC 0.0001563938 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 63.305 31.620 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.040 34.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.002 34.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 63.525 34.340 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 63.480 34.295 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 63.480 31.665 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 63.480 31.620 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 63.305 31.620 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.10557e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.10557e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001178167 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001178167 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.776982e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.333059e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_right_in[14]:15 7.819692e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_right_in[14]:14 7.819692e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0117148 //LENGTH 90.025 LUMPCC 0.0032629 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_0_:X O *L 0 *C 69.175 47.940 +*I mux_left_track_3\/BUFT_P_132:A I *L 0.001766 *C 22.540 88.400 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 22.578 88.400 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 31.695 88.400 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 31.740 88.355 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 31.740 80.285 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 31.785 80.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 34.040 80.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 34.075 80.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 38.135 80.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 38.180 80.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 38.180 80.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 38.188 80.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 *C 51.513 80.240 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 *C 51.520 80.183 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 *C 51.520 47.985 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 *C 51.565 47.940 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 *C 69.138 47.940 + +*CAP +0 mux_left_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_3\/BUFT_P_132:A 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004753792 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0004753792 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003717936 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003717936 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001265987 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001517044 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0002026592 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001775535 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 5.094161e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 5.479704e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0005367919 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.0005367919 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.001720771 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 0.001720771 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.0007380858 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.0007380858 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 chanx_right_in[5]:18 1.709169e-05 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 chanx_right_in[5]:5 6.101071e-06 +20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 chanx_right_in[5]:20 0.0001985626 +21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 chanx_right_in[5]:19 1.709169e-05 +22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 chanx_right_in[5]:4 6.101071e-06 +23 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 chanx_right_in[5]:21 0.0001985626 +24 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_right_in[16]:8 4.09535e-05 +25 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_right_in[16]:9 4.09535e-05 +26 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 chanx_right_in[16]:14 5.044435e-06 +27 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 chanx_right_in[16]:16 0.0007562819 +28 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 chanx_right_in[16]:17 0.0007562819 +29 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chanx_right_in[16]:13 5.044435e-06 +30 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 optlc_net_164:35 0.0002726954 +31 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 optlc_net_164:36 0.0002726954 +32 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.4816e-05 +33 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000119575 +34 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.4816e-05 +35 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000119575 +36 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.785144e-05 +37 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001524765 +38 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.785144e-05 +39 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001524765 + +*RES +0 mux_left_track_3\/mux_l3_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_3\/BUFT_P_132:A 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.008140625 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.007205358 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.003625 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001634615 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.00341 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.00341 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.002087583 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 0.0045 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.02874777 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.01568973 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.002013393 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002297297 + +*END + +*D_NET mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004895815 //LENGTH 2.865 LUMPCC 0.0003394142 DR + +*CONN +*I mux_bottom_track_15\/mux_l1_in_0_:X O *L 0 *C 51.805 28.900 +*I mux_bottom_track_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 54.380 28.900 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 54.343 28.900 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 51.843 28.900 + +*CAP +0 mux_bottom_track_15\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_15\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.408368e-05 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.408368e-05 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_right_in[12]:19 0.0001045976 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_right_in[12]:20 0.0001045976 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_2_sram[1]:3 6.510952e-05 +7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_2_sram[1]:4 6.510952e-05 + +*RES +0 mux_bottom_track_15\/mux_l1_in_0_:X mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_15\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002232143 + +*END + +*D_NET mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006566967 //LENGTH 3.620 LUMPCC 0.0001940329 DR + +*CONN +*I mux_bottom_track_19\/mux_l1_in_1_:X O *L 0 *C 56.755 28.900 +*I mux_bottom_track_19\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.330 26.180 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 57.330 26.180 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 57.040 26.180 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 57.040 26.225 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 57.040 28.855 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 57.040 28.900 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 56.755 28.900 + +*CAP +0 mux_bottom_track_19\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_19\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.028321e-05 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.458184e-05 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001176834 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001176834 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.996239e-05 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.046949e-05 +8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_165:21 3.357699e-05 +9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_165:19 4.405194e-07 +10 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_165:22 3.357699e-05 +11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_165:20 4.405194e-07 +12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.072241e-05 +13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.276544e-06 +14 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.072241e-05 +15 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.276544e-06 + +*RES +0 mux_bottom_track_19\/mux_l1_in_1_:X mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_19\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001576087 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0] 0.004069381 //LENGTH 33.800 LUMPCC 0.0006221921 DR + +*CONN +*I mux_bottom_track_23\/mux_l2_in_0_:X O *L 0 *C 85.735 36.380 +*I mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 82.940 6.665 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 82.940 6.665 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 82.800 7.140 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 82.800 7.185 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 82.800 15.980 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 84.180 15.980 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 84.180 36.335 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 84.225 36.380 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 85.698 36.380 + +*CAP +0 mux_bottom_track_23\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.871971e-05 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 8.105325e-05 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005014115 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000574182 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001062866 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0009900954 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 7.843065e-05 +9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 7.843065e-05 +10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 8.592099e-05 +11 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 6.65079e-06 +12 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 8.592099e-05 +13 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 6.65079e-06 +14 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size3_5_sram[1]:9 4.851877e-05 +15 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size3_5_sram[1]:10 7.359726e-05 +16 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size3_5_sram[1]:5 4.851877e-05 +17 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size3_5_sram[1]:9 7.359726e-05 +18 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.212125e-05 +19 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.212125e-05 +20 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.428702e-05 +21 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.428702e-05 + +*RES +0 mux_bottom_track_23\/mux_l2_in_0_:X mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001314732 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01817411 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004241072 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.007852678 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001232143 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00223547 //LENGTH 16.050 LUMPCC 0.0008601819 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_1_:X O *L 0 *C 18.225 38.760 +*I mux_bottom_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 26.395 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 26.358 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 18.445 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 18.400 31.665 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 18.400 38.715 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 18.400 38.760 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 18.225 38.760 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003129409 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003129409 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003227687 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003227687 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.302067e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 4.884807e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 bottom_left_grid_pin_41_[0]:22 6.992357e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 bottom_left_grid_pin_41_[0]:21 6.992357e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size7_1_sram[2]:3 0.0001903174 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size7_1_sram[2]:8 4.701833e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size7_1_sram[2]:8 0.0001903174 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size7_1_sram[2]:9 4.701833e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_1_sram[2]:7 2.583754e-06 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_1_sram[2]:6 2.583754e-06 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001202479 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001202479 + +*RES +0 mux_bottom_track_3\/mux_l2_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.007064733 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006294644 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 + +*END + +*D_NET optlc_net_167 0.006953093 //LENGTH 59.270 LUMPCC 0.0009421891 DR + +*CONN +*I optlc_159:HI O *L 0 *C 106.720 28.560 +*I mux_bottom_track_29\/mux_l2_in_0_:A0 I *L 0.001631 *C 107.470 11.900 +*I mux_bottom_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 104.710 31.620 +*I mux_right_track_32\/mux_l1_in_1_:A0 I *L 0.001631 *C 113.450 33.320 +*I mux_right_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 111.035 42.840 +*I mux_right_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 112.415 53.380 +*N optlc_net_167:6 *C 112.415 53.380 +*N optlc_net_167:7 *C 112.700 53.380 +*N optlc_net_167:8 *C 112.700 53.335 +*N optlc_net_167:9 *C 111.073 42.840 +*N optlc_net_167:10 *C 112.655 42.840 +*N optlc_net_167:11 *C 112.700 42.840 +*N optlc_net_167:12 *C 113.413 33.320 +*N optlc_net_167:13 *C 112.745 33.320 +*N optlc_net_167:14 *C 112.700 33.320 +*N optlc_net_167:15 *C 112.700 28.945 +*N optlc_net_167:16 *C 112.655 28.900 +*N optlc_net_167:17 *C 104.748 31.620 +*N optlc_net_167:18 *C 105.755 31.620 +*N optlc_net_167:19 *C 105.800 31.575 +*N optlc_net_167:20 *C 107.433 11.900 +*N optlc_net_167:21 *C 105.845 11.900 +*N optlc_net_167:22 *C 105.800 11.945 +*N optlc_net_167:23 *C 105.800 28.900 +*N optlc_net_167:24 *C 105.845 28.900 +*N optlc_net_167:25 *C 106.720 28.900 +*N optlc_net_167:26 *C 106.720 28.560 + +*CAP +0 optlc_159:HI 1e-06 +1 mux_bottom_track_29\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25\/mux_l2_in_1_:A0 1e-06 +3 mux_right_track_32\/mux_l1_in_1_:A0 1e-06 +4 mux_right_track_24\/mux_l2_in_1_:A0 1e-06 +5 mux_right_track_8\/mux_l2_in_1_:A0 1e-06 +6 optlc_net_167:6 5.016748e-05 +7 optlc_net_167:7 5.463427e-05 +8 optlc_net_167:8 0.0005381579 +9 optlc_net_167:9 0.0001301798 +10 optlc_net_167:10 0.0001301798 +11 optlc_net_167:11 0.001074561 +12 optlc_net_167:12 6.478019e-05 +13 optlc_net_167:13 6.478019e-05 +14 optlc_net_167:14 0.0007844219 +15 optlc_net_167:15 0.000249223 +16 optlc_net_167:16 0.0001781938 +17 optlc_net_167:17 7.976311e-05 +18 optlc_net_167:18 7.976311e-05 +19 optlc_net_167:19 0.0001610497 +20 optlc_net_167:20 0.0001142508 +21 optlc_net_167:21 0.0001142508 +22 optlc_net_167:22 0.0008132384 +23 optlc_net_167:23 0.001008679 +24 optlc_net_167:24 2.65014e-05 +25 optlc_net_167:25 0.0002321849 +26 optlc_net_167:26 5.594232e-05 +27 optlc_net_167:16 chanx_right_in[1]:10 0.0002285396 +28 optlc_net_167:24 chanx_right_in[1]:9 4.024678e-05 +29 optlc_net_167:25 chanx_right_in[1]:9 0.0002285396 +30 optlc_net_167:25 chanx_right_in[1]:10 4.024678e-05 +31 optlc_net_167:23 mux_tree_tapbuf_size2_1_sram[1]:7 5.876407e-05 +32 optlc_net_167:23 mux_tree_tapbuf_size2_1_sram[1]:8 6.741843e-05 +33 optlc_net_167:22 mux_tree_tapbuf_size2_1_sram[1]:4 5.876407e-05 +34 optlc_net_167:22 mux_tree_tapbuf_size2_1_sram[1]:7 6.741843e-05 +35 optlc_net_167:16 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.753356e-05 +36 optlc_net_167:15 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.119852e-07 +37 optlc_net_167:24 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.778012e-05 +38 optlc_net_167:14 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.119852e-07 +39 optlc_net_167:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.778012e-05 +40 optlc_net_167:25 mux_right_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.753356e-05 + +*RES +0 optlc_159:HI optlc_net_167:26 0.152 +1 optlc_net_167:16 optlc_net_167:15 0.0045 +2 optlc_net_167:15 optlc_net_167:14 0.00390625 +3 optlc_net_167:10 optlc_net_167:9 0.001412946 +4 optlc_net_167:11 optlc_net_167:10 0.0045 +5 optlc_net_167:11 optlc_net_167:8 0.009370537 +6 optlc_net_167:9 mux_right_track_24\/mux_l2_in_1_:A0 0.152 +7 optlc_net_167:24 optlc_net_167:23 0.0045 +8 optlc_net_167:23 optlc_net_167:22 0.01513839 +9 optlc_net_167:23 optlc_net_167:19 0.002388393 +10 optlc_net_167:7 optlc_net_167:6 0.0001548913 +11 optlc_net_167:8 optlc_net_167:7 0.0045 +12 optlc_net_167:6 mux_right_track_8\/mux_l2_in_1_:A0 0.152 +13 optlc_net_167:18 optlc_net_167:17 0.0008995536 +14 optlc_net_167:19 optlc_net_167:18 0.0045 +15 optlc_net_167:17 mux_bottom_track_25\/mux_l2_in_1_:A0 0.152 +16 optlc_net_167:21 optlc_net_167:20 0.001417411 +17 optlc_net_167:22 optlc_net_167:21 0.0045 +18 optlc_net_167:20 mux_bottom_track_29\/mux_l2_in_0_:A0 0.152 +19 optlc_net_167:13 optlc_net_167:12 0.0005959822 +20 optlc_net_167:14 optlc_net_167:13 0.0045 +21 optlc_net_167:14 optlc_net_167:11 0.0085 +22 optlc_net_167:12 mux_right_track_32\/mux_l1_in_1_:A0 0.152 +23 optlc_net_167:26 optlc_net_167:25 0.0003035715 +24 optlc_net_167:25 optlc_net_167:24 0.00078125 +25 optlc_net_167:25 optlc_net_167:16 0.005299107 + +*END + +*D_NET mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008009839 //LENGTH 7.210 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_27\/mux_l1_in_0_:X O *L 0 *C 88.495 10.200 +*I mux_bottom_track_27\/mux_l2_in_0_:A1 I *L 0.005458 *C 87.860 4.250 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 87.860 4.295 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 87.860 10.155 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 87.905 10.200 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 88.458 10.200 + +*CAP +0 mux_bottom_track_27\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_27\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003300298 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003300298 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.946215e-05 +5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.946215e-05 + +*RES +0 mux_bottom_track_27\/mux_l1_in_0_:X mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004933036 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005232143 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_27\/mux_l2_in_0_:A1 0.0045 + +*END + +*D_NET mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003762883 //LENGTH 27.445 LUMPCC 0.0004747237 DR + +*CONN +*I mux_bottom_track_31\/mux_l2_in_0_:X O *L 0 *C 85.735 14.620 +*I mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 67.290 6.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 67.290 6.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 67.290 7.480 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 85.055 7.480 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 85.100 7.525 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 85.100 14.575 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 85.145 14.620 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 85.698 14.620 + +*CAP +0 mux_bottom_track_31\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001099337 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.001147247 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001077686 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004105481 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004105481 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.509828e-05 +8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 6.509828e-05 +9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_out[18]:4 0.0001582342 +10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_out[18]:6 7.550896e-06 +11 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_out[18]:3 0.0001582342 +12 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_out[18]:5 7.550896e-06 +13 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_204:7 2.380594e-05 +14 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_204:5 4.1591e-05 +15 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_204:3 6.179814e-06 +16 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_204:6 2.380594e-05 +17 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 ropt_net_204:2 6.179814e-06 +18 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 ropt_net_204:4 4.1591e-05 + +*RES +0 mux_bottom_track_31\/mux_l2_in_0_:X mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004933036 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.006294643 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.01586161 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0007321429 + +*END + +*D_NET ropt_net_199 0.0009710197 //LENGTH 7.265 LUMPCC 0.0002350156 DR + +*CONN +*I FTB_3__2:X O *L 0 *C 7.820 44.200 +*I ropt_mt_inst_819:A I *L 0.001766 *C 3.220 42.160 +*N ropt_net_199:2 *C 3.220 42.160 +*N ropt_net_199:3 *C 3.220 42.205 +*N ropt_net_199:4 *C 3.220 44.155 +*N ropt_net_199:5 *C 3.265 44.200 +*N ropt_net_199:6 *C 7.783 44.200 + +*CAP +0 FTB_3__2:X 1e-06 +1 ropt_mt_inst_819:A 1e-06 +2 ropt_net_199:2 3.098719e-05 +3 ropt_net_199:3 4.882287e-05 +4 ropt_net_199:4 4.882287e-05 +5 ropt_net_199:5 0.0003026856 +6 ropt_net_199:6 0.0003026856 +7 ropt_net_199:4 chanx_left_in[3]:6 5.846145e-05 +8 ropt_net_199:3 chanx_left_in[3]:5 5.846145e-05 +9 ropt_net_199:6 ropt_net_212:2 5.433067e-06 +10 ropt_net_199:5 ropt_net_212:3 5.433067e-06 +11 ropt_net_199:4 ropt_net_212:4 5.361326e-05 +12 ropt_net_199:3 ropt_net_212:5 5.361326e-05 + +*RES +0 FTB_3__2:X ropt_net_199:6 0.152 +1 ropt_net_199:6 ropt_net_199:5 0.004033482 +2 ropt_net_199:5 ropt_net_199:4 0.0045 +3 ropt_net_199:4 ropt_net_199:3 0.001741072 +4 ropt_net_199:2 ropt_mt_inst_819:A 0.152 +5 ropt_net_199:3 ropt_net_199:2 0.0045 + +*END + +*D_NET ropt_net_205 0.0009200267 //LENGTH 6.970 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 7.095 86.360 +*I ropt_mt_inst_823:A I *L 0.001767 *C 3.220 88.400 +*N ropt_net_205:2 *C 3.220 88.400 +*N ropt_net_205:3 *C 3.220 88.355 +*N ropt_net_205:4 *C 3.220 87.765 +*N ropt_net_205:5 *C 3.265 87.720 +*N ropt_net_205:6 *C 6.855 87.720 +*N ropt_net_205:7 *C 6.900 87.675 +*N ropt_net_205:8 *C 6.900 86.405 +*N ropt_net_205:9 *C 6.900 86.360 +*N ropt_net_205:10 *C 7.095 86.360 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 ropt_mt_inst_823:A 1e-06 +2 ropt_net_205:2 3.288603e-05 +3 ropt_net_205:3 5.502512e-05 +4 ropt_net_205:4 5.502512e-05 +5 ropt_net_205:5 0.0002427005 +6 ropt_net_205:6 0.0002427005 +7 ropt_net_205:7 8.608664e-05 +8 ropt_net_205:8 8.608664e-05 +9 ropt_net_205:9 5.79128e-05 +10 ropt_net_205:10 5.960352e-05 + +*RES +0 ropt_mt_inst_796:X ropt_net_205:10 0.152 +1 ropt_net_205:10 ropt_net_205:9 0.0001059783 +2 ropt_net_205:9 ropt_net_205:8 0.0045 +3 ropt_net_205:8 ropt_net_205:7 0.001133929 +4 ropt_net_205:6 ropt_net_205:5 0.003205357 +5 ropt_net_205:7 ropt_net_205:6 0.0045 +6 ropt_net_205:5 ropt_net_205:4 0.0045 +7 ropt_net_205:4 ropt_net_205:3 0.0005267857 +8 ropt_net_205:2 ropt_mt_inst_823:A 0.152 +9 ropt_net_205:3 ropt_net_205:2 0.0045 + +*END + +*D_NET chanx_right_out[15] 0.0007503788 //LENGTH 6.390 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_806:X O *L 0 *C 136.160 69.360 +*P chanx_right_out[15] O *L 0.7423 *C 140.375 68.000 +*N chanx_right_out[15]:2 *C 137.088 68.000 +*N chanx_right_out[15]:3 *C 137.080 68.058 +*N chanx_right_out[15]:4 *C 137.080 69.315 +*N chanx_right_out[15]:5 *C 137.035 69.360 +*N chanx_right_out[15]:6 *C 136.198 69.360 + +*CAP +0 ropt_mt_inst_806:X 1e-06 +1 chanx_right_out[15] 0.0002149833 +2 chanx_right_out[15]:2 0.0002149833 +3 chanx_right_out[15]:3 9.097719e-05 +4 chanx_right_out[15]:4 9.097719e-05 +5 chanx_right_out[15]:5 6.872898e-05 +6 chanx_right_out[15]:6 6.872898e-05 + +*RES +0 ropt_mt_inst_806:X chanx_right_out[15]:6 0.152 +1 chanx_right_out[15]:3 chanx_right_out[15]:2 0.00341 +2 chanx_right_out[15]:2 chanx_right_out[15] 0.0005150416 +3 chanx_right_out[15]:5 chanx_right_out[15]:4 0.0045 +4 chanx_right_out[15]:4 chanx_right_out[15]:3 0.001122768 +5 chanx_right_out[15]:6 chanx_right_out[15]:5 0.0007477679 + +*END + +*D_NET chanx_left_out[7] 0.0007229217 //LENGTH 5.765 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 4.140 49.640 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 47.600 +*N chanx_left_out[7]:2 *C 2.292 47.600 +*N chanx_left_out[7]:3 *C 2.300 47.657 +*N chanx_left_out[7]:4 *C 2.300 49.595 +*N chanx_left_out[7]:5 *C 2.345 49.640 +*N chanx_left_out[7]:6 *C 4.103 49.640 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 chanx_left_out[7] 9.53886e-05 +2 chanx_left_out[7]:2 9.53886e-05 +3 chanx_left_out[7]:3 0.0001325799 +4 chanx_left_out[7]:4 0.0001325799 +5 chanx_left_out[7]:5 0.0001329923 +6 chanx_left_out[7]:6 0.0001329923 + +*RES +0 ropt_mt_inst_821:X chanx_left_out[7]:6 0.152 +1 chanx_left_out[7]:6 chanx_left_out[7]:5 0.001569197 +2 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +3 chanx_left_out[7]:4 chanx_left_out[7]:3 0.001729911 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 0.0001664583 + +*END + +*D_NET chanx_left_out[13] 0.0006274045 //LENGTH 5.425 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 4.140 88.740 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 87.040 +*N chanx_left_out[13]:2 *C 3.673 87.040 +*N chanx_left_out[13]:3 *C 3.680 87.098 +*N chanx_left_out[13]:4 *C 3.680 88.695 +*N chanx_left_out[13]:5 *C 3.725 88.740 +*N chanx_left_out[13]:6 *C 4.103 88.740 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 chanx_left_out[13] 0.0001612576 +2 chanx_left_out[13]:2 0.0001612576 +3 chanx_left_out[13]:3 0.0001086154 +4 chanx_left_out[13]:4 0.0001086154 +5 chanx_left_out[13]:5 4.332934e-05 +6 chanx_left_out[13]:6 4.332934e-05 + +*RES +0 ropt_mt_inst_823:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:6 chanx_left_out[13]:5 0.0003370536 +2 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.001426339 +4 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +5 chanx_left_out[13]:2 chanx_left_out[13] 0.0003826583 + +*END + +*D_NET chanx_left_out[3] 0.001167787 //LENGTH 10.095 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_828:X O *L 0 *C 7.095 52.360 +*P chanx_left_out[3] O *L 0.7423 *C 1.298 48.960 +*N chanx_left_out[3]:2 *C 1.380 48.960 +*N chanx_left_out[3]:3 *C 1.380 49.018 +*N chanx_left_out[3]:4 *C 1.380 52.315 +*N chanx_left_out[3]:5 *C 1.425 52.360 +*N chanx_left_out[3]:6 *C 7.058 52.360 + +*CAP +0 ropt_mt_inst_828:X 1e-06 +1 chanx_left_out[3] 3.191078e-05 +2 chanx_left_out[3]:2 3.191078e-05 +3 chanx_left_out[3]:3 0.0001763257 +4 chanx_left_out[3]:4 0.0001763257 +5 chanx_left_out[3]:5 0.000375157 +6 chanx_left_out[3]:6 0.000375157 + +*RES +0 ropt_mt_inst_828:X chanx_left_out[3]:6 0.152 +1 chanx_left_out[3]:6 chanx_left_out[3]:5 0.005029018 +2 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +3 chanx_left_out[3]:4 chanx_left_out[3]:3 0.002944197 +4 chanx_left_out[3]:3 chanx_left_out[3]:2 0.00341 +5 chanx_left_out[3]:2 chanx_left_out[3] 2.35e-05 + +*END + +*D_NET ropt_net_188 0.002490805 //LENGTH 25.510 LUMPCC 0 DR + +*CONN +*I BUFT_RR_84:X O *L 0 *C 18.400 83.300 +*I ropt_mt_inst_808:A I *L 0.001766 *C 7.820 93.840 +*N ropt_net_188:2 *C 7.858 93.840 +*N ropt_net_188:3 *C 8.695 93.840 +*N ropt_net_188:4 *C 8.740 93.795 +*N ropt_net_188:5 *C 8.740 88.458 +*N ropt_net_188:6 *C 8.748 88.400 +*N ropt_net_188:7 *C 19.773 88.400 +*N ropt_net_188:8 *C 19.780 88.343 +*N ropt_net_188:9 *C 19.780 83.345 +*N ropt_net_188:10 *C 19.735 83.300 +*N ropt_net_188:11 *C 18.438 83.300 + +*CAP +0 BUFT_RR_84:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_188:2 8.243982e-05 +3 ropt_net_188:3 8.243982e-05 +4 ropt_net_188:4 0.0003032463 +5 ropt_net_188:5 0.0003032463 +6 ropt_net_188:6 0.0005101551 +7 ropt_net_188:7 0.0005101551 +8 ropt_net_188:8 0.000250222 +9 ropt_net_188:9 0.000250222 +10 ropt_net_188:10 9.833911e-05 +11 ropt_net_188:11 9.833911e-05 + +*RES +0 BUFT_RR_84:X ropt_net_188:11 0.152 +1 ropt_net_188:11 ropt_net_188:10 0.001158482 +2 ropt_net_188:10 ropt_net_188:9 0.0045 +3 ropt_net_188:9 ropt_net_188:8 0.004462054 +4 ropt_net_188:8 ropt_net_188:7 0.00341 +5 ropt_net_188:7 ropt_net_188:6 0.00172725 +6 ropt_net_188:5 ropt_net_188:4 0.004765625 +7 ropt_net_188:6 ropt_net_188:5 0.00341 +8 ropt_net_188:3 ropt_net_188:2 0.0007477679 +9 ropt_net_188:4 ropt_net_188:3 0.0045 +10 ropt_net_188:2 ropt_mt_inst_808:A 0.152 + +*END + +*D_NET chanx_left_out[5] 0.001499602 //LENGTH 14.420 LUMPCC 0 DR + +*CONN +*I BUFT_P_138:X O *L 0 *C 4.865 60.860 +*P chanx_left_out[5] O *L 0.7423 *C 1.298 70.720 +*N chanx_left_out[5]:2 *C 1.380 70.720 +*N chanx_left_out[5]:3 *C 1.380 70.720 +*N chanx_left_out[5]:4 *C 2.300 70.720 +*N chanx_left_out[5]:5 *C 2.300 60.905 +*N chanx_left_out[5]:6 *C 2.345 60.860 +*N chanx_left_out[5]:7 *C 4.828 60.860 + +*CAP +0 BUFT_P_138:X 1e-06 +1 chanx_left_out[5] 2.860723e-05 +2 chanx_left_out[5]:2 2.860723e-05 +3 chanx_left_out[5]:3 8.830672e-05 +4 chanx_left_out[5]:4 0.0005491918 +5 chanx_left_out[5]:5 0.0004945145 +6 chanx_left_out[5]:6 0.0001546873 +7 chanx_left_out[5]:7 0.0001546873 + +*RES +0 BUFT_P_138:X chanx_left_out[5]:7 0.152 +1 chanx_left_out[5]:7 chanx_left_out[5]:6 0.002216518 +2 chanx_left_out[5]:6 chanx_left_out[5]:5 0.0045 +3 chanx_left_out[5]:5 chanx_left_out[5]:4 0.008763393 +4 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +5 chanx_left_out[5]:2 chanx_left_out[5] 2.35e-05 +6 chanx_left_out[5]:4 chanx_left_out[5]:3 0.0008214285 + +*END + +*D_NET chanx_left_in[5] 0.02599334 //LENGTH 196.495 LUMPCC 0.006440252 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 46.240 +*I mux_bottom_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 30.075 42.840 +*I mux_right_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 100.740 58.140 +*I ropt_mt_inst_807:A I *L 0.001767 *C 134.780 85.680 +*N chanx_left_in[5]:4 *C 134.817 85.680 +*N chanx_left_in[5]:5 *C 135.700 85.680 +*N chanx_left_in[5]:6 *C 135.700 85.000 +*N chanx_left_in[5]:7 *C 137.035 85.000 +*N chanx_left_in[5]:8 *C 137.080 84.955 +*N chanx_left_in[5]:9 *C 137.080 77.225 +*N chanx_left_in[5]:10 *C 137.035 77.180 +*N chanx_left_in[5]:11 *C 130.225 77.180 +*N chanx_left_in[5]:12 *C 130.180 77.135 +*N chanx_left_in[5]:13 *C 130.180 75.525 +*N chanx_left_in[5]:14 *C 130.135 75.480 +*N chanx_left_in[5]:15 *C 128.880 75.480 +*N chanx_left_in[5]:16 *C 128.810 75.470 +*N chanx_left_in[5]:17 *C 128.800 74.845 +*N chanx_left_in[5]:18 *C 128.755 74.800 +*N chanx_left_in[5]:19 *C 126.085 74.800 +*N chanx_left_in[5]:20 *C 126.040 74.755 +*N chanx_left_in[5]:21 *C 126.040 71.785 +*N chanx_left_in[5]:22 *C 125.995 71.740 +*N chanx_left_in[5]:23 *C 101.245 71.740 +*N chanx_left_in[5]:24 *C 101.200 71.695 +*N chanx_left_in[5]:25 *C 100.740 58.140 +*N chanx_left_in[5]:26 *C 100.740 58.480 +*N chanx_left_in[5]:27 *C 101.155 58.480 +*N chanx_left_in[5]:28 *C 101.200 58.525 +*N chanx_left_in[5]:29 *C 101.200 59.160 +*N chanx_left_in[5]:30 *C 101.155 59.160 +*N chanx_left_in[5]:31 *C 92.505 59.160 +*N chanx_left_in[5]:32 *C 92.460 59.205 +*N chanx_left_in[5]:33 *C 92.460 60.463 +*N chanx_left_in[5]:34 *C 92.453 60.520 +*N chanx_left_in[5]:35 *C 74.215 60.520 +*N chanx_left_in[5]:36 *C 24.388 60.520 +*N chanx_left_in[5]:37 *C 24.380 60.463 +*N chanx_left_in[5]:38 *C 30.038 42.840 +*N chanx_left_in[5]:39 *C 24.425 42.840 +*N chanx_left_in[5]:40 *C 24.380 42.885 +*N chanx_left_in[5]:41 *C 24.380 46.240 +*N chanx_left_in[5]:42 *C 24.373 46.240 + +*CAP +0 chanx_left_in[5] 0.0009784582 +1 mux_bottom_track_5\/mux_l1_in_2_:A0 1e-06 +2 mux_right_track_4\/mux_l1_in_2_:A1 1e-06 +3 ropt_mt_inst_807:A 1e-06 +4 chanx_left_in[5]:4 7.172222e-05 +5 chanx_left_in[5]:5 0.0001139856 +6 chanx_left_in[5]:6 0.0001594129 +7 chanx_left_in[5]:7 0.0001171495 +8 chanx_left_in[5]:8 0.0004319488 +9 chanx_left_in[5]:9 0.0004319488 +10 chanx_left_in[5]:10 0.0003794065 +11 chanx_left_in[5]:11 0.0003794065 +12 chanx_left_in[5]:12 0.0001031524 +13 chanx_left_in[5]:13 0.0001031524 +14 chanx_left_in[5]:14 0.0001318378 +15 chanx_left_in[5]:15 0.0001318378 +16 chanx_left_in[5]:16 6.266778e-05 +17 chanx_left_in[5]:17 6.266778e-05 +18 chanx_left_in[5]:18 0.0002233461 +19 chanx_left_in[5]:19 0.0002233461 +20 chanx_left_in[5]:20 0.0001669465 +21 chanx_left_in[5]:21 0.0001669465 +22 chanx_left_in[5]:22 0.00107669 +23 chanx_left_in[5]:23 0.00107669 +24 chanx_left_in[5]:24 0.0006264315 +25 chanx_left_in[5]:25 5.294414e-05 +26 chanx_left_in[5]:26 7.033713e-05 +27 chanx_left_in[5]:27 4.350029e-05 +28 chanx_left_in[5]:28 4.299874e-05 +29 chanx_left_in[5]:29 0.0007047841 +30 chanx_left_in[5]:30 0.0005738171 +31 chanx_left_in[5]:31 0.0005738171 +32 chanx_left_in[5]:32 0.0001093932 +33 chanx_left_in[5]:33 0.0001093932 +34 chanx_left_in[5]:34 0.0007468208 +35 chanx_left_in[5]:35 0.003330217 +36 chanx_left_in[5]:36 0.002583395 +37 chanx_left_in[5]:37 0.0006428618 +38 chanx_left_in[5]:38 0.0004112372 +39 chanx_left_in[5]:39 0.0004112372 +40 chanx_left_in[5]:40 0.0001314895 +41 chanx_left_in[5]:41 0.0008142305 +42 chanx_left_in[5]:42 0.0009784582 +43 chanx_left_in[5] chanx_right_in[14]:8 0.000322188 +44 chanx_left_in[5]:42 chanx_right_in[14]:9 0.000322188 +45 chanx_left_in[5]:36 chanx_right_in[17]:13 0.0001013475 +46 chanx_left_in[5]:36 chanx_right_in[17]:20 0.0002648539 +47 chanx_left_in[5]:34 chanx_right_in[17]:21 0.0001344885 +48 chanx_left_in[5]:34 chanx_right_in[17]:30 0.000605053 +49 chanx_left_in[5]:35 chanx_right_in[17]:14 0.0001013475 +50 chanx_left_in[5]:35 chanx_right_in[17]:20 0.0001344885 +51 chanx_left_in[5]:35 chanx_right_in[17]:21 0.0002648539 +52 chanx_left_in[5]:35 chanx_right_in[17]:29 0.000605053 +53 chanx_left_in[5] chanx_left_in[4] 1.327791e-05 +54 chanx_left_in[5]:23 chanx_left_in[4]:20 0.0001476162 +55 chanx_left_in[5]:23 chanx_left_in[4]:21 0.0002492352 +56 chanx_left_in[5]:22 chanx_left_in[4]:19 0.0001476162 +57 chanx_left_in[5]:22 chanx_left_in[4]:20 0.0002492352 +58 chanx_left_in[5]:21 chanx_left_in[4]:17 4.999944e-06 +59 chanx_left_in[5]:20 chanx_left_in[4]:16 4.999944e-06 +60 chanx_left_in[5]:42 chanx_left_in[4]:38 1.327791e-05 +61 chanx_left_in[5]:24 chanx_left_in[14]:12 1.085673e-05 +62 chanx_left_in[5]:36 chanx_left_in[14]:32 0.0003566776 +63 chanx_left_in[5]:31 chanx_left_in[14]:5 1.362362e-05 +64 chanx_left_in[5]:30 chanx_left_in[14]:4 1.362362e-05 +65 chanx_left_in[5]:29 chanx_left_in[14]:13 1.085673e-05 +66 chanx_left_in[5]:29 chanx_left_in[14]:15 2.510613e-06 +67 chanx_left_in[5]:28 chanx_left_in[14]:16 2.510613e-06 +68 chanx_left_in[5]:35 chanx_left_in[14]:31 0.0003566776 +69 chanx_left_in[5]:9 chanx_left_in[17]:7 1.656074e-06 +70 chanx_left_in[5]:8 chanx_left_in[17]:6 1.656074e-06 +71 chanx_left_in[5]:36 chanx_left_in[17]:32 0.0001757803 +72 chanx_left_in[5]:36 chanx_left_in[17]:31 0.0001090014 +73 chanx_left_in[5]:34 chanx_left_in[17]:30 0.0001149667 +74 chanx_left_in[5]:35 chanx_left_in[17]:30 0.0001090014 +75 chanx_left_in[5]:35 chanx_left_in[17]:31 0.000290747 +76 chanx_left_in[5] mux_tree_tapbuf_size7_3_sram[1]:9 9.296468e-05 +77 chanx_left_in[5] mux_tree_tapbuf_size7_3_sram[1]:14 0.0002177537 +78 chanx_left_in[5]:37 mux_tree_tapbuf_size7_3_sram[1]:16 1.64157e-05 +79 chanx_left_in[5]:37 mux_tree_tapbuf_size7_3_sram[1]:17 2.848607e-05 +80 chanx_left_in[5]:39 mux_tree_tapbuf_size7_3_sram[1]:4 5.556792e-06 +81 chanx_left_in[5]:40 mux_tree_tapbuf_size7_3_sram[1]:6 8.696884e-05 +82 chanx_left_in[5]:38 mux_tree_tapbuf_size7_3_sram[1]:5 5.556792e-06 +83 chanx_left_in[5]:41 mux_tree_tapbuf_size7_3_sram[1]:16 0.0001154549 +84 chanx_left_in[5]:41 mux_tree_tapbuf_size7_3_sram[1]:6 1.64157e-05 +85 chanx_left_in[5]:42 mux_tree_tapbuf_size7_3_sram[1]:15 0.0002177537 +86 chanx_left_in[5]:42 mux_tree_tapbuf_size7_3_sram[1]:14 9.296468e-05 +87 chanx_left_in[5]:37 mux_tree_tapbuf_size7_3_sram[2]:5 6.955303e-05 +88 chanx_left_in[5]:37 mux_tree_tapbuf_size7_3_sram[2]:9 6.69603e-05 +89 chanx_left_in[5]:40 mux_tree_tapbuf_size7_3_sram[2]:8 7.334616e-06 +90 chanx_left_in[5]:41 mux_tree_tapbuf_size7_3_sram[2]:8 6.69603e-05 +91 chanx_left_in[5]:41 mux_tree_tapbuf_size7_3_sram[2]:10 6.955303e-05 +92 chanx_left_in[5]:41 mux_tree_tapbuf_size7_3_sram[2]:9 7.334616e-06 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:42 0.003625658 +1 chanx_left_in[5]:23 chanx_left_in[5]:22 0.02209822 +2 chanx_left_in[5]:24 chanx_left_in[5]:23 0.0045 +3 chanx_left_in[5]:22 chanx_left_in[5]:21 0.0045 +4 chanx_left_in[5]:21 chanx_left_in[5]:20 0.002651786 +5 chanx_left_in[5]:19 chanx_left_in[5]:18 0.002383929 +6 chanx_left_in[5]:20 chanx_left_in[5]:19 0.0045 +7 chanx_left_in[5]:18 chanx_left_in[5]:17 0.0045 +8 chanx_left_in[5]:17 chanx_left_in[5]:16 0.0005580357 +9 chanx_left_in[5]:15 chanx_left_in[5]:14 0.001120536 +10 chanx_left_in[5]:16 chanx_left_in[5]:15 0.0045 +11 chanx_left_in[5]:14 chanx_left_in[5]:13 0.0045 +12 chanx_left_in[5]:13 chanx_left_in[5]:12 0.0014375 +13 chanx_left_in[5]:11 chanx_left_in[5]:10 0.006080357 +14 chanx_left_in[5]:12 chanx_left_in[5]:11 0.0045 +15 chanx_left_in[5]:10 chanx_left_in[5]:9 0.0045 +16 chanx_left_in[5]:9 chanx_left_in[5]:8 0.006901786 +17 chanx_left_in[5]:7 chanx_left_in[5]:6 0.001191964 +18 chanx_left_in[5]:8 chanx_left_in[5]:7 0.0045 +19 chanx_left_in[5]:4 ropt_mt_inst_807:A 0.152 +20 chanx_left_in[5]:37 chanx_left_in[5]:36 0.00341 +21 chanx_left_in[5]:36 chanx_left_in[5]:35 0.007806308 +22 chanx_left_in[5]:33 chanx_left_in[5]:32 0.001122768 +23 chanx_left_in[5]:34 chanx_left_in[5]:33 0.00341 +24 chanx_left_in[5]:31 chanx_left_in[5]:30 0.007723215 +25 chanx_left_in[5]:32 chanx_left_in[5]:31 0.0045 +26 chanx_left_in[5]:30 chanx_left_in[5]:29 0.0045 +27 chanx_left_in[5]:29 chanx_left_in[5]:28 0.0005669642 +28 chanx_left_in[5]:29 chanx_left_in[5]:24 0.01119196 +29 chanx_left_in[5]:39 chanx_left_in[5]:38 0.005011161 +30 chanx_left_in[5]:40 chanx_left_in[5]:39 0.0045 +31 chanx_left_in[5]:38 mux_bottom_track_5\/mux_l1_in_2_:A0 0.152 +32 chanx_left_in[5]:27 chanx_left_in[5]:26 0.0003705357 +33 chanx_left_in[5]:28 chanx_left_in[5]:27 0.0045 +34 chanx_left_in[5]:25 mux_right_track_4\/mux_l1_in_2_:A1 0.152 +35 chanx_left_in[5]:41 chanx_left_in[5]:40 0.002995536 +36 chanx_left_in[5]:41 chanx_left_in[5]:37 0.01269866 +37 chanx_left_in[5]:42 chanx_left_in[5]:41 0.00341 +38 chanx_left_in[5]:26 chanx_left_in[5]:25 0.0003035715 +39 chanx_left_in[5]:5 chanx_left_in[5]:4 0.0007879463 +40 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0006071429 +41 chanx_left_in[5]:35 chanx_left_in[5]:34 0.002857208 + +*END + +*D_NET mux_tree_tapbuf_size5_4_sram[1] 0.002545131 //LENGTH 19.440 LUMPCC 0.000104191 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 78.505 44.880 +*I mux_left_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 75.080 42.160 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 74.695 53.380 +*I mux_left_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 75.080 47.310 +*N mux_tree_tapbuf_size5_4_sram[1]:4 *C 75.080 47.310 +*N mux_tree_tapbuf_size5_4_sram[1]:5 *C 74.695 53.380 +*N mux_tree_tapbuf_size5_4_sram[1]:6 *C 74.980 53.380 +*N mux_tree_tapbuf_size5_4_sram[1]:7 *C 74.980 53.335 +*N mux_tree_tapbuf_size5_4_sram[1]:8 *C 74.980 46.965 +*N mux_tree_tapbuf_size5_4_sram[1]:9 *C 75.080 46.920 +*N mux_tree_tapbuf_size5_4_sram[1]:10 *C 77.235 46.920 +*N mux_tree_tapbuf_size5_4_sram[1]:11 *C 77.280 46.875 +*N mux_tree_tapbuf_size5_4_sram[1]:12 *C 75.118 42.160 +*N mux_tree_tapbuf_size5_4_sram[1]:13 *C 77.235 42.160 +*N mux_tree_tapbuf_size5_4_sram[1]:14 *C 77.280 42.205 +*N mux_tree_tapbuf_size5_4_sram[1]:15 *C 77.280 44.880 +*N mux_tree_tapbuf_size5_4_sram[1]:16 *C 77.325 44.880 +*N mux_tree_tapbuf_size5_4_sram[1]:17 *C 78.468 44.880 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_3\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_4_sram[1]:4 6.376574e-05 +5 mux_tree_tapbuf_size5_4_sram[1]:5 4.972976e-05 +6 mux_tree_tapbuf_size5_4_sram[1]:6 5.421001e-05 +7 mux_tree_tapbuf_size5_4_sram[1]:7 0.0003830369 +8 mux_tree_tapbuf_size5_4_sram[1]:8 0.0003830369 +9 mux_tree_tapbuf_size5_4_sram[1]:9 0.000223778 +10 mux_tree_tapbuf_size5_4_sram[1]:10 0.0001894234 +11 mux_tree_tapbuf_size5_4_sram[1]:11 0.0001343499 +12 mux_tree_tapbuf_size5_4_sram[1]:12 0.0001412539 +13 mux_tree_tapbuf_size5_4_sram[1]:13 0.0001412539 +14 mux_tree_tapbuf_size5_4_sram[1]:14 0.000159873 +15 mux_tree_tapbuf_size5_4_sram[1]:15 0.0003290394 +16 mux_tree_tapbuf_size5_4_sram[1]:16 9.209487e-05 +17 mux_tree_tapbuf_size5_4_sram[1]:17 9.209487e-05 +18 mux_tree_tapbuf_size5_4_sram[1]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.205076e-05 +19 mux_tree_tapbuf_size5_4_sram[1]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.472712e-08 +20 mux_tree_tapbuf_size5_4_sram[1]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.205076e-05 +21 mux_tree_tapbuf_size5_4_sram[1]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.472712e-08 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_4_sram[1]:17 0.152 +1 mux_tree_tapbuf_size5_4_sram[1]:10 mux_tree_tapbuf_size5_4_sram[1]:9 0.001924107 +2 mux_tree_tapbuf_size5_4_sram[1]:11 mux_tree_tapbuf_size5_4_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size5_4_sram[1]:9 mux_tree_tapbuf_size5_4_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size5_4_sram[1]:9 mux_tree_tapbuf_size5_4_sram[1]:4 0.0003482143 +5 mux_tree_tapbuf_size5_4_sram[1]:8 mux_tree_tapbuf_size5_4_sram[1]:7 0.0056875 +6 mux_tree_tapbuf_size5_4_sram[1]:6 mux_tree_tapbuf_size5_4_sram[1]:5 0.0001548913 +7 mux_tree_tapbuf_size5_4_sram[1]:7 mux_tree_tapbuf_size5_4_sram[1]:6 0.0045 +8 mux_tree_tapbuf_size5_4_sram[1]:5 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size5_4_sram[1]:13 mux_tree_tapbuf_size5_4_sram[1]:12 0.001890625 +10 mux_tree_tapbuf_size5_4_sram[1]:14 mux_tree_tapbuf_size5_4_sram[1]:13 0.0045 +11 mux_tree_tapbuf_size5_4_sram[1]:12 mux_left_track_3\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size5_4_sram[1]:4 mux_left_track_3\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size5_4_sram[1]:16 mux_tree_tapbuf_size5_4_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size5_4_sram[1]:15 mux_tree_tapbuf_size5_4_sram[1]:14 0.002388393 +15 mux_tree_tapbuf_size5_4_sram[1]:15 mux_tree_tapbuf_size5_4_sram[1]:11 0.00178125 +16 mux_tree_tapbuf_size5_4_sram[1]:17 mux_tree_tapbuf_size5_4_sram[1]:16 0.001020089 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.001717443 //LENGTH 15.120 LUMPCC 0.0001225339 DR + +*CONN +*I mem_right_track_0\/FTB_1__26:X O *L 0 *C 87.625 87.720 +*I mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 81.135 80.580 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 81.135 80.580 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 80.960 80.580 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 80.960 80.625 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 80.960 82.915 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 81.005 82.960 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 87.355 82.960 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 *C 87.400 83.005 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 *C 87.400 87.675 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:10 *C 87.400 87.720 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:11 *C 87.625 87.720 + +*CAP +0 mem_right_track_0\/FTB_1__26:X 1e-06 +1 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 4.493207e-05 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 4.885422e-05 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.000132224 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.000132224 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0003474866 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.0003474866 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 0.0002170373 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 0.0002170373 +10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:10 5.5294e-05 +11 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:11 5.033302e-05 +12 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size6_0_sram[0]:10 6.126694e-05 +13 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size6_0_sram[0]:14 6.126694e-05 + +*RES +0 mem_right_track_0\/FTB_1__26:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:11 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:10 0.0001222826 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 0.004169643 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.005669643 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.0045 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002044643 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 9.51087e-05 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_right_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_2_ccff_tail[0] 0.00203873 //LENGTH 14.910 LUMPCC 0.0003728071 DR + +*CONN +*I mem_bottom_track_5\/FTB_22__47:X O *L 0 *C 33.805 55.760 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 26.395 58.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 *C 26.433 58.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 *C 30.820 58.820 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 *C 30.820 58.480 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 *C 35.375 58.480 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 *C 35.420 58.435 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 *C 35.420 55.805 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:8 *C 35.375 55.760 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:9 *C 33.843 55.760 + +*CAP +0 mem_bottom_track_5\/FTB_22__47:X 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.0003082756 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0003332774 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.00030213 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0002771282 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.0001120521 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.0001120521 +8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:8 0.0001095038 +9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:9 0.0001095038 +10 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 chanx_left_in[16]:38 7.84865e-05 +11 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 chanx_left_in[16]:35 7.901236e-06 +12 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 chanx_left_in[16]:37 7.84865e-05 +13 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 chanx_left_in[16]:36 7.901236e-06 +14 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_3_sram[0]:38 5.917393e-06 +15 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_3_sram[0]:40 1.67579e-05 +16 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mux_tree_tapbuf_size7_3_sram[0]:37 7.573973e-05 +17 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_3_sram[0]:38 7.734052e-05 +18 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_3_sram[0]:37 5.917393e-06 +19 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_3_sram[0]:39 1.835869e-05 + +*RES +0 mem_bottom_track_5\/FTB_22__47:X mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:8 0.001368304 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.0045 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.002348214 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.004066965 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0045 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.003917411 +8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0003035715 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.008151212 //LENGTH 49.610 LUMPCC 0.003824666 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_0_:X O *L 0 *C 53.535 53.720 +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.900 55.575 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.938 55.475 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 12.835 55.420 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 12.880 55.375 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 12.880 52.418 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 12.888 52.360 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 48.293 52.360 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 48.300 52.418 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 48.300 53.675 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 48.345 53.720 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 53.498 53.720 + +*CAP +0 mux_left_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001920411 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001920411 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001857726 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001857726 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001291195 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001291195 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 9.47794e-05 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 9.47794e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0003984854 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0003984854 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_right_in[2]:22 0.0002864564 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_right_in[2]:21 0.0002864564 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[16]:39 0.001251908 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[16]:40 0.001251908 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 prog_clk[0]:409 2.258611e-07 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 prog_clk[0]:410 2.258611e-07 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:411 0.0002038476 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:415 8.393591e-05 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:446 3.439519e-05 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:452 5.156332e-05 +22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:415 0.0002038476 +23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:416 8.393591e-05 +24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:451 5.156332e-05 +25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:452 3.439519e-05 + +*RES +0 mux_left_track_9\/mux_l3_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.004600447 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.001122768 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.005546783 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002640625 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002587054 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005096614 //LENGTH 3.830 LUMPCC 0 DR + +*CONN +*I mux_right_track_32\/mux_l1_in_1_:X O *L 0 *C 111.495 33.320 +*I mux_right_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 109.655 31.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 109.655 31.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 109.940 31.960 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 109.940 32.005 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 109.940 33.275 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 109.985 33.320 +*N mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 111.458 33.320 + +*CAP +0 mux_right_track_32\/mux_l1_in_1_:X 1e-06 +1 mux_right_track_32\/mux_l2_in_0_:A0 1e-06 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.237801e-05 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.24719e-05 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.354068e-05 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.354068e-05 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001178651 +7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001178651 + +*RES +0 mux_right_track_32\/mux_l1_in_1_:X mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_right_track_32\/mux_l2_in_0_:A0 0.152 +2 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001133929 +6 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_right_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00157679 //LENGTH 13.540 LUMPCC 0.0003057932 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_1_:X O *L 0 *C 41.225 28.220 +*I mux_bottom_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 42.955 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 42.918 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 42.365 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 42.320 17.385 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 42.320 28.175 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 42.275 28.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 41.263 28.220 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.079716e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.079716e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0005152798 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0005152798 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.842147e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.842147e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 bottom_left_grid_pin_37_[0]:24 5.237113e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 bottom_left_grid_pin_37_[0]:25 5.237113e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_left_in[0]:4 5.846678e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[0]:5 5.846678e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.205867e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.205867e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004933036 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.009633929 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0154994 //LENGTH 114.645 LUMPCC 0.003737825 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_0_:X O *L 0 *C 26.505 66.640 +*I mux_bottom_track_9\/BUFT_RR_72:A I *L 0.001776 *C 85.100 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 85.062 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 83.765 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 83.720 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 83.713 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 46.020 12.240 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 46.000 12.248 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 46.000 66.633 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 45.980 66.640 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 27.148 66.640 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 27.140 66.640 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 27.095 66.640 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 26.543 66.640 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_9\/BUFT_RR_72:A 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.096043e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.096043e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.270374e-05 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.002156998 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002156998 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002711663 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.002711663 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0008211468 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0008211468 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 3.552288e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:12 6.49037e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:13 6.49037e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 chanx_right_in[12]:27 0.0004468747 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 chanx_right_in[12]:26 0.0004468747 +16 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 chanx_left_in[8]:21 0.001069934 +17 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 chanx_left_in[8]:20 0.001069934 +18 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0003521037 +19 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0003521037 + +*RES +0 mux_bottom_track_9\/mux_l3_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0004933036 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.00341 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.002950425 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.008520316 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.005905158 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001158482 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_9\/BUFT_RR_72:A 0.152 + +*END + +*D_NET mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00106697 //LENGTH 10.640 LUMPCC 0.0001351134 DR + +*CONN +*I mux_bottom_track_29\/mux_l1_in_0_:X O *L 0 *C 108.385 19.720 +*I mux_bottom_track_29\/mux_l2_in_0_:A1 I *L 0.00198 *C 107.085 12.580 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 107.123 12.580 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 108.975 12.580 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 109.020 12.625 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 109.020 19.675 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 108.975 19.720 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 108.422 19.720 + +*CAP +0 mux_bottom_track_29\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_29\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001240611 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001240611 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002844006 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002844006 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.646666e-05 +7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.646666e-05 +8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_1_sram[0]:12 6.755671e-05 +9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_1_sram[0]:11 6.755671e-05 + +*RES +0 mux_bottom_track_29\/mux_l1_in_0_:X mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_29\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001654018 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294643 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET ropt_net_214 0.001066618 //LENGTH 8.010 LUMPCC 0.0003576725 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 4.140 93.160 +*I ropt_mt_inst_832:A I *L 0.001766 *C 7.820 96.560 +*N ropt_net_214:2 *C 7.783 96.560 +*N ropt_net_214:3 *C 6.945 96.560 +*N ropt_net_214:4 *C 6.900 96.515 +*N ropt_net_214:5 *C 6.900 93.205 +*N ropt_net_214:6 *C 6.855 93.160 +*N ropt_net_214:7 *C 4.178 93.160 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 ropt_mt_inst_832:A 1e-06 +2 ropt_net_214:2 1.985784e-05 +3 ropt_net_214:3 1.985784e-05 +4 ropt_net_214:4 0.000197205 +5 ropt_net_214:5 0.000197205 +6 ropt_net_214:6 0.0001364099 +7 ropt_net_214:7 0.0001364099 +8 ropt_net_214:7 chanx_right_in[10]:9 7.964741e-05 +9 ropt_net_214:6 chanx_right_in[10]:10 7.964741e-05 +10 ropt_net_214:5 chanx_right_in[10]:12 6.55182e-06 +11 ropt_net_214:4 chanx_right_in[10]:11 6.55182e-06 +12 ropt_net_214:3 left_top_grid_pin_1_[0]:16 4.631851e-05 +13 ropt_net_214:2 left_top_grid_pin_1_[0]:15 4.631851e-05 +14 ropt_net_214:3 ropt_net_174:3 4.631851e-05 +15 ropt_net_214:2 ropt_net_174:4 4.631851e-05 + +*RES +0 ropt_mt_inst_791:X ropt_net_214:7 0.152 +1 ropt_net_214:7 ropt_net_214:6 0.002390625 +2 ropt_net_214:6 ropt_net_214:5 0.0045 +3 ropt_net_214:5 ropt_net_214:4 0.002955357 +4 ropt_net_214:3 ropt_net_214:2 0.0007477679 +5 ropt_net_214:4 ropt_net_214:3 0.0045 +6 ropt_net_214:2 ropt_mt_inst_832:A 0.152 + +*END + +*D_NET chanx_left_out[1] 0.001220983 //LENGTH 8.705 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 7.065 95.880 +*P chanx_left_out[1] O *L 0.7423 *C 1.298 93.840 +*N chanx_left_out[1]:2 *C 1.380 93.840 +*N chanx_left_out[1]:3 *C 1.380 93.898 +*N chanx_left_out[1]:4 *C 1.380 95.835 +*N chanx_left_out[1]:5 *C 1.425 95.880 +*N chanx_left_out[1]:6 *C 7.028 95.880 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 chanx_left_out[1] 3.14872e-05 +2 chanx_left_out[1]:2 3.14872e-05 +3 chanx_left_out[1]:3 0.000121308 +4 chanx_left_out[1]:4 0.000121308 +5 chanx_left_out[1]:5 0.0004571964 +6 chanx_left_out[1]:6 0.0004571964 + +*RES +0 ropt_mt_inst_794:X chanx_left_out[1]:6 0.152 +1 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +2 chanx_left_out[1]:2 chanx_left_out[1] 2.35e-05 +3 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +4 chanx_left_out[1]:4 chanx_left_out[1]:3 0.001729911 +5 chanx_left_out[1]:6 chanx_left_out[1]:5 0.005002232 + +*END + +*D_NET ropt_net_204 0.001144729 //LENGTH 8.220 LUMPCC 0.0001431535 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 88.040 9.520 +*I ropt_mt_inst_822:A I *L 0.001767 *C 83.720 6.800 +*N ropt_net_204:2 *C 83.720 6.800 +*N ropt_net_204:3 *C 84.180 6.800 +*N ropt_net_204:4 *C 84.180 7.140 +*N ropt_net_204:5 *C 85.975 7.140 +*N ropt_net_204:6 *C 86.020 7.185 +*N ropt_net_204:7 *C 86.020 9.475 +*N ropt_net_204:8 *C 86.065 9.520 +*N ropt_net_204:9 *C 88.002 9.520 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 ropt_mt_inst_822:A 1e-06 +2 ropt_net_204:2 8.096323e-05 +3 ropt_net_204:3 6.54474e-05 +4 ropt_net_204:4 0.0001340361 +5 ropt_net_204:5 0.0001055053 +6 ropt_net_204:6 0.0001358858 +7 ropt_net_204:7 0.0001358858 +8 ropt_net_204:8 0.0001709257 +9 ropt_net_204:9 0.0001709257 +10 ropt_net_204:7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.380594e-05 +11 ropt_net_204:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.1591e-05 +12 ropt_net_204:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.380594e-05 +13 ropt_net_204:2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.179814e-06 +14 ropt_net_204:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.179814e-06 +15 ropt_net_204:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.1591e-05 + +*RES +0 ropt_mt_inst_799:X ropt_net_204:9 0.152 +1 ropt_net_204:9 ropt_net_204:8 0.001729911 +2 ropt_net_204:8 ropt_net_204:7 0.0045 +3 ropt_net_204:7 ropt_net_204:6 0.002044643 +4 ropt_net_204:5 ropt_net_204:4 0.001602679 +5 ropt_net_204:6 ropt_net_204:5 0.0045 +6 ropt_net_204:2 ropt_mt_inst_822:A 0.152 +7 ropt_net_204:3 ropt_net_204:2 0.0004107143 +8 ropt_net_204:4 ropt_net_204:3 0.0003035715 + +*END + +*D_NET chanx_right_out[9] 0.0006242789 //LENGTH 4.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_813:X O *L 0 *C 136.160 44.880 +*P chanx_right_out[9] O *L 0.7423 *C 140.450 44.880 +*N chanx_right_out[9]:2 *C 138.468 44.880 +*N chanx_right_out[9]:3 *C 138.460 44.880 +*N chanx_right_out[9]:4 *C 138.415 44.880 +*N chanx_right_out[9]:5 *C 136.198 44.880 + +*CAP +0 ropt_mt_inst_813:X 1e-06 +1 chanx_right_out[9] 0.0001557639 +2 chanx_right_out[9]:2 0.0001557639 +3 chanx_right_out[9]:3 3.958821e-05 +4 chanx_right_out[9]:4 0.0001360815 +5 chanx_right_out[9]:5 0.0001360815 + +*RES +0 ropt_mt_inst_813:X chanx_right_out[9]:5 0.152 +1 chanx_right_out[9]:5 chanx_right_out[9]:4 0.001979911 +2 chanx_right_out[9]:4 chanx_right_out[9]:3 0.0045 +3 chanx_right_out[9]:3 chanx_right_out[9]:2 0.00341 +4 chanx_right_out[9]:2 chanx_right_out[9] 0.0003105917 + +*END + +*D_NET chanx_right_out[3] 0.0005930613 //LENGTH 4.760 LUMPCC 8.589491e-05 DR + +*CONN +*I ropt_mt_inst_824:X O *L 0 *C 136.160 82.960 +*P chanx_right_out[3] O *L 0.7423 *C 140.450 82.960 +*N chanx_right_out[3]:2 *C 139.388 82.960 +*N chanx_right_out[3]:3 *C 139.380 82.960 +*N chanx_right_out[3]:4 *C 139.335 82.960 +*N chanx_right_out[3]:5 *C 136.198 82.960 + +*CAP +0 ropt_mt_inst_824:X 1e-06 +1 chanx_right_out[3] 8.141754e-05 +2 chanx_right_out[3]:2 8.141754e-05 +3 chanx_right_out[3]:3 2.945316e-05 +4 chanx_right_out[3]:4 0.0001569391 +5 chanx_right_out[3]:5 0.0001569391 +6 chanx_right_out[3]:5 ropt_net_206:6 4.294746e-05 +7 chanx_right_out[3]:4 ropt_net_206:7 4.294746e-05 + +*RES +0 ropt_mt_inst_824:X chanx_right_out[3]:5 0.152 +1 chanx_right_out[3]:5 chanx_right_out[3]:4 0.002801339 +2 chanx_right_out[3]:4 chanx_right_out[3]:3 0.0045 +3 chanx_right_out[3]:3 chanx_right_out[3]:2 0.00341 +4 chanx_right_out[3]:2 chanx_right_out[3] 0.0001664583 + +*END + +*D_NET chanx_left_out[18] 0.00266029 //LENGTH 13.260 LUMPCC 0.001161439 DR + +*CONN +*I ropt_mt_inst_834:X O *L 0 *C 11.695 68.680 +*P chanx_left_out[18] O *L 0.7423 *C 1.305 66.640 +*N chanx_left_out[18]:2 *C 1.380 67.320 +*N chanx_left_out[18]:3 *C 11.492 67.320 +*N chanx_left_out[18]:4 *C 11.500 67.377 +*N chanx_left_out[18]:5 *C 11.500 68.635 +*N chanx_left_out[18]:6 *C 11.500 68.680 +*N chanx_left_out[18]:7 *C 11.695 68.680 + +*CAP +0 ropt_mt_inst_834:X 1e-06 +1 chanx_left_out[18] 5.246684e-05 +2 chanx_left_out[18]:2 0.0005861768 +3 chanx_left_out[18]:3 0.0005337099 +4 chanx_left_out[18]:4 0.0001011317 +5 chanx_left_out[18]:5 0.0001011317 +6 chanx_left_out[18]:6 6.149037e-05 +7 chanx_left_out[18]:7 6.174405e-05 +8 chanx_left_out[18]:3 chanx_left_in[2]:24 0.0005807196 +9 chanx_left_out[18]:2 chanx_left_in[2] 0.0005807196 + +*RES +0 ropt_mt_inst_834:X chanx_left_out[18]:7 0.152 +1 chanx_left_out[18]:7 chanx_left_out[18]:6 0.0001059783 +2 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0045 +3 chanx_left_out[18]:5 chanx_left_out[18]:4 0.001122768 +4 chanx_left_out[18]:4 chanx_left_out[18]:3 0.00341 +5 chanx_left_out[18]:3 chanx_left_out[18]:2 0.001584292 +6 chanx_left_out[18]:2 chanx_left_out[18] 0.0001065333 + +*END + +*D_NET ropt_net_177 0.001404914 //LENGTH 13.690 LUMPCC 0 DR + +*CONN +*I BUFT_P_143:X O *L 0 *C 15.445 85.680 +*I ropt_mt_inst_797:A I *L 0.001767 *C 7.820 91.120 +*N ropt_net_177:2 *C 7.820 91.120 +*N ropt_net_177:3 *C 7.820 91.075 +*N ropt_net_177:4 *C 7.820 85.725 +*N ropt_net_177:5 *C 7.865 85.680 +*N ropt_net_177:6 *C 15.408 85.680 + +*CAP +0 BUFT_P_143:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_177:2 3.825433e-05 +3 ropt_net_177:3 0.0002906777 +4 ropt_net_177:4 0.0002906777 +5 ropt_net_177:5 0.0003916522 +6 ropt_net_177:6 0.0003916522 + +*RES +0 BUFT_P_143:X ropt_net_177:6 0.152 +1 ropt_net_177:6 ropt_net_177:5 0.006734375 +2 ropt_net_177:5 ropt_net_177:4 0.0045 +3 ropt_net_177:4 ropt_net_177:3 0.004776786 +4 ropt_net_177:2 ropt_mt_inst_797:A 0.152 +5 ropt_net_177:3 ropt_net_177:2 0.0045 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..814bed1 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef @@ -0,0 +1,18292 @@ +*SPEF "1481-1998" +*DESIGN "sb_2__0_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 29.210 99.960 +chany_top_in[0] I *C 80.500 102.680 +chany_top_in[1] I *C 57.500 102.680 +chany_top_in[2] I *C 82.340 102.680 +chany_top_in[3] I *C 74.060 102.680 +chany_top_in[4] I *C 51.980 102.680 +chany_top_in[5] I *C 60.260 102.680 +chany_top_in[6] I *C 74.980 102.680 +chany_top_in[7] I *C 66.700 102.680 +chany_top_in[8] I *C 72.220 102.680 +chany_top_in[9] I *C 67.620 102.680 +chany_top_in[10] I *C 73.140 102.680 +chany_top_in[11] I *C 75.900 102.680 +chany_top_in[12] I *C 52.900 102.680 +chany_top_in[13] I *C 63.480 102.680 +chany_top_in[14] I *C 54.740 102.680 +chany_top_in[15] I *C 53.820 102.680 +chany_top_in[16] I *C 69.460 102.680 +chany_top_in[17] I *C 81.420 102.680 +chany_top_in[18] I *C 84.640 102.680 +chany_top_in[19] I *C 59.340 102.680 +top_left_grid_pin_34_[0] I *C 32.660 102.680 +top_left_grid_pin_35_[0] I *C 30.820 102.680 +top_left_grid_pin_36_[0] I *C 29.210 93.840 +top_left_grid_pin_37_[0] I *C 31.740 102.680 +top_left_grid_pin_38_[0] I *C 29.210 97.920 +top_left_grid_pin_39_[0] I *C 29.210 96.560 +top_left_grid_pin_40_[0] I *C 29.210 95.200 +top_left_grid_pin_41_[0] I *C 29.210 90.440 +top_right_grid_pin_1_[0] I *C 110.860 102.680 +chanx_left_in[0] I *C 0.690 51.680 +chanx_left_in[1] I *C 0.690 54.400 +chanx_left_in[2] I *C 0.690 57.120 +chanx_left_in[3] I *C 0.690 53.040 +chanx_left_in[4] I *C 0.690 62.560 +chanx_left_in[5] I *C 0.690 50.320 +chanx_left_in[6] I *C 0.690 47.600 +chanx_left_in[7] I *C 0.690 70.720 +chanx_left_in[8] I *C 0.690 32.640 +chanx_left_in[9] I *C 0.690 72.080 +chanx_left_in[10] I *C 0.690 67.320 +chanx_left_in[11] I *C 0.690 69.360 +chanx_left_in[12] I *C 0.690 36.720 +chanx_left_in[13] I *C 0.690 44.880 +chanx_left_in[14] I *C 0.690 6.800 +chanx_left_in[15] I *C 0.690 42.160 +chanx_left_in[16] I *C 0.690 28.560 +chanx_left_in[17] I *C 0.690 19.040 +chanx_left_in[18] I *C 0.690 5.440 +chanx_left_in[19] I *C 0.690 4.080 +left_top_grid_pin_42_[0] I *C 7.360 75.480 +left_top_grid_pin_43_[0] I *C 29.210 91.800 +left_top_grid_pin_44_[0] I *C 4.140 75.480 +left_top_grid_pin_45_[0] I *C 5.060 75.480 +left_top_grid_pin_46_[0] I *C 2.300 75.480 +left_top_grid_pin_47_[0] I *C 3.220 75.480 +left_top_grid_pin_48_[0] I *C 11.500 75.480 +left_top_grid_pin_49_[0] I *C 10.580 75.480 +left_bottom_grid_pin_1_[0] I *C 2.300 0.680 +ccff_head[0] I *C 108.100 102.680 +chany_top_out[0] O *C 76.820 102.680 +chany_top_out[1] O *C 61.180 102.680 +chany_top_out[2] O *C 77.740 102.680 +chany_top_out[3] O *C 71.300 102.680 +chany_top_out[4] O *C 98.900 102.680 +chany_top_out[5] O *C 83.720 102.680 +chany_top_out[6] O *C 70.380 102.680 +chany_top_out[7] O *C 50.140 102.680 +chany_top_out[8] O *C 68.540 102.680 +chany_top_out[9] O *C 58.420 102.680 +chany_top_out[10] O *C 96.600 102.680 +chany_top_out[11] O *C 93.840 102.680 +chany_top_out[12] O *C 79.580 102.680 +chany_top_out[13] O *C 64.400 102.680 +chany_top_out[14] O *C 97.520 102.680 +chany_top_out[15] O *C 51.060 102.680 +chany_top_out[16] O *C 86.940 102.680 +chany_top_out[17] O *C 62.100 102.680 +chany_top_out[18] O *C 95.680 102.680 +chany_top_out[19] O *C 78.660 102.680 +chanx_left_out[0] O *C 0.690 27.200 +chanx_left_out[1] O *C 0.690 64.600 +chanx_left_out[2] O *C 0.690 15.640 +chanx_left_out[3] O *C 0.690 59.840 +chanx_left_out[4] O *C 0.690 11.560 +chanx_left_out[5] O *C 0.690 61.200 +chanx_left_out[6] O *C 0.690 25.840 +chanx_left_out[7] O *C 0.690 48.960 +chanx_left_out[8] O *C 0.690 21.760 +chanx_left_out[9] O *C 0.690 34.000 +chanx_left_out[10] O *C 0.690 20.400 +chanx_left_out[11] O *C 0.690 38.080 +chanx_left_out[12] O *C 0.690 23.120 +chanx_left_out[13] O *C 0.690 65.960 +chanx_left_out[14] O *C 0.690 17.680 +chanx_left_out[15] O *C 0.690 39.440 +chanx_left_out[16] O *C 0.690 31.280 +chanx_left_out[17] O *C 0.690 43.520 +chanx_left_out[18] O *C 0.690 10.200 +chanx_left_out[19] O *C 0.690 58.480 +ccff_tail[0] O *C 0.690 55.760 +VDD I *C 56.580 51.680 +VSS I *C 56.580 51.680 + +*D_NET chany_top_in[1] 0.01047349 //LENGTH 79.400 LUMPCC 0.00185306 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 57.500 102.070 +*I BUFT_P_82:A I *L 0.001776 *C 26.680 58.480 +*N chany_top_in[1]:2 *C 26.643 58.480 +*N chany_top_in[1]:3 *C 26.265 58.480 +*N chany_top_in[1]:4 *C 26.220 58.525 +*N chany_top_in[1]:5 *C 26.220 74.415 +*N chany_top_in[1]:6 *C 26.265 74.460 +*N chany_top_in[1]:7 *C 37.225 74.460 +*N chany_top_in[1]:8 *C 37.260 74.800 +*N chany_top_in[1]:9 *C 37.260 74.845 +*N chany_top_in[1]:10 *C 37.260 75.422 +*N chany_top_in[1]:11 *C 37.267 75.480 +*N chany_top_in[1]:12 *C 56.573 75.480 +*N chany_top_in[1]:13 *C 56.580 75.480 +*N chany_top_in[1]:14 *C 56.580 75.140 +*N chany_top_in[1]:15 *C 56.625 75.140 +*N chany_top_in[1]:16 *C 57.915 75.140 +*N chany_top_in[1]:17 *C 57.960 75.185 +*N chany_top_in[1]:18 *C 57.960 86.360 +*N chany_top_in[1]:19 *C 57.500 86.360 + +*CAP +0 chany_top_in[1] 0.0008906535 +1 BUFT_P_82:A 1e-06 +2 chany_top_in[1]:2 5.282744e-05 +3 chany_top_in[1]:3 5.282744e-05 +4 chany_top_in[1]:4 0.0009036423 +5 chany_top_in[1]:5 0.0009036423 +6 chany_top_in[1]:6 0.0005254194 +7 chany_top_in[1]:7 0.0005585232 +8 chany_top_in[1]:8 7.026095e-05 +9 chany_top_in[1]:9 5.040898e-05 +10 chany_top_in[1]:10 5.040898e-05 +11 chany_top_in[1]:11 0.001057977 +12 chany_top_in[1]:12 0.001057977 +13 chany_top_in[1]:13 5.432197e-05 +14 chany_top_in[1]:14 4.994186e-05 +15 chany_top_in[1]:15 0.0001144023 +16 chany_top_in[1]:16 0.0001144023 +17 chany_top_in[1]:17 0.0005792017 +18 chany_top_in[1]:18 0.0006105707 +19 chany_top_in[1]:19 0.0009220224 +20 chany_top_in[1]:6 chanx_left_in[9]:8 5.557325e-06 +21 chany_top_in[1]:11 chanx_left_in[9]:8 0.0002870231 +22 chany_top_in[1]:11 chanx_left_in[9]:7 0.0001081592 +23 chany_top_in[1]:12 chanx_left_in[9]:6 0.0001081592 +24 chany_top_in[1]:12 chanx_left_in[9]:7 0.0002870231 +25 chany_top_in[1]:7 chanx_left_in[9]:7 5.557325e-06 +26 chany_top_in[1]:6 mux_tree_tapbuf_size2_15_sram[0]:12 0.0003552328 +27 chany_top_in[1]:9 mux_tree_tapbuf_size2_15_sram[0]:15 2.032925e-06 +28 chany_top_in[1]:10 mux_tree_tapbuf_size2_15_sram[0]:14 2.032925e-06 +29 chany_top_in[1]:7 mux_tree_tapbuf_size2_15_sram[0]:13 0.0003552328 +30 chany_top_in[1]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.063452e-05 +31 chany_top_in[1]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.063452e-05 +32 chany_top_in[1]:13 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.0009e-05 +33 chany_top_in[1]:14 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.0009e-05 +34 chany_top_in[1]:17 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.788094e-05 +35 chany_top_in[1]:18 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.788094e-05 + +*RES +0 chany_top_in[1] chany_top_in[1]:19 0.01402679 +1 chany_top_in[1]:2 BUFT_P_82:A 0.152 +2 chany_top_in[1]:3 chany_top_in[1]:2 0.0003370536 +3 chany_top_in[1]:4 chany_top_in[1]:3 0.0045 +4 chany_top_in[1]:6 chany_top_in[1]:5 0.0045 +5 chany_top_in[1]:5 chany_top_in[1]:4 0.0141875 +6 chany_top_in[1]:8 chany_top_in[1]:7 0.0002297298 +7 chany_top_in[1]:9 chany_top_in[1]:8 0.0045 +8 chany_top_in[1]:10 chany_top_in[1]:9 0.000515625 +9 chany_top_in[1]:11 chany_top_in[1]:10 0.00341 +10 chany_top_in[1]:13 chany_top_in[1]:12 0.00341 +11 chany_top_in[1]:12 chany_top_in[1]:11 0.00302445 +12 chany_top_in[1]:15 chany_top_in[1]:14 0.0045 +13 chany_top_in[1]:14 chany_top_in[1]:13 0.0001634615 +14 chany_top_in[1]:16 chany_top_in[1]:15 0.001151786 +15 chany_top_in[1]:17 chany_top_in[1]:16 0.0045 +16 chany_top_in[1]:7 chany_top_in[1]:6 0.009785715 +17 chany_top_in[1]:19 chany_top_in[1]:18 0.0004107143 +18 chany_top_in[1]:18 chany_top_in[1]:17 0.00997768 + +*END + +*D_NET top_left_grid_pin_39_[0] 0.01040661 //LENGTH 67.245 LUMPCC 0.004045011 DR + +*CONN +*P top_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 96.560 +*I mux_top_track_18\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.900 83.300 +*I mux_top_track_34\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.740 72.420 +*I mux_top_track_6\/mux_l1_in_1_:A1 I *L 0.00198 *C 57.600 63.580 +*I mux_top_track_2\/mux_l1_in_1_:A1 I *L 0.00198 *C 61.085 63.580 +*N top_left_grid_pin_39_[0]:5 *C 61.047 63.580 +*N top_left_grid_pin_39_[0]:6 *C 57.600 63.580 +*N top_left_grid_pin_39_[0]:7 *C 54.785 63.580 +*N top_left_grid_pin_39_[0]:8 *C 54.740 63.625 +*N top_left_grid_pin_39_[0]:9 *C 54.740 72.375 +*N top_left_grid_pin_39_[0]:10 *C 54.703 72.420 +*N top_left_grid_pin_39_[0]:11 *C 53.405 72.420 +*N top_left_grid_pin_39_[0]:12 *C 53.360 72.465 +*N top_left_grid_pin_39_[0]:13 *C 52.938 83.300 +*N top_left_grid_pin_39_[0]:14 *C 53.315 83.300 +*N top_left_grid_pin_39_[0]:15 *C 53.360 83.300 +*N top_left_grid_pin_39_[0]:16 *C 53.360 85.623 +*N top_left_grid_pin_39_[0]:17 *C 53.352 85.680 +*N top_left_grid_pin_39_[0]:18 *C 32.220 85.680 +*N top_left_grid_pin_39_[0]:19 *C 32.200 85.688 +*N top_left_grid_pin_39_[0]:20 *C 32.200 96.553 +*N top_left_grid_pin_39_[0]:21 *C 32.180 96.560 + +*CAP +0 top_left_grid_pin_39_[0] 0.0001963777 +1 mux_top_track_18\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_34\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_1_:A1 1e-06 +4 mux_top_track_2\/mux_l1_in_1_:A1 1e-06 +5 top_left_grid_pin_39_[0]:5 0.0002011915 +6 top_left_grid_pin_39_[0]:6 0.0003910951 +7 top_left_grid_pin_39_[0]:7 0.0001621741 +8 top_left_grid_pin_39_[0]:8 0.0004434919 +9 top_left_grid_pin_39_[0]:9 0.0004434919 +10 top_left_grid_pin_39_[0]:10 0.0001121961 +11 top_left_grid_pin_39_[0]:11 0.0001121961 +12 top_left_grid_pin_39_[0]:12 0.0004150189 +13 top_left_grid_pin_39_[0]:13 4.907096e-05 +14 top_left_grid_pin_39_[0]:14 4.907096e-05 +15 top_left_grid_pin_39_[0]:15 0.0005520927 +16 top_left_grid_pin_39_[0]:16 0.0001034551 +17 top_left_grid_pin_39_[0]:17 0.0008437623 +18 top_left_grid_pin_39_[0]:18 0.0008437623 +19 top_left_grid_pin_39_[0]:19 0.0006213847 +20 top_left_grid_pin_39_[0]:20 0.0006213847 +21 top_left_grid_pin_39_[0]:21 0.0001963777 +22 top_left_grid_pin_39_[0]:17 chany_top_in[19]:11 0.0009042483 +23 top_left_grid_pin_39_[0]:18 chany_top_in[19]:10 0.0009042483 +24 top_left_grid_pin_39_[0]:15 top_left_grid_pin_35_[0]:14 6.496724e-05 +25 top_left_grid_pin_39_[0]:15 top_left_grid_pin_35_[0]:15 0.0002853798 +26 top_left_grid_pin_39_[0]:12 top_left_grid_pin_35_[0]:14 0.0002853798 +27 top_left_grid_pin_39_[0]:9 top_left_grid_pin_35_[0]:15 2.932254e-05 +28 top_left_grid_pin_39_[0]:8 top_left_grid_pin_35_[0]:14 2.932254e-05 +29 top_left_grid_pin_39_[0]:16 top_left_grid_pin_35_[0]:15 6.496724e-05 +30 top_left_grid_pin_39_[0]:17 chanx_left_in[8]:7 0.0005663444 +31 top_left_grid_pin_39_[0]:18 chanx_left_in[8]:8 0.0005663444 +32 top_left_grid_pin_39_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.331087e-07 +33 top_left_grid_pin_39_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.499217e-05 +34 top_left_grid_pin_39_[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.331087e-07 +35 top_left_grid_pin_39_[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.499217e-05 +36 top_left_grid_pin_39_[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.903932e-05 +37 top_left_grid_pin_39_[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.807903e-05 +38 top_left_grid_pin_39_[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.903932e-05 +39 top_left_grid_pin_39_[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.807903e-05 + +*RES +0 top_left_grid_pin_39_[0] top_left_grid_pin_39_[0]:21 0.0003807 +1 top_left_grid_pin_39_[0]:13 mux_top_track_18\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_39_[0]:14 top_left_grid_pin_39_[0]:13 0.0003370536 +3 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:14 0.0045 +4 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:12 0.009674108 +5 top_left_grid_pin_39_[0]:10 mux_top_track_34\/mux_l1_in_0_:A1 0.152 +6 top_left_grid_pin_39_[0]:10 top_left_grid_pin_39_[0]:9 0.0045 +7 top_left_grid_pin_39_[0]:11 top_left_grid_pin_39_[0]:10 0.001158482 +8 top_left_grid_pin_39_[0]:12 top_left_grid_pin_39_[0]:11 0.0045 +9 top_left_grid_pin_39_[0]:9 top_left_grid_pin_39_[0]:8 0.0078125 +10 top_left_grid_pin_39_[0]:7 top_left_grid_pin_39_[0]:6 0.002513393 +11 top_left_grid_pin_39_[0]:8 top_left_grid_pin_39_[0]:7 0.0045 +12 top_left_grid_pin_39_[0]:16 top_left_grid_pin_39_[0]:15 0.002073661 +13 top_left_grid_pin_39_[0]:17 top_left_grid_pin_39_[0]:16 0.00341 +14 top_left_grid_pin_39_[0]:18 top_left_grid_pin_39_[0]:17 0.003310758 +15 top_left_grid_pin_39_[0]:19 top_left_grid_pin_39_[0]:18 0.00341 +16 top_left_grid_pin_39_[0]:21 top_left_grid_pin_39_[0]:20 0.00341 +17 top_left_grid_pin_39_[0]:20 top_left_grid_pin_39_[0]:19 0.001702183 +18 top_left_grid_pin_39_[0]:6 mux_top_track_6\/mux_l1_in_1_:A1 0.152 +19 top_left_grid_pin_39_[0]:6 top_left_grid_pin_39_[0]:5 0.003078125 +20 top_left_grid_pin_39_[0]:5 mux_top_track_2\/mux_l1_in_1_:A1 0.152 + +*END + +*D_NET left_top_grid_pin_44_[0] 0.008013859 //LENGTH 50.715 LUMPCC 0.003170216 DR + +*CONN +*P left_top_grid_pin_44_[0] I *L 0.29796 *C 4.140 74.835 +*I mux_left_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 13.440 50.660 +*I mux_left_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 22.180 50.660 +*I mux_left_track_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 18.690 71.740 +*N left_top_grid_pin_44_[0]:4 *C 18.690 71.740 +*N left_top_grid_pin_44_[0]:5 *C 18.400 71.740 +*N left_top_grid_pin_44_[0]:6 *C 18.370 71.710 +*N left_top_grid_pin_44_[0]:7 *C 18.355 71.400 +*N left_top_grid_pin_44_[0]:8 *C 22.143 50.660 +*N left_top_grid_pin_44_[0]:9 *C 13.478 50.660 +*N left_top_grid_pin_44_[0]:10 *C 14.720 50.660 +*N left_top_grid_pin_44_[0]:11 *C 14.720 50.320 +*N left_top_grid_pin_44_[0]:12 *C 17.940 50.320 +*N left_top_grid_pin_44_[0]:13 *C 17.940 50.660 +*N left_top_grid_pin_44_[0]:14 *C 17.940 50.705 +*N left_top_grid_pin_44_[0]:15 *C 17.940 71.400 +*N left_top_grid_pin_44_[0]:16 *C 17.940 72.703 +*N left_top_grid_pin_44_[0]:17 *C 17.933 72.760 +*N left_top_grid_pin_44_[0]:18 *C 4.147 72.760 +*N left_top_grid_pin_44_[0]:19 *C 4.140 72.818 + +*CAP +0 left_top_grid_pin_44_[0] 9.638887e-05 +1 mux_left_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_1_:A1 1e-06 +3 mux_left_track_13\/mux_l1_in_0_:A0 1e-06 +4 left_top_grid_pin_44_[0]:4 6.23718e-05 +5 left_top_grid_pin_44_[0]:5 6.184971e-05 +6 left_top_grid_pin_44_[0]:6 3.785137e-05 +7 left_top_grid_pin_44_[0]:7 6.774694e-05 +8 left_top_grid_pin_44_[0]:8 0.0003498928 +9 left_top_grid_pin_44_[0]:9 0.0001380531 +10 left_top_grid_pin_44_[0]:10 0.0001641731 +11 left_top_grid_pin_44_[0]:11 0.0002641552 +12 left_top_grid_pin_44_[0]:12 0.0002666168 +13 left_top_grid_pin_44_[0]:13 0.0003784744 +14 left_top_grid_pin_44_[0]:14 0.001054411 +15 left_top_grid_pin_44_[0]:15 0.001155425 +16 left_top_grid_pin_44_[0]:16 7.111877e-05 +17 left_top_grid_pin_44_[0]:17 0.0002878624 +18 left_top_grid_pin_44_[0]:18 0.0002878624 +19 left_top_grid_pin_44_[0]:19 9.638887e-05 +20 left_top_grid_pin_44_[0]:17 prog_clk[0]:462 0.000370332 +21 left_top_grid_pin_44_[0]:17 prog_clk[0]:463 0.0002469412 +22 left_top_grid_pin_44_[0]:18 prog_clk[0]:402 0.000370332 +23 left_top_grid_pin_44_[0]:18 prog_clk[0]:462 0.0002469412 +24 left_top_grid_pin_44_[0]:14 prog_clk[0]:438 3.162678e-06 +25 left_top_grid_pin_44_[0]:15 prog_clk[0]:439 3.162678e-06 +26 left_top_grid_pin_44_[0] left_top_grid_pin_47_[0] 2.32698e-05 +27 left_top_grid_pin_44_[0]:17 left_top_grid_pin_47_[0]:22 0.0007953587 +28 left_top_grid_pin_44_[0]:19 left_top_grid_pin_47_[0]:24 2.32698e-05 +29 left_top_grid_pin_44_[0]:18 left_top_grid_pin_47_[0]:23 0.0007953587 +30 left_top_grid_pin_44_[0]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001460437 +31 left_top_grid_pin_44_[0]:15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001460437 + +*RES +0 left_top_grid_pin_44_[0] left_top_grid_pin_44_[0]:19 0.001801339 +1 left_top_grid_pin_44_[0]:5 left_top_grid_pin_44_[0]:4 0.0001576087 +2 left_top_grid_pin_44_[0]:6 left_top_grid_pin_44_[0]:5 0.0045 +3 left_top_grid_pin_44_[0]:4 mux_left_track_13\/mux_l1_in_0_:A0 0.152 +4 left_top_grid_pin_44_[0]:8 mux_left_track_5\/mux_l1_in_1_:A1 0.152 +5 left_top_grid_pin_44_[0]:9 mux_left_track_1\/mux_l1_in_1_:A1 0.152 +6 left_top_grid_pin_44_[0]:16 left_top_grid_pin_44_[0]:15 0.001162946 +7 left_top_grid_pin_44_[0]:17 left_top_grid_pin_44_[0]:16 0.00341 +8 left_top_grid_pin_44_[0]:19 left_top_grid_pin_44_[0]:18 0.00341 +9 left_top_grid_pin_44_[0]:18 left_top_grid_pin_44_[0]:17 0.00215965 +10 left_top_grid_pin_44_[0]:13 left_top_grid_pin_44_[0]:12 0.0003035715 +11 left_top_grid_pin_44_[0]:13 left_top_grid_pin_44_[0]:8 0.003752232 +12 left_top_grid_pin_44_[0]:14 left_top_grid_pin_44_[0]:13 0.0045 +13 left_top_grid_pin_44_[0]:10 left_top_grid_pin_44_[0]:9 0.001109375 +14 left_top_grid_pin_44_[0]:11 left_top_grid_pin_44_[0]:10 0.0003035715 +15 left_top_grid_pin_44_[0]:12 left_top_grid_pin_44_[0]:11 0.002875 +16 left_top_grid_pin_44_[0]:15 left_top_grid_pin_44_[0]:14 0.01847768 +17 left_top_grid_pin_44_[0]:15 left_top_grid_pin_44_[0]:7 0.0003705357 +18 left_top_grid_pin_44_[0]:7 left_top_grid_pin_44_[0]:6 0.00019375 + +*END + +*D_NET chanx_left_out[2] 0.001498697 //LENGTH 13.235 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.180 20.060 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 15.640 +*N chanx_left_out[2]:2 *C 6.893 15.640 +*N chanx_left_out[2]:3 *C 6.900 15.698 +*N chanx_left_out[2]:4 *C 6.900 20.355 +*N chanx_left_out[2]:5 *C 6.923 20.400 +*N chanx_left_out[2]:6 *C 7.305 20.378 +*N chanx_left_out[2]:7 *C 7.305 20.060 +*N chanx_left_out[2]:8 *C 8.143 20.060 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 0.0003503755 +2 chanx_left_out[2]:2 0.0003503755 +3 chanx_left_out[2]:3 0.0002654739 +4 chanx_left_out[2]:4 0.0002654739 +5 chanx_left_out[2]:5 4.45903e-05 +6 chanx_left_out[2]:6 7.075649e-05 +7 chanx_left_out[2]:7 8.840853e-05 +8 chanx_left_out[2]:8 6.224234e-05 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:8 0.152 +1 chanx_left_out[2]:8 chanx_left_out[2]:7 0.0007477679 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.004158482 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.000887125 +6 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0002078805 +7 chanx_left_out[2]:7 chanx_left_out[2]:6 0.0002834821 + +*END + +*D_NET mux_tree_tapbuf_size2_15_sram[1] 0.002000138 //LENGTH 14.850 LUMPCC 0.0001572926 DR + +*CONN +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.105 72.080 +*I mem_left_track_13\/FTB_28__33:A I *L 0.001746 *C 6.900 66.640 +*I mux_left_track_13\/mux_l2_in_0_:S I *L 0.00357 *C 8.380 69.070 +*N mux_tree_tapbuf_size2_15_sram[1]:3 *C 8.380 69.070 +*N mux_tree_tapbuf_size2_15_sram[1]:4 *C 6.938 66.640 +*N mux_tree_tapbuf_size2_15_sram[1]:5 *C 8.235 66.640 +*N mux_tree_tapbuf_size2_15_sram[1]:6 *C 8.280 66.685 +*N mux_tree_tapbuf_size2_15_sram[1]:7 *C 8.280 68.635 +*N mux_tree_tapbuf_size2_15_sram[1]:8 *C 8.380 68.680 +*N mux_tree_tapbuf_size2_15_sram[1]:9 *C 12.835 68.680 +*N mux_tree_tapbuf_size2_15_sram[1]:10 *C 12.880 68.725 +*N mux_tree_tapbuf_size2_15_sram[1]:11 *C 12.880 72.035 +*N mux_tree_tapbuf_size2_15_sram[1]:12 *C 12.925 72.080 +*N mux_tree_tapbuf_size2_15_sram[1]:13 *C 14.068 72.080 + +*CAP +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_13\/FTB_28__33:A 1e-06 +2 mux_left_track_13\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_15_sram[1]:3 5.895516e-05 +4 mux_tree_tapbuf_size2_15_sram[1]:4 8.839598e-05 +5 mux_tree_tapbuf_size2_15_sram[1]:5 8.839598e-05 +6 mux_tree_tapbuf_size2_15_sram[1]:6 0.0001260042 +7 mux_tree_tapbuf_size2_15_sram[1]:7 0.0001260042 +8 mux_tree_tapbuf_size2_15_sram[1]:8 0.0003160331 +9 mux_tree_tapbuf_size2_15_sram[1]:9 0.0002845116 +10 mux_tree_tapbuf_size2_15_sram[1]:10 0.0002474264 +11 mux_tree_tapbuf_size2_15_sram[1]:11 0.0002474264 +12 mux_tree_tapbuf_size2_15_sram[1]:12 0.0001283464 +13 mux_tree_tapbuf_size2_15_sram[1]:13 0.0001283464 +14 mux_tree_tapbuf_size2_15_sram[1]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.208691e-05 +15 mux_tree_tapbuf_size2_15_sram[1]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.447194e-05 +16 mux_tree_tapbuf_size2_15_sram[1]:10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.237676e-06 +17 mux_tree_tapbuf_size2_15_sram[1]:11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.237676e-06 +18 mux_tree_tapbuf_size2_15_sram[1]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.497647e-07 +19 mux_tree_tapbuf_size2_15_sram[1]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.447194e-05 +20 mux_tree_tapbuf_size2_15_sram[1]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.497647e-07 +21 mux_tree_tapbuf_size2_15_sram[1]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.208691e-05 + +*RES +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_15_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_15_sram[1]:9 mux_tree_tapbuf_size2_15_sram[1]:8 0.003977679 +2 mux_tree_tapbuf_size2_15_sram[1]:10 mux_tree_tapbuf_size2_15_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size2_15_sram[1]:12 mux_tree_tapbuf_size2_15_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size2_15_sram[1]:11 mux_tree_tapbuf_size2_15_sram[1]:10 0.002955357 +5 mux_tree_tapbuf_size2_15_sram[1]:13 mux_tree_tapbuf_size2_15_sram[1]:12 0.001020089 +6 mux_tree_tapbuf_size2_15_sram[1]:3 mux_left_track_13\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_15_sram[1]:8 mux_tree_tapbuf_size2_15_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size2_15_sram[1]:8 mux_tree_tapbuf_size2_15_sram[1]:3 0.0003482143 +9 mux_tree_tapbuf_size2_15_sram[1]:7 mux_tree_tapbuf_size2_15_sram[1]:6 0.001741071 +10 mux_tree_tapbuf_size2_15_sram[1]:5 mux_tree_tapbuf_size2_15_sram[1]:4 0.001158482 +11 mux_tree_tapbuf_size2_15_sram[1]:6 mux_tree_tapbuf_size2_15_sram[1]:5 0.0045 +12 mux_tree_tapbuf_size2_15_sram[1]:4 mem_left_track_13\/FTB_28__33:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.002446594 //LENGTH 21.385 LUMPCC 0.0001026214 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.285 58.480 +*I mux_top_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 46.360 72.005 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.015 66.300 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 48.015 66.300 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 46.398 72.065 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 48.255 72.080 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 48.300 72.035 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 48.300 66.345 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 48.345 66.300 +*N mux_tree_tapbuf_size2_3_sram[0]:9 *C 51.015 66.300 +*N mux_tree_tapbuf_size2_3_sram[0]:10 *C 51.060 66.255 +*N mux_tree_tapbuf_size2_3_sram[0]:11 *C 51.060 58.525 +*N mux_tree_tapbuf_size2_3_sram[0]:12 *C 51.105 58.480 +*N mux_tree_tapbuf_size2_3_sram[0]:13 *C 52.248 58.480 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_16\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 4.908738e-05 +4 mux_tree_tapbuf_size2_3_sram[0]:4 0.0001400889 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0001400889 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.0002829696 +7 mux_tree_tapbuf_size2_3_sram[0]:7 0.0002829696 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.000215672 +9 mux_tree_tapbuf_size2_3_sram[0]:9 0.0001940495 +10 mux_tree_tapbuf_size2_3_sram[0]:10 0.0004336654 +11 mux_tree_tapbuf_size2_3_sram[0]:11 0.0004336654 +12 mux_tree_tapbuf_size2_3_sram[0]:12 8.435814e-05 +13 mux_tree_tapbuf_size2_3_sram[0]:13 8.435814e-05 +14 mux_tree_tapbuf_size2_3_sram[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.385068e-05 +15 mux_tree_tapbuf_size2_3_sram[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.385068e-05 +16 mux_tree_tapbuf_size2_3_sram[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.739079e-05 +17 mux_tree_tapbuf_size2_3_sram[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.511224e-08 +18 mux_tree_tapbuf_size2_3_sram[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.410455e-08 +19 mux_tree_tapbuf_size2_3_sram[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.739079e-05 +20 mux_tree_tapbuf_size2_3_sram[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.410455e-08 +21 mux_tree_tapbuf_size2_3_sram[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.511224e-08 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:4 mux_top_track_16\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.001658482 +3 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:3 0.0001793478 +6 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.005080358 +7 mux_tree_tapbuf_size2_3_sram[0]:9 mux_tree_tapbuf_size2_3_sram[0]:8 0.002383929 +8 mux_tree_tapbuf_size2_3_sram[0]:10 mux_tree_tapbuf_size2_3_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_3_sram[0]:12 mux_tree_tapbuf_size2_3_sram[0]:11 0.0045 +10 mux_tree_tapbuf_size2_3_sram[0]:11 mux_tree_tapbuf_size2_3_sram[0]:10 0.006901787 +11 mux_tree_tapbuf_size2_3_sram[0]:13 mux_tree_tapbuf_size2_3_sram[0]:12 0.001020089 +12 mux_tree_tapbuf_size2_3_sram[0]:3 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_15_ccff_tail[0] 0.002051211 //LENGTH 15.510 LUMPCC 0.0007428277 DR + +*CONN +*I mem_left_track_13\/FTB_28__33:X O *L 0 *C 3.905 66.300 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.915 60.860 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 *C 8.878 60.860 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 *C 1.885 60.860 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 *C 1.840 60.905 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 *C 1.840 66.255 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 *C 1.885 66.300 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 *C 3.868 66.300 + +*CAP +0 mem_left_track_13\/FTB_28__33:X 1e-06 +1 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 0.0003798926 +3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 0.0003798926 +4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 0.0001411875 +5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 0.0001411875 +6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 0.0001321115 +7 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 0.0001321115 +8 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 left_top_grid_pin_46_[0] 0.0001504954 +9 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 left_top_grid_pin_46_[0]:15 0.0001504954 +10 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 7.335986e-05 +11 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.335986e-05 +12 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 ropt_net_127:11 5.219894e-05 +13 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 ropt_net_127:12 5.219894e-05 +14 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 ropt_net_118:4 1.920949e-08 +15 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 ropt_net_118:2 9.534044e-05 +16 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 ropt_net_118:5 1.920949e-08 +17 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 ropt_net_118:3 9.534044e-05 + +*RES +0 mem_left_track_13\/FTB_28__33:X mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 0.001770089 +2 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 0.006243304 +5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.001387367 //LENGTH 11.485 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/FTB_10__15:X O *L 0 *C 70.145 94.180 +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 62.280 96.900 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 62.280 96.900 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 64.815 96.900 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 64.860 96.855 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 64.860 94.225 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 64.905 94.180 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 70.108 94.180 + +*CAP +0 mem_top_track_24\/FTB_10__15:X 1e-06 +1 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.0002139671 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0001761369 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.0001686564 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0001686564 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0003289753 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0003289753 + +*RES +0 mem_top_track_24\/FTB_10__15:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.002263393 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.00464509 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_2_ccff_tail[0] 0.0004628618 //LENGTH 3.300 LUMPCC 7.324832e-05 DR + +*CONN +*I mem_left_track_3\/FTB_7__12:X O *L 0 *C 17.245 55.080 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 16.735 53.380 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 *C 16.735 53.380 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 *C 16.560 53.380 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 *C 16.560 53.425 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 *C 16.560 55.035 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 *C 16.605 55.080 +*N mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 *C 17.207 55.080 + +*CAP +0 mem_left_track_3\/FTB_7__12:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 4.842806e-05 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 5.252247e-05 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.0001058484 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0001058484 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 3.748309e-05 +7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 3.748309e-05 +8 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 3.662416e-05 +9 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 3.662416e-05 + +*RES +0 mem_left_track_3\/FTB_7__12:X mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 9.510869e-05 +5 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_2_ccff_tail[0] 0.0006992391 //LENGTH 5.410 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/FTB_3__8:X O *L 0 *C 15.830 36.040 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 13.525 33.660 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 *C 13.562 33.660 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 *C 15.595 33.660 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 *C 15.640 33.705 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 *C 15.640 35.995 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 *C 15.640 36.040 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 *C 15.830 36.040 + +*CAP +0 mem_left_track_1\/FTB_3__8:X 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 0.0001499428 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0001499428 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.0001468296 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0001468296 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 5.290334e-05 +7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 5.079096e-05 + +*RES +0 mem_left_track_1\/FTB_3__8:X mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 0.001814732 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.0001032609 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002256375 //LENGTH 17.175 LUMPCC 0.0002765237 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_1_:X O *L 0 *C 83.085 56.440 +*I mux_top_track_4\/mux_l3_in_0_:A0 I *L 0.005103 *C 89.240 64.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 89.203 64.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 87.400 64.760 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 87.400 64.260 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 82.385 64.260 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 82.340 64.215 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 82.340 56.485 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 82.385 56.440 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 83.047 56.440 + +*CAP +0 mux_top_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001703608 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.000203028 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003928123 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003601451 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003579559 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003579559 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.779675e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 6.779675e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:9 1.272679e-06 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:10 4.247835e-06 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:11 7.636558e-07 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:8 1.272679e-06 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:11 4.247835e-06 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:12 7.636558e-07 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size6_1_sram[1]:13 6.353827e-05 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size6_1_sram[1]:14 6.84394e-05 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_1_sram[1]:6 6.84394e-05 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_1_sram[1]:14 6.353827e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0005915179 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.006901786 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004477679 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A0 0.152 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0004464286 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001609375 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004470834 //LENGTH 3.395 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_1_:X O *L 0 *C 23.175 64.600 +*I mux_left_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 20.070 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 20.108 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 23.138 64.600 + +*CAP +0 mux_left_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002225417 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002225417 + +*RES +0 mux_left_track_3\/mux_l2_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002705357 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009459068 //LENGTH 7.080 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 78.025 95.880 +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 82.060 93.665 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 82.023 93.560 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 78.245 93.500 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 78.200 93.545 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 78.200 95.835 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 78.200 95.880 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 78.025 95.880 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002699788 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002699788 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001431232 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001431232 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.730705e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.039576e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003372768 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006504913 //LENGTH 4.770 LUMPCC 0.0002770321 DR + +*CONN +*I mux_top_track_20\/mux_l1_in_0_:X O *L 0 *C 78.945 79.900 +*I mux_top_track_20\/mux_l2_in_0_:A1 I *L 0.00198 *C 78.300 83.300 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 78.200 83.300 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 78.200 83.255 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 78.200 79.945 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 78.245 79.900 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.907 79.900 + +*CAP +0 mux_top_track_20\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_20\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.358522e-05 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001176064 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001176064 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.133062e-05 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.133062e-05 +7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_34_[0]:21 9.727188e-05 +8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_34_[0]:20 9.727188e-05 +9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_40_[0]:16 2.707621e-05 +10 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_40_[0]:17 1.416794e-05 +11 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_40_[0]:15 2.707621e-05 +12 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_40_[0]:12 1.416794e-05 + +*RES +0 mux_top_track_20\/mux_l1_in_0_:X mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_20\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002955358 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005915179 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.006992495 //LENGTH 40.235 LUMPCC 0.003777724 DR + +*CONN +*I mux_left_track_11\/mux_l2_in_0_:X O *L 0 *C 32.835 69.360 +*I mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.345 64.090 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 5.383 64.198 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 5.935 64.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 5.980 64.305 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 5.980 67.943 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 5.988 68.000 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 35.873 68.000 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 35.880 68.058 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 35.880 69.315 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 35.835 69.360 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 32.873 69.360 + +*CAP +0 mux_left_track_11\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.368569e-05 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.368569e-05 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002133421 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002133421 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0009908578 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0009908578 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001090989 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001090989 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002394005 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002394005 +12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[10] 0.001271159 +13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[10]:20 0.001271159 +14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[11] 0.000617703 +15 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[11]:10 0.000617703 + +*RES +0 mux_left_track_11\/mux_l2_in_0_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003247768 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.004681983 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001122768 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002645089 + +*END + +*D_NET ropt_net_132 0.0004641666 //LENGTH 4.065 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_729:X O *L 0 *C 4.140 20.060 +*I ropt_mt_inst_737:A I *L 0.001766 *C 3.220 17.680 +*N ropt_net_132:2 *C 3.243 17.707 +*N ropt_net_132:3 *C 3.255 18.020 +*N ropt_net_132:4 *C 4.095 18.020 +*N ropt_net_132:5 *C 4.140 18.065 +*N ropt_net_132:6 *C 4.140 20.015 +*N ropt_net_132:7 *C 4.140 20.060 + +*CAP +0 ropt_mt_inst_729:X 1e-06 +1 ropt_mt_inst_737:A 1e-06 +2 ropt_net_132:2 3.052391e-05 +3 ropt_net_132:3 9.3043e-05 +4 ropt_net_132:4 6.251909e-05 +5 ropt_net_132:5 0.0001226972 +6 ropt_net_132:6 0.0001226972 +7 ropt_net_132:7 3.068617e-05 + +*RES +0 ropt_mt_inst_729:X ropt_net_132:7 0.152 +1 ropt_net_132:7 ropt_net_132:6 0.0045 +2 ropt_net_132:6 ropt_net_132:5 0.001741072 +3 ropt_net_132:4 ropt_net_132:3 0.00075 +4 ropt_net_132:5 ropt_net_132:4 0.0045 +5 ropt_net_132:2 ropt_mt_inst_737:A 0.152 +6 ropt_net_132:3 ropt_net_132:2 0.0002111487 + +*END + +*D_NET chany_top_in[2] 0.01709365 //LENGTH 173.045 LUMPCC 0.001294189 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 82.340 102.070 +*I ropt_mt_inst_730:A I *L 0.001767 *C 3.220 12.240 +*N chany_top_in[2]:2 *C 3.220 12.240 +*N chany_top_in[2]:3 *C 3.220 12.580 +*N chany_top_in[2]:4 *C 15.640 12.580 +*N chany_top_in[2]:5 *C 15.565 12.920 +*N chany_top_in[2]:6 *C 15.633 12.875 +*N chany_top_in[2]:7 *C 15.640 12.285 +*N chany_top_in[2]:8 *C 15.685 12.240 +*N chany_top_in[2]:9 *C 65.480 12.240 +*N chany_top_in[2]:10 *C 79.075 12.240 +*N chany_top_in[2]:11 *C 79.120 12.285 +*N chany_top_in[2]:12 *C 79.120 40.742 +*N chany_top_in[2]:13 *C 79.127 40.800 +*N chany_top_in[2]:14 *C 81.860 40.800 +*N chany_top_in[2]:15 *C 81.880 40.808 +*N chany_top_in[2]:16 *C 81.880 90.635 +*N chany_top_in[2]:17 *C 81.880 99.953 +*N chany_top_in[2]:18 *C 81.895 99.960 +*N chany_top_in[2]:19 *C 82.338 99.960 +*N chany_top_in[2]:20 *C 82.340 100.017 + +*CAP +0 chany_top_in[2] 0.000108247 +1 ropt_mt_inst_730:A 1e-06 +2 chany_top_in[2]:2 5.621571e-05 +3 chany_top_in[2]:3 0.0007043331 +4 chany_top_in[2]:4 0.0007010046 +5 chany_top_in[2]:5 5.209743e-05 +6 chany_top_in[2]:6 4.571757e-05 +7 chany_top_in[2]:7 4.571757e-05 +8 chany_top_in[2]:8 0.002367613 +9 chany_top_in[2]:9 0.003016073 +10 chany_top_in[2]:10 0.0006484597 +11 chany_top_in[2]:11 0.001291033 +12 chany_top_in[2]:12 0.001291033 +13 chany_top_in[2]:13 0.0001588646 +14 chany_top_in[2]:14 0.0001588646 +15 chany_top_in[2]:15 0.002136393 +16 chany_top_in[2]:16 0.002468193 +17 chany_top_in[2]:17 0.0003318007 +18 chany_top_in[2]:18 5.427329e-05 +19 chany_top_in[2]:19 5.427329e-05 +20 chany_top_in[2]:20 0.000108247 +21 chany_top_in[2] chany_top_in[17] 1.818107e-05 +22 chany_top_in[2]:15 chany_top_in[17]:8 0.000437237 +23 chany_top_in[2]:17 chany_top_in[17]:9 0.0001916766 +24 chany_top_in[2]:20 chany_top_in[17]:12 1.818107e-05 +25 chany_top_in[2]:16 chany_top_in[17]:8 0.0001916766 +26 chany_top_in[2]:16 chany_top_in[17]:9 0.000437237 + +*RES +0 chany_top_in[2] chany_top_in[2]:20 0.001832589 +1 chany_top_in[2]:2 ropt_mt_inst_730:A 0.152 +2 chany_top_in[2]:5 chany_top_in[2]:4 0.0003035715 +3 chany_top_in[2]:6 chany_top_in[2]:5 0.0045 +4 chany_top_in[2]:8 chany_top_in[2]:7 0.0045 +5 chany_top_in[2]:7 chany_top_in[2]:6 0.0005267857 +6 chany_top_in[2]:10 chany_top_in[2]:9 0.01213839 +7 chany_top_in[2]:11 chany_top_in[2]:10 0.0045 +8 chany_top_in[2]:12 chany_top_in[2]:11 0.02540849 +9 chany_top_in[2]:13 chany_top_in[2]:12 0.00341 +10 chany_top_in[2]:14 chany_top_in[2]:13 0.0004280916 +11 chany_top_in[2]:15 chany_top_in[2]:14 0.00341 +12 chany_top_in[2]:18 chany_top_in[2]:17 0.00341 +13 chany_top_in[2]:17 chany_top_in[2]:16 0.001459742 +14 chany_top_in[2]:20 chany_top_in[2]:19 0.00341 +15 chany_top_in[2]:19 chany_top_in[2]:18 6.499219e-05 +16 chany_top_in[2]:3 chany_top_in[2]:2 0.0003035714 +17 chany_top_in[2]:4 chany_top_in[2]:3 0.01108929 +18 chany_top_in[2]:9 chany_top_in[2]:8 0.04445983 +19 chany_top_in[2]:16 chany_top_in[2]:15 0.007806308 + +*END + +*D_NET left_top_grid_pin_43_[0] 0.005811745 //LENGTH 46.425 LUMPCC 0 DR + +*CONN +*P left_top_grid_pin_43_[0] I *L 0.29796 *C 29.750 91.800 +*I mux_left_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 27.430 69.700 +*I mux_left_track_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 31.570 65.960 +*I mux_left_track_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.010 65.960 +*I mux_left_track_27\/mux_l1_in_0_:A0 I *L 0.001631 *C 42.150 64.600 +*N left_top_grid_pin_43_[0]:5 *C 42.113 64.600 +*N left_top_grid_pin_43_[0]:6 *C 40.985 64.600 +*N left_top_grid_pin_43_[0]:7 *C 40.940 64.645 +*N left_top_grid_pin_43_[0]:8 *C 40.940 65.915 +*N left_top_grid_pin_43_[0]:9 *C 40.895 65.960 +*N left_top_grid_pin_43_[0]:10 *C 38.010 65.960 +*N left_top_grid_pin_43_[0]:11 *C 31.608 65.960 +*N left_top_grid_pin_43_[0]:12 *C 32.200 65.960 +*N left_top_grid_pin_43_[0]:13 *C 32.200 66.005 +*N left_top_grid_pin_43_[0]:14 *C 32.200 69.655 +*N left_top_grid_pin_43_[0]:15 *C 32.155 69.700 +*N left_top_grid_pin_43_[0]:16 *C 27.468 69.700 +*N left_top_grid_pin_43_[0]:17 *C 31.280 69.700 +*N left_top_grid_pin_43_[0]:18 *C 31.280 69.745 +*N left_top_grid_pin_43_[0]:19 *C 31.280 72.760 +*N left_top_grid_pin_43_[0]:20 *C 30.820 72.760 +*N left_top_grid_pin_43_[0]:21 *C 30.820 91.743 +*N left_top_grid_pin_43_[0]:22 *C 30.812 91.800 + +*CAP +0 left_top_grid_pin_43_[0] 8.544582e-05 +1 mux_left_track_3\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_7\/mux_l1_in_0_:A0 1e-06 +3 mux_left_track_11\/mux_l1_in_0_:A0 1e-06 +4 mux_left_track_27\/mux_l1_in_0_:A0 1e-06 +5 left_top_grid_pin_43_[0]:5 9.292821e-05 +6 left_top_grid_pin_43_[0]:6 9.292821e-05 +7 left_top_grid_pin_43_[0]:7 9.674909e-05 +8 left_top_grid_pin_43_[0]:8 9.674909e-05 +9 left_top_grid_pin_43_[0]:9 0.0002023186 +10 left_top_grid_pin_43_[0]:10 0.0006151898 +11 left_top_grid_pin_43_[0]:11 5.084728e-05 +12 left_top_grid_pin_43_[0]:12 0.0004646091 +13 left_top_grid_pin_43_[0]:13 0.0002309961 +14 left_top_grid_pin_43_[0]:14 0.0002309961 +15 left_top_grid_pin_43_[0]:15 7.773768e-05 +16 left_top_grid_pin_43_[0]:16 0.0002414503 +17 left_top_grid_pin_43_[0]:17 0.0003515613 +18 left_top_grid_pin_43_[0]:18 0.0002011811 +19 left_top_grid_pin_43_[0]:19 0.0002339715 +20 left_top_grid_pin_43_[0]:20 0.001194715 +21 left_top_grid_pin_43_[0]:21 0.001161925 +22 left_top_grid_pin_43_[0]:22 8.544582e-05 + +*RES +0 left_top_grid_pin_43_[0] left_top_grid_pin_43_[0]:22 0.0001664583 +1 left_top_grid_pin_43_[0]:15 left_top_grid_pin_43_[0]:14 0.0045 +2 left_top_grid_pin_43_[0]:14 left_top_grid_pin_43_[0]:13 0.003258929 +3 left_top_grid_pin_43_[0]:12 left_top_grid_pin_43_[0]:11 0.0005290179 +4 left_top_grid_pin_43_[0]:12 left_top_grid_pin_43_[0]:10 0.0051875 +5 left_top_grid_pin_43_[0]:13 left_top_grid_pin_43_[0]:12 0.0045 +6 left_top_grid_pin_43_[0]:17 left_top_grid_pin_43_[0]:16 0.003404018 +7 left_top_grid_pin_43_[0]:17 left_top_grid_pin_43_[0]:15 0.00078125 +8 left_top_grid_pin_43_[0]:18 left_top_grid_pin_43_[0]:17 0.0045 +9 left_top_grid_pin_43_[0]:21 left_top_grid_pin_43_[0]:20 0.01694866 +10 left_top_grid_pin_43_[0]:22 left_top_grid_pin_43_[0]:21 0.00341 +11 left_top_grid_pin_43_[0]:11 mux_left_track_7\/mux_l1_in_0_:A0 0.152 +12 left_top_grid_pin_43_[0]:9 left_top_grid_pin_43_[0]:8 0.0045 +13 left_top_grid_pin_43_[0]:8 left_top_grid_pin_43_[0]:7 0.001133929 +14 left_top_grid_pin_43_[0]:6 left_top_grid_pin_43_[0]:5 0.001006696 +15 left_top_grid_pin_43_[0]:7 left_top_grid_pin_43_[0]:6 0.0045 +16 left_top_grid_pin_43_[0]:5 mux_left_track_27\/mux_l1_in_0_:A0 0.152 +17 left_top_grid_pin_43_[0]:16 mux_left_track_3\/mux_l1_in_0_:A0 0.152 +18 left_top_grid_pin_43_[0]:10 mux_left_track_11\/mux_l1_in_0_:A0 0.152 +19 left_top_grid_pin_43_[0]:10 left_top_grid_pin_43_[0]:9 0.002575893 +20 left_top_grid_pin_43_[0]:20 left_top_grid_pin_43_[0]:19 0.0004107143 +21 left_top_grid_pin_43_[0]:19 left_top_grid_pin_43_[0]:18 0.002691965 + +*END + +*D_NET chany_top_out[6] 0.001647692 //LENGTH 13.320 LUMPCC 0 DR + +*CONN +*I mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 72.625 91.460 +*P chany_top_out[6] O *L 0.7423 *C 70.380 102.070 +*N chany_top_out[6]:2 *C 70.380 91.505 +*N chany_top_out[6]:3 *C 70.425 91.460 +*N chany_top_out[6]:4 *C 72.588 91.460 + +*CAP +0 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[6] 0.0006185165 +2 chany_top_out[6]:2 0.0006185165 +3 chany_top_out[6]:3 0.0002048298 +4 chany_top_out[6]:4 0.0002048298 + +*RES +0 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[6]:4 0.152 +1 chany_top_out[6]:4 chany_top_out[6]:3 0.001930804 +2 chany_top_out[6]:3 chany_top_out[6]:2 0.0045 +3 chany_top_out[6]:2 chany_top_out[6] 0.009433036 + +*END + +*D_NET chany_top_out[16] 0.0004419969 //LENGTH 4.575 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 85.620 99.280 +*P chany_top_out[16] O *L 0.7423 *C 86.940 102.070 +*N chany_top_out[16]:2 *C 86.940 99.325 +*N chany_top_out[16]:3 *C 86.895 99.280 +*N chany_top_out[16]:4 *C 85.657 99.280 + +*CAP +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[16] 0.0001342022 +2 chany_top_out[16]:2 0.0001342022 +3 chany_top_out[16]:3 8.629622e-05 +4 chany_top_out[16]:4 8.629622e-05 + +*RES +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[16]:4 0.152 +1 chany_top_out[16]:4 chany_top_out[16]:3 0.001104911 +2 chany_top_out[16]:3 chany_top_out[16]:2 0.0045 +3 chany_top_out[16]:2 chany_top_out[16] 0.002450893 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.003629935 //LENGTH 29.985 LUMPCC 9.403087e-05 DR + +*CONN +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 82.645 36.720 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 60.435 37.060 +*I mux_top_track_10\/mux_l1_in_0_:S I *L 0.00357 *C 56.940 39.440 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 56.940 39.440 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 57.040 39.100 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 60.215 39.100 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 60.260 39.055 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 60.435 37.060 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 60.260 37.400 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 60.260 37.400 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 60.260 36.778 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 60.268 36.720 +*N mux_tree_tapbuf_size2_0_sram[0]:12 *C 82.333 36.720 +*N mux_tree_tapbuf_size2_0_sram[0]:13 *C 82.340 36.720 +*N mux_tree_tapbuf_size2_0_sram[0]:14 *C 82.340 36.720 +*N mux_tree_tapbuf_size2_0_sram[0]:15 *C 82.645 36.720 + +*CAP +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_10\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 5.359355e-05 +4 mux_tree_tapbuf_size2_0_sram[0]:4 0.0002026002 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.000175907 +6 mux_tree_tapbuf_size2_0_sram[0]:6 0.0001063115 +7 mux_tree_tapbuf_size2_0_sram[0]:7 5.822519e-05 +8 mux_tree_tapbuf_size2_0_sram[0]:8 6.252048e-05 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0001862532 +10 mux_tree_tapbuf_size2_0_sram[0]:10 4.944056e-05 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.001251816 +12 mux_tree_tapbuf_size2_0_sram[0]:12 0.001251816 +13 mux_tree_tapbuf_size2_0_sram[0]:13 3.061863e-05 +14 mux_tree_tapbuf_size2_0_sram[0]:14 5.382352e-05 +15 mux_tree_tapbuf_size2_0_sram[0]:15 4.997923e-05 +16 mux_tree_tapbuf_size2_0_sram[0]:5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.701544e-05 +17 mux_tree_tapbuf_size2_0_sram[0]:4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.701544e-05 + +*RES +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.002834822 +2 mux_tree_tapbuf_size2_0_sram[0]:6 mux_tree_tapbuf_size2_0_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size2_0_sram[0]:3 mux_top_track_10\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.0001847826 +5 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:6 0.001477679 +7 mux_tree_tapbuf_size2_0_sram[0]:7 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0005558036 +9 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.00341 +10 mux_tree_tapbuf_size2_0_sram[0]:13 mux_tree_tapbuf_size2_0_sram[0]:12 0.00341 +11 mux_tree_tapbuf_size2_0_sram[0]:12 mux_tree_tapbuf_size2_0_sram[0]:11 0.00345685 +12 mux_tree_tapbuf_size2_0_sram[0]:14 mux_tree_tapbuf_size2_0_sram[0]:13 0.0045 +13 mux_tree_tapbuf_size2_0_sram[0]:15 mux_tree_tapbuf_size2_0_sram[0]:14 0.0001657609 +14 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.001883648 //LENGTH 15.880 LUMPCC 0 DR + +*CONN +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 75.285 31.620 +*I mem_top_track_12\/FTB_14__19:A I *L 0.001746 *C 70.840 36.720 +*I mux_top_track_12\/mux_l2_in_0_:S I *L 0.00357 *C 71.180 39.780 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 71.142 39.780 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 70.425 39.780 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 70.380 39.735 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 70.803 36.720 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 70.425 36.720 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 70.380 36.720 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 70.380 33.365 +*N mux_tree_tapbuf_size2_1_sram[1]:10 *C 70.425 33.320 +*N mux_tree_tapbuf_size2_1_sram[1]:11 *C 74.935 33.320 +*N mux_tree_tapbuf_size2_1_sram[1]:12 *C 74.980 33.275 +*N mux_tree_tapbuf_size2_1_sram[1]:13 *C 74.980 31.665 +*N mux_tree_tapbuf_size2_1_sram[1]:14 *C 74.980 31.620 +*N mux_tree_tapbuf_size2_1_sram[1]:15 *C 75.285 31.620 + +*CAP +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_12\/FTB_14__19:A 1e-06 +2 mux_top_track_12\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 6.083599e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:4 6.083599e-05 +5 mux_tree_tapbuf_size2_1_sram[1]:5 0.0001533967 +6 mux_tree_tapbuf_size2_1_sram[1]:6 3.993581e-05 +7 mux_tree_tapbuf_size2_1_sram[1]:7 3.993581e-05 +8 mux_tree_tapbuf_size2_1_sram[1]:8 0.0003682225 +9 mux_tree_tapbuf_size2_1_sram[1]:9 0.0001860752 +10 mux_tree_tapbuf_size2_1_sram[1]:10 0.0003307729 +11 mux_tree_tapbuf_size2_1_sram[1]:11 0.0003307729 +12 mux_tree_tapbuf_size2_1_sram[1]:12 0.0001030773 +13 mux_tree_tapbuf_size2_1_sram[1]:13 0.0001030773 +14 mux_tree_tapbuf_size2_1_sram[1]:14 5.202205e-05 +15 mux_tree_tapbuf_size2_1_sram[1]:15 5.168752e-05 + +*RES +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:3 mux_top_track_12\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[1]:4 mux_tree_tapbuf_size2_1_sram[1]:3 0.000640625 +3 mux_tree_tapbuf_size2_1_sram[1]:5 mux_tree_tapbuf_size2_1_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size2_1_sram[1]:9 mux_tree_tapbuf_size2_1_sram[1]:8 0.002995535 +6 mux_tree_tapbuf_size2_1_sram[1]:11 mux_tree_tapbuf_size2_1_sram[1]:10 0.004026786 +7 mux_tree_tapbuf_size2_1_sram[1]:12 mux_tree_tapbuf_size2_1_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size2_1_sram[1]:14 mux_tree_tapbuf_size2_1_sram[1]:13 0.0045 +9 mux_tree_tapbuf_size2_1_sram[1]:13 mux_tree_tapbuf_size2_1_sram[1]:12 0.0014375 +10 mux_tree_tapbuf_size2_1_sram[1]:15 mux_tree_tapbuf_size2_1_sram[1]:14 0.0001657609 +11 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.0003370536 +12 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.0045 +13 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:5 0.002691964 +14 mux_tree_tapbuf_size2_1_sram[1]:6 mem_top_track_12\/FTB_14__19:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[1] 0.001351177 //LENGTH 10.440 LUMPCC 0 DR + +*CONN +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.345 85.680 +*I mux_top_track_20\/mux_l2_in_0_:S I *L 0.00357 *C 79.020 82.960 +*I mem_top_track_20\/FTB_18__23:A I *L 0.001746 *C 82.800 80.240 +*N mux_tree_tapbuf_size2_5_sram[1]:3 *C 82.763 80.240 +*N mux_tree_tapbuf_size2_5_sram[1]:4 *C 80.085 80.240 +*N mux_tree_tapbuf_size2_5_sram[1]:5 *C 80.040 80.285 +*N mux_tree_tapbuf_size2_5_sram[1]:6 *C 79.058 82.960 +*N mux_tree_tapbuf_size2_5_sram[1]:7 *C 79.995 82.960 +*N mux_tree_tapbuf_size2_5_sram[1]:8 *C 80.040 82.960 +*N mux_tree_tapbuf_size2_5_sram[1]:9 *C 80.040 85.635 +*N mux_tree_tapbuf_size2_5_sram[1]:10 *C 80.040 85.680 +*N mux_tree_tapbuf_size2_5_sram[1]:11 *C 80.345 85.680 + +*CAP +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_20\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_20\/FTB_18__23:A 1e-06 +3 mux_tree_tapbuf_size2_5_sram[1]:3 0.0001941664 +4 mux_tree_tapbuf_size2_5_sram[1]:4 0.0001941664 +5 mux_tree_tapbuf_size2_5_sram[1]:5 0.0001615223 +6 mux_tree_tapbuf_size2_5_sram[1]:6 9.100298e-05 +7 mux_tree_tapbuf_size2_5_sram[1]:7 9.100298e-05 +8 mux_tree_tapbuf_size2_5_sram[1]:8 0.0003524236 +9 mux_tree_tapbuf_size2_5_sram[1]:9 0.0001579098 +10 mux_tree_tapbuf_size2_5_sram[1]:10 5.526003e-05 +11 mux_tree_tapbuf_size2_5_sram[1]:11 5.072202e-05 + +*RES +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_5_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_5_sram[1]:4 mux_tree_tapbuf_size2_5_sram[1]:3 0.002390625 +2 mux_tree_tapbuf_size2_5_sram[1]:5 mux_tree_tapbuf_size2_5_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_5_sram[1]:3 mem_top_track_20\/FTB_18__23:A 0.152 +4 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:6 0.0008370536 +5 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:5 0.002388393 +7 mux_tree_tapbuf_size2_5_sram[1]:6 mux_top_track_20\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_5_sram[1]:10 mux_tree_tapbuf_size2_5_sram[1]:9 0.0045 +9 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:8 0.002388393 +10 mux_tree_tapbuf_size2_5_sram[1]:11 mux_tree_tapbuf_size2_5_sram[1]:10 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_10_ccff_tail[0] 0.0007235103 //LENGTH 5.250 LUMPCC 0.0001396536 DR + +*CONN +*I mem_top_track_32\/FTB_23__28:X O *L 0 *C 52.215 79.900 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 50.775 77.180 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 *C 50.775 77.180 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 *C 50.600 77.180 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 *C 50.600 77.225 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 *C 50.600 79.855 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 *C 50.645 79.900 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 *C 52.178 79.900 + +*CAP +0 mem_top_track_32\/FTB_23__28:X 1e-06 +1 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 5.188786e-05 +3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 5.558085e-05 +4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 0.0001611756 +5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 0.0001611756 +6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 7.601838e-05 +7 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 7.601838e-05 +8 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 chany_top_in[7]:8 6.982678e-05 +9 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 chany_top_in[7]:7 6.982678e-05 + +*RES +0 mem_top_track_32\/FTB_23__28:X mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 0.001368304 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.002117626 //LENGTH 17.580 LUMPCC 0.0004486675 DR + +*CONN +*I mem_top_track_16\/FTB_16__21:X O *L 0 *C 47.605 75.480 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.095 91.460 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 47.095 91.460 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 46.920 91.460 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 46.920 91.415 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 46.920 75.525 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 46.965 75.480 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 47.568 75.480 + +*CAP +0 mem_top_track_16\/FTB_16__21:X 1e-06 +1 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 5.164516e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 5.384237e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0007205365 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0007205365 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 6.019917e-05 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 6.019917e-05 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_10_sram[1]:7 7.371695e-05 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_10_sram[1]:8 7.703927e-05 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_10_sram[1]:4 7.371695e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_10_sram[1]:7 7.703927e-05 +12 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 optlc_net_108:38 9.140816e-07 +13 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 optlc_net_108:43 3.601386e-05 +14 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 optlc_net_108:44 3.399182e-05 +15 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 optlc_net_108:39 2.657775e-06 +16 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 optlc_net_108:44 3.601386e-05 +17 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 optlc_net_108:35 2.657775e-06 +18 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 optlc_net_108:39 9.140816e-07 +19 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 optlc_net_108:40 3.399182e-05 + +*RES +0 mem_top_track_16\/FTB_16__21:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0141875 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_2_ccff_tail[0] 0.001035057 //LENGTH 8.330 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/FTB_11__16:X O *L 0 *C 35.645 45.560 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.815 49.980 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 *C 38.815 49.980 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 *C 38.640 49.980 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 *C 38.640 49.935 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 *C 38.640 45.605 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 *C 38.595 45.560 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 *C 35.683 45.560 + +*CAP +0 mem_left_track_9\/FTB_11__16:X 1e-06 +1 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 4.798231e-05 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 5.229145e-05 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.0002546897 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0002546897 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.0002117022 +7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.0002117022 + +*RES +0 mem_left_track_9\/FTB_11__16:X mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:6 0.002600447 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[0] 0.006983611 //LENGTH 55.720 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 19.165 34.000 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 13.975 66.300 +*I mux_left_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 26.320 69.360 +*I mux_left_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 24.280 72.080 +*N mux_tree_tapbuf_size5_2_sram[0]:4 *C 24.318 72.080 +*N mux_tree_tapbuf_size5_2_sram[0]:5 *C 25.715 72.080 +*N mux_tree_tapbuf_size5_2_sram[0]:6 *C 25.760 72.035 +*N mux_tree_tapbuf_size5_2_sram[0]:7 *C 26.283 69.360 +*N mux_tree_tapbuf_size5_2_sram[0]:8 *C 25.760 69.360 +*N mux_tree_tapbuf_size5_2_sram[0]:9 *C 25.760 69.700 +*N mux_tree_tapbuf_size5_2_sram[0]:10 *C 25.760 69.700 +*N mux_tree_tapbuf_size5_2_sram[0]:11 *C 25.760 66.345 +*N mux_tree_tapbuf_size5_2_sram[0]:12 *C 25.715 66.300 +*N mux_tree_tapbuf_size5_2_sram[0]:13 *C 14.013 66.300 +*N mux_tree_tapbuf_size5_2_sram[0]:14 *C 18.860 66.300 +*N mux_tree_tapbuf_size5_2_sram[0]:15 *C 18.860 66.255 +*N mux_tree_tapbuf_size5_2_sram[0]:16 *C 18.860 36.040 +*N mux_tree_tapbuf_size5_2_sram[0]:17 *C 18.400 36.040 +*N mux_tree_tapbuf_size5_2_sram[0]:18 *C 18.400 34.045 +*N mux_tree_tapbuf_size5_2_sram[0]:19 *C 18.445 34.000 +*N mux_tree_tapbuf_size5_2_sram[0]:20 *C 19.128 34.000 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_3\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_3\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_2_sram[0]:4 0.0001277081 +5 mux_tree_tapbuf_size5_2_sram[0]:5 0.0001277081 +6 mux_tree_tapbuf_size5_2_sram[0]:6 0.0001820614 +7 mux_tree_tapbuf_size5_2_sram[0]:7 6.286486e-05 +8 mux_tree_tapbuf_size5_2_sram[0]:8 9.586087e-05 +9 mux_tree_tapbuf_size5_2_sram[0]:9 7.293715e-05 +10 mux_tree_tapbuf_size5_2_sram[0]:10 0.0004701974 +11 mux_tree_tapbuf_size5_2_sram[0]:11 0.0002559103 +12 mux_tree_tapbuf_size5_2_sram[0]:12 0.0004875439 +13 mux_tree_tapbuf_size5_2_sram[0]:13 0.0003279489 +14 mux_tree_tapbuf_size5_2_sram[0]:14 0.000849165 +15 mux_tree_tapbuf_size5_2_sram[0]:15 0.001736173 +16 mux_tree_tapbuf_size5_2_sram[0]:16 0.00176665 +17 mux_tree_tapbuf_size5_2_sram[0]:17 0.0001654529 +18 mux_tree_tapbuf_size5_2_sram[0]:18 0.0001349764 +19 mux_tree_tapbuf_size5_2_sram[0]:19 5.822629e-05 +20 mux_tree_tapbuf_size5_2_sram[0]:20 5.822629e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_2_sram[0]:20 0.152 +1 mux_tree_tapbuf_size5_2_sram[0]:7 mux_left_track_3\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_2_sram[0]:9 mux_tree_tapbuf_size5_2_sram[0]:8 0.0003035715 +3 mux_tree_tapbuf_size5_2_sram[0]:10 mux_tree_tapbuf_size5_2_sram[0]:9 0.0045 +4 mux_tree_tapbuf_size5_2_sram[0]:10 mux_tree_tapbuf_size5_2_sram[0]:6 0.002084821 +5 mux_tree_tapbuf_size5_2_sram[0]:12 mux_tree_tapbuf_size5_2_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size5_2_sram[0]:11 mux_tree_tapbuf_size5_2_sram[0]:10 0.002995536 +7 mux_tree_tapbuf_size5_2_sram[0]:5 mux_tree_tapbuf_size5_2_sram[0]:4 0.001247768 +8 mux_tree_tapbuf_size5_2_sram[0]:6 mux_tree_tapbuf_size5_2_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size5_2_sram[0]:4 mux_left_track_3\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size5_2_sram[0]:13 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[0]:13 0.004328125 +12 mux_tree_tapbuf_size5_2_sram[0]:14 mux_tree_tapbuf_size5_2_sram[0]:12 0.006120536 +13 mux_tree_tapbuf_size5_2_sram[0]:15 mux_tree_tapbuf_size5_2_sram[0]:14 0.0045 +14 mux_tree_tapbuf_size5_2_sram[0]:19 mux_tree_tapbuf_size5_2_sram[0]:18 0.0045 +15 mux_tree_tapbuf_size5_2_sram[0]:18 mux_tree_tapbuf_size5_2_sram[0]:17 0.00178125 +16 mux_tree_tapbuf_size5_2_sram[0]:20 mux_tree_tapbuf_size5_2_sram[0]:19 0.000609375 +17 mux_tree_tapbuf_size5_2_sram[0]:8 mux_tree_tapbuf_size5_2_sram[0]:7 0.0004665179 +18 mux_tree_tapbuf_size5_2_sram[0]:17 mux_tree_tapbuf_size5_2_sram[0]:16 0.0004107143 +19 mux_tree_tapbuf_size5_2_sram[0]:16 mux_tree_tapbuf_size5_2_sram[0]:15 0.02697768 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[2] 0.001683302 //LENGTH 12.855 LUMPCC 0.0004622346 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 30.205 42.500 +*I mem_left_track_5\/FTB_4__9:A I *L 0.001746 *C 30.360 44.880 +*I mux_left_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 20.800 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:3 *C 20.838 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:4 *C 30.323 44.880 +*N mux_tree_tapbuf_size6_3_sram[2]:5 *C 30.360 44.835 +*N mux_tree_tapbuf_size6_3_sram[2]:6 *C 30.360 42.545 +*N mux_tree_tapbuf_size6_3_sram[2]:7 *C 30.360 42.500 +*N mux_tree_tapbuf_size6_3_sram[2]:8 *C 30.205 42.500 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_5\/FTB_4__9:A 1e-06 +2 mux_left_track_5\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_3_sram[2]:3 0.0003896432 +4 mux_tree_tapbuf_size6_3_sram[2]:4 0.0003896432 +5 mux_tree_tapbuf_size6_3_sram[2]:5 0.0001631604 +6 mux_tree_tapbuf_size6_3_sram[2]:6 0.0001631604 +7 mux_tree_tapbuf_size6_3_sram[2]:7 5.845721e-05 +8 mux_tree_tapbuf_size6_3_sram[2]:8 5.400259e-05 +9 mux_tree_tapbuf_size6_3_sram[2]:3 chany_top_in[5]:10 0.0001637995 +10 mux_tree_tapbuf_size6_3_sram[2]:4 chany_top_in[5]:11 0.0001637995 +11 mux_tree_tapbuf_size6_3_sram[2]:5 chany_top_in[5]:13 3.237508e-07 +12 mux_tree_tapbuf_size6_3_sram[2]:6 chany_top_in[5]:12 3.237508e-07 +13 mux_tree_tapbuf_size6_3_sram[2]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.699409e-05 +14 mux_tree_tapbuf_size6_3_sram[2]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.699409e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_3_sram[2]:8 0.152 +1 mux_tree_tapbuf_size6_3_sram[2]:3 mux_left_track_5\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_3_sram[2]:4 mem_left_track_5\/FTB_4__9:A 0.152 +3 mux_tree_tapbuf_size6_3_sram[2]:4 mux_tree_tapbuf_size6_3_sram[2]:3 0.00846875 +4 mux_tree_tapbuf_size6_3_sram[2]:5 mux_tree_tapbuf_size6_3_sram[2]:4 0.0045 +5 mux_tree_tapbuf_size6_3_sram[2]:7 mux_tree_tapbuf_size6_3_sram[2]:6 0.0045 +6 mux_tree_tapbuf_size6_3_sram[2]:6 mux_tree_tapbuf_size6_3_sram[2]:5 0.002044643 +7 mux_tree_tapbuf_size6_3_sram[2]:8 mux_tree_tapbuf_size6_3_sram[2]:7 8.423915e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00119424 //LENGTH 10.865 LUMPCC 0.000215176 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_2_:X O *L 0 *C 80.675 48.280 +*I mux_top_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 81.520 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 81.483 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 80.085 56.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.040 56.055 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 80.040 48.325 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 80.085 48.280 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 80.638 48.280 + +*CAP +0 mux_top_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001165598 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001165598 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003145474 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003145474 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.742493e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.742493e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 top_right_grid_pin_1_[0]:15 0.0001072903 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 top_right_grid_pin_1_[0]:10 2.977472e-07 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 top_right_grid_pin_1_[0]:11 0.0001072903 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 top_right_grid_pin_1_[0]:9 2.977472e-07 + +*RES +0 mux_top_track_4\/mux_l1_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001247768 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.006901786 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.002154162 //LENGTH 17.810 LUMPCC 0.0004264578 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_1_:X O *L 0 *C 58.705 55.080 +*I mux_top_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 65.955 64.260 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 65.955 64.260 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 65.780 64.260 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 65.780 64.215 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 65.780 58.185 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 65.735 58.140 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 61.225 58.140 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 61.180 58.095 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 61.180 55.125 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 61.135 55.080 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 58.742 55.080 + +*CAP +0 mux_top_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.05317e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.302884e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002431071 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002431071 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002633905 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002633905 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001662637 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001662637 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001383104 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001383104 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_0_sram[1]:13 1.670088e-06 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_0_sram[1]:12 1.670088e-06 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size5_0_sram[1]:6 1.482558e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_tree_tapbuf_size5_0_sram[1]:8 8.174969e-06 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_tree_tapbuf_size5_0_sram[1]:10 6.117046e-05 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size5_0_sram[1]:7 1.482558e-05 +18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_tree_tapbuf_size5_0_sram[1]:4 8.174969e-06 +19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_tree_tapbuf_size5_0_sram[1]:9 6.117046e-05 +20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.346003e-05 +21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.346003e-05 +22 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.344435e-05 +23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.344435e-05 +24 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.833728e-07 +25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.833728e-07 + +*RES +0 mux_top_track_2\/mux_l2_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.510871e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005383929 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.004026786 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.002651786 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.002136161 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.005152908 //LENGTH 54.055 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 86.765 42.840 +*I mux_top_track_8\/BUFT_RR_43:A I *L 0.001776 *C 96.600 85.680 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 96.562 85.680 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 94.805 85.680 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 94.760 85.635 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 94.760 44.925 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 94.715 44.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 86.985 44.880 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 86.940 44.835 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 86.940 42.885 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 86.940 42.840 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 86.765 42.840 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/BUFT_RR_43:A 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001180469 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001180469 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001892838 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001892838 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003889766 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003889766 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001231585 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001231585 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 4.782679e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 5.704181e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 9.51087e-05 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001741071 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.006901786 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.03634822 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001569197 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_8\/BUFT_RR_43:A 0.152 + +*END + +*D_NET optlc_net_109 0.007746248 //LENGTH 55.930 LUMPCC 0.0007555618 DR + +*CONN +*I optlc_103:HI O *L 0 *C 28.980 64.260 +*I mux_left_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.180 64.260 +*I mux_left_track_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 9.950 59.160 +*I mux_left_track_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 9.540 69.700 +*I mux_left_track_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 30.650 59.160 +*I mux_left_track_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 34.790 69.700 +*I mux_left_track_27\/mux_l2_in_0_:A0 I *L 0.001631 *C 35.250 64.260 +*N optlc_net_109:7 *C 35.250 64.260 +*N optlc_net_109:8 *C 34.790 69.700 +*N optlc_net_109:9 *C 34.960 69.700 +*N optlc_net_109:10 *C 34.960 69.655 +*N optlc_net_109:11 *C 34.960 64.645 +*N optlc_net_109:12 *C 35.005 64.593 +*N optlc_net_109:13 *C 30.360 64.600 +*N optlc_net_109:14 *C 30.650 59.160 +*N optlc_net_109:15 *C 9.540 69.700 +*N optlc_net_109:16 *C 9.660 69.360 +*N optlc_net_109:17 *C 9.660 69.315 +*N optlc_net_109:18 *C 9.660 59.205 +*N optlc_net_109:19 *C 9.660 59.160 +*N optlc_net_109:20 *C 9.988 59.160 +*N optlc_net_109:21 *C 30.315 59.160 +*N optlc_net_109:22 *C 30.360 59.205 +*N optlc_net_109:23 *C 30.360 63.875 +*N optlc_net_109:24 *C 30.360 63.950 +*N optlc_net_109:25 *C 25.203 64.233 +*N optlc_net_109:26 *C 25.215 63.920 +*N optlc_net_109:27 *C 28.980 63.920 +*N optlc_net_109:28 *C 28.980 64.260 + +*CAP +0 optlc_103:HI 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_15\/mux_l2_in_0_:A0 1e-06 +3 mux_left_track_13\/mux_l2_in_0_:A0 1e-06 +4 mux_left_track_7\/mux_l2_in_1_:A0 1e-06 +5 mux_left_track_11\/mux_l2_in_0_:A0 1e-06 +6 mux_left_track_27\/mux_l2_in_0_:A0 1e-06 +7 optlc_net_109:7 6.651952e-05 +8 optlc_net_109:8 5.511507e-05 +9 optlc_net_109:9 6.093536e-05 +10 optlc_net_109:10 0.0003289255 +11 optlc_net_109:11 0.0003289255 +12 optlc_net_109:12 0.0003919455 +13 optlc_net_109:13 0.0004055198 +14 optlc_net_109:14 5.753488e-05 +15 optlc_net_109:15 6.623797e-05 +16 optlc_net_109:16 7.1601e-05 +17 optlc_net_109:17 0.0005987996 +18 optlc_net_109:18 0.0005987996 +19 optlc_net_109:19 5.136082e-05 +20 optlc_net_109:20 0.00115503 +21 optlc_net_109:21 0.001159571 +22 optlc_net_109:22 0.0003435343 +23 optlc_net_109:23 0.0003435343 +24 optlc_net_109:24 0.000144444 +25 optlc_net_109:25 3.452366e-05 +26 optlc_net_109:26 0.0002866344 +27 optlc_net_109:27 0.0003769885 +28 optlc_net_109:28 5.720567e-05 +29 optlc_net_109:17 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001219061 +30 optlc_net_109:18 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001219061 +31 optlc_net_109:21 ropt_net_118:7 0.0002510961 +32 optlc_net_109:19 ropt_net_118:6 4.778648e-06 +33 optlc_net_109:20 ropt_net_118:6 0.0002510961 +34 optlc_net_109:20 ropt_net_118:7 4.778648e-06 + +*RES +0 optlc_103:HI optlc_net_109:28 0.152 +1 optlc_net_109:25 mux_left_track_3\/mux_l2_in_1_:A0 0.152 +2 optlc_net_109:7 mux_left_track_27\/mux_l2_in_0_:A0 0.152 +3 optlc_net_109:12 optlc_net_109:11 0.0045 +4 optlc_net_109:12 optlc_net_109:7 0.0001807065 +5 optlc_net_109:11 optlc_net_109:10 0.004473215 +6 optlc_net_109:9 optlc_net_109:8 9.239131e-05 +7 optlc_net_109:10 optlc_net_109:9 0.0045 +8 optlc_net_109:8 mux_left_track_11\/mux_l2_in_0_:A0 0.152 +9 optlc_net_109:21 optlc_net_109:20 0.01814955 +10 optlc_net_109:21 optlc_net_109:14 0.0001820652 +11 optlc_net_109:22 optlc_net_109:21 0.0045 +12 optlc_net_109:24 optlc_net_109:23 0.0045 +13 optlc_net_109:24 optlc_net_109:13 0.0005803572 +14 optlc_net_109:23 optlc_net_109:22 0.004169643 +15 optlc_net_109:28 optlc_net_109:27 0.0003035715 +16 optlc_net_109:14 mux_left_track_7\/mux_l2_in_1_:A0 0.152 +17 optlc_net_109:15 mux_left_track_13\/mux_l2_in_0_:A0 0.152 +18 optlc_net_109:16 optlc_net_109:15 0.0001976744 +19 optlc_net_109:17 optlc_net_109:16 0.0045 +20 optlc_net_109:19 optlc_net_109:18 0.0045 +21 optlc_net_109:18 optlc_net_109:17 0.009026786 +22 optlc_net_109:20 mux_left_track_15\/mux_l2_in_0_:A0 0.152 +23 optlc_net_109:20 optlc_net_109:19 0.0001779891 +24 optlc_net_109:26 optlc_net_109:25 0.0002111487 +25 optlc_net_109:27 optlc_net_109:26 0.003361607 +26 optlc_net_109:27 optlc_net_109:24 0.001232143 +27 optlc_net_109:13 optlc_net_109:12 0.004147321 + +*END + +*D_NET ropt_net_133 0.0007176099 //LENGTH 5.040 LUMPCC 0.0001031282 DR + +*CONN +*I ropt_mt_inst_726:X O *L 0 *C 4.140 42.840 +*I ropt_mt_inst_738:A I *L 0.001766 *C 7.820 42.160 +*N ropt_net_133:2 *C 7.783 42.160 +*N ropt_net_133:3 *C 7.095 42.160 +*N ropt_net_133:4 *C 7.095 42.500 +*N ropt_net_133:5 *C 4.140 42.500 +*N ropt_net_133:6 *C 4.140 42.840 + +*CAP +0 ropt_mt_inst_726:X 1e-06 +1 ropt_mt_inst_738:A 1e-06 +2 ropt_net_133:2 5.288878e-05 +3 ropt_net_133:3 8.623648e-05 +4 ropt_net_133:4 0.0002138643 +5 ropt_net_133:5 0.0002065983 +6 ropt_net_133:6 5.28938e-05 +7 ropt_net_133:2 optlc_net_107:13 5.795454e-06 +8 ropt_net_133:5 optlc_net_107:14 4.576866e-05 +9 ropt_net_133:4 optlc_net_107:13 4.576866e-05 +10 ropt_net_133:3 optlc_net_107:14 5.795454e-06 + +*RES +0 ropt_mt_inst_726:X ropt_net_133:6 0.152 +1 ropt_net_133:2 ropt_mt_inst_738:A 0.152 +2 ropt_net_133:6 ropt_net_133:5 0.0003035715 +3 ropt_net_133:5 ropt_net_133:4 0.002638393 +4 ropt_net_133:4 ropt_net_133:3 0.0003035715 +5 ropt_net_133:3 ropt_net_133:2 0.0006138393 + +*END + +*D_NET chany_top_out[0] 0.000589432 //LENGTH 4.415 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 78.660 99.960 +*P chany_top_out[0] O *L 0.7423 *C 76.820 102.340 +*N chany_top_out[0]:2 *C 76.820 100.005 +*N chany_top_out[0]:3 *C 76.865 99.960 +*N chany_top_out[0]:4 *C 78.623 99.960 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 chany_top_out[0] 0.0001275197 +2 chany_top_out[0]:2 0.0001275197 +3 chany_top_out[0]:3 0.0001666963 +4 chany_top_out[0]:4 0.0001666963 + +*RES +0 ropt_mt_inst_735:X chany_top_out[0]:4 0.152 +1 chany_top_out[0]:4 chany_top_out[0]:3 0.001569197 +2 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +3 chany_top_out[0]:2 chany_top_out[0] 0.00184375 + +*END + +*D_NET chany_top_in[3] 0.01871177 //LENGTH 132.960 LUMPCC 0.006227944 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 74.060 102.070 +*I ropt_mt_inst_726:A I *L 0.001767 *C 3.220 42.160 +*N chany_top_in[3]:2 *C 3.220 42.160 +*N chany_top_in[3]:3 *C 3.220 42.205 +*N chany_top_in[3]:4 *C 3.220 50.955 +*N chany_top_in[3]:5 *C 3.265 51.000 +*N chany_top_in[3]:6 *C 20.195 51.000 +*N chany_top_in[3]:7 *C 20.240 51.045 +*N chany_top_in[3]:8 *C 20.240 55.023 +*N chany_top_in[3]:9 *C 20.248 55.080 +*N chany_top_in[3]:10 *C 72.660 55.080 +*N chany_top_in[3]:11 *C 72.680 55.088 +*N chany_top_in[3]:12 *C 72.680 89.752 +*N chany_top_in[3]:13 *C 72.700 89.760 +*N chany_top_in[3]:14 *C 74.053 89.760 +*N chany_top_in[3]:15 *C 74.060 89.818 + +*CAP +0 chany_top_in[3] 0.0006189808 +1 ropt_mt_inst_726:A 1e-06 +2 chany_top_in[3]:2 3.119741e-05 +3 chany_top_in[3]:3 0.0004651129 +4 chany_top_in[3]:4 0.0004651129 +5 chany_top_in[3]:5 0.001225295 +6 chany_top_in[3]:6 0.001225295 +7 chany_top_in[3]:7 0.0002283948 +8 chany_top_in[3]:8 0.0002283948 +9 chany_top_in[3]:9 0.00197113 +10 chany_top_in[3]:10 0.00197113 +11 chany_top_in[3]:11 0.001537661 +12 chany_top_in[3]:12 0.001537661 +13 chany_top_in[3]:13 0.0001792389 +14 chany_top_in[3]:14 0.0001792389 +15 chany_top_in[3]:15 0.0006189808 +16 chany_top_in[3] chany_top_in[6] 2.333784e-05 +17 chany_top_in[3]:11 chany_top_in[6]:17 0.0003768706 +18 chany_top_in[3]:11 chany_top_in[6]:18 0.0003652919 +19 chany_top_in[3]:12 chany_top_in[6]:19 0.0003652919 +20 chany_top_in[3]:12 chany_top_in[6]:18 0.0003768706 +21 chany_top_in[3]:15 chany_top_in[6]:22 2.333784e-05 +22 chany_top_in[3] prog_clk[0]:140 8.026067e-05 +23 chany_top_in[3]:3 prog_clk[0]:405 7.206642e-05 +24 chany_top_in[3]:5 prog_clk[0]:434 1.295163e-05 +25 chany_top_in[3]:4 prog_clk[0]:408 7.206642e-05 +26 chany_top_in[3]:6 prog_clk[0]:438 1.295163e-05 +27 chany_top_in[3]:9 prog_clk[0]:381 0.000145638 +28 chany_top_in[3]:10 prog_clk[0]:382 0.000145638 +29 chany_top_in[3]:15 prog_clk[0]:139 8.026067e-05 +30 chany_top_in[3]:9 chany_top_in[0]:6 0.0006582707 +31 chany_top_in[3]:10 chany_top_in[0]:7 0.0006582707 +32 chany_top_in[3]:9 chany_top_in[18]:5 0.0009619963 +33 chany_top_in[3]:10 chany_top_in[18]:6 0.0009619963 +34 chany_top_in[3]:7 left_top_grid_pin_42_[0]:20 5.214449e-07 +35 chany_top_in[3]:7 left_top_grid_pin_42_[0]:23 7.09035e-08 +36 chany_top_in[3]:8 left_top_grid_pin_42_[0]:24 7.09035e-08 +37 chany_top_in[3]:8 left_top_grid_pin_42_[0]:23 5.214449e-07 +38 chany_top_in[3]:9 left_top_grid_pin_42_[0]:19 0.0002724328 +39 chany_top_in[3]:10 left_top_grid_pin_42_[0]:18 0.0002724328 +40 chany_top_in[3]:9 mux_tree_tapbuf_size5_3_sram[2]:10 0.000144263 +41 chany_top_in[3]:10 mux_tree_tapbuf_size5_3_sram[2]:11 0.000144263 + +*RES +0 chany_top_in[3] chany_top_in[3]:15 0.01093973 +1 chany_top_in[3]:2 ropt_mt_inst_726:A 0.152 +2 chany_top_in[3]:3 chany_top_in[3]:2 0.0045 +3 chany_top_in[3]:5 chany_top_in[3]:4 0.0045 +4 chany_top_in[3]:4 chany_top_in[3]:3 0.0078125 +5 chany_top_in[3]:6 chany_top_in[3]:5 0.01511607 +6 chany_top_in[3]:7 chany_top_in[3]:6 0.0045 +7 chany_top_in[3]:8 chany_top_in[3]:7 0.003551339 +8 chany_top_in[3]:9 chany_top_in[3]:8 0.00341 +9 chany_top_in[3]:10 chany_top_in[3]:9 0.008211291 +10 chany_top_in[3]:11 chany_top_in[3]:10 0.00341 +11 chany_top_in[3]:13 chany_top_in[3]:12 0.00341 +12 chany_top_in[3]:12 chany_top_in[3]:11 0.00543085 +13 chany_top_in[3]:15 chany_top_in[3]:14 0.00341 +14 chany_top_in[3]:14 chany_top_in[3]:13 0.0002118916 + +*END + +*D_NET chany_top_in[15] 0.007211084 //LENGTH 53.855 LUMPCC 0.001904743 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 53.820 102.070 +*I mux_left_track_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 37.625 66.980 +*N chany_top_in[15]:2 *C 37.625 66.980 +*N chany_top_in[15]:3 *C 37.720 66.640 +*N chany_top_in[15]:4 *C 43.655 66.640 +*N chany_top_in[15]:5 *C 43.700 66.685 +*N chany_top_in[15]:6 *C 43.700 69.303 +*N chany_top_in[15]:7 *C 43.708 69.360 +*N chany_top_in[15]:8 *C 48.740 69.360 +*N chany_top_in[15]:9 *C 48.760 69.368 +*N chany_top_in[15]:10 *C 48.760 100.633 +*N chany_top_in[15]:11 *C 48.780 100.640 +*N chany_top_in[15]:12 *C 53.812 100.640 +*N chany_top_in[15]:13 *C 53.820 100.698 + +*CAP +0 chany_top_in[15] 8.851926e-05 +1 mux_left_track_11\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[15]:2 5.716372e-05 +3 chany_top_in[15]:3 0.0003849182 +4 chany_top_in[15]:4 0.0003571141 +5 chany_top_in[15]:5 0.0001667245 +6 chany_top_in[15]:6 0.0001667245 +7 chany_top_in[15]:7 0.0003944458 +8 chany_top_in[15]:8 0.0003944458 +9 chany_top_in[15]:9 0.001155031 +10 chany_top_in[15]:10 0.001155031 +11 chany_top_in[15]:11 0.0004483513 +12 chany_top_in[15]:12 0.0004483513 +13 chany_top_in[15]:13 8.851926e-05 +14 chany_top_in[15]:9 chany_top_in[11]:7 0.000295827 +15 chany_top_in[15]:10 chany_top_in[11]:8 0.000295827 +16 chany_top_in[15]:9 chany_top_out[7]:6 0.0006101648 +17 chany_top_in[15]:11 chany_top_out[7]:3 4.638002e-05 +18 chany_top_in[15]:10 chany_top_out[7]:5 0.0006101648 +19 chany_top_in[15]:12 chany_top_out[7]:4 4.638002e-05 + +*RES +0 chany_top_in[15] chany_top_in[15]:13 0.001225446 +1 chany_top_in[15]:2 mux_left_track_11\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[15]:4 chany_top_in[15]:3 0.005299107 +3 chany_top_in[15]:5 chany_top_in[15]:4 0.0045 +4 chany_top_in[15]:6 chany_top_in[15]:5 0.002337054 +5 chany_top_in[15]:7 chany_top_in[15]:6 0.00341 +6 chany_top_in[15]:8 chany_top_in[15]:7 0.000788425 +7 chany_top_in[15]:9 chany_top_in[15]:8 0.00341 +8 chany_top_in[15]:11 chany_top_in[15]:10 0.00341 +9 chany_top_in[15]:10 chany_top_in[15]:9 0.004898183 +10 chany_top_in[15]:13 chany_top_in[15]:12 0.00341 +11 chany_top_in[15]:12 chany_top_in[15]:11 0.000788425 +12 chany_top_in[15]:3 chany_top_in[15]:2 0.0003035715 + +*END + +*D_NET chany_top_in[16] 0.0113384 //LENGTH 83.015 LUMPCC 0.004459383 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 69.460 102.070 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 43.145 47.260 +*N chany_top_in[16]:2 *C 43.145 47.260 +*N chany_top_in[16]:3 *C 43.240 47.600 +*N chany_top_in[16]:4 *C 50.555 47.600 +*N chany_top_in[16]:5 *C 50.600 47.645 +*N chany_top_in[16]:6 *C 50.600 48.223 +*N chany_top_in[16]:7 *C 50.608 48.280 +*N chany_top_in[16]:8 *C 61.620 48.280 +*N chany_top_in[16]:9 *C 61.640 48.288 +*N chany_top_in[16]:10 *C 61.640 97.233 +*N chany_top_in[16]:11 *C 61.660 97.240 +*N chany_top_in[16]:12 *C 69.453 97.240 +*N chany_top_in[16]:13 *C 69.460 97.297 + +*CAP +0 chany_top_in[16] 0.0002717747 +1 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[16]:2 5.98e-05 +3 chany_top_in[16]:3 0.0004479325 +4 chany_top_in[16]:4 0.000418554 +5 chany_top_in[16]:5 5.358801e-05 +6 chany_top_in[16]:6 5.358801e-05 +7 chany_top_in[16]:7 0.0005393576 +8 chany_top_in[16]:8 0.0005393576 +9 chany_top_in[16]:9 0.001625843 +10 chany_top_in[16]:10 0.001625843 +11 chany_top_in[16]:11 0.000485301 +12 chany_top_in[16]:12 0.000485301 +13 chany_top_in[16]:13 0.0002717747 +14 chany_top_in[16]:9 chany_top_in[5]:20 0.0003789556 +15 chany_top_in[16]:10 chany_top_in[5]:21 0.0003789556 +16 chany_top_in[16] chany_top_in[9] 4.635266e-06 +17 chany_top_in[16]:9 chany_top_in[9]:9 0.0006481193 +18 chany_top_in[16]:9 chany_top_in[9]:10 0.0003440182 +19 chany_top_in[16]:11 chany_top_in[9]:12 7.980349e-05 +20 chany_top_in[16]:10 chany_top_in[9]:10 0.0006481193 +21 chany_top_in[16]:10 chany_top_in[9]:11 0.0003440182 +22 chany_top_in[16]:13 chany_top_in[9]:14 4.635266e-06 +23 chany_top_in[16]:12 chany_top_in[9]:13 7.980349e-05 +24 chany_top_in[16]:5 mux_tree_tapbuf_size2_2_sram[0]:9 1.418382e-06 +25 chany_top_in[16]:6 mux_tree_tapbuf_size2_2_sram[0]:8 1.418382e-06 +26 chany_top_in[16]:7 mux_tree_tapbuf_size2_2_sram[0]:10 0.0006238302 +27 chany_top_in[16]:8 mux_tree_tapbuf_size2_2_sram[0]:11 0.0006238302 +28 chany_top_in[16]:11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001489114 +29 chany_top_in[16]:12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001489114 + +*RES +0 chany_top_in[16] chany_top_in[16]:13 0.004261161 +1 chany_top_in[16]:2 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[16]:4 chany_top_in[16]:3 0.00653125 +3 chany_top_in[16]:5 chany_top_in[16]:4 0.0045 +4 chany_top_in[16]:6 chany_top_in[16]:5 0.000515625 +5 chany_top_in[16]:7 chany_top_in[16]:6 0.00341 +6 chany_top_in[16]:8 chany_top_in[16]:7 0.001725292 +7 chany_top_in[16]:9 chany_top_in[16]:8 0.00341 +8 chany_top_in[16]:11 chany_top_in[16]:10 0.00341 +9 chany_top_in[16]:10 chany_top_in[16]:9 0.007668049 +10 chany_top_in[16]:13 chany_top_in[16]:12 0.00341 +11 chany_top_in[16]:12 chany_top_in[16]:11 0.001220825 +12 chany_top_in[16]:3 chany_top_in[16]:2 0.0003035714 + +*END + +*D_NET chany_top_in[17] 0.01214637 //LENGTH 86.645 LUMPCC 0.005215969 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 81.420 102.070 +*I mux_left_track_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 31.740 66.980 +*N chany_top_in[17]:2 *C 31.777 66.980 +*N chany_top_in[17]:3 *C 35.375 66.980 +*N chany_top_in[17]:4 *C 35.420 67.025 +*N chany_top_in[17]:5 *C 35.420 71.343 +*N chany_top_in[17]:6 *C 35.428 71.400 +*N chany_top_in[17]:7 *C 80.020 71.400 +*N chany_top_in[17]:8 *C 80.040 71.407 +*N chany_top_in[17]:9 *C 80.040 100.633 +*N chany_top_in[17]:10 *C 80.060 100.640 +*N chany_top_in[17]:11 *C 81.413 100.640 +*N chany_top_in[17]:12 *C 81.420 100.698 + +*CAP +0 chany_top_in[17] 7.538313e-05 +1 mux_left_track_7\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[17]:2 0.0002026793 +3 chany_top_in[17]:3 0.0002026793 +4 chany_top_in[17]:4 0.000316538 +5 chany_top_in[17]:5 0.000316538 +6 chany_top_in[17]:6 0.002186557 +7 chany_top_in[17]:7 0.002186557 +8 chany_top_in[17]:8 0.000567045 +9 chany_top_in[17]:9 0.000567045 +10 chany_top_in[17]:10 0.0001164978 +11 chany_top_in[17]:11 0.0001164978 +12 chany_top_in[17]:12 7.538313e-05 +13 chany_top_in[17] chany_top_in[2] 1.818107e-05 +14 chany_top_in[17]:8 chany_top_in[2]:15 0.000437237 +15 chany_top_in[17]:8 chany_top_in[2]:16 0.0001916766 +16 chany_top_in[17]:9 chany_top_in[2]:16 0.000437237 +17 chany_top_in[17]:9 chany_top_in[2]:17 0.0001916766 +18 chany_top_in[17]:12 chany_top_in[2]:20 1.818107e-05 +19 chany_top_in[17]:6 top_left_grid_pin_38_[0]:18 0.0005593937 +20 chany_top_in[17]:7 top_left_grid_pin_38_[0]:17 0.0005593937 +21 chany_top_in[17]:8 chany_top_out[2]:6 0.0006372764 +22 chany_top_in[17]:9 chany_top_out[2]:5 0.0006372764 +23 chany_top_in[17]:4 mux_tree_tapbuf_size2_14_sram[1]:8 4.822256e-06 +24 chany_top_in[17]:5 mux_tree_tapbuf_size2_14_sram[1]:9 4.822256e-06 +25 chany_top_in[17]:6 mux_tree_tapbuf_size2_14_sram[1]:10 0.0001278708 +26 chany_top_in[17]:7 mux_tree_tapbuf_size2_14_sram[1]:11 0.0001278708 +27 chany_top_in[17]:6 optlc_net_108:55 0.0003718095 +28 chany_top_in[17]:6 optlc_net_108:54 0.0001938291 +29 chany_top_in[17]:7 optlc_net_108:55 0.0001938291 +30 chany_top_in[17]:7 optlc_net_108:50 0.0003718095 +31 chany_top_in[17]:2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.279829e-05 +32 chany_top_in[17]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.279829e-05 +33 chany_top_in[17]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.090119e-06 +34 chany_top_in[17]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.090119e-06 + +*RES +0 chany_top_in[17] chany_top_in[17]:12 0.001225446 +1 chany_top_in[17]:2 mux_left_track_7\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[17]:3 chany_top_in[17]:2 0.003212054 +3 chany_top_in[17]:4 chany_top_in[17]:3 0.0045 +4 chany_top_in[17]:5 chany_top_in[17]:4 0.003854911 +5 chany_top_in[17]:6 chany_top_in[17]:5 0.00341 +6 chany_top_in[17]:7 chany_top_in[17]:6 0.006986158 +7 chany_top_in[17]:8 chany_top_in[17]:7 0.00341 +8 chany_top_in[17]:10 chany_top_in[17]:9 0.00341 +9 chany_top_in[17]:9 chany_top_in[17]:8 0.004578583 +10 chany_top_in[17]:12 chany_top_in[17]:11 0.00341 +11 chany_top_in[17]:11 chany_top_in[17]:10 0.0002118917 + +*END + +*D_NET top_left_grid_pin_35_[0] 0.01174 //LENGTH 91.435 LUMPCC 0.001926783 DR + +*CONN +*P top_left_grid_pin_35_[0] I *L 0.29796 *C 30.820 102.035 +*I mux_top_track_26\/mux_l1_in_0_:A1 I *L 0.00198 *C 52.080 88.740 +*I mux_top_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 53.000 61.540 +*I mux_top_track_6\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.760 52.700 +*I mux_top_track_10\/mux_l1_in_0_:A1 I *L 0.00198 *C 56.220 39.780 +*N top_left_grid_pin_35_[0]:5 *C 56.183 39.780 +*N top_left_grid_pin_35_[0]:6 *C 55.705 39.780 +*N top_left_grid_pin_35_[0]:7 *C 55.660 39.825 +*N top_left_grid_pin_35_[0]:8 *C 55.660 52.700 +*N top_left_grid_pin_35_[0]:9 *C 55.660 52.700 +*N top_left_grid_pin_35_[0]:10 *C 55.660 61.835 +*N top_left_grid_pin_35_[0]:11 *C 55.615 61.880 +*N top_left_grid_pin_35_[0]:12 *C 53.000 61.540 +*N top_left_grid_pin_35_[0]:13 *C 52.968 61.880 +*N top_left_grid_pin_35_[0]:14 *C 52.900 61.925 +*N top_left_grid_pin_35_[0]:15 *C 52.900 88.355 +*N top_left_grid_pin_35_[0]:16 *C 52.900 88.400 +*N top_left_grid_pin_35_[0]:17 *C 52.900 88.740 +*N top_left_grid_pin_35_[0]:18 *C 52.080 88.740 +*N top_left_grid_pin_35_[0]:19 *C 49.265 88.740 +*N top_left_grid_pin_35_[0]:20 *C 49.220 88.785 +*N top_left_grid_pin_35_[0]:21 *C 49.220 96.502 +*N top_left_grid_pin_35_[0]:22 *C 49.213 96.560 +*N top_left_grid_pin_35_[0]:23 *C 33.587 96.560 +*N top_left_grid_pin_35_[0]:24 *C 33.580 96.618 +*N top_left_grid_pin_35_[0]:25 *C 33.580 101.275 +*N top_left_grid_pin_35_[0]:26 *C 33.535 101.320 +*N top_left_grid_pin_35_[0]:27 *C 30.865 101.320 +*N top_left_grid_pin_35_[0]:28 *C 30.820 101.365 + +*CAP +0 top_left_grid_pin_35_[0] 5.033254e-05 +1 mux_top_track_26\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_2\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_10\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_35_[0]:5 5.47776e-05 +6 top_left_grid_pin_35_[0]:6 5.47776e-05 +7 top_left_grid_pin_35_[0]:7 0.000711787 +8 top_left_grid_pin_35_[0]:8 3.520168e-05 +9 top_left_grid_pin_35_[0]:9 0.001255566 +10 top_left_grid_pin_35_[0]:10 0.0005125706 +11 top_left_grid_pin_35_[0]:11 0.0001838726 +12 top_left_grid_pin_35_[0]:12 6.000193e-05 +13 top_left_grid_pin_35_[0]:13 0.000216607 +14 top_left_grid_pin_35_[0]:14 0.000972808 +15 top_left_grid_pin_35_[0]:15 0.000972808 +16 top_left_grid_pin_35_[0]:16 6.094409e-05 +17 top_left_grid_pin_35_[0]:17 9.808589e-05 +18 top_left_grid_pin_35_[0]:18 0.00033631 +19 top_left_grid_pin_35_[0]:19 0.0002446115 +20 top_left_grid_pin_35_[0]:20 0.0004352679 +21 top_left_grid_pin_35_[0]:21 0.0004352679 +22 top_left_grid_pin_35_[0]:22 0.001007069 +23 top_left_grid_pin_35_[0]:23 0.001007069 +24 top_left_grid_pin_35_[0]:24 0.0003205829 +25 top_left_grid_pin_35_[0]:25 0.0003205829 +26 top_left_grid_pin_35_[0]:26 0.0002059934 +27 top_left_grid_pin_35_[0]:27 0.0002059934 +28 top_left_grid_pin_35_[0]:28 5.033254e-05 +29 top_left_grid_pin_35_[0]:14 top_left_grid_pin_39_[0]:15 6.496724e-05 +30 top_left_grid_pin_35_[0]:14 top_left_grid_pin_39_[0]:12 0.0002853798 +31 top_left_grid_pin_35_[0]:14 top_left_grid_pin_39_[0]:8 2.932254e-05 +32 top_left_grid_pin_35_[0]:15 top_left_grid_pin_39_[0]:15 0.0002853798 +33 top_left_grid_pin_35_[0]:15 top_left_grid_pin_39_[0]:9 2.932254e-05 +34 top_left_grid_pin_35_[0]:15 top_left_grid_pin_39_[0]:16 6.496724e-05 +35 top_left_grid_pin_35_[0]:20 mux_tree_tapbuf_size2_4_sram[0]:10 6.107592e-07 +36 top_left_grid_pin_35_[0]:21 mux_tree_tapbuf_size2_4_sram[0]:11 6.107592e-07 +37 top_left_grid_pin_35_[0]:18 mux_tree_tapbuf_size2_4_sram[0]:9 3.364826e-06 +38 top_left_grid_pin_35_[0]:14 mux_tree_tapbuf_size2_4_sram[0]:5 0.0001073744 +39 top_left_grid_pin_35_[0]:14 mux_tree_tapbuf_size2_4_sram[0]:10 2.126805e-05 +40 top_left_grid_pin_35_[0]:15 mux_tree_tapbuf_size2_4_sram[0]:11 2.126805e-05 +41 top_left_grid_pin_35_[0]:15 mux_tree_tapbuf_size2_4_sram[0]:10 0.0001073744 +42 top_left_grid_pin_35_[0]:17 mux_tree_tapbuf_size2_4_sram[0]:8 3.364826e-06 +43 top_left_grid_pin_35_[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.82679e-05 +44 top_left_grid_pin_35_[0]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.82679e-05 +45 top_left_grid_pin_35_[0]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0002570607 +46 top_left_grid_pin_35_[0]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0002570607 +47 top_left_grid_pin_35_[0]:22 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001457752 +48 top_left_grid_pin_35_[0]:23 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001457752 + +*RES +0 top_left_grid_pin_35_[0] top_left_grid_pin_35_[0]:28 0.0005982143 +1 top_left_grid_pin_35_[0]:19 top_left_grid_pin_35_[0]:18 0.002513393 +2 top_left_grid_pin_35_[0]:20 top_left_grid_pin_35_[0]:19 0.0045 +3 top_left_grid_pin_35_[0]:21 top_left_grid_pin_35_[0]:20 0.006890625 +4 top_left_grid_pin_35_[0]:22 top_left_grid_pin_35_[0]:21 0.00341 +5 top_left_grid_pin_35_[0]:24 top_left_grid_pin_35_[0]:23 0.00341 +6 top_left_grid_pin_35_[0]:23 top_left_grid_pin_35_[0]:22 0.002447917 +7 top_left_grid_pin_35_[0]:26 top_left_grid_pin_35_[0]:25 0.0045 +8 top_left_grid_pin_35_[0]:25 top_left_grid_pin_35_[0]:24 0.004158482 +9 top_left_grid_pin_35_[0]:27 top_left_grid_pin_35_[0]:26 0.002383929 +10 top_left_grid_pin_35_[0]:28 top_left_grid_pin_35_[0]:27 0.0045 +11 top_left_grid_pin_35_[0]:6 top_left_grid_pin_35_[0]:5 0.0004263393 +12 top_left_grid_pin_35_[0]:7 top_left_grid_pin_35_[0]:6 0.0045 +13 top_left_grid_pin_35_[0]:5 mux_top_track_10\/mux_l1_in_0_:A1 0.152 +14 top_left_grid_pin_35_[0]:11 top_left_grid_pin_35_[0]:10 0.0045 +15 top_left_grid_pin_35_[0]:10 top_left_grid_pin_35_[0]:9 0.008156251 +16 top_left_grid_pin_35_[0]:8 mux_top_track_6\/mux_l1_in_0_:A1 0.152 +17 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:8 0.0045 +18 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:7 0.01149554 +19 top_left_grid_pin_35_[0]:18 mux_top_track_26\/mux_l1_in_0_:A1 0.152 +20 top_left_grid_pin_35_[0]:18 top_left_grid_pin_35_[0]:17 0.0007321429 +21 top_left_grid_pin_35_[0]:12 mux_top_track_2\/mux_l1_in_0_:A1 0.152 +22 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:12 0.0001847826 +23 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:11 0.002363839 +24 top_left_grid_pin_35_[0]:14 top_left_grid_pin_35_[0]:13 0.0045 +25 top_left_grid_pin_35_[0]:16 top_left_grid_pin_35_[0]:15 0.0045 +26 top_left_grid_pin_35_[0]:15 top_left_grid_pin_35_[0]:14 0.02359822 +27 top_left_grid_pin_35_[0]:17 top_left_grid_pin_35_[0]:16 0.0003035715 + +*END + +*D_NET chanx_left_in[1] 0.01192505 //LENGTH 72.960 LUMPCC 0.005106455 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.305 54.400 +*I mux_top_track_38\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.215 69.700 +*N chanx_left_in[1]:2 *C 57.178 69.700 +*N chanx_left_in[1]:3 *C 56.625 69.700 +*N chanx_left_in[1]:4 *C 56.580 69.655 +*N chanx_left_in[1]:5 *C 56.580 66.017 +*N chanx_left_in[1]:6 *C 56.573 65.960 +*N chanx_left_in[1]:7 *C 19.340 65.960 +*N chanx_left_in[1]:8 *C 19.320 65.953 +*N chanx_left_in[1]:9 *C 19.320 55.088 +*N chanx_left_in[1]:10 *C 19.300 55.080 +*N chanx_left_in[1]:11 *C 1.380 55.080 + +*CAP +0 chanx_left_in[1] 6.376572e-05 +1 mux_top_track_38\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[1]:2 5.302965e-05 +3 chanx_left_in[1]:3 5.302965e-05 +4 chanx_left_in[1]:4 0.00022929 +5 chanx_left_in[1]:5 0.00022929 +6 chanx_left_in[1]:6 0.001570095 +7 chanx_left_in[1]:7 0.001570095 +8 chanx_left_in[1]:8 0.0007093195 +9 chanx_left_in[1]:9 0.0007093195 +10 chanx_left_in[1]:10 0.0007832956 +11 chanx_left_in[1]:11 0.0008470613 +12 chanx_left_in[1]:6 prog_clk[0]:236 0.0003125882 +13 chanx_left_in[1]:7 prog_clk[0]:237 0.0003125882 +14 chanx_left_in[1]:6 chany_top_in[13]:6 0.0004975325 +15 chanx_left_in[1]:7 chany_top_in[13]:5 0.0004975325 +16 chanx_left_in[1]:6 chanx_left_in[3]:12 8.081004e-05 +17 chanx_left_in[1]:7 chanx_left_in[3]:13 8.081004e-05 +18 chanx_left_in[1]:10 chanx_left_in[3]:16 0.0002296366 +19 chanx_left_in[1]:11 chanx_left_in[3] 0.0002296366 +20 chanx_left_in[1]:4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 4.431534e-09 +21 chanx_left_in[1]:5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 4.431534e-09 +22 chanx_left_in[1]:6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 0.0001863232 +23 chanx_left_in[1]:7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 0.0001863232 +24 chanx_left_in[1]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003239348 +25 chanx_left_in[1]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.982402e-06 +26 chanx_left_in[1]:11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003239348 +27 chanx_left_in[1]:11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.982402e-06 +28 chanx_left_in[1]:6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006509745 +29 chanx_left_in[1]:7 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006509745 +30 chanx_left_in[1]:10 ccff_tail[0]:2 0.0002654409 +31 chanx_left_in[1]:11 ccff_tail[0] 0.0002654409 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:11 0.0001065333 +1 chanx_left_in[1]:2 mux_top_track_38\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[1]:3 chanx_left_in[1]:2 0.0004933036 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.0045 +4 chanx_left_in[1]:5 chanx_left_in[1]:4 0.003247768 +5 chanx_left_in[1]:6 chanx_left_in[1]:5 0.00341 +6 chanx_left_in[1]:7 chanx_left_in[1]:6 0.005833091 +7 chanx_left_in[1]:8 chanx_left_in[1]:7 0.00341 +8 chanx_left_in[1]:10 chanx_left_in[1]:9 0.00341 +9 chanx_left_in[1]:9 chanx_left_in[1]:8 0.001702183 +10 chanx_left_in[1]:11 chanx_left_in[1]:10 0.002807467 + +*END + +*D_NET chanx_left_in[16] 0.01029923 //LENGTH 88.845 LUMPCC 0.002042999 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 28.560 +*I mux_top_track_8\/mux_l1_in_1_:A1 I *L 0.00198 *C 76.000 41.820 +*N chanx_left_in[16]:2 *C 75.963 41.820 +*N chanx_left_in[16]:3 *C 74.105 41.820 +*N chanx_left_in[16]:4 *C 74.060 41.775 +*N chanx_left_in[16]:5 *C 74.060 28.617 +*N chanx_left_in[16]:6 *C 74.053 28.560 +*N chanx_left_in[16]:7 *C 51.230 28.560 + +*CAP +0 chanx_left_in[16] 0.002276396 +1 mux_top_track_8\/mux_l1_in_1_:A1 1e-06 +2 chanx_left_in[16]:2 0.0001382138 +3 chanx_left_in[16]:3 0.0001382138 +4 chanx_left_in[16]:4 0.0006421622 +5 chanx_left_in[16]:5 0.0006421622 +6 chanx_left_in[16]:6 0.001070843 +7 chanx_left_in[16]:7 0.003347239 +8 chanx_left_in[16] chany_top_in[9]:7 0.0001518061 +9 chanx_left_in[16]:6 chany_top_in[9]:8 0.0001926458 +10 chanx_left_in[16]:7 chany_top_in[9]:7 0.0001926458 +11 chanx_left_in[16]:7 chany_top_in[9]:8 0.0001518061 +12 chanx_left_in[16] mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003518303 +13 chanx_left_in[16]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0003518303 +14 chanx_left_in[16]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.471175e-05 +15 chanx_left_in[16]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.471175e-05 +16 chanx_left_in[16] mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001180096 +17 chanx_left_in[16]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001180096 +18 chanx_left_in[16] mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001324961 +19 chanx_left_in[16]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001324961 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:7 0.007833333 +1 chanx_left_in[16]:2 mux_top_track_8\/mux_l1_in_1_:A1 0.152 +2 chanx_left_in[16]:3 chanx_left_in[16]:2 0.001658482 +3 chanx_left_in[16]:4 chanx_left_in[16]:3 0.0045 +4 chanx_left_in[16]:5 chanx_left_in[16]:4 0.01174777 +5 chanx_left_in[16]:6 chanx_left_in[16]:5 0.00341 +6 chanx_left_in[16]:7 chanx_left_in[16]:6 0.003575525 + +*END + +*D_NET left_bottom_grid_pin_1_[0] 0.009559022 //LENGTH 77.135 LUMPCC 0.001598113 DR + +*CONN +*P left_bottom_grid_pin_1_[0] I *L 0.29796 *C 2.300 1.290 +*I mux_left_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 4.775 37.060 +*I mux_left_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 27.890 37.060 +*I mux_left_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.980 36.380 +*I mux_left_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 41.040 36.380 +*N left_bottom_grid_pin_1_[0]:5 *C 41.003 36.380 +*N left_bottom_grid_pin_1_[0]:6 *C 35.980 36.380 +*N left_bottom_grid_pin_1_[0]:7 *C 28.980 36.380 +*N left_bottom_grid_pin_1_[0]:8 *C 28.980 37.060 +*N left_bottom_grid_pin_1_[0]:9 *C 27.890 37.060 +*N left_bottom_grid_pin_1_[0]:10 *C 4.775 37.060 +*N left_bottom_grid_pin_1_[0]:11 *C 1.885 37.060 +*N left_bottom_grid_pin_1_[0]:12 *C 1.840 37.015 +*N left_bottom_grid_pin_1_[0]:13 *C 1.840 28.220 +*N left_bottom_grid_pin_1_[0]:14 *C 2.300 28.220 + +*CAP +0 left_bottom_grid_pin_1_[0] 0.001307334 +1 mux_left_track_1\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_5\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_9\/mux_l1_in_1_:A1 1e-06 +4 mux_left_track_25\/mux_l1_in_1_:A1 1e-06 +5 left_bottom_grid_pin_1_[0]:5 0.000300371 +6 left_bottom_grid_pin_1_[0]:6 0.0007127493 +7 left_bottom_grid_pin_1_[0]:7 0.0004242868 +8 left_bottom_grid_pin_1_[0]:8 0.0001096466 +9 left_bottom_grid_pin_1_[0]:9 0.001395426 +10 left_bottom_grid_pin_1_[0]:10 0.001509532 +11 left_bottom_grid_pin_1_[0]:11 0.000174862 +12 left_bottom_grid_pin_1_[0]:12 0.0003365597 +13 left_bottom_grid_pin_1_[0]:13 0.0003576838 +14 left_bottom_grid_pin_1_[0]:14 0.001328458 +15 left_bottom_grid_pin_1_[0]:9 mux_tree_tapbuf_size6_2_sram[2]:5 0.0002233506 +16 left_bottom_grid_pin_1_[0]:9 mux_tree_tapbuf_size6_2_sram[2]:3 2.184398e-05 +17 left_bottom_grid_pin_1_[0]:10 mux_tree_tapbuf_size6_2_sram[2]:5 2.184398e-05 +18 left_bottom_grid_pin_1_[0]:10 mux_tree_tapbuf_size6_2_sram[2]:4 0.0002233506 +19 left_bottom_grid_pin_1_[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.726802e-05 +20 left_bottom_grid_pin_1_[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.726802e-05 +21 left_bottom_grid_pin_1_[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001039967 +22 left_bottom_grid_pin_1_[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001039967 +23 left_bottom_grid_pin_1_[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001026781 +24 left_bottom_grid_pin_1_[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001026781 +25 left_bottom_grid_pin_1_[0] mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.07393e-05 +26 left_bottom_grid_pin_1_[0]:12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002395301 +27 left_bottom_grid_pin_1_[0]:13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.649436e-06 +28 left_bottom_grid_pin_1_[0]:13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002395301 +29 left_bottom_grid_pin_1_[0]:14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.649436e-06 +30 left_bottom_grid_pin_1_[0]:14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.07393e-05 + +*RES +0 left_bottom_grid_pin_1_[0] left_bottom_grid_pin_1_[0]:14 0.02404464 +1 left_bottom_grid_pin_1_[0]:9 mux_left_track_5\/mux_l1_in_2_:A0 0.152 +2 left_bottom_grid_pin_1_[0]:9 left_bottom_grid_pin_1_[0]:8 0.0009732143 +3 left_bottom_grid_pin_1_[0]:11 left_bottom_grid_pin_1_[0]:10 0.002580357 +4 left_bottom_grid_pin_1_[0]:12 left_bottom_grid_pin_1_[0]:11 0.0045 +5 left_bottom_grid_pin_1_[0]:5 mux_left_track_25\/mux_l1_in_1_:A1 0.152 +6 left_bottom_grid_pin_1_[0]:6 mux_left_track_9\/mux_l1_in_1_:A1 0.152 +7 left_bottom_grid_pin_1_[0]:6 left_bottom_grid_pin_1_[0]:5 0.004484375 +8 left_bottom_grid_pin_1_[0]:10 mux_left_track_1\/mux_l1_in_2_:A0 0.152 +9 left_bottom_grid_pin_1_[0]:10 left_bottom_grid_pin_1_[0]:9 0.0206384 +10 left_bottom_grid_pin_1_[0]:8 left_bottom_grid_pin_1_[0]:7 0.0006071429 +11 left_bottom_grid_pin_1_[0]:7 left_bottom_grid_pin_1_[0]:6 0.00625 +12 left_bottom_grid_pin_1_[0]:13 left_bottom_grid_pin_1_[0]:12 0.007852679 +13 left_bottom_grid_pin_1_[0]:14 left_bottom_grid_pin_1_[0]:13 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.0009232843 //LENGTH 8.515 LUMPCC 0 DR + +*CONN +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 66.085 37.060 +*I mem_top_track_10\/FTB_13__18:A I *L 0.001746 *C 63.940 34.000 +*I mux_top_track_10\/mux_l2_in_0_:S I *L 0.00357 *C 65.220 39.440 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 65.220 39.440 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 65.320 39.395 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 63.978 34.000 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 65.275 34.000 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 65.320 34.045 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 65.320 37.060 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 65.365 37.060 +*N mux_tree_tapbuf_size2_0_sram[1]:10 *C 66.047 37.060 + +*CAP +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_10\/FTB_13__18:A 1e-06 +2 mux_top_track_10\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 2.629718e-05 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0001233227 +5 mux_tree_tapbuf_size2_0_sram[1]:5 8.972118e-05 +6 mux_tree_tapbuf_size2_0_sram[1]:6 8.972118e-05 +7 mux_tree_tapbuf_size2_0_sram[1]:7 0.0001552517 +8 mux_tree_tapbuf_size2_0_sram[1]:8 0.000308325 +9 mux_tree_tapbuf_size2_0_sram[1]:9 6.382269e-05 +10 mux_tree_tapbuf_size2_0_sram[1]:10 6.382269e-05 + +*RES +0 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:3 mux_top_track_10\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.002691964 +5 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:4 0.002084821 +6 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:9 0.000609375 +7 mux_tree_tapbuf_size2_0_sram[1]:5 mem_top_track_10\/FTB_13__18:A 0.152 +8 mux_tree_tapbuf_size2_0_sram[1]:6 mux_tree_tapbuf_size2_0_sram[1]:5 0.001158482 +9 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_18_sram[1] 0.001062501 //LENGTH 9.040 LUMPCC 0 DR + +*CONN +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 25.850 25.500 +*I mem_left_track_19\/FTB_31__36:A I *L 0.001746 *C 25.300 28.560 +*I mux_left_track_19\/mux_l2_in_0_:S I *L 0.00357 *C 20.800 28.560 +*N mux_tree_tapbuf_size2_18_sram[1]:3 *C 20.838 28.560 +*N mux_tree_tapbuf_size2_18_sram[1]:4 *C 25.263 28.560 +*N mux_tree_tapbuf_size2_18_sram[1]:5 *C 25.300 28.515 +*N mux_tree_tapbuf_size2_18_sram[1]:6 *C 25.300 25.545 +*N mux_tree_tapbuf_size2_18_sram[1]:7 *C 25.345 25.500 +*N mux_tree_tapbuf_size2_18_sram[1]:8 *C 25.812 25.500 + +*CAP +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_19\/FTB_31__36:A 1e-06 +2 mux_left_track_19\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_18_sram[1]:3 0.000303797 +4 mux_tree_tapbuf_size2_18_sram[1]:4 0.000303797 +5 mux_tree_tapbuf_size2_18_sram[1]:5 0.0001699505 +6 mux_tree_tapbuf_size2_18_sram[1]:6 0.0001699505 +7 mux_tree_tapbuf_size2_18_sram[1]:7 5.600294e-05 +8 mux_tree_tapbuf_size2_18_sram[1]:8 5.600294e-05 + +*RES +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_18_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_18_sram[1]:8 mux_tree_tapbuf_size2_18_sram[1]:7 0.0004174107 +2 mux_tree_tapbuf_size2_18_sram[1]:7 mux_tree_tapbuf_size2_18_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size2_18_sram[1]:6 mux_tree_tapbuf_size2_18_sram[1]:5 0.002651786 +4 mux_tree_tapbuf_size2_18_sram[1]:4 mem_left_track_19\/FTB_31__36:A 0.152 +5 mux_tree_tapbuf_size2_18_sram[1]:4 mux_tree_tapbuf_size2_18_sram[1]:3 0.003950893 +6 mux_tree_tapbuf_size2_18_sram[1]:5 mux_tree_tapbuf_size2_18_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size2_18_sram[1]:3 mux_left_track_19\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_20_sram[1] 0.001703307 //LENGTH 13.170 LUMPCC 0 DR + +*CONN +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.625 28.220 +*I mux_left_track_23\/mux_l2_in_0_:S I *L 0.00357 *C 36.440 31.280 +*I mem_left_track_23\/FTB_33__38:A I *L 0.001746 *C 45.080 28.560 +*N mux_tree_tapbuf_size2_20_sram[1]:3 *C 45.043 28.560 +*N mux_tree_tapbuf_size2_20_sram[1]:4 *C 42.780 28.560 +*N mux_tree_tapbuf_size2_20_sram[1]:5 *C 36.477 31.280 +*N mux_tree_tapbuf_size2_20_sram[1]:6 *C 39.055 31.280 +*N mux_tree_tapbuf_size2_20_sram[1]:7 *C 39.100 31.235 +*N mux_tree_tapbuf_size2_20_sram[1]:8 *C 39.100 28.265 +*N mux_tree_tapbuf_size2_20_sram[1]:9 *C 39.145 28.220 +*N mux_tree_tapbuf_size2_20_sram[1]:10 *C 42.740 28.242 + +*CAP +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_23\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_23\/FTB_33__38:A 1e-06 +3 mux_tree_tapbuf_size2_20_sram[1]:3 0.0001627431 +4 mux_tree_tapbuf_size2_20_sram[1]:4 0.0001870921 +5 mux_tree_tapbuf_size2_20_sram[1]:5 0.00018899 +6 mux_tree_tapbuf_size2_20_sram[1]:6 0.00018899 +7 mux_tree_tapbuf_size2_20_sram[1]:7 0.0001890717 +8 mux_tree_tapbuf_size2_20_sram[1]:8 0.0001890717 +9 mux_tree_tapbuf_size2_20_sram[1]:9 0.0002849996 +10 mux_tree_tapbuf_size2_20_sram[1]:10 0.0003093487 + +*RES +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_20_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_20_sram[1]:9 mux_tree_tapbuf_size2_20_sram[1]:8 0.0045 +2 mux_tree_tapbuf_size2_20_sram[1]:8 mux_tree_tapbuf_size2_20_sram[1]:7 0.002651786 +3 mux_tree_tapbuf_size2_20_sram[1]:6 mux_tree_tapbuf_size2_20_sram[1]:5 0.002301339 +4 mux_tree_tapbuf_size2_20_sram[1]:7 mux_tree_tapbuf_size2_20_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size2_20_sram[1]:5 mux_left_track_23\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_20_sram[1]:3 mem_left_track_23\/FTB_33__38:A 0.152 +7 mux_tree_tapbuf_size2_20_sram[1]:10 mux_tree_tapbuf_size2_20_sram[1]:9 0.003209822 +8 mux_tree_tapbuf_size2_20_sram[1]:10 mux_tree_tapbuf_size2_20_sram[1]:4 0.0002834821 +9 mux_tree_tapbuf_size2_20_sram[1]:4 mux_tree_tapbuf_size2_20_sram[1]:3 0.002020089 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[0] 0.004832133 //LENGTH 33.690 LUMPCC 0.001097718 DR + +*CONN +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 90.005 82.960 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 85.735 86.020 +*I mux_top_track_22\/mux_l1_in_0_:S I *L 0.00357 *C 62.000 85.680 +*N mux_tree_tapbuf_size2_6_sram[0]:3 *C 62.038 85.680 +*N mux_tree_tapbuf_size2_6_sram[0]:4 *C 63.435 85.680 +*N mux_tree_tapbuf_size2_6_sram[0]:5 *C 63.480 85.635 +*N mux_tree_tapbuf_size2_6_sram[0]:6 *C 63.480 85.058 +*N mux_tree_tapbuf_size2_6_sram[0]:7 *C 63.488 85.000 +*N mux_tree_tapbuf_size2_6_sram[0]:8 *C 85.735 86.020 +*N mux_tree_tapbuf_size2_6_sram[0]:9 *C 85.560 86.020 +*N mux_tree_tapbuf_size2_6_sram[0]:10 *C 85.560 85.975 +*N mux_tree_tapbuf_size2_6_sram[0]:11 *C 85.560 85.058 +*N mux_tree_tapbuf_size2_6_sram[0]:12 *C 85.560 85.000 +*N mux_tree_tapbuf_size2_6_sram[0]:13 *C 89.693 85.000 +*N mux_tree_tapbuf_size2_6_sram[0]:14 *C 89.700 84.943 +*N mux_tree_tapbuf_size2_6_sram[0]:15 *C 89.700 83.005 +*N mux_tree_tapbuf_size2_6_sram[0]:16 *C 89.700 82.960 +*N mux_tree_tapbuf_size2_6_sram[0]:17 *C 90.005 82.960 + +*CAP +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_22\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_6_sram[0]:3 0.0001059395 +4 mux_tree_tapbuf_size2_6_sram[0]:4 0.0001059395 +5 mux_tree_tapbuf_size2_6_sram[0]:5 5.426373e-05 +6 mux_tree_tapbuf_size2_6_sram[0]:6 5.426373e-05 +7 mux_tree_tapbuf_size2_6_sram[0]:7 0.001230449 +8 mux_tree_tapbuf_size2_6_sram[0]:8 4.417739e-05 +9 mux_tree_tapbuf_size2_6_sram[0]:9 4.816565e-05 +10 mux_tree_tapbuf_size2_6_sram[0]:10 7.117653e-05 +11 mux_tree_tapbuf_size2_6_sram[0]:11 7.117653e-05 +12 mux_tree_tapbuf_size2_6_sram[0]:12 0.001433032 +13 mux_tree_tapbuf_size2_6_sram[0]:13 0.0002025831 +14 mux_tree_tapbuf_size2_6_sram[0]:14 0.0001090491 +15 mux_tree_tapbuf_size2_6_sram[0]:15 0.0001090491 +16 mux_tree_tapbuf_size2_6_sram[0]:16 4.621033e-05 +17 mux_tree_tapbuf_size2_6_sram[0]:17 4.594015e-05 +18 mux_tree_tapbuf_size2_6_sram[0]:7 chany_top_in[11]:9 0.0002236825 +19 mux_tree_tapbuf_size2_6_sram[0]:12 chany_top_in[11]:10 0.0002236825 +20 mux_tree_tapbuf_size2_6_sram[0]:7 chany_top_out[18]:4 0.0001048466 +21 mux_tree_tapbuf_size2_6_sram[0]:12 chany_top_out[18]:3 0.0001048466 +22 mux_tree_tapbuf_size2_6_sram[0]:12 chany_top_out[18]:4 5.460719e-05 +23 mux_tree_tapbuf_size2_6_sram[0]:13 chany_top_out[18]:3 5.460719e-05 +24 mux_tree_tapbuf_size2_6_sram[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001129515 +25 mux_tree_tapbuf_size2_6_sram[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 2.961019e-05 +26 mux_tree_tapbuf_size2_6_sram[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 2.961019e-05 +27 mux_tree_tapbuf_size2_6_sram[0]:12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001129515 +28 mux_tree_tapbuf_size2_6_sram[0]:12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.316092e-05 +29 mux_tree_tapbuf_size2_6_sram[0]:13 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.316092e-05 + +*RES +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_6_sram[0]:17 0.152 +1 mux_tree_tapbuf_size2_6_sram[0]:6 mux_tree_tapbuf_size2_6_sram[0]:5 0.0005156251 +2 mux_tree_tapbuf_size2_6_sram[0]:7 mux_tree_tapbuf_size2_6_sram[0]:6 0.00341 +3 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[0]:3 0.001247768 +4 mux_tree_tapbuf_size2_6_sram[0]:5 mux_tree_tapbuf_size2_6_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size2_6_sram[0]:3 mux_top_track_22\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_6_sram[0]:11 mux_tree_tapbuf_size2_6_sram[0]:10 0.0008191966 +7 mux_tree_tapbuf_size2_6_sram[0]:12 mux_tree_tapbuf_size2_6_sram[0]:11 0.00341 +8 mux_tree_tapbuf_size2_6_sram[0]:12 mux_tree_tapbuf_size2_6_sram[0]:7 0.003458025 +9 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:8 9.51087e-05 +10 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:9 0.0045 +11 mux_tree_tapbuf_size2_6_sram[0]:8 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_6_sram[0]:14 mux_tree_tapbuf_size2_6_sram[0]:13 0.00341 +13 mux_tree_tapbuf_size2_6_sram[0]:13 mux_tree_tapbuf_size2_6_sram[0]:12 0.000647425 +14 mux_tree_tapbuf_size2_6_sram[0]:16 mux_tree_tapbuf_size2_6_sram[0]:15 0.0045 +15 mux_tree_tapbuf_size2_6_sram[0]:15 mux_tree_tapbuf_size2_6_sram[0]:14 0.001729911 +16 mux_tree_tapbuf_size2_6_sram[0]:17 mux_tree_tapbuf_size2_6_sram[0]:16 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_18_ccff_tail[0] 0.0005652186 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mem_left_track_19\/FTB_31__36:X O *L 0 *C 28.295 28.900 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 28.235 31.620 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:2 *C 28.235 31.620 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:3 *C 28.520 31.620 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:4 *C 28.520 31.575 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:5 *C 28.520 28.945 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:6 *C 28.520 28.900 +*N mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:7 *C 28.295 28.900 + +*CAP +0 mem_left_track_19\/FTB_31__36:X 1e-06 +1 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:2 5.818923e-05 +3 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:3 5.829654e-05 +4 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:4 0.0001719791 +5 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:5 0.0001719791 +6 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:6 5.145583e-05 +7 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:7 5.131892e-05 + +*RES +0 mem_left_track_19\/FTB_31__36:X mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_18_ccff_tail[0]:2 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.005300823 //LENGTH 40.895 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 89.545 93.500 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 79.680 90.830 +*I mux_top_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 77.640 90.780 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 70.095 98.940 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 70.095 98.940 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 69.920 98.600 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 88.275 98.600 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 88.320 98.555 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 77.678 90.780 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 79.680 90.782 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 79.680 90.440 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 88.275 90.440 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 88.320 90.485 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 88.320 93.500 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 88.365 93.500 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 89.508 93.500 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_24\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 5.582286e-05 +5 mux_tree_tapbuf_size3_1_sram[0]:5 0.001284584 +6 mux_tree_tapbuf_size3_1_sram[0]:6 0.00125836 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0002696834 +8 mux_tree_tapbuf_size3_1_sram[0]:8 0.0001695531 +9 mux_tree_tapbuf_size3_1_sram[0]:9 0.000203124 +10 mux_tree_tapbuf_size3_1_sram[0]:10 0.0006354277 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.0006018568 +12 mux_tree_tapbuf_size3_1_sram[0]:12 0.0001678836 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0004696517 +14 mux_tree_tapbuf_size3_1_sram[0]:14 9.043818e-05 +15 mux_tree_tapbuf_size3_1_sram[0]:15 9.043818e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:15 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:8 mux_top_track_24\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.007674107 +3 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size3_1_sram[0]:6 mux_tree_tapbuf_size3_1_sram[0]:5 0.01638839 +5 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:6 0.0045 +6 mux_tree_tapbuf_size3_1_sram[0]:4 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.0045 +8 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.002691964 +9 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:7 0.004513393 +10 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.001020089 +11 mux_tree_tapbuf_size3_1_sram[0]:9 mux_top_track_24\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:8 0.001787947 +13 mux_tree_tapbuf_size3_1_sram[0]:5 mux_tree_tapbuf_size3_1_sram[0]:4 0.0003035715 +14 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0003058036 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_1_ccff_tail[0] 0.001158154 //LENGTH 9.090 LUMPCC 0.0002603244 DR + +*CONN +*I mem_top_track_6\/FTB_6__11:X O *L 0 *C 72.915 52.360 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 69.175 47.940 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 *C 69.213 47.940 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 *C 71.255 47.940 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 *C 71.300 47.985 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 *C 71.300 52.315 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 *C 71.345 52.360 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 *C 72.877 52.360 + +*CAP +0 mem_top_track_6\/FTB_6__11:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.000154032 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.000154032 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.0002091924 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0002091924 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 8.469051e-05 +7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 8.469051e-05 +8 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 top_left_grid_pin_36_[0]:7 5.281462e-05 +9 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 top_left_grid_pin_36_[0]:10 5.281462e-05 +10 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.955372e-06 +11 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.039219e-05 +12 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.955372e-06 +13 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.039219e-05 + +*RES +0 mem_top_track_6\/FTB_6__11:X mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.001823661 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.001368304 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[1] 0.002027583 //LENGTH 13.570 LUMPCC 0.0002944543 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 9.965 44.880 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 12.980 41.480 +*I mux_left_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 10.480 39.440 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 13.055 39.100 +*N mux_tree_tapbuf_size6_2_sram[1]:4 *C 13.018 39.100 +*N mux_tree_tapbuf_size6_2_sram[1]:5 *C 10.120 39.100 +*N mux_tree_tapbuf_size6_2_sram[1]:6 *C 10.465 39.440 +*N mux_tree_tapbuf_size6_2_sram[1]:7 *C 10.120 39.418 +*N mux_tree_tapbuf_size6_2_sram[1]:8 *C 10.120 39.485 +*N mux_tree_tapbuf_size6_2_sram[1]:9 *C 12.943 41.480 +*N mux_tree_tapbuf_size6_2_sram[1]:10 *C 10.165 41.480 +*N mux_tree_tapbuf_size6_2_sram[1]:11 *C 10.120 41.480 +*N mux_tree_tapbuf_size6_2_sram[1]:12 *C 10.120 44.835 +*N mux_tree_tapbuf_size6_2_sram[1]:13 *C 10.120 44.880 +*N mux_tree_tapbuf_size6_2_sram[1]:14 *C 9.965 44.880 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_1\/mux_l2_in_1_:S 1e-06 +3 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_2_sram[1]:4 0.0002534368 +5 mux_tree_tapbuf_size6_2_sram[1]:5 0.0002817218 +6 mux_tree_tapbuf_size6_2_sram[1]:6 7.421619e-05 +7 mux_tree_tapbuf_size6_2_sram[1]:7 0.0001025013 +8 mux_tree_tapbuf_size6_2_sram[1]:8 8.499556e-05 +9 mux_tree_tapbuf_size6_2_sram[1]:9 0.0001573662 +10 mux_tree_tapbuf_size6_2_sram[1]:10 0.0001573662 +11 mux_tree_tapbuf_size6_2_sram[1]:11 0.000313968 +12 mux_tree_tapbuf_size6_2_sram[1]:12 0.0001963589 +13 mux_tree_tapbuf_size6_2_sram[1]:13 5.579106e-05 +14 mux_tree_tapbuf_size6_2_sram[1]:14 5.140722e-05 +15 mux_tree_tapbuf_size6_2_sram[1]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.062727e-05 +16 mux_tree_tapbuf_size6_2_sram[1]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.118055e-05 +17 mux_tree_tapbuf_size6_2_sram[1]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.54193e-05 +18 mux_tree_tapbuf_size6_2_sram[1]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.54193e-05 +19 mux_tree_tapbuf_size6_2_sram[1]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.062727e-05 +20 mux_tree_tapbuf_size6_2_sram[1]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.118055e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_2_sram[1]:14 0.152 +1 mux_tree_tapbuf_size6_2_sram[1]:4 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size6_2_sram[1]:7 mux_tree_tapbuf_size6_2_sram[1]:6 0.0001875 +3 mux_tree_tapbuf_size6_2_sram[1]:7 mux_tree_tapbuf_size6_2_sram[1]:5 0.0002834822 +4 mux_tree_tapbuf_size6_2_sram[1]:8 mux_tree_tapbuf_size6_2_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size6_2_sram[1]:13 mux_tree_tapbuf_size6_2_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size6_2_sram[1]:12 mux_tree_tapbuf_size6_2_sram[1]:11 0.002995536 +7 mux_tree_tapbuf_size6_2_sram[1]:14 mux_tree_tapbuf_size6_2_sram[1]:13 8.423914e-05 +8 mux_tree_tapbuf_size6_2_sram[1]:9 mux_left_track_1\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size6_2_sram[1]:10 mux_tree_tapbuf_size6_2_sram[1]:9 0.002479911 +10 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:10 0.0045 +11 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:8 0.00178125 +12 mux_tree_tapbuf_size6_2_sram[1]:6 mux_left_track_1\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size6_2_sram[1]:5 mux_tree_tapbuf_size6_2_sram[1]:4 0.002587054 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000626693 //LENGTH 4.285 LUMPCC 0.0001520907 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_1_:X O *L 0 *C 23.745 49.640 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 25.590 47.940 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 25.553 47.940 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 23.965 47.940 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 23.920 47.985 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 23.920 49.595 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 23.920 49.640 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 23.745 49.640 + +*CAP +0 mux_left_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.358095e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.358095e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001090182 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001090182 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.167486e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.572916e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_3_sram[0]:16 7.356269e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_3_sram[0]:17 7.356269e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_3_sram[0]:18 2.482678e-06 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_3_sram[0]:22 2.482678e-06 + +*RES +0 mux_left_track_5\/mux_l1_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001417411 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003598347 //LENGTH 32.355 LUMPCC 0.0003105751 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_0_:X O *L 0 *C 67.905 64.260 +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 66.915 93.650 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 66.953 93.553 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 68.495 93.500 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 68.540 93.455 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 68.540 64.305 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 68.495 64.260 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 67.943 64.260 + +*CAP +0 mux_top_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001212015 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001212015 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001467404 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001467404 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.428048e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.428048e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_6/BUF_net_42:4 0.0001552876 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_6/BUF_net_42:3 0.0001552876 + +*RES +0 mux_top_track_2\/mux_l3_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0004933036 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.02602679 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001377232 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001709356 //LENGTH 12.490 LUMPCC 0.0005389228 DR + +*CONN +*I mux_left_track_7\/mux_l2_in_0_:X O *L 0 *C 26.395 60.520 +*I mux_left_track_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 27.965 56.100 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 27.965 56.100 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 28.060 56.055 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 28.060 53.425 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 28.015 53.380 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 26.725 53.380 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 26.680 53.425 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 26.680 60.475 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 26.680 60.520 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 26.395 60.520 + +*CAP +0 mux_left_track_7\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_7\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.26983e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001214065 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001214065 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.47329e-05 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.47329e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003123719 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0003123719 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:9 6.001551e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:10 5.869722e-05 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_top_in[1]:4 6.063452e-05 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chany_top_in[1]:5 6.063452e-05 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:380 6.859179e-05 +14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 prog_clk[0]:395 6.287466e-07 +15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:379 6.859179e-05 +16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 prog_clk[0]:383 6.287466e-07 +17 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:379 1.455961e-05 +18 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:383 2.084314e-07 +19 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:396 5.417017e-07 +20 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 prog_clk[0]:380 1.455961e-05 +21 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 prog_clk[0]:395 2.084314e-07 +22 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 prog_clk[0]:464 5.417017e-07 +23 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_3_sram[2]:4 1.023837e-05 +24 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_3_sram[2]:7 4.598423e-05 +25 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_3_sram[2]:5 1.023837e-05 +26 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_3_sram[2]:6 4.598423e-05 +27 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size5_3_sram[2]:5 6.807398e-05 +28 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size5_3_sram[2]:4 6.807398e-05 + +*RES +0 mux_left_track_7\/mux_l2_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_7\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002348214 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001151786 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0045 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.006294644 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001548913 + +*END + +*D_NET mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002189493 //LENGTH 19.075 LUMPCC 0.0002554966 DR + +*CONN +*I mux_top_track_20\/mux_l2_in_0_:X O *L 0 *C 79.865 83.640 +*I mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 93.665 88.205 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 93.627 88.110 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.465 88.060 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 81.420 88.015 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.420 83.685 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.375 83.640 +*N mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 79.903 83.640 + +*CAP +0 mux_top_track_20\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0006660545 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0006660545 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001706581 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001706581 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001292854 +7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001292854 +8 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_right_grid_pin_1_[0]:18 0.0001277483 +9 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_right_grid_pin_1_[0]:15 0.0001277483 + +*RES +0 mux_top_track_20\/mux_l2_in_0_:X mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.01085938 +3 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003132637 //LENGTH 27.080 LUMPCC 0.0004420644 DR + +*CONN +*I mux_top_track_38\/mux_l2_in_0_:X O *L 0 *C 65.605 72.760 +*I mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 66.005 99.080 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 66.005 99.080 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 65.780 98.940 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 65.780 98.895 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 65.780 72.805 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 65.780 72.760 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 65.605 72.760 + +*CAP +0 mux_top_track_38\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.558856e-05 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.927237e-05 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001231026 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001231026 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.685289e-05 +7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.480748e-05 +8 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[7]:9 0.0002210322 +9 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[7] 0.0002210322 + +*RES +0 mux_top_track_38\/mux_l2_in_0_:X mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.02329464 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001222826 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 + +*END + +*D_NET mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001221125 //LENGTH 9.430 LUMPCC 0.0004320043 DR + +*CONN +*I mux_left_track_19\/mux_l1_in_0_:X O *L 0 *C 23.285 36.040 +*I mux_left_track_19\/mux_l2_in_0_:A1 I *L 0.00198 *C 21.620 28.900 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 21.620 28.900 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 21.620 28.945 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 21.620 35.995 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 21.665 36.040 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 23.248 36.040 + +*CAP +0 mux_left_track_19\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_19\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.293397e-05 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002635319 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002635319 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001135613 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001135613 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_107:48 2.054907e-05 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_107:47 2.054907e-05 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_107:45 0.0001954531 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_107:44 0.0001954531 + +*RES +0 mux_left_track_19\/mux_l1_in_0_:X mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001412946 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006294644 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_19\/mux_l2_in_0_:A1 0.152 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET chanx_left_out[12] 0.0005401864 //LENGTH 3.700 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 4.140 23.460 +*P chanx_left_out[12] O *L 0.7423 *C 1.230 23.120 +*N chanx_left_out[12]:2 *C 1.833 23.120 +*N chanx_left_out[12]:3 *C 1.840 23.120 +*N chanx_left_out[12]:4 *C 1.840 23.460 +*N chanx_left_out[12]:5 *C 1.885 23.460 +*N chanx_left_out[12]:6 *C 4.103 23.460 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 chanx_left_out[12] 6.537733e-05 +2 chanx_left_out[12]:2 6.537733e-05 +3 chanx_left_out[12]:3 5.538912e-05 +4 chanx_left_out[12]:4 5.44569e-05 +5 chanx_left_out[12]:5 0.0001492929 +6 chanx_left_out[12]:6 0.0001492929 + +*RES +0 ropt_mt_inst_733:X chanx_left_out[12]:6 0.152 +1 chanx_left_out[12]:6 chanx_left_out[12]:5 0.001979911 +2 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0045 +3 chanx_left_out[12]:4 chanx_left_out[12]:3 0.0001634615 +4 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +5 chanx_left_out[12]:2 chanx_left_out[12] 9.439165e-05 + +*END + +*D_NET chanx_left_out[17] 0.00261851 //LENGTH 13.920 LUMPCC 0.001055489 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 11.695 42.840 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 43.520 +*N chanx_left_out[17]:2 *C 1.840 43.520 +*N chanx_left_out[17]:3 *C 1.840 44.200 +*N chanx_left_out[17]:4 *C 11.033 44.200 +*N chanx_left_out[17]:5 *C 11.040 44.143 +*N chanx_left_out[17]:6 *C 11.040 42.885 +*N chanx_left_out[17]:7 *C 11.085 42.840 +*N chanx_left_out[17]:8 *C 11.658 42.840 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 chanx_left_out[17] 5.441435e-05 +2 chanx_left_out[17]:2 0.0001011224 +3 chanx_left_out[17]:3 0.0005682142 +4 chanx_left_out[17]:4 0.0005215061 +5 chanx_left_out[17]:5 9.784381e-05 +6 chanx_left_out[17]:6 9.784381e-05 +7 chanx_left_out[17]:7 6.0538e-05 +8 chanx_left_out[17]:8 6.0538e-05 +9 chanx_left_out[17] chanx_left_in[13] 9.323312e-06 +10 chanx_left_out[17]:4 chanx_left_in[13]:6 0.0005184212 +11 chanx_left_out[17]:2 chanx_left_in[13]:6 9.323312e-06 +12 chanx_left_out[17]:3 chanx_left_in[13] 0.0005184212 + +*RES +0 ropt_mt_inst_738:X chanx_left_out[17]:8 0.152 +1 chanx_left_out[17]:8 chanx_left_out[17]:7 0.0005111608 +2 chanx_left_out[17]:7 chanx_left_out[17]:6 0.0045 +3 chanx_left_out[17]:6 chanx_left_out[17]:5 0.001122768 +4 chanx_left_out[17]:5 chanx_left_out[17]:4 0.00341 +5 chanx_left_out[17]:4 chanx_left_out[17]:3 0.001440158 +6 chanx_left_out[17]:2 chanx_left_out[17] 9.556666e-05 +7 chanx_left_out[17]:3 chanx_left_out[17]:2 0.0001065333 + +*END + +*D_NET chany_top_in[4] 0.01513547 //LENGTH 112.540 LUMPCC 0.003127008 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 51.980 102.035 +*I BUFT_P_83:A I *L 0.001776 *C 18.860 28.560 +*N chany_top_in[4]:2 *C 18.898 28.560 +*N chany_top_in[4]:3 *C 19.275 28.560 +*N chany_top_in[4]:4 *C 19.320 28.605 +*N chany_top_in[4]:5 *C 19.320 30.895 +*N chany_top_in[4]:6 *C 19.365 30.940 +*N chany_top_in[4]:7 *C 24.380 30.940 +*N chany_top_in[4]:8 *C 24.305 30.600 +*N chany_top_in[4]:9 *C 24.373 30.645 +*N chany_top_in[4]:10 *C 24.380 31.235 +*N chany_top_in[4]:11 *C 24.425 31.280 +*N chany_top_in[4]:12 *C 25.255 31.280 +*N chany_top_in[4]:13 *C 25.300 31.235 +*N chany_top_in[4]:14 *C 25.300 30.658 +*N chany_top_in[4]:15 *C 25.308 30.600 +*N chany_top_in[4]:16 *C 31.260 30.600 +*N chany_top_in[4]:17 *C 31.280 30.608 +*N chany_top_in[4]:18 *C 31.280 78.873 +*N chany_top_in[4]:19 *C 31.300 78.880 +*N chany_top_in[4]:20 *C 34.032 78.880 +*N chany_top_in[4]:21 *C 34.040 78.938 +*N chany_top_in[4]:22 *C 34.040 101.275 +*N chany_top_in[4]:23 *C 34.085 101.320 +*N chany_top_in[4]:24 *C 51.935 101.320 +*N chany_top_in[4]:25 *C 51.980 101.365 + +*CAP +0 chany_top_in[4] 5.289087e-05 +1 BUFT_P_83:A 1e-06 +2 chany_top_in[4]:2 5.792354e-05 +3 chany_top_in[4]:3 5.792354e-05 +4 chany_top_in[4]:4 0.0001481424 +5 chany_top_in[4]:5 0.0001481424 +6 chany_top_in[4]:6 0.0003013878 +7 chany_top_in[4]:7 0.0003332729 +8 chany_top_in[4]:8 7.091473e-05 +9 chany_top_in[4]:9 4.362674e-05 +10 chany_top_in[4]:10 4.362674e-05 +11 chany_top_in[4]:11 7.580066e-05 +12 chany_top_in[4]:12 7.580066e-05 +13 chany_top_in[4]:13 5.437417e-05 +14 chany_top_in[4]:14 5.437417e-05 +15 chany_top_in[4]:15 0.0002285073 +16 chany_top_in[4]:16 0.0002285073 +17 chany_top_in[4]:17 0.00261272 +18 chany_top_in[4]:18 0.00261272 +19 chany_top_in[4]:19 0.000225407 +20 chany_top_in[4]:20 0.000225407 +21 chany_top_in[4]:21 0.00121731 +22 chany_top_in[4]:22 0.00121731 +23 chany_top_in[4]:23 0.0009342398 +24 chany_top_in[4]:24 0.0009342398 +25 chany_top_in[4]:25 5.289087e-05 +26 chany_top_in[4]:17 chanx_left_in[5]:8 0.0007671652 +27 chany_top_in[4]:18 chanx_left_in[5]:7 0.0007671652 +28 chany_top_in[4]:21 mux_tree_tapbuf_size2_8_sram[0]:5 5.033373e-05 +29 chany_top_in[4]:21 mux_tree_tapbuf_size2_8_sram[0]:8 3.063999e-05 +30 chany_top_in[4]:23 mux_tree_tapbuf_size2_8_sram[0]:11 7.162608e-05 +31 chany_top_in[4]:23 mux_tree_tapbuf_size2_8_sram[0]:13 0.0002850767 +32 chany_top_in[4]:22 mux_tree_tapbuf_size2_8_sram[0]:9 3.063999e-05 +33 chany_top_in[4]:22 mux_tree_tapbuf_size2_8_sram[0]:8 5.033373e-05 +34 chany_top_in[4]:24 mux_tree_tapbuf_size2_8_sram[0]:14 0.0002850767 +35 chany_top_in[4]:24 mux_tree_tapbuf_size2_8_sram[0]:12 7.162608e-05 +36 chany_top_in[4]:15 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0003586626 +37 chany_top_in[4]:16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0003586626 + +*RES +0 chany_top_in[4] chany_top_in[4]:25 0.0005982143 +1 chany_top_in[4]:2 BUFT_P_83:A 0.152 +2 chany_top_in[4]:3 chany_top_in[4]:2 0.0003370536 +3 chany_top_in[4]:4 chany_top_in[4]:3 0.0045 +4 chany_top_in[4]:6 chany_top_in[4]:5 0.0045 +5 chany_top_in[4]:5 chany_top_in[4]:4 0.002044643 +6 chany_top_in[4]:8 chany_top_in[4]:7 0.0003035715 +7 chany_top_in[4]:9 chany_top_in[4]:8 0.0045 +8 chany_top_in[4]:11 chany_top_in[4]:10 0.0045 +9 chany_top_in[4]:10 chany_top_in[4]:9 0.0005267858 +10 chany_top_in[4]:12 chany_top_in[4]:11 0.0007410714 +11 chany_top_in[4]:13 chany_top_in[4]:12 0.0045 +12 chany_top_in[4]:14 chany_top_in[4]:13 0.000515625 +13 chany_top_in[4]:15 chany_top_in[4]:14 0.00341 +14 chany_top_in[4]:16 chany_top_in[4]:15 0.0009325583 +15 chany_top_in[4]:17 chany_top_in[4]:16 0.00341 +16 chany_top_in[4]:19 chany_top_in[4]:18 0.00341 +17 chany_top_in[4]:18 chany_top_in[4]:17 0.007561516 +18 chany_top_in[4]:21 chany_top_in[4]:20 0.00341 +19 chany_top_in[4]:20 chany_top_in[4]:19 0.0004280916 +20 chany_top_in[4]:23 chany_top_in[4]:22 0.0045 +21 chany_top_in[4]:22 chany_top_in[4]:21 0.0199442 +22 chany_top_in[4]:24 chany_top_in[4]:23 0.0159375 +23 chany_top_in[4]:25 chany_top_in[4]:24 0.0045 +24 chany_top_in[4]:7 chany_top_in[4]:6 0.004477679 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[1] 0.002719923 //LENGTH 21.175 LUMPCC 0.0002794318 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 19.625 66.640 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.655 60.860 +*I mux_left_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 24.020 63.580 +*I mux_left_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 22.180 68.680 +*N mux_tree_tapbuf_size5_2_sram[1]:4 *C 22.143 68.680 +*N mux_tree_tapbuf_size5_2_sram[1]:5 *C 20.285 68.680 +*N mux_tree_tapbuf_size5_2_sram[1]:6 *C 20.240 68.635 +*N mux_tree_tapbuf_size5_2_sram[1]:7 *C 20.240 66.640 +*N mux_tree_tapbuf_size5_2_sram[1]:8 *C 23.920 63.580 +*N mux_tree_tapbuf_size5_2_sram[1]:9 *C 23.920 63.535 +*N mux_tree_tapbuf_size5_2_sram[1]:10 *C 23.920 60.905 +*N mux_tree_tapbuf_size5_2_sram[1]:11 *C 23.875 60.860 +*N mux_tree_tapbuf_size5_2_sram[1]:12 *C 17.693 60.860 +*N mux_tree_tapbuf_size5_2_sram[1]:13 *C 19.780 60.860 +*N mux_tree_tapbuf_size5_2_sram[1]:14 *C 19.780 60.905 +*N mux_tree_tapbuf_size5_2_sram[1]:15 *C 19.780 66.640 +*N mux_tree_tapbuf_size5_2_sram[1]:16 *C 19.780 66.640 +*N mux_tree_tapbuf_size5_2_sram[1]:17 *C 19.625 66.640 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_3\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_3\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_2_sram[1]:4 0.0001444807 +5 mux_tree_tapbuf_size5_2_sram[1]:5 0.0001444807 +6 mux_tree_tapbuf_size5_2_sram[1]:6 0.0001243941 +7 mux_tree_tapbuf_size5_2_sram[1]:7 0.0001590902 +8 mux_tree_tapbuf_size5_2_sram[1]:8 3.365132e-05 +9 mux_tree_tapbuf_size5_2_sram[1]:9 0.0001673483 +10 mux_tree_tapbuf_size5_2_sram[1]:10 0.0001673483 +11 mux_tree_tapbuf_size5_2_sram[1]:11 0.0002178894 +12 mux_tree_tapbuf_size5_2_sram[1]:12 0.0001481859 +13 mux_tree_tapbuf_size5_2_sram[1]:13 0.0003989007 +14 mux_tree_tapbuf_size5_2_sram[1]:14 0.0002907481 +15 mux_tree_tapbuf_size5_2_sram[1]:15 0.0003254442 +16 mux_tree_tapbuf_size5_2_sram[1]:16 5.958218e-05 +17 mux_tree_tapbuf_size5_2_sram[1]:17 5.494698e-05 +18 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[2]:12 5.60789e-05 +19 mux_tree_tapbuf_size5_2_sram[1]:14 mux_tree_tapbuf_size5_2_sram[2]:8 7.119862e-05 +20 mux_tree_tapbuf_size5_2_sram[1]:14 mux_tree_tapbuf_size5_2_sram[2]:7 1.200992e-05 +21 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[2]:13 5.60789e-05 +22 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[2]:8 3.224224e-07 +23 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[2]:7 1.0606e-07 +24 mux_tree_tapbuf_size5_2_sram[1]:9 mux_tree_tapbuf_size5_2_sram[2]:8 1.0606e-07 +25 mux_tree_tapbuf_size5_2_sram[1]:9 mux_tree_tapbuf_size5_2_sram[2]:5 3.224224e-07 +26 mux_tree_tapbuf_size5_2_sram[1]:15 mux_tree_tapbuf_size5_2_sram[2]:8 1.200992e-05 +27 mux_tree_tapbuf_size5_2_sram[1]:15 mux_tree_tapbuf_size5_2_sram[2]:5 7.119862e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_2_sram[1]:17 0.152 +1 mux_tree_tapbuf_size5_2_sram[1]:12 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[1]:12 0.001863839 +3 mux_tree_tapbuf_size5_2_sram[1]:13 mux_tree_tapbuf_size5_2_sram[1]:11 0.00365625 +4 mux_tree_tapbuf_size5_2_sram[1]:14 mux_tree_tapbuf_size5_2_sram[1]:13 0.0045 +5 mux_tree_tapbuf_size5_2_sram[1]:11 mux_tree_tapbuf_size5_2_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size5_2_sram[1]:10 mux_tree_tapbuf_size5_2_sram[1]:9 0.002348214 +7 mux_tree_tapbuf_size5_2_sram[1]:8 mux_left_track_3\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size5_2_sram[1]:9 mux_tree_tapbuf_size5_2_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size5_2_sram[1]:5 mux_tree_tapbuf_size5_2_sram[1]:4 0.001658482 +10 mux_tree_tapbuf_size5_2_sram[1]:6 mux_tree_tapbuf_size5_2_sram[1]:5 0.0045 +11 mux_tree_tapbuf_size5_2_sram[1]:4 mux_left_track_3\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size5_2_sram[1]:16 mux_tree_tapbuf_size5_2_sram[1]:15 0.0045 +13 mux_tree_tapbuf_size5_2_sram[1]:15 mux_tree_tapbuf_size5_2_sram[1]:14 0.005120536 +14 mux_tree_tapbuf_size5_2_sram[1]:15 mux_tree_tapbuf_size5_2_sram[1]:7 0.0004107143 +15 mux_tree_tapbuf_size5_2_sram[1]:17 mux_tree_tapbuf_size5_2_sram[1]:16 8.423914e-05 +16 mux_tree_tapbuf_size5_2_sram[1]:7 mux_tree_tapbuf_size5_2_sram[1]:6 0.00178125 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_3_ccff_tail[0] 0.0009918212 //LENGTH 7.145 LUMPCC 0.0002252187 DR + +*CONN +*I mem_left_track_5\/FTB_4__9:X O *L 0 *C 27.315 45.560 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 25.470 49.980 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 *C 25.492 49.953 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 *C 25.505 49.640 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 *C 27.095 49.640 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 *C 27.140 49.595 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 *C 27.140 45.605 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 *C 27.140 45.560 +*N mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:8 *C 27.315 45.560 + +*CAP +0 mem_left_track_5\/FTB_4__9:X 1e-06 +1 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 2.907975e-05 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 0.0001491807 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.000120101 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0001722477 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 0.0001722477 +7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 6.07815e-05 +8 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:8 6.096416e-05 +9 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 prog_clk[0]:314 5.602902e-05 +10 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 prog_clk[0]:379 5.658033e-05 +11 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 prog_clk[0]:308 5.602902e-05 +12 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 prog_clk[0]:314 5.658033e-05 + +*RES +0 mem_left_track_5\/FTB_4__9:X mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 0.001419643 +3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:4 0.0045 +4 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 0.0045 +5 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 0.0035625 +6 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:8 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:7 9.51087e-05 +7 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:2 0.0002111487 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.004393409 //LENGTH 33.965 LUMPCC 0.001354882 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 36.055 52.360 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 14.260 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 14.298 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 16.515 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 16.560 41.865 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 16.560 43.462 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 16.568 43.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 34.953 43.520 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 34.960 43.578 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 34.960 52.315 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 35.005 52.360 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 36.017 52.360 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001531983 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001531983 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001089215 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001089215 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00066587 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00066587 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0004944985 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0004944985 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 9.577542e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 9.577542e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:297 0.000141487 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:306 3.437781e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:307 7.201844e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:301 3.437781e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:306 7.201844e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:307 0.000141487 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[13]:6 0.0004295577 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[13] 0.0004295577 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0009040179 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.00780134 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002880316 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001426339 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001979911 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001482254 //LENGTH 12.460 LUMPCC 0.0002322793 DR + +*CONN +*I mux_top_track_6\/mux_l2_in_1_:X O *L 0 *C 57.785 41.820 +*I mux_top_track_6\/mux_l3_in_0_:A0 I *L 0.001631 *C 63.195 47.940 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 63.158 47.940 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 62.145 47.940 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 62.100 47.895 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 62.100 41.865 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 62.055 41.820 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 57.823 41.820 + +*CAP +0 mux_top_track_6\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_6\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.319797e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.319797e-05 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003309919 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003309919 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002097976 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002097976 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:9 4.553625e-06 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:12 3.385787e-06 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:14 6.147552e-06 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.0001020527 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:6 4.553625e-06 +13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:9 3.385787e-06 +14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:13 6.147552e-06 +15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size5_1_sram[1]:4 0.0001020527 + +*RES +0 mux_top_track_6\/mux_l2_in_1_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_6\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0009040179 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005383929 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.003779018 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001303601 //LENGTH 9.770 LUMPCC 0.0003911672 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_1_:X O *L 0 *C 78.485 90.440 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 76.105 96.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 76.142 96.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 76.775 96.900 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 76.820 96.855 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 76.820 90.485 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 76.865 90.440 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 78.448 90.440 + +*CAP +0 mux_top_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.071297e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.071297e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002420559 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002420559 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001524478 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001524478 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[11]:11 6.072834e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[11] 6.072834e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.08405e-06 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.08405e-06 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000125948 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.823203e-06 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000125948 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.823203e-06 + +*RES +0 mux_top_track_24\/mux_l1_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001412946 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0056875 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005647321 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001149666 //LENGTH 9.030 LUMPCC 0.0002406559 DR + +*CONN +*I mux_top_track_18\/mux_l2_in_0_:X O *L 0 *C 56.295 91.460 +*I mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 55.465 99.080 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 55.465 99.080 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 55.660 98.940 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 55.660 98.895 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 55.660 91.505 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 55.705 91.460 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 56.258 91.460 + +*CAP +0 mux_top_track_18\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.404895e-05 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.819714e-05 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003437789 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003437789 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.360289e-05 +7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.360289e-05 +8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:155 5.94654e-05 +9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:154 5.94654e-05 +10 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_7_sram[1]:8 6.086256e-05 +11 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_7_sram[1]:9 6.086256e-05 + +*RES +0 mux_top_track_18\/mux_l2_in_0_:X mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001059783 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006598215 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001465625 //LENGTH 12.015 LUMPCC 0.0002157799 DR + +*CONN +*I mux_top_track_34\/mux_l1_in_0_:X O *L 0 *C 56.865 72.760 +*I mux_top_track_34\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.600 83.300 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.562 83.300 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.085 83.300 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.040 83.255 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 57.040 72.805 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 57.040 72.760 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 56.865 72.760 + +*CAP +0 mux_top_track_34\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_34\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.404459e-05 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.404459e-05 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005153989 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0005153989 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.668819e-05 +7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.226991e-05 +8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[1]:14 1.0009e-05 +9 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[1]:18 9.788094e-05 +10 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[1]:13 1.0009e-05 +11 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[1]:17 9.788094e-05 + +*RES +0 mux_top_track_34\/mux_l1_in_0_:X mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_34\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.009330358 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002792496 //LENGTH 23.795 LUMPCC 0.0003035039 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_0_:X O *L 0 *C 11.675 47.940 +*I mux_left_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 7.820 28.900 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 7.820 28.915 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 7.820 29.240 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 7.820 29.285 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 7.820 47.895 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 7.865 47.940 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 11.638 47.940 + +*CAP +0 mux_left_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.971963e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.684625e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0009319622 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0009319622 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002532511 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002532511 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[5]:4 8.93759e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[5]:5 8.93759e-05 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 ropt_net_134:6 4.600085e-07 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 ropt_net_134:10 6.191603e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 ropt_net_134:5 4.600085e-07 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 ropt_net_134:9 6.191603e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001766304 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.01661607 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003368304 + +*END + +*D_NET ropt_net_135 0.001353798 //LENGTH 9.900 LUMPCC 0.0003551689 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 4.140 11.560 +*I ropt_mt_inst_740:A I *L 0.001766 *C 3.220 9.520 +*N ropt_net_135:2 *C 3.220 9.520 +*N ropt_net_135:3 *C 3.220 9.565 +*N ropt_net_135:4 *C 3.220 10.200 +*N ropt_net_135:5 *C 4.120 10.200 +*N ropt_net_135:6 *C 4.128 10.200 +*N ropt_net_135:7 *C 6.893 10.200 +*N ropt_net_135:8 *C 6.900 10.258 +*N ropt_net_135:9 *C 6.900 11.515 +*N ropt_net_135:10 *C 6.855 11.560 +*N ropt_net_135:11 *C 4.178 11.560 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_135:2 3.322804e-05 +3 ropt_net_135:3 4.521263e-05 +4 ropt_net_135:4 9.603924e-05 +5 ropt_net_135:5 8.233628e-05 +6 ropt_net_135:6 9.268705e-05 +7 ropt_net_135:7 9.268705e-05 +8 ropt_net_135:8 8.901463e-05 +9 ropt_net_135:9 8.901463e-05 +10 ropt_net_135:10 0.0001882044 +11 ropt_net_135:11 0.0001882044 +12 ropt_net_135:6 chanx_left_out[4] 5.553371e-05 +13 ropt_net_135:7 chanx_left_out[4]:2 5.553371e-05 +14 ropt_net_135:6 chanx_left_out[18]:3 0.0001220508 +15 ropt_net_135:7 chanx_left_out[18]:4 0.0001220508 + +*RES +0 ropt_mt_inst_730:X ropt_net_135:11 0.152 +1 ropt_net_135:2 ropt_mt_inst_740:A 0.152 +2 ropt_net_135:3 ropt_net_135:2 0.0045 +3 ropt_net_135:5 ropt_net_135:4 0.0008035714 +4 ropt_net_135:6 ropt_net_135:5 0.00341 +5 ropt_net_135:8 ropt_net_135:7 0.00341 +6 ropt_net_135:7 ropt_net_135:6 0.0004331833 +7 ropt_net_135:10 ropt_net_135:9 0.0045 +8 ropt_net_135:9 ropt_net_135:8 0.001122768 +9 ropt_net_135:11 ropt_net_135:10 0.002390625 +10 ropt_net_135:4 ropt_net_135:3 0.0005669642 + +*END + +*D_NET chany_top_in[5] 0.01716555 //LENGTH 125.410 LUMPCC 0.003135996 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 60.260 102.070 +*I ropt_mt_inst_727:A I *L 0.001767 *C 7.360 36.720 +*N chany_top_in[5]:2 *C 7.360 36.720 +*N chany_top_in[5]:3 *C 7.360 36.720 +*N chany_top_in[5]:4 *C 6.900 36.720 +*N chany_top_in[5]:5 *C 6.900 44.495 +*N chany_top_in[5]:6 *C 6.945 44.540 +*N chany_top_in[5]:7 *C 17.940 44.540 +*N chany_top_in[5]:8 *C 17.940 44.880 +*N chany_top_in[5]:9 *C 19.320 44.880 +*N chany_top_in[5]:10 *C 19.320 44.200 +*N chany_top_in[5]:11 *C 33.535 44.200 +*N chany_top_in[5]:12 *C 33.580 44.245 +*N chany_top_in[5]:13 *C 33.580 44.835 +*N chany_top_in[5]:14 *C 33.625 44.880 +*N chany_top_in[5]:15 *C 35.835 44.880 +*N chany_top_in[5]:16 *C 35.880 44.835 +*N chany_top_in[5]:17 *C 35.880 44.258 +*N chany_top_in[5]:18 *C 35.888 44.200 +*N chany_top_in[5]:19 *C 57.940 44.200 +*N chany_top_in[5]:20 *C 57.960 44.208 +*N chany_top_in[5]:21 *C 57.960 97.913 +*N chany_top_in[5]:22 *C 57.980 97.920 +*N chany_top_in[5]:23 *C 60.253 97.920 +*N chany_top_in[5]:24 *C 60.260 97.978 + +*CAP +0 chany_top_in[5] 0.0002529025 +1 ropt_mt_inst_727:A 1e-06 +2 chany_top_in[5]:2 3.669738e-05 +3 chany_top_in[5]:3 6.630754e-05 +4 chany_top_in[5]:4 0.0004127487 +5 chany_top_in[5]:5 0.0003787066 +6 chany_top_in[5]:6 0.00070552 +7 chany_top_in[5]:7 0.0007279351 +8 chany_top_in[5]:8 7.844709e-05 +9 chany_top_in[5]:9 0.0001033333 +10 chany_top_in[5]:10 0.0008399197 +11 chany_top_in[5]:11 0.0007926184 +12 chany_top_in[5]:12 5.068809e-05 +13 chany_top_in[5]:13 5.068809e-05 +14 chany_top_in[5]:14 0.0001460924 +15 chany_top_in[5]:15 0.0001460924 +16 chany_top_in[5]:16 5.710234e-05 +17 chany_top_in[5]:17 5.710234e-05 +18 chany_top_in[5]:18 0.001117761 +19 chany_top_in[5]:19 0.001117761 +20 chany_top_in[5]:20 0.003103187 +21 chany_top_in[5]:21 0.003103187 +22 chany_top_in[5]:22 0.0002154284 +23 chany_top_in[5]:23 0.0002154284 +24 chany_top_in[5]:24 0.0002529025 +25 chany_top_in[5]:18 chany_top_in[8]:6 0.0005029559 +26 chany_top_in[5]:19 chany_top_in[8]:7 0.0005029559 +27 chany_top_in[5]:20 chany_top_in[16]:9 0.0003789556 +28 chany_top_in[5]:21 chany_top_in[16]:10 0.0003789556 +29 chany_top_in[5]:6 chanx_left_in[13] 5.103622e-06 +30 chany_top_in[5]:11 chanx_left_in[13]:6 7.420437e-06 +31 chany_top_in[5]:18 chanx_left_in[13] 0.0003013576 +32 chany_top_in[5]:19 chanx_left_in[13]:6 0.0003013576 +33 chany_top_in[5]:7 chanx_left_in[13]:6 5.103622e-06 +34 chany_top_in[5]:10 chanx_left_in[13] 7.420437e-06 +35 chany_top_in[5]:11 mux_tree_tapbuf_size6_3_sram[2]:4 0.0001637995 +36 chany_top_in[5]:12 mux_tree_tapbuf_size6_3_sram[2]:6 3.237508e-07 +37 chany_top_in[5]:13 mux_tree_tapbuf_size6_3_sram[2]:5 3.237508e-07 +38 chany_top_in[5]:10 mux_tree_tapbuf_size6_3_sram[2]:3 0.0001637995 +39 chany_top_in[5]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.955796e-05 +40 chany_top_in[5]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 1.542068e-06 +41 chany_top_in[5]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.955796e-05 +42 chany_top_in[5]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.760598e-05 +43 chany_top_in[5]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.760598e-05 +44 chany_top_in[5]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.542068e-06 +45 chany_top_in[5]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.93759e-05 +46 chany_top_in[5]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.93759e-05 + +*RES +0 chany_top_in[5] chany_top_in[5]:24 0.003654019 +1 chany_top_in[5]:2 ropt_mt_inst_727:A 0.152 +2 chany_top_in[5]:3 chany_top_in[5]:2 0.0045 +3 chany_top_in[5]:6 chany_top_in[5]:5 0.0045 +4 chany_top_in[5]:5 chany_top_in[5]:4 0.006941964 +5 chany_top_in[5]:11 chany_top_in[5]:10 0.01269197 +6 chany_top_in[5]:12 chany_top_in[5]:11 0.0045 +7 chany_top_in[5]:14 chany_top_in[5]:13 0.0045 +8 chany_top_in[5]:13 chany_top_in[5]:12 0.0005267857 +9 chany_top_in[5]:15 chany_top_in[5]:14 0.001973214 +10 chany_top_in[5]:16 chany_top_in[5]:15 0.0045 +11 chany_top_in[5]:17 chany_top_in[5]:16 0.000515625 +12 chany_top_in[5]:18 chany_top_in[5]:17 0.00341 +13 chany_top_in[5]:19 chany_top_in[5]:18 0.003454891 +14 chany_top_in[5]:20 chany_top_in[5]:19 0.00341 +15 chany_top_in[5]:22 chany_top_in[5]:21 0.00341 +16 chany_top_in[5]:21 chany_top_in[5]:20 0.008413782 +17 chany_top_in[5]:24 chany_top_in[5]:23 0.00341 +18 chany_top_in[5]:23 chany_top_in[5]:22 0.000356025 +19 chany_top_in[5]:7 chany_top_in[5]:6 0.009816965 +20 chany_top_in[5]:8 chany_top_in[5]:7 0.0003035714 +21 chany_top_in[5]:9 chany_top_in[5]:8 0.001232143 +22 chany_top_in[5]:10 chany_top_in[5]:9 0.0006071428 +23 chany_top_in[5]:4 chany_top_in[5]:3 0.0004107143 + +*END + +*D_NET chany_top_in[18] 0.01610339 //LENGTH 112.955 LUMPCC 0.005114437 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 84.640 102.070 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 24.480 56.100 +*N chany_top_in[18]:2 *C 24.380 56.100 +*N chany_top_in[18]:3 *C 24.380 56.100 +*N chany_top_in[18]:4 *C 24.380 56.440 +*N chany_top_in[18]:5 *C 24.388 56.440 +*N chany_top_in[18]:6 *C 74.215 56.440 +*N chany_top_in[18]:7 *C 87.380 56.440 +*N chany_top_in[18]:8 *C 87.400 56.448 +*N chany_top_in[18]:9 *C 87.400 91.113 +*N chany_top_in[18]:10 *C 87.380 91.120 +*N chany_top_in[18]:11 *C 84.648 91.120 +*N chany_top_in[18]:12 *C 84.640 91.178 + +*CAP +0 chany_top_in[18] 0.0005406264 +1 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[18]:2 3.611028e-05 +3 chany_top_in[18]:3 5.964376e-05 +4 chany_top_in[18]:4 6.39744e-05 +5 chany_top_in[18]:5 0.001828807 +6 chany_top_in[18]:6 0.002656233 +7 chany_top_in[18]:7 0.0008274259 +8 chany_top_in[18]:8 0.002020204 +9 chany_top_in[18]:9 0.002020204 +10 chany_top_in[18]:10 0.0001970516 +11 chany_top_in[18]:11 0.0001970516 +12 chany_top_in[18]:12 0.0005406264 +13 chany_top_in[18]:5 chany_top_in[3]:9 0.0009619963 +14 chany_top_in[18]:6 chany_top_in[3]:10 0.0009619963 +15 chany_top_in[18]:5 prog_clk[0]:191 0.0001052468 +16 chany_top_in[18]:5 prog_clk[0]:381 0.000145638 +17 chany_top_in[18]:5 prog_clk[0]:393 6.306248e-07 +18 chany_top_in[18]:8 prog_clk[0]:119 1.234088e-05 +19 chany_top_in[18]:9 prog_clk[0]:91 1.234088e-05 +20 chany_top_in[18]:6 prog_clk[0]:190 0.0001052468 +21 chany_top_in[18]:6 prog_clk[0]:382 0.000145638 +22 chany_top_in[18]:6 prog_clk[0]:388 6.306248e-07 +23 chany_top_in[18]:5 chanx_left_in[2] 0.0008283031 +24 chany_top_in[18]:5 chanx_left_in[2]:7 0.0004407342 +25 chany_top_in[18]:6 chanx_left_in[2]:6 0.0004407342 +26 chany_top_in[18]:6 chanx_left_in[2]:8 0.0008283031 +27 chany_top_in[18] mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 6.232818e-05 +28 chany_top_in[18]:12 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 6.232818e-05 + +*RES +0 chany_top_in[18] chany_top_in[18]:12 0.009725447 +1 chany_top_in[18]:2 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[18]:3 chany_top_in[18]:2 0.0045 +3 chany_top_in[18]:4 chany_top_in[18]:3 0.0001634616 +4 chany_top_in[18]:5 chany_top_in[18]:4 0.00341 +5 chany_top_in[18]:7 chany_top_in[18]:6 0.002062517 +6 chany_top_in[18]:8 chany_top_in[18]:7 0.00341 +7 chany_top_in[18]:10 chany_top_in[18]:9 0.00341 +8 chany_top_in[18]:9 chany_top_in[18]:8 0.00543085 +9 chany_top_in[18]:12 chany_top_in[18]:11 0.00341 +10 chany_top_in[18]:11 chany_top_in[18]:10 0.0004280916 +11 chany_top_in[18]:6 chany_top_in[18]:5 0.007806308 + +*END + +*D_NET top_left_grid_pin_36_[0] 0.01454268 //LENGTH 116.335 LUMPCC 0.002279683 DR + +*CONN +*P top_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 93.840 +*I mux_top_track_28\/mux_l1_in_0_:A1 I *L 0.00198 *C 35.420 94.180 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 79.295 75.140 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 75.615 60.520 +*I mux_top_track_12\/mux_l1_in_0_:A1 I *L 0.00198 *C 71.760 34.340 +*N top_left_grid_pin_36_[0]:5 *C 71.797 34.340 +*N top_left_grid_pin_36_[0]:6 *C 72.175 34.340 +*N top_left_grid_pin_36_[0]:7 *C 72.220 34.385 +*N top_left_grid_pin_36_[0]:8 *C 75.578 60.520 +*N top_left_grid_pin_36_[0]:9 *C 72.265 60.520 +*N top_left_grid_pin_36_[0]:10 *C 72.220 60.520 +*N top_left_grid_pin_36_[0]:11 *C 79.258 75.140 +*N top_left_grid_pin_36_[0]:12 *C 72.265 75.140 +*N top_left_grid_pin_36_[0]:13 *C 72.220 75.095 +*N top_left_grid_pin_36_[0]:14 *C 71.760 75.140 +*N top_left_grid_pin_36_[0]:15 *C 71.760 82.223 +*N top_left_grid_pin_36_[0]:16 *C 71.752 82.280 +*N top_left_grid_pin_36_[0]:17 *C 35.888 82.280 +*N top_left_grid_pin_36_[0]:18 *C 35.880 82.338 +*N top_left_grid_pin_36_[0]:19 *C 35.458 94.180 +*N top_left_grid_pin_36_[0]:20 *C 35.835 94.180 +*N top_left_grid_pin_36_[0]:21 *C 35.880 94.180 +*N top_left_grid_pin_36_[0]:22 *C 35.880 93.782 +*N top_left_grid_pin_36_[0]:23 *C 35.873 93.840 + +*CAP +0 top_left_grid_pin_36_[0] 0.0004445532 +1 mux_top_track_28\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +3 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +4 mux_top_track_12\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_36_[0]:5 4.510565e-05 +6 top_left_grid_pin_36_[0]:6 4.510565e-05 +7 top_left_grid_pin_36_[0]:7 0.001304784 +8 top_left_grid_pin_36_[0]:8 0.0002312821 +9 top_left_grid_pin_36_[0]:9 0.0002312821 +10 top_left_grid_pin_36_[0]:10 0.0020179 +11 top_left_grid_pin_36_[0]:11 0.0004715637 +12 top_left_grid_pin_36_[0]:12 0.0004715637 +13 top_left_grid_pin_36_[0]:13 0.0007133695 +14 top_left_grid_pin_36_[0]:14 0.0003265089 +15 top_left_grid_pin_36_[0]:15 0.0002950697 +16 top_left_grid_pin_36_[0]:16 0.001930813 +17 top_left_grid_pin_36_[0]:17 0.001930813 +18 top_left_grid_pin_36_[0]:18 0.000594822 +19 top_left_grid_pin_36_[0]:19 4.628714e-05 +20 top_left_grid_pin_36_[0]:20 4.628714e-05 +21 top_left_grid_pin_36_[0]:21 5.234018e-05 +22 top_left_grid_pin_36_[0]:22 0.0006149973 +23 top_left_grid_pin_36_[0]:23 0.0004445532 +24 top_left_grid_pin_36_[0]:17 chany_top_in[11]:9 0.0004937629 +25 top_left_grid_pin_36_[0]:16 chany_top_in[11]:10 0.0004937629 +26 top_left_grid_pin_36_[0]:17 chanx_left_in[11]:7 0.0002809081 +27 top_left_grid_pin_36_[0]:16 chanx_left_in[11]:6 0.0002809081 +28 top_left_grid_pin_36_[0]:10 mux_tree_tapbuf_size2_12_sram[1]:8 8.630267e-05 +29 top_left_grid_pin_36_[0]:13 mux_tree_tapbuf_size2_12_sram[1]:9 8.630267e-05 +30 top_left_grid_pin_36_[0]:15 mux_tree_tapbuf_size2_12_sram[1]:4 6.055623e-05 +31 top_left_grid_pin_36_[0]:15 mux_tree_tapbuf_size2_12_sram[1]:9 1.417593e-05 +32 top_left_grid_pin_36_[0]:15 mux_tree_tapbuf_size2_12_sram[1]:6 3.749115e-05 +33 top_left_grid_pin_36_[0]:14 mux_tree_tapbuf_size2_12_sram[1]:8 1.417593e-05 +34 top_left_grid_pin_36_[0]:14 mux_tree_tapbuf_size2_12_sram[1]:9 3.749115e-05 +35 top_left_grid_pin_36_[0]:14 mux_tree_tapbuf_size2_12_sram[1]:5 6.055623e-05 +36 top_left_grid_pin_36_[0]:22 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 6.18264e-05 +37 top_left_grid_pin_36_[0]:18 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 6.18264e-05 +38 top_left_grid_pin_36_[0]:7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 5.281462e-05 +39 top_left_grid_pin_36_[0]:10 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 5.281462e-05 +40 top_left_grid_pin_36_[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.200345e-05 +41 top_left_grid_pin_36_[0]:10 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.200345e-05 + +*RES +0 top_left_grid_pin_36_[0] top_left_grid_pin_36_[0]:23 0.0009591916 +1 top_left_grid_pin_36_[0]:6 top_left_grid_pin_36_[0]:5 0.0003370536 +2 top_left_grid_pin_36_[0]:7 top_left_grid_pin_36_[0]:6 0.0045 +3 top_left_grid_pin_36_[0]:5 mux_top_track_12\/mux_l1_in_0_:A1 0.152 +4 top_left_grid_pin_36_[0]:9 top_left_grid_pin_36_[0]:8 0.002957589 +5 top_left_grid_pin_36_[0]:10 top_left_grid_pin_36_[0]:9 0.0045 +6 top_left_grid_pin_36_[0]:10 top_left_grid_pin_36_[0]:7 0.02333482 +7 top_left_grid_pin_36_[0]:8 mux_top_track_4\/mux_l1_in_0_:A0 0.152 +8 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:11 0.006243303 +9 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:12 0.0045 +10 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:10 0.01301339 +11 top_left_grid_pin_36_[0]:11 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +12 top_left_grid_pin_36_[0]:22 top_left_grid_pin_36_[0]:21 0.0001911058 +13 top_left_grid_pin_36_[0]:22 top_left_grid_pin_36_[0]:18 0.01021875 +14 top_left_grid_pin_36_[0]:23 top_left_grid_pin_36_[0]:22 0.00341 +15 top_left_grid_pin_36_[0]:19 mux_top_track_28\/mux_l1_in_0_:A1 0.152 +16 top_left_grid_pin_36_[0]:20 top_left_grid_pin_36_[0]:19 0.0003370536 +17 top_left_grid_pin_36_[0]:21 top_left_grid_pin_36_[0]:20 0.0045 +18 top_left_grid_pin_36_[0]:18 top_left_grid_pin_36_[0]:17 0.00341 +19 top_left_grid_pin_36_[0]:17 top_left_grid_pin_36_[0]:16 0.00561885 +20 top_left_grid_pin_36_[0]:15 top_left_grid_pin_36_[0]:14 0.006323661 +21 top_left_grid_pin_36_[0]:16 top_left_grid_pin_36_[0]:15 0.00341 +22 top_left_grid_pin_36_[0]:14 top_left_grid_pin_36_[0]:13 0.0004107143 + +*END + +*D_NET top_left_grid_pin_41_[0] 0.01027704 //LENGTH 66.365 LUMPCC 0.004105217 DR + +*CONN +*P top_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 90.440 +*I mux_top_track_22\/mux_l1_in_0_:A1 I *L 0.00198 *C 61.280 85.340 +*I mux_top_track_38\/mux_l1_in_0_:A1 I *L 0.00198 *C 57.600 69.020 +*I mux_top_track_6\/mux_l1_in_1_:A0 I *L 0.001631 *C 57.215 64.600 +*I mux_top_track_2\/mux_l1_in_1_:A0 I *L 0.001631 *C 61.470 64.260 +*N top_left_grid_pin_41_[0]:5 *C 61.433 64.260 +*N top_left_grid_pin_41_[0]:6 *C 57.500 64.260 +*N top_left_grid_pin_41_[0]:7 *C 57.215 64.600 +*N top_left_grid_pin_41_[0]:8 *C 57.500 64.600 +*N top_left_grid_pin_41_[0]:9 *C 57.500 64.645 +*N top_left_grid_pin_41_[0]:10 *C 57.600 69.020 +*N top_left_grid_pin_41_[0]:11 *C 57.500 68.680 +*N top_left_grid_pin_41_[0]:12 *C 57.500 68.680 +*N top_left_grid_pin_41_[0]:13 *C 57.500 71.400 +*N top_left_grid_pin_41_[0]:14 *C 59.800 71.400 +*N top_left_grid_pin_41_[0]:15 *C 61.242 85.340 +*N top_left_grid_pin_41_[0]:16 *C 59.845 85.340 +*N top_left_grid_pin_41_[0]:17 *C 59.800 85.340 +*N top_left_grid_pin_41_[0]:18 *C 59.800 90.383 +*N top_left_grid_pin_41_[0]:19 *C 59.793 90.440 + +*CAP +0 top_left_grid_pin_41_[0] 0.001386462 +1 mux_top_track_22\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_38\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_1_:A0 1e-06 +4 mux_top_track_2\/mux_l1_in_1_:A0 1e-06 +5 top_left_grid_pin_41_[0]:5 0.0002425342 +6 top_left_grid_pin_41_[0]:6 0.0002702974 +7 top_left_grid_pin_41_[0]:7 2.852682e-05 +8 top_left_grid_pin_41_[0]:8 8.256364e-05 +9 top_left_grid_pin_41_[0]:9 0.0002318589 +10 top_left_grid_pin_41_[0]:10 6.720347e-05 +11 top_left_grid_pin_41_[0]:11 7.222872e-05 +12 top_left_grid_pin_41_[0]:12 0.000411696 +13 top_left_grid_pin_41_[0]:13 0.0002566372 +14 top_left_grid_pin_41_[0]:14 0.0006059561 +15 top_left_grid_pin_41_[0]:15 0.0001190205 +16 top_left_grid_pin_41_[0]:16 0.0001190205 +17 top_left_grid_pin_41_[0]:17 0.0007081234 +18 top_left_grid_pin_41_[0]:18 0.0001792297 +19 top_left_grid_pin_41_[0]:19 0.001386462 +20 top_left_grid_pin_41_[0] top_left_grid_pin_34_[0]:28 0.001132943 +21 top_left_grid_pin_41_[0]:19 top_left_grid_pin_34_[0]:27 0.001132943 +22 top_left_grid_pin_41_[0]:18 chanx_left_in[9]:4 2.237331e-05 +23 top_left_grid_pin_41_[0]:16 chanx_left_in[9]:3 6.979258e-06 +24 top_left_grid_pin_41_[0]:17 chanx_left_in[9]:4 0.0002919972 +25 top_left_grid_pin_41_[0]:17 chanx_left_in[9]:5 2.237331e-05 +26 top_left_grid_pin_41_[0]:15 chanx_left_in[9]:2 6.979258e-06 +27 top_left_grid_pin_41_[0]:14 chanx_left_in[9]:5 0.0002919972 +28 top_left_grid_pin_41_[0]:17 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.0001405298 +29 top_left_grid_pin_41_[0]:13 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 1.586754e-05 +30 top_left_grid_pin_41_[0]:14 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 1.586754e-05 +31 top_left_grid_pin_41_[0]:14 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.0001405298 +32 top_left_grid_pin_41_[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.499217e-05 +33 top_left_grid_pin_41_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.499217e-05 +34 top_left_grid_pin_41_[0] mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000218412 +35 top_left_grid_pin_41_[0]:19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000218412 +36 top_left_grid_pin_41_[0]:18 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001398927 +37 top_left_grid_pin_41_[0]:17 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.862102e-05 +38 top_left_grid_pin_41_[0]:17 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001398927 +39 top_left_grid_pin_41_[0]:14 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.862102e-05 + +*RES +0 top_left_grid_pin_41_[0] top_left_grid_pin_41_[0]:19 0.004706658 +1 top_left_grid_pin_41_[0]:18 top_left_grid_pin_41_[0]:17 0.004502233 +2 top_left_grid_pin_41_[0]:19 top_left_grid_pin_41_[0]:18 0.00341 +3 top_left_grid_pin_41_[0]:11 top_left_grid_pin_41_[0]:10 0.0001847826 +4 top_left_grid_pin_41_[0]:12 top_left_grid_pin_41_[0]:11 0.0045 +5 top_left_grid_pin_41_[0]:12 top_left_grid_pin_41_[0]:9 0.003602678 +6 top_left_grid_pin_41_[0]:10 mux_top_track_38\/mux_l1_in_0_:A1 0.152 +7 top_left_grid_pin_41_[0]:7 mux_top_track_6\/mux_l1_in_1_:A0 0.152 +8 top_left_grid_pin_41_[0]:16 top_left_grid_pin_41_[0]:15 0.001247768 +9 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:16 0.0045 +10 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:14 0.01244643 +11 top_left_grid_pin_41_[0]:15 mux_top_track_22\/mux_l1_in_0_:A1 0.152 +12 top_left_grid_pin_41_[0]:5 mux_top_track_2\/mux_l1_in_1_:A0 0.152 +13 top_left_grid_pin_41_[0]:8 top_left_grid_pin_41_[0]:7 0.0001548913 +14 top_left_grid_pin_41_[0]:8 top_left_grid_pin_41_[0]:6 0.0003035715 +15 top_left_grid_pin_41_[0]:9 top_left_grid_pin_41_[0]:8 0.0045 +16 top_left_grid_pin_41_[0]:6 top_left_grid_pin_41_[0]:5 0.003511161 +17 top_left_grid_pin_41_[0]:13 top_left_grid_pin_41_[0]:12 0.002428572 +18 top_left_grid_pin_41_[0]:14 top_left_grid_pin_41_[0]:13 0.002053571 + +*END + +*D_NET chanx_left_in[2] 0.01297185 //LENGTH 88.880 LUMPCC 0.00432159 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 57.120 +*I mux_top_track_36\/mux_l1_in_0_:A0 I *L 0.001631 *C 63.195 82.620 +*N chanx_left_in[2]:2 *C 63.158 82.620 +*N chanx_left_in[2]:3 *C 62.145 82.620 +*N chanx_left_in[2]:4 *C 62.100 82.575 +*N chanx_left_in[2]:5 *C 62.100 57.858 +*N chanx_left_in[2]:6 *C 62.093 57.800 +*N chanx_left_in[2]:7 *C 39.100 57.800 +*N chanx_left_in[2]:8 *C 39.100 57.120 + +*CAP +0 chanx_left_in[2] 0.001521829 +1 mux_top_track_36\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[2]:2 0.000104421 +3 chanx_left_in[2]:3 0.000104421 +4 chanx_left_in[2]:4 0.001333596 +5 chanx_left_in[2]:5 0.001333596 +6 chanx_left_in[2]:6 0.001306042 +7 chanx_left_in[2]:7 0.001364785 +8 chanx_left_in[2]:8 0.001580573 +9 chanx_left_in[2] chany_top_in[18]:5 0.0008283031 +10 chanx_left_in[2]:6 chany_top_in[18]:6 0.0004407342 +11 chanx_left_in[2]:8 chany_top_in[18]:6 0.0008283031 +12 chanx_left_in[2]:7 chany_top_in[18]:5 0.0004407342 +13 chanx_left_in[2] chanx_left_in[6]:7 0.0006394698 +14 chanx_left_in[2]:8 chanx_left_in[6]:6 0.0006394698 +15 chanx_left_in[2] mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001315548 +16 chanx_left_in[2]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001315548 +17 chanx_left_in[2] ropt_net_127:7 0.0001207331 +18 chanx_left_in[2]:8 ropt_net_127:8 0.0001207331 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:8 0.005932966 +1 chanx_left_in[2]:2 mux_top_track_36\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[2]:3 chanx_left_in[2]:2 0.0009040179 +3 chanx_left_in[2]:4 chanx_left_in[2]:3 0.0045 +4 chanx_left_in[2]:5 chanx_left_in[2]:4 0.0220692 +5 chanx_left_in[2]:6 chanx_left_in[2]:5 0.00341 +6 chanx_left_in[2]:8 chanx_left_in[2]:7 0.0001065333 +7 chanx_left_in[2]:7 chanx_left_in[2]:6 0.003602158 + +*END + +*D_NET chanx_left_in[7] 0.00931745 //LENGTH 69.275 LUMPCC 0.001062202 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 70.720 +*I mux_top_track_26\/mux_l1_in_0_:A0 I *L 0.001631 *C 51.695 87.720 +*N chanx_left_in[7]:2 *C 51.658 87.720 +*N chanx_left_in[7]:3 *C 47.885 87.720 +*N chanx_left_in[7]:4 *C 47.840 87.720 +*N chanx_left_in[7]:5 *C 47.833 87.720 +*N chanx_left_in[7]:6 *C 34.968 87.720 +*N chanx_left_in[7]:7 *C 34.960 87.663 +*N chanx_left_in[7]:8 *C 34.960 71.445 +*N chanx_left_in[7]:9 *C 34.915 71.400 +*N chanx_left_in[7]:10 *C 5.565 71.400 +*N chanx_left_in[7]:11 *C 5.520 71.355 +*N chanx_left_in[7]:12 *C 5.520 70.778 +*N chanx_left_in[7]:13 *C 5.513 70.720 + +*CAP +0 chanx_left_in[7] 0.0003055229 +1 mux_top_track_26\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[7]:2 0.000280743 +3 chanx_left_in[7]:3 0.000280743 +4 chanx_left_in[7]:4 3.574622e-05 +5 chanx_left_in[7]:5 0.0008718724 +6 chanx_left_in[7]:6 0.0008718724 +7 chanx_left_in[7]:7 0.0009037848 +8 chanx_left_in[7]:8 0.0009037848 +9 chanx_left_in[7]:9 0.001690267 +10 chanx_left_in[7]:10 0.001690267 +11 chanx_left_in[7]:11 5.706158e-05 +12 chanx_left_in[7]:12 5.706158e-05 +13 chanx_left_in[7]:13 0.0003055229 +14 chanx_left_in[7]:7 mux_tree_tapbuf_size2_15_sram[0]:14 2.250488e-05 +15 chanx_left_in[7]:9 mux_tree_tapbuf_size2_15_sram[0]:8 6.323623e-05 +16 chanx_left_in[7]:9 mux_tree_tapbuf_size2_15_sram[0]:5 0.0002510672 +17 chanx_left_in[7]:9 mux_tree_tapbuf_size2_15_sram[0]:7 2.289215e-05 +18 chanx_left_in[7]:8 mux_tree_tapbuf_size2_15_sram[0]:15 2.250488e-05 +19 chanx_left_in[7]:10 mux_tree_tapbuf_size2_15_sram[0]:4 0.0002510672 +20 chanx_left_in[7]:10 mux_tree_tapbuf_size2_15_sram[0]:6 2.289215e-05 +21 chanx_left_in[7]:10 mux_tree_tapbuf_size2_15_sram[0]:7 6.323623e-05 +22 chanx_left_in[7]:9 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 0.0001714006 +23 chanx_left_in[7]:10 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 0.0001714006 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:13 0.0006709249 +1 chanx_left_in[7]:2 mux_top_track_26\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[7]:3 chanx_left_in[7]:2 0.003368304 +3 chanx_left_in[7]:4 chanx_left_in[7]:3 0.0045 +4 chanx_left_in[7]:5 chanx_left_in[7]:4 0.00341 +5 chanx_left_in[7]:7 chanx_left_in[7]:6 0.00341 +6 chanx_left_in[7]:6 chanx_left_in[7]:5 0.002015517 +7 chanx_left_in[7]:9 chanx_left_in[7]:8 0.0045 +8 chanx_left_in[7]:8 chanx_left_in[7]:7 0.01447991 +9 chanx_left_in[7]:10 chanx_left_in[7]:9 0.02620536 +10 chanx_left_in[7]:11 chanx_left_in[7]:10 0.0045 +11 chanx_left_in[7]:12 chanx_left_in[7]:11 0.0005156251 +12 chanx_left_in[7]:13 chanx_left_in[7]:12 0.00341 + +*END + +*D_NET chanx_left_in[10] 0.01471317 //LENGTH 94.095 LUMPCC 0.005331586 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 67.320 +*I mux_top_track_20\/mux_l1_in_0_:A0 I *L 0.001631 *C 76.995 80.580 +*N chanx_left_in[10]:2 *C 76.958 80.580 +*N chanx_left_in[10]:3 *C 76.405 80.580 +*N chanx_left_in[10]:4 *C 76.360 80.535 +*N chanx_left_in[10]:5 *C 76.360 79.618 +*N chanx_left_in[10]:6 *C 76.353 79.560 +*N chanx_left_in[10]:7 *C 71.300 79.560 +*N chanx_left_in[10]:8 *C 71.300 80.240 +*N chanx_left_in[10]:9 *C 54.288 80.240 +*N chanx_left_in[10]:10 *C 54.280 80.240 +*N chanx_left_in[10]:11 *C 54.280 80.580 +*N chanx_left_in[10]:12 *C 54.235 80.580 +*N chanx_left_in[10]:13 *C 30.405 80.580 +*N chanx_left_in[10]:14 *C 30.360 80.535 +*N chanx_left_in[10]:15 *C 30.360 74.165 +*N chanx_left_in[10]:16 *C 30.315 74.120 +*N chanx_left_in[10]:17 *C 28.565 74.120 +*N chanx_left_in[10]:18 *C 28.520 74.075 +*N chanx_left_in[10]:19 *C 28.520 67.377 +*N chanx_left_in[10]:20 *C 28.513 67.320 + +*CAP +0 chanx_left_in[10] 0.001242895 +1 mux_top_track_20\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[10]:2 3.026909e-05 +3 chanx_left_in[10]:3 3.026909e-05 +4 chanx_left_in[10]:4 6.148658e-05 +5 chanx_left_in[10]:5 6.148658e-05 +6 chanx_left_in[10]:6 0.0003640997 +7 chanx_left_in[10]:7 0.000431762 +8 chanx_left_in[10]:8 0.001217628 +9 chanx_left_in[10]:9 0.001149965 +10 chanx_left_in[10]:10 5.689728e-05 +11 chanx_left_in[10]:11 5.298085e-05 +12 chanx_left_in[10]:12 0.0008955187 +13 chanx_left_in[10]:13 0.0008955187 +14 chanx_left_in[10]:14 0.0003084224 +15 chanx_left_in[10]:15 0.0003084224 +16 chanx_left_in[10]:16 0.0001784608 +17 chanx_left_in[10]:17 0.0001784608 +18 chanx_left_in[10]:18 0.0003365731 +19 chanx_left_in[10]:19 0.0003365731 +20 chanx_left_in[10]:20 0.001242895 +21 chanx_left_in[10] prog_clk[0]:458 6.904453e-05 +22 chanx_left_in[10]:9 prog_clk[0]:212 7.010862e-06 +23 chanx_left_in[10]:9 prog_clk[0]:216 3.891332e-05 +24 chanx_left_in[10]:9 prog_clk[0]:221 1.985504e-05 +25 chanx_left_in[10]:9 prog_clk[0]:225 3.298575e-06 +26 chanx_left_in[10]:14 prog_clk[0]:466 0.0001851087 +27 chanx_left_in[10]:15 prog_clk[0]:465 0.0001851087 +28 chanx_left_in[10]:18 prog_clk[0]:464 5.77234e-05 +29 chanx_left_in[10]:19 prog_clk[0]:396 5.77234e-05 +30 chanx_left_in[10]:20 prog_clk[0]:459 6.904453e-05 +31 chanx_left_in[10]:8 prog_clk[0]:183 7.010862e-06 +32 chanx_left_in[10]:8 prog_clk[0]:212 3.891332e-05 +33 chanx_left_in[10]:8 prog_clk[0]:216 1.985504e-05 +34 chanx_left_in[10]:8 prog_clk[0]:221 3.298575e-06 +35 chanx_left_in[10]:9 chany_top_in[7]:7 5.076335e-06 +36 chanx_left_in[10]:12 chany_top_in[7]:6 8.277514e-05 +37 chanx_left_in[10]:12 chany_top_in[7]:8 0.0001758679 +38 chanx_left_in[10]:13 chany_top_in[7]:5 8.277514e-05 +39 chanx_left_in[10]:13 chany_top_in[7]:7 0.0001758679 +40 chanx_left_in[10]:8 chany_top_in[7]:8 5.076335e-06 +41 chanx_left_in[10]:2 top_left_grid_pin_40_[0]:14 6.74664e-08 +42 chanx_left_in[10]:2 top_left_grid_pin_40_[0]:18 3.451919e-05 +43 chanx_left_in[10]:3 top_left_grid_pin_40_[0]:13 6.74664e-08 +44 chanx_left_in[10]:3 top_left_grid_pin_40_[0]:22 3.451919e-05 +45 chanx_left_in[10]:4 top_left_grid_pin_40_[0]:16 8.003967e-06 +46 chanx_left_in[10]:5 top_left_grid_pin_40_[0]:15 8.003967e-06 +47 chanx_left_in[10]:9 top_left_grid_pin_40_[0]:22 9.816769e-06 +48 chanx_left_in[10]:12 top_left_grid_pin_40_[0]:22 0.0006288396 +49 chanx_left_in[10]:13 top_left_grid_pin_40_[0]:23 0.0006288396 +50 chanx_left_in[10]:8 top_left_grid_pin_40_[0]:18 9.816769e-06 +51 chanx_left_in[10]:12 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 6.871285e-05 +52 chanx_left_in[10]:13 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 6.871285e-05 +53 chanx_left_in[10] mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001271159 +54 chanx_left_in[10]:20 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001271159 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:20 0.004274258 +1 chanx_left_in[10]:2 mux_top_track_20\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[10]:3 chanx_left_in[10]:2 0.0004933036 +3 chanx_left_in[10]:4 chanx_left_in[10]:3 0.0045 +4 chanx_left_in[10]:5 chanx_left_in[10]:4 0.0008191965 +5 chanx_left_in[10]:6 chanx_left_in[10]:5 0.00341 +6 chanx_left_in[10]:10 chanx_left_in[10]:9 0.00341 +7 chanx_left_in[10]:9 chanx_left_in[10]:8 0.002665292 +8 chanx_left_in[10]:12 chanx_left_in[10]:11 0.0045 +9 chanx_left_in[10]:11 chanx_left_in[10]:10 0.0001634615 +10 chanx_left_in[10]:13 chanx_left_in[10]:12 0.02127679 +11 chanx_left_in[10]:14 chanx_left_in[10]:13 0.0045 +12 chanx_left_in[10]:16 chanx_left_in[10]:15 0.0045 +13 chanx_left_in[10]:15 chanx_left_in[10]:14 0.0056875 +14 chanx_left_in[10]:17 chanx_left_in[10]:16 0.0015625 +15 chanx_left_in[10]:18 chanx_left_in[10]:17 0.0045 +16 chanx_left_in[10]:19 chanx_left_in[10]:18 0.005979911 +17 chanx_left_in[10]:20 chanx_left_in[10]:19 0.00341 +18 chanx_left_in[10]:8 chanx_left_in[10]:7 0.0001065333 +19 chanx_left_in[10]:7 chanx_left_in[10]:6 0.0007915583 + +*END + +*D_NET left_top_grid_pin_42_[0] 0.01168969 //LENGTH 78.920 LUMPCC 0.003155579 DR + +*CONN +*P left_top_grid_pin_42_[0] I *L 0.29796 *C 7.360 74.835 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 24.095 55.080 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.010 53.380 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 43.530 47.940 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 49.050 42.500 +*N left_top_grid_pin_42_[0]:5 *C 49.013 42.500 +*N left_top_grid_pin_42_[0]:6 *C 44.665 42.500 +*N left_top_grid_pin_42_[0]:7 *C 44.620 42.545 +*N left_top_grid_pin_42_[0]:8 *C 44.620 47.895 +*N left_top_grid_pin_42_[0]:9 *C 44.575 47.940 +*N left_top_grid_pin_42_[0]:10 *C 43.530 47.963 +*N left_top_grid_pin_42_[0]:11 *C 43.530 48.280 +*N left_top_grid_pin_42_[0]:12 *C 37.765 48.280 +*N left_top_grid_pin_42_[0]:13 *C 37.720 48.325 +*N left_top_grid_pin_42_[0]:14 *C 38.010 53.380 +*N left_top_grid_pin_42_[0]:15 *C 37.720 53.380 +*N left_top_grid_pin_42_[0]:16 *C 37.720 53.335 +*N left_top_grid_pin_42_[0]:17 *C 37.720 53.720 +*N left_top_grid_pin_42_[0]:18 *C 37.712 53.720 +*N left_top_grid_pin_42_[0]:19 *C 23.928 53.720 +*N left_top_grid_pin_42_[0]:20 *C 23.920 53.778 +*N left_top_grid_pin_42_[0]:21 *C 24.095 55.080 +*N left_top_grid_pin_42_[0]:22 *C 23.920 55.080 +*N left_top_grid_pin_42_[0]:23 *C 23.920 55.080 +*N left_top_grid_pin_42_[0]:24 *C 23.920 59.103 +*N left_top_grid_pin_42_[0]:25 *C 23.913 59.160 +*N left_top_grid_pin_42_[0]:26 *C 13.800 59.160 +*N left_top_grid_pin_42_[0]:27 *C 13.800 60.520 +*N left_top_grid_pin_42_[0]:28 *C 12.428 60.520 +*N left_top_grid_pin_42_[0]:29 *C 12.420 60.578 +*N left_top_grid_pin_42_[0]:30 *C 12.420 74.415 +*N left_top_grid_pin_42_[0]:31 *C 12.375 74.460 +*N left_top_grid_pin_42_[0]:32 *C 7.405 74.460 +*N left_top_grid_pin_42_[0]:33 *C 7.360 74.505 + +*CAP +0 left_top_grid_pin_42_[0] 3.470681e-05 +1 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +3 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +4 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +5 left_top_grid_pin_42_[0]:5 0.0002897686 +6 left_top_grid_pin_42_[0]:6 0.0002897686 +7 left_top_grid_pin_42_[0]:7 0.0003009381 +8 left_top_grid_pin_42_[0]:8 0.0003009381 +9 left_top_grid_pin_42_[0]:9 0.0001194486 +10 left_top_grid_pin_42_[0]:10 0.0001483402 +11 left_top_grid_pin_42_[0]:11 0.0004507647 +12 left_top_grid_pin_42_[0]:12 0.0004218731 +13 left_top_grid_pin_42_[0]:13 0.0002991466 +14 left_top_grid_pin_42_[0]:14 5.211397e-05 +15 left_top_grid_pin_42_[0]:15 5.642312e-05 +16 left_top_grid_pin_42_[0]:16 0.0003194118 +17 left_top_grid_pin_42_[0]:17 5.501112e-05 +18 left_top_grid_pin_42_[0]:18 0.0003731341 +19 left_top_grid_pin_42_[0]:19 0.0003731341 +20 left_top_grid_pin_42_[0]:20 8.552478e-05 +21 left_top_grid_pin_42_[0]:21 6.365402e-05 +22 left_top_grid_pin_42_[0]:22 5.992024e-05 +23 left_top_grid_pin_42_[0]:23 0.0003578401 +24 left_top_grid_pin_42_[0]:24 0.0002380086 +25 left_top_grid_pin_42_[0]:25 0.0004137155 +26 left_top_grid_pin_42_[0]:26 0.0005088717 +27 left_top_grid_pin_42_[0]:27 0.0002508137 +28 left_top_grid_pin_42_[0]:28 0.0001556575 +29 left_top_grid_pin_42_[0]:29 0.0008514068 +30 left_top_grid_pin_42_[0]:30 0.0008514068 +31 left_top_grid_pin_42_[0]:31 0.0003868324 +32 left_top_grid_pin_42_[0]:32 0.0003868324 +33 left_top_grid_pin_42_[0]:33 3.470681e-05 +34 left_top_grid_pin_42_[0]:18 chany_top_in[3]:10 0.0002724328 +35 left_top_grid_pin_42_[0]:20 chany_top_in[3]:7 5.214449e-07 +36 left_top_grid_pin_42_[0]:19 chany_top_in[3]:9 0.0002724328 +37 left_top_grid_pin_42_[0]:24 chany_top_in[3]:8 7.09035e-08 +38 left_top_grid_pin_42_[0]:23 chany_top_in[3]:7 7.09035e-08 +39 left_top_grid_pin_42_[0]:23 chany_top_in[3]:8 5.214449e-07 +40 left_top_grid_pin_42_[0]:18 chanx_left_in[3]:16 0.0005817451 +41 left_top_grid_pin_42_[0]:19 chanx_left_in[3] 0.0005817451 +42 left_top_grid_pin_42_[0]:25 chanx_left_in[6]:6 0.000577282 +43 left_top_grid_pin_42_[0]:28 chanx_left_in[6]:7 1.604747e-06 +44 left_top_grid_pin_42_[0]:27 chanx_left_in[6]:6 1.604747e-06 +45 left_top_grid_pin_42_[0]:26 chanx_left_in[6]:7 0.000577282 +46 left_top_grid_pin_42_[0]:17 mux_tree_tapbuf_size5_3_sram[2]:8 1.644134e-08 +47 left_top_grid_pin_42_[0]:18 mux_tree_tapbuf_size5_3_sram[2]:11 0.0001440872 +48 left_top_grid_pin_42_[0]:19 mux_tree_tapbuf_size5_3_sram[2]:10 0.0001440872 +49 left_top_grid_pin_42_[0]:13 mux_tree_tapbuf_size5_3_sram[2]:8 2.877235e-08 +50 left_top_grid_pin_42_[0]:16 mux_tree_tapbuf_size5_3_sram[2]:9 4.52137e-08 + +*RES +0 left_top_grid_pin_42_[0] left_top_grid_pin_42_[0]:33 0.0002946429 +1 left_top_grid_pin_42_[0]:17 left_top_grid_pin_42_[0]:16 0.0001850962 +2 left_top_grid_pin_42_[0]:18 left_top_grid_pin_42_[0]:17 0.00341 +3 left_top_grid_pin_42_[0]:20 left_top_grid_pin_42_[0]:19 0.00341 +4 left_top_grid_pin_42_[0]:19 left_top_grid_pin_42_[0]:18 0.00215965 +5 left_top_grid_pin_42_[0]:9 left_top_grid_pin_42_[0]:8 0.0045 +6 left_top_grid_pin_42_[0]:8 left_top_grid_pin_42_[0]:7 0.004776786 +7 left_top_grid_pin_42_[0]:6 left_top_grid_pin_42_[0]:5 0.003881697 +8 left_top_grid_pin_42_[0]:7 left_top_grid_pin_42_[0]:6 0.0045 +9 left_top_grid_pin_42_[0]:5 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +10 left_top_grid_pin_42_[0]:24 left_top_grid_pin_42_[0]:23 0.003591518 +11 left_top_grid_pin_42_[0]:25 left_top_grid_pin_42_[0]:24 0.00341 +12 left_top_grid_pin_42_[0]:29 left_top_grid_pin_42_[0]:28 0.00341 +13 left_top_grid_pin_42_[0]:28 left_top_grid_pin_42_[0]:27 0.000215025 +14 left_top_grid_pin_42_[0]:31 left_top_grid_pin_42_[0]:30 0.0045 +15 left_top_grid_pin_42_[0]:30 left_top_grid_pin_42_[0]:29 0.01235491 +16 left_top_grid_pin_42_[0]:32 left_top_grid_pin_42_[0]:31 0.0044375 +17 left_top_grid_pin_42_[0]:33 left_top_grid_pin_42_[0]:32 0.0045 +18 left_top_grid_pin_42_[0]:12 left_top_grid_pin_42_[0]:11 0.005147322 +19 left_top_grid_pin_42_[0]:13 left_top_grid_pin_42_[0]:12 0.0045 +20 left_top_grid_pin_42_[0]:22 left_top_grid_pin_42_[0]:21 9.51087e-05 +21 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:22 0.0045 +22 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:20 0.001162947 +23 left_top_grid_pin_42_[0]:21 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +24 left_top_grid_pin_42_[0]:10 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +25 left_top_grid_pin_42_[0]:10 left_top_grid_pin_42_[0]:9 0.0009330358 +26 left_top_grid_pin_42_[0]:15 left_top_grid_pin_42_[0]:14 0.0001576087 +27 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:15 0.0045 +28 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:13 0.004473215 +29 left_top_grid_pin_42_[0]:14 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +30 left_top_grid_pin_42_[0]:11 left_top_grid_pin_42_[0]:10 0.0002834821 +31 left_top_grid_pin_42_[0]:27 left_top_grid_pin_42_[0]:26 0.0002130667 +32 left_top_grid_pin_42_[0]:26 left_top_grid_pin_42_[0]:25 0.001584291 + +*END + +*D_NET ropt_net_121 0.0009387634 //LENGTH 9.670 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/BUFT_P_88:X O *L 0 *C 99.360 88.740 +*I ropt_mt_inst_728:A I *L 0.001766 *C 99.360 96.560 +*N ropt_net_121:2 *C 99.323 96.560 +*N ropt_net_121:3 *C 98.945 96.560 +*N ropt_net_121:4 *C 98.900 96.515 +*N ropt_net_121:5 *C 98.900 88.785 +*N ropt_net_121:6 *C 98.945 88.740 +*N ropt_net_121:7 *C 99.323 88.740 + +*CAP +0 mux_top_track_8\/BUFT_P_88:X 1e-06 +1 ropt_mt_inst_728:A 1e-06 +2 ropt_net_121:2 4.30801e-05 +3 ropt_net_121:3 4.30801e-05 +4 ropt_net_121:4 0.0003872723 +5 ropt_net_121:5 0.0003872723 +6 ropt_net_121:6 3.802929e-05 +7 ropt_net_121:7 3.802929e-05 + +*RES +0 mux_top_track_8\/BUFT_P_88:X ropt_net_121:7 0.152 +1 ropt_net_121:7 ropt_net_121:6 0.0003370536 +2 ropt_net_121:6 ropt_net_121:5 0.0045 +3 ropt_net_121:5 ropt_net_121:4 0.006901786 +4 ropt_net_121:3 ropt_net_121:2 0.0003370536 +5 ropt_net_121:4 ropt_net_121:3 0.0045 +6 ropt_net_121:2 ropt_mt_inst_728:A 0.152 + +*END + +*D_NET chany_top_out[10] 0.001577869 //LENGTH 15.455 LUMPCC 0 DR + +*CONN +*I mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 95.280 88.400 +*P chany_top_out[10] O *L 0.7423 *C 96.600 102.070 +*N chany_top_out[10]:2 *C 96.600 88.445 +*N chany_top_out[10]:3 *C 96.555 88.400 +*N chany_top_out[10]:4 *C 95.318 88.400 + +*CAP +0 mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[10] 0.000701804 +2 chany_top_out[10]:2 0.000701804 +3 chany_top_out[10]:3 8.663029e-05 +4 chany_top_out[10]:4 8.663029e-05 + +*RES +0 mux_top_track_20\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[10]:4 0.152 +1 chany_top_out[10]:4 chany_top_out[10]:3 0.001104911 +2 chany_top_out[10]:3 chany_top_out[10]:2 0.0045 +3 chany_top_out[10]:2 chany_top_out[10] 0.01216518 + +*END + +*D_NET chany_top_out[14] 0.0004745652 //LENGTH 4.575 LUMPCC 0 DR + +*CONN +*I mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 96.200 99.280 +*P chany_top_out[14] O *L 0.7423 *C 97.520 102.070 +*N chany_top_out[14]:2 *C 97.520 99.325 +*N chany_top_out[14]:3 *C 97.475 99.280 +*N chany_top_out[14]:4 *C 96.238 99.280 + +*CAP +0 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[14] 0.0001447337 +2 chany_top_out[14]:2 0.0001447337 +3 chany_top_out[14]:3 9.204887e-05 +4 chany_top_out[14]:4 9.204887e-05 + +*RES +0 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[14]:4 0.152 +1 chany_top_out[14]:4 chany_top_out[14]:3 0.001104911 +2 chany_top_out[14]:3 chany_top_out[14]:2 0.0045 +3 chany_top_out[14]:2 chany_top_out[14] 0.002450893 + +*END + +*D_NET chany_top_out[19] 0.002359709 //LENGTH 18.210 LUMPCC 0 DR + +*CONN +*I mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 64.345 99.280 +*P chany_top_out[19] O *L 0.7423 *C 78.660 102.070 +*N chany_top_out[19]:2 *C 78.660 101.365 +*N chany_top_out[19]:3 *C 78.615 101.320 +*N chany_top_out[19]:4 *C 64.905 101.320 +*N chany_top_out[19]:5 *C 64.860 101.275 +*N chany_top_out[19]:6 *C 64.860 99.325 +*N chany_top_out[19]:7 *C 64.815 99.280 +*N chany_top_out[19]:8 *C 64.383 99.280 + +*CAP +0 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[19] 6.28753e-05 +2 chany_top_out[19]:2 6.28753e-05 +3 chany_top_out[19]:3 0.0009254309 +4 chany_top_out[19]:4 0.0009254309 +5 chany_top_out[19]:5 0.0001401153 +6 chany_top_out[19]:6 0.0001401153 +7 chany_top_out[19]:7 5.093276e-05 +8 chany_top_out[19]:8 5.093276e-05 + +*RES +0 mux_top_track_38\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[19]:8 0.152 +1 chany_top_out[19]:8 chany_top_out[19]:7 0.0003861607 +2 chany_top_out[19]:7 chany_top_out[19]:6 0.0045 +3 chany_top_out[19]:6 chany_top_out[19]:5 0.001741072 +4 chany_top_out[19]:4 chany_top_out[19]:3 0.01224107 +5 chany_top_out[19]:5 chany_top_out[19]:4 0.0045 +6 chany_top_out[19]:3 chany_top_out[19]:2 0.0045 +7 chany_top_out[19]:2 chany_top_out[19] 0.0006294643 + +*END + +*D_NET chanx_left_out[7] 0.0009158693 //LENGTH 6.410 LUMPCC 0 DR + +*CONN +*I mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 5.465 50.320 +*P chanx_left_out[7] O *L 0.7423 *C 1.230 48.960 +*N chanx_left_out[7]:2 *C 3.673 48.960 +*N chanx_left_out[7]:3 *C 3.680 49.018 +*N chanx_left_out[7]:4 *C 3.680 50.275 +*N chanx_left_out[7]:5 *C 3.725 50.320 +*N chanx_left_out[7]:6 *C 5.428 50.320 + +*CAP +0 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[7] 0.0002364671 +2 chanx_left_out[7]:2 0.0002364671 +3 chanx_left_out[7]:3 0.0001012538 +4 chanx_left_out[7]:4 0.0001012538 +5 chanx_left_out[7]:5 0.0001197137 +6 chanx_left_out[7]:6 0.0001197137 + +*RES +0 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[7]:6 0.152 +1 chanx_left_out[7]:6 chanx_left_out[7]:5 0.001520089 +2 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +3 chanx_left_out[7]:4 chanx_left_out[7]:3 0.001122768 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 0.0003826583 + +*END + +*D_NET ropt_net_117 0.002630387 //LENGTH 25.660 LUMPCC 9.797898e-05 DR + +*CONN +*I mux_left_track_25\/BUFT_RR_45:X O *L 0 *C 23.225 20.740 +*I ropt_mt_inst_724:A I *L 0.001766 *C 5.980 25.840 +*N ropt_net_117:2 *C 6.018 25.840 +*N ropt_net_117:3 *C 9.155 25.840 +*N ropt_net_117:4 *C 9.200 25.795 +*N ropt_net_117:5 *C 9.200 23.178 +*N ropt_net_117:6 *C 9.207 23.120 +*N ropt_net_117:7 *C 16.093 23.120 +*N ropt_net_117:8 *C 16.100 23.120 +*N ropt_net_117:9 *C 16.145 23.120 +*N ropt_net_117:10 *C 23.875 23.120 +*N ropt_net_117:11 *C 23.920 23.075 +*N ropt_net_117:12 *C 23.920 20.785 +*N ropt_net_117:13 *C 23.875 20.740 +*N ropt_net_117:14 *C 23.263 20.740 + +*CAP +0 mux_left_track_25\/BUFT_RR_45:X 1e-06 +1 ropt_mt_inst_724:A 1e-06 +2 ropt_net_117:2 0.0001620671 +3 ropt_net_117:3 0.0001620671 +4 ropt_net_117:4 0.000137452 +5 ropt_net_117:5 0.000137452 +6 ropt_net_117:6 0.0003443735 +7 ropt_net_117:7 0.0003443735 +8 ropt_net_117:8 3.018369e-05 +9 ropt_net_117:9 0.0004137432 +10 ropt_net_117:10 0.0004137432 +11 ropt_net_117:11 0.000130616 +12 ropt_net_117:12 0.000130616 +13 ropt_net_117:13 6.186045e-05 +14 ropt_net_117:14 6.186045e-05 +15 ropt_net_117:2 ropt_net_128:10 4.161694e-05 +16 ropt_net_117:3 ropt_net_128:11 4.161694e-05 +17 ropt_net_117:4 ropt_net_128:9 7.372549e-06 +18 ropt_net_117:5 ropt_net_128:8 7.372549e-06 + +*RES +0 mux_left_track_25\/BUFT_RR_45:X ropt_net_117:14 0.152 +1 ropt_net_117:2 ropt_mt_inst_724:A 0.152 +2 ropt_net_117:3 ropt_net_117:2 0.00280134 +3 ropt_net_117:4 ropt_net_117:3 0.0045 +4 ropt_net_117:5 ropt_net_117:4 0.002337053 +5 ropt_net_117:6 ropt_net_117:5 0.00341 +6 ropt_net_117:8 ropt_net_117:7 0.00341 +7 ropt_net_117:7 ropt_net_117:6 0.00107865 +8 ropt_net_117:9 ropt_net_117:8 0.0045 +9 ropt_net_117:10 ropt_net_117:9 0.006901786 +10 ropt_net_117:11 ropt_net_117:10 0.0045 +11 ropt_net_117:13 ropt_net_117:12 0.0045 +12 ropt_net_117:12 ropt_net_117:11 0.002044643 +13 ropt_net_117:14 ropt_net_117:13 0.000546875 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[1] 0.001971966 //LENGTH 15.865 LUMPCC 0.0001740038 DR + +*CONN +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.485 75.140 +*I mem_top_track_34\/FTB_24__29:A I *L 0.001746 *C 58.420 72.080 +*I mux_top_track_34\/mux_l2_in_0_:S I *L 0.00357 *C 58.320 82.960 +*N mux_tree_tapbuf_size2_11_sram[1]:3 *C 58.358 82.960 +*N mux_tree_tapbuf_size2_11_sram[1]:4 *C 58.835 82.960 +*N mux_tree_tapbuf_size2_11_sram[1]:5 *C 58.880 82.915 +*N mux_tree_tapbuf_size2_11_sram[1]:6 *C 58.420 72.080 +*N mux_tree_tapbuf_size2_11_sram[1]:7 *C 58.420 72.125 +*N mux_tree_tapbuf_size2_11_sram[1]:8 *C 58.420 75.140 +*N mux_tree_tapbuf_size2_11_sram[1]:9 *C 58.880 75.185 +*N mux_tree_tapbuf_size2_11_sram[1]:10 *C 58.925 75.140 +*N mux_tree_tapbuf_size2_11_sram[1]:11 *C 61.448 75.140 + +*CAP +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_34\/FTB_24__29:A 1e-06 +2 mux_top_track_34\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_11_sram[1]:3 5.450284e-05 +4 mux_tree_tapbuf_size2_11_sram[1]:4 5.450284e-05 +5 mux_tree_tapbuf_size2_11_sram[1]:5 0.0004470596 +6 mux_tree_tapbuf_size2_11_sram[1]:6 3.574315e-05 +7 mux_tree_tapbuf_size2_11_sram[1]:7 0.0001691921 +8 mux_tree_tapbuf_size2_11_sram[1]:8 0.0002031065 +9 mux_tree_tapbuf_size2_11_sram[1]:9 0.000480974 +10 mux_tree_tapbuf_size2_11_sram[1]:10 0.0001749405 +11 mux_tree_tapbuf_size2_11_sram[1]:11 0.0001749405 +12 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 2.595917e-05 +13 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 6.104274e-05 +14 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 6.104274e-05 +15 mux_tree_tapbuf_size2_11_sram[1]:8 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 2.595917e-05 + +*RES +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_11_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_11_sram[1]:6 mem_top_track_34\/FTB_24__29:A 0.152 +2 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_11_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size2_11_sram[1]:4 mux_tree_tapbuf_size2_11_sram[1]:3 0.0004263393 +4 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_11_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size2_11_sram[1]:3 mux_top_track_34\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_11_sram[1]:10 mux_tree_tapbuf_size2_11_sram[1]:9 0.0045 +7 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_11_sram[1]:8 0.0004107143 +8 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_11_sram[1]:5 0.006901786 +9 mux_tree_tapbuf_size2_11_sram[1]:11 mux_tree_tapbuf_size2_11_sram[1]:10 0.002252232 +10 mux_tree_tapbuf_size2_11_sram[1]:8 mux_tree_tapbuf_size2_11_sram[1]:7 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size2_14_sram[0] 0.003686722 //LENGTH 28.885 LUMPCC 0.0004472204 DR + +*CONN +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.465 49.980 +*I mux_left_track_11\/mux_l1_in_0_:S I *L 0.00357 *C 36.900 67.320 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.720 69.700 +*N mux_tree_tapbuf_size2_14_sram[0]:3 *C 39.720 69.700 +*N mux_tree_tapbuf_size2_14_sram[0]:4 *C 39.560 69.700 +*N mux_tree_tapbuf_size2_14_sram[0]:5 *C 39.560 69.655 +*N mux_tree_tapbuf_size2_14_sram[0]:6 *C 36.938 67.320 +*N mux_tree_tapbuf_size2_14_sram[0]:7 *C 39.515 67.320 +*N mux_tree_tapbuf_size2_14_sram[0]:8 *C 39.560 67.320 +*N mux_tree_tapbuf_size2_14_sram[0]:9 *C 39.560 59.218 +*N mux_tree_tapbuf_size2_14_sram[0]:10 *C 39.568 59.160 +*N mux_tree_tapbuf_size2_14_sram[0]:11 *C 44.153 59.160 +*N mux_tree_tapbuf_size2_14_sram[0]:12 *C 44.160 59.103 +*N mux_tree_tapbuf_size2_14_sram[0]:13 *C 44.160 50.025 +*N mux_tree_tapbuf_size2_14_sram[0]:14 *C 44.160 49.980 +*N mux_tree_tapbuf_size2_14_sram[0]:15 *C 44.465 49.980 + +*CAP +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_11\/mux_l1_in_0_:S 1e-06 +2 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_14_sram[0]:3 5.866777e-05 +4 mux_tree_tapbuf_size2_14_sram[0]:4 5.546253e-05 +5 mux_tree_tapbuf_size2_14_sram[0]:5 0.0001495844 +6 mux_tree_tapbuf_size2_14_sram[0]:6 0.000204581 +7 mux_tree_tapbuf_size2_14_sram[0]:7 0.000204581 +8 mux_tree_tapbuf_size2_14_sram[0]:8 0.000552439 +9 mux_tree_tapbuf_size2_14_sram[0]:9 0.0003707952 +10 mux_tree_tapbuf_size2_14_sram[0]:10 0.0002982097 +11 mux_tree_tapbuf_size2_14_sram[0]:11 0.0002982097 +12 mux_tree_tapbuf_size2_14_sram[0]:12 0.0004699701 +13 mux_tree_tapbuf_size2_14_sram[0]:13 0.0004699701 +14 mux_tree_tapbuf_size2_14_sram[0]:14 5.319378e-05 +15 mux_tree_tapbuf_size2_14_sram[0]:15 5.083688e-05 +16 mux_tree_tapbuf_size2_14_sram[0]:5 top_left_grid_pin_37_[0]:20 2.196589e-05 +17 mux_tree_tapbuf_size2_14_sram[0]:9 top_left_grid_pin_37_[0]:19 8.620691e-05 +18 mux_tree_tapbuf_size2_14_sram[0]:10 top_left_grid_pin_37_[0]:17 3.750863e-05 +19 mux_tree_tapbuf_size2_14_sram[0]:10 top_left_grid_pin_37_[0]:18 5.456847e-05 +20 mux_tree_tapbuf_size2_14_sram[0]:12 top_left_grid_pin_37_[0]:15 4.487721e-06 +21 mux_tree_tapbuf_size2_14_sram[0]:12 top_left_grid_pin_37_[0]:16 1.88726e-05 +22 mux_tree_tapbuf_size2_14_sram[0]:11 top_left_grid_pin_37_[0]:8 3.750863e-05 +23 mux_tree_tapbuf_size2_14_sram[0]:11 top_left_grid_pin_37_[0]:17 5.456847e-05 +24 mux_tree_tapbuf_size2_14_sram[0]:13 top_left_grid_pin_37_[0]:14 4.487721e-06 +25 mux_tree_tapbuf_size2_14_sram[0]:13 top_left_grid_pin_37_[0]:15 1.88726e-05 +26 mux_tree_tapbuf_size2_14_sram[0]:8 top_left_grid_pin_37_[0]:19 2.196589e-05 +27 mux_tree_tapbuf_size2_14_sram[0]:8 top_left_grid_pin_37_[0]:20 8.620691e-05 + +*RES +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_14_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_14_sram[0]:3 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_14_sram[0]:4 mux_tree_tapbuf_size2_14_sram[0]:3 1e-05 +3 mux_tree_tapbuf_size2_14_sram[0]:5 mux_tree_tapbuf_size2_14_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_14_sram[0]:9 mux_tree_tapbuf_size2_14_sram[0]:8 0.007234375 +5 mux_tree_tapbuf_size2_14_sram[0]:10 mux_tree_tapbuf_size2_14_sram[0]:9 0.00341 +6 mux_tree_tapbuf_size2_14_sram[0]:12 mux_tree_tapbuf_size2_14_sram[0]:11 0.00341 +7 mux_tree_tapbuf_size2_14_sram[0]:11 mux_tree_tapbuf_size2_14_sram[0]:10 0.0007183166 +8 mux_tree_tapbuf_size2_14_sram[0]:14 mux_tree_tapbuf_size2_14_sram[0]:13 0.0045 +9 mux_tree_tapbuf_size2_14_sram[0]:13 mux_tree_tapbuf_size2_14_sram[0]:12 0.008104911 +10 mux_tree_tapbuf_size2_14_sram[0]:15 mux_tree_tapbuf_size2_14_sram[0]:14 0.0001657609 +11 mux_tree_tapbuf_size2_14_sram[0]:7 mux_tree_tapbuf_size2_14_sram[0]:6 0.002301339 +12 mux_tree_tapbuf_size2_14_sram[0]:8 mux_tree_tapbuf_size2_14_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size2_14_sram[0]:8 mux_tree_tapbuf_size2_14_sram[0]:5 0.002084822 +14 mux_tree_tapbuf_size2_14_sram[0]:6 mux_left_track_11\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_19_sram[1] 0.0005874719 //LENGTH 5.180 LUMPCC 0 DR + +*CONN +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 34.655 25.160 +*I mem_left_track_21\/FTB_32__37:A I *L 0.001746 *C 34.500 23.120 +*I mux_left_track_21\/mux_l2_in_0_:S I *L 0.00357 *C 32.200 23.295 +*N mux_tree_tapbuf_size2_19_sram[1]:3 *C 32.238 23.185 +*N mux_tree_tapbuf_size2_19_sram[1]:4 *C 34.462 23.120 +*N mux_tree_tapbuf_size2_19_sram[1]:5 *C 34.500 23.165 +*N mux_tree_tapbuf_size2_19_sram[1]:6 *C 34.500 25.115 +*N mux_tree_tapbuf_size2_19_sram[1]:7 *C 34.500 25.160 +*N mux_tree_tapbuf_size2_19_sram[1]:8 *C 34.655 25.160 + +*CAP +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_21\/FTB_32__37:A 1e-06 +2 mux_left_track_21\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_19_sram[1]:3 0.0001354295 +4 mux_tree_tapbuf_size2_19_sram[1]:4 0.0001354295 +5 mux_tree_tapbuf_size2_19_sram[1]:5 0.0001060213 +6 mux_tree_tapbuf_size2_19_sram[1]:6 0.0001060213 +7 mux_tree_tapbuf_size2_19_sram[1]:7 5.336649e-05 +8 mux_tree_tapbuf_size2_19_sram[1]:8 4.820393e-05 + +*RES +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_19_sram[1]:8 0.152 +1 mux_tree_tapbuf_size2_19_sram[1]:8 mux_tree_tapbuf_size2_19_sram[1]:7 8.423914e-05 +2 mux_tree_tapbuf_size2_19_sram[1]:7 mux_tree_tapbuf_size2_19_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size2_19_sram[1]:6 mux_tree_tapbuf_size2_19_sram[1]:5 0.001741072 +4 mux_tree_tapbuf_size2_19_sram[1]:4 mem_left_track_21\/FTB_32__37:A 0.152 +5 mux_tree_tapbuf_size2_19_sram[1]:4 mux_tree_tapbuf_size2_19_sram[1]:3 0.001986607 +6 mux_tree_tapbuf_size2_19_sram[1]:5 mux_tree_tapbuf_size2_19_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size2_19_sram[1]:3 mux_left_track_21\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_21_sram[0] 0.005379491 //LENGTH 42.400 LUMPCC 0.0005047099 DR + +*CONN +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 54.125 44.540 +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.275 60.860 +*I mux_left_track_27\/mux_l1_in_0_:S I *L 0.00357 *C 41.040 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:3 *C 40.940 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:4 *C 40.940 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:5 *C 39.312 60.860 +*N mux_tree_tapbuf_size2_21_sram[0]:6 *C 40.435 60.860 +*N mux_tree_tapbuf_size2_21_sram[0]:7 *C 40.480 60.905 +*N mux_tree_tapbuf_size2_21_sram[0]:8 *C 40.480 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:9 *C 40.488 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:10 *C 52.420 63.240 +*N mux_tree_tapbuf_size2_21_sram[0]:11 *C 52.440 63.233 +*N mux_tree_tapbuf_size2_21_sram[0]:12 *C 52.440 42.848 +*N mux_tree_tapbuf_size2_21_sram[0]:13 *C 52.460 42.840 +*N mux_tree_tapbuf_size2_21_sram[0]:14 *C 53.352 42.840 +*N mux_tree_tapbuf_size2_21_sram[0]:15 *C 53.360 42.898 +*N mux_tree_tapbuf_size2_21_sram[0]:16 *C 53.360 44.495 +*N mux_tree_tapbuf_size2_21_sram[0]:17 *C 53.405 44.540 +*N mux_tree_tapbuf_size2_21_sram[0]:18 *C 54.088 44.540 + +*CAP +0 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_27\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_21_sram[0]:3 3.089455e-05 +4 mux_tree_tapbuf_size2_21_sram[0]:4 6.999834e-05 +5 mux_tree_tapbuf_size2_21_sram[0]:5 9.979564e-05 +6 mux_tree_tapbuf_size2_21_sram[0]:6 9.979564e-05 +7 mux_tree_tapbuf_size2_21_sram[0]:7 0.0001576718 +8 mux_tree_tapbuf_size2_21_sram[0]:8 0.0001953755 +9 mux_tree_tapbuf_size2_21_sram[0]:9 0.0006717162 +10 mux_tree_tapbuf_size2_21_sram[0]:10 0.0006717162 +11 mux_tree_tapbuf_size2_21_sram[0]:11 0.001186668 +12 mux_tree_tapbuf_size2_21_sram[0]:12 0.001186668 +13 mux_tree_tapbuf_size2_21_sram[0]:13 7.759335e-05 +14 mux_tree_tapbuf_size2_21_sram[0]:14 7.759335e-05 +15 mux_tree_tapbuf_size2_21_sram[0]:15 0.0001109089 +16 mux_tree_tapbuf_size2_21_sram[0]:16 0.0001109089 +17 mux_tree_tapbuf_size2_21_sram[0]:17 6.223882e-05 +18 mux_tree_tapbuf_size2_21_sram[0]:18 6.223882e-05 +19 mux_tree_tapbuf_size2_21_sram[0]:9 chany_top_in[13]:5 0.0002523549 +20 mux_tree_tapbuf_size2_21_sram[0]:10 chany_top_in[13]:6 0.0002523549 + +*RES +0 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_21_sram[0]:18 0.152 +1 mux_tree_tapbuf_size2_21_sram[0]:3 mux_left_track_27\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_21_sram[0]:4 mux_tree_tapbuf_size2_21_sram[0]:3 0.0045 +3 mux_tree_tapbuf_size2_21_sram[0]:6 mux_tree_tapbuf_size2_21_sram[0]:5 0.001002232 +4 mux_tree_tapbuf_size2_21_sram[0]:7 mux_tree_tapbuf_size2_21_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size2_21_sram[0]:5 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_21_sram[0]:8 mux_tree_tapbuf_size2_21_sram[0]:7 0.002084821 +7 mux_tree_tapbuf_size2_21_sram[0]:8 mux_tree_tapbuf_size2_21_sram[0]:4 0.0004107143 +8 mux_tree_tapbuf_size2_21_sram[0]:9 mux_tree_tapbuf_size2_21_sram[0]:8 0.00341 +9 mux_tree_tapbuf_size2_21_sram[0]:10 mux_tree_tapbuf_size2_21_sram[0]:9 0.001869425 +10 mux_tree_tapbuf_size2_21_sram[0]:11 mux_tree_tapbuf_size2_21_sram[0]:10 0.00341 +11 mux_tree_tapbuf_size2_21_sram[0]:13 mux_tree_tapbuf_size2_21_sram[0]:12 0.00341 +12 mux_tree_tapbuf_size2_21_sram[0]:12 mux_tree_tapbuf_size2_21_sram[0]:11 0.00319365 +13 mux_tree_tapbuf_size2_21_sram[0]:15 mux_tree_tapbuf_size2_21_sram[0]:14 0.00341 +14 mux_tree_tapbuf_size2_21_sram[0]:14 mux_tree_tapbuf_size2_21_sram[0]:13 0.000139825 +15 mux_tree_tapbuf_size2_21_sram[0]:17 mux_tree_tapbuf_size2_21_sram[0]:16 0.0045 +16 mux_tree_tapbuf_size2_21_sram[0]:16 mux_tree_tapbuf_size2_21_sram[0]:15 0.001426339 +17 mux_tree_tapbuf_size2_21_sram[0]:18 mux_tree_tapbuf_size2_21_sram[0]:17 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[1] 0.001164343 //LENGTH 9.935 LUMPCC 0 DR + +*CONN +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 91.385 86.020 +*I mux_top_track_22\/mux_l2_in_0_:S I *L 0.00357 *C 90.980 90.830 +*I mem_top_track_22\/FTB_19__24:A I *L 0.001746 *C 87.400 91.120 +*N mux_tree_tapbuf_size2_6_sram[1]:3 *C 87.438 91.120 +*N mux_tree_tapbuf_size2_6_sram[1]:4 *C 90.922 91.120 +*N mux_tree_tapbuf_size2_6_sram[1]:5 *C 90.980 90.830 +*N mux_tree_tapbuf_size2_6_sram[1]:6 *C 91.080 90.440 +*N mux_tree_tapbuf_size2_6_sram[1]:7 *C 91.080 90.395 +*N mux_tree_tapbuf_size2_6_sram[1]:8 *C 91.080 86.065 +*N mux_tree_tapbuf_size2_6_sram[1]:9 *C 91.080 86.020 +*N mux_tree_tapbuf_size2_6_sram[1]:10 *C 91.385 86.020 + +*CAP +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_22\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_22\/FTB_19__24:A 1e-06 +3 mux_tree_tapbuf_size2_6_sram[1]:3 0.0002297218 +4 mux_tree_tapbuf_size2_6_sram[1]:4 0.00025837 +5 mux_tree_tapbuf_size2_6_sram[1]:5 8.967004e-05 +6 mux_tree_tapbuf_size2_6_sram[1]:6 6.52282e-05 +7 mux_tree_tapbuf_size2_6_sram[1]:7 0.0002136429 +8 mux_tree_tapbuf_size2_6_sram[1]:8 0.0002136429 +9 mux_tree_tapbuf_size2_6_sram[1]:9 4.691635e-05 +10 mux_tree_tapbuf_size2_6_sram[1]:10 4.415114e-05 + +*RES +0 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_6_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_6_sram[1]:3 mem_top_track_22\/FTB_19__24:A 0.152 +2 mux_tree_tapbuf_size2_6_sram[1]:5 mux_top_track_22\/mux_l2_in_0_:S 0.152 +3 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_6_sram[1]:4 0.0001686047 +4 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[1]:5 0.0003482143 +5 mux_tree_tapbuf_size2_6_sram[1]:7 mux_tree_tapbuf_size2_6_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_6_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size2_6_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:7 0.003866072 +8 mux_tree_tapbuf_size2_6_sram[1]:10 mux_tree_tapbuf_size2_6_sram[1]:9 0.0001657609 +9 mux_tree_tapbuf_size2_6_sram[1]:4 mux_tree_tapbuf_size2_6_sram[1]:3 0.003111607 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_11_ccff_tail[0] 0.001207355 //LENGTH 8.090 LUMPCC 0.00059026 DR + +*CONN +*I mem_top_track_34\/FTB_24__29:X O *L 0 *C 61.415 72.080 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 59.515 77.180 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 *C 59.515 77.180 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 *C 59.340 77.180 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 *C 59.340 77.135 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 *C 59.340 72.125 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 *C 59.385 72.080 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 *C 61.378 72.080 + +*CAP +0 mem_top_track_34\/FTB_24__29:X 1e-06 +1 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 5.576653e-05 +3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 5.867379e-05 +4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.000148106 +5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.000148106 +6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 0.0001022213 +7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 0.0001022213 +8 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 top_left_grid_pin_41_[0]:14 1.586754e-05 +9 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 top_left_grid_pin_41_[0]:13 1.586754e-05 +10 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 top_left_grid_pin_41_[0]:14 0.0001405298 +11 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 top_left_grid_pin_41_[0]:17 0.0001405298 +12 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size2_11_sram[1]:7 2.595917e-05 +13 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size2_11_sram[1]:9 6.104274e-05 +14 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size2_11_sram[1]:5 6.104274e-05 +15 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size2_11_sram[1]:8 2.595917e-05 +16 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.173077e-05 +17 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.173077e-05 + +*RES +0 mem_top_track_34\/FTB_24__29:X mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 0.001779018 +2 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.004473215 +4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.001094189 //LENGTH 8.720 LUMPCC 0.000103201 DR + +*CONN +*I mem_top_track_14\/FTB_15__20:X O *L 0 *C 48.985 53.380 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 46.635 58.820 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 46.672 58.820 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 48.255 58.820 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 48.300 58.775 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 48.300 53.425 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 48.345 53.380 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 48.948 53.380 + +*CAP +0 mem_top_track_14\/FTB_15__20:X 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.0001302492 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0001302492 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.000310013 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.000310013 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 5.423194e-05 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 5.423194e-05 +8 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size6_2_sram[0]:29 3.707659e-05 +9 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size6_2_sram[0]:28 3.707659e-05 +10 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size6_2_sram[0]:30 1.452389e-05 +11 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size6_2_sram[0]:31 1.452389e-05 + +*RES +0 mem_top_track_14\/FTB_15__20:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.001412947 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[1] 0.001152687 //LENGTH 9.205 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 40.785 42.160 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.008363 *C 41.525 39.703 +*I mem_left_track_9\/FTB_11__16:A I *L 0.001746 *C 38.640 44.880 +*N mux_tree_tapbuf_size3_2_sram[1]:3 *C 38.678 44.880 +*N mux_tree_tapbuf_size3_2_sram[1]:4 *C 40.435 44.880 +*N mux_tree_tapbuf_size3_2_sram[1]:5 *C 40.480 44.835 +*N mux_tree_tapbuf_size3_2_sram[1]:6 *C 41.490 39.750 +*N mux_tree_tapbuf_size3_2_sram[1]:7 *C 41.400 39.780 +*N mux_tree_tapbuf_size3_2_sram[1]:8 *C 40.480 39.780 +*N mux_tree_tapbuf_size3_2_sram[1]:9 *C 40.480 42.160 +*N mux_tree_tapbuf_size3_2_sram[1]:10 *C 40.480 42.160 +*N mux_tree_tapbuf_size3_2_sram[1]:11 *C 40.785 42.160 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:S 3.365176e-05 +2 mem_left_track_9\/FTB_11__16:A 1e-06 +3 mux_tree_tapbuf_size3_2_sram[1]:3 0.0001199378 +4 mux_tree_tapbuf_size3_2_sram[1]:4 0.0001199378 +5 mux_tree_tapbuf_size3_2_sram[1]:5 0.0001501984 +6 mux_tree_tapbuf_size3_2_sram[1]:6 3.365176e-05 +7 mux_tree_tapbuf_size3_2_sram[1]:7 9.441487e-05 +8 mux_tree_tapbuf_size3_2_sram[1]:8 0.0001918447 +9 mux_tree_tapbuf_size3_2_sram[1]:9 0.0003119306 +10 mux_tree_tapbuf_size3_2_sram[1]:10 4.972045e-05 +11 mux_tree_tapbuf_size3_2_sram[1]:11 4.539894e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_2_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_2_sram[1]:10 mux_tree_tapbuf_size3_2_sram[1]:9 0.0045 +2 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:8 0.002125 +3 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:5 0.002388393 +4 mux_tree_tapbuf_size3_2_sram[1]:11 mux_tree_tapbuf_size3_2_sram[1]:10 0.0001657609 +5 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size3_2_sram[1]:3 0.001569196 +6 mux_tree_tapbuf_size3_2_sram[1]:5 mux_tree_tapbuf_size3_2_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size3_2_sram[1]:3 mem_left_track_9\/FTB_11__16:A 0.152 +8 mux_tree_tapbuf_size3_2_sram[1]:6 mux_left_track_9\/mux_l2_in_0_:S 3.365385e-05 +9 mux_tree_tapbuf_size3_2_sram[1]:7 mux_tree_tapbuf_size3_2_sram[1]:6 0.0045 +10 mux_tree_tapbuf_size3_2_sram[1]:8 mux_tree_tapbuf_size3_2_sram[1]:7 0.0008214285 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[0] 0.008506458 //LENGTH 62.780 LUMPCC 0.001328523 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 95.065 60.860 +*I mux_top_track_6\/mux_l1_in_1_:S I *L 0.00357 *C 58.320 63.920 +*I mux_top_track_6\/mux_l1_in_0_:S I *L 0.00357 *C 56.480 52.360 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 56.295 49.980 +*N mux_tree_tapbuf_size5_1_sram[0]:4 *C 56.258 49.980 +*N mux_tree_tapbuf_size5_1_sram[0]:5 *C 54.325 49.980 +*N mux_tree_tapbuf_size5_1_sram[0]:6 *C 54.280 50.025 +*N mux_tree_tapbuf_size5_1_sram[0]:7 *C 56.443 52.360 +*N mux_tree_tapbuf_size5_1_sram[0]:8 *C 54.325 52.360 +*N mux_tree_tapbuf_size5_1_sram[0]:9 *C 54.280 52.360 +*N mux_tree_tapbuf_size5_1_sram[0]:10 *C 54.280 60.463 +*N mux_tree_tapbuf_size5_1_sram[0]:11 *C 54.288 60.520 +*N mux_tree_tapbuf_size5_1_sram[0]:12 *C 58.283 63.920 +*N mux_tree_tapbuf_size5_1_sram[0]:13 *C 57.085 63.920 +*N mux_tree_tapbuf_size5_1_sram[0]:14 *C 57.040 63.875 +*N mux_tree_tapbuf_size5_1_sram[0]:15 *C 57.040 60.578 +*N mux_tree_tapbuf_size5_1_sram[0]:16 *C 57.040 60.520 +*N mux_tree_tapbuf_size5_1_sram[0]:17 *C 93.833 60.520 +*N mux_tree_tapbuf_size5_1_sram[0]:18 *C 93.840 60.520 +*N mux_tree_tapbuf_size5_1_sram[0]:19 *C 93.840 60.860 +*N mux_tree_tapbuf_size5_1_sram[0]:20 *C 93.885 60.860 +*N mux_tree_tapbuf_size5_1_sram[0]:21 *C 95.028 60.860 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_6\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_6\/mux_l1_in_0_:S 1e-06 +3 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_1_sram[0]:4 0.0001382127 +5 mux_tree_tapbuf_size5_1_sram[0]:5 0.0001382127 +6 mux_tree_tapbuf_size5_1_sram[0]:6 9.712199e-05 +7 mux_tree_tapbuf_size5_1_sram[0]:7 0.0001800933 +8 mux_tree_tapbuf_size5_1_sram[0]:8 0.0001800933 +9 mux_tree_tapbuf_size5_1_sram[0]:9 0.0004462131 +10 mux_tree_tapbuf_size5_1_sram[0]:10 0.0003178823 +11 mux_tree_tapbuf_size5_1_sram[0]:11 0.0002198586 +12 mux_tree_tapbuf_size5_1_sram[0]:12 0.0001212062 +13 mux_tree_tapbuf_size5_1_sram[0]:13 0.0001212062 +14 mux_tree_tapbuf_size5_1_sram[0]:14 0.0002060092 +15 mux_tree_tapbuf_size5_1_sram[0]:15 0.0002060092 +16 mux_tree_tapbuf_size5_1_sram[0]:16 0.002375676 +17 mux_tree_tapbuf_size5_1_sram[0]:17 0.002155817 +18 mux_tree_tapbuf_size5_1_sram[0]:18 5.441986e-05 +19 mux_tree_tapbuf_size5_1_sram[0]:19 5.060388e-05 +20 mux_tree_tapbuf_size5_1_sram[0]:20 8.265056e-05 +21 mux_tree_tapbuf_size5_1_sram[0]:21 8.265056e-05 +22 mux_tree_tapbuf_size5_1_sram[0]:5 prog_clk[0]:360 1.254567e-05 +23 mux_tree_tapbuf_size5_1_sram[0]:4 prog_clk[0]:359 1.254567e-05 +24 mux_tree_tapbuf_size5_1_sram[0]:16 prog_clk[0]:103 0.0001426411 +25 mux_tree_tapbuf_size5_1_sram[0]:16 prog_clk[0]:191 0.0001139081 +26 mux_tree_tapbuf_size5_1_sram[0]:17 prog_clk[0]:102 0.0001426411 +27 mux_tree_tapbuf_size5_1_sram[0]:17 prog_clk[0]:190 0.0001139081 +28 mux_tree_tapbuf_size5_1_sram[0]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001104311 +29 mux_tree_tapbuf_size5_1_sram[0]:17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001104311 +30 mux_tree_tapbuf_size5_1_sram[0]:10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000215367 +31 mux_tree_tapbuf_size5_1_sram[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000215367 +32 mux_tree_tapbuf_size5_1_sram[0]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.710534e-05 +33 mux_tree_tapbuf_size5_1_sram[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.710534e-05 +34 mux_tree_tapbuf_size5_1_sram[0]:15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.526683e-07 +35 mux_tree_tapbuf_size5_1_sram[0]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.010601e-06 +36 mux_tree_tapbuf_size5_1_sram[0]:14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.526683e-07 +37 mux_tree_tapbuf_size5_1_sram[0]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.010601e-06 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_1_sram[0]:21 0.152 +1 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size5_1_sram[0]:9 0.007234375 +2 mux_tree_tapbuf_size5_1_sram[0]:11 mux_tree_tapbuf_size5_1_sram[0]:10 0.00341 +3 mux_tree_tapbuf_size5_1_sram[0]:8 mux_tree_tapbuf_size5_1_sram[0]:7 0.001890625 +4 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:6 0.002084821 +6 mux_tree_tapbuf_size5_1_sram[0]:7 mux_top_track_6\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size5_1_sram[0]:5 mux_tree_tapbuf_size5_1_sram[0]:4 0.001725447 +8 mux_tree_tapbuf_size5_1_sram[0]:6 mux_tree_tapbuf_size5_1_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size5_1_sram[0]:4 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:14 0.002944197 +11 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:15 0.00341 +12 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:11 0.000431225 +13 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:12 0.001069196 +14 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size5_1_sram[0]:13 0.0045 +15 mux_tree_tapbuf_size5_1_sram[0]:12 mux_top_track_6\/mux_l1_in_1_:S 0.152 +16 mux_tree_tapbuf_size5_1_sram[0]:18 mux_tree_tapbuf_size5_1_sram[0]:17 0.00341 +17 mux_tree_tapbuf_size5_1_sram[0]:17 mux_tree_tapbuf_size5_1_sram[0]:16 0.005764158 +18 mux_tree_tapbuf_size5_1_sram[0]:20 mux_tree_tapbuf_size5_1_sram[0]:19 0.0045 +19 mux_tree_tapbuf_size5_1_sram[0]:19 mux_tree_tapbuf_size5_1_sram[0]:18 0.0001634615 +20 mux_tree_tapbuf_size5_1_sram[0]:21 mux_tree_tapbuf_size5_1_sram[0]:20 0.001020089 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[1] 0.0031725 //LENGTH 23.750 LUMPCC 0.0001372749 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 31.125 39.440 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 24.480 46.920 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 24.555 42.500 +*I mux_left_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 19.220 42.160 +*N mux_tree_tapbuf_size6_3_sram[1]:4 *C 19.258 42.160 +*N mux_tree_tapbuf_size6_3_sram[1]:5 *C 22.540 42.160 +*N mux_tree_tapbuf_size6_3_sram[1]:6 *C 22.540 42.500 +*N mux_tree_tapbuf_size6_3_sram[1]:7 *C 24.555 42.500 +*N mux_tree_tapbuf_size6_3_sram[1]:8 *C 26.220 42.500 +*N mux_tree_tapbuf_size6_3_sram[1]:9 *C 24.518 46.920 +*N mux_tree_tapbuf_size6_3_sram[1]:10 *C 26.175 46.920 +*N mux_tree_tapbuf_size6_3_sram[1]:11 *C 26.220 46.875 +*N mux_tree_tapbuf_size6_3_sram[1]:12 *C 26.220 42.885 +*N mux_tree_tapbuf_size6_3_sram[1]:13 *C 26.220 42.840 +*N mux_tree_tapbuf_size6_3_sram[1]:14 *C 30.775 42.840 +*N mux_tree_tapbuf_size6_3_sram[1]:15 *C 30.820 42.795 +*N mux_tree_tapbuf_size6_3_sram[1]:16 *C 30.820 39.485 +*N mux_tree_tapbuf_size6_3_sram[1]:17 *C 30.820 39.440 +*N mux_tree_tapbuf_size6_3_sram[1]:18 *C 31.125 39.440 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_5\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_3_sram[1]:4 0.0001764756 +5 mux_tree_tapbuf_size6_3_sram[1]:5 0.000202736 +6 mux_tree_tapbuf_size6_3_sram[1]:6 0.0001674006 +7 mux_tree_tapbuf_size6_3_sram[1]:7 0.0002780358 +8 mux_tree_tapbuf_size6_3_sram[1]:8 0.0001381072 +9 mux_tree_tapbuf_size6_3_sram[1]:9 0.000137604 +10 mux_tree_tapbuf_size6_3_sram[1]:10 0.000137604 +11 mux_tree_tapbuf_size6_3_sram[1]:11 0.0002591232 +12 mux_tree_tapbuf_size6_3_sram[1]:12 0.0002591232 +13 mux_tree_tapbuf_size6_3_sram[1]:13 0.000379793 +14 mux_tree_tapbuf_size6_3_sram[1]:14 0.0003510451 +15 mux_tree_tapbuf_size6_3_sram[1]:15 0.000215526 +16 mux_tree_tapbuf_size6_3_sram[1]:16 0.000215526 +17 mux_tree_tapbuf_size6_3_sram[1]:17 5.862732e-05 +18 mux_tree_tapbuf_size6_3_sram[1]:18 5.449864e-05 +19 mux_tree_tapbuf_size6_3_sram[1]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.863745e-05 +20 mux_tree_tapbuf_size6_3_sram[1]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.863745e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_3_sram[1]:18 0.152 +1 mux_tree_tapbuf_size6_3_sram[1]:4 mux_left_track_5\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_3_sram[1]:13 mux_tree_tapbuf_size6_3_sram[1]:12 0.0045 +3 mux_tree_tapbuf_size6_3_sram[1]:13 mux_tree_tapbuf_size6_3_sram[1]:8 0.0003035715 +4 mux_tree_tapbuf_size6_3_sram[1]:12 mux_tree_tapbuf_size6_3_sram[1]:11 0.0035625 +5 mux_tree_tapbuf_size6_3_sram[1]:10 mux_tree_tapbuf_size6_3_sram[1]:9 0.001479911 +6 mux_tree_tapbuf_size6_3_sram[1]:11 mux_tree_tapbuf_size6_3_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size6_3_sram[1]:9 mux_left_track_5\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_3_sram[1]:7 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size6_3_sram[1]:7 mux_tree_tapbuf_size6_3_sram[1]:6 0.001799107 +10 mux_tree_tapbuf_size6_3_sram[1]:14 mux_tree_tapbuf_size6_3_sram[1]:13 0.004066964 +11 mux_tree_tapbuf_size6_3_sram[1]:15 mux_tree_tapbuf_size6_3_sram[1]:14 0.0045 +12 mux_tree_tapbuf_size6_3_sram[1]:17 mux_tree_tapbuf_size6_3_sram[1]:16 0.0045 +13 mux_tree_tapbuf_size6_3_sram[1]:16 mux_tree_tapbuf_size6_3_sram[1]:15 0.002955357 +14 mux_tree_tapbuf_size6_3_sram[1]:18 mux_tree_tapbuf_size6_3_sram[1]:17 0.0001657609 +15 mux_tree_tapbuf_size6_3_sram[1]:5 mux_tree_tapbuf_size6_3_sram[1]:4 0.002930804 +16 mux_tree_tapbuf_size6_3_sram[1]:6 mux_tree_tapbuf_size6_3_sram[1]:5 0.0003035715 +17 mux_tree_tapbuf_size6_3_sram[1]:8 mux_tree_tapbuf_size6_3_sram[1]:7 0.001486607 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009552955 //LENGTH 6.805 LUMPCC 0.0001238321 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_2_:X O *L 0 *C 6.725 36.380 +*I mux_left_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 9.200 39.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 9.162 39.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 8.785 39.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 8.740 39.735 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 8.740 36.425 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 8.695 36.380 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 6.763 36.380 + +*CAP +0 mux_left_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.980492e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.980492e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001781359 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001781359 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001767909 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001767909 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 ropt_net_134:10 6.191603e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 ropt_net_134:9 6.191603e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002955357 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003370536 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A1 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007399002 //LENGTH 4.510 LUMPCC 0.000281153 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_1_:X O *L 0 *C 20.065 42.500 +*I mux_left_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 21.890 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 21.890 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 21.620 44.540 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 21.620 44.495 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 21.620 42.545 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 21.575 42.500 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 20.103 42.500 + +*CAP +0 mux_left_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.221007e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.216698e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001221682 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001221682 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.401678e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.401678e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size6_3_sram[1]:4 6.863745e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_3_sram[1]:5 6.863745e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 optlc_net_107:20 5.490996e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_107:21 5.490996e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 optlc_net_107:45 1.702913e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_107:22 1.702913e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001314732 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001741072 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001467391 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006610506 //LENGTH 4.505 LUMPCC 0.0001519339 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_1_:X O *L 0 *C 25.125 71.740 +*I mux_left_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 23.290 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 23.328 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 24.795 69.700 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 24.840 69.745 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 24.840 71.695 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 24.840 71.740 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 25.125 71.740 + +*CAP +0 mux_left_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001033056 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001033056 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.65778e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.65778e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.391534e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.343469e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 left_top_grid_pin_45_[0]:9 1.523004e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 left_top_grid_pin_45_[0]:7 1.523004e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 left_top_grid_pin_45_[0]:6 6.073689e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_top_grid_pin_45_[0]:7 6.073689e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001310268 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741071 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008301559 //LENGTH 7.540 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_1_:X O *L 0 *C 77.565 42.500 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.815 42.500 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 84.778 42.500 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 77.603 42.500 + +*CAP +0 mux_top_track_8\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004140779 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0004140779 + +*RES +0 mux_top_track_8\/mux_l1_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00640625 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004631605 //LENGTH 3.515 LUMPCC 0.000104203 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_1_:X O *L 0 *C 42.605 37.060 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 45.830 37.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 45.793 37.060 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 42.643 37.060 + +*CAP +0 mux_left_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001784787 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001784787 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_3_sram[1]:4 5.21015e-05 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_3_sram[1]:3 5.21015e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0028125 + +*END + +*D_NET mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001044368 //LENGTH 6.887 LUMPCC 0.0004855571 DR + +*CONN +*I mux_top_track_14\/mux_l1_in_0_:X O *L 0 *C 44.445 53.380 +*I mux_top_track_14\/mux_l2_in_0_:A1 I *L 0.005458 *C 48.508 55.483 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 47.425 55.420 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 47.380 55.375 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 47.380 53.425 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 47.335 53.380 +*N mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 44.483 53.380 + +*CAP +0 mux_top_track_14\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_14\/mux_l2_in_0_:A1 9.218614e-05 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.218614e-05 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001350295 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001350295 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.168965e-05 +6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.168965e-05 +7 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_37_[0]:10 0.0001210715 +8 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_37_[0]:9 0.0001210715 +9 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_2_sram[0]:28 0.0001210715 +10 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_2_sram[0]:29 0.0001210715 +11 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_2_sram[0]:30 6.355374e-07 +12 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_2_sram[0]:31 6.355374e-07 + +*RES +0 mux_top_track_14\/mux_l1_in_0_:X mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002546875 +2 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.001741071 +4 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_14\/mux_l2_in_0_:A1 0.0009665179 +5 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0] 0.007038614 //LENGTH 52.610 LUMPCC 0.0008860279 DR + +*CONN +*I mux_top_track_28\/mux_l2_in_0_:X O *L 0 *C 46.285 95.880 +*I mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 94.625 99.105 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 94.588 99.000 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.965 98.940 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.920 98.895 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.920 95.938 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 92.913 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 46.928 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 46.920 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 46.875 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 46.323 95.880 + +*CAP +0 mux_top_track_28\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001073389 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001073389 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001780547 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001780547 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00271127 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00271127 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 3.5313e-05 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.097311e-05 +10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.097311e-05 +11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:141 4.476693e-05 +12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:142 4.48371e-05 +13 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:146 1.885187e-06 +14 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:151 4.196062e-06 +15 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:156 1.337581e-05 +16 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:164 1.062189e-05 +17 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:167 2.864439e-05 +18 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:80 1.885187e-06 +19 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:136 4.476693e-05 +20 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:141 4.48371e-05 +21 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:146 4.196062e-06 +22 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:151 1.337581e-05 +23 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:156 2.864439e-05 +24 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:163 1.062189e-05 +25 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[16]:11 0.0001489114 +26 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[16]:12 0.0001489114 +27 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_35_[0]:23 0.0001457752 +28 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_35_[0]:22 0.0001457752 + +*RES +0 mux_top_track_28\/mux_l2_in_0_:X mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.152 +1 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004933036 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.007204317 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002640625 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001448661 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_28\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001116531 //LENGTH 9.440 LUMPCC 0 DR + +*CONN +*I mux_left_track_15\/mux_l2_in_0_:X O *L 0 *C 7.995 58.140 +*I mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.040 50.180 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 7.078 50.273 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 7.775 50.320 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 7.820 50.365 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 7.820 58.095 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 7.820 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 7.995 58.140 + +*CAP +0 mux_left_track_15\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.074813e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.074813e-05 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004351665 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004351665 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.436636e-05 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.833573e-05 + +*RES +0 mux_left_track_15\/mux_l2_in_0_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0006227679 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006901786 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002917589 //LENGTH 16.960 LUMPCC 0.001562121 DR + +*CONN +*I mux_left_track_19\/mux_l2_in_0_:X O *L 0 *C 19.955 28.220 +*I mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.950 31.460 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 7.950 31.460 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 9.155 31.620 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 9.200 31.575 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 9.200 29.978 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 9.207 29.920 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 17.012 29.920 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 17.020 29.863 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 17.020 28.265 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 17.065 28.220 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 19.918 28.220 + +*CAP +0 mux_left_track_19\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001290598 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.637011e-05 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.019787e-05 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.019787e-05 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002029887 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002029887 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001126217 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001126217 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001582106 +11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001582106 +12 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[16] 0.0001180096 +13 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[16]:7 0.0001180096 +14 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 optlc_net_107:40 0.0001192238 +15 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 optlc_net_107:41 0.0001192238 +16 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001754417 +17 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001754417 +18 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_115:6 3.487846e-05 +19 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_115:7 3.487846e-05 +20 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_115:8 0.0003314913 +21 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 ropt_net_115:10 2.01578e-06 +22 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 ropt_net_115:9 0.0003314913 +23 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 ropt_net_115:11 2.01578e-06 + +*RES +0 mux_left_track_19\/mux_l2_in_0_:X mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001075893 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001426339 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001222783 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001426339 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002546875 + +*END + +*D_NET chany_top_out[4] 0.000447175 //LENGTH 3.955 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 100.280 99.960 +*P chany_top_out[4] O *L 0.7423 *C 98.900 102.070 +*N chany_top_out[4]:2 *C 98.900 100.005 +*N chany_top_out[4]:3 *C 98.945 99.960 +*N chany_top_out[4]:4 *C 100.243 99.960 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 chany_top_out[4] 0.0001206932 +2 chany_top_out[4]:2 0.0001206932 +3 chany_top_out[4]:3 0.0001023943 +4 chany_top_out[4]:4 0.0001023943 + +*RES +0 ropt_mt_inst_736:X chany_top_out[4]:4 0.152 +1 chany_top_out[4]:4 chany_top_out[4]:3 0.001158482 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0045 +3 chany_top_out[4]:2 chany_top_out[4] 0.00184375 + +*END + +*D_NET chany_top_in[6] 0.01697531 //LENGTH 162.025 LUMPCC 0.003995829 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 74.980 102.070 +*I ropt_mt_inst_729:A I *L 0.001767 *C 3.220 20.400 +*N chany_top_in[6]:2 *C 3.258 20.400 +*N chany_top_in[6]:3 *C 5.015 20.400 +*N chany_top_in[6]:4 *C 5.060 20.355 +*N chany_top_in[6]:5 *C 5.060 17.725 +*N chany_top_in[6]:6 *C 5.105 17.680 +*N chany_top_in[6]:7 *C 17.895 17.680 +*N chany_top_in[6]:8 *C 17.940 17.725 +*N chany_top_in[6]:9 *C 17.940 20.355 +*N chany_top_in[6]:10 *C 17.985 20.400 +*N chany_top_in[6]:11 *C 19.275 20.400 +*N chany_top_in[6]:12 *C 19.320 20.445 +*N chany_top_in[6]:13 *C 19.320 23.062 +*N chany_top_in[6]:14 *C 19.328 23.120 +*N chany_top_in[6]:15 *C 69.155 23.120 +*N chany_top_in[6]:16 *C 74.500 23.120 +*N chany_top_in[6]:17 *C 74.520 23.128 +*N chany_top_in[6]:18 *C 74.520 72.955 +*N chany_top_in[6]:19 *C 74.520 100.633 +*N chany_top_in[6]:20 *C 74.535 100.640 +*N chany_top_in[6]:21 *C 74.978 100.640 +*N chany_top_in[6]:22 *C 74.980 100.698 + +*CAP +0 chany_top_in[6] 7.222219e-05 +1 ropt_mt_inst_729:A 1e-06 +2 chany_top_in[6]:2 0.0001208652 +3 chany_top_in[6]:3 0.0001208652 +4 chany_top_in[6]:4 0.0001656269 +5 chany_top_in[6]:5 0.0001656269 +6 chany_top_in[6]:6 0.0006509017 +7 chany_top_in[6]:7 0.0006509017 +8 chany_top_in[6]:8 0.0001455194 +9 chany_top_in[6]:9 0.0001455194 +10 chany_top_in[6]:10 0.0001195266 +11 chany_top_in[6]:11 0.0001195266 +12 chany_top_in[6]:12 0.0001497594 +13 chany_top_in[6]:13 0.0001497594 +14 chany_top_in[6]:14 0.002068791 +15 chany_top_in[6]:15 0.002354976 +16 chany_top_in[6]:16 0.0002861854 +17 chany_top_in[6]:17 0.001856346 +18 chany_top_in[6]:18 0.002659038 +19 chany_top_in[6]:19 0.0008026919 +20 chany_top_in[6]:20 5.080325e-05 +21 chany_top_in[6]:21 5.080325e-05 +22 chany_top_in[6]:22 7.222219e-05 +23 chany_top_in[6] chany_top_in[3] 2.333784e-05 +24 chany_top_in[6]:17 chany_top_in[3]:11 0.0003768706 +25 chany_top_in[6]:19 chany_top_in[3]:12 0.0003652919 +26 chany_top_in[6]:22 chany_top_in[3]:15 2.333784e-05 +27 chany_top_in[6]:18 chany_top_in[3]:11 0.0003652919 +28 chany_top_in[6]:18 chany_top_in[3]:12 0.0003768706 +29 chany_top_in[6]:17 chany_top_in[0]:8 0.0004033584 +30 chany_top_in[6]:19 chany_top_in[0]:9 0.000552015 +31 chany_top_in[6]:18 chany_top_in[0]:8 0.000552015 +32 chany_top_in[6]:18 chany_top_in[0]:9 0.0004033584 +33 chany_top_in[6]:14 chanx_left_in[17] 0.0001469313 +34 chany_top_in[6]:14 chanx_left_in[17]:7 0.0001301095 +35 chany_top_in[6]:15 chanx_left_in[17]:6 0.0001301095 +36 chany_top_in[6]:15 chanx_left_in[17]:8 0.0001469313 + +*RES +0 chany_top_in[6] chany_top_in[6]:22 0.001225446 +1 chany_top_in[6]:2 ropt_mt_inst_729:A 0.152 +2 chany_top_in[6]:3 chany_top_in[6]:2 0.001569196 +3 chany_top_in[6]:4 chany_top_in[6]:3 0.0045 +4 chany_top_in[6]:6 chany_top_in[6]:5 0.0045 +5 chany_top_in[6]:5 chany_top_in[6]:4 0.002348214 +6 chany_top_in[6]:7 chany_top_in[6]:6 0.01141964 +7 chany_top_in[6]:8 chany_top_in[6]:7 0.0045 +8 chany_top_in[6]:10 chany_top_in[6]:9 0.0045 +9 chany_top_in[6]:9 chany_top_in[6]:8 0.002348214 +10 chany_top_in[6]:11 chany_top_in[6]:10 0.001151786 +11 chany_top_in[6]:12 chany_top_in[6]:11 0.0045 +12 chany_top_in[6]:13 chany_top_in[6]:12 0.002337054 +13 chany_top_in[6]:14 chany_top_in[6]:13 0.00341 +14 chany_top_in[6]:16 chany_top_in[6]:15 0.0008373833 +15 chany_top_in[6]:17 chany_top_in[6]:16 0.00341 +16 chany_top_in[6]:20 chany_top_in[6]:19 0.00341 +17 chany_top_in[6]:19 chany_top_in[6]:18 0.004336142 +18 chany_top_in[6]:22 chany_top_in[6]:21 0.00341 +19 chany_top_in[6]:21 chany_top_in[6]:20 6.499218e-05 +20 chany_top_in[6]:15 chany_top_in[6]:14 0.007806308 +21 chany_top_in[6]:18 chany_top_in[6]:17 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_16_ccff_tail[0] 0.0007501584 //LENGTH 5.600 LUMPCC 0 DR + +*CONN +*I mem_left_track_15\/FTB_29__34:X O *L 0 *C 7.585 49.640 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 4.315 47.940 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 *C 4.315 47.940 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 *C 4.600 47.940 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 *C 4.600 47.985 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 *C 4.600 49.595 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 *C 4.645 49.640 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 *C 7.548 49.640 + +*CAP +0 mem_left_track_15\/FTB_29__34:X 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 5.171839e-05 +3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 4.983076e-05 +4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 0.0001127167 +5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 0.0001127167 +6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 0.000210588 +7 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 0.000210588 + +*RES +0 mem_left_track_15\/FTB_29__34:X mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 8.967391e-05 +3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 0.002591518 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_8_ccff_tail[0] 0.0008399553 //LENGTH 6.660 LUMPCC 0.0001236528 DR + +*CONN +*I mem_top_track_28\/FTB_21__26:X O *L 0 *C 37.450 93.500 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 33.760 91.460 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 *C 33.797 91.460 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 *C 36.295 91.460 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 *C 36.340 91.505 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 *C 36.340 93.455 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 *C 36.385 93.500 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 *C 37.413 93.500 + +*CAP +0 mem_top_track_28\/FTB_21__26:X 1e-06 +1 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 0.0001802758 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 0.0001802758 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 9.127955e-05 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 9.127955e-05 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 8.559586e-05 +7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 8.559586e-05 +8 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 top_left_grid_pin_36_[0]:18 6.18264e-05 +9 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 top_left_grid_pin_36_[0]:22 6.18264e-05 + +*RES +0 mem_top_track_28\/FTB_21__26:X mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 0.002229911 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 0.0009174108 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[2] 0.002338299 //LENGTH 19.220 LUMPCC 0.0003265114 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 70.225 55.760 +*I mem_top_track_2\/FTB_5__10:A I *L 0.001746 *C 74.520 53.040 +*I mux_top_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 67.060 63.580 +*N mux_tree_tapbuf_size5_0_sram[2]:3 *C 67.097 63.580 +*N mux_tree_tapbuf_size5_0_sram[2]:4 *C 70.335 63.580 +*N mux_tree_tapbuf_size5_0_sram[2]:5 *C 70.380 63.535 +*N mux_tree_tapbuf_size5_0_sram[2]:6 *C 74.483 53.040 +*N mux_tree_tapbuf_size5_0_sram[2]:7 *C 70.425 53.040 +*N mux_tree_tapbuf_size5_0_sram[2]:8 *C 70.380 53.085 +*N mux_tree_tapbuf_size5_0_sram[2]:9 *C 70.380 55.760 +*N mux_tree_tapbuf_size5_0_sram[2]:10 *C 70.380 55.760 +*N mux_tree_tapbuf_size5_0_sram[2]:11 *C 70.225 55.760 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_2\/FTB_5__10:A 1e-06 +2 mux_top_track_2\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_0_sram[2]:3 0.0001993312 +4 mux_tree_tapbuf_size5_0_sram[2]:4 0.0001993312 +5 mux_tree_tapbuf_size5_0_sram[2]:5 0.0004251965 +6 mux_tree_tapbuf_size5_0_sram[2]:6 0.0001547894 +7 mux_tree_tapbuf_size5_0_sram[2]:7 0.0001547894 +8 mux_tree_tapbuf_size5_0_sram[2]:8 0.000156836 +9 mux_tree_tapbuf_size5_0_sram[2]:9 0.00061491 +10 mux_tree_tapbuf_size5_0_sram[2]:10 5.396285e-05 +11 mux_tree_tapbuf_size5_0_sram[2]:11 4.964073e-05 +12 mux_tree_tapbuf_size5_0_sram[2]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001632557 +13 mux_tree_tapbuf_size5_0_sram[2]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001632557 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_0_sram[2]:11 0.152 +1 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:6 0.003622768 +2 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size5_0_sram[2]:6 mem_top_track_2\/FTB_5__10:A 0.152 +4 mux_tree_tapbuf_size5_0_sram[2]:4 mux_tree_tapbuf_size5_0_sram[2]:3 0.002890625 +5 mux_tree_tapbuf_size5_0_sram[2]:5 mux_tree_tapbuf_size5_0_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size5_0_sram[2]:3 mux_top_track_2\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size5_0_sram[2]:10 mux_tree_tapbuf_size5_0_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:8 0.002388393 +9 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:5 0.006941965 +10 mux_tree_tapbuf_size5_0_sram[2]:11 mux_tree_tapbuf_size5_0_sram[2]:10 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.001690934 //LENGTH 15.480 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 96.445 71.740 +*I mux_top_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 89.600 74.460 +*I mem_top_track_0\/FTB_1__6:A I *L 0.001746 *C 90.160 69.360 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 90.160 69.360 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 89.638 74.460 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 90.115 74.460 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 90.160 74.415 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 90.160 69.745 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 90.198 69.700 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 96.095 69.700 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 96.140 69.745 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 96.140 71.695 +*N mux_tree_tapbuf_size6_0_sram[2]:12 *C 96.140 71.740 +*N mux_tree_tapbuf_size6_0_sram[2]:13 *C 96.445 71.740 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_0\/FTB_1__6:A 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 6.528257e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 4.67486e-05 +5 mux_tree_tapbuf_size6_0_sram[2]:5 4.67486e-05 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0002538886 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0002538886 +8 mux_tree_tapbuf_size6_0_sram[2]:8 0.000368962 +9 mux_tree_tapbuf_size6_0_sram[2]:9 0.0003324163 +10 mux_tree_tapbuf_size6_0_sram[2]:10 0.0001151724 +11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0001151724 +12 mux_tree_tapbuf_size6_0_sram[2]:12 4.675872e-05 +13 mux_tree_tapbuf_size6_0_sram[2]:13 4.28957e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:3 mem_top_track_0\/FTB_1__6:A 0.152 +2 mux_tree_tapbuf_size6_0_sram[2]:4 mux_top_track_0\/mux_l3_in_0_:S 0.152 +3 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0004263393 +4 mux_tree_tapbuf_size6_0_sram[2]:6 mux_tree_tapbuf_size6_0_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:3 0.0001465517 +7 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.004169643 +8 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:8 0.005265625 +9 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.0045 +10 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:11 0.0045 +11 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.001741071 +12 mux_tree_tapbuf_size6_0_sram[2]:13 mux_tree_tapbuf_size6_0_sram[2]:12 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.0005500165 //LENGTH 3.930 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/FTB_1__6:X O *L 0 *C 87.165 68.680 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 88.035 66.300 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 87.998 66.300 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 87.445 66.300 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 87.400 66.345 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 87.400 68.635 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 87.400 68.680 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 87.165 68.680 + +*CAP +0 mem_top_track_0\/FTB_1__6:X 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 7.144883e-05 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 7.144883e-05 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001410667 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001410667 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 6.158736e-05 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 6.139813e-05 + +*RES +0 mem_top_track_0\/FTB_1__6:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001095834 //LENGTH 9.050 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_1_:X O *L 0 *C 86.765 69.020 +*I mux_top_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 88.495 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 88.495 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 88.780 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 88.780 75.095 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 88.780 69.065 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 88.735 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 86.803 69.020 + +*CAP +0 mux_top_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.06705e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.547531e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003511622 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003511622 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001426821 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001426821 + +*RES +0 mux_top_track_0\/mux_l2_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001548913 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.005383929 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002594098 //LENGTH 15.355 LUMPCC 0.001054544 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_0_:X O *L 0 *C 11.675 36.040 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.625 28.405 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 5.663 28.475 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 5.950 28.530 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 5.980 28.605 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 5.980 29.183 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 5.988 29.240 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 11.953 29.240 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 11.960 29.298 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 11.960 35.995 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 11.960 36.040 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 11.675 36.040 + +*CAP +0 mux_left_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.16134e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.16134e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.765735e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.765735e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001783312 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001783312 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0004305072 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0004305072 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 6.090307e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 6.04327e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[16]:7 0.0003518303 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[16] 0.0003518303 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001754417 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001754417 + +*RES +0 mux_left_track_1\/mux_l3_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0001548913 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.00597991 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009345165 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000515625 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001796875 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003286757 //LENGTH 24.630 LUMPCC 0.000843708 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_1_:X O *L 0 *C 59.165 63.240 +*I mux_top_track_6\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.215 48.280 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 57.178 48.280 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 53.865 48.280 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 53.820 48.325 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 53.820 63.195 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 53.865 63.240 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 59.128 63.240 + +*CAP +0 mux_top_track_6\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002459768 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002459768 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0006531253 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006531253 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003214223 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003214223 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_39_[0]:6 4.807903e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_39_[0]:7 8.903932e-05 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_39_[0]:5 4.807903e-05 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_39_[0]:6 8.903932e-05 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_1_sram[0]:6 6.710534e-05 +13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_1_sram[0]:9 0.000215367 +14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_1_sram[0]:15 2.526683e-07 +15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_1_sram[0]:13 2.010601e-06 +16 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_1_sram[0]:9 6.710534e-05 +17 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_1_sram[0]:10 0.000215367 +18 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_1_sram[0]:14 2.526683e-07 +19 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size5_1_sram[0]:12 2.010601e-06 + +*RES +0 mux_top_track_6\/mux_l1_in_1_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_6\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002957589 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01327679 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.004698661 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005734197 //LENGTH 3.280 LUMPCC 0 DR + +*CONN +*I mux_left_track_7\/mux_l2_in_1_:X O *L 0 *C 28.695 57.800 +*I mux_left_track_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 28.350 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 28.350 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 28.520 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 28.520 55.465 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 28.520 57.755 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 28.520 57.800 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 28.695 57.800 + +*CAP +0 mux_left_track_7\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_7\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.824898e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.003275e-05 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001648071 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001648071 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.354265e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.998108e-05 + +*RES +0 mux_left_track_7\/mux_l2_in_1_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_7\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.239132e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003734506 //LENGTH 34.945 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 43.875 36.380 +*I mux_left_track_25\/BUFT_RR_45:A I *L 0.001746 *C 26.220 20.400 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 26.220 20.400 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 26.220 20.740 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 44.115 20.740 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 44.160 20.785 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 44.160 36.335 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 44.160 36.380 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 43.875 36.380 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/BUFT_RR_45:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.931866e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000963447 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0009345422 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000831897 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000831897 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.670253e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.470167e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001548913 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.01388393 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.01597768 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_25\/BUFT_RR_45:A 0.152 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007299747 //LENGTH 5.660 LUMPCC 0 DR + +*CONN +*I mux_top_track_22\/mux_l2_in_0_:X O *L 0 *C 91.825 91.800 +*I mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 92.280 96.725 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 92.280 96.725 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 92.000 96.560 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 92.000 96.515 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 92.000 91.845 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 92.000 91.800 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 91.825 91.800 + +*CAP +0 mux_top_track_22\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.332135e-05 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.97297e-05 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002602093 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002602093 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.96632e-05 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.484174e-05 + +*RES +0 mux_top_track_22\/mux_l2_in_0_:X mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001521739 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001534546 //LENGTH 13.045 LUMPCC 0.0002499306 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_0_:X O *L 0 *C 42.605 75.140 +*I mux_top_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 46.560 83.300 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 46.523 83.300 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 44.665 83.300 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 44.620 83.255 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 44.620 75.185 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 44.575 75.140 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 42.643 75.140 + +*CAP +0 mux_top_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001474853 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001474853 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00035955 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00035955 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001342725 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001342725 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_38_[0]:25 0.000100967 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_38_[0]:21 1.117164e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 top_left_grid_pin_38_[0]:23 1.282669e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_38_[0]:24 0.000100967 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 top_left_grid_pin_38_[0]:22 1.282669e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 top_left_grid_pin_38_[0]:23 1.117164e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007205357 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001292761 //LENGTH 9.330 LUMPCC 0.0003524964 DR + +*CONN +*I mux_left_track_15\/mux_l1_in_0_:X O *L 0 *C 12.705 64.260 +*I mux_left_track_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 10.120 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 10.120 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 10.120 58.185 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 10.120 64.215 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 10.165 64.260 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 12.668 64.260 + +*CAP +0 mux_left_track_15\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_15\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.333252e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002682744 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002682744 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001841918 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001841918 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_16_sram[0]:3 3.057554e-05 +8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_16_sram[0]:4 3.057554e-05 +9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_16_sram[0]:5 1.399515e-05 +10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_16_sram[0]:10 9.771409e-06 +11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_16_sram[0]:9 9.771409e-06 +12 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_16_sram[0]:10 1.399515e-05 +13 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_109:17 0.0001219061 +14 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_109:18 0.0001219061 + +*RES +0 mux_left_track_15\/mux_l1_in_0_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.002234375 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005383929 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_15\/mux_l2_in_0_:A1 0.152 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET ropt_net_128 0.001239035 //LENGTH 10.095 LUMPCC 9.797898e-05 DR + +*CONN +*I ropt_mt_inst_724:X O *L 0 *C 9.855 25.160 +*I ropt_mt_inst_733:A I *L 0.001767 *C 3.220 23.120 +*N ropt_net_128:2 *C 3.220 23.120 +*N ropt_net_128:3 *C 3.220 23.165 +*N ropt_net_128:4 *C 3.220 23.800 +*N ropt_net_128:5 *C 4.120 23.800 +*N ropt_net_128:6 *C 4.128 23.800 +*N ropt_net_128:7 *C 6.893 23.800 +*N ropt_net_128:8 *C 6.900 23.858 +*N ropt_net_128:9 *C 6.900 25.115 +*N ropt_net_128:10 *C 6.945 25.160 +*N ropt_net_128:11 *C 9.818 25.160 + +*CAP +0 ropt_mt_inst_724:X 1e-06 +1 ropt_mt_inst_733:A 1e-06 +2 ropt_net_128:2 2.981588e-05 +3 ropt_net_128:3 4.689346e-05 +4 ropt_net_128:4 9.648331e-05 +5 ropt_net_128:5 8.022081e-05 +6 ropt_net_128:6 0.0001915954 +7 ropt_net_128:7 0.0001915954 +8 ropt_net_128:8 7.805559e-05 +9 ropt_net_128:9 7.805559e-05 +10 ropt_net_128:10 0.0001731704 +11 ropt_net_128:11 0.0001731704 +12 ropt_net_128:8 ropt_net_117:5 7.372549e-06 +13 ropt_net_128:10 ropt_net_117:2 4.161694e-05 +14 ropt_net_128:9 ropt_net_117:4 7.372549e-06 +15 ropt_net_128:11 ropt_net_117:3 4.161694e-05 + +*RES +0 ropt_mt_inst_724:X ropt_net_128:11 0.152 +1 ropt_net_128:2 ropt_mt_inst_733:A 0.152 +2 ropt_net_128:3 ropt_net_128:2 0.0045 +3 ropt_net_128:5 ropt_net_128:4 0.0008035714 +4 ropt_net_128:6 ropt_net_128:5 0.00341 +5 ropt_net_128:8 ropt_net_128:7 0.00341 +6 ropt_net_128:7 ropt_net_128:6 0.0004331833 +7 ropt_net_128:10 ropt_net_128:9 0.0045 +8 ropt_net_128:9 ropt_net_128:8 0.001122768 +9 ropt_net_128:11 ropt_net_128:10 0.002564732 +10 ropt_net_128:4 ropt_net_128:3 0.0005669643 + +*END + +*D_NET ropt_net_131 0.0008825923 //LENGTH 6.970 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_728:X O *L 0 *C 103.235 97.240 +*I ropt_mt_inst_736:A I *L 0.001767 *C 99.360 99.280 +*N ropt_net_131:2 *C 99.360 99.280 +*N ropt_net_131:3 *C 99.360 99.235 +*N ropt_net_131:4 *C 99.360 98.645 +*N ropt_net_131:5 *C 99.405 98.600 +*N ropt_net_131:6 *C 102.995 98.600 +*N ropt_net_131:7 *C 103.040 98.555 +*N ropt_net_131:8 *C 103.040 97.285 +*N ropt_net_131:9 *C 103.040 97.240 +*N ropt_net_131:10 *C 103.235 97.240 + +*CAP +0 ropt_mt_inst_728:X 1e-06 +1 ropt_mt_inst_736:A 1e-06 +2 ropt_net_131:2 2.875065e-05 +3 ropt_net_131:3 5.598784e-05 +4 ropt_net_131:4 5.598784e-05 +5 ropt_net_131:5 0.0002408581 +6 ropt_net_131:6 0.0002408581 +7 ropt_net_131:7 7.500907e-05 +8 ropt_net_131:8 7.500907e-05 +9 ropt_net_131:9 5.297722e-05 +10 ropt_net_131:10 5.515451e-05 + +*RES +0 ropt_mt_inst_728:X ropt_net_131:10 0.152 +1 ropt_net_131:2 ropt_mt_inst_736:A 0.152 +2 ropt_net_131:3 ropt_net_131:2 0.0045 +3 ropt_net_131:5 ropt_net_131:4 0.0045 +4 ropt_net_131:4 ropt_net_131:3 0.0005267857 +5 ropt_net_131:6 ropt_net_131:5 0.003205357 +6 ropt_net_131:7 ropt_net_131:6 0.0045 +7 ropt_net_131:9 ropt_net_131:8 0.0045 +8 ropt_net_131:8 ropt_net_131:7 0.001133929 +9 ropt_net_131:10 ropt_net_131:9 0.0001059783 + +*END + +*D_NET chanx_left_out[18] 0.001157755 //LENGTH 7.615 LUMPCC 0.0002441015 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 7.095 9.520 +*P chanx_left_out[18] O *L 0.7423 *C 1.230 10.200 +*N chanx_left_out[18]:2 *C 1.840 10.200 +*N chanx_left_out[18]:3 *C 1.840 9.520 +*N chanx_left_out[18]:4 *C 5.973 9.520 +*N chanx_left_out[18]:5 *C 5.980 9.520 +*N chanx_left_out[18]:6 *C 6.025 9.520 +*N chanx_left_out[18]:7 *C 7.058 9.520 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 chanx_left_out[18] 8.019591e-05 +2 chanx_left_out[18]:2 0.0001240083 +3 chanx_left_out[18]:3 0.0002557662 +4 chanx_left_out[18]:4 0.0002119539 +5 chanx_left_out[18]:5 3.476308e-05 +6 chanx_left_out[18]:6 0.0001029829 +7 chanx_left_out[18]:7 0.0001029829 +8 chanx_left_out[18]:4 ropt_net_135:7 0.0001220508 +9 chanx_left_out[18]:3 ropt_net_135:6 0.0001220508 + +*RES +0 ropt_mt_inst_740:X chanx_left_out[18]:7 0.152 +1 chanx_left_out[18]:7 chanx_left_out[18]:6 0.0009218751 +2 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0045 +3 chanx_left_out[18]:5 chanx_left_out[18]:4 0.00341 +4 chanx_left_out[18]:4 chanx_left_out[18]:3 0.000647425 +5 chanx_left_out[18]:2 chanx_left_out[18] 9.556666e-05 +6 chanx_left_out[18]:3 chanx_left_out[18]:2 0.0001065333 + +*END + +*D_NET prog_clk[0] 0.09876021 //LENGTH 708.073 LUMPCC 0.01831822 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 29.825 99.960 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 12.685 66.640 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.625 61.200 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.535 55.760 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.410 61.200 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 15.445 53.040 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 11.765 39.440 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 12.225 34.000 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 8.515 31.280 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 10.295 25.840 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 3.025 47.600 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 3.025 44.880 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.165 72.080 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 29.245 72.080 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 34.305 58.480 +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 37.985 61.200 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 24.185 50.320 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.525 50.320 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 46.265 50.320 +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 47.185 44.880 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 55.005 50.320 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 59.145 44.880 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 65.125 42.160 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 75.705 36.720 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 76.625 39.440 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 59.145 36.720 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 68.345 31.280 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.525 28.560 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 67.885 47.600 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 72.485 50.320 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 30.625 47.600 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 24.185 39.440 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 23.265 42.160 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 33.845 42.160 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.685 28.560 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 36.550 25.840 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 43.965 31.280 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.185 34.000 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 26.945 31.280 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 27.820 25.840 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 19.205 25.840 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.085 55.760 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 32.465 91.120 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.465 85.680 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 40.745 77.520 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 38.445 69.360 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.805 63.920 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.345 58.480 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 46.725 66.640 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 49.485 77.520 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 54.545 74.800 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 58.225 77.520 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.045 69.360 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.505 66.640 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 62.825 61.200 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.865 58.480 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 63.285 55.760 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.965 77.520 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 32.005 77.520 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 99.280 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 40.285 99.280 +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 48.105 93.840 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.805 91.120 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 54.545 88.400 +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 60.895 96.560 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 73.405 85.680 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 84.400 85.680 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 83.085 82.960 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 89.505 77.520 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 86.745 66.640 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 88.125 61.200 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 84.905 55.760 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 89.505 72.080 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 91.805 80.240 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 82.605 93.840 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 63.285 88.400 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 68.805 99.280 +*N prog_clk[0]:77 *C 68.767 99.280 +*N prog_clk[0]:78 *C 68.125 99.280 +*N prog_clk[0]:79 *C 68.080 99.280 +*N prog_clk[0]:80 *C 68.073 99.280 +*N prog_clk[0]:81 *C 63.285 88.400 +*N prog_clk[0]:82 *C 63.480 88.400 +*N prog_clk[0]:83 *C 63.480 88.445 +*N prog_clk[0]:84 *C 82.605 93.840 +*N prog_clk[0]:85 *C 82.800 93.840 +*N prog_clk[0]:86 *C 82.800 93.795 +*N prog_clk[0]:87 *C 91.767 80.240 +*N prog_clk[0]:88 *C 91.125 80.240 +*N prog_clk[0]:89 *C 91.080 80.240 +*N prog_clk[0]:90 *C 91.073 80.240 +*N prog_clk[0]:91 *C 86.940 80.240 +*N prog_clk[0]:92 *C 89.468 72.080 +*N prog_clk[0]:93 *C 88.365 72.080 +*N prog_clk[0]:94 *C 88.320 72.080 +*N prog_clk[0]:95 *C 88.312 72.080 +*N prog_clk[0]:96 *C 84.905 55.760 +*N prog_clk[0]:97 *C 85.100 55.760 +*N prog_clk[0]:98 *C 85.100 55.805 +*N prog_clk[0]:99 *C 88.088 61.200 +*N prog_clk[0]:100 *C 87.445 61.200 +*N prog_clk[0]:101 *C 87.400 61.200 +*N prog_clk[0]:102 *C 87.392 61.200 +*N prog_clk[0]:103 *C 85.108 61.200 +*N prog_clk[0]:104 *C 85.100 61.200 +*N prog_clk[0]:105 *C 86.708 66.640 +*N prog_clk[0]:106 *C 85.145 66.640 +*N prog_clk[0]:107 *C 85.100 66.640 +*N prog_clk[0]:108 *C 85.100 72.023 +*N prog_clk[0]:109 *C 85.108 72.080 +*N prog_clk[0]:110 *C 86.940 72.080 +*N prog_clk[0]:111 *C 86.940 72.138 +*N prog_clk[0]:112 *C 89.468 77.520 +*N prog_clk[0]:113 *C 88.365 77.520 +*N prog_clk[0]:114 *C 88.320 77.520 +*N prog_clk[0]:115 *C 88.312 77.520 +*N prog_clk[0]:116 *C 86.948 77.520 +*N prog_clk[0]:117 *C 86.940 77.520 +*N prog_clk[0]:118 *C 86.940 79.502 +*N prog_clk[0]:119 *C 86.940 79.568 +*N prog_clk[0]:120 *C 84.188 79.560 +*N prog_clk[0]:121 *C 84.180 79.618 +*N prog_clk[0]:122 *C 83.085 82.960 +*N prog_clk[0]:123 *C 82.800 82.960 +*N prog_clk[0]:124 *C 82.800 82.915 +*N prog_clk[0]:125 *C 82.800 81.657 +*N prog_clk[0]:126 *C 82.808 81.600 +*N prog_clk[0]:127 *C 84.172 81.600 +*N prog_clk[0]:128 *C 84.180 81.600 +*N prog_clk[0]:129 *C 84.400 85.680 +*N prog_clk[0]:130 *C 84.180 85.680 +*N prog_clk[0]:131 *C 84.180 85.680 +*N prog_clk[0]:132 *C 84.172 85.680 +*N prog_clk[0]:133 *C 82.808 85.680 +*N prog_clk[0]:134 *C 82.800 85.737 +*N prog_clk[0]:135 *C 82.800 92.480 +*N prog_clk[0]:136 *C 82.793 92.480 +*N prog_clk[0]:137 *C 73.405 85.680 +*N prog_clk[0]:138 *C 73.600 85.680 +*N prog_clk[0]:139 *C 73.600 85.725 +*N prog_clk[0]:140 *C 73.600 92.422 +*N prog_clk[0]:141 *C 73.600 92.480 +*N prog_clk[0]:142 *C 63.488 92.480 +*N prog_clk[0]:143 *C 63.480 92.422 +*N prog_clk[0]:144 *C 62.100 92.480 +*N prog_clk[0]:145 *C 62.100 99.223 +*N prog_clk[0]:146 *C 62.100 99.280 +*N prog_clk[0]:147 *C 60.895 96.560 +*N prog_clk[0]:148 *C 60.720 96.560 +*N prog_clk[0]:149 *C 60.720 96.605 +*N prog_clk[0]:150 *C 60.720 99.223 +*N prog_clk[0]:151 *C 60.720 99.280 +*N prog_clk[0]:152 *C 54.545 88.400 +*N prog_clk[0]:153 *C 54.740 88.400 +*N prog_clk[0]:154 *C 54.740 88.445 +*N prog_clk[0]:155 *C 54.740 99.223 +*N prog_clk[0]:156 *C 54.740 99.280 +*N prog_clk[0]:157 *C 45.805 91.120 +*N prog_clk[0]:158 *C 46.000 91.120 +*N prog_clk[0]:159 *C 46.000 91.165 +*N prog_clk[0]:160 *C 48.068 93.840 +*N prog_clk[0]:161 *C 47.425 93.840 +*N prog_clk[0]:162 *C 47.380 93.840 +*N prog_clk[0]:163 *C 47.373 93.840 +*N prog_clk[0]:164 *C 46.008 93.840 +*N prog_clk[0]:165 *C 46.000 93.840 +*N prog_clk[0]:166 *C 46.000 99.223 +*N prog_clk[0]:167 *C 46.000 99.280 +*N prog_clk[0]:168 *C 40.285 99.280 +*N prog_clk[0]:169 *C 40.020 99.280 +*N prog_clk[0]:170 *C 40.020 99.280 +*N prog_clk[0]:171 *C 40.020 99.280 +*N prog_clk[0]:172 *C 32.275 99.280 +*N prog_clk[0]:173 *C 31.545 99.280 +*N prog_clk[0]:174 *C 31.740 99.280 +*N prog_clk[0]:175 *C 31.740 99.280 +*N prog_clk[0]:176 *C 31.745 99.288 +*N prog_clk[0]:177 *C 32.200 99.293 +*N prog_clk[0]:178 *C 32.005 77.520 +*N prog_clk[0]:179 *C 32.200 77.520 +*N prog_clk[0]:180 *C 66.928 77.520 +*N prog_clk[0]:181 *C 66.285 77.520 +*N prog_clk[0]:182 *C 66.240 77.520 +*N prog_clk[0]:183 *C 66.233 77.520 +*N prog_clk[0]:184 *C 63.285 55.760 +*N prog_clk[0]:185 *C 63.480 55.760 +*N prog_clk[0]:186 *C 63.480 55.805 +*N prog_clk[0]:187 *C 73.865 58.480 +*N prog_clk[0]:188 *C 73.600 58.480 +*N prog_clk[0]:189 *C 73.600 58.480 +*N prog_clk[0]:190 *C 73.593 58.480 +*N prog_clk[0]:191 *C 63.488 58.480 +*N prog_clk[0]:192 *C 63.480 58.480 +*N prog_clk[0]:193 *C 62.825 61.200 +*N prog_clk[0]:194 *C 63.020 60.860 +*N prog_clk[0]:195 *C 63.435 60.860 +*N prog_clk[0]:196 *C 63.480 60.860 +*N prog_clk[0]:197 *C 63.480 66.640 +*N prog_clk[0]:198 *C 66.505 66.640 +*N prog_clk[0]:199 *C 66.240 66.640 +*N prog_clk[0]:200 *C 66.240 66.640 +*N prog_clk[0]:201 *C 66.233 66.640 +*N prog_clk[0]:202 *C 63.948 66.640 +*N prog_clk[0]:203 *C 63.940 66.698 +*N prog_clk[0]:204 *C 63.940 69.360 +*N prog_clk[0]:205 *C 66.008 69.360 +*N prog_clk[0]:206 *C 65.365 69.360 +*N prog_clk[0]:207 *C 65.320 69.360 +*N prog_clk[0]:208 *C 65.312 69.360 +*N prog_clk[0]:209 *C 64.407 69.360 +*N prog_clk[0]:210 *C 64.400 69.418 +*N prog_clk[0]:211 *C 64.400 77.463 +*N prog_clk[0]:212 *C 64.400 77.520 +*N prog_clk[0]:213 *C 58.225 77.520 +*N prog_clk[0]:214 *C 58.420 77.520 +*N prog_clk[0]:215 *C 58.420 77.520 +*N prog_clk[0]:216 *C 58.420 77.520 +*N prog_clk[0]:217 *C 54.545 74.800 +*N prog_clk[0]:218 *C 54.740 74.800 +*N prog_clk[0]:219 *C 54.740 74.845 +*N prog_clk[0]:220 *C 54.740 77.463 +*N prog_clk[0]:221 *C 54.740 77.520 +*N prog_clk[0]:222 *C 49.485 77.520 +*N prog_clk[0]:223 *C 49.220 77.520 +*N prog_clk[0]:224 *C 49.220 77.520 +*N prog_clk[0]:225 *C 49.220 77.520 +*N prog_clk[0]:226 *C 46.725 66.640 +*N prog_clk[0]:227 *C 46.460 66.640 +*N prog_clk[0]:228 *C 46.460 66.640 +*N prog_clk[0]:229 *C 45.345 58.480 +*N prog_clk[0]:230 *C 45.540 58.480 +*N prog_clk[0]:231 *C 45.540 58.525 +*N prog_clk[0]:232 *C 45.805 63.920 +*N prog_clk[0]:233 *C 45.540 64.260 +*N prog_clk[0]:234 *C 45.540 64.260 +*N prog_clk[0]:235 *C 45.540 66.640 +*N prog_clk[0]:236 *C 45.532 66.640 +*N prog_clk[0]:237 *C 40.028 66.640 +*N prog_clk[0]:238 *C 40.020 66.698 +*N prog_clk[0]:239 *C 38.445 69.360 +*N prog_clk[0]:240 *C 38.640 69.700 +*N prog_clk[0]:241 *C 39.055 69.700 +*N prog_clk[0]:242 *C 39.100 69.745 +*N prog_clk[0]:243 *C 39.100 70.380 +*N prog_clk[0]:244 *C 40.020 70.380 +*N prog_clk[0]:245 *C 40.708 77.520 +*N prog_clk[0]:246 *C 40.065 77.520 +*N prog_clk[0]:247 *C 40.020 77.520 +*N prog_clk[0]:248 *C 40.020 77.520 +*N prog_clk[0]:249 *C 32.208 77.520 +*N prog_clk[0]:250 *C 32.200 77.520 +*N prog_clk[0]:251 *C 32.465 85.680 +*N prog_clk[0]:252 *C 32.200 86.020 +*N prog_clk[0]:253 *C 32.200 86.020 +*N prog_clk[0]:254 *C 32.465 91.120 +*N prog_clk[0]:255 *C 32.200 91.460 +*N prog_clk[0]:256 *C 32.200 91.460 +*N prog_clk[0]:257 *C 32.200 99.903 +*N prog_clk[0]:258 *C 32.200 99.953 +*N prog_clk[0]:259 *C 31.048 55.760 +*N prog_clk[0]:260 *C 30.405 55.760 +*N prog_clk[0]:261 *C 30.360 55.760 +*N prog_clk[0]:262 *C 19.205 25.840 +*N prog_clk[0]:263 *C 19.320 25.885 +*N prog_clk[0]:264 *C 19.320 26.475 +*N prog_clk[0]:265 *C 19.365 26.520 +*N prog_clk[0]:266 *C 27.600 26.520 +*N prog_clk[0]:267 *C 27.820 25.840 +*N prog_clk[0]:268 *C 27.600 25.840 +*N prog_clk[0]:269 *C 27.600 25.885 +*N prog_clk[0]:270 *C 26.945 31.280 +*N prog_clk[0]:271 *C 27.140 31.280 +*N prog_clk[0]:272 *C 27.140 31.280 +*N prog_clk[0]:273 *C 27.600 31.280 +*N prog_clk[0]:274 *C 47.148 34.000 +*N prog_clk[0]:275 *C 46.505 34.000 +*N prog_clk[0]:276 *C 46.460 33.955 +*N prog_clk[0]:277 *C 46.460 32.698 +*N prog_clk[0]:278 *C 46.453 32.640 +*N prog_clk[0]:279 *C 43.965 31.280 +*N prog_clk[0]:280 *C 43.700 31.280 +*N prog_clk[0]:281 *C 43.700 31.325 +*N prog_clk[0]:282 *C 43.700 32.583 +*N prog_clk[0]:283 *C 43.700 32.640 +*N prog_clk[0]:284 *C 36.513 25.840 +*N prog_clk[0]:285 *C 35.925 25.840 +*N prog_clk[0]:286 *C 35.880 25.885 +*N prog_clk[0]:287 *C 35.685 28.560 +*N prog_clk[0]:288 *C 35.880 28.220 +*N prog_clk[0]:289 *C 35.880 28.220 +*N prog_clk[0]:290 *C 35.880 32.583 +*N prog_clk[0]:291 *C 35.880 32.640 +*N prog_clk[0]:292 *C 27.608 32.640 +*N prog_clk[0]:293 *C 27.600 32.640 +*N prog_clk[0]:294 *C 33.845 42.160 +*N prog_clk[0]:295 *C 33.580 42.160 +*N prog_clk[0]:296 *C 33.580 42.160 +*N prog_clk[0]:297 *C 33.573 42.160 +*N prog_clk[0]:298 *C 23.265 42.160 +*N prog_clk[0]:299 *C 23.000 42.160 +*N prog_clk[0]:300 *C 23.000 42.160 +*N prog_clk[0]:301 *C 23.008 42.160 +*N prog_clk[0]:302 *C 24.185 39.440 +*N prog_clk[0]:303 *C 24.380 39.440 +*N prog_clk[0]:304 *C 24.380 39.485 +*N prog_clk[0]:305 *C 24.380 42.102 +*N prog_clk[0]:306 *C 24.380 42.160 +*N prog_clk[0]:307 *C 27.600 42.160 +*N prog_clk[0]:308 *C 27.600 42.160 +*N prog_clk[0]:309 *C 30.625 47.600 +*N prog_clk[0]:310 *C 30.360 47.600 +*N prog_clk[0]:311 *C 30.360 47.600 +*N prog_clk[0]:312 *C 30.353 47.600 +*N prog_clk[0]:313 *C 27.608 47.600 +*N prog_clk[0]:314 *C 27.600 47.600 +*N prog_clk[0]:315 *C 72.448 50.320 +*N prog_clk[0]:316 *C 71.805 50.320 +*N prog_clk[0]:317 *C 71.760 50.320 +*N prog_clk[0]:318 *C 71.752 50.320 +*N prog_clk[0]:319 *C 67.620 50.320 +*N prog_clk[0]:320 *C 67.885 47.600 +*N prog_clk[0]:321 *C 67.620 47.600 +*N prog_clk[0]:322 *C 67.620 47.645 +*N prog_clk[0]:323 *C 67.620 49.583 +*N prog_clk[0]:324 *C 67.620 49.648 +*N prog_clk[0]:325 *C 60.525 28.560 +*N prog_clk[0]:326 *C 60.260 28.560 +*N prog_clk[0]:327 *C 60.260 28.605 +*N prog_clk[0]:328 *C 68.345 31.280 +*N prog_clk[0]:329 *C 68.080 31.280 +*N prog_clk[0]:330 *C 68.080 31.280 +*N prog_clk[0]:331 *C 68.073 31.280 +*N prog_clk[0]:332 *C 60.268 31.280 +*N prog_clk[0]:333 *C 60.260 31.223 +*N prog_clk[0]:334 *C 59.340 31.280 +*N prog_clk[0]:335 *C 59.145 36.720 +*N prog_clk[0]:336 *C 59.340 37.060 +*N prog_clk[0]:337 *C 59.340 37.060 +*N prog_clk[0]:338 *C 76.625 39.440 +*N prog_clk[0]:339 *C 76.360 39.440 +*N prog_clk[0]:340 *C 76.360 39.440 +*N prog_clk[0]:341 *C 75.705 36.720 +*N prog_clk[0]:342 *C 75.900 36.720 +*N prog_clk[0]:343 *C 75.900 36.765 +*N prog_clk[0]:344 *C 75.900 39.440 +*N prog_clk[0]:345 *C 75.900 42.102 +*N prog_clk[0]:346 *C 75.892 42.160 +*N prog_clk[0]:347 *C 65.125 42.160 +*N prog_clk[0]:348 *C 64.860 42.160 +*N prog_clk[0]:349 *C 64.860 42.160 +*N prog_clk[0]:350 *C 64.860 42.160 +*N prog_clk[0]:351 *C 59.348 42.160 +*N prog_clk[0]:352 *C 59.340 42.160 +*N prog_clk[0]:353 *C 59.145 44.880 +*N prog_clk[0]:354 *C 59.340 44.540 +*N prog_clk[0]:355 *C 59.340 44.540 +*N prog_clk[0]:356 *C 59.340 49.583 +*N prog_clk[0]:357 *C 59.340 49.640 +*N prog_clk[0]:358 *C 59.340 50.320 +*N prog_clk[0]:359 *C 55.005 50.320 +*N prog_clk[0]:360 *C 54.740 50.320 +*N prog_clk[0]:361 *C 54.740 50.320 +*N prog_clk[0]:362 *C 54.740 50.320 +*N prog_clk[0]:363 *C 47.148 44.880 +*N prog_clk[0]:364 *C 46.505 44.880 +*N prog_clk[0]:365 *C 46.460 44.925 +*N prog_clk[0]:366 *C 46.265 50.320 +*N prog_clk[0]:367 *C 46.460 50.320 +*N prog_clk[0]:368 *C 46.460 50.320 +*N prog_clk[0]:369 *C 46.460 50.320 +*N prog_clk[0]:370 *C 37.525 50.320 +*N prog_clk[0]:371 *C 37.260 50.320 +*N prog_clk[0]:372 *C 37.260 50.320 +*N prog_clk[0]:373 *C 37.260 50.320 +*N prog_clk[0]:374 *C 24.185 50.320 +*N prog_clk[0]:375 *C 24.380 50.320 +*N prog_clk[0]:376 *C 24.380 50.320 +*N prog_clk[0]:377 *C 24.388 50.320 +*N prog_clk[0]:378 *C 27.600 50.320 +*N prog_clk[0]:379 *C 27.600 50.320 +*N prog_clk[0]:380 *C 27.600 55.703 +*N prog_clk[0]:381 *C 27.608 55.760 +*N prog_clk[0]:382 *C 29.893 55.760 +*N prog_clk[0]:383 *C 29.900 55.760 +*N prog_clk[0]:384 *C 37.948 61.200 +*N prog_clk[0]:385 *C 36.385 61.200 +*N prog_clk[0]:386 *C 36.340 61.155 +*N prog_clk[0]:387 *C 36.340 59.898 +*N prog_clk[0]:388 *C 36.333 59.840 +*N prog_clk[0]:389 *C 34.305 58.480 +*N prog_clk[0]:390 *C 34.500 58.480 +*N prog_clk[0]:391 *C 34.500 58.525 +*N prog_clk[0]:392 *C 34.500 59.783 +*N prog_clk[0]:393 *C 34.500 59.840 +*N prog_clk[0]:394 *C 29.908 59.840 +*N prog_clk[0]:395 *C 29.900 59.783 +*N prog_clk[0]:396 *C 29.440 59.840 +*N prog_clk[0]:397 *C 29.245 72.080 +*N prog_clk[0]:398 *C 29.440 72.080 +*N prog_clk[0]:399 *C 7.165 72.080 +*N prog_clk[0]:400 *C 7.360 72.080 +*N prog_clk[0]:401 *C 7.360 72.080 +*N prog_clk[0]:402 *C 7.368 72.080 +*N prog_clk[0]:403 *C 3.025 44.880 +*N prog_clk[0]:404 *C 2.760 44.880 +*N prog_clk[0]:405 *C 2.760 44.925 +*N prog_clk[0]:406 *C 3.025 47.600 +*N prog_clk[0]:407 *C 2.760 47.600 +*N prog_clk[0]:408 *C 2.760 47.600 +*N prog_clk[0]:409 *C 2.768 47.600 +*N prog_clk[0]:410 *C 10.640 39.440 +*N prog_clk[0]:411 *C 10.295 25.840 +*N prog_clk[0]:412 *C 10.120 25.840 +*N prog_clk[0]:413 *C 10.120 25.885 +*N prog_clk[0]:414 *C 8.515 31.280 +*N prog_clk[0]:415 *C 8.280 30.940 +*N prog_clk[0]:416 *C 8.280 30.895 +*N prog_clk[0]:417 *C 8.280 29.240 +*N prog_clk[0]:418 *C 10.120 29.240 +*N prog_clk[0]:419 *C 10.120 31.280 +*N prog_clk[0]:420 *C 11.040 31.280 +*N prog_clk[0]:421 *C 12.188 34.000 +*N prog_clk[0]:422 *C 11.040 34.000 +*N prog_clk[0]:423 *C 11.040 33.660 +*N prog_clk[0]:424 *C 11.040 33.660 +*N prog_clk[0]:425 *C 11.728 39.440 +*N prog_clk[0]:426 *C 11.085 39.440 +*N prog_clk[0]:427 *C 11.040 39.440 +*N prog_clk[0]:428 *C 11.040 39.440 +*N prog_clk[0]:429 *C 11.040 39.448 +*N prog_clk[0]:430 *C 11.040 47.593 +*N prog_clk[0]:431 *C 11.040 47.600 +*N prog_clk[0]:432 *C 13.793 47.600 +*N prog_clk[0]:433 *C 13.800 47.657 +*N prog_clk[0]:434 *C 13.800 53.380 +*N prog_clk[0]:435 *C 15.408 53.040 +*N prog_clk[0]:436 *C 14.260 53.040 +*N prog_clk[0]:437 *C 14.260 53.380 +*N prog_clk[0]:438 *C 14.260 53.425 +*N prog_clk[0]:439 *C 14.260 61.200 +*N prog_clk[0]:440 *C 16.373 61.200 +*N prog_clk[0]:441 *C 14.260 61.200 +*N prog_clk[0]:442 *C 14.260 60.860 +*N prog_clk[0]:443 *C 13.800 60.860 +*N prog_clk[0]:444 *C 13.800 61.200 +*N prog_clk[0]:445 *C 7.498 55.760 +*N prog_clk[0]:446 *C 6.900 55.760 +*N prog_clk[0]:447 *C 6.900 55.420 +*N prog_clk[0]:448 *C 6.900 55.465 +*N prog_clk[0]:449 *C 7.588 61.200 +*N prog_clk[0]:450 *C 6.945 61.200 +*N prog_clk[0]:451 *C 6.900 61.200 +*N prog_clk[0]:452 *C 6.908 61.200 +*N prog_clk[0]:453 *C 13.793 61.200 +*N prog_clk[0]:454 *C 13.800 61.200 +*N prog_clk[0]:455 *C 12.685 66.640 +*N prog_clk[0]:456 *C 12.880 66.640 +*N prog_clk[0]:457 *C 12.880 66.640 +*N prog_clk[0]:458 *C 12.888 66.640 +*N prog_clk[0]:459 *C 13.793 66.640 +*N prog_clk[0]:460 *C 13.800 66.640 +*N prog_clk[0]:461 *C 13.800 72.023 +*N prog_clk[0]:462 *C 13.800 72.080 +*N prog_clk[0]:463 *C 29.433 72.080 +*N prog_clk[0]:464 *C 29.440 72.080 +*N prog_clk[0]:465 *C 29.900 72.080 +*N prog_clk[0]:466 *C 29.900 99.903 +*N prog_clk[0]:467 *C 29.908 99.960 + +*CAP +0 prog_clk[0] 2.396298e-05 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +2 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +5 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +7 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +8 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +9 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +12 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +13 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +14 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +15 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +16 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +17 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +18 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +19 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +20 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +21 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +22 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +23 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +24 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +25 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +27 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +28 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +29 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +31 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +32 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +33 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +37 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +38 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +39 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +40 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +41 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +42 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +43 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +44 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +46 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +47 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +49 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +50 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +51 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +52 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +53 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +54 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +55 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +57 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +58 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +59 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +60 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +61 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +63 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +64 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +65 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +66 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +67 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +68 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +69 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +70 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +71 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +72 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +73 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +74 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +75 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +76 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +77 prog_clk[0]:77 7.939269e-05 +78 prog_clk[0]:78 7.939269e-05 +79 prog_clk[0]:79 3.49861e-05 +80 prog_clk[0]:80 0.0002862102 +81 prog_clk[0]:81 5.73685e-05 +82 prog_clk[0]:82 6.207351e-05 +83 prog_clk[0]:83 0.0002241741 +84 prog_clk[0]:84 6.012936e-05 +85 prog_clk[0]:85 6.41966e-05 +86 prog_clk[0]:86 7.017021e-05 +87 prog_clk[0]:87 6.72938e-05 +88 prog_clk[0]:88 6.72938e-05 +89 prog_clk[0]:89 3.746511e-05 +90 prog_clk[0]:90 0.0003166201 +91 prog_clk[0]:91 0.0003682561 +92 prog_clk[0]:92 0.0001082862 +93 prog_clk[0]:93 0.0001082862 +94 prog_clk[0]:94 3.637434e-05 +95 prog_clk[0]:95 0.0001018923 +96 prog_clk[0]:96 6.929539e-05 +97 prog_clk[0]:97 6.760869e-05 +98 prog_clk[0]:98 0.0002509473 +99 prog_clk[0]:99 6.583514e-05 +100 prog_clk[0]:100 6.583514e-05 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chany_top_in[10]:6 9.894506e-05 +498 prog_clk[0]:324 chany_top_in[10]:7 1.369701e-05 +499 prog_clk[0]:319 chany_top_in[10]:8 1.369701e-05 +500 prog_clk[0]:248 chany_top_in[14]:10 3.882849e-05 +501 prog_clk[0]:464 chany_top_in[14]:6 3.280371e-06 +502 prog_clk[0]:249 chany_top_in[14]:9 3.882849e-05 +503 prog_clk[0]:466 chany_top_in[14]:8 7.457883e-05 +504 prog_clk[0]:167 chany_top_in[14]:14 3.085414e-05 +505 prog_clk[0]:167 chany_top_in[14]:15 4.876567e-05 +506 prog_clk[0]:167 chany_top_in[14]:16 1.551707e-06 +507 prog_clk[0]:398 chany_top_in[14]:5 4.069022e-07 +508 prog_clk[0]:397 chany_top_in[14]:4 4.069022e-07 +509 prog_clk[0]:171 chany_top_in[14]:14 4.876567e-05 +510 prog_clk[0]:171 chany_top_in[14]:15 6.504958e-05 +511 prog_clk[0]:151 chany_top_in[14]:17 2.612567e-07 +512 prog_clk[0]:156 chany_top_in[14]:17 1.551707e-06 +513 prog_clk[0]:156 chany_top_in[14]:15 3.085414e-05 +514 prog_clk[0]:156 chany_top_in[14]:16 2.612567e-07 +515 prog_clk[0]:465 chany_top_in[14]:7 7.785921e-05 +516 prog_clk[0]:172 chany_top_in[14]:14 6.504958e-05 +517 prog_clk[0]:382 chany_top_in[18]:6 0.000145638 +518 prog_clk[0]:381 chany_top_in[18]:5 0.000145638 +519 prog_clk[0]:119 chany_top_in[18]:8 1.234088e-05 +520 prog_clk[0]:191 chany_top_in[18]:5 0.0001052468 +521 prog_clk[0]:190 chany_top_in[18]:6 0.0001052468 +522 prog_clk[0]:393 chany_top_in[18]:5 6.306248e-07 +523 prog_clk[0]:388 chany_top_in[18]:6 6.306248e-07 +524 prog_clk[0]:91 chany_top_in[18]:9 1.234088e-05 +525 prog_clk[0]:136 top_left_grid_pin_34_[0]:27 0.0001280926 +526 prog_clk[0]:257 top_left_grid_pin_34_[0] 0.0001048581 +527 prog_clk[0]:142 top_left_grid_pin_34_[0]:28 0.0002027247 +528 prog_clk[0]:256 top_left_grid_pin_34_[0]:33 0.0001048581 +529 prog_clk[0]:141 top_left_grid_pin_34_[0]:27 0.0002027247 +530 prog_clk[0]:141 top_left_grid_pin_34_[0]:28 0.0001280926 +531 prog_clk[0]:247 top_left_grid_pin_37_[0]:20 4.576842e-05 +532 prog_clk[0]:250 top_left_grid_pin_37_[0]:25 3.707761e-05 +533 prog_clk[0]:466 top_left_grid_pin_37_[0]:26 5.741628e-05 +534 prog_clk[0]:257 top_left_grid_pin_37_[0]:26 9.808777e-05 +535 prog_clk[0]:238 top_left_grid_pin_37_[0]:19 4.135927e-06 +536 prog_clk[0]:242 top_left_grid_pin_37_[0]:19 2.362653e-05 +537 prog_clk[0]:253 top_left_grid_pin_37_[0]:25 7.730934e-05 +538 prog_clk[0]:253 top_left_grid_pin_37_[0]:26 3.707761e-05 +539 prog_clk[0]:256 top_left_grid_pin_37_[0]:25 9.808777e-05 +540 prog_clk[0]:256 top_left_grid_pin_37_[0]:26 7.730934e-05 +541 prog_clk[0]:231 top_left_grid_pin_37_[0]:15 7.921062e-07 +542 prog_clk[0]:387 top_left_grid_pin_37_[0]:19 2.631222e-06 +543 prog_clk[0]:386 top_left_grid_pin_37_[0]:20 2.631222e-06 +544 prog_clk[0]:234 top_left_grid_pin_37_[0]:16 7.921062e-07 +545 prog_clk[0]:465 top_left_grid_pin_37_[0]:25 5.741628e-05 +546 prog_clk[0]:243 top_left_grid_pin_37_[0]:20 2.362653e-05 +547 prog_clk[0]:244 top_left_grid_pin_37_[0]:20 4.135927e-06 +548 prog_clk[0]:244 top_left_grid_pin_37_[0]:19 4.576842e-05 +549 prog_clk[0]:212 top_left_grid_pin_38_[0]:18 5.719017e-06 +550 prog_clk[0]:212 top_left_grid_pin_38_[0]:17 1.161869e-05 +551 prog_clk[0]:247 top_left_grid_pin_38_[0]:25 5.252753e-08 +552 prog_clk[0]:467 top_left_grid_pin_38_[0] 2.930285e-05 +553 prog_clk[0]:258 top_left_grid_pin_38_[0]:26 2.930285e-05 +554 prog_clk[0]:166 top_left_grid_pin_38_[0]:25 2.402299e-06 +555 prog_clk[0]:167 top_left_grid_pin_38_[0]:26 7.829366e-05 +556 prog_clk[0]:165 top_left_grid_pin_38_[0]:24 2.402299e-06 +557 prog_clk[0]:183 top_left_grid_pin_38_[0]:17 5.719017e-06 +558 prog_clk[0]:216 top_left_grid_pin_38_[0]:18 1.161869e-05 +559 prog_clk[0]:216 top_left_grid_pin_38_[0]:17 2.857686e-07 +560 prog_clk[0]:221 top_left_grid_pin_38_[0]:18 2.857686e-07 +561 prog_clk[0]:176 top_left_grid_pin_38_[0] 1.268854e-05 +562 prog_clk[0]:171 top_left_grid_pin_38_[0] 7.829366e-05 +563 prog_clk[0]:171 top_left_grid_pin_38_[0]:26 0.0001810854 +564 prog_clk[0]:244 top_left_grid_pin_38_[0]:24 5.252753e-08 +565 prog_clk[0]:177 top_left_grid_pin_38_[0] 3.045248e-06 +566 prog_clk[0]:177 top_left_grid_pin_38_[0]:26 1.268854e-05 +567 prog_clk[0]:172 top_left_grid_pin_38_[0] 0.0001810854 +568 prog_clk[0]:172 top_left_grid_pin_38_[0]:26 3.045248e-06 +569 prog_clk[0]:378 chanx_left_in[0] 0.0002165177 +570 prog_clk[0]:378 chanx_left_in[0]:12 7.709018e-05 +571 prog_clk[0]:369 chanx_left_in[0]:10 5.962492e-05 +572 prog_clk[0]:369 chanx_left_in[0]:12 4.176427e-05 +573 prog_clk[0]:369 chanx_left_in[0]:11 0.0001094867 +574 prog_clk[0]:357 chanx_left_in[0]:11 6.300692e-05 +575 prog_clk[0]:373 chanx_left_in[0] 4.176427e-05 +576 prog_clk[0]:373 chanx_left_in[0]:12 0.0002165177 +577 prog_clk[0]:373 chanx_left_in[0]:11 5.962492e-05 +578 prog_clk[0]:324 chanx_left_in[0]:10 6.300692e-05 +579 prog_clk[0]:318 chanx_left_in[0]:10 3.7887e-05 +580 prog_clk[0]:377 chanx_left_in[0] 7.709018e-05 +581 prog_clk[0]:362 chanx_left_in[0]:10 0.0001094867 +582 prog_clk[0]:362 chanx_left_in[0]:11 5.30092e-05 +583 prog_clk[0]:358 chanx_left_in[0]:10 5.30092e-05 +584 prog_clk[0]:319 chanx_left_in[0]:11 3.7887e-05 +585 prog_clk[0]:236 chanx_left_in[1]:6 0.0003125882 +586 prog_clk[0]:237 chanx_left_in[1]:7 0.0003125882 +587 prog_clk[0]:431 chanx_left_in[6]:10 1.986018e-05 +588 prog_clk[0]:409 chanx_left_in[6]:11 1.986018e-05 +589 prog_clk[0]:453 chanx_left_in[6]:6 2.434451e-06 +590 prog_clk[0]:452 chanx_left_in[6]:7 2.434451e-06 +591 prog_clk[0]:464 chanx_left_in[6]:4 3.879863e-07 +592 prog_clk[0]:250 chanx_left_in[6]:5 0.0001026157 +593 prog_clk[0]:257 chanx_left_in[6]:4 2.178622e-05 +594 prog_clk[0]:394 chanx_left_in[6]:7 7.467841e-05 +595 prog_clk[0]:253 chanx_left_in[6]:4 0.0001026157 +596 prog_clk[0]:253 chanx_left_in[6]:5 6.988569e-05 +597 prog_clk[0]:256 chanx_left_in[6]:4 6.988569e-05 +598 prog_clk[0]:256 chanx_left_in[6]:5 2.178622e-05 +599 prog_clk[0]:392 chanx_left_in[6]:4 1.183691e-05 +600 prog_clk[0]:393 chanx_left_in[6]:6 7.467841e-05 +601 prog_clk[0]:391 chanx_left_in[6]:5 1.183691e-05 +602 prog_clk[0]:396 chanx_left_in[6]:5 3.879863e-07 +603 prog_clk[0]:307 chanx_left_in[8]:11 0.0001631309 +604 prog_clk[0]:307 chanx_left_in[8]:12 0.0003425555 +605 prog_clk[0]:143 chanx_left_in[8]:5 2.885163e-05 +606 prog_clk[0]:143 chanx_left_in[8]:3 2.213431e-05 +607 prog_clk[0]:297 chanx_left_in[8]:11 0.0003425555 +608 prog_clk[0]:83 chanx_left_in[8]:6 2.885163e-05 +609 prog_clk[0]:306 chanx_left_in[8]:12 0.0001631309 +610 prog_clk[0]:419 chanx_left_in[8]:16 7.97508e-06 +611 prog_clk[0]:420 chanx_left_in[8]:15 7.97508e-06 +612 prog_clk[0]:144 chanx_left_in[8]:4 2.213431e-05 +613 prog_clk[0]:212 chanx_left_in[10]:9 7.010862e-06 +614 prog_clk[0]:212 chanx_left_in[10]:8 3.891332e-05 +615 prog_clk[0]:464 chanx_left_in[10]:18 5.77234e-05 +616 prog_clk[0]:466 chanx_left_in[10]:14 0.0001851087 +617 prog_clk[0]:183 chanx_left_in[10]:8 7.010862e-06 +618 prog_clk[0]:216 chanx_left_in[10]:9 3.891332e-05 +619 prog_clk[0]:216 chanx_left_in[10]:8 1.985504e-05 +620 prog_clk[0]:221 chanx_left_in[10]:9 1.985504e-05 +621 prog_clk[0]:221 chanx_left_in[10]:8 3.298575e-06 +622 prog_clk[0]:225 chanx_left_in[10]:9 3.298575e-06 +623 prog_clk[0]:459 chanx_left_in[10]:20 6.904453e-05 +624 prog_clk[0]:458 chanx_left_in[10] 6.904453e-05 +625 prog_clk[0]:396 chanx_left_in[10]:19 5.77234e-05 +626 prog_clk[0]:465 chanx_left_in[10]:15 0.0001851087 +627 prog_clk[0]:463 left_top_grid_pin_44_[0]:17 0.0002469412 +628 prog_clk[0]:462 left_top_grid_pin_44_[0]:17 0.000370332 +629 prog_clk[0]:462 left_top_grid_pin_44_[0]:18 0.0002469412 +630 prog_clk[0]:402 left_top_grid_pin_44_[0]:18 0.000370332 +631 prog_clk[0]:438 left_top_grid_pin_44_[0]:14 3.162678e-06 +632 prog_clk[0]:439 left_top_grid_pin_44_[0]:15 3.162678e-06 +633 prog_clk[0]:383 left_top_grid_pin_49_[0]:15 2.412133e-05 +634 prog_clk[0]:463 left_top_grid_pin_49_[0]:24 0.0001369709 +635 prog_clk[0]:292 left_top_grid_pin_49_[0]:9 1.059139e-05 +636 prog_clk[0]:394 left_top_grid_pin_49_[0]:13 2.432337e-06 +637 prog_clk[0]:291 left_top_grid_pin_49_[0]:9 0.0002409329 +638 prog_clk[0]:291 left_top_grid_pin_49_[0]:8 1.059139e-05 +639 prog_clk[0]:462 left_top_grid_pin_49_[0]:24 0.0001861332 +640 prog_clk[0]:462 left_top_grid_pin_49_[0]:25 0.0001369709 +641 prog_clk[0]:402 left_top_grid_pin_49_[0]:25 0.0001861332 +642 prog_clk[0]:282 left_top_grid_pin_49_[0]:6 2.548962e-07 +643 prog_clk[0]:283 left_top_grid_pin_49_[0]:8 0.0002409329 +644 prog_clk[0]:281 left_top_grid_pin_49_[0]:7 2.548962e-07 +645 prog_clk[0]:261 left_top_grid_pin_49_[0]:14 2.412133e-05 +646 prog_clk[0]:393 left_top_grid_pin_49_[0]:12 2.432337e-06 +647 prog_clk[0]:393 left_top_grid_pin_49_[0]:13 5.411914e-07 +648 prog_clk[0]:388 left_top_grid_pin_49_[0]:12 5.411914e-07 +649 prog_clk[0]:108 chany_top_out[5] 4.519101e-05 +650 prog_clk[0]:121 chany_top_out[5]:2 5.970427e-05 +651 prog_clk[0]:135 chany_top_out[5] 9.099608e-05 +652 prog_clk[0]:135 chany_top_out[5]:2 1.896673e-05 +653 prog_clk[0]:131 chany_top_out[5] 0.0001133695 +654 prog_clk[0]:134 chany_top_out[5]:2 9.099608e-05 +655 prog_clk[0]:107 chany_top_out[5] 2.478155e-05 +656 prog_clk[0]:107 chany_top_out[5]:2 4.519101e-05 +657 prog_clk[0]:104 chany_top_out[5] 4.234297e-05 +658 prog_clk[0]:104 chany_top_out[5]:2 2.478155e-05 +659 prog_clk[0]:86 chany_top_out[5] 1.896673e-05 +660 prog_clk[0]:98 chany_top_out[5]:2 4.234297e-05 +661 prog_clk[0]:128 chany_top_out[5] 5.970427e-05 +662 prog_clk[0]:128 chany_top_out[5]:2 0.0001133695 +663 prog_clk[0]:125 chany_top_out[5]:2 2.11992e-05 +664 prog_clk[0]:124 chany_top_out[5] 2.11992e-05 +665 prog_clk[0]:333 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 3.586542e-05 +666 prog_clk[0]:327 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 3.586542e-05 +667 prog_clk[0]:337 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 1.362626e-05 +668 prog_clk[0]:334 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 1.362626e-05 +669 prog_clk[0]:103 mux_tree_tapbuf_size5_1_sram[0]:16 0.0001426411 +670 prog_clk[0]:102 mux_tree_tapbuf_size5_1_sram[0]:17 0.0001426411 +671 prog_clk[0]:191 mux_tree_tapbuf_size5_1_sram[0]:16 0.0001139081 +672 prog_clk[0]:190 mux_tree_tapbuf_size5_1_sram[0]:17 0.0001139081 +673 prog_clk[0]:360 mux_tree_tapbuf_size5_1_sram[0]:5 1.254567e-05 +674 prog_clk[0]:359 mux_tree_tapbuf_size5_1_sram[0]:4 1.254567e-05 +675 prog_clk[0]:431 mux_tree_tapbuf_size6_2_sram[0]:22 5.889951e-05 +676 prog_clk[0]:378 mux_tree_tapbuf_size6_2_sram[0]:22 0.0002139483 +677 prog_clk[0]:378 mux_tree_tapbuf_size6_2_sram[0]:23 7.659566e-05 +678 prog_clk[0]:433 mux_tree_tapbuf_size6_2_sram[0]:20 2.517451e-06 +679 prog_clk[0]:433 mux_tree_tapbuf_size6_2_sram[0]:21 7.581967e-07 +680 prog_clk[0]:432 mux_tree_tapbuf_size6_2_sram[0]:23 5.889951e-05 +681 prog_clk[0]:373 mux_tree_tapbuf_size6_2_sram[0]:23 0.0002139483 +682 prog_clk[0]:313 mux_tree_tapbuf_size6_2_sram[0]:22 7.040244e-05 +683 prog_clk[0]:312 mux_tree_tapbuf_size6_2_sram[0]:23 7.040244e-05 +684 prog_clk[0]:377 mux_tree_tapbuf_size6_2_sram[0]:22 7.659566e-05 +685 prog_clk[0]:434 mux_tree_tapbuf_size6_2_sram[0]:8 7.581967e-07 +686 prog_clk[0]:434 mux_tree_tapbuf_size6_2_sram[0]:21 2.517451e-06 +687 prog_clk[0]:379 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 5.658033e-05 +688 prog_clk[0]:308 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 5.602902e-05 +689 prog_clk[0]:314 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:5 5.602902e-05 +690 prog_clk[0]:314 mux_tree_tapbuf_size6_mem_3_ccff_tail[0]:6 5.658033e-05 +691 prog_clk[0]:307 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.201844e-05 +692 prog_clk[0]:307 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000141487 +693 prog_clk[0]:297 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000141487 +694 prog_clk[0]:301 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.437781e-05 +695 prog_clk[0]:306 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 3.437781e-05 +696 prog_clk[0]:306 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.201844e-05 +697 prog_clk[0]:427 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.722756e-05 +698 prog_clk[0]:424 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.722756e-05 +699 prog_clk[0]:426 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.920854e-07 +700 prog_clk[0]:425 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.920854e-07 +701 prog_clk[0]:211 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001535288 +702 prog_clk[0]:203 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.984964e-05 +703 prog_clk[0]:210 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001535288 +704 prog_clk[0]:186 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.385338e-05 +705 prog_clk[0]:196 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.567334e-05 +706 prog_clk[0]:196 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.355569e-05 +707 prog_clk[0]:192 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.355569e-05 +708 prog_clk[0]:192 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.385338e-05 +709 prog_clk[0]:323 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.092425e-07 +710 prog_clk[0]:322 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.092425e-07 +711 prog_clk[0]:197 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.567334e-05 +712 prog_clk[0]:204 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.984964e-05 +713 prog_clk[0]:166 optlc_net_108:35 8.374578e-05 +714 prog_clk[0]:143 optlc_net_108:26 4.500589e-05 +715 prog_clk[0]:202 optlc_net_108:55 9.707629e-06 +716 prog_clk[0]:201 optlc_net_108:50 9.707629e-06 +717 prog_clk[0]:165 optlc_net_108:35 7.304313e-05 +718 prog_clk[0]:165 optlc_net_108:39 8.374578e-05 +719 prog_clk[0]:209 optlc_net_108:55 6.680021e-05 +720 prog_clk[0]:208 optlc_net_108:50 6.680021e-05 +721 prog_clk[0]:155 optlc_net_108:29 2.803549e-07 +722 prog_clk[0]:154 optlc_net_108:30 2.803549e-07 +723 prog_clk[0]:159 optlc_net_108:39 7.304313e-05 +724 prog_clk[0]:144 optlc_net_108:28 4.500589e-05 +725 prog_clk[0]:464 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.332075e-05 +726 prog_clk[0]:396 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.332075e-05 +727 prog_clk[0]:383 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.287466e-07 +728 prog_clk[0]:383 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.084314e-07 +729 prog_clk[0]:380 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.859179e-05 +730 prog_clk[0]:380 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 1.455961e-05 +731 prog_clk[0]:379 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.859179e-05 +732 prog_clk[0]:379 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.455961e-05 +733 prog_clk[0]:464 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.417017e-07 +734 prog_clk[0]:395 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.287466e-07 +735 prog_clk[0]:395 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 2.084314e-07 +736 prog_clk[0]:396 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.417017e-07 +737 prog_clk[0]:155 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.981079e-05 +738 prog_clk[0]:154 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.981079e-05 +739 prog_clk[0]:155 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.94654e-05 +740 prog_clk[0]:154 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.94654e-05 +741 prog_clk[0]:155 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.110484e-05 +742 prog_clk[0]:154 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.110484e-05 +743 prog_clk[0]:136 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.476693e-05 +744 prog_clk[0]:146 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.885187e-06 +745 prog_clk[0]:146 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.196062e-06 +746 prog_clk[0]:167 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.864439e-05 +747 prog_clk[0]:142 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.48371e-05 +748 prog_clk[0]:80 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.885187e-06 +749 prog_clk[0]:164 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.062189e-05 +750 prog_clk[0]:163 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.062189e-05 +751 prog_clk[0]:151 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.196062e-06 +752 prog_clk[0]:151 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.337581e-05 +753 prog_clk[0]:141 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.476693e-05 +754 prog_clk[0]:141 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.48371e-05 +755 prog_clk[0]:156 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.337581e-05 +756 prog_clk[0]:156 mux_top_track_28/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.864439e-05 +757 prog_clk[0]:292 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000163893 +758 prog_clk[0]:291 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.000163893 +759 prog_clk[0]:414 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.512033e-08 +760 prog_clk[0]:415 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.512033e-08 +761 prog_clk[0]:424 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.870468e-07 +762 prog_clk[0]:421 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.076419e-05 +763 prog_clk[0]:422 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.076419e-05 +764 prog_clk[0]:418 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 1.302199e-07 +765 prog_clk[0]:419 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 1.302199e-07 +766 prog_clk[0]:419 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.425043e-05 +767 prog_clk[0]:420 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.870468e-07 +768 prog_clk[0]:420 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.425043e-05 + +*RES +0 prog_clk[0] prog_clk[0]:467 2.35e-05 +1 prog_clk[0]:445 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +2 prog_clk[0]:447 prog_clk[0]:446 0.0003035715 +3 prog_clk[0]:448 prog_clk[0]:447 0.0045 +4 prog_clk[0]:108 prog_clk[0]:107 0.004805804 +5 prog_clk[0]:109 prog_clk[0]:108 0.00341 +6 prog_clk[0]:262 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +7 prog_clk[0]:263 prog_clk[0]:262 0.0045 +8 prog_clk[0]:265 prog_clk[0]:264 0.0045 +9 prog_clk[0]:264 prog_clk[0]:263 0.0005267857 +10 prog_clk[0]:267 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +11 prog_clk[0]:284 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +12 prog_clk[0]:285 prog_clk[0]:284 0.0005245536 +13 prog_clk[0]:286 prog_clk[0]:285 0.0045 +14 prog_clk[0]:277 prog_clk[0]:276 0.001122768 +15 prog_clk[0]:278 prog_clk[0]:277 0.00341 +16 prog_clk[0]:275 prog_clk[0]:274 0.0005736608 +17 prog_clk[0]:276 prog_clk[0]:275 0.0045 +18 prog_clk[0]:274 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +19 prog_clk[0]:427 prog_clk[0]:426 0.0045 +20 prog_clk[0]:427 prog_clk[0]:424 0.005160715 +21 prog_clk[0]:428 prog_clk[0]:427 0.00341 +22 prog_clk[0]:428 prog_clk[0]:410 5.69697e-05 +23 prog_clk[0]:429 prog_clk[0]:428 0.00341 +24 prog_clk[0]:431 prog_clk[0]:430 0.00341 +25 prog_clk[0]:431 prog_clk[0]:409 0.001296025 +26 prog_clk[0]:430 prog_clk[0]:429 0.00127605 +27 prog_clk[0]:121 prog_clk[0]:120 0.00341 +28 prog_clk[0]:120 prog_clk[0]:119 0.000431225 +29 prog_clk[0]:211 prog_clk[0]:210 0.007183036 +30 prog_clk[0]:212 prog_clk[0]:211 0.00341 +31 prog_clk[0]:212 prog_clk[0]:183 0.0002870917 +32 prog_clk[0]:408 prog_clk[0]:407 0.0045 +33 prog_clk[0]:408 prog_clk[0]:405 0.002388393 +34 prog_clk[0]:409 prog_clk[0]:408 0.00341 +35 prog_clk[0]:454 prog_clk[0]:453 0.00341 +36 prog_clk[0]:454 prog_clk[0]:444 0.0045 +37 prog_clk[0]:454 prog_clk[0]:439 0.0004107143 +38 prog_clk[0]:453 prog_clk[0]:452 0.00107865 +39 prog_clk[0]:451 prog_clk[0]:450 0.0045 +40 prog_clk[0]:451 prog_clk[0]:448 0.005120536 +41 prog_clk[0]:452 prog_clk[0]:451 0.00341 +42 prog_clk[0]:383 prog_clk[0]:382 0.00341 +43 prog_clk[0]:383 prog_clk[0]:261 0.0004107143 +44 prog_clk[0]:382 prog_clk[0]:381 0.0003579833 +45 prog_clk[0]:380 prog_clk[0]:379 0.004805803 +46 prog_clk[0]:381 prog_clk[0]:380 0.00341 +47 prog_clk[0]:379 prog_clk[0]:378 0.00341 +48 prog_clk[0]:379 prog_clk[0]:314 0.002428571 +49 prog_clk[0]:378 prog_clk[0]:377 0.0005032916 +50 prog_clk[0]:378 prog_clk[0]:373 0.0015134 +51 prog_clk[0]:247 prog_clk[0]:246 0.0045 +52 prog_clk[0]:247 prog_clk[0]:244 0.006375 +53 prog_clk[0]:248 prog_clk[0]:247 0.00341 +54 prog_clk[0]:248 prog_clk[0]:225 0.001441333 +55 prog_clk[0]:135 prog_clk[0]:134 0.00602009 +56 prog_clk[0]:135 prog_clk[0]:86 0.001174107 +57 prog_clk[0]:136 prog_clk[0]:135 0.00341 +58 prog_clk[0]:308 prog_clk[0]:307 0.00341 +59 prog_clk[0]:308 prog_clk[0]:293 0.0085 +60 prog_clk[0]:307 prog_clk[0]:306 0.0005044666 +61 prog_clk[0]:307 prog_clk[0]:297 0.0009356916 +62 prog_clk[0]:368 prog_clk[0]:367 0.0045 +63 prog_clk[0]:368 prog_clk[0]:365 0.004816964 +64 prog_clk[0]:369 prog_clk[0]:368 0.00341 +65 prog_clk[0]:369 prog_clk[0]:362 0.0012972 +66 prog_clk[0]:145 prog_clk[0]:144 0.00602009 +67 prog_clk[0]:146 prog_clk[0]:145 0.00341 +68 prog_clk[0]:146 prog_clk[0]:80 0.0009356916 +69 prog_clk[0]:131 prog_clk[0]:130 0.0045 +70 prog_clk[0]:131 prog_clk[0]:128 0.003642857 +71 prog_clk[0]:132 prog_clk[0]:131 0.00341 +72 prog_clk[0]:134 prog_clk[0]:133 0.00341 +73 prog_clk[0]:133 prog_clk[0]:132 0.00021385 +74 prog_clk[0]:464 prog_clk[0]:463 0.00341 +75 prog_clk[0]:464 prog_clk[0]:398 0.0045 +76 prog_clk[0]:464 prog_clk[0]:396 0.01092857 +77 prog_clk[0]:463 prog_clk[0]:462 0.002449092 +78 prog_clk[0]:250 prog_clk[0]:249 0.00341 +79 prog_clk[0]:250 prog_clk[0]:179 0.0045 +80 prog_clk[0]:249 prog_clk[0]:248 0.001223958 +81 prog_clk[0]:293 prog_clk[0]:292 0.00341 +82 prog_clk[0]:293 prog_clk[0]:273 0.001214286 +83 prog_clk[0]:292 prog_clk[0]:291 0.001296025 +84 prog_clk[0]:111 prog_clk[0]:110 0.00341 +85 prog_clk[0]:110 prog_clk[0]:109 0.0002870917 +86 prog_clk[0]:110 prog_clk[0]:95 0.000215025 +87 prog_clk[0]:466 prog_clk[0]:465 0.02484152 +88 prog_clk[0]:467 prog_clk[0]:466 0.00341 +89 prog_clk[0]:467 prog_clk[0]:258 0.0003591583 +90 prog_clk[0]:106 prog_clk[0]:105 0.001395089 +91 prog_clk[0]:107 prog_clk[0]:106 0.0045 +92 prog_clk[0]:107 prog_clk[0]:104 0.004857143 +93 prog_clk[0]:105 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +94 prog_clk[0]:118 prog_clk[0]:117 0.001770089 +95 prog_clk[0]:119 prog_clk[0]:118 0.00341 +96 prog_clk[0]:119 prog_clk[0]:91 0.0001053583 +97 prog_clk[0]:257 prog_clk[0]:256 0.007537947 +98 prog_clk[0]:258 prog_clk[0]:257 0.00341 +99 prog_clk[0]:258 prog_clk[0]:177 0.0001034 +100 prog_clk[0]:166 prog_clk[0]:165 0.004805804 +101 prog_clk[0]:167 prog_clk[0]:166 0.00341 +102 prog_clk[0]:167 prog_clk[0]:156 0.001369267 +103 prog_clk[0]:143 prog_clk[0]:142 0.00341 +104 prog_clk[0]:143 prog_clk[0]:83 0.003551339 +105 prog_clk[0]:142 prog_clk[0]:141 0.001584292 +106 prog_clk[0]:395 prog_clk[0]:394 0.00341 +107 prog_clk[0]:395 prog_clk[0]:383 0.003591518 +108 prog_clk[0]:394 prog_clk[0]:393 0.0007194916 +109 prog_clk[0]:290 prog_clk[0]:289 0.003895089 +110 prog_clk[0]:291 prog_clk[0]:290 0.00341 +111 prog_clk[0]:291 prog_clk[0]:283 0.001225133 +112 prog_clk[0]:461 prog_clk[0]:460 0.004805804 +113 prog_clk[0]:462 prog_clk[0]:461 0.00341 +114 prog_clk[0]:462 prog_clk[0]:402 0.001007758 +115 prog_clk[0]:104 prog_clk[0]:103 0.00341 +116 prog_clk[0]:104 prog_clk[0]:98 0.004816964 +117 prog_clk[0]:103 prog_clk[0]:102 0.0003579833 +118 prog_clk[0]:101 prog_clk[0]:100 0.0045 +119 prog_clk[0]:102 prog_clk[0]:101 0.00341 +120 prog_clk[0]:100 prog_clk[0]:99 0.0005736608 +121 prog_clk[0]:99 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +122 prog_clk[0]:227 prog_clk[0]:226 0.0001440218 +123 prog_clk[0]:228 prog_clk[0]:227 0.0045 +124 prog_clk[0]:226 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +125 prog_clk[0]:433 prog_clk[0]:432 0.00341 +126 prog_clk[0]:432 prog_clk[0]:431 0.0004312249 +127 prog_clk[0]:367 prog_clk[0]:366 0.0001059783 +128 prog_clk[0]:366 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +129 prog_clk[0]:352 prog_clk[0]:351 0.00341 +130 prog_clk[0]:352 prog_clk[0]:337 0.004553571 +131 prog_clk[0]:351 prog_clk[0]:350 0.000863625 +132 prog_clk[0]:235 prog_clk[0]:234 0.002125 +133 prog_clk[0]:235 prog_clk[0]:228 0.0008214285 +134 prog_clk[0]:236 prog_clk[0]:235 0.00341 +135 prog_clk[0]:238 prog_clk[0]:237 0.00341 +136 prog_clk[0]:237 prog_clk[0]:236 0.00086245 +137 prog_clk[0]:345 prog_clk[0]:344 0.002377232 +138 prog_clk[0]:346 prog_clk[0]:345 0.00341 +139 prog_clk[0]:411 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +140 prog_clk[0]:412 prog_clk[0]:411 9.510871e-05 +141 prog_clk[0]:413 prog_clk[0]:412 0.0045 +142 prog_clk[0]:414 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +143 prog_clk[0]:415 prog_clk[0]:414 0.0001847826 +144 prog_clk[0]:416 prog_clk[0]:415 0.0045 +145 prog_clk[0]:404 prog_clk[0]:403 0.0001440218 +146 prog_clk[0]:405 prog_clk[0]:404 0.0045 +147 prog_clk[0]:403 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +148 prog_clk[0]:407 prog_clk[0]:406 0.0001440218 +149 prog_clk[0]:406 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +150 prog_clk[0]:450 prog_clk[0]:449 0.0005736608 +151 prog_clk[0]:449 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +152 prog_clk[0]:401 prog_clk[0]:400 0.0045 +153 prog_clk[0]:402 prog_clk[0]:401 0.00341 +154 prog_clk[0]:400 prog_clk[0]:399 0.0001059783 +155 prog_clk[0]:399 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +156 prog_clk[0]:356 prog_clk[0]:355 0.004502233 +157 prog_clk[0]:357 prog_clk[0]:356 0.00341 +158 prog_clk[0]:357 prog_clk[0]:324 0.0012972 +159 prog_clk[0]:398 prog_clk[0]:397 0.0001059783 +160 prog_clk[0]:397 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +161 prog_clk[0]:282 prog_clk[0]:281 0.001122768 +162 prog_clk[0]:283 prog_clk[0]:282 0.00341 +163 prog_clk[0]:283 prog_clk[0]:278 0.0004312249 +164 prog_clk[0]:280 prog_clk[0]:279 0.0001440218 +165 prog_clk[0]:281 prog_clk[0]:280 0.0045 +166 prog_clk[0]:279 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +167 prog_clk[0]:241 prog_clk[0]:240 0.0003705357 +168 prog_clk[0]:242 prog_clk[0]:241 0.0045 +169 prog_clk[0]:239 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +170 prog_clk[0]:296 prog_clk[0]:295 0.0045 +171 prog_clk[0]:297 prog_clk[0]:296 0.00341 +172 prog_clk[0]:295 prog_clk[0]:294 0.0001440218 +173 prog_clk[0]:294 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +174 prog_clk[0]:372 prog_clk[0]:371 0.0045 +175 prog_clk[0]:373 prog_clk[0]:372 0.00341 +176 prog_clk[0]:373 prog_clk[0]:369 0.001441333 +177 prog_clk[0]:371 prog_clk[0]:370 0.0001440218 +178 prog_clk[0]:370 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +179 prog_clk[0]:314 prog_clk[0]:313 0.00341 +180 prog_clk[0]:314 prog_clk[0]:308 0.004857143 +181 prog_clk[0]:313 prog_clk[0]:312 0.00043005 +182 prog_clk[0]:311 prog_clk[0]:310 0.0045 +183 prog_clk[0]:312 prog_clk[0]:311 0.00341 +184 prog_clk[0]:310 prog_clk[0]:309 0.0001440217 +185 prog_clk[0]:309 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +186 prog_clk[0]:203 prog_clk[0]:202 0.00341 +187 prog_clk[0]:203 prog_clk[0]:197 0.0004107143 +188 prog_clk[0]:202 prog_clk[0]:201 0.0003579833 +189 prog_clk[0]:200 prog_clk[0]:199 0.0045 +190 prog_clk[0]:201 prog_clk[0]:200 0.00341 +191 prog_clk[0]:199 prog_clk[0]:198 0.0001440218 +192 prog_clk[0]:198 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +193 prog_clk[0]:79 prog_clk[0]:78 0.0045 +194 prog_clk[0]:80 prog_clk[0]:79 0.00341 +195 prog_clk[0]:78 prog_clk[0]:77 0.0005736608 +196 prog_clk[0]:77 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +197 prog_clk[0]:165 prog_clk[0]:164 0.00341 +198 prog_clk[0]:165 prog_clk[0]:159 0.002388393 +199 prog_clk[0]:164 prog_clk[0]:163 0.00021385 +200 prog_clk[0]:162 prog_clk[0]:161 0.0045 +201 prog_clk[0]:163 prog_clk[0]:162 0.00341 +202 prog_clk[0]:161 prog_clk[0]:160 0.0005736608 +203 prog_clk[0]:160 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +204 prog_clk[0]:210 prog_clk[0]:209 0.00341 +205 prog_clk[0]:210 prog_clk[0]:204 0.0004107143 +206 prog_clk[0]:209 prog_clk[0]:208 0.0001417833 +207 prog_clk[0]:207 prog_clk[0]:206 0.0045 +208 prog_clk[0]:208 prog_clk[0]:207 0.00341 +209 prog_clk[0]:206 prog_clk[0]:205 0.0005736608 +210 prog_clk[0]:205 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +211 prog_clk[0]:85 prog_clk[0]:84 0.0001059783 +212 prog_clk[0]:86 prog_clk[0]:85 0.0045 +213 prog_clk[0]:84 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +214 prog_clk[0]:185 prog_clk[0]:184 0.0001059783 +215 prog_clk[0]:186 prog_clk[0]:185 0.0045 +216 prog_clk[0]:184 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +217 prog_clk[0]:97 prog_clk[0]:96 0.0001059783 +218 prog_clk[0]:98 prog_clk[0]:97 0.0045 +219 prog_clk[0]:96 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +220 prog_clk[0]:182 prog_clk[0]:181 0.0045 +221 prog_clk[0]:183 prog_clk[0]:182 0.00341 +222 prog_clk[0]:181 prog_clk[0]:180 0.0005736608 +223 prog_clk[0]:180 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +224 prog_clk[0]:339 prog_clk[0]:338 0.0001440218 +225 prog_clk[0]:340 prog_clk[0]:339 0.0045 +226 prog_clk[0]:338 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +227 prog_clk[0]:195 prog_clk[0]:194 0.0003705357 +228 prog_clk[0]:196 prog_clk[0]:195 0.0045 +229 prog_clk[0]:196 prog_clk[0]:192 0.002125 +230 prog_clk[0]:193 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +231 prog_clk[0]:192 prog_clk[0]:191 0.00341 +232 prog_clk[0]:192 prog_clk[0]:186 0.002388393 +233 prog_clk[0]:191 prog_clk[0]:190 0.001583117 +234 prog_clk[0]:189 prog_clk[0]:188 0.0045 +235 prog_clk[0]:190 prog_clk[0]:189 0.00341 +236 prog_clk[0]:188 prog_clk[0]:187 0.0001440218 +237 prog_clk[0]:187 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +238 prog_clk[0]:333 prog_clk[0]:332 0.00341 +239 prog_clk[0]:333 prog_clk[0]:327 0.002337054 +240 prog_clk[0]:332 prog_clk[0]:331 0.001222783 +241 prog_clk[0]:330 prog_clk[0]:329 0.0045 +242 prog_clk[0]:331 prog_clk[0]:330 0.00341 +243 prog_clk[0]:329 prog_clk[0]:328 0.0001440218 +244 prog_clk[0]:328 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +245 prog_clk[0]:215 prog_clk[0]:214 0.0045 +246 prog_clk[0]:216 prog_clk[0]:215 0.00341 +247 prog_clk[0]:216 prog_clk[0]:212 0.0009368665 +248 prog_clk[0]:214 prog_clk[0]:213 0.0001059783 +249 prog_clk[0]:213 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +250 prog_clk[0]:323 prog_clk[0]:322 0.001729911 +251 prog_clk[0]:324 prog_clk[0]:323 0.00341 +252 prog_clk[0]:324 prog_clk[0]:319 0.0001053583 +253 prog_clk[0]:321 prog_clk[0]:320 0.0001440218 +254 prog_clk[0]:322 prog_clk[0]:321 0.0045 +255 prog_clk[0]:320 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +256 prog_clk[0]:317 prog_clk[0]:316 0.0045 +257 prog_clk[0]:318 prog_clk[0]:317 0.00341 +258 prog_clk[0]:316 prog_clk[0]:315 0.0005736608 +259 prog_clk[0]:315 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +260 prog_clk[0]:326 prog_clk[0]:325 0.0001440218 +261 prog_clk[0]:327 prog_clk[0]:326 0.0045 +262 prog_clk[0]:325 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +263 prog_clk[0]:220 prog_clk[0]:219 0.002337053 +264 prog_clk[0]:221 prog_clk[0]:220 0.00341 +265 prog_clk[0]:221 prog_clk[0]:216 0.0005765333 +266 prog_clk[0]:218 prog_clk[0]:217 0.0001059783 +267 prog_clk[0]:219 prog_clk[0]:218 0.0045 +268 prog_clk[0]:217 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +269 prog_clk[0]:94 prog_clk[0]:93 0.0045 +270 prog_clk[0]:95 prog_clk[0]:94 0.00341 +271 prog_clk[0]:93 prog_clk[0]:92 0.000984375 +272 prog_clk[0]:92 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +273 prog_clk[0]:336 prog_clk[0]:335 0.0001847826 +274 prog_clk[0]:337 prog_clk[0]:336 0.0045 +275 prog_clk[0]:337 prog_clk[0]:334 0.005160714 +276 prog_clk[0]:335 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +277 prog_clk[0]:224 prog_clk[0]:223 0.0045 +278 prog_clk[0]:225 prog_clk[0]:224 0.00341 +279 prog_clk[0]:225 prog_clk[0]:221 0.0008647999 +280 prog_clk[0]:223 prog_clk[0]:222 0.0001114131 +281 prog_clk[0]:222 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +282 prog_clk[0]:117 prog_clk[0]:116 0.00341 +283 prog_clk[0]:117 prog_clk[0]:111 0.004805804 +284 prog_clk[0]:116 prog_clk[0]:115 0.00021385 +285 prog_clk[0]:114 prog_clk[0]:113 0.0045 +286 prog_clk[0]:115 prog_clk[0]:114 0.00341 +287 prog_clk[0]:113 prog_clk[0]:112 0.000984375 +288 prog_clk[0]:112 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +289 prog_clk[0]:342 prog_clk[0]:341 0.0001059783 +290 prog_clk[0]:343 prog_clk[0]:342 0.0045 +291 prog_clk[0]:341 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +292 prog_clk[0]:246 prog_clk[0]:245 0.0005736608 +293 prog_clk[0]:245 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +294 prog_clk[0]:89 prog_clk[0]:88 0.0045 +295 prog_clk[0]:90 prog_clk[0]:89 0.00341 +296 prog_clk[0]:88 prog_clk[0]:87 0.0005736608 +297 prog_clk[0]:87 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +298 prog_clk[0]:179 prog_clk[0]:178 0.0001059783 +299 prog_clk[0]:178 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +300 prog_clk[0]:252 prog_clk[0]:251 0.0001847826 +301 prog_clk[0]:253 prog_clk[0]:252 0.0045 +302 prog_clk[0]:253 prog_clk[0]:250 0.007589286 +303 prog_clk[0]:251 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +304 prog_clk[0]:255 prog_clk[0]:254 0.0001847826 +305 prog_clk[0]:256 prog_clk[0]:255 0.0045 +306 prog_clk[0]:256 prog_clk[0]:253 0.004857143 +307 prog_clk[0]:254 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +308 prog_clk[0]:175 prog_clk[0]:174 0.0045 +309 prog_clk[0]:176 prog_clk[0]:175 0.00341 +310 prog_clk[0]:174 prog_clk[0]:173 0.0001059783 +311 prog_clk[0]:173 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +312 prog_clk[0]:170 prog_clk[0]:169 0.0045 +313 prog_clk[0]:171 prog_clk[0]:170 0.00341 +314 prog_clk[0]:171 prog_clk[0]:167 0.0009368666 +315 prog_clk[0]:169 prog_clk[0]:168 0.0001440218 +316 prog_clk[0]:168 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +317 prog_clk[0]:150 prog_clk[0]:149 0.002337054 +318 prog_clk[0]:151 prog_clk[0]:150 0.00341 +319 prog_clk[0]:151 prog_clk[0]:146 0.0002162 +320 prog_clk[0]:148 prog_clk[0]:147 9.51087e-05 +321 prog_clk[0]:149 prog_clk[0]:148 0.0045 +322 prog_clk[0]:147 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +323 prog_clk[0]:130 prog_clk[0]:129 0.0001195652 +324 prog_clk[0]:129 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +325 prog_clk[0]:128 prog_clk[0]:127 0.00341 +326 prog_clk[0]:128 prog_clk[0]:121 0.001770089 +327 prog_clk[0]:127 prog_clk[0]:126 0.00021385 +328 prog_clk[0]:125 prog_clk[0]:124 0.001122768 +329 prog_clk[0]:126 prog_clk[0]:125 0.00341 +330 prog_clk[0]:123 prog_clk[0]:122 0.0001548913 +331 prog_clk[0]:124 prog_clk[0]:123 0.0045 +332 prog_clk[0]:122 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +333 prog_clk[0]:140 prog_clk[0]:139 0.005979911 +334 prog_clk[0]:141 prog_clk[0]:140 0.00341 +335 prog_clk[0]:141 prog_clk[0]:136 0.001440158 +336 prog_clk[0]:138 prog_clk[0]:137 0.0001059783 +337 prog_clk[0]:139 prog_clk[0]:138 0.0045 +338 prog_clk[0]:137 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +339 prog_clk[0]:82 prog_clk[0]:81 0.0001059783 +340 prog_clk[0]:83 prog_clk[0]:82 0.0045 +341 prog_clk[0]:81 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +342 prog_clk[0]:260 prog_clk[0]:259 0.0005736608 +343 prog_clk[0]:261 prog_clk[0]:260 0.0045 +344 prog_clk[0]:259 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +345 prog_clk[0]:155 prog_clk[0]:154 0.009622768 +346 prog_clk[0]:156 prog_clk[0]:155 0.00341 +347 prog_clk[0]:156 prog_clk[0]:151 0.0009368666 +348 prog_clk[0]:153 prog_clk[0]:152 0.0001059783 +349 prog_clk[0]:154 prog_clk[0]:153 0.0045 +350 prog_clk[0]:152 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +351 prog_clk[0]:392 prog_clk[0]:391 0.001122768 +352 prog_clk[0]:393 prog_clk[0]:392 0.00341 +353 prog_clk[0]:393 prog_clk[0]:388 0.0002870917 +354 prog_clk[0]:390 prog_clk[0]:389 0.0001059783 +355 prog_clk[0]:391 prog_clk[0]:390 0.0045 +356 prog_clk[0]:389 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +357 prog_clk[0]:376 prog_clk[0]:375 0.0045 +358 prog_clk[0]:377 prog_clk[0]:376 0.00341 +359 prog_clk[0]:375 prog_clk[0]:374 0.0001059783 +360 prog_clk[0]:374 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +361 prog_clk[0]:158 prog_clk[0]:157 0.0001059783 +362 prog_clk[0]:159 prog_clk[0]:158 0.0045 +363 prog_clk[0]:157 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +364 prog_clk[0]:444 prog_clk[0]:443 0.0003035715 +365 prog_clk[0]:440 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +366 prog_clk[0]:288 prog_clk[0]:287 0.0001847826 +367 prog_clk[0]:289 prog_clk[0]:288 0.0045 +368 prog_clk[0]:289 prog_clk[0]:286 0.002084821 +369 prog_clk[0]:287 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +370 prog_clk[0]:460 prog_clk[0]:459 0.00341 +371 prog_clk[0]:460 prog_clk[0]:454 0.004857143 +372 prog_clk[0]:459 prog_clk[0]:458 0.0001417833 +373 prog_clk[0]:457 prog_clk[0]:456 0.0045 +374 prog_clk[0]:458 prog_clk[0]:457 0.00341 +375 prog_clk[0]:456 prog_clk[0]:455 0.0001059783 +376 prog_clk[0]:455 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +377 prog_clk[0]:230 prog_clk[0]:229 0.0001059783 +378 prog_clk[0]:231 prog_clk[0]:230 0.0045 +379 prog_clk[0]:229 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +380 prog_clk[0]:300 prog_clk[0]:299 0.0045 +381 prog_clk[0]:301 prog_clk[0]:300 0.00341 +382 prog_clk[0]:299 prog_clk[0]:298 0.0001440218 +383 prog_clk[0]:298 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +384 prog_clk[0]:423 prog_clk[0]:422 0.0003035715 +385 prog_clk[0]:424 prog_clk[0]:423 0.0045 +386 prog_clk[0]:424 prog_clk[0]:420 0.002125 +387 prog_clk[0]:421 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +388 prog_clk[0]:305 prog_clk[0]:304 0.002337054 +389 prog_clk[0]:306 prog_clk[0]:305 0.00341 +390 prog_clk[0]:306 prog_clk[0]:301 0.000215025 +391 prog_clk[0]:303 prog_clk[0]:302 0.0001059783 +392 prog_clk[0]:304 prog_clk[0]:303 0.0045 +393 prog_clk[0]:302 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +394 prog_clk[0]:268 prog_clk[0]:267 0.0001195652 +395 prog_clk[0]:268 prog_clk[0]:266 0.0006071429 +396 prog_clk[0]:269 prog_clk[0]:268 0.0045 +397 prog_clk[0]:387 prog_clk[0]:386 0.001122768 +398 prog_clk[0]:388 prog_clk[0]:387 0.00341 +399 prog_clk[0]:385 prog_clk[0]:384 0.001395089 +400 prog_clk[0]:386 prog_clk[0]:385 0.0045 +401 prog_clk[0]:384 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +402 prog_clk[0]:437 prog_clk[0]:436 0.0003035715 +403 prog_clk[0]:438 prog_clk[0]:437 0.0045 +404 prog_clk[0]:438 prog_clk[0]:434 0.0004107143 +405 prog_clk[0]:435 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +406 prog_clk[0]:354 prog_clk[0]:353 0.0001847826 +407 prog_clk[0]:355 prog_clk[0]:354 0.0045 +408 prog_clk[0]:355 prog_clk[0]:352 0.002125 +409 prog_clk[0]:353 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +410 prog_clk[0]:271 prog_clk[0]:270 0.0001059783 +411 prog_clk[0]:272 prog_clk[0]:271 0.0045 +412 prog_clk[0]:270 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +413 prog_clk[0]:349 prog_clk[0]:348 0.0045 +414 prog_clk[0]:350 prog_clk[0]:349 0.00341 +415 prog_clk[0]:350 prog_clk[0]:346 0.001728425 +416 prog_clk[0]:348 prog_clk[0]:347 0.0001440218 +417 prog_clk[0]:347 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +418 prog_clk[0]:426 prog_clk[0]:425 0.0005736608 +419 prog_clk[0]:425 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +420 prog_clk[0]:361 prog_clk[0]:360 0.0045 +421 prog_clk[0]:362 prog_clk[0]:361 0.00341 +422 prog_clk[0]:362 prog_clk[0]:358 0.0007206667 +423 prog_clk[0]:360 prog_clk[0]:359 0.0001440218 +424 prog_clk[0]:359 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +425 prog_clk[0]:364 prog_clk[0]:363 0.0005736608 +426 prog_clk[0]:365 prog_clk[0]:364 0.0045 +427 prog_clk[0]:363 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +428 prog_clk[0]:233 prog_clk[0]:232 0.0001847826 +429 prog_clk[0]:234 prog_clk[0]:233 0.0045 +430 prog_clk[0]:234 prog_clk[0]:231 0.005120536 +431 prog_clk[0]:232 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +432 prog_clk[0]:446 prog_clk[0]:445 0.0005334822 +433 prog_clk[0]:422 prog_clk[0]:421 0.001024554 +434 prog_clk[0]:443 prog_clk[0]:442 0.0004107143 +435 prog_clk[0]:442 prog_clk[0]:441 0.0003035715 +436 prog_clk[0]:436 prog_clk[0]:435 0.001024554 +437 prog_clk[0]:441 prog_clk[0]:440 0.001886161 +438 prog_clk[0]:266 prog_clk[0]:265 0.007352679 +439 prog_clk[0]:240 prog_clk[0]:239 0.0003035715 +440 prog_clk[0]:194 prog_clk[0]:193 0.0003035715 +441 prog_clk[0]:417 prog_clk[0]:416 0.001477679 +442 prog_clk[0]:418 prog_clk[0]:417 0.001642857 +443 prog_clk[0]:418 prog_clk[0]:413 0.002995536 +444 prog_clk[0]:419 prog_clk[0]:418 0.001821429 +445 prog_clk[0]:420 prog_clk[0]:419 0.0008214287 +446 prog_clk[0]:434 prog_clk[0]:433 0.005109375 +447 prog_clk[0]:439 prog_clk[0]:438 0.006941965 +448 prog_clk[0]:273 prog_clk[0]:272 0.0004107143 +449 prog_clk[0]:273 prog_clk[0]:269 0.004816965 +450 prog_clk[0]:396 prog_clk[0]:395 0.0004107143 +451 prog_clk[0]:465 prog_clk[0]:464 0.0004107143 +452 prog_clk[0]:243 prog_clk[0]:242 0.0005669643 +453 prog_clk[0]:244 prog_clk[0]:243 0.0008214285 +454 prog_clk[0]:244 prog_clk[0]:238 0.003287946 +455 prog_clk[0]:334 prog_clk[0]:333 0.0008214285 +456 prog_clk[0]:144 prog_clk[0]:143 0.001232143 +457 prog_clk[0]:197 prog_clk[0]:196 0.005160714 +458 prog_clk[0]:204 prog_clk[0]:203 0.002377232 +459 prog_clk[0]:344 prog_clk[0]:343 0.002388393 +460 prog_clk[0]:344 prog_clk[0]:340 0.0004107143 +461 prog_clk[0]:358 prog_clk[0]:357 0.0001065333 +462 prog_clk[0]:177 prog_clk[0]:176 6.788888e-05 +463 prog_clk[0]:177 prog_clk[0]:172 1.119047e-05 +464 prog_clk[0]:172 prog_clk[0]:171 0.001213383 +465 prog_clk[0]:319 prog_clk[0]:318 0.000647425 +466 prog_clk[0]:91 prog_clk[0]:90 0.000647425 + +*END + +*D_NET chany_top_in[0] 0.01270124 //LENGTH 94.120 LUMPCC 0.006512474 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 80.500 102.070 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 37.625 52.700 +*N chany_top_in[0]:2 *C 37.663 52.700 +*N chany_top_in[0]:3 *C 39.975 52.700 +*N chany_top_in[0]:4 *C 40.020 52.745 +*N chany_top_in[0]:5 *C 40.020 53.663 +*N chany_top_in[0]:6 *C 40.028 53.720 +*N chany_top_in[0]:7 *C 76.340 53.720 +*N chany_top_in[0]:8 *C 76.360 53.727 +*N chany_top_in[0]:9 *C 76.360 99.273 +*N chany_top_in[0]:10 *C 76.380 99.280 +*N chany_top_in[0]:11 *C 80.493 99.280 +*N chany_top_in[0]:12 *C 80.500 99.338 + +*CAP +0 chany_top_in[0] 0.0001673133 +1 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[0]:2 0.0002021265 +3 chany_top_in[0]:3 0.0002021265 +4 chany_top_in[0]:4 7.256022e-05 +5 chany_top_in[0]:5 7.256022e-05 +6 chany_top_in[0]:6 0.001382134 +7 chany_top_in[0]:7 0.001382134 +8 chany_top_in[0]:8 0.0009904745 +9 chany_top_in[0]:9 0.0009904745 +10 chany_top_in[0]:10 0.0002792751 +11 chany_top_in[0]:11 0.0002792751 +12 chany_top_in[0]:12 0.0001673133 +13 chany_top_in[0]:6 chany_top_in[3]:9 0.0006582707 +14 chany_top_in[0]:7 chany_top_in[3]:10 0.0006582707 +15 chany_top_in[0]:8 chany_top_in[6]:17 0.0004033584 +16 chany_top_in[0]:8 chany_top_in[6]:18 0.000552015 +17 chany_top_in[0]:9 chany_top_in[6]:18 0.0004033584 +18 chany_top_in[0]:9 chany_top_in[6]:19 0.000552015 +19 chany_top_in[0]:6 chanx_left_in[0]:11 0.000762489 +20 chany_top_in[0]:7 chanx_left_in[0]:10 0.000762489 +21 chany_top_in[0]:8 chanx_left_in[0]:9 0.0001672566 +22 chany_top_in[0]:9 chanx_left_in[0]:8 0.0001672566 +23 chany_top_in[0]:8 chany_top_out[2]:6 0.0006958634 +24 chany_top_in[0]:10 chany_top_out[2]:3 1.698399e-05 +25 chany_top_in[0]:9 chany_top_out[2]:5 0.0006958634 +26 chany_top_in[0]:11 chany_top_out[2]:4 1.698399e-05 + +*RES +0 chany_top_in[0] chany_top_in[0]:12 0.002439732 +1 chany_top_in[0]:2 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[0]:3 chany_top_in[0]:2 0.002064732 +3 chany_top_in[0]:4 chany_top_in[0]:3 0.0045 +4 chany_top_in[0]:5 chany_top_in[0]:4 0.0008191965 +5 chany_top_in[0]:6 chany_top_in[0]:5 0.00341 +6 chany_top_in[0]:7 chany_top_in[0]:6 0.005688958 +7 chany_top_in[0]:8 chany_top_in[0]:7 0.00341 +8 chany_top_in[0]:10 chany_top_in[0]:9 0.00341 +9 chany_top_in[0]:9 chany_top_in[0]:8 0.007135383 +10 chany_top_in[0]:12 chany_top_in[0]:11 0.00341 +11 chany_top_in[0]:11 chany_top_in[0]:10 0.0006442916 + +*END + +*D_NET chanx_left_out[6] 0.0004590175 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 26.180 +*P chanx_left_out[6] O *L 0.7423 *C 1.230 25.840 +*N chanx_left_out[6]:2 *C 3.673 25.840 +*N chanx_left_out[6]:3 *C 3.680 25.840 +*N chanx_left_out[6]:4 *C 3.680 26.180 +*N chanx_left_out[6]:5 *C 3.625 26.180 + +*CAP +0 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[6] 0.0001678964 +2 chanx_left_out[6]:2 0.0001678964 +3 chanx_left_out[6]:3 4.979924e-05 +4 chanx_left_out[6]:4 4.651807e-05 +5 chanx_left_out[6]:5 2.590743e-05 + +*RES +0 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[6]:5 0.152 +1 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +2 chanx_left_out[6]:4 chanx_left_out[6]:3 0.0001634615 +3 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +4 chanx_left_out[6]:2 chanx_left_out[6] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[1] 0.001284052 //LENGTH 8.195 LUMPCC 0.0003015124 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 47.685 77.520 +*I mem_top_track_32\/FTB_23__28:A I *L 0.001746 *C 49.220 80.240 +*I mux_top_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 47.280 82.960 +*N mux_tree_tapbuf_size2_10_sram[1]:3 *C 47.280 82.960 +*N mux_tree_tapbuf_size2_10_sram[1]:4 *C 47.380 82.915 +*N mux_tree_tapbuf_size2_10_sram[1]:5 *C 49.183 80.240 +*N mux_tree_tapbuf_size2_10_sram[1]:6 *C 47.425 80.240 +*N mux_tree_tapbuf_size2_10_sram[1]:7 *C 47.380 80.240 +*N mux_tree_tapbuf_size2_10_sram[1]:8 *C 47.380 77.565 +*N mux_tree_tapbuf_size2_10_sram[1]:9 *C 47.380 77.520 +*N mux_tree_tapbuf_size2_10_sram[1]:10 *C 47.685 77.520 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_32\/FTB_23__28:A 1e-06 +2 mux_top_track_32\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_10_sram[1]:3 3.120874e-05 +4 mux_tree_tapbuf_size2_10_sram[1]:4 0.0001095879 +5 mux_tree_tapbuf_size2_10_sram[1]:5 0.0001977565 +6 mux_tree_tapbuf_size2_10_sram[1]:6 0.0001977565 +7 mux_tree_tapbuf_size2_10_sram[1]:7 0.0002402576 +8 mux_tree_tapbuf_size2_10_sram[1]:8 0.0001000311 +9 mux_tree_tapbuf_size2_10_sram[1]:9 5.467653e-05 +10 mux_tree_tapbuf_size2_10_sram[1]:10 4.826491e-05 +11 mux_tree_tapbuf_size2_10_sram[1]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 7.371695e-05 +12 mux_tree_tapbuf_size2_10_sram[1]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 7.371695e-05 +13 mux_tree_tapbuf_size2_10_sram[1]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 7.703927e-05 +14 mux_tree_tapbuf_size2_10_sram[1]:8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 7.703927e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_10_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_10_sram[1]:3 mux_top_track_32\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_10_sram[1]:4 mux_tree_tapbuf_size2_10_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_10_sram[1]:6 mux_tree_tapbuf_size2_10_sram[1]:5 0.001569197 +4 mux_tree_tapbuf_size2_10_sram[1]:7 mux_tree_tapbuf_size2_10_sram[1]:6 0.0045 +5 mux_tree_tapbuf_size2_10_sram[1]:7 mux_tree_tapbuf_size2_10_sram[1]:4 0.002388393 +6 mux_tree_tapbuf_size2_10_sram[1]:5 mem_top_track_32\/FTB_23__28:A 0.152 +7 mux_tree_tapbuf_size2_10_sram[1]:9 mux_tree_tapbuf_size2_10_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size2_10_sram[1]:8 mux_tree_tapbuf_size2_10_sram[1]:7 0.002388393 +9 mux_tree_tapbuf_size2_10_sram[1]:10 mux_tree_tapbuf_size2_10_sram[1]:9 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_16_sram[1] 0.002223371 //LENGTH 17.835 LUMPCC 0 DR + +*CONN +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.565 55.760 +*I mux_left_track_15\/mux_l2_in_0_:S I *L 0.00357 *C 10.700 57.800 +*I mem_left_track_15\/FTB_29__34:A I *L 0.001746 *C 10.580 50.320 +*N mux_tree_tapbuf_size2_16_sram[1]:3 *C 10.543 50.320 +*N mux_tree_tapbuf_size2_16_sram[1]:4 *C 9.245 50.320 +*N mux_tree_tapbuf_size2_16_sram[1]:5 *C 9.200 50.365 +*N mux_tree_tapbuf_size2_16_sram[1]:6 *C 9.200 57.755 +*N mux_tree_tapbuf_size2_16_sram[1]:7 *C 9.325 57.800 +*N mux_tree_tapbuf_size2_16_sram[1]:8 *C 10.700 57.800 +*N mux_tree_tapbuf_size2_16_sram[1]:9 *C 13.755 57.800 +*N mux_tree_tapbuf_size2_16_sram[1]:10 *C 13.800 57.755 +*N mux_tree_tapbuf_size2_16_sram[1]:11 *C 13.800 55.805 +*N mux_tree_tapbuf_size2_16_sram[1]:12 *C 13.845 55.760 +*N mux_tree_tapbuf_size2_16_sram[1]:13 *C 14.527 55.760 + +*CAP +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_15\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_15\/FTB_29__34:A 1e-06 +3 mux_tree_tapbuf_size2_16_sram[1]:3 0.0001025038 +4 mux_tree_tapbuf_size2_16_sram[1]:4 0.0001025038 +5 mux_tree_tapbuf_size2_16_sram[1]:5 0.0004224398 +6 mux_tree_tapbuf_size2_16_sram[1]:6 0.0004224398 +7 mux_tree_tapbuf_size2_16_sram[1]:7 0.0001165329 +8 mux_tree_tapbuf_size2_16_sram[1]:8 0.0003721921 +9 mux_tree_tapbuf_size2_16_sram[1]:9 0.0002270727 +10 mux_tree_tapbuf_size2_16_sram[1]:10 0.0001530319 +11 mux_tree_tapbuf_size2_16_sram[1]:11 0.0001530319 +12 mux_tree_tapbuf_size2_16_sram[1]:12 7.431106e-05 +13 mux_tree_tapbuf_size2_16_sram[1]:13 7.431106e-05 + +*RES +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_16_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_16_sram[1]:8 mux_left_track_15\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_16_sram[1]:8 mux_tree_tapbuf_size2_16_sram[1]:7 0.001227679 +3 mux_tree_tapbuf_size2_16_sram[1]:7 mux_tree_tapbuf_size2_16_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size2_16_sram[1]:6 mux_tree_tapbuf_size2_16_sram[1]:5 0.006598215 +5 mux_tree_tapbuf_size2_16_sram[1]:4 mux_tree_tapbuf_size2_16_sram[1]:3 0.001158482 +6 mux_tree_tapbuf_size2_16_sram[1]:5 mux_tree_tapbuf_size2_16_sram[1]:4 0.0045 +7 mux_tree_tapbuf_size2_16_sram[1]:3 mem_left_track_15\/FTB_29__34:A 0.152 +8 mux_tree_tapbuf_size2_16_sram[1]:9 mux_tree_tapbuf_size2_16_sram[1]:8 0.002727679 +9 mux_tree_tapbuf_size2_16_sram[1]:10 mux_tree_tapbuf_size2_16_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size2_16_sram[1]:12 mux_tree_tapbuf_size2_16_sram[1]:11 0.0045 +11 mux_tree_tapbuf_size2_16_sram[1]:11 mux_tree_tapbuf_size2_16_sram[1]:10 0.001741072 +12 mux_tree_tapbuf_size2_16_sram[1]:13 mux_tree_tapbuf_size2_16_sram[1]:12 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size2_20_sram[0] 0.001819792 //LENGTH 13.765 LUMPCC 0 DR + +*CONN +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 43.545 26.180 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.975 28.220 +*I mux_left_track_23\/mux_l1_in_0_:S I *L 0.00357 *C 42.440 30.940 +*N mux_tree_tapbuf_size2_20_sram[0]:3 *C 42.403 30.940 +*N mux_tree_tapbuf_size2_20_sram[0]:4 *C 41.905 30.940 +*N mux_tree_tapbuf_size2_20_sram[0]:5 *C 41.860 30.895 +*N mux_tree_tapbuf_size2_20_sram[0]:6 *C 37.003 28.198 +*N mux_tree_tapbuf_size2_20_sram[0]:7 *C 37.260 28.185 +*N mux_tree_tapbuf_size2_20_sram[0]:8 *C 37.260 27.880 +*N mux_tree_tapbuf_size2_20_sram[0]:9 *C 41.815 27.880 +*N mux_tree_tapbuf_size2_20_sram[0]:10 *C 41.860 27.880 +*N mux_tree_tapbuf_size2_20_sram[0]:11 *C 41.860 26.225 +*N mux_tree_tapbuf_size2_20_sram[0]:12 *C 41.905 26.180 +*N mux_tree_tapbuf_size2_20_sram[0]:13 *C 43.508 26.180 + +*CAP +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_23\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_20_sram[0]:3 5.985752e-05 +4 mux_tree_tapbuf_size2_20_sram[0]:4 5.985752e-05 +5 mux_tree_tapbuf_size2_20_sram[0]:5 0.0001855334 +6 mux_tree_tapbuf_size2_20_sram[0]:6 4.2411e-05 +7 mux_tree_tapbuf_size2_20_sram[0]:7 6.740333e-05 +8 mux_tree_tapbuf_size2_20_sram[0]:8 0.0003938868 +9 mux_tree_tapbuf_size2_20_sram[0]:9 0.0003688945 +10 mux_tree_tapbuf_size2_20_sram[0]:10 0.0003194345 +11 mux_tree_tapbuf_size2_20_sram[0]:11 9.858361e-05 +12 mux_tree_tapbuf_size2_20_sram[0]:12 0.0001104647 +13 mux_tree_tapbuf_size2_20_sram[0]:13 0.0001104647 + +*RES +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_20_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_20_sram[0]:13 mux_tree_tapbuf_size2_20_sram[0]:12 0.001430803 +2 mux_tree_tapbuf_size2_20_sram[0]:12 mux_tree_tapbuf_size2_20_sram[0]:11 0.0045 +3 mux_tree_tapbuf_size2_20_sram[0]:11 mux_tree_tapbuf_size2_20_sram[0]:10 0.001477679 +4 mux_tree_tapbuf_size2_20_sram[0]:4 mux_tree_tapbuf_size2_20_sram[0]:3 0.0004441965 +5 mux_tree_tapbuf_size2_20_sram[0]:5 mux_tree_tapbuf_size2_20_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_20_sram[0]:3 mux_left_track_23\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_20_sram[0]:9 mux_tree_tapbuf_size2_20_sram[0]:8 0.004066965 +8 mux_tree_tapbuf_size2_20_sram[0]:10 mux_tree_tapbuf_size2_20_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_20_sram[0]:10 mux_tree_tapbuf_size2_20_sram[0]:5 0.002691964 +10 mux_tree_tapbuf_size2_20_sram[0]:6 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size2_20_sram[0]:7 mux_tree_tapbuf_size2_20_sram[0]:6 0.0001739865 +12 mux_tree_tapbuf_size2_20_sram[0]:8 mux_tree_tapbuf_size2_20_sram[0]:7 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[0] 0.004143631 //LENGTH 29.295 LUMPCC 0.00031947 DR + +*CONN +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.925 96.560 +*I mux_top_track_26\/mux_l1_in_0_:S I *L 0.00357 *C 52.800 89.080 +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 49.395 93.500 +*N mux_tree_tapbuf_size2_7_sram[0]:3 *C 49.433 93.500 +*N mux_tree_tapbuf_size2_7_sram[0]:4 *C 51.520 93.500 +*N mux_tree_tapbuf_size2_7_sram[0]:5 *C 52.763 89.080 +*N mux_tree_tapbuf_size2_7_sram[0]:6 *C 51.565 89.080 +*N mux_tree_tapbuf_size2_7_sram[0]:7 *C 51.520 89.125 +*N mux_tree_tapbuf_size2_7_sram[0]:8 *C 51.520 93.115 +*N mux_tree_tapbuf_size2_7_sram[0]:9 *C 51.520 93.160 +*N mux_tree_tapbuf_size2_7_sram[0]:10 *C 67.575 93.160 +*N mux_tree_tapbuf_size2_7_sram[0]:11 *C 67.620 93.205 +*N mux_tree_tapbuf_size2_7_sram[0]:12 *C 67.620 96.515 +*N mux_tree_tapbuf_size2_7_sram[0]:13 *C 67.620 96.560 +*N mux_tree_tapbuf_size2_7_sram[0]:14 *C 67.925 96.560 + +*CAP +0 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_26\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_7_sram[0]:3 0.0001756117 +4 mux_tree_tapbuf_size2_7_sram[0]:4 0.0002041162 +5 mux_tree_tapbuf_size2_7_sram[0]:5 0.0001340916 +6 mux_tree_tapbuf_size2_7_sram[0]:6 0.0001340916 +7 mux_tree_tapbuf_size2_7_sram[0]:7 0.0002821801 +8 mux_tree_tapbuf_size2_7_sram[0]:8 0.0002821801 +9 mux_tree_tapbuf_size2_7_sram[0]:9 0.001064239 +10 mux_tree_tapbuf_size2_7_sram[0]:10 0.001035735 +11 mux_tree_tapbuf_size2_7_sram[0]:11 0.0002049475 +12 mux_tree_tapbuf_size2_7_sram[0]:12 0.0002049475 +13 mux_tree_tapbuf_size2_7_sram[0]:13 5.044473e-05 +14 mux_tree_tapbuf_size2_7_sram[0]:14 4.857625e-05 +15 mux_tree_tapbuf_size2_7_sram[0]:10 chany_top_out[1]:4 0.000159735 +16 mux_tree_tapbuf_size2_7_sram[0]:9 chany_top_out[1]:3 0.000159735 + +*RES +0 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_7_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_7_sram[0]:10 mux_tree_tapbuf_size2_7_sram[0]:9 0.01433482 +2 mux_tree_tapbuf_size2_7_sram[0]:11 mux_tree_tapbuf_size2_7_sram[0]:10 0.0045 +3 mux_tree_tapbuf_size2_7_sram[0]:13 mux_tree_tapbuf_size2_7_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size2_7_sram[0]:12 mux_tree_tapbuf_size2_7_sram[0]:11 0.002955357 +5 mux_tree_tapbuf_size2_7_sram[0]:14 mux_tree_tapbuf_size2_7_sram[0]:13 0.0001657609 +6 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:8 0.0045 +7 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:4 0.0003035715 +8 mux_tree_tapbuf_size2_7_sram[0]:8 mux_tree_tapbuf_size2_7_sram[0]:7 0.0035625 +9 mux_tree_tapbuf_size2_7_sram[0]:6 mux_tree_tapbuf_size2_7_sram[0]:5 0.001069196 +10 mux_tree_tapbuf_size2_7_sram[0]:7 mux_tree_tapbuf_size2_7_sram[0]:6 0.0045 +11 mux_tree_tapbuf_size2_7_sram[0]:5 mux_top_track_26\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size2_7_sram[0]:3 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size2_7_sram[0]:4 mux_tree_tapbuf_size2_7_sram[0]:3 0.001863839 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_14_ccff_tail[0] 0.001273957 //LENGTH 8.620 LUMPCC 0.0004465335 DR + +*CONN +*I mem_left_track_11\/FTB_27__32:X O *L 0 *C 38.865 71.740 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 30.535 71.740 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 *C 30.573 71.740 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 *C 38.828 71.740 + +*CAP +0 mem_left_track_11\/FTB_27__32:X 1e-06 +1 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 0.000412712 +3 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 0.000412712 +4 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 chanx_left_in[3]:9 5.186618e-05 +5 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 chanx_left_in[3]:8 5.186618e-05 +6 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 chanx_left_in[7]:10 0.0001714006 +7 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 chanx_left_in[7]:9 0.0001714006 + +*RES +0 mem_left_track_11\/FTB_27__32:X mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 0.007370536 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.0005841595 //LENGTH 4.330 LUMPCC 8.102065e-05 DR + +*CONN +*I mem_top_track_18\/FTB_17__22:X O *L 0 *C 65.095 90.780 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 64.575 88.060 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 64.575 88.060 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 64.400 88.060 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 *C 64.400 88.105 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 *C 64.400 90.735 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 *C 64.445 90.780 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 *C 65.058 90.780 + +*CAP +0 mem_top_track_18\/FTB_17__22:X 1e-06 +1 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 4.975122e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 5.413321e-05 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0001606593 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0001606593 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 3.796787e-05 +7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 3.796787e-05 +8 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 chanx_left_in[8]:3 3.654968e-05 +9 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 chanx_left_in[8]:4 3.654968e-05 +10 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 chanx_left_in[8]:5 3.960643e-06 +11 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 chanx_left_in[8]:6 3.960643e-06 + +*RES +0 mem_top_track_18\/FTB_17__22:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.000546875 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[0] 0.002868497 //LENGTH 22.808 LUMPCC 0.0001310272 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 50.905 31.620 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.475 33.660 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 47.940 42.160 +*I mux_left_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 41.760 36.040 +*N mux_tree_tapbuf_size3_3_sram[0]:4 *C 41.797 36.040 +*N mux_tree_tapbuf_size3_3_sram[0]:5 *C 47.380 36.040 +*N mux_tree_tapbuf_size3_3_sram[0]:6 *C 47.903 42.160 +*N mux_tree_tapbuf_size3_3_sram[0]:7 *C 47.425 42.160 +*N mux_tree_tapbuf_size3_3_sram[0]:8 *C 47.380 42.115 +*N mux_tree_tapbuf_size3_3_sram[0]:9 *C 47.380 36.425 +*N mux_tree_tapbuf_size3_3_sram[0]:10 *C 47.380 36.380 +*N mux_tree_tapbuf_size3_3_sram[0]:11 *C 48.255 36.380 +*N mux_tree_tapbuf_size3_3_sram[0]:12 *C 48.300 36.335 +*N mux_tree_tapbuf_size3_3_sram[0]:13 *C 48.300 33.705 +*N mux_tree_tapbuf_size3_3_sram[0]:14 *C 48.300 33.660 +*N mux_tree_tapbuf_size3_3_sram[0]:15 *C 48.513 33.660 +*N mux_tree_tapbuf_size3_3_sram[0]:16 *C 50.555 33.660 +*N mux_tree_tapbuf_size3_3_sram[0]:17 *C 50.600 33.615 +*N mux_tree_tapbuf_size3_3_sram[0]:18 *C 50.600 31.665 +*N mux_tree_tapbuf_size3_3_sram[0]:19 *C 50.600 31.620 +*N mux_tree_tapbuf_size3_3_sram[0]:20 *C 50.905 31.620 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size3_3_sram[0]:4 0.0004135352 +5 mux_tree_tapbuf_size3_3_sram[0]:5 0.0004418163 +6 mux_tree_tapbuf_size3_3_sram[0]:6 6.905416e-05 +7 mux_tree_tapbuf_size3_3_sram[0]:7 6.905416e-05 +8 mux_tree_tapbuf_size3_3_sram[0]:8 0.0002471734 +9 mux_tree_tapbuf_size3_3_sram[0]:9 0.0002471734 +10 mux_tree_tapbuf_size3_3_sram[0]:10 0.0001369916 +11 mux_tree_tapbuf_size3_3_sram[0]:11 0.0001087104 +12 mux_tree_tapbuf_size3_3_sram[0]:12 0.000157306 +13 mux_tree_tapbuf_size3_3_sram[0]:13 0.000157306 +14 mux_tree_tapbuf_size3_3_sram[0]:14 5.250479e-05 +15 mux_tree_tapbuf_size3_3_sram[0]:15 0.0001648476 +16 mux_tree_tapbuf_size3_3_sram[0]:16 0.0001432534 +17 mux_tree_tapbuf_size3_3_sram[0]:17 0.0001165872 +18 mux_tree_tapbuf_size3_3_sram[0]:18 0.0001165872 +19 mux_tree_tapbuf_size3_3_sram[0]:19 4.775342e-05 +20 mux_tree_tapbuf_size3_3_sram[0]:20 4.381597e-05 +21 mux_tree_tapbuf_size3_3_sram[0]:9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 6.551358e-05 +22 mux_tree_tapbuf_size3_3_sram[0]:8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 6.551358e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_3_sram[0]:20 0.152 +1 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:13 0.0045 +2 mux_tree_tapbuf_size3_3_sram[0]:13 mux_tree_tapbuf_size3_3_sram[0]:12 0.002348214 +3 mux_tree_tapbuf_size3_3_sram[0]:11 mux_tree_tapbuf_size3_3_sram[0]:10 0.00078125 +4 mux_tree_tapbuf_size3_3_sram[0]:12 mux_tree_tapbuf_size3_3_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size3_3_sram[0]:15 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:14 0.0001154891 +7 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:15 0.001823661 +8 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:16 0.0045 +9 mux_tree_tapbuf_size3_3_sram[0]:19 mux_tree_tapbuf_size3_3_sram[0]:18 0.0045 +10 mux_tree_tapbuf_size3_3_sram[0]:18 mux_tree_tapbuf_size3_3_sram[0]:17 0.001741072 +11 mux_tree_tapbuf_size3_3_sram[0]:20 mux_tree_tapbuf_size3_3_sram[0]:19 0.0001657609 +12 mux_tree_tapbuf_size3_3_sram[0]:4 mux_left_track_25\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_3_sram[0]:10 mux_tree_tapbuf_size3_3_sram[0]:9 0.0045 +14 mux_tree_tapbuf_size3_3_sram[0]:10 mux_tree_tapbuf_size3_3_sram[0]:5 0.0003035715 +15 mux_tree_tapbuf_size3_3_sram[0]:9 mux_tree_tapbuf_size3_3_sram[0]:8 0.005080357 +16 mux_tree_tapbuf_size3_3_sram[0]:7 mux_tree_tapbuf_size3_3_sram[0]:6 0.0004263393 +17 mux_tree_tapbuf_size3_3_sram[0]:8 mux_tree_tapbuf_size3_3_sram[0]:7 0.0045 +18 mux_tree_tapbuf_size3_3_sram[0]:6 mux_left_track_25\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size3_3_sram[0]:5 mux_tree_tapbuf_size3_3_sram[0]:4 0.004984376 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_0_ccff_tail[0] 0.0009548762 //LENGTH 7.050 LUMPCC 0.0001742726 DR + +*CONN +*I mem_top_track_2\/FTB_5__10:X O *L 0 *C 77.515 52.360 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 73.775 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 *C 73.812 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 *C 75.395 49.980 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 *C 75.440 50.025 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 *C 75.440 52.315 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 *C 75.485 52.360 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 *C 77.478 52.360 + +*CAP +0 mem_top_track_2\/FTB_5__10:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 0.0001309025 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0001309025 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0001499901 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0001499901 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.0001084093 +7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.0001084093 +8 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.713629e-05 +9 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.713629e-05 + +*RES +0 mem_top_track_2\/FTB_5__10:X mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 0.001412946 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.001779018 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.001550746 //LENGTH 13.525 LUMPCC 9.283452e-05 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 91.845 55.420 +*I mem_top_track_4\/FTB_2__7:A I *L 0.001746 *C 95.680 58.480 +*I mux_top_track_4\/mux_l3_in_0_:S I *L 0.008363 *C 92.000 63.695 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 92.000 63.580 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 92.000 63.535 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 95.680 58.480 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 95.680 58.140 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 92.045 58.140 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 92.000 58.140 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 92.000 55.465 +*N mux_tree_tapbuf_size6_1_sram[2]:10 *C 92.000 55.420 +*N mux_tree_tapbuf_size6_1_sram[2]:11 *C 91.845 55.420 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_4\/FTB_2__7:A 1e-06 +2 mux_top_track_4\/mux_l3_in_0_:S 2.221809e-05 +3 mux_tree_tapbuf_size6_1_sram[2]:3 2.221809e-05 +4 mux_tree_tapbuf_size6_1_sram[2]:4 0.0002702623 +5 mux_tree_tapbuf_size6_1_sram[2]:5 5.338318e-05 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0002312453 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0002049686 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0004313494 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.0001328759 +10 mux_tree_tapbuf_size6_1_sram[2]:10 4.557541e-05 +11 mux_tree_tapbuf_size6_1_sram[2]:11 4.181529e-05 +12 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 8.797379e-06 +13 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 3.761988e-05 +14 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 8.797379e-06 +15 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 3.761988e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:11 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:3 mux_top_track_4\/mux_l3_in_0_:S 5.078125e-05 +2 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.0045 +3 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.003245536 +4 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:4 0.004816965 +6 mux_tree_tapbuf_size6_1_sram[2]:5 mem_top_track_4\/FTB_2__7:A 0.152 +7 mux_tree_tapbuf_size6_1_sram[2]:10 mux_tree_tapbuf_size6_1_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.002388393 +9 mux_tree_tapbuf_size6_1_sram[2]:11 mux_tree_tapbuf_size6_1_sram[2]:10 8.423914e-05 +10 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.0003035715 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001206302 //LENGTH 10.060 LUMPCC 0.0003594842 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_1_:X O *L 0 *C 81.245 71.740 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 85.275 76.840 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 85.237 76.840 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 82.845 76.840 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 82.800 76.795 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 82.800 71.785 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 82.755 71.740 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.282 71.740 + +*CAP +0 mux_top_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001256729 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001256729 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001947177 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001947177 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001020181 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001020181 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_out[5] 7.760805e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_out[5]:2 7.760805e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_0_sram[0]:18 0.0001021341 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_0_sram[0]:17 0.0001021341 + +*RES +0 mux_top_track_0\/mux_l1_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002136161 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473214 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001276739 //LENGTH 10.615 LUMPCC 0.0001097395 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_1_:X O *L 0 *C 15.005 49.980 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 14.070 42.500 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 14.107 42.500 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 15.595 42.500 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 15.640 42.545 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 15.640 49.935 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 15.595 49.980 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 15.043 49.980 + +*CAP +0 mux_left_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000122582 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000122582 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003731416 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003731416 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.677628e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.677628e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_17_sram[0]:6 5.486975e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_17_sram[0]:5 5.486975e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006598215 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001328125 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006124486 //LENGTH 4.740 LUMPCC 0.0001339882 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 23.635 46.920 +*I mux_left_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 21.525 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 21.562 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.955 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.000 45.265 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 23.000 46.875 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 23.045 46.920 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 23.598 46.920 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.110043e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.110043e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000113879 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000113879 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.325072e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.325072e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size6_3_sram[2]:3 6.699409e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_3_sram[2]:4 6.699409e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001243304 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003174368 //LENGTH 27.895 LUMPCC 0.0006209956 DR + +*CONN +*I mux_top_track_6\/mux_l3_in_0_:X O *L 0 *C 65.145 48.280 +*I mux_top_track_6\/BUFT_RR_42:A I *L 0.001776 *C 65.320 74.800 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 65.282 74.800 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 64.905 74.800 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 64.860 74.755 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 64.860 48.325 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 64.860 48.280 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 65.145 48.280 + +*CAP +0 mux_top_track_6\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_6\/BUFT_RR_42:A 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.145858e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.145858e-05 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001178127 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.001178127 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.620597e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.599391e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:186 1.385338e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:192 1.355569e-05 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:196 3.567334e-05 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:203 1.984964e-05 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:210 0.0001535288 +13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:322 1.092425e-07 +14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:192 1.385338e-05 +15 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:196 1.355569e-05 +16 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:197 3.567334e-05 +17 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:204 1.984964e-05 +18 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:211 0.0001535288 +19 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:323 1.092425e-07 +20 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.344435e-05 +21 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 4.833728e-07 +22 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.344435e-05 +23 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 4.833728e-07 + +*RES +0 mux_top_track_6\/mux_l3_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001548913 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.02359822 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003370536 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_6\/BUFT_RR_42:A 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001112534 //LENGTH 8.275 LUMPCC 0.0003729101 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 78.835 91.460 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 76.360 96.220 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 76.398 96.220 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 77.235 96.220 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 77.280 96.175 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 77.280 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 77.740 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 77.785 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 78.797 91.460 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.433633e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.433633e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001873181 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002229 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.959221e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.457069e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.457069e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_108:23 3.430885e-07 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_108:26 5.125669e-05 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 optlc_net_108:25 5.125669e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_108:22 3.430885e-07 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.823203e-06 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.823203e-06 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000125948 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.08405e-06 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.08405e-06 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000125948 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0007477679 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004107143 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0009040179 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004209822 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004600826 //LENGTH 33.345 LUMPCC 0.001396571 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_0_:X O *L 0 *C 52.265 70.040 +*I mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 56.505 96.740 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 52.040 79.560 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 56.505 96.740 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 56.580 96.560 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 56.580 96.515 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 56.580 94.578 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 56.573 94.520 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 52.460 94.520 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 52.440 94.513 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 52.440 79.568 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 52.440 79.560 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 52.440 79.502 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 52.440 70.085 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 52.440 70.040 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 52.265 70.040 + +*CAP +0 mux_top_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.624268e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.745555e-05 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.914364e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001395887 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001395887 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003408143 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0003408143 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.000560422 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000560422 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.624268e-05 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0003792579 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0003792579 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:14 5.485491e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:15 5.814967e-05 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_top_in[13]:7 0.0001756099 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_top_in[13]:8 0.0001756099 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 top_left_grid_pin_35_[0]:14 0.0002570607 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 top_left_grid_pin_35_[0]:15 0.0002570607 +20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_top_out[7]:6 0.0002656147 +21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_top_out[7]:5 0.0002656147 + +*RES +0 mux_top_track_16\/mux_l2_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:14 9.51087e-05 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.008408483 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.00341 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.69697e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.002341383 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006442917 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001729911 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.782609e-05 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.007343615 //LENGTH 52.745 LUMPCC 0.001511364 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_0_:X O *L 0 *C 48.125 83.640 +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 84.015 99.095 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.978 98.995 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 81.925 98.940 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 81.880 98.895 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 81.880 89.138 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 81.873 89.080 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 48.768 89.080 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 48.760 89.023 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 48.760 83.685 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 48.715 83.640 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 48.163 83.640 + +*CAP +0 mux_top_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001759918 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001759918 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0005260137 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0005260137 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001832466 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001832466 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0003131493 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0003131493 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.750493e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.750493e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_34_[0]:28 0.0001834447 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_34_[0]:27 0.0001834447 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_41_[0] 0.000218412 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_41_[0]:19 0.000218412 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002911902 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002911902 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_130:6 6.263501e-05 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_130:5 6.263501e-05 + +*RES +0 mux_top_track_32\/mux_l2_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0004933035 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.004765625 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00518645 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.008712053 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00183259 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET ropt_net_130 0.00120244 //LENGTH 9.075 LUMPCC 0.00012527 DR + +*CONN +*I ropt_mt_inst_723:X O *L 0 *C 82.535 96.900 +*I ropt_mt_inst_735:A I *L 0.001767 *C 77.740 99.280 +*N ropt_net_130:2 *C 77.740 99.280 +*N ropt_net_130:3 *C 77.740 99.620 +*N ropt_net_130:4 *C 81.375 99.620 +*N ropt_net_130:5 *C 81.420 99.575 +*N ropt_net_130:6 *C 81.420 96.945 +*N ropt_net_130:7 *C 81.465 96.900 +*N ropt_net_130:8 *C 82.498 96.900 + +*CAP +0 ropt_mt_inst_723:X 1e-06 +1 ropt_mt_inst_735:A 1e-06 +2 ropt_net_130:2 5.858374e-05 +3 ropt_net_130:3 0.0003123006 +4 ropt_net_130:4 0.0002835783 +5 ropt_net_130:5 0.0001279424 +6 ropt_net_130:6 0.0001279424 +7 ropt_net_130:7 8.241144e-05 +8 ropt_net_130:8 8.241144e-05 +9 ropt_net_130:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.263501e-05 +10 ropt_net_130:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.263501e-05 + +*RES +0 ropt_mt_inst_723:X ropt_net_130:8 0.152 +1 ropt_net_130:8 ropt_net_130:7 0.0009218751 +2 ropt_net_130:7 ropt_net_130:6 0.0045 +3 ropt_net_130:6 ropt_net_130:5 0.002348214 +4 ropt_net_130:4 ropt_net_130:3 0.003245536 +5 ropt_net_130:5 ropt_net_130:4 0.0045 +6 ropt_net_130:2 ropt_mt_inst_735:A 0.152 +7 ropt_net_130:3 ropt_net_130:2 0.0003035715 + +*END + +*D_NET mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004476033 //LENGTH 3.215 LUMPCC 0 DR + +*CONN +*I mux_left_track_23\/mux_l1_in_0_:X O *L 0 *C 39.735 30.600 +*I mux_left_track_23\/mux_l2_in_0_:A1 I *L 0.00198 *C 37.165 30.940 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 37.165 30.940 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 37.260 30.600 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 39.698 30.600 + +*CAP +0 mux_left_track_23\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_23\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.546233e-05 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002087382 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001814028 + +*RES +0 mux_left_track_23\/mux_l1_in_0_:X mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_23\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002176339 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET ropt_net_134 0.001411281 //LENGTH 8.850 LUMPCC 0.0004034445 DR + +*CONN +*I ropt_mt_inst_727:X O *L 0 *C 8.280 37.400 +*I ropt_mt_inst_739:A I *L 0.001766 *C 3.220 39.440 +*N ropt_net_134:2 *C 3.220 39.440 +*N ropt_net_134:3 *C 3.220 39.100 +*N ropt_net_134:4 *C 6.395 39.100 +*N ropt_net_134:5 *C 6.440 39.100 +*N ropt_net_134:6 *C 6.440 39.440 +*N ropt_net_134:7 *C 6.448 39.440 +*N ropt_net_134:8 *C 8.273 39.440 +*N ropt_net_134:9 *C 8.280 39.383 +*N ropt_net_134:10 *C 8.280 37.445 +*N ropt_net_134:11 *C 8.280 37.400 + +*CAP +0 ropt_mt_inst_727:X 1e-06 +1 ropt_mt_inst_739:A 1e-06 +2 ropt_net_134:2 5.566407e-05 +3 ropt_net_134:3 0.0001892456 +4 ropt_net_134:4 0.0001618909 +5 ropt_net_134:5 5.566741e-05 +6 ropt_net_134:6 5.96657e-05 +7 ropt_net_134:7 0.0001729948 +8 ropt_net_134:8 0.0001729948 +9 ropt_net_134:9 5.119646e-05 +10 ropt_net_134:10 5.119646e-05 +11 ropt_net_134:11 3.532059e-05 +12 ropt_net_134:4 chanx_left_in[15]:13 7.743017e-05 +13 ropt_net_134:3 chanx_left_in[15]:14 7.743017e-05 +14 ropt_net_134:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.191603e-05 +15 ropt_net_134:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.191603e-05 +16 ropt_net_134:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.600085e-07 +17 ropt_net_134:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.600085e-07 +18 ropt_net_134:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.191603e-05 +19 ropt_net_134:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.191603e-05 + +*RES +0 ropt_mt_inst_727:X ropt_net_134:11 0.152 +1 ropt_net_134:2 ropt_mt_inst_739:A 0.152 +2 ropt_net_134:4 ropt_net_134:3 0.002834822 +3 ropt_net_134:5 ropt_net_134:4 0.0045 +4 ropt_net_134:6 ropt_net_134:5 0.0001634615 +5 ropt_net_134:7 ropt_net_134:6 0.00341 +6 ropt_net_134:9 ropt_net_134:8 0.00341 +7 ropt_net_134:8 ropt_net_134:7 0.0002859167 +8 ropt_net_134:11 ropt_net_134:10 0.0045 +9 ropt_net_134:10 ropt_net_134:9 0.001729911 +10 ropt_net_134:3 ropt_net_134:2 0.0003035715 + +*END + +*D_NET mem_left_track_27/net_net_59 0.001684329 //LENGTH 14.350 LUMPCC 0 DR + +*CONN +*I mem_left_track_27\/BUFT_RR_60:X O *L 0 *C 6.125 63.580 +*I mem_left_track_27\/BUFT_RR_84:A I *L 0.001767 *C 5.980 53.040 +*N mem_left_track_27/net_net_59:2 *C 5.980 53.040 +*N mem_left_track_27/net_net_59:3 *C 5.980 53.085 +*N mem_left_track_27/net_net_59:4 *C 5.980 55.080 +*N mem_left_track_27/net_net_59:5 *C 4.600 55.080 +*N mem_left_track_27/net_net_59:6 *C 4.600 63.535 +*N mem_left_track_27/net_net_59:7 *C 4.645 63.580 +*N mem_left_track_27/net_net_59:8 *C 6.088 63.580 + +*CAP +0 mem_left_track_27\/BUFT_RR_60:X 1e-06 +1 mem_left_track_27\/BUFT_RR_84:A 1e-06 +2 mem_left_track_27/net_net_59:2 3.279629e-05 +3 mem_left_track_27/net_net_59:3 0.0001236736 +4 mem_left_track_27/net_net_59:4 0.0002043684 +5 mem_left_track_27/net_net_59:5 0.0005792449 +6 mem_left_track_27/net_net_59:6 0.0004985501 +7 mem_left_track_27/net_net_59:7 0.0001218476 +8 mem_left_track_27/net_net_59:8 0.0001218476 + +*RES +0 mem_left_track_27\/BUFT_RR_60:X mem_left_track_27/net_net_59:8 0.152 +1 mem_left_track_27/net_net_59:8 mem_left_track_27/net_net_59:7 0.001287946 +2 mem_left_track_27/net_net_59:7 mem_left_track_27/net_net_59:6 0.0045 +3 mem_left_track_27/net_net_59:6 mem_left_track_27/net_net_59:5 0.007549108 +4 mem_left_track_27/net_net_59:2 mem_left_track_27\/BUFT_RR_84:A 0.152 +5 mem_left_track_27/net_net_59:3 mem_left_track_27/net_net_59:2 0.0045 +6 mem_left_track_27/net_net_59:5 mem_left_track_27/net_net_59:4 0.001232143 +7 mem_left_track_27/net_net_59:4 mem_left_track_27/net_net_59:3 0.00178125 + +*END + +*D_NET chany_top_in[7] 0.007855379 //LENGTH 64.410 LUMPCC 0.001303816 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 66.700 102.070 +*I mux_left_track_27\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.765 63.580 +*N chany_top_in[7]:2 *C 41.765 63.580 +*N chany_top_in[7]:3 *C 41.860 63.625 +*N chany_top_in[7]:4 *C 41.860 79.855 +*N chany_top_in[7]:5 *C 41.905 79.900 +*N chany_top_in[7]:6 *C 49.680 79.900 +*N chany_top_in[7]:7 *C 49.680 80.240 +*N chany_top_in[7]:8 *C 66.655 80.240 +*N chany_top_in[7]:9 *C 66.700 80.285 + +*CAP +0 chany_top_in[7] 0.0009388124 +1 mux_left_track_27\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[7]:2 2.673816e-05 +3 chany_top_in[7]:3 0.0009532375 +4 chany_top_in[7]:4 0.0009532375 +5 chany_top_in[7]:5 0.0004429002 +6 chany_top_in[7]:6 0.0004692416 +7 chany_top_in[7]:7 0.0009269622 +8 chany_top_in[7]:8 0.0009006207 +9 chany_top_in[7]:9 0.0009388124 +10 chany_top_in[7]:5 chanx_left_in[10]:13 8.277514e-05 +11 chany_top_in[7]:8 chanx_left_in[10]:12 0.0001758679 +12 chany_top_in[7]:8 chanx_left_in[10]:8 5.076335e-06 +13 chany_top_in[7]:6 chanx_left_in[10]:12 8.277514e-05 +14 chany_top_in[7]:7 chanx_left_in[10]:9 5.076335e-06 +15 chany_top_in[7]:7 chanx_left_in[10]:13 0.0001758679 +16 chany_top_in[7]:8 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:7 6.982678e-05 +17 chany_top_in[7]:7 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:6 6.982678e-05 +18 chany_top_in[7] mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002210322 +19 chany_top_in[7]:9 mux_top_track_38/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002210322 +20 chany_top_in[7] mux_top_track_6/BUF_net_42:3 9.732984e-05 +21 chany_top_in[7]:9 mux_top_track_6/BUF_net_42:4 9.732984e-05 + +*RES +0 chany_top_in[7] chany_top_in[7]:9 0.01945089 +1 chany_top_in[7]:2 mux_left_track_27\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[7]:3 chany_top_in[7]:2 0.0045 +3 chany_top_in[7]:5 chany_top_in[7]:4 0.0045 +4 chany_top_in[7]:4 chany_top_in[7]:3 0.01449107 +5 chany_top_in[7]:8 chany_top_in[7]:7 0.01515625 +6 chany_top_in[7]:9 chany_top_in[7]:8 0.0045 +7 chany_top_in[7]:6 chany_top_in[7]:5 0.006941965 +8 chany_top_in[7]:7 chany_top_in[7]:6 0.0003035715 + +*END + +*D_NET chany_top_out[1] 0.001811751 //LENGTH 13.120 LUMPCC 0.00031947 DR + +*CONN +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 65.265 93.500 +*P chany_top_out[1] O *L 0.7423 *C 61.180 102.070 +*N chany_top_out[1]:2 *C 61.180 93.545 +*N chany_top_out[1]:3 *C 61.225 93.500 +*N chany_top_out[1]:4 *C 65.228 93.500 + +*CAP +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[1] 0.0005748406 +2 chany_top_out[1]:2 0.0005748406 +3 chany_top_out[1]:3 0.0001707998 +4 chany_top_out[1]:4 0.0001707998 +5 chany_top_out[1]:4 mux_tree_tapbuf_size2_7_sram[0]:10 0.000159735 +6 chany_top_out[1]:3 mux_tree_tapbuf_size2_7_sram[0]:9 0.000159735 + +*RES +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[1]:4 0.152 +1 chany_top_out[1]:4 chany_top_out[1]:3 0.003573661 +2 chany_top_out[1]:3 chany_top_out[1]:2 0.0045 +3 chany_top_out[1]:2 chany_top_out[1] 0.007611607 + +*END + +*D_NET chany_top_out[9] 0.0005909575 //LENGTH 4.915 LUMPCC 0 DR + +*CONN +*I mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 57.100 98.940 +*P chany_top_out[9] O *L 0.7423 *C 58.420 102.070 +*N chany_top_out[9]:2 *C 58.420 98.985 +*N chany_top_out[9]:3 *C 58.375 98.940 +*N chany_top_out[9]:4 *C 57.138 98.940 + +*CAP +0 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[9] 0.00020182 +2 chany_top_out[9]:2 0.00020182 +3 chany_top_out[9]:3 9.315871e-05 +4 chany_top_out[9]:4 9.315871e-05 + +*RES +0 mux_top_track_18\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[9]:4 0.152 +1 chany_top_out[9]:4 chany_top_out[9]:3 0.001104911 +2 chany_top_out[9]:3 chany_top_out[9]:2 0.0045 +3 chany_top_out[9]:2 chany_top_out[9] 0.002754464 + +*END + +*D_NET chanx_left_out[0] 0.0006237566 //LENGTH 4.690 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.085 28.220 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 27.200 +*N chanx_left_out[0]:2 *C 3.673 27.200 +*N chanx_left_out[0]:3 *C 3.680 27.258 +*N chanx_left_out[0]:4 *C 3.680 28.175 +*N chanx_left_out[0]:5 *C 3.703 28.220 +*N chanx_left_out[0]:6 *C 4.070 28.220 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 0.0001953294 +2 chanx_left_out[0]:2 0.0001953294 +3 chanx_left_out[0]:3 7.281575e-05 +4 chanx_left_out[0]:4 7.281575e-05 +5 chanx_left_out[0]:5 4.323308e-05 +6 chanx_left_out[0]:6 4.323308e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:6 0.152 +1 chanx_left_out[0]:6 chanx_left_out[0]:5 0.0001997283 +2 chanx_left_out[0]:5 chanx_left_out[0]:4 0.0045 +3 chanx_left_out[0]:4 chanx_left_out[0]:3 0.0008191965 +4 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +5 chanx_left_out[0]:2 chanx_left_out[0] 0.0003826583 + +*END + +*D_NET chanx_left_out[13] 0.002610899 //LENGTH 17.125 LUMPCC 0.0005657969 DR + +*CONN +*I mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 13.800 69.700 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 65.960 +*N chanx_left_out[13]:2 *C 10.113 65.960 +*N chanx_left_out[13]:3 *C 10.120 66.017 +*N chanx_left_out[13]:4 *C 10.120 69.655 +*N chanx_left_out[13]:5 *C 10.165 69.700 +*N chanx_left_out[13]:6 *C 13.763 69.700 + +*CAP +0 mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[13] 0.0006861497 +2 chanx_left_out[13]:2 0.0006861497 +3 chanx_left_out[13]:3 0.0002595109 +4 chanx_left_out[13]:4 0.0002595109 +5 chanx_left_out[13]:5 7.639035e-05 +6 chanx_left_out[13]:6 7.639035e-05 +7 chanx_left_out[13]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001414472 +8 chanx_left_out[13]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001414472 +9 chanx_left_out[13]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.54385e-07 +10 chanx_left_out[13]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001405969 +11 chanx_left_out[13]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001405969 +12 chanx_left_out[13]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.54385e-07 + +*RES +0 mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +2 chanx_left_out[13]:2 chanx_left_out[13] 0.001391592 +3 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +4 chanx_left_out[13]:4 chanx_left_out[13]:3 0.003247768 +5 chanx_left_out[13]:6 chanx_left_out[13]:5 0.003212054 + +*END + +*D_NET mux_tree_tapbuf_size2_15_sram[0] 0.005124149 //LENGTH 35.290 LUMPCC 0.002075178 DR + +*CONN +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 36.095 72.420 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.455 71.740 +*I mux_left_track_13\/mux_l1_in_0_:S I *L 0.00357 *C 17.580 72.375 +*N mux_tree_tapbuf_size2_15_sram[0]:3 *C 17.580 72.375 +*N mux_tree_tapbuf_size2_15_sram[0]:4 *C 8.492 71.740 +*N mux_tree_tapbuf_size2_15_sram[0]:5 *C 15.180 71.740 +*N mux_tree_tapbuf_size2_15_sram[0]:6 *C 15.180 72.080 +*N mux_tree_tapbuf_size2_15_sram[0]:7 *C 17.580 72.080 +*N mux_tree_tapbuf_size2_15_sram[0]:8 *C 21.575 72.080 +*N mux_tree_tapbuf_size2_15_sram[0]:9 *C 21.620 72.125 +*N mux_tree_tapbuf_size2_15_sram[0]:10 *C 21.620 74.415 +*N mux_tree_tapbuf_size2_15_sram[0]:11 *C 21.620 74.460 +*N mux_tree_tapbuf_size2_15_sram[0]:12 *C 21.620 74.800 +*N mux_tree_tapbuf_size2_15_sram[0]:13 *C 35.835 74.800 +*N mux_tree_tapbuf_size2_15_sram[0]:14 *C 35.880 74.755 +*N mux_tree_tapbuf_size2_15_sram[0]:15 *C 35.880 72.465 +*N mux_tree_tapbuf_size2_15_sram[0]:16 *C 35.880 72.420 +*N mux_tree_tapbuf_size2_15_sram[0]:17 *C 36.095 72.420 + +*CAP +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_13\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_15_sram[0]:3 5.422548e-05 +4 mux_tree_tapbuf_size2_15_sram[0]:4 0.0003215743 +5 mux_tree_tapbuf_size2_15_sram[0]:5 0.0003495907 +6 mux_tree_tapbuf_size2_15_sram[0]:6 0.0001254308 +7 mux_tree_tapbuf_size2_15_sram[0]:7 0.000360571 +8 mux_tree_tapbuf_size2_15_sram[0]:8 0.000235467 +9 mux_tree_tapbuf_size2_15_sram[0]:9 0.0001437178 +10 mux_tree_tapbuf_size2_15_sram[0]:10 0.0001437178 +11 mux_tree_tapbuf_size2_15_sram[0]:11 6.16535e-05 +12 mux_tree_tapbuf_size2_15_sram[0]:12 0.0004711126 +13 mux_tree_tapbuf_size2_15_sram[0]:13 0.0004427477 +14 mux_tree_tapbuf_size2_15_sram[0]:14 0.0001179277 +15 mux_tree_tapbuf_size2_15_sram[0]:15 0.0001179277 +16 mux_tree_tapbuf_size2_15_sram[0]:16 5.210963e-05 +17 mux_tree_tapbuf_size2_15_sram[0]:17 4.819793e-05 +18 mux_tree_tapbuf_size2_15_sram[0]:13 chany_top_in[1]:7 0.0003552328 +19 mux_tree_tapbuf_size2_15_sram[0]:14 chany_top_in[1]:10 2.032925e-06 +20 mux_tree_tapbuf_size2_15_sram[0]:15 chany_top_in[1]:9 2.032925e-06 +21 mux_tree_tapbuf_size2_15_sram[0]:12 chany_top_in[1]:6 0.0003552328 +22 mux_tree_tapbuf_size2_15_sram[0]:13 chanx_left_in[4]:2 0.0002508682 +23 mux_tree_tapbuf_size2_15_sram[0]:12 chanx_left_in[4]:3 0.0002508682 +24 mux_tree_tapbuf_size2_15_sram[0]:8 chanx_left_in[7]:9 6.323623e-05 +25 mux_tree_tapbuf_size2_15_sram[0]:14 chanx_left_in[7]:7 2.250488e-05 +26 mux_tree_tapbuf_size2_15_sram[0]:15 chanx_left_in[7]:8 2.250488e-05 +27 mux_tree_tapbuf_size2_15_sram[0]:4 chanx_left_in[7]:10 0.0002510672 +28 mux_tree_tapbuf_size2_15_sram[0]:5 chanx_left_in[7]:9 0.0002510672 +29 mux_tree_tapbuf_size2_15_sram[0]:6 chanx_left_in[7]:10 2.289215e-05 +30 mux_tree_tapbuf_size2_15_sram[0]:7 chanx_left_in[7]:9 2.289215e-05 +31 mux_tree_tapbuf_size2_15_sram[0]:7 chanx_left_in[7]:10 6.323623e-05 +32 mux_tree_tapbuf_size2_15_sram[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 2.578672e-06 +33 mux_tree_tapbuf_size2_15_sram[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 2.578672e-06 +34 mux_tree_tapbuf_size2_15_sram[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 6.717608e-05 +35 mux_tree_tapbuf_size2_15_sram[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 6.717608e-05 + +*RES +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_15_sram[0]:17 0.152 +1 mux_tree_tapbuf_size2_15_sram[0]:8 mux_tree_tapbuf_size2_15_sram[0]:7 0.003566965 +2 mux_tree_tapbuf_size2_15_sram[0]:9 mux_tree_tapbuf_size2_15_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size2_15_sram[0]:11 mux_tree_tapbuf_size2_15_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size2_15_sram[0]:10 mux_tree_tapbuf_size2_15_sram[0]:9 0.002044643 +5 mux_tree_tapbuf_size2_15_sram[0]:13 mux_tree_tapbuf_size2_15_sram[0]:12 0.01269197 +6 mux_tree_tapbuf_size2_15_sram[0]:14 mux_tree_tapbuf_size2_15_sram[0]:13 0.0045 +7 mux_tree_tapbuf_size2_15_sram[0]:16 mux_tree_tapbuf_size2_15_sram[0]:15 0.0045 +8 mux_tree_tapbuf_size2_15_sram[0]:15 mux_tree_tapbuf_size2_15_sram[0]:14 0.002044643 +9 mux_tree_tapbuf_size2_15_sram[0]:17 mux_tree_tapbuf_size2_15_sram[0]:16 0.0001168478 +10 mux_tree_tapbuf_size2_15_sram[0]:4 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size2_15_sram[0]:3 mux_left_track_13\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size2_15_sram[0]:5 mux_tree_tapbuf_size2_15_sram[0]:4 0.005970983 +13 mux_tree_tapbuf_size2_15_sram[0]:6 mux_tree_tapbuf_size2_15_sram[0]:5 0.0003035715 +14 mux_tree_tapbuf_size2_15_sram[0]:7 mux_tree_tapbuf_size2_15_sram[0]:6 0.002142857 +15 mux_tree_tapbuf_size2_15_sram[0]:7 mux_tree_tapbuf_size2_15_sram[0]:3 0.0001271552 +16 mux_tree_tapbuf_size2_15_sram[0]:12 mux_tree_tapbuf_size2_15_sram[0]:11 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.001606925 //LENGTH 13.510 LUMPCC 0 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 53.665 66.300 +*I mux_top_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 51.420 69.360 +*I mem_top_track_16\/FTB_16__21:A I *L 0.001746 *C 50.600 74.800 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 50.638 74.800 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 51.475 74.800 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 51.520 74.755 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 51.420 69.360 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 51.520 69.020 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 51.520 69.020 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 51.980 69.020 +*N mux_tree_tapbuf_size2_3_sram[1]:10 *C 51.980 66.345 +*N mux_tree_tapbuf_size2_3_sram[1]:11 *C 52.025 66.300 +*N mux_tree_tapbuf_size2_3_sram[1]:12 *C 53.628 66.300 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_16\/FTB_16__21:A 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 6.6817e-05 +4 mux_tree_tapbuf_size2_3_sram[1]:4 6.6817e-05 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0003261397 +6 mux_tree_tapbuf_size2_3_sram[1]:6 6.790251e-05 +7 mux_tree_tapbuf_size2_3_sram[1]:7 7.234493e-05 +8 mux_tree_tapbuf_size2_3_sram[1]:8 0.0003601453 +9 mux_tree_tapbuf_size2_3_sram[1]:9 0.0002177557 +10 mux_tree_tapbuf_size2_3_sram[1]:10 0.0001837501 +11 mux_tree_tapbuf_size2_3_sram[1]:11 0.0001211262 +12 mux_tree_tapbuf_size2_3_sram[1]:12 0.0001211262 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:4 mux_tree_tapbuf_size2_3_sram[1]:3 0.0007477679 +2 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_3_sram[1]:3 mem_top_track_16\/FTB_16__21:A 0.152 +4 mux_tree_tapbuf_size2_3_sram[1]:6 mux_top_track_16\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.0001847826 +6 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:5 0.005120536 +8 mux_tree_tapbuf_size2_3_sram[1]:11 mux_tree_tapbuf_size2_3_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size2_3_sram[1]:10 mux_tree_tapbuf_size2_3_sram[1]:9 0.002388393 +10 mux_tree_tapbuf_size2_3_sram[1]:12 mux_tree_tapbuf_size2_3_sram[1]:11 0.001430804 +11 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[1] 0.001370055 //LENGTH 8.820 LUMPCC 0.0003288627 DR + +*CONN +*I mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.045 93.840 +*I mux_top_track_26\/mux_l2_in_0_:S I *L 0.00357 *C 54.640 96.270 +*I mem_top_track_26\/FTB_20__25:A I *L 0.001746 *C 50.600 96.560 +*N mux_tree_tapbuf_size2_7_sram[1]:3 *C 50.638 96.560 +*N mux_tree_tapbuf_size2_7_sram[1]:4 *C 54.602 96.560 +*N mux_tree_tapbuf_size2_7_sram[1]:5 *C 54.640 96.270 +*N mux_tree_tapbuf_size2_7_sram[1]:6 *C 54.640 95.880 +*N mux_tree_tapbuf_size2_7_sram[1]:7 *C 55.155 95.880 +*N mux_tree_tapbuf_size2_7_sram[1]:8 *C 55.200 95.835 +*N mux_tree_tapbuf_size2_7_sram[1]:9 *C 55.200 93.885 +*N mux_tree_tapbuf_size2_7_sram[1]:10 *C 55.200 93.840 +*N mux_tree_tapbuf_size2_7_sram[1]:11 *C 55.045 93.840 + +*CAP +0 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_26\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_26\/FTB_20__25:A 1e-06 +3 mux_tree_tapbuf_size2_7_sram[1]:3 0.0002196453 +4 mux_tree_tapbuf_size2_7_sram[1]:4 0.0002529268 +5 mux_tree_tapbuf_size2_7_sram[1]:5 9.90574e-05 +6 mux_tree_tapbuf_size2_7_sram[1]:6 8.585305e-05 +7 mux_tree_tapbuf_size2_7_sram[1]:7 5.230775e-05 +8 mux_tree_tapbuf_size2_7_sram[1]:8 0.0001129622 +9 mux_tree_tapbuf_size2_7_sram[1]:9 0.0001129622 +10 mux_tree_tapbuf_size2_7_sram[1]:10 5.367254e-05 +11 mux_tree_tapbuf_size2_7_sram[1]:11 4.880466e-05 +12 mux_tree_tapbuf_size2_7_sram[1]:3 optlc_net_108:34 0.0001035688 +13 mux_tree_tapbuf_size2_7_sram[1]:4 optlc_net_108:32 0.0001035688 +14 mux_tree_tapbuf_size2_7_sram[1]:8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.086256e-05 +15 mux_tree_tapbuf_size2_7_sram[1]:9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.086256e-05 + +*RES +0 mem_top_track_26\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_7_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_7_sram[1]:7 mux_tree_tapbuf_size2_7_sram[1]:6 0.0004598215 +2 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size2_7_sram[1]:10 mux_tree_tapbuf_size2_7_sram[1]:9 0.0045 +4 mux_tree_tapbuf_size2_7_sram[1]:9 mux_tree_tapbuf_size2_7_sram[1]:8 0.001741071 +5 mux_tree_tapbuf_size2_7_sram[1]:11 mux_tree_tapbuf_size2_7_sram[1]:10 8.423914e-05 +6 mux_tree_tapbuf_size2_7_sram[1]:3 mem_top_track_26\/FTB_20__25:A 0.152 +7 mux_tree_tapbuf_size2_7_sram[1]:5 mux_top_track_26\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_7_sram[1]:5 mux_tree_tapbuf_size2_7_sram[1]:4 0.000125 +9 mux_tree_tapbuf_size2_7_sram[1]:4 mux_tree_tapbuf_size2_7_sram[1]:3 0.003540179 +10 mux_tree_tapbuf_size2_7_sram[1]:6 mux_tree_tapbuf_size2_7_sram[1]:5 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_13_ccff_tail[0] 0.002648248 //LENGTH 18.900 LUMPCC 0.0005203521 DR + +*CONN +*I mem_top_track_38\/FTB_26__31:X O *L 0 *C 60.025 68.680 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.095 64.260 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 *C 47.095 64.260 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 *C 47.380 64.260 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 *C 47.380 64.305 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 *C 47.380 67.263 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 *C 47.388 67.320 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 *C 60.253 67.320 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 *C 60.260 67.377 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 *C 60.260 68.635 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:10 *C 60.260 68.680 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:11 *C 60.025 68.680 + +*CAP +0 mem_top_track_38\/FTB_26__31:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 4.83318e-05 +3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 5.262317e-05 +4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 0.0001799553 +5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 0.0001799553 +6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 0.0006842501 +7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 0.0006842501 +8 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 9.016581e-05 +9 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 9.016581e-05 +10 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:10 5.830932e-05 +11 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:11 5.788918e-05 +12 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 chanx_left_in[1]:4 4.431534e-09 +13 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 chanx_left_in[1]:5 4.431534e-09 +14 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 chanx_left_in[1]:6 0.0001863232 +15 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 chanx_left_in[1]:7 0.0001863232 +16 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 optlc_net_108:55 7.384837e-05 +17 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 optlc_net_108:54 7.384837e-05 + +*RES +0 mem_top_track_38\/FTB_26__31:X mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:11 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:10 0.0001277174 +2 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:10 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 0.001122768 +4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 0.00341 +5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 0.002015517 +6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 0.002640625 +7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 0.00341 +8 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 0.0001548913 +9 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.002161983 //LENGTH 18.740 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 74.825 47.600 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 82.240 44.880 +*I mux_top_track_8\/mux_l1_in_1_:S I *L 0.00357 *C 76.720 41.480 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 77.915 39.100 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 77.915 39.100 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 77.740 39.100 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 77.740 39.145 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 76.758 41.480 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 77.695 41.480 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 77.740 41.480 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 82.203 44.880 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 77.785 44.880 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 77.740 44.880 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 77.740 47.215 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 77.695 47.260 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 75.440 47.260 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 75.440 47.600 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 74.862 47.600 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_8\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 4.620141e-05 +5 mux_tree_tapbuf_size3_0_sram[0]:5 5.029573e-05 +6 mux_tree_tapbuf_size3_0_sram[0]:6 0.0001262696 +7 mux_tree_tapbuf_size3_0_sram[0]:7 8.092082e-05 +8 mux_tree_tapbuf_size3_0_sram[0]:8 8.092082e-05 +9 mux_tree_tapbuf_size3_0_sram[0]:9 0.0003161552 +10 mux_tree_tapbuf_size3_0_sram[0]:10 0.0002772238 +11 mux_tree_tapbuf_size3_0_sram[0]:11 0.0002772238 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0003218534 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0001289928 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0001431376 +15 mux_tree_tapbuf_size3_0_sram[0]:15 0.000168871 +16 mux_tree_tapbuf_size3_0_sram[0]:16 8.282515e-05 +17 mux_tree_tapbuf_size3_0_sram[0]:17 5.709175e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:17 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 9.51087e-05 +2 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size3_0_sram[0]:4 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.0045 +5 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.002084821 +6 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.0005156251 +7 mux_tree_tapbuf_size3_0_sram[0]:8 mux_tree_tapbuf_size3_0_sram[0]:7 0.0008370536 +8 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:6 0.002084821 +10 mux_tree_tapbuf_size3_0_sram[0]:7 mux_top_track_8\/mux_l1_in_1_:S 0.152 +11 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.003944197 +12 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.0045 +13 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:9 0.003035714 +14 mux_tree_tapbuf_size3_0_sram[0]:10 mux_top_track_8\/mux_l1_in_0_:S 0.152 +15 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0003035715 +16 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.002013393 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[1] 0.00236311 //LENGTH 16.720 LUMPCC 0.0003529846 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.945 49.980 +*I mux_top_track_6\/mux_l2_in_0_:S I *L 0.00357 *C 58.320 46.920 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 60.435 44.540 +*I mux_top_track_6\/mux_l2_in_1_:S I *L 0.00357 *C 56.940 42.160 +*N mux_tree_tapbuf_size5_1_sram[1]:4 *C 56.978 42.160 +*N mux_tree_tapbuf_size5_1_sram[1]:5 *C 60.215 42.160 +*N mux_tree_tapbuf_size5_1_sram[1]:6 *C 60.260 42.205 +*N mux_tree_tapbuf_size5_1_sram[1]:7 *C 60.435 44.540 +*N mux_tree_tapbuf_size5_1_sram[1]:8 *C 60.260 44.540 +*N mux_tree_tapbuf_size5_1_sram[1]:9 *C 60.260 44.540 +*N mux_tree_tapbuf_size5_1_sram[1]:10 *C 58.408 46.920 +*N mux_tree_tapbuf_size5_1_sram[1]:11 *C 60.215 46.920 +*N mux_tree_tapbuf_size5_1_sram[1]:12 *C 60.260 46.920 +*N mux_tree_tapbuf_size5_1_sram[1]:13 *C 60.720 46.920 +*N mux_tree_tapbuf_size5_1_sram[1]:14 *C 60.720 49.935 +*N mux_tree_tapbuf_size5_1_sram[1]:15 *C 60.765 49.980 +*N mux_tree_tapbuf_size5_1_sram[1]:16 *C 61.908 49.980 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_6\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_6\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[1]:4 0.0002054715 +5 mux_tree_tapbuf_size5_1_sram[1]:5 0.0002054715 +6 mux_tree_tapbuf_size5_1_sram[1]:6 0.0001494215 +7 mux_tree_tapbuf_size5_1_sram[1]:7 5.901042e-05 +8 mux_tree_tapbuf_size5_1_sram[1]:8 6.227252e-05 +9 mux_tree_tapbuf_size5_1_sram[1]:9 0.0003282427 +10 mux_tree_tapbuf_size5_1_sram[1]:10 0.0001267178 +11 mux_tree_tapbuf_size5_1_sram[1]:11 0.0001267178 +12 mux_tree_tapbuf_size5_1_sram[1]:12 0.000176687 +13 mux_tree_tapbuf_size5_1_sram[1]:13 0.0002109156 +14 mux_tree_tapbuf_size5_1_sram[1]:14 0.0001833346 +15 mux_tree_tapbuf_size5_1_sram[1]:15 8.593129e-05 +16 mux_tree_tapbuf_size5_1_sram[1]:16 8.593129e-05 +17 mux_tree_tapbuf_size5_1_sram[1]:11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.124697e-05 +18 mux_tree_tapbuf_size5_1_sram[1]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.105653e-06 +19 mux_tree_tapbuf_size5_1_sram[1]:10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.124697e-05 +20 mux_tree_tapbuf_size5_1_sram[1]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.105653e-06 +21 mux_tree_tapbuf_size5_1_sram[1]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001020527 +22 mux_tree_tapbuf_size5_1_sram[1]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.553625e-06 +23 mux_tree_tapbuf_size5_1_sram[1]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001020527 +24 mux_tree_tapbuf_size5_1_sram[1]:12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.385787e-06 +25 mux_tree_tapbuf_size5_1_sram[1]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.553625e-06 +26 mux_tree_tapbuf_size5_1_sram[1]:9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.385787e-06 +27 mux_tree_tapbuf_size5_1_sram[1]:14 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.147552e-06 +28 mux_tree_tapbuf_size5_1_sram[1]:13 mux_top_track_6/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.147552e-06 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size5_1_sram[1]:5 mux_tree_tapbuf_size5_1_sram[1]:4 0.002890625 +2 mux_tree_tapbuf_size5_1_sram[1]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size5_1_sram[1]:4 mux_top_track_6\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size5_1_sram[1]:11 mux_tree_tapbuf_size5_1_sram[1]:10 0.001613839 +5 mux_tree_tapbuf_size5_1_sram[1]:12 mux_tree_tapbuf_size5_1_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size5_1_sram[1]:12 mux_tree_tapbuf_size5_1_sram[1]:9 0.002125 +7 mux_tree_tapbuf_size5_1_sram[1]:10 mux_top_track_6\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_1_sram[1]:8 mux_tree_tapbuf_size5_1_sram[1]:7 9.51087e-05 +9 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:8 0.0045 +10 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:6 0.002084821 +11 mux_tree_tapbuf_size5_1_sram[1]:7 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size5_1_sram[1]:15 mux_tree_tapbuf_size5_1_sram[1]:14 0.0045 +13 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:13 0.002691964 +14 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:15 0.001020089 +15 mux_tree_tapbuf_size5_1_sram[1]:13 mux_tree_tapbuf_size5_1_sram[1]:12 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.003738261 //LENGTH 32.240 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 79.425 49.980 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 76.720 61.200 +*I mux_top_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 80.400 66.640 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.155 58.820 +*I mux_top_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 81.520 47.260 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 81.535 47.260 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 81.858 47.260 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 81.880 47.305 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 81.880 49.935 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 81.835 49.980 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 75.193 58.820 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 80.362 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 76.865 66.640 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 76.820 66.595 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 76.720 61.200 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 76.820 61.200 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 76.820 58.865 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 76.820 58.820 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 78.155 58.820 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 78.200 58.775 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 78.200 50.025 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 78.245 49.980 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 79.425 49.980 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:S 1e-06 +3 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_4\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 4.922582e-05 +6 mux_tree_tapbuf_size6_1_sram[0]:6 4.922582e-05 +7 mux_tree_tapbuf_size6_1_sram[0]:7 0.0001604785 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0001604785 +9 mux_tree_tapbuf_size6_1_sram[0]:9 0.0001399671 +10 mux_tree_tapbuf_size6_1_sram[0]:10 0.0001118952 +11 mux_tree_tapbuf_size6_1_sram[0]:11 0.0002942889 +12 mux_tree_tapbuf_size6_1_sram[0]:12 0.0002942889 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0002999757 +14 mux_tree_tapbuf_size6_1_sram[0]:14 2.677023e-05 +15 mux_tree_tapbuf_size6_1_sram[0]:15 0.0004611505 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.0001306394 +17 mux_tree_tapbuf_size6_1_sram[0]:17 0.0002316776 +18 mux_tree_tapbuf_size6_1_sram[0]:18 8.868108e-05 +19 mux_tree_tapbuf_size6_1_sram[0]:19 0.0004542529 +20 mux_tree_tapbuf_size6_1_sram[0]:20 0.0004542529 +21 mux_tree_tapbuf_size6_1_sram[0]:21 7.932667e-05 +22 mux_tree_tapbuf_size6_1_sram[0]:22 0.0002466851 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:22 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.0045 +2 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.0078125 +3 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[0]:17 0.001191964 +4 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.0045 +5 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:16 0.0045 +6 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:10 0.001453125 +7 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.002084821 +8 mux_tree_tapbuf_size6_1_sram[0]:10 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:21 0.001053571 +10 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:9 0.002151786 +11 mux_tree_tapbuf_size6_1_sram[0]:9 mux_tree_tapbuf_size6_1_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.002348214 +13 mux_tree_tapbuf_size6_1_sram[0]:6 mux_tree_tapbuf_size6_1_sram[0]:5 0.0001752717 +14 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.0045 +15 mux_tree_tapbuf_size6_1_sram[0]:5 mux_top_track_4\/mux_l1_in_2_:S 0.152 +16 mux_tree_tapbuf_size6_1_sram[0]:12 mux_tree_tapbuf_size6_1_sram[0]:11 0.003122768 +17 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.0045 +18 mux_tree_tapbuf_size6_1_sram[0]:11 mux_top_track_4\/mux_l1_in_1_:S 0.152 +19 mux_tree_tapbuf_size6_1_sram[0]:14 mux_top_track_4\/mux_l1_in_0_:S 0.152 +20 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.0045 +21 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:13 0.004816964 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009210785 //LENGTH 7.410 LUMPCC 0.0003035604 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_1_:X O *L 0 *C 81.245 65.960 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 81.135 60.860 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 81.098 60.860 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 80.545 60.860 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 80.500 60.905 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 80.500 65.915 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 80.545 65.960 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 81.208 65.960 + +*CAP +0 mux_top_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.009424e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.009424e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000185822 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000185822 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.184282e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.184282e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_right_grid_pin_1_[0]:11 0.0001454107 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_right_grid_pin_1_[0]:14 6.369508e-06 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_right_grid_pin_1_[0]:15 0.0001454107 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_right_grid_pin_1_[0]:15 6.369508e-06 + +*RES +0 mux_top_track_4\/mux_l1_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005915178 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001816974 //LENGTH 13.680 LUMPCC 0.0002079935 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_2_:X O *L 0 *C 25.935 37.400 +*I mux_left_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 17.940 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 17.940 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.940 41.775 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.940 39.825 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.985 39.780 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 23.415 39.780 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 23.460 39.735 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 23.460 37.445 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 23.505 37.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 25.898 37.400 + +*CAP +0 mux_left_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.258487e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001354366 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001354366 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003799751 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003799751 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001489727 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001489727 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001228137 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001228137 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 left_bottom_grid_pin_1_[0]:9 0.0001039967 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 left_bottom_grid_pin_1_[0]:10 0.0001039967 + +*RES +0 mux_left_track_5\/mux_l1_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.002136161 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.002044643 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.004848215 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001741071 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A1 0.152 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0006311877 //LENGTH 4.705 LUMPCC 0.0001207052 DR + +*CONN +*I mux_top_track_6\/mux_l2_in_0_:X O *L 0 *C 59.165 47.260 +*I mux_top_track_6\/mux_l3_in_0_:A1 I *L 0.00198 *C 63.580 47.260 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 63.543 47.260 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 59.203 47.260 + +*CAP +0 mux_top_track_6\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_6\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002542412 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002542412 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:11 5.124697e-05 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:13 9.105653e-06 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:10 5.124697e-05 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:12 9.105653e-06 + +*RES +0 mux_top_track_6\/mux_l2_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_6\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003875 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008810242 //LENGTH 6.600 LUMPCC 0.0002663521 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_0_:X O *L 0 *C 29.615 65.960 +*I mux_left_track_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.965 61.540 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 27.965 61.540 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.060 61.585 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.060 65.915 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.105 65.960 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 29.578 65.960 + +*CAP +0 mux_left_track_7\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.026499e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001717868 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001717868 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001194167 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001194167 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001205031 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.267298e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001205031 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.267298e-05 + +*RES +0 mux_left_track_7\/mux_l1_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_7\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001047676 //LENGTH 7.335 LUMPCC 0.0002053562 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_1_:X O *L 0 *C 37.545 36.040 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.005103 *C 41.400 38.590 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 41.363 38.590 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 40.065 38.590 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 40.020 38.545 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 40.020 36.085 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 39.975 36.040 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 37.583 36.040 + +*CAP +0 mux_left_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001441755 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001441755 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001504437 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001504437 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001255407 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001255407 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 left_bottom_grid_pin_1_[0]:6 0.0001026781 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 left_bottom_grid_pin_1_[0]:5 0.0001026781 + +*RES +0 mux_left_track_9\/mux_l1_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002136161 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002196429 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001158482 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008615833 //LENGTH 6.955 LUMPCC 0.0001026214 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_0_:X O *L 0 *C 47.205 71.740 +*I mux_top_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 50.700 69.020 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 50.663 69.020 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 47.425 69.020 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 47.380 69.065 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 47.380 71.695 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 47.380 71.740 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 47.205 71.740 + +*CAP +0 mux_top_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002058346 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002058346 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001239548 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001239548 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.838863e-05 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.899457e-05 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_3_sram[0]:8 1.511224e-08 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_3_sram[0]:9 5.410455e-08 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_3_sram[0]:3 1.511224e-08 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_3_sram[0]:8 5.410455e-08 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_3_sram[0]:7 3.739079e-05 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 1.385068e-05 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_3_sram[0]:6 3.739079e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_3_sram[0]:4 1.385068e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002890625 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET optlc_net_110 0.009023051 //LENGTH 72.800 LUMPCC 9.644405e-05 DR + +*CONN +*I optlc_105:HI O *L 0 *C 60.720 42.500 +*I mux_top_track_10\/mux_l2_in_0_:A0 I *L 0.001631 *C 64.115 38.760 +*I mux_top_track_8\/mux_l1_in_1_:A0 I *L 0.001631 *C 75.615 42.840 +*I mux_top_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 81.135 55.420 +*I mux_top_track_12\/mux_l2_in_0_:A0 I *L 0.001631 *C 71.935 39.100 +*I mux_top_track_6\/mux_l2_in_1_:A0 I *L 0.001631 *C 55.835 42.500 +*I mux_top_track_14\/mux_l2_in_0_:A0 I *L 0.005103 *C 49.680 54.920 +*I mux_top_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 56.755 55.420 +*N optlc_net_110:8 *C 56.630 55.420 +*N optlc_net_110:9 *C 49.718 54.920 +*N optlc_net_110:10 *C 52.855 54.920 +*N optlc_net_110:11 *C 52.900 54.965 +*N optlc_net_110:12 *C 52.900 55.375 +*N optlc_net_110:13 *C 52.945 55.420 +*N optlc_net_110:14 *C 56.535 55.420 +*N optlc_net_110:15 *C 56.580 55.375 +*N optlc_net_110:16 *C 56.580 42.885 +*N optlc_net_110:17 *C 56.580 42.840 +*N optlc_net_110:18 *C 55.873 42.500 +*N optlc_net_110:19 *C 56.580 42.500 +*N optlc_net_110:20 *C 71.935 39.100 +*N optlc_net_110:21 *C 81.098 55.420 +*N optlc_net_110:22 *C 73.185 55.420 +*N optlc_net_110:23 *C 73.140 55.375 +*N optlc_net_110:24 *C 75.578 42.840 +*N optlc_net_110:25 *C 73.185 42.840 +*N optlc_net_110:26 *C 73.140 42.840 +*N optlc_net_110:27 *C 73.140 41.480 +*N optlc_net_110:28 *C 72.680 41.480 +*N optlc_net_110:29 *C 72.680 38.805 +*N optlc_net_110:30 *C 72.635 38.760 +*N optlc_net_110:31 *C 71.935 38.760 +*N optlc_net_110:32 *C 64.115 38.760 +*N optlc_net_110:33 *C 60.765 38.760 +*N optlc_net_110:34 *C 60.720 38.805 +*N optlc_net_110:35 *C 60.720 42.455 +*N optlc_net_110:36 *C 60.683 42.500 + +*CAP +0 optlc_105:HI 1e-06 +1 mux_top_track_10\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_8\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_4\/mux_l2_in_1_:A0 1e-06 +4 mux_top_track_12\/mux_l2_in_0_:A0 1e-06 +5 mux_top_track_6\/mux_l2_in_1_:A0 1e-06 +6 mux_top_track_14\/mux_l2_in_0_:A0 1e-06 +7 mux_top_track_2\/mux_l2_in_1_:A0 1e-06 +8 optlc_net_110:8 2.424492e-05 +9 optlc_net_110:9 0.0002781244 +10 optlc_net_110:10 0.0002781244 +11 optlc_net_110:11 4.756666e-05 +12 optlc_net_110:12 4.756666e-05 +13 optlc_net_110:13 0.0002725718 +14 optlc_net_110:14 0.0002968167 +15 optlc_net_110:15 0.0007392577 +16 optlc_net_110:16 0.0007392577 +17 optlc_net_110:17 6.053555e-05 +18 optlc_net_110:18 5.989106e-05 +19 optlc_net_110:19 0.0003799636 +20 optlc_net_110:20 5.764078e-05 +21 optlc_net_110:21 0.0004624659 +22 optlc_net_110:22 0.0004624659 +23 optlc_net_110:23 0.0006882064 +24 optlc_net_110:24 0.0001799584 +25 optlc_net_110:25 0.0001799584 +26 optlc_net_110:26 0.0007983968 +27 optlc_net_110:27 0.00010269 +28 optlc_net_110:28 0.0001936441 +29 optlc_net_110:29 0.0001711014 +30 optlc_net_110:30 5.355017e-05 +31 optlc_net_110:31 0.0005679862 +32 optlc_net_110:32 0.0007557506 +33 optlc_net_110:33 0.0002436495 +34 optlc_net_110:34 0.000242607 +35 optlc_net_110:35 0.000242607 +36 optlc_net_110:36 0.0002920072 +37 optlc_net_110:30 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.267354e-06 +38 optlc_net_110:29 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.678639e-05 +39 optlc_net_110:31 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.267354e-06 +40 optlc_net_110:28 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.168281e-06 +41 optlc_net_110:28 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.678639e-05 +42 optlc_net_110:27 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.168281e-06 + +*RES +0 optlc_105:HI optlc_net_110:36 0.152 +1 optlc_net_110:33 optlc_net_110:32 0.002991071 +2 optlc_net_110:34 optlc_net_110:33 0.0045 +3 optlc_net_110:36 optlc_net_110:35 0.0045 +4 optlc_net_110:36 optlc_net_110:19 0.003662946 +5 optlc_net_110:35 optlc_net_110:34 0.003258929 +6 optlc_net_110:30 optlc_net_110:29 0.0045 +7 optlc_net_110:29 optlc_net_110:28 0.002388393 +8 optlc_net_110:25 optlc_net_110:24 0.002136161 +9 optlc_net_110:26 optlc_net_110:25 0.0045 +10 optlc_net_110:26 optlc_net_110:23 0.01119197 +11 optlc_net_110:24 mux_top_track_8\/mux_l1_in_1_:A0 0.152 +12 optlc_net_110:9 mux_top_track_14\/mux_l2_in_0_:A0 0.152 +13 optlc_net_110:10 optlc_net_110:9 0.002801339 +14 optlc_net_110:11 optlc_net_110:10 0.0045 +15 optlc_net_110:13 optlc_net_110:12 0.0045 +16 optlc_net_110:12 optlc_net_110:11 0.0003660714 +17 optlc_net_110:20 mux_top_track_12\/mux_l2_in_0_:A0 0.152 +18 optlc_net_110:18 mux_top_track_6\/mux_l2_in_1_:A0 0.152 +19 optlc_net_110:8 mux_top_track_2\/mux_l2_in_1_:A0 0.152 +20 optlc_net_110:17 optlc_net_110:16 0.0045 +21 optlc_net_110:16 optlc_net_110:15 0.01115179 +22 optlc_net_110:14 optlc_net_110:13 0.003205357 +23 optlc_net_110:14 optlc_net_110:8 8.482143e-05 +24 optlc_net_110:15 optlc_net_110:14 0.0045 +25 optlc_net_110:22 optlc_net_110:21 0.007064732 +26 optlc_net_110:23 optlc_net_110:22 0.0045 +27 optlc_net_110:21 mux_top_track_4\/mux_l2_in_1_:A0 0.152 +28 optlc_net_110:32 mux_top_track_10\/mux_l2_in_0_:A0 0.152 +29 optlc_net_110:32 optlc_net_110:31 0.006982143 +30 optlc_net_110:19 optlc_net_110:18 0.0006316964 +31 optlc_net_110:19 optlc_net_110:17 0.0003035715 +32 optlc_net_110:31 optlc_net_110:30 0.0006250001 +33 optlc_net_110:31 optlc_net_110:20 0.0003035715 +34 optlc_net_110:28 optlc_net_110:27 0.0004107143 +35 optlc_net_110:27 optlc_net_110:26 0.001214286 + +*END + +*D_NET mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005003721 //LENGTH 24.625 LUMPCC 0.002907013 DR + +*CONN +*I mux_left_track_27\/mux_l2_in_0_:X O *L 0 *C 33.295 64.260 +*I mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 15.325 69.495 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 15.363 69.405 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 16.515 69.360 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 16.560 69.315 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 16.560 65.338 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 16.568 65.280 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 30.812 65.280 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 30.820 65.222 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 30.820 64.305 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 30.865 64.260 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 33.258 64.260 + +*CAP +0 mux_left_track_27\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.396943e-05 +3 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.396943e-05 +4 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002851607 +5 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002851607 +6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003555121 +7 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003555121 +8 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.223123e-05 +9 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 9.223123e-05 +10 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002204802 +11 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002204802 +12 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[13]:5 0.000802532 +13 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[13]:6 0.000802532 +14 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[1]:7 0.0006509745 +15 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[1]:6 0.0006509745 + +*RES +0 mux_left_track_27\/mux_l2_in_0_:X mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_27\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001029018 +3 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003551339 +5 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002231717 +8 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0008191965 +10 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002136161 + +*END + +*D_NET chany_top_in[8] 0.01129621 //LENGTH 85.645 LUMPCC 0.004482717 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 72.220 102.035 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 48.665 41.820 +*N chany_top_in[8]:2 *C 48.703 41.820 +*N chany_top_in[8]:3 *C 49.175 41.820 +*N chany_top_in[8]:4 *C 49.220 41.865 +*N chany_top_in[8]:5 *C 49.220 44.823 +*N chany_top_in[8]:6 *C 49.227 44.880 +*N chany_top_in[8]:7 *C 65.300 44.880 +*N chany_top_in[8]:8 *C 65.320 44.888 +*N chany_top_in[8]:9 *C 65.320 94.715 +*N chany_top_in[8]:10 *C 65.320 101.312 +*N chany_top_in[8]:11 *C 65.340 101.320 +*N chany_top_in[8]:12 *C 72.213 101.320 +*N chany_top_in[8]:13 *C 72.220 101.378 + +*CAP +0 chany_top_in[8] 4.016529e-05 +1 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[8]:2 6.085378e-05 +3 chany_top_in[8]:3 6.085378e-05 +4 chany_top_in[8]:4 0.0001370071 +5 chany_top_in[8]:5 0.0001370071 +6 chany_top_in[8]:6 0.0008278512 +7 chany_top_in[8]:7 0.0008278512 +8 chany_top_in[8]:8 0.001530616 +9 chany_top_in[8]:9 0.001844828 +10 chany_top_in[8]:10 0.0003142119 +11 chany_top_in[8]:11 0.0004955432 +12 chany_top_in[8]:12 0.0004955432 +13 chany_top_in[8]:13 4.016529e-05 +14 chany_top_in[8]:6 chany_top_in[5]:18 0.0005029559 +15 chany_top_in[8]:7 chany_top_in[5]:19 0.0005029559 +16 chany_top_in[8]:8 chany_top_in[9]:9 0.0006506511 +17 chany_top_in[8]:8 chany_top_in[9]:10 0.000293876 +18 chany_top_in[8]:11 chany_top_in[9]:12 2.660829e-06 +19 chany_top_in[8]:10 chany_top_in[9]:11 6.587871e-05 +20 chany_top_in[8]:12 chany_top_in[9]:13 2.660829e-06 +21 chany_top_in[8]:9 chany_top_in[9]:11 0.000293876 +22 chany_top_in[8]:9 chany_top_in[9]:10 0.0007165298 +23 chany_top_in[8] chany_top_in[10] 1.397301e-05 +24 chany_top_in[8]:8 chany_top_in[10]:7 0.0004874576 +25 chany_top_in[8]:8 chany_top_in[10]:8 0.0001426931 +26 chany_top_in[8]:11 chany_top_in[10]:10 9.124976e-06 +27 chany_top_in[8]:10 chany_top_in[10]:9 3.252668e-05 +28 chany_top_in[8]:13 chany_top_in[10]:12 1.397301e-05 +29 chany_top_in[8]:12 chany_top_in[10]:11 9.124976e-06 +30 chany_top_in[8]:9 chany_top_in[10]:9 0.0001426931 +31 chany_top_in[8]:9 chany_top_in[10]:8 0.0005199843 +32 chany_top_in[8]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 3.95606e-05 +33 chany_top_in[8]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 3.95606e-05 + +*RES +0 chany_top_in[8] chany_top_in[8]:13 0.0005870535 +1 chany_top_in[8]:2 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[8]:3 chany_top_in[8]:2 0.000421875 +3 chany_top_in[8]:4 chany_top_in[8]:3 0.0045 +4 chany_top_in[8]:5 chany_top_in[8]:4 0.002640625 +5 chany_top_in[8]:6 chany_top_in[8]:5 0.00341 +6 chany_top_in[8]:7 chany_top_in[8]:6 0.002518025 +7 chany_top_in[8]:8 chany_top_in[8]:7 0.00341 +8 chany_top_in[8]:11 chany_top_in[8]:10 0.00341 +9 chany_top_in[8]:10 chany_top_in[8]:9 0.001033608 +10 chany_top_in[8]:13 chany_top_in[8]:12 0.00341 +11 chany_top_in[8]:12 chany_top_in[8]:11 0.001076692 +12 chany_top_in[8]:9 chany_top_in[8]:8 0.007806308 + +*END + +*D_NET chanx_left_in[12] 0.01074787 //LENGTH 80.755 LUMPCC 0.004486396 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 36.720 +*I mux_top_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 45.255 71.740 +*N chanx_left_in[12]:2 *C 44.680 68.000 +*N chanx_left_in[12]:3 *C 45.255 71.740 +*N chanx_left_in[12]:4 *C 45.080 71.740 +*N chanx_left_in[12]:5 *C 45.080 71.695 +*N chanx_left_in[12]:6 *C 45.080 68.058 +*N chanx_left_in[12]:7 *C 45.080 68.000 +*N chanx_left_in[12]:8 *C 45.080 67.993 +*N chanx_left_in[12]:9 *C 45.080 36.727 +*N chanx_left_in[12]:10 *C 45.060 36.720 + +*CAP +0 chanx_left_in[12] 0.001827752 +1 mux_top_track_16\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[12]:2 8.151507e-05 +3 chanx_left_in[12]:3 5.719189e-05 +4 chanx_left_in[12]:4 6.097767e-05 +5 chanx_left_in[12]:5 0.0002084969 +6 chanx_left_in[12]:6 0.0002084969 +7 chanx_left_in[12]:7 8.151507e-05 +8 chanx_left_in[12]:8 0.0009533879 +9 chanx_left_in[12]:9 0.0009533879 +10 chanx_left_in[12]:10 0.001827752 +11 chanx_left_in[12] chany_top_in[11]:5 0.0005696454 +12 chanx_left_in[12]:8 chany_top_in[11]:8 0.0005993988 +13 chanx_left_in[12]:10 chany_top_in[11]:6 0.0005696454 +14 chanx_left_in[12]:9 chany_top_in[11]:7 0.0005993988 +15 chanx_left_in[12] chanx_left_in[8] 5.246031e-06 +16 chanx_left_in[12]:8 chanx_left_in[8]:9 0.0005005286 +17 chanx_left_in[12]:10 chanx_left_in[8]:17 5.246031e-06 +18 chanx_left_in[12]:9 chanx_left_in[8]:10 0.0005005286 +19 chanx_left_in[12] left_top_grid_pin_48_[0]:15 0.0001028545 +20 chanx_left_in[12] left_top_grid_pin_48_[0]:16 0.0004655243 +21 chanx_left_in[12]:10 left_top_grid_pin_48_[0]:11 0.0004655243 +22 chanx_left_in[12]:10 left_top_grid_pin_48_[0]:16 0.0001028545 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:10 0.0068667 +1 chanx_left_in[12]:3 mux_top_track_16\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[12]:4 chanx_left_in[12]:3 9.51087e-05 +3 chanx_left_in[12]:5 chanx_left_in[12]:4 0.0045 +4 chanx_left_in[12]:6 chanx_left_in[12]:5 0.003247768 +5 chanx_left_in[12]:7 chanx_left_in[12]:6 0.00341 +6 chanx_left_in[12]:7 chanx_left_in[12]:2 5.69697e-05 +7 chanx_left_in[12]:8 chanx_left_in[12]:7 0.00341 +8 chanx_left_in[12]:10 chanx_left_in[12]:9 0.00341 +9 chanx_left_in[12]:9 chanx_left_in[12]:8 0.004898183 + +*END + +*D_NET chanx_left_in[17] 0.008158369 //LENGTH 79.185 LUMPCC 0.001069876 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 19.040 +*I mux_top_track_6\/mux_l2_in_1_:A1 I *L 0.00198 *C 56.220 41.820 +*N chanx_left_in[17]:2 *C 56.183 41.820 +*N chanx_left_in[17]:3 *C 52.945 41.820 +*N chanx_left_in[17]:4 *C 52.900 41.775 +*N chanx_left_in[17]:5 *C 52.900 19.777 +*N chanx_left_in[17]:6 *C 52.893 19.720 +*N chanx_left_in[17]:7 *C 39.100 19.720 +*N chanx_left_in[17]:8 *C 39.100 19.040 + +*CAP +0 chanx_left_in[17] 0.001557504 +1 mux_top_track_6\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[17]:2 0.0002238184 +3 chanx_left_in[17]:3 0.0002238184 +4 chanx_left_in[17]:4 0.001057834 +5 chanx_left_in[17]:5 0.001057834 +6 chanx_left_in[17]:6 0.0006597359 +7 chanx_left_in[17]:7 0.0007045895 +8 chanx_left_in[17]:8 0.001602358 +9 chanx_left_in[17] chany_top_in[6]:14 0.0001469313 +10 chanx_left_in[17]:6 chany_top_in[6]:15 0.0001301095 +11 chanx_left_in[17]:8 chany_top_in[6]:15 0.0001469313 +12 chanx_left_in[17]:7 chany_top_in[6]:14 0.0001301095 +13 chanx_left_in[17] chanx_left_out[10] 0.0002578972 +14 chanx_left_in[17]:8 chanx_left_out[10]:2 0.0002578972 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:8 0.005932966 +1 chanx_left_in[17]:2 mux_top_track_6\/mux_l2_in_1_:A1 0.152 +2 chanx_left_in[17]:3 chanx_left_in[17]:2 0.002890625 +3 chanx_left_in[17]:4 chanx_left_in[17]:3 0.0045 +4 chanx_left_in[17]:5 chanx_left_in[17]:4 0.01964063 +5 chanx_left_in[17]:6 chanx_left_in[17]:5 0.00341 +6 chanx_left_in[17]:8 chanx_left_in[17]:7 0.0001065333 +7 chanx_left_in[17]:7 chanx_left_in[17]:6 0.002160825 + +*END + +*D_NET left_top_grid_pin_47_[0] 0.01115865 //LENGTH 70.345 LUMPCC 0.003912931 DR + +*CONN +*P left_top_grid_pin_47_[0] I *L 0.29796 *C 3.220 74.870 +*I mux_left_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 23.175 71.740 +*I mux_left_track_7\/mux_l1_in_1_:A0 I *L 0.001631 *C 26.855 65.960 +*I mux_left_track_19\/mux_l1_in_0_:A0 I *L 0.001631 *C 21.335 37.400 +*N left_top_grid_pin_47_[0]:4 *C 22.600 63.240 +*N left_top_grid_pin_47_[0]:5 *C 21.297 37.400 +*N left_top_grid_pin_47_[0]:6 *C 19.365 37.400 +*N left_top_grid_pin_47_[0]:7 *C 19.320 37.445 +*N left_top_grid_pin_47_[0]:8 *C 19.320 40.742 +*N left_top_grid_pin_47_[0]:9 *C 19.328 40.800 +*N left_top_grid_pin_47_[0]:10 *C 22.980 40.800 +*N left_top_grid_pin_47_[0]:11 *C 23.000 40.808 +*N left_top_grid_pin_47_[0]:12 *C 23.000 63.233 +*N left_top_grid_pin_47_[0]:13 *C 23.000 63.240 +*N left_top_grid_pin_47_[0]:14 *C 23.000 63.298 +*N left_top_grid_pin_47_[0]:15 *C 26.818 65.960 +*N left_top_grid_pin_47_[0]:16 *C 23.045 65.960 +*N left_top_grid_pin_47_[0]:17 *C 23.000 65.960 +*N left_top_grid_pin_47_[0]:18 *C 23.175 71.740 +*N left_top_grid_pin_47_[0]:19 *C 23.000 71.740 +*N left_top_grid_pin_47_[0]:20 *C 23.000 71.740 +*N left_top_grid_pin_47_[0]:21 *C 23.000 73.383 +*N left_top_grid_pin_47_[0]:22 *C 22.992 73.440 +*N left_top_grid_pin_47_[0]:23 *C 3.228 73.440 +*N left_top_grid_pin_47_[0]:24 *C 3.220 73.498 + +*CAP +0 left_top_grid_pin_47_[0] 6.698447e-05 +1 mux_left_track_3\/mux_l1_in_1_:A0 1e-06 +2 mux_left_track_7\/mux_l1_in_1_:A0 1e-06 +3 mux_left_track_19\/mux_l1_in_0_:A0 1e-06 +4 left_top_grid_pin_47_[0]:4 8.603182e-05 +5 left_top_grid_pin_47_[0]:5 0.0001923545 +6 left_top_grid_pin_47_[0]:6 0.0001923545 +7 left_top_grid_pin_47_[0]:7 0.0002347475 +8 left_top_grid_pin_47_[0]:8 0.0002347475 +9 left_top_grid_pin_47_[0]:9 0.0002400971 +10 left_top_grid_pin_47_[0]:10 0.0002400971 +11 left_top_grid_pin_47_[0]:11 0.001365101 +12 left_top_grid_pin_47_[0]:12 0.001365101 +13 left_top_grid_pin_47_[0]:13 8.603182e-05 +14 left_top_grid_pin_47_[0]:14 0.0001609607 +15 left_top_grid_pin_47_[0]:15 0.0003255143 +16 left_top_grid_pin_47_[0]:16 0.0003255143 +17 left_top_grid_pin_47_[0]:17 0.0005001778 +18 left_top_grid_pin_47_[0]:18 5.62952e-05 +19 left_top_grid_pin_47_[0]:19 6.067116e-05 +20 left_top_grid_pin_47_[0]:20 0.0004505286 +21 left_top_grid_pin_47_[0]:21 0.0001112368 +22 left_top_grid_pin_47_[0]:22 0.0004405959 +23 left_top_grid_pin_47_[0]:23 0.0004405959 +24 left_top_grid_pin_47_[0]:24 6.698447e-05 +25 left_top_grid_pin_47_[0]:22 chanx_left_in[9]:7 0.001137837 +26 left_top_grid_pin_47_[0]:23 chanx_left_in[9]:8 0.001137837 +27 left_top_grid_pin_47_[0] left_top_grid_pin_44_[0] 2.32698e-05 +28 left_top_grid_pin_47_[0]:22 left_top_grid_pin_44_[0]:17 0.0007953587 +29 left_top_grid_pin_47_[0]:24 left_top_grid_pin_44_[0]:19 2.32698e-05 +30 left_top_grid_pin_47_[0]:23 left_top_grid_pin_44_[0]:18 0.0007953587 + +*RES +0 left_top_grid_pin_47_[0] left_top_grid_pin_47_[0]:24 0.001225446 +1 left_top_grid_pin_47_[0]:21 left_top_grid_pin_47_[0]:20 0.001466518 +2 left_top_grid_pin_47_[0]:22 left_top_grid_pin_47_[0]:21 0.00341 +3 left_top_grid_pin_47_[0]:24 left_top_grid_pin_47_[0]:23 0.00341 +4 left_top_grid_pin_47_[0]:23 left_top_grid_pin_47_[0]:22 0.003096516 +5 left_top_grid_pin_47_[0]:16 left_top_grid_pin_47_[0]:15 0.003368304 +6 left_top_grid_pin_47_[0]:17 left_top_grid_pin_47_[0]:16 0.0045 +7 left_top_grid_pin_47_[0]:17 left_top_grid_pin_47_[0]:14 0.002377233 +8 left_top_grid_pin_47_[0]:15 mux_left_track_7\/mux_l1_in_1_:A0 0.152 +9 left_top_grid_pin_47_[0]:19 left_top_grid_pin_47_[0]:18 9.510869e-05 +10 left_top_grid_pin_47_[0]:20 left_top_grid_pin_47_[0]:19 0.0045 +11 left_top_grid_pin_47_[0]:20 left_top_grid_pin_47_[0]:17 0.005160714 +12 left_top_grid_pin_47_[0]:18 mux_left_track_3\/mux_l1_in_1_:A0 0.152 +13 left_top_grid_pin_47_[0]:14 left_top_grid_pin_47_[0]:13 0.00341 +14 left_top_grid_pin_47_[0]:13 left_top_grid_pin_47_[0]:12 0.00341 +15 left_top_grid_pin_47_[0]:13 left_top_grid_pin_47_[0]:4 5.69697e-05 +16 left_top_grid_pin_47_[0]:12 left_top_grid_pin_47_[0]:11 0.00351325 +17 left_top_grid_pin_47_[0]:10 left_top_grid_pin_47_[0]:9 0.000572225 +18 left_top_grid_pin_47_[0]:11 left_top_grid_pin_47_[0]:10 0.00341 +19 left_top_grid_pin_47_[0]:8 left_top_grid_pin_47_[0]:7 0.002944197 +20 left_top_grid_pin_47_[0]:9 left_top_grid_pin_47_[0]:8 0.00341 +21 left_top_grid_pin_47_[0]:6 left_top_grid_pin_47_[0]:5 0.001725447 +22 left_top_grid_pin_47_[0]:7 left_top_grid_pin_47_[0]:6 0.0045 +23 left_top_grid_pin_47_[0]:5 mux_left_track_19\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_top_out[7] 0.006905718 //LENGTH 53.725 LUMPCC 0.001844319 DR + +*CONN +*I mux_top_track_14\/mux_l2_in_0_:X O *L 0 *C 44.840 56.440 +*P chany_top_out[7] O *L 0.7423 *C 50.140 102.070 +*N chany_top_out[7]:2 *C 50.140 101.378 +*N chany_top_out[7]:3 *C 50.143 101.320 +*N chany_top_out[7]:4 *C 50.585 101.320 +*N chany_top_out[7]:5 *C 50.600 101.312 +*N chany_top_out[7]:6 *C 50.600 59.168 +*N chany_top_out[7]:7 *C 50.580 59.160 +*N chany_top_out[7]:8 *C 46.468 59.160 +*N chany_top_out[7]:9 *C 46.460 59.103 +*N chany_top_out[7]:10 *C 46.460 56.485 +*N chany_top_out[7]:11 *C 46.415 56.440 +*N chany_top_out[7]:12 *C 44.878 56.440 + +*CAP +0 mux_top_track_14\/mux_l2_in_0_:X 1e-06 +1 chany_top_out[7] 5.285591e-05 +2 chany_top_out[7]:2 5.285591e-05 +3 chany_top_out[7]:3 4.673687e-05 +4 chany_top_out[7]:4 4.673687e-05 +5 chany_top_out[7]:5 0.001808407 +6 chany_top_out[7]:6 0.001808407 +7 chany_top_out[7]:7 0.0003323403 +8 chany_top_out[7]:8 0.0003323403 +9 chany_top_out[7]:9 0.0001704352 +10 chany_top_out[7]:10 0.0001704352 +11 chany_top_out[7]:11 0.0001194246 +12 chany_top_out[7]:12 0.0001194246 +13 chany_top_out[7]:6 chany_top_in[15]:9 0.0006101648 +14 chany_top_out[7]:4 chany_top_in[15]:12 4.638002e-05 +15 chany_top_out[7]:5 chany_top_in[15]:10 0.0006101648 +16 chany_top_out[7]:3 chany_top_in[15]:11 4.638002e-05 +17 chany_top_out[7]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002656147 +18 chany_top_out[7]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002656147 + +*RES +0 mux_top_track_14\/mux_l2_in_0_:X chany_top_out[7]:12 0.152 +1 chany_top_out[7]:12 chany_top_out[7]:11 0.001372768 +2 chany_top_out[7]:11 chany_top_out[7]:10 0.0045 +3 chany_top_out[7]:10 chany_top_out[7]:9 0.002337054 +4 chany_top_out[7]:9 chany_top_out[7]:8 0.00341 +5 chany_top_out[7]:8 chany_top_out[7]:7 0.0006442916 +6 chany_top_out[7]:7 chany_top_out[7]:6 0.00341 +7 chany_top_out[7]:6 chany_top_out[7]:5 0.006602716 +8 chany_top_out[7]:4 chany_top_out[7]:3 6.499219e-05 +9 chany_top_out[7]:5 chany_top_out[7]:4 0.00341 +10 chany_top_out[7]:2 chany_top_out[7] 0.0006183035 +11 chany_top_out[7]:3 chany_top_out[7]:2 0.00341 + +*END + +*D_NET chany_top_out[15] 0.001970372 //LENGTH 16.655 LUMPCC 0 DR + +*CONN +*I mux_top_track_30\/mux_l2_in_0_:X O *L 0 *C 48.540 88.400 +*P chany_top_out[15] O *L 0.7423 *C 51.060 102.070 +*N chany_top_out[15]:2 *C 51.060 88.445 +*N chany_top_out[15]:3 *C 51.015 88.400 +*N chany_top_out[15]:4 *C 48.578 88.400 + +*CAP +0 mux_top_track_30\/mux_l2_in_0_:X 1e-06 +1 chany_top_out[15] 0.000779675 +2 chany_top_out[15]:2 0.000779675 +3 chany_top_out[15]:3 0.0002050112 +4 chany_top_out[15]:4 0.0002050112 + +*RES +0 mux_top_track_30\/mux_l2_in_0_:X chany_top_out[15]:4 0.152 +1 chany_top_out[15]:4 chany_top_out[15]:3 0.002176339 +2 chany_top_out[15]:3 chany_top_out[15]:2 0.0045 +3 chany_top_out[15]:2 chany_top_out[15] 0.01216518 + +*END + +*D_NET chanx_left_out[3] 0.001249544 //LENGTH 9.760 LUMPCC 0 DR + +*CONN +*I mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.680 53.380 +*P chanx_left_out[3] O *L 0.7423 *C 1.305 59.840 +*N chanx_left_out[3]:2 *C 2.752 59.840 +*N chanx_left_out[3]:3 *C 2.760 59.783 +*N chanx_left_out[3]:4 *C 2.760 53.765 +*N chanx_left_out[3]:5 *C 2.805 53.720 +*N chanx_left_out[3]:6 *C 3.680 53.720 +*N chanx_left_out[3]:7 *C 3.680 53.380 + +*CAP +0 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[3] 0.0001580762 +2 chanx_left_out[3]:2 0.0001580762 +3 chanx_left_out[3]:3 0.0003565022 +4 chanx_left_out[3]:4 0.0003565022 +5 chanx_left_out[3]:5 7.097025e-05 +6 chanx_left_out[3]:6 9.665018e-05 +7 chanx_left_out[3]:7 5.17669e-05 + +*RES +0 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[3]:7 0.152 +1 chanx_left_out[3]:3 chanx_left_out[3]:2 0.00341 +2 chanx_left_out[3]:2 chanx_left_out[3] 0.000226775 +3 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +4 chanx_left_out[3]:4 chanx_left_out[3]:3 0.005372768 +5 chanx_left_out[3]:7 chanx_left_out[3]:6 0.0003035714 +6 chanx_left_out[3]:6 chanx_left_out[3]:5 0.00078125 + +*END + +*D_NET chanx_left_out[9] 0.001096857 //LENGTH 8.610 LUMPCC 0 DR + +*CONN +*I mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.440 31.620 +*P chanx_left_out[9] O *L 0.7423 *C 1.305 34.000 +*N chanx_left_out[9]:2 *C 2.752 34.000 +*N chanx_left_out[9]:3 *C 2.760 33.943 +*N chanx_left_out[9]:4 *C 2.760 32.005 +*N chanx_left_out[9]:5 *C 2.805 31.960 +*N chanx_left_out[9]:6 *C 5.980 31.960 +*N chanx_left_out[9]:7 *C 5.980 31.620 +*N chanx_left_out[9]:8 *C 6.403 31.620 + +*CAP +0 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[9] 0.0001181684 +2 chanx_left_out[9]:2 0.0001181684 +3 chanx_left_out[9]:3 0.0001304962 +4 chanx_left_out[9]:4 0.0001304962 +5 chanx_left_out[9]:5 0.0002342519 +6 chanx_left_out[9]:6 0.00026036 +7 chanx_left_out[9]:7 6.501217e-05 +8 chanx_left_out[9]:8 3.890405e-05 + +*RES +0 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[9]:8 0.152 +1 chanx_left_out[9]:8 chanx_left_out[9]:7 0.0003772322 +2 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +3 chanx_left_out[9]:4 chanx_left_out[9]:3 0.001729911 +4 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +5 chanx_left_out[9]:2 chanx_left_out[9] 0.000226775 +6 chanx_left_out[9]:6 chanx_left_out[9]:5 0.002834822 +7 chanx_left_out[9]:7 chanx_left_out[9]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_12_sram[0] 0.00186528 //LENGTH 12.800 LUMPCC 0 DR + +*CONN +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 65.165 77.520 +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 68.255 77.180 +*I mux_top_track_36\/mux_l1_in_0_:S I *L 0.00357 *C 64.300 82.960 +*N mux_tree_tapbuf_size2_12_sram[0]:3 *C 64.338 82.960 +*N mux_tree_tapbuf_size2_12_sram[0]:4 *C 64.815 82.960 +*N mux_tree_tapbuf_size2_12_sram[0]:5 *C 64.860 82.915 +*N mux_tree_tapbuf_size2_12_sram[0]:6 *C 68.255 77.180 +*N mux_tree_tapbuf_size2_12_sram[0]:7 *C 68.080 77.180 +*N mux_tree_tapbuf_size2_12_sram[0]:8 *C 68.080 77.225 +*N mux_tree_tapbuf_size2_12_sram[0]:9 *C 68.080 78.823 +*N mux_tree_tapbuf_size2_12_sram[0]:10 *C 68.073 78.880 +*N mux_tree_tapbuf_size2_12_sram[0]:11 *C 64.868 78.880 +*N mux_tree_tapbuf_size2_12_sram[0]:12 *C 64.860 78.880 +*N mux_tree_tapbuf_size2_12_sram[0]:13 *C 64.860 77.565 +*N mux_tree_tapbuf_size2_12_sram[0]:14 *C 64.860 77.520 +*N mux_tree_tapbuf_size2_12_sram[0]:15 *C 65.165 77.520 + +*CAP +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_36\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_12_sram[0]:3 6.50334e-05 +4 mux_tree_tapbuf_size2_12_sram[0]:4 6.50334e-05 +5 mux_tree_tapbuf_size2_12_sram[0]:5 0.000236254 +6 mux_tree_tapbuf_size2_12_sram[0]:6 4.892975e-05 +7 mux_tree_tapbuf_size2_12_sram[0]:7 5.232311e-05 +8 mux_tree_tapbuf_size2_12_sram[0]:8 0.0001513734 +9 mux_tree_tapbuf_size2_12_sram[0]:9 0.0001513734 +10 mux_tree_tapbuf_size2_12_sram[0]:10 0.0002706318 +11 mux_tree_tapbuf_size2_12_sram[0]:11 0.0002706318 +12 mux_tree_tapbuf_size2_12_sram[0]:12 0.0003587489 +13 mux_tree_tapbuf_size2_12_sram[0]:13 8.742473e-05 +14 mux_tree_tapbuf_size2_12_sram[0]:14 5.360125e-05 +15 mux_tree_tapbuf_size2_12_sram[0]:15 5.092087e-05 + +*RES +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_12_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_12_sram[0]:12 mux_tree_tapbuf_size2_12_sram[0]:11 0.00341 +2 mux_tree_tapbuf_size2_12_sram[0]:12 mux_tree_tapbuf_size2_12_sram[0]:5 0.003602678 +3 mux_tree_tapbuf_size2_12_sram[0]:11 mux_tree_tapbuf_size2_12_sram[0]:10 0.0005021166 +4 mux_tree_tapbuf_size2_12_sram[0]:9 mux_tree_tapbuf_size2_12_sram[0]:8 0.001426339 +5 mux_tree_tapbuf_size2_12_sram[0]:10 mux_tree_tapbuf_size2_12_sram[0]:9 0.00341 +6 mux_tree_tapbuf_size2_12_sram[0]:7 mux_tree_tapbuf_size2_12_sram[0]:6 9.51087e-05 +7 mux_tree_tapbuf_size2_12_sram[0]:8 mux_tree_tapbuf_size2_12_sram[0]:7 0.0045 +8 mux_tree_tapbuf_size2_12_sram[0]:6 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size2_12_sram[0]:14 mux_tree_tapbuf_size2_12_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size2_12_sram[0]:13 mux_tree_tapbuf_size2_12_sram[0]:12 0.001174107 +11 mux_tree_tapbuf_size2_12_sram[0]:15 mux_tree_tapbuf_size2_12_sram[0]:14 0.0001657609 +12 mux_tree_tapbuf_size2_12_sram[0]:4 mux_tree_tapbuf_size2_12_sram[0]:3 0.0004263393 +13 mux_tree_tapbuf_size2_12_sram[0]:5 mux_tree_tapbuf_size2_12_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size2_12_sram[0]:3 mux_top_track_36\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_17_sram[0] 0.00343926 //LENGTH 26.910 LUMPCC 0.0008289417 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 9.965 47.600 +*I mux_left_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 12.520 47.310 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 9.835 31.620 +*N mux_tree_tapbuf_size2_17_sram[0]:3 *C 9.873 31.620 +*N mux_tree_tapbuf_size2_17_sram[0]:4 *C 14.675 31.620 +*N mux_tree_tapbuf_size2_17_sram[0]:5 *C 14.720 31.665 +*N mux_tree_tapbuf_size2_17_sram[0]:6 *C 14.720 46.875 +*N mux_tree_tapbuf_size2_17_sram[0]:7 *C 14.675 46.920 +*N mux_tree_tapbuf_size2_17_sram[0]:8 *C 12.520 46.920 +*N mux_tree_tapbuf_size2_17_sram[0]:9 *C 12.520 47.263 +*N mux_tree_tapbuf_size2_17_sram[0]:10 *C 10.120 47.260 +*N mux_tree_tapbuf_size2_17_sram[0]:11 *C 9.965 47.600 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_17\/mux_l1_in_0_:S 1e-06 +2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_17_sram[0]:3 0.0003376478 +4 mux_tree_tapbuf_size2_17_sram[0]:4 0.0003376478 +5 mux_tree_tapbuf_size2_17_sram[0]:5 0.0005676935 +6 mux_tree_tapbuf_size2_17_sram[0]:6 0.0005676935 +7 mux_tree_tapbuf_size2_17_sram[0]:7 0.0001619305 +8 mux_tree_tapbuf_size2_17_sram[0]:8 0.0001902701 +9 mux_tree_tapbuf_size2_17_sram[0]:9 0.000199549 +10 mux_tree_tapbuf_size2_17_sram[0]:10 0.000194816 +11 mux_tree_tapbuf_size2_17_sram[0]:11 5.007054e-05 +12 mux_tree_tapbuf_size2_17_sram[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.486975e-05 +13 mux_tree_tapbuf_size2_17_sram[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.486975e-05 +14 mux_tree_tapbuf_size2_17_sram[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0003596011 +15 mux_tree_tapbuf_size2_17_sram[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0003596011 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_17_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_17_sram[0]:7 mux_tree_tapbuf_size2_17_sram[0]:6 0.0045 +2 mux_tree_tapbuf_size2_17_sram[0]:6 mux_tree_tapbuf_size2_17_sram[0]:5 0.01358036 +3 mux_tree_tapbuf_size2_17_sram[0]:4 mux_tree_tapbuf_size2_17_sram[0]:3 0.004287947 +4 mux_tree_tapbuf_size2_17_sram[0]:5 mux_tree_tapbuf_size2_17_sram[0]:4 0.0045 +5 mux_tree_tapbuf_size2_17_sram[0]:3 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_17_sram[0]:11 mux_tree_tapbuf_size2_17_sram[0]:10 0.0003035715 +7 mux_tree_tapbuf_size2_17_sram[0]:9 mux_left_track_17\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_17_sram[0]:9 mux_tree_tapbuf_size2_17_sram[0]:8 0.0003058036 +9 mux_tree_tapbuf_size2_17_sram[0]:10 mux_tree_tapbuf_size2_17_sram[0]:9 0.002142857 +10 mux_tree_tapbuf_size2_17_sram[0]:8 mux_tree_tapbuf_size2_17_sram[0]:7 0.001924107 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.001796823 //LENGTH 13.295 LUMPCC 0.0002652361 DR + +*CONN +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.745 91.120 +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 55.835 88.060 +*I mux_top_track_18\/mux_l1_in_0_:S I *L 0.00357 *C 51.860 83.640 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 51.898 83.640 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 52.395 83.640 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 52.440 83.685 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 55.797 88.060 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 55.200 88.060 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 55.200 87.720 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 52.485 87.720 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 52.440 87.720 +*N mux_tree_tapbuf_size2_4_sram[0]:11 *C 52.440 91.075 +*N mux_tree_tapbuf_size2_4_sram[0]:12 *C 52.440 91.120 +*N mux_tree_tapbuf_size2_4_sram[0]:13 *C 52.745 91.120 + +*CAP +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_18\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 6.052147e-05 +4 mux_tree_tapbuf_size2_4_sram[0]:4 6.052147e-05 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.0001598198 +6 mux_tree_tapbuf_size2_4_sram[0]:6 6.007159e-05 +7 mux_tree_tapbuf_size2_4_sram[0]:7 8.614316e-05 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.0002191552 +9 mux_tree_tapbuf_size2_4_sram[0]:9 0.0001930836 +10 mux_tree_tapbuf_size2_4_sram[0]:10 0.0003907625 +11 mux_tree_tapbuf_size2_4_sram[0]:11 0.000197381 +12 mux_tree_tapbuf_size2_4_sram[0]:12 5.288938e-05 +13 mux_tree_tapbuf_size2_4_sram[0]:13 4.823799e-05 +14 mux_tree_tapbuf_size2_4_sram[0]:5 top_left_grid_pin_35_[0]:14 0.0001073744 +15 mux_tree_tapbuf_size2_4_sram[0]:11 top_left_grid_pin_35_[0]:15 2.126805e-05 +16 mux_tree_tapbuf_size2_4_sram[0]:11 top_left_grid_pin_35_[0]:21 6.107592e-07 +17 mux_tree_tapbuf_size2_4_sram[0]:9 top_left_grid_pin_35_[0]:18 3.364826e-06 +18 mux_tree_tapbuf_size2_4_sram[0]:10 top_left_grid_pin_35_[0]:14 2.126805e-05 +19 mux_tree_tapbuf_size2_4_sram[0]:10 top_left_grid_pin_35_[0]:15 0.0001073744 +20 mux_tree_tapbuf_size2_4_sram[0]:10 top_left_grid_pin_35_[0]:20 6.107592e-07 +21 mux_tree_tapbuf_size2_4_sram[0]:8 top_left_grid_pin_35_[0]:17 3.364826e-06 + +*RES +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:3 mux_top_track_18\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_4_sram[0]:4 mux_tree_tapbuf_size2_4_sram[0]:3 0.0004441965 +3 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_4_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_4_sram[0]:12 mux_tree_tapbuf_size2_4_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size2_4_sram[0]:11 mux_tree_tapbuf_size2_4_sram[0]:10 0.002995536 +6 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_4_sram[0]:12 0.0001657609 +7 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.002424107 +8 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:5 0.003602679 +10 mux_tree_tapbuf_size2_4_sram[0]:6 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.0003035715 +12 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:6 0.0005334822 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.0008005056 //LENGTH 6.990 LUMPCC 9.898335e-05 DR + +*CONN +*I mem_top_track_10\/FTB_13__18:X O *L 0 *C 60.945 33.660 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 61.815 28.220 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 61.778 28.220 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 61.225 28.220 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 61.180 28.265 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 61.180 33.615 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 61.180 33.660 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 60.945 33.660 + +*CAP +0 mem_top_track_10\/FTB_13__18:X 1e-06 +1 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 6.02483e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 6.02483e-05 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0002424371 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0002424371 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 4.64954e-05 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 4.765609e-05 +8 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 prog_clk[0]:327 3.586542e-05 +9 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 prog_clk[0]:334 1.362626e-05 +10 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 prog_clk[0]:333 3.586542e-05 +11 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 prog_clk[0]:337 1.362626e-05 + +*RES +0 mem_top_track_10\/FTB_13__18:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.0004933036 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_20_ccff_tail[0] 0.000826437 //LENGTH 6.560 LUMPCC 0 DR + +*CONN +*I mem_left_track_23\/FTB_33__38:X O *L 0 *C 48.075 28.560 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 45.255 31.620 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:2 *C 45.293 31.620 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:3 *C 47.795 31.620 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:4 *C 47.840 31.575 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:5 *C 47.840 28.605 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:6 *C 47.840 28.560 +*N mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:7 *C 48.075 28.560 + +*CAP +0 mem_left_track_23\/FTB_33__38:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:2 0.0001820337 +3 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:3 0.0001820337 +4 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:4 0.0001802616 +5 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:5 0.0001802616 +6 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:6 4.984738e-05 +7 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:7 4.999893e-05 + +*RES +0 mem_left_track_23\/FTB_33__38:X mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:2 0.002234375 +3 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_20_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[0] 0.002305197 //LENGTH 19.445 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 37.565 47.600 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 35.135 42.500 +*I mux_left_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 36.700 36.720 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 42.420 47.260 +*N mux_tree_tapbuf_size3_2_sram[0]:4 *C 42.420 47.260 +*N mux_tree_tapbuf_size3_2_sram[0]:5 *C 42.320 47.600 +*N mux_tree_tapbuf_size3_2_sram[0]:6 *C 36.700 36.720 +*N mux_tree_tapbuf_size3_2_sram[0]:7 *C 36.800 36.765 +*N mux_tree_tapbuf_size3_2_sram[0]:8 *C 35.172 42.500 +*N mux_tree_tapbuf_size3_2_sram[0]:9 *C 36.755 42.500 +*N mux_tree_tapbuf_size3_2_sram[0]:10 *C 36.800 42.500 +*N mux_tree_tapbuf_size3_2_sram[0]:11 *C 36.800 47.555 +*N mux_tree_tapbuf_size3_2_sram[0]:12 *C 36.845 47.600 +*N mux_tree_tapbuf_size3_2_sram[0]:13 *C 37.565 47.600 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_9\/mux_l1_in_1_:S 1e-06 +3 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_2_sram[0]:4 5.630091e-05 +5 mux_tree_tapbuf_size3_2_sram[0]:5 0.0003233175 +6 mux_tree_tapbuf_size3_2_sram[0]:6 2.813237e-05 +7 mux_tree_tapbuf_size3_2_sram[0]:7 0.0003188257 +8 mux_tree_tapbuf_size3_2_sram[0]:8 0.0001170335 +9 mux_tree_tapbuf_size3_2_sram[0]:9 0.0001170335 +10 mux_tree_tapbuf_size3_2_sram[0]:10 0.0006325098 +11 mux_tree_tapbuf_size3_2_sram[0]:11 0.0002812906 +12 mux_tree_tapbuf_size3_2_sram[0]:12 5.183813e-05 +13 mux_tree_tapbuf_size3_2_sram[0]:13 0.0003749146 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size3_2_sram[0]:12 mux_tree_tapbuf_size3_2_sram[0]:11 0.0045 +2 mux_tree_tapbuf_size3_2_sram[0]:11 mux_tree_tapbuf_size3_2_sram[0]:10 0.004513393 +3 mux_tree_tapbuf_size3_2_sram[0]:9 mux_tree_tapbuf_size3_2_sram[0]:8 0.001412946 +4 mux_tree_tapbuf_size3_2_sram[0]:10 mux_tree_tapbuf_size3_2_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size3_2_sram[0]:10 mux_tree_tapbuf_size3_2_sram[0]:7 0.005120536 +6 mux_tree_tapbuf_size3_2_sram[0]:8 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:12 0.0006428572 +8 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:5 0.004245536 +9 mux_tree_tapbuf_size3_2_sram[0]:6 mux_left_track_9\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size3_2_sram[0]:7 mux_tree_tapbuf_size3_2_sram[0]:6 0.0045 +11 mux_tree_tapbuf_size3_2_sram[0]:4 mux_left_track_9\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size3_2_sram[0]:5 mux_tree_tapbuf_size3_2_sram[0]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_2_sram[2] 0.001983392 //LENGTH 13.765 LUMPCC 0.0005183732 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.305 61.200 +*I mem_left_track_3\/FTB_7__12:A I *L 0.001746 *C 20.240 55.760 +*I mux_left_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 18.960 63.920 +*N mux_tree_tapbuf_size5_2_sram[2]:3 *C 18.998 63.920 +*N mux_tree_tapbuf_size5_2_sram[2]:4 *C 20.195 63.920 +*N mux_tree_tapbuf_size5_2_sram[2]:5 *C 20.240 63.875 +*N mux_tree_tapbuf_size5_2_sram[2]:6 *C 20.240 55.760 +*N mux_tree_tapbuf_size5_2_sram[2]:7 *C 20.240 55.805 +*N mux_tree_tapbuf_size5_2_sram[2]:8 *C 20.240 61.200 +*N mux_tree_tapbuf_size5_2_sram[2]:9 *C 20.248 61.200 +*N mux_tree_tapbuf_size5_2_sram[2]:10 *C 22.073 61.200 +*N mux_tree_tapbuf_size5_2_sram[2]:11 *C 22.080 61.200 +*N mux_tree_tapbuf_size5_2_sram[2]:12 *C 22.125 61.200 +*N mux_tree_tapbuf_size5_2_sram[2]:13 *C 23.268 61.200 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_3\/FTB_7__12:A 1e-06 +2 mux_left_track_3\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_2_sram[2]:3 0.000109965 +4 mux_tree_tapbuf_size5_2_sram[2]:4 0.000109965 +5 mux_tree_tapbuf_size5_2_sram[2]:5 0.0001090861 +6 mux_tree_tapbuf_size5_2_sram[2]:6 3.23147e-05 +7 mux_tree_tapbuf_size5_2_sram[2]:7 0.0003076982 +8 mux_tree_tapbuf_size5_2_sram[2]:8 0.0004573442 +9 mux_tree_tapbuf_size5_2_sram[2]:9 9.110138e-05 +10 mux_tree_tapbuf_size5_2_sram[2]:10 9.110138e-05 +11 mux_tree_tapbuf_size5_2_sram[2]:11 4.055985e-05 +12 mux_tree_tapbuf_size5_2_sram[2]:12 5.644144e-05 +13 mux_tree_tapbuf_size5_2_sram[2]:13 5.644144e-05 +14 mux_tree_tapbuf_size5_2_sram[2]:10 chanx_left_in[5]:9 0.0001194707 +15 mux_tree_tapbuf_size5_2_sram[2]:9 chanx_left_in[5]:10 0.0001194707 +16 mux_tree_tapbuf_size5_2_sram[2]:13 mux_tree_tapbuf_size5_2_sram[1]:11 5.60789e-05 +17 mux_tree_tapbuf_size5_2_sram[2]:12 mux_tree_tapbuf_size5_2_sram[1]:13 5.60789e-05 +18 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[1]:9 1.0606e-07 +19 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[1]:10 3.224224e-07 +20 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[1]:14 7.119862e-05 +21 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[1]:15 1.200992e-05 +22 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[1]:9 3.224224e-07 +23 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[1]:15 7.119862e-05 +24 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[1]:10 1.0606e-07 +25 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[1]:14 1.200992e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_2_sram[2]:13 0.152 +1 mux_tree_tapbuf_size5_2_sram[2]:13 mux_tree_tapbuf_size5_2_sram[2]:12 0.001020089 +2 mux_tree_tapbuf_size5_2_sram[2]:12 mux_tree_tapbuf_size5_2_sram[2]:11 0.0045 +3 mux_tree_tapbuf_size5_2_sram[2]:11 mux_tree_tapbuf_size5_2_sram[2]:10 0.00341 +4 mux_tree_tapbuf_size5_2_sram[2]:10 mux_tree_tapbuf_size5_2_sram[2]:9 0.0002859167 +5 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[2]:7 0.004816964 +6 mux_tree_tapbuf_size5_2_sram[2]:8 mux_tree_tapbuf_size5_2_sram[2]:5 0.002388393 +7 mux_tree_tapbuf_size5_2_sram[2]:9 mux_tree_tapbuf_size5_2_sram[2]:8 0.00341 +8 mux_tree_tapbuf_size5_2_sram[2]:4 mux_tree_tapbuf_size5_2_sram[2]:3 0.001069196 +9 mux_tree_tapbuf_size5_2_sram[2]:5 mux_tree_tapbuf_size5_2_sram[2]:4 0.0045 +10 mux_tree_tapbuf_size5_2_sram[2]:3 mux_left_track_3\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size5_2_sram[2]:6 mem_left_track_3\/FTB_7__12:A 0.152 +12 mux_tree_tapbuf_size5_2_sram[2]:7 mux_tree_tapbuf_size5_2_sram[2]:6 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[2] 0.001562978 //LENGTH 9.620 LUMPCC 0.0004903892 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 18.700 39.100 +*I mux_left_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 12.520 36.720 +*I mem_left_track_1\/FTB_3__8:A I *L 0.001746 *C 18.860 36.720 +*N mux_tree_tapbuf_size6_2_sram[2]:3 *C 18.823 36.720 +*N mux_tree_tapbuf_size6_2_sram[2]:4 *C 12.558 36.720 +*N mux_tree_tapbuf_size6_2_sram[2]:5 *C 18.400 36.720 +*N mux_tree_tapbuf_size6_2_sram[2]:6 *C 18.400 36.765 +*N mux_tree_tapbuf_size6_2_sram[2]:7 *C 18.400 39.055 +*N mux_tree_tapbuf_size6_2_sram[2]:8 *C 18.400 39.100 +*N mux_tree_tapbuf_size6_2_sram[2]:9 *C 18.700 39.100 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_1\/FTB_3__8:A 1e-06 +3 mux_tree_tapbuf_size6_2_sram[2]:3 3.090165e-05 +4 mux_tree_tapbuf_size6_2_sram[2]:4 0.0002507237 +5 mux_tree_tapbuf_size6_2_sram[2]:5 0.0003157536 +6 mux_tree_tapbuf_size6_2_sram[2]:6 0.0001789553 +7 mux_tree_tapbuf_size6_2_sram[2]:7 0.0001789553 +8 mux_tree_tapbuf_size6_2_sram[2]:8 5.948063e-05 +9 mux_tree_tapbuf_size6_2_sram[2]:9 5.481882e-05 +10 mux_tree_tapbuf_size6_2_sram[2]:5 left_bottom_grid_pin_1_[0]:9 0.0002233506 +11 mux_tree_tapbuf_size6_2_sram[2]:5 left_bottom_grid_pin_1_[0]:10 2.184398e-05 +12 mux_tree_tapbuf_size6_2_sram[2]:4 left_bottom_grid_pin_1_[0]:10 0.0002233506 +13 mux_tree_tapbuf_size6_2_sram[2]:3 left_bottom_grid_pin_1_[0]:9 2.184398e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_2_sram[2]:9 0.152 +1 mux_tree_tapbuf_size6_2_sram[2]:5 mux_tree_tapbuf_size6_2_sram[2]:4 0.005216518 +2 mux_tree_tapbuf_size6_2_sram[2]:5 mux_tree_tapbuf_size6_2_sram[2]:3 0.0003772322 +3 mux_tree_tapbuf_size6_2_sram[2]:6 mux_tree_tapbuf_size6_2_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size6_2_sram[2]:8 mux_tree_tapbuf_size6_2_sram[2]:7 0.0045 +5 mux_tree_tapbuf_size6_2_sram[2]:7 mux_tree_tapbuf_size6_2_sram[2]:6 0.002044643 +6 mux_tree_tapbuf_size6_2_sram[2]:9 mux_tree_tapbuf_size6_2_sram[2]:8 0.0001630435 +7 mux_tree_tapbuf_size6_2_sram[2]:4 mux_left_track_1\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_2_sram[2]:3 mem_left_track_1\/FTB_3__8:A 0.152 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008144966 //LENGTH 7.200 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 81.245 75.140 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.100 77.860 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.100 77.860 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 85.100 77.815 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 85.100 75.185 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 85.055 75.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 81.282 75.140 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.18627e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001615895 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001615895 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002287274 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002287274 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.003368304 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002348214 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.00146663 //LENGTH 9.965 LUMPCC 0.0002268357 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 83.085 61.880 +*I mux_top_track_4\/mux_l3_in_0_:A1 I *L 0.005458 *C 88.030 64.183 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 87.950 64.135 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 87.950 64.150 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 87.950 64.573 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 87.943 64.600 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 82.808 64.600 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 82.800 64.543 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 82.800 61.925 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 82.800 61.880 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 83.085 61.880 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A1 3.192643e-05 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.192643e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.996029e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.996029e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002979265 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002979265 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001788978 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001788978 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.097508e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:10 6.039711e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size5_0_sram[0]:15 0.0001134179 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_0_sram[0]:16 0.0001134179 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001548913 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002337054 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0008044833 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000203125 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A1 7.692308e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001262421 //LENGTH 8.375 LUMPCC 0.0005486445 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_0_:X O *L 0 *C 60.545 61.880 +*I mux_top_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 66.340 63.580 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 66.240 63.580 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 66.240 63.535 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 66.240 61.938 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 66.233 61.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 61.188 61.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 61.180 61.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 61.135 61.880 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 60.583 61.880 + +*CAP +0 mux_top_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.242892e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.822303e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.822303e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000189586 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.000189586 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.480497e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.446246e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 6.446246e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_0_sram[0]:16 0.0001104311 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_0_sram[0]:15 0.0001104311 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_1_sram[0]:17 0.0001104311 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_1_sram[0]:16 0.0001104311 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.346003e-05 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.346003e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001426339 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00341 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00341 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0007903833 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0004933036 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00102526 //LENGTH 7.830 LUMPCC 0.0001122781 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_0_:X O *L 0 *C 21.335 69.020 +*I mux_left_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 19.685 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 19.723 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 21.115 63.580 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 21.160 63.625 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 21.160 68.975 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 21.160 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 21.335 69.020 + +*CAP +0 mux_left_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.227385e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.227385e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003048849 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003048849 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.315492e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.350987e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mem_left_track_27/net_net_60:5 5.613906e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mem_left_track_27/net_net_60:6 5.613906e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243303 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004776786 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006206145 //LENGTH 5.425 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 83.085 44.200 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.200 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.163 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 83.765 41.820 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 83.720 41.865 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 83.720 44.155 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 83.675 44.200 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 83.123 44.200 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001055709 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001055709 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001384511 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001384511 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.528525e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.528525e-05 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001247768 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004933036 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0] 0.000828766 //LENGTH 7.005 LUMPCC 9.403087e-05 DR + +*CONN +*I mux_top_track_10\/mux_l1_in_0_:X O *L 0 *C 57.785 39.780 +*I mux_top_track_10\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.500 39.780 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.463 39.780 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.823 39.780 + +*CAP +0 mux_top_track_10\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_10\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003663676 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003663676 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_0_sram[0]:5 4.701544e-05 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_0_sram[0]:4 4.701544e-05 + +*RES +0 mux_top_track_10\/mux_l1_in_0_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_10\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005928572 + +*END + +*D_NET mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00160757 //LENGTH 12.320 LUMPCC 0.0002616882 DR + +*CONN +*I mux_top_track_18\/mux_l1_in_0_:X O *L 0 *C 54.565 82.960 +*I mux_top_track_18\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.865 90.780 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.828 90.780 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 54.325 90.780 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 54.280 90.735 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 54.280 83.005 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 54.280 82.960 +*N mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 54.565 82.960 + +*CAP +0 mux_top_track_18\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_18\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002505452 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002505452 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003621481 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003621481 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.94146e-05 +7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.908032e-05 +8 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:155 6.981079e-05 +9 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:154 6.981079e-05 +10 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.103331e-05 +11 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.103331e-05 + +*RES +0 mux_top_track_18\/mux_l1_in_0_:X mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_18\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003127232 +3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008651976 //LENGTH 7.265 LUMPCC 0 DR + +*CONN +*I mux_top_track_30\/mux_l1_in_0_:X O *L 0 *C 39.845 82.960 +*I mux_top_track_30\/mux_l2_in_0_:A1 I *L 0.005458 *C 41.065 88.308 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 40.940 88.185 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 40.940 88.140 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 40.940 83.005 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 40.895 82.960 +*N mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 39.883 82.960 + +*CAP +0 mux_top_track_30\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_30\/mux_l2_in_0_:A1 4.203212e-05 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.203212e-05 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003000888 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003000888 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.997788e-05 +6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.997788e-05 + +*RES +0 mux_top_track_30\/mux_l1_in_0_:X mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_30\/mux_l2_in_0_:A1 7.692308e-05 +2 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004584821 +5 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_30/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0009040179 + +*END + +*D_NET mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0002852773 //LENGTH 1.860 LUMPCC 0 DR + +*CONN +*I mux_top_track_36\/mux_l1_in_0_:X O *L 0 *C 65.145 82.545 +*I mux_top_track_36\/mux_l2_in_0_:A1 I *L 0.005458 *C 66.860 82.683 +*N mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 65.183 82.605 + +*CAP +0 mux_top_track_36\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_36\/mux_l2_in_0_:A1 0.0001421387 +2 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001421387 + +*RES +0 mux_top_track_36\/mux_l1_in_0_:X mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.152 +1 mux_top_track_36/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_36\/mux_l2_in_0_:A1 0.001497768 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001715335 //LENGTH 12.240 LUMPCC 0.0005797046 DR + +*CONN +*I mux_left_track_13\/mux_l1_in_0_:X O *L 0 *C 16.735 72.420 +*I mux_left_track_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 9.105 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 9.143 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 10.120 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 10.120 69.360 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 14.675 69.360 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 14.720 69.405 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 14.720 72.375 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 14.765 72.420 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 16.698 72.420 + +*CAP +0 mux_left_track_13\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_13\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.945572e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.590757e-05 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002220908 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001956389 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001916728 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001916728 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.359601e-05 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 9.359601e-05 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_out[13]:5 8.54385e-07 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_out[13]:6 0.0001405969 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_out[13]:6 8.54385e-07 +13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_out[13]:5 0.0001405969 +14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size2_15_sram[0]:4 2.578672e-06 +15 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size2_15_sram[0]:6 6.717608e-05 +16 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size2_15_sram[0]:5 2.578672e-06 +17 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_tree_tapbuf_size2_15_sram[0]:7 6.717608e-05 +18 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_15_sram[1]:8 4.447194e-05 +19 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_15_sram[1]:9 3.208691e-05 +20 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_15_sram[1]:10 1.237676e-06 +21 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_15_sram[1]:11 1.237676e-06 +22 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_15_sram[1]:8 8.497647e-07 +23 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_15_sram[1]:9 4.447194e-05 +24 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_15_sram[1]:3 8.497647e-07 +25 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_15_sram[1]:8 3.208691e-05 + +*RES +0 mux_left_track_13\/mux_l1_in_0_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_13\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004066964 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002651786 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.001725447 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008727679 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 + +*END + +*D_NET ropt_net_127 0.00151027 //LENGTH 9.000 LUMPCC 0.000702841 DR + +*CONN +*I ropt_mt_inst_725:X O *L 0 *C 7.095 60.520 +*I ropt_mt_inst_732:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_127:2 *C 3.258 58.480 +*N ropt_net_127:3 *C 3.635 58.480 +*N ropt_net_127:4 *C 3.680 58.435 +*N ropt_net_127:5 *C 3.680 57.800 +*N ropt_net_127:6 *C 4.120 57.800 +*N ropt_net_127:7 *C 4.128 57.800 +*N ropt_net_127:8 *C 5.973 57.800 +*N ropt_net_127:9 *C 5.980 57.858 +*N ropt_net_127:10 *C 5.980 60.475 +*N ropt_net_127:11 *C 6.025 60.520 +*N ropt_net_127:12 *C 7.058 60.520 + +*CAP +0 ropt_mt_inst_725:X 1e-06 +1 ropt_mt_inst_732:A 1e-06 +2 ropt_net_127:2 5.221445e-05 +3 ropt_net_127:3 5.221445e-05 +4 ropt_net_127:4 5.305531e-05 +5 ropt_net_127:5 8.620224e-05 +6 ropt_net_127:6 6.892685e-05 +7 ropt_net_127:7 4.695678e-05 +8 ropt_net_127:8 4.695678e-05 +9 ropt_net_127:9 0.0001348625 +10 ropt_net_127:10 0.0001348625 +11 ropt_net_127:11 6.458858e-05 +12 ropt_net_127:12 6.458858e-05 +13 ropt_net_127:8 chanx_left_in[2]:8 0.0001207331 +14 ropt_net_127:7 chanx_left_in[2] 0.0001207331 +15 ropt_net_127:8 chanx_left_in[6]:6 0.0001189652 +16 ropt_net_127:7 chanx_left_in[6]:7 0.0001189652 +17 ropt_net_127:12 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 5.219894e-05 +18 ropt_net_127:11 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 5.219894e-05 +19 ropt_net_127:10 ropt_net_118:4 5.952327e-05 +20 ropt_net_127:9 ropt_net_118:5 5.952327e-05 + +*RES +0 ropt_mt_inst_725:X ropt_net_127:12 0.152 +1 ropt_net_127:12 ropt_net_127:11 0.0009218751 +2 ropt_net_127:11 ropt_net_127:10 0.0045 +3 ropt_net_127:10 ropt_net_127:9 0.002337054 +4 ropt_net_127:9 ropt_net_127:8 0.00341 +5 ropt_net_127:8 ropt_net_127:7 0.00028905 +6 ropt_net_127:6 ropt_net_127:5 0.0003928572 +7 ropt_net_127:7 ropt_net_127:6 0.00341 +8 ropt_net_127:3 ropt_net_127:2 0.0003370536 +9 ropt_net_127:4 ropt_net_127:3 0.0045 +10 ropt_net_127:2 ropt_mt_inst_732:A 0.152 +11 ropt_net_127:5 ropt_net_127:4 0.0005669643 + +*END + +*D_NET mux_top_track_6/BUF_net_42 0.002008511 //LENGTH 16.300 LUMPCC 0.0006507599 DR + +*CONN +*I mux_top_track_6\/BUFT_RR_42:X O *L 0 *C 67.620 75.140 +*I mux_top_track_6\/BUFT_P_87:A I *L 0.001766 *C 67.620 91.120 +*N mux_top_track_6/BUF_net_42:2 *C 67.620 91.120 +*N mux_top_track_6/BUF_net_42:3 *C 67.620 91.075 +*N mux_top_track_6/BUF_net_42:4 *C 67.620 75.185 +*N mux_top_track_6/BUF_net_42:5 *C 67.620 75.140 + +*CAP +0 mux_top_track_6\/BUFT_RR_42:X 1e-06 +1 mux_top_track_6\/BUFT_P_87:A 1e-06 +2 mux_top_track_6/BUF_net_42:2 3.27577e-05 +3 mux_top_track_6/BUF_net_42:3 0.0006467489 +4 mux_top_track_6/BUF_net_42:4 0.0006467489 +5 mux_top_track_6/BUF_net_42:5 2.949526e-05 +6 mux_top_track_6/BUF_net_42:3 chany_top_in[7] 9.732984e-05 +7 mux_top_track_6/BUF_net_42:4 chany_top_in[7]:9 9.732984e-05 +8 mux_top_track_6/BUF_net_42:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001552876 +9 mux_top_track_6/BUF_net_42:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001552876 +10 mux_top_track_6/BUF_net_42:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 7.276254e-05 +11 mux_top_track_6/BUF_net_42:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 7.276254e-05 + +*RES +0 mux_top_track_6\/BUFT_RR_42:X mux_top_track_6/BUF_net_42:5 0.152 +1 mux_top_track_6/BUF_net_42:2 mux_top_track_6\/BUFT_P_87:A 0.152 +2 mux_top_track_6/BUF_net_42:3 mux_top_track_6/BUF_net_42:2 0.0045 +3 mux_top_track_6/BUF_net_42:5 mux_top_track_6/BUF_net_42:4 0.0045 +4 mux_top_track_6/BUF_net_42:4 mux_top_track_6/BUF_net_42:3 0.0141875 + +*END + +*D_NET chany_top_in[9] 0.01304093 //LENGTH 101.405 LUMPCC 0.005965255 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 67.620 102.035 +*I mux_left_track_23\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.400 30.940 +*N chany_top_in[9]:2 *C 41.363 30.940 +*N chany_top_in[9]:3 *C 40.985 30.940 +*N chany_top_in[9]:4 *C 40.940 30.940 +*N chany_top_in[9]:5 *C 40.940 31.280 +*N chany_top_in[9]:6 *C 40.940 31.273 +*N chany_top_in[9]:7 *C 40.940 30.600 +*N chany_top_in[9]:8 *C 63.460 30.600 +*N chany_top_in[9]:9 *C 63.480 30.608 +*N chany_top_in[9]:10 *C 63.480 80.435 +*N chany_top_in[9]:11 *C 63.480 98.593 +*N chany_top_in[9]:12 *C 63.500 98.600 +*N chany_top_in[9]:13 *C 67.612 98.600 +*N chany_top_in[9]:14 *C 67.620 98.657 + +*CAP +0 chany_top_in[9] 0.0002028482 +1 mux_left_track_23\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[9]:2 5.174124e-05 +3 chany_top_in[9]:3 5.174124e-05 +4 chany_top_in[9]:4 5.731455e-05 +5 chany_top_in[9]:5 6.180658e-05 +6 chany_top_in[9]:6 5.597156e-05 +7 chany_top_in[9]:7 0.0008901203 +8 chany_top_in[9]:8 0.0008341487 +9 chany_top_in[9]:9 0.001704949 +10 chany_top_in[9]:10 0.002205767 +11 chany_top_in[9]:11 0.0005008183 +12 chany_top_in[9]:12 0.0001273021 +13 chany_top_in[9]:13 0.0001273021 +14 chany_top_in[9]:14 0.0002028482 +15 chany_top_in[9]:6 prog_clk[0]:282 5.724788e-06 +16 chany_top_in[9]:8 prog_clk[0]:278 4.677111e-05 +17 chany_top_in[9]:8 prog_clk[0]:283 3.860682e-05 +18 chany_top_in[9]:8 prog_clk[0]:331 0.0002042895 +19 chany_top_in[9]:9 prog_clk[0]:210 5.941655e-06 +20 chany_top_in[9]:12 prog_clk[0]:146 0.0002471989 +21 chany_top_in[9]:13 prog_clk[0]:80 0.0002471989 +22 chany_top_in[9]:7 prog_clk[0]:281 5.724788e-06 +23 chany_top_in[9]:7 prog_clk[0]:283 4.677111e-05 +24 chany_top_in[9]:7 prog_clk[0]:291 3.860682e-05 +25 chany_top_in[9]:7 prog_clk[0]:332 0.0002042895 +26 chany_top_in[9]:10 prog_clk[0]:211 5.941655e-06 +27 chany_top_in[9]:9 chany_top_in[8]:8 0.0006506511 +28 chany_top_in[9]:12 chany_top_in[8]:11 2.660829e-06 +29 chany_top_in[9]:11 chany_top_in[8]:9 0.000293876 +30 chany_top_in[9]:11 chany_top_in[8]:10 6.587871e-05 +31 chany_top_in[9]:13 chany_top_in[8]:12 2.660829e-06 +32 chany_top_in[9]:10 chany_top_in[8]:8 0.000293876 +33 chany_top_in[9]:10 chany_top_in[8]:9 0.0007165298 +34 chany_top_in[9] chany_top_in[16] 4.635266e-06 +35 chany_top_in[9]:9 chany_top_in[16]:9 0.0006481193 +36 chany_top_in[9]:12 chany_top_in[16]:11 7.980349e-05 +37 chany_top_in[9]:11 chany_top_in[16]:10 0.0003440182 +38 chany_top_in[9]:14 chany_top_in[16]:13 4.635266e-06 +39 chany_top_in[9]:13 chany_top_in[16]:12 7.980349e-05 +40 chany_top_in[9]:10 chany_top_in[16]:9 0.0003440182 +41 chany_top_in[9]:10 chany_top_in[16]:10 0.0006481193 +42 chany_top_in[9]:8 chanx_left_in[16]:6 0.0001926458 +43 chany_top_in[9]:8 chanx_left_in[16]:7 0.0001518061 +44 chany_top_in[9]:7 chanx_left_in[16] 0.0001518061 +45 chany_top_in[9]:7 chanx_left_in[16]:7 0.0001926458 + +*RES +0 chany_top_in[9] chany_top_in[9]:14 0.003015625 +1 chany_top_in[9]:2 mux_left_track_23\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[9]:3 chany_top_in[9]:2 0.0003370536 +3 chany_top_in[9]:4 chany_top_in[9]:3 0.0045 +4 chany_top_in[9]:5 chany_top_in[9]:4 0.0001634615 +5 chany_top_in[9]:6 chany_top_in[9]:5 0.00341 +6 chany_top_in[9]:8 chany_top_in[9]:7 0.003528134 +7 chany_top_in[9]:9 chany_top_in[9]:8 0.00341 +8 chany_top_in[9]:12 chany_top_in[9]:11 0.00341 +9 chany_top_in[9]:11 chany_top_in[9]:10 0.002844675 +10 chany_top_in[9]:14 chany_top_in[9]:13 0.00341 +11 chany_top_in[9]:13 chany_top_in[9]:12 0.0006442916 +12 chany_top_in[9]:7 chany_top_in[9]:6 0.0001053583 +13 chany_top_in[9]:10 chany_top_in[9]:9 0.007806308 + +*END + +*D_NET chany_top_in[19] 0.010256 //LENGTH 67.500 LUMPCC 0.002949466 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 59.340 102.070 +*I mux_left_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 27.045 69.020 +*N chany_top_in[19]:2 *C 27.082 69.020 +*N chany_top_in[19]:3 *C 30.775 69.020 +*N chany_top_in[19]:4 *C 30.820 69.065 +*N chany_top_in[19]:5 *C 30.820 72.023 +*N chany_top_in[19]:6 *C 30.828 72.080 +*N chany_top_in[19]:7 *C 36.780 72.080 +*N chany_top_in[19]:8 *C 36.800 72.088 +*N chany_top_in[19]:9 *C 36.800 84.993 +*N chany_top_in[19]:10 *C 36.820 85.000 +*N chany_top_in[19]:11 *C 58.873 85.000 +*N chany_top_in[19]:12 *C 58.880 85.058 +*N chany_top_in[19]:13 *C 58.880 94.520 +*N chany_top_in[19]:14 *C 59.340 94.520 + +*CAP +0 chany_top_in[19] 0.0003836887 +1 mux_left_track_3\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[19]:2 0.0002465875 +3 chany_top_in[19]:3 0.0002465875 +4 chany_top_in[19]:4 0.0002022878 +5 chany_top_in[19]:5 0.0002022878 +6 chany_top_in[19]:6 0.0004739023 +7 chany_top_in[19]:7 0.0004739023 +8 chany_top_in[19]:8 0.0005769042 +9 chany_top_in[19]:9 0.0005769042 +10 chany_top_in[19]:10 0.001296973 +11 chany_top_in[19]:11 0.001296973 +12 chany_top_in[19]:12 0.0004517791 +13 chany_top_in[19]:13 0.0004724249 +14 chany_top_in[19]:14 0.0004043344 +15 chany_top_in[19]:8 chany_top_in[12]:9 0.0002757979 +16 chany_top_in[19]:9 chany_top_in[12]:10 0.0002757979 +17 chany_top_in[19]:10 top_left_grid_pin_39_[0]:18 0.0009042483 +18 chany_top_in[19]:11 top_left_grid_pin_39_[0]:17 0.0009042483 +19 chany_top_in[19] mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.376965e-05 +20 chany_top_in[19]:14 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.376965e-05 +21 chany_top_in[19]:12 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002319578 +22 chany_top_in[19]:13 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.959632e-06 +23 chany_top_in[19]:13 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002319578 +24 chany_top_in[19]:14 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.959632e-06 + +*RES +0 chany_top_in[19] chany_top_in[19]:14 0.006741072 +1 chany_top_in[19]:2 mux_left_track_3\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[19]:3 chany_top_in[19]:2 0.003296875 +3 chany_top_in[19]:4 chany_top_in[19]:3 0.0045 +4 chany_top_in[19]:5 chany_top_in[19]:4 0.002640625 +5 chany_top_in[19]:6 chany_top_in[19]:5 0.00341 +6 chany_top_in[19]:7 chany_top_in[19]:6 0.0009325583 +7 chany_top_in[19]:8 chany_top_in[19]:7 0.00341 +8 chany_top_in[19]:10 chany_top_in[19]:9 0.00341 +9 chany_top_in[19]:9 chany_top_in[19]:8 0.002021783 +10 chany_top_in[19]:12 chany_top_in[19]:11 0.00341 +11 chany_top_in[19]:11 chany_top_in[19]:10 0.003454891 +12 chany_top_in[19]:13 chany_top_in[19]:12 0.008448661 +13 chany_top_in[19]:14 chany_top_in[19]:13 0.0004107143 + +*END + +*D_NET top_left_grid_pin_34_[0] 0.01614422 //LENGTH 119.090 LUMPCC 0.004645992 DR + +*CONN +*P top_left_grid_pin_34_[0] I *L 0.29796 *C 32.660 102.070 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.000 61.540 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 81.520 45.220 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 79.120 74.460 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 80.500 90.780 +*N top_left_grid_pin_34_[0]:5 *C 80.500 90.780 +*N top_left_grid_pin_34_[0]:6 *C 80.500 90.780 +*N top_left_grid_pin_34_[0]:7 *C 79.098 74.487 +*N top_left_grid_pin_34_[0]:8 *C 79.085 74.800 +*N top_left_grid_pin_34_[0]:9 *C 81.520 45.220 +*N top_left_grid_pin_34_[0]:10 *C 81.420 45.560 +*N top_left_grid_pin_34_[0]:11 *C 76.405 45.560 +*N top_left_grid_pin_34_[0]:12 *C 76.360 45.605 +*N top_left_grid_pin_34_[0]:13 *C 76.360 54.060 +*N top_left_grid_pin_34_[0]:14 *C 75.900 54.060 +*N top_left_grid_pin_34_[0]:15 *C 75.900 61.540 +*N top_left_grid_pin_34_[0]:16 *C 75.900 61.540 +*N top_left_grid_pin_34_[0]:17 *C 75.900 74.755 +*N top_left_grid_pin_34_[0]:18 *C 75.945 74.800 +*N top_left_grid_pin_34_[0]:19 *C 78.660 74.800 +*N top_left_grid_pin_34_[0]:20 *C 78.660 74.845 +*N top_left_grid_pin_34_[0]:21 *C 78.660 88.015 +*N top_left_grid_pin_34_[0]:22 *C 78.705 88.060 +*N top_left_grid_pin_34_[0]:23 *C 79.995 88.060 +*N top_left_grid_pin_34_[0]:24 *C 80.040 88.105 +*N top_left_grid_pin_34_[0]:25 *C 80.040 90.780 +*N top_left_grid_pin_34_[0]:26 *C 80.075 91.080 +*N top_left_grid_pin_34_[0]:27 *C 80.032 91.120 +*N top_left_grid_pin_34_[0]:28 *C 39.108 91.120 +*N top_left_grid_pin_34_[0]:29 *C 39.100 91.178 +*N top_left_grid_pin_34_[0]:30 *C 39.100 96.175 +*N top_left_grid_pin_34_[0]:31 *C 39.055 96.220 +*N top_left_grid_pin_34_[0]:32 *C 32.705 96.220 +*N top_left_grid_pin_34_[0]:33 *C 32.660 96.265 + +*CAP +0 top_left_grid_pin_34_[0] 0.0002685323 +1 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +4 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_34_[0]:5 3.356789e-05 +6 top_left_grid_pin_34_[0]:6 6.959221e-05 +7 top_left_grid_pin_34_[0]:7 2.988097e-05 +8 top_left_grid_pin_34_[0]:8 6.871788e-05 +9 top_left_grid_pin_34_[0]:9 5.612872e-05 +10 top_left_grid_pin_34_[0]:10 0.0003649841 +11 top_left_grid_pin_34_[0]:11 0.0003372299 +12 top_left_grid_pin_34_[0]:12 0.000415077 +13 top_left_grid_pin_34_[0]:13 0.0004451497 +14 top_left_grid_pin_34_[0]:14 0.0003698503 +15 top_left_grid_pin_34_[0]:15 3.369091e-05 +16 top_left_grid_pin_34_[0]:16 0.0009392382 +17 top_left_grid_pin_34_[0]:17 0.0005682752 +18 top_left_grid_pin_34_[0]:18 0.0002135245 +19 top_left_grid_pin_34_[0]:19 0.0002727738 +20 top_left_grid_pin_34_[0]:20 0.0007177986 +21 top_left_grid_pin_34_[0]:21 0.0007177986 +22 top_left_grid_pin_34_[0]:22 9.190671e-05 +23 top_left_grid_pin_34_[0]:23 9.190671e-05 +24 top_left_grid_pin_34_[0]:24 0.000160321 +25 top_left_grid_pin_34_[0]:25 0.0002335807 +26 top_left_grid_pin_34_[0]:26 3.767783e-05 +27 top_left_grid_pin_34_[0]:27 0.001690828 +28 top_left_grid_pin_34_[0]:28 0.001690828 +29 top_left_grid_pin_34_[0]:29 0.0002828135 +30 top_left_grid_pin_34_[0]:30 0.0002828135 +31 top_left_grid_pin_34_[0]:31 0.0003706041 +32 top_left_grid_pin_34_[0]:32 0.0003706041 +33 top_left_grid_pin_34_[0]:33 0.0002685323 +34 top_left_grid_pin_34_[0] prog_clk[0]:257 0.0001048581 +35 top_left_grid_pin_34_[0]:27 prog_clk[0]:136 0.0001280926 +36 top_left_grid_pin_34_[0]:27 prog_clk[0]:141 0.0002027247 +37 top_left_grid_pin_34_[0]:28 prog_clk[0]:141 0.0001280926 +38 top_left_grid_pin_34_[0]:28 prog_clk[0]:142 0.0002027247 +39 top_left_grid_pin_34_[0]:33 prog_clk[0]:256 0.0001048581 +40 top_left_grid_pin_34_[0]:27 chany_top_in[12]:12 0.0002852073 +41 top_left_grid_pin_34_[0]:28 chany_top_in[12]:11 0.0002852073 +42 top_left_grid_pin_34_[0]:27 top_left_grid_pin_41_[0]:19 0.001132943 +43 top_left_grid_pin_34_[0]:28 top_left_grid_pin_41_[0] 0.001132943 +44 top_left_grid_pin_34_[0]:12 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.662815e-05 +45 top_left_grid_pin_34_[0]:17 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001091104 +46 top_left_grid_pin_34_[0]:16 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001091104 +47 top_left_grid_pin_34_[0]:16 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.271485e-05 +48 top_left_grid_pin_34_[0]:14 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.271485e-05 +49 top_left_grid_pin_34_[0]:13 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.662815e-05 +50 top_left_grid_pin_34_[0]:21 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.727188e-05 +51 top_left_grid_pin_34_[0]:20 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.727188e-05 +52 top_left_grid_pin_34_[0]:27 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001834447 +53 top_left_grid_pin_34_[0]:28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001834447 + +*RES +0 top_left_grid_pin_34_[0] top_left_grid_pin_34_[0]:33 0.005183036 +1 top_left_grid_pin_34_[0]:23 top_left_grid_pin_34_[0]:22 0.001151786 +2 top_left_grid_pin_34_[0]:24 top_left_grid_pin_34_[0]:23 0.0045 +3 top_left_grid_pin_34_[0]:22 top_left_grid_pin_34_[0]:21 0.0045 +4 top_left_grid_pin_34_[0]:21 top_left_grid_pin_34_[0]:20 0.01175893 +5 top_left_grid_pin_34_[0]:19 top_left_grid_pin_34_[0]:18 0.002424107 +6 top_left_grid_pin_34_[0]:19 top_left_grid_pin_34_[0]:8 0.0003794643 +7 top_left_grid_pin_34_[0]:20 top_left_grid_pin_34_[0]:19 0.0045 +8 top_left_grid_pin_34_[0]:9 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +9 top_left_grid_pin_34_[0]:11 top_left_grid_pin_34_[0]:10 0.004477679 +10 top_left_grid_pin_34_[0]:12 top_left_grid_pin_34_[0]:11 0.0045 +11 top_left_grid_pin_34_[0]:7 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +12 top_left_grid_pin_34_[0]:18 top_left_grid_pin_34_[0]:17 0.0045 +13 top_left_grid_pin_34_[0]:17 top_left_grid_pin_34_[0]:16 0.01179911 +14 top_left_grid_pin_34_[0]:15 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +15 top_left_grid_pin_34_[0]:16 top_left_grid_pin_34_[0]:15 0.0045 +16 top_left_grid_pin_34_[0]:16 top_left_grid_pin_34_[0]:14 0.006678572 +17 top_left_grid_pin_34_[0]:26 top_left_grid_pin_34_[0]:25 0.0001785714 +18 top_left_grid_pin_34_[0]:27 top_left_grid_pin_34_[0]:26 0.00341 +19 top_left_grid_pin_34_[0]:29 top_left_grid_pin_34_[0]:28 0.00341 +20 top_left_grid_pin_34_[0]:28 top_left_grid_pin_34_[0]:27 0.006411583 +21 top_left_grid_pin_34_[0]:31 top_left_grid_pin_34_[0]:30 0.0045 +22 top_left_grid_pin_34_[0]:30 top_left_grid_pin_34_[0]:29 0.004462054 +23 top_left_grid_pin_34_[0]:32 top_left_grid_pin_34_[0]:31 0.005669643 +24 top_left_grid_pin_34_[0]:33 top_left_grid_pin_34_[0]:32 0.0045 +25 top_left_grid_pin_34_[0]:5 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +26 top_left_grid_pin_34_[0]:6 top_left_grid_pin_34_[0]:5 0.0045 +27 top_left_grid_pin_34_[0]:8 top_left_grid_pin_34_[0]:7 0.0002111487 +28 top_left_grid_pin_34_[0]:10 top_left_grid_pin_34_[0]:9 0.0003035715 +29 top_left_grid_pin_34_[0]:14 top_left_grid_pin_34_[0]:13 0.0004107143 +30 top_left_grid_pin_34_[0]:13 top_left_grid_pin_34_[0]:12 0.007549108 +31 top_left_grid_pin_34_[0]:25 top_left_grid_pin_34_[0]:24 0.002388393 +32 top_left_grid_pin_34_[0]:25 top_left_grid_pin_34_[0]:6 0.0004107143 + +*END + +*D_NET top_left_grid_pin_38_[0] 0.01195019 //LENGTH 89.515 LUMPCC 0.002601416 DR + +*CONN +*P top_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 97.920 +*I mux_top_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 40.940 74.460 +*I mux_top_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 79.680 66.980 +*I mux_top_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 79.680 72.420 +*I mux_top_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 45.540 72.420 +*N top_left_grid_pin_38_[0]:5 *C 45.578 72.420 +*N top_left_grid_pin_38_[0]:6 *C 45.955 72.420 +*N top_left_grid_pin_38_[0]:7 *C 46.000 72.420 +*N top_left_grid_pin_38_[0]:8 *C 79.642 72.420 +*N top_left_grid_pin_38_[0]:9 *C 79.642 66.980 +*N top_left_grid_pin_38_[0]:10 *C 77.325 66.980 +*N top_left_grid_pin_38_[0]:11 *C 77.280 67.025 +*N top_left_grid_pin_38_[0]:12 *C 77.280 72.375 +*N top_left_grid_pin_38_[0]:13 *C 77.280 72.420 +*N top_left_grid_pin_38_[0]:14 *C 73.645 72.420 +*N top_left_grid_pin_38_[0]:15 *C 73.600 72.420 +*N top_left_grid_pin_38_[0]:16 *C 73.600 72.760 +*N top_left_grid_pin_38_[0]:17 *C 73.593 72.760 +*N top_left_grid_pin_38_[0]:18 *C 46.008 72.760 +*N top_left_grid_pin_38_[0]:19 *C 46.000 72.818 +*N top_left_grid_pin_38_[0]:20 *C 46.000 74.415 +*N top_left_grid_pin_38_[0]:21 *C 45.955 74.460 +*N top_left_grid_pin_38_[0]:22 *C 40.977 74.460 +*N top_left_grid_pin_38_[0]:23 *C 43.700 74.460 +*N top_left_grid_pin_38_[0]:24 *C 43.700 74.505 +*N top_left_grid_pin_38_[0]:25 *C 43.700 97.863 +*N top_left_grid_pin_38_[0]:26 *C 43.693 97.920 + +*CAP +0 top_left_grid_pin_38_[0] 0.0007304598 +1 mux_top_track_32\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_1_:A1 1e-06 +4 mux_top_track_16\/mux_l1_in_0_:A1 1e-06 +5 top_left_grid_pin_38_[0]:5 5.128875e-05 +6 top_left_grid_pin_38_[0]:6 5.128875e-05 +7 top_left_grid_pin_38_[0]:7 5.052464e-05 +8 top_left_grid_pin_38_[0]:8 0.0001601451 +9 top_left_grid_pin_38_[0]:9 0.0001971294 +10 top_left_grid_pin_38_[0]:10 0.0001971294 +11 top_left_grid_pin_38_[0]:11 0.000302217 +12 top_left_grid_pin_38_[0]:12 0.000302217 +13 top_left_grid_pin_38_[0]:13 0.0004260058 +14 top_left_grid_pin_38_[0]:14 0.0002321501 +15 top_left_grid_pin_38_[0]:15 4.960159e-05 +16 top_left_grid_pin_38_[0]:16 5.319344e-05 +17 top_left_grid_pin_38_[0]:17 0.001248323 +18 top_left_grid_pin_38_[0]:18 0.001248323 +19 top_left_grid_pin_38_[0]:19 0.0001251953 +20 top_left_grid_pin_38_[0]:20 0.0001061919 +21 top_left_grid_pin_38_[0]:21 0.0001362697 +22 top_left_grid_pin_38_[0]:22 0.0001828711 +23 top_left_grid_pin_38_[0]:23 0.0003532078 +24 top_left_grid_pin_38_[0]:24 0.001205293 +25 top_left_grid_pin_38_[0]:25 0.001205293 +26 top_left_grid_pin_38_[0]:26 0.0007304598 +27 top_left_grid_pin_38_[0] prog_clk[0]:171 7.829366e-05 +28 top_left_grid_pin_38_[0] prog_clk[0]:172 0.0001810854 +29 top_left_grid_pin_38_[0] prog_clk[0]:176 1.268854e-05 +30 top_left_grid_pin_38_[0] prog_clk[0]:177 3.045248e-06 +31 top_left_grid_pin_38_[0] prog_clk[0]:467 2.930285e-05 +32 top_left_grid_pin_38_[0]:24 prog_clk[0]:165 2.402299e-06 +33 top_left_grid_pin_38_[0]:24 prog_clk[0]:244 5.252753e-08 +34 top_left_grid_pin_38_[0]:25 prog_clk[0]:166 2.402299e-06 +35 top_left_grid_pin_38_[0]:25 prog_clk[0]:247 5.252753e-08 +36 top_left_grid_pin_38_[0]:26 prog_clk[0]:167 7.829366e-05 +37 top_left_grid_pin_38_[0]:26 prog_clk[0]:171 0.0001810854 +38 top_left_grid_pin_38_[0]:26 prog_clk[0]:172 3.045248e-06 +39 top_left_grid_pin_38_[0]:26 prog_clk[0]:177 1.268854e-05 +40 top_left_grid_pin_38_[0]:26 prog_clk[0]:258 2.930285e-05 +41 top_left_grid_pin_38_[0]:18 prog_clk[0]:212 5.719017e-06 +42 top_left_grid_pin_38_[0]:18 prog_clk[0]:216 1.161869e-05 +43 top_left_grid_pin_38_[0]:18 prog_clk[0]:221 2.857686e-07 +44 top_left_grid_pin_38_[0]:17 prog_clk[0]:183 5.719017e-06 +45 top_left_grid_pin_38_[0]:17 prog_clk[0]:212 1.161869e-05 +46 top_left_grid_pin_38_[0]:17 prog_clk[0]:216 2.857686e-07 +47 top_left_grid_pin_38_[0]:18 chany_top_in[17]:6 0.0005593937 +48 top_left_grid_pin_38_[0]:17 chany_top_in[17]:7 0.0005593937 +49 top_left_grid_pin_38_[0]:18 chanx_left_in[9]:8 0.0001135435 +50 top_left_grid_pin_38_[0]:18 chanx_left_in[9]:7 0.0001783114 +51 top_left_grid_pin_38_[0]:17 chanx_left_in[9]:6 0.0001783114 +52 top_left_grid_pin_38_[0]:17 chanx_left_in[9]:7 0.0001135435 +53 top_left_grid_pin_38_[0]:22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.282669e-05 +54 top_left_grid_pin_38_[0]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.282669e-05 +55 top_left_grid_pin_38_[0]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.117164e-05 +56 top_left_grid_pin_38_[0]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000100967 +57 top_left_grid_pin_38_[0]:25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000100967 +58 top_left_grid_pin_38_[0]:21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.117164e-05 + +*RES +0 top_left_grid_pin_38_[0] top_left_grid_pin_38_[0]:26 0.002184325 +1 top_left_grid_pin_38_[0]:22 mux_top_track_32\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_38_[0]:23 top_left_grid_pin_38_[0]:22 0.002430804 +3 top_left_grid_pin_38_[0]:23 top_left_grid_pin_38_[0]:21 0.002013393 +4 top_left_grid_pin_38_[0]:24 top_left_grid_pin_38_[0]:23 0.0045 +5 top_left_grid_pin_38_[0]:25 top_left_grid_pin_38_[0]:24 0.02085491 +6 top_left_grid_pin_38_[0]:26 top_left_grid_pin_38_[0]:25 0.00341 +7 top_left_grid_pin_38_[0]:21 top_left_grid_pin_38_[0]:20 0.0045 +8 top_left_grid_pin_38_[0]:20 top_left_grid_pin_38_[0]:19 0.001426339 +9 top_left_grid_pin_38_[0]:5 mux_top_track_16\/mux_l1_in_0_:A1 0.152 +10 top_left_grid_pin_38_[0]:6 top_left_grid_pin_38_[0]:5 0.0003370536 +11 top_left_grid_pin_38_[0]:7 top_left_grid_pin_38_[0]:6 0.0045 +12 top_left_grid_pin_38_[0]:13 top_left_grid_pin_38_[0]:12 0.0045 +13 top_left_grid_pin_38_[0]:13 top_left_grid_pin_38_[0]:8 0.002109375 +14 top_left_grid_pin_38_[0]:12 top_left_grid_pin_38_[0]:11 0.004776786 +15 top_left_grid_pin_38_[0]:10 top_left_grid_pin_38_[0]:9 0.002069197 +16 top_left_grid_pin_38_[0]:11 top_left_grid_pin_38_[0]:10 0.0045 +17 top_left_grid_pin_38_[0]:9 mux_top_track_4\/mux_l1_in_1_:A1 0.152 +18 top_left_grid_pin_38_[0]:8 mux_top_track_0\/mux_l1_in_1_:A1 0.152 +19 top_left_grid_pin_38_[0]:19 top_left_grid_pin_38_[0]:18 0.00341 +20 top_left_grid_pin_38_[0]:19 top_left_grid_pin_38_[0]:7 0.0001911058 +21 top_left_grid_pin_38_[0]:18 top_left_grid_pin_38_[0]:17 0.00432165 +22 top_left_grid_pin_38_[0]:16 top_left_grid_pin_38_[0]:15 0.0001634615 +23 top_left_grid_pin_38_[0]:17 top_left_grid_pin_38_[0]:16 0.00341 +24 top_left_grid_pin_38_[0]:14 top_left_grid_pin_38_[0]:13 0.003245536 +25 top_left_grid_pin_38_[0]:15 top_left_grid_pin_38_[0]:14 0.0045 + +*END + +*D_NET chanx_left_in[0] 0.01377576 //LENGTH 98.115 LUMPCC 0.005390998 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.230 51.680 +*I mux_top_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 79.295 69.700 +*N chanx_left_in[0]:2 *C 79.295 69.700 +*N chanx_left_in[0]:3 *C 79.580 69.700 +*N chanx_left_in[0]:4 *C 79.580 69.700 +*N chanx_left_in[0]:5 *C 79.580 69.360 +*N chanx_left_in[0]:6 *C 79.578 69.360 +*N chanx_left_in[0]:7 *C 79.135 69.360 +*N chanx_left_in[0]:8 *C 79.120 69.353 +*N chanx_left_in[0]:9 *C 79.120 52.367 +*N chanx_left_in[0]:10 *C 79.100 52.360 +*N chanx_left_in[0]:11 *C 39.100 52.360 +*N chanx_left_in[0]:12 *C 39.100 51.680 + +*CAP +0 chanx_left_in[0] 0.0012757 +1 mux_top_track_0\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[0]:2 4.627852e-05 +3 chanx_left_in[0]:3 5.098359e-05 +4 chanx_left_in[0]:4 5.702877e-05 +5 chanx_left_in[0]:5 6.275828e-05 +6 chanx_left_in[0]:6 8.328883e-05 +7 chanx_left_in[0]:7 8.328883e-05 +8 chanx_left_in[0]:8 0.0008526955 +9 chanx_left_in[0]:9 0.0008526955 +10 chanx_left_in[0]:10 0.001811285 +11 chanx_left_in[0]:11 0.001871674 +12 chanx_left_in[0]:12 0.001336088 +13 chanx_left_in[0] prog_clk[0]:373 4.176427e-05 +14 chanx_left_in[0] prog_clk[0]:377 7.709018e-05 +15 chanx_left_in[0] prog_clk[0]:378 0.0002165177 +16 chanx_left_in[0]:10 prog_clk[0]:318 3.7887e-05 +17 chanx_left_in[0]:10 prog_clk[0]:324 6.300692e-05 +18 chanx_left_in[0]:10 prog_clk[0]:358 5.30092e-05 +19 chanx_left_in[0]:10 prog_clk[0]:362 0.0001094867 +20 chanx_left_in[0]:10 prog_clk[0]:369 5.962492e-05 +21 chanx_left_in[0]:12 prog_clk[0]:369 4.176427e-05 +22 chanx_left_in[0]:12 prog_clk[0]:373 0.0002165177 +23 chanx_left_in[0]:12 prog_clk[0]:378 7.709018e-05 +24 chanx_left_in[0]:11 prog_clk[0]:319 3.7887e-05 +25 chanx_left_in[0]:11 prog_clk[0]:357 6.300692e-05 +26 chanx_left_in[0]:11 prog_clk[0]:362 5.30092e-05 +27 chanx_left_in[0]:11 prog_clk[0]:369 0.0001094867 +28 chanx_left_in[0]:11 prog_clk[0]:373 5.962492e-05 +29 chanx_left_in[0]:8 chany_top_in[0]:9 0.0001672566 +30 chanx_left_in[0]:10 chany_top_in[0]:7 0.000762489 +31 chanx_left_in[0]:9 chany_top_in[0]:8 0.0001672566 +32 chanx_left_in[0]:11 chany_top_in[0]:6 0.000762489 +33 chanx_left_in[0] chanx_left_in[3] 0.000754914 +34 chanx_left_in[0]:12 chanx_left_in[3]:16 0.000754914 +35 chanx_left_in[0] chanx_left_in[5] 0.0003524525 +36 chanx_left_in[0]:12 chanx_left_in[5]:13 0.0003524525 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:12 0.005932966 +1 chanx_left_in[0]:2 mux_top_track_0\/mux_l1_in_2_:A0 0.152 +2 chanx_left_in[0]:3 chanx_left_in[0]:2 0.0001548913 +3 chanx_left_in[0]:4 chanx_left_in[0]:3 0.0045 +4 chanx_left_in[0]:5 chanx_left_in[0]:4 0.0001634615 +5 chanx_left_in[0]:6 chanx_left_in[0]:5 0.00341 +6 chanx_left_in[0]:7 chanx_left_in[0]:6 6.499219e-05 +7 chanx_left_in[0]:8 chanx_left_in[0]:7 0.00341 +8 chanx_left_in[0]:10 chanx_left_in[0]:9 0.00341 +9 chanx_left_in[0]:9 chanx_left_in[0]:8 0.002660983 +10 chanx_left_in[0]:12 chanx_left_in[0]:11 0.0001065333 +11 chanx_left_in[0]:11 chanx_left_in[0]:10 0.006266666 + +*END + +*D_NET chanx_left_in[4] 0.006922888 //LENGTH 53.270 LUMPCC 0.0005017363 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 62.560 +*I mux_top_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 40.655 75.480 +*N chanx_left_in[4]:2 *C 40.617 75.480 +*N chanx_left_in[4]:3 *C 15.640 75.480 +*N chanx_left_in[4]:4 *C 15.640 74.460 +*N chanx_left_in[4]:5 *C 15.640 74.415 +*N chanx_left_in[4]:6 *C 15.640 62.617 +*N chanx_left_in[4]:7 *C 15.633 62.560 + +*CAP +0 chanx_left_in[4] 0.001007232 +1 mux_top_track_32\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[4]:2 0.001380858 +3 chanx_left_in[4]:3 0.001442856 +4 chanx_left_in[4]:4 9.378275e-05 +5 chanx_left_in[4]:5 0.000744095 +6 chanx_left_in[4]:6 0.000744095 +7 chanx_left_in[4]:7 0.001007232 +8 chanx_left_in[4]:2 mux_tree_tapbuf_size2_15_sram[0]:13 0.0002508682 +9 chanx_left_in[4]:3 mux_tree_tapbuf_size2_15_sram[0]:12 0.0002508682 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:7 0.002256392 +1 chanx_left_in[4]:2 mux_top_track_32\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[4]:4 chanx_left_in[4]:3 0.0009107143 +3 chanx_left_in[4]:5 chanx_left_in[4]:4 0.0045 +4 chanx_left_in[4]:6 chanx_left_in[4]:5 0.01053348 +5 chanx_left_in[4]:7 chanx_left_in[4]:6 0.00341 +6 chanx_left_in[4]:3 chanx_left_in[4]:2 0.02230134 + +*END + +*D_NET chanx_left_in[6] 0.01168314 //LENGTH 81.140 LUMPCC 0.004435174 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.305 47.600 +*I mux_top_track_28\/mux_l1_in_0_:A0 I *L 0.001631 *C 35.135 93.160 +*N chanx_left_in[6]:2 *C 35.098 93.160 +*N chanx_left_in[6]:3 *C 33.165 93.160 +*N chanx_left_in[6]:4 *C 33.120 93.115 +*N chanx_left_in[6]:5 *C 33.120 58.538 +*N chanx_left_in[6]:6 *C 33.113 58.480 +*N chanx_left_in[6]:7 *C 2.780 58.480 +*N chanx_left_in[6]:8 *C 2.760 58.473 +*N chanx_left_in[6]:9 *C 2.760 48.288 +*N chanx_left_in[6]:10 *C 2.740 48.280 +*N chanx_left_in[6]:11 *C 1.380 48.280 + +*CAP +0 chanx_left_in[6] 5.806371e-05 +1 mux_top_track_28\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[6]:2 0.0001467084 +3 chanx_left_in[6]:3 0.0001467084 +4 chanx_left_in[6]:4 0.001714067 +5 chanx_left_in[6]:5 0.001714067 +6 chanx_left_in[6]:6 0.0008640637 +7 chanx_left_in[6]:7 0.0008640638 +8 chanx_left_in[6]:8 0.0006602674 +9 chanx_left_in[6]:9 0.0006602674 +10 chanx_left_in[6]:10 0.0001803106 +11 chanx_left_in[6]:11 0.0002383743 +12 chanx_left_in[6]:4 prog_clk[0]:253 0.0001026157 +13 chanx_left_in[6]:4 prog_clk[0]:256 6.988569e-05 +14 chanx_left_in[6]:4 prog_clk[0]:257 2.178622e-05 +15 chanx_left_in[6]:4 prog_clk[0]:392 1.183691e-05 +16 chanx_left_in[6]:4 prog_clk[0]:464 3.879863e-07 +17 chanx_left_in[6]:5 prog_clk[0]:250 0.0001026157 +18 chanx_left_in[6]:5 prog_clk[0]:253 6.988569e-05 +19 chanx_left_in[6]:5 prog_clk[0]:256 2.178622e-05 +20 chanx_left_in[6]:5 prog_clk[0]:391 1.183691e-05 +21 chanx_left_in[6]:5 prog_clk[0]:396 3.879863e-07 +22 chanx_left_in[6]:6 prog_clk[0]:393 7.467841e-05 +23 chanx_left_in[6]:6 prog_clk[0]:453 2.434451e-06 +24 chanx_left_in[6]:7 prog_clk[0]:394 7.467841e-05 +25 chanx_left_in[6]:7 prog_clk[0]:452 2.434451e-06 +26 chanx_left_in[6]:10 prog_clk[0]:431 1.986018e-05 +27 chanx_left_in[6]:11 prog_clk[0]:409 1.986018e-05 +28 chanx_left_in[6]:6 chanx_left_in[2]:8 0.0006394698 +29 chanx_left_in[6]:7 chanx_left_in[2] 0.0006394698 +30 chanx_left_in[6]:6 left_top_grid_pin_42_[0]:25 0.000577282 +31 chanx_left_in[6]:6 left_top_grid_pin_42_[0]:27 1.604747e-06 +32 chanx_left_in[6]:7 left_top_grid_pin_42_[0]:28 1.604747e-06 +33 chanx_left_in[6]:7 left_top_grid_pin_42_[0]:26 0.000577282 +34 chanx_left_in[6]:6 left_top_grid_pin_46_[0]:13 0.0005767798 +35 chanx_left_in[6]:7 left_top_grid_pin_46_[0]:14 0.0005767798 +36 chanx_left_in[6]:6 ropt_net_127:8 0.0001189652 +37 chanx_left_in[6]:7 ropt_net_127:7 0.0001189652 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:11 0.0001065333 +1 chanx_left_in[6]:2 mux_top_track_28\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[6]:3 chanx_left_in[6]:2 0.001725447 +3 chanx_left_in[6]:4 chanx_left_in[6]:3 0.0045 +4 chanx_left_in[6]:5 chanx_left_in[6]:4 0.03087277 +5 chanx_left_in[6]:6 chanx_left_in[6]:5 0.00341 +6 chanx_left_in[6]:7 chanx_left_in[6]:6 0.004752091 +7 chanx_left_in[6]:8 chanx_left_in[6]:7 0.00341 +8 chanx_left_in[6]:10 chanx_left_in[6]:9 0.00341 +9 chanx_left_in[6]:9 chanx_left_in[6]:8 0.00159565 +10 chanx_left_in[6]:11 chanx_left_in[6]:10 0.0002130667 + +*END + +*D_NET chanx_left_in[11] 0.008781455 //LENGTH 66.170 LUMPCC 0.001797222 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 69.360 +*I mux_top_track_18\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.615 82.620 +*N chanx_left_in[11]:2 *C 52.578 82.620 +*N chanx_left_in[11]:3 *C 49.725 82.620 +*N chanx_left_in[11]:4 *C 49.680 82.575 +*N chanx_left_in[11]:5 *C 49.680 80.978 +*N chanx_left_in[11]:6 *C 49.672 80.920 +*N chanx_left_in[11]:7 *C 33.140 80.920 +*N chanx_left_in[11]:8 *C 33.120 80.913 +*N chanx_left_in[11]:9 *C 33.120 69.368 +*N chanx_left_in[11]:10 *C 33.100 69.360 + +*CAP +0 chanx_left_in[11] 0.001523446 +1 mux_top_track_18\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[11]:2 0.0001856136 +3 chanx_left_in[11]:3 0.0001856136 +4 chanx_left_in[11]:4 0.0001106158 +5 chanx_left_in[11]:5 0.0001106158 +6 chanx_left_in[11]:6 0.0009084145 +7 chanx_left_in[11]:7 0.0009084145 +8 chanx_left_in[11]:8 0.0007635264 +9 chanx_left_in[11]:9 0.0007635264 +10 chanx_left_in[11]:10 0.001523446 +11 chanx_left_in[11]:6 top_left_grid_pin_36_[0]:16 0.0002809081 +12 chanx_left_in[11]:7 top_left_grid_pin_36_[0]:17 0.0002809081 +13 chanx_left_in[11] mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000617703 +14 chanx_left_in[11]:10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000617703 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:10 0.004992966 +1 chanx_left_in[11]:2 mux_top_track_18\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[11]:3 chanx_left_in[11]:2 0.002546875 +3 chanx_left_in[11]:4 chanx_left_in[11]:3 0.0045 +4 chanx_left_in[11]:5 chanx_left_in[11]:4 0.001426339 +5 chanx_left_in[11]:6 chanx_left_in[11]:5 0.00341 +6 chanx_left_in[11]:7 chanx_left_in[11]:6 0.002590092 +7 chanx_left_in[11]:8 chanx_left_in[11]:7 0.00341 +8 chanx_left_in[11]:10 chanx_left_in[11]:9 0.00341 +9 chanx_left_in[11]:9 chanx_left_in[11]:8 0.001808717 + +*END + +*D_NET chanx_left_in[14] 0.009517785 //LENGTH 97.920 LUMPCC 0.00134412 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 6.800 +*I mux_top_track_12\/mux_l1_in_0_:A0 I *L 0.001631 *C 71.475 33.660 +*N chanx_left_in[14]:2 *C 71.438 33.660 +*N chanx_left_in[14]:3 *C 67.205 33.660 +*N chanx_left_in[14]:4 *C 67.160 33.615 +*N chanx_left_in[14]:5 *C 67.160 6.857 +*N chanx_left_in[14]:6 *C 67.153 6.800 +*N chanx_left_in[14]:7 *C 51.230 6.800 + +*CAP +0 chanx_left_in[14] 0.001865265 +1 mux_top_track_12\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[14]:2 0.0002941945 +3 chanx_left_in[14]:3 0.0002941945 +4 chanx_left_in[14]:4 0.001227415 +5 chanx_left_in[14]:5 0.001227415 +6 chanx_left_in[14]:6 0.0006994581 +7 chanx_left_in[14]:7 0.002564723 +8 chanx_left_in[14] chanx_left_in[19] 0.0006069721 +9 chanx_left_in[14]:6 chanx_left_in[19]:6 6.50877e-05 +10 chanx_left_in[14]:7 chanx_left_in[19]:7 0.0006720598 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:7 0.007833333 +1 chanx_left_in[14]:2 mux_top_track_12\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[14]:3 chanx_left_in[14]:2 0.003779018 +3 chanx_left_in[14]:4 chanx_left_in[14]:3 0.0045 +4 chanx_left_in[14]:5 chanx_left_in[14]:4 0.02389063 +5 chanx_left_in[14]:6 chanx_left_in[14]:5 0.00341 +6 chanx_left_in[14]:7 chanx_left_in[14]:6 0.002494525 + +*END + +*D_NET chanx_left_in[19] 0.01071538 //LENGTH 109.565 LUMPCC 0.001478217 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 4.080 +*I mux_top_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 57.040 56.100 +*N chanx_left_in[19]:2 *C 57.078 56.100 +*N chanx_left_in[19]:3 *C 57.455 56.100 +*N chanx_left_in[19]:4 *C 57.500 56.055 +*N chanx_left_in[19]:5 *C 57.500 4.138 +*N chanx_left_in[19]:6 *C 57.492 4.080 +*N chanx_left_in[19]:7 *C 51.230 4.080 + +*CAP +0 chanx_left_in[19] 0.001812465 +1 mux_top_track_2\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[19]:2 4.883115e-05 +3 chanx_left_in[19]:3 4.883115e-05 +4 chanx_left_in[19]:4 0.002479029 +5 chanx_left_in[19]:5 0.002479029 +6 chanx_left_in[19]:6 0.0002777591 +7 chanx_left_in[19]:7 0.002090225 +8 chanx_left_in[19] chanx_left_in[14] 0.0006069721 +9 chanx_left_in[19]:6 chanx_left_in[14]:6 6.50877e-05 +10 chanx_left_in[19]:7 chanx_left_in[14]:7 0.0006720598 +11 chanx_left_in[19]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.075349e-05 +12 chanx_left_in[19]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.295021e-06 +13 chanx_left_in[19]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.295021e-06 +14 chanx_left_in[19]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.075349e-05 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:7 0.007833333 +1 chanx_left_in[19]:2 mux_top_track_2\/mux_l2_in_1_:A1 0.152 +2 chanx_left_in[19]:3 chanx_left_in[19]:2 0.0003370536 +3 chanx_left_in[19]:4 chanx_left_in[19]:3 0.0045 +4 chanx_left_in[19]:5 chanx_left_in[19]:4 0.04635492 +5 chanx_left_in[19]:6 chanx_left_in[19]:5 0.00341 +6 chanx_left_in[19]:7 chanx_left_in[19]:6 0.000981125 + +*END + +*D_NET left_top_grid_pin_45_[0] 0.005654764 //LENGTH 42.745 LUMPCC 0.0001519339 DR + +*CONN +*P left_top_grid_pin_45_[0] I *L 0.29796 *C 5.060 74.870 +*I mux_left_track_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 10.755 64.600 +*I mux_left_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 23.560 72.420 +*I mux_left_track_7\/mux_l1_in_1_:A1 I *L 0.00198 *C 26.680 66.980 +*N left_top_grid_pin_45_[0]:4 *C 26.643 66.980 +*N left_top_grid_pin_45_[0]:5 *C 25.345 66.980 +*N left_top_grid_pin_45_[0]:6 *C 25.300 67.025 +*N left_top_grid_pin_45_[0]:7 *C 25.300 72.420 +*N left_top_grid_pin_45_[0]:8 *C 23.460 72.420 +*N left_top_grid_pin_45_[0]:9 *C 23.460 72.420 +*N left_top_grid_pin_45_[0]:10 *C 23.460 74.075 +*N left_top_grid_pin_45_[0]:11 *C 23.415 74.120 +*N left_top_grid_pin_45_[0]:12 *C 10.718 64.600 +*N left_top_grid_pin_45_[0]:13 *C 9.245 64.600 +*N left_top_grid_pin_45_[0]:14 *C 9.200 64.645 +*N left_top_grid_pin_45_[0]:15 *C 9.200 74.075 +*N left_top_grid_pin_45_[0]:16 *C 9.200 74.120 +*N left_top_grid_pin_45_[0]:17 *C 5.105 74.120 +*N left_top_grid_pin_45_[0]:18 *C 5.060 74.165 + +*CAP +0 left_top_grid_pin_45_[0] 5.57669e-05 +1 mux_left_track_15\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_3\/mux_l1_in_1_:A1 1e-06 +3 mux_left_track_7\/mux_l1_in_1_:A1 1e-06 +4 left_top_grid_pin_45_[0]:4 0.0001013561 +5 left_top_grid_pin_45_[0]:5 0.0001013561 +6 left_top_grid_pin_45_[0]:6 0.0003233611 +7 left_top_grid_pin_45_[0]:7 0.0004157073 +8 left_top_grid_pin_45_[0]:8 3.072518e-05 +9 left_top_grid_pin_45_[0]:9 0.0002117357 +10 left_top_grid_pin_45_[0]:10 0.0001193896 +11 left_top_grid_pin_45_[0]:11 0.0009810819 +12 left_top_grid_pin_45_[0]:12 0.0001453912 +13 left_top_grid_pin_45_[0]:13 0.0001453912 +14 left_top_grid_pin_45_[0]:14 0.0005992225 +15 left_top_grid_pin_45_[0]:15 0.0005992225 +16 left_top_grid_pin_45_[0]:16 0.001314096 +17 left_top_grid_pin_45_[0]:17 0.0003002592 +18 left_top_grid_pin_45_[0]:18 5.57669e-05 +19 left_top_grid_pin_45_[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.073689e-05 +20 left_top_grid_pin_45_[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.523004e-05 +21 left_top_grid_pin_45_[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.523004e-05 +22 left_top_grid_pin_45_[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.073689e-05 + +*RES +0 left_top_grid_pin_45_[0] left_top_grid_pin_45_[0]:18 0.0006294643 +1 left_top_grid_pin_45_[0]:5 left_top_grid_pin_45_[0]:4 0.001158482 +2 left_top_grid_pin_45_[0]:6 left_top_grid_pin_45_[0]:5 0.0045 +3 left_top_grid_pin_45_[0]:4 mux_left_track_7\/mux_l1_in_1_:A1 0.152 +4 left_top_grid_pin_45_[0]:8 mux_left_track_3\/mux_l1_in_1_:A1 0.152 +5 left_top_grid_pin_45_[0]:9 left_top_grid_pin_45_[0]:8 0.0045 +6 left_top_grid_pin_45_[0]:9 left_top_grid_pin_45_[0]:7 0.001642857 +7 left_top_grid_pin_45_[0]:16 left_top_grid_pin_45_[0]:15 0.0045 +8 left_top_grid_pin_45_[0]:16 left_top_grid_pin_45_[0]:11 0.01269196 +9 left_top_grid_pin_45_[0]:15 left_top_grid_pin_45_[0]:14 0.008419643 +10 left_top_grid_pin_45_[0]:13 left_top_grid_pin_45_[0]:12 0.001314732 +11 left_top_grid_pin_45_[0]:14 left_top_grid_pin_45_[0]:13 0.0045 +12 left_top_grid_pin_45_[0]:12 mux_left_track_15\/mux_l1_in_0_:A0 0.152 +13 left_top_grid_pin_45_[0]:17 left_top_grid_pin_45_[0]:16 0.00365625 +14 left_top_grid_pin_45_[0]:18 left_top_grid_pin_45_[0]:17 0.0045 +15 left_top_grid_pin_45_[0]:11 left_top_grid_pin_45_[0]:10 0.0045 +16 left_top_grid_pin_45_[0]:10 left_top_grid_pin_45_[0]:9 0.001477679 +17 left_top_grid_pin_45_[0]:7 left_top_grid_pin_45_[0]:6 0.004816964 + +*END + +*D_NET ccff_head[0] 0.003585731 //LENGTH 36.960 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 108.100 102.070 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 93.095 80.580 +*N ccff_head[0]:2 *C 93.133 80.580 +*N ccff_head[0]:3 *C 108.055 80.580 +*N ccff_head[0]:4 *C 108.100 80.625 + +*CAP +0 ccff_head[0] 0.0009577796 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 0.0008345857 +3 ccff_head[0]:3 0.0008345857 +4 ccff_head[0]:4 0.0009577796 + +*RES +0 ccff_head[0] ccff_head[0]:4 0.01914732 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.01332366 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 + +*END + +*D_NET ropt_net_116 0.005846645 //LENGTH 55.180 LUMPCC 0 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_0_:X O *L 0 *C 90.445 75.480 +*I ropt_mt_inst_723:A I *L 0.001766 *C 78.660 96.560 +*N ropt_net_116:2 *C 78.623 96.560 +*N ropt_net_116:3 *C 78.245 96.560 +*N ropt_net_116:4 *C 78.200 96.605 +*N ropt_net_116:5 *C 78.200 101.615 +*N ropt_net_116:6 *C 78.245 101.660 +*N ropt_net_116:7 *C 81.420 101.660 +*N ropt_net_116:8 *C 81.420 102.000 +*N ropt_net_116:9 *C 91.080 102.000 +*N ropt_net_116:10 *C 91.080 101.660 +*N ropt_net_116:11 *C 91.080 101.615 +*N ropt_net_116:12 *C 91.080 94.565 +*N ropt_net_116:13 *C 91.125 94.520 +*N ropt_net_116:14 *C 94.180 94.520 +*N ropt_net_116:15 *C 94.293 94.475 +*N ropt_net_116:16 *C 94.300 87.720 +*N ropt_net_116:17 *C 92.920 87.720 +*N ropt_net_116:18 *C 92.920 75.525 +*N ropt_net_116:19 *C 92.875 75.480 +*N ropt_net_116:20 *C 90.483 75.480 + +*CAP +0 mux_top_track_0\/mux_l3_in_0_:X 1e-06 +1 ropt_mt_inst_723:A 1e-06 +2 ropt_net_116:2 5.673081e-05 +3 ropt_net_116:3 5.673081e-05 +4 ropt_net_116:4 0.0003155858 +5 ropt_net_116:5 0.0003155858 +6 ropt_net_116:6 0.0002397664 +7 ropt_net_116:7 0.0002657893 +8 ropt_net_116:8 0.0005463686 +9 ropt_net_116:9 0.0005443589 +10 ropt_net_116:10 5.109499e-05 +11 ropt_net_116:11 0.0003488931 +12 ropt_net_116:12 0.0003488931 +13 ropt_net_116:13 0.0002120014 +14 ropt_net_116:14 0.0002120014 +15 ropt_net_116:15 0.0003360345 +16 ropt_net_116:16 0.0004012663 +17 ropt_net_116:17 0.0006636961 +18 ropt_net_116:18 0.0005984643 +19 ropt_net_116:19 0.0001656916 +20 ropt_net_116:20 0.0001656916 + +*RES +0 mux_top_track_0\/mux_l3_in_0_:X ropt_net_116:20 0.152 +1 ropt_net_116:2 ropt_mt_inst_723:A 0.152 +2 ropt_net_116:3 ropt_net_116:2 0.0003370536 +3 ropt_net_116:4 ropt_net_116:3 0.0045 +4 ropt_net_116:6 ropt_net_116:5 0.0045 +5 ropt_net_116:5 ropt_net_116:4 0.004473215 +6 ropt_net_116:10 ropt_net_116:9 0.0003035715 +7 ropt_net_116:11 ropt_net_116:10 0.0045 +8 ropt_net_116:13 ropt_net_116:12 0.0045 +9 ropt_net_116:12 ropt_net_116:11 0.006294643 +10 ropt_net_116:14 ropt_net_116:13 0.002727679 +11 ropt_net_116:15 ropt_net_116:14 0.0045 +12 ropt_net_116:19 ropt_net_116:18 0.0045 +13 ropt_net_116:18 ropt_net_116:17 0.01088839 +14 ropt_net_116:20 ropt_net_116:19 0.002136161 +15 ropt_net_116:7 ropt_net_116:6 0.002834822 +16 ropt_net_116:8 ropt_net_116:7 0.0003035715 +17 ropt_net_116:9 ropt_net_116:8 0.008625001 +18 ropt_net_116:17 ropt_net_116:16 0.001232143 +19 ropt_net_116:16 ropt_net_116:15 0.006031251 + +*END + +*D_NET chany_top_out[3] 0.00137916 //LENGTH 11.400 LUMPCC 0 DR + +*CONN +*I mux_top_track_6\/BUFT_P_87:X O *L 0 *C 71.495 91.120 +*P chany_top_out[3] O *L 0.7423 *C 71.300 102.070 +*N chany_top_out[3]:2 *C 71.300 91.165 +*N chany_top_out[3]:3 *C 71.300 91.120 +*N chany_top_out[3]:4 *C 71.495 91.120 + +*CAP +0 mux_top_track_6\/BUFT_P_87:X 1e-06 +1 chany_top_out[3] 0.0006294854 +2 chany_top_out[3]:2 0.0006294854 +3 chany_top_out[3]:3 5.99008e-05 +4 chany_top_out[3]:4 5.928825e-05 + +*RES +0 mux_top_track_6\/BUFT_P_87:X chany_top_out[3]:4 0.152 +1 chany_top_out[3]:4 chany_top_out[3]:3 0.0001059783 +2 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +3 chany_top_out[3]:2 chany_top_out[3] 0.009736608 + +*END + +*D_NET chany_top_out[5] 0.00568781 //LENGTH 52.485 LUMPCC 0.001112975 DR + +*CONN +*I mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 86.940 53.380 +*P chany_top_out[5] O *L 0.7423 *C 83.720 102.070 +*N chany_top_out[5]:2 *C 83.720 53.765 +*N chany_top_out[5]:3 *C 83.765 53.720 +*N chany_top_out[5]:4 *C 86.940 53.720 +*N chany_top_out[5]:5 *C 86.940 53.380 + +*CAP +0 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[5] 0.002048766 +2 chany_top_out[5]:2 0.002048766 +3 chany_top_out[5]:3 0.0002041717 +4 chany_top_out[5]:4 0.0002268775 +5 chany_top_out[5]:5 4.525365e-05 +6 chany_top_out[5] prog_clk[0]:86 1.896673e-05 +7 chany_top_out[5] prog_clk[0]:104 4.234297e-05 +8 chany_top_out[5] prog_clk[0]:107 2.478155e-05 +9 chany_top_out[5] prog_clk[0]:108 4.519101e-05 +10 chany_top_out[5] prog_clk[0]:124 2.11992e-05 +11 chany_top_out[5] prog_clk[0]:128 5.970427e-05 +12 chany_top_out[5] prog_clk[0]:131 0.0001133695 +13 chany_top_out[5] prog_clk[0]:135 9.099608e-05 +14 chany_top_out[5]:2 prog_clk[0]:98 4.234297e-05 +15 chany_top_out[5]:2 prog_clk[0]:104 2.478155e-05 +16 chany_top_out[5]:2 prog_clk[0]:107 4.519101e-05 +17 chany_top_out[5]:2 prog_clk[0]:121 5.970427e-05 +18 chany_top_out[5]:2 prog_clk[0]:125 2.11992e-05 +19 chany_top_out[5]:2 prog_clk[0]:128 0.0001133695 +20 chany_top_out[5]:2 prog_clk[0]:134 9.099608e-05 +21 chany_top_out[5]:2 prog_clk[0]:135 1.896673e-05 +22 chany_top_out[5] mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 6.232818e-05 +23 chany_top_out[5]:2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 6.232818e-05 +24 chany_top_out[5] mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.760805e-05 +25 chany_top_out[5]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.760805e-05 + +*RES +0 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[5]:5 0.152 +1 chany_top_out[5]:5 chany_top_out[5]:4 0.0003035715 +2 chany_top_out[5]:3 chany_top_out[5]:2 0.0045 +3 chany_top_out[5]:2 chany_top_out[5] 0.04312947 +4 chany_top_out[5]:4 chany_top_out[5]:3 0.002834822 + +*END + +*D_NET chany_top_out[17] 0.001289453 //LENGTH 9.130 LUMPCC 0 DR + +*CONN +*I mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 61.700 93.840 +*P chany_top_out[17] O *L 0.7423 *C 62.100 102.070 +*N chany_top_out[17]:2 *C 62.100 101.320 +*N chany_top_out[17]:3 *C 61.640 101.320 +*N chany_top_out[17]:4 *C 61.640 93.885 +*N chany_top_out[17]:5 *C 61.640 93.840 + +*CAP +0 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[17] 5.313778e-05 +2 chany_top_out[17]:2 8.088068e-05 +3 chany_top_out[17]:3 0.0005725689 +4 chany_top_out[17]:4 0.000544826 +5 chany_top_out[17]:5 3.703925e-05 + +*RES +0 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[17]:5 0.152 +1 chany_top_out[17]:5 chany_top_out[17]:4 0.0045 +2 chany_top_out[17]:4 chany_top_out[17]:3 0.006638393 +3 chany_top_out[17]:3 chany_top_out[17]:2 0.0004107143 +4 chany_top_out[17]:2 chany_top_out[17] 0.0006696429 + +*END + +*D_NET chanx_left_out[4] 0.006544582 //LENGTH 66.585 LUMPCC 0.0002616568 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 36.560 38.760 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 11.560 +*N chanx_left_out[4]:2 *C 38.172 11.560 +*N chanx_left_out[4]:3 *C 38.180 11.617 +*N chanx_left_out[4]:4 *C 38.180 38.715 +*N chanx_left_out[4]:5 *C 38.135 38.760 +*N chanx_left_out[4]:6 *C 36.598 38.760 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 chanx_left_out[4] 0.001700877 +2 chanx_left_out[4]:2 0.001700877 +3 chanx_left_out[4]:3 0.001313652 +4 chanx_left_out[4]:4 0.001313652 +5 chanx_left_out[4]:5 0.0001264347 +6 chanx_left_out[4]:6 0.0001264347 +7 chanx_left_out[4]:4 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 7.529467e-05 +8 chanx_left_out[4]:3 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 7.529467e-05 +9 chanx_left_out[4] ropt_net_135:6 5.553371e-05 +10 chanx_left_out[4]:2 ropt_net_135:7 5.553371e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X chanx_left_out[4]:6 0.152 +1 chanx_left_out[4]:6 chanx_left_out[4]:5 0.001372768 +2 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +3 chanx_left_out[4]:4 chanx_left_out[4]:3 0.0241942 +4 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.005787658 + +*END + +*D_NET chanx_left_out[11] 0.001266491 //LENGTH 9.685 LUMPCC 0 DR + +*CONN +*I mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.680 31.280 +*P chanx_left_out[11] O *L 0.7423 *C 1.305 38.080 +*N chanx_left_out[11]:2 *C 3.673 38.080 +*N chanx_left_out[11]:3 *C 3.680 38.023 +*N chanx_left_out[11]:4 *C 3.680 31.325 +*N chanx_left_out[11]:5 *C 3.680 31.280 + +*CAP +0 mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[11] 0.0002034468 +2 chanx_left_out[11]:2 0.0002034468 +3 chanx_left_out[11]:3 0.0004114007 +4 chanx_left_out[11]:4 0.0004114007 +5 chanx_left_out[11]:5 3.579635e-05 + +*RES +0 mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[11]:5 0.152 +1 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 +2 chanx_left_out[11]:2 chanx_left_out[11] 0.0003709083 +3 chanx_left_out[11]:5 chanx_left_out[11]:4 0.0045 +4 chanx_left_out[11]:4 chanx_left_out[11]:3 0.005979911 + +*END + +*D_NET mux_tree_tapbuf_size2_13_sram[0] 0.002555583 //LENGTH 21.610 LUMPCC 0 DR + +*CONN +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.985 69.700 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.795 66.300 +*I mux_top_track_38\/mux_l1_in_0_:S I *L 0.00357 *C 58.320 68.680 +*N mux_tree_tapbuf_size2_13_sram[0]:3 *C 58.320 68.680 +*N mux_tree_tapbuf_size2_13_sram[0]:4 *C 58.420 68.635 +*N mux_tree_tapbuf_size2_13_sram[0]:5 *C 58.420 66.345 +*N mux_tree_tapbuf_size2_13_sram[0]:6 *C 58.465 66.300 +*N mux_tree_tapbuf_size2_13_sram[0]:7 *C 67.795 66.300 +*N mux_tree_tapbuf_size2_13_sram[0]:8 *C 69.415 66.300 +*N mux_tree_tapbuf_size2_13_sram[0]:9 *C 69.460 66.345 +*N mux_tree_tapbuf_size2_13_sram[0]:10 *C 69.460 69.655 +*N mux_tree_tapbuf_size2_13_sram[0]:11 *C 69.505 69.700 +*N mux_tree_tapbuf_size2_13_sram[0]:12 *C 72.948 69.700 + +*CAP +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_38\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_13_sram[0]:3 2.976462e-05 +4 mux_tree_tapbuf_size2_13_sram[0]:4 0.0001461453 +5 mux_tree_tapbuf_size2_13_sram[0]:5 0.0001461453 +6 mux_tree_tapbuf_size2_13_sram[0]:6 0.0005461322 +7 mux_tree_tapbuf_size2_13_sram[0]:7 0.0006903443 +8 mux_tree_tapbuf_size2_13_sram[0]:8 0.0001152201 +9 mux_tree_tapbuf_size2_13_sram[0]:9 0.0002051608 +10 mux_tree_tapbuf_size2_13_sram[0]:10 0.0002051608 +11 mux_tree_tapbuf_size2_13_sram[0]:11 0.0002342545 +12 mux_tree_tapbuf_size2_13_sram[0]:12 0.0002342545 + +*RES +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_13_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_13_sram[0]:7 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_13_sram[0]:7 mux_tree_tapbuf_size2_13_sram[0]:6 0.008330356 +3 mux_tree_tapbuf_size2_13_sram[0]:8 mux_tree_tapbuf_size2_13_sram[0]:7 0.001446429 +4 mux_tree_tapbuf_size2_13_sram[0]:9 mux_tree_tapbuf_size2_13_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size2_13_sram[0]:11 mux_tree_tapbuf_size2_13_sram[0]:10 0.0045 +6 mux_tree_tapbuf_size2_13_sram[0]:10 mux_tree_tapbuf_size2_13_sram[0]:9 0.002955357 +7 mux_tree_tapbuf_size2_13_sram[0]:12 mux_tree_tapbuf_size2_13_sram[0]:11 0.003073661 +8 mux_tree_tapbuf_size2_13_sram[0]:6 mux_tree_tapbuf_size2_13_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size2_13_sram[0]:5 mux_tree_tapbuf_size2_13_sram[0]:4 0.002044643 +10 mux_tree_tapbuf_size2_13_sram[0]:3 mux_top_track_38\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size2_13_sram[0]:4 mux_tree_tapbuf_size2_13_sram[0]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_16_sram[0] 0.00207748 //LENGTH 16.430 LUMPCC 0.0001086842 DR + +*CONN +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.430 60.520 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.915 55.420 +*I mux_left_track_15\/mux_l1_in_0_:S I *L 0.00357 *C 11.860 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:3 *C 11.845 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:4 *C 11.523 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:5 *C 11.500 63.875 +*N mux_tree_tapbuf_size2_16_sram[0]:6 *C 8.938 55.393 +*N mux_tree_tapbuf_size2_16_sram[0]:7 *C 8.950 55.080 +*N mux_tree_tapbuf_size2_16_sram[0]:8 *C 11.455 55.080 +*N mux_tree_tapbuf_size2_16_sram[0]:9 *C 11.500 55.125 +*N mux_tree_tapbuf_size2_16_sram[0]:10 *C 11.500 60.520 +*N mux_tree_tapbuf_size2_16_sram[0]:11 *C 11.545 60.520 +*N mux_tree_tapbuf_size2_16_sram[0]:12 *C 14.393 60.520 + +*CAP +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_15\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_16_sram[0]:3 2.96142e-05 +4 mux_tree_tapbuf_size2_16_sram[0]:4 2.96142e-05 +5 mux_tree_tapbuf_size2_16_sram[0]:5 0.0001918972 +6 mux_tree_tapbuf_size2_16_sram[0]:6 3.098734e-05 +7 mux_tree_tapbuf_size2_16_sram[0]:7 0.0002141525 +8 mux_tree_tapbuf_size2_16_sram[0]:8 0.0001831652 +9 mux_tree_tapbuf_size2_16_sram[0]:9 0.0003097413 +10 mux_tree_tapbuf_size2_16_sram[0]:10 0.0005378499 +11 mux_tree_tapbuf_size2_16_sram[0]:11 0.0002193868 +12 mux_tree_tapbuf_size2_16_sram[0]:12 0.0002193868 +13 mux_tree_tapbuf_size2_16_sram[0]:9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.771409e-06 +14 mux_tree_tapbuf_size2_16_sram[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 3.057554e-05 +15 mux_tree_tapbuf_size2_16_sram[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.057554e-05 +16 mux_tree_tapbuf_size2_16_sram[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.399515e-05 +17 mux_tree_tapbuf_size2_16_sram[0]:10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.771409e-06 +18 mux_tree_tapbuf_size2_16_sram[0]:10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.399515e-05 + +*RES +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_16_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_16_sram[0]:8 mux_tree_tapbuf_size2_16_sram[0]:7 0.002236607 +2 mux_tree_tapbuf_size2_16_sram[0]:9 mux_tree_tapbuf_size2_16_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size2_16_sram[0]:6 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size2_16_sram[0]:3 mux_left_track_15\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_16_sram[0]:4 mux_tree_tapbuf_size2_16_sram[0]:3 0.0001752718 +6 mux_tree_tapbuf_size2_16_sram[0]:5 mux_tree_tapbuf_size2_16_sram[0]:4 0.0045 +7 mux_tree_tapbuf_size2_16_sram[0]:12 mux_tree_tapbuf_size2_16_sram[0]:11 0.002542411 +8 mux_tree_tapbuf_size2_16_sram[0]:11 mux_tree_tapbuf_size2_16_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size2_16_sram[0]:10 mux_tree_tapbuf_size2_16_sram[0]:9 0.004816964 +10 mux_tree_tapbuf_size2_16_sram[0]:10 mux_tree_tapbuf_size2_16_sram[0]:5 0.002995536 +11 mux_tree_tapbuf_size2_16_sram[0]:7 mux_tree_tapbuf_size2_16_sram[0]:6 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size2_19_sram[0] 0.002092682 //LENGTH 17.390 LUMPCC 0 DR + +*CONN +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 33.885 31.620 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 29.155 26.180 +*I mux_left_track_21\/mux_l1_in_0_:S I *L 0.00357 *C 30.920 34.295 +*N mux_tree_tapbuf_size2_19_sram[0]:3 *C 30.920 34.295 +*N mux_tree_tapbuf_size2_19_sram[0]:4 *C 30.978 34.000 +*N mux_tree_tapbuf_size2_19_sram[0]:5 *C 29.193 26.180 +*N mux_tree_tapbuf_size2_19_sram[0]:6 *C 31.695 26.180 +*N mux_tree_tapbuf_size2_19_sram[0]:7 *C 31.740 26.225 +*N mux_tree_tapbuf_size2_19_sram[0]:8 *C 31.740 33.955 +*N mux_tree_tapbuf_size2_19_sram[0]:9 *C 31.740 34.000 +*N mux_tree_tapbuf_size2_19_sram[0]:10 *C 33.535 34.000 +*N mux_tree_tapbuf_size2_19_sram[0]:11 *C 33.580 33.955 +*N mux_tree_tapbuf_size2_19_sram[0]:12 *C 33.580 31.665 +*N mux_tree_tapbuf_size2_19_sram[0]:13 *C 33.580 31.620 +*N mux_tree_tapbuf_size2_19_sram[0]:14 *C 33.885 31.620 + +*CAP +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_21\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_19_sram[0]:3 5.345552e-05 +4 mux_tree_tapbuf_size2_19_sram[0]:4 7.966622e-05 +5 mux_tree_tapbuf_size2_19_sram[0]:5 0.0001918677 +6 mux_tree_tapbuf_size2_19_sram[0]:6 0.0001918677 +7 mux_tree_tapbuf_size2_19_sram[0]:7 0.0004383971 +8 mux_tree_tapbuf_size2_19_sram[0]:8 0.0004383971 +9 mux_tree_tapbuf_size2_19_sram[0]:9 0.0001995382 +10 mux_tree_tapbuf_size2_19_sram[0]:10 0.0001147096 +11 mux_tree_tapbuf_size2_19_sram[0]:11 0.0001374004 +12 mux_tree_tapbuf_size2_19_sram[0]:12 0.0001374004 +13 mux_tree_tapbuf_size2_19_sram[0]:13 5.678429e-05 +14 mux_tree_tapbuf_size2_19_sram[0]:14 5.019804e-05 + +*RES +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_19_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_19_sram[0]:5 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_19_sram[0]:6 mux_tree_tapbuf_size2_19_sram[0]:5 0.002234375 +3 mux_tree_tapbuf_size2_19_sram[0]:7 mux_tree_tapbuf_size2_19_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size2_19_sram[0]:9 mux_tree_tapbuf_size2_19_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size2_19_sram[0]:9 mux_tree_tapbuf_size2_19_sram[0]:4 0.0006808036 +6 mux_tree_tapbuf_size2_19_sram[0]:8 mux_tree_tapbuf_size2_19_sram[0]:7 0.006901786 +7 mux_tree_tapbuf_size2_19_sram[0]:3 mux_left_track_21\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_19_sram[0]:10 mux_tree_tapbuf_size2_19_sram[0]:9 0.001602679 +9 mux_tree_tapbuf_size2_19_sram[0]:11 mux_tree_tapbuf_size2_19_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_19_sram[0]:13 mux_tree_tapbuf_size2_19_sram[0]:12 0.0045 +11 mux_tree_tapbuf_size2_19_sram[0]:12 mux_tree_tapbuf_size2_19_sram[0]:11 0.002044643 +12 mux_tree_tapbuf_size2_19_sram[0]:14 mux_tree_tapbuf_size2_19_sram[0]:13 0.0001657609 +13 mux_tree_tapbuf_size2_19_sram[0]:4 mux_tree_tapbuf_size2_19_sram[0]:3 0.0001715116 + +*END + +*D_NET mux_tree_tapbuf_size2_21_sram[1] 0.002494636 //LENGTH 16.805 LUMPCC 0.0003747724 DR + +*CONN +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 44.925 61.200 +*I mux_left_track_27\/mux_l2_in_0_:S I *L 0.00357 *C 34.140 63.630 +*I mem_left_track_27\/FTB_34__39:A I *L 0.001746 *C 32.660 63.920 +*N mux_tree_tapbuf_size2_21_sram[1]:3 *C 32.698 63.920 +*N mux_tree_tapbuf_size2_21_sram[1]:4 *C 34.083 63.920 +*N mux_tree_tapbuf_size2_21_sram[1]:5 *C 34.140 63.630 +*N mux_tree_tapbuf_size2_21_sram[1]:6 *C 34.140 63.240 +*N mux_tree_tapbuf_size2_21_sram[1]:7 *C 36.295 63.240 +*N mux_tree_tapbuf_size2_21_sram[1]:8 *C 36.340 63.195 +*N mux_tree_tapbuf_size2_21_sram[1]:9 *C 36.340 61.938 +*N mux_tree_tapbuf_size2_21_sram[1]:10 *C 36.348 61.880 +*N mux_tree_tapbuf_size2_21_sram[1]:11 *C 44.613 61.880 +*N mux_tree_tapbuf_size2_21_sram[1]:12 *C 44.620 61.823 +*N mux_tree_tapbuf_size2_21_sram[1]:13 *C 44.620 61.245 +*N mux_tree_tapbuf_size2_21_sram[1]:14 *C 44.620 61.200 +*N mux_tree_tapbuf_size2_21_sram[1]:15 *C 44.925 61.200 + +*CAP +0 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_27\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_27\/FTB_34__39:A 1e-06 +3 mux_tree_tapbuf_size2_21_sram[1]:3 0.0001265793 +4 mux_tree_tapbuf_size2_21_sram[1]:4 0.0001545265 +5 mux_tree_tapbuf_size2_21_sram[1]:5 8.794322e-05 +6 mux_tree_tapbuf_size2_21_sram[1]:6 0.0001505132 +7 mux_tree_tapbuf_size2_21_sram[1]:7 0.0001196654 +8 mux_tree_tapbuf_size2_21_sram[1]:8 8.45504e-05 +9 mux_tree_tapbuf_size2_21_sram[1]:9 8.45504e-05 +10 mux_tree_tapbuf_size2_21_sram[1]:10 0.0005436878 +11 mux_tree_tapbuf_size2_21_sram[1]:11 0.0005436878 +12 mux_tree_tapbuf_size2_21_sram[1]:12 5.895954e-05 +13 mux_tree_tapbuf_size2_21_sram[1]:13 5.895954e-05 +14 mux_tree_tapbuf_size2_21_sram[1]:14 5.174307e-05 +15 mux_tree_tapbuf_size2_21_sram[1]:15 5.149715e-05 +16 mux_tree_tapbuf_size2_21_sram[1]:8 top_left_grid_pin_37_[0]:20 4.587831e-06 +17 mux_tree_tapbuf_size2_21_sram[1]:9 top_left_grid_pin_37_[0]:19 4.587831e-06 +18 mux_tree_tapbuf_size2_21_sram[1]:10 top_left_grid_pin_37_[0]:17 4.61141e-05 +19 mux_tree_tapbuf_size2_21_sram[1]:10 top_left_grid_pin_37_[0]:18 7.689283e-05 +20 mux_tree_tapbuf_size2_21_sram[1]:11 top_left_grid_pin_37_[0]:8 4.61141e-05 +21 mux_tree_tapbuf_size2_21_sram[1]:11 top_left_grid_pin_37_[0]:17 7.689283e-05 +22 mux_tree_tapbuf_size2_21_sram[1]:7 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.979144e-05 +23 mux_tree_tapbuf_size2_21_sram[1]:6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.979144e-05 + +*RES +0 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_21_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_21_sram[1]:7 mux_tree_tapbuf_size2_21_sram[1]:6 0.001924107 +2 mux_tree_tapbuf_size2_21_sram[1]:8 mux_tree_tapbuf_size2_21_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size2_21_sram[1]:9 mux_tree_tapbuf_size2_21_sram[1]:8 0.001122768 +4 mux_tree_tapbuf_size2_21_sram[1]:10 mux_tree_tapbuf_size2_21_sram[1]:9 0.00341 +5 mux_tree_tapbuf_size2_21_sram[1]:12 mux_tree_tapbuf_size2_21_sram[1]:11 0.00341 +6 mux_tree_tapbuf_size2_21_sram[1]:11 mux_tree_tapbuf_size2_21_sram[1]:10 0.00129485 +7 mux_tree_tapbuf_size2_21_sram[1]:14 mux_tree_tapbuf_size2_21_sram[1]:13 0.0045 +8 mux_tree_tapbuf_size2_21_sram[1]:13 mux_tree_tapbuf_size2_21_sram[1]:12 0.000515625 +9 mux_tree_tapbuf_size2_21_sram[1]:15 mux_tree_tapbuf_size2_21_sram[1]:14 0.0001657609 +10 mux_tree_tapbuf_size2_21_sram[1]:5 mux_left_track_27\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size2_21_sram[1]:5 mux_tree_tapbuf_size2_21_sram[1]:4 0.0001686047 +12 mux_tree_tapbuf_size2_21_sram[1]:3 mem_left_track_27\/FTB_34__39:A 0.152 +13 mux_tree_tapbuf_size2_21_sram[1]:4 mux_tree_tapbuf_size2_21_sram[1]:3 0.001236607 +14 mux_tree_tapbuf_size2_21_sram[1]:6 mux_tree_tapbuf_size2_21_sram[1]:5 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[0] 0.001943684 //LENGTH 15.575 LUMPCC 0 DR + +*CONN +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 70.225 88.060 +*I mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 74.695 86.020 +*I mux_top_track_20\/mux_l1_in_0_:S I *L 0.00357 *C 76.240 79.900 +*N mux_tree_tapbuf_size2_5_sram[0]:3 *C 76.203 79.900 +*N mux_tree_tapbuf_size2_5_sram[0]:4 *C 75.485 79.900 +*N mux_tree_tapbuf_size2_5_sram[0]:5 *C 75.440 79.945 +*N mux_tree_tapbuf_size2_5_sram[0]:6 *C 75.440 85.975 +*N mux_tree_tapbuf_size2_5_sram[0]:7 *C 75.395 86.020 +*N mux_tree_tapbuf_size2_5_sram[0]:8 *C 74.695 86.020 +*N mux_tree_tapbuf_size2_5_sram[0]:9 *C 70.425 86.020 +*N mux_tree_tapbuf_size2_5_sram[0]:10 *C 70.380 86.065 +*N mux_tree_tapbuf_size2_5_sram[0]:11 *C 70.380 88.015 +*N mux_tree_tapbuf_size2_5_sram[0]:12 *C 70.380 88.060 +*N mux_tree_tapbuf_size2_5_sram[0]:13 *C 70.225 88.060 + +*CAP +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_20\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[0]:3 6.41349e-05 +4 mux_tree_tapbuf_size2_5_sram[0]:4 6.41349e-05 +5 mux_tree_tapbuf_size2_5_sram[0]:5 0.0003926773 +6 mux_tree_tapbuf_size2_5_sram[0]:6 0.0003926773 +7 mux_tree_tapbuf_size2_5_sram[0]:7 5.698519e-05 +8 mux_tree_tapbuf_size2_5_sram[0]:8 0.0003588778 +9 mux_tree_tapbuf_size2_5_sram[0]:9 0.0002725493 +10 mux_tree_tapbuf_size2_5_sram[0]:10 0.0001182249 +11 mux_tree_tapbuf_size2_5_sram[0]:11 0.0001182249 +12 mux_tree_tapbuf_size2_5_sram[0]:12 5.138939e-05 +13 mux_tree_tapbuf_size2_5_sram[0]:13 5.080792e-05 + +*RES +0 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_5_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_5_sram[0]:3 mux_top_track_20\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_5_sram[0]:4 mux_tree_tapbuf_size2_5_sram[0]:3 0.000640625 +3 mux_tree_tapbuf_size2_5_sram[0]:5 mux_tree_tapbuf_size2_5_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_5_sram[0]:7 mux_tree_tapbuf_size2_5_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size2_5_sram[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 0.005383929 +6 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:8 0.0038125 +7 mux_tree_tapbuf_size2_5_sram[0]:10 mux_tree_tapbuf_size2_5_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size2_5_sram[0]:12 mux_tree_tapbuf_size2_5_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:10 0.001741072 +10 mux_tree_tapbuf_size2_5_sram[0]:13 mux_tree_tapbuf_size2_5_sram[0]:12 8.423912e-05 +11 mux_tree_tapbuf_size2_5_sram[0]:8 mem_top_track_20\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:7 0.000625 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[0] 0.001898476 //LENGTH 16.055 LUMPCC 0.0002779017 DR + +*CONN +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 39.405 91.460 +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 33.755 86.020 +*I mux_top_track_30\/mux_l1_in_0_:S I *L 0.00357 *C 37.140 83.300 +*N mux_tree_tapbuf_size2_9_sram[0]:3 *C 37.178 83.300 +*N mux_tree_tapbuf_size2_9_sram[0]:4 *C 37.675 83.300 +*N mux_tree_tapbuf_size2_9_sram[0]:5 *C 37.720 83.345 +*N mux_tree_tapbuf_size2_9_sram[0]:6 *C 33.793 86.020 +*N mux_tree_tapbuf_size2_9_sram[0]:7 *C 37.675 86.020 +*N mux_tree_tapbuf_size2_9_sram[0]:8 *C 37.720 86.020 +*N mux_tree_tapbuf_size2_9_sram[0]:9 *C 38.180 86.020 +*N mux_tree_tapbuf_size2_9_sram[0]:10 *C 38.180 91.415 +*N mux_tree_tapbuf_size2_9_sram[0]:11 *C 38.225 91.460 +*N mux_tree_tapbuf_size2_9_sram[0]:12 *C 39.367 91.460 + +*CAP +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_30\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_9_sram[0]:3 6.166681e-05 +4 mux_tree_tapbuf_size2_9_sram[0]:4 6.166681e-05 +5 mux_tree_tapbuf_size2_9_sram[0]:5 0.0001183423 +6 mux_tree_tapbuf_size2_9_sram[0]:6 0.0002592563 +7 mux_tree_tapbuf_size2_9_sram[0]:7 0.0002592563 +8 mux_tree_tapbuf_size2_9_sram[0]:8 0.0001499105 +9 mux_tree_tapbuf_size2_9_sram[0]:9 0.000280452 +10 mux_tree_tapbuf_size2_9_sram[0]:10 0.0002488839 +11 mux_tree_tapbuf_size2_9_sram[0]:11 8.906987e-05 +12 mux_tree_tapbuf_size2_9_sram[0]:12 8.906987e-05 +13 mux_tree_tapbuf_size2_9_sram[0]:5 top_left_grid_pin_40_[0]:24 7.922788e-05 +14 mux_tree_tapbuf_size2_9_sram[0]:8 top_left_grid_pin_40_[0]:25 7.922788e-05 +15 mux_tree_tapbuf_size2_9_sram[0]:10 top_left_grid_pin_40_[0]:25 5.972298e-05 +16 mux_tree_tapbuf_size2_9_sram[0]:9 top_left_grid_pin_40_[0]:24 5.972298e-05 + +*RES +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_9_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_9_sram[0]:3 mux_top_track_30\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_9_sram[0]:4 mux_tree_tapbuf_size2_9_sram[0]:3 0.0004441965 +3 mux_tree_tapbuf_size2_9_sram[0]:5 mux_tree_tapbuf_size2_9_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_9_sram[0]:7 mux_tree_tapbuf_size2_9_sram[0]:6 0.003466518 +5 mux_tree_tapbuf_size2_9_sram[0]:8 mux_tree_tapbuf_size2_9_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_9_sram[0]:8 mux_tree_tapbuf_size2_9_sram[0]:5 0.002388393 +7 mux_tree_tapbuf_size2_9_sram[0]:6 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_9_sram[0]:11 mux_tree_tapbuf_size2_9_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size2_9_sram[0]:10 mux_tree_tapbuf_size2_9_sram[0]:9 0.004816965 +10 mux_tree_tapbuf_size2_9_sram[0]:12 mux_tree_tapbuf_size2_9_sram[0]:11 0.001020089 +11 mux_tree_tapbuf_size2_9_sram[0]:9 mux_tree_tapbuf_size2_9_sram[0]:8 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_12_ccff_tail[0] 0.0007022631 //LENGTH 5.020 LUMPCC 0.000175514 DR + +*CONN +*I mem_top_track_36\/FTB_25__30:X O *L 0 *C 69.685 71.740 +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.335 69.700 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 *C 67.335 69.700 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 *C 67.620 69.700 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 *C 67.620 69.745 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 *C 67.620 71.695 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 *C 67.665 71.740 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 *C 69.648 71.740 + +*CAP +0 mem_top_track_36\/FTB_25__30:X 1e-06 +1 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 4.871302e-05 +3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 5.282766e-05 +4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 0.000131202 +5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 0.000131202 +6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 8.040213e-05 +7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 8.040213e-05 +8 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 mux_tree_tapbuf_size2_13_sram[1]:11 8.775701e-05 +9 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 mux_tree_tapbuf_size2_13_sram[1]:12 8.775701e-05 + +*RES +0 mem_top_track_36\/FTB_25__30:X mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 0.001741071 +6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_19_ccff_tail[0] 0.0005213775 //LENGTH 3.280 LUMPCC 0.0001505893 DR + +*CONN +*I mem_left_track_21\/FTB_32__37:X O *L 0 *C 37.550 23.800 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 37.885 26.180 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:2 *C 37.885 26.180 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:3 *C 37.720 26.180 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 *C 37.720 26.135 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 *C 37.720 23.845 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:6 *C 37.720 23.800 +*N mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:7 *C 37.550 23.800 + +*CAP +0 mem_left_track_21\/FTB_32__37:X 1e-06 +1 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:2 5.252768e-05 +3 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:3 5.243077e-05 +4 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 8.390923e-05 +5 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 8.390923e-05 +6 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:6 5.003736e-05 +7 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:7 4.597383e-05 +8 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 chanx_left_out[4]:4 7.529467e-05 +9 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 chanx_left_out[4]:3 7.529467e-05 + +*RES +0 mem_left_track_21\/FTB_32__37:X mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:2 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:2 8.967391e-05 +3 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_19_ccff_tail[0]:6 9.239131e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_5_ccff_tail[0] 0.0005634541 //LENGTH 4.315 LUMPCC 0 DR + +*CONN +*I mem_top_track_20\/FTB_18__23:X O *L 0 *C 85.740 80.580 +*I mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 84.365 82.620 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 *C 84.365 82.620 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 *C 85.055 82.620 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 *C 85.100 82.575 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 *C 85.100 80.625 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 *C 85.145 80.580 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 *C 85.703 80.580 + +*CAP +0 mem_top_track_20\/FTB_18__23:X 1e-06 +1 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.000116031 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 7.582091e-05 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.0001312362 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0001312362 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 5.356489e-05 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 5.356489e-05 + +*RES +0 mem_top_track_20\/FTB_18__23:X mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 mem_top_track_22\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 0.0006160715 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0004977679 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001220725 //LENGTH 9.340 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 75.745 98.940 +*I mem_top_track_24\/FTB_10__15:A I *L 0.001746 *C 73.140 93.840 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 74.980 96.395 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 74.980 96.395 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 73.140 93.840 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 73.140 93.885 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 73.140 96.855 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 73.185 96.900 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 74.980 96.900 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 75.395 96.900 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 75.440 96.945 +*N mux_tree_tapbuf_size3_1_sram[1]:11 *C 75.440 98.895 +*N mux_tree_tapbuf_size3_1_sram[1]:12 *C 75.440 98.940 +*N mux_tree_tapbuf_size3_1_sram[1]:13 *C 75.745 98.940 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_24\/FTB_10__15:A 1e-06 +2 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 6.593681e-05 +4 mux_tree_tapbuf_size3_1_sram[1]:4 3.317375e-05 +5 mux_tree_tapbuf_size3_1_sram[1]:5 0.0001825204 +6 mux_tree_tapbuf_size3_1_sram[1]:6 0.0001825204 +7 mux_tree_tapbuf_size3_1_sram[1]:7 0.0001137041 +8 mux_tree_tapbuf_size3_1_sram[1]:8 0.0001858557 +9 mux_tree_tapbuf_size3_1_sram[1]:9 3.524827e-05 +10 mux_tree_tapbuf_size3_1_sram[1]:10 0.0001512978 +11 mux_tree_tapbuf_size3_1_sram[1]:11 0.0001512978 +12 mux_tree_tapbuf_size3_1_sram[1]:12 6.010832e-05 +13 mux_tree_tapbuf_size3_1_sram[1]:13 5.606159e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:3 mux_top_track_24\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size3_1_sram[1]:6 mux_tree_tapbuf_size3_1_sram[1]:5 0.002651786 +4 mux_tree_tapbuf_size3_1_sram[1]:4 mem_top_track_24\/FTB_10__15:A 0.152 +5 mux_tree_tapbuf_size3_1_sram[1]:5 mux_tree_tapbuf_size3_1_sram[1]:4 0.0045 +6 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.0003705357 +7 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size3_1_sram[1]:12 mux_tree_tapbuf_size3_1_sram[1]:11 0.0045 +9 mux_tree_tapbuf_size3_1_sram[1]:11 mux_tree_tapbuf_size3_1_sram[1]:10 0.001741071 +10 mux_tree_tapbuf_size3_1_sram[1]:13 mux_tree_tapbuf_size3_1_sram[1]:12 0.0001657609 +11 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.001602679 +12 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:3 0.0004508929 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.00103895 //LENGTH 9.080 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/FTB_9__14:X O *L 0 *C 85.785 37.060 +*I mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.995 37.060 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 77.032 37.060 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 85.748 37.060 + +*CAP +0 mem_top_track_8\/FTB_9__14:X 1e-06 +1 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.000518475 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.000518475 + +*RES +0 mem_top_track_8\/FTB_9__14:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_top_track_10\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.00778125 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[1] 0.003083749 //LENGTH 24.805 LUMPCC 0.0001716822 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 69.765 60.860 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 64.575 55.420 +*I mux_top_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 59.700 61.200 +*I mux_top_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 57.860 55.685 +*N mux_tree_tapbuf_size5_0_sram[1]:4 *C 57.898 55.745 +*N mux_tree_tapbuf_size5_0_sram[1]:5 *C 59.700 61.200 +*N mux_tree_tapbuf_size5_0_sram[1]:6 *C 59.800 61.155 +*N mux_tree_tapbuf_size5_0_sram[1]:7 *C 59.800 55.805 +*N mux_tree_tapbuf_size5_0_sram[1]:8 *C 59.800 55.730 +*N mux_tree_tapbuf_size5_0_sram[1]:9 *C 59.800 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:10 *C 64.575 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:11 *C 68.955 55.420 +*N mux_tree_tapbuf_size5_0_sram[1]:12 *C 69.000 55.465 +*N mux_tree_tapbuf_size5_0_sram[1]:13 *C 69.000 60.815 +*N mux_tree_tapbuf_size5_0_sram[1]:14 *C 69.045 60.860 +*N mux_tree_tapbuf_size5_0_sram[1]:15 *C 69.728 60.860 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_top_track_2\/mux_l2_in_0_:S 1e-06 +3 mux_top_track_2\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[1]:4 0.0001461401 +5 mux_tree_tapbuf_size5_0_sram[1]:5 2.771768e-05 +6 mux_tree_tapbuf_size5_0_sram[1]:6 0.0003085673 +7 mux_tree_tapbuf_size5_0_sram[1]:7 0.0003085673 +8 mux_tree_tapbuf_size5_0_sram[1]:8 0.0001729849 +9 mux_tree_tapbuf_size5_0_sram[1]:9 0.0003100258 +10 mux_tree_tapbuf_size5_0_sram[1]:10 0.0006201328 +11 mux_tree_tapbuf_size5_0_sram[1]:11 0.0003021422 +12 mux_tree_tapbuf_size5_0_sram[1]:12 0.0002968166 +13 mux_tree_tapbuf_size5_0_sram[1]:13 0.0002968166 +14 mux_tree_tapbuf_size5_0_sram[1]:14 5.907784e-05 +15 mux_tree_tapbuf_size5_0_sram[1]:15 5.907784e-05 +16 mux_tree_tapbuf_size5_0_sram[1]:12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.670088e-06 +17 mux_tree_tapbuf_size5_0_sram[1]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.670088e-06 +18 mux_tree_tapbuf_size5_0_sram[1]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 8.174969e-06 +19 mux_tree_tapbuf_size5_0_sram[1]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 8.174969e-06 +20 mux_tree_tapbuf_size5_0_sram[1]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:9 1.482558e-05 +21 mux_tree_tapbuf_size5_0_sram[1]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.482558e-05 +22 mux_tree_tapbuf_size5_0_sram[1]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:10 6.117046e-05 +23 mux_tree_tapbuf_size5_0_sram[1]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:11 6.117046e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_0_sram[1]:15 0.152 +1 mux_tree_tapbuf_size5_0_sram[1]:11 mux_tree_tapbuf_size5_0_sram[1]:10 0.003910714 +2 mux_tree_tapbuf_size5_0_sram[1]:12 mux_tree_tapbuf_size5_0_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size5_0_sram[1]:14 mux_tree_tapbuf_size5_0_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:12 0.004776786 +5 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:14 0.000609375 +6 mux_tree_tapbuf_size5_0_sram[1]:4 mux_top_track_2\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:4 0.001698661 +9 mux_tree_tapbuf_size5_0_sram[1]:7 mux_tree_tapbuf_size5_0_sram[1]:6 0.004776786 +10 mux_tree_tapbuf_size5_0_sram[1]:5 mux_top_track_2\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size5_0_sram[1]:6 mux_tree_tapbuf_size5_0_sram[1]:5 0.0045 +12 mux_tree_tapbuf_size5_0_sram[1]:10 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:9 0.004263393 +14 mux_tree_tapbuf_size5_0_sram[1]:9 mux_tree_tapbuf_size5_0_sram[1]:8 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[0] 0.00416017 //LENGTH 30.325 LUMPCC 0.0004818256 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 31.125 50.320 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 35.595 58.820 +*I mux_left_track_7\/mux_l1_in_0_:S I *L 0.00357 *C 30.460 66.640 +*I mux_left_track_7\/mux_l1_in_1_:S I *L 0.00357 *C 27.960 66.640 +*N mux_tree_tapbuf_size5_3_sram[0]:4 *C 27.998 66.640 +*N mux_tree_tapbuf_size5_3_sram[0]:5 *C 30.460 66.640 +*N mux_tree_tapbuf_size5_3_sram[0]:6 *C 31.235 66.640 +*N mux_tree_tapbuf_size5_3_sram[0]:7 *C 31.280 66.595 +*N mux_tree_tapbuf_size5_3_sram[0]:8 *C 35.595 58.820 +*N mux_tree_tapbuf_size5_3_sram[0]:9 *C 35.420 58.820 +*N mux_tree_tapbuf_size5_3_sram[0]:10 *C 35.420 58.865 +*N mux_tree_tapbuf_size5_3_sram[0]:11 *C 35.420 62.503 +*N mux_tree_tapbuf_size5_3_sram[0]:12 *C 35.413 62.560 +*N mux_tree_tapbuf_size5_3_sram[0]:13 *C 31.288 62.560 +*N mux_tree_tapbuf_size5_3_sram[0]:14 *C 31.280 62.617 +*N mux_tree_tapbuf_size5_3_sram[0]:15 *C 30.820 62.560 +*N mux_tree_tapbuf_size5_3_sram[0]:16 *C 30.820 50.365 +*N mux_tree_tapbuf_size5_3_sram[0]:17 *C 30.820 50.320 +*N mux_tree_tapbuf_size5_3_sram[0]:18 *C 31.125 50.320 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_7\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_7\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_3_sram[0]:4 0.0001787405 +5 mux_tree_tapbuf_size5_3_sram[0]:5 0.0002750907 +6 mux_tree_tapbuf_size5_3_sram[0]:6 6.702328e-05 +7 mux_tree_tapbuf_size5_3_sram[0]:7 0.0002610173 +8 mux_tree_tapbuf_size5_3_sram[0]:8 4.916671e-05 +9 mux_tree_tapbuf_size5_3_sram[0]:9 5.363044e-05 +10 mux_tree_tapbuf_size5_3_sram[0]:10 0.0002141564 +11 mux_tree_tapbuf_size5_3_sram[0]:11 0.0002141564 +12 mux_tree_tapbuf_size5_3_sram[0]:12 0.0002062658 +13 mux_tree_tapbuf_size5_3_sram[0]:13 0.0002062658 +14 mux_tree_tapbuf_size5_3_sram[0]:14 0.0002957217 +15 mux_tree_tapbuf_size5_3_sram[0]:15 0.000789828 +16 mux_tree_tapbuf_size5_3_sram[0]:16 0.0007551236 +17 mux_tree_tapbuf_size5_3_sram[0]:17 5.72374e-05 +18 mux_tree_tapbuf_size5_3_sram[0]:18 5.092075e-05 +19 mux_tree_tapbuf_size5_3_sram[0]:13 left_top_grid_pin_49_[0]:13 0.0002409128 +20 mux_tree_tapbuf_size5_3_sram[0]:12 left_top_grid_pin_49_[0]:12 0.0002409128 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_3_sram[0]:18 0.152 +1 mux_tree_tapbuf_size5_3_sram[0]:14 mux_tree_tapbuf_size5_3_sram[0]:13 0.00341 +2 mux_tree_tapbuf_size5_3_sram[0]:14 mux_tree_tapbuf_size5_3_sram[0]:7 0.003551339 +3 mux_tree_tapbuf_size5_3_sram[0]:13 mux_tree_tapbuf_size5_3_sram[0]:12 0.00064625 +4 mux_tree_tapbuf_size5_3_sram[0]:11 mux_tree_tapbuf_size5_3_sram[0]:10 0.003247768 +5 mux_tree_tapbuf_size5_3_sram[0]:12 mux_tree_tapbuf_size5_3_sram[0]:11 0.00341 +6 mux_tree_tapbuf_size5_3_sram[0]:9 mux_tree_tapbuf_size5_3_sram[0]:8 9.51087e-05 +7 mux_tree_tapbuf_size5_3_sram[0]:10 mux_tree_tapbuf_size5_3_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size5_3_sram[0]:8 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size5_3_sram[0]:6 mux_tree_tapbuf_size5_3_sram[0]:5 0.0006919644 +10 mux_tree_tapbuf_size5_3_sram[0]:7 mux_tree_tapbuf_size5_3_sram[0]:6 0.0045 +11 mux_tree_tapbuf_size5_3_sram[0]:4 mux_left_track_7\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size5_3_sram[0]:5 mux_left_track_7\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size5_3_sram[0]:5 mux_tree_tapbuf_size5_3_sram[0]:4 0.002198661 +14 mux_tree_tapbuf_size5_3_sram[0]:17 mux_tree_tapbuf_size5_3_sram[0]:16 0.0045 +15 mux_tree_tapbuf_size5_3_sram[0]:16 mux_tree_tapbuf_size5_3_sram[0]:15 0.01088839 +16 mux_tree_tapbuf_size5_3_sram[0]:18 mux_tree_tapbuf_size5_3_sram[0]:17 0.0001657609 +17 mux_tree_tapbuf_size5_3_sram[0]:15 mux_tree_tapbuf_size5_3_sram[0]:14 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.004603328 //LENGTH 33.050 LUMPCC 0.0003081793 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 98.745 80.240 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 90.795 77.180 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 80.400 74.510 +*I mux_top_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 80.400 72.080 +*I mux_top_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 80.400 69.435 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 80.400 69.435 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 80.500 69.700 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 80.500 69.745 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 80.362 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 80.040 72.080 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 80.040 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 80.455 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 80.500 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 80.400 74.510 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 80.500 74.120 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 80.500 74.120 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 80.500 77.135 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 80.545 77.180 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 90.795 77.180 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 97.060 77.180 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 97.060 77.520 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 98.395 77.520 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 98.440 77.565 +*N mux_tree_tapbuf_size6_0_sram[0]:23 *C 98.440 80.195 +*N mux_tree_tapbuf_size6_0_sram[0]:24 *C 98.440 80.240 +*N mux_tree_tapbuf_size6_0_sram[0]:25 *C 98.745 80.240 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +3 mux_top_track_0\/mux_l1_in_1_:S 1e-06 +4 mux_top_track_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 6.49529e-05 +6 mux_tree_tapbuf_size6_0_sram[0]:6 5.30875e-05 +7 mux_tree_tapbuf_size6_0_sram[0]:7 0.0002062638 +8 mux_tree_tapbuf_size6_0_sram[0]:8 4.396674e-05 +9 mux_tree_tapbuf_size6_0_sram[0]:9 8.837612e-05 +10 mux_tree_tapbuf_size6_0_sram[0]:10 0.0001004551 +11 mux_tree_tapbuf_size6_0_sram[0]:11 5.604568e-05 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.0003243657 +13 mux_tree_tapbuf_size6_0_sram[0]:13 6.503218e-05 +14 mux_tree_tapbuf_size6_0_sram[0]:14 6.841829e-05 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0003249561 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.0002064862 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0005835763 +18 mux_tree_tapbuf_size6_0_sram[0]:18 0.001015397 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0004275351 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0001432761 +21 mux_tree_tapbuf_size6_0_sram[0]:21 0.0001199007 +22 mux_tree_tapbuf_size6_0_sram[0]:22 0.0001485766 +23 mux_tree_tapbuf_size6_0_sram[0]:23 0.0001485766 +24 mux_tree_tapbuf_size6_0_sram[0]:24 5.407257e-05 +25 mux_tree_tapbuf_size6_0_sram[0]:25 4.682997e-05 +26 mux_tree_tapbuf_size6_0_sram[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001021341 +27 mux_tree_tapbuf_size6_0_sram[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001021341 +28 mux_tree_tapbuf_size6_0_sram[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.195561e-05 +29 mux_tree_tapbuf_size6_0_sram[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.195561e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:25 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 0.0003482143 +2 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.0045 +3 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:12 0.001214286 +4 mux_tree_tapbuf_size6_0_sram[0]:13 mux_top_track_0\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.0045 +6 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.002691964 +7 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:10 0.0003705357 +8 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:7 0.002691964 +10 mux_tree_tapbuf_size6_0_sram[0]:8 mux_top_track_0\/mux_l1_in_1_:S 0.152 +11 mux_tree_tapbuf_size6_0_sram[0]:18 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.009151787 +13 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.001191964 +14 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.0045 +15 mux_tree_tapbuf_size6_0_sram[0]:24 mux_tree_tapbuf_size6_0_sram[0]:23 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:23 mux_tree_tapbuf_size6_0_sram[0]:22 0.002348215 +17 mux_tree_tapbuf_size6_0_sram[0]:25 mux_tree_tapbuf_size6_0_sram[0]:24 0.0001005435 +18 mux_tree_tapbuf_size6_0_sram[0]:5 mux_top_track_0\/mux_l1_in_2_:S 0.152 +19 mux_tree_tapbuf_size6_0_sram[0]:6 mux_tree_tapbuf_size6_0_sram[0]:5 4.807693e-05 +20 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.0045 +21 mux_tree_tapbuf_size6_0_sram[0]:9 mux_tree_tapbuf_size6_0_sram[0]:8 0.0002879465 +22 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0006071429 +23 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.00559375 +24 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.0003035715 + +*END + +*D_NET optlc_net_107 0.01306867 //LENGTH 95.165 LUMPCC 0.001638532 DR + +*CONN +*I optlc_99:HI O *L 0 *C 23.920 36.720 +*I mux_left_track_19\/mux_l2_in_0_:A0 I *L 0.001631 *C 21.910 28.220 +*I mux_left_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 8.110 27.880 +*I mux_left_track_23\/mux_l2_in_0_:A0 I *L 0.001631 *C 37.550 31.960 +*I mux_left_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 35.595 37.060 +*I mux_left_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 40.655 37.060 +*I mux_left_track_21\/mux_l2_in_0_:A0 I *L 0.001631 *C 31.110 22.780 +*I mux_left_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 18.105 42.840 +*I mux_left_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 9.375 39.100 +*N optlc_net_107:9 *C 9.375 39.100 +*N optlc_net_107:10 *C 9.200 39.100 +*N optlc_net_107:11 *C 9.200 39.145 +*N optlc_net_107:12 *C 9.200 42.795 +*N optlc_net_107:13 *C 9.200 42.840 +*N optlc_net_107:14 *C 6.025 42.840 +*N optlc_net_107:15 *C 5.980 42.840 +*N optlc_net_107:16 *C 5.988 42.840 +*N optlc_net_107:17 *C 17.473 42.840 +*N optlc_net_107:18 *C 17.480 42.840 +*N optlc_net_107:19 *C 17.613 42.840 +*N optlc_net_107:20 *C 18.105 42.840 +*N optlc_net_107:21 *C 22.035 42.840 +*N optlc_net_107:22 *C 22.080 42.795 +*N optlc_net_107:23 *C 31.110 22.780 +*N optlc_net_107:24 *C 31.280 22.780 +*N optlc_net_107:25 *C 31.280 22.825 +*N optlc_net_107:26 *C 40.617 37.060 +*N optlc_net_107:27 *C 35.595 37.060 +*N optlc_net_107:28 *C 35.925 37.060 +*N optlc_net_107:29 *C 35.880 37.060 +*N optlc_net_107:30 *C 36.340 37.060 +*N optlc_net_107:31 *C 37.513 31.960 +*N optlc_net_107:32 *C 36.385 31.960 +*N optlc_net_107:33 *C 36.340 31.960 +*N optlc_net_107:34 *C 36.340 27.258 +*N optlc_net_107:35 *C 36.333 27.200 +*N optlc_net_107:36 *C 31.288 27.200 +*N optlc_net_107:37 *C 31.280 27.200 +*N optlc_net_107:38 *C 31.280 27.835 +*N optlc_net_107:39 *C 31.235 27.880 +*N optlc_net_107:40 *C 8.148 27.880 +*N optlc_net_107:41 *C 22.080 27.880 +*N optlc_net_107:42 *C 21.910 28.220 +*N optlc_net_107:43 *C 22.080 28.220 +*N optlc_net_107:44 *C 22.080 28.265 +*N optlc_net_107:45 *C 22.080 36.380 +*N optlc_net_107:46 *C 22.080 36.380 +*N optlc_net_107:47 *C 22.080 36.720 +*N optlc_net_107:48 *C 23.883 36.720 + +*CAP +0 optlc_99:HI 1e-06 +1 mux_left_track_19\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_17\/mux_l2_in_0_:A0 1e-06 +3 mux_left_track_23\/mux_l2_in_0_:A0 1e-06 +4 mux_left_track_9\/mux_l1_in_1_:A0 1e-06 +5 mux_left_track_25\/mux_l1_in_1_:A0 1e-06 +6 mux_left_track_21\/mux_l2_in_0_:A0 1e-06 +7 mux_left_track_5\/mux_l2_in_1_:A0 1e-06 +8 mux_left_track_1\/mux_l2_in_1_:A0 1e-06 +9 optlc_net_107:9 5.94644e-05 +10 optlc_net_107:10 6.383333e-05 +11 optlc_net_107:11 0.0001801661 +12 optlc_net_107:12 0.0001801661 +13 optlc_net_107:13 0.0002469174 +14 optlc_net_107:14 0.000214747 +15 optlc_net_107:15 3.948693e-05 +16 optlc_net_107:16 0.0008360371 +17 optlc_net_107:17 0.0008360371 +18 optlc_net_107:18 3.537236e-05 +19 optlc_net_107:19 6.000494e-05 +20 optlc_net_107:20 0.0003550581 +21 optlc_net_107:21 0.0002666439 +22 optlc_net_107:22 0.0003552365 +23 optlc_net_107:23 4.422916e-05 +24 optlc_net_107:24 4.833884e-05 +25 optlc_net_107:25 0.000195226 +26 optlc_net_107:26 0.0003187241 +27 optlc_net_107:27 4.835511e-05 +28 optlc_net_107:28 0.0003370949 +29 optlc_net_107:29 6.354955e-05 +30 optlc_net_107:30 0.0003261123 +31 optlc_net_107:31 0.0001092721 +32 optlc_net_107:32 0.0001092721 +33 optlc_net_107:33 0.0006378221 +34 optlc_net_107:34 0.0003135967 +35 optlc_net_107:35 0.000320634 +36 optlc_net_107:36 0.000320634 +37 optlc_net_107:37 0.0002823631 +38 optlc_net_107:38 4.823289e-05 +39 optlc_net_107:39 0.0005978879 +40 optlc_net_107:40 0.0007230815 +41 optlc_net_107:41 0.001340299 +42 optlc_net_107:42 5.906147e-05 +43 optlc_net_107:43 8.271178e-05 +44 optlc_net_107:44 0.0003041074 +45 optlc_net_107:45 0.0006932687 +46 optlc_net_107:46 6.388052e-05 +47 optlc_net_107:47 0.0001668388 +48 optlc_net_107:48 0.0001373708 +49 optlc_net_107:40 mux_tree_tapbuf_size2_17_sram[1]:8 0.0002217024 +50 optlc_net_107:41 mux_tree_tapbuf_size2_17_sram[1]:9 0.0002217024 +51 optlc_net_107:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.792967e-05 +52 optlc_net_107:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.792967e-05 +53 optlc_net_107:20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.490996e-05 +54 optlc_net_107:21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.490996e-05 +55 optlc_net_107:22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.702913e-05 +56 optlc_net_107:45 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.702913e-05 +57 optlc_net_107:45 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001954531 +58 optlc_net_107:48 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.054907e-05 +59 optlc_net_107:44 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001954531 +60 optlc_net_107:47 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.054907e-05 +61 optlc_net_107:40 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001192238 +62 optlc_net_107:41 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001192238 +63 optlc_net_107:38 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.12835e-06 +64 optlc_net_107:25 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.277633e-05 +65 optlc_net_107:37 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.277633e-05 +66 optlc_net_107:37 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.12835e-06 +67 optlc_net_107:14 ropt_net_133:5 4.576866e-05 +68 optlc_net_107:14 ropt_net_133:3 5.795454e-06 +69 optlc_net_107:13 ropt_net_133:2 5.795454e-06 +70 optlc_net_107:13 ropt_net_133:4 4.576866e-05 + +*RES +0 optlc_99:HI optlc_net_107:48 0.152 +1 optlc_net_107:20 mux_left_track_5\/mux_l2_in_1_:A0 0.152 +2 optlc_net_107:20 optlc_net_107:19 0.0004397322 +3 optlc_net_107:19 optlc_net_107:18 0.0045 +4 optlc_net_107:18 optlc_net_107:17 0.00341 +5 optlc_net_107:17 optlc_net_107:16 0.001799316 +6 optlc_net_107:15 optlc_net_107:14 0.0045 +7 optlc_net_107:16 optlc_net_107:15 0.00341 +8 optlc_net_107:14 optlc_net_107:13 0.002834821 +9 optlc_net_107:13 optlc_net_107:12 0.0045 +10 optlc_net_107:12 optlc_net_107:11 0.003258929 +11 optlc_net_107:10 optlc_net_107:9 9.51087e-05 +12 optlc_net_107:11 optlc_net_107:10 0.0045 +13 optlc_net_107:9 mux_left_track_1\/mux_l2_in_1_:A0 0.152 +14 optlc_net_107:21 optlc_net_107:20 0.003508929 +15 optlc_net_107:22 optlc_net_107:21 0.0045 +16 optlc_net_107:28 optlc_net_107:27 0.0001331522 +17 optlc_net_107:28 optlc_net_107:26 0.004189732 +18 optlc_net_107:29 optlc_net_107:28 0.0045 +19 optlc_net_107:46 optlc_net_107:45 0.0045 +20 optlc_net_107:45 optlc_net_107:44 0.007245536 +21 optlc_net_107:45 optlc_net_107:22 0.00572768 +22 optlc_net_107:48 optlc_net_107:47 0.001609375 +23 optlc_net_107:39 optlc_net_107:38 0.0045 +24 optlc_net_107:38 optlc_net_107:37 0.0005669643 +25 optlc_net_107:26 mux_left_track_25\/mux_l1_in_1_:A0 0.152 +26 optlc_net_107:32 optlc_net_107:31 0.001006696 +27 optlc_net_107:33 optlc_net_107:32 0.0045 +28 optlc_net_107:33 optlc_net_107:30 0.004553572 +29 optlc_net_107:31 mux_left_track_23\/mux_l2_in_0_:A0 0.152 +30 optlc_net_107:27 mux_left_track_9\/mux_l1_in_1_:A0 0.152 +31 optlc_net_107:24 optlc_net_107:23 9.239132e-05 +32 optlc_net_107:25 optlc_net_107:24 0.0045 +33 optlc_net_107:23 mux_left_track_21\/mux_l2_in_0_:A0 0.152 +34 optlc_net_107:42 mux_left_track_19\/mux_l2_in_0_:A0 0.152 +35 optlc_net_107:40 mux_left_track_17\/mux_l2_in_0_:A0 0.152 +36 optlc_net_107:37 optlc_net_107:36 0.00341 +37 optlc_net_107:37 optlc_net_107:25 0.00390625 +38 optlc_net_107:36 optlc_net_107:35 0.0007903833 +39 optlc_net_107:34 optlc_net_107:33 0.004198661 +40 optlc_net_107:35 optlc_net_107:34 0.00341 +41 optlc_net_107:43 optlc_net_107:42 9.239131e-05 +42 optlc_net_107:43 optlc_net_107:41 0.0003035715 +43 optlc_net_107:44 optlc_net_107:43 0.0045 +44 optlc_net_107:41 optlc_net_107:40 0.01243973 +45 optlc_net_107:41 optlc_net_107:39 0.008174107 +46 optlc_net_107:47 optlc_net_107:46 0.0003035715 +47 optlc_net_107:30 optlc_net_107:29 0.0004107143 + +*END + +*D_NET mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0] 0.004012276 //LENGTH 33.735 LUMPCC 0.0006554791 DR + +*CONN +*I mux_top_track_10\/mux_l2_in_0_:X O *L 0 *C 66.065 39.780 +*I mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 85.305 53.205 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 85.305 53.168 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 85.305 52.700 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 69.045 52.700 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 69.000 52.655 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 69.000 39.825 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 68.955 39.780 +*N mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 66.103 39.780 + +*CAP +0 mux_top_track_10\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.514429e-05 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0008191995 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0007840553 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006702096 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006702096 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001879894 +8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001879894 +9 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_0_sram[2]:7 0.0001632557 +10 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_0_sram[2]:6 0.0001632557 +11 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 8.713629e-05 +12 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 8.713629e-05 +13 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 7.039219e-05 +14 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 6.955372e-06 +15 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 6.955372e-06 +16 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 7.039219e-05 + +*RES +0 mux_top_track_10\/mux_l2_in_0_:X mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_10\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.01451786 +3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.01145536 +6 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.002546875 +7 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_10/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004174107 + +*END + +*D_NET mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001361941 //LENGTH 10.615 LUMPCC 0.0001708571 DR + +*CONN +*I mux_top_track_28\/mux_l1_in_0_:X O *L 0 *C 37.085 94.180 +*I mux_top_track_28\/mux_l2_in_0_:A1 I *L 0.00198 *C 44.720 96.220 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 44.720 96.220 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 44.620 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 41.905 95.880 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 41.860 95.835 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 41.860 94.225 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 41.815 94.180 +*N mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 37.123 94.180 + +*CAP +0 mux_top_track_28\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_28\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.422557e-05 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001927751 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001659933 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001005333 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001005333 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002875115 +8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002875115 +9 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_8_sram[1]:4 1.050837e-05 +10 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_8_sram[1]:6 7.492017e-05 +11 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_8_sram[1]:7 1.050837e-05 +12 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_8_sram[1]:5 7.492017e-05 + +*RES +0 mux_top_track_28\/mux_l1_in_0_:X mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.004189732 +2 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0014375 +4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002424107 +5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_28\/mux_l2_in_0_:A1 0.152 +7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007782821 //LENGTH 5.690 LUMPCC 0.0001317768 DR + +*CONN +*I mux_left_track_11\/mux_l1_in_0_:X O *L 0 *C 36.055 66.640 +*I mux_left_track_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.405 69.020 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.390 69.020 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.062 69.020 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 34.040 68.975 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 34.040 66.685 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 34.085 66.640 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 36.017 66.640 + +*CAP +0 mux_left_track_11\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_11\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.975616e-05 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.975616e-05 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001508066 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001508066 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001116899 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001116899 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[17]:5 3.090119e-06 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[17]:2 6.279829e-05 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[17]:4 3.090119e-06 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[17]:3 6.279829e-05 + +*RES +0 mux_left_track_11\/mux_l1_in_0_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_11\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001779891 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725446 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001188487 //LENGTH 9.625 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_0_:X O *L 0 *C 6.155 27.880 +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.735 22.960 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 9.735 22.960 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 9.660 23.800 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 6.025 23.800 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 5.980 23.845 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 5.980 27.835 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 5.980 27.880 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 6.155 27.880 + +*CAP +0 mux_left_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.174205e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002939329 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002408978 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002288315 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002288315 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.909774e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.315321e-05 + +*RES +0 mux_left_track_17\/mux_l2_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003245536 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0035625 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.51087e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0007500001 + +*END + +*D_NET mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005129027 //LENGTH 36.065 LUMPCC 0.002163753 DR + +*CONN +*I mux_left_track_23\/mux_l2_in_0_:X O *L 0 *C 35.595 31.280 +*I mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.310 31.410 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 5.310 31.410 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 5.520 31.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 5.520 31.325 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 5.520 33.275 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 5.565 33.320 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 12.375 33.320 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 12.420 33.275 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 12.420 31.338 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 12.428 31.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 34.492 31.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 34.500 31.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 34.545 31.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 35.558 31.280 + +*CAP +0 mux_left_track_23\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.298239e-05 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.573969e-05 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001185053 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001185053 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004136985 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004136985 +8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001507787 +9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001507787 +10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0006457335 +11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0006457335 +12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:12 3.57503e-05 +13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:13 8.068473e-05 +14 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:14 8.068473e-05 +15 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chany_top_in[4]:16 0.0003586626 +16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_top_in[4]:15 0.0003586626 +17 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 prog_clk[0]:291 0.000163893 +18 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:418 1.302199e-07 +19 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:420 2.870468e-07 +20 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 prog_clk[0]:292 0.000163893 +21 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:420 1.425043e-05 +22 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:421 2.076419e-05 +23 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:419 1.302199e-07 +24 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:424 2.870468e-07 +25 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:419 1.425043e-05 +26 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:422 2.076419e-05 +27 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 prog_clk[0]:414 1.512033e-08 +28 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 prog_clk[0]:415 1.512033e-08 +29 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[8]:15 0.0002076916 +30 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[8]:16 0.0002076916 +31 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[8]:16 9.750054e-06 +32 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[8]:17 9.750054e-06 +33 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[16]:7 0.0001324961 +34 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[16] 0.0001324961 +35 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 ropt_net_115:9 0.0001486686 +36 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 ropt_net_115:8 0.0001486686 +37 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 ropt_net_115:5 1.362736e-05 +38 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 ropt_net_115:2 1.16401e-05 +39 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_115:3 1.16401e-05 +40 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_115:4 1.362736e-05 + +*RES +0 mux_left_track_23\/mux_l2_in_0_:X mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.152 +1 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0009040179 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0045 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.00345685 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001729911 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006080357 +8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741071 +11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.065218e-05 +12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_23\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET chany_top_in[11] 0.01640006 //LENGTH 122.000 LUMPCC 0.005618297 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 75.900 102.070 +*I mux_left_track_19\/mux_l1_in_0_:A1 I *L 0.00198 *C 21.160 36.380 +*N chany_top_in[11]:2 *C 21.160 36.380 +*N chany_top_in[11]:3 *C 21.160 36.425 +*N chany_top_in[11]:4 *C 21.160 38.023 +*N chany_top_in[11]:5 *C 21.168 38.080 +*N chany_top_in[11]:6 *C 46.900 38.080 +*N chany_top_in[11]:7 *C 46.920 38.087 +*N chany_top_in[11]:8 *C 46.920 83.633 +*N chany_top_in[11]:9 *C 46.940 83.640 +*N chany_top_in[11]:10 *C 75.892 83.640 +*N chany_top_in[11]:11 *C 75.900 83.698 + +*CAP +0 chany_top_in[11] 0.001059225 +1 mux_left_track_19\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[11]:2 3.474798e-05 +3 chany_top_in[11]:3 0.00011258 +4 chany_top_in[11]:4 0.00011258 +5 chany_top_in[11]:5 0.0007290347 +6 chany_top_in[11]:6 0.0007290347 +7 chany_top_in[11]:7 0.001896546 +8 chany_top_in[11]:8 0.001896546 +9 chany_top_in[11]:9 0.001575621 +10 chany_top_in[11]:10 0.001575621 +11 chany_top_in[11]:11 0.001059225 +12 chany_top_in[11]:7 chany_top_in[15]:9 0.000295827 +13 chany_top_in[11]:8 chany_top_in[15]:10 0.000295827 +14 chany_top_in[11]:9 top_left_grid_pin_36_[0]:17 0.0004937629 +15 chany_top_in[11]:10 top_left_grid_pin_36_[0]:16 0.0004937629 +16 chany_top_in[11]:5 chanx_left_in[12] 0.0005696454 +17 chany_top_in[11]:6 chanx_left_in[12]:10 0.0005696454 +18 chany_top_in[11]:7 chanx_left_in[12]:9 0.0005993988 +19 chany_top_in[11]:8 chanx_left_in[12]:8 0.0005993988 +20 chany_top_in[11]:5 chanx_left_in[15]:8 0.0005661033 +21 chany_top_in[11]:6 chanx_left_in[15]:7 0.0005661033 +22 chany_top_in[11]:9 mux_tree_tapbuf_size2_6_sram[0]:7 0.0002236825 +23 chany_top_in[11]:10 mux_tree_tapbuf_size2_6_sram[0]:12 0.0002236825 +24 chany_top_in[11] mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.072834e-05 +25 chany_top_in[11]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.072834e-05 + +*RES +0 chany_top_in[11] chany_top_in[11]:11 0.01640402 +1 chany_top_in[11]:2 mux_left_track_19\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[11]:3 chany_top_in[11]:2 0.0045 +3 chany_top_in[11]:4 chany_top_in[11]:3 0.001426339 +4 chany_top_in[11]:5 chany_top_in[11]:4 0.00341 +5 chany_top_in[11]:6 chany_top_in[11]:5 0.004031425 +6 chany_top_in[11]:7 chany_top_in[11]:6 0.00341 +7 chany_top_in[11]:9 chany_top_in[11]:8 0.00341 +8 chany_top_in[11]:8 chany_top_in[11]:7 0.007135383 +9 chany_top_in[11]:11 chany_top_in[11]:10 0.00341 +10 chany_top_in[11]:10 chany_top_in[11]:9 0.004535892 + +*END + +*D_NET top_left_grid_pin_37_[0] 0.01086222 //LENGTH 87.975 LUMPCC 0.001638243 DR + +*CONN +*P top_left_grid_pin_37_[0] I *L 0.29796 *C 31.740 102.070 +*I mux_top_track_30\/mux_l1_in_0_:A1 I *L 0.00198 *C 38.280 83.300 +*I mux_top_track_14\/mux_l1_in_0_:A1 I *L 0.00198 *C 42.880 52.700 +*I mux_top_track_6\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.375 53.720 +*I mux_top_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 52.615 60.520 +*N top_left_grid_pin_37_[0]:5 *C 52.578 60.520 +*N top_left_grid_pin_37_[0]:6 *C 48.805 60.520 +*N top_left_grid_pin_37_[0]:7 *C 48.760 60.520 +*N top_left_grid_pin_37_[0]:8 *C 48.753 60.520 +*N top_left_grid_pin_37_[0]:9 *C 55.338 53.720 +*N top_left_grid_pin_37_[0]:10 *C 43.285 53.720 +*N top_left_grid_pin_37_[0]:11 *C 43.240 53.720 +*N top_left_grid_pin_37_[0]:12 *C 42.843 52.700 +*N top_left_grid_pin_37_[0]:13 *C 42.365 52.700 +*N top_left_grid_pin_37_[0]:14 *C 42.320 52.745 +*N top_left_grid_pin_37_[0]:15 *C 42.320 53.720 +*N top_left_grid_pin_37_[0]:16 *C 42.320 60.463 +*N top_left_grid_pin_37_[0]:17 *C 42.320 60.520 +*N top_left_grid_pin_37_[0]:18 *C 38.648 60.520 +*N top_left_grid_pin_37_[0]:19 *C 38.640 60.578 +*N top_left_grid_pin_37_[0]:20 *C 38.640 83.255 +*N top_left_grid_pin_37_[0]:21 *C 38.617 83.300 +*N top_left_grid_pin_37_[0]:22 *C 38.295 83.300 +*N top_left_grid_pin_37_[0]:23 *C 38.180 83.640 +*N top_left_grid_pin_37_[0]:24 *C 31.325 83.640 +*N top_left_grid_pin_37_[0]:25 *C 31.280 83.685 +*N top_left_grid_pin_37_[0]:26 *C 31.280 100.640 +*N top_left_grid_pin_37_[0]:27 *C 31.740 100.640 + +*CAP +0 top_left_grid_pin_37_[0] 0.0001022762 +1 mux_top_track_30\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_14\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_6\/mux_l1_in_0_:A0 1e-06 +4 mux_top_track_2\/mux_l1_in_0_:A0 1e-06 +5 top_left_grid_pin_37_[0]:5 0.0002574921 +6 top_left_grid_pin_37_[0]:6 0.0002574921 +7 top_left_grid_pin_37_[0]:7 3.504966e-05 +8 top_left_grid_pin_37_[0]:8 0.0003953769 +9 top_left_grid_pin_37_[0]:9 0.0007820002 +10 top_left_grid_pin_37_[0]:10 0.0007820002 +11 top_left_grid_pin_37_[0]:11 8.794054e-05 +12 top_left_grid_pin_37_[0]:12 6.511073e-05 +13 top_left_grid_pin_37_[0]:13 6.511073e-05 +14 top_left_grid_pin_37_[0]:14 5.68955e-05 +15 top_left_grid_pin_37_[0]:15 0.0004609999 +16 top_left_grid_pin_37_[0]:16 0.0003476065 +17 top_left_grid_pin_37_[0]:17 0.0005607737 +18 top_left_grid_pin_37_[0]:18 0.0001653967 +19 top_left_grid_pin_37_[0]:19 0.001043666 +20 top_left_grid_pin_37_[0]:20 0.001043666 +21 top_left_grid_pin_37_[0]:21 4.892446e-05 +22 top_left_grid_pin_37_[0]:22 7.633997e-05 +23 top_left_grid_pin_37_[0]:23 0.0005094385 +24 top_left_grid_pin_37_[0]:24 0.000482023 +25 top_left_grid_pin_37_[0]:25 0.000717723 +26 top_left_grid_pin_37_[0]:26 0.0007460632 +27 top_left_grid_pin_37_[0]:27 0.0001306163 +28 top_left_grid_pin_37_[0]:25 prog_clk[0]:250 3.707761e-05 +29 top_left_grid_pin_37_[0]:25 prog_clk[0]:253 7.730934e-05 +30 top_left_grid_pin_37_[0]:25 prog_clk[0]:256 9.808777e-05 +31 top_left_grid_pin_37_[0]:25 prog_clk[0]:465 5.741628e-05 +32 top_left_grid_pin_37_[0]:16 prog_clk[0]:234 7.921062e-07 +33 top_left_grid_pin_37_[0]:20 prog_clk[0]:243 2.362653e-05 +34 top_left_grid_pin_37_[0]:20 prog_clk[0]:244 4.135927e-06 +35 top_left_grid_pin_37_[0]:20 prog_clk[0]:247 4.576842e-05 +36 top_left_grid_pin_37_[0]:20 prog_clk[0]:386 2.631222e-06 +37 top_left_grid_pin_37_[0]:19 prog_clk[0]:238 4.135927e-06 +38 top_left_grid_pin_37_[0]:19 prog_clk[0]:242 2.362653e-05 +39 top_left_grid_pin_37_[0]:19 prog_clk[0]:244 4.576842e-05 +40 top_left_grid_pin_37_[0]:19 prog_clk[0]:387 2.631222e-06 +41 top_left_grid_pin_37_[0]:26 prog_clk[0]:253 3.707761e-05 +42 top_left_grid_pin_37_[0]:26 prog_clk[0]:256 7.730934e-05 +43 top_left_grid_pin_37_[0]:26 prog_clk[0]:257 9.808777e-05 +44 top_left_grid_pin_37_[0]:26 prog_clk[0]:466 5.741628e-05 +45 top_left_grid_pin_37_[0]:15 prog_clk[0]:231 7.921062e-07 +46 top_left_grid_pin_37_[0]:8 mux_tree_tapbuf_size2_14_sram[0]:11 3.750863e-05 +47 top_left_grid_pin_37_[0]:16 mux_tree_tapbuf_size2_14_sram[0]:12 1.88726e-05 +48 top_left_grid_pin_37_[0]:17 mux_tree_tapbuf_size2_14_sram[0]:10 3.750863e-05 +49 top_left_grid_pin_37_[0]:17 mux_tree_tapbuf_size2_14_sram[0]:11 5.456847e-05 +50 top_left_grid_pin_37_[0]:14 mux_tree_tapbuf_size2_14_sram[0]:13 4.487721e-06 +51 top_left_grid_pin_37_[0]:20 mux_tree_tapbuf_size2_14_sram[0]:5 2.196589e-05 +52 top_left_grid_pin_37_[0]:20 mux_tree_tapbuf_size2_14_sram[0]:8 8.620691e-05 +53 top_left_grid_pin_37_[0]:19 mux_tree_tapbuf_size2_14_sram[0]:9 8.620691e-05 +54 top_left_grid_pin_37_[0]:19 mux_tree_tapbuf_size2_14_sram[0]:8 2.196589e-05 +55 top_left_grid_pin_37_[0]:18 mux_tree_tapbuf_size2_14_sram[0]:10 5.456847e-05 +56 top_left_grid_pin_37_[0]:15 mux_tree_tapbuf_size2_14_sram[0]:12 4.487721e-06 +57 top_left_grid_pin_37_[0]:15 mux_tree_tapbuf_size2_14_sram[0]:13 1.88726e-05 +58 top_left_grid_pin_37_[0]:8 mux_tree_tapbuf_size2_21_sram[1]:11 4.61141e-05 +59 top_left_grid_pin_37_[0]:17 mux_tree_tapbuf_size2_21_sram[1]:10 4.61141e-05 +60 top_left_grid_pin_37_[0]:17 mux_tree_tapbuf_size2_21_sram[1]:11 7.689283e-05 +61 top_left_grid_pin_37_[0]:20 mux_tree_tapbuf_size2_21_sram[1]:8 4.587831e-06 +62 top_left_grid_pin_37_[0]:19 mux_tree_tapbuf_size2_21_sram[1]:9 4.587831e-06 +63 top_left_grid_pin_37_[0]:18 mux_tree_tapbuf_size2_21_sram[1]:10 7.689283e-05 +64 top_left_grid_pin_37_[0]:9 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001210715 +65 top_left_grid_pin_37_[0]:10 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001210715 + +*RES +0 top_left_grid_pin_37_[0] top_left_grid_pin_37_[0]:27 0.001276786 +1 top_left_grid_pin_37_[0]:7 top_left_grid_pin_37_[0]:6 0.0045 +2 top_left_grid_pin_37_[0]:8 top_left_grid_pin_37_[0]:7 0.00341 +3 top_left_grid_pin_37_[0]:6 top_left_grid_pin_37_[0]:5 0.003368304 +4 top_left_grid_pin_37_[0]:5 mux_top_track_2\/mux_l1_in_0_:A0 0.152 +5 top_left_grid_pin_37_[0]:24 top_left_grid_pin_37_[0]:23 0.006120536 +6 top_left_grid_pin_37_[0]:25 top_left_grid_pin_37_[0]:24 0.0045 +7 top_left_grid_pin_37_[0]:16 top_left_grid_pin_37_[0]:15 0.00602009 +8 top_left_grid_pin_37_[0]:17 top_left_grid_pin_37_[0]:16 0.00341 +9 top_left_grid_pin_37_[0]:17 top_left_grid_pin_37_[0]:8 0.001007758 +10 top_left_grid_pin_37_[0]:22 mux_top_track_30\/mux_l1_in_0_:A1 0.152 +11 top_left_grid_pin_37_[0]:22 top_left_grid_pin_37_[0]:21 0.0001752718 +12 top_left_grid_pin_37_[0]:13 top_left_grid_pin_37_[0]:12 0.0004263393 +13 top_left_grid_pin_37_[0]:14 top_left_grid_pin_37_[0]:13 0.0045 +14 top_left_grid_pin_37_[0]:12 mux_top_track_14\/mux_l1_in_0_:A1 0.152 +15 top_left_grid_pin_37_[0]:9 mux_top_track_6\/mux_l1_in_0_:A0 0.152 +16 top_left_grid_pin_37_[0]:10 top_left_grid_pin_37_[0]:9 0.01076116 +17 top_left_grid_pin_37_[0]:11 top_left_grid_pin_37_[0]:10 0.0045 +18 top_left_grid_pin_37_[0]:21 top_left_grid_pin_37_[0]:20 0.0045 +19 top_left_grid_pin_37_[0]:20 top_left_grid_pin_37_[0]:19 0.02024777 +20 top_left_grid_pin_37_[0]:19 top_left_grid_pin_37_[0]:18 0.00341 +21 top_left_grid_pin_37_[0]:18 top_left_grid_pin_37_[0]:17 0.0005753583 +22 top_left_grid_pin_37_[0]:23 top_left_grid_pin_37_[0]:22 0.0003035715 +23 top_left_grid_pin_37_[0]:26 top_left_grid_pin_37_[0]:25 0.01513839 +24 top_left_grid_pin_37_[0]:27 top_left_grid_pin_37_[0]:26 0.0004107143 +25 top_left_grid_pin_37_[0]:15 top_left_grid_pin_37_[0]:14 0.0008705358 +26 top_left_grid_pin_37_[0]:15 top_left_grid_pin_37_[0]:11 0.0008214285 + +*END + +*D_NET top_right_grid_pin_1_[0] 0.0107929 //LENGTH 92.830 LUMPCC 0.000774233 DR + +*CONN +*P top_right_grid_pin_1_[0] I *L 0.29796 *C 110.860 102.070 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 80.790 91.460 +*I mux_top_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 79.580 69.020 +*I mux_top_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 82.340 47.260 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 81.135 44.540 +*N top_right_grid_pin_1_[0]:5 *C 81.135 44.540 +*N top_right_grid_pin_1_[0]:6 *C 80.960 44.540 +*N top_right_grid_pin_1_[0]:7 *C 80.960 44.585 +*N top_right_grid_pin_1_[0]:8 *C 82.340 47.260 +*N top_right_grid_pin_1_[0]:9 *C 82.340 47.600 +*N top_right_grid_pin_1_[0]:10 *C 81.005 47.600 +*N top_right_grid_pin_1_[0]:11 *C 80.960 47.600 +*N top_right_grid_pin_1_[0]:12 *C 79.618 69.020 +*N top_right_grid_pin_1_[0]:13 *C 79.995 69.020 +*N top_right_grid_pin_1_[0]:14 *C 80.040 69.020 +*N top_right_grid_pin_1_[0]:15 *C 80.960 69.020 +*N top_right_grid_pin_1_[0]:16 *C 80.790 91.460 +*N top_right_grid_pin_1_[0]:17 *C 80.960 91.460 +*N top_right_grid_pin_1_[0]:18 *C 80.960 91.460 +*N top_right_grid_pin_1_[0]:19 *C 80.960 95.835 +*N top_right_grid_pin_1_[0]:20 *C 81.005 95.880 +*N top_right_grid_pin_1_[0]:21 *C 110.815 95.880 +*N top_right_grid_pin_1_[0]:22 *C 110.860 95.925 + +*CAP +0 top_right_grid_pin_1_[0] 0.0002833109 +1 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_0\/mux_l1_in_2_:A1 1e-06 +3 mux_top_track_4\/mux_l1_in_2_:A1 1e-06 +4 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +5 top_right_grid_pin_1_[0]:5 5.14498e-05 +6 top_right_grid_pin_1_[0]:6 5.553933e-05 +7 top_right_grid_pin_1_[0]:7 0.0001689206 +8 top_right_grid_pin_1_[0]:8 5.453578e-05 +9 top_right_grid_pin_1_[0]:9 0.0001373756 +10 top_right_grid_pin_1_[0]:10 0.000110472 +11 top_right_grid_pin_1_[0]:11 0.001109784 +12 top_right_grid_pin_1_[0]:12 4.323322e-05 +13 top_right_grid_pin_1_[0]:13 4.323322e-05 +14 top_right_grid_pin_1_[0]:14 8.071248e-05 +15 top_right_grid_pin_1_[0]:15 0.002110717 +16 top_right_grid_pin_1_[0]:16 5.715787e-05 +17 top_right_grid_pin_1_[0]:17 6.194003e-05 +18 top_right_grid_pin_1_[0]:18 0.001458437 +19 top_right_grid_pin_1_[0]:19 0.0002750921 +20 top_right_grid_pin_1_[0]:20 0.001814721 +21 top_right_grid_pin_1_[0]:21 0.001814721 +22 top_right_grid_pin_1_[0]:22 0.0002833109 +23 top_right_grid_pin_1_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001454107 +24 top_right_grid_pin_1_[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.369508e-06 +25 top_right_grid_pin_1_[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001454107 +26 top_right_grid_pin_1_[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.369508e-06 +27 top_right_grid_pin_1_[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.977472e-07 +28 top_right_grid_pin_1_[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001072903 +29 top_right_grid_pin_1_[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.977472e-07 +30 top_right_grid_pin_1_[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001072903 +31 top_right_grid_pin_1_[0]:18 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001277483 +32 top_right_grid_pin_1_[0]:15 mux_top_track_20/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001277483 + +*RES +0 top_right_grid_pin_1_[0] top_right_grid_pin_1_[0]:22 0.005486608 +1 top_right_grid_pin_1_[0]:8 mux_top_track_4\/mux_l1_in_2_:A1 0.152 +2 top_right_grid_pin_1_[0]:10 top_right_grid_pin_1_[0]:9 0.001191964 +3 top_right_grid_pin_1_[0]:11 top_right_grid_pin_1_[0]:10 0.0045 +4 top_right_grid_pin_1_[0]:11 top_right_grid_pin_1_[0]:7 0.002691964 +5 top_right_grid_pin_1_[0]:12 mux_top_track_0\/mux_l1_in_2_:A1 0.152 +6 top_right_grid_pin_1_[0]:13 top_right_grid_pin_1_[0]:12 0.0003370536 +7 top_right_grid_pin_1_[0]:14 top_right_grid_pin_1_[0]:13 0.0045 +8 top_right_grid_pin_1_[0]:6 top_right_grid_pin_1_[0]:5 9.51087e-05 +9 top_right_grid_pin_1_[0]:7 top_right_grid_pin_1_[0]:6 0.0045 +10 top_right_grid_pin_1_[0]:5 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +11 top_right_grid_pin_1_[0]:17 top_right_grid_pin_1_[0]:16 9.239131e-05 +12 top_right_grid_pin_1_[0]:18 top_right_grid_pin_1_[0]:17 0.0045 +13 top_right_grid_pin_1_[0]:18 top_right_grid_pin_1_[0]:15 0.02003572 +14 top_right_grid_pin_1_[0]:16 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +15 top_right_grid_pin_1_[0]:20 top_right_grid_pin_1_[0]:19 0.0045 +16 top_right_grid_pin_1_[0]:19 top_right_grid_pin_1_[0]:18 0.00390625 +17 top_right_grid_pin_1_[0]:21 top_right_grid_pin_1_[0]:20 0.02661607 +18 top_right_grid_pin_1_[0]:22 top_right_grid_pin_1_[0]:21 0.0045 +19 top_right_grid_pin_1_[0]:9 top_right_grid_pin_1_[0]:8 0.0003035715 +20 top_right_grid_pin_1_[0]:15 top_right_grid_pin_1_[0]:14 0.0008214285 +21 top_right_grid_pin_1_[0]:15 top_right_grid_pin_1_[0]:11 0.019125 + +*END + +*D_NET chanx_left_in[5] 0.009955426 //LENGTH 70.890 LUMPCC 0.002478177 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 50.320 +*I mux_top_track_30\/mux_l1_in_0_:A0 I *L 0.001631 *C 37.895 82.280 +*N chanx_left_in[5]:2 *C 29.960 82.280 +*N chanx_left_in[5]:3 *C 37.858 82.280 +*N chanx_left_in[5]:4 *C 30.405 82.280 +*N chanx_left_in[5]:5 *C 30.360 82.280 +*N chanx_left_in[5]:6 *C 30.360 82.280 +*N chanx_left_in[5]:7 *C 30.360 82.273 +*N chanx_left_in[5]:8 *C 30.360 61.888 +*N chanx_left_in[5]:9 *C 30.340 61.880 +*N chanx_left_in[5]:10 *C 16.580 61.880 +*N chanx_left_in[5]:11 *C 16.560 61.873 +*N chanx_left_in[5]:12 *C 16.560 50.328 +*N chanx_left_in[5]:13 *C 16.540 50.320 + +*CAP +0 chanx_left_in[5] 0.0007587576 +1 mux_top_track_30\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[5]:2 5.170309e-05 +3 chanx_left_in[5]:3 0.0004921847 +4 chanx_left_in[5]:4 0.0004921847 +5 chanx_left_in[5]:5 3.015483e-05 +6 chanx_left_in[5]:6 5.170309e-05 +7 chanx_left_in[5]:7 0.0007841781 +8 chanx_left_in[5]:8 0.0007841781 +9 chanx_left_in[5]:9 0.0009130863 +10 chanx_left_in[5]:10 0.0009130863 +11 chanx_left_in[5]:11 0.0007231377 +12 chanx_left_in[5]:12 0.0007231377 +13 chanx_left_in[5]:13 0.0007587576 +14 chanx_left_in[5]:7 chany_top_in[4]:18 0.0007671652 +15 chanx_left_in[5]:8 chany_top_in[4]:17 0.0007671652 +16 chanx_left_in[5] chanx_left_in[0] 0.0003524525 +17 chanx_left_in[5]:13 chanx_left_in[0]:12 0.0003524525 +18 chanx_left_in[5]:9 mux_tree_tapbuf_size5_2_sram[2]:10 0.0001194707 +19 chanx_left_in[5]:10 mux_tree_tapbuf_size5_2_sram[2]:9 0.0001194707 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:13 0.002398567 +1 chanx_left_in[5]:3 mux_top_track_30\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[5]:4 chanx_left_in[5]:3 0.006654018 +3 chanx_left_in[5]:5 chanx_left_in[5]:4 0.0045 +4 chanx_left_in[5]:6 chanx_left_in[5]:5 0.00341 +5 chanx_left_in[5]:6 chanx_left_in[5]:2 5.69697e-05 +6 chanx_left_in[5]:7 chanx_left_in[5]:6 0.00341 +7 chanx_left_in[5]:9 chanx_left_in[5]:8 0.00341 +8 chanx_left_in[5]:8 chanx_left_in[5]:7 0.00319365 +9 chanx_left_in[5]:10 chanx_left_in[5]:9 0.002155733 +10 chanx_left_in[5]:11 chanx_left_in[5]:10 0.00341 +11 chanx_left_in[5]:13 chanx_left_in[5]:12 0.00341 +12 chanx_left_in[5]:12 chanx_left_in[5]:11 0.001808717 + +*END + +*D_NET chanx_left_in[8] 0.019174 //LENGTH 136.215 LUMPCC 0.004943512 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 32.640 +*I mux_top_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 76.360 90.780 +*N chanx_left_in[8]:2 *C 76.360 90.780 +*N chanx_left_in[8]:3 *C 76.360 90.440 +*N chanx_left_in[8]:4 *C 62.605 90.440 +*N chanx_left_in[8]:5 *C 62.560 90.395 +*N chanx_left_in[8]:6 *C 62.560 86.418 +*N chanx_left_in[8]:7 *C 62.553 86.360 +*N chanx_left_in[8]:8 *C 43.260 86.360 +*N chanx_left_in[8]:9 *C 43.240 86.353 +*N chanx_left_in[8]:10 *C 43.240 41.488 +*N chanx_left_in[8]:11 *C 43.220 41.480 +*N chanx_left_in[8]:12 *C 24.860 41.480 +*N chanx_left_in[8]:13 *C 24.840 41.473 +*N chanx_left_in[8]:14 *C 24.840 33.328 +*N chanx_left_in[8]:15 *C 24.820 33.320 +*N chanx_left_in[8]:16 *C 5.520 33.320 +*N chanx_left_in[8]:17 *C 5.520 32.640 + +*CAP +0 chanx_left_in[8] 0.0003187725 +1 mux_top_track_24\/mux_l1_in_1_:A1 1e-06 +2 chanx_left_in[8]:2 5.578184e-05 +3 chanx_left_in[8]:3 0.0008990238 +4 chanx_left_in[8]:4 0.0008715386 +5 chanx_left_in[8]:5 0.0002025645 +6 chanx_left_in[8]:6 0.0002025645 +7 chanx_left_in[8]:7 0.001176767 +8 chanx_left_in[8]:8 0.001176767 +9 chanx_left_in[8]:9 0.002536457 +10 chanx_left_in[8]:10 0.002536457 +11 chanx_left_in[8]:11 0.0007339123 +12 chanx_left_in[8]:12 0.0007339123 +13 chanx_left_in[8]:13 0.0004994342 +14 chanx_left_in[8]:14 0.0004994342 +15 chanx_left_in[8]:15 0.0006828225 +16 chanx_left_in[8]:16 0.0007336633 +17 chanx_left_in[8]:17 0.0003696133 +18 chanx_left_in[8]:4 prog_clk[0]:144 2.213431e-05 +19 chanx_left_in[8]:5 prog_clk[0]:143 2.885163e-05 +20 chanx_left_in[8]:6 prog_clk[0]:83 2.885163e-05 +21 chanx_left_in[8]:11 prog_clk[0]:297 0.0003425555 +22 chanx_left_in[8]:11 prog_clk[0]:307 0.0001631309 +23 chanx_left_in[8]:12 prog_clk[0]:306 0.0001631309 +24 chanx_left_in[8]:12 prog_clk[0]:307 0.0003425555 +25 chanx_left_in[8]:15 prog_clk[0]:420 7.97508e-06 +26 chanx_left_in[8]:3 prog_clk[0]:143 2.213431e-05 +27 chanx_left_in[8]:16 prog_clk[0]:419 7.97508e-06 +28 chanx_left_in[8]:7 top_left_grid_pin_39_[0]:17 0.0005663444 +29 chanx_left_in[8]:8 top_left_grid_pin_39_[0]:18 0.0005663444 +30 chanx_left_in[8] chanx_left_in[12] 5.246031e-06 +31 chanx_left_in[8]:9 chanx_left_in[12]:8 0.0005005286 +32 chanx_left_in[8]:10 chanx_left_in[12]:9 0.0005005286 +33 chanx_left_in[8]:17 chanx_left_in[12]:10 5.246031e-06 +34 chanx_left_in[8]:11 chanx_left_in[15]:7 0.0002695872 +35 chanx_left_in[8]:12 chanx_left_in[15]:8 0.0002695872 +36 chanx_left_in[8] left_top_grid_pin_48_[0]:15 2.26314e-06 +37 chanx_left_in[8]:15 left_top_grid_pin_48_[0]:11 0.0002543773 +38 chanx_left_in[8]:15 left_top_grid_pin_48_[0]:16 5.081065e-05 +39 chanx_left_in[8]:17 left_top_grid_pin_48_[0]:16 2.26314e-06 +40 chanx_left_in[8]:16 left_top_grid_pin_48_[0]:15 5.081065e-05 +41 chanx_left_in[8]:16 left_top_grid_pin_48_[0]:16 0.0002543773 +42 chanx_left_in[8]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 3.654968e-05 +43 chanx_left_in[8]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 3.960643e-06 +44 chanx_left_in[8]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 3.960643e-06 +45 chanx_left_in[8]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 3.654968e-05 +46 chanx_left_in[8]:15 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002076916 +47 chanx_left_in[8]:17 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.750054e-06 +48 chanx_left_in[8]:16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002076916 +49 chanx_left_in[8]:16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.750054e-06 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:17 0.0006721 +1 chanx_left_in[8]:2 mux_top_track_24\/mux_l1_in_1_:A1 0.152 +2 chanx_left_in[8]:4 chanx_left_in[8]:3 0.01228125 +3 chanx_left_in[8]:5 chanx_left_in[8]:4 0.0045 +4 chanx_left_in[8]:6 chanx_left_in[8]:5 0.00355134 +5 chanx_left_in[8]:7 chanx_left_in[8]:6 0.00341 +6 chanx_left_in[8]:8 chanx_left_in[8]:7 0.003022492 +7 chanx_left_in[8]:9 chanx_left_in[8]:8 0.00341 +8 chanx_left_in[8]:11 chanx_left_in[8]:10 0.00341 +9 chanx_left_in[8]:10 chanx_left_in[8]:9 0.007028849 +10 chanx_left_in[8]:12 chanx_left_in[8]:11 0.0028764 +11 chanx_left_in[8]:13 chanx_left_in[8]:12 0.00341 +12 chanx_left_in[8]:15 chanx_left_in[8]:14 0.00341 +13 chanx_left_in[8]:14 chanx_left_in[8]:13 0.00127605 +14 chanx_left_in[8]:3 chanx_left_in[8]:2 0.0003035715 +15 chanx_left_in[8]:17 chanx_left_in[8]:16 0.0001065333 +16 chanx_left_in[8]:16 chanx_left_in[8]:15 0.003023666 + +*END + +*D_NET chanx_left_in[15] 0.008406069 //LENGTH 61.470 LUMPCC 0.001826241 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 42.160 +*I mux_top_track_10\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.835 39.100 +*N chanx_left_in[15]:2 *C 4.200 38.760 +*N chanx_left_in[15]:3 *C 55.797 39.100 +*N chanx_left_in[15]:4 *C 51.565 39.100 +*N chanx_left_in[15]:5 *C 51.520 39.100 +*N chanx_left_in[15]:6 *C 51.520 39.440 +*N chanx_left_in[15]:7 *C 51.513 39.440 +*N chanx_left_in[15]:8 *C 23.008 39.440 +*N chanx_left_in[15]:9 *C 23.000 39.440 +*N chanx_left_in[15]:10 *C 23.000 39.100 +*N chanx_left_in[15]:11 *C 22.955 39.100 +*N chanx_left_in[15]:12 *C 21.160 39.100 +*N chanx_left_in[15]:13 *C 21.160 38.760 +*N chanx_left_in[15]:14 *C 4.645 38.760 +*N chanx_left_in[15]:15 *C 4.600 38.760 +*N chanx_left_in[15]:16 *C 4.600 38.760 +*N chanx_left_in[15]:17 *C 4.600 38.768 +*N chanx_left_in[15]:18 *C 4.600 42.153 +*N chanx_left_in[15]:19 *C 4.580 42.160 + +*CAP +0 chanx_left_in[15] 0.0002284911 +1 mux_top_track_10\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[15]:2 0.0001025887 +3 chanx_left_in[15]:3 0.0002518308 +4 chanx_left_in[15]:4 0.0002518308 +5 chanx_left_in[15]:5 4.421181e-05 +6 chanx_left_in[15]:6 4.745898e-05 +7 chanx_left_in[15]:7 0.00103712 +8 chanx_left_in[15]:8 0.00103712 +9 chanx_left_in[15]:9 5.993744e-05 +10 chanx_left_in[15]:10 5.589123e-05 +11 chanx_left_in[15]:11 0.0001456269 +12 chanx_left_in[15]:12 0.0001720214 +13 chanx_left_in[15]:13 0.00116125 +14 chanx_left_in[15]:14 0.001134855 +15 chanx_left_in[15]:15 3.600504e-05 +16 chanx_left_in[15]:16 0.0001025887 +17 chanx_left_in[15]:17 0.0002407547 +18 chanx_left_in[15]:18 0.0002407547 +19 chanx_left_in[15]:19 0.0002284911 +20 chanx_left_in[15]:7 chany_top_in[11]:6 0.0005661033 +21 chanx_left_in[15]:8 chany_top_in[11]:5 0.0005661033 +22 chanx_left_in[15]:7 chanx_left_in[8]:11 0.0002695872 +23 chanx_left_in[15]:8 chanx_left_in[8]:12 0.0002695872 +24 chanx_left_in[15]:14 ropt_net_134:3 7.743017e-05 +25 chanx_left_in[15]:13 ropt_net_134:4 7.743017e-05 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:19 0.0005248332 +1 chanx_left_in[15]:3 mux_top_track_10\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[15]:4 chanx_left_in[15]:3 0.003779018 +3 chanx_left_in[15]:5 chanx_left_in[15]:4 0.0045 +4 chanx_left_in[15]:6 chanx_left_in[15]:5 0.0001634615 +5 chanx_left_in[15]:7 chanx_left_in[15]:6 0.00341 +6 chanx_left_in[15]:9 chanx_left_in[15]:8 0.00341 +7 chanx_left_in[15]:8 chanx_left_in[15]:7 0.004465783 +8 chanx_left_in[15]:11 chanx_left_in[15]:10 0.0045 +9 chanx_left_in[15]:10 chanx_left_in[15]:9 0.0001634615 +10 chanx_left_in[15]:14 chanx_left_in[15]:13 0.01474554 +11 chanx_left_in[15]:15 chanx_left_in[15]:14 0.0045 +12 chanx_left_in[15]:16 chanx_left_in[15]:15 0.00341 +13 chanx_left_in[15]:16 chanx_left_in[15]:2 5.69697e-05 +14 chanx_left_in[15]:17 chanx_left_in[15]:16 0.00341 +15 chanx_left_in[15]:19 chanx_left_in[15]:18 0.00341 +16 chanx_left_in[15]:18 chanx_left_in[15]:17 0.0005303166 +17 chanx_left_in[15]:13 chanx_left_in[15]:12 0.0003035715 +18 chanx_left_in[15]:12 chanx_left_in[15]:11 0.001602679 + +*END + +*D_NET left_top_grid_pin_48_[0] 0.009789815 //LENGTH 77.085 LUMPCC 0.00175166 DR + +*CONN +*P left_top_grid_pin_48_[0] I *L 0.29796 *C 11.500 74.835 +*I mux_left_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 4.600 36.380 +*I mux_left_track_21\/mux_l1_in_0_:A0 I *L 0.001631 *C 32.030 33.320 +*I mux_left_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 27.505 36.380 +*N left_top_grid_pin_48_[0]:4 *C 27.543 36.380 +*N left_top_grid_pin_48_[0]:5 *C 28.475 36.380 +*N left_top_grid_pin_48_[0]:6 *C 28.520 36.335 +*N left_top_grid_pin_48_[0]:7 *C 31.993 33.320 +*N left_top_grid_pin_48_[0]:8 *C 28.565 33.320 +*N left_top_grid_pin_48_[0]:9 *C 28.520 33.365 +*N left_top_grid_pin_48_[0]:10 *C 28.520 35.360 +*N left_top_grid_pin_48_[0]:11 *C 28.513 35.360 +*N left_top_grid_pin_48_[0]:12 *C 4.600 36.380 +*N left_top_grid_pin_48_[0]:13 *C 4.600 36.335 +*N left_top_grid_pin_48_[0]:14 *C 4.600 35.418 +*N left_top_grid_pin_48_[0]:15 *C 4.607 35.360 +*N left_top_grid_pin_48_[0]:16 *C 9.200 35.360 +*N left_top_grid_pin_48_[0]:17 *C 9.200 36.035 +*N left_top_grid_pin_48_[0]:18 *C 9.200 36.047 +*N left_top_grid_pin_48_[0]:19 *C 9.200 70.713 +*N left_top_grid_pin_48_[0]:20 *C 9.220 70.720 +*N left_top_grid_pin_48_[0]:21 *C 11.492 70.720 +*N left_top_grid_pin_48_[0]:22 *C 11.500 70.778 + +*CAP +0 left_top_grid_pin_48_[0] 0.0002564288 +1 mux_left_track_1\/mux_l1_in_2_:A1 1e-06 +2 mux_left_track_21\/mux_l1_in_0_:A0 1e-06 +3 mux_left_track_5\/mux_l1_in_2_:A1 1e-06 +4 left_top_grid_pin_48_[0]:4 7.774093e-05 +5 left_top_grid_pin_48_[0]:5 7.774093e-05 +6 left_top_grid_pin_48_[0]:6 6.232255e-05 +7 left_top_grid_pin_48_[0]:7 0.0002507311 +8 left_top_grid_pin_48_[0]:8 0.0002507311 +9 left_top_grid_pin_48_[0]:9 0.000114527 +10 left_top_grid_pin_48_[0]:10 0.0002106881 +11 left_top_grid_pin_48_[0]:11 0.0005173836 +12 left_top_grid_pin_48_[0]:12 3.499486e-05 +13 left_top_grid_pin_48_[0]:13 8.197012e-05 +14 left_top_grid_pin_48_[0]:14 8.197012e-05 +15 left_top_grid_pin_48_[0]:15 0.0001736598 +16 left_top_grid_pin_48_[0]:16 0.0007438491 +17 left_top_grid_pin_48_[0]:17 5.280576e-05 +18 left_top_grid_pin_48_[0]:18 0.002150543 +19 left_top_grid_pin_48_[0]:19 0.002150543 +20 left_top_grid_pin_48_[0]:20 0.0002450485 +21 left_top_grid_pin_48_[0]:21 0.0002450485 +22 left_top_grid_pin_48_[0]:22 0.0002564288 +23 left_top_grid_pin_48_[0]:15 chanx_left_in[8] 2.26314e-06 +24 left_top_grid_pin_48_[0]:15 chanx_left_in[8]:16 5.081065e-05 +25 left_top_grid_pin_48_[0]:11 chanx_left_in[8]:15 0.0002543773 +26 left_top_grid_pin_48_[0]:16 chanx_left_in[8]:15 5.081065e-05 +27 left_top_grid_pin_48_[0]:16 chanx_left_in[8]:16 0.0002543773 +28 left_top_grid_pin_48_[0]:16 chanx_left_in[8]:17 2.26314e-06 +29 left_top_grid_pin_48_[0]:15 chanx_left_in[12] 0.0001028545 +30 left_top_grid_pin_48_[0]:11 chanx_left_in[12]:10 0.0004655243 +31 left_top_grid_pin_48_[0]:16 chanx_left_in[12] 0.0004655243 +32 left_top_grid_pin_48_[0]:16 chanx_left_in[12]:10 0.0001028545 + +*RES +0 left_top_grid_pin_48_[0] left_top_grid_pin_48_[0]:22 0.003622768 +1 left_top_grid_pin_48_[0]:12 mux_left_track_1\/mux_l1_in_2_:A1 0.152 +2 left_top_grid_pin_48_[0]:13 left_top_grid_pin_48_[0]:12 0.0045 +3 left_top_grid_pin_48_[0]:14 left_top_grid_pin_48_[0]:13 0.0008191965 +4 left_top_grid_pin_48_[0]:15 left_top_grid_pin_48_[0]:14 0.00341 +5 left_top_grid_pin_48_[0]:10 left_top_grid_pin_48_[0]:9 0.00178125 +6 left_top_grid_pin_48_[0]:10 left_top_grid_pin_48_[0]:6 0.0008705357 +7 left_top_grid_pin_48_[0]:11 left_top_grid_pin_48_[0]:10 0.00341 +8 left_top_grid_pin_48_[0]:5 left_top_grid_pin_48_[0]:4 0.0008325893 +9 left_top_grid_pin_48_[0]:6 left_top_grid_pin_48_[0]:5 0.0045 +10 left_top_grid_pin_48_[0]:4 mux_left_track_5\/mux_l1_in_2_:A1 0.152 +11 left_top_grid_pin_48_[0]:22 left_top_grid_pin_48_[0]:21 0.00341 +12 left_top_grid_pin_48_[0]:21 left_top_grid_pin_48_[0]:20 0.000356025 +13 left_top_grid_pin_48_[0]:20 left_top_grid_pin_48_[0]:19 0.00341 +14 left_top_grid_pin_48_[0]:19 left_top_grid_pin_48_[0]:18 0.005430849 +15 left_top_grid_pin_48_[0]:17 left_top_grid_pin_48_[0]:16 0.00010575 +16 left_top_grid_pin_48_[0]:18 left_top_grid_pin_48_[0]:17 0.00341 +17 left_top_grid_pin_48_[0]:8 left_top_grid_pin_48_[0]:7 0.003060268 +18 left_top_grid_pin_48_[0]:9 left_top_grid_pin_48_[0]:8 0.0045 +19 left_top_grid_pin_48_[0]:7 mux_left_track_21\/mux_l1_in_0_:A0 0.152 +20 left_top_grid_pin_48_[0]:16 left_top_grid_pin_48_[0]:15 0.0007194917 +21 left_top_grid_pin_48_[0]:16 left_top_grid_pin_48_[0]:11 0.003025625 + +*END + +*D_NET chany_top_out[2] 0.005985244 //LENGTH 46.230 LUMPCC 0.002700248 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_0_:X O *L 0 *C 84.400 64.600 +*P chany_top_out[2] O *L 0.7423 *C 77.740 102.070 +*N chany_top_out[2]:2 *C 77.740 100.698 +*N chany_top_out[2]:3 *C 77.743 100.640 +*N chany_top_out[2]:4 *C 78.185 100.640 +*N chany_top_out[2]:5 *C 78.200 100.633 +*N chany_top_out[2]:6 *C 78.200 66.648 +*N chany_top_out[2]:7 *C 78.220 66.640 +*N chany_top_out[2]:8 *C 84.633 66.640 +*N chany_top_out[2]:9 *C 84.640 66.583 +*N chany_top_out[2]:10 *C 84.640 64.645 +*N chany_top_out[2]:11 *C 84.640 64.600 +*N chany_top_out[2]:12 *C 84.400 64.600 + +*CAP +0 mux_top_track_4\/mux_l3_in_0_:X 1e-06 +1 chany_top_out[2] 0.0001052858 +2 chany_top_out[2]:2 0.0001052858 +3 chany_top_out[2]:3 3.952935e-05 +4 chany_top_out[2]:4 3.952935e-05 +5 chany_top_out[2]:5 0.0008666637 +6 chany_top_out[2]:6 0.0008666637 +7 chany_top_out[2]:7 0.0004230654 +8 chany_top_out[2]:8 0.0004230654 +9 chany_top_out[2]:9 0.0001506509 +10 chany_top_out[2]:10 0.0001506509 +11 chany_top_out[2]:11 5.901227e-05 +12 chany_top_out[2]:12 5.459354e-05 +13 chany_top_out[2]:6 chany_top_in[0]:8 0.0006958634 +14 chany_top_out[2]:4 chany_top_in[0]:11 1.698399e-05 +15 chany_top_out[2]:5 chany_top_in[0]:9 0.0006958634 +16 chany_top_out[2]:3 chany_top_in[0]:10 1.698399e-05 +17 chany_top_out[2]:6 chany_top_in[17]:8 0.0006372764 +18 chany_top_out[2]:5 chany_top_in[17]:9 0.0006372764 + +*RES +0 mux_top_track_4\/mux_l3_in_0_:X chany_top_out[2]:12 0.152 +1 chany_top_out[2]:12 chany_top_out[2]:11 0.0001304348 +2 chany_top_out[2]:11 chany_top_out[2]:10 0.0045 +3 chany_top_out[2]:10 chany_top_out[2]:9 0.001729911 +4 chany_top_out[2]:9 chany_top_out[2]:8 0.00341 +5 chany_top_out[2]:8 chany_top_out[2]:7 0.001004625 +6 chany_top_out[2]:7 chany_top_out[2]:6 0.00341 +7 chany_top_out[2]:6 chany_top_out[2]:5 0.005324316 +8 chany_top_out[2]:4 chany_top_out[2]:3 6.499219e-05 +9 chany_top_out[2]:5 chany_top_out[2]:4 0.00341 +10 chany_top_out[2]:2 chany_top_out[2] 0.001225446 +11 chany_top_out[2]:3 chany_top_out[2]:2 0.00341 + +*END + +*D_NET chany_top_out[11] 0.0005443913 //LENGTH 5.330 LUMPCC 0 DR + +*CONN +*I mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 93.900 96.900 +*P chany_top_out[11] O *L 0.7423 *C 93.840 102.070 +*N chany_top_out[11]:2 *C 93.840 96.945 +*N chany_top_out[11]:3 *C 93.840 96.900 + +*CAP +0 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[11] 0.0002548575 +2 chany_top_out[11]:2 0.0002548575 +3 chany_top_out[11]:3 3.367632e-05 + +*RES +0 mux_top_track_22\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[11]:3 0.152 +1 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +2 chany_top_out[11]:2 chany_top_out[11] 0.004575893 + +*END + +*D_NET chany_top_out[12] 0.001084267 //LENGTH 9.555 LUMPCC 0 DR + +*CONN +*I mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 80.445 93.840 +*P chany_top_out[12] O *L 0.7423 *C 79.580 102.035 +*N chany_top_out[12]:2 *C 79.580 96.560 +*N chany_top_out[12]:3 *C 80.500 96.560 +*N chany_top_out[12]:4 *C 80.500 93.885 +*N chany_top_out[12]:5 *C 80.445 93.840 + +*CAP +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[12] 0.0002976542 +2 chany_top_out[12]:2 0.0003501791 +3 chany_top_out[12]:3 0.0002294105 +4 chany_top_out[12]:4 0.0001768856 +5 chany_top_out[12]:5 2.91378e-05 + +*RES +0 mux_top_track_24\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[12]:5 0.152 +1 chany_top_out[12]:5 chany_top_out[12]:4 0.0045 +2 chany_top_out[12]:4 chany_top_out[12]:3 0.002388393 +3 chany_top_out[12]:2 chany_top_out[12] 0.004888393 +4 chany_top_out[12]:3 chany_top_out[12]:2 0.0008214285 + +*END + +*D_NET chany_top_out[18] 0.004667747 //LENGTH 41.310 LUMPCC 0.0003189075 DR + +*CONN +*I mux_top_track_36\/mux_l2_in_0_:X O *L 0 *C 74.300 82.960 +*P chany_top_out[18] O *L 0.7423 *C 95.680 102.070 +*N chany_top_out[18]:2 *C 95.680 83.017 +*N chany_top_out[18]:3 *C 95.672 82.960 +*N chany_top_out[18]:4 *C 75.907 82.960 +*N chany_top_out[18]:5 *C 75.900 82.960 +*N chany_top_out[18]:6 *C 75.855 82.960 +*N chany_top_out[18]:7 *C 74.338 82.960 + +*CAP +0 mux_top_track_36\/mux_l2_in_0_:X 1e-06 +1 chany_top_out[18] 0.0009541949 +2 chany_top_out[18]:2 0.0009541949 +3 chany_top_out[18]:3 0.001083381 +4 chany_top_out[18]:4 0.001083381 +5 chany_top_out[18]:5 3.606622e-05 +6 chany_top_out[18]:6 0.0001183103 +7 chany_top_out[18]:7 0.0001183103 +8 chany_top_out[18]:4 mux_tree_tapbuf_size2_6_sram[0]:7 0.0001048466 +9 chany_top_out[18]:4 mux_tree_tapbuf_size2_6_sram[0]:12 5.460719e-05 +10 chany_top_out[18]:3 mux_tree_tapbuf_size2_6_sram[0]:12 0.0001048466 +11 chany_top_out[18]:3 mux_tree_tapbuf_size2_6_sram[0]:13 5.460719e-05 + +*RES +0 mux_top_track_36\/mux_l2_in_0_:X chany_top_out[18]:7 0.152 +1 chany_top_out[18]:7 chany_top_out[18]:6 0.001354911 +2 chany_top_out[18]:6 chany_top_out[18]:5 0.0045 +3 chany_top_out[18]:5 chany_top_out[18]:4 0.00341 +4 chany_top_out[18]:4 chany_top_out[18]:3 0.003096517 +5 chany_top_out[18]:2 chany_top_out[18] 0.01701116 +6 chany_top_out[18]:3 chany_top_out[18]:2 0.00341 + +*END + +*D_NET chanx_left_out[8] 0.001212313 //LENGTH 9.270 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.180 22.440 +*P chanx_left_out[8] O *L 0.7423 *C 1.305 21.760 +*N chanx_left_out[8]:2 *C 5.513 21.760 +*N chanx_left_out[8]:3 *C 5.520 21.818 +*N chanx_left_out[8]:4 *C 5.520 22.780 +*N chanx_left_out[8]:5 *C 6.440 22.780 +*N chanx_left_out[8]:6 *C 6.440 22.780 +*N chanx_left_out[8]:7 *C 6.440 22.440 +*N chanx_left_out[8]:8 *C 8.143 22.440 + +*CAP +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[8] 0.0002999566 +2 chanx_left_out[8]:2 0.0002999566 +3 chanx_left_out[8]:3 7.495407e-05 +4 chanx_left_out[8]:4 0.000126144 +5 chanx_left_out[8]:5 7.929344e-05 +6 chanx_left_out[8]:6 5.863672e-05 +7 chanx_left_out[8]:7 0.0001498345 +8 chanx_left_out[8]:8 0.0001225375 + +*RES +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[8]:8 0.152 +1 chanx_left_out[8]:8 chanx_left_out[8]:7 0.001520089 +2 chanx_left_out[8]:6 chanx_left_out[8]:5 0.0045 +3 chanx_left_out[8]:5 chanx_left_out[8]:4 0.0008214285 +4 chanx_left_out[8]:3 chanx_left_out[8]:2 0.00341 +5 chanx_left_out[8]:2 chanx_left_out[8] 0.000659175 +6 chanx_left_out[8]:7 chanx_left_out[8]:6 0.0003035715 +7 chanx_left_out[8]:4 chanx_left_out[8]:3 0.0008593751 + +*END + +*D_NET ropt_net_124 0.0008982681 //LENGTH 7.670 LUMPCC 0 DR + +*CONN +*I mem_left_track_27\/BUFT_RR_84:X O *L 0 *C 6.900 52.700 +*I ropt_mt_inst_731:A I *L 0.001766 *C 3.220 55.760 +*N ropt_net_124:2 *C 3.258 55.760 +*N ropt_net_124:3 *C 4.095 55.760 +*N ropt_net_124:4 *C 4.140 55.715 +*N ropt_net_124:5 *C 4.140 52.745 +*N ropt_net_124:6 *C 4.185 52.700 +*N ropt_net_124:7 *C 6.863 52.700 + +*CAP +0 mem_left_track_27\/BUFT_RR_84:X 1e-06 +1 ropt_mt_inst_731:A 1e-06 +2 ropt_net_124:2 6.649593e-05 +3 ropt_net_124:3 6.649593e-05 +4 ropt_net_124:4 0.000198303 +5 ropt_net_124:5 0.000198303 +6 ropt_net_124:6 0.0001833351 +7 ropt_net_124:7 0.0001833351 + +*RES +0 mem_left_track_27\/BUFT_RR_84:X ropt_net_124:7 0.152 +1 ropt_net_124:2 ropt_mt_inst_731:A 0.152 +2 ropt_net_124:3 ropt_net_124:2 0.0007477679 +3 ropt_net_124:4 ropt_net_124:3 0.0045 +4 ropt_net_124:6 ropt_net_124:5 0.0045 +5 ropt_net_124:5 ropt_net_124:4 0.002651786 +6 ropt_net_124:7 ropt_net_124:6 0.002390625 + +*END + +*D_NET mux_tree_tapbuf_size2_13_sram[1] 0.002911948 //LENGTH 22.805 LUMPCC 0.0002992872 DR + +*CONN +*I mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.445 66.640 +*I mux_top_track_38\/mux_l2_in_0_:S I *L 0.00357 *C 64.760 72.080 +*I mem_top_track_38\/FTB_26__31:A I *L 0.001746 *C 63.020 69.360 +*N mux_tree_tapbuf_size2_13_sram[1]:3 *C 63.020 69.360 +*N mux_tree_tapbuf_size2_13_sram[1]:4 *C 63.020 69.405 +*N mux_tree_tapbuf_size2_13_sram[1]:5 *C 63.020 72.715 +*N mux_tree_tapbuf_size2_13_sram[1]:6 *C 63.065 72.760 +*N mux_tree_tapbuf_size2_13_sram[1]:7 *C 64.400 72.760 +*N mux_tree_tapbuf_size2_13_sram[1]:8 *C 64.722 72.080 +*N mux_tree_tapbuf_size2_13_sram[1]:9 *C 64.400 72.080 +*N mux_tree_tapbuf_size2_13_sram[1]:10 *C 63.940 72.080 +*N mux_tree_tapbuf_size2_13_sram[1]:11 *C 63.940 71.400 +*N mux_tree_tapbuf_size2_13_sram[1]:12 *C 73.095 71.400 +*N mux_tree_tapbuf_size2_13_sram[1]:13 *C 73.140 71.355 +*N mux_tree_tapbuf_size2_13_sram[1]:14 *C 73.140 66.685 +*N mux_tree_tapbuf_size2_13_sram[1]:15 *C 73.140 66.640 +*N mux_tree_tapbuf_size2_13_sram[1]:16 *C 73.445 66.640 + +*CAP +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_38\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_38\/FTB_26__31:A 1e-06 +3 mux_tree_tapbuf_size2_13_sram[1]:3 4.030412e-05 +4 mux_tree_tapbuf_size2_13_sram[1]:4 0.000202402 +5 mux_tree_tapbuf_size2_13_sram[1]:5 0.000202402 +6 mux_tree_tapbuf_size2_13_sram[1]:6 6.592374e-05 +7 mux_tree_tapbuf_size2_13_sram[1]:7 0.0001128449 +8 mux_tree_tapbuf_size2_13_sram[1]:8 3.438817e-05 +9 mux_tree_tapbuf_size2_13_sram[1]:9 0.0001012278 +10 mux_tree_tapbuf_size2_13_sram[1]:10 6.402165e-05 +11 mux_tree_tapbuf_size2_13_sram[1]:11 0.0005994916 +12 mux_tree_tapbuf_size2_13_sram[1]:12 0.0005553885 +13 mux_tree_tapbuf_size2_13_sram[1]:13 0.0002680466 +14 mux_tree_tapbuf_size2_13_sram[1]:14 0.0002680466 +15 mux_tree_tapbuf_size2_13_sram[1]:15 4.908257e-05 +16 mux_tree_tapbuf_size2_13_sram[1]:16 4.609103e-05 +17 mux_tree_tapbuf_size2_13_sram[1]:12 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 8.775701e-05 +18 mux_tree_tapbuf_size2_13_sram[1]:11 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 8.775701e-05 +19 mux_tree_tapbuf_size2_13_sram[1]:12 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.698892e-06 +20 mux_tree_tapbuf_size2_13_sram[1]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.862726e-05 +21 mux_tree_tapbuf_size2_13_sram[1]:7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.862726e-05 +22 mux_tree_tapbuf_size2_13_sram[1]:11 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.698892e-06 +23 mux_tree_tapbuf_size2_13_sram[1]:10 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.156044e-05 +24 mux_tree_tapbuf_size2_13_sram[1]:9 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.156044e-05 + +*RES +0 mem_top_track_38\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_13_sram[1]:16 0.152 +1 mux_tree_tapbuf_size2_13_sram[1]:8 mux_top_track_38\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_13_sram[1]:16 mux_tree_tapbuf_size2_13_sram[1]:15 0.0001657609 +3 mux_tree_tapbuf_size2_13_sram[1]:15 mux_tree_tapbuf_size2_13_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size2_13_sram[1]:14 mux_tree_tapbuf_size2_13_sram[1]:13 0.004169643 +5 mux_tree_tapbuf_size2_13_sram[1]:12 mux_tree_tapbuf_size2_13_sram[1]:11 0.008174107 +6 mux_tree_tapbuf_size2_13_sram[1]:13 mux_tree_tapbuf_size2_13_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size2_13_sram[1]:3 mem_top_track_38\/FTB_26__31:A 0.152 +8 mux_tree_tapbuf_size2_13_sram[1]:4 mux_tree_tapbuf_size2_13_sram[1]:3 0.0045 +9 mux_tree_tapbuf_size2_13_sram[1]:6 mux_tree_tapbuf_size2_13_sram[1]:5 0.0045 +10 mux_tree_tapbuf_size2_13_sram[1]:5 mux_tree_tapbuf_size2_13_sram[1]:4 0.002955357 +11 mux_tree_tapbuf_size2_13_sram[1]:7 mux_tree_tapbuf_size2_13_sram[1]:6 0.001191964 +12 mux_tree_tapbuf_size2_13_sram[1]:11 mux_tree_tapbuf_size2_13_sram[1]:10 0.0006071429 +13 mux_tree_tapbuf_size2_13_sram[1]:10 mux_tree_tapbuf_size2_13_sram[1]:9 0.0004107142 +14 mux_tree_tapbuf_size2_13_sram[1]:9 mux_tree_tapbuf_size2_13_sram[1]:8 0.0002879464 +15 mux_tree_tapbuf_size2_13_sram[1]:9 mux_tree_tapbuf_size2_13_sram[1]:7 0.000607143 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.001208604 //LENGTH 10.255 LUMPCC 0 DR + +*CONN +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 67.465 28.560 +*I mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 69.635 31.620 +*I mux_top_track_12\/mux_l1_in_0_:S I *L 0.00357 *C 70.720 34.340 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 70.683 34.340 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 69.505 34.340 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 69.460 34.295 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 69.635 31.620 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 69.460 31.620 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 69.460 31.620 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 69.460 28.605 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 69.415 28.560 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 67.502 28.560 + +*CAP +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_12\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 9.246313e-05 +4 mux_tree_tapbuf_size2_1_sram[0]:4 9.246313e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:5 0.0001473568 +6 mux_tree_tapbuf_size2_1_sram[0]:6 5.750359e-05 +7 mux_tree_tapbuf_size2_1_sram[0]:7 6.037753e-05 +8 mux_tree_tapbuf_size2_1_sram[0]:8 0.0003469231 +9 mux_tree_tapbuf_size2_1_sram[0]:9 0.0001693684 +10 mux_tree_tapbuf_size2_1_sram[0]:10 0.0001195742 +11 mux_tree_tapbuf_size2_1_sram[0]:11 0.0001195742 + +*RES +0 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:3 mux_top_track_12\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[0]:4 mux_tree_tapbuf_size2_1_sram[0]:3 0.001051339 +3 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_1_sram[0]:7 mux_tree_tapbuf_size2_1_sram[0]:6 9.51087e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:5 0.002388393 +7 mux_tree_tapbuf_size2_1_sram[0]:6 mem_top_track_12\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.002691964 +10 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.001707589 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.001190461 //LENGTH 8.920 LUMPCC 0 DR + +*CONN +*I mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 61.485 88.060 +*I mux_top_track_18\/mux_l2_in_0_:S I *L 0.00357 *C 57.140 91.120 +*I mem_top_track_18\/FTB_17__22:A I *L 0.001746 *C 62.100 91.120 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 62.062 91.120 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 57.178 91.120 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 61.180 91.120 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 61.180 91.075 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 61.180 88.105 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 61.180 88.060 +*N mux_tree_tapbuf_size2_4_sram[1]:9 *C 61.485 88.060 + +*CAP +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_18\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_18\/FTB_17__22:A 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 6.425477e-05 +4 mux_tree_tapbuf_size2_4_sram[1]:4 0.0002766242 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.0003761711 +6 mux_tree_tapbuf_size2_4_sram[1]:6 0.0001814294 +7 mux_tree_tapbuf_size2_4_sram[1]:7 0.0001814294 +8 mux_tree_tapbuf_size2_4_sram[1]:8 5.512133e-05 +9 mux_tree_tapbuf_size2_4_sram[1]:9 5.243094e-05 + +*RES +0 mem_top_track_18\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:9 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:3 mem_top_track_18\/FTB_17__22:A 0.152 +2 mux_tree_tapbuf_size2_4_sram[1]:4 mux_top_track_18\/mux_l2_in_0_:S 0.152 +3 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.003573661 +4 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:3 0.0007879465 +5 mux_tree_tapbuf_size2_4_sram[1]:6 mux_tree_tapbuf_size2_4_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.0045 +7 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.002651786 +8 mux_tree_tapbuf_size2_4_sram[1]:9 mux_tree_tapbuf_size2_4_sram[1]:8 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[1] 0.001285304 //LENGTH 10.975 LUMPCC 0 DR + +*CONN +*I mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 39.405 86.020 +*I mem_top_track_30\/FTB_22__27:A I *L 0.001746 *C 43.700 82.960 +*I mux_top_track_30\/mux_l2_in_0_:S I *L 0.008363 *C 40.020 88.570 +*N mux_tree_tapbuf_size2_9_sram[1]:3 *C 43.465 88.570 +*N mux_tree_tapbuf_size2_9_sram[1]:4 *C 43.663 82.960 +*N mux_tree_tapbuf_size2_9_sram[1]:5 *C 43.285 82.960 +*N mux_tree_tapbuf_size2_9_sram[1]:6 *C 43.240 83.005 +*N mux_tree_tapbuf_size2_9_sram[1]:7 *C 43.240 88.695 +*N mux_tree_tapbuf_size2_9_sram[1]:8 *C 43.240 88.740 +*N mux_tree_tapbuf_size2_9_sram[1]:9 *C 43.240 88.625 +*N mux_tree_tapbuf_size2_9_sram[1]:10 *C 39.795 88.478 +*N mux_tree_tapbuf_size2_9_sram[1]:11 *C 39.795 88.570 +*N mux_tree_tapbuf_size2_9_sram[1]:12 *C 40.020 88.570 +*N mux_tree_tapbuf_size2_9_sram[1]:13 *C 40.020 88.525 +*N mux_tree_tapbuf_size2_9_sram[1]:14 *C 40.020 86.065 +*N mux_tree_tapbuf_size2_9_sram[1]:15 *C 39.975 86.020 +*N mux_tree_tapbuf_size2_9_sram[1]:16 *C 39.443 86.020 + +*CAP +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_30\/FTB_22__27:A 1e-06 +2 mux_top_track_30\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_9_sram[1]:3 1e-06 +4 mux_tree_tapbuf_size2_9_sram[1]:4 4.439996e-05 +5 mux_tree_tapbuf_size2_9_sram[1]:5 4.439996e-05 +6 mux_tree_tapbuf_size2_9_sram[1]:6 0.0003807157 +7 mux_tree_tapbuf_size2_9_sram[1]:7 0.0003807157 +8 mux_tree_tapbuf_size2_9_sram[1]:8 1.610866e-05 +9 mux_tree_tapbuf_size2_9_sram[1]:9 1.610866e-05 +10 mux_tree_tapbuf_size2_9_sram[1]:10 1e-06 +11 mux_tree_tapbuf_size2_9_sram[1]:11 1e-06 +12 mux_tree_tapbuf_size2_9_sram[1]:12 1e-06 +13 mux_tree_tapbuf_size2_9_sram[1]:13 0.0001442781 +14 mux_tree_tapbuf_size2_9_sram[1]:14 0.0001442781 +15 mux_tree_tapbuf_size2_9_sram[1]:15 5.364967e-05 +16 mux_tree_tapbuf_size2_9_sram[1]:16 5.364967e-05 + +*RES +0 mem_top_track_30\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_9_sram[1]:16 0.152 +1 mux_tree_tapbuf_size2_9_sram[1]:8 mux_tree_tapbuf_size2_9_sram[1]:7 0.0045 +2 mux_tree_tapbuf_size2_9_sram[1]:7 mux_tree_tapbuf_size2_9_sram[1]:6 0.005080357 +3 mux_tree_tapbuf_size2_9_sram[1]:5 mux_tree_tapbuf_size2_9_sram[1]:4 0.0003370536 +4 mux_tree_tapbuf_size2_9_sram[1]:6 mux_tree_tapbuf_size2_9_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size2_9_sram[1]:4 mem_top_track_30\/FTB_22__27:A 0.152 +6 mux_tree_tapbuf_size2_9_sram[1]:13 mux_tree_tapbuf_size2_9_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size2_9_sram[1]:15 mux_tree_tapbuf_size2_9_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size2_9_sram[1]:14 mux_tree_tapbuf_size2_9_sram[1]:13 0.002196429 +9 mux_tree_tapbuf_size2_9_sram[1]:16 mux_tree_tapbuf_size2_9_sram[1]:15 0.0004754465 +10 mux_tree_tapbuf_size2_9_sram[1]:9 mux_tree_tapbuf_size2_9_sram[1]:8 4.492188e-05 +11 mux_tree_tapbuf_size2_9_sram[1]:9 mux_tree_tapbuf_size2_9_sram[1]:3 0.0002008929 +12 mux_tree_tapbuf_size2_9_sram[1]:11 mux_tree_tapbuf_size2_9_sram[1]:10 1e-05 +13 mux_tree_tapbuf_size2_9_sram[1]:12 mux_tree_tapbuf_size2_9_sram[1]:11 0.000200625 +14 mux_tree_tapbuf_size2_9_sram[1]:12 mux_tree_tapbuf_size2_9_sram[1]:9 0.002875268 +15 mux_tree_tapbuf_size2_9_sram[1]:12 mux_top_track_30\/mux_l2_in_0_:S 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.0008402157 //LENGTH 8.140 LUMPCC 0 DR + +*CONN +*I mem_top_track_12\/FTB_14__19:X O *L 0 *C 67.845 36.720 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 66.415 42.500 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 66.453 42.500 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 67.115 42.500 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 67.160 42.455 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 67.160 36.765 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 *C 67.205 36.720 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 *C 67.808 36.720 + +*CAP +0 mem_top_track_12\/FTB_14__19:X 1e-06 +1 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 6.482114e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 6.482114e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.000299226 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.000299226 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 5.50607e-05 +7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 5.50607e-05 + +*RES +0 mem_top_track_12\/FTB_14__19:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.005080357 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001366788 //LENGTH 12.690 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 83.565 39.440 +*I mem_top_track_8\/FTB_9__14:A I *L 0.001746 *C 88.780 36.720 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 85.920 41.480 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 85.958 41.480 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 87.355 41.480 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 87.400 41.435 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 88.743 36.720 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 87.445 36.720 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 87.400 36.765 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 87.400 39.440 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 87.355 39.440 +*N mux_tree_tapbuf_size3_0_sram[1]:11 *C 83.603 39.440 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_8\/FTB_9__14:A 1e-06 +2 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 0.00011018 +4 mux_tree_tapbuf_size3_0_sram[1]:4 0.00011018 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0001118253 +6 mux_tree_tapbuf_size3_0_sram[1]:6 9.20457e-05 +7 mux_tree_tapbuf_size3_0_sram[1]:7 9.20457e-05 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0001283841 +9 mux_tree_tapbuf_size3_0_sram[1]:9 0.000267416 +10 mux_tree_tapbuf_size3_0_sram[1]:10 0.0002258555 +11 mux_tree_tapbuf_size3_0_sram[1]:11 0.0002258555 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.001158482 +2 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size3_0_sram[1]:6 mem_top_track_8\/FTB_9__14:A 0.152 +4 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.002388393 +6 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:5 0.00178125 +7 mux_tree_tapbuf_size3_0_sram[1]:11 mux_tree_tapbuf_size3_0_sram[1]:10 0.003350446 +8 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.001247768 +9 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_0_sram[1]:3 mux_top_track_8\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[0] 0.006911821 //LENGTH 52.123 LUMPCC 0.0006413804 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 93.685 66.300 +*I mux_top_track_2\/mux_l1_in_1_:S I *L 0.00357 *C 60.360 63.240 +*I mux_top_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 53.720 61.200 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 64.115 60.860 +*N mux_tree_tapbuf_size5_0_sram[0]:4 *C 64.115 60.860 +*N mux_tree_tapbuf_size5_0_sram[0]:5 *C 63.940 60.520 +*N mux_tree_tapbuf_size5_0_sram[0]:6 *C 53.758 61.200 +*N mux_tree_tapbuf_size5_0_sram[0]:7 *C 56.580 61.200 +*N mux_tree_tapbuf_size5_0_sram[0]:8 *C 56.580 60.860 +*N mux_tree_tapbuf_size5_0_sram[0]:9 *C 57.960 60.860 +*N mux_tree_tapbuf_size5_0_sram[0]:10 *C 57.960 60.520 +*N mux_tree_tapbuf_size5_0_sram[0]:11 *C 60.260 60.520 +*N mux_tree_tapbuf_size5_0_sram[0]:12 *C 60.260 60.565 +*N mux_tree_tapbuf_size5_0_sram[0]:13 *C 60.260 63.240 +*N mux_tree_tapbuf_size5_0_sram[0]:14 *C 60.260 63.240 +*N mux_tree_tapbuf_size5_0_sram[0]:15 *C 60.268 63.240 +*N mux_tree_tapbuf_size5_0_sram[0]:16 *C 93.373 63.240 +*N mux_tree_tapbuf_size5_0_sram[0]:17 *C 93.380 63.298 +*N mux_tree_tapbuf_size5_0_sram[0]:18 *C 93.380 66.255 +*N mux_tree_tapbuf_size5_0_sram[0]:19 *C 93.380 66.300 +*N mux_tree_tapbuf_size5_0_sram[0]:20 *C 93.685 66.300 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_2\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_2\/mux_l1_in_0_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size5_0_sram[0]:4 5.603165e-05 +5 mux_tree_tapbuf_size5_0_sram[0]:5 0.000280423 +6 mux_tree_tapbuf_size5_0_sram[0]:6 0.0001566335 +7 mux_tree_tapbuf_size5_0_sram[0]:7 0.0001806637 +8 mux_tree_tapbuf_size5_0_sram[0]:8 0.0001212194 +9 mux_tree_tapbuf_size5_0_sram[0]:9 0.0001228065 +10 mux_tree_tapbuf_size5_0_sram[0]:10 0.0001736291 +11 mux_tree_tapbuf_size5_0_sram[0]:11 0.0004341546 +12 mux_tree_tapbuf_size5_0_sram[0]:12 0.0001637435 +13 mux_tree_tapbuf_size5_0_sram[0]:13 3.03404e-05 +14 mux_tree_tapbuf_size5_0_sram[0]:14 0.0001973176 +15 mux_tree_tapbuf_size5_0_sram[0]:15 0.001957812 +16 mux_tree_tapbuf_size5_0_sram[0]:16 0.001957812 +17 mux_tree_tapbuf_size5_0_sram[0]:17 0.0001679801 +18 mux_tree_tapbuf_size5_0_sram[0]:18 0.0001679801 +19 mux_tree_tapbuf_size5_0_sram[0]:19 4.808255e-05 +20 mux_tree_tapbuf_size5_0_sram[0]:20 4.981065e-05 +21 mux_tree_tapbuf_size5_0_sram[0]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001134179 +22 mux_tree_tapbuf_size5_0_sram[0]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001134179 +23 mux_tree_tapbuf_size5_0_sram[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.237557e-05 +24 mux_tree_tapbuf_size5_0_sram[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.992086e-06 +25 mux_tree_tapbuf_size5_0_sram[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.237557e-05 +26 mux_tree_tapbuf_size5_0_sram[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.473605e-06 +27 mux_tree_tapbuf_size5_0_sram[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.473605e-06 +28 mux_tree_tapbuf_size5_0_sram[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.992086e-06 +29 mux_tree_tapbuf_size5_0_sram[0]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001104311 +30 mux_tree_tapbuf_size5_0_sram[0]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001104311 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_0_sram[0]:20 0.152 +1 mux_tree_tapbuf_size5_0_sram[0]:6 mux_top_track_2\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:10 0.002053572 +3 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:5 0.003285714 +4 mux_tree_tapbuf_size5_0_sram[0]:12 mux_tree_tapbuf_size5_0_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size5_0_sram[0]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:13 0.0045 +7 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:12 0.002388393 +8 mux_tree_tapbuf_size5_0_sram[0]:15 mux_tree_tapbuf_size5_0_sram[0]:14 0.00341 +9 mux_tree_tapbuf_size5_0_sram[0]:17 mux_tree_tapbuf_size5_0_sram[0]:16 0.00341 +10 mux_tree_tapbuf_size5_0_sram[0]:16 mux_tree_tapbuf_size5_0_sram[0]:15 0.00518645 +11 mux_tree_tapbuf_size5_0_sram[0]:19 mux_tree_tapbuf_size5_0_sram[0]:18 0.0045 +12 mux_tree_tapbuf_size5_0_sram[0]:18 mux_tree_tapbuf_size5_0_sram[0]:17 0.002640625 +13 mux_tree_tapbuf_size5_0_sram[0]:20 mux_tree_tapbuf_size5_0_sram[0]:19 0.0001657609 +14 mux_tree_tapbuf_size5_0_sram[0]:13 mux_top_track_2\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size5_0_sram[0]:7 mux_tree_tapbuf_size5_0_sram[0]:6 0.002520089 +16 mux_tree_tapbuf_size5_0_sram[0]:8 mux_tree_tapbuf_size5_0_sram[0]:7 0.0003035715 +17 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:8 0.001232143 +18 mux_tree_tapbuf_size5_0_sram[0]:10 mux_tree_tapbuf_size5_0_sram[0]:9 0.0003035715 +19 mux_tree_tapbuf_size5_0_sram[0]:5 mux_tree_tapbuf_size5_0_sram[0]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_3_ccff_tail[0] 0.0006997078 //LENGTH 5.320 LUMPCC 0 DR + +*CONN +*I mem_left_track_7\/FTB_8__13:X O *L 0 *C 31.505 52.360 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 31.915 47.940 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 *C 31.915 47.940 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 *C 31.740 47.940 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 *C 31.740 47.985 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 *C 31.740 52.315 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 *C 31.740 52.360 +*N mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 *C 31.505 52.360 + +*CAP +0 mem_left_track_7\/FTB_8__13:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 4.626262e-05 +3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 5.012917e-05 +4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 0.0002471152 +5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 0.0002471152 +6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 5.475001e-05 +7 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 5.233568e-05 + +*RES +0 mem_left_track_7\/FTB_8__13:X mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_3_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.001815735 //LENGTH 14.065 LUMPCC 0.0002765237 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 80.805 58.820 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 86.195 55.420 +*I mux_top_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 82.240 56.055 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 82.240 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 82.225 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 81.903 61.200 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 81.880 61.155 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 82.240 56.055 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 82.270 55.690 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 82.385 55.830 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 86.157 55.420 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 82.340 55.420 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 81.925 55.420 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 81.880 55.465 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 81.880 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 81.420 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 81.375 58.820 +*N mux_tree_tapbuf_size6_1_sram[1]:17 *C 80.843 58.820 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 4.950295e-05 +5 mux_tree_tapbuf_size6_1_sram[1]:5 4.950295e-05 +6 mux_tree_tapbuf_size6_1_sram[1]:6 9.593951e-05 +7 mux_tree_tapbuf_size6_1_sram[1]:7 5.688068e-05 +8 mux_tree_tapbuf_size6_1_sram[1]:8 3.634735e-05 +9 mux_tree_tapbuf_size6_1_sram[1]:9 3.404136e-05 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.0002557706 +11 mux_tree_tapbuf_size6_1_sram[1]:11 0.0003202616 +12 mux_tree_tapbuf_size6_1_sram[1]:12 3.879723e-05 +13 mux_tree_tapbuf_size6_1_sram[1]:13 0.0001513153 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0002788694 +15 mux_tree_tapbuf_size6_1_sram[1]:15 6.127455e-05 +16 mux_tree_tapbuf_size6_1_sram[1]:16 5.335393e-05 +17 mux_tree_tapbuf_size6_1_sram[1]:17 5.335393e-05 +18 mux_tree_tapbuf_size6_1_sram[1]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.84394e-05 +19 mux_tree_tapbuf_size6_1_sram[1]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 7.636558e-07 +20 mux_tree_tapbuf_size6_1_sram[1]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.353827e-05 +21 mux_tree_tapbuf_size6_1_sram[1]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 4.247835e-06 +22 mux_tree_tapbuf_size6_1_sram[1]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 7.636558e-07 +23 mux_tree_tapbuf_size6_1_sram[1]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 4.247835e-06 +24 mux_tree_tapbuf_size6_1_sram[1]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 1.272679e-06 +25 mux_tree_tapbuf_size6_1_sram[1]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 1.272679e-06 +26 mux_tree_tapbuf_size6_1_sram[1]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.84394e-05 +27 mux_tree_tapbuf_size6_1_sram[1]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.353827e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:17 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:4 mux_top_track_4\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.0001752718 +3 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.0004107143 +6 mux_tree_tapbuf_size6_1_sram[1]:17 mux_tree_tapbuf_size6_1_sram[1]:16 0.0004754465 +7 mux_tree_tapbuf_size6_1_sram[1]:7 mux_top_track_4\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.0003705358 +9 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size6_1_sram[1]:10 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.003408483 +12 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:9 0.0003660714 +13 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.0002122093 +14 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0001026786 +15 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.002995536 +16 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:6 0.002084821 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004409718 //LENGTH 3.685 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 77.565 61.540 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 80.960 61.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 80.922 61.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 77.603 61.540 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002194859 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002194859 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002964286 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009001918 //LENGTH 5.710 LUMPCC 0.0002699753 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_1_:X O *L 0 *C 11.325 40.120 +*I mux_left_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 13.575 37.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 13.538 37.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 11.545 37.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 11.500 37.445 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 11.500 40.075 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 11.500 40.120 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 11.325 40.120 + +*CAP +0 mux_left_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001085427 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001085427 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001476893 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001476893 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.812422e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.762839e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 prog_clk[0]:426 4.920854e-07 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:425 4.920854e-07 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:427 4.722756e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:424 4.722756e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 left_bottom_grid_pin_1_[0]:10 8.726802e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 left_bottom_grid_pin_1_[0]:9 8.726802e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001779018 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006302084 //LENGTH 4.610 LUMPCC 0.0001402349 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_1_:X O *L 0 *C 59.515 63.920 +*I mux_top_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.595 60.860 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.595 60.860 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 58.880 60.860 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.880 60.905 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.880 63.875 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.925 63.920 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 59.478 63.920 + +*CAP +0 mux_top_track_2\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.566195e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.962628e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001776517 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001776517 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.69092e-06 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.69092e-06 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 top_left_grid_pin_39_[0]:6 1.331087e-07 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 top_left_grid_pin_39_[0]:5 1.331087e-07 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_39_[0]:6 3.499217e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_39_[0]:5 3.499217e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 top_left_grid_pin_41_[0]:6 3.499217e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 top_left_grid_pin_41_[0]:5 3.499217e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001548913 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002651786 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003649436 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_0_:X O *L 0 *C 25.475 69.020 +*I mux_left_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 22.905 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 22.943 69.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 25.438 69.020 + +*CAP +0 mux_left_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001814718 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001814718 + +*RES +0 mux_left_track_3\/mux_l1_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002227679 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008730341 //LENGTH 6.050 LUMPCC 0.0003929937 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_1_:X O *L 0 *C 28.805 66.300 +*I mux_left_track_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.395 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 28.395 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 28.520 60.905 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.520 66.255 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.520 66.300 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 28.805 66.300 + +*CAP +0 mux_left_track_7\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.180252e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001703512 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001703512 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.66407e-05 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.889495e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:464 6.332075e-05 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 prog_clk[0]:396 6.332075e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.267298e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.267298e-05 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001205031 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001205031 + +*RES +0 mux_left_track_7\/mux_l1_in_1_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001548913 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.004776786 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_7\/mux_l2_in_0_:A0 0.152 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008210014 //LENGTH 7.280 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 47.095 41.480 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 45.445 36.380 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 45.445 36.380 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 45.540 36.425 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 45.540 41.435 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 45.585 41.480 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 47.058 41.480 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.714396e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002683204 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002683204 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001276083 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001276083 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004473215 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005562058 //LENGTH 52.550 LUMPCC 0.0003769069 DR + +*CONN +*I mux_top_track_12\/mux_l2_in_0_:X O *L 0 *C 73.885 40.120 +*I mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 74.340 91.275 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 74.340 91.275 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 74.520 91.120 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 74.520 91.075 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 74.520 40.165 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 74.475 40.120 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 73.922 40.120 + +*CAP +0 mux_top_track_12\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.28779e-05 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.455421e-05 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002472585 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.002472585 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.527444e-05 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.527444e-05 +8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_34_[0]:12 2.662815e-05 +9 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_34_[0]:14 5.271485e-05 +10 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_34_[0]:16 0.0001091104 +11 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_34_[0]:13 2.662815e-05 +12 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_34_[0]:16 5.271485e-05 +13 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_34_[0]:17 0.0001091104 + +*RES +0 mux_top_track_12\/mux_l2_in_0_:X mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.04545536 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.782609e-05 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_12\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000886008 //LENGTH 6.630 LUMPCC 0.0001075393 DR + +*CONN +*I mux_top_track_26\/mux_l2_in_0_:X O *L 0 *C 55.485 97.240 +*I mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 59.560 99.085 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 59.523 98.990 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 58.925 98.940 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.880 98.895 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.880 97.285 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.835 97.240 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 55.523 97.240 + +*CAP +0 mux_top_track_26\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.138031e-05 +3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.138031e-05 +4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.831807e-05 +5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.831807e-05 +6 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002485359 +7 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002485359 +8 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[19] 5.376965e-05 +9 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[19]:14 5.376965e-05 + +*RES +0 mux_top_track_26\/mux_l2_in_0_:X mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005334822 +3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_26/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002957589 + +*END + +*D_NET mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001133773 //LENGTH 8.865 LUMPCC 0.000324824 DR + +*CONN +*I mux_top_track_38\/mux_l1_in_0_:X O *L 0 *C 59.165 69.360 +*I mux_top_track_38\/mux_l2_in_0_:A1 I *L 0.00198 *C 64.040 72.420 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 64.002 72.420 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 60.305 72.420 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 60.260 72.375 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 60.260 69.405 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 60.215 69.360 +*N mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 59.203 69.360 + +*CAP +0 mux_top_track_38\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_38\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001671618 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001671618 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001575029 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001575029 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.880983e-05 +7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.880983e-05 +8 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_13_sram[1]:7 4.862726e-05 +9 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_13_sram[1]:9 1.156044e-05 +10 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_13_sram[1]:12 1.698892e-06 +11 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_13_sram[1]:6 4.862726e-05 +12 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_13_sram[1]:10 1.156044e-05 +13 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_13_sram[1]:11 1.698892e-06 +14 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 5.173077e-05 +15 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 5.173077e-05 +16 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_108:57 1.209119e-05 +17 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_108:59 3.964584e-06 +18 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_108:58 1.209119e-05 +19 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_108:60 3.964584e-06 +20 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_108:61 1.869824e-05 +21 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_108:62 1.404062e-05 +22 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_108:56 1.869824e-05 +23 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_108:61 1.404062e-05 + +*RES +0 mux_top_track_38\/mux_l1_in_0_:X mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_38\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00330134 +3 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002651786 +6 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000904018 + +*END + +*D_NET mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001315846 //LENGTH 11.575 LUMPCC 0.0001218094 DR + +*CONN +*I mux_left_track_21\/mux_l1_in_0_:X O *L 0 *C 30.075 33.660 +*I mux_left_track_21\/mux_l2_in_0_:A1 I *L 0.00198 *C 30.820 23.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 30.783 23.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 30.405 23.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 30.360 23.505 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 30.360 33.615 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 30.360 33.660 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 30.075 33.660 + +*CAP +0 mux_left_track_21\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_21\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.303403e-05 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.303403e-05 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004951106 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004951106 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.759511e-05 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.815276e-05 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_107:37 5.277633e-05 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_107:38 8.12835e-06 +10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_107:25 5.277633e-05 +11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_107:37 8.12835e-06 + +*RES +0 mux_left_track_21\/mux_l1_in_0_:X mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.009026786 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003370536 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_21\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_8/BUF_net_43 0.000540862 //LENGTH 4.505 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/BUFT_RR_43:X O *L 0 *C 98.900 86.360 +*I mux_top_track_8\/BUFT_P_88:A I *L 0.001776 *C 97.060 88.400 +*N mux_top_track_8/BUF_net_43:2 *C 97.060 88.400 +*N mux_top_track_8/BUF_net_43:3 *C 97.060 88.355 +*N mux_top_track_8/BUF_net_43:4 *C 97.060 86.405 +*N mux_top_track_8/BUF_net_43:5 *C 97.105 86.360 +*N mux_top_track_8/BUF_net_43:6 *C 98.863 86.360 + +*CAP +0 mux_top_track_8\/BUFT_RR_43:X 1e-06 +1 mux_top_track_8\/BUFT_P_88:A 1e-06 +2 mux_top_track_8/BUF_net_43:2 3.101662e-05 +3 mux_top_track_8/BUF_net_43:3 0.0001197785 +4 mux_top_track_8/BUF_net_43:4 0.0001197785 +5 mux_top_track_8/BUF_net_43:5 0.0001341442 +6 mux_top_track_8/BUF_net_43:6 0.0001341442 + +*RES +0 mux_top_track_8\/BUFT_RR_43:X mux_top_track_8/BUF_net_43:6 0.152 +1 mux_top_track_8/BUF_net_43:6 mux_top_track_8/BUF_net_43:5 0.001569196 +2 mux_top_track_8/BUF_net_43:5 mux_top_track_8/BUF_net_43:4 0.0045 +3 mux_top_track_8/BUF_net_43:4 mux_top_track_8/BUF_net_43:3 0.001741072 +4 mux_top_track_8/BUF_net_43:2 mux_top_track_8\/BUFT_P_88:A 0.152 +5 mux_top_track_8/BUF_net_43:3 mux_top_track_8/BUF_net_43:2 0.0045 + +*END + +*D_NET chany_top_in[10] 0.0131978 //LENGTH 110.555 LUMPCC 0.002281968 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 73.140 102.070 +*I mux_left_track_21\/mux_l1_in_0_:A1 I *L 0.00198 *C 32.200 34.340 +*N chany_top_in[10]:2 *C 32.200 34.340 +*N chany_top_in[10]:3 *C 32.200 34.340 +*N chany_top_in[10]:4 *C 32.200 34.000 +*N chany_top_in[10]:5 *C 32.208 34.000 +*N chany_top_in[10]:6 *C 68.060 34.000 +*N chany_top_in[10]:7 *C 68.080 34.008 +*N chany_top_in[10]:8 *C 68.080 83.835 +*N chany_top_in[10]:9 *C 68.080 97.913 +*N chany_top_in[10]:10 *C 68.100 97.920 +*N chany_top_in[10]:11 *C 73.133 97.920 +*N chany_top_in[10]:12 *C 73.140 97.978 + +*CAP +0 chany_top_in[10] 0.0002181098 +1 mux_left_track_21\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[10]:2 3.078869e-05 +3 chany_top_in[10]:3 5.302494e-05 +4 chany_top_in[10]:4 5.683236e-05 +5 chany_top_in[10]:5 0.00167375 +6 chany_top_in[10]:6 0.00167375 +7 chany_top_in[10]:7 0.002348903 +8 chany_top_in[10]:8 0.00304858 +9 chany_top_in[10]:9 0.0006996769 +10 chany_top_in[10]:10 0.0004466535 +11 chany_top_in[10]:11 0.0004466535 +12 chany_top_in[10]:12 0.0002181098 +13 chany_top_in[10]:5 prog_clk[0]:283 7.050103e-05 +14 chany_top_in[10]:5 prog_clk[0]:291 0.0001784153 +15 chany_top_in[10]:5 prog_clk[0]:292 8.822668e-05 +16 chany_top_in[10]:5 prog_clk[0]:332 9.894506e-05 +17 chany_top_in[10]:6 prog_clk[0]:278 7.050103e-05 +18 chany_top_in[10]:6 prog_clk[0]:283 0.0001784153 +19 chany_top_in[10]:6 prog_clk[0]:291 8.822668e-05 +20 chany_top_in[10]:6 prog_clk[0]:331 9.894506e-05 +21 chany_top_in[10]:7 prog_clk[0]:324 1.369701e-05 +22 chany_top_in[10]:10 prog_clk[0]:146 5.423635e-06 +23 chany_top_in[10]:11 prog_clk[0]:80 5.423635e-06 +24 chany_top_in[10]:8 prog_clk[0]:319 1.369701e-05 +25 chany_top_in[10] chany_top_in[8] 1.397301e-05 +26 chany_top_in[10]:7 chany_top_in[8]:8 0.0004874576 +27 chany_top_in[10]:10 chany_top_in[8]:11 9.124976e-06 +28 chany_top_in[10]:9 chany_top_in[8]:9 0.0001426931 +29 chany_top_in[10]:9 chany_top_in[8]:10 3.252668e-05 +30 chany_top_in[10]:12 chany_top_in[8]:13 1.397301e-05 +31 chany_top_in[10]:11 chany_top_in[8]:12 9.124976e-06 +32 chany_top_in[10]:8 chany_top_in[8]:8 0.0001426931 +33 chany_top_in[10]:8 chany_top_in[8]:9 0.0005199843 + +*RES +0 chany_top_in[10] chany_top_in[10]:12 0.003654018 +1 chany_top_in[10]:2 mux_left_track_21\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[10]:3 chany_top_in[10]:2 0.0045 +3 chany_top_in[10]:4 chany_top_in[10]:3 0.0001634615 +4 chany_top_in[10]:5 chany_top_in[10]:4 0.00341 +5 chany_top_in[10]:6 chany_top_in[10]:5 0.005616891 +6 chany_top_in[10]:7 chany_top_in[10]:6 0.00341 +7 chany_top_in[10]:10 chany_top_in[10]:9 0.00341 +8 chany_top_in[10]:9 chany_top_in[10]:8 0.002205475 +9 chany_top_in[10]:12 chany_top_in[10]:11 0.00341 +10 chany_top_in[10]:11 chany_top_in[10]:10 0.000788425 +11 chany_top_in[10]:8 chany_top_in[10]:7 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size2_12_sram[1] 0.002111798 //LENGTH 16.890 LUMPCC 0.0003970519 DR + +*CONN +*I mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.905 77.180 +*I mem_top_track_36\/FTB_25__30:A I *L 0.001746 *C 72.680 72.080 +*I mux_top_track_36\/mux_l2_in_0_:S I *L 0.008363 *C 69.300 83.237 +*N mux_tree_tapbuf_size2_12_sram[1]:3 *C 72.175 83.300 +*N mux_tree_tapbuf_size2_12_sram[1]:4 *C 72.220 83.255 +*N mux_tree_tapbuf_size2_12_sram[1]:5 *C 72.220 80.240 +*N mux_tree_tapbuf_size2_12_sram[1]:6 *C 72.680 80.240 +*N mux_tree_tapbuf_size2_12_sram[1]:7 *C 72.680 72.080 +*N mux_tree_tapbuf_size2_12_sram[1]:8 *C 72.680 72.125 +*N mux_tree_tapbuf_size2_12_sram[1]:9 *C 72.680 77.180 +*N mux_tree_tapbuf_size2_12_sram[1]:10 *C 72.725 77.180 +*N mux_tree_tapbuf_size2_12_sram[1]:11 *C 73.868 77.180 + +*CAP +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_36\/FTB_25__30:A 1e-06 +2 mux_top_track_36\/mux_l2_in_0_:S 0.0002477589 +3 mux_tree_tapbuf_size2_12_sram[1]:3 0.0002477589 +4 mux_tree_tapbuf_size2_12_sram[1]:4 0.0001299195 +5 mux_tree_tapbuf_size2_12_sram[1]:5 0.0001581651 +6 mux_tree_tapbuf_size2_12_sram[1]:6 0.000154842 +7 mux_tree_tapbuf_size2_12_sram[1]:7 3.257307e-05 +8 mux_tree_tapbuf_size2_12_sram[1]:8 0.0002084201 +9 mux_tree_tapbuf_size2_12_sram[1]:9 0.0003630805 +10 mux_tree_tapbuf_size2_12_sram[1]:10 8.511375e-05 +11 mux_tree_tapbuf_size2_12_sram[1]:11 8.511375e-05 +12 mux_tree_tapbuf_size2_12_sram[1]:4 top_left_grid_pin_36_[0]:15 6.055623e-05 +13 mux_tree_tapbuf_size2_12_sram[1]:8 top_left_grid_pin_36_[0]:10 8.630267e-05 +14 mux_tree_tapbuf_size2_12_sram[1]:8 top_left_grid_pin_36_[0]:14 1.417593e-05 +15 mux_tree_tapbuf_size2_12_sram[1]:9 top_left_grid_pin_36_[0]:13 8.630267e-05 +16 mux_tree_tapbuf_size2_12_sram[1]:9 top_left_grid_pin_36_[0]:14 3.749115e-05 +17 mux_tree_tapbuf_size2_12_sram[1]:9 top_left_grid_pin_36_[0]:15 1.417593e-05 +18 mux_tree_tapbuf_size2_12_sram[1]:5 top_left_grid_pin_36_[0]:14 6.055623e-05 +19 mux_tree_tapbuf_size2_12_sram[1]:6 top_left_grid_pin_36_[0]:15 3.749115e-05 + +*RES +0 mem_top_track_36\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_12_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_12_sram[1]:3 mux_top_track_36\/mux_l2_in_0_:S 0.002566964 +2 mux_tree_tapbuf_size2_12_sram[1]:4 mux_tree_tapbuf_size2_12_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_12_sram[1]:7 mem_top_track_36\/FTB_25__30:A 0.152 +4 mux_tree_tapbuf_size2_12_sram[1]:8 mux_tree_tapbuf_size2_12_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_12_sram[1]:10 mux_tree_tapbuf_size2_12_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_12_sram[1]:9 mux_tree_tapbuf_size2_12_sram[1]:8 0.004513393 +7 mux_tree_tapbuf_size2_12_sram[1]:9 mux_tree_tapbuf_size2_12_sram[1]:6 0.002732143 +8 mux_tree_tapbuf_size2_12_sram[1]:11 mux_tree_tapbuf_size2_12_sram[1]:10 0.001020089 +9 mux_tree_tapbuf_size2_12_sram[1]:5 mux_tree_tapbuf_size2_12_sram[1]:4 0.002691964 +10 mux_tree_tapbuf_size2_12_sram[1]:6 mux_tree_tapbuf_size2_12_sram[1]:5 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_3_sram[0] 0.004788327 //LENGTH 37.935 LUMPCC 0.0004350176 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 22.385 53.040 +*I mux_left_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 22.900 50.615 +*I mux_left_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 26.780 36.040 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 25.475 39.100 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 25.200 55.760 +*N mux_tree_tapbuf_size6_3_sram[0]:5 *C 25.163 55.760 +*N mux_tree_tapbuf_size6_3_sram[0]:6 *C 22.125 55.760 +*N mux_tree_tapbuf_size6_3_sram[0]:7 *C 22.080 55.715 +*N mux_tree_tapbuf_size6_3_sram[0]:8 *C 25.513 39.100 +*N mux_tree_tapbuf_size6_3_sram[0]:9 *C 26.680 36.040 +*N mux_tree_tapbuf_size6_3_sram[0]:10 *C 26.680 36.085 +*N mux_tree_tapbuf_size6_3_sram[0]:11 *C 26.680 39.055 +*N mux_tree_tapbuf_size6_3_sram[0]:12 *C 26.680 39.100 +*N mux_tree_tapbuf_size6_3_sram[0]:13 *C 28.475 39.100 +*N mux_tree_tapbuf_size6_3_sram[0]:14 *C 28.520 39.145 +*N mux_tree_tapbuf_size6_3_sram[0]:15 *C 28.520 48.235 +*N mux_tree_tapbuf_size6_3_sram[0]:16 *C 28.475 48.280 +*N mux_tree_tapbuf_size6_3_sram[0]:17 *C 21.665 48.280 +*N mux_tree_tapbuf_size6_3_sram[0]:18 *C 21.620 48.325 +*N mux_tree_tapbuf_size6_3_sram[0]:19 *C 22.900 50.615 +*N mux_tree_tapbuf_size6_3_sram[0]:20 *C 22.900 51.000 +*N mux_tree_tapbuf_size6_3_sram[0]:21 *C 21.665 51.000 +*N mux_tree_tapbuf_size6_3_sram[0]:22 *C 21.620 51.000 +*N mux_tree_tapbuf_size6_3_sram[0]:23 *C 21.620 53.040 +*N mux_tree_tapbuf_size6_3_sram[0]:24 *C 22.080 53.085 +*N mux_tree_tapbuf_size6_3_sram[0]:25 *C 22.080 53.040 +*N mux_tree_tapbuf_size6_3_sram[0]:26 *C 22.385 53.040 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_5\/mux_l1_in_1_:S 1e-06 +2 mux_left_track_5\/mux_l1_in_2_:S 1e-06 +3 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_3_sram[0]:5 0.0001417838 +6 mux_tree_tapbuf_size6_3_sram[0]:6 0.0001417838 +7 mux_tree_tapbuf_size6_3_sram[0]:7 0.0001663096 +8 mux_tree_tapbuf_size6_3_sram[0]:8 8.592021e-05 +9 mux_tree_tapbuf_size6_3_sram[0]:9 3.099786e-05 +10 mux_tree_tapbuf_size6_3_sram[0]:10 0.0001832779 +11 mux_tree_tapbuf_size6_3_sram[0]:11 0.0001832779 +12 mux_tree_tapbuf_size6_3_sram[0]:12 0.0002412273 +13 mux_tree_tapbuf_size6_3_sram[0]:13 0.0001243092 +14 mux_tree_tapbuf_size6_3_sram[0]:14 0.0005230563 +15 mux_tree_tapbuf_size6_3_sram[0]:15 0.0005230563 +16 mux_tree_tapbuf_size6_3_sram[0]:16 0.0004205565 +17 mux_tree_tapbuf_size6_3_sram[0]:17 0.0004205565 +18 mux_tree_tapbuf_size6_3_sram[0]:18 0.0001499284 +19 mux_tree_tapbuf_size6_3_sram[0]:19 5.584907e-05 +20 mux_tree_tapbuf_size6_3_sram[0]:20 0.000156904 +21 mux_tree_tapbuf_size6_3_sram[0]:21 0.0001281511 +22 mux_tree_tapbuf_size6_3_sram[0]:22 0.000284452 +23 mux_tree_tapbuf_size6_3_sram[0]:23 0.000112963 +24 mux_tree_tapbuf_size6_3_sram[0]:24 0.0001731948 +25 mux_tree_tapbuf_size6_3_sram[0]:25 5.244539e-05 +26 mux_tree_tapbuf_size6_3_sram[0]:26 4.830932e-05 +27 mux_tree_tapbuf_size6_3_sram[0]:22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.482678e-06 +28 mux_tree_tapbuf_size6_3_sram[0]:16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.356269e-05 +29 mux_tree_tapbuf_size6_3_sram[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.356269e-05 +30 mux_tree_tapbuf_size6_3_sram[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.482678e-06 +31 mux_tree_tapbuf_size6_3_sram[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001159652 +32 mux_tree_tapbuf_size6_3_sram[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0001159652 +33 mux_tree_tapbuf_size6_3_sram[0]:24 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 2.549824e-05 +34 mux_tree_tapbuf_size6_3_sram[0]:23 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 2.549824e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_3_sram[0]:26 0.152 +1 mux_tree_tapbuf_size6_3_sram[0]:21 mux_tree_tapbuf_size6_3_sram[0]:20 0.001102679 +2 mux_tree_tapbuf_size6_3_sram[0]:22 mux_tree_tapbuf_size6_3_sram[0]:21 0.0045 +3 mux_tree_tapbuf_size6_3_sram[0]:22 mux_tree_tapbuf_size6_3_sram[0]:18 0.002388393 +4 mux_tree_tapbuf_size6_3_sram[0]:19 mux_left_track_5\/mux_l1_in_1_:S 0.152 +5 mux_tree_tapbuf_size6_3_sram[0]:12 mux_tree_tapbuf_size6_3_sram[0]:11 0.0045 +6 mux_tree_tapbuf_size6_3_sram[0]:12 mux_tree_tapbuf_size6_3_sram[0]:8 0.001042411 +7 mux_tree_tapbuf_size6_3_sram[0]:11 mux_tree_tapbuf_size6_3_sram[0]:10 0.002651786 +8 mux_tree_tapbuf_size6_3_sram[0]:9 mux_left_track_5\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size6_3_sram[0]:10 mux_tree_tapbuf_size6_3_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size6_3_sram[0]:13 mux_tree_tapbuf_size6_3_sram[0]:12 0.001602679 +11 mux_tree_tapbuf_size6_3_sram[0]:14 mux_tree_tapbuf_size6_3_sram[0]:13 0.0045 +12 mux_tree_tapbuf_size6_3_sram[0]:16 mux_tree_tapbuf_size6_3_sram[0]:15 0.0045 +13 mux_tree_tapbuf_size6_3_sram[0]:15 mux_tree_tapbuf_size6_3_sram[0]:14 0.008116072 +14 mux_tree_tapbuf_size6_3_sram[0]:17 mux_tree_tapbuf_size6_3_sram[0]:16 0.006080357 +15 mux_tree_tapbuf_size6_3_sram[0]:18 mux_tree_tapbuf_size6_3_sram[0]:17 0.0045 +16 mux_tree_tapbuf_size6_3_sram[0]:6 mux_tree_tapbuf_size6_3_sram[0]:5 0.002712054 +17 mux_tree_tapbuf_size6_3_sram[0]:7 mux_tree_tapbuf_size6_3_sram[0]:6 0.0045 +18 mux_tree_tapbuf_size6_3_sram[0]:5 mux_left_track_5\/mux_l1_in_0_:S 0.152 +19 mux_tree_tapbuf_size6_3_sram[0]:8 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size6_3_sram[0]:25 mux_tree_tapbuf_size6_3_sram[0]:24 0.0045 +21 mux_tree_tapbuf_size6_3_sram[0]:24 mux_tree_tapbuf_size6_3_sram[0]:23 0.0004107143 +22 mux_tree_tapbuf_size6_3_sram[0]:24 mux_tree_tapbuf_size6_3_sram[0]:7 0.002348214 +23 mux_tree_tapbuf_size6_3_sram[0]:26 mux_tree_tapbuf_size6_3_sram[0]:25 0.0001657609 +24 mux_tree_tapbuf_size6_3_sram[0]:20 mux_tree_tapbuf_size6_3_sram[0]:19 0.00034375 +25 mux_tree_tapbuf_size6_3_sram[0]:23 mux_tree_tapbuf_size6_3_sram[0]:22 0.001821429 + +*END + +*D_NET chany_top_in[12] 0.01229877 //LENGTH 99.075 LUMPCC 0.002255625 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 52.900 102.070 +*I mux_left_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 13.245 47.260 +*N chany_top_in[12]:2 *C 13.245 47.260 +*N chany_top_in[12]:3 *C 13.340 47.600 +*N chany_top_in[12]:4 *C 16.515 47.600 +*N chany_top_in[12]:5 *C 16.560 47.555 +*N chany_top_in[12]:6 *C 16.560 46.297 +*N chany_top_in[12]:7 *C 16.568 46.240 +*N chany_top_in[12]:8 *C 38.620 46.240 +*N chany_top_in[12]:9 *C 38.640 46.248 +*N chany_top_in[12]:10 *C 38.640 92.473 +*N chany_top_in[12]:11 *C 38.660 92.480 +*N chany_top_in[12]:12 *C 52.893 92.480 +*N chany_top_in[12]:13 *C 52.900 92.538 + +*CAP +0 chany_top_in[12] 0.0004902834 +1 mux_left_track_17\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[12]:2 5.236172e-05 +3 chany_top_in[12]:3 0.00022348 +4 chany_top_in[12]:4 0.0001976047 +5 chany_top_in[12]:5 9.363994e-05 +6 chany_top_in[12]:6 9.363994e-05 +7 chany_top_in[12]:7 0.0009493355 +8 chany_top_in[12]:8 0.0009493355 +9 chany_top_in[12]:9 0.002541471 +10 chany_top_in[12]:10 0.002541471 +11 chany_top_in[12]:11 0.0007096201 +12 chany_top_in[12]:12 0.0007096201 +13 chany_top_in[12]:13 0.0004902834 +14 chany_top_in[12]:9 chany_top_in[19]:8 0.0002757979 +15 chany_top_in[12]:10 chany_top_in[19]:9 0.0002757979 +16 chany_top_in[12]:11 top_left_grid_pin_34_[0]:28 0.0002852073 +17 chany_top_in[12]:12 top_left_grid_pin_34_[0]:27 0.0002852073 +18 chany_top_in[12]:7 chanx_left_in[13] 0.0005224063 +19 chany_top_in[12]:8 chanx_left_in[13]:6 0.0005224063 +20 chany_top_in[12] mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.440079e-05 +21 chany_top_in[12]:13 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.440079e-05 + +*RES +0 chany_top_in[12] chany_top_in[12]:13 0.008511161 +1 chany_top_in[12]:2 mux_left_track_17\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[12]:4 chany_top_in[12]:3 0.002834822 +3 chany_top_in[12]:5 chany_top_in[12]:4 0.0045 +4 chany_top_in[12]:6 chany_top_in[12]:5 0.001122768 +5 chany_top_in[12]:7 chany_top_in[12]:6 0.00341 +6 chany_top_in[12]:8 chany_top_in[12]:7 0.003454891 +7 chany_top_in[12]:9 chany_top_in[12]:8 0.00341 +8 chany_top_in[12]:11 chany_top_in[12]:10 0.00341 +9 chany_top_in[12]:10 chany_top_in[12]:9 0.007241916 +10 chany_top_in[12]:13 chany_top_in[12]:12 0.00341 +11 chany_top_in[12]:12 chany_top_in[12]:11 0.002229758 +12 chany_top_in[12]:3 chany_top_in[12]:2 0.0003035715 + +*END + +*D_NET top_left_grid_pin_40_[0] 0.01145514 //LENGTH 84.895 LUMPCC 0.001722884 DR + +*CONN +*P top_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 95.200 +*I mux_top_track_36\/mux_l1_in_0_:A1 I *L 0.00198 *C 63.580 83.300 +*I mux_top_track_20\/mux_l1_in_0_:A1 I *L 0.00198 *C 77.280 79.900 +*I mux_top_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 79.295 71.740 +*I mux_top_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 79.295 66.300 +*N top_left_grid_pin_40_[0]:5 *C 79.295 66.300 +*N top_left_grid_pin_40_[0]:6 *C 79.120 66.300 +*N top_left_grid_pin_40_[0]:7 *C 79.120 66.345 +*N top_left_grid_pin_40_[0]:8 *C 79.295 71.740 +*N top_left_grid_pin_40_[0]:9 *C 79.120 71.740 +*N top_left_grid_pin_40_[0]:10 *C 79.120 71.740 +*N top_left_grid_pin_40_[0]:11 *C 79.120 80.535 +*N top_left_grid_pin_40_[0]:12 *C 79.075 80.580 +*N top_left_grid_pin_40_[0]:13 *C 77.318 79.900 +*N top_left_grid_pin_40_[0]:14 *C 77.695 79.900 +*N top_left_grid_pin_40_[0]:15 *C 77.740 79.945 +*N top_left_grid_pin_40_[0]:16 *C 77.740 80.535 +*N top_left_grid_pin_40_[0]:17 *C 77.740 80.580 +*N top_left_grid_pin_40_[0]:18 *C 77.740 80.920 +*N top_left_grid_pin_40_[0]:19 *C 63.480 83.300 +*N top_left_grid_pin_40_[0]:20 *C 63.480 83.255 +*N top_left_grid_pin_40_[0]:21 *C 63.480 80.965 +*N top_left_grid_pin_40_[0]:22 *C 63.480 80.920 +*N top_left_grid_pin_40_[0]:23 *C 37.305 80.920 +*N top_left_grid_pin_40_[0]:24 *C 37.260 80.965 +*N top_left_grid_pin_40_[0]:25 *C 37.260 95.142 +*N top_left_grid_pin_40_[0]:26 *C 37.253 95.200 + +*CAP +0 top_left_grid_pin_40_[0] 0.0005539281 +1 mux_top_track_36\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_20\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_1_:A0 1e-06 +4 mux_top_track_4\/mux_l1_in_1_:A0 1e-06 +5 top_left_grid_pin_40_[0]:5 6.061628e-05 +6 top_left_grid_pin_40_[0]:6 5.672114e-05 +7 top_left_grid_pin_40_[0]:7 0.0002995303 +8 top_left_grid_pin_40_[0]:8 5.403659e-05 +9 top_left_grid_pin_40_[0]:9 5.272103e-05 +10 top_left_grid_pin_40_[0]:10 0.0008700737 +11 top_left_grid_pin_40_[0]:11 0.0005384858 +12 top_left_grid_pin_40_[0]:12 9.467819e-05 +13 top_left_grid_pin_40_[0]:13 4.225828e-05 +14 top_left_grid_pin_40_[0]:14 4.225828e-05 +15 top_left_grid_pin_40_[0]:15 2.011482e-05 +16 top_left_grid_pin_40_[0]:16 2.011482e-05 +17 top_left_grid_pin_40_[0]:17 0.0001229067 +18 top_left_grid_pin_40_[0]:18 0.0009283823 +19 top_left_grid_pin_40_[0]:19 3.402982e-05 +20 top_left_grid_pin_40_[0]:20 0.0001412471 +21 top_left_grid_pin_40_[0]:21 0.0001412471 +22 top_left_grid_pin_40_[0]:22 0.002349065 +23 top_left_grid_pin_40_[0]:23 0.001414881 +24 top_left_grid_pin_40_[0]:24 0.0006685161 +25 top_left_grid_pin_40_[0]:25 0.0006685161 +26 top_left_grid_pin_40_[0]:26 0.0005539281 +27 top_left_grid_pin_40_[0]:13 chanx_left_in[10]:3 6.74664e-08 +28 top_left_grid_pin_40_[0]:14 chanx_left_in[10]:2 6.74664e-08 +29 top_left_grid_pin_40_[0]:15 chanx_left_in[10]:5 8.003967e-06 +30 top_left_grid_pin_40_[0]:16 chanx_left_in[10]:4 8.003967e-06 +31 top_left_grid_pin_40_[0]:23 chanx_left_in[10]:13 0.0006288396 +32 top_left_grid_pin_40_[0]:22 chanx_left_in[10]:3 3.451919e-05 +33 top_left_grid_pin_40_[0]:22 chanx_left_in[10]:9 9.816769e-06 +34 top_left_grid_pin_40_[0]:22 chanx_left_in[10]:12 0.0006288396 +35 top_left_grid_pin_40_[0]:18 chanx_left_in[10]:2 3.451919e-05 +36 top_left_grid_pin_40_[0]:18 chanx_left_in[10]:8 9.816769e-06 +37 top_left_grid_pin_40_[0]:24 mux_tree_tapbuf_size2_9_sram[0]:5 7.922788e-05 +38 top_left_grid_pin_40_[0]:24 mux_tree_tapbuf_size2_9_sram[0]:9 5.972298e-05 +39 top_left_grid_pin_40_[0]:25 mux_tree_tapbuf_size2_9_sram[0]:8 7.922788e-05 +40 top_left_grid_pin_40_[0]:25 mux_tree_tapbuf_size2_9_sram[0]:10 5.972298e-05 +41 top_left_grid_pin_40_[0]:15 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.707621e-05 +42 top_left_grid_pin_40_[0]:17 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.416794e-05 +43 top_left_grid_pin_40_[0]:16 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.707621e-05 +44 top_left_grid_pin_40_[0]:12 mux_top_track_20/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.416794e-05 + +*RES +0 top_left_grid_pin_40_[0] top_left_grid_pin_40_[0]:26 0.001175392 +1 top_left_grid_pin_40_[0]:13 mux_top_track_20\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_40_[0]:14 top_left_grid_pin_40_[0]:13 0.0003370536 +3 top_left_grid_pin_40_[0]:15 top_left_grid_pin_40_[0]:14 0.0045 +4 top_left_grid_pin_40_[0]:17 top_left_grid_pin_40_[0]:16 0.0045 +5 top_left_grid_pin_40_[0]:17 top_left_grid_pin_40_[0]:12 0.001191964 +6 top_left_grid_pin_40_[0]:16 top_left_grid_pin_40_[0]:15 0.0005267858 +7 top_left_grid_pin_40_[0]:12 top_left_grid_pin_40_[0]:11 0.0045 +8 top_left_grid_pin_40_[0]:11 top_left_grid_pin_40_[0]:10 0.007852679 +9 top_left_grid_pin_40_[0]:23 top_left_grid_pin_40_[0]:22 0.02337054 +10 top_left_grid_pin_40_[0]:24 top_left_grid_pin_40_[0]:23 0.0045 +11 top_left_grid_pin_40_[0]:25 top_left_grid_pin_40_[0]:24 0.01265848 +12 top_left_grid_pin_40_[0]:26 top_left_grid_pin_40_[0]:25 0.00341 +13 top_left_grid_pin_40_[0]:6 top_left_grid_pin_40_[0]:5 9.51087e-05 +14 top_left_grid_pin_40_[0]:7 top_left_grid_pin_40_[0]:6 0.0045 +15 top_left_grid_pin_40_[0]:5 mux_top_track_4\/mux_l1_in_1_:A0 0.152 +16 top_left_grid_pin_40_[0]:22 top_left_grid_pin_40_[0]:21 0.0045 +17 top_left_grid_pin_40_[0]:22 top_left_grid_pin_40_[0]:18 0.01273214 +18 top_left_grid_pin_40_[0]:21 top_left_grid_pin_40_[0]:20 0.002044643 +19 top_left_grid_pin_40_[0]:19 mux_top_track_36\/mux_l1_in_0_:A1 0.152 +20 top_left_grid_pin_40_[0]:20 top_left_grid_pin_40_[0]:19 0.0045 +21 top_left_grid_pin_40_[0]:9 top_left_grid_pin_40_[0]:8 9.51087e-05 +22 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:9 0.0045 +23 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:7 0.004816965 +24 top_left_grid_pin_40_[0]:8 mux_top_track_0\/mux_l1_in_1_:A0 0.152 +25 top_left_grid_pin_40_[0]:18 top_left_grid_pin_40_[0]:17 0.0003035715 + +*END + +*D_NET chanx_left_in[3] 0.01093237 //LENGTH 76.158 LUMPCC 0.003397944 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 53.040 +*I mux_top_track_34\/mux_l1_in_0_:A0 I *L 0.001631 *C 54.915 71.740 +*N chanx_left_in[3]:2 *C 54.740 72.080 +*N chanx_left_in[3]:3 *C 55.200 72.080 +*N chanx_left_in[3]:4 *C 55.200 71.775 +*N chanx_left_in[3]:5 *C 54.943 71.763 +*N chanx_left_in[3]:6 *C 54.740 71.740 +*N chanx_left_in[3]:7 *C 51.980 71.740 +*N chanx_left_in[3]:8 *C 51.980 71.400 +*N chanx_left_in[3]:9 *C 37.765 71.400 +*N chanx_left_in[3]:10 *C 37.720 71.355 +*N chanx_left_in[3]:11 *C 37.720 67.377 +*N chanx_left_in[3]:12 *C 37.712 67.320 +*N chanx_left_in[3]:13 *C 34.060 67.320 +*N chanx_left_in[3]:14 *C 34.040 67.312 +*N chanx_left_in[3]:15 *C 34.040 53.047 +*N chanx_left_in[3]:16 *C 34.020 53.040 + +*CAP +0 chanx_left_in[3] 0.001012133 +1 mux_top_track_34\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[3]:2 5.48809e-05 +3 chanx_left_in[3]:3 6.956531e-05 +4 chanx_left_in[3]:4 3.581028e-05 +5 chanx_left_in[3]:5 2.874453e-05 +6 chanx_left_in[3]:6 0.0001883866 +7 chanx_left_in[3]:7 0.0002081408 +8 chanx_left_in[3]:8 0.0009862432 +9 chanx_left_in[3]:9 0.0009588704 +10 chanx_left_in[3]:10 0.0002435565 +11 chanx_left_in[3]:11 0.0002435565 +12 chanx_left_in[3]:12 0.0002769867 +13 chanx_left_in[3]:13 0.0002769867 +14 chanx_left_in[3]:14 0.0009687161 +15 chanx_left_in[3]:15 0.0009687161 +16 chanx_left_in[3]:16 0.001012133 +17 chanx_left_in[3] chanx_left_in[0] 0.000754914 +18 chanx_left_in[3]:16 chanx_left_in[0]:12 0.000754914 +19 chanx_left_in[3] chanx_left_in[1]:11 0.0002296366 +20 chanx_left_in[3]:12 chanx_left_in[1]:6 8.081004e-05 +21 chanx_left_in[3]:13 chanx_left_in[1]:7 8.081004e-05 +22 chanx_left_in[3]:16 chanx_left_in[1]:10 0.0002296366 +23 chanx_left_in[3] left_top_grid_pin_42_[0]:19 0.0005817451 +24 chanx_left_in[3]:16 left_top_grid_pin_42_[0]:18 0.0005817451 +25 chanx_left_in[3]:9 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 5.186618e-05 +26 chanx_left_in[3]:8 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 5.186618e-05 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:16 0.0051371 +1 chanx_left_in[3]:9 chanx_left_in[3]:8 0.01269196 +2 chanx_left_in[3]:10 chanx_left_in[3]:9 0.0045 +3 chanx_left_in[3]:11 chanx_left_in[3]:10 0.003551339 +4 chanx_left_in[3]:12 chanx_left_in[3]:11 0.00341 +5 chanx_left_in[3]:13 chanx_left_in[3]:12 0.000572225 +6 chanx_left_in[3]:14 chanx_left_in[3]:13 0.00341 +7 chanx_left_in[3]:16 chanx_left_in[3]:15 0.00341 +8 chanx_left_in[3]:15 chanx_left_in[3]:14 0.00223485 +9 chanx_left_in[3]:5 mux_top_track_34\/mux_l1_in_0_:A0 0.152 +10 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0001739865 +11 chanx_left_in[3]:8 chanx_left_in[3]:7 0.0003035715 +12 chanx_left_in[3]:7 chanx_left_in[3]:6 0.002464286 +13 chanx_left_in[3]:6 chanx_left_in[3]:5 0.0001808036 +14 chanx_left_in[3]:3 chanx_left_in[3]:2 0.0004107142 +15 chanx_left_in[3]:4 chanx_left_in[3]:3 0.0002723215 + +*END + +*D_NET chanx_left_in[9] 0.01111717 //LENGTH 75.135 LUMPCC 0.004303562 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.298 72.080 +*I mux_top_track_22\/mux_l1_in_0_:A0 I *L 0.001631 *C 60.895 86.020 +*N chanx_left_in[9]:2 *C 60.858 86.020 +*N chanx_left_in[9]:3 *C 60.305 86.020 +*N chanx_left_in[9]:4 *C 60.260 85.975 +*N chanx_left_in[9]:5 *C 60.260 74.178 +*N chanx_left_in[9]:6 *C 60.253 74.120 +*N chanx_left_in[9]:7 *C 51.215 74.120 +*N chanx_left_in[9]:8 *C 1.387 74.120 +*N chanx_left_in[9]:9 *C 1.380 74.062 +*N chanx_left_in[9]:10 *C 1.380 72.138 +*N chanx_left_in[9]:11 *C 1.380 72.080 + +*CAP +0 chanx_left_in[9] 2.956095e-05 +1 mux_top_track_22\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[9]:2 5.649865e-05 +3 chanx_left_in[9]:3 5.649865e-05 +4 chanx_left_in[9]:4 0.0004764184 +5 chanx_left_in[9]:5 0.0004764184 +6 chanx_left_in[9]:6 0.0004157735 +7 chanx_left_in[9]:7 0.002727129 +8 chanx_left_in[9]:8 0.002311355 +9 chanx_left_in[9]:9 0.000116699 +10 chanx_left_in[9]:10 0.000116699 +11 chanx_left_in[9]:11 2.956095e-05 +12 chanx_left_in[9]:6 chany_top_in[1]:12 0.0001081592 +13 chanx_left_in[9]:8 chany_top_in[1]:6 5.557325e-06 +14 chanx_left_in[9]:8 chany_top_in[1]:11 0.0002870231 +15 chanx_left_in[9]:7 chany_top_in[1]:7 5.557325e-06 +16 chanx_left_in[9]:7 chany_top_in[1]:11 0.0001081592 +17 chanx_left_in[9]:7 chany_top_in[1]:12 0.0002870231 +18 chanx_left_in[9]:6 top_left_grid_pin_38_[0]:17 0.0001783114 +19 chanx_left_in[9]:8 top_left_grid_pin_38_[0]:18 0.0001135435 +20 chanx_left_in[9]:7 top_left_grid_pin_38_[0]:17 0.0001135435 +21 chanx_left_in[9]:7 top_left_grid_pin_38_[0]:18 0.0001783114 +22 chanx_left_in[9]:2 top_left_grid_pin_41_[0]:15 6.979258e-06 +23 chanx_left_in[9]:3 top_left_grid_pin_41_[0]:16 6.979258e-06 +24 chanx_left_in[9]:4 top_left_grid_pin_41_[0]:17 0.0002919972 +25 chanx_left_in[9]:4 top_left_grid_pin_41_[0]:18 2.237331e-05 +26 chanx_left_in[9]:5 top_left_grid_pin_41_[0]:14 0.0002919972 +27 chanx_left_in[9]:5 top_left_grid_pin_41_[0]:17 2.237331e-05 +28 chanx_left_in[9]:8 left_top_grid_pin_47_[0]:23 0.001137837 +29 chanx_left_in[9]:7 left_top_grid_pin_47_[0]:22 0.001137837 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:11 2.35e-05 +1 chanx_left_in[9]:2 mux_top_track_22\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[9]:3 chanx_left_in[9]:2 0.0004933036 +3 chanx_left_in[9]:4 chanx_left_in[9]:3 0.0045 +4 chanx_left_in[9]:5 chanx_left_in[9]:4 0.01053348 +5 chanx_left_in[9]:6 chanx_left_in[9]:5 0.00341 +6 chanx_left_in[9]:9 chanx_left_in[9]:8 0.00341 +7 chanx_left_in[9]:8 chanx_left_in[9]:7 0.007806308 +8 chanx_left_in[9]:10 chanx_left_in[9]:9 0.00171875 +9 chanx_left_in[9]:11 chanx_left_in[9]:10 0.00341 +10 chanx_left_in[9]:7 chanx_left_in[9]:6 0.001415875 + +*END + +*D_NET chanx_left_in[13] 0.007587792 //LENGTH 50.580 LUMPCC 0.00358718 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 44.880 +*I mux_top_track_14\/mux_l1_in_0_:A0 I *L 0.001631 *C 42.495 53.380 +*N chanx_left_in[13]:2 *C 42.458 53.380 +*N chanx_left_in[13]:3 *C 40.985 53.380 +*N chanx_left_in[13]:4 *C 40.940 53.335 +*N chanx_left_in[13]:5 *C 40.940 44.938 +*N chanx_left_in[13]:6 *C 40.933 44.880 + +*CAP +0 chanx_left_in[13] 0.001348285 +1 mux_top_track_14\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[13]:2 0.0001529671 +3 chanx_left_in[13]:3 0.0001529671 +4 chanx_left_in[13]:4 0.0004985536 +5 chanx_left_in[13]:5 0.0004985536 +6 chanx_left_in[13]:6 0.001348285 +7 chanx_left_in[13] chany_top_in[5]:6 5.103622e-06 +8 chanx_left_in[13] chany_top_in[5]:10 7.420437e-06 +9 chanx_left_in[13] chany_top_in[5]:18 0.0003013576 +10 chanx_left_in[13]:6 chany_top_in[5]:7 5.103622e-06 +11 chanx_left_in[13]:6 chany_top_in[5]:11 7.420437e-06 +12 chanx_left_in[13]:6 chany_top_in[5]:19 0.0003013576 +13 chanx_left_in[13] chany_top_in[12]:7 0.0005224063 +14 chanx_left_in[13]:6 chany_top_in[12]:8 0.0005224063 +15 chanx_left_in[13] mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004295577 +16 chanx_left_in[13]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004295577 +17 chanx_left_in[13] chanx_left_out[17] 9.323312e-06 +18 chanx_left_in[13] chanx_left_out[17]:3 0.0005184212 +19 chanx_left_in[13]:6 chanx_left_out[17]:4 0.0005184212 +20 chanx_left_in[13]:6 chanx_left_out[17]:2 9.323312e-06 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:6 0.006220058 +1 chanx_left_in[13]:2 mux_top_track_14\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[13]:3 chanx_left_in[13]:2 0.001314732 +3 chanx_left_in[13]:4 chanx_left_in[13]:3 0.0045 +4 chanx_left_in[13]:5 chanx_left_in[13]:4 0.007497768 +5 chanx_left_in[13]:6 chanx_left_in[13]:5 0.00341 + +*END + +*D_NET chanx_left_in[18] 0.01230498 //LENGTH 125.510 LUMPCC 0 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 5.440 +*I mux_top_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 82.630 47.940 +*N chanx_left_in[18]:2 *C 82.630 47.940 +*N chanx_left_in[18]:3 *C 82.800 47.940 +*N chanx_left_in[18]:4 *C 82.800 47.895 +*N chanx_left_in[18]:5 *C 82.800 9.225 +*N chanx_left_in[18]:6 *C 82.755 9.180 +*N chanx_left_in[18]:7 *C 54.900 9.180 +*N chanx_left_in[18]:8 *C 5.105 9.180 +*N chanx_left_in[18]:9 *C 5.060 9.135 +*N chanx_left_in[18]:10 *C 5.060 5.498 +*N chanx_left_in[18]:11 *C 5.053 5.440 + +*CAP +0 chanx_left_in[18] 0.0002893817 +1 mux_top_track_4\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[18]:2 5.238816e-05 +3 chanx_left_in[18]:3 5.713964e-05 +4 chanx_left_in[18]:4 0.001758683 +5 chanx_left_in[18]:5 0.001758683 +6 chanx_left_in[18]:6 0.00136666 +7 chanx_left_in[18]:7 0.003854474 +8 chanx_left_in[18]:8 0.002487814 +9 chanx_left_in[18]:9 0.0001946894 +10 chanx_left_in[18]:10 0.0001946894 +11 chanx_left_in[18]:11 0.0002893817 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:11 0.0005988583 +1 chanx_left_in[18]:2 mux_top_track_4\/mux_l1_in_2_:A0 0.152 +2 chanx_left_in[18]:3 chanx_left_in[18]:2 9.239131e-05 +3 chanx_left_in[18]:4 chanx_left_in[18]:3 0.0045 +4 chanx_left_in[18]:6 chanx_left_in[18]:5 0.0045 +5 chanx_left_in[18]:5 chanx_left_in[18]:4 0.03452679 +6 chanx_left_in[18]:8 chanx_left_in[18]:7 0.04445983 +7 chanx_left_in[18]:9 chanx_left_in[18]:8 0.0045 +8 chanx_left_in[18]:10 chanx_left_in[18]:9 0.003247768 +9 chanx_left_in[18]:11 chanx_left_in[18]:10 0.00341 +10 chanx_left_in[18]:7 chanx_left_in[18]:6 0.02487054 + +*END + +*D_NET left_top_grid_pin_46_[0] 0.006819389 //LENGTH 48.055 LUMPCC 0.001454551 DR + +*CONN +*P left_top_grid_pin_46_[0] I *L 0.29796 *C 2.300 74.870 +*I mux_left_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 13.055 49.640 +*I mux_left_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 21.795 49.640 +*I mux_left_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 13.630 48.280 +*N left_top_grid_pin_46_[0]:4 *C 13.630 48.280 +*N left_top_grid_pin_46_[0]:5 *C 13.340 48.280 +*N left_top_grid_pin_46_[0]:6 *C 13.340 48.325 +*N left_top_grid_pin_46_[0]:7 *C 21.758 49.640 +*N left_top_grid_pin_46_[0]:8 *C 13.055 49.640 +*N left_top_grid_pin_46_[0]:9 *C 13.385 49.640 +*N left_top_grid_pin_46_[0]:10 *C 13.340 49.595 +*N left_top_grid_pin_46_[0]:11 *C 12.880 49.640 +*N left_top_grid_pin_46_[0]:12 *C 12.880 59.103 +*N left_top_grid_pin_46_[0]:13 *C 12.873 59.160 +*N left_top_grid_pin_46_[0]:14 *C 2.308 59.160 +*N left_top_grid_pin_46_[0]:15 *C 2.300 59.218 + +*CAP +0 left_top_grid_pin_46_[0] 0.0007467011 +1 mux_left_track_1\/mux_l1_in_1_:A0 1e-06 +2 mux_left_track_5\/mux_l1_in_1_:A0 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:A0 1e-06 +4 left_top_grid_pin_46_[0]:4 5.096128e-05 +5 left_top_grid_pin_46_[0]:5 5.217779e-05 +6 left_top_grid_pin_46_[0]:6 8.977199e-05 +7 left_top_grid_pin_46_[0]:7 0.0005944166 +8 left_top_grid_pin_46_[0]:8 5.037275e-05 +9 left_top_grid_pin_46_[0]:9 0.0006165251 +10 left_top_grid_pin_46_[0]:10 0.0001218485 +11 left_top_grid_pin_46_[0]:11 0.0005797488 +12 left_top_grid_pin_46_[0]:12 0.0005476723 +13 left_top_grid_pin_46_[0]:13 0.0005824704 +14 left_top_grid_pin_46_[0]:14 0.0005824704 +15 left_top_grid_pin_46_[0]:15 0.0007467011 +16 left_top_grid_pin_46_[0]:13 chanx_left_in[6]:6 0.0005767798 +17 left_top_grid_pin_46_[0]:14 chanx_left_in[6]:7 0.0005767798 +18 left_top_grid_pin_46_[0] mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 0.0001504954 +19 left_top_grid_pin_46_[0]:15 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 0.0001504954 + +*RES +0 left_top_grid_pin_46_[0] left_top_grid_pin_46_[0]:15 0.01397545 +1 left_top_grid_pin_46_[0]:12 left_top_grid_pin_46_[0]:11 0.008448661 +2 left_top_grid_pin_46_[0]:13 left_top_grid_pin_46_[0]:12 0.00341 +3 left_top_grid_pin_46_[0]:15 left_top_grid_pin_46_[0]:14 0.00341 +4 left_top_grid_pin_46_[0]:14 left_top_grid_pin_46_[0]:13 0.001655183 +5 left_top_grid_pin_46_[0]:9 left_top_grid_pin_46_[0]:8 0.0001793478 +6 left_top_grid_pin_46_[0]:9 left_top_grid_pin_46_[0]:7 0.007475447 +7 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:9 0.0045 +8 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:6 0.001133929 +9 left_top_grid_pin_46_[0]:7 mux_left_track_5\/mux_l1_in_1_:A0 0.152 +10 left_top_grid_pin_46_[0]:5 left_top_grid_pin_46_[0]:4 0.0001032609 +11 left_top_grid_pin_46_[0]:6 left_top_grid_pin_46_[0]:5 0.0045 +12 left_top_grid_pin_46_[0]:4 mux_left_track_17\/mux_l1_in_0_:A0 0.152 +13 left_top_grid_pin_46_[0]:8 mux_left_track_1\/mux_l1_in_1_:A0 0.152 +14 left_top_grid_pin_46_[0]:11 left_top_grid_pin_46_[0]:10 0.0004107143 + +*END + +*D_NET left_top_grid_pin_49_[0] 0.01334891 //LENGTH 88.970 LUMPCC 0.003111931 DR + +*CONN +*P left_top_grid_pin_49_[0] I *L 0.29796 *C 10.580 74.835 +*I mux_left_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 24.840 63.580 +*I mux_left_track_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 30.265 58.140 +*I mux_left_track_23\/mux_l1_in_0_:A0 I *L 0.001631 *C 41.685 31.620 +*N left_top_grid_pin_49_[0]:4 *C 41.648 31.620 +*N left_top_grid_pin_49_[0]:5 *C 40.065 31.620 +*N left_top_grid_pin_49_[0]:6 *C 40.020 31.620 +*N left_top_grid_pin_49_[0]:7 *C 40.020 31.960 +*N left_top_grid_pin_49_[0]:8 *C 40.013 31.960 +*N left_top_grid_pin_49_[0]:9 *C 35.900 31.960 +*N left_top_grid_pin_49_[0]:10 *C 35.880 31.968 +*N left_top_grid_pin_49_[0]:11 *C 35.880 63.233 +*N left_top_grid_pin_49_[0]:12 *C 35.860 63.240 +*N left_top_grid_pin_49_[0]:13 *C 24.840 63.240 +*N left_top_grid_pin_49_[0]:14 *C 30.228 58.140 +*N left_top_grid_pin_49_[0]:15 *C 24.885 58.140 +*N left_top_grid_pin_49_[0]:16 *C 24.840 58.185 +*N left_top_grid_pin_49_[0]:17 *C 24.840 63.580 +*N left_top_grid_pin_49_[0]:18 *C 24.840 63.535 +*N left_top_grid_pin_49_[0]:19 *C 24.840 63.920 +*N left_top_grid_pin_49_[0]:20 *C 24.840 63.913 +*N left_top_grid_pin_49_[0]:21 *C 16.108 63.920 +*N left_top_grid_pin_49_[0]:22 *C 16.100 63.978 +*N left_top_grid_pin_49_[0]:23 *C 16.100 71.343 +*N left_top_grid_pin_49_[0]:24 *C 16.093 71.400 +*N left_top_grid_pin_49_[0]:25 *C 10.588 71.400 +*N left_top_grid_pin_49_[0]:26 *C 10.580 71.458 + +*CAP +0 left_top_grid_pin_49_[0] 0.0002154663 +1 mux_left_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_7\/mux_l2_in_1_:A1 1e-06 +3 mux_left_track_23\/mux_l1_in_0_:A0 1e-06 +4 left_top_grid_pin_49_[0]:4 0.0001332397 +5 left_top_grid_pin_49_[0]:5 0.0001332397 +6 left_top_grid_pin_49_[0]:6 4.941251e-05 +7 left_top_grid_pin_49_[0]:7 5.323427e-05 +8 left_top_grid_pin_49_[0]:8 0.0001638174 +9 left_top_grid_pin_49_[0]:9 0.0001638174 +10 left_top_grid_pin_49_[0]:10 0.001923404 +11 left_top_grid_pin_49_[0]:11 0.001923404 +12 left_top_grid_pin_49_[0]:12 0.0005386723 +13 left_top_grid_pin_49_[0]:13 0.0005894562 +14 left_top_grid_pin_49_[0]:14 0.0003845911 +15 left_top_grid_pin_49_[0]:15 0.0003845911 +16 left_top_grid_pin_49_[0]:16 0.0003168693 +17 left_top_grid_pin_49_[0]:17 3.874762e-05 +18 left_top_grid_pin_49_[0]:18 0.0003381832 +19 left_top_grid_pin_49_[0]:19 6.057866e-05 +20 left_top_grid_pin_49_[0]:20 0.0004766642 +21 left_top_grid_pin_49_[0]:21 0.0004258803 +22 left_top_grid_pin_49_[0]:22 0.0005516447 +23 left_top_grid_pin_49_[0]:23 0.0005516447 +24 left_top_grid_pin_49_[0]:24 0.0003009775 +25 left_top_grid_pin_49_[0]:25 0.0003009775 +26 left_top_grid_pin_49_[0]:26 0.0002154663 +27 left_top_grid_pin_49_[0]:12 prog_clk[0]:388 5.411914e-07 +28 left_top_grid_pin_49_[0]:12 prog_clk[0]:393 2.432337e-06 +29 left_top_grid_pin_49_[0]:9 prog_clk[0]:291 0.0002409329 +30 left_top_grid_pin_49_[0]:9 prog_clk[0]:292 1.059139e-05 +31 left_top_grid_pin_49_[0]:7 prog_clk[0]:281 2.548962e-07 +32 left_top_grid_pin_49_[0]:8 prog_clk[0]:283 0.0002409329 +33 left_top_grid_pin_49_[0]:8 prog_clk[0]:291 1.059139e-05 +34 left_top_grid_pin_49_[0]:6 prog_clk[0]:282 2.548962e-07 +35 left_top_grid_pin_49_[0]:24 prog_clk[0]:462 0.0001861332 +36 left_top_grid_pin_49_[0]:24 prog_clk[0]:463 0.0001369709 +37 left_top_grid_pin_49_[0]:25 prog_clk[0]:402 0.0001861332 +38 left_top_grid_pin_49_[0]:25 prog_clk[0]:462 0.0001369709 +39 left_top_grid_pin_49_[0]:15 prog_clk[0]:383 2.412133e-05 +40 left_top_grid_pin_49_[0]:14 prog_clk[0]:261 2.412133e-05 +41 left_top_grid_pin_49_[0]:13 prog_clk[0]:393 5.411914e-07 +42 left_top_grid_pin_49_[0]:13 prog_clk[0]:394 2.432337e-06 +43 left_top_grid_pin_49_[0]:12 chany_top_in[13]:6 0.0002102551 +44 left_top_grid_pin_49_[0]:21 chany_top_in[13]:5 0.0005028191 +45 left_top_grid_pin_49_[0]:20 chany_top_in[13]:6 0.0005028191 +46 left_top_grid_pin_49_[0]:13 chany_top_in[13]:5 0.0002102551 +47 left_top_grid_pin_49_[0]:12 mux_tree_tapbuf_size5_3_sram[0]:12 0.0002409128 +48 left_top_grid_pin_49_[0]:13 mux_tree_tapbuf_size5_3_sram[0]:13 0.0002409128 + +*RES +0 left_top_grid_pin_49_[0] left_top_grid_pin_49_[0]:26 0.003015625 +1 left_top_grid_pin_49_[0]:12 left_top_grid_pin_49_[0]:11 0.00341 +2 left_top_grid_pin_49_[0]:11 left_top_grid_pin_49_[0]:10 0.004898183 +3 left_top_grid_pin_49_[0]:9 left_top_grid_pin_49_[0]:8 0.0006442916 +4 left_top_grid_pin_49_[0]:10 left_top_grid_pin_49_[0]:9 0.00341 +5 left_top_grid_pin_49_[0]:7 left_top_grid_pin_49_[0]:6 0.0001634615 +6 left_top_grid_pin_49_[0]:8 left_top_grid_pin_49_[0]:7 0.00341 +7 left_top_grid_pin_49_[0]:5 left_top_grid_pin_49_[0]:4 0.001412946 +8 left_top_grid_pin_49_[0]:6 left_top_grid_pin_49_[0]:5 0.0045 +9 left_top_grid_pin_49_[0]:4 mux_left_track_23\/mux_l1_in_0_:A0 0.152 +10 left_top_grid_pin_49_[0]:22 left_top_grid_pin_49_[0]:21 0.00341 +11 left_top_grid_pin_49_[0]:21 left_top_grid_pin_49_[0]:20 0.001368092 +12 left_top_grid_pin_49_[0]:23 left_top_grid_pin_49_[0]:22 0.006575893 +13 left_top_grid_pin_49_[0]:24 left_top_grid_pin_49_[0]:23 0.00341 +14 left_top_grid_pin_49_[0]:26 left_top_grid_pin_49_[0]:25 0.00341 +15 left_top_grid_pin_49_[0]:25 left_top_grid_pin_49_[0]:24 0.0008624499 +16 left_top_grid_pin_49_[0]:15 left_top_grid_pin_49_[0]:14 0.004770089 +17 left_top_grid_pin_49_[0]:16 left_top_grid_pin_49_[0]:15 0.0045 +18 left_top_grid_pin_49_[0]:14 mux_left_track_7\/mux_l2_in_1_:A1 0.152 +19 left_top_grid_pin_49_[0]:19 left_top_grid_pin_49_[0]:18 0.0001850962 +20 left_top_grid_pin_49_[0]:20 left_top_grid_pin_49_[0]:19 0.00341 +21 left_top_grid_pin_49_[0]:20 left_top_grid_pin_49_[0]:13 0.0001053583 +22 left_top_grid_pin_49_[0]:17 mux_left_track_3\/mux_l2_in_1_:A1 0.152 +23 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:17 0.0045 +24 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:16 0.004776786 +25 left_top_grid_pin_49_[0]:13 left_top_grid_pin_49_[0]:12 0.001726467 + +*END + +*D_NET chany_top_out[8] 0.002254676 //LENGTH 16.855 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 57.960 96.560 +*P chany_top_out[8] O *L 0.7423 *C 68.540 102.035 +*N chany_top_out[8]:2 *C 68.540 100.005 +*N chany_top_out[8]:3 *C 68.495 99.960 +*N chany_top_out[8]:4 *C 58.005 99.960 +*N chany_top_out[8]:5 *C 57.960 99.915 +*N chany_top_out[8]:6 *C 57.960 96.605 +*N chany_top_out[8]:7 *C 57.960 96.560 + +*CAP +0 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[8] 0.0001321577 +2 chany_top_out[8]:2 0.0001321577 +3 chany_top_out[8]:3 0.0007235361 +4 chany_top_out[8]:4 0.0007235361 +5 chany_top_out[8]:5 0.0002523202 +6 chany_top_out[8]:6 0.0002523202 +7 chany_top_out[8]:7 3.764821e-05 + +*RES +0 mux_top_track_16\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[8]:7 0.152 +1 chany_top_out[8]:3 chany_top_out[8]:2 0.0045 +2 chany_top_out[8]:2 chany_top_out[8] 0.0018125 +3 chany_top_out[8]:4 chany_top_out[8]:3 0.009366071 +4 chany_top_out[8]:5 chany_top_out[8]:4 0.0045 +5 chany_top_out[8]:7 chany_top_out[8]:6 0.0045 +6 chany_top_out[8]:6 chany_top_out[8]:5 0.002955357 + +*END + +*D_NET chany_top_out[13] 0.0008180392 //LENGTH 6.550 LUMPCC 0 DR + +*CONN +*I mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 61.180 99.280 +*P chany_top_out[13] O *L 0.7423 *C 64.400 102.035 +*N chany_top_out[13]:2 *C 64.400 99.280 +*N chany_top_out[13]:3 *C 63.480 99.280 +*N chany_top_out[13]:4 *C 63.435 99.280 +*N chany_top_out[13]:5 *C 61.218 99.280 + +*CAP +0 mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[13] 0.0001681821 +2 chany_top_out[13]:2 0.0002204552 +3 chany_top_out[13]:3 8.105571e-05 +4 chany_top_out[13]:4 0.0001736731 +5 chany_top_out[13]:5 0.0001736731 + +*RES +0 mux_top_track_26\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[13]:5 0.152 +1 chany_top_out[13]:4 chany_top_out[13]:3 0.0045 +2 chany_top_out[13]:3 chany_top_out[13]:2 0.0008214285 +3 chany_top_out[13]:5 chany_top_out[13]:4 0.001979911 +4 chany_top_out[13]:2 chany_top_out[13] 0.002459822 + +*END + +*D_NET chanx_left_out[1] 0.0009305689 //LENGTH 8.060 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 69.700 +*P chanx_left_out[1] O *L 0.7423 *C 1.230 64.600 +*N chanx_left_out[1]:2 *C 3.673 64.600 +*N chanx_left_out[1]:3 *C 3.680 64.657 +*N chanx_left_out[1]:4 *C 3.680 69.655 +*N chanx_left_out[1]:5 *C 3.625 69.700 + +*CAP +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[1] 0.0001814296 +2 chanx_left_out[1]:2 0.0001814296 +3 chanx_left_out[1]:3 0.0002700242 +4 chanx_left_out[1]:4 0.0002700242 +5 chanx_left_out[1]:5 2.66612e-05 + +*RES +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[1]:5 0.152 +1 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +2 chanx_left_out[1]:4 chanx_left_out[1]:3 0.004462054 +3 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +4 chanx_left_out[1]:2 chanx_left_out[1] 0.0003826583 + +*END + +*D_NET chanx_left_out[5] 0.0007376003 //LENGTH 5.605 LUMPCC 0 DR + +*CONN +*I mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.680 63.920 +*P chanx_left_out[5] O *L 0.7423 *C 1.305 61.200 +*N chanx_left_out[5]:2 *C 3.673 61.200 +*N chanx_left_out[5]:3 *C 3.680 61.258 +*N chanx_left_out[5]:4 *C 3.680 63.875 +*N chanx_left_out[5]:5 *C 3.680 63.920 + +*CAP +0 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[5] 0.0001916606 +2 chanx_left_out[5]:2 0.0001916606 +3 chanx_left_out[5]:3 0.0001604762 +4 chanx_left_out[5]:4 0.0001604762 +5 chanx_left_out[5]:5 3.232675e-05 + +*RES +0 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[5]:5 0.152 +1 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +2 chanx_left_out[5]:2 chanx_left_out[5] 0.0003709083 +3 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +4 chanx_left_out[5]:4 chanx_left_out[5]:3 0.002337054 + +*END + +*D_NET chanx_left_out[10] 0.001549472 //LENGTH 11.145 LUMPCC 0.0005157944 DR + +*CONN +*I mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 11.905 20.400 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 20.400 +*N chanx_left_out[10]:2 *C 11.492 20.400 +*N chanx_left_out[10]:3 *C 11.500 20.400 +*N chanx_left_out[10]:4 *C 11.523 20.400 +*N chanx_left_out[10]:5 *C 11.890 20.400 + +*CAP +0 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[10] 0.000456321 +2 chanx_left_out[10]:2 0.000456321 +3 chanx_left_out[10]:3 3.500239e-05 +4 chanx_left_out[10]:4 4.251656e-05 +5 chanx_left_out[10]:5 4.251656e-05 +6 chanx_left_out[10] chanx_left_in[17] 0.0002578972 +7 chanx_left_out[10]:2 chanx_left_in[17]:8 0.0002578972 + +*RES +0 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[10]:5 0.152 +1 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0001997283 +2 chanx_left_out[10]:4 chanx_left_out[10]:3 0.0045 +3 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +4 chanx_left_out[10]:2 chanx_left_out[10] 0.001607792 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[0] 0.0009334513 //LENGTH 6.745 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.945 77.180 +*I mux_top_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 41.760 74.800 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.035 77.180 +*N mux_tree_tapbuf_size2_10_sram[0]:3 *C 41.998 77.180 +*N mux_tree_tapbuf_size2_10_sram[0]:4 *C 41.745 74.800 +*N mux_tree_tapbuf_size2_10_sram[0]:5 *C 41.422 74.800 +*N mux_tree_tapbuf_size2_10_sram[0]:6 *C 41.400 74.845 +*N mux_tree_tapbuf_size2_10_sram[0]:7 *C 41.400 77.135 +*N mux_tree_tapbuf_size2_10_sram[0]:8 *C 41.400 77.180 +*N mux_tree_tapbuf_size2_10_sram[0]:9 *C 38.983 77.180 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_32\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_10_sram[0]:3 4.991204e-05 +4 mux_tree_tapbuf_size2_10_sram[0]:4 6.95355e-05 +5 mux_tree_tapbuf_size2_10_sram[0]:5 6.95355e-05 +6 mux_tree_tapbuf_size2_10_sram[0]:6 0.0001700134 +7 mux_tree_tapbuf_size2_10_sram[0]:7 0.0001700134 +8 mux_tree_tapbuf_size2_10_sram[0]:8 0.000242252 +9 mux_tree_tapbuf_size2_10_sram[0]:9 0.0001591895 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_10_sram[0]:9 0.152 +1 mux_tree_tapbuf_size2_10_sram[0]:4 mux_top_track_32\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_10_sram[0]:5 mux_tree_tapbuf_size2_10_sram[0]:4 0.0001752718 +3 mux_tree_tapbuf_size2_10_sram[0]:6 mux_tree_tapbuf_size2_10_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size2_10_sram[0]:8 mux_tree_tapbuf_size2_10_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size2_10_sram[0]:8 mux_tree_tapbuf_size2_10_sram[0]:3 0.0005334822 +6 mux_tree_tapbuf_size2_10_sram[0]:7 mux_tree_tapbuf_size2_10_sram[0]:6 0.002044643 +7 mux_tree_tapbuf_size2_10_sram[0]:3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_10_sram[0]:9 mux_tree_tapbuf_size2_10_sram[0]:8 0.002158482 + +*END + +*D_NET mux_tree_tapbuf_size2_14_sram[1] 0.002188717 //LENGTH 16.420 LUMPCC 0.0002653861 DR + +*CONN +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 45.385 69.700 +*I mux_left_track_11\/mux_l2_in_0_:S I *L 0.00357 *C 35.540 68.680 +*I mem_left_track_11\/FTB_27__32:A I *L 0.001746 *C 41.860 72.080 +*N mux_tree_tapbuf_size2_14_sram[1]:3 *C 41.898 72.080 +*N mux_tree_tapbuf_size2_14_sram[1]:4 *C 42.735 72.080 +*N mux_tree_tapbuf_size2_14_sram[1]:5 *C 42.780 72.035 +*N mux_tree_tapbuf_size2_14_sram[1]:6 *C 35.578 68.680 +*N mux_tree_tapbuf_size2_14_sram[1]:7 *C 36.755 68.680 +*N mux_tree_tapbuf_size2_14_sram[1]:8 *C 36.800 68.725 +*N mux_tree_tapbuf_size2_14_sram[1]:9 *C 36.800 69.983 +*N mux_tree_tapbuf_size2_14_sram[1]:10 *C 36.808 70.040 +*N mux_tree_tapbuf_size2_14_sram[1]:11 *C 42.773 70.040 +*N mux_tree_tapbuf_size2_14_sram[1]:12 *C 42.780 70.097 +*N mux_tree_tapbuf_size2_14_sram[1]:13 *C 42.780 69.700 +*N mux_tree_tapbuf_size2_14_sram[1]:14 *C 42.825 69.700 +*N mux_tree_tapbuf_size2_14_sram[1]:15 *C 45.348 69.700 + +*CAP +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_11\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_11\/FTB_27__32:A 1e-06 +3 mux_tree_tapbuf_size2_14_sram[1]:3 7.100322e-05 +4 mux_tree_tapbuf_size2_14_sram[1]:4 7.100322e-05 +5 mux_tree_tapbuf_size2_14_sram[1]:5 0.0001338058 +6 mux_tree_tapbuf_size2_14_sram[1]:6 0.0001102402 +7 mux_tree_tapbuf_size2_14_sram[1]:7 0.0001102402 +8 mux_tree_tapbuf_size2_14_sram[1]:8 8.965583e-05 +9 mux_tree_tapbuf_size2_14_sram[1]:9 8.965583e-05 +10 mux_tree_tapbuf_size2_14_sram[1]:10 0.0003401143 +11 mux_tree_tapbuf_size2_14_sram[1]:11 0.0003401143 +12 mux_tree_tapbuf_size2_14_sram[1]:12 0.0001547405 +13 mux_tree_tapbuf_size2_14_sram[1]:13 5.444483e-05 +14 mux_tree_tapbuf_size2_14_sram[1]:14 0.0001776563 +15 mux_tree_tapbuf_size2_14_sram[1]:15 0.0001776563 +16 mux_tree_tapbuf_size2_14_sram[1]:11 chany_top_in[17]:7 0.0001278708 +17 mux_tree_tapbuf_size2_14_sram[1]:9 chany_top_in[17]:5 4.822256e-06 +18 mux_tree_tapbuf_size2_14_sram[1]:10 chany_top_in[17]:6 0.0001278708 +19 mux_tree_tapbuf_size2_14_sram[1]:8 chany_top_in[17]:4 4.822256e-06 + +*RES +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_14_sram[1]:15 0.152 +1 mux_tree_tapbuf_size2_14_sram[1]:12 mux_tree_tapbuf_size2_14_sram[1]:11 0.00341 +2 mux_tree_tapbuf_size2_14_sram[1]:12 mux_tree_tapbuf_size2_14_sram[1]:5 0.001729911 +3 mux_tree_tapbuf_size2_14_sram[1]:11 mux_tree_tapbuf_size2_14_sram[1]:10 0.0009345167 +4 mux_tree_tapbuf_size2_14_sram[1]:9 mux_tree_tapbuf_size2_14_sram[1]:8 0.001122768 +5 mux_tree_tapbuf_size2_14_sram[1]:10 mux_tree_tapbuf_size2_14_sram[1]:9 0.00341 +6 mux_tree_tapbuf_size2_14_sram[1]:7 mux_tree_tapbuf_size2_14_sram[1]:6 0.001051339 +7 mux_tree_tapbuf_size2_14_sram[1]:8 mux_tree_tapbuf_size2_14_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size2_14_sram[1]:6 mux_left_track_11\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_14_sram[1]:14 mux_tree_tapbuf_size2_14_sram[1]:13 0.0045 +10 mux_tree_tapbuf_size2_14_sram[1]:13 mux_tree_tapbuf_size2_14_sram[1]:12 0.0001911058 +11 mux_tree_tapbuf_size2_14_sram[1]:15 mux_tree_tapbuf_size2_14_sram[1]:14 0.002252232 +12 mux_tree_tapbuf_size2_14_sram[1]:4 mux_tree_tapbuf_size2_14_sram[1]:3 0.0007477679 +13 mux_tree_tapbuf_size2_14_sram[1]:5 mux_tree_tapbuf_size2_14_sram[1]:4 0.0045 +14 mux_tree_tapbuf_size2_14_sram[1]:3 mem_left_track_11\/FTB_27__32:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_18_sram[0] 0.002091327 //LENGTH 16.635 LUMPCC 0 DR + +*CONN +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 17.335 26.180 +*I mux_left_track_19\/mux_l1_in_0_:S I *L 0.00357 *C 20.580 36.040 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 20.370 26.180 +*N mux_tree_tapbuf_size2_18_sram[0]:3 *C 20.332 26.180 +*N mux_tree_tapbuf_size2_18_sram[0]:4 *C 20.543 36.040 +*N mux_tree_tapbuf_size2_18_sram[0]:5 *C 18.303 36.040 +*N mux_tree_tapbuf_size2_18_sram[0]:6 *C 17.963 36.040 +*N mux_tree_tapbuf_size2_18_sram[0]:7 *C 17.940 35.995 +*N mux_tree_tapbuf_size2_18_sram[0]:8 *C 17.940 26.225 +*N mux_tree_tapbuf_size2_18_sram[0]:9 *C 17.940 26.180 +*N mux_tree_tapbuf_size2_18_sram[0]:10 *C 17.373 26.180 + +*CAP +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_19\/mux_l1_in_0_:S 1e-06 +2 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_18_sram[0]:3 0.0001998377 +4 mux_tree_tapbuf_size2_18_sram[0]:4 0.0001817539 +5 mux_tree_tapbuf_size2_18_sram[0]:5 0.0002313799 +6 mux_tree_tapbuf_size2_18_sram[0]:6 4.962593e-05 +7 mux_tree_tapbuf_size2_18_sram[0]:7 0.0005538607 +8 mux_tree_tapbuf_size2_18_sram[0]:8 0.0005538607 +9 mux_tree_tapbuf_size2_18_sram[0]:9 0.0002743549 +10 mux_tree_tapbuf_size2_18_sram[0]:10 4.365347e-05 + +*RES +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_18_sram[0]:10 0.152 +1 mux_tree_tapbuf_size2_18_sram[0]:10 mux_tree_tapbuf_size2_18_sram[0]:9 0.0005066964 +2 mux_tree_tapbuf_size2_18_sram[0]:9 mux_tree_tapbuf_size2_18_sram[0]:8 0.0045 +3 mux_tree_tapbuf_size2_18_sram[0]:9 mux_tree_tapbuf_size2_18_sram[0]:3 0.002136161 +4 mux_tree_tapbuf_size2_18_sram[0]:8 mux_tree_tapbuf_size2_18_sram[0]:7 0.008723214 +5 mux_tree_tapbuf_size2_18_sram[0]:6 mux_tree_tapbuf_size2_18_sram[0]:5 0.0001847826 +6 mux_tree_tapbuf_size2_18_sram[0]:7 mux_tree_tapbuf_size2_18_sram[0]:6 0.0045 +7 mux_tree_tapbuf_size2_18_sram[0]:4 mux_left_track_19\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_18_sram[0]:3 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size2_18_sram[0]:5 mux_tree_tapbuf_size2_18_sram[0]:4 0.002 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.005987999 //LENGTH 40.925 LUMPCC 0.001250497 DR + +*CONN +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.065 42.160 +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 47.555 49.980 +*I mux_top_track_14\/mux_l1_in_0_:S I *L 0.00357 *C 43.600 52.700 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 43.638 52.700 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 47.335 52.700 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 47.380 52.655 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 47.555 49.980 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 47.380 49.980 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 47.380 49.980 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 47.380 47.657 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 47.388 47.600 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 70.373 47.600 +*N mux_tree_tapbuf_size2_2_sram[0]:12 *C 70.380 47.543 +*N mux_tree_tapbuf_size2_2_sram[0]:13 *C 70.380 42.205 +*N mux_tree_tapbuf_size2_2_sram[0]:14 *C 70.425 42.160 +*N mux_tree_tapbuf_size2_2_sram[0]:15 *C 72.028 42.160 + +*CAP +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_14\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 0.0003051435 +4 mux_tree_tapbuf_size2_2_sram[0]:4 0.0003051435 +5 mux_tree_tapbuf_size2_2_sram[0]:5 0.0001537521 +6 mux_tree_tapbuf_size2_2_sram[0]:6 4.741128e-05 +7 mux_tree_tapbuf_size2_2_sram[0]:7 5.138489e-05 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.0003206476 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.0001344837 +10 mux_tree_tapbuf_size2_2_sram[0]:10 0.001257351 +11 mux_tree_tapbuf_size2_2_sram[0]:11 0.001257351 +12 mux_tree_tapbuf_size2_2_sram[0]:12 0.0003181921 +13 mux_tree_tapbuf_size2_2_sram[0]:13 0.0003181921 +14 mux_tree_tapbuf_size2_2_sram[0]:14 0.0001327242 +15 mux_tree_tapbuf_size2_2_sram[0]:15 0.0001327242 +16 mux_tree_tapbuf_size2_2_sram[0]:9 chany_top_in[16]:5 1.418382e-06 +17 mux_tree_tapbuf_size2_2_sram[0]:10 chany_top_in[16]:7 0.0006238302 +18 mux_tree_tapbuf_size2_2_sram[0]:11 chany_top_in[16]:8 0.0006238302 +19 mux_tree_tapbuf_size2_2_sram[0]:8 chany_top_in[16]:6 1.418382e-06 + +*RES +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.002073661 +2 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.00341 +3 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_2_sram[0]:11 0.00341 +4 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.003600983 +5 mux_tree_tapbuf_size2_2_sram[0]:14 mux_tree_tapbuf_size2_2_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_2_sram[0]:12 0.004765625 +7 mux_tree_tapbuf_size2_2_sram[0]:15 mux_tree_tapbuf_size2_2_sram[0]:14 0.001430804 +8 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 9.51087e-05 +9 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:5 0.002388393 +11 mux_tree_tapbuf_size2_2_sram[0]:6 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_2_sram[0]:4 mux_tree_tapbuf_size2_2_sram[0]:3 0.00330134 +13 mux_tree_tapbuf_size2_2_sram[0]:5 mux_tree_tapbuf_size2_2_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size2_2_sram[0]:3 mux_top_track_14\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[1] 0.001365038 //LENGTH 10.845 LUMPCC 0.0001708571 DR + +*CONN +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.425 98.600 +*I mux_top_track_28\/mux_l2_in_0_:S I *L 0.00357 *C 43.580 96.220 +*I mem_top_track_28\/FTB_21__26:A I *L 0.001746 *C 40.480 93.840 +*N mux_tree_tapbuf_size2_8_sram[1]:3 *C 40.480 93.840 +*N mux_tree_tapbuf_size2_8_sram[1]:4 *C 40.480 93.885 +*N mux_tree_tapbuf_size2_8_sram[1]:5 *C 43.543 96.220 +*N mux_tree_tapbuf_size2_8_sram[1]:6 *C 40.525 96.220 +*N mux_tree_tapbuf_size2_8_sram[1]:7 *C 40.480 96.220 +*N mux_tree_tapbuf_size2_8_sram[1]:8 *C 40.480 98.555 +*N mux_tree_tapbuf_size2_8_sram[1]:9 *C 40.435 98.600 +*N mux_tree_tapbuf_size2_8_sram[1]:10 *C 38.462 98.600 + +*CAP +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_28\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_28\/FTB_21__26:A 1e-06 +3 mux_tree_tapbuf_size2_8_sram[1]:3 2.898299e-05 +4 mux_tree_tapbuf_size2_8_sram[1]:4 0.0001235606 +5 mux_tree_tapbuf_size2_8_sram[1]:5 0.00016063 +6 mux_tree_tapbuf_size2_8_sram[1]:6 0.00016063 +7 mux_tree_tapbuf_size2_8_sram[1]:7 0.0002918475 +8 mux_tree_tapbuf_size2_8_sram[1]:8 0.0001354518 +9 mux_tree_tapbuf_size2_8_sram[1]:9 0.000145039 +10 mux_tree_tapbuf_size2_8_sram[1]:10 0.000145039 +11 mux_tree_tapbuf_size2_8_sram[1]:5 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.492017e-05 +12 mux_tree_tapbuf_size2_8_sram[1]:6 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.492017e-05 +13 mux_tree_tapbuf_size2_8_sram[1]:7 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.050837e-05 +14 mux_tree_tapbuf_size2_8_sram[1]:4 mux_top_track_28/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.050837e-05 + +*RES +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_8_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_8_sram[1]:5 mux_top_track_28\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_8_sram[1]:6 mux_tree_tapbuf_size2_8_sram[1]:5 0.002694197 +3 mux_tree_tapbuf_size2_8_sram[1]:7 mux_tree_tapbuf_size2_8_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size2_8_sram[1]:7 mux_tree_tapbuf_size2_8_sram[1]:4 0.002084821 +5 mux_tree_tapbuf_size2_8_sram[1]:3 mem_top_track_28\/FTB_21__26:A 0.152 +6 mux_tree_tapbuf_size2_8_sram[1]:4 mux_tree_tapbuf_size2_8_sram[1]:3 0.0045 +7 mux_tree_tapbuf_size2_8_sram[1]:10 mux_tree_tapbuf_size2_8_sram[1]:9 0.001761161 +8 mux_tree_tapbuf_size2_8_sram[1]:9 mux_tree_tapbuf_size2_8_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size2_8_sram[1]:8 mux_tree_tapbuf_size2_8_sram[1]:7 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_17_ccff_tail[0] 0.0004176736 //LENGTH 3.330 LUMPCC 0 DR + +*CONN +*I mem_left_track_17\/FTB_30__35:X O *L 0 *C 11.315 23.460 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 11.630 26.180 +*N mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:2 *C 11.500 26.180 +*N mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:3 *C 11.500 26.135 +*N mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:4 *C 11.500 23.505 +*N mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:5 *C 11.500 23.460 +*N mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:6 *C 11.315 23.460 + +*CAP +0 mem_left_track_17\/FTB_30__35:X 1e-06 +1 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:2 3.233681e-05 +3 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:3 0.0001413509 +4 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:4 0.0001413509 +5 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:5 5.136492e-05 +6 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:6 4.927016e-05 + +*RES +0 mem_left_track_17\/FTB_30__35:X mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:6 0.152 +1 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:5 0.0001005435 +2 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:4 0.0045 +3 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:3 0.002348214 +4 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:2 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +5 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_17_ccff_tail[0]:2 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_6_ccff_tail[0] 0.0005853028 //LENGTH 2.940 LUMPCC 0.0002493127 DR + +*CONN +*I mem_top_track_22\/FTB_19__24:X O *L 0 *C 84.415 91.460 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 83.890 93.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 *C 83.890 93.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 *C 84.180 93.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 *C 84.180 93.455 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 *C 84.180 91.505 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 *C 84.180 91.460 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 *C 84.415 91.460 + +*CAP +0 mem_top_track_22\/FTB_19__24:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 6.277903e-05 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 6.06936e-05 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 4.225549e-05 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 4.225549e-05 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 6.323531e-05 +7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 6.277116e-05 +8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chany_top_in[18] 6.232818e-05 +9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chany_top_in[18]:12 6.232818e-05 +10 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chany_top_out[5] 6.232818e-05 +11 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chany_top_out[5]:2 6.232818e-05 + +*RES +0 mem_top_track_22\/FTB_19__24:X mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.0001576087 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_3_ccff_tail[0] 0.001000476 //LENGTH 8.040 LUMPCC 0.0002101484 DR + +*CONN +*I mem_left_track_25\/FTB_12__17:X O *L 0 *C 48.525 37.400 +*I mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 48.475 44.540 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 *C 48.475 44.540 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 *C 48.300 44.540 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 *C 48.300 44.495 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 *C 48.300 37.445 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 *C 48.300 37.400 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 *C 48.525 37.400 + +*CAP +0 mem_left_track_25\/FTB_12__17:X 1e-06 +1 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 5.160747e-05 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 5.604567e-05 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.0002840268 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0002840268 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 5.68626e-05 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 5.575785e-05 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 chany_top_in[8]:4 3.95606e-05 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 chany_top_in[8]:5 3.95606e-05 +10 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_3_sram[0]:9 6.551358e-05 +11 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_3_sram[0]:8 6.551358e-05 + +*RES +0 mem_left_track_25\/FTB_12__17:X mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.006294643 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 mem_left_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[2] 0.002601415 //LENGTH 18.290 LUMPCC 0.0008253841 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.025 55.760 +*I mem_left_track_7\/FTB_8__13:A I *L 0.001746 *C 34.500 53.040 +*I mux_left_track_7\/mux_l3_in_0_:S I *L 0.00357 *C 27.240 55.760 +*N mux_tree_tapbuf_size5_3_sram[2]:3 *C 27.140 55.760 +*N mux_tree_tapbuf_size5_3_sram[2]:4 *C 27.140 55.715 +*N mux_tree_tapbuf_size5_3_sram[2]:5 *C 27.140 53.085 +*N mux_tree_tapbuf_size5_3_sram[2]:6 *C 27.185 53.040 +*N mux_tree_tapbuf_size5_3_sram[2]:7 *C 34.462 53.040 +*N mux_tree_tapbuf_size5_3_sram[2]:8 *C 34.500 53.085 +*N mux_tree_tapbuf_size5_3_sram[2]:9 *C 34.500 54.343 +*N mux_tree_tapbuf_size5_3_sram[2]:10 *C 34.508 54.400 +*N mux_tree_tapbuf_size5_3_sram[2]:11 *C 36.793 54.400 +*N mux_tree_tapbuf_size5_3_sram[2]:12 *C 36.800 54.458 +*N mux_tree_tapbuf_size5_3_sram[2]:13 *C 36.800 55.715 +*N mux_tree_tapbuf_size5_3_sram[2]:14 *C 36.845 55.760 +*N mux_tree_tapbuf_size5_3_sram[2]:15 *C 37.988 55.760 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_7\/FTB_8__13:A 1e-06 +2 mux_left_track_7\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size5_3_sram[2]:3 3.725277e-05 +4 mux_tree_tapbuf_size5_3_sram[2]:4 0.0001307551 +5 mux_tree_tapbuf_size5_3_sram[2]:5 0.0001307551 +6 mux_tree_tapbuf_size5_3_sram[2]:6 0.0003972967 +7 mux_tree_tapbuf_size5_3_sram[2]:7 0.0003972967 +8 mux_tree_tapbuf_size5_3_sram[2]:8 9.748427e-05 +9 mux_tree_tapbuf_size5_3_sram[2]:9 9.748427e-05 +10 mux_tree_tapbuf_size5_3_sram[2]:10 3.997647e-05 +11 mux_tree_tapbuf_size5_3_sram[2]:11 3.997647e-05 +12 mux_tree_tapbuf_size5_3_sram[2]:12 9.293829e-05 +13 mux_tree_tapbuf_size5_3_sram[2]:13 9.293829e-05 +14 mux_tree_tapbuf_size5_3_sram[2]:14 0.0001094386 +15 mux_tree_tapbuf_size5_3_sram[2]:15 0.0001094386 +16 mux_tree_tapbuf_size5_3_sram[2]:10 chany_top_in[3]:9 0.000144263 +17 mux_tree_tapbuf_size5_3_sram[2]:11 chany_top_in[3]:10 0.000144263 +18 mux_tree_tapbuf_size5_3_sram[2]:8 left_top_grid_pin_42_[0]:13 2.877235e-08 +19 mux_tree_tapbuf_size5_3_sram[2]:8 left_top_grid_pin_42_[0]:17 1.644134e-08 +20 mux_tree_tapbuf_size5_3_sram[2]:9 left_top_grid_pin_42_[0]:16 4.52137e-08 +21 mux_tree_tapbuf_size5_3_sram[2]:10 left_top_grid_pin_42_[0]:19 0.0001440872 +22 mux_tree_tapbuf_size5_3_sram[2]:11 left_top_grid_pin_42_[0]:18 0.0001440872 +23 mux_tree_tapbuf_size5_3_sram[2]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 4.598423e-05 +24 mux_tree_tapbuf_size5_3_sram[2]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.598423e-05 +25 mux_tree_tapbuf_size5_3_sram[2]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.023837e-05 +26 mux_tree_tapbuf_size5_3_sram[2]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.807398e-05 +27 mux_tree_tapbuf_size5_3_sram[2]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 1.023837e-05 +28 mux_tree_tapbuf_size5_3_sram[2]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.807398e-05 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_3_sram[2]:15 0.152 +1 mux_tree_tapbuf_size5_3_sram[2]:7 mem_left_track_7\/FTB_8__13:A 0.152 +2 mux_tree_tapbuf_size5_3_sram[2]:7 mux_tree_tapbuf_size5_3_sram[2]:6 0.006497768 +3 mux_tree_tapbuf_size5_3_sram[2]:8 mux_tree_tapbuf_size5_3_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size5_3_sram[2]:9 mux_tree_tapbuf_size5_3_sram[2]:8 0.001122768 +5 mux_tree_tapbuf_size5_3_sram[2]:10 mux_tree_tapbuf_size5_3_sram[2]:9 0.00341 +6 mux_tree_tapbuf_size5_3_sram[2]:12 mux_tree_tapbuf_size5_3_sram[2]:11 0.00341 +7 mux_tree_tapbuf_size5_3_sram[2]:11 mux_tree_tapbuf_size5_3_sram[2]:10 0.0003579833 +8 mux_tree_tapbuf_size5_3_sram[2]:14 mux_tree_tapbuf_size5_3_sram[2]:13 0.0045 +9 mux_tree_tapbuf_size5_3_sram[2]:13 mux_tree_tapbuf_size5_3_sram[2]:12 0.001122768 +10 mux_tree_tapbuf_size5_3_sram[2]:15 mux_tree_tapbuf_size5_3_sram[2]:14 0.001020089 +11 mux_tree_tapbuf_size5_3_sram[2]:6 mux_tree_tapbuf_size5_3_sram[2]:5 0.0045 +12 mux_tree_tapbuf_size5_3_sram[2]:5 mux_tree_tapbuf_size5_3_sram[2]:4 0.002348214 +13 mux_tree_tapbuf_size5_3_sram[2]:3 mux_left_track_7\/mux_l3_in_0_:S 0.152 +14 mux_tree_tapbuf_size5_3_sram[2]:4 mux_tree_tapbuf_size5_3_sram[2]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.0007838778 //LENGTH 6.280 LUMPCC 9.283451e-05 DR + +*CONN +*I mem_top_track_4\/FTB_2__7:X O *L 0 *C 92.685 58.480 +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 89.415 60.860 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 89.415 60.860 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 89.700 60.860 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 89.700 60.815 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 89.700 58.525 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 89.745 58.480 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 92.648 58.480 + +*CAP +0 mem_top_track_4\/FTB_2__7:X 1e-06 +1 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 4.940583e-05 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 5.021891e-05 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.0001264523 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0001264523 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.000168257 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.000168257 +8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_1_sram[2]:6 3.761988e-05 +9 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_1_sram[2]:7 3.761988e-05 +10 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_1_sram[2]:8 8.797379e-06 +11 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_1_sram[2]:4 8.797379e-06 + +*RES +0 mem_top_track_4\/FTB_2__7:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.002591518 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 0.0001005435 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005795677 //LENGTH 4.100 LUMPCC 0.0001039112 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 87.225 76.840 +*I mux_top_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 88.320 74.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 88.320 74.460 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 88.320 74.505 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 88.320 76.795 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 88.275 76.840 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 87.263 76.840 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.333379e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001577518 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001577518 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.240953e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.240953e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_0_sram[0]:17 5.195561e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_0_sram[0]:18 5.195561e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0009040179 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002044643 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A1 0.152 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001130809 //LENGTH 9.290 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 26.045 55.080 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 25.205 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 25.242 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 25.715 47.260 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 25.760 47.305 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 25.760 55.035 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 25.760 55.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 26.045 55.080 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.27676e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.27676e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004411534 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004411534 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.434233e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.662515e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.004487568 //LENGTH 35.765 LUMPCC 0.001403576 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_0_:X O *L 0 *C 19.955 45.220 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.850 20.600 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.850 20.600 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 9.850 21.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 14.215 21.080 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 14.260 21.125 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 14.260 45.175 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 14.305 45.220 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 19.918 45.220 + +*CAP +0 mux_left_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.893786e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003217666 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002843567 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000937505 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000937505 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002659606 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002659606 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_top_in[5]:6 5.955796e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_top_in[5]:8 5.760598e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_top_in[5]:10 1.542068e-06 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[5]:7 5.955796e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[5]:9 5.760598e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[5]:11 1.542068e-06 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size2_17_sram[0]:5 0.0003596011 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size2_17_sram[0]:6 0.0003596011 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size2_17_sram[1]:5 0.0001433873 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size2_17_sram[1]:10 8.009336e-05 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size2_17_sram[1]:10 0.0001433873 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size2_17_sram[1]:11 8.009336e-05 + +*RES +0 mux_left_track_5\/mux_l3_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.003897321 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.02147322 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.005011161 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0004285715 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002788258 //LENGTH 19.860 LUMPCC 0.0005749817 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_0_:X O *L 0 *C 18.115 64.600 +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.275 69.530 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 5.275 69.568 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 5.275 70.040 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 17.435 70.040 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 17.480 69.995 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 17.480 64.645 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 17.525 64.600 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 18.078 64.600 + +*CAP +0 mux_left_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.097666e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0008167331 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0007657565 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002283023 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002283023 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.060279e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.060279e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 left_top_grid_pin_44_[0]:15 0.0001460437 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 left_top_grid_pin_44_[0]:14 0.0001460437 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 chanx_left_out[13]:6 0.0001414472 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_out[13]:5 0.0001414472 + +*RES +0 mux_left_track_3\/mux_l3_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.01085714 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.004776786 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0004933036 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.000421875 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001071022 //LENGTH 8.830 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 41.575 46.920 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.005458 *C 42.320 39.270 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 42.320 39.270 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.860 39.270 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 41.860 46.875 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 41.860 46.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 41.575 46.920 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.147084e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004613772 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000425024 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.589107e-05 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.525923e-05 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.0045 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006790179 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001548913 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004107143 + +*END + +*D_NET mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008564035 //LENGTH 6.835 LUMPCC 0.0003498745 DR + +*CONN +*I mux_top_track_12\/mux_l1_in_0_:X O *L 0 *C 73.425 34.680 +*I mux_top_track_12\/mux_l2_in_0_:A1 I *L 0.00198 *C 72.320 39.780 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 72.358 39.780 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 73.095 39.780 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 73.140 39.735 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 73.140 34.725 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 73.140 34.680 +*N mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 73.425 34.680 + +*CAP +0 mux_top_track_12\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_12\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.932005e-05 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.932005e-05 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001399079 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001399079 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.305801e-05 +7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.301516e-05 +8 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_36_[0]:10 5.200345e-05 +9 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_36_[0]:7 5.200345e-05 +10 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[16]:4 7.471175e-05 +11 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[16]:5 7.471175e-05 +12 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_110:31 5.267354e-06 +13 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_110:28 6.168281e-06 +14 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_110:30 5.267354e-06 +15 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_110:27 6.168281e-06 +16 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_110:28 3.678639e-05 +17 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_110:29 3.678639e-05 + +*RES +0 mux_top_track_12\/mux_l1_in_0_:X mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_12\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006584821 +3 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004473215 +6 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_12/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001081805 //LENGTH 8.090 LUMPCC 0.0003330779 DR + +*CONN +*I mux_top_track_26\/mux_l1_in_0_:X O *L 0 *C 53.645 88.740 +*I mux_top_track_26\/mux_l2_in_0_:A1 I *L 0.00198 *C 53.820 96.220 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 53.820 96.220 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.820 96.175 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 53.820 88.785 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 53.820 88.740 +*N mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 53.645 88.740 + +*CAP +0 mux_top_track_26\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_26\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.518321e-05 +3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002952353 +4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002952353 +5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.20631e-05 +6 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.900987e-05 +7 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:154 6.110484e-05 +8 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 prog_clk[0]:155 6.110484e-05 +9 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[12]:13 4.440079e-05 +10 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[12] 4.440079e-05 +11 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.103331e-05 +12 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_18/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.103331e-05 + +*RES +0 mux_top_track_26\/mux_l1_in_0_:X mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 +2 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006598214 +4 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_26\/mux_l2_in_0_:A1 0.152 +5 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_26/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001688909 //LENGTH 11.405 LUMPCC 0.0008588623 DR + +*CONN +*I mux_top_track_34\/mux_l2_in_0_:X O *L 0 *C 59.165 83.640 +*I mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 60.045 93.655 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 60.008 93.555 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 59.385 93.500 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 59.340 93.455 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 59.340 83.685 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 59.340 83.640 +*N mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 59.165 83.640 + +*CAP +0 mux_top_track_34\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.031966e-05 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.031966e-05 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002944289 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002944289 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.92879e-05 +7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.926216e-05 +8 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_top_in[19]:14 8.959632e-06 +9 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[19]:13 8.959632e-06 +10 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[19]:13 0.0002319578 +11 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[19]:12 0.0002319578 +12 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_41_[0]:17 4.862102e-05 +13 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_41_[0]:18 0.0001398927 +14 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_41_[0]:14 4.862102e-05 +15 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_41_[0]:17 0.0001398927 + +*RES +0 mux_top_track_34\/mux_l2_in_0_:X mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_34\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005558036 +3 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.008723214 +6 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_34/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.510871e-05 + +*END + +*D_NET ropt_net_129 0.001337176 //LENGTH 10.085 LUMPCC 0.0001330157 DR + +*CONN +*I ropt_mt_inst_722:X O *L 0 *C 11.695 34.680 +*I ropt_mt_inst_734:A I *L 0.001767 *C 3.220 34.000 +*N ropt_net_129:2 *C 3.258 34.000 +*N ropt_net_129:3 *C 4.095 34.000 +*N ropt_net_129:4 *C 4.140 34.045 +*N ropt_net_129:5 *C 4.140 34.635 +*N ropt_net_129:6 *C 4.185 34.680 +*N ropt_net_129:7 *C 11.658 34.680 + +*CAP +0 ropt_mt_inst_722:X 1e-06 +1 ropt_mt_inst_734:A 1e-06 +2 ropt_net_129:2 6.493367e-05 +3 ropt_net_129:3 6.493367e-05 +4 ropt_net_129:4 6.385819e-05 +5 ropt_net_129:5 6.385819e-05 +6 ropt_net_129:6 0.0004722885 +7 ropt_net_129:7 0.0004722884 +8 ropt_net_129:7 ropt_net_115:5 5.952378e-05 +9 ropt_net_129:7 ropt_net_115:2 6.984061e-06 +10 ropt_net_129:6 ropt_net_115:3 6.984061e-06 +11 ropt_net_129:6 ropt_net_115:4 5.952378e-05 + +*RES +0 ropt_mt_inst_722:X ropt_net_129:7 0.152 +1 ropt_net_129:7 ropt_net_129:6 0.006671875 +2 ropt_net_129:6 ropt_net_129:5 0.0045 +3 ropt_net_129:5 ropt_net_129:4 0.0005267857 +4 ropt_net_129:3 ropt_net_129:2 0.0007477679 +5 ropt_net_129:4 ropt_net_129:3 0.0045 +6 ropt_net_129:2 ropt_mt_inst_734:A 0.152 + +*END + +*D_NET mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002264478 //LENGTH 19.850 LUMPCC 0 DR + +*CONN +*I mux_left_track_21\/mux_l2_in_0_:X O *L 0 *C 29.155 22.780 +*I mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 13.560 20.555 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 13.560 20.555 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 13.560 20.060 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.475 20.060 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.520 20.105 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 28.520 22.735 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 28.565 22.780 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 29.117 22.780 + +*CAP +0 mux_left_track_21\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.280728e-05 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0009141115 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0008737983 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001489885 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001489885 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.189179e-05 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:8 5.189179e-05 + +*RES +0 mux_left_track_21\/mux_l2_in_0_:X mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.152 +1 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.01331696 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0045 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.002348214 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004933036 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004419643 + +*END + +*D_NET chanx_left_out[16] 0.0007341056 //LENGTH 5.385 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 4.140 33.320 +*P chanx_left_out[16] O *L 0.7423 *C 1.305 31.280 +*N chanx_left_out[16]:2 *C 4.133 31.280 +*N chanx_left_out[16]:3 *C 4.140 31.338 +*N chanx_left_out[16]:4 *C 4.140 33.275 +*N chanx_left_out[16]:5 *C 4.140 33.320 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 chanx_left_out[16] 0.000198892 +2 chanx_left_out[16]:2 0.000198892 +3 chanx_left_out[16]:3 0.0001506751 +4 chanx_left_out[16]:4 0.0001506751 +5 chanx_left_out[16]:5 3.397154e-05 + +*RES +0 ropt_mt_inst_734:X chanx_left_out[16]:5 0.152 +1 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +2 chanx_left_out[16]:2 chanx_left_out[16] 0.000442975 +3 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +4 chanx_left_out[16]:4 chanx_left_out[16]:3 0.001729911 + +*END + +*D_NET chanx_left_out[14] 0.0009361343 //LENGTH 7.360 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 7.095 17.000 +*P chanx_left_out[14] O *L 0.7423 *C 1.230 17.680 +*N chanx_left_out[14]:2 *C 1.833 17.680 +*N chanx_left_out[14]:3 *C 1.840 17.623 +*N chanx_left_out[14]:4 *C 1.840 17.045 +*N chanx_left_out[14]:5 *C 1.885 17.000 +*N chanx_left_out[14]:6 *C 7.058 17.000 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 chanx_left_out[14] 6.187672e-05 +2 chanx_left_out[14]:2 6.187672e-05 +3 chanx_left_out[14]:3 6.121117e-05 +4 chanx_left_out[14]:4 6.121117e-05 +5 chanx_left_out[14]:5 0.0003444792 +6 chanx_left_out[14]:6 0.0003444792 + +*RES +0 ropt_mt_inst_737:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:6 chanx_left_out[14]:5 0.004618304 +2 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +3 chanx_left_out[14]:4 chanx_left_out[14]:3 0.000515625 +4 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +5 chanx_left_out[14]:2 chanx_left_out[14] 9.439165e-05 + +*END + +*D_NET mem_left_track_27/net_net_60 0.003153922 //LENGTH 22.690 LUMPCC 0.0001122781 DR + +*CONN +*I mem_left_track_27\/FTB_34__39:X O *L 0 *C 29.665 63.240 +*I mem_left_track_27\/BUFT_RR_60:A I *L 0.001743 *C 8.280 63.920 +*N mem_left_track_27/net_net_60:2 *C 8.280 63.920 +*N mem_left_track_27/net_net_60:3 *C 8.280 63.875 +*N mem_left_track_27/net_net_60:4 *C 8.280 63.285 +*N mem_left_track_27/net_net_60:5 *C 8.325 63.240 +*N mem_left_track_27/net_net_60:6 *C 29.628 63.240 + +*CAP +0 mem_left_track_27\/FTB_34__39:X 1e-06 +1 mem_left_track_27\/BUFT_RR_60:A 1e-06 +2 mem_left_track_27/net_net_60:2 3.120442e-05 +3 mem_left_track_27/net_net_60:3 5.043894e-05 +4 mem_left_track_27/net_net_60:4 5.043894e-05 +5 mem_left_track_27/net_net_60:5 0.001453781 +6 mem_left_track_27/net_net_60:6 0.001453781 +7 mem_left_track_27/net_net_60:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.613906e-05 +8 mem_left_track_27/net_net_60:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.613906e-05 + +*RES +0 mem_left_track_27\/FTB_34__39:X mem_left_track_27/net_net_60:6 0.152 +1 mem_left_track_27/net_net_60:2 mem_left_track_27\/BUFT_RR_60:A 0.152 +2 mem_left_track_27/net_net_60:3 mem_left_track_27/net_net_60:2 0.0045 +3 mem_left_track_27/net_net_60:5 mem_left_track_27/net_net_60:4 0.0045 +4 mem_left_track_27/net_net_60:4 mem_left_track_27/net_net_60:3 0.0005267857 +5 mem_left_track_27/net_net_60:6 mem_left_track_27/net_net_60:5 0.01902009 + +*END + +*D_NET ropt_net_118 0.003201806 //LENGTH 24.810 LUMPCC 0.0008215153 DR + +*CONN +*I BUFT_P_82:X O *L 0 *C 24.380 58.480 +*I ropt_mt_inst_725:A I *L 0.001766 *C 3.220 61.200 +*N ropt_net_118:2 *C 3.258 61.200 +*N ropt_net_118:3 *C 5.475 61.200 +*N ropt_net_118:4 *C 5.520 61.155 +*N ropt_net_118:5 *C 5.520 58.525 +*N ropt_net_118:6 *C 5.565 58.480 +*N ropt_net_118:7 *C 24.343 58.480 + +*CAP +0 BUFT_P_82:X 1e-06 +1 ropt_mt_inst_725:A 1e-06 +2 ropt_net_118:2 9.781239e-05 +3 ropt_net_118:3 9.781239e-05 +4 ropt_net_118:4 0.0001288687 +5 ropt_net_118:5 0.0001288687 +6 ropt_net_118:6 0.0009624643 +7 ropt_net_118:7 0.0009624643 +8 ropt_net_118:2 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 9.534044e-05 +9 ropt_net_118:3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 9.534044e-05 +10 ropt_net_118:4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 1.920949e-08 +11 ropt_net_118:5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 1.920949e-08 +12 ropt_net_118:6 optlc_net_109:19 4.778648e-06 +13 ropt_net_118:6 optlc_net_109:20 0.0002510961 +14 ropt_net_118:7 optlc_net_109:20 4.778648e-06 +15 ropt_net_118:7 optlc_net_109:21 0.0002510961 +16 ropt_net_118:4 ropt_net_127:10 5.952327e-05 +17 ropt_net_118:5 ropt_net_127:9 5.952327e-05 + +*RES +0 BUFT_P_82:X ropt_net_118:7 0.152 +1 ropt_net_118:2 ropt_mt_inst_725:A 0.152 +2 ropt_net_118:3 ropt_net_118:2 0.001979911 +3 ropt_net_118:4 ropt_net_118:3 0.0045 +4 ropt_net_118:6 ropt_net_118:5 0.0045 +5 ropt_net_118:5 ropt_net_118:4 0.002348214 +6 ropt_net_118:7 ropt_net_118:6 0.01676563 + +*END + +*D_NET chany_top_in[13] 0.01613902 //LENGTH 92.500 LUMPCC 0.004882207 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 63.480 102.070 +*I mux_left_track_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 11.040 63.580 +*N chany_top_in[13]:2 *C 11.040 63.580 +*N chany_top_in[13]:3 *C 11.040 63.625 +*N chany_top_in[13]:4 *C 11.040 64.543 +*N chany_top_in[13]:5 *C 11.048 64.600 +*N chany_top_in[13]:6 *C 55.180 64.600 +*N chany_top_in[13]:7 *C 55.200 64.608 +*N chany_top_in[13]:8 *C 55.200 100.633 +*N chany_top_in[13]:9 *C 55.220 100.640 +*N chany_top_in[13]:10 *C 63.473 100.640 +*N chany_top_in[13]:11 *C 63.480 100.698 + +*CAP +0 chany_top_in[13] 8.85847e-05 +1 mux_left_track_15\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[13]:2 3.444431e-05 +3 chany_top_in[13]:3 7.833148e-05 +4 chany_top_in[13]:4 7.833148e-05 +5 chany_top_in[13]:5 0.001632923 +6 chany_top_in[13]:6 0.001632923 +7 chany_top_in[13]:7 0.003200564 +8 chany_top_in[13]:8 0.003200564 +9 chany_top_in[13]:9 0.0006102794 +10 chany_top_in[13]:10 0.0006102794 +11 chany_top_in[13]:11 8.85847e-05 +12 chany_top_in[13]:5 chanx_left_in[1]:7 0.0004975325 +13 chany_top_in[13]:6 chanx_left_in[1]:6 0.0004975325 +14 chany_top_in[13]:5 left_top_grid_pin_49_[0]:21 0.0005028191 +15 chany_top_in[13]:5 left_top_grid_pin_49_[0]:13 0.0002102551 +16 chany_top_in[13]:6 left_top_grid_pin_49_[0]:12 0.0002102551 +17 chany_top_in[13]:6 left_top_grid_pin_49_[0]:20 0.0005028191 +18 chany_top_in[13]:5 mux_tree_tapbuf_size2_21_sram[0]:9 0.0002523549 +19 chany_top_in[13]:6 mux_tree_tapbuf_size2_21_sram[0]:10 0.0002523549 +20 chany_top_in[13]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001756099 +21 chany_top_in[13]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001756099 +22 chany_top_in[13]:5 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000802532 +23 chany_top_in[13]:6 mux_left_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000802532 + +*RES +0 chany_top_in[13] chany_top_in[13]:11 0.001225446 +1 chany_top_in[13]:2 mux_left_track_15\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[13]:3 chany_top_in[13]:2 0.0045 +3 chany_top_in[13]:4 chany_top_in[13]:3 0.0008191965 +4 chany_top_in[13]:5 chany_top_in[13]:4 0.00341 +5 chany_top_in[13]:6 chany_top_in[13]:5 0.006914091 +6 chany_top_in[13]:7 chany_top_in[13]:6 0.00341 +7 chany_top_in[13]:9 chany_top_in[13]:8 0.00341 +8 chany_top_in[13]:8 chany_top_in[13]:7 0.005643916 +9 chany_top_in[13]:11 chany_top_in[13]:10 0.00341 +10 chany_top_in[13]:10 chany_top_in[13]:9 0.001292892 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[0] 0.000924037 //LENGTH 6.765 LUMPCC 0 DR + +*CONN +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 56.425 77.180 +*I mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 55.835 75.140 +*I mux_top_track_34\/mux_l1_in_0_:S I *L 0.00357 *C 56.020 72.760 +*N mux_tree_tapbuf_size2_11_sram[0]:3 *C 56.005 72.760 +*N mux_tree_tapbuf_size2_11_sram[0]:4 *C 55.683 72.760 +*N mux_tree_tapbuf_size2_11_sram[0]:5 *C 55.660 72.805 +*N mux_tree_tapbuf_size2_11_sram[0]:6 *C 55.835 75.140 +*N mux_tree_tapbuf_size2_11_sram[0]:7 *C 55.660 75.140 +*N mux_tree_tapbuf_size2_11_sram[0]:8 *C 55.660 75.140 +*N mux_tree_tapbuf_size2_11_sram[0]:9 *C 55.660 77.135 +*N mux_tree_tapbuf_size2_11_sram[0]:10 *C 55.705 77.180 +*N mux_tree_tapbuf_size2_11_sram[0]:11 *C 56.388 77.180 + +*CAP +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_34\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_11_sram[0]:3 5.502535e-05 +4 mux_tree_tapbuf_size2_11_sram[0]:4 5.502535e-05 +5 mux_tree_tapbuf_size2_11_sram[0]:5 0.0001477813 +6 mux_tree_tapbuf_size2_11_sram[0]:6 5.091407e-05 +7 mux_tree_tapbuf_size2_11_sram[0]:7 5.626433e-05 +8 mux_tree_tapbuf_size2_11_sram[0]:8 0.0003062529 +9 mux_tree_tapbuf_size2_11_sram[0]:9 0.0001239145 +10 mux_tree_tapbuf_size2_11_sram[0]:10 6.29296e-05 +11 mux_tree_tapbuf_size2_11_sram[0]:11 6.29296e-05 + +*RES +0 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_11_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_11_sram[0]:3 mux_top_track_34\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_11_sram[0]:4 mux_tree_tapbuf_size2_11_sram[0]:3 0.0001752718 +3 mux_tree_tapbuf_size2_11_sram[0]:5 mux_tree_tapbuf_size2_11_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size2_11_sram[0]:7 mux_tree_tapbuf_size2_11_sram[0]:6 9.51087e-05 +5 mux_tree_tapbuf_size2_11_sram[0]:8 mux_tree_tapbuf_size2_11_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_11_sram[0]:8 mux_tree_tapbuf_size2_11_sram[0]:5 0.002084821 +7 mux_tree_tapbuf_size2_11_sram[0]:6 mem_top_track_34\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size2_11_sram[0]:10 mux_tree_tapbuf_size2_11_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_11_sram[0]:9 mux_tree_tapbuf_size2_11_sram[0]:8 0.00178125 +10 mux_tree_tapbuf_size2_11_sram[0]:11 mux_tree_tapbuf_size2_11_sram[0]:10 0.000609375 + +*END + +*D_NET mux_tree_tapbuf_size2_17_sram[1] 0.002524445 //LENGTH 18.960 LUMPCC 0.0008903662 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 15.485 31.280 +*I mux_left_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 7.000 28.560 +*I mem_left_track_17\/FTB_30__35:A I *L 0.001746 *C 14.260 23.120 +*N mux_tree_tapbuf_size2_17_sram[1]:3 *C 14.223 23.120 +*N mux_tree_tapbuf_size2_17_sram[1]:4 *C 13.845 23.120 +*N mux_tree_tapbuf_size2_17_sram[1]:5 *C 13.800 23.165 +*N mux_tree_tapbuf_size2_17_sram[1]:6 *C 7.038 28.560 +*N mux_tree_tapbuf_size2_17_sram[1]:7 *C 7.360 28.560 +*N mux_tree_tapbuf_size2_17_sram[1]:8 *C 7.360 28.220 +*N mux_tree_tapbuf_size2_17_sram[1]:9 *C 13.755 28.220 +*N mux_tree_tapbuf_size2_17_sram[1]:10 *C 13.800 28.220 +*N mux_tree_tapbuf_size2_17_sram[1]:11 *C 13.800 31.235 +*N mux_tree_tapbuf_size2_17_sram[1]:12 *C 13.845 31.280 +*N mux_tree_tapbuf_size2_17_sram[1]:13 *C 15.448 31.280 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_17\/FTB_30__35:A 1e-06 +3 mux_tree_tapbuf_size2_17_sram[1]:3 4.036578e-05 +4 mux_tree_tapbuf_size2_17_sram[1]:4 4.036578e-05 +5 mux_tree_tapbuf_size2_17_sram[1]:5 0.0001731847 +6 mux_tree_tapbuf_size2_17_sram[1]:6 3.603771e-05 +7 mux_tree_tapbuf_size2_17_sram[1]:7 6.325036e-05 +8 mux_tree_tapbuf_size2_17_sram[1]:8 0.0002959435 +9 mux_tree_tapbuf_size2_17_sram[1]:9 0.0002687308 +10 mux_tree_tapbuf_size2_17_sram[1]:10 0.0003353122 +11 mux_tree_tapbuf_size2_17_sram[1]:11 0.0001279173 +12 mux_tree_tapbuf_size2_17_sram[1]:12 0.0001249852 +13 mux_tree_tapbuf_size2_17_sram[1]:13 0.0001249852 +14 mux_tree_tapbuf_size2_17_sram[1]:9 optlc_net_107:41 0.0002217024 +15 mux_tree_tapbuf_size2_17_sram[1]:8 optlc_net_107:40 0.0002217024 +16 mux_tree_tapbuf_size2_17_sram[1]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.009336e-05 +17 mux_tree_tapbuf_size2_17_sram[1]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.009336e-05 +18 mux_tree_tapbuf_size2_17_sram[1]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001433873 +19 mux_tree_tapbuf_size2_17_sram[1]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001433873 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_17_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_17_sram[1]:13 mux_tree_tapbuf_size2_17_sram[1]:12 0.001430804 +2 mux_tree_tapbuf_size2_17_sram[1]:12 mux_tree_tapbuf_size2_17_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size2_17_sram[1]:11 mux_tree_tapbuf_size2_17_sram[1]:10 0.002691964 +4 mux_tree_tapbuf_size2_17_sram[1]:9 mux_tree_tapbuf_size2_17_sram[1]:8 0.005709822 +5 mux_tree_tapbuf_size2_17_sram[1]:10 mux_tree_tapbuf_size2_17_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_17_sram[1]:10 mux_tree_tapbuf_size2_17_sram[1]:5 0.004513393 +7 mux_tree_tapbuf_size2_17_sram[1]:6 mux_left_track_17\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_17_sram[1]:4 mux_tree_tapbuf_size2_17_sram[1]:3 0.0003370536 +9 mux_tree_tapbuf_size2_17_sram[1]:5 mux_tree_tapbuf_size2_17_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size2_17_sram[1]:3 mem_left_track_17\/FTB_30__35:A 0.152 +11 mux_tree_tapbuf_size2_17_sram[1]:7 mux_tree_tapbuf_size2_17_sram[1]:6 0.0002879465 +12 mux_tree_tapbuf_size2_17_sram[1]:8 mux_tree_tapbuf_size2_17_sram[1]:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.001057643 //LENGTH 8.730 LUMPCC 0 DR + +*CONN +*I mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 53.205 50.320 +*I mem_top_track_14\/FTB_15__20:A I *L 0.001746 *C 51.980 53.040 +*I mux_top_track_14\/mux_l2_in_0_:S I *L 0.008363 *C 51.938 55.930 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 51.523 56.070 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 51.520 56.055 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 51.520 53.085 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 51.565 53.040 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 51.980 53.040 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 52.855 53.040 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 52.900 52.995 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 52.900 50.365 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 52.900 50.320 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 53.205 50.320 + +*CAP +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_14\/FTB_15__20:A 1e-06 +2 mux_top_track_14\/mux_l2_in_0_:S 2.423014e-05 +3 mux_tree_tapbuf_size2_2_sram[1]:3 2.423014e-05 +4 mux_tree_tapbuf_size2_2_sram[1]:4 0.0001827356 +5 mux_tree_tapbuf_size2_2_sram[1]:5 0.0001827356 +6 mux_tree_tapbuf_size2_2_sram[1]:6 3.526116e-05 +7 mux_tree_tapbuf_size2_2_sram[1]:7 0.0001249301 +8 mux_tree_tapbuf_size2_2_sram[1]:8 6.142267e-05 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.0001569276 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.0001569276 +11 mux_tree_tapbuf_size2_2_sram[1]:11 5.698801e-05 +12 mux_tree_tapbuf_size2_2_sram[1]:12 4.925478e-05 + +*RES +0 mem_top_track_14\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:3 mux_top_track_14\/mux_l2_in_0_:S 3.90625e-05 +2 mux_tree_tapbuf_size2_2_sram[1]:4 mux_tree_tapbuf_size2_2_sram[1]:3 0.0045 +3 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size2_2_sram[1]:5 mux_tree_tapbuf_size2_2_sram[1]:4 0.002651786 +5 mux_tree_tapbuf_size2_2_sram[1]:7 mem_top_track_14\/FTB_15__20:A 0.152 +6 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.0003705357 +7 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.00078125 +8 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.0045 +10 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.002348214 +11 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[0] 0.003378639 //LENGTH 26.775 LUMPCC 0.000875353 DR + +*CONN +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 47.105 99.620 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 98.940 +*I mux_top_track_28\/mux_l1_in_0_:S I *L 0.00357 *C 34.380 94.520 +*N mux_tree_tapbuf_size2_8_sram[0]:3 *C 34.418 94.520 +*N mux_tree_tapbuf_size2_8_sram[0]:4 *C 34.915 94.520 +*N mux_tree_tapbuf_size2_8_sram[0]:5 *C 34.960 94.565 +*N mux_tree_tapbuf_size2_8_sram[0]:6 *C 32.873 98.940 +*N mux_tree_tapbuf_size2_8_sram[0]:7 *C 34.915 98.940 +*N mux_tree_tapbuf_size2_8_sram[0]:8 *C 34.960 98.940 +*N mux_tree_tapbuf_size2_8_sram[0]:9 *C 34.960 101.615 +*N mux_tree_tapbuf_size2_8_sram[0]:10 *C 34.960 101.660 +*N mux_tree_tapbuf_size2_8_sram[0]:11 *C 34.960 102.000 +*N mux_tree_tapbuf_size2_8_sram[0]:12 *C 39.560 102.000 +*N mux_tree_tapbuf_size2_8_sram[0]:13 *C 39.560 101.660 +*N mux_tree_tapbuf_size2_8_sram[0]:14 *C 46.875 101.660 +*N mux_tree_tapbuf_size2_8_sram[0]:15 *C 46.920 101.615 +*N mux_tree_tapbuf_size2_8_sram[0]:16 *C 46.920 99.665 +*N mux_tree_tapbuf_size2_8_sram[0]:17 *C 46.920 99.620 +*N mux_tree_tapbuf_size2_8_sram[0]:18 *C 47.105 99.620 + +*CAP +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_28\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_8_sram[0]:3 6.076067e-05 +4 mux_tree_tapbuf_size2_8_sram[0]:4 6.076067e-05 +5 mux_tree_tapbuf_size2_8_sram[0]:5 0.0002007409 +6 mux_tree_tapbuf_size2_8_sram[0]:6 0.0001588078 +7 mux_tree_tapbuf_size2_8_sram[0]:7 0.0001588078 +8 mux_tree_tapbuf_size2_8_sram[0]:8 0.000351749 +9 mux_tree_tapbuf_size2_8_sram[0]:9 0.0001197233 +10 mux_tree_tapbuf_size2_8_sram[0]:10 6.296847e-05 +11 mux_tree_tapbuf_size2_8_sram[0]:11 0.0002341715 +12 mux_tree_tapbuf_size2_8_sram[0]:12 0.0002273349 +13 mux_tree_tapbuf_size2_8_sram[0]:13 0.0002773849 +14 mux_tree_tapbuf_size2_8_sram[0]:14 0.0002551356 +15 mux_tree_tapbuf_size2_8_sram[0]:15 0.0001189677 +16 mux_tree_tapbuf_size2_8_sram[0]:16 0.0001189677 +17 mux_tree_tapbuf_size2_8_sram[0]:17 4.675732e-05 +18 mux_tree_tapbuf_size2_8_sram[0]:18 4.724816e-05 +19 mux_tree_tapbuf_size2_8_sram[0]:9 chany_top_in[4]:22 3.063999e-05 +20 mux_tree_tapbuf_size2_8_sram[0]:14 chany_top_in[4]:24 0.0002850767 +21 mux_tree_tapbuf_size2_8_sram[0]:5 chany_top_in[4]:21 5.033373e-05 +22 mux_tree_tapbuf_size2_8_sram[0]:8 chany_top_in[4]:21 3.063999e-05 +23 mux_tree_tapbuf_size2_8_sram[0]:8 chany_top_in[4]:22 5.033373e-05 +24 mux_tree_tapbuf_size2_8_sram[0]:11 chany_top_in[4]:23 7.162608e-05 +25 mux_tree_tapbuf_size2_8_sram[0]:12 chany_top_in[4]:24 7.162608e-05 +26 mux_tree_tapbuf_size2_8_sram[0]:13 chany_top_in[4]:23 0.0002850767 + +*RES +0 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_8_sram[0]:18 0.152 +1 mux_tree_tapbuf_size2_8_sram[0]:10 mux_tree_tapbuf_size2_8_sram[0]:9 0.0045 +2 mux_tree_tapbuf_size2_8_sram[0]:9 mux_tree_tapbuf_size2_8_sram[0]:8 0.002388393 +3 mux_tree_tapbuf_size2_8_sram[0]:14 mux_tree_tapbuf_size2_8_sram[0]:13 0.00653125 +4 mux_tree_tapbuf_size2_8_sram[0]:15 mux_tree_tapbuf_size2_8_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size2_8_sram[0]:17 mux_tree_tapbuf_size2_8_sram[0]:16 0.0045 +6 mux_tree_tapbuf_size2_8_sram[0]:16 mux_tree_tapbuf_size2_8_sram[0]:15 0.001741072 +7 mux_tree_tapbuf_size2_8_sram[0]:18 mux_tree_tapbuf_size2_8_sram[0]:17 0.0001005435 +8 mux_tree_tapbuf_size2_8_sram[0]:3 mux_top_track_28\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_8_sram[0]:4 mux_tree_tapbuf_size2_8_sram[0]:3 0.0004441965 +10 mux_tree_tapbuf_size2_8_sram[0]:5 mux_tree_tapbuf_size2_8_sram[0]:4 0.0045 +11 mux_tree_tapbuf_size2_8_sram[0]:7 mux_tree_tapbuf_size2_8_sram[0]:6 0.001823661 +12 mux_tree_tapbuf_size2_8_sram[0]:8 mux_tree_tapbuf_size2_8_sram[0]:7 0.0045 +13 mux_tree_tapbuf_size2_8_sram[0]:8 mux_tree_tapbuf_size2_8_sram[0]:5 0.00390625 +14 mux_tree_tapbuf_size2_8_sram[0]:6 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size2_8_sram[0]:11 mux_tree_tapbuf_size2_8_sram[0]:10 0.0003035715 +16 mux_tree_tapbuf_size2_8_sram[0]:12 mux_tree_tapbuf_size2_8_sram[0]:11 0.004107143 +17 mux_tree_tapbuf_size2_8_sram[0]:13 mux_tree_tapbuf_size2_8_sram[0]:12 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_9_ccff_tail[0] 0.001632081 //LENGTH 14.080 LUMPCC 0.0001374257 DR + +*CONN +*I mem_top_track_30\/FTB_22__27:X O *L 0 *C 40.705 82.280 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 33.295 77.180 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 *C 33.333 77.180 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 *C 36.295 77.180 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 *C 36.340 77.225 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 *C 36.340 79.855 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 *C 36.385 79.900 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 *C 39.975 79.900 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:8 *C 40.020 79.945 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:9 *C 40.020 82.235 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:10 *C 40.065 82.280 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:11 *C 40.668 82.280 + +*CAP +0 mem_top_track_30\/FTB_22__27:X 1e-06 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 0.0002122724 +3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 0.0002122724 +4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 0.0001559235 +5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 0.0001559235 +6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 0.0001701273 +7 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 0.0001701273 +8 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:8 0.000144445 +9 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:9 0.000144445 +10 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:10 6.35597e-05 +11 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:11 6.35597e-05 +12 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 chanx_left_in[10]:12 6.871285e-05 +13 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 chanx_left_in[10]:13 6.871285e-05 + +*RES +0 mem_top_track_30\/FTB_22__27:X mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:11 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:10 0.0005379464 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:10 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:8 0.002044643 +4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 0.003205357 +5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 0.0045 +6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 0.0045 +7 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 0.002348214 +8 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 0.002645089 +9 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[2] 0.001762948 //LENGTH 15.000 LUMPCC 0 DR + +*CONN +*I mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 66.085 44.880 +*I mux_top_track_6\/mux_l3_in_0_:S I *L 0.00357 *C 64.300 46.920 +*I mem_top_track_6\/FTB_6__11:A I *L 0.001746 *C 69.920 53.040 +*N mux_tree_tapbuf_size5_1_sram[2]:3 *C 69.883 53.040 +*N mux_tree_tapbuf_size5_1_sram[2]:4 *C 65.825 53.040 +*N mux_tree_tapbuf_size5_1_sram[2]:5 *C 65.780 52.995 +*N mux_tree_tapbuf_size5_1_sram[2]:6 *C 64.338 46.920 +*N mux_tree_tapbuf_size5_1_sram[2]:7 *C 65.735 46.920 +*N mux_tree_tapbuf_size5_1_sram[2]:8 *C 65.780 46.920 +*N mux_tree_tapbuf_size5_1_sram[2]:9 *C 65.780 44.925 +*N mux_tree_tapbuf_size5_1_sram[2]:10 *C 65.780 44.880 +*N mux_tree_tapbuf_size5_1_sram[2]:11 *C 66.085 44.880 + +*CAP +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_6\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_6\/FTB_6__11:A 1e-06 +3 mux_tree_tapbuf_size5_1_sram[2]:3 0.0002685444 +4 mux_tree_tapbuf_size5_1_sram[2]:4 0.0002685444 +5 mux_tree_tapbuf_size5_1_sram[2]:5 0.0003129021 +6 mux_tree_tapbuf_size5_1_sram[2]:6 0.0001177502 +7 mux_tree_tapbuf_size5_1_sram[2]:7 0.0001177502 +8 mux_tree_tapbuf_size5_1_sram[2]:8 0.000461956 +9 mux_tree_tapbuf_size5_1_sram[2]:9 0.0001163563 +10 mux_tree_tapbuf_size5_1_sram[2]:10 5.155915e-05 +11 mux_tree_tapbuf_size5_1_sram[2]:11 4.458555e-05 + +*RES +0 mem_top_track_6\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_1_sram[2]:11 0.152 +1 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:9 0.0045 +2 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:8 0.00178125 +3 mux_tree_tapbuf_size5_1_sram[2]:11 mux_tree_tapbuf_size5_1_sram[2]:10 0.0001657609 +4 mux_tree_tapbuf_size5_1_sram[2]:7 mux_tree_tapbuf_size5_1_sram[2]:6 0.001247768 +5 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:5 0.005424107 +7 mux_tree_tapbuf_size5_1_sram[2]:6 mux_top_track_6\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size5_1_sram[2]:4 mux_tree_tapbuf_size5_1_sram[2]:3 0.003622768 +9 mux_tree_tapbuf_size5_1_sram[2]:5 mux_tree_tapbuf_size5_1_sram[2]:4 0.0045 +10 mux_tree_tapbuf_size5_1_sram[2]:3 mem_top_track_6\/FTB_6__11:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.003202989 //LENGTH 26.295 LUMPCC 0 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 96.445 77.520 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 90.795 71.740 +*I mux_top_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 85.920 69.360 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 86.380 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 86.365 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 86.043 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 86.020 77.475 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 85.920 69.360 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 86.020 69.405 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 86.020 71.740 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 86.065 71.740 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 90.795 71.740 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 95.635 71.740 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 95.680 71.785 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 95.680 77.475 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 95.725 77.520 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 96.407 77.520 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_top_track_0\/mux_l2_in_1_:S 1e-06 +3 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 6.823956e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 6.823956e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 0.0003348473 +7 mux_tree_tapbuf_size6_0_sram[1]:7 2.794213e-05 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.0001386997 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.0005044035 +10 mux_tree_tapbuf_size6_0_sram[1]:10 0.0003177975 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0006561809 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0003066171 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0003076193 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.0003076193 +15 mux_tree_tapbuf_size6_0_sram[1]:15 8.039174e-05 +16 mux_tree_tapbuf_size6_0_sram[1]:16 8.039174e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:11 0.004321429 +2 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0045 +3 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.005080357 +5 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.000609375 +6 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.0045 +7 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:8 0.002084822 +8 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:6 0.005120536 +9 mux_tree_tapbuf_size6_0_sram[1]:11 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.004223214 +11 mux_tree_tapbuf_size6_0_sram[1]:7 mux_top_track_0\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.0045 +13 mux_tree_tapbuf_size6_0_sram[1]:4 mux_top_track_0\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size6_0_sram[1]:5 mux_tree_tapbuf_size6_0_sram[1]:4 0.0001752718 +15 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0045 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004995666 //LENGTH 4.245 LUMPCC 7.827526e-05 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_2_:X O *L 0 *C 81.245 69.020 +*I mux_top_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 85.200 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 85.163 69.020 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 81.282 69.020 + +*CAP +0 mux_top_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002096457 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002096457 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 optlc_net_108:46 3.913763e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 optlc_net_108:47 3.913763e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.003464286 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001695342 //LENGTH 12.430 LUMPCC 0.0004503136 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 12.135 41.820 +*I mux_left_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 13.245 36.380 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 13.208 36.380 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 9.705 36.380 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 9.660 36.425 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 9.660 41.775 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 9.705 41.820 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 12.098 41.820 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002776087 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002776087 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002343286 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002343286 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000109577 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000109577 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size6_2_sram[1]:9 8.54193e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size6_2_sram[1]:10 8.54193e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_2_sram[1]:11 5.062727e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size6_2_sram[1]:12 1.118055e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_2_sram[1]:8 5.062727e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_2_sram[1]:11 1.118055e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_107:12 7.792967e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 optlc_net_107:11 7.792967e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002136161 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.004776786 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003127232 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001006413 //LENGTH 8.495 LUMPCC 0.000134097 DR + +*CONN +*I mux_top_track_6\/mux_l1_in_0_:X O *L 0 *C 57.325 52.700 +*I mux_top_track_6\/mux_l2_in_0_:A1 I *L 0.00198 *C 57.500 47.260 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 57.500 47.260 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 57.500 47.940 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 58.375 47.940 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 58.420 47.985 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 58.420 52.655 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 58.375 52.700 +*N mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 57.363 52.700 + +*CAP +0 mux_top_track_6\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_6\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.888349e-05 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001193082 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.939016e-05 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002094377 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002094377 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 9.192945e-05 +8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 9.192945e-05 +9 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chanx_left_in[19]:5 6.295021e-06 +10 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[19]:5 6.075349e-05 +11 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[19]:4 6.075349e-05 +12 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[19]:4 6.295021e-06 + +*RES +0 mux_top_track_6\/mux_l1_in_0_:X mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_6\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.00078125 +3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.004169643 +6 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0009040179 +7 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_6/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000607143 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00388566 //LENGTH 25.155 LUMPCC 0.001279119 DR + +*CONN +*I mux_left_track_7\/mux_l3_in_0_:X O *L 0 *C 26.395 55.495 +*I mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.150 53.215 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 5.150 53.215 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 10.075 53.380 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 10.120 53.425 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 10.120 55.703 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 10.128 55.760 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 15.633 55.760 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 15.640 55.760 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 15.640 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 15.685 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 26.395 55.495 + +*CAP +0 mux_left_track_7\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003305989 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002983765 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001542627 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001542627 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001388204 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001388204 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.489622e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.100119e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0006139045 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0006695971 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[1]:10 0.0003239348 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[1]:11 0.0003239348 +14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 chanx_left_in[1]:10 5.982402e-06 +15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 chanx_left_in[1]:11 5.982402e-06 +16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[2]:8 0.0001315548 +17 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[2] 0.0001315548 +18 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:7 3.662416e-05 +19 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size5_mem_2_ccff_tail[0]:6 3.662416e-05 +20 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size6_3_sram[0]:5 0.0001159652 +21 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_tree_tapbuf_size6_3_sram[0]:24 2.549824e-05 +22 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size6_3_sram[0]:6 0.0001159652 +23 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_tree_tapbuf_size6_3_sram[0]:23 2.549824e-05 + +*RES +0 mux_left_track_7\/mux_l3_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.009562501 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001634615 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.00086245 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002033482 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.004397321 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0] 0.004744385 //LENGTH 34.485 LUMPCC 0.001059351 DR + +*CONN +*I mux_top_track_22\/mux_l1_in_0_:X O *L 0 *C 62.845 85.340 +*I mux_top_track_22\/mux_l2_in_0_:A1 I *L 0.00198 *C 90.260 90.780 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 90.223 90.780 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 89.285 90.780 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 89.240 90.735 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 89.240 87.778 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 89.233 87.720 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 67.168 87.720 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 67.160 87.663 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 67.160 85.385 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 67.115 85.340 +*N mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 62.883 85.340 + +*CAP +0 mux_top_track_22\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_22\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.133446e-05 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.133446e-05 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001770854 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001770854 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001177112 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.001177112 +8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001276511 +9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001276511 +10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0002683349 +11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0002683349 +12 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_6_sram[0]:12 0.0001129515 +13 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_6_sram[0]:13 2.316092e-05 +14 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_6_sram[0]:7 0.0001129515 +15 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_6_sram[0]:12 2.316092e-05 +16 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size2_6_sram[0]:4 2.961019e-05 +17 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_tree_tapbuf_size2_6_sram[0]:3 2.961019e-05 +18 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002911902 +19 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002911902 +20 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_6/BUF_net_42:3 7.276254e-05 +21 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_6/BUF_net_42:4 7.276254e-05 + +*RES +0 mux_top_track_22\/mux_l1_in_0_:X mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_22\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002640625 +5 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00345685 +8 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.002033482 +10 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_top_track_22/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.003779018 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.006159464 //LENGTH 56.580 LUMPCC 0.0006665573 DR + +*CONN +*I mux_left_track_13\/mux_l2_in_0_:X O *L 0 *C 7.535 69.020 +*I mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.230 26.025 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 5.230 26.062 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 5.230 26.520 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 1.425 26.520 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 1.380 26.565 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 1.380 38.760 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 1.840 38.760 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 1.840 42.840 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 0.920 42.840 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 0.920 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 1.380 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 1.425 69.020 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 7.498 69.020 + +*CAP +0 mux_left_track_13\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.848608e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002887748 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002502888 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004800219 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005081555 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002586938 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0002816963 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.001305226 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001286377 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.26758e-05 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0003652557 +13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0003652557 +14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 left_bottom_grid_pin_1_[0]:13 9.649436e-06 +15 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_bottom_grid_pin_1_[0] 1.07393e-05 +16 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_bottom_grid_pin_1_[0]:13 0.0002395301 +17 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 left_bottom_grid_pin_1_[0]:14 9.649436e-06 +18 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 left_bottom_grid_pin_1_[0]:12 0.0002395301 +19 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 left_bottom_grid_pin_1_[0]:14 1.07393e-05 +20 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 7.335986e-05 +21 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 7.335986e-05 + +*RES +0 mux_left_track_13\/mux_l2_in_0_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.005421875 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0045 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0004107143 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.003397322 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004084822 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0008214285 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.023375 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.003642857 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.01088839 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004107143 + +*END + +*D_NET chanx_left_out[19] 0.001015112 //LENGTH 6.520 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 7.035 58.140 +*P chanx_left_out[19] O *L 0.7423 *C 1.305 58.480 +*N chanx_left_out[19]:2 *C 1.833 58.480 +*N chanx_left_out[19]:3 *C 1.840 58.480 +*N chanx_left_out[19]:4 *C 1.840 58.140 +*N chanx_left_out[19]:5 *C 1.885 58.140 +*N chanx_left_out[19]:6 *C 6.998 58.140 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 chanx_left_out[19] 8.218754e-05 +2 chanx_left_out[19]:2 8.218754e-05 +3 chanx_left_out[19]:3 5.783248e-05 +4 chanx_left_out[19]:4 5.540102e-05 +5 chanx_left_out[19]:5 0.0003682517 +6 chanx_left_out[19]:6 0.0003682517 + +*RES +0 ropt_mt_inst_732:X chanx_left_out[19]:6 0.152 +1 chanx_left_out[19]:3 chanx_left_out[19]:2 0.00341 +2 chanx_left_out[19]:2 chanx_left_out[19] 8.264167e-05 +3 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0045 +4 chanx_left_out[19]:4 chanx_left_out[19]:3 0.0001634615 +5 chanx_left_out[19]:6 chanx_left_out[19]:5 0.004564732 + +*END + +*D_NET chanx_left_out[15] 0.000977113 //LENGTH 7.360 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 7.095 40.120 +*P chanx_left_out[15] O *L 0.7423 *C 1.230 39.440 +*N chanx_left_out[15]:2 *C 2.292 39.440 +*N chanx_left_out[15]:3 *C 2.300 39.498 +*N chanx_left_out[15]:4 *C 2.300 40.075 +*N chanx_left_out[15]:5 *C 2.345 40.120 +*N chanx_left_out[15]:6 *C 7.058 40.120 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 chanx_left_out[15] 9.960115e-05 +2 chanx_left_out[15]:2 9.960115e-05 +3 chanx_left_out[15]:3 5.863468e-05 +4 chanx_left_out[15]:4 5.863468e-05 +5 chanx_left_out[15]:5 0.0003298207 +6 chanx_left_out[15]:6 0.0003298207 + +*RES +0 ropt_mt_inst_739:X chanx_left_out[15]:6 0.152 +1 chanx_left_out[15]:6 chanx_left_out[15]:5 0.00420759 +2 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +3 chanx_left_out[15]:4 chanx_left_out[15]:3 0.0005156251 +4 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +5 chanx_left_out[15]:2 chanx_left_out[15] 0.0001664583 + +*END + +*D_NET ropt_net_115 0.002716472 //LENGTH 17.675 LUMPCC 0.001217659 DR + +*CONN +*I BUFT_P_83:X O *L 0 *C 16.560 28.900 +*I ropt_mt_inst_722:A I *L 0.001766 *C 7.820 34.000 +*N ropt_net_115:2 *C 7.783 34.000 +*N ropt_net_115:3 *C 7.360 34.000 +*N ropt_net_115:4 *C 7.360 34.340 +*N ropt_net_115:5 *C 8.695 34.340 +*N ropt_net_115:6 *C 8.740 34.295 +*N ropt_net_115:7 *C 8.740 30.658 +*N ropt_net_115:8 *C 8.748 30.600 +*N ropt_net_115:9 *C 14.713 30.600 +*N ropt_net_115:10 *C 14.720 30.543 +*N ropt_net_115:11 *C 14.720 29.285 +*N ropt_net_115:12 *C 14.740 29.233 +*N ropt_net_115:13 *C 15.048 29.240 +*N ropt_net_115:14 *C 15.070 28.900 +*N ropt_net_115:15 *C 16.523 28.900 + +*CAP +0 BUFT_P_83:X 1e-06 +1 ropt_mt_inst_722:A 1e-06 +2 ropt_net_115:2 2.154651e-06 +3 ropt_net_115:3 2.849118e-05 +4 ropt_net_115:4 7.799396e-05 +5 ropt_net_115:5 5.165743e-05 +6 ropt_net_115:6 0.0002008819 +7 ropt_net_115:7 0.0002008819 +8 ropt_net_115:8 0.0001724741 +9 ropt_net_115:9 0.0001724741 +10 ropt_net_115:10 0.0001079122 +11 ropt_net_115:11 0.0001079122 +12 ropt_net_115:12 4.948237e-05 +13 ropt_net_115:13 7.744041e-05 +14 ropt_net_115:14 0.0001375076 +15 ropt_net_115:15 0.0001095496 +16 ropt_net_115:5 ropt_net_129:7 5.952378e-05 +17 ropt_net_115:2 ropt_net_129:7 6.984061e-06 +18 ropt_net_115:3 ropt_net_129:6 6.984061e-06 +19 ropt_net_115:4 ropt_net_129:6 5.952378e-05 +20 ropt_net_115:11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.01578e-06 +21 ropt_net_115:10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.01578e-06 +22 ropt_net_115:9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003314913 +23 ropt_net_115:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.487846e-05 +24 ropt_net_115:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003314913 +25 ropt_net_115:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.487846e-05 +26 ropt_net_115:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001486686 +27 ropt_net_115:8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001486686 +28 ropt_net_115:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.362736e-05 +29 ropt_net_115:2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.16401e-05 +30 ropt_net_115:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.16401e-05 +31 ropt_net_115:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.362736e-05 + +*RES +0 BUFT_P_83:X ropt_net_115:15 0.152 +1 ropt_net_115:12 ropt_net_115:11 0.0045 +2 ropt_net_115:11 ropt_net_115:10 0.001122768 +3 ropt_net_115:10 ropt_net_115:9 0.00341 +4 ropt_net_115:9 ropt_net_115:8 0.0009345167 +5 ropt_net_115:7 ropt_net_115:6 0.003247768 +6 ropt_net_115:8 ropt_net_115:7 0.00341 +7 ropt_net_115:5 ropt_net_115:4 0.001191964 +8 ropt_net_115:6 ropt_net_115:5 0.0045 +9 ropt_net_115:2 ropt_mt_inst_722:A 0.152 +10 ropt_net_115:15 ropt_net_115:14 0.001296875 +11 ropt_net_115:3 ropt_net_115:2 0.0003772322 +12 ropt_net_115:4 ropt_net_115:3 0.0003035715 +13 ropt_net_115:13 ropt_net_115:12 0.0001568878 +14 ropt_net_115:14 ropt_net_115:13 0.0003035715 + +*END + +*D_NET chany_top_in[14] 0.008913522 //LENGTH 69.990 LUMPCC 0.0005271538 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 54.740 102.035 +*I mux_left_track_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 18.860 72.420 +*N chany_top_in[14]:2 *C 18.898 72.420 +*N chany_top_in[14]:3 *C 20.700 72.420 +*N chany_top_in[14]:4 *C 20.700 72.760 +*N chany_top_in[14]:5 *C 28.935 72.760 +*N chany_top_in[14]:6 *C 28.980 72.760 +*N chany_top_in[14]:7 *C 29.440 72.760 +*N chany_top_in[14]:8 *C 29.440 75.422 +*N chany_top_in[14]:9 *C 29.448 75.480 +*N chany_top_in[14]:10 *C 34.940 75.480 +*N chany_top_in[14]:11 *C 34.960 75.487 +*N chany_top_in[14]:12 *C 34.960 101.312 +*N chany_top_in[14]:13 *C 34.960 101.325 +*N chany_top_in[14]:14 *C 34.960 102.000 +*N chany_top_in[14]:15 *C 51.520 102.000 +*N chany_top_in[14]:16 *C 51.520 101.320 +*N chany_top_in[14]:17 *C 54.733 101.320 +*N chany_top_in[14]:18 *C 54.740 101.378 + +*CAP +0 chany_top_in[14] 4.895293e-05 +1 mux_left_track_13\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[14]:2 0.0001581692 +3 chany_top_in[14]:3 0.0001822954 +4 chany_top_in[14]:4 0.0006123094 +5 chany_top_in[14]:5 0.0005881832 +6 chany_top_in[14]:6 6.734223e-05 +7 chany_top_in[14]:7 0.0001541507 +8 chany_top_in[14]:8 0.0001213616 +9 chany_top_in[14]:9 0.00037813 +10 chany_top_in[14]:10 0.00037813 +11 chany_top_in[14]:11 0.001523171 +12 chany_top_in[14]:12 0.001523171 +13 chany_top_in[14]:13 5.691523e-05 +14 chany_top_in[14]:14 0.0008921697 +15 chany_top_in[14]:15 0.0008887299 +16 chany_top_in[14]:16 0.000408354 +17 chany_top_in[14]:17 0.0003548786 +18 chany_top_in[14]:18 4.895293e-05 +19 chany_top_in[14]:5 prog_clk[0]:398 4.069022e-07 +20 chany_top_in[14]:6 prog_clk[0]:464 3.280371e-06 +21 chany_top_in[14]:8 prog_clk[0]:466 7.457883e-05 +22 chany_top_in[14]:9 prog_clk[0]:249 3.882849e-05 +23 chany_top_in[14]:10 prog_clk[0]:248 3.882849e-05 +24 chany_top_in[14]:17 prog_clk[0]:151 2.612567e-07 +25 chany_top_in[14]:17 prog_clk[0]:156 1.551707e-06 +26 chany_top_in[14]:4 prog_clk[0]:397 4.069022e-07 +27 chany_top_in[14]:7 prog_clk[0]:465 7.785921e-05 +28 chany_top_in[14]:14 prog_clk[0]:167 3.085414e-05 +29 chany_top_in[14]:14 prog_clk[0]:171 4.876567e-05 +30 chany_top_in[14]:14 prog_clk[0]:172 6.504958e-05 +31 chany_top_in[14]:15 prog_clk[0]:156 3.085414e-05 +32 chany_top_in[14]:15 prog_clk[0]:167 4.876567e-05 +33 chany_top_in[14]:15 prog_clk[0]:171 6.504958e-05 +34 chany_top_in[14]:16 prog_clk[0]:156 2.612567e-07 +35 chany_top_in[14]:16 prog_clk[0]:167 1.551707e-06 + +*RES +0 chany_top_in[14] chany_top_in[14]:18 0.0005870535 +1 chany_top_in[14]:2 mux_left_track_13\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[14]:5 chany_top_in[14]:4 0.007352679 +3 chany_top_in[14]:6 chany_top_in[14]:5 0.0045 +4 chany_top_in[14]:8 chany_top_in[14]:7 0.002377232 +5 chany_top_in[14]:9 chany_top_in[14]:8 0.00341 +6 chany_top_in[14]:10 chany_top_in[14]:9 0.0008604917 +7 chany_top_in[14]:11 chany_top_in[14]:10 0.00341 +8 chany_top_in[14]:13 chany_top_in[14]:12 0.00341 +9 chany_top_in[14]:12 chany_top_in[14]:11 0.004045916 +10 chany_top_in[14]:18 chany_top_in[14]:17 0.00341 +11 chany_top_in[14]:17 chany_top_in[14]:16 0.0005032916 +12 chany_top_in[14]:3 chany_top_in[14]:2 0.001609375 +13 chany_top_in[14]:4 chany_top_in[14]:3 0.0003035715 +14 chany_top_in[14]:7 chany_top_in[14]:6 0.0004107143 +15 chany_top_in[14]:14 chany_top_in[14]:13 0.00010575 +16 chany_top_in[14]:15 chany_top_in[14]:14 0.0025944 +17 chany_top_in[14]:16 chany_top_in[14]:15 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_7_ccff_tail[0] 0.001058542 //LENGTH 8.420 LUMPCC 0 DR + +*CONN +*I mem_top_track_26\/FTB_20__25:X O *L 0 *C 47.605 97.240 +*I mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 41.575 98.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 *C 41.613 98.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 *C 47.335 98.940 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 *C 47.380 98.895 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 *C 47.380 97.285 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 *C 47.380 97.240 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 *C 47.605 97.240 + +*CAP +0 mem_top_track_26\/FTB_20__25:X 1e-06 +1 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 0.0003569697 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 0.0003569697 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.0001087763 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.0001087763 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 6.11537e-05 +7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 6.389617e-05 + +*RES +0 mem_top_track_26\/FTB_20__25:X mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 0.005109375 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 mem_top_track_28\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[1] 0.001613971 //LENGTH 12.735 LUMPCC 0.000104203 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.125 34.000 +*I mem_left_track_25\/FTB_12__17:A I *L 0.001746 *C 51.520 36.720 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 44.720 36.720 +*N mux_tree_tapbuf_size3_3_sram[1]:3 *C 44.758 36.720 +*N mux_tree_tapbuf_size3_3_sram[1]:4 *C 51.520 36.720 +*N mux_tree_tapbuf_size3_3_sram[1]:5 *C 53.775 36.720 +*N mux_tree_tapbuf_size3_3_sram[1]:6 *C 53.820 36.675 +*N mux_tree_tapbuf_size3_3_sram[1]:7 *C 53.820 34.045 +*N mux_tree_tapbuf_size3_3_sram[1]:8 *C 53.820 34.000 +*N mux_tree_tapbuf_size3_3_sram[1]:9 *C 54.125 34.000 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_25\/FTB_12__17:A 1e-06 +2 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_3_sram[1]:3 0.0004225524 +4 mux_tree_tapbuf_size3_3_sram[1]:4 0.0005717977 +5 mux_tree_tapbuf_size3_3_sram[1]:5 0.0001232722 +6 mux_tree_tapbuf_size3_3_sram[1]:6 0.0001507038 +7 mux_tree_tapbuf_size3_3_sram[1]:7 0.0001507038 +8 mux_tree_tapbuf_size3_3_sram[1]:8 4.589678e-05 +9 mux_tree_tapbuf_size3_3_sram[1]:9 4.184151e-05 +10 mux_tree_tapbuf_size3_3_sram[1]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.21015e-05 +11 mux_tree_tapbuf_size3_3_sram[1]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.21015e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_3_sram[1]:9 0.152 +1 mux_tree_tapbuf_size3_3_sram[1]:5 mux_tree_tapbuf_size3_3_sram[1]:4 0.002013393 +2 mux_tree_tapbuf_size3_3_sram[1]:6 mux_tree_tapbuf_size3_3_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size3_3_sram[1]:8 mux_tree_tapbuf_size3_3_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size3_3_sram[1]:7 mux_tree_tapbuf_size3_3_sram[1]:6 0.002348214 +5 mux_tree_tapbuf_size3_3_sram[1]:9 mux_tree_tapbuf_size3_3_sram[1]:8 0.0001657609 +6 mux_tree_tapbuf_size3_3_sram[1]:3 mux_left_track_25\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size3_3_sram[1]:4 mem_left_track_25\/FTB_12__17:A 0.152 +8 mux_tree_tapbuf_size3_3_sram[1]:4 mux_tree_tapbuf_size3_3_sram[1]:3 0.006037947 + +*END + +*D_NET mux_tree_tapbuf_size5_3_sram[1] 0.0033977 //LENGTH 26.570 LUMPCC 0 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 41.245 58.480 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.375 55.420 +*I mux_left_track_7\/mux_l2_in_1_:S I *L 0.00357 *C 29.540 58.480 +*I mux_left_track_7\/mux_l2_in_0_:S I *L 0.00357 *C 27.240 61.200 +*N mux_tree_tapbuf_size5_3_sram[1]:4 *C 27.277 61.200 +*N mux_tree_tapbuf_size5_3_sram[1]:5 *C 31.235 61.200 +*N mux_tree_tapbuf_size5_3_sram[1]:6 *C 31.280 61.155 +*N mux_tree_tapbuf_size5_3_sram[1]:7 *C 29.578 58.480 +*N mux_tree_tapbuf_size5_3_sram[1]:8 *C 31.235 58.480 +*N mux_tree_tapbuf_size5_3_sram[1]:9 *C 31.280 58.480 +*N mux_tree_tapbuf_size5_3_sram[1]:10 *C 31.740 58.480 +*N mux_tree_tapbuf_size5_3_sram[1]:11 *C 31.740 55.465 +*N mux_tree_tapbuf_size5_3_sram[1]:12 *C 31.785 55.420 +*N mux_tree_tapbuf_size5_3_sram[1]:13 *C 32.375 55.420 +*N mux_tree_tapbuf_size5_3_sram[1]:14 *C 40.895 55.420 +*N mux_tree_tapbuf_size5_3_sram[1]:15 *C 40.940 55.465 +*N mux_tree_tapbuf_size5_3_sram[1]:16 *C 40.940 58.435 +*N mux_tree_tapbuf_size5_3_sram[1]:17 *C 40.940 58.480 +*N mux_tree_tapbuf_size5_3_sram[1]:18 *C 41.245 58.480 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_7\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_7\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_3_sram[1]:4 0.0002744924 +5 mux_tree_tapbuf_size5_3_sram[1]:5 0.0002744924 +6 mux_tree_tapbuf_size5_3_sram[1]:6 0.0001891475 +7 mux_tree_tapbuf_size5_3_sram[1]:7 0.0001557509 +8 mux_tree_tapbuf_size5_3_sram[1]:8 0.0001557509 +9 mux_tree_tapbuf_size5_3_sram[1]:9 0.0002219713 +10 mux_tree_tapbuf_size5_3_sram[1]:10 0.0002258531 +11 mux_tree_tapbuf_size5_3_sram[1]:11 0.0001930293 +12 mux_tree_tapbuf_size5_3_sram[1]:12 5.021651e-05 +13 mux_tree_tapbuf_size5_3_sram[1]:13 0.0006348859 +14 mux_tree_tapbuf_size5_3_sram[1]:14 0.0005541335 +15 mux_tree_tapbuf_size5_3_sram[1]:15 0.0001857982 +16 mux_tree_tapbuf_size5_3_sram[1]:16 0.0001857982 +17 mux_tree_tapbuf_size5_3_sram[1]:17 4.829435e-05 +18 mux_tree_tapbuf_size5_3_sram[1]:18 4.408601e-05 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_3_sram[1]:18 0.152 +1 mux_tree_tapbuf_size5_3_sram[1]:12 mux_tree_tapbuf_size5_3_sram[1]:11 0.0045 +2 mux_tree_tapbuf_size5_3_sram[1]:11 mux_tree_tapbuf_size5_3_sram[1]:10 0.002691964 +3 mux_tree_tapbuf_size5_3_sram[1]:14 mux_tree_tapbuf_size5_3_sram[1]:13 0.007607143 +4 mux_tree_tapbuf_size5_3_sram[1]:15 mux_tree_tapbuf_size5_3_sram[1]:14 0.0045 +5 mux_tree_tapbuf_size5_3_sram[1]:17 mux_tree_tapbuf_size5_3_sram[1]:16 0.0045 +6 mux_tree_tapbuf_size5_3_sram[1]:16 mux_tree_tapbuf_size5_3_sram[1]:15 0.002651786 +7 mux_tree_tapbuf_size5_3_sram[1]:18 mux_tree_tapbuf_size5_3_sram[1]:17 0.0001657609 +8 mux_tree_tapbuf_size5_3_sram[1]:8 mux_tree_tapbuf_size5_3_sram[1]:7 0.001479911 +9 mux_tree_tapbuf_size5_3_sram[1]:9 mux_tree_tapbuf_size5_3_sram[1]:8 0.0045 +10 mux_tree_tapbuf_size5_3_sram[1]:9 mux_tree_tapbuf_size5_3_sram[1]:6 0.002388393 +11 mux_tree_tapbuf_size5_3_sram[1]:7 mux_left_track_7\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size5_3_sram[1]:5 mux_tree_tapbuf_size5_3_sram[1]:4 0.003533482 +13 mux_tree_tapbuf_size5_3_sram[1]:6 mux_tree_tapbuf_size5_3_sram[1]:5 0.0045 +14 mux_tree_tapbuf_size5_3_sram[1]:4 mux_left_track_7\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size5_3_sram[1]:13 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size5_3_sram[1]:13 mux_tree_tapbuf_size5_3_sram[1]:12 0.0005267857 +17 mux_tree_tapbuf_size5_3_sram[1]:10 mux_tree_tapbuf_size5_3_sram[1]:9 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[0] 0.01111077 //LENGTH 85.710 LUMPCC 0.001192858 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.745 64.260 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 36.900 52.750 +*I mux_left_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 5.880 36.720 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 4.315 44.540 +*I mux_left_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 14.160 50.320 +*N mux_tree_tapbuf_size6_2_sram[0]:5 *C 36.920 53.040 +*N mux_tree_tapbuf_size6_2_sram[0]:6 *C 14.123 50.320 +*N mux_tree_tapbuf_size6_2_sram[0]:7 *C 11.545 50.320 +*N mux_tree_tapbuf_size6_2_sram[0]:8 *C 11.500 50.275 +*N mux_tree_tapbuf_size6_2_sram[0]:9 *C 4.353 44.540 +*N mux_tree_tapbuf_size6_2_sram[0]:10 *C 5.865 36.720 +*N mux_tree_tapbuf_size6_2_sram[0]:11 *C 5.543 36.720 +*N mux_tree_tapbuf_size6_2_sram[0]:12 *C 5.520 36.765 +*N mux_tree_tapbuf_size6_2_sram[0]:13 *C 5.520 42.500 +*N mux_tree_tapbuf_size6_2_sram[0]:14 *C 5.060 42.500 +*N mux_tree_tapbuf_size6_2_sram[0]:15 *C 5.060 44.495 +*N mux_tree_tapbuf_size6_2_sram[0]:16 *C 5.060 44.540 +*N mux_tree_tapbuf_size6_2_sram[0]:17 *C 5.520 44.540 +*N mux_tree_tapbuf_size6_2_sram[0]:18 *C 5.520 44.200 +*N mux_tree_tapbuf_size6_2_sram[0]:19 *C 11.455 44.200 +*N mux_tree_tapbuf_size6_2_sram[0]:20 *C 11.500 44.245 +*N mux_tree_tapbuf_size6_2_sram[0]:21 *C 11.500 48.960 +*N mux_tree_tapbuf_size6_2_sram[0]:22 *C 11.508 48.960 +*N mux_tree_tapbuf_size6_2_sram[0]:23 *C 36.793 48.960 +*N mux_tree_tapbuf_size6_2_sram[0]:24 *C 36.800 49.018 +*N mux_tree_tapbuf_size6_2_sram[0]:25 *C 36.800 52.315 +*N mux_tree_tapbuf_size6_2_sram[0]:26 *C 36.800 52.360 +*N mux_tree_tapbuf_size6_2_sram[0]:27 *C 36.900 52.750 +*N mux_tree_tapbuf_size6_2_sram[0]:28 *C 36.975 53.040 +*N mux_tree_tapbuf_size6_2_sram[0]:29 *C 50.095 53.040 +*N mux_tree_tapbuf_size6_2_sram[0]:30 *C 50.140 53.085 +*N mux_tree_tapbuf_size6_2_sram[0]:31 *C 50.140 64.215 +*N mux_tree_tapbuf_size6_2_sram[0]:32 *C 50.185 64.260 +*N mux_tree_tapbuf_size6_2_sram[0]:33 *C 52.708 64.260 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +2 mux_left_track_1\/mux_l1_in_2_:S 1e-06 +3 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_track_1\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_2_sram[0]:5 2.994885e-05 +6 mux_tree_tapbuf_size6_2_sram[0]:6 0.0001925064 +7 mux_tree_tapbuf_size6_2_sram[0]:7 0.0001925064 +8 mux_tree_tapbuf_size6_2_sram[0]:8 7.57762e-05 +9 mux_tree_tapbuf_size6_2_sram[0]:9 6.558621e-05 +10 mux_tree_tapbuf_size6_2_sram[0]:10 7.639031e-05 +11 mux_tree_tapbuf_size6_2_sram[0]:11 7.639031e-05 +12 mux_tree_tapbuf_size6_2_sram[0]:12 0.0003393437 +13 mux_tree_tapbuf_size6_2_sram[0]:13 0.0003709428 +14 mux_tree_tapbuf_size6_2_sram[0]:14 0.0001614718 +15 mux_tree_tapbuf_size6_2_sram[0]:15 0.0001298727 +16 mux_tree_tapbuf_size6_2_sram[0]:16 0.0001271485 +17 mux_tree_tapbuf_size6_2_sram[0]:17 6.696774e-05 +18 mux_tree_tapbuf_size6_2_sram[0]:18 0.0005294193 +19 mux_tree_tapbuf_size6_2_sram[0]:19 0.0005038399 +20 mux_tree_tapbuf_size6_2_sram[0]:20 0.0002587941 +21 mux_tree_tapbuf_size6_2_sram[0]:21 0.0003719774 +22 mux_tree_tapbuf_size6_2_sram[0]:22 0.001208478 +23 mux_tree_tapbuf_size6_2_sram[0]:23 0.001208478 +24 mux_tree_tapbuf_size6_2_sram[0]:24 0.0002042245 +25 mux_tree_tapbuf_size6_2_sram[0]:25 0.0002042245 +26 mux_tree_tapbuf_size6_2_sram[0]:26 6.226964e-05 +27 mux_tree_tapbuf_size6_2_sram[0]:27 0.0001031178 +28 mux_tree_tapbuf_size6_2_sram[0]:28 0.0009155672 +29 mux_tree_tapbuf_size6_2_sram[0]:29 0.0008791625 +30 mux_tree_tapbuf_size6_2_sram[0]:30 0.0006104754 +31 mux_tree_tapbuf_size6_2_sram[0]:31 0.0006104754 +32 mux_tree_tapbuf_size6_2_sram[0]:32 0.000168778 +33 mux_tree_tapbuf_size6_2_sram[0]:33 0.000168778 +34 mux_tree_tapbuf_size6_2_sram[0]:20 prog_clk[0]:433 2.517451e-06 +35 mux_tree_tapbuf_size6_2_sram[0]:8 prog_clk[0]:434 7.581967e-07 +36 mux_tree_tapbuf_size6_2_sram[0]:21 prog_clk[0]:433 7.581967e-07 +37 mux_tree_tapbuf_size6_2_sram[0]:21 prog_clk[0]:434 2.517451e-06 +38 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:313 7.040244e-05 +39 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:377 7.659566e-05 +40 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:378 0.0002139483 +41 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:431 5.889951e-05 +42 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:312 7.040244e-05 +43 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:373 0.0002139483 +44 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:378 7.659566e-05 +45 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:432 5.889951e-05 +46 mux_tree_tapbuf_size6_2_sram[0]:29 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 3.707659e-05 +47 mux_tree_tapbuf_size6_2_sram[0]:30 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 1.452389e-05 +48 mux_tree_tapbuf_size6_2_sram[0]:31 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 1.452389e-05 +49 mux_tree_tapbuf_size6_2_sram[0]:28 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 3.707659e-05 +50 mux_tree_tapbuf_size6_2_sram[0]:29 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001210715 +51 mux_tree_tapbuf_size6_2_sram[0]:30 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.355374e-07 +52 mux_tree_tapbuf_size6_2_sram[0]:31 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.355374e-07 +53 mux_tree_tapbuf_size6_2_sram[0]:28 mux_top_track_14/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001210715 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_2_sram[0]:33 0.152 +1 mux_tree_tapbuf_size6_2_sram[0]:10 mux_left_track_1\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[0]:11 mux_tree_tapbuf_size6_2_sram[0]:10 0.0001752718 +3 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size6_2_sram[0]:16 mux_tree_tapbuf_size6_2_sram[0]:15 0.0045 +5 mux_tree_tapbuf_size6_2_sram[0]:16 mux_tree_tapbuf_size6_2_sram[0]:9 0.0006316964 +6 mux_tree_tapbuf_size6_2_sram[0]:15 mux_tree_tapbuf_size6_2_sram[0]:14 0.00178125 +7 mux_tree_tapbuf_size6_2_sram[0]:19 mux_tree_tapbuf_size6_2_sram[0]:18 0.005299107 +8 mux_tree_tapbuf_size6_2_sram[0]:20 mux_tree_tapbuf_size6_2_sram[0]:19 0.0045 +9 mux_tree_tapbuf_size6_2_sram[0]:27 mux_left_track_1\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size6_2_sram[0]:27 mux_tree_tapbuf_size6_2_sram[0]:26 0.0003482143 +11 mux_tree_tapbuf_size6_2_sram[0]:27 mux_tree_tapbuf_size6_2_sram[0]:5 0.0002589286 +12 mux_tree_tapbuf_size6_2_sram[0]:7 mux_tree_tapbuf_size6_2_sram[0]:6 0.002301339 +13 mux_tree_tapbuf_size6_2_sram[0]:8 mux_tree_tapbuf_size6_2_sram[0]:7 0.0045 +14 mux_tree_tapbuf_size6_2_sram[0]:6 mux_left_track_1\/mux_l1_in_1_:S 0.152 +15 mux_tree_tapbuf_size6_2_sram[0]:29 mux_tree_tapbuf_size6_2_sram[0]:28 0.01171429 +16 mux_tree_tapbuf_size6_2_sram[0]:30 mux_tree_tapbuf_size6_2_sram[0]:29 0.0045 +17 mux_tree_tapbuf_size6_2_sram[0]:32 mux_tree_tapbuf_size6_2_sram[0]:31 0.0045 +18 mux_tree_tapbuf_size6_2_sram[0]:31 mux_tree_tapbuf_size6_2_sram[0]:30 0.009937501 +19 mux_tree_tapbuf_size6_2_sram[0]:33 mux_tree_tapbuf_size6_2_sram[0]:32 0.002252232 +20 mux_tree_tapbuf_size6_2_sram[0]:9 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +21 mux_tree_tapbuf_size6_2_sram[0]:21 mux_tree_tapbuf_size6_2_sram[0]:20 0.004209822 +22 mux_tree_tapbuf_size6_2_sram[0]:21 mux_tree_tapbuf_size6_2_sram[0]:8 0.001174107 +23 mux_tree_tapbuf_size6_2_sram[0]:22 mux_tree_tapbuf_size6_2_sram[0]:21 0.00341 +24 mux_tree_tapbuf_size6_2_sram[0]:24 mux_tree_tapbuf_size6_2_sram[0]:23 0.00341 +25 mux_tree_tapbuf_size6_2_sram[0]:23 mux_tree_tapbuf_size6_2_sram[0]:22 0.003961316 +26 mux_tree_tapbuf_size6_2_sram[0]:26 mux_tree_tapbuf_size6_2_sram[0]:25 0.0045 +27 mux_tree_tapbuf_size6_2_sram[0]:25 mux_tree_tapbuf_size6_2_sram[0]:24 0.002944197 +28 mux_tree_tapbuf_size6_2_sram[0]:17 mux_tree_tapbuf_size6_2_sram[0]:16 0.0004107143 +29 mux_tree_tapbuf_size6_2_sram[0]:18 mux_tree_tapbuf_size6_2_sram[0]:17 0.0003035715 +30 mux_tree_tapbuf_size6_2_sram[0]:28 mux_tree_tapbuf_size6_2_sram[0]:27 0.0002589286 +31 mux_tree_tapbuf_size6_2_sram[0]:14 mux_tree_tapbuf_size6_2_sram[0]:13 0.0004107143 +32 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:12 0.005120536 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007433392 //LENGTH 4.705 LUMPCC 0.0002902183 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_0_:X O *L 0 *C 54.565 61.540 +*I mux_top_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.980 61.540 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.943 61.540 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 54.602 61.540 + +*CAP +0 mux_top_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002255604 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002255604 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 top_left_grid_pin_35_[0]:11 4.82679e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 top_left_grid_pin_35_[0]:13 4.82679e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_0_sram[0]:7 8.237557e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_0_sram[0]:9 7.473605e-06 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size5_0_sram[0]:11 6.992086e-06 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_0_sram[0]:6 8.237557e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_0_sram[0]:8 7.473605e-06 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size5_0_sram[0]:10 6.992086e-06 + +*RES +0 mux_top_track_2\/mux_l1_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003875 + +*END + +*D_NET optlc_net_108 0.02176097 //LENGTH 161.070 LUMPCC 0.002469497 DR + +*CONN +*I optlc_101:HI O *L 0 *C 56.580 86.020 +*I mux_top_track_34\/mux_l2_in_0_:A0 I *L 0.001631 *C 57.215 82.620 +*I mux_top_track_38\/mux_l2_in_0_:A0 I *L 0.001631 *C 63.600 71.740 +*I mux_top_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 50.315 70.040 +*I mux_top_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 84.815 69.700 +*I mux_top_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 46.175 82.620 +*I mux_top_track_30\/mux_l2_in_0_:A0 I *L 0.005103 *C 43.700 87.565 +*I mux_top_track_28\/mux_l2_in_0_:A0 I *L 0.001631 *C 44.335 96.900 +*I mux_top_track_26\/mux_l2_in_0_:A0 I *L 0.001631 *C 53.535 96.900 +*I mux_top_track_18\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.250 91.800 +*I mux_top_track_22\/mux_l2_in_0_:A0 I *L 0.001631 *C 89.875 91.800 +*I mux_top_track_36\/mux_l2_in_0_:A0 I *L 0.005103 *C 69.460 82.110 +*I mux_top_track_20\/mux_l2_in_0_:A0 I *L 0.001631 *C 77.915 82.620 +*I mux_top_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 76.535 91.460 +*N optlc_net_108:14 *C 76.535 91.460 +*N optlc_net_108:15 *C 77.877 82.620 +*N optlc_net_108:16 *C 76.360 82.620 +*N optlc_net_108:17 *C 69.460 82.110 +*N optlc_net_108:18 *C 69.460 82.155 +*N optlc_net_108:19 *C 69.460 83.595 +*N optlc_net_108:20 *C 69.505 83.640 +*N optlc_net_108:21 *C 76.360 83.610 +*N optlc_net_108:22 *C 76.360 83.685 +*N optlc_net_108:23 *C 76.360 91.415 +*N optlc_net_108:24 *C 76.360 91.460 +*N optlc_net_108:25 *C 89.838 91.800 +*N optlc_net_108:26 *C 76.360 91.800 +*N optlc_net_108:27 *C 58.250 91.800 +*N optlc_net_108:28 *C 58.465 91.800 +*N optlc_net_108:29 *C 58.420 91.755 +*N optlc_net_108:30 *C 58.420 85.725 +*N optlc_net_108:31 *C 58.375 85.680 +*N optlc_net_108:32 *C 53.498 96.900 +*N optlc_net_108:33 *C 44.373 96.900 +*N optlc_net_108:34 *C 45.540 96.900 +*N optlc_net_108:35 *C 45.540 96.855 +*N optlc_net_108:36 *C 43.738 87.565 +*N optlc_net_108:37 *C 45.495 87.565 +*N optlc_net_108:38 *C 45.540 87.610 +*N optlc_net_108:39 *C 45.540 88.400 +*N optlc_net_108:40 *C 46.000 88.400 +*N optlc_net_108:41 *C 46.175 82.620 +*N optlc_net_108:42 *C 46.000 82.620 +*N optlc_net_108:43 *C 46.000 82.665 +*N optlc_net_108:44 *C 46.000 85.680 +*N optlc_net_108:45 *C 46.045 85.680 +*N optlc_net_108:46 *C 84.778 69.700 +*N optlc_net_108:47 *C 82.845 69.700 +*N optlc_net_108:48 *C 82.800 69.700 +*N optlc_net_108:49 *C 82.800 70.040 +*N optlc_net_108:50 *C 82.793 70.040 +*N optlc_net_108:51 *C 50.315 70.040 +*N optlc_net_108:52 *C 50.600 70.040 +*N optlc_net_108:53 *C 50.600 70.040 +*N optlc_net_108:54 *C 50.608 70.040 +*N optlc_net_108:55 *C 61.180 70.040 +*N optlc_net_108:56 *C 61.180 70.097 +*N optlc_net_108:57 *C 63.600 71.740 +*N optlc_net_108:58 *C 62.560 71.740 +*N optlc_net_108:59 *C 62.560 71.400 +*N optlc_net_108:60 *C 61.225 71.400 +*N optlc_net_108:61 *C 61.180 71.400 +*N optlc_net_108:62 *C 61.180 82.235 +*N optlc_net_108:63 *C 61.135 82.280 +*N optlc_net_108:64 *C 57.215 82.280 +*N optlc_net_108:65 *C 57.215 82.598 +*N optlc_net_108:66 *C 56.625 82.620 +*N optlc_net_108:67 *C 56.580 82.665 +*N optlc_net_108:68 *C 56.580 85.635 +*N optlc_net_108:69 *C 56.580 85.680 +*N optlc_net_108:70 *C 56.580 86.020 + +*CAP +0 optlc_101:HI 1e-06 +1 mux_top_track_34\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_38\/mux_l2_in_0_:A0 1e-06 +3 mux_top_track_16\/mux_l2_in_0_:A0 1e-06 +4 mux_top_track_0\/mux_l2_in_1_:A0 1e-06 +5 mux_top_track_32\/mux_l2_in_0_:A0 1e-06 +6 mux_top_track_30\/mux_l2_in_0_:A0 1e-06 +7 mux_top_track_28\/mux_l2_in_0_:A0 1e-06 +8 mux_top_track_26\/mux_l2_in_0_:A0 1e-06 +9 mux_top_track_18\/mux_l2_in_0_:A0 1e-06 +10 mux_top_track_22\/mux_l2_in_0_:A0 1e-06 +11 mux_top_track_36\/mux_l2_in_0_:A0 1e-06 +12 mux_top_track_20\/mux_l2_in_0_:A0 1e-06 +13 mux_top_track_24\/mux_l1_in_1_:A0 1e-06 +14 optlc_net_108:14 4.131266e-05 +15 optlc_net_108:15 0.0001128121 +16 optlc_net_108:16 0.000179141 +17 optlc_net_108:17 3.279604e-05 +18 optlc_net_108:18 0.0001068772 +19 optlc_net_108:19 0.0001068772 +20 optlc_net_108:20 0.000511047 +21 optlc_net_108:21 0.0005773759 +22 optlc_net_108:22 0.0005186538 +23 optlc_net_108:23 0.0005186538 +24 optlc_net_108:24 6.572373e-05 +25 optlc_net_108:25 0.0008955988 +26 optlc_net_108:26 0.002091321 +27 optlc_net_108:27 5.238385e-05 +28 optlc_net_108:28 0.001199083 +29 optlc_net_108:29 0.0004245849 +30 optlc_net_108:30 0.0004245849 +31 optlc_net_108:31 0.0001199203 +32 optlc_net_108:32 0.0004378968 +33 optlc_net_108:33 8.040067e-05 +34 optlc_net_108:34 0.0005508294 +35 optlc_net_108:35 0.0003773727 +36 optlc_net_108:36 0.0001873963 +37 optlc_net_108:37 0.0001873963 +38 optlc_net_108:38 3.330021e-05 +39 optlc_net_108:39 0.0004407563 +40 optlc_net_108:40 0.0001609709 +41 optlc_net_108:41 4.849109e-05 +42 optlc_net_108:42 5.275163e-05 +43 optlc_net_108:43 0.0001447075 +44 optlc_net_108:44 0.0003058795 +45 optlc_net_108:45 0.0005948078 +46 optlc_net_108:46 0.0001002241 +47 optlc_net_108:47 0.0001002241 +48 optlc_net_108:48 4.845284e-05 +49 optlc_net_108:49 5.182475e-05 +50 optlc_net_108:50 0.001171177 +51 optlc_net_108:51 4.928416e-05 +52 optlc_net_108:52 5.523502e-05 +53 optlc_net_108:53 3.648083e-05 +54 optlc_net_108:54 0.000532142 +55 optlc_net_108:55 0.001703319 +56 optlc_net_108:56 6.760752e-05 +57 optlc_net_108:57 0.0001278607 +58 optlc_net_108:58 0.0001085769 +59 optlc_net_108:59 0.0001256668 +60 optlc_net_108:60 9.932969e-05 +61 optlc_net_108:61 0.0007054468 +62 optlc_net_108:62 0.0006062965 +63 optlc_net_108:63 0.0002926961 +64 optlc_net_108:64 0.0003232646 +65 optlc_net_108:65 9.322965e-05 +66 optlc_net_108:66 6.266117e-05 +67 optlc_net_108:67 0.0002046055 +68 optlc_net_108:68 0.0002046055 +69 optlc_net_108:69 0.0007545061 +70 optlc_net_108:70 7.105649e-05 +71 optlc_net_108:55 prog_clk[0]:202 9.707629e-06 +72 optlc_net_108:55 prog_clk[0]:209 6.680021e-05 +73 optlc_net_108:30 prog_clk[0]:154 2.803549e-07 +74 optlc_net_108:28 prog_clk[0]:144 4.500589e-05 +75 optlc_net_108:29 prog_clk[0]:155 2.803549e-07 +76 optlc_net_108:35 prog_clk[0]:165 7.304313e-05 +77 optlc_net_108:35 prog_clk[0]:166 8.374578e-05 +78 optlc_net_108:50 prog_clk[0]:201 9.707629e-06 +79 optlc_net_108:50 prog_clk[0]:208 6.680021e-05 +80 optlc_net_108:26 prog_clk[0]:143 4.500589e-05 +81 optlc_net_108:39 prog_clk[0]:159 7.304313e-05 +82 optlc_net_108:39 prog_clk[0]:165 8.374578e-05 +83 optlc_net_108:55 chany_top_in[17]:6 0.0003718095 +84 optlc_net_108:55 chany_top_in[17]:7 0.0001938291 +85 optlc_net_108:50 chany_top_in[17]:7 0.0003718095 +86 optlc_net_108:54 chany_top_in[17]:6 0.0001938291 +87 optlc_net_108:32 mux_tree_tapbuf_size2_7_sram[1]:4 0.0001035688 +88 optlc_net_108:34 mux_tree_tapbuf_size2_7_sram[1]:3 0.0001035688 +89 optlc_net_108:55 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 7.384837e-05 +90 optlc_net_108:54 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 7.384837e-05 +91 optlc_net_108:38 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 9.140816e-07 +92 optlc_net_108:43 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 3.601386e-05 +93 optlc_net_108:44 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 3.601386e-05 +94 optlc_net_108:44 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 3.399182e-05 +95 optlc_net_108:35 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 2.657775e-06 +96 optlc_net_108:39 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 9.140816e-07 +97 optlc_net_108:39 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 2.657775e-06 +98 optlc_net_108:40 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 3.399182e-05 +99 optlc_net_108:47 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 3.913763e-05 +100 optlc_net_108:46 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.913763e-05 +101 optlc_net_108:23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.430885e-07 +102 optlc_net_108:22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.430885e-07 +103 optlc_net_108:25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.125669e-05 +104 optlc_net_108:26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.125669e-05 +105 optlc_net_108:60 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.964584e-06 +106 optlc_net_108:61 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.869824e-05 +107 optlc_net_108:61 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.404062e-05 +108 optlc_net_108:57 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.209119e-05 +109 optlc_net_108:56 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.869824e-05 +110 optlc_net_108:62 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.404062e-05 +111 optlc_net_108:59 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.964584e-06 +112 optlc_net_108:58 mux_top_track_38/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.209119e-05 + +*RES +0 optlc_101:HI optlc_net_108:70 0.152 +1 optlc_net_108:36 mux_top_track_30\/mux_l2_in_0_:A0 0.152 +2 optlc_net_108:37 optlc_net_108:36 0.001569197 +3 optlc_net_108:38 optlc_net_108:37 0.0045 +4 optlc_net_108:60 optlc_net_108:59 0.001191964 +5 optlc_net_108:61 optlc_net_108:60 0.0045 +6 optlc_net_108:61 optlc_net_108:56 0.001162947 +7 optlc_net_108:57 mux_top_track_38\/mux_l2_in_0_:A0 0.152 +8 optlc_net_108:56 optlc_net_108:55 0.00341 +9 optlc_net_108:55 optlc_net_108:54 0.001656358 +10 optlc_net_108:55 optlc_net_108:50 0.003385958 +11 optlc_net_108:42 optlc_net_108:41 9.510869e-05 +12 optlc_net_108:43 optlc_net_108:42 0.0045 +13 optlc_net_108:41 mux_top_track_32\/mux_l2_in_0_:A0 0.152 +14 optlc_net_108:69 optlc_net_108:68 0.0045 +15 optlc_net_108:69 optlc_net_108:45 0.00940625 +16 optlc_net_108:69 optlc_net_108:31 0.001602679 +17 optlc_net_108:68 optlc_net_108:67 0.002651786 +18 optlc_net_108:66 optlc_net_108:65 0.0005267858 +19 optlc_net_108:67 optlc_net_108:66 0.0045 +20 optlc_net_108:31 optlc_net_108:30 0.0045 +21 optlc_net_108:30 optlc_net_108:29 0.005383929 +22 optlc_net_108:28 optlc_net_108:27 0.0001168478 +23 optlc_net_108:28 optlc_net_108:26 0.01597768 +24 optlc_net_108:29 optlc_net_108:28 0.0045 +25 optlc_net_108:24 optlc_net_108:23 0.0045 +26 optlc_net_108:24 optlc_net_108:14 9.51087e-05 +27 optlc_net_108:23 optlc_net_108:22 0.006901786 +28 optlc_net_108:21 optlc_net_108:20 0.006120536 +29 optlc_net_108:21 optlc_net_108:16 0.0008839285 +30 optlc_net_108:22 optlc_net_108:21 0.0045 +31 optlc_net_108:25 mux_top_track_22\/mux_l2_in_0_:A0 0.152 +32 optlc_net_108:45 optlc_net_108:44 0.0045 +33 optlc_net_108:44 optlc_net_108:43 0.002691964 +34 optlc_net_108:44 optlc_net_108:40 0.002428572 +35 optlc_net_108:32 mux_top_track_26\/mux_l2_in_0_:A0 0.152 +36 optlc_net_108:34 optlc_net_108:33 0.001042411 +37 optlc_net_108:34 optlc_net_108:32 0.007104911 +38 optlc_net_108:35 optlc_net_108:34 0.0045 +39 optlc_net_108:65 mux_top_track_34\/mux_l2_in_0_:A0 0.152 +40 optlc_net_108:65 optlc_net_108:64 0.0002834821 +41 optlc_net_108:63 optlc_net_108:62 0.0045 +42 optlc_net_108:62 optlc_net_108:61 0.009674107 +43 optlc_net_108:33 mux_top_track_28\/mux_l2_in_0_:A0 0.152 +44 optlc_net_108:49 optlc_net_108:48 0.0001634615 +45 optlc_net_108:50 optlc_net_108:49 0.00341 +46 optlc_net_108:47 optlc_net_108:46 0.001725447 +47 optlc_net_108:48 optlc_net_108:47 0.0045 +48 optlc_net_108:46 mux_top_track_0\/mux_l2_in_1_:A0 0.152 +49 optlc_net_108:17 mux_top_track_36\/mux_l2_in_0_:A0 0.152 +50 optlc_net_108:18 optlc_net_108:17 0.0045 +51 optlc_net_108:20 optlc_net_108:19 0.0045 +52 optlc_net_108:19 optlc_net_108:18 0.001285714 +53 optlc_net_108:14 mux_top_track_24\/mux_l1_in_1_:A0 0.152 +54 optlc_net_108:15 mux_top_track_20\/mux_l2_in_0_:A0 0.152 +55 optlc_net_108:27 mux_top_track_18\/mux_l2_in_0_:A0 0.152 +56 optlc_net_108:70 optlc_net_108:69 0.0001465517 +57 optlc_net_108:53 optlc_net_108:52 0.0045 +58 optlc_net_108:54 optlc_net_108:53 0.00341 +59 optlc_net_108:52 optlc_net_108:51 0.0001548913 +60 optlc_net_108:51 mux_top_track_16\/mux_l2_in_0_:A0 0.152 +61 optlc_net_108:64 optlc_net_108:63 0.0035 +62 optlc_net_108:26 optlc_net_108:25 0.01203348 +63 optlc_net_108:26 optlc_net_108:24 0.0003035715 +64 optlc_net_108:59 optlc_net_108:58 0.0003035714 +65 optlc_net_108:58 optlc_net_108:57 0.0009285714 +66 optlc_net_108:16 optlc_net_108:15 0.001354911 +67 optlc_net_108:39 optlc_net_108:38 0.0007053572 +68 optlc_net_108:39 optlc_net_108:35 0.007549107 +69 optlc_net_108:40 optlc_net_108:39 0.0004107143 + +*END + +*D_NET mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007173413 //LENGTH 5.620 LUMPCC 0.0001195829 DR + +*CONN +*I mux_left_track_27\/mux_l1_in_0_:X O *L 0 *C 40.195 63.580 +*I mux_left_track_27\/mux_l2_in_0_:A1 I *L 0.00198 *C 34.865 63.580 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 34.903 63.580 +*N mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 40.157 63.580 + +*CAP +0 mux_left_track_27\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_27\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002978792 +3 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002978792 +4 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_21_sram[1]:6 5.979144e-05 +5 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_21_sram[1]:7 5.979144e-05 + +*RES +0 mux_left_track_27\/mux_l1_in_0_:X mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_27\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004691964 + +*END + +*D_NET ccff_tail[0] 0.001278824 //LENGTH 6.510 LUMPCC 0.0005308818 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 7.025 56.100 +*P ccff_tail[0] O *L 0.7423 *C 1.305 55.760 +*N ccff_tail[0]:2 *C 5.973 55.760 +*N ccff_tail[0]:3 *C 5.980 55.760 +*N ccff_tail[0]:4 *C 5.980 56.100 +*N ccff_tail[0]:5 *C 6.025 56.100 +*N ccff_tail[0]:6 *C 6.988 56.100 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 ccff_tail[0] 0.0002250638 +2 ccff_tail[0]:2 0.0002250638 +3 ccff_tail[0]:3 6.006445e-05 +4 ccff_tail[0]:4 5.480575e-05 +5 ccff_tail[0]:5 9.097234e-05 +6 ccff_tail[0]:6 9.097234e-05 +7 ccff_tail[0] chanx_left_in[1]:11 0.0002654409 +8 ccff_tail[0]:2 chanx_left_in[1]:10 0.0002654409 + +*RES +0 ropt_mt_inst_731:X ccff_tail[0]:6 0.152 +1 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +2 ccff_tail[0]:2 ccff_tail[0] 0.0007312417 +3 ccff_tail[0]:5 ccff_tail[0]:4 0.0045 +4 ccff_tail[0]:4 ccff_tail[0]:3 0.0001634616 +5 ccff_tail[0]:6 ccff_tail[0]:5 0.0008593749 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..32b3e2f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef @@ -0,0 +1,29884 @@ +*SPEF "1481-1998" +*DESIGN "sb_2__1_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 2.300 27.880 +chany_top_in[0] I *C 80.500 129.880 +chany_top_in[1] I *C 57.500 129.880 +chany_top_in[2] I *C 82.340 129.880 +chany_top_in[3] I *C 74.060 129.880 +chany_top_in[4] I *C 51.980 129.880 +chany_top_in[5] I *C 60.260 129.880 +chany_top_in[6] I *C 74.980 129.880 +chany_top_in[7] I *C 66.700 129.880 +chany_top_in[8] I *C 72.220 129.880 +chany_top_in[9] I *C 67.620 129.880 +chany_top_in[10] I *C 73.140 129.880 +chany_top_in[11] I *C 75.900 129.880 +chany_top_in[12] I *C 52.900 129.880 +chany_top_in[13] I *C 63.480 129.880 +chany_top_in[14] I *C 54.740 129.880 +chany_top_in[15] I *C 53.820 129.880 +chany_top_in[16] I *C 69.460 129.880 +chany_top_in[17] I *C 81.420 129.880 +chany_top_in[18] I *C 84.640 129.880 +chany_top_in[19] I *C 59.340 129.880 +top_left_grid_pin_34_[0] I *C 32.660 129.880 +top_left_grid_pin_35_[0] I *C 30.820 129.880 +top_left_grid_pin_36_[0] I *C 29.210 127.160 +top_left_grid_pin_37_[0] I *C 31.740 129.880 +top_left_grid_pin_38_[0] I *C 29.210 125.120 +top_left_grid_pin_39_[0] I *C 29.210 123.760 +top_left_grid_pin_40_[0] I *C 29.210 122.400 +top_left_grid_pin_41_[0] I *C 29.210 117.640 +top_right_grid_pin_1_[0] I *C 108.100 129.880 +chany_bottom_in[0] I *C 82.340 0.680 +chany_bottom_in[1] I *C 67.160 0.680 +chany_bottom_in[2] I *C 81.420 0.680 +chany_bottom_in[3] I *C 88.320 0.680 +chany_bottom_in[4] I *C 65.320 0.680 +chany_bottom_in[5] I *C 75.900 0.680 +chany_bottom_in[6] I *C 94.300 0.680 +chany_bottom_in[7] I *C 87.400 0.680 +chany_bottom_in[8] I *C 77.740 0.680 +chany_bottom_in[9] I *C 84.180 0.680 +chany_bottom_in[10] I *C 62.560 0.680 +chany_bottom_in[11] I *C 86.480 0.680 +chany_bottom_in[12] I *C 79.580 0.680 +chany_bottom_in[13] I *C 68.080 0.680 +chany_bottom_in[14] I *C 66.240 0.680 +chany_bottom_in[15] I *C 53.360 0.680 +chany_bottom_in[16] I *C 76.820 0.680 +chany_bottom_in[17] I *C 69.920 0.680 +chany_bottom_in[18] I *C 57.500 0.680 +chany_bottom_in[19] I *C 78.660 0.680 +bottom_right_grid_pin_1_[0] I *C 110.860 0.680 +bottom_left_grid_pin_34_[0] I *C 29.210 10.200 +bottom_left_grid_pin_35_[0] I *C 29.210 8.160 +bottom_left_grid_pin_36_[0] I *C 29.210 6.800 +bottom_left_grid_pin_37_[0] I *C 29.210 3.400 +bottom_left_grid_pin_38_[0] I *C 29.210 4.760 +bottom_left_grid_pin_39_[0] I *C 29.210 11.560 +bottom_left_grid_pin_40_[0] I *C 29.210 12.920 +bottom_left_grid_pin_41_[0] I *C 29.210 14.280 +chanx_left_in[0] I *C 0.690 76.160 +chanx_left_in[1] I *C 0.690 38.080 +chanx_left_in[2] I *C 0.690 46.240 +chanx_left_in[3] I *C 0.690 39.440 +chanx_left_in[4] I *C 0.690 85.680 +chanx_left_in[5] I *C 0.690 87.040 +chanx_left_in[6] I *C 0.690 34.000 +chanx_left_in[7] I *C 0.690 42.160 +chanx_left_in[8] I *C 0.690 43.520 +chanx_left_in[9] I *C 0.690 72.080 +chanx_left_in[10] I *C 0.690 59.160 +chanx_left_in[11] I *C 0.690 36.720 +chanx_left_in[12] I *C 0.690 97.920 +chanx_left_in[13] I *C 0.690 93.840 +chanx_left_in[14] I *C 0.690 92.480 +chanx_left_in[15] I *C 0.690 77.520 +chanx_left_in[16] I *C 0.690 51.680 +chanx_left_in[17] I *C 0.690 55.760 +chanx_left_in[18] I *C 0.690 68.000 +chanx_left_in[19] I *C 0.690 35.360 +left_top_grid_pin_42_[0] I *C 7.360 102.680 +left_top_grid_pin_43_[0] I *C 29.210 119.000 +left_top_grid_pin_44_[0] I *C 4.140 102.680 +left_top_grid_pin_45_[0] I *C 5.060 102.680 +left_top_grid_pin_46_[0] I *C 2.300 102.680 +left_top_grid_pin_47_[0] I *C 3.220 102.680 +left_top_grid_pin_48_[0] I *C 11.500 102.680 +left_top_grid_pin_49_[0] I *C 10.580 102.680 +ccff_head[0] I *C 107.640 129.880 +chany_top_out[0] O *C 76.820 129.880 +chany_top_out[1] O *C 61.180 129.880 +chany_top_out[2] O *C 77.740 129.880 +chany_top_out[3] O *C 71.300 129.880 +chany_top_out[4] O *C 98.900 129.880 +chany_top_out[5] O *C 83.720 129.880 +chany_top_out[6] O *C 70.380 129.880 +chany_top_out[7] O *C 50.140 129.880 +chany_top_out[8] O *C 68.540 129.880 +chany_top_out[9] O *C 58.420 129.880 +chany_top_out[10] O *C 96.600 129.880 +chany_top_out[11] O *C 93.840 129.880 +chany_top_out[12] O *C 79.580 129.880 +chany_top_out[13] O *C 64.400 129.880 +chany_top_out[14] O *C 97.520 129.880 +chany_top_out[15] O *C 51.060 129.880 +chany_top_out[16] O *C 86.940 129.880 +chany_top_out[17] O *C 62.100 129.880 +chany_top_out[18] O *C 95.680 129.880 +chany_top_out[19] O *C 78.660 129.880 +chany_bottom_out[0] O *C 83.260 0.680 +chany_bottom_out[1] O *C 59.800 0.680 +chany_bottom_out[2] O *C 52.440 0.680 +chany_bottom_out[3] O *C 69.000 0.680 +chany_bottom_out[4] O *C 96.600 0.680 +chany_bottom_out[5] O *C 71.760 0.680 +chany_bottom_out[6] O *C 74.980 0.680 +chany_bottom_out[7] O *C 60.720 0.680 +chany_bottom_out[8] O *C 63.480 0.680 +chany_bottom_out[9] O *C 54.280 0.680 +chany_bottom_out[10] O *C 93.380 0.680 +chany_bottom_out[11] O *C 74.060 0.680 +chany_bottom_out[12] O *C 80.500 0.680 +chany_bottom_out[13] O *C 61.640 0.680 +chany_bottom_out[14] O *C 97.520 0.680 +chany_bottom_out[15] O *C 55.200 0.680 +chany_bottom_out[16] O *C 64.400 0.680 +chany_bottom_out[17] O *C 58.880 0.680 +chany_bottom_out[18] O *C 73.140 0.680 +chany_bottom_out[19] O *C 70.840 0.680 +chanx_left_out[0] O *C 0.690 61.200 +chanx_left_out[1] O *C 0.690 81.600 +chanx_left_out[2] O *C 0.690 82.960 +chanx_left_out[3] O *C 0.690 74.800 +chanx_left_out[4] O *C 0.690 80.240 +chanx_left_out[5] O *C 0.690 47.600 +chanx_left_out[6] O *C 0.690 50.320 +chanx_left_out[7] O *C 0.690 65.960 +chanx_left_out[8] O *C 0.690 48.960 +chanx_left_out[9] O *C 0.690 69.360 +chanx_left_out[10] O *C 0.690 53.040 +chanx_left_out[11] O *C 0.690 96.560 +chanx_left_out[12] O *C 0.690 44.880 +chanx_left_out[13] O *C 0.690 99.280 +chanx_left_out[14] O *C 0.690 54.400 +chanx_left_out[15] O *C 0.690 40.800 +chanx_left_out[16] O *C 0.690 31.960 +chanx_left_out[17] O *C 0.690 88.400 +chanx_left_out[18] O *C 0.690 70.720 +chanx_left_out[19] O *C 0.690 91.120 +ccff_tail[0] O *C 0.690 64.600 +VDD I *C 56.580 65.280 +VSS I *C 56.580 65.280 + +*D_NET chany_top_in[1] 0.01407217 //LENGTH 91.275 LUMPCC 0.000937223 DR + +*CONN +*P chany_top_in[1] I *L 0.29796 *C 57.500 129.270 +*I FTB_1__0:A I *L 0.001776 *C 10.120 96.560 +*N chany_top_in[1]:2 *C 40.080 93.160 +*N chany_top_in[1]:3 *C 10.083 96.560 +*N chany_top_in[1]:4 *C 9.245 96.560 +*N chany_top_in[1]:5 *C 9.200 96.515 +*N chany_top_in[1]:6 *C 9.200 93.205 +*N chany_top_in[1]:7 *C 9.245 93.160 +*N chany_top_in[1]:8 *C 40.435 93.160 +*N chany_top_in[1]:9 *C 40.480 93.160 +*N chany_top_in[1]:10 *C 40.480 93.160 +*N chany_top_in[1]:11 *C 40.480 93.168 +*N chany_top_in[1]:12 *C 40.480 121.032 +*N chany_top_in[1]:13 *C 40.500 121.040 +*N chany_top_in[1]:14 *C 57.492 121.040 +*N chany_top_in[1]:15 *C 57.500 121.098 + +*CAP +0 chany_top_in[1] 0.0004707707 +1 FTB_1__0:A 1e-06 +2 chany_top_in[1]:2 7.724621e-05 +3 chany_top_in[1]:3 0.000101451 +4 chany_top_in[1]:4 0.000101451 +5 chany_top_in[1]:5 0.0002063396 +6 chany_top_in[1]:6 0.0002063396 +7 chany_top_in[1]:7 0.002157227 +8 chany_top_in[1]:8 0.002157227 +9 chany_top_in[1]:9 3.744927e-05 +10 chany_top_in[1]:10 7.724621e-05 +11 chany_top_in[1]:11 0.002307442 +12 chany_top_in[1]:12 0.002307442 +13 chany_top_in[1]:13 0.001227773 +14 chany_top_in[1]:14 0.001227773 +15 chany_top_in[1]:15 0.0004707707 +16 chany_top_in[1]:11 chany_top_in[3]:7 0.0002885943 +17 chany_top_in[1]:13 chany_top_in[3]:9 2.372622e-05 +18 chany_top_in[1]:12 chany_top_in[3]:8 0.0002885943 +19 chany_top_in[1]:14 chany_top_in[3]:10 2.372622e-05 +20 chany_top_in[1]:7 mux_tree_tapbuf_size7_3_sram[2]:9 0.000156291 +21 chany_top_in[1]:8 mux_tree_tapbuf_size7_3_sram[2]:10 0.000156291 + +*RES +0 chany_top_in[1] chany_top_in[1]:15 0.007296875 +1 chany_top_in[1]:3 FTB_1__0:A 0.152 +2 chany_top_in[1]:4 chany_top_in[1]:3 0.0007477679 +3 chany_top_in[1]:5 chany_top_in[1]:4 0.0045 +4 chany_top_in[1]:7 chany_top_in[1]:6 0.0045 +5 chany_top_in[1]:6 chany_top_in[1]:5 0.002955357 +6 chany_top_in[1]:8 chany_top_in[1]:7 0.02784822 +7 chany_top_in[1]:9 chany_top_in[1]:8 0.0045 +8 chany_top_in[1]:10 chany_top_in[1]:9 0.00341 +9 chany_top_in[1]:10 chany_top_in[1]:2 5.69697e-05 +10 chany_top_in[1]:11 chany_top_in[1]:10 0.00341 +11 chany_top_in[1]:13 chany_top_in[1]:12 0.00341 +12 chany_top_in[1]:12 chany_top_in[1]:11 0.004365516 +13 chany_top_in[1]:15 chany_top_in[1]:14 0.00341 +14 chany_top_in[1]:14 chany_top_in[1]:13 0.002662158 + +*END + +*D_NET chany_top_in[17] 0.02115542 //LENGTH 179.540 LUMPCC 0.003726257 DR + +*CONN +*P chany_top_in[17] I *L 0.29796 *C 81.420 129.270 +*I mux_left_track_23\/mux_l1_in_0_:A1 I *L 0.00198 *C 57.405 77.860 +*I ropt_mt_inst_777:A I *L 0.001767 *C 74.980 4.080 +*I mux_bottom_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 63.310 44.540 +*N chany_top_in[17]:4 *C 63.348 44.540 +*N chany_top_in[17]:5 *C 64.355 44.540 +*N chany_top_in[17]:6 *C 64.400 44.540 +*N chany_top_in[17]:7 *C 74.943 4.080 +*N chany_top_in[17]:8 *C 73.185 4.080 +*N chany_top_in[17]:9 *C 73.140 4.125 +*N chany_top_in[17]:10 *C 73.140 25.115 +*N chany_top_in[17]:11 *C 73.185 25.160 +*N chany_top_in[17]:12 *C 80.075 25.160 +*N chany_top_in[17]:13 *C 80.050 25.205 +*N chany_top_in[17]:14 *C 80.040 25.795 +*N chany_top_in[17]:15 *C 79.995 25.840 +*N chany_top_in[17]:16 *C 78.245 25.840 +*N chany_top_in[17]:17 *C 78.200 25.885 +*N chany_top_in[17]:18 *C 78.200 44.823 +*N chany_top_in[17]:19 *C 78.193 44.880 +*N chany_top_in[17]:20 *C 64.407 44.880 +*N chany_top_in[17]:21 *C 64.400 44.938 +*N chany_top_in[17]:22 *C 57.443 77.860 +*N chany_top_in[17]:23 *C 64.355 77.860 +*N chany_top_in[17]:24 *C 64.400 77.860 +*N chany_top_in[17]:25 *C 64.400 86.303 +*N chany_top_in[17]:26 *C 64.407 86.360 +*N chany_top_in[17]:27 *C 79.100 86.360 +*N chany_top_in[17]:28 *C 79.120 86.368 +*N chany_top_in[17]:29 *C 79.120 127.833 +*N chany_top_in[17]:30 *C 79.140 127.840 +*N chany_top_in[17]:31 *C 81.413 127.840 +*N chany_top_in[17]:32 *C 81.420 127.898 + +*CAP +0 chany_top_in[17] 0.0001037773 +1 mux_left_track_23\/mux_l1_in_0_:A1 1e-06 +2 ropt_mt_inst_777:A 1e-06 +3 mux_bottom_track_17\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[17]:4 8.043875e-05 +5 chany_top_in[17]:5 8.043875e-05 +6 chany_top_in[17]:6 4.683475e-05 +7 chany_top_in[17]:7 0.0001499699 +8 chany_top_in[17]:8 0.0001499699 +9 chany_top_in[17]:9 0.001168151 +10 chany_top_in[17]:10 0.001168151 +11 chany_top_in[17]:11 0.0004238393 +12 chany_top_in[17]:12 0.0004238393 +13 chany_top_in[17]:13 6.234917e-05 +14 chany_top_in[17]:14 6.234917e-05 +15 chany_top_in[17]:15 0.0001259573 +16 chany_top_in[17]:16 0.0001259573 +17 chany_top_in[17]:17 0.0009722296 +18 chany_top_in[17]:18 0.0009722296 +19 chany_top_in[17]:19 0.0009879491 +20 chany_top_in[17]:20 0.0009879491 +21 chany_top_in[17]:21 0.001519597 +22 chany_top_in[17]:22 0.0004245955 +23 chany_top_in[17]:23 0.0004245955 +24 chany_top_in[17]:24 0.001832438 +25 chany_top_in[17]:25 0.0003011838 +26 chany_top_in[17]:26 0.0008102575 +27 chany_top_in[17]:27 0.0008102575 +28 chany_top_in[17]:28 0.00139504 +29 chany_top_in[17]:29 0.00139504 +30 chany_top_in[17]:30 0.0001585016 +31 chany_top_in[17]:31 0.0001585016 +32 chany_top_in[17]:32 0.0001037773 +33 chany_top_in[17] chany_top_in[2] 3.309684e-06 +34 chany_top_in[17]:9 chany_top_in[2]:6 2.137094e-05 +35 chany_top_in[17]:10 chany_top_in[2]:7 2.137094e-05 +36 chany_top_in[17]:21 chany_top_in[2]:14 2.04611e-06 +37 chany_top_in[17]:21 chany_top_in[2]:15 6.128436e-07 +38 chany_top_in[17]:25 chany_top_in[2]:18 3.106402e-06 +39 chany_top_in[17]:28 chany_top_in[2]:22 0.000473999 +40 chany_top_in[17]:29 chany_top_in[2]:23 0.000473999 +41 chany_top_in[17]:32 chany_top_in[2]:26 3.309684e-06 +42 chany_top_in[17]:24 chany_top_in[2]:15 5.152512e-06 +43 chany_top_in[17]:24 chany_top_in[2]:18 6.128436e-07 +44 chany_top_in[17]:21 chany_bottom_in[8]:14 0.0003567 +45 chany_top_in[17]:25 chany_bottom_in[8]:13 0.0002316654 +46 chany_top_in[17]:24 chany_bottom_in[8]:14 0.0002316654 +47 chany_top_in[17]:24 chany_bottom_in[8]:13 0.0003567 +48 chany_top_in[17]:9 chany_bottom_in[16] 3.242907e-07 +49 chany_top_in[17]:10 chany_bottom_in[16]:29 3.242907e-07 +50 chany_top_in[17]:17 chany_bottom_in[16]:28 7.58606e-05 +51 chany_top_in[17]:18 chany_bottom_in[16]:27 7.58606e-05 +52 chany_top_in[17]:28 chany_bottom_in[16]:16 0.0002664041 +53 chany_top_in[17]:28 chany_bottom_in[16]:23 7.085694e-05 +54 chany_top_in[17]:29 chany_bottom_in[16]:9 0.0002664041 +55 chany_top_in[17]:29 chany_bottom_in[16]:16 7.085694e-05 +56 chany_top_in[17]:26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002379814 +57 chany_top_in[17]:27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002379814 +58 chany_top_in[17]:21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.533814e-05 +59 chany_top_in[17]:23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.877167e-05 +60 chany_top_in[17]:24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.533814e-05 +61 chany_top_in[17]:22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.877167e-05 +62 chany_top_in[17]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.478081e-05 +63 chany_top_in[17]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.478081e-05 + +*RES +0 chany_top_in[17] chany_top_in[17]:32 0.001225446 +1 chany_top_in[17]:7 ropt_mt_inst_777:A 0.152 +2 chany_top_in[17]:8 chany_top_in[17]:7 0.001569197 +3 chany_top_in[17]:9 chany_top_in[17]:8 0.0045 +4 chany_top_in[17]:11 chany_top_in[17]:10 0.0045 +5 chany_top_in[17]:10 chany_top_in[17]:9 0.01874107 +6 chany_top_in[17]:12 chany_top_in[17]:11 0.006151786 +7 chany_top_in[17]:13 chany_top_in[17]:12 0.0045 +8 chany_top_in[17]:15 chany_top_in[17]:14 0.0045 +9 chany_top_in[17]:14 chany_top_in[17]:13 0.0005267857 +10 chany_top_in[17]:16 chany_top_in[17]:15 0.0015625 +11 chany_top_in[17]:17 chany_top_in[17]:16 0.0045 +12 chany_top_in[17]:18 chany_top_in[17]:17 0.01690848 +13 chany_top_in[17]:19 chany_top_in[17]:18 0.00341 +14 chany_top_in[17]:21 chany_top_in[17]:20 0.00341 +15 chany_top_in[17]:21 chany_top_in[17]:6 0.000125 +16 chany_top_in[17]:20 chany_top_in[17]:19 0.00215965 +17 chany_top_in[17]:25 chany_top_in[17]:24 0.007537947 +18 chany_top_in[17]:26 chany_top_in[17]:25 0.00341 +19 chany_top_in[17]:27 chany_top_in[17]:26 0.002301825 +20 chany_top_in[17]:28 chany_top_in[17]:27 0.00341 +21 chany_top_in[17]:30 chany_top_in[17]:29 0.00341 +22 chany_top_in[17]:29 chany_top_in[17]:28 0.006496183 +23 chany_top_in[17]:32 chany_top_in[17]:31 0.00341 +24 chany_top_in[17]:31 chany_top_in[17]:30 0.000356025 +25 chany_top_in[17]:5 chany_top_in[17]:4 0.0008995536 +26 chany_top_in[17]:6 chany_top_in[17]:5 0.0045 +27 chany_top_in[17]:4 mux_bottom_track_17\/mux_l1_in_0_:A0 0.152 +28 chany_top_in[17]:23 chany_top_in[17]:22 0.006171875 +29 chany_top_in[17]:24 chany_top_in[17]:23 0.0045 +30 chany_top_in[17]:24 chany_top_in[17]:21 0.02939509 +31 chany_top_in[17]:22 mux_left_track_23\/mux_l1_in_0_:A1 0.152 + +*END + +*D_NET chany_top_in[18] 0.02110955 //LENGTH 163.305 LUMPCC 0.00343054 DR + +*CONN +*P chany_top_in[18] I *L 0.29796 *C 84.640 129.270 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 59.245 66.980 +*I FTB_18__17:A I *L 0.001776 *C 77.740 9.520 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 80.330 11.560 +*N chany_top_in[18]:4 *C 80.293 11.560 +*N chany_top_in[18]:5 *C 76.405 11.560 +*N chany_top_in[18]:6 *C 76.360 11.560 +*N chany_top_in[18]:7 *C 77.703 9.520 +*N chany_top_in[18]:8 *C 75.485 9.520 +*N chany_top_in[18]:9 *C 75.440 9.565 +*N chany_top_in[18]:10 *C 75.440 11.560 +*N chany_top_in[18]:11 *C 75.440 11.568 +*N chany_top_in[18]:12 *C 75.440 12.240 +*N chany_top_in[18]:13 *C 69.020 12.240 +*N chany_top_in[18]:14 *C 69.000 12.248 +*N chany_top_in[18]:15 *C 59.245 66.980 +*N chany_top_in[18]:16 *C 59.340 66.980 +*N chany_top_in[18]:17 *C 59.340 66.640 +*N chany_top_in[18]:18 *C 59.348 66.640 +*N chany_top_in[18]:19 *C 68.980 66.640 +*N chany_top_in[18]:20 *C 69.000 66.640 +*N chany_top_in[18]:21 *C 69.000 113.553 +*N chany_top_in[18]:22 *C 69.020 113.560 +*N chany_top_in[18]:23 *C 85.093 113.560 +*N chany_top_in[18]:24 *C 85.100 113.618 +*N chany_top_in[18]:25 *C 85.100 127.160 +*N chany_top_in[18]:26 *C 84.640 127.160 + +*CAP +0 chany_top_in[18] 0.0001210681 +1 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +2 FTB_18__17:A 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[18]:4 0.0002960907 +5 chany_top_in[18]:5 0.0002960907 +6 chany_top_in[18]:6 9.031317e-05 +7 chany_top_in[18]:7 0.0002036659 +8 chany_top_in[18]:8 0.0002036659 +9 chany_top_in[18]:9 0.0001420859 +10 chany_top_in[18]:10 0.0002003619 +11 chany_top_in[18]:11 5.885844e-05 +12 chany_top_in[18]:12 0.0004975069 +13 chany_top_in[18]:13 0.0004386485 +14 chany_top_in[18]:14 0.002423968 +15 chany_top_in[18]:15 2.819387e-05 +16 chany_top_in[18]:16 5.720816e-05 +17 chany_top_in[18]:17 6.119693e-05 +18 chany_top_in[18]:18 0.0007572484 +19 chany_top_in[18]:19 0.0007572484 +20 chany_top_in[18]:20 0.00485994 +21 chany_top_in[18]:21 0.002435972 +22 chany_top_in[18]:22 0.001007621 +23 chany_top_in[18]:23 0.001007621 +24 chany_top_in[18]:24 0.0008355172 +25 chany_top_in[18]:25 0.0008051873 +26 chany_top_in[18]:26 9.073826e-05 +27 chany_top_in[18]:21 chany_top_in[10]:25 0.0001693337 +28 chany_top_in[18]:21 chany_top_in[10]:26 0.00015966 +29 chany_top_in[18]:20 chany_top_in[10]:24 0.0001693337 +30 chany_top_in[18]:20 chany_top_in[10]:25 0.00015966 +31 chany_top_in[18]:21 chany_bottom_in[17]:26 0.0001798218 +32 chany_top_in[18]:24 chany_bottom_in[17]:7 6.60352e-06 +33 chany_top_in[18]:20 chany_bottom_in[17]:26 0.000284983 +34 chany_top_in[18]:20 chany_bottom_in[17]:27 0.001036488 +35 chany_top_in[18]:14 chany_bottom_in[17]:28 0.0008566664 +36 chany_top_in[18]:14 chany_bottom_in[17]:27 0.000284983 +37 chany_top_in[18]:25 chany_bottom_in[17]:6 6.60352e-06 +38 chany_top_in[18]:26 ropt_net_148:5 5.820139e-05 +39 chany_top_in[18]:25 ropt_net_148:6 5.820139e-05 + +*RES +0 chany_top_in[18] chany_top_in[18]:26 0.001883929 +1 chany_top_in[18]:4 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +2 chany_top_in[18]:5 chany_top_in[18]:4 0.003470982 +3 chany_top_in[18]:6 chany_top_in[18]:5 0.0045 +4 chany_top_in[18]:8 chany_top_in[18]:7 0.001979911 +5 chany_top_in[18]:9 chany_top_in[18]:8 0.0045 +6 chany_top_in[18]:7 FTB_18__17:A 0.152 +7 chany_top_in[18]:22 chany_top_in[18]:21 0.00341 +8 chany_top_in[18]:21 chany_top_in[18]:20 0.007349624 +9 chany_top_in[18]:24 chany_top_in[18]:23 0.00341 +10 chany_top_in[18]:23 chany_top_in[18]:22 0.002518025 +11 chany_top_in[18]:19 chany_top_in[18]:18 0.001509092 +12 chany_top_in[18]:20 chany_top_in[18]:19 0.00341 +13 chany_top_in[18]:20 chany_top_in[18]:14 0.008521492 +14 chany_top_in[18]:17 chany_top_in[18]:16 0.0001634615 +15 chany_top_in[18]:18 chany_top_in[18]:17 0.00341 +16 chany_top_in[18]:15 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +17 chany_top_in[18]:16 chany_top_in[18]:15 0.0045 +18 chany_top_in[18]:10 chany_top_in[18]:9 0.00178125 +19 chany_top_in[18]:10 chany_top_in[18]:6 0.0008214286 +20 chany_top_in[18]:11 chany_top_in[18]:10 0.00341 +21 chany_top_in[18]:13 chany_top_in[18]:12 0.0010058 +22 chany_top_in[18]:14 chany_top_in[18]:13 0.00341 +23 chany_top_in[18]:26 chany_top_in[18]:25 0.0004107143 +24 chany_top_in[18]:25 chany_top_in[18]:24 0.01209152 +25 chany_top_in[18]:12 chany_top_in[18]:11 0.0001053583 + +*END + +*D_NET chany_bottom_in[2] 0.02622633 //LENGTH 199.630 LUMPCC 0.005867919 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 81.420 1.290 +*I mux_top_track_0\/mux_l1_in_2_:A0 I *L 0.001631 *C 63.310 118.660 +*I FTB_20__19:A I *L 0.001776 *C 69.000 123.760 +*I mux_left_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 27.505 88.740 +*N chany_bottom_in[2]:4 *C 80.250 31.960 +*N chany_bottom_in[2]:5 *C 27.505 88.740 +*N chany_bottom_in[2]:6 *C 27.600 88.785 +*N chany_bottom_in[2]:7 *C 27.600 91.743 +*N chany_bottom_in[2]:8 *C 27.608 91.800 +*N chany_bottom_in[2]:9 *C 69.038 123.760 +*N chany_bottom_in[2]:10 *C 69.415 123.760 +*N chany_bottom_in[2]:11 *C 69.460 123.715 +*N chany_bottom_in[2]:12 *C 69.460 121.778 +*N chany_bottom_in[2]:13 *C 69.453 121.720 +*N chany_bottom_in[2]:14 *C 63.028 121.720 +*N chany_bottom_in[2]:15 *C 63.020 121.663 +*N chany_bottom_in[2]:16 *C 63.310 118.660 +*N chany_bottom_in[2]:17 *C 63.020 118.660 +*N chany_bottom_in[2]:18 *C 63.020 118.660 +*N chany_bottom_in[2]:19 *C 63.020 117.018 +*N chany_bottom_in[2]:20 *C 63.013 116.960 +*N chany_bottom_in[2]:21 *C 55.220 116.960 +*N chany_bottom_in[2]:22 *C 55.200 116.953 +*N chany_bottom_in[2]:23 *C 55.200 91.808 +*N chany_bottom_in[2]:24 *C 55.200 91.800 +*N chany_bottom_in[2]:25 *C 57.020 91.800 +*N chany_bottom_in[2]:26 *C 57.040 91.793 +*N chany_bottom_in[2]:27 *C 57.040 90.448 +*N chany_bottom_in[2]:28 *C 57.060 90.440 +*N chany_bottom_in[2]:29 *C 80.940 90.440 +*N chany_bottom_in[2]:30 *C 80.960 90.433 +*N chany_bottom_in[2]:31 *C 80.960 81.795 +*N chany_bottom_in[2]:32 *C 80.960 31.968 +*N chany_bottom_in[2]:33 *C 80.958 31.960 +*N chany_bottom_in[2]:34 *C 80.960 31.902 +*N chany_bottom_in[2]:35 *C 80.960 21.080 +*N chany_bottom_in[2]:36 *C 81.420 21.080 + +*CAP +0 chany_bottom_in[2] 0.001011703 +1 mux_top_track_0\/mux_l1_in_2_:A0 1e-06 +2 FTB_20__19:A 1e-06 +3 mux_left_track_1\/mux_l1_in_1_:A1 1e-06 +4 chany_bottom_in[2]:4 9.224984e-05 +5 chany_bottom_in[2]:5 2.976825e-05 +6 chany_bottom_in[2]:6 0.0002207976 +7 chany_bottom_in[2]:7 0.0002207976 +8 chany_bottom_in[2]:8 0.001720588 +9 chany_bottom_in[2]:9 4.899499e-05 +10 chany_bottom_in[2]:10 4.899499e-05 +11 chany_bottom_in[2]:11 0.0001490177 +12 chany_bottom_in[2]:12 0.0001490177 +13 chany_bottom_in[2]:13 0.0005106615 +14 chany_bottom_in[2]:14 0.0005106615 +15 chany_bottom_in[2]:15 0.0001856381 +16 chany_bottom_in[2]:16 5.483531e-05 +17 chany_bottom_in[2]:17 5.517873e-05 +18 chany_bottom_in[2]:18 0.0003207143 +19 chany_bottom_in[2]:19 0.0001035247 +20 chany_bottom_in[2]:20 0.0004113535 +21 chany_bottom_in[2]:21 0.0004113535 +22 chany_bottom_in[2]:22 0.001855147 +23 chany_bottom_in[2]:23 0.001855147 +24 chany_bottom_in[2]:24 0.001874505 +25 chany_bottom_in[2]:25 0.0001539171 +26 chany_bottom_in[2]:26 0.000160426 +27 chany_bottom_in[2]:27 0.000160426 +28 chany_bottom_in[2]:28 0.001194061 +29 chany_bottom_in[2]:29 0.001194061 +30 chany_bottom_in[2]:30 0.0003787107 +31 chany_bottom_in[2]:31 0.001668617 +32 chany_bottom_in[2]:32 0.001289906 +33 chany_bottom_in[2]:33 9.224984e-05 +34 chany_bottom_in[2]:34 0.000577332 +35 chany_bottom_in[2]:35 0.0006053437 +36 chany_bottom_in[2]:36 0.001039715 +37 chany_bottom_in[2]:21 chany_top_in[11]:14 0.0004367247 +38 chany_bottom_in[2]:20 chany_top_in[11]:15 0.0004367247 +39 chany_bottom_in[2]:23 chany_top_in[15]:15 0.0002969114 +40 chany_bottom_in[2]:23 chany_top_in[15]:16 0.0002569715 +41 chany_bottom_in[2]:22 chany_top_in[15]:16 0.0002969114 +42 chany_bottom_in[2]:22 chany_top_in[15]:17 0.0002569715 +43 chany_bottom_in[2] chany_bottom_in[6]:41 1.543567e-05 +44 chany_bottom_in[2]:15 chany_bottom_in[6]:21 1.970136e-08 +45 chany_bottom_in[2]:18 chany_bottom_in[6]:22 1.970136e-08 +46 chany_bottom_in[2]:32 chany_bottom_in[6]:41 0.0003874342 +47 chany_bottom_in[2]:32 chany_bottom_in[6]:37 1.057868e-05 +48 chany_bottom_in[2]:36 chany_bottom_in[6]:40 1.543567e-05 +49 chany_bottom_in[2]:31 chany_bottom_in[6]:40 0.0003874342 +50 chany_bottom_in[2]:31 chany_bottom_in[6]:36 1.057868e-05 +51 chany_bottom_in[2]:28 chany_bottom_in[16]:15 6.505901e-05 +52 chany_bottom_in[2]:29 chany_bottom_in[16]:14 6.505901e-05 +53 chany_bottom_in[2]:30 chany_bottom_in[16]:16 3.175058e-05 +54 chany_bottom_in[2]:32 chany_bottom_in[16]:25 0.0001798862 +55 chany_bottom_in[2]:32 chany_bottom_in[16]:23 5.888338e-05 +56 chany_bottom_in[2]:31 chany_bottom_in[16]:16 5.888338e-05 +57 chany_bottom_in[2]:31 chany_bottom_in[16]:23 3.175058e-05 +58 chany_bottom_in[2]:31 chany_bottom_in[16]:24 0.0001798862 +59 chany_bottom_in[2]:24 prog_clk[0]:339 4.562285e-05 +60 chany_bottom_in[2]:23 prog_clk[0]:306 1.527338e-05 +61 chany_bottom_in[2]:22 prog_clk[0]:311 1.527338e-05 +62 chany_bottom_in[2]:8 prog_clk[0]:340 4.562285e-05 +63 chany_bottom_in[2]:28 prog_clk[0]:443 0.0001219124 +64 chany_bottom_in[2]:28 prog_clk[0]:421 0.0003165239 +65 chany_bottom_in[2]:29 prog_clk[0]:442 0.0001219124 +66 chany_bottom_in[2]:29 prog_clk[0]:420 0.0003165239 +67 chany_bottom_in[2]:32 prog_clk[0]:103 7.72473e-06 +68 chany_bottom_in[2]:31 prog_clk[0]:108 7.72473e-06 +69 chany_bottom_in[2] chany_bottom_in[19]:10 5.470358e-06 +70 chany_bottom_in[2]:32 chany_bottom_in[19]:10 0.0003357835 +71 chany_bottom_in[2]:36 chany_bottom_in[19]:9 5.470358e-06 +72 chany_bottom_in[2]:31 chany_bottom_in[19]:9 0.0003357835 +73 chany_bottom_in[2]:24 mux_tree_tapbuf_size7_1_sram[0]:32 9.923951e-05 +74 chany_bottom_in[2]:24 mux_tree_tapbuf_size7_1_sram[0]:31 1.014905e-05 +75 chany_bottom_in[2]:8 mux_tree_tapbuf_size7_1_sram[0]:31 9.923951e-05 +76 chany_bottom_in[2]:25 mux_tree_tapbuf_size7_1_sram[0]:32 1.014905e-05 +77 chany_bottom_in[2]:28 mux_tree_tapbuf_size7_1_sram[0]:35 6.055879e-06 +78 chany_bottom_in[2]:28 mux_tree_tapbuf_size7_1_sram[0]:31 0.0002305485 +79 chany_bottom_in[2]:29 mux_tree_tapbuf_size7_1_sram[0]:32 0.0002305485 +80 chany_bottom_in[2]:29 mux_tree_tapbuf_size7_1_sram[0]:6 6.055879e-06 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:36 0.01766964 +1 chany_bottom_in[2]:24 chany_bottom_in[2]:23 0.00341 +2 chany_bottom_in[2]:24 chany_bottom_in[2]:8 0.004322825 +3 chany_bottom_in[2]:23 chany_bottom_in[2]:22 0.003939383 +4 chany_bottom_in[2]:21 chany_bottom_in[2]:20 0.001220825 +5 chany_bottom_in[2]:22 chany_bottom_in[2]:21 0.00341 +6 chany_bottom_in[2]:19 chany_bottom_in[2]:18 0.001466518 +7 chany_bottom_in[2]:20 chany_bottom_in[2]:19 0.00341 +8 chany_bottom_in[2]:15 chany_bottom_in[2]:14 0.00341 +9 chany_bottom_in[2]:14 chany_bottom_in[2]:13 0.001006583 +10 chany_bottom_in[2]:12 chany_bottom_in[2]:11 0.001729911 +11 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.00341 +12 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.0003370536 +13 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.0045 +14 chany_bottom_in[2]:9 FTB_20__19:A 0.152 +15 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.002640625 +16 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.00341 +17 chany_bottom_in[2]:5 mux_left_track_1\/mux_l1_in_1_:A1 0.152 +18 chany_bottom_in[2]:6 chany_bottom_in[2]:5 0.0045 +19 chany_bottom_in[2]:17 chany_bottom_in[2]:16 0.0001576087 +20 chany_bottom_in[2]:18 chany_bottom_in[2]:17 0.0045 +21 chany_bottom_in[2]:18 chany_bottom_in[2]:15 0.002680804 +22 chany_bottom_in[2]:16 mux_top_track_0\/mux_l1_in_2_:A0 0.152 +23 chany_bottom_in[2]:25 chany_bottom_in[2]:24 0.0002851333 +24 chany_bottom_in[2]:26 chany_bottom_in[2]:25 0.00341 +25 chany_bottom_in[2]:28 chany_bottom_in[2]:27 0.00341 +26 chany_bottom_in[2]:27 chany_bottom_in[2]:26 0.0002107167 +27 chany_bottom_in[2]:29 chany_bottom_in[2]:28 0.0037412 +28 chany_bottom_in[2]:30 chany_bottom_in[2]:29 0.00341 +29 chany_bottom_in[2]:33 chany_bottom_in[2]:32 0.00341 +30 chany_bottom_in[2]:33 chany_bottom_in[2]:4 0.0001039141 +31 chany_bottom_in[2]:32 chany_bottom_in[2]:31 0.007806308 +32 chany_bottom_in[2]:34 chany_bottom_in[2]:33 0.00341 +33 chany_bottom_in[2]:35 chany_bottom_in[2]:34 0.009662947 +34 chany_bottom_in[2]:36 chany_bottom_in[2]:35 0.0004107143 +35 chany_bottom_in[2]:31 chany_bottom_in[2]:30 0.001353208 + +*END + +*D_NET chany_bottom_in[6] 0.02463379 //LENGTH 207.925 LUMPCC 0.00336538 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 94.300 1.325 +*I ropt_mt_inst_769:A I *L 0.001767 *C 47.380 126.480 +*I mux_top_track_8\/mux_l2_in_1_:A1 I *L 0.00198 *C 80.500 94.180 +*I mux_left_track_7\/mux_l1_in_1_:A1 I *L 0.00198 *C 60.625 58.140 +*N chany_bottom_in[6]:4 *C 60.663 58.140 +*N chany_bottom_in[6]:5 *C 61.180 58.140 +*N chany_bottom_in[6]:6 *C 61.180 57.800 +*N chany_bottom_in[6]:7 *C 77.235 57.800 +*N chany_bottom_in[6]:8 *C 77.280 57.755 +*N chany_bottom_in[6]:9 *C 77.280 56.498 +*N chany_bottom_in[6]:10 *C 77.288 56.440 +*N chany_bottom_in[6]:11 *C 80.500 94.180 +*N chany_bottom_in[6]:12 *C 47.418 126.480 +*N chany_bottom_in[6]:13 *C 47.795 126.480 +*N chany_bottom_in[6]:14 *C 47.840 126.480 +*N chany_bottom_in[6]:15 *C 47.848 126.480 +*N chany_bottom_in[6]:16 *C 49.672 126.480 +*N chany_bottom_in[6]:17 *C 49.680 126.538 +*N chany_bottom_in[6]:18 *C 49.680 128.815 +*N chany_bottom_in[6]:19 *C 49.725 128.860 +*N chany_bottom_in[6]:20 *C 65.275 128.860 +*N chany_bottom_in[6]:21 *C 65.320 128.815 +*N chany_bottom_in[6]:22 *C 65.320 121.425 +*N chany_bottom_in[6]:23 *C 65.365 121.380 +*N chany_bottom_in[6]:24 *C 66.700 121.380 +*N chany_bottom_in[6]:25 *C 66.700 121.040 +*N chany_bottom_in[6]:26 *C 67.160 121.040 +*N chany_bottom_in[6]:27 *C 67.160 120.700 +*N chany_bottom_in[6]:28 *C 74.475 120.700 +*N chany_bottom_in[6]:29 *C 74.520 120.655 +*N chany_bottom_in[6]:30 *C 74.520 93.205 +*N chany_bottom_in[6]:31 *C 74.565 93.160 +*N chany_bottom_in[6]:32 *C 78.660 93.160 +*N chany_bottom_in[6]:33 *C 78.660 93.840 +*N chany_bottom_in[6]:34 *C 80.500 93.840 +*N chany_bottom_in[6]:35 *C 81.835 93.840 +*N chany_bottom_in[6]:36 *C 81.880 93.795 +*N chany_bottom_in[6]:37 *C 81.880 56.498 +*N chany_bottom_in[6]:38 *C 81.880 56.440 +*N chany_bottom_in[6]:39 *C 83.700 56.440 +*N chany_bottom_in[6]:40 *C 83.720 56.433 +*N chany_bottom_in[6]:41 *C 83.720 2.048 +*N chany_bottom_in[6]:42 *C 83.740 2.040 +*N chany_bottom_in[6]:43 *C 94.293 2.040 +*N chany_bottom_in[6]:44 *C 94.300 1.983 + +*CAP +0 chany_bottom_in[6] 5.423361e-05 +1 ropt_mt_inst_769:A 1e-06 +2 mux_top_track_8\/mux_l2_in_1_:A1 1e-06 +3 mux_left_track_7\/mux_l1_in_1_:A1 1e-06 +4 chany_bottom_in[6]:4 5.447234e-05 +5 chany_bottom_in[6]:5 8.040522e-05 +6 chany_bottom_in[6]:6 0.001062692 +7 chany_bottom_in[6]:7 0.001036759 +8 chany_bottom_in[6]:8 9.17678e-05 +9 chany_bottom_in[6]:9 9.17678e-05 +10 chany_bottom_in[6]:10 0.0003621444 +11 chany_bottom_in[6]:11 5.26439e-05 +12 chany_bottom_in[6]:12 5.89181e-05 +13 chany_bottom_in[6]:13 5.89181e-05 +14 chany_bottom_in[6]:14 3.461755e-05 +15 chany_bottom_in[6]:15 0.0001928141 +16 chany_bottom_in[6]:16 0.0001928141 +17 chany_bottom_in[6]:17 0.0001706625 +18 chany_bottom_in[6]:18 0.0001706625 +19 chany_bottom_in[6]:19 0.0007639771 +20 chany_bottom_in[6]:20 0.0007639771 +21 chany_bottom_in[6]:21 0.0004171224 +22 chany_bottom_in[6]:22 0.0004171224 +23 chany_bottom_in[6]:23 8.071816e-05 +24 chany_bottom_in[6]:24 0.0001043641 +25 chany_bottom_in[6]:25 4.982585e-05 +26 chany_bottom_in[6]:26 5.242721e-05 +27 chany_bottom_in[6]:27 0.0005077862 +28 chany_bottom_in[6]:28 0.0004815389 +29 chany_bottom_in[6]:29 0.001011726 +30 chany_bottom_in[6]:30 0.001011726 +31 chany_bottom_in[6]:31 0.000277214 +32 chany_bottom_in[6]:32 0.0003186945 +33 chany_bottom_in[6]:33 0.0001735562 +34 chany_bottom_in[6]:34 0.0002545061 +35 chany_bottom_in[6]:35 9.629678e-05 +36 chany_bottom_in[6]:36 0.00187119 +37 chany_bottom_in[6]:37 0.00187119 +38 chany_bottom_in[6]:38 0.0004840547 +39 chany_bottom_in[6]:39 0.0001219103 +40 chany_bottom_in[6]:40 0.002533805 +41 chany_bottom_in[6]:41 0.002533805 +42 chany_bottom_in[6]:42 0.0006231733 +43 chany_bottom_in[6]:43 0.0006231733 +44 chany_bottom_in[6]:44 5.423361e-05 +45 chany_bottom_in[6]:29 chany_top_in[6] 0.0007358087 +46 chany_bottom_in[6]:30 chany_top_in[6]:19 0.0007358087 +47 chany_bottom_in[6]:19 chany_top_in[19]:18 0.0003618342 +48 chany_bottom_in[6]:20 chany_top_in[19]:19 0.0003618342 +49 chany_bottom_in[6]:21 chany_bottom_in[2]:15 1.970136e-08 +50 chany_bottom_in[6]:22 chany_bottom_in[2]:18 1.970136e-08 +51 chany_bottom_in[6]:40 chany_bottom_in[2]:31 0.0003874342 +52 chany_bottom_in[6]:40 chany_bottom_in[2]:36 1.543567e-05 +53 chany_bottom_in[6]:41 chany_bottom_in[2] 1.543567e-05 +54 chany_bottom_in[6]:41 chany_bottom_in[2]:32 0.0003874342 +55 chany_bottom_in[6]:37 chany_bottom_in[2]:32 1.057868e-05 +56 chany_bottom_in[6]:36 chany_bottom_in[2]:31 1.057868e-05 +57 chany_bottom_in[6]:29 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 5.907936e-05 +58 chany_bottom_in[6]:31 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 3.372563e-07 +59 chany_bottom_in[6]:30 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 5.907936e-05 +60 chany_bottom_in[6]:32 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 3.372563e-07 +61 chany_bottom_in[6]:21 ropt_net_174:6 2.717849e-06 +62 chany_bottom_in[6]:23 ropt_net_174:3 6.094738e-05 +63 chany_bottom_in[6]:22 ropt_net_174:5 2.717849e-06 +64 chany_bottom_in[6]:24 ropt_net_174:4 6.094738e-05 +65 chany_bottom_in[6]:24 ropt_net_174:3 1.019808e-07 +66 chany_bottom_in[6]:25 ropt_net_174:2 1.019808e-07 +67 chany_bottom_in[6]:25 ropt_net_174:3 1.681989e-06 +68 chany_bottom_in[6]:26 ropt_net_174:4 1.681989e-06 +69 chany_bottom_in[6]:26 ropt_net_174:3 2.404384e-08 +70 chany_bottom_in[6]:27 ropt_net_174:2 2.404384e-08 +71 chany_bottom_in[6]:28 ropt_net_168:4 4.665997e-05 +72 chany_bottom_in[6]:26 ropt_net_168:3 2.921188e-08 +73 chany_bottom_in[6]:27 ropt_net_168:2 2.921188e-08 +74 chany_bottom_in[6]:27 ropt_net_168:3 4.665997e-05 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:44 0.0005870535 +1 chany_bottom_in[6]:12 ropt_mt_inst_769:A 0.152 +2 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.0003370536 +3 chany_bottom_in[6]:14 chany_bottom_in[6]:13 0.0045 +4 chany_bottom_in[6]:15 chany_bottom_in[6]:14 0.00341 +5 chany_bottom_in[6]:17 chany_bottom_in[6]:16 0.00341 +6 chany_bottom_in[6]:16 chany_bottom_in[6]:15 0.0002859167 +7 chany_bottom_in[6]:19 chany_bottom_in[6]:18 0.0045 +8 chany_bottom_in[6]:18 chany_bottom_in[6]:17 0.002033482 +9 chany_bottom_in[6]:20 chany_bottom_in[6]:19 0.01388393 +10 chany_bottom_in[6]:21 chany_bottom_in[6]:20 0.0045 +11 chany_bottom_in[6]:23 chany_bottom_in[6]:22 0.0045 +12 chany_bottom_in[6]:22 chany_bottom_in[6]:21 0.006598215 +13 chany_bottom_in[6]:28 chany_bottom_in[6]:27 0.00653125 +14 chany_bottom_in[6]:29 chany_bottom_in[6]:28 0.0045 +15 chany_bottom_in[6]:31 chany_bottom_in[6]:30 0.0045 +16 chany_bottom_in[6]:30 chany_bottom_in[6]:29 0.02450893 +17 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.001122768 +18 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.00341 +19 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.01433482 +20 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.0045 +21 chany_bottom_in[6]:4 mux_left_track_7\/mux_l1_in_1_:A1 0.152 +22 chany_bottom_in[6]:11 mux_top_track_8\/mux_l2_in_1_:A1 0.152 +23 chany_bottom_in[6]:39 chany_bottom_in[6]:38 0.0002851333 +24 chany_bottom_in[6]:40 chany_bottom_in[6]:39 0.00341 +25 chany_bottom_in[6]:42 chany_bottom_in[6]:41 0.00341 +26 chany_bottom_in[6]:41 chany_bottom_in[6]:40 0.008520316 +27 chany_bottom_in[6]:44 chany_bottom_in[6]:43 0.00341 +28 chany_bottom_in[6]:43 chany_bottom_in[6]:42 0.001653225 +29 chany_bottom_in[6]:37 chany_bottom_in[6]:36 0.03330134 +30 chany_bottom_in[6]:38 chany_bottom_in[6]:37 0.00341 +31 chany_bottom_in[6]:38 chany_bottom_in[6]:10 0.0007194917 +32 chany_bottom_in[6]:35 chany_bottom_in[6]:34 0.001191964 +33 chany_bottom_in[6]:36 chany_bottom_in[6]:35 0.0045 +34 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.0004620536 +35 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.0003035715 +36 chany_bottom_in[6]:24 chany_bottom_in[6]:23 0.001191964 +37 chany_bottom_in[6]:25 chany_bottom_in[6]:24 0.0003035714 +38 chany_bottom_in[6]:26 chany_bottom_in[6]:25 0.0004107142 +39 chany_bottom_in[6]:27 chany_bottom_in[6]:26 0.0003035714 +40 chany_bottom_in[6]:32 chany_bottom_in[6]:31 0.00365625 +41 chany_bottom_in[6]:33 chany_bottom_in[6]:32 0.000607143 +42 chany_bottom_in[6]:34 chany_bottom_in[6]:33 0.001642857 +43 chany_bottom_in[6]:34 chany_bottom_in[6]:11 0.0003035715 + +*END + +*D_NET chany_bottom_in[12] 0.02157657 //LENGTH 163.965 LUMPCC 0.005884378 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 79.580 1.290 +*I mux_left_track_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 53.720 +*I mux_top_track_0\/mux_l2_in_1_:A0 I *L 0.001631 *C 57.330 120.360 +*I FTB_27__26:A I *L 0.001776 *C 65.780 123.760 +*N chany_bottom_in[12]:4 *C 65.758 123.788 +*N chany_bottom_in[12]:5 *C 65.745 124.100 +*N chany_bottom_in[12]:6 *C 57.367 120.360 +*N chany_bottom_in[12]:7 *C 58.375 120.360 +*N chany_bottom_in[12]:8 *C 58.420 120.405 +*N chany_bottom_in[12]:9 *C 58.420 124.055 +*N chany_bottom_in[12]:10 *C 58.420 124.100 +*N chany_bottom_in[12]:11 *C 56.625 124.100 +*N chany_bottom_in[12]:12 *C 56.580 124.055 +*N chany_bottom_in[12]:13 *C 56.580 103.535 +*N chany_bottom_in[12]:14 *C 55.068 53.720 +*N chany_bottom_in[12]:15 *C 56.535 53.720 +*N chany_bottom_in[12]:16 *C 56.580 53.720 +*N chany_bottom_in[12]:17 *C 56.588 53.720 +*N chany_bottom_in[12]:18 *C 79.573 53.720 +*N chany_bottom_in[12]:19 *C 79.580 53.663 + +*CAP +0 chany_bottom_in[12] 0.002272693 +1 mux_left_track_15\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_0\/mux_l2_in_1_:A0 1e-06 +3 FTB_27__26:A 1e-06 +4 chany_bottom_in[12]:4 3.705098e-05 +5 chany_bottom_in[12]:5 0.0004912773 +6 chany_bottom_in[12]:6 0.0001137678 +7 chany_bottom_in[12]:7 0.0001137678 +8 chany_bottom_in[12]:8 0.0001757163 +9 chany_bottom_in[12]:9 0.0001757163 +10 chany_bottom_in[12]:10 0.0006139369 +11 chany_bottom_in[12]:11 0.0001246752 +12 chany_bottom_in[12]:12 0.001029053 +13 chany_bottom_in[12]:13 0.003147157 +14 chany_bottom_in[12]:14 9.643723e-05 +15 chany_bottom_in[12]:15 9.643723e-05 +16 chany_bottom_in[12]:16 0.002151472 +17 chany_bottom_in[12]:17 0.001388669 +18 chany_bottom_in[12]:18 0.001388669 +19 chany_bottom_in[12]:19 0.002272693 +20 chany_bottom_in[12]:17 chany_top_in[8]:13 0.000570251 +21 chany_bottom_in[12]:18 chany_top_in[8]:18 0.000570251 +22 chany_bottom_in[12]:16 chany_bottom_in[10]:16 0.0005480053 +23 chany_bottom_in[12]:13 chany_bottom_in[10]:13 0.0005480053 +24 chany_bottom_in[12] mux_tree_tapbuf_size10_1_sram[0]:25 0.0004738747 +25 chany_bottom_in[12]:19 mux_tree_tapbuf_size10_1_sram[0]:26 0.0004738747 +26 chany_bottom_in[12]:16 mux_tree_tapbuf_size7_0_sram[1]:10 0.0002560463 +27 chany_bottom_in[12]:16 mux_tree_tapbuf_size7_0_sram[1]:15 7.362539e-05 +28 chany_bottom_in[12]:13 mux_tree_tapbuf_size7_0_sram[1]:9 0.0002560463 +29 chany_bottom_in[12]:13 mux_tree_tapbuf_size7_0_sram[1]:16 7.362539e-05 +30 chany_bottom_in[12]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.481666e-06 +31 chany_bottom_in[12]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 4.481666e-06 +32 chany_bottom_in[12]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.93607e-05 +33 chany_bottom_in[12]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.93607e-05 +34 chany_bottom_in[12]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 8.162294e-05 +35 chany_bottom_in[12]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 1.37542e-05 +36 chany_bottom_in[12]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 8.661547e-06 +37 chany_bottom_in[12]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 8.162294e-05 +38 chany_bottom_in[12]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 8.661547e-06 +39 chany_bottom_in[12]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 1.37542e-05 +40 chany_bottom_in[12]:12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 5.293314e-05 +41 chany_bottom_in[12]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 5.293314e-05 +42 chany_bottom_in[12]:15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.579902e-05 +43 chany_bottom_in[12]:16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.548976e-05 +44 chany_bottom_in[12]:14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.579902e-05 +45 chany_bottom_in[12]:13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.548976e-05 +46 chany_bottom_in[12] mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002097448 +47 chany_bottom_in[12]:19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002097448 +48 chany_bottom_in[12] ropt_net_203:6 0.0001038169 +49 chany_bottom_in[12]:19 ropt_net_203:5 0.0001038169 +50 chany_bottom_in[12]:10 ropt_net_172:6 2.201458e-05 +51 chany_bottom_in[12]:10 ropt_net_172:7 2.23373e-05 +52 chany_bottom_in[12]:9 ropt_net_172:5 7.498272e-05 +53 chany_bottom_in[12]:8 ropt_net_172:4 7.498272e-05 +54 chany_bottom_in[12]:11 ropt_net_172:7 2.201458e-05 +55 chany_bottom_in[12]:5 ropt_net_172:6 2.23373e-05 +56 chany_bottom_in[12] ropt_net_154:4 0.0002111745 +57 chany_bottom_in[12]:19 ropt_net_154:5 0.0002111745 +58 chany_bottom_in[12]:10 ropt_net_187:6 7.42124e-05 +59 chany_bottom_in[12]:5 ropt_net_187:7 7.42124e-05 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:19 0.04676116 +1 chany_bottom_in[12]:4 FTB_27__26:A 0.152 +2 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.0045 +3 chany_bottom_in[12]:10 chany_bottom_in[12]:5 0.006540179 +4 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.003258929 +5 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.0008995536 +6 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.0045 +7 chany_bottom_in[12]:6 mux_top_track_0\/mux_l2_in_1_:A0 0.152 +8 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.001602679 +9 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.0045 +10 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.001310268 +11 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.0045 +12 chany_bottom_in[12]:16 chany_bottom_in[12]:13 0.04447768 +13 chany_bottom_in[12]:14 mux_left_track_15\/mux_l1_in_0_:A0 0.152 +14 chany_bottom_in[12]:17 chany_bottom_in[12]:16 0.00341 +15 chany_bottom_in[12]:19 chany_bottom_in[12]:18 0.00341 +16 chany_bottom_in[12]:18 chany_bottom_in[12]:17 0.003600983 +17 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.0002111487 +18 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.01832143 + +*END + +*D_NET left_top_grid_pin_43_[0] 0.02201835 //LENGTH 152.310 LUMPCC 0.00703436 DR + +*CONN +*P left_top_grid_pin_43_[0] I *L 0.29796 *C 29.825 119.000 +*I mux_left_track_7\/mux_l1_in_1_:A0 I *L 0.001631 *C 61.010 58.820 +*I mux_left_track_11\/mux_l2_in_1_:A1 I *L 0.00198 *C 80.140 45.220 +*I mux_left_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 31.570 86.020 +*I FTB_33__32:A I *L 0.001767 *C 11.500 99.280 +*N left_top_grid_pin_43_[0]:5 *C 11.538 99.280 +*N left_top_grid_pin_43_[0]:6 *C 12.835 99.280 +*N left_top_grid_pin_43_[0]:7 *C 12.880 99.280 +*N left_top_grid_pin_43_[0]:8 *C 12.888 99.280 +*N left_top_grid_pin_43_[0]:9 *C 31.570 86.020 +*N left_top_grid_pin_43_[0]:10 *C 80.103 45.220 +*N left_top_grid_pin_43_[0]:11 *C 79.165 45.220 +*N left_top_grid_pin_43_[0]:12 *C 79.120 45.265 +*N left_top_grid_pin_43_[0]:13 *C 79.120 50.943 +*N left_top_grid_pin_43_[0]:14 *C 79.112 51.000 +*N left_top_grid_pin_43_[0]:15 *C 62.108 51.000 +*N left_top_grid_pin_43_[0]:16 *C 62.100 51.058 +*N left_top_grid_pin_43_[0]:17 *C 61.047 58.820 +*N left_top_grid_pin_43_[0]:18 *C 62.055 58.820 +*N left_top_grid_pin_43_[0]:19 *C 62.100 58.820 +*N left_top_grid_pin_43_[0]:20 *C 62.100 61.495 +*N left_top_grid_pin_43_[0]:21 *C 62.055 61.540 +*N left_top_grid_pin_43_[0]:22 *C 60.305 61.540 +*N left_top_grid_pin_43_[0]:23 *C 60.260 61.585 +*N left_top_grid_pin_43_[0]:24 *C 60.260 78.142 +*N left_top_grid_pin_43_[0]:25 *C 60.253 78.200 +*N left_top_grid_pin_43_[0]:26 *C 31.748 78.200 +*N left_top_grid_pin_43_[0]:27 *C 31.740 78.258 +*N left_top_grid_pin_43_[0]:28 *C 31.740 85.975 +*N left_top_grid_pin_43_[0]:29 *C 31.740 86.020 +*N left_top_grid_pin_43_[0]:30 *C 31.740 86.360 +*N left_top_grid_pin_43_[0]:31 *C 27.185 86.360 +*N left_top_grid_pin_43_[0]:32 *C 27.140 86.405 +*N left_top_grid_pin_43_[0]:33 *C 27.140 99.223 +*N left_top_grid_pin_43_[0]:34 *C 27.140 99.280 +*N left_top_grid_pin_43_[0]:35 *C 30.353 99.280 +*N left_top_grid_pin_43_[0]:36 *C 30.360 99.338 +*N left_top_grid_pin_43_[0]:37 *C 30.360 118.943 +*N left_top_grid_pin_43_[0]:38 *C 30.353 119.000 + +*CAP +0 left_top_grid_pin_43_[0] 6.433787e-05 +1 mux_left_track_7\/mux_l1_in_1_:A0 1e-06 +2 mux_left_track_11\/mux_l2_in_1_:A1 1e-06 +3 mux_left_track_3\/mux_l1_in_1_:A0 1e-06 +4 FTB_33__32:A 1e-06 +5 left_top_grid_pin_43_[0]:5 6.825212e-05 +6 left_top_grid_pin_43_[0]:6 6.825212e-05 +7 left_top_grid_pin_43_[0]:7 3.227185e-05 +8 left_top_grid_pin_43_[0]:8 0.0004435227 +9 left_top_grid_pin_43_[0]:9 4.286972e-05 +10 left_top_grid_pin_43_[0]:10 0.0001120992 +11 left_top_grid_pin_43_[0]:11 0.0001120992 +12 left_top_grid_pin_43_[0]:12 0.0004375849 +13 left_top_grid_pin_43_[0]:13 0.0004375849 +14 left_top_grid_pin_43_[0]:14 0.001043186 +15 left_top_grid_pin_43_[0]:15 0.001043186 +16 left_top_grid_pin_43_[0]:16 0.0003628515 +17 left_top_grid_pin_43_[0]:17 0.0001047682 +18 left_top_grid_pin_43_[0]:18 0.0001047682 +19 left_top_grid_pin_43_[0]:19 0.0005185331 +20 left_top_grid_pin_43_[0]:20 0.0001247972 +21 left_top_grid_pin_43_[0]:21 0.0001235477 +22 left_top_grid_pin_43_[0]:22 0.0001235477 +23 left_top_grid_pin_43_[0]:23 0.0006731207 +24 left_top_grid_pin_43_[0]:24 0.0006731207 +25 left_top_grid_pin_43_[0]:25 0.001828785 +26 left_top_grid_pin_43_[0]:26 0.001828785 +27 left_top_grid_pin_43_[0]:27 0.0004467576 +28 left_top_grid_pin_43_[0]:28 0.0004467576 +29 left_top_grid_pin_43_[0]:29 6.752464e-05 +30 left_top_grid_pin_43_[0]:30 0.000365847 +31 left_top_grid_pin_43_[0]:31 0.0003453465 +32 left_top_grid_pin_43_[0]:32 0.0007081573 +33 left_top_grid_pin_43_[0]:33 0.0007081573 +34 left_top_grid_pin_43_[0]:34 0.0005312527 +35 left_top_grid_pin_43_[0]:35 8.773021e-05 +36 left_top_grid_pin_43_[0]:36 0.0004181272 +37 left_top_grid_pin_43_[0]:37 0.0004181272 +38 left_top_grid_pin_43_[0]:38 6.433787e-05 +39 left_top_grid_pin_43_[0]:16 chany_top_in[2]:14 5.693351e-05 +40 left_top_grid_pin_43_[0]:19 chany_top_in[2]:14 2.183991e-05 +41 left_top_grid_pin_43_[0]:19 chany_top_in[2]:15 5.693351e-05 +42 left_top_grid_pin_43_[0]:20 chany_top_in[2]:15 2.183991e-05 +43 left_top_grid_pin_43_[0]:23 chany_top_in[2]:14 0.0003189801 +44 left_top_grid_pin_43_[0]:23 chany_top_in[2]:15 0.0001193668 +45 left_top_grid_pin_43_[0]:24 chany_top_in[2]:15 0.0003189801 +46 left_top_grid_pin_43_[0]:24 chany_top_in[2]:18 0.0001193668 +47 left_top_grid_pin_43_[0]:33 top_left_grid_pin_41_[0]:9 1.637249e-05 +48 left_top_grid_pin_43_[0]:32 top_left_grid_pin_41_[0]:8 1.637249e-05 +49 left_top_grid_pin_43_[0]:37 top_left_grid_pin_41_[0]:18 0.0002604889 +50 left_top_grid_pin_43_[0]:37 top_left_grid_pin_41_[0]:19 0.0002399138 +51 left_top_grid_pin_43_[0]:36 top_left_grid_pin_41_[0]:18 0.0002399138 +52 left_top_grid_pin_43_[0]:36 top_left_grid_pin_41_[0]:12 0.0002604889 +53 left_top_grid_pin_43_[0]:34 chanx_left_in[12]:20 0.0002324885 +54 left_top_grid_pin_43_[0]:34 chanx_left_in[12]:21 5.322972e-05 +55 left_top_grid_pin_43_[0]:8 chanx_left_in[12]:21 0.0002324885 +56 left_top_grid_pin_43_[0]:35 chanx_left_in[12]:20 5.322972e-05 +57 left_top_grid_pin_43_[0]:25 chanx_left_in[15]:11 0.0007259487 +58 left_top_grid_pin_43_[0]:26 chanx_left_in[15] 0.0007259487 +59 left_top_grid_pin_43_[0]:33 mux_tree_tapbuf_size10_0_sram[1]:22 2.865686e-08 +60 left_top_grid_pin_43_[0]:34 mux_tree_tapbuf_size10_0_sram[1]:20 1.178352e-05 +61 left_top_grid_pin_43_[0]:32 mux_tree_tapbuf_size10_0_sram[1]:21 2.865686e-08 +62 left_top_grid_pin_43_[0]:8 mux_tree_tapbuf_size10_0_sram[1]:19 1.178352e-05 +63 left_top_grid_pin_43_[0]:6 mux_tree_tapbuf_size10_0_sram[1]:18 2.94502e-05 +64 left_top_grid_pin_43_[0]:5 mux_tree_tapbuf_size10_0_sram[1]:17 2.94502e-05 +65 left_top_grid_pin_43_[0]:37 mux_tree_tapbuf_size10_0_sram[1]:22 0.0005085287 +66 left_top_grid_pin_43_[0]:36 mux_tree_tapbuf_size10_0_sram[1]:21 0.0005085287 +67 left_top_grid_pin_43_[0]:34 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0004043568 +68 left_top_grid_pin_43_[0]:34 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0001849893 +69 left_top_grid_pin_43_[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0004043568 +70 left_top_grid_pin_43_[0]:35 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0001849893 +71 left_top_grid_pin_43_[0]:33 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.328899e-05 +72 left_top_grid_pin_43_[0]:32 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.328899e-05 +73 left_top_grid_pin_43_[0]:15 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0002959369 +74 left_top_grid_pin_43_[0]:13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 3.254224e-06 +75 left_top_grid_pin_43_[0]:14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0002959369 +76 left_top_grid_pin_43_[0]:12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 3.254224e-06 + +*RES +0 left_top_grid_pin_43_[0] left_top_grid_pin_43_[0]:38 8.264166e-05 +1 left_top_grid_pin_43_[0]:16 left_top_grid_pin_43_[0]:15 0.00341 +2 left_top_grid_pin_43_[0]:15 left_top_grid_pin_43_[0]:14 0.002664117 +3 left_top_grid_pin_43_[0]:13 left_top_grid_pin_43_[0]:12 0.005069197 +4 left_top_grid_pin_43_[0]:14 left_top_grid_pin_43_[0]:13 0.00341 +5 left_top_grid_pin_43_[0]:11 left_top_grid_pin_43_[0]:10 0.0008370536 +6 left_top_grid_pin_43_[0]:12 left_top_grid_pin_43_[0]:11 0.0045 +7 left_top_grid_pin_43_[0]:10 mux_left_track_11\/mux_l2_in_1_:A1 0.152 +8 left_top_grid_pin_43_[0]:18 left_top_grid_pin_43_[0]:17 0.0008995536 +9 left_top_grid_pin_43_[0]:19 left_top_grid_pin_43_[0]:18 0.0045 +10 left_top_grid_pin_43_[0]:19 left_top_grid_pin_43_[0]:16 0.006930804 +11 left_top_grid_pin_43_[0]:17 mux_left_track_7\/mux_l1_in_1_:A0 0.152 +12 left_top_grid_pin_43_[0]:33 left_top_grid_pin_43_[0]:32 0.0114442 +13 left_top_grid_pin_43_[0]:34 left_top_grid_pin_43_[0]:33 0.00341 +14 left_top_grid_pin_43_[0]:34 left_top_grid_pin_43_[0]:8 0.002232892 +15 left_top_grid_pin_43_[0]:31 left_top_grid_pin_43_[0]:30 0.004066965 +16 left_top_grid_pin_43_[0]:32 left_top_grid_pin_43_[0]:31 0.0045 +17 left_top_grid_pin_43_[0]:7 left_top_grid_pin_43_[0]:6 0.0045 +18 left_top_grid_pin_43_[0]:8 left_top_grid_pin_43_[0]:7 0.00341 +19 left_top_grid_pin_43_[0]:6 left_top_grid_pin_43_[0]:5 0.001158482 +20 left_top_grid_pin_43_[0]:5 FTB_33__32:A 0.152 +21 left_top_grid_pin_43_[0]:21 left_top_grid_pin_43_[0]:20 0.0045 +22 left_top_grid_pin_43_[0]:20 left_top_grid_pin_43_[0]:19 0.002388393 +23 left_top_grid_pin_43_[0]:22 left_top_grid_pin_43_[0]:21 0.0015625 +24 left_top_grid_pin_43_[0]:23 left_top_grid_pin_43_[0]:22 0.0045 +25 left_top_grid_pin_43_[0]:24 left_top_grid_pin_43_[0]:23 0.01478348 +26 left_top_grid_pin_43_[0]:25 left_top_grid_pin_43_[0]:24 0.00341 +27 left_top_grid_pin_43_[0]:27 left_top_grid_pin_43_[0]:26 0.00341 +28 left_top_grid_pin_43_[0]:26 left_top_grid_pin_43_[0]:25 0.004465783 +29 left_top_grid_pin_43_[0]:29 left_top_grid_pin_43_[0]:28 0.0045 +30 left_top_grid_pin_43_[0]:29 left_top_grid_pin_43_[0]:9 9.239131e-05 +31 left_top_grid_pin_43_[0]:28 left_top_grid_pin_43_[0]:27 0.006890626 +32 left_top_grid_pin_43_[0]:37 left_top_grid_pin_43_[0]:36 0.01750446 +33 left_top_grid_pin_43_[0]:38 left_top_grid_pin_43_[0]:37 0.00341 +34 left_top_grid_pin_43_[0]:36 left_top_grid_pin_43_[0]:35 0.00341 +35 left_top_grid_pin_43_[0]:35 left_top_grid_pin_43_[0]:34 0.0005032916 +36 left_top_grid_pin_43_[0]:9 mux_left_track_3\/mux_l1_in_1_:A0 0.152 +37 left_top_grid_pin_43_[0]:30 left_top_grid_pin_43_[0]:29 0.0003035715 + +*END + +*D_NET top_left_grid_pin_41_[0] 0.008605693 //LENGTH 58.240 LUMPCC 0.003365347 DR + +*CONN +*P top_left_grid_pin_41_[0] I *L 0.29796 *C 29.818 117.640 +*I mux_top_track_4\/mux_l1_in_3_:A0 I *L 0.001631 *C 45.255 109.480 +*I mux_top_track_32\/mux_l1_in_0_:A0 I *L 0.001631 *C 45.715 96.900 +*I mux_top_track_2\/mux_l2_in_1_:A1 I *L 0.00198 *C 29.080 99.620 +*N top_left_grid_pin_41_[0]:4 *C 29.043 99.620 +*N top_left_grid_pin_41_[0]:5 *C 28.520 99.620 +*N top_left_grid_pin_41_[0]:6 *C 45.678 96.900 +*N top_left_grid_pin_41_[0]:7 *C 28.565 96.900 +*N top_left_grid_pin_41_[0]:8 *C 28.520 96.945 +*N top_left_grid_pin_41_[0]:9 *C 28.520 99.915 +*N top_left_grid_pin_41_[0]:10 *C 28.520 99.960 +*N top_left_grid_pin_41_[0]:11 *C 29.855 99.960 +*N top_left_grid_pin_41_[0]:12 *C 29.900 100.005 +*N top_left_grid_pin_41_[0]:13 *C 45.218 109.480 +*N top_left_grid_pin_41_[0]:14 *C 42.365 109.480 +*N top_left_grid_pin_41_[0]:15 *C 42.320 109.480 +*N top_left_grid_pin_41_[0]:16 *C 42.312 109.480 +*N top_left_grid_pin_41_[0]:17 *C 29.908 109.480 +*N top_left_grid_pin_41_[0]:18 *C 29.900 109.480 +*N top_left_grid_pin_41_[0]:19 *C 29.900 117.583 +*N top_left_grid_pin_41_[0]:20 *C 29.900 117.640 + +*CAP +0 top_left_grid_pin_41_[0] 3.385716e-05 +1 mux_top_track_4\/mux_l1_in_3_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_0_:A0 1e-06 +3 mux_top_track_2\/mux_l2_in_1_:A1 1e-06 +4 top_left_grid_pin_41_[0]:4 2.077775e-05 +5 top_left_grid_pin_41_[0]:5 5.01961e-05 +6 top_left_grid_pin_41_[0]:6 0.001014684 +7 top_left_grid_pin_41_[0]:7 0.001014684 +8 top_left_grid_pin_41_[0]:8 0.000194767 +9 top_left_grid_pin_41_[0]:9 0.000194767 +10 top_left_grid_pin_41_[0]:10 0.000127626 +11 top_left_grid_pin_41_[0]:11 9.820764e-05 +12 top_left_grid_pin_41_[0]:12 0.0002180021 +13 top_left_grid_pin_41_[0]:13 0.0002131513 +14 top_left_grid_pin_41_[0]:14 0.0002131513 +15 top_left_grid_pin_41_[0]:15 3.555694e-05 +16 top_left_grid_pin_41_[0]:16 0.0006570042 +17 top_left_grid_pin_41_[0]:17 0.0006570042 +18 top_left_grid_pin_41_[0]:18 0.000353521 +19 top_left_grid_pin_41_[0]:19 0.0001065311 +20 top_left_grid_pin_41_[0]:20 3.385716e-05 +21 top_left_grid_pin_41_[0]:18 chany_top_in[19]:14 0.0002399138 +22 top_left_grid_pin_41_[0]:18 chany_top_in[19]:15 0.0002085208 +23 top_left_grid_pin_41_[0]:12 chany_top_in[19]:14 0.0002085208 +24 top_left_grid_pin_41_[0]:19 chany_top_in[19]:15 0.0002399138 +25 top_left_grid_pin_41_[0]:18 left_top_grid_pin_43_[0]:36 0.0002399138 +26 top_left_grid_pin_41_[0]:18 left_top_grid_pin_43_[0]:37 0.0002604889 +27 top_left_grid_pin_41_[0]:9 left_top_grid_pin_43_[0]:33 1.637249e-05 +28 top_left_grid_pin_41_[0]:8 left_top_grid_pin_43_[0]:32 1.637249e-05 +29 top_left_grid_pin_41_[0]:12 left_top_grid_pin_43_[0]:36 0.0002604889 +30 top_left_grid_pin_41_[0]:19 left_top_grid_pin_43_[0]:37 0.0002399138 +31 top_left_grid_pin_41_[0]:17 mux_tree_tapbuf_size8_0_sram[1]:29 0.0003903395 +32 top_left_grid_pin_41_[0]:16 mux_tree_tapbuf_size8_0_sram[1]:30 0.0003903395 +33 top_left_grid_pin_41_[0]:10 mux_tree_tapbuf_size8_0_sram[1]:23 4.139449e-06 +34 top_left_grid_pin_41_[0]:10 mux_tree_tapbuf_size8_0_sram[1]:21 1.129405e-05 +35 top_left_grid_pin_41_[0]:10 mux_tree_tapbuf_size8_0_sram[1]:22 7.384707e-06 +36 top_left_grid_pin_41_[0]:9 mux_tree_tapbuf_size8_0_sram[1]:20 1.421999e-06 +37 top_left_grid_pin_41_[0]:7 mux_tree_tapbuf_size8_0_sram[1]:16 1.35923e-05 +38 top_left_grid_pin_41_[0]:8 mux_tree_tapbuf_size8_0_sram[1]:19 1.421999e-06 +39 top_left_grid_pin_41_[0]:6 mux_tree_tapbuf_size8_0_sram[1]:15 1.35923e-05 +40 top_left_grid_pin_41_[0]:11 mux_tree_tapbuf_size8_0_sram[1]:24 4.139449e-06 +41 top_left_grid_pin_41_[0]:11 mux_tree_tapbuf_size8_0_sram[1]:23 7.384707e-06 +42 top_left_grid_pin_41_[0]:11 mux_tree_tapbuf_size8_0_sram[1]:22 1.129405e-05 +43 top_left_grid_pin_41_[0]:4 mux_tree_tapbuf_size8_0_sram[1]:22 2.794115e-05 +44 top_left_grid_pin_41_[0]:5 mux_tree_tapbuf_size8_0_sram[1]:21 2.794115e-05 +45 top_left_grid_pin_41_[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001179937 +46 top_left_grid_pin_41_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001179937 +47 top_left_grid_pin_41_[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001433568 +48 top_left_grid_pin_41_[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001433568 + +*RES +0 top_left_grid_pin_41_[0] top_left_grid_pin_41_[0]:20 2.35e-05 +1 top_left_grid_pin_41_[0]:18 top_left_grid_pin_41_[0]:17 0.00341 +2 top_left_grid_pin_41_[0]:18 top_left_grid_pin_41_[0]:12 0.008459821 +3 top_left_grid_pin_41_[0]:17 top_left_grid_pin_41_[0]:16 0.00194345 +4 top_left_grid_pin_41_[0]:15 top_left_grid_pin_41_[0]:14 0.0045 +5 top_left_grid_pin_41_[0]:16 top_left_grid_pin_41_[0]:15 0.00341 +6 top_left_grid_pin_41_[0]:14 top_left_grid_pin_41_[0]:13 0.002546875 +7 top_left_grid_pin_41_[0]:13 mux_top_track_4\/mux_l1_in_3_:A0 0.152 +8 top_left_grid_pin_41_[0]:10 top_left_grid_pin_41_[0]:9 0.0045 +9 top_left_grid_pin_41_[0]:10 top_left_grid_pin_41_[0]:5 0.0003035715 +10 top_left_grid_pin_41_[0]:9 top_left_grid_pin_41_[0]:8 0.002651786 +11 top_left_grid_pin_41_[0]:7 top_left_grid_pin_41_[0]:6 0.01527902 +12 top_left_grid_pin_41_[0]:8 top_left_grid_pin_41_[0]:7 0.0045 +13 top_left_grid_pin_41_[0]:6 mux_top_track_32\/mux_l1_in_0_:A0 0.152 +14 top_left_grid_pin_41_[0]:11 top_left_grid_pin_41_[0]:10 0.001191964 +15 top_left_grid_pin_41_[0]:12 top_left_grid_pin_41_[0]:11 0.0045 +16 top_left_grid_pin_41_[0]:4 mux_top_track_2\/mux_l2_in_1_:A1 0.152 +17 top_left_grid_pin_41_[0]:19 top_left_grid_pin_41_[0]:18 0.007234375 +18 top_left_grid_pin_41_[0]:20 top_left_grid_pin_41_[0]:19 0.00341 +19 top_left_grid_pin_41_[0]:5 top_left_grid_pin_41_[0]:4 0.0004665179 + +*END + +*D_NET bottom_left_grid_pin_38_[0] 0.006066889 //LENGTH 52.757 LUMPCC 0.0007637356 DR + +*CONN +*P bottom_left_grid_pin_38_[0] I *L 0.29796 *C 29.825 4.760 +*I mux_bottom_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 25.300 34.340 +*I mux_bottom_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 37.435 38.760 +*I mux_bottom_track_5\/mux_l1_in_3_:A0 I *L 0.001631 *C 33.295 4.760 +*N bottom_left_grid_pin_38_[0]:4 *C 33.258 4.760 +*N bottom_left_grid_pin_38_[0]:5 *C 32.705 4.760 +*N bottom_left_grid_pin_38_[0]:6 *C 32.660 4.760 +*N bottom_left_grid_pin_38_[0]:7 *C 32.653 4.760 +*N bottom_left_grid_pin_38_[0]:8 *C 37.398 38.760 +*N bottom_left_grid_pin_38_[0]:9 *C 29.945 38.760 +*N bottom_left_grid_pin_38_[0]:10 *C 29.900 38.715 +*N bottom_left_grid_pin_38_[0]:11 *C 25.338 34.340 +*N bottom_left_grid_pin_38_[0]:12 *C 29.855 34.340 +*N bottom_left_grid_pin_38_[0]:13 *C 29.900 34.340 +*N bottom_left_grid_pin_38_[0]:14 *C 29.900 24.140 +*N bottom_left_grid_pin_38_[0]:15 *C 29.440 24.140 +*N bottom_left_grid_pin_38_[0]:16 *C 29.440 12.240 +*N bottom_left_grid_pin_38_[0]:17 *C 29.900 12.240 +*N bottom_left_grid_pin_38_[0]:18 *C 29.900 4.817 +*N bottom_left_grid_pin_38_[0]:19 *C 29.908 4.760 + +*CAP +0 bottom_left_grid_pin_38_[0] 2.827837e-05 +1 mux_bottom_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_5\/mux_l1_in_3_:A0 1e-06 +4 bottom_left_grid_pin_38_[0]:4 6.070996e-05 +5 bottom_left_grid_pin_38_[0]:5 6.070996e-05 +6 bottom_left_grid_pin_38_[0]:6 3.567623e-05 +7 bottom_left_grid_pin_38_[0]:7 0.0001896681 +8 bottom_left_grid_pin_38_[0]:8 0.0005388496 +9 bottom_left_grid_pin_38_[0]:9 0.0005388496 +10 bottom_left_grid_pin_38_[0]:10 0.0002182327 +11 bottom_left_grid_pin_38_[0]:11 0.0002803647 +12 bottom_left_grid_pin_38_[0]:12 0.0002803647 +13 bottom_left_grid_pin_38_[0]:13 0.0007135581 +14 bottom_left_grid_pin_38_[0]:14 0.0004841789 +15 bottom_left_grid_pin_38_[0]:15 0.0004442257 +16 bottom_left_grid_pin_38_[0]:16 0.0004473155 +17 bottom_left_grid_pin_38_[0]:17 0.0003931874 +18 bottom_left_grid_pin_38_[0]:18 0.0003680368 +19 bottom_left_grid_pin_38_[0]:19 0.0002179465 +20 bottom_left_grid_pin_38_[0]:11 bottom_left_grid_pin_40_[0]:9 1.440243e-05 +21 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_40_[0]:10 1.207949e-05 +22 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_40_[0]:5 2.322941e-06 +23 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_40_[0]:15 0.0001366075 +24 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_40_[0]:20 7.588556e-05 +25 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_40_[0]:16 0.0001006505 +26 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_40_[0]:19 7.588556e-05 +27 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_40_[0]:15 0.0001006505 +28 bottom_left_grid_pin_38_[0]:14 bottom_left_grid_pin_40_[0]:16 0.0001366075 +29 bottom_left_grid_pin_38_[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.063589e-05 +30 bottom_left_grid_pin_38_[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.063589e-05 +31 bottom_left_grid_pin_38_[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.156978e-06 +32 bottom_left_grid_pin_38_[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.452882e-05 +33 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.452882e-05 +34 bottom_left_grid_pin_38_[0]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.156978e-06 + +*RES +0 bottom_left_grid_pin_38_[0] bottom_left_grid_pin_38_[0]:19 2.35e-05 +1 bottom_left_grid_pin_38_[0]:18 bottom_left_grid_pin_38_[0]:17 0.006627232 +2 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_38_[0]:18 0.00341 +3 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_38_[0]:7 0.00043005 +4 bottom_left_grid_pin_38_[0]:11 mux_bottom_track_3\/mux_l2_in_1_:A1 0.152 +5 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_38_[0]:11 0.004033482 +6 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:12 0.0045 +7 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:10 0.00390625 +8 bottom_left_grid_pin_38_[0]:9 bottom_left_grid_pin_38_[0]:8 0.006654019 +9 bottom_left_grid_pin_38_[0]:10 bottom_left_grid_pin_38_[0]:9 0.0045 +10 bottom_left_grid_pin_38_[0]:8 mux_bottom_track_17\/mux_l1_in_1_:A0 0.152 +11 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_38_[0]:5 0.0045 +12 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_38_[0]:6 0.00341 +13 bottom_left_grid_pin_38_[0]:5 bottom_left_grid_pin_38_[0]:4 0.0004933036 +14 bottom_left_grid_pin_38_[0]:4 mux_bottom_track_5\/mux_l1_in_3_:A0 0.152 +15 bottom_left_grid_pin_38_[0]:16 bottom_left_grid_pin_38_[0]:15 0.010625 +16 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_38_[0]:14 0.0004107143 +17 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_38_[0]:16 0.0004107143 +18 bottom_left_grid_pin_38_[0]:14 bottom_left_grid_pin_38_[0]:13 0.009107143 + +*END + +*D_NET chanx_left_in[5] 0.01207723 //LENGTH 93.380 LUMPCC 0.001720181 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 87.040 +*I mux_bottom_track_17\/mux_l1_in_2_:A1 I *L 0.00198 *C 41.860 56.100 +*I mux_top_track_4\/mux_l1_in_5_:A0 I *L 0.001631 *C 47.555 98.940 +*N chanx_left_in[5]:3 *C 47.518 98.940 +*N chanx_left_in[5]:4 *C 43.745 98.940 +*N chanx_left_in[5]:5 *C 43.700 98.895 +*N chanx_left_in[5]:6 *C 41.898 56.100 +*N chanx_left_in[5]:7 *C 43.655 56.100 +*N chanx_left_in[5]:8 *C 43.700 56.145 +*N chanx_left_in[5]:9 *C 43.700 87.720 +*N chanx_left_in[5]:10 *C 43.693 87.720 +*N chanx_left_in[5]:11 *C 5.520 87.720 +*N chanx_left_in[5]:12 *C 5.520 87.040 + +*CAP +0 chanx_left_in[5] 0.0003303703 +1 mux_bottom_track_17\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_5_:A0 1e-06 +3 chanx_left_in[5]:3 0.0002347985 +4 chanx_left_in[5]:4 0.0002347985 +5 chanx_left_in[5]:5 0.0006301635 +6 chanx_left_in[5]:6 0.0001428545 +7 chanx_left_in[5]:7 0.0001428545 +8 chanx_left_in[5]:8 0.001404221 +9 chanx_left_in[5]:9 0.002070521 +10 chanx_left_in[5]:10 0.002349439 +11 chanx_left_in[5]:11 0.00241705 +12 chanx_left_in[5]:12 0.0003979818 +13 chanx_left_in[5]:8 prog_clk[0]:232 1.336076e-05 +14 chanx_left_in[5]:8 prog_clk[0]:233 3.072224e-05 +15 chanx_left_in[5]:8 prog_clk[0]:466 8.725238e-06 +16 chanx_left_in[5]:8 prog_clk[0]:469 1.110485e-06 +17 chanx_left_in[5]:5 prog_clk[0]:327 2.417549e-09 +18 chanx_left_in[5]:9 prog_clk[0]:229 1.336076e-05 +19 chanx_left_in[5]:9 prog_clk[0]:232 3.072224e-05 +20 chanx_left_in[5]:9 prog_clk[0]:328 2.417549e-09 +21 chanx_left_in[5]:9 prog_clk[0]:404 8.725238e-06 +22 chanx_left_in[5]:9 prog_clk[0]:466 1.110485e-06 +23 chanx_left_in[5]:10 prog_clk[0]:282 5.864703e-05 +24 chanx_left_in[5]:10 prog_clk[0]:343 0.0002439078 +25 chanx_left_in[5]:11 prog_clk[0]:283 5.864703e-05 +26 chanx_left_in[5]:11 prog_clk[0]:344 0.0002439078 +27 chanx_left_in[5]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003380351 +28 chanx_left_in[5]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003380351 +29 chanx_left_in[5]:8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001655792 +30 chanx_left_in[5]:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001655792 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:12 0.0006720999 +1 chanx_left_in[5]:7 chanx_left_in[5]:6 0.001569197 +2 chanx_left_in[5]:8 chanx_left_in[5]:7 0.0045 +3 chanx_left_in[5]:6 mux_bottom_track_17\/mux_l1_in_2_:A1 0.152 +4 chanx_left_in[5]:4 chanx_left_in[5]:3 0.003368304 +5 chanx_left_in[5]:5 chanx_left_in[5]:4 0.0045 +6 chanx_left_in[5]:3 mux_top_track_4\/mux_l1_in_5_:A0 0.152 +7 chanx_left_in[5]:9 chanx_left_in[5]:8 0.02819197 +8 chanx_left_in[5]:9 chanx_left_in[5]:5 0.00997768 +9 chanx_left_in[5]:10 chanx_left_in[5]:9 0.00341 +10 chanx_left_in[5]:12 chanx_left_in[5]:11 0.0001065333 +11 chanx_left_in[5]:11 chanx_left_in[5]:10 0.005980358 + +*END + +*D_NET chanx_left_in[12] 0.01380764 //LENGTH 90.405 LUMPCC 0.004029066 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 97.920 +*I mux_top_track_4\/mux_l1_in_6_:A1 I *L 0.00198 *C 40.580 96.220 +*I mux_bottom_track_17\/mux_l1_in_2_:A0 I *L 0.001631 *C 41.575 55.080 +*N chanx_left_in[12]:3 *C 42.840 96.560 +*N chanx_left_in[12]:4 *C 41.575 55.080 +*N chanx_left_in[12]:5 *C 41.860 55.080 +*N chanx_left_in[12]:6 *C 41.860 55.125 +*N chanx_left_in[12]:7 *C 41.860 59.783 +*N chanx_left_in[12]:8 *C 41.867 59.840 +*N chanx_left_in[12]:9 *C 43.220 59.840 +*N chanx_left_in[12]:10 *C 43.240 59.848 +*N chanx_left_in[12]:11 *C 43.240 96.553 +*N chanx_left_in[12]:12 *C 43.240 96.560 +*N chanx_left_in[12]:13 *C 43.240 96.560 +*N chanx_left_in[12]:14 *C 43.195 96.560 +*N chanx_left_in[12]:15 *C 40.580 96.220 +*N chanx_left_in[12]:16 *C 40.547 96.560 +*N chanx_left_in[12]:17 *C 40.480 96.560 +*N chanx_left_in[12]:18 *C 40.020 96.560 +*N chanx_left_in[12]:19 *C 40.020 97.183 +*N chanx_left_in[12]:20 *C 40.013 97.240 +*N chanx_left_in[12]:21 *C 2.760 97.240 +*N chanx_left_in[12]:22 *C 2.760 97.920 + +*CAP +0 chanx_left_in[12] 0.0001507824 +1 mux_top_track_4\/mux_l1_in_6_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_2_:A0 1e-06 +3 chanx_left_in[12]:3 0.0001015022 +4 chanx_left_in[12]:4 5.711676e-05 +5 chanx_left_in[12]:5 6.163812e-05 +6 chanx_left_in[12]:6 0.0003085001 +7 chanx_left_in[12]:7 0.0003085001 +8 chanx_left_in[12]:8 0.0001807038 +9 chanx_left_in[12]:9 0.0001807038 +10 chanx_left_in[12]:10 0.001908221 +11 chanx_left_in[12]:11 0.001908221 +12 chanx_left_in[12]:12 0.0001015022 +13 chanx_left_in[12]:13 3.760216e-05 +14 chanx_left_in[12]:14 0.0002354313 +15 chanx_left_in[12]:15 5.943517e-05 +16 chanx_left_in[12]:16 0.0002678687 +17 chanx_left_in[12]:17 6.879184e-05 +18 chanx_left_in[12]:18 9.63653e-05 +19 chanx_left_in[12]:19 6.098822e-05 +20 chanx_left_in[12]:20 0.001714785 +21 chanx_left_in[12]:21 0.001765959 +22 chanx_left_in[12]:22 0.0002019568 +23 chanx_left_in[12]:20 chany_top_in[3]:6 0.001044179 +24 chanx_left_in[12]:21 chany_top_in[3]:5 0.001044179 +25 chanx_left_in[12]:11 chany_top_in[4]:29 0.0003516096 +26 chanx_left_in[12]:11 chany_top_in[4]:30 0.000332031 +27 chanx_left_in[12]:9 chany_top_in[4]:21 9.95198e-07 +28 chanx_left_in[12]:10 chany_top_in[4]:22 0.0003516096 +29 chanx_left_in[12]:10 chany_top_in[4]:29 0.000332031 +30 chanx_left_in[12]:8 chany_top_in[4]:20 9.95198e-07 +31 chanx_left_in[12]:20 left_top_grid_pin_43_[0]:34 0.0002324885 +32 chanx_left_in[12]:20 left_top_grid_pin_43_[0]:35 5.322972e-05 +33 chanx_left_in[12]:21 left_top_grid_pin_43_[0]:8 0.0002324885 +34 chanx_left_in[12]:21 left_top_grid_pin_43_[0]:34 5.322972e-05 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:22 0.0002397 +1 chanx_left_in[12]:16 chanx_left_in[12]:15 0.0001847826 +2 chanx_left_in[12]:16 chanx_left_in[12]:14 0.002363839 +3 chanx_left_in[12]:17 chanx_left_in[12]:16 0.0045 +4 chanx_left_in[12]:19 chanx_left_in[12]:18 0.0005558036 +5 chanx_left_in[12]:20 chanx_left_in[12]:19 0.00341 +6 chanx_left_in[12]:14 chanx_left_in[12]:13 0.0045 +7 chanx_left_in[12]:13 chanx_left_in[12]:12 0.00341 +8 chanx_left_in[12]:12 chanx_left_in[12]:11 0.00341 +9 chanx_left_in[12]:12 chanx_left_in[12]:3 5.69697e-05 +10 chanx_left_in[12]:11 chanx_left_in[12]:10 0.00575045 +11 chanx_left_in[12]:9 chanx_left_in[12]:8 0.0002118916 +12 chanx_left_in[12]:10 chanx_left_in[12]:9 0.00341 +13 chanx_left_in[12]:7 chanx_left_in[12]:6 0.004158482 +14 chanx_left_in[12]:8 chanx_left_in[12]:7 0.00341 +15 chanx_left_in[12]:5 chanx_left_in[12]:4 0.0001548913 +16 chanx_left_in[12]:6 chanx_left_in[12]:5 0.0045 +17 chanx_left_in[12]:4 mux_bottom_track_17\/mux_l1_in_2_:A0 0.152 +18 chanx_left_in[12]:15 mux_top_track_4\/mux_l1_in_6_:A1 0.152 +19 chanx_left_in[12]:18 chanx_left_in[12]:17 0.0004107143 +20 chanx_left_in[12]:22 chanx_left_in[12]:21 0.0001065333 +21 chanx_left_in[12]:21 chanx_left_in[12]:20 0.005836225 + +*END + +*D_NET chany_top_out[1] 0.001793834 //LENGTH 12.510 LUMPCC 8.148342e-05 DR + +*CONN +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 56.180 123.760 +*P chany_top_out[1] O *L 0.7423 *C 61.180 129.235 +*N chany_top_out[1]:2 *C 61.180 128.565 +*N chany_top_out[1]:3 *C 61.135 128.520 +*N chany_top_out[1]:4 *C 59.845 128.520 +*N chany_top_out[1]:5 *C 59.800 128.475 +*N chany_top_out[1]:6 *C 59.800 123.465 +*N chany_top_out[1]:7 *C 59.755 123.420 +*N chany_top_out[1]:8 *C 57.040 123.420 +*N chany_top_out[1]:9 *C 57.040 123.760 +*N chany_top_out[1]:10 *C 56.180 123.760 + +*CAP +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[1] 5.713286e-05 +2 chany_top_out[1]:2 5.713286e-05 +3 chany_top_out[1]:3 0.0001408148 +4 chany_top_out[1]:4 0.0001408148 +5 chany_top_out[1]:5 0.0003409134 +6 chany_top_out[1]:6 0.0003409134 +7 chany_top_out[1]:7 0.0001919456 +8 chany_top_out[1]:8 0.0002200172 +9 chany_top_out[1]:9 0.0001035882 +10 chany_top_out[1]:10 0.0001180775 +11 chany_top_out[1]:7 ropt_net_172:6 3.370913e-05 +12 chany_top_out[1]:6 ropt_net_172:4 7.03258e-06 +13 chany_top_out[1]:5 ropt_net_172:5 7.03258e-06 +14 chany_top_out[1]:8 ropt_net_172:7 3.370913e-05 + +*RES +0 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[1]:10 0.152 +1 chany_top_out[1]:10 chany_top_out[1]:9 0.0007678572 +2 chany_top_out[1]:7 chany_top_out[1]:6 0.0045 +3 chany_top_out[1]:6 chany_top_out[1]:5 0.004473215 +4 chany_top_out[1]:4 chany_top_out[1]:3 0.001151786 +5 chany_top_out[1]:5 chany_top_out[1]:4 0.0045 +6 chany_top_out[1]:3 chany_top_out[1]:2 0.0045 +7 chany_top_out[1]:2 chany_top_out[1] 0.0005982143 +8 chany_top_out[1]:9 chany_top_out[1]:8 0.0003035715 +9 chany_top_out[1]:8 chany_top_out[1]:7 0.002424107 + +*END + +*D_NET chanx_left_out[0] 0.002015383 //LENGTH 16.720 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.845 71.740 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 61.200 +*N chanx_left_out[0]:2 *C 6.893 61.200 +*N chanx_left_out[0]:3 *C 6.900 61.258 +*N chanx_left_out[0]:4 *C 6.900 71.695 +*N chanx_left_out[0]:5 *C 6.845 71.740 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 0.0003897696 +2 chanx_left_out[0]:2 0.0003897696 +3 chanx_left_out[0]:3 0.00060235 +4 chanx_left_out[0]:4 0.00060235 +5 chanx_left_out[0]:5 3.01432e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:5 0.152 +1 chanx_left_out[0]:5 chanx_left_out[0]:4 0.0045 +2 chanx_left_out[0]:4 chanx_left_out[0]:3 0.009319196 +3 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +4 chanx_left_out[0]:2 chanx_left_out[0] 0.0008871249 + +*END + +*D_NET chanx_left_out[12] 0.0009098418 //LENGTH 5.025 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 5.465 44.540 +*P chanx_left_out[12] O *L 0.7423 *C 1.230 44.880 +*N chanx_left_out[12]:2 *C 4.593 44.880 +*N chanx_left_out[12]:3 *C 4.600 44.880 +*N chanx_left_out[12]:4 *C 4.600 44.540 +*N chanx_left_out[12]:5 *C 4.645 44.540 +*N chanx_left_out[12]:6 *C 5.428 44.540 + +*CAP +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[12] 0.0003273112 +2 chanx_left_out[12]:2 0.0003273112 +3 chanx_left_out[12]:3 6.08565e-05 +4 chanx_left_out[12]:4 5.771822e-05 +5 chanx_left_out[12]:5 6.782234e-05 +6 chanx_left_out[12]:6 6.782234e-05 + +*RES +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[12]:6 0.152 +1 chanx_left_out[12]:6 chanx_left_out[12]:5 0.0006986608 +2 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0045 +3 chanx_left_out[12]:4 chanx_left_out[12]:3 0.000125 +4 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +5 chanx_left_out[12]:2 chanx_left_out[12] 0.0005267917 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[3] 0.002183961 //LENGTH 18.810 LUMPCC 0.0001711457 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 47.685 25.840 +*I mux_bottom_track_1\/mux_l4_in_0_:S I *L 0.00357 *C 44.520 23.415 +*I mem_bottom_track_1\/FTB_2__34:A I *L 0.001746 *C 38.640 28.560 +*N mux_tree_tapbuf_size10_1_sram[3]:3 *C 38.678 28.560 +*N mux_tree_tapbuf_size10_1_sram[3]:4 *C 42.275 28.560 +*N mux_tree_tapbuf_size10_1_sram[3]:5 *C 42.320 28.515 +*N mux_tree_tapbuf_size10_1_sram[3]:6 *C 42.320 23.165 +*N mux_tree_tapbuf_size10_1_sram[3]:7 *C 42.365 23.120 +*N mux_tree_tapbuf_size10_1_sram[3]:8 *C 44.462 23.120 +*N mux_tree_tapbuf_size10_1_sram[3]:9 *C 44.558 23.460 +*N mux_tree_tapbuf_size10_1_sram[3]:10 *C 47.335 23.460 +*N mux_tree_tapbuf_size10_1_sram[3]:11 *C 47.380 23.505 +*N mux_tree_tapbuf_size10_1_sram[3]:12 *C 47.380 25.795 +*N mux_tree_tapbuf_size10_1_sram[3]:13 *C 47.380 25.840 +*N mux_tree_tapbuf_size10_1_sram[3]:14 *C 47.685 25.840 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_bottom_track_1\/mux_l4_in_0_:S 1e-06 +2 mem_bottom_track_1\/FTB_2__34:A 1e-06 +3 mux_tree_tapbuf_size10_1_sram[3]:3 0.0002246377 +4 mux_tree_tapbuf_size10_1_sram[3]:4 0.0002246377 +5 mux_tree_tapbuf_size10_1_sram[3]:5 0.0002350906 +6 mux_tree_tapbuf_size10_1_sram[3]:6 0.0002350906 +7 mux_tree_tapbuf_size10_1_sram[3]:7 0.0001292203 +8 mux_tree_tapbuf_size10_1_sram[3]:8 0.000155752 +9 mux_tree_tapbuf_size10_1_sram[3]:9 0.0002289615 +10 mux_tree_tapbuf_size10_1_sram[3]:10 0.0002024298 +11 mux_tree_tapbuf_size10_1_sram[3]:11 0.0001318228 +12 mux_tree_tapbuf_size10_1_sram[3]:12 0.0001318228 +13 mux_tree_tapbuf_size10_1_sram[3]:13 5.722664e-05 +14 mux_tree_tapbuf_size10_1_sram[3]:14 5.312248e-05 +15 mux_tree_tapbuf_size10_1_sram[3]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.363212e-05 +16 mux_tree_tapbuf_size10_1_sram[3]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 7.194074e-05 +17 mux_tree_tapbuf_size10_1_sram[3]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 7.194074e-05 +18 mux_tree_tapbuf_size10_1_sram[3]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.363212e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_1_sram[3]:14 0.152 +1 mux_tree_tapbuf_size10_1_sram[3]:9 mux_bottom_track_1\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[3]:9 mux_tree_tapbuf_size10_1_sram[3]:8 0.0001976745 +3 mux_tree_tapbuf_size10_1_sram[3]:10 mux_tree_tapbuf_size10_1_sram[3]:9 0.002479911 +4 mux_tree_tapbuf_size10_1_sram[3]:11 mux_tree_tapbuf_size10_1_sram[3]:10 0.0045 +5 mux_tree_tapbuf_size10_1_sram[3]:13 mux_tree_tapbuf_size10_1_sram[3]:12 0.0045 +6 mux_tree_tapbuf_size10_1_sram[3]:12 mux_tree_tapbuf_size10_1_sram[3]:11 0.002044643 +7 mux_tree_tapbuf_size10_1_sram[3]:14 mux_tree_tapbuf_size10_1_sram[3]:13 0.0001657609 +8 mux_tree_tapbuf_size10_1_sram[3]:7 mux_tree_tapbuf_size10_1_sram[3]:6 0.0045 +9 mux_tree_tapbuf_size10_1_sram[3]:6 mux_tree_tapbuf_size10_1_sram[3]:5 0.004776786 +10 mux_tree_tapbuf_size10_1_sram[3]:4 mux_tree_tapbuf_size10_1_sram[3]:3 0.003212054 +11 mux_tree_tapbuf_size10_1_sram[3]:5 mux_tree_tapbuf_size10_1_sram[3]:4 0.0045 +12 mux_tree_tapbuf_size10_1_sram[3]:3 mem_bottom_track_1\/FTB_2__34:A 0.152 +13 mux_tree_tapbuf_size10_1_sram[3]:8 mux_tree_tapbuf_size10_1_sram[3]:7 0.001872768 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[2] 0.003074021 //LENGTH 25.590 LUMPCC 0.0003308732 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 46.765 17.340 +*I mux_bottom_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 43.600 9.230 +*I mux_bottom_track_5\/mux_l3_in_1_:S I *L 0.00357 *C 39.920 14.280 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 43.875 15.300 +*N mux_tree_tapbuf_size14_1_sram[2]:4 *C 43.913 15.300 +*N mux_tree_tapbuf_size14_1_sram[2]:5 *C 39.883 14.280 +*N mux_tree_tapbuf_size14_1_sram[2]:6 *C 37.765 14.280 +*N mux_tree_tapbuf_size14_1_sram[2]:7 *C 37.720 14.235 +*N mux_tree_tapbuf_size14_1_sram[2]:8 *C 37.720 12.625 +*N mux_tree_tapbuf_size14_1_sram[2]:9 *C 37.765 12.580 +*N mux_tree_tapbuf_size14_1_sram[2]:10 *C 43.655 12.580 +*N mux_tree_tapbuf_size14_1_sram[2]:11 *C 43.700 12.535 +*N mux_tree_tapbuf_size14_1_sram[2]:12 *C 43.600 9.230 +*N mux_tree_tapbuf_size14_1_sram[2]:13 *C 43.700 9.520 +*N mux_tree_tapbuf_size14_1_sram[2]:14 *C 43.700 9.565 +*N mux_tree_tapbuf_size14_1_sram[2]:15 *C 43.700 11.560 +*N mux_tree_tapbuf_size14_1_sram[2]:16 *C 44.160 11.560 +*N mux_tree_tapbuf_size14_1_sram[2]:17 *C 44.160 13.260 +*N mux_tree_tapbuf_size14_1_sram[2]:18 *C 44.620 13.260 +*N mux_tree_tapbuf_size14_1_sram[2]:19 *C 44.620 15.255 +*N mux_tree_tapbuf_size14_1_sram[2]:20 *C 44.620 15.300 +*N mux_tree_tapbuf_size14_1_sram[2]:21 *C 46.415 15.300 +*N mux_tree_tapbuf_size14_1_sram[2]:22 *C 46.460 15.345 +*N mux_tree_tapbuf_size14_1_sram[2]:23 *C 46.460 17.295 +*N mux_tree_tapbuf_size14_1_sram[2]:24 *C 46.460 17.340 +*N mux_tree_tapbuf_size14_1_sram[2]:25 *C 46.765 17.340 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_track_5\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size14_1_sram[2]:4 5.938855e-05 +5 mux_tree_tapbuf_size14_1_sram[2]:5 0.0001630991 +6 mux_tree_tapbuf_size14_1_sram[2]:6 0.0001630991 +7 mux_tree_tapbuf_size14_1_sram[2]:7 9.9849e-05 +8 mux_tree_tapbuf_size14_1_sram[2]:8 9.9849e-05 +9 mux_tree_tapbuf_size14_1_sram[2]:9 0.0002927747 +10 mux_tree_tapbuf_size14_1_sram[2]:10 0.0002927747 +11 mux_tree_tapbuf_size14_1_sram[2]:11 2.528026e-05 +12 mux_tree_tapbuf_size14_1_sram[2]:12 7.166169e-05 +13 mux_tree_tapbuf_size14_1_sram[2]:13 7.670869e-05 +14 mux_tree_tapbuf_size14_1_sram[2]:14 0.0001064984 +15 mux_tree_tapbuf_size14_1_sram[2]:15 0.0001373247 +16 mux_tree_tapbuf_size14_1_sram[2]:16 9.688671e-05 +17 mux_tree_tapbuf_size14_1_sram[2]:17 0.0001002948 +18 mux_tree_tapbuf_size14_1_sram[2]:18 0.0001325541 +19 mux_tree_tapbuf_size14_1_sram[2]:19 0.0001235999 +20 mux_tree_tapbuf_size14_1_sram[2]:20 0.0002144048 +21 mux_tree_tapbuf_size14_1_sram[2]:21 0.0001238331 +22 mux_tree_tapbuf_size14_1_sram[2]:22 0.0001317053 +23 mux_tree_tapbuf_size14_1_sram[2]:23 0.0001317053 +24 mux_tree_tapbuf_size14_1_sram[2]:24 5.008979e-05 +25 mux_tree_tapbuf_size14_1_sram[2]:25 4.576611e-05 +26 mux_tree_tapbuf_size14_1_sram[2]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 9.02697e-06 +27 mux_tree_tapbuf_size14_1_sram[2]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 1.422895e-05 +28 mux_tree_tapbuf_size14_1_sram[2]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 1.422895e-05 +29 mux_tree_tapbuf_size14_1_sram[2]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 9.02697e-06 +30 mux_tree_tapbuf_size14_1_sram[2]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 3.33126e-05 +31 mux_tree_tapbuf_size14_1_sram[2]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 3.33126e-05 +32 mux_tree_tapbuf_size14_1_sram[2]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 6.173515e-05 +33 mux_tree_tapbuf_size14_1_sram[2]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 6.173515e-05 +34 mux_tree_tapbuf_size14_1_sram[2]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 2.357586e-06 +35 mux_tree_tapbuf_size14_1_sram[2]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 2.357586e-06 +36 mux_tree_tapbuf_size14_1_sram[2]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 2.313668e-05 +37 mux_tree_tapbuf_size14_1_sram[2]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 2.313668e-05 +38 mux_tree_tapbuf_size14_1_sram[2]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 1.137478e-06 +39 mux_tree_tapbuf_size14_1_sram[2]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 2.05012e-05 +40 mux_tree_tapbuf_size14_1_sram[2]:17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 1.137478e-06 +41 mux_tree_tapbuf_size14_1_sram[2]:18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 2.05012e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size14_1_sram[2]:25 0.152 +1 mux_tree_tapbuf_size14_1_sram[2]:20 mux_tree_tapbuf_size14_1_sram[2]:19 0.0045 +2 mux_tree_tapbuf_size14_1_sram[2]:20 mux_tree_tapbuf_size14_1_sram[2]:4 0.0006316965 +3 mux_tree_tapbuf_size14_1_sram[2]:19 mux_tree_tapbuf_size14_1_sram[2]:18 0.00178125 +4 mux_tree_tapbuf_size14_1_sram[2]:21 mux_tree_tapbuf_size14_1_sram[2]:20 0.001602679 +5 mux_tree_tapbuf_size14_1_sram[2]:22 mux_tree_tapbuf_size14_1_sram[2]:21 0.0045 +6 mux_tree_tapbuf_size14_1_sram[2]:24 mux_tree_tapbuf_size14_1_sram[2]:23 0.0045 +7 mux_tree_tapbuf_size14_1_sram[2]:23 mux_tree_tapbuf_size14_1_sram[2]:22 0.001741071 +8 mux_tree_tapbuf_size14_1_sram[2]:25 mux_tree_tapbuf_size14_1_sram[2]:24 0.0001657609 +9 mux_tree_tapbuf_size14_1_sram[2]:4 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +10 mux_tree_tapbuf_size14_1_sram[2]:10 mux_tree_tapbuf_size14_1_sram[2]:9 0.005258929 +11 mux_tree_tapbuf_size14_1_sram[2]:11 mux_tree_tapbuf_size14_1_sram[2]:10 0.0045 +12 mux_tree_tapbuf_size14_1_sram[2]:9 mux_tree_tapbuf_size14_1_sram[2]:8 0.0045 +13 mux_tree_tapbuf_size14_1_sram[2]:8 mux_tree_tapbuf_size14_1_sram[2]:7 0.0014375 +14 mux_tree_tapbuf_size14_1_sram[2]:6 mux_tree_tapbuf_size14_1_sram[2]:5 0.001890625 +15 mux_tree_tapbuf_size14_1_sram[2]:7 mux_tree_tapbuf_size14_1_sram[2]:6 0.0045 +16 mux_tree_tapbuf_size14_1_sram[2]:5 mux_bottom_track_5\/mux_l3_in_1_:S 0.152 +17 mux_tree_tapbuf_size14_1_sram[2]:13 mux_tree_tapbuf_size14_1_sram[2]:12 0.000125 +18 mux_tree_tapbuf_size14_1_sram[2]:14 mux_tree_tapbuf_size14_1_sram[2]:13 0.0045 +19 mux_tree_tapbuf_size14_1_sram[2]:12 mux_bottom_track_5\/mux_l3_in_0_:S 0.152 +20 mux_tree_tapbuf_size14_1_sram[2]:15 mux_tree_tapbuf_size14_1_sram[2]:14 0.00178125 +21 mux_tree_tapbuf_size14_1_sram[2]:15 mux_tree_tapbuf_size14_1_sram[2]:11 0.0008705358 +22 mux_tree_tapbuf_size14_1_sram[2]:16 mux_tree_tapbuf_size14_1_sram[2]:15 0.0004107143 +23 mux_tree_tapbuf_size14_1_sram[2]:17 mux_tree_tapbuf_size14_1_sram[2]:16 0.001517857 +24 mux_tree_tapbuf_size14_1_sram[2]:18 mux_tree_tapbuf_size14_1_sram[2]:17 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[1] 0.004699941 //LENGTH 38.190 LUMPCC 0.0001309325 DR + +*CONN +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 57.345 49.980 +*I mux_left_track_13\/mux_l2_in_1_:S I *L 0.00357 *C 27.500 50.660 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.835 47.940 +*I mux_left_track_13\/mux_l2_in_0_:S I *L 0.00357 *C 47.940 47.310 +*N mux_tree_tapbuf_size4_2_sram[1]:4 *C 47.940 47.310 +*N mux_tree_tapbuf_size4_2_sram[1]:5 *C 32.835 47.940 +*N mux_tree_tapbuf_size4_2_sram[1]:6 *C 27.538 50.660 +*N mux_tree_tapbuf_size4_2_sram[1]:7 *C 33.075 50.660 +*N mux_tree_tapbuf_size4_2_sram[1]:8 *C 33.120 50.615 +*N mux_tree_tapbuf_size4_2_sram[1]:9 *C 33.120 47.985 +*N mux_tree_tapbuf_size4_2_sram[1]:10 *C 33.165 47.940 +*N mux_tree_tapbuf_size4_2_sram[1]:11 *C 44.160 47.940 +*N mux_tree_tapbuf_size4_2_sram[1]:12 *C 44.160 47.600 +*N mux_tree_tapbuf_size4_2_sram[1]:13 *C 47.830 47.600 +*N mux_tree_tapbuf_size4_2_sram[1]:14 *C 55.155 47.600 +*N mux_tree_tapbuf_size4_2_sram[1]:15 *C 55.200 47.645 +*N mux_tree_tapbuf_size4_2_sram[1]:16 *C 55.200 49.935 +*N mux_tree_tapbuf_size4_2_sram[1]:17 *C 55.245 49.980 +*N mux_tree_tapbuf_size4_2_sram[1]:18 *C 57.308 49.980 + +*CAP +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_13\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_13\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_2_sram[1]:4 6.430811e-05 +5 mux_tree_tapbuf_size4_2_sram[1]:5 5.09469e-05 +6 mux_tree_tapbuf_size4_2_sram[1]:6 0.0003348264 +7 mux_tree_tapbuf_size4_2_sram[1]:7 0.0003348264 +8 mux_tree_tapbuf_size4_2_sram[1]:8 0.000169574 +9 mux_tree_tapbuf_size4_2_sram[1]:9 0.000169574 +10 mux_tree_tapbuf_size4_2_sram[1]:10 0.0007327006 +11 mux_tree_tapbuf_size4_2_sram[1]:11 0.000737117 +12 mux_tree_tapbuf_size4_2_sram[1]:12 0.0002987979 +13 mux_tree_tapbuf_size4_2_sram[1]:13 0.0007018151 +14 mux_tree_tapbuf_size4_2_sram[1]:14 0.0003961205 +15 mux_tree_tapbuf_size4_2_sram[1]:15 0.0001455235 +16 mux_tree_tapbuf_size4_2_sram[1]:16 0.0001455235 +17 mux_tree_tapbuf_size4_2_sram[1]:17 0.0001416775 +18 mux_tree_tapbuf_size4_2_sram[1]:18 0.0001416775 +19 mux_tree_tapbuf_size4_2_sram[1]:14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.546626e-05 +20 mux_tree_tapbuf_size4_2_sram[1]:13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.546626e-05 + +*RES +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_2_sram[1]:18 0.152 +1 mux_tree_tapbuf_size4_2_sram[1]:5 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size4_2_sram[1]:14 mux_tree_tapbuf_size4_2_sram[1]:13 0.006540179 +3 mux_tree_tapbuf_size4_2_sram[1]:15 mux_tree_tapbuf_size4_2_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size4_2_sram[1]:17 mux_tree_tapbuf_size4_2_sram[1]:16 0.0045 +5 mux_tree_tapbuf_size4_2_sram[1]:16 mux_tree_tapbuf_size4_2_sram[1]:15 0.002044643 +6 mux_tree_tapbuf_size4_2_sram[1]:18 mux_tree_tapbuf_size4_2_sram[1]:17 0.001841518 +7 mux_tree_tapbuf_size4_2_sram[1]:10 mux_tree_tapbuf_size4_2_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size4_2_sram[1]:10 mux_tree_tapbuf_size4_2_sram[1]:5 0.0001793478 +9 mux_tree_tapbuf_size4_2_sram[1]:9 mux_tree_tapbuf_size4_2_sram[1]:8 0.002348214 +10 mux_tree_tapbuf_size4_2_sram[1]:7 mux_tree_tapbuf_size4_2_sram[1]:6 0.004944197 +11 mux_tree_tapbuf_size4_2_sram[1]:8 mux_tree_tapbuf_size4_2_sram[1]:7 0.0045 +12 mux_tree_tapbuf_size4_2_sram[1]:6 mux_left_track_13\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size4_2_sram[1]:4 mux_left_track_13\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size4_2_sram[1]:11 mux_tree_tapbuf_size4_2_sram[1]:10 0.009816965 +15 mux_tree_tapbuf_size4_2_sram[1]:12 mux_tree_tapbuf_size4_2_sram[1]:11 0.0003035715 +16 mux_tree_tapbuf_size4_2_sram[1]:13 mux_tree_tapbuf_size4_2_sram[1]:12 0.003276786 +17 mux_tree_tapbuf_size4_2_sram[1]:13 mux_tree_tapbuf_size4_2_sram[1]:4 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[0] 0.01242275 //LENGTH 88.325 LUMPCC 0.003361616 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 68.845 99.280 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 50.315 86.020 +*I mux_top_track_16\/mux_l1_in_3_:S I *L 0.00357 *C 38.540 67.320 +*I mux_top_track_16\/mux_l1_in_2_:S I *L 0.00357 *C 38.540 56.440 +*I mux_top_track_16\/mux_l1_in_0_:S I *L 0.00357 *C 50.960 106.760 +*I mux_top_track_16\/mux_l1_in_1_:S I *L 0.00357 *C 62.660 96.220 +*N mux_tree_tapbuf_size7_0_sram[0]:6 *C 62.698 96.220 +*N mux_tree_tapbuf_size7_0_sram[0]:7 *C 63.020 96.220 +*N mux_tree_tapbuf_size7_0_sram[0]:8 *C 50.960 106.760 +*N mux_tree_tapbuf_size7_0_sram[0]:9 *C 51.060 106.715 +*N mux_tree_tapbuf_size7_0_sram[0]:10 *C 51.060 97.335 +*N mux_tree_tapbuf_size7_0_sram[0]:11 *C 38.540 56.440 +*N mux_tree_tapbuf_size7_0_sram[0]:12 *C 38.640 56.485 +*N mux_tree_tapbuf_size7_0_sram[0]:13 *C 38.540 67.320 +*N mux_tree_tapbuf_size7_0_sram[0]:14 *C 38.640 66.980 +*N mux_tree_tapbuf_size7_0_sram[0]:15 *C 38.640 66.980 +*N mux_tree_tapbuf_size7_0_sram[0]:16 *C 39.100 66.980 +*N mux_tree_tapbuf_size7_0_sram[0]:17 *C 39.100 76.782 +*N mux_tree_tapbuf_size7_0_sram[0]:18 *C 39.108 76.840 +*N mux_tree_tapbuf_size7_0_sram[0]:19 *C 50.133 76.840 +*N mux_tree_tapbuf_size7_0_sram[0]:20 *C 50.140 76.898 +*N mux_tree_tapbuf_size7_0_sram[0]:21 *C 50.140 85.975 +*N mux_tree_tapbuf_size7_0_sram[0]:22 *C 50.140 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:23 *C 50.315 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:24 *C 50.600 86.020 +*N mux_tree_tapbuf_size7_0_sram[0]:25 *C 50.600 86.065 +*N mux_tree_tapbuf_size7_0_sram[0]:26 *C 50.600 96.900 +*N mux_tree_tapbuf_size7_0_sram[0]:27 *C 51.015 96.900 +*N mux_tree_tapbuf_size7_0_sram[0]:28 *C 51.060 97.365 +*N mux_tree_tapbuf_size7_0_sram[0]:29 *C 51.105 97.240 +*N mux_tree_tapbuf_size7_0_sram[0]:30 *C 63.020 97.210 +*N mux_tree_tapbuf_size7_0_sram[0]:31 *C 63.020 97.285 +*N mux_tree_tapbuf_size7_0_sram[0]:32 *C 63.020 97.863 +*N mux_tree_tapbuf_size7_0_sram[0]:33 *C 63.028 97.920 +*N mux_tree_tapbuf_size7_0_sram[0]:34 *C 68.532 97.920 +*N mux_tree_tapbuf_size7_0_sram[0]:35 *C 68.540 97.978 +*N mux_tree_tapbuf_size7_0_sram[0]:36 *C 68.540 99.235 +*N mux_tree_tapbuf_size7_0_sram[0]:37 *C 68.540 99.280 +*N mux_tree_tapbuf_size7_0_sram[0]:38 *C 68.845 99.280 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_16\/mux_l1_in_3_:S 1e-06 +3 mux_top_track_16\/mux_l1_in_2_:S 1e-06 +4 mux_top_track_16\/mux_l1_in_0_:S 1e-06 +5 mux_top_track_16\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_0_sram[0]:6 3.892923e-05 +7 mux_tree_tapbuf_size7_0_sram[0]:7 9.738075e-05 +8 mux_tree_tapbuf_size7_0_sram[0]:8 3.000395e-05 +9 mux_tree_tapbuf_size7_0_sram[0]:9 0.0004617813 +10 mux_tree_tapbuf_size7_0_sram[0]:10 1.742266e-05 +11 mux_tree_tapbuf_size7_0_sram[0]:11 2.753874e-05 +12 mux_tree_tapbuf_size7_0_sram[0]:12 0.0005126881 +13 mux_tree_tapbuf_size7_0_sram[0]:13 6.596329e-05 +14 mux_tree_tapbuf_size7_0_sram[0]:14 6.976693e-05 +15 mux_tree_tapbuf_size7_0_sram[0]:15 0.000548234 +16 mux_tree_tapbuf_size7_0_sram[0]:16 0.0005003554 +17 mux_tree_tapbuf_size7_0_sram[0]:17 0.0004648095 +18 mux_tree_tapbuf_size7_0_sram[0]:18 0.0004031162 +19 mux_tree_tapbuf_size7_0_sram[0]:19 0.0004031162 +20 mux_tree_tapbuf_size7_0_sram[0]:20 0.0005016431 +21 mux_tree_tapbuf_size7_0_sram[0]:21 0.0005016431 +22 mux_tree_tapbuf_size7_0_sram[0]:22 5.045921e-05 +23 mux_tree_tapbuf_size7_0_sram[0]:23 6.659776e-05 +24 mux_tree_tapbuf_size7_0_sram[0]:24 5.113826e-05 +25 mux_tree_tapbuf_size7_0_sram[0]:25 0.000542059 +26 mux_tree_tapbuf_size7_0_sram[0]:26 0.0005718062 +27 mux_tree_tapbuf_size7_0_sram[0]:27 5.703849e-05 +28 mux_tree_tapbuf_size7_0_sram[0]:28 0.0005064953 +29 mux_tree_tapbuf_size7_0_sram[0]:29 0.0006359706 +30 mux_tree_tapbuf_size7_0_sram[0]:30 0.0006944221 +31 mux_tree_tapbuf_size7_0_sram[0]:31 6.174731e-05 +32 mux_tree_tapbuf_size7_0_sram[0]:32 6.174731e-05 +33 mux_tree_tapbuf_size7_0_sram[0]:33 0.000386082 +34 mux_tree_tapbuf_size7_0_sram[0]:34 0.000386082 +35 mux_tree_tapbuf_size7_0_sram[0]:35 0.0001100781 +36 mux_tree_tapbuf_size7_0_sram[0]:36 0.0001100781 +37 mux_tree_tapbuf_size7_0_sram[0]:37 6.23681e-05 +38 mux_tree_tapbuf_size7_0_sram[0]:38 5.656936e-05 +39 mux_tree_tapbuf_size7_0_sram[0]:19 chanx_left_in[15]:11 0.000331542 +40 mux_tree_tapbuf_size7_0_sram[0]:18 chanx_left_in[15] 0.000331542 +41 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.0001466412 +42 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0001466412 +43 mux_tree_tapbuf_size7_0_sram[0]:28 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001266868 +44 mux_tree_tapbuf_size7_0_sram[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001266868 +45 mux_tree_tapbuf_size7_0_sram[0]:29 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002971615 +46 mux_tree_tapbuf_size7_0_sram[0]:30 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002971615 +47 mux_tree_tapbuf_size7_0_sram[0]:21 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.62758e-06 +48 mux_tree_tapbuf_size7_0_sram[0]:20 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.62758e-06 +49 mux_tree_tapbuf_size7_0_sram[0]:17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001082623 +50 mux_tree_tapbuf_size7_0_sram[0]:15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 6.546439e-05 +51 mux_tree_tapbuf_size7_0_sram[0]:12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 6.546439e-05 +52 mux_tree_tapbuf_size7_0_sram[0]:16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001082623 +53 mux_tree_tapbuf_size7_0_sram[0]:19 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0006017066 +54 mux_tree_tapbuf_size7_0_sram[0]:19 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 7.160102e-07 +55 mux_tree_tapbuf_size7_0_sram[0]:18 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0006017066 +56 mux_tree_tapbuf_size7_0_sram[0]:18 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 7.160102e-07 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_0_sram[0]:38 0.152 +1 mux_tree_tapbuf_size7_0_sram[0]:22 mux_tree_tapbuf_size7_0_sram[0]:21 0.0045 +2 mux_tree_tapbuf_size7_0_sram[0]:21 mux_tree_tapbuf_size7_0_sram[0]:20 0.008104911 +3 mux_tree_tapbuf_size7_0_sram[0]:20 mux_tree_tapbuf_size7_0_sram[0]:19 0.00341 +4 mux_tree_tapbuf_size7_0_sram[0]:19 mux_tree_tapbuf_size7_0_sram[0]:18 0.00172725 +5 mux_tree_tapbuf_size7_0_sram[0]:17 mux_tree_tapbuf_size7_0_sram[0]:16 0.008752231 +6 mux_tree_tapbuf_size7_0_sram[0]:18 mux_tree_tapbuf_size7_0_sram[0]:17 0.00341 +7 mux_tree_tapbuf_size7_0_sram[0]:29 mux_tree_tapbuf_size7_0_sram[0]:28 0.0045 +8 mux_tree_tapbuf_size7_0_sram[0]:28 mux_tree_tapbuf_size7_0_sram[0]:27 0.000290625 +9 mux_tree_tapbuf_size7_0_sram[0]:28 mux_tree_tapbuf_size7_0_sram[0]:10 1.875e-05 +10 mux_tree_tapbuf_size7_0_sram[0]:28 mux_tree_tapbuf_size7_0_sram[0]:9 0.008348215 +11 mux_tree_tapbuf_size7_0_sram[0]:8 mux_top_track_16\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size7_0_sram[0]:9 mux_tree_tapbuf_size7_0_sram[0]:8 0.0045 +13 mux_tree_tapbuf_size7_0_sram[0]:23 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size7_0_sram[0]:23 mux_tree_tapbuf_size7_0_sram[0]:22 9.51087e-05 +15 mux_tree_tapbuf_size7_0_sram[0]:13 mux_top_track_16\/mux_l1_in_3_:S 0.152 +16 mux_tree_tapbuf_size7_0_sram[0]:14 mux_tree_tapbuf_size7_0_sram[0]:13 0.0001847826 +17 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:14 0.0045 +18 mux_tree_tapbuf_size7_0_sram[0]:15 mux_tree_tapbuf_size7_0_sram[0]:12 0.009370536 +19 mux_tree_tapbuf_size7_0_sram[0]:30 mux_tree_tapbuf_size7_0_sram[0]:29 0.01063839 +20 mux_tree_tapbuf_size7_0_sram[0]:30 mux_tree_tapbuf_size7_0_sram[0]:7 0.0008839287 +21 mux_tree_tapbuf_size7_0_sram[0]:31 mux_tree_tapbuf_size7_0_sram[0]:30 0.0045 +22 mux_tree_tapbuf_size7_0_sram[0]:32 mux_tree_tapbuf_size7_0_sram[0]:31 0.000515625 +23 mux_tree_tapbuf_size7_0_sram[0]:33 mux_tree_tapbuf_size7_0_sram[0]:32 0.00341 +24 mux_tree_tapbuf_size7_0_sram[0]:35 mux_tree_tapbuf_size7_0_sram[0]:34 0.00341 +25 mux_tree_tapbuf_size7_0_sram[0]:34 mux_tree_tapbuf_size7_0_sram[0]:33 0.0008624499 +26 mux_tree_tapbuf_size7_0_sram[0]:37 mux_tree_tapbuf_size7_0_sram[0]:36 0.0045 +27 mux_tree_tapbuf_size7_0_sram[0]:36 mux_tree_tapbuf_size7_0_sram[0]:35 0.001122768 +28 mux_tree_tapbuf_size7_0_sram[0]:38 mux_tree_tapbuf_size7_0_sram[0]:37 0.0001657609 +29 mux_tree_tapbuf_size7_0_sram[0]:11 mux_top_track_16\/mux_l1_in_2_:S 0.152 +30 mux_tree_tapbuf_size7_0_sram[0]:12 mux_tree_tapbuf_size7_0_sram[0]:11 0.0045 +31 mux_tree_tapbuf_size7_0_sram[0]:6 mux_top_track_16\/mux_l1_in_1_:S 0.152 +32 mux_tree_tapbuf_size7_0_sram[0]:24 mux_tree_tapbuf_size7_0_sram[0]:23 0.0001548913 +33 mux_tree_tapbuf_size7_0_sram[0]:25 mux_tree_tapbuf_size7_0_sram[0]:24 0.0045 +34 mux_tree_tapbuf_size7_0_sram[0]:7 mux_tree_tapbuf_size7_0_sram[0]:6 0.0002879464 +35 mux_tree_tapbuf_size7_0_sram[0]:16 mux_tree_tapbuf_size7_0_sram[0]:15 0.0004107143 +36 mux_tree_tapbuf_size7_0_sram[0]:26 mux_tree_tapbuf_size7_0_sram[0]:25 0.009674108 +37 mux_tree_tapbuf_size7_0_sram[0]:27 mux_tree_tapbuf_size7_0_sram[0]:26 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[3] 0.001589598 //LENGTH 13.400 LUMPCC 0.0001754776 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 40.785 98.940 +*I mem_top_track_2\/FTB_3__35:A I *L 0.001746 *C 36.800 102.000 +*I mux_top_track_2\/mux_l4_in_0_:S I *L 0.00357 *C 37.620 106.760 +*N mux_tree_tapbuf_size8_0_sram[3]:3 *C 37.605 106.760 +*N mux_tree_tapbuf_size8_0_sram[3]:4 *C 37.282 106.760 +*N mux_tree_tapbuf_size8_0_sram[3]:5 *C 37.260 106.715 +*N mux_tree_tapbuf_size8_0_sram[3]:6 *C 36.837 102.000 +*N mux_tree_tapbuf_size8_0_sram[3]:7 *C 37.215 102.000 +*N mux_tree_tapbuf_size8_0_sram[3]:8 *C 37.260 102.000 +*N mux_tree_tapbuf_size8_0_sram[3]:9 *C 37.260 98.985 +*N mux_tree_tapbuf_size8_0_sram[3]:10 *C 37.305 98.940 +*N mux_tree_tapbuf_size8_0_sram[3]:11 *C 40.748 98.940 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_2\/FTB_3__35:A 1e-06 +2 mux_top_track_2\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_0_sram[3]:3 5.795423e-05 +4 mux_tree_tapbuf_size8_0_sram[3]:4 5.795423e-05 +5 mux_tree_tapbuf_size8_0_sram[3]:5 0.0002212198 +6 mux_tree_tapbuf_size8_0_sram[3]:6 4.689802e-05 +7 mux_tree_tapbuf_size8_0_sram[3]:7 4.689802e-05 +8 mux_tree_tapbuf_size8_0_sram[3]:8 0.0003838218 +9 mux_tree_tapbuf_size8_0_sram[3]:9 0.0001324937 +10 mux_tree_tapbuf_size8_0_sram[3]:10 0.0002319405 +11 mux_tree_tapbuf_size8_0_sram[3]:11 0.0002319405 +12 mux_tree_tapbuf_size8_0_sram[3]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.132283e-05 +13 mux_tree_tapbuf_size8_0_sram[3]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.641596e-05 +14 mux_tree_tapbuf_size8_0_sram[3]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.132283e-05 +15 mux_tree_tapbuf_size8_0_sram[3]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.641596e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_0_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_0_sram[3]:3 mux_top_track_2\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_0_sram[3]:4 mux_tree_tapbuf_size8_0_sram[3]:3 0.0001752718 +3 mux_tree_tapbuf_size8_0_sram[3]:5 mux_tree_tapbuf_size8_0_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size8_0_sram[3]:7 mux_tree_tapbuf_size8_0_sram[3]:6 0.0003370536 +5 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size8_0_sram[3]:8 mux_tree_tapbuf_size8_0_sram[3]:5 0.004209822 +7 mux_tree_tapbuf_size8_0_sram[3]:6 mem_top_track_2\/FTB_3__35:A 0.152 +8 mux_tree_tapbuf_size8_0_sram[3]:10 mux_tree_tapbuf_size8_0_sram[3]:9 0.0045 +9 mux_tree_tapbuf_size8_0_sram[3]:9 mux_tree_tapbuf_size8_0_sram[3]:8 0.002691964 +10 mux_tree_tapbuf_size8_0_sram[3]:11 mux_tree_tapbuf_size8_0_sram[3]:10 0.003073661 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001031379 //LENGTH 8.235 LUMPCC 0.0001301733 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_0_:X O *L 0 *C 39.735 118.660 +*I mux_top_track_0\/mux_l3_in_0_:A1 I *L 0.00198 *C 40.940 123.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 40.903 123.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 40.480 123.420 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 40.480 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 40.065 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 40.020 124.055 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 40.020 118.705 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 40.020 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 39.735 118.660 + +*CAP +0 mux_top_track_0\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.755201e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.485577e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001032494 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.594564e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000245851 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000245851 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 5.593749e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 4.996377e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.508664e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.508664e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003705357 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.004776786 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0001548913 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0006071429 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0003772322 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0007128114 //LENGTH 5.410 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_1_:X O *L 0 *C 49.855 17.340 +*I mux_bottom_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 48.590 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 48.590 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 48.760 20.740 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 48.760 20.695 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 48.760 17.385 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 48.805 17.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 49.818 17.340 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.04367e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.275339e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002144461 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002144461 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.936454e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 7.936454e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.239131e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002955357 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040178 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001540142 //LENGTH 11.440 LUMPCC 0.0004376206 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_1_:X O *L 0 *C 36.625 97.240 +*I mux_top_track_2\/mux_l4_in_0_:A0 I *L 0.001631 *C 36.515 107.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 36.515 107.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 36.340 107.780 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 36.340 107.735 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 36.340 97.285 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 36.340 97.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 36.625 97.240 + +*CAP +0 mux_top_track_2\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.75031e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.174981e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0004337869 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004337869 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.620519e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.748961e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_0_sram[3]:5 5.132283e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size8_0_sram[3]:8 3.641596e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_0_sram[3]:8 5.132283e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size8_0_sram[3]:9 3.641596e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.47432e-07 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.47432e-07 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001301241 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001301241 + +*RES +0 mux_top_track_2\/mux_l3_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_2\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.51087e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.009330357 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0] 0.0008819795 //LENGTH 6.695 LUMPCC 0.0001624276 DR + +*CONN +*I mux_top_track_4\/mux_l4_in_0_:X O *L 0 *C 71.125 118.660 +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 77.605 118.510 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 77.605 118.510 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 71.163 118.660 + +*CAP +0 mux_top_track_4\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0003776356 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0003399164 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 8.12138e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.12138e-05 + +*RES +0 mux_top_track_4\/mux_l4_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.005752233 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0] 0.001294682 //LENGTH 10.130 LUMPCC 0.0002177362 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_1_:X O *L 0 *C 40.765 14.960 +*I mux_bottom_track_5\/mux_l4_in_0_:A0 I *L 0.001631 *C 46.635 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 46.598 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 40.525 11.900 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 40.480 11.945 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 40.480 14.915 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 40.480 14.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 40.765 14.960 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0002957892 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0002957892 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0001878768 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0001878768 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 5.477979e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 5.283357e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:10 6.173515e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:16 2.313668e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_tree_tapbuf_size14_1_sram[2]:18 2.05012e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:9 6.173515e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:15 2.313668e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_tree_tapbuf_size14_1_sram[2]:17 2.05012e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:8 2.357586e-06 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:16 1.137478e-06 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:7 2.357586e-06 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:17 1.137478e-06 + +*RES +0 mux_bottom_track_5\/mux_l3_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_bottom_track_5\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.005421875 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.002651786 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002898556 //LENGTH 22.240 LUMPCC 0.0001759884 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_0_:X O *L 0 *C 61.355 44.200 +*I mux_bottom_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 44.260 39.780 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 44.160 39.780 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 44.160 39.825 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 44.160 44.155 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 44.205 44.200 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 61.318 44.200 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.228691e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002437256 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002437256 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001100415 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001100415 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:14 7.807424e-07 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size7_2_sram[0]:18 5.156546e-06 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:20 5.740503e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:28 2.46519e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:15 7.807424e-07 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:19 5.156546e-06 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:21 5.740503e-05 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:29 2.46519e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003866072 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.01527902 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0006722808 //LENGTH 5.655 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l3_in_0_:X O *L 0 *C 7.995 83.640 +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.235 85.835 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 5.272 85.735 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 5.935 85.680 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 5.980 85.635 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 5.980 83.685 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 6.025 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 7.958 83.640 + +*CAP +0 mux_left_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.868725e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.868725e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001295795 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001295795 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001468736 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001468736 + +*RES +0 mux_left_track_3\/mux_l3_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0005915179 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001741072 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0] 0.006228223 //LENGTH 42.000 LUMPCC 0.002303489 DR + +*CONN +*I mux_left_track_7\/mux_l3_in_0_:X O *L 0 *C 42.035 61.200 +*I mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 11.785 71.880 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 11.822 71.788 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 12.375 71.740 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 12.420 71.695 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 12.420 61.258 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 12.428 61.200 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 40.473 61.200 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 40.480 61.200 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 40.525 61.200 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 41.998 61.200 + +*CAP +0 mux_left_track_7\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.524013e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.524013e-05 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0006387387 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0006387387 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001113668 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.001113668 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 3.747646e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.000134982 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.000134982 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chany_bottom_in[14]:8 0.0001604575 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chany_bottom_in[14]:29 0.0001604575 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 left_top_grid_pin_45_[0]:15 0.0002903338 +14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 left_top_grid_pin_45_[0]:16 0.0001119846 +15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 left_top_grid_pin_45_[0]:10 0.0001119846 +16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 left_top_grid_pin_45_[0]:16 0.0002903338 +17 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size7_6_sram[0]:22 5.527713e-05 +18 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_tree_tapbuf_size7_6_sram[0]:23 0.0001330457 +19 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size7_6_sram[0]:18 5.527713e-05 +20 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_tree_tapbuf_size7_6_sram[0]:22 0.0001330457 +21 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 optlc_net_139:38 0.0004006457 +22 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 optlc_net_139:39 0.0004006457 + +*RES +0 mux_left_track_7\/mux_l3_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004933036 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.009319197 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.004393716 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0045 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.001314732 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.01222185 //LENGTH 81.995 LUMPCC 0.004083476 DR + +*CONN +*I mux_left_track_9\/mux_l3_in_0_:X O *L 0 *C 79.295 64.600 +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.340 71.890 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 5.340 71.890 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 5.520 71.740 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 5.520 71.695 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 5.520 64.657 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 5.527 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 55.355 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 79.112 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 79.120 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 79.120 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 79.295 64.600 + +*CAP +0 mux_left_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.627142e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.308891e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002913589 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002913589 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.002156714 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.003653751 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.001497038 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 3.24151e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 5.161748e-05 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 5.276344e-05 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:370 0.0001394491 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 prog_clk[0]:383 5.867623e-05 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:383 0.0001394491 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 prog_clk[0]:400 5.867623e-05 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:221 2.344555e-05 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:381 2.873828e-05 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 prog_clk[0]:382 3.694908e-05 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 prog_clk[0]:96 3.316312e-06 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 prog_clk[0]:108 8.233555e-06 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 prog_clk[0]:220 3.779014e-06 +22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:97 3.316312e-06 +23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:109 8.233555e-06 +24 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:220 2.344555e-05 +25 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:221 3.779014e-06 +26 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:378 2.873828e-05 +27 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 prog_clk[0]:381 3.694908e-05 +28 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_6_sram[0]:22 0.0002159423 +29 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_6_sram[0]:23 0.0002183084 +30 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_6_sram[0]:18 0.0002159423 +31 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_6_sram[0]:22 0.0002183084 +32 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_6_sram[2]:12 0.0001207646 +33 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size7_6_sram[2]:13 9.154326e-05 +34 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_6_sram[2]:12 9.154326e-05 +35 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_6_sram[2]:13 0.0001207646 +36 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.991677e-05 +37 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.991677e-05 +38 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0003382577 +39 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0003382577 +40 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0006744177 +41 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0006744177 + +*RES +0 mux_left_track_9\/mux_l3_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.782609e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.006283482 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.00341 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.003722008 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0045 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:10 9.51087e-05 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.007806308 + +*END + +*D_NET chany_bottom_out[11] 0.0003995291 //LENGTH 2.525 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_807:X O *L 0 *C 74.300 3.400 +*P chany_bottom_out[11] O *L 0.7423 *C 74.060 1.325 +*N chany_bottom_out[11]:2 *C 74.060 3.355 +*N chany_bottom_out[11]:3 *C 74.060 3.400 +*N chany_bottom_out[11]:4 *C 74.300 3.400 + +*CAP +0 ropt_mt_inst_807:X 1e-06 +1 chany_bottom_out[11] 0.0001438224 +2 chany_bottom_out[11]:2 0.0001438224 +3 chany_bottom_out[11]:3 5.687615e-05 +4 chany_bottom_out[11]:4 5.400803e-05 + +*RES +0 ropt_mt_inst_807:X chany_bottom_out[11]:4 0.152 +1 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +2 chany_bottom_out[11]:2 chany_bottom_out[11] 0.0018125 +3 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.0001304348 + +*END + +*D_NET ropt_net_207 0.0008817512 //LENGTH 6.260 LUMPCC 0.0003458571 DR + +*CONN +*I ropt_mt_inst_775:X O *L 0 *C 105.340 126.820 +*I ropt_mt_inst_845:A I *L 0.001766 *C 99.820 126.480 +*N ropt_net_207:2 *C 99.820 126.480 +*N ropt_net_207:3 *C 99.820 126.820 +*N ropt_net_207:4 *C 105.303 126.820 + +*CAP +0 ropt_mt_inst_775:X 1e-06 +1 ropt_mt_inst_845:A 1e-06 +2 ropt_net_207:2 5.016359e-05 +3 ropt_net_207:3 0.0002529032 +4 ropt_net_207:4 0.0002308273 +5 ropt_net_207:4 chany_bottom_in[13]:4 0.0001642324 +6 ropt_net_207:4 chany_bottom_in[13]:6 3.609394e-06 +7 ropt_net_207:2 chany_bottom_in[13]:6 5.086743e-06 +8 ropt_net_207:3 chany_bottom_in[13]:5 0.0001693191 +9 ropt_net_207:3 chany_bottom_in[13]:7 3.609394e-06 + +*RES +0 ropt_mt_inst_775:X ropt_net_207:4 0.152 +1 ropt_net_207:4 ropt_net_207:3 0.00489509 +2 ropt_net_207:2 ropt_mt_inst_845:A 0.152 +3 ropt_net_207:3 ropt_net_207:2 0.0003035715 + +*END + +*D_NET ropt_net_191 0.001042365 //LENGTH 8.845 LUMPCC 0.000145049 DR + +*CONN +*I ropt_mt_inst_786:X O *L 0 *C 7.095 36.040 +*I ropt_mt_inst_823:A I *L 0.001767 *C 3.220 34.000 +*N ropt_net_191:2 *C 3.258 34.000 +*N ropt_net_191:3 *C 4.555 34.000 +*N ropt_net_191:4 *C 4.600 33.955 +*N ropt_net_191:5 *C 4.600 33.365 +*N ropt_net_191:6 *C 4.645 33.320 +*N ropt_net_191:7 *C 5.935 33.320 +*N ropt_net_191:8 *C 5.980 33.365 +*N ropt_net_191:9 *C 5.980 35.995 +*N ropt_net_191:10 *C 6.025 36.040 +*N ropt_net_191:11 *C 7.058 36.040 + +*CAP +0 ropt_mt_inst_786:X 1e-06 +1 ropt_mt_inst_823:A 1e-06 +2 ropt_net_191:2 9.205235e-05 +3 ropt_net_191:3 9.205235e-05 +4 ropt_net_191:4 3.687281e-05 +5 ropt_net_191:5 3.687281e-05 +6 ropt_net_191:6 9.631337e-05 +7 ropt_net_191:7 9.631337e-05 +8 ropt_net_191:8 0.0001368035 +9 ropt_net_191:9 0.0001368035 +10 ropt_net_191:10 8.561603e-05 +11 ropt_net_191:11 8.561603e-05 +12 ropt_net_191:9 prog_clk[0]:525 2.476976e-05 +13 ropt_net_191:9 prog_clk[0]:526 9.134069e-06 +14 ropt_net_191:7 prog_clk[0]:267 1.26941e-05 +15 ropt_net_191:8 prog_clk[0]:526 2.476976e-05 +16 ropt_net_191:8 prog_clk[0]:527 9.134069e-06 +17 ropt_net_191:6 prog_clk[0]:268 1.26941e-05 +18 ropt_net_191:5 prog_clk[0]:526 4.148252e-06 +19 ropt_net_191:5 prog_clk[0]:527 2.177832e-05 +20 ropt_net_191:4 prog_clk[0]:525 4.148252e-06 +21 ropt_net_191:4 prog_clk[0]:526 2.177832e-05 + +*RES +0 ropt_mt_inst_786:X ropt_net_191:11 0.152 +1 ropt_net_191:11 ropt_net_191:10 0.0009218751 +2 ropt_net_191:10 ropt_net_191:9 0.0045 +3 ropt_net_191:9 ropt_net_191:8 0.002348214 +4 ropt_net_191:7 ropt_net_191:6 0.001151786 +5 ropt_net_191:8 ropt_net_191:7 0.0045 +6 ropt_net_191:6 ropt_net_191:5 0.0045 +7 ropt_net_191:5 ropt_net_191:4 0.0005267857 +8 ropt_net_191:3 ropt_net_191:2 0.001158482 +9 ropt_net_191:4 ropt_net_191:3 0.0045 +10 ropt_net_191:2 ropt_mt_inst_823:A 0.152 + +*END + +*D_NET chany_top_out[19] 0.0002986943 //LENGTH 2.270 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_819:X O *L 0 *C 78.660 127.160 +*P chany_top_out[19] O *L 0.7423 *C 78.660 129.270 +*N chany_top_out[19]:2 *C 78.660 127.205 +*N chany_top_out[19]:3 *C 78.660 127.160 + +*CAP +0 ropt_mt_inst_819:X 1e-06 +1 chany_top_out[19] 0.0001313614 +2 chany_top_out[19]:2 0.0001313614 +3 chany_top_out[19]:3 3.497148e-05 + +*RES +0 ropt_mt_inst_819:X chany_top_out[19]:3 0.152 +1 chany_top_out[19]:3 chany_top_out[19]:2 0.0045 +2 chany_top_out[19]:2 chany_top_out[19] 0.00184375 + +*END + +*D_NET chany_bottom_out[9] 0.0007360444 //LENGTH 5.755 LUMPCC 0.0001364586 DR + +*CONN +*I ropt_mt_inst_831:X O *L 0 *C 54.740 6.120 +*P chany_bottom_out[9] O *L 0.7423 *C 54.280 1.290 +*N chany_bottom_out[9]:2 *C 54.280 6.075 +*N chany_bottom_out[9]:3 *C 54.325 6.120 +*N chany_bottom_out[9]:4 *C 54.703 6.120 + +*CAP +0 ropt_mt_inst_831:X 1e-06 +1 chany_bottom_out[9] 0.0002491834 +2 chany_bottom_out[9]:2 0.0002491834 +3 chany_bottom_out[9]:3 5.010955e-05 +4 chany_bottom_out[9]:4 5.010955e-05 +5 chany_bottom_out[9] ropt_net_198:4 6.822928e-05 +6 chany_bottom_out[9]:2 ropt_net_198:3 6.822928e-05 + +*RES +0 ropt_mt_inst_831:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.0003370536 +2 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +3 chany_bottom_out[9]:2 chany_bottom_out[9] 0.004272321 + +*END + +*D_NET chanx_left_out[18] 0.001019613 //LENGTH 9.520 LUMPCC 0 DR + +*CONN +*I BUFT_P_119:X O *L 0 *C 3.025 77.520 +*P chanx_left_out[18] O *L 0.7423 *C 1.298 70.720 +*N chanx_left_out[18]:2 *C 1.380 70.720 +*N chanx_left_out[18]:3 *C 1.380 70.720 +*N chanx_left_out[18]:4 *C 2.300 70.720 +*N chanx_left_out[18]:5 *C 2.300 77.475 +*N chanx_left_out[18]:6 *C 2.345 77.520 +*N chanx_left_out[18]:7 *C 2.988 77.520 + +*CAP +0 BUFT_P_119:X 1e-06 +1 chanx_left_out[18] 2.948893e-05 +2 chanx_left_out[18]:2 2.948893e-05 +3 chanx_left_out[18]:3 8.772092e-05 +4 chanx_left_out[18]:4 0.0004106955 +5 chanx_left_out[18]:5 0.0003563779 +6 chanx_left_out[18]:6 5.242036e-05 +7 chanx_left_out[18]:7 5.242036e-05 + +*RES +0 BUFT_P_119:X chanx_left_out[18]:7 0.152 +1 chanx_left_out[18]:7 chanx_left_out[18]:6 0.0005736608 +2 chanx_left_out[18]:6 chanx_left_out[18]:5 0.0045 +3 chanx_left_out[18]:5 chanx_left_out[18]:4 0.00603125 +4 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +5 chanx_left_out[18]:2 chanx_left_out[18] 2.35e-05 +6 chanx_left_out[18]:4 chanx_left_out[18]:3 0.0008214285 + +*END + +*D_NET chany_top_in[2] 0.02310483 //LENGTH 182.440 LUMPCC 0.006130512 DR + +*CONN +*P chany_top_in[2] I *L 0.29796 *C 82.340 129.235 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 35.250 91.800 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 57.405 23.460 +*I FTB_2__1:A I *L 0.001767 *C 70.380 12.240 +*N chany_top_in[2]:4 *C 70.418 12.240 +*N chany_top_in[2]:5 *C 71.255 12.240 +*N chany_top_in[2]:6 *C 71.300 12.285 +*N chany_top_in[2]:7 *C 71.300 21.023 +*N chany_top_in[2]:8 *C 71.293 21.080 +*N chany_top_in[2]:9 *C 60.728 21.080 +*N chany_top_in[2]:10 *C 60.720 21.137 +*N chany_top_in[2]:11 *C 57.405 23.460 +*N chany_top_in[2]:12 *C 57.500 23.800 +*N chany_top_in[2]:13 *C 60.675 23.800 +*N chany_top_in[2]:14 *C 60.720 23.800 +*N chany_top_in[2]:15 *C 60.720 73.800 +*N chany_top_in[2]:16 *C 35.288 91.800 +*N chany_top_in[2]:17 *C 60.675 91.800 +*N chany_top_in[2]:18 *C 60.720 91.800 +*N chany_top_in[2]:19 *C 60.720 93.782 +*N chany_top_in[2]:20 *C 60.728 93.840 +*N chany_top_in[2]:21 *C 81.860 93.840 +*N chany_top_in[2]:22 *C 81.880 93.848 +*N chany_top_in[2]:23 *C 81.880 126.473 +*N chany_top_in[2]:24 *C 81.895 126.480 +*N chany_top_in[2]:25 *C 82.338 126.480 +*N chany_top_in[2]:26 *C 82.340 126.538 + +*CAP +0 chany_top_in[2] 0.0001948504 +1 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +3 FTB_2__1:A 1e-06 +4 chany_top_in[2]:4 7.490524e-05 +5 chany_top_in[2]:5 7.490524e-05 +6 chany_top_in[2]:6 0.0005025627 +7 chany_top_in[2]:7 0.0005025627 +8 chany_top_in[2]:8 0.0005328574 +9 chany_top_in[2]:9 0.0005328574 +10 chany_top_in[2]:10 0.0001610132 +11 chany_top_in[2]:11 5.541461e-05 +12 chany_top_in[2]:12 0.000256817 +13 chany_top_in[2]:13 0.0002296863 +14 chany_top_in[2]:14 0.002275096 +15 chany_top_in[2]:15 0.002703564 +16 chany_top_in[2]:16 0.001423819 +17 chany_top_in[2]:17 0.001423819 +18 chany_top_in[2]:18 0.0007147316 +19 chany_top_in[2]:19 6.585118e-05 +20 chany_top_in[2]:20 0.001295692 +21 chany_top_in[2]:21 0.001295692 +22 chany_top_in[2]:22 0.001180197 +23 chany_top_in[2]:23 0.001180197 +24 chany_top_in[2]:24 4.968923e-05 +25 chany_top_in[2]:25 4.968923e-05 +26 chany_top_in[2]:26 0.0001948504 +27 chany_top_in[2]:9 chany_top_in[13]:25 0.00057283 +28 chany_top_in[2]:8 chany_top_in[13]:24 0.00057283 +29 chany_top_in[2] chany_top_in[17] 3.309684e-06 +30 chany_top_in[2]:18 chany_top_in[17]:25 3.106402e-06 +31 chany_top_in[2]:18 chany_top_in[17]:24 6.128436e-07 +32 chany_top_in[2]:7 chany_top_in[17]:10 2.137094e-05 +33 chany_top_in[2]:6 chany_top_in[17]:9 2.137094e-05 +34 chany_top_in[2]:14 chany_top_in[17]:21 2.04611e-06 +35 chany_top_in[2]:22 chany_top_in[17]:28 0.000473999 +36 chany_top_in[2]:23 chany_top_in[17]:29 0.000473999 +37 chany_top_in[2]:26 chany_top_in[17]:32 3.309684e-06 +38 chany_top_in[2]:15 chany_top_in[17]:21 6.128436e-07 +39 chany_top_in[2]:15 chany_top_in[17]:24 5.152512e-06 +40 chany_top_in[2]:18 left_top_grid_pin_43_[0]:24 0.0001193668 +41 chany_top_in[2]:14 left_top_grid_pin_43_[0]:16 5.693351e-05 +42 chany_top_in[2]:14 left_top_grid_pin_43_[0]:19 2.183991e-05 +43 chany_top_in[2]:14 left_top_grid_pin_43_[0]:23 0.0003189801 +44 chany_top_in[2]:15 left_top_grid_pin_43_[0]:19 5.693351e-05 +45 chany_top_in[2]:15 left_top_grid_pin_43_[0]:20 2.183991e-05 +46 chany_top_in[2]:15 left_top_grid_pin_43_[0]:23 0.0001193668 +47 chany_top_in[2]:15 left_top_grid_pin_43_[0]:24 0.0003189801 +48 chany_top_in[2]:18 prog_clk[0]:444 4.070079e-05 +49 chany_top_in[2]:18 prog_clk[0]:447 7.521411e-06 +50 chany_top_in[2]:14 prog_clk[0]:156 0.0002360768 +51 chany_top_in[2]:14 prog_clk[0]:157 1.003986e-05 +52 chany_top_in[2]:14 prog_clk[0]:152 0.0001419998 +53 chany_top_in[2]:14 prog_clk[0]:155 5.769197e-05 +54 chany_top_in[2]:19 prog_clk[0]:416 1.5632e-05 +55 chany_top_in[2]:20 prog_clk[0]:443 8.414789e-05 +56 chany_top_in[2]:20 prog_clk[0]:421 3.847123e-05 +57 chany_top_in[2]:21 prog_clk[0]:442 8.414789e-05 +58 chany_top_in[2]:21 prog_clk[0]:420 3.847123e-05 +59 chany_top_in[2]:15 prog_clk[0]:156 5.769197e-05 +60 chany_top_in[2]:15 prog_clk[0]:148 0.0001419998 +61 chany_top_in[2]:15 prog_clk[0]:448 7.521411e-06 +62 chany_top_in[2]:15 prog_clk[0]:152 0.0002360768 +63 chany_top_in[2]:15 prog_clk[0]:447 2.506879e-05 +64 chany_top_in[2]:15 prog_clk[0]:158 1.003986e-05 +65 chany_top_in[2]:17 mux_tree_tapbuf_size6_0_sram[0]:9 0.0003018499 +66 chany_top_in[2]:18 mux_tree_tapbuf_size6_0_sram[0]:23 3.761986e-06 +67 chany_top_in[2]:18 mux_tree_tapbuf_size6_0_sram[0]:21 0.0001303256 +68 chany_top_in[2]:16 mux_tree_tapbuf_size6_0_sram[0]:8 0.0003018499 +69 chany_top_in[2]:15 mux_tree_tapbuf_size6_0_sram[0]:20 0.0001303256 +70 chany_top_in[2]:15 mux_tree_tapbuf_size6_0_sram[0]:22 3.761986e-06 +71 chany_top_in[2]:18 optlc_net_138:24 5.865822e-05 +72 chany_top_in[2]:18 optlc_net_138:23 0.0002442549 +73 chany_top_in[2]:19 optlc_net_138:23 5.865822e-05 +74 chany_top_in[2]:15 optlc_net_138:24 0.0002442549 +75 chany_top_in[2]:17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.824962e-05 +76 chany_top_in[2]:17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.71108e-05 +77 chany_top_in[2]:16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.71108e-05 +78 chany_top_in[2]:16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.824962e-05 + +*RES +0 chany_top_in[2] chany_top_in[2]:26 0.002408482 +1 chany_top_in[2]:17 chany_top_in[2]:16 0.02266741 +2 chany_top_in[2]:18 chany_top_in[2]:17 0.0045 +3 chany_top_in[2]:18 chany_top_in[2]:15 0.01607143 +4 chany_top_in[2]:16 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +5 chany_top_in[2]:10 chany_top_in[2]:9 0.00341 +6 chany_top_in[2]:9 chany_top_in[2]:8 0.001655183 +7 chany_top_in[2]:7 chany_top_in[2]:6 0.00780134 +8 chany_top_in[2]:8 chany_top_in[2]:7 0.00341 +9 chany_top_in[2]:5 chany_top_in[2]:4 0.0007477679 +10 chany_top_in[2]:6 chany_top_in[2]:5 0.0045 +11 chany_top_in[2]:4 FTB_2__1:A 0.152 +12 chany_top_in[2]:13 chany_top_in[2]:12 0.002834821 +13 chany_top_in[2]:14 chany_top_in[2]:13 0.0045 +14 chany_top_in[2]:14 chany_top_in[2]:10 0.002377232 +15 chany_top_in[2]:11 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[2]:19 chany_top_in[2]:18 0.001770089 +17 chany_top_in[2]:20 chany_top_in[2]:19 0.00341 +18 chany_top_in[2]:21 chany_top_in[2]:20 0.003310758 +19 chany_top_in[2]:22 chany_top_in[2]:21 0.00341 +20 chany_top_in[2]:24 chany_top_in[2]:23 0.00341 +21 chany_top_in[2]:23 chany_top_in[2]:22 0.00511125 +22 chany_top_in[2]:26 chany_top_in[2]:25 0.00341 +23 chany_top_in[2]:25 chany_top_in[2]:24 6.499219e-05 +24 chany_top_in[2]:12 chany_top_in[2]:11 0.0003035715 +25 chany_top_in[2]:15 chany_top_in[2]:14 0.04464286 + +*END + +*D_NET chany_top_in[19] 0.01380399 //LENGTH 115.295 LUMPCC 0.003251011 DR + +*CONN +*P chany_top_in[19] I *L 0.29796 *C 59.340 129.270 +*I BUFT_RR_74:A I *L 0.001776 *C 6.900 69.360 +*N chany_top_in[19]:2 *C 6.938 69.360 +*N chany_top_in[19]:3 *C 7.775 69.360 +*N chany_top_in[19]:4 *C 7.820 69.405 +*N chany_top_in[19]:5 *C 7.820 91.075 +*N chany_top_in[19]:6 *C 7.865 91.120 +*N chany_top_in[19]:7 *C 10.075 91.120 +*N chany_top_in[19]:8 *C 10.120 91.165 +*N chany_top_in[19]:9 *C 10.120 101.615 +*N chany_top_in[19]:10 *C 10.165 101.660 +*N chany_top_in[19]:11 *C 17.480 101.660 +*N chany_top_in[19]:12 *C 17.480 102.000 +*N chany_top_in[19]:13 *C 29.395 102.000 +*N chany_top_in[19]:14 *C 29.440 102.045 +*N chany_top_in[19]:15 *C 29.440 119.680 +*N chany_top_in[19]:16 *C 29.900 119.680 +*N chany_top_in[19]:17 *C 29.900 128.475 +*N chany_top_in[19]:18 *C 29.945 128.520 +*N chany_top_in[19]:19 *C 59.295 128.520 +*N chany_top_in[19]:20 *C 59.340 128.565 + +*CAP +0 chany_top_in[19] 6.258245e-05 +1 BUFT_RR_74:A 1e-06 +2 chany_top_in[19]:2 7.206529e-05 +3 chany_top_in[19]:3 7.206529e-05 +4 chany_top_in[19]:4 0.001002386 +5 chany_top_in[19]:5 0.001002386 +6 chany_top_in[19]:6 0.0001990634 +7 chany_top_in[19]:7 0.0001990634 +8 chany_top_in[19]:8 0.0004098676 +9 chany_top_in[19]:9 0.0004098676 +10 chany_top_in[19]:10 0.0003312681 +11 chany_top_in[19]:11 0.0003531454 +12 chany_top_in[19]:12 0.0004898392 +13 chany_top_in[19]:13 0.0004679619 +14 chany_top_in[19]:14 0.0005792786 +15 chany_top_in[19]:15 0.0006057112 +16 chany_top_in[19]:16 0.0004725558 +17 chany_top_in[19]:17 0.000446123 +18 chany_top_in[19]:18 0.001657082 +19 chany_top_in[19]:19 0.001657082 +20 chany_top_in[19]:20 6.258245e-05 +21 chany_top_in[19]:10 chany_top_in[7]:11 8.487869e-05 +22 chany_top_in[19]:13 chany_top_in[7]:12 0.0002254394 +23 chany_top_in[19]:11 chany_top_in[7]:12 8.487869e-05 +24 chany_top_in[19]:12 chany_top_in[7]:11 0.0002254394 +25 chany_top_in[19]:18 chany_bottom_in[6]:19 0.0003618342 +26 chany_top_in[19]:19 chany_bottom_in[6]:20 0.0003618342 +27 chany_top_in[19]:14 top_left_grid_pin_41_[0]:18 0.0002399138 +28 chany_top_in[19]:14 top_left_grid_pin_41_[0]:12 0.0002085208 +29 chany_top_in[19]:15 top_left_grid_pin_41_[0]:18 0.0002085208 +30 chany_top_in[19]:15 top_left_grid_pin_41_[0]:19 0.0002399138 +31 chany_top_in[19]:4 left_top_grid_pin_49_[0]:27 3.382095e-08 +32 chany_top_in[19]:5 left_top_grid_pin_49_[0] 3.382095e-08 +33 chany_top_in[19]:8 left_top_grid_pin_49_[0]:27 0.0002809416 +34 chany_top_in[19]:9 left_top_grid_pin_49_[0] 0.0002809416 +35 chany_top_in[19]:4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 7.017353e-05 +36 chany_top_in[19]:5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 7.017353e-05 +37 chany_top_in[19]:4 BUF_net_69:3 0.0001534626 +38 chany_top_in[19]:5 BUF_net_69:4 0.0001534626 +39 chany_top_in[19]:8 BUF_net_69:3 3.072912e-07 +40 chany_top_in[19]:9 BUF_net_69:4 3.072912e-07 + +*RES +0 chany_top_in[19] chany_top_in[19]:20 0.0006294643 +1 chany_top_in[19]:2 BUFT_RR_74:A 0.152 +2 chany_top_in[19]:3 chany_top_in[19]:2 0.0007477679 +3 chany_top_in[19]:4 chany_top_in[19]:3 0.0045 +4 chany_top_in[19]:6 chany_top_in[19]:5 0.0045 +5 chany_top_in[19]:5 chany_top_in[19]:4 0.01934822 +6 chany_top_in[19]:7 chany_top_in[19]:6 0.001973214 +7 chany_top_in[19]:8 chany_top_in[19]:7 0.0045 +8 chany_top_in[19]:10 chany_top_in[19]:9 0.0045 +9 chany_top_in[19]:9 chany_top_in[19]:8 0.009330357 +10 chany_top_in[19]:13 chany_top_in[19]:12 0.01063839 +11 chany_top_in[19]:14 chany_top_in[19]:13 0.0045 +12 chany_top_in[19]:18 chany_top_in[19]:17 0.0045 +13 chany_top_in[19]:17 chany_top_in[19]:16 0.007852679 +14 chany_top_in[19]:19 chany_top_in[19]:18 0.02620536 +15 chany_top_in[19]:20 chany_top_in[19]:19 0.0045 +16 chany_top_in[19]:11 chany_top_in[19]:10 0.006531251 +17 chany_top_in[19]:12 chany_top_in[19]:11 0.0003035715 +18 chany_top_in[19]:15 chany_top_in[19]:14 0.01574554 +19 chany_top_in[19]:16 chany_top_in[19]:15 0.0004107143 + +*END + +*D_NET chany_bottom_in[4] 0.02649706 //LENGTH 211.860 LUMPCC 0.005913947 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 65.320 1.325 +*I mux_top_track_2\/mux_l2_in_1_:A0 I *L 0.001631 *C 28.695 98.600 +*I mux_left_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 31.185 85.340 +*I ropt_mt_inst_771:A I *L 0.001767 *C 90.620 126.480 +*N chany_bottom_in[4]:4 *C 90.583 126.480 +*N chany_bottom_in[4]:5 *C 87.400 126.480 +*N chany_bottom_in[4]:6 *C 87.400 126.140 +*N chany_bottom_in[4]:7 *C 83.765 126.140 +*N chany_bottom_in[4]:8 *C 83.720 126.095 +*N chany_bottom_in[4]:9 *C 83.720 112.925 +*N chany_bottom_in[4]:10 *C 83.720 112.880 +*N chany_bottom_in[4]:11 *C 80.085 112.880 +*N chany_bottom_in[4]:12 *C 80.040 112.835 +*N chany_bottom_in[4]:13 *C 80.040 102.680 +*N chany_bottom_in[4]:14 *C 80.500 102.680 +*N chany_bottom_in[4]:15 *C 80.500 102.045 +*N chany_bottom_in[4]:16 *C 80.455 102.000 +*N chany_bottom_in[4]:17 *C 77.325 102.000 +*N chany_bottom_in[4]:18 *C 77.280 101.955 +*N chany_bottom_in[4]:19 *C 77.280 101.378 +*N chany_bottom_in[4]:20 *C 77.273 101.320 +*N chany_bottom_in[4]:21 *C 31.185 85.340 +*N chany_bottom_in[4]:22 *C 31.280 85.000 +*N chany_bottom_in[4]:23 *C 29.025 85.000 +*N chany_bottom_in[4]:24 *C 28.980 85.045 +*N chany_bottom_in[4]:25 *C 28.695 98.600 +*N chany_bottom_in[4]:26 *C 28.980 98.600 +*N chany_bottom_in[4]:27 *C 28.980 98.600 +*N chany_bottom_in[4]:28 *C 28.980 101.263 +*N chany_bottom_in[4]:29 *C 28.988 101.320 +*N chany_bottom_in[4]:30 *C 65.780 101.320 +*N chany_bottom_in[4]:31 *C 65.780 101.263 +*N chany_bottom_in[4]:32 *C 65.780 51.290 +*N chany_bottom_in[4]:33 *C 65.780 1.360 + +*CAP +0 chany_bottom_in[4] 3.370855e-05 +1 mux_top_track_2\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_3\/mux_l1_in_1_:A1 1e-06 +3 ropt_mt_inst_771:A 1e-06 +4 chany_bottom_in[4]:4 0.0001933369 +5 chany_bottom_in[4]:5 0.0002173075 +6 chany_bottom_in[4]:6 0.0002629539 +7 chany_bottom_in[4]:7 0.0002389832 +8 chany_bottom_in[4]:8 0.0007337513 +9 chany_bottom_in[4]:9 0.0007337513 +10 chany_bottom_in[4]:10 0.0002179757 +11 chany_bottom_in[4]:11 0.0001888854 +12 chany_bottom_in[4]:12 0.0003482561 +13 chany_bottom_in[4]:13 0.0003610988 +14 chany_bottom_in[4]:14 6.534504e-05 +15 chany_bottom_in[4]:15 5.250238e-05 +16 chany_bottom_in[4]:16 0.0002102631 +17 chany_bottom_in[4]:17 0.0002102631 +18 chany_bottom_in[4]:18 5.078456e-05 +19 chany_bottom_in[4]:19 5.078456e-05 +20 chany_bottom_in[4]:20 0.0008155283 +21 chany_bottom_in[4]:21 6.053556e-05 +22 chany_bottom_in[4]:22 0.0002368904 +23 chany_bottom_in[4]:23 0.0002079594 +24 chany_bottom_in[4]:24 0.0008368666 +25 chany_bottom_in[4]:25 5.757658e-05 +26 chany_bottom_in[4]:26 6.296394e-05 +27 chany_bottom_in[4]:27 0.001052565 +28 chany_bottom_in[4]:28 0.0001828802 +29 chany_bottom_in[4]:29 0.002463113 +30 chany_bottom_in[4]:30 0.003278641 +31 chany_bottom_in[4]:31 0.001588837 +32 chany_bottom_in[4]:32 0.003560467 +33 chany_bottom_in[4]:33 0.002005338 +34 chany_bottom_in[4]:31 chany_top_in[16]:10 0.0001796182 +35 chany_bottom_in[4]:31 chany_top_in[16]:15 8.602332e-05 +36 chany_bottom_in[4]:31 chany_top_in[16]:17 0.0001429812 +37 chany_bottom_in[4]:33 chany_top_in[16]:6 3.426684e-05 +38 chany_bottom_in[4]:33 chany_top_in[16]:9 0.0004498252 +39 chany_bottom_in[4]:32 chany_top_in[16]:9 0.000213885 +40 chany_bottom_in[4]:32 chany_top_in[16]:10 0.0005358485 +41 chany_bottom_in[4]:32 chany_top_in[16]:16 0.0001429812 +42 chany_bottom_in[4]:31 chany_bottom_in[8]:11 2.228994e-06 +43 chany_bottom_in[4]:31 chany_bottom_in[8]:8 2.726243e-05 +44 chany_bottom_in[4]:31 chany_bottom_in[8]:13 0.000388288 +45 chany_bottom_in[4]:32 chany_bottom_in[8]:14 0.000388288 +46 chany_bottom_in[4]:32 chany_bottom_in[8]:11 2.726243e-05 +47 chany_bottom_in[4]:32 chany_bottom_in[8]:12 2.228994e-06 +48 chany_bottom_in[4]:31 prog_clk[0]:442 1.207481e-05 +49 chany_bottom_in[4]:31 prog_clk[0]:132 0.00016032 +50 chany_bottom_in[4]:31 prog_clk[0]:136 8.639479e-05 +51 chany_bottom_in[4]:31 prog_clk[0]:416 5.774637e-07 +52 chany_bottom_in[4]:30 prog_clk[0]:329 7.242509e-05 +53 chany_bottom_in[4]:30 prog_clk[0]:333 8.336514e-06 +54 chany_bottom_in[4]:29 prog_clk[0]:334 8.336514e-06 +55 chany_bottom_in[4]:29 prog_clk[0]:333 7.242509e-05 +56 chany_bottom_in[4]:27 prog_clk[0]:341 2.095128e-06 +57 chany_bottom_in[4]:27 prog_clk[0]:343 1.303668e-05 +58 chany_bottom_in[4]:27 prog_clk[0]:335 8.427843e-08 +59 chany_bottom_in[4]:24 prog_clk[0]:341 8.427843e-08 +60 chany_bottom_in[4]:24 prog_clk[0]:342 2.095128e-06 +61 chany_bottom_in[4]:24 prog_clk[0]:283 1.303668e-05 +62 chany_bottom_in[4]:33 prog_clk[0]:145 8.402618e-06 +63 chany_bottom_in[4]:32 prog_clk[0]:444 5.774637e-07 +64 chany_bottom_in[4]:32 prog_clk[0]:137 8.639479e-05 +65 chany_bottom_in[4]:32 prog_clk[0]:144 8.402618e-06 +66 chany_bottom_in[4]:32 prog_clk[0]:136 0.00016032 +67 chany_bottom_in[4]:32 prog_clk[0]:421 1.207481e-05 +68 chany_bottom_in[4]:20 chany_top_in[0]:7 3.979508e-06 +69 chany_bottom_in[4]:17 chany_top_in[0]:10 3.005164e-05 +70 chany_bottom_in[4]:16 chany_top_in[0]:9 3.005164e-05 +71 chany_bottom_in[4]:15 chany_top_in[0]:10 2.584135e-06 +72 chany_bottom_in[4]:11 chany_top_in[0]:19 2.151225e-05 +73 chany_bottom_in[4]:11 chany_top_in[0]:15 3.000747e-05 +74 chany_bottom_in[4]:12 chany_top_in[0]:11 0.0001184715 +75 chany_bottom_in[4]:12 chany_top_in[0]:17 1.578872e-05 +76 chany_bottom_in[4]:12 chany_top_in[0]:15 9.606979e-05 +77 chany_bottom_in[4]:10 chany_top_in[0]:18 2.151225e-05 +78 chany_bottom_in[4]:10 chany_top_in[0]:16 3.000747e-05 +79 chany_bottom_in[4]:9 chany_top_in[0]:20 8.955266e-07 +80 chany_bottom_in[4]:9 chany_top_in[0]:22 4.540659e-06 +81 chany_bottom_in[4]:9 chany_top_in[0]:24 5.724748e-07 +82 chany_bottom_in[4]:9 chany_top_in[0]:16 3.442368e-06 +83 chany_bottom_in[4]:8 chany_top_in[0]:17 3.442368e-06 +84 chany_bottom_in[4]:8 chany_top_in[0]:21 8.955266e-07 +85 chany_bottom_in[4]:8 chany_top_in[0]:23 4.540659e-06 +86 chany_bottom_in[4]:8 chany_top_in[0]:25 5.724748e-07 +87 chany_bottom_in[4]:30 chany_top_in[0]:6 3.979508e-06 +88 chany_bottom_in[4]:30 chany_top_in[0]:7 3.068651e-05 +89 chany_bottom_in[4]:29 chany_top_in[0]:6 3.068651e-05 +90 chany_bottom_in[4]:13 chany_top_in[0]:14 9.606979e-05 +91 chany_bottom_in[4]:13 chany_top_in[0]:10 0.0001202948 +92 chany_bottom_in[4]:13 chany_top_in[0]:16 1.578872e-05 +93 chany_bottom_in[4]:14 chany_top_in[0]:11 2.584135e-06 +94 chany_bottom_in[4]:14 chany_top_in[0]:9 1.823338e-06 +95 chany_bottom_in[4]:31 mux_tree_tapbuf_size7_0_sram[2]:7 0.0002197233 +96 chany_bottom_in[4]:32 mux_tree_tapbuf_size7_0_sram[2]:8 0.0002197233 +97 chany_bottom_in[4]:33 mux_tree_tapbuf_size8_2_sram[1]:22 3.914303e-05 +98 chany_bottom_in[4]:33 mux_tree_tapbuf_size8_2_sram[1]:21 0.0004691671 +99 chany_bottom_in[4]:32 mux_tree_tapbuf_size8_2_sram[1]:18 0.0004691671 +100 chany_bottom_in[4]:32 mux_tree_tapbuf_size8_2_sram[1]:21 3.914303e-05 +101 chany_bottom_in[4]:12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.229955e-05 +102 chany_bottom_in[4]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.261115e-05 +103 chany_bottom_in[4]:13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.229955e-05 +104 chany_bottom_in[4]:14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.261115e-05 +105 chany_bottom_in[4]:9 ropt_net_205:3 4.375061e-07 +106 chany_bottom_in[4]:7 ropt_net_205:5 6.827535e-05 +107 chany_bottom_in[4]:8 ropt_net_205:4 4.375061e-07 +108 chany_bottom_in[4]:4 ropt_net_205:6 4.064918e-05 +109 chany_bottom_in[4]:6 ropt_net_205:6 6.827535e-05 +110 chany_bottom_in[4]:5 ropt_net_205:5 4.064918e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:33 0.0004107143 +1 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.000515625 +2 chany_bottom_in[4]:20 chany_bottom_in[4]:19 0.00341 +3 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.002794643 +4 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.0045 +5 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.0045 +6 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.0005669643 +7 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.003245536 +8 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.0045 +9 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.0045 +10 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.01175893 +11 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.003245536 +12 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.0045 +13 chany_bottom_in[4]:4 ropt_mt_inst_771:A 0.152 +14 chany_bottom_in[4]:31 chany_bottom_in[4]:30 0.00341 +15 chany_bottom_in[4]:30 chany_bottom_in[4]:29 0.005764158 +16 chany_bottom_in[4]:30 chany_bottom_in[4]:20 0.001800492 +17 chany_bottom_in[4]:28 chany_bottom_in[4]:27 0.002377232 +18 chany_bottom_in[4]:29 chany_bottom_in[4]:28 0.00341 +19 chany_bottom_in[4]:26 chany_bottom_in[4]:25 0.0001548913 +20 chany_bottom_in[4]:27 chany_bottom_in[4]:26 0.0045 +21 chany_bottom_in[4]:27 chany_bottom_in[4]:24 0.01210268 +22 chany_bottom_in[4]:25 mux_top_track_2\/mux_l2_in_1_:A0 0.152 +23 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.002013393 +24 chany_bottom_in[4]:24 chany_bottom_in[4]:23 0.0045 +25 chany_bottom_in[4]:21 mux_left_track_3\/mux_l1_in_1_:A1 0.152 +26 chany_bottom_in[4]:22 chany_bottom_in[4]:21 0.0003035714 +27 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.0003035715 +28 chany_bottom_in[4]:5 chany_bottom_in[4]:4 0.002841518 +29 chany_bottom_in[4]:33 chany_bottom_in[4]:32 0.04458036 +30 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.009066964 +31 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.0004107143 +32 chany_bottom_in[4]:32 chany_bottom_in[4]:31 0.04461831 + +*END + +*D_NET chany_bottom_in[5] 0.02295215 //LENGTH 169.795 LUMPCC 0.007790294 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 75.900 1.290 +*I mux_top_track_4\/mux_l1_in_4_:A0 I *L 0.001631 *C 64.230 102.680 +*I BUFT_P_123:A I *L 0.001767 *C 73.395 121.040 +*I mux_left_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 42.685 69.020 +*N chany_bottom_in[5]:4 *C 42.685 69.020 +*N chany_bottom_in[5]:5 *C 42.780 69.360 +*N chany_bottom_in[5]:6 *C 51.935 69.360 +*N chany_bottom_in[5]:7 *C 51.980 69.360 +*N chany_bottom_in[5]:8 *C 51.988 69.360 +*N chany_bottom_in[5]:9 *C 73.358 121.040 +*N chany_bottom_in[5]:10 *C 71.805 121.040 +*N chany_bottom_in[5]:11 *C 71.760 120.995 +*N chany_bottom_in[5]:12 *C 71.760 102.738 +*N chany_bottom_in[5]:13 *C 71.752 102.680 +*N chany_bottom_in[5]:14 *C 64.267 102.680 +*N chany_bottom_in[5]:15 *C 64.815 102.680 +*N chany_bottom_in[5]:16 *C 64.860 102.680 +*N chany_bottom_in[5]:17 *C 64.860 102.680 +*N chany_bottom_in[5]:18 *C 60.740 102.680 +*N chany_bottom_in[5]:19 *C 60.720 102.672 +*N chany_bottom_in[5]:20 *C 60.720 69.368 +*N chany_bottom_in[5]:21 *C 60.720 69.360 +*N chany_bottom_in[5]:22 *C 63.460 69.360 +*N chany_bottom_in[5]:23 *C 63.480 69.353 +*N chany_bottom_in[5]:24 *C 63.480 58.675 +*N chany_bottom_in[5]:25 *C 63.480 8.848 +*N chany_bottom_in[5]:26 *C 63.500 8.840 +*N chany_bottom_in[5]:27 *C 75.892 8.840 +*N chany_bottom_in[5]:28 *C 75.900 8.783 + +*CAP +0 chany_bottom_in[5] 0.0004646089 +1 mux_top_track_4\/mux_l1_in_4_:A0 1e-06 +2 BUFT_P_123:A 1e-06 +3 mux_left_track_5\/mux_l1_in_1_:A1 1e-06 +4 chany_bottom_in[5]:4 5.612915e-05 +5 chany_bottom_in[5]:5 0.0005842341 +6 chany_bottom_in[5]:6 0.0005565655 +7 chany_bottom_in[5]:7 3.728911e-05 +8 chany_bottom_in[5]:8 0.000644478 +9 chany_bottom_in[5]:9 9.341414e-05 +10 chany_bottom_in[5]:10 9.341414e-05 +11 chany_bottom_in[5]:11 0.0008127195 +12 chany_bottom_in[5]:12 0.0008127195 +13 chany_bottom_in[5]:13 0.0005174699 +14 chany_bottom_in[5]:14 5.892547e-05 +15 chany_bottom_in[5]:15 5.892547e-05 +16 chany_bottom_in[5]:16 3.450533e-05 +17 chany_bottom_in[5]:17 0.0008474544 +18 chany_bottom_in[5]:18 0.0003299845 +19 chany_bottom_in[5]:19 0.0007822359 +20 chany_bottom_in[5]:20 0.0007822359 +21 chany_bottom_in[5]:21 0.0008598309 +22 chany_bottom_in[5]:22 0.0002153529 +23 chany_bottom_in[5]:23 0.0001835774 +24 chany_bottom_in[5]:24 0.002008479 +25 chany_bottom_in[5]:25 0.001824901 +26 chany_bottom_in[5]:26 0.001017401 +27 chany_bottom_in[5]:27 0.001017401 +28 chany_bottom_in[5]:28 0.0004646089 +29 chany_bottom_in[5]:23 chany_top_in[10]:25 0.0002285179 +30 chany_bottom_in[5]:25 chany_top_in[10]:24 0.0002050405 +31 chany_bottom_in[5]:24 chany_top_in[10]:24 0.0002285179 +32 chany_bottom_in[5]:24 chany_top_in[10]:25 0.0002050405 +33 chany_bottom_in[5]:20 chany_top_in[12]:20 0.000696492 +34 chany_bottom_in[5]:19 chany_top_in[12]:21 0.000696492 +35 chany_bottom_in[5]:20 chany_top_in[13]:30 0.0003681625 +36 chany_bottom_in[5]:20 chany_top_in[13]:31 0.0003283294 +37 chany_bottom_in[5]:19 chany_top_in[13]:31 0.0003681625 +38 chany_bottom_in[5]:19 chany_top_in[13]:32 0.0003283294 +39 chany_bottom_in[5]:23 chany_top_in[13]:31 0.0004814982 +40 chany_bottom_in[5]:25 chany_top_in[13]:30 0.0009581621 +41 chany_bottom_in[5]:24 chany_top_in[13]:30 0.0004814982 +42 chany_bottom_in[5]:24 chany_top_in[13]:31 0.0009581621 +43 chany_bottom_in[5]:25 chany_bottom_in[14]:33 0.0003679861 +44 chany_bottom_in[5]:24 chany_bottom_in[14]:32 0.0003679861 +45 chany_bottom_in[5]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001909075 +46 chany_bottom_in[5]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001909075 +47 chany_bottom_in[5]:10 ropt_net_168:3 7.005065e-05 +48 chany_bottom_in[5]:9 ropt_net_168:4 7.005065e-05 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:28 0.006689733 +1 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.01630134 +2 chany_bottom_in[5]:13 chany_bottom_in[5]:12 0.00341 +3 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.001386161 +4 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.0045 +5 chany_bottom_in[5]:9 BUFT_P_123:A 0.152 +6 chany_bottom_in[5]:21 chany_bottom_in[5]:20 0.00341 +7 chany_bottom_in[5]:21 chany_bottom_in[5]:8 0.001368092 +8 chany_bottom_in[5]:20 chany_bottom_in[5]:19 0.005217783 +9 chany_bottom_in[5]:18 chany_bottom_in[5]:17 0.0006454666 +10 chany_bottom_in[5]:19 chany_bottom_in[5]:18 0.00341 +11 chany_bottom_in[5]:16 chany_bottom_in[5]:15 0.0045 +12 chany_bottom_in[5]:17 chany_bottom_in[5]:16 0.00341 +13 chany_bottom_in[5]:17 chany_bottom_in[5]:13 0.001079825 +14 chany_bottom_in[5]:15 chany_bottom_in[5]:14 0.0004888393 +15 chany_bottom_in[5]:14 mux_top_track_4\/mux_l1_in_4_:A0 0.152 +16 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.0045 +17 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.00341 +18 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.008174107 +19 chany_bottom_in[5]:4 mux_left_track_5\/mux_l1_in_1_:A1 0.152 +20 chany_bottom_in[5]:22 chany_bottom_in[5]:21 0.0004292667 +21 chany_bottom_in[5]:23 chany_bottom_in[5]:22 0.00341 +22 chany_bottom_in[5]:26 chany_bottom_in[5]:25 0.00341 +23 chany_bottom_in[5]:25 chany_bottom_in[5]:24 0.007806308 +24 chany_bottom_in[5]:28 chany_bottom_in[5]:27 0.00341 +25 chany_bottom_in[5]:27 chany_bottom_in[5]:26 0.001941492 +26 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.0003035715 +27 chany_bottom_in[5]:24 chany_bottom_in[5]:23 0.001672808 + +*END + +*D_NET chany_bottom_in[8] 0.01737396 //LENGTH 144.315 LUMPCC 0.004941823 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 77.740 1.325 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 74.695 64.260 +*I mux_top_track_16\/mux_l1_in_1_:A1 I *L 0.00198 *C 63.940 96.220 +*I FTB_24__23:A I *L 0.001776 *C 60.260 123.760 +*N chany_bottom_in[8]:4 *C 60.297 123.760 +*N chany_bottom_in[8]:5 *C 60.720 123.760 +*N chany_bottom_in[8]:6 *C 60.720 123.420 +*N chany_bottom_in[8]:7 *C 64.355 123.420 +*N chany_bottom_in[8]:8 *C 64.400 123.375 +*N chany_bottom_in[8]:9 *C 63.978 96.220 +*N chany_bottom_in[8]:10 *C 64.355 96.220 +*N chany_bottom_in[8]:11 *C 64.400 96.235 +*N chany_bottom_in[8]:12 *C 64.445 95.880 +*N chany_bottom_in[8]:13 *C 64.860 95.880 +*N chany_bottom_in[8]:14 *C 64.860 64.645 +*N chany_bottom_in[8]:15 *C 64.905 64.600 +*N chany_bottom_in[8]:16 *C 74.520 64.600 +*N chany_bottom_in[8]:17 *C 74.695 64.260 +*N chany_bottom_in[8]:18 *C 74.520 64.260 +*N chany_bottom_in[8]:19 *C 74.520 64.215 +*N chany_bottom_in[8]:20 *C 74.520 61.938 +*N chany_bottom_in[8]:21 *C 74.528 61.880 +*N chany_bottom_in[8]:22 *C 75.420 61.880 +*N chany_bottom_in[8]:23 *C 75.440 61.873 +*N chany_bottom_in[8]:24 *C 75.440 54.595 +*N chany_bottom_in[8]:25 *C 75.440 4.768 +*N chany_bottom_in[8]:26 *C 75.460 4.760 +*N chany_bottom_in[8]:27 *C 77.733 4.760 +*N chany_bottom_in[8]:28 *C 77.740 4.703 + +*CAP +0 chany_bottom_in[8] 0.0001637352 +1 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A1 1e-06 +3 FTB_24__23:A 1e-06 +4 chany_bottom_in[8]:4 6.406454e-05 +5 chany_bottom_in[8]:5 9.004588e-05 +6 chany_bottom_in[8]:6 0.0002152701 +7 chany_bottom_in[8]:7 0.0001892888 +8 chany_bottom_in[8]:8 0.001182201 +9 chany_bottom_in[8]:9 5.006475e-05 +10 chany_bottom_in[8]:10 5.006475e-05 +11 chany_bottom_in[8]:11 0.001212762 +12 chany_bottom_in[8]:12 3.434339e-05 +13 chany_bottom_in[8]:13 0.0009497859 +14 chany_bottom_in[8]:14 0.0009460041 +15 chany_bottom_in[8]:15 0.0006427692 +16 chany_bottom_in[8]:16 0.0006640157 +17 chany_bottom_in[8]:17 5.586957e-05 +18 chany_bottom_in[8]:18 7.989774e-05 +19 chany_bottom_in[8]:19 0.0001665758 +20 chany_bottom_in[8]:20 0.0001665758 +21 chany_bottom_in[8]:21 8.915112e-05 +22 chany_bottom_in[8]:22 8.915112e-05 +23 chany_bottom_in[8]:23 0.0002928324 +24 chany_bottom_in[8]:24 0.002477675 +25 chany_bottom_in[8]:25 0.002184842 +26 chany_bottom_in[8]:26 0.0001042072 +27 chany_bottom_in[8]:27 0.0001042072 +28 chany_bottom_in[8]:28 0.0001637352 +29 chany_bottom_in[8]:14 chany_top_in[17]:21 0.0003567 +30 chany_bottom_in[8]:14 chany_top_in[17]:24 0.0002316654 +31 chany_bottom_in[8]:13 chany_top_in[17]:24 0.0003567 +32 chany_bottom_in[8]:13 chany_top_in[17]:25 0.0002316654 +33 chany_bottom_in[8]:14 chany_bottom_in[4]:32 0.000388288 +34 chany_bottom_in[8]:11 chany_bottom_in[4]:31 2.228994e-06 +35 chany_bottom_in[8]:11 chany_bottom_in[4]:32 2.726243e-05 +36 chany_bottom_in[8]:8 chany_bottom_in[4]:31 2.726243e-05 +37 chany_bottom_in[8]:12 chany_bottom_in[4]:32 2.228994e-06 +38 chany_bottom_in[8]:13 chany_bottom_in[4]:31 0.000388288 +39 chany_bottom_in[8] chany_bottom_in[16] 4.422068e-05 +40 chany_bottom_in[8]:23 chany_bottom_in[16]:24 0.0001675423 +41 chany_bottom_in[8]:25 chany_bottom_in[16]:25 0.0004856529 +42 chany_bottom_in[8]:28 chany_bottom_in[16]:29 4.422068e-05 +43 chany_bottom_in[8]:24 chany_bottom_in[16]:25 0.0001675423 +44 chany_bottom_in[8]:24 chany_bottom_in[16]:24 0.0004856529 +45 chany_bottom_in[8]:11 top_right_grid_pin_1_[0]:9 6.663206e-05 +46 chany_bottom_in[8]:11 top_right_grid_pin_1_[0]:10 0.0003807323 +47 chany_bottom_in[8]:8 top_right_grid_pin_1_[0]:7 0.0003807323 +48 chany_bottom_in[8]:8 top_right_grid_pin_1_[0]:10 6.663206e-05 +49 chany_bottom_in[8]:14 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 3.279055e-05 +50 chany_bottom_in[8]:12 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 2.852974e-05 +51 chany_bottom_in[8]:13 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 3.279055e-05 +52 chany_bottom_in[8]:13 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 2.852974e-05 +53 chany_bottom_in[8]:26 ropt_net_180:8 0.000148008 +54 chany_bottom_in[8]:27 ropt_net_180:9 0.000148008 +55 chany_bottom_in[8]:11 ropt_net_183:5 1.740731e-08 +56 chany_bottom_in[8]:7 ropt_net_183:7 0.0001106412 +57 chany_bottom_in[8]:8 ropt_net_183:4 1.740731e-08 +58 chany_bottom_in[8]:6 ropt_net_183:6 0.0001106412 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:28 0.003015625 +1 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.0045 +2 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.02788839 +3 chany_bottom_in[8]:18 chany_bottom_in[8]:17 9.51087e-05 +4 chany_bottom_in[8]:18 chany_bottom_in[8]:16 0.0003035715 +5 chany_bottom_in[8]:19 chany_bottom_in[8]:18 0.0045 +6 chany_bottom_in[8]:20 chany_bottom_in[8]:19 0.002033482 +7 chany_bottom_in[8]:21 chany_bottom_in[8]:20 0.00341 +8 chany_bottom_in[8]:22 chany_bottom_in[8]:21 0.000139825 +9 chany_bottom_in[8]:23 chany_bottom_in[8]:22 0.00341 +10 chany_bottom_in[8]:26 chany_bottom_in[8]:25 0.00341 +11 chany_bottom_in[8]:25 chany_bottom_in[8]:24 0.007806308 +12 chany_bottom_in[8]:28 chany_bottom_in[8]:27 0.00341 +13 chany_bottom_in[8]:27 chany_bottom_in[8]:26 0.000356025 +14 chany_bottom_in[8]:17 mux_left_track_9\/mux_l2_in_0_:A0 0.152 +15 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.0003370536 +16 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.0045 +17 chany_bottom_in[8]:11 chany_bottom_in[8]:8 0.02423215 +18 chany_bottom_in[8]:9 mux_top_track_16\/mux_l1_in_1_:A1 0.152 +19 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.003245536 +20 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.0045 +21 chany_bottom_in[8]:4 FTB_24__23:A 0.152 +22 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.0003772322 +23 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.0003035715 +24 chany_bottom_in[8]:16 chany_bottom_in[8]:15 0.008584822 +25 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.000221875 +26 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.0003705357 +27 chany_bottom_in[8]:24 chany_bottom_in[8]:23 0.001140142 + +*END + +*D_NET chany_bottom_in[10] 0.01926008 //LENGTH 159.837 LUMPCC 0.002311123 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 62.560 1.325 +*I mux_left_track_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.490 44.540 +*I mux_top_track_32\/mux_l1_in_1_:A1 I *L 0.00198 *C 61.740 74.460 +*I BUFT_P_126:A I *L 0.001776 *C 86.940 121.040 +*N chany_bottom_in[10]:4 *C 86.903 121.040 +*N chany_bottom_in[10]:5 *C 84.685 121.040 +*N chany_bottom_in[10]:6 *C 84.640 120.995 +*N chany_bottom_in[10]:7 *C 84.640 74.165 +*N chany_bottom_in[10]:8 *C 84.595 74.120 +*N chany_bottom_in[10]:9 *C 61.640 74.120 +*N chany_bottom_in[10]:10 *C 61.653 74.438 +*N chany_bottom_in[10]:11 *C 61.640 74.460 +*N chany_bottom_in[10]:12 *C 57.085 74.460 +*N chany_bottom_in[10]:13 *C 57.040 74.415 +*N chany_bottom_in[10]:14 *C 55.528 44.540 +*N chany_bottom_in[10]:15 *C 56.995 44.540 +*N chany_bottom_in[10]:16 *C 57.040 44.540 +*N chany_bottom_in[10]:17 *C 57.040 12.978 +*N chany_bottom_in[10]:18 *C 57.047 12.920 +*N chany_bottom_in[10]:19 *C 62.553 12.920 +*N chany_bottom_in[10]:20 *C 62.560 12.863 + +*CAP +0 chany_bottom_in[10] 0.000677269 +1 mux_left_track_13\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_1_:A1 1e-06 +3 BUFT_P_126:A 1e-06 +4 chany_bottom_in[10]:4 0.0001493332 +5 chany_bottom_in[10]:5 0.0001493332 +6 chany_bottom_in[10]:6 0.002328573 +7 chany_bottom_in[10]:7 0.002328573 +8 chany_bottom_in[10]:8 0.001521345 +9 chany_bottom_in[10]:9 0.001542011 +10 chany_bottom_in[10]:10 3.884872e-05 +11 chany_bottom_in[10]:11 0.0003459195 +12 chany_bottom_in[10]:12 0.0003277368 +13 chany_bottom_in[10]:13 0.001037388 +14 chany_bottom_in[10]:14 0.00014457 +15 chany_bottom_in[10]:15 0.00014457 +16 chany_bottom_in[10]:16 0.002772109 +17 chany_bottom_in[10]:17 0.001703358 +18 chany_bottom_in[10]:18 0.0005288777 +19 chany_bottom_in[10]:19 0.0005288777 +20 chany_bottom_in[10]:20 0.000677269 +21 chany_bottom_in[10]:13 chany_bottom_in[12]:13 0.0005480053 +22 chany_bottom_in[10]:16 chany_bottom_in[12]:16 0.0005480053 +23 chany_bottom_in[10]:12 chanx_left_in[1]:4 5.699133e-06 +24 chany_bottom_in[10]:13 chanx_left_in[1]:5 0.0003148484 +25 chany_bottom_in[10]:17 chanx_left_in[1]:6 0.0001258586 +26 chany_bottom_in[10]:16 chanx_left_in[1]:6 0.0003148484 +27 chany_bottom_in[10]:16 chanx_left_in[1]:5 0.0001258586 +28 chany_bottom_in[10]:11 chanx_left_in[1]:3 5.699133e-06 +29 chany_bottom_in[10]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001117912 +30 chany_bottom_in[10]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001117912 +31 chany_bottom_in[10] ropt_net_185:3 4.935883e-05 +32 chany_bottom_in[10]:20 ropt_net_185:4 4.935883e-05 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:20 0.01030134 +1 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.004066965 +2 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.0045 +3 chany_bottom_in[10]:17 chany_bottom_in[10]:16 0.02818081 +4 chany_bottom_in[10]:18 chany_bottom_in[10]:17 0.00341 +5 chany_bottom_in[10]:20 chany_bottom_in[10]:19 0.00341 +6 chany_bottom_in[10]:19 chany_bottom_in[10]:18 0.00086245 +7 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.001310268 +8 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.0045 +9 chany_bottom_in[10]:16 chany_bottom_in[10]:13 0.02667411 +10 chany_bottom_in[10]:14 mux_left_track_13\/mux_l1_in_0_:A0 0.152 +11 chany_bottom_in[10]:10 mux_top_track_32\/mux_l1_in_1_:A1 0.152 +12 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.0002834821 +13 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.0045 +14 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.04181251 +15 chany_bottom_in[10]:5 chany_bottom_in[10]:4 0.001979911 +16 chany_bottom_in[10]:6 chany_bottom_in[10]:5 0.0045 +17 chany_bottom_in[10]:4 BUFT_P_126:A 0.152 +18 chany_bottom_in[10]:11 chany_bottom_in[10]:10 1.116072e-05 +19 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.02049554 + +*END + +*D_NET chany_bottom_in[16] 0.01998504 //LENGTH 157.035 LUMPCC 0.008499499 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 76.820 1.290 +*I mux_left_track_21\/mux_l1_in_0_:A0 I *L 0.001631 *C 55.030 71.740 +*I mux_top_track_8\/mux_l2_in_1_:A0 I *L 0.001631 *C 80.675 93.160 +*I BUFT_RR_81:A I *L 0.001776 *C 63.480 110.160 +*N chany_bottom_in[16]:4 *C 76.880 31.960 +*N chany_bottom_in[16]:5 *C 63.480 110.160 +*N chany_bottom_in[16]:6 *C 63.480 110.160 +*N chany_bottom_in[16]:7 *C 63.488 110.160 +*N chany_bottom_in[16]:8 *C 76.340 110.160 +*N chany_bottom_in[16]:9 *C 76.360 110.153 +*N chany_bottom_in[16]:10 *C 80.638 93.160 +*N chany_bottom_in[16]:11 *C 79.165 93.160 +*N chany_bottom_in[16]:12 *C 79.120 93.115 +*N chany_bottom_in[16]:13 *C 79.120 91.858 +*N chany_bottom_in[16]:14 *C 79.112 91.800 +*N chany_bottom_in[16]:15 *C 76.380 91.800 +*N chany_bottom_in[16]:16 *C 76.360 91.800 +*N chany_bottom_in[16]:17 *C 55.068 71.740 +*N chany_bottom_in[16]:18 *C 68.035 71.740 +*N chany_bottom_in[16]:19 *C 68.080 71.785 +*N chany_bottom_in[16]:20 *C 68.080 74.062 +*N chany_bottom_in[16]:21 *C 68.088 74.120 +*N chany_bottom_in[16]:22 *C 76.340 74.120 +*N chany_bottom_in[16]:23 *C 76.360 74.120 +*N chany_bottom_in[16]:24 *C 77.280 74.120 +*N chany_bottom_in[16]:25 *C 77.280 31.968 +*N chany_bottom_in[16]:26 *C 77.280 31.960 +*N chany_bottom_in[16]:27 *C 77.280 31.902 +*N chany_bottom_in[16]:28 *C 77.280 11.900 +*N chany_bottom_in[16]:29 *C 76.820 11.900 + +*CAP +0 chany_bottom_in[16] 0.0005399942 +1 mux_left_track_21\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_8\/mux_l2_in_1_:A0 1e-06 +3 BUFT_RR_81:A 1e-06 +4 chany_bottom_in[16]:4 7.295744e-05 +5 chany_bottom_in[16]:5 3.297138e-05 +6 chany_bottom_in[16]:6 3.399682e-05 +7 chany_bottom_in[16]:7 0.0008511297 +8 chany_bottom_in[16]:8 0.0008511297 +9 chany_bottom_in[16]:9 0.0004725379 +10 chany_bottom_in[16]:10 0.0001194136 +11 chany_bottom_in[16]:11 0.0001194136 +12 chany_bottom_in[16]:12 9.782119e-05 +13 chany_bottom_in[16]:13 9.782119e-05 +14 chany_bottom_in[16]:14 0.00015908 +15 chany_bottom_in[16]:15 0.00015908 +16 chany_bottom_in[16]:16 0.0009490494 +17 chany_bottom_in[16]:17 0.0003368749 +18 chany_bottom_in[16]:18 0.0003368749 +19 chany_bottom_in[16]:19 0.0001484734 +20 chany_bottom_in[16]:20 0.0001484734 +21 chany_bottom_in[16]:21 0.0006283952 +22 chany_bottom_in[16]:22 0.0006283952 +23 chany_bottom_in[16]:23 0.0005241978 +24 chany_bottom_in[16]:24 0.001004539 +25 chany_bottom_in[16]:25 0.0009568528 +26 chany_bottom_in[16]:26 7.295744e-05 +27 chany_bottom_in[16]:27 0.000770442 +28 chany_bottom_in[16]:28 0.0008000574 +29 chany_bottom_in[16]:29 0.0005696096 +30 chany_bottom_in[16]:9 chany_top_in[8]:20 0.0001473118 +31 chany_bottom_in[16]:9 chany_top_in[8]:21 0.0001041667 +32 chany_bottom_in[16]:25 chany_top_in[8]:19 9.827306e-05 +33 chany_bottom_in[16]:16 chany_top_in[8]:19 0.0001473118 +34 chany_bottom_in[16]:16 chany_top_in[8]:20 0.000344046 +35 chany_bottom_in[16]:23 chany_top_in[8]:19 0.0002398792 +36 chany_bottom_in[16]:24 chany_top_in[8]:20 9.827306e-05 +37 chany_bottom_in[16]:27 chany_top_in[10]:7 0.0003760994 +38 chany_bottom_in[16]:28 chany_top_in[10]:6 0.0003760994 +39 chany_bottom_in[16]:20 chany_top_in[16]:15 6.913083e-07 +40 chany_bottom_in[16]:20 chany_top_in[16]:17 2.581228e-05 +41 chany_bottom_in[16]:18 chany_top_in[16]:12 0.0001524659 +42 chany_bottom_in[16]:18 chany_top_in[16]:14 5.914487e-05 +43 chany_bottom_in[16]:18 chany_top_in[16]:16 2.082422e-05 +44 chany_bottom_in[16]:19 chany_top_in[16]:10 6.913083e-07 +45 chany_bottom_in[16]:19 chany_top_in[16]:16 2.581228e-05 +46 chany_bottom_in[16]:17 chany_top_in[16]:11 0.0001524659 +47 chany_bottom_in[16]:17 chany_top_in[16]:13 5.914487e-05 +48 chany_bottom_in[16]:17 chany_top_in[16]:15 2.082422e-05 +49 chany_bottom_in[16] chany_top_in[17]:9 3.242907e-07 +50 chany_bottom_in[16]:9 chany_top_in[17]:29 0.0002664041 +51 chany_bottom_in[16]:27 chany_top_in[17]:18 7.58606e-05 +52 chany_bottom_in[16]:16 chany_top_in[17]:28 0.0002664041 +53 chany_bottom_in[16]:16 chany_top_in[17]:29 7.085694e-05 +54 chany_bottom_in[16]:23 chany_top_in[17]:28 7.085694e-05 +55 chany_bottom_in[16]:29 chany_top_in[17]:10 3.242907e-07 +56 chany_bottom_in[16]:28 chany_top_in[17]:17 7.58606e-05 +57 chany_bottom_in[16]:25 chany_bottom_in[2]:32 0.0001798862 +58 chany_bottom_in[16]:15 chany_bottom_in[2]:28 6.505901e-05 +59 chany_bottom_in[16]:16 chany_bottom_in[2]:30 3.175058e-05 +60 chany_bottom_in[16]:16 chany_bottom_in[2]:31 5.888338e-05 +61 chany_bottom_in[16]:14 chany_bottom_in[2]:29 6.505901e-05 +62 chany_bottom_in[16]:23 chany_bottom_in[2]:31 3.175058e-05 +63 chany_bottom_in[16]:23 chany_bottom_in[2]:32 5.888338e-05 +64 chany_bottom_in[16]:24 chany_bottom_in[2]:31 0.0001798862 +65 chany_bottom_in[16] chany_bottom_in[8] 4.422068e-05 +66 chany_bottom_in[16]:25 chany_bottom_in[8]:24 0.0001675423 +67 chany_bottom_in[16]:25 chany_bottom_in[8]:25 0.0004856529 +68 chany_bottom_in[16]:29 chany_bottom_in[8]:28 4.422068e-05 +69 chany_bottom_in[16]:24 chany_bottom_in[8]:23 0.0001675423 +70 chany_bottom_in[16]:24 chany_bottom_in[8]:24 0.0004856529 +71 chany_bottom_in[16] chany_bottom_in[19] 9.889742e-06 +72 chany_bottom_in[16]:25 chany_bottom_in[19]:10 0.001023188 +73 chany_bottom_in[16]:27 chany_bottom_in[19]:13 8.270324e-06 +74 chany_bottom_in[16]:29 chany_bottom_in[19]:13 9.889742e-06 +75 chany_bottom_in[16]:28 chany_bottom_in[19] 8.270324e-06 +76 chany_bottom_in[16]:24 chany_bottom_in[19]:9 0.001023188 +77 chany_bottom_in[16]:18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004873398 +78 chany_bottom_in[16]:17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0004873398 +79 chany_bottom_in[16] ropt_net_200:4 9.941968e-06 +80 chany_bottom_in[16] ropt_net_200:6 4.001013e-05 +81 chany_bottom_in[16]:29 ropt_net_200:7 4.001013e-05 +82 chany_bottom_in[16]:29 ropt_net_200:5 9.941968e-06 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:29 0.009473214 +1 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.002013558 +2 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.00341 +3 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.0045 +4 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.00341 +5 chany_bottom_in[16]:5 BUFT_RR_81:A 0.152 +6 chany_bottom_in[16]:26 chany_bottom_in[16]:25 0.00341 +7 chany_bottom_in[16]:26 chany_bottom_in[16]:4 5.69697e-05 +8 chany_bottom_in[16]:25 chany_bottom_in[16]:24 0.006603891 +9 chany_bottom_in[16]:27 chany_bottom_in[16]:26 0.00341 +10 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.0004280916 +11 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.00341 +12 chany_bottom_in[16]:16 chany_bottom_in[16]:9 0.002875225 +13 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.001122768 +14 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.00341 +15 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.001314732 +16 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.0045 +17 chany_bottom_in[16]:10 mux_top_track_8\/mux_l2_in_1_:A0 0.152 +18 chany_bottom_in[16]:22 chany_bottom_in[16]:21 0.001292892 +19 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.00341 +20 chany_bottom_in[16]:23 chany_bottom_in[16]:16 0.002769866 +21 chany_bottom_in[16]:20 chany_bottom_in[16]:19 0.002033482 +22 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.00341 +23 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.01157813 +24 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.0045 +25 chany_bottom_in[16]:17 mux_left_track_21\/mux_l1_in_0_:A0 0.152 +26 chany_bottom_in[16]:29 chany_bottom_in[16]:28 0.0004107143 +27 chany_bottom_in[16]:28 chany_bottom_in[16]:27 0.01785938 +28 chany_bottom_in[16]:24 chany_bottom_in[16]:23 0.0001441333 + +*END + +*D_NET chany_bottom_in[17] 0.01988857 //LENGTH 166.810 LUMPCC 0.004947519 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 69.920 1.325 +*I mux_left_track_23\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.790 77.180 +*I mux_top_track_16\/mux_l1_in_1_:A0 I *L 0.001631 *C 63.770 96.900 +*I BUFT_P_129:A I *L 0.001776 *C 90.160 121.040 +*N chany_bottom_in[17]:4 *C 90.123 121.040 +*N chany_bottom_in[17]:5 *C 88.365 121.040 +*N chany_bottom_in[17]:6 *C 88.320 120.995 +*N chany_bottom_in[17]:7 *C 88.320 98.657 +*N chany_bottom_in[17]:8 *C 88.312 98.600 +*N chany_bottom_in[17]:9 *C 71.767 98.600 +*N chany_bottom_in[17]:10 *C 71.760 98.543 +*N chany_bottom_in[17]:11 *C 71.760 96.945 +*N chany_bottom_in[17]:12 *C 71.715 96.900 +*N chany_bottom_in[17]:13 *C 63.808 96.900 +*N chany_bottom_in[17]:14 *C 63.480 96.900 +*N chany_bottom_in[17]:15 *C 63.480 96.855 +*N chany_bottom_in[17]:16 *C 63.480 95.925 +*N chany_bottom_in[17]:17 *C 63.435 95.880 +*N chany_bottom_in[17]:18 *C 59.385 95.880 +*N chany_bottom_in[17]:19 *C 59.340 95.835 +*N chany_bottom_in[17]:20 *C 57.828 77.180 +*N chany_bottom_in[17]:21 *C 59.295 77.180 +*N chany_bottom_in[17]:22 *C 59.340 77.180 +*N chany_bottom_in[17]:23 *C 59.340 74.858 +*N chany_bottom_in[17]:24 *C 59.348 74.800 +*N chany_bottom_in[17]:25 *C 67.140 74.800 +*N chany_bottom_in[17]:26 *C 67.160 74.793 +*N chany_bottom_in[17]:27 *C 67.160 53.235 +*N chany_bottom_in[17]:28 *C 67.160 3.408 +*N chany_bottom_in[17]:29 *C 67.180 3.400 +*N chany_bottom_in[17]:30 *C 69.913 3.400 +*N chany_bottom_in[17]:31 *C 69.920 3.343 + +*CAP +0 chany_bottom_in[17] 0.0001425956 +1 mux_left_track_23\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_1_:A0 1e-06 +3 BUFT_P_129:A 1e-06 +4 chany_bottom_in[17]:4 0.0001226594 +5 chany_bottom_in[17]:5 0.0001226594 +6 chany_bottom_in[17]:6 0.0008691792 +7 chany_bottom_in[17]:7 0.0008691792 +8 chany_bottom_in[17]:8 0.001044327 +9 chany_bottom_in[17]:9 0.001044327 +10 chany_bottom_in[17]:10 0.0001097965 +11 chany_bottom_in[17]:11 0.0001097965 +12 chany_bottom_in[17]:12 0.0004826849 +13 chany_bottom_in[17]:13 0.0005026361 +14 chany_bottom_in[17]:14 5.567676e-05 +15 chany_bottom_in[17]:15 7.936104e-05 +16 chany_bottom_in[17]:16 7.936104e-05 +17 chany_bottom_in[17]:17 0.0002950738 +18 chany_bottom_in[17]:18 0.0002950738 +19 chany_bottom_in[17]:19 0.001024239 +20 chany_bottom_in[17]:20 0.0001189348 +21 chany_bottom_in[17]:21 0.0001189348 +22 chany_bottom_in[17]:22 0.00119618 +23 chany_bottom_in[17]:23 0.000140121 +24 chany_bottom_in[17]:24 0.0005424511 +25 chany_bottom_in[17]:25 0.0005424511 +26 chany_bottom_in[17]:26 0.0004281605 +27 chany_bottom_in[17]:27 0.002197763 +28 chany_bottom_in[17]:28 0.001769603 +29 chany_bottom_in[17]:29 0.0002461168 +30 chany_bottom_in[17]:30 0.0002461168 +31 chany_bottom_in[17]:31 0.0001425956 +32 chany_bottom_in[17]:7 chany_top_in[9]:12 0.0001042353 +33 chany_bottom_in[17]:7 chany_top_in[9]:13 0.0001706298 +34 chany_bottom_in[17]:6 chany_top_in[9]:13 0.0001042353 +35 chany_bottom_in[17]:6 chany_top_in[9]:14 0.0001706298 +36 chany_bottom_in[17]:26 chany_top_in[10]:25 0.0004648048 +37 chany_bottom_in[17]:28 chany_top_in[10]:24 0.0001271794 +38 chany_bottom_in[17]:27 chany_top_in[10]:24 0.0004648048 +39 chany_bottom_in[17]:27 chany_top_in[10]:25 0.0001271794 +40 chany_bottom_in[17]:26 chany_top_in[18]:20 0.000284983 +41 chany_bottom_in[17]:26 chany_top_in[18]:21 0.0001798218 +42 chany_bottom_in[17]:28 chany_top_in[18]:14 0.0008566664 +43 chany_bottom_in[17]:7 chany_top_in[18]:24 6.60352e-06 +44 chany_bottom_in[17]:6 chany_top_in[18]:25 6.60352e-06 +45 chany_bottom_in[17]:27 chany_top_in[18]:14 0.000284983 +46 chany_bottom_in[17]:27 chany_top_in[18]:20 0.001036488 +47 chany_bottom_in[17]:28 chany_bottom_in[1]:14 0.0002788354 +48 chany_bottom_in[17]:27 chany_bottom_in[1]:13 0.0002788354 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:31 0.001801339 +1 chany_bottom_in[17]:23 chany_bottom_in[17]:22 0.002073661 +2 chany_bottom_in[17]:24 chany_bottom_in[17]:23 0.00341 +3 chany_bottom_in[17]:25 chany_bottom_in[17]:24 0.001220825 +4 chany_bottom_in[17]:26 chany_bottom_in[17]:25 0.00341 +5 chany_bottom_in[17]:29 chany_bottom_in[17]:28 0.00341 +6 chany_bottom_in[17]:28 chany_bottom_in[17]:27 0.007806308 +7 chany_bottom_in[17]:31 chany_bottom_in[17]:30 0.00341 +8 chany_bottom_in[17]:30 chany_bottom_in[17]:29 0.0004280917 +9 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.0045 +10 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.001426339 +11 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.00341 +12 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.00259205 +13 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.0199442 +14 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.00341 +15 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.001569197 +16 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.0045 +17 chany_bottom_in[17]:4 BUFT_P_129:A 0.152 +18 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.001310268 +19 chany_bottom_in[17]:22 chany_bottom_in[17]:21 0.0045 +20 chany_bottom_in[17]:22 chany_bottom_in[17]:19 0.01665625 +21 chany_bottom_in[17]:20 mux_left_track_23\/mux_l1_in_0_:A0 0.152 +22 chany_bottom_in[17]:13 mux_top_track_16\/mux_l1_in_1_:A0 0.152 +23 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.007060268 +24 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.0001779892 +25 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.0045 +26 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.0045 +27 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.0008303572 +28 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.003616072 +29 chany_bottom_in[17]:19 chany_bottom_in[17]:18 0.0045 +30 chany_bottom_in[17]:27 chany_bottom_in[17]:26 0.003377341 + +*END + +*D_NET top_left_grid_pin_34_[0] 0.01054819 //LENGTH 62.855 LUMPCC 0.004507917 DR + +*CONN +*P top_left_grid_pin_34_[0] I *L 0.29796 *C 32.660 129.235 +*I mux_top_track_0\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.400 126.820 +*I mux_top_track_4\/mux_l1_in_0_:A1 I *L 0.00198 *C 45.080 115.940 +*I mux_top_track_8\/mux_l1_in_0_:A1 I *L 0.00198 *C 75.440 115.940 +*N top_left_grid_pin_34_[0]:4 *C 75.440 115.940 +*N top_left_grid_pin_34_[0]:5 *C 75.440 115.260 +*N top_left_grid_pin_34_[0]:6 *C 65.365 115.260 +*N top_left_grid_pin_34_[0]:7 *C 65.320 115.260 +*N top_left_grid_pin_34_[0]:8 *C 65.320 115.600 +*N top_left_grid_pin_34_[0]:9 *C 65.312 115.600 +*N top_left_grid_pin_34_[0]:10 *C 45.547 115.600 +*N top_left_grid_pin_34_[0]:11 *C 45.540 115.600 +*N top_left_grid_pin_34_[0]:12 *C 45.117 115.940 +*N top_left_grid_pin_34_[0]:13 *C 45.495 115.940 +*N top_left_grid_pin_34_[0]:14 *C 45.540 115.985 +*N top_left_grid_pin_34_[0]:15 *C 45.540 127.160 +*N top_left_grid_pin_34_[0]:16 *C 45.080 127.160 +*N top_left_grid_pin_34_[0]:17 *C 45.080 128.463 +*N top_left_grid_pin_34_[0]:18 *C 45.073 128.520 +*N top_left_grid_pin_34_[0]:19 *C 41.363 126.820 +*N top_left_grid_pin_34_[0]:20 *C 40.985 126.820 +*N top_left_grid_pin_34_[0]:21 *C 40.940 126.865 +*N top_left_grid_pin_34_[0]:22 *C 40.940 128.463 +*N top_left_grid_pin_34_[0]:23 *C 40.940 128.520 +*N top_left_grid_pin_34_[0]:24 *C 32.668 128.520 +*N top_left_grid_pin_34_[0]:25 *C 32.660 128.578 + +*CAP +0 top_left_grid_pin_34_[0] 5.462512e-05 +1 mux_top_track_0\/mux_l1_in_0_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_34_[0]:4 7.52263e-05 +5 top_left_grid_pin_34_[0]:5 0.0005901583 +6 top_left_grid_pin_34_[0]:6 0.0005439356 +7 top_left_grid_pin_34_[0]:7 5.140965e-05 +8 top_left_grid_pin_34_[0]:8 5.520697e-05 +9 top_left_grid_pin_34_[0]:9 0.0005699649 +10 top_left_grid_pin_34_[0]:10 0.0005699649 +11 top_left_grid_pin_34_[0]:11 5.705408e-05 +12 top_left_grid_pin_34_[0]:12 5.723643e-05 +13 top_left_grid_pin_34_[0]:13 5.723643e-05 +14 top_left_grid_pin_34_[0]:14 0.0005894243 +15 top_left_grid_pin_34_[0]:15 0.0005973855 +16 top_left_grid_pin_34_[0]:16 0.0001128759 +17 top_left_grid_pin_34_[0]:17 8.369611e-05 +18 top_left_grid_pin_34_[0]:18 0.0003027011 +19 top_left_grid_pin_34_[0]:19 5.890617e-05 +20 top_left_grid_pin_34_[0]:20 5.890617e-05 +21 top_left_grid_pin_34_[0]:21 0.0001076108 +22 top_left_grid_pin_34_[0]:22 0.0001076108 +23 top_left_grid_pin_34_[0]:23 0.0007921059 +24 top_left_grid_pin_34_[0]:24 0.0004894048 +25 top_left_grid_pin_34_[0]:25 5.462512e-05 +26 top_left_grid_pin_34_[0]:10 chany_top_in[11]:14 0.001069981 +27 top_left_grid_pin_34_[0]:9 chany_top_in[11]:15 0.001069981 +28 top_left_grid_pin_34_[0]:6 chany_top_in[11]:14 6.003252e-06 +29 top_left_grid_pin_34_[0]:5 chany_top_in[11]:15 6.003252e-06 +30 top_left_grid_pin_34_[0]:10 top_left_grid_pin_38_[0]:8 0.0008234975 +31 top_left_grid_pin_34_[0]:9 top_left_grid_pin_38_[0]:7 0.0008234975 +32 top_left_grid_pin_34_[0]:6 top_left_grid_pin_38_[0]:5 9.178608e-05 +33 top_left_grid_pin_34_[0]:5 top_left_grid_pin_38_[0]:4 9.178608e-05 +34 top_left_grid_pin_34_[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000119704 +35 top_left_grid_pin_34_[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000119704 +36 top_left_grid_pin_34_[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0001429874 +37 top_left_grid_pin_34_[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0001429874 + +*RES +0 top_left_grid_pin_34_[0] top_left_grid_pin_34_[0]:25 0.0005870535 +1 top_left_grid_pin_34_[0]:19 mux_top_track_0\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_34_[0]:20 top_left_grid_pin_34_[0]:19 0.0003370536 +3 top_left_grid_pin_34_[0]:21 top_left_grid_pin_34_[0]:20 0.0045 +4 top_left_grid_pin_34_[0]:22 top_left_grid_pin_34_[0]:21 0.001426339 +5 top_left_grid_pin_34_[0]:23 top_left_grid_pin_34_[0]:22 0.00341 +6 top_left_grid_pin_34_[0]:23 top_left_grid_pin_34_[0]:18 0.000647425 +7 top_left_grid_pin_34_[0]:17 top_left_grid_pin_34_[0]:16 0.001162947 +8 top_left_grid_pin_34_[0]:18 top_left_grid_pin_34_[0]:17 0.00341 +9 top_left_grid_pin_34_[0]:11 top_left_grid_pin_34_[0]:10 0.00341 +10 top_left_grid_pin_34_[0]:10 top_left_grid_pin_34_[0]:9 0.003096516 +11 top_left_grid_pin_34_[0]:8 top_left_grid_pin_34_[0]:7 0.0001634615 +12 top_left_grid_pin_34_[0]:9 top_left_grid_pin_34_[0]:8 0.00341 +13 top_left_grid_pin_34_[0]:6 top_left_grid_pin_34_[0]:5 0.008995537 +14 top_left_grid_pin_34_[0]:7 top_left_grid_pin_34_[0]:6 0.0045 +15 top_left_grid_pin_34_[0]:4 mux_top_track_8\/mux_l1_in_0_:A1 0.152 +16 top_left_grid_pin_34_[0]:25 top_left_grid_pin_34_[0]:24 0.00341 +17 top_left_grid_pin_34_[0]:24 top_left_grid_pin_34_[0]:23 0.001296025 +18 top_left_grid_pin_34_[0]:13 top_left_grid_pin_34_[0]:12 0.0003370536 +19 top_left_grid_pin_34_[0]:14 top_left_grid_pin_34_[0]:13 0.0045 +20 top_left_grid_pin_34_[0]:14 top_left_grid_pin_34_[0]:11 0.0001850962 +21 top_left_grid_pin_34_[0]:12 mux_top_track_4\/mux_l1_in_0_:A1 0.152 +22 top_left_grid_pin_34_[0]:5 top_left_grid_pin_34_[0]:4 0.0006071429 +23 top_left_grid_pin_34_[0]:16 top_left_grid_pin_34_[0]:15 0.0004107143 +24 top_left_grid_pin_34_[0]:15 top_left_grid_pin_34_[0]:14 0.009977679 + +*END + +*D_NET top_left_grid_pin_37_[0] 0.006157068 //LENGTH 49.748 LUMPCC 6.79939e-05 DR + +*CONN +*P top_left_grid_pin_37_[0] I *L 0.29796 *C 31.740 129.270 +*I mux_top_track_2\/mux_l1_in_0_:A0 I *L 0.001631 *C 37.550 113.220 +*I mux_top_track_4\/mux_l1_in_1_:A0 I *L 0.001631 *C 43.415 113.220 +*I mux_top_track_32\/mux_l1_in_0_:A1 I *L 0.00198 *C 46.100 96.220 +*N top_left_grid_pin_37_[0]:4 *C 46.000 96.220 +*N top_left_grid_pin_37_[0]:5 *C 46.000 96.265 +*N top_left_grid_pin_37_[0]:6 *C 46.000 112.835 +*N top_left_grid_pin_37_[0]:7 *C 45.955 112.880 +*N top_left_grid_pin_37_[0]:8 *C 43.240 112.880 +*N top_left_grid_pin_37_[0]:9 *C 43.290 113.198 +*N top_left_grid_pin_37_[0]:10 *C 43.240 113.220 +*N top_left_grid_pin_37_[0]:11 *C 37.550 113.220 +*N top_left_grid_pin_37_[0]:12 *C 31.325 113.220 +*N top_left_grid_pin_37_[0]:13 *C 31.280 113.265 +*N top_left_grid_pin_37_[0]:14 *C 31.280 127.840 +*N top_left_grid_pin_37_[0]:15 *C 31.740 127.840 + +*CAP +0 top_left_grid_pin_37_[0] 9.194457e-05 +1 mux_top_track_2\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:A0 1e-06 +3 mux_top_track_32\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_37_[0]:4 3.403582e-05 +5 top_left_grid_pin_37_[0]:5 0.0009992401 +6 top_left_grid_pin_37_[0]:6 0.0009992401 +7 top_left_grid_pin_37_[0]:7 0.0002056983 +8 top_left_grid_pin_37_[0]:8 0.000226718 +9 top_left_grid_pin_37_[0]:9 4.184818e-05 +10 top_left_grid_pin_37_[0]:10 0.0003985943 +11 top_left_grid_pin_37_[0]:11 0.0007841206 +12 top_left_grid_pin_37_[0]:12 0.0003787094 +13 top_left_grid_pin_37_[0]:13 0.0008899029 +14 top_left_grid_pin_37_[0]:14 0.0009169901 +15 top_left_grid_pin_37_[0]:15 0.0001190317 +16 top_left_grid_pin_37_[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.399695e-05 +17 top_left_grid_pin_37_[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.399695e-05 + +*RES +0 top_left_grid_pin_37_[0] top_left_grid_pin_37_[0]:15 0.001276786 +1 top_left_grid_pin_37_[0]:4 mux_top_track_32\/mux_l1_in_0_:A1 0.152 +2 top_left_grid_pin_37_[0]:5 top_left_grid_pin_37_[0]:4 0.0045 +3 top_left_grid_pin_37_[0]:7 top_left_grid_pin_37_[0]:6 0.0045 +4 top_left_grid_pin_37_[0]:6 top_left_grid_pin_37_[0]:5 0.01479464 +5 top_left_grid_pin_37_[0]:11 mux_top_track_2\/mux_l1_in_0_:A0 0.152 +6 top_left_grid_pin_37_[0]:11 top_left_grid_pin_37_[0]:10 0.005080357 +7 top_left_grid_pin_37_[0]:9 mux_top_track_4\/mux_l1_in_1_:A0 0.152 +8 top_left_grid_pin_37_[0]:9 top_left_grid_pin_37_[0]:8 0.0002834821 +9 top_left_grid_pin_37_[0]:12 top_left_grid_pin_37_[0]:11 0.005558036 +10 top_left_grid_pin_37_[0]:13 top_left_grid_pin_37_[0]:12 0.0045 +11 top_left_grid_pin_37_[0]:10 top_left_grid_pin_37_[0]:9 4.464286e-05 +12 top_left_grid_pin_37_[0]:8 top_left_grid_pin_37_[0]:7 0.002424107 +13 top_left_grid_pin_37_[0]:14 top_left_grid_pin_37_[0]:13 0.01301339 +14 top_left_grid_pin_37_[0]:15 top_left_grid_pin_37_[0]:14 0.0004107143 + +*END + +*D_NET top_right_grid_pin_1_[0] 0.009768211 //LENGTH 88.925 LUMPCC 0.0008947287 DR + +*CONN +*P top_right_grid_pin_1_[0] I *L 0.29796 *C 108.100 129.270 +*I mux_top_track_8\/mux_l2_in_0_:A0 I *L 0.001631 *C 81.595 104.380 +*I mux_top_track_4\/mux_l1_in_4_:A1 I *L 0.00198 *C 63.845 101.660 +*I mux_top_track_0\/mux_l1_in_2_:A1 I *L 0.00198 *C 63.020 117.980 +*N top_right_grid_pin_1_[0]:4 *C 63.020 117.980 +*N top_right_grid_pin_1_[0]:5 *C 63.055 118.320 +*N top_right_grid_pin_1_[0]:6 *C 63.895 118.320 +*N top_right_grid_pin_1_[0]:7 *C 63.940 118.275 +*N top_right_grid_pin_1_[0]:8 *C 63.845 101.660 +*N top_right_grid_pin_1_[0]:9 *C 63.940 101.705 +*N top_right_grid_pin_1_[0]:10 *C 63.940 104.040 +*N top_right_grid_pin_1_[0]:11 *C 63.985 104.040 +*N top_right_grid_pin_1_[0]:12 *C 81.595 104.040 +*N top_right_grid_pin_1_[0]:13 *C 81.595 104.380 +*N top_right_grid_pin_1_[0]:14 *C 108.055 104.380 +*N top_right_grid_pin_1_[0]:15 *C 108.100 104.425 + +*CAP +0 top_right_grid_pin_1_[0] 0.001112375 +1 mux_top_track_8\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_4\/mux_l1_in_4_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_2_:A1 1e-06 +4 top_right_grid_pin_1_[0]:4 5.97153e-05 +5 top_right_grid_pin_1_[0]:5 0.0001043033 +6 top_right_grid_pin_1_[0]:6 7.413473e-05 +7 top_right_grid_pin_1_[0]:7 0.0005368331 +8 top_right_grid_pin_1_[0]:8 2.775912e-05 +9 top_right_grid_pin_1_[0]:9 9.132881e-05 +10 top_right_grid_pin_1_[0]:10 0.0006607517 +11 top_right_grid_pin_1_[0]:11 0.0011148 +12 top_right_grid_pin_1_[0]:12 0.001141369 +13 top_right_grid_pin_1_[0]:13 0.001430654 +14 top_right_grid_pin_1_[0]:14 0.001404085 +15 top_right_grid_pin_1_[0]:15 0.001112375 +16 top_right_grid_pin_1_[0]:7 chany_bottom_in[8]:8 0.0003807323 +17 top_right_grid_pin_1_[0]:9 chany_bottom_in[8]:11 6.663206e-05 +18 top_right_grid_pin_1_[0]:10 chany_bottom_in[8]:8 6.663206e-05 +19 top_right_grid_pin_1_[0]:10 chany_bottom_in[8]:11 0.0003807323 + +*RES +0 top_right_grid_pin_1_[0] top_right_grid_pin_1_[0]:15 0.02218304 +1 top_right_grid_pin_1_[0]:14 top_right_grid_pin_1_[0]:13 0.023625 +2 top_right_grid_pin_1_[0]:15 top_right_grid_pin_1_[0]:14 0.0045 +3 top_right_grid_pin_1_[0]:6 top_right_grid_pin_1_[0]:5 0.00075 +4 top_right_grid_pin_1_[0]:7 top_right_grid_pin_1_[0]:6 0.0045 +5 top_right_grid_pin_1_[0]:4 mux_top_track_0\/mux_l1_in_2_:A1 0.152 +6 top_right_grid_pin_1_[0]:13 mux_top_track_8\/mux_l2_in_0_:A0 0.152 +7 top_right_grid_pin_1_[0]:13 top_right_grid_pin_1_[0]:12 0.0003035715 +8 top_right_grid_pin_1_[0]:8 mux_top_track_4\/mux_l1_in_4_:A1 0.152 +9 top_right_grid_pin_1_[0]:9 top_right_grid_pin_1_[0]:8 0.0045 +10 top_right_grid_pin_1_[0]:11 top_right_grid_pin_1_[0]:10 0.0045 +11 top_right_grid_pin_1_[0]:10 top_right_grid_pin_1_[0]:9 0.002084821 +12 top_right_grid_pin_1_[0]:10 top_right_grid_pin_1_[0]:7 0.01270982 +13 top_right_grid_pin_1_[0]:5 top_right_grid_pin_1_[0]:4 0.0002297297 +14 top_right_grid_pin_1_[0]:12 top_right_grid_pin_1_[0]:11 0.01572322 + +*END + +*D_NET chany_bottom_in[15] 0.006145344 //LENGTH 52.985 LUMPCC 0.0006853617 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 53.360 1.325 +*I mux_left_track_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 49.050 48.280 +*N chany_bottom_in[15]:2 *C 52.960 4.080 +*N chany_bottom_in[15]:3 *C 49.050 48.280 +*N chany_bottom_in[15]:4 *C 49.220 48.280 +*N chany_bottom_in[15]:5 *C 49.220 48.280 +*N chany_bottom_in[15]:6 *C 49.227 48.280 +*N chany_bottom_in[15]:7 *C 53.340 48.280 +*N chany_bottom_in[15]:8 *C 53.360 48.273 +*N chany_bottom_in[15]:9 *C 53.360 4.088 +*N chany_bottom_in[15]:10 *C 53.360 4.080 +*N chany_bottom_in[15]:11 *C 53.360 4.022 + +*CAP +0 chany_bottom_in[15] 0.000179541 +1 mux_left_track_13\/mux_l2_in_0_:A0 1e-06 +2 chany_bottom_in[15]:2 5.475809e-05 +3 chany_bottom_in[15]:3 5.260157e-05 +4 chany_bottom_in[15]:4 5.810622e-05 +5 chany_bottom_in[15]:5 3.741022e-05 +6 chany_bottom_in[15]:6 0.0002921023 +7 chany_bottom_in[15]:7 0.0002921023 +8 chany_bottom_in[15]:8 0.002129031 +9 chany_bottom_in[15]:9 0.002129031 +10 chany_bottom_in[15]:10 5.475809e-05 +11 chany_bottom_in[15]:11 0.000179541 +12 chany_bottom_in[15]:8 chany_top_in[5]:18 0.0003426809 +13 chany_bottom_in[15]:9 chany_top_in[5]:17 0.0003426809 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:11 0.002408482 +1 chany_bottom_in[15]:3 mux_left_track_13\/mux_l2_in_0_:A0 0.152 +2 chany_bottom_in[15]:4 chany_bottom_in[15]:3 9.239131e-05 +3 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.0045 +4 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.00341 +5 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.0006442916 +6 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.00341 +7 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.00341 +8 chany_bottom_in[15]:10 chany_bottom_in[15]:2 5.69697e-05 +9 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.006922316 +10 chany_bottom_in[15]:11 chany_bottom_in[15]:10 0.00341 + +*END + +*D_NET bottom_left_grid_pin_37_[0] 0.007076894 //LENGTH 53.820 LUMPCC 0.0002427698 DR + +*CONN +*P bottom_left_grid_pin_37_[0] I *L 0.29796 *C 29.750 3.400 +*I mux_bottom_track_5\/mux_l1_in_3_:A1 I *L 0.00198 *C 33.680 3.740 +*I mux_bottom_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 56.025 14.620 +*I mux_bottom_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 64.860 20.060 +*N bottom_left_grid_pin_37_[0]:4 *C 64.823 20.060 +*N bottom_left_grid_pin_37_[0]:5 *C 60.305 20.060 +*N bottom_left_grid_pin_37_[0]:6 *C 60.260 20.015 +*N bottom_left_grid_pin_37_[0]:7 *C 60.260 14.665 +*N bottom_left_grid_pin_37_[0]:8 *C 60.215 14.620 +*N bottom_left_grid_pin_37_[0]:9 *C 56.025 14.620 +*N bottom_left_grid_pin_37_[0]:10 *C 53.405 14.620 +*N bottom_left_grid_pin_37_[0]:11 *C 53.360 14.575 +*N bottom_left_grid_pin_37_[0]:12 *C 53.360 6.165 +*N bottom_left_grid_pin_37_[0]:13 *C 53.315 6.120 +*N bottom_left_grid_pin_37_[0]:14 *C 33.625 6.120 +*N bottom_left_grid_pin_37_[0]:15 *C 33.580 6.075 +*N bottom_left_grid_pin_37_[0]:16 *C 33.580 3.740 +*N bottom_left_grid_pin_37_[0]:17 *C 33.580 3.785 +*N bottom_left_grid_pin_37_[0]:18 *C 33.580 3.400 +*N bottom_left_grid_pin_37_[0]:19 *C 33.573 3.400 + +*CAP +0 bottom_left_grid_pin_37_[0] 0.000229401 +1 mux_bottom_track_5\/mux_l1_in_3_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_9\/mux_l2_in_1_:A1 1e-06 +4 bottom_left_grid_pin_37_[0]:4 0.0002965999 +5 bottom_left_grid_pin_37_[0]:5 0.0002965999 +6 bottom_left_grid_pin_37_[0]:6 0.0003240874 +7 bottom_left_grid_pin_37_[0]:7 0.0003240874 +8 bottom_left_grid_pin_37_[0]:8 0.0002961825 +9 bottom_left_grid_pin_37_[0]:9 0.0005030456 +10 bottom_left_grid_pin_37_[0]:10 0.0001786413 +11 bottom_left_grid_pin_37_[0]:11 0.000522291 +12 bottom_left_grid_pin_37_[0]:12 0.000522291 +13 bottom_left_grid_pin_37_[0]:13 0.001367589 +14 bottom_left_grid_pin_37_[0]:14 0.001367589 +15 bottom_left_grid_pin_37_[0]:15 0.0001377224 +16 bottom_left_grid_pin_37_[0]:16 2.865578e-05 +17 bottom_left_grid_pin_37_[0]:17 0.0001554537 +18 bottom_left_grid_pin_37_[0]:18 5.148615e-05 +19 bottom_left_grid_pin_37_[0]:19 0.000229401 +20 bottom_left_grid_pin_37_[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001213849 +21 bottom_left_grid_pin_37_[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001213849 + +*RES +0 bottom_left_grid_pin_37_[0] bottom_left_grid_pin_37_[0]:19 0.0005988583 +1 bottom_left_grid_pin_37_[0]:14 bottom_left_grid_pin_37_[0]:13 0.01758036 +2 bottom_left_grid_pin_37_[0]:15 bottom_left_grid_pin_37_[0]:14 0.0045 +3 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_37_[0]:12 0.0045 +4 bottom_left_grid_pin_37_[0]:12 bottom_left_grid_pin_37_[0]:11 0.007508929 +5 bottom_left_grid_pin_37_[0]:10 bottom_left_grid_pin_37_[0]:9 0.002339286 +6 bottom_left_grid_pin_37_[0]:11 bottom_left_grid_pin_37_[0]:10 0.0045 +7 bottom_left_grid_pin_37_[0]:4 mux_bottom_track_9\/mux_l2_in_1_:A1 0.152 +8 bottom_left_grid_pin_37_[0]:5 bottom_left_grid_pin_37_[0]:4 0.004033483 +9 bottom_left_grid_pin_37_[0]:6 bottom_left_grid_pin_37_[0]:5 0.0045 +10 bottom_left_grid_pin_37_[0]:8 bottom_left_grid_pin_37_[0]:7 0.0045 +11 bottom_left_grid_pin_37_[0]:7 bottom_left_grid_pin_37_[0]:6 0.004776786 +12 bottom_left_grid_pin_37_[0]:16 mux_bottom_track_5\/mux_l1_in_3_:A1 0.152 +13 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:16 0.0045 +14 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:15 0.002044643 +15 bottom_left_grid_pin_37_[0]:9 mux_bottom_track_1\/mux_l1_in_2_:A1 0.152 +16 bottom_left_grid_pin_37_[0]:9 bottom_left_grid_pin_37_[0]:8 0.003741072 +17 bottom_left_grid_pin_37_[0]:18 bottom_left_grid_pin_37_[0]:17 0.0001850962 +18 bottom_left_grid_pin_37_[0]:19 bottom_left_grid_pin_37_[0]:18 0.00341 + +*END + +*D_NET chanx_left_in[0] 0.01143977 //LENGTH 80.695 LUMPCC 0.003486254 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.305 76.160 +*I mux_bottom_track_33\/mux_l1_in_1_:A0 I *L 0.001631 *C 20.875 33.320 +*I mux_top_track_0\/mux_l2_in_2_:A1 I *L 0.00198 *C 11.040 88.740 +*N chanx_left_in[0]:3 *C 11.040 88.740 +*N chanx_left_in[0]:4 *C 11.040 88.695 +*N chanx_left_in[0]:5 *C 11.040 81.657 +*N chanx_left_in[0]:6 *C 11.048 81.600 +*N chanx_left_in[0]:7 *C 11.940 81.600 +*N chanx_left_in[0]:8 *C 11.960 81.593 +*N chanx_left_in[0]:9 *C 20.450 36.040 +*N chanx_left_in[0]:10 *C 20.875 33.320 +*N chanx_left_in[0]:11 *C 21.160 33.320 +*N chanx_left_in[0]:12 *C 21.160 33.365 +*N chanx_left_in[0]:13 *C 21.160 35.983 +*N chanx_left_in[0]:14 *C 21.158 36.040 +*N chanx_left_in[0]:15 *C 21.160 36.047 +*N chanx_left_in[0]:16 *C 21.160 48.953 +*N chanx_left_in[0]:17 *C 21.140 48.960 +*N chanx_left_in[0]:18 *C 11.980 48.960 +*N chanx_left_in[0]:19 *C 11.960 48.968 +*N chanx_left_in[0]:20 *C 11.960 76.840 +*N chanx_left_in[0]:21 *C 11.940 76.840 +*N chanx_left_in[0]:22 *C 1.380 76.840 + +*CAP +0 chanx_left_in[0] 5.285756e-05 +1 mux_bottom_track_33\/mux_l1_in_1_:A0 1e-06 +2 mux_top_track_0\/mux_l2_in_2_:A1 1e-06 +3 chanx_left_in[0]:3 3.187903e-05 +4 chanx_left_in[0]:4 0.0004662523 +5 chanx_left_in[0]:5 0.0004662523 +6 chanx_left_in[0]:6 9.626924e-05 +7 chanx_left_in[0]:7 9.626924e-05 +8 chanx_left_in[0]:8 0.0001709039 +9 chanx_left_in[0]:9 0.0001386055 +10 chanx_left_in[0]:10 5.706022e-05 +11 chanx_left_in[0]:11 5.887789e-05 +12 chanx_left_in[0]:12 0.0001659867 +13 chanx_left_in[0]:13 0.0001659867 +14 chanx_left_in[0]:14 0.0001386055 +15 chanx_left_in[0]:15 0.0007730041 +16 chanx_left_in[0]:16 0.0007730041 +17 chanx_left_in[0]:17 0.0005110165 +18 chanx_left_in[0]:18 0.0005110165 +19 chanx_left_in[0]:19 0.0009708662 +20 chanx_left_in[0]:20 0.00114177 +21 chanx_left_in[0]:21 0.0005560875 +22 chanx_left_in[0]:22 0.000608945 +23 chanx_left_in[0]:19 chany_top_in[11]:8 0.0005182311 +24 chanx_left_in[0]:20 chany_top_in[11]:9 0.0005182311 +25 chanx_left_in[0]:21 chanx_left_in[15]:11 0.0005855809 +26 chanx_left_in[0]:22 chanx_left_in[15] 0.0005855809 +27 chanx_left_in[0]:8 left_top_grid_pin_44_[0]:15 9.289412e-06 +28 chanx_left_in[0]:8 left_top_grid_pin_44_[0]:16 2.497058e-05 +29 chanx_left_in[0]:18 left_top_grid_pin_44_[0]:8 9.201544e-05 +30 chanx_left_in[0]:19 left_top_grid_pin_44_[0]:9 0.0002092261 +31 chanx_left_in[0]:17 left_top_grid_pin_44_[0]:7 9.201544e-05 +32 chanx_left_in[0]:20 left_top_grid_pin_44_[0]:15 0.0002341967 +33 chanx_left_in[0]:20 left_top_grid_pin_44_[0]:9 9.289412e-06 +34 chanx_left_in[0]:8 left_top_grid_pin_49_[0]:24 0.000211769 +35 chanx_left_in[0]:19 left_top_grid_pin_49_[0]:23 6.61176e-05 +36 chanx_left_in[0]:21 left_top_grid_pin_49_[0]:21 2.592685e-05 +37 chanx_left_in[0]:20 left_top_grid_pin_49_[0]:23 0.000211769 +38 chanx_left_in[0]:20 left_top_grid_pin_49_[0]:24 6.61176e-05 +39 chanx_left_in[0]:22 left_top_grid_pin_49_[0]:22 2.592685e-05 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:22 0.0001065333 +1 chanx_left_in[0]:3 mux_top_track_0\/mux_l2_in_2_:A1 0.152 +2 chanx_left_in[0]:4 chanx_left_in[0]:3 0.0045 +3 chanx_left_in[0]:5 chanx_left_in[0]:4 0.006283483 +4 chanx_left_in[0]:6 chanx_left_in[0]:5 0.00341 +5 chanx_left_in[0]:7 chanx_left_in[0]:6 0.000139825 +6 chanx_left_in[0]:8 chanx_left_in[0]:7 0.00341 +7 chanx_left_in[0]:18 chanx_left_in[0]:17 0.001435067 +8 chanx_left_in[0]:19 chanx_left_in[0]:18 0.00341 +9 chanx_left_in[0]:17 chanx_left_in[0]:16 0.00341 +10 chanx_left_in[0]:16 chanx_left_in[0]:15 0.002021783 +11 chanx_left_in[0]:14 chanx_left_in[0]:13 0.00341 +12 chanx_left_in[0]:14 chanx_left_in[0]:9 0.0001039141 +13 chanx_left_in[0]:15 chanx_left_in[0]:14 0.00341 +14 chanx_left_in[0]:13 chanx_left_in[0]:12 0.002337054 +15 chanx_left_in[0]:11 chanx_left_in[0]:10 0.0001548913 +16 chanx_left_in[0]:12 chanx_left_in[0]:11 0.0045 +17 chanx_left_in[0]:10 mux_bottom_track_33\/mux_l1_in_1_:A0 0.152 +18 chanx_left_in[0]:21 chanx_left_in[0]:20 0.00341 +19 chanx_left_in[0]:20 chanx_left_in[0]:19 0.004366692 +20 chanx_left_in[0]:20 chanx_left_in[0]:8 0.0007445583 +21 chanx_left_in[0]:22 chanx_left_in[0]:21 0.0016544 + +*END + +*D_NET chanx_left_in[11] 0.01903277 //LENGTH 128.275 LUMPCC 0.006701292 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_track_9\/mux_l2_in_2_:A0 I *L 0.001631 *C 68.255 38.760 +*I mux_top_track_8\/mux_l2_in_2_:A0 I *L 0.001631 *C 71.935 86.020 +*N chanx_left_in[11]:3 *C 71.970 82.960 +*N chanx_left_in[11]:4 *C 71.972 86.020 +*N chanx_left_in[11]:5 *C 72.635 86.020 +*N chanx_left_in[11]:6 *C 72.680 85.975 +*N chanx_left_in[11]:7 *C 72.680 83.017 +*N chanx_left_in[11]:8 *C 72.678 82.960 +*N chanx_left_in[11]:9 *C 72.680 82.953 +*N chanx_left_in[11]:10 *C 72.680 48.968 +*N chanx_left_in[11]:11 *C 72.660 48.960 +*N chanx_left_in[11]:12 *C 71.308 48.960 +*N chanx_left_in[11]:13 *C 71.300 48.903 +*N chanx_left_in[11]:14 *C 71.300 40.120 +*N chanx_left_in[11]:15 *C 70.840 40.120 +*N chanx_left_in[11]:16 *C 68.293 38.760 +*N chanx_left_in[11]:17 *C 70.795 38.760 +*N chanx_left_in[11]:18 *C 70.840 38.760 +*N chanx_left_in[11]:19 *C 70.833 38.760 +*N chanx_left_in[11]:20 *C 27.620 38.760 +*N chanx_left_in[11]:21 *C 27.600 38.753 +*N chanx_left_in[11]:22 *C 27.600 36.727 +*N chanx_left_in[11]:23 *C 27.580 36.720 + +*CAP +0 chanx_left_in[11] 0.001143762 +1 mux_bottom_track_9\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_8\/mux_l2_in_2_:A0 1e-06 +3 chanx_left_in[11]:3 8.407614e-05 +4 chanx_left_in[11]:4 5.760849e-05 +5 chanx_left_in[11]:5 5.760849e-05 +6 chanx_left_in[11]:6 0.0001727151 +7 chanx_left_in[11]:7 0.0001727151 +8 chanx_left_in[11]:8 8.407614e-05 +9 chanx_left_in[11]:9 0.001406156 +10 chanx_left_in[11]:10 0.001406156 +11 chanx_left_in[11]:11 0.0001707366 +12 chanx_left_in[11]:12 0.0001707366 +13 chanx_left_in[11]:13 0.0005750376 +14 chanx_left_in[11]:14 0.0006052331 +15 chanx_left_in[11]:15 0.0001072097 +16 chanx_left_in[11]:16 0.0001818112 +17 chanx_left_in[11]:17 0.0001818112 +18 chanx_left_in[11]:18 0.0001063101 +19 chanx_left_in[11]:19 0.0020958 +20 chanx_left_in[11]:20 0.0020958 +21 chanx_left_in[11]:21 0.0001551764 +22 chanx_left_in[11]:22 0.0001551764 +23 chanx_left_in[11]:23 0.001143762 +24 chanx_left_in[11]:10 chany_top_in[8]:19 0.001388901 +25 chanx_left_in[11]:9 chany_top_in[8]:20 0.001388901 +26 chanx_left_in[11]:19 chany_top_in[13]:28 0.000463892 +27 chanx_left_in[11]:19 chany_top_in[13]:29 0.000127723 +28 chanx_left_in[11]:20 chany_top_in[13]:12 0.000463892 +29 chanx_left_in[11]:20 chany_top_in[13]:28 0.000127723 +30 chanx_left_in[11] chanx_left_in[3] 0.0002409872 +31 chanx_left_in[11]:19 chanx_left_in[3]:10 0.000442068 +32 chanx_left_in[11]:20 chanx_left_in[3] 0.000442068 +33 chanx_left_in[11]:23 chanx_left_in[3]:10 0.0002409872 +34 chanx_left_in[11]:19 chanx_left_in[8]:7 0.0001397534 +35 chanx_left_in[11]:19 chanx_left_in[8]:12 0.0001268256 +36 chanx_left_in[11]:20 chanx_left_in[8]:12 0.0001397534 +37 chanx_left_in[11]:20 chanx_left_in[8]:13 0.0001268256 +38 chanx_left_in[11] chanx_left_in[19] 0.0004204961 +39 chanx_left_in[11]:23 chanx_left_in[19]:22 0.0004204961 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:23 0.004128166 +1 chanx_left_in[11]:18 chanx_left_in[11]:17 0.0045 +2 chanx_left_in[11]:18 chanx_left_in[11]:15 0.001214286 +3 chanx_left_in[11]:19 chanx_left_in[11]:18 0.00341 +4 chanx_left_in[11]:20 chanx_left_in[11]:19 0.006769958 +5 chanx_left_in[11]:21 chanx_left_in[11]:20 0.00341 +6 chanx_left_in[11]:23 chanx_left_in[11]:22 0.00341 +7 chanx_left_in[11]:22 chanx_left_in[11]:21 0.00031725 +8 chanx_left_in[11]:17 chanx_left_in[11]:16 0.002234375 +9 chanx_left_in[11]:16 mux_bottom_track_9\/mux_l2_in_2_:A0 0.152 +10 chanx_left_in[11]:13 chanx_left_in[11]:12 0.00341 +11 chanx_left_in[11]:12 chanx_left_in[11]:11 0.0002118917 +12 chanx_left_in[11]:11 chanx_left_in[11]:10 0.00341 +13 chanx_left_in[11]:10 chanx_left_in[11]:9 0.005324316 +14 chanx_left_in[11]:8 chanx_left_in[11]:7 0.00341 +15 chanx_left_in[11]:8 chanx_left_in[11]:3 0.0001039141 +16 chanx_left_in[11]:9 chanx_left_in[11]:8 0.00341 +17 chanx_left_in[11]:7 chanx_left_in[11]:6 0.002640625 +18 chanx_left_in[11]:5 chanx_left_in[11]:4 0.0005915179 +19 chanx_left_in[11]:6 chanx_left_in[11]:5 0.0045 +20 chanx_left_in[11]:4 mux_top_track_8\/mux_l2_in_2_:A0 0.152 +21 chanx_left_in[11]:15 chanx_left_in[11]:14 0.0004107143 +22 chanx_left_in[11]:14 chanx_left_in[11]:13 0.007841518 + +*END + +*D_NET left_top_grid_pin_44_[0] 0.01069197 //LENGTH 78.395 LUMPCC 0.002220512 DR + +*CONN +*P left_top_grid_pin_44_[0] I *L 0.29796 *C 4.140 102.070 +*I mux_left_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 14.820 90.780 +*I mux_left_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 16.100 77.860 +*I mux_left_track_13\/mux_l2_in_1_:A1 I *L 0.00198 *C 26.780 50.660 +*N left_top_grid_pin_44_[0]:4 *C 26.680 50.660 +*N left_top_grid_pin_44_[0]:5 *C 26.680 50.660 +*N left_top_grid_pin_44_[0]:6 *C 26.680 51.000 +*N left_top_grid_pin_44_[0]:7 *C 26.673 51.000 +*N left_top_grid_pin_44_[0]:8 *C 15.660 51.000 +*N left_top_grid_pin_44_[0]:9 *C 15.640 51.008 +*N left_top_grid_pin_44_[0]:10 *C 16.100 77.860 +*N left_top_grid_pin_44_[0]:11 *C 16.100 77.860 +*N left_top_grid_pin_44_[0]:12 *C 16.100 78.200 +*N left_top_grid_pin_44_[0]:13 *C 16.098 78.200 +*N left_top_grid_pin_44_[0]:14 *C 15.655 78.200 +*N left_top_grid_pin_44_[0]:15 *C 15.640 78.200 +*N left_top_grid_pin_44_[0]:16 *C 15.640 91.113 +*N left_top_grid_pin_44_[0]:17 *C 15.620 91.120 +*N left_top_grid_pin_44_[0]:18 *C 14.783 90.780 +*N left_top_grid_pin_44_[0]:19 *C 13.385 90.780 +*N left_top_grid_pin_44_[0]:20 *C 13.340 90.780 +*N left_top_grid_pin_44_[0]:21 *C 13.340 91.120 +*N left_top_grid_pin_44_[0]:22 *C 13.340 91.120 +*N left_top_grid_pin_44_[0]:23 *C 4.147 91.120 +*N left_top_grid_pin_44_[0]:24 *C 4.140 91.178 + +*CAP +0 left_top_grid_pin_44_[0] 0.0004926607 +1 mux_left_track_1\/mux_l1_in_2_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_2_:A1 1e-06 +3 mux_left_track_13\/mux_l2_in_1_:A1 1e-06 +4 left_top_grid_pin_44_[0]:4 3.161559e-05 +5 left_top_grid_pin_44_[0]:5 5.009506e-05 +6 left_top_grid_pin_44_[0]:6 5.382732e-05 +7 left_top_grid_pin_44_[0]:7 0.0005920209 +8 left_top_grid_pin_44_[0]:8 0.0005920209 +9 left_top_grid_pin_44_[0]:9 0.001417422 +10 left_top_grid_pin_44_[0]:10 3.577716e-05 +11 left_top_grid_pin_44_[0]:11 6.350401e-05 +12 left_top_grid_pin_44_[0]:12 6.770062e-05 +13 left_top_grid_pin_44_[0]:13 0.0001092201 +14 left_top_grid_pin_44_[0]:14 0.0001092201 +15 left_top_grid_pin_44_[0]:15 0.002128959 +16 left_top_grid_pin_44_[0]:16 0.0007115373 +17 left_top_grid_pin_44_[0]:17 9.202349e-05 +18 left_top_grid_pin_44_[0]:18 0.0001258619 +19 left_top_grid_pin_44_[0]:19 0.0001258619 +20 left_top_grid_pin_44_[0]:20 6.262373e-05 +21 left_top_grid_pin_44_[0]:21 6.685257e-05 +22 left_top_grid_pin_44_[0]:22 0.000569507 +23 left_top_grid_pin_44_[0]:23 0.0004774835 +24 left_top_grid_pin_44_[0]:24 0.0004926607 +25 left_top_grid_pin_44_[0]:15 chanx_left_in[0]:8 9.289412e-06 +26 left_top_grid_pin_44_[0]:15 chanx_left_in[0]:20 0.0002341967 +27 left_top_grid_pin_44_[0]:16 chanx_left_in[0]:8 2.497058e-05 +28 left_top_grid_pin_44_[0]:8 chanx_left_in[0]:18 9.201544e-05 +29 left_top_grid_pin_44_[0]:9 chanx_left_in[0]:19 0.0002092261 +30 left_top_grid_pin_44_[0]:9 chanx_left_in[0]:20 9.289412e-06 +31 left_top_grid_pin_44_[0]:7 chanx_left_in[0]:17 9.201544e-05 +32 left_top_grid_pin_44_[0]:17 chanx_left_in[13]:15 0.0001384621 +33 left_top_grid_pin_44_[0]:22 chanx_left_in[13]:15 0.0004798095 +34 left_top_grid_pin_44_[0]:22 chanx_left_in[13]:16 0.0001384621 +35 left_top_grid_pin_44_[0]:22 chanx_left_in[13]:19 5.456313e-07 +36 left_top_grid_pin_44_[0]:23 chanx_left_in[13] 5.456313e-07 +37 left_top_grid_pin_44_[0]:23 chanx_left_in[13]:16 0.0004798095 +38 left_top_grid_pin_44_[0] ropt_net_145:3 5.692972e-05 +39 left_top_grid_pin_44_[0]:22 ropt_net_145:5 8.28269e-06 +40 left_top_grid_pin_44_[0]:24 ropt_net_145:4 5.692972e-05 +41 left_top_grid_pin_44_[0]:23 ropt_net_145:4 8.28269e-06 +42 left_top_grid_pin_44_[0] ropt_net_184:5 9.072469e-05 +43 left_top_grid_pin_44_[0]:24 ropt_net_184:4 9.072469e-05 + +*RES +0 left_top_grid_pin_44_[0] left_top_grid_pin_44_[0]:24 0.009725447 +1 left_top_grid_pin_44_[0]:10 mux_left_track_5\/mux_l1_in_2_:A1 0.152 +2 left_top_grid_pin_44_[0]:11 left_top_grid_pin_44_[0]:10 0.0045 +3 left_top_grid_pin_44_[0]:12 left_top_grid_pin_44_[0]:11 0.0001634615 +4 left_top_grid_pin_44_[0]:13 left_top_grid_pin_44_[0]:12 0.00341 +5 left_top_grid_pin_44_[0]:14 left_top_grid_pin_44_[0]:13 6.499219e-05 +6 left_top_grid_pin_44_[0]:15 left_top_grid_pin_44_[0]:14 0.00341 +7 left_top_grid_pin_44_[0]:15 left_top_grid_pin_44_[0]:9 0.004260158 +8 left_top_grid_pin_44_[0]:17 left_top_grid_pin_44_[0]:16 0.00341 +9 left_top_grid_pin_44_[0]:16 left_top_grid_pin_44_[0]:15 0.002022958 +10 left_top_grid_pin_44_[0]:8 left_top_grid_pin_44_[0]:7 0.001725292 +11 left_top_grid_pin_44_[0]:9 left_top_grid_pin_44_[0]:8 0.00341 +12 left_top_grid_pin_44_[0]:6 left_top_grid_pin_44_[0]:5 0.0001634616 +13 left_top_grid_pin_44_[0]:7 left_top_grid_pin_44_[0]:6 0.00341 +14 left_top_grid_pin_44_[0]:4 mux_left_track_13\/mux_l2_in_1_:A1 0.152 +15 left_top_grid_pin_44_[0]:5 left_top_grid_pin_44_[0]:4 0.0045 +16 left_top_grid_pin_44_[0]:21 left_top_grid_pin_44_[0]:20 0.0001634615 +17 left_top_grid_pin_44_[0]:22 left_top_grid_pin_44_[0]:21 0.00341 +18 left_top_grid_pin_44_[0]:22 left_top_grid_pin_44_[0]:17 0.0003572 +19 left_top_grid_pin_44_[0]:19 left_top_grid_pin_44_[0]:18 0.001247768 +20 left_top_grid_pin_44_[0]:20 left_top_grid_pin_44_[0]:19 0.0045 +21 left_top_grid_pin_44_[0]:18 mux_left_track_1\/mux_l1_in_2_:A1 0.152 +22 left_top_grid_pin_44_[0]:24 left_top_grid_pin_44_[0]:23 0.00341 +23 left_top_grid_pin_44_[0]:23 left_top_grid_pin_44_[0]:22 0.001440158 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[3] 0.00127361 //LENGTH 8.920 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 49.525 14.960 +*I mem_bottom_track_5\/FTB_7__39:A I *L 0.001746 *C 46.460 9.520 +*I mux_bottom_track_5\/mux_l4_in_0_:S I *L 0.00357 *C 45.880 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:3 *C 47.740 12.205 +*N mux_tree_tapbuf_size14_1_sram[3]:4 *C 45.880 12.415 +*N mux_tree_tapbuf_size14_1_sram[3]:5 *C 46.422 9.520 +*N mux_tree_tapbuf_size14_1_sram[3]:6 *C 46.045 9.520 +*N mux_tree_tapbuf_size14_1_sram[3]:7 *C 46.000 9.565 +*N mux_tree_tapbuf_size14_1_sram[3]:8 *C 46.000 12.875 +*N mux_tree_tapbuf_size14_1_sram[3]:9 *C 45.880 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:10 *C 45.880 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:11 *C 45.880 13.260 +*N mux_tree_tapbuf_size14_1_sram[3]:12 *C 47.740 13.260 +*N mux_tree_tapbuf_size14_1_sram[3]:13 *C 47.740 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:14 *C 47.778 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:15 *C 49.175 12.920 +*N mux_tree_tapbuf_size14_1_sram[3]:16 *C 49.220 12.965 +*N mux_tree_tapbuf_size14_1_sram[3]:17 *C 49.220 14.915 +*N mux_tree_tapbuf_size14_1_sram[3]:18 *C 49.220 14.960 +*N mux_tree_tapbuf_size14_1_sram[3]:19 *C 49.525 14.960 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_5\/FTB_7__39:A 1e-06 +2 mux_bottom_track_5\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size14_1_sram[3]:3 1e-06 +4 mux_tree_tapbuf_size14_1_sram[3]:4 1e-06 +5 mux_tree_tapbuf_size14_1_sram[3]:5 4.589331e-05 +6 mux_tree_tapbuf_size14_1_sram[3]:6 4.589331e-05 +7 mux_tree_tapbuf_size14_1_sram[3]:7 0.0002308804 +8 mux_tree_tapbuf_size14_1_sram[3]:8 0.0002308804 +9 mux_tree_tapbuf_size14_1_sram[3]:9 3.209124e-05 +10 mux_tree_tapbuf_size14_1_sram[3]:10 1e-06 +11 mux_tree_tapbuf_size14_1_sram[3]:11 1e-06 +12 mux_tree_tapbuf_size14_1_sram[3]:12 1e-06 +13 mux_tree_tapbuf_size14_1_sram[3]:13 1e-06 +14 mux_tree_tapbuf_size14_1_sram[3]:14 0.0001433278 +15 mux_tree_tapbuf_size14_1_sram[3]:15 0.0001433278 +16 mux_tree_tapbuf_size14_1_sram[3]:16 0.0001333142 +17 mux_tree_tapbuf_size14_1_sram[3]:17 0.0001333142 +18 mux_tree_tapbuf_size14_1_sram[3]:18 6.299932e-05 +19 mux_tree_tapbuf_size14_1_sram[3]:19 6.268806e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size14_1_sram[3]:19 0.152 +1 mux_tree_tapbuf_size14_1_sram[3]:9 mux_tree_tapbuf_size14_1_sram[3]:8 0.0045 +2 mux_tree_tapbuf_size14_1_sram[3]:8 mux_tree_tapbuf_size14_1_sram[3]:7 0.002955357 +3 mux_tree_tapbuf_size14_1_sram[3]:6 mux_tree_tapbuf_size14_1_sram[3]:5 0.0003370536 +4 mux_tree_tapbuf_size14_1_sram[3]:7 mux_tree_tapbuf_size14_1_sram[3]:6 0.0045 +5 mux_tree_tapbuf_size14_1_sram[3]:5 mem_bottom_track_5\/FTB_7__39:A 0.152 +6 mux_tree_tapbuf_size14_1_sram[3]:14 mux_tree_tapbuf_size14_1_sram[3]:13 0.152 +7 mux_tree_tapbuf_size14_1_sram[3]:15 mux_tree_tapbuf_size14_1_sram[3]:14 0.001247768 +8 mux_tree_tapbuf_size14_1_sram[3]:16 mux_tree_tapbuf_size14_1_sram[3]:15 0.0045 +9 mux_tree_tapbuf_size14_1_sram[3]:18 mux_tree_tapbuf_size14_1_sram[3]:17 0.0045 +10 mux_tree_tapbuf_size14_1_sram[3]:17 mux_tree_tapbuf_size14_1_sram[3]:16 0.001741071 +11 mux_tree_tapbuf_size14_1_sram[3]:19 mux_tree_tapbuf_size14_1_sram[3]:18 0.0001331522 +12 mux_tree_tapbuf_size14_1_sram[3]:13 mux_tree_tapbuf_size14_1_sram[3]:12 0.0244 +13 mux_tree_tapbuf_size14_1_sram[3]:13 mux_tree_tapbuf_size14_1_sram[3]:3 0.05131176 +14 mux_tree_tapbuf_size14_1_sram[3]:11 mux_tree_tapbuf_size14_1_sram[3]:10 0.02442153 +15 mux_tree_tapbuf_size14_1_sram[3]:12 mux_tree_tapbuf_size14_1_sram[3]:11 0.1334824 +16 mux_tree_tapbuf_size14_1_sram[3]:10 mux_tree_tapbuf_size14_1_sram[3]:9 0.152 +17 mux_tree_tapbuf_size14_1_sram[3]:10 mux_tree_tapbuf_size14_1_sram[3]:4 0.03621965 +18 mux_tree_tapbuf_size14_1_sram[3]:10 mux_bottom_track_5\/mux_l4_in_0_:S 1e-05 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[1] 0.002775571 //LENGTH 21.275 LUMPCC 0.0003142867 DR + +*CONN +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 52.550 82.280 +*I mem_left_track_23\/FTB_26__58:A I *L 0.001746 *C 41.400 77.520 +*I mux_left_track_23\/mux_l2_in_0_:S I *L 0.00357 *C 39.660 82.960 +*N mux_tree_tapbuf_size3_3_sram[1]:3 *C 39.698 82.960 +*N mux_tree_tapbuf_size3_3_sram[1]:4 *C 42.275 82.960 +*N mux_tree_tapbuf_size3_3_sram[1]:5 *C 42.320 82.915 +*N mux_tree_tapbuf_size3_3_sram[1]:6 *C 41.400 77.520 +*N mux_tree_tapbuf_size3_3_sram[1]:7 *C 41.400 77.180 +*N mux_tree_tapbuf_size3_3_sram[1]:8 *C 42.275 77.180 +*N mux_tree_tapbuf_size3_3_sram[1]:9 *C 42.320 77.225 +*N mux_tree_tapbuf_size3_3_sram[1]:10 *C 42.320 82.280 +*N mux_tree_tapbuf_size3_3_sram[1]:11 *C 42.365 82.280 +*N mux_tree_tapbuf_size3_3_sram[1]:12 *C 52.513 82.280 + +*CAP +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_23\/FTB_26__58:A 1e-06 +2 mux_left_track_23\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_3_sram[1]:3 0.0001210855 +4 mux_tree_tapbuf_size3_3_sram[1]:4 0.0001210855 +5 mux_tree_tapbuf_size3_3_sram[1]:5 3.497528e-05 +6 mux_tree_tapbuf_size3_3_sram[1]:6 6.095695e-05 +7 mux_tree_tapbuf_size3_3_sram[1]:7 0.0001061109 +8 mux_tree_tapbuf_size3_3_sram[1]:8 7.632507e-05 +9 mux_tree_tapbuf_size3_3_sram[1]:9 0.0002286982 +10 mux_tree_tapbuf_size3_3_sram[1]:10 0.0002956722 +11 mux_tree_tapbuf_size3_3_sram[1]:11 0.0007066873 +12 mux_tree_tapbuf_size3_3_sram[1]:12 0.0007066873 +13 mux_tree_tapbuf_size3_3_sram[1]:12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.905079e-06 +14 mux_tree_tapbuf_size3_3_sram[1]:11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.905079e-06 +15 mux_tree_tapbuf_size3_3_sram[1]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.876962e-05 +16 mux_tree_tapbuf_size3_3_sram[1]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.006045e-05 +17 mux_tree_tapbuf_size3_3_sram[1]:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.876962e-05 +18 mux_tree_tapbuf_size3_3_sram[1]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.240822e-05 +19 mux_tree_tapbuf_size3_3_sram[1]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.006045e-05 +20 mux_tree_tapbuf_size3_3_sram[1]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.240822e-05 + +*RES +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_3_sram[1]:12 0.152 +1 mux_tree_tapbuf_size3_3_sram[1]:12 mux_tree_tapbuf_size3_3_sram[1]:11 0.009060267 +2 mux_tree_tapbuf_size3_3_sram[1]:11 mux_tree_tapbuf_size3_3_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size3_3_sram[1]:10 mux_tree_tapbuf_size3_3_sram[1]:9 0.004513393 +4 mux_tree_tapbuf_size3_3_sram[1]:10 mux_tree_tapbuf_size3_3_sram[1]:5 0.0005669643 +5 mux_tree_tapbuf_size3_3_sram[1]:6 mem_left_track_23\/FTB_26__58:A 0.152 +6 mux_tree_tapbuf_size3_3_sram[1]:8 mux_tree_tapbuf_size3_3_sram[1]:7 0.00078125 +7 mux_tree_tapbuf_size3_3_sram[1]:9 mux_tree_tapbuf_size3_3_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size3_3_sram[1]:4 mux_tree_tapbuf_size3_3_sram[1]:3 0.002301339 +9 mux_tree_tapbuf_size3_3_sram[1]:5 mux_tree_tapbuf_size3_3_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_3_sram[1]:3 mux_left_track_23\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size3_3_sram[1]:7 mux_tree_tapbuf_size3_3_sram[1]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[2] 0.001446507 //LENGTH 11.205 LUMPCC 0.0001307674 DR + +*CONN +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 81.725 49.980 +*I mux_left_track_11\/mux_l3_in_0_:S I *L 0.00357 *C 82.440 47.310 +*I mem_left_track_11\/FTB_20__52:A I *L 0.001746 *C 86.020 44.880 +*N mux_tree_tapbuf_size4_1_sram[2]:3 *C 85.983 44.880 +*N mux_tree_tapbuf_size4_1_sram[2]:4 *C 84.685 44.880 +*N mux_tree_tapbuf_size4_1_sram[2]:5 *C 84.640 44.925 +*N mux_tree_tapbuf_size4_1_sram[2]:6 *C 84.640 46.875 +*N mux_tree_tapbuf_size4_1_sram[2]:7 *C 84.595 46.920 +*N mux_tree_tapbuf_size4_1_sram[2]:8 *C 82.440 46.920 +*N mux_tree_tapbuf_size4_1_sram[2]:9 *C 82.440 47.310 +*N mux_tree_tapbuf_size4_1_sram[2]:10 *C 82.340 47.600 +*N mux_tree_tapbuf_size4_1_sram[2]:11 *C 82.340 47.645 +*N mux_tree_tapbuf_size4_1_sram[2]:12 *C 82.340 49.935 +*N mux_tree_tapbuf_size4_1_sram[2]:13 *C 82.295 49.980 +*N mux_tree_tapbuf_size4_1_sram[2]:14 *C 81.763 49.980 + +*CAP +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_11\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_11\/FTB_20__52:A 1e-06 +3 mux_tree_tapbuf_size4_1_sram[2]:3 0.0001000314 +4 mux_tree_tapbuf_size4_1_sram[2]:4 0.0001000314 +5 mux_tree_tapbuf_size4_1_sram[2]:5 0.0001302942 +6 mux_tree_tapbuf_size4_1_sram[2]:6 0.0001302942 +7 mux_tree_tapbuf_size4_1_sram[2]:7 0.0001165918 +8 mux_tree_tapbuf_size4_1_sram[2]:8 0.0001496799 +9 mux_tree_tapbuf_size4_1_sram[2]:9 9.881931e-05 +10 mux_tree_tapbuf_size4_1_sram[2]:10 7.05183e-05 +11 mux_tree_tapbuf_size4_1_sram[2]:11 0.0001437395 +12 mux_tree_tapbuf_size4_1_sram[2]:12 0.0001437395 +13 mux_tree_tapbuf_size4_1_sram[2]:13 6.450019e-05 +14 mux_tree_tapbuf_size4_1_sram[2]:14 6.450019e-05 +15 mux_tree_tapbuf_size4_1_sram[2]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.538369e-05 +16 mux_tree_tapbuf_size4_1_sram[2]:8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.538369e-05 + +*RES +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_1_sram[2]:14 0.152 +1 mux_tree_tapbuf_size4_1_sram[2]:9 mux_left_track_11\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_1_sram[2]:9 mux_tree_tapbuf_size4_1_sram[2]:8 0.0003482143 +3 mux_tree_tapbuf_size4_1_sram[2]:7 mux_tree_tapbuf_size4_1_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size4_1_sram[2]:6 mux_tree_tapbuf_size4_1_sram[2]:5 0.001741072 +5 mux_tree_tapbuf_size4_1_sram[2]:4 mux_tree_tapbuf_size4_1_sram[2]:3 0.001158482 +6 mux_tree_tapbuf_size4_1_sram[2]:5 mux_tree_tapbuf_size4_1_sram[2]:4 0.0045 +7 mux_tree_tapbuf_size4_1_sram[2]:3 mem_left_track_11\/FTB_20__52:A 0.152 +8 mux_tree_tapbuf_size4_1_sram[2]:14 mux_tree_tapbuf_size4_1_sram[2]:13 0.0004754465 +9 mux_tree_tapbuf_size4_1_sram[2]:13 mux_tree_tapbuf_size4_1_sram[2]:12 0.0045 +10 mux_tree_tapbuf_size4_1_sram[2]:12 mux_tree_tapbuf_size4_1_sram[2]:11 0.002044643 +11 mux_tree_tapbuf_size4_1_sram[2]:10 mux_tree_tapbuf_size4_1_sram[2]:9 0.0001686047 +12 mux_tree_tapbuf_size4_1_sram[2]:11 mux_tree_tapbuf_size4_1_sram[2]:10 0.0045 +13 mux_tree_tapbuf_size4_1_sram[2]:8 mux_tree_tapbuf_size4_1_sram[2]:7 0.001924107 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.00157396 //LENGTH 13.730 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 77.125 80.240 +*I mem_top_track_32\/FTB_15__47:A I *L 0.001746 *C 81.880 74.800 +*I mux_top_track_32\/mux_l3_in_0_:S I *L 0.00357 *C 81.780 79.950 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 81.780 79.950 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 81.918 74.800 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 82.755 74.800 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 82.800 74.845 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 82.800 79.515 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 82.755 79.560 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 81.780 79.560 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 80.500 79.560 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 80.500 79.900 +*N mux_tree_tapbuf_size6_0_sram[2]:12 *C 77.280 79.900 +*N mux_tree_tapbuf_size6_0_sram[2]:13 *C 77.125 80.240 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_32\/FTB_15__47:A 1e-06 +2 mux_top_track_32\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 5.73055e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 6.903562e-05 +5 mux_tree_tapbuf_size6_0_sram[2]:5 6.903562e-05 +6 mux_tree_tapbuf_size6_0_sram[2]:6 0.0002539623 +7 mux_tree_tapbuf_size6_0_sram[2]:7 0.0002539623 +8 mux_tree_tapbuf_size6_0_sram[2]:8 8.014599e-05 +9 mux_tree_tapbuf_size6_0_sram[2]:9 0.0001978133 +10 mux_tree_tapbuf_size6_0_sram[2]:10 0.000108368 +11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0002138834 +12 mux_tree_tapbuf_size6_0_sram[2]:12 0.0002174146 +13 mux_tree_tapbuf_size6_0_sram[2]:13 5.003334e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +2 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.004169643 +3 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0007477679 +4 mux_tree_tapbuf_size6_0_sram[2]:6 mux_tree_tapbuf_size6_0_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size6_0_sram[2]:4 mem_top_track_32\/FTB_15__47:A 0.152 +6 mux_tree_tapbuf_size6_0_sram[2]:3 mux_top_track_32\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size6_0_sram[2]:13 mux_tree_tapbuf_size6_0_sram[2]:12 0.0003035715 +8 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:11 0.002875 +9 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.0003035715 +10 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.001142857 +11 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:8 0.0008705358 +12 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:3 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[2] 0.001405245 //LENGTH 11.080 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 56.425 42.160 +*I mux_bottom_track_17\/mux_l3_in_0_:S I *L 0.00357 *C 53.260 39.440 +*I mem_bottom_track_17\/FTB_10__42:A I *L 0.001746 *C 60.720 39.440 +*N mux_tree_tapbuf_size7_2_sram[2]:3 *C 60.683 39.440 +*N mux_tree_tapbuf_size7_2_sram[2]:4 *C 53.297 39.440 +*N mux_tree_tapbuf_size7_2_sram[2]:5 *C 56.580 39.440 +*N mux_tree_tapbuf_size7_2_sram[2]:6 *C 56.580 39.485 +*N mux_tree_tapbuf_size7_2_sram[2]:7 *C 56.580 42.115 +*N mux_tree_tapbuf_size7_2_sram[2]:8 *C 56.580 42.160 +*N mux_tree_tapbuf_size7_2_sram[2]:9 *C 56.425 42.160 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_17\/FTB_10__42:A 1e-06 +3 mux_tree_tapbuf_size7_2_sram[2]:3 0.0002311761 +4 mux_tree_tapbuf_size7_2_sram[2]:4 0.0002066695 +5 mux_tree_tapbuf_size7_2_sram[2]:5 0.0004715605 +6 mux_tree_tapbuf_size7_2_sram[2]:6 0.0001961062 +7 mux_tree_tapbuf_size7_2_sram[2]:7 0.0001961062 +8 mux_tree_tapbuf_size7_2_sram[2]:8 5.269156e-05 +9 mux_tree_tapbuf_size7_2_sram[2]:9 4.793506e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_2_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_2_sram[2]:4 mux_bottom_track_17\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[2]:3 mem_bottom_track_17\/FTB_10__42:A 0.152 +3 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:4 0.002930804 +4 mux_tree_tapbuf_size7_2_sram[2]:5 mux_tree_tapbuf_size7_2_sram[2]:3 0.003662946 +5 mux_tree_tapbuf_size7_2_sram[2]:6 mux_tree_tapbuf_size7_2_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size7_2_sram[2]:8 mux_tree_tapbuf_size7_2_sram[2]:7 0.0045 +7 mux_tree_tapbuf_size7_2_sram[2]:7 mux_tree_tapbuf_size7_2_sram[2]:6 0.002348214 +8 mux_tree_tapbuf_size7_2_sram[2]:9 mux_tree_tapbuf_size7_2_sram[2]:8 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[1] 0.00344993 //LENGTH 24.275 LUMPCC 0.0008994081 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 51.825 58.480 +*I mux_left_track_7\/mux_l2_in_0_:S I *L 0.00357 *C 53.000 56.440 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 53.995 60.860 +*I mux_left_track_7\/mux_l2_in_1_:S I *L 0.00357 *C 40.380 63.920 +*N mux_tree_tapbuf_size7_6_sram[1]:4 *C 40.380 63.920 +*N mux_tree_tapbuf_size7_6_sram[1]:5 *C 40.480 63.580 +*N mux_tree_tapbuf_size7_6_sram[1]:6 *C 51.935 63.580 +*N mux_tree_tapbuf_size7_6_sram[1]:7 *C 51.980 63.535 +*N mux_tree_tapbuf_size7_6_sram[1]:8 *C 51.980 60.520 +*N mux_tree_tapbuf_size7_6_sram[1]:9 *C 53.995 60.860 +*N mux_tree_tapbuf_size7_6_sram[1]:10 *C 53.820 60.520 +*N mux_tree_tapbuf_size7_6_sram[1]:11 *C 52.485 60.520 +*N mux_tree_tapbuf_size7_6_sram[1]:12 *C 52.440 60.475 +*N mux_tree_tapbuf_size7_6_sram[1]:13 *C 52.963 56.440 +*N mux_tree_tapbuf_size7_6_sram[1]:14 *C 52.485 56.440 +*N mux_tree_tapbuf_size7_6_sram[1]:15 *C 52.440 56.485 +*N mux_tree_tapbuf_size7_6_sram[1]:16 *C 52.440 58.480 +*N mux_tree_tapbuf_size7_6_sram[1]:17 *C 52.395 58.480 +*N mux_tree_tapbuf_size7_6_sram[1]:18 *C 51.863 58.480 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_7\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_7\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size7_6_sram[1]:4 5.895081e-05 +5 mux_tree_tapbuf_size7_6_sram[1]:5 0.0004873271 +6 mux_tree_tapbuf_size7_6_sram[1]:6 0.0004584242 +7 mux_tree_tapbuf_size7_6_sram[1]:7 0.0001974432 +8 mux_tree_tapbuf_size7_6_sram[1]:8 0.0002320175 +9 mux_tree_tapbuf_size7_6_sram[1]:9 5.653712e-05 +10 mux_tree_tapbuf_size7_6_sram[1]:10 0.0001432593 +11 mux_tree_tapbuf_size7_6_sram[1]:11 0.0001167248 +12 mux_tree_tapbuf_size7_6_sram[1]:12 0.0001685594 +13 mux_tree_tapbuf_size7_6_sram[1]:13 6.060582e-05 +14 mux_tree_tapbuf_size7_6_sram[1]:14 6.060582e-05 +15 mux_tree_tapbuf_size7_6_sram[1]:15 0.0001167049 +16 mux_tree_tapbuf_size7_6_sram[1]:16 0.0002816295 +17 mux_tree_tapbuf_size7_6_sram[1]:17 5.386655e-05 +18 mux_tree_tapbuf_size7_6_sram[1]:18 5.386655e-05 +19 mux_tree_tapbuf_size7_6_sram[1]:6 mux_tree_tapbuf_size3_4_sram[1]:8 0.0001821992 +20 mux_tree_tapbuf_size7_6_sram[1]:5 mux_tree_tapbuf_size3_4_sram[1]:7 0.0001821992 +21 mux_tree_tapbuf_size7_6_sram[1]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.99964e-07 +22 mux_tree_tapbuf_size7_6_sram[1]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.998571e-05 +23 mux_tree_tapbuf_size7_6_sram[1]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.99964e-07 +24 mux_tree_tapbuf_size7_6_sram[1]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.998571e-05 +25 mux_tree_tapbuf_size7_6_sram[1]:6 mem_left_track_25/net_net_84:10 0.0001973192 +26 mux_tree_tapbuf_size7_6_sram[1]:5 mem_left_track_25/net_net_84:9 0.0001973192 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_6_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_6_sram[1]:6 mux_tree_tapbuf_size7_6_sram[1]:5 0.01022768 +2 mux_tree_tapbuf_size7_6_sram[1]:7 mux_tree_tapbuf_size7_6_sram[1]:6 0.0045 +3 mux_tree_tapbuf_size7_6_sram[1]:4 mux_left_track_7\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size7_6_sram[1]:11 mux_tree_tapbuf_size7_6_sram[1]:10 0.001191964 +5 mux_tree_tapbuf_size7_6_sram[1]:12 mux_tree_tapbuf_size7_6_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size7_6_sram[1]:12 mux_tree_tapbuf_size7_6_sram[1]:8 0.0004107143 +7 mux_tree_tapbuf_size7_6_sram[1]:9 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size7_6_sram[1]:17 mux_tree_tapbuf_size7_6_sram[1]:16 0.0045 +9 mux_tree_tapbuf_size7_6_sram[1]:16 mux_tree_tapbuf_size7_6_sram[1]:15 0.00178125 +10 mux_tree_tapbuf_size7_6_sram[1]:16 mux_tree_tapbuf_size7_6_sram[1]:12 0.00178125 +11 mux_tree_tapbuf_size7_6_sram[1]:18 mux_tree_tapbuf_size7_6_sram[1]:17 0.0004754465 +12 mux_tree_tapbuf_size7_6_sram[1]:14 mux_tree_tapbuf_size7_6_sram[1]:13 0.0004263393 +13 mux_tree_tapbuf_size7_6_sram[1]:15 mux_tree_tapbuf_size7_6_sram[1]:14 0.0045 +14 mux_tree_tapbuf_size7_6_sram[1]:13 mux_left_track_7\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size7_6_sram[1]:5 mux_tree_tapbuf_size7_6_sram[1]:4 0.0003035715 +16 mux_tree_tapbuf_size7_6_sram[1]:10 mux_tree_tapbuf_size7_6_sram[1]:9 0.0003035715 +17 mux_tree_tapbuf_size7_6_sram[1]:8 mux_tree_tapbuf_size7_6_sram[1]:7 0.002691965 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[2] 0.003194451 //LENGTH 26.390 LUMPCC 0.0001976052 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 69.305 37.060 +*I mux_bottom_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 73.500 31.280 +*I mux_bottom_track_9\/mux_l3_in_1_:S I *L 0.00357 *C 79.480 39.440 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 76.075 33.660 +*N mux_tree_tapbuf_size8_2_sram[2]:4 *C 76.038 33.660 +*N mux_tree_tapbuf_size8_2_sram[2]:5 *C 75.440 33.660 +*N mux_tree_tapbuf_size8_2_sram[2]:6 *C 79.443 39.440 +*N mux_tree_tapbuf_size8_2_sram[2]:7 *C 77.325 39.440 +*N mux_tree_tapbuf_size8_2_sram[2]:8 *C 77.280 39.395 +*N mux_tree_tapbuf_size8_2_sram[2]:9 *C 77.280 33.365 +*N mux_tree_tapbuf_size8_2_sram[2]:10 *C 77.235 33.320 +*N mux_tree_tapbuf_size8_2_sram[2]:11 *C 75.440 33.320 +*N mux_tree_tapbuf_size8_2_sram[2]:12 *C 73.485 31.280 +*N mux_tree_tapbuf_size8_2_sram[2]:13 *C 73.163 31.280 +*N mux_tree_tapbuf_size8_2_sram[2]:14 *C 73.140 31.325 +*N mux_tree_tapbuf_size8_2_sram[2]:15 *C 73.140 33.275 +*N mux_tree_tapbuf_size8_2_sram[2]:16 *C 73.140 33.320 +*N mux_tree_tapbuf_size8_2_sram[2]:17 *C 73.140 34.340 +*N mux_tree_tapbuf_size8_2_sram[2]:18 *C 69.965 34.340 +*N mux_tree_tapbuf_size8_2_sram[2]:19 *C 69.920 34.385 +*N mux_tree_tapbuf_size8_2_sram[2]:20 *C 69.920 37.015 +*N mux_tree_tapbuf_size8_2_sram[2]:21 *C 69.875 37.060 +*N mux_tree_tapbuf_size8_2_sram[2]:22 *C 69.343 37.060 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:S 1e-06 +2 mux_bottom_track_9\/mux_l3_in_1_:S 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_2_sram[2]:4 6.314741e-05 +5 mux_tree_tapbuf_size8_2_sram[2]:5 8.873217e-05 +6 mux_tree_tapbuf_size8_2_sram[2]:6 0.0001074423 +7 mux_tree_tapbuf_size8_2_sram[2]:7 0.0001074423 +8 mux_tree_tapbuf_size8_2_sram[2]:8 0.0003350972 +9 mux_tree_tapbuf_size8_2_sram[2]:9 0.0003350972 +10 mux_tree_tapbuf_size8_2_sram[2]:10 0.0001061203 +11 mux_tree_tapbuf_size8_2_sram[2]:11 0.0002978159 +12 mux_tree_tapbuf_size8_2_sram[2]:12 6.209381e-05 +13 mux_tree_tapbuf_size8_2_sram[2]:13 6.209381e-05 +14 mux_tree_tapbuf_size8_2_sram[2]:14 0.0001473801 +15 mux_tree_tapbuf_size8_2_sram[2]:15 0.0001473801 +16 mux_tree_tapbuf_size8_2_sram[2]:16 0.0002292361 +17 mux_tree_tapbuf_size8_2_sram[2]:17 0.0002697117 +18 mux_tree_tapbuf_size8_2_sram[2]:18 0.0002065865 +19 mux_tree_tapbuf_size8_2_sram[2]:19 0.0001607498 +20 mux_tree_tapbuf_size8_2_sram[2]:20 0.0001607498 +21 mux_tree_tapbuf_size8_2_sram[2]:21 5.298451e-05 +22 mux_tree_tapbuf_size8_2_sram[2]:22 5.298451e-05 +23 mux_tree_tapbuf_size8_2_sram[2]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.774183e-05 +24 mux_tree_tapbuf_size8_2_sram[2]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.774183e-05 +25 mux_tree_tapbuf_size8_2_sram[2]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.106078e-05 +26 mux_tree_tapbuf_size8_2_sram[2]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.106078e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_2_sram[2]:22 0.152 +1 mux_tree_tapbuf_size8_2_sram[2]:12 mux_bottom_track_9\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_2_sram[2]:13 mux_tree_tapbuf_size8_2_sram[2]:12 0.0001752718 +3 mux_tree_tapbuf_size8_2_sram[2]:14 mux_tree_tapbuf_size8_2_sram[2]:13 0.0045 +4 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:15 0.0045 +5 mux_tree_tapbuf_size8_2_sram[2]:16 mux_tree_tapbuf_size8_2_sram[2]:11 0.002053572 +6 mux_tree_tapbuf_size8_2_sram[2]:15 mux_tree_tapbuf_size8_2_sram[2]:14 0.001741071 +7 mux_tree_tapbuf_size8_2_sram[2]:18 mux_tree_tapbuf_size8_2_sram[2]:17 0.002834822 +8 mux_tree_tapbuf_size8_2_sram[2]:19 mux_tree_tapbuf_size8_2_sram[2]:18 0.0045 +9 mux_tree_tapbuf_size8_2_sram[2]:21 mux_tree_tapbuf_size8_2_sram[2]:20 0.0045 +10 mux_tree_tapbuf_size8_2_sram[2]:20 mux_tree_tapbuf_size8_2_sram[2]:19 0.002348214 +11 mux_tree_tapbuf_size8_2_sram[2]:22 mux_tree_tapbuf_size8_2_sram[2]:21 0.0004754465 +12 mux_tree_tapbuf_size8_2_sram[2]:6 mux_bottom_track_9\/mux_l3_in_1_:S 0.152 +13 mux_tree_tapbuf_size8_2_sram[2]:7 mux_tree_tapbuf_size8_2_sram[2]:6 0.001890625 +14 mux_tree_tapbuf_size8_2_sram[2]:8 mux_tree_tapbuf_size8_2_sram[2]:7 0.0045 +15 mux_tree_tapbuf_size8_2_sram[2]:10 mux_tree_tapbuf_size8_2_sram[2]:9 0.0045 +16 mux_tree_tapbuf_size8_2_sram[2]:9 mux_tree_tapbuf_size8_2_sram[2]:8 0.005383929 +17 mux_tree_tapbuf_size8_2_sram[2]:4 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +18 mux_tree_tapbuf_size8_2_sram[2]:17 mux_tree_tapbuf_size8_2_sram[2]:16 0.0009107143 +19 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:10 0.001602679 +20 mux_tree_tapbuf_size8_2_sram[2]:11 mux_tree_tapbuf_size8_2_sram[2]:5 0.0003035715 +21 mux_tree_tapbuf_size8_2_sram[2]:5 mux_tree_tapbuf_size8_2_sram[2]:4 0.0005334822 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005713332 //LENGTH 37.355 LUMPCC 0.0008001541 DR + +*CONN +*I mux_top_track_0\/mux_l4_in_0_:X O *L 0 *C 39.385 127.160 +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 74.780 126.350 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 74.780 126.350 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 74.780 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 44.205 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 44.160 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 43.285 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 43.270 127.130 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 43.195 127.160 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 39.422 127.160 + +*CAP +0 mux_top_track_0\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 7.000352e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.002026852 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.001988868 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 8.706438e-05 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.732502e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 3.139221e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0003098363 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.0003098363 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_tree_tapbuf_size10_0_sram[0]:12 0.0001150568 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_tree_tapbuf_size10_0_sram[0]:11 2.733363e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_tree_tapbuf_size10_0_sram[0]:10 2.733363e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_tree_tapbuf_size10_0_sram[0]:13 0.0001150568 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 chany_top_out[13]:3 0.0001801369 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 chany_top_out[13]:4 0.0001801369 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 ropt_net_187:3 7.754965e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 ropt_net_187:2 7.754965e-05 + +*RES +0 mux_top_track_0\/mux_l4_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.02729911 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00019375 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.003368304 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0004196429 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0007812501 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0009127598 //LENGTH 6.785 LUMPCC 0.0002621431 DR + +*CONN +*I mux_top_track_2\/mux_l3_in_0_:X O *L 0 *C 35.245 102.340 +*I mux_top_track_2\/mux_l4_in_0_:A1 I *L 0.00198 *C 36.340 107.100 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 36.303 107.100 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 35.925 107.100 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 35.880 107.055 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 35.880 102.385 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 35.835 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 35.282 102.340 + +*CAP +0 mux_top_track_2\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.996294e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.996294e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001978573 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001978573 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.648815e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.648815e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001301241 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.47432e-07 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001301241 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.47432e-07 + +*RES +0 mux_top_track_2\/mux_l3_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004933036 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004169643 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003370536 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_2\/mux_l4_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001337823 //LENGTH 9.940 LUMPCC 0.0003490031 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_3_:X O *L 0 *C 57.785 102.340 +*I mux_top_track_4\/mux_l3_in_1_:A0 I *L 0.001631 *C 56.755 109.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 56.755 109.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 57.040 109.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 57.040 109.775 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 57.040 107.145 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 57.085 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 57.915 107.100 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 *C 57.960 107.055 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 *C 57.960 102.385 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:10 *C 57.960 102.340 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:11 *C 57.785 102.340 + +*CAP +0 mux_top_track_4\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 4.44814e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 4.869211e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 8.463821e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 8.463821e-05 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 7.271856e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 7.271856e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 0.0002290974 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 0.0002290974 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:10 6.131741e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:11 5.942066e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 chany_bottom_in[12]:12 8.162294e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 chany_bottom_in[12]:13 8.162294e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 chany_bottom_in[12]:12 1.37542e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 chany_bottom_in[12]:13 8.661547e-06 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 chany_bottom_in[12]:13 1.37542e-05 +17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 chany_bottom_in[12]:16 8.661547e-06 +18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 2.062684e-05 +19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 2.062684e-05 +20 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 4.983601e-05 +21 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.983601e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_3_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:11 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_top_track_4\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:2 0.0001548913 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.002348215 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:6 0.0007410714 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.0045 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 0.0045 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 0.004169643 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002738358 //LENGTH 23.370 LUMPCC 0.0006222792 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_6_:X O *L 0 *C 36.165 44.540 +*I mux_bottom_track_5\/mux_l2_in_3_:A1 I *L 0.00198 *C 36.800 23.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 36.800 23.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 36.800 23.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 37.260 23.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 37.260 44.495 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 37.215 44.540 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 36.203 44.540 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_6_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_3_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 3.311664e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.497594e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.000916226 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0008876548 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001110525 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001110525 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 chanx_left_in[13]:10 8.071751e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 chanx_left_in[13]:9 8.071751e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 optlc_net_137:7 9.957795e-06 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 optlc_net_137:16 8.061072e-06 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 optlc_net_137:22 0.0001489666 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 optlc_net_137:23 6.343664e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_137:16 9.957795e-06 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_137:19 0.0001489666 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_137:22 6.343664e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 optlc_net_137:23 8.061072e-06 + +*RES +0 mux_bottom_track_5\/mux_l1_in_6_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009040179 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.01878125 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_5\/mux_l2_in_3_:A1 0.152 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0004107143 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0] 0.009426205 //LENGTH 79.635 LUMPCC 0.001310036 DR + +*CONN +*I mux_top_track_24\/mux_l3_in_0_:X O *L 0 *C 45.365 90.780 +*I mux_top_track_24\/BUFT_P_117:A I *L 0.001746 *C 86.940 126.480 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 86.940 126.480 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 86.940 126.820 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 79.625 126.820 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 79.580 126.775 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 79.580 118.025 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 79.535 117.980 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 72.725 117.980 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 72.680 117.935 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 72.680 90.825 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 72.635 90.780 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 45.403 90.780 + +*CAP +0 mux_top_track_24\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_24\/BUFT_P_117:A 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.659283e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0004389058 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0004111895 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004321595 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004321595 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0003540739 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0003540739 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.001236118 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001236118 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.00158139 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.00158139 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 chany_bottom_in[5]:11 0.0001909075 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 chany_bottom_in[5]:12 0.0001909075 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 ropt_net_148:5 0.0001989489 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 ropt_net_148:6 0.0001989489 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 5.907936e-05 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 5.907936e-05 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:2 8.12138e-05 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_13_X[0]:3 8.12138e-05 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 ropt_net_189:6 3.665186e-06 +22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 ropt_net_189:4 2.534417e-06 +23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 ropt_net_189:8 4.471487e-05 +24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 ropt_net_189:5 2.534417e-06 +25 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 ropt_net_189:9 4.471487e-05 +26 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 ropt_net_189:7 3.665186e-06 +27 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 ropt_net_159:4 7.395411e-05 +28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 ropt_net_159:5 7.395411e-05 + +*RES +0 mux_top_track_24\/mux_l3_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_24\/BUFT_P_117:A 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.006531251 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0078125 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.006080357 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0045 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0045 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.02420536 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.02431473 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008430393 //LENGTH 5.030 LUMPCC 0.0004247616 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_2_:X O *L 0 *C 17.725 76.840 +*I mux_left_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 17.480 72.420 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 17.480 72.420 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.480 72.465 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.480 76.795 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.480 76.840 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 17.725 76.840 + +*CAP +0 mux_left_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.463541e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001297231 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001297231 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.134296e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.085328e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_3_sram[0]:27 0.0001215012 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_3_sram[0]:26 0.0001215012 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 9.087961e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 9.087961e-05 + +*RES +0 mux_left_track_5\/mux_l1_in_2_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.003866072 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001331522 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008098955 //LENGTH 6.075 LUMPCC 0.0001403714 DR + +*CONN +*I mux_left_track_7\/mux_l2_in_1_:X O *L 0 *C 41.225 63.240 +*I mux_left_track_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 43.990 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 43.953 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 42.825 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 42.780 60.905 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 42.780 63.195 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 42.735 63.240 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 41.263 63.240 + +*CAP +0 mux_left_track_7\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_7\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001013372 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001013372 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001510068 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001510068 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.141813e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.141813e-05 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size7_6_sram[1]:6 1.99964e-07 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size7_6_sram[1]:5 1.99964e-07 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_6_sram[1]:6 6.998571e-05 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_6_sram[1]:5 6.998571e-05 + +*RES +0 mux_left_track_7\/mux_l2_in_1_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_7\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001006696 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002044643 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001148071 //LENGTH 9.610 LUMPCC 0.0002218189 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_1_:X O *L 0 *C 14.545 39.100 +*I mux_bottom_track_33\/mux_l3_in_0_:A0 I *L 0.001631 *C 16.275 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 16.238 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 14.765 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 14.720 32.005 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 14.720 39.055 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 14.720 39.100 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 14.545 39.100 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001131345 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001131345 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002917633 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002917633 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.731943e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 5.713736e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_2_sram[1]:9 1.89657e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_2_sram[1]:14 1.34357e-05 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_2_sram[1]:15 2.175448e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_2_sram[1]:6 1.89657e-05 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_2_sram[1]:9 2.175448e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_2_sram[1]:15 1.34357e-05 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size6_2_sram[2]:8 8.088961e-06 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size6_2_sram[2]:7 8.088961e-06 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_2_sram[2]:6 4.866461e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_2_sram[2]:5 4.866461e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_1_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_33\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001314732 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.006294643 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009448658 //LENGTH 7.270 LUMPCC 0 DR + +*CONN +*I mux_left_track_15\/mux_l2_in_1_:X O *L 0 *C 12.135 60.860 +*I mux_left_track_15\/mux_l3_in_0_:A0 I *L 0.001631 *C 8.110 58.820 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 8.110 58.820 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 7.820 58.820 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 7.820 58.865 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 7.820 60.815 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 7.865 60.860 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 12.098 60.860 + +*CAP +0 mux_left_track_15\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_15\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.459734e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.863986e-05 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001322678 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001322678 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002825464 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002825464 + +*RES +0 mux_left_track_15\/mux_l2_in_1_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_15\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001576087 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003779018 + +*END + +*D_NET mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002921882 //LENGTH 22.500 LUMPCC 0.00106264 DR + +*CONN +*I mux_left_track_23\/mux_l1_in_0_:X O *L 0 *C 55.835 77.180 +*I mux_left_track_23\/mux_l2_in_0_:A1 I *L 0.00198 *C 40.385 83.300 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 40.422 83.300 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 43.195 83.300 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 43.240 83.255 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 43.240 77.225 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 43.285 77.180 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 55.797 77.180 + +*CAP +0 mux_left_track_23\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_23\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001222041 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001222041 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001836728 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001836728 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0006227442 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0006227442 +8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[5]:9 0.0001655792 +9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[5]:8 0.0001655792 +10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[0]:14 2.293366e-07 +11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_3_sram[0]:5 8.687036e-05 +12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[0]:13 2.293366e-07 +13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_3_sram[0]:4 8.687036e-05 +14 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[1]:3 8.240822e-05 +15 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size3_3_sram[1]:11 5.905079e-06 +16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[1]:4 8.240822e-05 +17 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_3_sram[1]:12 5.905079e-06 +18 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[1]:5 1.006045e-05 +19 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_3_sram[1]:10 5.876962e-05 +20 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[1]:9 5.876962e-05 +21 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_3_sram[1]:10 1.006045e-05 +22 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0001214976 +23 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0001214976 + +*RES +0 mux_left_track_23\/mux_l1_in_0_:X mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_23\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002475447 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005383929 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01117188 + +*END + +*D_NET ropt_net_203 0.001652271 //LENGTH 11.685 LUMPCC 0.0004171676 DR + +*CONN +*I ropt_mt_inst_777:X O *L 0 *C 76.360 4.080 +*I ropt_mt_inst_841:A I *L 0.001766 *C 81.880 6.800 +*N ropt_net_203:2 *C 81.858 6.828 +*N ropt_net_203:3 *C 81.845 7.140 +*N ropt_net_203:4 *C 79.165 7.140 +*N ropt_net_203:5 *C 79.120 7.095 +*N ropt_net_203:6 *C 79.120 3.445 +*N ropt_net_203:7 *C 79.075 3.400 +*N ropt_net_203:8 *C 76.405 3.400 +*N ropt_net_203:9 *C 76.360 3.445 +*N ropt_net_203:10 *C 76.360 4.035 +*N ropt_net_203:11 *C 76.360 4.080 + +*CAP +0 ropt_mt_inst_777:X 1e-06 +1 ropt_mt_inst_841:A 1e-06 +2 ropt_net_203:2 3.2711e-05 +3 ropt_net_203:3 0.0002289962 +4 ropt_net_203:4 0.0001962852 +5 ropt_net_203:5 9.228635e-05 +6 ropt_net_203:6 9.228635e-05 +7 ropt_net_203:7 0.0002044974 +8 ropt_net_203:8 0.0002044974 +9 ropt_net_203:9 7.34589e-05 +10 ropt_net_203:10 7.34589e-05 +11 ropt_net_203:11 3.462586e-05 +12 ropt_net_203:6 chany_bottom_in[12] 0.0001038169 +13 ropt_net_203:5 chany_bottom_in[12]:19 0.0001038169 +14 ropt_net_203:6 chany_bottom_in[19] 0.0001047669 +15 ropt_net_203:5 chany_bottom_in[19]:13 0.0001047669 + +*RES +0 ropt_mt_inst_777:X ropt_net_203:11 0.152 +1 ropt_net_203:11 ropt_net_203:10 0.0045 +2 ropt_net_203:10 ropt_net_203:9 0.0005267857 +3 ropt_net_203:8 ropt_net_203:7 0.002383929 +4 ropt_net_203:9 ropt_net_203:8 0.0045 +5 ropt_net_203:7 ropt_net_203:6 0.0045 +6 ropt_net_203:6 ropt_net_203:5 0.003258929 +7 ropt_net_203:4 ropt_net_203:3 0.002392857 +8 ropt_net_203:5 ropt_net_203:4 0.0045 +9 ropt_net_203:2 ropt_mt_inst_841:A 0.152 +10 ropt_net_203:3 ropt_net_203:2 0.0002111487 + +*END + +*D_NET BUF_net_69 0.002860172 //LENGTH 23.465 LUMPCC 0.0003980644 DR + +*CONN +*I BUFT_RR_69:X O *L 0 *C 11.040 96.220 +*I BUFT_P_119:A I *L 0.001766 *C 6.900 77.520 +*N BUF_net_69:2 *C 6.900 77.520 +*N BUF_net_69:3 *C 6.900 77.565 +*N BUF_net_69:4 *C 6.900 96.175 +*N BUF_net_69:5 *C 6.945 96.220 +*N BUF_net_69:6 *C 11.003 96.220 + +*CAP +0 BUFT_RR_69:X 1e-06 +1 BUFT_P_119:A 1e-06 +2 BUF_net_69:2 3.60484e-05 +3 BUF_net_69:3 0.000934439 +4 BUF_net_69:4 0.000934439 +5 BUF_net_69:5 0.0002775903 +6 BUF_net_69:6 0.0002775903 +7 BUF_net_69:3 chany_top_in[19]:4 0.0001534626 +8 BUF_net_69:3 chany_top_in[19]:8 3.072912e-07 +9 BUF_net_69:4 chany_top_in[19]:5 0.0001534626 +10 BUF_net_69:4 chany_top_in[19]:9 3.072912e-07 +11 BUF_net_69:5 ropt_net_169:2 4.526233e-05 +12 BUF_net_69:6 ropt_net_169:3 4.526233e-05 + +*RES +0 BUFT_RR_69:X BUF_net_69:6 0.152 +1 BUF_net_69:2 BUFT_P_119:A 0.152 +2 BUF_net_69:3 BUF_net_69:2 0.0045 +3 BUF_net_69:5 BUF_net_69:4 0.0045 +4 BUF_net_69:4 BUF_net_69:3 0.01661607 +5 BUF_net_69:6 BUF_net_69:5 0.003622768 + +*END + +*D_NET ropt_net_194 0.001458034 //LENGTH 9.995 LUMPCC 0.0003027766 DR + +*CONN +*I ropt_mt_inst_803:X O *L 0 *C 54.935 121.720 +*I ropt_mt_inst_826:A I *L 0.001767 *C 51.980 126.480 +*N ropt_net_194:2 *C 51.943 126.480 +*N ropt_net_194:3 *C 51.565 126.480 +*N ropt_net_194:4 *C 51.520 126.435 +*N ropt_net_194:5 *C 51.520 124.485 +*N ropt_net_194:6 *C 51.565 124.440 +*N ropt_net_194:7 *C 54.695 124.440 +*N ropt_net_194:8 *C 54.740 124.395 +*N ropt_net_194:9 *C 54.740 121.765 +*N ropt_net_194:10 *C 54.740 121.720 +*N ropt_net_194:11 *C 54.935 121.720 + +*CAP +0 ropt_mt_inst_803:X 1e-06 +1 ropt_mt_inst_826:A 1e-06 +2 ropt_net_194:2 5.879551e-05 +3 ropt_net_194:3 5.879551e-05 +4 ropt_net_194:4 0.0001056106 +5 ropt_net_194:5 0.0001056106 +6 ropt_net_194:6 0.0002017325 +7 ropt_net_194:7 0.0002017325 +8 ropt_net_194:8 0.000162456 +9 ropt_net_194:9 0.000162456 +10 ropt_net_194:10 4.804569e-05 +11 ropt_net_194:11 4.802248e-05 +12 ropt_net_194:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.891234e-05 +13 ropt_net_194:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.891234e-05 +14 ropt_net_194:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.98796e-06 +15 ropt_net_194:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 1.273621e-05 +16 ropt_net_194:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 4.98796e-06 +17 ropt_net_194:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 1.273621e-05 +18 ropt_net_194:4 chany_top_out[7]:5 5.388847e-05 +19 ropt_net_194:6 chany_top_out[7]:7 7.919991e-07 +20 ropt_net_194:5 chany_top_out[7]:6 5.388847e-05 +21 ropt_net_194:7 chany_top_out[7]:8 7.919991e-07 +22 ropt_net_194:8 chany_top_out[7]:5 7.130657e-08 +23 ropt_net_194:9 chany_top_out[7]:6 7.130657e-08 + +*RES +0 ropt_mt_inst_803:X ropt_net_194:11 0.152 +1 ropt_net_194:2 ropt_mt_inst_826:A 0.152 +2 ropt_net_194:3 ropt_net_194:2 0.0003370536 +3 ropt_net_194:4 ropt_net_194:3 0.0045 +4 ropt_net_194:6 ropt_net_194:5 0.0045 +5 ropt_net_194:5 ropt_net_194:4 0.001741071 +6 ropt_net_194:7 ropt_net_194:6 0.002794643 +7 ropt_net_194:8 ropt_net_194:7 0.0045 +8 ropt_net_194:10 ropt_net_194:9 0.0045 +9 ropt_net_194:9 ropt_net_194:8 0.002348215 +10 ropt_net_194:11 ropt_net_194:10 0.0001059783 + +*END + +*D_NET ropt_net_160 0.001551672 //LENGTH 14.310 LUMPCC 0.0003008432 DR + +*CONN +*I BUFT_P_125:X O *L 0 *C 95.680 115.940 +*I ropt_mt_inst_785:A I *L 0.001766 *C 95.220 123.760 +*N ropt_net_160:2 *C 95.258 123.760 +*N ropt_net_160:3 *C 96.140 123.760 +*N ropt_net_160:4 *C 96.140 124.100 +*N ropt_net_160:5 *C 94.345 124.100 +*N ropt_net_160:6 *C 94.300 124.055 +*N ropt_net_160:7 *C 94.300 115.985 +*N ropt_net_160:8 *C 94.345 115.940 +*N ropt_net_160:9 *C 95.642 115.940 + +*CAP +0 BUFT_P_125:X 1e-06 +1 ropt_mt_inst_785:A 1e-06 +2 ropt_net_160:2 1.719099e-05 +3 ropt_net_160:3 4.137702e-05 +4 ropt_net_160:4 0.0001597457 +5 ropt_net_160:5 0.0001355597 +6 ropt_net_160:6 0.0003647831 +7 ropt_net_160:7 0.0003647831 +8 ropt_net_160:8 8.26945e-05 +9 ropt_net_160:9 8.26945e-05 +10 ropt_net_160:7 chany_bottom_in[13]:9 4.02384e-07 +11 ropt_net_160:7 chany_bottom_in[13]:13 1.77419e-05 +12 ropt_net_160:5 chany_bottom_in[13]:11 2.634523e-05 +13 ropt_net_160:6 chany_bottom_in[13]:8 4.02384e-07 +14 ropt_net_160:6 chany_bottom_in[13]:12 1.77419e-05 +15 ropt_net_160:2 chany_bottom_in[13]:11 3.685897e-05 +16 ropt_net_160:4 chany_bottom_in[13]:10 2.634523e-05 +17 ropt_net_160:3 chany_bottom_in[13]:10 3.685897e-05 +18 ropt_net_160:7 chany_top_out[11]:2 6.907311e-05 +19 ropt_net_160:6 chany_top_out[11] 6.907311e-05 + +*RES +0 BUFT_P_125:X ropt_net_160:9 0.152 +1 ropt_net_160:9 ropt_net_160:8 0.001158482 +2 ropt_net_160:8 ropt_net_160:7 0.0045 +3 ropt_net_160:7 ropt_net_160:6 0.007205358 +4 ropt_net_160:5 ropt_net_160:4 0.001602679 +5 ropt_net_160:6 ropt_net_160:5 0.0045 +6 ropt_net_160:2 ropt_mt_inst_785:A 0.152 +7 ropt_net_160:4 ropt_net_160:3 0.0003035715 +8 ropt_net_160:3 ropt_net_160:2 0.0007879463 + +*END + +*D_NET chany_top_in[3] 0.01405618 //LENGTH 95.945 LUMPCC 0.003956025 DR + +*CONN +*P chany_top_in[3] I *L 0.29796 *C 74.060 129.270 +*I BUFT_RR_69:A I *L 0.001776 *C 13.340 96.560 +*N chany_top_in[3]:2 *C 13.340 96.560 +*N chany_top_in[3]:3 *C 19.275 96.560 +*N chany_top_in[3]:4 *C 19.320 96.560 +*N chany_top_in[3]:5 *C 19.328 96.560 +*N chany_top_in[3]:6 *C 37.700 96.560 +*N chany_top_in[3]:7 *C 37.720 96.568 +*N chany_top_in[3]:8 *C 37.720 118.312 +*N chany_top_in[3]:9 *C 37.740 118.320 +*N chany_top_in[3]:10 *C 74.053 118.320 +*N chany_top_in[3]:11 *C 74.060 118.378 + +*CAP +0 chany_top_in[3] 0.0006671251 +1 BUFT_RR_69:A 1e-06 +2 chany_top_in[3]:2 0.000427916 +3 chany_top_in[3]:3 0.000394616 +4 chany_top_in[3]:4 3.698812e-05 +5 chany_top_in[3]:5 0.0007930753 +6 chany_top_in[3]:6 0.0007930753 +7 chany_top_in[3]:7 0.0009147125 +8 chany_top_in[3]:8 0.0009147125 +9 chany_top_in[3]:9 0.002244906 +10 chany_top_in[3]:10 0.002244906 +11 chany_top_in[3]:11 0.0006671251 +12 chany_top_in[3]:7 chany_top_in[1]:11 0.0002885943 +13 chany_top_in[3]:9 chany_top_in[1]:13 2.372622e-05 +14 chany_top_in[3]:8 chany_top_in[1]:12 0.0002885943 +15 chany_top_in[3]:10 chany_top_in[1]:14 2.372622e-05 +16 chany_top_in[3]:7 chany_top_in[11]:12 8.605495e-05 +17 chany_top_in[3]:9 chany_top_in[11]:14 0.0002915832 +18 chany_top_in[3]:8 chany_top_in[11]:13 8.605495e-05 +19 chany_top_in[3]:10 chany_top_in[11]:15 0.0002915832 +20 chany_top_in[3]:5 chanx_left_in[12]:21 0.001044179 +21 chany_top_in[3]:6 chanx_left_in[12]:20 0.001044179 +22 chany_top_in[3]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001505647 +23 chany_top_in[3]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001505647 +24 chany_top_in[3]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 9.331009e-05 +25 chany_top_in[3]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.331009e-05 + +*RES +0 chany_top_in[3] chany_top_in[3]:11 0.009725447 +1 chany_top_in[3]:2 BUFT_RR_69:A 0.152 +2 chany_top_in[3]:3 chany_top_in[3]:2 0.005299108 +3 chany_top_in[3]:4 chany_top_in[3]:3 0.0045 +4 chany_top_in[3]:5 chany_top_in[3]:4 0.00341 +5 chany_top_in[3]:6 chany_top_in[3]:5 0.002878358 +6 chany_top_in[3]:7 chany_top_in[3]:6 0.00341 +7 chany_top_in[3]:9 chany_top_in[3]:8 0.00341 +8 chany_top_in[3]:8 chany_top_in[3]:7 0.003406716 +9 chany_top_in[3]:11 chany_top_in[3]:10 0.00341 +10 chany_top_in[3]:10 chany_top_in[3]:9 0.005688958 + +*END + +*D_NET top_left_grid_pin_39_[0] 0.007298825 //LENGTH 55.925 LUMPCC 0.0006290251 DR + +*CONN +*P top_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 123.760 +*I mux_top_track_16\/mux_l1_in_0_:A0 I *L 0.001631 *C 49.855 107.780 +*I mux_top_track_4\/mux_l1_in_2_:A0 I *L 0.001631 *C 49.855 118.660 +*I mux_top_track_2\/mux_l2_in_0_:A0 I *L 0.001631 *C 33.295 104.380 +*N top_left_grid_pin_39_[0]:4 *C 33.295 104.380 +*N top_left_grid_pin_39_[0]:5 *C 33.580 104.380 +*N top_left_grid_pin_39_[0]:6 *C 33.580 104.425 +*N top_left_grid_pin_39_[0]:7 *C 49.818 118.660 +*N top_left_grid_pin_39_[0]:8 *C 48.805 118.660 +*N top_left_grid_pin_39_[0]:9 *C 48.760 118.615 +*N top_left_grid_pin_39_[0]:10 *C 49.818 107.780 +*N top_left_grid_pin_39_[0]:11 *C 48.805 107.780 +*N top_left_grid_pin_39_[0]:12 *C 48.760 107.780 +*N top_left_grid_pin_39_[0]:13 *C 48.760 105.458 +*N top_left_grid_pin_39_[0]:14 *C 48.753 105.400 +*N top_left_grid_pin_39_[0]:15 *C 33.587 105.400 +*N top_left_grid_pin_39_[0]:16 *C 33.580 105.400 +*N top_left_grid_pin_39_[0]:17 *C 33.580 123.703 +*N top_left_grid_pin_39_[0]:18 *C 33.573 123.760 + +*CAP +0 top_left_grid_pin_39_[0] 0.0002673003 +1 mux_top_track_16\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_4\/mux_l1_in_2_:A0 1e-06 +3 mux_top_track_2\/mux_l2_in_0_:A0 1e-06 +4 top_left_grid_pin_39_[0]:4 5.038041e-05 +5 top_left_grid_pin_39_[0]:5 5.647873e-05 +6 top_left_grid_pin_39_[0]:6 6.016238e-05 +7 top_left_grid_pin_39_[0]:7 8.27139e-05 +8 top_left_grid_pin_39_[0]:8 8.27139e-05 +9 top_left_grid_pin_39_[0]:9 0.0006180315 +10 top_left_grid_pin_39_[0]:10 8.003335e-05 +11 top_left_grid_pin_39_[0]:11 8.003335e-05 +12 top_left_grid_pin_39_[0]:12 0.0007880124 +13 top_left_grid_pin_39_[0]:13 0.0001398616 +14 top_left_grid_pin_39_[0]:14 0.001165046 +15 top_left_grid_pin_39_[0]:15 0.001165046 +16 top_left_grid_pin_39_[0]:16 0.0009302917 +17 top_left_grid_pin_39_[0]:17 0.0008333942 +18 top_left_grid_pin_39_[0]:18 0.0002673003 +19 top_left_grid_pin_39_[0]:17 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0002271647 +20 top_left_grid_pin_39_[0]:16 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0002271647 +21 top_left_grid_pin_39_[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.974128e-06 +22 top_left_grid_pin_39_[0]:17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.137377e-05 +23 top_left_grid_pin_39_[0]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.137377e-05 +24 top_left_grid_pin_39_[0]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.974128e-06 + +*RES +0 top_left_grid_pin_39_[0] top_left_grid_pin_39_[0]:18 0.0005988583 +1 top_left_grid_pin_39_[0]:5 top_left_grid_pin_39_[0]:4 0.0001548913 +2 top_left_grid_pin_39_[0]:6 top_left_grid_pin_39_[0]:5 0.0045 +3 top_left_grid_pin_39_[0]:4 mux_top_track_2\/mux_l2_in_0_:A0 0.152 +4 top_left_grid_pin_39_[0]:17 top_left_grid_pin_39_[0]:16 0.01634152 +5 top_left_grid_pin_39_[0]:18 top_left_grid_pin_39_[0]:17 0.00341 +6 top_left_grid_pin_39_[0]:16 top_left_grid_pin_39_[0]:15 0.00341 +7 top_left_grid_pin_39_[0]:16 top_left_grid_pin_39_[0]:6 0.0008705358 +8 top_left_grid_pin_39_[0]:15 top_left_grid_pin_39_[0]:14 0.00237585 +9 top_left_grid_pin_39_[0]:13 top_left_grid_pin_39_[0]:12 0.002073661 +10 top_left_grid_pin_39_[0]:14 top_left_grid_pin_39_[0]:13 0.00341 +11 top_left_grid_pin_39_[0]:11 top_left_grid_pin_39_[0]:10 0.0009040179 +12 top_left_grid_pin_39_[0]:12 top_left_grid_pin_39_[0]:11 0.0045 +13 top_left_grid_pin_39_[0]:12 top_left_grid_pin_39_[0]:9 0.009674108 +14 top_left_grid_pin_39_[0]:10 mux_top_track_16\/mux_l1_in_0_:A0 0.152 +15 top_left_grid_pin_39_[0]:8 top_left_grid_pin_39_[0]:7 0.0009040179 +16 top_left_grid_pin_39_[0]:9 top_left_grid_pin_39_[0]:8 0.0045 +17 top_left_grid_pin_39_[0]:7 mux_top_track_4\/mux_l1_in_2_:A0 0.152 + +*END + +*D_NET bottom_left_grid_pin_36_[0] 0.005008343 //LENGTH 38.995 LUMPCC 0.001678981 DR + +*CONN +*P bottom_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 6.800 +*I mux_bottom_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 33.295 9.860 +*I mux_bottom_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 26.050 31.620 +*I mux_bottom_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 30.190 31.620 +*N bottom_left_grid_pin_36_[0]:4 *C 30.228 31.620 +*N bottom_left_grid_pin_36_[0]:5 *C 30.775 31.620 +*N bottom_left_grid_pin_36_[0]:6 *C 30.820 31.575 +*N bottom_left_grid_pin_36_[0]:7 *C 26.088 31.620 +*N bottom_left_grid_pin_36_[0]:8 *C 26.635 31.620 +*N bottom_left_grid_pin_36_[0]:9 *C 26.680 31.575 +*N bottom_left_grid_pin_36_[0]:10 *C 26.680 29.285 +*N bottom_left_grid_pin_36_[0]:11 *C 26.725 29.240 +*N bottom_left_grid_pin_36_[0]:12 *C 30.775 29.240 +*N bottom_left_grid_pin_36_[0]:13 *C 30.820 29.240 +*N bottom_left_grid_pin_36_[0]:14 *C 30.820 10.200 +*N bottom_left_grid_pin_36_[0]:15 *C 31.235 10.200 +*N bottom_left_grid_pin_36_[0]:16 *C 31.280 9.765 +*N bottom_left_grid_pin_36_[0]:17 *C 33.258 9.860 +*N bottom_left_grid_pin_36_[0]:18 *C 31.325 9.860 +*N bottom_left_grid_pin_36_[0]:19 *C 31.280 9.735 +*N bottom_left_grid_pin_36_[0]:20 *C 31.280 6.857 +*N bottom_left_grid_pin_36_[0]:21 *C 31.273 6.800 + +*CAP +0 bottom_left_grid_pin_36_[0] 0.0001146674 +1 mux_bottom_track_5\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_3\/mux_l1_in_1_:A0 1e-06 +4 bottom_left_grid_pin_36_[0]:4 7.405381e-05 +5 bottom_left_grid_pin_36_[0]:5 7.405381e-05 +6 bottom_left_grid_pin_36_[0]:6 0.0001707313 +7 bottom_left_grid_pin_36_[0]:7 6.383878e-05 +8 bottom_left_grid_pin_36_[0]:8 6.383878e-05 +9 bottom_left_grid_pin_36_[0]:9 0.0001206781 +10 bottom_left_grid_pin_36_[0]:10 0.0001206781 +11 bottom_left_grid_pin_36_[0]:11 0.0002025207 +12 bottom_left_grid_pin_36_[0]:12 0.0002025207 +13 bottom_left_grid_pin_36_[0]:13 0.0007487407 +14 bottom_left_grid_pin_36_[0]:14 0.0005684452 +15 bottom_left_grid_pin_36_[0]:15 4.866109e-05 +16 bottom_left_grid_pin_36_[0]:16 1.487468e-05 +17 bottom_left_grid_pin_36_[0]:17 0.0001305859 +18 bottom_left_grid_pin_36_[0]:18 0.0001305859 +19 bottom_left_grid_pin_36_[0]:19 0.0002003029 +20 bottom_left_grid_pin_36_[0]:20 0.0001619178 +21 bottom_left_grid_pin_36_[0]:21 0.0001146674 +22 bottom_left_grid_pin_36_[0]:6 prog_clk[0]:260 4.5588e-06 +23 bottom_left_grid_pin_36_[0]:13 prog_clk[0]:259 4.5588e-06 +24 bottom_left_grid_pin_36_[0]:13 prog_clk[0]:260 0.0002513849 +25 bottom_left_grid_pin_36_[0]:14 prog_clk[0]:259 0.0002513849 +26 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_40_[0]:14 0.0001472123 +27 bottom_left_grid_pin_36_[0]:13 bottom_left_grid_pin_40_[0]:19 1.988092e-05 +28 bottom_left_grid_pin_36_[0]:13 bottom_left_grid_pin_40_[0]:15 0.0003861476 +29 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_40_[0]:13 0.0001472123 +30 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_40_[0]:12 3.030592e-05 +31 bottom_left_grid_pin_36_[0]:9 bottom_left_grid_pin_40_[0]:11 3.030592e-05 +32 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_40_[0]:20 1.988092e-05 +33 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_40_[0]:16 0.0003861476 + +*RES +0 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_36_[0]:21 0.000238525 +1 bottom_left_grid_pin_36_[0]:18 bottom_left_grid_pin_36_[0]:17 0.001725446 +2 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:18 0.0045 +3 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:16 1.875e-05 +4 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:15 0.000290625 +5 bottom_left_grid_pin_36_[0]:17 mux_bottom_track_5\/mux_l1_in_2_:A0 0.152 +6 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_36_[0]:19 0.002569197 +7 bottom_left_grid_pin_36_[0]:21 bottom_left_grid_pin_36_[0]:20 0.00341 +8 bottom_left_grid_pin_36_[0]:5 bottom_left_grid_pin_36_[0]:4 0.0004888393 +9 bottom_left_grid_pin_36_[0]:6 bottom_left_grid_pin_36_[0]:5 0.0045 +10 bottom_left_grid_pin_36_[0]:4 mux_bottom_track_3\/mux_l1_in_1_:A0 0.152 +11 bottom_left_grid_pin_36_[0]:12 bottom_left_grid_pin_36_[0]:11 0.003616072 +12 bottom_left_grid_pin_36_[0]:13 bottom_left_grid_pin_36_[0]:12 0.0045 +13 bottom_left_grid_pin_36_[0]:13 bottom_left_grid_pin_36_[0]:6 0.002084821 +14 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_36_[0]:10 0.0045 +15 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_36_[0]:9 0.002044643 +16 bottom_left_grid_pin_36_[0]:8 bottom_left_grid_pin_36_[0]:7 0.0004888393 +17 bottom_left_grid_pin_36_[0]:9 bottom_left_grid_pin_36_[0]:8 0.0045 +18 bottom_left_grid_pin_36_[0]:7 mux_bottom_track_33\/mux_l1_in_0_:A0 0.152 +19 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_36_[0]:13 0.017 +20 bottom_left_grid_pin_36_[0]:15 bottom_left_grid_pin_36_[0]:14 0.0003705357 + +*END + +*D_NET chanx_left_in[9] 0.00610021 //LENGTH 44.645 LUMPCC 0.001247306 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 72.080 +*I mux_top_track_24\/mux_l1_in_2_:A0 I *L 0.001631 *C 22.715 71.740 +*I mux_bottom_track_3\/mux_l2_in_2_:A0 I *L 0.001631 *C 19.955 49.980 +*N chanx_left_in[9]:3 *C 19.955 49.980 +*N chanx_left_in[9]:4 *C 19.780 49.980 +*N chanx_left_in[9]:5 *C 19.780 50.025 +*N chanx_left_in[9]:6 *C 22.678 71.740 +*N chanx_left_in[9]:7 *C 19.825 71.740 +*N chanx_left_in[9]:8 *C 19.780 71.695 +*N chanx_left_in[9]:9 *C 19.780 72.080 +*N chanx_left_in[9]:10 *C 19.773 72.080 + +*CAP +0 chanx_left_in[9] 0.001107195 +1 mux_top_track_24\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_track_3\/mux_l2_in_2_:A0 1e-06 +3 chanx_left_in[9]:3 5.502588e-05 +4 chanx_left_in[9]:4 5.844212e-05 +5 chanx_left_in[9]:5 0.001040854 +6 chanx_left_in[9]:6 0.0001798968 +7 chanx_left_in[9]:7 0.0001798968 +8 chanx_left_in[9]:8 0.001064116 +9 chanx_left_in[9]:9 5.828171e-05 +10 chanx_left_in[9]:10 0.001107195 +11 chanx_left_in[9]:5 mux_tree_tapbuf_size3_0_sram[0]:17 7.419498e-05 +12 chanx_left_in[9]:5 mux_tree_tapbuf_size3_0_sram[0]:9 4.717578e-05 +13 chanx_left_in[9]:5 mux_tree_tapbuf_size3_0_sram[0]:12 8.098906e-05 +14 chanx_left_in[9]:8 mux_tree_tapbuf_size3_0_sram[0]:16 7.419498e-05 +15 chanx_left_in[9]:8 mux_tree_tapbuf_size3_0_sram[0]:12 4.717578e-05 +16 chanx_left_in[9]:8 mux_tree_tapbuf_size3_0_sram[0]:13 8.098906e-05 +17 chanx_left_in[9]:5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 5.217312e-05 +18 chanx_left_in[9]:8 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 5.217312e-05 +19 chanx_left_in[9] mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001947068 +20 chanx_left_in[9]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001947068 +21 chanx_left_in[9]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001188337 +22 chanx_left_in[9]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001188337 +23 chanx_left_in[9]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.557952e-05 +24 chanx_left_in[9]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.557952e-05 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:10 0.002904991 +1 chanx_left_in[9]:4 chanx_left_in[9]:3 9.51087e-05 +2 chanx_left_in[9]:5 chanx_left_in[9]:4 0.0045 +3 chanx_left_in[9]:3 mux_bottom_track_3\/mux_l2_in_2_:A0 0.152 +4 chanx_left_in[9]:7 chanx_left_in[9]:6 0.002546875 +5 chanx_left_in[9]:8 chanx_left_in[9]:7 0.0045 +6 chanx_left_in[9]:8 chanx_left_in[9]:5 0.01934822 +7 chanx_left_in[9]:6 mux_top_track_24\/mux_l1_in_2_:A0 0.152 +8 chanx_left_in[9]:9 chanx_left_in[9]:8 0.0001850962 +9 chanx_left_in[9]:10 chanx_left_in[9]:9 0.00341 + +*END + +*D_NET left_top_grid_pin_47_[0] 0.008234478 //LENGTH 69.435 LUMPCC 0.0002377036 DR + +*CONN +*P left_top_grid_pin_47_[0] I *L 0.29796 *C 3.220 102.070 +*I mux_left_track_3\/mux_l1_in_2_:A0 I *L 0.001631 *C 19.610 86.020 +*I mux_left_track_19\/mux_l1_in_1_:A1 I *L 0.00198 *C 25.400 58.140 +*I mux_left_track_7\/mux_l1_in_2_:A0 I *L 0.001631 *C 24.090 64.600 +*N left_top_grid_pin_47_[0]:4 *C 18.920 86.020 +*N left_top_grid_pin_47_[0]:5 *C 23.968 64.600 +*N left_top_grid_pin_47_[0]:6 *C 25.363 58.140 +*N left_top_grid_pin_47_[0]:7 *C 23.965 58.140 +*N left_top_grid_pin_47_[0]:8 *C 23.920 58.185 +*N left_top_grid_pin_47_[0]:9 *C 23.920 64.555 +*N left_top_grid_pin_47_[0]:10 *C 23.875 64.600 +*N left_top_grid_pin_47_[0]:11 *C 21.205 64.600 +*N left_top_grid_pin_47_[0]:12 *C 21.160 64.645 +*N left_top_grid_pin_47_[0]:13 *C 21.160 85.975 +*N left_top_grid_pin_47_[0]:14 *C 21.115 86.020 +*N left_top_grid_pin_47_[0]:15 *C 19.648 86.020 +*N left_top_grid_pin_47_[0]:16 *C 19.320 86.020 +*N left_top_grid_pin_47_[0]:17 *C 19.320 86.020 +*N left_top_grid_pin_47_[0]:18 *C 19.320 86.020 +*N left_top_grid_pin_47_[0]:19 *C 19.320 86.028 +*N left_top_grid_pin_47_[0]:20 *C 19.320 100.633 +*N left_top_grid_pin_47_[0]:21 *C 19.300 100.640 +*N left_top_grid_pin_47_[0]:22 *C 3.228 100.640 +*N left_top_grid_pin_47_[0]:23 *C 3.220 100.698 + +*CAP +0 left_top_grid_pin_47_[0] 8.988351e-05 +1 mux_left_track_3\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_19\/mux_l1_in_1_:A1 1e-06 +3 mux_left_track_7\/mux_l1_in_2_:A0 1e-06 +4 left_top_grid_pin_47_[0]:4 8.160339e-05 +5 left_top_grid_pin_47_[0]:5 1.551227e-05 +6 left_top_grid_pin_47_[0]:6 0.0001209433 +7 left_top_grid_pin_47_[0]:7 0.0001209433 +8 left_top_grid_pin_47_[0]:8 0.0004015524 +9 left_top_grid_pin_47_[0]:9 0.0004015524 +10 left_top_grid_pin_47_[0]:10 0.0001425975 +11 left_top_grid_pin_47_[0]:11 0.0001270853 +12 left_top_grid_pin_47_[0]:12 0.001213889 +13 left_top_grid_pin_47_[0]:13 0.001213889 +14 left_top_grid_pin_47_[0]:14 0.0001128729 +15 left_top_grid_pin_47_[0]:15 0.0001327787 +16 left_top_grid_pin_47_[0]:16 5.564435e-05 +17 left_top_grid_pin_47_[0]:17 3.986867e-05 +18 left_top_grid_pin_47_[0]:18 8.160339e-05 +19 left_top_grid_pin_47_[0]:19 0.0007947723 +20 left_top_grid_pin_47_[0]:20 0.0007947723 +21 left_top_grid_pin_47_[0]:21 0.0009810638 +22 left_top_grid_pin_47_[0]:22 0.0009810638 +23 left_top_grid_pin_47_[0]:23 8.988351e-05 +24 left_top_grid_pin_47_[0]:10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.320596e-05 +25 left_top_grid_pin_47_[0]:10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001056459 +26 left_top_grid_pin_47_[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.320596e-05 +27 left_top_grid_pin_47_[0]:11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001056459 + +*RES +0 left_top_grid_pin_47_[0] left_top_grid_pin_47_[0]:23 0.001225446 +1 left_top_grid_pin_47_[0]:10 left_top_grid_pin_47_[0]:9 0.0045 +2 left_top_grid_pin_47_[0]:10 left_top_grid_pin_47_[0]:5 8.258929e-05 +3 left_top_grid_pin_47_[0]:9 left_top_grid_pin_47_[0]:8 0.0056875 +4 left_top_grid_pin_47_[0]:7 left_top_grid_pin_47_[0]:6 0.001247768 +5 left_top_grid_pin_47_[0]:8 left_top_grid_pin_47_[0]:7 0.0045 +6 left_top_grid_pin_47_[0]:6 mux_left_track_19\/mux_l1_in_1_:A1 0.152 +7 left_top_grid_pin_47_[0]:5 mux_left_track_7\/mux_l1_in_2_:A0 0.152 +8 left_top_grid_pin_47_[0]:14 left_top_grid_pin_47_[0]:13 0.0045 +9 left_top_grid_pin_47_[0]:13 left_top_grid_pin_47_[0]:12 0.01904464 +10 left_top_grid_pin_47_[0]:11 left_top_grid_pin_47_[0]:10 0.002383929 +11 left_top_grid_pin_47_[0]:12 left_top_grid_pin_47_[0]:11 0.0045 +12 left_top_grid_pin_47_[0]:15 mux_left_track_3\/mux_l1_in_2_:A0 0.152 +13 left_top_grid_pin_47_[0]:15 left_top_grid_pin_47_[0]:14 0.001310268 +14 left_top_grid_pin_47_[0]:16 left_top_grid_pin_47_[0]:15 0.0001779891 +15 left_top_grid_pin_47_[0]:17 left_top_grid_pin_47_[0]:16 0.0045 +16 left_top_grid_pin_47_[0]:18 left_top_grid_pin_47_[0]:17 0.00341 +17 left_top_grid_pin_47_[0]:18 left_top_grid_pin_47_[0]:4 5.69697e-05 +18 left_top_grid_pin_47_[0]:19 left_top_grid_pin_47_[0]:18 0.00341 +19 left_top_grid_pin_47_[0]:21 left_top_grid_pin_47_[0]:20 0.00341 +20 left_top_grid_pin_47_[0]:20 left_top_grid_pin_47_[0]:19 0.002288116 +21 left_top_grid_pin_47_[0]:23 left_top_grid_pin_47_[0]:22 0.00341 +22 left_top_grid_pin_47_[0]:22 left_top_grid_pin_47_[0]:21 0.002518025 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[2] 0.003234984 //LENGTH 27.070 LUMPCC 0.0001639953 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 50.905 28.220 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 42.035 26.180 +*I mux_bottom_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 47.480 20.400 +*I mux_bottom_track_1\/mux_l3_in_1_:S I *L 0.00357 *C 47.020 31.280 +*N mux_tree_tapbuf_size10_1_sram[2]:4 *C 47.058 31.280 +*N mux_tree_tapbuf_size10_1_sram[2]:5 *C 50.095 31.280 +*N mux_tree_tapbuf_size10_1_sram[2]:6 *C 50.140 31.235 +*N mux_tree_tapbuf_size10_1_sram[2]:7 *C 47.518 20.400 +*N mux_tree_tapbuf_size10_1_sram[2]:8 *C 50.095 20.400 +*N mux_tree_tapbuf_size10_1_sram[2]:9 *C 50.140 20.445 +*N mux_tree_tapbuf_size10_1_sram[2]:10 *C 42.073 26.180 +*N mux_tree_tapbuf_size10_1_sram[2]:11 *C 50.095 26.180 +*N mux_tree_tapbuf_size10_1_sram[2]:12 *C 50.140 26.180 +*N mux_tree_tapbuf_size10_1_sram[2]:13 *C 50.140 28.220 +*N mux_tree_tapbuf_size10_1_sram[2]:14 *C 50.185 28.220 +*N mux_tree_tapbuf_size10_1_sram[2]:15 *C 50.867 28.220 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_track_1\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_track_1\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size10_1_sram[2]:4 0.0002112608 +5 mux_tree_tapbuf_size10_1_sram[2]:5 0.0002112608 +6 mux_tree_tapbuf_size10_1_sram[2]:6 0.0001753391 +7 mux_tree_tapbuf_size10_1_sram[2]:7 0.0001506488 +8 mux_tree_tapbuf_size10_1_sram[2]:8 0.0001506488 +9 mux_tree_tapbuf_size10_1_sram[2]:9 0.0002837326 +10 mux_tree_tapbuf_size10_1_sram[2]:10 0.0005139486 +11 mux_tree_tapbuf_size10_1_sram[2]:11 0.0005139486 +12 mux_tree_tapbuf_size10_1_sram[2]:12 0.0004215792 +13 mux_tree_tapbuf_size10_1_sram[2]:13 0.0003173641 +14 mux_tree_tapbuf_size10_1_sram[2]:14 5.862884e-05 +15 mux_tree_tapbuf_size10_1_sram[2]:15 5.862884e-05 +16 mux_tree_tapbuf_size10_1_sram[2]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.315203e-05 +17 mux_tree_tapbuf_size10_1_sram[2]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.884561e-05 +18 mux_tree_tapbuf_size10_1_sram[2]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.315203e-05 +19 mux_tree_tapbuf_size10_1_sram[2]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.884561e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_1_sram[2]:15 0.152 +1 mux_tree_tapbuf_size10_1_sram[2]:11 mux_tree_tapbuf_size10_1_sram[2]:10 0.007162947 +2 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:11 0.0045 +3 mux_tree_tapbuf_size10_1_sram[2]:12 mux_tree_tapbuf_size10_1_sram[2]:9 0.005120536 +4 mux_tree_tapbuf_size10_1_sram[2]:10 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +5 mux_tree_tapbuf_size10_1_sram[2]:14 mux_tree_tapbuf_size10_1_sram[2]:13 0.0045 +6 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:12 0.001821429 +7 mux_tree_tapbuf_size10_1_sram[2]:13 mux_tree_tapbuf_size10_1_sram[2]:6 0.002691964 +8 mux_tree_tapbuf_size10_1_sram[2]:15 mux_tree_tapbuf_size10_1_sram[2]:14 0.000609375 +9 mux_tree_tapbuf_size10_1_sram[2]:5 mux_tree_tapbuf_size10_1_sram[2]:4 0.002712054 +10 mux_tree_tapbuf_size10_1_sram[2]:6 mux_tree_tapbuf_size10_1_sram[2]:5 0.0045 +11 mux_tree_tapbuf_size10_1_sram[2]:4 mux_bottom_track_1\/mux_l3_in_1_:S 0.152 +12 mux_tree_tapbuf_size10_1_sram[2]:8 mux_tree_tapbuf_size10_1_sram[2]:7 0.00230134 +13 mux_tree_tapbuf_size10_1_sram[2]:9 mux_tree_tapbuf_size10_1_sram[2]:8 0.0045 +14 mux_tree_tapbuf_size10_1_sram[2]:7 mux_bottom_track_1\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[0] 0.005945044 //LENGTH 43.580 LUMPCC 0 DR + +*CONN +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.025 69.700 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 33.295 71.740 +*I mux_left_track_21\/mux_l1_in_0_:S I *L 0.00357 *C 53.920 72.080 +*I mux_left_track_21\/mux_l1_in_1_:S I *L 0.00357 *C 26.120 77.520 +*N mux_tree_tapbuf_size3_2_sram[0]:4 *C 26.158 77.520 +*N mux_tree_tapbuf_size3_2_sram[0]:5 *C 35.375 77.520 +*N mux_tree_tapbuf_size3_2_sram[0]:6 *C 35.420 77.475 +*N mux_tree_tapbuf_size3_2_sram[0]:7 *C 53.883 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:8 *C 51.980 72.080 +*N mux_tree_tapbuf_size3_2_sram[0]:9 *C 51.980 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:10 *C 35.420 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:11 *C 33.333 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:12 *C 34.500 71.740 +*N mux_tree_tapbuf_size3_2_sram[0]:13 *C 34.500 71.400 +*N mux_tree_tapbuf_size3_2_sram[0]:14 *C 35.420 71.430 +*N mux_tree_tapbuf_size3_2_sram[0]:15 *C 35.420 71.400 +*N mux_tree_tapbuf_size3_2_sram[0]:16 *C 35.420 69.745 +*N mux_tree_tapbuf_size3_2_sram[0]:17 *C 35.465 69.700 +*N mux_tree_tapbuf_size3_2_sram[0]:18 *C 37.988 69.700 + +*CAP +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_21\/mux_l1_in_0_:S 1e-06 +3 mux_left_track_21\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size3_2_sram[0]:4 0.000707726 +5 mux_tree_tapbuf_size3_2_sram[0]:5 0.000707726 +6 mux_tree_tapbuf_size3_2_sram[0]:6 0.0004224132 +7 mux_tree_tapbuf_size3_2_sram[0]:7 0.0001547598 +8 mux_tree_tapbuf_size3_2_sram[0]:8 0.0001806683 +9 mux_tree_tapbuf_size3_2_sram[0]:9 0.001140052 +10 mux_tree_tapbuf_size3_2_sram[0]:10 0.00114282 +11 mux_tree_tapbuf_size3_2_sram[0]:11 0.0001024823 +12 mux_tree_tapbuf_size3_2_sram[0]:12 0.0001229102 +13 mux_tree_tapbuf_size3_2_sram[0]:13 9.716817e-05 +14 mux_tree_tapbuf_size3_2_sram[0]:14 0.0001054169 +15 mux_tree_tapbuf_size3_2_sram[0]:15 0.0005786852 +16 mux_tree_tapbuf_size3_2_sram[0]:16 0.0001214819 +17 mux_tree_tapbuf_size3_2_sram[0]:17 0.0001783669 +18 mux_tree_tapbuf_size3_2_sram[0]:18 0.0001783669 + +*RES +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_2_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_2_sram[0]:5 mux_tree_tapbuf_size3_2_sram[0]:4 0.008229911 +2 mux_tree_tapbuf_size3_2_sram[0]:6 mux_tree_tapbuf_size3_2_sram[0]:5 0.0045 +3 mux_tree_tapbuf_size3_2_sram[0]:4 mux_left_track_21\/mux_l1_in_1_:S 0.152 +4 mux_tree_tapbuf_size3_2_sram[0]:7 mux_left_track_21\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size3_2_sram[0]:14 mux_tree_tapbuf_size3_2_sram[0]:13 0.0008214285 +6 mux_tree_tapbuf_size3_2_sram[0]:14 mux_tree_tapbuf_size3_2_sram[0]:10 0.0002767857 +7 mux_tree_tapbuf_size3_2_sram[0]:15 mux_tree_tapbuf_size3_2_sram[0]:14 0.0045 +8 mux_tree_tapbuf_size3_2_sram[0]:15 mux_tree_tapbuf_size3_2_sram[0]:6 0.005424107 +9 mux_tree_tapbuf_size3_2_sram[0]:11 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +10 mux_tree_tapbuf_size3_2_sram[0]:17 mux_tree_tapbuf_size3_2_sram[0]:16 0.0045 +11 mux_tree_tapbuf_size3_2_sram[0]:16 mux_tree_tapbuf_size3_2_sram[0]:15 0.001477679 +12 mux_tree_tapbuf_size3_2_sram[0]:18 mux_tree_tapbuf_size3_2_sram[0]:17 0.002252232 +13 mux_tree_tapbuf_size3_2_sram[0]:12 mux_tree_tapbuf_size3_2_sram[0]:11 0.001042411 +14 mux_tree_tapbuf_size3_2_sram[0]:13 mux_tree_tapbuf_size3_2_sram[0]:12 0.0003035714 +15 mux_tree_tapbuf_size3_2_sram[0]:10 mux_tree_tapbuf_size3_2_sram[0]:9 0.01478572 +16 mux_tree_tapbuf_size3_2_sram[0]:9 mux_tree_tapbuf_size3_2_sram[0]:8 0.0003035715 +17 mux_tree_tapbuf_size3_2_sram[0]:8 mux_tree_tapbuf_size3_2_sram[0]:7 0.001698661 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.002453995 //LENGTH 17.710 LUMPCC 0 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 67.465 80.240 +*I mux_top_track_32\/mux_l2_in_0_:S I *L 0.00357 *C 68.900 77.815 +*I mux_top_track_32\/mux_l2_in_1_:S I *L 0.00357 *C 74.880 74.800 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 71.475 80.580 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 71.475 80.580 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 71.760 80.580 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 71.760 80.535 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 74.843 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 71.805 74.800 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 71.760 74.845 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 71.760 77.860 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 71.715 77.860 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 68.900 77.860 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 68.900 78.200 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 67.665 78.200 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 67.620 78.245 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 67.620 80.195 +*N mux_tree_tapbuf_size6_0_sram[1]:17 *C 67.620 80.240 +*N mux_tree_tapbuf_size6_0_sram[1]:18 *C 67.465 80.240 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_32\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 5.417303e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 5.457832e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 0.0001465971 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.000258274 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.000258274 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.0001675653 +10 mux_tree_tapbuf_size6_0_sram[1]:10 0.0003451644 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0002041914 +12 mux_tree_tapbuf_size6_0_sram[1]:12 0.0002357668 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0001550729 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.0001234975 +15 mux_tree_tapbuf_size6_0_sram[1]:15 0.0001697268 +16 mux_tree_tapbuf_size6_0_sram[1]:16 0.0001697268 +17 mux_tree_tapbuf_size6_0_sram[1]:17 5.568206e-05 +18 mux_tree_tapbuf_size6_0_sram[1]:18 5.170434e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:18 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0045 +2 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.002691964 +3 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:6 0.002388393 +4 mux_tree_tapbuf_size6_0_sram[1]:5 mux_tree_tapbuf_size6_0_sram[1]:4 0.000111413 +5 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0045 +6 mux_tree_tapbuf_size6_0_sram[1]:4 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +7 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.001102679 +8 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.0045 +9 mux_tree_tapbuf_size6_0_sram[1]:17 mux_tree_tapbuf_size6_0_sram[1]:16 0.0045 +10 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.001741072 +11 mux_tree_tapbuf_size6_0_sram[1]:18 mux_tree_tapbuf_size6_0_sram[1]:17 8.423912e-05 +12 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.002712054 +13 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:8 0.0045 +14 mux_tree_tapbuf_size6_0_sram[1]:7 mux_top_track_32\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size6_0_sram[1]:12 mux_top_track_32\/mux_l2_in_0_:S 0.152 +16 mux_tree_tapbuf_size6_0_sram[1]:12 mux_tree_tapbuf_size6_0_sram[1]:11 0.002513393 +17 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[1] 0.001863052 //LENGTH 13.270 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 20.545 93.500 +*I mux_left_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 19.680 91.120 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 23.630 93.500 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 24.940 90.780 +*N mux_tree_tapbuf_size7_3_sram[1]:4 *C 24.902 90.780 +*N mux_tree_tapbuf_size7_3_sram[1]:5 *C 23.630 93.500 +*N mux_tree_tapbuf_size7_3_sram[1]:6 *C 23.460 93.500 +*N mux_tree_tapbuf_size7_3_sram[1]:7 *C 23.460 93.455 +*N mux_tree_tapbuf_size7_3_sram[1]:8 *C 23.460 90.825 +*N mux_tree_tapbuf_size7_3_sram[1]:9 *C 23.460 90.780 +*N mux_tree_tapbuf_size7_3_sram[1]:10 *C 21.160 90.780 +*N mux_tree_tapbuf_size7_3_sram[1]:11 *C 19.718 91.120 +*N mux_tree_tapbuf_size7_3_sram[1]:12 *C 21.160 91.090 +*N mux_tree_tapbuf_size7_3_sram[1]:13 *C 21.160 91.165 +*N mux_tree_tapbuf_size7_3_sram[1]:14 *C 21.160 93.455 +*N mux_tree_tapbuf_size7_3_sram[1]:15 *C 21.115 93.500 +*N mux_tree_tapbuf_size7_3_sram[1]:16 *C 20.582 93.500 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_3_sram[1]:4 0.0001037749 +5 mux_tree_tapbuf_size7_3_sram[1]:5 6.841224e-05 +6 mux_tree_tapbuf_size7_3_sram[1]:6 6.656069e-05 +7 mux_tree_tapbuf_size7_3_sram[1]:7 0.0001775376 +8 mux_tree_tapbuf_size7_3_sram[1]:8 0.0001775376 +9 mux_tree_tapbuf_size7_3_sram[1]:9 0.0003073295 +10 mux_tree_tapbuf_size7_3_sram[1]:10 0.0001960474 +11 mux_tree_tapbuf_size7_3_sram[1]:11 0.0001293253 +12 mux_tree_tapbuf_size7_3_sram[1]:12 0.0001584804 +13 mux_tree_tapbuf_size7_3_sram[1]:13 0.0001624778 +14 mux_tree_tapbuf_size7_3_sram[1]:14 0.0001624778 +15 mux_tree_tapbuf_size7_3_sram[1]:15 7.454527e-05 +16 mux_tree_tapbuf_size7_3_sram[1]:16 7.454527e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_3_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_3_sram[1]:5 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_3_sram[1]:6 mux_tree_tapbuf_size7_3_sram[1]:5 9.239132e-05 +3 mux_tree_tapbuf_size7_3_sram[1]:7 mux_tree_tapbuf_size7_3_sram[1]:6 0.0045 +4 mux_tree_tapbuf_size7_3_sram[1]:9 mux_tree_tapbuf_size7_3_sram[1]:8 0.0045 +5 mux_tree_tapbuf_size7_3_sram[1]:9 mux_tree_tapbuf_size7_3_sram[1]:4 0.001287946 +6 mux_tree_tapbuf_size7_3_sram[1]:8 mux_tree_tapbuf_size7_3_sram[1]:7 0.002348214 +7 mux_tree_tapbuf_size7_3_sram[1]:12 mux_tree_tapbuf_size7_3_sram[1]:11 0.001287946 +8 mux_tree_tapbuf_size7_3_sram[1]:12 mux_tree_tapbuf_size7_3_sram[1]:10 0.0002767857 +9 mux_tree_tapbuf_size7_3_sram[1]:13 mux_tree_tapbuf_size7_3_sram[1]:12 0.0045 +10 mux_tree_tapbuf_size7_3_sram[1]:15 mux_tree_tapbuf_size7_3_sram[1]:14 0.0045 +11 mux_tree_tapbuf_size7_3_sram[1]:14 mux_tree_tapbuf_size7_3_sram[1]:13 0.002044643 +12 mux_tree_tapbuf_size7_3_sram[1]:16 mux_tree_tapbuf_size7_3_sram[1]:15 0.0004754465 +13 mux_tree_tapbuf_size7_3_sram[1]:11 mux_left_track_1\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size7_3_sram[1]:4 mux_left_track_1\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size7_3_sram[1]:10 mux_tree_tapbuf_size7_3_sram[1]:9 0.002053571 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[1] 0.00658425 //LENGTH 45.080 LUMPCC 0.0020804 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.485 110.160 +*I mux_top_track_2\/mux_l2_in_1_:S I *L 0.00357 *C 29.800 99.280 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 25.475 96.900 +*I mux_top_track_2\/mux_l2_in_3_:S I *L 0.00357 *C 31.640 90.830 +*I mux_top_track_2\/mux_l2_in_2_:S I *L 0.00357 *C 33.940 88.400 +*I mux_top_track_2\/mux_l2_in_0_:S I *L 0.00357 *C 32.540 105.060 +*N mux_tree_tapbuf_size8_0_sram[1]:6 *C 32.503 105.060 +*N mux_tree_tapbuf_size8_0_sram[1]:7 *C 31.785 105.060 +*N mux_tree_tapbuf_size8_0_sram[1]:8 *C 31.710 105.090 +*N mux_tree_tapbuf_size8_0_sram[1]:9 *C 33.903 88.400 +*N mux_tree_tapbuf_size8_0_sram[1]:10 *C 31.785 88.400 +*N mux_tree_tapbuf_size8_0_sram[1]:11 *C 31.740 88.445 +*N mux_tree_tapbuf_size8_0_sram[1]:12 *C 31.640 90.830 +*N mux_tree_tapbuf_size8_0_sram[1]:13 *C 31.740 91.120 +*N mux_tree_tapbuf_size8_0_sram[1]:14 *C 31.740 91.120 +*N mux_tree_tapbuf_size8_0_sram[1]:15 *C 31.740 93.840 +*N mux_tree_tapbuf_size8_0_sram[1]:16 *C 31.280 93.840 +*N mux_tree_tapbuf_size8_0_sram[1]:17 *C 25.475 96.900 +*N mux_tree_tapbuf_size8_0_sram[1]:18 *C 25.760 96.900 +*N mux_tree_tapbuf_size8_0_sram[1]:19 *C 25.760 96.945 +*N mux_tree_tapbuf_size8_0_sram[1]:20 *C 25.760 99.235 +*N mux_tree_tapbuf_size8_0_sram[1]:21 *C 25.805 99.280 +*N mux_tree_tapbuf_size8_0_sram[1]:22 *C 29.395 99.280 +*N mux_tree_tapbuf_size8_0_sram[1]:23 *C 29.838 99.280 +*N mux_tree_tapbuf_size8_0_sram[1]:24 *C 31.235 99.280 +*N mux_tree_tapbuf_size8_0_sram[1]:25 *C 31.280 99.280 +*N mux_tree_tapbuf_size8_0_sram[1]:26 *C 31.280 105.400 +*N mux_tree_tapbuf_size8_0_sram[1]:27 *C 31.695 105.400 +*N mux_tree_tapbuf_size8_0_sram[1]:28 *C 31.740 110.103 +*N mux_tree_tapbuf_size8_0_sram[1]:29 *C 31.748 110.160 +*N mux_tree_tapbuf_size8_0_sram[1]:30 *C 38.633 110.160 +*N mux_tree_tapbuf_size8_0_sram[1]:31 *C 38.640 110.160 +*N mux_tree_tapbuf_size8_0_sram[1]:32 *C 38.640 110.160 +*N mux_tree_tapbuf_size8_0_sram[1]:33 *C 38.485 110.160 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_2\/mux_l2_in_1_:S 1e-06 +2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_2\/mux_l2_in_3_:S 1e-06 +4 mux_top_track_2\/mux_l2_in_2_:S 1e-06 +5 mux_top_track_2\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size8_0_sram[1]:6 6.438434e-05 +7 mux_tree_tapbuf_size8_0_sram[1]:7 6.438434e-05 +8 mux_tree_tapbuf_size8_0_sram[1]:8 3.481318e-05 +9 mux_tree_tapbuf_size8_0_sram[1]:9 0.0001727611 +10 mux_tree_tapbuf_size8_0_sram[1]:10 0.0001727611 +11 mux_tree_tapbuf_size8_0_sram[1]:11 0.0001628542 +12 mux_tree_tapbuf_size8_0_sram[1]:12 6.451679e-05 +13 mux_tree_tapbuf_size8_0_sram[1]:13 6.941509e-05 +14 mux_tree_tapbuf_size8_0_sram[1]:14 0.0003513895 +15 mux_tree_tapbuf_size8_0_sram[1]:15 0.0001569386 +16 mux_tree_tapbuf_size8_0_sram[1]:16 0.0002539261 +17 mux_tree_tapbuf_size8_0_sram[1]:17 5.282716e-05 +18 mux_tree_tapbuf_size8_0_sram[1]:18 5.65775e-05 +19 mux_tree_tapbuf_size8_0_sram[1]:19 0.0001407788 +20 mux_tree_tapbuf_size8_0_sram[1]:20 0.0001407788 +21 mux_tree_tapbuf_size8_0_sram[1]:21 0.0001160408 +22 mux_tree_tapbuf_size8_0_sram[1]:22 0.0001456682 +23 mux_tree_tapbuf_size8_0_sram[1]:23 0.0001265742 +24 mux_tree_tapbuf_size8_0_sram[1]:24 9.694682e-05 +25 mux_tree_tapbuf_size8_0_sram[1]:25 0.0004833924 +26 mux_tree_tapbuf_size8_0_sram[1]:26 0.0002269862 +27 mux_tree_tapbuf_size8_0_sram[1]:27 0.0003313647 +28 mux_tree_tapbuf_size8_0_sram[1]:28 0.0002661321 +29 mux_tree_tapbuf_size8_0_sram[1]:29 0.0003070352 +30 mux_tree_tapbuf_size8_0_sram[1]:30 0.0003070352 +31 mux_tree_tapbuf_size8_0_sram[1]:31 3.488226e-05 +32 mux_tree_tapbuf_size8_0_sram[1]:32 4.942981e-05 +33 mux_tree_tapbuf_size8_0_sram[1]:33 4.725565e-05 +34 mux_tree_tapbuf_size8_0_sram[1]:24 top_left_grid_pin_41_[0]:11 4.139449e-06 +35 mux_tree_tapbuf_size8_0_sram[1]:23 top_left_grid_pin_41_[0]:10 4.139449e-06 +36 mux_tree_tapbuf_size8_0_sram[1]:23 top_left_grid_pin_41_[0]:11 7.384707e-06 +37 mux_tree_tapbuf_size8_0_sram[1]:29 top_left_grid_pin_41_[0]:17 0.0003903395 +38 mux_tree_tapbuf_size8_0_sram[1]:30 top_left_grid_pin_41_[0]:16 0.0003903395 +39 mux_tree_tapbuf_size8_0_sram[1]:21 top_left_grid_pin_41_[0]:5 2.794115e-05 +40 mux_tree_tapbuf_size8_0_sram[1]:21 top_left_grid_pin_41_[0]:10 1.129405e-05 +41 mux_tree_tapbuf_size8_0_sram[1]:20 top_left_grid_pin_41_[0]:9 1.421999e-06 +42 mux_tree_tapbuf_size8_0_sram[1]:19 top_left_grid_pin_41_[0]:8 1.421999e-06 +43 mux_tree_tapbuf_size8_0_sram[1]:22 top_left_grid_pin_41_[0]:4 2.794115e-05 +44 mux_tree_tapbuf_size8_0_sram[1]:22 top_left_grid_pin_41_[0]:10 7.384707e-06 +45 mux_tree_tapbuf_size8_0_sram[1]:22 top_left_grid_pin_41_[0]:11 1.129405e-05 +46 mux_tree_tapbuf_size8_0_sram[1]:16 top_left_grid_pin_41_[0]:7 1.35923e-05 +47 mux_tree_tapbuf_size8_0_sram[1]:15 top_left_grid_pin_41_[0]:6 1.35923e-05 +48 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:20 3.226752e-05 +49 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:21 0.0001622405 +50 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:22 1.27373e-05 +51 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:19 3.226752e-05 +52 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:20 2.235292e-05 +53 mux_tree_tapbuf_size8_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:21 3.963846e-06 +54 mux_tree_tapbuf_size8_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:22 4.440521e-05 +55 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:19 0.0001422815 +56 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:19 2.235292e-05 +57 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:20 0.0001422815 +58 mux_tree_tapbuf_size8_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:21 1.27373e-05 +59 mux_tree_tapbuf_size8_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:22 0.0001622405 +60 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:21 4.440521e-05 +61 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:22 3.963846e-06 +62 mux_tree_tapbuf_size8_0_sram[1]:24 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.035621e-06 +63 mux_tree_tapbuf_size8_0_sram[1]:25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.012005e-05 +64 mux_tree_tapbuf_size8_0_sram[1]:23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 9.035621e-06 +65 mux_tree_tapbuf_size8_0_sram[1]:26 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 6.012005e-05 +66 mux_tree_tapbuf_size8_0_sram[1]:25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.719666e-05 +67 mux_tree_tapbuf_size8_0_sram[1]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.74855e-05 +68 mux_tree_tapbuf_size8_0_sram[1]:16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.719666e-05 +69 mux_tree_tapbuf_size8_0_sram[1]:15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 1.74855e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_0_sram[1]:33 0.152 +1 mux_tree_tapbuf_size8_0_sram[1]:24 mux_tree_tapbuf_size8_0_sram[1]:23 0.001247768 +2 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:24 0.0045 +3 mux_tree_tapbuf_size8_0_sram[1]:25 mux_tree_tapbuf_size8_0_sram[1]:16 0.004857143 +4 mux_tree_tapbuf_size8_0_sram[1]:23 mux_top_track_2\/mux_l2_in_1_:S 0.152 +5 mux_tree_tapbuf_size8_0_sram[1]:23 mux_tree_tapbuf_size8_0_sram[1]:22 0.0002404892 +6 mux_tree_tapbuf_size8_0_sram[1]:10 mux_tree_tapbuf_size8_0_sram[1]:9 0.001890625 +7 mux_tree_tapbuf_size8_0_sram[1]:11 mux_tree_tapbuf_size8_0_sram[1]:10 0.0045 +8 mux_tree_tapbuf_size8_0_sram[1]:9 mux_top_track_2\/mux_l2_in_2_:S 0.152 +9 mux_tree_tapbuf_size8_0_sram[1]:7 mux_tree_tapbuf_size8_0_sram[1]:6 0.000640625 +10 mux_tree_tapbuf_size8_0_sram[1]:8 mux_tree_tapbuf_size8_0_sram[1]:7 0.0045 +11 mux_tree_tapbuf_size8_0_sram[1]:6 mux_top_track_2\/mux_l2_in_0_:S 0.152 +12 mux_tree_tapbuf_size8_0_sram[1]:13 mux_tree_tapbuf_size8_0_sram[1]:12 0.000125 +13 mux_tree_tapbuf_size8_0_sram[1]:14 mux_tree_tapbuf_size8_0_sram[1]:13 0.0045 +14 mux_tree_tapbuf_size8_0_sram[1]:14 mux_tree_tapbuf_size8_0_sram[1]:11 0.002388393 +15 mux_tree_tapbuf_size8_0_sram[1]:12 mux_top_track_2\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size8_0_sram[1]:28 mux_tree_tapbuf_size8_0_sram[1]:27 0.004198661 +17 mux_tree_tapbuf_size8_0_sram[1]:29 mux_tree_tapbuf_size8_0_sram[1]:28 0.00341 +18 mux_tree_tapbuf_size8_0_sram[1]:31 mux_tree_tapbuf_size8_0_sram[1]:30 0.00341 +19 mux_tree_tapbuf_size8_0_sram[1]:30 mux_tree_tapbuf_size8_0_sram[1]:29 0.00107865 +20 mux_tree_tapbuf_size8_0_sram[1]:32 mux_tree_tapbuf_size8_0_sram[1]:31 0.0045 +21 mux_tree_tapbuf_size8_0_sram[1]:33 mux_tree_tapbuf_size8_0_sram[1]:32 8.423914e-05 +22 mux_tree_tapbuf_size8_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:20 0.0045 +23 mux_tree_tapbuf_size8_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:19 0.002044643 +24 mux_tree_tapbuf_size8_0_sram[1]:18 mux_tree_tapbuf_size8_0_sram[1]:17 0.0001548913 +25 mux_tree_tapbuf_size8_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:18 0.0045 +26 mux_tree_tapbuf_size8_0_sram[1]:17 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +27 mux_tree_tapbuf_size8_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:21 0.003205357 +28 mux_tree_tapbuf_size8_0_sram[1]:16 mux_tree_tapbuf_size8_0_sram[1]:15 0.0004107143 +29 mux_tree_tapbuf_size8_0_sram[1]:15 mux_tree_tapbuf_size8_0_sram[1]:14 0.002428572 +30 mux_tree_tapbuf_size8_0_sram[1]:26 mux_tree_tapbuf_size8_0_sram[1]:25 0.005464286 +31 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size8_0_sram[1]:26 0.0003705357 +32 mux_tree_tapbuf_size8_0_sram[1]:27 mux_tree_tapbuf_size8_0_sram[1]:8 0.00019375 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001064957 //LENGTH 7.605 LUMPCC 0.0003285133 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 38.925 6.460 +*I mux_bottom_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 42.880 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 42.843 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 42.365 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 42.320 9.135 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 42.320 6.505 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 42.275 6.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 38.962 6.460 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.478654e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.478654e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0001752457 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001752457 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001371894 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001371894 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 bottom_left_grid_pin_37_[0]:13 0.0001213849 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 bottom_left_grid_pin_37_[0]:14 0.0001213849 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.287174e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.287174e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0004263393 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.002348215 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.002957589 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002291435 //LENGTH 15.280 LUMPCC 0.000817191 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_1_:X O *L 0 *C 46.285 47.260 +*I mux_bottom_track_17\/mux_l3_in_0_:A0 I *L 0.001631 *C 52.155 39.100 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 52.155 39.100 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 51.980 39.100 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 51.980 39.145 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 51.980 40.742 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 51.973 40.800 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 46.468 40.800 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 46.460 40.858 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 46.460 47.215 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 46.460 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 46.285 47.260 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.007524e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.201655e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001055649 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001055649 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000303626 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000303626 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002092807 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0002092807 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 6.728796e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 6.592141e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 prog_clk[0]:204 5.937315e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 prog_clk[0]:208 5.937315e-05 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chanx_left_in[8]:6 3.204206e-07 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chanx_left_in[8]:5 3.204206e-07 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chanx_left_in[8]:7 0.0001168848 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chanx_left_in[8]:12 0.0001168848 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chanx_left_in[15]:5 0.0001740551 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chanx_left_in[15]:6 0.0001740551 +20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size7_2_sram[1]:8 4.72169e-06 +21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size7_2_sram[1]:10 5.324031e-05 +22 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size7_2_sram[1]:6 5.324031e-05 +23 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size7_2_sram[1]:9 4.72169e-06 + +*RES +0 mux_bottom_track_17\/mux_l2_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.51087e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001426339 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0008624499 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.005676339 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:10 9.510871e-05 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008690134 //LENGTH 6.160 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_1_:X O *L 0 *C 72.965 21.080 +*I mux_bottom_track_25\/mux_l3_in_0_:A0 I *L 0.001631 *C 78.835 21.080 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 78.797 21.080 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 73.002 21.080 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004335067 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0004335067 + +*RES +0 mux_bottom_track_25\/mux_l2_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.005174107 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0] 0.007486108 //LENGTH 60.610 LUMPCC 0.0009428285 DR + +*CONN +*I mux_bottom_track_3\/mux_l4_in_0_:X O *L 0 *C 28.345 39.440 +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 47.640 6.625 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 47.640 6.625 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 48.255 6.800 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 48.300 6.845 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 48.300 13.543 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 48.308 13.600 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 51.053 13.600 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 51.060 13.658 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 51.060 39.055 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 *C 51.015 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 *C 46.000 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 *C 46.000 39.440 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 *C 28.383 39.440 + +*CAP +0 mux_bottom_track_3\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.000115919 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.589735e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0003902322 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0003902322 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0002287792 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0002287792 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.001355959 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.001355959 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0002602272 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.000284081 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.0009395335 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.0009156798 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 bottom_left_grid_pin_34_[0]:6 0.0002136163 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 bottom_left_grid_pin_34_[0]:5 0.0002136163 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001784397 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001784397 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.362303e-05 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 6.573521e-05 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 1.362303e-05 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.573521e-05 + +*RES +0 mux_bottom_track_3\/mux_l4_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.01572991 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.02267634 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.00341 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.00043005 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.005979911 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.00341 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0005491071 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0003035715 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.004477679 + +*END + +*D_NET ropt_net_162 0.001369437 //LENGTH 9.435 LUMPCC 0.0003613394 DR + +*CONN +*I FTB_2__1:X O *L 0 *C 71.300 11.560 +*I ropt_mt_inst_787:A I *L 0.001766 *C 65.320 9.520 +*N ropt_net_162:2 *C 65.320 9.520 +*N ropt_net_162:3 *C 65.320 9.180 +*N ropt_net_162:4 *C 71.255 9.180 +*N ropt_net_162:5 *C 71.300 9.225 +*N ropt_net_162:6 *C 71.300 11.515 +*N ropt_net_162:7 *C 71.300 11.560 + +*CAP +0 FTB_2__1:X 1e-06 +1 ropt_mt_inst_787:A 1e-06 +2 ropt_net_162:2 5.759151e-05 +3 ropt_net_162:3 0.0003495351 +4 ropt_net_162:4 0.0003212862 +5 ropt_net_162:5 0.0001217978 +6 ropt_net_162:6 0.0001217978 +7 ropt_net_162:7 3.408908e-05 +8 ropt_net_162:4 chany_top_in[5]:5 0.0001186194 +9 ropt_net_162:3 chany_top_in[5]:6 0.0001186194 +10 ropt_net_162:6 ropt_net_158:5 2.619084e-05 +11 ropt_net_162:4 ropt_net_158:2 3.585951e-05 +12 ropt_net_162:5 ropt_net_158:4 2.619084e-05 +13 ropt_net_162:3 ropt_net_158:3 3.585951e-05 + +*RES +0 FTB_2__1:X ropt_net_162:7 0.152 +1 ropt_net_162:7 ropt_net_162:6 0.0045 +2 ropt_net_162:6 ropt_net_162:5 0.002044643 +3 ropt_net_162:4 ropt_net_162:3 0.005299107 +4 ropt_net_162:5 ropt_net_162:4 0.0045 +5 ropt_net_162:2 ropt_mt_inst_787:A 0.152 +6 ropt_net_162:3 ropt_net_162:2 0.0003035715 + +*END + +*D_NET ropt_net_177 0.001647643 //LENGTH 12.590 LUMPCC 0.0001516147 DR + +*CONN +*I FTB_29__28:X O *L 0 *C 44.160 125.800 +*I ropt_mt_inst_803:A I *L 0.001766 *C 51.060 121.040 +*N ropt_net_177:2 *C 51.023 121.040 +*N ropt_net_177:3 *C 50.645 121.040 +*N ropt_net_177:4 *C 50.600 121.085 +*N ropt_net_177:5 *C 50.600 125.755 +*N ropt_net_177:6 *C 50.555 125.800 +*N ropt_net_177:7 *C 44.198 125.800 + +*CAP +0 FTB_29__28:X 1e-06 +1 ropt_mt_inst_803:A 1e-06 +2 ropt_net_177:2 6.120631e-05 +3 ropt_net_177:3 6.120631e-05 +4 ropt_net_177:4 0.0002502894 +5 ropt_net_177:5 0.0002502894 +6 ropt_net_177:6 0.0004355182 +7 ropt_net_177:7 0.0004355182 +8 ropt_net_177:4 chany_top_out[7]:6 6.69349e-05 +9 ropt_net_177:6 chany_top_out[7]:5 8.872472e-06 +10 ropt_net_177:5 chany_top_out[7]:5 6.69349e-05 +11 ropt_net_177:7 chany_top_out[7]:4 8.872472e-06 + +*RES +0 FTB_29__28:X ropt_net_177:7 0.152 +1 ropt_net_177:2 ropt_mt_inst_803:A 0.152 +2 ropt_net_177:3 ropt_net_177:2 0.0003370536 +3 ropt_net_177:4 ropt_net_177:3 0.0045 +4 ropt_net_177:6 ropt_net_177:5 0.0045 +5 ropt_net_177:5 ropt_net_177:4 0.004169643 +6 ropt_net_177:7 ropt_net_177:6 0.005676339 + +*END + +*D_NET ropt_net_155 0.002257394 //LENGTH 18.790 LUMPCC 0.0001197062 DR + +*CONN +*I BUFT_RR_81:X O *L 0 *C 65.780 110.500 +*I ropt_mt_inst_780:A I *L 0.001766 *C 61.180 123.760 +*N ropt_net_155:2 *C 61.218 123.760 +*N ropt_net_155:3 *C 62.055 123.760 +*N ropt_net_155:4 *C 62.100 123.715 +*N ropt_net_155:5 *C 62.100 110.545 +*N ropt_net_155:6 *C 62.145 110.500 +*N ropt_net_155:7 *C 65.743 110.500 + +*CAP +0 BUFT_RR_81:X 1e-06 +1 ropt_mt_inst_780:A 1e-06 +2 ropt_net_155:2 0.0001162653 +3 ropt_net_155:3 0.0001162653 +4 ropt_net_155:4 0.0007532485 +5 ropt_net_155:5 0.0007532485 +6 ropt_net_155:6 0.0001983299 +7 ropt_net_155:7 0.0001983299 +8 ropt_net_155:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 5.985308e-05 +9 ropt_net_155:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 5.985308e-05 + +*RES +0 BUFT_RR_81:X ropt_net_155:7 0.152 +1 ropt_net_155:7 ropt_net_155:6 0.003212054 +2 ropt_net_155:6 ropt_net_155:5 0.0045 +3 ropt_net_155:5 ropt_net_155:4 0.01175893 +4 ropt_net_155:3 ropt_net_155:2 0.0007477679 +5 ropt_net_155:4 ropt_net_155:3 0.0045 +6 ropt_net_155:2 ropt_mt_inst_780:A 0.152 + +*END + +*D_NET chany_top_out[11] 0.0009606755 //LENGTH 8.475 LUMPCC 0.0002183733 DR + +*CONN +*I ropt_mt_inst_833:X O *L 0 *C 94.300 121.720 +*P chany_top_out[11] O *L 0.7423 *C 93.840 129.270 +*N chany_top_out[11]:2 *C 93.840 121.765 +*N chany_top_out[11]:3 *C 93.885 121.720 +*N chany_top_out[11]:4 *C 94.263 121.720 + +*CAP +0 ropt_mt_inst_833:X 1e-06 +1 chany_top_out[11] 0.0003223622 +2 chany_top_out[11]:2 0.0003223622 +3 chany_top_out[11]:3 4.828885e-05 +4 chany_top_out[11]:4 4.828885e-05 +5 chany_top_out[11] ropt_net_199:4 4.011357e-05 +6 chany_top_out[11]:2 ropt_net_199:3 4.011357e-05 +7 chany_top_out[11] ropt_net_160:6 6.907311e-05 +8 chany_top_out[11]:2 ropt_net_160:7 6.907311e-05 + +*RES +0 ropt_mt_inst_833:X chany_top_out[11]:4 0.152 +1 chany_top_out[11]:4 chany_top_out[11]:3 0.0003370536 +2 chany_top_out[11]:3 chany_top_out[11]:2 0.0045 +3 chany_top_out[11]:2 chany_top_out[11] 0.006700894 + +*END + +*D_NET chany_top_in[4] 0.02763731 //LENGTH 204.365 LUMPCC 0.008893713 DR + +*CONN +*P chany_top_in[4] I *L 0.29796 *C 51.980 129.270 +*I mux_left_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 34.500 79.900 +*I mux_bottom_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 32.200 34.340 +*I FTB_4__3:A I *L 0.001776 *C 67.160 12.240 +*N chany_top_in[4]:4 *C 67.198 12.240 +*N chany_top_in[4]:5 *C 67.575 12.240 +*N chany_top_in[4]:6 *C 67.620 12.195 +*N chany_top_in[4]:7 *C 67.620 9.578 +*N chany_top_in[4]:8 *C 67.612 9.520 +*N chany_top_in[4]:9 *C 47.860 9.520 +*N chany_top_in[4]:10 *C 47.840 9.527 +*N chany_top_in[4]:11 *C 47.840 56.433 +*N chany_top_in[4]:12 *C 47.820 56.440 +*N chany_top_in[4]:13 *C 32.200 34.340 +*N chany_top_in[4]:14 *C 32.200 34.385 +*N chany_top_in[4]:15 *C 32.200 36.663 +*N chany_top_in[4]:16 *C 32.193 36.720 +*N chany_top_in[4]:17 *C 31.300 36.720 +*N chany_top_in[4]:18 *C 31.280 36.727 +*N chany_top_in[4]:19 *C 31.280 56.433 +*N chany_top_in[4]:20 *C 31.300 56.440 +*N chany_top_in[4]:21 *C 45.080 56.440 +*N chany_top_in[4]:22 *C 45.080 56.448 +*N chany_top_in[4]:23 *C 34.538 79.900 +*N chany_top_in[4]:24 *C 37.675 79.900 +*N chany_top_in[4]:25 *C 37.720 79.900 +*N chany_top_in[4]:26 *C 37.720 79.560 +*N chany_top_in[4]:27 *C 37.727 79.560 +*N chany_top_in[4]:28 *C 45.060 79.560 +*N chany_top_in[4]:29 *C 45.080 79.560 +*N chany_top_in[4]:30 *C 45.080 127.153 +*N chany_top_in[4]:31 *C 45.100 127.160 +*N chany_top_in[4]:32 *C 51.973 127.160 +*N chany_top_in[4]:33 *C 51.980 127.218 + +*CAP +0 chany_top_in[4] 0.0001319768 +1 mux_left_track_3\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:A1 1e-06 +3 FTB_4__3:A 1e-06 +4 chany_top_in[4]:4 4.866572e-05 +5 chany_top_in[4]:5 4.866572e-05 +6 chany_top_in[4]:6 0.0001867156 +7 chany_top_in[4]:7 0.0001867156 +8 chany_top_in[4]:8 0.001251511 +9 chany_top_in[4]:9 0.001251511 +10 chany_top_in[4]:10 0.001088933 +11 chany_top_in[4]:11 0.001088933 +12 chany_top_in[4]:12 0.0001291724 +13 chany_top_in[4]:13 3.805081e-05 +14 chany_top_in[4]:14 0.0001884166 +15 chany_top_in[4]:15 0.0001884166 +16 chany_top_in[4]:16 0.0001496454 +17 chany_top_in[4]:17 0.0001496454 +18 chany_top_in[4]:18 0.001214586 +19 chany_top_in[4]:19 0.001214586 +20 chany_top_in[4]:20 0.0007230724 +21 chany_top_in[4]:21 0.0008522446 +22 chany_top_in[4]:22 0.000791165 +23 chany_top_in[4]:23 0.0002508361 +24 chany_top_in[4]:24 0.0002508361 +25 chany_top_in[4]:25 5.375618e-05 +26 chany_top_in[4]:26 5.794691e-05 +27 chany_top_in[4]:27 0.0006068704 +28 chany_top_in[4]:28 0.0006068704 +29 chany_top_in[4]:29 0.00283401 +30 chany_top_in[4]:30 0.002042844 +31 chany_top_in[4]:31 0.0004910109 +32 chany_top_in[4]:32 0.0004910109 +33 chany_top_in[4]:33 0.0001319768 +34 chany_top_in[4]:31 chany_top_in[5]:27 4.684005e-06 +35 chany_top_in[4]:30 chany_top_in[5]:26 4.893961e-06 +36 chany_top_in[4]:30 chany_top_in[5]:25 0.0001044761 +37 chany_top_in[4]:32 chany_top_in[5]:28 4.684005e-06 +38 chany_top_in[4]:29 chany_top_in[5]:24 0.0001084247 +39 chany_top_in[4]:29 chany_top_in[5]:18 4.874269e-06 +40 chany_top_in[4]:29 chany_top_in[5]:25 4.893961e-06 +41 chany_top_in[4]:22 chany_top_in[5]:17 4.874269e-06 +42 chany_top_in[4]:22 chany_top_in[5]:18 3.94865e-06 +43 chany_top_in[4]:11 chany_top_in[5]:18 0.0009611454 +44 chany_top_in[4]:9 chany_top_in[5]:16 2.073945e-05 +45 chany_top_in[4]:10 chany_top_in[5]:17 0.0009611454 +46 chany_top_in[4]:7 chany_top_in[5]:8 7.086463e-07 +47 chany_top_in[4]:8 chany_top_in[5]:4 2.073945e-05 +48 chany_top_in[4]:6 chany_top_in[5]:7 7.086463e-07 +49 chany_top_in[4]:20 chany_top_in[14]:8 3.96809e-05 +50 chany_top_in[4]:31 chany_top_in[14]:26 4.515351e-05 +51 chany_top_in[4]:30 chany_top_in[14]:25 4.701439e-06 +52 chany_top_in[4]:32 chany_top_in[14]:27 4.515351e-05 +53 chany_top_in[4]:29 chany_top_in[14]:20 9.204263e-05 +54 chany_top_in[4]:29 chany_top_in[14]:24 4.701439e-06 +55 chany_top_in[4]:21 chany_top_in[14]:21 6.199253e-05 +56 chany_top_in[4]:21 chany_top_in[14]:8 1.011167e-05 +57 chany_top_in[4]:22 chany_top_in[14]:19 9.204263e-05 +58 chany_top_in[4]:12 chany_top_in[14]:21 1.011167e-05 +59 chany_top_in[4]:12 chany_top_in[14]:22 2.231163e-05 +60 chany_top_in[4]:11 chany_top_in[14]:20 0.0009900054 +61 chany_top_in[4]:10 chany_top_in[14]:19 0.0009900054 +62 chany_top_in[4] chany_top_in[15] 5.390852e-06 +63 chany_top_in[4]:20 chany_top_in[15]:13 0.0002825469 +64 chany_top_in[4]:33 chany_top_in[15]:20 5.390852e-06 +65 chany_top_in[4]:21 chany_top_in[15]:13 5.771182e-05 +66 chany_top_in[4]:21 chany_top_in[15]:14 0.0002825469 +67 chany_top_in[4]:12 chany_top_in[15]:14 5.771182e-05 +68 chany_top_in[4]:20 chany_bottom_in[14]:8 6.077243e-06 +69 chany_top_in[4]:30 chany_bottom_in[14]:25 6.480583e-06 +70 chany_top_in[4]:30 chany_bottom_in[14]:27 0.0002372958 +71 chany_top_in[4]:29 chany_bottom_in[14]:28 0.0002372958 +72 chany_top_in[4]:29 chany_bottom_in[14]:27 0.0002366229 +73 chany_top_in[4]:29 chany_bottom_in[14]:26 6.480583e-06 +74 chany_top_in[4]:21 chany_bottom_in[14]:29 6.077243e-06 +75 chany_top_in[4]:22 chany_bottom_in[14]:28 0.0002366229 +76 chany_top_in[4]:9 bottom_left_grid_pin_35_[0]:15 0.0006206161 +77 chany_top_in[4]:8 bottom_left_grid_pin_35_[0]:11 0.0006206161 +78 chany_top_in[4]:20 chanx_left_in[12]:8 9.95198e-07 +79 chany_top_in[4]:30 chanx_left_in[12]:11 0.000332031 +80 chany_top_in[4]:29 chanx_left_in[12]:11 0.0003516096 +81 chany_top_in[4]:29 chanx_left_in[12]:10 0.000332031 +82 chany_top_in[4]:21 chanx_left_in[12]:9 9.95198e-07 +83 chany_top_in[4]:22 chanx_left_in[12]:10 0.0003516096 + +*RES +0 chany_top_in[4] chany_top_in[4]:33 0.001832589 +1 chany_top_in[4]:20 chany_top_in[4]:19 0.00341 +2 chany_top_in[4]:19 chany_top_in[4]:18 0.003087116 +3 chany_top_in[4]:17 chany_top_in[4]:16 0.000139825 +4 chany_top_in[4]:18 chany_top_in[4]:17 0.00341 +5 chany_top_in[4]:15 chany_top_in[4]:14 0.002033482 +6 chany_top_in[4]:16 chany_top_in[4]:15 0.00341 +7 chany_top_in[4]:13 mux_bottom_track_3\/mux_l1_in_0_:A1 0.152 +8 chany_top_in[4]:14 chany_top_in[4]:13 0.0045 +9 chany_top_in[4]:31 chany_top_in[4]:30 0.00341 +10 chany_top_in[4]:30 chany_top_in[4]:29 0.007456158 +11 chany_top_in[4]:33 chany_top_in[4]:32 0.00341 +12 chany_top_in[4]:32 chany_top_in[4]:31 0.001076692 +13 chany_top_in[4]:28 chany_top_in[4]:27 0.001148758 +14 chany_top_in[4]:29 chany_top_in[4]:28 0.00341 +15 chany_top_in[4]:29 chany_top_in[4]:22 0.003620958 +16 chany_top_in[4]:26 chany_top_in[4]:25 0.0001634615 +17 chany_top_in[4]:27 chany_top_in[4]:26 0.00341 +18 chany_top_in[4]:24 chany_top_in[4]:23 0.00280134 +19 chany_top_in[4]:25 chany_top_in[4]:24 0.0045 +20 chany_top_in[4]:23 mux_left_track_3\/mux_l1_in_0_:A1 0.152 +21 chany_top_in[4]:21 chany_top_in[4]:20 0.002158867 +22 chany_top_in[4]:21 chany_top_in[4]:12 0.0004292666 +23 chany_top_in[4]:22 chany_top_in[4]:21 0.00341 +24 chany_top_in[4]:12 chany_top_in[4]:11 0.00341 +25 chany_top_in[4]:11 chany_top_in[4]:10 0.007348449 +26 chany_top_in[4]:9 chany_top_in[4]:8 0.003094558 +27 chany_top_in[4]:10 chany_top_in[4]:9 0.00341 +28 chany_top_in[4]:7 chany_top_in[4]:6 0.002337054 +29 chany_top_in[4]:8 chany_top_in[4]:7 0.00341 +30 chany_top_in[4]:5 chany_top_in[4]:4 0.0003370536 +31 chany_top_in[4]:6 chany_top_in[4]:5 0.0045 +32 chany_top_in[4]:4 FTB_4__3:A 0.152 + +*END + +*D_NET chany_bottom_in[14] 0.02230027 //LENGTH 172.000 LUMPCC 0.006583408 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 66.240 1.290 +*I mux_top_track_4\/mux_l1_in_5_:A1 I *L 0.00198 *C 47.840 99.620 +*I FTB_29__28:A I *L 0.001776 *C 46.460 126.480 +*I mux_left_track_19\/mux_l1_in_0_:A0 I *L 0.001631 *C 37.550 59.160 +*N chany_bottom_in[14]:4 *C 37.550 59.160 +*N chany_bottom_in[14]:5 *C 37.720 59.160 +*N chany_bottom_in[14]:6 *C 37.720 59.205 +*N chany_bottom_in[14]:7 *C 37.720 60.463 +*N chany_bottom_in[14]:8 *C 37.727 60.520 +*N chany_bottom_in[14]:9 *C 48.050 98.940 +*N chany_bottom_in[14]:10 *C 46.498 126.480 +*N chany_bottom_in[14]:11 *C 46.875 126.480 +*N chany_bottom_in[14]:12 *C 46.920 126.435 +*N chany_bottom_in[14]:13 *C 46.920 121.765 +*N chany_bottom_in[14]:14 *C 46.965 121.720 +*N chany_bottom_in[14]:15 *C 51.935 121.720 +*N chany_bottom_in[14]:16 *C 51.980 121.675 +*N chany_bottom_in[14]:17 *C 51.980 98.985 +*N chany_bottom_in[14]:18 *C 51.935 98.940 +*N chany_bottom_in[14]:19 *C 47.878 99.620 +*N chany_bottom_in[14]:20 *C 48.300 99.620 +*N chany_bottom_in[14]:21 *C 48.300 98.940 +*N chany_bottom_in[14]:22 *C 48.760 98.940 +*N chany_bottom_in[14]:23 *C 48.760 98.940 +*N chany_bottom_in[14]:24 *C 48.758 98.940 +*N chany_bottom_in[14]:25 *C 48.760 98.933 +*N chany_bottom_in[14]:26 *C 48.760 97.920 +*N chany_bottom_in[14]:27 *C 47.840 97.920 +*N chany_bottom_in[14]:28 *C 47.840 60.528 +*N chany_bottom_in[14]:29 *C 47.840 60.520 +*N chany_bottom_in[14]:30 *C 60.700 60.520 +*N chany_bottom_in[14]:31 *C 60.720 60.513 +*N chany_bottom_in[14]:32 *C 60.720 53.915 +*N chany_bottom_in[14]:33 *C 60.720 4.088 +*N chany_bottom_in[14]:34 *C 60.740 4.080 +*N chany_bottom_in[14]:35 *C 66.233 4.080 +*N chany_bottom_in[14]:36 *C 66.240 4.022 + +*CAP +0 chany_bottom_in[14] 0.0001917675 +1 mux_top_track_4\/mux_l1_in_5_:A1 1e-06 +2 FTB_29__28:A 1e-06 +3 mux_left_track_19\/mux_l1_in_0_:A0 1e-06 +4 chany_bottom_in[14]:4 5.039615e-05 +5 chany_bottom_in[14]:5 5.496945e-05 +6 chany_bottom_in[14]:6 9.365024e-05 +7 chany_bottom_in[14]:7 9.365024e-05 +8 chany_bottom_in[14]:8 0.0006473135 +9 chany_bottom_in[14]:9 7.924051e-05 +10 chany_bottom_in[14]:10 5.89181e-05 +11 chany_bottom_in[14]:11 5.89181e-05 +12 chany_bottom_in[14]:12 0.0003553347 +13 chany_bottom_in[14]:13 0.0003553347 +14 chany_bottom_in[14]:14 0.0003805624 +15 chany_bottom_in[14]:15 0.0003805624 +16 chany_bottom_in[14]:16 0.001192086 +17 chany_bottom_in[14]:17 0.001192086 +18 chany_bottom_in[14]:18 0.0001904054 +19 chany_bottom_in[14]:19 5.387294e-05 +20 chany_bottom_in[14]:20 9.659553e-05 +21 chany_bottom_in[14]:21 7.067926e-05 +22 chany_bottom_in[14]:22 0.0002524326 +23 chany_bottom_in[14]:23 3.464911e-05 +24 chany_bottom_in[14]:24 7.924051e-05 +25 chany_bottom_in[14]:25 5.222207e-05 +26 chany_bottom_in[14]:26 0.0001079086 +27 chany_bottom_in[14]:27 0.001140313 +28 chany_bottom_in[14]:28 0.001084626 +29 chany_bottom_in[14]:29 0.001451008 +30 chany_bottom_in[14]:30 0.0008036946 +31 chany_bottom_in[14]:31 0.0002591978 +32 chany_bottom_in[14]:32 0.002026501 +33 chany_bottom_in[14]:33 0.001767303 +34 chany_bottom_in[14]:34 0.0004333284 +35 chany_bottom_in[14]:35 0.0004333284 +36 chany_bottom_in[14]:36 0.0001917675 +37 chany_bottom_in[14]:29 chany_top_in[4]:21 6.077243e-06 +38 chany_bottom_in[14]:28 chany_top_in[4]:22 0.0002366229 +39 chany_bottom_in[14]:28 chany_top_in[4]:29 0.0002372958 +40 chany_bottom_in[14]:25 chany_top_in[4]:30 6.480583e-06 +41 chany_bottom_in[14]:8 chany_top_in[4]:20 6.077243e-06 +42 chany_bottom_in[14]:27 chany_top_in[4]:29 0.0002366229 +43 chany_bottom_in[14]:27 chany_top_in[4]:30 0.0002372958 +44 chany_bottom_in[14]:26 chany_top_in[4]:29 6.480583e-06 +45 chany_bottom_in[14]:28 chany_top_in[5]:17 6.811375e-06 +46 chany_bottom_in[14]:28 chany_top_in[5]:18 0.0001054494 +47 chany_bottom_in[14]:28 chany_top_in[5]:24 0.0006337716 +48 chany_bottom_in[14]:25 chany_top_in[5]:25 6.154673e-05 +49 chany_bottom_in[14]:27 chany_top_in[5]:18 6.811375e-06 +50 chany_bottom_in[14]:27 chany_top_in[5]:24 0.0001054494 +51 chany_bottom_in[14]:27 chany_top_in[5]:25 0.0006337716 +52 chany_bottom_in[14]:26 chany_top_in[5]:24 6.154673e-05 +53 chany_bottom_in[14]:31 chany_top_in[13]:31 0.0001516627 +54 chany_bottom_in[14]:33 chany_top_in[13]:30 0.0003334781 +55 chany_bottom_in[14]:32 chany_top_in[13]:30 0.0001516627 +56 chany_bottom_in[14]:32 chany_top_in[13]:31 0.0003334781 +57 chany_bottom_in[14]:33 chany_bottom_in[5]:25 0.0003679861 +58 chany_bottom_in[14]:32 chany_bottom_in[5]:24 0.0003679861 +59 chany_bottom_in[14]:33 chany_bottom_in[18]:24 0.000474523 +60 chany_bottom_in[14]:32 chany_bottom_in[18]:23 0.000474523 +61 chany_bottom_in[14]:30 prog_clk[0]:227 0.0002761494 +62 chany_bottom_in[14]:33 prog_clk[0]:157 7.218011e-06 +63 chany_bottom_in[14]:29 prog_clk[0]:227 0.0001823574 +64 chany_bottom_in[14]:29 prog_clk[0]:228 0.0002761494 +65 chany_bottom_in[14]:8 prog_clk[0]:228 0.0001823574 +66 chany_bottom_in[14]:32 prog_clk[0]:158 7.218011e-06 +67 chany_bottom_in[14]:17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.381599e-05 +68 chany_bottom_in[14]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.381599e-05 +69 chany_bottom_in[14]:29 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001604575 +70 chany_bottom_in[14]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001604575 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:36 0.002439732 +1 chany_bottom_in[14]:30 chany_bottom_in[14]:29 0.002014733 +2 chany_bottom_in[14]:31 chany_bottom_in[14]:30 0.00341 +3 chany_bottom_in[14]:34 chany_bottom_in[14]:33 0.00341 +4 chany_bottom_in[14]:33 chany_bottom_in[14]:32 0.007806308 +5 chany_bottom_in[14]:36 chany_bottom_in[14]:35 0.00341 +6 chany_bottom_in[14]:35 chany_bottom_in[14]:34 0.0008604915 +7 chany_bottom_in[14]:29 chany_bottom_in[14]:28 0.00341 +8 chany_bottom_in[14]:29 chany_bottom_in[14]:8 0.001584292 +9 chany_bottom_in[14]:28 chany_bottom_in[14]:27 0.005858158 +10 chany_bottom_in[14]:24 chany_bottom_in[14]:23 0.00341 +11 chany_bottom_in[14]:24 chany_bottom_in[14]:9 0.0001039141 +12 chany_bottom_in[14]:25 chany_bottom_in[14]:24 0.00341 +13 chany_bottom_in[14]:23 chany_bottom_in[14]:22 0.0045 +14 chany_bottom_in[14]:22 chany_bottom_in[14]:21 0.0004107143 +15 chany_bottom_in[14]:22 chany_bottom_in[14]:18 0.002834821 +16 chany_bottom_in[14]:19 mux_top_track_4\/mux_l1_in_5_:A1 0.152 +17 chany_bottom_in[14]:18 chany_bottom_in[14]:17 0.0045 +18 chany_bottom_in[14]:17 chany_bottom_in[14]:16 0.02025893 +19 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.0044375 +20 chany_bottom_in[14]:16 chany_bottom_in[14]:15 0.0045 +21 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.0045 +22 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.004169643 +23 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.0003370536 +24 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.0045 +25 chany_bottom_in[14]:10 FTB_29__28:A 0.152 +26 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.001122768 +27 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.00341 +28 chany_bottom_in[14]:5 chany_bottom_in[14]:4 9.239131e-05 +29 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.0045 +30 chany_bottom_in[14]:4 mux_left_track_19\/mux_l1_in_0_:A0 0.152 +31 chany_bottom_in[14]:20 chany_bottom_in[14]:19 0.0003772322 +32 chany_bottom_in[14]:21 chany_bottom_in[14]:20 0.0006071429 +33 chany_bottom_in[14]:27 chany_bottom_in[14]:26 0.0001441333 +34 chany_bottom_in[14]:26 chany_bottom_in[14]:25 0.000158625 +35 chany_bottom_in[14]:32 chany_bottom_in[14]:31 0.001033608 + +*END + +*D_NET chany_bottom_in[18] 0.01683746 //LENGTH 139.495 LUMPCC 0.002107878 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 57.500 1.290 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 59.630 65.960 +*I mux_top_track_24\/mux_l1_in_1_:A0 I *L 0.001631 *C 77.570 87.720 +*I BUFT_P_109:A I *L 0.001776 *C 78.660 115.600 +*N chany_bottom_in[18]:4 *C 78.623 115.600 +*N chany_bottom_in[18]:5 *C 78.245 115.600 +*N chany_bottom_in[18]:6 *C 78.200 115.555 +*N chany_bottom_in[18]:7 *C 78.200 88.400 +*N chany_bottom_in[18]:8 *C 77.740 88.400 +*N chany_bottom_in[18]:9 *C 77.570 87.720 +*N chany_bottom_in[18]:10 *C 77.280 87.720 +*N chany_bottom_in[18]:11 *C 77.280 87.720 +*N chany_bottom_in[18]:12 *C 77.740 87.720 +*N chany_bottom_in[18]:13 *C 77.740 70.040 +*N chany_bottom_in[18]:14 *C 77.280 70.040 +*N chany_bottom_in[18]:15 *C 77.280 66.005 +*N chany_bottom_in[18]:16 *C 77.235 65.960 +*N chany_bottom_in[18]:17 *C 59.630 65.960 +*N chany_bottom_in[18]:18 *C 58.925 65.960 +*N chany_bottom_in[18]:19 *C 58.880 65.915 +*N chany_bottom_in[18]:20 *C 58.880 50.378 +*N chany_bottom_in[18]:21 *C 58.873 50.320 +*N chany_bottom_in[18]:22 *C 57.980 50.320 +*N chany_bottom_in[18]:23 *C 57.960 50.312 +*N chany_bottom_in[18]:24 *C 57.960 13.607 +*N chany_bottom_in[18]:25 *C 57.945 13.600 +*N chany_bottom_in[18]:26 *C 57.503 13.600 +*N chany_bottom_in[18]:27 *C 57.500 13.543 + +*CAP +0 chany_bottom_in[18] 0.0007788524 +1 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_24\/mux_l1_in_1_:A0 1e-06 +3 BUFT_P_109:A 1e-06 +4 chany_bottom_in[18]:4 4.262682e-05 +5 chany_bottom_in[18]:5 4.262682e-05 +6 chany_bottom_in[18]:6 0.001343817 +7 chany_bottom_in[18]:7 0.001372945 +8 chany_bottom_in[18]:8 6.553801e-05 +9 chany_bottom_in[18]:9 4.928985e-05 +10 chany_bottom_in[18]:10 5.56664e-05 +11 chany_bottom_in[18]:11 5.970567e-05 +12 chany_bottom_in[18]:12 0.0009247782 +13 chany_bottom_in[18]:13 0.0008772783 +14 chany_bottom_in[18]:14 0.0002418243 +15 chany_bottom_in[18]:15 0.0002233879 +16 chany_bottom_in[18]:16 0.0009670976 +17 chany_bottom_in[18]:17 0.00103693 +18 chany_bottom_in[18]:18 4.15895e-05 +19 chany_bottom_in[18]:19 0.000880849 +20 chany_bottom_in[18]:20 0.000880849 +21 chany_bottom_in[18]:21 0.0001286907 +22 chany_bottom_in[18]:22 0.0001286907 +23 chany_bottom_in[18]:23 0.001834254 +24 chany_bottom_in[18]:24 0.001834254 +25 chany_bottom_in[18]:25 6.80925e-05 +26 chany_bottom_in[18]:26 6.80925e-05 +27 chany_bottom_in[18]:27 0.0007788524 +28 chany_bottom_in[18]:23 chany_bottom_in[14]:32 0.000474523 +29 chany_bottom_in[18]:24 chany_bottom_in[14]:33 0.000474523 +30 chany_bottom_in[18]:14 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 1.073695e-05 +31 chany_bottom_in[18]:13 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 1.073695e-05 +32 chany_bottom_in[18]:13 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 3.848251e-05 +33 chany_bottom_in[18]:12 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 3.848251e-05 +34 chany_bottom_in[18]:18 optlc_net_138:7 3.334418e-05 +35 chany_bottom_in[18]:17 optlc_net_138:8 3.334418e-05 +36 chany_bottom_in[18]:17 optlc_net_138:7 0.0003002571 +37 chany_bottom_in[18]:16 optlc_net_138:8 0.0003002571 +38 chany_bottom_in[18]:15 optlc_net_138:15 5.293345e-08 +39 chany_bottom_in[18]:14 optlc_net_138:18 5.293345e-08 +40 chany_bottom_in[18]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.306531e-06 +41 chany_bottom_in[18]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.306531e-06 +42 chany_bottom_in[18]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001235359 +43 chany_bottom_in[18]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001235359 +44 chany_bottom_in[18]:19 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.069979e-05 +45 chany_bottom_in[18]:20 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.069979e-05 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:27 0.01093973 +1 chany_bottom_in[18]:4 BUFT_P_109:A 0.152 +2 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.0003370536 +3 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.0045 +4 chany_bottom_in[18]:18 chany_bottom_in[18]:17 0.0006294643 +5 chany_bottom_in[18]:19 chany_bottom_in[18]:18 0.0045 +6 chany_bottom_in[18]:20 chany_bottom_in[18]:19 0.01387277 +7 chany_bottom_in[18]:21 chany_bottom_in[18]:20 0.00341 +8 chany_bottom_in[18]:22 chany_bottom_in[18]:21 0.000139825 +9 chany_bottom_in[18]:23 chany_bottom_in[18]:22 0.00341 +10 chany_bottom_in[18]:25 chany_bottom_in[18]:24 0.00341 +11 chany_bottom_in[18]:24 chany_bottom_in[18]:23 0.005750449 +12 chany_bottom_in[18]:27 chany_bottom_in[18]:26 0.00341 +13 chany_bottom_in[18]:26 chany_bottom_in[18]:25 6.499219e-05 +14 chany_bottom_in[18]:17 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +15 chany_bottom_in[18]:17 chany_bottom_in[18]:16 0.01571875 +16 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.0001576087 +17 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.0045 +18 chany_bottom_in[18]:9 mux_top_track_24\/mux_l1_in_1_:A0 0.152 +19 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.0045 +20 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.003602679 +21 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.0004107143 +22 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.01578572 +23 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.0004107143 +24 chany_bottom_in[18]:12 chany_bottom_in[18]:8 0.0006071429 +25 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.0004107143 +26 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.02424554 + +*END + +*D_NET top_left_grid_pin_35_[0] 0.006044953 //LENGTH 48.670 LUMPCC 0.0008225874 DR + +*CONN +*P top_left_grid_pin_35_[0] I *L 0.29796 *C 30.820 129.235 +*I mux_top_track_4\/mux_l1_in_0_:A0 I *L 0.001631 *C 44.795 115.260 +*I mux_top_track_16\/mux_l1_in_0_:A1 I *L 0.00198 *C 50.240 107.100 +*I mux_top_track_2\/mux_l1_in_0_:A1 I *L 0.00198 *C 37.165 112.540 +*N top_left_grid_pin_35_[0]:4 *C 37.165 112.540 +*N top_left_grid_pin_35_[0]:5 *C 37.260 112.585 +*N top_left_grid_pin_35_[0]:6 *C 50.203 107.100 +*N top_left_grid_pin_35_[0]:7 *C 49.725 107.100 +*N top_left_grid_pin_35_[0]:8 *C 49.680 107.145 +*N top_left_grid_pin_35_[0]:9 *C 49.680 116.235 +*N top_left_grid_pin_35_[0]:10 *C 49.635 116.280 +*N top_left_grid_pin_35_[0]:11 *C 44.795 115.260 +*N top_left_grid_pin_35_[0]:12 *C 44.620 115.260 +*N top_left_grid_pin_35_[0]:13 *C 44.620 115.305 +*N top_left_grid_pin_35_[0]:14 *C 44.620 116.235 +*N top_left_grid_pin_35_[0]:15 *C 44.620 116.280 +*N top_left_grid_pin_35_[0]:16 *C 37.305 116.280 +*N top_left_grid_pin_35_[0]:17 *C 37.260 116.280 +*N top_left_grid_pin_35_[0]:18 *C 37.260 126.775 +*N top_left_grid_pin_35_[0]:19 *C 37.215 126.820 +*N top_left_grid_pin_35_[0]:20 *C 30.865 126.820 +*N top_left_grid_pin_35_[0]:21 *C 30.820 126.865 + +*CAP +0 top_left_grid_pin_35_[0] 0.0001449083 +1 mux_top_track_4\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_2\/mux_l1_in_0_:A1 1e-06 +4 top_left_grid_pin_35_[0]:4 2.836892e-05 +5 top_left_grid_pin_35_[0]:5 0.0001773117 +6 top_left_grid_pin_35_[0]:6 6.033172e-05 +7 top_left_grid_pin_35_[0]:7 6.033172e-05 +8 top_left_grid_pin_35_[0]:8 0.0005228625 +9 top_left_grid_pin_35_[0]:9 0.0005228625 +10 top_left_grid_pin_35_[0]:10 0.0003550821 +11 top_left_grid_pin_35_[0]:11 4.775462e-05 +12 top_left_grid_pin_35_[0]:12 5.213221e-05 +13 top_left_grid_pin_35_[0]:13 7.223922e-05 +14 top_left_grid_pin_35_[0]:14 7.223922e-05 +15 top_left_grid_pin_35_[0]:15 0.0008745516 +16 top_left_grid_pin_35_[0]:16 0.0004858424 +17 top_left_grid_pin_35_[0]:17 0.0005973946 +18 top_left_grid_pin_35_[0]:18 0.0003899586 +19 top_left_grid_pin_35_[0]:19 0.0003051427 +20 top_left_grid_pin_35_[0]:20 0.0003051427 +21 top_left_grid_pin_35_[0]:21 0.0001449083 +22 top_left_grid_pin_35_[0]:20 mux_tree_tapbuf_size10_0_sram[3]:4 9.825036e-05 +23 top_left_grid_pin_35_[0]:19 mux_tree_tapbuf_size10_0_sram[3]:5 9.825036e-05 +24 top_left_grid_pin_35_[0]:18 mux_tree_tapbuf_size10_0_sram[3]:6 2.563025e-05 +25 top_left_grid_pin_35_[0]:17 mux_tree_tapbuf_size10_0_sram[3]:7 2.563025e-05 +26 top_left_grid_pin_35_[0]:20 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 5.513159e-05 +27 top_left_grid_pin_35_[0]:19 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 5.513159e-05 +28 top_left_grid_pin_35_[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 8.619096e-05 +29 top_left_grid_pin_35_[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 8.619096e-05 +30 top_left_grid_pin_35_[0]:20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.537109e-06 +31 top_left_grid_pin_35_[0]:19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 4.537109e-06 +32 top_left_grid_pin_35_[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0001162279 +33 top_left_grid_pin_35_[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 2.532551e-05 +34 top_left_grid_pin_35_[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 2.532551e-05 +35 top_left_grid_pin_35_[0]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0001162279 + +*RES +0 top_left_grid_pin_35_[0] top_left_grid_pin_35_[0]:21 0.002116072 +1 top_left_grid_pin_35_[0]:20 top_left_grid_pin_35_[0]:19 0.005669643 +2 top_left_grid_pin_35_[0]:21 top_left_grid_pin_35_[0]:20 0.0045 +3 top_left_grid_pin_35_[0]:19 top_left_grid_pin_35_[0]:18 0.0045 +4 top_left_grid_pin_35_[0]:18 top_left_grid_pin_35_[0]:17 0.009370536 +5 top_left_grid_pin_35_[0]:4 mux_top_track_2\/mux_l1_in_0_:A1 0.152 +6 top_left_grid_pin_35_[0]:5 top_left_grid_pin_35_[0]:4 0.0045 +7 top_left_grid_pin_35_[0]:16 top_left_grid_pin_35_[0]:15 0.00653125 +8 top_left_grid_pin_35_[0]:17 top_left_grid_pin_35_[0]:16 0.0045 +9 top_left_grid_pin_35_[0]:17 top_left_grid_pin_35_[0]:5 0.003299108 +10 top_left_grid_pin_35_[0]:10 top_left_grid_pin_35_[0]:9 0.0045 +11 top_left_grid_pin_35_[0]:9 top_left_grid_pin_35_[0]:8 0.008116072 +12 top_left_grid_pin_35_[0]:7 top_left_grid_pin_35_[0]:6 0.0004263393 +13 top_left_grid_pin_35_[0]:8 top_left_grid_pin_35_[0]:7 0.0045 +14 top_left_grid_pin_35_[0]:6 mux_top_track_16\/mux_l1_in_0_:A1 0.152 +15 top_left_grid_pin_35_[0]:15 top_left_grid_pin_35_[0]:14 0.0045 +16 top_left_grid_pin_35_[0]:15 top_left_grid_pin_35_[0]:10 0.004477679 +17 top_left_grid_pin_35_[0]:14 top_left_grid_pin_35_[0]:13 0.0008303571 +18 top_left_grid_pin_35_[0]:12 top_left_grid_pin_35_[0]:11 9.51087e-05 +19 top_left_grid_pin_35_[0]:13 top_left_grid_pin_35_[0]:12 0.0045 +20 top_left_grid_pin_35_[0]:11 mux_top_track_4\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_bottom_in[1] 0.01347832 //LENGTH 98.740 LUMPCC 0.002357315 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 67.160 1.290 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 42.150 65.960 +*N chany_bottom_in[1]:2 *C 42.113 65.960 +*N chany_bottom_in[1]:3 *C 40.940 65.960 +*N chany_bottom_in[1]:4 *C 40.940 66.640 +*N chany_bottom_in[1]:5 *C 40.525 66.640 +*N chany_bottom_in[1]:6 *C 40.480 66.640 +*N chany_bottom_in[1]:7 *C 40.473 66.640 +*N chany_bottom_in[1]:8 *C 39.580 66.640 +*N chany_bottom_in[1]:9 *C 39.560 66.633 +*N chany_bottom_in[1]:10 *C 39.560 23.808 +*N chany_bottom_in[1]:11 *C 39.580 23.800 +*N chany_bottom_in[1]:12 *C 65.300 23.800 +*N chany_bottom_in[1]:13 *C 65.320 23.793 +*N chany_bottom_in[1]:14 *C 65.320 10.888 +*N chany_bottom_in[1]:15 *C 65.340 10.880 +*N chany_bottom_in[1]:16 *C 67.153 10.880 +*N chany_bottom_in[1]:17 *C 67.160 10.822 + +*CAP +0 chany_bottom_in[1] 0.0005014795 +1 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[1]:2 8.703761e-05 +3 chany_bottom_in[1]:3 0.0001357457 +4 chany_bottom_in[1]:4 9.407862e-05 +5 chany_bottom_in[1]:5 4.537054e-05 +6 chany_bottom_in[1]:6 3.748558e-05 +7 chany_bottom_in[1]:7 0.0001358535 +8 chany_bottom_in[1]:8 0.0001358535 +9 chany_bottom_in[1]:9 0.002287896 +10 chany_bottom_in[1]:10 0.002287896 +11 chany_bottom_in[1]:11 0.001690526 +12 chany_bottom_in[1]:12 0.001690526 +13 chany_bottom_in[1]:13 0.0005767506 +14 chany_bottom_in[1]:14 0.0005767506 +15 chany_bottom_in[1]:15 0.000167636 +16 chany_bottom_in[1]:16 0.000167636 +17 chany_bottom_in[1]:17 0.0005014795 +18 chany_bottom_in[1] chany_bottom_in[13] 7.1089e-05 +19 chany_bottom_in[1]:9 chany_bottom_in[13]:26 2.793159e-07 +20 chany_bottom_in[1]:9 chany_bottom_in[13]:32 0.0003185244 +21 chany_bottom_in[1]:10 chany_bottom_in[13]:32 2.793159e-07 +22 chany_bottom_in[1]:10 chany_bottom_in[13]:33 0.0003185244 +23 chany_bottom_in[1]:17 chany_bottom_in[13]:36 7.1089e-05 +24 chany_bottom_in[1]:13 chany_bottom_in[17]:27 0.0002788354 +25 chany_bottom_in[1]:14 chany_bottom_in[17]:28 0.0002788354 +26 chany_bottom_in[1]:9 chanx_left_in[19]:14 5.029882e-06 +27 chany_bottom_in[1]:9 chanx_left_in[19]:11 0.0005048993 +28 chany_bottom_in[1]:10 chanx_left_in[19]:15 5.029882e-06 +29 chany_bottom_in[1]:10 chanx_left_in[19]:12 0.0005048993 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:17 0.008511161 +1 chany_bottom_in[1]:2 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.0003705357 +3 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.0045 +4 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.00341 +5 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.000139825 +6 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.00341 +7 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.00341 +8 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.00670925 +9 chany_bottom_in[1]:12 chany_bottom_in[1]:11 0.004029466 +10 chany_bottom_in[1]:13 chany_bottom_in[1]:12 0.00341 +11 chany_bottom_in[1]:15 chany_bottom_in[1]:14 0.00341 +12 chany_bottom_in[1]:14 chany_bottom_in[1]:13 0.002021783 +13 chany_bottom_in[1]:17 chany_bottom_in[1]:16 0.00341 +14 chany_bottom_in[1]:16 chany_bottom_in[1]:15 0.0002839583 +15 chany_bottom_in[1]:4 chany_bottom_in[1]:3 0.0006071429 +16 chany_bottom_in[1]:3 chany_bottom_in[1]:2 0.001046875 + +*END + +*D_NET bottom_left_grid_pin_34_[0] 0.007466608 //LENGTH 58.610 LUMPCC 0.0004272326 DR + +*CONN +*P bottom_left_grid_pin_34_[0] I *L 0.29796 *C 29.750 10.200 +*I mux_bottom_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 40.770 4.760 +*I mux_bottom_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 29.805 30.940 +*I mux_bottom_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 37.820 39.780 +*N bottom_left_grid_pin_34_[0]:4 *C 31.490 15.640 +*N bottom_left_grid_pin_34_[0]:5 *C 37.782 39.780 +*N bottom_left_grid_pin_34_[0]:6 *C 31.785 39.780 +*N bottom_left_grid_pin_34_[0]:7 *C 31.740 39.735 +*N bottom_left_grid_pin_34_[0]:8 *C 29.843 30.940 +*N bottom_left_grid_pin_34_[0]:9 *C 31.695 30.940 +*N bottom_left_grid_pin_34_[0]:10 *C 31.740 30.940 +*N bottom_left_grid_pin_34_[0]:11 *C 32.200 30.940 +*N bottom_left_grid_pin_34_[0]:12 *C 32.200 15.698 +*N bottom_left_grid_pin_34_[0]:13 *C 32.197 15.640 +*N bottom_left_grid_pin_34_[0]:14 *C 32.200 15.633 +*N bottom_left_grid_pin_34_[0]:15 *C 40.770 4.760 +*N bottom_left_grid_pin_34_[0]:16 *C 40.940 4.760 +*N bottom_left_grid_pin_34_[0]:17 *C 40.940 4.805 +*N bottom_left_grid_pin_34_[0]:18 *C 40.940 6.062 +*N bottom_left_grid_pin_34_[0]:19 *C 40.933 6.120 +*N bottom_left_grid_pin_34_[0]:20 *C 32.220 6.120 +*N bottom_left_grid_pin_34_[0]:21 *C 32.200 6.128 +*N bottom_left_grid_pin_34_[0]:22 *C 32.200 10.200 +*N bottom_left_grid_pin_34_[0]:23 *C 32.180 10.200 + +*CAP +0 bottom_left_grid_pin_34_[0] 0.000181684 +1 mux_bottom_track_5\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_17\/mux_l1_in_1_:A1 1e-06 +4 bottom_left_grid_pin_34_[0]:4 8.432318e-05 +5 bottom_left_grid_pin_34_[0]:5 0.0002949763 +6 bottom_left_grid_pin_34_[0]:6 0.0002949763 +7 bottom_left_grid_pin_34_[0]:7 0.0005975646 +8 bottom_left_grid_pin_34_[0]:8 0.0001497288 +9 bottom_left_grid_pin_34_[0]:9 0.0001497288 +10 bottom_left_grid_pin_34_[0]:10 0.0006323077 +11 bottom_left_grid_pin_34_[0]:11 0.0008749919 +12 bottom_left_grid_pin_34_[0]:12 0.0008402488 +13 bottom_left_grid_pin_34_[0]:13 8.432318e-05 +14 bottom_left_grid_pin_34_[0]:14 0.0003200571 +15 bottom_left_grid_pin_34_[0]:15 5.239004e-05 +16 bottom_left_grid_pin_34_[0]:16 5.469044e-05 +17 bottom_left_grid_pin_34_[0]:17 9.392064e-05 +18 bottom_left_grid_pin_34_[0]:18 9.392064e-05 +19 bottom_left_grid_pin_34_[0]:19 0.000619281 +20 bottom_left_grid_pin_34_[0]:20 0.000619281 +21 bottom_left_grid_pin_34_[0]:21 0.00024812 +22 bottom_left_grid_pin_34_[0]:22 0.0005681771 +23 bottom_left_grid_pin_34_[0]:23 0.000181684 +24 bottom_left_grid_pin_34_[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.0002136163 +25 bottom_left_grid_pin_34_[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.0002136163 + +*RES +0 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_34_[0]:23 0.0003807 +1 bottom_left_grid_pin_34_[0]:12 bottom_left_grid_pin_34_[0]:11 0.01360938 +2 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:12 0.00341 +3 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:4 0.0001039141 +4 bottom_left_grid_pin_34_[0]:14 bottom_left_grid_pin_34_[0]:13 0.00341 +5 bottom_left_grid_pin_34_[0]:6 bottom_left_grid_pin_34_[0]:5 0.005354911 +6 bottom_left_grid_pin_34_[0]:7 bottom_left_grid_pin_34_[0]:6 0.0045 +7 bottom_left_grid_pin_34_[0]:5 mux_bottom_track_17\/mux_l1_in_1_:A1 0.152 +8 bottom_left_grid_pin_34_[0]:9 bottom_left_grid_pin_34_[0]:8 0.001654018 +9 bottom_left_grid_pin_34_[0]:10 bottom_left_grid_pin_34_[0]:9 0.0045 +10 bottom_left_grid_pin_34_[0]:10 bottom_left_grid_pin_34_[0]:7 0.007852679 +11 bottom_left_grid_pin_34_[0]:8 mux_bottom_track_3\/mux_l1_in_1_:A1 0.152 +12 bottom_left_grid_pin_34_[0]:23 bottom_left_grid_pin_34_[0]:22 0.00341 +13 bottom_left_grid_pin_34_[0]:22 bottom_left_grid_pin_34_[0]:21 0.0006380249 +14 bottom_left_grid_pin_34_[0]:22 bottom_left_grid_pin_34_[0]:14 0.0008510916 +15 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_34_[0]:19 0.001364958 +16 bottom_left_grid_pin_34_[0]:21 bottom_left_grid_pin_34_[0]:20 0.00341 +17 bottom_left_grid_pin_34_[0]:18 bottom_left_grid_pin_34_[0]:17 0.001122768 +18 bottom_left_grid_pin_34_[0]:19 bottom_left_grid_pin_34_[0]:18 0.00341 +19 bottom_left_grid_pin_34_[0]:16 bottom_left_grid_pin_34_[0]:15 9.239131e-05 +20 bottom_left_grid_pin_34_[0]:17 bottom_left_grid_pin_34_[0]:16 0.0045 +21 bottom_left_grid_pin_34_[0]:15 mux_bottom_track_5\/mux_l1_in_1_:A0 0.152 +22 bottom_left_grid_pin_34_[0]:11 bottom_left_grid_pin_34_[0]:10 0.0004107143 + +*END + +*D_NET bottom_left_grid_pin_41_[0] 0.006773761 //LENGTH 51.565 LUMPCC 0 DR + +*CONN +*P bottom_left_grid_pin_41_[0] I *L 0.29796 *C 29.750 14.280 +*I mux_bottom_track_5\/mux_l1_in_5_:A1 I *L 0.00198 *C 34.040 25.500 +*I mux_bottom_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 51.835 17.340 +*I mux_bottom_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 65.035 20.740 +*N bottom_left_grid_pin_41_[0]:4 *C 65.035 20.740 +*N bottom_left_grid_pin_41_[0]:5 *C 64.860 20.740 +*N bottom_left_grid_pin_41_[0]:6 *C 64.860 20.695 +*N bottom_left_grid_pin_41_[0]:7 *C 64.860 17.738 +*N bottom_left_grid_pin_41_[0]:8 *C 64.853 17.680 +*N bottom_left_grid_pin_41_[0]:9 *C 51.835 17.340 +*N bottom_left_grid_pin_41_[0]:10 *C 51.980 17.340 +*N bottom_left_grid_pin_41_[0]:11 *C 51.980 17.680 +*N bottom_left_grid_pin_41_[0]:12 *C 51.980 17.680 +*N bottom_left_grid_pin_41_[0]:13 *C 34.040 25.500 +*N bottom_left_grid_pin_41_[0]:14 *C 34.040 25.455 +*N bottom_left_grid_pin_41_[0]:15 *C 34.040 17.738 +*N bottom_left_grid_pin_41_[0]:16 *C 34.040 17.680 +*N bottom_left_grid_pin_41_[0]:17 *C 30.380 17.680 +*N bottom_left_grid_pin_41_[0]:18 *C 30.360 17.672 +*N bottom_left_grid_pin_41_[0]:19 *C 30.360 14.288 +*N bottom_left_grid_pin_41_[0]:20 *C 30.340 14.280 + +*CAP +0 bottom_left_grid_pin_41_[0] 6.134069e-05 +1 mux_bottom_track_5\/mux_l1_in_5_:A1 1e-06 +2 mux_bottom_track_1\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_track_9\/mux_l2_in_1_:A0 1e-06 +4 bottom_left_grid_pin_41_[0]:4 6.133475e-05 +5 bottom_left_grid_pin_41_[0]:5 6.262988e-05 +6 bottom_left_grid_pin_41_[0]:6 0.0002198678 +7 bottom_left_grid_pin_41_[0]:7 0.0002198678 +8 bottom_left_grid_pin_41_[0]:8 0.0008644413 +9 bottom_left_grid_pin_41_[0]:9 2.849699e-05 +10 bottom_left_grid_pin_41_[0]:10 5.208816e-05 +11 bottom_left_grid_pin_41_[0]:11 5.600447e-05 +12 bottom_left_grid_pin_41_[0]:12 0.002010346 +13 bottom_left_grid_pin_41_[0]:13 3.410413e-05 +14 bottom_left_grid_pin_41_[0]:14 0.0005179495 +15 bottom_left_grid_pin_41_[0]:15 0.0005179495 +16 bottom_left_grid_pin_41_[0]:16 0.001387541 +17 bottom_left_grid_pin_41_[0]:17 0.0002416363 +18 bottom_left_grid_pin_41_[0]:18 0.0001869112 +19 bottom_left_grid_pin_41_[0]:19 0.0001869112 +20 bottom_left_grid_pin_41_[0]:20 6.134069e-05 + +*RES +0 bottom_left_grid_pin_41_[0] bottom_left_grid_pin_41_[0]:20 9.243332e-05 +1 bottom_left_grid_pin_41_[0]:13 mux_bottom_track_5\/mux_l1_in_5_:A1 0.152 +2 bottom_left_grid_pin_41_[0]:14 bottom_left_grid_pin_41_[0]:13 0.0045 +3 bottom_left_grid_pin_41_[0]:15 bottom_left_grid_pin_41_[0]:14 0.006890626 +4 bottom_left_grid_pin_41_[0]:16 bottom_left_grid_pin_41_[0]:15 0.00341 +5 bottom_left_grid_pin_41_[0]:16 bottom_left_grid_pin_41_[0]:12 0.0028106 +6 bottom_left_grid_pin_41_[0]:9 mux_bottom_track_1\/mux_l2_in_1_:A0 0.152 +7 bottom_left_grid_pin_41_[0]:10 bottom_left_grid_pin_41_[0]:9 0.0045 +8 bottom_left_grid_pin_41_[0]:11 bottom_left_grid_pin_41_[0]:10 0.0001634615 +9 bottom_left_grid_pin_41_[0]:12 bottom_left_grid_pin_41_[0]:11 0.00341 +10 bottom_left_grid_pin_41_[0]:12 bottom_left_grid_pin_41_[0]:8 0.002016692 +11 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_41_[0]:16 0.0005734 +12 bottom_left_grid_pin_41_[0]:18 bottom_left_grid_pin_41_[0]:17 0.00341 +13 bottom_left_grid_pin_41_[0]:20 bottom_left_grid_pin_41_[0]:19 0.00341 +14 bottom_left_grid_pin_41_[0]:19 bottom_left_grid_pin_41_[0]:18 0.0005303166 +15 bottom_left_grid_pin_41_[0]:7 bottom_left_grid_pin_41_[0]:6 0.002640625 +16 bottom_left_grid_pin_41_[0]:8 bottom_left_grid_pin_41_[0]:7 0.00341 +17 bottom_left_grid_pin_41_[0]:5 bottom_left_grid_pin_41_[0]:4 9.51087e-05 +18 bottom_left_grid_pin_41_[0]:6 bottom_left_grid_pin_41_[0]:5 0.0045 +19 bottom_left_grid_pin_41_[0]:4 mux_bottom_track_9\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET chanx_left_in[10] 0.008011112 //LENGTH 51.890 LUMPCC 0.002905889 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 59.160 +*I mux_top_track_16\/mux_l1_in_2_:A0 I *L 0.001631 *C 37.435 55.080 +*I mux_bottom_track_5\/mux_l1_in_6_:A1 I *L 0.00198 *C 34.500 45.220 +*N chanx_left_in[10]:3 *C 34.500 45.220 +*N chanx_left_in[10]:4 *C 34.500 45.560 +*N chanx_left_in[10]:5 *C 34.500 45.605 +*N chanx_left_in[10]:6 *C 34.500 55.080 +*N chanx_left_in[10]:7 *C 37.398 55.080 +*N chanx_left_in[10]:8 *C 35.005 55.080 +*N chanx_left_in[10]:9 *C 34.960 55.125 +*N chanx_left_in[10]:10 *C 34.960 59.103 +*N chanx_left_in[10]:11 *C 34.953 59.160 + +*CAP +0 chanx_left_in[10] 0.001543392 +1 mux_top_track_16\/mux_l1_in_2_:A0 1e-06 +2 mux_bottom_track_5\/mux_l1_in_6_:A1 1e-06 +3 chanx_left_in[10]:3 6.79325e-05 +4 chanx_left_in[10]:4 7.267618e-05 +5 chanx_left_in[10]:5 0.0005377808 +6 chanx_left_in[10]:6 0.0005541681 +7 chanx_left_in[10]:7 0.0001219337 +8 chanx_left_in[10]:8 0.0001219337 +9 chanx_left_in[10]:9 0.000278201 +10 chanx_left_in[10]:10 0.0002618137 +11 chanx_left_in[10]:11 0.001543392 +12 chanx_left_in[10] optlc_net_139:30 5.443561e-06 +13 chanx_left_in[10] optlc_net_139:38 0.000932536 +14 chanx_left_in[10]:11 optlc_net_139:29 5.443561e-06 +15 chanx_left_in[10]:11 optlc_net_139:39 0.000932536 +16 chanx_left_in[10] mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0003921707 +17 chanx_left_in[10]:8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0001029678 +18 chanx_left_in[10]:9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 7.866335e-07 +19 chanx_left_in[10]:9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 1.903991e-05 +20 chanx_left_in[10]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0001029678 +21 chanx_left_in[10]:10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 7.866335e-07 +22 chanx_left_in[10]:11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0003921707 +23 chanx_left_in[10]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 1.903991e-05 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:11 0.005283191 +1 chanx_left_in[10]:8 chanx_left_in[10]:7 0.002136161 +2 chanx_left_in[10]:9 chanx_left_in[10]:8 0.0045 +3 chanx_left_in[10]:9 chanx_left_in[10]:6 0.0004107143 +4 chanx_left_in[10]:7 mux_top_track_16\/mux_l1_in_2_:A0 0.152 +5 chanx_left_in[10]:4 chanx_left_in[10]:3 0.0001465517 +6 chanx_left_in[10]:5 chanx_left_in[10]:4 0.0045 +7 chanx_left_in[10]:3 mux_bottom_track_5\/mux_l1_in_6_:A1 0.152 +8 chanx_left_in[10]:10 chanx_left_in[10]:9 0.003551339 +9 chanx_left_in[10]:11 chanx_left_in[10]:10 0.00341 +10 chanx_left_in[10]:6 chanx_left_in[10]:5 0.008459822 + +*END + +*D_NET chanx_left_in[19] 0.01566024 //LENGTH 106.965 LUMPCC 0.005403589 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 35.360 +*I mux_top_track_4\/mux_l1_in_6_:A0 I *L 0.001631 *C 40.195 97.240 +*I mux_bottom_track_17\/mux_l1_in_3_:A1 I *L 0.00198 *C 40.580 45.220 +*N chanx_left_in[19]:3 *C 40.543 45.220 +*N chanx_left_in[19]:4 *C 38.240 52.360 +*N chanx_left_in[19]:5 *C 37.930 94.520 +*N chanx_left_in[19]:6 *C 40.157 97.240 +*N chanx_left_in[19]:7 *C 38.685 97.240 +*N chanx_left_in[19]:8 *C 38.640 97.195 +*N chanx_left_in[19]:9 *C 38.640 94.578 +*N chanx_left_in[19]:10 *C 38.638 94.520 +*N chanx_left_in[19]:11 *C 38.640 94.513 +*N chanx_left_in[19]:12 *C 38.640 52.367 +*N chanx_left_in[19]:13 *C 38.640 52.360 +*N chanx_left_in[19]:14 *C 38.640 52.303 +*N chanx_left_in[19]:15 *C 38.640 45.265 +*N chanx_left_in[19]:16 *C 38.640 45.220 +*N chanx_left_in[19]:17 *C 37.720 45.220 +*N chanx_left_in[19]:18 *C 37.720 44.200 +*N chanx_left_in[19]:19 *C 18.905 44.200 +*N chanx_left_in[19]:20 *C 18.860 44.155 +*N chanx_left_in[19]:21 *C 18.860 35.418 +*N chanx_left_in[19]:22 *C 18.852 35.360 + +*CAP +0 chanx_left_in[19] 0.0004011513 +1 mux_top_track_4\/mux_l1_in_6_:A0 1e-06 +2 mux_bottom_track_17\/mux_l1_in_3_:A1 1e-06 +3 chanx_left_in[19]:3 0.0001315509 +4 chanx_left_in[19]:4 0.0001000893 +5 chanx_left_in[19]:5 9.920548e-05 +6 chanx_left_in[19]:6 0.0001535446 +7 chanx_left_in[19]:7 0.0001535446 +8 chanx_left_in[19]:8 0.0001199637 +9 chanx_left_in[19]:9 0.0001199637 +10 chanx_left_in[19]:10 9.920548e-05 +11 chanx_left_in[19]:11 0.001742865 +12 chanx_left_in[19]:12 0.001742865 +13 chanx_left_in[19]:13 0.0001000893 +14 chanx_left_in[19]:14 0.0003952488 +15 chanx_left_in[19]:15 0.0003952488 +16 chanx_left_in[19]:16 0.0002236072 +17 chanx_left_in[19]:17 0.0001229443 +18 chanx_left_in[19]:18 0.001435004 +19 chanx_left_in[19]:19 0.001369719 +20 chanx_left_in[19]:20 0.000473846 +21 chanx_left_in[19]:21 0.000473846 +22 chanx_left_in[19]:22 0.0004011513 +23 chanx_left_in[19]:12 chany_bottom_in[13]:25 0.0001179155 +24 chanx_left_in[19]:12 chany_bottom_in[13]:32 0.0005652575 +25 chanx_left_in[19]:12 chany_bottom_in[13]:33 2.937545e-05 +26 chanx_left_in[19]:11 chany_bottom_in[13]:18 0.0001179155 +27 chanx_left_in[19]:11 chany_bottom_in[13]:26 0.0005652575 +28 chanx_left_in[19]:11 chany_bottom_in[13]:32 2.937545e-05 +29 chanx_left_in[19]:15 chany_bottom_in[1]:10 5.029882e-06 +30 chanx_left_in[19]:14 chany_bottom_in[1]:9 5.029882e-06 +31 chanx_left_in[19]:12 chany_bottom_in[1]:10 0.0005048993 +32 chanx_left_in[19]:11 chany_bottom_in[1]:9 0.0005048993 +33 chanx_left_in[19] chanx_left_in[1]:12 0.0009249342 +34 chanx_left_in[19]:22 chanx_left_in[1]:11 0.0009249342 +35 chanx_left_in[19] chanx_left_in[11] 0.0004204961 +36 chanx_left_in[19]:22 chanx_left_in[11]:23 0.0004204961 +37 chanx_left_in[19]:19 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 5.688661e-05 +38 chanx_left_in[19]:18 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 5.688661e-05 +39 chanx_left_in[19]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.700008e-05 +40 chanx_left_in[19]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.700008e-05 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:22 0.002760858 +1 chanx_left_in[19]:21 chanx_left_in[19]:20 0.00780134 +2 chanx_left_in[19]:22 chanx_left_in[19]:21 0.00341 +3 chanx_left_in[19]:19 chanx_left_in[19]:18 0.01679911 +4 chanx_left_in[19]:20 chanx_left_in[19]:19 0.0045 +5 chanx_left_in[19]:3 mux_bottom_track_17\/mux_l1_in_3_:A1 0.152 +6 chanx_left_in[19]:16 chanx_left_in[19]:15 0.0045 +7 chanx_left_in[19]:16 chanx_left_in[19]:3 0.001698661 +8 chanx_left_in[19]:15 chanx_left_in[19]:14 0.006283482 +9 chanx_left_in[19]:14 chanx_left_in[19]:13 0.00341 +10 chanx_left_in[19]:13 chanx_left_in[19]:12 0.00341 +11 chanx_left_in[19]:13 chanx_left_in[19]:4 5.69697e-05 +12 chanx_left_in[19]:12 chanx_left_in[19]:11 0.006602716 +13 chanx_left_in[19]:10 chanx_left_in[19]:9 0.00341 +14 chanx_left_in[19]:10 chanx_left_in[19]:5 0.0001039141 +15 chanx_left_in[19]:11 chanx_left_in[19]:10 0.00341 +16 chanx_left_in[19]:9 chanx_left_in[19]:8 0.002337054 +17 chanx_left_in[19]:7 chanx_left_in[19]:6 0.001314732 +18 chanx_left_in[19]:8 chanx_left_in[19]:7 0.0045 +19 chanx_left_in[19]:6 mux_top_track_4\/mux_l1_in_6_:A0 0.152 +20 chanx_left_in[19]:18 chanx_left_in[19]:17 0.0009107144 +21 chanx_left_in[19]:17 chanx_left_in[19]:16 0.0008214287 + +*END + +*D_NET chanx_left_out[4] 0.001303532 //LENGTH 11.860 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 71.740 +*P chanx_left_out[4] O *L 0.7423 *C 1.305 80.240 +*N chanx_left_out[4]:2 *C 1.380 79.560 +*N chanx_left_out[4]:3 *C 3.213 79.560 +*N chanx_left_out[4]:4 *C 3.220 79.502 +*N chanx_left_out[4]:5 *C 3.220 71.785 +*N chanx_left_out[4]:6 *C 3.243 71.740 +*N chanx_left_out[4]:7 *C 3.610 71.740 + +*CAP +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[4] 5.285756e-05 +2 chanx_left_out[4]:2 0.0002002938 +3 chanx_left_out[4]:3 0.0001474363 +4 chanx_left_out[4]:4 0.0004093746 +5 chanx_left_out[4]:5 0.0004093746 +6 chanx_left_out[4]:6 4.15974e-05 +7 chanx_left_out[4]:7 4.15974e-05 + +*RES +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[4]:7 0.152 +1 chanx_left_out[4]:7 chanx_left_out[4]:6 0.0001997283 +2 chanx_left_out[4]:6 chanx_left_out[4]:5 0.0045 +3 chanx_left_out[4]:5 chanx_left_out[4]:4 0.006890626 +4 chanx_left_out[4]:4 chanx_left_out[4]:3 0.00341 +5 chanx_left_out[4]:3 chanx_left_out[4]:2 0.0002870917 +6 chanx_left_out[4]:2 chanx_left_out[4] 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size14_mem_0_ccff_tail[0] 0.0005084687 //LENGTH 3.610 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/FTB_6__38:X O *L 0 *C 72.455 109.480 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 75.155 109.820 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 *C 75.118 109.820 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 *C 74.060 109.820 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 *C 74.060 109.480 +*N mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 *C 72.493 109.480 + +*CAP +0 mem_top_track_4\/FTB_6__38:X 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 9.530014e-05 +3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 0.0001262395 +4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 0.0001579342 +5 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 0.0001269949 + +*RES +0 mem_top_track_4\/FTB_6__38:X mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 0.152 +1 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 0.001399554 +2 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 0.0003035715 +4 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size14_mem_0_ccff_tail[0]:2 0.0009441964 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.0005646361 //LENGTH 4.040 LUMPCC 0 DR + +*CONN +*I mem_left_track_19\/FTB_24__56:X O *L 0 *C 33.355 67.320 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 32.375 69.700 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 32.413 69.700 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 33.075 69.700 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 33.120 69.655 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 33.120 67.365 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 33.120 67.320 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 33.355 67.320 + +*CAP +0 mem_left_track_19\/FTB_24__56:X 1e-06 +1 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 6.806108e-05 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 6.806108e-05 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.0001532883 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0001532883 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 6.118607e-05 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 5.875131e-05 + +*RES +0 mem_left_track_19\/FTB_24__56:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.0005915179 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.002044643 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[1] 0.003989061 //LENGTH 32.670 LUMPCC 0 DR + +*CONN +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 85.865 58.820 +*I mux_left_track_11\/mux_l2_in_1_:S I *L 0.00357 *C 80.860 44.880 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 76.075 49.980 +*I mux_left_track_11\/mux_l2_in_0_:S I *L 0.00357 *C 87.040 47.600 +*N mux_tree_tapbuf_size4_1_sram[1]:4 *C 86.940 47.600 +*N mux_tree_tapbuf_size4_1_sram[1]:5 *C 86.940 47.645 +*N mux_tree_tapbuf_size4_1_sram[1]:6 *C 76.112 49.980 +*N mux_tree_tapbuf_size4_1_sram[1]:7 *C 78.660 49.980 +*N mux_tree_tapbuf_size4_1_sram[1]:8 *C 80.823 44.880 +*N mux_tree_tapbuf_size4_1_sram[1]:9 *C 78.705 44.880 +*N mux_tree_tapbuf_size4_1_sram[1]:10 *C 78.660 44.925 +*N mux_tree_tapbuf_size4_1_sram[1]:11 *C 78.660 49.595 +*N mux_tree_tapbuf_size4_1_sram[1]:12 *C 78.660 49.640 +*N mux_tree_tapbuf_size4_1_sram[1]:13 *C 86.895 49.640 +*N mux_tree_tapbuf_size4_1_sram[1]:14 *C 86.940 49.595 +*N mux_tree_tapbuf_size4_1_sram[1]:15 *C 86.480 49.640 +*N mux_tree_tapbuf_size4_1_sram[1]:16 *C 86.480 58.775 +*N mux_tree_tapbuf_size4_1_sram[1]:17 *C 86.435 58.820 +*N mux_tree_tapbuf_size4_1_sram[1]:18 *C 85.903 58.820 + +*CAP +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_11\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_11\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_1_sram[1]:4 3.286823e-05 +5 mux_tree_tapbuf_size4_1_sram[1]:5 0.0001377375 +6 mux_tree_tapbuf_size4_1_sram[1]:6 0.0001933803 +7 mux_tree_tapbuf_size4_1_sram[1]:7 0.0002226551 +8 mux_tree_tapbuf_size4_1_sram[1]:8 0.000172697 +9 mux_tree_tapbuf_size4_1_sram[1]:9 0.000172697 +10 mux_tree_tapbuf_size4_1_sram[1]:10 0.0003335301 +11 mux_tree_tapbuf_size4_1_sram[1]:11 0.0003335301 +12 mux_tree_tapbuf_size4_1_sram[1]:12 0.0005946191 +13 mux_tree_tapbuf_size4_1_sram[1]:13 0.0005653443 +14 mux_tree_tapbuf_size4_1_sram[1]:14 0.0001656885 +15 mux_tree_tapbuf_size4_1_sram[1]:15 0.0004934485 +16 mux_tree_tapbuf_size4_1_sram[1]:16 0.0004654973 +17 mux_tree_tapbuf_size4_1_sram[1]:17 5.068399e-05 +18 mux_tree_tapbuf_size4_1_sram[1]:18 5.068399e-05 + +*RES +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_1_sram[1]:18 0.152 +1 mux_tree_tapbuf_size4_1_sram[1]:4 mux_left_track_11\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_1_sram[1]:5 mux_tree_tapbuf_size4_1_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size4_1_sram[1]:13 mux_tree_tapbuf_size4_1_sram[1]:12 0.007352679 +4 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:13 0.0045 +5 mux_tree_tapbuf_size4_1_sram[1]:14 mux_tree_tapbuf_size4_1_sram[1]:5 0.001741071 +6 mux_tree_tapbuf_size4_1_sram[1]:17 mux_tree_tapbuf_size4_1_sram[1]:16 0.0045 +7 mux_tree_tapbuf_size4_1_sram[1]:16 mux_tree_tapbuf_size4_1_sram[1]:15 0.00815625 +8 mux_tree_tapbuf_size4_1_sram[1]:18 mux_tree_tapbuf_size4_1_sram[1]:17 0.0004754465 +9 mux_tree_tapbuf_size4_1_sram[1]:6 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size4_1_sram[1]:12 mux_tree_tapbuf_size4_1_sram[1]:11 0.0045 +11 mux_tree_tapbuf_size4_1_sram[1]:12 mux_tree_tapbuf_size4_1_sram[1]:7 0.0003035715 +12 mux_tree_tapbuf_size4_1_sram[1]:11 mux_tree_tapbuf_size4_1_sram[1]:10 0.004169643 +13 mux_tree_tapbuf_size4_1_sram[1]:9 mux_tree_tapbuf_size4_1_sram[1]:8 0.001890625 +14 mux_tree_tapbuf_size4_1_sram[1]:10 mux_tree_tapbuf_size4_1_sram[1]:9 0.0045 +15 mux_tree_tapbuf_size4_1_sram[1]:8 mux_left_track_11\/mux_l2_in_1_:S 0.152 +16 mux_tree_tapbuf_size4_1_sram[1]:7 mux_tree_tapbuf_size4_1_sram[1]:6 0.002274554 +17 mux_tree_tapbuf_size4_1_sram[1]:15 mux_tree_tapbuf_size4_1_sram[1]:14 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[1] 0.002370956 //LENGTH 18.780 LUMPCC 0.0005440572 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.565 34.000 +*I mux_bottom_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 19.880 30.600 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 13.515 37.060 +*I mux_bottom_track_33\/mux_l2_in_1_:S I *L 0.00357 *C 13.700 39.780 +*N mux_tree_tapbuf_size6_2_sram[1]:4 *C 13.685 39.780 +*N mux_tree_tapbuf_size6_2_sram[1]:5 *C 13.363 39.780 +*N mux_tree_tapbuf_size6_2_sram[1]:6 *C 13.340 39.735 +*N mux_tree_tapbuf_size6_2_sram[1]:7 *C 13.515 37.060 +*N mux_tree_tapbuf_size6_2_sram[1]:8 *C 13.340 37.060 +*N mux_tree_tapbuf_size6_2_sram[1]:9 *C 13.340 37.060 +*N mux_tree_tapbuf_size6_2_sram[1]:10 *C 19.780 30.600 +*N mux_tree_tapbuf_size6_2_sram[1]:11 *C 19.780 30.600 +*N mux_tree_tapbuf_size6_2_sram[1]:12 *C 19.773 30.600 +*N mux_tree_tapbuf_size6_2_sram[1]:13 *C 13.348 30.600 +*N mux_tree_tapbuf_size6_2_sram[1]:14 *C 13.340 30.658 +*N mux_tree_tapbuf_size6_2_sram[1]:15 *C 13.340 34.000 +*N mux_tree_tapbuf_size6_2_sram[1]:16 *C 13.385 34.000 +*N mux_tree_tapbuf_size6_2_sram[1]:17 *C 14.527 34.000 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_33\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_2_sram[1]:4 5.694231e-05 +5 mux_tree_tapbuf_size6_2_sram[1]:5 5.694231e-05 +6 mux_tree_tapbuf_size6_2_sram[1]:6 0.000121071 +7 mux_tree_tapbuf_size6_2_sram[1]:7 4.942519e-05 +8 mux_tree_tapbuf_size6_2_sram[1]:8 5.411243e-05 +9 mux_tree_tapbuf_size6_2_sram[1]:9 0.0002677622 +10 mux_tree_tapbuf_size6_2_sram[1]:10 2.827973e-05 +11 mux_tree_tapbuf_size6_2_sram[1]:11 3.497517e-05 +12 mux_tree_tapbuf_size6_2_sram[1]:12 0.0002328402 +13 mux_tree_tapbuf_size6_2_sram[1]:13 0.0002328402 +14 mux_tree_tapbuf_size6_2_sram[1]:14 0.0001505588 +15 mux_tree_tapbuf_size6_2_sram[1]:15 0.0003006807 +16 mux_tree_tapbuf_size6_2_sram[1]:16 0.0001182342 +17 mux_tree_tapbuf_size6_2_sram[1]:17 0.0001182342 +18 mux_tree_tapbuf_size6_2_sram[1]:14 prog_clk[0]:265 2.351664e-05 +19 mux_tree_tapbuf_size6_2_sram[1]:13 prog_clk[0]:266 0.0001759464 +20 mux_tree_tapbuf_size6_2_sram[1]:12 prog_clk[0]:261 0.0001759464 +21 mux_tree_tapbuf_size6_2_sram[1]:9 prog_clk[0]:264 1.840962e-05 +22 mux_tree_tapbuf_size6_2_sram[1]:15 prog_clk[0]:264 2.351664e-05 +23 mux_tree_tapbuf_size6_2_sram[1]:15 prog_clk[0]:265 1.840962e-05 +24 mux_tree_tapbuf_size6_2_sram[1]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.89657e-05 +25 mux_tree_tapbuf_size6_2_sram[1]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.34357e-05 +26 mux_tree_tapbuf_size6_2_sram[1]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.89657e-05 +27 mux_tree_tapbuf_size6_2_sram[1]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 2.175448e-05 +28 mux_tree_tapbuf_size6_2_sram[1]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.175448e-05 +29 mux_tree_tapbuf_size6_2_sram[1]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.34357e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_2_sram[1]:17 0.152 +1 mux_tree_tapbuf_size6_2_sram[1]:4 mux_bottom_track_33\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[1]:5 mux_tree_tapbuf_size6_2_sram[1]:4 0.0001752718 +3 mux_tree_tapbuf_size6_2_sram[1]:6 mux_tree_tapbuf_size6_2_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size6_2_sram[1]:14 mux_tree_tapbuf_size6_2_sram[1]:13 0.00341 +5 mux_tree_tapbuf_size6_2_sram[1]:13 mux_tree_tapbuf_size6_2_sram[1]:12 0.001006583 +6 mux_tree_tapbuf_size6_2_sram[1]:11 mux_tree_tapbuf_size6_2_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size6_2_sram[1]:12 mux_tree_tapbuf_size6_2_sram[1]:11 0.00341 +8 mux_tree_tapbuf_size6_2_sram[1]:10 mux_bottom_track_33\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size6_2_sram[1]:8 mux_tree_tapbuf_size6_2_sram[1]:7 9.51087e-05 +10 mux_tree_tapbuf_size6_2_sram[1]:9 mux_tree_tapbuf_size6_2_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size6_2_sram[1]:9 mux_tree_tapbuf_size6_2_sram[1]:6 0.002388393 +12 mux_tree_tapbuf_size6_2_sram[1]:7 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +13 mux_tree_tapbuf_size6_2_sram[1]:16 mux_tree_tapbuf_size6_2_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size6_2_sram[1]:15 mux_tree_tapbuf_size6_2_sram[1]:14 0.002984375 +15 mux_tree_tapbuf_size6_2_sram[1]:15 mux_tree_tapbuf_size6_2_sram[1]:9 0.002732143 +16 mux_tree_tapbuf_size6_2_sram[1]:17 mux_tree_tapbuf_size6_2_sram[1]:16 0.001020089 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[2] 0.001732719 //LENGTH 13.515 LUMPCC 0.00015756 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 17.325 66.300 +*I mem_left_track_5\/FTB_13__45:A I *L 0.001746 *C 16.560 63.920 +*I mux_left_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 12.520 68.680 +*N mux_tree_tapbuf_size7_5_sram[2]:3 *C 12.558 68.680 +*N mux_tree_tapbuf_size7_5_sram[2]:4 *C 14.675 68.680 +*N mux_tree_tapbuf_size7_5_sram[2]:5 *C 14.720 68.635 +*N mux_tree_tapbuf_size7_5_sram[2]:6 *C 14.720 63.965 +*N mux_tree_tapbuf_size7_5_sram[2]:7 *C 14.765 63.920 +*N mux_tree_tapbuf_size7_5_sram[2]:8 *C 16.523 63.920 +*N mux_tree_tapbuf_size7_5_sram[2]:9 *C 16.560 63.965 +*N mux_tree_tapbuf_size7_5_sram[2]:10 *C 16.560 66.255 +*N mux_tree_tapbuf_size7_5_sram[2]:11 *C 16.605 66.300 +*N mux_tree_tapbuf_size7_5_sram[2]:12 *C 17.288 66.300 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_5\/FTB_13__45:A 1e-06 +2 mux_left_track_5\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_5_sram[2]:3 0.0001653248 +4 mux_tree_tapbuf_size7_5_sram[2]:4 0.0001653248 +5 mux_tree_tapbuf_size7_5_sram[2]:5 0.0002725531 +6 mux_tree_tapbuf_size7_5_sram[2]:6 0.0002725531 +7 mux_tree_tapbuf_size7_5_sram[2]:7 8.200758e-05 +8 mux_tree_tapbuf_size7_5_sram[2]:8 8.200758e-05 +9 mux_tree_tapbuf_size7_5_sram[2]:9 0.0002004554 +10 mux_tree_tapbuf_size7_5_sram[2]:10 0.0002004554 +11 mux_tree_tapbuf_size7_5_sram[2]:11 6.573857e-05 +12 mux_tree_tapbuf_size7_5_sram[2]:12 6.573857e-05 +13 mux_tree_tapbuf_size7_5_sram[2]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.878002e-05 +14 mux_tree_tapbuf_size7_5_sram[2]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.878002e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_5_sram[2]:12 0.152 +1 mux_tree_tapbuf_size7_5_sram[2]:8 mem_left_track_5\/FTB_13__45:A 0.152 +2 mux_tree_tapbuf_size7_5_sram[2]:8 mux_tree_tapbuf_size7_5_sram[2]:7 0.001569197 +3 mux_tree_tapbuf_size7_5_sram[2]:9 mux_tree_tapbuf_size7_5_sram[2]:8 0.0045 +4 mux_tree_tapbuf_size7_5_sram[2]:11 mux_tree_tapbuf_size7_5_sram[2]:10 0.0045 +5 mux_tree_tapbuf_size7_5_sram[2]:10 mux_tree_tapbuf_size7_5_sram[2]:9 0.002044643 +6 mux_tree_tapbuf_size7_5_sram[2]:12 mux_tree_tapbuf_size7_5_sram[2]:11 0.000609375 +7 mux_tree_tapbuf_size7_5_sram[2]:7 mux_tree_tapbuf_size7_5_sram[2]:6 0.0045 +8 mux_tree_tapbuf_size7_5_sram[2]:6 mux_tree_tapbuf_size7_5_sram[2]:5 0.004169643 +9 mux_tree_tapbuf_size7_5_sram[2]:4 mux_tree_tapbuf_size7_5_sram[2]:3 0.001890625 +10 mux_tree_tapbuf_size7_5_sram[2]:5 mux_tree_tapbuf_size7_5_sram[2]:4 0.0045 +11 mux_tree_tapbuf_size7_5_sram[2]:3 mux_left_track_5\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[1] 0.00630684 //LENGTH 47.880 LUMPCC 0.00101662 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 68.385 14.960 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 69.360 17.975 +*I mux_bottom_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 66.140 19.720 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 63.655 37.060 +*I mux_bottom_track_9\/mux_l2_in_2_:S I *L 0.00357 *C 67.500 39.780 +*I mux_bottom_track_9\/mux_l2_in_3_:S I *L 0.00357 *C 67.620 45.055 +*N mux_tree_tapbuf_size8_2_sram[1]:6 *C 67.620 45.055 +*N mux_tree_tapbuf_size8_2_sram[1]:7 *C 67.620 44.880 +*N mux_tree_tapbuf_size8_2_sram[1]:8 *C 67.620 44.835 +*N mux_tree_tapbuf_size8_2_sram[1]:9 *C 67.620 39.780 +*N mux_tree_tapbuf_size8_2_sram[1]:10 *C 67.485 39.780 +*N mux_tree_tapbuf_size8_2_sram[1]:11 *C 67.183 39.780 +*N mux_tree_tapbuf_size8_2_sram[1]:12 *C 67.160 39.780 +*N mux_tree_tapbuf_size8_2_sram[1]:13 *C 67.160 37.445 +*N mux_tree_tapbuf_size8_2_sram[1]:14 *C 67.115 37.400 +*N mux_tree_tapbuf_size8_2_sram[1]:15 *C 65.320 37.400 +*N mux_tree_tapbuf_size8_2_sram[1]:16 *C 63.693 37.060 +*N mux_tree_tapbuf_size8_2_sram[1]:17 *C 65.320 37.090 +*N mux_tree_tapbuf_size8_2_sram[1]:18 *C 65.320 37.015 +*N mux_tree_tapbuf_size8_2_sram[1]:19 *C 66.103 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:20 *C 65.365 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:21 *C 65.320 19.720 +*N mux_tree_tapbuf_size8_2_sram[1]:22 *C 65.320 18.405 +*N mux_tree_tapbuf_size8_2_sram[1]:23 *C 65.365 18.360 +*N mux_tree_tapbuf_size8_2_sram[1]:24 *C 69.360 18.360 +*N mux_tree_tapbuf_size8_2_sram[1]:25 *C 69.380 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:26 *C 69.360 17.975 +*N mux_tree_tapbuf_size8_2_sram[1]:27 *C 69.435 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:28 *C 69.875 17.680 +*N mux_tree_tapbuf_size8_2_sram[1]:29 *C 69.920 17.635 +*N mux_tree_tapbuf_size8_2_sram[1]:30 *C 69.920 14.325 +*N mux_tree_tapbuf_size8_2_sram[1]:31 *C 69.875 14.280 +*N mux_tree_tapbuf_size8_2_sram[1]:32 *C 68.125 14.280 +*N mux_tree_tapbuf_size8_2_sram[1]:33 *C 68.080 14.325 +*N mux_tree_tapbuf_size8_2_sram[1]:34 *C 68.080 14.915 +*N mux_tree_tapbuf_size8_2_sram[1]:35 *C 68.080 14.960 +*N mux_tree_tapbuf_size8_2_sram[1]:36 *C 68.385 14.960 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_track_9\/mux_l2_in_1_:S 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_bottom_track_9\/mux_l2_in_2_:S 1e-06 +5 mux_bottom_track_9\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_2_sram[1]:6 4.471279e-05 +7 mux_tree_tapbuf_size8_2_sram[1]:7 4.928355e-05 +8 mux_tree_tapbuf_size8_2_sram[1]:8 0.0002962497 +9 mux_tree_tapbuf_size8_2_sram[1]:9 0.000329272 +10 mux_tree_tapbuf_size8_2_sram[1]:10 4.187227e-05 +11 mux_tree_tapbuf_size8_2_sram[1]:11 4.187227e-05 +12 mux_tree_tapbuf_size8_2_sram[1]:12 0.0001980745 +13 mux_tree_tapbuf_size8_2_sram[1]:13 0.0001650522 +14 mux_tree_tapbuf_size8_2_sram[1]:14 0.0001534416 +15 mux_tree_tapbuf_size8_2_sram[1]:15 0.0001837631 +16 mux_tree_tapbuf_size8_2_sram[1]:16 0.0001290543 +17 mux_tree_tapbuf_size8_2_sram[1]:17 0.0001593757 +18 mux_tree_tapbuf_size8_2_sram[1]:18 0.000649654 +19 mux_tree_tapbuf_size8_2_sram[1]:19 8.460516e-05 +20 mux_tree_tapbuf_size8_2_sram[1]:20 8.460516e-05 +21 mux_tree_tapbuf_size8_2_sram[1]:21 0.0007522911 +22 mux_tree_tapbuf_size8_2_sram[1]:22 6.968852e-05 +23 mux_tree_tapbuf_size8_2_sram[1]:23 0.0002992705 +24 mux_tree_tapbuf_size8_2_sram[1]:24 0.0003270666 +25 mux_tree_tapbuf_size8_2_sram[1]:25 3.051681e-05 +26 mux_tree_tapbuf_size8_2_sram[1]:26 0.0001107444 +27 mux_tree_tapbuf_size8_2_sram[1]:27 8.580636e-05 +28 mux_tree_tapbuf_size8_2_sram[1]:28 4.825401e-05 +29 mux_tree_tapbuf_size8_2_sram[1]:29 0.0002169886 +30 mux_tree_tapbuf_size8_2_sram[1]:30 0.0002169886 +31 mux_tree_tapbuf_size8_2_sram[1]:31 0.0001410956 +32 mux_tree_tapbuf_size8_2_sram[1]:32 0.0001410956 +33 mux_tree_tapbuf_size8_2_sram[1]:33 5.776156e-05 +34 mux_tree_tapbuf_size8_2_sram[1]:34 5.776156e-05 +35 mux_tree_tapbuf_size8_2_sram[1]:35 6.12437e-05 +36 mux_tree_tapbuf_size8_2_sram[1]:36 5.675752e-05 +37 mux_tree_tapbuf_size8_2_sram[1]:18 chany_bottom_in[4]:32 0.0004691671 +38 mux_tree_tapbuf_size8_2_sram[1]:22 chany_bottom_in[4]:33 3.914303e-05 +39 mux_tree_tapbuf_size8_2_sram[1]:21 chany_bottom_in[4]:32 3.914303e-05 +40 mux_tree_tapbuf_size8_2_sram[1]:21 chany_bottom_in[4]:33 0.0004691671 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_2_sram[1]:36 0.152 +1 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:16 0.001453125 +2 mux_tree_tapbuf_size8_2_sram[1]:17 mux_tree_tapbuf_size8_2_sram[1]:15 0.0002767857 +3 mux_tree_tapbuf_size8_2_sram[1]:18 mux_tree_tapbuf_size8_2_sram[1]:17 0.0045 +4 mux_tree_tapbuf_size8_2_sram[1]:23 mux_tree_tapbuf_size8_2_sram[1]:22 0.0045 +5 mux_tree_tapbuf_size8_2_sram[1]:22 mux_tree_tapbuf_size8_2_sram[1]:21 0.001174107 +6 mux_tree_tapbuf_size8_2_sram[1]:14 mux_tree_tapbuf_size8_2_sram[1]:13 0.0045 +7 mux_tree_tapbuf_size8_2_sram[1]:13 mux_tree_tapbuf_size8_2_sram[1]:12 0.002084821 +8 mux_tree_tapbuf_size8_2_sram[1]:20 mux_tree_tapbuf_size8_2_sram[1]:19 0.0006584821 +9 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:20 0.0045 +10 mux_tree_tapbuf_size8_2_sram[1]:21 mux_tree_tapbuf_size8_2_sram[1]:18 0.01544197 +11 mux_tree_tapbuf_size8_2_sram[1]:19 mux_bottom_track_9\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size8_2_sram[1]:26 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size8_2_sram[1]:26 mux_tree_tapbuf_size8_2_sram[1]:25 0.0002633929 +14 mux_tree_tapbuf_size8_2_sram[1]:26 mux_tree_tapbuf_size8_2_sram[1]:24 0.00034375 +15 mux_tree_tapbuf_size8_2_sram[1]:16 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +16 mux_tree_tapbuf_size8_2_sram[1]:28 mux_tree_tapbuf_size8_2_sram[1]:27 0.0003928572 +17 mux_tree_tapbuf_size8_2_sram[1]:29 mux_tree_tapbuf_size8_2_sram[1]:28 0.0045 +18 mux_tree_tapbuf_size8_2_sram[1]:31 mux_tree_tapbuf_size8_2_sram[1]:30 0.0045 +19 mux_tree_tapbuf_size8_2_sram[1]:30 mux_tree_tapbuf_size8_2_sram[1]:29 0.002955358 +20 mux_tree_tapbuf_size8_2_sram[1]:32 mux_tree_tapbuf_size8_2_sram[1]:31 0.0015625 +21 mux_tree_tapbuf_size8_2_sram[1]:33 mux_tree_tapbuf_size8_2_sram[1]:32 0.0045 +22 mux_tree_tapbuf_size8_2_sram[1]:35 mux_tree_tapbuf_size8_2_sram[1]:34 0.0045 +23 mux_tree_tapbuf_size8_2_sram[1]:34 mux_tree_tapbuf_size8_2_sram[1]:33 0.0005267857 +24 mux_tree_tapbuf_size8_2_sram[1]:36 mux_tree_tapbuf_size8_2_sram[1]:35 0.0001657609 +25 mux_tree_tapbuf_size8_2_sram[1]:7 mux_tree_tapbuf_size8_2_sram[1]:6 7.543105e-05 +26 mux_tree_tapbuf_size8_2_sram[1]:8 mux_tree_tapbuf_size8_2_sram[1]:7 0.0045 +27 mux_tree_tapbuf_size8_2_sram[1]:6 mux_bottom_track_9\/mux_l2_in_3_:S 0.152 +28 mux_tree_tapbuf_size8_2_sram[1]:11 mux_tree_tapbuf_size8_2_sram[1]:10 0.0001644022 +29 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:11 0.0045 +30 mux_tree_tapbuf_size8_2_sram[1]:12 mux_tree_tapbuf_size8_2_sram[1]:9 0.0004107143 +31 mux_tree_tapbuf_size8_2_sram[1]:10 mux_bottom_track_9\/mux_l2_in_2_:S 0.152 +32 mux_tree_tapbuf_size8_2_sram[1]:24 mux_tree_tapbuf_size8_2_sram[1]:23 0.003566965 +33 mux_tree_tapbuf_size8_2_sram[1]:15 mux_tree_tapbuf_size8_2_sram[1]:14 0.001602679 +34 mux_tree_tapbuf_size8_2_sram[1]:27 mux_tree_tapbuf_size8_2_sram[1]:26 0.0002633929 +35 mux_tree_tapbuf_size8_2_sram[1]:9 mux_tree_tapbuf_size8_2_sram[1]:8 0.004513393 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001911978 //LENGTH 16.365 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_1_:X O *L 0 *C 83.545 88.060 +*I mux_top_track_8\/mux_l4_in_0_:A0 I *L 0.005103 *C 85.560 98.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 85.598 98.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 86.895 98.440 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 86.940 98.395 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 86.940 90.780 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 85.100 90.780 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 85.100 88.105 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 85.055 88.060 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 83.583 88.060 + +*CAP +0 mux_top_track_8\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001349032 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001349032 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003980543 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0004880746 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002745505 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001845302 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001474809 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001474809 + +*RES +0 mux_top_track_8\/mux_l3_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_8\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.001158482 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.002388393 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.001314732 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.001642857 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.006799108 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0] 0.001025813 //LENGTH 7.700 LUMPCC 0.0001673593 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_3_:X O *L 0 *C 38.465 22.365 +*I mux_bottom_track_5\/mux_l3_in_1_:A0 I *L 0.001631 *C 38.800 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 *C 38.800 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 *C 38.640 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 *C 38.640 15.685 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 *C 38.640 22.395 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 *C 38.640 22.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 *C 38.465 22.365 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 5.145949e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 5.511648e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.0003174678 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0003174678 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 5.881223e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 5.613039e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 prog_clk[0]:193 1.438827e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 prog_clk[0]:197 2.438087e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 prog_clk[0]:190 1.438827e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 prog_clk[0]:193 2.438087e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.491052e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.491052e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_3_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 9.51087e-05 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 0.005991071 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 8.695653e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:2 mux_bottom_track_5\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001815375 //LENGTH 13.930 LUMPCC 0.0003464414 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_3_:X O *L 0 *C 32.945 75.480 +*I mux_top_track_24\/mux_l2_in_1_:A0 I *L 0.001631 *C 35.595 86.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 35.558 86.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 33.165 86.020 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 33.120 85.975 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 33.120 75.525 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 33.120 75.480 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 32.945 75.480 + +*CAP +0 mux_top_track_24\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001202114 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001202114 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0005533203 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0005533203 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.909752e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.077303e-05 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_4_sram[0]:9 7.997395e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_4_sram[0]:8 7.997395e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.044245e-07 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.274232e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.044245e-07 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.274232e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_3_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_24\/mux_l2_in_1_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002136161 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.009330357 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0006868911 //LENGTH 4.830 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_1_:X O *L 0 *C 20.525 90.780 +*I mux_left_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 21.895 88.060 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 21.858 88.060 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 20.745 88.060 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 20.700 88.105 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 20.700 90.735 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 20.700 90.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 20.525 90.780 + +*CAP +0 mux_left_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.000103095 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.000103095 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001782109 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001782109 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.22576e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.002169e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.510869e-05 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0009933036 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000518784 //LENGTH 3.860 LUMPCC 0.0002123295 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_3_:X O *L 0 *C 35.705 64.260 +*I mux_left_track_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 39.275 64.260 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 39.238 64.260 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 35.742 64.260 + +*CAP +0 mux_left_track_7\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001522273 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001522273 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 optlc_net_139:42 5.117886e-05 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 optlc_net_139:41 5.117886e-05 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.498587e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.498587e-05 + +*RES +0 mux_left_track_7\/mux_l1_in_3_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_7\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.003120536 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0003293272 //LENGTH 2.665 LUMPCC 7.777692e-05 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_0_:X O *L 0 *C 19.035 30.940 +*I mux_bottom_track_33\/mux_l3_in_0_:A1 I *L 0.00198 *C 16.660 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 16.698 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 18.998 30.940 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001247751 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001247751 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size6_2_sram[2]:7 3.888846e-05 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_2_sram[2]:8 3.888846e-05 + +*RES +0 mux_bottom_track_33\/mux_l2_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_33\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002053572 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004712833 //LENGTH 3.320 LUMPCC 0.0001307674 DR + +*CONN +*I mux_left_track_11\/mux_l2_in_0_:X O *L 0 *C 86.195 47.260 +*I mux_left_track_11\/mux_l3_in_0_:A1 I *L 0.00198 *C 83.165 47.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.203 47.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 86.157 47.260 + +*CAP +0 mux_left_track_11\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_11\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001692579 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001692579 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_1_sram[2]:8 6.538369e-05 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_1_sram[2]:7 6.538369e-05 + +*RES +0 mux_left_track_11\/mux_l2_in_0_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_11\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002638393 + +*END + +*D_NET mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001927393 //LENGTH 14.695 LUMPCC 0.0005475584 DR + +*CONN +*I mux_left_track_19\/mux_l1_in_0_:X O *L 0 *C 35.595 58.140 +*I mux_left_track_19\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.965 63.580 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 27.965 63.580 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.060 63.920 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 31.695 63.920 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 31.740 63.875 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 31.740 58.185 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 31.785 58.140 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 35.558 58.140 + +*CAP +0 mux_left_track_19\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_19\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.975825e-05 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001874915 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001586362 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002983548 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002983548 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001876198 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001876198 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[0]:18 2.581897e-06 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_1_sram[0]:5 8.119172e-05 +11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size3_1_sram[0]:16 1.547233e-05 +12 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_1_sram[0]:19 2.581897e-06 +13 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size3_1_sram[0]:4 8.119172e-05 +14 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size3_1_sram[0]:17 1.547233e-05 +15 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_1_sram[1]:7 4.057318e-05 +16 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[1]:5 8.516952e-06 +17 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size3_1_sram[1]:8 2.694094e-05 +18 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_1_sram[1]:8 8.516952e-06 +19 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size3_1_sram[1]:9 2.694094e-05 +20 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_1_sram[1]:6 4.057318e-05 +21 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.33457e-05 +22 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.156458e-06 +23 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.33457e-05 +24 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.156458e-06 + +*RES +0 mux_left_track_19\/mux_l1_in_0_:X mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_19\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003245536 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.005080357 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.003368304 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET ropt_net_178 0.000148625 //LENGTH 1.210 LUMPCC 0 DR + +*CONN +*I FTB_20__19:X O *L 0 *C 71.300 123.760 +*I ropt_mt_inst_804:A I *L 0.001766 *C 72.220 123.760 +*N ropt_net_178:2 *C 72.183 123.760 +*N ropt_net_178:3 *C 71.338 123.760 + +*CAP +0 FTB_20__19:X 1e-06 +1 ropt_mt_inst_804:A 1e-06 +2 ropt_net_178:2 7.331248e-05 +3 ropt_net_178:3 7.331248e-05 + +*RES +0 FTB_20__19:X ropt_net_178:3 0.152 +1 ropt_net_178:3 ropt_net_178:2 0.0007544643 +2 ropt_net_178:2 ropt_mt_inst_804:A 0.152 + +*END + +*D_NET ropt_net_195 0.0001138809 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_785:X O *L 0 *C 99.095 123.760 +*I ropt_mt_inst_827:A I *L 0.001767 *C 99.820 123.760 +*N ropt_net_195:2 *C 99.782 123.760 +*N ropt_net_195:3 *C 99.133 123.760 + +*CAP +0 ropt_mt_inst_785:X 1e-06 +1 ropt_mt_inst_827:A 1e-06 +2 ropt_net_195:2 5.594043e-05 +3 ropt_net_195:3 5.594043e-05 + +*RES +0 ropt_mt_inst_785:X ropt_net_195:3 0.152 +1 ropt_net_195:3 ropt_net_195:2 0.0005803572 +2 ropt_net_195:2 ropt_mt_inst_827:A 0.152 + +*END + +*D_NET ropt_net_192 0.001696 //LENGTH 13.985 LUMPCC 0.0001761527 DR + +*CONN +*I ropt_mt_inst_792:X O *L 0 *C 101.855 120.700 +*I ropt_mt_inst_824:A I *L 0.001766 *C 95.220 126.480 +*N ropt_net_192:2 *C 95.258 126.480 +*N ropt_net_192:3 *C 95.635 126.480 +*N ropt_net_192:4 *C 95.680 126.435 +*N ropt_net_192:5 *C 95.680 123.125 +*N ropt_net_192:6 *C 95.725 123.080 +*N ropt_net_192:7 *C 99.775 123.080 +*N ropt_net_192:8 *C 99.820 123.035 +*N ropt_net_192:9 *C 99.820 120.745 +*N ropt_net_192:10 *C 99.865 120.700 +*N ropt_net_192:11 *C 101.818 120.700 + +*CAP +0 ropt_mt_inst_792:X 1e-06 +1 ropt_mt_inst_824:A 1e-06 +2 ropt_net_192:2 4.846113e-05 +3 ropt_net_192:3 4.846113e-05 +4 ropt_net_192:4 0.0001882391 +5 ropt_net_192:5 0.0001882391 +6 ropt_net_192:6 0.0002492967 +7 ropt_net_192:7 0.0002492967 +8 ropt_net_192:8 0.0001509846 +9 ropt_net_192:9 0.0001509846 +10 ropt_net_192:10 0.0001219423 +11 ropt_net_192:11 0.0001219423 +12 ropt_net_192:4 chany_bottom_in[13]:8 7.13897e-06 +13 ropt_net_192:6 chany_bottom_in[13]:11 8.093736e-05 +14 ropt_net_192:5 chany_bottom_in[13]:9 7.13897e-06 +15 ropt_net_192:7 chany_bottom_in[13]:10 8.093736e-05 + +*RES +0 ropt_mt_inst_792:X ropt_net_192:11 0.152 +1 ropt_net_192:2 ropt_mt_inst_824:A 0.152 +2 ropt_net_192:3 ropt_net_192:2 0.0003370536 +3 ropt_net_192:4 ropt_net_192:3 0.0045 +4 ropt_net_192:6 ropt_net_192:5 0.0045 +5 ropt_net_192:5 ropt_net_192:4 0.002955357 +6 ropt_net_192:7 ropt_net_192:6 0.003616072 +7 ropt_net_192:8 ropt_net_192:7 0.0045 +8 ropt_net_192:10 ropt_net_192:9 0.0045 +9 ropt_net_192:9 ropt_net_192:8 0.002044643 +10 ropt_net_192:11 ropt_net_192:10 0.001743304 + +*END + +*D_NET ropt_net_163 0.00124346 //LENGTH 11.670 LUMPCC 0 DR + +*CONN +*I BUFT_P_108:X O *L 0 *C 87.860 11.560 +*I ropt_mt_inst_788:A I *L 0.001766 *C 93.840 6.800 +*N ropt_net_163:2 *C 93.803 6.800 +*N ropt_net_163:3 *C 93.425 6.800 +*N ropt_net_163:4 *C 93.380 6.845 +*N ropt_net_163:5 *C 93.380 11.515 +*N ropt_net_163:6 *C 93.335 11.560 +*N ropt_net_163:7 *C 87.898 11.560 + +*CAP +0 BUFT_P_108:X 1e-06 +1 ropt_mt_inst_788:A 1e-06 +2 ropt_net_163:2 3.831868e-05 +3 ropt_net_163:3 3.831868e-05 +4 ropt_net_163:4 0.000233452 +5 ropt_net_163:5 0.000233452 +6 ropt_net_163:6 0.0003489593 +7 ropt_net_163:7 0.0003489593 + +*RES +0 BUFT_P_108:X ropt_net_163:7 0.152 +1 ropt_net_163:7 ropt_net_163:6 0.004854911 +2 ropt_net_163:6 ropt_net_163:5 0.0045 +3 ropt_net_163:5 ropt_net_163:4 0.004169643 +4 ropt_net_163:3 ropt_net_163:2 0.0003370536 +5 ropt_net_163:4 ropt_net_163:3 0.0045 +6 ropt_net_163:2 ropt_mt_inst_788:A 0.152 + +*END + +*D_NET chany_top_in[5] 0.02281956 //LENGTH 171.635 LUMPCC 0.009125326 DR + +*CONN +*P chany_top_in[5] I *L 0.29796 *C 60.260 129.270 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 41.765 66.980 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 44.985 7.140 +*I FTB_5__4:A I *L 0.001776 *C 69.920 9.520 +*N chany_top_in[5]:4 *C 48.970 10.880 +*N chany_top_in[5]:5 *C 69.883 9.520 +*N chany_top_in[5]:6 *C 66.285 9.520 +*N chany_top_in[5]:7 *C 66.240 9.475 +*N chany_top_in[5]:8 *C 66.240 7.525 +*N chany_top_in[5]:9 *C 66.195 7.480 +*N chany_top_in[5]:10 *C 45.023 7.140 +*N chany_top_in[5]:11 *C 45.540 7.140 +*N chany_top_in[5]:12 *C 45.540 7.480 +*N chany_top_in[5]:13 *C 49.680 7.480 +*N chany_top_in[5]:14 *C 49.680 7.525 +*N chany_top_in[5]:15 *C 49.680 10.822 +*N chany_top_in[5]:16 *C 49.678 10.880 +*N chany_top_in[5]:17 *C 49.680 10.888 +*N chany_top_in[5]:18 *C 49.680 60.715 +*N chany_top_in[5]:19 *C 41.765 66.980 +*N chany_top_in[5]:20 *C 41.860 66.980 +*N chany_top_in[5]:21 *C 41.860 66.640 +*N chany_top_in[5]:22 *C 41.867 66.640 +*N chany_top_in[5]:23 *C 49.660 66.640 +*N chany_top_in[5]:24 *C 49.680 66.640 +*N chany_top_in[5]:25 *C 49.680 116.640 +*N chany_top_in[5]:26 *C 49.680 124.433 +*N chany_top_in[5]:27 *C 49.700 124.440 +*N chany_top_in[5]:28 *C 60.253 124.440 +*N chany_top_in[5]:29 *C 60.260 124.498 + +*CAP +0 chany_top_in[5] 0.0002916119 +1 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +3 FTB_5__4:A 1e-06 +4 chany_top_in[5]:4 8.182985e-05 +5 chany_top_in[5]:5 0.000197009 +6 chany_top_in[5]:6 0.000197009 +7 chany_top_in[5]:7 0.0001559029 +8 chany_top_in[5]:8 0.0001559029 +9 chany_top_in[5]:9 0.001059068 +10 chany_top_in[5]:10 4.532575e-05 +11 chany_top_in[5]:11 7.069418e-05 +12 chany_top_in[5]:12 0.0002393999 +13 chany_top_in[5]:13 0.001306772 +14 chany_top_in[5]:14 0.0001817724 +15 chany_top_in[5]:15 0.0001817724 +16 chany_top_in[5]:16 8.182985e-05 +17 chany_top_in[5]:17 0.001525508 +18 chany_top_in[5]:18 0.001709051 +19 chany_top_in[5]:19 3.172207e-05 +20 chany_top_in[5]:20 5.34744e-05 +21 chany_top_in[5]:21 5.764227e-05 +22 chany_top_in[5]:22 0.0006948735 +23 chany_top_in[5]:23 0.0006948735 +24 chany_top_in[5]:24 0.001429802 +25 chany_top_in[5]:25 0.001493405 +26 chany_top_in[5]:26 0.0002471458 +27 chany_top_in[5]:27 0.0006081115 +28 chany_top_in[5]:28 0.0006081115 +29 chany_top_in[5]:29 0.0002916119 +30 chany_top_in[5]:27 chany_top_in[4]:31 4.684005e-06 +31 chany_top_in[5]:26 chany_top_in[4]:30 4.893961e-06 +32 chany_top_in[5]:28 chany_top_in[4]:32 4.684005e-06 +33 chany_top_in[5]:24 chany_top_in[4]:29 0.0001084247 +34 chany_top_in[5]:16 chany_top_in[4]:9 2.073945e-05 +35 chany_top_in[5]:17 chany_top_in[4]:10 0.0009611454 +36 chany_top_in[5]:17 chany_top_in[4]:22 4.874269e-06 +37 chany_top_in[5]:7 chany_top_in[4]:6 7.086463e-07 +38 chany_top_in[5]:8 chany_top_in[4]:7 7.086463e-07 +39 chany_top_in[5]:4 chany_top_in[4]:8 2.073945e-05 +40 chany_top_in[5]:18 chany_top_in[4]:11 0.0009611454 +41 chany_top_in[5]:18 chany_top_in[4]:22 3.94865e-06 +42 chany_top_in[5]:18 chany_top_in[4]:29 4.874269e-06 +43 chany_top_in[5]:25 chany_top_in[4]:29 4.893961e-06 +44 chany_top_in[5]:25 chany_top_in[4]:30 0.0001044761 +45 chany_top_in[5]:27 chany_top_in[14]:26 3.230049e-05 +46 chany_top_in[5]:26 chany_top_in[14]:25 0.0001473897 +47 chany_top_in[5]:28 chany_top_in[14]:27 3.230049e-05 +48 chany_top_in[5]:10 chany_top_in[14]:14 9.914033e-06 +49 chany_top_in[5]:24 chany_top_in[14]:23 0.0008802768 +50 chany_top_in[5]:24 chany_top_in[14]:24 0.0002792953 +51 chany_top_in[5]:13 chany_top_in[14]:15 1.306307e-06 +52 chany_top_in[5]:13 chany_top_in[14]:13 2.440084e-06 +53 chany_top_in[5]:13 chany_top_in[14]:12 3.686417e-05 +54 chany_top_in[5]:13 chany_top_in[14]:11 0.0001051988 +55 chany_top_in[5]:17 chany_top_in[14]:19 1.411224e-05 +56 chany_top_in[5]:17 chany_top_in[14]:23 4.773683e-05 +57 chany_top_in[5]:9 chany_top_in[14]:11 3.686417e-05 +58 chany_top_in[5]:11 chany_top_in[14]:15 9.914033e-06 +59 chany_top_in[5]:11 chany_top_in[14]:13 7.057935e-07 +60 chany_top_in[5]:12 chany_top_in[14]:15 2.440084e-06 +61 chany_top_in[5]:12 chany_top_in[14]:14 1.306307e-06 +62 chany_top_in[5]:12 chany_top_in[14]:12 0.0001059046 +63 chany_top_in[5]:18 chany_top_in[14]:20 1.411224e-05 +64 chany_top_in[5]:18 chany_top_in[14]:23 0.0001052323 +65 chany_top_in[5]:18 chany_top_in[14]:24 4.773683e-05 +66 chany_top_in[5]:25 chany_top_in[14]:25 0.0001740629 +67 chany_top_in[5]:25 chany_top_in[14]:24 0.001027666 +68 chany_top_in[5]:24 chany_bottom_in[14]:28 0.0006337716 +69 chany_top_in[5]:24 chany_bottom_in[14]:27 0.0001054494 +70 chany_top_in[5]:24 chany_bottom_in[14]:26 6.154673e-05 +71 chany_top_in[5]:17 chany_bottom_in[14]:28 6.811375e-06 +72 chany_top_in[5]:18 chany_bottom_in[14]:28 0.0001054494 +73 chany_top_in[5]:18 chany_bottom_in[14]:27 6.811375e-06 +74 chany_top_in[5]:25 chany_bottom_in[14]:25 6.154673e-05 +75 chany_top_in[5]:25 chany_bottom_in[14]:27 0.0006337716 +76 chany_top_in[5]:17 chany_bottom_in[15]:9 0.0003426809 +77 chany_top_in[5]:18 chany_bottom_in[15]:8 0.0003426809 +78 chany_top_in[5]:27 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001652258 +79 chany_top_in[5]:26 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0001407905 +80 chany_top_in[5]:28 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001652258 +81 chany_top_in[5]:24 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 3.443199e-05 +82 chany_top_in[5]:25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0001407905 +83 chany_top_in[5]:25 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 3.443199e-05 +84 chany_top_in[5]:5 ropt_net_162:4 0.0001186194 +85 chany_top_in[5]:6 ropt_net_162:3 0.0001186194 +86 chany_top_in[5]:14 ropt_net_171:5 4.198657e-05 +87 chany_top_in[5]:15 ropt_net_171:6 4.198657e-05 +88 chany_top_in[5]:13 ropt_net_175:7 4.350808e-05 +89 chany_top_in[5]:9 ropt_net_175:6 4.350808e-05 +90 chany_top_in[5]:13 ropt_net_176:7 0.0001114632 +91 chany_top_in[5]:9 ropt_net_176:6 0.0001114632 +92 chany_top_in[5] ropt_net_186:7 2.001936e-05 +93 chany_top_in[5]:27 ropt_net_186:5 7.334584e-05 +94 chany_top_in[5]:29 ropt_net_186:8 2.001936e-05 +95 chany_top_in[5]:28 ropt_net_186:6 7.334584e-05 + +*RES +0 chany_top_in[5] chany_top_in[5]:29 0.004261161 +1 chany_top_in[5]:27 chany_top_in[5]:26 0.00341 +2 chany_top_in[5]:26 chany_top_in[5]:25 0.001220825 +3 chany_top_in[5]:29 chany_top_in[5]:28 0.00341 +4 chany_top_in[5]:28 chany_top_in[5]:27 0.001653225 +5 chany_top_in[5]:10 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +6 chany_top_in[5]:23 chany_top_in[5]:22 0.001220825 +7 chany_top_in[5]:24 chany_top_in[5]:23 0.00341 +8 chany_top_in[5]:24 chany_top_in[5]:18 0.0009282499 +9 chany_top_in[5]:21 chany_top_in[5]:20 0.0001634615 +10 chany_top_in[5]:22 chany_top_in[5]:21 0.00341 +11 chany_top_in[5]:19 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +12 chany_top_in[5]:20 chany_top_in[5]:19 0.0045 +13 chany_top_in[5]:13 chany_top_in[5]:12 0.003696429 +14 chany_top_in[5]:13 chany_top_in[5]:9 0.01474554 +15 chany_top_in[5]:14 chany_top_in[5]:13 0.0045 +16 chany_top_in[5]:15 chany_top_in[5]:14 0.002944197 +17 chany_top_in[5]:16 chany_top_in[5]:15 0.00341 +18 chany_top_in[5]:16 chany_top_in[5]:4 0.000103914 +19 chany_top_in[5]:17 chany_top_in[5]:16 0.00341 +20 chany_top_in[5]:5 FTB_5__4:A 0.152 +21 chany_top_in[5]:6 chany_top_in[5]:5 0.003212053 +22 chany_top_in[5]:7 chany_top_in[5]:6 0.0045 +23 chany_top_in[5]:9 chany_top_in[5]:8 0.0045 +24 chany_top_in[5]:8 chany_top_in[5]:7 0.001741071 +25 chany_top_in[5]:11 chany_top_in[5]:10 0.0004620536 +26 chany_top_in[5]:12 chany_top_in[5]:11 0.0003035715 +27 chany_top_in[5]:18 chany_top_in[5]:17 0.007806308 +28 chany_top_in[5]:25 chany_top_in[5]:24 0.007833333 + +*END + +*D_NET chanx_left_in[1] 0.01683683 //LENGTH 106.125 LUMPCC 0.007951733 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 38.080 +*I mux_bottom_track_1\/mux_l2_in_2_:A1 I *L 0.00198 *C 42.880 34.340 +*I mux_top_track_32\/mux_l1_in_1_:A0 I *L 0.001631 *C 61.310 75.480 +*N chanx_left_in[1]:3 *C 61.273 75.480 +*N chanx_left_in[1]:4 *C 58.005 75.480 +*N chanx_left_in[1]:5 *C 57.960 75.435 +*N chanx_left_in[1]:6 *C 57.960 34.738 +*N chanx_left_in[1]:7 *C 57.953 34.680 +*N chanx_left_in[1]:8 *C 42.780 34.340 +*N chanx_left_in[1]:9 *C 42.780 34.340 +*N chanx_left_in[1]:10 *C 42.780 34.680 +*N chanx_left_in[1]:11 *C 42.780 34.680 +*N chanx_left_in[1]:12 *C 2.780 34.680 +*N chanx_left_in[1]:13 *C 2.760 34.688 +*N chanx_left_in[1]:14 *C 2.760 38.073 +*N chanx_left_in[1]:15 *C 2.740 38.080 + +*CAP +0 chanx_left_in[1] 0.0001380579 +1 mux_bottom_track_1\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_1_:A0 1e-06 +3 chanx_left_in[1]:3 0.0002756687 +4 chanx_left_in[1]:4 0.0002756687 +5 chanx_left_in[1]:5 0.001799123 +6 chanx_left_in[1]:6 0.001799123 +7 chanx_left_in[1]:7 0.000803819 +8 chanx_left_in[1]:8 3.433802e-05 +9 chanx_left_in[1]:9 5.004969e-05 +10 chanx_left_in[1]:10 5.40149e-05 +11 chanx_left_in[1]:11 0.001935714 +12 chanx_left_in[1]:12 0.001131895 +13 chanx_left_in[1]:13 0.0002237854 +14 chanx_left_in[1]:14 0.0002237854 +15 chanx_left_in[1]:15 0.0001380579 +16 chanx_left_in[1]:6 chany_bottom_in[10]:16 0.0003148484 +17 chanx_left_in[1]:6 chany_bottom_in[10]:17 0.0001258586 +18 chanx_left_in[1]:4 chany_bottom_in[10]:12 5.699133e-06 +19 chanx_left_in[1]:5 chany_bottom_in[10]:13 0.0003148484 +20 chanx_left_in[1]:5 chany_bottom_in[10]:16 0.0001258586 +21 chanx_left_in[1]:3 chany_bottom_in[10]:11 5.699133e-06 +22 chanx_left_in[1]:11 chanx_left_in[6]:10 0.001882722 +23 chanx_left_in[1]:12 chanx_left_in[6] 0.001882722 +24 chanx_left_in[1]:11 chanx_left_in[19]:22 0.0009249342 +25 chanx_left_in[1]:12 chanx_left_in[19] 0.0009249342 +26 chanx_left_in[1]:7 mux_tree_tapbuf_size6_1_sram[0]:29 0.0003093918 +27 chanx_left_in[1]:10 mux_tree_tapbuf_size6_1_sram[0]:27 3.612169e-06 +28 chanx_left_in[1]:11 mux_tree_tapbuf_size6_1_sram[0]:29 1.350543e-05 +29 chanx_left_in[1]:11 mux_tree_tapbuf_size6_1_sram[0]:28 0.0003093918 +30 chanx_left_in[1]:9 mux_tree_tapbuf_size6_1_sram[0]:26 3.612169e-06 +31 chanx_left_in[1]:12 mux_tree_tapbuf_size6_1_sram[0]:28 1.350543e-05 +32 chanx_left_in[1]:11 mux_tree_tapbuf_size9_0_sram[1]:30 0.0002616891 +33 chanx_left_in[1]:11 mux_tree_tapbuf_size9_0_sram[1]:29 6.286314e-05 +34 chanx_left_in[1]:12 mux_tree_tapbuf_size9_0_sram[1]:26 6.286314e-05 +35 chanx_left_in[1]:12 mux_tree_tapbuf_size9_0_sram[1]:29 0.0002616891 +36 chanx_left_in[1]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.074208e-05 +37 chanx_left_in[1]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.074208e-05 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:15 0.0002365667 +1 chanx_left_in[1]:6 chanx_left_in[1]:5 0.03633706 +2 chanx_left_in[1]:7 chanx_left_in[1]:6 0.00341 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.002917411 +4 chanx_left_in[1]:5 chanx_left_in[1]:4 0.0045 +5 chanx_left_in[1]:3 mux_top_track_32\/mux_l1_in_1_:A0 0.152 +6 chanx_left_in[1]:10 chanx_left_in[1]:9 0.0001634616 +7 chanx_left_in[1]:11 chanx_left_in[1]:10 0.00341 +8 chanx_left_in[1]:11 chanx_left_in[1]:7 0.002377025 +9 chanx_left_in[1]:8 mux_bottom_track_1\/mux_l2_in_2_:A1 0.152 +10 chanx_left_in[1]:9 chanx_left_in[1]:8 0.0045 +11 chanx_left_in[1]:12 chanx_left_in[1]:11 0.006266666 +12 chanx_left_in[1]:13 chanx_left_in[1]:12 0.00341 +13 chanx_left_in[1]:15 chanx_left_in[1]:14 0.00341 +14 chanx_left_in[1]:14 chanx_left_in[1]:13 0.0005303166 + +*END + +*D_NET chanx_left_in[18] 0.01693651 //LENGTH 118.885 LUMPCC 0.004598254 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 68.000 +*I mux_bottom_track_9\/mux_l2_in_3_:A1 I *L 0.00198 *C 69.000 45.220 +*I mux_top_track_8\/mux_l2_in_3_:A1 I *L 0.00198 *C 75.900 83.300 +*N chanx_left_in[18]:3 *C 75.862 83.300 +*N chanx_left_in[18]:4 *C 69.965 83.300 +*N chanx_left_in[18]:5 *C 69.920 83.255 +*N chanx_left_in[18]:6 *C 69.038 45.220 +*N chanx_left_in[18]:7 *C 69.415 45.220 +*N chanx_left_in[18]:8 *C 69.460 45.265 +*N chanx_left_in[18]:9 *C 69.460 52.700 +*N chanx_left_in[18]:10 *C 69.920 52.700 +*N chanx_left_in[18]:11 *C 69.920 68.680 +*N chanx_left_in[18]:12 *C 69.915 68.672 +*N chanx_left_in[18]:13 *C 69.460 68.668 +*N chanx_left_in[18]:14 *C 69.460 68.000 +*N chanx_left_in[18]:15 *C 44.620 68.000 +*N chanx_left_in[18]:16 *C 44.620 68.680 +*N chanx_left_in[18]:17 *C 40.480 68.680 +*N chanx_left_in[18]:18 *C 40.480 68.000 + +*CAP +0 chanx_left_in[18] 0.001640072 +1 mux_bottom_track_9\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_8\/mux_l2_in_3_:A1 1e-06 +3 chanx_left_in[18]:3 0.0003741844 +4 chanx_left_in[18]:4 0.0003741844 +5 chanx_left_in[18]:5 0.0006795956 +6 chanx_left_in[18]:6 6.415389e-05 +7 chanx_left_in[18]:7 6.415389e-05 +8 chanx_left_in[18]:8 0.0003087898 +9 chanx_left_in[18]:9 0.0003384437 +10 chanx_left_in[18]:10 0.0007297355 +11 chanx_left_in[18]:11 0.001416249 +12 chanx_left_in[18]:12 7.594622e-05 +13 chanx_left_in[18]:13 0.0001380672 +14 chanx_left_in[18]:14 0.001848831 +15 chanx_left_in[18]:15 0.001848223 +16 chanx_left_in[18]:16 0.0003631587 +17 chanx_left_in[18]:17 0.0003670205 +18 chanx_left_in[18]:18 0.001705447 +19 chanx_left_in[18]:8 chany_top_in[6]:11 0.0001900826 +20 chanx_left_in[18]:5 chany_top_in[6]:16 0.0001037566 +21 chanx_left_in[18]:11 chany_top_in[6]:15 0.0001056102 +22 chanx_left_in[18]:11 chany_top_in[6]:16 0.0001796807 +23 chanx_left_in[18]:9 chany_top_in[6]:15 0.0001900826 +24 chanx_left_in[18]:10 chany_top_in[6]:11 1.853638e-06 +25 chanx_left_in[18]:10 chany_top_in[6]:15 0.0001796807 +26 chanx_left_in[18]:14 chany_top_in[6]:15 1.010263e-05 +27 chanx_left_in[18]:13 chany_top_in[6]:16 1.010263e-05 +28 chanx_left_in[18] prog_clk[0]:381 0.0001697235 +29 chanx_left_in[18] prog_clk[0]:382 9.963858e-05 +30 chanx_left_in[18] prog_clk[0]:488 5.677631e-05 +31 chanx_left_in[18]:18 prog_clk[0]:378 0.0001697235 +32 chanx_left_in[18]:18 prog_clk[0]:381 9.963858e-05 +33 chanx_left_in[18]:18 prog_clk[0]:487 5.677631e-05 +34 chanx_left_in[18]:15 prog_clk[0]:221 5.969785e-05 +35 chanx_left_in[18]:14 prog_clk[0]:220 5.969785e-05 +36 chanx_left_in[18] mux_tree_tapbuf_size7_5_sram[0]:15 0.0009518908 +37 chanx_left_in[18]:18 mux_tree_tapbuf_size7_5_sram[0]:14 0.0009518908 +38 chanx_left_in[18] mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002313176 +39 chanx_left_in[18]:18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0002313176 +40 chanx_left_in[18]:17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.017637e-06 +41 chanx_left_in[18]:16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.017637e-06 +42 chanx_left_in[18]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.414838e-07 +43 chanx_left_in[18]:14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 9.414838e-07 +44 chanx_left_in[18] mem_left_track_25/net_net_84:5 0.0001378847 +45 chanx_left_in[18]:18 mem_left_track_25/net_net_84:6 0.0001378847 +46 chanx_left_in[18]:17 mem_left_track_25/net_net_84:5 8.383745e-05 +47 chanx_left_in[18]:16 mem_left_track_25/net_net_84:7 6.315831e-06 +48 chanx_left_in[18]:16 mem_left_track_25/net_net_84:6 8.383745e-05 +49 chanx_left_in[18]:15 mem_left_track_25/net_net_84:5 1.060909e-05 +50 chanx_left_in[18]:15 mem_left_track_25/net_net_84:8 6.315831e-06 +51 chanx_left_in[18]:14 mem_left_track_25/net_net_84:6 1.060909e-05 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:18 0.006149166 +1 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0003370536 +2 chanx_left_in[18]:8 chanx_left_in[18]:7 0.0045 +3 chanx_left_in[18]:6 mux_bottom_track_9\/mux_l2_in_3_:A1 0.152 +4 chanx_left_in[18]:4 chanx_left_in[18]:3 0.005265625 +5 chanx_left_in[18]:5 chanx_left_in[18]:4 0.0045 +6 chanx_left_in[18]:3 mux_top_track_8\/mux_l2_in_3_:A1 0.152 +7 chanx_left_in[18]:11 chanx_left_in[18]:10 0.01426786 +8 chanx_left_in[18]:11 chanx_left_in[18]:5 0.01301339 +9 chanx_left_in[18]:12 chanx_left_in[18]:11 0.00341 +10 chanx_left_in[18]:9 chanx_left_in[18]:8 0.006638394 +11 chanx_left_in[18]:10 chanx_left_in[18]:9 0.0004107143 +12 chanx_left_in[18]:18 chanx_left_in[18]:17 0.0001065333 +13 chanx_left_in[18]:17 chanx_left_in[18]:16 0.0006486 +14 chanx_left_in[18]:16 chanx_left_in[18]:15 0.0001065333 +15 chanx_left_in[18]:15 chanx_left_in[18]:14 0.0038916 +16 chanx_left_in[18]:14 chanx_left_in[18]:13 0.000104575 +17 chanx_left_in[18]:13 chanx_left_in[18]:12 6.788888e-05 + +*END + +*D_NET chanx_left_out[6] 0.0007947308 //LENGTH 5.590 LUMPCC 0 DR + +*CONN +*I mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 47.940 +*P chanx_left_out[6] O *L 0.7423 *C 1.230 50.320 +*N chanx_left_out[6]:2 *C 3.213 50.320 +*N chanx_left_out[6]:3 *C 3.220 50.263 +*N chanx_left_out[6]:4 *C 3.220 47.985 +*N chanx_left_out[6]:5 *C 3.243 47.940 +*N chanx_left_out[6]:6 *C 3.610 47.940 + +*CAP +0 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[6] 0.0002030742 +2 chanx_left_out[6]:2 0.0002030742 +3 chanx_left_out[6]:3 0.0001514047 +4 chanx_left_out[6]:4 0.0001514047 +5 chanx_left_out[6]:5 4.238647e-05 +6 chanx_left_out[6]:6 4.238647e-05 + +*RES +0 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:6 chanx_left_out[6]:5 0.0001997283 +2 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +3 chanx_left_out[6]:4 chanx_left_out[6]:3 0.002033482 +4 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +5 chanx_left_out[6]:2 chanx_left_out[6] 0.0003105917 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[0] 0.01091967 //LENGTH 87.380 LUMPCC 0.001481511 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.805 71.740 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 58.595 28.220 +*I mux_bottom_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 55.760 17.975 +*I mux_bottom_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 55.300 14.960 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 56.680 23.415 +*N mux_tree_tapbuf_size10_1_sram[0]:5 *C 56.680 23.415 +*N mux_tree_tapbuf_size10_1_sram[0]:6 *C 55.200 14.960 +*N mux_tree_tapbuf_size10_1_sram[0]:7 *C 55.200 15.005 +*N mux_tree_tapbuf_size10_1_sram[0]:8 *C 55.200 18.360 +*N mux_tree_tapbuf_size10_1_sram[0]:9 *C 55.760 17.975 +*N mux_tree_tapbuf_size10_1_sram[0]:10 *C 55.760 18.360 +*N mux_tree_tapbuf_size10_1_sram[0]:11 *C 56.535 18.360 +*N mux_tree_tapbuf_size10_1_sram[0]:12 *C 56.580 18.405 +*N mux_tree_tapbuf_size10_1_sram[0]:13 *C 56.580 23.075 +*N mux_tree_tapbuf_size10_1_sram[0]:14 *C 56.738 23.120 +*N mux_tree_tapbuf_size10_1_sram[0]:15 *C 58.375 23.120 +*N mux_tree_tapbuf_size10_1_sram[0]:16 *C 58.420 23.165 +*N mux_tree_tapbuf_size10_1_sram[0]:17 *C 58.420 28.175 +*N mux_tree_tapbuf_size10_1_sram[0]:18 *C 58.420 28.220 +*N mux_tree_tapbuf_size10_1_sram[0]:19 *C 58.595 28.220 +*N mux_tree_tapbuf_size10_1_sram[0]:20 *C 58.880 28.220 +*N mux_tree_tapbuf_size10_1_sram[0]:21 *C 58.880 28.265 +*N mux_tree_tapbuf_size10_1_sram[0]:22 *C 58.880 35.983 +*N mux_tree_tapbuf_size10_1_sram[0]:23 *C 58.888 36.040 +*N mux_tree_tapbuf_size10_1_sram[0]:24 *C 80.032 36.040 +*N mux_tree_tapbuf_size10_1_sram[0]:25 *C 80.040 36.098 +*N mux_tree_tapbuf_size10_1_sram[0]:26 *C 80.040 71.695 +*N mux_tree_tapbuf_size10_1_sram[0]:27 *C 80.085 71.740 +*N mux_tree_tapbuf_size10_1_sram[0]:28 *C 80.767 71.740 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_1\/mux_l1_in_1_:S 1e-06 +3 mux_bottom_track_1\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size10_1_sram[0]:5 5.921191e-05 +6 mux_tree_tapbuf_size10_1_sram[0]:6 3.474808e-05 +7 mux_tree_tapbuf_size10_1_sram[0]:7 0.0001973665 +8 mux_tree_tapbuf_size10_1_sram[0]:8 0.0002802981 +9 mux_tree_tapbuf_size10_1_sram[0]:9 6.291724e-05 +10 mux_tree_tapbuf_size10_1_sram[0]:10 0.0001081987 +11 mux_tree_tapbuf_size10_1_sram[0]:11 7.499267e-05 +12 mux_tree_tapbuf_size10_1_sram[0]:12 0.000418555 +13 mux_tree_tapbuf_size10_1_sram[0]:13 0.0003356234 +14 mux_tree_tapbuf_size10_1_sram[0]:14 0.0002149746 +15 mux_tree_tapbuf_size10_1_sram[0]:15 0.0001830002 +16 mux_tree_tapbuf_size10_1_sram[0]:16 0.0002322862 +17 mux_tree_tapbuf_size10_1_sram[0]:17 0.0002322862 +18 mux_tree_tapbuf_size10_1_sram[0]:18 5.712048e-05 +19 mux_tree_tapbuf_size10_1_sram[0]:19 7.4535e-05 +20 mux_tree_tapbuf_size10_1_sram[0]:20 5.716555e-05 +21 mux_tree_tapbuf_size10_1_sram[0]:21 0.0003287605 +22 mux_tree_tapbuf_size10_1_sram[0]:22 0.0003287605 +23 mux_tree_tapbuf_size10_1_sram[0]:23 0.001434658 +24 mux_tree_tapbuf_size10_1_sram[0]:24 0.001434658 +25 mux_tree_tapbuf_size10_1_sram[0]:25 0.001580606 +26 mux_tree_tapbuf_size10_1_sram[0]:26 0.001580606 +27 mux_tree_tapbuf_size10_1_sram[0]:27 6.091353e-05 +28 mux_tree_tapbuf_size10_1_sram[0]:28 6.091353e-05 +29 mux_tree_tapbuf_size10_1_sram[0]:21 chany_top_in[12]:13 0.0002090656 +30 mux_tree_tapbuf_size10_1_sram[0]:22 chany_top_in[12]:16 0.0002090656 +31 mux_tree_tapbuf_size10_1_sram[0]:17 chany_top_in[12]:16 5.781537e-05 +32 mux_tree_tapbuf_size10_1_sram[0]:16 chany_top_in[12]:13 5.781537e-05 +33 mux_tree_tapbuf_size10_1_sram[0]:25 chany_bottom_in[12] 0.0004738747 +34 mux_tree_tapbuf_size10_1_sram[0]:26 chany_bottom_in[12]:19 0.0004738747 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_1_sram[0]:28 0.152 +1 mux_tree_tapbuf_size10_1_sram[0]:6 mux_bottom_track_1\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[0]:7 mux_tree_tapbuf_size10_1_sram[0]:6 0.0045 +3 mux_tree_tapbuf_size10_1_sram[0]:11 mux_tree_tapbuf_size10_1_sram[0]:10 0.0006919643 +4 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:11 0.0045 +5 mux_tree_tapbuf_size10_1_sram[0]:12 mux_tree_tapbuf_size10_1_sram[0]:8 0.001232143 +6 mux_tree_tapbuf_size10_1_sram[0]:9 mux_bottom_track_1\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size10_1_sram[0]:20 mux_tree_tapbuf_size10_1_sram[0]:19 0.0001548913 +8 mux_tree_tapbuf_size10_1_sram[0]:21 mux_tree_tapbuf_size10_1_sram[0]:20 0.0045 +9 mux_tree_tapbuf_size10_1_sram[0]:22 mux_tree_tapbuf_size10_1_sram[0]:21 0.006890626 +10 mux_tree_tapbuf_size10_1_sram[0]:23 mux_tree_tapbuf_size10_1_sram[0]:22 0.00341 +11 mux_tree_tapbuf_size10_1_sram[0]:25 mux_tree_tapbuf_size10_1_sram[0]:24 0.00341 +12 mux_tree_tapbuf_size10_1_sram[0]:24 mux_tree_tapbuf_size10_1_sram[0]:23 0.003312716 +13 mux_tree_tapbuf_size10_1_sram[0]:27 mux_tree_tapbuf_size10_1_sram[0]:26 0.0045 +14 mux_tree_tapbuf_size10_1_sram[0]:26 mux_tree_tapbuf_size10_1_sram[0]:25 0.03178349 +15 mux_tree_tapbuf_size10_1_sram[0]:28 mux_tree_tapbuf_size10_1_sram[0]:27 0.000609375 +16 mux_tree_tapbuf_size10_1_sram[0]:18 mux_tree_tapbuf_size10_1_sram[0]:17 0.0045 +17 mux_tree_tapbuf_size10_1_sram[0]:17 mux_tree_tapbuf_size10_1_sram[0]:16 0.004473214 +18 mux_tree_tapbuf_size10_1_sram[0]:15 mux_tree_tapbuf_size10_1_sram[0]:14 0.001462054 +19 mux_tree_tapbuf_size10_1_sram[0]:16 mux_tree_tapbuf_size10_1_sram[0]:15 0.0045 +20 mux_tree_tapbuf_size10_1_sram[0]:19 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +21 mux_tree_tapbuf_size10_1_sram[0]:19 mux_tree_tapbuf_size10_1_sram[0]:18 9.51087e-05 +22 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:13 0.0045 +23 mux_tree_tapbuf_size10_1_sram[0]:14 mux_tree_tapbuf_size10_1_sram[0]:5 0.0001271552 +24 mux_tree_tapbuf_size10_1_sram[0]:13 mux_tree_tapbuf_size10_1_sram[0]:12 0.004169643 +25 mux_tree_tapbuf_size10_1_sram[0]:5 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 +26 mux_tree_tapbuf_size10_1_sram[0]:10 mux_tree_tapbuf_size10_1_sram[0]:9 0.00034375 +27 mux_tree_tapbuf_size10_1_sram[0]:8 mux_tree_tapbuf_size10_1_sram[0]:7 0.002995536 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001962051 //LENGTH 15.500 LUMPCC 0.0001520622 DR + +*CONN +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 35.265 60.860 +*I mux_left_track_19\/mux_l2_in_0_:S I *L 0.00357 *C 27.240 63.240 +*I mem_left_track_19\/FTB_24__56:A I *L 0.001746 *C 30.360 66.640 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 30.398 66.640 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 30.775 66.640 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 30.820 66.595 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 27.277 63.240 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 30.775 63.240 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 30.820 63.240 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 30.820 60.905 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 30.865 60.860 +*N mux_tree_tapbuf_size3_1_sram[1]:11 *C 35.227 60.860 + +*CAP +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_19\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_19\/FTB_24__56:A 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 5.877496e-05 +4 mux_tree_tapbuf_size3_1_sram[1]:4 5.877496e-05 +5 mux_tree_tapbuf_size3_1_sram[1]:5 0.000194275 +6 mux_tree_tapbuf_size3_1_sram[1]:6 0.0002343088 +7 mux_tree_tapbuf_size3_1_sram[1]:7 0.0002343088 +8 mux_tree_tapbuf_size3_1_sram[1]:8 0.0003437303 +9 mux_tree_tapbuf_size3_1_sram[1]:9 0.0001151242 +10 mux_tree_tapbuf_size3_1_sram[1]:10 0.0002838457 +11 mux_tree_tapbuf_size3_1_sram[1]:11 0.0002838457 +12 mux_tree_tapbuf_size3_1_sram[1]:9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.694094e-05 +13 mux_tree_tapbuf_size3_1_sram[1]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.057318e-05 +14 mux_tree_tapbuf_size3_1_sram[1]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.694094e-05 +15 mux_tree_tapbuf_size3_1_sram[1]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.516952e-06 +16 mux_tree_tapbuf_size3_1_sram[1]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.057318e-05 +17 mux_tree_tapbuf_size3_1_sram[1]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.516952e-06 + +*RES +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.0045 +2 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.002084822 +3 mux_tree_tapbuf_size3_1_sram[1]:11 mux_tree_tapbuf_size3_1_sram[1]:10 0.003895089 +4 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.003122768 +5 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:5 0.002995536 +7 mux_tree_tapbuf_size3_1_sram[1]:6 mux_left_track_19\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.0003370536 +9 mux_tree_tapbuf_size3_1_sram[1]:5 mux_tree_tapbuf_size3_1_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size3_1_sram[1]:3 mem_left_track_19\/FTB_24__56:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_2_ccff_tail[0] 0.0003225459 //LENGTH 2.530 LUMPCC 0 DR + +*CONN +*I mem_left_track_13\/FTB_21__53:X O *L 0 *C 35.195 49.980 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 37.435 49.980 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 *C 37.398 49.980 +*N mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 *C 35.233 49.980 + +*CAP +0 mem_left_track_13\/FTB_21__53:X 1e-06 +1 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 0.0001602729 +3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 0.0001602729 + +*RES +0 mem_left_track_13\/FTB_21__53:X mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_2_ccff_tail[0]:2 0.001933036 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.009412385 //LENGTH 69.805 LUMPCC 0.0008589668 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 61.485 34.000 +*I mux_bottom_track_25\/mux_l1_in_2_:S I *L 0.00357 *C 38.080 34.680 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 62.735 26.180 +*I mux_bottom_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 63.840 18.360 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 79.220 12.920 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 79.183 12.920 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 76.865 12.920 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 76.820 12.965 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 76.820 14.223 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 76.812 14.280 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 63.948 14.280 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 63.940 14.338 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 63.840 18.360 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 63.940 18.360 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 62.773 26.180 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 63.895 26.180 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 63.940 26.135 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 63.940 26.520 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 63.933 26.520 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 62.108 26.520 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 62.100 26.578 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 62.100 33.320 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 38.043 34.680 +*N mux_tree_tapbuf_size6_1_sram[0]:23 *C 37.720 34.680 +*N mux_tree_tapbuf_size6_1_sram[0]:24 *C 37.720 34.340 +*N mux_tree_tapbuf_size6_1_sram[0]:25 *C 42.275 34.340 +*N mux_tree_tapbuf_size6_1_sram[0]:26 *C 42.320 34.295 +*N mux_tree_tapbuf_size6_1_sram[0]:27 *C 42.320 33.378 +*N mux_tree_tapbuf_size6_1_sram[0]:28 *C 42.328 33.320 +*N mux_tree_tapbuf_size6_1_sram[0]:29 *C 61.633 33.320 +*N mux_tree_tapbuf_size6_1_sram[0]:30 *C 61.640 33.320 +*N mux_tree_tapbuf_size6_1_sram[0]:31 *C 61.640 33.955 +*N mux_tree_tapbuf_size6_1_sram[0]:32 *C 61.640 34.000 +*N mux_tree_tapbuf_size6_1_sram[0]:33 *C 61.485 34.000 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 0.0001719744 +6 mux_tree_tapbuf_size6_1_sram[0]:6 0.0001719744 +7 mux_tree_tapbuf_size6_1_sram[0]:7 9.852702e-05 +8 mux_tree_tapbuf_size6_1_sram[0]:8 9.852702e-05 +9 mux_tree_tapbuf_size6_1_sram[0]:9 0.0009157511 +10 mux_tree_tapbuf_size6_1_sram[0]:10 0.0009157511 +11 mux_tree_tapbuf_size6_1_sram[0]:11 0.0002407469 +12 mux_tree_tapbuf_size6_1_sram[0]:12 3.36563e-05 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0007515577 +14 mux_tree_tapbuf_size6_1_sram[0]:14 9.595526e-05 +15 mux_tree_tapbuf_size6_1_sram[0]:15 9.595526e-05 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.0005020313 +17 mux_tree_tapbuf_size6_1_sram[0]:17 5.591977e-05 +18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001530985 +19 mux_tree_tapbuf_size6_1_sram[0]:19 0.0001530985 +20 mux_tree_tapbuf_size6_1_sram[0]:20 0.0004117619 +21 mux_tree_tapbuf_size6_1_sram[0]:21 0.0004065681 +22 mux_tree_tapbuf_size6_1_sram[0]:22 4.736366e-05 +23 mux_tree_tapbuf_size6_1_sram[0]:23 7.27458e-05 +24 mux_tree_tapbuf_size6_1_sram[0]:24 0.0003029109 +25 mux_tree_tapbuf_size6_1_sram[0]:25 0.0002775287 +26 mux_tree_tapbuf_size6_1_sram[0]:26 7.923609e-05 +27 mux_tree_tapbuf_size6_1_sram[0]:27 7.923609e-05 +28 mux_tree_tapbuf_size6_1_sram[0]:28 0.00109538 +29 mux_tree_tapbuf_size6_1_sram[0]:29 0.00109538 +30 mux_tree_tapbuf_size6_1_sram[0]:30 5.810377e-05 +31 mux_tree_tapbuf_size6_1_sram[0]:31 6.329759e-05 +32 mux_tree_tapbuf_size6_1_sram[0]:32 5.316912e-05 +33 mux_tree_tapbuf_size6_1_sram[0]:33 5.12124e-05 +34 mux_tree_tapbuf_size6_1_sram[0]:29 chanx_left_in[1]:7 0.0003093918 +35 mux_tree_tapbuf_size6_1_sram[0]:29 chanx_left_in[1]:11 1.350543e-05 +36 mux_tree_tapbuf_size6_1_sram[0]:27 chanx_left_in[1]:10 3.612169e-06 +37 mux_tree_tapbuf_size6_1_sram[0]:28 chanx_left_in[1]:11 0.0003093918 +38 mux_tree_tapbuf_size6_1_sram[0]:28 chanx_left_in[1]:12 1.350543e-05 +39 mux_tree_tapbuf_size6_1_sram[0]:26 chanx_left_in[1]:9 3.612169e-06 +40 mux_tree_tapbuf_size6_1_sram[0]:30 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 3.918348e-05 +41 mux_tree_tapbuf_size6_1_sram[0]:32 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 1.253686e-05 +42 mux_tree_tapbuf_size6_1_sram[0]:33 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 1.253686e-05 +43 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 3.918348e-05 +44 mux_tree_tapbuf_size6_1_sram[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 2.796821e-06 +45 mux_tree_tapbuf_size6_1_sram[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.845682e-05 +46 mux_tree_tapbuf_size6_1_sram[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.796821e-06 +47 mux_tree_tapbuf_size6_1_sram[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.845682e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:33 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:30 mux_tree_tapbuf_size6_1_sram[0]:29 0.00341 +2 mux_tree_tapbuf_size6_1_sram[0]:30 mux_tree_tapbuf_size6_1_sram[0]:21 0.0004107143 +3 mux_tree_tapbuf_size6_1_sram[0]:29 mux_tree_tapbuf_size6_1_sram[0]:28 0.00302445 +4 mux_tree_tapbuf_size6_1_sram[0]:27 mux_tree_tapbuf_size6_1_sram[0]:26 0.0008191965 +5 mux_tree_tapbuf_size6_1_sram[0]:28 mux_tree_tapbuf_size6_1_sram[0]:27 0.00341 +6 mux_tree_tapbuf_size6_1_sram[0]:25 mux_tree_tapbuf_size6_1_sram[0]:24 0.004066965 +7 mux_tree_tapbuf_size6_1_sram[0]:26 mux_tree_tapbuf_size6_1_sram[0]:25 0.0045 +8 mux_tree_tapbuf_size6_1_sram[0]:22 mux_bottom_track_25\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size6_1_sram[0]:17 mux_tree_tapbuf_size6_1_sram[0]:16 0.0001850962 +10 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[0]:17 0.00341 +11 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.00341 +12 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.0002859167 +13 mux_tree_tapbuf_size6_1_sram[0]:12 mux_bottom_track_25\/mux_l1_in_1_:S 0.152 +14 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.0045 +15 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:11 0.003591518 +16 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 0.00341 +17 mux_tree_tapbuf_size6_1_sram[0]:10 mux_tree_tapbuf_size6_1_sram[0]:9 0.002015516 +18 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.001122768 +19 mux_tree_tapbuf_size6_1_sram[0]:9 mux_tree_tapbuf_size6_1_sram[0]:8 0.00341 +20 mux_tree_tapbuf_size6_1_sram[0]:6 mux_tree_tapbuf_size6_1_sram[0]:5 0.002069197 +21 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.0045 +22 mux_tree_tapbuf_size6_1_sram[0]:5 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +23 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.001002232 +24 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.0045 +25 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:13 0.006941965 +26 mux_tree_tapbuf_size6_1_sram[0]:14 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +27 mux_tree_tapbuf_size6_1_sram[0]:32 mux_tree_tapbuf_size6_1_sram[0]:31 0.0045 +28 mux_tree_tapbuf_size6_1_sram[0]:31 mux_tree_tapbuf_size6_1_sram[0]:30 0.0005669643 +29 mux_tree_tapbuf_size6_1_sram[0]:33 mux_tree_tapbuf_size6_1_sram[0]:32 8.423914e-05 +30 mux_tree_tapbuf_size6_1_sram[0]:24 mux_tree_tapbuf_size6_1_sram[0]:23 0.0003035715 +31 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:22 0.0002879465 +32 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.00602009 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[1] 0.003348574 //LENGTH 24.825 LUMPCC 0.000191767 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 25.145 69.700 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 11.675 66.300 +*I mux_left_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 16.660 72.375 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 26.320 72.080 +*N mux_tree_tapbuf_size7_5_sram[1]:4 *C 26.283 72.080 +*N mux_tree_tapbuf_size7_5_sram[1]:5 *C 16.660 72.375 +*N mux_tree_tapbuf_size7_5_sram[1]:6 *C 11.713 66.300 +*N mux_tree_tapbuf_size7_5_sram[1]:7 *C 15.595 66.300 +*N mux_tree_tapbuf_size7_5_sram[1]:8 *C 15.640 66.345 +*N mux_tree_tapbuf_size7_5_sram[1]:9 *C 15.640 72.035 +*N mux_tree_tapbuf_size7_5_sram[1]:10 *C 15.685 72.080 +*N mux_tree_tapbuf_size7_5_sram[1]:11 *C 16.660 72.080 +*N mux_tree_tapbuf_size7_5_sram[1]:12 *C 25.300 72.080 +*N mux_tree_tapbuf_size7_5_sram[1]:13 *C 25.300 72.035 +*N mux_tree_tapbuf_size7_5_sram[1]:14 *C 25.300 69.745 +*N mux_tree_tapbuf_size7_5_sram[1]:15 *C 25.300 69.700 +*N mux_tree_tapbuf_size7_5_sram[1]:16 *C 25.145 69.700 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_5\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_5_sram[1]:4 7.054306e-05 +5 mux_tree_tapbuf_size7_5_sram[1]:5 6.038973e-05 +6 mux_tree_tapbuf_size7_5_sram[1]:6 0.0002741217 +7 mux_tree_tapbuf_size7_5_sram[1]:7 0.0002741217 +8 mux_tree_tapbuf_size7_5_sram[1]:8 0.00039368 +9 mux_tree_tapbuf_size7_5_sram[1]:9 0.00039368 +10 mux_tree_tapbuf_size7_5_sram[1]:10 6.3923e-05 +11 mux_tree_tapbuf_size7_5_sram[1]:11 0.0006162258 +12 mux_tree_tapbuf_size7_5_sram[1]:12 0.0006278668 +13 mux_tree_tapbuf_size7_5_sram[1]:13 0.0001372299 +14 mux_tree_tapbuf_size7_5_sram[1]:14 0.0001372299 +15 mux_tree_tapbuf_size7_5_sram[1]:15 5.12614e-05 +16 mux_tree_tapbuf_size7_5_sram[1]:16 5.253366e-05 +17 mux_tree_tapbuf_size7_5_sram[1]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 1.153111e-06 +18 mux_tree_tapbuf_size7_5_sram[1]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.664235e-05 +19 mux_tree_tapbuf_size7_5_sram[1]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.153111e-06 +20 mux_tree_tapbuf_size7_5_sram[1]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.007342e-06 +21 mux_tree_tapbuf_size7_5_sram[1]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 7.308067e-05 +22 mux_tree_tapbuf_size7_5_sram[1]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.007342e-06 +23 mux_tree_tapbuf_size7_5_sram[1]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.308067e-05 +24 mux_tree_tapbuf_size7_5_sram[1]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 1.664235e-05 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_5_sram[1]:16 0.152 +1 mux_tree_tapbuf_size7_5_sram[1]:6 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_5_sram[1]:7 mux_tree_tapbuf_size7_5_sram[1]:6 0.003466518 +3 mux_tree_tapbuf_size7_5_sram[1]:8 mux_tree_tapbuf_size7_5_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size7_5_sram[1]:10 mux_tree_tapbuf_size7_5_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size7_5_sram[1]:9 mux_tree_tapbuf_size7_5_sram[1]:8 0.005080358 +6 mux_tree_tapbuf_size7_5_sram[1]:12 mux_tree_tapbuf_size7_5_sram[1]:11 0.007714286 +7 mux_tree_tapbuf_size7_5_sram[1]:12 mux_tree_tapbuf_size7_5_sram[1]:4 0.0008772321 +8 mux_tree_tapbuf_size7_5_sram[1]:13 mux_tree_tapbuf_size7_5_sram[1]:12 0.0045 +9 mux_tree_tapbuf_size7_5_sram[1]:15 mux_tree_tapbuf_size7_5_sram[1]:14 0.0045 +10 mux_tree_tapbuf_size7_5_sram[1]:14 mux_tree_tapbuf_size7_5_sram[1]:13 0.002044643 +11 mux_tree_tapbuf_size7_5_sram[1]:16 mux_tree_tapbuf_size7_5_sram[1]:15 8.423912e-05 +12 mux_tree_tapbuf_size7_5_sram[1]:4 mux_left_track_5\/mux_l2_in_0_:S 0.152 +13 mux_tree_tapbuf_size7_5_sram[1]:5 mux_left_track_5\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size7_5_sram[1]:11 mux_tree_tapbuf_size7_5_sram[1]:10 0.0008705358 +15 mux_tree_tapbuf_size7_5_sram[1]:11 mux_tree_tapbuf_size7_5_sram[1]:5 0.0001271552 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[0] 0.001664386 //LENGTH 14.605 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 80.805 109.820 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 75.615 107.780 +*I mux_top_track_8\/mux_l1_in_0_:S I *L 0.00357 *C 76.720 115.600 +*N mux_tree_tapbuf_size8_1_sram[0]:3 *C 76.705 115.600 +*N mux_tree_tapbuf_size8_1_sram[0]:4 *C 76.383 115.600 +*N mux_tree_tapbuf_size8_1_sram[0]:5 *C 76.360 115.555 +*N mux_tree_tapbuf_size8_1_sram[0]:6 *C 75.653 107.780 +*N mux_tree_tapbuf_size8_1_sram[0]:7 *C 76.315 107.780 +*N mux_tree_tapbuf_size8_1_sram[0]:8 *C 76.360 107.825 +*N mux_tree_tapbuf_size8_1_sram[0]:9 *C 76.360 109.820 +*N mux_tree_tapbuf_size8_1_sram[0]:10 *C 76.405 109.820 +*N mux_tree_tapbuf_size8_1_sram[0]:11 *C 80.767 109.820 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_8\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_1_sram[0]:3 4.385742e-05 +4 mux_tree_tapbuf_size8_1_sram[0]:4 4.385742e-05 +5 mux_tree_tapbuf_size8_1_sram[0]:5 0.0002992332 +6 mux_tree_tapbuf_size8_1_sram[0]:6 7.131459e-05 +7 mux_tree_tapbuf_size8_1_sram[0]:7 7.131459e-05 +8 mux_tree_tapbuf_size8_1_sram[0]:8 0.0001126721 +9 mux_tree_tapbuf_size8_1_sram[0]:9 0.0004430627 +10 mux_tree_tapbuf_size8_1_sram[0]:10 0.000288037 +11 mux_tree_tapbuf_size8_1_sram[0]:11 0.000288037 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_1_sram[0]:11 0.152 +1 mux_tree_tapbuf_size8_1_sram[0]:3 mux_top_track_8\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[0]:4 mux_tree_tapbuf_size8_1_sram[0]:3 0.0001752718 +3 mux_tree_tapbuf_size8_1_sram[0]:5 mux_tree_tapbuf_size8_1_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size8_1_sram[0]:7 mux_tree_tapbuf_size8_1_sram[0]:6 0.0005915179 +5 mux_tree_tapbuf_size8_1_sram[0]:8 mux_tree_tapbuf_size8_1_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size8_1_sram[0]:6 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size8_1_sram[0]:10 mux_tree_tapbuf_size8_1_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:8 0.00178125 +9 mux_tree_tapbuf_size8_1_sram[0]:9 mux_tree_tapbuf_size8_1_sram[0]:5 0.005120536 +10 mux_tree_tapbuf_size8_1_sram[0]:11 mux_tree_tapbuf_size8_1_sram[0]:10 0.003895089 + +*END + +*D_NET mux_tree_tapbuf_size9_mem_0_ccff_tail[0] 0.0006633591 //LENGTH 4.570 LUMPCC 0.0001137732 DR + +*CONN +*I mem_bottom_track_3\/FTB_18__50:X O *L 0 *C 31.055 44.540 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 29.155 42.500 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 *C 29.155 42.500 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 *C 29.440 42.500 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 *C 29.440 42.545 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 *C 29.440 44.495 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 *C 29.485 44.540 +*N mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 *C 31.018 44.540 + +*CAP +0 mem_bottom_track_3\/FTB_18__50:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 4.841955e-05 +3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 5.274075e-05 +4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 0.0001305524 +5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 0.0001305524 +6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 9.266038e-05 +7 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 9.266038e-05 +8 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 chanx_left_in[19]:19 5.688661e-05 +9 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 chanx_left_in[19]:18 5.688661e-05 + +*RES +0 mem_bottom_track_3\/FTB_18__50:X mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size9_mem_0_ccff_tail[0]:6 0.001368304 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001143653 //LENGTH 8.550 LUMPCC 0.0003281714 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_1_:X O *L 0 *C 54.915 18.360 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 51.375 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 51.413 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 54.235 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 54.280 22.395 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 54.280 18.405 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 54.325 18.360 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 54.878 18.360 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000145923 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000145923 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001936814 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001936814 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.713629e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.713629e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_1_sram[1]:25 5.056961e-06 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:21 6.909171e-07 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:28 9.677104e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_1_sram[1]:26 5.056961e-06 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:20 6.909171e-07 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:27 9.677104e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 6.116813e-05 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 3.986568e-07 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 6.116813e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 3.986568e-07 + +*RES +0 mux_bottom_track_1\/mux_l1_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0035625 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002520089 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET optlc_net_138 0.01037815 //LENGTH 81.855 LUMPCC 0.001778067 DR + +*CONN +*I optlc_134:HI O *L 0 *C 69.000 82.620 +*I mux_top_track_4\/mux_l2_in_3_:A0 I *L 0.001631 *C 55.835 102.680 +*I mux_top_track_32\/mux_l2_in_1_:A0 I *L 0.001631 *C 73.775 75.140 +*I mux_left_track_9\/mux_l2_in_1_:A0 I *L 0.001631 *C 71.935 69.700 +*I mux_left_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 51.350 66.300 +*I mux_top_track_8\/mux_l2_in_3_:A0 I *L 0.001631 *C 76.075 82.620 +*N optlc_net_138:6 *C 76.038 82.620 +*N optlc_net_138:7 *C 51.388 66.300 +*N optlc_net_138:8 *C 67.575 66.300 +*N optlc_net_138:9 *C 67.620 66.345 +*N optlc_net_138:10 *C 67.620 69.315 +*N optlc_net_138:11 *C 67.665 69.360 +*N optlc_net_138:12 *C 71.935 69.360 +*N optlc_net_138:13 *C 71.935 69.678 +*N optlc_net_138:14 *C 73.555 69.700 +*N optlc_net_138:15 *C 73.600 69.745 +*N optlc_net_138:16 *C 73.775 75.140 +*N optlc_net_138:17 *C 73.600 75.140 +*N optlc_net_138:18 *C 73.600 75.140 +*N optlc_net_138:19 *C 73.600 82.575 +*N optlc_net_138:20 *C 73.600 82.620 +*N optlc_net_138:21 *C 55.873 102.680 +*N optlc_net_138:22 *C 60.215 102.680 +*N optlc_net_138:23 *C 60.260 102.635 +*N optlc_net_138:24 *C 60.260 82.665 +*N optlc_net_138:25 *C 60.305 82.620 +*N optlc_net_138:26 *C 69.000 82.620 + +*CAP +0 optlc_134:HI 1e-06 +1 mux_top_track_4\/mux_l2_in_3_:A0 1e-06 +2 mux_top_track_32\/mux_l2_in_1_:A0 1e-06 +3 mux_left_track_9\/mux_l2_in_1_:A0 1e-06 +4 mux_left_track_25\/mux_l1_in_1_:A0 1e-06 +5 mux_top_track_8\/mux_l2_in_3_:A0 1e-06 +6 optlc_net_138:6 0.0001558087 +7 optlc_net_138:7 0.0006622682 +8 optlc_net_138:8 0.0006622681 +9 optlc_net_138:9 0.0001941159 +10 optlc_net_138:10 0.0001941159 +11 optlc_net_138:11 0.0002846515 +12 optlc_net_138:12 0.0003124626 +13 optlc_net_138:13 0.0001854173 +14 optlc_net_138:14 0.0001576062 +15 optlc_net_138:15 0.0003313344 +16 optlc_net_138:16 5.482563e-05 +17 optlc_net_138:17 5.602593e-05 +18 optlc_net_138:18 0.000758775 +19 optlc_net_138:19 0.0003959305 +20 optlc_net_138:20 0.0004609463 +21 optlc_net_138:21 0.0003177156 +22 optlc_net_138:22 0.0003177156 +23 optlc_net_138:23 0.0008975451 +24 optlc_net_138:24 0.0008975451 +25 optlc_net_138:25 0.0004996623 +26 optlc_net_138:26 0.0007973486 +27 optlc_net_138:24 chany_top_in[2]:15 0.0002442549 +28 optlc_net_138:24 chany_top_in[2]:18 5.865822e-05 +29 optlc_net_138:23 chany_top_in[2]:18 0.0002442549 +30 optlc_net_138:23 chany_top_in[2]:19 5.865822e-05 +31 optlc_net_138:15 chany_bottom_in[18]:15 5.293345e-08 +32 optlc_net_138:18 chany_bottom_in[18]:14 5.293345e-08 +33 optlc_net_138:8 chany_bottom_in[18]:16 0.0003002571 +34 optlc_net_138:8 chany_bottom_in[18]:17 3.334418e-05 +35 optlc_net_138:7 chany_bottom_in[18]:17 0.0003002571 +36 optlc_net_138:7 chany_bottom_in[18]:18 3.334418e-05 +37 optlc_net_138:8 mux_tree_tapbuf_size3_4_sram[0]:4 4.01661e-05 +38 optlc_net_138:8 mux_tree_tapbuf_size3_4_sram[0]:9 0.000172298 +39 optlc_net_138:8 mux_tree_tapbuf_size3_4_sram[0]:11 4.000202e-05 +40 optlc_net_138:7 mux_tree_tapbuf_size3_4_sram[0]:9 4.01661e-05 +41 optlc_net_138:7 mux_tree_tapbuf_size3_4_sram[0]:10 4.000202e-05 +42 optlc_net_138:7 mux_tree_tapbuf_size3_4_sram[0]:11 0.000172298 + +*RES +0 optlc_134:HI optlc_net_138:26 0.152 +1 optlc_net_138:25 optlc_net_138:24 0.0045 +2 optlc_net_138:24 optlc_net_138:23 0.01783036 +3 optlc_net_138:22 optlc_net_138:21 0.003877232 +4 optlc_net_138:23 optlc_net_138:22 0.0045 +5 optlc_net_138:21 mux_top_track_4\/mux_l2_in_3_:A0 0.152 +6 optlc_net_138:20 optlc_net_138:19 0.0045 +7 optlc_net_138:20 optlc_net_138:6 0.002176339 +8 optlc_net_138:19 optlc_net_138:18 0.006638393 +9 optlc_net_138:6 mux_top_track_8\/mux_l2_in_3_:A0 0.152 +10 optlc_net_138:14 optlc_net_138:13 0.001446429 +11 optlc_net_138:15 optlc_net_138:14 0.0045 +12 optlc_net_138:26 optlc_net_138:25 0.007763393 +13 optlc_net_138:26 optlc_net_138:20 0.004107143 +14 optlc_net_138:17 optlc_net_138:16 9.51087e-05 +15 optlc_net_138:18 optlc_net_138:17 0.0045 +16 optlc_net_138:18 optlc_net_138:15 0.004816965 +17 optlc_net_138:16 mux_top_track_32\/mux_l2_in_1_:A0 0.152 +18 optlc_net_138:11 optlc_net_138:10 0.0045 +19 optlc_net_138:10 optlc_net_138:9 0.002651786 +20 optlc_net_138:8 optlc_net_138:7 0.01445313 +21 optlc_net_138:9 optlc_net_138:8 0.0045 +22 optlc_net_138:7 mux_left_track_25\/mux_l1_in_1_:A0 0.152 +23 optlc_net_138:13 mux_left_track_9\/mux_l2_in_1_:A0 0.152 +24 optlc_net_138:13 optlc_net_138:12 0.0002834821 +25 optlc_net_138:12 optlc_net_138:11 0.0038125 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0] 0.005886362 //LENGTH 37.870 LUMPCC 0.002028712 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_1_:X O *L 0 *C 75.615 87.720 +*I mux_top_track_24\/mux_l2_in_0_:A0 I *L 0.001631 *C 38.815 88.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 38.852 88.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 46.415 88.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 46.460 88.060 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 46.460 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 46.468 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 75.433 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 75.440 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 75.440 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 75.615 87.720 + +*CAP +0 mux_top_track_24\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004203934 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0004203934 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.690701e-05 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.03893e-05 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001394315 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001394315 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:8 3.378048e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 4.729205e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 4.786413e-05 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_top_in[17]:26 0.0002379814 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_top_in[17]:27 0.0002379814 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:450 0.0002094342 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:449 0.0002094342 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_1_sram[0]:28 1.119677e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_1_sram[0]:29 1.119677e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:31 0.0004513477 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:35 1.120646e-05 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_1_sram[0]:6 1.120646e-05 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_1_sram[0]:32 0.0004513477 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size7_1_sram[0]:35 6.261232e-06 +22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size7_1_sram[0]:6 6.261232e-06 +23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.692814e-05 +24 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.692814e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.006752233 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001634615 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00453785 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 9.51087e-05 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.004033232 //LENGTH 29.150 LUMPCC 0.000916302 DR + +*CONN +*I mux_left_track_1\/mux_l3_in_0_:X O *L 0 *C 19.955 88.400 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 8.495 71.930 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 8.495 71.930 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 8.740 72.080 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 8.740 72.125 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 8.740 73.383 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 8.748 73.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 17.933 73.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 17.940 73.498 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 17.940 88.355 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 17.985 88.400 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 19.918 88.400 + +*CAP +0 mux_left_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 5.133069e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 5.255363e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.340796e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.340796e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0005274389 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0005274389 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0007151719 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0007151719 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0001695039 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0001695039 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 chanx_left_in[9]:10 0.0001947068 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 chanx_left_in[9] 0.0001947068 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.792631e-05 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.792631e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.087961e-05 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.087961e-05 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001146383 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001146383 + +*RES +0 mux_left_track_1\/mux_l3_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.001725447 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.01326563 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.00341 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001438983 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.001122768 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.00341 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001331522 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0] 0.004172576 //LENGTH 27.725 LUMPCC 0.0009746797 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_2_:X O *L 0 *C 50.425 71.400 +*I mux_top_track_32\/mux_l2_in_1_:A1 I *L 0.00198 *C 74.160 74.460 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 74.123 74.460 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 72.725 74.460 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 72.680 74.415 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 72.680 71.445 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 72.635 71.400 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 50.463 71.400 + +*CAP +0 mux_top_track_32\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001647209 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001647209 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000186279 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000186279 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001246948 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001246948 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[16]:18 0.0004873398 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[16]:17 0.0004873398 + +*RES +0 mux_top_track_32\/mux_l1_in_2_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_32\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001247768 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002651786 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01979688 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0] 0.006638476 //LENGTH 54.590 LUMPCC 0.001905079 DR + +*CONN +*I mux_bottom_track_33\/mux_l3_in_0_:X O *L 0 *C 18.225 31.960 +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 42.990 4.210 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 42.990 4.210 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 42.780 4.080 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 42.780 4.080 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 42.773 4.080 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 38.660 4.080 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 38.640 4.088 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 38.640 19.713 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 38.620 19.720 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 32.220 19.720 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 32.200 19.728 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 32.200 31.953 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 32.180 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 18.408 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 18.400 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:16 *C 18.400 31.960 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:17 *C 18.225 31.960 + +*CAP +0 mux_bottom_track_33\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 5.177671e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.058621e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.503519e-05 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001962468 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001962468 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0006584476 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0006584476 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0004454965 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0004454965 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0004633695 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0004633695 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0004518142 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0004518142 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:15 3.748165e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:16 6.409307e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:17 6.167433e-05 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[13]:32 0.0002696714 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chany_bottom_in[13]:34 1.424792e-05 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_in[13]:33 0.0002696714 +21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[13]:35 1.424792e-05 +22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 chany_bottom_in[0]:9 0.0001783391 +23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 chany_bottom_in[0]:10 0.0001783391 +24 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_bottom_in[0]:9 2.205755e-05 +25 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 chany_bottom_in[0]:11 5.916547e-05 +26 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 chany_bottom_in[0]:10 2.205755e-05 +27 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[0]:12 5.916547e-05 +28 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 chanx_left_in[6] 0.0002263193 +29 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 chanx_left_in[6]:10 0.0002263193 +30 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_tree_tapbuf_size6_2_sram[0]:22 0.0001827385 +31 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_tree_tapbuf_size6_2_sram[0]:23 0.0001827385 + +*RES +0 mux_bottom_track_33\/mux_l3_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:17 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:16 9.51087e-05 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:15 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.00341 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.002157691 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.00341 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.00191525 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.001002667 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.00341 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.00341 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.002447917 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0006442916 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.00341 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.00341 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001141304 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001154073 //LENGTH 9.695 LUMPCC 0.0001163377 DR + +*CONN +*I mux_left_track_19\/mux_l1_in_1_:X O *L 0 *C 26.965 58.140 +*I mux_left_track_19\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.350 64.260 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 28.388 64.260 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 28.935 64.260 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.980 64.215 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.980 58.185 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 28.935 58.140 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 27.003 58.140 + +*CAP +0 mux_left_track_19\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_19\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.594389e-05 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.594389e-05 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003184703 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003184703 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001234534 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001234534 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:489 2.854706e-05 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:493 6.439706e-06 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:494 8.829428e-06 +11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:493 6.741508e-06 +12 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:498 7.611151e-06 +13 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:492 6.439706e-06 +14 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:493 2.854706e-05 +15 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:498 8.829428e-06 +16 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:494 6.741508e-06 +17 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:497 7.611151e-06 + +*RES +0 mux_left_track_19\/mux_l1_in_1_:X mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_19\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004888393 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005383928 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001725447 + +*END + +*D_NET ropt_net_166 0.001864024 //LENGTH 12.845 LUMPCC 0.0006700837 DR + +*CONN +*I FTB_6__5:X O *L 0 *C 67.160 3.740 +*I ropt_mt_inst_791:A I *L 0.001766 *C 60.720 9.520 +*N ropt_net_166:2 *C 60.720 9.520 +*N ropt_net_166:3 *C 60.720 9.475 +*N ropt_net_166:4 *C 60.720 3.785 +*N ropt_net_166:5 *C 60.765 3.740 +*N ropt_net_166:6 *C 67.123 3.740 + +*CAP +0 FTB_6__5:X 1e-06 +1 ropt_mt_inst_791:A 1e-06 +2 ropt_net_166:2 3.585128e-05 +3 ropt_net_166:3 0.0002356843 +4 ropt_net_166:4 0.0002356843 +5 ropt_net_166:5 0.0003423601 +6 ropt_net_166:6 0.0003423601 +7 ropt_net_166:6 ropt_net_175:2 7.700004e-05 +8 ropt_net_166:5 ropt_net_175:3 7.700004e-05 +9 ropt_net_166:4 ropt_net_175:4 8.228298e-05 +10 ropt_net_166:3 ropt_net_175:5 8.228298e-05 +11 ropt_net_166:4 chany_bottom_out[7]:3 9.096628e-05 +12 ropt_net_166:3 chany_bottom_out[7]:4 9.096628e-05 +13 ropt_net_166:6 chany_bottom_out[13]:7 8.475751e-05 +14 ropt_net_166:5 chany_bottom_out[13]:6 8.475751e-05 +15 ropt_net_166:4 chany_bottom_out[13] 3.506963e-08 +16 ropt_net_166:3 chany_bottom_out[13]:2 3.506963e-08 + +*RES +0 FTB_6__5:X ropt_net_166:6 0.152 +1 ropt_net_166:6 ropt_net_166:5 0.005676339 +2 ropt_net_166:5 ropt_net_166:4 0.0045 +3 ropt_net_166:4 ropt_net_166:3 0.005080357 +4 ropt_net_166:2 ropt_mt_inst_791:A 0.152 +5 ropt_net_166:3 ropt_net_166:2 0.0045 + +*END + +*D_NET ropt_net_172 0.0007740638 //LENGTH 5.490 LUMPCC 0.0004047677 DR + +*CONN +*I FTB_24__23:X O *L 0 *C 57.960 123.760 +*I ropt_mt_inst_798:A I *L 0.001766 *C 59.800 121.040 +*N ropt_net_172:2 *C 59.763 121.040 +*N ropt_net_172:3 *C 58.925 121.040 +*N ropt_net_172:4 *C 58.880 121.085 +*N ropt_net_172:5 *C 58.880 123.715 +*N ropt_net_172:6 *C 58.835 123.760 +*N ropt_net_172:7 *C 57.998 123.760 + +*CAP +0 FTB_24__23:X 1e-06 +1 ropt_mt_inst_798:A 1e-06 +2 ropt_net_172:2 4.394085e-05 +3 ropt_net_172:3 4.394085e-05 +4 ropt_net_172:4 0.0001111274 +5 ropt_net_172:5 0.0001111274 +6 ropt_net_172:6 2.857987e-05 +7 ropt_net_172:7 2.857987e-05 +8 ropt_net_172:4 chany_bottom_in[12]:8 7.498272e-05 +9 ropt_net_172:6 chany_bottom_in[12]:5 2.23373e-05 +10 ropt_net_172:6 chany_bottom_in[12]:10 2.201458e-05 +11 ropt_net_172:5 chany_bottom_in[12]:9 7.498272e-05 +12 ropt_net_172:7 chany_bottom_in[12]:10 2.23373e-05 +13 ropt_net_172:7 chany_bottom_in[12]:11 2.201458e-05 +14 ropt_net_172:4 chany_top_out[1]:6 7.03258e-06 +15 ropt_net_172:6 chany_top_out[1]:7 3.370913e-05 +16 ropt_net_172:5 chany_top_out[1]:5 7.03258e-06 +17 ropt_net_172:7 chany_top_out[1]:8 3.370913e-05 +18 ropt_net_172:2 mux_tree_tapbuf_size10_0_sram[0]:20 4.230751e-05 +19 ropt_net_172:3 mux_tree_tapbuf_size10_0_sram[0]:19 4.230751e-05 + +*RES +0 FTB_24__23:X ropt_net_172:7 0.152 +1 ropt_net_172:2 ropt_mt_inst_798:A 0.152 +2 ropt_net_172:3 ropt_net_172:2 0.000747768 +3 ropt_net_172:4 ropt_net_172:3 0.0045 +4 ropt_net_172:6 ropt_net_172:5 0.0045 +5 ropt_net_172:5 ropt_net_172:4 0.002348214 +6 ropt_net_172:7 ropt_net_172:6 0.0007477679 + +*END + +*D_NET chany_top_out[9] 0.0006427668 //LENGTH 4.610 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_815:X O *L 0 *C 60.455 127.160 +*P chany_top_out[9] O *L 0.7423 *C 58.420 129.270 +*N chany_top_out[9]:2 *C 58.420 127.205 +*N chany_top_out[9]:3 *C 58.465 127.160 +*N chany_top_out[9]:4 *C 60.418 127.160 + +*CAP +0 ropt_mt_inst_815:X 1e-06 +1 chany_top_out[9] 0.000127056 +2 chany_top_out[9]:2 0.000127056 +3 chany_top_out[9]:3 0.0001938274 +4 chany_top_out[9]:4 0.0001938274 + +*RES +0 ropt_mt_inst_815:X chany_top_out[9]:4 0.152 +1 chany_top_out[9]:4 chany_top_out[9]:3 0.001743304 +2 chany_top_out[9]:3 chany_top_out[9]:2 0.0045 +3 chany_top_out[9]:2 chany_top_out[9] 0.00184375 + +*END + +*D_NET mem_left_track_25/net_net_83 0.0003247792 //LENGTH 2.735 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/BUFT_RR_84:X O *L 0 *C 9.345 63.920 +*I mem_left_track_25\/BUFT_RR_112:A I *L 0.001767 *C 6.900 63.920 +*N mem_left_track_25/net_net_83:2 *C 6.938 63.920 +*N mem_left_track_25/net_net_83:3 *C 9.308 63.920 + +*CAP +0 mem_left_track_25\/BUFT_RR_84:X 1e-06 +1 mem_left_track_25\/BUFT_RR_112:A 1e-06 +2 mem_left_track_25/net_net_83:2 0.0001613896 +3 mem_left_track_25/net_net_83:3 0.0001613896 + +*RES +0 mem_left_track_25\/BUFT_RR_84:X mem_left_track_25/net_net_83:3 0.152 +1 mem_left_track_25/net_net_83:2 mem_left_track_25\/BUFT_RR_112:A 0.152 +2 mem_left_track_25/net_net_83:3 mem_left_track_25/net_net_83:2 0.002116072 + +*END + +*D_NET chany_top_out[3] 0.0007780081 //LENGTH 5.530 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_821:X O *L 0 *C 74.255 127.160 +*P chany_top_out[3] O *L 0.7423 *C 71.300 129.270 +*N chany_top_out[3]:2 *C 71.300 127.205 +*N chany_top_out[3]:3 *C 71.345 127.160 +*N chany_top_out[3]:4 *C 74.218 127.160 + +*CAP +0 ropt_mt_inst_821:X 1e-06 +1 chany_top_out[3] 0.0001308148 +2 chany_top_out[3]:2 0.0001308148 +3 chany_top_out[3]:3 0.0002576892 +4 chany_top_out[3]:4 0.0002576892 + +*RES +0 ropt_mt_inst_821:X chany_top_out[3]:4 0.152 +1 chany_top_out[3]:4 chany_top_out[3]:3 0.002564732 +2 chany_top_out[3]:3 chany_top_out[3]:2 0.0045 +3 chany_top_out[3]:2 chany_top_out[3] 0.00184375 + +*END + +*D_NET chanx_left_out[15] 0.001047513 //LENGTH 8.735 LUMPCC 0.0001200921 DR + +*CONN +*I ropt_mt_inst_842:X O *L 0 *C 7.095 38.760 +*P chanx_left_out[15] O *L 0.7423 *C 1.298 40.800 +*N chanx_left_out[15]:2 *C 1.380 40.800 +*N chanx_left_out[15]:3 *C 1.380 40.742 +*N chanx_left_out[15]:4 *C 1.380 38.805 +*N chanx_left_out[15]:5 *C 1.425 38.760 +*N chanx_left_out[15]:6 *C 7.058 38.760 + +*CAP +0 ropt_mt_inst_842:X 1e-06 +1 chanx_left_out[15] 2.98526e-05 +2 chanx_left_out[15]:2 2.98526e-05 +3 chanx_left_out[15]:3 0.0001035449 +4 chanx_left_out[15]:4 0.0001035449 +5 chanx_left_out[15]:5 0.0003298128 +6 chanx_left_out[15]:6 0.0003298128 +7 chanx_left_out[15]:6 ropt_net_161:7 3.949875e-05 +8 chanx_left_out[15]:6 ropt_net_161:9 2.964517e-06 +9 chanx_left_out[15]:5 ropt_net_161:6 3.949875e-05 +10 chanx_left_out[15]:5 ropt_net_161:8 2.964517e-06 +11 chanx_left_out[15]:4 ropt_net_161:4 1.758279e-05 +12 chanx_left_out[15]:3 ropt_net_161:5 1.758279e-05 + +*RES +0 ropt_mt_inst_842:X chanx_left_out[15]:6 0.152 +1 chanx_left_out[15]:6 chanx_left_out[15]:5 0.005029018 +2 chanx_left_out[15]:5 chanx_left_out[15]:4 0.0045 +3 chanx_left_out[15]:4 chanx_left_out[15]:3 0.001729911 +4 chanx_left_out[15]:3 chanx_left_out[15]:2 0.00341 +5 chanx_left_out[15]:2 chanx_left_out[15] 2.35e-05 + +*END + +*D_NET chany_top_in[6] 0.01705357 //LENGTH 139.470 LUMPCC 0.004553272 DR + +*CONN +*P chany_top_in[6] I *L 0.29796 *C 74.980 129.270 +*I mux_left_track_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 69.460 52.700 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 72.220 14.620 +*I FTB_6__5:A I *L 0.001776 *C 69.460 4.080 +*N chany_top_in[6]:4 *C 69.422 4.080 +*N chany_top_in[6]:5 *C 68.585 4.080 +*N chany_top_in[6]:6 *C 68.540 4.125 +*N chany_top_in[6]:7 *C 68.540 14.960 +*N chany_top_in[6]:8 *C 72.220 14.620 +*N chany_top_in[6]:9 *C 72.220 14.960 +*N chany_top_in[6]:10 *C 69.045 14.960 +*N chany_top_in[6]:11 *C 69.000 15.005 +*N chany_top_in[6]:12 *C 69.422 52.700 +*N chany_top_in[6]:13 *C 69.000 52.700 +*N chany_top_in[6]:14 *C 69.000 53.380 +*N chany_top_in[6]:15 *C 69.000 53.380 +*N chany_top_in[6]:16 *C 69.000 76.782 +*N chany_top_in[6]:17 *C 69.008 76.840 +*N chany_top_in[6]:18 *C 74.972 76.840 +*N chany_top_in[6]:19 *C 74.980 76.898 + +*CAP +0 chany_top_in[6] 0.002324454 +1 mux_left_track_7\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +3 FTB_6__5:A 1e-06 +4 chany_top_in[6]:4 7.983706e-05 +5 chany_top_in[6]:5 7.983706e-05 +6 chany_top_in[6]:6 0.0007028147 +7 chany_top_in[6]:7 0.0007379734 +8 chany_top_in[6]:8 5.277071e-05 +9 chany_top_in[6]:9 0.0002827076 +10 chany_top_in[6]:10 0.0002565939 +11 chany_top_in[6]:11 0.001667348 +12 chany_top_in[6]:12 3.907521e-05 +13 chany_top_in[6]:13 8.801764e-05 +14 chany_top_in[6]:14 8.410491e-05 +15 chany_top_in[6]:15 0.002291283 +16 chany_top_in[6]:16 0.000627825 +17 chany_top_in[6]:17 0.0004290984 +18 chany_top_in[6]:18 0.0004290984 +19 chany_top_in[6]:19 0.002324454 +20 chany_top_in[6] chany_bottom_in[6]:29 0.0007358087 +21 chany_top_in[6]:19 chany_bottom_in[6]:30 0.0007358087 +22 chany_top_in[6]:16 chanx_left_in[4]:9 0.0006203312 +23 chany_top_in[6]:11 chanx_left_in[4]:5 0.0003504826 +24 chany_top_in[6]:15 chanx_left_in[4]:9 0.0003504826 +25 chany_top_in[6]:15 chanx_left_in[4]:5 0.0006203312 +26 chany_top_in[6]:16 chanx_left_in[18]:5 0.0001037566 +27 chany_top_in[6]:16 chanx_left_in[18]:11 0.0001796807 +28 chany_top_in[6]:16 chanx_left_in[18]:13 1.010263e-05 +29 chany_top_in[6]:11 chanx_left_in[18]:8 0.0001900826 +30 chany_top_in[6]:11 chanx_left_in[18]:10 1.853638e-06 +31 chany_top_in[6]:15 chanx_left_in[18]:11 0.0001056102 +32 chany_top_in[6]:15 chanx_left_in[18]:9 0.0001900826 +33 chany_top_in[6]:15 chanx_left_in[18]:10 0.0001796807 +34 chany_top_in[6]:15 chanx_left_in[18]:14 1.010263e-05 +35 chany_top_in[6]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.453763e-05 +36 chany_top_in[6]:15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.453763e-05 + +*RES +0 chany_top_in[6] chany_top_in[6]:19 0.04676116 +1 chany_top_in[6]:4 FTB_6__5:A 0.152 +2 chany_top_in[6]:5 chany_top_in[6]:4 0.0007477679 +3 chany_top_in[6]:6 chany_top_in[6]:5 0.0045 +4 chany_top_in[6]:16 chany_top_in[6]:15 0.02089509 +5 chany_top_in[6]:17 chany_top_in[6]:16 0.00341 +6 chany_top_in[6]:19 chany_top_in[6]:18 0.00341 +7 chany_top_in[6]:18 chany_top_in[6]:17 0.0009345167 +8 chany_top_in[6]:8 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +9 chany_top_in[6]:10 chany_top_in[6]:9 0.002834822 +10 chany_top_in[6]:11 chany_top_in[6]:10 0.0045 +11 chany_top_in[6]:11 chany_top_in[6]:7 0.0004107143 +12 chany_top_in[6]:14 chany_top_in[6]:13 0.0006071429 +13 chany_top_in[6]:15 chany_top_in[6]:14 0.0045 +14 chany_top_in[6]:15 chany_top_in[6]:11 0.03426339 +15 chany_top_in[6]:12 mux_left_track_7\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[6]:9 chany_top_in[6]:8 0.0003035715 +17 chany_top_in[6]:13 chany_top_in[6]:12 0.0003772322 +18 chany_top_in[6]:7 chany_top_in[6]:6 0.009674107 + +*END + +*D_NET chany_bottom_in[9] 0.01446711 //LENGTH 138.530 LUMPCC 0.0009526521 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 84.180 1.290 +*I mux_left_track_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 89.085 55.420 +*I mux_top_track_24\/mux_l1_in_1_:A1 I *L 0.00198 *C 77.185 88.740 +*I BUFT_P_125:A I *L 0.001776 *C 93.380 115.600 +*N chany_bottom_in[9]:4 *C 93.380 115.600 +*N chany_bottom_in[9]:5 *C 93.380 115.555 +*N chany_bottom_in[9]:6 *C 93.380 88.445 +*N chany_bottom_in[9]:7 *C 93.335 88.400 +*N chany_bottom_in[9]:8 *C 77.223 88.740 +*N chany_bottom_in[9]:9 *C 78.660 88.740 +*N chany_bottom_in[9]:10 *C 78.660 88.400 +*N chany_bottom_in[9]:11 *C 88.320 88.400 +*N chany_bottom_in[9]:12 *C 88.320 88.355 +*N chany_bottom_in[9]:13 *C 89.047 55.420 +*N chany_bottom_in[9]:14 *C 88.365 55.420 +*N chany_bottom_in[9]:15 *C 88.320 55.420 +*N chany_bottom_in[9]:16 *C 88.320 53.778 +*N chany_bottom_in[9]:17 *C 88.312 53.720 +*N chany_bottom_in[9]:18 *C 87.420 53.720 +*N chany_bottom_in[9]:19 *C 87.400 53.713 +*N chany_bottom_in[9]:20 *C 87.400 3.408 +*N chany_bottom_in[9]:21 *C 87.380 3.400 +*N chany_bottom_in[9]:22 *C 84.188 3.400 +*N chany_bottom_in[9]:23 *C 84.180 3.343 + +*CAP +0 chany_bottom_in[9] 0.0001383643 +1 mux_left_track_11\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_24\/mux_l1_in_1_:A1 1e-06 +3 BUFT_P_125:A 1e-06 +4 chany_bottom_in[9]:4 2.883451e-05 +5 chany_bottom_in[9]:5 0.001214697 +6 chany_bottom_in[9]:6 0.001214697 +7 chany_bottom_in[9]:7 0.0002604853 +8 chany_bottom_in[9]:8 0.0001140429 +9 chany_bottom_in[9]:9 0.0001388978 +10 chany_bottom_in[9]:10 0.0006470954 +11 chany_bottom_in[9]:11 0.0009106182 +12 chany_bottom_in[9]:12 0.001196724 +13 chany_bottom_in[9]:13 6.493014e-05 +14 chany_bottom_in[9]:14 6.493014e-05 +15 chany_bottom_in[9]:15 0.001319719 +16 chany_bottom_in[9]:16 9.19853e-05 +17 chany_bottom_in[9]:17 9.100528e-05 +18 chany_bottom_in[9]:18 9.100528e-05 +19 chany_bottom_in[9]:19 0.002639625 +20 chany_bottom_in[9]:20 0.002639625 +21 chany_bottom_in[9]:21 0.0002529084 +22 chany_bottom_in[9]:22 0.0002529084 +23 chany_bottom_in[9]:23 0.0001383643 +24 chany_bottom_in[9]:13 chany_top_in[9]:11 1.168594e-05 +25 chany_bottom_in[9]:14 chany_top_in[9]:10 1.168594e-05 +26 chany_bottom_in[9]:15 chany_top_in[9]:7 1.770132e-06 +27 chany_bottom_in[9]:15 chany_top_in[9]:8 5.072248e-06 +28 chany_bottom_in[9]:15 chany_top_in[9]:12 0.0004577977 +29 chany_bottom_in[9]:16 chany_top_in[9]:7 5.072248e-06 +30 chany_bottom_in[9]:12 chany_top_in[9]:8 1.770132e-06 +31 chany_bottom_in[9]:12 chany_top_in[9]:13 0.0004577977 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:23 0.001832589 +1 chany_bottom_in[9]:13 mux_left_track_11\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.000609375 +3 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.0045 +4 chany_bottom_in[9]:15 chany_bottom_in[9]:12 0.02940625 +5 chany_bottom_in[9]:8 mux_top_track_24\/mux_l1_in_1_:A1 0.152 +6 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.001466518 +7 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.00341 +8 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.000139825 +9 chany_bottom_in[9]:19 chany_bottom_in[9]:18 0.00341 +10 chany_bottom_in[9]:21 chany_bottom_in[9]:20 0.00341 +11 chany_bottom_in[9]:20 chany_bottom_in[9]:19 0.007881116 +12 chany_bottom_in[9]:23 chany_bottom_in[9]:22 0.00341 +13 chany_bottom_in[9]:22 chany_bottom_in[9]:21 0.0005001583 +14 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.0045 +15 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.02420536 +16 chany_bottom_in[9]:4 BUFT_P_125:A 0.152 +17 chany_bottom_in[9]:5 chany_bottom_in[9]:4 0.0045 +18 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.008625001 +19 chany_bottom_in[9]:11 chany_bottom_in[9]:7 0.004477679 +20 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.0045 +21 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.001283482 +22 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.0003035715 + +*END + +*D_NET chany_bottom_in[13] 0.03323592 //LENGTH 245.805 LUMPCC 0.01033233 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 68.080 1.290 +*I mux_left_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 30.190 53.720 +*I mux_top_track_2\/mux_l2_in_2_:A1 I *L 0.00198 *C 33.220 88.740 +*I ropt_mt_inst_775:A I *L 0.001767 *C 104.420 126.480 +*N chany_bottom_in[13]:4 *C 104.383 126.480 +*N chany_bottom_in[13]:5 *C 100.280 126.480 +*N chany_bottom_in[13]:6 *C 100.280 126.140 +*N chany_bottom_in[13]:7 *C 97.565 126.140 +*N chany_bottom_in[13]:8 *C 97.520 126.095 +*N chany_bottom_in[13]:9 *C 97.520 123.465 +*N chany_bottom_in[13]:10 *C 97.475 123.420 +*N chany_bottom_in[13]:11 *C 91.585 123.420 +*N chany_bottom_in[13]:12 *C 91.540 123.375 +*N chany_bottom_in[13]:13 *C 91.540 107.498 +*N chany_bottom_in[13]:14 *C 91.532 107.440 +*N chany_bottom_in[13]:15 *C 86.480 107.440 +*N chany_bottom_in[13]:16 *C 86.480 106.760 +*N chany_bottom_in[13]:17 *C 35.900 106.760 +*N chany_bottom_in[13]:18 *C 35.880 106.753 +*N chany_bottom_in[13]:19 *C 33.258 88.740 +*N chany_bottom_in[13]:20 *C 34.455 88.740 +*N chany_bottom_in[13]:21 *C 34.500 88.695 +*N chany_bottom_in[13]:22 *C 34.500 83.698 +*N chany_bottom_in[13]:23 *C 34.508 83.640 +*N chany_bottom_in[13]:24 *C 35.860 83.640 +*N chany_bottom_in[13]:25 *C 35.880 83.640 +*N chany_bottom_in[13]:26 *C 36.800 83.640 +*N chany_bottom_in[13]:27 *C 30.190 53.720 +*N chany_bottom_in[13]:28 *C 30.360 53.720 +*N chany_bottom_in[13]:29 *C 30.360 53.720 +*N chany_bottom_in[13]:30 *C 30.367 53.720 +*N chany_bottom_in[13]:31 *C 36.780 53.720 +*N chany_bottom_in[13]:32 *C 36.800 53.720 +*N chany_bottom_in[13]:33 *C 36.800 7.488 +*N chany_bottom_in[13]:34 *C 36.820 7.480 +*N chany_bottom_in[13]:35 *C 68.073 7.480 +*N chany_bottom_in[13]:36 *C 68.080 7.423 + +*CAP +0 chany_bottom_in[13] 0.0003221837 +1 mux_left_track_17\/mux_l1_in_0_:A0 1e-06 +2 mux_top_track_2\/mux_l2_in_2_:A1 1e-06 +3 ropt_mt_inst_775:A 1e-06 +4 chany_bottom_in[13]:4 0.00014391 +5 chany_bottom_in[13]:5 0.0001631142 +6 chany_bottom_in[13]:6 0.0002060008 +7 chany_bottom_in[13]:7 0.0001867966 +8 chany_bottom_in[13]:8 0.0001537906 +9 chany_bottom_in[13]:9 0.0001537906 +10 chany_bottom_in[13]:10 0.0002901939 +11 chany_bottom_in[13]:11 0.0002901939 +12 chany_bottom_in[13]:12 0.0007237758 +13 chany_bottom_in[13]:13 0.0007237758 +14 chany_bottom_in[13]:14 0.0003325488 +15 chany_bottom_in[13]:15 0.0003892527 +16 chany_bottom_in[13]:16 0.003360078 +17 chany_bottom_in[13]:17 0.003303374 +18 chany_bottom_in[13]:18 0.0009320001 +19 chany_bottom_in[13]:19 0.0001373718 +20 chany_bottom_in[13]:20 0.0001373718 +21 chany_bottom_in[13]:21 0.0003020674 +22 chany_bottom_in[13]:22 0.0003020674 +23 chany_bottom_in[13]:23 8.072176e-05 +24 chany_bottom_in[13]:24 8.072176e-05 +25 chany_bottom_in[13]:25 0.0009219412 +26 chany_bottom_in[13]:26 0.00100842 +27 chany_bottom_in[13]:27 4.959168e-05 +28 chany_bottom_in[13]:28 5.113104e-05 +29 chany_bottom_in[13]:29 3.208929e-05 +30 chany_bottom_in[13]:30 0.000352638 +31 chany_bottom_in[13]:31 0.000352638 +32 chany_bottom_in[13]:32 0.002363028 +33 chany_bottom_in[13]:33 0.001344549 +34 chany_bottom_in[13]:34 0.00169364 +35 chany_bottom_in[13]:35 0.00169364 +36 chany_bottom_in[13]:36 0.0003221837 +37 chany_bottom_in[13]:18 chany_top_in[11]:13 0.0004742627 +38 chany_bottom_in[13]:32 chany_top_in[11]:12 2.18388e-05 +39 chany_bottom_in[13]:25 chany_top_in[11]:12 0.0004742627 +40 chany_bottom_in[13]:26 chany_top_in[11]:13 2.18388e-05 +41 chany_bottom_in[13]:17 prog_clk[0]:436 0.000264163 +42 chany_bottom_in[13]:17 prog_clk[0]:317 2.498328e-05 +43 chany_bottom_in[13]:25 prog_clk[0]:283 2.732469e-05 +44 chany_bottom_in[13]:22 prog_clk[0]:342 5.32408e-06 +45 chany_bottom_in[13]:21 prog_clk[0]:341 5.32408e-06 +46 chany_bottom_in[13]:16 prog_clk[0]:435 0.000264163 +47 chany_bottom_in[13]:16 prog_clk[0]:316 2.498328e-05 +48 chany_bottom_in[13]:26 prog_clk[0]:282 2.732469e-05 +49 chany_bottom_in[13]:32 chany_bottom_in[0]:8 3.980461e-05 +50 chany_bottom_in[13]:32 chany_bottom_in[0]:9 0.001358134 +51 chany_bottom_in[13]:34 chany_bottom_in[0]:11 3.407435e-05 +52 chany_bottom_in[13]:33 chany_bottom_in[0]:10 0.0008842351 +53 chany_bottom_in[13]:33 chany_bottom_in[0]:9 3.980461e-05 +54 chany_bottom_in[13]:35 chany_bottom_in[0]:12 3.407435e-05 +55 chany_bottom_in[13]:26 chany_bottom_in[0]:8 0.0004738992 +56 chany_bottom_in[13] chany_bottom_in[1] 7.1089e-05 +57 chany_bottom_in[13]:32 chany_bottom_in[1]:9 0.0003185244 +58 chany_bottom_in[13]:32 chany_bottom_in[1]:10 2.793159e-07 +59 chany_bottom_in[13]:33 chany_bottom_in[1]:10 0.0003185244 +60 chany_bottom_in[13]:36 chany_bottom_in[1]:17 7.1089e-05 +61 chany_bottom_in[13]:26 chany_bottom_in[1]:9 2.793159e-07 +62 chany_bottom_in[13]:34 bottom_left_grid_pin_35_[0]:15 0.000450316 +63 chany_bottom_in[13]:35 bottom_left_grid_pin_35_[0]:11 0.000450316 +64 chany_bottom_in[13]:18 chanx_left_in[19]:11 0.0001179155 +65 chany_bottom_in[13]:32 chanx_left_in[19]:12 0.0005652575 +66 chany_bottom_in[13]:32 chanx_left_in[19]:11 2.937545e-05 +67 chany_bottom_in[13]:25 chanx_left_in[19]:12 0.0001179155 +68 chany_bottom_in[13]:33 chanx_left_in[19]:12 2.937545e-05 +69 chany_bottom_in[13]:26 chanx_left_in[19]:11 0.0005652575 +70 chany_bottom_in[13]:31 mux_tree_tapbuf_size4_3_sram[1]:18 0.0003651321 +71 chany_bottom_in[13]:30 mux_tree_tapbuf_size4_3_sram[1]:17 0.0003651321 +72 chany_bottom_in[13]:32 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0002696714 +73 chany_bottom_in[13]:34 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.424792e-05 +74 chany_bottom_in[13]:33 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002696714 +75 chany_bottom_in[13]:35 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.424792e-05 +76 chany_bottom_in[13]:24 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 9.45224e-05 +77 chany_bottom_in[13]:25 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.678254e-05 +78 chany_bottom_in[13]:23 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.45224e-05 +79 chany_bottom_in[13]:26 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.678254e-05 +80 chany_bottom_in[13]:7 ropt_net_207:3 3.609394e-06 +81 chany_bottom_in[13]:4 ropt_net_207:4 0.0001642324 +82 chany_bottom_in[13]:6 ropt_net_207:4 3.609394e-06 +83 chany_bottom_in[13]:6 ropt_net_207:2 5.086743e-06 +84 chany_bottom_in[13]:5 ropt_net_207:3 0.0001693191 +85 chany_bottom_in[13]:34 ropt_net_181:6 0.0001681487 +86 chany_bottom_in[13]:35 ropt_net_181:7 0.0001681487 +87 chany_bottom_in[13]:11 ropt_net_192:6 8.093736e-05 +88 chany_bottom_in[13]:10 ropt_net_192:7 8.093736e-05 +89 chany_bottom_in[13]:9 ropt_net_192:5 7.13897e-06 +90 chany_bottom_in[13]:8 ropt_net_192:4 7.13897e-06 +91 chany_bottom_in[13]:13 ropt_net_199:3 9.72051e-06 +92 chany_bottom_in[13]:11 ropt_net_199:5 5.291831e-05 +93 chany_bottom_in[13]:12 ropt_net_199:4 9.72051e-06 +94 chany_bottom_in[13]:10 ropt_net_199:6 5.291831e-05 +95 chany_bottom_in[13]:13 ropt_net_160:7 1.77419e-05 +96 chany_bottom_in[13]:11 ropt_net_160:5 2.634523e-05 +97 chany_bottom_in[13]:11 ropt_net_160:2 3.685897e-05 +98 chany_bottom_in[13]:12 ropt_net_160:6 1.77419e-05 +99 chany_bottom_in[13]:10 ropt_net_160:4 2.634523e-05 +100 chany_bottom_in[13]:10 ropt_net_160:3 3.685897e-05 +101 chany_bottom_in[13]:9 ropt_net_160:7 4.02384e-07 +102 chany_bottom_in[13]:8 ropt_net_160:6 4.02384e-07 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:36 0.005475447 +1 chany_bottom_in[13]:17 chany_bottom_in[13]:16 0.007924199 +2 chany_bottom_in[13]:18 chany_bottom_in[13]:17 0.00341 +3 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.01417634 +4 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.00341 +5 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.005258929 +6 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.0045 +7 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.0045 +8 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.002348214 +9 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.002424107 +10 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.0045 +11 chany_bottom_in[13]:4 ropt_mt_inst_775:A 0.152 +12 chany_bottom_in[13]:31 chany_bottom_in[13]:30 0.001004625 +13 chany_bottom_in[13]:32 chany_bottom_in[13]:31 0.00341 +14 chany_bottom_in[13]:32 chany_bottom_in[13]:26 0.004687466 +15 chany_bottom_in[13]:29 chany_bottom_in[13]:28 0.0045 +16 chany_bottom_in[13]:30 chany_bottom_in[13]:29 0.00341 +17 chany_bottom_in[13]:28 chany_bottom_in[13]:27 9.23913e-05 +18 chany_bottom_in[13]:27 mux_left_track_17\/mux_l1_in_0_:A0 0.152 +19 chany_bottom_in[13]:24 chany_bottom_in[13]:23 0.0002118917 +20 chany_bottom_in[13]:25 chany_bottom_in[13]:24 0.00341 +21 chany_bottom_in[13]:25 chany_bottom_in[13]:18 0.003620958 +22 chany_bottom_in[13]:22 chany_bottom_in[13]:21 0.004462054 +23 chany_bottom_in[13]:23 chany_bottom_in[13]:22 0.00341 +24 chany_bottom_in[13]:20 chany_bottom_in[13]:19 0.001069197 +25 chany_bottom_in[13]:21 chany_bottom_in[13]:20 0.0045 +26 chany_bottom_in[13]:19 mux_top_track_2\/mux_l2_in_2_:A1 0.152 +27 chany_bottom_in[13]:34 chany_bottom_in[13]:33 0.00341 +28 chany_bottom_in[13]:33 chany_bottom_in[13]:32 0.007243091 +29 chany_bottom_in[13]:36 chany_bottom_in[13]:35 0.00341 +30 chany_bottom_in[13]:35 chany_bottom_in[13]:34 0.004896224 +31 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.0003035715 +32 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.003662947 +33 chany_bottom_in[13]:16 chany_bottom_in[13]:15 0.0001065333 +34 chany_bottom_in[13]:15 chany_bottom_in[13]:14 0.0007915583 +35 chany_bottom_in[13]:26 chany_bottom_in[13]:25 0.0001441333 + +*END + +*D_NET prog_clk[0] 0.1205137 //LENGTH 858.085 LUMPCC 0.01873862 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 2.300 28.490 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 10.845 47.600 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 14.065 44.880 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 18.205 42.160 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 27.865 42.160 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.545 47.600 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 26.940 55.760 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 28.325 61.200 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 31.085 69.360 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.065 74.800 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 45.805 74.800 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 49.025 85.680 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 49.025 88.400 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 58.685 85.680 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 61.905 88.400 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 68.805 102.000 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 74.325 107.440 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.865 110.160 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 77.990 121.040 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 75.245 91.120 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 61.905 99.280 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 60.525 80.240 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 70.185 80.240 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 45.805 82.960 +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 32.005 72.080 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 7.625 53.040 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 18.115 55.760 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 10.385 58.480 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 10.475 66.640 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 19.125 66.640 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 18.205 69.360 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 6.705 74.800 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 13.695 93.840 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.365 99.280 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 19.585 80.240 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 36.605 93.840 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 33.845 99.280 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 42.585 102.000 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 43.045 104.720 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 56.845 115.600 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 61.905 112.880 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 110.160 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 31.545 115.600 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 31.545 121.040 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 42.125 121.040 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 38.445 85.680 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 22.345 93.840 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 24.185 96.560 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 21.425 82.960 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 4.865 80.240 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.625 34.000 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 12.225 36.720 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 31.545 20.400 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 34.765 31.280 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 33.465 36.720 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 39.825 53.040 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 44.885 58.480 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 52.705 61.200 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 56.385 69.360 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 50.405 50.320 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 36.145 50.320 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 40.745 42.160 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 49.485 42.160 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 40.745 25.840 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 39.825 17.680 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 42.585 14.960 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 50.405 12.240 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 61.445 14.960 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 43.965 28.560 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 54.545 34.000 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 57.305 28.560 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 61.445 25.840 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 62.365 36.720 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.665 47.600 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.045 55.760 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 65.585 61.200 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 71.565 23.120 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK I *L 0.001922 *C 74.785 34.000 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 75.245 42.160 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 74.785 50.320 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 78.005 61.200 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 78.925 58.480 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 76.625 69.360 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 73.865 72.080 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 77.085 28.560 +*N prog_clk[0]:85 *C 77.047 28.560 +*N prog_clk[0]:86 *C 76.405 28.560 +*N prog_clk[0]:87 *C 76.360 28.560 +*N prog_clk[0]:88 *C 76.353 28.560 +*N prog_clk[0]:89 *C 73.865 72.080 +*N prog_clk[0]:90 *C 74.060 72.080 +*N prog_clk[0]:91 *C 74.060 72.035 +*N prog_clk[0]:92 *C 74.060 69.360 +*N prog_clk[0]:93 *C 76.625 69.360 +*N prog_clk[0]:94 *C 76.360 69.360 +*N prog_clk[0]:95 *C 76.360 69.360 +*N prog_clk[0]:96 *C 76.353 69.360 +*N prog_clk[0]:97 *C 74.987 69.360 +*N prog_clk[0]:98 *C 74.980 69.303 +*N prog_clk[0]:99 *C 78.925 58.480 +*N prog_clk[0]:100 *C 79.120 58.480 +*N prog_clk[0]:101 *C 79.120 58.480 +*N prog_clk[0]:102 *C 79.112 58.480 +*N prog_clk[0]:103 *C 78.200 58.480 +*N prog_clk[0]:104 *C 78.005 61.200 +*N prog_clk[0]:105 *C 78.200 61.200 +*N prog_clk[0]:106 *C 78.200 61.155 +*N prog_clk[0]:107 *C 78.200 59.218 +*N prog_clk[0]:108 *C 78.200 59.153 +*N prog_clk[0]:109 *C 74.987 59.160 +*N prog_clk[0]:110 *C 74.980 59.218 +*N prog_clk[0]:111 *C 74.520 59.160 +*N prog_clk[0]:112 *C 74.785 50.320 +*N prog_clk[0]:113 *C 74.520 49.980 +*N prog_clk[0]:114 *C 74.520 49.980 +*N prog_clk[0]:115 *C 75.208 42.160 +*N prog_clk[0]:116 *C 74.520 42.160 +*N prog_clk[0]:117 *C 74.520 42.500 +*N prog_clk[0]:118 *C 74.520 42.500 +*N prog_clk[0]:119 *C 74.785 34.000 +*N prog_clk[0]:120 *C 74.520 33.660 +*N prog_clk[0]:121 *C 74.520 33.660 +*N prog_clk[0]:122 *C 74.520 28.617 +*N prog_clk[0]:123 *C 74.520 28.560 +*N prog_clk[0]:124 *C 71.760 28.560 +*N prog_clk[0]:125 *C 71.565 23.120 +*N prog_clk[0]:126 *C 71.760 23.120 +*N prog_clk[0]:127 *C 71.760 23.165 +*N prog_clk[0]:128 *C 71.760 27.823 +*N prog_clk[0]:129 *C 71.760 27.888 +*N prog_clk[0]:130 *C 65.585 61.200 +*N prog_clk[0]:131 *C 65.320 61.200 +*N prog_clk[0]:132 *C 65.320 61.155 +*N prog_clk[0]:133 *C 66.008 55.760 +*N prog_clk[0]:134 *C 65.320 55.760 +*N prog_clk[0]:135 *C 65.320 55.420 +*N prog_clk[0]:136 *C 65.320 55.420 +*N prog_clk[0]:137 *C 65.320 52.418 +*N prog_clk[0]:138 *C 65.312 52.360 +*N prog_clk[0]:139 *C 63.488 52.360 +*N prog_clk[0]:140 *C 63.480 52.303 +*N prog_clk[0]:141 *C 64.627 47.600 +*N prog_clk[0]:142 *C 63.480 47.600 +*N prog_clk[0]:143 *C 63.480 47.940 +*N prog_clk[0]:144 *C 63.480 47.940 +*N prog_clk[0]:145 *C 63.480 42.218 +*N prog_clk[0]:146 *C 63.473 42.160 +*N prog_clk[0]:147 *C 61.188 42.160 +*N prog_clk[0]:148 *C 61.180 42.102 +*N prog_clk[0]:149 *C 62.328 36.720 +*N prog_clk[0]:150 *C 61.180 36.720 +*N prog_clk[0]:151 *C 61.180 37.060 +*N prog_clk[0]:152 *C 61.180 37.060 +*N prog_clk[0]:153 *C 61.445 25.840 +*N prog_clk[0]:154 *C 61.180 25.840 +*N prog_clk[0]:155 *C 61.180 25.885 +*N prog_clk[0]:156 *C 61.180 27.880 +*N prog_clk[0]:157 *C 61.180 27.880 +*N prog_clk[0]:158 *C 61.180 28.560 +*N prog_clk[0]:159 *C 57.305 28.560 +*N prog_clk[0]:160 *C 57.500 28.560 +*N prog_clk[0]:161 *C 57.500 28.560 +*N prog_clk[0]:162 *C 57.500 28.560 +*N prog_clk[0]:163 *C 54.545 34.000 +*N prog_clk[0]:164 *C 54.740 34.000 +*N prog_clk[0]:165 *C 54.740 33.955 +*N prog_clk[0]:166 *C 54.740 28.617 +*N prog_clk[0]:167 *C 54.740 28.560 +*N prog_clk[0]:168 *C 43.965 28.560 +*N prog_clk[0]:169 *C 43.700 28.560 +*N prog_clk[0]:170 *C 43.700 28.560 +*N prog_clk[0]:171 *C 43.700 28.560 +*N prog_clk[0]:172 *C 61.445 14.960 +*N prog_clk[0]:173 *C 61.180 14.960 +*N prog_clk[0]:174 *C 61.180 14.915 +*N prog_clk[0]:175 *C 61.180 12.298 +*N prog_clk[0]:176 *C 61.172 12.240 +*N prog_clk[0]:177 *C 50.405 12.240 +*N prog_clk[0]:178 *C 50.600 12.240 +*N prog_clk[0]:179 *C 50.600 12.240 +*N prog_clk[0]:180 *C 50.608 12.240 +*N prog_clk[0]:181 *C 51.980 12.240 +*N prog_clk[0]:182 *C 51.980 12.298 +*N prog_clk[0]:183 *C 51.980 14.902 +*N prog_clk[0]:184 *C 51.973 14.960 +*N prog_clk[0]:185 *C 42.585 14.960 +*N prog_clk[0]:186 *C 42.780 14.960 +*N prog_clk[0]:187 *C 42.780 14.960 +*N prog_clk[0]:188 *C 42.780 14.960 +*N prog_clk[0]:189 *C 40.028 14.960 +*N prog_clk[0]:190 *C 40.020 15.018 +*N prog_clk[0]:191 *C 39.825 17.680 +*N prog_clk[0]:192 *C 40.020 17.340 +*N prog_clk[0]:193 *C 40.020 17.340 +*N prog_clk[0]:194 *C 40.708 25.840 +*N prog_clk[0]:195 *C 40.020 25.840 +*N prog_clk[0]:196 *C 40.020 26.180 +*N prog_clk[0]:197 *C 40.020 26.180 +*N prog_clk[0]:198 *C 40.020 28.503 +*N prog_clk[0]:199 *C 40.020 28.560 +*N prog_clk[0]:200 *C 34.500 28.560 +*N prog_clk[0]:201 *C 49.485 42.160 +*N prog_clk[0]:202 *C 49.220 42.160 +*N prog_clk[0]:203 *C 49.220 42.160 +*N prog_clk[0]:204 *C 49.213 42.160 +*N prog_clk[0]:205 *C 40.745 42.160 +*N prog_clk[0]:206 *C 40.480 42.160 +*N prog_clk[0]:207 *C 40.480 42.160 +*N prog_clk[0]:208 *C 40.480 42.160 +*N prog_clk[0]:209 *C 36.145 50.320 +*N prog_clk[0]:210 *C 36.340 50.320 +*N prog_clk[0]:211 *C 36.340 50.275 +*N prog_clk[0]:212 *C 50.405 50.320 +*N prog_clk[0]:213 *C 50.140 50.320 +*N prog_clk[0]:214 *C 50.140 50.320 +*N prog_clk[0]:215 *C 50.133 50.320 +*N prog_clk[0]:216 *C 56.348 69.360 +*N prog_clk[0]:217 *C 55.705 69.360 +*N prog_clk[0]:218 *C 55.660 69.315 +*N prog_clk[0]:219 *C 55.660 66.698 +*N prog_clk[0]:220 *C 55.653 66.640 +*N prog_clk[0]:221 *C 52.908 66.640 +*N prog_clk[0]:222 *C 52.900 66.583 +*N prog_clk[0]:223 *C 52.705 61.200 +*N prog_clk[0]:224 *C 52.900 60.860 +*N prog_clk[0]:225 *C 52.900 60.860 +*N prog_clk[0]:226 *C 52.900 59.898 +*N prog_clk[0]:227 *C 52.893 59.840 +*N prog_clk[0]:228 *C 44.628 59.840 +*N prog_clk[0]:229 *C 44.620 59.783 +*N prog_clk[0]:230 *C 44.885 58.480 +*N prog_clk[0]:231 *C 44.620 58.820 +*N prog_clk[0]:232 *C 44.620 58.820 +*N prog_clk[0]:233 *C 44.620 50.378 +*N prog_clk[0]:234 *C 44.620 50.320 +*N prog_clk[0]:235 *C 39.825 53.040 +*N prog_clk[0]:236 *C 40.020 53.040 +*N prog_clk[0]:237 *C 40.020 52.995 +*N prog_clk[0]:238 *C 40.020 50.378 +*N prog_clk[0]:239 *C 40.020 50.320 +*N prog_clk[0]:240 *C 40.020 49.640 +*N prog_clk[0]:241 *C 36.348 49.640 +*N prog_clk[0]:242 *C 36.340 49.640 +*N prog_clk[0]:243 *C 36.340 42.218 +*N prog_clk[0]:244 *C 36.340 42.160 +*N prog_clk[0]:245 *C 34.508 42.160 +*N prog_clk[0]:246 *C 34.500 42.102 +*N prog_clk[0]:247 *C 33.465 36.720 +*N prog_clk[0]:248 *C 33.580 37.060 +*N prog_clk[0]:249 *C 33.995 37.060 +*N prog_clk[0]:250 *C 34.040 37.060 +*N prog_clk[0]:251 *C 34.500 37.060 +*N prog_clk[0]:252 *C 34.765 31.280 +*N prog_clk[0]:253 *C 34.500 31.620 +*N prog_clk[0]:254 *C 34.500 31.620 +*N prog_clk[0]:255 *C 34.500 29.298 +*N prog_clk[0]:256 *C 34.500 29.233 +*N prog_clk[0]:257 *C 31.545 20.400 +*N prog_clk[0]:258 *C 31.280 20.400 +*N prog_clk[0]:259 *C 31.280 20.445 +*N prog_clk[0]:260 *C 31.280 29.183 +*N prog_clk[0]:261 *C 31.280 29.240 +*N prog_clk[0]:262 *C 12.225 36.720 +*N prog_clk[0]:263 *C 11.960 36.720 +*N prog_clk[0]:264 *C 11.960 36.675 +*N prog_clk[0]:265 *C 11.960 29.298 +*N prog_clk[0]:266 *C 11.960 29.240 +*N prog_clk[0]:267 *C 7.588 34.000 +*N prog_clk[0]:268 *C 5.565 34.000 +*N prog_clk[0]:269 *C 5.520 34.000 +*N prog_clk[0]:270 *C 4.865 80.240 +*N prog_clk[0]:271 *C 5.060 80.240 +*N prog_clk[0]:272 *C 21.425 82.960 +*N prog_clk[0]:273 *C 24.148 96.560 +*N prog_clk[0]:274 *C 22.125 96.560 +*N prog_clk[0]:275 *C 22.080 96.515 +*N prog_clk[0]:276 *C 22.345 93.840 +*N prog_clk[0]:277 *C 22.080 93.500 +*N prog_clk[0]:278 *C 22.080 93.500 +*N prog_clk[0]:279 *C 38.445 85.680 +*N prog_clk[0]:280 *C 38.180 85.680 +*N prog_clk[0]:281 *C 38.180 85.680 +*N prog_clk[0]:282 *C 38.172 85.680 +*N prog_clk[0]:283 *C 32.660 85.680 +*N prog_clk[0]:284 *C 42.087 121.040 +*N prog_clk[0]:285 *C 37.765 121.040 +*N prog_clk[0]:286 *C 37.720 121.040 +*N prog_clk[0]:287 *C 37.712 121.040 +*N prog_clk[0]:288 *C 31.748 121.040 +*N prog_clk[0]:289 *C 31.545 121.040 +*N prog_clk[0]:290 *C 31.740 121.040 +*N prog_clk[0]:291 *C 31.740 121.040 +*N prog_clk[0]:292 *C 31.545 115.600 +*N prog_clk[0]:293 *C 31.740 115.260 +*N prog_clk[0]:294 *C 31.770 115.290 +*N prog_clk[0]:295 *C 31.740 115.600 +*N prog_clk[0]:296 *C 32.200 115.600 +*N prog_clk[0]:297 *C 31.545 110.160 +*N prog_clk[0]:298 *C 31.740 109.820 +*N prog_clk[0]:299 *C 32.155 109.820 +*N prog_clk[0]:300 *C 32.200 109.820 +*N prog_clk[0]:301 *C 32.660 109.820 +*N prog_clk[0]:302 *C 61.867 112.880 +*N prog_clk[0]:303 *C 61.225 112.880 +*N prog_clk[0]:304 *C 61.180 112.880 +*N prog_clk[0]:305 *C 61.172 112.880 +*N prog_clk[0]:306 *C 57.040 112.880 +*N prog_clk[0]:307 *C 56.845 115.600 +*N prog_clk[0]:308 *C 57.040 115.600 +*N prog_clk[0]:309 *C 57.040 115.555 +*N prog_clk[0]:310 *C 57.040 113.618 +*N prog_clk[0]:311 *C 57.040 113.553 +*N prog_clk[0]:312 *C 44.168 113.560 +*N prog_clk[0]:313 *C 44.160 113.560 +*N prog_clk[0]:314 *C 43.700 113.560 +*N prog_clk[0]:315 *C 43.700 108.178 +*N prog_clk[0]:316 *C 43.693 108.120 +*N prog_clk[0]:317 *C 42.788 108.120 +*N prog_clk[0]:318 *C 42.780 108.062 +*N prog_clk[0]:319 *C 43.045 104.720 +*N prog_clk[0]:320 *C 42.780 104.380 +*N prog_clk[0]:321 *C 42.780 104.380 +*N prog_clk[0]:322 *C 42.780 102.045 +*N prog_clk[0]:323 *C 42.638 102.000 +*N prog_clk[0]:324 *C 42.547 102.000 +*N prog_clk[0]:325 *C 40.940 102.000 +*N prog_clk[0]:326 *C 40.940 102.340 +*N prog_clk[0]:327 *C 40.940 102.295 +*N prog_clk[0]:328 *C 40.940 99.338 +*N prog_clk[0]:329 *C 40.933 99.280 +*N prog_clk[0]:330 *C 33.845 99.280 +*N prog_clk[0]:331 *C 33.580 99.280 +*N prog_clk[0]:332 *C 33.580 99.280 +*N prog_clk[0]:333 *C 33.580 99.280 +*N prog_clk[0]:334 *C 32.668 99.280 +*N prog_clk[0]:335 *C 32.660 99.280 +*N prog_clk[0]:336 *C 36.605 93.840 +*N prog_clk[0]:337 *C 36.340 93.840 +*N prog_clk[0]:338 *C 36.340 93.840 +*N prog_clk[0]:339 *C 36.333 93.840 +*N prog_clk[0]:340 *C 32.668 93.840 +*N prog_clk[0]:341 *C 32.660 93.840 +*N prog_clk[0]:342 *C 32.660 86.418 +*N prog_clk[0]:343 *C 32.660 86.353 +*N prog_clk[0]:344 *C 22.088 86.360 +*N prog_clk[0]:345 *C 22.080 86.418 +*N prog_clk[0]:346 *C 21.620 86.360 +*N prog_clk[0]:347 *C 21.620 82.665 +*N prog_clk[0]:348 *C 21.575 82.627 +*N prog_clk[0]:349 *C 19.365 82.620 +*N prog_clk[0]:350 *C 19.320 82.575 +*N prog_clk[0]:351 *C 19.585 80.240 +*N prog_clk[0]:352 *C 19.320 80.580 +*N prog_clk[0]:353 *C 19.320 80.625 +*N prog_clk[0]:354 *C 19.320 80.240 +*N prog_clk[0]:355 *C 19.312 80.240 +*N prog_clk[0]:356 *C 16.328 99.280 +*N prog_clk[0]:357 *C 13.845 99.280 +*N prog_clk[0]:358 *C 13.800 99.235 +*N prog_clk[0]:359 *C 13.695 93.840 +*N prog_clk[0]:360 *C 13.800 93.840 +*N prog_clk[0]:361 *C 13.800 80.297 +*N prog_clk[0]:362 *C 13.800 80.240 +*N prog_clk[0]:363 *C 5.067 80.240 +*N prog_clk[0]:364 *C 5.060 80.240 +*N prog_clk[0]:365 *C 6.705 74.800 +*N prog_clk[0]:366 *C 6.440 74.800 +*N prog_clk[0]:367 *C 6.440 74.800 +*N prog_clk[0]:368 *C 6.433 74.800 +*N prog_clk[0]:369 *C 5.067 74.800 +*N prog_clk[0]:370 *C 5.060 74.800 +*N prog_clk[0]:371 *C 18.205 69.360 +*N prog_clk[0]:372 *C 18.400 69.360 +*N prog_clk[0]:373 *C 18.400 69.315 +*N prog_clk[0]:374 *C 19.125 66.640 +*N prog_clk[0]:375 *C 19.320 66.640 +*N prog_clk[0]:376 *C 19.320 66.640 +*N prog_clk[0]:377 *C 18.400 66.640 +*N prog_clk[0]:378 *C 18.393 66.640 +*N prog_clk[0]:379 *C 10.475 66.640 +*N prog_clk[0]:380 *C 10.580 66.640 +*N prog_clk[0]:381 *C 10.580 66.640 +*N prog_clk[0]:382 *C 5.067 66.640 +*N prog_clk[0]:383 *C 5.060 66.640 +*N prog_clk[0]:384 *C 10.385 58.480 +*N prog_clk[0]:385 *C 10.120 58.480 +*N prog_clk[0]:386 *C 10.120 58.435 +*N prog_clk[0]:387 *C 18.078 55.760 +*N prog_clk[0]:388 *C 13.845 55.760 +*N prog_clk[0]:389 *C 13.800 55.760 +*N prog_clk[0]:390 *C 13.793 55.760 +*N prog_clk[0]:391 *C 10.128 55.760 +*N prog_clk[0]:392 *C 10.120 55.760 +*N prog_clk[0]:393 *C 10.120 53.098 +*N prog_clk[0]:394 *C 10.113 53.040 +*N prog_clk[0]:395 *C 7.625 53.040 +*N prog_clk[0]:396 *C 7.360 53.040 +*N prog_clk[0]:397 *C 7.360 53.040 +*N prog_clk[0]:398 *C 7.360 53.040 +*N prog_clk[0]:399 *C 5.067 53.040 +*N prog_clk[0]:400 *C 5.060 53.040 +*N prog_clk[0]:401 *C 32.005 72.080 +*N prog_clk[0]:402 *C 45.805 82.960 +*N prog_clk[0]:403 *C 45.540 82.960 +*N prog_clk[0]:404 *C 45.540 82.915 +*N prog_clk[0]:405 *C 70.148 80.240 +*N prog_clk[0]:406 *C 69.045 80.240 +*N prog_clk[0]:407 *C 69.000 80.240 +*N prog_clk[0]:408 *C 68.993 80.240 +*N prog_clk[0]:409 *C 60.525 80.240 +*N prog_clk[0]:410 *C 60.260 80.240 +*N prog_clk[0]:411 *C 60.260 80.240 +*N prog_clk[0]:412 *C 60.260 80.240 +*N prog_clk[0]:413 *C 58.420 80.240 +*N prog_clk[0]:414 *C 61.905 99.280 +*N prog_clk[0]:415 *C 62.100 99.280 +*N prog_clk[0]:416 *C 62.100 99.235 +*N prog_clk[0]:417 *C 75.208 91.120 +*N prog_clk[0]:418 *C 74.565 91.120 +*N prog_clk[0]:419 *C 74.520 91.120 +*N prog_clk[0]:420 *C 74.513 91.120 +*N prog_clk[0]:421 *C 69.000 91.120 +*N prog_clk[0]:422 *C 77.953 121.040 +*N prog_clk[0]:423 *C 74.980 121.040 +*N prog_clk[0]:424 *C 74.980 120.360 +*N prog_clk[0]:425 *C 73.645 120.360 +*N prog_clk[0]:426 *C 73.600 120.315 +*N prog_clk[0]:427 *C 73.865 110.160 +*N prog_clk[0]:428 *C 73.600 109.820 +*N prog_clk[0]:429 *C 73.600 109.820 +*N prog_clk[0]:430 *C 74.288 107.440 +*N prog_clk[0]:431 *C 73.600 107.440 +*N prog_clk[0]:432 *C 73.600 107.780 +*N prog_clk[0]:433 *C 73.600 107.825 +*N prog_clk[0]:434 *C 73.600 107.440 +*N prog_clk[0]:435 *C 73.593 107.440 +*N prog_clk[0]:436 *C 69.008 107.440 +*N prog_clk[0]:437 *C 69.000 107.383 +*N prog_clk[0]:438 *C 68.805 102.000 +*N prog_clk[0]:439 *C 69.000 102.340 +*N prog_clk[0]:440 *C 69.000 102.340 +*N prog_clk[0]:441 *C 69.000 91.858 +*N prog_clk[0]:442 *C 69.000 91.793 +*N prog_clk[0]:443 *C 62.108 91.800 +*N prog_clk[0]:444 *C 62.100 91.800 +*N prog_clk[0]:445 *C 61.905 88.400 +*N prog_clk[0]:446 *C 62.100 88.060 +*N prog_clk[0]:447 *C 62.100 88.060 +*N prog_clk[0]:448 *C 62.100 87.098 +*N prog_clk[0]:449 *C 62.093 87.040 +*N prog_clk[0]:450 *C 58.428 87.040 +*N prog_clk[0]:451 *C 58.420 86.983 +*N prog_clk[0]:452 *C 58.685 85.680 +*N prog_clk[0]:453 *C 58.420 86.020 +*N prog_clk[0]:454 *C 58.420 86.020 +*N prog_clk[0]:455 *C 58.420 80.978 +*N prog_clk[0]:456 *C 58.420 80.913 +*N prog_clk[0]:457 *C 49.025 88.400 +*N prog_clk[0]:458 *C 49.220 88.400 +*N prog_clk[0]:459 *C 49.220 88.355 +*N prog_clk[0]:460 *C 49.025 85.680 +*N prog_clk[0]:461 *C 49.220 86.020 +*N prog_clk[0]:462 *C 49.220 86.020 +*N prog_clk[0]:463 *C 49.220 80.978 +*N prog_clk[0]:464 *C 49.220 80.920 +*N prog_clk[0]:465 *C 45.547 80.920 +*N prog_clk[0]:466 *C 45.540 80.920 +*N prog_clk[0]:467 *C 45.805 74.800 +*N prog_clk[0]:468 *C 45.540 75.140 +*N prog_clk[0]:469 *C 45.540 75.185 +*N prog_clk[0]:470 *C 45.540 74.800 +*N prog_clk[0]:471 *C 45.532 74.800 +*N prog_clk[0]:472 *C 37.065 74.800 +*N prog_clk[0]:473 *C 37.260 74.800 +*N prog_clk[0]:474 *C 37.260 74.800 +*N prog_clk[0]:475 *C 37.260 74.800 +*N prog_clk[0]:476 *C 32.208 74.800 +*N prog_clk[0]:477 *C 32.200 74.743 +*N prog_clk[0]:478 *C 32.200 71.785 +*N prog_clk[0]:479 *C 32.155 71.748 +*N prog_clk[0]:480 *C 30.405 71.740 +*N prog_clk[0]:481 *C 30.360 71.695 +*N prog_clk[0]:482 *C 31.048 69.360 +*N prog_clk[0]:483 *C 30.360 69.360 +*N prog_clk[0]:484 *C 30.360 69.700 +*N prog_clk[0]:485 *C 30.360 69.700 +*N prog_clk[0]:486 *C 30.360 66.698 +*N prog_clk[0]:487 *C 30.353 66.640 +*N prog_clk[0]:488 *C 28.068 66.640 +*N prog_clk[0]:489 *C 28.060 66.583 +*N prog_clk[0]:490 *C 28.325 61.200 +*N prog_clk[0]:491 *C 28.060 60.860 +*N prog_clk[0]:492 *C 28.030 60.890 +*N prog_clk[0]:493 *C 28.015 61.200 +*N prog_clk[0]:494 *C 27.600 61.200 +*N prog_clk[0]:495 *C 26.940 55.760 +*N prog_clk[0]:496 *C 27.140 55.760 +*N prog_clk[0]:497 *C 27.140 55.760 +*N prog_clk[0]:498 *C 27.600 55.760 +*N prog_clk[0]:499 *C 31.545 47.600 +*N prog_clk[0]:500 *C 31.280 47.600 +*N prog_clk[0]:501 *C 31.280 47.600 +*N prog_clk[0]:502 *C 31.273 47.600 +*N prog_clk[0]:503 *C 27.608 47.600 +*N prog_clk[0]:504 *C 27.600 47.600 +*N prog_clk[0]:505 *C 27.865 42.160 +*N prog_clk[0]:506 *C 27.600 42.160 +*N prog_clk[0]:507 *C 27.600 42.160 +*N prog_clk[0]:508 *C 27.593 42.160 +*N prog_clk[0]:509 *C 18.205 42.160 +*N prog_clk[0]:510 *C 18.400 42.160 +*N prog_clk[0]:511 *C 18.400 42.160 +*N prog_clk[0]:512 *C 18.400 42.160 +*N prog_clk[0]:513 *C 13.800 42.160 +*N prog_clk[0]:514 *C 14.065 44.880 +*N prog_clk[0]:515 *C 13.800 44.880 +*N prog_clk[0]:516 *C 13.800 44.835 +*N prog_clk[0]:517 *C 13.800 42.898 +*N prog_clk[0]:518 *C 13.800 42.833 +*N prog_clk[0]:519 *C 10.845 47.600 +*N prog_clk[0]:520 *C 11.040 47.600 +*N prog_clk[0]:521 *C 11.040 47.555 +*N prog_clk[0]:522 *C 11.040 42.898 +*N prog_clk[0]:523 *C 11.040 42.840 +*N prog_clk[0]:524 *C 5.067 42.840 +*N prog_clk[0]:525 *C 5.060 42.840 +*N prog_clk[0]:526 *C 5.060 34.000 +*N prog_clk[0]:527 *C 5.060 29.298 +*N prog_clk[0]:528 *C 5.060 29.240 +*N prog_clk[0]:529 *C 2.308 29.240 +*N prog_clk[0]:530 *C 2.300 29.183 + +*CAP +0 prog_clk[0] 5.040281e-05 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +3 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +4 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +6 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +7 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +8 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +9 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +11 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +12 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +13 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +14 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +15 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +16 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +17 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +18 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +19 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +20 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +21 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +22 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +23 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +24 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +25 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +26 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +27 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +28 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +29 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +32 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +33 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +34 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +36 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +37 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +38 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +39 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +40 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +41 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +42 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +43 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +44 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +46 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +47 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +48 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +49 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +50 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +51 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +52 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +53 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +54 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +55 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +56 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +57 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +58 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +59 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +60 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +61 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +62 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +63 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +64 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +65 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +66 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +67 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +68 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +69 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +70 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +71 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +72 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +73 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +74 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +75 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +76 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +77 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 1e-06 +78 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +79 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +80 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +81 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +82 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +83 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +84 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +85 prog_clk[0]:85 7.74263e-05 +86 prog_clk[0]:86 7.74263e-05 +87 prog_clk[0]:87 4.036508e-05 +88 prog_clk[0]:88 9.626149e-05 +89 prog_clk[0]:89 5.623141e-05 +90 prog_clk[0]:90 5.731225e-05 +91 prog_clk[0]:91 0.0001769402 +92 prog_clk[0]:92 0.0002360431 +93 prog_clk[0]:93 6.346412e-05 +94 prog_clk[0]:94 5.85153e-05 +95 prog_clk[0]:95 3.635676e-05 +96 prog_clk[0]:96 0.0001104766 +97 prog_clk[0]:97 0.0001104766 +98 prog_clk[0]:98 0.0005980135 +99 prog_clk[0]:99 5.643307e-05 +100 prog_clk[0]:100 5.717956e-05 +101 prog_clk[0]:101 3.513641e-05 +102 prog_clk[0]:102 7.78024e-05 +103 prog_clk[0]:103 0.0001283102 +104 prog_clk[0]:104 6.609809e-05 +105 prog_clk[0]:105 6.547417e-05 +106 prog_clk[0]:106 0.0001120762 +107 prog_clk[0]:107 0.0001120762 +108 prog_clk[0]:108 0.0002907899 +109 prog_clk[0]:109 0.0002402822 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prog_clk[0]:503 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001679033 +797 prog_clk[0]:502 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001679033 +798 prog_clk[0]:240 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.403656e-05 +799 prog_clk[0]:122 optlc_net_140:8 5.727711e-05 +800 prog_clk[0]:114 optlc_net_140:9 1.924848e-05 +801 prog_clk[0]:121 optlc_net_140:8 0.0001124951 +802 prog_clk[0]:121 optlc_net_140:9 5.727711e-05 +803 prog_clk[0]:118 optlc_net_140:8 1.924848e-05 +804 prog_clk[0]:118 optlc_net_140:9 0.0001124951 +805 prog_clk[0]:128 optlc_net_140:9 1.04079e-05 +806 prog_clk[0]:129 optlc_net_140:8 1.089097e-05 +807 prog_clk[0]:127 optlc_net_140:8 1.04079e-05 +808 prog_clk[0]:124 optlc_net_140:9 1.089097e-05 +809 prog_clk[0]:489 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.854706e-05 +810 prog_clk[0]:492 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.439706e-06 +811 prog_clk[0]:497 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.611151e-06 +812 prog_clk[0]:498 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.611151e-06 +813 prog_clk[0]:498 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.829428e-06 +814 prog_clk[0]:494 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.829428e-06 +815 prog_clk[0]:494 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.741508e-06 +816 prog_clk[0]:493 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.439706e-06 +817 prog_clk[0]:493 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.741508e-06 +818 prog_clk[0]:493 mux_left_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.854706e-05 +819 prog_clk[0]:471 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001634721 +820 prog_clk[0]:478 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.190884e-08 +821 prog_clk[0]:477 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.190884e-08 +822 prog_clk[0]:476 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.907601e-05 +823 prog_clk[0]:475 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001634721 +824 prog_clk[0]:475 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.907601e-05 +825 prog_clk[0]:522 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.500379e-06 +826 prog_clk[0]:521 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.500379e-06 +827 prog_clk[0]:378 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0003204898 +828 prog_clk[0]:393 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.140689e-07 +829 prog_clk[0]:487 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001439391 +830 prog_clk[0]:488 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001439391 +831 prog_clk[0]:381 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003204898 +832 prog_clk[0]:392 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.744137e-07 +833 prog_clk[0]:392 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.140689e-07 +834 prog_clk[0]:386 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.744137e-07 +835 prog_clk[0]:525 ropt_net_191:9 2.476976e-05 +836 prog_clk[0]:525 ropt_net_191:4 4.148252e-06 +837 prog_clk[0]:527 ropt_net_191:8 9.134069e-06 +838 prog_clk[0]:527 ropt_net_191:5 2.177832e-05 +839 prog_clk[0]:268 ropt_net_191:6 1.26941e-05 +840 prog_clk[0]:267 ropt_net_191:7 1.26941e-05 +841 prog_clk[0]:526 ropt_net_191:9 9.134069e-06 +842 prog_clk[0]:526 ropt_net_191:8 2.476976e-05 +843 prog_clk[0]:526 ropt_net_191:5 4.148252e-06 +844 prog_clk[0]:526 ropt_net_191:4 2.177832e-05 + +*RES +0 prog_clk[0] prog_clk[0]:530 0.0006183035 +1 prog_clk[0]:348 prog_clk[0]:347 0.0045 +2 prog_clk[0]:348 prog_clk[0]:272 0.0001807065 +3 prog_clk[0]:347 prog_clk[0]:346 0.003299107 +4 prog_clk[0]:177 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +5 prog_clk[0]:178 prog_clk[0]:177 0.0001059783 +6 prog_clk[0]:179 prog_clk[0]:178 0.0045 +7 prog_clk[0]:180 prog_clk[0]:179 0.00341 +8 prog_clk[0]:522 prog_clk[0]:521 0.004158482 +9 prog_clk[0]:523 prog_clk[0]:522 0.00341 +10 prog_clk[0]:523 prog_clk[0]:518 0.0004324 +11 prog_clk[0]:520 prog_clk[0]:519 0.0001059783 +12 prog_clk[0]:521 prog_clk[0]:520 0.0045 +13 prog_clk[0]:519 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +14 prog_clk[0]:226 prog_clk[0]:225 0.0008593751 +15 prog_clk[0]:227 prog_clk[0]:226 0.00341 +16 prog_clk[0]:229 prog_clk[0]:228 0.00341 +17 prog_clk[0]:228 prog_clk[0]:227 0.00129485 +18 prog_clk[0]:349 prog_clk[0]:348 0.001973214 +19 prog_clk[0]:350 prog_clk[0]:349 0.0045 +20 prog_clk[0]:156 prog_clk[0]:155 0.00178125 +21 prog_clk[0]:156 prog_clk[0]:152 0.008196429 +22 prog_clk[0]:157 prog_clk[0]:156 0.00341 +23 prog_clk[0]:157 prog_clk[0]:129 0.001657533 +24 prog_clk[0]:145 prog_clk[0]:144 0.005109375 +25 prog_clk[0]:146 prog_clk[0]:145 0.00341 +26 prog_clk[0]:148 prog_clk[0]:147 0.00341 +27 prog_clk[0]:147 prog_clk[0]:146 0.0003579833 +28 prog_clk[0]:364 prog_clk[0]:363 0.00341 +29 prog_clk[0]:364 prog_clk[0]:271 0.0045 +30 prog_clk[0]:363 prog_clk[0]:362 0.001368092 +31 prog_clk[0]:354 prog_clk[0]:353 0.0001850962 +32 prog_clk[0]:355 prog_clk[0]:354 0.00341 +33 prog_clk[0]:214 prog_clk[0]:213 0.0045 +34 prog_clk[0]:215 prog_clk[0]:214 0.00341 +35 prog_clk[0]:213 prog_clk[0]:212 0.0001440218 +36 prog_clk[0]:212 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +37 prog_clk[0]:345 prog_clk[0]:344 0.00341 +38 prog_clk[0]:345 prog_clk[0]:278 0.006323661 +39 prog_clk[0]:344 prog_clk[0]:343 0.001656358 +40 prog_clk[0]:444 prog_clk[0]:443 0.00341 +41 prog_clk[0]:444 prog_clk[0]:416 0.006638393 +42 prog_clk[0]:443 prog_clk[0]:442 0.001079825 +43 prog_clk[0]:463 prog_clk[0]:462 0.004502232 +44 prog_clk[0]:464 prog_clk[0]:463 0.00341 +45 prog_clk[0]:464 prog_clk[0]:456 0.001441333 +46 prog_clk[0]:400 prog_clk[0]:399 0.00341 +47 prog_clk[0]:400 prog_clk[0]:383 0.01214286 +48 prog_clk[0]:399 prog_clk[0]:398 0.0003591583 +49 prog_clk[0]:242 prog_clk[0]:241 0.00341 +50 prog_clk[0]:242 prog_clk[0]:211 0.0005669643 +51 prog_clk[0]:241 prog_clk[0]:240 0.0005753583 +52 prog_clk[0]:243 prog_clk[0]:242 0.006627232 +53 prog_clk[0]:244 prog_clk[0]:243 0.00341 +54 prog_clk[0]:244 prog_clk[0]:208 0.0006485999 +55 prog_clk[0]:110 prog_clk[0]:109 0.00341 +56 prog_clk[0]:110 prog_clk[0]:98 0.009004464 +57 prog_clk[0]:109 prog_clk[0]:108 0.0005032916 +58 prog_clk[0]:140 prog_clk[0]:139 0.00341 +59 prog_clk[0]:139 prog_clk[0]:138 0.0002859167 +60 prog_clk[0]:137 prog_clk[0]:136 0.002680804 +61 prog_clk[0]:138 prog_clk[0]:137 0.00341 +62 prog_clk[0]:323 prog_clk[0]:322 0.0045 +63 prog_clk[0]:322 prog_clk[0]:321 0.002084821 +64 prog_clk[0]:90 prog_clk[0]:89 0.0001059783 +65 prog_clk[0]:91 prog_clk[0]:90 0.0045 +66 prog_clk[0]:89 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +67 prog_clk[0]:455 prog_clk[0]:454 0.004502232 +68 prog_clk[0]:456 prog_clk[0]:455 0.00341 +69 prog_clk[0]:456 prog_clk[0]:413 0.0001053583 +70 prog_clk[0]:233 prog_clk[0]:232 0.007537946 +71 prog_clk[0]:234 prog_clk[0]:233 0.00341 +72 prog_clk[0]:234 prog_clk[0]:215 0.0008636249 +73 prog_clk[0]:383 prog_clk[0]:382 0.00341 +74 prog_clk[0]:383 prog_clk[0]:370 0.007285715 +75 prog_clk[0]:382 prog_clk[0]:381 0.000863625 +76 prog_clk[0]:377 prog_clk[0]:376 0.0008214285 +77 prog_clk[0]:377 prog_clk[0]:373 0.002388393 +78 prog_clk[0]:378 prog_clk[0]:377 0.00341 +79 prog_clk[0]:341 prog_clk[0]:340 0.00341 +80 prog_clk[0]:341 prog_clk[0]:335 0.004857143 +81 prog_clk[0]:340 prog_clk[0]:339 0.0005741833 +82 prog_clk[0]:338 prog_clk[0]:337 0.0045 +83 prog_clk[0]:339 prog_clk[0]:338 0.00341 +84 prog_clk[0]:337 prog_clk[0]:336 0.0001440218 +85 prog_clk[0]:336 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +86 prog_clk[0]:198 prog_clk[0]:197 0.002073661 +87 prog_clk[0]:199 prog_clk[0]:198 0.00341 +88 prog_clk[0]:199 prog_clk[0]:171 0.0005765333 +89 prog_clk[0]:507 prog_clk[0]:506 0.0045 +90 prog_clk[0]:507 prog_clk[0]:504 0.004857143 +91 prog_clk[0]:508 prog_clk[0]:507 0.00341 +92 prog_clk[0]:470 prog_clk[0]:469 0.0001850962 +93 prog_clk[0]:471 prog_clk[0]:470 0.00341 +94 prog_clk[0]:326 prog_clk[0]:325 0.0003035715 +95 prog_clk[0]:327 prog_clk[0]:326 0.0045 +96 prog_clk[0]:328 prog_clk[0]:327 0.002640625 +97 prog_clk[0]:329 prog_clk[0]:328 0.00341 +98 prog_clk[0]:525 prog_clk[0]:524 0.00341 +99 prog_clk[0]:525 prog_clk[0]:400 0.009107144 +100 prog_clk[0]:524 prog_clk[0]:523 0.0009356916 +101 prog_clk[0]:255 prog_clk[0]:254 0.002073661 +102 prog_clk[0]:256 prog_clk[0]:255 0.00341 +103 prog_clk[0]:256 prog_clk[0]:200 0.0001053583 +104 prog_clk[0]:480 prog_clk[0]:479 0.0015625 +105 prog_clk[0]:481 prog_clk[0]:480 0.0045 +106 prog_clk[0]:393 prog_clk[0]:392 0.002377232 +107 prog_clk[0]:394 prog_clk[0]:393 0.00341 +108 prog_clk[0]:122 prog_clk[0]:121 0.004502232 +109 prog_clk[0]:123 prog_clk[0]:122 0.00341 +110 prog_clk[0]:123 prog_clk[0]:88 0.0002870917 +111 prog_clk[0]:466 prog_clk[0]:465 0.00341 +112 prog_clk[0]:466 prog_clk[0]:404 0.00178125 +113 prog_clk[0]:465 prog_clk[0]:464 0.0005753583 +114 prog_clk[0]:361 prog_clk[0]:360 0.01209152 +115 prog_clk[0]:362 prog_clk[0]:361 0.00341 +116 prog_clk[0]:362 prog_clk[0]:355 0.000863625 +117 prog_clk[0]:342 prog_clk[0]:341 0.006627232 +118 prog_clk[0]:343 prog_clk[0]:342 0.00341 +119 prog_clk[0]:343 prog_clk[0]:283 0.0001053583 +120 prog_clk[0]:441 prog_clk[0]:440 0.009359376 +121 prog_clk[0]:442 prog_clk[0]:441 0.00341 +122 prog_clk[0]:442 prog_clk[0]:421 0.0001053583 +123 prog_clk[0]:419 prog_clk[0]:418 0.0045 +124 prog_clk[0]:420 prog_clk[0]:419 0.00341 +125 prog_clk[0]:418 prog_clk[0]:417 0.0005736608 +126 prog_clk[0]:417 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +127 prog_clk[0]:448 prog_clk[0]:447 0.0008593751 +128 prog_clk[0]:449 prog_clk[0]:448 0.00341 +129 prog_clk[0]:451 prog_clk[0]:450 0.00341 +130 prog_clk[0]:450 prog_clk[0]:449 0.0005741833 +131 prog_clk[0]:260 prog_clk[0]:259 0.007801339 +132 prog_clk[0]:261 prog_clk[0]:260 0.00341 +133 prog_clk[0]:261 prog_clk[0]:256 0.0005044666 +134 prog_clk[0]:258 prog_clk[0]:257 0.0001005435 +135 prog_clk[0]:259 prog_clk[0]:258 0.0045 +136 prog_clk[0]:257 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +137 prog_clk[0]:335 prog_clk[0]:334 0.00341 +138 prog_clk[0]:335 prog_clk[0]:301 0.009410716 +139 prog_clk[0]:334 prog_clk[0]:333 0.0001429583 +140 prog_clk[0]:190 prog_clk[0]:189 0.00341 +141 prog_clk[0]:189 prog_clk[0]:188 0.000431225 +142 prog_clk[0]:425 prog_clk[0]:424 0.001191964 +143 prog_clk[0]:426 prog_clk[0]:425 0.0045 +144 prog_clk[0]:422 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +145 prog_clk[0]:486 prog_clk[0]:485 0.002680804 +146 prog_clk[0]:487 prog_clk[0]:486 0.00341 +147 prog_clk[0]:489 prog_clk[0]:488 0.00341 +148 prog_clk[0]:488 prog_clk[0]:487 0.0003579833 +149 prog_clk[0]:265 prog_clk[0]:264 0.006587054 +150 prog_clk[0]:266 prog_clk[0]:265 0.00341 +151 prog_clk[0]:266 prog_clk[0]:261 0.0030268 +152 prog_clk[0]:263 prog_clk[0]:262 0.0001440217 +153 prog_clk[0]:264 prog_clk[0]:263 0.0045 +154 prog_clk[0]:262 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mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +430 prog_clk[0]:461 prog_clk[0]:460 0.0001847826 +431 prog_clk[0]:462 prog_clk[0]:461 0.0045 +432 prog_clk[0]:462 prog_clk[0]:459 0.002084822 +433 prog_clk[0]:460 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +434 prog_clk[0]:332 prog_clk[0]:331 0.0045 +435 prog_clk[0]:333 prog_clk[0]:332 0.00341 +436 prog_clk[0]:333 prog_clk[0]:329 0.001151892 +437 prog_clk[0]:331 prog_clk[0]:330 0.0001440218 +438 prog_clk[0]:330 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +439 prog_clk[0]:268 prog_clk[0]:267 0.001805804 +440 prog_clk[0]:269 prog_clk[0]:268 0.0045 +441 prog_clk[0]:267 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +442 prog_clk[0]:415 prog_clk[0]:414 0.0001059783 +443 prog_clk[0]:416 prog_clk[0]:415 0.0045 +444 prog_clk[0]:414 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +445 prog_clk[0]:274 prog_clk[0]:273 0.001805804 +446 prog_clk[0]:275 prog_clk[0]:274 0.0045 +447 prog_clk[0]:273 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +448 prog_clk[0]:87 prog_clk[0]:86 0.0045 +449 prog_clk[0]:88 prog_clk[0]:87 0.00341 +450 prog_clk[0]:86 prog_clk[0]:85 0.0005736608 +451 prog_clk[0]:85 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +452 prog_clk[0]:299 prog_clk[0]:298 0.0003705357 +453 prog_clk[0]:300 prog_clk[0]:299 0.0045 +454 prog_clk[0]:300 prog_clk[0]:296 0.005160714 +455 prog_clk[0]:297 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +456 prog_clk[0]:128 prog_clk[0]:127 0.004158482 +457 prog_clk[0]:129 prog_clk[0]:128 0.00341 +458 prog_clk[0]:129 prog_clk[0]:124 0.0001053583 +459 prog_clk[0]:126 prog_clk[0]:125 0.0001059783 +460 prog_clk[0]:127 prog_clk[0]:126 0.0045 +461 prog_clk[0]:125 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +462 prog_clk[0]:293 prog_clk[0]:292 0.0001847826 +463 prog_clk[0]:294 prog_clk[0]:293 0.0045 +464 prog_clk[0]:292 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +465 prog_clk[0]:154 prog_clk[0]:153 0.0001440218 +466 prog_clk[0]:155 prog_clk[0]:154 0.0045 +467 prog_clk[0]:153 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +468 prog_clk[0]:187 prog_clk[0]:186 0.0045 +469 prog_clk[0]:188 prog_clk[0]:187 0.00341 +470 prog_clk[0]:188 prog_clk[0]:184 0.001440158 +471 prog_clk[0]:186 prog_clk[0]:185 0.0001059783 +472 prog_clk[0]:185 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_3_:CLK 0.152 +473 prog_clk[0]:192 prog_clk[0]:191 0.0001847826 +474 prog_clk[0]:193 prog_clk[0]:192 0.0045 +475 prog_clk[0]:193 prog_clk[0]:190 0.002073661 +476 prog_clk[0]:191 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +477 prog_clk[0]:166 prog_clk[0]:165 0.004765625 +478 prog_clk[0]:167 prog_clk[0]:166 0.00341 +479 prog_clk[0]:167 prog_clk[0]:162 0.0004324 +480 prog_clk[0]:164 prog_clk[0]:163 0.0001059783 +481 prog_clk[0]:165 prog_clk[0]:164 0.0045 +482 prog_clk[0]:163 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +483 prog_clk[0]:313 prog_clk[0]:312 0.00341 +484 prog_clk[0]:312 prog_clk[0]:311 0.002016691 +485 prog_clk[0]:315 prog_clk[0]:314 0.004805804 +486 prog_clk[0]:316 prog_clk[0]:315 0.00341 +487 prog_clk[0]:318 prog_clk[0]:317 0.00341 +488 prog_clk[0]:317 prog_clk[0]:316 0.0001417833 +489 prog_clk[0]:530 prog_clk[0]:529 0.00341 +490 prog_clk[0]:529 prog_clk[0]:528 0.000431225 +491 prog_clk[0]:483 prog_clk[0]:482 0.0006138393 +492 prog_clk[0]:298 prog_clk[0]:297 0.0003035715 +493 prog_clk[0]:248 prog_clk[0]:247 0.0003035715 +494 prog_clk[0]:195 prog_clk[0]:194 0.0006138394 +495 prog_clk[0]:325 prog_clk[0]:324 0.001435268 +496 prog_clk[0]:150 prog_clk[0]:149 0.001024554 +497 prog_clk[0]:142 prog_clk[0]:141 0.001024554 +498 prog_clk[0]:134 prog_clk[0]:133 0.0006138393 +499 prog_clk[0]:431 prog_clk[0]:430 0.0006138393 +500 prog_clk[0]:424 prog_clk[0]:423 0.0006071428 +501 prog_clk[0]:116 prog_clk[0]:115 0.0006138393 +502 prog_clk[0]:423 prog_clk[0]:422 0.002654018 +503 prog_clk[0]:526 prog_clk[0]:525 0.007892857 +504 prog_clk[0]:526 prog_clk[0]:269 0.0004107143 +505 prog_clk[0]:346 prog_clk[0]:345 0.0004107143 +506 prog_clk[0]:498 prog_clk[0]:497 0.0004107143 +507 prog_clk[0]:498 prog_clk[0]:494 0.004857143 +508 prog_clk[0]:494 prog_clk[0]:493 0.0003705357 +509 prog_clk[0]:493 prog_clk[0]:492 0.00019375 +510 prog_clk[0]:493 prog_clk[0]:489 0.004805803 +511 prog_clk[0]:295 prog_clk[0]:294 0.00019375 +512 prog_clk[0]:295 prog_clk[0]:291 0.004857143 +513 prog_clk[0]:296 prog_clk[0]:295 0.0004107143 +514 prog_clk[0]:301 prog_clk[0]:300 0.0004107143 +515 prog_clk[0]:251 prog_clk[0]:250 0.0004107143 +516 prog_clk[0]:251 prog_clk[0]:246 0.004502232 +517 prog_clk[0]:314 prog_clk[0]:313 0.0004107143 +518 prog_clk[0]:92 prog_clk[0]:91 0.002388393 +519 prog_clk[0]:111 prog_clk[0]:110 0.0004107143 +520 prog_clk[0]:513 prog_clk[0]:512 0.0007206667 +521 prog_clk[0]:283 prog_clk[0]:282 0.0008636249 +522 prog_clk[0]:200 prog_clk[0]:199 0.0008648 +523 prog_clk[0]:158 prog_clk[0]:157 0.0001065333 +524 prog_clk[0]:240 prog_clk[0]:239 0.0001065333 +525 prog_clk[0]:306 prog_clk[0]:305 0.000647425 +526 prog_clk[0]:413 prog_clk[0]:412 0.0002882666 +527 prog_clk[0]:421 prog_clk[0]:420 0.0008636249 +528 prog_clk[0]:124 prog_clk[0]:123 0.0004324 +529 prog_clk[0]:103 prog_clk[0]:102 0.0001429583 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0] 0.000429538 //LENGTH 3.960 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l3_in_0_:X O *L 0 *C 85.385 96.900 +*I mux_top_track_8\/mux_l4_in_0_:A1 I *L 0.005458 *C 86.020 99.165 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 86.020 99.280 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 86.020 99.235 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 86.020 96.945 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 85.975 96.900 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 85.422 96.900 + +*CAP +0 mux_top_track_8\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:A1 2.296907e-05 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.296907e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001398023 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001398023 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.149769e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.149769e-05 + +*RES +0 mux_top_track_8\/mux_l3_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_8\/mux_l4_in_0_:A1 5.078125e-05 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0004933036 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007814735 //LENGTH 5.235 LUMPCC 0.0001406217 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_0_:X O *L 0 *C 46.745 114.920 +*I mux_top_track_4\/mux_l2_in_0_:A1 I *L 0.00198 *C 48.860 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 48.823 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 46.965 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 46.920 112.585 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 46.920 114.875 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 46.920 114.920 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 46.745 114.920 + +*CAP +0 mux_top_track_4\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001574507 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001574507 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001049405 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001049405 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.695605e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.711328e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_40_[0]:13 7.031085e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_40_[0]:14 7.031085e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0] 0.002759526 //LENGTH 19.425 LUMPCC 0.0008844502 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_6_:X O *L 0 *C 42.145 97.240 +*I mux_top_track_4\/mux_l2_in_3_:A1 I *L 0.00198 *C 56.220 101.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 56.183 101.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 50.185 101.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 50.140 101.615 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 50.140 97.285 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 50.095 97.240 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 42.183 97.240 + +*CAP +0 mux_top_track_4\/mux_l1_in_6_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002757517 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002757517 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002123759 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002123759 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004484105 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004484105 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 top_left_grid_pin_41_[0]:6 0.0001433568 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 top_left_grid_pin_41_[0]:7 0.0001433568 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size14_0_sram[0]:9 0.0002353635 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size14_0_sram[0]:47 0.0002353635 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size14_0_sram[0]:45 7.755597e-06 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size14_0_sram[0]:44 7.755597e-06 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.57492e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.57492e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_6_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_4\/mux_l2_in_3_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.005354911 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.003866072 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.007064733 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0005140611 //LENGTH 2.990 LUMPCC 0.0001413025 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_4_:X O *L 0 *C 35.705 15.640 +*I mux_bottom_track_5\/mux_l2_in_2_:A1 I *L 0.00198 *C 35.420 18.020 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 35.420 18.020 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 35.420 17.975 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 35.420 15.685 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 35.420 15.640 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 35.705 15.640 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_4_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.437801e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001090275 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001090275 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.966259e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.866298e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size14_1_sram[1]:24 7.065125e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size14_1_sram[1]:21 7.065125e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_4_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_5\/mux_l2_in_2_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002044643 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001548913 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0] 0.002181914 //LENGTH 19.255 LUMPCC 0.000301512 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_1_:X O *L 0 *C 51.345 80.240 +*I mux_top_track_16\/mux_l3_in_0_:A0 I *L 0.005103 *C 54.280 92.995 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 54.318 92.995 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 55.615 92.995 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 55.660 92.995 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 53.820 92.820 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 53.820 80.285 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 53.775 80.240 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 51.383 80.240 + +*CAP +0 mux_top_track_16\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001336004 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001336004 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001269941 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0006238141 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005302613 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000165066 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.000165066 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size6_0_sram[0]:26 9.634705e-05 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size6_0_sram[0]:27 4.260178e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size6_0_sram[0]:9 1.180718e-05 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size6_0_sram[0]:8 1.180718e-05 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size6_0_sram[0]:10 4.260178e-05 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size6_0_sram[0]:27 9.634705e-05 + +*RES +0 mux_top_track_16\/mux_l2_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.002136161 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.01119197 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001158482 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A0 0.152 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001642857 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0007331938 //LENGTH 4.780 LUMPCC 0.0003568795 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_1_:X O *L 0 *C 39.385 39.100 +*I mux_bottom_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 43.875 39.100 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 43.837 39.100 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 39.422 39.100 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001871572 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001871572 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.0001784397 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.0001784397 + +*RES +0 mux_bottom_track_17\/mux_l1_in_1_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003941964 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001095336 //LENGTH 7.815 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 33.295 90.440 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 26.220 90.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 26.220 90.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 26.220 90.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 33.258 90.440 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.462168e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005328238 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005058905 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006283482 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003771178 //LENGTH 2.860 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_0_:X O *L 0 *C 32.375 79.900 +*I mux_left_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 29.805 79.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 29.843 79.900 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 32.337 79.900 + +*CAP +0 mux_left_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001875589 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001875589 + +*RES +0 mux_left_track_3\/mux_l1_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002227679 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002989525 //LENGTH 17.165 LUMPCC 0.00167712 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_1_:X O *L 0 *C 41.115 69.020 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 27.430 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 27.430 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 27.600 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 27.600 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 27.608 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 38.172 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 38.180 71.343 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 38.180 69.065 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 38.225 69.020 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 41.078 69.020 + +*CAP +0 mux_left_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.546984e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.527597e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.707439e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002993842 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002993842 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000152054 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.000152054 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001298542 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001298542 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[16]:7 0.000219875 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[16]:6 0.000219875 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_top_grid_pin_42_[0]:20 9.45636e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 left_top_grid_pin_42_[0]:19 9.45636e-05 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_2_sram[1]:7 0.0002661992 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size3_2_sram[1]:8 0.0002661992 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size7_5_sram[0]:11 2.864402e-05 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size7_5_sram[0]:12 8.877243e-05 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size7_5_sram[0]:6 2.864402e-05 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size7_5_sram[0]:11 8.877243e-05 +21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mem_left_track_25/net_net_84:5 0.0001405056 +22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mem_left_track_25/net_net_84:6 0.0001405056 + +*RES +0 mux_left_track_5\/mux_l1_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00341 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001655183 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.002033482 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.002546875 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001645555 //LENGTH 14.560 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_0_:X O *L 0 *C 69.745 77.180 +*I mux_top_track_32\/mux_l3_in_0_:A1 I *L 0.00198 *C 80.960 79.900 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 80.960 79.900 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 80.960 79.855 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 80.960 77.225 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 80.915 77.180 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 69.782 77.180 + +*CAP +0 mux_top_track_32\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.331078e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001617251 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001617251 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0006433968 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0006433968 + +*RES +0 mux_top_track_32\/mux_l2_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.002348214 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.009939732 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004836242 //LENGTH 3.780 LUMPCC 0.0001766123 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_0_:X O *L 0 *C 24.095 30.940 +*I mux_bottom_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 20.605 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 20.643 30.940 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 24.058 30.940 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001525059 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001525059 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size6_2_sram[0]:17 8.830617e-05 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_2_sram[0]:18 8.830617e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003049107 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008787185 //LENGTH 7.105 LUMPCC 8.948348e-05 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_1_:X O *L 0 *C 28.235 31.620 +*I mux_bottom_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.810 37.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 28.773 37.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 28.105 37.060 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.060 37.015 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.060 31.665 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 28.060 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 28.235 31.620 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.809215e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.809215e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002862056 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002862056 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.041535e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.822411e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.214622e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 1.214622e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.259552e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.259552e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0005959822 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00161936 //LENGTH 13.110 LUMPCC 0.0001598335 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_1_:X O *L 0 *C 73.885 69.020 +*I mux_left_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 81.250 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 81.250 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 80.960 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 80.960 64.645 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 80.960 65.903 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 80.953 65.960 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 75.907 65.960 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 75.900 66.017 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 75.900 68.975 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 75.855 69.020 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 73.922 69.020 + +*CAP +0 mux_left_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.757864e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.151838e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 8.991195e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.991195e-05 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002543935 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002543935 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.000188119 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.000188119 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001467904 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001467904 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 7.991677e-05 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 7.991677e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_1_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001576087 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001122768 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0007903834 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002640625 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.001725447 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0004598673 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mux_left_track_15\/mux_l3_in_0_:X O *L 0 *C 6.155 59.160 +*I mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 6.155 61.000 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 6.155 61.000 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 5.980 60.860 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 5.980 60.815 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 5.980 59.205 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 5.980 59.160 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 6.155 59.160 + +*CAP +0 mux_left_track_15\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.530156e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.577495e-05 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001148547 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001148547 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.87774e-05 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.8304e-05 + +*RES +0 mux_left_track_15\/mux_l3_in_0_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00578397 //LENGTH 33.385 LUMPCC 0.002704102 DR + +*CONN +*I mux_left_track_21\/mux_l1_in_0_:X O *L 0 *C 53.075 72.760 +*I mux_left_track_21\/mux_l2_in_0_:A1 I *L 0.00198 *C 26.585 74.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 26.623 74.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.475 74.460 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.520 74.505 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.520 76.103 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 28.527 76.160 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 50.133 76.160 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 50.140 76.103 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 50.140 72.818 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 50.148 72.760 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 52.893 72.760 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:12 *C 52.900 72.760 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:13 *C 52.900 72.760 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:14 *C 53.075 72.760 + +*CAP +0 mux_left_track_21\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_21\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001817249 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001817249 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001066544 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001066544 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0007665033 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0007665033 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002006833 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002006833 +10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0002116304 +11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0002116304 +12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:12 3.63419e-05 +13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:13 5.546586e-05 +14 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:14 5.166824e-05 +15 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:478 9.190884e-08 +16 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:477 9.190884e-08 +17 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:475 0.0001634721 +18 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:476 5.907601e-05 +19 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:471 0.0001634721 +20 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:475 5.907601e-05 +21 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[15] 0.0002114508 +22 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[15]:11 0.0002114508 +23 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 left_top_grid_pin_49_[0]:21 0.0003155377 +24 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 left_top_grid_pin_49_[0]:16 0.0003155377 +25 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_0_sram[0]:18 0.0006017066 +26 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size7_0_sram[0]:19 0.0006017066 +27 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size7_0_sram[0]:18 7.160102e-07 +28 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_tree_tapbuf_size7_0_sram[0]:19 7.160102e-07 + +*RES +0 mux_left_track_21\/mux_l1_in_0_:X mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:14 0.152 +1 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_21\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001654018 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001426339 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.00341 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00341 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003384783 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.002933036 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.00341 +10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.00341 +11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.00043005 +12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:12 0.0045 +13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:14 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:13 9.51087e-05 + +*END + +*D_NET ropt_net_197 0.0007988525 //LENGTH 5.925 LUMPCC 0.0001243088 DR + +*CONN +*I ropt_mt_inst_773:X O *L 0 *C 85.295 124.440 +*I ropt_mt_inst_830:A I *L 0.001767 *C 82.340 126.480 +*N ropt_net_197:2 *C 82.377 126.480 +*N ropt_net_197:3 *C 82.755 126.480 +*N ropt_net_197:4 *C 82.800 126.435 +*N ropt_net_197:5 *C 82.800 124.485 +*N ropt_net_197:6 *C 82.845 124.440 +*N ropt_net_197:7 *C 85.258 124.440 + +*CAP +0 ropt_mt_inst_773:X 1e-06 +1 ropt_mt_inst_830:A 1e-06 +2 ropt_net_197:2 6.423364e-05 +3 ropt_net_197:3 6.423364e-05 +4 ropt_net_197:4 9.376054e-05 +5 ropt_net_197:5 9.376054e-05 +6 ropt_net_197:6 0.0001782777 +7 ropt_net_197:7 0.0001782777 +8 ropt_net_197:5 chany_top_out[5]:3 6.215438e-05 +9 ropt_net_197:4 chany_top_out[5]:2 6.215438e-05 + +*RES +0 ropt_mt_inst_773:X ropt_net_197:7 0.152 +1 ropt_net_197:7 ropt_net_197:6 0.002154018 +2 ropt_net_197:6 ropt_net_197:5 0.0045 +3 ropt_net_197:5 ropt_net_197:4 0.001741071 +4 ropt_net_197:3 ropt_net_197:2 0.0003370536 +5 ropt_net_197:4 ropt_net_197:3 0.0045 +6 ropt_net_197:2 ropt_mt_inst_830:A 0.152 + +*END + +*D_NET chany_bottom_out[17] 0.0007609952 //LENGTH 5.530 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_808:X O *L 0 *C 61.835 3.400 +*P chany_bottom_out[17] O *L 0.7423 *C 58.880 1.290 +*N chany_bottom_out[17]:2 *C 58.880 3.355 +*N chany_bottom_out[17]:3 *C 58.925 3.400 +*N chany_bottom_out[17]:4 *C 61.797 3.400 + +*CAP +0 ropt_mt_inst_808:X 1e-06 +1 chany_bottom_out[17] 0.0001322148 +2 chany_bottom_out[17]:2 0.0001322148 +3 chany_bottom_out[17]:3 0.0002477828 +4 chany_bottom_out[17]:4 0.0002477828 + +*RES +0 ropt_mt_inst_808:X chany_bottom_out[17]:4 0.152 +1 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.002564732 +2 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0045 +3 chany_bottom_out[17]:2 chany_bottom_out[17] 0.00184375 + +*END + +*D_NET ropt_net_183 0.001218599 //LENGTH 8.205 LUMPCC 0.0003666495 DR + +*CONN +*I ropt_mt_inst_780:X O *L 0 *C 65.055 123.080 +*I ropt_mt_inst_810:A I *L 0.001767 *C 61.180 126.480 +*N ropt_net_183:2 *C 61.218 126.480 +*N ropt_net_183:3 *C 61.595 126.480 +*N ropt_net_183:4 *C 61.640 126.435 +*N ropt_net_183:5 *C 61.640 123.125 +*N ropt_net_183:6 *C 61.685 123.080 +*N ropt_net_183:7 *C 65.017 123.080 + +*CAP +0 ropt_mt_inst_780:X 1e-06 +1 ropt_mt_inst_810:A 1e-06 +2 ropt_net_183:2 5.723324e-05 +3 ropt_net_183:3 5.723324e-05 +4 ropt_net_183:4 0.0001866681 +5 ropt_net_183:5 0.0001866681 +6 ropt_net_183:6 0.0001810736 +7 ropt_net_183:7 0.0001810736 +8 ropt_net_183:4 chany_bottom_in[8]:8 1.740731e-08 +9 ropt_net_183:6 chany_bottom_in[8]:6 0.0001106412 +10 ropt_net_183:5 chany_bottom_in[8]:11 1.740731e-08 +11 ropt_net_183:7 chany_bottom_in[8]:7 0.0001106412 +12 ropt_net_183:4 ropt_net_186:7 7.266614e-05 +13 ropt_net_183:5 ropt_net_186:8 7.266614e-05 + +*RES +0 ropt_mt_inst_780:X ropt_net_183:7 0.152 +1 ropt_net_183:2 ropt_mt_inst_810:A 0.152 +2 ropt_net_183:3 ropt_net_183:2 0.0003370536 +3 ropt_net_183:4 ropt_net_183:3 0.0045 +4 ropt_net_183:6 ropt_net_183:5 0.0045 +5 ropt_net_183:5 ropt_net_183:4 0.002955357 +6 ropt_net_183:7 ropt_net_183:6 0.002975446 + +*END + +*D_NET chany_top_out[17] 0.0002963972 //LENGTH 2.270 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_810:X O *L 0 *C 62.100 127.160 +*P chany_top_out[17] O *L 0.7423 *C 62.100 129.270 +*N chany_top_out[17]:2 *C 62.100 127.205 +*N chany_top_out[17]:3 *C 62.100 127.160 + +*CAP +0 ropt_mt_inst_810:X 1e-06 +1 chany_top_out[17] 0.0001307361 +2 chany_top_out[17]:2 0.0001307361 +3 chany_top_out[17]:3 3.392511e-05 + +*RES +0 ropt_mt_inst_810:X chany_top_out[17]:3 0.152 +1 chany_top_out[17]:3 chany_top_out[17]:2 0.0045 +2 chany_top_out[17]:2 chany_top_out[17] 0.00184375 + +*END + +*D_NET ccff_tail[0] 0.001247521 //LENGTH 9.820 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_789:X O *L 0 *C 7.095 65.960 +*P ccff_tail[0] O *L 0.7423 *C 1.298 64.600 +*N ccff_tail[0]:2 *C 1.380 64.600 +*N ccff_tail[0]:3 *C 1.380 64.600 +*N ccff_tail[0]:4 *C 1.380 64.600 +*N ccff_tail[0]:5 *C 1.380 63.920 +*N ccff_tail[0]:6 *C 5.935 63.920 +*N ccff_tail[0]:7 *C 5.980 63.965 +*N ccff_tail[0]:8 *C 5.980 65.915 +*N ccff_tail[0]:9 *C 6.025 65.960 +*N ccff_tail[0]:10 *C 7.058 65.960 + +*CAP +0 ropt_mt_inst_789:X 1e-06 +1 ccff_tail[0] 3.22413e-05 +2 ccff_tail[0]:2 3.22413e-05 +3 ccff_tail[0]:3 3.159857e-05 +4 ccff_tail[0]:4 8.705628e-05 +5 ccff_tail[0]:5 0.0003169184 +6 ccff_tail[0]:6 0.0002667062 +7 ccff_tail[0]:7 0.0001494053 +8 ccff_tail[0]:8 0.0001494053 +9 ccff_tail[0]:9 9.047406e-05 +10 ccff_tail[0]:10 9.047406e-05 + +*RES +0 ropt_mt_inst_789:X ccff_tail[0]:10 0.152 +1 ccff_tail[0]:10 ccff_tail[0]:9 0.0009218751 +2 ccff_tail[0]:9 ccff_tail[0]:8 0.0045 +3 ccff_tail[0]:8 ccff_tail[0]:7 0.001741072 +4 ccff_tail[0]:6 ccff_tail[0]:5 0.004066964 +5 ccff_tail[0]:7 ccff_tail[0]:6 0.0045 +6 ccff_tail[0]:4 ccff_tail[0]:3 0.0045 +7 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +8 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 +9 ccff_tail[0]:5 ccff_tail[0]:4 0.0006071429 + +*END + +*D_NET ropt_net_199 0.0005450236 //LENGTH 3.780 LUMPCC 0.0002055048 DR + +*CONN +*I ropt_mt_inst_796:X O *L 0 *C 94.495 123.080 +*I ropt_mt_inst_833:A I *L 0.001767 *C 93.380 121.040 +*N ropt_net_199:2 *C 93.380 121.040 +*N ropt_net_199:3 *C 93.380 121.085 +*N ropt_net_199:4 *C 93.380 123.035 +*N ropt_net_199:5 *C 93.425 123.080 +*N ropt_net_199:6 *C 94.458 123.080 + +*CAP +0 ropt_mt_inst_796:X 1e-06 +1 ropt_mt_inst_833:A 1e-06 +2 ropt_net_199:2 3.109032e-05 +3 ropt_net_199:3 9.673003e-05 +4 ropt_net_199:4 9.673003e-05 +5 ropt_net_199:5 5.648428e-05 +6 ropt_net_199:6 5.648428e-05 +7 ropt_net_199:3 chany_bottom_in[13]:13 9.72051e-06 +8 ropt_net_199:5 chany_bottom_in[13]:11 5.291831e-05 +9 ropt_net_199:4 chany_bottom_in[13]:12 9.72051e-06 +10 ropt_net_199:6 chany_bottom_in[13]:10 5.291831e-05 +11 ropt_net_199:3 chany_top_out[11]:2 4.011357e-05 +12 ropt_net_199:4 chany_top_out[11] 4.011357e-05 + +*RES +0 ropt_mt_inst_796:X ropt_net_199:6 0.152 +1 ropt_net_199:2 ropt_mt_inst_833:A 0.152 +2 ropt_net_199:3 ropt_net_199:2 0.0045 +3 ropt_net_199:5 ropt_net_199:4 0.0045 +4 ropt_net_199:4 ropt_net_199:3 0.001741072 +5 ropt_net_199:6 ropt_net_199:5 0.000921875 + +*END + +*D_NET chanx_left_out[14] 0.0007567475 //LENGTH 5.165 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_817:X O *L 0 *C 4.600 55.760 +*P chanx_left_out[14] O *L 0.7423 *C 1.305 54.400 +*N chanx_left_out[14]:2 *C 4.593 54.400 +*N chanx_left_out[14]:3 *C 4.600 54.458 +*N chanx_left_out[14]:4 *C 4.600 55.715 +*N chanx_left_out[14]:5 *C 4.600 55.760 + +*CAP +0 ropt_mt_inst_817:X 1e-06 +1 chanx_left_out[14] 0.0002486859 +2 chanx_left_out[14]:2 0.0002486859 +3 chanx_left_out[14]:3 0.0001124873 +4 chanx_left_out[14]:4 0.0001124873 +5 chanx_left_out[14]:5 3.340112e-05 + +*RES +0 ropt_mt_inst_817:X chanx_left_out[14]:5 0.152 +1 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +2 chanx_left_out[14]:2 chanx_left_out[14] 0.0005150416 +3 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +4 chanx_left_out[14]:4 chanx_left_out[14]:3 0.001122768 + +*END + +*D_NET chany_bottom_out[10] 0.000518783 //LENGTH 4.295 LUMPCC 0.000123773 DR + +*CONN +*I ropt_mt_inst_825:X O *L 0 *C 94.760 3.740 +*P chany_bottom_out[10] O *L 0.7423 *C 93.380 1.290 +*N chany_bottom_out[10]:2 *C 93.380 3.695 +*N chany_bottom_out[10]:3 *C 93.425 3.740 +*N chany_bottom_out[10]:4 *C 94.723 3.740 + +*CAP +0 ropt_mt_inst_825:X 1e-06 +1 chany_bottom_out[10] 0.0001326234 +2 chany_bottom_out[10]:2 0.0001326234 +3 chany_bottom_out[10]:3 6.438166e-05 +4 chany_bottom_out[10]:4 6.438166e-05 +5 chany_bottom_out[10] ropt_net_193:4 1.596367e-05 +6 chany_bottom_out[10]:4 ropt_net_193:6 4.59228e-05 +7 chany_bottom_out[10]:3 ropt_net_193:5 4.59228e-05 +8 chany_bottom_out[10]:2 ropt_net_193:3 1.596367e-05 + +*RES +0 ropt_mt_inst_825:X chany_bottom_out[10]:4 0.152 +1 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.001158482 +2 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0045 +3 chany_bottom_out[10]:2 chany_bottom_out[10] 0.002147322 + +*END + +*D_NET ropt_net_159 0.001453 //LENGTH 12.550 LUMPCC 0.0002707143 DR + +*CONN +*I BUFT_P_109:X O *L 0 *C 80.960 116.280 +*I ropt_mt_inst_784:A I *L 0.001766 *C 76.820 123.760 +*N ropt_net_159:2 *C 76.858 123.760 +*N ropt_net_159:3 *C 78.615 123.760 +*N ropt_net_159:4 *C 78.660 123.715 +*N ropt_net_159:5 *C 78.660 116.325 +*N ropt_net_159:6 *C 78.705 116.280 +*N ropt_net_159:7 *C 80.922 116.280 + +*CAP +0 BUFT_P_109:X 1e-06 +1 ropt_mt_inst_784:A 1e-06 +2 ropt_net_159:2 0.0001233886 +3 ropt_net_159:3 0.0001233886 +4 ropt_net_159:4 0.0002978495 +5 ropt_net_159:5 0.0002978495 +6 ropt_net_159:6 0.000168905 +7 ropt_net_159:7 0.000168905 +8 ropt_net_159:5 chany_top_out[2]:2 6.140303e-05 +9 ropt_net_159:4 chany_top_out[2] 6.140303e-05 +10 ropt_net_159:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 7.395411e-05 +11 ropt_net_159:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.395411e-05 + +*RES +0 BUFT_P_109:X ropt_net_159:7 0.152 +1 ropt_net_159:7 ropt_net_159:6 0.001979911 +2 ropt_net_159:6 ropt_net_159:5 0.0045 +3 ropt_net_159:5 ropt_net_159:4 0.006598215 +4 ropt_net_159:3 ropt_net_159:2 0.001569197 +5 ropt_net_159:4 ropt_net_159:3 0.0045 +6 ropt_net_159:2 ropt_mt_inst_784:A 0.152 + +*END + +*D_NET chany_top_in[7] 0.01355559 //LENGTH 106.305 LUMPCC 0.002238336 DR + +*CONN +*P chany_top_in[7] I *L 0.29796 *C 66.700 129.270 +*I ropt_mt_inst_781:A I *L 0.001767 *C 3.220 91.120 +*N chany_top_in[7]:2 *C 3.183 91.120 +*N chany_top_in[7]:3 *C 2.345 91.120 +*N chany_top_in[7]:4 *C 2.300 91.165 +*N chany_top_in[7]:5 *C 2.300 98.895 +*N chany_top_in[7]:6 *C 2.345 98.940 +*N chany_top_in[7]:7 *C 5.935 98.940 +*N chany_top_in[7]:8 *C 5.980 98.985 +*N chany_top_in[7]:9 *C 5.980 101.615 +*N chany_top_in[7]:10 *C 5.980 101.660 +*N chany_top_in[7]:11 *C 5.980 102.680 +*N chany_top_in[7]:12 *C 38.135 102.680 +*N chany_top_in[7]:13 *C 38.180 102.725 +*N chany_top_in[7]:14 *C 38.180 103.983 +*N chany_top_in[7]:15 *C 38.188 104.040 +*N chany_top_in[7]:16 *C 66.233 104.040 +*N chany_top_in[7]:17 *C 66.240 104.098 +*N chany_top_in[7]:18 *C 66.240 124.100 +*N chany_top_in[7]:19 *C 66.700 124.100 + +*CAP +0 chany_top_in[7] 0.0002028865 +1 ropt_mt_inst_781:A 1e-06 +2 chany_top_in[7]:2 1.284614e-05 +3 chany_top_in[7]:3 1.284614e-05 +4 chany_top_in[7]:4 0.000193715 +5 chany_top_in[7]:5 0.000193715 +6 chany_top_in[7]:6 0.0002412921 +7 chany_top_in[7]:7 0.0002412921 +8 chany_top_in[7]:8 0.0001560747 +9 chany_top_in[7]:9 0.0001560747 +10 chany_top_in[7]:10 9.44342e-05 +11 chany_top_in[7]:11 0.001853137 +12 chany_top_in[7]:12 0.001790622 +13 chany_top_in[7]:13 9.64004e-05 +14 chany_top_in[7]:14 9.64004e-05 +15 chany_top_in[7]:15 0.002012274 +16 chany_top_in[7]:16 0.002012274 +17 chany_top_in[7]:17 0.0008573527 +18 chany_top_in[7]:18 0.0008735431 +19 chany_top_in[7]:19 0.0002190769 +20 chany_top_in[7] chany_top_in[16]:18 0.0001276507 +21 chany_top_in[7]:17 chany_top_in[16]:16 0.0002117948 +22 chany_top_in[7]:17 chany_top_in[16]:17 2.874471e-06 +23 chany_top_in[7]:18 chany_top_in[16]:18 2.874471e-06 +24 chany_top_in[7]:18 chany_top_in[16]:17 0.0002117948 +25 chany_top_in[7]:19 chany_top_in[16]:17 0.0001276507 +26 chany_top_in[7]:12 chany_top_in[19]:13 0.0002254394 +27 chany_top_in[7]:12 chany_top_in[19]:11 8.487869e-05 +28 chany_top_in[7]:11 chany_top_in[19]:10 8.487869e-05 +29 chany_top_in[7]:11 chany_top_in[19]:12 0.0002254394 +30 chany_top_in[7]:2 left_top_grid_pin_46_[0]:13 4.455197e-05 +31 chany_top_in[7]:3 left_top_grid_pin_46_[0]:14 4.455197e-05 +32 chany_top_in[7]:4 left_top_grid_pin_46_[0]:15 0.0002078367 +33 chany_top_in[7]:5 left_top_grid_pin_46_[0]:16 0.0002078367 +34 chany_top_in[7]:4 ropt_net_145:4 0.0001030221 +35 chany_top_in[7]:5 ropt_net_145:3 0.0001030221 +36 chany_top_in[7]:17 ropt_net_174:5 4.968265e-05 +37 chany_top_in[7]:18 ropt_net_174:6 4.968265e-05 +38 chany_top_in[7]:18 ropt_net_174:3 1.688473e-05 +39 chany_top_in[7]:19 ropt_net_174:4 1.688473e-05 +40 chany_top_in[7]:2 ropt_net_202:8 4.455197e-05 +41 chany_top_in[7]:3 ropt_net_202:7 4.455197e-05 + +*RES +0 chany_top_in[7] chany_top_in[7]:19 0.004616071 +1 chany_top_in[7]:2 ropt_mt_inst_781:A 0.152 +2 chany_top_in[7]:3 chany_top_in[7]:2 0.0007477679 +3 chany_top_in[7]:4 chany_top_in[7]:3 0.0045 +4 chany_top_in[7]:6 chany_top_in[7]:5 0.0045 +5 chany_top_in[7]:5 chany_top_in[7]:4 0.006901786 +6 chany_top_in[7]:7 chany_top_in[7]:6 0.003205357 +7 chany_top_in[7]:8 chany_top_in[7]:7 0.0045 +8 chany_top_in[7]:10 chany_top_in[7]:9 0.0045 +9 chany_top_in[7]:9 chany_top_in[7]:8 0.002348214 +10 chany_top_in[7]:12 chany_top_in[7]:11 0.02870983 +11 chany_top_in[7]:13 chany_top_in[7]:12 0.0045 +12 chany_top_in[7]:14 chany_top_in[7]:13 0.001122768 +13 chany_top_in[7]:15 chany_top_in[7]:14 0.00341 +14 chany_top_in[7]:17 chany_top_in[7]:16 0.00341 +15 chany_top_in[7]:16 chany_top_in[7]:15 0.004393716 +16 chany_top_in[7]:11 chany_top_in[7]:10 0.0009107143 +17 chany_top_in[7]:18 chany_top_in[7]:17 0.01785938 +18 chany_top_in[7]:19 chany_top_in[7]:18 0.0004107143 + +*END + +*D_NET chany_top_in[0] 0.01220685 //LENGTH 91.650 LUMPCC 0.001128047 DR + +*CONN +*P chany_top_in[0] I *L 0.29796 *C 80.500 129.270 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 34.865 90.780 +*N chany_top_in[0]:2 *C 34.903 90.780 +*N chany_top_in[0]:3 *C 35.835 90.780 +*N chany_top_in[0]:4 *C 35.880 90.825 +*N chany_top_in[0]:5 *C 35.880 95.823 +*N chany_top_in[0]:6 *C 35.888 95.880 +*N chany_top_in[0]:7 *C 80.032 95.880 +*N chany_top_in[0]:8 *C 80.040 95.938 +*N chany_top_in[0]:9 *C 80.040 101.660 +*N chany_top_in[0]:10 *C 79.580 101.660 +*N chany_top_in[0]:11 *C 79.580 107.055 +*N chany_top_in[0]:12 *C 79.625 107.100 +*N chany_top_in[0]:13 *C 80.455 107.100 +*N chany_top_in[0]:14 *C 80.500 107.145 +*N chany_top_in[0]:15 *C 80.500 110.500 +*N chany_top_in[0]:16 *C 80.960 110.500 +*N chany_top_in[0]:17 *C 80.960 113.515 +*N chany_top_in[0]:18 *C 80.915 113.560 +*N chany_top_in[0]:19 *C 80.085 113.560 +*N chany_top_in[0]:20 *C 80.040 113.605 +*N chany_top_in[0]:21 *C 80.040 114.920 +*N chany_top_in[0]:22 *C 80.500 114.920 +*N chany_top_in[0]:23 *C 80.500 119.000 +*N chany_top_in[0]:24 *C 80.040 119.000 +*N chany_top_in[0]:25 *C 80.040 123.420 +*N chany_top_in[0]:26 *C 80.500 123.420 + +*CAP +0 chany_top_in[0] 0.0003161848 +1 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +2 chany_top_in[0]:2 9.38504e-05 +3 chany_top_in[0]:3 9.38504e-05 +4 chany_top_in[0]:4 0.0002641701 +5 chany_top_in[0]:5 0.0002641701 +6 chany_top_in[0]:6 0.003171797 +7 chany_top_in[0]:7 0.003171797 +8 chany_top_in[0]:8 0.0003345109 +9 chany_top_in[0]:9 0.0003299131 +10 chany_top_in[0]:10 0.000212092 +11 chany_top_in[0]:11 0.0002166898 +12 chany_top_in[0]:12 0.000115233 +13 chany_top_in[0]:13 0.000115233 +14 chany_top_in[0]:14 0.0001395365 +15 chany_top_in[0]:15 0.0001372573 +16 chany_top_in[0]:16 0.0001518465 +17 chany_top_in[0]:17 0.0001541257 +18 chany_top_in[0]:18 5.774869e-05 +19 chany_top_in[0]:19 5.774869e-05 +20 chany_top_in[0]:20 5.710544e-05 +21 chany_top_in[0]:21 8.470527e-05 +22 chany_top_in[0]:22 0.0002781047 +23 chany_top_in[0]:23 0.0002806527 +24 chany_top_in[0]:24 0.0003321959 +25 chany_top_in[0]:25 0.000316575 +26 chany_top_in[0]:26 0.0003307119 +27 chany_top_in[0]:6 chany_bottom_in[4]:29 3.068651e-05 +28 chany_top_in[0]:6 chany_bottom_in[4]:30 3.979508e-06 +29 chany_top_in[0]:7 chany_bottom_in[4]:20 3.979508e-06 +30 chany_top_in[0]:7 chany_bottom_in[4]:30 3.068651e-05 +31 chany_top_in[0]:11 chany_bottom_in[4]:12 0.0001184715 +32 chany_top_in[0]:11 chany_bottom_in[4]:14 2.584135e-06 +33 chany_top_in[0]:14 chany_bottom_in[4]:13 9.606979e-05 +34 chany_top_in[0]:18 chany_bottom_in[4]:10 2.151225e-05 +35 chany_top_in[0]:17 chany_bottom_in[4]:8 3.442368e-06 +36 chany_top_in[0]:17 chany_bottom_in[4]:12 1.578872e-05 +37 chany_top_in[0]:19 chany_bottom_in[4]:11 2.151225e-05 +38 chany_top_in[0]:20 chany_bottom_in[4]:9 8.955266e-07 +39 chany_top_in[0]:10 chany_bottom_in[4]:13 0.0001202948 +40 chany_top_in[0]:10 chany_bottom_in[4]:15 2.584135e-06 +41 chany_top_in[0]:10 chany_bottom_in[4]:17 3.005164e-05 +42 chany_top_in[0]:9 chany_bottom_in[4]:14 1.823338e-06 +43 chany_top_in[0]:9 chany_bottom_in[4]:16 3.005164e-05 +44 chany_top_in[0]:21 chany_bottom_in[4]:8 8.955266e-07 +45 chany_top_in[0]:22 chany_bottom_in[4]:9 4.540659e-06 +46 chany_top_in[0]:24 chany_bottom_in[4]:9 5.724748e-07 +47 chany_top_in[0]:23 chany_bottom_in[4]:8 4.540659e-06 +48 chany_top_in[0]:25 chany_bottom_in[4]:8 5.724748e-07 +49 chany_top_in[0]:15 chany_bottom_in[4]:11 3.000747e-05 +50 chany_top_in[0]:15 chany_bottom_in[4]:12 9.606979e-05 +51 chany_top_in[0]:16 chany_bottom_in[4]:9 3.442368e-06 +52 chany_top_in[0]:16 chany_bottom_in[4]:10 3.000747e-05 +53 chany_top_in[0]:16 chany_bottom_in[4]:13 1.578872e-05 +54 chany_top_in[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.769459e-05 +55 chany_top_in[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.769459e-05 +56 chany_top_in[0]:11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.958738e-05 +57 chany_top_in[0]:17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.107824e-06 +58 chany_top_in[0]:20 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.221249e-05 +59 chany_top_in[0]:10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.958738e-05 +60 chany_top_in[0]:21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.221249e-05 +61 chany_top_in[0]:22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.732122e-07 +62 chany_top_in[0]:23 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.732122e-07 +63 chany_top_in[0]:16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.107824e-06 +64 chany_top_in[0] ropt_net_189:4 2.891005e-07 +65 chany_top_in[0] ropt_net_189:8 4.471487e-05 +66 chany_top_in[0]:25 ropt_net_189:6 1.631826e-05 +67 chany_top_in[0]:26 ropt_net_189:5 2.891005e-07 +68 chany_top_in[0]:26 ropt_net_189:7 1.631826e-05 +69 chany_top_in[0]:26 ropt_net_189:9 4.471487e-05 + +*RES +0 chany_top_in[0] chany_top_in[0]:26 0.005223215 +1 chany_top_in[0]:2 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[0]:3 chany_top_in[0]:2 0.0008325893 +3 chany_top_in[0]:4 chany_top_in[0]:3 0.0045 +4 chany_top_in[0]:5 chany_top_in[0]:4 0.004462054 +5 chany_top_in[0]:6 chany_top_in[0]:5 0.00341 +6 chany_top_in[0]:8 chany_top_in[0]:7 0.00341 +7 chany_top_in[0]:7 chany_top_in[0]:6 0.006916049 +8 chany_top_in[0]:12 chany_top_in[0]:11 0.0045 +9 chany_top_in[0]:11 chany_top_in[0]:10 0.004816965 +10 chany_top_in[0]:13 chany_top_in[0]:12 0.0007410714 +11 chany_top_in[0]:14 chany_top_in[0]:13 0.0045 +12 chany_top_in[0]:18 chany_top_in[0]:17 0.0045 +13 chany_top_in[0]:17 chany_top_in[0]:16 0.002691964 +14 chany_top_in[0]:19 chany_top_in[0]:18 0.0007410714 +15 chany_top_in[0]:20 chany_top_in[0]:19 0.0045 +16 chany_top_in[0]:10 chany_top_in[0]:9 0.0004107143 +17 chany_top_in[0]:9 chany_top_in[0]:8 0.005109375 +18 chany_top_in[0]:21 chany_top_in[0]:20 0.001174107 +19 chany_top_in[0]:22 chany_top_in[0]:21 0.0004107143 +20 chany_top_in[0]:24 chany_top_in[0]:23 0.0004107143 +21 chany_top_in[0]:23 chany_top_in[0]:22 0.003642857 +22 chany_top_in[0]:25 chany_top_in[0]:24 0.003946428 +23 chany_top_in[0]:26 chany_top_in[0]:25 0.0004107143 +24 chany_top_in[0]:15 chany_top_in[0]:14 0.002995536 +25 chany_top_in[0]:16 chany_top_in[0]:15 0.0004107143 + +*END + +*D_NET top_left_grid_pin_36_[0] 0.004633832 //LENGTH 39.220 LUMPCC 0.0001526831 DR + +*CONN +*P top_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 127.160 +*I mux_top_track_4\/mux_l1_in_1_:A1 I *L 0.00198 *C 43.800 112.540 +*I mux_top_track_24\/mux_l1_in_0_:A1 I *L 0.00198 *C 40.385 107.100 +*I mux_top_track_0\/mux_l1_in_0_:A0 I *L 0.001631 *C 41.690 125.800 +*N top_left_grid_pin_36_[0]:4 *C 41.727 125.800 +*N top_left_grid_pin_36_[0]:5 *C 42.650 125.800 +*N top_left_grid_pin_36_[0]:6 *C 42.780 125.800 +*N top_left_grid_pin_36_[0]:7 *C 40.422 107.100 +*N top_left_grid_pin_36_[0]:8 *C 41.815 107.100 +*N top_left_grid_pin_36_[0]:9 *C 41.860 107.145 +*N top_left_grid_pin_36_[0]:10 *C 43.763 112.540 +*N top_left_grid_pin_36_[0]:11 *C 41.905 112.540 +*N top_left_grid_pin_36_[0]:12 *C 41.860 112.540 +*N top_left_grid_pin_36_[0]:13 *C 41.860 125.800 +*N top_left_grid_pin_36_[0]:14 *C 41.860 127.103 +*N top_left_grid_pin_36_[0]:15 *C 41.852 127.160 + +*CAP +0 top_left_grid_pin_36_[0] 0.0007271963 +1 mux_top_track_4\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A1 1e-06 +3 mux_top_track_0\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_36_[0]:4 9.281607e-05 +5 top_left_grid_pin_36_[0]:5 9.281607e-05 +6 top_left_grid_pin_36_[0]:6 8.677616e-05 +7 top_left_grid_pin_36_[0]:7 0.000106785 +8 top_left_grid_pin_36_[0]:8 0.000106785 +9 top_left_grid_pin_36_[0]:9 0.0003134101 +10 top_left_grid_pin_36_[0]:10 0.0001642404 +11 top_left_grid_pin_36_[0]:11 0.0001642404 +12 top_left_grid_pin_36_[0]:12 0.001014845 +13 top_left_grid_pin_36_[0]:13 0.0008032942 +14 top_left_grid_pin_36_[0]:14 7.774719e-05 +15 top_left_grid_pin_36_[0]:15 0.0007271963 +16 top_left_grid_pin_36_[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.466149e-06 +17 top_left_grid_pin_36_[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.087539e-05 +18 top_left_grid_pin_36_[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.087539e-05 +19 top_left_grid_pin_36_[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.466149e-06 + +*RES +0 top_left_grid_pin_36_[0] top_left_grid_pin_36_[0]:15 0.001896058 +1 top_left_grid_pin_36_[0]:14 top_left_grid_pin_36_[0]:13 0.001162946 +2 top_left_grid_pin_36_[0]:15 top_left_grid_pin_36_[0]:14 0.00341 +3 top_left_grid_pin_36_[0]:5 top_left_grid_pin_36_[0]:4 0.0008236608 +4 top_left_grid_pin_36_[0]:6 top_left_grid_pin_36_[0]:5 0.0045 +5 top_left_grid_pin_36_[0]:4 mux_top_track_0\/mux_l1_in_0_:A0 0.152 +6 top_left_grid_pin_36_[0]:11 top_left_grid_pin_36_[0]:10 0.001658482 +7 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:11 0.0045 +8 top_left_grid_pin_36_[0]:12 top_left_grid_pin_36_[0]:9 0.004816965 +9 top_left_grid_pin_36_[0]:10 mux_top_track_4\/mux_l1_in_1_:A1 0.152 +10 top_left_grid_pin_36_[0]:8 top_left_grid_pin_36_[0]:7 0.001243304 +11 top_left_grid_pin_36_[0]:9 top_left_grid_pin_36_[0]:8 0.0045 +12 top_left_grid_pin_36_[0]:7 mux_top_track_24\/mux_l1_in_0_:A1 0.152 +13 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:12 0.01183929 +14 top_left_grid_pin_36_[0]:13 top_left_grid_pin_36_[0]:6 0.0008214285 + +*END + +*D_NET top_left_grid_pin_38_[0] 0.009427869 //LENGTH 60.240 LUMPCC 0.002032697 DR + +*CONN +*P top_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 125.120 +*I mux_top_track_0\/mux_l1_in_1_:A1 I *L 0.00198 *C 47.840 123.420 +*I mux_top_track_4\/mux_l1_in_2_:A1 I *L 0.00198 *C 50.240 117.980 +*I mux_top_track_8\/mux_l1_in_0_:A0 I *L 0.001631 *C 75.615 114.920 +*N top_left_grid_pin_38_[0]:4 *C 75.578 114.920 +*N top_left_grid_pin_38_[0]:5 *C 73.185 114.920 +*N top_left_grid_pin_38_[0]:6 *C 73.140 114.920 +*N top_left_grid_pin_38_[0]:7 *C 73.133 114.920 +*N top_left_grid_pin_38_[0]:8 *C 50.148 114.920 +*N top_left_grid_pin_38_[0]:9 *C 50.140 114.978 +*N top_left_grid_pin_38_[0]:10 *C 50.140 117.935 +*N top_left_grid_pin_38_[0]:11 *C 50.153 117.980 +*N top_left_grid_pin_38_[0]:12 *C 48.345 117.980 +*N top_left_grid_pin_38_[0]:13 *C 48.300 118.025 +*N top_left_grid_pin_38_[0]:14 *C 47.878 123.420 +*N top_left_grid_pin_38_[0]:15 *C 48.255 123.420 +*N top_left_grid_pin_38_[0]:16 *C 48.300 123.420 +*N top_left_grid_pin_38_[0]:17 *C 48.300 124.395 +*N top_left_grid_pin_38_[0]:18 *C 48.255 124.440 +*N top_left_grid_pin_38_[0]:19 *C 38.180 124.440 +*N top_left_grid_pin_38_[0]:20 *C 38.180 124.100 +*N top_left_grid_pin_38_[0]:21 *C 32.245 124.100 +*N top_left_grid_pin_38_[0]:22 *C 32.200 124.145 +*N top_left_grid_pin_38_[0]:23 *C 32.200 125.062 +*N top_left_grid_pin_38_[0]:24 *C 32.193 125.120 + +*CAP +0 top_left_grid_pin_38_[0] 0.0001685673 +1 mux_top_track_0\/mux_l1_in_1_:A1 1e-06 +2 mux_top_track_4\/mux_l1_in_2_:A1 1e-06 +3 mux_top_track_8\/mux_l1_in_0_:A0 1e-06 +4 top_left_grid_pin_38_[0]:4 0.0001308084 +5 top_left_grid_pin_38_[0]:5 0.0001308084 +6 top_left_grid_pin_38_[0]:6 3.229513e-05 +7 top_left_grid_pin_38_[0]:7 0.001360482 +8 top_left_grid_pin_38_[0]:8 0.001360482 +9 top_left_grid_pin_38_[0]:9 0.0001998896 +10 top_left_grid_pin_38_[0]:10 0.0001998896 +11 top_left_grid_pin_38_[0]:11 0.0001398968 +12 top_left_grid_pin_38_[0]:12 0.0001398968 +13 top_left_grid_pin_38_[0]:13 0.0003548152 +14 top_left_grid_pin_38_[0]:14 4.495539e-05 +15 top_left_grid_pin_38_[0]:15 4.495539e-05 +16 top_left_grid_pin_38_[0]:16 0.0004572857 +17 top_left_grid_pin_38_[0]:17 6.781848e-05 +18 top_left_grid_pin_38_[0]:18 0.0006802009 +19 top_left_grid_pin_38_[0]:19 0.0007096389 +20 top_left_grid_pin_38_[0]:20 0.0004326067 +21 top_left_grid_pin_38_[0]:21 0.0004031688 +22 top_left_grid_pin_38_[0]:22 8.257134e-05 +23 top_left_grid_pin_38_[0]:23 8.257134e-05 +24 top_left_grid_pin_38_[0]:24 0.0001685673 +25 top_left_grid_pin_38_[0]:8 top_left_grid_pin_34_[0]:10 0.0008234975 +26 top_left_grid_pin_38_[0]:7 top_left_grid_pin_34_[0]:9 0.0008234975 +27 top_left_grid_pin_38_[0]:5 top_left_grid_pin_34_[0]:6 9.178608e-05 +28 top_left_grid_pin_38_[0]:4 top_left_grid_pin_34_[0]:5 9.178608e-05 +29 top_left_grid_pin_38_[0]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.750907e-05 +30 top_left_grid_pin_38_[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 2.355596e-05 +31 top_left_grid_pin_38_[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 2.355596e-05 +32 top_left_grid_pin_38_[0]:19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.750907e-05 + +*RES +0 top_left_grid_pin_38_[0] top_left_grid_pin_38_[0]:24 0.0003826583 +1 top_left_grid_pin_38_[0]:12 top_left_grid_pin_38_[0]:11 0.001613839 +2 top_left_grid_pin_38_[0]:13 top_left_grid_pin_38_[0]:12 0.0045 +3 top_left_grid_pin_38_[0]:18 top_left_grid_pin_38_[0]:17 0.0045 +4 top_left_grid_pin_38_[0]:17 top_left_grid_pin_38_[0]:16 0.0008705358 +5 top_left_grid_pin_38_[0]:21 top_left_grid_pin_38_[0]:20 0.005299107 +6 top_left_grid_pin_38_[0]:22 top_left_grid_pin_38_[0]:21 0.0045 +7 top_left_grid_pin_38_[0]:23 top_left_grid_pin_38_[0]:22 0.0008191965 +8 top_left_grid_pin_38_[0]:24 top_left_grid_pin_38_[0]:23 0.00341 +9 top_left_grid_pin_38_[0]:11 mux_top_track_4\/mux_l1_in_2_:A1 0.152 +10 top_left_grid_pin_38_[0]:11 top_left_grid_pin_38_[0]:10 0.0045 +11 top_left_grid_pin_38_[0]:15 top_left_grid_pin_38_[0]:14 0.0003370536 +12 top_left_grid_pin_38_[0]:16 top_left_grid_pin_38_[0]:15 0.0045 +13 top_left_grid_pin_38_[0]:16 top_left_grid_pin_38_[0]:13 0.004816964 +14 top_left_grid_pin_38_[0]:14 mux_top_track_0\/mux_l1_in_1_:A1 0.152 +15 top_left_grid_pin_38_[0]:10 top_left_grid_pin_38_[0]:9 0.002640625 +16 top_left_grid_pin_38_[0]:9 top_left_grid_pin_38_[0]:8 0.00341 +17 top_left_grid_pin_38_[0]:8 top_left_grid_pin_38_[0]:7 0.003600983 +18 top_left_grid_pin_38_[0]:6 top_left_grid_pin_38_[0]:5 0.0045 +19 top_left_grid_pin_38_[0]:7 top_left_grid_pin_38_[0]:6 0.00341 +20 top_left_grid_pin_38_[0]:5 top_left_grid_pin_38_[0]:4 0.002136161 +21 top_left_grid_pin_38_[0]:4 mux_top_track_8\/mux_l1_in_0_:A0 0.152 +22 top_left_grid_pin_38_[0]:20 top_left_grid_pin_38_[0]:19 0.0003035715 +23 top_left_grid_pin_38_[0]:19 top_left_grid_pin_38_[0]:18 0.008995537 + +*END + +*D_NET chany_bottom_in[0] 0.01614348 //LENGTH 129.185 LUMPCC 0.003383151 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 82.340 1.290 +*I mux_left_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 34.330 80.580 +*N chany_bottom_in[0]:2 *C 34.560 80.240 +*N chany_bottom_in[0]:3 *C 34.367 80.580 +*N chany_bottom_in[0]:4 *C 34.915 80.580 +*N chany_bottom_in[0]:5 *C 34.960 80.580 +*N chany_bottom_in[0]:6 *C 34.960 80.240 +*N chany_bottom_in[0]:7 *C 34.960 80.240 +*N chany_bottom_in[0]:8 *C 34.960 80.233 +*N chany_bottom_in[0]:9 *C 34.960 51.875 +*N chany_bottom_in[0]:10 *C 34.960 2.048 +*N chany_bottom_in[0]:11 *C 34.980 2.040 +*N chany_bottom_in[0]:12 *C 82.333 2.040 +*N chany_bottom_in[0]:13 *C 82.340 1.983 + +*CAP +0 chany_bottom_in[0] 6.620004e-05 +1 mux_left_track_3\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[0]:2 6.958604e-05 +3 chany_bottom_in[0]:3 6.182987e-05 +4 chany_bottom_in[0]:4 6.182987e-05 +5 chany_bottom_in[0]:5 5.79839e-05 +6 chany_bottom_in[0]:6 6.236351e-05 +7 chany_bottom_in[0]:7 6.958604e-05 +8 chany_bottom_in[0]:8 0.00141812 +9 chany_bottom_in[0]:9 0.003394236 +10 chany_bottom_in[0]:10 0.001976116 +11 chany_bottom_in[0]:11 0.002727638 +12 chany_bottom_in[0]:12 0.002727638 +13 chany_bottom_in[0]:13 6.620004e-05 +14 chany_bottom_in[0]:8 chany_bottom_in[13]:26 0.0004738992 +15 chany_bottom_in[0]:8 chany_bottom_in[13]:32 3.980461e-05 +16 chany_bottom_in[0]:11 chany_bottom_in[13]:34 3.407435e-05 +17 chany_bottom_in[0]:10 chany_bottom_in[13]:33 0.0008842351 +18 chany_bottom_in[0]:12 chany_bottom_in[13]:35 3.407435e-05 +19 chany_bottom_in[0]:9 chany_bottom_in[13]:32 0.001358134 +20 chany_bottom_in[0]:9 chany_bottom_in[13]:33 3.980461e-05 +21 chany_bottom_in[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.916547e-05 +22 chany_bottom_in[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0001783391 +23 chany_bottom_in[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.205755e-05 +24 chany_bottom_in[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.916547e-05 +25 chany_bottom_in[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0001783391 +26 chany_bottom_in[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:8 2.205755e-05 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:13 0.0006183035 +1 chany_bottom_in[0]:3 mux_left_track_3\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.0004888393 +3 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.0045 +4 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.0001634615 +5 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.00341 +6 chany_bottom_in[0]:7 chany_bottom_in[0]:2 5.69697e-05 +7 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.00341 +8 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.00341 +9 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.007806308 +10 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.00341 +11 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.007418558 +12 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.004442675 + +*END + +*D_NET chany_bottom_in[3] 0.008283406 //LENGTH 71.720 LUMPCC 0.001814801 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 88.320 1.290 +*I mux_left_track_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 69.750 53.380 +*N chany_bottom_in[3]:2 *C 69.750 53.380 +*N chany_bottom_in[3]:3 *C 69.920 52.700 +*N chany_bottom_in[3]:4 *C 71.715 52.700 +*N chany_bottom_in[3]:5 *C 71.760 52.655 +*N chany_bottom_in[3]:6 *C 71.760 42.898 +*N chany_bottom_in[3]:7 *C 71.767 42.840 +*N chany_bottom_in[3]:8 *C 88.312 42.840 +*N chany_bottom_in[3]:9 *C 88.320 42.782 + +*CAP +0 chany_bottom_in[3] 0.001364644 +1 mux_left_track_7\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[3]:2 7.290597e-05 +3 chany_bottom_in[3]:3 0.0001656908 +4 chany_bottom_in[3]:4 0.0001219467 +5 chany_bottom_in[3]:5 0.000590326 +6 chany_bottom_in[3]:6 0.000590326 +7 chany_bottom_in[3]:7 0.001098561 +8 chany_bottom_in[3]:8 0.001098561 +9 chany_bottom_in[3]:9 0.001364644 +10 chany_bottom_in[3] chany_bottom_in[7] 0.0005764258 +11 chany_bottom_in[3]:9 chany_bottom_in[7]:6 0.0005764258 +12 chany_bottom_in[3] chany_bottom_in[11]:5 0.0002552302 +13 chany_bottom_in[3]:9 chany_bottom_in[11]:4 0.0002552302 +14 chany_bottom_in[3] ropt_net_147:3 7.574421e-05 +15 chany_bottom_in[3]:9 ropt_net_147:4 7.574421e-05 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:9 0.03704688 +1 chany_bottom_in[3]:2 mux_left_track_7\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.001602679 +3 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.0045 +4 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.008712054 +5 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.00341 +6 chany_bottom_in[3]:9 chany_bottom_in[3]:8 0.00341 +7 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.00259205 +8 chany_bottom_in[3]:3 chany_bottom_in[3]:2 0.0006071429 + +*END + +*D_NET chany_bottom_in[11] 0.005515203 //LENGTH 51.605 LUMPCC 0.001843725 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 86.480 1.290 +*I mux_left_track_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 88.150 47.940 +*N chany_bottom_in[11]:2 *C 88.188 47.940 +*N chany_bottom_in[11]:3 *C 89.195 47.940 +*N chany_bottom_in[11]:4 *C 89.240 47.895 +*N chany_bottom_in[11]:5 *C 89.240 25.205 +*N chany_bottom_in[11]:6 *C 89.195 25.160 +*N chany_bottom_in[11]:7 *C 86.525 25.160 +*N chany_bottom_in[11]:8 *C 86.480 25.115 + +*CAP +0 chany_bottom_in[11] 0.0009246735 +1 mux_left_track_11\/mux_l2_in_0_:A0 1e-06 +2 chany_bottom_in[11]:2 8.59314e-05 +3 chany_bottom_in[11]:3 8.59314e-05 +4 chany_bottom_in[11]:4 0.0006395435 +5 chany_bottom_in[11]:5 0.0006395435 +6 chany_bottom_in[11]:6 0.0001850906 +7 chany_bottom_in[11]:7 0.0001850906 +8 chany_bottom_in[11]:8 0.0009246735 +9 chany_bottom_in[11]:4 chany_top_in[9]:8 0.0003188227 +10 chany_bottom_in[11]:5 chany_top_in[9]:7 0.0003188227 +11 chany_bottom_in[11]:4 chany_bottom_in[3]:9 0.0002552302 +12 chany_bottom_in[11]:5 chany_bottom_in[3] 0.0002552302 +13 chany_bottom_in[11] chany_bottom_in[7] 0.0003261388 +14 chany_bottom_in[11]:4 chany_bottom_in[7]:6 2.167078e-05 +15 chany_bottom_in[11]:5 chany_bottom_in[7] 2.167078e-05 +16 chany_bottom_in[11]:8 chany_bottom_in[7]:6 0.0003261388 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:8 0.02127232 +1 chany_bottom_in[11]:2 mux_left_track_11\/mux_l2_in_0_:A0 0.152 +2 chany_bottom_in[11]:3 chany_bottom_in[11]:2 0.0008995536 +3 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.0045 +4 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.0045 +5 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.02025893 +6 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.002383929 +7 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.0045 + +*END + +*D_NET bottom_left_grid_pin_35_[0] 0.007663121 //LENGTH 47.310 LUMPCC 0.002787776 DR + +*CONN +*P bottom_left_grid_pin_35_[0] I *L 0.29796 *C 29.750 8.160 +*I mux_bottom_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 33.680 9.180 +*I mux_bottom_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 56.870 17.000 +*I mux_bottom_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 63.120 18.020 +*N bottom_left_grid_pin_35_[0]:4 *C 63.083 18.020 +*N bottom_left_grid_pin_35_[0]:5 *C 58.925 18.020 +*N bottom_left_grid_pin_35_[0]:6 *C 58.880 17.975 +*N bottom_left_grid_pin_35_[0]:7 *C 56.908 17.000 +*N bottom_left_grid_pin_35_[0]:8 *C 58.835 17.000 +*N bottom_left_grid_pin_35_[0]:9 *C 58.880 17.000 +*N bottom_left_grid_pin_35_[0]:10 *C 58.880 8.898 +*N bottom_left_grid_pin_35_[0]:11 *C 58.873 8.840 +*N bottom_left_grid_pin_35_[0]:12 *C 33.580 9.180 +*N bottom_left_grid_pin_35_[0]:13 *C 33.580 9.180 +*N bottom_left_grid_pin_35_[0]:14 *C 33.580 8.840 +*N bottom_left_grid_pin_35_[0]:15 *C 33.580 8.840 +*N bottom_left_grid_pin_35_[0]:16 *C 33.580 8.160 + +*CAP +0 bottom_left_grid_pin_35_[0] 0.0002870297 +1 mux_bottom_track_5\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:A1 1e-06 +4 bottom_left_grid_pin_35_[0]:4 0.0002196734 +5 bottom_left_grid_pin_35_[0]:5 0.0002196734 +6 bottom_left_grid_pin_35_[0]:6 6.273125e-05 +7 bottom_left_grid_pin_35_[0]:7 0.0001392313 +8 bottom_left_grid_pin_35_[0]:8 0.0001392313 +9 bottom_left_grid_pin_35_[0]:9 0.0005017089 +10 bottom_left_grid_pin_35_[0]:10 0.0004075446 +11 bottom_left_grid_pin_35_[0]:11 0.001171379 +12 bottom_left_grid_pin_35_[0]:12 3.089842e-05 +13 bottom_left_grid_pin_35_[0]:13 5.28106e-05 +14 bottom_left_grid_pin_35_[0]:14 5.65252e-05 +15 bottom_left_grid_pin_35_[0]:15 0.001234128 +16 bottom_left_grid_pin_35_[0]:16 0.0003497787 +17 bottom_left_grid_pin_35_[0]:11 chany_top_in[4]:8 0.0006206161 +18 bottom_left_grid_pin_35_[0]:15 chany_top_in[4]:9 0.0006206161 +19 bottom_left_grid_pin_35_[0]:11 chany_bottom_in[13]:35 0.000450316 +20 bottom_left_grid_pin_35_[0]:15 chany_bottom_in[13]:34 0.000450316 +21 bottom_left_grid_pin_35_[0]:5 bottom_right_grid_pin_1_[0]:11 3.493429e-05 +22 bottom_left_grid_pin_35_[0]:5 bottom_right_grid_pin_1_[0]:15 4.13069e-05 +23 bottom_left_grid_pin_35_[0]:6 bottom_right_grid_pin_1_[0]:16 2.21362e-05 +24 bottom_left_grid_pin_35_[0]:4 bottom_right_grid_pin_1_[0]:10 3.493429e-05 +25 bottom_left_grid_pin_35_[0]:4 bottom_right_grid_pin_1_[0]:12 4.13069e-05 +26 bottom_left_grid_pin_35_[0]:10 bottom_right_grid_pin_1_[0]:17 0.0002070567 +27 bottom_left_grid_pin_35_[0]:8 bottom_right_grid_pin_1_[0]:12 3.819919e-06 +28 bottom_left_grid_pin_35_[0]:8 bottom_right_grid_pin_1_[0]:14 1.37019e-05 +29 bottom_left_grid_pin_35_[0]:9 bottom_right_grid_pin_1_[0]:16 0.0002070567 +30 bottom_left_grid_pin_35_[0]:9 bottom_right_grid_pin_1_[0]:17 2.21362e-05 +31 bottom_left_grid_pin_35_[0]:7 bottom_right_grid_pin_1_[0]:13 1.37019e-05 +32 bottom_left_grid_pin_35_[0]:7 bottom_right_grid_pin_1_[0]:15 3.819919e-06 + +*RES +0 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_35_[0]:16 0.0006000333 +1 bottom_left_grid_pin_35_[0]:5 bottom_left_grid_pin_35_[0]:4 0.003712054 +2 bottom_left_grid_pin_35_[0]:6 bottom_left_grid_pin_35_[0]:5 0.0045 +3 bottom_left_grid_pin_35_[0]:4 mux_bottom_track_25\/mux_l1_in_1_:A1 0.152 +4 bottom_left_grid_pin_35_[0]:10 bottom_left_grid_pin_35_[0]:9 0.007234375 +5 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_35_[0]:10 0.00341 +6 bottom_left_grid_pin_35_[0]:14 bottom_left_grid_pin_35_[0]:13 0.0001057692 +7 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:14 0.00341 +8 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:11 0.003962492 +9 bottom_left_grid_pin_35_[0]:12 mux_bottom_track_5\/mux_l1_in_2_:A1 0.152 +10 bottom_left_grid_pin_35_[0]:13 bottom_left_grid_pin_35_[0]:12 0.0045 +11 bottom_left_grid_pin_35_[0]:8 bottom_left_grid_pin_35_[0]:7 0.001720982 +12 bottom_left_grid_pin_35_[0]:9 bottom_left_grid_pin_35_[0]:8 0.0045 +13 bottom_left_grid_pin_35_[0]:9 bottom_left_grid_pin_35_[0]:6 0.0008705357 +14 bottom_left_grid_pin_35_[0]:7 mux_bottom_track_1\/mux_l1_in_1_:A0 0.152 +15 bottom_left_grid_pin_35_[0]:16 bottom_left_grid_pin_35_[0]:15 0.0001065333 + +*END + +*D_NET bottom_left_grid_pin_39_[0] 0.005737525 //LENGTH 43.235 LUMPCC 0.0001366361 DR + +*CONN +*P bottom_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 11.560 +*I mux_bottom_track_5\/mux_l1_in_4_:A1 I *L 0.00198 *C 34.140 14.620 +*I mux_bottom_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 56.410 15.300 +*I mux_bottom_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 62.735 17.000 +*N bottom_left_grid_pin_39_[0]:4 *C 62.698 17.000 +*N bottom_left_grid_pin_39_[0]:5 *C 62.145 17.000 +*N bottom_left_grid_pin_39_[0]:6 *C 62.100 16.955 +*N bottom_left_grid_pin_39_[0]:7 *C 62.100 15.345 +*N bottom_left_grid_pin_39_[0]:8 *C 62.055 15.300 +*N bottom_left_grid_pin_39_[0]:9 *C 56.410 15.300 +*N bottom_left_grid_pin_39_[0]:10 *C 47.425 15.300 +*N bottom_left_grid_pin_39_[0]:11 *C 47.380 15.255 +*N bottom_left_grid_pin_39_[0]:12 *C 47.380 12.298 +*N bottom_left_grid_pin_39_[0]:13 *C 47.373 12.240 +*N bottom_left_grid_pin_39_[0]:14 *C 34.040 14.620 +*N bottom_left_grid_pin_39_[0]:15 *C 34.040 14.575 +*N bottom_left_grid_pin_39_[0]:16 *C 34.040 12.298 +*N bottom_left_grid_pin_39_[0]:17 *C 34.040 12.240 +*N bottom_left_grid_pin_39_[0]:18 *C 34.040 11.560 + +*CAP +0 bottom_left_grid_pin_39_[0] 0.0003272581 +1 mux_bottom_track_5\/mux_l1_in_4_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:A0 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:A0 1e-06 +4 bottom_left_grid_pin_39_[0]:4 7.36864e-05 +5 bottom_left_grid_pin_39_[0]:5 7.36864e-05 +6 bottom_left_grid_pin_39_[0]:6 0.000110107 +7 bottom_left_grid_pin_39_[0]:7 0.000110107 +8 bottom_left_grid_pin_39_[0]:8 0.0003873399 +9 bottom_left_grid_pin_39_[0]:9 0.0009417153 +10 bottom_left_grid_pin_39_[0]:10 0.0005262196 +11 bottom_left_grid_pin_39_[0]:11 0.0001944497 +12 bottom_left_grid_pin_39_[0]:12 0.0001944497 +13 bottom_left_grid_pin_39_[0]:13 0.00091911 +14 bottom_left_grid_pin_39_[0]:14 3.369926e-05 +15 bottom_left_grid_pin_39_[0]:15 0.0001600413 +16 bottom_left_grid_pin_39_[0]:16 0.0001600413 +17 bottom_left_grid_pin_39_[0]:17 0.0009889146 +18 bottom_left_grid_pin_39_[0]:18 0.0003970628 +19 bottom_left_grid_pin_39_[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.831807e-05 +20 bottom_left_grid_pin_39_[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.831807e-05 + +*RES +0 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_39_[0]:18 0.0006721 +1 bottom_left_grid_pin_39_[0]:8 bottom_left_grid_pin_39_[0]:7 0.0045 +2 bottom_left_grid_pin_39_[0]:7 bottom_left_grid_pin_39_[0]:6 0.0014375 +3 bottom_left_grid_pin_39_[0]:5 bottom_left_grid_pin_39_[0]:4 0.0004933036 +4 bottom_left_grid_pin_39_[0]:6 bottom_left_grid_pin_39_[0]:5 0.0045 +5 bottom_left_grid_pin_39_[0]:4 mux_bottom_track_25\/mux_l1_in_1_:A0 0.152 +6 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_39_[0]:11 0.002640625 +7 bottom_left_grid_pin_39_[0]:13 bottom_left_grid_pin_39_[0]:12 0.00341 +8 bottom_left_grid_pin_39_[0]:10 bottom_left_grid_pin_39_[0]:9 0.008022322 +9 bottom_left_grid_pin_39_[0]:11 bottom_left_grid_pin_39_[0]:10 0.0045 +10 bottom_left_grid_pin_39_[0]:16 bottom_left_grid_pin_39_[0]:15 0.002033482 +11 bottom_left_grid_pin_39_[0]:17 bottom_left_grid_pin_39_[0]:16 0.00341 +12 bottom_left_grid_pin_39_[0]:17 bottom_left_grid_pin_39_[0]:13 0.002088758 +13 bottom_left_grid_pin_39_[0]:14 mux_bottom_track_5\/mux_l1_in_4_:A1 0.152 +14 bottom_left_grid_pin_39_[0]:15 bottom_left_grid_pin_39_[0]:14 0.0045 +15 bottom_left_grid_pin_39_[0]:9 mux_bottom_track_1\/mux_l1_in_2_:A0 0.152 +16 bottom_left_grid_pin_39_[0]:9 bottom_left_grid_pin_39_[0]:8 0.005040179 +17 bottom_left_grid_pin_39_[0]:18 bottom_left_grid_pin_39_[0]:17 0.0001065333 + +*END + +*D_NET chanx_left_in[3] 0.01053736 //LENGTH 69.270 LUMPCC 0.004854151 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 39.440 +*I mux_bottom_track_5\/mux_l1_in_5_:A0 I *L 0.001631 *C 33.755 26.180 +*I mux_top_track_16\/mux_l1_in_2_:A1 I *L 0.00198 *C 37.820 56.100 +*N chanx_left_in[3]:3 *C 37.782 56.100 +*N chanx_left_in[3]:4 *C 35.465 56.100 +*N chanx_left_in[3]:5 *C 35.420 56.055 +*N chanx_left_in[3]:6 *C 33.793 26.180 +*N chanx_left_in[3]:7 *C 35.375 26.180 +*N chanx_left_in[3]:8 *C 35.420 26.225 +*N chanx_left_in[3]:9 *C 35.420 39.440 +*N chanx_left_in[3]:10 *C 35.413 39.440 + +*CAP +0 chanx_left_in[3] 0.001166484 +1 mux_bottom_track_5\/mux_l1_in_5_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_2_:A1 1e-06 +3 chanx_left_in[3]:3 0.0001819096 +4 chanx_left_in[3]:4 0.0001819096 +5 chanx_left_in[3]:5 0.0006865168 +6 chanx_left_in[3]:6 0.0001147648 +7 chanx_left_in[3]:7 0.0001147648 +8 chanx_left_in[3]:8 0.0006717459 +9 chanx_left_in[3]:9 0.001396625 +10 chanx_left_in[3]:10 0.001166484 +11 chanx_left_in[3]:8 chanx_left_in[6]:9 6.625355e-06 +12 chanx_left_in[3]:8 chanx_left_in[6]:8 0.0001237246 +13 chanx_left_in[3]:9 chanx_left_in[6]:5 0.0001237246 +14 chanx_left_in[3]:9 chanx_left_in[6]:8 0.0004372349 +15 chanx_left_in[3]:5 chanx_left_in[6]:5 0.0004306096 +16 chanx_left_in[3] chanx_left_in[8]:13 0.001019015 +17 chanx_left_in[3] chanx_left_in[8]:17 1.617257e-07 +18 chanx_left_in[3]:10 chanx_left_in[8]:12 0.001019015 +19 chanx_left_in[3]:10 chanx_left_in[8]:16 1.617257e-07 +20 chanx_left_in[3] chanx_left_in[11] 0.0002409872 +21 chanx_left_in[3] chanx_left_in[11]:20 0.000442068 +22 chanx_left_in[3]:10 chanx_left_in[11]:19 0.000442068 +23 chanx_left_in[3]:10 chanx_left_in[11]:23 0.0002409872 +24 chanx_left_in[3]:8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 7.123046e-05 +25 chanx_left_in[3]:9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 7.123046e-05 +26 chanx_left_in[3] ropt_net_204:5 9.265373e-05 +27 chanx_left_in[3]:10 ropt_net_204:6 9.265373e-05 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:10 0.005355258 +1 chanx_left_in[3]:7 chanx_left_in[3]:6 0.001412946 +2 chanx_left_in[3]:8 chanx_left_in[3]:7 0.0045 +3 chanx_left_in[3]:6 mux_bottom_track_5\/mux_l1_in_5_:A0 0.152 +4 chanx_left_in[3]:9 chanx_left_in[3]:8 0.01179911 +5 chanx_left_in[3]:9 chanx_left_in[3]:5 0.01483482 +6 chanx_left_in[3]:10 chanx_left_in[3]:9 0.00341 +7 chanx_left_in[3]:4 chanx_left_in[3]:3 0.002069197 +8 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0045 +9 chanx_left_in[3]:3 mux_top_track_16\/mux_l1_in_2_:A1 0.152 + +*END + +*D_NET chanx_left_in[7] 0.008575725 //LENGTH 62.260 LUMPCC 0.0008431326 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.230 42.160 +*I mux_top_track_0\/mux_l2_in_2_:A0 I *L 0.001631 *C 10.755 88.060 +*I mux_bottom_track_33\/mux_l1_in_2_:A1 I *L 0.00198 *C 9.200 41.820 +*N chanx_left_in[7]:3 *C 9.162 41.820 +*N chanx_left_in[7]:4 *C 7.820 41.820 +*N chanx_left_in[7]:5 *C 7.820 42.160 +*N chanx_left_in[7]:6 *C 6.025 42.160 +*N chanx_left_in[7]:7 *C 5.980 42.160 +*N chanx_left_in[7]:8 *C 5.973 42.160 +*N chanx_left_in[7]:9 *C 10.755 88.060 +*N chanx_left_in[7]:10 *C 10.580 88.060 +*N chanx_left_in[7]:11 *C 10.580 88.015 +*N chanx_left_in[7]:12 *C 10.580 85.737 +*N chanx_left_in[7]:13 *C 10.572 85.680 +*N chanx_left_in[7]:14 *C 4.620 85.680 +*N chanx_left_in[7]:15 *C 4.600 85.672 +*N chanx_left_in[7]:16 *C 4.600 42.168 +*N chanx_left_in[7]:17 *C 4.600 42.160 + +*CAP +0 chanx_left_in[7] 0.0001926229 +1 mux_top_track_0\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_2_:A1 1e-06 +3 chanx_left_in[7]:3 0.0001028055 +4 chanx_left_in[7]:4 0.000133356 +5 chanx_left_in[7]:5 0.0001432532 +6 chanx_left_in[7]:6 0.0001127027 +7 chanx_left_in[7]:7 3.755508e-05 +8 chanx_left_in[7]:8 0.0001540733 +9 chanx_left_in[7]:9 4.763047e-05 +10 chanx_left_in[7]:10 5.085988e-05 +11 chanx_left_in[7]:11 0.0001621105 +12 chanx_left_in[7]:12 0.0001621105 +13 chanx_left_in[7]:13 0.00030647 +14 chanx_left_in[7]:14 0.00030647 +15 chanx_left_in[7]:15 0.002735939 +16 chanx_left_in[7]:16 0.002735939 +17 chanx_left_in[7]:17 0.0003466962 +18 chanx_left_in[7]:14 chanx_left_in[4]:12 0.0003362191 +19 chanx_left_in[7]:13 chanx_left_in[4]:11 0.0003362191 +20 chanx_left_in[7] ropt_net_204:5 3.625357e-05 +21 chanx_left_in[7]:6 ropt_net_204:10 4.558978e-05 +22 chanx_left_in[7]:8 ropt_net_204:6 3.50386e-06 +23 chanx_left_in[7]:17 ropt_net_204:5 3.50386e-06 +24 chanx_left_in[7]:17 ropt_net_204:6 3.625357e-05 +25 chanx_left_in[7]:5 ropt_net_204:9 4.558978e-05 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:17 0.0005279667 +1 chanx_left_in[7]:3 mux_bottom_track_33\/mux_l1_in_2_:A1 0.152 +2 chanx_left_in[7]:6 chanx_left_in[7]:5 0.001602679 +3 chanx_left_in[7]:7 chanx_left_in[7]:6 0.0045 +4 chanx_left_in[7]:8 chanx_left_in[7]:7 0.00341 +5 chanx_left_in[7]:17 chanx_left_in[7]:16 0.00341 +6 chanx_left_in[7]:17 chanx_left_in[7]:8 0.000215025 +7 chanx_left_in[7]:16 chanx_left_in[7]:15 0.006815783 +8 chanx_left_in[7]:14 chanx_left_in[7]:13 0.0009325583 +9 chanx_left_in[7]:15 chanx_left_in[7]:14 0.00341 +10 chanx_left_in[7]:12 chanx_left_in[7]:11 0.002033482 +11 chanx_left_in[7]:13 chanx_left_in[7]:12 0.00341 +12 chanx_left_in[7]:10 chanx_left_in[7]:9 9.51087e-05 +13 chanx_left_in[7]:11 chanx_left_in[7]:10 0.0045 +14 chanx_left_in[7]:9 mux_top_track_0\/mux_l2_in_2_:A0 0.152 +15 chanx_left_in[7]:5 chanx_left_in[7]:4 0.0003035715 +16 chanx_left_in[7]:4 chanx_left_in[7]:3 0.001198661 + +*END + +*D_NET chanx_left_in[13] 0.01430194 //LENGTH 100.295 LUMPCC 0.003936333 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 93.840 +*I mux_bottom_track_25\/mux_l1_in_2_:A0 I *L 0.001631 *C 36.975 33.660 +*I mux_top_track_2\/mux_l2_in_3_:A1 I *L 0.00198 *C 30.360 90.780 +*N chanx_left_in[13]:3 *C 30.360 90.780 +*N chanx_left_in[13]:4 *C 30.360 90.780 +*N chanx_left_in[13]:5 *C 30.360 90.440 +*N chanx_left_in[13]:6 *C 30.353 90.440 +*N chanx_left_in[13]:7 *C 36.938 33.660 +*N chanx_left_in[13]:8 *C 36.385 33.660 +*N chanx_left_in[13]:9 *C 36.340 33.705 +*N chanx_left_in[13]:10 *C 36.340 40.742 +*N chanx_left_in[13]:11 *C 36.333 40.800 +*N chanx_left_in[13]:12 *C 28.540 40.800 +*N chanx_left_in[13]:13 *C 28.520 40.808 +*N chanx_left_in[13]:14 *C 28.520 90.433 +*N chanx_left_in[13]:15 *C 28.520 90.440 +*N chanx_left_in[13]:16 *C 4.620 90.440 +*N chanx_left_in[13]:17 *C 4.600 90.448 +*N chanx_left_in[13]:18 *C 4.600 93.833 +*N chanx_left_in[13]:19 *C 4.580 93.840 + +*CAP +0 chanx_left_in[13] 0.0002658775 +1 mux_bottom_track_25\/mux_l1_in_2_:A0 1e-06 +2 mux_top_track_2\/mux_l2_in_3_:A1 1e-06 +3 chanx_left_in[13]:3 3.384237e-05 +4 chanx_left_in[13]:4 5.440555e-05 +5 chanx_left_in[13]:5 5.842627e-05 +6 chanx_left_in[13]:6 0.0001132879 +7 chanx_left_in[13]:7 6.010553e-05 +8 chanx_left_in[13]:8 6.010553e-05 +9 chanx_left_in[13]:9 0.000405732 +10 chanx_left_in[13]:10 0.000405732 +11 chanx_left_in[13]:11 0.0003756599 +12 chanx_left_in[13]:12 0.0003756599 +13 chanx_left_in[13]:13 0.002412441 +14 chanx_left_in[13]:14 0.002412441 +15 chanx_left_in[13]:15 0.001324785 +16 chanx_left_in[13]:16 0.001211497 +17 chanx_left_in[13]:17 0.0002638673 +18 chanx_left_in[13]:18 0.0002638673 +19 chanx_left_in[13]:19 0.0002658775 +20 chanx_left_in[13]:12 chanx_left_in[8]:13 0.0004401316 +21 chanx_left_in[13]:11 chanx_left_in[8]:12 0.0004401316 +22 chanx_left_in[13]:14 chanx_left_in[16]:8 0.0004381649 +23 chanx_left_in[13]:13 chanx_left_in[16]:9 0.0004381649 +24 chanx_left_in[13]:6 left_top_grid_pin_42_[0]:31 1.260434e-07 +25 chanx_left_in[13]:6 left_top_grid_pin_42_[0]:5 1.436381e-05 +26 chanx_left_in[13]:16 left_top_grid_pin_42_[0]:32 6.410633e-05 +27 chanx_left_in[13]:15 left_top_grid_pin_42_[0]:23 1.436381e-05 +28 chanx_left_in[13]:15 left_top_grid_pin_42_[0]:31 6.410633e-05 +29 chanx_left_in[13]:15 left_top_grid_pin_42_[0]:32 1.260434e-07 +30 chanx_left_in[13]:14 left_top_grid_pin_42_[0]:22 0.0003117392 +31 chanx_left_in[13]:13 left_top_grid_pin_42_[0]:21 0.0003117392 +32 chanx_left_in[13] left_top_grid_pin_44_[0]:23 5.456313e-07 +33 chanx_left_in[13]:16 left_top_grid_pin_44_[0]:22 0.0001384621 +34 chanx_left_in[13]:16 left_top_grid_pin_44_[0]:23 0.0004798095 +35 chanx_left_in[13]:19 left_top_grid_pin_44_[0]:22 5.456313e-07 +36 chanx_left_in[13]:15 left_top_grid_pin_44_[0]:17 0.0001384621 +37 chanx_left_in[13]:15 left_top_grid_pin_44_[0]:22 0.0004798095 +38 chanx_left_in[13]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.071751e-05 +39 chanx_left_in[13]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.071751e-05 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:19 0.0005248333 +1 chanx_left_in[13]:3 mux_top_track_2\/mux_l2_in_3_:A1 0.152 +2 chanx_left_in[13]:4 chanx_left_in[13]:3 0.0045 +3 chanx_left_in[13]:5 chanx_left_in[13]:4 0.0001634615 +4 chanx_left_in[13]:6 chanx_left_in[13]:5 0.00341 +5 chanx_left_in[13]:16 chanx_left_in[13]:15 0.003744333 +6 chanx_left_in[13]:17 chanx_left_in[13]:16 0.00341 +7 chanx_left_in[13]:19 chanx_left_in[13]:18 0.00341 +8 chanx_left_in[13]:18 chanx_left_in[13]:17 0.0005303166 +9 chanx_left_in[13]:15 chanx_left_in[13]:14 0.00341 +10 chanx_left_in[13]:15 chanx_left_in[13]:6 0.0002870917 +11 chanx_left_in[13]:14 chanx_left_in[13]:13 0.007774583 +12 chanx_left_in[13]:12 chanx_left_in[13]:11 0.001220825 +13 chanx_left_in[13]:13 chanx_left_in[13]:12 0.00341 +14 chanx_left_in[13]:10 chanx_left_in[13]:9 0.006283483 +15 chanx_left_in[13]:11 chanx_left_in[13]:10 0.00341 +16 chanx_left_in[13]:8 chanx_left_in[13]:7 0.0004933036 +17 chanx_left_in[13]:9 chanx_left_in[13]:8 0.0045 +18 chanx_left_in[13]:7 mux_bottom_track_25\/mux_l1_in_2_:A0 0.152 + +*END + +*D_NET left_top_grid_pin_45_[0] 0.01049163 //LENGTH 78.095 LUMPCC 0.001541738 DR + +*CONN +*P left_top_grid_pin_45_[0] I *L 0.29796 *C 5.060 102.070 +*I mux_left_track_15\/mux_l2_in_1_:A1 I *L 0.00198 *C 14.260 61.540 +*I mux_left_track_7\/mux_l1_in_2_:A1 I *L 0.00198 *C 23.920 63.580 +*I mux_left_track_3\/mux_l1_in_2_:A1 I *L 0.00198 *C 19.320 85.340 +*N left_top_grid_pin_45_[0]:4 *C 19.320 85.325 +*N left_top_grid_pin_45_[0]:5 *C 19.530 82.280 +*N left_top_grid_pin_45_[0]:6 *C 23.883 63.580 +*N left_top_grid_pin_45_[0]:7 *C 22.125 63.580 +*N left_top_grid_pin_45_[0]:8 *C 22.080 63.535 +*N left_top_grid_pin_45_[0]:9 *C 22.080 61.938 +*N left_top_grid_pin_45_[0]:10 *C 22.073 61.880 +*N left_top_grid_pin_45_[0]:11 *C 14.298 61.540 +*N left_top_grid_pin_45_[0]:12 *C 15.135 61.540 +*N left_top_grid_pin_45_[0]:13 *C 15.180 61.540 +*N left_top_grid_pin_45_[0]:14 *C 15.180 61.880 +*N left_top_grid_pin_45_[0]:15 *C 15.188 61.880 +*N left_top_grid_pin_45_[0]:16 *C 20.240 61.880 +*N left_top_grid_pin_45_[0]:17 *C 20.240 61.888 +*N left_top_grid_pin_45_[0]:18 *C 20.240 82.273 +*N left_top_grid_pin_45_[0]:19 *C 20.238 82.280 +*N left_top_grid_pin_45_[0]:20 *C 20.240 82.338 +*N left_top_grid_pin_45_[0]:21 *C 20.240 84.955 +*N left_top_grid_pin_45_[0]:22 *C 20.195 85.000 +*N left_top_grid_pin_45_[0]:23 *C 19.320 85.000 +*N left_top_grid_pin_45_[0]:24 *C 1.885 85.000 +*N left_top_grid_pin_45_[0]:25 *C 1.840 85.045 +*N left_top_grid_pin_45_[0]:26 *C 1.840 88.060 +*N left_top_grid_pin_45_[0]:27 *C 1.840 88.060 +*N left_top_grid_pin_45_[0]:28 *C 5.015 88.060 +*N left_top_grid_pin_45_[0]:29 *C 5.060 88.105 + +*CAP +0 left_top_grid_pin_45_[0] 0.0007766996 +1 mux_left_track_15\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_7\/mux_l1_in_2_:A1 1e-06 +3 mux_left_track_3\/mux_l1_in_2_:A1 1e-06 +4 left_top_grid_pin_45_[0]:4 3.532129e-05 +5 left_top_grid_pin_45_[0]:5 0.0001621699 +6 left_top_grid_pin_45_[0]:6 0.0001405147 +7 left_top_grid_pin_45_[0]:7 0.0001405147 +8 left_top_grid_pin_45_[0]:8 0.0001150757 +9 left_top_grid_pin_45_[0]:9 0.0001150757 +10 left_top_grid_pin_45_[0]:10 4.212907e-05 +11 left_top_grid_pin_45_[0]:11 7.262906e-05 +12 left_top_grid_pin_45_[0]:12 7.262906e-05 +13 left_top_grid_pin_45_[0]:13 5.428789e-05 +14 left_top_grid_pin_45_[0]:14 5.843658e-05 +15 left_top_grid_pin_45_[0]:15 0.000117558 +16 left_top_grid_pin_45_[0]:16 0.0001596871 +17 left_top_grid_pin_45_[0]:17 0.001084048 +18 left_top_grid_pin_45_[0]:18 0.001084048 +19 left_top_grid_pin_45_[0]:19 0.0001621699 +20 left_top_grid_pin_45_[0]:20 0.0001772731 +21 left_top_grid_pin_45_[0]:21 0.0001772731 +22 left_top_grid_pin_45_[0]:22 8.864728e-05 +23 left_top_grid_pin_45_[0]:23 0.001294148 +24 left_top_grid_pin_45_[0]:24 0.001170179 +25 left_top_grid_pin_45_[0]:25 0.0001810335 +26 left_top_grid_pin_45_[0]:26 0.0002161381 +27 left_top_grid_pin_45_[0]:27 0.0002552689 +28 left_top_grid_pin_45_[0]:28 0.0002172367 +29 left_top_grid_pin_45_[0]:29 0.0007766996 +30 left_top_grid_pin_45_[0]:10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001119846 +31 left_top_grid_pin_45_[0]:16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001119846 +32 left_top_grid_pin_45_[0]:16 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002903338 +33 left_top_grid_pin_45_[0]:15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002903338 +34 left_top_grid_pin_45_[0]:10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 4.648681e-05 +35 left_top_grid_pin_45_[0]:16 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.000119023 +36 left_top_grid_pin_45_[0]:16 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 4.648681e-05 +37 left_top_grid_pin_45_[0]:17 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0002030408 +38 left_top_grid_pin_45_[0]:18 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0002030408 +39 left_top_grid_pin_45_[0]:15 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.000119023 + +*RES +0 left_top_grid_pin_45_[0] left_top_grid_pin_45_[0]:29 0.01246875 +1 left_top_grid_pin_45_[0]:6 mux_left_track_7\/mux_l1_in_2_:A1 0.152 +2 left_top_grid_pin_45_[0]:7 left_top_grid_pin_45_[0]:6 0.001569197 +3 left_top_grid_pin_45_[0]:8 left_top_grid_pin_45_[0]:7 0.0045 +4 left_top_grid_pin_45_[0]:9 left_top_grid_pin_45_[0]:8 0.001426339 +5 left_top_grid_pin_45_[0]:10 left_top_grid_pin_45_[0]:9 0.00341 +6 left_top_grid_pin_45_[0]:24 left_top_grid_pin_45_[0]:23 0.01556696 +7 left_top_grid_pin_45_[0]:25 left_top_grid_pin_45_[0]:24 0.0045 +8 left_top_grid_pin_45_[0]:27 left_top_grid_pin_45_[0]:26 0.0045 +9 left_top_grid_pin_45_[0]:26 left_top_grid_pin_45_[0]:25 0.002691964 +10 left_top_grid_pin_45_[0]:28 left_top_grid_pin_45_[0]:27 0.002834822 +11 left_top_grid_pin_45_[0]:29 left_top_grid_pin_45_[0]:28 0.0045 +12 left_top_grid_pin_45_[0]:16 left_top_grid_pin_45_[0]:15 0.0007915583 +13 left_top_grid_pin_45_[0]:16 left_top_grid_pin_45_[0]:10 0.0002870917 +14 left_top_grid_pin_45_[0]:17 left_top_grid_pin_45_[0]:16 0.00341 +15 left_top_grid_pin_45_[0]:19 left_top_grid_pin_45_[0]:18 0.00341 +16 left_top_grid_pin_45_[0]:19 left_top_grid_pin_45_[0]:5 0.0001039141 +17 left_top_grid_pin_45_[0]:18 left_top_grid_pin_45_[0]:17 0.00319365 +18 left_top_grid_pin_45_[0]:20 left_top_grid_pin_45_[0]:19 0.00341 +19 left_top_grid_pin_45_[0]:22 left_top_grid_pin_45_[0]:21 0.0045 +20 left_top_grid_pin_45_[0]:21 left_top_grid_pin_45_[0]:20 0.002337054 +21 left_top_grid_pin_45_[0]:4 mux_left_track_3\/mux_l1_in_2_:A1 0.152 +22 left_top_grid_pin_45_[0]:11 mux_left_track_15\/mux_l2_in_1_:A1 0.152 +23 left_top_grid_pin_45_[0]:12 left_top_grid_pin_45_[0]:11 0.0007477679 +24 left_top_grid_pin_45_[0]:13 left_top_grid_pin_45_[0]:12 0.0045 +25 left_top_grid_pin_45_[0]:14 left_top_grid_pin_45_[0]:13 0.0001634616 +26 left_top_grid_pin_45_[0]:15 left_top_grid_pin_45_[0]:14 0.00341 +27 left_top_grid_pin_45_[0]:23 left_top_grid_pin_45_[0]:22 0.00078125 +28 left_top_grid_pin_45_[0]:23 left_top_grid_pin_45_[0]:4 0.0001766305 + +*END + +*D_NET ropt_net_147 0.0005615551 //LENGTH 4.265 LUMPCC 0.0001514884 DR + +*CONN +*I mux_bottom_track_1\/BUFT_P_113:X O *L 0 *C 87.860 6.800 +*I ropt_mt_inst_772:A I *L 0.001766 *C 88.780 4.080 +*N ropt_net_147:2 *C 88.780 4.080 +*N ropt_net_147:3 *C 88.780 4.125 +*N ropt_net_147:4 *C 88.780 6.755 +*N ropt_net_147:5 *C 88.735 6.800 +*N ropt_net_147:6 *C 87.898 6.800 + +*CAP +0 mux_bottom_track_1\/BUFT_P_113:X 1e-06 +1 ropt_mt_inst_772:A 1e-06 +2 ropt_net_147:2 3.431975e-05 +3 ropt_net_147:3 0.0001124522 +4 ropt_net_147:4 0.0001124522 +5 ropt_net_147:5 7.442127e-05 +6 ropt_net_147:6 7.442127e-05 +7 ropt_net_147:3 chany_bottom_in[3] 7.574421e-05 +8 ropt_net_147:4 chany_bottom_in[3]:9 7.574421e-05 + +*RES +0 mux_bottom_track_1\/BUFT_P_113:X ropt_net_147:6 0.152 +1 ropt_net_147:2 ropt_mt_inst_772:A 0.152 +2 ropt_net_147:3 ropt_net_147:2 0.0045 +3 ropt_net_147:5 ropt_net_147:4 0.0045 +4 ropt_net_147:4 ropt_net_147:3 0.002348214 +5 ropt_net_147:6 ropt_net_147:5 0.000747768 + +*END + +*D_NET chany_bottom_out[16] 0.002840425 //LENGTH 23.335 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 44.620 4.080 +*P chany_bottom_out[16] O *L 0.7423 *C 64.400 1.325 +*N chany_bottom_out[16]:2 *C 64.400 1.995 +*N chany_bottom_out[16]:3 *C 64.355 2.040 +*N chany_bottom_out[16]:4 *C 44.665 2.040 +*N chany_bottom_out[16]:5 *C 44.620 2.085 +*N chany_bottom_out[16]:6 *C 44.620 4.035 +*N chany_bottom_out[16]:7 *C 44.620 4.080 + +*CAP +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[16] 5.448816e-05 +2 chany_bottom_out[16]:2 5.448816e-05 +3 chany_bottom_out[16]:3 0.00123188 +4 chany_bottom_out[16]:4 0.00123188 +5 chany_bottom_out[16]:5 0.0001183651 +6 chany_bottom_out[16]:6 0.0001183651 +7 chany_bottom_out[16]:7 2.995797e-05 + +*RES +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[16]:7 0.152 +1 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0045 +2 chany_bottom_out[16]:2 chany_bottom_out[16] 0.0005982142 +3 chany_bottom_out[16]:4 chany_bottom_out[16]:3 0.01758036 +4 chany_bottom_out[16]:5 chany_bottom_out[16]:4 0.0045 +5 chany_bottom_out[16]:7 chany_bottom_out[16]:6 0.0045 +6 chany_bottom_out[16]:6 chany_bottom_out[16]:5 0.001741072 + +*END + +*D_NET chanx_left_out[7] 0.001080047 //LENGTH 8.870 LUMPCC 9.287927e-05 DR + +*CONN +*I mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.600 61.200 +*P chanx_left_out[7] O *L 0.7423 *C 1.305 65.960 +*N chanx_left_out[7]:2 *C 3.673 65.960 +*N chanx_left_out[7]:3 *C 3.680 65.903 +*N chanx_left_out[7]:4 *C 3.680 61.245 +*N chanx_left_out[7]:5 *C 3.725 61.200 +*N chanx_left_out[7]:6 *C 4.562 61.200 + +*CAP +0 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[7] 0.0001652983 +2 chanx_left_out[7]:2 0.0001652983 +3 chanx_left_out[7]:3 0.0002603381 +4 chanx_left_out[7]:4 0.0002603381 +5 chanx_left_out[7]:5 6.744725e-05 +6 chanx_left_out[7]:6 6.744725e-05 +7 chanx_left_out[7]:3 ropt_net_164:4 4.643963e-05 +8 chanx_left_out[7]:4 ropt_net_164:5 4.643963e-05 + +*RES +0 mux_left_track_15\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[7]:6 0.152 +1 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +2 chanx_left_out[7]:2 chanx_left_out[7] 0.0003709083 +3 chanx_left_out[7]:5 chanx_left_out[7]:4 0.0045 +4 chanx_left_out[7]:4 chanx_left_out[7]:3 0.004158482 +5 chanx_left_out[7]:6 chanx_left_out[7]:5 0.0007477679 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[3] 0.001296058 //LENGTH 9.270 LUMPCC 0.0004019232 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 38.320 121.720 +*I mem_top_track_0\/FTB_1__33:A I *L 0.001746 *C 34.960 126.480 +*I mux_top_track_0\/mux_l4_in_0_:S I *L 0.00357 *C 38.540 126.480 +*N mux_tree_tapbuf_size10_0_sram[3]:3 *C 38.525 126.480 +*N mux_tree_tapbuf_size10_0_sram[3]:4 *C 34.998 126.480 +*N mux_tree_tapbuf_size10_0_sram[3]:5 *C 38.203 126.480 +*N mux_tree_tapbuf_size10_0_sram[3]:6 *C 38.180 126.435 +*N mux_tree_tapbuf_size10_0_sram[3]:7 *C 38.180 121.765 +*N mux_tree_tapbuf_size10_0_sram[3]:8 *C 38.180 121.720 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_0\/FTB_1__33:A 1e-06 +2 mux_top_track_0\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size10_0_sram[3]:3 6.009001e-05 +4 mux_tree_tapbuf_size10_0_sram[3]:4 0.0001646826 +5 mux_tree_tapbuf_size10_0_sram[3]:5 0.0002247726 +6 mux_tree_tapbuf_size10_0_sram[3]:6 0.0002007283 +7 mux_tree_tapbuf_size10_0_sram[3]:7 0.0002007283 +8 mux_tree_tapbuf_size10_0_sram[3]:8 4.013329e-05 +9 mux_tree_tapbuf_size10_0_sram[3]:7 top_left_grid_pin_35_[0]:17 2.563025e-05 +10 mux_tree_tapbuf_size10_0_sram[3]:5 top_left_grid_pin_35_[0]:19 9.825036e-05 +11 mux_tree_tapbuf_size10_0_sram[3]:6 top_left_grid_pin_35_[0]:18 2.563025e-05 +12 mux_tree_tapbuf_size10_0_sram[3]:4 top_left_grid_pin_35_[0]:20 9.825036e-05 +13 mux_tree_tapbuf_size10_0_sram[3]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 7.708099e-05 +14 mux_tree_tapbuf_size10_0_sram[3]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 7.708099e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size10_0_sram[3]:8 0.152 +1 mux_tree_tapbuf_size10_0_sram[3]:3 mux_top_track_0\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[3]:8 mux_tree_tapbuf_size10_0_sram[3]:7 0.0045 +3 mux_tree_tapbuf_size10_0_sram[3]:7 mux_tree_tapbuf_size10_0_sram[3]:6 0.004169643 +4 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:4 0.002861607 +5 mux_tree_tapbuf_size10_0_sram[3]:5 mux_tree_tapbuf_size10_0_sram[3]:3 0.0001752718 +6 mux_tree_tapbuf_size10_0_sram[3]:6 mux_tree_tapbuf_size10_0_sram[3]:5 0.0045 +7 mux_tree_tapbuf_size10_0_sram[3]:4 mem_top_track_0\/FTB_1__33:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_1_ccff_tail[0] 0.0006364235 //LENGTH 3.620 LUMPCC 0.0001424609 DR + +*CONN +*I mem_bottom_track_1\/FTB_2__34:X O *L 0 *C 35.645 28.900 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 36.055 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 *C 36.055 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 *C 35.880 31.620 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 *C 35.880 31.575 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 *C 35.880 28.945 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 *C 35.880 28.900 +*N mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 *C 35.645 28.900 + +*CAP +0 mem_bottom_track_1\/FTB_2__34:X 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 5.682954e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 6.128166e-05 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.0001303053 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0001303053 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 5.592232e-05 +7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 5.731841e-05 +8 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 chanx_left_in[3]:9 7.123046e-05 +9 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 chanx_left_in[3]:8 7.123046e-05 + +*RES +0 mem_bottom_track_1\/FTB_2__34:X mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_1_ccff_tail[0]:6 0.0001059783 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[0] 0.008524407 //LENGTH 70.340 LUMPCC 0.0002812962 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 34.805 42.500 +*I mux_bottom_track_5\/mux_l1_in_5_:S I *L 0.00357 *C 34.860 25.160 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 20.740 +*I mux_bottom_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 34.400 8.840 +*I mux_bottom_track_5\/mux_l1_in_3_:S I *L 0.00357 *C 34.400 3.790 +*I mux_bottom_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 39.660 3.740 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 43.800 6.800 +*I mux_bottom_track_5\/mux_l1_in_4_:S I *L 0.00357 *C 34.860 14.670 +*I mux_bottom_track_5\/mux_l1_in_6_:S I *L 0.00357 *C 35.320 44.880 +*N mux_tree_tapbuf_size14_1_sram[0]:9 *C 35.282 44.880 +*N mux_tree_tapbuf_size14_1_sram[0]:10 *C 33.625 44.880 +*N mux_tree_tapbuf_size14_1_sram[0]:11 *C 33.580 44.835 +*N mux_tree_tapbuf_size14_1_sram[0]:12 *C 34.860 14.670 +*N mux_tree_tapbuf_size14_1_sram[0]:13 *C 34.860 14.280 +*N mux_tree_tapbuf_size14_1_sram[0]:14 *C 43.763 6.800 +*N mux_tree_tapbuf_size14_1_sram[0]:15 *C 41.905 6.800 +*N mux_tree_tapbuf_size14_1_sram[0]:16 *C 41.860 6.755 +*N mux_tree_tapbuf_size14_1_sram[0]:17 *C 41.860 4.125 +*N mux_tree_tapbuf_size14_1_sram[0]:18 *C 41.815 4.080 +*N mux_tree_tapbuf_size14_1_sram[0]:19 *C 40.153 4.080 +*N mux_tree_tapbuf_size14_1_sram[0]:20 *C 40.020 3.765 +*N mux_tree_tapbuf_size14_1_sram[0]:21 *C 39.660 3.740 +*N mux_tree_tapbuf_size14_1_sram[0]:22 *C 34.400 3.748 +*N mux_tree_tapbuf_size14_1_sram[0]:23 *C 34.343 4.080 +*N mux_tree_tapbuf_size14_1_sram[0]:24 *C 32.245 4.080 +*N mux_tree_tapbuf_size14_1_sram[0]:25 *C 32.200 4.125 +*N mux_tree_tapbuf_size14_1_sram[0]:26 *C 32.200 8.840 +*N mux_tree_tapbuf_size14_1_sram[0]:27 *C 34.363 8.840 +*N mux_tree_tapbuf_size14_1_sram[0]:28 *C 32.705 8.840 +*N mux_tree_tapbuf_size14_1_sram[0]:29 *C 32.660 8.885 +*N mux_tree_tapbuf_size14_1_sram[0]:30 *C 32.660 14.235 +*N mux_tree_tapbuf_size14_1_sram[0]:31 *C 32.705 14.280 +*N mux_tree_tapbuf_size14_1_sram[0]:32 *C 33.580 14.280 +*N mux_tree_tapbuf_size14_1_sram[0]:33 *C 33.580 14.325 +*N mux_tree_tapbuf_size14_1_sram[0]:34 *C 32.873 20.740 +*N mux_tree_tapbuf_size14_1_sram[0]:35 *C 33.535 20.740 +*N mux_tree_tapbuf_size14_1_sram[0]:36 *C 33.580 20.740 +*N mux_tree_tapbuf_size14_1_sram[0]:37 *C 34.823 25.160 +*N mux_tree_tapbuf_size14_1_sram[0]:38 *C 33.625 25.160 +*N mux_tree_tapbuf_size14_1_sram[0]:39 *C 33.580 25.160 +*N mux_tree_tapbuf_size14_1_sram[0]:40 *C 33.580 42.500 +*N mux_tree_tapbuf_size14_1_sram[0]:41 *C 33.625 42.500 +*N mux_tree_tapbuf_size14_1_sram[0]:42 *C 34.767 42.500 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_5\/mux_l1_in_5_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_5\/mux_l1_in_2_:S 1e-06 +4 mux_bottom_track_5\/mux_l1_in_3_:S 1e-06 +5 mux_bottom_track_5\/mux_l1_in_1_:S 1e-06 +6 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +7 mux_bottom_track_5\/mux_l1_in_4_:S 1e-06 +8 mux_bottom_track_5\/mux_l1_in_6_:S 1e-06 +9 mux_tree_tapbuf_size14_1_sram[0]:9 0.0001431534 +10 mux_tree_tapbuf_size14_1_sram[0]:10 0.0001431534 +11 mux_tree_tapbuf_size14_1_sram[0]:11 0.0001418044 +12 mux_tree_tapbuf_size14_1_sram[0]:12 5.938751e-05 +13 mux_tree_tapbuf_size14_1_sram[0]:13 0.0001235235 +14 mux_tree_tapbuf_size14_1_sram[0]:14 0.0001241218 +15 mux_tree_tapbuf_size14_1_sram[0]:15 0.0001241218 +16 mux_tree_tapbuf_size14_1_sram[0]:16 0.0001847764 +17 mux_tree_tapbuf_size14_1_sram[0]:17 0.0001847764 +18 mux_tree_tapbuf_size14_1_sram[0]:18 0.0001276304 +19 mux_tree_tapbuf_size14_1_sram[0]:19 0.0001550773 +20 mux_tree_tapbuf_size14_1_sram[0]:20 5.068037e-05 +21 mux_tree_tapbuf_size14_1_sram[0]:21 0.0002644355 +22 mux_tree_tapbuf_size14_1_sram[0]:22 0.0002591476 +23 mux_tree_tapbuf_size14_1_sram[0]:23 0.0001781021 +24 mux_tree_tapbuf_size14_1_sram[0]:24 0.0001544772 +25 mux_tree_tapbuf_size14_1_sram[0]:25 0.0002679451 +26 mux_tree_tapbuf_size14_1_sram[0]:26 0.0003015122 +27 mux_tree_tapbuf_size14_1_sram[0]:27 0.0001402042 +28 mux_tree_tapbuf_size14_1_sram[0]:28 0.0001402042 +29 mux_tree_tapbuf_size14_1_sram[0]:29 0.0003299799 +30 mux_tree_tapbuf_size14_1_sram[0]:30 0.0002964128 +31 mux_tree_tapbuf_size14_1_sram[0]:31 7.436091e-05 +32 mux_tree_tapbuf_size14_1_sram[0]:32 0.0001994358 +33 mux_tree_tapbuf_size14_1_sram[0]:33 0.0004000008 +34 mux_tree_tapbuf_size14_1_sram[0]:34 7.137675e-05 +35 mux_tree_tapbuf_size14_1_sram[0]:35 7.137675e-05 +36 mux_tree_tapbuf_size14_1_sram[0]:36 0.0006966945 +37 mux_tree_tapbuf_size14_1_sram[0]:37 0.0001186158 +38 mux_tree_tapbuf_size14_1_sram[0]:38 0.0001186158 +39 mux_tree_tapbuf_size14_1_sram[0]:39 0.001261991 +40 mux_tree_tapbuf_size14_1_sram[0]:40 0.001146205 +41 mux_tree_tapbuf_size14_1_sram[0]:41 9.040592e-05 +42 mux_tree_tapbuf_size14_1_sram[0]:42 9.040592e-05 +43 mux_tree_tapbuf_size14_1_sram[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.233216e-05 +44 mux_tree_tapbuf_size14_1_sram[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.233216e-05 +45 mux_tree_tapbuf_size14_1_sram[0]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.425146e-05 +46 mux_tree_tapbuf_size14_1_sram[0]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.425146e-05 +47 mux_tree_tapbuf_size14_1_sram[0]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.383877e-05 +48 mux_tree_tapbuf_size14_1_sram[0]:30 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 2.257013e-07 +49 mux_tree_tapbuf_size14_1_sram[0]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.383877e-05 +50 mux_tree_tapbuf_size14_1_sram[0]:29 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 2.257013e-07 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size14_1_sram[0]:42 0.152 +1 mux_tree_tapbuf_size14_1_sram[0]:21 mux_bottom_track_5\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size14_1_sram[0]:21 mux_tree_tapbuf_size14_1_sram[0]:20 0.0003214286 +3 mux_tree_tapbuf_size14_1_sram[0]:10 mux_tree_tapbuf_size14_1_sram[0]:9 0.001479911 +4 mux_tree_tapbuf_size14_1_sram[0]:11 mux_tree_tapbuf_size14_1_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size14_1_sram[0]:9 mux_bottom_track_5\/mux_l1_in_6_:S 0.152 +6 mux_tree_tapbuf_size14_1_sram[0]:18 mux_tree_tapbuf_size14_1_sram[0]:17 0.0045 +7 mux_tree_tapbuf_size14_1_sram[0]:17 mux_tree_tapbuf_size14_1_sram[0]:16 0.002348214 +8 mux_tree_tapbuf_size14_1_sram[0]:15 mux_tree_tapbuf_size14_1_sram[0]:14 0.001658482 +9 mux_tree_tapbuf_size14_1_sram[0]:16 mux_tree_tapbuf_size14_1_sram[0]:15 0.0045 +10 mux_tree_tapbuf_size14_1_sram[0]:14 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +11 mux_tree_tapbuf_size14_1_sram[0]:24 mux_tree_tapbuf_size14_1_sram[0]:23 0.001872768 +12 mux_tree_tapbuf_size14_1_sram[0]:25 mux_tree_tapbuf_size14_1_sram[0]:24 0.0045 +13 mux_tree_tapbuf_size14_1_sram[0]:31 mux_tree_tapbuf_size14_1_sram[0]:30 0.0045 +14 mux_tree_tapbuf_size14_1_sram[0]:30 mux_tree_tapbuf_size14_1_sram[0]:29 0.004776786 +15 mux_tree_tapbuf_size14_1_sram[0]:32 mux_tree_tapbuf_size14_1_sram[0]:31 0.00078125 +16 mux_tree_tapbuf_size14_1_sram[0]:32 mux_tree_tapbuf_size14_1_sram[0]:13 0.001142857 +17 mux_tree_tapbuf_size14_1_sram[0]:33 mux_tree_tapbuf_size14_1_sram[0]:32 0.0045 +18 mux_tree_tapbuf_size14_1_sram[0]:41 mux_tree_tapbuf_size14_1_sram[0]:40 0.0045 +19 mux_tree_tapbuf_size14_1_sram[0]:40 mux_tree_tapbuf_size14_1_sram[0]:39 0.01548214 +20 mux_tree_tapbuf_size14_1_sram[0]:40 mux_tree_tapbuf_size14_1_sram[0]:11 0.002084822 +21 mux_tree_tapbuf_size14_1_sram[0]:42 mux_tree_tapbuf_size14_1_sram[0]:41 0.001020089 +22 mux_tree_tapbuf_size14_1_sram[0]:38 mux_tree_tapbuf_size14_1_sram[0]:37 0.001069196 +23 mux_tree_tapbuf_size14_1_sram[0]:39 mux_tree_tapbuf_size14_1_sram[0]:38 0.0045 +24 mux_tree_tapbuf_size14_1_sram[0]:39 mux_tree_tapbuf_size14_1_sram[0]:36 0.003946429 +25 mux_tree_tapbuf_size14_1_sram[0]:37 mux_bottom_track_5\/mux_l1_in_5_:S 0.152 +26 mux_tree_tapbuf_size14_1_sram[0]:12 mux_bottom_track_5\/mux_l1_in_4_:S 0.152 +27 mux_tree_tapbuf_size14_1_sram[0]:22 mux_bottom_track_5\/mux_l1_in_3_:S 0.152 +28 mux_tree_tapbuf_size14_1_sram[0]:22 mux_tree_tapbuf_size14_1_sram[0]:21 0.004696429 +29 mux_tree_tapbuf_size14_1_sram[0]:28 mux_tree_tapbuf_size14_1_sram[0]:27 0.001479911 +30 mux_tree_tapbuf_size14_1_sram[0]:29 mux_tree_tapbuf_size14_1_sram[0]:28 0.0045 +31 mux_tree_tapbuf_size14_1_sram[0]:29 mux_tree_tapbuf_size14_1_sram[0]:26 0.0004107143 +32 mux_tree_tapbuf_size14_1_sram[0]:27 mux_bottom_track_5\/mux_l1_in_2_:S 0.152 +33 mux_tree_tapbuf_size14_1_sram[0]:35 mux_tree_tapbuf_size14_1_sram[0]:34 0.0005915179 +34 mux_tree_tapbuf_size14_1_sram[0]:36 mux_tree_tapbuf_size14_1_sram[0]:35 0.0045 +35 mux_tree_tapbuf_size14_1_sram[0]:36 mux_tree_tapbuf_size14_1_sram[0]:33 0.005727679 +36 mux_tree_tapbuf_size14_1_sram[0]:34 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +37 mux_tree_tapbuf_size14_1_sram[0]:23 mux_tree_tapbuf_size14_1_sram[0]:22 0.000193314 +38 mux_tree_tapbuf_size14_1_sram[0]:13 mux_tree_tapbuf_size14_1_sram[0]:12 0.0003482143 +39 mux_tree_tapbuf_size14_1_sram[0]:20 mux_tree_tapbuf_size14_1_sram[0]:19 0.000125 +40 mux_tree_tapbuf_size14_1_sram[0]:19 mux_tree_tapbuf_size14_1_sram[0]:18 0.001484375 +41 mux_tree_tapbuf_size14_1_sram[0]:26 mux_tree_tapbuf_size14_1_sram[0]:25 0.004209822 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.007315458 //LENGTH 56.790 LUMPCC 0.001173387 DR + +*CONN +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 55.965 88.060 +*I mux_top_track_32\/mux_l1_in_1_:S I *L 0.00357 *C 62.460 74.800 +*I mux_top_track_32\/mux_l1_in_2_:S I *L 0.00357 *C 49.580 72.760 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 61.815 80.580 +*I mux_top_track_32\/mux_l1_in_0_:S I *L 0.00357 *C 46.820 95.880 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 46.820 95.880 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 46.920 95.835 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 46.920 91.505 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 46.965 91.460 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 54.695 91.460 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 54.740 91.415 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 61.690 80.580 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 49.617 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 51.015 72.760 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 51.060 72.805 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 51.060 75.095 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 51.105 75.140 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 61.180 75.140 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 62.423 74.800 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 61.180 74.800 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 61.180 74.845 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 61.180 79.560 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 61.640 79.560 +*N mux_tree_tapbuf_size6_0_sram[0]:23 *C 61.640 80.535 +*N mux_tree_tapbuf_size6_0_sram[0]:24 *C 61.595 80.580 +*N mux_tree_tapbuf_size6_0_sram[0]:25 *C 54.785 80.580 +*N mux_tree_tapbuf_size6_0_sram[0]:26 *C 54.740 80.625 +*N mux_tree_tapbuf_size6_0_sram[0]:27 *C 54.740 88.060 +*N mux_tree_tapbuf_size6_0_sram[0]:28 *C 54.785 88.060 +*N mux_tree_tapbuf_size6_0_sram[0]:29 *C 55.928 88.060 + +*CAP +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_32\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:S 1e-06 +3 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_32\/mux_l1_in_0_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 2.621977e-05 +6 mux_tree_tapbuf_size6_0_sram[0]:6 0.000255765 +7 mux_tree_tapbuf_size6_0_sram[0]:7 0.000255765 +8 mux_tree_tapbuf_size6_0_sram[0]:8 0.0003127444 +9 mux_tree_tapbuf_size6_0_sram[0]:9 0.0003127444 +10 mux_tree_tapbuf_size6_0_sram[0]:10 0.0001499495 +11 mux_tree_tapbuf_size6_0_sram[0]:11 2.391194e-05 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.0001147978 +13 mux_tree_tapbuf_size6_0_sram[0]:13 0.0001147978 +14 mux_tree_tapbuf_size6_0_sram[0]:14 0.0001473233 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0001473233 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.0007486193 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0007779524 +18 mux_tree_tapbuf_size6_0_sram[0]:18 0.0001289453 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0001582785 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0001955356 +21 mux_tree_tapbuf_size6_0_sram[0]:21 0.0002260937 +22 mux_tree_tapbuf_size6_0_sram[0]:22 0.0001019227 +23 mux_tree_tapbuf_size6_0_sram[0]:23 7.136462e-05 +24 mux_tree_tapbuf_size6_0_sram[0]:24 0.0004520784 +25 mux_tree_tapbuf_size6_0_sram[0]:25 0.0004281664 +26 mux_tree_tapbuf_size6_0_sram[0]:26 0.0003162178 +27 mux_tree_tapbuf_size6_0_sram[0]:27 0.0004962325 +28 mux_tree_tapbuf_size6_0_sram[0]:28 8.716071e-05 +29 mux_tree_tapbuf_size6_0_sram[0]:29 8.716071e-05 +30 mux_tree_tapbuf_size6_0_sram[0]:23 chany_top_in[2]:18 3.761986e-06 +31 mux_tree_tapbuf_size6_0_sram[0]:20 chany_top_in[2]:15 0.0001303256 +32 mux_tree_tapbuf_size6_0_sram[0]:9 chany_top_in[2]:17 0.0003018499 +33 mux_tree_tapbuf_size6_0_sram[0]:8 chany_top_in[2]:16 0.0003018499 +34 mux_tree_tapbuf_size6_0_sram[0]:21 chany_top_in[2]:18 0.0001303256 +35 mux_tree_tapbuf_size6_0_sram[0]:22 chany_top_in[2]:15 3.761986e-06 +36 mux_tree_tapbuf_size6_0_sram[0]:26 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.634705e-05 +37 mux_tree_tapbuf_size6_0_sram[0]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:6 4.260178e-05 +38 mux_tree_tapbuf_size6_0_sram[0]:27 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 9.634705e-05 +39 mux_tree_tapbuf_size6_0_sram[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.180718e-05 +40 mux_tree_tapbuf_size6_0_sram[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 4.260178e-05 +41 mux_tree_tapbuf_size6_0_sram[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.180718e-05 + +*RES +0 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:29 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:18 mux_top_track_32\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.002044643 +4 mux_tree_tapbuf_size6_0_sram[0]:13 mux_tree_tapbuf_size6_0_sram[0]:12 0.001247768 +5 mux_tree_tapbuf_size6_0_sram[0]:14 mux_tree_tapbuf_size6_0_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size6_0_sram[0]:12 mux_top_track_32\/mux_l1_in_2_:S 0.152 +7 mux_tree_tapbuf_size6_0_sram[0]:25 mux_tree_tapbuf_size6_0_sram[0]:24 0.006080358 +8 mux_tree_tapbuf_size6_0_sram[0]:26 mux_tree_tapbuf_size6_0_sram[0]:25 0.0045 +9 mux_tree_tapbuf_size6_0_sram[0]:24 mux_tree_tapbuf_size6_0_sram[0]:23 0.0045 +10 mux_tree_tapbuf_size6_0_sram[0]:24 mux_tree_tapbuf_size6_0_sram[0]:11 8.482144e-05 +11 mux_tree_tapbuf_size6_0_sram[0]:23 mux_tree_tapbuf_size6_0_sram[0]:22 0.0008705358 +12 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.001109375 +13 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:17 0.0003035715 +14 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.0045 +15 mux_tree_tapbuf_size6_0_sram[0]:28 mux_tree_tapbuf_size6_0_sram[0]:27 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:27 mux_tree_tapbuf_size6_0_sram[0]:26 0.006638393 +17 mux_tree_tapbuf_size6_0_sram[0]:27 mux_tree_tapbuf_size6_0_sram[0]:10 0.002995536 +18 mux_tree_tapbuf_size6_0_sram[0]:29 mux_tree_tapbuf_size6_0_sram[0]:28 0.001020089 +19 mux_tree_tapbuf_size6_0_sram[0]:11 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size6_0_sram[0]:9 mux_tree_tapbuf_size6_0_sram[0]:8 0.006901786 +21 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0045 +22 mux_tree_tapbuf_size6_0_sram[0]:8 mux_tree_tapbuf_size6_0_sram[0]:7 0.0045 +23 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.003866072 +24 mux_tree_tapbuf_size6_0_sram[0]:5 mux_top_track_32\/mux_l1_in_0_:S 0.152 +25 mux_tree_tapbuf_size6_0_sram[0]:6 mux_tree_tapbuf_size6_0_sram[0]:5 0.0045 +26 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.008995537 +27 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.004209821 +28 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[2] 0.0008920548 //LENGTH 7.815 LUMPCC 0 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 43.545 93.500 +*I mux_top_track_24\/mux_l3_in_0_:S I *L 0.00357 *C 44.520 90.440 +*I mem_top_track_24\/FTB_9__41:A I *L 0.001746 *C 46.920 93.840 +*N mux_tree_tapbuf_size7_1_sram[2]:3 *C 46.883 93.840 +*N mux_tree_tapbuf_size7_1_sram[2]:4 *C 44.620 93.840 +*N mux_tree_tapbuf_size7_1_sram[2]:5 *C 44.520 90.440 +*N mux_tree_tapbuf_size7_1_sram[2]:6 *C 44.620 90.485 +*N mux_tree_tapbuf_size7_1_sram[2]:7 *C 44.620 93.455 +*N mux_tree_tapbuf_size7_1_sram[2]:8 *C 44.620 93.530 +*N mux_tree_tapbuf_size7_1_sram[2]:9 *C 43.583 93.500 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:S 1e-06 +2 mem_top_track_24\/FTB_9__41:A 1e-06 +3 mux_tree_tapbuf_size7_1_sram[2]:3 0.0001345007 +4 mux_tree_tapbuf_size7_1_sram[2]:4 0.0001632293 +5 mux_tree_tapbuf_size7_1_sram[2]:5 2.850882e-05 +6 mux_tree_tapbuf_size7_1_sram[2]:6 0.0001863194 +7 mux_tree_tapbuf_size7_1_sram[2]:7 0.0001863194 +8 mux_tree_tapbuf_size7_1_sram[2]:8 0.0001094529 +9 mux_tree_tapbuf_size7_1_sram[2]:9 8.072425e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_1_sram[2]:9 0.152 +1 mux_tree_tapbuf_size7_1_sram[2]:3 mem_top_track_24\/FTB_9__41:A 0.152 +2 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size7_1_sram[2]:8 mux_tree_tapbuf_size7_1_sram[2]:4 0.0002767857 +4 mux_tree_tapbuf_size7_1_sram[2]:7 mux_tree_tapbuf_size7_1_sram[2]:6 0.002651786 +5 mux_tree_tapbuf_size7_1_sram[2]:5 mux_top_track_24\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size7_1_sram[2]:6 mux_tree_tapbuf_size7_1_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size7_1_sram[2]:9 mux_tree_tapbuf_size7_1_sram[2]:8 0.0009263393 +8 mux_tree_tapbuf_size7_1_sram[2]:4 mux_tree_tapbuf_size7_1_sram[2]:3 0.002020089 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[2] 0.002358356 //LENGTH 17.235 LUMPCC 0.0005631257 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 29.285 93.500 +*I mux_left_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 20.800 89.080 +*I mem_left_track_1\/FTB_11__43:A I *L 0.001746 *C 25.300 85.680 +*N mux_tree_tapbuf_size7_3_sram[2]:3 *C 25.300 85.680 +*N mux_tree_tapbuf_size7_3_sram[2]:4 *C 25.300 85.725 +*N mux_tree_tapbuf_size7_3_sram[2]:5 *C 20.838 89.080 +*N mux_tree_tapbuf_size7_3_sram[2]:6 *C 25.255 89.080 +*N mux_tree_tapbuf_size7_3_sram[2]:7 *C 25.300 89.080 +*N mux_tree_tapbuf_size7_3_sram[2]:8 *C 25.300 93.455 +*N mux_tree_tapbuf_size7_3_sram[2]:9 *C 25.345 93.500 +*N mux_tree_tapbuf_size7_3_sram[2]:10 *C 29.248 93.500 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_1\/FTB_11__43:A 1e-06 +3 mux_tree_tapbuf_size7_3_sram[2]:3 3.135922e-05 +4 mux_tree_tapbuf_size7_3_sram[2]:4 0.0001752129 +5 mux_tree_tapbuf_size7_3_sram[2]:5 0.0002994302 +6 mux_tree_tapbuf_size7_3_sram[2]:6 0.0002994302 +7 mux_tree_tapbuf_size7_3_sram[2]:7 0.0004099141 +8 mux_tree_tapbuf_size7_3_sram[2]:8 0.0002031929 +9 mux_tree_tapbuf_size7_3_sram[2]:9 0.0001868451 +10 mux_tree_tapbuf_size7_3_sram[2]:10 0.0001868451 +11 mux_tree_tapbuf_size7_3_sram[2]:9 chany_top_in[1]:7 0.000156291 +12 mux_tree_tapbuf_size7_3_sram[2]:10 chany_top_in[1]:8 0.000156291 +13 mux_tree_tapbuf_size7_3_sram[2]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.890756e-06 +14 mux_tree_tapbuf_size7_3_sram[2]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.980166e-05 +15 mux_tree_tapbuf_size7_3_sram[2]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.890756e-06 +16 mux_tree_tapbuf_size7_3_sram[2]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.980166e-05 +17 mux_tree_tapbuf_size7_3_sram[2]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.593838e-05 +18 mux_tree_tapbuf_size7_3_sram[2]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.027076e-05 +19 mux_tree_tapbuf_size7_3_sram[2]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.370272e-06 +20 mux_tree_tapbuf_size7_3_sram[2]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.593838e-05 +21 mux_tree_tapbuf_size7_3_sram[2]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 3.370272e-06 +22 mux_tree_tapbuf_size7_3_sram[2]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.027076e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_3_sram[2]:10 0.152 +1 mux_tree_tapbuf_size7_3_sram[2]:6 mux_tree_tapbuf_size7_3_sram[2]:5 0.003944197 +2 mux_tree_tapbuf_size7_3_sram[2]:7 mux_tree_tapbuf_size7_3_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size7_3_sram[2]:7 mux_tree_tapbuf_size7_3_sram[2]:4 0.002995536 +4 mux_tree_tapbuf_size7_3_sram[2]:5 mux_left_track_1\/mux_l3_in_0_:S 0.152 +5 mux_tree_tapbuf_size7_3_sram[2]:3 mem_left_track_1\/FTB_11__43:A 0.152 +6 mux_tree_tapbuf_size7_3_sram[2]:4 mux_tree_tapbuf_size7_3_sram[2]:3 0.0045 +7 mux_tree_tapbuf_size7_3_sram[2]:9 mux_tree_tapbuf_size7_3_sram[2]:8 0.0045 +8 mux_tree_tapbuf_size7_3_sram[2]:8 mux_tree_tapbuf_size7_3_sram[2]:7 0.00390625 +9 mux_tree_tapbuf_size7_3_sram[2]:10 mux_tree_tapbuf_size7_3_sram[2]:9 0.003484375 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_0_ccff_tail[0] 0.00185907 //LENGTH 15.490 LUMPCC 0.0003551299 DR + +*CONN +*I mem_top_track_16\/FTB_8__40:X O *L 0 *C 71.995 93.840 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 63.195 88.060 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 *C 63.195 88.060 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 *C 63.480 88.060 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 *C 63.480 88.105 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 *C 63.480 93.455 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 *C 63.525 93.500 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 *C 71.760 93.500 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 *C 71.760 93.805 +*N mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:9 *C 71.968 93.818 + +*CAP +0 mem_top_track_16\/FTB_8__40:X 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 5.019047e-05 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 5.542445e-05 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.0002719148 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0002719148 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.0003715515 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.0003983365 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 5.469652e-05 +9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:9 2.791142e-05 +10 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 chany_bottom_in[8]:12 2.852974e-05 +11 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 chany_bottom_in[8]:13 3.279055e-05 +12 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 chany_bottom_in[8]:14 3.279055e-05 +13 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 chany_bottom_in[8]:13 2.852974e-05 +14 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_top_track_16\/mux_l3_in_0_:S 4.897243e-05 +15 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_0_sram[2]:4 4.016977e-05 +16 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_0_sram[2]:6 2.710248e-05 +17 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_0_sram[2]:3 4.016977e-05 +18 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_0_sram[2]:5 2.710248e-05 +19 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_0_sram[2]:6 4.897243e-05 + +*RES +0 mem_top_track_16\/FTB_8__40:X mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 0.0001402027 +2 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 0.007352679 +8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[3] 0.001318398 //LENGTH 11.900 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 81.565 33.320 +*I mem_bottom_track_9\/FTB_5__37:A I *L 0.001746 *C 84.640 39.440 +*I mux_bottom_track_9\/mux_l4_in_0_:S I *L 0.008363 *C 81.420 31.165 +*N mux_tree_tapbuf_size8_2_sram[3]:3 *C 84.640 39.440 +*N mux_tree_tapbuf_size8_2_sram[3]:4 *C 84.640 39.395 +*N mux_tree_tapbuf_size8_2_sram[3]:5 *C 84.640 31.110 +*N mux_tree_tapbuf_size8_2_sram[3]:6 *C 84.180 31.110 +*N mux_tree_tapbuf_size8_2_sram[3]:7 *C 81.420 31.165 +*N mux_tree_tapbuf_size8_2_sram[3]:8 *C 81.420 31.280 +*N mux_tree_tapbuf_size8_2_sram[3]:9 *C 81.420 31.325 +*N mux_tree_tapbuf_size8_2_sram[3]:10 *C 81.420 33.275 +*N mux_tree_tapbuf_size8_2_sram[3]:11 *C 81.420 33.320 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_9\/FTB_5__37:A 1e-06 +2 mux_bottom_track_9\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_2_sram[3]:3 2.921434e-05 +4 mux_tree_tapbuf_size8_2_sram[3]:4 0.0004080147 +5 mux_tree_tapbuf_size8_2_sram[3]:5 0.0004435192 +6 mux_tree_tapbuf_size8_2_sram[3]:6 6.937511e-05 +7 mux_tree_tapbuf_size8_2_sram[3]:7 1.578511e-05 +8 mux_tree_tapbuf_size8_2_sram[3]:8 1.578511e-05 +9 mux_tree_tapbuf_size8_2_sram[3]:9 0.0001497145 +10 mux_tree_tapbuf_size8_2_sram[3]:10 0.0001497145 +11 mux_tree_tapbuf_size8_2_sram[3]:11 3.427535e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_2_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_2_sram[3]:8 mux_tree_tapbuf_size8_2_sram[3]:7 4.503907e-05 +2 mux_tree_tapbuf_size8_2_sram[3]:9 mux_tree_tapbuf_size8_2_sram[3]:8 0.0045 +3 mux_tree_tapbuf_size8_2_sram[3]:11 mux_tree_tapbuf_size8_2_sram[3]:10 0.0045 +4 mux_tree_tapbuf_size8_2_sram[3]:10 mux_tree_tapbuf_size8_2_sram[3]:9 0.001741071 +5 mux_tree_tapbuf_size8_2_sram[3]:3 mem_bottom_track_9\/FTB_5__37:A 0.152 +6 mux_tree_tapbuf_size8_2_sram[3]:4 mux_tree_tapbuf_size8_2_sram[3]:3 0.0045 +7 mux_tree_tapbuf_size8_2_sram[3]:6 mux_tree_tapbuf_size8_2_sram[3]:5 0.0004107143 +8 mux_tree_tapbuf_size8_2_sram[3]:5 mux_tree_tapbuf_size8_2_sram[3]:4 0.007397322 +9 mux_tree_tapbuf_size8_2_sram[3]:7 mux_tree_tapbuf_size8_2_sram[3]:6 0.0045 +10 mux_tree_tapbuf_size8_2_sram[3]:7 mux_bottom_track_9\/mux_l4_in_0_:S 1e-05 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001337377 //LENGTH 10.560 LUMPCC 0.0002828564 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_0_:X O *L 0 *C 39.735 126.140 +*I mux_top_track_0\/mux_l2_in_0_:A1 I *L 0.00198 *C 41.400 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 41.400 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 41.400 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 40.940 117.980 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 40.940 126.095 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 40.895 126.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 39.773 126.140 + +*CAP +0 mux_top_track_0\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.70555e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.740914e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003854538 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003508875 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001058574 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001058574 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_36_[0]:13 7.087539e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_36_[0]:14 5.466149e-06 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_36_[0]:12 7.087539e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_36_[0]:13 5.466149e-06 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.508664e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.508664e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001002232 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007245536 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A1 0.152 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004107143 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0] 0.00150345 //LENGTH 12.350 LUMPCC 0.0001711457 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_1_:X O *L 0 *C 46.175 31.280 +*I mux_bottom_track_1\/mux_l4_in_0_:A0 I *L 0.001631 *C 43.415 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 43.415 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 43.240 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 43.240 22.825 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 43.240 31.235 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 43.285 31.280 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 46.138 31.280 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 3.647629e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 4.061769e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004231977 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004231977 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0002034076 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0002034076 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_1_sram[3]:8 1.363212e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_1_sram[3]:7 1.363212e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_1_sram[3]:6 7.194074e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_1_sram[3]:5 7.194074e-05 + +*RES +0 mux_bottom_track_1\/mux_l3_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_1\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.51087e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.007508929 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.002546875 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002208767 //LENGTH 17.530 LUMPCC 0.0008174946 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_1_:X O *L 0 *C 66.985 20.740 +*I mux_bottom_track_9\/mux_l3_in_0_:A0 I *L 0.001631 *C 72.365 31.960 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 72.328 31.960 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 67.665 31.960 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 67.620 31.915 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 67.620 20.785 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 67.575 20.740 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 67.023 20.740 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002333941 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002333941 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003870239 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003870239 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.421832e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 7.421832e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[6]:11 8.453763e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[6]:15 8.453763e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_top_in[10]:9 0.0001764951 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 chany_top_in[10]:8 0.0001764951 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 chany_top_in[16]:9 0.0001477146 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_top_in[16]:10 0.0001477146 + +*RES +0 mux_bottom_track_9\/mux_l2_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004933036 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0099375 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004162947 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001065279 //LENGTH 9.185 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_4_:X O *L 0 *C 62.275 102.680 +*I mux_top_track_4\/mux_l2_in_2_:A1 I *L 0.00198 *C 56.680 105.060 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 56.718 105.060 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 57.040 105.060 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 57.040 104.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 61.135 104.720 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 61.180 104.675 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 61.180 102.725 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 61.225 102.680 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 62.238 102.680 + +*CAP +0 mux_top_track_4\/mux_l1_in_4_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_2_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.756925e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 6.286643e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002809162 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000255619 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001223005 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001223005 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 9.085379e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 9.085379e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_4_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_4\/mux_l2_in_2_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.00365625 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001741071 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0009040179 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002879465 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0002959385 //LENGTH 2.305 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_2_:X O *L 0 *C 35.245 9.180 +*I mux_bottom_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 37.260 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 37.223 9.180 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 35.282 9.180 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001469693 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001469693 + +*RES +0 mux_bottom_track_5\/mux_l1_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001732143 + +*END + +*D_NET optlc_net_139 0.01962945 //LENGTH 140.092 LUMPCC 0.003781759 DR + +*CONN +*I optlc_136:HI O *L 0 *C 33.120 76.840 +*I mux_top_track_24\/mux_l1_in_3_:A0 I *L 0.001631 *C 30.995 75.480 +*I mux_top_track_2\/mux_l2_in_3_:A0 I *L 0.001631 *C 30.535 91.460 +*I mux_left_track_21\/mux_l1_in_1_:A0 I *L 0.001631 *C 25.015 76.840 +*I mux_left_track_5\/mux_l1_in_3_:A0 I *L 0.001631 *C 20.530 76.840 +*I mux_left_track_3\/mux_l1_in_3_:A0 I *L 0.001631 *C 15.930 80.580 +*I mux_left_track_1\/mux_l1_in_3_:A0 I *L 0.001631 *C 15.355 88.060 +*I mux_top_track_0\/mux_l2_in_3_:A0 I *L 0.001631 *C 10.295 93.500 +*I mux_top_track_16\/mux_l1_in_3_:A0 I *L 0.001631 *C 37.435 66.300 +*I mux_left_track_7\/mux_l1_in_3_:A0 I *L 0.001631 *C 33.755 64.600 +*I mux_left_track_15\/mux_l2_in_1_:A0 I *L 0.001631 *C 14.090 60.520 +*I mux_left_track_17\/mux_l1_in_1_:A0 I *L 0.001631 *C 20.530 60.520 +*I mux_bottom_track_3\/mux_l2_in_3_:A0 I *L 0.001631 *C 23.635 48.280 +*I mux_left_track_13\/mux_l2_in_1_:A0 I *L 0.001631 *C 26.395 49.640 +*I mux_left_track_19\/mux_l1_in_1_:A0 I *L 0.001631 *C 25.015 58.820 +*I mux_left_track_23\/mux_l1_in_1_:A0 I *L 0.001631 *C 38.355 80.580 +*N optlc_net_139:16 *C 38.318 80.580 +*N optlc_net_139:17 *C 36.845 80.580 +*N optlc_net_139:18 *C 36.800 80.535 +*N optlc_net_139:19 *C 24.890 58.820 +*N optlc_net_139:20 *C 26.358 49.640 +*N optlc_net_139:21 *C 23.635 48.280 +*N optlc_net_139:22 *C 23.920 48.280 +*N optlc_net_139:23 *C 23.920 48.325 +*N optlc_net_139:24 *C 23.920 49.595 +*N optlc_net_139:25 *C 23.965 49.640 +*N optlc_net_139:26 *C 24.840 49.640 +*N optlc_net_139:27 *C 24.840 49.685 +*N optlc_net_139:28 *C 24.840 58.775 +*N optlc_net_139:29 *C 24.795 58.820 +*N optlc_net_139:30 *C 18.445 58.820 +*N optlc_net_139:31 *C 18.400 58.865 +*N optlc_net_139:32 *C 20.492 60.520 +*N optlc_net_139:33 *C 14.128 60.520 +*N optlc_net_139:34 *C 17.940 60.520 +*N optlc_net_139:35 *C 17.940 60.475 +*N optlc_net_139:36 *C 17.940 59.840 +*N optlc_net_139:37 *C 18.400 59.783 +*N optlc_net_139:38 *C 18.408 59.840 +*N optlc_net_139:39 *C 36.793 59.840 +*N optlc_net_139:40 *C 36.800 59.898 +*N optlc_net_139:41 *C 33.793 64.600 +*N optlc_net_139:42 *C 36.755 64.600 +*N optlc_net_139:43 *C 36.800 64.600 +*N optlc_net_139:44 *C 37.398 66.300 +*N optlc_net_139:45 *C 36.845 66.300 +*N optlc_net_139:46 *C 36.800 66.300 +*N optlc_net_139:47 *C 36.800 76.840 +*N optlc_net_139:48 *C 36.755 76.840 +*N optlc_net_139:49 *C 10.333 93.500 +*N optlc_net_139:50 *C 12.835 93.500 +*N optlc_net_139:51 *C 12.880 93.455 +*N optlc_net_139:52 *C 12.880 88.105 +*N optlc_net_139:53 *C 12.925 88.060 +*N optlc_net_139:54 *C 15.180 88.060 +*N optlc_net_139:55 *C 15.230 88.038 +*N optlc_net_139:56 *C 15.180 87.720 +*N optlc_net_139:57 *C 16.515 87.720 +*N optlc_net_139:58 *C 16.560 87.675 +*N optlc_net_139:59 *C 15.968 80.580 +*N optlc_net_139:60 *C 16.515 80.580 +*N optlc_net_139:61 *C 16.560 80.580 +*N optlc_net_139:62 *C 16.560 77.225 +*N optlc_net_139:63 *C 16.605 77.180 +*N optlc_net_139:64 *C 19.320 77.180 +*N optlc_net_139:65 *C 19.320 76.840 +*N optlc_net_139:66 *C 20.530 76.840 +*N optlc_net_139:67 *C 25.015 76.840 +*N optlc_net_139:68 *C 30.535 91.460 +*N optlc_net_139:69 *C 30.820 91.460 +*N optlc_net_139:70 *C 30.820 91.415 +*N optlc_net_139:71 *C 30.995 75.480 +*N optlc_net_139:72 *C 30.820 75.480 +*N optlc_net_139:73 *C 30.820 75.525 +*N optlc_net_139:74 *C 30.820 76.840 +*N optlc_net_139:75 *C 30.820 76.840 +*N optlc_net_139:76 *C 33.120 76.840 + +*CAP +0 optlc_136:HI 1e-06 +1 mux_top_track_24\/mux_l1_in_3_:A0 1e-06 +2 mux_top_track_2\/mux_l2_in_3_:A0 1e-06 +3 mux_left_track_21\/mux_l1_in_1_:A0 1e-06 +4 mux_left_track_5\/mux_l1_in_3_:A0 1e-06 +5 mux_left_track_3\/mux_l1_in_3_:A0 1e-06 +6 mux_left_track_1\/mux_l1_in_3_:A0 1e-06 +7 mux_top_track_0\/mux_l2_in_3_:A0 1e-06 +8 mux_top_track_16\/mux_l1_in_3_:A0 1e-06 +9 mux_left_track_7\/mux_l1_in_3_:A0 1e-06 +10 mux_left_track_15\/mux_l2_in_1_:A0 1e-06 +11 mux_left_track_17\/mux_l1_in_1_:A0 1e-06 +12 mux_bottom_track_3\/mux_l2_in_3_:A0 1e-06 +13 mux_left_track_13\/mux_l2_in_1_:A0 1e-06 +14 mux_left_track_19\/mux_l1_in_1_:A0 1e-06 +15 mux_left_track_23\/mux_l1_in_1_:A0 1e-06 +16 optlc_net_139:16 0.0001186686 +17 optlc_net_139:17 0.0001186686 +18 optlc_net_139:18 0.0002151029 +19 optlc_net_139:19 2.156438e-05 +20 optlc_net_139:20 0.0001049742 +21 optlc_net_139:21 6.018675e-05 +22 optlc_net_139:22 6.196907e-05 +23 optlc_net_139:23 9.17181e-05 +24 optlc_net_139:24 9.17181e-05 +25 optlc_net_139:25 6.668948e-05 +26 optlc_net_139:26 0.0002052136 +27 optlc_net_139:27 0.0005164898 +28 optlc_net_139:28 0.0005164898 +29 optlc_net_139:29 0.0004643469 +30 optlc_net_139:30 0.0004427825 +31 optlc_net_139:31 5.032208e-05 +32 optlc_net_139:32 0.0001814052 +33 optlc_net_139:33 0.0002524437 +34 optlc_net_139:34 0.0004704466 +35 optlc_net_139:35 3.530481e-05 +36 optlc_net_139:36 7.244106e-05 +37 optlc_net_139:37 8.745834e-05 +38 optlc_net_139:38 0.000534802 +39 optlc_net_139:39 0.000534802 +40 optlc_net_139:40 0.0002712304 +41 optlc_net_139:41 0.0002165893 +42 optlc_net_139:42 0.0002165893 +43 optlc_net_139:43 0.0003988434 +44 optlc_net_139:44 7.309869e-05 +45 optlc_net_139:45 7.309869e-05 +46 optlc_net_139:46 0.0007296774 +47 optlc_net_139:47 0.0008488116 +48 optlc_net_139:48 0.0002557723 +49 optlc_net_139:49 0.0002449109 +50 optlc_net_139:50 0.0002449109 +51 optlc_net_139:51 0.0002604579 +52 optlc_net_139:52 0.0002604579 +53 optlc_net_139:53 0.0001617787 +54 optlc_net_139:54 0.0001842982 +55 optlc_net_139:55 4.4403e-05 +56 optlc_net_139:56 0.0001273278 +57 optlc_net_139:57 0.0001054442 +58 optlc_net_139:58 0.0002956864 +59 optlc_net_139:59 6.82807e-05 +60 optlc_net_139:60 6.82807e-05 +61 optlc_net_139:61 0.0004862311 +62 optlc_net_139:62 0.0001565343 +63 optlc_net_139:63 0.0002153018 +64 optlc_net_139:64 0.0002409106 +65 optlc_net_139:65 0.0001097497 +66 optlc_net_139:66 0.0004094995 +67 optlc_net_139:67 0.000715376 +68 optlc_net_139:68 5.143958e-05 +69 optlc_net_139:69 5.353446e-05 +70 optlc_net_139:70 0.0007868076 +71 optlc_net_139:71 5.964991e-05 +72 optlc_net_139:72 6.080573e-05 +73 optlc_net_139:73 8.982746e-05 +74 optlc_net_139:74 0.0009090159 +75 optlc_net_139:75 0.0005768592 +76 optlc_net_139:76 0.000444189 +77 optlc_net_139:30 chanx_left_in[10] 5.443561e-06 +78 optlc_net_139:29 chanx_left_in[10]:11 5.443561e-06 +79 optlc_net_139:39 chanx_left_in[10]:11 0.000932536 +80 optlc_net_139:38 chanx_left_in[10] 0.000932536 +81 optlc_net_139:35 mux_tree_tapbuf_size7_3_sram[0]:26 9.377487e-06 +82 optlc_net_139:58 mux_tree_tapbuf_size7_3_sram[0]:26 0.0001851398 +83 optlc_net_139:70 mux_tree_tapbuf_size7_3_sram[0]:10 2.867296e-08 +84 optlc_net_139:31 mux_tree_tapbuf_size7_3_sram[0]:27 5.556346e-06 +85 optlc_net_139:74 mux_tree_tapbuf_size7_3_sram[0]:11 2.867296e-08 +86 optlc_net_139:62 mux_tree_tapbuf_size7_3_sram[0]:27 8.913663e-05 +87 optlc_net_139:37 mux_tree_tapbuf_size7_3_sram[0]:26 5.556346e-06 +88 optlc_net_139:61 mux_tree_tapbuf_size7_3_sram[0]:26 8.913663e-05 +89 optlc_net_139:61 mux_tree_tapbuf_size7_3_sram[0]:27 0.0001851398 +90 optlc_net_139:36 mux_tree_tapbuf_size7_3_sram[0]:27 9.377487e-06 +91 optlc_net_139:53 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 1.274592e-06 +92 optlc_net_139:52 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001060475 +93 optlc_net_139:51 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001060475 +94 optlc_net_139:54 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 1.274592e-06 +95 optlc_net_139:70 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.300822e-05 +96 optlc_net_139:70 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 8.389214e-06 +97 optlc_net_139:74 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.300822e-05 +98 optlc_net_139:74 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.389214e-06 +99 optlc_net_139:42 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.117886e-05 +100 optlc_net_139:41 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.117886e-05 +101 optlc_net_139:39 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0004006457 +102 optlc_net_139:38 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004006457 +103 optlc_net_139:34 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.551245e-06 +104 optlc_net_139:35 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.25118e-06 +105 optlc_net_139:31 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.331452e-05 +106 optlc_net_139:37 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.331452e-05 +107 optlc_net_139:32 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.551245e-06 +108 optlc_net_139:36 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.25118e-06 + +*RES +0 optlc_136:HI optlc_net_139:76 0.152 +1 optlc_net_139:34 optlc_net_139:33 0.003404018 +2 optlc_net_139:34 optlc_net_139:32 0.002279018 +3 optlc_net_139:35 optlc_net_139:34 0.0045 +4 optlc_net_139:33 mux_left_track_15\/mux_l2_in_1_:A0 0.152 +5 optlc_net_139:57 optlc_net_139:56 0.001191964 +6 optlc_net_139:58 optlc_net_139:57 0.0045 +7 optlc_net_139:69 optlc_net_139:68 0.0001548913 +8 optlc_net_139:70 optlc_net_139:69 0.0045 +9 optlc_net_139:68 mux_top_track_2\/mux_l2_in_3_:A0 0.152 +10 optlc_net_139:48 optlc_net_139:47 0.0045 +11 optlc_net_139:47 optlc_net_139:46 0.009410716 +12 optlc_net_139:47 optlc_net_139:18 0.003299107 +13 optlc_net_139:30 optlc_net_139:29 0.005669643 +14 optlc_net_139:31 optlc_net_139:30 0.0045 +15 optlc_net_139:75 optlc_net_139:74 0.0045 +16 optlc_net_139:75 optlc_net_139:67 0.005183036 +17 optlc_net_139:74 optlc_net_139:73 0.001174107 +18 optlc_net_139:74 optlc_net_139:70 0.01301339 +19 optlc_net_139:29 optlc_net_139:28 0.0045 +20 optlc_net_139:29 optlc_net_139:19 8.482143e-05 +21 optlc_net_139:28 optlc_net_139:27 0.008116071 +22 optlc_net_139:26 optlc_net_139:25 0.00078125 +23 optlc_net_139:26 optlc_net_139:20 0.001354911 +24 optlc_net_139:27 optlc_net_139:26 0.0045 +25 optlc_net_139:63 optlc_net_139:62 0.0045 +26 optlc_net_139:62 optlc_net_139:61 0.002995536 +27 optlc_net_139:40 optlc_net_139:39 0.00341 +28 optlc_net_139:39 optlc_net_139:38 0.002880317 +29 optlc_net_139:37 optlc_net_139:36 0.0004107143 +30 optlc_net_139:37 optlc_net_139:31 0.0008191965 +31 optlc_net_139:38 optlc_net_139:37 0.00341 +32 optlc_net_139:42 optlc_net_139:41 0.002645089 +33 optlc_net_139:43 optlc_net_139:42 0.0045 +34 optlc_net_139:43 optlc_net_139:40 0.004198661 +35 optlc_net_139:41 mux_left_track_7\/mux_l1_in_3_:A0 0.152 +36 optlc_net_139:55 mux_left_track_1\/mux_l1_in_3_:A0 0.152 +37 optlc_net_139:55 optlc_net_139:54 4.464286e-05 +38 optlc_net_139:17 optlc_net_139:16 0.001314732 +39 optlc_net_139:18 optlc_net_139:17 0.0045 +40 optlc_net_139:16 mux_left_track_23\/mux_l1_in_1_:A0 0.152 +41 optlc_net_139:67 mux_left_track_21\/mux_l1_in_1_:A0 0.152 +42 optlc_net_139:67 optlc_net_139:66 0.004004464 +43 optlc_net_139:19 mux_left_track_19\/mux_l1_in_1_:A0 0.152 +44 optlc_net_139:25 optlc_net_139:24 0.0045 +45 optlc_net_139:24 optlc_net_139:23 0.001133929 +46 optlc_net_139:22 optlc_net_139:21 0.0001548913 +47 optlc_net_139:23 optlc_net_139:22 0.0045 +48 optlc_net_139:21 mux_bottom_track_3\/mux_l2_in_3_:A0 0.152 +49 optlc_net_139:72 optlc_net_139:71 9.51087e-05 +50 optlc_net_139:73 optlc_net_139:72 0.0045 +51 optlc_net_139:71 mux_top_track_24\/mux_l1_in_3_:A0 0.152 +52 optlc_net_139:45 optlc_net_139:44 0.0004933036 +53 optlc_net_139:46 optlc_net_139:45 0.0045 +54 optlc_net_139:46 optlc_net_139:43 0.001517857 +55 optlc_net_139:44 mux_top_track_16\/mux_l1_in_3_:A0 0.152 +56 optlc_net_139:32 mux_left_track_17\/mux_l1_in_1_:A0 0.152 +57 optlc_net_139:20 mux_left_track_13\/mux_l2_in_1_:A0 0.152 +58 optlc_net_139:66 mux_left_track_5\/mux_l1_in_3_:A0 0.152 +59 optlc_net_139:66 optlc_net_139:65 0.001080357 +60 optlc_net_139:53 optlc_net_139:52 0.0045 +61 optlc_net_139:52 optlc_net_139:51 0.004776786 +62 optlc_net_139:50 optlc_net_139:49 0.002234375 +63 optlc_net_139:51 optlc_net_139:50 0.0045 +64 optlc_net_139:49 mux_top_track_0\/mux_l2_in_3_:A0 0.152 +65 optlc_net_139:60 optlc_net_139:59 0.0004888393 +66 optlc_net_139:61 optlc_net_139:60 0.0045 +67 optlc_net_139:61 optlc_net_139:58 0.006334822 +68 optlc_net_139:59 mux_left_track_3\/mux_l1_in_3_:A0 0.152 +69 optlc_net_139:76 optlc_net_139:75 0.002053571 +70 optlc_net_139:76 optlc_net_139:48 0.003245536 +71 optlc_net_139:54 optlc_net_139:53 0.002013393 +72 optlc_net_139:56 optlc_net_139:55 0.0002834821 +73 optlc_net_139:64 optlc_net_139:63 0.002424107 +74 optlc_net_139:65 optlc_net_139:64 0.0003035715 +75 optlc_net_139:36 optlc_net_139:35 0.0005669643 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005306724 //LENGTH 4.510 LUMPCC 7.661311e-05 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 76.645 63.580 +*I mux_left_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 80.865 63.580 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 80.828 63.580 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 76.683 63.580 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002260297 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002260297 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_0_sram[2]:4 3.830656e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_0_sram[2]:5 3.830656e-05 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003700893 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0] 0.003302385 //LENGTH 24.560 LUMPCC 0.0002846389 DR + +*CONN +*I mux_left_track_13\/mux_l3_in_0_:X O *L 0 *C 26.855 47.940 +*I mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.230 47.770 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 5.230 47.808 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 5.230 48.280 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 10.075 48.280 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 10.120 48.235 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 10.120 47.657 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 10.128 47.600 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 14.713 47.600 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 14.720 47.600 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 14.720 47.940 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 14.765 47.940 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 26.818 47.940 + +*CAP +0 mux_left_track_13\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.640443e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0004085053 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003621009 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.79144e-05 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.79144e-05 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003008023 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0003008023 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 6.047643e-05 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 5.600606e-05 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0006824099 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0006824099 +13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size9_0_sram[1]:9 7.589106e-08 +14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_tree_tapbuf_size9_0_sram[1]:16 0.0001422436 +15 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_tree_tapbuf_size9_0_sram[1]:10 7.589106e-08 +16 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_tree_tapbuf_size9_0_sram[1]:17 0.0001422436 + +*RES +0 mux_left_track_13\/mux_l3_in_0_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.004325893 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000515625 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0007183166 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0045 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001634615 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.01076116 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004218751 + +*END + +*D_NET ropt_net_206 0.0006862875 //LENGTH 5.030 LUMPCC 8.906523e-05 DR + +*CONN +*I ropt_mt_inst_769:X O *L 0 *C 48.760 126.480 +*I ropt_mt_inst_844:A I *L 0.001766 *C 50.140 123.760 +*N ropt_net_206:2 *C 50.102 123.760 +*N ropt_net_206:3 *C 49.265 123.760 +*N ropt_net_206:4 *C 49.220 123.805 +*N ropt_net_206:5 *C 49.220 126.435 +*N ropt_net_206:6 *C 49.175 126.480 +*N ropt_net_206:7 *C 48.797 126.480 + +*CAP +0 ropt_mt_inst_769:X 1e-06 +1 ropt_mt_inst_844:A 1e-06 +2 ropt_net_206:2 6.420344e-05 +3 ropt_net_206:3 6.420344e-05 +4 ropt_net_206:4 0.0001745056 +5 ropt_net_206:5 0.0001745056 +6 ropt_net_206:6 5.890207e-05 +7 ropt_net_206:7 5.890207e-05 +8 ropt_net_206:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.453261e-05 +9 ropt_net_206:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.453261e-05 + +*RES +0 ropt_mt_inst_769:X ropt_net_206:7 0.152 +1 ropt_net_206:7 ropt_net_206:6 0.0003370536 +2 ropt_net_206:6 ropt_net_206:5 0.0045 +3 ropt_net_206:5 ropt_net_206:4 0.002348214 +4 ropt_net_206:3 ropt_net_206:2 0.0007477679 +5 ropt_net_206:4 ropt_net_206:3 0.0045 +6 ropt_net_206:2 ropt_mt_inst_844:A 0.152 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00163828 //LENGTH 11.955 LUMPCC 0.0002553531 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 57.675 67.320 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 46.365 66.980 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 46.365 66.980 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 46.460 67.320 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 57.638 67.320 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.764006e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0006756629 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0006476237 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[0]:4 5.604104e-06 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[0]:9 8.587404e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_4_sram[0]:11 3.61984e-05 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[0]:9 5.604104e-06 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[0]:10 3.61984e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_4_sram[0]:11 8.587404e-05 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.009979911 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET chany_bottom_out[0] 0.001674853 //LENGTH 12.590 LUMPCC 0.0002039836 DR + +*CONN +*I ropt_mt_inst_772:X O *L 0 *C 92.655 3.740 +*P chany_bottom_out[0] O *L 0.7423 *C 83.260 1.290 +*N chany_bottom_out[0]:2 *C 83.260 3.355 +*N chany_bottom_out[0]:3 *C 83.305 3.400 +*N chany_bottom_out[0]:4 *C 85.560 3.400 +*N chany_bottom_out[0]:5 *C 85.560 3.740 +*N chany_bottom_out[0]:6 *C 92.618 3.740 + +*CAP +0 ropt_mt_inst_772:X 1e-06 +1 chany_bottom_out[0] 0.0001501265 +2 chany_bottom_out[0]:2 0.0001501265 +3 chany_bottom_out[0]:3 0.0001387221 +4 chany_bottom_out[0]:4 0.0001636321 +5 chany_bottom_out[0]:5 0.0004460863 +6 chany_bottom_out[0]:6 0.0004211763 +7 chany_bottom_out[0]:6 ropt_net_182:9 3.962398e-05 +8 chany_bottom_out[0]:3 ropt_net_182:8 9.735522e-07 +9 chany_bottom_out[0]:3 ropt_net_182:4 6.139425e-05 +10 chany_bottom_out[0]:4 ropt_net_182:5 6.139425e-05 +11 chany_bottom_out[0]:4 ropt_net_182:9 9.735522e-07 +12 chany_bottom_out[0]:5 ropt_net_182:8 3.962398e-05 + +*RES +0 ropt_mt_inst_772:X chany_bottom_out[0]:6 0.152 +1 chany_bottom_out[0]:6 chany_bottom_out[0]:5 0.00630134 +2 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +3 chany_bottom_out[0]:2 chany_bottom_out[0] 0.00184375 +4 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002013393 +5 chany_bottom_out[0]:5 chany_bottom_out[0]:4 0.0003035715 + +*END + +*D_NET ropt_net_165 0.001338742 //LENGTH 7.810 LUMPCC 0.0007825574 DR + +*CONN +*I FTB_16__15:X O *L 0 *C 66.240 12.580 +*I ropt_mt_inst_790:A I *L 0.001766 *C 59.340 12.240 +*N ropt_net_165:2 *C 59.378 12.240 +*N ropt_net_165:3 *C 59.800 12.240 +*N ropt_net_165:4 *C 59.800 12.580 +*N ropt_net_165:5 *C 66.203 12.580 + +*CAP +0 FTB_16__15:X 1e-06 +1 ropt_mt_inst_790:A 1e-06 +2 ropt_net_165:2 3.907799e-05 +3 ropt_net_165:3 6.67588e-05 +4 ropt_net_165:4 0.0002380141 +5 ropt_net_165:5 0.0002103334 +6 ropt_net_165:5 chany_top_in[16]:5 9.543475e-05 +7 ropt_net_165:4 chany_top_in[16]:4 9.543475e-05 +8 ropt_net_165:5 mux_tree_tapbuf_size8_2_sram[0]:7 4.869997e-05 +9 ropt_net_165:5 mux_tree_tapbuf_size8_2_sram[0]:12 0.0001755659 +10 ropt_net_165:2 mux_tree_tapbuf_size8_2_sram[0]:13 3.527347e-06 +11 ropt_net_165:3 mux_tree_tapbuf_size8_2_sram[0]:12 3.527347e-06 +12 ropt_net_165:4 mux_tree_tapbuf_size8_2_sram[0]:12 4.869997e-05 +13 ropt_net_165:4 mux_tree_tapbuf_size8_2_sram[0]:13 0.0001755659 +14 ropt_net_165:5 ropt_net_181:11 6.805074e-05 +15 ropt_net_165:4 ropt_net_181:10 6.805074e-05 + +*RES +0 FTB_16__15:X ropt_net_165:5 0.152 +1 ropt_net_165:5 ropt_net_165:4 0.005716518 +2 ropt_net_165:2 ropt_mt_inst_790:A 0.152 +3 ropt_net_165:3 ropt_net_165:2 0.0003772322 +4 ropt_net_165:4 ropt_net_165:3 0.0003035715 + +*END + +*D_NET ropt_net_202 0.001079114 //LENGTH 8.270 LUMPCC 8.910393e-05 DR + +*CONN +*I ropt_mt_inst_781:X O *L 0 *C 4.140 90.780 +*I ropt_mt_inst_840:A I *L 0.001766 *C 3.220 88.400 +*N ropt_net_202:2 *C 3.220 88.400 +*N ropt_net_202:3 *C 3.220 88.740 +*N ropt_net_202:4 *C 1.425 88.740 +*N ropt_net_202:5 *C 1.380 88.740 +*N ropt_net_202:6 *C 1.380 90.735 +*N ropt_net_202:7 *C 1.425 90.780 +*N ropt_net_202:8 *C 4.103 90.780 + +*CAP +0 ropt_mt_inst_781:X 1e-06 +1 ropt_mt_inst_840:A 1e-06 +2 ropt_net_202:2 5.742585e-05 +3 ropt_net_202:3 0.0001522732 +4 ropt_net_202:4 0.0001241397 +5 ropt_net_202:5 0.0001833616 +6 ropt_net_202:6 0.0001528747 +7 ropt_net_202:7 0.0001589675 +8 ropt_net_202:8 0.0001589675 +9 ropt_net_202:7 chany_top_in[7]:3 4.455197e-05 +10 ropt_net_202:8 chany_top_in[7]:2 4.455197e-05 + +*RES +0 ropt_mt_inst_781:X ropt_net_202:8 0.152 +1 ropt_net_202:2 ropt_mt_inst_840:A 0.152 +2 ropt_net_202:4 ropt_net_202:3 0.001602679 +3 ropt_net_202:5 ropt_net_202:4 0.0045 +4 ropt_net_202:7 ropt_net_202:6 0.0045 +5 ropt_net_202:6 ropt_net_202:5 0.00178125 +6 ropt_net_202:8 ropt_net_202:7 0.002390625 +7 ropt_net_202:3 ropt_net_202:2 0.0003035715 + +*END + +*D_NET ropt_net_193 0.001167933 //LENGTH 8.540 LUMPCC 0.0002903831 DR + +*CONN +*I ropt_mt_inst_788:X O *L 0 *C 97.715 6.120 +*I ropt_mt_inst_825:A I *L 0.001767 *C 93.840 4.080 +*N ropt_net_193:2 *C 93.840 4.080 +*N ropt_net_193:3 *C 93.840 4.035 +*N ropt_net_193:4 *C 93.840 3.445 +*N ropt_net_193:5 *C 93.885 3.400 +*N ropt_net_193:6 *C 97.015 3.400 +*N ropt_net_193:7 *C 97.060 3.445 +*N ropt_net_193:8 *C 97.060 6.075 +*N ropt_net_193:9 *C 97.105 6.120 +*N ropt_net_193:10 *C 97.678 6.120 + +*CAP +0 ropt_mt_inst_788:X 1e-06 +1 ropt_mt_inst_825:A 1e-06 +2 ropt_net_193:2 3.214532e-05 +3 ropt_net_193:3 5.082843e-05 +4 ropt_net_193:4 5.082843e-05 +5 ropt_net_193:5 0.0001965721 +6 ropt_net_193:6 0.0001965721 +7 ropt_net_193:7 0.0001109723 +8 ropt_net_193:8 0.0001109723 +9 ropt_net_193:9 6.332945e-05 +10 ropt_net_193:10 6.332945e-05 +11 ropt_net_193:8 chany_bottom_out[4]:2 8.208929e-05 +12 ropt_net_193:7 chany_bottom_out[4] 8.208929e-05 +13 ropt_net_193:4 chany_bottom_out[4] 1.215788e-06 +14 ropt_net_193:3 chany_bottom_out[4]:2 1.215788e-06 +15 ropt_net_193:6 chany_bottom_out[10]:4 4.59228e-05 +16 ropt_net_193:5 chany_bottom_out[10]:3 4.59228e-05 +17 ropt_net_193:4 chany_bottom_out[10] 1.596367e-05 +18 ropt_net_193:3 chany_bottom_out[10]:2 1.596367e-05 + +*RES +0 ropt_mt_inst_788:X ropt_net_193:10 0.152 +1 ropt_net_193:10 ropt_net_193:9 0.0005111608 +2 ropt_net_193:9 ropt_net_193:8 0.0045 +3 ropt_net_193:8 ropt_net_193:7 0.002348214 +4 ropt_net_193:6 ropt_net_193:5 0.002794643 +5 ropt_net_193:7 ropt_net_193:6 0.0045 +6 ropt_net_193:5 ropt_net_193:4 0.0045 +7 ropt_net_193:4 ropt_net_193:3 0.0005267857 +8 ropt_net_193:2 ropt_mt_inst_825:A 0.152 +9 ropt_net_193:3 ropt_net_193:2 0.0045 + +*END + +*D_NET chany_top_out[13] 0.001187809 //LENGTH 7.830 LUMPCC 0.0003602738 DR + +*CONN +*I ropt_mt_inst_816:X O *L 0 *C 69.655 127.160 +*P chany_top_out[13] O *L 0.7423 *C 64.400 129.270 +*N chany_top_out[13]:2 *C 64.400 127.205 +*N chany_top_out[13]:3 *C 64.445 127.160 +*N chany_top_out[13]:4 *C 69.618 127.160 + +*CAP +0 ropt_mt_inst_816:X 1e-06 +1 chany_top_out[13] 0.0001319062 +2 chany_top_out[13]:2 0.0001319062 +3 chany_top_out[13]:3 0.0002813613 +4 chany_top_out[13]:4 0.0002813613 +5 chany_top_out[13]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001801369 +6 chany_top_out[13]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001801369 + +*RES +0 ropt_mt_inst_816:X chany_top_out[13]:4 0.152 +1 chany_top_out[13]:4 chany_top_out[13]:3 0.004618304 +2 chany_top_out[13]:3 chany_top_out[13]:2 0.0045 +3 chany_top_out[13]:2 chany_top_out[13] 0.00184375 + +*END + +*D_NET ropt_net_196 0.001960322 //LENGTH 12.755 LUMPCC 0.0006625295 DR + +*CONN +*I ropt_mt_inst_802:X O *L 0 *C 59.995 8.840 +*I ropt_mt_inst_828:A I *L 0.001766 *C 53.360 4.080 +*N ropt_net_196:2 *C 53.398 4.080 +*N ropt_net_196:3 *C 56.535 4.080 +*N ropt_net_196:4 *C 56.580 4.125 +*N ropt_net_196:5 *C 56.580 6.075 +*N ropt_net_196:6 *C 56.625 6.120 +*N ropt_net_196:7 *C 59.755 6.120 +*N ropt_net_196:8 *C 59.800 6.165 +*N ropt_net_196:9 *C 59.800 8.795 +*N ropt_net_196:10 *C 59.800 8.840 +*N ropt_net_196:11 *C 59.995 8.840 + +*CAP +0 ropt_mt_inst_802:X 1e-06 +1 ropt_mt_inst_828:A 1e-06 +2 ropt_net_196:2 0.0001121144 +3 ropt_net_196:3 0.0001121144 +4 ropt_net_196:4 0.0001029905 +5 ropt_net_196:5 0.0001029905 +6 ropt_net_196:6 0.0002254431 +7 ropt_net_196:7 0.0002254431 +8 ropt_net_196:8 0.0001493534 +9 ropt_net_196:9 0.0001493534 +10 ropt_net_196:10 5.992568e-05 +11 ropt_net_196:11 5.606435e-05 +12 ropt_net_196:6 chany_top_in[12]:4 1.49484e-05 +13 ropt_net_196:7 chany_top_in[12]:5 1.49484e-05 +14 ropt_net_196:8 chany_top_in[12]:7 6.434798e-05 +15 ropt_net_196:9 chany_top_in[12]:13 6.434798e-05 +16 ropt_net_196:2 bottom_right_grid_pin_1_[0]:5 9.787037e-06 +17 ropt_net_196:3 bottom_right_grid_pin_1_[0]:6 9.787037e-06 +18 ropt_net_196:4 bottom_right_grid_pin_1_[0]:7 9.109426e-06 +19 ropt_net_196:4 bottom_right_grid_pin_1_[0]:21 4.172049e-05 +20 ropt_net_196:5 bottom_right_grid_pin_1_[0]:8 9.109426e-06 +21 ropt_net_196:5 bottom_right_grid_pin_1_[0]:20 4.172049e-05 +22 ropt_net_196:2 chany_bottom_out[1]:4 0.000129236 +23 ropt_net_196:3 chany_bottom_out[1]:3 0.000129236 +24 ropt_net_196:2 chany_bottom_out[15]:3 6.21154e-05 +25 ropt_net_196:3 chany_bottom_out[15]:4 6.21154e-05 + +*RES +0 ropt_mt_inst_802:X ropt_net_196:11 0.152 +1 ropt_net_196:2 ropt_mt_inst_828:A 0.152 +2 ropt_net_196:3 ropt_net_196:2 0.002801339 +3 ropt_net_196:4 ropt_net_196:3 0.0045 +4 ropt_net_196:6 ropt_net_196:5 0.0045 +5 ropt_net_196:5 ropt_net_196:4 0.001741071 +6 ropt_net_196:7 ropt_net_196:6 0.002794643 +7 ropt_net_196:8 ropt_net_196:7 0.0045 +8 ropt_net_196:10 ropt_net_196:9 0.0045 +9 ropt_net_196:9 ropt_net_196:8 0.002348214 +10 ropt_net_196:11 ropt_net_196:10 0.0001059783 + +*END + +*D_NET chany_bottom_out[18] 0.002676476 //LENGTH 19.660 LUMPCC 0.0002240694 DR + +*CONN +*I ropt_mt_inst_841:X O *L 0 *C 85.755 6.460 +*P chany_bottom_out[18] O *L 0.7423 *C 73.140 1.290 +*N chany_bottom_out[18]:2 *C 73.140 3.343 +*N chany_bottom_out[18]:3 *C 73.148 3.400 +*N chany_bottom_out[18]:4 *C 81.860 3.400 +*N chany_bottom_out[18]:5 *C 81.880 3.408 +*N chany_bottom_out[18]:6 *C 81.880 4.753 +*N chany_bottom_out[18]:7 *C 81.900 4.760 +*N chany_bottom_out[18]:8 *C 85.093 4.760 +*N chany_bottom_out[18]:9 *C 85.100 4.817 +*N chany_bottom_out[18]:10 *C 85.100 6.415 +*N chany_bottom_out[18]:11 *C 85.145 6.460 +*N chany_bottom_out[18]:12 *C 85.718 6.460 + +*CAP +0 ropt_mt_inst_841:X 1e-06 +1 chany_bottom_out[18] 0.0001477333 +2 chany_bottom_out[18]:2 0.0001477333 +3 chany_bottom_out[18]:3 0.0005400502 +4 chany_bottom_out[18]:4 0.0005400502 +5 chany_bottom_out[18]:5 9.637426e-05 +6 chany_bottom_out[18]:6 9.637426e-05 +7 chany_bottom_out[18]:7 0.0002456356 +8 chany_bottom_out[18]:8 0.0002456356 +9 chany_bottom_out[18]:9 0.0001272064 +10 chany_bottom_out[18]:10 0.0001272064 +11 chany_bottom_out[18]:11 6.870377e-05 +12 chany_bottom_out[18]:12 6.870377e-05 +13 chany_bottom_out[18]:10 ropt_net_180:11 2.870491e-07 +14 chany_bottom_out[18]:9 ropt_net_180:10 2.870491e-07 +15 chany_bottom_out[18]:8 ropt_net_180:9 4.423884e-05 +16 chany_bottom_out[18]:7 ropt_net_180:8 4.423884e-05 +17 chany_bottom_out[18]:4 ropt_net_180:9 6.750881e-05 +18 chany_bottom_out[18]:3 ropt_net_180:8 6.750881e-05 + +*RES +0 ropt_mt_inst_841:X chany_bottom_out[18]:12 0.152 +1 chany_bottom_out[18]:12 chany_bottom_out[18]:11 0.0005111608 +2 chany_bottom_out[18]:11 chany_bottom_out[18]:10 0.0045 +3 chany_bottom_out[18]:10 chany_bottom_out[18]:9 0.001426339 +4 chany_bottom_out[18]:9 chany_bottom_out[18]:8 0.00341 +5 chany_bottom_out[18]:8 chany_bottom_out[18]:7 0.0005001583 +6 chany_bottom_out[18]:7 chany_bottom_out[18]:6 0.00341 +7 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.0002107167 +8 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.001364958 +9 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.00341 +10 chany_bottom_out[18]:2 chany_bottom_out[18] 0.001832589 +11 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.00341 + +*END + +*D_NET ropt_net_170 0.0005096066 //LENGTH 4.045 LUMPCC 0 DR + +*CONN +*I BUFT_P_126:X O *L 0 *C 89.240 121.720 +*I ropt_mt_inst_796:A I *L 0.001766 *C 90.620 123.760 +*N ropt_net_170:2 *C 90.583 123.760 +*N ropt_net_170:3 *C 89.285 123.760 +*N ropt_net_170:4 *C 89.240 123.715 +*N ropt_net_170:5 *C 89.240 121.765 +*N ropt_net_170:6 *C 89.240 121.720 + +*CAP +0 BUFT_P_126:X 1e-06 +1 ropt_mt_inst_796:A 1e-06 +2 ropt_net_170:2 0.0001089759 +3 ropt_net_170:3 0.0001089759 +4 ropt_net_170:4 0.0001275359 +5 ropt_net_170:5 0.0001275359 +6 ropt_net_170:6 3.458299e-05 + +*RES +0 BUFT_P_126:X ropt_net_170:6 0.152 +1 ropt_net_170:2 ropt_mt_inst_796:A 0.152 +2 ropt_net_170:3 ropt_net_170:2 0.001158482 +3 ropt_net_170:4 ropt_net_170:3 0.0045 +4 ropt_net_170:6 ropt_net_170:5 0.0045 +5 ropt_net_170:5 ropt_net_170:4 0.001741072 + +*END + +*D_NET chany_top_in[8] 0.02113289 //LENGTH 154.480 LUMPCC 0.007500909 DR + +*CONN +*P chany_top_in[8] I *L 0.29796 *C 72.220 129.235 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.705 52.700 +*I mux_bottom_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 62.925 45.220 +*I FTB_8__7:A I *L 0.001776 *C 52.440 9.520 +*N chany_top_in[8]:4 *C 52.440 9.520 +*N chany_top_in[8]:5 *C 52.440 9.565 +*N chany_top_in[8]:6 *C 52.440 11.503 +*N chany_top_in[8]:7 *C 52.448 11.560 +*N chany_top_in[8]:8 *C 63.013 11.560 +*N chany_top_in[8]:9 *C 63.020 11.617 +*N chany_top_in[8]:10 *C 62.925 45.220 +*N chany_top_in[8]:11 *C 63.020 45.220 +*N chany_top_in[8]:12 *C 63.020 52.983 +*N chany_top_in[8]:13 *C 63.028 53.040 +*N chany_top_in[8]:14 *C 82.705 52.700 +*N chany_top_in[8]:15 *C 82.800 53.040 +*N chany_top_in[8]:16 *C 73.645 53.040 +*N chany_top_in[8]:17 *C 73.600 53.040 +*N chany_top_in[8]:18 *C 73.593 53.040 +*N chany_top_in[8]:19 *C 73.600 53.047 +*N chany_top_in[8]:20 *C 73.600 102.875 +*N chany_top_in[8]:21 *C 73.600 122.393 +*N chany_top_in[8]:22 *C 73.580 122.400 +*N chany_top_in[8]:23 *C 72.228 122.400 +*N chany_top_in[8]:24 *C 72.220 122.458 + +*CAP +0 chany_top_in[8] 0.0003962697 +1 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_17\/mux_l1_in_0_:A1 1e-06 +3 FTB_8__7:A 1e-06 +4 chany_top_in[8]:4 3.339331e-05 +5 chany_top_in[8]:5 0.0001406001 +6 chany_top_in[8]:6 0.0001406001 +7 chany_top_in[8]:7 0.0005717808 +8 chany_top_in[8]:8 0.0005717808 +9 chany_top_in[8]:9 0.00161007 +10 chany_top_in[8]:10 3.478082e-05 +11 chany_top_in[8]:11 0.001961024 +12 chany_top_in[8]:12 0.0003156413 +13 chany_top_in[8]:13 0.0005072387 +14 chany_top_in[8]:14 5.248287e-05 +15 chany_top_in[8]:15 0.0004691321 +16 chany_top_in[8]:16 0.0004429414 +17 chany_top_in[8]:17 3.214098e-05 +18 chany_top_in[8]:18 0.0005072387 +19 chany_top_in[8]:19 0.001623282 +20 chany_top_in[8]:20 0.00261605 +21 chany_top_in[8]:21 0.0009927683 +22 chany_top_in[8]:22 0.0001067472 +23 chany_top_in[8]:23 0.0001067472 +24 chany_top_in[8]:24 0.0003962697 +25 chany_top_in[8]:13 chany_bottom_in[12]:17 0.000570251 +26 chany_top_in[8]:18 chany_bottom_in[12]:18 0.000570251 +27 chany_top_in[8]:19 chany_bottom_in[16]:25 9.827306e-05 +28 chany_top_in[8]:19 chany_bottom_in[16]:16 0.0001473118 +29 chany_top_in[8]:19 chany_bottom_in[16]:23 0.0002398792 +30 chany_top_in[8]:21 chany_bottom_in[16]:9 0.0001041667 +31 chany_top_in[8]:20 chany_bottom_in[16]:9 0.0001473118 +32 chany_top_in[8]:20 chany_bottom_in[16]:16 0.000344046 +33 chany_top_in[8]:20 chany_bottom_in[16]:24 9.827306e-05 +34 chany_top_in[8]:7 prog_clk[0]:181 0.0004908107 +35 chany_top_in[8]:9 prog_clk[0]:156 1.219364e-05 +36 chany_top_in[8]:9 prog_clk[0]:157 1.302757e-05 +37 chany_top_in[8]:9 prog_clk[0]:145 8.814656e-05 +38 chany_top_in[8]:9 prog_clk[0]:152 2.579453e-05 +39 chany_top_in[8]:9 prog_clk[0]:175 3.604443e-06 +40 chany_top_in[8]:9 prog_clk[0]:155 6.089425e-06 +41 chany_top_in[8]:8 prog_clk[0]:176 0.0004908107 +42 chany_top_in[8]:12 prog_clk[0]:140 0.0001199852 +43 chany_top_in[8]:12 prog_clk[0]:144 6.711658e-05 +44 chany_top_in[8]:13 prog_clk[0]:139 0.0001117078 +45 chany_top_in[8]:11 prog_clk[0]:156 6.089425e-06 +46 chany_top_in[8]:11 prog_clk[0]:145 6.711658e-05 +47 chany_top_in[8]:11 prog_clk[0]:148 2.579453e-05 +48 chany_top_in[8]:11 prog_clk[0]:144 0.0002081317 +49 chany_top_in[8]:11 prog_clk[0]:152 1.219364e-05 +50 chany_top_in[8]:11 prog_clk[0]:174 3.604443e-06 +51 chany_top_in[8]:11 prog_clk[0]:158 1.302757e-05 +52 chany_top_in[8]:18 prog_clk[0]:138 0.0001117078 +53 chany_top_in[8]:19 chanx_left_in[11]:10 0.001388901 +54 chany_top_in[8]:20 chanx_left_in[11]:9 0.001388901 +55 chany_top_in[8]:9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 7.62726e-05 +56 chany_top_in[8]:11 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 7.62726e-05 +57 chany_top_in[8]:16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001869229 +58 chany_top_in[8]:15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001869229 + +*RES +0 chany_top_in[8] chany_top_in[8]:24 0.006051339 +1 chany_top_in[8]:4 FTB_8__7:A 0.152 +2 chany_top_in[8]:5 chany_top_in[8]:4 0.0045 +3 chany_top_in[8]:6 chany_top_in[8]:5 0.001729911 +4 chany_top_in[8]:7 chany_top_in[8]:6 0.00341 +5 chany_top_in[8]:9 chany_top_in[8]:8 0.00341 +6 chany_top_in[8]:8 chany_top_in[8]:7 0.001655183 +7 chany_top_in[8]:12 chany_top_in[8]:11 0.006930804 +8 chany_top_in[8]:13 chany_top_in[8]:12 0.00341 +9 chany_top_in[8]:10 mux_bottom_track_17\/mux_l1_in_0_:A1 0.152 +10 chany_top_in[8]:11 chany_top_in[8]:10 0.0045 +11 chany_top_in[8]:11 chany_top_in[8]:9 0.03000224 +12 chany_top_in[8]:17 chany_top_in[8]:16 0.0045 +13 chany_top_in[8]:18 chany_top_in[8]:17 0.00341 +14 chany_top_in[8]:18 chany_top_in[8]:13 0.001655183 +15 chany_top_in[8]:16 chany_top_in[8]:15 0.008174107 +16 chany_top_in[8]:14 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +17 chany_top_in[8]:19 chany_top_in[8]:18 0.00341 +18 chany_top_in[8]:22 chany_top_in[8]:21 0.00341 +19 chany_top_in[8]:21 chany_top_in[8]:20 0.003057742 +20 chany_top_in[8]:24 chany_top_in[8]:23 0.00341 +21 chany_top_in[8]:23 chany_top_in[8]:22 0.0002118916 +22 chany_top_in[8]:15 chany_top_in[8]:14 0.0003035715 +23 chany_top_in[8]:20 chany_top_in[8]:19 0.007806308 + +*END + +*D_NET left_top_grid_pin_46_[0] 0.007828213 //LENGTH 61.495 LUMPCC 0.0005047773 DR + +*CONN +*P left_top_grid_pin_46_[0] I *L 0.29796 *C 2.300 102.070 +*I mux_left_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 14.435 91.460 +*I mux_left_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 15.815 76.840 +*I mux_left_track_17\/mux_l1_in_1_:A1 I *L 0.00198 *C 20.240 61.540 +*N left_top_grid_pin_46_[0]:4 *C 20.203 61.540 +*N left_top_grid_pin_46_[0]:5 *C 16.145 61.540 +*N left_top_grid_pin_46_[0]:6 *C 16.100 61.585 +*N left_top_grid_pin_46_[0]:7 *C 16.100 76.840 +*N left_top_grid_pin_46_[0]:8 *C 15.815 76.840 +*N left_top_grid_pin_46_[0]:9 *C 15.640 76.840 +*N left_top_grid_pin_46_[0]:10 *C 15.640 76.840 +*N left_top_grid_pin_46_[0]:11 *C 15.640 91.415 +*N left_top_grid_pin_46_[0]:12 *C 15.595 91.460 +*N left_top_grid_pin_46_[0]:13 *C 14.435 91.460 +*N left_top_grid_pin_46_[0]:14 *C 1.885 91.460 +*N left_top_grid_pin_46_[0]:15 *C 1.840 91.505 +*N left_top_grid_pin_46_[0]:16 *C 1.840 99.620 +*N left_top_grid_pin_46_[0]:17 *C 2.300 99.620 + +*CAP +0 left_top_grid_pin_46_[0] 0.0001375588 +1 mux_left_track_1\/mux_l1_in_2_:A0 1e-06 +2 mux_left_track_5\/mux_l1_in_2_:A0 1e-06 +3 mux_left_track_17\/mux_l1_in_1_:A1 1e-06 +4 left_top_grid_pin_46_[0]:4 0.000268754 +5 left_top_grid_pin_46_[0]:5 0.000268754 +6 left_top_grid_pin_46_[0]:6 0.0009719632 +7 left_top_grid_pin_46_[0]:7 0.00100762 +8 left_top_grid_pin_46_[0]:8 5.513688e-05 +9 left_top_grid_pin_46_[0]:9 5.991903e-05 +10 left_top_grid_pin_46_[0]:10 0.0009851727 +11 left_top_grid_pin_46_[0]:11 0.0009495158 +12 left_top_grid_pin_46_[0]:12 8.237614e-05 +13 left_top_grid_pin_46_[0]:13 0.0008857655 +14 left_top_grid_pin_46_[0]:14 0.0007746031 +15 left_top_grid_pin_46_[0]:15 0.0003420822 +16 left_top_grid_pin_46_[0]:16 0.0003678686 +17 left_top_grid_pin_46_[0]:17 0.0001633453 +18 left_top_grid_pin_46_[0]:13 chany_top_in[7]:2 4.455197e-05 +19 left_top_grid_pin_46_[0]:14 chany_top_in[7]:3 4.455197e-05 +20 left_top_grid_pin_46_[0]:15 chany_top_in[7]:4 0.0002078367 +21 left_top_grid_pin_46_[0]:16 chany_top_in[7]:5 0.0002078367 + +*RES +0 left_top_grid_pin_46_[0] left_top_grid_pin_46_[0]:17 0.0021875 +1 left_top_grid_pin_46_[0]:12 left_top_grid_pin_46_[0]:11 0.0045 +2 left_top_grid_pin_46_[0]:11 left_top_grid_pin_46_[0]:10 0.01301339 +3 left_top_grid_pin_46_[0]:4 mux_left_track_17\/mux_l1_in_1_:A1 0.152 +4 left_top_grid_pin_46_[0]:5 left_top_grid_pin_46_[0]:4 0.003622768 +5 left_top_grid_pin_46_[0]:6 left_top_grid_pin_46_[0]:5 0.0045 +6 left_top_grid_pin_46_[0]:13 mux_left_track_1\/mux_l1_in_2_:A0 0.152 +7 left_top_grid_pin_46_[0]:13 left_top_grid_pin_46_[0]:12 0.001035714 +8 left_top_grid_pin_46_[0]:9 left_top_grid_pin_46_[0]:8 9.510871e-05 +9 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:9 0.0045 +10 left_top_grid_pin_46_[0]:10 left_top_grid_pin_46_[0]:7 0.0004107143 +11 left_top_grid_pin_46_[0]:8 mux_left_track_5\/mux_l1_in_2_:A0 0.152 +12 left_top_grid_pin_46_[0]:14 left_top_grid_pin_46_[0]:13 0.01120536 +13 left_top_grid_pin_46_[0]:15 left_top_grid_pin_46_[0]:14 0.0045 +14 left_top_grid_pin_46_[0]:16 left_top_grid_pin_46_[0]:15 0.007245536 +15 left_top_grid_pin_46_[0]:17 left_top_grid_pin_46_[0]:16 0.0004107143 +16 left_top_grid_pin_46_[0]:7 left_top_grid_pin_46_[0]:6 0.01362054 + +*END + +*D_NET chanx_left_out[10] 0.001106106 //LENGTH 8.740 LUMPCC 0 DR + +*CONN +*I mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 58.820 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 53.040 +*N chanx_left_out[10]:2 *C 3.673 53.040 +*N chanx_left_out[10]:3 *C 3.680 53.098 +*N chanx_left_out[10]:4 *C 3.680 58.775 +*N chanx_left_out[10]:5 *C 3.625 58.820 + +*CAP +0 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[10] 0.0001866484 +2 chanx_left_out[10]:2 0.0001866484 +3 chanx_left_out[10]:3 0.0003518861 +4 chanx_left_out[10]:4 0.0003518861 +5 chanx_left_out[10]:5 2.80371e-05 + +*RES +0 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[10]:5 0.152 +1 chanx_left_out[10]:5 chanx_left_out[10]:4 0.0045 +2 chanx_left_out[10]:4 chanx_left_out[10]:3 0.005069197 +3 chanx_left_out[10]:3 chanx_left_out[10]:2 0.00341 +4 chanx_left_out[10]:2 chanx_left_out[10] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[0] 0.008554455 //LENGTH 66.625 LUMPCC 0.0004862382 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.525 102.000 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 44.335 104.380 +*I mux_top_track_4\/mux_l1_in_1_:S I *L 0.00357 *C 44.520 112.200 +*I mux_top_track_4\/mux_l1_in_0_:S I *L 0.00357 *C 43.700 115.770 +*I mux_top_track_4\/mux_l1_in_3_:S I *L 0.00357 *C 46.360 110.455 +*I mux_top_track_4\/mux_l1_in_2_:S I *L 0.00357 *C 50.960 117.640 +*I mux_top_track_4\/mux_l1_in_6_:S I *L 0.00357 *C 41.300 95.880 +*I mux_top_track_4\/mux_l1_in_5_:S I *L 0.00357 *C 48.660 99.575 +*I mux_top_track_4\/mux_l1_in_4_:S I *L 0.00357 *C 63.120 102.000 +*N mux_tree_tapbuf_size14_0_sram[0]:9 *C 63.083 102.000 +*N mux_tree_tapbuf_size14_0_sram[0]:10 *C 48.660 99.575 +*N mux_tree_tapbuf_size14_0_sram[0]:11 *C 48.660 99.915 +*N mux_tree_tapbuf_size14_0_sram[0]:12 *C 48.205 99.960 +*N mux_tree_tapbuf_size14_0_sram[0]:13 *C 41.337 95.880 +*N mux_tree_tapbuf_size14_0_sram[0]:14 *C 42.735 95.880 +*N mux_tree_tapbuf_size14_0_sram[0]:15 *C 42.780 95.925 +*N mux_tree_tapbuf_size14_0_sram[0]:16 *C 42.780 99.915 +*N mux_tree_tapbuf_size14_0_sram[0]:17 *C 42.825 99.960 +*N mux_tree_tapbuf_size14_0_sram[0]:18 *C 50.922 117.640 +*N mux_tree_tapbuf_size14_0_sram[0]:19 *C 47.885 117.640 +*N mux_tree_tapbuf_size14_0_sram[0]:20 *C 47.840 117.595 +*N mux_tree_tapbuf_size14_0_sram[0]:21 *C 47.840 110.885 +*N mux_tree_tapbuf_size14_0_sram[0]:22 *C 47.795 110.840 +*N mux_tree_tapbuf_size14_0_sram[0]:23 *C 46.360 110.840 +*N mux_tree_tapbuf_size14_0_sram[0]:24 *C 46.360 110.530 +*N mux_tree_tapbuf_size14_0_sram[0]:25 *C 46.360 110.455 +*N mux_tree_tapbuf_size14_0_sram[0]:26 *C 46.303 110.160 +*N mux_tree_tapbuf_size14_0_sram[0]:27 *C 43.663 115.663 +*N mux_tree_tapbuf_size14_0_sram[0]:28 *C 43.285 115.600 +*N mux_tree_tapbuf_size14_0_sram[0]:29 *C 43.240 115.555 +*N mux_tree_tapbuf_size14_0_sram[0]:30 *C 44.483 112.200 +*N mux_tree_tapbuf_size14_0_sram[0]:31 *C 43.285 112.200 +*N mux_tree_tapbuf_size14_0_sram[0]:32 *C 43.240 112.200 +*N mux_tree_tapbuf_size14_0_sram[0]:33 *C 43.240 110.205 +*N mux_tree_tapbuf_size14_0_sram[0]:34 *C 43.285 110.160 +*N mux_tree_tapbuf_size14_0_sram[0]:35 *C 44.620 110.160 +*N mux_tree_tapbuf_size14_0_sram[0]:36 *C 44.620 110.115 +*N mux_tree_tapbuf_size14_0_sram[0]:37 *C 44.335 104.380 +*N mux_tree_tapbuf_size14_0_sram[0]:38 *C 44.620 104.380 +*N mux_tree_tapbuf_size14_0_sram[0]:39 *C 44.620 104.380 +*N mux_tree_tapbuf_size14_0_sram[0]:40 *C 45.080 104.380 +*N mux_tree_tapbuf_size14_0_sram[0]:41 *C 45.080 100.005 +*N mux_tree_tapbuf_size14_0_sram[0]:42 *C 45.080 99.960 +*N mux_tree_tapbuf_size14_0_sram[0]:43 *C 48.330 99.930 +*N mux_tree_tapbuf_size14_0_sram[0]:44 *C 48.300 100.005 +*N mux_tree_tapbuf_size14_0_sram[0]:45 *C 48.300 101.955 +*N mux_tree_tapbuf_size14_0_sram[0]:46 *C 48.345 102.000 +*N mux_tree_tapbuf_size14_0_sram[0]:47 *C 49.525 102.000 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_4\/mux_l1_in_1_:S 1e-06 +3 mux_top_track_4\/mux_l1_in_0_:S 1e-06 +4 mux_top_track_4\/mux_l1_in_3_:S 1e-06 +5 mux_top_track_4\/mux_l1_in_2_:S 1e-06 +6 mux_top_track_4\/mux_l1_in_6_:S 1e-06 +7 mux_top_track_4\/mux_l1_in_5_:S 1e-06 +8 mux_top_track_4\/mux_l1_in_4_:S 1e-06 +9 mux_tree_tapbuf_size14_0_sram[0]:9 0.0006639561 +10 mux_tree_tapbuf_size14_0_sram[0]:10 6.178286e-05 +11 mux_tree_tapbuf_size14_0_sram[0]:11 6.150401e-05 +12 mux_tree_tapbuf_size14_0_sram[0]:12 9.908707e-06 +13 mux_tree_tapbuf_size14_0_sram[0]:13 0.0001198215 +14 mux_tree_tapbuf_size14_0_sram[0]:14 0.0001198215 +15 mux_tree_tapbuf_size14_0_sram[0]:15 0.0002391766 +16 mux_tree_tapbuf_size14_0_sram[0]:16 0.0002391766 +17 mux_tree_tapbuf_size14_0_sram[0]:17 0.0001525228 +18 mux_tree_tapbuf_size14_0_sram[0]:18 0.0002567024 +19 mux_tree_tapbuf_size14_0_sram[0]:19 0.0002567024 +20 mux_tree_tapbuf_size14_0_sram[0]:20 0.0004015153 +21 mux_tree_tapbuf_size14_0_sram[0]:21 0.0004015153 +22 mux_tree_tapbuf_size14_0_sram[0]:22 0.0001332098 +23 mux_tree_tapbuf_size14_0_sram[0]:23 0.0001563846 +24 mux_tree_tapbuf_size14_0_sram[0]:24 1.591073e-05 +25 mux_tree_tapbuf_size14_0_sram[0]:25 9.274745e-05 +26 mux_tree_tapbuf_size14_0_sram[0]:26 0.0001495529 +27 mux_tree_tapbuf_size14_0_sram[0]:27 4.345523e-05 +28 mux_tree_tapbuf_size14_0_sram[0]:28 4.345523e-05 +29 mux_tree_tapbuf_size14_0_sram[0]:29 0.0001978441 +30 mux_tree_tapbuf_size14_0_sram[0]:30 0.0001196468 +31 mux_tree_tapbuf_size14_0_sram[0]:31 0.0001196468 +32 mux_tree_tapbuf_size14_0_sram[0]:32 0.0003722646 +33 mux_tree_tapbuf_size14_0_sram[0]:33 0.0001428883 +34 mux_tree_tapbuf_size14_0_sram[0]:34 9.043969e-05 +35 mux_tree_tapbuf_size14_0_sram[0]:35 0.0002492173 +36 mux_tree_tapbuf_size14_0_sram[0]:36 0.0003421179 +37 mux_tree_tapbuf_size14_0_sram[0]:37 4.824748e-05 +38 mux_tree_tapbuf_size14_0_sram[0]:38 5.235385e-05 +39 mux_tree_tapbuf_size14_0_sram[0]:39 0.0003781576 +40 mux_tree_tapbuf_size14_0_sram[0]:40 0.0002982122 +41 mux_tree_tapbuf_size14_0_sram[0]:41 0.0002621725 +42 mux_tree_tapbuf_size14_0_sram[0]:42 0.0003972841 +43 mux_tree_tapbuf_size14_0_sram[0]:43 0.0002507339 +44 mux_tree_tapbuf_size14_0_sram[0]:44 0.000115484 +45 mux_tree_tapbuf_size14_0_sram[0]:45 0.000115484 +46 mux_tree_tapbuf_size14_0_sram[0]:46 9.606726e-05 +47 mux_tree_tapbuf_size14_0_sram[0]:47 0.0007921319 +48 mux_tree_tapbuf_size14_0_sram[0]:45 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 7.755597e-06 +49 mux_tree_tapbuf_size14_0_sram[0]:44 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 7.755597e-06 +50 mux_tree_tapbuf_size14_0_sram[0]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002353635 +51 mux_tree_tapbuf_size14_0_sram[0]:47 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002353635 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size14_0_sram[0]:47 0.152 +1 mux_tree_tapbuf_size14_0_sram[0]:46 mux_tree_tapbuf_size14_0_sram[0]:45 0.0045 +2 mux_tree_tapbuf_size14_0_sram[0]:45 mux_tree_tapbuf_size14_0_sram[0]:44 0.001741072 +3 mux_tree_tapbuf_size14_0_sram[0]:43 mux_tree_tapbuf_size14_0_sram[0]:42 0.002901786 +4 mux_tree_tapbuf_size14_0_sram[0]:43 mux_tree_tapbuf_size14_0_sram[0]:12 0.0001116072 +5 mux_tree_tapbuf_size14_0_sram[0]:43 mux_tree_tapbuf_size14_0_sram[0]:11 0.00020625 +6 mux_tree_tapbuf_size14_0_sram[0]:44 mux_tree_tapbuf_size14_0_sram[0]:43 0.0045 +7 mux_tree_tapbuf_size14_0_sram[0]:34 mux_tree_tapbuf_size14_0_sram[0]:33 0.0045 +8 mux_tree_tapbuf_size14_0_sram[0]:33 mux_tree_tapbuf_size14_0_sram[0]:32 0.00178125 +9 mux_tree_tapbuf_size14_0_sram[0]:35 mux_tree_tapbuf_size14_0_sram[0]:34 0.001191964 +10 mux_tree_tapbuf_size14_0_sram[0]:35 mux_tree_tapbuf_size14_0_sram[0]:26 0.001502232 +11 mux_tree_tapbuf_size14_0_sram[0]:36 mux_tree_tapbuf_size14_0_sram[0]:35 0.0045 +12 mux_tree_tapbuf_size14_0_sram[0]:25 mux_top_track_4\/mux_l1_in_3_:S 0.152 +13 mux_tree_tapbuf_size14_0_sram[0]:25 mux_tree_tapbuf_size14_0_sram[0]:24 4.360465e-05 +14 mux_tree_tapbuf_size14_0_sram[0]:25 mux_tree_tapbuf_size14_0_sram[0]:23 0.00034375 +15 mux_tree_tapbuf_size14_0_sram[0]:42 mux_tree_tapbuf_size14_0_sram[0]:41 0.0045 +16 mux_tree_tapbuf_size14_0_sram[0]:42 mux_tree_tapbuf_size14_0_sram[0]:17 0.002013393 +17 mux_tree_tapbuf_size14_0_sram[0]:41 mux_tree_tapbuf_size14_0_sram[0]:40 0.00390625 +18 mux_tree_tapbuf_size14_0_sram[0]:17 mux_tree_tapbuf_size14_0_sram[0]:16 0.0045 +19 mux_tree_tapbuf_size14_0_sram[0]:16 mux_tree_tapbuf_size14_0_sram[0]:15 0.003562501 +20 mux_tree_tapbuf_size14_0_sram[0]:14 mux_tree_tapbuf_size14_0_sram[0]:13 0.001247768 +21 mux_tree_tapbuf_size14_0_sram[0]:15 mux_tree_tapbuf_size14_0_sram[0]:14 0.0045 +22 mux_tree_tapbuf_size14_0_sram[0]:13 mux_top_track_4\/mux_l1_in_6_:S 0.152 +23 mux_tree_tapbuf_size14_0_sram[0]:10 mux_top_track_4\/mux_l1_in_5_:S 0.152 +24 mux_tree_tapbuf_size14_0_sram[0]:9 mux_top_track_4\/mux_l1_in_4_:S 0.152 +25 mux_tree_tapbuf_size14_0_sram[0]:27 mux_top_track_4\/mux_l1_in_0_:S 0.152 +26 mux_tree_tapbuf_size14_0_sram[0]:28 mux_tree_tapbuf_size14_0_sram[0]:27 0.0003370536 +27 mux_tree_tapbuf_size14_0_sram[0]:29 mux_tree_tapbuf_size14_0_sram[0]:28 0.0045 +28 mux_tree_tapbuf_size14_0_sram[0]:31 mux_tree_tapbuf_size14_0_sram[0]:30 0.001069196 +29 mux_tree_tapbuf_size14_0_sram[0]:32 mux_tree_tapbuf_size14_0_sram[0]:31 0.0045 +30 mux_tree_tapbuf_size14_0_sram[0]:32 mux_tree_tapbuf_size14_0_sram[0]:29 0.002995536 +31 mux_tree_tapbuf_size14_0_sram[0]:30 mux_top_track_4\/mux_l1_in_1_:S 0.152 +32 mux_tree_tapbuf_size14_0_sram[0]:22 mux_tree_tapbuf_size14_0_sram[0]:21 0.0045 +33 mux_tree_tapbuf_size14_0_sram[0]:21 mux_tree_tapbuf_size14_0_sram[0]:20 0.005991072 +34 mux_tree_tapbuf_size14_0_sram[0]:19 mux_tree_tapbuf_size14_0_sram[0]:18 0.002712054 +35 mux_tree_tapbuf_size14_0_sram[0]:20 mux_tree_tapbuf_size14_0_sram[0]:19 0.0045 +36 mux_tree_tapbuf_size14_0_sram[0]:18 mux_top_track_4\/mux_l1_in_2_:S 0.152 +37 mux_tree_tapbuf_size14_0_sram[0]:38 mux_tree_tapbuf_size14_0_sram[0]:37 0.0001548913 +38 mux_tree_tapbuf_size14_0_sram[0]:39 mux_tree_tapbuf_size14_0_sram[0]:38 0.0045 +39 mux_tree_tapbuf_size14_0_sram[0]:39 mux_tree_tapbuf_size14_0_sram[0]:36 0.005120535 +40 mux_tree_tapbuf_size14_0_sram[0]:37 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +41 mux_tree_tapbuf_size14_0_sram[0]:47 mux_tree_tapbuf_size14_0_sram[0]:46 0.001053571 +42 mux_tree_tapbuf_size14_0_sram[0]:47 mux_tree_tapbuf_size14_0_sram[0]:9 0.01210491 +43 mux_tree_tapbuf_size14_0_sram[0]:26 mux_tree_tapbuf_size14_0_sram[0]:25 0.0001715116 +44 mux_tree_tapbuf_size14_0_sram[0]:23 mux_tree_tapbuf_size14_0_sram[0]:22 0.00128125 +45 mux_tree_tapbuf_size14_0_sram[0]:11 mux_tree_tapbuf_size14_0_sram[0]:10 0.0003035715 +46 mux_tree_tapbuf_size14_0_sram[0]:40 mux_tree_tapbuf_size14_0_sram[0]:39 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_2_ccff_tail[0] 0.0009862204 //LENGTH 7.960 LUMPCC 0.0001213479 DR + +*CONN +*I mem_bottom_track_33\/FTB_17__49:X O *L 0 *C 13.565 42.500 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 12.135 47.940 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 *C 12.135 47.940 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 *C 11.960 47.940 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 *C 11.960 47.895 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 *C 11.960 42.545 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 *C 12.005 42.500 +*N mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 *C 13.527 42.500 + +*CAP +0 mem_bottom_track_33\/FTB_17__49:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 5.062689e-05 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 5.496379e-05 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.000269011 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.000269011 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.00010963 +7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.00010963 +8 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 prog_clk[0]:516 5.019489e-06 +9 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 prog_clk[0]:521 5.565445e-05 +10 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 prog_clk[0]:517 5.019489e-06 +11 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 prog_clk[0]:522 5.565445e-05 + +*RES +0 mem_bottom_track_33\/FTB_17__49:X mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:4 0.004776786 +6 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_2_ccff_tail[0]:6 0.001359375 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[1] 0.004137663 //LENGTH 29.730 LUMPCC 0 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 26.525 80.580 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 6.160 80.580 +*I mux_left_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 13.440 83.255 +*I mux_left_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 29.080 80.240 +*N mux_tree_tapbuf_size7_4_sram[1]:4 *C 29.043 80.240 +*N mux_tree_tapbuf_size7_4_sram[1]:5 *C 27.600 80.240 +*N mux_tree_tapbuf_size7_4_sram[1]:6 *C 27.600 80.580 +*N mux_tree_tapbuf_size7_4_sram[1]:7 *C 13.440 83.255 +*N mux_tree_tapbuf_size7_4_sram[1]:8 *C 13.340 82.960 +*N mux_tree_tapbuf_size7_4_sram[1]:9 *C 13.340 82.915 +*N mux_tree_tapbuf_size7_4_sram[1]:10 *C 6.198 80.580 +*N mux_tree_tapbuf_size7_4_sram[1]:11 *C 13.295 80.580 +*N mux_tree_tapbuf_size7_4_sram[1]:12 *C 13.340 80.625 +*N mux_tree_tapbuf_size7_4_sram[1]:13 *C 13.340 82.280 +*N mux_tree_tapbuf_size7_4_sram[1]:14 *C 13.385 82.280 +*N mux_tree_tapbuf_size7_4_sram[1]:15 *C 25.715 82.280 +*N mux_tree_tapbuf_size7_4_sram[1]:16 *C 25.760 82.235 +*N mux_tree_tapbuf_size7_4_sram[1]:17 *C 25.760 80.625 +*N mux_tree_tapbuf_size7_4_sram[1]:18 *C 25.805 80.580 +*N mux_tree_tapbuf_size7_4_sram[1]:19 *C 26.525 80.580 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_left_track_3\/mux_l2_in_1_:S 1e-06 +3 mux_left_track_3\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_4_sram[1]:4 0.0001060943 +5 mux_tree_tapbuf_size7_4_sram[1]:5 0.0001314449 +6 mux_tree_tapbuf_size7_4_sram[1]:6 0.000100242 +7 mux_tree_tapbuf_size7_4_sram[1]:7 6.791428e-05 +8 mux_tree_tapbuf_size7_4_sram[1]:8 6.94324e-05 +9 mux_tree_tapbuf_size7_4_sram[1]:9 5.498093e-05 +10 mux_tree_tapbuf_size7_4_sram[1]:10 0.0004725645 +11 mux_tree_tapbuf_size7_4_sram[1]:11 0.0004725645 +12 mux_tree_tapbuf_size7_4_sram[1]:12 0.0001193297 +13 mux_tree_tapbuf_size7_4_sram[1]:13 0.0002093666 +14 mux_tree_tapbuf_size7_4_sram[1]:14 0.0009515552 +15 mux_tree_tapbuf_size7_4_sram[1]:15 0.0009515552 +16 mux_tree_tapbuf_size7_4_sram[1]:16 0.0001121231 +17 mux_tree_tapbuf_size7_4_sram[1]:17 0.0001121231 +18 mux_tree_tapbuf_size7_4_sram[1]:18 5.137096e-05 +19 mux_tree_tapbuf_size7_4_sram[1]:19 0.0001510012 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_4_sram[1]:19 0.152 +1 mux_tree_tapbuf_size7_4_sram[1]:10 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +2 mux_tree_tapbuf_size7_4_sram[1]:11 mux_tree_tapbuf_size7_4_sram[1]:10 0.006337054 +3 mux_tree_tapbuf_size7_4_sram[1]:12 mux_tree_tapbuf_size7_4_sram[1]:11 0.0045 +4 mux_tree_tapbuf_size7_4_sram[1]:14 mux_tree_tapbuf_size7_4_sram[1]:13 0.0045 +5 mux_tree_tapbuf_size7_4_sram[1]:13 mux_tree_tapbuf_size7_4_sram[1]:12 0.001477679 +6 mux_tree_tapbuf_size7_4_sram[1]:13 mux_tree_tapbuf_size7_4_sram[1]:9 0.0005669643 +7 mux_tree_tapbuf_size7_4_sram[1]:15 mux_tree_tapbuf_size7_4_sram[1]:14 0.01100893 +8 mux_tree_tapbuf_size7_4_sram[1]:16 mux_tree_tapbuf_size7_4_sram[1]:15 0.0045 +9 mux_tree_tapbuf_size7_4_sram[1]:18 mux_tree_tapbuf_size7_4_sram[1]:17 0.0045 +10 mux_tree_tapbuf_size7_4_sram[1]:17 mux_tree_tapbuf_size7_4_sram[1]:16 0.0014375 +11 mux_tree_tapbuf_size7_4_sram[1]:7 mux_left_track_3\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size7_4_sram[1]:8 mux_tree_tapbuf_size7_4_sram[1]:7 0.0001715116 +13 mux_tree_tapbuf_size7_4_sram[1]:9 mux_tree_tapbuf_size7_4_sram[1]:8 0.0045 +14 mux_tree_tapbuf_size7_4_sram[1]:19 mux_tree_tapbuf_size7_4_sram[1]:18 0.0006428572 +15 mux_tree_tapbuf_size7_4_sram[1]:19 mux_tree_tapbuf_size7_4_sram[1]:6 0.0009598215 +16 mux_tree_tapbuf_size7_4_sram[1]:4 mux_left_track_3\/mux_l2_in_0_:S 0.152 +17 mux_tree_tapbuf_size7_4_sram[1]:6 mux_tree_tapbuf_size7_4_sram[1]:5 0.0003035714 +18 mux_tree_tapbuf_size7_4_sram[1]:5 mux_tree_tapbuf_size7_4_sram[1]:4 0.001287946 + +*END + +*D_NET mux_tree_tapbuf_size8_2_sram[0] 0.00300355 //LENGTH 21.115 LUMPCC 0.0004555863 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 57.245 12.920 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 62.735 15.300 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 70.940 14.280 +*N mux_tree_tapbuf_size8_2_sram[0]:3 *C 70.903 14.280 +*N mux_tree_tapbuf_size8_2_sram[0]:4 *C 70.425 14.280 +*N mux_tree_tapbuf_size8_2_sram[0]:5 *C 70.380 14.235 +*N mux_tree_tapbuf_size8_2_sram[0]:6 *C 70.380 12.965 +*N mux_tree_tapbuf_size8_2_sram[0]:7 *C 70.335 12.920 +*N mux_tree_tapbuf_size8_2_sram[0]:8 *C 62.773 15.300 +*N mux_tree_tapbuf_size8_2_sram[0]:9 *C 64.815 15.300 +*N mux_tree_tapbuf_size8_2_sram[0]:10 *C 64.860 15.255 +*N mux_tree_tapbuf_size8_2_sram[0]:11 *C 64.860 12.965 +*N mux_tree_tapbuf_size8_2_sram[0]:12 *C 64.860 12.920 +*N mux_tree_tapbuf_size8_2_sram[0]:13 *C 57.283 12.920 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size8_2_sram[0]:3 5.83436e-05 +4 mux_tree_tapbuf_size8_2_sram[0]:4 5.83436e-05 +5 mux_tree_tapbuf_size8_2_sram[0]:5 0.0001046078 +6 mux_tree_tapbuf_size8_2_sram[0]:6 0.0001046078 +7 mux_tree_tapbuf_size8_2_sram[0]:7 0.0003627629 +8 mux_tree_tapbuf_size8_2_sram[0]:8 0.0001495758 +9 mux_tree_tapbuf_size8_2_sram[0]:9 0.0001495758 +10 mux_tree_tapbuf_size8_2_sram[0]:10 0.0001519042 +11 mux_tree_tapbuf_size8_2_sram[0]:11 0.0001519042 +12 mux_tree_tapbuf_size8_2_sram[0]:12 0.0008248094 +13 mux_tree_tapbuf_size8_2_sram[0]:13 0.0004285284 +14 mux_tree_tapbuf_size8_2_sram[0]:13 ropt_net_165:2 3.527347e-06 +15 mux_tree_tapbuf_size8_2_sram[0]:13 ropt_net_165:4 0.0001755659 +16 mux_tree_tapbuf_size8_2_sram[0]:12 ropt_net_165:5 0.0001755659 +17 mux_tree_tapbuf_size8_2_sram[0]:12 ropt_net_165:3 3.527347e-06 +18 mux_tree_tapbuf_size8_2_sram[0]:12 ropt_net_165:4 4.869997e-05 +19 mux_tree_tapbuf_size8_2_sram[0]:7 ropt_net_165:5 4.869997e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size8_2_sram[0]:13 mux_tree_tapbuf_size8_2_sram[0]:12 0.006765625 +2 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:11 0.0045 +3 mux_tree_tapbuf_size8_2_sram[0]:12 mux_tree_tapbuf_size8_2_sram[0]:7 0.004888393 +4 mux_tree_tapbuf_size8_2_sram[0]:11 mux_tree_tapbuf_size8_2_sram[0]:10 0.002044643 +5 mux_tree_tapbuf_size8_2_sram[0]:9 mux_tree_tapbuf_size8_2_sram[0]:8 0.001823661 +6 mux_tree_tapbuf_size8_2_sram[0]:10 mux_tree_tapbuf_size8_2_sram[0]:9 0.0045 +7 mux_tree_tapbuf_size8_2_sram[0]:8 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size8_2_sram[0]:3 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size8_2_sram[0]:4 mux_tree_tapbuf_size8_2_sram[0]:3 0.0004263393 +10 mux_tree_tapbuf_size8_2_sram[0]:5 mux_tree_tapbuf_size8_2_sram[0]:4 0.0045 +11 mux_tree_tapbuf_size8_2_sram[0]:7 mux_tree_tapbuf_size8_2_sram[0]:6 0.0045 +12 mux_tree_tapbuf_size8_2_sram[0]:6 mux_tree_tapbuf_size8_2_sram[0]:5 0.001133929 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001060774 //LENGTH 7.320 LUMPCC 0.0003006075 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_2_:X O *L 0 *C 61.355 119.000 +*I mux_top_track_0\/mux_l2_in_1_:A1 I *L 0.00198 *C 57.040 121.380 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 57.040 121.380 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 57.040 121.335 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 57.040 119.045 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 57.085 119.000 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 61.318 119.000 + +*CAP +0 mux_top_track_0\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.779779e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001041367 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001041367 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002560477 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002560477 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[12]:8 4.481666e-06 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 chany_bottom_in[12]:13 6.93607e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[12]:9 4.481666e-06 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 chany_bottom_in[12]:12 6.93607e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 7.646141e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 7.646141e-05 + +*RES +0 mux_top_track_0\/mux_l1_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.003779018 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002044643 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_0\/mux_l2_in_1_:A1 0.152 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0] 0.007518334 //LENGTH 51.250 LUMPCC 0.003723699 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_1_:X O *L 0 *C 17.765 96.900 +*I mux_top_track_0\/mux_l4_in_0_:A0 I *L 0.001631 *C 37.435 126.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 37.398 126.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 36.385 126.140 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 36.340 126.095 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 36.340 114.297 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 36.333 114.240 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 32.220 114.240 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 *C 32.200 114.233 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 *C 32.200 99.968 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 *C 32.180 99.960 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 *C 20.248 99.960 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 *C 20.240 99.903 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 *C 20.240 96.945 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 *C 20.195 96.900 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 *C 17.803 96.900 + +*CAP +0 mux_top_track_0\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 9.408112e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 9.408112e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0004970577 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0004970577 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0002560117 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.0002560117 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0002915091 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0002915091 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0004079699 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0004079699 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.000170823 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.000170823 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 0.0001788653 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 0.0001788653 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 chany_top_in[11]:15 1.633097e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 chany_top_in[11]:14 1.633097e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 chany_top_in[11]:13 0.0003134812 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 chany_top_in[11]:12 0.0003134812 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 left_top_grid_pin_43_[0]:34 0.0004043568 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 left_top_grid_pin_43_[0]:35 0.0001849893 +22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 left_top_grid_pin_43_[0]:8 0.0004043568 +23 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 left_top_grid_pin_43_[0]:34 0.0001849893 +24 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 top_left_grid_pin_35_[0]:19 4.537109e-06 +25 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 top_left_grid_pin_35_[0]:20 4.537109e-06 +26 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 top_left_grid_pin_35_[0]:17 2.532551e-05 +27 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 top_left_grid_pin_35_[0]:18 0.0001162279 +28 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 top_left_grid_pin_35_[0]:5 2.532551e-05 +29 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 top_left_grid_pin_35_[0]:17 0.0001162279 +30 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_tree_tapbuf_size10_0_sram[2]:4 1.000525e-07 +31 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_tree_tapbuf_size10_0_sram[2]:5 1.000525e-07 +32 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:6 4.958627e-06 +33 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_tree_tapbuf_size10_0_sram[2]:9 8.918385e-06 +34 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:9 4.958627e-06 +35 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:10 8.918385e-06 +36 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:11 7.150501e-06 +37 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_tree_tapbuf_size10_0_sram[2]:12 7.150501e-06 +38 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_tree_tapbuf_size10_0_sram[2]:13 0.0003206895 +39 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_tree_tapbuf_size10_0_sram[2]:15 0.0004335898 +40 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_tree_tapbuf_size10_0_sram[2]:14 0.0003206895 +41 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_tree_tapbuf_size10_0_sram[2]:17 1.708495e-06 +42 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_tree_tapbuf_size10_0_sram[2]:21 2.296941e-06 +43 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_tree_tapbuf_size10_0_sram[2]:16 0.0004335898 +44 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 mux_tree_tapbuf_size10_0_sram[2]:19 1.718847e-05 +45 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_tree_tapbuf_size10_0_sram[2]:20 2.296941e-06 +46 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_tree_tapbuf_size10_0_sram[2]:21 1.708495e-06 +47 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 mux_tree_tapbuf_size10_0_sram[2]:18 1.718847e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0009040179 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.01053348 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.00341 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0006442916 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.00341 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.00341 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.00223485 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.00341 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.001869425 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 0.0045 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 0.002640625 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 0.002136161 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001949638 //LENGTH 15.335 LUMPCC 0.0003134928 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 70.205 18.360 +*I mux_bottom_track_9\/mux_l3_in_0_:A1 I *L 0.00198 *C 72.220 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 72.183 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 70.425 30.940 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 70.380 30.895 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 70.380 18.405 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 70.380 18.360 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 70.205 18.360 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001375929 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001375929 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0006204307 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0006204307 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.967579e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.842161e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:6 6.406738e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:10 1.218678e-06 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:14 9.146037e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:11 1.218678e-06 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:14 6.406738e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:15 9.146037e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01115179 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001569196 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0008872063 //LENGTH 7.295 LUMPCC 0.0001409257 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_2_:X O *L 0 *C 58.245 105.400 +*I mux_top_track_4\/mux_l3_in_1_:A1 I *L 0.00198 *C 57.140 110.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 57.178 110.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 58.375 110.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 58.420 110.455 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 58.420 105.445 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 58.420 105.400 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 58.245 105.400 + +*CAP +0 mux_top_track_4\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 9.531144e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 9.531144e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0002256411 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0002256411 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 5.251346e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 4.986199e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:4 2.062684e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:8 4.983601e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:5 2.062684e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_10_X[0]:9 4.983601e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_top_track_4\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.001069196 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.004473214 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_9_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0] 0.000527914 //LENGTH 4.300 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/mux_l2_in_0_:X O *L 0 *C 52.155 96.220 +*I mux_top_track_16\/mux_l3_in_0_:A1 I *L 0.005458 *C 51.645 93.648 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 51.610 93.530 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 51.520 93.545 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 51.520 96.175 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 51.565 96.220 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 52.117 96.220 + +*CAP +0 mux_top_track_16\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:A1 3.931628e-05 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 3.931628e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001714855 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001714855 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.265524e-05 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 5.265524e-05 + +*RES +0 mux_top_track_16\/mux_l2_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004933036 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002348214 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_16\/mux_l3_in_0_:A1 3.365385e-05 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004355998 //LENGTH 2.865 LUMPCC 0.0002099251 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_2_:X O *L 0 *C 16.385 90.780 +*I mux_left_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 18.960 90.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 18.922 90.780 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 16.422 90.780 + +*CAP +0 mux_left_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001118374 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001118374 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size7_3_sram[0]:20 7.65252e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size7_3_sram[0]:22 2.843733e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_3_sram[0]:21 2.843733e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size7_3_sram[0]:22 7.65252e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_2_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002232143 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0004626691 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_1_:X O *L 0 *C 12.595 82.280 +*I mux_left_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 9.950 82.280 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 9.988 82.280 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 12.558 82.280 + +*CAP +0 mux_left_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002303346 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0002303346 + +*RES +0 mux_left_track_3\/mux_l2_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002294643 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002068709 //LENGTH 17.165 LUMPCC 0.0004031959 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_0_:X O *L 0 *C 67.795 53.380 +*I mux_left_track_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 54.280 56.100 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 54.318 56.100 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 55.615 56.100 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 55.660 56.055 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 55.660 53.425 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 55.705 53.380 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 67.758 53.380 + +*CAP +0 mux_left_track_7\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.69374e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.69374e-05 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001418632 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001418632 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0006229561 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0006229561 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[12]:15 6.919337e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[12]:14 6.919337e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[12]:15 4.579902e-05 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[12]:14 4.579902e-05 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[12]:16 2.548976e-05 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[12]:13 2.548976e-05 +14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[19]:5 6.111579e-05 +15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[19]:4 6.111579e-05 + +*RES +0 mux_left_track_7\/mux_l1_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01076116 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001158482 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_7\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001274656 //LENGTH 10.380 LUMPCC 0.0002520689 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 78.375 12.580 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 74.060 18.020 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 74.060 18.020 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 74.060 17.975 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 74.060 12.625 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 74.105 12.580 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.338 12.580 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.196537e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002227041 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002227041 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002716068 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002716068 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[17]:9 7.478081e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_top_in[17]:10 7.478081e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_1_sram[0]:5 4.845682e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size6_1_sram[0]:6 4.845682e-05 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size6_1_sram[0]:7 2.796821e-06 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size6_1_sram[0]:8 2.796821e-06 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.003779018 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.004776786 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007865999 //LENGTH 5.740 LUMPCC 0.0001328131 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_1_:X O *L 0 *C 23.175 34.680 +*I mux_bottom_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 22.255 38.760 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.293 38.760 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.955 38.760 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 23.000 38.715 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 23.000 34.725 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 23.000 34.680 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 23.175 34.680 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.052289e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.052289e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000194433 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000194433 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.984736e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.202757e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.640656e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 6.640656e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0005915179 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0035625 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007742867 //LENGTH 5.650 LUMPCC 7.612375e-05 DR + +*CONN +*I mux_left_track_11\/mux_l2_in_1_:X O *L 0 *C 81.705 45.220 +*I mux_left_track_11\/mux_l3_in_0_:A0 I *L 0.001631 *C 83.550 47.940 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 83.550 47.940 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 83.720 47.940 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 83.720 47.895 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 83.720 45.265 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 83.675 45.220 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 81.743 45.220 + +*CAP +0 mux_left_track_11\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_11\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.359358e-05 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.600257e-05 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001639228 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001639228 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001293605 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001293605 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:33 3.533416e-06 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:32 3.452846e-05 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:34 3.533416e-06 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:31 3.452846e-05 + +*RES +0 mux_left_track_11\/mux_l2_in_1_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_11\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:2 9.239131e-05 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348215 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001725447 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001133909 //LENGTH 8.040 LUMPCC 0.0003118047 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_1_:X O *L 0 *C 18.575 60.860 +*I mux_left_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 18.690 53.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 18.690 53.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 18.860 53.720 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 18.860 53.765 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 18.860 60.815 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 18.860 60.860 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 18.575 60.860 + +*CAP +0 mux_left_track_17\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.183059e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.435402e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000297761 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000297761 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.803933e-05 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.035879e-05 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[9]:5 5.557952e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[9]:8 5.557952e-05 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_0_sram[0]:9 9.526801e-08 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_0_sram[0]:17 5.711061e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_0_sram[0]:12 9.526801e-08 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_0_sram[0]:16 5.711061e-05 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_139:31 3.331452e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_139:36 5.25118e-06 +16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_139:32 4.551245e-06 +17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_139:35 5.25118e-06 +18 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_139:37 3.331452e-05 +19 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_139:34 4.551245e-06 + +*RES +0 mux_left_track_17\/mux_l1_in_1_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.006294644 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.009048815 //LENGTH 60.225 LUMPCC 0.003188159 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 44.795 65.960 +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.010 44.725 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 7.010 44.725 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 7.010 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 12.835 45.220 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 12.880 45.265 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 12.880 65.903 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 12.888 65.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 44.613 65.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 44.620 65.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 44.620 65.960 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 44.795 65.960 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.799503e-05 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004426703 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004018083 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001055978 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001055978 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001335316 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001335316 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 3.748558e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 5.80304e-05 +11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 5.807686e-05 +12 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:392 3.744137e-07 +13 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:393 1.140689e-07 +14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 prog_clk[0]:522 1.500379e-06 +15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:386 3.744137e-07 +16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:392 1.140689e-07 +17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 prog_clk[0]:521 1.500379e-06 +18 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:381 0.0003204898 +19 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 prog_clk[0]:488 0.0001439391 +20 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 prog_clk[0]:378 0.0003204898 +21 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 prog_clk[0]:487 0.0001439391 +22 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[18] 0.0002313176 +23 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[18]:15 9.414838e-07 +24 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[18]:17 5.017637e-06 +25 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_left_in[18]:14 9.414838e-07 +26 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_left_in[18]:16 5.017637e-06 +27 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_left_in[18]:18 0.0002313176 +28 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_3_sram[1]:10 1.2613e-08 +29 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_3_sram[1]:15 0.0002021337 +30 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_3_sram[1]:17 1.382127e-05 +31 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_3_sram[1]:9 1.2613e-08 +32 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_3_sram[1]:14 0.0002021337 +33 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_3_sram[1]:16 1.382127e-05 +34 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0006744177 +35 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0006744177 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.005200893 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.01842634 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00341 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.00341 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00497025 +8 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 9.51087e-05 +10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004419643 + +*END + +*D_NET chany_bottom_out[7] 0.001385499 //LENGTH 9.780 LUMPCC 0.0001819326 DR + +*CONN +*I ropt_mt_inst_814:X O *L 0 *C 63.940 7.140 +*P chany_bottom_out[7] O *L 0.7423 *C 60.720 1.325 +*N chany_bottom_out[7]:2 *C 60.720 3.060 +*N chany_bottom_out[7]:3 *C 61.180 3.060 +*N chany_bottom_out[7]:4 *C 61.180 7.095 +*N chany_bottom_out[7]:5 *C 61.225 7.140 +*N chany_bottom_out[7]:6 *C 63.903 7.140 + +*CAP +0 ropt_mt_inst_814:X 1e-06 +1 chany_bottom_out[7] 0.0001142977 +2 chany_bottom_out[7]:2 0.0001455309 +3 chany_bottom_out[7]:3 0.0002460008 +4 chany_bottom_out[7]:4 0.0002147676 +5 chany_bottom_out[7]:5 0.0002409848 +6 chany_bottom_out[7]:6 0.0002409848 +7 chany_bottom_out[7]:4 ropt_net_166:3 9.096628e-05 +8 chany_bottom_out[7]:3 ropt_net_166:4 9.096628e-05 + +*RES +0 ropt_mt_inst_814:X chany_bottom_out[7]:6 0.152 +1 chany_bottom_out[7]:5 chany_bottom_out[7]:4 0.0045 +2 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.003602679 +3 chany_bottom_out[7]:6 chany_bottom_out[7]:5 0.002390625 +4 chany_bottom_out[7]:2 chany_bottom_out[7] 0.001549107 +5 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0004107143 + +*END + +*D_NET mem_left_track_25/net_net_84 0.007613262 //LENGTH 53.570 LUMPCC 0.002454129 DR + +*CONN +*I mem_left_track_25\/FTB_27__59:X O *L 0 *C 50.825 63.240 +*I mem_left_track_25\/BUFT_RR_84:A I *L 0.001743 *C 11.500 63.920 +*N mem_left_track_25/net_net_84:2 *C 11.500 63.920 +*N mem_left_track_25/net_net_84:3 *C 11.500 63.965 +*N mem_left_track_25/net_net_84:4 *C 11.500 69.983 +*N mem_left_track_25/net_net_84:5 *C 11.508 70.040 +*N mem_left_track_25/net_net_84:6 *C 45.532 70.040 +*N mem_left_track_25/net_net_84:7 *C 45.540 69.983 +*N mem_left_track_25/net_net_84:8 *C 45.540 63.285 +*N mem_left_track_25/net_net_84:9 *C 45.585 63.240 +*N mem_left_track_25/net_net_84:10 *C 50.788 63.240 + +*CAP +0 mem_left_track_25\/FTB_27__59:X 1e-06 +1 mem_left_track_25\/BUFT_RR_84:A 1e-06 +2 mem_left_track_25/net_net_84:2 3.700448e-05 +3 mem_left_track_25/net_net_84:3 0.0003723135 +4 mem_left_track_25/net_net_84:4 0.0003723135 +5 mem_left_track_25/net_net_84:5 0.001543691 +6 mem_left_track_25/net_net_84:6 0.001543691 +7 mem_left_track_25/net_net_84:7 0.0003875777 +8 mem_left_track_25/net_net_84:8 0.0003875777 +9 mem_left_track_25/net_net_84:9 0.0002564821 +10 mem_left_track_25/net_net_84:10 0.0002564821 +11 mem_left_track_25/net_net_84:5 chanx_left_in[16]:7 0.0002720952 +12 mem_left_track_25/net_net_84:6 chanx_left_in[16]:6 0.0002720952 +13 mem_left_track_25/net_net_84:5 chanx_left_in[18] 0.0001378847 +14 mem_left_track_25/net_net_84:5 chanx_left_in[18]:15 1.060909e-05 +15 mem_left_track_25/net_net_84:5 chanx_left_in[18]:17 8.383745e-05 +16 mem_left_track_25/net_net_84:7 chanx_left_in[18]:16 6.315831e-06 +17 mem_left_track_25/net_net_84:6 chanx_left_in[18]:14 1.060909e-05 +18 mem_left_track_25/net_net_84:6 chanx_left_in[18]:16 8.383745e-05 +19 mem_left_track_25/net_net_84:6 chanx_left_in[18]:18 0.0001378847 +20 mem_left_track_25/net_net_84:8 chanx_left_in[18]:15 6.315831e-06 +21 mem_left_track_25/net_net_84:5 mux_tree_tapbuf_size7_5_sram[0]:15 0.0003784972 +22 mem_left_track_25/net_net_84:6 mux_tree_tapbuf_size7_5_sram[0]:14 0.0003784972 +23 mem_left_track_25/net_net_84:9 mux_tree_tapbuf_size7_6_sram[1]:5 0.0001973192 +24 mem_left_track_25/net_net_84:10 mux_tree_tapbuf_size7_6_sram[1]:6 0.0001973192 +25 mem_left_track_25/net_net_84:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001405056 +26 mem_left_track_25/net_net_84:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001405056 + +*RES +0 mem_left_track_25\/FTB_27__59:X mem_left_track_25/net_net_84:10 0.152 +1 mem_left_track_25/net_net_84:2 mem_left_track_25\/BUFT_RR_84:A 0.152 +2 mem_left_track_25/net_net_84:3 mem_left_track_25/net_net_84:2 0.0045 +3 mem_left_track_25/net_net_84:4 mem_left_track_25/net_net_84:3 0.005372768 +4 mem_left_track_25/net_net_84:5 mem_left_track_25/net_net_84:4 0.00341 +5 mem_left_track_25/net_net_84:7 mem_left_track_25/net_net_84:6 0.00341 +6 mem_left_track_25/net_net_84:6 mem_left_track_25/net_net_84:5 0.005330583 +7 mem_left_track_25/net_net_84:9 mem_left_track_25/net_net_84:8 0.0045 +8 mem_left_track_25/net_net_84:8 mem_left_track_25/net_net_84:7 0.005979911 +9 mem_left_track_25/net_net_84:10 mem_left_track_25/net_net_84:9 0.00464509 + +*END + +*D_NET chany_top_out[5] 0.002153815 //LENGTH 16.130 LUMPCC 0.0001243088 DR + +*CONN +*I ropt_mt_inst_843:X O *L 0 *C 89.895 123.080 +*P chany_top_out[5] O *L 0.7423 *C 83.720 129.235 +*N chany_top_out[5]:2 *C 83.260 129.200 +*N chany_top_out[5]:3 *C 83.260 122.458 +*N chany_top_out[5]:4 *C 83.267 122.400 +*N chany_top_out[5]:5 *C 90.153 122.400 +*N chany_top_out[5]:6 *C 90.160 122.458 +*N chany_top_out[5]:7 *C 90.160 123.035 +*N chany_top_out[5]:8 *C 90.160 123.080 +*N chany_top_out[5]:9 *C 89.895 123.080 + +*CAP +0 ropt_mt_inst_843:X 1e-06 +1 chany_top_out[5] 3.092908e-05 +2 chany_top_out[5]:2 0.0004153117 +3 chany_top_out[5]:3 0.0003843826 +4 chany_top_out[5]:4 0.0004830177 +5 chany_top_out[5]:5 0.0004830177 +6 chany_top_out[5]:6 5.466478e-05 +7 chany_top_out[5]:7 5.466478e-05 +8 chany_top_out[5]:8 5.934796e-05 +9 chany_top_out[5]:9 6.31704e-05 +10 chany_top_out[5]:3 ropt_net_197:5 6.215438e-05 +11 chany_top_out[5]:2 ropt_net_197:4 6.215438e-05 + +*RES +0 ropt_mt_inst_843:X chany_top_out[5]:9 0.152 +1 chany_top_out[5]:9 chany_top_out[5]:8 0.0001440218 +2 chany_top_out[5]:8 chany_top_out[5]:7 0.0045 +3 chany_top_out[5]:7 chany_top_out[5]:6 0.000515625 +4 chany_top_out[5]:6 chany_top_out[5]:5 0.00341 +5 chany_top_out[5]:5 chany_top_out[5]:4 0.00107865 +6 chany_top_out[5]:3 chany_top_out[5]:2 0.00602009 +7 chany_top_out[5]:4 chany_top_out[5]:3 0.00341 +8 chany_top_out[5]:2 chany_top_out[5] 0.0004107143 + +*END + +*D_NET chany_top_in[9] 0.01618778 //LENGTH 152.530 LUMPCC 0.00353843 DR + +*CONN +*P chany_top_in[9] I *L 0.29796 *C 67.620 129.270 +*I mux_left_track_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 88.685 56.100 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 80.500 12.580 +*I BUFT_P_108:A I *L 0.001776 *C 90.160 12.240 +*N chany_top_in[9]:4 *C 90.160 12.240 +*N chany_top_in[9]:5 *C 80.538 12.580 +*N chany_top_in[9]:6 *C 90.160 12.580 +*N chany_top_in[9]:7 *C 90.160 12.625 +*N chany_top_in[9]:8 *C 90.160 56.055 +*N chany_top_in[9]:9 *C 90.115 56.100 +*N chany_top_in[9]:10 *C 88.723 56.100 +*N chany_top_in[9]:11 *C 89.240 56.100 +*N chany_top_in[9]:12 *C 89.240 56.145 +*N chany_top_in[9]:13 *C 89.240 105.940 +*N chany_top_in[9]:14 *C 89.240 118.263 +*N chany_top_in[9]:15 *C 89.233 118.320 +*N chany_top_in[9]:16 *C 76.380 118.320 +*N chany_top_in[9]:17 *C 76.360 118.328 +*N chany_top_in[9]:18 *C 76.360 126.473 +*N chany_top_in[9]:19 *C 76.340 126.480 +*N chany_top_in[9]:20 *C 67.627 126.480 +*N chany_top_in[9]:21 *C 67.620 126.538 + +*CAP +0 chany_top_in[9] 0.0001918874 +1 mux_left_track_11\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +3 BUFT_P_108:A 1e-06 +4 chany_top_in[9]:4 5.900901e-05 +5 chany_top_in[9]:5 0.000523109 +6 chany_top_in[9]:6 0.0005561428 +7 chany_top_in[9]:7 0.001638775 +8 chany_top_in[9]:8 0.001638775 +9 chany_top_in[9]:9 4.691179e-05 +10 chany_top_in[9]:10 2.404992e-05 +11 chany_top_in[9]:11 0.0001027717 +12 chany_top_in[9]:12 0.001645904 +13 chany_top_in[9]:13 0.002019407 +14 chany_top_in[9]:14 0.0003735027 +15 chany_top_in[9]:15 0.000810253 +16 chany_top_in[9]:16 0.000810253 +17 chany_top_in[9]:17 0.0004282555 +18 chany_top_in[9]:18 0.0004282555 +19 chany_top_in[9]:19 0.0005786016 +20 chany_top_in[9]:20 0.0005786016 +21 chany_top_in[9]:21 0.0001918874 +22 chany_top_in[9]:7 chany_bottom_in[9]:15 1.770132e-06 +23 chany_top_in[9]:7 chany_bottom_in[9]:16 5.072248e-06 +24 chany_top_in[9]:8 chany_bottom_in[9]:15 5.072248e-06 +25 chany_top_in[9]:8 chany_bottom_in[9]:12 1.770132e-06 +26 chany_top_in[9]:11 chany_bottom_in[9]:13 1.168594e-05 +27 chany_top_in[9]:12 chany_bottom_in[9]:15 0.0004577977 +28 chany_top_in[9]:10 chany_bottom_in[9]:14 1.168594e-05 +29 chany_top_in[9]:13 chany_bottom_in[9]:12 0.0004577977 +30 chany_top_in[9]:12 chany_bottom_in[17]:7 0.0001042353 +31 chany_top_in[9]:14 chany_bottom_in[17]:6 0.0001706298 +32 chany_top_in[9]:13 chany_bottom_in[17]:7 0.0001706298 +33 chany_top_in[9]:13 chany_bottom_in[17]:6 0.0001042353 +34 chany_top_in[9]:7 chany_bottom_in[11]:5 0.0003188227 +35 chany_top_in[9]:8 chany_bottom_in[11]:4 0.0003188227 +36 chany_top_in[9]:12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.000349363 +37 chany_top_in[9]:14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001260948 +38 chany_top_in[9]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.000349363 +39 chany_top_in[9]:13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001260948 +40 chany_top_in[9]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.513804e-05 +41 chany_top_in[9]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.513804e-05 +42 chany_top_in[9]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001227249 +43 chany_top_in[9]:9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 1.117826e-05 +44 chany_top_in[9]:8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001227249 +45 chany_top_in[9]:11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.702372e-06 +46 chany_top_in[9]:11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.117826e-05 +47 chany_top_in[9]:10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.702372e-06 + +*RES +0 chany_top_in[9] chany_top_in[9]:21 0.002439732 +1 chany_top_in[9]:5 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +2 chany_top_in[9]:6 chany_top_in[9]:5 0.008591519 +3 chany_top_in[9]:6 chany_top_in[9]:4 0.0001465517 +4 chany_top_in[9]:7 chany_top_in[9]:6 0.0045 +5 chany_top_in[9]:9 chany_top_in[9]:8 0.0045 +6 chany_top_in[9]:8 chany_top_in[9]:7 0.03877679 +7 chany_top_in[9]:11 chany_top_in[9]:10 0.0004620536 +8 chany_top_in[9]:11 chany_top_in[9]:9 0.0007812501 +9 chany_top_in[9]:12 chany_top_in[9]:11 0.0045 +10 chany_top_in[9]:14 chany_top_in[9]:13 0.01100223 +11 chany_top_in[9]:15 chany_top_in[9]:14 0.00341 +12 chany_top_in[9]:16 chany_top_in[9]:15 0.002013558 +13 chany_top_in[9]:17 chany_top_in[9]:16 0.00341 +14 chany_top_in[9]:19 chany_top_in[9]:18 0.00341 +15 chany_top_in[9]:18 chany_top_in[9]:17 0.00127605 +16 chany_top_in[9]:21 chany_top_in[9]:20 0.00341 +17 chany_top_in[9]:20 chany_top_in[9]:19 0.001364958 +18 chany_top_in[9]:10 mux_left_track_11\/mux_l1_in_0_:A1 0.152 +19 chany_top_in[9]:4 BUFT_P_108:A 0.152 +20 chany_top_in[9]:13 chany_top_in[9]:12 0.04445983 + +*END + +*D_NET chany_bottom_in[19] 0.01214785 //LENGTH 88.940 LUMPCC 0.004061139 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 78.660 1.290 +*I mux_left_track_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 46.340 55.420 +*N chany_bottom_in[19]:2 *C 46.378 55.420 +*N chany_bottom_in[19]:3 *C 46.920 55.420 +*N chany_bottom_in[19]:4 *C 46.920 55.760 +*N chany_bottom_in[19]:5 *C 61.595 55.760 +*N chany_bottom_in[19]:6 *C 61.640 55.760 +*N chany_bottom_in[19]:7 *C 61.648 55.760 +*N chany_bottom_in[19]:8 *C 78.180 55.760 +*N chany_bottom_in[19]:9 *C 78.200 55.753 +*N chany_bottom_in[19]:10 *C 78.200 13.607 +*N chany_bottom_in[19]:11 *C 78.215 13.600 +*N chany_bottom_in[19]:12 *C 78.657 13.600 +*N chany_bottom_in[19]:13 *C 78.660 13.543 + +*CAP +0 chany_bottom_in[19] 0.0004892808 +1 mux_left_track_15\/mux_l2_in_0_:A0 1e-06 +2 chany_bottom_in[19]:2 4.262845e-05 +3 chany_bottom_in[19]:3 6.768123e-05 +4 chany_bottom_in[19]:4 0.0007586394 +5 chany_bottom_in[19]:5 0.0007335866 +6 chany_bottom_in[19]:6 3.604451e-05 +7 chany_bottom_in[19]:7 0.001277813 +8 chany_bottom_in[19]:8 0.001277813 +9 chany_bottom_in[19]:9 0.001402225 +10 chany_bottom_in[19]:10 0.001402225 +11 chany_bottom_in[19]:11 5.424584e-05 +12 chany_bottom_in[19]:12 5.424584e-05 +13 chany_bottom_in[19]:13 0.0004892808 +14 chany_bottom_in[19]:9 chany_bottom_in[2]:31 0.0003357835 +15 chany_bottom_in[19]:9 chany_bottom_in[2]:36 5.470358e-06 +16 chany_bottom_in[19]:10 chany_bottom_in[2] 5.470358e-06 +17 chany_bottom_in[19]:10 chany_bottom_in[2]:32 0.0003357835 +18 chany_bottom_in[19] chany_bottom_in[16] 9.889742e-06 +19 chany_bottom_in[19] chany_bottom_in[16]:28 8.270324e-06 +20 chany_bottom_in[19]:9 chany_bottom_in[16]:24 0.001023188 +21 chany_bottom_in[19]:10 chany_bottom_in[16]:25 0.001023188 +22 chany_bottom_in[19]:13 chany_bottom_in[16]:27 8.270324e-06 +23 chany_bottom_in[19]:13 chany_bottom_in[16]:29 9.889742e-06 +24 chany_bottom_in[19]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.111579e-05 +25 chany_bottom_in[19]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.111579e-05 +26 chany_bottom_in[19]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001657813 +27 chany_bottom_in[19]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001657813 +28 chany_bottom_in[19]:2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.294826e-06 +29 chany_bottom_in[19]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001274107 +30 chany_bottom_in[19]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.294826e-06 +31 chany_bottom_in[19]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001274107 +32 chany_bottom_in[19] ropt_net_203:6 0.0001047669 +33 chany_bottom_in[19]:13 ropt_net_203:5 0.0001047669 +34 chany_bottom_in[19] mux_bottom_track_1/BUF_net_60:9 6.346672e-05 +35 chany_bottom_in[19]:13 mux_bottom_track_1/BUF_net_60:10 6.346672e-05 +36 chany_bottom_in[19] ropt_net_154:4 0.000119131 +37 chany_bottom_in[19]:13 ropt_net_154:5 0.000119131 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:13 0.01093973 +1 chany_bottom_in[19]:2 mux_left_track_15\/mux_l2_in_0_:A0 0.152 +2 chany_bottom_in[19]:5 chany_bottom_in[19]:4 0.01310268 +3 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.0045 +4 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.00341 +5 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.002590092 +6 chany_bottom_in[19]:9 chany_bottom_in[19]:8 0.00341 +7 chany_bottom_in[19]:11 chany_bottom_in[19]:10 0.00341 +8 chany_bottom_in[19]:10 chany_bottom_in[19]:9 0.006602716 +9 chany_bottom_in[19]:13 chany_bottom_in[19]:12 0.00341 +10 chany_bottom_in[19]:12 chany_bottom_in[19]:11 6.499219e-05 +11 chany_bottom_in[19]:3 chany_bottom_in[19]:2 0.000484375 +12 chany_bottom_in[19]:4 chany_bottom_in[19]:3 0.0003035715 + +*END + +*D_NET chanx_left_in[2] 0.00610996 //LENGTH 49.640 LUMPCC 0.0004801581 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.298 46.240 +*I mux_top_track_24\/mux_l1_in_2_:A1 I *L 0.00198 *C 23.000 72.420 +*I mux_bottom_track_3\/mux_l2_in_2_:A1 I *L 0.00198 *C 20.340 50.660 +*N chanx_left_in[2]:3 *C 20.340 50.660 +*N chanx_left_in[2]:4 *C 23.000 72.420 +*N chanx_left_in[2]:5 *C 23.000 72.375 +*N chanx_left_in[2]:6 *C 23.000 51.045 +*N chanx_left_in[2]:7 *C 22.955 51.000 +*N chanx_left_in[2]:8 *C 20.240 51.000 +*N chanx_left_in[2]:9 *C 1.425 51.000 +*N chanx_left_in[2]:10 *C 1.380 50.955 +*N chanx_left_in[2]:11 *C 1.380 46.297 +*N chanx_left_in[2]:12 *C 1.380 46.240 + +*CAP +0 chanx_left_in[2] 3.19817e-05 +1 mux_top_track_24\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_3\/mux_l2_in_2_:A1 1e-06 +3 chanx_left_in[2]:3 5.480432e-05 +4 chanx_left_in[2]:4 3.46115e-05 +5 chanx_left_in[2]:5 0.001156953 +6 chanx_left_in[2]:6 0.001156953 +7 chanx_left_in[2]:7 0.0001999223 +8 chanx_left_in[2]:8 0.001328443 +9 chanx_left_in[2]:9 0.001101689 +10 chanx_left_in[2]:10 0.0002652316 +11 chanx_left_in[2]:11 0.0002652316 +12 chanx_left_in[2]:12 3.19817e-05 +13 chanx_left_in[2]:9 mux_tree_tapbuf_size4_3_sram[2]:8 0.0002163013 +14 chanx_left_in[2]:9 mux_tree_tapbuf_size4_3_sram[2]:3 2.377781e-05 +15 chanx_left_in[2]:8 mux_tree_tapbuf_size4_3_sram[2]:9 0.0002163013 +16 chanx_left_in[2]:8 mux_tree_tapbuf_size4_3_sram[2]:4 2.377781e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:12 2.35e-05 +1 chanx_left_in[2]:9 chanx_left_in[2]:8 0.01679911 +2 chanx_left_in[2]:10 chanx_left_in[2]:9 0.0045 +3 chanx_left_in[2]:11 chanx_left_in[2]:10 0.004158482 +4 chanx_left_in[2]:12 chanx_left_in[2]:11 0.00341 +5 chanx_left_in[2]:3 mux_bottom_track_3\/mux_l2_in_2_:A1 0.152 +6 chanx_left_in[2]:4 mux_top_track_24\/mux_l1_in_2_:A1 0.152 +7 chanx_left_in[2]:5 chanx_left_in[2]:4 0.0045 +8 chanx_left_in[2]:7 chanx_left_in[2]:6 0.0045 +9 chanx_left_in[2]:6 chanx_left_in[2]:5 0.01904465 +10 chanx_left_in[2]:8 chanx_left_in[2]:7 0.002424107 +11 chanx_left_in[2]:8 chanx_left_in[2]:3 0.0003035715 + +*END + +*D_NET chanx_left_in[8] 0.01391832 //LENGTH 94.110 LUMPCC 0.004679876 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.305 43.520 +*I mux_bottom_track_1\/mux_l2_in_2_:A0 I *L 0.001631 *C 42.495 33.660 +*I mux_top_track_32\/mux_l1_in_2_:A1 I *L 0.00198 *C 48.860 72.420 +*N chanx_left_in[8]:3 *C 48.823 72.420 +*N chanx_left_in[8]:4 *C 48.345 72.420 +*N chanx_left_in[8]:5 *C 48.300 72.375 +*N chanx_left_in[8]:6 *C 48.300 40.178 +*N chanx_left_in[8]:7 *C 48.293 40.120 +*N chanx_left_in[8]:8 *C 42.458 33.660 +*N chanx_left_in[8]:9 *C 41.905 33.660 +*N chanx_left_in[8]:10 *C 41.860 33.705 +*N chanx_left_in[8]:11 *C 41.860 40.062 +*N chanx_left_in[8]:12 *C 41.860 40.120 +*N chanx_left_in[8]:13 *C 13.820 40.120 +*N chanx_left_in[8]:14 *C 13.800 40.128 +*N chanx_left_in[8]:15 *C 13.800 44.193 +*N chanx_left_in[8]:16 *C 13.780 44.200 +*N chanx_left_in[8]:17 *C 1.380 44.200 + +*CAP +0 chanx_left_in[8] 5.36584e-05 +1 mux_bottom_track_1\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:A1 1e-06 +3 chanx_left_in[8]:3 5.13542e-05 +4 chanx_left_in[8]:4 5.13542e-05 +5 chanx_left_in[8]:5 0.001732078 +6 chanx_left_in[8]:6 0.001732078 +7 chanx_left_in[8]:7 0.0002715552 +8 chanx_left_in[8]:8 5.691684e-05 +9 chanx_left_in[8]:9 5.691684e-05 +10 chanx_left_in[8]:10 0.0003744691 +11 chanx_left_in[8]:11 0.0003744691 +12 chanx_left_in[8]:12 0.001251813 +13 chanx_left_in[8]:13 0.0009802579 +14 chanx_left_in[8]:14 0.0002372986 +15 chanx_left_in[8]:15 0.0002372986 +16 chanx_left_in[8]:16 0.0008606334 +17 chanx_left_in[8]:17 0.0009142918 +18 chanx_left_in[8]:12 prog_clk[0]:204 1.38227e-05 +19 chanx_left_in[8]:12 prog_clk[0]:208 8.305248e-05 +20 chanx_left_in[8]:12 prog_clk[0]:244 4.711991e-06 +21 chanx_left_in[8]:12 prog_clk[0]:508 0.0001299827 +22 chanx_left_in[8]:12 prog_clk[0]:512 7.472071e-05 +23 chanx_left_in[8]:12 prog_clk[0]:518 2.757021e-07 +24 chanx_left_in[8]:7 prog_clk[0]:204 4.39424e-05 +25 chanx_left_in[8]:13 prog_clk[0]:208 1.38227e-05 +26 chanx_left_in[8]:13 prog_clk[0]:244 3.911008e-05 +27 chanx_left_in[8]:13 prog_clk[0]:245 4.711991e-06 +28 chanx_left_in[8]:13 prog_clk[0]:512 0.0001299827 +29 chanx_left_in[8]:13 prog_clk[0]:513 7.472071e-05 +30 chanx_left_in[8]:13 prog_clk[0]:523 2.757021e-07 +31 chanx_left_in[8]:14 prog_clk[0]:513 5.579886e-06 +32 chanx_left_in[8]:16 prog_clk[0]:512 4.51382e-06 +33 chanx_left_in[8]:16 prog_clk[0]:518 7.168227e-05 +34 chanx_left_in[8]:16 prog_clk[0]:523 0.000108503 +35 chanx_left_in[8]:15 prog_clk[0]:518 5.579886e-06 +36 chanx_left_in[8]:17 prog_clk[0]:513 4.51382e-06 +37 chanx_left_in[8]:17 prog_clk[0]:523 7.168227e-05 +38 chanx_left_in[8]:17 prog_clk[0]:524 0.000108503 +39 chanx_left_in[8]:12 chanx_left_in[3]:10 0.001019015 +40 chanx_left_in[8]:13 chanx_left_in[3] 0.001019015 +41 chanx_left_in[8]:16 chanx_left_in[3]:10 1.617257e-07 +42 chanx_left_in[8]:17 chanx_left_in[3] 1.617257e-07 +43 chanx_left_in[8]:12 chanx_left_in[11]:19 0.0001268256 +44 chanx_left_in[8]:12 chanx_left_in[11]:20 0.0001397534 +45 chanx_left_in[8]:7 chanx_left_in[11]:19 0.0001397534 +46 chanx_left_in[8]:13 chanx_left_in[11]:20 0.0001268256 +47 chanx_left_in[8]:12 chanx_left_in[13]:11 0.0004401316 +48 chanx_left_in[8]:13 chanx_left_in[13]:12 0.0004401316 +49 chanx_left_in[8]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0001168848 +50 chanx_left_in[8]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:4 3.204206e-07 +51 chanx_left_in[8]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001168848 +52 chanx_left_in[8]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:5 3.204206e-07 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:17 0.0001065333 +1 chanx_left_in[8]:11 chanx_left_in[8]:10 0.005676339 +2 chanx_left_in[8]:12 chanx_left_in[8]:11 0.00341 +3 chanx_left_in[8]:12 chanx_left_in[8]:7 0.001007758 +4 chanx_left_in[8]:9 chanx_left_in[8]:8 0.0004933036 +5 chanx_left_in[8]:10 chanx_left_in[8]:9 0.0045 +6 chanx_left_in[8]:8 mux_bottom_track_1\/mux_l2_in_2_:A0 0.152 +7 chanx_left_in[8]:6 chanx_left_in[8]:5 0.02874777 +8 chanx_left_in[8]:7 chanx_left_in[8]:6 0.00341 +9 chanx_left_in[8]:4 chanx_left_in[8]:3 0.0004263393 +10 chanx_left_in[8]:5 chanx_left_in[8]:4 0.0045 +11 chanx_left_in[8]:3 mux_top_track_32\/mux_l1_in_2_:A1 0.152 +12 chanx_left_in[8]:13 chanx_left_in[8]:12 0.004392933 +13 chanx_left_in[8]:14 chanx_left_in[8]:13 0.00341 +14 chanx_left_in[8]:16 chanx_left_in[8]:15 0.00341 +15 chanx_left_in[8]:15 chanx_left_in[8]:14 0.00063685 +16 chanx_left_in[8]:17 chanx_left_in[8]:16 0.001942667 + +*END + +*D_NET left_top_grid_pin_49_[0] 0.01118678 //LENGTH 80.990 LUMPCC 0.001800653 DR + +*CONN +*P left_top_grid_pin_49_[0] I *L 0.29796 *C 10.580 102.070 +*I mux_left_track_3\/mux_l1_in_3_:A1 I *L 0.00198 *C 15.640 79.900 +*I mux_left_track_7\/mux_l1_in_3_:A1 I *L 0.00198 *C 34.040 63.580 +*I mux_left_track_23\/mux_l1_in_1_:A1 I *L 0.00198 *C 38.180 79.900 +*N left_top_grid_pin_49_[0]:4 *C 38.180 79.900 +*N left_top_grid_pin_49_[0]:5 *C 38.180 79.560 +*N left_top_grid_pin_49_[0]:6 *C 35.005 79.560 +*N left_top_grid_pin_49_[0]:7 *C 34.960 79.515 +*N left_top_grid_pin_49_[0]:8 *C 34.960 77.860 +*N left_top_grid_pin_49_[0]:9 *C 34.500 77.860 +*N left_top_grid_pin_49_[0]:10 *C 34.500 73.440 +*N left_top_grid_pin_49_[0]:11 *C 34.040 63.595 +*N left_top_grid_pin_49_[0]:12 *C 34.040 63.920 +*N left_top_grid_pin_49_[0]:13 *C 34.040 63.965 +*N left_top_grid_pin_49_[0]:14 *C 34.040 73.440 +*N left_top_grid_pin_49_[0]:15 *C 34.040 75.422 +*N left_top_grid_pin_49_[0]:16 *C 34.032 75.480 +*N left_top_grid_pin_49_[0]:17 *C 15.603 79.900 +*N left_top_grid_pin_49_[0]:18 *C 15.225 79.900 +*N left_top_grid_pin_49_[0]:19 *C 15.180 79.855 +*N left_top_grid_pin_49_[0]:20 *C 15.180 75.538 +*N left_top_grid_pin_49_[0]:21 *C 15.180 75.480 +*N left_top_grid_pin_49_[0]:22 *C 11.060 75.480 +*N left_top_grid_pin_49_[0]:23 *C 11.040 75.487 +*N left_top_grid_pin_49_[0]:24 *C 11.040 89.752 +*N left_top_grid_pin_49_[0]:25 *C 11.025 89.760 +*N left_top_grid_pin_49_[0]:26 *C 10.583 89.760 +*N left_top_grid_pin_49_[0]:27 *C 10.580 89.818 + +*CAP +0 left_top_grid_pin_49_[0] 0.0005183115 +1 mux_left_track_3\/mux_l1_in_3_:A1 1e-06 +2 mux_left_track_7\/mux_l1_in_3_:A1 1e-06 +3 mux_left_track_23\/mux_l1_in_1_:A1 1e-06 +4 left_top_grid_pin_49_[0]:4 6.073922e-05 +5 left_top_grid_pin_49_[0]:5 0.0002917037 +6 left_top_grid_pin_49_[0]:6 0.0002620554 +7 left_top_grid_pin_49_[0]:7 0.0001233245 +8 left_top_grid_pin_49_[0]:8 0.0001562161 +9 left_top_grid_pin_49_[0]:9 0.0003219892 +10 left_top_grid_pin_49_[0]:10 0.0003214803 +11 left_top_grid_pin_49_[0]:11 3.713739e-05 +12 left_top_grid_pin_49_[0]:12 7.155087e-05 +13 left_top_grid_pin_49_[0]:13 0.0005585431 +14 left_top_grid_pin_49_[0]:14 0.000689858 +15 left_top_grid_pin_49_[0]:15 9.893224e-05 +16 left_top_grid_pin_49_[0]:16 0.001142583 +17 left_top_grid_pin_49_[0]:17 4.635047e-05 +18 left_top_grid_pin_49_[0]:18 4.635047e-05 +19 left_top_grid_pin_49_[0]:19 0.0003003969 +20 left_top_grid_pin_49_[0]:20 0.0003003969 +21 left_top_grid_pin_49_[0]:21 0.001418617 +22 left_top_grid_pin_49_[0]:22 0.0002760347 +23 left_top_grid_pin_49_[0]:23 0.0008325866 +24 left_top_grid_pin_49_[0]:24 0.0008325866 +25 left_top_grid_pin_49_[0]:25 7.853695e-05 +26 left_top_grid_pin_49_[0]:26 7.853695e-05 +27 left_top_grid_pin_49_[0]:27 0.0005183115 +28 left_top_grid_pin_49_[0] chany_top_in[19]:5 3.382095e-08 +29 left_top_grid_pin_49_[0] chany_top_in[19]:9 0.0002809416 +30 left_top_grid_pin_49_[0]:27 chany_top_in[19]:4 3.382095e-08 +31 left_top_grid_pin_49_[0]:27 chany_top_in[19]:8 0.0002809416 +32 left_top_grid_pin_49_[0]:22 chanx_left_in[0]:22 2.592685e-05 +33 left_top_grid_pin_49_[0]:23 chanx_left_in[0]:19 6.61176e-05 +34 left_top_grid_pin_49_[0]:23 chanx_left_in[0]:20 0.000211769 +35 left_top_grid_pin_49_[0]:24 chanx_left_in[0]:8 0.000211769 +36 left_top_grid_pin_49_[0]:24 chanx_left_in[0]:20 6.61176e-05 +37 left_top_grid_pin_49_[0]:21 chanx_left_in[0]:21 2.592685e-05 +38 left_top_grid_pin_49_[0]:16 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003155377 +39 left_top_grid_pin_49_[0]:21 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003155377 + +*RES +0 left_top_grid_pin_49_[0] left_top_grid_pin_49_[0]:27 0.01093973 +1 left_top_grid_pin_49_[0]:12 left_top_grid_pin_49_[0]:11 0.0001766304 +2 left_top_grid_pin_49_[0]:13 left_top_grid_pin_49_[0]:12 0.0045 +3 left_top_grid_pin_49_[0]:11 mux_left_track_7\/mux_l1_in_3_:A1 0.152 +4 left_top_grid_pin_49_[0]:15 left_top_grid_pin_49_[0]:14 0.00177009 +5 left_top_grid_pin_49_[0]:16 left_top_grid_pin_49_[0]:15 0.00341 +6 left_top_grid_pin_49_[0]:22 left_top_grid_pin_49_[0]:21 0.0006454666 +7 left_top_grid_pin_49_[0]:23 left_top_grid_pin_49_[0]:22 0.00341 +8 left_top_grid_pin_49_[0]:25 left_top_grid_pin_49_[0]:24 0.00341 +9 left_top_grid_pin_49_[0]:24 left_top_grid_pin_49_[0]:23 0.00223485 +10 left_top_grid_pin_49_[0]:27 left_top_grid_pin_49_[0]:26 0.00341 +11 left_top_grid_pin_49_[0]:26 left_top_grid_pin_49_[0]:25 6.499219e-05 +12 left_top_grid_pin_49_[0]:6 left_top_grid_pin_49_[0]:5 0.002834822 +13 left_top_grid_pin_49_[0]:7 left_top_grid_pin_49_[0]:6 0.0045 +14 left_top_grid_pin_49_[0]:4 mux_left_track_23\/mux_l1_in_1_:A1 0.152 +15 left_top_grid_pin_49_[0]:20 left_top_grid_pin_49_[0]:19 0.003854911 +16 left_top_grid_pin_49_[0]:21 left_top_grid_pin_49_[0]:20 0.00341 +17 left_top_grid_pin_49_[0]:21 left_top_grid_pin_49_[0]:16 0.002953558 +18 left_top_grid_pin_49_[0]:18 left_top_grid_pin_49_[0]:17 0.0003370536 +19 left_top_grid_pin_49_[0]:19 left_top_grid_pin_49_[0]:18 0.0045 +20 left_top_grid_pin_49_[0]:17 mux_left_track_3\/mux_l1_in_3_:A1 0.152 +21 left_top_grid_pin_49_[0]:5 left_top_grid_pin_49_[0]:4 0.0003035715 +22 left_top_grid_pin_49_[0]:14 left_top_grid_pin_49_[0]:13 0.008459822 +23 left_top_grid_pin_49_[0]:14 left_top_grid_pin_49_[0]:10 0.0004107143 +24 left_top_grid_pin_49_[0]:10 left_top_grid_pin_49_[0]:9 0.003946429 +25 left_top_grid_pin_49_[0]:9 left_top_grid_pin_49_[0]:8 0.0004107143 +26 left_top_grid_pin_49_[0]:8 left_top_grid_pin_49_[0]:7 0.001477679 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[2] 0.00723446 //LENGTH 54.510 LUMPCC 0.001710168 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.305 99.280 +*I mux_top_track_0\/mux_l3_in_1_:S I *L 0.00357 *C 16.920 96.220 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 32.835 120.700 +*I mux_top_track_0\/mux_l3_in_0_:S I *L 0.00357 *C 40.120 123.420 +*N mux_tree_tapbuf_size10_0_sram[2]:4 *C 40.120 123.420 +*N mux_tree_tapbuf_size10_0_sram[2]:5 *C 34.085 123.420 +*N mux_tree_tapbuf_size10_0_sram[2]:6 *C 34.040 123.375 +*N mux_tree_tapbuf_size10_0_sram[2]:7 *C 32.873 120.700 +*N mux_tree_tapbuf_size10_0_sram[2]:8 *C 33.995 120.700 +*N mux_tree_tapbuf_size10_0_sram[2]:9 *C 34.040 120.700 +*N mux_tree_tapbuf_size10_0_sram[2]:10 *C 34.040 118.378 +*N mux_tree_tapbuf_size10_0_sram[2]:11 *C 34.032 118.320 +*N mux_tree_tapbuf_size10_0_sram[2]:12 *C 30.380 118.320 +*N mux_tree_tapbuf_size10_0_sram[2]:13 *C 30.360 118.312 +*N mux_tree_tapbuf_size10_0_sram[2]:14 *C 30.360 100.648 +*N mux_tree_tapbuf_size10_0_sram[2]:15 *C 30.340 100.640 +*N mux_tree_tapbuf_size10_0_sram[2]:16 *C 23.008 100.640 +*N mux_tree_tapbuf_size10_0_sram[2]:17 *C 23.000 100.583 +*N mux_tree_tapbuf_size10_0_sram[2]:18 *C 16.957 96.220 +*N mux_tree_tapbuf_size10_0_sram[2]:19 *C 22.955 96.220 +*N mux_tree_tapbuf_size10_0_sram[2]:20 *C 23.000 96.265 +*N mux_tree_tapbuf_size10_0_sram[2]:21 *C 23.000 99.280 +*N mux_tree_tapbuf_size10_0_sram[2]:22 *C 23.000 99.280 +*N mux_tree_tapbuf_size10_0_sram[2]:23 *C 23.305 99.280 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:S 1e-06 +2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_top_track_0\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size10_0_sram[2]:4 0.0004061693 +5 mux_tree_tapbuf_size10_0_sram[2]:5 0.0003710867 +6 mux_tree_tapbuf_size10_0_sram[2]:6 0.0001776171 +7 mux_tree_tapbuf_size10_0_sram[2]:7 0.0001289305 +8 mux_tree_tapbuf_size10_0_sram[2]:8 0.0001289305 +9 mux_tree_tapbuf_size10_0_sram[2]:9 0.0003581864 +10 mux_tree_tapbuf_size10_0_sram[2]:10 0.0001497603 +11 mux_tree_tapbuf_size10_0_sram[2]:11 0.0002509609 +12 mux_tree_tapbuf_size10_0_sram[2]:12 0.0002509609 +13 mux_tree_tapbuf_size10_0_sram[2]:13 0.0005906 +14 mux_tree_tapbuf_size10_0_sram[2]:14 0.0005906 +15 mux_tree_tapbuf_size10_0_sram[2]:15 0.0003257478 +16 mux_tree_tapbuf_size10_0_sram[2]:16 0.0003257478 +17 mux_tree_tapbuf_size10_0_sram[2]:17 7.422552e-05 +18 mux_tree_tapbuf_size10_0_sram[2]:18 0.0004215891 +19 mux_tree_tapbuf_size10_0_sram[2]:19 0.0004215891 +20 mux_tree_tapbuf_size10_0_sram[2]:20 0.0001708827 +21 mux_tree_tapbuf_size10_0_sram[2]:21 0.0002756306 +22 mux_tree_tapbuf_size10_0_sram[2]:22 5.236347e-05 +23 mux_tree_tapbuf_size10_0_sram[2]:23 4.87131e-05 +24 mux_tree_tapbuf_size10_0_sram[2]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 5.848326e-05 +25 mux_tree_tapbuf_size10_0_sram[2]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 5.848326e-05 +26 mux_tree_tapbuf_size10_0_sram[2]:19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:14 1.718847e-05 +27 mux_tree_tapbuf_size10_0_sram[2]:20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 2.296941e-06 +28 mux_tree_tapbuf_size10_0_sram[2]:18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:15 1.718847e-05 +29 mux_tree_tapbuf_size10_0_sram[2]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:3 1.000525e-07 +30 mux_tree_tapbuf_size10_0_sram[2]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 4.958627e-06 +31 mux_tree_tapbuf_size10_0_sram[2]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:2 1.000525e-07 +32 mux_tree_tapbuf_size10_0_sram[2]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:4 8.918385e-06 +33 mux_tree_tapbuf_size10_0_sram[2]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 4.958627e-06 +34 mux_tree_tapbuf_size10_0_sram[2]:21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 2.296941e-06 +35 mux_tree_tapbuf_size10_0_sram[2]:21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:13 1.708495e-06 +36 mux_tree_tapbuf_size10_0_sram[2]:17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:12 1.708495e-06 +37 mux_tree_tapbuf_size10_0_sram[2]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:11 0.0004335898 +38 mux_tree_tapbuf_size10_0_sram[2]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:10 0.0004335898 +39 mux_tree_tapbuf_size10_0_sram[2]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0003206895 +40 mux_tree_tapbuf_size10_0_sram[2]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.150501e-06 +41 mux_tree_tapbuf_size10_0_sram[2]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0003206895 +42 mux_tree_tapbuf_size10_0_sram[2]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:5 8.918385e-06 +43 mux_tree_tapbuf_size10_0_sram[2]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.150501e-06 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size10_0_sram[2]:23 0.152 +1 mux_tree_tapbuf_size10_0_sram[2]:19 mux_tree_tapbuf_size10_0_sram[2]:18 0.005354911 +2 mux_tree_tapbuf_size10_0_sram[2]:20 mux_tree_tapbuf_size10_0_sram[2]:19 0.0045 +3 mux_tree_tapbuf_size10_0_sram[2]:18 mux_top_track_0\/mux_l3_in_1_:S 0.152 +4 mux_tree_tapbuf_size10_0_sram[2]:5 mux_tree_tapbuf_size10_0_sram[2]:4 0.005388393 +5 mux_tree_tapbuf_size10_0_sram[2]:6 mux_tree_tapbuf_size10_0_sram[2]:5 0.0045 +6 mux_tree_tapbuf_size10_0_sram[2]:4 mux_top_track_0\/mux_l3_in_0_:S 0.152 +7 mux_tree_tapbuf_size10_0_sram[2]:8 mux_tree_tapbuf_size10_0_sram[2]:7 0.001002232 +8 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:8 0.0045 +9 mux_tree_tapbuf_size10_0_sram[2]:9 mux_tree_tapbuf_size10_0_sram[2]:6 0.002388393 +10 mux_tree_tapbuf_size10_0_sram[2]:7 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +11 mux_tree_tapbuf_size10_0_sram[2]:22 mux_tree_tapbuf_size10_0_sram[2]:21 0.0045 +12 mux_tree_tapbuf_size10_0_sram[2]:21 mux_tree_tapbuf_size10_0_sram[2]:20 0.002691964 +13 mux_tree_tapbuf_size10_0_sram[2]:21 mux_tree_tapbuf_size10_0_sram[2]:17 0.001162947 +14 mux_tree_tapbuf_size10_0_sram[2]:23 mux_tree_tapbuf_size10_0_sram[2]:22 0.0001657609 +15 mux_tree_tapbuf_size10_0_sram[2]:17 mux_tree_tapbuf_size10_0_sram[2]:16 0.00341 +16 mux_tree_tapbuf_size10_0_sram[2]:16 mux_tree_tapbuf_size10_0_sram[2]:15 0.001148758 +17 mux_tree_tapbuf_size10_0_sram[2]:15 mux_tree_tapbuf_size10_0_sram[2]:14 0.00341 +18 mux_tree_tapbuf_size10_0_sram[2]:14 mux_tree_tapbuf_size10_0_sram[2]:13 0.002767516 +19 mux_tree_tapbuf_size10_0_sram[2]:12 mux_tree_tapbuf_size10_0_sram[2]:11 0.000572225 +20 mux_tree_tapbuf_size10_0_sram[2]:13 mux_tree_tapbuf_size10_0_sram[2]:12 0.00341 +21 mux_tree_tapbuf_size10_0_sram[2]:10 mux_tree_tapbuf_size10_0_sram[2]:9 0.002073661 +22 mux_tree_tapbuf_size10_0_sram[2]:11 mux_tree_tapbuf_size10_0_sram[2]:10 0.00341 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.001241763 //LENGTH 7.440 LUMPCC 0.0004444376 DR + +*CONN +*I mem_left_track_17\/FTB_23__55:X O *L 0 *C 25.075 53.040 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 28.235 55.420 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 28.235 55.420 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 28.520 55.420 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 28.520 55.375 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 28.520 54.458 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 28.513 54.400 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 25.768 54.400 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 *C 25.760 54.343 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 *C 25.760 53.085 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 *C 25.715 53.040 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 *C 25.113 53.040 + +*CAP +0 mem_left_track_17\/FTB_23__55:X 1e-06 +1 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 5.120126e-05 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 5.328459e-05 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 8.011752e-05 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 8.011752e-05 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0001106133 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.0001106133 +8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 9.328014e-05 +9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 9.328014e-05 +10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 6.140902e-05 +11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 6.140902e-05 +12 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 chany_top_in[15]:13 0.0001678936 +13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 chany_top_in[15]:14 0.0001678936 +14 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size4_3_sram[1]:17 5.43252e-05 +15 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size4_3_sram[1]:18 5.43252e-05 + +*RES +0 mem_left_track_17\/FTB_23__55:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:11 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 0.0005379464 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 0.0045 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 0.001122768 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.00341 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.00043005 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.0008191965 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.00341 +8 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0001548913 +9 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0045 +10 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_3_ccff_tail[0] 0.002169996 //LENGTH 16.885 LUMPCC 0.0005167163 DR + +*CONN +*I mem_left_track_15\/FTB_22__54:X O *L 0 *C 4.370 49.980 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 11.675 58.820 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 *C 11.675 58.820 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 *C 11.500 58.820 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 *C 11.500 58.775 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 *C 11.500 50.025 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 *C 11.455 49.980 +*N mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 *C 4.408 49.980 + +*CAP +0 mem_left_track_15\/FTB_22__54:X 1e-06 +1 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 6.380508e-05 +3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 6.412511e-05 +4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 0.0004849688 +5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 0.0004849688 +6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 0.0002767057 +7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 0.0002767057 +8 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size4_3_sram[2]:6 7.234932e-08 +9 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size4_3_sram[2]:4 5.895509e-05 +10 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size4_3_sram[2]:9 5.104058e-05 +11 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size4_3_sram[2]:7 7.234932e-08 +12 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size4_3_sram[2]:3 5.895509e-05 +13 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size4_3_sram[2]:8 5.104058e-05 +14 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001482901 +15 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001482901 + +*RES +0 mem_left_track_15\/FTB_22__54:X mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 0.0078125 +6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 0.006292411 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[1] 0.004187629 //LENGTH 32.960 LUMPCC 0.0006593433 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 55.965 86.020 +*I mux_top_track_16\/mux_l2_in_1_:S I *L 0.00357 *C 50.500 79.560 +*I mux_top_track_16\/mux_l2_in_0_:S I *L 0.00357 *C 54.860 95.880 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 59.975 86.020 +*N mux_tree_tapbuf_size7_0_sram[1]:4 *C 60.013 86.020 +*N mux_tree_tapbuf_size7_0_sram[1]:5 *C 61.180 86.020 +*N mux_tree_tapbuf_size7_0_sram[1]:6 *C 61.180 86.360 +*N mux_tree_tapbuf_size7_0_sram[1]:7 *C 54.898 95.880 +*N mux_tree_tapbuf_size7_0_sram[1]:8 *C 56.995 95.880 +*N mux_tree_tapbuf_size7_0_sram[1]:9 *C 57.040 95.835 +*N mux_tree_tapbuf_size7_0_sram[1]:10 *C 57.040 86.405 +*N mux_tree_tapbuf_size7_0_sram[1]:11 *C 57.040 86.360 +*N mux_tree_tapbuf_size7_0_sram[1]:12 *C 55.660 86.360 +*N mux_tree_tapbuf_size7_0_sram[1]:13 *C 50.538 79.560 +*N mux_tree_tapbuf_size7_0_sram[1]:14 *C 55.615 79.560 +*N mux_tree_tapbuf_size7_0_sram[1]:15 *C 55.660 79.605 +*N mux_tree_tapbuf_size7_0_sram[1]:16 *C 55.660 85.975 +*N mux_tree_tapbuf_size7_0_sram[1]:17 *C 55.660 86.020 +*N mux_tree_tapbuf_size7_0_sram[1]:18 *C 55.965 86.020 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_16\/mux_l2_in_1_:S 1e-06 +2 mux_top_track_16\/mux_l2_in_0_:S 1e-06 +3 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_0_sram[1]:4 5.500337e-05 +5 mux_tree_tapbuf_size7_0_sram[1]:5 8.200534e-05 +6 mux_tree_tapbuf_size7_0_sram[1]:6 0.0003280976 +7 mux_tree_tapbuf_size7_0_sram[1]:7 0.0001639362 +8 mux_tree_tapbuf_size7_0_sram[1]:8 0.0001639362 +9 mux_tree_tapbuf_size7_0_sram[1]:9 0.000364802 +10 mux_tree_tapbuf_size7_0_sram[1]:10 0.000364802 +11 mux_tree_tapbuf_size7_0_sram[1]:11 0.0004360731 +12 mux_tree_tapbuf_size7_0_sram[1]:12 0.0001250193 +13 mux_tree_tapbuf_size7_0_sram[1]:13 0.0003561483 +14 mux_tree_tapbuf_size7_0_sram[1]:14 0.0003561483 +15 mux_tree_tapbuf_size7_0_sram[1]:15 0.00030794 +16 mux_tree_tapbuf_size7_0_sram[1]:16 0.00030794 +17 mux_tree_tapbuf_size7_0_sram[1]:17 7.180452e-05 +18 mux_tree_tapbuf_size7_0_sram[1]:18 4.062836e-05 +19 mux_tree_tapbuf_size7_0_sram[1]:9 chany_bottom_in[12]:13 0.0002560463 +20 mux_tree_tapbuf_size7_0_sram[1]:10 chany_bottom_in[12]:16 0.0002560463 +21 mux_tree_tapbuf_size7_0_sram[1]:16 chany_bottom_in[12]:13 7.362539e-05 +22 mux_tree_tapbuf_size7_0_sram[1]:15 chany_bottom_in[12]:16 7.362539e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_0_sram[1]:18 0.152 +1 mux_tree_tapbuf_size7_0_sram[1]:7 mux_top_track_16\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_0_sram[1]:8 mux_tree_tapbuf_size7_0_sram[1]:7 0.001872768 +3 mux_tree_tapbuf_size7_0_sram[1]:9 mux_tree_tapbuf_size7_0_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size7_0_sram[1]:11 mux_tree_tapbuf_size7_0_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size7_0_sram[1]:11 mux_tree_tapbuf_size7_0_sram[1]:6 0.003696428 +6 mux_tree_tapbuf_size7_0_sram[1]:10 mux_tree_tapbuf_size7_0_sram[1]:9 0.008419643 +7 mux_tree_tapbuf_size7_0_sram[1]:17 mux_tree_tapbuf_size7_0_sram[1]:16 0.0045 +8 mux_tree_tapbuf_size7_0_sram[1]:17 mux_tree_tapbuf_size7_0_sram[1]:12 0.0003035715 +9 mux_tree_tapbuf_size7_0_sram[1]:16 mux_tree_tapbuf_size7_0_sram[1]:15 0.0056875 +10 mux_tree_tapbuf_size7_0_sram[1]:14 mux_tree_tapbuf_size7_0_sram[1]:13 0.004533482 +11 mux_tree_tapbuf_size7_0_sram[1]:15 mux_tree_tapbuf_size7_0_sram[1]:14 0.0045 +12 mux_tree_tapbuf_size7_0_sram[1]:13 mux_top_track_16\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size7_0_sram[1]:4 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +14 mux_tree_tapbuf_size7_0_sram[1]:18 mux_tree_tapbuf_size7_0_sram[1]:17 0.0001657609 +15 mux_tree_tapbuf_size7_0_sram[1]:12 mux_tree_tapbuf_size7_0_sram[1]:11 0.001232143 +16 mux_tree_tapbuf_size7_0_sram[1]:6 mux_tree_tapbuf_size7_0_sram[1]:5 0.0003035714 +17 mux_tree_tapbuf_size7_0_sram[1]:5 mux_tree_tapbuf_size7_0_sram[1]:4 0.001042411 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[0] 0.004943535 //LENGTH 34.835 LUMPCC 0.0006839009 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 28.365 82.960 +*I mux_left_track_3\/mux_l1_in_2_:S I *L 0.00357 *C 18.500 85.390 +*I mux_left_track_3\/mux_l1_in_3_:S I *L 0.00357 *C 17.020 80.065 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 20.875 80.580 +*I mux_left_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 30.460 85.340 +*I mux_left_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 33.220 80.240 +*N mux_tree_tapbuf_size7_4_sram[0]:6 *C 33.235 80.240 +*N mux_tree_tapbuf_size7_4_sram[0]:7 *C 33.558 80.240 +*N mux_tree_tapbuf_size7_4_sram[0]:8 *C 33.580 80.285 +*N mux_tree_tapbuf_size7_4_sram[0]:9 *C 33.580 82.915 +*N mux_tree_tapbuf_size7_4_sram[0]:10 *C 33.535 82.960 +*N mux_tree_tapbuf_size7_4_sram[0]:11 *C 30.423 85.340 +*N mux_tree_tapbuf_size7_4_sram[0]:12 *C 20.875 80.580 +*N mux_tree_tapbuf_size7_4_sram[0]:13 *C 20.700 80.920 +*N mux_tree_tapbuf_size7_4_sram[0]:14 *C 17.020 80.065 +*N mux_tree_tapbuf_size7_4_sram[0]:15 *C 17.020 80.920 +*N mux_tree_tapbuf_size7_4_sram[0]:16 *C 18.860 80.920 +*N mux_tree_tapbuf_size7_4_sram[0]:17 *C 18.860 80.965 +*N mux_tree_tapbuf_size7_4_sram[0]:18 *C 18.538 85.373 +*N mux_tree_tapbuf_size7_4_sram[0]:19 *C 18.830 85.370 +*N mux_tree_tapbuf_size7_4_sram[0]:20 *C 18.860 85.340 +*N mux_tree_tapbuf_size7_4_sram[0]:21 *C 19.780 85.340 +*N mux_tree_tapbuf_size7_4_sram[0]:22 *C 19.825 85.340 +*N mux_tree_tapbuf_size7_4_sram[0]:23 *C 29.900 85.340 +*N mux_tree_tapbuf_size7_4_sram[0]:24 *C 29.900 85.295 +*N mux_tree_tapbuf_size7_4_sram[0]:25 *C 29.900 83.005 +*N mux_tree_tapbuf_size7_4_sram[0]:26 *C 29.900 82.960 +*N mux_tree_tapbuf_size7_4_sram[0]:27 *C 28.402 82.960 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_3\/mux_l1_in_2_:S 1e-06 +2 mux_left_track_3\/mux_l1_in_3_:S 1e-06 +3 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_track_3\/mux_l1_in_1_:S 1e-06 +5 mux_left_track_3\/mux_l1_in_0_:S 1e-06 +6 mux_tree_tapbuf_size7_4_sram[0]:6 6.011317e-05 +7 mux_tree_tapbuf_size7_4_sram[0]:7 6.011317e-05 +8 mux_tree_tapbuf_size7_4_sram[0]:8 0.000112053 +9 mux_tree_tapbuf_size7_4_sram[0]:9 0.000112053 +10 mux_tree_tapbuf_size7_4_sram[0]:10 0.0001984009 +11 mux_tree_tapbuf_size7_4_sram[0]:11 3.531127e-05 +12 mux_tree_tapbuf_size7_4_sram[0]:12 6.035189e-05 +13 mux_tree_tapbuf_size7_4_sram[0]:13 0.000167183 +14 mux_tree_tapbuf_size7_4_sram[0]:14 9.018023e-05 +15 mux_tree_tapbuf_size7_4_sram[0]:15 0.0002036908 +16 mux_tree_tapbuf_size7_4_sram[0]:16 0.0003208871 +17 mux_tree_tapbuf_size7_4_sram[0]:17 0.0003067607 +18 mux_tree_tapbuf_size7_4_sram[0]:18 5.118128e-05 +19 mux_tree_tapbuf_size7_4_sram[0]:19 5.118128e-05 +20 mux_tree_tapbuf_size7_4_sram[0]:20 0.000367796 +21 mux_tree_tapbuf_size7_4_sram[0]:21 9.344109e-05 +22 mux_tree_tapbuf_size7_4_sram[0]:22 0.0006429068 +23 mux_tree_tapbuf_size7_4_sram[0]:23 0.0007127944 +24 mux_tree_tapbuf_size7_4_sram[0]:24 0.0001057922 +25 mux_tree_tapbuf_size7_4_sram[0]:25 0.0001057922 +26 mux_tree_tapbuf_size7_4_sram[0]:26 0.0003137754 +27 mux_tree_tapbuf_size7_4_sram[0]:27 8.187481e-05 +28 mux_tree_tapbuf_size7_4_sram[0]:23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.56102e-05 +29 mux_tree_tapbuf_size7_4_sram[0]:23 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001204592 +30 mux_tree_tapbuf_size7_4_sram[0]:22 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001204592 +31 mux_tree_tapbuf_size7_4_sram[0]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.56102e-05 +32 mux_tree_tapbuf_size7_4_sram[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.997395e-05 +33 mux_tree_tapbuf_size7_4_sram[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.997395e-05 +34 mux_tree_tapbuf_size7_4_sram[0]:26 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.274172e-05 +35 mux_tree_tapbuf_size7_4_sram[0]:26 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.274172e-05 +36 mux_tree_tapbuf_size7_4_sram[0]:25 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 7.042364e-05 +37 mux_tree_tapbuf_size7_4_sram[0]:24 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 7.042364e-05 +38 mux_tree_tapbuf_size7_4_sram[0]:27 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.274172e-05 +39 mux_tree_tapbuf_size7_4_sram[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.274172e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_4_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_4_sram[0]:14 mux_left_track_3\/mux_l1_in_3_:S 0.152 +2 mux_tree_tapbuf_size7_4_sram[0]:26 mux_tree_tapbuf_size7_4_sram[0]:25 0.0045 +3 mux_tree_tapbuf_size7_4_sram[0]:26 mux_tree_tapbuf_size7_4_sram[0]:10 0.003245536 +4 mux_tree_tapbuf_size7_4_sram[0]:25 mux_tree_tapbuf_size7_4_sram[0]:24 0.002044643 +5 mux_tree_tapbuf_size7_4_sram[0]:23 mux_tree_tapbuf_size7_4_sram[0]:22 0.008995536 +6 mux_tree_tapbuf_size7_4_sram[0]:23 mux_tree_tapbuf_size7_4_sram[0]:11 0.0004665179 +7 mux_tree_tapbuf_size7_4_sram[0]:24 mux_tree_tapbuf_size7_4_sram[0]:23 0.0045 +8 mux_tree_tapbuf_size7_4_sram[0]:22 mux_tree_tapbuf_size7_4_sram[0]:21 0.0045 +9 mux_tree_tapbuf_size7_4_sram[0]:21 mux_tree_tapbuf_size7_4_sram[0]:20 0.0008214285 +10 mux_tree_tapbuf_size7_4_sram[0]:19 mux_tree_tapbuf_size7_4_sram[0]:18 0.0001828125 +11 mux_tree_tapbuf_size7_4_sram[0]:20 mux_tree_tapbuf_size7_4_sram[0]:19 0.0045 +12 mux_tree_tapbuf_size7_4_sram[0]:20 mux_tree_tapbuf_size7_4_sram[0]:17 0.00390625 +13 mux_tree_tapbuf_size7_4_sram[0]:18 mux_left_track_3\/mux_l1_in_2_:S 0.152 +14 mux_tree_tapbuf_size7_4_sram[0]:16 mux_tree_tapbuf_size7_4_sram[0]:15 0.001642857 +15 mux_tree_tapbuf_size7_4_sram[0]:16 mux_tree_tapbuf_size7_4_sram[0]:13 0.001642857 +16 mux_tree_tapbuf_size7_4_sram[0]:17 mux_tree_tapbuf_size7_4_sram[0]:16 0.0045 +17 mux_tree_tapbuf_size7_4_sram[0]:27 mux_tree_tapbuf_size7_4_sram[0]:26 0.001337054 +18 mux_tree_tapbuf_size7_4_sram[0]:12 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size7_4_sram[0]:11 mux_left_track_3\/mux_l1_in_1_:S 0.152 +20 mux_tree_tapbuf_size7_4_sram[0]:10 mux_tree_tapbuf_size7_4_sram[0]:9 0.0045 +21 mux_tree_tapbuf_size7_4_sram[0]:9 mux_tree_tapbuf_size7_4_sram[0]:8 0.002348215 +22 mux_tree_tapbuf_size7_4_sram[0]:7 mux_tree_tapbuf_size7_4_sram[0]:6 0.0001752718 +23 mux_tree_tapbuf_size7_4_sram[0]:8 mux_tree_tapbuf_size7_4_sram[0]:7 0.0045 +24 mux_tree_tapbuf_size7_4_sram[0]:6 mux_left_track_3\/mux_l1_in_0_:S 0.152 +25 mux_tree_tapbuf_size7_4_sram[0]:15 mux_tree_tapbuf_size7_4_sram[0]:14 0.0007633929 +26 mux_tree_tapbuf_size7_4_sram[0]:13 mux_tree_tapbuf_size7_4_sram[0]:12 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_2_ccff_tail[0] 0.0009675614 //LENGTH 8.420 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/FTB_5__37:X O *L 0 *C 81.645 40.120 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 76.535 42.500 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 *C 76.573 42.500 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 *C 80.915 42.500 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 *C 80.960 42.455 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 *C 80.960 40.165 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 *C 81.005 40.120 +*N mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 *C 81.608 40.120 + +*CAP +0 mem_bottom_track_9\/FTB_5__37:X 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.0002812449 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0002812449 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.000139006 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.000139006 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 6.252983e-05 +7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 6.252983e-05 + +*RES +0 mem_bottom_track_9\/FTB_5__37:X mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 0.003877232 +5 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_2_ccff_tail[0]:2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001699865 //LENGTH 11.835 LUMPCC 0.000788714 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_2_:X O *L 0 *C 12.705 89.080 +*I mux_top_track_0\/mux_l3_in_1_:A1 I *L 0.00198 *C 16.200 96.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 16.163 96.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 12.465 96.220 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 12.420 96.175 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 12.420 89.125 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 12.420 89.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 12.705 89.080 + +*CAP +0 mux_top_track_0\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001512574 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001512574 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002433165 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002433165 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.85273e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.147547e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_top_in[3]:3 0.0001505647 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_top_in[3]:2 0.0001505647 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:15 5.512684e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:16 2.786101e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:13 5.512684e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:15 2.786101e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 1.655588e-06 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 1.655588e-06 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.18268e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.18268e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 optlc_net_139:51 0.0001060475 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 optlc_net_139:53 1.274592e-06 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 optlc_net_139:52 0.0001060475 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 optlc_net_139:54 1.274592e-06 + +*RES +0 mux_top_track_0\/mux_l2_in_2_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A1 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.003301339 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006294643 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0009229054 //LENGTH 7.300 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_0_:X O *L 0 *C 46.635 19.720 +*I mux_bottom_track_1\/mux_l4_in_0_:A1 I *L 0.00198 *C 43.800 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 43.700 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 43.700 23.415 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 43.700 19.765 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 43.745 19.720 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 46.598 19.720 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.214019e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000227067 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.000227067 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0002173157 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0002173157 + +*RES +0 mux_bottom_track_1\/mux_l3_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_1\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.003258929 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.002546875 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0] 0.00497676 //LENGTH 33.585 LUMPCC 0.0009668712 DR + +*CONN +*I mux_top_track_2\/mux_l4_in_0_:X O *L 0 *C 38.465 108.120 +*I mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 54.490 123.925 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 54.490 123.925 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 52.485 123.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 52.440 123.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 52.433 123.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 47.860 123.760 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 47.840 123.753 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 *C 47.840 114.928 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 *C 47.820 114.920 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 *C 40.488 114.920 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 *C 40.480 114.863 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 *C 40.480 108.165 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 *C 40.435 108.120 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 *C 38.503 108.120 + +*CAP +0 mux_top_track_2\/mux_l4_in_0_:X 1e-06 +1 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0002268144 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.000192307 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 4.016761e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003227686 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0003227686 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.0004120108 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.0004120108 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.0005099076 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.0005099076 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.0003697717 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0003697717 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.0001598412 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.0001598412 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chany_top_in[5]:24 3.443199e-05 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 chany_top_in[5]:25 0.0001407905 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 chany_top_in[5]:27 0.0001652258 +18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_top_in[5]:25 3.443199e-05 +19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 chany_top_in[5]:26 0.0001407905 +20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 chany_top_in[5]:28 0.0001652258 +21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 top_left_grid_pin_34_[0]:10 0.0001429874 +22 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 top_left_grid_pin_34_[0]:9 0.0001429874 + +*RES +0 mux_top_track_2\/mux_l4_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 0.001725446 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 0.005979911 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 0.00341 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 0.001148758 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 0.00341 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.001382583 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0007163583 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.00341 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.00341 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.001790179 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_2\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001591842 //LENGTH 12.140 LUMPCC 0.000506724 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_5_:X O *L 0 *C 49.505 99.960 +*I mux_top_track_4\/mux_l2_in_2_:A0 I *L 0.001631 *C 56.295 104.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 56.258 104.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 50.645 104.380 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 50.600 104.335 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 50.600 100.005 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 50.555 99.960 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 49.543 99.960 + +*CAP +0 mux_top_track_4\/mux_l1_in_5_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_2_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0003110613 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003110613 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001424085 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001424085 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 8.808946e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 8.808946e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size14_0_sram[1]:10 3.566431e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size14_0_sram[1]:22 3.526172e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size14_0_sram[1]:22 3.566431e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size14_0_sram[1]:23 3.526172e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:9 0.0001266868 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:28 0.0001266868 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.57492e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.57492e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_5_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_4\/mux_l2_in_2_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.005011161 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.003866072 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0] 0.0006275916 //LENGTH 4.785 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_2_:X O *L 0 *C 37.545 17.000 +*I mux_bottom_track_5\/mux_l3_in_1_:A1 I *L 0.00198 *C 39.200 14.620 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 39.200 14.620 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 39.100 14.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 37.765 14.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 37.720 15.005 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 37.720 16.955 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 37.720 17.000 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 37.545 17.000 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 6.038331e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001237933 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 9.493963e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.0001211305 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0001211305 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 5.413476e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 5.007948e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_5\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.001191964 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.001741072 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:7 9.510869e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005760461 //LENGTH 3.620 LUMPCC 0.0001379628 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_1_:X O *L 0 *C 25.935 88.740 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 26.050 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 26.050 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 26.220 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 26.220 91.415 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 26.220 88.785 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 26.220 88.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 25.935 88.740 + +*CAP +0 mux_left_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.749325e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.128075e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001034784 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001034784 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.579079e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.456167e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 left_top_grid_pin_43_[0]:33 3.328899e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 left_top_grid_pin_43_[0]:32 3.328899e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:7 5.890756e-06 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:8 2.980166e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:4 5.890756e-06 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:7 2.980166e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_1_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348214 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002121616 //LENGTH 15.140 LUMPCC 0.0004294344 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 25.475 71.400 +*I mux_left_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 13.245 69.020 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 13.245 69.020 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 13.340 69.065 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 13.340 71.355 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 13.385 71.400 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 25.438 71.400 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 2.791453e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001418672 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001418672 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0006892667 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0006892667 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 chanx_left_in[9]:7 0.0001188337 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[9]:6 0.0001188337 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_5_sram[1]:8 1.153111e-06 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_5_sram[1]:10 1.664235e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_5_sram[1]:11 7.308067e-05 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_5_sram[1]:12 5.007342e-06 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_5_sram[1]:9 1.153111e-06 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_5_sram[1]:4 5.007342e-06 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_5_sram[1]:11 1.664235e-05 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size7_5_sram[1]:12 7.308067e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.002044643 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.01076116 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0] 0.005333276 //LENGTH 52.825 LUMPCC 0.0009509155 DR + +*CONN +*I mux_top_track_32\/mux_l3_in_0_:X O *L 0 *C 82.625 80.580 +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 84.105 118.455 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 84.142 118.365 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 85.975 118.320 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 86.020 118.275 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 86.020 115.305 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 86.065 115.260 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 90.115 115.260 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 90.160 115.215 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 90.160 80.625 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 90.115 80.580 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 82.663 80.580 + +*CAP +0 mux_top_track_32\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001262092 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001262092 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001808442 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001808442 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002377827 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002377827 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.001227101 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.001227101 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0004182436 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0004182436 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[9]:13 0.000349363 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chany_top_in[9]:14 0.0001260948 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[9]:12 0.000349363 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chany_top_in[9]:13 0.0001260948 + +*RES +0 mux_top_track_32\/mux_l3_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001636161 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002651786 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.003616072 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.03088393 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.006654018 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002157158 //LENGTH 18.215 LUMPCC 0.0005176727 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 81.135 53.380 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 74.980 63.580 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 75.002 63.608 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.015 63.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 75.395 63.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 75.440 63.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 76.360 63.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 76.360 53.425 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 76.405 53.380 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 81.098 53.380 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.112565e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.709378e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.596813e-05 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.474418e-05 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000537631 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004833867 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001887677 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001887677 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 chany_top_in[8]:15 0.0001869229 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 chany_top_in[8]:16 0.0001869229 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:107 1.249488e-05 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:110 3.702585e-05 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:114 2.239276e-05 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:98 3.702585e-05 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:106 1.249488e-05 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:111 2.239276e-05 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004189732 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.009370536 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003392857 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.152 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002111487 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0008214286 + +*END + +*D_NET mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002734392 //LENGTH 19.695 LUMPCC 0.0004681533 DR + +*CONN +*I mux_left_track_19\/mux_l2_in_0_:X O *L 0 *C 26.395 63.920 +*I mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.825 66.475 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 9.825 66.475 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 10.995 66.300 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 11.040 66.255 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 11.040 64.305 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 11.085 64.260 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 26.220 64.260 +*N mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 26.395 63.920 + +*CAP +0 mux_left_track_19\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001398417 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 9.769127e-05 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001486988 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001486988 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0008251489 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0008503998 +8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.375945e-05 +9 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 left_top_grid_pin_47_[0]:10 1.320596e-05 +10 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 left_top_grid_pin_47_[0]:11 0.0001056459 +11 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 left_top_grid_pin_47_[0]:5 1.320596e-05 +12 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 left_top_grid_pin_47_[0]:10 0.0001056459 +13 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_5_sram[2]:7 7.878002e-05 +14 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size7_5_sram[2]:8 7.878002e-05 +15 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 3.644481e-05 +16 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 3.644481e-05 + +*RES +0 mux_left_track_19\/mux_l2_in_0_:X mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001044643 +3 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003035715 +7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01351339 + +*END + +*D_NET ropt_net_175 0.001112395 //LENGTH 7.210 LUMPCC 0.0004055822 DR + +*CONN +*I FTB_12__11:X O *L 0 *C 59.340 7.140 +*I ropt_mt_inst_801:A I *L 0.001766 *C 62.560 4.080 +*N ropt_net_175:2 *C 62.523 4.080 +*N ropt_net_175:3 *C 60.305 4.080 +*N ropt_net_175:4 *C 60.260 4.125 +*N ropt_net_175:5 *C 60.260 7.095 +*N ropt_net_175:6 *C 60.215 7.140 +*N ropt_net_175:7 *C 59.378 7.140 + +*CAP +0 FTB_12__11:X 1e-06 +1 ropt_mt_inst_801:A 1e-06 +2 ropt_net_175:2 0.0001249814 +3 ropt_net_175:3 0.0001249814 +4 ropt_net_175:4 0.000170401 +5 ropt_net_175:5 0.000170401 +6 ropt_net_175:6 5.702395e-05 +7 ropt_net_175:7 5.702395e-05 +8 ropt_net_175:7 chany_top_in[5]:13 4.350808e-05 +9 ropt_net_175:6 chany_top_in[5]:9 4.350808e-05 +10 ropt_net_175:5 ropt_net_166:3 8.228298e-05 +11 ropt_net_175:3 ropt_net_166:5 7.700004e-05 +12 ropt_net_175:4 ropt_net_166:4 8.228298e-05 +13 ropt_net_175:2 ropt_net_166:6 7.700004e-05 + +*RES +0 FTB_12__11:X ropt_net_175:7 0.152 +1 ropt_net_175:7 ropt_net_175:6 0.0007477679 +2 ropt_net_175:6 ropt_net_175:5 0.0045 +3 ropt_net_175:5 ropt_net_175:4 0.002651786 +4 ropt_net_175:3 ropt_net_175:2 0.001979911 +5 ropt_net_175:4 ropt_net_175:3 0.0045 +6 ropt_net_175:2 ropt_mt_inst_801:A 0.152 + +*END + +*D_NET chanx_left_out[13] 0.001273936 //LENGTH 9.285 LUMPCC 0 DR + +*CONN +*I FTB_33__32:X O *L 0 *C 10.120 99.280 +*P chanx_left_out[13] O *L 0.7423 *C 1.305 99.280 +*N chanx_left_out[13]:2 *C 9.193 99.280 +*N chanx_left_out[13]:3 *C 9.200 99.280 +*N chanx_left_out[13]:4 *C 9.245 99.280 +*N chanx_left_out[13]:5 *C 10.083 99.280 + +*CAP +0 FTB_33__32:X 1e-06 +1 chanx_left_out[13] 0.0005493021 +2 chanx_left_out[13]:2 0.0005493021 +3 chanx_left_out[13]:3 3.227185e-05 +4 chanx_left_out[13]:4 7.102988e-05 +5 chanx_left_out[13]:5 7.102988e-05 + +*RES +0 FTB_33__32:X chanx_left_out[13]:5 0.152 +1 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +2 chanx_left_out[13]:2 chanx_left_out[13] 0.001235708 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.0045 +4 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0007477679 + +*END + +*D_NET ropt_net_154 0.001703221 //LENGTH 12.090 LUMPCC 0.0008145126 DR + +*CONN +*I BUFT_RR_70:X O *L 0 *C 80.960 17.000 +*I ropt_mt_inst_779:A I *L 0.001766 *C 80.960 9.520 +*N ropt_net_154:2 *C 80.922 9.520 +*N ropt_net_154:3 *C 79.165 9.520 +*N ropt_net_154:4 *C 79.120 9.565 +*N ropt_net_154:5 *C 79.120 16.955 +*N ropt_net_154:6 *C 79.165 17.000 +*N ropt_net_154:7 *C 80.922 17.000 + +*CAP +0 BUFT_RR_70:X 1e-06 +1 ropt_mt_inst_779:A 1e-06 +2 ropt_net_154:2 9.98287e-05 +3 ropt_net_154:3 9.98287e-05 +4 ropt_net_154:4 0.0002058667 +5 ropt_net_154:5 0.0002058667 +6 ropt_net_154:6 0.0001376588 +7 ropt_net_154:7 0.0001376588 +8 ropt_net_154:5 chany_bottom_in[12]:19 0.0002111745 +9 ropt_net_154:4 chany_bottom_in[12] 0.0002111745 +10 ropt_net_154:5 chany_bottom_in[19]:13 0.000119131 +11 ropt_net_154:4 chany_bottom_in[19] 0.000119131 +12 ropt_net_154:3 mux_bottom_track_1/BUF_net_60:8 7.695079e-05 +13 ropt_net_154:2 mux_bottom_track_1/BUF_net_60:7 7.695079e-05 + +*RES +0 BUFT_RR_70:X ropt_net_154:7 0.152 +1 ropt_net_154:7 ropt_net_154:6 0.001569196 +2 ropt_net_154:6 ropt_net_154:5 0.0045 +3 ropt_net_154:5 ropt_net_154:4 0.006598215 +4 ropt_net_154:3 ropt_net_154:2 0.001569196 +5 ropt_net_154:4 ropt_net_154:3 0.0045 +6 ropt_net_154:2 ropt_mt_inst_779:A 0.152 + +*END + +*D_NET ropt_net_190 0.0023509 //LENGTH 17.095 LUMPCC 0.0005624895 DR + +*CONN +*I ropt_mt_inst_804:X O *L 0 *C 76.095 124.440 +*I ropt_mt_inst_821:A I *L 0.001766 *C 70.380 126.480 +*N ropt_net_190:2 *C 70.343 126.480 +*N ropt_net_190:3 *C 69.045 126.480 +*N ropt_net_190:4 *C 69.000 126.525 +*N ropt_net_190:5 *C 69.000 128.815 +*N ropt_net_190:6 *C 69.045 128.860 +*N ropt_net_190:7 *C 76.315 128.860 +*N ropt_net_190:8 *C 76.360 128.815 +*N ropt_net_190:9 *C 76.360 124.485 +*N ropt_net_190:10 *C 76.360 124.440 +*N ropt_net_190:11 *C 76.095 124.440 + +*CAP +0 ropt_mt_inst_804:X 1e-06 +1 ropt_mt_inst_821:A 1e-06 +2 ropt_net_190:2 0.0001275721 +3 ropt_net_190:3 0.0001275721 +4 ropt_net_190:4 0.0001077488 +5 ropt_net_190:5 0.0001077488 +6 ropt_net_190:6 0.0004803252 +7 ropt_net_190:7 0.0004803252 +8 ropt_net_190:8 0.0001206464 +9 ropt_net_190:9 0.0001206464 +10 ropt_net_190:10 5.519785e-05 +11 ropt_net_190:11 5.862783e-05 +12 ropt_net_190:8 chany_top_in[11] 0.0001307254 +13 ropt_net_190:9 chany_top_in[11]:16 0.0001307254 +14 ropt_net_190:8 chany_top_out[0] 7.564362e-05 +15 ropt_net_190:9 chany_top_out[0]:2 7.564362e-05 +16 ropt_net_190:4 chany_top_out[8]:2 7.487576e-05 +17 ropt_net_190:5 chany_top_out[8] 7.487576e-05 + +*RES +0 ropt_mt_inst_804:X ropt_net_190:11 0.152 +1 ropt_net_190:2 ropt_mt_inst_821:A 0.152 +2 ropt_net_190:3 ropt_net_190:2 0.001158482 +3 ropt_net_190:4 ropt_net_190:3 0.0045 +4 ropt_net_190:6 ropt_net_190:5 0.0045 +5 ropt_net_190:5 ropt_net_190:4 0.002044643 +6 ropt_net_190:7 ropt_net_190:6 0.006491072 +7 ropt_net_190:8 ropt_net_190:7 0.0045 +8 ropt_net_190:10 ropt_net_190:9 0.0045 +9 ropt_net_190:9 ropt_net_190:8 0.003866072 +10 ropt_net_190:11 ropt_net_190:10 0.0001440217 + +*END + +*D_NET ropt_net_168 0.0009192163 //LENGTH 6.260 LUMPCC 0.0002334796 DR + +*CONN +*I BUFT_P_123:X O *L 0 *C 74.520 121.380 +*I ropt_mt_inst_794:A I *L 0.001766 *C 69.000 121.040 +*N ropt_net_168:2 *C 69.000 121.040 +*N ropt_net_168:3 *C 69.000 121.380 +*N ropt_net_168:4 *C 74.483 121.380 + +*CAP +0 BUFT_P_123:X 1e-06 +1 ropt_mt_inst_794:A 1e-06 +2 ropt_net_168:2 6.091935e-05 +3 ropt_net_168:3 0.0003263192 +4 ropt_net_168:4 0.0002964981 +5 ropt_net_168:4 chany_bottom_in[5]:9 7.005065e-05 +6 ropt_net_168:3 chany_bottom_in[5]:10 7.005065e-05 +7 ropt_net_168:4 chany_bottom_in[6]:28 4.665997e-05 +8 ropt_net_168:2 chany_bottom_in[6]:27 2.921188e-08 +9 ropt_net_168:3 chany_bottom_in[6]:26 2.921188e-08 +10 ropt_net_168:3 chany_bottom_in[6]:27 4.665997e-05 + +*RES +0 BUFT_P_123:X ropt_net_168:4 0.152 +1 ropt_net_168:4 ropt_net_168:3 0.004895089 +2 ropt_net_168:2 ropt_mt_inst_794:A 0.152 +3 ropt_net_168:3 ropt_net_168:2 0.0003035715 + +*END + +*D_NET chany_top_in[10] 0.02379793 //LENGTH 187.580 LUMPCC 0.005899118 DR + +*CONN +*P chany_top_in[10] I *L 0.29796 *C 73.140 129.270 +*I mux_left_track_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.200 45.220 +*I mux_bottom_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 25.665 30.940 +*I BUFT_RR_70:A I *L 0.001776 *C 78.660 17.680 +*N chany_top_in[10]:4 *C 78.623 17.680 +*N chany_top_in[10]:5 *C 76.865 17.680 +*N chany_top_in[10]:6 *C 76.820 17.725 +*N chany_top_in[10]:7 *C 76.820 31.575 +*N chany_top_in[10]:8 *C 76.775 31.620 +*N chany_top_in[10]:9 *C 64.400 31.620 +*N chany_top_in[10]:10 *C 64.400 31.960 +*N chany_top_in[10]:11 *C 25.703 30.940 +*N chany_top_in[10]:12 *C 27.095 30.940 +*N chany_top_in[10]:13 *C 27.140 30.985 +*N chany_top_in[10]:14 *C 27.140 31.915 +*N chany_top_in[10]:15 *C 27.185 31.960 +*N chany_top_in[10]:16 *C 55.200 31.960 +*N chany_top_in[10]:17 *C 55.200 32.005 +*N chany_top_in[10]:18 *C 55.200 45.235 +*N chany_top_in[10]:19 *C 55.200 45.560 +*N chany_top_in[10]:20 *C 55.200 45.560 +*N chany_top_in[10]:21 *C 55.200 46.183 +*N chany_top_in[10]:22 *C 55.208 46.240 +*N chany_top_in[10]:23 *C 65.300 46.240 +*N chany_top_in[10]:24 *C 65.320 46.248 +*N chany_top_in[10]:25 *C 65.320 96.075 +*N chany_top_in[10]:26 *C 65.320 125.113 +*N chany_top_in[10]:27 *C 65.340 125.120 +*N chany_top_in[10]:28 *C 73.133 125.120 +*N chany_top_in[10]:29 *C 73.140 125.178 + +*CAP +0 chany_top_in[10] 0.0002406608 +1 mux_left_track_13\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_33\/mux_l1_in_0_:A1 1e-06 +3 BUFT_RR_70:A 1e-06 +4 chany_top_in[10]:4 0.0001226414 +5 chany_top_in[10]:5 0.0001226414 +6 chany_top_in[10]:6 0.000518835 +7 chany_top_in[10]:7 0.000518835 +8 chany_top_in[10]:8 0.0006852749 +9 chany_top_in[10]:9 0.000711488 +10 chany_top_in[10]:10 0.0006393982 +11 chany_top_in[10]:11 0.0001186492 +12 chany_top_in[10]:12 0.0001186492 +13 chany_top_in[10]:13 7.814544e-05 +14 chany_top_in[10]:14 7.814544e-05 +15 chany_top_in[10]:15 0.001956871 +16 chany_top_in[10]:16 0.002604883 +17 chany_top_in[10]:17 0.0006403319 +18 chany_top_in[10]:18 3.855216e-05 +19 chany_top_in[10]:19 7.594811e-05 +20 chany_top_in[10]:20 0.000713407 +21 chany_top_in[10]:21 3.993691e-05 +22 chany_top_in[10]:22 0.0005759135 +23 chany_top_in[10]:23 0.0005759135 +24 chany_top_in[10]:24 0.001524662 +25 chany_top_in[10]:25 0.002671989 +26 chany_top_in[10]:26 0.001147327 +27 chany_top_in[10]:27 0.0005680281 +28 chany_top_in[10]:28 0.0005680281 +29 chany_top_in[10]:29 0.0002406608 +30 chany_top_in[10]:20 chany_top_in[13]:27 0.0001501015 +31 chany_top_in[10]:17 chany_top_in[13]:26 0.0001501015 +32 chany_top_in[10]:24 chany_top_in[13]:30 0.000220802 +33 chany_top_in[10]:24 chany_top_in[13]:31 0.000110443 +34 chany_top_in[10]:26 chany_top_in[13]:32 0.0003396717 +35 chany_top_in[10]:25 chany_top_in[13]:32 0.000110443 +36 chany_top_in[10]:25 chany_top_in[13]:31 0.0005604737 +37 chany_top_in[10]:24 chany_top_in[18]:20 0.0001693337 +38 chany_top_in[10]:26 chany_top_in[18]:21 0.00015966 +39 chany_top_in[10]:25 chany_top_in[18]:21 0.0001693337 +40 chany_top_in[10]:25 chany_top_in[18]:20 0.00015966 +41 chany_top_in[10]:24 chany_bottom_in[5]:25 0.0002050405 +42 chany_top_in[10]:24 chany_bottom_in[5]:24 0.0002285179 +43 chany_top_in[10]:25 chany_bottom_in[5]:23 0.0002285179 +44 chany_top_in[10]:25 chany_bottom_in[5]:24 0.0002050405 +45 chany_top_in[10]:7 chany_bottom_in[16]:27 0.0003760994 +46 chany_top_in[10]:6 chany_bottom_in[16]:28 0.0003760994 +47 chany_top_in[10]:24 chany_bottom_in[17]:28 0.0001271794 +48 chany_top_in[10]:24 chany_bottom_in[17]:27 0.0004648048 +49 chany_top_in[10]:25 chany_bottom_in[17]:26 0.0004648048 +50 chany_top_in[10]:25 chany_bottom_in[17]:27 0.0001271794 +51 chany_top_in[10]:19 mux_tree_tapbuf_size4_2_sram[0]:3 1.496792e-06 +52 chany_top_in[10]:20 mux_tree_tapbuf_size4_2_sram[0]:7 2.871035e-08 +53 chany_top_in[10]:20 mux_tree_tapbuf_size4_2_sram[0]:12 7.806169e-06 +54 chany_top_in[10]:20 mux_tree_tapbuf_size4_2_sram[0]:11 7.758095e-06 +55 chany_top_in[10]:18 mux_tree_tapbuf_size4_2_sram[0]:10 1.496792e-06 +56 chany_top_in[10]:17 mux_tree_tapbuf_size4_2_sram[0]:8 2.871035e-08 +57 chany_top_in[10]:17 mux_tree_tapbuf_size4_2_sram[0]:11 7.806169e-06 +58 chany_top_in[10]:21 mux_tree_tapbuf_size4_2_sram[0]:12 7.758095e-06 +59 chany_top_in[10]:22 mux_tree_tapbuf_size4_2_sram[0]:13 0.0002043199 +60 chany_top_in[10]:23 mux_tree_tapbuf_size4_2_sram[0]:14 0.0002043199 +61 chany_top_in[10]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001764951 +62 chany_top_in[10]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001764951 + +*RES +0 chany_top_in[10] chany_top_in[10]:29 0.003654018 +1 chany_top_in[10]:19 chany_top_in[10]:18 0.0001766305 +2 chany_top_in[10]:20 chany_top_in[10]:19 0.0045 +3 chany_top_in[10]:20 chany_top_in[10]:17 0.01210268 +4 chany_top_in[10]:18 mux_left_track_13\/mux_l1_in_0_:A1 0.152 +5 chany_top_in[10]:15 chany_top_in[10]:14 0.0045 +6 chany_top_in[10]:14 chany_top_in[10]:13 0.0008303572 +7 chany_top_in[10]:12 chany_top_in[10]:11 0.001243304 +8 chany_top_in[10]:13 chany_top_in[10]:12 0.0045 +9 chany_top_in[10]:11 mux_bottom_track_33\/mux_l1_in_0_:A1 0.152 +10 chany_top_in[10]:8 chany_top_in[10]:7 0.0045 +11 chany_top_in[10]:7 chany_top_in[10]:6 0.01236607 +12 chany_top_in[10]:5 chany_top_in[10]:4 0.001569197 +13 chany_top_in[10]:6 chany_top_in[10]:5 0.0045 +14 chany_top_in[10]:4 BUFT_RR_70:A 0.152 +15 chany_top_in[10]:16 chany_top_in[10]:15 0.0250134 +16 chany_top_in[10]:16 chany_top_in[10]:10 0.008214286 +17 chany_top_in[10]:17 chany_top_in[10]:16 0.0045 +18 chany_top_in[10]:21 chany_top_in[10]:20 0.0005558036 +19 chany_top_in[10]:22 chany_top_in[10]:21 0.00341 +20 chany_top_in[10]:23 chany_top_in[10]:22 0.001581158 +21 chany_top_in[10]:24 chany_top_in[10]:23 0.00341 +22 chany_top_in[10]:27 chany_top_in[10]:26 0.00341 +23 chany_top_in[10]:26 chany_top_in[10]:25 0.004549208 +24 chany_top_in[10]:29 chany_top_in[10]:28 0.00341 +25 chany_top_in[10]:28 chany_top_in[10]:27 0.001220825 +26 chany_top_in[10]:10 chany_top_in[10]:9 0.0003035715 +27 chany_top_in[10]:9 chany_top_in[10]:8 0.01104911 +28 chany_top_in[10]:25 chany_top_in[10]:24 0.007806308 + +*END + +*D_NET ropt_net_148 0.001833273 //LENGTH 12.540 LUMPCC 0.0005143005 DR + +*CONN +*I mux_top_track_24\/BUFT_P_117:X O *L 0 *C 89.935 127.160 +*I ropt_mt_inst_773:A I *L 0.001766 *C 81.420 123.760 +*N ropt_net_148:2 *C 81.420 123.760 +*N ropt_net_148:3 *C 81.420 123.805 +*N ropt_net_148:4 *C 81.420 127.115 +*N ropt_net_148:5 *C 81.465 127.160 +*N ropt_net_148:6 *C 89.898 127.160 + +*CAP +0 mux_top_track_24\/BUFT_P_117:X 1e-06 +1 ropt_mt_inst_773:A 1e-06 +2 ropt_net_148:2 3.537872e-05 +3 ropt_net_148:3 0.0002300164 +4 ropt_net_148:4 0.0002300164 +5 ropt_net_148:5 0.0004107804 +6 ropt_net_148:6 0.0004107804 +7 ropt_net_148:6 chany_top_in[18]:25 5.820139e-05 +8 ropt_net_148:5 chany_top_in[18]:26 5.820139e-05 +9 ropt_net_148:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001989489 +10 ropt_net_148:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001989489 + +*RES +0 mux_top_track_24\/BUFT_P_117:X ropt_net_148:6 0.152 +1 ropt_net_148:6 ropt_net_148:5 0.007529019 +2 ropt_net_148:5 ropt_net_148:4 0.0045 +3 ropt_net_148:4 ropt_net_148:3 0.002955357 +4 ropt_net_148:2 ropt_mt_inst_773:A 0.152 +5 ropt_net_148:3 ropt_net_148:2 0.0045 + +*END + +*D_NET chany_bottom_out[12] 0.001969571 //LENGTH 15.735 LUMPCC 0.0001612234 DR + +*CONN +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 84.240 11.900 +*P chany_bottom_out[12] O *L 0.7423 *C 80.500 1.290 +*N chany_bottom_out[12]:2 *C 80.500 9.135 +*N chany_bottom_out[12]:3 *C 80.545 9.180 +*N chany_bottom_out[12]:4 *C 82.340 9.180 +*N chany_bottom_out[12]:5 *C 82.340 9.520 +*N chany_bottom_out[12]:6 *C 83.675 9.520 +*N chany_bottom_out[12]:7 *C 83.720 9.565 +*N chany_bottom_out[12]:8 *C 83.720 11.855 +*N chany_bottom_out[12]:9 *C 83.765 11.900 +*N chany_bottom_out[12]:10 *C 84.203 11.900 + +*CAP +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[12] 0.0004600385 +2 chany_bottom_out[12]:2 0.0004600385 +3 chany_bottom_out[12]:3 0.0001589136 +4 chany_bottom_out[12]:4 0.0001824106 +5 chany_bottom_out[12]:5 0.0001038053 +6 chany_bottom_out[12]:6 8.030825e-05 +7 chany_bottom_out[12]:7 0.0001254498 +8 chany_bottom_out[12]:8 0.0001254498 +9 chany_bottom_out[12]:9 5.546655e-05 +10 chany_bottom_out[12]:10 5.546655e-05 +11 chany_bottom_out[12]:8 mux_bottom_track_1/BUF_net_60:6 8.850057e-06 +12 chany_bottom_out[12]:6 mux_bottom_track_1/BUF_net_60:7 5.97878e-05 +13 chany_bottom_out[12]:7 mux_bottom_track_1/BUF_net_60:5 8.850057e-06 +14 chany_bottom_out[12]:3 mux_bottom_track_1/BUF_net_60:8 1.197384e-05 +15 chany_bottom_out[12]:4 mux_bottom_track_1/BUF_net_60:7 1.197384e-05 +16 chany_bottom_out[12]:5 mux_bottom_track_1/BUF_net_60:8 5.97878e-05 + +*RES +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[12]:10 0.152 +1 chany_bottom_out[12]:10 chany_bottom_out[12]:9 0.000390625 +2 chany_bottom_out[12]:9 chany_bottom_out[12]:8 0.0045 +3 chany_bottom_out[12]:8 chany_bottom_out[12]:7 0.002044643 +4 chany_bottom_out[12]:6 chany_bottom_out[12]:5 0.001191964 +5 chany_bottom_out[12]:7 chany_bottom_out[12]:6 0.0045 +6 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +7 chany_bottom_out[12]:2 chany_bottom_out[12] 0.007004464 +8 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.001602679 +9 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[1] 0.01098208 //LENGTH 81.555 LUMPCC 0.002252389 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 48.890 120.360 +*I mux_top_track_0\/mux_l2_in_0_:S I *L 0.00357 *C 40.580 117.640 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.655 98.940 +*I mux_top_track_0\/mux_l2_in_3_:S I *L 0.00357 *C 11.400 93.840 +*I mux_top_track_0\/mux_l2_in_2_:S I *L 0.00357 *C 11.860 89.080 +*I mux_top_track_0\/mux_l2_in_1_:S I *L 0.00357 *C 56.220 121.040 +*N mux_tree_tapbuf_size10_0_sram[1]:6 *C 56.183 121.040 +*N mux_tree_tapbuf_size10_0_sram[1]:7 *C 54.785 121.040 +*N mux_tree_tapbuf_size10_0_sram[1]:8 *C 54.740 120.995 +*N mux_tree_tapbuf_size10_0_sram[1]:9 *C 54.740 119.738 +*N mux_tree_tapbuf_size10_0_sram[1]:10 *C 54.733 119.680 +*N mux_tree_tapbuf_size10_0_sram[1]:11 *C 11.845 89.080 +*N mux_tree_tapbuf_size10_0_sram[1]:12 *C 11.523 89.080 +*N mux_tree_tapbuf_size10_0_sram[1]:13 *C 11.500 89.125 +*N mux_tree_tapbuf_size10_0_sram[1]:14 *C 11.400 93.840 +*N mux_tree_tapbuf_size10_0_sram[1]:15 *C 11.500 93.840 +*N mux_tree_tapbuf_size10_0_sram[1]:16 *C 11.500 98.555 +*N mux_tree_tapbuf_size10_0_sram[1]:17 *C 11.545 98.600 +*N mux_tree_tapbuf_size10_0_sram[1]:18 *C 17.480 98.600 +*N mux_tree_tapbuf_size10_0_sram[1]:19 *C 17.693 98.940 +*N mux_tree_tapbuf_size10_0_sram[1]:20 *C 30.775 98.940 +*N mux_tree_tapbuf_size10_0_sram[1]:21 *C 30.820 98.985 +*N mux_tree_tapbuf_size10_0_sram[1]:22 *C 30.820 117.595 +*N mux_tree_tapbuf_size10_0_sram[1]:23 *C 30.865 117.640 +*N mux_tree_tapbuf_size10_0_sram[1]:24 *C 40.580 117.663 +*N mux_tree_tapbuf_size10_0_sram[1]:25 *C 40.600 118.320 +*N mux_tree_tapbuf_size10_0_sram[1]:26 *C 40.655 118.320 +*N mux_tree_tapbuf_size10_0_sram[1]:27 *C 43.195 118.320 +*N mux_tree_tapbuf_size10_0_sram[1]:28 *C 43.240 118.365 +*N mux_tree_tapbuf_size10_0_sram[1]:29 *C 43.240 119.623 +*N mux_tree_tapbuf_size10_0_sram[1]:30 *C 43.248 119.680 +*N mux_tree_tapbuf_size10_0_sram[1]:31 *C 48.760 119.680 +*N mux_tree_tapbuf_size10_0_sram[1]:32 *C 48.760 119.738 +*N mux_tree_tapbuf_size10_0_sram[1]:33 *C 48.760 120.315 +*N mux_tree_tapbuf_size10_0_sram[1]:34 *C 48.760 120.360 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:S 1e-06 +2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_0\/mux_l2_in_3_:S 1e-06 +4 mux_top_track_0\/mux_l2_in_2_:S 1e-06 +5 mux_top_track_0\/mux_l2_in_1_:S 1e-06 +6 mux_tree_tapbuf_size10_0_sram[1]:6 0.0001529724 +7 mux_tree_tapbuf_size10_0_sram[1]:7 0.0001529724 +8 mux_tree_tapbuf_size10_0_sram[1]:8 9.164235e-05 +9 mux_tree_tapbuf_size10_0_sram[1]:9 9.164235e-05 +10 mux_tree_tapbuf_size10_0_sram[1]:10 0.0004843612 +11 mux_tree_tapbuf_size10_0_sram[1]:11 5.762023e-05 +12 mux_tree_tapbuf_size10_0_sram[1]:12 5.762023e-05 +13 mux_tree_tapbuf_size10_0_sram[1]:13 0.0002293745 +14 mux_tree_tapbuf_size10_0_sram[1]:14 3.549629e-05 +15 mux_tree_tapbuf_size10_0_sram[1]:15 0.0005122976 +16 mux_tree_tapbuf_size10_0_sram[1]:16 0.0002496339 +17 mux_tree_tapbuf_size10_0_sram[1]:17 0.0003740581 +18 mux_tree_tapbuf_size10_0_sram[1]:18 0.000396144 +19 mux_tree_tapbuf_size10_0_sram[1]:19 0.0007117772 +20 mux_tree_tapbuf_size10_0_sram[1]:20 0.0006896913 +21 mux_tree_tapbuf_size10_0_sram[1]:21 0.0005583646 +22 mux_tree_tapbuf_size10_0_sram[1]:22 0.0005583646 +23 mux_tree_tapbuf_size10_0_sram[1]:23 0.0006245566 +24 mux_tree_tapbuf_size10_0_sram[1]:24 0.0006712835 +25 mux_tree_tapbuf_size10_0_sram[1]:25 5.740899e-05 +26 mux_tree_tapbuf_size10_0_sram[1]:26 0.0001443709 +27 mux_tree_tapbuf_size10_0_sram[1]:27 0.0001336888 +28 mux_tree_tapbuf_size10_0_sram[1]:28 8.595185e-05 +29 mux_tree_tapbuf_size10_0_sram[1]:29 8.595185e-05 +30 mux_tree_tapbuf_size10_0_sram[1]:30 0.0004363756 +31 mux_tree_tapbuf_size10_0_sram[1]:31 0.0009207368 +32 mux_tree_tapbuf_size10_0_sram[1]:32 6.237559e-05 +33 mux_tree_tapbuf_size10_0_sram[1]:33 6.237559e-05 +34 mux_tree_tapbuf_size10_0_sram[1]:34 3.457881e-05 +35 mux_tree_tapbuf_size10_0_sram[1]:17 left_top_grid_pin_43_[0]:5 2.94502e-05 +36 mux_tree_tapbuf_size10_0_sram[1]:20 left_top_grid_pin_43_[0]:34 1.178352e-05 +37 mux_tree_tapbuf_size10_0_sram[1]:21 left_top_grid_pin_43_[0]:32 2.865686e-08 +38 mux_tree_tapbuf_size10_0_sram[1]:21 left_top_grid_pin_43_[0]:36 0.0005085287 +39 mux_tree_tapbuf_size10_0_sram[1]:22 left_top_grid_pin_43_[0]:33 2.865686e-08 +40 mux_tree_tapbuf_size10_0_sram[1]:22 left_top_grid_pin_43_[0]:37 0.0005085287 +41 mux_tree_tapbuf_size10_0_sram[1]:19 left_top_grid_pin_43_[0]:8 1.178352e-05 +42 mux_tree_tapbuf_size10_0_sram[1]:18 left_top_grid_pin_43_[0]:6 2.94502e-05 +43 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:24 3.226752e-05 +44 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:23 2.235292e-05 +45 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size8_0_sram[1]:22 0.0001422815 +46 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:25 0.0001622405 +47 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:8 3.963846e-06 +48 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:16 1.27373e-05 +49 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size8_0_sram[1]:27 4.440521e-05 +50 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:25 1.27373e-05 +51 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:28 4.440521e-05 +52 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:26 0.0001622405 +53 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size8_0_sram[1]:27 3.963846e-06 +54 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:23 3.226752e-05 +55 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:21 0.0001422815 +56 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size8_0_sram[1]:22 2.235292e-05 +57 mux_tree_tapbuf_size10_0_sram[1]:29 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.63289e-06 +58 mux_tree_tapbuf_size10_0_sram[1]:27 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.853416e-05 +59 mux_tree_tapbuf_size10_0_sram[1]:28 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.63289e-06 +60 mux_tree_tapbuf_size10_0_sram[1]:26 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.853416e-05 +61 mux_tree_tapbuf_size10_0_sram[1]:16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 2.786101e-05 +62 mux_tree_tapbuf_size10_0_sram[1]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.512684e-05 +63 mux_tree_tapbuf_size10_0_sram[1]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 2.786101e-05 +64 mux_tree_tapbuf_size10_0_sram[1]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.512684e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_0_sram[1]:34 0.152 +1 mux_tree_tapbuf_size10_0_sram[1]:34 mux_tree_tapbuf_size10_0_sram[1]:33 0.0045 +2 mux_tree_tapbuf_size10_0_sram[1]:33 mux_tree_tapbuf_size10_0_sram[1]:32 0.000515625 +3 mux_tree_tapbuf_size10_0_sram[1]:32 mux_tree_tapbuf_size10_0_sram[1]:31 0.00341 +4 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:30 0.0008636249 +5 mux_tree_tapbuf_size10_0_sram[1]:31 mux_tree_tapbuf_size10_0_sram[1]:10 0.0009356916 +6 mux_tree_tapbuf_size10_0_sram[1]:29 mux_tree_tapbuf_size10_0_sram[1]:28 0.001122768 +7 mux_tree_tapbuf_size10_0_sram[1]:30 mux_tree_tapbuf_size10_0_sram[1]:29 0.00341 +8 mux_tree_tapbuf_size10_0_sram[1]:27 mux_tree_tapbuf_size10_0_sram[1]:26 0.002267857 +9 mux_tree_tapbuf_size10_0_sram[1]:28 mux_tree_tapbuf_size10_0_sram[1]:27 0.0045 +10 mux_tree_tapbuf_size10_0_sram[1]:17 mux_tree_tapbuf_size10_0_sram[1]:16 0.0045 +11 mux_tree_tapbuf_size10_0_sram[1]:16 mux_tree_tapbuf_size10_0_sram[1]:15 0.004209822 +12 mux_tree_tapbuf_size10_0_sram[1]:9 mux_tree_tapbuf_size10_0_sram[1]:8 0.001122768 +13 mux_tree_tapbuf_size10_0_sram[1]:10 mux_tree_tapbuf_size10_0_sram[1]:9 0.00341 +14 mux_tree_tapbuf_size10_0_sram[1]:7 mux_tree_tapbuf_size10_0_sram[1]:6 0.001247768 +15 mux_tree_tapbuf_size10_0_sram[1]:8 mux_tree_tapbuf_size10_0_sram[1]:7 0.0045 +16 mux_tree_tapbuf_size10_0_sram[1]:6 mux_top_track_0\/mux_l2_in_1_:S 0.152 +17 mux_tree_tapbuf_size10_0_sram[1]:20 mux_tree_tapbuf_size10_0_sram[1]:19 0.0116808 +18 mux_tree_tapbuf_size10_0_sram[1]:21 mux_tree_tapbuf_size10_0_sram[1]:20 0.0045 +19 mux_tree_tapbuf_size10_0_sram[1]:23 mux_tree_tapbuf_size10_0_sram[1]:22 0.0045 +20 mux_tree_tapbuf_size10_0_sram[1]:22 mux_tree_tapbuf_size10_0_sram[1]:21 0.01661607 +21 mux_tree_tapbuf_size10_0_sram[1]:19 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +22 mux_tree_tapbuf_size10_0_sram[1]:19 mux_tree_tapbuf_size10_0_sram[1]:18 0.0003035715 +23 mux_tree_tapbuf_size10_0_sram[1]:14 mux_top_track_0\/mux_l2_in_3_:S 0.152 +24 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:14 0.0045 +25 mux_tree_tapbuf_size10_0_sram[1]:15 mux_tree_tapbuf_size10_0_sram[1]:13 0.004209822 +26 mux_tree_tapbuf_size10_0_sram[1]:12 mux_tree_tapbuf_size10_0_sram[1]:11 0.0001752718 +27 mux_tree_tapbuf_size10_0_sram[1]:13 mux_tree_tapbuf_size10_0_sram[1]:12 0.0045 +28 mux_tree_tapbuf_size10_0_sram[1]:11 mux_top_track_0\/mux_l2_in_2_:S 0.152 +29 mux_tree_tapbuf_size10_0_sram[1]:24 mux_top_track_0\/mux_l2_in_0_:S 0.152 +30 mux_tree_tapbuf_size10_0_sram[1]:24 mux_tree_tapbuf_size10_0_sram[1]:23 0.008674107 +31 mux_tree_tapbuf_size10_0_sram[1]:18 mux_tree_tapbuf_size10_0_sram[1]:17 0.005299108 +32 mux_tree_tapbuf_size10_0_sram[1]:25 mux_tree_tapbuf_size10_0_sram[1]:24 0.0005870535 +33 mux_tree_tapbuf_size10_0_sram[1]:26 mux_tree_tapbuf_size10_0_sram[1]:25 4.910714e-05 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.003111972 //LENGTH 22.450 LUMPCC 0.0005191314 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 17.325 58.480 +*I mux_left_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 19.420 61.200 +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 19.495 55.420 +*I mux_left_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 29.080 53.040 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 28.980 53.040 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 28.980 53.085 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 28.980 53.675 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 28.935 53.720 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 20.285 53.720 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 20.240 53.765 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 19.533 55.420 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 20.195 55.420 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 20.240 55.420 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 20.240 58.435 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 20.195 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 19.320 61.200 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 19.320 61.155 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 19.320 58.525 +*N mux_tree_tapbuf_size3_0_sram[0]:18 *C 19.320 58.480 +*N mux_tree_tapbuf_size3_0_sram[0]:19 *C 17.363 58.480 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_17\/mux_l1_in_1_:S 1e-06 +2 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_17\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 3.032578e-05 +5 mux_tree_tapbuf_size3_0_sram[0]:5 5.17491e-05 +6 mux_tree_tapbuf_size3_0_sram[0]:6 5.17491e-05 +7 mux_tree_tapbuf_size3_0_sram[0]:7 0.0005769785 +8 mux_tree_tapbuf_size3_0_sram[0]:8 0.0005769785 +9 mux_tree_tapbuf_size3_0_sram[0]:9 7.107923e-05 +10 mux_tree_tapbuf_size3_0_sram[0]:10 8.140229e-05 +11 mux_tree_tapbuf_size3_0_sram[0]:11 8.140229e-05 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0002294486 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0001250182 +14 mux_tree_tapbuf_size3_0_sram[0]:14 8.222902e-05 +15 mux_tree_tapbuf_size3_0_sram[0]:15 3.672374e-05 +16 mux_tree_tapbuf_size3_0_sram[0]:16 8.779117e-05 +17 mux_tree_tapbuf_size3_0_sram[0]:17 8.779117e-05 +18 mux_tree_tapbuf_size3_0_sram[0]:18 0.0002685633 +19 mux_tree_tapbuf_size3_0_sram[0]:19 0.0001496105 +20 mux_tree_tapbuf_size3_0_sram[0]:16 chanx_left_in[9]:8 7.419498e-05 +21 mux_tree_tapbuf_size3_0_sram[0]:17 chanx_left_in[9]:5 7.419498e-05 +22 mux_tree_tapbuf_size3_0_sram[0]:9 chanx_left_in[9]:5 4.717578e-05 +23 mux_tree_tapbuf_size3_0_sram[0]:12 chanx_left_in[9]:5 8.098906e-05 +24 mux_tree_tapbuf_size3_0_sram[0]:12 chanx_left_in[9]:8 4.717578e-05 +25 mux_tree_tapbuf_size3_0_sram[0]:13 chanx_left_in[9]:8 8.098906e-05 +26 mux_tree_tapbuf_size3_0_sram[0]:16 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.711061e-05 +27 mux_tree_tapbuf_size3_0_sram[0]:17 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.711061e-05 +28 mux_tree_tapbuf_size3_0_sram[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.526801e-08 +29 mux_tree_tapbuf_size3_0_sram[0]:12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.526801e-08 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:19 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:15 mux_left_track_17\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0045 +3 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:17 0.0045 +4 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:14 0.00078125 +5 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.002348214 +6 mux_tree_tapbuf_size3_0_sram[0]:19 mux_tree_tapbuf_size3_0_sram[0]:18 0.001747768 +7 mux_tree_tapbuf_size3_0_sram[0]:8 mux_tree_tapbuf_size3_0_sram[0]:7 0.007723215 +8 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size3_0_sram[0]:7 mux_tree_tapbuf_size3_0_sram[0]:6 0.0045 +10 mux_tree_tapbuf_size3_0_sram[0]:6 mux_tree_tapbuf_size3_0_sram[0]:5 0.0005267857 +11 mux_tree_tapbuf_size3_0_sram[0]:4 mux_left_track_17\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 0.0045 +13 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.0005915179 +14 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.0045 +15 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:9 0.001477679 +16 mux_tree_tapbuf_size3_0_sram[0]:10 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +17 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.0045 +18 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.002691964 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[0] 0.002926031 //LENGTH 25.775 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 72.985 55.760 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 66.875 60.860 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 81.980 52.360 +*N mux_tree_tapbuf_size4_0_sram[0]:3 *C 81.880 52.360 +*N mux_tree_tapbuf_size4_0_sram[0]:4 *C 81.880 52.405 +*N mux_tree_tapbuf_size4_0_sram[0]:5 *C 81.880 55.715 +*N mux_tree_tapbuf_size4_0_sram[0]:6 *C 81.835 55.760 +*N mux_tree_tapbuf_size4_0_sram[0]:7 *C 66.903 60.838 +*N mux_tree_tapbuf_size4_0_sram[0]:8 *C 67.160 60.825 +*N mux_tree_tapbuf_size4_0_sram[0]:9 *C 67.160 60.520 +*N mux_tree_tapbuf_size4_0_sram[0]:10 *C 71.715 60.520 +*N mux_tree_tapbuf_size4_0_sram[0]:11 *C 71.760 60.475 +*N mux_tree_tapbuf_size4_0_sram[0]:12 *C 71.760 56.485 +*N mux_tree_tapbuf_size4_0_sram[0]:13 *C 71.805 56.440 +*N mux_tree_tapbuf_size4_0_sram[0]:14 *C 73.095 56.440 +*N mux_tree_tapbuf_size4_0_sram[0]:15 *C 73.140 56.395 +*N mux_tree_tapbuf_size4_0_sram[0]:16 *C 73.140 55.805 +*N mux_tree_tapbuf_size4_0_sram[0]:17 *C 73.185 55.760 +*N mux_tree_tapbuf_size4_0_sram[0]:18 *C 72.985 55.760 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_0_sram[0]:3 2.90114e-05 +4 mux_tree_tapbuf_size4_0_sram[0]:4 0.0001880041 +5 mux_tree_tapbuf_size4_0_sram[0]:5 0.0001880041 +6 mux_tree_tapbuf_size4_0_sram[0]:6 0.0004706533 +7 mux_tree_tapbuf_size4_0_sram[0]:7 3.421368e-05 +8 mux_tree_tapbuf_size4_0_sram[0]:8 5.976162e-05 +9 mux_tree_tapbuf_size4_0_sram[0]:9 0.0003471947 +10 mux_tree_tapbuf_size4_0_sram[0]:10 0.0003216468 +11 mux_tree_tapbuf_size4_0_sram[0]:11 0.0002181203 +12 mux_tree_tapbuf_size4_0_sram[0]:12 0.0002181203 +13 mux_tree_tapbuf_size4_0_sram[0]:13 0.000112024 +14 mux_tree_tapbuf_size4_0_sram[0]:14 0.000112024 +15 mux_tree_tapbuf_size4_0_sram[0]:15 5.194959e-05 +16 mux_tree_tapbuf_size4_0_sram[0]:16 5.194959e-05 +17 mux_tree_tapbuf_size4_0_sram[0]:17 0.0004821518 +18 mux_tree_tapbuf_size4_0_sram[0]:18 3.820159e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_0_sram[0]:18 0.152 +1 mux_tree_tapbuf_size4_0_sram[0]:6 mux_tree_tapbuf_size4_0_sram[0]:5 0.0045 +2 mux_tree_tapbuf_size4_0_sram[0]:5 mux_tree_tapbuf_size4_0_sram[0]:4 0.002955357 +3 mux_tree_tapbuf_size4_0_sram[0]:3 mux_left_track_9\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size4_0_sram[0]:4 mux_tree_tapbuf_size4_0_sram[0]:3 0.0045 +5 mux_tree_tapbuf_size4_0_sram[0]:17 mux_tree_tapbuf_size4_0_sram[0]:16 0.0045 +6 mux_tree_tapbuf_size4_0_sram[0]:17 mux_tree_tapbuf_size4_0_sram[0]:6 0.007723214 +7 mux_tree_tapbuf_size4_0_sram[0]:16 mux_tree_tapbuf_size4_0_sram[0]:15 0.0005267857 +8 mux_tree_tapbuf_size4_0_sram[0]:14 mux_tree_tapbuf_size4_0_sram[0]:13 0.001151786 +9 mux_tree_tapbuf_size4_0_sram[0]:15 mux_tree_tapbuf_size4_0_sram[0]:14 0.0045 +10 mux_tree_tapbuf_size4_0_sram[0]:13 mux_tree_tapbuf_size4_0_sram[0]:12 0.0045 +11 mux_tree_tapbuf_size4_0_sram[0]:12 mux_tree_tapbuf_size4_0_sram[0]:11 0.0035625 +12 mux_tree_tapbuf_size4_0_sram[0]:10 mux_tree_tapbuf_size4_0_sram[0]:9 0.004066965 +13 mux_tree_tapbuf_size4_0_sram[0]:11 mux_tree_tapbuf_size4_0_sram[0]:10 0.0045 +14 mux_tree_tapbuf_size4_0_sram[0]:7 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size4_0_sram[0]:18 mux_tree_tapbuf_size4_0_sram[0]:17 0.0001086957 +16 mux_tree_tapbuf_size4_0_sram[0]:8 mux_tree_tapbuf_size4_0_sram[0]:7 0.0001739865 +17 mux_tree_tapbuf_size4_0_sram[0]:9 mux_tree_tapbuf_size4_0_sram[0]:8 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[0] 0.002118014 //LENGTH 16.735 LUMPCC 0.0002926479 DR + +*CONN +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 43.085 50.320 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 41.115 53.380 +*I mux_left_track_15\/mux_l1_in_0_:S I *L 0.00357 *C 53.920 53.320 +*N mux_tree_tapbuf_size4_3_sram[0]:3 *C 53.920 53.320 +*N mux_tree_tapbuf_size4_3_sram[0]:4 *C 41.153 53.380 +*N mux_tree_tapbuf_size4_3_sram[0]:5 *C 43.240 53.380 +*N mux_tree_tapbuf_size4_3_sram[0]:6 *C 43.240 53.335 +*N mux_tree_tapbuf_size4_3_sram[0]:7 *C 43.240 50.365 +*N mux_tree_tapbuf_size4_3_sram[0]:8 *C 43.240 50.320 +*N mux_tree_tapbuf_size4_3_sram[0]:9 *C 43.085 50.320 + +*CAP +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_15\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_3_sram[0]:3 0.0006041627 +4 mux_tree_tapbuf_size4_3_sram[0]:4 0.0001388161 +5 mux_tree_tapbuf_size4_3_sram[0]:5 0.0007388009 +6 mux_tree_tapbuf_size4_3_sram[0]:6 0.0001209714 +7 mux_tree_tapbuf_size4_3_sram[0]:7 0.0001209714 +8 mux_tree_tapbuf_size4_3_sram[0]:8 5.162505e-05 +9 mux_tree_tapbuf_size4_3_sram[0]:9 4.701825e-05 +10 mux_tree_tapbuf_size4_3_sram[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.253921e-05 +11 mux_tree_tapbuf_size4_3_sram[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 7.166861e-05 +12 mux_tree_tapbuf_size4_3_sram[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 2.963431e-06 +13 mux_tree_tapbuf_size4_3_sram[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.253921e-05 +14 mux_tree_tapbuf_size4_3_sram[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 7.166861e-05 +15 mux_tree_tapbuf_size4_3_sram[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 2.963431e-06 +16 mux_tree_tapbuf_size4_3_sram[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.915269e-05 +17 mux_tree_tapbuf_size4_3_sram[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.915269e-05 + +*RES +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_3_sram[0]:9 0.152 +1 mux_tree_tapbuf_size4_3_sram[0]:3 mux_left_track_15\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_3_sram[0]:4 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +3 mux_tree_tapbuf_size4_3_sram[0]:5 mux_tree_tapbuf_size4_3_sram[0]:4 0.001863839 +4 mux_tree_tapbuf_size4_3_sram[0]:5 mux_tree_tapbuf_size4_3_sram[0]:3 0.009535715 +5 mux_tree_tapbuf_size4_3_sram[0]:6 mux_tree_tapbuf_size4_3_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size4_3_sram[0]:8 mux_tree_tapbuf_size4_3_sram[0]:7 0.0045 +7 mux_tree_tapbuf_size4_3_sram[0]:7 mux_tree_tapbuf_size4_3_sram[0]:6 0.002651786 +8 mux_tree_tapbuf_size4_3_sram[0]:9 mux_tree_tapbuf_size4_3_sram[0]:8 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.0009148569 //LENGTH 7.140 LUMPCC 9.843893e-05 DR + +*CONN +*I mem_top_track_32\/FTB_15__47:X O *L 0 *C 78.885 74.460 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 75.155 71.740 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 75.193 71.740 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 78.615 71.740 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 78.660 71.785 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 78.660 74.415 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 78.660 74.460 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 78.885 74.460 + +*CAP +0 mem_top_track_32\/FTB_15__47:X 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.0002259821 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0002259821 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001241591 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001241591 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 5.782483e-05 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 5.63107e-05 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 chany_bottom_in[18]:12 3.848251e-05 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 chany_bottom_in[18]:13 1.073695e-05 +10 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 chany_bottom_in[18]:13 3.848251e-05 +11 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 chany_bottom_in[18]:14 1.073695e-05 + +*RES +0 mem_top_track_32\/FTB_15__47:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002348214 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.003055803 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[1] 0.003385129 //LENGTH 27.780 LUMPCC 0.00042642 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 45.385 86.020 +*I mux_top_track_24\/mux_l2_in_1_:S I *L 0.00357 *C 36.700 85.000 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 37.890 93.500 +*I mux_top_track_24\/mux_l2_in_0_:S I *L 0.00357 *C 39.920 88.695 +*N mux_tree_tapbuf_size7_1_sram[1]:4 *C 39.958 88.740 +*N mux_tree_tapbuf_size7_1_sram[1]:5 *C 37.852 93.500 +*N mux_tree_tapbuf_size7_1_sram[1]:6 *C 37.305 93.500 +*N mux_tree_tapbuf_size7_1_sram[1]:7 *C 37.260 93.455 +*N mux_tree_tapbuf_size7_1_sram[1]:8 *C 37.260 88.740 +*N mux_tree_tapbuf_size7_1_sram[1]:9 *C 36.700 85.000 +*N mux_tree_tapbuf_size7_1_sram[1]:10 *C 36.800 85.045 +*N mux_tree_tapbuf_size7_1_sram[1]:11 *C 36.800 88.740 +*N mux_tree_tapbuf_size7_1_sram[1]:12 *C 36.800 90.735 +*N mux_tree_tapbuf_size7_1_sram[1]:13 *C 36.845 90.780 +*N mux_tree_tapbuf_size7_1_sram[1]:14 *C 40.435 90.780 +*N mux_tree_tapbuf_size7_1_sram[1]:15 *C 40.480 90.735 +*N mux_tree_tapbuf_size7_1_sram[1]:16 *C 40.480 88.785 +*N mux_tree_tapbuf_size7_1_sram[1]:17 *C 40.480 88.740 +*N mux_tree_tapbuf_size7_1_sram[1]:18 *C 45.035 88.740 +*N mux_tree_tapbuf_size7_1_sram[1]:19 *C 45.080 88.695 +*N mux_tree_tapbuf_size7_1_sram[1]:20 *C 45.080 86.065 +*N mux_tree_tapbuf_size7_1_sram[1]:21 *C 45.080 86.020 +*N mux_tree_tapbuf_size7_1_sram[1]:22 *C 45.385 86.020 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_24\/mux_l2_in_1_:S 1e-06 +2 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_top_track_24\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size7_1_sram[1]:4 4.263296e-05 +5 mux_tree_tapbuf_size7_1_sram[1]:5 8.212987e-05 +6 mux_tree_tapbuf_size7_1_sram[1]:6 8.212987e-05 +7 mux_tree_tapbuf_size7_1_sram[1]:7 0.0002538743 +8 mux_tree_tapbuf_size7_1_sram[1]:8 0.0002833587 +9 mux_tree_tapbuf_size7_1_sram[1]:9 2.715059e-05 +10 mux_tree_tapbuf_size7_1_sram[1]:10 0.0001880017 +11 mux_tree_tapbuf_size7_1_sram[1]:11 0.0002918649 +12 mux_tree_tapbuf_size7_1_sram[1]:12 7.437879e-05 +13 mux_tree_tapbuf_size7_1_sram[1]:13 0.0001708702 +14 mux_tree_tapbuf_size7_1_sram[1]:14 0.0001708702 +15 mux_tree_tapbuf_size7_1_sram[1]:15 0.0001291408 +16 mux_tree_tapbuf_size7_1_sram[1]:16 0.0001291408 +17 mux_tree_tapbuf_size7_1_sram[1]:17 0.0003541684 +18 mux_tree_tapbuf_size7_1_sram[1]:18 0.0002811073 +19 mux_tree_tapbuf_size7_1_sram[1]:19 0.0001477143 +20 mux_tree_tapbuf_size7_1_sram[1]:20 0.0001477143 +21 mux_tree_tapbuf_size7_1_sram[1]:21 5.293868e-05 +22 mux_tree_tapbuf_size7_1_sram[1]:22 4.552233e-05 +23 mux_tree_tapbuf_size7_1_sram[1]:10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 2.566075e-05 +24 mux_tree_tapbuf_size7_1_sram[1]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 6.692021e-05 +25 mux_tree_tapbuf_size7_1_sram[1]:13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001110517 +26 mux_tree_tapbuf_size7_1_sram[1]:12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.577292e-06 +27 mux_tree_tapbuf_size7_1_sram[1]:14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001110517 +28 mux_tree_tapbuf_size7_1_sram[1]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 2.566075e-05 +29 mux_tree_tapbuf_size7_1_sram[1]:11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.577292e-06 +30 mux_tree_tapbuf_size7_1_sram[1]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 6.692021e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_1_sram[1]:22 0.152 +1 mux_tree_tapbuf_size7_1_sram[1]:9 mux_top_track_24\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_1_sram[1]:10 mux_tree_tapbuf_size7_1_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size7_1_sram[1]:5 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +4 mux_tree_tapbuf_size7_1_sram[1]:6 mux_tree_tapbuf_size7_1_sram[1]:5 0.0004888393 +5 mux_tree_tapbuf_size7_1_sram[1]:7 mux_tree_tapbuf_size7_1_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size7_1_sram[1]:13 mux_tree_tapbuf_size7_1_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size7_1_sram[1]:12 mux_tree_tapbuf_size7_1_sram[1]:11 0.00178125 +8 mux_tree_tapbuf_size7_1_sram[1]:14 mux_tree_tapbuf_size7_1_sram[1]:13 0.003205357 +9 mux_tree_tapbuf_size7_1_sram[1]:15 mux_tree_tapbuf_size7_1_sram[1]:14 0.0045 +10 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:16 0.0045 +11 mux_tree_tapbuf_size7_1_sram[1]:17 mux_tree_tapbuf_size7_1_sram[1]:4 0.0004665179 +12 mux_tree_tapbuf_size7_1_sram[1]:16 mux_tree_tapbuf_size7_1_sram[1]:15 0.001741071 +13 mux_tree_tapbuf_size7_1_sram[1]:4 mux_top_track_24\/mux_l2_in_0_:S 0.152 +14 mux_tree_tapbuf_size7_1_sram[1]:22 mux_tree_tapbuf_size7_1_sram[1]:21 0.0001657609 +15 mux_tree_tapbuf_size7_1_sram[1]:21 mux_tree_tapbuf_size7_1_sram[1]:20 0.0045 +16 mux_tree_tapbuf_size7_1_sram[1]:20 mux_tree_tapbuf_size7_1_sram[1]:19 0.002348214 +17 mux_tree_tapbuf_size7_1_sram[1]:18 mux_tree_tapbuf_size7_1_sram[1]:17 0.004066965 +18 mux_tree_tapbuf_size7_1_sram[1]:19 mux_tree_tapbuf_size7_1_sram[1]:18 0.0045 +19 mux_tree_tapbuf_size7_1_sram[1]:11 mux_tree_tapbuf_size7_1_sram[1]:10 0.003299108 +20 mux_tree_tapbuf_size7_1_sram[1]:11 mux_tree_tapbuf_size7_1_sram[1]:8 0.0004107143 +21 mux_tree_tapbuf_size7_1_sram[1]:8 mux_tree_tapbuf_size7_1_sram[1]:7 0.004209822 + +*END + +*D_NET mux_tree_tapbuf_size7_5_sram[0] 0.008058029 //LENGTH 50.145 LUMPCC 0.002975274 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 13.645 75.315 +*I mux_left_track_5\/mux_l1_in_3_:S I *L 0.00357 *C 19.420 78.200 +*I mux_left_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 16.920 77.815 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 19.495 69.700 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 41.040 67.320 +*I mux_left_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 41.960 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:6 *C 41.922 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:7 *C 41.003 67.320 +*N mux_tree_tapbuf_size7_5_sram[0]:8 *C 40.525 67.320 +*N mux_tree_tapbuf_size7_5_sram[0]:9 *C 40.480 67.365 +*N mux_tree_tapbuf_size7_5_sram[0]:10 *C 40.480 68.635 +*N mux_tree_tapbuf_size7_5_sram[0]:11 *C 40.480 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:12 *C 36.385 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:13 *C 36.340 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:14 *C 36.333 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:15 *C 19.328 68.680 +*N mux_tree_tapbuf_size7_5_sram[0]:16 *C 19.320 68.737 +*N mux_tree_tapbuf_size7_5_sram[0]:17 *C 19.495 69.700 +*N mux_tree_tapbuf_size7_5_sram[0]:18 *C 19.320 69.700 +*N mux_tree_tapbuf_size7_5_sram[0]:19 *C 19.320 69.700 +*N mux_tree_tapbuf_size7_5_sram[0]:20 *C 19.320 74.755 +*N mux_tree_tapbuf_size7_5_sram[0]:21 *C 19.275 74.800 +*N mux_tree_tapbuf_size7_5_sram[0]:22 *C 13.690 74.800 +*N mux_tree_tapbuf_size7_5_sram[0]:23 *C 13.645 74.868 +*N mux_tree_tapbuf_size7_5_sram[0]:24 *C 16.920 77.815 +*N mux_tree_tapbuf_size7_5_sram[0]:25 *C 19.383 78.200 +*N mux_tree_tapbuf_size7_5_sram[0]:26 *C 16.920 78.200 +*N mux_tree_tapbuf_size7_5_sram[0]:27 *C 14.720 78.200 +*N mux_tree_tapbuf_size7_5_sram[0]:28 *C 14.720 77.860 +*N mux_tree_tapbuf_size7_5_sram[0]:29 *C 13.385 77.860 +*N mux_tree_tapbuf_size7_5_sram[0]:30 *C 13.340 77.815 +*N mux_tree_tapbuf_size7_5_sram[0]:31 *C 13.340 75.360 +*N mux_tree_tapbuf_size7_5_sram[0]:32 *C 13.645 75.270 +*N mux_tree_tapbuf_size7_5_sram[0]:33 *C 13.645 75.315 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_5\/mux_l1_in_3_:S 1e-06 +2 mux_left_track_5\/mux_l1_in_2_:S 1e-06 +3 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +5 mux_left_track_5\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_5_sram[0]:6 8.580474e-05 +7 mux_tree_tapbuf_size7_5_sram[0]:7 6.13445e-05 +8 mux_tree_tapbuf_size7_5_sram[0]:8 6.13445e-05 +9 mux_tree_tapbuf_size7_5_sram[0]:9 0.0001091071 +10 mux_tree_tapbuf_size7_5_sram[0]:10 0.0001091071 +11 mux_tree_tapbuf_size7_5_sram[0]:11 0.000352835 +12 mux_tree_tapbuf_size7_5_sram[0]:12 0.0002302836 +13 mux_tree_tapbuf_size7_5_sram[0]:13 3.767446e-05 +14 mux_tree_tapbuf_size7_5_sram[0]:14 0.0004441736 +15 mux_tree_tapbuf_size7_5_sram[0]:15 0.0004441736 +16 mux_tree_tapbuf_size7_5_sram[0]:16 7.850183e-05 +17 mux_tree_tapbuf_size7_5_sram[0]:17 6.031532e-05 +18 mux_tree_tapbuf_size7_5_sram[0]:18 6.399315e-05 +19 mux_tree_tapbuf_size7_5_sram[0]:19 0.0003844669 +20 mux_tree_tapbuf_size7_5_sram[0]:20 0.0002726511 +21 mux_tree_tapbuf_size7_5_sram[0]:21 0.0003423277 +22 mux_tree_tapbuf_size7_5_sram[0]:22 0.0003423277 +23 mux_tree_tapbuf_size7_5_sram[0]:23 3.605391e-05 +24 mux_tree_tapbuf_size7_5_sram[0]:24 6.20945e-05 +25 mux_tree_tapbuf_size7_5_sram[0]:25 0.0001996516 +26 mux_tree_tapbuf_size7_5_sram[0]:26 0.0004039072 +27 mux_tree_tapbuf_size7_5_sram[0]:27 0.0001994576 +28 mux_tree_tapbuf_size7_5_sram[0]:28 0.0001384532 +29 mux_tree_tapbuf_size7_5_sram[0]:29 0.0001115276 +30 mux_tree_tapbuf_size7_5_sram[0]:30 0.0001549534 +31 mux_tree_tapbuf_size7_5_sram[0]:31 0.0001863418 +32 mux_tree_tapbuf_size7_5_sram[0]:32 6.744225e-05 +33 mux_tree_tapbuf_size7_5_sram[0]:33 3.643942e-05 +34 mux_tree_tapbuf_size7_5_sram[0]:15 chanx_left_in[18] 0.0009518908 +35 mux_tree_tapbuf_size7_5_sram[0]:14 chanx_left_in[18]:18 0.0009518908 +36 mux_tree_tapbuf_size7_5_sram[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.864402e-05 +37 mux_tree_tapbuf_size7_5_sram[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 8.877243e-05 +38 mux_tree_tapbuf_size7_5_sram[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 2.864402e-05 +39 mux_tree_tapbuf_size7_5_sram[0]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 8.877243e-05 +40 mux_tree_tapbuf_size7_5_sram[0]:20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 3.842747e-05 +41 mux_tree_tapbuf_size7_5_sram[0]:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.842747e-05 +42 mux_tree_tapbuf_size7_5_sram[0]:25 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.405211e-06 +43 mux_tree_tapbuf_size7_5_sram[0]:26 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 1.405211e-06 +44 mux_tree_tapbuf_size7_5_sram[0]:15 mem_left_track_25/net_net_84:5 0.0003784972 +45 mux_tree_tapbuf_size7_5_sram[0]:14 mem_left_track_25/net_net_84:6 0.0003784972 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_5_sram[0]:33 0.152 +1 mux_tree_tapbuf_size7_5_sram[0]:7 mux_left_track_5\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_5_sram[0]:8 mux_tree_tapbuf_size7_5_sram[0]:7 0.0004263393 +3 mux_tree_tapbuf_size7_5_sram[0]:9 mux_tree_tapbuf_size7_5_sram[0]:8 0.0045 +4 mux_tree_tapbuf_size7_5_sram[0]:11 mux_tree_tapbuf_size7_5_sram[0]:10 0.0045 +5 mux_tree_tapbuf_size7_5_sram[0]:11 mux_tree_tapbuf_size7_5_sram[0]:6 0.001287946 +6 mux_tree_tapbuf_size7_5_sram[0]:10 mux_tree_tapbuf_size7_5_sram[0]:9 0.001133929 +7 mux_tree_tapbuf_size7_5_sram[0]:29 mux_tree_tapbuf_size7_5_sram[0]:28 0.001191964 +8 mux_tree_tapbuf_size7_5_sram[0]:30 mux_tree_tapbuf_size7_5_sram[0]:29 0.0045 +9 mux_tree_tapbuf_size7_5_sram[0]:33 mux_tree_tapbuf_size7_5_sram[0]:32 0.0045 +10 mux_tree_tapbuf_size7_5_sram[0]:32 mux_tree_tapbuf_size7_5_sram[0]:31 0.0001191406 +11 mux_tree_tapbuf_size7_5_sram[0]:32 mux_tree_tapbuf_size7_5_sram[0]:23 0.000359375 +12 mux_tree_tapbuf_size7_5_sram[0]:22 mux_tree_tapbuf_size7_5_sram[0]:21 0.004986607 +13 mux_tree_tapbuf_size7_5_sram[0]:23 mux_tree_tapbuf_size7_5_sram[0]:22 0.0045 +14 mux_tree_tapbuf_size7_5_sram[0]:21 mux_tree_tapbuf_size7_5_sram[0]:20 0.0045 +15 mux_tree_tapbuf_size7_5_sram[0]:20 mux_tree_tapbuf_size7_5_sram[0]:19 0.004513393 +16 mux_tree_tapbuf_size7_5_sram[0]:6 mux_left_track_5\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size7_5_sram[0]:18 mux_tree_tapbuf_size7_5_sram[0]:17 9.51087e-05 +18 mux_tree_tapbuf_size7_5_sram[0]:19 mux_tree_tapbuf_size7_5_sram[0]:18 0.0045 +19 mux_tree_tapbuf_size7_5_sram[0]:19 mux_tree_tapbuf_size7_5_sram[0]:16 0.0008593751 +20 mux_tree_tapbuf_size7_5_sram[0]:17 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +21 mux_tree_tapbuf_size7_5_sram[0]:16 mux_tree_tapbuf_size7_5_sram[0]:15 0.00341 +22 mux_tree_tapbuf_size7_5_sram[0]:15 mux_tree_tapbuf_size7_5_sram[0]:14 0.002664117 +23 mux_tree_tapbuf_size7_5_sram[0]:13 mux_tree_tapbuf_size7_5_sram[0]:12 0.0045 +24 mux_tree_tapbuf_size7_5_sram[0]:14 mux_tree_tapbuf_size7_5_sram[0]:13 0.00341 +25 mux_tree_tapbuf_size7_5_sram[0]:12 mux_tree_tapbuf_size7_5_sram[0]:11 0.00365625 +26 mux_tree_tapbuf_size7_5_sram[0]:25 mux_left_track_5\/mux_l1_in_3_:S 0.152 +27 mux_tree_tapbuf_size7_5_sram[0]:24 mux_left_track_5\/mux_l1_in_2_:S 0.152 +28 mux_tree_tapbuf_size7_5_sram[0]:28 mux_tree_tapbuf_size7_5_sram[0]:27 0.0003035715 +29 mux_tree_tapbuf_size7_5_sram[0]:27 mux_tree_tapbuf_size7_5_sram[0]:26 0.001964286 +30 mux_tree_tapbuf_size7_5_sram[0]:26 mux_tree_tapbuf_size7_5_sram[0]:25 0.002198661 +31 mux_tree_tapbuf_size7_5_sram[0]:26 mux_tree_tapbuf_size7_5_sram[0]:24 0.00034375 +32 mux_tree_tapbuf_size7_5_sram[0]:31 mux_tree_tapbuf_size7_5_sram[0]:30 0.002191965 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_0_ccff_tail[0] 0.0006399949 //LENGTH 4.600 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/FTB_3__35:X O *L 0 *C 39.795 102.680 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 43.875 102.340 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 *C 43.875 102.340 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 *C 43.700 102.680 +*N mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 *C 39.833 102.680 + +*CAP +0 mem_top_track_2\/FTB_3__35:X 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 5.502858e-05 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.0003038556 +4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.0002791107 + +*RES +0 mem_top_track_2\/FTB_3__35:X mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 0.152 +1 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 0.003453125 +2 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_0_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[1] 0.007262858 //LENGTH 51.590 LUMPCC 0.001066987 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 40.325 36.720 +*I mux_bottom_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 27.700 36.040 +*I mux_bottom_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 24.020 34.680 +*I mux_bottom_track_3\/mux_l2_in_3_:S I *L 0.00357 *C 24.740 47.310 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 15.355 44.540 +*I mux_bottom_track_3\/mux_l2_in_2_:S I *L 0.00357 *C 21.060 50.615 +*N mux_tree_tapbuf_size9_0_sram[1]:6 *C 21.060 50.615 +*N mux_tree_tapbuf_size9_0_sram[1]:7 *C 15.393 44.540 +*N mux_tree_tapbuf_size9_0_sram[1]:8 *C 17.895 44.540 +*N mux_tree_tapbuf_size9_0_sram[1]:9 *C 17.940 44.585 +*N mux_tree_tapbuf_size9_0_sram[1]:10 *C 17.940 50.275 +*N mux_tree_tapbuf_size9_0_sram[1]:11 *C 17.985 50.320 +*N mux_tree_tapbuf_size9_0_sram[1]:12 *C 21.023 50.320 +*N mux_tree_tapbuf_size9_0_sram[1]:13 *C 21.103 50.350 +*N mux_tree_tapbuf_size9_0_sram[1]:14 *C 21.160 50.275 +*N mux_tree_tapbuf_size9_0_sram[1]:15 *C 21.160 47.645 +*N mux_tree_tapbuf_size9_0_sram[1]:16 *C 21.205 47.600 +*N mux_tree_tapbuf_size9_0_sram[1]:17 *C 24.683 47.600 +*N mux_tree_tapbuf_size9_0_sram[1]:18 *C 24.740 47.310 +*N mux_tree_tapbuf_size9_0_sram[1]:19 *C 24.840 46.920 +*N mux_tree_tapbuf_size9_0_sram[1]:20 *C 24.840 46.875 +*N mux_tree_tapbuf_size9_0_sram[1]:21 *C 24.058 34.680 +*N mux_tree_tapbuf_size9_0_sram[1]:22 *C 24.795 34.680 +*N mux_tree_tapbuf_size9_0_sram[1]:23 *C 24.840 34.725 +*N mux_tree_tapbuf_size9_0_sram[1]:24 *C 24.840 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:25 *C 25.300 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:26 *C 25.308 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:27 *C 27.700 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:28 *C 27.700 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:29 *C 27.700 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:30 *C 40.013 36.040 +*N mux_tree_tapbuf_size9_0_sram[1]:31 *C 40.020 36.098 +*N mux_tree_tapbuf_size9_0_sram[1]:32 *C 40.020 36.675 +*N mux_tree_tapbuf_size9_0_sram[1]:33 *C 40.020 36.720 +*N mux_tree_tapbuf_size9_0_sram[1]:34 *C 40.325 36.720 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_track_3\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_track_3\/mux_l2_in_3_:S 1e-06 +4 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +5 mux_bottom_track_3\/mux_l2_in_2_:S 1e-06 +6 mux_tree_tapbuf_size9_0_sram[1]:6 5.251118e-05 +7 mux_tree_tapbuf_size9_0_sram[1]:7 0.000233642 +8 mux_tree_tapbuf_size9_0_sram[1]:8 0.000233642 +9 mux_tree_tapbuf_size9_0_sram[1]:9 0.0003305137 +10 mux_tree_tapbuf_size9_0_sram[1]:10 0.0003305137 +11 mux_tree_tapbuf_size9_0_sram[1]:11 0.0002104699 +12 mux_tree_tapbuf_size9_0_sram[1]:12 0.0002271334 +13 mux_tree_tapbuf_size9_0_sram[1]:13 4.041858e-05 +14 mux_tree_tapbuf_size9_0_sram[1]:14 0.0001643492 +15 mux_tree_tapbuf_size9_0_sram[1]:15 0.0001643492 +16 mux_tree_tapbuf_size9_0_sram[1]:16 0.0001768928 +17 mux_tree_tapbuf_size9_0_sram[1]:17 0.0002048189 +18 mux_tree_tapbuf_size9_0_sram[1]:18 9.071045e-05 +19 mux_tree_tapbuf_size9_0_sram[1]:19 6.672564e-05 +20 mux_tree_tapbuf_size9_0_sram[1]:20 0.0005337873 +21 mux_tree_tapbuf_size9_0_sram[1]:21 9.177239e-05 +22 mux_tree_tapbuf_size9_0_sram[1]:22 9.177239e-05 +23 mux_tree_tapbuf_size9_0_sram[1]:23 8.280352e-05 +24 mux_tree_tapbuf_size9_0_sram[1]:24 0.0006497253 +25 mux_tree_tapbuf_size9_0_sram[1]:25 6.766416e-05 +26 mux_tree_tapbuf_size9_0_sram[1]:26 0.0001753526 +27 mux_tree_tapbuf_size9_0_sram[1]:27 3.132079e-05 +28 mux_tree_tapbuf_size9_0_sram[1]:28 3.593673e-05 +29 mux_tree_tapbuf_size9_0_sram[1]:29 0.0009242846 +30 mux_tree_tapbuf_size9_0_sram[1]:30 0.0007489319 +31 mux_tree_tapbuf_size9_0_sram[1]:31 5.68521e-05 +32 mux_tree_tapbuf_size9_0_sram[1]:32 5.68521e-05 +33 mux_tree_tapbuf_size9_0_sram[1]:33 6.254817e-05 +34 mux_tree_tapbuf_size9_0_sram[1]:34 5.357654e-05 +35 mux_tree_tapbuf_size9_0_sram[1]:26 chanx_left_in[1]:12 6.286314e-05 +36 mux_tree_tapbuf_size9_0_sram[1]:30 chanx_left_in[1]:11 0.0002616891 +37 mux_tree_tapbuf_size9_0_sram[1]:29 chanx_left_in[1]:11 6.286314e-05 +38 mux_tree_tapbuf_size9_0_sram[1]:29 chanx_left_in[1]:12 0.0002616891 +39 mux_tree_tapbuf_size9_0_sram[1]:20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.662161e-05 +40 mux_tree_tapbuf_size9_0_sram[1]:24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.662161e-05 +41 mux_tree_tapbuf_size9_0_sram[1]:10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:10 7.589106e-08 +42 mux_tree_tapbuf_size9_0_sram[1]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:9 7.589106e-08 +43 mux_tree_tapbuf_size9_0_sram[1]:16 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001422436 +44 mux_tree_tapbuf_size9_0_sram[1]:17 mux_left_track_13/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0001422436 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size9_0_sram[1]:34 0.152 +1 mux_tree_tapbuf_size9_0_sram[1]:18 mux_bottom_track_3\/mux_l2_in_3_:S 0.152 +2 mux_tree_tapbuf_size9_0_sram[1]:18 mux_tree_tapbuf_size9_0_sram[1]:17 0.0001686047 +3 mux_tree_tapbuf_size9_0_sram[1]:25 mux_tree_tapbuf_size9_0_sram[1]:24 0.0004107143 +4 mux_tree_tapbuf_size9_0_sram[1]:26 mux_tree_tapbuf_size9_0_sram[1]:25 0.00341 +5 mux_tree_tapbuf_size9_0_sram[1]:11 mux_tree_tapbuf_size9_0_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size9_0_sram[1]:10 mux_tree_tapbuf_size9_0_sram[1]:9 0.005080357 +7 mux_tree_tapbuf_size9_0_sram[1]:8 mux_tree_tapbuf_size9_0_sram[1]:7 0.002234375 +8 mux_tree_tapbuf_size9_0_sram[1]:9 mux_tree_tapbuf_size9_0_sram[1]:8 0.0045 +9 mux_tree_tapbuf_size9_0_sram[1]:7 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +10 mux_tree_tapbuf_size9_0_sram[1]:19 mux_tree_tapbuf_size9_0_sram[1]:18 0.0003482143 +11 mux_tree_tapbuf_size9_0_sram[1]:20 mux_tree_tapbuf_size9_0_sram[1]:19 0.0045 +12 mux_tree_tapbuf_size9_0_sram[1]:22 mux_tree_tapbuf_size9_0_sram[1]:21 0.0006584821 +13 mux_tree_tapbuf_size9_0_sram[1]:23 mux_tree_tapbuf_size9_0_sram[1]:22 0.0045 +14 mux_tree_tapbuf_size9_0_sram[1]:21 mux_bottom_track_3\/mux_l2_in_1_:S 0.152 +15 mux_tree_tapbuf_size9_0_sram[1]:13 mux_tree_tapbuf_size9_0_sram[1]:12 7.142856e-05 +16 mux_tree_tapbuf_size9_0_sram[1]:13 mux_tree_tapbuf_size9_0_sram[1]:6 0.0001142241 +17 mux_tree_tapbuf_size9_0_sram[1]:14 mux_tree_tapbuf_size9_0_sram[1]:13 0.0045 +18 mux_tree_tapbuf_size9_0_sram[1]:16 mux_tree_tapbuf_size9_0_sram[1]:15 0.0045 +19 mux_tree_tapbuf_size9_0_sram[1]:15 mux_tree_tapbuf_size9_0_sram[1]:14 0.002348214 +20 mux_tree_tapbuf_size9_0_sram[1]:6 mux_bottom_track_3\/mux_l2_in_2_:S 0.152 +21 mux_tree_tapbuf_size9_0_sram[1]:31 mux_tree_tapbuf_size9_0_sram[1]:30 0.00341 +22 mux_tree_tapbuf_size9_0_sram[1]:30 mux_tree_tapbuf_size9_0_sram[1]:29 0.001928958 +23 mux_tree_tapbuf_size9_0_sram[1]:33 mux_tree_tapbuf_size9_0_sram[1]:32 0.0045 +24 mux_tree_tapbuf_size9_0_sram[1]:32 mux_tree_tapbuf_size9_0_sram[1]:31 0.000515625 +25 mux_tree_tapbuf_size9_0_sram[1]:34 mux_tree_tapbuf_size9_0_sram[1]:33 0.0001657609 +26 mux_tree_tapbuf_size9_0_sram[1]:28 mux_tree_tapbuf_size9_0_sram[1]:27 0.0045 +27 mux_tree_tapbuf_size9_0_sram[1]:29 mux_tree_tapbuf_size9_0_sram[1]:28 0.00341 +28 mux_tree_tapbuf_size9_0_sram[1]:29 mux_tree_tapbuf_size9_0_sram[1]:26 0.000374825 +29 mux_tree_tapbuf_size9_0_sram[1]:27 mux_bottom_track_3\/mux_l2_in_0_:S 0.152 +30 mux_tree_tapbuf_size9_0_sram[1]:12 mux_tree_tapbuf_size9_0_sram[1]:11 0.002712053 +31 mux_tree_tapbuf_size9_0_sram[1]:17 mux_tree_tapbuf_size9_0_sram[1]:16 0.003104911 +32 mux_tree_tapbuf_size9_0_sram[1]:24 mux_tree_tapbuf_size9_0_sram[1]:23 0.001174107 +33 mux_tree_tapbuf_size9_0_sram[1]:24 mux_tree_tapbuf_size9_0_sram[1]:20 0.009674108 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001145639 //LENGTH 9.985 LUMPCC 0.0001746958 DR + +*CONN +*I mux_top_track_2\/mux_l1_in_0_:X O *L 0 *C 35.595 112.200 +*I mux_top_track_2\/mux_l2_in_0_:A1 I *L 0.00198 *C 33.680 105.060 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 33.718 105.060 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.455 105.060 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 34.500 105.105 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 34.500 112.155 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 34.545 112.200 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 35.558 112.200 + +*CAP +0 mux_top_track_2\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.554967e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.554967e-05 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003303017 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003303017 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.86203e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.86203e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_39_[0]:6 5.974128e-06 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 top_left_grid_pin_39_[0]:16 8.137377e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_39_[0]:16 5.974128e-06 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 top_left_grid_pin_39_[0]:17 8.137377e-05 + +*RES +0 mux_top_track_2\/mux_l1_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_2\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0006584821 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294643 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005427541 //LENGTH 4.270 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_1_:X O *L 0 *C 82.625 94.180 +*I mux_top_track_8\/mux_l3_in_0_:A0 I *L 0.001631 *C 83.435 96.900 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 83.398 96.900 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 82.845 96.900 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 82.800 96.855 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 82.800 94.225 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 82.800 94.180 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 82.625 94.180 + +*CAP +0 mux_top_track_8\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.45954e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.45954e-05 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001626387 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001626387 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.535024e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.093571e-05 + +*RES +0 mux_top_track_8\/mux_l2_in_1_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004933036 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0] 0.001518186 //LENGTH 12.560 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_1_:X O *L 0 *C 80.325 39.440 +*I mux_bottom_track_9\/mux_l4_in_0_:A0 I *L 0.005103 *C 84.640 32.125 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 84.603 32.125 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 81.925 32.125 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 81.880 32.170 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 81.880 39.395 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 81.835 39.440 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 80.362 39.440 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002524738 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002524738 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0003934929 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0003934929 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001121263 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001121263 + +*RES +0 mux_bottom_track_9\/mux_l3_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_9\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002390625 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.006450893 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001244894 //LENGTH 9.805 LUMPCC 0.0002532256 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_3_:X O *L 0 *C 47.205 110.500 +*I mux_top_track_4\/mux_l2_in_1_:A0 I *L 0.001631 *C 53.020 113.560 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 52.983 113.560 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 51.105 113.560 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 51.060 113.515 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 51.060 110.545 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 51.015 110.500 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 47.242 110.500 + +*CAP +0 mux_top_track_4\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.531005e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.531005e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001361379 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001361379 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002633863 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002633863 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chany_bottom_in[14]:17 4.381599e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_bottom_in[14]:16 4.381599e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 8.279679e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 8.279679e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_3_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.003368304 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002651786 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001676339 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006053551 //LENGTH 4.510 LUMPCC 6.850292e-05 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_1_:X O *L 0 *C 38.815 4.420 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 36.980 6.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 36.980 6.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.260 6.460 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 37.260 6.415 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 37.260 4.465 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 37.305 4.420 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 38.778 4.420 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.542491e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.78813e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001379386 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001379386 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.28344e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.28344e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size14_1_sram[0]:21 3.425146e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size14_1_sram[0]:22 3.425146e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741071 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001521739 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0] 0.003275958 //LENGTH 25.050 LUMPCC 0.0009808237 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_3_:X O *L 0 *C 39.385 66.980 +*I mux_top_track_16\/mux_l2_in_1_:A0 I *L 0.001631 *C 49.395 80.920 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 49.395 80.920 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 49.220 80.240 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 44.205 80.240 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 44.160 80.195 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 44.160 67.365 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 44.115 67.320 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 41.400 67.320 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 41.400 66.980 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 39.422 66.980 + +*CAP +0 mux_top_track_16\/mux_l1_in_3_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_1_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.97471e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002998937 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00025733 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004462728 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004462728 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002120463 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002383279 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001747626 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.000148481 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[5]:8 0.0003380351 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[5]:9 0.0003380351 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[15]:5 9.480173e-07 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[15]:9 7.471628e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[15]:6 9.480173e-07 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[15]:10 7.471628e-05 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.671241e-05 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.671241e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_3_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001765625 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.01145536 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.004477679 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_16\/mux_l2_in_1_:A0 0.152 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0003035714 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.002424107 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0006071429 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006515258 //LENGTH 4.730 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_3_:X O *L 0 *C 17.305 88.740 +*I mux_left_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 18.575 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 18.575 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 18.400 91.460 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 18.400 91.415 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 18.400 88.785 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 18.355 88.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 17.343 88.740 + +*CAP +0 mux_left_track_1\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.957665e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.393001e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001741188 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001741188 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.889081e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.889081e-05 + +*RES +0 mux_left_track_1\/mux_l1_in_3_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_1\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.510869e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0005602818 //LENGTH 3.360 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_3_:X O *L 0 *C 13.975 80.920 +*I mux_left_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 14.550 82.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 14.550 82.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 14.720 82.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 14.720 82.575 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 14.720 80.965 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 14.675 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 14.013 80.920 + +*CAP +0 mux_left_track_3\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 6.046257e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 6.536499e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001338666 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001338666 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.236049e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 8.236049e-05 + +*RES +0 mux_left_track_3\/mux_l1_in_3_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_3\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.239131e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0005915179 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0022788 //LENGTH 19.525 LUMPCC 0.0001945247 DR + +*CONN +*I mux_left_track_5\/mux_l3_in_0_:X O *L 0 *C 11.675 69.360 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 6.265 82.760 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 6.303 82.668 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 10.535 82.620 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 10.580 82.575 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 10.580 69.405 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 10.625 69.360 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 11.638 69.360 + +*CAP +0 mux_left_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0002472932 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0002472932 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0007118966 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0007118966 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 8.194782e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 8.194782e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size7_4_sram[2]:7 1.817351e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_tree_tapbuf_size7_4_sram[2]:8 3.945116e-06 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size7_4_sram[2]:4 7.514373e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size7_4_sram[2]:5 3.945116e-06 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_tree_tapbuf_size7_4_sram[2]:8 1.817351e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size7_4_sram[2]:3 7.514373e-05 + +*RES +0 mux_left_track_5\/mux_l3_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0009040179 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.01175893 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.003779018 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0] 0.005259078 //LENGTH 40.250 LUMPCC 0.00124178 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_0_:X O *L 0 *C 47.665 96.560 +*I mux_top_track_32\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.180 77.860 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.080 77.860 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.080 77.905 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 68.080 82.223 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 68.073 82.280 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 47.848 82.280 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 47.840 82.338 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 47.840 96.515 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 47.840 96.560 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 47.665 96.560 + +*CAP +0 mux_top_track_32\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.537675e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000197254 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000197254 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001033472 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001033472 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0007061473 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0007061473 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 5.306887e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 5.310476e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:408 8.663921e-05 +12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:412 1.768142e-05 +13 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:456 0.0001617851 +14 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:464 3.158944e-05 +15 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:462 2.034541e-05 +16 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:463 2.586738e-05 +17 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:466 1.089779e-06 +18 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:412 8.663921e-05 +19 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:413 1.768142e-05 +20 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:464 0.0001617851 +21 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:465 3.158944e-05 +22 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 prog_clk[0]:404 1.089779e-06 +23 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 prog_clk[0]:459 2.034541e-05 +24 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 prog_clk[0]:462 2.586738e-05 +25 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[4]:5 0.0001265148 +26 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[4]:9 0.0001265148 +27 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[4]:10 0.0001242133 +28 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[4]:11 2.516408e-05 +29 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[4]:11 0.0001242133 +30 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[4]:12 2.516408e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_0_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.003854911 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.00341 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00341 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.003168583 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0045 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.01265848 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:9 9.510869e-05 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0008636009 //LENGTH 6.340 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_1_:X O *L 0 *C 26.965 44.540 +*I mux_bottom_track_3\/mux_l4_in_0_:A0 I *L 0.001631 *C 26.395 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 26.395 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 26.680 39.100 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 26.680 39.145 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 26.680 44.495 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 26.680 44.540 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 *C 26.965 44.540 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l4_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 5.851375e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 5.715467e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0003078666 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0003078666 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.210255e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 6.809674e-05 + +*RES +0 mux_bottom_track_3\/mux_l3_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_bottom_track_3\/mux_l4_in_0_:A0 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0001548913 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.004776786 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001548913 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003286992 //LENGTH 20.065 LUMPCC 0.001226006 DR + +*CONN +*I mux_left_track_13\/mux_l2_in_0_:X O *L 0 *C 47.095 46.920 +*I mux_left_track_13\/mux_l3_in_0_:A1 I *L 0.00198 *C 28.425 47.260 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 28.425 47.260 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 28.520 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 28.520 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 28.527 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 47.373 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 47.380 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 47.380 46.920 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 47.095 46.920 + +*CAP +0 mux_left_track_13\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_13\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.926965e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.35964e-05 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.90674e-05 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0008664632 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0008664632 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.746976e-05 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 6.405703e-05 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.259856e-05 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:234 1.280854e-05 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:239 2.342848e-05 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:241 1.403656e-05 +13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:503 0.0001679033 +14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:215 1.280854e-05 +15 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:234 2.342848e-05 +16 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:240 1.403656e-05 +17 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:502 0.0001679033 +18 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[17]:13 9.342247e-05 +19 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[17]:12 9.342247e-05 +20 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size4_2_sram[2]:4 2.488338e-06 +21 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size4_2_sram[2]:5 2.488338e-06 +22 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_2_sram[2]:9 1.057312e-05 +23 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size4_2_sram[2]:14 0.0001293012 +24 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size4_2_sram[2]:14 1.057312e-05 +25 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size4_2_sram[2]:15 0.0001293012 +26 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000159041 +27 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000159041 + +*RES +0 mux_left_track_13\/mux_l2_in_0_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_13\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001847826 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00341 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.002952383 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001548913 + +*END + +*D_NET mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004939514 //LENGTH 2.600 LUMPCC 0.0001044573 DR + +*CONN +*I mux_left_track_21\/mux_l1_in_1_:X O *L 0 *C 26.965 77.180 +*I mux_left_track_21\/mux_l2_in_0_:A0 I *L 0.001631 *C 26.970 75.480 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 26.970 75.480 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 27.140 75.480 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 27.140 75.525 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 27.140 77.135 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 27.140 77.180 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 26.965 77.180 + +*CAP +0 mux_left_track_21\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_21\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.512992e-05 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.840708e-05 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.39235e-05 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.39235e-05 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.410234e-05 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.200779e-05 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.222863e-05 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.222863e-05 + +*RES +0 mux_left_track_21\/mux_l1_in_1_:X mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_21\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET chanx_left_out[11] 0.001163908 //LENGTH 9.755 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_770:X O *L 0 *C 7.095 99.620 +*P chanx_left_out[11] O *L 0.7423 *C 1.298 96.560 +*N chanx_left_out[11]:2 *C 1.380 96.560 +*N chanx_left_out[11]:3 *C 1.380 96.618 +*N chanx_left_out[11]:4 *C 1.380 99.575 +*N chanx_left_out[11]:5 *C 1.425 99.620 +*N chanx_left_out[11]:6 *C 7.058 99.620 + +*CAP +0 ropt_mt_inst_770:X 1e-06 +1 chanx_left_out[11] 3.293375e-05 +2 chanx_left_out[11]:2 3.293375e-05 +3 chanx_left_out[11]:3 0.0001928375 +4 chanx_left_out[11]:4 0.0001928375 +5 chanx_left_out[11]:5 0.0003556829 +6 chanx_left_out[11]:6 0.0003556829 + +*RES +0 ropt_mt_inst_770:X chanx_left_out[11]:6 0.152 +1 chanx_left_out[11]:6 chanx_left_out[11]:5 0.005029018 +2 chanx_left_out[11]:5 chanx_left_out[11]:4 0.0045 +3 chanx_left_out[11]:4 chanx_left_out[11]:3 0.002640625 +4 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 +5 chanx_left_out[11]:2 chanx_left_out[11] 2.35e-05 + +*END + +*D_NET ropt_net_169 0.0007326819 //LENGTH 4.890 LUMPCC 0.0003270379 DR + +*CONN +*I FTB_1__0:X O *L 0 *C 7.820 96.560 +*I ropt_mt_inst_795:A I *L 0.001766 *C 3.220 96.560 +*N ropt_net_169:2 *C 3.258 96.560 +*N ropt_net_169:3 *C 7.783 96.560 + +*CAP +0 FTB_1__0:X 1e-06 +1 ropt_mt_inst_795:A 1e-06 +2 ropt_net_169:2 0.000201822 +3 ropt_net_169:3 0.000201822 +4 ropt_net_169:3 BUF_net_69:6 4.526233e-05 +5 ropt_net_169:2 BUF_net_69:5 4.526233e-05 +6 ropt_net_169:3 ropt_net_184:7 0.0001182566 +7 ropt_net_169:2 ropt_net_184:6 0.0001182566 + +*RES +0 FTB_1__0:X ropt_net_169:3 0.152 +1 ropt_net_169:3 ropt_net_169:2 0.004040178 +2 ropt_net_169:2 ropt_mt_inst_795:A 0.152 + +*END + +*D_NET chany_bottom_out[6] 0.001591203 //LENGTH 12.710 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_809:X O *L 0 *C 83.455 4.420 +*P chany_bottom_out[6] O *L 0.7423 *C 74.980 1.290 +*N chany_bottom_out[6]:2 *C 74.980 1.655 +*N chany_bottom_out[6]:3 *C 75.025 1.700 +*N chany_bottom_out[6]:4 *C 82.755 1.700 +*N chany_bottom_out[6]:5 *C 82.800 1.745 +*N chany_bottom_out[6]:6 *C 82.800 4.375 +*N chany_bottom_out[6]:7 *C 82.845 4.420 +*N chany_bottom_out[6]:8 *C 83.418 4.420 + +*CAP +0 ropt_mt_inst_809:X 1e-06 +1 chany_bottom_out[6] 3.805187e-05 +2 chany_bottom_out[6]:2 3.805187e-05 +3 chany_bottom_out[6]:3 0.000471041 +4 chany_bottom_out[6]:4 0.000471041 +5 chany_bottom_out[6]:5 0.0002089331 +6 chany_bottom_out[6]:6 0.0002089331 +7 chany_bottom_out[6]:7 7.707565e-05 +8 chany_bottom_out[6]:8 7.707565e-05 + +*RES +0 ropt_mt_inst_809:X chany_bottom_out[6]:8 0.152 +1 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +2 chany_bottom_out[6]:2 chany_bottom_out[6] 0.0003258929 +3 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.006901786 +4 chany_bottom_out[6]:5 chany_bottom_out[6]:4 0.0045 +5 chany_bottom_out[6]:7 chany_bottom_out[6]:6 0.0045 +6 chany_bottom_out[6]:6 chany_bottom_out[6]:5 0.002348214 +7 chany_bottom_out[6]:8 chany_bottom_out[6]:7 0.0005111608 + +*END + +*D_NET ropt_net_201 0.0001373663 //LENGTH 1.015 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_782:X O *L 0 *C 71.955 6.800 +*I ropt_mt_inst_835:A I *L 0.001767 *C 72.680 6.800 +*N ropt_net_201:2 *C 72.642 6.800 +*N ropt_net_201:3 *C 71.993 6.800 + +*CAP +0 ropt_mt_inst_782:X 1e-06 +1 ropt_mt_inst_835:A 1e-06 +2 ropt_net_201:2 6.768313e-05 +3 ropt_net_201:3 6.768313e-05 + +*RES +0 ropt_mt_inst_782:X ropt_net_201:3 0.152 +1 ropt_net_201:2 ropt_mt_inst_835:A 0.152 +2 ropt_net_201:3 ropt_net_201:2 0.0005803572 + +*END + +*D_NET chany_bottom_out[3] 0.001411652 //LENGTH 10.500 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_787:X O *L 0 *C 69.195 9.860 +*P chany_bottom_out[3] O *L 0.7423 *C 69.000 1.290 +*N chany_bottom_out[3]:2 *C 69.000 1.700 +*N chany_bottom_out[3]:3 *C 69.460 1.700 +*N chany_bottom_out[3]:4 *C 69.460 6.800 +*N chany_bottom_out[3]:5 *C 69.000 6.800 +*N chany_bottom_out[3]:6 *C 69.000 9.815 +*N chany_bottom_out[3]:7 *C 69.000 9.860 +*N chany_bottom_out[3]:8 *C 69.195 9.860 + +*CAP +0 ropt_mt_inst_787:X 1e-06 +1 chany_bottom_out[3] 3.312324e-05 +2 chany_bottom_out[3]:2 6.253019e-05 +3 chany_bottom_out[3]:3 0.0003576135 +4 chany_bottom_out[3]:4 0.0003591953 +5 chany_bottom_out[3]:5 0.0002484829 +6 chany_bottom_out[3]:6 0.0002174941 +7 chany_bottom_out[3]:7 6.691323e-05 +8 chany_bottom_out[3]:8 6.529913e-05 + +*RES +0 ropt_mt_inst_787:X chany_bottom_out[3]:8 0.152 +1 chany_bottom_out[3]:8 chany_bottom_out[3]:7 0.0001059783 +2 chany_bottom_out[3]:7 chany_bottom_out[3]:6 0.0045 +3 chany_bottom_out[3]:6 chany_bottom_out[3]:5 0.002691965 +4 chany_bottom_out[3]:2 chany_bottom_out[3] 0.0003660715 +5 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0004107143 +6 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.0004107143 +7 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.004553571 + +*END + +*D_NET ropt_net_185 0.0006472257 //LENGTH 4.315 LUMPCC 9.871765e-05 DR + +*CONN +*I ropt_mt_inst_791:X O *L 0 *C 64.670 8.840 +*I ropt_mt_inst_814:A I *L 0.001767 *C 63.020 6.800 +*N ropt_net_185:2 *C 63.020 6.800 +*N ropt_net_185:3 *C 63.020 6.845 +*N ropt_net_185:4 *C 63.020 8.795 +*N ropt_net_185:5 *C 63.065 8.840 +*N ropt_net_185:6 *C 64.633 8.840 + +*CAP +0 ropt_mt_inst_791:X 1e-06 +1 ropt_mt_inst_814:A 1e-06 +2 ropt_net_185:2 3.672739e-05 +3 ropt_net_185:3 0.0001123169 +4 ropt_net_185:4 0.0001123169 +5 ropt_net_185:5 0.0001425733 +6 ropt_net_185:6 0.0001425733 +7 ropt_net_185:4 chany_bottom_in[10]:20 4.935883e-05 +8 ropt_net_185:3 chany_bottom_in[10] 4.935883e-05 + +*RES +0 ropt_mt_inst_791:X ropt_net_185:6 0.152 +1 ropt_net_185:6 ropt_net_185:5 0.001399553 +2 ropt_net_185:5 ropt_net_185:4 0.0045 +3 ropt_net_185:4 ropt_net_185:3 0.001741072 +4 ropt_net_185:2 ropt_mt_inst_814:A 0.152 +5 ropt_net_185:3 ropt_net_185:2 0.0045 + +*END + +*D_NET ropt_net_182 0.001532158 //LENGTH 10.705 LUMPCC 0.0005440483 DR + +*CONN +*I ropt_mt_inst_799:X O *L 0 *C 88.055 4.420 +*I ropt_mt_inst_809:A I *L 0.001766 *C 79.580 4.080 +*N ropt_net_182:2 *C 79.618 4.080 +*N ropt_net_182:3 *C 80.960 4.080 +*N ropt_net_182:4 *C 80.960 3.740 +*N ropt_net_182:5 *C 84.595 3.740 +*N ropt_net_182:6 *C 84.640 3.785 +*N ropt_net_182:7 *C 84.640 4.375 +*N ropt_net_182:8 *C 84.685 4.420 +*N ropt_net_182:9 *C 88.017 4.420 + +*CAP +0 ropt_mt_inst_799:X 1e-06 +1 ropt_mt_inst_809:A 1e-06 +2 ropt_net_182:2 8.880613e-05 +3 ropt_net_182:3 0.000114641 +4 ropt_net_182:4 0.0002177367 +5 ropt_net_182:5 0.0001919017 +6 ropt_net_182:6 6.325807e-05 +7 ropt_net_182:7 6.325807e-05 +8 ropt_net_182:8 0.000123254 +9 ropt_net_182:9 0.000123254 +10 ropt_net_182:2 bottom_right_grid_pin_1_[0]:22 2.141166e-05 +11 ropt_net_182:5 bottom_right_grid_pin_1_[0]:23 1.246848e-05 +12 ropt_net_182:8 bottom_right_grid_pin_1_[0]:22 0.0001361522 +13 ropt_net_182:9 bottom_right_grid_pin_1_[0]:23 0.0001361522 +14 ropt_net_182:3 bottom_right_grid_pin_1_[0]:23 2.141166e-05 +15 ropt_net_182:4 bottom_right_grid_pin_1_[0]:22 1.246848e-05 +16 ropt_net_182:5 chany_bottom_out[0]:4 6.139425e-05 +17 ropt_net_182:8 chany_bottom_out[0]:3 9.735522e-07 +18 ropt_net_182:8 chany_bottom_out[0]:5 3.962398e-05 +19 ropt_net_182:9 chany_bottom_out[0]:4 9.735522e-07 +20 ropt_net_182:9 chany_bottom_out[0]:6 3.962398e-05 +21 ropt_net_182:4 chany_bottom_out[0]:3 6.139425e-05 + +*RES +0 ropt_mt_inst_799:X ropt_net_182:9 0.152 +1 ropt_net_182:2 ropt_mt_inst_809:A 0.152 +2 ropt_net_182:5 ropt_net_182:4 0.003245536 +3 ropt_net_182:6 ropt_net_182:5 0.0045 +4 ropt_net_182:8 ropt_net_182:7 0.0045 +5 ropt_net_182:7 ropt_net_182:6 0.0005267857 +6 ropt_net_182:9 ropt_net_182:8 0.002975447 +7 ropt_net_182:3 ropt_net_182:2 0.001198661 +8 ropt_net_182:4 ropt_net_182:3 0.0003035715 + +*END + +*D_NET chany_top_out[12] 0.001117665 //LENGTH 8.255 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_830:X O *L 0 *C 83.260 125.800 +*P chany_top_out[12] O *L 0.7423 *C 79.580 129.270 +*N chany_top_out[12]:2 *C 79.580 128.905 +*N chany_top_out[12]:3 *C 79.625 128.860 +*N chany_top_out[12]:4 *C 81.835 128.860 +*N chany_top_out[12]:5 *C 81.880 128.815 +*N chany_top_out[12]:6 *C 81.880 125.845 +*N chany_top_out[12]:7 *C 81.925 125.800 +*N chany_top_out[12]:8 *C 83.223 125.800 + +*CAP +0 ropt_mt_inst_830:X 1e-06 +1 chany_top_out[12] 3.642174e-05 +2 chany_top_out[12]:2 3.642174e-05 +3 chany_top_out[12]:3 0.0001537495 +4 chany_top_out[12]:4 0.0001537495 +5 chany_top_out[12]:5 0.000244506 +6 chany_top_out[12]:6 0.000244506 +7 chany_top_out[12]:7 0.0001236554 +8 chany_top_out[12]:8 0.0001236554 + +*RES +0 ropt_mt_inst_830:X chany_top_out[12]:8 0.152 +1 chany_top_out[12]:8 chany_top_out[12]:7 0.001158482 +2 chany_top_out[12]:7 chany_top_out[12]:6 0.0045 +3 chany_top_out[12]:6 chany_top_out[12]:5 0.002651786 +4 chany_top_out[12]:4 chany_top_out[12]:3 0.001973214 +5 chany_top_out[12]:5 chany_top_out[12]:4 0.0045 +6 chany_top_out[12]:3 chany_top_out[12]:2 0.0045 +7 chany_top_out[12]:2 chany_top_out[12] 0.0003258929 + +*END + +*D_NET chany_top_out[14] 0.001022196 //LENGTH 9.180 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_845:X O *L 0 *C 103.695 127.160 +*P chany_top_out[14] O *L 0.7423 *C 97.520 129.270 +*N chany_top_out[14]:2 *C 97.520 128.905 +*N chany_top_out[14]:3 *C 97.565 128.860 +*N chany_top_out[14]:4 *C 103.455 128.860 +*N chany_top_out[14]:5 *C 103.500 128.815 +*N chany_top_out[14]:6 *C 103.500 127.205 +*N chany_top_out[14]:7 *C 103.500 127.160 +*N chany_top_out[14]:8 *C 103.695 127.160 + +*CAP +0 ropt_mt_inst_845:X 1e-06 +1 chany_top_out[14] 3.395902e-05 +2 chany_top_out[14]:2 3.395902e-05 +3 chany_top_out[14]:3 0.0003357287 +4 chany_top_out[14]:4 0.0003357287 +5 chany_top_out[14]:5 8.565374e-05 +6 chany_top_out[14]:6 8.565374e-05 +7 chany_top_out[14]:7 5.618455e-05 +8 chany_top_out[14]:8 5.43285e-05 + +*RES +0 ropt_mt_inst_845:X chany_top_out[14]:8 0.152 +1 chany_top_out[14]:8 chany_top_out[14]:7 0.0001059783 +2 chany_top_out[14]:7 chany_top_out[14]:6 0.0045 +3 chany_top_out[14]:6 chany_top_out[14]:5 0.0014375 +4 chany_top_out[14]:4 chany_top_out[14]:3 0.005258929 +5 chany_top_out[14]:5 chany_top_out[14]:4 0.0045 +6 chany_top_out[14]:3 chany_top_out[14]:2 0.0045 +7 chany_top_out[14]:2 chany_top_out[14] 0.0003258929 + +*END + +*D_NET chany_top_in[11] 0.02343288 //LENGTH 160.955 LUMPCC 0.008811385 DR + +*CONN +*P chany_top_in[11] I *L 0.29796 *C 75.900 129.270 +*I FTB_11__10:A I *L 0.001776 *C 10.120 39.440 +*N chany_top_in[11]:2 *C 10.083 39.440 +*N chany_top_in[11]:3 *C 8.785 39.440 +*N chany_top_in[11]:4 *C 8.740 39.485 +*N chany_top_in[11]:5 *C 8.740 48.903 +*N chany_top_in[11]:6 *C 8.748 48.960 +*N chany_top_in[11]:7 *C 10.100 48.960 +*N chany_top_in[11]:8 *C 10.120 48.968 +*N chany_top_in[11]:9 *C 10.120 78.873 +*N chany_top_in[11]:10 *C 10.140 78.880 +*N chany_top_in[11]:11 *C 34.020 78.880 +*N chany_top_in[11]:12 *C 34.040 78.888 +*N chany_top_in[11]:13 *C 34.040 116.273 +*N chany_top_in[11]:14 *C 34.060 116.280 +*N chany_top_in[11]:15 *C 75.892 116.280 +*N chany_top_in[11]:16 *C 75.900 116.338 + +*CAP +0 chany_top_in[11] 0.000643116 +1 FTB_11__10:A 1e-06 +2 chany_top_in[11]:2 0.0001106799 +3 chany_top_in[11]:3 0.0001106799 +4 chany_top_in[11]:4 0.0005814333 +5 chany_top_in[11]:5 0.0005814333 +6 chany_top_in[11]:6 0.000116082 +7 chany_top_in[11]:7 0.000116082 +8 chany_top_in[11]:8 0.0009895379 +9 chany_top_in[11]:9 0.0009895379 +10 chany_top_in[11]:10 0.001386912 +11 chany_top_in[11]:11 0.001386912 +12 chany_top_in[11]:12 0.001431257 +13 chany_top_in[11]:13 0.001431257 +14 chany_top_in[11]:14 0.002051228 +15 chany_top_in[11]:15 0.002051228 +16 chany_top_in[11]:16 0.000643116 +17 chany_top_in[11]:12 chany_top_in[3]:7 8.605495e-05 +18 chany_top_in[11]:14 chany_top_in[3]:9 0.0002915832 +19 chany_top_in[11]:13 chany_top_in[3]:8 8.605495e-05 +20 chany_top_in[11]:15 chany_top_in[3]:10 0.0002915832 +21 chany_top_in[11]:14 chany_bottom_in[2]:21 0.0004367247 +22 chany_top_in[11]:15 chany_bottom_in[2]:20 0.0004367247 +23 chany_top_in[11]:12 chany_bottom_in[13]:32 2.18388e-05 +24 chany_top_in[11]:12 chany_bottom_in[13]:25 0.0004742627 +25 chany_top_in[11]:13 chany_bottom_in[13]:18 0.0004742627 +26 chany_top_in[11]:13 chany_bottom_in[13]:26 2.18388e-05 +27 chany_top_in[11]:14 top_left_grid_pin_34_[0]:10 0.001069981 +28 chany_top_in[11]:14 top_left_grid_pin_34_[0]:6 6.003252e-06 +29 chany_top_in[11]:15 top_left_grid_pin_34_[0]:9 0.001069981 +30 chany_top_in[11]:15 top_left_grid_pin_34_[0]:5 6.003252e-06 +31 chany_top_in[11]:8 chanx_left_in[0]:19 0.0005182311 +32 chany_top_in[11]:9 chanx_left_in[0]:20 0.0005182311 +33 chany_top_in[11]:4 chanx_left_in[14]:10 3.627374e-06 +34 chany_top_in[11]:5 chanx_left_in[14]:9 3.627374e-06 +35 chany_top_in[11]:8 chanx_left_in[14]:13 0.0005933775 +36 chany_top_in[11]:9 chanx_left_in[14]:14 0.0005933775 +37 chany_top_in[11]:10 chanx_left_in[15] 0.0004434711 +38 chany_top_in[11]:11 chanx_left_in[15]:11 0.0004434711 +39 chany_top_in[11]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:9 0.0003134812 +40 chany_top_in[11]:14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:7 1.633097e-05 +41 chany_top_in[11]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:8 0.0003134812 +42 chany_top_in[11]:15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_8_X[0]:6 1.633097e-05 +43 chany_top_in[11] ropt_net_190:8 0.0001307254 +44 chany_top_in[11]:16 ropt_net_190:9 0.0001307254 + +*RES +0 chany_top_in[11] chany_top_in[11]:16 0.01154688 +1 chany_top_in[11]:2 FTB_11__10:A 0.152 +2 chany_top_in[11]:3 chany_top_in[11]:2 0.001158482 +3 chany_top_in[11]:4 chany_top_in[11]:3 0.0045 +4 chany_top_in[11]:5 chany_top_in[11]:4 0.008408482 +5 chany_top_in[11]:6 chany_top_in[11]:5 0.00341 +6 chany_top_in[11]:7 chany_top_in[11]:6 0.0002118916 +7 chany_top_in[11]:8 chany_top_in[11]:7 0.00341 +8 chany_top_in[11]:10 chany_top_in[11]:9 0.00341 +9 chany_top_in[11]:9 chany_top_in[11]:8 0.004685116 +10 chany_top_in[11]:11 chany_top_in[11]:10 0.0037412 +11 chany_top_in[11]:12 chany_top_in[11]:11 0.00341 +12 chany_top_in[11]:14 chany_top_in[11]:13 0.00341 +13 chany_top_in[11]:13 chany_top_in[11]:12 0.005856983 +14 chany_top_in[11]:16 chany_top_in[11]:15 0.00341 +15 chany_top_in[11]:15 chany_top_in[11]:14 0.006553758 + +*END + +*D_NET chany_top_out[2] 0.001272659 //LENGTH 11.340 LUMPCC 0.0001228061 DR + +*CONN +*I mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 78.380 119.000 +*P chany_top_out[2] O *L 0.7423 *C 77.740 129.235 +*N chany_top_out[2]:2 *C 77.740 119.045 +*N chany_top_out[2]:3 *C 77.785 119.000 +*N chany_top_out[2]:4 *C 78.343 119.000 + +*CAP +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[2] 0.0005084204 +2 chany_top_out[2]:2 0.0005084204 +3 chany_top_out[2]:3 6.600594e-05 +4 chany_top_out[2]:4 6.600594e-05 +5 chany_top_out[2] ropt_net_159:4 6.140303e-05 +6 chany_top_out[2]:2 ropt_net_159:5 6.140303e-05 + +*RES +0 mux_top_track_4\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[2]:4 0.152 +1 chany_top_out[2]:4 chany_top_out[2]:3 0.0004977679 +2 chany_top_out[2]:3 chany_top_out[2]:2 0.0045 +3 chany_top_out[2]:2 chany_top_out[2] 0.009098214 + +*END + +*D_NET chany_bottom_out[4] 0.003605635 //LENGTH 37.855 LUMPCC 0.0001666101 DR + +*CONN +*I mux_bottom_track_9\/mux_l4_in_0_:X O *L 0 *C 89.480 31.280 +*P chany_bottom_out[4] O *L 0.7423 *C 96.600 1.290 +*N chany_bottom_out[4]:2 *C 96.600 30.895 +*N chany_bottom_out[4]:3 *C 96.555 30.940 +*N chany_bottom_out[4]:4 *C 89.700 30.940 +*N chany_bottom_out[4]:5 *C 89.700 31.245 +*N chany_bottom_out[4]:6 *C 89.508 31.258 + +*CAP +0 mux_bottom_track_9\/mux_l4_in_0_:X 1e-06 +1 chany_bottom_out[4] 0.001290202 +2 chany_bottom_out[4]:2 0.001290202 +3 chany_bottom_out[4]:3 0.0003744758 +4 chany_bottom_out[4]:4 0.0003995146 +5 chany_bottom_out[4]:5 5.43339e-05 +6 chany_bottom_out[4]:6 2.929515e-05 +7 chany_bottom_out[4] ropt_net_193:7 8.208929e-05 +8 chany_bottom_out[4] ropt_net_193:4 1.215788e-06 +9 chany_bottom_out[4]:2 ropt_net_193:8 8.208929e-05 +10 chany_bottom_out[4]:2 ropt_net_193:3 1.215788e-06 + +*RES +0 mux_bottom_track_9\/mux_l4_in_0_:X chany_bottom_out[4]:6 0.152 +1 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +2 chany_bottom_out[4]:2 chany_bottom_out[4] 0.02643304 +3 chany_bottom_out[4]:6 chany_bottom_out[4]:5 0.0001300676 +4 chany_bottom_out[4]:5 chany_bottom_out[4]:4 0.0002723215 +5 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.006120536 + +*END + +*D_NET ropt_net_145 0.001948377 //LENGTH 16.585 LUMPCC 0.0005058218 DR + +*CONN +*I mux_left_track_23\/BUFT_RR_68:X O *L 0 *C 5.980 86.360 +*I ropt_mt_inst_770:A I *L 0.001766 *C 3.220 99.280 +*N ropt_net_145:2 *C 3.220 99.280 +*N ropt_net_145:3 *C 3.220 99.235 +*N ropt_net_145:4 *C 3.220 90.440 +*N ropt_net_145:5 *C 4.140 90.440 +*N ropt_net_145:6 *C 4.140 86.405 +*N ropt_net_145:7 *C 4.185 86.360 +*N ropt_net_145:8 *C 5.942 86.360 + +*CAP +0 mux_left_track_23\/BUFT_RR_68:X 1e-06 +1 ropt_mt_inst_770:A 1e-06 +2 ropt_net_145:2 3.097851e-05 +3 ropt_net_145:3 0.0002891644 +4 ropt_net_145:4 0.0003354496 +5 ropt_net_145:5 0.0002770771 +6 ropt_net_145:6 0.0002307919 +7 ropt_net_145:7 0.000138547 +8 ropt_net_145:8 0.000138547 +9 ropt_net_145:3 chany_top_in[7]:5 0.0001030221 +10 ropt_net_145:4 chany_top_in[7]:4 0.0001030221 +11 ropt_net_145:3 left_top_grid_pin_44_[0] 5.692972e-05 +12 ropt_net_145:4 left_top_grid_pin_44_[0]:23 8.28269e-06 +13 ropt_net_145:4 left_top_grid_pin_44_[0]:24 5.692972e-05 +14 ropt_net_145:5 left_top_grid_pin_44_[0]:22 8.28269e-06 +15 ropt_net_145:3 ropt_net_184:5 8.467639e-05 +16 ropt_net_145:4 ropt_net_184:4 8.467639e-05 + +*RES +0 mux_left_track_23\/BUFT_RR_68:X ropt_net_145:8 0.152 +1 ropt_net_145:8 ropt_net_145:7 0.001569197 +2 ropt_net_145:7 ropt_net_145:6 0.0045 +3 ropt_net_145:6 ropt_net_145:5 0.003602678 +4 ropt_net_145:2 ropt_mt_inst_770:A 0.152 +5 ropt_net_145:3 ropt_net_145:2 0.0045 +6 ropt_net_145:4 ropt_net_145:3 0.007852679 +7 ropt_net_145:5 ropt_net_145:4 0.0008214285 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[2] 0.002136871 //LENGTH 16.585 LUMPCC 0 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 63.785 115.260 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 63.195 113.220 +*I mux_top_track_4\/mux_l3_in_1_:S I *L 0.00357 *C 57.860 110.840 +*I mux_top_track_4\/mux_l3_in_0_:S I *L 0.00357 *C 60.160 117.640 +*N mux_tree_tapbuf_size14_0_sram[2]:4 *C 60.160 117.640 +*N mux_tree_tapbuf_size14_0_sram[2]:5 *C 60.260 117.595 +*N mux_tree_tapbuf_size14_0_sram[2]:6 *C 57.898 110.840 +*N mux_tree_tapbuf_size14_0_sram[2]:7 *C 60.215 110.840 +*N mux_tree_tapbuf_size14_0_sram[2]:8 *C 60.260 110.885 +*N mux_tree_tapbuf_size14_0_sram[2]:9 *C 60.260 114.920 +*N mux_tree_tapbuf_size14_0_sram[2]:10 *C 60.305 114.920 +*N mux_tree_tapbuf_size14_0_sram[2]:11 *C 63.195 113.220 +*N mux_tree_tapbuf_size14_0_sram[2]:12 *C 63.020 113.220 +*N mux_tree_tapbuf_size14_0_sram[2]:13 *C 63.020 113.265 +*N mux_tree_tapbuf_size14_0_sram[2]:14 *C 63.020 114.875 +*N mux_tree_tapbuf_size14_0_sram[2]:15 *C 63.020 114.920 +*N mux_tree_tapbuf_size14_0_sram[2]:16 *C 63.480 114.920 +*N mux_tree_tapbuf_size14_0_sram[2]:17 *C 63.480 115.225 +*N mux_tree_tapbuf_size14_0_sram[2]:18 *C 63.758 115.238 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_top_track_4\/mux_l3_in_1_:S 1e-06 +3 mux_top_track_4\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size14_0_sram[2]:4 3.0642e-05 +5 mux_tree_tapbuf_size14_0_sram[2]:5 0.0001639357 +6 mux_tree_tapbuf_size14_0_sram[2]:6 0.0001824186 +7 mux_tree_tapbuf_size14_0_sram[2]:7 0.0001824186 +8 mux_tree_tapbuf_size14_0_sram[2]:8 0.0002196374 +9 mux_tree_tapbuf_size14_0_sram[2]:9 0.000415359 +10 mux_tree_tapbuf_size14_0_sram[2]:10 0.0001957681 +11 mux_tree_tapbuf_size14_0_sram[2]:11 5.095885e-05 +12 mux_tree_tapbuf_size14_0_sram[2]:12 5.495254e-05 +13 mux_tree_tapbuf_size14_0_sram[2]:13 0.0001118246 +14 mux_tree_tapbuf_size14_0_sram[2]:14 0.0001118246 +15 mux_tree_tapbuf_size14_0_sram[2]:15 0.0002539837 +16 mux_tree_tapbuf_size14_0_sram[2]:16 6.335208e-05 +17 mux_tree_tapbuf_size14_0_sram[2]:17 6.085313e-05 +18 mux_tree_tapbuf_size14_0_sram[2]:18 3.494285e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size14_0_sram[2]:18 0.152 +1 mux_tree_tapbuf_size14_0_sram[2]:6 mux_top_track_4\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size14_0_sram[2]:7 mux_tree_tapbuf_size14_0_sram[2]:6 0.002069196 +3 mux_tree_tapbuf_size14_0_sram[2]:8 mux_tree_tapbuf_size14_0_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size14_0_sram[2]:10 mux_tree_tapbuf_size14_0_sram[2]:9 0.0045 +5 mux_tree_tapbuf_size14_0_sram[2]:9 mux_tree_tapbuf_size14_0_sram[2]:8 0.003602679 +6 mux_tree_tapbuf_size14_0_sram[2]:9 mux_tree_tapbuf_size14_0_sram[2]:5 0.002388393 +7 mux_tree_tapbuf_size14_0_sram[2]:4 mux_top_track_4\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size14_0_sram[2]:5 mux_tree_tapbuf_size14_0_sram[2]:4 0.0045 +9 mux_tree_tapbuf_size14_0_sram[2]:15 mux_tree_tapbuf_size14_0_sram[2]:14 0.0045 +10 mux_tree_tapbuf_size14_0_sram[2]:15 mux_tree_tapbuf_size14_0_sram[2]:10 0.002424107 +11 mux_tree_tapbuf_size14_0_sram[2]:14 mux_tree_tapbuf_size14_0_sram[2]:13 0.0014375 +12 mux_tree_tapbuf_size14_0_sram[2]:12 mux_tree_tapbuf_size14_0_sram[2]:11 9.51087e-05 +13 mux_tree_tapbuf_size14_0_sram[2]:13 mux_tree_tapbuf_size14_0_sram[2]:12 0.0045 +14 mux_tree_tapbuf_size14_0_sram[2]:11 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +15 mux_tree_tapbuf_size14_0_sram[2]:18 mux_tree_tapbuf_size14_0_sram[2]:17 0.0001875 +16 mux_tree_tapbuf_size14_0_sram[2]:16 mux_tree_tapbuf_size14_0_sram[2]:15 0.0004107143 +17 mux_tree_tapbuf_size14_0_sram[2]:17 mux_tree_tapbuf_size14_0_sram[2]:16 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size3_3_sram[0] 0.00470171 //LENGTH 34.285 LUMPCC 0.0001741994 DR + +*CONN +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.005 75.140 +*I mux_left_track_23\/mux_l1_in_1_:S I *L 0.00357 *C 39.460 80.240 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 47.095 82.620 +*I mux_left_track_23\/mux_l1_in_0_:S I *L 0.00357 *C 56.680 77.520 +*N mux_tree_tapbuf_size3_3_sram[0]:4 *C 56.643 77.520 +*N mux_tree_tapbuf_size3_3_sram[0]:5 *C 53.865 77.520 +*N mux_tree_tapbuf_size3_3_sram[0]:6 *C 53.820 77.475 +*N mux_tree_tapbuf_size3_3_sram[0]:7 *C 53.820 75.525 +*N mux_tree_tapbuf_size3_3_sram[0]:8 *C 53.775 75.480 +*N mux_tree_tapbuf_size3_3_sram[0]:9 *C 47.058 82.620 +*N mux_tree_tapbuf_size3_3_sram[0]:10 *C 46.505 82.620 +*N mux_tree_tapbuf_size3_3_sram[0]:11 *C 46.460 82.620 +*N mux_tree_tapbuf_size3_3_sram[0]:12 *C 39.460 80.240 +*N mux_tree_tapbuf_size3_3_sram[0]:13 *C 39.560 80.285 +*N mux_tree_tapbuf_size3_3_sram[0]:14 *C 39.560 82.223 +*N mux_tree_tapbuf_size3_3_sram[0]:15 *C 39.568 82.280 +*N mux_tree_tapbuf_size3_3_sram[0]:16 *C 46.453 82.280 +*N mux_tree_tapbuf_size3_3_sram[0]:17 *C 46.460 82.223 +*N mux_tree_tapbuf_size3_3_sram[0]:18 *C 46.460 75.525 +*N mux_tree_tapbuf_size3_3_sram[0]:19 *C 46.460 75.480 +*N mux_tree_tapbuf_size3_3_sram[0]:20 *C 44.620 75.480 +*N mux_tree_tapbuf_size3_3_sram[0]:21 *C 44.620 75.140 +*N mux_tree_tapbuf_size3_3_sram[0]:22 *C 44.043 75.140 + +*CAP +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_23\/mux_l1_in_1_:S 1e-06 +2 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_23\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_3_sram[0]:4 0.00015421 +5 mux_tree_tapbuf_size3_3_sram[0]:5 0.00015421 +6 mux_tree_tapbuf_size3_3_sram[0]:6 0.0001180234 +7 mux_tree_tapbuf_size3_3_sram[0]:7 0.0001180234 +8 mux_tree_tapbuf_size3_3_sram[0]:8 0.000551883 +9 mux_tree_tapbuf_size3_3_sram[0]:9 9.240646e-05 +10 mux_tree_tapbuf_size3_3_sram[0]:10 9.240646e-05 +11 mux_tree_tapbuf_size3_3_sram[0]:11 5.274426e-05 +12 mux_tree_tapbuf_size3_3_sram[0]:12 2.92386e-05 +13 mux_tree_tapbuf_size3_3_sram[0]:13 0.0001513176 +14 mux_tree_tapbuf_size3_3_sram[0]:14 0.0001513176 +15 mux_tree_tapbuf_size3_3_sram[0]:15 0.0005258308 +16 mux_tree_tapbuf_size3_3_sram[0]:16 0.0005258308 +17 mux_tree_tapbuf_size3_3_sram[0]:17 0.0004198505 +18 mux_tree_tapbuf_size3_3_sram[0]:18 0.0003998845 +19 mux_tree_tapbuf_size3_3_sram[0]:19 0.0007174314 +20 mux_tree_tapbuf_size3_3_sram[0]:20 0.0001575395 +21 mux_tree_tapbuf_size3_3_sram[0]:21 6.880253e-05 +22 mux_tree_tapbuf_size3_3_sram[0]:22 4.25596e-05 +23 mux_tree_tapbuf_size3_3_sram[0]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.687036e-05 +24 mux_tree_tapbuf_size3_3_sram[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.687036e-05 +25 mux_tree_tapbuf_size3_3_sram[0]:14 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.293366e-07 +26 mux_tree_tapbuf_size3_3_sram[0]:13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.293366e-07 + +*RES +0 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_3_sram[0]:22 0.152 +1 mux_tree_tapbuf_size3_3_sram[0]:19 mux_tree_tapbuf_size3_3_sram[0]:18 0.0045 +2 mux_tree_tapbuf_size3_3_sram[0]:19 mux_tree_tapbuf_size3_3_sram[0]:8 0.00653125 +3 mux_tree_tapbuf_size3_3_sram[0]:18 mux_tree_tapbuf_size3_3_sram[0]:17 0.005979911 +4 mux_tree_tapbuf_size3_3_sram[0]:22 mux_tree_tapbuf_size3_3_sram[0]:21 0.000515625 +5 mux_tree_tapbuf_size3_3_sram[0]:8 mux_tree_tapbuf_size3_3_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size3_3_sram[0]:7 mux_tree_tapbuf_size3_3_sram[0]:6 0.001741071 +7 mux_tree_tapbuf_size3_3_sram[0]:5 mux_tree_tapbuf_size3_3_sram[0]:4 0.002479911 +8 mux_tree_tapbuf_size3_3_sram[0]:6 mux_tree_tapbuf_size3_3_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size3_3_sram[0]:4 mux_left_track_23\/mux_l1_in_0_:S 0.152 +10 mux_tree_tapbuf_size3_3_sram[0]:10 mux_tree_tapbuf_size3_3_sram[0]:9 0.0004933036 +11 mux_tree_tapbuf_size3_3_sram[0]:11 mux_tree_tapbuf_size3_3_sram[0]:10 0.0045 +12 mux_tree_tapbuf_size3_3_sram[0]:9 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:16 0.00341 +14 mux_tree_tapbuf_size3_3_sram[0]:17 mux_tree_tapbuf_size3_3_sram[0]:11 0.0001911058 +15 mux_tree_tapbuf_size3_3_sram[0]:16 mux_tree_tapbuf_size3_3_sram[0]:15 0.00107865 +16 mux_tree_tapbuf_size3_3_sram[0]:14 mux_tree_tapbuf_size3_3_sram[0]:13 0.001729911 +17 mux_tree_tapbuf_size3_3_sram[0]:15 mux_tree_tapbuf_size3_3_sram[0]:14 0.00341 +18 mux_tree_tapbuf_size3_3_sram[0]:12 mux_left_track_23\/mux_l1_in_1_:S 0.152 +19 mux_tree_tapbuf_size3_3_sram[0]:13 mux_tree_tapbuf_size3_3_sram[0]:12 0.0045 +20 mux_tree_tapbuf_size3_3_sram[0]:21 mux_tree_tapbuf_size3_3_sram[0]:20 0.0003035715 +21 mux_tree_tapbuf_size3_3_sram[0]:20 mux_tree_tapbuf_size3_3_sram[0]:19 0.001642857 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_0_ccff_tail[0] 0.001592332 //LENGTH 14.170 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/FTB_19__51:X O *L 0 *C 89.475 63.920 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 79.295 60.860 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 *C 79.333 60.860 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 *C 87.355 60.860 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 *C 87.400 60.905 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 *C 87.400 63.875 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 *C 87.445 63.920 +*N mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 *C 89.438 63.920 + +*CAP +0 mem_left_track_9\/FTB_19__51:X 1e-06 +1 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 0.0004982795 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.0004982795 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.0001712949 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0001712949 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.0001255918 +7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.0001255918 + +*RES +0 mem_left_track_9\/FTB_19__51:X mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:2 0.007162946 +3 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:4 0.002651786 +6 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_0_ccff_tail[0]:6 0.001779018 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.001098239 //LENGTH 9.155 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 78.505 23.120 +*I mux_bottom_track_25\/mux_l3_in_0_:S I *L 0.00357 *C 79.940 20.400 +*I mem_bottom_track_25\/FTB_16__48:A I *L 0.001746 *C 82.800 23.120 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 82.763 23.120 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 79.903 20.400 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 78.705 20.400 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 78.660 20.445 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 78.660 23.075 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 78.705 23.120 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 78.505 23.120 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_25\/FTB_16__48:A 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 0.0002340371 +4 mux_tree_tapbuf_size6_1_sram[2]:4 0.0001145418 +5 mux_tree_tapbuf_size6_1_sram[2]:5 0.0001145418 +6 mux_tree_tapbuf_size6_1_sram[2]:6 0.0001659807 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0001659807 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0002532842 +9 mux_tree_tapbuf_size6_1_sram[2]:9 4.687241e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:9 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.0001086957 +2 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:3 0.003622768 +4 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.002348214 +5 mux_tree_tapbuf_size6_1_sram[2]:5 mux_tree_tapbuf_size6_1_sram[2]:4 0.001069196 +6 mux_tree_tapbuf_size6_1_sram[2]:6 mux_tree_tapbuf_size6_1_sram[2]:5 0.0045 +7 mux_tree_tapbuf_size6_1_sram[2]:4 mux_bottom_track_25\/mux_l3_in_0_:S 0.152 +8 mux_tree_tapbuf_size6_1_sram[2]:3 mem_bottom_track_25\/FTB_16__48:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[1] 0.001705394 //LENGTH 13.550 LUMPCC 0.000115924 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 47.685 42.500 +*I mux_bottom_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 44.980 40.120 +*I mux_bottom_track_17\/mux_l2_in_1_:S I *L 0.00357 *C 45.440 46.920 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 50.775 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:4 *C 50.738 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:5 *C 45.440 46.920 +*N mux_tree_tapbuf_size7_2_sram[1]:6 *C 45.540 46.875 +*N mux_tree_tapbuf_size7_2_sram[1]:7 *C 44.980 40.120 +*N mux_tree_tapbuf_size7_2_sram[1]:8 *C 45.080 40.165 +*N mux_tree_tapbuf_size7_2_sram[1]:9 *C 45.080 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:10 *C 45.540 42.545 +*N mux_tree_tapbuf_size7_2_sram[1]:11 *C 45.585 42.500 +*N mux_tree_tapbuf_size7_2_sram[1]:12 *C 47.685 42.500 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_track_17\/mux_l2_in_1_:S 1e-06 +3 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size7_2_sram[1]:4 0.0002023255 +5 mux_tree_tapbuf_size7_2_sram[1]:5 3.042867e-05 +6 mux_tree_tapbuf_size7_2_sram[1]:6 0.000221387 +7 mux_tree_tapbuf_size7_2_sram[1]:7 2.973123e-05 +8 mux_tree_tapbuf_size7_2_sram[1]:8 0.000146008 +9 mux_tree_tapbuf_size7_2_sram[1]:9 0.000180618 +10 mux_tree_tapbuf_size7_2_sram[1]:10 0.000255997 +11 mux_tree_tapbuf_size7_2_sram[1]:11 0.0001434201 +12 mux_tree_tapbuf_size7_2_sram[1]:12 0.0003755548 +13 mux_tree_tapbuf_size7_2_sram[1]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 4.72169e-06 +14 mux_tree_tapbuf_size7_2_sram[1]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.324031e-05 +15 mux_tree_tapbuf_size7_2_sram[1]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 5.324031e-05 +16 mux_tree_tapbuf_size7_2_sram[1]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 4.72169e-06 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size7_2_sram[1]:12 0.152 +1 mux_tree_tapbuf_size7_2_sram[1]:7 mux_bottom_track_17\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size7_2_sram[1]:8 mux_tree_tapbuf_size7_2_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size7_2_sram[1]:5 mux_bottom_track_17\/mux_l2_in_1_:S 0.152 +4 mux_tree_tapbuf_size7_2_sram[1]:6 mux_tree_tapbuf_size7_2_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size7_2_sram[1]:11 mux_tree_tapbuf_size7_2_sram[1]:10 0.0045 +6 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:9 0.0004107143 +7 mux_tree_tapbuf_size7_2_sram[1]:10 mux_tree_tapbuf_size7_2_sram[1]:6 0.003866072 +8 mux_tree_tapbuf_size7_2_sram[1]:4 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +9 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:11 0.001875 +10 mux_tree_tapbuf_size7_2_sram[1]:12 mux_tree_tapbuf_size7_2_sram[1]:4 0.002725447 +11 mux_tree_tapbuf_size7_2_sram[1]:9 mux_tree_tapbuf_size7_2_sram[1]:8 0.002084821 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[0] 0.008481575 //LENGTH 62.175 LUMPCC 0.001462847 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 26.065 66.300 +*I mux_left_track_7\/mux_l1_in_3_:S I *L 0.00357 *C 34.860 63.920 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 46.175 58.820 +*I mux_left_track_7\/mux_l1_in_0_:S I *L 0.00357 *C 68.640 52.700 +*I mux_left_track_7\/mux_l1_in_1_:S I *L 0.00357 *C 59.900 58.755 +*I mux_left_track_7\/mux_l1_in_2_:S I *L 0.00357 *C 25.200 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:6 *C 25.200 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:7 *C 59.900 58.793 +*N mux_tree_tapbuf_size7_6_sram[0]:8 *C 68.640 52.700 +*N mux_tree_tapbuf_size7_6_sram[0]:9 *C 67.205 52.700 +*N mux_tree_tapbuf_size7_6_sram[0]:10 *C 67.160 52.745 +*N mux_tree_tapbuf_size7_6_sram[0]:11 *C 67.160 59.115 +*N mux_tree_tapbuf_size7_6_sram[0]:12 *C 67.115 59.160 +*N mux_tree_tapbuf_size7_6_sram[0]:13 *C 59.900 59.160 +*N mux_tree_tapbuf_size7_6_sram[0]:14 *C 46.175 58.820 +*N mux_tree_tapbuf_size7_6_sram[0]:15 *C 46.068 59.160 +*N mux_tree_tapbuf_size7_6_sram[0]:16 *C 46.000 59.205 +*N mux_tree_tapbuf_size7_6_sram[0]:17 *C 46.000 63.183 +*N mux_tree_tapbuf_size7_6_sram[0]:18 *C 45.992 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:19 *C 34.860 63.920 +*N mux_tree_tapbuf_size7_6_sram[0]:20 *C 34.960 63.875 +*N mux_tree_tapbuf_size7_6_sram[0]:21 *C 34.960 63.298 +*N mux_tree_tapbuf_size7_6_sram[0]:22 *C 34.960 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:23 *C 25.308 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:24 *C 25.300 63.240 +*N mux_tree_tapbuf_size7_6_sram[0]:25 *C 25.300 66.255 +*N mux_tree_tapbuf_size7_6_sram[0]:26 *C 25.345 66.300 +*N mux_tree_tapbuf_size7_6_sram[0]:27 *C 26.027 66.300 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_7\/mux_l1_in_3_:S 1e-06 +2 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_7\/mux_l1_in_0_:S 1e-06 +4 mux_left_track_7\/mux_l1_in_1_:S 1e-06 +5 mux_left_track_7\/mux_l1_in_2_:S 1e-06 +6 mux_tree_tapbuf_size7_6_sram[0]:6 2.911853e-05 +7 mux_tree_tapbuf_size7_6_sram[0]:7 3.3174e-05 +8 mux_tree_tapbuf_size7_6_sram[0]:8 0.0001341524 +9 mux_tree_tapbuf_size7_6_sram[0]:9 0.000102244 +10 mux_tree_tapbuf_size7_6_sram[0]:10 0.0003617247 +11 mux_tree_tapbuf_size7_6_sram[0]:11 0.0003617247 +12 mux_tree_tapbuf_size7_6_sram[0]:12 0.0004895478 +13 mux_tree_tapbuf_size7_6_sram[0]:13 0.001437406 +14 mux_tree_tapbuf_size7_6_sram[0]:14 6.194089e-05 +15 mux_tree_tapbuf_size7_6_sram[0]:15 0.0009484504 +16 mux_tree_tapbuf_size7_6_sram[0]:16 0.0002541873 +17 mux_tree_tapbuf_size7_6_sram[0]:17 0.0002541873 +18 mux_tree_tapbuf_size7_6_sram[0]:18 0.0006079358 +19 mux_tree_tapbuf_size7_6_sram[0]:19 3.174965e-05 +20 mux_tree_tapbuf_size7_6_sram[0]:20 5.831025e-05 +21 mux_tree_tapbuf_size7_6_sram[0]:21 5.831025e-05 +22 mux_tree_tapbuf_size7_6_sram[0]:22 0.0009357571 +23 mux_tree_tapbuf_size7_6_sram[0]:23 0.0003278212 +24 mux_tree_tapbuf_size7_6_sram[0]:24 0.0002152473 +25 mux_tree_tapbuf_size7_6_sram[0]:25 0.0001791462 +26 mux_tree_tapbuf_size7_6_sram[0]:26 6.529588e-05 +27 mux_tree_tapbuf_size7_6_sram[0]:27 6.529588e-05 +28 mux_tree_tapbuf_size7_6_sram[0]:10 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.0001088498 +29 mux_tree_tapbuf_size7_6_sram[0]:11 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0001088498 +30 mux_tree_tapbuf_size7_6_sram[0]:23 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001330457 +31 mux_tree_tapbuf_size7_6_sram[0]:18 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.527713e-05 +32 mux_tree_tapbuf_size7_6_sram[0]:22 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.527713e-05 +33 mux_tree_tapbuf_size7_6_sram[0]:22 mux_left_track_7/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0001330457 +34 mux_tree_tapbuf_size7_6_sram[0]:23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002183084 +35 mux_tree_tapbuf_size7_6_sram[0]:18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002159423 +36 mux_tree_tapbuf_size7_6_sram[0]:22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002159423 +37 mux_tree_tapbuf_size7_6_sram[0]:22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002183084 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_6_sram[0]:27 0.152 +1 mux_tree_tapbuf_size7_6_sram[0]:7 mux_left_track_7\/mux_l1_in_1_:S 0.152 +2 mux_tree_tapbuf_size7_6_sram[0]:14 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +3 mux_tree_tapbuf_size7_6_sram[0]:24 mux_tree_tapbuf_size7_6_sram[0]:23 0.00341 +4 mux_tree_tapbuf_size7_6_sram[0]:24 mux_tree_tapbuf_size7_6_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size7_6_sram[0]:23 mux_tree_tapbuf_size7_6_sram[0]:22 0.001512225 +6 mux_tree_tapbuf_size7_6_sram[0]:15 mux_tree_tapbuf_size7_6_sram[0]:14 0.0001847826 +7 mux_tree_tapbuf_size7_6_sram[0]:15 mux_tree_tapbuf_size7_6_sram[0]:13 0.01235045 +8 mux_tree_tapbuf_size7_6_sram[0]:16 mux_tree_tapbuf_size7_6_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size7_6_sram[0]:17 mux_tree_tapbuf_size7_6_sram[0]:16 0.00355134 +10 mux_tree_tapbuf_size7_6_sram[0]:18 mux_tree_tapbuf_size7_6_sram[0]:17 0.00341 +11 mux_tree_tapbuf_size7_6_sram[0]:26 mux_tree_tapbuf_size7_6_sram[0]:25 0.0045 +12 mux_tree_tapbuf_size7_6_sram[0]:25 mux_tree_tapbuf_size7_6_sram[0]:24 0.002691964 +13 mux_tree_tapbuf_size7_6_sram[0]:27 mux_tree_tapbuf_size7_6_sram[0]:26 0.0006093751 +14 mux_tree_tapbuf_size7_6_sram[0]:21 mux_tree_tapbuf_size7_6_sram[0]:20 0.000515625 +15 mux_tree_tapbuf_size7_6_sram[0]:22 mux_tree_tapbuf_size7_6_sram[0]:21 0.00341 +16 mux_tree_tapbuf_size7_6_sram[0]:22 mux_tree_tapbuf_size7_6_sram[0]:18 0.001728425 +17 mux_tree_tapbuf_size7_6_sram[0]:19 mux_left_track_7\/mux_l1_in_3_:S 0.152 +18 mux_tree_tapbuf_size7_6_sram[0]:20 mux_tree_tapbuf_size7_6_sram[0]:19 0.0045 +19 mux_tree_tapbuf_size7_6_sram[0]:6 mux_left_track_7\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size7_6_sram[0]:8 mux_left_track_7\/mux_l1_in_0_:S 0.152 +21 mux_tree_tapbuf_size7_6_sram[0]:9 mux_tree_tapbuf_size7_6_sram[0]:8 0.00128125 +22 mux_tree_tapbuf_size7_6_sram[0]:10 mux_tree_tapbuf_size7_6_sram[0]:9 0.0045 +23 mux_tree_tapbuf_size7_6_sram[0]:12 mux_tree_tapbuf_size7_6_sram[0]:11 0.0045 +24 mux_tree_tapbuf_size7_6_sram[0]:11 mux_tree_tapbuf_size7_6_sram[0]:10 0.0056875 +25 mux_tree_tapbuf_size7_6_sram[0]:13 mux_tree_tapbuf_size7_6_sram[0]:12 0.006441964 +26 mux_tree_tapbuf_size7_6_sram[0]:13 mux_tree_tapbuf_size7_6_sram[0]:7 0.0003281251 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001246676 //LENGTH 9.375 LUMPCC 0.0003857422 DR + +*CONN +*I mux_top_track_0\/mux_l1_in_1_:X O *L 0 *C 45.715 123.080 +*I mux_top_track_0\/mux_l2_in_0_:A0 I *L 0.001631 *C 41.690 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 41.727 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 45.035 118.660 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 45.080 118.705 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 45.080 123.035 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 45.125 123.080 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 45.678 123.080 + +*CAP +0 mux_top_track_0\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000181563 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.000181563 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001793423 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001793423 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.856163e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.856163e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 top_left_grid_pin_34_[0]:14 0.000119704 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 top_left_grid_pin_34_[0]:15 0.000119704 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size10_0_sram[1]:26 6.853416e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size10_0_sram[1]:27 6.853416e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size10_0_sram[1]:28 4.63289e-06 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size10_0_sram[1]:29 4.63289e-06 + +*RES +0 mux_top_track_0\/mux_l1_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_0\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002953125 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.003866072 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0006611042 //LENGTH 4.650 LUMPCC 0.0001639953 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 49.395 22.780 +*I mux_bottom_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 48.205 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 48.242 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 49.175 20.060 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 49.220 20.105 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 49.220 22.735 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 49.220 22.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 49.395 22.780 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 4.689275e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.689275e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001465738 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001465738 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.361027e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.456559e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size10_1_sram[2]:7 4.884561e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size10_1_sram[2]:8 4.884561e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size10_1_sram[2]:9 3.315203e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size10_1_sram[2]:12 3.315203e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008325893 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.510871e-05 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009915255 //LENGTH 8.430 LUMPCC 0.0002235824 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_0_:X O *L 0 *C 83.545 104.040 +*I mux_top_track_8\/mux_l3_in_0_:A1 I *L 0.00198 *C 83.820 96.220 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 83.720 96.220 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 83.720 96.265 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 83.720 103.995 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 83.720 104.040 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 83.545 104.040 + +*CAP +0 mux_top_track_8\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.335018e-05 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003068986 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003068986 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.952262e-05 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.927308e-05 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_in[10]:7 0.0001117912 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[10]:6 0.0001117912 + +*RES +0 mux_top_track_8\/mux_l2_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_8\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.006901786 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.51087e-05 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0] 0.002277797 //LENGTH 20.240 LUMPCC 0.0004703825 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_1_:X O *L 0 *C 58.705 109.820 +*I mux_top_track_4\/mux_l4_in_0_:A0 I *L 0.001631 *C 69.175 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 *C 69.138 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 *C 68.585 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 *C 68.540 118.615 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 *C 68.540 109.865 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 *C 68.495 109.820 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 *C 58.742 109.820 + +*CAP +0 mux_top_track_4\/mux_l3_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 5.33944e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 5.33944e-05 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0003094164 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0003094164 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.0005398965 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.0005398965 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 chany_top_out[8]:5 0.0001167083 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 chany_top_out[8]:6 0.0001167083 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_tree_tapbuf_size14_0_sram[3]:5 3.703852e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_tree_tapbuf_size14_0_sram[3]:9 2.159133e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_tree_tapbuf_size14_0_sram[3]:8 2.159133e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_tree_tapbuf_size14_0_sram[3]:9 3.703852e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 ropt_net_155:7 5.985308e-05 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 ropt_net_155:6 5.985308e-05 + +*RES +0 mux_top_track_4\/mux_l3_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 mux_top_track_4\/mux_l4_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:2 0.0004933036 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0078125 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:6 0.008707589 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0] 0.0004079491 //LENGTH 3.400 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_1_:X O *L 0 *C 39.385 9.860 +*I mux_bottom_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 42.495 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 42.458 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 39.422 9.860 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0002029746 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0002029746 + +*RES +0 mux_bottom_track_5\/mux_l2_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002709822 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001728488 //LENGTH 11.990 LUMPCC 0.0006571408 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_1_:X O *L 0 *C 37.545 86.360 +*I mux_top_track_24\/mux_l3_in_0_:A0 I *L 0.001631 *C 43.415 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 43.378 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 42.320 91.460 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 42.320 91.120 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 37.765 91.120 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 37.720 91.075 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 37.720 86.405 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 37.720 86.360 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 37.545 86.360 + +*CAP +0 mux_top_track_24\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.096964e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.547432e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002109573 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001864526 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002023831 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0002023831 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:8 6.116024e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:9 5.956721e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_top_in[2]:17 4.824962e-05 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_top_in[2]:16 6.71108e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_top_in[2]:17 6.71108e-05 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_top_in[2]:16 4.824962e-05 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size7_1_sram[1]:13 0.0001110517 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:7 6.692021e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:11 2.566075e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size7_1_sram[1]:12 9.577292e-06 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:8 6.692021e-05 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:10 2.566075e-05 +20 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size7_1_sram[1]:11 9.577292e-06 +21 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size7_1_sram[1]:14 0.0001110517 + +*RES +0 mux_top_track_24\/mux_l2_in_1_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.004066965 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.004169643 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:8 9.51087e-05 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0003035715 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0009441964 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002485445 //LENGTH 19.985 LUMPCC 0.0001692164 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 40.195 65.960 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 27.600 72.420 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 27.638 72.420 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.475 72.420 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.520 72.375 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.520 66.005 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 28.565 65.960 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 40.157 65.960 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.946614e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.946614e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003787788 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003787788 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0007088697 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0007088697 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[17]:3 8.428581e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[17]:4 8.428581e-05 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[17]:6 3.223907e-07 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[17]:5 3.223907e-07 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01035045 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0056875 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0007477679 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001231471 //LENGTH 11.320 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/mux_l2_in_1_:X O *L 0 *C 75.725 75.140 +*I mux_top_track_32\/mux_l3_in_0_:A0 I *L 0.001631 *C 80.675 80.580 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 80.638 80.580 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 80.085 80.580 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 80.040 80.535 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 80.040 75.185 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 79.995 75.140 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 75.763 75.140 + +*CAP +0 mux_top_track_32\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_32\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.496118e-05 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 5.496118e-05 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002906377 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002906377 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0002691364 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0002691364 + +*RES +0 mux_top_track_32\/mux_l2_in_1_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_32\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004933036 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004776786 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.003779018 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009904049 //LENGTH 8.340 LUMPCC 0.0001328131 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_0_:X O *L 0 *C 26.855 36.380 +*I mux_bottom_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 22.640 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 22.540 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 22.540 39.735 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 22.540 36.425 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 22.585 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 26.818 36.380 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.19318e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001554005 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001554005 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002564295 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002564295 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 6.640656e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.640656e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002955358 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.003779018 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.006781959 //LENGTH 44.370 LUMPCC 0.002389213 DR + +*CONN +*I mux_left_track_15\/mux_l2_in_0_:X O *L 0 *C 44.335 55.420 +*I mux_left_track_15\/mux_l3_in_0_:A1 I *L 0.00198 *C 7.725 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 7.710 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 7.383 58.140 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 7.360 58.185 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 7.360 59.115 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 7.405 59.160 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 14.675 59.160 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 14.720 59.115 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 14.720 57.858 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 14.728 57.800 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 32.193 57.800 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 32.200 57.742 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 32.200 55.465 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 32.245 55.420 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 44.297 55.420 + +*CAP +0 mux_left_track_15\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_15\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.882329e-05 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.882329e-05 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.46954e-05 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.46954e-05 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005147374 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005147374 +8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 9.44942e-05 +9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 9.44942e-05 +10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0005684004 +11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0005684004 +12 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0001500784 +13 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0001500784 +14 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0007441437 +15 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0007441437 +16 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[10] 0.0003921707 +17 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 chanx_left_in[10]:10 7.866335e-07 +18 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[10]:11 0.0003921707 +19 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 chanx_left_in[10]:6 1.903991e-05 +20 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 chanx_left_in[10]:8 0.0001029678 +21 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 chanx_left_in[10]:9 7.866335e-07 +22 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 chanx_left_in[10]:7 0.0001029678 +23 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 chanx_left_in[10]:9 1.903991e-05 +24 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[17]:16 0.000158508 +25 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[17]:17 0.0005211336 +26 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[17]:7 0.000158508 +27 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[17]:16 0.0005211336 + +*RES +0 mux_left_track_15\/mux_l2_in_0_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_15\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001779891 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0008303573 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006491072 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001122768 +9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002736183 +12 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0045 +13 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.002033482 +14 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.01076116 + +*END + +*D_NET ropt_net_158 0.0009022786 //LENGTH 6.650 LUMPCC 0.0002192082 DR + +*CONN +*I FTB_4__3:X O *L 0 *C 69.460 11.560 +*I ropt_mt_inst_783:A I *L 0.001766 *C 73.140 9.520 +*N ropt_net_158:2 *C 73.103 9.520 +*N ropt_net_158:3 *C 70.425 9.520 +*N ropt_net_158:4 *C 70.380 9.565 +*N ropt_net_158:5 *C 70.380 11.515 +*N ropt_net_158:6 *C 70.335 11.560 +*N ropt_net_158:7 *C 69.498 11.560 + +*CAP +0 FTB_4__3:X 1e-06 +1 ropt_mt_inst_783:A 1e-06 +2 ropt_net_158:2 0.0001545819 +3 ropt_net_158:3 0.0001545819 +4 ropt_net_158:4 0.0001045452 +5 ropt_net_158:5 0.0001045452 +6 ropt_net_158:6 8.140812e-05 +7 ropt_net_158:7 8.140812e-05 +8 ropt_net_158:2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 4.755373e-05 +9 ropt_net_158:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 4.755373e-05 +10 ropt_net_158:2 ropt_net_162:4 3.585951e-05 +11 ropt_net_158:3 ropt_net_162:3 3.585951e-05 +12 ropt_net_158:4 ropt_net_162:5 2.619084e-05 +13 ropt_net_158:5 ropt_net_162:6 2.619084e-05 + +*RES +0 FTB_4__3:X ropt_net_158:7 0.152 +1 ropt_net_158:2 ropt_mt_inst_783:A 0.152 +2 ropt_net_158:3 ropt_net_158:2 0.002390625 +3 ropt_net_158:4 ropt_net_158:3 0.0045 +4 ropt_net_158:6 ropt_net_158:5 0.0045 +5 ropt_net_158:5 ropt_net_158:4 0.001741072 +6 ropt_net_158:7 ropt_net_158:6 0.0007477679 + +*END + +*D_NET ropt_net_204 0.001381354 //LENGTH 10.145 LUMPCC 0.0003560019 DR + +*CONN +*I ropt_mt_inst_778:X O *L 0 *C 4.140 41.820 +*I ropt_mt_inst_842:A I *L 0.001766 *C 3.220 39.440 +*N ropt_net_204:2 *C 3.220 39.440 +*N ropt_net_204:3 *C 3.220 39.485 +*N ropt_net_204:4 *C 3.220 40.742 +*N ropt_net_204:5 *C 3.228 40.800 +*N ropt_net_204:6 *C 6.893 40.800 +*N ropt_net_204:7 *C 6.900 40.858 +*N ropt_net_204:8 *C 6.900 41.775 +*N ropt_net_204:9 *C 6.855 41.820 +*N ropt_net_204:10 *C 4.178 41.820 + +*CAP +0 ropt_mt_inst_778:X 1e-06 +1 ropt_mt_inst_842:A 1e-06 +2 ropt_net_204:2 2.92711e-05 +3 ropt_net_204:3 8.772133e-05 +4 ropt_net_204:4 8.772133e-05 +5 ropt_net_204:5 0.0001702318 +6 ropt_net_204:6 0.0001702318 +7 ropt_net_204:7 7.605013e-05 +8 ropt_net_204:8 7.605013e-05 +9 ropt_net_204:9 0.0001630374 +10 ropt_net_204:10 0.0001630374 +11 ropt_net_204:5 chanx_left_in[3] 9.265373e-05 +12 ropt_net_204:6 chanx_left_in[3]:10 9.265373e-05 +13 ropt_net_204:5 chanx_left_in[7] 3.625357e-05 +14 ropt_net_204:5 chanx_left_in[7]:17 3.50386e-06 +15 ropt_net_204:6 chanx_left_in[7]:8 3.50386e-06 +16 ropt_net_204:6 chanx_left_in[7]:17 3.625357e-05 +17 ropt_net_204:9 chanx_left_in[7]:5 4.558978e-05 +18 ropt_net_204:10 chanx_left_in[7]:6 4.558978e-05 + +*RES +0 ropt_mt_inst_778:X ropt_net_204:10 0.152 +1 ropt_net_204:2 ropt_mt_inst_842:A 0.152 +2 ropt_net_204:3 ropt_net_204:2 0.0045 +3 ropt_net_204:4 ropt_net_204:3 0.001122768 +4 ropt_net_204:5 ropt_net_204:4 0.00341 +5 ropt_net_204:7 ropt_net_204:6 0.00341 +6 ropt_net_204:6 ropt_net_204:5 0.0005741833 +7 ropt_net_204:9 ropt_net_204:8 0.0045 +8 ropt_net_204:8 ropt_net_204:7 0.0008191963 +9 ropt_net_204:10 ropt_net_204:9 0.002390625 + +*END + +*D_NET ropt_net_184 0.001110975 //LENGTH 7.865 LUMPCC 0.0005873154 DR + +*CONN +*I ropt_mt_inst_795:X O *L 0 *C 7.095 96.900 +*I ropt_mt_inst_812:A I *L 0.001767 *C 3.220 93.840 +*N ropt_net_184:2 *C 3.258 93.840 +*N ropt_net_184:3 *C 3.635 93.840 +*N ropt_net_184:4 *C 3.680 93.885 +*N ropt_net_184:5 *C 3.680 96.855 +*N ropt_net_184:6 *C 3.725 96.900 +*N ropt_net_184:7 *C 7.058 96.900 + +*CAP +0 ropt_mt_inst_795:X 1e-06 +1 ropt_mt_inst_812:A 1e-06 +2 ropt_net_184:2 4.309045e-05 +3 ropt_net_184:3 4.309045e-05 +4 ropt_net_184:4 7.079204e-05 +5 ropt_net_184:5 7.079204e-05 +6 ropt_net_184:6 0.0001469471 +7 ropt_net_184:7 0.0001469471 +8 ropt_net_184:4 left_top_grid_pin_44_[0]:24 9.072469e-05 +9 ropt_net_184:5 left_top_grid_pin_44_[0] 9.072469e-05 +10 ropt_net_184:4 ropt_net_145:4 8.467639e-05 +11 ropt_net_184:5 ropt_net_145:3 8.467639e-05 +12 ropt_net_184:6 ropt_net_169:2 0.0001182566 +13 ropt_net_184:7 ropt_net_169:3 0.0001182566 + +*RES +0 ropt_mt_inst_795:X ropt_net_184:7 0.152 +1 ropt_net_184:2 ropt_mt_inst_812:A 0.152 +2 ropt_net_184:3 ropt_net_184:2 0.0003370536 +3 ropt_net_184:4 ropt_net_184:3 0.0045 +4 ropt_net_184:6 ropt_net_184:5 0.0045 +5 ropt_net_184:5 ropt_net_184:4 0.002651786 +6 ropt_net_184:7 ropt_net_184:6 0.002975446 + +*END + +*D_NET chany_top_out[10] 0.001100444 //LENGTH 9.830 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_827:X O *L 0 *C 100.740 124.440 +*P chany_top_out[10] O *L 0.7423 *C 96.600 129.270 +*N chany_top_out[10]:2 *C 96.600 125.858 +*N chany_top_out[10]:3 *C 96.608 125.800 +*N chany_top_out[10]:4 *C 100.733 125.800 +*N chany_top_out[10]:5 *C 100.740 125.743 +*N chany_top_out[10]:6 *C 100.740 124.485 +*N chany_top_out[10]:7 *C 100.740 124.440 + +*CAP +0 ropt_mt_inst_827:X 1e-06 +1 chany_top_out[10] 0.0001902704 +2 chany_top_out[10]:2 0.0001902704 +3 chany_top_out[10]:3 0.0002531775 +4 chany_top_out[10]:4 0.0002531775 +5 chany_top_out[10]:5 9.074973e-05 +6 chany_top_out[10]:6 9.074973e-05 +7 chany_top_out[10]:7 3.104874e-05 + +*RES +0 ropt_mt_inst_827:X chany_top_out[10]:7 0.152 +1 chany_top_out[10]:7 chany_top_out[10]:6 0.0045 +2 chany_top_out[10]:6 chany_top_out[10]:5 0.001122768 +3 chany_top_out[10]:5 chany_top_out[10]:4 0.00341 +4 chany_top_out[10]:4 chany_top_out[10]:3 0.00064625 +5 chany_top_out[10]:2 chany_top_out[10] 0.003046875 +6 chany_top_out[10]:3 chany_top_out[10]:2 0.00341 + +*END + +*D_NET chany_top_in[12] 0.01677966 //LENGTH 139.365 LUMPCC 0.002740733 DR + +*CONN +*P chany_top_in[12] I *L 0.29796 *C 52.900 129.235 +*I mux_left_track_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 55.200 52.700 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 57.790 22.440 +*I FTB_12__11:A I *L 0.001767 *C 58.420 6.800 +*N chany_top_in[12]:4 *C 58.458 6.800 +*N chany_top_in[12]:5 *C 59.340 6.800 +*N chany_top_in[12]:6 *C 59.340 6.460 +*N chany_top_in[12]:7 *C 59.340 6.505 +*N chany_top_in[12]:8 *C 57.790 22.440 +*N chany_top_in[12]:9 *C 57.500 22.440 +*N chany_top_in[12]:10 *C 57.500 22.440 +*N chany_top_in[12]:11 *C 57.508 22.440 +*N chany_top_in[12]:12 *C 59.333 22.440 +*N chany_top_in[12]:13 *C 59.340 22.440 +*N chany_top_in[12]:14 *C 55.238 52.700 +*N chany_top_in[12]:15 *C 59.295 52.700 +*N chany_top_in[12]:16 *C 59.340 52.700 +*N chany_top_in[12]:17 *C 59.340 55.023 +*N chany_top_in[12]:18 *C 59.338 55.080 +*N chany_top_in[12]:19 *C 58.895 55.080 +*N chany_top_in[12]:20 *C 58.880 55.088 +*N chany_top_in[12]:21 *C 58.880 104.915 +*N chany_top_in[12]:22 *C 58.880 127.833 +*N chany_top_in[12]:23 *C 58.860 127.840 +*N chany_top_in[12]:24 *C 52.908 127.840 +*N chany_top_in[12]:25 *C 52.900 127.898 + +*CAP +0 chany_top_in[12] 9.250227e-05 +1 mux_left_track_15\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +3 FTB_12__11:A 1e-06 +4 chany_top_in[12]:4 7.199492e-05 +5 chany_top_in[12]:5 0.0001024799 +6 chany_top_in[12]:6 6.627991e-05 +7 chany_top_in[12]:7 0.0009620015 +8 chany_top_in[12]:8 5.918969e-05 +9 chany_top_in[12]:9 6.136607e-05 +10 chany_top_in[12]:10 3.24854e-05 +11 chany_top_in[12]:11 0.0001495663 +12 chany_top_in[12]:12 0.0001495663 +13 chany_top_in[12]:13 0.002419755 +14 chany_top_in[12]:14 0.0001927523 +15 chany_top_in[12]:15 0.0001927523 +16 chany_top_in[12]:16 0.001611043 +17 chany_top_in[12]:17 0.0001575098 +18 chany_top_in[12]:18 6.870805e-05 +19 chany_top_in[12]:19 6.870805e-05 +20 chany_top_in[12]:20 0.002221099 +21 chany_top_in[12]:21 0.0033302 +22 chany_top_in[12]:22 0.001109102 +23 chany_top_in[12]:23 0.0004121789 +24 chany_top_in[12]:24 0.0004121789 +25 chany_top_in[12]:25 9.250227e-05 +26 chany_top_in[12]:20 chany_top_in[13]:30 6.194555e-05 +27 chany_top_in[12]:20 chany_top_in[13]:31 1.72944e-05 +28 chany_top_in[12]:22 chany_top_in[13]:32 0.0001635661 +29 chany_top_in[12]:12 chany_top_in[13]:24 1.569803e-05 +30 chany_top_in[12]:11 chany_top_in[13]:25 1.569803e-05 +31 chany_top_in[12]:21 chany_top_in[13]:32 1.72944e-05 +32 chany_top_in[12]:21 chany_top_in[13]:31 0.0002255116 +33 chany_top_in[12]:20 chany_bottom_in[5]:20 0.000696492 +34 chany_top_in[12]:21 chany_bottom_in[5]:19 0.000696492 +35 chany_top_in[12]:16 mux_tree_tapbuf_size10_1_sram[0]:22 0.0002090656 +36 chany_top_in[12]:16 mux_tree_tapbuf_size10_1_sram[0]:17 5.781537e-05 +37 chany_top_in[12]:13 mux_tree_tapbuf_size10_1_sram[0]:21 0.0002090656 +38 chany_top_in[12]:13 mux_tree_tapbuf_size10_1_sram[0]:16 5.781537e-05 +39 chany_top_in[12]:15 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.919337e-05 +40 chany_top_in[12]:14 mux_left_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.919337e-05 +41 chany_top_in[12]:4 ropt_net_196:6 1.49484e-05 +42 chany_top_in[12]:7 ropt_net_196:8 6.434798e-05 +43 chany_top_in[12]:13 ropt_net_196:9 6.434798e-05 +44 chany_top_in[12]:5 ropt_net_196:7 1.49484e-05 + +*RES +0 chany_top_in[12] chany_top_in[12]:25 0.001194197 +1 chany_top_in[12]:4 FTB_12__11:A 0.152 +2 chany_top_in[12]:6 chany_top_in[12]:5 0.0003035715 +3 chany_top_in[12]:7 chany_top_in[12]:6 0.0045 +4 chany_top_in[12]:15 chany_top_in[12]:14 0.003622768 +5 chany_top_in[12]:16 chany_top_in[12]:15 0.0045 +6 chany_top_in[12]:16 chany_top_in[12]:13 0.02701786 +7 chany_top_in[12]:14 mux_left_track_15\/mux_l1_in_0_:A1 0.152 +8 chany_top_in[12]:17 chany_top_in[12]:16 0.002073661 +9 chany_top_in[12]:18 chany_top_in[12]:17 0.00341 +10 chany_top_in[12]:19 chany_top_in[12]:18 6.499219e-05 +11 chany_top_in[12]:20 chany_top_in[12]:19 0.00341 +12 chany_top_in[12]:23 chany_top_in[12]:22 0.00341 +13 chany_top_in[12]:22 chany_top_in[12]:21 0.003590408 +14 chany_top_in[12]:25 chany_top_in[12]:24 0.00341 +15 chany_top_in[12]:24 chany_top_in[12]:23 0.0009325583 +16 chany_top_in[12]:13 chany_top_in[12]:12 0.00341 +17 chany_top_in[12]:13 chany_top_in[12]:7 0.01422768 +18 chany_top_in[12]:12 chany_top_in[12]:11 0.0002859166 +19 chany_top_in[12]:10 chany_top_in[12]:9 0.0045 +20 chany_top_in[12]:11 chany_top_in[12]:10 0.00341 +21 chany_top_in[12]:9 chany_top_in[12]:8 0.0001576087 +22 chany_top_in[12]:8 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +23 chany_top_in[12]:5 chany_top_in[12]:4 0.0007879465 +24 chany_top_in[12]:21 chany_top_in[12]:20 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_2_ccff_tail[0] 0.0002794255 //LENGTH 2.070 LUMPCC 0 DR + +*CONN +*I mem_left_track_21\/FTB_25__57:X O *L 0 *C 36.575 75.140 +*I mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.355 75.140 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 *C 38.318 75.140 +*N mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 *C 36.613 75.140 + +*CAP +0 mem_left_track_21\/FTB_25__57:X 1e-06 +1 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 0.0001387128 +3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.0001387128 + +*RES +0 mem_left_track_21\/FTB_25__57:X mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 mem_left_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_2_ccff_tail[0]:2 0.001522321 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[1] 0.007783262 //LENGTH 52.920 LUMPCC 0.002059696 DR + +*CONN +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 46.765 53.040 +*I mux_left_track_15\/mux_l2_in_1_:S I *L 0.00357 *C 12.980 61.200 +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 8.915 53.380 +*I mux_left_track_15\/mux_l2_in_0_:S I *L 0.00357 *C 47.040 56.440 +*N mux_tree_tapbuf_size4_3_sram[1]:4 *C 47.003 56.440 +*N mux_tree_tapbuf_size4_3_sram[1]:5 *C 46.505 56.440 +*N mux_tree_tapbuf_size4_3_sram[1]:6 *C 46.460 56.395 +*N mux_tree_tapbuf_size4_3_sram[1]:7 *C 8.915 53.380 +*N mux_tree_tapbuf_size4_3_sram[1]:8 *C 9.200 53.380 +*N mux_tree_tapbuf_size4_3_sram[1]:9 *C 9.200 53.380 +*N mux_tree_tapbuf_size4_3_sram[1]:10 *C 9.200 53.720 +*N mux_tree_tapbuf_size4_3_sram[1]:11 *C 9.207 53.720 +*N mux_tree_tapbuf_size4_3_sram[1]:12 *C 12.995 61.200 +*N mux_tree_tapbuf_size4_3_sram[1]:13 *C 13.318 61.200 +*N mux_tree_tapbuf_size4_3_sram[1]:14 *C 13.340 61.155 +*N mux_tree_tapbuf_size4_3_sram[1]:15 *C 13.340 53.778 +*N mux_tree_tapbuf_size4_3_sram[1]:16 *C 13.340 53.713 +*N mux_tree_tapbuf_size4_3_sram[1]:17 *C 13.340 53.040 +*N mux_tree_tapbuf_size4_3_sram[1]:18 *C 46.453 53.040 +*N mux_tree_tapbuf_size4_3_sram[1]:19 *C 46.460 53.040 +*N mux_tree_tapbuf_size4_3_sram[1]:20 *C 46.460 53.040 +*N mux_tree_tapbuf_size4_3_sram[1]:21 *C 46.765 53.040 + +*CAP +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_15\/mux_l2_in_1_:S 1e-06 +2 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_left_track_15\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size4_3_sram[1]:4 7.055438e-05 +5 mux_tree_tapbuf_size4_3_sram[1]:5 7.055438e-05 +6 mux_tree_tapbuf_size4_3_sram[1]:6 0.0002366858 +7 mux_tree_tapbuf_size4_3_sram[1]:7 4.747684e-05 +8 mux_tree_tapbuf_size4_3_sram[1]:8 5.246921e-05 +9 mux_tree_tapbuf_size4_3_sram[1]:9 5.44443e-05 +10 mux_tree_tapbuf_size4_3_sram[1]:10 5.83209e-05 +11 mux_tree_tapbuf_size4_3_sram[1]:11 0.0002763847 +12 mux_tree_tapbuf_size4_3_sram[1]:12 5.426209e-05 +13 mux_tree_tapbuf_size4_3_sram[1]:13 5.426209e-05 +14 mux_tree_tapbuf_size4_3_sram[1]:14 0.0003009448 +15 mux_tree_tapbuf_size4_3_sram[1]:15 0.0003009448 +16 mux_tree_tapbuf_size4_3_sram[1]:16 0.0003260173 +17 mux_tree_tapbuf_size4_3_sram[1]:17 0.00174603 +18 mux_tree_tapbuf_size4_3_sram[1]:18 0.001696398 +19 mux_tree_tapbuf_size4_3_sram[1]:19 0.000267058 +20 mux_tree_tapbuf_size4_3_sram[1]:20 5.539048e-05 +21 mux_tree_tapbuf_size4_3_sram[1]:21 5.136741e-05 +22 mux_tree_tapbuf_size4_3_sram[1]:16 chany_top_in[15]:14 9.035799e-05 +23 mux_tree_tapbuf_size4_3_sram[1]:18 chany_top_in[15]:14 0.0003040651 +24 mux_tree_tapbuf_size4_3_sram[1]:11 chany_top_in[15]:13 9.035799e-05 +25 mux_tree_tapbuf_size4_3_sram[1]:17 chany_top_in[15]:13 0.0003040651 +26 mux_tree_tapbuf_size4_3_sram[1]:18 chany_bottom_in[13]:31 0.0003651321 +27 mux_tree_tapbuf_size4_3_sram[1]:17 chany_bottom_in[13]:30 0.0003651321 +28 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 5.43252e-05 +29 mux_tree_tapbuf_size4_3_sram[1]:17 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 5.43252e-05 +30 mux_tree_tapbuf_size4_3_sram[1]:15 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002021337 +31 mux_tree_tapbuf_size4_3_sram[1]:16 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.382127e-05 +32 mux_tree_tapbuf_size4_3_sram[1]:14 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002021337 +33 mux_tree_tapbuf_size4_3_sram[1]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.2613e-08 +34 mux_tree_tapbuf_size4_3_sram[1]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.2613e-08 +35 mux_tree_tapbuf_size4_3_sram[1]:17 mux_left_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.382127e-05 + +*RES +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_3_sram[1]:21 0.152 +1 mux_tree_tapbuf_size4_3_sram[1]:15 mux_tree_tapbuf_size4_3_sram[1]:14 0.006587054 +2 mux_tree_tapbuf_size4_3_sram[1]:16 mux_tree_tapbuf_size4_3_sram[1]:15 0.00341 +3 mux_tree_tapbuf_size4_3_sram[1]:16 mux_tree_tapbuf_size4_3_sram[1]:11 0.000647425 +4 mux_tree_tapbuf_size4_3_sram[1]:13 mux_tree_tapbuf_size4_3_sram[1]:12 0.0001752718 +5 mux_tree_tapbuf_size4_3_sram[1]:14 mux_tree_tapbuf_size4_3_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size4_3_sram[1]:12 mux_left_track_15\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size4_3_sram[1]:4 mux_left_track_15\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size4_3_sram[1]:5 mux_tree_tapbuf_size4_3_sram[1]:4 0.0004441965 +9 mux_tree_tapbuf_size4_3_sram[1]:6 mux_tree_tapbuf_size4_3_sram[1]:5 0.0045 +10 mux_tree_tapbuf_size4_3_sram[1]:19 mux_tree_tapbuf_size4_3_sram[1]:18 0.00341 +11 mux_tree_tapbuf_size4_3_sram[1]:19 mux_tree_tapbuf_size4_3_sram[1]:6 0.002995536 +12 mux_tree_tapbuf_size4_3_sram[1]:18 mux_tree_tapbuf_size4_3_sram[1]:17 0.005187625 +13 mux_tree_tapbuf_size4_3_sram[1]:10 mux_tree_tapbuf_size4_3_sram[1]:9 0.0001634615 +14 mux_tree_tapbuf_size4_3_sram[1]:11 mux_tree_tapbuf_size4_3_sram[1]:10 0.00341 +15 mux_tree_tapbuf_size4_3_sram[1]:8 mux_tree_tapbuf_size4_3_sram[1]:7 0.0001548913 +16 mux_tree_tapbuf_size4_3_sram[1]:9 mux_tree_tapbuf_size4_3_sram[1]:8 0.0045 +17 mux_tree_tapbuf_size4_3_sram[1]:7 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size4_3_sram[1]:20 mux_tree_tapbuf_size4_3_sram[1]:19 0.0045 +19 mux_tree_tapbuf_size4_3_sram[1]:21 mux_tree_tapbuf_size4_3_sram[1]:20 0.0001657609 +20 mux_tree_tapbuf_size4_3_sram[1]:17 mux_tree_tapbuf_size4_3_sram[1]:16 0.0001053583 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_2_ccff_tail[0] 0.001785754 //LENGTH 14.460 LUMPCC 0.0002559859 DR + +*CONN +*I mem_bottom_track_17\/FTB_10__42:X O *L 0 *C 63.715 39.100 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 55.835 33.660 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 *C 55.873 33.660 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 *C 63.895 33.660 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 *C 63.940 33.705 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 *C 63.940 39.055 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 *C 63.940 39.100 +*N mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 *C 63.715 39.100 + +*CAP +0 mem_bottom_track_17\/FTB_10__42:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.0004852388 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0004852388 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.0002257178 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0002257178 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 5.340266e-05 +7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 5.245278e-05 +8 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 chany_top_in[8]:11 7.62726e-05 +9 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 chany_top_in[8]:9 7.62726e-05 +10 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_1_sram[0]:21 3.918348e-05 +11 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size6_1_sram[0]:32 1.253686e-05 +12 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mux_tree_tapbuf_size6_1_sram[0]:30 3.918348e-05 +13 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mux_tree_tapbuf_size6_1_sram[0]:33 1.253686e-05 + +*RES +0 mem_bottom_track_17\/FTB_10__42:X mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 0.007162947 +5 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_2_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[3] 0.002136863 //LENGTH 17.427 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 75.745 102.340 +*I mux_top_track_8\/mux_l4_in_0_:S I *L 0.008363 *C 81.603 99.558 +*I mem_top_track_8\/FTB_4__36:A I *L 0.001746 *C 77.280 93.840 +*N mux_tree_tapbuf_size8_1_sram[3]:3 *C 77.303 93.868 +*N mux_tree_tapbuf_size8_1_sram[3]:4 *C 77.315 94.180 +*N mux_tree_tapbuf_size8_1_sram[3]:5 *C 79.075 94.180 +*N mux_tree_tapbuf_size8_1_sram[3]:6 *C 79.120 94.225 +*N mux_tree_tapbuf_size8_1_sram[3]:7 *C 79.165 99.620 +*N mux_tree_tapbuf_size8_1_sram[3]:8 *C 79.120 99.620 +*N mux_tree_tapbuf_size8_1_sram[3]:9 *C 79.120 102.295 +*N mux_tree_tapbuf_size8_1_sram[3]:10 *C 79.075 102.340 +*N mux_tree_tapbuf_size8_1_sram[3]:11 *C 75.782 102.340 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mux_top_track_8\/mux_l4_in_0_:S 0.0001579112 +2 mem_top_track_8\/FTB_4__36:A 1e-06 +3 mux_tree_tapbuf_size8_1_sram[3]:3 3.254223e-05 +4 mux_tree_tapbuf_size8_1_sram[3]:4 0.0001688791 +5 mux_tree_tapbuf_size8_1_sram[3]:5 0.0001363369 +6 mux_tree_tapbuf_size8_1_sram[3]:6 0.0003063898 +7 mux_tree_tapbuf_size8_1_sram[3]:7 0.0001579112 +8 mux_tree_tapbuf_size8_1_sram[3]:8 0.0004950395 +9 mux_tree_tapbuf_size8_1_sram[3]:9 0.0001609305 +10 mux_tree_tapbuf_size8_1_sram[3]:10 0.0002594615 +11 mux_tree_tapbuf_size8_1_sram[3]:11 0.0002594615 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size8_1_sram[3]:11 0.152 +1 mux_tree_tapbuf_size8_1_sram[3]:5 mux_tree_tapbuf_size8_1_sram[3]:4 0.001571429 +2 mux_tree_tapbuf_size8_1_sram[3]:6 mux_tree_tapbuf_size8_1_sram[3]:5 0.0045 +3 mux_tree_tapbuf_size8_1_sram[3]:3 mem_top_track_8\/FTB_4__36:A 0.152 +4 mux_tree_tapbuf_size8_1_sram[3]:7 mux_top_track_8\/mux_l4_in_0_:S 0.002176339 +5 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size8_1_sram[3]:8 mux_tree_tapbuf_size8_1_sram[3]:6 0.004816964 +7 mux_tree_tapbuf_size8_1_sram[3]:10 mux_tree_tapbuf_size8_1_sram[3]:9 0.0045 +8 mux_tree_tapbuf_size8_1_sram[3]:9 mux_tree_tapbuf_size8_1_sram[3]:8 0.002388393 +9 mux_tree_tapbuf_size8_1_sram[3]:11 mux_tree_tapbuf_size8_1_sram[3]:10 0.002939732 +10 mux_tree_tapbuf_size8_1_sram[3]:4 mux_tree_tapbuf_size8_1_sram[3]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[2] 0.002077148 //LENGTH 15.640 LUMPCC 0.0002007748 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 21.005 44.880 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 19.495 42.500 +*I mux_bottom_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 23.360 39.440 +*I mux_bottom_track_3\/mux_l3_in_1_:S I *L 0.00357 *C 26.120 44.880 +*N mux_tree_tapbuf_size9_0_sram[2]:4 *C 26.082 44.880 +*N mux_tree_tapbuf_size9_0_sram[2]:5 *C 23.323 39.440 +*N mux_tree_tapbuf_size9_0_sram[2]:6 *C 21.665 39.440 +*N mux_tree_tapbuf_size9_0_sram[2]:7 *C 21.620 39.485 +*N mux_tree_tapbuf_size9_0_sram[2]:8 *C 19.533 42.500 +*N mux_tree_tapbuf_size9_0_sram[2]:9 *C 21.575 42.500 +*N mux_tree_tapbuf_size9_0_sram[2]:10 *C 21.620 42.500 +*N mux_tree_tapbuf_size9_0_sram[2]:11 *C 21.620 44.835 +*N mux_tree_tapbuf_size9_0_sram[2]:12 *C 21.620 44.880 +*N mux_tree_tapbuf_size9_0_sram[2]:13 *C 21.043 44.880 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +2 mux_bottom_track_3\/mux_l3_in_0_:S 1e-06 +3 mux_bottom_track_3\/mux_l3_in_1_:S 1e-06 +4 mux_tree_tapbuf_size9_0_sram[2]:4 0.0002475017 +5 mux_tree_tapbuf_size9_0_sram[2]:5 0.0001431233 +6 mux_tree_tapbuf_size9_0_sram[2]:6 0.0001431233 +7 mux_tree_tapbuf_size9_0_sram[2]:7 0.0001699088 +8 mux_tree_tapbuf_size9_0_sram[2]:8 0.0001595313 +9 mux_tree_tapbuf_size9_0_sram[2]:9 0.0001595313 +10 mux_tree_tapbuf_size9_0_sram[2]:10 0.0003389469 +11 mux_tree_tapbuf_size9_0_sram[2]:11 0.0001360512 +12 mux_tree_tapbuf_size9_0_sram[2]:12 0.0003288273 +13 mux_tree_tapbuf_size9_0_sram[2]:13 4.582855e-05 +14 mux_tree_tapbuf_size9_0_sram[2]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001003874 +15 mux_tree_tapbuf_size9_0_sram[2]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001003874 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size9_0_sram[2]:13 0.152 +1 mux_tree_tapbuf_size9_0_sram[2]:4 mux_bottom_track_3\/mux_l3_in_1_:S 0.152 +2 mux_tree_tapbuf_size9_0_sram[2]:12 mux_tree_tapbuf_size9_0_sram[2]:11 0.0045 +3 mux_tree_tapbuf_size9_0_sram[2]:12 mux_tree_tapbuf_size9_0_sram[2]:4 0.003984375 +4 mux_tree_tapbuf_size9_0_sram[2]:11 mux_tree_tapbuf_size9_0_sram[2]:10 0.002084822 +5 mux_tree_tapbuf_size9_0_sram[2]:9 mux_tree_tapbuf_size9_0_sram[2]:8 0.001823661 +6 mux_tree_tapbuf_size9_0_sram[2]:10 mux_tree_tapbuf_size9_0_sram[2]:9 0.0045 +7 mux_tree_tapbuf_size9_0_sram[2]:10 mux_tree_tapbuf_size9_0_sram[2]:7 0.002691964 +8 mux_tree_tapbuf_size9_0_sram[2]:8 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +9 mux_tree_tapbuf_size9_0_sram[2]:13 mux_tree_tapbuf_size9_0_sram[2]:12 0.000515625 +10 mux_tree_tapbuf_size9_0_sram[2]:6 mux_tree_tapbuf_size9_0_sram[2]:5 0.001479911 +11 mux_tree_tapbuf_size9_0_sram[2]:7 mux_tree_tapbuf_size9_0_sram[2]:6 0.0045 +12 mux_tree_tapbuf_size9_0_sram[2]:5 mux_bottom_track_3\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007264212 //LENGTH 5.160 LUMPCC 0.0002035545 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 55.835 23.460 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 50.965 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.003 23.460 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 55.797 23.460 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002604333 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002604333 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:20 4.548436e-05 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size10_1_sram[1]:27 5.629291e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:21 4.548436e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size10_1_sram[1]:28 5.629291e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.00428125 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0] 0.005877861 //LENGTH 44.970 LUMPCC 0.0002696278 DR + +*CONN +*I mux_bottom_track_1\/mux_l4_in_0_:X O *L 0 *C 45.365 22.440 +*I mux_bottom_track_1\/BUFT_RR_60:A I *L 0.001746 *C 74.980 12.240 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 *C 74.980 12.240 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 *C 74.980 12.195 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 *C 74.980 10.245 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 *C 74.935 10.200 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 *C 45.585 10.200 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 *C 45.540 10.245 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 *C 45.540 22.395 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 *C 45.540 22.440 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 *C 45.365 22.440 + +*CAP +0 mux_bottom_track_1\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_1\/BUFT_RR_60:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 3.188175e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001362483 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001362483 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.00190245 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.00190245 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.0006984008 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0006984008 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 5.206801e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 4.808485e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 8.726015e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 8.726015e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 ropt_net_158:3 4.755373e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 ropt_net_158:2 4.755373e-05 + +*RES +0 mux_bottom_track_1\/mux_l4_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 9.510871e-05 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 0.01084821 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 0.02620536 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0045 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.001741072 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 mux_bottom_track_1\/BUFT_RR_60:A 0.152 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008305393 //LENGTH 5.885 LUMPCC 0.0001910505 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 70.095 15.640 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 68.640 18.020 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 68.603 18.020 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 68.125 18.020 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 68.080 17.975 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 68.080 15.685 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 68.125 15.640 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 70.058 15.640 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.329873e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.329873e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001467261 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001467261 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001087195 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001087195 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[16]:10 1.200997e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[16]:8 8.351527e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[16]:9 1.200997e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[16]:7 8.351527e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002044643 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001725447 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001483569 //LENGTH 13.180 LUMPCC 0 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_0_:X O *L 0 *C 51.805 106.760 +*I mux_top_track_16\/mux_l2_in_0_:A1 I *L 0.00198 *C 53.725 96.220 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 53.725 96.220 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 53.820 96.265 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 53.820 106.715 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 53.775 106.760 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 51.843 106.760 + +*CAP +0 mux_top_track_16\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.983305e-05 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0005675377 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005675377 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001583303 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001583303 + +*RES +0 mux_top_track_16\/mux_l1_in_0_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.009330357 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001725447 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.001056475 //LENGTH 6.270 LUMPCC 0.0004878192 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_2_:X O *L 0 *C 17.655 85.340 +*I mux_left_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 14.165 83.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 14.203 83.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.435 83.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.480 83.345 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.480 85.295 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 17.480 85.340 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 17.655 85.340 + +*CAP +0 mux_left_track_3\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001595743 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001595743 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.951681e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.951681e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 6.246063e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.601277e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_3_sram[0]:27 5.860667e-05 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_3_sram[0]:26 5.860667e-05 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 5.792631e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 5.792631e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001273766 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001273766 + +*RES +0 mux_left_track_3\/mux_l1_in_2_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_3\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002886161 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741071 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.005922867 //LENGTH 46.195 LUMPCC 0.0003345683 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_2_:X O *L 0 *C 38.925 33.320 +*I mux_bottom_track_25\/mux_l2_in_1_:A1 I *L 0.00198 *C 70.840 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 70.803 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 69.460 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 69.460 21.080 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 39.145 21.080 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 39.100 21.125 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 39.100 33.275 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 39.100 33.320 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 38.925 33.320 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001072153 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001754686 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002088006 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.002019753 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005436183 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0005436183 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 5.65327e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.208725e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 optlc_net_137:22 0.0001223736 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 optlc_net_137:19 0.0001223736 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:5 4.491052e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_10_X[0]:4 4.491052e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_2_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 9.51087e-05 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01084821 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.02706697 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_25\/mux_l2_in_1_:A1 0.152 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0009107143 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001198661 + +*END + +*D_NET mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001422648 //LENGTH 11.500 LUMPCC 0.0003857164 DR + +*CONN +*I mux_left_track_15\/mux_l1_in_0_:X O *L 0 *C 53.075 52.700 +*I mux_left_track_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 45.905 56.100 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 45.943 56.100 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 50.095 56.100 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 50.140 56.055 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 50.140 52.745 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 50.185 52.700 +*N mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 53.038 52.700 + +*CAP +0 mux_left_track_15\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_15\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001979854 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001979854 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001909659 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001909659 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001285146 +7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001285146 +8 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[19]:2 6.294826e-06 +9 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[19]:4 0.0001274107 +10 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[19]:3 6.294826e-06 +11 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[19]:5 0.0001274107 +12 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size4_3_sram[0]:5 5.915269e-05 +13 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size4_3_sram[0]:3 5.915269e-05 + +*RES +0 mux_left_track_15\/mux_l1_in_0_:X mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_15\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.003707589 +3 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002955357 +6 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002546875 + +*END + +*D_NET ropt_net_161 0.001331386 //LENGTH 11.300 LUMPCC 0.0001200921 DR + +*CONN +*I FTB_11__10:X O *L 0 *C 7.820 40.120 +*I ropt_mt_inst_786:A I *L 0.001766 *C 3.220 36.720 +*N ropt_net_161:2 *C 3.183 36.720 +*N ropt_net_161:3 *C 2.345 36.720 +*N ropt_net_161:4 *C 2.300 36.720 +*N ropt_net_161:5 *C 2.300 39.735 +*N ropt_net_161:6 *C 2.345 39.780 +*N ropt_net_161:7 *C 6.440 39.780 +*N ropt_net_161:8 *C 6.440 40.120 +*N ropt_net_161:9 *C 7.783 40.120 + +*CAP +0 FTB_11__10:X 1e-06 +1 ropt_mt_inst_786:A 1e-06 +2 ropt_net_161:2 6.299914e-05 +3 ropt_net_161:3 6.299914e-05 +4 ropt_net_161:4 0.000191754 +5 ropt_net_161:5 0.000162651 +6 ropt_net_161:6 0.0002300615 +7 ropt_net_161:7 0.0002543259 +8 ropt_net_161:8 0.0001343836 +9 ropt_net_161:9 0.0001101193 +10 ropt_net_161:9 chanx_left_out[15]:6 2.964517e-06 +11 ropt_net_161:6 chanx_left_out[15]:5 3.949875e-05 +12 ropt_net_161:5 chanx_left_out[15]:3 1.758279e-05 +13 ropt_net_161:4 chanx_left_out[15]:4 1.758279e-05 +14 ropt_net_161:7 chanx_left_out[15]:6 3.949875e-05 +15 ropt_net_161:8 chanx_left_out[15]:5 2.964517e-06 + +*RES +0 FTB_11__10:X ropt_net_161:9 0.152 +1 ropt_net_161:9 ropt_net_161:8 0.001198661 +2 ropt_net_161:6 ropt_net_161:5 0.0045 +3 ropt_net_161:5 ropt_net_161:4 0.002691964 +4 ropt_net_161:3 ropt_net_161:2 0.0007477679 +5 ropt_net_161:4 ropt_net_161:3 0.0045 +6 ropt_net_161:2 ropt_mt_inst_786:A 0.152 +7 ropt_net_161:7 ropt_net_161:6 0.00365625 +8 ropt_net_161:8 ropt_net_161:7 0.0003035715 + +*END + +*D_NET mux_bottom_track_1/BUF_net_60 0.002099044 //LENGTH 15.045 LUMPCC 0.0004420584 DR + +*CONN +*I mux_bottom_track_1\/BUFT_RR_60:X O *L 0 *C 77.965 11.900 +*I mux_bottom_track_1\/BUFT_P_113:A I *L 0.001767 *C 86.480 6.800 +*N mux_bottom_track_1/BUF_net_60:2 *C 86.443 6.800 +*N mux_bottom_track_1/BUF_net_60:3 *C 84.640 6.800 +*N mux_bottom_track_1/BUF_net_60:4 *C 84.640 7.140 +*N mux_bottom_track_1/BUF_net_60:5 *C 84.640 7.185 +*N mux_bottom_track_1/BUF_net_60:6 *C 84.640 9.815 +*N mux_bottom_track_1/BUF_net_60:7 *C 84.595 9.860 +*N mux_bottom_track_1/BUF_net_60:8 *C 78.245 9.860 +*N mux_bottom_track_1/BUF_net_60:9 *C 78.200 9.905 +*N mux_bottom_track_1/BUF_net_60:10 *C 78.200 11.855 +*N mux_bottom_track_1/BUF_net_60:11 *C 78.200 11.900 +*N mux_bottom_track_1/BUF_net_60:12 *C 77.965 11.900 + +*CAP +0 mux_bottom_track_1\/BUFT_RR_60:X 1e-06 +1 mux_bottom_track_1\/BUFT_P_113:A 1e-06 +2 mux_bottom_track_1/BUF_net_60:2 0.0001312636 +3 mux_bottom_track_1/BUF_net_60:3 0.0001610341 +4 mux_bottom_track_1/BUF_net_60:4 6.490519e-05 +5 mux_bottom_track_1/BUF_net_60:5 0.0001751685 +6 mux_bottom_track_1/BUF_net_60:6 0.0001751685 +7 mux_bottom_track_1/BUF_net_60:7 0.0003231158 +8 mux_bottom_track_1/BUF_net_60:8 0.0003231158 +9 mux_bottom_track_1/BUF_net_60:9 8.508535e-05 +10 mux_bottom_track_1/BUF_net_60:10 8.508535e-05 +11 mux_bottom_track_1/BUF_net_60:11 6.46034e-05 +12 mux_bottom_track_1/BUF_net_60:12 6.643982e-05 +13 mux_bottom_track_1/BUF_net_60:9 chany_bottom_in[19] 6.346672e-05 +14 mux_bottom_track_1/BUF_net_60:10 chany_bottom_in[19]:13 6.346672e-05 +15 mux_bottom_track_1/BUF_net_60:5 chany_bottom_out[12]:7 8.850057e-06 +16 mux_bottom_track_1/BUF_net_60:7 chany_bottom_out[12]:4 1.197384e-05 +17 mux_bottom_track_1/BUF_net_60:7 chany_bottom_out[12]:6 5.97878e-05 +18 mux_bottom_track_1/BUF_net_60:6 chany_bottom_out[12]:8 8.850057e-06 +19 mux_bottom_track_1/BUF_net_60:8 chany_bottom_out[12]:3 1.197384e-05 +20 mux_bottom_track_1/BUF_net_60:8 chany_bottom_out[12]:5 5.97878e-05 +21 mux_bottom_track_1/BUF_net_60:7 ropt_net_154:2 7.695079e-05 +22 mux_bottom_track_1/BUF_net_60:8 ropt_net_154:3 7.695079e-05 + +*RES +0 mux_bottom_track_1\/BUFT_RR_60:X mux_bottom_track_1/BUF_net_60:12 0.152 +1 mux_bottom_track_1/BUF_net_60:2 mux_bottom_track_1\/BUFT_P_113:A 0.152 +2 mux_bottom_track_1/BUF_net_60:4 mux_bottom_track_1/BUF_net_60:3 0.0003035715 +3 mux_bottom_track_1/BUF_net_60:5 mux_bottom_track_1/BUF_net_60:4 0.0045 +4 mux_bottom_track_1/BUF_net_60:7 mux_bottom_track_1/BUF_net_60:6 0.0045 +5 mux_bottom_track_1/BUF_net_60:6 mux_bottom_track_1/BUF_net_60:5 0.002348214 +6 mux_bottom_track_1/BUF_net_60:8 mux_bottom_track_1/BUF_net_60:7 0.005669643 +7 mux_bottom_track_1/BUF_net_60:9 mux_bottom_track_1/BUF_net_60:8 0.0045 +8 mux_bottom_track_1/BUF_net_60:11 mux_bottom_track_1/BUF_net_60:10 0.0045 +9 mux_bottom_track_1/BUF_net_60:10 mux_bottom_track_1/BUF_net_60:9 0.001741072 +10 mux_bottom_track_1/BUF_net_60:12 mux_bottom_track_1/BUF_net_60:11 0.0001277174 +11 mux_bottom_track_1/BUF_net_60:3 mux_bottom_track_1/BUF_net_60:2 0.001609375 + +*END + +*D_NET chany_top_out[15] 0.0006449919 //LENGTH 4.415 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_826:X O *L 0 *C 52.900 127.160 +*P chany_top_out[15] O *L 0.7423 *C 51.060 129.270 +*N chany_top_out[15]:2 *C 51.060 127.205 +*N chany_top_out[15]:3 *C 51.105 127.160 +*N chany_top_out[15]:4 *C 52.863 127.160 + +*CAP +0 ropt_mt_inst_826:X 1e-06 +1 chany_top_out[15] 0.0001435582 +2 chany_top_out[15]:2 0.0001435582 +3 chany_top_out[15]:3 0.0001784377 +4 chany_top_out[15]:4 0.0001784377 + +*RES +0 ropt_mt_inst_826:X chany_top_out[15]:4 0.152 +1 chany_top_out[15]:3 chany_top_out[15]:2 0.0045 +2 chany_top_out[15]:2 chany_top_out[15] 0.00184375 +3 chany_top_out[15]:4 chany_top_out[15]:3 0.001569197 + +*END + +*D_NET chany_top_in[13] 0.02944211 //LENGTH 223.465 LUMPCC 0.009856466 DR + +*CONN +*P chany_top_in[13] I *L 0.29796 *C 63.480 129.235 +*I ropt_mt_inst_776:A I *L 0.001767 *C 98.440 6.800 +*I mux_left_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 29.805 52.700 +*I mux_bottom_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 32.030 33.660 +*N chany_top_in[13]:4 *C 32.068 33.660 +*N chany_top_in[13]:5 *C 32.615 33.660 +*N chany_top_in[13]:6 *C 32.660 33.705 +*N chany_top_in[13]:7 *C 29.843 52.700 +*N chany_top_in[13]:8 *C 32.155 52.700 +*N chany_top_in[13]:9 *C 32.200 52.655 +*N chany_top_in[13]:10 *C 32.200 37.400 +*N chany_top_in[13]:11 *C 32.660 37.343 +*N chany_top_in[13]:12 *C 32.668 37.400 +*N chany_top_in[13]:13 *C 98.403 6.800 +*N chany_top_in[13]:14 *C 94.805 6.800 +*N chany_top_in[13]:15 *C 94.760 6.845 +*N chany_top_in[13]:16 *C 94.760 9.475 +*N chany_top_in[13]:17 *C 94.715 9.520 +*N chany_top_in[13]:18 *C 89.285 9.520 +*N chany_top_in[13]:19 *C 89.240 9.565 +*N chany_top_in[13]:20 *C 89.240 20.355 +*N chany_top_in[13]:21 *C 89.195 20.400 +*N chany_top_in[13]:22 *C 80.545 20.400 +*N chany_top_in[13]:23 *C 80.500 20.400 +*N chany_top_in[13]:24 *C 80.493 20.400 +*N chany_top_in[13]:25 *C 55.668 20.400 +*N chany_top_in[13]:26 *C 55.660 20.457 +*N chany_top_in[13]:27 *C 55.660 37.343 +*N chany_top_in[13]:28 *C 55.660 37.400 +*N chany_top_in[13]:29 *C 62.540 37.400 +*N chany_top_in[13]:30 *C 62.560 37.407 +*N chany_top_in[13]:31 *C 62.560 87.235 +*N chany_top_in[13]:32 *C 62.560 123.073 +*N chany_top_in[13]:33 *C 62.580 123.080 +*N chany_top_in[13]:34 *C 63.473 123.080 +*N chany_top_in[13]:35 *C 63.480 123.138 + +*CAP +0 chany_top_in[13] 0.0003008574 +1 ropt_mt_inst_776:A 1e-06 +2 mux_left_track_17\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_track_3\/mux_l1_in_0_:A0 1e-06 +4 chany_top_in[13]:4 5.699087e-05 +5 chany_top_in[13]:5 5.699087e-05 +6 chany_top_in[13]:6 0.0002547866 +7 chany_top_in[13]:7 0.0001672151 +8 chany_top_in[13]:8 0.0001672151 +9 chany_top_in[13]:9 0.0009097646 +10 chany_top_in[13]:10 0.0009476561 +11 chany_top_in[13]:11 0.0002926782 +12 chany_top_in[13]:12 0.001256207 +13 chany_top_in[13]:13 0.0002169797 +14 chany_top_in[13]:14 0.0002169797 +15 chany_top_in[13]:15 0.0001479104 +16 chany_top_in[13]:16 0.0001479104 +17 chany_top_in[13]:17 0.0002871877 +18 chany_top_in[13]:18 0.0002871877 +19 chany_top_in[13]:19 0.0005978078 +20 chany_top_in[13]:20 0.0005978078 +21 chany_top_in[13]:21 0.0004779848 +22 chany_top_in[13]:22 0.0004779848 +23 chany_top_in[13]:23 3.608214e-05 +24 chany_top_in[13]:24 0.001382479 +25 chany_top_in[13]:25 0.001382479 +26 chany_top_in[13]:26 0.0008591388 +27 chany_top_in[13]:27 0.0008591388 +28 chany_top_in[13]:28 0.0016799 +29 chany_top_in[13]:29 0.0004236927 +30 chany_top_in[13]:30 0.001188902 +31 chany_top_in[13]:31 0.002307974 +32 chany_top_in[13]:32 0.001119072 +33 chany_top_in[13]:33 8.841326e-05 +34 chany_top_in[13]:34 8.841326e-05 +35 chany_top_in[13]:35 0.0003008574 +36 chany_top_in[13]:25 chany_top_in[2]:9 0.00057283 +37 chany_top_in[13]:24 chany_top_in[2]:8 0.00057283 +38 chany_top_in[13]:30 chany_top_in[10]:24 0.000220802 +39 chany_top_in[13]:32 chany_top_in[10]:25 0.000110443 +40 chany_top_in[13]:32 chany_top_in[10]:26 0.0003396717 +41 chany_top_in[13]:27 chany_top_in[10]:20 0.0001501015 +42 chany_top_in[13]:26 chany_top_in[10]:17 0.0001501015 +43 chany_top_in[13]:31 chany_top_in[10]:24 0.000110443 +44 chany_top_in[13]:31 chany_top_in[10]:25 0.0005604737 +45 chany_top_in[13]:30 chany_top_in[12]:20 6.194555e-05 +46 chany_top_in[13]:32 chany_top_in[12]:21 1.72944e-05 +47 chany_top_in[13]:32 chany_top_in[12]:22 0.0001635661 +48 chany_top_in[13]:25 chany_top_in[12]:11 1.569803e-05 +49 chany_top_in[13]:24 chany_top_in[12]:12 1.569803e-05 +50 chany_top_in[13]:31 chany_top_in[12]:20 1.72944e-05 +51 chany_top_in[13]:31 chany_top_in[12]:21 0.0002255116 +52 chany_top_in[13]:30 chany_bottom_in[5]:20 0.0003681625 +53 chany_top_in[13]:30 chany_bottom_in[5]:25 0.0009581621 +54 chany_top_in[13]:30 chany_bottom_in[5]:24 0.0004814982 +55 chany_top_in[13]:32 chany_bottom_in[5]:19 0.0003283294 +56 chany_top_in[13]:31 chany_bottom_in[5]:20 0.0003283294 +57 chany_top_in[13]:31 chany_bottom_in[5]:19 0.0003681625 +58 chany_top_in[13]:31 chany_bottom_in[5]:23 0.0004814982 +59 chany_top_in[13]:31 chany_bottom_in[5]:24 0.0009581621 +60 chany_top_in[13]:30 chany_bottom_in[14]:33 0.0003334781 +61 chany_top_in[13]:30 chany_bottom_in[14]:32 0.0001516627 +62 chany_top_in[13]:31 chany_bottom_in[14]:31 0.0001516627 +63 chany_top_in[13]:31 chany_bottom_in[14]:32 0.0003334781 +64 chany_top_in[13]:29 chanx_left_in[11]:19 0.000127723 +65 chany_top_in[13]:28 chanx_left_in[11]:19 0.000463892 +66 chany_top_in[13]:28 chanx_left_in[11]:20 0.000127723 +67 chany_top_in[13]:12 chanx_left_in[11]:20 0.000463892 +68 chany_top_in[13] ropt_net_187:4 6.29719e-05 +69 chany_top_in[13]:35 ropt_net_187:5 6.29719e-05 + +*RES +0 chany_top_in[13] chany_top_in[13]:35 0.005444197 +1 chany_top_in[13]:29 chany_top_in[13]:28 0.001077867 +2 chany_top_in[13]:30 chany_top_in[13]:29 0.00341 +3 chany_top_in[13]:33 chany_top_in[13]:32 0.00341 +4 chany_top_in[13]:32 chany_top_in[13]:31 0.005614541 +5 chany_top_in[13]:35 chany_top_in[13]:34 0.00341 +6 chany_top_in[13]:34 chany_top_in[13]:33 0.000139825 +7 chany_top_in[13]:5 chany_top_in[13]:4 0.0004888393 +8 chany_top_in[13]:6 chany_top_in[13]:5 0.0045 +9 chany_top_in[13]:4 mux_bottom_track_3\/mux_l1_in_0_:A0 0.152 +10 chany_top_in[13]:8 chany_top_in[13]:7 0.002064732 +11 chany_top_in[13]:9 chany_top_in[13]:8 0.0045 +12 chany_top_in[13]:7 mux_left_track_17\/mux_l1_in_0_:A1 0.152 +13 chany_top_in[13]:27 chany_top_in[13]:26 0.01507589 +14 chany_top_in[13]:28 chany_top_in[13]:27 0.00341 +15 chany_top_in[13]:28 chany_top_in[13]:12 0.003602158 +16 chany_top_in[13]:26 chany_top_in[13]:25 0.00341 +17 chany_top_in[13]:25 chany_top_in[13]:24 0.00388925 +18 chany_top_in[13]:23 chany_top_in[13]:22 0.0045 +19 chany_top_in[13]:24 chany_top_in[13]:23 0.00341 +20 chany_top_in[13]:22 chany_top_in[13]:21 0.007723215 +21 chany_top_in[13]:21 chany_top_in[13]:20 0.0045 +22 chany_top_in[13]:20 chany_top_in[13]:19 0.009633929 +23 chany_top_in[13]:18 chany_top_in[13]:17 0.004848215 +24 chany_top_in[13]:19 chany_top_in[13]:18 0.0045 +25 chany_top_in[13]:17 chany_top_in[13]:16 0.0045 +26 chany_top_in[13]:16 chany_top_in[13]:15 0.002348214 +27 chany_top_in[13]:14 chany_top_in[13]:13 0.003212054 +28 chany_top_in[13]:15 chany_top_in[13]:14 0.0045 +29 chany_top_in[13]:13 ropt_mt_inst_776:A 0.152 +30 chany_top_in[13]:11 chany_top_in[13]:10 0.0004107143 +31 chany_top_in[13]:11 chany_top_in[13]:6 0.003247768 +32 chany_top_in[13]:12 chany_top_in[13]:11 0.00341 +33 chany_top_in[13]:10 chany_top_in[13]:9 0.01362054 +34 chany_top_in[13]:31 chany_top_in[13]:30 0.007806308 + +*END + +*D_NET chanx_left_in[4] 0.01673025 //LENGTH 118.550 LUMPCC 0.005335032 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.305 85.680 +*I mux_top_track_8\/mux_l2_in_2_:A1 I *L 0.00198 *C 72.320 85.340 +*I mux_bottom_track_9\/mux_l2_in_2_:A1 I *L 0.00198 *C 68.540 39.780 +*N chanx_left_in[4]:3 *C 68.540 39.795 +*N chanx_left_in[4]:4 *C 68.540 40.120 +*N chanx_left_in[4]:5 *C 68.540 40.165 +*N chanx_left_in[4]:6 *C 72.282 85.340 +*N chanx_left_in[4]:7 *C 68.585 85.340 +*N chanx_left_in[4]:8 *C 68.540 85.340 +*N chanx_left_in[4]:9 *C 68.540 84.943 +*N chanx_left_in[4]:10 *C 68.532 85.000 +*N chanx_left_in[4]:11 *C 51.230 85.000 +*N chanx_left_in[4]:12 *C 1.380 85.000 + +*CAP +0 chanx_left_in[4] 5.382166e-05 +1 mux_top_track_8\/mux_l2_in_2_:A1 1e-06 +2 mux_bottom_track_9\/mux_l2_in_2_:A1 1e-06 +3 chanx_left_in[4]:3 3.490889e-05 +4 chanx_left_in[4]:4 6.692299e-05 +5 chanx_left_in[4]:5 0.00170103 +6 chanx_left_in[4]:6 0.000231043 +7 chanx_left_in[4]:7 0.000231043 +8 chanx_left_in[4]:8 5.273167e-05 +9 chanx_left_in[4]:9 0.001723796 +10 chanx_left_in[4]:10 0.001045844 +11 chanx_left_in[4]:11 0.003622051 +12 chanx_left_in[4]:12 0.002630028 +13 chanx_left_in[4]:9 chany_top_in[6]:15 0.0003504826 +14 chanx_left_in[4]:9 chany_top_in[6]:16 0.0006203312 +15 chanx_left_in[4]:5 chany_top_in[6]:11 0.0003504826 +16 chanx_left_in[4]:5 chany_top_in[6]:15 0.0006203312 +17 chanx_left_in[4]:10 prog_clk[0]:408 1.880431e-06 +18 chanx_left_in[4]:10 prog_clk[0]:449 4.002986e-05 +19 chanx_left_in[4]:12 prog_clk[0]:283 0.0003159983 +20 chanx_left_in[4]:12 prog_clk[0]:344 0.0002088549 +21 chanx_left_in[4]:12 prog_clk[0]:363 5.161669e-06 +22 chanx_left_in[4]:12 prog_clk[0]:464 6.159302e-08 +23 chanx_left_in[4]:12 prog_clk[0]:465 3.947086e-06 +24 chanx_left_in[4]:11 prog_clk[0]:282 0.0003159983 +25 chanx_left_in[4]:11 prog_clk[0]:343 0.0002088549 +26 chanx_left_in[4]:11 prog_clk[0]:362 5.161669e-06 +27 chanx_left_in[4]:11 prog_clk[0]:412 1.880431e-06 +28 chanx_left_in[4]:11 prog_clk[0]:450 4.002986e-05 +29 chanx_left_in[4]:11 prog_clk[0]:456 6.159302e-08 +30 chanx_left_in[4]:11 prog_clk[0]:464 3.947086e-06 +31 chanx_left_in[4]:12 chanx_left_in[7]:14 0.0003362191 +32 chanx_left_in[4]:11 chanx_left_in[7]:13 0.0003362191 +33 chanx_left_in[4]:9 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0001057253 +34 chanx_left_in[4]:5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.0001057253 +35 chanx_left_in[4]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001537177 +36 chanx_left_in[4]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001537177 +37 chanx_left_in[4]:9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001265148 +38 chanx_left_in[4]:10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001242133 +39 chanx_left_in[4]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001265148 +40 chanx_left_in[4]:12 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.516408e-05 +41 chanx_left_in[4]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.516408e-05 +42 chanx_left_in[4]:11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001242133 +43 chanx_left_in[4]:12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002492139 +44 chanx_left_in[4]:11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002492139 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:12 0.0001065333 +1 chanx_left_in[4]:9 chanx_left_in[4]:8 0.0001057692 +2 chanx_left_in[4]:9 chanx_left_in[4]:5 0.03997992 +3 chanx_left_in[4]:10 chanx_left_in[4]:9 0.00341 +4 chanx_left_in[4]:7 chanx_left_in[4]:6 0.003301339 +5 chanx_left_in[4]:8 chanx_left_in[4]:7 0.0045 +6 chanx_left_in[4]:6 mux_top_track_8\/mux_l2_in_2_:A1 0.152 +7 chanx_left_in[4]:4 chanx_left_in[4]:3 0.0001766305 +8 chanx_left_in[4]:5 chanx_left_in[4]:4 0.0045 +9 chanx_left_in[4]:3 mux_bottom_track_9\/mux_l2_in_2_:A1 0.152 +10 chanx_left_in[4]:12 chanx_left_in[4]:11 0.007809833 +11 chanx_left_in[4]:11 chanx_left_in[4]:10 0.002710725 + +*END + +*D_NET chanx_left_in[16] 0.01002434 //LENGTH 74.900 LUMPCC 0.00186027 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.298 51.680 +*I mux_bottom_track_3\/mux_l2_in_3_:A1 I *L 0.00198 *C 24.020 47.260 +*I mux_top_track_24\/mux_l1_in_3_:A1 I *L 0.00198 *C 31.380 74.460 +*N chanx_left_in[16]:3 *C 31.280 74.460 +*N chanx_left_in[16]:4 *C 31.280 74.415 +*N chanx_left_in[16]:5 *C 31.280 70.778 +*N chanx_left_in[16]:6 *C 31.273 70.720 +*N chanx_left_in[16]:7 *C 26.700 70.720 +*N chanx_left_in[16]:8 *C 26.680 70.713 +*N chanx_left_in[16]:9 *C 26.680 47.608 +*N chanx_left_in[16]:10 *C 26.660 47.600 +*N chanx_left_in[16]:11 *C 23.983 47.260 +*N chanx_left_in[16]:12 *C 20.240 47.260 +*N chanx_left_in[16]:13 *C 20.240 47.600 +*N chanx_left_in[16]:14 *C 20.240 47.600 +*N chanx_left_in[16]:15 *C 20.240 47.600 +*N chanx_left_in[16]:16 *C 15.648 47.600 +*N chanx_left_in[16]:17 *C 15.640 47.657 +*N chanx_left_in[16]:18 *C 15.640 55.035 +*N chanx_left_in[16]:19 *C 15.595 55.080 +*N chanx_left_in[16]:20 *C 1.425 55.080 +*N chanx_left_in[16]:21 *C 1.380 55.035 +*N chanx_left_in[16]:22 *C 1.380 51.738 +*N chanx_left_in[16]:23 *C 1.380 51.680 + +*CAP +0 chanx_left_in[16] 3.113653e-05 +1 mux_bottom_track_3\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_3_:A1 1e-06 +3 chanx_left_in[16]:3 3.455672e-05 +4 chanx_left_in[16]:4 0.0002310798 +5 chanx_left_in[16]:5 0.0002310798 +6 chanx_left_in[16]:6 0.0001169662 +7 chanx_left_in[16]:7 0.0001169662 +8 chanx_left_in[16]:8 0.001071452 +9 chanx_left_in[16]:9 0.001071452 +10 chanx_left_in[16]:10 0.0004189771 +11 chanx_left_in[16]:11 0.0002839747 +12 chanx_left_in[16]:12 0.0003110496 +13 chanx_left_in[16]:13 5.818895e-05 +14 chanx_left_in[16]:14 3.786665e-05 +15 chanx_left_in[16]:15 0.000718666 +16 chanx_left_in[16]:16 0.0002996889 +17 chanx_left_in[16]:17 0.0004106673 +18 chanx_left_in[16]:18 0.0004106673 +19 chanx_left_in[16]:19 0.0009487177 +20 chanx_left_in[16]:20 0.0009487177 +21 chanx_left_in[16]:21 0.0001895303 +22 chanx_left_in[16]:22 0.0001895303 +23 chanx_left_in[16]:23 3.113653e-05 +24 chanx_left_in[16]:9 chanx_left_in[13]:13 0.0004381649 +25 chanx_left_in[16]:8 chanx_left_in[13]:14 0.0004381649 +26 chanx_left_in[16]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000219875 +27 chanx_left_in[16]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000219875 +28 chanx_left_in[16]:7 mem_left_track_25/net_net_84:5 0.0002720952 +29 chanx_left_in[16]:6 mem_left_track_25/net_net_84:6 0.0002720952 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:23 2.35e-05 +1 chanx_left_in[16]:10 chanx_left_in[16]:9 0.00341 +2 chanx_left_in[16]:9 chanx_left_in[16]:8 0.003619783 +3 chanx_left_in[16]:7 chanx_left_in[16]:6 0.0007163582 +4 chanx_left_in[16]:8 chanx_left_in[16]:7 0.00341 +5 chanx_left_in[16]:5 chanx_left_in[16]:4 0.003247768 +6 chanx_left_in[16]:6 chanx_left_in[16]:5 0.00341 +7 chanx_left_in[16]:3 mux_top_track_24\/mux_l1_in_3_:A1 0.152 +8 chanx_left_in[16]:4 chanx_left_in[16]:3 0.0045 +9 chanx_left_in[16]:14 chanx_left_in[16]:13 0.0045 +10 chanx_left_in[16]:15 chanx_left_in[16]:14 0.00341 +11 chanx_left_in[16]:15 chanx_left_in[16]:10 0.0010058 +12 chanx_left_in[16]:13 chanx_left_in[16]:12 0.0003035715 +13 chanx_left_in[16]:11 mux_bottom_track_3\/mux_l2_in_3_:A1 0.152 +14 chanx_left_in[16]:17 chanx_left_in[16]:16 0.00341 +15 chanx_left_in[16]:16 chanx_left_in[16]:15 0.0007194916 +16 chanx_left_in[16]:19 chanx_left_in[16]:18 0.0045 +17 chanx_left_in[16]:18 chanx_left_in[16]:17 0.006587054 +18 chanx_left_in[16]:20 chanx_left_in[16]:19 0.01265179 +19 chanx_left_in[16]:21 chanx_left_in[16]:20 0.0045 +20 chanx_left_in[16]:22 chanx_left_in[16]:21 0.002944197 +21 chanx_left_in[16]:23 chanx_left_in[16]:22 0.00341 +22 chanx_left_in[16]:12 chanx_left_in[16]:11 0.003341518 + +*END + +*D_NET left_top_grid_pin_48_[0] 0.005593556 //LENGTH 43.555 LUMPCC 0.0002607071 DR + +*CONN +*P left_top_grid_pin_48_[0] I *L 0.29796 *C 11.500 102.035 +*I mux_left_track_1\/mux_l1_in_3_:A1 I *L 0.00198 *C 15.740 88.740 +*I mux_left_track_5\/mux_l1_in_3_:A1 I *L 0.00198 *C 20.145 77.860 +*I mux_left_track_21\/mux_l1_in_1_:A1 I *L 0.00198 *C 25.400 77.860 +*N left_top_grid_pin_48_[0]:4 *C 25.363 77.860 +*N left_top_grid_pin_48_[0]:5 *C 20.183 77.860 +*N left_top_grid_pin_48_[0]:6 *C 22.080 77.860 +*N left_top_grid_pin_48_[0]:7 *C 22.080 77.905 +*N left_top_grid_pin_48_[0]:8 *C 22.080 81.543 +*N left_top_grid_pin_48_[0]:9 *C 22.073 81.600 +*N left_top_grid_pin_48_[0]:10 *C 15.188 81.600 +*N left_top_grid_pin_48_[0]:11 *C 15.180 81.657 +*N left_top_grid_pin_48_[0]:12 *C 15.180 88.740 +*N left_top_grid_pin_48_[0]:13 *C 15.653 88.740 +*N left_top_grid_pin_48_[0]:14 *C 14.765 88.740 +*N left_top_grid_pin_48_[0]:15 *C 14.720 88.740 +*N left_top_grid_pin_48_[0]:16 *C 14.720 99.915 +*N left_top_grid_pin_48_[0]:17 *C 14.675 99.960 +*N left_top_grid_pin_48_[0]:18 *C 11.545 99.960 +*N left_top_grid_pin_48_[0]:19 *C 11.500 100.005 + +*CAP +0 left_top_grid_pin_48_[0] 0.0001189573 +1 mux_left_track_1\/mux_l1_in_3_:A1 1e-06 +2 mux_left_track_5\/mux_l1_in_3_:A1 1e-06 +3 mux_left_track_21\/mux_l1_in_1_:A1 1e-06 +4 left_top_grid_pin_48_[0]:4 0.0002190738 +5 left_top_grid_pin_48_[0]:5 0.0001477572 +6 left_top_grid_pin_48_[0]:6 0.0004032091 +7 left_top_grid_pin_48_[0]:7 0.0002429904 +8 left_top_grid_pin_48_[0]:8 0.0002429904 +9 left_top_grid_pin_48_[0]:9 0.0004224597 +10 left_top_grid_pin_48_[0]:10 0.0004224597 +11 left_top_grid_pin_48_[0]:11 0.0005018435 +12 left_top_grid_pin_48_[0]:12 0.0005335486 +13 left_top_grid_pin_48_[0]:13 8.353115e-05 +14 left_top_grid_pin_48_[0]:14 8.353115e-05 +15 left_top_grid_pin_48_[0]:15 0.0006778482 +16 left_top_grid_pin_48_[0]:16 0.000646143 +17 left_top_grid_pin_48_[0]:17 0.0002322744 +18 left_top_grid_pin_48_[0]:18 0.0002322744 +19 left_top_grid_pin_48_[0]:19 0.0001189573 +20 left_top_grid_pin_48_[0]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001303536 +21 left_top_grid_pin_48_[0]:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001303536 + +*RES +0 left_top_grid_pin_48_[0] left_top_grid_pin_48_[0]:19 0.0018125 +1 left_top_grid_pin_48_[0]:11 left_top_grid_pin_48_[0]:10 0.00341 +2 left_top_grid_pin_48_[0]:10 left_top_grid_pin_48_[0]:9 0.00107865 +3 left_top_grid_pin_48_[0]:8 left_top_grid_pin_48_[0]:7 0.003247768 +4 left_top_grid_pin_48_[0]:9 left_top_grid_pin_48_[0]:8 0.00341 +5 left_top_grid_pin_48_[0]:6 left_top_grid_pin_48_[0]:5 0.001694196 +6 left_top_grid_pin_48_[0]:6 left_top_grid_pin_48_[0]:4 0.002930804 +7 left_top_grid_pin_48_[0]:7 left_top_grid_pin_48_[0]:6 0.0045 +8 left_top_grid_pin_48_[0]:14 left_top_grid_pin_48_[0]:13 0.0007924107 +9 left_top_grid_pin_48_[0]:15 left_top_grid_pin_48_[0]:14 0.0045 +10 left_top_grid_pin_48_[0]:15 left_top_grid_pin_48_[0]:12 0.0004107143 +11 left_top_grid_pin_48_[0]:13 mux_left_track_1\/mux_l1_in_3_:A1 0.152 +12 left_top_grid_pin_48_[0]:18 left_top_grid_pin_48_[0]:17 0.002794643 +13 left_top_grid_pin_48_[0]:19 left_top_grid_pin_48_[0]:18 0.0045 +14 left_top_grid_pin_48_[0]:17 left_top_grid_pin_48_[0]:16 0.0045 +15 left_top_grid_pin_48_[0]:16 left_top_grid_pin_48_[0]:15 0.00997768 +16 left_top_grid_pin_48_[0]:4 mux_left_track_21\/mux_l1_in_1_:A1 0.152 +17 left_top_grid_pin_48_[0]:5 mux_left_track_5\/mux_l1_in_3_:A1 0.152 +18 left_top_grid_pin_48_[0]:12 left_top_grid_pin_48_[0]:11 0.006323662 + +*END + +*D_NET chany_top_out[16] 0.00131856 //LENGTH 12.455 LUMPCC 0 DR + +*CONN +*I mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 85.560 118.660 +*P chany_top_out[16] O *L 0.7423 *C 86.940 129.270 +*N chany_top_out[16]:2 *C 86.940 118.705 +*N chany_top_out[16]:3 *C 86.895 118.660 +*N chany_top_out[16]:4 *C 85.598 118.660 + +*CAP +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[16] 0.0005558264 +2 chany_top_out[16]:2 0.0005558264 +3 chany_top_out[16]:3 0.0001029537 +4 chany_top_out[16]:4 0.0001029537 + +*RES +0 mux_top_track_32\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[16]:4 0.152 +1 chany_top_out[16]:3 chany_top_out[16]:2 0.0045 +2 chany_top_out[16]:2 chany_top_out[16] 0.009433036 +3 chany_top_out[16]:4 chany_top_out[16]:3 0.001158482 + +*END + +*D_NET chany_bottom_out[2] 0.001205094 //LENGTH 8.610 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 47.440 4.080 +*P chany_bottom_out[2] O *L 0.7423 *C 52.440 1.325 +*N chany_bottom_out[2]:2 *C 52.440 3.740 +*N chany_bottom_out[2]:3 *C 51.980 3.740 +*N chany_bottom_out[2]:4 *C 51.935 3.740 +*N chany_bottom_out[2]:5 *C 48.300 3.740 +*N chany_bottom_out[2]:6 *C 48.300 4.080 +*N chany_bottom_out[2]:7 *C 47.477 4.080 + +*CAP +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[2] 0.0001440114 +2 chany_bottom_out[2]:2 0.0001783207 +3 chany_bottom_out[2]:3 6.692963e-05 +4 chany_bottom_out[2]:4 0.0003220586 +5 chany_bottom_out[2]:5 0.0003440898 +6 chany_bottom_out[2]:6 8.535735e-05 +7 chany_bottom_out[2]:7 6.332611e-05 + +*RES +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[2]:7 0.152 +1 chany_bottom_out[2]:7 chany_bottom_out[2]:6 0.0007343751 +2 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.0045 +3 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0004107143 +4 chany_bottom_out[2]:6 chany_bottom_out[2]:5 0.0003035715 +5 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.003245536 +6 chany_bottom_out[2]:2 chany_bottom_out[2] 0.00215625 + +*END + +*D_NET chanx_left_out[2] 0.0005964346 //LENGTH 4.105 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.545 82.620 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 82.960 +*N chanx_left_out[2]:2 *C 4.133 82.960 +*N chanx_left_out[2]:3 *C 4.140 82.960 +*N chanx_left_out[2]:4 *C 4.140 82.620 +*N chanx_left_out[2]:5 *C 4.163 82.620 +*N chanx_left_out[2]:6 *C 4.530 82.620 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 0.0002042388 +2 chanx_left_out[2]:2 0.0002042388 +3 chanx_left_out[2]:3 5.264767e-05 +4 chanx_left_out[2]:4 4.89782e-05 +5 chanx_left_out[2]:5 4.266557e-05 +6 chanx_left_out[2]:6 4.266557e-05 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:6 0.152 +1 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0001997283 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.0001634615 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.000454725 + +*END + +*D_NET chanx_left_out[9] 0.001444748 //LENGTH 10.205 LUMPCC 0 DR + +*CONN +*I mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.280 66.640 +*P chanx_left_out[9] O *L 0.7423 *C 1.305 69.360 +*N chanx_left_out[9]:2 *C 8.273 69.360 +*N chanx_left_out[9]:3 *C 8.280 69.303 +*N chanx_left_out[9]:4 *C 8.280 66.685 +*N chanx_left_out[9]:5 *C 8.280 66.640 + +*CAP +0 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[9] 0.000531068 +2 chanx_left_out[9]:2 0.000531068 +3 chanx_left_out[9]:3 0.0001728298 +4 chanx_left_out[9]:4 0.0001728298 +5 chanx_left_out[9]:5 3.595282e-05 + +*RES +0 mux_left_track_19\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[9]:5 0.152 +1 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +2 chanx_left_out[9]:2 chanx_left_out[9] 0.001091575 +3 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +4 chanx_left_out[9]:4 chanx_left_out[9]:3 0.002337054 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[1] 0.004025032 //LENGTH 31.980 LUMPCC 0.0003697571 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 49.985 104.720 +*I mux_top_track_4\/mux_l2_in_0_:S I *L 0.00357 *C 49.580 112.200 +*I mux_top_track_4\/mux_l2_in_1_:S I *L 0.00357 *C 54.180 112.200 +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 58.135 115.260 +*I mux_top_track_4\/mux_l2_in_2_:S I *L 0.00357 *C 55.540 105.060 +*I mux_top_track_4\/mux_l2_in_3_:S I *L 0.00357 *C 56.940 101.320 +*N mux_tree_tapbuf_size14_0_sram[1]:6 *C 56.903 101.320 +*N mux_tree_tapbuf_size14_0_sram[1]:7 *C 55.705 101.320 +*N mux_tree_tapbuf_size14_0_sram[1]:8 *C 55.660 101.365 +*N mux_tree_tapbuf_size14_0_sram[1]:9 *C 55.660 105.015 +*N mux_tree_tapbuf_size14_0_sram[1]:10 *C 55.555 105.060 +*N mux_tree_tapbuf_size14_0_sram[1]:11 *C 58.135 115.260 +*N mux_tree_tapbuf_size14_0_sram[1]:12 *C 57.960 115.260 +*N mux_tree_tapbuf_size14_0_sram[1]:13 *C 57.960 115.215 +*N mux_tree_tapbuf_size14_0_sram[1]:14 *C 57.960 112.585 +*N mux_tree_tapbuf_size14_0_sram[1]:15 *C 57.915 112.540 +*N mux_tree_tapbuf_size14_0_sram[1]:16 *C 54.180 112.540 +*N mux_tree_tapbuf_size14_0_sram[1]:17 *C 54.180 112.223 +*N mux_tree_tapbuf_size14_0_sram[1]:18 *C 49.617 112.200 +*N mux_tree_tapbuf_size14_0_sram[1]:19 *C 52.900 112.200 +*N mux_tree_tapbuf_size14_0_sram[1]:20 *C 52.900 112.155 +*N mux_tree_tapbuf_size14_0_sram[1]:21 *C 52.900 105.105 +*N mux_tree_tapbuf_size14_0_sram[1]:22 *C 52.900 105.060 +*N mux_tree_tapbuf_size14_0_sram[1]:23 *C 50.140 105.060 +*N mux_tree_tapbuf_size14_0_sram[1]:24 *C 49.985 104.720 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_4\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_top_track_4\/mux_l2_in_2_:S 1e-06 +5 mux_top_track_4\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size14_0_sram[1]:6 0.0001235245 +7 mux_tree_tapbuf_size14_0_sram[1]:7 0.0001235245 +8 mux_tree_tapbuf_size14_0_sram[1]:8 0.0002241309 +9 mux_tree_tapbuf_size14_0_sram[1]:9 0.0002241309 +10 mux_tree_tapbuf_size14_0_sram[1]:10 0.0001431174 +11 mux_tree_tapbuf_size14_0_sram[1]:11 4.874512e-05 +12 mux_tree_tapbuf_size14_0_sram[1]:12 5.288834e-05 +13 mux_tree_tapbuf_size14_0_sram[1]:13 0.0001504937 +14 mux_tree_tapbuf_size14_0_sram[1]:14 0.0001504937 +15 mux_tree_tapbuf_size14_0_sram[1]:15 0.0001904849 +16 mux_tree_tapbuf_size14_0_sram[1]:16 0.0002195037 +17 mux_tree_tapbuf_size14_0_sram[1]:17 0.0001177324 +18 mux_tree_tapbuf_size14_0_sram[1]:18 0.0002101841 +19 mux_tree_tapbuf_size14_0_sram[1]:19 0.0003279123 +20 mux_tree_tapbuf_size14_0_sram[1]:20 0.0004018346 +21 mux_tree_tapbuf_size14_0_sram[1]:21 0.0004018346 +22 mux_tree_tapbuf_size14_0_sram[1]:22 0.0003198536 +23 mux_tree_tapbuf_size14_0_sram[1]:23 0.0001646654 +24 mux_tree_tapbuf_size14_0_sram[1]:24 5.422042e-05 +25 mux_tree_tapbuf_size14_0_sram[1]:10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.566431e-05 +26 mux_tree_tapbuf_size14_0_sram[1]:22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.526172e-05 +27 mux_tree_tapbuf_size14_0_sram[1]:22 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.566431e-05 +28 mux_tree_tapbuf_size14_0_sram[1]:23 mux_top_track_4/sky130_fd_sc_hd__mux2_1_5_X[0]:3 3.526172e-05 +29 mux_tree_tapbuf_size14_0_sram[1]:15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 6.956729e-05 +30 mux_tree_tapbuf_size14_0_sram[1]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 1.373568e-05 +31 mux_tree_tapbuf_size14_0_sram[1]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 1.373568e-05 +32 mux_tree_tapbuf_size14_0_sram[1]:19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 2.275369e-05 +33 mux_tree_tapbuf_size14_0_sram[1]:19 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 7.895854e-06 +34 mux_tree_tapbuf_size14_0_sram[1]:17 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 7.895854e-06 +35 mux_tree_tapbuf_size14_0_sram[1]:18 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 2.275369e-05 +36 mux_tree_tapbuf_size14_0_sram[1]:16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 6.956729e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size14_0_sram[1]:24 0.152 +1 mux_tree_tapbuf_size14_0_sram[1]:10 mux_top_track_4\/mux_l2_in_2_:S 0.152 +2 mux_tree_tapbuf_size14_0_sram[1]:10 mux_tree_tapbuf_size14_0_sram[1]:9 0.0045 +3 mux_tree_tapbuf_size14_0_sram[1]:15 mux_tree_tapbuf_size14_0_sram[1]:14 0.0045 +4 mux_tree_tapbuf_size14_0_sram[1]:14 mux_tree_tapbuf_size14_0_sram[1]:13 0.002348214 +5 mux_tree_tapbuf_size14_0_sram[1]:12 mux_tree_tapbuf_size14_0_sram[1]:11 9.51087e-05 +6 mux_tree_tapbuf_size14_0_sram[1]:13 mux_tree_tapbuf_size14_0_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size14_0_sram[1]:11 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +8 mux_tree_tapbuf_size14_0_sram[1]:22 mux_tree_tapbuf_size14_0_sram[1]:21 0.0045 +9 mux_tree_tapbuf_size14_0_sram[1]:22 mux_tree_tapbuf_size14_0_sram[1]:10 0.002370536 +10 mux_tree_tapbuf_size14_0_sram[1]:21 mux_tree_tapbuf_size14_0_sram[1]:20 0.006294643 +11 mux_tree_tapbuf_size14_0_sram[1]:19 mux_tree_tapbuf_size14_0_sram[1]:18 0.002930804 +12 mux_tree_tapbuf_size14_0_sram[1]:19 mux_tree_tapbuf_size14_0_sram[1]:17 0.001142857 +13 mux_tree_tapbuf_size14_0_sram[1]:20 mux_tree_tapbuf_size14_0_sram[1]:19 0.0045 +14 mux_tree_tapbuf_size14_0_sram[1]:9 mux_tree_tapbuf_size14_0_sram[1]:8 0.003258929 +15 mux_tree_tapbuf_size14_0_sram[1]:7 mux_tree_tapbuf_size14_0_sram[1]:6 0.001069196 +16 mux_tree_tapbuf_size14_0_sram[1]:8 mux_tree_tapbuf_size14_0_sram[1]:7 0.0045 +17 mux_tree_tapbuf_size14_0_sram[1]:6 mux_top_track_4\/mux_l2_in_3_:S 0.152 +18 mux_tree_tapbuf_size14_0_sram[1]:17 mux_top_track_4\/mux_l2_in_1_:S 0.152 +19 mux_tree_tapbuf_size14_0_sram[1]:17 mux_tree_tapbuf_size14_0_sram[1]:16 0.0002834821 +20 mux_tree_tapbuf_size14_0_sram[1]:18 mux_top_track_4\/mux_l2_in_0_:S 0.152 +21 mux_tree_tapbuf_size14_0_sram[1]:24 mux_tree_tapbuf_size14_0_sram[1]:23 0.0003035715 +22 mux_tree_tapbuf_size14_0_sram[1]:23 mux_tree_tapbuf_size14_0_sram[1]:22 0.002464286 +23 mux_tree_tapbuf_size14_0_sram[1]:16 mux_tree_tapbuf_size14_0_sram[1]:15 0.003334822 + +*END + +*D_NET mux_tree_tapbuf_size3_2_sram[1] 0.00308673 //LENGTH 17.090 LUMPCC 0.001422263 DR + +*CONN +*I mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.945 72.080 +*I mem_left_track_21\/FTB_25__57:A I *L 0.001746 *C 33.580 74.800 +*I mux_left_track_21\/mux_l2_in_0_:S I *L 0.00357 *C 25.860 74.800 +*N mux_tree_tapbuf_size3_2_sram[1]:3 *C 25.898 74.800 +*N mux_tree_tapbuf_size3_2_sram[1]:4 *C 33.543 74.800 +*N mux_tree_tapbuf_size3_2_sram[1]:5 *C 33.580 74.755 +*N mux_tree_tapbuf_size3_2_sram[1]:6 *C 33.580 72.138 +*N mux_tree_tapbuf_size3_2_sram[1]:7 *C 33.587 72.080 +*N mux_tree_tapbuf_size3_2_sram[1]:8 *C 38.172 72.080 +*N mux_tree_tapbuf_size3_2_sram[1]:9 *C 38.180 72.080 +*N mux_tree_tapbuf_size3_2_sram[1]:10 *C 38.225 72.080 +*N mux_tree_tapbuf_size3_2_sram[1]:11 *C 38.907 72.080 + +*CAP +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_21\/FTB_25__57:A 1e-06 +2 mux_left_track_21\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_2_sram[1]:3 0.0004403042 +4 mux_tree_tapbuf_size3_2_sram[1]:4 0.0004403042 +5 mux_tree_tapbuf_size3_2_sram[1]:5 0.0002044794 +6 mux_tree_tapbuf_size3_2_sram[1]:6 0.0002044794 +7 mux_tree_tapbuf_size3_2_sram[1]:7 8.022678e-05 +8 mux_tree_tapbuf_size3_2_sram[1]:8 8.022678e-05 +9 mux_tree_tapbuf_size3_2_sram[1]:9 3.779549e-05 +10 mux_tree_tapbuf_size3_2_sram[1]:10 8.682561e-05 +11 mux_tree_tapbuf_size3_2_sram[1]:11 8.682561e-05 +12 mux_tree_tapbuf_size3_2_sram[1]:7 left_top_grid_pin_42_[0]:20 0.0002640499 +13 mux_tree_tapbuf_size3_2_sram[1]:8 left_top_grid_pin_42_[0]:19 0.0002640499 +14 mux_tree_tapbuf_size3_2_sram[1]:3 mux_tree_tapbuf_size7_1_sram[0]:16 0.0001609375 +15 mux_tree_tapbuf_size3_2_sram[1]:3 mux_tree_tapbuf_size7_1_sram[0]:11 1.983723e-05 +16 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size7_1_sram[0]:17 0.0001609375 +17 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size7_1_sram[0]:10 1.983723e-05 +18 mux_tree_tapbuf_size3_2_sram[1]:5 mux_tree_tapbuf_size7_1_sram[0]:18 1.073388e-07 +19 mux_tree_tapbuf_size3_2_sram[1]:6 mux_tree_tapbuf_size7_1_sram[0]:12 1.073388e-07 +20 mux_tree_tapbuf_size3_2_sram[1]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002661992 +21 mux_tree_tapbuf_size3_2_sram[1]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002661992 + +*RES +0 mem_left_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_2_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_2_sram[1]:3 mux_left_track_21\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_2_sram[1]:4 mem_left_track_21\/FTB_25__57:A 0.152 +3 mux_tree_tapbuf_size3_2_sram[1]:4 mux_tree_tapbuf_size3_2_sram[1]:3 0.006825893 +4 mux_tree_tapbuf_size3_2_sram[1]:5 mux_tree_tapbuf_size3_2_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size3_2_sram[1]:6 mux_tree_tapbuf_size3_2_sram[1]:5 0.002337054 +6 mux_tree_tapbuf_size3_2_sram[1]:7 mux_tree_tapbuf_size3_2_sram[1]:6 0.00341 +7 mux_tree_tapbuf_size3_2_sram[1]:9 mux_tree_tapbuf_size3_2_sram[1]:8 0.00341 +8 mux_tree_tapbuf_size3_2_sram[1]:8 mux_tree_tapbuf_size3_2_sram[1]:7 0.0007183166 +9 mux_tree_tapbuf_size3_2_sram[1]:10 mux_tree_tapbuf_size3_2_sram[1]:9 0.0045 +10 mux_tree_tapbuf_size3_2_sram[1]:11 mux_tree_tapbuf_size3_2_sram[1]:10 0.0006093751 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_3_ccff_tail[0] 0.0008682889 //LENGTH 5.600 LUMPCC 0.0002429952 DR + +*CONN +*I mem_left_track_23\/FTB_26__58:X O *L 0 *C 44.395 76.840 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.095 75.140 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 *C 47.095 75.140 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 *C 47.380 75.140 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 *C 47.380 75.185 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 *C 47.380 76.795 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 *C 47.335 76.840 +*N mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 *C 44.433 76.840 + +*CAP +0 mem_left_track_23\/FTB_26__58:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 5.479151e-05 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 5.909046e-05 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.0001088933 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0001088933 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.0001458126 +7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.0001458126 +8 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001214976 +9 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001214976 + +*RES +0 mem_left_track_23\/FTB_26__58:X mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:2 0.0001548913 +3 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_3_ccff_tail[0]:6 0.002591518 + +*END + +*D_NET mux_tree_tapbuf_size4_1_sram[0] 0.001693923 //LENGTH 14.065 LUMPCC 0 DR + +*CONN +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 84.945 61.200 +*I mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 80.215 58.820 +*I mux_left_track_11\/mux_l1_in_0_:S I *L 0.00357 *C 87.960 56.100 +*N mux_tree_tapbuf_size4_1_sram[0]:3 *C 87.922 56.100 +*N mux_tree_tapbuf_size4_1_sram[0]:4 *C 84.685 56.100 +*N mux_tree_tapbuf_size4_1_sram[0]:5 *C 84.640 56.145 +*N mux_tree_tapbuf_size4_1_sram[0]:6 *C 80.252 58.820 +*N mux_tree_tapbuf_size4_1_sram[0]:7 *C 84.595 58.820 +*N mux_tree_tapbuf_size4_1_sram[0]:8 *C 84.640 58.820 +*N mux_tree_tapbuf_size4_1_sram[0]:9 *C 84.640 61.155 +*N mux_tree_tapbuf_size4_1_sram[0]:10 *C 84.640 61.200 +*N mux_tree_tapbuf_size4_1_sram[0]:11 *C 84.945 61.200 + +*CAP +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_11\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_1_sram[0]:3 0.0002108541 +4 mux_tree_tapbuf_size4_1_sram[0]:4 0.0002108541 +5 mux_tree_tapbuf_size4_1_sram[0]:5 0.0001472178 +6 mux_tree_tapbuf_size4_1_sram[0]:6 0.0002816942 +7 mux_tree_tapbuf_size4_1_sram[0]:7 0.0002816942 +8 mux_tree_tapbuf_size4_1_sram[0]:8 0.0003094928 +9 mux_tree_tapbuf_size4_1_sram[0]:9 0.0001305982 +10 mux_tree_tapbuf_size4_1_sram[0]:10 6.077759e-05 +11 mux_tree_tapbuf_size4_1_sram[0]:11 5.773963e-05 + +*RES +0 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_1_sram[0]:11 0.152 +1 mux_tree_tapbuf_size4_1_sram[0]:3 mux_left_track_11\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_1_sram[0]:4 mux_tree_tapbuf_size4_1_sram[0]:3 0.002890625 +3 mux_tree_tapbuf_size4_1_sram[0]:5 mux_tree_tapbuf_size4_1_sram[0]:4 0.0045 +4 mux_tree_tapbuf_size4_1_sram[0]:7 mux_tree_tapbuf_size4_1_sram[0]:6 0.003877232 +5 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size4_1_sram[0]:8 mux_tree_tapbuf_size4_1_sram[0]:5 0.002388393 +7 mux_tree_tapbuf_size4_1_sram[0]:6 mem_left_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +8 mux_tree_tapbuf_size4_1_sram[0]:10 mux_tree_tapbuf_size4_1_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size4_1_sram[0]:9 mux_tree_tapbuf_size4_1_sram[0]:8 0.002084821 +10 mux_tree_tapbuf_size4_1_sram[0]:11 mux_tree_tapbuf_size4_1_sram[0]:10 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size4_mem_1_ccff_tail[0] 0.002718425 //LENGTH 21.740 LUMPCC 0.0002571963 DR + +*CONN +*I mem_left_track_11\/FTB_20__52:X O *L 0 *C 83.025 44.200 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.955 47.940 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 *C 65.993 47.940 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 *C 80.915 47.940 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 *C 80.960 47.895 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 *C 80.960 44.245 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 *C 81.005 44.200 +*N mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 *C 82.987 44.200 + +*CAP +0 mem_left_track_11\/FTB_20__52:X 1e-06 +1 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.0008572308 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0008572308 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.0002238739 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0002238739 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 0.0001485096 +7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 0.0001485096 +8 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0001285981 +9 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.0001285981 + +*RES +0 mem_left_track_11\/FTB_20__52:X mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.01332366 +3 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:4 0.003258929 +6 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:6 0.001770089 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.001487939 //LENGTH 12.770 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_25\/FTB_16__48:X O *L 0 *C 85.795 23.800 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 78.375 28.220 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 78.413 28.220 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 84.595 28.220 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 84.640 28.175 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 84.640 23.845 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 84.685 23.800 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 85.758 23.800 + +*CAP +0 mem_bottom_track_25\/FTB_16__48:X 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 0.0004347407 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0004347407 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.0002191806 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0002191806 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 8.904818e-05 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 8.904818e-05 + +*RES +0 mem_bottom_track_25\/FTB_16__48:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 0.00552009 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.0009575893 + +*END + +*D_NET mux_tree_tapbuf_size7_0_sram[2] 0.003399937 //LENGTH 25.045 LUMPCC 0.001319783 DR + +*CONN +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 65.625 86.020 +*I mux_top_track_16\/mux_l3_in_0_:S I *L 0.008363 *C 54.120 94.118 +*I mem_top_track_16\/FTB_8__40:A I *L 0.001746 *C 69.000 93.840 +*N mux_tree_tapbuf_size7_0_sram[2]:3 *C 68.963 93.840 +*N mux_tree_tapbuf_size7_0_sram[2]:4 *C 68.080 93.840 +*N mux_tree_tapbuf_size7_0_sram[2]:5 *C 68.080 94.180 +*N mux_tree_tapbuf_size7_0_sram[2]:6 *C 66.240 94.180 +*N mux_tree_tapbuf_size7_0_sram[2]:7 *C 66.240 94.135 +*N mux_tree_tapbuf_size7_0_sram[2]:8 *C 66.240 86.065 +*N mux_tree_tapbuf_size7_0_sram[2]:9 *C 66.195 86.020 +*N mux_tree_tapbuf_size7_0_sram[2]:10 *C 65.663 86.020 + +*CAP +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_16\/mux_l3_in_0_:S 0.0005132238 +2 mem_top_track_16\/FTB_8__40:A 1e-06 +3 mux_tree_tapbuf_size7_0_sram[2]:3 4.131035e-05 +4 mux_tree_tapbuf_size7_0_sram[2]:4 6.69032e-05 +5 mux_tree_tapbuf_size7_0_sram[2]:5 8.248863e-05 +6 mux_tree_tapbuf_size7_0_sram[2]:6 0.0006026663 +7 mux_tree_tapbuf_size7_0_sram[2]:7 0.0003316788 +8 mux_tree_tapbuf_size7_0_sram[2]:8 0.0003316788 +9 mux_tree_tapbuf_size7_0_sram[2]:9 5.410203e-05 +10 mux_tree_tapbuf_size7_0_sram[2]:10 5.410203e-05 +11 mux_tree_tapbuf_size7_0_sram[2]:7 chany_bottom_in[4]:31 0.0002197233 +12 mux_tree_tapbuf_size7_0_sram[2]:8 chany_bottom_in[4]:32 0.0002197233 +13 mux_top_track_16\/mux_l3_in_0_:S chany_top_out[8]:8 0.0002676603 +14 mux_tree_tapbuf_size7_0_sram[2]:6 chany_top_out[8]:7 0.0002676603 +15 mux_tree_tapbuf_size7_0_sram[2]:6 chany_top_out[8]:8 5.626328e-05 +16 mux_tree_tapbuf_size7_0_sram[2]:5 chany_top_out[8]:7 5.626328e-05 +17 mux_top_track_16\/mux_l3_in_0_:S mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 4.897243e-05 +18 mux_tree_tapbuf_size7_0_sram[2]:3 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 4.016977e-05 +19 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 2.710248e-05 +20 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 4.897243e-05 +21 mux_tree_tapbuf_size7_0_sram[2]:5 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:7 2.710248e-05 +22 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_mem_0_ccff_tail[0]:6 4.016977e-05 + +*RES +0 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_0_sram[2]:10 0.152 +1 mux_tree_tapbuf_size7_0_sram[2]:3 mem_top_track_16\/FTB_8__40:A 0.152 +2 mux_tree_tapbuf_size7_0_sram[2]:6 mux_top_track_16\/mux_l3_in_0_:S 0.01082143 +3 mux_tree_tapbuf_size7_0_sram[2]:6 mux_tree_tapbuf_size7_0_sram[2]:5 0.001642857 +4 mux_tree_tapbuf_size7_0_sram[2]:7 mux_tree_tapbuf_size7_0_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size7_0_sram[2]:9 mux_tree_tapbuf_size7_0_sram[2]:8 0.0045 +6 mux_tree_tapbuf_size7_0_sram[2]:8 mux_tree_tapbuf_size7_0_sram[2]:7 0.007205357 +7 mux_tree_tapbuf_size7_0_sram[2]:10 mux_tree_tapbuf_size7_0_sram[2]:9 0.0004754465 +8 mux_tree_tapbuf_size7_0_sram[2]:5 mux_tree_tapbuf_size7_0_sram[2]:4 0.0003035715 +9 mux_tree_tapbuf_size7_0_sram[2]:4 mux_tree_tapbuf_size7_0_sram[2]:3 0.0007879465 + +*END + +*D_NET mux_tree_tapbuf_size7_3_sram[0] 0.009860149 //LENGTH 74.630 LUMPCC 0.001436791 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 17.785 47.600 +*I mux_left_track_1\/mux_l1_in_3_:S I *L 0.00357 *C 16.460 88.740 +*I mux_left_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 15.540 90.440 +*I mux_left_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 26.780 88.695 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 34.140 90.440 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 14.900 93.500 +*N mux_tree_tapbuf_size7_3_sram[0]:6 *C 14.938 93.500 +*N mux_tree_tapbuf_size7_3_sram[0]:7 *C 16.975 93.500 +*N mux_tree_tapbuf_size7_3_sram[0]:8 *C 17.020 93.455 +*N mux_tree_tapbuf_size7_3_sram[0]:9 *C 34.040 90.440 +*N mux_tree_tapbuf_size7_3_sram[0]:10 *C 34.040 90.395 +*N mux_tree_tapbuf_size7_3_sram[0]:11 *C 34.040 89.125 +*N mux_tree_tapbuf_size7_3_sram[0]:12 *C 33.995 89.080 +*N mux_tree_tapbuf_size7_3_sram[0]:13 *C 26.780 89.080 +*N mux_tree_tapbuf_size7_3_sram[0]:14 *C 26.780 88.770 +*N mux_tree_tapbuf_size7_3_sram[0]:15 *C 26.780 88.695 +*N mux_tree_tapbuf_size7_3_sram[0]:16 *C 26.723 88.400 +*N mux_tree_tapbuf_size7_3_sram[0]:17 *C 23.045 88.400 +*N mux_tree_tapbuf_size7_3_sram[0]:18 *C 23.000 88.445 +*N mux_tree_tapbuf_size7_3_sram[0]:19 *C 23.000 90.395 +*N mux_tree_tapbuf_size7_3_sram[0]:20 *C 22.955 90.440 +*N mux_tree_tapbuf_size7_3_sram[0]:21 *C 15.578 90.440 +*N mux_tree_tapbuf_size7_3_sram[0]:22 *C 17.020 90.440 +*N mux_tree_tapbuf_size7_3_sram[0]:23 *C 17.020 90.440 +*N mux_tree_tapbuf_size7_3_sram[0]:24 *C 16.460 88.740 +*N mux_tree_tapbuf_size7_3_sram[0]:25 *C 16.560 88.740 +*N mux_tree_tapbuf_size7_3_sram[0]:26 *C 17.020 88.740 +*N mux_tree_tapbuf_size7_3_sram[0]:27 *C 17.020 47.645 +*N mux_tree_tapbuf_size7_3_sram[0]:28 *C 17.065 47.600 +*N mux_tree_tapbuf_size7_3_sram[0]:29 *C 17.748 47.600 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_1\/mux_l1_in_3_:S 1e-06 +2 mux_left_track_1\/mux_l1_in_2_:S 1e-06 +3 mux_left_track_1\/mux_l1_in_1_:S 1e-06 +4 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +5 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +6 mux_tree_tapbuf_size7_3_sram[0]:6 0.0002106906 +7 mux_tree_tapbuf_size7_3_sram[0]:7 0.0002106906 +8 mux_tree_tapbuf_size7_3_sram[0]:8 0.000177172 +9 mux_tree_tapbuf_size7_3_sram[0]:9 3.472918e-05 +10 mux_tree_tapbuf_size7_3_sram[0]:10 0.0001048953 +11 mux_tree_tapbuf_size7_3_sram[0]:11 0.0001048953 +12 mux_tree_tapbuf_size7_3_sram[0]:12 0.0005558502 +13 mux_tree_tapbuf_size7_3_sram[0]:13 0.0005745994 +14 mux_tree_tapbuf_size7_3_sram[0]:14 1.336352e-05 +15 mux_tree_tapbuf_size7_3_sram[0]:15 7.848767e-05 +16 mux_tree_tapbuf_size7_3_sram[0]:16 0.0002391896 +17 mux_tree_tapbuf_size7_3_sram[0]:17 0.0002196275 +18 mux_tree_tapbuf_size7_3_sram[0]:18 0.0001230316 +19 mux_tree_tapbuf_size7_3_sram[0]:19 0.0001230316 +20 mux_tree_tapbuf_size7_3_sram[0]:20 0.0003996436 +21 mux_tree_tapbuf_size7_3_sram[0]:21 0.0001013768 +22 mux_tree_tapbuf_size7_3_sram[0]:22 0.0005348559 +23 mux_tree_tapbuf_size7_3_sram[0]:23 0.0003109266 +24 mux_tree_tapbuf_size7_3_sram[0]:24 3.381345e-05 +25 mux_tree_tapbuf_size7_3_sram[0]:25 6.12345e-05 +26 mux_tree_tapbuf_size7_3_sram[0]:26 0.002075274 +27 mux_tree_tapbuf_size7_3_sram[0]:27 0.001944528 +28 mux_tree_tapbuf_size7_3_sram[0]:28 9.272507e-05 +29 mux_tree_tapbuf_size7_3_sram[0]:29 9.272507e-05 +30 mux_tree_tapbuf_size7_3_sram[0]:27 optlc_net_139:31 5.556346e-06 +31 mux_tree_tapbuf_size7_3_sram[0]:27 optlc_net_139:62 8.913663e-05 +32 mux_tree_tapbuf_size7_3_sram[0]:27 optlc_net_139:61 0.0001851398 +33 mux_tree_tapbuf_size7_3_sram[0]:27 optlc_net_139:36 9.377487e-06 +34 mux_tree_tapbuf_size7_3_sram[0]:11 optlc_net_139:74 2.867296e-08 +35 mux_tree_tapbuf_size7_3_sram[0]:10 optlc_net_139:70 2.867296e-08 +36 mux_tree_tapbuf_size7_3_sram[0]:26 optlc_net_139:35 9.377487e-06 +37 mux_tree_tapbuf_size7_3_sram[0]:26 optlc_net_139:58 0.0001851398 +38 mux_tree_tapbuf_size7_3_sram[0]:26 optlc_net_139:37 5.556346e-06 +39 mux_tree_tapbuf_size7_3_sram[0]:26 optlc_net_139:61 8.913663e-05 +40 mux_tree_tapbuf_size7_3_sram[0]:22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.843733e-05 +41 mux_tree_tapbuf_size7_3_sram[0]:22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.65252e-05 +42 mux_tree_tapbuf_size7_3_sram[0]:21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.843733e-05 +43 mux_tree_tapbuf_size7_3_sram[0]:20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.65252e-05 +44 mux_tree_tapbuf_size7_3_sram[0]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.629814e-05 +45 mux_tree_tapbuf_size7_3_sram[0]:18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 1.436123e-05 +46 mux_tree_tapbuf_size7_3_sram[0]:19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 1.436123e-05 +47 mux_tree_tapbuf_size7_3_sram[0]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.629814e-05 +48 mux_tree_tapbuf_size7_3_sram[0]:27 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.860667e-05 +49 mux_tree_tapbuf_size7_3_sram[0]:26 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.860667e-05 +50 mux_tree_tapbuf_size7_3_sram[0]:27 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001215012 +51 mux_tree_tapbuf_size7_3_sram[0]:26 mux_left_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001215012 +52 mux_tree_tapbuf_size7_3_sram[0]:27 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 8.342673e-05 +53 mux_tree_tapbuf_size7_3_sram[0]:26 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 8.342673e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_3_sram[0]:29 0.152 +1 mux_tree_tapbuf_size7_3_sram[0]:6 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size7_3_sram[0]:7 mux_tree_tapbuf_size7_3_sram[0]:6 0.001819197 +3 mux_tree_tapbuf_size7_3_sram[0]:8 mux_tree_tapbuf_size7_3_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size7_3_sram[0]:22 mux_tree_tapbuf_size7_3_sram[0]:21 0.001287946 +5 mux_tree_tapbuf_size7_3_sram[0]:22 mux_tree_tapbuf_size7_3_sram[0]:20 0.005299108 +6 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:22 0.0045 +7 mux_tree_tapbuf_size7_3_sram[0]:23 mux_tree_tapbuf_size7_3_sram[0]:8 0.002691964 +8 mux_tree_tapbuf_size7_3_sram[0]:21 mux_left_track_1\/mux_l1_in_2_:S 0.152 +9 mux_tree_tapbuf_size7_3_sram[0]:15 mux_left_track_1\/mux_l1_in_1_:S 0.152 +10 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:14 4.360465e-05 +11 mux_tree_tapbuf_size7_3_sram[0]:15 mux_tree_tapbuf_size7_3_sram[0]:13 0.00034375 +12 mux_tree_tapbuf_size7_3_sram[0]:28 mux_tree_tapbuf_size7_3_sram[0]:27 0.0045 +13 mux_tree_tapbuf_size7_3_sram[0]:27 mux_tree_tapbuf_size7_3_sram[0]:26 0.03669197 +14 mux_tree_tapbuf_size7_3_sram[0]:29 mux_tree_tapbuf_size7_3_sram[0]:28 0.000609375 +15 mux_tree_tapbuf_size7_3_sram[0]:12 mux_tree_tapbuf_size7_3_sram[0]:11 0.0045 +16 mux_tree_tapbuf_size7_3_sram[0]:11 mux_tree_tapbuf_size7_3_sram[0]:10 0.001133929 +17 mux_tree_tapbuf_size7_3_sram[0]:9 mux_left_track_1\/mux_l1_in_0_:S 0.152 +18 mux_tree_tapbuf_size7_3_sram[0]:10 mux_tree_tapbuf_size7_3_sram[0]:9 0.0045 +19 mux_tree_tapbuf_size7_3_sram[0]:17 mux_tree_tapbuf_size7_3_sram[0]:16 0.003283482 +20 mux_tree_tapbuf_size7_3_sram[0]:18 mux_tree_tapbuf_size7_3_sram[0]:17 0.0045 +21 mux_tree_tapbuf_size7_3_sram[0]:20 mux_tree_tapbuf_size7_3_sram[0]:19 0.0045 +22 mux_tree_tapbuf_size7_3_sram[0]:19 mux_tree_tapbuf_size7_3_sram[0]:18 0.001741071 +23 mux_tree_tapbuf_size7_3_sram[0]:24 mux_left_track_1\/mux_l1_in_3_:S 0.152 +24 mux_tree_tapbuf_size7_3_sram[0]:25 mux_tree_tapbuf_size7_3_sram[0]:24 0.0045 +25 mux_tree_tapbuf_size7_3_sram[0]:16 mux_tree_tapbuf_size7_3_sram[0]:15 0.0001715116 +26 mux_tree_tapbuf_size7_3_sram[0]:13 mux_tree_tapbuf_size7_3_sram[0]:12 0.006441965 +27 mux_tree_tapbuf_size7_3_sram[0]:26 mux_tree_tapbuf_size7_3_sram[0]:25 0.0004107143 +28 mux_tree_tapbuf_size7_3_sram[0]:26 mux_tree_tapbuf_size7_3_sram[0]:23 0.001517857 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_4_ccff_tail[0] 0.0007107447 //LENGTH 5.550 LUMPCC 0.0001403471 DR + +*CONN +*I mem_left_track_3\/FTB_12__44:X O *L 0 *C 8.965 77.520 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 7.995 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 *C 7.958 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 *C 7.405 75.140 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 *C 7.360 75.185 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 *C 7.360 77.475 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 *C 7.405 77.520 +*N mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 *C 8.928 77.520 + +*CAP +0 mem_left_track_3\/FTB_12__44:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 6.230032e-05 +3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 6.230032e-05 +4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 0.000115441 +5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 0.000115441 +6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 0.0001064575 +7 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 0.0001064575 +8 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 chany_top_in[19]:5 7.017353e-05 +9 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 chany_top_in[19]:4 7.017353e-05 + +*RES +0 mem_left_track_3\/FTB_12__44:X mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 0.001359375 +2 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 0.0004933036 +5 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_4_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[2] 0.001392349 //LENGTH 10.990 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 31.125 96.560 +*I mux_top_track_2\/mux_l3_in_1_:S I *L 0.00357 *C 33.920 96.220 +*I mux_top_track_2\/mux_l3_in_0_:S I *L 0.00357 *C 34.400 101.320 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 35.105 98.940 +*N mux_tree_tapbuf_size8_0_sram[2]:4 *C 35.068 98.940 +*N mux_tree_tapbuf_size8_0_sram[2]:5 *C 34.545 98.940 +*N mux_tree_tapbuf_size8_0_sram[2]:6 *C 34.500 98.940 +*N mux_tree_tapbuf_size8_0_sram[2]:7 *C 34.385 101.320 +*N mux_tree_tapbuf_size8_0_sram[2]:8 *C 34.062 101.320 +*N mux_tree_tapbuf_size8_0_sram[2]:9 *C 34.040 101.275 +*N mux_tree_tapbuf_size8_0_sram[2]:10 *C 34.040 98.940 +*N mux_tree_tapbuf_size8_0_sram[2]:11 *C 34.040 96.265 +*N mux_tree_tapbuf_size8_0_sram[2]:12 *C 33.935 96.220 +*N mux_tree_tapbuf_size8_0_sram[2]:13 *C 31.280 96.220 +*N mux_tree_tapbuf_size8_0_sram[2]:14 *C 31.125 96.560 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:S 1e-06 +2 mux_top_track_2\/mux_l3_in_0_:S 1e-06 +3 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +4 mux_tree_tapbuf_size8_0_sram[2]:4 5.888204e-05 +5 mux_tree_tapbuf_size8_0_sram[2]:5 5.888204e-05 +6 mux_tree_tapbuf_size8_0_sram[2]:6 6.463367e-05 +7 mux_tree_tapbuf_size8_0_sram[2]:7 6.121211e-05 +8 mux_tree_tapbuf_size8_0_sram[2]:8 6.121211e-05 +9 mux_tree_tapbuf_size8_0_sram[2]:9 0.0001403956 +10 mux_tree_tapbuf_size8_0_sram[2]:10 0.0003395213 +11 mux_tree_tapbuf_size8_0_sram[2]:11 0.0001658873 +12 mux_tree_tapbuf_size8_0_sram[2]:12 0.000176414 +13 mux_tree_tapbuf_size8_0_sram[2]:13 0.0002029103 +14 mux_tree_tapbuf_size8_0_sram[2]:14 5.839804e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_0_sram[2]:14 0.152 +1 mux_tree_tapbuf_size8_0_sram[2]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +2 mux_tree_tapbuf_size8_0_sram[2]:5 mux_tree_tapbuf_size8_0_sram[2]:4 0.0004665179 +3 mux_tree_tapbuf_size8_0_sram[2]:6 mux_tree_tapbuf_size8_0_sram[2]:5 0.0045 +4 mux_tree_tapbuf_size8_0_sram[2]:14 mux_tree_tapbuf_size8_0_sram[2]:13 0.0003035715 +5 mux_tree_tapbuf_size8_0_sram[2]:7 mux_top_track_2\/mux_l3_in_0_:S 0.152 +6 mux_tree_tapbuf_size8_0_sram[2]:8 mux_tree_tapbuf_size8_0_sram[2]:7 0.0001752718 +7 mux_tree_tapbuf_size8_0_sram[2]:9 mux_tree_tapbuf_size8_0_sram[2]:8 0.0045 +8 mux_tree_tapbuf_size8_0_sram[2]:12 mux_top_track_2\/mux_l3_in_1_:S 0.152 +9 mux_tree_tapbuf_size8_0_sram[2]:12 mux_tree_tapbuf_size8_0_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size8_0_sram[2]:11 mux_tree_tapbuf_size8_0_sram[2]:10 0.002388393 +11 mux_tree_tapbuf_size8_0_sram[2]:13 mux_tree_tapbuf_size8_0_sram[2]:12 0.002370536 +12 mux_tree_tapbuf_size8_0_sram[2]:10 mux_tree_tapbuf_size8_0_sram[2]:9 0.002084822 +13 mux_tree_tapbuf_size8_0_sram[2]:10 mux_tree_tapbuf_size8_0_sram[2]:6 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size8_mem_1_ccff_tail[0] 0.001931989 //LENGTH 16.440 LUMPCC 0.000236992 DR + +*CONN +*I mem_top_track_8\/FTB_4__36:X O *L 0 *C 74.285 94.520 +*I mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 63.195 98.940 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 *C 63.233 98.940 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 *C 73.555 98.940 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 *C 73.600 98.895 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 *C 73.600 94.565 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 *C 73.645 94.520 +*N mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 *C 74.248 94.520 + +*CAP +0 mem_top_track_8\/FTB_4__36:X 1e-06 +1 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 0.000639041 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.000639041 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.0001447509 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0001447509 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 6.270647e-05 +7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 6.270647e-05 +8 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 chany_bottom_in[6]:32 3.372563e-07 +9 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 chany_bottom_in[6]:31 3.372563e-07 +10 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 chany_bottom_in[6]:30 5.907936e-05 +11 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 chany_bottom_in[6]:29 5.907936e-05 +12 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:10 5.907936e-05 +13 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:9 5.907936e-05 + +*RES +0 mem_top_track_8\/FTB_4__36:X mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 0.0005379464 +2 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 0.003866071 +4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 0.009216518 +5 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size8_mem_1_ccff_tail[0]:2 mem_top_track_16\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET optlc_net_137 0.008491081 //LENGTH 66.005 LUMPCC 0.00205917 DR + +*CONN +*I optlc_132:HI O *L 0 *C 38.180 42.840 +*I mux_bottom_track_1\/mux_l2_in_3_:A0 I *L 0.001631 *C 46.635 37.060 +*I mux_bottom_track_5\/mux_l2_in_3_:A0 I *L 0.001631 *C 36.565 22.780 +*I mux_bottom_track_33\/mux_l2_in_1_:A0 I *L 0.001631 *C 12.595 39.100 +*I mux_bottom_track_17\/mux_l1_in_3_:A0 I *L 0.001631 *C 40.195 44.200 +*N optlc_net_137:5 *C 40.157 44.200 +*N optlc_net_137:6 *C 38.225 44.200 +*N optlc_net_137:7 *C 38.180 44.155 +*N optlc_net_137:8 *C 12.623 39.123 +*N optlc_net_137:9 *C 12.880 39.135 +*N optlc_net_137:10 *C 12.880 39.440 +*N optlc_net_137:11 *C 20.195 39.440 +*N optlc_net_137:12 *C 20.240 39.485 +*N optlc_net_137:13 *C 20.240 43.462 +*N optlc_net_137:14 *C 20.248 43.520 +*N optlc_net_137:15 *C 38.172 43.520 +*N optlc_net_137:16 *C 38.180 43.520 +*N optlc_net_137:17 *C 36.602 22.780 +*N optlc_net_137:18 *C 38.135 22.780 +*N optlc_net_137:19 *C 38.180 22.825 +*N optlc_net_137:20 *C 46.598 37.060 +*N optlc_net_137:21 *C 38.225 37.060 +*N optlc_net_137:22 *C 38.180 37.060 +*N optlc_net_137:23 *C 38.180 42.840 +*N optlc_net_137:24 *C 38.180 42.840 + +*CAP +0 optlc_132:HI 1e-06 +1 mux_bottom_track_1\/mux_l2_in_3_:A0 1e-06 +2 mux_bottom_track_5\/mux_l2_in_3_:A0 1e-06 +3 mux_bottom_track_33\/mux_l2_in_1_:A0 1e-06 +4 mux_bottom_track_17\/mux_l1_in_3_:A0 1e-06 +5 optlc_net_137:5 0.0001776712 +6 optlc_net_137:6 0.0001776712 +7 optlc_net_137:7 3.500287e-05 +8 optlc_net_137:8 2.92999e-05 +9 optlc_net_137:9 5.369824e-05 +10 optlc_net_137:10 0.0004901355 +11 optlc_net_137:11 0.0004657372 +12 optlc_net_137:12 0.0002333384 +13 optlc_net_137:13 0.0002333384 +14 optlc_net_137:14 0.0006586782 +15 optlc_net_137:15 0.0006586782 +16 optlc_net_137:16 9.915969e-05 +17 optlc_net_137:17 0.00013613 +18 optlc_net_137:18 0.00013613 +19 optlc_net_137:19 0.0005371161 +20 optlc_net_137:20 0.0005637211 +21 optlc_net_137:21 0.0005637211 +22 optlc_net_137:22 0.0008262487 +23 optlc_net_137:23 0.0003145843 +24 optlc_net_137:24 3.685049e-05 +25 optlc_net_137:19 prog_clk[0]:200 1.383907e-05 +26 optlc_net_137:15 prog_clk[0]:208 3.984521e-05 +27 optlc_net_137:15 prog_clk[0]:244 4.117306e-05 +28 optlc_net_137:15 prog_clk[0]:508 0.0001814897 +29 optlc_net_137:14 prog_clk[0]:244 3.984521e-05 +30 optlc_net_137:14 prog_clk[0]:245 4.117306e-05 +31 optlc_net_137:14 prog_clk[0]:512 0.0001814897 +32 optlc_net_137:22 prog_clk[0]:256 1.383907e-05 +33 optlc_net_137:19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001489666 +34 optlc_net_137:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 8.061072e-06 +35 optlc_net_137:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 9.957795e-06 +36 optlc_net_137:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 9.957795e-06 +37 optlc_net_137:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 6.343664e-05 +38 optlc_net_137:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 8.061072e-06 +39 optlc_net_137:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001489666 +40 optlc_net_137:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 6.343664e-05 +41 optlc_net_137:19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001223736 +42 optlc_net_137:22 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001223736 +43 optlc_net_137:15 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004004423 +44 optlc_net_137:14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004004423 + +*RES +0 optlc_132:HI optlc_net_137:24 0.152 +1 optlc_net_137:18 optlc_net_137:17 0.001368304 +2 optlc_net_137:19 optlc_net_137:18 0.0045 +3 optlc_net_137:17 mux_bottom_track_5\/mux_l2_in_3_:A0 0.152 +4 optlc_net_137:16 optlc_net_137:15 0.00341 +5 optlc_net_137:16 optlc_net_137:7 0.0005669643 +6 optlc_net_137:15 optlc_net_137:14 0.00280825 +7 optlc_net_137:13 optlc_net_137:12 0.003551339 +8 optlc_net_137:14 optlc_net_137:13 0.00341 +9 optlc_net_137:11 optlc_net_137:10 0.006531251 +10 optlc_net_137:12 optlc_net_137:11 0.0045 +11 optlc_net_137:8 mux_bottom_track_33\/mux_l2_in_1_:A0 0.152 +12 optlc_net_137:6 optlc_net_137:5 0.001725447 +13 optlc_net_137:7 optlc_net_137:6 0.0045 +14 optlc_net_137:5 mux_bottom_track_17\/mux_l1_in_3_:A0 0.152 +15 optlc_net_137:24 optlc_net_137:23 0.0045 +16 optlc_net_137:23 optlc_net_137:22 0.005160714 +17 optlc_net_137:23 optlc_net_137:16 0.0006071429 +18 optlc_net_137:21 optlc_net_137:20 0.007475447 +19 optlc_net_137:22 optlc_net_137:21 0.0045 +20 optlc_net_137:22 optlc_net_137:19 0.01270982 +21 optlc_net_137:20 mux_bottom_track_1\/mux_l2_in_3_:A0 0.152 +22 optlc_net_137:9 optlc_net_137:8 0.0001739865 +23 optlc_net_137:10 optlc_net_137:9 0.0002723215 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0009911754 //LENGTH 7.750 LUMPCC 0.0001153892 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_2_:X O *L 0 *C 34.785 89.155 +*I mux_top_track_2\/mux_l3_in_1_:A1 I *L 0.00198 *C 34.960 96.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 34.960 96.220 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 34.960 96.175 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 34.960 89.125 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 34.960 89.080 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 34.785 89.155 + +*CAP +0 mux_top_track_2\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.409733e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003610347 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003610347 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.003051e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.758907e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chany_top_in[0]:4 5.769459e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chany_top_in[0]:5 5.769459e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_2_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.51087e-05 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.006294643 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_2\/mux_l3_in_1_:A1 0.152 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001025995 //LENGTH 9.260 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_3_:X O *L 0 *C 78.025 82.960 +*I mux_top_track_8\/mux_l3_in_1_:A0 I *L 0.001631 *C 81.595 87.720 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 81.558 87.720 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 80.085 87.720 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 80.040 87.675 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 80.040 83.005 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 79.995 82.960 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 78.062 82.960 + +*CAP +0 mux_top_track_8\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001316692 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001316692 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002509595 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002509595 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001293689 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001293689 + +*RES +0 mux_top_track_8\/mux_l2_in_3_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725446 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004169643 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.001314732 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_8\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001709325 //LENGTH 14.420 LUMPCC 0.0004651212 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_3_:X O *L 0 *C 70.665 44.880 +*I mux_bottom_track_9\/mux_l3_in_1_:A0 I *L 0.001631 *C 78.375 39.100 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 78.338 39.100 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 72.725 39.100 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 72.680 39.145 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 72.680 44.835 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 72.635 44.880 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 70.703 44.880 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002561937 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002561937 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002536014 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002536014 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001113067 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001113067 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:6 5.106078e-05 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:7 5.106078e-05 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.404666e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.404666e-05 +12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 optlc_net_140:8 6.888236e-05 +13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 optlc_net_140:11 3.857079e-05 +14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 optlc_net_140:9 6.888236e-05 +15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 optlc_net_140:5 3.857079e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_3_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_9\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.005011161 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.005080358 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725446 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0] 0.001839735 //LENGTH 14.300 LUMPCC 0.0003934986 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_0_:X O *L 0 *C 50.425 113.220 +*I mux_top_track_4\/mux_l3_in_0_:A1 I *L 0.00198 *C 59.440 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 59.340 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 59.340 117.935 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 59.340 113.265 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 59.295 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 50.463 113.220 + +*CAP +0 mux_top_track_4\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 3.385244e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.0002734687 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0002734687 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.000431723 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.000431723 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size14_0_sram[1]:13 1.373568e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size14_0_sram[1]:15 6.956729e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size14_0_sram[1]:17 7.895854e-06 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size14_0_sram[1]:19 2.275369e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size14_0_sram[1]:14 1.373568e-05 +12 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size14_0_sram[1]:16 6.956729e-05 +13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size14_0_sram[1]:18 2.275369e-05 +14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size14_0_sram[1]:19 7.895854e-06 +15 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.279679e-05 +16 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.279679e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.004169643 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.007886161 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001086114 //LENGTH 8.720 LUMPCC 0.0001426238 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_5_:X O *L 0 *C 35.705 25.160 +*I mux_bottom_track_5\/mux_l2_in_2_:A0 I *L 0.001631 *C 35.595 17.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 35.595 17.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 35.880 17.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 35.880 17.385 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 35.880 25.115 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 35.880 25.160 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 35.705 25.160 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_5_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_2_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.93748e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.851073e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.000365675 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.000365675 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.740314e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.485175e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size14_1_sram[1]:24 7.303127e-06 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size14_1_sram[1]:25 5.051363e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size14_1_sram[1]:28 1.081568e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_tree_tapbuf_size14_1_sram[1]:22 2.679485e-06 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size14_1_sram[1]:21 7.303127e-06 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size14_1_sram[1]:24 5.051363e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size14_1_sram[1]:29 1.081568e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_tree_tapbuf_size14_1_sram[1]:23 2.679485e-06 + +*RES +0 mux_bottom_track_5\/mux_l1_in_5_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.51087e-05 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006901786 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001331522 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_5\/mux_l2_in_2_:A0 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0] 0.003358924 //LENGTH 25.785 LUMPCC 0.0005830896 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_2_:X O *L 0 *C 24.665 72.760 +*I mux_top_track_24\/mux_l2_in_1_:A1 I *L 0.00198 *C 35.980 85.340 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 35.943 85.340 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 35.420 85.340 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 35.420 85.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 26.725 85.680 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 26.680 85.635 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 26.680 72.805 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 26.635 72.760 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 24.703 72.760 + +*CAP +0 mux_top_track_24\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.282703e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.899409e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0004907437 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0004645766 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006827713 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0006827713 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001605753 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001605753 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_4_sram[0]:22 0.0001204592 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_4_sram[0]:23 2.56102e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_4_sram[0]:11 2.56102e-05 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_4_sram[0]:23 0.0001204592 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.044245e-07 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.274232e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.274232e-05 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.044245e-07 +18 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.222863e-05 +19 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.222863e-05 + +*RES +0 mux_top_track_24\/mux_l1_in_2_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_24\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.007763393 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.01145536 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001725447 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003035715 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004665179 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0] 0.00482461 //LENGTH 39.835 LUMPCC 0.0004521154 DR + +*CONN +*I mux_bottom_track_17\/mux_l3_in_0_:X O *L 0 *C 54.105 38.760 +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 53.285 9.710 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 53.285 9.710 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 53.775 9.860 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 53.820 9.905 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 53.820 11.515 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 53.865 11.560 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 57.915 11.560 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 *C 57.960 11.605 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 *C 57.960 20.355 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 *C 57.915 20.400 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 *C 53.865 20.400 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 *C 53.820 20.445 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 *C 53.820 38.715 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:14 *C 53.820 38.760 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:15 *C 54.105 38.760 + +*CAP +0 mux_bottom_track_17\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.698531e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.009922e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001303174 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001303174 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0002827128 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0002827128 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0004385297 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0004385297 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.0002683131 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0002683131 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0009339893 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0009339893 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:14 5.399208e-05 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:15 5.169412e-05 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 bottom_right_grid_pin_1_[0]:16 0.0001644909 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 bottom_right_grid_pin_1_[0]:17 0.0001644909 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.116813e-05 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.116813e-05 +20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.986568e-07 +21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.986568e-07 + +*RES +0 mux_bottom_track_17\/mux_l3_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:15 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:14 0.0001548913 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 0.0163125 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 0.003616072 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:11 0.0045 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0045 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0078125 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.003616072 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.0045 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0014375 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0004375 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001062289 //LENGTH 7.325 LUMPCC 0.000308942 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_3_:X O *L 0 *C 18.575 77.520 +*I mux_left_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 17.770 71.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 17.808 71.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 18.355 71.740 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 18.400 71.785 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 18.400 77.475 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 18.400 77.520 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 18.575 77.520 + +*CAP +0 mux_left_track_5\/mux_l1_in_3_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.485836e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.485836e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002253517 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0002253517 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.405137e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 6.687537e-05 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_5_sram[0]:19 3.842747e-05 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_5_sram[0]:26 1.405211e-06 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_5_sram[0]:20 3.842747e-05 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_5_sram[0]:25 1.405211e-06 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001146383 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001146383 + +*RES +0 mux_left_track_5\/mux_l1_in_3_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_5\/mux_l2_in_1_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004888393 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.005080358 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001903451 //LENGTH 15.880 LUMPCC 0.0001718962 DR + +*CONN +*I mux_left_track_7\/mux_l2_in_0_:X O *L 0 *C 52.155 55.420 +*I mux_left_track_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 43.605 61.540 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 43.643 61.540 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 44.620 61.540 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 44.620 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 51.015 60.860 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 51.060 60.815 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 51.060 55.465 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 51.105 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 52.117 55.420 + +*CAP +0 mux_left_track_7\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_7\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.310048e-05 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.848985e-05 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0004009515 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0003555621 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003065428 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003065428 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001041829 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001041829 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_6_sram[2]:8 4.227049e-05 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_6_sram[2]:9 4.36776e-05 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_6_sram[2]:9 4.227049e-05 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_6_sram[2]:8 4.36776e-05 + +*RES +0 mux_left_track_7\/mux_l2_in_0_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_7\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.005709821 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.004776786 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0009040179 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008727679 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0006071429 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001577872 //LENGTH 11.630 LUMPCC 0.0005897656 DR + +*CONN +*I mux_bottom_track_25\/mux_l3_in_0_:X O *L 0 *C 80.785 19.720 +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 82.590 12.075 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 82.553 12.180 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 80.085 12.240 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 80.040 12.285 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 80.040 19.675 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 80.085 19.720 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 80.748 19.720 + +*CAP +0 mux_bottom_track_25\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001336542 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001336542 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0002812187 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002812187 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 7.81803e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 7.81803e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_top_in[9]:6 8.513804e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_top_in[9]:5 8.513804e-05 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[12] 0.0002097448 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[12]:19 0.0002097448 + +*RES +0 mux_bottom_track_25\/mux_l3_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.002203125 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.006598215 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0005915179 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001109896 //LENGTH 8.845 LUMPCC 0.0002007748 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_2_:X O *L 0 *C 21.905 49.640 +*I mux_bottom_track_3\/mux_l3_in_1_:A1 I *L 0.00198 *C 25.400 45.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 25.363 45.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.045 45.220 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 23.000 45.265 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 23.000 49.595 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 22.955 49.640 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 21.943 49.640 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.93245e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.93245e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002635774 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002635774 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.065876e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 9.065876e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size9_0_sram[2]:4 0.0001003874 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size9_0_sram[2]:12 0.0001003874 + +*RES +0 mux_bottom_track_3\/mux_l2_in_2_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002069197 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003866072 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004012609 //LENGTH 2.260 LUMPCC 0 DR + +*CONN +*I mux_left_track_13\/mux_l2_in_1_:X O *L 0 *C 28.345 49.640 +*I mux_left_track_13\/mux_l3_in_0_:A0 I *L 0.001631 *C 28.810 48.280 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 28.810 48.280 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 28.520 48.280 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 28.520 48.325 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 28.520 49.595 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 28.520 49.640 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 28.345 49.640 + +*CAP +0 mux_left_track_13\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_13\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.440493e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.46657e-05 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 9.388248e-05 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.388248e-05 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.172326e-05 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.070204e-05 + +*RES +0 mux_left_track_13\/mux_l2_in_1_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_13\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001576087 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001133929 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001408196 //LENGTH 10.575 LUMPCC 0.0001301429 DR + +*CONN +*I mux_left_track_17\/mux_l1_in_0_:X O *L 0 *C 28.235 52.360 +*I mux_left_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.305 52.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.305 52.700 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 18.400 52.360 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.198 52.360 + +*CAP +0 mux_left_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.424739e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0006241867 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0005976194 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size3_0_sram[1]:4 6.507144e-05 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size3_0_sram[1]:3 6.507144e-05 + +*RES +0 mux_left_track_17\/mux_l1_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_17\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.008747769 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0] 0.005973884 //LENGTH 41.500 LUMPCC 0.001650538 DR + +*CONN +*I mux_left_track_21\/mux_l2_in_0_:X O *L 0 *C 25.015 74.120 +*I mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.220 58.630 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 21.680 74.120 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 5.220 58.630 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 5.060 59.160 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 3.220 59.160 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 3.220 59.160 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 3.220 63.183 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 3.228 63.240 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 22.060 63.240 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 22.080 63.248 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 22.080 74.112 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 22.080 74.120 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:13 *C 22.080 74.120 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:14 *C 22.125 74.120 +*N mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:15 *C 24.978 74.120 + +*CAP +0 mux_left_track_21\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.267917e-05 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.892973e-05 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001706399 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001759686 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0002350773 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001873629 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0009244055 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0009244055 +10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0005144835 +11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0005144835 +12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:12 7.267917e-05 +13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:13 3.501982e-05 +14 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.0002126058 +15 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.0002126058 +16 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 left_top_grid_pin_45_[0]:18 0.0002030408 +17 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 left_top_grid_pin_45_[0]:10 4.648681e-05 +18 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 left_top_grid_pin_45_[0]:16 0.000119023 +19 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 left_top_grid_pin_45_[0]:17 0.0002030408 +20 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 left_top_grid_pin_45_[0]:15 0.000119023 +21 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 left_top_grid_pin_45_[0]:16 4.648681e-05 +22 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0003382577 +23 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003382577 +24 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 ropt_net_149:5 0.0001184606 +25 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 ropt_net_149:4 0.0001184606 + +*RES +0 mux_left_track_21\/mux_l2_in_0_:X mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:15 0.152 +1 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:15 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:14 0.002546875 +2 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:14 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:13 0.0045 +3 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.00341 +4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.00341 +5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.69697e-05 +6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.001702183 +7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002950425 +8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.00341 +9 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.003591518 +10 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001642857 +12 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +13 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_21\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +14 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004732143 + +*END + +*D_NET ropt_net_171 0.00091291 //LENGTH 7.045 LUMPCC 0.0002035705 DR + +*CONN +*I FTB_8__7:X O *L 0 *C 50.140 8.840 +*I ropt_mt_inst_797:A I *L 0.001766 *C 48.760 4.080 +*N ropt_net_171:2 *C 48.760 4.080 +*N ropt_net_171:3 *C 48.790 4.110 +*N ropt_net_171:4 *C 48.805 4.420 +*N ropt_net_171:5 *C 49.220 4.420 +*N ropt_net_171:6 *C 49.220 8.795 +*N ropt_net_171:7 *C 49.265 8.840 +*N ropt_net_171:8 *C 50.102 8.840 + +*CAP +0 FTB_8__7:X 1e-06 +1 ropt_mt_inst_797:A 1e-06 +2 ropt_net_171:2 3.254157e-05 +3 ropt_net_171:3 2.379279e-05 +4 ropt_net_171:4 5.327749e-05 +5 ropt_net_171:5 0.0002360719 +6 ropt_net_171:6 0.0002065873 +7 ropt_net_171:7 7.753425e-05 +8 ropt_net_171:8 7.753425e-05 +9 ropt_net_171:6 chany_top_in[5]:15 4.198657e-05 +10 ropt_net_171:5 chany_top_in[5]:14 4.198657e-05 +11 ropt_net_171:6 chany_bottom_out[1]:6 5.684857e-05 +12 ropt_net_171:3 chany_bottom_out[1]:5 2.950094e-06 +13 ropt_net_171:4 chany_bottom_out[1]:6 2.950094e-06 +14 ropt_net_171:5 chany_bottom_out[1]:5 5.684857e-05 + +*RES +0 FTB_8__7:X ropt_net_171:8 0.152 +1 ropt_net_171:8 ropt_net_171:7 0.0007477679 +2 ropt_net_171:7 ropt_net_171:6 0.0045 +3 ropt_net_171:6 ropt_net_171:5 0.00390625 +4 ropt_net_171:2 ropt_mt_inst_797:A 0.152 +5 ropt_net_171:3 ropt_net_171:2 0.0045 +6 ropt_net_171:4 ropt_net_171:3 0.00019375 +7 ropt_net_171:5 ropt_net_171:4 0.0003705357 + +*END + +*D_NET ropt_net_157 0.002237758 //LENGTH 16.245 LUMPCC 8.044821e-05 DR + +*CONN +*I FTB_18__17:X O *L 0 *C 80.040 8.840 +*I ropt_mt_inst_782:A I *L 0.001766 *C 67.915 6.800 +*N ropt_net_157:2 *C 67.888 6.823 +*N ropt_net_157:3 *C 67.620 6.835 +*N ropt_net_157:4 *C 67.620 7.140 +*N ropt_net_157:5 *C 71.300 7.140 +*N ropt_net_157:6 *C 71.300 7.480 +*N ropt_net_157:7 *C 76.315 7.480 +*N ropt_net_157:8 *C 76.360 7.525 +*N ropt_net_157:9 *C 76.360 8.795 +*N ropt_net_157:10 *C 76.405 8.840 +*N ropt_net_157:11 *C 80.002 8.840 + +*CAP +0 FTB_18__17:X 1e-06 +1 ropt_mt_inst_782:A 1e-06 +2 ropt_net_157:2 1.805472e-05 +3 ropt_net_157:3 4.445916e-05 +4 ropt_net_157:4 0.0002776638 +5 ropt_net_157:5 0.0002769079 +6 ropt_net_157:6 0.000407742 +7 ropt_net_157:7 0.0003820934 +8 ropt_net_157:8 0.0001244407 +9 ropt_net_157:9 0.0001244407 +10 ropt_net_157:10 0.0002497536 +11 ropt_net_157:11 0.0002497536 +12 ropt_net_157:8 ropt_net_200:6 6.599708e-08 +13 ropt_net_157:10 ropt_net_200:9 1.032223e-05 +14 ropt_net_157:10 ropt_net_200:6 2.983588e-05 +15 ropt_net_157:9 ropt_net_200:7 6.599708e-08 +16 ropt_net_157:11 ropt_net_200:8 1.032223e-05 +17 ropt_net_157:11 ropt_net_200:5 2.983588e-05 + +*RES +0 FTB_18__17:X ropt_net_157:11 0.152 +1 ropt_net_157:2 ropt_mt_inst_782:A 0.152 +2 ropt_net_157:7 ropt_net_157:6 0.004477679 +3 ropt_net_157:8 ropt_net_157:7 0.0045 +4 ropt_net_157:10 ropt_net_157:9 0.0045 +5 ropt_net_157:9 ropt_net_157:8 0.001133929 +6 ropt_net_157:11 ropt_net_157:10 0.003212054 +7 ropt_net_157:3 ropt_net_157:2 0.0001807433 +8 ropt_net_157:4 ropt_net_157:3 0.0002723215 +9 ropt_net_157:5 ropt_net_157:4 0.003285714 +10 ropt_net_157:6 ropt_net_157:5 0.0003035715 + +*END + +*D_NET ropt_net_189 0.0009336944 //LENGTH 6.715 LUMPCC 0.0002244734 DR + +*CONN +*I ropt_mt_inst_784:X O *L 0 *C 80.695 124.440 +*I ropt_mt_inst_819:A I *L 0.001767 *C 77.740 126.480 +*N ropt_net_189:2 *C 77.778 126.480 +*N ropt_net_189:3 *C 78.155 126.480 +*N ropt_net_189:4 *C 78.200 126.435 +*N ropt_net_189:5 *C 78.200 125.845 +*N ropt_net_189:6 *C 78.245 125.800 +*N ropt_net_189:7 *C 80.040 125.800 +*N ropt_net_189:8 *C 80.040 125.755 +*N ropt_net_189:9 *C 80.040 124.485 +*N ropt_net_189:10 *C 80.085 124.440 +*N ropt_net_189:11 *C 80.657 124.440 + +*CAP +0 ropt_mt_inst_784:X 1e-06 +1 ropt_mt_inst_819:A 1e-06 +2 ropt_net_189:2 5.078612e-05 +3 ropt_net_189:3 5.078612e-05 +4 ropt_net_189:4 6.6033e-05 +5 ropt_net_189:5 6.6033e-05 +6 ropt_net_189:6 0.0001295991 +7 ropt_net_189:7 0.0001646213 +8 ropt_net_189:8 2.675442e-05 +9 ropt_net_189:9 2.675442e-05 +10 ropt_net_189:10 6.292671e-05 +11 ropt_net_189:11 6.292671e-05 +12 ropt_net_189:4 chany_top_in[0] 2.891005e-07 +13 ropt_net_189:6 chany_top_in[0]:25 1.631826e-05 +14 ropt_net_189:5 chany_top_in[0]:26 2.891005e-07 +15 ropt_net_189:7 chany_top_in[0]:26 1.631826e-05 +16 ropt_net_189:8 chany_top_in[0] 4.471487e-05 +17 ropt_net_189:9 chany_top_in[0]:26 4.471487e-05 +18 ropt_net_189:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 2.534417e-06 +19 ropt_net_189:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.665186e-06 +20 ropt_net_189:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 2.534417e-06 +21 ropt_net_189:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:3 3.665186e-06 +22 ropt_net_189:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:5 4.471487e-05 +23 ropt_net_189:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_6_X[0]:6 4.471487e-05 + +*RES +0 ropt_mt_inst_784:X ropt_net_189:11 0.152 +1 ropt_net_189:2 ropt_mt_inst_819:A 0.152 +2 ropt_net_189:3 ropt_net_189:2 0.0003370536 +3 ropt_net_189:4 ropt_net_189:3 0.0045 +4 ropt_net_189:6 ropt_net_189:5 0.0045 +5 ropt_net_189:5 ropt_net_189:4 0.0005267857 +6 ropt_net_189:7 ropt_net_189:6 0.001602679 +7 ropt_net_189:8 ropt_net_189:7 0.0045 +8 ropt_net_189:10 ropt_net_189:9 0.0045 +9 ropt_net_189:9 ropt_net_189:8 0.001133929 +10 ropt_net_189:11 ropt_net_189:10 0.0005111607 + +*END + +*D_NET chany_top_out[6] 0.001606879 //LENGTH 12.140 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_794:X O *L 0 *C 72.875 121.720 +*P chany_top_out[6] O *L 0.7423 *C 70.380 129.270 +*N chany_top_out[6]:2 *C 70.380 128.520 +*N chany_top_out[6]:3 *C 69.920 128.520 +*N chany_top_out[6]:4 *C 69.920 123.125 +*N chany_top_out[6]:5 *C 69.965 123.080 +*N chany_top_out[6]:6 *C 72.635 123.080 +*N chany_top_out[6]:7 *C 72.680 123.035 +*N chany_top_out[6]:8 *C 72.680 121.765 +*N chany_top_out[6]:9 *C 72.680 121.720 +*N chany_top_out[6]:10 *C 72.875 121.720 + +*CAP +0 ropt_mt_inst_794:X 1e-06 +1 chany_top_out[6] 5.776932e-05 +2 chany_top_out[6]:2 8.637666e-05 +3 chany_top_out[6]:3 0.0003676294 +4 chany_top_out[6]:4 0.000339022 +5 chany_top_out[6]:5 0.0002099541 +6 chany_top_out[6]:6 0.0002099541 +7 chany_top_out[6]:7 0.0001072633 +8 chany_top_out[6]:8 0.0001072633 +9 chany_top_out[6]:9 6.188994e-05 +10 chany_top_out[6]:10 5.875715e-05 + +*RES +0 ropt_mt_inst_794:X chany_top_out[6]:10 0.152 +1 chany_top_out[6]:10 chany_top_out[6]:9 0.0001059783 +2 chany_top_out[6]:9 chany_top_out[6]:8 0.0045 +3 chany_top_out[6]:8 chany_top_out[6]:7 0.001133929 +4 chany_top_out[6]:6 chany_top_out[6]:5 0.002383929 +5 chany_top_out[6]:7 chany_top_out[6]:6 0.0045 +6 chany_top_out[6]:5 chany_top_out[6]:4 0.0045 +7 chany_top_out[6]:4 chany_top_out[6]:3 0.004816964 +8 chany_top_out[6]:3 chany_top_out[6]:2 0.0004107143 +9 chany_top_out[6]:2 chany_top_out[6] 0.000669643 + +*END + +*D_NET chany_bottom_out[13] 0.001263219 //LENGTH 7.725 LUMPCC 0.0001695852 DR + +*CONN +*I ropt_mt_inst_801:X O *L 0 *C 66.435 3.400 +*P chany_bottom_out[13] O *L 0.7423 *C 61.640 1.290 +*N chany_bottom_out[13]:2 *C 61.640 3.343 +*N chany_bottom_out[13]:3 *C 61.648 3.400 +*N chany_bottom_out[13]:4 *C 64.392 3.400 +*N chany_bottom_out[13]:5 *C 64.400 3.400 +*N chany_bottom_out[13]:6 *C 64.445 3.400 +*N chany_bottom_out[13]:7 *C 66.398 3.400 + +*CAP +0 ropt_mt_inst_801:X 1e-06 +1 chany_bottom_out[13] 0.000144213 +2 chany_bottom_out[13]:2 0.000144213 +3 chany_bottom_out[13]:3 0.0002754647 +4 chany_bottom_out[13]:4 0.0002754647 +5 chany_bottom_out[13]:5 3.54801e-05 +6 chany_bottom_out[13]:6 0.0001088991 +7 chany_bottom_out[13]:7 0.0001088991 +8 chany_bottom_out[13] ropt_net_166:4 3.506963e-08 +9 chany_bottom_out[13]:7 ropt_net_166:6 8.475751e-05 +10 chany_bottom_out[13]:6 ropt_net_166:5 8.475751e-05 +11 chany_bottom_out[13]:2 ropt_net_166:3 3.506963e-08 + +*RES +0 ropt_mt_inst_801:X chany_bottom_out[13]:7 0.152 +1 chany_bottom_out[13]:7 chany_bottom_out[13]:6 0.001743304 +2 chany_bottom_out[13]:6 chany_bottom_out[13]:5 0.0045 +3 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.00341 +4 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.00043005 +5 chany_bottom_out[13]:2 chany_bottom_out[13] 0.001832589 +6 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.00341 + +*END + +*D_NET chany_top_out[18] 0.0007209423 //LENGTH 5.990 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_824:X O *L 0 *C 99.095 127.160 +*P chany_top_out[18] O *L 0.7423 *C 95.680 129.270 +*N chany_top_out[18]:2 *C 95.680 127.205 +*N chany_top_out[18]:3 *C 95.725 127.160 +*N chany_top_out[18]:4 *C 99.058 127.160 + +*CAP +0 ropt_mt_inst_824:X 1e-06 +1 chany_top_out[18] 0.0001161368 +2 chany_top_out[18]:2 0.0001161368 +3 chany_top_out[18]:3 0.0002438343 +4 chany_top_out[18]:4 0.0002438343 + +*RES +0 ropt_mt_inst_824:X chany_top_out[18]:4 0.152 +1 chany_top_out[18]:4 chany_top_out[18]:3 0.002975447 +2 chany_top_out[18]:3 chany_top_out[18]:2 0.0045 +3 chany_top_out[18]:2 chany_top_out[18] 0.00184375 + +*END + +*D_NET chanx_left_out[17] 0.0008438492 //LENGTH 6.335 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_840:X O *L 0 *C 7.095 88.400 +*P chanx_left_out[17] O *L 0.7423 *C 1.230 88.400 +*N chanx_left_out[17]:2 *C 4.593 88.400 +*N chanx_left_out[17]:3 *C 4.600 88.400 +*N chanx_left_out[17]:4 *C 4.645 88.400 +*N chanx_left_out[17]:5 *C 7.058 88.400 + +*CAP +0 ropt_mt_inst_840:X 1e-06 +1 chanx_left_out[17] 0.0002399761 +2 chanx_left_out[17]:2 0.0002399761 +3 chanx_left_out[17]:3 3.477825e-05 +4 chanx_left_out[17]:4 0.0001640594 +5 chanx_left_out[17]:5 0.0001640594 + +*RES +0 ropt_mt_inst_840:X chanx_left_out[17]:5 0.152 +1 chanx_left_out[17]:5 chanx_left_out[17]:4 0.002154018 +2 chanx_left_out[17]:4 chanx_left_out[17]:3 0.0045 +3 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +4 chanx_left_out[17]:2 chanx_left_out[17] 0.0005267916 + +*END + +*D_NET chany_bottom_out[14] 0.0008857771 //LENGTH 7.800 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_846:X O *L 0 *C 102.315 3.400 +*P chany_bottom_out[14] O *L 0.7423 *C 97.520 1.290 +*N chany_bottom_out[14]:2 *C 97.520 1.655 +*N chany_bottom_out[14]:3 *C 97.565 1.700 +*N chany_bottom_out[14]:4 *C 102.075 1.700 +*N chany_bottom_out[14]:5 *C 102.120 1.745 +*N chany_bottom_out[14]:6 *C 102.120 3.355 +*N chany_bottom_out[14]:7 *C 102.120 3.400 +*N chany_bottom_out[14]:8 *C 102.315 3.400 + +*CAP +0 ropt_mt_inst_846:X 1e-06 +1 chany_bottom_out[14] 3.649791e-05 +2 chany_bottom_out[14]:2 3.649791e-05 +3 chany_bottom_out[14]:3 0.0002564109 +4 chany_bottom_out[14]:4 0.0002564109 +5 chany_bottom_out[14]:5 9.649296e-05 +6 chany_bottom_out[14]:6 9.649296e-05 +7 chany_bottom_out[14]:7 5.061012e-05 +8 chany_bottom_out[14]:8 5.536354e-05 + +*RES +0 ropt_mt_inst_846:X chany_bottom_out[14]:8 0.152 +1 chany_bottom_out[14]:8 chany_bottom_out[14]:7 0.0001059783 +2 chany_bottom_out[14]:7 chany_bottom_out[14]:6 0.0045 +3 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.0014375 +4 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.004026786 +5 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.0045 +6 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.0045 +7 chany_bottom_out[14]:2 chany_bottom_out[14] 0.0003258929 + +*END + +*D_NET chany_top_in[14] 0.01963299 //LENGTH 151.305 LUMPCC 0.00830455 DR + +*CONN +*P chany_top_in[14] I *L 0.29796 *C 54.740 129.270 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 44.950 6.460 +*I FTB_14__13:A I *L 0.001776 *C 50.600 6.800 +*I mux_left_track_19\/mux_l1_in_0_:A1 I *L 0.00198 *C 37.165 58.140 +*N chany_top_in[14]:4 *C 37.203 58.140 +*N chany_top_in[14]:5 *C 40.895 58.140 +*N chany_top_in[14]:6 *C 40.940 58.140 +*N chany_top_in[14]:7 *C 40.940 58.480 +*N chany_top_in[14]:8 *C 40.948 58.480 +*N chany_top_in[14]:9 *C 45.600 6.120 +*N chany_top_in[14]:10 *C 50.600 6.800 +*N chany_top_in[14]:11 *C 50.600 7.140 +*N chany_top_in[14]:12 *C 46.920 7.140 +*N chany_top_in[14]:13 *C 46.920 6.460 +*N chany_top_in[14]:14 *C 44.988 6.460 +*N chany_top_in[14]:15 *C 46.000 6.460 +*N chany_top_in[14]:16 *C 46.000 6.460 +*N chany_top_in[14]:17 *C 46.000 6.120 +*N chany_top_in[14]:18 *C 46.000 6.120 +*N chany_top_in[14]:19 *C 46.000 6.128 +*N chany_top_in[14]:20 *C 46.000 58.473 +*N chany_top_in[14]:21 *C 46.000 58.480 +*N chany_top_in[14]:22 *C 51.500 58.480 +*N chany_top_in[14]:23 *C 51.520 58.488 +*N chany_top_in[14]:24 *C 51.520 108.315 +*N chany_top_in[14]:25 *C 51.520 126.473 +*N chany_top_in[14]:26 *C 51.540 126.480 +*N chany_top_in[14]:27 *C 54.733 126.480 +*N chany_top_in[14]:28 *C 54.740 126.538 + +*CAP +0 chany_top_in[14] 0.0001166605 +1 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +2 FTB_14__13:A 1e-06 +3 mux_left_track_19\/mux_l1_in_0_:A1 1e-06 +4 chany_top_in[14]:4 0.0002370434 +5 chany_top_in[14]:5 0.0002370434 +6 chany_top_in[14]:6 5.606446e-05 +7 chany_top_in[14]:7 5.937296e-05 +8 chany_top_in[14]:8 0.0003317431 +9 chany_top_in[14]:9 6.456914e-05 +10 chany_top_in[14]:10 5.690454e-05 +11 chany_top_in[14]:11 0.0001872822 +12 chany_top_in[14]:12 0.0002027852 +13 chany_top_in[14]:13 0.0001190441 +14 chany_top_in[14]:14 8.517081e-05 +15 chany_top_in[14]:15 0.0001946467 +16 chany_top_in[14]:16 5.424725e-05 +17 chany_top_in[14]:17 5.850708e-05 +18 chany_top_in[14]:18 6.456914e-05 +19 chany_top_in[14]:19 0.002052689 +20 chany_top_in[14]:20 0.002052689 +21 chany_top_in[14]:21 0.0007086821 +22 chany_top_in[14]:22 0.000376939 +23 chany_top_in[14]:23 0.001149719 +24 chany_top_in[14]:24 0.001725049 +25 chany_top_in[14]:25 0.0005753305 +26 chany_top_in[14]:26 0.0002210125 +27 chany_top_in[14]:27 0.0002210125 +28 chany_top_in[14]:28 0.0001166605 +29 chany_top_in[14]:19 chany_top_in[4]:10 0.0009900054 +30 chany_top_in[14]:19 chany_top_in[4]:22 9.204263e-05 +31 chany_top_in[14]:21 chany_top_in[4]:12 1.011167e-05 +32 chany_top_in[14]:21 chany_top_in[4]:21 6.199253e-05 +33 chany_top_in[14]:20 chany_top_in[4]:11 0.0009900054 +34 chany_top_in[14]:20 chany_top_in[4]:29 9.204263e-05 +35 chany_top_in[14]:8 chany_top_in[4]:20 3.96809e-05 +36 chany_top_in[14]:8 chany_top_in[4]:21 1.011167e-05 +37 chany_top_in[14]:22 chany_top_in[4]:12 2.231163e-05 +38 chany_top_in[14]:26 chany_top_in[4]:31 4.515351e-05 +39 chany_top_in[14]:25 chany_top_in[4]:30 4.701439e-06 +40 chany_top_in[14]:27 chany_top_in[4]:32 4.515351e-05 +41 chany_top_in[14]:24 chany_top_in[4]:29 4.701439e-06 +42 chany_top_in[14]:15 chany_top_in[5]:11 9.914033e-06 +43 chany_top_in[14]:15 chany_top_in[5]:12 2.440084e-06 +44 chany_top_in[14]:15 chany_top_in[5]:13 1.306307e-06 +45 chany_top_in[14]:19 chany_top_in[5]:17 1.411224e-05 +46 chany_top_in[14]:20 chany_top_in[5]:18 1.411224e-05 +47 chany_top_in[14]:14 chany_top_in[5]:10 9.914033e-06 +48 chany_top_in[14]:14 chany_top_in[5]:12 1.306307e-06 +49 chany_top_in[14]:23 chany_top_in[5]:17 4.773683e-05 +50 chany_top_in[14]:23 chany_top_in[5]:18 0.0001052323 +51 chany_top_in[14]:23 chany_top_in[5]:24 0.0008802768 +52 chany_top_in[14]:26 chany_top_in[5]:27 3.230049e-05 +53 chany_top_in[14]:25 chany_top_in[5]:25 0.0001740629 +54 chany_top_in[14]:25 chany_top_in[5]:26 0.0001473897 +55 chany_top_in[14]:27 chany_top_in[5]:28 3.230049e-05 +56 chany_top_in[14]:13 chany_top_in[5]:11 7.057935e-07 +57 chany_top_in[14]:13 chany_top_in[5]:13 2.440084e-06 +58 chany_top_in[14]:12 chany_top_in[5]:12 0.0001059046 +59 chany_top_in[14]:12 chany_top_in[5]:13 3.686417e-05 +60 chany_top_in[14]:11 chany_top_in[5]:9 3.686417e-05 +61 chany_top_in[14]:11 chany_top_in[5]:13 0.0001051988 +62 chany_top_in[14]:24 chany_top_in[5]:18 4.773683e-05 +63 chany_top_in[14]:24 chany_top_in[5]:24 0.0002792953 +64 chany_top_in[14]:24 chany_top_in[5]:25 0.001027666 +65 chany_top_in[14] chany_top_in[15] 4.115813e-05 +66 chany_top_in[14]:21 chany_top_in[15]:13 1.712631e-05 +67 chany_top_in[14]:21 chany_top_in[15]:14 7.502507e-07 +68 chany_top_in[14]:8 chany_top_in[15]:13 7.502507e-07 +69 chany_top_in[14]:22 chany_top_in[15]:14 1.712631e-05 +70 chany_top_in[14]:23 chany_top_in[15]:15 0.0009599623 +71 chany_top_in[14]:23 chany_top_in[15]:16 7.328357e-05 +72 chany_top_in[14]:25 chany_top_in[15]:17 0.0002984474 +73 chany_top_in[14]:28 chany_top_in[15]:20 4.115813e-05 +74 chany_top_in[14]:24 chany_top_in[15]:17 7.328357e-05 +75 chany_top_in[14]:24 chany_top_in[15]:16 0.00125841 + +*RES +0 chany_top_in[14] chany_top_in[14]:28 0.002439732 +1 chany_top_in[14]:10 FTB_14__13:A 0.152 +2 chany_top_in[14]:15 chany_top_in[14]:14 0.0009040179 +3 chany_top_in[14]:15 chany_top_in[14]:13 0.0008214285 +4 chany_top_in[14]:16 chany_top_in[14]:15 0.0045 +5 chany_top_in[14]:17 chany_top_in[14]:16 0.0001634615 +6 chany_top_in[14]:18 chany_top_in[14]:17 0.00341 +7 chany_top_in[14]:18 chany_top_in[14]:9 5.69697e-05 +8 chany_top_in[14]:19 chany_top_in[14]:18 0.00341 +9 chany_top_in[14]:21 chany_top_in[14]:20 0.00341 +10 chany_top_in[14]:21 chany_top_in[14]:8 0.0007915583 +11 chany_top_in[14]:20 chany_top_in[14]:19 0.008200716 +12 chany_top_in[14]:14 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +13 chany_top_in[14]:7 chany_top_in[14]:6 0.0001634615 +14 chany_top_in[14]:8 chany_top_in[14]:7 0.00341 +15 chany_top_in[14]:5 chany_top_in[14]:4 0.003296875 +16 chany_top_in[14]:6 chany_top_in[14]:5 0.0045 +17 chany_top_in[14]:4 mux_left_track_19\/mux_l1_in_0_:A1 0.152 +18 chany_top_in[14]:22 chany_top_in[14]:21 0.0008616666 +19 chany_top_in[14]:23 chany_top_in[14]:22 0.00341 +20 chany_top_in[14]:26 chany_top_in[14]:25 0.00341 +21 chany_top_in[14]:25 chany_top_in[14]:24 0.002844675 +22 chany_top_in[14]:28 chany_top_in[14]:27 0.00341 +23 chany_top_in[14]:27 chany_top_in[14]:26 0.0005001583 +24 chany_top_in[14]:13 chany_top_in[14]:12 0.0006071429 +25 chany_top_in[14]:12 chany_top_in[14]:11 0.003285714 +26 chany_top_in[14]:11 chany_top_in[14]:10 0.0003035715 +27 chany_top_in[14]:24 chany_top_in[14]:23 0.007806308 + +*END + +*D_NET top_left_grid_pin_40_[0] 0.00611237 //LENGTH 45.315 LUMPCC 0.0001406217 DR + +*CONN +*P top_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 122.400 +*I mux_top_track_4\/mux_l1_in_3_:A1 I *L 0.00198 *C 45.540 110.500 +*I mux_top_track_24\/mux_l1_in_0_:A0 I *L 0.001631 *C 40.800 107.705 +*I mux_top_track_0\/mux_l1_in_1_:A0 I *L 0.001631 *C 47.670 124.100 +*N top_left_grid_pin_40_[0]:4 *C 47.633 124.100 +*N top_left_grid_pin_40_[0]:5 *C 46.505 124.100 +*N top_left_grid_pin_40_[0]:6 *C 46.460 124.055 +*N top_left_grid_pin_40_[0]:7 *C 40.837 107.765 +*N top_left_grid_pin_40_[0]:8 *C 45.540 110.500 +*N top_left_grid_pin_40_[0]:9 *C 45.540 110.455 +*N top_left_grid_pin_40_[0]:10 *C 45.540 107.825 +*N top_left_grid_pin_40_[0]:11 *C 45.540 107.780 +*N top_left_grid_pin_40_[0]:12 *C 46.415 107.780 +*N top_left_grid_pin_40_[0]:13 *C 46.460 107.825 +*N top_left_grid_pin_40_[0]:14 *C 46.460 123.080 +*N top_left_grid_pin_40_[0]:15 *C 46.453 123.080 +*N top_left_grid_pin_40_[0]:16 *C 38.640 123.080 +*N top_left_grid_pin_40_[0]:17 *C 38.640 122.400 + +*CAP +0 top_left_grid_pin_40_[0] 0.0005952456 +1 mux_top_track_4\/mux_l1_in_3_:A1 1e-06 +2 mux_top_track_24\/mux_l1_in_0_:A0 1e-06 +3 mux_top_track_0\/mux_l1_in_1_:A0 1e-06 +4 top_left_grid_pin_40_[0]:4 0.0001388247 +5 top_left_grid_pin_40_[0]:5 0.0001388247 +6 top_left_grid_pin_40_[0]:6 7.81148e-05 +7 top_left_grid_pin_40_[0]:7 0.0003040761 +8 top_left_grid_pin_40_[0]:8 3.525455e-05 +9 top_left_grid_pin_40_[0]:9 0.000192709 +10 top_left_grid_pin_40_[0]:10 0.000192709 +11 top_left_grid_pin_40_[0]:11 0.0004008821 +12 top_left_grid_pin_40_[0]:12 6.155152e-05 +13 top_left_grid_pin_40_[0]:13 0.0008669879 +14 top_left_grid_pin_40_[0]:14 0.000984144 +15 top_left_grid_pin_40_[0]:15 0.0006394226 +16 top_left_grid_pin_40_[0]:16 0.0006920893 +17 top_left_grid_pin_40_[0]:17 0.0006479123 +18 top_left_grid_pin_40_[0]:14 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.031085e-05 +19 top_left_grid_pin_40_[0]:13 mux_top_track_4/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.031085e-05 + +*RES +0 top_left_grid_pin_40_[0] top_left_grid_pin_40_[0]:17 0.001392767 +1 top_left_grid_pin_40_[0]:8 mux_top_track_4\/mux_l1_in_3_:A1 0.152 +2 top_left_grid_pin_40_[0]:9 top_left_grid_pin_40_[0]:8 0.0045 +3 top_left_grid_pin_40_[0]:11 top_left_grid_pin_40_[0]:10 0.0045 +4 top_left_grid_pin_40_[0]:11 top_left_grid_pin_40_[0]:7 0.004198661 +5 top_left_grid_pin_40_[0]:10 top_left_grid_pin_40_[0]:9 0.002348214 +6 top_left_grid_pin_40_[0]:14 top_left_grid_pin_40_[0]:13 0.01362054 +7 top_left_grid_pin_40_[0]:14 top_left_grid_pin_40_[0]:6 0.0008705358 +8 top_left_grid_pin_40_[0]:15 top_left_grid_pin_40_[0]:14 0.00341 +9 top_left_grid_pin_40_[0]:12 top_left_grid_pin_40_[0]:11 0.00078125 +10 top_left_grid_pin_40_[0]:13 top_left_grid_pin_40_[0]:12 0.0045 +11 top_left_grid_pin_40_[0]:7 mux_top_track_24\/mux_l1_in_0_:A0 0.152 +12 top_left_grid_pin_40_[0]:5 top_left_grid_pin_40_[0]:4 0.001006696 +13 top_left_grid_pin_40_[0]:6 top_left_grid_pin_40_[0]:5 0.0045 +14 top_left_grid_pin_40_[0]:4 mux_top_track_0\/mux_l1_in_1_:A0 0.152 +15 top_left_grid_pin_40_[0]:17 top_left_grid_pin_40_[0]:16 0.0001065333 +16 top_left_grid_pin_40_[0]:16 top_left_grid_pin_40_[0]:15 0.001223958 + +*END + +*D_NET chany_bottom_in[7] 0.00607078 //LENGTH 57.145 LUMPCC 0.001848471 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 87.400 1.290 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 83.090 53.380 +*N chany_bottom_in[7]:2 *C 83.127 53.380 +*N chany_bottom_in[7]:3 *C 83.720 53.380 +*N chany_bottom_in[7]:4 *C 83.720 52.700 +*N chany_bottom_in[7]:5 *C 87.355 52.700 +*N chany_bottom_in[7]:6 *C 87.400 52.655 + +*CAP +0 chany_bottom_in[7] 0.001793208 +1 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +2 chany_bottom_in[7]:2 5.339997e-05 +3 chany_bottom_in[7]:3 9.416298e-05 +4 chany_bottom_in[7]:4 0.0002640463 +5 chany_bottom_in[7]:5 0.0002232833 +6 chany_bottom_in[7]:6 0.001793208 +7 chany_bottom_in[7] chany_bottom_in[3] 0.0005764258 +8 chany_bottom_in[7]:6 chany_bottom_in[3]:9 0.0005764258 +9 chany_bottom_in[7] chany_bottom_in[11] 0.0003261388 +10 chany_bottom_in[7] chany_bottom_in[11]:5 2.167078e-05 +11 chany_bottom_in[7]:6 chany_bottom_in[11]:4 2.167078e-05 +12 chany_bottom_in[7]:6 chany_bottom_in[11]:8 0.0003261388 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:6 0.04586161 +1 chany_bottom_in[7]:2 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +2 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.003245536 +3 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.0045 +4 chany_bottom_in[7]:3 chany_bottom_in[7]:2 0.0005290179 +5 chany_bottom_in[7]:4 chany_bottom_in[7]:3 0.0006071429 + +*END + +*D_NET bottom_right_grid_pin_1_[0] 0.01441867 //LENGTH 104.460 LUMPCC 0.002066601 DR + +*CONN +*P bottom_right_grid_pin_1_[0] I *L 0.29796 *C 110.860 1.290 +*I mux_bottom_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 57.040 18.020 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 68.255 17.340 +*I mux_bottom_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 40.845 3.740 +*N bottom_right_grid_pin_1_[0]:4 *C 40.845 3.740 +*N bottom_right_grid_pin_1_[0]:5 *C 40.940 3.400 +*N bottom_right_grid_pin_1_[0]:6 *C 55.615 3.400 +*N bottom_right_grid_pin_1_[0]:7 *C 55.660 3.445 +*N bottom_right_grid_pin_1_[0]:8 *C 55.660 4.715 +*N bottom_right_grid_pin_1_[0]:9 *C 55.705 4.760 +*N bottom_right_grid_pin_1_[0]:10 *C 68.218 17.340 +*N bottom_right_grid_pin_1_[0]:11 *C 59.800 17.340 +*N bottom_right_grid_pin_1_[0]:12 *C 59.800 17.680 +*N bottom_right_grid_pin_1_[0]:13 *C 57.078 18.020 +*N bottom_right_grid_pin_1_[0]:14 *C 58.420 18.020 +*N bottom_right_grid_pin_1_[0]:15 *C 58.420 17.680 +*N bottom_right_grid_pin_1_[0]:16 *C 58.420 17.635 +*N bottom_right_grid_pin_1_[0]:17 *C 58.420 9.225 +*N bottom_right_grid_pin_1_[0]:18 *C 58.375 9.180 +*N bottom_right_grid_pin_1_[0]:19 *C 57.085 9.180 +*N bottom_right_grid_pin_1_[0]:20 *C 57.040 9.135 +*N bottom_right_grid_pin_1_[0]:21 *C 57.040 4.805 +*N bottom_right_grid_pin_1_[0]:22 *C 57.040 4.760 +*N bottom_right_grid_pin_1_[0]:23 *C 110.815 4.760 +*N bottom_right_grid_pin_1_[0]:24 *C 110.860 4.715 + +*CAP +0 bottom_right_grid_pin_1_[0] 0.0001630264 +1 mux_bottom_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_5\/mux_l1_in_1_:A1 1e-06 +4 bottom_right_grid_pin_1_[0]:4 5.132399e-05 +5 bottom_right_grid_pin_1_[0]:5 0.001049764 +6 bottom_right_grid_pin_1_[0]:6 0.001024415 +7 bottom_right_grid_pin_1_[0]:7 9.689953e-05 +8 bottom_right_grid_pin_1_[0]:8 9.689953e-05 +9 bottom_right_grid_pin_1_[0]:9 0.000127926 +10 bottom_right_grid_pin_1_[0]:10 0.0004754234 +11 bottom_right_grid_pin_1_[0]:11 0.0005029222 +12 bottom_right_grid_pin_1_[0]:12 0.0001155392 +13 bottom_right_grid_pin_1_[0]:13 9.381857e-05 +14 bottom_right_grid_pin_1_[0]:14 0.0001237025 +15 bottom_right_grid_pin_1_[0]:15 0.0001179243 +16 bottom_right_grid_pin_1_[0]:16 0.0002411713 +17 bottom_right_grid_pin_1_[0]:17 0.0002411713 +18 bottom_right_grid_pin_1_[0]:18 0.0001145694 +19 bottom_right_grid_pin_1_[0]:19 0.0001145694 +20 bottom_right_grid_pin_1_[0]:20 0.0002871684 +21 bottom_right_grid_pin_1_[0]:21 0.0002871684 +22 bottom_right_grid_pin_1_[0]:22 0.00351266 +23 bottom_right_grid_pin_1_[0]:23 0.003347982 +24 bottom_right_grid_pin_1_[0]:24 0.0001630264 +25 bottom_right_grid_pin_1_[0]:17 bottom_left_grid_pin_35_[0]:10 0.0002070567 +26 bottom_right_grid_pin_1_[0]:17 bottom_left_grid_pin_35_[0]:9 2.21362e-05 +27 bottom_right_grid_pin_1_[0]:15 bottom_left_grid_pin_35_[0]:5 4.13069e-05 +28 bottom_right_grid_pin_1_[0]:15 bottom_left_grid_pin_35_[0]:7 3.819919e-06 +29 bottom_right_grid_pin_1_[0]:16 bottom_left_grid_pin_35_[0]:6 2.21362e-05 +30 bottom_right_grid_pin_1_[0]:16 bottom_left_grid_pin_35_[0]:9 0.0002070567 +31 bottom_right_grid_pin_1_[0]:13 bottom_left_grid_pin_35_[0]:7 1.37019e-05 +32 bottom_right_grid_pin_1_[0]:10 bottom_left_grid_pin_35_[0]:4 3.493429e-05 +33 bottom_right_grid_pin_1_[0]:14 bottom_left_grid_pin_35_[0]:8 1.37019e-05 +34 bottom_right_grid_pin_1_[0]:12 bottom_left_grid_pin_35_[0]:4 4.13069e-05 +35 bottom_right_grid_pin_1_[0]:12 bottom_left_grid_pin_35_[0]:8 3.819919e-06 +36 bottom_right_grid_pin_1_[0]:11 bottom_left_grid_pin_35_[0]:5 3.493429e-05 +37 bottom_right_grid_pin_1_[0]:17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:8 0.0001644909 +38 bottom_right_grid_pin_1_[0]:16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_6_X[0]:9 0.0001644909 +39 bottom_right_grid_pin_1_[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001387456 +40 bottom_right_grid_pin_1_[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001387456 +41 bottom_right_grid_pin_1_[0]:22 ropt_net_180:2 8.760282e-06 +42 bottom_right_grid_pin_1_[0]:22 ropt_net_180:4 0.0001241871 +43 bottom_right_grid_pin_1_[0]:23 ropt_net_180:5 0.0001241871 +44 bottom_right_grid_pin_1_[0]:23 ropt_net_180:3 8.760282e-06 +45 bottom_right_grid_pin_1_[0]:8 ropt_net_198:3 1.75376e-07 +46 bottom_right_grid_pin_1_[0]:6 ropt_net_198:5 4.276652e-05 +47 bottom_right_grid_pin_1_[0]:6 ropt_net_198:7 5.695994e-07 +48 bottom_right_grid_pin_1_[0]:7 ropt_net_198:4 1.75376e-07 +49 bottom_right_grid_pin_1_[0]:5 ropt_net_198:8 5.695994e-07 +50 bottom_right_grid_pin_1_[0]:5 ropt_net_198:6 4.276652e-05 +51 bottom_right_grid_pin_1_[0]:22 ropt_net_182:2 2.141166e-05 +52 bottom_right_grid_pin_1_[0]:22 ropt_net_182:8 0.0001361522 +53 bottom_right_grid_pin_1_[0]:22 ropt_net_182:4 1.246848e-05 +54 bottom_right_grid_pin_1_[0]:23 ropt_net_182:5 1.246848e-05 +55 bottom_right_grid_pin_1_[0]:23 ropt_net_182:9 0.0001361522 +56 bottom_right_grid_pin_1_[0]:23 ropt_net_182:3 2.141166e-05 +57 bottom_right_grid_pin_1_[0]:21 ropt_net_196:4 4.172049e-05 +58 bottom_right_grid_pin_1_[0]:20 ropt_net_196:5 4.172049e-05 +59 bottom_right_grid_pin_1_[0]:8 ropt_net_196:5 9.109426e-06 +60 bottom_right_grid_pin_1_[0]:6 ropt_net_196:3 9.787037e-06 +61 bottom_right_grid_pin_1_[0]:7 ropt_net_196:4 9.109426e-06 +62 bottom_right_grid_pin_1_[0]:5 ropt_net_196:2 9.787037e-06 + +*RES +0 bottom_right_grid_pin_1_[0] bottom_right_grid_pin_1_[0]:24 0.003058036 +1 bottom_right_grid_pin_1_[0]:22 bottom_right_grid_pin_1_[0]:21 0.0045 +2 bottom_right_grid_pin_1_[0]:22 bottom_right_grid_pin_1_[0]:9 0.001191964 +3 bottom_right_grid_pin_1_[0]:21 bottom_right_grid_pin_1_[0]:20 0.003866071 +4 bottom_right_grid_pin_1_[0]:19 bottom_right_grid_pin_1_[0]:18 0.001151786 +5 bottom_right_grid_pin_1_[0]:20 bottom_right_grid_pin_1_[0]:19 0.0045 +6 bottom_right_grid_pin_1_[0]:18 bottom_right_grid_pin_1_[0]:17 0.0045 +7 bottom_right_grid_pin_1_[0]:17 bottom_right_grid_pin_1_[0]:16 0.007508929 +8 bottom_right_grid_pin_1_[0]:15 bottom_right_grid_pin_1_[0]:14 0.0003035715 +9 bottom_right_grid_pin_1_[0]:15 bottom_right_grid_pin_1_[0]:12 0.001232143 +10 bottom_right_grid_pin_1_[0]:16 bottom_right_grid_pin_1_[0]:15 0.0045 +11 bottom_right_grid_pin_1_[0]:13 mux_bottom_track_1\/mux_l1_in_1_:A1 0.152 +12 bottom_right_grid_pin_1_[0]:9 bottom_right_grid_pin_1_[0]:8 0.0045 +13 bottom_right_grid_pin_1_[0]:8 bottom_right_grid_pin_1_[0]:7 0.001133929 +14 bottom_right_grid_pin_1_[0]:6 bottom_right_grid_pin_1_[0]:5 0.01310268 +15 bottom_right_grid_pin_1_[0]:7 bottom_right_grid_pin_1_[0]:6 0.0045 +16 bottom_right_grid_pin_1_[0]:4 mux_bottom_track_5\/mux_l1_in_1_:A1 0.152 +17 bottom_right_grid_pin_1_[0]:23 bottom_right_grid_pin_1_[0]:22 0.0480134 +18 bottom_right_grid_pin_1_[0]:24 bottom_right_grid_pin_1_[0]:23 0.0045 +19 bottom_right_grid_pin_1_[0]:10 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 +20 bottom_right_grid_pin_1_[0]:5 bottom_right_grid_pin_1_[0]:4 0.0003035715 +21 bottom_right_grid_pin_1_[0]:14 bottom_right_grid_pin_1_[0]:13 0.001198661 +22 bottom_right_grid_pin_1_[0]:12 bottom_right_grid_pin_1_[0]:11 0.0003035715 +23 bottom_right_grid_pin_1_[0]:11 bottom_right_grid_pin_1_[0]:10 0.007515626 + +*END + +*D_NET bottom_left_grid_pin_40_[0] 0.004689429 //LENGTH 37.007 LUMPCC 0.001822186 DR + +*CONN +*P bottom_left_grid_pin_40_[0] I *L 0.29796 *C 29.818 12.920 +*I mux_bottom_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 25.130 33.660 +*I mux_bottom_track_33\/mux_l1_in_1_:A1 I *L 0.00198 *C 21.160 34.340 +*I mux_bottom_track_5\/mux_l1_in_4_:A0 I *L 0.001631 *C 33.715 15.300 +*N bottom_left_grid_pin_40_[0]:4 *C 33.678 15.300 +*N bottom_left_grid_pin_40_[0]:5 *C 25.213 33.660 +*N bottom_left_grid_pin_40_[0]:6 *C 21.198 34.340 +*N bottom_left_grid_pin_40_[0]:7 *C 24.840 34.340 +*N bottom_left_grid_pin_40_[0]:8 *C 24.840 33.695 +*N bottom_left_grid_pin_40_[0]:9 *C 25.240 33.660 +*N bottom_left_grid_pin_40_[0]:10 *C 25.715 33.660 +*N bottom_left_grid_pin_40_[0]:11 *C 25.760 33.615 +*N bottom_left_grid_pin_40_[0]:12 *C 25.760 28.945 +*N bottom_left_grid_pin_40_[0]:13 *C 25.805 28.900 +*N bottom_left_grid_pin_40_[0]:14 *C 30.315 28.900 +*N bottom_left_grid_pin_40_[0]:15 *C 30.360 28.855 +*N bottom_left_grid_pin_40_[0]:16 *C 30.360 15.345 +*N bottom_left_grid_pin_40_[0]:17 *C 30.360 15.300 +*N bottom_left_grid_pin_40_[0]:18 *C 29.945 15.300 +*N bottom_left_grid_pin_40_[0]:19 *C 29.900 15.255 +*N bottom_left_grid_pin_40_[0]:20 *C 29.900 12.978 +*N bottom_left_grid_pin_40_[0]:21 *C 29.900 12.920 + +*CAP +0 bottom_left_grid_pin_40_[0] 2.796429e-05 +1 mux_bottom_track_3\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_33\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_5\/mux_l1_in_4_:A0 1e-06 +4 bottom_left_grid_pin_40_[0]:4 0.000207565 +5 bottom_left_grid_pin_40_[0]:5 1.2953e-05 +6 bottom_left_grid_pin_40_[0]:6 0.0002469553 +7 bottom_left_grid_pin_40_[0]:7 0.0002896927 +8 bottom_left_grid_pin_40_[0]:8 6.209928e-05 +9 bottom_left_grid_pin_40_[0]:9 6.275281e-05 +10 bottom_left_grid_pin_40_[0]:10 3.04379e-05 +11 bottom_left_grid_pin_40_[0]:11 0.0002444807 +12 bottom_left_grid_pin_40_[0]:12 0.0002444807 +13 bottom_left_grid_pin_40_[0]:13 0.0001840759 +14 bottom_left_grid_pin_40_[0]:14 0.0001840759 +15 bottom_left_grid_pin_40_[0]:15 0.0002969646 +16 bottom_left_grid_pin_40_[0]:16 0.0002969646 +17 bottom_left_grid_pin_40_[0]:17 0.0002718278 +18 bottom_left_grid_pin_40_[0]:18 3.315996e-05 +19 bottom_left_grid_pin_40_[0]:19 6.991459e-05 +20 bottom_left_grid_pin_40_[0]:20 6.991459e-05 +21 bottom_left_grid_pin_40_[0]:21 2.796429e-05 +22 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_36_[0]:13 1.988092e-05 +23 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_36_[0]:14 1.988092e-05 +24 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_36_[0]:9 3.030592e-05 +25 bottom_left_grid_pin_40_[0]:13 bottom_left_grid_pin_36_[0]:11 0.0001472123 +26 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_36_[0]:10 3.030592e-05 +27 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_36_[0]:12 0.0001472123 +28 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_36_[0]:13 0.0003861476 +29 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_36_[0]:14 0.0003861476 +30 bottom_left_grid_pin_40_[0]:9 bottom_left_grid_pin_38_[0]:11 1.440243e-05 +31 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_38_[0]:15 7.588556e-05 +32 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_38_[0]:16 7.588556e-05 +33 bottom_left_grid_pin_40_[0]:10 bottom_left_grid_pin_38_[0]:12 1.207949e-05 +34 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_38_[0]:13 0.0001366075 +35 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_38_[0]:15 0.0001006505 +36 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_38_[0]:14 0.0001366075 +37 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_38_[0]:16 0.0001006505 +38 bottom_left_grid_pin_40_[0]:5 bottom_left_grid_pin_38_[0]:12 2.322941e-06 + +*RES +0 bottom_left_grid_pin_40_[0] bottom_left_grid_pin_40_[0]:21 2.35e-05 +1 bottom_left_grid_pin_40_[0]:9 mux_bottom_track_3\/mux_l2_in_1_:A0 0.152 +2 bottom_left_grid_pin_40_[0]:9 bottom_left_grid_pin_40_[0]:8 0.0002702703 +3 bottom_left_grid_pin_40_[0]:9 bottom_left_grid_pin_40_[0]:5 1.858108e-05 +4 bottom_left_grid_pin_40_[0]:18 bottom_left_grid_pin_40_[0]:17 0.0003705357 +5 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_40_[0]:18 0.0045 +6 bottom_left_grid_pin_40_[0]:20 bottom_left_grid_pin_40_[0]:19 0.002033482 +7 bottom_left_grid_pin_40_[0]:21 bottom_left_grid_pin_40_[0]:20 0.00341 +8 bottom_left_grid_pin_40_[0]:4 mux_bottom_track_5\/mux_l1_in_4_:A0 0.152 +9 bottom_left_grid_pin_40_[0]:6 mux_bottom_track_33\/mux_l1_in_1_:A1 0.152 +10 bottom_left_grid_pin_40_[0]:10 bottom_left_grid_pin_40_[0]:9 0.0004241072 +11 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_40_[0]:10 0.0045 +12 bottom_left_grid_pin_40_[0]:13 bottom_left_grid_pin_40_[0]:12 0.0045 +13 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_40_[0]:11 0.004169643 +14 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_40_[0]:13 0.004026785 +15 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_40_[0]:14 0.0045 +16 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_40_[0]:16 0.0045 +17 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_40_[0]:4 0.002962054 +18 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_40_[0]:15 0.0120625 +19 bottom_left_grid_pin_40_[0]:7 bottom_left_grid_pin_40_[0]:6 0.003252232 +20 bottom_left_grid_pin_40_[0]:8 bottom_left_grid_pin_40_[0]:7 0.0005758929 + +*END + +*D_NET chanx_left_in[6] 0.01391446 //LENGTH 93.970 LUMPCC 0.005872886 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.230 34.000 +*I mux_bottom_track_25\/mux_l1_in_2_:A1 I *L 0.00198 *C 37.360 34.340 +*I mux_top_track_2\/mux_l2_in_2_:A0 I *L 0.001631 *C 32.835 87.720 +*N chanx_left_in[6]:3 *C 32.873 87.720 +*N chanx_left_in[6]:4 *C 35.835 87.720 +*N chanx_left_in[6]:5 *C 35.880 87.675 +*N chanx_left_in[6]:6 *C 37.323 34.340 +*N chanx_left_in[6]:7 *C 35.925 34.340 +*N chanx_left_in[6]:8 *C 35.880 34.385 +*N chanx_left_in[6]:9 *C 35.880 34.000 +*N chanx_left_in[6]:10 *C 35.873 34.000 + +*CAP +0 chanx_left_in[6] 0.001030347 +1 mux_bottom_track_25\/mux_l1_in_2_:A1 1e-06 +2 mux_top_track_2\/mux_l2_in_2_:A0 1e-06 +3 chanx_left_in[6]:3 0.0002221782 +4 chanx_left_in[6]:4 0.0002221782 +5 chanx_left_in[6]:5 0.002616945 +6 chanx_left_in[6]:6 0.0001113443 +7 chanx_left_in[6]:7 0.0001113443 +8 chanx_left_in[6]:8 0.002637576 +9 chanx_left_in[6]:9 5.731819e-05 +10 chanx_left_in[6]:10 0.001030347 +11 chanx_left_in[6] prog_clk[0]:266 1.007673e-05 +12 chanx_left_in[6] prog_clk[0]:528 3.051674e-05 +13 chanx_left_in[6] prog_clk[0]:529 6.008492e-06 +14 chanx_left_in[6]:10 prog_clk[0]:261 1.007673e-05 +15 chanx_left_in[6]:10 prog_clk[0]:266 3.051674e-05 +16 chanx_left_in[6]:10 prog_clk[0]:528 6.008492e-06 +17 chanx_left_in[6]:5 prog_clk[0]:211 2.259871e-05 +18 chanx_left_in[6]:5 prog_clk[0]:242 0.0001972413 +19 chanx_left_in[6]:8 prog_clk[0]:242 2.259871e-05 +20 chanx_left_in[6]:8 prog_clk[0]:243 0.0001972413 +21 chanx_left_in[6] chanx_left_in[1]:12 0.001882722 +22 chanx_left_in[6]:10 chanx_left_in[1]:11 0.001882722 +23 chanx_left_in[6]:9 chanx_left_in[3]:8 6.625355e-06 +24 chanx_left_in[6]:5 chanx_left_in[3]:5 0.0004306096 +25 chanx_left_in[6]:5 chanx_left_in[3]:9 0.0001237246 +26 chanx_left_in[6]:8 chanx_left_in[3]:8 0.0001237246 +27 chanx_left_in[6]:8 chanx_left_in[3]:9 0.0004372349 +28 chanx_left_in[6] mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0002263193 +29 chanx_left_in[6]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0002263193 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:10 0.005427325 +1 chanx_left_in[6]:9 chanx_left_in[6]:8 0.0001850962 +2 chanx_left_in[6]:10 chanx_left_in[6]:9 0.00341 +3 chanx_left_in[6]:4 chanx_left_in[6]:3 0.002645089 +4 chanx_left_in[6]:5 chanx_left_in[6]:4 0.0045 +5 chanx_left_in[6]:3 mux_top_track_2\/mux_l2_in_2_:A0 0.152 +6 chanx_left_in[6]:7 chanx_left_in[6]:6 0.001247768 +7 chanx_left_in[6]:8 chanx_left_in[6]:7 0.0045 +8 chanx_left_in[6]:8 chanx_left_in[6]:5 0.04758036 +9 chanx_left_in[6]:6 mux_bottom_track_25\/mux_l1_in_2_:A1 0.152 + +*END + +*D_NET chanx_left_in[14] 0.009703303 //LENGTH 67.830 LUMPCC 0.00119401 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.230 92.480 +*I mux_bottom_track_33\/mux_l1_in_2_:A0 I *L 0.001631 *C 9.375 42.500 +*I mux_top_track_0\/mux_l2_in_3_:A1 I *L 0.00198 *C 10.680 94.180 +*N chanx_left_in[14]:3 *C 10.643 94.180 +*N chanx_left_in[14]:4 *C 8.325 94.180 +*N chanx_left_in[14]:5 *C 8.280 94.180 +*N chanx_left_in[14]:6 *C 8.280 93.840 +*N chanx_left_in[14]:7 *C 9.338 42.500 +*N chanx_left_in[14]:8 *C 7.953 42.500 +*N chanx_left_in[14]:9 *C 7.820 42.500 +*N chanx_left_in[14]:10 *C 7.820 42.160 +*N chanx_left_in[14]:11 *C 7.823 42.160 +*N chanx_left_in[14]:12 *C 8.265 42.160 +*N chanx_left_in[14]:13 *C 8.280 42.168 +*N chanx_left_in[14]:14 *C 8.280 93.833 +*N chanx_left_in[14]:15 *C 8.273 93.840 +*N chanx_left_in[14]:16 *C 5.520 93.840 +*N chanx_left_in[14]:17 *C 5.520 93.160 +*N chanx_left_in[14]:18 *C 3.680 93.160 +*N chanx_left_in[14]:19 *C 3.680 92.480 + +*CAP +0 chanx_left_in[14] 0.0002565141 +1 mux_bottom_track_33\/mux_l1_in_2_:A0 1e-06 +2 mux_top_track_0\/mux_l2_in_3_:A1 1e-06 +3 chanx_left_in[14]:3 0.0001694578 +4 chanx_left_in[14]:4 0.0001694578 +5 chanx_left_in[14]:5 5.257063e-05 +6 chanx_left_in[14]:6 5.767227e-05 +7 chanx_left_in[14]:7 0.0001208997 +8 chanx_left_in[14]:8 0.0001208997 +9 chanx_left_in[14]:9 5.094397e-05 +10 chanx_left_in[14]:10 5.512112e-05 +11 chanx_left_in[14]:11 8.482529e-05 +12 chanx_left_in[14]:12 8.482529e-05 +13 chanx_left_in[14]:13 0.002901475 +14 chanx_left_in[14]:14 0.002901475 +15 chanx_left_in[14]:15 0.0002522485 +16 chanx_left_in[14]:16 0.0003257603 +17 chanx_left_in[14]:17 0.0003079415 +18 chanx_left_in[14]:18 0.0002865597 +19 chanx_left_in[14]:19 0.0003086441 +20 chanx_left_in[14]:14 chany_top_in[11]:9 0.0005933775 +21 chanx_left_in[14]:13 chany_top_in[11]:8 0.0005933775 +22 chanx_left_in[14]:10 chany_top_in[11]:4 3.627374e-06 +23 chanx_left_in[14]:9 chany_top_in[11]:5 3.627374e-06 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:19 0.0003838334 +1 chanx_left_in[14]:15 chanx_left_in[14]:14 0.00341 +2 chanx_left_in[14]:15 chanx_left_in[14]:6 0.00341 +3 chanx_left_in[14]:14 chanx_left_in[14]:13 0.008094182 +4 chanx_left_in[14]:12 chanx_left_in[14]:11 6.499218e-05 +5 chanx_left_in[14]:13 chanx_left_in[14]:12 0.00341 +6 chanx_left_in[14]:10 chanx_left_in[14]:9 0.0001634615 +7 chanx_left_in[14]:11 chanx_left_in[14]:10 0.00341 +8 chanx_left_in[14]:8 chanx_left_in[14]:7 0.001236607 +9 chanx_left_in[14]:9 chanx_left_in[14]:8 0.0045 +10 chanx_left_in[14]:7 mux_bottom_track_33\/mux_l1_in_2_:A0 0.152 +11 chanx_left_in[14]:6 chanx_left_in[14]:5 0.0001634615 +12 chanx_left_in[14]:4 chanx_left_in[14]:3 0.002069197 +13 chanx_left_in[14]:5 chanx_left_in[14]:4 0.0045 +14 chanx_left_in[14]:3 mux_top_track_0\/mux_l2_in_3_:A1 0.152 +15 chanx_left_in[14]:19 chanx_left_in[14]:18 0.0001065333 +16 chanx_left_in[14]:18 chanx_left_in[14]:17 0.0002882667 +17 chanx_left_in[14]:17 chanx_left_in[14]:16 0.0001065333 +18 chanx_left_in[14]:16 chanx_left_in[14]:15 0.000431225 + +*END + +*D_NET left_top_grid_pin_42_[0] 0.01415452 //LENGTH 107.755 LUMPCC 0.001497898 DR + +*CONN +*P left_top_grid_pin_42_[0] I *L 0.29796 *C 7.360 102.070 +*I mux_left_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 27.890 88.060 +*I mux_left_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 43.070 70.040 +*I mux_left_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 50.965 66.980 +*I mux_left_track_9\/mux_l2_in_1_:A1 I *L 0.00198 *C 72.320 69.020 +*N left_top_grid_pin_42_[0]:5 *C 29.650 88.400 +*N left_top_grid_pin_42_[0]:6 *C 72.282 69.020 +*N left_top_grid_pin_42_[0]:7 *C 70.885 69.020 +*N left_top_grid_pin_42_[0]:8 *C 70.840 69.065 +*N left_top_grid_pin_42_[0]:9 *C 70.840 69.995 +*N left_top_grid_pin_42_[0]:10 *C 70.795 70.040 +*N left_top_grid_pin_42_[0]:11 *C 50.965 66.980 +*N left_top_grid_pin_42_[0]:12 *C 51.060 67.025 +*N left_top_grid_pin_42_[0]:13 *C 51.060 69.995 +*N left_top_grid_pin_42_[0]:14 *C 51.060 70.040 +*N left_top_grid_pin_42_[0]:15 *C 43.070 70.040 +*N left_top_grid_pin_42_[0]:16 *C 43.285 70.040 +*N left_top_grid_pin_42_[0]:17 *C 43.240 70.085 +*N left_top_grid_pin_42_[0]:18 *C 43.240 72.703 +*N left_top_grid_pin_42_[0]:19 *C 43.233 72.760 +*N left_top_grid_pin_42_[0]:20 *C 30.380 72.760 +*N left_top_grid_pin_42_[0]:21 *C 30.360 72.767 +*N left_top_grid_pin_42_[0]:22 *C 30.360 88.392 +*N left_top_grid_pin_42_[0]:23 *C 30.358 88.400 +*N left_top_grid_pin_42_[0]:24 *C 30.360 88.400 +*N left_top_grid_pin_42_[0]:25 *C 30.315 88.400 +*N left_top_grid_pin_42_[0]:26 *C 27.928 88.060 +*N left_top_grid_pin_42_[0]:27 *C 28.520 88.060 +*N left_top_grid_pin_42_[0]:28 *C 28.520 88.400 +*N left_top_grid_pin_42_[0]:29 *C 28.520 88.445 +*N left_top_grid_pin_42_[0]:30 *C 28.520 94.463 +*N left_top_grid_pin_42_[0]:31 *C 28.513 94.520 +*N left_top_grid_pin_42_[0]:32 *C 11.060 94.520 +*N left_top_grid_pin_42_[0]:33 *C 11.040 94.528 +*N left_top_grid_pin_42_[0]:34 *C 11.040 95.873 +*N left_top_grid_pin_42_[0]:35 *C 11.020 95.880 +*N left_top_grid_pin_42_[0]:36 *C 7.368 95.880 +*N left_top_grid_pin_42_[0]:37 *C 7.360 95.938 + +*CAP +0 left_top_grid_pin_42_[0] 0.0003396849 +1 mux_left_track_1\/mux_l1_in_1_:A0 1e-06 +2 mux_left_track_5\/mux_l1_in_1_:A0 1e-06 +3 mux_left_track_25\/mux_l1_in_1_:A1 1e-06 +4 mux_left_track_9\/mux_l2_in_1_:A1 1e-06 +5 left_top_grid_pin_42_[0]:5 0.0001148154 +6 left_top_grid_pin_42_[0]:6 0.0001256105 +7 left_top_grid_pin_42_[0]:7 0.0001256105 +8 left_top_grid_pin_42_[0]:8 7.287905e-05 +9 left_top_grid_pin_42_[0]:9 7.287905e-05 +10 left_top_grid_pin_42_[0]:10 0.001354791 +11 left_top_grid_pin_42_[0]:11 3.065243e-05 +12 left_top_grid_pin_42_[0]:12 0.0001812523 +13 left_top_grid_pin_42_[0]:13 0.0001812523 +14 left_top_grid_pin_42_[0]:14 0.001897916 +15 left_top_grid_pin_42_[0]:15 5.206176e-05 +16 left_top_grid_pin_42_[0]:16 0.000531658 +17 left_top_grid_pin_42_[0]:17 0.0001949179 +18 left_top_grid_pin_42_[0]:18 0.0001949179 +19 left_top_grid_pin_42_[0]:19 0.0007368373 +20 left_top_grid_pin_42_[0]:20 0.0007368373 +21 left_top_grid_pin_42_[0]:21 0.000670586 +22 left_top_grid_pin_42_[0]:22 0.000670586 +23 left_top_grid_pin_42_[0]:23 0.0001148154 +24 left_top_grid_pin_42_[0]:24 3.814499e-05 +25 left_top_grid_pin_42_[0]:25 0.0001500219 +26 left_top_grid_pin_42_[0]:26 5.027914e-05 +27 left_top_grid_pin_42_[0]:27 7.955311e-05 +28 left_top_grid_pin_42_[0]:28 0.0001792959 +29 left_top_grid_pin_42_[0]:29 0.0004185486 +30 left_top_grid_pin_42_[0]:30 0.0004185486 +31 left_top_grid_pin_42_[0]:31 0.000912967 +32 left_top_grid_pin_42_[0]:32 0.000912967 +33 left_top_grid_pin_42_[0]:33 9.406887e-05 +34 left_top_grid_pin_42_[0]:34 9.406887e-05 +35 left_top_grid_pin_42_[0]:35 0.0002819524 +36 left_top_grid_pin_42_[0]:36 0.0002819524 +37 left_top_grid_pin_42_[0]:37 0.0003396849 +38 left_top_grid_pin_42_[0]:21 chanx_left_in[13]:13 0.0003117392 +39 left_top_grid_pin_42_[0]:23 chanx_left_in[13]:15 1.436381e-05 +40 left_top_grid_pin_42_[0]:22 chanx_left_in[13]:14 0.0003117392 +41 left_top_grid_pin_42_[0]:31 chanx_left_in[13]:6 1.260434e-07 +42 left_top_grid_pin_42_[0]:31 chanx_left_in[13]:15 6.410633e-05 +43 left_top_grid_pin_42_[0]:32 chanx_left_in[13]:15 1.260434e-07 +44 left_top_grid_pin_42_[0]:32 chanx_left_in[13]:16 6.410633e-05 +45 left_top_grid_pin_42_[0]:5 chanx_left_in[13]:6 1.436381e-05 +46 left_top_grid_pin_42_[0]:19 mux_tree_tapbuf_size3_2_sram[1]:8 0.0002640499 +47 left_top_grid_pin_42_[0]:20 mux_tree_tapbuf_size3_2_sram[1]:7 0.0002640499 +48 left_top_grid_pin_42_[0]:19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.45636e-05 +49 left_top_grid_pin_42_[0]:20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.45636e-05 + +*RES +0 left_top_grid_pin_42_[0] left_top_grid_pin_42_[0]:37 0.005475447 +1 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:15 0.0001168478 +2 left_top_grid_pin_42_[0]:16 left_top_grid_pin_42_[0]:14 0.006941964 +3 left_top_grid_pin_42_[0]:17 left_top_grid_pin_42_[0]:16 0.0045 +4 left_top_grid_pin_42_[0]:18 left_top_grid_pin_42_[0]:17 0.002337054 +5 left_top_grid_pin_42_[0]:19 left_top_grid_pin_42_[0]:18 0.00341 +6 left_top_grid_pin_42_[0]:20 left_top_grid_pin_42_[0]:19 0.002013558 +7 left_top_grid_pin_42_[0]:21 left_top_grid_pin_42_[0]:20 0.00341 +8 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:22 0.00341 +9 left_top_grid_pin_42_[0]:23 left_top_grid_pin_42_[0]:5 0.0001039141 +10 left_top_grid_pin_42_[0]:22 left_top_grid_pin_42_[0]:21 0.002447916 +11 left_top_grid_pin_42_[0]:24 left_top_grid_pin_42_[0]:23 0.00341 +12 left_top_grid_pin_42_[0]:25 left_top_grid_pin_42_[0]:24 0.0045 +13 left_top_grid_pin_42_[0]:26 mux_left_track_1\/mux_l1_in_1_:A0 0.152 +14 left_top_grid_pin_42_[0]:15 mux_left_track_5\/mux_l1_in_1_:A0 0.152 +15 left_top_grid_pin_42_[0]:14 left_top_grid_pin_42_[0]:13 0.0045 +16 left_top_grid_pin_42_[0]:14 left_top_grid_pin_42_[0]:10 0.01762054 +17 left_top_grid_pin_42_[0]:13 left_top_grid_pin_42_[0]:12 0.002651786 +18 left_top_grid_pin_42_[0]:11 mux_left_track_25\/mux_l1_in_1_:A1 0.152 +19 left_top_grid_pin_42_[0]:12 left_top_grid_pin_42_[0]:11 0.0045 +20 left_top_grid_pin_42_[0]:10 left_top_grid_pin_42_[0]:9 0.0045 +21 left_top_grid_pin_42_[0]:9 left_top_grid_pin_42_[0]:8 0.0008303572 +22 left_top_grid_pin_42_[0]:7 left_top_grid_pin_42_[0]:6 0.001247768 +23 left_top_grid_pin_42_[0]:8 left_top_grid_pin_42_[0]:7 0.0045 +24 left_top_grid_pin_42_[0]:6 mux_left_track_9\/mux_l2_in_1_:A1 0.152 +25 left_top_grid_pin_42_[0]:28 left_top_grid_pin_42_[0]:27 0.0003035714 +26 left_top_grid_pin_42_[0]:28 left_top_grid_pin_42_[0]:25 0.001602679 +27 left_top_grid_pin_42_[0]:29 left_top_grid_pin_42_[0]:28 0.0045 +28 left_top_grid_pin_42_[0]:30 left_top_grid_pin_42_[0]:29 0.005372768 +29 left_top_grid_pin_42_[0]:31 left_top_grid_pin_42_[0]:30 0.00341 +30 left_top_grid_pin_42_[0]:32 left_top_grid_pin_42_[0]:31 0.002734225 +31 left_top_grid_pin_42_[0]:33 left_top_grid_pin_42_[0]:32 0.00341 +32 left_top_grid_pin_42_[0]:35 left_top_grid_pin_42_[0]:34 0.00341 +33 left_top_grid_pin_42_[0]:34 left_top_grid_pin_42_[0]:33 0.0002107167 +34 left_top_grid_pin_42_[0]:37 left_top_grid_pin_42_[0]:36 0.00341 +35 left_top_grid_pin_42_[0]:36 left_top_grid_pin_42_[0]:35 0.000572225 +36 left_top_grid_pin_42_[0]:27 left_top_grid_pin_42_[0]:26 0.0005290179 + +*END + +*D_NET chany_bottom_out[8] 0.002471902 //LENGTH 18.135 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 54.740 9.860 +*P chany_bottom_out[8] O *L 0.7423 *C 63.480 1.325 +*N chany_bottom_out[8]:2 *C 63.480 6.062 +*N chany_bottom_out[8]:3 *C 63.473 6.120 +*N chany_bottom_out[8]:4 *C 54.748 6.120 +*N chany_bottom_out[8]:5 *C 54.740 6.178 +*N chany_bottom_out[8]:6 *C 54.740 9.815 +*N chany_bottom_out[8]:7 *C 54.740 9.860 + +*CAP +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[8] 0.0002915493 +2 chany_bottom_out[8]:2 0.0002915493 +3 chany_bottom_out[8]:3 0.0006825463 +4 chany_bottom_out[8]:4 0.0006825463 +5 chany_bottom_out[8]:5 0.0002449994 +6 chany_bottom_out[8]:6 0.0002449994 +7 chany_bottom_out[8]:7 3.271196e-05 + +*RES +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[8]:7 0.152 +1 chany_bottom_out[8]:2 chany_bottom_out[8] 0.004229911 +2 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.00341 +3 chany_bottom_out[8]:5 chany_bottom_out[8]:4 0.00341 +4 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.001366917 +5 chany_bottom_out[8]:7 chany_bottom_out[8]:6 0.0045 +6 chany_bottom_out[8]:6 chany_bottom_out[8]:5 0.003247768 + +*END + +*D_NET chanx_left_out[5] 0.001623029 //LENGTH 11.790 LUMPCC 0 DR + +*CONN +*I mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 9.145 44.540 +*P chanx_left_out[5] O *L 0.7423 *C 1.230 47.600 +*N chanx_left_out[5]:2 *C 8.273 47.600 +*N chanx_left_out[5]:3 *C 8.280 47.543 +*N chanx_left_out[5]:4 *C 8.280 44.585 +*N chanx_left_out[5]:5 *C 8.325 44.540 +*N chanx_left_out[5]:6 *C 9.107 44.540 + +*CAP +0 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[5] 0.0005073182 +2 chanx_left_out[5]:2 0.0005073182 +3 chanx_left_out[5]:3 0.0002318717 +4 chanx_left_out[5]:4 0.0002318717 +5 chanx_left_out[5]:5 7.182435e-05 +6 chanx_left_out[5]:6 7.182435e-05 + +*RES +0 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[5]:6 0.152 +1 chanx_left_out[5]:6 chanx_left_out[5]:5 0.0006986607 +2 chanx_left_out[5]:5 chanx_left_out[5]:4 0.0045 +3 chanx_left_out[5]:4 chanx_left_out[5]:3 0.002640625 +4 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 +5 chanx_left_out[5]:2 chanx_left_out[5] 0.001103325 + +*END + +*D_NET mux_tree_tapbuf_size10_0_sram[0] 0.008538039 //LENGTH 61.710 LUMPCC 0.0003693959 DR + +*CONN +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 84.765 120.360 +*I mux_top_track_0\/mux_l1_in_1_:S I *L 0.00357 *C 46.560 123.080 +*I mux_top_track_0\/mux_l1_in_0_:S I *L 0.00357 *C 42.440 126.820 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 43.415 120.700 +*I mux_top_track_0\/mux_l1_in_2_:S I *L 0.00357 *C 62.200 118.320 +*N mux_tree_tapbuf_size10_0_sram[0]:5 *C 62.163 118.320 +*N mux_tree_tapbuf_size10_0_sram[0]:6 *C 60.305 118.320 +*N mux_tree_tapbuf_size10_0_sram[0]:7 *C 60.260 118.320 +*N mux_tree_tapbuf_size10_0_sram[0]:8 *C 59.800 118.320 +*N mux_tree_tapbuf_size10_0_sram[0]:9 *C 43.453 120.700 +*N mux_tree_tapbuf_size10_0_sram[0]:10 *C 42.477 126.820 +*N mux_tree_tapbuf_size10_0_sram[0]:11 *C 43.700 126.820 +*N mux_tree_tapbuf_size10_0_sram[0]:12 *C 43.700 127.160 +*N mux_tree_tapbuf_size10_0_sram[0]:13 *C 47.335 127.160 +*N mux_tree_tapbuf_size10_0_sram[0]:14 *C 47.380 127.115 +*N mux_tree_tapbuf_size10_0_sram[0]:15 *C 46.598 123.080 +*N mux_tree_tapbuf_size10_0_sram[0]:16 *C 47.335 123.080 +*N mux_tree_tapbuf_size10_0_sram[0]:17 *C 47.380 123.080 +*N mux_tree_tapbuf_size10_0_sram[0]:18 *C 47.380 120.745 +*N mux_tree_tapbuf_size10_0_sram[0]:19 *C 47.380 120.700 +*N mux_tree_tapbuf_size10_0_sram[0]:20 *C 59.800 120.700 +*N mux_tree_tapbuf_size10_0_sram[0]:21 *C 59.800 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:22 *C 59.800 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:23 *C 59.808 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:24 *C 81.873 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:25 *C 81.880 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:26 *C 81.925 120.360 +*N mux_tree_tapbuf_size10_0_sram[0]:27 *C 84.728 120.360 + +*CAP +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_0\/mux_l1_in_1_:S 1e-06 +2 mux_top_track_0\/mux_l1_in_0_:S 1e-06 +3 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_top_track_0\/mux_l1_in_2_:S 1e-06 +5 mux_tree_tapbuf_size10_0_sram[0]:5 0.0001516468 +6 mux_tree_tapbuf_size10_0_sram[0]:6 0.0001516468 +7 mux_tree_tapbuf_size10_0_sram[0]:7 6.962771e-05 +8 mux_tree_tapbuf_size10_0_sram[0]:8 0.000180348 +9 mux_tree_tapbuf_size10_0_sram[0]:9 0.0002892939 +10 mux_tree_tapbuf_size10_0_sram[0]:10 8.278055e-05 +11 mux_tree_tapbuf_size10_0_sram[0]:11 0.0001081955 +12 mux_tree_tapbuf_size10_0_sram[0]:12 0.0002299352 +13 mux_tree_tapbuf_size10_0_sram[0]:13 0.0002045202 +14 mux_tree_tapbuf_size10_0_sram[0]:14 0.0002599902 +15 mux_tree_tapbuf_size10_0_sram[0]:15 8.205514e-05 +16 mux_tree_tapbuf_size10_0_sram[0]:16 8.205514e-05 +17 mux_tree_tapbuf_size10_0_sram[0]:17 0.0004597043 +18 mux_tree_tapbuf_size10_0_sram[0]:18 0.0001650579 +19 mux_tree_tapbuf_size10_0_sram[0]:19 0.001126592 +20 mux_tree_tapbuf_size10_0_sram[0]:20 0.0008279727 +21 mux_tree_tapbuf_size10_0_sram[0]:21 6.254445e-05 +22 mux_tree_tapbuf_size10_0_sram[0]:22 0.0001830966 +23 mux_tree_tapbuf_size10_0_sram[0]:23 0.001475056 +24 mux_tree_tapbuf_size10_0_sram[0]:24 0.001475056 +25 mux_tree_tapbuf_size10_0_sram[0]:25 3.427671e-05 +26 mux_tree_tapbuf_size10_0_sram[0]:26 0.0002310964 +27 mux_tree_tapbuf_size10_0_sram[0]:27 0.0002310964 +28 mux_tree_tapbuf_size10_0_sram[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:9 2.733363e-05 +29 mux_tree_tapbuf_size10_0_sram[0]:13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 0.0001150568 +30 mux_tree_tapbuf_size10_0_sram[0]:11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:8 2.733363e-05 +31 mux_tree_tapbuf_size10_0_sram[0]:12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 0.0001150568 +32 mux_tree_tapbuf_size10_0_sram[0]:19 ropt_net_172:3 4.230751e-05 +33 mux_tree_tapbuf_size10_0_sram[0]:20 ropt_net_172:2 4.230751e-05 + +*RES +0 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size10_0_sram[0]:27 0.152 +1 mux_tree_tapbuf_size10_0_sram[0]:5 mux_top_track_0\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size10_0_sram[0]:6 mux_tree_tapbuf_size10_0_sram[0]:5 0.001658482 +3 mux_tree_tapbuf_size10_0_sram[0]:7 mux_tree_tapbuf_size10_0_sram[0]:6 0.0045 +4 mux_tree_tapbuf_size10_0_sram[0]:10 mux_top_track_0\/mux_l1_in_0_:S 0.152 +5 mux_tree_tapbuf_size10_0_sram[0]:13 mux_tree_tapbuf_size10_0_sram[0]:12 0.003245536 +6 mux_tree_tapbuf_size10_0_sram[0]:14 mux_tree_tapbuf_size10_0_sram[0]:13 0.0045 +7 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:18 0.0045 +8 mux_tree_tapbuf_size10_0_sram[0]:19 mux_tree_tapbuf_size10_0_sram[0]:9 0.003506697 +9 mux_tree_tapbuf_size10_0_sram[0]:18 mux_tree_tapbuf_size10_0_sram[0]:17 0.002084821 +10 mux_tree_tapbuf_size10_0_sram[0]:21 mux_tree_tapbuf_size10_0_sram[0]:20 0.0003035715 +11 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:21 0.0045 +12 mux_tree_tapbuf_size10_0_sram[0]:22 mux_tree_tapbuf_size10_0_sram[0]:8 0.001821429 +13 mux_tree_tapbuf_size10_0_sram[0]:9 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size10_0_sram[0]:16 mux_tree_tapbuf_size10_0_sram[0]:15 0.0006584821 +15 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:16 0.0045 +16 mux_tree_tapbuf_size10_0_sram[0]:17 mux_tree_tapbuf_size10_0_sram[0]:14 0.003602678 +17 mux_tree_tapbuf_size10_0_sram[0]:15 mux_top_track_0\/mux_l1_in_1_:S 0.152 +18 mux_tree_tapbuf_size10_0_sram[0]:23 mux_tree_tapbuf_size10_0_sram[0]:22 0.00341 +19 mux_tree_tapbuf_size10_0_sram[0]:25 mux_tree_tapbuf_size10_0_sram[0]:24 0.00341 +20 mux_tree_tapbuf_size10_0_sram[0]:24 mux_tree_tapbuf_size10_0_sram[0]:23 0.00345685 +21 mux_tree_tapbuf_size10_0_sram[0]:26 mux_tree_tapbuf_size10_0_sram[0]:25 0.0045 +22 mux_tree_tapbuf_size10_0_sram[0]:27 mux_tree_tapbuf_size10_0_sram[0]:26 0.002502232 +23 mux_tree_tapbuf_size10_0_sram[0]:11 mux_tree_tapbuf_size10_0_sram[0]:10 0.001091518 +24 mux_tree_tapbuf_size10_0_sram[0]:20 mux_tree_tapbuf_size10_0_sram[0]:19 0.01108929 +25 mux_tree_tapbuf_size10_0_sram[0]:12 mux_tree_tapbuf_size10_0_sram[0]:11 0.0003035715 +26 mux_tree_tapbuf_size10_0_sram[0]:8 mux_tree_tapbuf_size10_0_sram[0]:7 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size14_1_sram[1] 0.004622463 //LENGTH 36.750 LUMPCC 0.0002839263 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 38.485 20.400 +*I mux_bottom_track_5\/mux_l2_in_3_:S I *L 0.00357 *C 37.620 23.120 +*I mux_bottom_track_5\/mux_l2_in_2_:S I *L 0.00357 *C 36.700 18.360 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 38.080 7.480 +*I mux_bottom_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 38.540 9.520 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 41.115 17.340 +*N mux_tree_tapbuf_size14_1_sram[1]:6 *C 41.115 17.340 +*N mux_tree_tapbuf_size14_1_sram[1]:7 *C 40.940 17.340 +*N mux_tree_tapbuf_size14_1_sram[1]:8 *C 40.940 17.385 +*N mux_tree_tapbuf_size14_1_sram[1]:9 *C 40.940 20.355 +*N mux_tree_tapbuf_size14_1_sram[1]:10 *C 40.895 20.400 +*N mux_tree_tapbuf_size14_1_sram[1]:11 *C 38.525 9.520 +*N mux_tree_tapbuf_size14_1_sram[1]:12 *C 38.203 9.520 +*N mux_tree_tapbuf_size14_1_sram[1]:13 *C 38.180 9.520 +*N mux_tree_tapbuf_size14_1_sram[1]:14 *C 38.065 7.480 +*N mux_tree_tapbuf_size14_1_sram[1]:15 *C 37.742 7.480 +*N mux_tree_tapbuf_size14_1_sram[1]:16 *C 37.720 7.525 +*N mux_tree_tapbuf_size14_1_sram[1]:17 *C 37.720 9.520 +*N mux_tree_tapbuf_size14_1_sram[1]:18 *C 37.720 10.143 +*N mux_tree_tapbuf_size14_1_sram[1]:19 *C 37.712 10.200 +*N mux_tree_tapbuf_size14_1_sram[1]:20 *C 34.968 10.200 +*N mux_tree_tapbuf_size14_1_sram[1]:21 *C 34.960 10.258 +*N mux_tree_tapbuf_size14_1_sram[1]:22 *C 36.663 18.360 +*N mux_tree_tapbuf_size14_1_sram[1]:23 *C 35.005 18.360 +*N mux_tree_tapbuf_size14_1_sram[1]:24 *C 34.960 18.360 +*N mux_tree_tapbuf_size14_1_sram[1]:25 *C 34.960 23.075 +*N mux_tree_tapbuf_size14_1_sram[1]:26 *C 35.005 23.120 +*N mux_tree_tapbuf_size14_1_sram[1]:27 *C 37.625 23.120 +*N mux_tree_tapbuf_size14_1_sram[1]:28 *C 37.720 23.075 +*N mux_tree_tapbuf_size14_1_sram[1]:29 *C 37.720 20.400 +*N mux_tree_tapbuf_size14_1_sram[1]:30 *C 38.180 20.400 +*N mux_tree_tapbuf_size14_1_sram[1]:31 *C 38.180 20.400 +*N mux_tree_tapbuf_size14_1_sram[1]:32 *C 38.523 20.400 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_5\/mux_l2_in_3_:S 1e-06 +2 mux_bottom_track_5\/mux_l2_in_2_:S 1e-06 +3 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +4 mux_bottom_track_5\/mux_l2_in_1_:S 1e-06 +5 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +6 mux_tree_tapbuf_size14_1_sram[1]:6 5.144681e-05 +7 mux_tree_tapbuf_size14_1_sram[1]:7 5.236294e-05 +8 mux_tree_tapbuf_size14_1_sram[1]:8 0.0001958682 +9 mux_tree_tapbuf_size14_1_sram[1]:9 0.0001958682 +10 mux_tree_tapbuf_size14_1_sram[1]:10 0.0001563971 +11 mux_tree_tapbuf_size14_1_sram[1]:11 5.740673e-05 +12 mux_tree_tapbuf_size14_1_sram[1]:12 5.740673e-05 +13 mux_tree_tapbuf_size14_1_sram[1]:13 6.18826e-05 +14 mux_tree_tapbuf_size14_1_sram[1]:14 6.011526e-05 +15 mux_tree_tapbuf_size14_1_sram[1]:15 6.011526e-05 +16 mux_tree_tapbuf_size14_1_sram[1]:16 0.0001257686 +17 mux_tree_tapbuf_size14_1_sram[1]:17 0.0002008266 +18 mux_tree_tapbuf_size14_1_sram[1]:18 4.314831e-05 +19 mux_tree_tapbuf_size14_1_sram[1]:19 0.0002214807 +20 mux_tree_tapbuf_size14_1_sram[1]:20 0.0002214807 +21 mux_tree_tapbuf_size14_1_sram[1]:21 0.0003880255 +22 mux_tree_tapbuf_size14_1_sram[1]:22 0.0001349694 +23 mux_tree_tapbuf_size14_1_sram[1]:23 0.0001349694 +24 mux_tree_tapbuf_size14_1_sram[1]:24 0.0006512117 +25 mux_tree_tapbuf_size14_1_sram[1]:25 0.0002307071 +26 mux_tree_tapbuf_size14_1_sram[1]:26 0.0001909247 +27 mux_tree_tapbuf_size14_1_sram[1]:27 0.0001909247 +28 mux_tree_tapbuf_size14_1_sram[1]:28 0.0001622857 +29 mux_tree_tapbuf_size14_1_sram[1]:29 0.0001952566 +30 mux_tree_tapbuf_size14_1_sram[1]:30 6.410228e-05 +31 mux_tree_tapbuf_size14_1_sram[1]:31 5.297115e-05 +32 mux_tree_tapbuf_size14_1_sram[1]:32 0.0001746132 +33 mux_tree_tapbuf_size14_1_sram[1]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.065125e-05 +34 mux_tree_tapbuf_size14_1_sram[1]:24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.065125e-05 +35 mux_tree_tapbuf_size14_1_sram[1]:21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 7.303127e-06 +36 mux_tree_tapbuf_size14_1_sram[1]:28 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 1.081568e-05 +37 mux_tree_tapbuf_size14_1_sram[1]:23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 2.679485e-06 +38 mux_tree_tapbuf_size14_1_sram[1]:24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 7.303127e-06 +39 mux_tree_tapbuf_size14_1_sram[1]:24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.051363e-05 +40 mux_tree_tapbuf_size14_1_sram[1]:22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 2.679485e-06 +41 mux_tree_tapbuf_size14_1_sram[1]:25 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.051363e-05 +42 mux_tree_tapbuf_size14_1_sram[1]:29 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 1.081568e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size14_1_sram[1]:32 0.152 +1 mux_tree_tapbuf_size14_1_sram[1]:11 mux_bottom_track_5\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size14_1_sram[1]:12 mux_tree_tapbuf_size14_1_sram[1]:11 0.0001752718 +3 mux_tree_tapbuf_size14_1_sram[1]:13 mux_tree_tapbuf_size14_1_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size14_1_sram[1]:21 mux_tree_tapbuf_size14_1_sram[1]:20 0.00341 +5 mux_tree_tapbuf_size14_1_sram[1]:20 mux_tree_tapbuf_size14_1_sram[1]:19 0.00043005 +6 mux_tree_tapbuf_size14_1_sram[1]:18 mux_tree_tapbuf_size14_1_sram[1]:17 0.0005558035 +7 mux_tree_tapbuf_size14_1_sram[1]:19 mux_tree_tapbuf_size14_1_sram[1]:18 0.00341 +8 mux_tree_tapbuf_size14_1_sram[1]:14 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size14_1_sram[1]:15 mux_tree_tapbuf_size14_1_sram[1]:14 0.0001752718 +10 mux_tree_tapbuf_size14_1_sram[1]:16 mux_tree_tapbuf_size14_1_sram[1]:15 0.0045 +11 mux_tree_tapbuf_size14_1_sram[1]:31 mux_tree_tapbuf_size14_1_sram[1]:30 0.0045 +12 mux_tree_tapbuf_size14_1_sram[1]:30 mux_tree_tapbuf_size14_1_sram[1]:29 0.0004107143 +13 mux_tree_tapbuf_size14_1_sram[1]:27 mux_bottom_track_5\/mux_l2_in_3_:S 0.152 +14 mux_tree_tapbuf_size14_1_sram[1]:27 mux_tree_tapbuf_size14_1_sram[1]:26 0.002339286 +15 mux_tree_tapbuf_size14_1_sram[1]:28 mux_tree_tapbuf_size14_1_sram[1]:27 0.0045 +16 mux_tree_tapbuf_size14_1_sram[1]:10 mux_tree_tapbuf_size14_1_sram[1]:9 0.0045 +17 mux_tree_tapbuf_size14_1_sram[1]:9 mux_tree_tapbuf_size14_1_sram[1]:8 0.002651786 +18 mux_tree_tapbuf_size14_1_sram[1]:7 mux_tree_tapbuf_size14_1_sram[1]:6 9.51087e-05 +19 mux_tree_tapbuf_size14_1_sram[1]:8 mux_tree_tapbuf_size14_1_sram[1]:7 0.0045 +20 mux_tree_tapbuf_size14_1_sram[1]:6 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +21 mux_tree_tapbuf_size14_1_sram[1]:32 mux_tree_tapbuf_size14_1_sram[1]:31 0.0001861413 +22 mux_tree_tapbuf_size14_1_sram[1]:32 mux_tree_tapbuf_size14_1_sram[1]:10 0.002118304 +23 mux_tree_tapbuf_size14_1_sram[1]:23 mux_tree_tapbuf_size14_1_sram[1]:22 0.001479911 +24 mux_tree_tapbuf_size14_1_sram[1]:24 mux_tree_tapbuf_size14_1_sram[1]:23 0.0045 +25 mux_tree_tapbuf_size14_1_sram[1]:24 mux_tree_tapbuf_size14_1_sram[1]:21 0.007234375 +26 mux_tree_tapbuf_size14_1_sram[1]:22 mux_bottom_track_5\/mux_l2_in_2_:S 0.152 +27 mux_tree_tapbuf_size14_1_sram[1]:26 mux_tree_tapbuf_size14_1_sram[1]:25 0.0045 +28 mux_tree_tapbuf_size14_1_sram[1]:25 mux_tree_tapbuf_size14_1_sram[1]:24 0.004209822 +29 mux_tree_tapbuf_size14_1_sram[1]:17 mux_tree_tapbuf_size14_1_sram[1]:16 0.00178125 +30 mux_tree_tapbuf_size14_1_sram[1]:17 mux_tree_tapbuf_size14_1_sram[1]:13 0.0004107143 +31 mux_tree_tapbuf_size14_1_sram[1]:29 mux_tree_tapbuf_size14_1_sram[1]:28 0.002388393 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[1] 0.003549712 //LENGTH 27.755 LUMPCC 0.0003643985 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 63.325 69.700 +*I mem_left_track_25\/FTB_27__59:A I *L 0.001746 *C 53.820 63.920 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 45.640 66.640 +*N mux_tree_tapbuf_size3_4_sram[1]:3 *C 45.678 66.640 +*N mux_tree_tapbuf_size3_4_sram[1]:4 *C 47.335 66.640 +*N mux_tree_tapbuf_size3_4_sram[1]:5 *C 47.380 66.595 +*N mux_tree_tapbuf_size3_4_sram[1]:6 *C 47.380 63.965 +*N mux_tree_tapbuf_size3_4_sram[1]:7 *C 47.425 63.920 +*N mux_tree_tapbuf_size3_4_sram[1]:8 *C 53.820 63.920 +*N mux_tree_tapbuf_size3_4_sram[1]:9 *C 62.055 63.920 +*N mux_tree_tapbuf_size3_4_sram[1]:10 *C 62.100 63.965 +*N mux_tree_tapbuf_size3_4_sram[1]:11 *C 62.100 69.655 +*N mux_tree_tapbuf_size3_4_sram[1]:12 *C 62.145 69.700 +*N mux_tree_tapbuf_size3_4_sram[1]:13 *C 63.288 69.700 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_25\/FTB_27__59:A 1e-06 +2 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_4_sram[1]:3 0.0001498274 +4 mux_tree_tapbuf_size3_4_sram[1]:4 0.0001498274 +5 mux_tree_tapbuf_size3_4_sram[1]:5 0.0001983794 +6 mux_tree_tapbuf_size3_4_sram[1]:6 0.0001983794 +7 mux_tree_tapbuf_size3_4_sram[1]:7 0.0002724488 +8 mux_tree_tapbuf_size3_4_sram[1]:8 0.0008149223 +9 mux_tree_tapbuf_size3_4_sram[1]:9 0.0005136054 +10 mux_tree_tapbuf_size3_4_sram[1]:10 0.0003246324 +11 mux_tree_tapbuf_size3_4_sram[1]:11 0.0003246324 +12 mux_tree_tapbuf_size3_4_sram[1]:12 0.0001178294 +13 mux_tree_tapbuf_size3_4_sram[1]:13 0.0001178294 +14 mux_tree_tapbuf_size3_4_sram[1]:7 mux_tree_tapbuf_size7_6_sram[1]:5 0.0001821992 +15 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size7_6_sram[1]:6 0.0001821992 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_4_sram[1]:13 0.152 +1 mux_tree_tapbuf_size3_4_sram[1]:7 mux_tree_tapbuf_size3_4_sram[1]:6 0.0045 +2 mux_tree_tapbuf_size3_4_sram[1]:6 mux_tree_tapbuf_size3_4_sram[1]:5 0.002348214 +3 mux_tree_tapbuf_size3_4_sram[1]:4 mux_tree_tapbuf_size3_4_sram[1]:3 0.001479911 +4 mux_tree_tapbuf_size3_4_sram[1]:5 mux_tree_tapbuf_size3_4_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size3_4_sram[1]:3 mux_left_track_25\/mux_l2_in_0_:S 0.152 +6 mux_tree_tapbuf_size3_4_sram[1]:9 mux_tree_tapbuf_size3_4_sram[1]:8 0.007352679 +7 mux_tree_tapbuf_size3_4_sram[1]:10 mux_tree_tapbuf_size3_4_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size3_4_sram[1]:12 mux_tree_tapbuf_size3_4_sram[1]:11 0.0045 +9 mux_tree_tapbuf_size3_4_sram[1]:11 mux_tree_tapbuf_size3_4_sram[1]:10 0.005080357 +10 mux_tree_tapbuf_size3_4_sram[1]:13 mux_tree_tapbuf_size3_4_sram[1]:12 0.001020089 +11 mux_tree_tapbuf_size3_4_sram[1]:8 mem_left_track_25\/FTB_27__59:A 0.152 +12 mux_tree_tapbuf_size3_4_sram[1]:8 mux_tree_tapbuf_size3_4_sram[1]:7 0.005709822 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[2] 0.001404005 //LENGTH 12.680 LUMPCC 7.661311e-05 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 83.565 69.360 +*I mux_left_track_9\/mux_l3_in_0_:S I *L 0.00357 *C 80.140 63.920 +*I mem_left_track_9\/FTB_19__51:A I *L 0.001746 *C 86.480 63.920 +*N mux_tree_tapbuf_size4_0_sram[2]:3 *C 86.443 63.920 +*N mux_tree_tapbuf_size4_0_sram[2]:4 *C 80.178 63.920 +*N mux_tree_tapbuf_size4_0_sram[2]:5 *C 83.720 63.920 +*N mux_tree_tapbuf_size4_0_sram[2]:6 *C 83.720 63.965 +*N mux_tree_tapbuf_size4_0_sram[2]:7 *C 83.720 69.315 +*N mux_tree_tapbuf_size4_0_sram[2]:8 *C 83.720 69.360 +*N mux_tree_tapbuf_size4_0_sram[2]:9 *C 83.565 69.360 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_9\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_9\/FTB_19__51:A 1e-06 +3 mux_tree_tapbuf_size4_0_sram[2]:3 0.0001571223 +4 mux_tree_tapbuf_size4_0_sram[2]:4 0.0001792338 +5 mux_tree_tapbuf_size4_0_sram[2]:5 0.000369419 +6 mux_tree_tapbuf_size4_0_sram[2]:6 0.0002632321 +7 mux_tree_tapbuf_size4_0_sram[2]:7 0.0002632321 +8 mux_tree_tapbuf_size4_0_sram[2]:8 4.700605e-05 +9 mux_tree_tapbuf_size4_0_sram[2]:9 4.514676e-05 +10 mux_tree_tapbuf_size4_0_sram[2]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 3.830656e-05 +11 mux_tree_tapbuf_size4_0_sram[2]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 3.830656e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_0_sram[2]:9 0.152 +1 mux_tree_tapbuf_size4_0_sram[2]:3 mem_left_track_9\/FTB_19__51:A 0.152 +2 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:4 0.003162947 +3 mux_tree_tapbuf_size4_0_sram[2]:5 mux_tree_tapbuf_size4_0_sram[2]:3 0.002430804 +4 mux_tree_tapbuf_size4_0_sram[2]:6 mux_tree_tapbuf_size4_0_sram[2]:5 0.0045 +5 mux_tree_tapbuf_size4_0_sram[2]:8 mux_tree_tapbuf_size4_0_sram[2]:7 0.0045 +6 mux_tree_tapbuf_size4_0_sram[2]:7 mux_tree_tapbuf_size4_0_sram[2]:6 0.004776786 +7 mux_tree_tapbuf_size4_0_sram[2]:9 mux_tree_tapbuf_size4_0_sram[2]:8 8.423914e-05 +8 mux_tree_tapbuf_size4_0_sram[2]:4 mux_left_track_9\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_3_sram[2] 0.002462123 //LENGTH 19.105 LUMPCC 0.0007002942 DR + +*CONN +*I mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 14.565 53.380 +*I mux_left_track_15\/mux_l3_in_0_:S I *L 0.00357 *C 8.860 58.140 +*I mem_left_track_15\/FTB_22__54:A I *L 0.001746 *C 7.360 50.320 +*N mux_tree_tapbuf_size4_3_sram[2]:3 *C 7.397 50.320 +*N mux_tree_tapbuf_size4_3_sram[2]:4 *C 8.740 50.320 +*N mux_tree_tapbuf_size4_3_sram[2]:5 *C 8.740 58.140 +*N mux_tree_tapbuf_size4_3_sram[2]:6 *C 8.740 58.095 +*N mux_tree_tapbuf_size4_3_sram[2]:7 *C 8.740 50.705 +*N mux_tree_tapbuf_size4_3_sram[2]:8 *C 8.740 50.660 +*N mux_tree_tapbuf_size4_3_sram[2]:9 *C 14.215 50.660 +*N mux_tree_tapbuf_size4_3_sram[2]:10 *C 14.260 50.705 +*N mux_tree_tapbuf_size4_3_sram[2]:11 *C 14.260 53.335 +*N mux_tree_tapbuf_size4_3_sram[2]:12 *C 14.260 53.380 +*N mux_tree_tapbuf_size4_3_sram[2]:13 *C 14.565 53.380 + +*CAP +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_15\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_15\/FTB_22__54:A 1e-06 +3 mux_tree_tapbuf_size4_3_sram[2]:3 3.526689e-05 +4 mux_tree_tapbuf_size4_3_sram[2]:4 6.258854e-05 +5 mux_tree_tapbuf_size4_3_sram[2]:5 3.384399e-05 +6 mux_tree_tapbuf_size4_3_sram[2]:6 0.0004212858 +7 mux_tree_tapbuf_size4_3_sram[2]:7 0.0004212858 +8 mux_tree_tapbuf_size4_3_sram[2]:8 0.0002064469 +9 mux_tree_tapbuf_size4_3_sram[2]:9 0.0001791252 +10 mux_tree_tapbuf_size4_3_sram[2]:10 0.0001503009 +11 mux_tree_tapbuf_size4_3_sram[2]:11 0.0001503009 +12 mux_tree_tapbuf_size4_3_sram[2]:12 5.137519e-05 +13 mux_tree_tapbuf_size4_3_sram[2]:13 4.700854e-05 +14 mux_tree_tapbuf_size4_3_sram[2]:8 chanx_left_in[2]:9 0.0002163013 +15 mux_tree_tapbuf_size4_3_sram[2]:3 chanx_left_in[2]:9 2.377781e-05 +16 mux_tree_tapbuf_size4_3_sram[2]:9 chanx_left_in[2]:8 0.0002163013 +17 mux_tree_tapbuf_size4_3_sram[2]:4 chanx_left_in[2]:8 2.377781e-05 +18 mux_tree_tapbuf_size4_3_sram[2]:6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:4 7.234932e-08 +19 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 5.104058e-05 +20 mux_tree_tapbuf_size4_3_sram[2]:7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:5 7.234932e-08 +21 mux_tree_tapbuf_size4_3_sram[2]:3 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 5.895509e-05 +22 mux_tree_tapbuf_size4_3_sram[2]:9 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 5.104058e-05 +23 mux_tree_tapbuf_size4_3_sram[2]:4 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 5.895509e-05 + +*RES +0 mem_left_track_15\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_3_sram[2]:13 0.152 +1 mux_tree_tapbuf_size4_3_sram[2]:5 mux_left_track_15\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size4_3_sram[2]:6 mux_tree_tapbuf_size4_3_sram[2]:5 0.0045 +3 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_3_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size4_3_sram[2]:8 mux_tree_tapbuf_size4_3_sram[2]:4 0.0003035715 +5 mux_tree_tapbuf_size4_3_sram[2]:7 mux_tree_tapbuf_size4_3_sram[2]:6 0.006598215 +6 mux_tree_tapbuf_size4_3_sram[2]:3 mem_left_track_15\/FTB_22__54:A 0.152 +7 mux_tree_tapbuf_size4_3_sram[2]:9 mux_tree_tapbuf_size4_3_sram[2]:8 0.004888393 +8 mux_tree_tapbuf_size4_3_sram[2]:10 mux_tree_tapbuf_size4_3_sram[2]:9 0.0045 +9 mux_tree_tapbuf_size4_3_sram[2]:12 mux_tree_tapbuf_size4_3_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size4_3_sram[2]:11 mux_tree_tapbuf_size4_3_sram[2]:10 0.002348214 +11 mux_tree_tapbuf_size4_3_sram[2]:13 mux_tree_tapbuf_size4_3_sram[2]:12 0.0001657609 +12 mux_tree_tapbuf_size4_3_sram[2]:4 mux_tree_tapbuf_size4_3_sram[2]:3 0.001198661 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[2] 0.002231633 //LENGTH 21.300 LUMPCC 0.000191284 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 19.165 36.720 +*I mux_bottom_track_33\/mux_l3_in_0_:S I *L 0.00357 *C 17.380 31.280 +*I mem_bottom_track_33\/FTB_17__49:A I *L 0.001746 *C 16.560 42.160 +*N mux_tree_tapbuf_size6_2_sram[2]:3 *C 16.523 42.160 +*N mux_tree_tapbuf_size6_2_sram[2]:4 *C 16.145 42.160 +*N mux_tree_tapbuf_size6_2_sram[2]:5 *C 16.100 42.115 +*N mux_tree_tapbuf_size6_2_sram[2]:6 *C 16.100 31.325 +*N mux_tree_tapbuf_size6_2_sram[2]:7 *C 16.145 31.280 +*N mux_tree_tapbuf_size6_2_sram[2]:8 *C 17.385 31.280 +*N mux_tree_tapbuf_size6_2_sram[2]:9 *C 17.480 31.325 +*N mux_tree_tapbuf_size6_2_sram[2]:10 *C 17.480 36.675 +*N mux_tree_tapbuf_size6_2_sram[2]:11 *C 17.525 36.720 +*N mux_tree_tapbuf_size6_2_sram[2]:12 *C 19.128 36.720 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_33\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_33\/FTB_17__49:A 1e-06 +3 mux_tree_tapbuf_size6_2_sram[2]:3 4.157925e-05 +4 mux_tree_tapbuf_size6_2_sram[2]:4 4.157925e-05 +5 mux_tree_tapbuf_size6_2_sram[2]:5 0.0004980493 +6 mux_tree_tapbuf_size6_2_sram[2]:6 0.0004980493 +7 mux_tree_tapbuf_size6_2_sram[2]:7 4.717653e-05 +8 mux_tree_tapbuf_size6_2_sram[2]:8 4.717653e-05 +9 mux_tree_tapbuf_size6_2_sram[2]:9 0.000305192 +10 mux_tree_tapbuf_size6_2_sram[2]:10 0.000305192 +11 mux_tree_tapbuf_size6_2_sram[2]:11 0.0001266775 +12 mux_tree_tapbuf_size6_2_sram[2]:12 0.0001266775 +13 mux_tree_tapbuf_size6_2_sram[2]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:3 3.888846e-05 +14 mux_tree_tapbuf_size6_2_sram[2]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.888846e-05 +15 mux_tree_tapbuf_size6_2_sram[2]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:2 8.088961e-06 +16 mux_tree_tapbuf_size6_2_sram[2]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:3 8.088961e-06 +17 mux_tree_tapbuf_size6_2_sram[2]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.866461e-05 +18 mux_tree_tapbuf_size6_2_sram[2]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.866461e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_2_sram[2]:12 0.152 +1 mux_tree_tapbuf_size6_2_sram[2]:8 mux_bottom_track_33\/mux_l3_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_2_sram[2]:8 mux_tree_tapbuf_size6_2_sram[2]:7 0.001107143 +3 mux_tree_tapbuf_size6_2_sram[2]:9 mux_tree_tapbuf_size6_2_sram[2]:8 0.0045 +4 mux_tree_tapbuf_size6_2_sram[2]:11 mux_tree_tapbuf_size6_2_sram[2]:10 0.0045 +5 mux_tree_tapbuf_size6_2_sram[2]:10 mux_tree_tapbuf_size6_2_sram[2]:9 0.004776786 +6 mux_tree_tapbuf_size6_2_sram[2]:12 mux_tree_tapbuf_size6_2_sram[2]:11 0.001430804 +7 mux_tree_tapbuf_size6_2_sram[2]:7 mux_tree_tapbuf_size6_2_sram[2]:6 0.0045 +8 mux_tree_tapbuf_size6_2_sram[2]:6 mux_tree_tapbuf_size6_2_sram[2]:5 0.009633929 +9 mux_tree_tapbuf_size6_2_sram[2]:4 mux_tree_tapbuf_size6_2_sram[2]:3 0.0003370536 +10 mux_tree_tapbuf_size6_2_sram[2]:5 mux_tree_tapbuf_size6_2_sram[2]:4 0.0045 +11 mux_tree_tapbuf_size6_2_sram[2]:3 mem_bottom_track_33\/FTB_17__49:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_2_sram[0] 0.009670985 //LENGTH 70.665 LUMPCC 0.001201652 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 82.190 42.500 +*I mux_bottom_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 62.200 45.175 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.035 42.500 +*I mux_bottom_track_17\/mux_l1_in_1_:S I *L 0.00357 *C 38.540 40.120 +*I mux_bottom_track_17\/mux_l1_in_2_:S I *L 0.00357 *C 42.680 55.760 +*I mux_bottom_track_17\/mux_l1_in_3_:S I *L 0.00357 *C 41.300 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:6 *C 62.200 45.250 +*N mux_tree_tapbuf_size7_2_sram[0]:7 *C 41.337 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:8 *C 42.665 55.760 +*N mux_tree_tapbuf_size7_2_sram[0]:9 *C 42.343 55.760 +*N mux_tree_tapbuf_size7_2_sram[0]:10 *C 42.320 55.715 +*N mux_tree_tapbuf_size7_2_sram[0]:11 *C 42.320 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:12 *C 38.578 40.120 +*N mux_tree_tapbuf_size7_2_sram[0]:13 *C 40.895 40.120 +*N mux_tree_tapbuf_size7_2_sram[0]:14 *C 40.940 40.165 +*N mux_tree_tapbuf_size7_2_sram[0]:15 *C 40.940 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:16 *C 42.035 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:17 *C 41.860 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:18 *C 41.860 42.545 +*N mux_tree_tapbuf_size7_2_sram[0]:19 *C 41.860 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:20 *C 41.860 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:21 *C 47.335 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:22 *C 47.380 44.835 +*N mux_tree_tapbuf_size7_2_sram[0]:23 *C 47.380 44.258 +*N mux_tree_tapbuf_size7_2_sram[0]:24 *C 47.388 44.200 +*N mux_tree_tapbuf_size7_2_sram[0]:25 *C 60.253 44.200 +*N mux_tree_tapbuf_size7_2_sram[0]:26 *C 60.260 44.258 +*N mux_tree_tapbuf_size7_2_sram[0]:27 *C 60.260 44.835 +*N mux_tree_tapbuf_size7_2_sram[0]:28 *C 60.305 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:29 *C 62.143 44.880 +*N mux_tree_tapbuf_size7_2_sram[0]:30 *C 62.200 45.175 +*N mux_tree_tapbuf_size7_2_sram[0]:31 *C 62.200 45.560 +*N mux_tree_tapbuf_size7_2_sram[0]:32 *C 82.295 45.560 +*N mux_tree_tapbuf_size7_2_sram[0]:33 *C 82.340 45.515 +*N mux_tree_tapbuf_size7_2_sram[0]:34 *C 82.340 42.545 +*N mux_tree_tapbuf_size7_2_sram[0]:35 *C 82.340 42.500 +*N mux_tree_tapbuf_size7_2_sram[0]:36 *C 82.190 42.500 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_17\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_17\/mux_l1_in_1_:S 1e-06 +4 mux_bottom_track_17\/mux_l1_in_2_:S 1e-06 +5 mux_bottom_track_17\/mux_l1_in_3_:S 1e-06 +6 mux_tree_tapbuf_size7_2_sram[0]:6 1.358058e-05 +7 mux_tree_tapbuf_size7_2_sram[0]:7 4.236602e-05 +8 mux_tree_tapbuf_size7_2_sram[0]:8 6.960874e-05 +9 mux_tree_tapbuf_size7_2_sram[0]:9 6.960874e-05 +10 mux_tree_tapbuf_size7_2_sram[0]:10 0.0005340778 +11 mux_tree_tapbuf_size7_2_sram[0]:11 0.0005705957 +12 mux_tree_tapbuf_size7_2_sram[0]:12 0.0001993387 +13 mux_tree_tapbuf_size7_2_sram[0]:13 0.0001993387 +14 mux_tree_tapbuf_size7_2_sram[0]:14 0.0001441348 +15 mux_tree_tapbuf_size7_2_sram[0]:15 0.0002009574 +16 mux_tree_tapbuf_size7_2_sram[0]:16 5.498366e-05 +17 mux_tree_tapbuf_size7_2_sram[0]:17 5.515121e-05 +18 mux_tree_tapbuf_size7_2_sram[0]:18 0.0001964045 +19 mux_tree_tapbuf_size7_2_sram[0]:19 0.0001760999 +20 mux_tree_tapbuf_size7_2_sram[0]:20 0.0003306816 +21 mux_tree_tapbuf_size7_2_sram[0]:21 0.000253535 +22 mux_tree_tapbuf_size7_2_sram[0]:22 6.728469e-05 +23 mux_tree_tapbuf_size7_2_sram[0]:23 6.728469e-05 +24 mux_tree_tapbuf_size7_2_sram[0]:24 0.0007926501 +25 mux_tree_tapbuf_size7_2_sram[0]:25 0.0007926501 +26 mux_tree_tapbuf_size7_2_sram[0]:26 6.609876e-05 +27 mux_tree_tapbuf_size7_2_sram[0]:27 6.609876e-05 +28 mux_tree_tapbuf_size7_2_sram[0]:28 9.934037e-05 +29 mux_tree_tapbuf_size7_2_sram[0]:29 0.0001201143 +30 mux_tree_tapbuf_size7_2_sram[0]:30 8.3387e-05 +31 mux_tree_tapbuf_size7_2_sram[0]:31 0.001393627 +32 mux_tree_tapbuf_size7_2_sram[0]:32 0.001373691 +33 mux_tree_tapbuf_size7_2_sram[0]:33 0.0001655322 +34 mux_tree_tapbuf_size7_2_sram[0]:34 0.0001655322 +35 mux_tree_tapbuf_size7_2_sram[0]:35 5.1662e-05 +36 mux_tree_tapbuf_size7_2_sram[0]:36 4.791639e-05 +37 mux_tree_tapbuf_size7_2_sram[0]:18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.156546e-06 +38 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.740503e-05 +39 mux_tree_tapbuf_size7_2_sram[0]:19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.156546e-06 +40 mux_tree_tapbuf_size7_2_sram[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.807424e-07 +41 mux_tree_tapbuf_size7_2_sram[0]:28 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.46519e-05 +42 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.740503e-05 +43 mux_tree_tapbuf_size7_2_sram[0]:29 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.46519e-05 +44 mux_tree_tapbuf_size7_2_sram[0]:15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.807424e-07 +45 mux_tree_tapbuf_size7_2_sram[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 1.849812e-06 +46 mux_tree_tapbuf_size7_2_sram[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001146003 +47 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 1.849812e-06 +48 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001146003 +49 mux_tree_tapbuf_size7_2_sram[0]:20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 2.775867e-05 +50 mux_tree_tapbuf_size7_2_sram[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 1.321262e-05 +51 mux_tree_tapbuf_size7_2_sram[0]:21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 2.775867e-05 +52 mux_tree_tapbuf_size7_2_sram[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 1.321262e-05 +53 mux_tree_tapbuf_size7_2_sram[0]:32 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.452846e-05 +54 mux_tree_tapbuf_size7_2_sram[0]:33 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.533416e-06 +55 mux_tree_tapbuf_size7_2_sram[0]:34 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.533416e-06 +56 mux_tree_tapbuf_size7_2_sram[0]:31 mux_left_track_11/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.452846e-05 +57 mux_tree_tapbuf_size7_2_sram[0]:25 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0003173485 +58 mux_tree_tapbuf_size7_2_sram[0]:24 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003173485 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_2_sram[0]:36 0.152 +1 mux_tree_tapbuf_size7_2_sram[0]:32 mux_tree_tapbuf_size7_2_sram[0]:31 0.01794197 +2 mux_tree_tapbuf_size7_2_sram[0]:33 mux_tree_tapbuf_size7_2_sram[0]:32 0.0045 +3 mux_tree_tapbuf_size7_2_sram[0]:35 mux_tree_tapbuf_size7_2_sram[0]:34 0.0045 +4 mux_tree_tapbuf_size7_2_sram[0]:34 mux_tree_tapbuf_size7_2_sram[0]:33 0.002651786 +5 mux_tree_tapbuf_size7_2_sram[0]:36 mux_tree_tapbuf_size7_2_sram[0]:35 8.152174e-05 +6 mux_tree_tapbuf_size7_2_sram[0]:30 mux_bottom_track_17\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size7_2_sram[0]:30 mux_tree_tapbuf_size7_2_sram[0]:29 0.0001715116 +8 mux_tree_tapbuf_size7_2_sram[0]:30 mux_tree_tapbuf_size7_2_sram[0]:6 4.360465e-05 +9 mux_tree_tapbuf_size7_2_sram[0]:17 mux_tree_tapbuf_size7_2_sram[0]:16 9.510871e-05 +10 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:17 0.0045 +11 mux_tree_tapbuf_size7_2_sram[0]:18 mux_tree_tapbuf_size7_2_sram[0]:15 0.0008214285 +12 mux_tree_tapbuf_size7_2_sram[0]:16 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:19 0.0045 +14 mux_tree_tapbuf_size7_2_sram[0]:20 mux_tree_tapbuf_size7_2_sram[0]:7 0.0004665179 +15 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:18 0.002084821 +16 mux_tree_tapbuf_size7_2_sram[0]:19 mux_tree_tapbuf_size7_2_sram[0]:11 0.0004107143 +17 mux_tree_tapbuf_size7_2_sram[0]:8 mux_bottom_track_17\/mux_l1_in_2_:S 0.152 +18 mux_tree_tapbuf_size7_2_sram[0]:9 mux_tree_tapbuf_size7_2_sram[0]:8 0.0001752718 +19 mux_tree_tapbuf_size7_2_sram[0]:10 mux_tree_tapbuf_size7_2_sram[0]:9 0.0045 +20 mux_tree_tapbuf_size7_2_sram[0]:7 mux_bottom_track_17\/mux_l1_in_3_:S 0.152 +21 mux_tree_tapbuf_size7_2_sram[0]:12 mux_bottom_track_17\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_2_sram[0]:13 mux_tree_tapbuf_size7_2_sram[0]:12 0.002069196 +23 mux_tree_tapbuf_size7_2_sram[0]:14 mux_tree_tapbuf_size7_2_sram[0]:13 0.0045 +24 mux_tree_tapbuf_size7_2_sram[0]:28 mux_tree_tapbuf_size7_2_sram[0]:27 0.0045 +25 mux_tree_tapbuf_size7_2_sram[0]:27 mux_tree_tapbuf_size7_2_sram[0]:26 0.000515625 +26 mux_tree_tapbuf_size7_2_sram[0]:26 mux_tree_tapbuf_size7_2_sram[0]:25 0.00341 +27 mux_tree_tapbuf_size7_2_sram[0]:25 mux_tree_tapbuf_size7_2_sram[0]:24 0.002015517 +28 mux_tree_tapbuf_size7_2_sram[0]:23 mux_tree_tapbuf_size7_2_sram[0]:22 0.000515625 +29 mux_tree_tapbuf_size7_2_sram[0]:24 mux_tree_tapbuf_size7_2_sram[0]:23 0.00341 +30 mux_tree_tapbuf_size7_2_sram[0]:21 mux_tree_tapbuf_size7_2_sram[0]:20 0.004888393 +31 mux_tree_tapbuf_size7_2_sram[0]:22 mux_tree_tapbuf_size7_2_sram[0]:21 0.0045 +32 mux_tree_tapbuf_size7_2_sram[0]:29 mux_tree_tapbuf_size7_2_sram[0]:28 0.001640625 +33 mux_tree_tapbuf_size7_2_sram[0]:31 mux_tree_tapbuf_size7_2_sram[0]:30 0.00034375 +34 mux_tree_tapbuf_size7_2_sram[0]:15 mux_tree_tapbuf_size7_2_sram[0]:14 0.002084821 +35 mux_tree_tapbuf_size7_2_sram[0]:11 mux_tree_tapbuf_size7_2_sram[0]:10 0.009674108 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_3_ccff_tail[0] 0.000550541 //LENGTH 3.280 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/FTB_11__43:X O *L 0 *C 22.305 85.000 +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 22.715 82.620 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 *C 22.715 82.620 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 *C 22.540 82.620 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 *C 22.540 82.665 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 *C 22.540 84.955 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 *C 22.540 85.000 +*N mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 *C 22.305 85.000 + +*CAP +0 mem_left_track_1\/FTB_11__43:X 1e-06 +1 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 5.403957e-05 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 5.819295e-05 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.000157585 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.000157585 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 5.933033e-05 +7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 6.180815e-05 + +*RES +0 mem_left_track_1\/FTB_11__43:X mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_3_ccff_tail[0]:2 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_0_sram[0] 0.001727933 //LENGTH 13.285 LUMPCC 0 DR + +*CONN +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 38.485 115.260 +*I mux_top_track_2\/mux_l1_in_0_:S I *L 0.00357 *C 36.440 112.590 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 32.835 109.820 +*N mux_tree_tapbuf_size8_0_sram[0]:3 *C 36.460 112.880 +*N mux_tree_tapbuf_size8_0_sram[0]:4 *C 32.873 109.820 +*N mux_tree_tapbuf_size8_0_sram[0]:5 *C 36.295 109.820 +*N mux_tree_tapbuf_size8_0_sram[0]:6 *C 36.340 109.865 +*N mux_tree_tapbuf_size8_0_sram[0]:7 *C 36.340 112.155 +*N mux_tree_tapbuf_size8_0_sram[0]:8 *C 36.340 112.200 +*N mux_tree_tapbuf_size8_0_sram[0]:9 *C 36.440 112.590 +*N mux_tree_tapbuf_size8_0_sram[0]:10 *C 36.515 112.880 +*N mux_tree_tapbuf_size8_0_sram[0]:11 *C 38.595 112.880 +*N mux_tree_tapbuf_size8_0_sram[0]:12 *C 38.640 112.925 +*N mux_tree_tapbuf_size8_0_sram[0]:13 *C 38.640 115.215 +*N mux_tree_tapbuf_size8_0_sram[0]:14 *C 38.640 115.260 +*N mux_tree_tapbuf_size8_0_sram[0]:15 *C 38.485 115.260 + +*CAP +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_top_track_2\/mux_l1_in_0_:S 1e-06 +2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size8_0_sram[0]:3 3.017081e-05 +4 mux_tree_tapbuf_size8_0_sram[0]:4 0.0002462627 +5 mux_tree_tapbuf_size8_0_sram[0]:5 0.0002462627 +6 mux_tree_tapbuf_size8_0_sram[0]:6 0.0001364488 +7 mux_tree_tapbuf_size8_0_sram[0]:7 0.0001364488 +8 mux_tree_tapbuf_size8_0_sram[0]:8 5.861753e-05 +9 mux_tree_tapbuf_size8_0_sram[0]:9 9.685777e-05 +10 mux_tree_tapbuf_size8_0_sram[0]:10 0.0002211926 +11 mux_tree_tapbuf_size8_0_sram[0]:11 0.0001851762 +12 mux_tree_tapbuf_size8_0_sram[0]:12 0.0001355199 +13 mux_tree_tapbuf_size8_0_sram[0]:13 0.0001355199 +14 mux_tree_tapbuf_size8_0_sram[0]:14 5.046546e-05 +15 mux_tree_tapbuf_size8_0_sram[0]:15 4.59901e-05 + +*RES +0 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size8_0_sram[0]:15 0.152 +1 mux_tree_tapbuf_size8_0_sram[0]:8 mux_tree_tapbuf_size8_0_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size8_0_sram[0]:7 mux_tree_tapbuf_size8_0_sram[0]:6 0.002044643 +3 mux_tree_tapbuf_size8_0_sram[0]:5 mux_tree_tapbuf_size8_0_sram[0]:4 0.003055803 +4 mux_tree_tapbuf_size8_0_sram[0]:6 mux_tree_tapbuf_size8_0_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size8_0_sram[0]:4 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size8_0_sram[0]:9 mux_top_track_2\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:8 0.0003482143 +8 mux_tree_tapbuf_size8_0_sram[0]:9 mux_tree_tapbuf_size8_0_sram[0]:3 0.0002589286 +9 mux_tree_tapbuf_size8_0_sram[0]:15 mux_tree_tapbuf_size8_0_sram[0]:14 8.423914e-05 +10 mux_tree_tapbuf_size8_0_sram[0]:14 mux_tree_tapbuf_size8_0_sram[0]:13 0.0045 +11 mux_tree_tapbuf_size8_0_sram[0]:13 mux_tree_tapbuf_size8_0_sram[0]:12 0.002044643 +12 mux_tree_tapbuf_size8_0_sram[0]:11 mux_tree_tapbuf_size8_0_sram[0]:10 0.001857143 +13 mux_tree_tapbuf_size8_0_sram[0]:12 mux_tree_tapbuf_size8_0_sram[0]:11 0.0045 +14 mux_tree_tapbuf_size8_0_sram[0]:10 mux_tree_tapbuf_size8_0_sram[0]:9 0.0002589286 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[0] 0.00379332 //LENGTH 27.125 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 41.705 31.620 +*I mux_bottom_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 30.940 30.600 +*I mux_bottom_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 30.920 34.295 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 34.660 37.060 +*N mux_tree_tapbuf_size9_0_sram[0]:4 *C 34.660 37.060 +*N mux_tree_tapbuf_size9_0_sram[0]:5 *C 31.375 34.680 +*N mux_tree_tapbuf_size9_0_sram[0]:6 *C 30.920 34.295 +*N mux_tree_tapbuf_size9_0_sram[0]:7 *C 30.920 34.635 +*N mux_tree_tapbuf_size9_0_sram[0]:8 *C 30.955 30.600 +*N mux_tree_tapbuf_size9_0_sram[0]:9 *C 31.258 30.600 +*N mux_tree_tapbuf_size9_0_sram[0]:10 *C 31.280 30.645 +*N mux_tree_tapbuf_size9_0_sram[0]:11 *C 31.280 34.635 +*N mux_tree_tapbuf_size9_0_sram[0]:12 *C 31.405 34.680 +*N mux_tree_tapbuf_size9_0_sram[0]:13 *C 34.915 34.680 +*N mux_tree_tapbuf_size9_0_sram[0]:14 *C 34.960 34.725 +*N mux_tree_tapbuf_size9_0_sram[0]:15 *C 34.960 37.015 +*N mux_tree_tapbuf_size9_0_sram[0]:16 *C 34.960 37.095 +*N mux_tree_tapbuf_size9_0_sram[0]:17 *C 34.960 37.400 +*N mux_tree_tapbuf_size9_0_sram[0]:18 *C 40.895 37.400 +*N mux_tree_tapbuf_size9_0_sram[0]:19 *C 40.940 37.355 +*N mux_tree_tapbuf_size9_0_sram[0]:20 *C 40.940 31.665 +*N mux_tree_tapbuf_size9_0_sram[0]:21 *C 40.985 31.620 +*N mux_tree_tapbuf_size9_0_sram[0]:22 *C 41.668 31.620 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_3\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:S 1e-06 +3 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size9_0_sram[0]:4 7.631059e-05 +5 mux_tree_tapbuf_size9_0_sram[0]:5 2.127597e-05 +6 mux_tree_tapbuf_size9_0_sram[0]:6 6.086121e-05 +7 mux_tree_tapbuf_size9_0_sram[0]:7 6.889184e-05 +8 mux_tree_tapbuf_size9_0_sram[0]:8 5.515954e-05 +9 mux_tree_tapbuf_size9_0_sram[0]:9 5.515954e-05 +10 mux_tree_tapbuf_size9_0_sram[0]:10 0.0002912094 +11 mux_tree_tapbuf_size9_0_sram[0]:11 0.0002912094 +12 mux_tree_tapbuf_size9_0_sram[0]:12 0.0003190777 +13 mux_tree_tapbuf_size9_0_sram[0]:13 0.0002612188 +14 mux_tree_tapbuf_size9_0_sram[0]:14 0.00020079 +15 mux_tree_tapbuf_size9_0_sram[0]:15 0.00020079 +16 mux_tree_tapbuf_size9_0_sram[0]:16 6.96067e-05 +17 mux_tree_tapbuf_size9_0_sram[0]:17 0.0005063252 +18 mux_tree_tapbuf_size9_0_sram[0]:18 0.0004736803 +19 mux_tree_tapbuf_size9_0_sram[0]:19 0.0003328559 +20 mux_tree_tapbuf_size9_0_sram[0]:20 0.0003328559 +21 mux_tree_tapbuf_size9_0_sram[0]:21 8.60211e-05 +22 mux_tree_tapbuf_size9_0_sram[0]:22 8.60211e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size9_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size9_0_sram[0]:16 mux_tree_tapbuf_size9_0_sram[0]:15 0.0045 +2 mux_tree_tapbuf_size9_0_sram[0]:16 mux_tree_tapbuf_size9_0_sram[0]:4 0.0001363636 +3 mux_tree_tapbuf_size9_0_sram[0]:15 mux_tree_tapbuf_size9_0_sram[0]:14 0.002044643 +4 mux_tree_tapbuf_size9_0_sram[0]:13 mux_tree_tapbuf_size9_0_sram[0]:12 0.003133929 +5 mux_tree_tapbuf_size9_0_sram[0]:14 mux_tree_tapbuf_size9_0_sram[0]:13 0.0045 +6 mux_tree_tapbuf_size9_0_sram[0]:4 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size9_0_sram[0]:12 mux_tree_tapbuf_size9_0_sram[0]:11 0.0045 +8 mux_tree_tapbuf_size9_0_sram[0]:12 mux_tree_tapbuf_size9_0_sram[0]:7 0.000275 +9 mux_tree_tapbuf_size9_0_sram[0]:12 mux_tree_tapbuf_size9_0_sram[0]:5 1.875e-05 +10 mux_tree_tapbuf_size9_0_sram[0]:11 mux_tree_tapbuf_size9_0_sram[0]:10 0.0035625 +11 mux_tree_tapbuf_size9_0_sram[0]:9 mux_tree_tapbuf_size9_0_sram[0]:8 0.0001644022 +12 mux_tree_tapbuf_size9_0_sram[0]:10 mux_tree_tapbuf_size9_0_sram[0]:9 0.0045 +13 mux_tree_tapbuf_size9_0_sram[0]:8 mux_bottom_track_3\/mux_l1_in_1_:S 0.152 +14 mux_tree_tapbuf_size9_0_sram[0]:18 mux_tree_tapbuf_size9_0_sram[0]:17 0.005299108 +15 mux_tree_tapbuf_size9_0_sram[0]:19 mux_tree_tapbuf_size9_0_sram[0]:18 0.0045 +16 mux_tree_tapbuf_size9_0_sram[0]:21 mux_tree_tapbuf_size9_0_sram[0]:20 0.0045 +17 mux_tree_tapbuf_size9_0_sram[0]:20 mux_tree_tapbuf_size9_0_sram[0]:19 0.005080357 +18 mux_tree_tapbuf_size9_0_sram[0]:22 mux_tree_tapbuf_size9_0_sram[0]:21 0.000609375 +19 mux_tree_tapbuf_size9_0_sram[0]:6 mux_bottom_track_3\/mux_l1_in_0_:S 0.152 +20 mux_tree_tapbuf_size9_0_sram[0]:7 mux_tree_tapbuf_size9_0_sram[0]:6 0.0003035715 +21 mux_tree_tapbuf_size9_0_sram[0]:17 mux_tree_tapbuf_size9_0_sram[0]:16 0.0002723215 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0009859458 //LENGTH 7.195 LUMPCC 0.0002935849 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_3_:X O *L 0 *C 12.245 94.180 +*I mux_top_track_0\/mux_l3_in_1_:A0 I *L 0.001631 *C 15.790 96.900 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 15.753 96.900 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 12.925 96.900 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 12.880 96.855 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 12.880 94.225 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 12.835 94.180 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 12.283 94.180 + +*CAP +0 mux_top_track_0\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.0001493262 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0001493262 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0001346758 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0001346758 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 6.117848e-05 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 6.117848e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 chany_top_in[3]:2 9.331009e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 chany_top_in[3]:3 9.331009e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:5 5.18268e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:3 1.655588e-06 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.18268e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_5_X[0]:2 1.655588e-06 + +*RES +0 mux_top_track_0\/mux_l2_in_3_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0004933036 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.002348214 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002524554 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_top_track_0\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0008283076 //LENGTH 5.660 LUMPCC 0.0001041887 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_3_:X O *L 0 *C 48.585 36.380 +*I mux_bottom_track_1\/mux_l3_in_1_:A0 I *L 0.001631 *C 48.130 31.620 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 48.130 31.620 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 48.300 31.620 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 *C 48.300 31.665 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 *C 48.300 36.335 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 *C 48.300 36.380 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 *C 48.585 36.380 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 6.842487e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 6.532177e-05 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.0002409235 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0002409235 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 5.416526e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 5.236009e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 5.209433e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 5.209433e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_3_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_1\/mux_l3_in_1_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:2 9.239131e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 0.004169643 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:6 0.0001548913 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00174984 //LENGTH 12.880 LUMPCC 0.0005613214 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_3_:X O *L 0 *C 32.485 91.800 +*I mux_top_track_2\/mux_l3_in_1_:A0 I *L 0.001631 *C 34.675 97.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 34.638 97.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 31.785 97.240 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 31.740 97.195 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 31.740 94.565 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 31.785 94.520 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 33.535 94.520 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 33.580 94.475 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 33.580 91.845 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 33.535 91.800 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 32.523 91.800 + +*CAP +0 mux_top_track_2\/mux_l2_in_3_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_1_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001492091 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001492091 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 9.076629e-05 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 9.076629e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.000119197 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.000119197 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001436254 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001436254 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 9.046144e-05 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 9.046144e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:335 3.310135e-05 +13 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:341 3.310135e-05 +14 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 prog_clk[0]:335 9.321722e-06 +15 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 prog_clk[0]:341 2.556181e-05 +16 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 prog_clk[0]:341 9.321722e-06 +17 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 prog_clk[0]:342 2.556181e-05 +18 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 top_left_grid_pin_41_[0]:6 0.0001179937 +19 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 top_left_grid_pin_41_[0]:7 0.0001179937 +20 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size8_0_sram[1]:25 7.719666e-05 +21 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size8_0_sram[1]:16 1.74855e-05 +22 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size8_0_sram[1]:16 7.719666e-05 +23 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size8_0_sram[1]:15 1.74855e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_3_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_2\/mux_l3_in_1_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002546875 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002348214 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0015625 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0045 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.002348215 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0009040179 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0] 0.001255674 //LENGTH 9.140 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l3_in_0_:X O *L 0 *C 74.345 30.600 +*I mux_bottom_track_9\/mux_l4_in_0_:A1 I *L 0.005458 *C 82.040 31.558 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 80.040 31.620 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 80.040 30.600 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 74.383 30.600 + +*CAP +0 mux_bottom_track_9\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l4_in_0_:A1 0.00017469 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0002389674 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0004526468 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0003883695 + +*RES +0 mux_bottom_track_9\/mux_l3_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.00505134 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0009107143 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_9\/mux_l4_in_0_:A1 0.001785714 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008888454 //LENGTH 7.620 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_2_:X O *L 0 *C 51.805 117.980 +*I mux_top_track_4\/mux_l2_in_1_:A1 I *L 0.00198 *C 53.460 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 53.360 112.540 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 53.360 112.585 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 53.360 117.935 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 53.315 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 51.843 117.980 + +*CAP +0 mux_top_track_4\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.388064e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0003085047 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003085047 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001179777 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001179777 + +*RES +0 mux_top_track_4\/mux_l1_in_2_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_4\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.004776786 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0] 0.0008628776 //LENGTH 6.035 LUMPCC 0.000113137 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_0_:X O *L 0 *C 44.445 9.860 +*I mux_bottom_track_5\/mux_l4_in_0_:A1 I *L 0.00198 *C 47.020 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 46.983 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 44.665 12.580 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 44.620 12.535 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 *C 44.620 9.905 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 *C 44.620 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:7 *C 44.445 9.860 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0001949912 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0001949912 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.0001203571 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0001203571 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 5.423285e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:7 6.281124e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:11 9.02697e-06 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:15 1.422895e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_tree_tapbuf_size14_1_sram[2]:17 3.33126e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:14 1.422895e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:15 9.02697e-06 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_tree_tapbuf_size14_1_sram[2]:16 3.33126e-05 + +*RES +0 mux_bottom_track_5\/mux_l3_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_bottom_track_5\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.002069196 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.002348215 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_11_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0] 0.004210926 //LENGTH 35.425 LUMPCC 0.0005061334 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_2_:X O *L 0 *C 39.385 56.440 +*I mux_top_track_16\/mux_l2_in_1_:A1 I *L 0.00198 *C 49.780 79.900 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 49.742 79.900 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 47.425 79.900 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 47.380 79.855 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 47.380 77.905 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 47.335 77.860 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 40.065 77.860 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 40.020 77.815 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 40.020 56.485 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 39.975 56.440 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 39.422 56.440 + +*CAP +0 mux_top_track_16\/mux_l1_in_2_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_1_:A1 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001312673 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001312673 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001276641 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001276641 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0004678778 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0004678778 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001056537 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001056537 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 6.804976e-05 +11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 6.804976e-05 +12 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_0_sram[0]:21 2.62758e-06 +13 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_0_sram[0]:20 2.62758e-06 +14 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size7_0_sram[0]:15 6.546439e-05 +15 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size7_0_sram[0]:17 0.0001082623 +16 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size7_0_sram[0]:12 6.546439e-05 +17 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size7_0_sram[0]:16 0.0001082623 +18 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.671241e-05 +19 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:4 7.671241e-05 + +*RES +0 mux_top_track_16\/mux_l1_in_2_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_16\/mux_l2_in_1_:A1 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002069197 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001741072 +6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.006491072 +7 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +8 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.01904465 +10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_top_track_16/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0004933036 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.00164654 //LENGTH 12.075 LUMPCC 0.0004072427 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_2_:X O *L 0 *C 43.525 55.080 +*I mux_bottom_track_17\/mux_l2_in_1_:A1 I *L 0.00198 *C 44.720 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 44.683 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 44.205 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 44.160 47.305 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 44.160 50.955 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 44.115 51.000 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 42.825 51.000 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 42.780 51.045 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 42.780 55.035 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 42.825 55.080 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 43.488 55.080 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.461348e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.461348e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002413619 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0002413619 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001214996 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001214996 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001147464 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001147464 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 8.642738e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 8.642738e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size4_3_sram[0]:7 1.253921e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_3_sram[0]:8 2.963431e-06 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size4_3_sram[0]:6 1.253921e-05 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size4_3_sram[0]:9 2.963431e-06 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size4_3_sram[0]:7 7.166861e-05 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size4_3_sram[0]:6 7.166861e-05 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:11 1.849812e-06 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:10 1.849812e-06 +20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size7_2_sram[0]:11 0.0001146003 +21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size7_2_sram[0]:10 0.0001146003 + +*RES +0 mux_bottom_track_17\/mux_l1_in_2_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_17\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0004263393 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003258929 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001151786 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0035625 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0005915179 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003840571 //LENGTH 23.205 LUMPCC 0.001413101 DR + +*CONN +*I mux_left_track_3\/mux_l2_in_0_:X O *L 0 *C 28.235 80.920 +*I mux_left_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 9.565 83.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 9.565 83.300 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 9.660 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 18.355 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 18.400 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 18.408 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 24.820 83.640 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 24.840 83.633 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 24.840 80.928 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 24.860 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 28.053 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 28.060 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 *C 28.060 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 *C 28.235 80.920 + +*CAP +0 mux_left_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.529158e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0005870626 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0005597944 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 3.92368e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001571623 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001571623 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001821951 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001821951 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001805093 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0001805093 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 3.544081e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 5.588138e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 5.302871e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 chanx_left_in[4]:12 0.0001537177 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 chanx_left_in[4]:11 0.0001537177 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001273766 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001273766 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003769025 +20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003769025 +21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 4.855377e-05 +22 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 4.855377e-05 + +*RES +0 mux_left_track_3\/mux_l2_in_0_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.007763394 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001004625 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.00341 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0004237833 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.00341 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0005001583 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0045 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 9.51087e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000862559 //LENGTH 6.930 LUMPCC 8.821962e-05 DR + +*CONN +*I mux_top_track_32\/mux_l1_in_1_:X O *L 0 *C 63.305 75.480 +*I mux_top_track_32\/mux_l2_in_0_:A0 I *L 0.001631 *C 67.795 77.180 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 67.758 77.180 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 63.525 77.180 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 63.480 77.135 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 63.480 75.525 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 63.480 75.480 +*N mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 63.305 75.480 + +*CAP +0 mux_top_track_32\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_32\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002561369 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002561369 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.983147e-05 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.983147e-05 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.234336e-05 +7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.805922e-05 +8 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_top_in[17]:23 1.877167e-05 +9 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_top_in[17]:22 1.877167e-05 +10 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_top_in[17]:24 2.533814e-05 +11 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_top_in[17]:21 2.533814e-05 + +*RES +0 mux_top_track_32\/mux_l1_in_1_:X mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_32\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003779018 +3 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_32/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0006426179 //LENGTH 4.625 LUMPCC 0.0001296236 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_1_:X O *L 0 *C 22.825 33.320 +*I mux_bottom_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 20.990 31.620 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 21.027 31.620 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 22.955 31.620 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 23.000 31.665 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 23.000 33.275 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 23.000 33.320 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 22.825 33.320 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001057836 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001057836 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.37024e-05 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.37024e-05 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.522527e-05 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.679714e-05 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size6_2_sram[0]:17 4.731333e-05 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size6_2_sram[0]:18 4.731333e-05 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_2_sram[0]:16 1.749848e-05 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_2_sram[0]:15 1.749848e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_1_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001720982 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0005778612 //LENGTH 3.280 LUMPCC 0.0001332432 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_3_:X O *L 0 *C 25.585 46.920 +*I mux_bottom_track_3\/mux_l3_in_1_:A0 I *L 0.001631 *C 25.055 44.540 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 25.055 44.540 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 25.300 44.540 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 25.300 44.585 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 25.300 46.875 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 25.300 46.920 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 25.585 46.920 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_3_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_1_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 6.012772e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 6.458419e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001008631 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001008631 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 5.864091e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 5.753888e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_tree_tapbuf_size9_0_sram[1]:20 6.662161e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_tree_tapbuf_size9_0_sram[1]:24 6.662161e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_3_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0001548913 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002044643 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001331522 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_3\/mux_l3_in_1_:A0 0.152 + +*END + +*D_NET mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001035581 //LENGTH 7.840 LUMPCC 0.0003295402 DR + +*CONN +*I mux_left_track_13\/mux_l1_in_0_:X O *L 0 *C 53.535 45.220 +*I mux_left_track_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 48.665 47.260 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 48.703 47.260 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 50.095 47.260 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 50.140 47.215 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 50.140 45.265 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 50.185 45.220 +*N mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 53.498 45.220 + +*CAP +0 mux_left_track_13\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_13\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.411813e-05 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.411813e-05 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001138765 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001138765 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001640256 +7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001640256 +8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size4_2_sram[0]:7 1.340168e-05 +9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size4_2_sram[0]:9 8.590215e-05 +10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size4_2_sram[0]:8 1.340168e-05 +11 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size4_2_sram[0]:10 8.590215e-05 +12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size4_2_sram[1]:13 6.546626e-05 +13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size4_2_sram[1]:14 6.546626e-05 + +*RES +0 mux_left_track_13\/mux_l1_in_0_:X mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_13\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001243304 +3 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.001741072 +6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002957589 + +*END + +*D_NET mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002157081 //LENGTH 14.700 LUMPCC 0.0004634337 DR + +*CONN +*I mux_left_track_17\/mux_l2_in_0_:X O *L 0 *C 16.735 52.360 +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 7.925 47.770 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 7.925 47.770 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 7.820 47.940 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 7.820 47.985 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 7.820 49.595 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 7.865 49.640 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 16.515 49.640 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 16.560 49.685 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 16.560 52.315 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 16.560 52.360 +*N mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 16.735 52.360 + +*CAP +0 mux_left_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.79536e-05 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 6.167886e-05 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001194416 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001194416 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0005035085 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0005035085 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0001083587 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001083587 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 5.603695e-05 +11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 5.335989e-05 +12 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:6 0.0001482901 +13 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size4_mem_3_ccff_tail[0]:7 0.0001482901 +14 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_tree_tapbuf_size7_3_sram[0]:26 8.342673e-05 +15 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size7_3_sram[0]:27 8.342673e-05 + +*RES +0 mux_left_track_17\/mux_l2_in_0_:X mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.152 +1 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 9.51087e-05 +2 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0045 +3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.002348214 +4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.007723215 +5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0045 +6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +7 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +8 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.706522e-05 +9 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +10 mux_left_track_17/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0] 0.005196765 //LENGTH 34.540 LUMPCC 0.001892657 DR + +*CONN +*I mux_left_track_23\/mux_l2_in_0_:X O *L 0 *C 38.815 82.960 +*I mux_left_track_23\/BUFT_RR_68:A I *L 0.001776 *C 8.280 85.680 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 8.318 85.680 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 9.155 85.680 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 9.200 85.635 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 9.200 83.017 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 9.207 82.960 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 38.172 82.960 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 38.180 82.960 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 38.225 82.960 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 38.778 82.960 + +*CAP +0 mux_left_track_23\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_23\/BUFT_RR_68:A 1e-06 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.277723e-05 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.277723e-05 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.000167322 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.000167322 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001341224 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001341224 +8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 3.398738e-05 +9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 5.273695e-05 +10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:10 5.273695e-05 +11 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[13]:24 9.45224e-05 +12 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chany_bottom_in[13]:26 4.678254e-05 +13 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[13]:23 9.45224e-05 +14 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chany_bottom_in[13]:25 4.678254e-05 +15 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[4]:11 0.0002492139 +16 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 chanx_left_in[4]:12 0.0002492139 +17 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 left_top_grid_pin_48_[0]:9 0.0001303536 +18 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 left_top_grid_pin_48_[0]:10 0.0001303536 +19 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0003769025 +20 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 4.855377e-05 +21 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0003769025 +22 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 4.855377e-05 + +*RES +0 mux_left_track_23\/mux_l2_in_0_:X mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0004933036 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0045 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.00341 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.00453785 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002337054 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0007477679 +8 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +9 mux_left_track_23/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_23\/BUFT_RR_68:A 0.152 + +*END + +*D_NET ropt_net_188 0.00123461 //LENGTH 8.330 LUMPCC 0.0002963782 DR + +*CONN +*I ropt_mt_inst_774:X O *L 0 *C 7.095 53.720 +*I ropt_mt_inst_817:A I *L 0.001767 *C 3.220 55.760 +*N ropt_net_188:2 *C 3.220 55.760 +*N ropt_net_188:3 *C 3.220 55.805 +*N ropt_net_188:4 *C 3.220 56.395 +*N ropt_net_188:5 *C 3.265 56.440 +*N ropt_net_188:6 *C 6.855 56.440 +*N ropt_net_188:7 *C 6.900 56.395 +*N ropt_net_188:8 *C 6.900 53.765 +*N ropt_net_188:9 *C 6.900 53.720 +*N ropt_net_188:10 *C 7.095 53.720 + +*CAP +0 ropt_mt_inst_774:X 1e-06 +1 ropt_mt_inst_817:A 1e-06 +2 ropt_net_188:2 3.217321e-05 +3 ropt_net_188:3 7.38212e-05 +4 ropt_net_188:4 7.38212e-05 +5 ropt_net_188:5 0.0001528499 +6 ropt_net_188:6 0.0001528499 +7 ropt_net_188:7 0.000169009 +8 ropt_net_188:8 0.000169009 +9 ropt_net_188:9 5.695884e-05 +10 ropt_net_188:10 5.57395e-05 +11 ropt_net_188:8 chany_top_in[15]:12 3.455835e-06 +12 ropt_net_188:6 chany_top_in[15]:7 0.0001430361 +13 ropt_net_188:6 chany_top_in[15]:9 1.697181e-06 +14 ropt_net_188:7 chany_top_in[15]:11 3.455835e-06 +15 ropt_net_188:5 chany_top_in[15]:6 0.0001430361 +16 ropt_net_188:5 chany_top_in[15]:8 1.697181e-06 + +*RES +0 ropt_mt_inst_774:X ropt_net_188:10 0.152 +1 ropt_net_188:10 ropt_net_188:9 0.0001059783 +2 ropt_net_188:9 ropt_net_188:8 0.0045 +3 ropt_net_188:8 ropt_net_188:7 0.002348214 +4 ropt_net_188:6 ropt_net_188:5 0.003205357 +5 ropt_net_188:7 ropt_net_188:6 0.0045 +6 ropt_net_188:5 ropt_net_188:4 0.0045 +7 ropt_net_188:4 ropt_net_188:3 0.0005267857 +8 ropt_net_188:2 ropt_mt_inst_817:A 0.152 +9 ropt_net_188:3 ropt_net_188:2 0.0045 + +*END + +*D_NET ropt_net_200 0.0006709682 //LENGTH 4.495 LUMPCC 0.0002625926 DR + +*CONN +*I ropt_mt_inst_783:X O *L 0 *C 77.110 9.180 +*I ropt_mt_inst_834:A I *L 0.001767 *C 77.280 6.800 +*N ropt_net_200:2 *C 77.318 6.800 +*N ropt_net_200:3 *C 77.695 6.800 +*N ropt_net_200:4 *C 77.740 6.845 +*N ropt_net_200:5 *C 77.740 7.820 +*N ropt_net_200:6 *C 77.280 7.820 +*N ropt_net_200:7 *C 77.280 9.135 +*N ropt_net_200:8 *C 77.280 9.180 +*N ropt_net_200:9 *C 77.110 9.180 + +*CAP +0 ropt_mt_inst_783:X 1e-06 +1 ropt_mt_inst_834:A 1e-06 +2 ropt_net_200:2 3.076538e-05 +3 ropt_net_200:3 3.076538e-05 +4 ropt_net_200:4 6.423867e-05 +5 ropt_net_200:5 5.18396e-05 +6 ropt_net_200:6 5.082147e-05 +7 ropt_net_200:7 6.322053e-05 +8 ropt_net_200:8 5.925899e-05 +9 ropt_net_200:9 5.546557e-05 +10 ropt_net_200:7 chany_bottom_in[16]:29 4.001013e-05 +11 ropt_net_200:4 chany_bottom_in[16] 9.941968e-06 +12 ropt_net_200:6 chany_bottom_in[16] 4.001013e-05 +13 ropt_net_200:5 chany_bottom_in[16]:29 9.941968e-06 +14 ropt_net_200:9 ropt_net_157:10 1.032223e-05 +15 ropt_net_200:8 ropt_net_157:11 1.032223e-05 +16 ropt_net_200:7 ropt_net_157:9 6.599708e-08 +17 ropt_net_200:6 ropt_net_157:8 6.599708e-08 +18 ropt_net_200:6 ropt_net_157:10 2.983588e-05 +19 ropt_net_200:5 ropt_net_157:11 2.983588e-05 +20 ropt_net_200:3 chany_bottom_out[5]:9 2.722933e-05 +21 ropt_net_200:2 chany_bottom_out[5]:8 2.722933e-05 +22 ropt_net_200:6 chany_bottom_out[5]:8 1.389078e-05 +23 ropt_net_200:5 chany_bottom_out[5]:9 1.389078e-05 + +*RES +0 ropt_mt_inst_783:X ropt_net_200:9 0.152 +1 ropt_net_200:9 ropt_net_200:8 9.239131e-05 +2 ropt_net_200:8 ropt_net_200:7 0.0045 +3 ropt_net_200:7 ropt_net_200:6 0.001174107 +4 ropt_net_200:3 ropt_net_200:2 0.0003370536 +5 ropt_net_200:4 ropt_net_200:3 0.0045 +6 ropt_net_200:2 ropt_mt_inst_834:A 0.152 +7 ropt_net_200:6 ropt_net_200:5 0.0004107143 +8 ropt_net_200:5 ropt_net_200:4 0.0008705358 + +*END + +*D_NET ropt_net_149 0.002184327 //LENGTH 19.210 LUMPCC 0.000415444 DR + +*CONN +*I BUFT_RR_74:X O *L 0 *C 4.600 69.020 +*I ropt_mt_inst_774:A I *L 0.001766 *C 3.220 53.040 +*N ropt_net_149:2 *C 3.183 53.040 +*N ropt_net_149:3 *C 2.805 53.040 +*N ropt_net_149:4 *C 2.760 53.085 +*N ropt_net_149:5 *C 2.760 68.975 +*N ropt_net_149:6 *C 2.805 69.020 +*N ropt_net_149:7 *C 4.562 69.020 + +*CAP +0 BUFT_RR_74:X 1e-06 +1 ropt_mt_inst_774:A 1e-06 +2 ropt_net_149:2 4.041766e-05 +3 ropt_net_149:3 4.041766e-05 +4 ropt_net_149:4 0.0007281885 +5 ropt_net_149:5 0.0007281885 +6 ropt_net_149:6 0.0001148352 +7 ropt_net_149:7 0.0001148352 +8 ropt_net_149:5 chany_top_in[15]:5 8.926139e-05 +9 ropt_net_149:4 chany_top_in[15]:4 8.926139e-05 +10 ropt_net_149:5 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001184606 +11 ropt_net_149:4 mux_left_track_21/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0001184606 + +*RES +0 BUFT_RR_74:X ropt_net_149:7 0.152 +1 ropt_net_149:7 ropt_net_149:6 0.001569197 +2 ropt_net_149:6 ropt_net_149:5 0.0045 +3 ropt_net_149:5 ropt_net_149:4 0.0141875 +4 ropt_net_149:3 ropt_net_149:2 0.0003370536 +5 ropt_net_149:4 ropt_net_149:3 0.0045 +6 ropt_net_149:2 ropt_mt_inst_774:A 0.152 + +*END + +*D_NET ropt_net_187 0.001834192 //LENGTH 12.295 LUMPCC 0.0005871757 DR + +*CONN +*I ropt_mt_inst_800:X O *L 0 *C 68.275 121.720 +*I ropt_mt_inst_816:A I *L 0.001766 *C 65.780 126.480 +*N ropt_net_187:2 *C 65.743 126.480 +*N ropt_net_187:3 *C 63.985 126.480 +*N ropt_net_187:4 *C 63.940 126.435 +*N ropt_net_187:5 *C 63.940 124.485 +*N ropt_net_187:6 *C 63.985 124.440 +*N ropt_net_187:7 *C 68.035 124.440 +*N ropt_net_187:8 *C 68.080 124.395 +*N ropt_net_187:9 *C 68.080 121.765 +*N ropt_net_187:10 *C 68.080 121.720 +*N ropt_net_187:11 *C 68.275 121.720 + +*CAP +0 ropt_mt_inst_800:X 1e-06 +1 ropt_mt_inst_816:A 1e-06 +2 ropt_net_187:2 8.240979e-05 +3 ropt_net_187:3 8.240979e-05 +4 ropt_net_187:4 9.915451e-05 +5 ropt_net_187:5 9.915451e-05 +6 ropt_net_187:6 0.0002562536 +7 ropt_net_187:7 0.0002562536 +8 ropt_net_187:8 0.0001276867 +9 ropt_net_187:9 0.0001276867 +10 ropt_net_187:10 5.932512e-05 +11 ropt_net_187:11 5.468227e-05 +12 ropt_net_187:5 chany_top_in[13]:35 6.29719e-05 +13 ropt_net_187:4 chany_top_in[13] 6.29719e-05 +14 ropt_net_187:7 chany_bottom_in[12]:5 7.42124e-05 +15 ropt_net_187:6 chany_bottom_in[12]:10 7.42124e-05 +16 ropt_net_187:9 chany_top_out[8]:2 4.146818e-05 +17 ropt_net_187:9 chany_top_out[8]:6 3.593909e-05 +18 ropt_net_187:7 chany_top_out[8]:3 1.446594e-06 +19 ropt_net_187:8 chany_top_out[8] 4.146818e-05 +20 ropt_net_187:8 chany_top_out[8]:5 3.593909e-05 +21 ropt_net_187:6 chany_top_out[8]:4 1.446594e-06 +22 ropt_net_187:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:4 7.754965e-05 +23 ropt_net_187:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_9_X[0]:3 7.754965e-05 + +*RES +0 ropt_mt_inst_800:X ropt_net_187:11 0.152 +1 ropt_net_187:11 ropt_net_187:10 0.0001059783 +2 ropt_net_187:10 ropt_net_187:9 0.0045 +3 ropt_net_187:9 ropt_net_187:8 0.002348214 +4 ropt_net_187:7 ropt_net_187:6 0.003616072 +5 ropt_net_187:8 ropt_net_187:7 0.0045 +6 ropt_net_187:6 ropt_net_187:5 0.0045 +7 ropt_net_187:5 ropt_net_187:4 0.001741071 +8 ropt_net_187:3 ropt_net_187:2 0.001569197 +9 ropt_net_187:4 ropt_net_187:3 0.0045 +10 ropt_net_187:2 ropt_mt_inst_816:A 0.152 + +*END + +*D_NET chany_bottom_out[19] 0.00131597 //LENGTH 9.375 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_835:X O *L 0 *C 73.600 7.140 +*P chany_bottom_out[19] O *L 0.7423 *C 70.840 1.325 +*N chany_bottom_out[19]:2 *C 70.840 1.655 +*N chany_bottom_out[19]:3 *C 70.885 1.700 +*N chany_bottom_out[19]:4 *C 73.555 1.700 +*N chany_bottom_out[19]:5 *C 73.600 1.745 +*N chany_bottom_out[19]:6 *C 73.600 7.095 +*N chany_bottom_out[19]:7 *C 73.600 7.140 + +*CAP +0 ropt_mt_inst_835:X 1e-06 +1 chany_bottom_out[19] 3.496403e-05 +2 chany_bottom_out[19]:2 3.496403e-05 +3 chany_bottom_out[19]:3 0.0001775677 +4 chany_bottom_out[19]:4 0.0001775677 +5 chany_bottom_out[19]:5 0.000427882 +6 chany_bottom_out[19]:6 0.000427882 +7 chany_bottom_out[19]:7 3.414321e-05 + +*RES +0 ropt_mt_inst_835:X chany_bottom_out[19]:7 0.152 +1 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.0045 +2 chany_bottom_out[19]:2 chany_bottom_out[19] 0.0002946428 +3 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.002383929 +4 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.0045 +5 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.0045 +6 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.004776786 + +*END + +*D_NET ropt_net_167 0.0007120008 //LENGTH 6.100 LUMPCC 0 DR + +*CONN +*I BUFT_P_129:X O *L 0 *C 92.635 120.700 +*I ropt_mt_inst_792:A I *L 0.001766 *C 97.825 121.040 +*N ropt_net_167:2 *C 97.788 121.040 +*N ropt_net_167:3 *C 97.060 121.040 +*N ropt_net_167:4 *C 97.060 120.700 +*N ropt_net_167:5 *C 92.672 120.700 + +*CAP +0 BUFT_P_129:X 1e-06 +1 ropt_mt_inst_792:A 1e-06 +2 ropt_net_167:2 6.501115e-05 +3 ropt_net_167:3 9.118606e-05 +4 ropt_net_167:4 0.0002899893 +5 ropt_net_167:5 0.0002638143 + +*RES +0 BUFT_P_129:X ropt_net_167:5 0.152 +1 ropt_net_167:5 ropt_net_167:4 0.003917411 +2 ropt_net_167:2 ropt_mt_inst_792:A 0.152 +3 ropt_net_167:4 ropt_net_167:3 0.0003035715 +4 ropt_net_167:3 ropt_net_167:2 0.0006495537 + +*END + +*D_NET chany_top_in[15] 0.0190718 //LENGTH 144.455 LUMPCC 0.006724939 DR + +*CONN +*P chany_top_in[15] I *L 0.29796 *C 53.820 129.270 +*I ropt_mt_inst_778:A I *L 0.001767 *C 3.220 42.160 +*N chany_top_in[15]:2 *C 3.183 42.160 +*N chany_top_in[15]:3 *C 2.345 42.160 +*N chany_top_in[15]:4 *C 2.300 42.160 +*N chany_top_in[15]:5 *C 2.300 56.055 +*N chany_top_in[15]:6 *C 2.345 56.100 +*N chany_top_in[15]:7 *C 6.900 56.100 +*N chany_top_in[15]:8 *C 6.900 55.730 +*N chany_top_in[15]:9 *C 7.770 55.730 +*N chany_top_in[15]:10 *C 7.820 55.420 +*N chany_top_in[15]:11 *C 7.820 55.420 +*N chany_top_in[15]:12 *C 7.820 55.080 +*N chany_top_in[15]:13 *C 7.828 55.080 +*N chany_top_in[15]:14 *C 53.340 55.080 +*N chany_top_in[15]:15 *C 53.360 55.088 +*N chany_top_in[15]:16 *C 53.360 104.915 +*N chany_top_in[15]:17 *C 53.360 123.073 +*N chany_top_in[15]:18 *C 53.375 123.080 +*N chany_top_in[15]:19 *C 53.818 123.080 +*N chany_top_in[15]:20 *C 53.820 123.138 + +*CAP +0 chany_top_in[15] 0.0003227346 +1 ropt_mt_inst_778:A 1e-06 +2 chany_top_in[15]:2 6.62817e-05 +3 chany_top_in[15]:3 6.62817e-05 +4 chany_top_in[15]:4 0.0007296258 +5 chany_top_in[15]:5 0.0006991141 +6 chany_top_in[15]:6 0.0002061395 +7 chany_top_in[15]:7 0.0002366492 +8 chany_top_in[15]:8 0.000108029 +9 chany_top_in[15]:9 0.000115255 +10 chany_top_in[15]:10 7.662851e-05 +11 chany_top_in[15]:11 5.15497e-05 +12 chany_top_in[15]:12 5.57457e-05 +13 chany_top_in[15]:13 0.002226414 +14 chany_top_in[15]:14 0.002226414 +15 chany_top_in[15]:15 0.001782306 +16 chany_top_in[15]:16 0.002344938 +17 chany_top_in[15]:17 0.0005626321 +18 chany_top_in[15]:18 7.319047e-05 +19 chany_top_in[15]:19 7.319047e-05 +20 chany_top_in[15]:20 0.0003227346 +21 chany_top_in[15] chany_top_in[4] 5.390852e-06 +22 chany_top_in[15]:13 chany_top_in[4]:20 0.0002825469 +23 chany_top_in[15]:13 chany_top_in[4]:21 5.771182e-05 +24 chany_top_in[15]:14 chany_top_in[4]:12 5.771182e-05 +25 chany_top_in[15]:14 chany_top_in[4]:21 0.0002825469 +26 chany_top_in[15]:20 chany_top_in[4]:33 5.390852e-06 +27 chany_top_in[15] chany_top_in[14] 4.115813e-05 +28 chany_top_in[15]:13 chany_top_in[14]:8 7.502507e-07 +29 chany_top_in[15]:13 chany_top_in[14]:21 1.712631e-05 +30 chany_top_in[15]:14 chany_top_in[14]:21 7.502507e-07 +31 chany_top_in[15]:14 chany_top_in[14]:22 1.712631e-05 +32 chany_top_in[15]:15 chany_top_in[14]:23 0.0009599623 +33 chany_top_in[15]:17 chany_top_in[14]:24 7.328357e-05 +34 chany_top_in[15]:17 chany_top_in[14]:25 0.0002984474 +35 chany_top_in[15]:20 chany_top_in[14]:28 4.115813e-05 +36 chany_top_in[15]:16 chany_top_in[14]:23 7.328357e-05 +37 chany_top_in[15]:16 chany_top_in[14]:24 0.00125841 +38 chany_top_in[15]:15 chany_bottom_in[2]:23 0.0002969114 +39 chany_top_in[15]:17 chany_bottom_in[2]:22 0.0002569715 +40 chany_top_in[15]:16 chany_bottom_in[2]:23 0.0002569715 +41 chany_top_in[15]:16 chany_bottom_in[2]:22 0.0002969114 +42 chany_top_in[15]:4 prog_clk[0]:525 6.958355e-06 +43 chany_top_in[15]:4 prog_clk[0]:526 1.331122e-06 +44 chany_top_in[15]:5 prog_clk[0]:400 6.958355e-06 +45 chany_top_in[15]:5 prog_clk[0]:525 1.331122e-06 +46 chany_top_in[15]:11 prog_clk[0]:383 8.958289e-08 +47 chany_top_in[15]:12 prog_clk[0]:400 8.958289e-08 +48 chany_top_in[15]:13 prog_clk[0]:228 5.431983e-06 +49 chany_top_in[15]:13 prog_clk[0]:234 1.31523e-05 +50 chany_top_in[15]:13 prog_clk[0]:398 9.40141e-06 +51 chany_top_in[15]:13 prog_clk[0]:391 0.0002142879 +52 chany_top_in[15]:14 prog_clk[0]:227 5.431983e-06 +53 chany_top_in[15]:14 prog_clk[0]:215 1.31523e-05 +54 chany_top_in[15]:14 prog_clk[0]:394 9.40141e-06 +55 chany_top_in[15]:14 prog_clk[0]:390 0.0002142879 +56 chany_top_in[15]:15 prog_clk[0]:225 5.74235e-06 +57 chany_top_in[15]:15 prog_clk[0]:413 1.604699e-05 +58 chany_top_in[15]:16 prog_clk[0]:456 1.604699e-05 +59 chany_top_in[15]:16 prog_clk[0]:222 5.74235e-06 +60 chany_top_in[15]:13 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.0001678936 +61 chany_top_in[15]:14 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0001678936 +62 chany_top_in[15]:13 mux_tree_tapbuf_size4_3_sram[1]:11 9.035799e-05 +63 chany_top_in[15]:13 mux_tree_tapbuf_size4_3_sram[1]:17 0.0003040651 +64 chany_top_in[15]:14 mux_tree_tapbuf_size4_3_sram[1]:16 9.035799e-05 +65 chany_top_in[15]:14 mux_tree_tapbuf_size4_3_sram[1]:18 0.0003040651 +66 chany_top_in[15]:6 ropt_net_188:5 0.0001430361 +67 chany_top_in[15]:11 ropt_net_188:7 3.455835e-06 +68 chany_top_in[15]:12 ropt_net_188:8 3.455835e-06 +69 chany_top_in[15]:7 ropt_net_188:6 0.0001430361 +70 chany_top_in[15]:8 ropt_net_188:5 1.697181e-06 +71 chany_top_in[15]:9 ropt_net_188:6 1.697181e-06 +72 chany_top_in[15]:4 ropt_net_149:4 8.926139e-05 +73 chany_top_in[15]:5 ropt_net_149:5 8.926139e-05 + +*RES +0 chany_top_in[15] chany_top_in[15]:20 0.005475447 +1 chany_top_in[15]:2 ropt_mt_inst_778:A 0.152 +2 chany_top_in[15]:3 chany_top_in[15]:2 0.0007477679 +3 chany_top_in[15]:4 chany_top_in[15]:3 0.0045 +4 chany_top_in[15]:6 chany_top_in[15]:5 0.0045 +5 chany_top_in[15]:5 chany_top_in[15]:4 0.01240625 +6 chany_top_in[15]:10 chany_top_in[15]:9 0.0001270492 +7 chany_top_in[15]:11 chany_top_in[15]:10 0.0045 +8 chany_top_in[15]:12 chany_top_in[15]:11 0.0001634615 +9 chany_top_in[15]:13 chany_top_in[15]:12 0.00341 +10 chany_top_in[15]:14 chany_top_in[15]:13 0.007130291 +11 chany_top_in[15]:15 chany_top_in[15]:14 0.00341 +12 chany_top_in[15]:18 chany_top_in[15]:17 0.00341 +13 chany_top_in[15]:17 chany_top_in[15]:16 0.002844675 +14 chany_top_in[15]:20 chany_top_in[15]:19 0.00341 +15 chany_top_in[15]:19 chany_top_in[15]:18 6.499219e-05 +16 chany_top_in[15]:7 chany_top_in[15]:6 0.004066965 +17 chany_top_in[15]:8 chany_top_in[15]:7 0.0003303571 +18 chany_top_in[15]:9 chany_top_in[15]:8 0.0007767858 +19 chany_top_in[15]:16 chany_top_in[15]:15 0.007806308 + +*END + +*D_NET chanx_left_in[15] 0.01377428 //LENGTH 89.520 LUMPCC 0.005095425 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 77.520 +*I mux_bottom_track_1\/mux_l2_in_3_:A1 I *L 0.00198 *C 47.020 36.380 +*I mux_top_track_32\/mux_l1_in_2_:A0 I *L 0.001631 *C 48.475 71.400 +*N chanx_left_in[15]:3 *C 48.438 71.400 +*N chanx_left_in[15]:4 *C 46.920 36.380 +*N chanx_left_in[15]:5 *C 46.920 36.425 +*N chanx_left_in[15]:6 *C 46.920 71.355 +*N chanx_left_in[15]:7 *C 46.920 71.400 +*N chanx_left_in[15]:8 *C 45.125 71.400 +*N chanx_left_in[15]:9 *C 45.080 71.445 +*N chanx_left_in[15]:10 *C 45.080 77.463 +*N chanx_left_in[15]:11 *C 45.073 77.520 + +*CAP +0 chanx_left_in[15] 0.001783478 +1 mux_bottom_track_1\/mux_l2_in_3_:A1 1e-06 +2 mux_top_track_32\/mux_l1_in_2_:A0 1e-06 +3 chanx_left_in[15]:3 0.0001391366 +4 chanx_left_in[15]:4 3.149535e-05 +5 chanx_left_in[15]:5 0.001903796 +6 chanx_left_in[15]:6 0.001903796 +7 chanx_left_in[15]:7 0.0003341815 +8 chanx_left_in[15]:8 0.0001636901 +9 chanx_left_in[15]:9 0.0003169027 +10 chanx_left_in[15]:10 0.0003169027 +11 chanx_left_in[15]:11 0.001783478 +12 chanx_left_in[15] chany_top_in[11]:10 0.0004434711 +13 chanx_left_in[15]:11 chany_top_in[11]:11 0.0004434711 +14 chanx_left_in[15] left_top_grid_pin_43_[0]:26 0.0007259487 +15 chanx_left_in[15]:11 left_top_grid_pin_43_[0]:25 0.0007259487 +16 chanx_left_in[15] chanx_left_in[0]:22 0.0005855809 +17 chanx_left_in[15]:11 chanx_left_in[0]:21 0.0005855809 +18 chanx_left_in[15] mux_tree_tapbuf_size7_0_sram[0]:18 0.000331542 +19 chanx_left_in[15]:11 mux_tree_tapbuf_size7_0_sram[0]:19 0.000331542 +20 chanx_left_in[15]:9 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 7.471628e-05 +21 chanx_left_in[15]:10 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 7.471628e-05 +22 chanx_left_in[15]:6 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:5 9.480173e-07 +23 chanx_left_in[15]:5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.480173e-07 +24 chanx_left_in[15]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0001740551 +25 chanx_left_in[15]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0001740551 +26 chanx_left_in[15] mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002114508 +27 chanx_left_in[15]:11 mux_left_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002114508 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:11 0.006868658 +1 chanx_left_in[15]:8 chanx_left_in[15]:7 0.001602679 +2 chanx_left_in[15]:9 chanx_left_in[15]:8 0.0045 +3 chanx_left_in[15]:10 chanx_left_in[15]:9 0.005372768 +4 chanx_left_in[15]:11 chanx_left_in[15]:10 0.00341 +5 chanx_left_in[15]:7 chanx_left_in[15]:6 0.0045 +6 chanx_left_in[15]:7 chanx_left_in[15]:3 0.001354911 +7 chanx_left_in[15]:6 chanx_left_in[15]:5 0.0311875 +8 chanx_left_in[15]:4 mux_bottom_track_1\/mux_l2_in_3_:A1 0.152 +9 chanx_left_in[15]:5 chanx_left_in[15]:4 0.0045 +10 chanx_left_in[15]:3 mux_top_track_32\/mux_l1_in_2_:A0 0.152 + +*END + +*D_NET ccff_head[0] 0.004323086 //LENGTH 38.165 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 107.640 129.350 +*I mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 79.295 120.700 +*N ccff_head[0]:2 *C 79.333 120.700 +*N ccff_head[0]:3 *C 80.915 120.700 +*N ccff_head[0]:4 *C 80.960 120.745 +*N ccff_head[0]:5 *C 80.960 123.703 +*N ccff_head[0]:6 *C 80.968 123.760 +*N ccff_head[0]:7 *C 107.620 123.760 +*N ccff_head[0]:8 *C 107.640 123.768 + +*CAP +0 ccff_head[0] 0.0002313774 +1 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 0.0001541455 +3 ccff_head[0]:3 0.0001541455 +4 ccff_head[0]:4 0.0002157766 +5 ccff_head[0]:5 0.0002157766 +6 ccff_head[0]:6 0.001559744 +7 ccff_head[0]:7 0.001559744 +8 ccff_head[0]:8 0.0002313774 + +*RES +0 ccff_head[0] ccff_head[0]:8 0.0008745916 +1 ccff_head[0]:2 mem_top_track_0\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.001412946 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 +4 ccff_head[0]:5 ccff_head[0]:4 0.002640625 +5 ccff_head[0]:6 ccff_head[0]:5 0.00341 +6 ccff_head[0]:7 ccff_head[0]:6 0.004175558 +7 ccff_head[0]:8 ccff_head[0]:7 0.00341 + +*END + +*D_NET chany_top_out[4] 0.003776404 //LENGTH 39.235 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l4_in_0_:X O *L 0 *C 90.400 99.280 +*P chany_top_out[4] O *L 0.7423 *C 98.900 129.270 +*N chany_top_out[4]:2 *C 98.900 99.665 +*N chany_top_out[4]:3 *C 98.855 99.620 +*N chany_top_out[4]:4 *C 91.080 99.620 +*N chany_top_out[4]:5 *C 91.080 99.280 +*N chany_top_out[4]:6 *C 90.438 99.280 + +*CAP +0 mux_top_track_8\/mux_l4_in_0_:X 1e-06 +1 chany_top_out[4] 0.001397663 +2 chany_top_out[4]:2 0.001397663 +3 chany_top_out[4]:3 0.0004156095 +4 chany_top_out[4]:4 0.0004379438 +5 chany_top_out[4]:5 7.44295e-05 +6 chany_top_out[4]:6 5.209521e-05 + +*RES +0 mux_top_track_8\/mux_l4_in_0_:X chany_top_out[4]:6 0.152 +1 chany_top_out[4]:6 chany_top_out[4]:5 0.0005736608 +2 chany_top_out[4]:3 chany_top_out[4]:2 0.0045 +3 chany_top_out[4]:2 chany_top_out[4] 0.02643304 +4 chany_top_out[4]:5 chany_top_out[4]:4 0.0003035715 +5 chany_top_out[4]:4 chany_top_out[4]:3 0.006941965 + +*END + +*D_NET chany_bottom_out[1] 0.002486586 //LENGTH 16.795 LUMPCC 0.0003780694 DR + +*CONN +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 49.280 6.460 +*P chany_bottom_out[1] O *L 0.7423 *C 59.800 1.290 +*N chany_bottom_out[1]:2 *C 59.800 4.375 +*N chany_bottom_out[1]:3 *C 59.755 4.420 +*N chany_bottom_out[1]:4 *C 49.725 4.420 +*N chany_bottom_out[1]:5 *C 49.680 4.465 +*N chany_bottom_out[1]:6 *C 49.680 6.415 +*N chany_bottom_out[1]:7 *C 49.657 6.460 +*N chany_bottom_out[1]:8 *C 49.295 6.460 + +*CAP +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[1] 0.0002009567 +2 chany_bottom_out[1]:2 0.0002009567 +3 chany_bottom_out[1]:3 0.0006986995 +4 chany_bottom_out[1]:4 0.0006986995 +5 chany_bottom_out[1]:5 8.605667e-05 +6 chany_bottom_out[1]:6 8.605667e-05 +7 chany_bottom_out[1]:7 6.80454e-05 +8 chany_bottom_out[1]:8 6.80454e-05 +9 chany_bottom_out[1]:5 ropt_net_171:3 2.950094e-06 +10 chany_bottom_out[1]:5 ropt_net_171:5 5.684857e-05 +11 chany_bottom_out[1]:6 ropt_net_171:6 5.684857e-05 +12 chany_bottom_out[1]:6 ropt_net_171:4 2.950094e-06 +13 chany_bottom_out[1]:3 ropt_net_196:3 0.000129236 +14 chany_bottom_out[1]:4 ropt_net_196:2 0.000129236 + +*RES +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[1]:8 0.152 +1 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +2 chany_bottom_out[1]:2 chany_bottom_out[1] 0.002754464 +3 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.008955358 +4 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0045 +5 chany_bottom_out[1]:7 chany_bottom_out[1]:6 0.0045 +6 chany_bottom_out[1]:6 chany_bottom_out[1]:5 0.001741071 +7 chany_bottom_out[1]:8 chany_bottom_out[1]:7 0.0001970109 + +*END + +*D_NET chanx_left_out[3] 0.001870874 //LENGTH 12.520 LUMPCC 0 DR + +*CONN +*I mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 10.065 72.080 +*P chanx_left_out[3] O *L 0.7423 *C 1.305 74.800 +*N chanx_left_out[3]:2 *C 1.380 74.120 +*N chanx_left_out[3]:3 *C 9.652 74.120 +*N chanx_left_out[3]:4 *C 9.660 74.062 +*N chanx_left_out[3]:5 *C 9.660 72.125 +*N chanx_left_out[3]:6 *C 9.683 72.080 +*N chanx_left_out[3]:7 *C 10.050 72.080 + +*CAP +0 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[3] 5.411648e-05 +2 chanx_left_out[3]:2 0.0007554683 +3 chanx_left_out[3]:3 0.0007013518 +4 chanx_left_out[3]:4 0.0001309002 +5 chanx_left_out[3]:5 0.0001309002 +6 chanx_left_out[3]:6 4.856845e-05 +7 chanx_left_out[3]:7 4.856845e-05 + +*RES +0 mux_left_track_7\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[3]:7 0.152 +1 chanx_left_out[3]:7 chanx_left_out[3]:6 0.0001997283 +2 chanx_left_out[3]:6 chanx_left_out[3]:5 0.0045 +3 chanx_left_out[3]:5 chanx_left_out[3]:4 0.001729911 +4 chanx_left_out[3]:4 chanx_left_out[3]:3 0.00341 +5 chanx_left_out[3]:3 chanx_left_out[3]:2 0.001296025 +6 chanx_left_out[3]:2 chanx_left_out[3] 0.0001065333 + +*END + +*D_NET ropt_net_164 0.0007061978 //LENGTH 5.730 LUMPCC 9.287927e-05 DR + +*CONN +*I mem_left_track_25\/BUFT_RR_112:X O *L 0 *C 5.980 64.600 +*I ropt_mt_inst_789:A I *L 0.001766 *C 3.220 66.640 +*N ropt_net_164:2 *C 3.258 66.640 +*N ropt_net_164:3 *C 4.095 66.640 +*N ropt_net_164:4 *C 4.140 66.595 +*N ropt_net_164:5 *C 4.140 64.645 +*N ropt_net_164:6 *C 4.185 64.600 +*N ropt_net_164:7 *C 5.942 64.600 + +*CAP +0 mem_left_track_25\/BUFT_RR_112:X 1e-06 +1 ropt_mt_inst_789:A 1e-06 +2 ropt_net_164:2 6.532014e-05 +3 ropt_net_164:3 6.532014e-05 +4 ropt_net_164:4 9.703562e-05 +5 ropt_net_164:5 9.703562e-05 +6 ropt_net_164:6 0.0001433035 +7 ropt_net_164:7 0.0001433035 +8 ropt_net_164:4 chanx_left_out[7]:3 4.643963e-05 +9 ropt_net_164:5 chanx_left_out[7]:4 4.643963e-05 + +*RES +0 mem_left_track_25\/BUFT_RR_112:X ropt_net_164:7 0.152 +1 ropt_net_164:2 ropt_mt_inst_789:A 0.152 +2 ropt_net_164:3 ropt_net_164:2 0.0007477679 +3 ropt_net_164:4 ropt_net_164:3 0.0045 +4 ropt_net_164:6 ropt_net_164:5 0.0045 +5 ropt_net_164:5 ropt_net_164:4 0.001741072 +6 ropt_net_164:7 ropt_net_164:6 0.001569197 + +*END + +*D_NET mux_tree_tapbuf_size10_1_sram[1] 0.006569398 //LENGTH 51.792 LUMPCC 0.0004085924 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 64.245 28.220 +*I mux_bottom_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 50.700 18.360 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 45.255 28.220 +*I mux_bottom_track_1\/mux_l2_in_2_:S I *L 0.00357 *C 43.600 34.680 +*I mux_bottom_track_1\/mux_l2_in_3_:S I *L 0.00357 *C 47.740 36.040 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 50.240 23.415 +*N mux_tree_tapbuf_size10_1_sram[1]:6 *C 50.240 23.415 +*N mux_tree_tapbuf_size10_1_sram[1]:7 *C 47.703 36.040 +*N mux_tree_tapbuf_size10_1_sram[1]:8 *C 45.125 36.040 +*N mux_tree_tapbuf_size10_1_sram[1]:9 *C 45.080 35.995 +*N mux_tree_tapbuf_size10_1_sram[1]:10 *C 43.638 34.680 +*N mux_tree_tapbuf_size10_1_sram[1]:11 *C 45.035 34.680 +*N mux_tree_tapbuf_size10_1_sram[1]:12 *C 45.080 34.680 +*N mux_tree_tapbuf_size10_1_sram[1]:13 *C 45.080 28.265 +*N mux_tree_tapbuf_size10_1_sram[1]:14 *C 45.080 28.220 +*N mux_tree_tapbuf_size10_1_sram[1]:15 *C 45.293 28.220 +*N mux_tree_tapbuf_size10_1_sram[1]:16 *C 48.255 28.220 +*N mux_tree_tapbuf_size10_1_sram[1]:17 *C 48.300 28.175 +*N mux_tree_tapbuf_size10_1_sram[1]:18 *C 48.300 23.845 +*N mux_tree_tapbuf_size10_1_sram[1]:19 *C 48.345 23.800 +*N mux_tree_tapbuf_size10_1_sram[1]:20 *C 50.240 23.800 +*N mux_tree_tapbuf_size10_1_sram[1]:21 *C 51.935 23.800 +*N mux_tree_tapbuf_size10_1_sram[1]:22 *C 51.980 23.755 +*N mux_tree_tapbuf_size10_1_sram[1]:23 *C 50.738 18.360 +*N mux_tree_tapbuf_size10_1_sram[1]:24 *C 51.935 18.360 +*N mux_tree_tapbuf_size10_1_sram[1]:25 *C 51.980 18.405 +*N mux_tree_tapbuf_size10_1_sram[1]:26 *C 51.980 22.780 +*N mux_tree_tapbuf_size10_1_sram[1]:27 *C 52.025 22.780 +*N mux_tree_tapbuf_size10_1_sram[1]:28 *C 64.355 22.780 +*N mux_tree_tapbuf_size10_1_sram[1]:29 *C 64.400 22.825 +*N mux_tree_tapbuf_size10_1_sram[1]:30 *C 64.400 28.175 +*N mux_tree_tapbuf_size10_1_sram[1]:31 *C 64.400 28.220 +*N mux_tree_tapbuf_size10_1_sram[1]:32 *C 64.245 28.220 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:S 1e-06 +2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_1\/mux_l2_in_2_:S 1e-06 +4 mux_bottom_track_1\/mux_l2_in_3_:S 1e-06 +5 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +6 mux_tree_tapbuf_size10_1_sram[1]:6 5.569994e-05 +7 mux_tree_tapbuf_size10_1_sram[1]:7 0.0002050222 +8 mux_tree_tapbuf_size10_1_sram[1]:8 0.0002050222 +9 mux_tree_tapbuf_size10_1_sram[1]:9 7.9186e-05 +10 mux_tree_tapbuf_size10_1_sram[1]:10 0.0001281561 +11 mux_tree_tapbuf_size10_1_sram[1]:11 0.0001281561 +12 mux_tree_tapbuf_size10_1_sram[1]:12 0.0004676173 +13 mux_tree_tapbuf_size10_1_sram[1]:13 0.0003557313 +14 mux_tree_tapbuf_size10_1_sram[1]:14 5.137251e-05 +15 mux_tree_tapbuf_size10_1_sram[1]:15 0.0002212582 +16 mux_tree_tapbuf_size10_1_sram[1]:16 0.0002003873 +17 mux_tree_tapbuf_size10_1_sram[1]:17 0.0002475829 +18 mux_tree_tapbuf_size10_1_sram[1]:18 0.0002475829 +19 mux_tree_tapbuf_size10_1_sram[1]:19 0.0001620431 +20 mux_tree_tapbuf_size10_1_sram[1]:20 0.0002926443 +21 mux_tree_tapbuf_size10_1_sram[1]:21 0.0001019328 +22 mux_tree_tapbuf_size10_1_sram[1]:22 6.062293e-05 +23 mux_tree_tapbuf_size10_1_sram[1]:23 0.0001135093 +24 mux_tree_tapbuf_size10_1_sram[1]:24 0.0001135093 +25 mux_tree_tapbuf_size10_1_sram[1]:25 0.0002425313 +26 mux_tree_tapbuf_size10_1_sram[1]:26 0.000332354 +27 mux_tree_tapbuf_size10_1_sram[1]:27 0.0006691391 +28 mux_tree_tapbuf_size10_1_sram[1]:28 0.0006691391 +29 mux_tree_tapbuf_size10_1_sram[1]:29 0.0003506765 +30 mux_tree_tapbuf_size10_1_sram[1]:30 0.0003506765 +31 mux_tree_tapbuf_size10_1_sram[1]:31 5.446718e-05 +32 mux_tree_tapbuf_size10_1_sram[1]:32 4.878511e-05 +33 mux_tree_tapbuf_size10_1_sram[1]:27 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.629291e-05 +34 mux_tree_tapbuf_size10_1_sram[1]:28 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.629291e-05 +35 mux_tree_tapbuf_size10_1_sram[1]:21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.548436e-05 +36 mux_tree_tapbuf_size10_1_sram[1]:20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.548436e-05 +37 mux_tree_tapbuf_size10_1_sram[1]:25 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.056961e-06 +38 mux_tree_tapbuf_size10_1_sram[1]:27 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.677104e-05 +39 mux_tree_tapbuf_size10_1_sram[1]:26 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.056961e-06 +40 mux_tree_tapbuf_size10_1_sram[1]:28 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.677104e-05 +41 mux_tree_tapbuf_size10_1_sram[1]:21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.909171e-07 +42 mux_tree_tapbuf_size10_1_sram[1]:20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.909171e-07 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size10_1_sram[1]:32 0.152 +1 mux_tree_tapbuf_size10_1_sram[1]:6 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size10_1_sram[1]:8 mux_tree_tapbuf_size10_1_sram[1]:7 0.002301339 +3 mux_tree_tapbuf_size10_1_sram[1]:9 mux_tree_tapbuf_size10_1_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size10_1_sram[1]:7 mux_bottom_track_1\/mux_l2_in_3_:S 0.152 +5 mux_tree_tapbuf_size10_1_sram[1]:14 mux_tree_tapbuf_size10_1_sram[1]:13 0.0045 +6 mux_tree_tapbuf_size10_1_sram[1]:13 mux_tree_tapbuf_size10_1_sram[1]:12 0.005727679 +7 mux_tree_tapbuf_size10_1_sram[1]:24 mux_tree_tapbuf_size10_1_sram[1]:23 0.001069196 +8 mux_tree_tapbuf_size10_1_sram[1]:25 mux_tree_tapbuf_size10_1_sram[1]:24 0.0045 +9 mux_tree_tapbuf_size10_1_sram[1]:23 mux_bottom_track_1\/mux_l2_in_1_:S 0.152 +10 mux_tree_tapbuf_size10_1_sram[1]:27 mux_tree_tapbuf_size10_1_sram[1]:26 0.0045 +11 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:25 0.00390625 +12 mux_tree_tapbuf_size10_1_sram[1]:26 mux_tree_tapbuf_size10_1_sram[1]:22 0.0008705358 +13 mux_tree_tapbuf_size10_1_sram[1]:28 mux_tree_tapbuf_size10_1_sram[1]:27 0.01100893 +14 mux_tree_tapbuf_size10_1_sram[1]:29 mux_tree_tapbuf_size10_1_sram[1]:28 0.0045 +15 mux_tree_tapbuf_size10_1_sram[1]:31 mux_tree_tapbuf_size10_1_sram[1]:30 0.0045 +16 mux_tree_tapbuf_size10_1_sram[1]:30 mux_tree_tapbuf_size10_1_sram[1]:29 0.004776786 +17 mux_tree_tapbuf_size10_1_sram[1]:32 mux_tree_tapbuf_size10_1_sram[1]:31 8.423914e-05 +18 mux_tree_tapbuf_size10_1_sram[1]:15 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +19 mux_tree_tapbuf_size10_1_sram[1]:15 mux_tree_tapbuf_size10_1_sram[1]:14 0.0001154891 +20 mux_tree_tapbuf_size10_1_sram[1]:16 mux_tree_tapbuf_size10_1_sram[1]:15 0.002645089 +21 mux_tree_tapbuf_size10_1_sram[1]:17 mux_tree_tapbuf_size10_1_sram[1]:16 0.0045 +22 mux_tree_tapbuf_size10_1_sram[1]:19 mux_tree_tapbuf_size10_1_sram[1]:18 0.0045 +23 mux_tree_tapbuf_size10_1_sram[1]:18 mux_tree_tapbuf_size10_1_sram[1]:17 0.003866072 +24 mux_tree_tapbuf_size10_1_sram[1]:11 mux_tree_tapbuf_size10_1_sram[1]:10 0.001247768 +25 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:11 0.0045 +26 mux_tree_tapbuf_size10_1_sram[1]:12 mux_tree_tapbuf_size10_1_sram[1]:9 0.001174107 +27 mux_tree_tapbuf_size10_1_sram[1]:10 mux_bottom_track_1\/mux_l2_in_2_:S 0.152 +28 mux_tree_tapbuf_size10_1_sram[1]:21 mux_tree_tapbuf_size10_1_sram[1]:20 0.001513393 +29 mux_tree_tapbuf_size10_1_sram[1]:22 mux_tree_tapbuf_size10_1_sram[1]:21 0.0045 +30 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:19 0.001691964 +31 mux_tree_tapbuf_size10_1_sram[1]:20 mux_tree_tapbuf_size10_1_sram[1]:6 0.00034375 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001311572 //LENGTH 10.875 LUMPCC 0.0001301429 DR + +*CONN +*I mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 25.145 55.420 +*I mem_left_track_17\/FTB_23__55:A I *L 0.001746 *C 22.080 53.040 +*I mux_left_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 17.580 53.040 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 17.617 53.040 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 22.043 53.040 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 22.080 53.085 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 22.080 55.375 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 22.125 55.420 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 25.108 55.420 + +*CAP +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_17\/FTB_23__55:A 1e-06 +2 mux_left_track_17\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 0.0002271339 +4 mux_tree_tapbuf_size3_0_sram[1]:4 0.0002271339 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0001478474 +6 mux_tree_tapbuf_size3_0_sram[1]:6 0.0001478474 +7 mux_tree_tapbuf_size3_0_sram[1]:7 0.0002142331 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0002142331 +9 mux_tree_tapbuf_size3_0_sram[1]:3 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.507144e-05 +10 mux_tree_tapbuf_size3_0_sram[1]:4 mux_left_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.507144e-05 + +*RES +0 mem_left_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:8 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:3 mux_left_track_17\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_0_sram[1]:4 mem_left_track_17\/FTB_23__55:A 0.152 +3 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.003950893 +4 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.0045 +5 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size3_0_sram[1]:6 mux_tree_tapbuf_size3_0_sram[1]:5 0.002044643 +7 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.002662946 + +*END + +*D_NET mux_tree_tapbuf_size3_4_sram[0] 0.003080376 //LENGTH 21.010 LUMPCC 0.0007602854 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 52.745 74.800 +*I mux_left_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 50.240 66.640 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 57.675 69.700 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 58.520 66.640 +*N mux_tree_tapbuf_size3_4_sram[0]:4 *C 58.483 66.640 +*N mux_tree_tapbuf_size3_4_sram[0]:5 *C 57.675 69.700 +*N mux_tree_tapbuf_size3_4_sram[0]:6 *C 57.500 69.700 +*N mux_tree_tapbuf_size3_4_sram[0]:7 *C 57.500 69.655 +*N mux_tree_tapbuf_size3_4_sram[0]:8 *C 57.500 66.685 +*N mux_tree_tapbuf_size3_4_sram[0]:9 *C 57.500 66.640 +*N mux_tree_tapbuf_size3_4_sram[0]:10 *C 50.278 66.640 +*N mux_tree_tapbuf_size3_4_sram[0]:11 *C 52.440 66.640 +*N mux_tree_tapbuf_size3_4_sram[0]:12 *C 52.440 66.685 +*N mux_tree_tapbuf_size3_4_sram[0]:13 *C 52.440 74.755 +*N mux_tree_tapbuf_size3_4_sram[0]:14 *C 52.440 74.800 +*N mux_tree_tapbuf_size3_4_sram[0]:15 *C 52.745 74.800 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_25\/mux_l1_in_1_:S 1e-06 +2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_4_sram[0]:4 4.430446e-05 +5 mux_tree_tapbuf_size3_4_sram[0]:5 6.522008e-05 +6 mux_tree_tapbuf_size3_4_sram[0]:6 6.873252e-05 +7 mux_tree_tapbuf_size3_4_sram[0]:7 0.0002519675 +8 mux_tree_tapbuf_size3_4_sram[0]:8 0.0002519675 +9 mux_tree_tapbuf_size3_4_sram[0]:9 0.0002078893 +10 mux_tree_tapbuf_size3_4_sram[0]:10 9.861231e-05 +11 mux_tree_tapbuf_size3_4_sram[0]:11 0.0002584674 +12 mux_tree_tapbuf_size3_4_sram[0]:12 0.0004724402 +13 mux_tree_tapbuf_size3_4_sram[0]:13 0.0004724402 +14 mux_tree_tapbuf_size3_4_sram[0]:14 6.304827e-05 +15 mux_tree_tapbuf_size3_4_sram[0]:15 6.100113e-05 +16 mux_tree_tapbuf_size3_4_sram[0]:11 optlc_net_138:8 4.000202e-05 +17 mux_tree_tapbuf_size3_4_sram[0]:11 optlc_net_138:7 0.000172298 +18 mux_tree_tapbuf_size3_4_sram[0]:4 optlc_net_138:8 4.01661e-05 +19 mux_tree_tapbuf_size3_4_sram[0]:9 optlc_net_138:8 0.000172298 +20 mux_tree_tapbuf_size3_4_sram[0]:9 optlc_net_138:7 4.01661e-05 +21 mux_tree_tapbuf_size3_4_sram[0]:10 optlc_net_138:7 4.000202e-05 +22 mux_tree_tapbuf_size3_4_sram[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.61984e-05 +23 mux_tree_tapbuf_size3_4_sram[0]:11 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.587404e-05 +24 mux_tree_tapbuf_size3_4_sram[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.604104e-06 +25 mux_tree_tapbuf_size3_4_sram[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.587404e-05 +26 mux_tree_tapbuf_size3_4_sram[0]:9 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.604104e-06 +27 mux_tree_tapbuf_size3_4_sram[0]:10 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.61984e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_4_sram[0]:15 0.152 +1 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:10 0.001930804 +2 mux_tree_tapbuf_size3_4_sram[0]:11 mux_tree_tapbuf_size3_4_sram[0]:9 0.004517857 +3 mux_tree_tapbuf_size3_4_sram[0]:12 mux_tree_tapbuf_size3_4_sram[0]:11 0.0045 +4 mux_tree_tapbuf_size3_4_sram[0]:14 mux_tree_tapbuf_size3_4_sram[0]:13 0.0045 +5 mux_tree_tapbuf_size3_4_sram[0]:13 mux_tree_tapbuf_size3_4_sram[0]:12 0.007205358 +6 mux_tree_tapbuf_size3_4_sram[0]:15 mux_tree_tapbuf_size3_4_sram[0]:14 0.0001657609 +7 mux_tree_tapbuf_size3_4_sram[0]:4 mux_left_track_25\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size3_4_sram[0]:9 mux_tree_tapbuf_size3_4_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size3_4_sram[0]:9 mux_tree_tapbuf_size3_4_sram[0]:4 0.0008772322 +10 mux_tree_tapbuf_size3_4_sram[0]:8 mux_tree_tapbuf_size3_4_sram[0]:7 0.002651786 +11 mux_tree_tapbuf_size3_4_sram[0]:6 mux_tree_tapbuf_size3_4_sram[0]:5 9.51087e-05 +12 mux_tree_tapbuf_size3_4_sram[0]:7 mux_tree_tapbuf_size3_4_sram[0]:6 0.0045 +13 mux_tree_tapbuf_size3_4_sram[0]:5 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size3_4_sram[0]:10 mux_left_track_25\/mux_l1_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[0] 0.004351608 //LENGTH 30.205 LUMPCC 0.001053962 DR + +*CONN +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.605 47.600 +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 51.695 49.980 +*I mux_left_track_13\/mux_l1_in_0_:S I *L 0.00357 *C 54.380 45.175 +*N mux_tree_tapbuf_size4_2_sram[0]:3 *C 54.380 45.175 +*N mux_tree_tapbuf_size4_2_sram[0]:4 *C 54.293 44.880 +*N mux_tree_tapbuf_size4_2_sram[0]:5 *C 51.695 49.980 +*N mux_tree_tapbuf_size4_2_sram[0]:6 *C 51.520 49.980 +*N mux_tree_tapbuf_size4_2_sram[0]:7 *C 51.520 49.935 +*N mux_tree_tapbuf_size4_2_sram[0]:8 *C 51.520 44.925 +*N mux_tree_tapbuf_size4_2_sram[0]:9 *C 51.565 44.880 +*N mux_tree_tapbuf_size4_2_sram[0]:10 *C 54.338 44.910 +*N mux_tree_tapbuf_size4_2_sram[0]:11 *C 54.280 44.925 +*N mux_tree_tapbuf_size4_2_sram[0]:12 *C 54.280 47.543 +*N mux_tree_tapbuf_size4_2_sram[0]:13 *C 54.288 47.600 +*N mux_tree_tapbuf_size4_2_sram[0]:14 *C 70.833 47.600 +*N mux_tree_tapbuf_size4_2_sram[0]:15 *C 70.840 47.600 +*N mux_tree_tapbuf_size4_2_sram[0]:16 *C 70.885 47.600 +*N mux_tree_tapbuf_size4_2_sram[0]:17 *C 71.568 47.600 + +*CAP +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_13\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_2_sram[0]:3 5.780359e-05 +4 mux_tree_tapbuf_size4_2_sram[0]:4 2.280516e-05 +5 mux_tree_tapbuf_size4_2_sram[0]:5 4.918867e-05 +6 mux_tree_tapbuf_size4_2_sram[0]:6 5.107918e-05 +7 mux_tree_tapbuf_size4_2_sram[0]:7 0.0002407035 +8 mux_tree_tapbuf_size4_2_sram[0]:8 0.0002407035 +9 mux_tree_tapbuf_size4_2_sram[0]:9 0.0001295882 +10 mux_tree_tapbuf_size4_2_sram[0]:10 0.0001760682 +11 mux_tree_tapbuf_size4_2_sram[0]:11 0.0001364912 +12 mux_tree_tapbuf_size4_2_sram[0]:12 0.0001364912 +13 mux_tree_tapbuf_size4_2_sram[0]:13 0.0009097999 +14 mux_tree_tapbuf_size4_2_sram[0]:14 0.0009097999 +15 mux_tree_tapbuf_size4_2_sram[0]:15 3.985343e-05 +16 mux_tree_tapbuf_size4_2_sram[0]:16 9.713571e-05 +17 mux_tree_tapbuf_size4_2_sram[0]:17 9.713571e-05 +18 mux_tree_tapbuf_size4_2_sram[0]:8 chany_top_in[10]:17 2.871035e-08 +19 mux_tree_tapbuf_size4_2_sram[0]:7 chany_top_in[10]:20 2.871035e-08 +20 mux_tree_tapbuf_size4_2_sram[0]:3 chany_top_in[10]:19 1.496792e-06 +21 mux_tree_tapbuf_size4_2_sram[0]:14 chany_top_in[10]:23 0.0002043199 +22 mux_tree_tapbuf_size4_2_sram[0]:12 chany_top_in[10]:20 7.806169e-06 +23 mux_tree_tapbuf_size4_2_sram[0]:12 chany_top_in[10]:21 7.758095e-06 +24 mux_tree_tapbuf_size4_2_sram[0]:13 chany_top_in[10]:22 0.0002043199 +25 mux_tree_tapbuf_size4_2_sram[0]:10 chany_top_in[10]:18 1.496792e-06 +26 mux_tree_tapbuf_size4_2_sram[0]:11 chany_top_in[10]:17 7.806169e-06 +27 mux_tree_tapbuf_size4_2_sram[0]:11 chany_top_in[10]:20 7.758095e-06 +28 mux_tree_tapbuf_size4_2_sram[0]:8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.209358e-05 +29 mux_tree_tapbuf_size4_2_sram[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 3.209358e-05 +30 mux_tree_tapbuf_size4_2_sram[0]:14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.0001558575 +31 mux_tree_tapbuf_size4_2_sram[0]:12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 1.831625e-05 +32 mux_tree_tapbuf_size4_2_sram[0]:13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0001558575 +33 mux_tree_tapbuf_size4_2_sram[0]:11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 1.831625e-05 +34 mux_tree_tapbuf_size4_2_sram[0]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.590215e-05 +35 mux_tree_tapbuf_size4_2_sram[0]:8 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.340168e-05 +36 mux_tree_tapbuf_size4_2_sram[0]:7 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.340168e-05 +37 mux_tree_tapbuf_size4_2_sram[0]:10 mux_left_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.590215e-05 + +*RES +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size4_2_sram[0]:17 0.152 +1 mux_tree_tapbuf_size4_2_sram[0]:9 mux_tree_tapbuf_size4_2_sram[0]:8 0.0045 +2 mux_tree_tapbuf_size4_2_sram[0]:8 mux_tree_tapbuf_size4_2_sram[0]:7 0.004473215 +3 mux_tree_tapbuf_size4_2_sram[0]:6 mux_tree_tapbuf_size4_2_sram[0]:5 9.51087e-05 +4 mux_tree_tapbuf_size4_2_sram[0]:7 mux_tree_tapbuf_size4_2_sram[0]:6 0.0045 +5 mux_tree_tapbuf_size4_2_sram[0]:5 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size4_2_sram[0]:3 mux_left_track_13\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size4_2_sram[0]:17 mux_tree_tapbuf_size4_2_sram[0]:16 0.000609375 +8 mux_tree_tapbuf_size4_2_sram[0]:16 mux_tree_tapbuf_size4_2_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size4_2_sram[0]:15 mux_tree_tapbuf_size4_2_sram[0]:14 0.00341 +10 mux_tree_tapbuf_size4_2_sram[0]:14 mux_tree_tapbuf_size4_2_sram[0]:13 0.00259205 +11 mux_tree_tapbuf_size4_2_sram[0]:12 mux_tree_tapbuf_size4_2_sram[0]:11 0.002337054 +12 mux_tree_tapbuf_size4_2_sram[0]:13 mux_tree_tapbuf_size4_2_sram[0]:12 0.00341 +13 mux_tree_tapbuf_size4_2_sram[0]:10 mux_tree_tapbuf_size4_2_sram[0]:9 0.002475447 +14 mux_tree_tapbuf_size4_2_sram[0]:10 mux_tree_tapbuf_size4_2_sram[0]:4 4.017858e-05 +15 mux_tree_tapbuf_size4_2_sram[0]:10 mux_tree_tapbuf_size4_2_sram[0]:3 0.0001540698 +16 mux_tree_tapbuf_size4_2_sram[0]:11 mux_tree_tapbuf_size4_2_sram[0]:10 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.002481946 //LENGTH 19.190 LUMPCC 0.0003134928 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 68.385 25.840 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 73.480 18.360 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 72.855 22.780 +*I mux_bottom_track_25\/mux_l2_in_1_:S I *L 0.00357 *C 72.120 20.400 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 72.083 20.400 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 69.965 20.400 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 69.920 20.445 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 72.730 22.780 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 73.443 18.360 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 72.725 18.360 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 72.680 18.405 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 72.680 22.735 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 72.635 22.780 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 69.965 22.780 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 69.920 22.780 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 69.920 25.795 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 69.875 25.840 +*N mux_tree_tapbuf_size6_1_sram[1]:17 *C 68.422 25.840 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_25\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 0.0001860901 +5 mux_tree_tapbuf_size6_1_sram[1]:5 0.0001860901 +6 mux_tree_tapbuf_size6_1_sram[1]:6 0.0001045779 +7 mux_tree_tapbuf_size6_1_sram[1]:7 2.286605e-05 +8 mux_tree_tapbuf_size6_1_sram[1]:8 7.262161e-05 +9 mux_tree_tapbuf_size6_1_sram[1]:9 7.262161e-05 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.0002976716 +11 mux_tree_tapbuf_size6_1_sram[1]:11 0.0002976716 +12 mux_tree_tapbuf_size6_1_sram[1]:12 0.0001976474 +13 mux_tree_tapbuf_size6_1_sram[1]:13 0.0001747813 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0002398067 +15 mux_tree_tapbuf_size6_1_sram[1]:15 0.0001086077 +16 mux_tree_tapbuf_size6_1_sram[1]:16 0.0001016996 +17 mux_tree_tapbuf_size6_1_sram[1]:17 0.0001016996 +18 mux_tree_tapbuf_size6_1_sram[1]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.218678e-06 +19 mux_tree_tapbuf_size6_1_sram[1]:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.218678e-06 +20 mux_tree_tapbuf_size6_1_sram[1]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.146037e-05 +21 mux_tree_tapbuf_size6_1_sram[1]:14 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.406738e-05 +22 mux_tree_tapbuf_size6_1_sram[1]:15 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.146037e-05 +23 mux_tree_tapbuf_size6_1_sram[1]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.406738e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:17 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:8 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.0006406251 +3 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:9 0.0045 +4 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:7 8.482143e-05 +6 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.003866071 +7 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.002383929 +8 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.0045 +9 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:6 0.002084821 +10 mux_tree_tapbuf_size6_1_sram[1]:7 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +11 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.0045 +12 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.002691964 +13 mux_tree_tapbuf_size6_1_sram[1]:17 mux_tree_tapbuf_size6_1_sram[1]:16 0.001296875 +14 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.001890625 +15 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +16 mux_tree_tapbuf_size6_1_sram[1]:4 mux_bottom_track_25\/mux_l2_in_1_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_1_sram[0] 0.01269373 //LENGTH 94.810 LUMPCC 0.00278839 DR + +*CONN +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 68.845 88.400 +*I mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 39.735 86.020 +*I mux_top_track_24\/mux_l1_in_2_:S I *L 0.00357 *C 23.820 72.760 +*I mux_top_track_24\/mux_l1_in_3_:S I *L 0.00357 *C 32.100 74.120 +*I mux_top_track_24\/mux_l1_in_0_:S I *L 0.00357 *C 39.660 106.760 +*I mux_top_track_24\/mux_l1_in_1_:S I *L 0.00357 *C 76.460 88.400 +*N mux_tree_tapbuf_size7_1_sram[0]:6 *C 76.422 88.400 +*N mux_tree_tapbuf_size7_1_sram[0]:7 *C 39.560 106.760 +*N mux_tree_tapbuf_size7_1_sram[0]:8 *C 39.560 106.715 +*N mux_tree_tapbuf_size7_1_sram[0]:9 *C 39.100 85.925 +*N mux_tree_tapbuf_size7_1_sram[0]:10 *C 32.062 74.120 +*N mux_tree_tapbuf_size7_1_sram[0]:11 *C 29.945 74.120 +*N mux_tree_tapbuf_size7_1_sram[0]:12 *C 29.900 74.165 +*N mux_tree_tapbuf_size7_1_sram[0]:13 *C 23.820 72.760 +*N mux_tree_tapbuf_size7_1_sram[0]:14 *C 23.920 72.805 +*N mux_tree_tapbuf_size7_1_sram[0]:15 *C 23.920 75.095 +*N mux_tree_tapbuf_size7_1_sram[0]:16 *C 23.965 75.140 +*N mux_tree_tapbuf_size7_1_sram[0]:17 *C 29.855 75.140 +*N mux_tree_tapbuf_size7_1_sram[0]:18 *C 29.900 75.140 +*N mux_tree_tapbuf_size7_1_sram[0]:19 *C 29.900 77.815 +*N mux_tree_tapbuf_size7_1_sram[0]:20 *C 29.945 77.860 +*N mux_tree_tapbuf_size7_1_sram[0]:21 *C 38.595 77.860 +*N mux_tree_tapbuf_size7_1_sram[0]:22 *C 38.670 77.890 +*N mux_tree_tapbuf_size7_1_sram[0]:23 *C 38.685 78.200 +*N mux_tree_tapbuf_size7_1_sram[0]:24 *C 39.100 78.200 +*N mux_tree_tapbuf_size7_1_sram[0]:25 *C 39.698 86.020 +*N mux_tree_tapbuf_size7_1_sram[0]:26 *C 39.145 86.020 +*N mux_tree_tapbuf_size7_1_sram[0]:27 *C 39.130 86.050 +*N mux_tree_tapbuf_size7_1_sram[0]:28 *C 39.145 86.360 +*N mux_tree_tapbuf_size7_1_sram[0]:29 *C 39.560 86.360 +*N mux_tree_tapbuf_size7_1_sram[0]:30 *C 39.560 89.080 +*N mux_tree_tapbuf_size7_1_sram[0]:31 *C 39.568 89.080 +*N mux_tree_tapbuf_size7_1_sram[0]:32 *C 68.838 89.080 +*N mux_tree_tapbuf_size7_1_sram[0]:33 *C 68.845 89.023 +*N mux_tree_tapbuf_size7_1_sram[0]:34 *C 68.845 88.445 +*N mux_tree_tapbuf_size7_1_sram[0]:35 *C 68.883 88.400 + +*CAP +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_top_track_24\/mux_l1_in_2_:S 1e-06 +3 mux_top_track_24\/mux_l1_in_3_:S 1e-06 +4 mux_top_track_24\/mux_l1_in_0_:S 1e-06 +5 mux_top_track_24\/mux_l1_in_1_:S 1e-06 +6 mux_tree_tapbuf_size7_1_sram[0]:6 0.000391941 +7 mux_tree_tapbuf_size7_1_sram[0]:7 3.827409e-05 +8 mux_tree_tapbuf_size7_1_sram[0]:8 0.0007277268 +9 mux_tree_tapbuf_size7_1_sram[0]:9 9.35447e-06 +10 mux_tree_tapbuf_size7_1_sram[0]:10 0.0001659638 +11 mux_tree_tapbuf_size7_1_sram[0]:11 0.0001659638 +12 mux_tree_tapbuf_size7_1_sram[0]:12 6.416957e-05 +13 mux_tree_tapbuf_size7_1_sram[0]:13 2.612046e-05 +14 mux_tree_tapbuf_size7_1_sram[0]:14 0.000138929 +15 mux_tree_tapbuf_size7_1_sram[0]:15 0.000138929 +16 mux_tree_tapbuf_size7_1_sram[0]:16 0.0002985718 +17 mux_tree_tapbuf_size7_1_sram[0]:17 0.0002985718 +18 mux_tree_tapbuf_size7_1_sram[0]:18 0.0002526707 +19 mux_tree_tapbuf_size7_1_sram[0]:19 0.0001565334 +20 mux_tree_tapbuf_size7_1_sram[0]:20 0.0006321393 +21 mux_tree_tapbuf_size7_1_sram[0]:21 0.0006321393 +22 mux_tree_tapbuf_size7_1_sram[0]:22 3.51097e-05 +23 mux_tree_tapbuf_size7_1_sram[0]:23 6.677466e-05 +24 mux_tree_tapbuf_size7_1_sram[0]:24 0.0004756184 +25 mux_tree_tapbuf_size7_1_sram[0]:25 6.339639e-05 +26 mux_tree_tapbuf_size7_1_sram[0]:26 6.339639e-05 +27 mux_tree_tapbuf_size7_1_sram[0]:27 0.0004755914 +28 mux_tree_tapbuf_size7_1_sram[0]:28 4.057116e-05 +29 mux_tree_tapbuf_size7_1_sram[0]:29 0.0001715003 +30 mux_tree_tapbuf_size7_1_sram[0]:30 0.0009176329 +31 mux_tree_tapbuf_size7_1_sram[0]:31 0.001479704 +32 mux_tree_tapbuf_size7_1_sram[0]:32 0.001479704 +33 mux_tree_tapbuf_size7_1_sram[0]:33 5.019981e-05 +34 mux_tree_tapbuf_size7_1_sram[0]:34 5.019981e-05 +35 mux_tree_tapbuf_size7_1_sram[0]:35 0.000391941 +36 mux_tree_tapbuf_size7_1_sram[0]:35 chany_bottom_in[2]:28 6.055879e-06 +37 mux_tree_tapbuf_size7_1_sram[0]:32 chany_bottom_in[2]:24 9.923951e-05 +38 mux_tree_tapbuf_size7_1_sram[0]:32 chany_bottom_in[2]:25 1.014905e-05 +39 mux_tree_tapbuf_size7_1_sram[0]:32 chany_bottom_in[2]:29 0.0002305485 +40 mux_tree_tapbuf_size7_1_sram[0]:31 chany_bottom_in[2]:8 9.923951e-05 +41 mux_tree_tapbuf_size7_1_sram[0]:31 chany_bottom_in[2]:24 1.014905e-05 +42 mux_tree_tapbuf_size7_1_sram[0]:31 chany_bottom_in[2]:28 0.0002305485 +43 mux_tree_tapbuf_size7_1_sram[0]:6 chany_bottom_in[2]:29 6.055879e-06 +44 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size3_2_sram[1]:4 0.0001609375 +45 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size3_2_sram[1]:5 1.073388e-07 +46 mux_tree_tapbuf_size7_1_sram[0]:16 mux_tree_tapbuf_size3_2_sram[1]:3 0.0001609375 +47 mux_tree_tapbuf_size7_1_sram[0]:11 mux_tree_tapbuf_size3_2_sram[1]:3 1.983723e-05 +48 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size3_2_sram[1]:6 1.073388e-07 +49 mux_tree_tapbuf_size7_1_sram[0]:10 mux_tree_tapbuf_size3_2_sram[1]:4 1.983723e-05 +50 mux_tree_tapbuf_size7_1_sram[0]:30 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.683122e-05 +51 mux_tree_tapbuf_size7_1_sram[0]:30 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.212319e-06 +52 mux_tree_tapbuf_size7_1_sram[0]:30 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.000339264 +53 mux_tree_tapbuf_size7_1_sram[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.000339264 +54 mux_tree_tapbuf_size7_1_sram[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.683122e-05 +55 mux_tree_tapbuf_size7_1_sram[0]:29 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.212319e-06 +56 mux_tree_tapbuf_size7_1_sram[0]:35 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.120646e-05 +57 mux_tree_tapbuf_size7_1_sram[0]:35 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.261232e-06 +58 mux_tree_tapbuf_size7_1_sram[0]:32 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004513477 +59 mux_tree_tapbuf_size7_1_sram[0]:31 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004513477 +60 mux_tree_tapbuf_size7_1_sram[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.120646e-05 +61 mux_tree_tapbuf_size7_1_sram[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.261232e-06 +62 mux_tree_tapbuf_size7_1_sram[0]:28 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.119677e-05 +63 mux_tree_tapbuf_size7_1_sram[0]:29 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.119677e-05 + +*RES +0 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size7_1_sram[0]:35 0.152 +1 mux_tree_tapbuf_size7_1_sram[0]:26 mux_tree_tapbuf_size7_1_sram[0]:25 0.0004933036 +2 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:26 0.0045 +3 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:24 0.007008929 +4 mux_tree_tapbuf_size7_1_sram[0]:27 mux_tree_tapbuf_size7_1_sram[0]:9 0.0001116071 +5 mux_tree_tapbuf_size7_1_sram[0]:25 mem_top_track_24\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size7_1_sram[0]:35 mux_tree_tapbuf_size7_1_sram[0]:34 0.0045 +7 mux_tree_tapbuf_size7_1_sram[0]:35 mux_tree_tapbuf_size7_1_sram[0]:6 0.006732143 +8 mux_tree_tapbuf_size7_1_sram[0]:34 mux_tree_tapbuf_size7_1_sram[0]:33 0.000515625 +9 mux_tree_tapbuf_size7_1_sram[0]:33 mux_tree_tapbuf_size7_1_sram[0]:32 0.00341 +10 mux_tree_tapbuf_size7_1_sram[0]:32 mux_tree_tapbuf_size7_1_sram[0]:31 0.004585633 +11 mux_tree_tapbuf_size7_1_sram[0]:30 mux_tree_tapbuf_size7_1_sram[0]:29 0.002428572 +12 mux_tree_tapbuf_size7_1_sram[0]:30 mux_tree_tapbuf_size7_1_sram[0]:8 0.01574554 +13 mux_tree_tapbuf_size7_1_sram[0]:31 mux_tree_tapbuf_size7_1_sram[0]:30 0.00341 +14 mux_tree_tapbuf_size7_1_sram[0]:17 mux_tree_tapbuf_size7_1_sram[0]:16 0.005258929 +15 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size7_1_sram[0]:17 0.0045 +16 mux_tree_tapbuf_size7_1_sram[0]:18 mux_tree_tapbuf_size7_1_sram[0]:12 0.0008705358 +17 mux_tree_tapbuf_size7_1_sram[0]:16 mux_tree_tapbuf_size7_1_sram[0]:15 0.0045 +18 mux_tree_tapbuf_size7_1_sram[0]:15 mux_tree_tapbuf_size7_1_sram[0]:14 0.002044643 +19 mux_tree_tapbuf_size7_1_sram[0]:13 mux_top_track_24\/mux_l1_in_2_:S 0.152 +20 mux_tree_tapbuf_size7_1_sram[0]:14 mux_tree_tapbuf_size7_1_sram[0]:13 0.0045 +21 mux_tree_tapbuf_size7_1_sram[0]:6 mux_top_track_24\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size7_1_sram[0]:11 mux_tree_tapbuf_size7_1_sram[0]:10 0.001890625 +23 mux_tree_tapbuf_size7_1_sram[0]:12 mux_tree_tapbuf_size7_1_sram[0]:11 0.0045 +24 mux_tree_tapbuf_size7_1_sram[0]:10 mux_top_track_24\/mux_l1_in_3_:S 0.152 +25 mux_tree_tapbuf_size7_1_sram[0]:21 mux_tree_tapbuf_size7_1_sram[0]:20 0.007723215 +26 mux_tree_tapbuf_size7_1_sram[0]:22 mux_tree_tapbuf_size7_1_sram[0]:21 0.0045 +27 mux_tree_tapbuf_size7_1_sram[0]:20 mux_tree_tapbuf_size7_1_sram[0]:19 0.0045 +28 mux_tree_tapbuf_size7_1_sram[0]:19 mux_tree_tapbuf_size7_1_sram[0]:18 0.002388393 +29 mux_tree_tapbuf_size7_1_sram[0]:7 mux_top_track_24\/mux_l1_in_0_:S 0.152 +30 mux_tree_tapbuf_size7_1_sram[0]:8 mux_tree_tapbuf_size7_1_sram[0]:7 0.0045 +31 mux_tree_tapbuf_size7_1_sram[0]:23 mux_tree_tapbuf_size7_1_sram[0]:22 0.00019375 +32 mux_tree_tapbuf_size7_1_sram[0]:24 mux_tree_tapbuf_size7_1_sram[0]:23 0.0003705357 +33 mux_tree_tapbuf_size7_1_sram[0]:28 mux_tree_tapbuf_size7_1_sram[0]:27 0.00019375 +34 mux_tree_tapbuf_size7_1_sram[0]:29 mux_tree_tapbuf_size7_1_sram[0]:28 0.0003705357 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_1_ccff_tail[0] 0.0009557135 //LENGTH 6.340 LUMPCC 0.0002932824 DR + +*CONN +*I mem_top_track_24\/FTB_9__41:X O *L 0 *C 49.915 93.500 +*I mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 50.315 88.060 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 *C 50.315 88.060 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 *C 50.140 88.060 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 *C 50.140 88.105 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 *C 50.140 93.455 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 *C 50.140 93.500 +*N mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 *C 49.915 93.500 + +*CAP +0 mem_top_track_24\/FTB_9__41:X 1e-06 +1 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 4.736505e-05 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 5.160746e-05 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.0002248665 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0002248665 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 5.692209e-05 +7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 5.480351e-05 +8 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_0_sram[0]:26 0.0001466412 +9 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_0_sram[0]:25 0.0001466412 + +*RES +0 mem_top_track_24\/FTB_9__41:X mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 0.0001222826 +2 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 0.004776786 +4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_1_ccff_tail[0]:2 mem_top_track_32\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_5_ccff_tail[0] 0.0005343811 //LENGTH 3.300 LUMPCC 0.0001772359 DR + +*CONN +*I mem_left_track_5\/FTB_13__45:X O *L 0 *C 19.555 64.600 +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 20.415 66.300 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 *C 20.415 66.300 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 *C 20.240 66.300 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 *C 20.240 66.255 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 *C 20.240 64.645 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 *C 20.195 64.600 +*N mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 *C 19.593 64.600 + +*CAP +0 mem_left_track_5\/FTB_13__45:X 1e-06 +1 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 5.173861e-05 +3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 5.790881e-05 +4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 7.782554e-05 +5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 7.782554e-05 +6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 4.492338e-05 +7 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 4.492338e-05 +8 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 chanx_left_in[9]:8 5.217312e-05 +9 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 chanx_left_in[9]:5 5.217312e-05 +10 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:7 3.644481e-05 +11 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_2_X[0]:6 3.644481e-05 + +*RES +0 mem_left_track_5\/FTB_13__45:X mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_5_ccff_tail[0]:6 0.0005379464 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[1] 0.004345594 //LENGTH 37.028 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 81.265 107.440 +*I mux_top_track_8\/mux_l2_in_0_:S I *L 0.00357 *C 82.700 105.400 +*I mux_top_track_8\/mux_l2_in_1_:S I *L 0.00357 *C 81.780 94.520 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 76.535 91.460 +*I mux_top_track_8\/mux_l2_in_2_:S I *L 0.00357 *C 73.040 85.000 +*I mux_top_track_8\/mux_l2_in_3_:S I *L 0.00357 *C 77.180 83.640 +*N mux_tree_tapbuf_size8_1_sram[1]:6 *C 77.142 83.640 +*N mux_tree_tapbuf_size8_1_sram[1]:7 *C 76.405 83.640 +*N mux_tree_tapbuf_size8_1_sram[1]:8 *C 76.360 83.685 +*N mux_tree_tapbuf_size8_1_sram[1]:9 *C 73.078 85.000 +*N mux_tree_tapbuf_size8_1_sram[1]:10 *C 76.315 85.000 +*N mux_tree_tapbuf_size8_1_sram[1]:11 *C 76.360 85.000 +*N mux_tree_tapbuf_size8_1_sram[1]:12 *C 76.360 91.415 +*N mux_tree_tapbuf_size8_1_sram[1]:13 *C 76.360 91.460 +*N mux_tree_tapbuf_size8_1_sram[1]:14 *C 76.573 91.460 +*N mux_tree_tapbuf_size8_1_sram[1]:15 *C 81.375 91.460 +*N mux_tree_tapbuf_size8_1_sram[1]:16 *C 81.420 91.505 +*N mux_tree_tapbuf_size8_1_sram[1]:17 *C 81.765 94.520 +*N mux_tree_tapbuf_size8_1_sram[1]:18 *C 81.443 94.520 +*N mux_tree_tapbuf_size8_1_sram[1]:19 *C 81.420 94.520 +*N mux_tree_tapbuf_size8_1_sram[1]:20 *C 82.663 105.400 +*N mux_tree_tapbuf_size8_1_sram[1]:21 *C 81.465 105.400 +*N mux_tree_tapbuf_size8_1_sram[1]:22 *C 81.420 105.400 +*N mux_tree_tapbuf_size8_1_sram[1]:23 *C 81.420 107.395 +*N mux_tree_tapbuf_size8_1_sram[1]:24 *C 81.420 107.440 +*N mux_tree_tapbuf_size8_1_sram[1]:25 *C 81.265 107.440 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:S 1e-06 +2 mux_top_track_8\/mux_l2_in_1_:S 1e-06 +3 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_top_track_8\/mux_l2_in_2_:S 1e-06 +5 mux_top_track_8\/mux_l2_in_3_:S 1e-06 +6 mux_tree_tapbuf_size8_1_sram[1]:6 7.178736e-05 +7 mux_tree_tapbuf_size8_1_sram[1]:7 7.178736e-05 +8 mux_tree_tapbuf_size8_1_sram[1]:8 7.510022e-05 +9 mux_tree_tapbuf_size8_1_sram[1]:9 0.0002387365 +10 mux_tree_tapbuf_size8_1_sram[1]:10 0.0002387365 +11 mux_tree_tapbuf_size8_1_sram[1]:11 0.0004499805 +12 mux_tree_tapbuf_size8_1_sram[1]:12 0.0003464138 +13 mux_tree_tapbuf_size8_1_sram[1]:13 5.140812e-05 +14 mux_tree_tapbuf_size8_1_sram[1]:14 0.0003124884 +15 mux_tree_tapbuf_size8_1_sram[1]:15 0.0002931619 +16 mux_tree_tapbuf_size8_1_sram[1]:16 0.000190049 +17 mux_tree_tapbuf_size8_1_sram[1]:17 5.220535e-05 +18 mux_tree_tapbuf_size8_1_sram[1]:18 5.220535e-05 +19 mux_tree_tapbuf_size8_1_sram[1]:19 0.0007657976 +20 mux_tree_tapbuf_size8_1_sram[1]:20 0.0001114033 +21 mux_tree_tapbuf_size8_1_sram[1]:21 0.0001114033 +22 mux_tree_tapbuf_size8_1_sram[1]:22 0.000694212 +23 mux_tree_tapbuf_size8_1_sram[1]:23 0.0001172944 +24 mux_tree_tapbuf_size8_1_sram[1]:24 4.877525e-05 +25 mux_tree_tapbuf_size8_1_sram[1]:25 4.664739e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size8_1_sram[1]:25 0.152 +1 mux_tree_tapbuf_size8_1_sram[1]:17 mux_top_track_8\/mux_l2_in_1_:S 0.152 +2 mux_tree_tapbuf_size8_1_sram[1]:18 mux_tree_tapbuf_size8_1_sram[1]:17 0.0001752718 +3 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:18 0.0045 +4 mux_tree_tapbuf_size8_1_sram[1]:19 mux_tree_tapbuf_size8_1_sram[1]:16 0.002691964 +5 mux_tree_tapbuf_size8_1_sram[1]:13 mux_tree_tapbuf_size8_1_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size8_1_sram[1]:12 mux_tree_tapbuf_size8_1_sram[1]:11 0.005727679 +7 mux_tree_tapbuf_size8_1_sram[1]:10 mux_tree_tapbuf_size8_1_sram[1]:9 0.002890625 +8 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:10 0.0045 +9 mux_tree_tapbuf_size8_1_sram[1]:11 mux_tree_tapbuf_size8_1_sram[1]:8 0.001174107 +10 mux_tree_tapbuf_size8_1_sram[1]:9 mux_top_track_8\/mux_l2_in_2_:S 0.152 +11 mux_tree_tapbuf_size8_1_sram[1]:15 mux_tree_tapbuf_size8_1_sram[1]:14 0.004287947 +12 mux_tree_tapbuf_size8_1_sram[1]:16 mux_tree_tapbuf_size8_1_sram[1]:15 0.0045 +13 mux_tree_tapbuf_size8_1_sram[1]:7 mux_tree_tapbuf_size8_1_sram[1]:6 0.0006584821 +14 mux_tree_tapbuf_size8_1_sram[1]:8 mux_tree_tapbuf_size8_1_sram[1]:7 0.0045 +15 mux_tree_tapbuf_size8_1_sram[1]:6 mux_top_track_8\/mux_l2_in_3_:S 0.152 +16 mux_tree_tapbuf_size8_1_sram[1]:21 mux_tree_tapbuf_size8_1_sram[1]:20 0.001069196 +17 mux_tree_tapbuf_size8_1_sram[1]:22 mux_tree_tapbuf_size8_1_sram[1]:21 0.0045 +18 mux_tree_tapbuf_size8_1_sram[1]:22 mux_tree_tapbuf_size8_1_sram[1]:19 0.009714287 +19 mux_tree_tapbuf_size8_1_sram[1]:20 mux_top_track_8\/mux_l2_in_0_:S 0.152 +20 mux_tree_tapbuf_size8_1_sram[1]:14 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +21 mux_tree_tapbuf_size8_1_sram[1]:14 mux_tree_tapbuf_size8_1_sram[1]:13 0.0001154891 +22 mux_tree_tapbuf_size8_1_sram[1]:24 mux_tree_tapbuf_size8_1_sram[1]:23 0.0045 +23 mux_tree_tapbuf_size8_1_sram[1]:23 mux_tree_tapbuf_size8_1_sram[1]:22 0.00178125 +24 mux_tree_tapbuf_size8_1_sram[1]:25 mux_tree_tapbuf_size8_1_sram[1]:24 8.423914e-05 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0] 0.00275242 //LENGTH 18.865 LUMPCC 0.0004844683 DR + +*CONN +*I mux_top_track_0\/mux_l2_in_1_:X O *L 0 *C 55.375 121.380 +*I mux_top_track_0\/mux_l3_in_0_:A0 I *L 0.001631 *C 41.230 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 41.230 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 41.230 123.760 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 48.760 123.760 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 48.760 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 53.315 124.100 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 53.360 124.055 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 53.360 121.425 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 53.405 121.380 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 55.338 121.380 + +*CAP +0 mux_top_track_0\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_0\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 5.691971e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0004720473 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000471448 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00030558 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.000278201 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001859178 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0001859178 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0001549598 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001549598 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 top_left_grid_pin_38_[0]:14 2.355596e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 top_left_grid_pin_38_[0]:19 7.750907e-05 +13 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 top_left_grid_pin_38_[0]:15 2.355596e-05 +14 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 top_left_grid_pin_38_[0]:18 7.750907e-05 +15 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 ropt_net_206:2 4.453261e-05 +16 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 ropt_net_206:3 4.453261e-05 +17 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 ropt_net_194:11 1.273621e-05 +18 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 ropt_net_194:10 1.273621e-05 +19 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 ropt_net_194:9 4.98796e-06 +20 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 ropt_net_194:7 7.891234e-05 +21 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 ropt_net_194:8 4.98796e-06 +22 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 ropt_net_194:6 7.891234e-05 + +*RES +0 mux_top_track_0\/mux_l2_in_1_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.001725446 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.002348214 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.004066965 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0045 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_0\/mux_l3_in_0_:A0 0.152 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003035715 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.006723214 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0003035715 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008450625 //LENGTH 6.340 LUMPCC 0.0001366361 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_2_:X O *L 0 *C 54.455 15.640 +*I mux_bottom_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 51.425 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 51.463 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 52.855 18.020 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 52.900 17.975 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 52.900 15.685 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 52.945 15.640 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 54.418 15.640 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.000117252 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000117252 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00015161 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00015161 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.435122e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.435122e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 bottom_left_grid_pin_39_[0]:10 6.831807e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 bottom_left_grid_pin_39_[0]:9 6.831807e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001243304 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002044643 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000690625 //LENGTH 4.675 LUMPCC 0 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_0_:X O *L 0 *C 35.245 104.040 +*I mux_top_track_2\/mux_l3_in_0_:A1 I *L 0.00198 *C 33.580 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 33.617 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 34.915 101.660 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 34.960 101.705 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 34.960 103.995 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 34.960 104.040 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 35.245 104.040 + +*CAP +0 mux_top_track_2\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001263843 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001263843 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001555637 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001555637 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.176044e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.296865e-05 + +*RES +0 mux_top_track_2\/mux_l2_in_0_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001158482 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A1 0.152 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001818774 //LENGTH 15.205 LUMPCC 0.0005906681 DR + +*CONN +*I mux_top_track_8\/mux_l1_in_0_:X O *L 0 *C 77.565 114.920 +*I mux_top_track_8\/mux_l2_in_0_:A1 I *L 0.00198 *C 81.980 105.060 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 81.943 105.060 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 79.165 105.060 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 79.120 105.105 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 79.120 114.875 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 79.075 114.920 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 77.603 114.920 + +*CAP +0 mux_top_track_8\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_8\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001841374 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001841374 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003098837 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003098837 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001190318 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001190318 +8 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 chany_bottom_in[4]:14 1.261115e-05 +9 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chany_bottom_in[4]:13 1.261115e-05 +10 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[4]:13 7.229955e-05 +11 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[4]:12 7.229955e-05 +12 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[18]:7 0.0001235359 +13 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[18]:4 2.306531e-06 +14 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[18]:6 0.0001235359 +15 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[18]:5 2.306531e-06 +16 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[0]:10 5.958738e-05 +17 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[0]:16 2.107824e-06 +18 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[0]:20 2.221249e-05 +19 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[0]:22 6.732122e-07 +20 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:11 5.958738e-05 +21 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:17 2.107824e-06 +22 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:21 2.221249e-05 +23 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[0]:23 6.732122e-07 + +*RES +0 mux_top_track_8\/mux_l1_in_0_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_8\/mux_l2_in_0_:A1 0.152 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002479911 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.008723214 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001314732 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0] 0.001173984 //LENGTH 8.735 LUMPCC 0 DR + +*CONN +*I mux_top_track_4\/mux_l3_in_0_:X O *L 0 *C 61.005 117.640 +*I mux_top_track_4\/mux_l4_in_0_:A1 I *L 0.00198 *C 69.000 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 *C 69.000 117.980 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 *C 69.000 117.640 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 *C 61.043 117.640 + +*CAP +0 mux_top_track_4\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_4\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 5.636328e-05 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.0005716711 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.00054395 + +*RES +0 mux_top_track_4\/mux_l3_in_0_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 0.007104911 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 mux_top_track_4\/mux_l4_in_0_:A1 0.152 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_11_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0] 0.001275909 //LENGTH 10.060 LUMPCC 0.0002587891 DR + +*CONN +*I mux_top_track_4\/mux_l2_in_1_:X O *L 0 *C 55.025 113.560 +*I mux_top_track_4\/mux_l3_in_0_:A0 I *L 0.001631 *C 59.055 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 *C 59.018 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 *C 55.705 118.660 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 *C 55.660 118.615 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 *C 55.660 113.605 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 *C 55.615 113.560 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 *C 55.062 113.560 + +*CAP +0 mux_top_track_4\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.0001780994 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0001780994 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.0002523325 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0002523325 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 7.712807e-05 +7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 7.712807e-05 +8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 chany_bottom_in[12]:12 5.293314e-05 +9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 chany_bottom_in[12]:13 5.293314e-05 +10 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:6 7.646141e-05 +11 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.646141e-05 + +*RES +0 mux_top_track_4\/mux_l2_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 mux_top_track_4\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:2 0.002957589 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:3 0.0045 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 0.0045 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:4 0.004473215 +6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:7 mux_top_track_4/sky130_fd_sc_hd__mux2_1_8_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001099804 //LENGTH 9.580 LUMPCC 0.0001081289 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_3_:X O *L 0 *C 35.245 3.400 +*I mux_bottom_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 37.435 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 37.398 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 36.385 9.860 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 36.340 9.815 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 36.340 3.445 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 36.295 3.400 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 35.282 3.400 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 8.571934e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.571934e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0003569971 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0003569971 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.212091e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.212091e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size14_1_sram[0]:22 5.383877e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size14_1_sram[0]:21 5.383877e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size14_1_sram[0]:29 2.257013e-07 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size14_1_sram[0]:30 2.257013e-07 + +*RES +0 mux_bottom_track_5\/mux_l1_in_3_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0009040179 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0056875 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000904018 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002665331 //LENGTH 19.985 LUMPCC 0.0009286152 DR + +*CONN +*I mux_top_track_24\/mux_l1_in_0_:X O *L 0 *C 38.815 107.100 +*I mux_top_track_24\/mux_l2_in_0_:A1 I *L 0.00198 *C 38.640 88.740 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 38.640 88.755 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 38.640 89.080 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 38.640 89.125 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 38.640 93.840 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 39.100 93.840 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 39.100 107.055 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 39.100 107.100 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 38.815 107.100 + +*CAP +0 mux_top_track_24\/mux_l1_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l2_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.899899e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.521536e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002390394 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002717998 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005115361 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004787757 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 5.77569e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 6.15934e-05 +10 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chanx_left_in[19]:8 7.700008e-05 +11 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chanx_left_in[19]:9 7.700008e-05 +12 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size7_1_sram[0]:8 0.000339264 +13 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:29 1.212319e-06 +14 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size7_1_sram[0]:30 4.683122e-05 +15 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:8 4.683122e-05 +16 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size7_1_sram[0]:30 1.212319e-06 +17 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size7_1_sram[0]:30 0.000339264 + +*RES +0 mux_top_track_24\/mux_l1_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001548913 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01179911 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001766304 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_top_track_24\/mux_l2_in_0_:A1 0.152 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.004209822 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0004107143 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0007700294 //LENGTH 5.800 LUMPCC 8.194258e-05 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_3_:X O *L 0 *C 42.145 45.560 +*I mux_bottom_track_17\/mux_l2_in_1_:A0 I *L 0.001631 *C 44.295 48.280 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 44.258 48.280 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 43.745 48.280 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 43.700 48.235 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 43.700 45.605 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 43.655 45.560 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 42.183 45.560 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_3_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 7.141975e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 7.141975e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001720024 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001720024 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 9.962125e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.962125e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size7_2_sram[0]:20 2.775867e-05 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:21 2.775867e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:11 1.321262e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size7_2_sram[0]:10 1.321262e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_3_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0004575893 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_17\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001162671 //LENGTH 7.560 LUMPCC 0.000354609 DR + +*CONN +*I mux_left_track_3\/mux_l1_in_1_:X O *L 0 *C 29.615 86.020 +*I mux_left_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 30.190 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 30.190 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 30.360 80.920 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 30.360 80.965 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 30.360 82.575 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 30.315 82.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 29.485 82.620 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 29.440 82.665 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 29.440 85.975 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 29.440 86.020 +*N mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 29.615 86.020 + +*CAP +0 mux_left_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.492219e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.533743e-05 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.791675e-05 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.791675e-05 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 4.496251e-05 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.496251e-05 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001473229 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001473229 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.829703e-05 +11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.710121e-05 +12 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_4_sram[0]:10 2.274172e-05 +13 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size7_4_sram[0]:26 2.274172e-05 +14 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_4_sram[0]:26 2.274172e-05 +15 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size7_4_sram[0]:27 2.274172e-05 +16 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_tree_tapbuf_size7_4_sram[0]:25 7.042364e-05 +17 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size7_4_sram[0]:24 7.042364e-05 +18 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_139:74 5.300822e-05 +19 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_139:70 5.300822e-05 +20 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 optlc_net_139:74 8.389214e-06 +21 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 optlc_net_139:70 8.389214e-06 + +*RES +0 mux_left_track_3\/mux_l1_in_1_:X mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_3\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0014375 +6 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0007410714 +7 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +8 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.002955357 +10 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001229423 //LENGTH 8.255 LUMPCC 0.0006144463 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_1_:X O *L 0 *C 59.055 57.800 +*I mux_left_track_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 54.110 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 54.148 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 58.375 55.420 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.420 55.465 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.420 57.755 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.465 57.800 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 59.018 57.800 + +*CAP +0 mux_left_track_7\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001845642 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001845642 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.85626e-05 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.85626e-05 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.336175e-05 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.336175e-05 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[18]:20 7.069979e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[18]:19 7.069979e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chany_bottom_in[19]:4 0.0001657813 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chany_bottom_in[19]:5 0.0001657813 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chanx_left_in[1]:6 7.074208e-05 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chanx_left_in[1]:5 7.074208e-05 + +*RES +0 mux_left_track_7\/mux_l1_in_1_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_7\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.003774554 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001410531 //LENGTH 9.840 LUMPCC 0.0002774912 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_1_:X O *L 0 *C 64.685 17.000 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 74.235 17.000 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 74.198 17.000 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 64.722 17.000 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00056552 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00056552 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 bottom_right_grid_pin_1_[0]:10 0.0001387456 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 bottom_right_grid_pin_1_[0]:11 0.0001387456 + +*RES +0 mux_bottom_track_25\/mux_l1_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.008459821 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0004794884 //LENGTH 3.760 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_2_:X O *L 0 *C 11.325 41.820 +*I mux_bottom_track_33\/mux_l2_in_1_:A1 I *L 0.00198 *C 12.420 39.780 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 12.420 39.780 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 12.420 39.825 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 12.420 41.775 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 12.375 41.820 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 11.363 41.820 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 3.473622e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001340023 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001340023 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 8.73738e-05 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 8.73738e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_2_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0009040179 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001741071 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_33\/mux_l2_in_1_:A1 0.152 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0] 0.0004250158 //LENGTH 2.865 LUMPCC 9.787575e-05 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_0_:X O *L 0 *C 24.205 39.780 +*I mux_bottom_track_3\/mux_l4_in_0_:A1 I *L 0.00198 *C 26.780 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 *C 26.742 39.780 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 *C 24.242 39.780 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l4_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.00016257 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.00016257 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_tree_tapbuf_size9_0_sram[3]:9 4.893787e-05 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_tree_tapbuf_size9_0_sram[3]:10 4.893787e-05 + +*RES +0 mux_bottom_track_3\/mux_l3_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 mux_bottom_track_3\/mux_l4_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 0.002232143 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0] 0.01215613 //LENGTH 79.440 LUMPCC 0.00401289 DR + +*CONN +*I mux_left_track_11\/mux_l3_in_0_:X O *L 0 *C 81.595 47.600 +*I mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 10.865 44.745 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 10.902 44.835 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 13.295 44.880 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 13.340 44.880 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 13.348 44.880 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 52.893 44.880 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 52.900 44.938 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 52.900 49.583 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 52.908 49.640 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 *C 77.733 49.640 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 *C 77.740 49.583 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 *C 77.740 47.645 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 *C 77.785 47.600 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 *C 81.558 47.600 + +*CAP +0 mux_left_track_11\/mux_l3_in_0_:X 1e-06 +1 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002055992 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002055992 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 3.899131e-05 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001822844 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001822844 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002225993 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0002225993 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.001488927 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.001488927 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.0001297746 +12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0001297746 +13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.0001813789 +14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.0001813789 +15 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 left_top_grid_pin_43_[0]:12 3.254224e-06 +16 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 left_top_grid_pin_43_[0]:13 3.254224e-06 +17 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 left_top_grid_pin_43_[0]:14 0.0002959369 +18 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 left_top_grid_pin_43_[0]:15 0.0002959369 +19 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 chanx_left_in[17]:12 0.0004955567 +20 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 chanx_left_in[17]:13 0.0004955567 +21 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_tree_tapbuf_size4_2_sram[0]:14 0.0001558575 +22 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size4_2_sram[0]:7 3.209358e-05 +23 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size4_2_sram[0]:12 1.831625e-05 +24 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size4_2_sram[0]:13 0.0001558575 +25 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size4_2_sram[0]:8 3.209358e-05 +26 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size4_2_sram[0]:11 1.831625e-05 +27 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:3 0.0001285981 +28 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_tree_tapbuf_size4_mem_1_ccff_tail[0]:2 0.0001285981 +29 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size7_2_sram[0]:25 0.0003173485 +30 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size7_2_sram[0]:24 0.0003173485 +31 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 optlc_net_137:15 0.0004004423 +32 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 optlc_net_137:14 0.0004004423 +33 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000159041 +34 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000159041 + +*RES +0 mux_left_track_11\/mux_l3_in_0_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:14 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 0.003368304 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 0.0045 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 0.001729911 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 0.00341 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.00388925 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.004147321 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.00341 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.00341 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.006195383 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.00341 +12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002136161 +13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_left_track_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0] 0.000488785 //LENGTH 2.940 LUMPCC 0 DR + +*CONN +*I mux_left_track_23\/mux_l1_in_1_:X O *L 0 *C 40.305 80.240 +*I mux_left_track_23\/mux_l2_in_0_:A0 I *L 0.001631 *C 40.770 82.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 40.770 82.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 40.480 82.280 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 40.480 82.235 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 40.480 80.285 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 40.480 80.240 +*N mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 40.305 80.240 + +*CAP +0 mux_left_track_23\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_23\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.321431e-05 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.371928e-05 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001292464 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001292464 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.908436e-05 +7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.22743e-05 + +*RES +0 mux_left_track_23\/mux_l1_in_1_:X mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_23\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001576087 +3 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741071 +6 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_205 0.001168847 //LENGTH 8.395 LUMPCC 0.0002187241 DR + +*CONN +*I ropt_mt_inst_771:X O *L 0 *C 91.540 125.800 +*I ropt_mt_inst_843:A I *L 0.001766 *C 86.020 123.760 +*N ropt_net_205:2 *C 86.020 123.760 +*N ropt_net_205:3 *C 86.020 123.805 +*N ropt_net_205:4 *C 86.020 125.755 +*N ropt_net_205:5 *C 86.020 125.800 +*N ropt_net_205:6 *C 91.502 125.800 + +*CAP +0 ropt_mt_inst_771:X 1e-06 +1 ropt_mt_inst_843:A 1e-06 +2 ropt_net_205:2 3.613932e-05 +3 ropt_net_205:3 0.0001348097 +4 ropt_net_205:4 0.0001348097 +5 ropt_net_205:5 0.0003358811 +6 ropt_net_205:6 0.0003064828 +7 ropt_net_205:3 chany_bottom_in[4]:9 4.375061e-07 +8 ropt_net_205:5 chany_bottom_in[4]:5 4.064918e-05 +9 ropt_net_205:5 chany_bottom_in[4]:7 6.827535e-05 +10 ropt_net_205:4 chany_bottom_in[4]:8 4.375061e-07 +11 ropt_net_205:6 chany_bottom_in[4]:4 4.064918e-05 +12 ropt_net_205:6 chany_bottom_in[4]:6 6.827535e-05 + +*RES +0 ropt_mt_inst_771:X ropt_net_205:6 0.152 +1 ropt_net_205:2 ropt_mt_inst_843:A 0.152 +2 ropt_net_205:3 ropt_net_205:2 0.0045 +3 ropt_net_205:5 ropt_net_205:4 0.0045 +4 ropt_net_205:4 ropt_net_205:3 0.001741071 +5 ropt_net_205:6 ropt_net_205:5 0.00489509 + +*END + +*D_NET ropt_net_176 0.0009131427 //LENGTH 6.530 LUMPCC 0.0002229264 DR + +*CONN +*I FTB_14__13:X O *L 0 *C 52.900 7.140 +*I ropt_mt_inst_802:A I *L 0.001766 *C 56.120 9.520 +*N ropt_net_176:2 *C 56.083 9.520 +*N ropt_net_176:3 *C 55.705 9.520 +*N ropt_net_176:4 *C 55.660 9.475 +*N ropt_net_176:5 *C 55.660 7.185 +*N ropt_net_176:6 *C 55.615 7.140 +*N ropt_net_176:7 *C 52.938 7.140 + +*CAP +0 FTB_14__13:X 1e-06 +1 ropt_mt_inst_802:A 1e-06 +2 ropt_net_176:2 5.62683e-05 +3 ropt_net_176:3 5.62683e-05 +4 ropt_net_176:4 0.0001569612 +5 ropt_net_176:5 0.0001569612 +6 ropt_net_176:6 0.0001308787 +7 ropt_net_176:7 0.0001308787 +8 ropt_net_176:7 chany_top_in[5]:13 0.0001114632 +9 ropt_net_176:6 chany_top_in[5]:9 0.0001114632 + +*RES +0 FTB_14__13:X ropt_net_176:7 0.152 +1 ropt_net_176:7 ropt_net_176:6 0.002390625 +2 ropt_net_176:6 ropt_net_176:5 0.0045 +3 ropt_net_176:5 ropt_net_176:4 0.002044643 +4 ropt_net_176:3 ropt_net_176:2 0.0003370536 +5 ropt_net_176:4 ropt_net_176:3 0.0045 +6 ropt_net_176:2 ropt_mt_inst_802:A 0.152 + +*END + +*D_NET ropt_net_174 0.001073529 //LENGTH 7.100 LUMPCC 0.0003634465 DR + +*CONN +*I FTB_27__26:X O *L 0 *C 68.080 123.420 +*I ropt_mt_inst_800:A I *L 0.001766 *C 64.400 121.040 +*N ropt_net_174:2 *C 64.400 121.040 +*N ropt_net_174:3 *C 64.400 121.720 +*N ropt_net_174:4 *C 66.655 121.720 +*N ropt_net_174:5 *C 66.700 121.765 +*N ropt_net_174:6 *C 66.700 123.375 +*N ropt_net_174:7 *C 66.745 123.420 +*N ropt_net_174:8 *C 68.043 123.420 + +*CAP +0 FTB_27__26:X 1e-06 +1 ropt_mt_inst_800:A 1e-06 +2 ropt_net_174:2 8.285969e-05 +3 ropt_net_174:3 0.0001603763 +4 ropt_net_174:4 0.0001098391 +5 ropt_net_174:5 4.446867e-05 +6 ropt_net_174:6 4.446867e-05 +7 ropt_net_174:7 0.000133035 +8 ropt_net_174:8 0.000133035 +9 ropt_net_174:6 chany_top_in[7]:18 4.968265e-05 +10 ropt_net_174:4 chany_top_in[7]:19 1.688473e-05 +11 ropt_net_174:5 chany_top_in[7]:17 4.968265e-05 +12 ropt_net_174:3 chany_top_in[7]:18 1.688473e-05 +13 ropt_net_174:6 chany_top_in[16]:17 1.106792e-05 +14 ropt_net_174:6 chany_top_in[16]:18 3.861473e-05 +15 ropt_net_174:5 chany_top_in[16]:16 1.106792e-05 +16 ropt_net_174:5 chany_top_in[16]:17 3.861473e-05 +17 ropt_net_174:6 chany_bottom_in[6]:21 2.717849e-06 +18 ropt_net_174:4 chany_bottom_in[6]:24 6.094738e-05 +19 ropt_net_174:4 chany_bottom_in[6]:26 1.681989e-06 +20 ropt_net_174:5 chany_bottom_in[6]:22 2.717849e-06 +21 ropt_net_174:2 chany_bottom_in[6]:25 1.019808e-07 +22 ropt_net_174:2 chany_bottom_in[6]:27 2.404384e-08 +23 ropt_net_174:3 chany_bottom_in[6]:23 6.094738e-05 +24 ropt_net_174:3 chany_bottom_in[6]:24 1.019808e-07 +25 ropt_net_174:3 chany_bottom_in[6]:25 1.681989e-06 +26 ropt_net_174:3 chany_bottom_in[6]:26 2.404384e-08 + +*RES +0 FTB_27__26:X ropt_net_174:8 0.152 +1 ropt_net_174:8 ropt_net_174:7 0.001158482 +2 ropt_net_174:7 ropt_net_174:6 0.0045 +3 ropt_net_174:6 ropt_net_174:5 0.0014375 +4 ropt_net_174:4 ropt_net_174:3 0.002013393 +5 ropt_net_174:5 ropt_net_174:4 0.0045 +6 ropt_net_174:2 ropt_mt_inst_800:A 0.152 +7 ropt_net_174:3 ropt_net_174:2 0.000607143 + +*END + +*D_NET chanx_left_out[19] 0.00175218 //LENGTH 10.555 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_812:X O *L 0 *C 4.140 93.160 +*P chanx_left_out[19] O *L 0.7423 *C 1.305 91.120 +*N chanx_left_out[19]:2 *C 1.380 91.800 +*N chanx_left_out[19]:3 *C 5.973 91.800 +*N chanx_left_out[19]:4 *C 5.980 91.858 +*N chanx_left_out[19]:5 *C 5.980 93.455 +*N chanx_left_out[19]:6 *C 5.935 93.500 +*N chanx_left_out[19]:7 *C 4.600 93.500 +*N chanx_left_out[19]:8 *C 4.600 93.160 +*N chanx_left_out[19]:9 *C 4.178 93.160 + +*CAP +0 ropt_mt_inst_812:X 1e-06 +1 chanx_left_out[19] 5.952018e-05 +2 chanx_left_out[19]:2 0.000596516 +3 chanx_left_out[19]:3 0.0005369958 +4 chanx_left_out[19]:4 0.0001195592 +5 chanx_left_out[19]:5 0.0001195592 +6 chanx_left_out[19]:6 9.440988e-05 +7 chanx_left_out[19]:7 0.0001197284 +8 chanx_left_out[19]:8 6.510493e-05 +9 chanx_left_out[19]:9 3.978638e-05 + +*RES +0 ropt_mt_inst_812:X chanx_left_out[19]:9 0.152 +1 chanx_left_out[19]:9 chanx_left_out[19]:8 0.0003772322 +2 chanx_left_out[19]:6 chanx_left_out[19]:5 0.0045 +3 chanx_left_out[19]:5 chanx_left_out[19]:4 0.001426339 +4 chanx_left_out[19]:4 chanx_left_out[19]:3 0.00341 +5 chanx_left_out[19]:3 chanx_left_out[19]:2 0.0007194916 +6 chanx_left_out[19]:8 chanx_left_out[19]:7 0.0003035715 +7 chanx_left_out[19]:7 chanx_left_out[19]:6 0.001191964 +8 chanx_left_out[19]:2 chanx_left_out[19] 0.0001065333 + +*END + +*D_NET ropt_net_198 0.0008339072 //LENGTH 5.490 LUMPCC 0.0002234815 DR + +*CONN +*I ropt_mt_inst_797:X O *L 0 *C 52.635 4.080 +*I ropt_mt_inst_831:A I *L 0.001767 *C 53.820 6.800 +*N ropt_net_198:2 *C 53.820 6.800 +*N ropt_net_198:3 *C 53.820 6.755 +*N ropt_net_198:4 *C 53.820 3.785 +*N ropt_net_198:5 *C 53.775 3.740 +*N ropt_net_198:6 *C 52.900 3.740 +*N ropt_net_198:7 *C 52.900 4.045 +*N ropt_net_198:8 *C 52.663 4.058 + +*CAP +0 ropt_mt_inst_797:X 1e-06 +1 ropt_mt_inst_831:A 1e-06 +2 ropt_net_198:2 3.849929e-05 +3 ropt_net_198:3 0.0001656718 +4 ropt_net_198:4 0.0001656718 +5 ropt_net_198:5 4.74803e-05 +6 ropt_net_198:6 7.109593e-05 +7 ropt_net_198:7 7.181108e-05 +8 ropt_net_198:8 4.819544e-05 +9 ropt_net_198:3 bottom_right_grid_pin_1_[0]:8 1.75376e-07 +10 ropt_net_198:5 bottom_right_grid_pin_1_[0]:6 4.276652e-05 +11 ropt_net_198:4 bottom_right_grid_pin_1_[0]:7 1.75376e-07 +12 ropt_net_198:8 bottom_right_grid_pin_1_[0]:5 5.695994e-07 +13 ropt_net_198:7 bottom_right_grid_pin_1_[0]:6 5.695994e-07 +14 ropt_net_198:6 bottom_right_grid_pin_1_[0]:5 4.276652e-05 +15 ropt_net_198:3 chany_bottom_out[9]:2 6.822928e-05 +16 ropt_net_198:4 chany_bottom_out[9] 6.822928e-05 + +*RES +0 ropt_mt_inst_797:X ropt_net_198:8 0.152 +1 ropt_net_198:2 ropt_mt_inst_831:A 0.152 +2 ropt_net_198:3 ropt_net_198:2 0.0045 +3 ropt_net_198:5 ropt_net_198:4 0.0045 +4 ropt_net_198:4 ropt_net_198:3 0.002651786 +5 ropt_net_198:8 ropt_net_198:7 0.000160473 +6 ropt_net_198:7 ropt_net_198:6 0.0002723215 +7 ropt_net_198:6 ropt_net_198:5 0.0007812501 + +*END + +*D_NET chanx_left_out[16] 0.0005806701 //LENGTH 5.085 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_823:X O *L 0 *C 4.140 33.320 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 31.960 +*N chanx_left_out[16]:2 *C 2.752 31.960 +*N chanx_left_out[16]:3 *C 2.760 32.017 +*N chanx_left_out[16]:4 *C 2.760 33.275 +*N chanx_left_out[16]:5 *C 2.805 33.320 +*N chanx_left_out[16]:6 *C 4.103 33.320 + +*CAP +0 ropt_mt_inst_823:X 1e-06 +1 chanx_left_out[16] 0.0001025588 +2 chanx_left_out[16]:2 0.0001025588 +3 chanx_left_out[16]:3 8.439327e-05 +4 chanx_left_out[16]:4 8.439327e-05 +5 chanx_left_out[16]:5 0.0001028829 +6 chanx_left_out[16]:6 0.0001028829 + +*RES +0 ropt_mt_inst_823:X chanx_left_out[16]:6 0.152 +1 chanx_left_out[16]:6 chanx_left_out[16]:5 0.001158482 +2 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +3 chanx_left_out[16]:4 chanx_left_out[16]:3 0.001122768 +4 chanx_left_out[16]:3 chanx_left_out[16]:2 0.00341 +5 chanx_left_out[16]:2 chanx_left_out[16] 0.000238525 + +*END + +*D_NET chany_bottom_out[5] 0.001662113 //LENGTH 13.385 LUMPCC 8.224021e-05 DR + +*CONN +*I ropt_mt_inst_834:X O *L 0 *C 78.200 7.140 +*P chany_bottom_out[5] O *L 0.7423 *C 71.760 1.325 +*N chany_bottom_out[5]:2 *C 72.220 1.360 +*N chany_bottom_out[5]:3 *C 72.220 6.075 +*N chany_bottom_out[5]:4 *C 72.265 6.120 +*N chany_bottom_out[5]:5 *C 73.600 6.120 +*N chany_bottom_out[5]:6 *C 73.600 6.800 +*N chany_bottom_out[5]:7 *C 76.820 6.800 +*N chany_bottom_out[5]:8 *C 76.820 7.140 +*N chany_bottom_out[5]:9 *C 78.163 7.140 + +*CAP +0 ropt_mt_inst_834:X 1e-06 +1 chany_bottom_out[5] 3.280293e-05 +2 chany_bottom_out[5]:2 0.0003162777 +3 chany_bottom_out[5]:3 0.0002834748 +4 chany_bottom_out[5]:4 0.0001065368 +5 chany_bottom_out[5]:5 0.0001509869 +6 chany_bottom_out[5]:6 0.0002701843 +7 chany_bottom_out[5]:7 0.0002531346 +8 chany_bottom_out[5]:8 9.64378e-05 +9 chany_bottom_out[5]:9 6.903741e-05 +10 chany_bottom_out[5]:9 ropt_net_200:3 2.722933e-05 +11 chany_bottom_out[5]:9 ropt_net_200:5 1.389078e-05 +12 chany_bottom_out[5]:8 ropt_net_200:2 2.722933e-05 +13 chany_bottom_out[5]:8 ropt_net_200:6 1.389078e-05 + +*RES +0 ropt_mt_inst_834:X chany_bottom_out[5]:9 0.152 +1 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.0045 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.004209822 +3 chany_bottom_out[5]:9 chany_bottom_out[5]:8 0.001198661 +4 chany_bottom_out[5]:5 chany_bottom_out[5]:4 0.001191964 +5 chany_bottom_out[5]:6 chany_bottom_out[5]:5 0.0006071429 +6 chany_bottom_out[5]:7 chany_bottom_out[5]:6 0.002875 +7 chany_bottom_out[5]:8 chany_bottom_out[5]:7 0.0003035715 +8 chany_bottom_out[5]:2 chany_bottom_out[5] 0.0004107143 + +*END + +*D_NET chany_top_in[16] 0.01734253 //LENGTH 142.685 LUMPCC 0.00541003 DR + +*CONN +*P chany_top_in[16] I *L 0.29796 *C 69.460 129.235 +*I mux_left_track_21\/mux_l1_in_0_:A1 I *L 0.00198 *C 54.645 72.420 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 72.050 15.300 +*I FTB_16__15:A I *L 0.001776 *C 63.940 12.240 +*N chany_top_in[16]:4 *C 63.978 12.240 +*N chany_top_in[16]:5 *C 66.655 12.240 +*N chany_top_in[16]:6 *C 66.700 12.285 +*N chany_top_in[16]:7 *C 72.013 15.300 +*N chany_top_in[16]:8 *C 66.745 15.300 +*N chany_top_in[16]:9 *C 66.700 15.300 +*N chany_top_in[16]:10 *C 66.700 65.300 +*N chany_top_in[16]:11 *C 54.683 72.420 +*N chany_top_in[16]:12 *C 65.320 72.420 +*N chany_top_in[16]:13 *C 65.320 72.080 +*N chany_top_in[16]:14 *C 66.655 72.080 +*N chany_top_in[16]:15 *C 66.700 72.080 +*N chany_top_in[16]:16 *C 67.160 72.080 +*N chany_top_in[16]:17 *C 67.160 122.010 +*N chany_top_in[16]:18 *C 67.160 128.475 +*N chany_top_in[16]:19 *C 67.205 128.520 +*N chany_top_in[16]:20 *C 69.415 128.520 +*N chany_top_in[16]:21 *C 69.460 128.565 + +*CAP +0 chany_top_in[16] 6.212002e-05 +1 mux_left_track_21\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +3 FTB_16__15:A 1e-06 +4 chany_top_in[16]:4 0.0001232634 +5 chany_top_in[16]:5 0.0001232634 +6 chany_top_in[16]:6 0.0001545837 +7 chany_top_in[16]:7 0.0003583393 +8 chany_top_in[16]:8 0.0003583393 +9 chany_top_in[16]:9 0.002157978 +10 chany_top_in[16]:10 0.002262092 +11 chany_top_in[16]:11 0.0005223474 +12 chany_top_in[16]:12 0.0005470953 +13 chany_top_in[16]:13 9.738552e-05 +14 chany_top_in[16]:14 7.263757e-05 +15 chany_top_in[16]:15 0.0003030942 +16 chany_top_in[16]:16 0.001901778 +17 chany_top_in[16]:17 0.002154994 +18 chany_top_in[16]:18 0.0002644103 +19 chany_top_in[16]:19 0.0002018276 +20 chany_top_in[16]:20 0.0002018276 +21 chany_top_in[16]:21 6.212002e-05 +22 chany_top_in[16]:18 chany_top_in[7] 0.0001276507 +23 chany_top_in[16]:18 chany_top_in[7]:18 2.874471e-06 +24 chany_top_in[16]:16 chany_top_in[7]:17 0.0002117948 +25 chany_top_in[16]:17 chany_top_in[7]:17 2.874471e-06 +26 chany_top_in[16]:17 chany_top_in[7]:18 0.0002117948 +27 chany_top_in[16]:17 chany_top_in[7]:19 0.0001276507 +28 chany_top_in[16]:6 chany_bottom_in[4]:33 3.426684e-05 +29 chany_top_in[16]:9 chany_bottom_in[4]:33 0.0004498252 +30 chany_top_in[16]:9 chany_bottom_in[4]:32 0.000213885 +31 chany_top_in[16]:15 chany_bottom_in[4]:31 8.602332e-05 +32 chany_top_in[16]:16 chany_bottom_in[4]:32 0.0001429812 +33 chany_top_in[16]:10 chany_bottom_in[4]:31 0.0001796182 +34 chany_top_in[16]:10 chany_bottom_in[4]:32 0.0005358485 +35 chany_top_in[16]:17 chany_bottom_in[4]:31 0.0001429812 +36 chany_top_in[16]:14 chany_bottom_in[16]:18 5.914487e-05 +37 chany_top_in[16]:15 chany_bottom_in[16]:20 6.913083e-07 +38 chany_top_in[16]:15 chany_bottom_in[16]:17 2.082422e-05 +39 chany_top_in[16]:11 chany_bottom_in[16]:17 0.0001524659 +40 chany_top_in[16]:12 chany_bottom_in[16]:18 0.0001524659 +41 chany_top_in[16]:13 chany_bottom_in[16]:17 5.914487e-05 +42 chany_top_in[16]:16 chany_bottom_in[16]:18 2.082422e-05 +43 chany_top_in[16]:16 chany_bottom_in[16]:19 2.581228e-05 +44 chany_top_in[16]:10 chany_bottom_in[16]:19 6.913083e-07 +45 chany_top_in[16]:17 chany_bottom_in[16]:20 2.581228e-05 +46 chany_top_in[16] chany_top_out[8] 3.718108e-06 +47 chany_top_in[16]:18 chany_top_out[8] 5.276372e-06 +48 chany_top_in[16]:18 chany_top_out[8]:5 3.02523e-05 +49 chany_top_in[16]:21 chany_top_out[8]:2 3.718108e-06 +50 chany_top_in[16]:16 chany_top_out[8]:6 0.0007221488 +51 chany_top_in[16]:17 chany_top_out[8]:6 3.02523e-05 +52 chany_top_in[16]:17 chany_top_out[8]:5 0.0007221488 +53 chany_top_in[16]:17 chany_top_out[8]:2 5.276372e-06 +54 chany_top_in[16]:9 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 6.128893e-05 +55 chany_top_in[16]:10 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 6.128893e-05 +56 chany_top_in[16]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.351527e-05 +57 chany_top_in[16]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.200997e-05 +58 chany_top_in[16]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.351527e-05 +59 chany_top_in[16]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.200997e-05 +60 chany_top_in[16]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001477146 +61 chany_top_in[16]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001477146 +62 chany_top_in[16]:5 ropt_net_165:5 9.543475e-05 +63 chany_top_in[16]:4 ropt_net_165:4 9.543475e-05 +64 chany_top_in[16]:18 ropt_net_174:6 3.861473e-05 +65 chany_top_in[16]:16 ropt_net_174:5 1.106792e-05 +66 chany_top_in[16]:17 ropt_net_174:6 1.106792e-05 +67 chany_top_in[16]:17 ropt_net_174:5 3.861473e-05 + +*RES +0 chany_top_in[16] chany_top_in[16]:21 0.0005982143 +1 chany_top_in[16]:19 chany_top_in[16]:18 0.0045 +2 chany_top_in[16]:18 chany_top_in[16]:17 0.005772321 +3 chany_top_in[16]:20 chany_top_in[16]:19 0.001973214 +4 chany_top_in[16]:21 chany_top_in[16]:20 0.0045 +5 chany_top_in[16]:5 chany_top_in[16]:4 0.002390625 +6 chany_top_in[16]:6 chany_top_in[16]:5 0.0045 +7 chany_top_in[16]:4 FTB_16__15:A 0.152 +8 chany_top_in[16]:8 chany_top_in[16]:7 0.004703125 +9 chany_top_in[16]:9 chany_top_in[16]:8 0.0045 +10 chany_top_in[16]:9 chany_top_in[16]:6 0.002691965 +11 chany_top_in[16]:7 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +12 chany_top_in[16]:14 chany_top_in[16]:13 0.001191964 +13 chany_top_in[16]:15 chany_top_in[16]:14 0.0045 +14 chany_top_in[16]:15 chany_top_in[16]:10 0.006053572 +15 chany_top_in[16]:11 mux_left_track_21\/mux_l1_in_0_:A1 0.152 +16 chany_top_in[16]:12 chany_top_in[16]:11 0.009497768 +17 chany_top_in[16]:13 chany_top_in[16]:12 0.0003035715 +18 chany_top_in[16]:16 chany_top_in[16]:15 0.0004107143 +19 chany_top_in[16]:10 chany_top_in[16]:9 0.04464286 +20 chany_top_in[16]:17 chany_top_in[16]:16 0.04458036 + +*END + +*D_NET chanx_left_in[17] 0.0106098 //LENGTH 72.985 LUMPCC 0.002706458 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.305 55.760 +*I mux_bottom_track_5\/mux_l1_in_6_:A0 I *L 0.001631 *C 34.215 44.540 +*I mux_top_track_16\/mux_l1_in_3_:A1 I *L 0.00198 *C 37.820 66.980 +*N chanx_left_in[17]:3 *C 37.782 66.980 +*N chanx_left_in[17]:4 *C 26.725 66.980 +*N chanx_left_in[17]:5 *C 26.680 66.935 +*N chanx_left_in[17]:6 *C 26.680 57.178 +*N chanx_left_in[17]:7 *C 26.673 57.120 +*N chanx_left_in[17]:8 *C 34.178 44.540 +*N chanx_left_in[17]:9 *C 32.705 44.540 +*N chanx_left_in[17]:10 *C 32.660 44.585 +*N chanx_left_in[17]:11 *C 32.660 45.503 +*N chanx_left_in[17]:12 *C 32.653 45.560 +*N chanx_left_in[17]:13 *C 23.940 45.560 +*N chanx_left_in[17]:14 *C 23.920 45.568 +*N chanx_left_in[17]:15 *C 23.920 57.113 +*N chanx_left_in[17]:16 *C 23.920 57.120 +*N chanx_left_in[17]:17 *C 1.380 57.120 + +*CAP +0 chanx_left_in[17] 9.354098e-05 +1 mux_bottom_track_5\/mux_l1_in_6_:A0 1e-06 +2 mux_top_track_16\/mux_l1_in_3_:A1 1e-06 +3 chanx_left_in[17]:3 0.0006139099 +4 chanx_left_in[17]:4 0.0006139099 +5 chanx_left_in[17]:5 0.0005461458 +6 chanx_left_in[17]:6 0.0005461458 +7 chanx_left_in[17]:7 0.0001296801 +8 chanx_left_in[17]:8 0.00015725 +9 chanx_left_in[17]:9 0.00015725 +10 chanx_left_in[17]:10 9.368722e-05 +11 chanx_left_in[17]:11 9.368722e-05 +12 chanx_left_in[17]:12 0.0003277934 +13 chanx_left_in[17]:13 0.0003277934 +14 chanx_left_in[17]:14 0.0007001392 +15 chanx_left_in[17]:15 0.0007001392 +16 chanx_left_in[17]:16 0.001418202 +17 chanx_left_in[17]:17 0.001382063 +18 chanx_left_in[17]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 3.223907e-07 +19 chanx_left_in[17]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.428581e-05 +20 chanx_left_in[17]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.223907e-07 +21 chanx_left_in[17]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.428581e-05 +22 chanx_left_in[17]:13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0004955567 +23 chanx_left_in[17]:12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0004955567 +24 chanx_left_in[17]:13 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.342247e-05 +25 chanx_left_in[17]:12 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.342247e-05 +26 chanx_left_in[17]:7 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.000158508 +27 chanx_left_in[17]:16 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000158508 +28 chanx_left_in[17]:16 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0005211336 +29 chanx_left_in[17]:17 mux_left_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0005211336 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:17 0.0002130667 +1 chanx_left_in[17]:6 chanx_left_in[17]:5 0.008712053 +2 chanx_left_in[17]:7 chanx_left_in[17]:6 0.00341 +3 chanx_left_in[17]:4 chanx_left_in[17]:3 0.009872768 +4 chanx_left_in[17]:5 chanx_left_in[17]:4 0.0045 +5 chanx_left_in[17]:3 mux_top_track_16\/mux_l1_in_3_:A1 0.152 +6 chanx_left_in[17]:16 chanx_left_in[17]:15 0.00341 +7 chanx_left_in[17]:16 chanx_left_in[17]:7 0.000431225 +8 chanx_left_in[17]:15 chanx_left_in[17]:14 0.001808717 +9 chanx_left_in[17]:13 chanx_left_in[17]:12 0.001364958 +10 chanx_left_in[17]:14 chanx_left_in[17]:13 0.00341 +11 chanx_left_in[17]:11 chanx_left_in[17]:10 0.0008191965 +12 chanx_left_in[17]:12 chanx_left_in[17]:11 0.00341 +13 chanx_left_in[17]:9 chanx_left_in[17]:8 0.001314732 +14 chanx_left_in[17]:10 chanx_left_in[17]:9 0.0045 +15 chanx_left_in[17]:8 mux_bottom_track_5\/mux_l1_in_6_:A0 0.152 +16 chanx_left_in[17]:17 chanx_left_in[17]:16 0.003531266 + +*END + +*D_NET chany_top_out[0] 0.0004725923 //LENGTH 3.680 LUMPCC 0.0001512872 DR + +*CONN +*I mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 76.360 126.480 +*P chany_top_out[0] O *L 0.7423 *C 76.820 129.235 +*N chany_top_out[0]:2 *C 76.820 126.525 +*N chany_top_out[0]:3 *C 76.775 126.480 +*N chany_top_out[0]:4 *C 76.398 126.480 + +*CAP +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_top_out[0] 0.0001093664 +2 chany_top_out[0]:2 0.0001093664 +3 chany_top_out[0]:3 5.078612e-05 +4 chany_top_out[0]:4 5.078612e-05 +5 chany_top_out[0] ropt_net_190:8 7.564362e-05 +6 chany_top_out[0]:2 ropt_net_190:9 7.564362e-05 + +*RES +0 mux_top_track_0\/sky130_fd_sc_hd__buf_4_0_:X chany_top_out[0]:4 0.152 +1 chany_top_out[0]:3 chany_top_out[0]:2 0.0045 +2 chany_top_out[0]:2 chany_top_out[0] 0.002419643 +3 chany_top_out[0]:4 chany_top_out[0]:3 0.0003370536 + +*END + +*D_NET chany_top_out[8] 0.006122354 //LENGTH 45.275 LUMPCC 0.002711514 DR + +*CONN +*I mux_top_track_16\/mux_l3_in_0_:X O *L 0 *C 59.120 94.520 +*P chany_top_out[8] O *L 0.7423 *C 68.540 129.270 +*N chany_top_out[8]:2 *C 68.540 123.125 +*N chany_top_out[8]:3 *C 68.495 123.080 +*N chany_top_out[8]:4 *C 67.665 123.080 +*N chany_top_out[8]:5 *C 67.620 123.035 +*N chany_top_out[8]:6 *C 67.620 94.565 +*N chany_top_out[8]:7 *C 67.575 94.520 +*N chany_top_out[8]:8 *C 59.158 94.520 + +*CAP +0 mux_top_track_16\/mux_l3_in_0_:X 1e-06 +1 chany_top_out[8] 0.0002738512 +2 chany_top_out[8]:2 0.0002738512 +3 chany_top_out[8]:3 8.561368e-05 +4 chany_top_out[8]:4 8.561368e-05 +5 chany_top_out[8]:5 0.0009552056 +6 chany_top_out[8]:6 0.0009552056 +7 chany_top_out[8]:7 0.0003902493 +8 chany_top_out[8]:8 0.0003902493 +9 chany_top_out[8] chany_top_in[16] 3.718108e-06 +10 chany_top_out[8] chany_top_in[16]:18 5.276372e-06 +11 chany_top_out[8]:6 chany_top_in[16]:16 0.0007221488 +12 chany_top_out[8]:6 chany_top_in[16]:17 3.02523e-05 +13 chany_top_out[8]:5 chany_top_in[16]:17 0.0007221488 +14 chany_top_out[8]:5 chany_top_in[16]:18 3.02523e-05 +15 chany_top_out[8]:2 chany_top_in[16]:17 5.276372e-06 +16 chany_top_out[8]:2 chany_top_in[16]:21 3.718108e-06 +17 chany_top_out[8]:8 mux_top_track_16\/mux_l3_in_0_:S 0.0002676603 +18 chany_top_out[8]:8 mux_tree_tapbuf_size7_0_sram[2]:6 5.626328e-05 +19 chany_top_out[8]:7 mux_tree_tapbuf_size7_0_sram[2]:6 0.0002676603 +20 chany_top_out[8]:7 mux_tree_tapbuf_size7_0_sram[2]:5 5.626328e-05 +21 chany_top_out[8]:6 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 0.0001167083 +22 chany_top_out[8]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 0.0001167083 +23 chany_top_out[8] ropt_net_187:8 4.146818e-05 +24 chany_top_out[8]:6 ropt_net_187:9 3.593909e-05 +25 chany_top_out[8]:4 ropt_net_187:6 1.446594e-06 +26 chany_top_out[8]:5 ropt_net_187:8 3.593909e-05 +27 chany_top_out[8]:3 ropt_net_187:7 1.446594e-06 +28 chany_top_out[8]:2 ropt_net_187:9 4.146818e-05 +29 chany_top_out[8] ropt_net_190:5 7.487576e-05 +30 chany_top_out[8]:2 ropt_net_190:4 7.487576e-05 + +*RES +0 mux_top_track_16\/mux_l3_in_0_:X chany_top_out[8]:8 0.152 +1 chany_top_out[8]:8 chany_top_out[8]:7 0.007515626 +2 chany_top_out[8]:7 chany_top_out[8]:6 0.0045 +3 chany_top_out[8]:6 chany_top_out[8]:5 0.02541965 +4 chany_top_out[8]:4 chany_top_out[8]:3 0.0007410715 +5 chany_top_out[8]:5 chany_top_out[8]:4 0.0045 +6 chany_top_out[8]:3 chany_top_out[8]:2 0.0045 +7 chany_top_out[8]:2 chany_top_out[8] 0.005486608 + +*END + +*D_NET chanx_left_out[1] 0.0008368306 //LENGTH 7.290 LUMPCC 0 DR + +*CONN +*I mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 3.625 85.680 +*P chanx_left_out[1] O *L 0.7423 *C 1.230 81.600 +*N chanx_left_out[1]:2 *C 3.213 81.600 +*N chanx_left_out[1]:3 *C 3.220 81.657 +*N chanx_left_out[1]:4 *C 3.220 85.635 +*N chanx_left_out[1]:5 *C 3.243 85.680 +*N chanx_left_out[1]:6 *C 3.610 85.680 + +*CAP +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[1] 0.0001539576 +2 chanx_left_out[1]:2 0.0001539576 +3 chanx_left_out[1]:3 0.0002196618 +4 chanx_left_out[1]:4 0.0002196618 +5 chanx_left_out[1]:5 4.429602e-05 +6 chanx_left_out[1]:6 4.429602e-05 + +*RES +0 mux_left_track_3\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[1]:6 0.152 +1 chanx_left_out[1]:6 chanx_left_out[1]:5 0.0001997283 +2 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +3 chanx_left_out[1]:4 chanx_left_out[1]:3 0.003551339 +4 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +5 chanx_left_out[1]:2 chanx_left_out[1] 0.0003105916 + +*END + +*D_NET chanx_left_out[8] 0.001381103 //LENGTH 8.500 LUMPCC 0 DR + +*CONN +*I mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 6.385 47.940 +*P chanx_left_out[8] O *L 0.7423 *C 1.305 48.960 +*N chanx_left_out[8]:2 *C 1.380 49.640 +*N chanx_left_out[8]:3 *C 5.973 49.640 +*N chanx_left_out[8]:4 *C 5.980 49.583 +*N chanx_left_out[8]:5 *C 5.980 47.985 +*N chanx_left_out[8]:6 *C 6.003 47.940 +*N chanx_left_out[8]:7 *C 6.370 47.940 + +*CAP +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[8] 5.674758e-05 +2 chanx_left_out[8]:2 0.0005173074 +3 chanx_left_out[8]:3 0.0004605599 +4 chanx_left_out[8]:4 0.0001131314 +5 chanx_left_out[8]:5 0.0001131314 +6 chanx_left_out[8]:6 5.961254e-05 +7 chanx_left_out[8]:7 5.961254e-05 + +*RES +0 mux_left_track_17\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[8]:7 0.152 +1 chanx_left_out[8]:7 chanx_left_out[8]:6 0.0001997283 +2 chanx_left_out[8]:6 chanx_left_out[8]:5 0.0045 +3 chanx_left_out[8]:5 chanx_left_out[8]:4 0.001426339 +4 chanx_left_out[8]:4 chanx_left_out[8]:3 0.00341 +5 chanx_left_out[8]:3 chanx_left_out[8]:2 0.0007194916 +6 chanx_left_out[8]:2 chanx_left_out[8] 0.0001065333 + +*END + +*D_NET mux_tree_tapbuf_size10_mem_0_ccff_tail[0] 0.001748276 //LENGTH 13.290 LUMPCC 0.0005645925 DR + +*CONN +*I mem_top_track_0\/FTB_1__33:X O *L 0 *C 31.965 126.480 +*I mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 32.835 115.260 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 *C 32.835 115.260 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 *C 33.120 115.260 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 *C 33.120 115.305 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 *C 33.120 126.435 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 *C 33.075 126.480 +*N mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 *C 32.003 126.480 + +*CAP +0 mem_top_track_0\/FTB_1__33:X 1e-06 +1 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 4.794833e-05 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 5.251299e-05 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.0004908945 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0004908945 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 4.971644e-05 +7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 4.971644e-05 +8 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 top_left_grid_pin_35_[0]:20 5.513159e-05 +9 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 top_left_grid_pin_35_[0]:19 5.513159e-05 +10 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 top_left_grid_pin_39_[0]:17 0.0002271647 +11 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 top_left_grid_pin_39_[0]:16 0.0002271647 + +*RES +0 mem_top_track_0\/FTB_1__33:X mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 0.0009575893 +2 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 0.009937502 +4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size10_mem_0_ccff_tail[0]:2 mem_top_track_2\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size14_0_sram[3] 0.001154258 //LENGTH 10.610 LUMPCC 0.0001172597 DR + +*CONN +*I mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 68.845 112.880 +*I mem_top_track_4\/FTB_6__38:A I *L 0.001746 *C 69.460 110.160 +*I mux_top_track_4\/mux_l4_in_0_:S I *L 0.00357 *C 70.280 117.640 +*N mux_tree_tapbuf_size14_0_sram[3]:3 *C 70.265 117.640 +*N mux_tree_tapbuf_size14_0_sram[3]:4 *C 69.943 117.640 +*N mux_tree_tapbuf_size14_0_sram[3]:5 *C 69.920 117.595 +*N mux_tree_tapbuf_size14_0_sram[3]:6 *C 69.498 110.160 +*N mux_tree_tapbuf_size14_0_sram[3]:7 *C 69.875 110.160 +*N mux_tree_tapbuf_size14_0_sram[3]:8 *C 69.920 110.205 +*N mux_tree_tapbuf_size14_0_sram[3]:9 *C 69.920 112.880 +*N mux_tree_tapbuf_size14_0_sram[3]:10 *C 69.875 112.880 +*N mux_tree_tapbuf_size14_0_sram[3]:11 *C 68.883 112.880 + +*CAP +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_top_track_4\/FTB_6__38:A 1e-06 +2 mux_top_track_4\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size14_0_sram[3]:3 4.868399e-05 +4 mux_tree_tapbuf_size14_0_sram[3]:4 4.868399e-05 +5 mux_tree_tapbuf_size14_0_sram[3]:5 0.0002091294 +6 mux_tree_tapbuf_size14_0_sram[3]:6 4.748178e-05 +7 mux_tree_tapbuf_size14_0_sram[3]:7 4.748178e-05 +8 mux_tree_tapbuf_size14_0_sram[3]:8 0.0001223432 +9 mux_tree_tapbuf_size14_0_sram[3]:9 0.0003602504 +10 mux_tree_tapbuf_size14_0_sram[3]:10 7.497203e-05 +11 mux_tree_tapbuf_size14_0_sram[3]:11 7.497203e-05 +12 mux_tree_tapbuf_size14_0_sram[3]:5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 3.703852e-05 +13 mux_tree_tapbuf_size14_0_sram[3]:8 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 2.159133e-05 +14 mux_tree_tapbuf_size14_0_sram[3]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:4 2.159133e-05 +15 mux_tree_tapbuf_size14_0_sram[3]:9 mux_top_track_4/sky130_fd_sc_hd__mux2_1_12_X[0]:5 3.703852e-05 + +*RES +0 mem_top_track_4\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size14_0_sram[3]:11 0.152 +1 mux_tree_tapbuf_size14_0_sram[3]:3 mux_top_track_4\/mux_l4_in_0_:S 0.152 +2 mux_tree_tapbuf_size14_0_sram[3]:4 mux_tree_tapbuf_size14_0_sram[3]:3 0.0001752718 +3 mux_tree_tapbuf_size14_0_sram[3]:5 mux_tree_tapbuf_size14_0_sram[3]:4 0.0045 +4 mux_tree_tapbuf_size14_0_sram[3]:7 mux_tree_tapbuf_size14_0_sram[3]:6 0.0003370536 +5 mux_tree_tapbuf_size14_0_sram[3]:8 mux_tree_tapbuf_size14_0_sram[3]:7 0.0045 +6 mux_tree_tapbuf_size14_0_sram[3]:6 mem_top_track_4\/FTB_6__38:A 0.152 +7 mux_tree_tapbuf_size14_0_sram[3]:10 mux_tree_tapbuf_size14_0_sram[3]:9 0.0045 +8 mux_tree_tapbuf_size14_0_sram[3]:9 mux_tree_tapbuf_size14_0_sram[3]:8 0.002388393 +9 mux_tree_tapbuf_size14_0_sram[3]:9 mux_tree_tapbuf_size14_0_sram[3]:5 0.004209822 +10 mux_tree_tapbuf_size14_0_sram[3]:11 mux_tree_tapbuf_size14_0_sram[3]:10 0.0008861608 + +*END + +*D_NET mux_tree_tapbuf_size14_mem_1_ccff_tail[0] 0.0006836557 //LENGTH 4.755 LUMPCC 0.0001745203 DR + +*CONN +*I mem_bottom_track_5\/FTB_7__39:X O *L 0 *C 49.430 9.860 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 51.625 11.900 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 *C 51.520 11.900 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 *C 51.520 11.855 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:4 *C 51.520 9.905 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 *C 51.475 9.860 +*N mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 *C 49.468 9.860 + +*CAP +0 mem_bottom_track_5\/FTB_7__39:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 3.430049e-05 +3 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 0.0001371425 +4 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:4 0.0001371425 +5 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 9.9275e-05 +6 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 9.9275e-05 +7 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:6 8.726015e-05 +8 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_9_X[0]:5 8.726015e-05 + +*RES +0 mem_bottom_track_5\/FTB_7__39:X mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 0.152 +1 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 0.001792411 +2 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:4 0.0045 +3 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 0.001741072 +4 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +5 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size14_mem_1_ccff_tail[0]:2 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.003626739 //LENGTH 27.560 LUMPCC 0.0001984919 DR + +*CONN +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 33.885 55.760 +*I mux_left_track_19\/mux_l1_in_1_:S I *L 0.00357 *C 26.120 58.190 +*I mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 29.615 60.860 +*I mux_left_track_19\/mux_l1_in_0_:S I *L 0.00357 *C 36.440 58.480 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 36.403 58.480 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 33.580 58.480 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 26.150 58.410 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 29.615 60.860 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 29.440 60.520 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 24.425 60.520 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 24.380 60.475 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 24.380 57.845 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 24.425 57.800 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 26.120 57.800 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 26.120 58.190 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 26.190 58.550 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 26.220 58.820 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 33.580 58.790 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 33.580 58.775 +*N mux_tree_tapbuf_size3_1_sram[0]:19 *C 33.580 55.805 +*N mux_tree_tapbuf_size3_1_sram[0]:20 *C 33.580 55.760 +*N mux_tree_tapbuf_size3_1_sram[0]:21 *C 33.885 55.760 + +*CAP +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_left_track_19\/mux_l1_in_1_:S 1e-06 +2 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_left_track_19\/mux_l1_in_0_:S 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 0.0001635188 +5 mux_tree_tapbuf_size3_1_sram[0]:5 0.0001905834 +6 mux_tree_tapbuf_size3_1_sram[0]:6 2.106453e-05 +7 mux_tree_tapbuf_size3_1_sram[0]:7 5.397621e-05 +8 mux_tree_tapbuf_size3_1_sram[0]:8 0.0003750506 +9 mux_tree_tapbuf_size3_1_sram[0]:9 0.0003497046 +10 mux_tree_tapbuf_size3_1_sram[0]:10 0.0001981973 +11 mux_tree_tapbuf_size3_1_sram[0]:11 0.0001981973 +12 mux_tree_tapbuf_size3_1_sram[0]:12 0.0001464324 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0001722507 +14 mux_tree_tapbuf_size3_1_sram[0]:14 8.420052e-05 +15 mux_tree_tapbuf_size3_1_sram[0]:15 3.64599e-05 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.0004758156 +17 mux_tree_tapbuf_size3_1_sram[0]:17 0.0004778448 +18 mux_tree_tapbuf_size3_1_sram[0]:18 0.0001824597 +19 mux_tree_tapbuf_size3_1_sram[0]:19 0.0001824597 +20 mux_tree_tapbuf_size3_1_sram[0]:20 6.028033e-05 +21 mux_tree_tapbuf_size3_1_sram[0]:21 5.575054e-05 +22 mux_tree_tapbuf_size3_1_sram[0]:17 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 1.547233e-05 +23 mux_tree_tapbuf_size3_1_sram[0]:18 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.581897e-06 +24 mux_tree_tapbuf_size3_1_sram[0]:19 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.581897e-06 +25 mux_tree_tapbuf_size3_1_sram[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:8 8.119172e-05 +26 mux_tree_tapbuf_size3_1_sram[0]:16 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.547233e-05 +27 mux_tree_tapbuf_size3_1_sram[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 8.119172e-05 + +*RES +0 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:21 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.006571429 +2 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:5 0.0002767857 +3 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.0045 +4 mux_tree_tapbuf_size3_1_sram[0]:20 mux_tree_tapbuf_size3_1_sram[0]:19 0.0045 +5 mux_tree_tapbuf_size3_1_sram[0]:19 mux_tree_tapbuf_size3_1_sram[0]:18 0.002651786 +6 mux_tree_tapbuf_size3_1_sram[0]:21 mux_tree_tapbuf_size3_1_sram[0]:20 0.0001657609 +7 mux_tree_tapbuf_size3_1_sram[0]:14 mux_left_track_19\/mux_l1_in_1_:S 0.152 +8 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:13 0.0003482143 +9 mux_tree_tapbuf_size3_1_sram[0]:14 mux_tree_tapbuf_size3_1_sram[0]:6 0.0001964286 +10 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.002348214 +12 mux_tree_tapbuf_size3_1_sram[0]:9 mux_tree_tapbuf_size3_1_sram[0]:8 0.004477678 +13 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0045 +14 mux_tree_tapbuf_size3_1_sram[0]:7 mem_left_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +15 mux_tree_tapbuf_size3_1_sram[0]:4 mux_left_track_19\/mux_l1_in_0_:S 0.152 +16 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.001513393 +17 mux_tree_tapbuf_size3_1_sram[0]:8 mux_tree_tapbuf_size3_1_sram[0]:7 0.0003035715 +18 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 1.881721e-05 +19 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.0002410715 +20 mux_tree_tapbuf_size3_1_sram[0]:5 mux_tree_tapbuf_size3_1_sram[0]:4 0.00252009 + +*END + +*D_NET mux_tree_tapbuf_size4_0_sram[1] 0.002160209 //LENGTH 16.885 LUMPCC 0 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 72.525 61.200 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 73.940 63.580 +*I mux_left_track_9\/mux_l2_in_1_:S I *L 0.00357 *C 73.040 68.680 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 77.915 69.700 +*N mux_tree_tapbuf_size4_0_sram[1]:4 *C 77.877 69.700 +*N mux_tree_tapbuf_size4_0_sram[1]:5 *C 76.820 69.700 +*N mux_tree_tapbuf_size4_0_sram[1]:6 *C 76.820 70.040 +*N mux_tree_tapbuf_size4_0_sram[1]:7 *C 73.185 70.040 +*N mux_tree_tapbuf_size4_0_sram[1]:8 *C 73.140 69.995 +*N mux_tree_tapbuf_size4_0_sram[1]:9 *C 73.040 68.680 +*N mux_tree_tapbuf_size4_0_sram[1]:10 *C 73.140 68.680 +*N mux_tree_tapbuf_size4_0_sram[1]:11 *C 73.903 63.580 +*N mux_tree_tapbuf_size4_0_sram[1]:12 *C 73.185 63.580 +*N mux_tree_tapbuf_size4_0_sram[1]:13 *C 73.140 63.580 +*N mux_tree_tapbuf_size4_0_sram[1]:14 *C 73.140 61.245 +*N mux_tree_tapbuf_size4_0_sram[1]:15 *C 73.095 61.200 +*N mux_tree_tapbuf_size4_0_sram[1]:16 *C 72.562 61.200 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:S 1e-06 +2 mux_left_track_9\/mux_l2_in_1_:S 1e-06 +3 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size4_0_sram[1]:4 0.000104035 +5 mux_tree_tapbuf_size4_0_sram[1]:5 0.0001317008 +6 mux_tree_tapbuf_size4_0_sram[1]:6 0.0003274787 +7 mux_tree_tapbuf_size4_0_sram[1]:7 0.0002998129 +8 mux_tree_tapbuf_size4_0_sram[1]:8 8.920787e-05 +9 mux_tree_tapbuf_size4_0_sram[1]:9 3.086551e-05 +10 mux_tree_tapbuf_size4_0_sram[1]:10 0.0003889269 +11 mux_tree_tapbuf_size4_0_sram[1]:11 6.680934e-05 +12 mux_tree_tapbuf_size4_0_sram[1]:12 6.680934e-05 +13 mux_tree_tapbuf_size4_0_sram[1]:13 0.000426498 +14 mux_tree_tapbuf_size4_0_sram[1]:14 0.0001251176 +15 mux_tree_tapbuf_size4_0_sram[1]:15 4.94737e-05 +16 mux_tree_tapbuf_size4_0_sram[1]:16 4.94737e-05 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size4_0_sram[1]:16 0.152 +1 mux_tree_tapbuf_size4_0_sram[1]:7 mux_tree_tapbuf_size4_0_sram[1]:6 0.003245536 +2 mux_tree_tapbuf_size4_0_sram[1]:8 mux_tree_tapbuf_size4_0_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size4_0_sram[1]:4 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +4 mux_tree_tapbuf_size4_0_sram[1]:11 mux_left_track_9\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size4_0_sram[1]:12 mux_tree_tapbuf_size4_0_sram[1]:11 0.000640625 +6 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:12 0.0045 +7 mux_tree_tapbuf_size4_0_sram[1]:13 mux_tree_tapbuf_size4_0_sram[1]:10 0.004553572 +8 mux_tree_tapbuf_size4_0_sram[1]:15 mux_tree_tapbuf_size4_0_sram[1]:14 0.0045 +9 mux_tree_tapbuf_size4_0_sram[1]:14 mux_tree_tapbuf_size4_0_sram[1]:13 0.002084822 +10 mux_tree_tapbuf_size4_0_sram[1]:16 mux_tree_tapbuf_size4_0_sram[1]:15 0.0004754465 +11 mux_tree_tapbuf_size4_0_sram[1]:9 mux_left_track_9\/mux_l2_in_1_:S 0.152 +12 mux_tree_tapbuf_size4_0_sram[1]:10 mux_tree_tapbuf_size4_0_sram[1]:9 0.0045 +13 mux_tree_tapbuf_size4_0_sram[1]:10 mux_tree_tapbuf_size4_0_sram[1]:8 0.001174107 +14 mux_tree_tapbuf_size4_0_sram[1]:6 mux_tree_tapbuf_size4_0_sram[1]:5 0.0003035715 +15 mux_tree_tapbuf_size4_0_sram[1]:5 mux_tree_tapbuf_size4_0_sram[1]:4 0.0009441964 + +*END + +*D_NET mux_tree_tapbuf_size4_2_sram[2] 0.002524689 //LENGTH 17.565 LUMPCC 0.0002847254 DR + +*CONN +*I mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.485 47.600 +*I mem_left_track_13\/FTB_21__53:A I *L 0.001746 *C 32.200 50.320 +*I mux_left_track_13\/mux_l3_in_0_:S I *L 0.00357 *C 27.700 47.600 +*N mux_tree_tapbuf_size4_2_sram[2]:3 *C 27.738 47.600 +*N mux_tree_tapbuf_size4_2_sram[2]:4 *C 29.440 47.600 +*N mux_tree_tapbuf_size4_2_sram[2]:5 *C 29.440 47.260 +*N mux_tree_tapbuf_size4_2_sram[2]:6 *C 30.315 47.260 +*N mux_tree_tapbuf_size4_2_sram[2]:7 *C 30.360 47.305 +*N mux_tree_tapbuf_size4_2_sram[2]:8 *C 30.360 48.223 +*N mux_tree_tapbuf_size4_2_sram[2]:9 *C 30.367 48.280 +*N mux_tree_tapbuf_size4_2_sram[2]:10 *C 32.163 50.320 +*N mux_tree_tapbuf_size4_2_sram[2]:11 *C 31.785 50.320 +*N mux_tree_tapbuf_size4_2_sram[2]:12 *C 31.740 50.275 +*N mux_tree_tapbuf_size4_2_sram[2]:13 *C 31.740 48.338 +*N mux_tree_tapbuf_size4_2_sram[2]:14 *C 31.740 48.280 +*N mux_tree_tapbuf_size4_2_sram[2]:15 *C 38.172 48.280 +*N mux_tree_tapbuf_size4_2_sram[2]:16 *C 38.180 48.223 +*N mux_tree_tapbuf_size4_2_sram[2]:17 *C 38.180 47.645 +*N mux_tree_tapbuf_size4_2_sram[2]:18 *C 38.180 47.600 +*N mux_tree_tapbuf_size4_2_sram[2]:19 *C 38.485 47.600 + +*CAP +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_13\/FTB_21__53:A 1e-06 +2 mux_left_track_13\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size4_2_sram[2]:3 0.0001347144 +4 mux_tree_tapbuf_size4_2_sram[2]:4 0.0001570093 +5 mux_tree_tapbuf_size4_2_sram[2]:5 9.998123e-05 +6 mux_tree_tapbuf_size4_2_sram[2]:6 7.768635e-05 +7 mux_tree_tapbuf_size4_2_sram[2]:7 7.371495e-05 +8 mux_tree_tapbuf_size4_2_sram[2]:8 7.371495e-05 +9 mux_tree_tapbuf_size4_2_sram[2]:9 0.000124556 +10 mux_tree_tapbuf_size4_2_sram[2]:10 5.194702e-05 +11 mux_tree_tapbuf_size4_2_sram[2]:11 5.194702e-05 +12 mux_tree_tapbuf_size4_2_sram[2]:12 0.0001495222 +13 mux_tree_tapbuf_size4_2_sram[2]:13 0.0001495222 +14 mux_tree_tapbuf_size4_2_sram[2]:14 0.0004821875 +15 mux_tree_tapbuf_size4_2_sram[2]:15 0.0003576315 +16 mux_tree_tapbuf_size4_2_sram[2]:16 6.570578e-05 +17 mux_tree_tapbuf_size4_2_sram[2]:17 6.570578e-05 +18 mux_tree_tapbuf_size4_2_sram[2]:18 6.169437e-05 +19 mux_tree_tapbuf_size4_2_sram[2]:19 5.972306e-05 +20 mux_tree_tapbuf_size4_2_sram[2]:15 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001293012 +21 mux_tree_tapbuf_size4_2_sram[2]:9 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.057312e-05 +22 mux_tree_tapbuf_size4_2_sram[2]:14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001293012 +23 mux_tree_tapbuf_size4_2_sram[2]:14 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.057312e-05 +24 mux_tree_tapbuf_size4_2_sram[2]:4 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.488338e-06 +25 mux_tree_tapbuf_size4_2_sram[2]:5 mux_left_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.488338e-06 + +*RES +0 mem_left_track_13\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size4_2_sram[2]:19 0.152 +1 mux_tree_tapbuf_size4_2_sram[2]:16 mux_tree_tapbuf_size4_2_sram[2]:15 0.00341 +2 mux_tree_tapbuf_size4_2_sram[2]:15 mux_tree_tapbuf_size4_2_sram[2]:14 0.001007758 +3 mux_tree_tapbuf_size4_2_sram[2]:18 mux_tree_tapbuf_size4_2_sram[2]:17 0.0045 +4 mux_tree_tapbuf_size4_2_sram[2]:17 mux_tree_tapbuf_size4_2_sram[2]:16 0.000515625 +5 mux_tree_tapbuf_size4_2_sram[2]:19 mux_tree_tapbuf_size4_2_sram[2]:18 0.0001657609 +6 mux_tree_tapbuf_size4_2_sram[2]:8 mux_tree_tapbuf_size4_2_sram[2]:7 0.0008191965 +7 mux_tree_tapbuf_size4_2_sram[2]:9 mux_tree_tapbuf_size4_2_sram[2]:8 0.00341 +8 mux_tree_tapbuf_size4_2_sram[2]:6 mux_tree_tapbuf_size4_2_sram[2]:5 0.00078125 +9 mux_tree_tapbuf_size4_2_sram[2]:7 mux_tree_tapbuf_size4_2_sram[2]:6 0.0045 +10 mux_tree_tapbuf_size4_2_sram[2]:3 mux_left_track_13\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size4_2_sram[2]:13 mux_tree_tapbuf_size4_2_sram[2]:12 0.001729911 +12 mux_tree_tapbuf_size4_2_sram[2]:14 mux_tree_tapbuf_size4_2_sram[2]:13 0.00341 +13 mux_tree_tapbuf_size4_2_sram[2]:14 mux_tree_tapbuf_size4_2_sram[2]:9 0.000215025 +14 mux_tree_tapbuf_size4_2_sram[2]:11 mux_tree_tapbuf_size4_2_sram[2]:10 0.0003370536 +15 mux_tree_tapbuf_size4_2_sram[2]:12 mux_tree_tapbuf_size4_2_sram[2]:11 0.0045 +16 mux_tree_tapbuf_size4_2_sram[2]:10 mem_left_track_13\/FTB_21__53:A 0.152 +17 mux_tree_tapbuf_size4_2_sram[2]:4 mux_tree_tapbuf_size4_2_sram[2]:3 0.001520089 +18 mux_tree_tapbuf_size4_2_sram[2]:5 mux_tree_tapbuf_size4_2_sram[2]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_2_sram[0] 0.01225271 //LENGTH 92.855 LUMPCC 0.001967199 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 83.875 28.900 +*I mux_bottom_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 24.940 30.990 +*I mux_bottom_track_33\/mux_l1_in_2_:S I *L 0.00357 *C 8.620 41.480 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.915 33.660 +*I mux_bottom_track_33\/mux_l1_in_1_:S I *L 0.00357 *C 19.780 34.170 +*N mux_tree_tapbuf_size6_2_sram[0]:5 *C 19.780 34.170 +*N mux_tree_tapbuf_size6_2_sram[0]:6 *C 8.915 33.660 +*N mux_tree_tapbuf_size6_2_sram[0]:7 *C 8.658 41.480 +*N mux_tree_tapbuf_size6_2_sram[0]:8 *C 9.615 41.480 +*N mux_tree_tapbuf_size6_2_sram[0]:9 *C 9.660 41.480 +*N mux_tree_tapbuf_size6_2_sram[0]:10 *C 9.200 41.480 +*N mux_tree_tapbuf_size6_2_sram[0]:11 *C 9.200 33.705 +*N mux_tree_tapbuf_size6_2_sram[0]:12 *C 9.245 33.660 +*N mux_tree_tapbuf_size6_2_sram[0]:13 *C 19.780 33.660 +*N mux_tree_tapbuf_size6_2_sram[0]:14 *C 22.035 33.660 +*N mux_tree_tapbuf_size6_2_sram[0]:15 *C 22.080 33.615 +*N mux_tree_tapbuf_size6_2_sram[0]:16 *C 22.080 31.325 +*N mux_tree_tapbuf_size6_2_sram[0]:17 *C 22.125 31.280 +*N mux_tree_tapbuf_size6_2_sram[0]:18 *C 24.883 31.280 +*N mux_tree_tapbuf_size6_2_sram[0]:19 *C 24.940 30.990 +*N mux_tree_tapbuf_size6_2_sram[0]:20 *C 24.840 30.600 +*N mux_tree_tapbuf_size6_2_sram[0]:21 *C 24.840 30.600 +*N mux_tree_tapbuf_size6_2_sram[0]:22 *C 24.848 30.600 +*N mux_tree_tapbuf_size6_2_sram[0]:23 *C 74.675 30.600 +*N mux_tree_tapbuf_size6_2_sram[0]:24 *C 83.252 30.600 +*N mux_tree_tapbuf_size6_2_sram[0]:25 *C 83.260 30.543 +*N mux_tree_tapbuf_size6_2_sram[0]:26 *C 83.260 28.945 +*N mux_tree_tapbuf_size6_2_sram[0]:27 *C 83.305 28.900 +*N mux_tree_tapbuf_size6_2_sram[0]:28 *C 83.838 28.900 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_33\/mux_l1_in_0_:S 1e-06 +2 mux_bottom_track_33\/mux_l1_in_2_:S 1e-06 +3 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_bottom_track_33\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_2_sram[0]:5 6.361902e-05 +6 mux_tree_tapbuf_size6_2_sram[0]:6 5.352714e-05 +7 mux_tree_tapbuf_size6_2_sram[0]:7 0.0001011131 +8 mux_tree_tapbuf_size6_2_sram[0]:8 0.0001011131 +9 mux_tree_tapbuf_size6_2_sram[0]:9 6.384947e-05 +10 mux_tree_tapbuf_size6_2_sram[0]:10 0.0004492383 +11 mux_tree_tapbuf_size6_2_sram[0]:11 0.0004163876 +12 mux_tree_tapbuf_size6_2_sram[0]:12 0.0007045846 +13 mux_tree_tapbuf_size6_2_sram[0]:13 0.0008627753 +14 mux_tree_tapbuf_size6_2_sram[0]:14 0.0001481429 +15 mux_tree_tapbuf_size6_2_sram[0]:15 0.0001331825 +16 mux_tree_tapbuf_size6_2_sram[0]:16 0.0001331825 +17 mux_tree_tapbuf_size6_2_sram[0]:17 0.0001079833 +18 mux_tree_tapbuf_size6_2_sram[0]:18 0.0001322575 +19 mux_tree_tapbuf_size6_2_sram[0]:19 7.93066e-05 +20 mux_tree_tapbuf_size6_2_sram[0]:20 5.90323e-05 +21 mux_tree_tapbuf_size6_2_sram[0]:21 3.661407e-05 +22 mux_tree_tapbuf_size6_2_sram[0]:22 0.002633489 +23 mux_tree_tapbuf_size6_2_sram[0]:23 0.003142664 +24 mux_tree_tapbuf_size6_2_sram[0]:24 0.0005091752 +25 mux_tree_tapbuf_size6_2_sram[0]:25 0.0001110107 +26 mux_tree_tapbuf_size6_2_sram[0]:26 0.0001110107 +27 mux_tree_tapbuf_size6_2_sram[0]:27 6.362538e-05 +28 mux_tree_tapbuf_size6_2_sram[0]:28 6.362538e-05 +29 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:123 2.193105e-06 +30 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:124 4.068246e-05 +31 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:157 5.641899e-05 +32 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:162 4.435147e-05 +33 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:167 2.893904e-05 +34 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:171 0.0001302801 +35 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:199 3.685465e-05 +36 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:200 4.891494e-05 +37 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:261 6.532016e-05 +38 mux_tree_tapbuf_size6_2_sram[0]:22 prog_clk[0]:266 0.0001610639 +39 mux_tree_tapbuf_size6_2_sram[0]:24 prog_clk[0]:88 2.573212e-05 +40 mux_tree_tapbuf_size6_2_sram[0]:11 prog_clk[0]:265 6.992102e-06 +41 mux_tree_tapbuf_size6_2_sram[0]:10 prog_clk[0]:264 6.992102e-06 +42 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:88 2.193105e-06 +43 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:123 6.641458e-05 +44 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:129 5.641899e-05 +45 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:158 4.435147e-05 +46 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:162 2.893904e-05 +47 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:167 0.0001302801 +48 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:171 3.685465e-05 +49 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:199 4.891494e-05 +50 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:256 6.532016e-05 +51 mux_tree_tapbuf_size6_2_sram[0]:23 prog_clk[0]:261 0.0001610639 +52 mux_tree_tapbuf_size6_2_sram[0]:17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.830617e-05 +53 mux_tree_tapbuf_size6_2_sram[0]:18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.830617e-05 +54 mux_tree_tapbuf_size6_2_sram[0]:17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.731333e-05 +55 mux_tree_tapbuf_size6_2_sram[0]:16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.749848e-05 +56 mux_tree_tapbuf_size6_2_sram[0]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.749848e-05 +57 mux_tree_tapbuf_size6_2_sram[0]:18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.731333e-05 +58 mux_tree_tapbuf_size6_2_sram[0]:22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0001827385 +59 mux_tree_tapbuf_size6_2_sram[0]:23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0001827385 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_2_sram[0]:28 0.152 +1 mux_tree_tapbuf_size6_2_sram[0]:20 mux_tree_tapbuf_size6_2_sram[0]:19 0.0003482143 +2 mux_tree_tapbuf_size6_2_sram[0]:21 mux_tree_tapbuf_size6_2_sram[0]:20 0.0045 +3 mux_tree_tapbuf_size6_2_sram[0]:22 mux_tree_tapbuf_size6_2_sram[0]:21 0.00341 +4 mux_tree_tapbuf_size6_2_sram[0]:25 mux_tree_tapbuf_size6_2_sram[0]:24 0.00341 +5 mux_tree_tapbuf_size6_2_sram[0]:24 mux_tree_tapbuf_size6_2_sram[0]:23 0.001343808 +6 mux_tree_tapbuf_size6_2_sram[0]:27 mux_tree_tapbuf_size6_2_sram[0]:26 0.0045 +7 mux_tree_tapbuf_size6_2_sram[0]:26 mux_tree_tapbuf_size6_2_sram[0]:25 0.001426339 +8 mux_tree_tapbuf_size6_2_sram[0]:28 mux_tree_tapbuf_size6_2_sram[0]:27 0.0004754465 +9 mux_tree_tapbuf_size6_2_sram[0]:17 mux_tree_tapbuf_size6_2_sram[0]:16 0.0045 +10 mux_tree_tapbuf_size6_2_sram[0]:16 mux_tree_tapbuf_size6_2_sram[0]:15 0.002044643 +11 mux_tree_tapbuf_size6_2_sram[0]:14 mux_tree_tapbuf_size6_2_sram[0]:13 0.002013393 +12 mux_tree_tapbuf_size6_2_sram[0]:15 mux_tree_tapbuf_size6_2_sram[0]:14 0.0045 +13 mux_tree_tapbuf_size6_2_sram[0]:6 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +14 mux_tree_tapbuf_size6_2_sram[0]:7 mux_bottom_track_33\/mux_l1_in_2_:S 0.152 +15 mux_tree_tapbuf_size6_2_sram[0]:8 mux_tree_tapbuf_size6_2_sram[0]:7 0.0008549107 +16 mux_tree_tapbuf_size6_2_sram[0]:9 mux_tree_tapbuf_size6_2_sram[0]:8 0.0045 +17 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:11 0.0045 +18 mux_tree_tapbuf_size6_2_sram[0]:12 mux_tree_tapbuf_size6_2_sram[0]:6 0.0001793478 +19 mux_tree_tapbuf_size6_2_sram[0]:11 mux_tree_tapbuf_size6_2_sram[0]:10 0.006941965 +20 mux_tree_tapbuf_size6_2_sram[0]:5 mux_bottom_track_33\/mux_l1_in_1_:S 0.152 +21 mux_tree_tapbuf_size6_2_sram[0]:19 mux_bottom_track_33\/mux_l1_in_0_:S 0.152 +22 mux_tree_tapbuf_size6_2_sram[0]:19 mux_tree_tapbuf_size6_2_sram[0]:18 0.0001686047 +23 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:12 0.009406251 +24 mux_tree_tapbuf_size6_2_sram[0]:13 mux_tree_tapbuf_size6_2_sram[0]:5 0.0004553572 +25 mux_tree_tapbuf_size6_2_sram[0]:18 mux_tree_tapbuf_size6_2_sram[0]:17 0.002462053 +26 mux_tree_tapbuf_size6_2_sram[0]:10 mux_tree_tapbuf_size6_2_sram[0]:9 0.0004107143 +27 mux_tree_tapbuf_size6_2_sram[0]:23 mux_tree_tapbuf_size6_2_sram[0]:22 0.007806308 + +*END + +*D_NET mux_tree_tapbuf_size7_4_sram[2] 0.001308319 //LENGTH 9.475 LUMPCC 0.0001945247 DR + +*CONN +*I mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 11.805 80.240 +*I mem_left_track_3\/FTB_12__44:A I *L 0.001746 *C 11.960 77.520 +*I mux_left_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 8.840 82.960 +*N mux_tree_tapbuf_size7_4_sram[2]:3 *C 8.878 82.960 +*N mux_tree_tapbuf_size7_4_sram[2]:4 *C 11.915 82.960 +*N mux_tree_tapbuf_size7_4_sram[2]:5 *C 11.960 82.915 +*N mux_tree_tapbuf_size7_4_sram[2]:6 *C 11.960 77.520 +*N mux_tree_tapbuf_size7_4_sram[2]:7 *C 11.960 77.565 +*N mux_tree_tapbuf_size7_4_sram[2]:8 *C 11.960 80.240 +*N mux_tree_tapbuf_size7_4_sram[2]:9 *C 11.960 80.240 +*N mux_tree_tapbuf_size7_4_sram[2]:10 *C 11.805 80.240 + +*CAP +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_left_track_3\/FTB_12__44:A 1e-06 +2 mux_left_track_3\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size7_4_sram[2]:3 0.0001713985 +4 mux_tree_tapbuf_size7_4_sram[2]:4 0.0001713985 +5 mux_tree_tapbuf_size7_4_sram[2]:5 0.0001587413 +6 mux_tree_tapbuf_size7_4_sram[2]:6 3.508755e-05 +7 mux_tree_tapbuf_size7_4_sram[2]:7 0.0001331459 +8 mux_tree_tapbuf_size7_4_sram[2]:8 0.0003241003 +9 mux_tree_tapbuf_size7_4_sram[2]:9 6.148467e-05 +10 mux_tree_tapbuf_size7_4_sram[2]:10 5.543758e-05 +11 mux_tree_tapbuf_size7_4_sram[2]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 1.817351e-05 +12 mux_tree_tapbuf_size7_4_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:5 3.945116e-06 +13 mux_tree_tapbuf_size7_4_sram[2]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 1.817351e-05 +14 mux_tree_tapbuf_size7_4_sram[2]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:3 7.514373e-05 +15 mux_tree_tapbuf_size7_4_sram[2]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:4 3.945116e-06 +16 mux_tree_tapbuf_size7_4_sram[2]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_6_X[0]:2 7.514373e-05 + +*RES +0 mem_left_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_4_sram[2]:10 0.152 +1 mux_tree_tapbuf_size7_4_sram[2]:6 mem_left_track_3\/FTB_12__44:A 0.152 +2 mux_tree_tapbuf_size7_4_sram[2]:7 mux_tree_tapbuf_size7_4_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size7_4_sram[2]:9 mux_tree_tapbuf_size7_4_sram[2]:8 0.0045 +4 mux_tree_tapbuf_size7_4_sram[2]:8 mux_tree_tapbuf_size7_4_sram[2]:7 0.002388393 +5 mux_tree_tapbuf_size7_4_sram[2]:8 mux_tree_tapbuf_size7_4_sram[2]:5 0.002388393 +6 mux_tree_tapbuf_size7_4_sram[2]:10 mux_tree_tapbuf_size7_4_sram[2]:9 8.423914e-05 +7 mux_tree_tapbuf_size7_4_sram[2]:4 mux_tree_tapbuf_size7_4_sram[2]:3 0.002712054 +8 mux_tree_tapbuf_size7_4_sram[2]:5 mux_tree_tapbuf_size7_4_sram[2]:4 0.0045 +9 mux_tree_tapbuf_size7_4_sram[2]:3 mux_left_track_3\/mux_l3_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size7_6_sram[2] 0.004188607 //LENGTH 29.960 LUMPCC 0.0005965118 DR + +*CONN +*I mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 59.645 60.860 +*I mux_left_track_7\/mux_l3_in_0_:S I *L 0.00357 *C 42.880 61.880 +*I mem_left_track_7\/FTB_14__46:A I *L 0.001746 *C 66.240 63.920 +*N mux_tree_tapbuf_size7_6_sram[2]:3 *C 66.203 63.920 +*N mux_tree_tapbuf_size7_6_sram[2]:4 *C 65.320 63.920 +*N mux_tree_tapbuf_size7_6_sram[2]:5 *C 65.320 63.580 +*N mux_tree_tapbuf_size7_6_sram[2]:6 *C 59.845 63.580 +*N mux_tree_tapbuf_size7_6_sram[2]:7 *C 59.800 63.580 +*N mux_tree_tapbuf_size7_6_sram[2]:8 *C 42.918 61.880 +*N mux_tree_tapbuf_size7_6_sram[2]:9 *C 49.175 61.880 +*N mux_tree_tapbuf_size7_6_sram[2]:10 *C 49.220 61.925 +*N mux_tree_tapbuf_size7_6_sram[2]:11 *C 49.220 63.183 +*N mux_tree_tapbuf_size7_6_sram[2]:12 *C 49.227 63.240 +*N mux_tree_tapbuf_size7_6_sram[2]:13 *C 59.793 63.240 +*N mux_tree_tapbuf_size7_6_sram[2]:14 *C 59.800 63.183 +*N mux_tree_tapbuf_size7_6_sram[2]:15 *C 59.800 60.905 +*N mux_tree_tapbuf_size7_6_sram[2]:16 *C 59.800 60.860 +*N mux_tree_tapbuf_size7_6_sram[2]:17 *C 59.645 60.860 + +*CAP +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_left_track_7\/mux_l3_in_0_:S 1e-06 +2 mem_left_track_7\/FTB_14__46:A 1e-06 +3 mux_tree_tapbuf_size7_6_sram[2]:3 7.712933e-05 +4 mux_tree_tapbuf_size7_6_sram[2]:4 0.000102893 +5 mux_tree_tapbuf_size7_6_sram[2]:5 0.0004163268 +6 mux_tree_tapbuf_size7_6_sram[2]:6 0.0003905631 +7 mux_tree_tapbuf_size7_6_sram[2]:7 5.767796e-05 +8 mux_tree_tapbuf_size7_6_sram[2]:8 0.0003523072 +9 mux_tree_tapbuf_size7_6_sram[2]:9 0.0003523072 +10 mux_tree_tapbuf_size7_6_sram[2]:10 9.395221e-05 +11 mux_tree_tapbuf_size7_6_sram[2]:11 9.395221e-05 +12 mux_tree_tapbuf_size7_6_sram[2]:12 0.0005960257 +13 mux_tree_tapbuf_size7_6_sram[2]:13 0.0005960257 +14 mux_tree_tapbuf_size7_6_sram[2]:14 0.0001905614 +15 mux_tree_tapbuf_size7_6_sram[2]:15 0.0001650262 +16 mux_tree_tapbuf_size7_6_sram[2]:16 5.293821e-05 +17 mux_tree_tapbuf_size7_6_sram[2]:17 5.140909e-05 +18 mux_tree_tapbuf_size7_6_sram[2]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.36776e-05 +19 mux_tree_tapbuf_size7_6_sram[2]:9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.227049e-05 +20 mux_tree_tapbuf_size7_6_sram[2]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.227049e-05 +21 mux_tree_tapbuf_size7_6_sram[2]:8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.36776e-05 +22 mux_tree_tapbuf_size7_6_sram[2]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:8 9.154326e-05 +23 mux_tree_tapbuf_size7_6_sram[2]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001207646 +24 mux_tree_tapbuf_size7_6_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001207646 +25 mux_tree_tapbuf_size7_6_sram[2]:12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:7 9.154326e-05 + +*RES +0 mem_left_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size7_6_sram[2]:17 0.152 +1 mux_tree_tapbuf_size7_6_sram[2]:14 mux_tree_tapbuf_size7_6_sram[2]:13 0.00341 +2 mux_tree_tapbuf_size7_6_sram[2]:14 mux_tree_tapbuf_size7_6_sram[2]:7 0.0001911058 +3 mux_tree_tapbuf_size7_6_sram[2]:13 mux_tree_tapbuf_size7_6_sram[2]:12 0.001655183 +4 mux_tree_tapbuf_size7_6_sram[2]:11 mux_tree_tapbuf_size7_6_sram[2]:10 0.001122768 +5 mux_tree_tapbuf_size7_6_sram[2]:12 mux_tree_tapbuf_size7_6_sram[2]:11 0.00341 +6 mux_tree_tapbuf_size7_6_sram[2]:9 mux_tree_tapbuf_size7_6_sram[2]:8 0.005587053 +7 mux_tree_tapbuf_size7_6_sram[2]:10 mux_tree_tapbuf_size7_6_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size7_6_sram[2]:8 mux_left_track_7\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size7_6_sram[2]:16 mux_tree_tapbuf_size7_6_sram[2]:15 0.0045 +10 mux_tree_tapbuf_size7_6_sram[2]:15 mux_tree_tapbuf_size7_6_sram[2]:14 0.002033482 +11 mux_tree_tapbuf_size7_6_sram[2]:17 mux_tree_tapbuf_size7_6_sram[2]:16 8.423914e-05 +12 mux_tree_tapbuf_size7_6_sram[2]:6 mux_tree_tapbuf_size7_6_sram[2]:5 0.004888393 +13 mux_tree_tapbuf_size7_6_sram[2]:7 mux_tree_tapbuf_size7_6_sram[2]:6 0.0045 +14 mux_tree_tapbuf_size7_6_sram[2]:3 mem_left_track_7\/FTB_14__46:A 0.152 +15 mux_tree_tapbuf_size7_6_sram[2]:5 mux_tree_tapbuf_size7_6_sram[2]:4 0.0003035715 +16 mux_tree_tapbuf_size7_6_sram[2]:4 mux_tree_tapbuf_size7_6_sram[2]:3 0.0007879465 + +*END + +*D_NET mux_tree_tapbuf_size7_mem_6_ccff_tail[0] 0.001416476 //LENGTH 11.030 LUMPCC 0.0005517279 DR + +*CONN +*I mem_left_track_7\/FTB_14__46:X O *L 0 *C 69.235 63.920 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 67.335 55.420 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 *C 67.335 55.420 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 *C 67.620 55.420 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 *C 67.620 55.465 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 *C 67.620 63.875 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 *C 67.665 63.920 +*N mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 *C 69.198 63.920 + +*CAP +0 mem_left_track_7\/FTB_14__46:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 5.744356e-05 +3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 5.707156e-05 +4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.0002621862 +5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0002621862 +6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 0.0001119301 +7 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 0.0001119301 +8 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 chany_top_in[16]:10 6.128893e-05 +9 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 chany_top_in[16]:9 6.128893e-05 +10 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 chanx_left_in[4]:9 0.0001057253 +11 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 chanx_left_in[4]:5 0.0001057253 +12 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size7_6_sram[0]:11 0.0001088498 +13 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size7_6_sram[0]:10 0.0001088498 + +*RES +0 mem_left_track_7\/FTB_14__46:X mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 0.001368304 +2 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 0.007508929 +4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size7_mem_6_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size8_1_sram[2] 0.004259656 //LENGTH 35.185 LUMPCC 0 DR + +*CONN +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 82.185 91.460 +*I mux_top_track_8\/mux_l3_in_1_:S I *L 0.00357 *C 82.700 89.080 +*I mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D I *L 0.001695 *C 70.095 102.340 +*I mux_top_track_8\/mux_l3_in_0_:S I *L 0.00357 *C 84.540 96.270 +*N mux_tree_tapbuf_size8_1_sram[2]:4 *C 84.540 96.270 +*N mux_tree_tapbuf_size8_1_sram[2]:5 *C 70.095 102.340 +*N mux_tree_tapbuf_size8_1_sram[2]:6 *C 70.380 102.340 +*N mux_tree_tapbuf_size8_1_sram[2]:7 *C 70.380 102.295 +*N mux_tree_tapbuf_size8_1_sram[2]:8 *C 70.380 95.925 +*N mux_tree_tapbuf_size8_1_sram[2]:9 *C 70.425 95.880 +*N mux_tree_tapbuf_size8_1_sram[2]:10 *C 84.540 95.880 +*N mux_tree_tapbuf_size8_1_sram[2]:11 *C 85.975 95.880 +*N mux_tree_tapbuf_size8_1_sram[2]:12 *C 86.020 95.835 +*N mux_tree_tapbuf_size8_1_sram[2]:13 *C 86.020 91.505 +*N mux_tree_tapbuf_size8_1_sram[2]:14 *C 85.975 91.460 +*N mux_tree_tapbuf_size8_1_sram[2]:15 *C 82.700 89.080 +*N mux_tree_tapbuf_size8_1_sram[2]:16 *C 82.800 89.125 +*N mux_tree_tapbuf_size8_1_sram[2]:17 *C 82.800 91.415 +*N mux_tree_tapbuf_size8_1_sram[2]:18 *C 82.800 91.460 +*N mux_tree_tapbuf_size8_1_sram[2]:19 *C 82.223 91.460 + +*CAP +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_top_track_8\/mux_l3_in_1_:S 1e-06 +2 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 1e-06 +3 mux_top_track_8\/mux_l3_in_0_:S 1e-06 +4 mux_tree_tapbuf_size8_1_sram[2]:4 5.907554e-05 +5 mux_tree_tapbuf_size8_1_sram[2]:5 5.419287e-05 +6 mux_tree_tapbuf_size8_1_sram[2]:6 5.48279e-05 +7 mux_tree_tapbuf_size8_1_sram[2]:7 0.0003608821 +8 mux_tree_tapbuf_size8_1_sram[2]:8 0.0003608821 +9 mux_tree_tapbuf_size8_1_sram[2]:9 0.0009128562 +10 mux_tree_tapbuf_size8_1_sram[2]:10 0.001048418 +11 mux_tree_tapbuf_size8_1_sram[2]:11 0.0001051484 +12 mux_tree_tapbuf_size8_1_sram[2]:12 0.0002536866 +13 mux_tree_tapbuf_size8_1_sram[2]:13 0.0002536866 +14 mux_tree_tapbuf_size8_1_sram[2]:14 0.0001865381 +15 mux_tree_tapbuf_size8_1_sram[2]:15 2.699172e-05 +16 mux_tree_tapbuf_size8_1_sram[2]:16 0.0001374179 +17 mux_tree_tapbuf_size8_1_sram[2]:17 0.0001374179 +18 mux_tree_tapbuf_size8_1_sram[2]:18 0.0002612405 +19 mux_tree_tapbuf_size8_1_sram[2]:19 4.239333e-05 + +*RES +0 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size8_1_sram[2]:19 0.152 +1 mux_tree_tapbuf_size8_1_sram[2]:9 mux_tree_tapbuf_size8_1_sram[2]:8 0.0045 +2 mux_tree_tapbuf_size8_1_sram[2]:8 mux_tree_tapbuf_size8_1_sram[2]:7 0.0056875 +3 mux_tree_tapbuf_size8_1_sram[2]:6 mux_tree_tapbuf_size8_1_sram[2]:5 0.0001548913 +4 mux_tree_tapbuf_size8_1_sram[2]:7 mux_tree_tapbuf_size8_1_sram[2]:6 0.0045 +5 mux_tree_tapbuf_size8_1_sram[2]:5 mem_top_track_8\/sky130_fd_sc_hd__dfxbp_1_3_:D 0.152 +6 mux_tree_tapbuf_size8_1_sram[2]:14 mux_tree_tapbuf_size8_1_sram[2]:13 0.0045 +7 mux_tree_tapbuf_size8_1_sram[2]:13 mux_tree_tapbuf_size8_1_sram[2]:12 0.003866072 +8 mux_tree_tapbuf_size8_1_sram[2]:11 mux_tree_tapbuf_size8_1_sram[2]:10 0.00128125 +9 mux_tree_tapbuf_size8_1_sram[2]:12 mux_tree_tapbuf_size8_1_sram[2]:11 0.0045 +10 mux_tree_tapbuf_size8_1_sram[2]:4 mux_top_track_8\/mux_l3_in_0_:S 0.152 +11 mux_tree_tapbuf_size8_1_sram[2]:19 mux_tree_tapbuf_size8_1_sram[2]:18 0.000515625 +12 mux_tree_tapbuf_size8_1_sram[2]:18 mux_tree_tapbuf_size8_1_sram[2]:17 0.0045 +13 mux_tree_tapbuf_size8_1_sram[2]:18 mux_tree_tapbuf_size8_1_sram[2]:14 0.002834822 +14 mux_tree_tapbuf_size8_1_sram[2]:17 mux_tree_tapbuf_size8_1_sram[2]:16 0.002044643 +15 mux_tree_tapbuf_size8_1_sram[2]:15 mux_top_track_8\/mux_l3_in_1_:S 0.152 +16 mux_tree_tapbuf_size8_1_sram[2]:16 mux_tree_tapbuf_size8_1_sram[2]:15 0.0045 +17 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:9 0.01260268 +18 mux_tree_tapbuf_size8_1_sram[2]:10 mux_tree_tapbuf_size8_1_sram[2]:4 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size9_0_sram[3] 0.001585385 //LENGTH 12.775 LUMPCC 9.787575e-05 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q O *L 0 *C 25.145 42.160 +*I mem_bottom_track_3\/FTB_18__50:A I *L 0.001746 *C 28.060 44.880 +*I mux_bottom_track_3\/mux_l4_in_0_:S I *L 0.00357 *C 27.500 39.735 +*N mux_tree_tapbuf_size9_0_sram[3]:3 *C 27.500 39.735 +*N mux_tree_tapbuf_size9_0_sram[3]:4 *C 28.098 44.880 +*N mux_tree_tapbuf_size9_0_sram[3]:5 *C 28.475 44.880 +*N mux_tree_tapbuf_size9_0_sram[3]:6 *C 28.520 44.835 +*N mux_tree_tapbuf_size9_0_sram[3]:7 *C 28.520 40.165 +*N mux_tree_tapbuf_size9_0_sram[3]:8 *C 28.475 40.120 +*N mux_tree_tapbuf_size9_0_sram[3]:9 *C 27.500 40.120 +*N mux_tree_tapbuf_size9_0_sram[3]:10 *C 25.805 40.120 +*N mux_tree_tapbuf_size9_0_sram[3]:11 *C 25.760 40.165 +*N mux_tree_tapbuf_size9_0_sram[3]:12 *C 25.760 42.115 +*N mux_tree_tapbuf_size9_0_sram[3]:13 *C 25.715 42.160 +*N mux_tree_tapbuf_size9_0_sram[3]:14 *C 25.183 42.160 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q 1e-06 +1 mem_bottom_track_3\/FTB_18__50:A 1e-06 +2 mux_bottom_track_3\/mux_l4_in_0_:S 1e-06 +3 mux_tree_tapbuf_size9_0_sram[3]:3 5.638511e-05 +4 mux_tree_tapbuf_size9_0_sram[3]:4 5.117147e-05 +5 mux_tree_tapbuf_size9_0_sram[3]:5 5.117147e-05 +6 mux_tree_tapbuf_size9_0_sram[3]:6 0.0002864353 +7 mux_tree_tapbuf_size9_0_sram[3]:7 0.0002864353 +8 mux_tree_tapbuf_size9_0_sram[3]:8 8.041921e-05 +9 mux_tree_tapbuf_size9_0_sram[3]:9 0.0002047947 +10 mux_tree_tapbuf_size9_0_sram[3]:10 9.536125e-05 +11 mux_tree_tapbuf_size9_0_sram[3]:11 0.0001336971 +12 mux_tree_tapbuf_size9_0_sram[3]:12 0.0001336971 +13 mux_tree_tapbuf_size9_0_sram[3]:13 5.247055e-05 +14 mux_tree_tapbuf_size9_0_sram[3]:14 5.247055e-05 +15 mux_tree_tapbuf_size9_0_sram[3]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:3 4.893787e-05 +16 mux_tree_tapbuf_size9_0_sram[3]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_6_X[0]:2 4.893787e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_3_:Q mux_tree_tapbuf_size9_0_sram[3]:14 0.152 +1 mux_tree_tapbuf_size9_0_sram[3]:10 mux_tree_tapbuf_size9_0_sram[3]:9 0.001513393 +2 mux_tree_tapbuf_size9_0_sram[3]:11 mux_tree_tapbuf_size9_0_sram[3]:10 0.0045 +3 mux_tree_tapbuf_size9_0_sram[3]:13 mux_tree_tapbuf_size9_0_sram[3]:12 0.0045 +4 mux_tree_tapbuf_size9_0_sram[3]:12 mux_tree_tapbuf_size9_0_sram[3]:11 0.001741071 +5 mux_tree_tapbuf_size9_0_sram[3]:14 mux_tree_tapbuf_size9_0_sram[3]:13 0.0004754465 +6 mux_tree_tapbuf_size9_0_sram[3]:3 mux_bottom_track_3\/mux_l4_in_0_:S 0.152 +7 mux_tree_tapbuf_size9_0_sram[3]:8 mux_tree_tapbuf_size9_0_sram[3]:7 0.0045 +8 mux_tree_tapbuf_size9_0_sram[3]:7 mux_tree_tapbuf_size9_0_sram[3]:6 0.004169643 +9 mux_tree_tapbuf_size9_0_sram[3]:5 mux_tree_tapbuf_size9_0_sram[3]:4 0.0003370536 +10 mux_tree_tapbuf_size9_0_sram[3]:6 mux_tree_tapbuf_size9_0_sram[3]:5 0.0045 +11 mux_tree_tapbuf_size9_0_sram[3]:4 mem_bottom_track_3\/FTB_18__50:A 0.152 +12 mux_tree_tapbuf_size9_0_sram[3]:9 mux_tree_tapbuf_size9_0_sram[3]:8 0.0008705358 +13 mux_tree_tapbuf_size9_0_sram[3]:9 mux_tree_tapbuf_size9_0_sram[3]:3 0.00034375 + +*END + +*D_NET mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0] 0.0008087391 //LENGTH 5.240 LUMPCC 0.0004435104 DR + +*CONN +*I mux_top_track_0\/mux_l3_in_0_:X O *L 0 *C 39.275 123.760 +*I mux_top_track_0\/mux_l4_in_0_:A1 I *L 0.00198 *C 37.720 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 *C 37.720 126.820 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 *C 37.720 126.775 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 *C 37.720 123.805 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 *C 37.765 123.760 +*N mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 *C 39.238 123.760 + +*CAP +0 mux_top_track_0\/mux_l3_in_0_:X 1e-06 +1 mux_top_track_0\/mux_l4_in_0_:A1 1e-06 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 2.99545e-05 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 6.208942e-05 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 6.208942e-05 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.0001045476 +6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.0001045476 +7 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 top_left_grid_pin_35_[0]:17 8.619096e-05 +8 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 top_left_grid_pin_35_[0]:18 8.619096e-05 +9 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_tree_tapbuf_size10_0_sram[2]:4 5.848326e-05 +10 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_tree_tapbuf_size10_0_sram[2]:5 5.848326e-05 +11 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_tree_tapbuf_size10_0_sram[3]:7 7.708099e-05 +12 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_tree_tapbuf_size10_0_sram[3]:6 7.708099e-05 + +*RES +0 mux_top_track_0\/mux_l3_in_0_:X mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 0.152 +1 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:6 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 0.001314732 +2 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 0.0045 +3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 0.002651786 +4 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 mux_top_track_0\/mux_l4_in_0_:A1 0.152 +5 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:3 mux_top_track_0/sky130_fd_sc_hd__mux2_1_7_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0008290189 //LENGTH 6.400 LUMPCC 0.0001041887 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_2_:X O *L 0 *C 44.445 33.320 +*I mux_bottom_track_1\/mux_l3_in_1_:A1 I *L 0.00198 *C 47.840 30.940 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 47.840 30.940 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 47.840 30.985 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 47.840 33.275 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 47.795 33.320 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 44.483 33.320 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 3.004375e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001162 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001162 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0002301932 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0002301932 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:5 5.209433e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_6_X[0]:4 5.209433e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.002957589 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.002044643 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_1\/mux_l3_in_1_:A1 0.152 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0045 + +*END + +*D_NET mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0008289331 //LENGTH 5.850 LUMPCC 0.0001383113 DR + +*CONN +*I mux_top_track_2\/mux_l2_in_1_:X O *L 0 *C 30.645 99.960 +*I mux_top_track_2\/mux_l3_in_0_:A0 I *L 0.001631 *C 33.295 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 33.295 102.340 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 33.120 102.000 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 31.785 102.000 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 31.740 101.955 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 31.740 100.005 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 31.695 99.960 +*N mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 30.683 99.960 + +*CAP +0 mux_top_track_2\/mux_l2_in_1_:X 1e-06 +1 mux_top_track_2\/mux_l3_in_0_:A0 1e-06 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.859865e-05 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001463549 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001192322 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 9.258906e-05 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.258906e-05 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 8.962898e-05 +8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 8.962898e-05 +9 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size8_0_sram[1]:26 6.012005e-05 +10 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size8_0_sram[1]:24 9.035621e-06 +11 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size8_0_sram[1]:25 6.012005e-05 +12 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size8_0_sram[1]:23 9.035621e-06 + +*RES +0 mux_top_track_2\/mux_l2_in_1_:X mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.152 +1 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_top_track_2\/mux_l3_in_0_:A0 0.152 +2 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.001191964 +3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0045 +4 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +5 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001741072 +6 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0009040179 +7 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_top_track_2/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001350552 //LENGTH 11.745 LUMPCC 0 DR + +*CONN +*I mux_top_track_8\/mux_l2_in_2_:X O *L 0 *C 73.885 86.020 +*I mux_top_track_8\/mux_l3_in_1_:A1 I *L 0.00198 *C 81.980 88.740 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 81.943 88.740 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 81.005 88.740 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 80.960 88.695 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 80.960 86.065 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 80.915 86.020 +*N mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 73.922 86.020 + +*CAP +0 mux_top_track_8\/mux_l2_in_2_:X 1e-06 +1 mux_top_track_8\/mux_l3_in_1_:A1 1e-06 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001079084 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001079084 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001587505 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001587505 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.000407617 +7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.000407617 + +*RES +0 mux_top_track_8\/mux_l2_in_2_:X mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.006243304 +2 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002348214 +4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0008370537 +5 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +6 mux_top_track_8/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_top_track_8\/mux_l3_in_1_:A1 0.152 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001115595 //LENGTH 8.845 LUMPCC 0.000243577 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_2_:X O *L 0 *C 70.205 39.780 +*I mux_bottom_track_9\/mux_l3_in_1_:A1 I *L 0.00198 *C 78.760 39.780 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 78.723 39.780 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 70.243 39.780 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_2_:X 1e-06 +1 mux_bottom_track_9\/mux_l3_in_1_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.000435009 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000435009 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_tree_tapbuf_size8_2_sram[2]:6 4.774183e-05 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size8_2_sram[2]:7 4.774183e-05 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:2 7.404666e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:3 7.404666e-05 + +*RES +0 mux_bottom_track_9\/mux_l2_in_2_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_9\/mux_l3_in_1_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.007571429 + +*END + +*D_NET mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004499762 //LENGTH 3.400 LUMPCC 6.79939e-05 DR + +*CONN +*I mux_top_track_4\/mux_l1_in_1_:X O *L 0 *C 45.365 113.220 +*I mux_top_track_4\/mux_l2_in_0_:A0 I *L 0.001631 *C 48.475 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 48.438 113.220 +*N mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 45.403 113.220 + +*CAP +0 mux_top_track_4\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_4\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001899912 +3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001899912 +4 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 top_left_grid_pin_37_[0]:7 3.399695e-05 +5 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 top_left_grid_pin_37_[0]:8 3.399695e-05 + +*RES +0 mux_top_track_4\/mux_l1_in_1_:X mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_4\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_4/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002709822 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007895139 //LENGTH 5.985 LUMPCC 0.0001904078 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 42.955 7.140 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 37.260 7.140 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 37.297 7.140 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 42.918 7.140 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002985531 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0002985531 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size14_1_sram[0]:14 5.233216e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size14_1_sram[0]:15 5.233216e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:6 4.287174e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_7_X[0]:7 4.287174e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005017857 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0] 0.001364603 //LENGTH 11.200 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/mux_l4_in_0_:X O *L 0 *C 48.585 11.560 +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 45.875 4.210 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 *C 45.875 4.210 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 *C 46.875 4.080 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 *C 46.920 4.125 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 *C 46.920 11.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 *C 47.380 11.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 *C 47.425 11.560 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 *C 48.547 11.560 + +*CAP +0 mux_bottom_track_5\/mux_l4_in_0_:X 1e-06 +1 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0001083773 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 7.775857e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.0004287238 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0004623582 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 6.547118e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.000109957 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 0.000109957 + +*RES +0 mux_bottom_track_5\/mux_l4_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:2 0.0008928573 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 0.0004107143 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:7 0.001002232 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_13_X[0]:4 0.006638393 + +*END + +*D_NET mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0] 0.00117795 //LENGTH 7.995 LUMPCC 0.0005943229 DR + +*CONN +*I mux_top_track_16\/mux_l1_in_1_:X O *L 0 *C 61.815 96.900 +*I mux_top_track_16\/mux_l2_in_0_:A0 I *L 0.001631 *C 54.110 96.900 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 54.148 96.900 +*N mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 61.778 96.900 + +*CAP +0 mux_top_track_16\/mux_l1_in_1_:X 1e-06 +1 mux_top_track_16\/mux_l2_in_0_:A0 1e-06 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002908136 +3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002908136 +4 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size7_0_sram[0]:29 0.0002971615 +5 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size7_0_sram[0]:30 0.0002971615 + +*RES +0 mux_top_track_16\/mux_l1_in_1_:X mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_top_track_16\/mux_l2_in_0_:A0 0.152 +2 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_top_track_16/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.006812501 + +*END + +*D_NET mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0009303291 //LENGTH 7.025 LUMPCC 0.0001738563 DR + +*CONN +*I mux_top_track_24\/mux_l2_in_0_:X O *L 0 *C 40.765 87.720 +*I mux_top_track_24\/mux_l3_in_0_:A1 I *L 0.00198 *C 43.800 90.780 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 43.763 90.780 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 42.825 90.780 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 42.780 90.735 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 42.780 87.765 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 42.735 87.720 +*N mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 40.803 87.720 + +*CAP +0 mux_top_track_24\/mux_l2_in_0_:X 1e-06 +1 mux_top_track_24\/mux_l3_in_0_:A1 1e-06 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 9.140382e-05 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 9.140382e-05 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001839518 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001839518 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001018808 +7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0001018808 +8 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.692814e-05 +9 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_1_X[0]:2 8.692814e-05 + +*RES +0 mux_top_track_24\/mux_l2_in_0_:X mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_top_track_24\/mux_l3_in_0_:A1 0.152 +2 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0008370535 +3 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.002651786 +6 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_top_track_24/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001725447 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008982128 //LENGTH 7.005 LUMPCC 0.0001587165 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_0_:X O *L 0 *C 45.825 39.780 +*I mux_bottom_track_17\/mux_l3_in_0_:A1 I *L 0.00198 *C 52.540 39.780 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 52.503 39.780 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 45.863 39.780 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0003687482 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0003687482 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:10 6.573521e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:12 1.362303e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:13 1.362303e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_8_X[0]:11 6.573521e-05 + +*RES +0 mux_bottom_track_17\/mux_l2_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_17\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.005928572 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.0008244541 //LENGTH 5.010 LUMPCC 0.0003004776 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 24.095 90.440 +*I mux_left_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 21.525 88.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 21.562 88.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 23.875 88.740 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 23.920 88.785 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 23.920 90.395 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 23.920 90.440 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 24.095 90.440 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001118116 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001118116 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 8.78539e-05 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.78539e-05 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.013028e-05 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.251517e-05 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_3_sram[0]:17 4.629814e-05 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_3_sram[0]:16 4.629814e-05 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_3_sram[0]:18 1.436123e-05 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_3_sram[0]:19 1.436123e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_tree_tapbuf_size7_3_sram[2]:5 7.593838e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size7_3_sram[2]:6 7.593838e-05 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:4 3.370272e-06 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size7_3_sram[2]:7 1.027076e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:7 3.370272e-06 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size7_3_sram[2]:8 1.027076e-05 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_left_track_1\/mux_l3_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.002064732 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0014375 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.0007121074 //LENGTH 5.835 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_1_:X O *L 0 *C 15.815 72.760 +*I mux_left_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 13.630 70.040 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 13.668 70.040 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 14.675 70.040 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 14.720 70.085 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 14.720 72.715 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 14.765 72.760 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 15.778 72.760 + +*CAP +0 mux_left_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_left_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 8.838385e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 8.838385e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0001671256 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0001671256 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 9.954423e-05 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 9.954423e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_1_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_left_track_5\/mux_l3_in_0_:A0 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0008995536 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.002348214 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.002102722 //LENGTH 14.925 LUMPCC 0.0003069761 DR + +*CONN +*I mux_left_track_7\/mux_l1_in_2_:X O *L 0 *C 26.045 64.600 +*I mux_left_track_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 39.100 63.580 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 39.062 63.580 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 34.500 63.580 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 34.500 64.260 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 29.440 64.260 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 29.440 64.600 +*N mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 26.082 64.600 + +*CAP +0 mux_left_track_7\/mux_l1_in_2_:X 1e-06 +1 mux_left_track_7\/mux_l2_in_1_:A1 1e-06 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0002482123 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.000292626 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0003415753 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003233936 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0003070855 +7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0002808534 +8 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.498587e-05 +9 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.498587e-05 +10 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.156458e-06 +11 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.156458e-06 +12 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 9.33457e-05 +13 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.33457e-05 + +*RES +0 mux_left_track_7\/mux_l1_in_2_:X mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_left_track_7\/mux_l2_in_1_:A1 0.152 +2 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.002997768 +3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0003035715 +4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.004517857 +5 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0006071429 +6 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_left_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.004073661 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0] 0.0008446451 //LENGTH 5.935 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 76.185 18.360 +*I mux_bottom_track_25\/mux_l3_in_0_:A1 I *L 0.00198 *C 79.220 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 79.183 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 75.945 20.060 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 75.900 20.015 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 75.900 18.405 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 75.900 18.360 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 76.185 18.360 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0002575158 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002575158 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001093355 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001093355 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.657826e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 5.236425e-05 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_25\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.002890625 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0014375 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006184142 //LENGTH 5.300 LUMPCC 0.0001981268 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_0_:X O *L 0 *C 30.075 33.660 +*I mux_bottom_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 28.425 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 28.463 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.935 36.380 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 28.980 36.335 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.980 33.705 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 29.025 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 30.038 33.660 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.892802e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.892802e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001067299 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001067299 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.348579e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.348579e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_38_[0]:10 2.452882e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_38_[0]:13 9.156978e-06 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_left_grid_pin_38_[0]:11 2.063589e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_38_[0]:13 2.452882e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_38_[0]:14 9.156978e-06 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 bottom_left_grid_pin_38_[0]:12 2.063589e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.214622e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.214622e-05 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.259552e-05 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.259552e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00172091 //LENGTH 16.030 LUMPCC 0.0002772111 DR + +*CONN +*I mux_left_track_11\/mux_l1_in_0_:X O *L 0 *C 87.115 55.080 +*I mux_left_track_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 87.765 47.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 87.803 47.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 91.035 47.260 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 91.080 47.305 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 91.080 55.035 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 91.035 55.080 +*N mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 87.153 55.080 + +*CAP +0 mux_left_track_11\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_11\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000203039 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000203039 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002554668 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002554668 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0002623437 +7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0002623437 +8 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_top_in[9]:7 0.0001227249 +9 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[9]:9 1.117826e-05 +10 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_top_in[9]:11 4.702372e-06 +11 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_top_in[9]:8 0.0001227249 +12 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[9]:10 4.702372e-06 +13 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_top_in[9]:11 1.117826e-05 + +*RES +0 mux_left_track_11\/mux_l1_in_0_:X mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_11\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002886161 +3 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.003466518 + +*END + +*D_NET optlc_net_140 0.004729831 //LENGTH 38.570 LUMPCC 0.0006355454 DR + +*CONN +*I optlc_138:HI O *L 0 *C 74.520 44.200 +*I mux_bottom_track_25\/mux_l2_in_1_:A0 I *L 0.001631 *C 71.015 20.740 +*I mux_bottom_track_9\/mux_l2_in_3_:A0 I *L 0.001631 *C 68.715 44.200 +*I mux_left_track_11\/mux_l2_in_1_:A0 I *L 0.001631 *C 79.755 44.200 +*N optlc_net_140:4 *C 79.718 44.200 +*N optlc_net_140:5 *C 68.752 44.200 +*N optlc_net_140:6 *C 71.053 20.740 +*N optlc_net_140:7 *C 73.555 20.740 +*N optlc_net_140:8 *C 73.600 20.785 +*N optlc_net_140:9 *C 73.600 44.200 +*N optlc_net_140:10 *C 74.060 44.200 +*N optlc_net_140:11 *C 74.060 44.200 +*N optlc_net_140:12 *C 74.520 44.200 + +*CAP +0 optlc_138:HI 1e-06 +1 mux_bottom_track_25\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_9\/mux_l2_in_3_:A0 1e-06 +3 mux_left_track_11\/mux_l2_in_1_:A0 1e-06 +4 optlc_net_140:4 0.000348095 +5 optlc_net_140:5 0.0003178205 +6 optlc_net_140:6 0.0002242235 +7 optlc_net_140:7 0.0002242235 +8 optlc_net_140:8 0.001051077 +9 optlc_net_140:9 0.001083405 +10 optlc_net_140:10 6.276792e-05 +11 optlc_net_140:11 0.0003679912 +12 optlc_net_140:12 0.0004106819 +13 optlc_net_140:8 prog_clk[0]:118 1.924848e-05 +14 optlc_net_140:8 prog_clk[0]:121 0.0001124951 +15 optlc_net_140:8 prog_clk[0]:122 5.727711e-05 +16 optlc_net_140:8 prog_clk[0]:127 1.04079e-05 +17 optlc_net_140:8 prog_clk[0]:129 1.089097e-05 +18 optlc_net_140:9 prog_clk[0]:114 1.924848e-05 +19 optlc_net_140:9 prog_clk[0]:118 0.0001124951 +20 optlc_net_140:9 prog_clk[0]:121 5.727711e-05 +21 optlc_net_140:9 prog_clk[0]:124 1.089097e-05 +22 optlc_net_140:9 prog_clk[0]:128 1.04079e-05 +23 optlc_net_140:11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:6 3.857079e-05 +24 optlc_net_140:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.888236e-05 +25 optlc_net_140:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:7 3.857079e-05 +26 optlc_net_140:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.888236e-05 + +*RES +0 optlc_138:HI optlc_net_140:12 0.152 +1 optlc_net_140:11 optlc_net_140:10 0.0045 +2 optlc_net_140:11 optlc_net_140:5 0.004738839 +3 optlc_net_140:10 optlc_net_140:9 0.0004107143 +4 optlc_net_140:7 optlc_net_140:6 0.002234375 +5 optlc_net_140:8 optlc_net_140:7 0.0045 +6 optlc_net_140:6 mux_bottom_track_25\/mux_l2_in_1_:A0 0.152 +7 optlc_net_140:12 optlc_net_140:11 0.0004107143 +8 optlc_net_140:12 optlc_net_140:4 0.004640625 +9 optlc_net_140:5 mux_bottom_track_9\/mux_l2_in_3_:A0 0.152 +10 optlc_net_140:4 mux_left_track_11\/mux_l2_in_1_:A0 0.152 +11 optlc_net_140:9 optlc_net_140:8 0.02090625 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0004197305 //LENGTH 2.935 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_1_:X O *L 0 *C 49.395 66.300 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 46.750 66.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 46.788 66.300 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 49.358 66.300 + +*CAP +0 mux_left_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0002088652 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0002088652 + +*RES +0 mux_left_track_25\/mux_l1_in_1_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002294643 + +*END + +*D_NET ropt_net_173 0.002663693 //LENGTH 19.530 LUMPCC 0 DR + +*CONN +*I FTB_5__4:X O *L 0 *C 72.220 9.180 +*I ropt_mt_inst_799:A I *L 0.001766 *C 84.180 4.080 +*N ropt_net_173:2 *C 84.180 4.080 +*N ropt_net_173:3 *C 84.180 4.420 +*N ropt_net_173:4 *C 84.180 4.465 +*N ropt_net_173:5 *C 84.180 6.415 +*N ropt_net_173:6 *C 84.135 6.460 +*N ropt_net_173:7 *C 82.800 6.460 +*N ropt_net_173:8 *C 82.800 6.120 +*N ropt_net_173:9 *C 74.105 6.120 +*N ropt_net_173:10 *C 74.060 6.165 +*N ropt_net_173:11 *C 74.060 9.135 +*N ropt_net_173:12 *C 74.015 9.180 +*N ropt_net_173:13 *C 72.258 9.180 + +*CAP +0 FTB_5__4:X 1e-06 +1 ropt_mt_inst_799:A 1e-06 +2 ropt_net_173:2 7.093932e-05 +3 ropt_net_173:3 7.578147e-05 +4 ropt_net_173:4 0.0001410464 +5 ropt_net_173:5 0.0001410464 +6 ropt_net_173:6 0.0001098763 +7 ropt_net_173:7 0.0001355807 +8 ropt_net_173:8 0.0006437118 +9 ropt_net_173:9 0.0006180073 +10 ropt_net_173:10 0.0002081979 +11 ropt_net_173:11 0.0002081979 +12 ropt_net_173:12 0.0001546538 +13 ropt_net_173:13 0.0001546538 + +*RES +0 FTB_5__4:X ropt_net_173:13 0.152 +1 ropt_net_173:2 ropt_mt_inst_799:A 0.152 +2 ropt_net_173:3 ropt_net_173:2 0.0001465517 +3 ropt_net_173:4 ropt_net_173:3 0.0045 +4 ropt_net_173:6 ropt_net_173:5 0.0045 +5 ropt_net_173:5 ropt_net_173:4 0.001741072 +6 ropt_net_173:9 ropt_net_173:8 0.007763393 +7 ropt_net_173:10 ropt_net_173:9 0.0045 +8 ropt_net_173:12 ropt_net_173:11 0.0045 +9 ropt_net_173:11 ropt_net_173:10 0.002651786 +10 ropt_net_173:13 ropt_net_173:12 0.001569197 +11 ropt_net_173:8 ropt_net_173:7 0.0003035715 +12 ropt_net_173:7 ropt_net_173:6 0.001191964 + +*END + +*D_NET ropt_net_208 0.0004074586 //LENGTH 3.585 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_776:X O *L 0 *C 99.360 6.120 +*I ropt_mt_inst_846:A I *L 0.001766 *C 98.440 4.080 +*N ropt_net_208:2 *C 98.478 4.080 +*N ropt_net_208:3 *C 99.315 4.080 +*N ropt_net_208:4 *C 99.360 4.125 +*N ropt_net_208:5 *C 99.360 6.075 +*N ropt_net_208:6 *C 99.360 6.120 + +*CAP +0 ropt_mt_inst_776:X 1e-06 +1 ropt_mt_inst_846:A 1e-06 +2 ropt_net_208:2 7.080167e-05 +3 ropt_net_208:3 7.080167e-05 +4 ropt_net_208:4 0.0001165523 +5 ropt_net_208:5 0.0001165523 +6 ropt_net_208:6 3.075064e-05 + +*RES +0 ropt_mt_inst_776:X ropt_net_208:6 0.152 +1 ropt_net_208:2 ropt_mt_inst_846:A 0.152 +2 ropt_net_208:3 ropt_net_208:2 0.0007477679 +3 ropt_net_208:4 ropt_net_208:3 0.0045 +4 ropt_net_208:6 ropt_net_208:5 0.0045 +5 ropt_net_208:5 ropt_net_208:4 0.001741071 + +*END + +*D_NET ropt_net_180 0.003086182 //LENGTH 21.375 LUMPCC 0.0007859801 DR + +*CONN +*I ropt_mt_inst_779:X O *L 0 *C 84.835 8.840 +*I ropt_mt_inst_807:A I *L 0.001766 *C 70.380 4.080 +*N ropt_net_180:2 *C 70.418 4.080 +*N ropt_net_180:3 *C 70.840 4.080 +*N ropt_net_180:4 *C 70.840 4.420 +*N ropt_net_180:5 *C 74.015 4.420 +*N ropt_net_180:6 *C 74.060 4.420 +*N ropt_net_180:7 *C 74.060 5.383 +*N ropt_net_180:8 *C 74.068 5.440 +*N ropt_net_180:9 *C 82.333 5.440 +*N ropt_net_180:10 *C 82.340 5.498 +*N ropt_net_180:11 *C 82.340 8.795 +*N ropt_net_180:12 *C 82.385 8.840 +*N ropt_net_180:13 *C 84.797 8.840 + +*CAP +0 ropt_mt_inst_779:X 1e-06 +1 ropt_mt_inst_807:A 1e-06 +2 ropt_net_180:2 3.015776e-05 +3 ropt_net_180:3 5.616802e-05 +4 ropt_net_180:4 0.00019842 +5 ropt_net_180:5 0.0001724097 +6 ropt_net_180:6 0.0001310709 +7 ropt_net_180:7 0.0001004396 +8 ropt_net_180:8 0.0003867005 +9 ropt_net_180:9 0.0003867005 +10 ropt_net_180:10 0.000211318 +11 ropt_net_180:11 0.000211318 +12 ropt_net_180:12 0.0002067496 +13 ropt_net_180:13 0.0002067496 +14 ropt_net_180:8 chany_bottom_in[8]:26 0.000148008 +15 ropt_net_180:9 chany_bottom_in[8]:27 0.000148008 +16 ropt_net_180:2 bottom_right_grid_pin_1_[0]:22 8.760282e-06 +17 ropt_net_180:5 bottom_right_grid_pin_1_[0]:23 0.0001241871 +18 ropt_net_180:3 bottom_right_grid_pin_1_[0]:23 8.760282e-06 +19 ropt_net_180:4 bottom_right_grid_pin_1_[0]:22 0.0001241871 +20 ropt_net_180:8 chany_bottom_out[18]:7 4.423884e-05 +21 ropt_net_180:8 chany_bottom_out[18]:3 6.750881e-05 +22 ropt_net_180:10 chany_bottom_out[18]:9 2.870491e-07 +23 ropt_net_180:9 chany_bottom_out[18]:8 4.423884e-05 +24 ropt_net_180:9 chany_bottom_out[18]:4 6.750881e-05 +25 ropt_net_180:11 chany_bottom_out[18]:10 2.870491e-07 + +*RES +0 ropt_mt_inst_779:X ropt_net_180:13 0.152 +1 ropt_net_180:2 ropt_mt_inst_807:A 0.152 +2 ropt_net_180:5 ropt_net_180:4 0.002834822 +3 ropt_net_180:6 ropt_net_180:5 0.0045 +4 ropt_net_180:7 ropt_net_180:6 0.000859375 +5 ropt_net_180:8 ropt_net_180:7 0.00341 +6 ropt_net_180:10 ropt_net_180:9 0.00341 +7 ropt_net_180:9 ropt_net_180:8 0.00129485 +8 ropt_net_180:12 ropt_net_180:11 0.0045 +9 ropt_net_180:11 ropt_net_180:10 0.002944197 +10 ropt_net_180:13 ropt_net_180:12 0.002154018 +11 ropt_net_180:3 ropt_net_180:2 0.0003772322 +12 ropt_net_180:4 ropt_net_180:3 0.0003035715 + +*END + +*D_NET ropt_net_181 0.002220723 //LENGTH 15.045 LUMPCC 0.0004723988 DR + +*CONN +*I ropt_mt_inst_790:X O *L 0 *C 63.215 12.240 +*I ropt_mt_inst_808:A I *L 0.001766 *C 57.960 4.080 +*N ropt_net_181:2 *C 57.998 4.080 +*N ropt_net_181:3 *C 58.835 4.080 +*N ropt_net_181:4 *C 58.880 4.125 +*N ropt_net_181:5 *C 58.880 8.103 +*N ropt_net_181:6 *C 58.888 8.160 +*N ropt_net_181:7 *C 61.633 8.160 +*N ropt_net_181:8 *C 61.640 8.218 +*N ropt_net_181:9 *C 61.640 12.195 +*N ropt_net_181:10 *C 61.685 12.240 +*N ropt_net_181:11 *C 63.178 12.240 + +*CAP +0 ropt_mt_inst_790:X 1e-06 +1 ropt_mt_inst_808:A 1e-06 +2 ropt_net_181:2 9.96103e-05 +3 ropt_net_181:3 9.96103e-05 +4 ropt_net_181:4 0.0002756926 +5 ropt_net_181:5 0.0002756926 +6 ropt_net_181:6 0.0001682702 +7 ropt_net_181:7 0.0001682702 +8 ropt_net_181:8 0.0002644829 +9 ropt_net_181:9 0.0002644829 +10 ropt_net_181:10 6.510608e-05 +11 ropt_net_181:11 6.510608e-05 +12 ropt_net_181:6 chany_bottom_in[13]:34 0.0001681487 +13 ropt_net_181:7 chany_bottom_in[13]:35 0.0001681487 +14 ropt_net_181:10 ropt_net_165:4 6.805074e-05 +15 ropt_net_181:11 ropt_net_165:5 6.805074e-05 + +*RES +0 ropt_mt_inst_790:X ropt_net_181:11 0.152 +1 ropt_net_181:2 ropt_mt_inst_808:A 0.152 +2 ropt_net_181:3 ropt_net_181:2 0.0007477679 +3 ropt_net_181:4 ropt_net_181:3 0.0045 +4 ropt_net_181:5 ropt_net_181:4 0.003551339 +5 ropt_net_181:6 ropt_net_181:5 0.00341 +6 ropt_net_181:8 ropt_net_181:7 0.00341 +7 ropt_net_181:7 ropt_net_181:6 0.00043005 +8 ropt_net_181:10 ropt_net_181:9 0.0045 +9 ropt_net_181:9 ropt_net_181:8 0.003551339 +10 ropt_net_181:11 ropt_net_181:10 0.001332589 + +*END + +*D_NET ropt_net_186 0.00188457 //LENGTH 14.200 LUMPCC 0.0003320627 DR + +*CONN +*I ropt_mt_inst_798:X O *L 0 *C 63.675 120.700 +*I ropt_mt_inst_815:A I *L 0.001766 *C 56.580 126.480 +*N ropt_net_186:2 *C 56.580 126.480 +*N ropt_net_186:3 *C 56.580 126.435 +*N ropt_net_186:4 *C 56.580 125.858 +*N ropt_net_186:5 *C 56.588 125.800 +*N ropt_net_186:6 *C 61.172 125.800 +*N ropt_net_186:7 *C 61.180 125.743 +*N ropt_net_186:8 *C 61.180 120.745 +*N ropt_net_186:9 *C 61.225 120.700 +*N ropt_net_186:10 *C 63.638 120.700 + +*CAP +0 ropt_mt_inst_798:X 1e-06 +1 ropt_mt_inst_815:A 1e-06 +2 ropt_net_186:2 3.42708e-05 +3 ropt_net_186:3 5.242281e-05 +4 ropt_net_186:4 5.242281e-05 +5 ropt_net_186:5 0.0002734449 +6 ropt_net_186:6 0.0002734449 +7 ropt_net_186:7 0.0002410601 +8 ropt_net_186:8 0.0002410601 +9 ropt_net_186:9 0.0001911906 +10 ropt_net_186:10 0.0001911906 +11 ropt_net_186:5 chany_top_in[5]:27 7.334584e-05 +12 ropt_net_186:7 chany_top_in[5] 2.001936e-05 +13 ropt_net_186:6 chany_top_in[5]:28 7.334584e-05 +14 ropt_net_186:8 chany_top_in[5]:29 2.001936e-05 +15 ropt_net_186:7 ropt_net_183:4 7.266614e-05 +16 ropt_net_186:8 ropt_net_183:5 7.266614e-05 + +*RES +0 ropt_mt_inst_798:X ropt_net_186:10 0.152 +1 ropt_net_186:2 ropt_mt_inst_815:A 0.152 +2 ropt_net_186:3 ropt_net_186:2 0.0045 +3 ropt_net_186:4 ropt_net_186:3 0.000515625 +4 ropt_net_186:5 ropt_net_186:4 0.00341 +5 ropt_net_186:7 ropt_net_186:6 0.00341 +6 ropt_net_186:6 ropt_net_186:5 0.0007183166 +7 ropt_net_186:9 ropt_net_186:8 0.0045 +8 ropt_net_186:8 ropt_net_186:7 0.004462054 +9 ropt_net_186:10 ropt_net_186:9 0.002154018 + +*END + +*D_NET chany_bottom_out[15] 0.0007059777 //LENGTH 4.960 LUMPCC 0.0001242308 DR + +*CONN +*I ropt_mt_inst_828:X O *L 0 *C 57.245 3.740 +*P chany_bottom_out[15] O *L 0.7423 *C 55.200 1.290 +*N chany_bottom_out[15]:2 *C 55.200 3.695 +*N chany_bottom_out[15]:3 *C 55.245 3.740 +*N chany_bottom_out[15]:4 *C 57.208 3.740 + +*CAP +0 ropt_mt_inst_828:X 1e-06 +1 chany_bottom_out[15] 0.0001576705 +2 chany_bottom_out[15]:2 0.0001576705 +3 chany_bottom_out[15]:3 0.0001327029 +4 chany_bottom_out[15]:4 0.0001327029 +5 chany_bottom_out[15]:4 ropt_net_196:3 6.21154e-05 +6 chany_bottom_out[15]:3 ropt_net_196:2 6.21154e-05 + +*RES +0 ropt_mt_inst_828:X chany_bottom_out[15]:4 0.152 +1 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.001752232 +2 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.0045 +3 chany_bottom_out[15]:2 chany_bottom_out[15] 0.002147322 + +*END + +*D_NET chany_top_out[7] 0.001411711 //LENGTH 10.660 LUMPCC 0.0002611183 DR + +*CONN +*I ropt_mt_inst_844:X O *L 0 *C 53.960 123.420 +*P chany_top_out[7] O *L 0.7423 *C 50.140 129.235 +*N chany_top_out[7]:2 *C 50.140 126.820 +*N chany_top_out[7]:3 *C 50.600 126.820 +*N chany_top_out[7]:4 *C 50.600 126.480 +*N chany_top_out[7]:5 *C 51.060 126.480 +*N chany_top_out[7]:6 *C 51.060 123.465 +*N chany_top_out[7]:7 *C 51.105 123.420 +*N chany_top_out[7]:8 *C 53.922 123.420 + +*CAP +0 ropt_mt_inst_844:X 1e-06 +1 chany_top_out[7] 0.0001598534 +2 chany_top_out[7]:2 0.0001908571 +3 chany_top_out[7]:3 6.093144e-05 +4 chany_top_out[7]:4 4.699184e-05 +5 chany_top_out[7]:5 0.000115367 +6 chany_top_out[7]:6 9.830289e-05 +7 chany_top_out[7]:7 0.0002386447 +8 chany_top_out[7]:8 0.0002386447 +9 chany_top_out[7]:6 ropt_net_177:4 6.69349e-05 +10 chany_top_out[7]:4 ropt_net_177:7 8.872472e-06 +11 chany_top_out[7]:5 ropt_net_177:5 6.69349e-05 +12 chany_top_out[7]:5 ropt_net_177:6 8.872472e-06 +13 chany_top_out[7]:7 ropt_net_194:6 7.919991e-07 +14 chany_top_out[7]:6 ropt_net_194:5 5.388847e-05 +15 chany_top_out[7]:6 ropt_net_194:9 7.130657e-08 +16 chany_top_out[7]:8 ropt_net_194:7 7.919991e-07 +17 chany_top_out[7]:5 ropt_net_194:4 5.388847e-05 +18 chany_top_out[7]:5 ropt_net_194:8 7.130657e-08 + +*RES +0 ropt_mt_inst_844:X chany_top_out[7]:8 0.152 +1 chany_top_out[7]:7 chany_top_out[7]:6 0.0045 +2 chany_top_out[7]:6 chany_top_out[7]:5 0.002691964 +3 chany_top_out[7]:8 chany_top_out[7]:7 0.002515625 +4 chany_top_out[7]:2 chany_top_out[7] 0.00215625 +5 chany_top_out[7]:3 chany_top_out[7]:2 0.0004107143 +6 chany_top_out[7]:4 chany_top_out[7]:3 0.0003035715 +7 chany_top_out[7]:5 chany_top_out[7]:4 0.0004107143 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..56fda5b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef @@ -0,0 +1,15020 @@ +*SPEF "1481-1998" +*DESIGN "sb_2__2_" +*DATE "Mon Oct 26 23:03:32 2020" +* +* +* +* +*DIVIDER / +*DELIMITER : +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 KOHM +*L_UNIT 1 HENRY + +// XY_UNIT 1 UM +// PARASITIC_TECH nominal at 25.000 degree + +*PORTS +prog_clk[0] I *C 30.820 0.680 +chany_bottom_in[0] I *C 82.340 0.680 +chany_bottom_in[1] I *C 67.160 0.680 +chany_bottom_in[2] I *C 81.420 0.680 +chany_bottom_in[3] I *C 88.320 0.680 +chany_bottom_in[4] I *C 65.320 0.680 +chany_bottom_in[5] I *C 75.900 0.680 +chany_bottom_in[6] I *C 94.300 0.680 +chany_bottom_in[7] I *C 87.400 0.680 +chany_bottom_in[8] I *C 77.740 0.680 +chany_bottom_in[9] I *C 84.180 0.680 +chany_bottom_in[10] I *C 62.560 0.680 +chany_bottom_in[11] I *C 86.480 0.680 +chany_bottom_in[12] I *C 79.580 0.680 +chany_bottom_in[13] I *C 68.080 0.680 +chany_bottom_in[14] I *C 66.240 0.680 +chany_bottom_in[15] I *C 53.360 0.680 +chany_bottom_in[16] I *C 76.820 0.680 +chany_bottom_in[17] I *C 69.920 0.680 +chany_bottom_in[18] I *C 57.500 0.680 +chany_bottom_in[19] I *C 78.660 0.680 +bottom_right_grid_pin_1_[0] I *C 110.860 0.680 +bottom_left_grid_pin_34_[0] I *C 29.210 10.200 +bottom_left_grid_pin_35_[0] I *C 29.210 8.160 +bottom_left_grid_pin_36_[0] I *C 29.210 6.800 +bottom_left_grid_pin_37_[0] I *C 29.210 3.400 +bottom_left_grid_pin_38_[0] I *C 29.210 4.760 +bottom_left_grid_pin_39_[0] I *C 29.210 11.560 +bottom_left_grid_pin_40_[0] I *C 29.210 12.920 +bottom_left_grid_pin_41_[0] I *C 29.210 14.280 +chanx_left_in[0] I *C 0.690 39.440 +chanx_left_in[1] I *C 0.690 42.160 +chanx_left_in[2] I *C 0.690 68.000 +chanx_left_in[3] I *C 0.690 61.200 +chanx_left_in[4] I *C 0.690 50.320 +chanx_left_in[5] I *C 0.690 46.240 +chanx_left_in[6] I *C 0.690 31.280 +chanx_left_in[7] I *C 0.690 72.080 +chanx_left_in[8] I *C 0.690 76.160 +chanx_left_in[9] I *C 0.690 99.280 +chanx_left_in[10] I *C 0.690 36.720 +chanx_left_in[11] I *C 0.690 63.920 +chanx_left_in[12] I *C 0.690 32.640 +chanx_left_in[13] I *C 0.690 74.800 +chanx_left_in[14] I *C 0.690 59.840 +chanx_left_in[15] I *C 0.690 96.560 +chanx_left_in[16] I *C 0.690 55.760 +chanx_left_in[17] I *C 0.690 53.040 +chanx_left_in[18] I *C 0.690 38.080 +chanx_left_in[19] I *C 0.690 81.600 +left_top_grid_pin_1_[0] I *C 2.300 102.680 +ccff_head[0] I *C 18.860 102.680 +chany_bottom_out[0] O *C 83.260 0.680 +chany_bottom_out[1] O *C 59.800 0.680 +chany_bottom_out[2] O *C 52.440 0.680 +chany_bottom_out[3] O *C 69.000 0.680 +chany_bottom_out[4] O *C 96.600 0.680 +chany_bottom_out[5] O *C 71.760 0.680 +chany_bottom_out[6] O *C 74.980 0.680 +chany_bottom_out[7] O *C 60.720 0.680 +chany_bottom_out[8] O *C 63.480 0.680 +chany_bottom_out[9] O *C 54.280 0.680 +chany_bottom_out[10] O *C 93.380 0.680 +chany_bottom_out[11] O *C 74.060 0.680 +chany_bottom_out[12] O *C 80.500 0.680 +chany_bottom_out[13] O *C 61.640 0.680 +chany_bottom_out[14] O *C 97.520 0.680 +chany_bottom_out[15] O *C 55.200 0.680 +chany_bottom_out[16] O *C 64.400 0.680 +chany_bottom_out[17] O *C 58.880 0.680 +chany_bottom_out[18] O *C 73.140 0.680 +chany_bottom_out[19] O *C 70.840 0.680 +chanx_left_out[0] O *C 0.690 80.240 +chanx_left_out[1] O *C 0.690 93.840 +chanx_left_out[2] O *C 0.690 34.000 +chanx_left_out[3] O *C 0.690 48.960 +chanx_left_out[4] O *C 0.690 58.480 +chanx_left_out[5] O *C 0.690 70.720 +chanx_left_out[6] O *C 0.690 43.520 +chanx_left_out[7] O *C 0.690 47.600 +chanx_left_out[8] O *C 0.690 85.680 +chanx_left_out[9] O *C 0.690 65.280 +chanx_left_out[10] O *C 0.690 97.920 +chanx_left_out[11] O *C 0.690 92.480 +chanx_left_out[12] O *C 0.690 82.960 +chanx_left_out[13] O *C 0.690 87.040 +chanx_left_out[14] O *C 0.690 69.360 +chanx_left_out[15] O *C 0.690 44.880 +chanx_left_out[16] O *C 0.690 54.400 +chanx_left_out[17] O *C 0.690 91.120 +chanx_left_out[18] O *C 0.690 66.640 +chanx_left_out[19] O *C 0.690 88.400 +ccff_tail[0] O *C 0.690 77.520 +VDD I *C 56.580 51.680 +VSS I *C 56.580 51.680 + +*D_NET chany_bottom_in[0] 0.01646179 //LENGTH 155.920 LUMPCC 0.002226518 DR + +*CONN +*P chany_bottom_in[0] I *L 0.29796 *C 82.340 1.290 +*I BUFT_P_85:A I *L 0.001776 *C 18.400 91.120 +*N chany_bottom_in[0]:2 *C 18.438 91.120 +*N chany_bottom_in[0]:3 *C 25.715 91.120 +*N chany_bottom_in[0]:4 *C 25.760 91.075 +*N chany_bottom_in[0]:5 *C 25.760 83.005 +*N chany_bottom_in[0]:6 *C 25.805 82.960 +*N chany_bottom_in[0]:7 *C 28.060 82.960 +*N chany_bottom_in[0]:8 *C 28.095 82.620 +*N chany_bottom_in[0]:9 *C 79.995 82.620 +*N chany_bottom_in[0]:10 *C 80.040 82.575 +*N chany_bottom_in[0]:11 *C 80.040 30.658 +*N chany_bottom_in[0]:12 *C 80.047 30.600 +*N chany_bottom_in[0]:13 *C 82.333 30.600 +*N chany_bottom_in[0]:14 *C 82.340 30.543 + +*CAP +0 chany_bottom_in[0] 0.001484762 +1 BUFT_P_85:A 1e-06 +2 chany_bottom_in[0]:2 0.0003794302 +3 chany_bottom_in[0]:3 0.0003794302 +4 chany_bottom_in[0]:4 0.0003426599 +5 chany_bottom_in[0]:5 0.0003426599 +6 chany_bottom_in[0]:6 0.0001393757 +7 chany_bottom_in[0]:7 0.0001685122 +8 chany_bottom_in[0]:8 0.002204178 +9 chany_bottom_in[0]:9 0.002175042 +10 chany_bottom_in[0]:10 0.002401354 +11 chany_bottom_in[0]:11 0.002401354 +12 chany_bottom_in[0]:12 0.000165374 +13 chany_bottom_in[0]:13 0.000165374 +14 chany_bottom_in[0]:14 0.001484762 +15 chany_bottom_in[0]:4 chany_bottom_in[10]:5 3.89766e-05 +16 chany_bottom_in[0]:6 chany_bottom_in[10]:9 3.254965e-05 +17 chany_bottom_in[0]:5 chany_bottom_in[10]:6 3.89766e-05 +18 chany_bottom_in[0]:9 chany_bottom_in[10]:12 0.0006577841 +19 chany_bottom_in[0]:9 chany_bottom_in[10]:10 1.730588e-06 +20 chany_bottom_in[0]:7 chany_bottom_in[10]:10 3.254965e-05 +21 chany_bottom_in[0]:8 chany_bottom_in[10]:9 1.730588e-06 +22 chany_bottom_in[0]:8 chany_bottom_in[10]:11 0.0006577841 +23 chany_bottom_in[0] mux_tree_tapbuf_size2_13_sram[1]:8 0.0001131313 +24 chany_bottom_in[0]:10 mux_tree_tapbuf_size2_13_sram[1]:4 2.119742e-06 +25 chany_bottom_in[0]:11 mux_tree_tapbuf_size2_13_sram[1]:9 2.119742e-06 +26 chany_bottom_in[0]:14 mux_tree_tapbuf_size2_13_sram[1]:9 0.0001131313 +27 chany_bottom_in[0]:10 mux_tree_tapbuf_size2_15_sram[0]:7 0.0001698953 +28 chany_bottom_in[0]:11 mux_tree_tapbuf_size2_15_sram[0]:6 0.0001698953 +29 chany_bottom_in[0] mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 9.707203e-05 +30 chany_bottom_in[0]:14 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.707203e-05 + +*RES +0 chany_bottom_in[0] chany_bottom_in[0]:14 0.02611831 +1 chany_bottom_in[0]:2 BUFT_P_85:A 0.152 +2 chany_bottom_in[0]:3 chany_bottom_in[0]:2 0.006497768 +3 chany_bottom_in[0]:4 chany_bottom_in[0]:3 0.0045 +4 chany_bottom_in[0]:6 chany_bottom_in[0]:5 0.0045 +5 chany_bottom_in[0]:5 chany_bottom_in[0]:4 0.007205357 +6 chany_bottom_in[0]:9 chany_bottom_in[0]:8 0.04633929 +7 chany_bottom_in[0]:10 chany_bottom_in[0]:9 0.0045 +8 chany_bottom_in[0]:11 chany_bottom_in[0]:10 0.04635492 +9 chany_bottom_in[0]:12 chany_bottom_in[0]:11 0.00341 +10 chany_bottom_in[0]:14 chany_bottom_in[0]:13 0.00341 +11 chany_bottom_in[0]:13 chany_bottom_in[0]:12 0.0003579833 +12 chany_bottom_in[0]:7 chany_bottom_in[0]:6 0.002013393 +13 chany_bottom_in[0]:8 chany_bottom_in[0]:7 0.0002297298 + +*END + +*D_NET chany_bottom_in[14] 0.01346214 //LENGTH 100.560 LUMPCC 0.004798342 DR + +*CONN +*P chany_bottom_in[14] I *L 0.29796 *C 66.240 1.325 +*I BUFT_RR_54:A I *L 0.001776 *C 13.340 44.880 +*N chany_bottom_in[14]:2 *C 13.378 44.880 +*N chany_bottom_in[14]:3 *C 13.755 44.880 +*N chany_bottom_in[14]:4 *C 13.800 44.835 +*N chany_bottom_in[14]:5 *C 13.800 41.538 +*N chany_bottom_in[14]:6 *C 13.808 41.480 +*N chany_bottom_in[14]:7 *C 35.860 41.480 +*N chany_bottom_in[14]:8 *C 35.880 41.473 +*N chany_bottom_in[14]:9 *C 35.880 2.048 +*N chany_bottom_in[14]:10 *C 35.880 2.035 +*N chany_bottom_in[14]:11 *C 35.880 1.360 +*N chany_bottom_in[14]:12 *C 58.880 1.360 +*N chany_bottom_in[14]:13 *C 58.880 2.040 +*N chany_bottom_in[14]:14 *C 66.233 2.040 +*N chany_bottom_in[14]:15 *C 66.240 1.983 + +*CAP +0 chany_bottom_in[14] 5.476408e-05 +1 BUFT_RR_54:A 1e-06 +2 chany_bottom_in[14]:2 4.582798e-05 +3 chany_bottom_in[14]:3 4.582798e-05 +4 chany_bottom_in[14]:4 0.0001401015 +5 chany_bottom_in[14]:5 0.0001401015 +6 chany_bottom_in[14]:6 0.001037666 +7 chany_bottom_in[14]:7 0.001037666 +8 chany_bottom_in[14]:8 0.001618953 +9 chany_bottom_in[14]:9 0.001618953 +10 chany_bottom_in[14]:10 4.745892e-05 +11 chany_bottom_in[14]:11 0.001062548 +12 chany_bottom_in[14]:12 0.001065788 +13 chany_bottom_in[14]:13 0.0003715384 +14 chany_bottom_in[14]:14 0.0003208405 +15 chany_bottom_in[14]:15 5.476408e-05 +16 chany_bottom_in[14]:6 chany_bottom_in[2]:6 0.0002602187 +17 chany_bottom_in[14]:7 chany_bottom_in[2]:7 0.0002602187 +18 chany_bottom_in[14]:8 chany_bottom_in[5]:8 0.0003682282 +19 chany_bottom_in[14]:9 chany_bottom_in[5]:9 0.0003682282 +20 chany_bottom_in[14]:14 chany_bottom_in[5]:11 0.0001792866 +21 chany_bottom_in[14]:11 chany_bottom_in[5]:10 0.0002895194 +22 chany_bottom_in[14]:12 chany_bottom_in[5]:11 0.0002895194 +23 chany_bottom_in[14]:13 chany_bottom_in[5]:10 0.0001792866 +24 chany_bottom_in[14]:4 bottom_left_grid_pin_34_[0]:7 9.551924e-05 +25 chany_bottom_in[14]:5 bottom_left_grid_pin_34_[0]:8 9.551924e-05 +26 chany_bottom_in[14]:8 bottom_left_grid_pin_34_[0]:18 7.839109e-05 +27 chany_bottom_in[14]:8 bottom_left_grid_pin_34_[0]:33 3.8771e-05 +28 chany_bottom_in[14]:8 bottom_left_grid_pin_34_[0]:20 6.725767e-05 +29 chany_bottom_in[14]:8 bottom_left_grid_pin_34_[0]:27 4.570755e-05 +30 chany_bottom_in[14]:9 bottom_left_grid_pin_34_[0]:26 6.725767e-05 +31 chany_bottom_in[14]:9 bottom_left_grid_pin_34_[0]:33 4.570755e-05 +32 chany_bottom_in[14]:9 bottom_left_grid_pin_34_[0]:34 3.8771e-05 +33 chany_bottom_in[14]:9 bottom_left_grid_pin_34_[0]:19 7.839109e-05 +34 chany_bottom_in[14]:6 chanx_left_in[1] 0.0005008007 +35 chany_bottom_in[14]:7 chanx_left_in[1]:7 0.0005008007 +36 chany_bottom_in[14]:4 mux_tree_tapbuf_size6_0_sram[2]:8 3.123416e-06 +37 chany_bottom_in[14]:5 mux_tree_tapbuf_size6_0_sram[2]:9 3.123416e-06 +38 chany_bottom_in[14]:6 mux_tree_tapbuf_size6_0_sram[2]:10 0.0004723475 +39 chany_bottom_in[14]:7 mux_tree_tapbuf_size6_0_sram[2]:11 0.0004723475 + +*RES +0 chany_bottom_in[14] chany_bottom_in[14]:15 0.0005870535 +1 chany_bottom_in[14]:2 BUFT_RR_54:A 0.152 +2 chany_bottom_in[14]:3 chany_bottom_in[14]:2 0.0003370536 +3 chany_bottom_in[14]:4 chany_bottom_in[14]:3 0.0045 +4 chany_bottom_in[14]:5 chany_bottom_in[14]:4 0.002944196 +5 chany_bottom_in[14]:6 chany_bottom_in[14]:5 0.00341 +6 chany_bottom_in[14]:7 chany_bottom_in[14]:6 0.003454891 +7 chany_bottom_in[14]:8 chany_bottom_in[14]:7 0.00341 +8 chany_bottom_in[14]:10 chany_bottom_in[14]:9 0.00341 +9 chany_bottom_in[14]:9 chany_bottom_in[14]:8 0.006176583 +10 chany_bottom_in[14]:15 chany_bottom_in[14]:14 0.00341 +11 chany_bottom_in[14]:14 chany_bottom_in[14]:13 0.001151892 +12 chany_bottom_in[14]:11 chany_bottom_in[14]:10 0.00010575 +13 chany_bottom_in[14]:12 chany_bottom_in[14]:11 0.003603333 +14 chany_bottom_in[14]:13 chany_bottom_in[14]:12 0.0001065333 + +*END + +*D_NET chany_bottom_in[15] 0.0136783 //LENGTH 100.810 LUMPCC 0.003025736 DR + +*CONN +*P chany_bottom_in[15] I *L 0.29796 *C 53.360 1.325 +*I BUFT_RR_55:A I *L 0.001776 *C 10.120 55.760 +*N chany_bottom_in[15]:2 *C 10.120 55.760 +*N chany_bottom_in[15]:3 *C 10.120 56.100 +*N chany_bottom_in[15]:4 *C 10.120 56.055 +*N chany_bottom_in[15]:5 *C 10.120 50.378 +*N chany_bottom_in[15]:6 *C 10.128 50.320 +*N chany_bottom_in[15]:7 *C 22.060 50.320 +*N chany_bottom_in[15]:8 *C 22.080 50.312 +*N chany_bottom_in[15]:9 *C 22.080 40.128 +*N chany_bottom_in[15]:10 *C 22.100 40.120 +*N chany_bottom_in[15]:11 *C 42.773 40.120 +*N chany_bottom_in[15]:12 *C 42.780 40.062 +*N chany_bottom_in[15]:13 *C 42.780 3.785 +*N chany_bottom_in[15]:14 *C 42.825 3.740 +*N chany_bottom_in[15]:15 *C 53.315 3.740 +*N chany_bottom_in[15]:16 *C 53.360 3.695 + +*CAP +0 chany_bottom_in[15] 0.0001497332 +1 BUFT_RR_55:A 1e-06 +2 chany_bottom_in[15]:2 7.349033e-05 +3 chany_bottom_in[15]:3 7.875406e-05 +4 chany_bottom_in[15]:4 0.0003668258 +5 chany_bottom_in[15]:5 0.0003668258 +6 chany_bottom_in[15]:6 0.0005951954 +7 chany_bottom_in[15]:7 0.0005951954 +8 chany_bottom_in[15]:8 0.0007385282 +9 chany_bottom_in[15]:9 0.0007385282 +10 chany_bottom_in[15]:10 0.001096599 +11 chany_bottom_in[15]:11 0.001096599 +12 chany_bottom_in[15]:12 0.001711828 +13 chany_bottom_in[15]:13 0.001711828 +14 chany_bottom_in[15]:14 0.0005909475 +15 chany_bottom_in[15]:15 0.0005909475 +16 chany_bottom_in[15]:16 0.0001497332 +17 chany_bottom_in[15]:10 chanx_left_in[0]:12 0.0004600522 +18 chany_bottom_in[15]:11 chanx_left_in[0]:11 0.0004600522 +19 chany_bottom_in[15]:6 chanx_left_in[16]:7 0.0004552651 +20 chany_bottom_in[15]:6 chanx_left_in[16]:11 5.597575e-06 +21 chany_bottom_in[15]:7 chanx_left_in[16]:6 0.0004552651 +22 chany_bottom_in[15]:7 chanx_left_in[16]:10 5.597575e-06 +23 chany_bottom_in[15]:10 mux_tree_tapbuf_size6_0_sram[2]:10 0.0001230968 +24 chany_bottom_in[15]:11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0001230968 +25 chany_bottom_in[15]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 8.59623e-05 +26 chany_bottom_in[15]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 4.482516e-05 +27 chany_bottom_in[15]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 8.59623e-05 +28 chany_bottom_in[15]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 4.482516e-05 +29 chany_bottom_in[15]:12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 4.402085e-05 +30 chany_bottom_in[15]:13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 4.402085e-05 +31 chany_bottom_in[15]:12 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001505319 +32 chany_bottom_in[15]:13 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001505319 +33 chany_bottom_in[15]:4 ropt_net_128:5 6.357194e-05 +34 chany_bottom_in[15]:5 ropt_net_128:6 6.357194e-05 +35 chany_bottom_in[15]:4 ropt_net_131:9 1.155373e-05 +36 chany_bottom_in[15]:5 ropt_net_131:8 1.155373e-05 +37 chany_bottom_in[15]:6 ropt_net_131:6 6.839067e-05 +38 chany_bottom_in[15]:7 ropt_net_131:7 6.839067e-05 + +*RES +0 chany_bottom_in[15] chany_bottom_in[15]:16 0.002116072 +1 chany_bottom_in[15]:2 BUFT_RR_55:A 0.152 +2 chany_bottom_in[15]:3 chany_bottom_in[15]:2 0.0001465517 +3 chany_bottom_in[15]:4 chany_bottom_in[15]:3 0.0045 +4 chany_bottom_in[15]:5 chany_bottom_in[15]:4 0.005069196 +5 chany_bottom_in[15]:6 chany_bottom_in[15]:5 0.00341 +6 chany_bottom_in[15]:7 chany_bottom_in[15]:6 0.001869425 +7 chany_bottom_in[15]:8 chany_bottom_in[15]:7 0.00341 +8 chany_bottom_in[15]:10 chany_bottom_in[15]:9 0.00341 +9 chany_bottom_in[15]:9 chany_bottom_in[15]:8 0.00159565 +10 chany_bottom_in[15]:12 chany_bottom_in[15]:11 0.00341 +11 chany_bottom_in[15]:11 chany_bottom_in[15]:10 0.003238691 +12 chany_bottom_in[15]:14 chany_bottom_in[15]:13 0.0045 +13 chany_bottom_in[15]:13 chany_bottom_in[15]:12 0.03239063 +14 chany_bottom_in[15]:15 chany_bottom_in[15]:14 0.009366072 +15 chany_bottom_in[15]:16 chany_bottom_in[15]:15 0.0045 + +*END + +*D_NET chany_bottom_in[16] 0.01706615 //LENGTH 160.095 LUMPCC 0.005788227 DR + +*CONN +*P chany_bottom_in[16] I *L 0.29796 *C 76.820 1.325 +*I ropt_mt_inst_732:A I *L 0.001766 *C 12.420 93.840 +*N chany_bottom_in[16]:2 *C 12.420 93.840 +*N chany_bottom_in[16]:3 *C 12.420 93.795 +*N chany_bottom_in[16]:4 *C 12.420 88.105 +*N chany_bottom_in[16]:5 *C 12.420 88.060 +*N chany_bottom_in[16]:6 *C 17.435 88.060 +*N chany_bottom_in[16]:7 *C 17.480 88.015 +*N chany_bottom_in[16]:8 *C 17.480 83.345 +*N chany_bottom_in[16]:9 *C 17.525 83.300 +*N chany_bottom_in[16]:10 *C 18.400 83.300 +*N chany_bottom_in[16]:11 *C 18.400 82.960 +*N chany_bottom_in[16]:12 *C 20.195 82.960 +*N chany_bottom_in[16]:13 *C 20.240 82.915 +*N chany_bottom_in[16]:14 *C 20.240 74.178 +*N chany_bottom_in[16]:15 *C 20.248 74.120 +*N chany_bottom_in[16]:16 *C 70.075 74.120 +*N chany_bottom_in[16]:17 *C 76.340 74.120 +*N chany_bottom_in[16]:18 *C 76.360 74.112 +*N chany_bottom_in[16]:19 *C 76.360 51.875 +*N chany_bottom_in[16]:20 *C 76.360 2.048 +*N chany_bottom_in[16]:21 *C 76.375 2.040 +*N chany_bottom_in[16]:22 *C 76.818 2.040 +*N chany_bottom_in[16]:23 *C 76.820 1.983 + +*CAP +0 chany_bottom_in[16] 5.60541e-05 +1 ropt_mt_inst_732:A 1e-06 +2 chany_bottom_in[16]:2 3.709922e-05 +3 chany_bottom_in[16]:3 0.0003209672 +4 chany_bottom_in[16]:4 0.0003209672 +5 chany_bottom_in[16]:5 0.0003154426 +6 chany_bottom_in[16]:6 0.0002792362 +7 chany_bottom_in[16]:7 0.0002439708 +8 chany_bottom_in[16]:8 0.0002439708 +9 chany_bottom_in[16]:9 6.820717e-05 +10 chany_bottom_in[16]:10 9.135828e-05 +11 chany_bottom_in[16]:11 0.0001313779 +12 chany_bottom_in[16]:12 0.0001082268 +13 chany_bottom_in[16]:13 0.0004437593 +14 chany_bottom_in[16]:14 0.0004437593 +15 chany_bottom_in[16]:15 0.001966171 +16 chany_bottom_in[16]:16 0.002276281 +17 chany_bottom_in[16]:17 0.0003101104 +18 chany_bottom_in[16]:18 0.0005345692 +19 chany_bottom_in[16]:19 0.00172457 +20 chany_bottom_in[16]:20 0.001190001 +21 chany_bottom_in[16]:21 5.738336e-05 +22 chany_bottom_in[16]:22 5.738336e-05 +23 chany_bottom_in[16]:23 5.60541e-05 +24 chany_bottom_in[16]:18 chany_bottom_in[12]:11 0.0002848014 +25 chany_bottom_in[16]:18 chany_bottom_in[12]:12 3.003063e-05 +26 chany_bottom_in[16]:21 chany_bottom_in[12]:14 5.743482e-06 +27 chany_bottom_in[16]:20 chany_bottom_in[12]:13 0.0006709116 +28 chany_bottom_in[16]:22 chany_bottom_in[12]:15 5.743482e-06 +29 chany_bottom_in[16]:19 chany_bottom_in[12]:12 0.000955713 +30 chany_bottom_in[16]:19 chany_bottom_in[12]:13 3.003063e-05 +31 chany_bottom_in[16]:13 prog_clk[0]:106 1.243885e-05 +32 chany_bottom_in[16]:14 prog_clk[0]:112 1.243885e-05 +33 chany_bottom_in[16]:15 prog_clk[0]:91 0.0001235046 +34 chany_bottom_in[16]:15 prog_clk[0]:64 0.0001505029 +35 chany_bottom_in[16]:16 prog_clk[0]:90 0.0001235046 +36 chany_bottom_in[16]:16 prog_clk[0]:63 0.0001505029 +37 chany_bottom_in[16]:15 chany_bottom_in[11]:6 0.0003172933 +38 chany_bottom_in[16]:17 chany_bottom_in[11]:7 4.696229e-05 +39 chany_bottom_in[16]:18 chany_bottom_in[11]:8 0.0003104578 +40 chany_bottom_in[16]:18 chany_bottom_in[11]:9 1.152764e-05 +41 chany_bottom_in[16]:20 chany_bottom_in[11]:10 0.0007190357 +42 chany_bottom_in[16]:16 chany_bottom_in[11]:6 4.696229e-05 +43 chany_bottom_in[16]:16 chany_bottom_in[11]:7 0.0003172933 +44 chany_bottom_in[16]:19 chany_bottom_in[11]:10 1.152764e-05 +45 chany_bottom_in[16]:19 chany_bottom_in[11]:9 0.001029494 +46 chany_bottom_in[16]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001386679 +47 chany_bottom_in[16]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.236674e-05 +48 chany_bottom_in[16]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.986907e-05 +49 chany_bottom_in[16]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 4.236674e-05 +50 chany_bottom_in[16]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000168537 + +*RES +0 chany_bottom_in[16] chany_bottom_in[16]:23 0.0005870535 +1 chany_bottom_in[16]:2 ropt_mt_inst_732:A 0.152 +2 chany_bottom_in[16]:3 chany_bottom_in[16]:2 0.0045 +3 chany_bottom_in[16]:5 chany_bottom_in[16]:4 0.0045 +4 chany_bottom_in[16]:4 chany_bottom_in[16]:3 0.005080357 +5 chany_bottom_in[16]:6 chany_bottom_in[16]:5 0.004477679 +6 chany_bottom_in[16]:7 chany_bottom_in[16]:6 0.0045 +7 chany_bottom_in[16]:9 chany_bottom_in[16]:8 0.0045 +8 chany_bottom_in[16]:8 chany_bottom_in[16]:7 0.004169643 +9 chany_bottom_in[16]:12 chany_bottom_in[16]:11 0.001602679 +10 chany_bottom_in[16]:13 chany_bottom_in[16]:12 0.0045 +11 chany_bottom_in[16]:14 chany_bottom_in[16]:13 0.00780134 +12 chany_bottom_in[16]:15 chany_bottom_in[16]:14 0.00341 +13 chany_bottom_in[16]:17 chany_bottom_in[16]:16 0.0009815167 +14 chany_bottom_in[16]:18 chany_bottom_in[16]:17 0.00341 +15 chany_bottom_in[16]:21 chany_bottom_in[16]:20 0.00341 +16 chany_bottom_in[16]:20 chany_bottom_in[16]:19 0.007806308 +17 chany_bottom_in[16]:23 chany_bottom_in[16]:22 0.00341 +18 chany_bottom_in[16]:22 chany_bottom_in[16]:21 6.499218e-05 +19 chany_bottom_in[16]:10 chany_bottom_in[16]:9 0.0007812501 +20 chany_bottom_in[16]:11 chany_bottom_in[16]:10 0.0003035715 +21 chany_bottom_in[16]:16 chany_bottom_in[16]:15 0.007806307 +22 chany_bottom_in[16]:19 chany_bottom_in[16]:18 0.003483875 + +*END + +*D_NET chany_bottom_in[17] 0.01721762 //LENGTH 142.635 LUMPCC 0.003569548 DR + +*CONN +*P chany_bottom_in[17] I *L 0.29796 *C 69.920 1.290 +*I ropt_mt_inst_738:A I *L 0.001767 *C 3.220 69.360 +*N chany_bottom_in[17]:2 *C 3.198 69.333 +*N chany_bottom_in[17]:3 *C 3.185 69.020 +*N chany_bottom_in[17]:4 *C 1.885 69.020 +*N chany_bottom_in[17]:5 *C 1.840 68.975 +*N chany_bottom_in[17]:6 *C 1.840 58.865 +*N chany_bottom_in[17]:7 *C 1.885 58.820 +*N chany_bottom_in[17]:8 *C 8.740 58.820 +*N chany_bottom_in[17]:9 *C 8.740 59.160 +*N chany_bottom_in[17]:10 *C 18.860 59.160 +*N chany_bottom_in[17]:11 *C 18.860 57.800 +*N chany_bottom_in[17]:12 *C 26.680 57.800 +*N chany_bottom_in[17]:13 *C 26.680 58.140 +*N chany_bottom_in[17]:14 *C 42.780 58.140 +*N chany_bottom_in[17]:15 *C 42.780 58.480 +*N chany_bottom_in[17]:16 *C 65.275 58.480 +*N chany_bottom_in[17]:17 *C 65.320 58.435 +*N chany_bottom_in[17]:18 *C 65.320 23.178 +*N chany_bottom_in[17]:19 *C 65.328 23.120 +*N chany_bottom_in[17]:20 *C 69.913 23.120 +*N chany_bottom_in[17]:21 *C 69.920 23.062 + +*CAP +0 chany_bottom_in[17] 0.001021971 +1 ropt_mt_inst_738:A 1e-06 +2 chany_bottom_in[17]:2 3.336033e-05 +3 chany_bottom_in[17]:3 0.0001245354 +4 chany_bottom_in[17]:4 9.117507e-05 +5 chany_bottom_in[17]:5 0.0005421132 +6 chany_bottom_in[17]:6 0.0005421132 +7 chany_bottom_in[17]:7 0.0005056112 +8 chany_bottom_in[17]:8 0.0005293657 +9 chany_bottom_in[17]:9 0.0007045247 +10 chany_bottom_in[17]:10 0.0007572373 +11 chany_bottom_in[17]:11 0.0004836501 +12 chany_bottom_in[17]:12 0.0004308336 +13 chany_bottom_in[17]:13 0.000798761 +14 chany_bottom_in[17]:14 0.0007996536 +15 chany_bottom_in[17]:15 0.0009064401 +16 chany_bottom_in[17]:16 0.000881897 +17 chany_bottom_in[17]:17 0.001420481 +18 chany_bottom_in[17]:18 0.001420481 +19 chany_bottom_in[17]:19 0.0003154485 +20 chany_bottom_in[17]:20 0.0003154485 +21 chany_bottom_in[17]:21 0.001021971 +22 chany_bottom_in[17]:17 prog_clk[0]:290 6.78611e-05 +23 chany_bottom_in[17]:17 prog_clk[0]:283 9.122254e-05 +24 chany_bottom_in[17]:17 prog_clk[0]:259 9.119186e-06 +25 chany_bottom_in[17]:17 prog_clk[0]:293 4.488831e-05 +26 chany_bottom_in[17]:17 prog_clk[0]:286 3.268994e-05 +27 chany_bottom_in[17]:17 prog_clk[0]:271 0.0001295728 +28 chany_bottom_in[17]:17 prog_clk[0]:264 4.072061e-05 +29 chany_bottom_in[17]:17 prog_clk[0]:263 1.570933e-06 +30 chany_bottom_in[17]:18 prog_clk[0]:294 4.488831e-05 +31 chany_bottom_in[17]:18 prog_clk[0]:287 3.268994e-05 +32 chany_bottom_in[17]:18 prog_clk[0]:283 0.0001295728 +33 chany_bottom_in[17]:18 prog_clk[0]:262 1.570933e-06 +34 chany_bottom_in[17]:18 prog_clk[0]:270 4.072061e-05 +35 chany_bottom_in[17]:18 prog_clk[0]:293 6.78611e-05 +36 chany_bottom_in[17]:18 prog_clk[0]:286 9.122254e-05 +37 chany_bottom_in[17]:18 prog_clk[0]:263 9.119186e-06 +38 chany_bottom_in[17]:19 prog_clk[0]:295 6.784438e-06 +39 chany_bottom_in[17]:20 prog_clk[0]:244 6.784438e-06 +40 chany_bottom_in[17] mux_tree_tapbuf_size2_5_sram[1]:7 8.300375e-05 +41 chany_bottom_in[17] mux_tree_tapbuf_size2_5_sram[1]:4 0.0001311829 +42 chany_bottom_in[17]:21 mux_tree_tapbuf_size2_5_sram[1]:8 8.300375e-05 +43 chany_bottom_in[17]:21 mux_tree_tapbuf_size2_5_sram[1]:7 0.0001311829 +44 chany_bottom_in[17]:11 mux_tree_tapbuf_size2_8_sram[1]:5 2.086405e-05 +45 chany_bottom_in[17]:11 mux_tree_tapbuf_size2_8_sram[1]:4 0.000100019 +46 chany_bottom_in[17]:12 mux_tree_tapbuf_size2_8_sram[1]:5 0.000100019 +47 chany_bottom_in[17]:12 mux_tree_tapbuf_size2_8_sram[1]:3 2.086405e-05 +48 chany_bottom_in[17]:13 mux_tree_tapbuf_size2_8_sram[1]:5 2.134946e-05 +49 chany_bottom_in[17]:14 mux_tree_tapbuf_size2_8_sram[1]:3 2.134946e-05 +50 chany_bottom_in[17]:8 optlc_net_106:34 1.594776e-06 +51 chany_bottom_in[17]:9 optlc_net_106:33 1.594776e-06 +52 chany_bottom_in[17]:13 optlc_net_106:28 0.0002855258 +53 chany_bottom_in[17]:13 optlc_net_106:9 3.87902e-06 +54 chany_bottom_in[17]:14 optlc_net_106:27 0.0002855258 +55 chany_bottom_in[17]:14 optlc_net_106:10 3.87902e-06 +56 chany_bottom_in[17]:16 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0006651818 +57 chany_bottom_in[17]:13 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 3.917657e-05 +58 chany_bottom_in[17]:13 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 8.567386e-06 +59 chany_bottom_in[17]:14 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 8.567386e-06 +60 chany_bottom_in[17]:14 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 3.917657e-05 +61 chany_bottom_in[17]:15 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0006651818 + +*RES +0 chany_bottom_in[17] chany_bottom_in[17]:21 0.01943973 +1 chany_bottom_in[17]:2 ropt_mt_inst_738:A 0.152 +2 chany_bottom_in[17]:4 chany_bottom_in[17]:3 0.001160714 +3 chany_bottom_in[17]:5 chany_bottom_in[17]:4 0.0045 +4 chany_bottom_in[17]:7 chany_bottom_in[17]:6 0.0045 +5 chany_bottom_in[17]:6 chany_bottom_in[17]:5 0.009026786 +6 chany_bottom_in[17]:16 chany_bottom_in[17]:15 0.02008482 +7 chany_bottom_in[17]:17 chany_bottom_in[17]:16 0.0045 +8 chany_bottom_in[17]:18 chany_bottom_in[17]:17 0.03147991 +9 chany_bottom_in[17]:19 chany_bottom_in[17]:18 0.00341 +10 chany_bottom_in[17]:21 chany_bottom_in[17]:20 0.00341 +11 chany_bottom_in[17]:20 chany_bottom_in[17]:19 0.0007183166 +12 chany_bottom_in[17]:8 chany_bottom_in[17]:7 0.006120536 +13 chany_bottom_in[17]:3 chany_bottom_in[17]:2 0.0002111487 +14 chany_bottom_in[17]:9 chany_bottom_in[17]:8 0.0003035715 +15 chany_bottom_in[17]:10 chany_bottom_in[17]:9 0.009035714 +16 chany_bottom_in[17]:11 chany_bottom_in[17]:10 0.001214286 +17 chany_bottom_in[17]:12 chany_bottom_in[17]:11 0.006982143 +18 chany_bottom_in[17]:13 chany_bottom_in[17]:12 0.0003035715 +19 chany_bottom_in[17]:14 chany_bottom_in[17]:13 0.014375 +20 chany_bottom_in[17]:15 chany_bottom_in[17]:14 0.0003035715 + +*END + +*D_NET chany_bottom_in[18] 0.0136886 //LENGTH 129.015 LUMPCC 0.002615544 DR + +*CONN +*P chany_bottom_in[18] I *L 0.29796 *C 57.500 1.290 +*I BUFT_RR_74:A I *L 0.001776 *C 16.100 85.680 +*N chany_bottom_in[18]:2 *C 16.137 85.680 +*N chany_bottom_in[18]:3 *C 22.035 85.680 +*N chany_bottom_in[18]:4 *C 22.080 85.635 +*N chany_bottom_in[18]:5 *C 22.080 80.965 +*N chany_bottom_in[18]:6 *C 22.125 80.920 +*N chany_bottom_in[18]:7 *C 23.385 80.950 +*N chany_bottom_in[18]:8 *C 23.453 80.910 +*N chany_bottom_in[18]:9 *C 23.460 80.285 +*N chany_bottom_in[18]:10 *C 23.505 80.240 +*N chany_bottom_in[18]:11 *C 24.335 80.240 +*N chany_bottom_in[18]:12 *C 24.380 80.240 +*N chany_bottom_in[18]:13 *C 24.388 80.240 +*N chany_bottom_in[18]:14 *C 57.953 80.240 +*N chany_bottom_in[18]:15 *C 57.960 80.183 +*N chany_bottom_in[18]:16 *C 57.960 71.400 +*N chany_bottom_in[18]:17 *C 57.500 71.400 +*N chany_bottom_in[18]:18 *C 57.500 51.290 + +*CAP +0 chany_bottom_in[18] 0.002234814 +1 BUFT_RR_74:A 1e-06 +2 chany_bottom_in[18]:2 0.0003137744 +3 chany_bottom_in[18]:3 0.0003137744 +4 chany_bottom_in[18]:4 0.0002432176 +5 chany_bottom_in[18]:5 0.0002432176 +6 chany_bottom_in[18]:6 9.994878e-05 +7 chany_bottom_in[18]:7 9.994878e-05 +8 chany_bottom_in[18]:8 4.967274e-05 +9 chany_bottom_in[18]:9 4.967274e-05 +10 chany_bottom_in[18]:10 6.516669e-05 +11 chany_bottom_in[18]:11 6.516669e-05 +12 chany_bottom_in[18]:12 3.337878e-05 +13 chany_bottom_in[18]:13 0.001026599 +14 chany_bottom_in[18]:14 0.001026599 +15 chany_bottom_in[18]:15 0.0004466943 +16 chany_bottom_in[18]:16 0.0004753039 +17 chany_bottom_in[18]:17 0.001039452 +18 chany_bottom_in[18]:18 0.003245657 +19 chany_bottom_in[18]:13 chany_bottom_in[11]:6 0.0003112265 +20 chany_bottom_in[18]:14 chany_bottom_in[11]:7 0.0003112265 +21 chany_bottom_in[18]:13 chanx_left_in[19]:9 0.0005106003 +22 chany_bottom_in[18]:13 chanx_left_in[19]:8 2.819108e-05 +23 chany_bottom_in[18]:14 chanx_left_in[19]:7 2.819108e-05 +24 chany_bottom_in[18]:14 chanx_left_in[19]:8 0.0005106003 +25 chany_bottom_in[18] mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 5.234602e-05 +26 chany_bottom_in[18]:18 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 5.234602e-05 +27 chany_bottom_in[18] mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001016824 +28 chany_bottom_in[18]:18 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001016824 +29 chany_bottom_in[18] mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0003037257 +30 chany_bottom_in[18]:18 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0003037257 + +*RES +0 chany_bottom_in[18] chany_bottom_in[18]:18 0.04464287 +1 chany_bottom_in[18]:2 BUFT_RR_74:A 0.152 +2 chany_bottom_in[18]:3 chany_bottom_in[18]:2 0.005265625 +3 chany_bottom_in[18]:4 chany_bottom_in[18]:3 0.0045 +4 chany_bottom_in[18]:6 chany_bottom_in[18]:5 0.0045 +5 chany_bottom_in[18]:5 chany_bottom_in[18]:4 0.004169643 +6 chany_bottom_in[18]:7 chany_bottom_in[18]:6 0.001125 +7 chany_bottom_in[18]:8 chany_bottom_in[18]:7 0.0045 +8 chany_bottom_in[18]:10 chany_bottom_in[18]:9 0.0045 +9 chany_bottom_in[18]:9 chany_bottom_in[18]:8 0.0005580357 +10 chany_bottom_in[18]:11 chany_bottom_in[18]:10 0.0007410714 +11 chany_bottom_in[18]:12 chany_bottom_in[18]:11 0.0045 +12 chany_bottom_in[18]:13 chany_bottom_in[18]:12 0.00341 +13 chany_bottom_in[18]:15 chany_bottom_in[18]:14 0.00341 +14 chany_bottom_in[18]:14 chany_bottom_in[18]:13 0.005258516 +15 chany_bottom_in[18]:17 chany_bottom_in[18]:16 0.0004107143 +16 chany_bottom_in[18]:16 chany_bottom_in[18]:15 0.007841518 +17 chany_bottom_in[18]:18 chany_bottom_in[18]:17 0.01795536 + +*END + +*D_NET prog_clk[0] 0.07021943 //LENGTH 511.645 LUMPCC 0.01586134 DR + +*CONN +*P prog_clk[0] I *L 0.29796 *C 30.820 1.290 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 31.545 4.080 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 38.905 9.520 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 47.645 9.520 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.205 25.840 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 66.505 34.000 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 70.185 42.160 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 77.545 39.440 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 75.245 50.320 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 66.965 55.760 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 69.265 58.480 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 72.485 66.640 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 75.705 31.280 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 72.945 17.680 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 62.365 17.680 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 64.665 12.240 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.230 14.960 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 49.945 20.400 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 51.785 23.120 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 35.685 20.400 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.065 23.120 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 33.845 28.560 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 18.205 36.720 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 16.410 42.160 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 19.965 47.600 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.165 31.280 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK I *L 0.001922 *C 7.165 36.720 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 7.145 39.440 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 7.625 47.600 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 39.825 39.440 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 43.505 31.280 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 53.625 39.440 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 55.465 42.160 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 45.805 34.000 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 33.845 44.880 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 10.845 55.760 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 12.685 61.200 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 19.660 55.760 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 21.425 63.920 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 14.525 66.640 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 16.825 72.080 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 19.585 74.800 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 25.565 53.040 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 34.305 53.040 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 34.765 69.360 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 37.525 74.800 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 42.585 50.320 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 42.585 55.760 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 41.665 63.920 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 53.165 61.200 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 57.305 72.080 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK I *L 0.001922 *C 46.725 72.080 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK I *L 0.001922 *C 52.245 55.760 +*N prog_clk[0]:53 *C 52.245 55.760 +*N prog_clk[0]:54 *C 51.980 55.760 +*N prog_clk[0]:55 *C 51.980 55.760 +*N prog_clk[0]:56 *C 51.973 55.760 +*N prog_clk[0]:57 *C 46.725 72.080 +*N prog_clk[0]:58 *C 46.460 72.080 +*N prog_clk[0]:59 *C 46.460 72.080 +*N prog_clk[0]:60 *C 57.305 72.080 +*N prog_clk[0]:61 *C 57.500 72.080 +*N prog_clk[0]:62 *C 57.500 72.080 +*N prog_clk[0]:63 *C 57.492 72.080 +*N prog_clk[0]:64 *C 48.308 72.080 +*N prog_clk[0]:65 *C 48.300 72.023 +*N prog_clk[0]:66 *C 53.165 61.200 +*N prog_clk[0]:67 *C 52.900 61.200 +*N prog_clk[0]:68 *C 52.900 61.200 +*N prog_clk[0]:69 *C 52.893 61.200 +*N prog_clk[0]:70 *C 48.308 61.200 +*N prog_clk[0]:71 *C 48.300 61.200 +*N prog_clk[0]:72 *C 48.300 55.818 +*N prog_clk[0]:73 *C 48.300 55.760 +*N prog_clk[0]:74 *C 42.788 55.760 +*N prog_clk[0]:75 *C 41.665 63.920 +*N prog_clk[0]:76 *C 41.860 63.920 +*N prog_clk[0]:77 *C 41.860 63.875 +*N prog_clk[0]:78 *C 41.860 55.805 +*N prog_clk[0]:79 *C 41.905 55.760 +*N prog_clk[0]:80 *C 42.547 55.760 +*N prog_clk[0]:81 *C 42.638 55.760 +*N prog_clk[0]:82 *C 42.780 55.760 +*N prog_clk[0]:83 *C 42.585 50.320 +*N prog_clk[0]:84 *C 42.780 50.320 +*N prog_clk[0]:85 *C 42.780 50.320 +*N prog_clk[0]:86 *C 42.773 50.320 +*N prog_clk[0]:87 *C 37.488 74.800 +*N prog_clk[0]:88 *C 36.385 74.800 +*N prog_clk[0]:89 *C 36.340 74.800 +*N prog_clk[0]:90 *C 36.333 74.800 +*N prog_clk[0]:91 *C 34.508 74.800 +*N prog_clk[0]:92 *C 34.500 74.743 +*N prog_clk[0]:93 *C 34.765 69.360 +*N prog_clk[0]:94 *C 34.500 69.700 +*N prog_clk[0]:95 *C 34.500 69.700 +*N prog_clk[0]:96 *C 34.305 53.040 +*N prog_clk[0]:97 *C 34.500 53.380 +*N prog_clk[0]:98 *C 34.500 53.380 +*N prog_clk[0]:99 *C 34.500 50.378 +*N prog_clk[0]:100 *C 34.500 50.320 +*N prog_clk[0]:101 *C 32.200 50.320 +*N prog_clk[0]:102 *C 25.565 53.040 +*N prog_clk[0]:103 *C 25.760 53.040 +*N prog_clk[0]:104 *C 19.585 74.800 +*N prog_clk[0]:105 *C 19.320 74.800 +*N prog_clk[0]:106 *C 19.320 74.755 +*N prog_clk[0]:107 *C 16.825 72.080 +*N prog_clk[0]:108 *C 17.020 72.080 +*N prog_clk[0]:109 *C 17.020 72.080 +*N prog_clk[0]:110 *C 17.027 72.080 +*N prog_clk[0]:111 *C 19.312 72.080 +*N prog_clk[0]:112 *C 19.320 72.080 +*N prog_clk[0]:113 *C 14.525 66.640 +*N prog_clk[0]:114 *C 14.720 66.640 +*N prog_clk[0]:115 *C 14.720 66.640 +*N prog_clk[0]:116 *C 14.728 66.640 +*N prog_clk[0]:117 *C 19.312 66.640 +*N prog_clk[0]:118 *C 19.320 66.640 +*N prog_clk[0]:119 *C 19.780 66.640 +*N prog_clk[0]:120 *C 21.387 63.920 +*N prog_clk[0]:121 *C 19.825 63.920 +*N prog_clk[0]:122 *C 19.780 63.920 +*N prog_clk[0]:123 *C 19.660 55.760 +*N prog_clk[0]:124 *C 12.685 61.200 +*N prog_clk[0]:125 *C 12.880 61.200 +*N prog_clk[0]:126 *C 12.880 61.155 +*N prog_clk[0]:127 *C 10.845 55.760 +*N prog_clk[0]:128 *C 11.040 55.760 +*N prog_clk[0]:129 *C 11.040 55.760 +*N prog_clk[0]:130 *C 12.880 55.818 +*N prog_clk[0]:131 *C 12.888 55.760 +*N prog_clk[0]:132 *C 19.773 55.760 +*N prog_clk[0]:133 *C 19.780 55.760 +*N prog_clk[0]:134 *C 19.780 53.098 +*N prog_clk[0]:135 *C 19.788 53.040 +*N prog_clk[0]:136 *C 25.753 53.040 +*N prog_clk[0]:137 *C 25.760 53.040 +*N prog_clk[0]:138 *C 25.760 49.698 +*N prog_clk[0]:139 *C 25.768 49.640 +*N prog_clk[0]:140 *C 32.200 49.648 +*N prog_clk[0]:141 *C 32.200 49.583 +*N prog_clk[0]:142 *C 33.845 44.880 +*N prog_clk[0]:143 *C 33.580 44.880 +*N prog_clk[0]:144 *C 33.580 44.880 +*N prog_clk[0]:145 *C 33.573 44.880 +*N prog_clk[0]:146 *C 32.208 44.880 +*N prog_clk[0]:147 *C 32.200 44.880 +*N prog_clk[0]:148 *C 45.805 34.000 +*N prog_clk[0]:149 *C 55.428 42.160 +*N prog_clk[0]:150 *C 54.785 42.160 +*N prog_clk[0]:151 *C 54.740 42.115 +*N prog_clk[0]:152 *C 54.740 39.440 +*N prog_clk[0]:153 *C 53.625 39.440 +*N prog_clk[0]:154 *C 53.820 39.440 +*N prog_clk[0]:155 *C 53.820 39.440 +*N prog_clk[0]:156 *C 53.812 39.440 +*N prog_clk[0]:157 *C 46.008 39.440 +*N prog_clk[0]:158 *C 46.000 39.383 +*N prog_clk[0]:159 *C 46.000 33.705 +*N prog_clk[0]:160 *C 45.955 33.668 +*N prog_clk[0]:161 *C 43.745 33.660 +*N prog_clk[0]:162 *C 43.700 33.615 +*N prog_clk[0]:163 *C 43.505 31.280 +*N prog_clk[0]:164 *C 43.700 31.280 +*N prog_clk[0]:165 *C 43.700 31.325 +*N prog_clk[0]:166 *C 43.700 31.960 +*N prog_clk[0]:167 *C 43.693 31.960 +*N prog_clk[0]:168 *C 39.825 39.440 +*N prog_clk[0]:169 *C 40.020 39.440 +*N prog_clk[0]:170 *C 40.020 39.395 +*N prog_clk[0]:171 *C 40.020 32.017 +*N prog_clk[0]:172 *C 40.020 31.960 +*N prog_clk[0]:173 *C 7.625 47.600 +*N prog_clk[0]:174 *C 7.360 47.600 +*N prog_clk[0]:175 *C 7.360 47.555 +*N prog_clk[0]:176 *C 7.145 39.440 +*N prog_clk[0]:177 *C 7.360 39.440 +*N prog_clk[0]:178 *C 7.360 39.440 +*N prog_clk[0]:179 *C 7.165 36.720 +*N prog_clk[0]:180 *C 7.360 37.060 +*N prog_clk[0]:181 *C 7.360 37.060 +*N prog_clk[0]:182 *C 7.165 31.280 +*N prog_clk[0]:183 *C 7.360 31.280 +*N prog_clk[0]:184 *C 7.360 31.325 +*N prog_clk[0]:185 *C 7.360 31.960 +*N prog_clk[0]:186 *C 7.368 31.960 +*N prog_clk[0]:187 *C 19.965 47.600 +*N prog_clk[0]:188 *C 19.965 46.920 +*N prog_clk[0]:189 *C 18.445 46.920 +*N prog_clk[0]:190 *C 18.400 46.875 +*N prog_clk[0]:191 *C 16.410 42.160 +*N prog_clk[0]:192 *C 16.560 42.160 +*N prog_clk[0]:193 *C 16.560 42.160 +*N prog_clk[0]:194 *C 18.400 42.160 +*N prog_clk[0]:195 *C 18.205 36.720 +*N prog_clk[0]:196 *C 18.400 37.060 +*N prog_clk[0]:197 *C 18.400 37.060 +*N prog_clk[0]:198 *C 18.400 32.017 +*N prog_clk[0]:199 *C 18.400 31.960 +*N prog_clk[0]:200 *C 32.200 31.960 +*N prog_clk[0]:201 *C 32.200 31.960 +*N prog_clk[0]:202 *C 33.845 28.560 +*N prog_clk[0]:203 *C 33.580 28.560 +*N prog_clk[0]:204 *C 33.580 28.560 +*N prog_clk[0]:205 *C 33.573 28.560 +*N prog_clk[0]:206 *C 32.208 28.560 +*N prog_clk[0]:207 *C 32.200 28.560 +*N prog_clk[0]:208 *C 37.028 23.120 +*N prog_clk[0]:209 *C 35.925 23.120 +*N prog_clk[0]:210 *C 35.880 23.075 +*N prog_clk[0]:211 *C 35.685 20.400 +*N prog_clk[0]:212 *C 35.880 20.400 +*N prog_clk[0]:213 *C 35.880 20.445 +*N prog_clk[0]:214 *C 35.880 21.080 +*N prog_clk[0]:215 *C 35.873 21.080 +*N prog_clk[0]:216 *C 32.208 21.080 +*N prog_clk[0]:217 *C 32.200 21.137 +*N prog_clk[0]:218 *C 31.740 21.080 +*N prog_clk[0]:219 *C 51.785 23.120 +*N prog_clk[0]:220 *C 51.980 23.120 +*N prog_clk[0]:221 *C 51.980 23.075 +*N prog_clk[0]:222 *C 51.980 20.457 +*N prog_clk[0]:223 *C 51.973 20.400 +*N prog_clk[0]:224 *C 49.945 20.400 +*N prog_clk[0]:225 *C 50.140 20.400 +*N prog_clk[0]:226 *C 50.140 20.400 +*N prog_clk[0]:227 *C 50.140 20.400 +*N prog_clk[0]:228 *C 47.388 20.400 +*N prog_clk[0]:229 *C 47.380 20.343 +*N prog_clk[0]:230 *C 46.230 14.960 +*N prog_clk[0]:231 *C 46.460 14.960 +*N prog_clk[0]:232 *C 46.460 14.960 +*N prog_clk[0]:233 *C 47.380 14.960 +*N prog_clk[0]:234 *C 64.627 12.240 +*N prog_clk[0]:235 *C 63.525 12.240 +*N prog_clk[0]:236 *C 63.480 12.240 +*N prog_clk[0]:237 *C 63.473 12.240 +*N prog_clk[0]:238 *C 62.560 12.240 +*N prog_clk[0]:239 *C 62.365 17.680 +*N prog_clk[0]:240 *C 62.560 17.680 +*N prog_clk[0]:241 *C 72.907 17.680 +*N prog_clk[0]:242 *C 71.805 17.680 +*N prog_clk[0]:243 *C 71.760 17.680 +*N prog_clk[0]:244 *C 71.752 17.680 +*N prog_clk[0]:245 *C 75.668 31.280 +*N prog_clk[0]:246 *C 74.565 31.280 +*N prog_clk[0]:247 *C 74.520 31.280 +*N prog_clk[0]:248 *C 74.513 31.280 +*N prog_clk[0]:249 *C 72.448 66.640 +*N prog_clk[0]:250 *C 71.805 66.640 +*N prog_clk[0]:251 *C 71.760 66.595 +*N prog_clk[0]:252 *C 71.760 58.538 +*N prog_clk[0]:253 *C 71.752 58.480 +*N prog_clk[0]:254 *C 69.265 58.480 +*N prog_clk[0]:255 *C 69.000 58.480 +*N prog_clk[0]:256 *C 69.000 58.480 +*N prog_clk[0]:257 *C 69.000 58.480 +*N prog_clk[0]:258 *C 67.168 58.480 +*N prog_clk[0]:259 *C 67.160 58.422 +*N prog_clk[0]:260 *C 66.965 55.760 +*N prog_clk[0]:261 *C 67.160 55.420 +*N prog_clk[0]:262 *C 67.130 55.450 +*N prog_clk[0]:263 *C 67.115 55.760 +*N prog_clk[0]:264 *C 66.700 55.760 +*N prog_clk[0]:265 *C 75.208 50.320 +*N prog_clk[0]:266 *C 74.565 50.320 +*N prog_clk[0]:267 *C 74.520 50.320 +*N prog_clk[0]:268 *C 74.513 50.320 +*N prog_clk[0]:269 *C 66.708 50.320 +*N prog_clk[0]:270 *C 66.700 50.378 +*N prog_clk[0]:271 *C 66.240 50.320 +*N prog_clk[0]:272 *C 77.545 39.440 +*N prog_clk[0]:273 *C 77.280 39.440 +*N prog_clk[0]:274 *C 77.280 39.440 +*N prog_clk[0]:275 *C 77.273 39.440 +*N prog_clk[0]:276 *C 69.920 39.440 +*N prog_clk[0]:277 *C 70.185 42.160 +*N prog_clk[0]:278 *C 69.920 42.160 +*N prog_clk[0]:279 *C 69.920 42.115 +*N prog_clk[0]:280 *C 69.920 40.178 +*N prog_clk[0]:281 *C 69.920 40.113 +*N prog_clk[0]:282 *C 66.248 40.120 +*N prog_clk[0]:283 *C 66.240 40.120 +*N prog_clk[0]:284 *C 66.505 34.000 +*N prog_clk[0]:285 *C 66.240 33.660 +*N prog_clk[0]:286 *C 66.240 33.660 +*N prog_clk[0]:287 *C 66.240 31.338 +*N prog_clk[0]:288 *C 66.240 31.280 +*N prog_clk[0]:289 *C 64.407 31.280 +*N prog_clk[0]:290 *C 64.400 31.223 +*N prog_clk[0]:291 *C 64.205 25.840 +*N prog_clk[0]:292 *C 64.400 26.180 +*N prog_clk[0]:293 *C 64.400 26.180 +*N prog_clk[0]:294 *C 64.400 17.738 +*N prog_clk[0]:295 *C 64.400 17.680 +*N prog_clk[0]:296 *C 62.568 17.680 +*N prog_clk[0]:297 *C 62.560 17.680 +*N prog_clk[0]:298 *C 62.560 12.978 +*N prog_clk[0]:299 *C 62.560 12.913 +*N prog_clk[0]:300 *C 47.388 12.920 +*N prog_clk[0]:301 *C 47.380 12.920 +*N prog_clk[0]:302 *C 47.645 9.520 +*N prog_clk[0]:303 *C 47.380 9.860 +*N prog_clk[0]:304 *C 47.380 9.905 +*N prog_clk[0]:305 *C 47.380 9.520 +*N prog_clk[0]:306 *C 47.373 9.520 +*N prog_clk[0]:307 *C 38.905 9.520 +*N prog_clk[0]:308 *C 39.100 9.520 +*N prog_clk[0]:309 *C 39.100 9.520 +*N prog_clk[0]:310 *C 39.100 9.520 +*N prog_clk[0]:311 *C 31.748 9.520 +*N prog_clk[0]:312 *C 31.740 9.578 +*N prog_clk[0]:313 *C 31.280 9.520 +*N prog_clk[0]:314 *C 31.545 4.080 +*N prog_clk[0]:315 *C 31.280 4.420 +*N prog_clk[0]:316 *C 31.280 4.465 +*N prog_clk[0]:317 *C 30.820 4.420 + +*CAP +0 prog_clk[0] 0.0001424715 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +4 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +5 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +6 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +7 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +8 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +9 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +10 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +11 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +12 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +13 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +14 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +15 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +16 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +17 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +18 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +19 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +20 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +21 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +22 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +23 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +24 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +25 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +26 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 1e-06 +27 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +28 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +29 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +30 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +31 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +32 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +33 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +34 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +35 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +36 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +37 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +38 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +39 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +40 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +41 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +42 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +43 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +44 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +45 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +46 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +47 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +48 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +49 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +50 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +51 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 1e-06 +52 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 1e-06 +53 prog_clk[0]:53 6.267069e-05 +54 prog_clk[0]:54 5.981146e-05 +55 prog_clk[0]:55 3.736765e-05 +56 prog_clk[0]:56 7.265064e-05 +57 prog_clk[0]:57 5.492778e-05 +58 prog_clk[0]:58 5.955702e-05 +59 prog_clk[0]:59 0.0001362433 +60 prog_clk[0]:60 5.545104e-05 +61 prog_clk[0]:61 5.438707e-05 +62 prog_clk[0]:62 3.498335e-05 +63 prog_clk[0]:63 0.0004226626 +64 prog_clk[0]:64 0.0004226626 +65 prog_clk[0]:65 0.0006677501 +66 prog_clk[0]:66 4.672738e-05 +67 prog_clk[0]:67 4.931109e-05 +68 prog_clk[0]:68 3.650502e-05 +69 prog_clk[0]:69 0.0001006718 +70 prog_clk[0]:70 0.0001006718 +71 prog_clk[0]:71 0.0009066056 +72 prog_clk[0]:72 0.0003075317 +73 prog_clk[0]:73 0.0002425515 +74 prog_clk[0]:74 0.0001699009 +75 prog_clk[0]:75 5.914196e-05 +76 prog_clk[0]:76 5.965136e-05 +77 prog_clk[0]:77 0.0004176933 +78 prog_clk[0]:78 0.0004176933 +79 prog_clk[0]:79 6.170623e-05 +80 prog_clk[0]:80 9.028403e-05 +81 prog_clk[0]:81 2.857781e-05 +82 prog_clk[0]:82 0.0003383351 +83 prog_clk[0]:83 5.766768e-05 +84 prog_clk[0]:84 5.874959e-05 +85 prog_clk[0]:85 0.0003366499 +86 prog_clk[0]:86 0.0002251483 +87 prog_clk[0]:87 0.0001087494 +88 prog_clk[0]:88 0.0001087494 +89 prog_clk[0]:89 3.481499e-05 +90 prog_clk[0]:90 7.309816e-05 +91 prog_clk[0]:91 7.309816e-05 +92 prog_clk[0]:92 0.000260249 +93 prog_clk[0]:93 6.829016e-05 +94 prog_clk[0]:94 7.143118e-05 +95 prog_clk[0]:95 0.001164205 +96 prog_clk[0]:96 6.595853e-05 +97 prog_clk[0]:97 6.84397e-05 +98 prog_clk[0]:98 0.001082325 +99 prog_clk[0]:99 0.0001788528 +100 prog_clk[0]:100 0.0003155566 +101 prog_clk[0]:101 0.0001308993 +102 prog_clk[0]:102 6.515664e-05 +103 prog_clk[0]:103 6.789278e-05 +104 prog_clk[0]:104 5.909485e-05 +105 prog_clk[0]:105 6.097461e-05 +106 prog_clk[0]:106 0.0001708762 +107 prog_clk[0]:107 4.284845e-05 +108 prog_clk[0]:108 4.688674e-05 +109 prog_clk[0]:109 3.160753e-05 +110 prog_clk[0]:110 0.0002332675 +111 prog_clk[0]:111 0.0002332675 +112 prog_clk[0]:112 0.0004819032 +113 prog_clk[0]:113 5.739518e-05 +114 prog_clk[0]:114 5.398095e-05 +115 prog_clk[0]:115 3.696978e-05 +116 prog_clk[0]:116 0.0001679574 +117 prog_clk[0]:117 0.0001679574 +118 prog_clk[0]:118 0.0003076508 +119 prog_clk[0]:119 0.0001695668 +120 prog_clk[0]:120 0.0001140659 +121 prog_clk[0]:121 0.0001140659 +122 prog_clk[0]:122 0.0005856759 +123 prog_clk[0]:123 3.09653e-05 +124 prog_clk[0]:124 5.405473e-05 +125 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prog_clk[0]:276 chanx_left_in[12]:7 2.568112e-05 +461 prog_clk[0]:140 mux_tree_tapbuf_size3_1_sram[0]:18 0.0001549667 +462 prog_clk[0]:135 mux_tree_tapbuf_size3_1_sram[0]:17 5.307189e-07 +463 prog_clk[0]:135 mux_tree_tapbuf_size3_1_sram[0]:13 2.462536e-06 +464 prog_clk[0]:137 mux_tree_tapbuf_size3_1_sram[0]:15 2.132515e-05 +465 prog_clk[0]:136 mux_tree_tapbuf_size3_1_sram[0]:17 2.462536e-06 +466 prog_clk[0]:136 mux_tree_tapbuf_size3_1_sram[0]:18 5.307189e-07 +467 prog_clk[0]:138 mux_tree_tapbuf_size3_1_sram[0]:16 2.132515e-05 +468 prog_clk[0]:139 mux_tree_tapbuf_size3_1_sram[0]:17 0.0001549667 +469 prog_clk[0]:100 mux_tree_tapbuf_size3_1_sram[0]:17 0.0001187712 +470 prog_clk[0]:100 mux_tree_tapbuf_size3_1_sram[0]:18 2.644241e-05 +471 prog_clk[0]:269 mux_tree_tapbuf_size3_1_sram[0]:17 9.976575e-05 +472 prog_clk[0]:268 mux_tree_tapbuf_size3_1_sram[0]:18 9.976575e-05 +473 prog_clk[0]:86 mux_tree_tapbuf_size3_1_sram[0]:18 0.0001187712 +474 prog_clk[0]:101 mux_tree_tapbuf_size3_1_sram[0]:17 2.644241e-05 +475 prog_clk[0]:197 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 8.079335e-05 +476 prog_clk[0]:189 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.54239e-08 +477 prog_clk[0]:190 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.375418e-05 +478 prog_clk[0]:188 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.54239e-08 +479 prog_clk[0]:194 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 8.079335e-05 +480 prog_clk[0]:194 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.375418e-05 +481 prog_clk[0]:140 optlc_net_106:45 4.113661e-07 +482 prog_clk[0]:140 optlc_net_106:32 1.534627e-05 +483 prog_clk[0]:134 optlc_net_106:43 2.471987e-06 +484 prog_clk[0]:135 optlc_net_106:44 0.0003451954 +485 prog_clk[0]:137 optlc_net_106:46 4.895739e-06 +486 prog_clk[0]:136 optlc_net_106:45 0.0003451954 +487 prog_clk[0]:138 optlc_net_106:32 4.895739e-06 +488 prog_clk[0]:139 optlc_net_106:44 4.113661e-07 +489 prog_clk[0]:258 optlc_net_106:19 4.21817e-06 +490 prog_clk[0]:253 optlc_net_106:18 6.640946e-06 +491 prog_clk[0]:257 optlc_net_106:19 6.640946e-06 +492 prog_clk[0]:257 optlc_net_106:18 4.21817e-06 +493 prog_clk[0]:95 optlc_net_106:13 3.186329e-07 +494 prog_clk[0]:95 optlc_net_106:20 1.02036e-06 +495 prog_clk[0]:95 optlc_net_106:25 1.015093e-05 +496 prog_clk[0]:98 optlc_net_106:21 1.02036e-06 +497 prog_clk[0]:98 optlc_net_106:20 3.186329e-07 +498 prog_clk[0]:98 optlc_net_106:26 1.015093e-05 +499 prog_clk[0]:122 optlc_net_106:43 5.653628e-06 +500 prog_clk[0]:122 optlc_net_106:40 1.728138e-05 +501 prog_clk[0]:118 optlc_net_106:43 2.113989e-05 +502 prog_clk[0]:133 optlc_net_106:43 1.728138e-05 +503 prog_clk[0]:133 optlc_net_106:40 2.471987e-06 +504 prog_clk[0]:112 optlc_net_106:40 2.113989e-05 +505 prog_clk[0]:119 optlc_net_106:40 5.653628e-06 +506 prog_clk[0]:101 optlc_net_106:46 1.534627e-05 +507 prog_clk[0]:201 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 9.489823e-06 +508 prog_clk[0]:200 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0001678639 +509 prog_clk[0]:300 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.962366e-06 +510 prog_clk[0]:299 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 8.962366e-06 +511 prog_clk[0]:167 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 7.450996e-05 +512 prog_clk[0]:172 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0001678639 +513 prog_clk[0]:172 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 7.450996e-05 +514 prog_clk[0]:147 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 9.489823e-06 +515 prog_clk[0]:82 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.200487e-06 +516 prog_clk[0]:290 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.192281e-08 +517 prog_clk[0]:294 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.640926e-07 +518 prog_clk[0]:287 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.268994e-05 +519 prog_clk[0]:283 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.122254e-05 +520 prog_clk[0]:283 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001150262 +521 prog_clk[0]:270 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.98344e-05 +522 prog_clk[0]:270 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.638077e-05 +523 prog_clk[0]:85 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.200487e-06 +524 prog_clk[0]:293 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.640926e-07 +525 prog_clk[0]:293 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.192281e-08 +526 prog_clk[0]:78 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 4.690485e-05 +527 prog_clk[0]:77 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 4.690485e-05 +528 prog_clk[0]:286 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.268994e-05 +529 prog_clk[0]:286 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.122254e-05 +530 prog_clk[0]:280 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.210236e-06 +531 prog_clk[0]:281 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.960399e-06 +532 prog_clk[0]:279 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.210236e-06 +533 prog_clk[0]:271 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.98344e-05 +534 prog_clk[0]:271 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001150262 +535 prog_clk[0]:264 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 3.166691e-05 +536 prog_clk[0]:264 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.638077e-05 +537 prog_clk[0]:263 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 3.166691e-05 +538 prog_clk[0]:276 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.960399e-06 +539 prog_clk[0]:161 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.929272e-05 +540 prog_clk[0]:162 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.076854e-06 +541 prog_clk[0]:166 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.076854e-06 +542 prog_clk[0]:166 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 2.323058e-06 +543 prog_clk[0]:160 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.929272e-05 +544 prog_clk[0]:165 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 2.323058e-06 +545 prog_clk[0]:140 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001351251 +546 prog_clk[0]:135 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 2.798429e-05 +547 prog_clk[0]:137 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 4.410357e-06 +548 prog_clk[0]:136 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 2.798429e-05 +549 prog_clk[0]:299 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.512201e-05 +550 prog_clk[0]:138 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 4.410357e-06 +551 prog_clk[0]:139 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001351251 +552 prog_clk[0]:100 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004687048 +553 prog_clk[0]:100 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001348785 +554 prog_clk[0]:86 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004687048 +555 prog_clk[0]:101 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001348785 +556 prog_clk[0]:238 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.512201e-05 +557 prog_clk[0]:141 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0001162507 +558 prog_clk[0]:201 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 3.744733e-06 +559 prog_clk[0]:298 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001365956 +560 prog_clk[0]:299 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.629905e-06 +561 prog_clk[0]:297 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001365956 +562 prog_clk[0]:290 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.808882e-05 +563 prog_clk[0]:294 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.941193e-05 +564 prog_clk[0]:293 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.941193e-05 +565 prog_clk[0]:293 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.808882e-05 +566 prog_clk[0]:147 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0001162507 +567 prog_clk[0]:147 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 3.744733e-06 +568 prog_clk[0]:238 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.629905e-06 + +*RES +0 prog_clk[0] prog_clk[0]:317 0.002794643 +1 prog_clk[0]:127 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +2 prog_clk[0]:128 prog_clk[0]:127 0.0001059783 +3 prog_clk[0]:129 prog_clk[0]:128 0.0045 +4 prog_clk[0]:247 prog_clk[0]:246 0.0045 +5 prog_clk[0]:248 prog_clk[0]:247 0.00341 +6 prog_clk[0]:246 prog_clk[0]:245 0.000984375 +7 prog_clk[0]:245 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +8 prog_clk[0]:141 prog_clk[0]:140 0.00341 +9 prog_clk[0]:140 prog_clk[0]:139 0.001007758 +10 prog_clk[0]:140 prog_clk[0]:101 0.0001053583 +11 prog_clk[0]:174 prog_clk[0]:173 0.0001440218 +12 prog_clk[0]:175 prog_clk[0]:174 0.0045 +13 prog_clk[0]:173 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +14 prog_clk[0]:214 prog_clk[0]:213 0.0005669643 +15 prog_clk[0]:214 prog_clk[0]:210 0.00178125 +16 prog_clk[0]:215 prog_clk[0]:214 0.00341 +17 prog_clk[0]:217 prog_clk[0]:216 0.00341 +18 prog_clk[0]:217 prog_clk[0]:207 0.006627233 +19 prog_clk[0]:216 prog_clk[0]:215 0.0005741833 +20 prog_clk[0]:134 prog_clk[0]:133 0.002377232 +21 prog_clk[0]:135 prog_clk[0]:134 0.00341 +22 prog_clk[0]:137 prog_clk[0]:136 0.00341 +23 prog_clk[0]:137 prog_clk[0]:103 0.0045 +24 prog_clk[0]:136 prog_clk[0]:135 0.0009345167 +25 prog_clk[0]:198 prog_clk[0]:197 0.004502233 +26 prog_clk[0]:199 prog_clk[0]:198 0.00341 +27 prog_clk[0]:199 prog_clk[0]:186 0.001728425 +28 prog_clk[0]:201 prog_clk[0]:200 0.00341 +29 prog_clk[0]:201 prog_clk[0]:147 0.01153572 +30 prog_clk[0]:200 prog_clk[0]:199 0.002162 +31 prog_clk[0]:200 prog_clk[0]:172 0.001225133 +32 prog_clk[0]:301 prog_clk[0]:300 0.00341 +33 prog_clk[0]:301 prog_clk[0]:233 0.001821429 +34 prog_clk[0]:300 prog_clk[0]:299 0.002377025 +35 prog_clk[0]:298 prog_clk[0]:297 0.004198661 +36 prog_clk[0]:299 prog_clk[0]:298 0.00341 +37 prog_clk[0]:299 prog_clk[0]:238 0.0001053583 +38 prog_clk[0]:81 prog_clk[0]:80 8.035715e-05 +39 prog_clk[0]:82 prog_clk[0]:81 0.0045 +40 prog_clk[0]:82 prog_clk[0]:74 0.00341 +41 prog_clk[0]:297 prog_clk[0]:296 0.00341 +42 prog_clk[0]:297 prog_clk[0]:240 0.0045 +43 prog_clk[0]:296 prog_clk[0]:295 0.0002870917 +44 prog_clk[0]:92 prog_clk[0]:91 0.00341 +45 prog_clk[0]:91 prog_clk[0]:90 0.0002859167 +46 prog_clk[0]:89 prog_clk[0]:88 0.0045 +47 prog_clk[0]:90 prog_clk[0]:89 0.00341 +48 prog_clk[0]:88 prog_clk[0]:87 0.000984375 +49 prog_clk[0]:87 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +50 prog_clk[0]:161 prog_clk[0]:160 0.001973215 +51 prog_clk[0]:162 prog_clk[0]:161 0.0045 +52 prog_clk[0]:138 prog_clk[0]:137 0.002984375 +53 prog_clk[0]:139 prog_clk[0]:138 0.00341 +54 prog_clk[0]:185 prog_clk[0]:184 0.0005669643 +55 prog_clk[0]:185 prog_clk[0]:181 0.004553571 +56 prog_clk[0]:186 prog_clk[0]:185 0.00341 +57 prog_clk[0]:290 prog_clk[0]:289 0.00341 +58 prog_clk[0]:289 prog_clk[0]:288 0.0002870917 +59 prog_clk[0]:294 prog_clk[0]:293 0.007537947 +60 prog_clk[0]:295 prog_clk[0]:294 0.00341 +61 prog_clk[0]:295 prog_clk[0]:244 0.001151892 +62 prog_clk[0]:105 prog_clk[0]:104 0.0001440218 +63 prog_clk[0]:106 prog_clk[0]:105 0.0045 +64 prog_clk[0]:104 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +65 prog_clk[0]:287 prog_clk[0]:286 0.002073661 +66 prog_clk[0]:288 prog_clk[0]:287 0.00341 +67 prog_clk[0]:288 prog_clk[0]:248 0.001296025 +68 prog_clk[0]:72 prog_clk[0]:71 0.004805804 +69 prog_clk[0]:73 prog_clk[0]:72 0.00341 +70 prog_clk[0]:73 prog_clk[0]:56 0.0005753583 +71 prog_clk[0]:166 prog_clk[0]:165 0.0005669643 +72 prog_clk[0]:166 prog_clk[0]:162 0.001477679 +73 prog_clk[0]:167 prog_clk[0]:166 0.00341 +74 prog_clk[0]:283 prog_clk[0]:282 0.00341 +75 prog_clk[0]:283 prog_clk[0]:271 0.009107143 +76 prog_clk[0]:282 prog_clk[0]:281 0.0005753583 +77 prog_clk[0]:99 prog_clk[0]:98 0.002680804 +78 prog_clk[0]:100 prog_clk[0]:99 0.00341 +79 prog_clk[0]:100 prog_clk[0]:86 0.001296025 +80 prog_clk[0]:171 prog_clk[0]:170 0.006587054 +81 prog_clk[0]:172 prog_clk[0]:171 0.00341 +82 prog_clk[0]:172 prog_clk[0]:167 0.0005753583 +83 prog_clk[0]:169 prog_clk[0]:168 0.0001059783 +84 prog_clk[0]:170 prog_clk[0]:169 0.0045 +85 prog_clk[0]:168 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +86 prog_clk[0]:312 prog_clk[0]:311 0.00341 +87 prog_clk[0]:312 prog_clk[0]:218 0.01027009 +88 prog_clk[0]:311 prog_clk[0]:310 0.001151892 +89 prog_clk[0]:155 prog_clk[0]:154 0.0045 +90 prog_clk[0]:155 prog_clk[0]:152 0.0008214285 +91 prog_clk[0]:156 prog_clk[0]:155 0.00341 +92 prog_clk[0]:158 prog_clk[0]:157 0.00341 +93 prog_clk[0]:157 prog_clk[0]:156 0.001222783 +94 prog_clk[0]:160 prog_clk[0]:159 0.0045 +95 prog_clk[0]:160 prog_clk[0]:148 0.0001807065 +96 prog_clk[0]:159 prog_clk[0]:158 0.005069197 +97 prog_clk[0]:259 prog_clk[0]:258 0.00341 +98 prog_clk[0]:258 prog_clk[0]:257 0.0002870917 +99 prog_clk[0]:192 prog_clk[0]:191 8.152174e-05 +100 prog_clk[0]:193 prog_clk[0]:192 0.0045 +101 prog_clk[0]:191 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +102 prog_clk[0]:229 prog_clk[0]:228 0.00341 +103 prog_clk[0]:228 prog_clk[0]:227 0.000431225 +104 prog_clk[0]:274 prog_clk[0]:273 0.0045 +105 prog_clk[0]:275 prog_clk[0]:274 0.00341 +106 prog_clk[0]:273 prog_clk[0]:272 0.0001440218 +107 prog_clk[0]:272 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +108 prog_clk[0]:58 prog_clk[0]:57 0.0001440218 +109 prog_clk[0]:59 prog_clk[0]:58 0.0045 +110 prog_clk[0]:57 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +111 prog_clk[0]:65 prog_clk[0]:64 0.00341 +112 prog_clk[0]:65 prog_clk[0]:59 0.001642857 +113 prog_clk[0]:64 prog_clk[0]:63 0.001438983 +114 prog_clk[0]:62 prog_clk[0]:61 0.0045 +115 prog_clk[0]:63 prog_clk[0]:62 0.00341 +116 prog_clk[0]:61 prog_clk[0]:60 0.0001059783 +117 prog_clk[0]:60 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +118 prog_clk[0]:252 prog_clk[0]:251 0.007194196 +119 prog_clk[0]:253 prog_clk[0]:252 0.00341 +120 prog_clk[0]:250 prog_clk[0]:249 0.0005736608 +121 prog_clk[0]:251 prog_clk[0]:250 0.0045 +122 prog_clk[0]:249 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +123 prog_clk[0]:256 prog_clk[0]:255 0.0045 +124 prog_clk[0]:257 prog_clk[0]:256 0.00341 +125 prog_clk[0]:257 prog_clk[0]:253 0.000431225 +126 prog_clk[0]:255 prog_clk[0]:254 0.0001440218 +127 prog_clk[0]:254 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +128 prog_clk[0]:261 prog_clk[0]:260 0.0001847826 +129 prog_clk[0]:262 prog_clk[0]:261 0.0045 +130 prog_clk[0]:260 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +131 prog_clk[0]:270 prog_clk[0]:269 0.00341 +132 prog_clk[0]:270 prog_clk[0]:264 0.004805804 +133 prog_clk[0]:269 prog_clk[0]:268 0.001222783 +134 prog_clk[0]:267 prog_clk[0]:266 0.0045 +135 prog_clk[0]:268 prog_clk[0]:267 0.00341 +136 prog_clk[0]:266 prog_clk[0]:265 0.0005736608 +137 prog_clk[0]:265 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +138 prog_clk[0]:85 prog_clk[0]:84 0.0045 +139 prog_clk[0]:85 prog_clk[0]:82 0.004857142 +140 prog_clk[0]:86 prog_clk[0]:85 0.00341 +141 prog_clk[0]:55 prog_clk[0]:54 0.0045 +142 prog_clk[0]:56 prog_clk[0]:55 0.00341 +143 prog_clk[0]:54 prog_clk[0]:53 0.0001440218 +144 prog_clk[0]:53 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +145 prog_clk[0]:292 prog_clk[0]:291 0.0001847826 +146 prog_clk[0]:293 prog_clk[0]:292 0.0045 +147 prog_clk[0]:293 prog_clk[0]:290 0.004502232 +148 prog_clk[0]:291 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +149 prog_clk[0]:80 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +150 prog_clk[0]:80 prog_clk[0]:79 0.0005736608 +151 prog_clk[0]:79 prog_clk[0]:78 0.0045 +152 prog_clk[0]:78 prog_clk[0]:77 0.007205357 +153 prog_clk[0]:76 prog_clk[0]:75 0.0001059783 +154 prog_clk[0]:77 prog_clk[0]:76 0.0045 +155 prog_clk[0]:75 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +156 prog_clk[0]:285 prog_clk[0]:284 0.0001847826 +157 prog_clk[0]:286 prog_clk[0]:285 0.0045 +158 prog_clk[0]:286 prog_clk[0]:283 0.005767857 +159 prog_clk[0]:284 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +160 prog_clk[0]:154 prog_clk[0]:153 0.0001059783 +161 prog_clk[0]:153 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +162 prog_clk[0]:94 prog_clk[0]:93 0.0001847826 +163 prog_clk[0]:95 prog_clk[0]:94 0.0045 +164 prog_clk[0]:95 prog_clk[0]:92 0.004502233 +165 prog_clk[0]:93 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +166 prog_clk[0]:148 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +167 prog_clk[0]:71 prog_clk[0]:70 0.00341 +168 prog_clk[0]:71 prog_clk[0]:65 0.009662947 +169 prog_clk[0]:70 prog_clk[0]:69 0.0007183166 +170 prog_clk[0]:68 prog_clk[0]:67 0.0045 +171 prog_clk[0]:69 prog_clk[0]:68 0.00341 +172 prog_clk[0]:67 prog_clk[0]:66 0.0001440218 +173 prog_clk[0]:66 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +174 prog_clk[0]:226 prog_clk[0]:225 0.0045 +175 prog_clk[0]:227 prog_clk[0]:226 0.00341 +176 prog_clk[0]:227 prog_clk[0]:223 0.0002870916 +177 prog_clk[0]:225 prog_clk[0]:224 0.0001059783 +178 prog_clk[0]:224 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +179 prog_clk[0]:74 prog_clk[0]:73 0.000863625 +180 prog_clk[0]:84 prog_clk[0]:83 0.0001059783 +181 prog_clk[0]:83 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +182 prog_clk[0]:280 prog_clk[0]:279 0.001729911 +183 prog_clk[0]:281 prog_clk[0]:280 0.00341 +184 prog_clk[0]:281 prog_clk[0]:276 0.0001053583 +185 prog_clk[0]:278 prog_clk[0]:277 0.0001440217 +186 prog_clk[0]:279 prog_clk[0]:278 0.0045 +187 prog_clk[0]:277 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +188 prog_clk[0]:97 prog_clk[0]:96 0.0001847826 +189 prog_clk[0]:98 prog_clk[0]:97 0.0045 +190 prog_clk[0]:98 prog_clk[0]:95 0.01457143 +191 prog_clk[0]:96 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +192 prog_clk[0]:303 prog_clk[0]:302 0.0001847826 +193 prog_clk[0]:304 prog_clk[0]:303 0.0045 +194 prog_clk[0]:304 prog_clk[0]:301 0.002691964 +195 prog_clk[0]:302 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +196 prog_clk[0]:103 prog_clk[0]:102 0.0001059783 +197 prog_clk[0]:102 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +198 prog_clk[0]:309 prog_clk[0]:308 0.0045 +199 prog_clk[0]:310 prog_clk[0]:309 0.00341 +200 prog_clk[0]:310 prog_clk[0]:306 0.001296025 +201 prog_clk[0]:308 prog_clk[0]:307 0.0001059783 +202 prog_clk[0]:307 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +203 prog_clk[0]:207 prog_clk[0]:206 0.00341 +204 prog_clk[0]:207 prog_clk[0]:201 0.003035714 +205 prog_clk[0]:206 prog_clk[0]:205 0.00021385 +206 prog_clk[0]:204 prog_clk[0]:203 0.0045 +207 prog_clk[0]:205 prog_clk[0]:204 0.00341 +208 prog_clk[0]:203 prog_clk[0]:202 0.0001440218 +209 prog_clk[0]:202 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +210 prog_clk[0]:121 prog_clk[0]:120 0.001395089 +211 prog_clk[0]:122 prog_clk[0]:121 0.0045 +212 prog_clk[0]:122 prog_clk[0]:119 0.002428572 +213 prog_clk[0]:120 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +214 prog_clk[0]:147 prog_clk[0]:146 0.00341 +215 prog_clk[0]:147 prog_clk[0]:141 0.004198661 +216 prog_clk[0]:146 prog_clk[0]:145 0.00021385 +217 prog_clk[0]:144 prog_clk[0]:143 0.0045 +218 prog_clk[0]:145 prog_clk[0]:144 0.00341 +219 prog_clk[0]:143 prog_clk[0]:142 0.0001440218 +220 prog_clk[0]:142 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +221 prog_clk[0]:118 prog_clk[0]:117 0.00341 +222 prog_clk[0]:118 prog_clk[0]:112 0.004857143 +223 prog_clk[0]:117 prog_clk[0]:116 0.0007183166 +224 prog_clk[0]:115 prog_clk[0]:114 0.0045 +225 prog_clk[0]:116 prog_clk[0]:115 0.00341 +226 prog_clk[0]:114 prog_clk[0]:113 0.0001059783 +227 prog_clk[0]:113 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +228 prog_clk[0]:196 prog_clk[0]:195 0.0001847826 +229 prog_clk[0]:197 prog_clk[0]:196 0.0045 +230 prog_clk[0]:197 prog_clk[0]:194 0.004553572 +231 prog_clk[0]:195 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +232 prog_clk[0]:189 prog_clk[0]:188 0.001357143 +233 prog_clk[0]:190 prog_clk[0]:189 0.0045 +234 prog_clk[0]:187 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +235 prog_clk[0]:133 prog_clk[0]:132 0.00341 +236 prog_clk[0]:133 prog_clk[0]:123 0.0045 +237 prog_clk[0]:133 prog_clk[0]:122 0.007285715 +238 prog_clk[0]:132 prog_clk[0]:131 0.00107865 +239 prog_clk[0]:130 prog_clk[0]:129 0.001642857 +240 prog_clk[0]:130 prog_clk[0]:126 0.004765625 +241 prog_clk[0]:131 prog_clk[0]:130 0.00341 +242 prog_clk[0]:125 prog_clk[0]:124 0.0001059783 +243 prog_clk[0]:126 prog_clk[0]:125 0.0045 +244 prog_clk[0]:124 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +245 prog_clk[0]:112 prog_clk[0]:111 0.00341 +246 prog_clk[0]:112 prog_clk[0]:106 0.002388393 +247 prog_clk[0]:111 prog_clk[0]:110 0.0003579833 +248 prog_clk[0]:109 prog_clk[0]:108 0.0045 +249 prog_clk[0]:110 prog_clk[0]:109 0.00341 +250 prog_clk[0]:108 prog_clk[0]:107 0.0001059783 +251 prog_clk[0]:107 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +252 prog_clk[0]:305 prog_clk[0]:304 0.0001850962 +253 prog_clk[0]:306 prog_clk[0]:305 0.00341 +254 prog_clk[0]:243 prog_clk[0]:242 0.0045 +255 prog_clk[0]:244 prog_clk[0]:243 0.00341 +256 prog_clk[0]:242 prog_clk[0]:241 0.0009843751 +257 prog_clk[0]:241 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +258 prog_clk[0]:315 prog_clk[0]:314 0.0001847826 +259 prog_clk[0]:316 prog_clk[0]:315 0.0045 +260 prog_clk[0]:316 prog_clk[0]:313 0.004513393 +261 prog_clk[0]:314 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +262 prog_clk[0]:236 prog_clk[0]:235 0.0045 +263 prog_clk[0]:237 prog_clk[0]:236 0.00341 +264 prog_clk[0]:235 prog_clk[0]:234 0.000984375 +265 prog_clk[0]:234 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +266 prog_clk[0]:212 prog_clk[0]:211 8.423914e-05 +267 prog_clk[0]:213 prog_clk[0]:212 0.0045 +268 prog_clk[0]:211 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +269 prog_clk[0]:240 prog_clk[0]:239 0.0001059783 +270 prog_clk[0]:239 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +271 prog_clk[0]:209 prog_clk[0]:208 0.000984375 +272 prog_clk[0]:210 prog_clk[0]:209 0.0045 +273 prog_clk[0]:208 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +274 prog_clk[0]:222 prog_clk[0]:221 0.002337054 +275 prog_clk[0]:223 prog_clk[0]:222 0.00341 +276 prog_clk[0]:220 prog_clk[0]:219 0.0001059783 +277 prog_clk[0]:221 prog_clk[0]:220 0.0045 +278 prog_clk[0]:219 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +279 prog_clk[0]:180 prog_clk[0]:179 0.0001847826 +280 prog_clk[0]:181 prog_clk[0]:180 0.0045 +281 prog_clk[0]:181 prog_clk[0]:178 0.002125 +282 prog_clk[0]:179 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:CLK 0.152 +283 prog_clk[0]:183 prog_clk[0]:182 0.0001059783 +284 prog_clk[0]:184 prog_clk[0]:183 0.0045 +285 prog_clk[0]:182 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +286 prog_clk[0]:164 prog_clk[0]:163 0.0001059783 +287 prog_clk[0]:165 prog_clk[0]:164 0.0045 +288 prog_clk[0]:163 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:CLK 0.152 +289 prog_clk[0]:177 prog_clk[0]:176 0.0001168478 +290 prog_clk[0]:178 prog_clk[0]:177 0.0045 +291 prog_clk[0]:178 prog_clk[0]:175 0.007245536 +292 prog_clk[0]:176 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +293 prog_clk[0]:150 prog_clk[0]:149 0.0005736608 +294 prog_clk[0]:151 prog_clk[0]:150 0.0045 +295 prog_clk[0]:149 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +296 prog_clk[0]:231 prog_clk[0]:230 0.000125 +297 prog_clk[0]:232 prog_clk[0]:231 0.0045 +298 prog_clk[0]:230 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +299 prog_clk[0]:123 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:CLK 0.152 +300 prog_clk[0]:188 prog_clk[0]:187 0.0006071429 +301 prog_clk[0]:194 prog_clk[0]:193 0.001642857 +302 prog_clk[0]:194 prog_clk[0]:190 0.004209822 +303 prog_clk[0]:119 prog_clk[0]:118 0.0004107143 +304 prog_clk[0]:317 prog_clk[0]:316 0.0004107143 +305 prog_clk[0]:313 prog_clk[0]:312 0.0004107143 +306 prog_clk[0]:218 prog_clk[0]:217 0.0004107143 +307 prog_clk[0]:233 prog_clk[0]:232 0.0008214285 +308 prog_clk[0]:233 prog_clk[0]:229 0.004805804 +309 prog_clk[0]:152 prog_clk[0]:151 0.002388393 +310 prog_clk[0]:271 prog_clk[0]:270 0.0004107143 +311 prog_clk[0]:264 prog_clk[0]:263 0.0003705357 +312 prog_clk[0]:263 prog_clk[0]:262 0.00019375 +313 prog_clk[0]:263 prog_clk[0]:259 0.002377232 +314 prog_clk[0]:101 prog_clk[0]:100 0.0003603333 +315 prog_clk[0]:238 prog_clk[0]:237 0.0001429583 +316 prog_clk[0]:276 prog_clk[0]:275 0.001151892 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0005277042 //LENGTH 3.880 LUMPCC 0.0001005093 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_0_:X O *L 0 *C 35.245 14.280 +*I mux_bottom_track_7\/mux_l2_in_0_:A1 I *L 0.00198 *C 36.705 12.580 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 36.705 12.580 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.800 12.625 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.800 14.235 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.755 14.280 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 35.282 14.280 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.871611e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.011453e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 7.011453e-05 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001281248 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001281248 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.025467e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.025467e-05 + +*RES +0 mux_bottom_track_7\/mux_l1_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_7\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0014375 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001165453 //LENGTH 7.355 LUMPCC 0.0004391806 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_0_:X O *L 0 *C 24.555 50.320 +*I mux_bottom_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 17.940 50.660 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 17.940 50.660 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 17.940 50.320 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 24.518 50.320 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.232649e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003489348 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003230112 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_36_[0]:13 8.058533e-05 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_left_grid_pin_36_[0]:14 8.058533e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[16]:2 0.000139005 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 chanx_left_in[16]:3 0.000139005 + +*RES +0 mux_bottom_track_25\/mux_l1_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005872768 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003884915 //LENGTH 2.865 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_15\/mux_l1_in_0_:X O *L 0 *C 34.785 61.540 +*I mux_bottom_track_15\/mux_l2_in_0_:A1 I *L 0.00198 *C 37.360 61.540 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 37.323 61.540 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 34.823 61.540 + +*CAP +0 mux_bottom_track_15\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_15\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001932458 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001932458 + +*RES +0 mux_bottom_track_15\/mux_l1_in_0_:X mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_15\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002232143 + +*END + +*D_NET mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003278429 //LENGTH 26.350 LUMPCC 0.000993975 DR + +*CONN +*I mux_bottom_track_19\/mux_l2_in_0_:X O *L 0 *C 48.125 25.840 +*I mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 49.855 4.260 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 49.280 23.120 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 48.970 11.560 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 49.855 4.260 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 49.680 4.420 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 49.680 4.465 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 49.680 11.503 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 49.678 11.560 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 49.680 11.568 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 49.680 23.113 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 49.680 23.120 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 49.680 23.178 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 49.680 25.795 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 49.635 25.840 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 48.163 25.840 + +*CAP +0 mux_bottom_track_19\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.801936e-05 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 8.816573e-05 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.427462e-05 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 5.455321e-05 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004153286 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004153286 +8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 8.816573e-05 +9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0003171646 +10 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0003171646 +11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.801936e-05 +12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 9.441646e-05 +13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 9.441646e-05 +14 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0001137184 +15 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0001137184 +16 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 bottom_left_grid_pin_39_[0]:17 7.167099e-07 +17 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 bottom_left_grid_pin_39_[0]:18 0.0001346392 +18 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 bottom_left_grid_pin_39_[0]:19 0.0001346392 +19 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 bottom_left_grid_pin_39_[0]:16 7.167099e-07 +20 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_tree_tapbuf_size2_4_sram[1]:6 1.141311e-05 +21 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_tree_tapbuf_size2_4_sram[1]:7 1.141311e-05 +22 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_tree_tapbuf_size2_4_sram[1]:8 6.245199e-05 +23 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_tree_tapbuf_size2_4_sram[1]:9 2.357738e-05 +24 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_tree_tapbuf_size2_4_sram[1]:5 6.245199e-05 +25 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_tree_tapbuf_size2_4_sram[1]:8 2.357738e-05 +26 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0002569379 +27 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0002569379 +28 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 7.251165e-06 +29 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 7.251165e-06 + +*RES +0 mux_bottom_track_19\/mux_l2_in_0_:X mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.152 +1 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.001314732 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0045 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.002337054 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.00341 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.69697e-05 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.001808717 +8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001039141 +10 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.006283483 +12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.51087e-05 +13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +14 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002730542 //LENGTH 22.605 LUMPCC 0.0003425247 DR + +*CONN +*I mux_bottom_track_35\/mux_l1_in_0_:X O *L 0 *C 37.085 36.040 +*I mux_bottom_track_35\/mux_l2_in_0_:A1 I *L 0.00198 *C 51.620 28.900 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 51.583 28.900 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 51.105 28.900 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 51.060 28.945 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 51.060 35.995 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 51.015 36.040 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 37.123 36.040 + +*CAP +0 mux_bottom_track_35\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_35\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.286961e-05 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.286961e-05 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003883113 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003883113 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0007518278 +7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0007518278 +8 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_11_sram[0]:7 0.0001712623 +9 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_11_sram[0]:6 0.0001712623 + +*RES +0 mux_bottom_track_35\/mux_l1_in_0_:X mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_35\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294643 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01240402 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01155959 //LENGTH 92.925 LUMPCC 0.005001873 DR + +*CONN +*I mux_left_track_1\/mux_l2_in_0_:X O *L 0 *C 90.335 59.160 +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 13.055 66.490 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 13.055 66.490 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 13.755 66.640 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 13.800 66.685 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 13.800 69.983 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 13.808 70.040 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 63.635 70.040 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 90.153 70.040 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 90.160 69.983 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 90.160 59.205 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 90.160 59.160 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 90.335 59.160 + +*CAP +0 mux_left_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.260631e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.913609e-05 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000165645 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000165645 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001413457 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.002481295 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001067838 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004994912 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0004994912 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.59853e-05 +12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.512882e-05 +13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_bottom_in[7]:17 0.0005578871 +14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[7]:9 2.132059e-06 +15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[7]:13 2.780347e-05 +16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[7]:15 0.001218322 +17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[7]:16 1.207623e-05 +18 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[7]:10 2.132059e-06 +19 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[7]:14 2.780347e-05 +20 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[7]:16 0.001776209 +21 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[7]:17 1.207623e-05 +22 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_bottom_in[16]:16 4.236674e-05 +23 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_bottom_in[16]:17 2.986907e-05 +24 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[16]:15 0.0001386679 +25 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[16]:15 4.236674e-05 +26 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[16]:16 0.000168537 +27 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[7]:7 0.0004718123 +28 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[7]:6 0.0004718123 + +*RES +0 mux_left_track_1\/mux_l2_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 9.51087e-05 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.009622768 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.00341 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.004154408 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002944197 +7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000625 +9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.007806308 + +*END + +*D_NET chanx_left_out[15] 0.001742425 //LENGTH 10.680 LUMPCC 0.0002151234 DR + +*CONN +*I ropt_mt_inst_745:X O *L 0 *C 7.095 46.920 +*P chanx_left_out[15] O *L 0.7423 *C 1.230 44.880 +*N chanx_left_out[15]:2 *C 1.840 44.880 +*N chanx_left_out[15]:3 *C 1.840 44.200 +*N chanx_left_out[15]:4 *C 5.973 44.200 +*N chanx_left_out[15]:5 *C 5.980 44.258 +*N chanx_left_out[15]:6 *C 5.980 46.875 +*N chanx_left_out[15]:7 *C 6.025 46.920 +*N chanx_left_out[15]:8 *C 7.058 46.920 + +*CAP +0 ropt_mt_inst_745:X 1e-06 +1 chanx_left_out[15] 8.875981e-05 +2 chanx_left_out[15]:2 0.0001379424 +3 chanx_left_out[15]:3 0.0003848952 +4 chanx_left_out[15]:4 0.0003357126 +5 chanx_left_out[15]:5 0.0001961156 +6 chanx_left_out[15]:6 0.0001961156 +7 chanx_left_out[15]:7 9.338014e-05 +8 chanx_left_out[15]:8 9.338014e-05 +9 chanx_left_out[15]:4 ropt_net_130:10 0.0001075617 +10 chanx_left_out[15]:3 ropt_net_130:9 0.0001075617 + +*RES +0 ropt_mt_inst_745:X chanx_left_out[15]:8 0.152 +1 chanx_left_out[15]:8 chanx_left_out[15]:7 0.0009218751 +2 chanx_left_out[15]:7 chanx_left_out[15]:6 0.0045 +3 chanx_left_out[15]:6 chanx_left_out[15]:5 0.002337054 +4 chanx_left_out[15]:5 chanx_left_out[15]:4 0.00341 +5 chanx_left_out[15]:4 chanx_left_out[15]:3 0.000647425 +6 chanx_left_out[15]:2 chanx_left_out[15] 9.556666e-05 +7 chanx_left_out[15]:3 chanx_left_out[15]:2 0.0001065333 + +*END + +*D_NET ropt_net_133 0.001585121 //LENGTH 8.255 LUMPCC 0.0006956896 DR + +*CONN +*I ropt_mt_inst_735:X O *L 0 *C 7.095 64.600 +*I ropt_mt_inst_748:A I *L 0.001766 *C 3.220 66.640 +*N ropt_net_133:2 *C 3.183 66.640 +*N ropt_net_133:3 *C 2.805 66.640 +*N ropt_net_133:4 *C 2.760 66.595 +*N ropt_net_133:5 *C 2.760 66.017 +*N ropt_net_133:6 *C 2.768 65.960 +*N ropt_net_133:7 *C 6.893 65.960 +*N ropt_net_133:8 *C 6.900 65.903 +*N ropt_net_133:9 *C 6.900 64.645 +*N ropt_net_133:10 *C 6.900 64.600 +*N ropt_net_133:11 *C 7.095 64.600 + +*CAP +0 ropt_mt_inst_735:X 1e-06 +1 ropt_mt_inst_748:A 1e-06 +2 ropt_net_133:2 4.374533e-05 +3 ropt_net_133:3 4.374533e-05 +4 ropt_net_133:4 6.516781e-05 +5 ropt_net_133:5 6.516781e-05 +6 ropt_net_133:6 0.0001791614 +7 ropt_net_133:7 0.0001791614 +8 ropt_net_133:8 9.511201e-05 +9 ropt_net_133:9 9.511201e-05 +10 ropt_net_133:10 5.939607e-05 +11 ropt_net_133:11 6.166171e-05 +12 ropt_net_133:6 chanx_left_out[9] 0.0001036612 +13 ropt_net_133:7 chanx_left_out[9]:2 0.0001036612 +14 ropt_net_133:6 chanx_left_out[18] 0.0002441836 +15 ropt_net_133:7 chanx_left_out[18]:2 0.0002441836 + +*RES +0 ropt_mt_inst_735:X ropt_net_133:11 0.152 +1 ropt_net_133:2 ropt_mt_inst_748:A 0.152 +2 ropt_net_133:3 ropt_net_133:2 0.0003370536 +3 ropt_net_133:4 ropt_net_133:3 0.0045 +4 ropt_net_133:5 ropt_net_133:4 0.000515625 +5 ropt_net_133:6 ropt_net_133:5 0.00341 +6 ropt_net_133:8 ropt_net_133:7 0.00341 +7 ropt_net_133:7 ropt_net_133:6 0.00064625 +8 ropt_net_133:10 ropt_net_133:9 0.0045 +9 ropt_net_133:9 ropt_net_133:8 0.001122768 +10 ropt_net_133:11 ropt_net_133:10 0.0001059783 + +*END + +*D_NET ropt_net_136 0.00115781 //LENGTH 8.865 LUMPCC 0.0002076028 DR + +*CONN +*I ropt_mt_inst_741:X O *L 0 *C 7.000 57.800 +*I ropt_mt_inst_751:A I *L 0.001767 *C 3.220 55.760 +*N ropt_net_136:2 *C 3.183 55.760 +*N ropt_net_136:3 *C 2.345 55.760 +*N ropt_net_136:4 *C 2.300 55.760 +*N ropt_net_136:5 *C 2.300 57.755 +*N ropt_net_136:6 *C 2.345 57.800 +*N ropt_net_136:7 *C 6.963 57.800 + +*CAP +0 ropt_mt_inst_741:X 1e-06 +1 ropt_mt_inst_751:A 1e-06 +2 ropt_net_136:2 5.565592e-05 +3 ropt_net_136:3 5.565592e-05 +4 ropt_net_136:4 0.0001202985 +5 ropt_net_136:5 8.911062e-05 +6 ropt_net_136:6 0.0003137431 +7 ropt_net_136:7 0.0003137431 +8 ropt_net_136:2 ropt_net_126:8 2.155877e-05 +9 ropt_net_136:3 ropt_net_126:7 2.155877e-05 +10 ropt_net_136:4 ropt_net_126:5 6.916818e-05 +11 ropt_net_136:6 ropt_net_126:3 1.307443e-05 +12 ropt_net_136:5 ropt_net_126:4 6.916818e-05 +13 ropt_net_136:7 ropt_net_126:2 1.307443e-05 + +*RES +0 ropt_mt_inst_741:X ropt_net_136:7 0.152 +1 ropt_net_136:2 ropt_mt_inst_751:A 0.152 +2 ropt_net_136:3 ropt_net_136:2 0.0007477679 +3 ropt_net_136:4 ropt_net_136:3 0.0045 +4 ropt_net_136:6 ropt_net_136:5 0.0045 +5 ropt_net_136:5 ropt_net_136:4 0.00178125 +6 ropt_net_136:7 ropt_net_136:6 0.004122769 + +*END + +*D_NET chanx_left_out[18] 0.002106885 //LENGTH 13.490 LUMPCC 0.0004883672 DR + +*CONN +*I ropt_mt_inst_761:X O *L 0 *C 11.600 69.020 +*P chanx_left_out[18] O *L 0.7423 *C 1.305 66.640 +*N chanx_left_out[18]:2 *C 10.113 66.640 +*N chanx_left_out[18]:3 *C 10.120 66.698 +*N chanx_left_out[18]:4 *C 10.120 68.975 +*N chanx_left_out[18]:5 *C 10.165 69.020 +*N chanx_left_out[18]:6 *C 11.562 69.020 + +*CAP +0 ropt_mt_inst_761:X 1e-06 +1 chanx_left_out[18] 0.0005493762 +2 chanx_left_out[18]:2 0.0005493762 +3 chanx_left_out[18]:3 0.0001398633 +4 chanx_left_out[18]:4 0.0001398633 +5 chanx_left_out[18]:5 0.0001195194 +6 chanx_left_out[18]:6 0.0001195194 +7 chanx_left_out[18] ropt_net_133:6 0.0002441836 +8 chanx_left_out[18]:2 ropt_net_133:7 0.0002441836 + +*RES +0 ropt_mt_inst_761:X chanx_left_out[18]:6 0.152 +1 chanx_left_out[18]:3 chanx_left_out[18]:2 0.00341 +2 chanx_left_out[18]:2 chanx_left_out[18] 0.001379842 +3 chanx_left_out[18]:5 chanx_left_out[18]:4 0.0045 +4 chanx_left_out[18]:4 chanx_left_out[18]:3 0.002033482 +5 chanx_left_out[18]:6 chanx_left_out[18]:5 0.001247768 + +*END + +*D_NET ropt_net_127 0.001077816 //LENGTH 8.550 LUMPCC 0.0001943265 DR + +*CONN +*I BUFT_P_91:X O *L 0 *C 10.580 83.640 +*I ropt_mt_inst_742:A I *L 0.001766 *C 3.220 82.960 +*N ropt_net_127:2 *C 3.220 82.960 +*N ropt_net_127:3 *C 3.220 83.300 +*N ropt_net_127:4 *C 10.580 83.300 +*N ropt_net_127:5 *C 10.580 83.640 + +*CAP +0 BUFT_P_91:X 1e-06 +1 ropt_mt_inst_742:A 1e-06 +2 ropt_net_127:2 5.616077e-05 +3 ropt_net_127:3 0.0003859175 +4 ropt_net_127:4 0.0003851552 +5 ropt_net_127:5 5.425628e-05 +6 ropt_net_127:3 chanx_left_out[12]:5 9.716326e-05 +7 ropt_net_127:4 chanx_left_out[12]:6 9.716326e-05 + +*RES +0 BUFT_P_91:X ropt_net_127:5 0.152 +1 ropt_net_127:5 ropt_net_127:4 0.0003035715 +2 ropt_net_127:2 ropt_mt_inst_742:A 0.152 +3 ropt_net_127:3 ropt_net_127:2 0.0003035715 +4 ropt_net_127:4 ropt_net_127:3 0.006571429 + +*END + +*D_NET chany_bottom_in[2] 0.01555792 //LENGTH 117.625 LUMPCC 0.006239538 DR + +*CONN +*P chany_bottom_in[2] I *L 0.29796 *C 81.420 1.290 +*I BUFT_RR_46:A I *L 0.001776 *C 10.120 44.880 +*N chany_bottom_in[2]:2 *C 10.120 44.880 +*N chany_bottom_in[2]:3 *C 10.120 44.540 +*N chany_bottom_in[2]:4 *C 10.120 44.495 +*N chany_bottom_in[2]:5 *C 10.120 42.898 +*N chany_bottom_in[2]:6 *C 10.128 42.840 +*N chany_bottom_in[2]:7 *C 59.955 42.840 +*N chany_bottom_in[2]:8 *C 81.860 42.840 +*N chany_bottom_in[2]:9 *C 81.880 42.833 +*N chany_bottom_in[2]:10 *C 81.880 5.448 +*N chany_bottom_in[2]:11 *C 81.865 5.440 +*N chany_bottom_in[2]:12 *C 81.422 5.440 +*N chany_bottom_in[2]:13 *C 81.420 5.383 + +*CAP +0 chany_bottom_in[2] 0.0002469058 +1 BUFT_RR_46:A 1e-06 +2 chany_bottom_in[2]:2 6.595027e-05 +3 chany_bottom_in[2]:3 7.089524e-05 +4 chany_bottom_in[2]:4 0.0001054655 +5 chany_bottom_in[2]:5 0.0001054655 +6 chany_bottom_in[2]:6 0.001843971 +7 chany_bottom_in[2]:7 0.002901339 +8 chany_bottom_in[2]:8 0.001057368 +9 chany_bottom_in[2]:9 0.001295177 +10 chany_bottom_in[2]:10 0.001295177 +11 chany_bottom_in[2]:11 4.138084e-05 +12 chany_bottom_in[2]:12 4.138084e-05 +13 chany_bottom_in[2]:13 0.0002469058 +14 chany_bottom_in[2]:4 chany_bottom_in[6]:8 2.241439e-06 +15 chany_bottom_in[2]:5 chany_bottom_in[6]:9 2.241439e-06 +16 chany_bottom_in[2]:6 chany_bottom_in[6]:10 0.00107314 +17 chany_bottom_in[2]:6 chany_bottom_in[6]:11 3.586666e-05 +18 chany_bottom_in[2]:8 chany_bottom_in[6]:12 0.0004679178 +19 chany_bottom_in[2]:7 chany_bottom_in[6]:12 3.586666e-05 +20 chany_bottom_in[2]:7 chany_bottom_in[6]:11 0.001541057 +21 chany_bottom_in[2]:6 chany_bottom_in[14]:6 0.0002602187 +22 chany_bottom_in[2]:7 chany_bottom_in[14]:7 0.0002602187 +23 chany_bottom_in[2]:9 chany_bottom_in[11]:9 0.0005616221 +24 chany_bottom_in[2]:11 chany_bottom_in[11]:12 8.340258e-06 +25 chany_bottom_in[2]:10 chany_bottom_in[11]:10 0.0005616221 +26 chany_bottom_in[2]:12 chany_bottom_in[11]:11 8.340258e-06 +27 chany_bottom_in[2]:6 chanx_left_in[1] 0.0007104221 +28 chany_bottom_in[2]:7 chanx_left_in[1]:7 0.0007104221 + +*RES +0 chany_bottom_in[2] chany_bottom_in[2]:13 0.003654018 +1 chany_bottom_in[2]:2 BUFT_RR_46:A 0.152 +2 chany_bottom_in[2]:3 chany_bottom_in[2]:2 0.0001465517 +3 chany_bottom_in[2]:4 chany_bottom_in[2]:3 0.0045 +4 chany_bottom_in[2]:5 chany_bottom_in[2]:4 0.001426339 +5 chany_bottom_in[2]:6 chany_bottom_in[2]:5 0.00341 +6 chany_bottom_in[2]:8 chany_bottom_in[2]:7 0.003431783 +7 chany_bottom_in[2]:9 chany_bottom_in[2]:8 0.00341 +8 chany_bottom_in[2]:11 chany_bottom_in[2]:10 0.00341 +9 chany_bottom_in[2]:10 chany_bottom_in[2]:9 0.005856983 +10 chany_bottom_in[2]:13 chany_bottom_in[2]:12 0.00341 +11 chany_bottom_in[2]:12 chany_bottom_in[2]:11 6.499219e-05 +12 chany_bottom_in[2]:7 chany_bottom_in[2]:6 0.007806308 + +*END + +*D_NET chany_bottom_in[11] 0.0141207 //LENGTH 136.605 LUMPCC 0.004572932 DR + +*CONN +*P chany_bottom_in[11] I *L 0.29796 *C 86.480 1.290 +*I mux_left_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 30.360 79.900 +*N chany_bottom_in[11]:2 *C 30.398 79.900 +*N chany_bottom_in[11]:3 *C 31.235 79.900 +*N chany_bottom_in[11]:4 *C 31.280 79.855 +*N chany_bottom_in[11]:5 *C 31.280 77.578 +*N chany_bottom_in[11]:6 *C 31.288 77.520 +*N chany_bottom_in[11]:7 *C 79.100 77.520 +*N chany_bottom_in[11]:8 *C 79.120 77.513 +*N chany_bottom_in[11]:9 *C 79.120 52.555 +*N chany_bottom_in[11]:10 *C 79.120 2.728 +*N chany_bottom_in[11]:11 *C 79.140 2.720 +*N chany_bottom_in[11]:12 *C 86.473 2.720 +*N chany_bottom_in[11]:13 *C 86.480 2.663 + +*CAP +0 chany_bottom_in[11] 9.065633e-05 +1 mux_left_track_25\/mux_l1_in_0_:A1 1e-06 +2 chany_bottom_in[11]:2 8.030409e-05 +3 chany_bottom_in[11]:3 8.030409e-05 +4 chany_bottom_in[11]:4 0.0001319134 +5 chany_bottom_in[11]:5 0.0001319134 +6 chany_bottom_in[11]:6 0.001851409 +7 chany_bottom_in[11]:7 0.001851409 +8 chany_bottom_in[11]:8 0.0009093609 +9 chany_bottom_in[11]:9 0.002163176 +10 chany_bottom_in[11]:10 0.001253815 +11 chany_bottom_in[11]:11 0.0004559262 +12 chany_bottom_in[11]:12 0.0004559262 +13 chany_bottom_in[11]:13 9.065633e-05 +14 chany_bottom_in[11]:11 chany_bottom_in[2]:12 8.340258e-06 +15 chany_bottom_in[11]:10 chany_bottom_in[2]:10 0.0005616221 +16 chany_bottom_in[11]:12 chany_bottom_in[2]:11 8.340258e-06 +17 chany_bottom_in[11]:9 chany_bottom_in[2]:9 0.0005616221 +18 chany_bottom_in[11]:6 chany_bottom_in[16]:15 0.0003172933 +19 chany_bottom_in[11]:6 chany_bottom_in[16]:16 4.696229e-05 +20 chany_bottom_in[11]:7 chany_bottom_in[16]:16 0.0003172933 +21 chany_bottom_in[11]:7 chany_bottom_in[16]:17 4.696229e-05 +22 chany_bottom_in[11]:8 chany_bottom_in[16]:18 0.0003104578 +23 chany_bottom_in[11]:10 chany_bottom_in[16]:19 1.152764e-05 +24 chany_bottom_in[11]:10 chany_bottom_in[16]:20 0.0007190357 +25 chany_bottom_in[11]:9 chany_bottom_in[16]:18 1.152764e-05 +26 chany_bottom_in[11]:9 chany_bottom_in[16]:19 0.001029494 +27 chany_bottom_in[11]:6 chany_bottom_in[18]:13 0.0003112265 +28 chany_bottom_in[11]:7 chany_bottom_in[18]:14 0.0003112265 + +*RES +0 chany_bottom_in[11] chany_bottom_in[11]:13 0.001225447 +1 chany_bottom_in[11]:2 mux_left_track_25\/mux_l1_in_0_:A1 0.152 +2 chany_bottom_in[11]:3 chany_bottom_in[11]:2 0.0007477679 +3 chany_bottom_in[11]:4 chany_bottom_in[11]:3 0.0045 +4 chany_bottom_in[11]:5 chany_bottom_in[11]:4 0.002033482 +5 chany_bottom_in[11]:6 chany_bottom_in[11]:5 0.00341 +6 chany_bottom_in[11]:7 chany_bottom_in[11]:6 0.007490624 +7 chany_bottom_in[11]:8 chany_bottom_in[11]:7 0.00341 +8 chany_bottom_in[11]:11 chany_bottom_in[11]:10 0.00341 +9 chany_bottom_in[11]:10 chany_bottom_in[11]:9 0.007806308 +10 chany_bottom_in[11]:13 chany_bottom_in[11]:12 0.00341 +11 chany_bottom_in[11]:12 chany_bottom_in[11]:11 0.001148758 +12 chany_bottom_in[11]:9 chany_bottom_in[11]:8 0.003910008 + +*END + +*D_NET bottom_left_grid_pin_34_[0] 0.0126752 //LENGTH 84.980 LUMPCC 0.003777834 DR + +*CONN +*P bottom_left_grid_pin_34_[0] I *L 0.29796 *C 29.750 10.200 +*I mux_bottom_track_7\/mux_l1_in_0_:A1 I *L 0.00198 *C 33.120 14.620 +*I mux_bottom_track_11\/mux_l1_in_0_:A1 I *L 0.00198 *C 46.560 18.020 +*I mux_bottom_track_3\/mux_l1_in_0_:A1 I *L 0.00198 *C 23.825 30.940 +*I mux_bottom_track_27\/mux_l1_in_0_:A1 I *L 0.00198 *C 13.600 50.660 +*N bottom_left_grid_pin_34_[0]:5 *C 13.600 50.660 +*N bottom_left_grid_pin_34_[0]:6 *C 13.340 50.660 +*N bottom_left_grid_pin_34_[0]:7 *C 13.340 50.615 +*N bottom_left_grid_pin_34_[0]:8 *C 13.340 30.645 +*N bottom_left_grid_pin_34_[0]:9 *C 13.385 30.600 +*N bottom_left_grid_pin_34_[0]:10 *C 22.080 30.600 +*N bottom_left_grid_pin_34_[0]:11 *C 22.080 30.940 +*N bottom_left_grid_pin_34_[0]:12 *C 23.825 30.940 +*N bottom_left_grid_pin_34_[0]:13 *C 24.795 30.940 +*N bottom_left_grid_pin_34_[0]:14 *C 24.840 30.895 +*N bottom_left_grid_pin_34_[0]:15 *C 24.840 29.978 +*N bottom_left_grid_pin_34_[0]:16 *C 24.848 29.920 +*N bottom_left_grid_pin_34_[0]:17 *C 32.180 29.920 +*N bottom_left_grid_pin_34_[0]:18 *C 32.200 29.913 +*N bottom_left_grid_pin_34_[0]:19 *C 32.200 20.400 +*N bottom_left_grid_pin_34_[0]:20 *C 34.040 20.400 +*N bottom_left_grid_pin_34_[0]:21 *C 46.460 18.020 +*N bottom_left_grid_pin_34_[0]:22 *C 46.460 18.020 +*N bottom_left_grid_pin_34_[0]:23 *C 46.460 17.680 +*N bottom_left_grid_pin_34_[0]:24 *C 46.453 17.680 +*N bottom_left_grid_pin_34_[0]:25 *C 34.060 17.680 +*N bottom_left_grid_pin_34_[0]:26 *C 34.040 17.688 +*N bottom_left_grid_pin_34_[0]:27 *C 33.120 17.680 +*N bottom_left_grid_pin_34_[0]:28 *C 32.720 13.600 +*N bottom_left_grid_pin_34_[0]:29 *C 33.120 14.620 +*N bottom_left_grid_pin_34_[0]:30 *C 33.120 14.575 +*N bottom_left_grid_pin_34_[0]:31 *C 33.120 13.658 +*N bottom_left_grid_pin_34_[0]:32 *C 33.120 13.600 +*N bottom_left_grid_pin_34_[0]:33 *C 33.120 13.600 +*N bottom_left_grid_pin_34_[0]:34 *C 33.120 10.208 +*N bottom_left_grid_pin_34_[0]:35 *C 33.100 10.200 + +*CAP +0 bottom_left_grid_pin_34_[0] 0.0002555772 +1 mux_bottom_track_7\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_11\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_track_3\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_27\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_34_[0]:5 5.503956e-05 +6 bottom_left_grid_pin_34_[0]:6 6.227737e-05 +7 bottom_left_grid_pin_34_[0]:7 0.001151932 +8 bottom_left_grid_pin_34_[0]:8 0.001151932 +9 bottom_left_grid_pin_34_[0]:9 0.0005193534 +10 bottom_left_grid_pin_34_[0]:10 0.0005397101 +11 bottom_left_grid_pin_34_[0]:11 0.0001482378 +12 bottom_left_grid_pin_34_[0]:12 0.0002454823 +13 bottom_left_grid_pin_34_[0]:13 9.221644e-05 +14 bottom_left_grid_pin_34_[0]:14 7.860854e-05 +15 bottom_left_grid_pin_34_[0]:15 7.860854e-05 +16 bottom_left_grid_pin_34_[0]:16 0.0001765931 +17 bottom_left_grid_pin_34_[0]:17 0.0001765931 +18 bottom_left_grid_pin_34_[0]:18 0.0002432372 +19 bottom_left_grid_pin_34_[0]:19 0.000344886 +20 bottom_left_grid_pin_34_[0]:20 0.0001999339 +21 bottom_left_grid_pin_34_[0]:21 3.257199e-05 +22 bottom_left_grid_pin_34_[0]:22 4.673456e-05 +23 bottom_left_grid_pin_34_[0]:23 5.45792e-05 +24 bottom_left_grid_pin_34_[0]:24 0.0008368274 +25 bottom_left_grid_pin_34_[0]:25 0.0008368274 +26 bottom_left_grid_pin_34_[0]:26 0.0001357585 +27 bottom_left_grid_pin_34_[0]:27 0.0001975377 +28 bottom_left_grid_pin_34_[0]:28 0.0001135386 +29 bottom_left_grid_pin_34_[0]:29 3.706965e-05 +30 bottom_left_grid_pin_34_[0]:30 9.635322e-05 +31 bottom_left_grid_pin_34_[0]:31 9.635322e-05 +32 bottom_left_grid_pin_34_[0]:32 0.0001135386 +33 bottom_left_grid_pin_34_[0]:33 0.0003399702 +34 bottom_left_grid_pin_34_[0]:34 0.0001799058 +35 bottom_left_grid_pin_34_[0]:35 0.0002555772 +36 bottom_left_grid_pin_34_[0]:17 chany_bottom_in[5]:7 0.0004174792 +37 bottom_left_grid_pin_34_[0]:16 chany_bottom_in[5]:6 0.0004174792 +38 bottom_left_grid_pin_34_[0]:8 chany_bottom_in[14]:5 9.551924e-05 +39 bottom_left_grid_pin_34_[0]:7 chany_bottom_in[14]:4 9.551924e-05 +40 bottom_left_grid_pin_34_[0]:18 chany_bottom_in[14]:8 7.839109e-05 +41 bottom_left_grid_pin_34_[0]:26 chany_bottom_in[14]:9 6.725767e-05 +42 bottom_left_grid_pin_34_[0]:33 chany_bottom_in[14]:8 3.8771e-05 +43 bottom_left_grid_pin_34_[0]:33 chany_bottom_in[14]:9 4.570755e-05 +44 bottom_left_grid_pin_34_[0]:34 chany_bottom_in[14]:9 3.8771e-05 +45 bottom_left_grid_pin_34_[0]:19 chany_bottom_in[14]:9 7.839109e-05 +46 bottom_left_grid_pin_34_[0]:20 chany_bottom_in[14]:8 6.725767e-05 +47 bottom_left_grid_pin_34_[0]:27 chany_bottom_in[14]:8 4.570755e-05 +48 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_39_[0] 1.806593e-05 +49 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_39_[0]:31 1.455569e-05 +50 bottom_left_grid_pin_34_[0]:18 bottom_left_grid_pin_39_[0]:29 0.0004535991 +51 bottom_left_grid_pin_34_[0]:26 bottom_left_grid_pin_39_[0]:20 1.598291e-05 +52 bottom_left_grid_pin_34_[0]:26 bottom_left_grid_pin_39_[0]:30 2.498925e-05 +53 bottom_left_grid_pin_34_[0]:32 bottom_left_grid_pin_39_[0]:31 3.923384e-06 +54 bottom_left_grid_pin_34_[0]:33 bottom_left_grid_pin_39_[0]:29 1.406285e-05 +55 bottom_left_grid_pin_34_[0]:33 bottom_left_grid_pin_39_[0]:30 5.840218e-05 +56 bottom_left_grid_pin_34_[0]:35 bottom_left_grid_pin_39_[0]:20 1.455569e-05 +57 bottom_left_grid_pin_34_[0]:35 bottom_left_grid_pin_39_[0]:31 1.806593e-05 +58 bottom_left_grid_pin_34_[0]:34 bottom_left_grid_pin_39_[0]:30 1.406285e-05 +59 bottom_left_grid_pin_34_[0]:28 bottom_left_grid_pin_39_[0]:20 3.923384e-06 +60 bottom_left_grid_pin_34_[0]:19 bottom_left_grid_pin_39_[0]:30 0.0004535991 +61 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_39_[0]:29 2.498925e-05 +62 bottom_left_grid_pin_34_[0]:27 bottom_left_grid_pin_39_[0]:29 5.840218e-05 +63 bottom_left_grid_pin_34_[0]:27 bottom_left_grid_pin_39_[0]:31 1.598291e-05 +64 bottom_left_grid_pin_34_[0]:17 chanx_left_in[6]:6 0.0004174792 +65 bottom_left_grid_pin_34_[0]:16 chanx_left_in[6]:7 0.0004174792 +66 bottom_left_grid_pin_34_[0]:23 chanx_left_in[6]:4 2.587524e-06 +67 bottom_left_grid_pin_34_[0]:22 chanx_left_in[6]:5 2.587524e-06 +68 bottom_left_grid_pin_34_[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 9.985056e-05 +69 bottom_left_grid_pin_34_[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.399591e-06 +70 bottom_left_grid_pin_34_[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.49202e-05 +71 bottom_left_grid_pin_34_[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.399591e-06 +72 bottom_left_grid_pin_34_[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001018237 +73 bottom_left_grid_pin_34_[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.689334e-05 + +*RES +0 bottom_left_grid_pin_34_[0] bottom_left_grid_pin_34_[0]:35 0.0005248332 +1 bottom_left_grid_pin_34_[0]:9 bottom_left_grid_pin_34_[0]:8 0.0045 +2 bottom_left_grid_pin_34_[0]:8 bottom_left_grid_pin_34_[0]:7 0.01783036 +3 bottom_left_grid_pin_34_[0]:6 bottom_left_grid_pin_34_[0]:5 8.695653e-05 +4 bottom_left_grid_pin_34_[0]:7 bottom_left_grid_pin_34_[0]:6 0.0045 +5 bottom_left_grid_pin_34_[0]:5 mux_bottom_track_27\/mux_l1_in_0_:A1 0.152 +6 bottom_left_grid_pin_34_[0]:17 bottom_left_grid_pin_34_[0]:16 0.001148758 +7 bottom_left_grid_pin_34_[0]:18 bottom_left_grid_pin_34_[0]:17 0.00341 +8 bottom_left_grid_pin_34_[0]:15 bottom_left_grid_pin_34_[0]:14 0.0008191965 +9 bottom_left_grid_pin_34_[0]:16 bottom_left_grid_pin_34_[0]:15 0.00341 +10 bottom_left_grid_pin_34_[0]:13 bottom_left_grid_pin_34_[0]:12 0.0008660714 +11 bottom_left_grid_pin_34_[0]:14 bottom_left_grid_pin_34_[0]:13 0.0045 +12 bottom_left_grid_pin_34_[0]:25 bottom_left_grid_pin_34_[0]:24 0.001941492 +13 bottom_left_grid_pin_34_[0]:26 bottom_left_grid_pin_34_[0]:25 0.00341 +14 bottom_left_grid_pin_34_[0]:26 bottom_left_grid_pin_34_[0]:20 0.0004249583 +15 bottom_left_grid_pin_34_[0]:23 bottom_left_grid_pin_34_[0]:22 0.0001634615 +16 bottom_left_grid_pin_34_[0]:24 bottom_left_grid_pin_34_[0]:23 0.00341 +17 bottom_left_grid_pin_34_[0]:21 mux_bottom_track_11\/mux_l1_in_0_:A1 0.152 +18 bottom_left_grid_pin_34_[0]:22 bottom_left_grid_pin_34_[0]:21 0.0045 +19 bottom_left_grid_pin_34_[0]:32 bottom_left_grid_pin_34_[0]:31 0.00341 +20 bottom_left_grid_pin_34_[0]:32 bottom_left_grid_pin_34_[0]:28 5.69697e-05 +21 bottom_left_grid_pin_34_[0]:33 bottom_left_grid_pin_34_[0]:32 0.00341 +22 bottom_left_grid_pin_34_[0]:33 bottom_left_grid_pin_34_[0]:27 0.0006391999 +23 bottom_left_grid_pin_34_[0]:31 bottom_left_grid_pin_34_[0]:30 0.0008191965 +24 bottom_left_grid_pin_34_[0]:29 mux_bottom_track_7\/mux_l1_in_0_:A1 0.152 +25 bottom_left_grid_pin_34_[0]:30 bottom_left_grid_pin_34_[0]:29 0.0045 +26 bottom_left_grid_pin_34_[0]:12 mux_bottom_track_3\/mux_l1_in_0_:A1 0.152 +27 bottom_left_grid_pin_34_[0]:12 bottom_left_grid_pin_34_[0]:11 0.001558036 +28 bottom_left_grid_pin_34_[0]:35 bottom_left_grid_pin_34_[0]:34 0.00341 +29 bottom_left_grid_pin_34_[0]:34 bottom_left_grid_pin_34_[0]:33 0.0005314916 +30 bottom_left_grid_pin_34_[0]:10 bottom_left_grid_pin_34_[0]:9 0.007763393 +31 bottom_left_grid_pin_34_[0]:11 bottom_left_grid_pin_34_[0]:10 0.0003035715 +32 bottom_left_grid_pin_34_[0]:19 bottom_left_grid_pin_34_[0]:18 0.001490292 +33 bottom_left_grid_pin_34_[0]:20 bottom_left_grid_pin_34_[0]:19 0.0002882667 +34 bottom_left_grid_pin_34_[0]:27 bottom_left_grid_pin_34_[0]:26 0.0001441333 + +*END + +*D_NET bottom_left_grid_pin_37_[0] 0.008981442 //LENGTH 68.915 LUMPCC 0.001414278 DR + +*CONN +*P bottom_left_grid_pin_37_[0] I *L 0.29796 *C 29.818 3.400 +*I mux_bottom_track_1\/mux_l1_in_1_:A1 I *L 0.00198 *C 28.980 30.940 +*I mux_bottom_track_5\/mux_l1_in_1_:A1 I *L 0.00198 *C 31.185 34.340 +*I mux_bottom_track_33\/mux_l1_in_0_:A1 I *L 0.00198 *C 34.960 56.100 +*I mux_bottom_track_17\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.100 56.100 +*N bottom_left_grid_pin_37_[0]:5 *C 39.100 56.115 +*N bottom_left_grid_pin_37_[0]:6 *C 39.100 56.440 +*N bottom_left_grid_pin_37_[0]:7 *C 39.100 56.395 +*N bottom_left_grid_pin_37_[0]:8 *C 39.100 55.818 +*N bottom_left_grid_pin_37_[0]:9 *C 39.093 55.760 +*N bottom_left_grid_pin_37_[0]:10 *C 34.960 56.115 +*N bottom_left_grid_pin_37_[0]:11 *C 34.960 56.440 +*N bottom_left_grid_pin_37_[0]:12 *C 34.960 56.395 +*N bottom_left_grid_pin_37_[0]:13 *C 34.960 55.818 +*N bottom_left_grid_pin_37_[0]:14 *C 34.960 55.760 +*N bottom_left_grid_pin_37_[0]:15 *C 34.060 55.760 +*N bottom_left_grid_pin_37_[0]:16 *C 34.040 55.753 +*N bottom_left_grid_pin_37_[0]:17 *C 34.040 40.808 +*N bottom_left_grid_pin_37_[0]:18 *C 34.020 40.800 +*N bottom_left_grid_pin_37_[0]:19 *C 31.288 40.800 +*N bottom_left_grid_pin_37_[0]:20 *C 31.280 40.742 +*N bottom_left_grid_pin_37_[0]:21 *C 31.185 34.340 +*N bottom_left_grid_pin_37_[0]:22 *C 31.280 34.340 +*N bottom_left_grid_pin_37_[0]:23 *C 31.280 31.665 +*N bottom_left_grid_pin_37_[0]:24 *C 31.235 31.620 +*N bottom_left_grid_pin_37_[0]:25 *C 28.980 30.940 +*N bottom_left_grid_pin_37_[0]:26 *C 28.980 31.620 +*N bottom_left_grid_pin_37_[0]:27 *C 29.900 31.620 +*N bottom_left_grid_pin_37_[0]:28 *C 29.900 31.575 +*N bottom_left_grid_pin_37_[0]:29 *C 29.900 3.458 +*N bottom_left_grid_pin_37_[0]:30 *C 29.900 3.400 + +*CAP +0 bottom_left_grid_pin_37_[0] 2.673936e-05 +1 mux_bottom_track_1\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_5\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_33\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_17\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_37_[0]:5 3.464953e-05 +6 bottom_left_grid_pin_37_[0]:6 6.640842e-05 +7 bottom_left_grid_pin_37_[0]:7 5.693766e-05 +8 bottom_left_grid_pin_37_[0]:8 5.693766e-05 +9 bottom_left_grid_pin_37_[0]:9 0.0002733458 +10 bottom_left_grid_pin_37_[0]:10 3.606856e-05 +11 bottom_left_grid_pin_37_[0]:11 6.937477e-05 +12 bottom_left_grid_pin_37_[0]:12 6.646637e-05 +13 bottom_left_grid_pin_37_[0]:13 6.646637e-05 +14 bottom_left_grid_pin_37_[0]:14 0.000345689 +15 bottom_left_grid_pin_37_[0]:15 7.234318e-05 +16 bottom_left_grid_pin_37_[0]:16 0.0009590469 +17 bottom_left_grid_pin_37_[0]:17 0.0009590469 +18 bottom_left_grid_pin_37_[0]:18 0.0004062259 +19 bottom_left_grid_pin_37_[0]:19 0.0004062259 +20 bottom_left_grid_pin_37_[0]:20 0.0003857129 +21 bottom_left_grid_pin_37_[0]:21 2.947533e-05 +22 bottom_left_grid_pin_37_[0]:22 0.0005905982 +23 bottom_left_grid_pin_37_[0]:23 0.0001699475 +24 bottom_left_grid_pin_37_[0]:24 0.0001036997 +25 bottom_left_grid_pin_37_[0]:25 7.690916e-05 +26 bottom_left_grid_pin_37_[0]:26 0.0001060202 +27 bottom_left_grid_pin_37_[0]:27 0.0001983692 +28 bottom_left_grid_pin_37_[0]:28 0.0009868598 +29 bottom_left_grid_pin_37_[0]:29 0.0009868598 +30 bottom_left_grid_pin_37_[0]:30 2.673936e-05 +31 bottom_left_grid_pin_37_[0]:24 bottom_left_grid_pin_35_[0]:18 2.279782e-05 +32 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_35_[0]:12 1.706607e-06 +33 bottom_left_grid_pin_37_[0]:22 bottom_left_grid_pin_35_[0]:15 1.706607e-06 +34 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_35_[0]:17 2.279782e-05 +35 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_35_[0]:18 2.279782e-05 +36 bottom_left_grid_pin_37_[0]:28 bottom_left_grid_pin_35_[0]:15 1.608866e-05 +37 bottom_left_grid_pin_37_[0]:28 bottom_left_grid_pin_35_[0]:19 0.000643748 +38 bottom_left_grid_pin_37_[0]:29 bottom_left_grid_pin_35_[0]:16 1.608866e-05 +39 bottom_left_grid_pin_37_[0]:29 bottom_left_grid_pin_35_[0]:20 0.000643748 +40 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_35_[0]:17 2.279782e-05 + +*RES +0 bottom_left_grid_pin_37_[0] bottom_left_grid_pin_37_[0]:30 2.35e-05 +1 bottom_left_grid_pin_37_[0]:13 bottom_left_grid_pin_37_[0]:12 0.000515625 +2 bottom_left_grid_pin_37_[0]:14 bottom_left_grid_pin_37_[0]:13 0.00341 +3 bottom_left_grid_pin_37_[0]:14 bottom_left_grid_pin_37_[0]:9 0.000647425 +4 bottom_left_grid_pin_37_[0]:11 bottom_left_grid_pin_37_[0]:10 0.0001766304 +5 bottom_left_grid_pin_37_[0]:12 bottom_left_grid_pin_37_[0]:11 0.0045 +6 bottom_left_grid_pin_37_[0]:10 mux_bottom_track_33\/mux_l1_in_0_:A1 0.152 +7 bottom_left_grid_pin_37_[0]:25 mux_bottom_track_1\/mux_l1_in_1_:A1 0.152 +8 bottom_left_grid_pin_37_[0]:8 bottom_left_grid_pin_37_[0]:7 0.0005156249 +9 bottom_left_grid_pin_37_[0]:9 bottom_left_grid_pin_37_[0]:8 0.00341 +10 bottom_left_grid_pin_37_[0]:6 bottom_left_grid_pin_37_[0]:5 0.0001766304 +11 bottom_left_grid_pin_37_[0]:7 bottom_left_grid_pin_37_[0]:6 0.0045 +12 bottom_left_grid_pin_37_[0]:5 mux_bottom_track_17\/mux_l1_in_0_:A1 0.152 +13 bottom_left_grid_pin_37_[0]:24 bottom_left_grid_pin_37_[0]:23 0.0045 +14 bottom_left_grid_pin_37_[0]:23 bottom_left_grid_pin_37_[0]:22 0.002388393 +15 bottom_left_grid_pin_37_[0]:15 bottom_left_grid_pin_37_[0]:14 0.000141 +16 bottom_left_grid_pin_37_[0]:16 bottom_left_grid_pin_37_[0]:15 0.00341 +17 bottom_left_grid_pin_37_[0]:18 bottom_left_grid_pin_37_[0]:17 0.00341 +18 bottom_left_grid_pin_37_[0]:17 bottom_left_grid_pin_37_[0]:16 0.002341383 +19 bottom_left_grid_pin_37_[0]:20 bottom_left_grid_pin_37_[0]:19 0.00341 +20 bottom_left_grid_pin_37_[0]:19 bottom_left_grid_pin_37_[0]:18 0.0004280916 +21 bottom_left_grid_pin_37_[0]:21 mux_bottom_track_5\/mux_l1_in_1_:A1 0.152 +22 bottom_left_grid_pin_37_[0]:22 bottom_left_grid_pin_37_[0]:21 0.0045 +23 bottom_left_grid_pin_37_[0]:22 bottom_left_grid_pin_37_[0]:20 0.005716518 +24 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_37_[0]:26 0.0008214285 +25 bottom_left_grid_pin_37_[0]:27 bottom_left_grid_pin_37_[0]:24 0.001191964 +26 bottom_left_grid_pin_37_[0]:28 bottom_left_grid_pin_37_[0]:27 0.0045 +27 bottom_left_grid_pin_37_[0]:29 bottom_left_grid_pin_37_[0]:28 0.02510491 +28 bottom_left_grid_pin_37_[0]:30 bottom_left_grid_pin_37_[0]:29 0.00341 +29 bottom_left_grid_pin_37_[0]:26 bottom_left_grid_pin_37_[0]:25 0.0006071429 + +*END + +*D_NET bottom_left_grid_pin_40_[0] 0.01086854 //LENGTH 84.955 LUMPCC 0.000529087 DR + +*CONN +*P bottom_left_grid_pin_40_[0] I *L 0.29796 *C 29.750 12.920 +*I mux_bottom_track_7\/mux_l1_in_1_:A0 I *L 0.001631 *C 34.675 17.000 +*I mux_bottom_track_23\/mux_l1_in_0_:A1 I *L 0.00198 *C 91.540 20.060 +*I mux_bottom_track_39\/mux_l1_in_0_:A1 I *L 0.00198 *C 82.440 25.500 +*I mux_bottom_track_3\/mux_l1_in_1_:A0 I *L 0.001631 *C 33.870 26.180 +*N bottom_left_grid_pin_40_[0]:5 *C 33.870 26.180 +*N bottom_left_grid_pin_40_[0]:6 *C 33.580 26.180 +*N bottom_left_grid_pin_40_[0]:7 *C 33.580 26.135 +*N bottom_left_grid_pin_40_[0]:8 *C 82.403 25.500 +*N bottom_left_grid_pin_40_[0]:9 *C 91.540 20.060 +*N bottom_left_grid_pin_40_[0]:10 *C 91.540 20.105 +*N bottom_left_grid_pin_40_[0]:11 *C 91.540 25.115 +*N bottom_left_grid_pin_40_[0]:12 *C 91.495 25.160 +*N bottom_left_grid_pin_40_[0]:13 *C 81.880 25.160 +*N bottom_left_grid_pin_40_[0]:14 *C 81.880 25.500 +*N bottom_left_grid_pin_40_[0]:15 *C 81.880 25.500 +*N bottom_left_grid_pin_40_[0]:16 *C 81.880 25.160 +*N bottom_left_grid_pin_40_[0]:17 *C 81.873 25.160 +*N bottom_left_grid_pin_40_[0]:18 *C 33.587 25.160 +*N bottom_left_grid_pin_40_[0]:19 *C 33.580 25.160 +*N bottom_left_grid_pin_40_[0]:20 *C 34.638 17.000 +*N bottom_left_grid_pin_40_[0]:21 *C 33.625 17.000 +*N bottom_left_grid_pin_40_[0]:22 *C 33.580 17.000 +*N bottom_left_grid_pin_40_[0]:23 *C 33.580 12.978 +*N bottom_left_grid_pin_40_[0]:24 *C 33.573 12.920 + +*CAP +0 bottom_left_grid_pin_40_[0] 0.0003221852 +1 mux_bottom_track_7\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_23\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_track_39\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_3\/mux_l1_in_1_:A0 1e-06 +5 bottom_left_grid_pin_40_[0]:5 4.893675e-05 +6 bottom_left_grid_pin_40_[0]:6 5.428171e-05 +7 bottom_left_grid_pin_40_[0]:7 5.733161e-05 +8 bottom_left_grid_pin_40_[0]:8 7.36198e-05 +9 bottom_left_grid_pin_40_[0]:9 3.298774e-05 +10 bottom_left_grid_pin_40_[0]:10 0.0002944272 +11 bottom_left_grid_pin_40_[0]:11 0.0002944272 +12 bottom_left_grid_pin_40_[0]:12 0.0006045426 +13 bottom_left_grid_pin_40_[0]:13 0.0006341476 +14 bottom_left_grid_pin_40_[0]:14 0.0001032248 +15 bottom_left_grid_pin_40_[0]:15 6.012485e-05 +16 bottom_left_grid_pin_40_[0]:16 6.396876e-05 +17 bottom_left_grid_pin_40_[0]:17 0.002863529 +18 bottom_left_grid_pin_40_[0]:18 0.002863529 +19 bottom_left_grid_pin_40_[0]:19 0.0005065475 +20 bottom_left_grid_pin_40_[0]:20 9.375765e-05 +21 bottom_left_grid_pin_40_[0]:21 9.375765e-05 +22 bottom_left_grid_pin_40_[0]:22 0.0006992925 +23 bottom_left_grid_pin_40_[0]:23 0.0002486504 +24 bottom_left_grid_pin_40_[0]:24 0.0003221852 +25 bottom_left_grid_pin_40_[0]:12 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 6.855464e-05 +26 bottom_left_grid_pin_40_[0]:13 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 6.855464e-05 +27 bottom_left_grid_pin_40_[0]:18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001959889 +28 bottom_left_grid_pin_40_[0]:17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001959889 + +*RES +0 bottom_left_grid_pin_40_[0] bottom_left_grid_pin_40_[0]:24 0.0005988583 +1 bottom_left_grid_pin_40_[0]:9 mux_bottom_track_23\/mux_l1_in_0_:A1 0.152 +2 bottom_left_grid_pin_40_[0]:10 bottom_left_grid_pin_40_[0]:9 0.0045 +3 bottom_left_grid_pin_40_[0]:12 bottom_left_grid_pin_40_[0]:11 0.0045 +4 bottom_left_grid_pin_40_[0]:11 bottom_left_grid_pin_40_[0]:10 0.004473215 +5 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_40_[0]:18 0.00341 +6 bottom_left_grid_pin_40_[0]:19 bottom_left_grid_pin_40_[0]:7 0.0008705358 +7 bottom_left_grid_pin_40_[0]:18 bottom_left_grid_pin_40_[0]:17 0.007564649 +8 bottom_left_grid_pin_40_[0]:16 bottom_left_grid_pin_40_[0]:15 0.0001634615 +9 bottom_left_grid_pin_40_[0]:17 bottom_left_grid_pin_40_[0]:16 0.00341 +10 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_40_[0]:13 0.0003035715 +11 bottom_left_grid_pin_40_[0]:14 bottom_left_grid_pin_40_[0]:8 0.0004665179 +12 bottom_left_grid_pin_40_[0]:15 bottom_left_grid_pin_40_[0]:14 0.0045 +13 bottom_left_grid_pin_40_[0]:6 bottom_left_grid_pin_40_[0]:5 0.0001576087 +14 bottom_left_grid_pin_40_[0]:7 bottom_left_grid_pin_40_[0]:6 0.0045 +15 bottom_left_grid_pin_40_[0]:5 mux_bottom_track_3\/mux_l1_in_1_:A0 0.152 +16 bottom_left_grid_pin_40_[0]:8 mux_bottom_track_39\/mux_l1_in_0_:A1 0.152 +17 bottom_left_grid_pin_40_[0]:21 bottom_left_grid_pin_40_[0]:20 0.0009040179 +18 bottom_left_grid_pin_40_[0]:22 bottom_left_grid_pin_40_[0]:21 0.0045 +19 bottom_left_grid_pin_40_[0]:22 bottom_left_grid_pin_40_[0]:19 0.007285715 +20 bottom_left_grid_pin_40_[0]:20 mux_bottom_track_7\/mux_l1_in_1_:A0 0.152 +21 bottom_left_grid_pin_40_[0]:23 bottom_left_grid_pin_40_[0]:22 0.003591519 +22 bottom_left_grid_pin_40_[0]:24 bottom_left_grid_pin_40_[0]:23 0.00341 +23 bottom_left_grid_pin_40_[0]:13 bottom_left_grid_pin_40_[0]:12 0.008584822 + +*END + +*D_NET chanx_left_in[3] 0.007062011 //LENGTH 46.540 LUMPCC 0.002124315 DR + +*CONN +*P chanx_left_in[3] I *L 0.29796 *C 1.230 61.200 +*I mux_bottom_track_5\/mux_l1_in_2_:A0 I *L 0.001631 *C 26.855 42.500 +*N chanx_left_in[3]:2 *C 25.360 42.160 +*N chanx_left_in[3]:3 *C 26.818 42.500 +*N chanx_left_in[3]:4 *C 25.805 42.500 +*N chanx_left_in[3]:5 *C 25.760 42.500 +*N chanx_left_in[3]:6 *C 25.760 42.160 +*N chanx_left_in[3]:7 *C 25.760 42.160 +*N chanx_left_in[3]:8 *C 25.760 42.168 +*N chanx_left_in[3]:9 *C 25.760 61.193 +*N chanx_left_in[3]:10 *C 25.740 61.200 + +*CAP +0 chanx_left_in[3] 0.0009903266 +1 mux_bottom_track_5\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[3]:2 0.0001267268 +3 chanx_left_in[3]:3 9.326014e-05 +4 chanx_left_in[3]:4 9.326014e-05 +5 chanx_left_in[3]:5 5.770547e-05 +6 chanx_left_in[3]:6 6.188611e-05 +7 chanx_left_in[3]:7 0.0001267268 +8 chanx_left_in[3]:8 0.001198239 +9 chanx_left_in[3]:9 0.001198239 +10 chanx_left_in[3]:10 0.0009903266 +11 chanx_left_in[3] chany_bottom_in[4]:17 0.0005376645 +12 chanx_left_in[3]:10 chany_bottom_in[4]:18 0.0005376645 +13 chanx_left_in[3] chanx_left_in[14]:11 0.0005244929 +14 chanx_left_in[3]:10 chanx_left_in[14]:10 0.0005244929 + +*RES +0 chanx_left_in[3] chanx_left_in[3]:10 0.0038399 +1 chanx_left_in[3]:3 mux_bottom_track_5\/mux_l1_in_2_:A0 0.152 +2 chanx_left_in[3]:4 chanx_left_in[3]:3 0.0009040179 +3 chanx_left_in[3]:5 chanx_left_in[3]:4 0.0045 +4 chanx_left_in[3]:6 chanx_left_in[3]:5 0.0001634615 +5 chanx_left_in[3]:7 chanx_left_in[3]:6 0.00341 +6 chanx_left_in[3]:7 chanx_left_in[3]:2 5.69697e-05 +7 chanx_left_in[3]:8 chanx_left_in[3]:7 0.00341 +8 chanx_left_in[3]:10 chanx_left_in[3]:9 0.00341 +9 chanx_left_in[3]:9 chanx_left_in[3]:8 0.002980583 + +*END + +*D_NET chanx_left_in[6] 0.008423727 //LENGTH 60.805 LUMPCC 0.002056845 DR + +*CONN +*P chanx_left_in[6] I *L 0.29796 *C 1.298 31.280 +*I mux_bottom_track_11\/mux_l1_in_0_:A0 I *L 0.001631 *C 46.175 17.340 +*N chanx_left_in[6]:2 *C 46.138 17.340 +*N chanx_left_in[6]:3 *C 45.125 17.340 +*N chanx_left_in[6]:4 *C 45.080 17.385 +*N chanx_left_in[6]:5 *C 45.080 29.183 +*N chanx_left_in[6]:6 *C 45.073 29.240 +*N chanx_left_in[6]:7 *C 21.628 29.240 +*N chanx_left_in[6]:8 *C 21.620 29.240 +*N chanx_left_in[6]:9 *C 21.575 29.240 +*N chanx_left_in[6]:10 *C 2.345 29.240 +*N chanx_left_in[6]:11 *C 2.300 29.285 +*N chanx_left_in[6]:12 *C 2.300 31.280 +*N chanx_left_in[6]:13 *C 1.380 31.280 +*N chanx_left_in[6]:14 *C 1.380 31.280 + +*CAP +0 chanx_left_in[6] 2.743235e-05 +1 mux_bottom_track_11\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[6]:2 0.0001189004 +3 chanx_left_in[6]:3 0.0001189004 +4 chanx_left_in[6]:4 0.0005558069 +5 chanx_left_in[6]:5 0.0005558069 +6 chanx_left_in[6]:6 0.001165188 +7 chanx_left_in[6]:7 0.001165188 +8 chanx_left_in[6]:8 3.931489e-05 +9 chanx_left_in[6]:9 0.001120582 +10 chanx_left_in[6]:10 0.001120582 +11 chanx_left_in[6]:11 0.000106527 +12 chanx_left_in[6]:12 0.0001592248 +13 chanx_left_in[6]:13 8.499724e-05 +14 chanx_left_in[6]:14 2.743235e-05 +15 chanx_left_in[6]:7 bottom_left_grid_pin_34_[0]:16 0.0004174792 +16 chanx_left_in[6]:5 bottom_left_grid_pin_34_[0]:22 2.587524e-06 +17 chanx_left_in[6]:6 bottom_left_grid_pin_34_[0]:17 0.0004174792 +18 chanx_left_in[6]:4 bottom_left_grid_pin_34_[0]:23 2.587524e-06 +19 chanx_left_in[6]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001069524 +20 chanx_left_in[6]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001069524 +21 chanx_left_in[6]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.048867e-05 +22 chanx_left_in[6]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 2.416321e-05 +23 chanx_left_in[6]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 2.416321e-05 +24 chanx_left_in[6]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.048867e-05 +25 chanx_left_in[6]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0004667513 +26 chanx_left_in[6]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004667513 + +*RES +0 chanx_left_in[6] chanx_left_in[6]:14 2.35e-05 +1 chanx_left_in[6]:13 chanx_left_in[6]:12 0.0008214285 +2 chanx_left_in[6]:14 chanx_left_in[6]:13 0.00341 +3 chanx_left_in[6]:10 chanx_left_in[6]:9 0.01716965 +4 chanx_left_in[6]:11 chanx_left_in[6]:10 0.0045 +5 chanx_left_in[6]:9 chanx_left_in[6]:8 0.0045 +6 chanx_left_in[6]:8 chanx_left_in[6]:7 0.00341 +7 chanx_left_in[6]:7 chanx_left_in[6]:6 0.00367305 +8 chanx_left_in[6]:5 chanx_left_in[6]:4 0.01053348 +9 chanx_left_in[6]:6 chanx_left_in[6]:5 0.00341 +10 chanx_left_in[6]:3 chanx_left_in[6]:2 0.000904018 +11 chanx_left_in[6]:4 chanx_left_in[6]:3 0.0045 +12 chanx_left_in[6]:2 mux_bottom_track_11\/mux_l1_in_0_:A0 0.152 +13 chanx_left_in[6]:12 chanx_left_in[6]:11 0.00178125 + +*END + +*D_NET chanx_left_in[11] 0.0126029 //LENGTH 108.805 LUMPCC 0.002281626 DR + +*CONN +*P chanx_left_in[11] I *L 0.29796 *C 1.230 63.920 +*I mux_bottom_track_21\/mux_l1_in_0_:A0 I *L 0.001631 *C 65.495 21.080 +*N chanx_left_in[11]:2 *C 65.495 21.080 +*N chanx_left_in[11]:3 *C 65.320 21.080 +*N chanx_left_in[11]:4 *C 65.320 21.080 +*N chanx_left_in[11]:5 *C 65.312 21.080 +*N chanx_left_in[11]:6 *C 61.660 21.080 +*N chanx_left_in[11]:7 *C 61.640 21.088 +*N chanx_left_in[11]:8 *C 61.640 57.793 +*N chanx_left_in[11]:9 *C 61.620 57.800 +*N chanx_left_in[11]:10 *C 54.410 57.800 +*N chanx_left_in[11]:11 *C 4.620 57.800 +*N chanx_left_in[11]:12 *C 4.600 57.808 +*N chanx_left_in[11]:13 *C 4.600 63.913 +*N chanx_left_in[11]:14 *C 4.580 63.920 + +*CAP +0 chanx_left_in[11] 0.0002427866 +1 mux_bottom_track_21\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[11]:2 5.243028e-05 +3 chanx_left_in[11]:3 5.711027e-05 +4 chanx_left_in[11]:4 3.821832e-05 +5 chanx_left_in[11]:5 0.0002280995 +6 chanx_left_in[11]:6 0.0002280995 +7 chanx_left_in[11]:7 0.001216478 +8 chanx_left_in[11]:8 0.001216478 +9 chanx_left_in[11]:9 0.0004045713 +10 chanx_left_in[11]:10 0.002991602 +11 chanx_left_in[11]:11 0.002587031 +12 chanx_left_in[11]:12 0.0004072902 +13 chanx_left_in[11]:13 0.0004072902 +14 chanx_left_in[11]:14 0.0002427866 +15 chanx_left_in[11]:7 chany_bottom_in[4]:20 3.871718e-05 +16 chanx_left_in[11]:7 chany_bottom_in[4]:21 0.0003169044 +17 chanx_left_in[11]:9 chany_bottom_in[4]:18 3.35754e-05 +18 chanx_left_in[11]:8 chany_bottom_in[4]:19 3.871718e-05 +19 chanx_left_in[11]:8 chany_bottom_in[4]:20 0.0003169044 +20 chanx_left_in[11]:11 chany_bottom_in[4]:17 7.82489e-05 +21 chanx_left_in[11]:10 chany_bottom_in[4]:17 3.35754e-05 +22 chanx_left_in[11]:10 chany_bottom_in[4]:18 7.82489e-05 +23 chanx_left_in[11]:5 prog_clk[0]:244 7.414486e-06 +24 chanx_left_in[11]:5 prog_clk[0]:295 1.148049e-05 +25 chanx_left_in[11]:6 prog_clk[0]:295 7.414486e-06 +26 chanx_left_in[11]:6 prog_clk[0]:296 1.148049e-05 +27 chanx_left_in[11]:11 prog_clk[0]:70 4.830245e-05 +28 chanx_left_in[11]:11 prog_clk[0]:73 6.632268e-05 +29 chanx_left_in[11]:11 prog_clk[0]:74 7.879707e-05 +30 chanx_left_in[11]:11 prog_clk[0]:131 0.0001043003 +31 chanx_left_in[11]:10 prog_clk[0]:56 6.632268e-05 +32 chanx_left_in[11]:10 prog_clk[0]:69 4.830245e-05 +33 chanx_left_in[11]:10 prog_clk[0]:73 7.879707e-05 +34 chanx_left_in[11]:10 prog_clk[0]:132 0.0001043003 +35 chanx_left_in[11]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0003567499 +36 chanx_left_in[11]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0003567499 + +*RES +0 chanx_left_in[11] chanx_left_in[11]:14 0.0005248333 +1 chanx_left_in[11]:2 mux_bottom_track_21\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[11]:3 chanx_left_in[11]:2 9.51087e-05 +3 chanx_left_in[11]:4 chanx_left_in[11]:3 0.0045 +4 chanx_left_in[11]:5 chanx_left_in[11]:4 0.00341 +5 chanx_left_in[11]:6 chanx_left_in[11]:5 0.000572225 +6 chanx_left_in[11]:7 chanx_left_in[11]:6 0.00341 +7 chanx_left_in[11]:9 chanx_left_in[11]:8 0.00341 +8 chanx_left_in[11]:8 chanx_left_in[11]:7 0.00575045 +9 chanx_left_in[11]:11 chanx_left_in[11]:10 0.007800432 +10 chanx_left_in[11]:12 chanx_left_in[11]:11 0.00341 +11 chanx_left_in[11]:14 chanx_left_in[11]:13 0.00341 +12 chanx_left_in[11]:13 chanx_left_in[11]:12 0.0009564499 +13 chanx_left_in[11]:10 chanx_left_in[11]:9 0.001129567 + +*END + +*D_NET chanx_left_in[19] 0.0145929 //LENGTH 134.410 LUMPCC 0.003730894 DR + +*CONN +*P chanx_left_in[19] I *L 0.29796 *C 1.230 81.600 +*I mux_bottom_track_37\/mux_l1_in_0_:A0 I *L 0.001631 *C 73.775 22.780 +*N chanx_left_in[19]:2 *C 73.775 22.780 +*N chanx_left_in[19]:3 *C 74.060 22.780 +*N chanx_left_in[19]:4 *C 74.060 22.825 +*N chanx_left_in[19]:5 *C 74.060 72.620 +*N chanx_left_in[19]:6 *C 74.060 82.223 +*N chanx_left_in[19]:7 *C 74.053 82.280 +*N chanx_left_in[19]:8 *C 55.370 82.280 +*N chanx_left_in[19]:9 *C 5.520 82.280 +*N chanx_left_in[19]:10 *C 5.520 81.600 + +*CAP +0 chanx_left_in[19] 0.0003040215 +1 mux_bottom_track_37\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[19]:2 5.32403e-05 +3 chanx_left_in[19]:3 5.640235e-05 +4 chanx_left_in[19]:4 0.001984087 +5 chanx_left_in[19]:5 0.002336361 +6 chanx_left_in[19]:6 0.0003522738 +7 chanx_left_in[19]:7 0.0008441414 +8 chanx_left_in[19]:8 0.002679506 +9 chanx_left_in[19]:9 0.001891156 +10 chanx_left_in[19]:10 0.0003598127 +11 chanx_left_in[19]:4 chany_bottom_in[9]:14 0.0001451162 +12 chanx_left_in[19]:4 chany_bottom_in[9]:15 0.0005037216 +13 chanx_left_in[19]:6 chany_bottom_in[9]:13 0.0001372452 +14 chanx_left_in[19]:5 chany_bottom_in[9]:13 0.0001451162 +15 chanx_left_in[19]:5 chany_bottom_in[9]:14 0.0006409668 +16 chanx_left_in[19]:7 chany_bottom_in[12]:9 3.363187e-05 +17 chanx_left_in[19]:7 chany_bottom_in[12]:10 0.0001177244 +18 chanx_left_in[19]:9 chany_bottom_in[12]:8 0.0003892162 +19 chanx_left_in[19]:8 chany_bottom_in[12]:8 3.363187e-05 +20 chanx_left_in[19]:8 chany_bottom_in[12]:9 0.0005069406 +21 chanx_left_in[19]:7 chany_bottom_in[18]:14 2.819108e-05 +22 chanx_left_in[19]:9 chany_bottom_in[18]:13 0.0005106003 +23 chanx_left_in[19]:8 chany_bottom_in[18]:13 2.819108e-05 +24 chanx_left_in[19]:8 chany_bottom_in[18]:14 0.0005106003 + +*RES +0 chanx_left_in[19] chanx_left_in[19]:10 0.0006720999 +1 chanx_left_in[19]:2 mux_bottom_track_37\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[19]:3 chanx_left_in[19]:2 0.0001548913 +3 chanx_left_in[19]:4 chanx_left_in[19]:3 0.0045 +4 chanx_left_in[19]:6 chanx_left_in[19]:5 0.008573662 +5 chanx_left_in[19]:7 chanx_left_in[19]:6 0.00341 +6 chanx_left_in[19]:10 chanx_left_in[19]:9 0.0001065333 +7 chanx_left_in[19]:9 chanx_left_in[19]:8 0.007809833 +8 chanx_left_in[19]:5 chanx_left_in[19]:4 0.04445983 +9 chanx_left_in[19]:8 chanx_left_in[19]:7 0.002926925 + +*END + +*D_NET chany_bottom_out[2] 0.001152078 //LENGTH 8.985 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 47.900 4.420 +*P chany_bottom_out[2] O *L 0.7423 *C 52.440 1.290 +*N chany_bottom_out[2]:2 *C 52.440 4.715 +*N chany_bottom_out[2]:3 *C 52.395 4.760 +*N chany_bottom_out[2]:4 *C 47.840 4.760 +*N chany_bottom_out[2]:5 *C 47.900 4.420 + +*CAP +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[2] 0.0001993344 +2 chany_bottom_out[2]:2 0.0001993344 +3 chany_bottom_out[2]:3 0.0003373993 +4 chany_bottom_out[2]:4 0.0003636411 +5 chany_bottom_out[2]:5 5.136879e-05 + +*RES +0 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[2]:5 0.152 +1 chany_bottom_out[2]:5 chany_bottom_out[2]:4 0.0003035715 +2 chany_bottom_out[2]:3 chany_bottom_out[2]:2 0.0045 +3 chany_bottom_out[2]:2 chany_bottom_out[2] 0.003058036 +4 chany_bottom_out[2]:4 chany_bottom_out[2]:3 0.004066965 + +*END + +*D_NET chany_bottom_out[6] 0.001158683 //LENGTH 10.175 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 70.440 6.460 +*P chany_bottom_out[6] O *L 0.7423 *C 74.980 1.290 +*N chany_bottom_out[6]:2 *C 74.980 6.415 +*N chany_bottom_out[6]:3 *C 74.935 6.460 +*N chany_bottom_out[6]:4 *C 70.478 6.460 + +*CAP +0 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[6] 0.0002950974 +2 chany_bottom_out[6]:2 0.0002950974 +3 chany_bottom_out[6]:3 0.0002837439 +4 chany_bottom_out[6]:4 0.0002837439 + +*RES +0 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[6]:4 0.152 +1 chany_bottom_out[6]:4 chany_bottom_out[6]:3 0.003979911 +2 chany_bottom_out[6]:3 chany_bottom_out[6]:2 0.0045 +3 chany_bottom_out[6]:2 chany_bottom_out[6] 0.004575893 + +*END + +*D_NET chany_bottom_out[10] 0.001791994 //LENGTH 17.455 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 87.000 11.900 +*P chany_bottom_out[10] O *L 0.7423 *C 93.380 1.290 +*N chany_bottom_out[10]:2 *C 93.380 11.855 +*N chany_bottom_out[10]:3 *C 93.335 11.900 +*N chany_bottom_out[10]:4 *C 87.038 11.900 + +*CAP +0 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[10] 0.0005317046 +2 chany_bottom_out[10]:2 0.0005317046 +3 chany_bottom_out[10]:3 0.0003637922 +4 chany_bottom_out[10]:4 0.0003637922 + +*RES +0 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[10]:4 0.152 +1 chany_bottom_out[10]:4 chany_bottom_out[10]:3 0.005622768 +2 chany_bottom_out[10]:3 chany_bottom_out[10]:2 0.0045 +3 chany_bottom_out[10]:2 chany_bottom_out[10] 0.009433036 + +*END + +*D_NET chany_bottom_out[15] 0.001431411 //LENGTH 11.915 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 49.280 6.460 +*P chany_bottom_out[15] O *L 0.7423 *C 55.200 1.325 +*N chany_bottom_out[15]:2 *C 55.200 1.995 +*N chany_bottom_out[15]:3 *C 55.155 2.040 +*N chany_bottom_out[15]:4 *C 49.265 2.040 +*N chany_bottom_out[15]:5 *C 49.220 2.085 +*N chany_bottom_out[15]:6 *C 49.220 6.415 +*N chany_bottom_out[15]:7 *C 49.220 6.460 + +*CAP +0 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[15] 5.590504e-05 +2 chany_bottom_out[15]:2 5.590504e-05 +3 chany_bottom_out[15]:3 0.000378296 +4 chany_bottom_out[15]:4 0.000378296 +5 chany_bottom_out[15]:5 0.0002650437 +6 chany_bottom_out[15]:6 0.0002650437 +7 chany_bottom_out[15]:7 3.192165e-05 + +*RES +0 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[15]:7 0.152 +1 chany_bottom_out[15]:3 chany_bottom_out[15]:2 0.0045 +2 chany_bottom_out[15]:2 chany_bottom_out[15] 0.0005982143 +3 chany_bottom_out[15]:4 chany_bottom_out[15]:3 0.005258929 +4 chany_bottom_out[15]:5 chany_bottom_out[15]:4 0.0045 +5 chany_bottom_out[15]:7 chany_bottom_out[15]:6 0.0045 +6 chany_bottom_out[15]:6 chany_bottom_out[15]:5 0.003866072 + +*END + +*D_NET chanx_left_out[0] 0.003045057 //LENGTH 26.630 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 11.445 66.640 +*P chanx_left_out[0] O *L 0.7423 *C 1.230 80.240 +*N chanx_left_out[0]:2 *C 8.273 80.240 +*N chanx_left_out[0]:3 *C 8.280 80.183 +*N chanx_left_out[0]:4 *C 8.280 66.005 +*N chanx_left_out[0]:5 *C 8.325 65.960 +*N chanx_left_out[0]:6 *C 10.995 65.960 +*N chanx_left_out[0]:7 *C 11.040 66.005 +*N chanx_left_out[0]:8 *C 11.040 66.595 +*N chanx_left_out[0]:9 *C 11.062 66.640 +*N chanx_left_out[0]:10 *C 11.430 66.640 + +*CAP +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[0] 0.0004577197 +2 chanx_left_out[0]:2 0.0004577197 +3 chanx_left_out[0]:3 0.0007618782 +4 chanx_left_out[0]:4 0.0007618782 +5 chanx_left_out[0]:5 0.0001930996 +6 chanx_left_out[0]:6 0.0001930996 +7 chanx_left_out[0]:7 6.466296e-05 +8 chanx_left_out[0]:8 6.466296e-05 +9 chanx_left_out[0]:9 4.466802e-05 +10 chanx_left_out[0]:10 4.466802e-05 + +*RES +0 mux_left_track_1\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[0]:10 0.152 +1 chanx_left_out[0]:10 chanx_left_out[0]:9 0.0001997283 +2 chanx_left_out[0]:9 chanx_left_out[0]:8 0.0045 +3 chanx_left_out[0]:8 chanx_left_out[0]:7 0.0005267857 +4 chanx_left_out[0]:6 chanx_left_out[0]:5 0.002383928 +5 chanx_left_out[0]:7 chanx_left_out[0]:6 0.0045 +6 chanx_left_out[0]:5 chanx_left_out[0]:4 0.0045 +7 chanx_left_out[0]:4 chanx_left_out[0]:3 0.01265848 +8 chanx_left_out[0]:3 chanx_left_out[0]:2 0.00341 +9 chanx_left_out[0]:2 chanx_left_out[0] 0.001103325 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[0] 0.001648019 //LENGTH 12.135 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.095 15.715 +*I mux_bottom_track_11\/mux_l1_in_0_:S I *L 0.00357 *C 47.280 18.020 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 51.235 20.740 +*N mux_tree_tapbuf_size2_0_sram[0]:3 *C 51.235 20.740 +*N mux_tree_tapbuf_size2_0_sram[0]:4 *C 51.060 20.740 +*N mux_tree_tapbuf_size2_0_sram[0]:5 *C 51.060 20.695 +*N mux_tree_tapbuf_size2_0_sram[0]:6 *C 47.318 18.020 +*N mux_tree_tapbuf_size2_0_sram[0]:7 *C 51.015 18.020 +*N mux_tree_tapbuf_size2_0_sram[0]:8 *C 51.060 18.020 +*N mux_tree_tapbuf_size2_0_sram[0]:9 *C 51.060 15.685 +*N mux_tree_tapbuf_size2_0_sram[0]:10 *C 51.105 15.640 +*N mux_tree_tapbuf_size2_0_sram[0]:11 *C 53.095 15.715 + +*CAP +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_11\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_0_sram[0]:3 5.426354e-05 +4 mux_tree_tapbuf_size2_0_sram[0]:4 5.816883e-05 +5 mux_tree_tapbuf_size2_0_sram[0]:5 0.0001551066 +6 mux_tree_tapbuf_size2_0_sram[0]:6 0.0002687434 +7 mux_tree_tapbuf_size2_0_sram[0]:7 0.0002687434 +8 mux_tree_tapbuf_size2_0_sram[0]:8 0.0003241236 +9 mux_tree_tapbuf_size2_0_sram[0]:9 0.0001368273 +10 mux_tree_tapbuf_size2_0_sram[0]:10 0.0001634207 +11 mux_tree_tapbuf_size2_0_sram[0]:11 0.0002156215 + +*RES +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_0_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_0_sram[0]:11 mux_tree_tapbuf_size2_0_sram[0]:10 0.001776786 +2 mux_tree_tapbuf_size2_0_sram[0]:10 mux_tree_tapbuf_size2_0_sram[0]:9 0.0045 +3 mux_tree_tapbuf_size2_0_sram[0]:9 mux_tree_tapbuf_size2_0_sram[0]:8 0.002084822 +4 mux_tree_tapbuf_size2_0_sram[0]:4 mux_tree_tapbuf_size2_0_sram[0]:3 9.510871e-05 +5 mux_tree_tapbuf_size2_0_sram[0]:5 mux_tree_tapbuf_size2_0_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_0_sram[0]:3 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_0_sram[0]:7 mux_tree_tapbuf_size2_0_sram[0]:6 0.003301339 +8 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:7 0.0045 +9 mux_tree_tapbuf_size2_0_sram[0]:8 mux_tree_tapbuf_size2_0_sram[0]:5 0.002388393 +10 mux_tree_tapbuf_size2_0_sram[0]:6 mux_bottom_track_11\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_12_sram[1] 0.002347294 //LENGTH 20.090 LUMPCC 0.0002652349 DR + +*CONN +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 73.445 33.660 +*I mem_bottom_track_37\/FTB_19__34:A I *L 0.001746 *C 80.040 28.560 +*I mux_bottom_track_37\/mux_l2_in_0_:S I *L 0.00357 *C 81.520 23.800 +*N mux_tree_tapbuf_size2_12_sram[1]:3 *C 81.483 23.800 +*N mux_tree_tapbuf_size2_12_sram[1]:4 *C 81.005 23.800 +*N mux_tree_tapbuf_size2_12_sram[1]:5 *C 80.960 23.845 +*N mux_tree_tapbuf_size2_12_sram[1]:6 *C 80.078 28.560 +*N mux_tree_tapbuf_size2_12_sram[1]:7 *C 80.915 28.560 +*N mux_tree_tapbuf_size2_12_sram[1]:8 *C 80.960 28.560 +*N mux_tree_tapbuf_size2_12_sram[1]:9 *C 80.960 33.615 +*N mux_tree_tapbuf_size2_12_sram[1]:10 *C 80.915 33.660 +*N mux_tree_tapbuf_size2_12_sram[1]:11 *C 73.483 33.660 + +*CAP +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_37\/FTB_19__34:A 1e-06 +2 mux_bottom_track_37\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_12_sram[1]:3 6.360334e-05 +4 mux_tree_tapbuf_size2_12_sram[1]:4 6.360334e-05 +5 mux_tree_tapbuf_size2_12_sram[1]:5 0.0001734675 +6 mux_tree_tapbuf_size2_12_sram[1]:6 7.20637e-05 +7 mux_tree_tapbuf_size2_12_sram[1]:7 7.20637e-05 +8 mux_tree_tapbuf_size2_12_sram[1]:8 0.0005014309 +9 mux_tree_tapbuf_size2_12_sram[1]:9 0.000294268 +10 mux_tree_tapbuf_size2_12_sram[1]:10 0.0004192793 +11 mux_tree_tapbuf_size2_12_sram[1]:11 0.0004192793 +12 mux_tree_tapbuf_size2_12_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:5 0.0001285463 +13 mux_tree_tapbuf_size2_12_sram[1]:8 mux_tree_tapbuf_size2_6_sram[1]:6 4.071132e-06 +14 mux_tree_tapbuf_size2_12_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:5 4.071132e-06 +15 mux_tree_tapbuf_size2_12_sram[1]:5 mux_tree_tapbuf_size2_6_sram[1]:6 0.0001285463 + +*RES +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_12_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_12_sram[1]:6 mem_bottom_track_37\/FTB_19__34:A 0.152 +2 mux_tree_tapbuf_size2_12_sram[1]:7 mux_tree_tapbuf_size2_12_sram[1]:6 0.0007477679 +3 mux_tree_tapbuf_size2_12_sram[1]:8 mux_tree_tapbuf_size2_12_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size2_12_sram[1]:8 mux_tree_tapbuf_size2_12_sram[1]:5 0.004209822 +5 mux_tree_tapbuf_size2_12_sram[1]:10 mux_tree_tapbuf_size2_12_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_12_sram[1]:9 mux_tree_tapbuf_size2_12_sram[1]:8 0.004513393 +7 mux_tree_tapbuf_size2_12_sram[1]:11 mux_tree_tapbuf_size2_12_sram[1]:10 0.006636161 +8 mux_tree_tapbuf_size2_12_sram[1]:4 mux_tree_tapbuf_size2_12_sram[1]:3 0.0004263393 +9 mux_tree_tapbuf_size2_12_sram[1]:5 mux_tree_tapbuf_size2_12_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size2_12_sram[1]:3 mux_bottom_track_37\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_14_sram[1] 0.002027409 //LENGTH 17.695 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 82.185 50.320 +*I mem_left_track_1\/FTB_21__36:A I *L 0.001746 *C 81.880 53.040 +*I mux_left_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 91.180 57.800 +*N mux_tree_tapbuf_size2_14_sram[1]:3 *C 91.142 57.800 +*N mux_tree_tapbuf_size2_14_sram[1]:4 *C 81.925 57.800 +*N mux_tree_tapbuf_size2_14_sram[1]:5 *C 81.880 57.755 +*N mux_tree_tapbuf_size2_14_sram[1]:6 *C 81.880 53.040 +*N mux_tree_tapbuf_size2_14_sram[1]:7 *C 81.880 53.040 +*N mux_tree_tapbuf_size2_14_sram[1]:8 *C 81.880 50.365 +*N mux_tree_tapbuf_size2_14_sram[1]:9 *C 81.880 50.320 +*N mux_tree_tapbuf_size2_14_sram[1]:10 *C 82.185 50.320 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_1\/FTB_21__36:A 1e-06 +2 mux_left_track_1\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_14_sram[1]:3 0.0005688691 +4 mux_tree_tapbuf_size2_14_sram[1]:4 0.0005688691 +5 mux_tree_tapbuf_size2_14_sram[1]:5 0.0002409086 +6 mux_tree_tapbuf_size2_14_sram[1]:6 3.001064e-05 +7 mux_tree_tapbuf_size2_14_sram[1]:7 0.0003944815 +8 mux_tree_tapbuf_size2_14_sram[1]:8 0.0001296867 +9 mux_tree_tapbuf_size2_14_sram[1]:9 4.675948e-05 +10 mux_tree_tapbuf_size2_14_sram[1]:10 4.482379e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_14_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_14_sram[1]:4 mux_tree_tapbuf_size2_14_sram[1]:3 0.008229911 +2 mux_tree_tapbuf_size2_14_sram[1]:5 mux_tree_tapbuf_size2_14_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_14_sram[1]:3 mux_left_track_1\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_14_sram[1]:6 mem_left_track_1\/FTB_21__36:A 0.152 +5 mux_tree_tapbuf_size2_14_sram[1]:7 mux_tree_tapbuf_size2_14_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_14_sram[1]:7 mux_tree_tapbuf_size2_14_sram[1]:5 0.004209822 +7 mux_tree_tapbuf_size2_14_sram[1]:9 mux_tree_tapbuf_size2_14_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size2_14_sram[1]:8 mux_tree_tapbuf_size2_14_sram[1]:7 0.002388393 +9 mux_tree_tapbuf_size2_14_sram[1]:10 mux_tree_tapbuf_size2_14_sram[1]:9 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_16_sram[1] 0.004522597 //LENGTH 44.550 LUMPCC 0.0004350144 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 64.245 72.080 +*I mem_left_track_9\/FTB_23__38:A I *L 0.001746 *C 58.420 80.240 +*I mux_left_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 83.360 61.880 +*N mux_tree_tapbuf_size2_16_sram[1]:3 *C 83.260 61.880 +*N mux_tree_tapbuf_size2_16_sram[1]:4 *C 83.260 61.925 +*N mux_tree_tapbuf_size2_16_sram[1]:5 *C 83.260 72.035 +*N mux_tree_tapbuf_size2_16_sram[1]:6 *C 83.215 72.080 +*N mux_tree_tapbuf_size2_16_sram[1]:7 *C 58.458 80.240 +*N mux_tree_tapbuf_size2_16_sram[1]:8 *C 64.355 80.240 +*N mux_tree_tapbuf_size2_16_sram[1]:9 *C 64.400 80.195 +*N mux_tree_tapbuf_size2_16_sram[1]:10 *C 64.400 72.125 +*N mux_tree_tapbuf_size2_16_sram[1]:11 *C 64.445 72.080 +*N mux_tree_tapbuf_size2_16_sram[1]:12 *C 64.245 72.080 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_left_track_9\/FTB_23__38:A 1e-06 +2 mux_left_track_9\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_16_sram[1]:3 2.823178e-05 +4 mux_tree_tapbuf_size2_16_sram[1]:4 0.0004970427 +5 mux_tree_tapbuf_size2_16_sram[1]:5 0.0004970427 +6 mux_tree_tapbuf_size2_16_sram[1]:6 0.0007828267 +7 mux_tree_tapbuf_size2_16_sram[1]:7 0.000340556 +8 mux_tree_tapbuf_size2_16_sram[1]:8 0.000340556 +9 mux_tree_tapbuf_size2_16_sram[1]:9 0.0003820285 +10 mux_tree_tapbuf_size2_16_sram[1]:10 0.0003820285 +11 mux_tree_tapbuf_size2_16_sram[1]:11 0.0007948579 +12 mux_tree_tapbuf_size2_16_sram[1]:12 3.941174e-05 +13 mux_tree_tapbuf_size2_16_sram[1]:6 mux_tree_tapbuf_size2_16_sram[0]:8 0.0002117465 +14 mux_tree_tapbuf_size2_16_sram[1]:12 mux_tree_tapbuf_size2_16_sram[0]:7 5.760693e-06 +15 mux_tree_tapbuf_size2_16_sram[1]:11 mux_tree_tapbuf_size2_16_sram[0]:7 0.0002117465 +16 mux_tree_tapbuf_size2_16_sram[1]:11 mux_tree_tapbuf_size2_16_sram[0]:8 5.760693e-06 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_16_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_16_sram[1]:6 mux_tree_tapbuf_size2_16_sram[1]:5 0.0045 +2 mux_tree_tapbuf_size2_16_sram[1]:5 mux_tree_tapbuf_size2_16_sram[1]:4 0.009026786 +3 mux_tree_tapbuf_size2_16_sram[1]:3 mux_left_track_9\/mux_l2_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_16_sram[1]:4 mux_tree_tapbuf_size2_16_sram[1]:3 0.0045 +5 mux_tree_tapbuf_size2_16_sram[1]:12 mux_tree_tapbuf_size2_16_sram[1]:11 0.0001086957 +6 mux_tree_tapbuf_size2_16_sram[1]:11 mux_tree_tapbuf_size2_16_sram[1]:10 0.0045 +7 mux_tree_tapbuf_size2_16_sram[1]:11 mux_tree_tapbuf_size2_16_sram[1]:6 0.01675893 +8 mux_tree_tapbuf_size2_16_sram[1]:10 mux_tree_tapbuf_size2_16_sram[1]:9 0.007205357 +9 mux_tree_tapbuf_size2_16_sram[1]:8 mux_tree_tapbuf_size2_16_sram[1]:7 0.005265625 +10 mux_tree_tapbuf_size2_16_sram[1]:9 mux_tree_tapbuf_size2_16_sram[1]:8 0.0045 +11 mux_tree_tapbuf_size2_16_sram[1]:7 mem_left_track_9\/FTB_23__38:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[0] 0.001959345 //LENGTH 14.925 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 49.525 55.420 +*I mux_bottom_track_17\/mux_l1_in_0_:S I *L 0.00357 *C 40.480 55.930 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 53.535 55.420 +*N mux_tree_tapbuf_size2_3_sram[0]:3 *C 53.498 55.420 +*N mux_tree_tapbuf_size2_3_sram[0]:4 *C 40.480 55.930 +*N mux_tree_tapbuf_size2_3_sram[0]:5 *C 40.480 55.080 +*N mux_tree_tapbuf_size2_3_sram[0]:6 *C 44.620 55.080 +*N mux_tree_tapbuf_size2_3_sram[0]:7 *C 44.620 55.420 +*N mux_tree_tapbuf_size2_3_sram[0]:8 *C 49.525 55.420 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_17\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_3_sram[0]:3 0.0002678045 +4 mux_tree_tapbuf_size2_3_sram[0]:4 8.458547e-05 +5 mux_tree_tapbuf_size2_3_sram[0]:5 0.0003511251 +6 mux_tree_tapbuf_size2_3_sram[0]:6 0.0003217704 +7 mux_tree_tapbuf_size2_3_sram[0]:7 0.0003317943 +8 mux_tree_tapbuf_size2_3_sram[0]:8 0.0005992651 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_3_sram[0]:8 0.152 +1 mux_tree_tapbuf_size2_3_sram[0]:4 mux_bottom_track_17\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_3_sram[0]:3 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +3 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:7 0.004379464 +4 mux_tree_tapbuf_size2_3_sram[0]:8 mux_tree_tapbuf_size2_3_sram[0]:3 0.003546876 +5 mux_tree_tapbuf_size2_3_sram[0]:5 mux_tree_tapbuf_size2_3_sram[0]:4 0.0007589286 +6 mux_tree_tapbuf_size2_3_sram[0]:6 mux_tree_tapbuf_size2_3_sram[0]:5 0.003696429 +7 mux_tree_tapbuf_size2_3_sram[0]:7 mux_tree_tapbuf_size2_3_sram[0]:6 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[0] 0.003360189 //LENGTH 27.870 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.605 12.240 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 74.235 17.340 +*I mux_bottom_track_23\/mux_l1_in_0_:S I *L 0.00357 *C 90.260 19.720 +*N mux_tree_tapbuf_size2_6_sram[0]:3 *C 90.160 19.720 +*N mux_tree_tapbuf_size2_6_sram[0]:4 *C 90.160 19.675 +*N mux_tree_tapbuf_size2_6_sram[0]:5 *C 90.160 17.385 +*N mux_tree_tapbuf_size2_6_sram[0]:6 *C 90.115 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:7 *C 74.235 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:8 *C 74.565 17.340 +*N mux_tree_tapbuf_size2_6_sram[0]:9 *C 74.520 17.295 +*N mux_tree_tapbuf_size2_6_sram[0]:10 *C 74.520 12.625 +*N mux_tree_tapbuf_size2_6_sram[0]:11 *C 74.475 12.580 +*N mux_tree_tapbuf_size2_6_sram[0]:12 *C 72.220 12.580 +*N mux_tree_tapbuf_size2_6_sram[0]:13 *C 72.220 12.240 +*N mux_tree_tapbuf_size2_6_sram[0]:14 *C 71.642 12.240 + +*CAP +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_23\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_6_sram[0]:3 3.176277e-05 +4 mux_tree_tapbuf_size2_6_sram[0]:4 0.0001641128 +5 mux_tree_tapbuf_size2_6_sram[0]:5 0.0001641128 +6 mux_tree_tapbuf_size2_6_sram[0]:6 0.0009572968 +7 mux_tree_tapbuf_size2_6_sram[0]:7 5.34831e-05 +8 mux_tree_tapbuf_size2_6_sram[0]:8 0.0009834411 +9 mux_tree_tapbuf_size2_6_sram[0]:9 0.0002697948 +10 mux_tree_tapbuf_size2_6_sram[0]:10 0.0002697948 +11 mux_tree_tapbuf_size2_6_sram[0]:11 0.0001543665 +12 mux_tree_tapbuf_size2_6_sram[0]:12 0.0001782623 +13 mux_tree_tapbuf_size2_6_sram[0]:13 7.732821e-05 +14 mux_tree_tapbuf_size2_6_sram[0]:14 5.34324e-05 + +*RES +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_6_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_6_sram[0]:6 mux_tree_tapbuf_size2_6_sram[0]:5 0.0045 +2 mux_tree_tapbuf_size2_6_sram[0]:5 mux_tree_tapbuf_size2_6_sram[0]:4 0.002044643 +3 mux_tree_tapbuf_size2_6_sram[0]:3 mux_bottom_track_23\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size2_6_sram[0]:4 mux_tree_tapbuf_size2_6_sram[0]:3 0.0045 +5 mux_tree_tapbuf_size2_6_sram[0]:7 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:7 0.0001793479 +7 mux_tree_tapbuf_size2_6_sram[0]:8 mux_tree_tapbuf_size2_6_sram[0]:6 0.01388393 +8 mux_tree_tapbuf_size2_6_sram[0]:9 mux_tree_tapbuf_size2_6_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size2_6_sram[0]:11 mux_tree_tapbuf_size2_6_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_6_sram[0]:10 mux_tree_tapbuf_size2_6_sram[0]:9 0.004169643 +11 mux_tree_tapbuf_size2_6_sram[0]:14 mux_tree_tapbuf_size2_6_sram[0]:13 0.0005156251 +12 mux_tree_tapbuf_size2_6_sram[0]:13 mux_tree_tapbuf_size2_6_sram[0]:12 0.0003035715 +13 mux_tree_tapbuf_size2_6_sram[0]:12 mux_tree_tapbuf_size2_6_sram[0]:11 0.002013393 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[0] 0.001369279 //LENGTH 11.165 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 21.465 66.640 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 22.715 64.260 +*I mux_bottom_track_29\/mux_l1_in_0_:S I *L 0.00357 *C 27.240 67.320 +*N mux_tree_tapbuf_size2_8_sram[0]:3 *C 27.277 67.320 +*N mux_tree_tapbuf_size2_8_sram[0]:4 *C 27.600 67.320 +*N mux_tree_tapbuf_size2_8_sram[0]:5 *C 27.600 66.980 +*N mux_tree_tapbuf_size2_8_sram[0]:6 *C 22.540 66.980 +*N mux_tree_tapbuf_size2_8_sram[0]:7 *C 22.715 64.260 +*N mux_tree_tapbuf_size2_8_sram[0]:8 *C 22.540 64.260 +*N mux_tree_tapbuf_size2_8_sram[0]:9 *C 22.540 64.305 +*N mux_tree_tapbuf_size2_8_sram[0]:10 *C 22.540 66.595 +*N mux_tree_tapbuf_size2_8_sram[0]:11 *C 22.540 66.670 +*N mux_tree_tapbuf_size2_8_sram[0]:12 *C 21.503 66.640 + +*CAP +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_29\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_8_sram[0]:3 4.639147e-05 +4 mux_tree_tapbuf_size2_8_sram[0]:4 6.992569e-05 +5 mux_tree_tapbuf_size2_8_sram[0]:5 0.0003124387 +6 mux_tree_tapbuf_size2_8_sram[0]:6 0.00031806 +7 mux_tree_tapbuf_size2_8_sram[0]:7 5.098775e-05 +8 mux_tree_tapbuf_size2_8_sram[0]:8 5.458524e-05 +9 mux_tree_tapbuf_size2_8_sram[0]:9 0.0001667304 +10 mux_tree_tapbuf_size2_8_sram[0]:10 0.0001667304 +11 mux_tree_tapbuf_size2_8_sram[0]:11 0.0001047924 +12 mux_tree_tapbuf_size2_8_sram[0]:12 7.563692e-05 + +*RES +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_8_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_8_sram[0]:11 mux_tree_tapbuf_size2_8_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size2_8_sram[0]:11 mux_tree_tapbuf_size2_8_sram[0]:6 0.0002767857 +3 mux_tree_tapbuf_size2_8_sram[0]:10 mux_tree_tapbuf_size2_8_sram[0]:9 0.002044643 +4 mux_tree_tapbuf_size2_8_sram[0]:8 mux_tree_tapbuf_size2_8_sram[0]:7 9.51087e-05 +5 mux_tree_tapbuf_size2_8_sram[0]:9 mux_tree_tapbuf_size2_8_sram[0]:8 0.0045 +6 mux_tree_tapbuf_size2_8_sram[0]:7 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_8_sram[0]:12 mux_tree_tapbuf_size2_8_sram[0]:11 0.0009263393 +8 mux_tree_tapbuf_size2_8_sram[0]:3 mux_bottom_track_29\/mux_l1_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_8_sram[0]:6 mux_tree_tapbuf_size2_8_sram[0]:5 0.004517857 +10 mux_tree_tapbuf_size2_8_sram[0]:5 mux_tree_tapbuf_size2_8_sram[0]:4 0.0003035715 +11 mux_tree_tapbuf_size2_8_sram[0]:4 mux_tree_tapbuf_size2_8_sram[0]:3 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_13_ccff_tail[0] 0.0005406248 //LENGTH 4.100 LUMPCC 0.0001086104 DR + +*CONN +*I mem_bottom_track_39\/FTB_20__35:X O *L 0 *C 79.805 37.060 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 78.835 39.100 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 *C 78.835 39.100 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 *C 78.660 39.100 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 *C 78.660 39.055 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 *C 78.660 37.105 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 *C 78.705 37.060 +*N mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 *C 79.767 37.060 + +*CAP +0 mem_bottom_track_39\/FTB_20__35:X 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 4.607233e-05 +3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 5.032834e-05 +4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 0.0001137352 +5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 0.0001137352 +6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 5.307169e-05 +7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 5.307169e-05 +8 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 5.43052e-05 +9 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.43052e-05 + +*RES +0 mem_bottom_track_39\/FTB_20__35:X mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 0.0009486608 +2 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 0.001741072 +4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:2 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_1_ccff_tail[0] 0.0005309578 //LENGTH 4.110 LUMPCC 0.0001117822 DR + +*CONN +*I mem_bottom_track_13\/FTB_8__23:X O *L 0 *C 37.485 77.180 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.815 75.140 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 *C 38.815 75.140 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 *C 38.640 75.140 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 *C 38.640 75.185 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 *C 38.640 77.135 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 *C 38.595 77.180 +*N mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 *C 37.523 77.180 + +*CAP +0 mem_bottom_track_13\/FTB_8__23:X 1e-06 +1 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 4.63822e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 5.01047e-05 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.0001145277 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0001145277 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 4.581665e-05 +7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 4.581665e-05 +8 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_17_sram[0]:11 5.589111e-05 +9 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_17_sram[0]:10 5.589111e-05 + +*RES +0 mem_bottom_track_13\/FTB_8__23:X mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:4 0.001741072 +6 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 0.0009575893 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_6_ccff_tail[0] 0.004116832 //LENGTH 33.250 LUMPCC 0.0006136378 DR + +*CONN +*I mem_bottom_track_23\/FTB_13__28:X O *L 0 *C 89.475 27.880 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 71.475 42.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 *C 71.475 42.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 *C 71.760 42.500 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 *C 71.760 42.455 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 *C 71.760 27.925 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 *C 71.805 27.880 +*N mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 *C 89.438 27.880 + +*CAP +0 mem_bottom_track_23\/FTB_13__28:X 1e-06 +1 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 4.923427e-05 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 5.166889e-05 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.0006378105 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0006378105 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.001062335 +7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.001062335 +8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 chany_bottom_in[9]:14 0.0001136622 +9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 chany_bottom_in[9]:15 0.0001136622 +10 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 0.0001801414 +11 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 1.301526e-05 +12 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 0.0001801414 +13 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 1.301526e-05 + +*RES +0 mem_bottom_track_23\/FTB_13__28:X mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:2 0.0001114131 +3 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.01297321 +6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.0157433 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_0_ccff_tail[0] 0.0007256696 //LENGTH 5.660 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/FTB_5__20:X O *L 0 *C 49.905 12.920 +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 47.555 15.300 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 *C 47.593 15.300 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 *C 49.175 15.300 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 *C 49.220 15.255 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 *C 49.220 12.965 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 *C 49.265 12.920 +*N mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 *C 49.867 12.920 + +*CAP +0 mem_bottom_track_9\/FTB_5__20:X 1e-06 +1 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.0001300164 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0001300164 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.0001535823 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0001535823 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 7.823614e-05 +7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 7.823614e-05 + +*RES +0 mem_bottom_track_9\/FTB_5__20:X mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 0.0005379465 +2 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size3_mem_0_ccff_tail[0]:2 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[0] 0.00290283 //LENGTH 22.490 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.005 22.780 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.975 20.740 +*I mux_bottom_track_7\/mux_l1_in_0_:S I *L 0.00357 *C 34.400 14.960 +*I mux_bottom_track_7\/mux_l1_in_1_:S I *L 0.00357 *C 35.780 17.975 +*N mux_tree_tapbuf_size5_1_sram[0]:4 *C 35.780 17.975 +*N mux_tree_tapbuf_size5_1_sram[0]:5 *C 34.400 14.960 +*N mux_tree_tapbuf_size5_1_sram[0]:6 *C 34.500 15.005 +*N mux_tree_tapbuf_size5_1_sram[0]:7 *C 34.500 17.635 +*N mux_tree_tapbuf_size5_1_sram[0]:8 *C 34.545 17.680 +*N mux_tree_tapbuf_size5_1_sram[0]:9 *C 35.780 17.680 +*N mux_tree_tapbuf_size5_1_sram[0]:10 *C 36.800 17.680 +*N mux_tree_tapbuf_size5_1_sram[0]:11 *C 36.975 20.740 +*N mux_tree_tapbuf_size5_1_sram[0]:12 *C 36.800 20.740 +*N mux_tree_tapbuf_size5_1_sram[0]:13 *C 36.800 20.695 +*N mux_tree_tapbuf_size5_1_sram[0]:14 *C 36.800 18.405 +*N mux_tree_tapbuf_size5_1_sram[0]:15 *C 36.800 18.360 +*N mux_tree_tapbuf_size5_1_sram[0]:16 *C 39.975 18.360 +*N mux_tree_tapbuf_size5_1_sram[0]:17 *C 40.020 18.405 +*N mux_tree_tapbuf_size5_1_sram[0]:18 *C 40.020 22.735 +*N mux_tree_tapbuf_size5_1_sram[0]:19 *C 40.065 22.780 +*N mux_tree_tapbuf_size5_1_sram[0]:20 *C 43.968 22.780 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_7\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_7\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[0]:4 6.115837e-05 +5 mux_tree_tapbuf_size5_1_sram[0]:5 3.129325e-05 +6 mux_tree_tapbuf_size5_1_sram[0]:6 0.0001661381 +7 mux_tree_tapbuf_size5_1_sram[0]:7 0.0001661381 +8 mux_tree_tapbuf_size5_1_sram[0]:8 0.0001071741 +9 mux_tree_tapbuf_size5_1_sram[0]:9 0.0002029044 +10 mux_tree_tapbuf_size5_1_sram[0]:10 0.0001115919 +11 mux_tree_tapbuf_size5_1_sram[0]:11 5.095032e-05 +12 mux_tree_tapbuf_size5_1_sram[0]:12 5.582551e-05 +13 mux_tree_tapbuf_size5_1_sram[0]:13 0.0001561556 +14 mux_tree_tapbuf_size5_1_sram[0]:14 0.0001561556 +15 mux_tree_tapbuf_size5_1_sram[0]:15 0.0002775946 +16 mux_tree_tapbuf_size5_1_sram[0]:16 0.0002300891 +17 mux_tree_tapbuf_size5_1_sram[0]:17 0.0003130188 +18 mux_tree_tapbuf_size5_1_sram[0]:18 0.0003130188 +19 mux_tree_tapbuf_size5_1_sram[0]:19 0.0002498117 +20 mux_tree_tapbuf_size5_1_sram[0]:20 0.0002498117 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_1_sram[0]:20 0.152 +1 mux_tree_tapbuf_size5_1_sram[0]:8 mux_tree_tapbuf_size5_1_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size5_1_sram[0]:7 mux_tree_tapbuf_size5_1_sram[0]:6 0.002348215 +3 mux_tree_tapbuf_size5_1_sram[0]:5 mux_bottom_track_7\/mux_l1_in_0_:S 0.152 +4 mux_tree_tapbuf_size5_1_sram[0]:6 mux_tree_tapbuf_size5_1_sram[0]:5 0.0045 +5 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:14 0.0045 +6 mux_tree_tapbuf_size5_1_sram[0]:15 mux_tree_tapbuf_size5_1_sram[0]:10 0.0006071429 +7 mux_tree_tapbuf_size5_1_sram[0]:14 mux_tree_tapbuf_size5_1_sram[0]:13 0.002044643 +8 mux_tree_tapbuf_size5_1_sram[0]:12 mux_tree_tapbuf_size5_1_sram[0]:11 9.510871e-05 +9 mux_tree_tapbuf_size5_1_sram[0]:13 mux_tree_tapbuf_size5_1_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size5_1_sram[0]:11 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size5_1_sram[0]:16 mux_tree_tapbuf_size5_1_sram[0]:15 0.002834822 +12 mux_tree_tapbuf_size5_1_sram[0]:17 mux_tree_tapbuf_size5_1_sram[0]:16 0.0045 +13 mux_tree_tapbuf_size5_1_sram[0]:19 mux_tree_tapbuf_size5_1_sram[0]:18 0.0045 +14 mux_tree_tapbuf_size5_1_sram[0]:18 mux_tree_tapbuf_size5_1_sram[0]:17 0.003866071 +15 mux_tree_tapbuf_size5_1_sram[0]:20 mux_tree_tapbuf_size5_1_sram[0]:19 0.003484375 +16 mux_tree_tapbuf_size5_1_sram[0]:4 mux_bottom_track_7\/mux_l1_in_1_:S 0.152 +17 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:8 0.001102679 +18 mux_tree_tapbuf_size5_1_sram[0]:9 mux_tree_tapbuf_size5_1_sram[0]:4 0.0001271552 +19 mux_tree_tapbuf_size5_1_sram[0]:10 mux_tree_tapbuf_size5_1_sram[0]:9 0.0009107143 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[1] 0.003778827 //LENGTH 27.660 LUMPCC 0.0002798967 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 26.805 47.260 +*I mux_bottom_track_1\/mux_l2_in_0_:S I *L 0.00357 *C 22.180 34.680 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 17.665 42.500 +*I mux_bottom_track_1\/mux_l2_in_1_:S I *L 0.00357 *C 17.840 44.880 +*N mux_tree_tapbuf_size6_0_sram[1]:4 *C 17.840 44.880 +*N mux_tree_tapbuf_size6_0_sram[1]:5 *C 17.688 42.528 +*N mux_tree_tapbuf_size6_0_sram[1]:6 *C 17.940 42.840 +*N mux_tree_tapbuf_size6_0_sram[1]:7 *C 17.940 42.885 +*N mux_tree_tapbuf_size6_0_sram[1]:8 *C 17.940 44.495 +*N mux_tree_tapbuf_size6_0_sram[1]:9 *C 17.940 44.540 +*N mux_tree_tapbuf_size6_0_sram[1]:10 *C 19.320 44.540 +*N mux_tree_tapbuf_size6_0_sram[1]:11 *C 19.320 44.200 +*N mux_tree_tapbuf_size6_0_sram[1]:12 *C 22.080 34.680 +*N mux_tree_tapbuf_size6_0_sram[1]:13 *C 22.080 34.725 +*N mux_tree_tapbuf_size6_0_sram[1]:14 *C 22.080 41.140 +*N mux_tree_tapbuf_size6_0_sram[1]:15 *C 21.160 41.140 +*N mux_tree_tapbuf_size6_0_sram[1]:16 *C 21.160 44.155 +*N mux_tree_tapbuf_size6_0_sram[1]:17 *C 21.160 44.200 +*N mux_tree_tapbuf_size6_0_sram[1]:18 *C 25.715 44.200 +*N mux_tree_tapbuf_size6_0_sram[1]:19 *C 25.760 44.245 +*N mux_tree_tapbuf_size6_0_sram[1]:20 *C 25.760 47.215 +*N mux_tree_tapbuf_size6_0_sram[1]:21 *C 25.805 47.260 +*N mux_tree_tapbuf_size6_0_sram[1]:22 *C 26.805 47.260 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +3 mux_bottom_track_1\/mux_l2_in_1_:S 1e-06 +4 mux_tree_tapbuf_size6_0_sram[1]:4 6.382742e-05 +5 mux_tree_tapbuf_size6_0_sram[1]:5 3.046582e-05 +6 mux_tree_tapbuf_size6_0_sram[1]:6 7.200198e-05 +7 mux_tree_tapbuf_size6_0_sram[1]:7 0.0001318188 +8 mux_tree_tapbuf_size6_0_sram[1]:8 0.0001318188 +9 mux_tree_tapbuf_size6_0_sram[1]:9 0.0001705905 +10 mux_tree_tapbuf_size6_0_sram[1]:10 0.0001631057 +11 mux_tree_tapbuf_size6_0_sram[1]:11 0.0001785158 +12 mux_tree_tapbuf_size6_0_sram[1]:12 3.188194e-05 +13 mux_tree_tapbuf_size6_0_sram[1]:13 0.0002775496 +14 mux_tree_tapbuf_size6_0_sram[1]:14 0.000336692 +15 mux_tree_tapbuf_size6_0_sram[1]:15 0.0002648085 +16 mux_tree_tapbuf_size6_0_sram[1]:16 0.0002056662 +17 mux_tree_tapbuf_size6_0_sram[1]:17 0.0005054122 +18 mux_tree_tapbuf_size6_0_sram[1]:18 0.0003216777 +19 mux_tree_tapbuf_size6_0_sram[1]:19 0.0002130368 +20 mux_tree_tapbuf_size6_0_sram[1]:20 0.0002130368 +21 mux_tree_tapbuf_size6_0_sram[1]:21 7.519442e-05 +22 mux_tree_tapbuf_size6_0_sram[1]:22 0.0001078293 +23 mux_tree_tapbuf_size6_0_sram[1]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001399483 +24 mux_tree_tapbuf_size6_0_sram[1]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001399483 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_0_sram[1]:22 0.152 +1 mux_tree_tapbuf_size6_0_sram[1]:17 mux_tree_tapbuf_size6_0_sram[1]:16 0.0045 +2 mux_tree_tapbuf_size6_0_sram[1]:17 mux_tree_tapbuf_size6_0_sram[1]:11 0.001642857 +3 mux_tree_tapbuf_size6_0_sram[1]:16 mux_tree_tapbuf_size6_0_sram[1]:15 0.002691964 +4 mux_tree_tapbuf_size6_0_sram[1]:12 mux_bottom_track_1\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size6_0_sram[1]:13 mux_tree_tapbuf_size6_0_sram[1]:12 0.0045 +6 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size6_0_sram[1]:9 mux_tree_tapbuf_size6_0_sram[1]:4 0.0001847826 +8 mux_tree_tapbuf_size6_0_sram[1]:8 mux_tree_tapbuf_size6_0_sram[1]:7 0.0014375 +9 mux_tree_tapbuf_size6_0_sram[1]:6 mux_tree_tapbuf_size6_0_sram[1]:5 0.0002111487 +10 mux_tree_tapbuf_size6_0_sram[1]:7 mux_tree_tapbuf_size6_0_sram[1]:6 0.0045 +11 mux_tree_tapbuf_size6_0_sram[1]:5 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size6_0_sram[1]:4 mux_bottom_track_1\/mux_l2_in_1_:S 0.152 +13 mux_tree_tapbuf_size6_0_sram[1]:18 mux_tree_tapbuf_size6_0_sram[1]:17 0.004066965 +14 mux_tree_tapbuf_size6_0_sram[1]:19 mux_tree_tapbuf_size6_0_sram[1]:18 0.0045 +15 mux_tree_tapbuf_size6_0_sram[1]:21 mux_tree_tapbuf_size6_0_sram[1]:20 0.0045 +16 mux_tree_tapbuf_size6_0_sram[1]:20 mux_tree_tapbuf_size6_0_sram[1]:19 0.002651786 +17 mux_tree_tapbuf_size6_0_sram[1]:22 mux_tree_tapbuf_size6_0_sram[1]:21 0.0008928571 +18 mux_tree_tapbuf_size6_0_sram[1]:10 mux_tree_tapbuf_size6_0_sram[1]:9 0.001232143 +19 mux_tree_tapbuf_size6_0_sram[1]:11 mux_tree_tapbuf_size6_0_sram[1]:10 0.0003035715 +20 mux_tree_tapbuf_size6_0_sram[1]:15 mux_tree_tapbuf_size6_0_sram[1]:14 0.0008214285 +21 mux_tree_tapbuf_size6_0_sram[1]:14 mux_tree_tapbuf_size6_0_sram[1]:13 0.005727679 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0005111704 //LENGTH 3.675 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_2_:X O *L 0 *C 19.955 45.560 +*I mux_bottom_track_1\/mux_l2_in_1_:A1 I *L 0.00198 *C 17.020 45.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 17.020 45.220 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 17.020 45.560 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 19.918 45.560 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.354059e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0002410424 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0002145874 + +*RES +0 mux_bottom_track_1\/mux_l1_in_2_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.002587054 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_1\/mux_l2_in_1_:A1 0.152 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001060585 //LENGTH 6.770 LUMPCC 0.000483845 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_1_:X O *L 0 *C 29.615 34.340 +*I mux_bottom_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 30.995 39.100 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 30.958 39.100 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 29.945 39.100 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 29.900 39.055 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 29.900 34.385 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 29.900 34.340 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 29.615 34.340 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.336784e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.336784e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001698501 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001698501 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.512417e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.317966e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_35_[0]:12 0.0001251719 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_35_[0]:15 0.0001251719 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size6_1_sram[0]:7 6.649387e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size6_1_sram[0]:6 6.649387e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 5.02567e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 5.02567e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009040179 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001548913 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0] 0.002289936 //LENGTH 15.815 LUMPCC 0.0008773557 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_1_:X O *L 0 *C 28.805 38.760 +*I mux_bottom_track_5\/mux_l3_in_0_:A0 I *L 0.001631 *C 34.230 31.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 34.267 31.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 35.375 31.960 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 35.420 32.005 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 35.420 37.060 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 34.960 37.060 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 34.960 38.715 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 34.915 38.760 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 28.843 38.760 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001060864 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001060864 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001343145 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001660367 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.0001140187 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 8.229644e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0003508707 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0003508707 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 bottom_left_grid_pin_38_[0]:10 5.60732e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 bottom_left_grid_pin_38_[0]:13 6.488196e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 bottom_left_grid_pin_38_[0]:7 5.60732e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 bottom_left_grid_pin_38_[0]:10 6.488196e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:7 1.312233e-06 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:8 9.301902e-07 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_tree_tapbuf_size6_1_sram[1]:10 8.151542e-06 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:8 1.312233e-06 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:9 9.301902e-07 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_tree_tapbuf_size6_1_sram[1]:11 8.151542e-06 +20 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_tree_tapbuf_size6_1_sram[1]:12 2.810556e-06 +21 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size6_1_sram[1]:6 0.0001337402 +22 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_tree_tapbuf_size6_1_sram[1]:6 2.810556e-06 +23 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_tree_tapbuf_size6_1_sram[1]:12 0.0001337402 +24 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.02567e-05 +25 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.02567e-05 +26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 6.686604e-05 +27 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 6.686604e-05 +28 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.895881e-05 +29 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.696396e-06 +30 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 4.895881e-05 +31 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 4.696396e-06 + +*RES +0 mux_bottom_track_5\/mux_l2_in_1_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.005421876 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 0.001477679 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0009888393 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A0 0.152 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0004107143 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004513393 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0008374674 //LENGTH 6.650 LUMPCC 0.0002621055 DR + +*CONN +*I mux_bottom_track_7\/mux_l1_in_1_:X O *L 0 *C 36.625 17.000 +*I mux_bottom_track_7\/mux_l2_in_0_:A0 I *L 0.001631 *C 37.090 11.900 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 37.090 11.900 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 37.260 11.900 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 37.260 11.945 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 37.260 16.955 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 37.215 17.000 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 36.663 17.000 + +*CAP +0 mux_bottom_track_7\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_7\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.056341e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.196062e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001854353 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001854353 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.998367e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 5.998367e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size5_1_sram[1]:14 1.375019e-05 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_1_sram[1]:15 1.375019e-05 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:12 3.192791e-06 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:16 6.38551e-05 +12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:13 3.192791e-06 +13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:17 6.38551e-05 +14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.025467e-05 +15 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.025467e-05 + +*RES +0 mux_bottom_track_7\/mux_l1_in_1_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_7\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004473215 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004933036 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0] 0.01427128 //LENGTH 99.950 LUMPCC 0.005875923 DR + +*CONN +*I mux_bottom_track_25\/mux_l2_in_0_:X O *L 0 *C 20.065 49.640 +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 83.645 15.105 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 83.645 15.105 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 83.720 14.960 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 83.720 15.005 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 83.720 46.863 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 83.713 46.920 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 71.455 46.920 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 21.628 46.920 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 21.620 46.977 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 21.620 49.595 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 *C 21.575 49.640 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 *C 20.103 49.640 + +*CAP +0 mux_bottom_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.532991e-05 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 5.599071e-05 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.001482024 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.001482024 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006801104 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.002333091 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.00165298 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.0001745788 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0001745788 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.0001513243 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.0001513243 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 chanx_left_in[5] 0.001067668 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 chanx_left_in[5]:8 0.001067668 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size2_13_sram[1]:4 7.749569e-05 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size2_13_sram[1]:9 5.569008e-05 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size2_13_sram[1]:8 5.569008e-05 +18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size2_13_sram[1]:9 7.749569e-05 +19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size3_1_sram[0]:13 8.309686e-05 +20 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_tree_tapbuf_size3_1_sram[0]:17 0.001036471 +21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size3_1_sram[0]:18 9.009747e-05 +22 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size3_1_sram[0]:17 0.0001731943 +23 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size3_1_sram[0]:18 0.001036471 +24 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0003968434 +25 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0003968434 +26 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001305993 +27 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001305993 + +*RES +0 mux_bottom_track_25\/mux_l2_in_0_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 0.001314732 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.002337054 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.00341 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.007806308 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0284442 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00341 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.880435e-05 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.001920342 + +*END + +*D_NET mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001957563 //LENGTH 15.005 LUMPCC 0.00038729 DR + +*CONN +*I mux_bottom_track_19\/mux_l1_in_0_:X O *L 0 *C 40.305 33.320 +*I mux_bottom_track_19\/mux_l2_in_0_:A1 I *L 0.00198 *C 46.560 25.500 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 46.523 25.500 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 45.585 25.500 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 45.540 25.545 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 45.540 33.275 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 45.495 33.320 +*N mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 40.343 33.320 + +*CAP +0 mux_bottom_track_19\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_19\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001026327 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001026327 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003728774 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003728774 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003086263 +7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003086263 +8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:165 2.323058e-06 +9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 prog_clk[0]:166 5.076854e-06 +10 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 prog_clk[0]:160 7.929272e-05 +11 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:162 5.076854e-06 +12 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 prog_clk[0]:166 2.323058e-06 +13 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 prog_clk[0]:161 7.929272e-05 +14 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chanx_left_in[6]:4 0.0001069524 +15 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chanx_left_in[6]:5 0.0001069524 + +*RES +0 mux_bottom_track_19\/mux_l1_in_0_:X mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_19\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0008370536 +3 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.004600446 + +*END + +*D_NET mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01158055 //LENGTH 90.810 LUMPCC 0.003112448 DR + +*CONN +*I mux_bottom_track_27\/mux_l2_in_0_:X O *L 0 *C 20.525 52.700 +*I mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 61.500 4.255 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 61.500 4.255 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 60.305 4.420 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 60.260 4.465 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 60.260 50.943 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 60.253 51.000 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 23.928 51.000 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 23.920 51.058 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 23.920 52.655 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 23.875 52.700 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 20.562 52.700 + +*CAP +0 mux_bottom_track_27\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001257427 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.216004e-05 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002178848 +5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.002178848 +6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001606579 +7 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001606579 +8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001062559 +9 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001062559 +10 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002324178 +11 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0002324178 +12 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:137 4.410357e-06 +13 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:138 4.410357e-06 +14 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:100 0.0004687048 +15 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:101 0.0001348785 +16 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:135 2.798429e-05 +17 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:139 0.0001351251 +18 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:299 1.512201e-05 +19 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:86 0.0004687048 +20 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:100 0.0001348785 +21 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:136 2.798429e-05 +22 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:140 0.0001351251 +23 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:238 1.512201e-05 +24 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_0_sram[1]:8 7.812175e-05 +25 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_0_sram[1]:9 7.25431e-05 +26 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_0_sram[1]:5 7.812175e-05 +27 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_0_sram[1]:8 7.25431e-05 +28 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size2_10_sram[1]:14 0.0003463801 +29 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size2_10_sram[1]:15 0.0003463801 +30 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_12_sram[0]:16 0.0001673648 +31 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_12_sram[0]:15 0.0001673648 +32 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001055892 +33 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001055892 + +*RES +0 mux_bottom_track_27\/mux_l2_in_0_:X mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.002957589 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001426339 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.005690916 +6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.04149777 +7 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001066964 +9 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002527599 //LENGTH 23.130 LUMPCC 0.0005918054 DR + +*CONN +*I mux_bottom_track_37\/mux_l2_in_0_:X O *L 0 *C 80.675 22.780 +*I mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 76.630 4.280 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 76.630 4.280 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 76.820 4.420 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 76.820 4.465 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 76.820 22.735 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 76.865 22.780 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 80.638 22.780 + +*CAP +0 mux_bottom_track_37\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.00584e-05 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.745968e-05 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0007558247 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0007558247 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001523131 +7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001523131 +8 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[8] 7.590173e-05 +9 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[8]:16 7.590173e-05 +10 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.165141e-05 +11 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.165141e-05 +12 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001383496 +13 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001383496 + +*RES +0 mux_bottom_track_37\/mux_l2_in_0_:X mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001032609 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0163125 +6 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.003368304 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.004355988 //LENGTH 39.600 LUMPCC 0.0005248263 DR + +*CONN +*I mux_left_track_5\/mux_l1_in_0_:X O *L 0 *C 83.895 41.820 +*I mux_left_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.785 28.900 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.823 28.900 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 59.295 28.900 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 59.340 28.945 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 59.340 36.675 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 59.385 36.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 81.375 36.720 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 81.420 36.765 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 81.420 41.775 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 *C 81.465 41.820 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 *C 83.858 41.820 + +*CAP +0 mux_left_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.487138e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.487138e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003377051 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003377051 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.00114783 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.00114783 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0002709689 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0002709689 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001032051 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001032051 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_tree_tapbuf_size2_15_sram[0]:4 0.0001025188 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_tree_tapbuf_size2_15_sram[0]:3 0.0001025188 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:6 5.43052e-05 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_mem_13_ccff_tail[0]:7 5.43052e-05 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001055892 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001055892 + +*RES +0 mux_left_track_5\/mux_l1_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_5\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.000421875 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006901786 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.01963393 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0045 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.004473215 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.002136161 + +*END + +*D_NET ropt_net_134 0.001143756 //LENGTH 9.385 LUMPCC 0.0001362072 DR + +*CONN +*I ropt_mt_inst_725:X O *L 0 *C 11.695 94.180 +*I ropt_mt_inst_749:A I *L 0.001767 *C 3.220 93.840 +*N ropt_net_134:2 *C 3.258 93.840 +*N ropt_net_134:3 *C 5.520 93.840 +*N ropt_net_134:4 *C 5.520 94.180 +*N ropt_net_134:5 *C 11.658 94.180 + +*CAP +0 ropt_mt_inst_725:X 1e-06 +1 ropt_mt_inst_749:A 1e-06 +2 ropt_net_134:2 0.0001586773 +3 ropt_net_134:3 0.0001822452 +4 ropt_net_134:4 0.0003440972 +5 ropt_net_134:5 0.0003205294 +6 ropt_net_134:5 chany_bottom_in[10]:4 6.80357e-05 +7 ropt_net_134:3 chany_bottom_in[10]:3 6.78945e-08 +8 ropt_net_134:4 chany_bottom_in[10]:2 6.78945e-08 +9 ropt_net_134:4 chany_bottom_in[10]:3 6.80357e-05 + +*RES +0 ropt_mt_inst_725:X ropt_net_134:5 0.152 +1 ropt_net_134:2 ropt_mt_inst_749:A 0.152 +2 ropt_net_134:5 ropt_net_134:4 0.005479911 +3 ropt_net_134:3 ropt_net_134:2 0.002020089 +4 ropt_net_134:4 ropt_net_134:3 0.0003035715 + +*END + +*D_NET ropt_net_145 0.001033484 //LENGTH 7.130 LUMPCC 0.0004011345 DR + +*CONN +*I ropt_mt_inst_730:X O *L 0 *C 87.860 3.400 +*I ropt_mt_inst_764:A I *L 0.001766 *C 82.340 4.080 +*N ropt_net_145:2 *C 82.377 4.080 +*N ropt_net_145:3 *C 82.755 4.080 +*N ropt_net_145:4 *C 82.800 4.035 +*N ropt_net_145:5 *C 82.800 3.445 +*N ropt_net_145:6 *C 82.845 3.400 +*N ropt_net_145:7 *C 87.823 3.400 + +*CAP +0 ropt_mt_inst_730:X 1e-06 +1 ropt_mt_inst_764:A 1e-06 +2 ropt_net_145:2 3.152728e-05 +3 ropt_net_145:3 3.152728e-05 +4 ropt_net_145:4 5.651498e-05 +5 ropt_net_145:5 5.651498e-05 +6 ropt_net_145:6 0.0002271326 +7 ropt_net_145:7 0.0002271326 +8 ropt_net_145:2 ropt_net_115:5 2.758281e-05 +9 ropt_net_145:3 ropt_net_115:4 2.758281e-05 +10 ropt_net_145:6 ropt_net_115:3 3.491754e-05 +11 ropt_net_145:6 ropt_net_115:5 2.230523e-06 +12 ropt_net_145:7 ropt_net_115:2 3.491754e-05 +13 ropt_net_145:7 ropt_net_115:4 2.230523e-06 +14 ropt_net_145:4 chany_bottom_out[0]:2 1.728653e-05 +15 ropt_net_145:6 chany_bottom_out[0]:3 0.0001185498 +16 ropt_net_145:5 chany_bottom_out[0] 1.728653e-05 +17 ropt_net_145:7 chany_bottom_out[0]:4 0.0001185498 + +*RES +0 ropt_mt_inst_730:X ropt_net_145:7 0.152 +1 ropt_net_145:2 ropt_mt_inst_764:A 0.152 +2 ropt_net_145:3 ropt_net_145:2 0.0003370536 +3 ropt_net_145:4 ropt_net_145:3 0.0045 +4 ropt_net_145:6 ropt_net_145:5 0.0045 +5 ropt_net_145:5 ropt_net_145:4 0.0005267857 +6 ropt_net_145:7 ropt_net_145:6 0.004444197 + +*END + +*D_NET ropt_net_135 0.00131387 //LENGTH 10.865 LUMPCC 0.0001375615 DR + +*CONN +*I ropt_mt_inst_736:X O *L 0 *C 7.095 52.700 +*I ropt_mt_inst_750:A I *L 0.001767 *C 3.220 50.320 +*N ropt_net_135:2 *C 3.183 50.320 +*N ropt_net_135:3 *C 1.425 50.320 +*N ropt_net_135:4 *C 1.380 50.365 +*N ropt_net_135:5 *C 1.380 52.655 +*N ropt_net_135:6 *C 1.425 52.700 +*N ropt_net_135:7 *C 7.058 52.700 + +*CAP +0 ropt_mt_inst_736:X 1e-06 +1 ropt_mt_inst_750:A 1e-06 +2 ropt_net_135:2 0.0001222608 +3 ropt_net_135:3 0.0001222608 +4 ropt_net_135:4 0.0001318892 +5 ropt_net_135:5 0.0001318892 +6 ropt_net_135:6 0.0003330045 +7 ropt_net_135:7 0.0003330045 +8 ropt_net_135:6 ropt_net_129:5 6.878073e-05 +9 ropt_net_135:7 ropt_net_129:4 6.878073e-05 + +*RES +0 ropt_mt_inst_736:X ropt_net_135:7 0.152 +1 ropt_net_135:2 ropt_mt_inst_750:A 0.152 +2 ropt_net_135:3 ropt_net_135:2 0.001569197 +3 ropt_net_135:4 ropt_net_135:3 0.0045 +4 ropt_net_135:6 ropt_net_135:5 0.0045 +5 ropt_net_135:5 ropt_net_135:4 0.002044643 +6 ropt_net_135:7 ropt_net_135:6 0.005029018 + +*END + +*D_NET chanx_left_out[9] 0.001072626 //LENGTH 7.360 LUMPCC 0.0002073225 DR + +*CONN +*I ropt_mt_inst_748:X O *L 0 *C 7.095 65.960 +*P chanx_left_out[9] O *L 0.7423 *C 1.230 65.280 +*N chanx_left_out[9]:2 *C 4.133 65.280 +*N chanx_left_out[9]:3 *C 4.140 65.338 +*N chanx_left_out[9]:4 *C 4.140 65.915 +*N chanx_left_out[9]:5 *C 4.185 65.960 +*N chanx_left_out[9]:6 *C 7.058 65.960 + +*CAP +0 ropt_mt_inst_748:X 1e-06 +1 chanx_left_out[9] 0.0001661566 +2 chanx_left_out[9]:2 0.0001661566 +3 chanx_left_out[9]:3 5.553556e-05 +4 chanx_left_out[9]:4 5.553556e-05 +5 chanx_left_out[9]:5 0.0002104597 +6 chanx_left_out[9]:6 0.0002104597 +7 chanx_left_out[9] ropt_net_133:6 0.0001036612 +8 chanx_left_out[9]:2 ropt_net_133:7 0.0001036612 + +*RES +0 ropt_mt_inst_748:X chanx_left_out[9]:6 0.152 +1 chanx_left_out[9]:6 chanx_left_out[9]:5 0.002564732 +2 chanx_left_out[9]:5 chanx_left_out[9]:4 0.0045 +3 chanx_left_out[9]:4 chanx_left_out[9]:3 0.000515625 +4 chanx_left_out[9]:3 chanx_left_out[9]:2 0.00341 +5 chanx_left_out[9]:2 chanx_left_out[9] 0.000454725 + +*END + +*D_NET ropt_net_125 0.001861347 //LENGTH 16.520 LUMPCC 0.0001781511 DR + +*CONN +*I BUFT_RR_53:X O *L 0 *C 7.820 67.320 +*I ropt_mt_inst_740:A I *L 0.001766 *C 3.220 77.520 +*N ropt_net_125:2 *C 3.258 77.520 +*N ropt_net_125:3 *C 4.095 77.520 +*N ropt_net_125:4 *C 4.140 77.475 +*N ropt_net_125:5 *C 4.140 67.025 +*N ropt_net_125:6 *C 4.185 66.980 +*N ropt_net_125:7 *C 7.820 66.980 +*N ropt_net_125:8 *C 7.820 67.320 + +*CAP +0 BUFT_RR_53:X 1e-06 +1 ropt_mt_inst_740:A 1e-06 +2 ropt_net_125:2 6.608607e-05 +3 ropt_net_125:3 6.608607e-05 +4 ropt_net_125:4 0.0004848481 +5 ropt_net_125:5 0.0004848481 +6 ropt_net_125:6 0.0002411206 +7 ropt_net_125:7 0.0002725657 +8 ropt_net_125:8 6.564088e-05 +9 ropt_net_125:5 chanx_left_in[13]:5 8.907553e-05 +10 ropt_net_125:4 chanx_left_in[13]:6 8.907553e-05 + +*RES +0 BUFT_RR_53:X ropt_net_125:8 0.152 +1 ropt_net_125:8 ropt_net_125:7 0.0003035715 +2 ropt_net_125:6 ropt_net_125:5 0.0045 +3 ropt_net_125:5 ropt_net_125:4 0.009330358 +4 ropt_net_125:3 ropt_net_125:2 0.0007477679 +5 ropt_net_125:4 ropt_net_125:3 0.0045 +6 ropt_net_125:2 ropt_mt_inst_740:A 0.152 +7 ropt_net_125:7 ropt_net_125:6 0.003245536 + +*END + +*D_NET ropt_net_141 0.001044054 //LENGTH 7.425 LUMPCC 0.0003161966 DR + +*CONN +*I ropt_mt_inst_742:X O *L 0 *C 7.095 83.640 +*I ropt_mt_inst_757:A I *L 0.001767 *C 3.220 85.680 +*N ropt_net_141:2 *C 3.220 85.680 +*N ropt_net_141:3 *C 3.220 86.020 +*N ropt_net_141:4 *C 6.855 86.020 +*N ropt_net_141:5 *C 6.900 85.975 +*N ropt_net_141:6 *C 6.900 83.685 +*N ropt_net_141:7 *C 6.900 83.640 +*N ropt_net_141:8 *C 7.095 83.640 + +*CAP +0 ropt_mt_inst_742:X 1e-06 +1 ropt_mt_inst_757:A 1e-06 +2 ropt_net_141:2 5.564053e-05 +3 ropt_net_141:3 0.0001392854 +4 ropt_net_141:4 0.0001119687 +5 ropt_net_141:5 0.0001421238 +6 ropt_net_141:6 0.0001421238 +7 ropt_net_141:7 6.560882e-05 +8 ropt_net_141:8 6.910629e-05 +9 ropt_net_141:4 ropt_net_147:2 0.0001146721 +10 ropt_net_141:5 ropt_net_147:5 2.088178e-07 +11 ropt_net_141:6 ropt_net_147:4 2.088178e-07 +12 ropt_net_141:3 ropt_net_147:3 0.0001146721 +13 ropt_net_141:4 chanx_left_out[13]:6 4.321742e-05 +14 ropt_net_141:3 chanx_left_out[13]:5 4.321742e-05 + +*RES +0 ropt_mt_inst_742:X ropt_net_141:8 0.152 +1 ropt_net_141:2 ropt_mt_inst_757:A 0.152 +2 ropt_net_141:4 ropt_net_141:3 0.003245536 +3 ropt_net_141:5 ropt_net_141:4 0.0045 +4 ropt_net_141:7 ropt_net_141:6 0.0045 +5 ropt_net_141:6 ropt_net_141:5 0.002044643 +6 ropt_net_141:8 ropt_net_141:7 0.0001059783 +7 ropt_net_141:3 ropt_net_141:2 0.0003035715 + +*END + +*D_NET ccff_tail[0] 0.001618146 //LENGTH 14.450 LUMPCC 7.730004e-05 DR + +*CONN +*I ropt_mt_inst_763:X O *L 0 *C 11.695 80.580 +*P ccff_tail[0] O *L 0.7423 *C 1.298 77.520 +*N ccff_tail[0]:2 *C 1.380 77.520 +*N ccff_tail[0]:3 *C 1.380 77.520 +*N ccff_tail[0]:4 *C 2.300 77.520 +*N ccff_tail[0]:5 *C 2.300 80.535 +*N ccff_tail[0]:6 *C 2.345 80.580 +*N ccff_tail[0]:7 *C 11.658 80.580 + +*CAP +0 ropt_mt_inst_763:X 1e-06 +1 ccff_tail[0] 2.846919e-05 +2 ccff_tail[0]:2 2.846919e-05 +3 ccff_tail[0]:3 8.550692e-05 +4 ccff_tail[0]:4 0.0002155862 +5 ccff_tail[0]:5 0.0001625572 +6 ccff_tail[0]:6 0.0005096288 +7 ccff_tail[0]:7 0.0005096288 +8 ccff_tail[0]:7 ropt_net_144:5 3.865002e-05 +9 ccff_tail[0]:6 ropt_net_144:6 3.865002e-05 + +*RES +0 ropt_mt_inst_763:X ccff_tail[0]:7 0.152 +1 ccff_tail[0]:7 ccff_tail[0]:6 0.008314732 +2 ccff_tail[0]:6 ccff_tail[0]:5 0.0045 +3 ccff_tail[0]:5 ccff_tail[0]:4 0.002691964 +4 ccff_tail[0]:3 ccff_tail[0]:2 0.00341 +5 ccff_tail[0]:2 ccff_tail[0] 2.35e-05 +6 ccff_tail[0]:4 ccff_tail[0]:3 0.0008214285 + +*END + +*D_NET ropt_net_114 0.001591782 //LENGTH 12.800 LUMPCC 0.0002678154 DR + +*CONN +*I BUFT_RR_74:X O *L 0 *C 13.800 86.020 +*I ropt_mt_inst_729:A I *L 0.001766 *C 7.820 91.120 +*N ropt_net_114:2 *C 7.820 91.120 +*N ropt_net_114:3 *C 7.820 91.460 +*N ropt_net_114:4 *C 8.695 91.460 +*N ropt_net_114:5 *C 8.740 91.415 +*N ropt_net_114:6 *C 8.740 86.065 +*N ropt_net_114:7 *C 8.785 86.020 +*N ropt_net_114:8 *C 13.763 86.020 + +*CAP +0 BUFT_RR_74:X 1e-06 +1 ropt_mt_inst_729:A 1e-06 +2 ropt_net_114:2 6.200185e-05 +3 ropt_net_114:3 0.0001147739 +4 ropt_net_114:4 8.464689e-05 +5 ropt_net_114:5 0.0002855525 +6 ropt_net_114:6 0.0002855525 +7 ropt_net_114:7 0.0002447194 +8 ropt_net_114:8 0.0002447194 +9 ropt_net_114:8 chany_bottom_in[12]:5 0.0001339077 +10 ropt_net_114:7 chany_bottom_in[12]:6 0.0001339077 + +*RES +0 BUFT_RR_74:X ropt_net_114:8 0.152 +1 ropt_net_114:8 ropt_net_114:7 0.004444196 +2 ropt_net_114:7 ropt_net_114:6 0.0045 +3 ropt_net_114:6 ropt_net_114:5 0.004776786 +4 ropt_net_114:4 ropt_net_114:3 0.00078125 +5 ropt_net_114:5 ropt_net_114:4 0.0045 +6 ropt_net_114:2 ropt_mt_inst_729:A 0.152 +7 ropt_net_114:3 ropt_net_114:2 0.0003035715 + +*END + +*D_NET chany_bottom_in[4] 0.01676581 //LENGTH 138.300 LUMPCC 0.006172419 DR + +*CONN +*P chany_bottom_in[4] I *L 0.29796 *C 65.320 1.290 +*I ropt_mt_inst_733:A I *L 0.001767 *C 3.220 72.080 +*N chany_bottom_in[4]:2 *C 64.610 4.080 +*N chany_bottom_in[4]:3 *C 3.220 72.080 +*N chany_bottom_in[4]:4 *C 3.220 71.740 +*N chany_bottom_in[4]:5 *C 5.935 71.740 +*N chany_bottom_in[4]:6 *C 5.980 71.695 +*N chany_bottom_in[4]:7 *C 5.980 63.625 +*N chany_bottom_in[4]:8 *C 6.025 63.580 +*N chany_bottom_in[4]:9 *C 10.580 63.580 +*N chany_bottom_in[4]:10 *C 10.505 63.240 +*N chany_bottom_in[4]:11 *C 10.572 63.285 +*N chany_bottom_in[4]:12 *C 10.580 63.875 +*N chany_bottom_in[4]:13 *C 10.625 63.920 +*N chany_bottom_in[4]:14 *C 16.515 63.920 +*N chany_bottom_in[4]:15 *C 16.560 63.875 +*N chany_bottom_in[4]:16 *C 16.560 61.938 +*N chany_bottom_in[4]:17 *C 16.568 61.880 +*N chany_bottom_in[4]:18 *C 65.300 61.880 +*N chany_bottom_in[4]:19 *C 65.320 61.873 +*N chany_bottom_in[4]:20 *C 65.320 53.915 +*N chany_bottom_in[4]:21 *C 65.320 4.088 +*N chany_bottom_in[4]:22 *C 65.318 4.080 +*N chany_bottom_in[4]:23 *C 65.320 4.022 + +*CAP +0 chany_bottom_in[4] 0.0001671764 +1 ropt_mt_inst_733:A 1e-06 +2 chany_bottom_in[4]:2 0.0001159399 +3 chany_bottom_in[4]:3 5.57804e-05 +4 chany_bottom_in[4]:4 0.0001536332 +5 chany_bottom_in[4]:5 0.0001269915 +6 chany_bottom_in[4]:6 0.0004601801 +7 chany_bottom_in[4]:7 0.0004601801 +8 chany_bottom_in[4]:8 0.0002887994 +9 chany_bottom_in[4]:9 0.0003169674 +10 chany_bottom_in[4]:10 6.030472e-05 +11 chany_bottom_in[4]:11 5.765889e-05 +12 chany_bottom_in[4]:12 5.765889e-05 +13 chany_bottom_in[4]:13 0.0003447289 +14 chany_bottom_in[4]:14 0.0003447289 +15 chany_bottom_in[4]:15 0.0001027638 +16 chany_bottom_in[4]:16 0.0001027638 +17 chany_bottom_in[4]:17 0.001691804 +18 chany_bottom_in[4]:18 0.001691804 +19 chany_bottom_in[4]:19 0.0002451405 +20 chany_bottom_in[4]:20 0.001854704 +21 chany_bottom_in[4]:21 0.001609564 +22 chany_bottom_in[4]:22 0.0001159399 +23 chany_bottom_in[4]:23 0.0001671764 +24 chany_bottom_in[4] chany_bottom_in[13] 4.625613e-07 +25 chany_bottom_in[4]:19 chany_bottom_in[13]:10 0.0001222632 +26 chany_bottom_in[4]:21 chany_bottom_in[13]:12 0.0006634632 +27 chany_bottom_in[4]:21 chany_bottom_in[13]:11 2.038945e-05 +28 chany_bottom_in[4]:23 chany_bottom_in[13]:14 4.625613e-07 +29 chany_bottom_in[4]:20 chany_bottom_in[13]:10 2.038945e-05 +30 chany_bottom_in[4]:20 chany_bottom_in[13]:11 0.0007857265 +31 chany_bottom_in[4]:17 prog_clk[0]:70 0.0002839621 +32 chany_bottom_in[4]:18 prog_clk[0]:69 0.0002839621 +33 chany_bottom_in[4]:21 prog_clk[0]:238 6.399865e-06 +34 chany_bottom_in[4]:20 prog_clk[0]:299 6.399865e-06 +35 chany_bottom_in[4]:17 chanx_left_in[3] 0.0005376645 +36 chany_bottom_in[4]:18 chanx_left_in[3]:10 0.0005376645 +37 chany_bottom_in[4]:17 chanx_left_in[11]:11 7.82489e-05 +38 chany_bottom_in[4]:17 chanx_left_in[11]:10 3.35754e-05 +39 chany_bottom_in[4]:18 chanx_left_in[11]:9 3.35754e-05 +40 chany_bottom_in[4]:18 chanx_left_in[11]:10 7.82489e-05 +41 chany_bottom_in[4]:19 chanx_left_in[11]:8 3.871718e-05 +42 chany_bottom_in[4]:21 chanx_left_in[11]:7 0.0003169044 +43 chany_bottom_in[4]:20 chanx_left_in[11]:7 3.871718e-05 +44 chany_bottom_in[4]:20 chanx_left_in[11]:8 0.0003169044 +45 chany_bottom_in[4]:15 optlc_net_106:40 2.731132e-05 +46 chany_bottom_in[4]:16 optlc_net_106:43 2.731132e-05 +47 chany_bottom_in[4]:17 optlc_net_106:19 0.0006394541 +48 chany_bottom_in[4]:18 optlc_net_106:18 0.0006394541 +49 chany_bottom_in[4]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.629714e-06 +50 chany_bottom_in[4]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.629714e-06 +51 chany_bottom_in[4]:13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.052656e-06 +52 chany_bottom_in[4]:14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.052656e-06 +53 chany_bottom_in[4]:17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.000242356 +54 chany_bottom_in[4]:18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.000242356 +55 chany_bottom_in[4]:3 ropt_net_143:4 1.401458e-06 +56 chany_bottom_in[4]:5 ropt_net_143:2 5.926772e-05 +57 chany_bottom_in[4]:5 ropt_net_143:4 5.685497e-06 +58 chany_bottom_in[4]:4 ropt_net_143:5 5.685497e-06 +59 chany_bottom_in[4]:4 ropt_net_143:3 6.066918e-05 + +*RES +0 chany_bottom_in[4] chany_bottom_in[4]:23 0.002439732 +1 chany_bottom_in[4]:3 ropt_mt_inst_733:A 0.152 +2 chany_bottom_in[4]:5 chany_bottom_in[4]:4 0.002424107 +3 chany_bottom_in[4]:6 chany_bottom_in[4]:5 0.0045 +4 chany_bottom_in[4]:8 chany_bottom_in[4]:7 0.0045 +5 chany_bottom_in[4]:7 chany_bottom_in[4]:6 0.007205357 +6 chany_bottom_in[4]:10 chany_bottom_in[4]:9 0.0003035715 +7 chany_bottom_in[4]:11 chany_bottom_in[4]:10 0.0045 +8 chany_bottom_in[4]:13 chany_bottom_in[4]:12 0.0045 +9 chany_bottom_in[4]:12 chany_bottom_in[4]:11 0.0005267857 +10 chany_bottom_in[4]:14 chany_bottom_in[4]:13 0.005258929 +11 chany_bottom_in[4]:15 chany_bottom_in[4]:14 0.0045 +12 chany_bottom_in[4]:16 chany_bottom_in[4]:15 0.001729911 +13 chany_bottom_in[4]:17 chany_bottom_in[4]:16 0.00341 +14 chany_bottom_in[4]:18 chany_bottom_in[4]:17 0.007634758 +15 chany_bottom_in[4]:19 chany_bottom_in[4]:18 0.00341 +16 chany_bottom_in[4]:22 chany_bottom_in[4]:21 0.00341 +17 chany_bottom_in[4]:22 chany_bottom_in[4]:2 0.0001039141 +18 chany_bottom_in[4]:21 chany_bottom_in[4]:20 0.007806308 +19 chany_bottom_in[4]:23 chany_bottom_in[4]:22 0.00341 +20 chany_bottom_in[4]:4 chany_bottom_in[4]:3 0.0003035715 +21 chany_bottom_in[4]:9 chany_bottom_in[4]:8 0.004066964 +22 chany_bottom_in[4]:20 chany_bottom_in[4]:19 0.001246675 + +*END + +*D_NET chany_bottom_in[1] 0.006831393 //LENGTH 60.875 LUMPCC 0 DR + +*CONN +*P chany_bottom_in[1] I *L 0.29796 *C 67.160 1.325 +*I mux_left_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 85.560 41.820 +*N chany_bottom_in[1]:2 *C 85.560 41.820 +*N chany_bottom_in[1]:3 *C 85.560 41.820 +*N chany_bottom_in[1]:4 *C 85.100 41.820 +*N chany_bottom_in[1]:5 *C 85.100 1.745 +*N chany_bottom_in[1]:6 *C 85.100 1.700 +*N chany_bottom_in[1]:7 *C 85.100 1.360 +*N chany_bottom_in[1]:8 *C 74.520 1.360 +*N chany_bottom_in[1]:9 *C 74.520 1.700 +*N chany_bottom_in[1]:10 *C 67.205 1.700 +*N chany_bottom_in[1]:11 *C 67.160 1.655 + +*CAP +0 chany_bottom_in[1] 3.51518e-05 +1 mux_left_track_5\/mux_l1_in_0_:A1 1e-06 +2 chany_bottom_in[1]:2 3.25964e-05 +3 chany_bottom_in[1]:3 6.211436e-05 +4 chany_bottom_in[1]:4 0.002203739 +5 chany_bottom_in[1]:5 0.002171687 +6 chany_bottom_in[1]:6 6.345853e-05 +7 chany_bottom_in[1]:7 0.0006505144 +8 chany_bottom_in[1]:8 0.0006478311 +9 chany_bottom_in[1]:9 0.0004773781 +10 chany_bottom_in[1]:10 0.000450771 +11 chany_bottom_in[1]:11 3.51518e-05 + +*RES +0 chany_bottom_in[1] chany_bottom_in[1]:11 0.0002946429 +1 chany_bottom_in[1]:2 mux_left_track_5\/mux_l1_in_0_:A1 0.152 +2 chany_bottom_in[1]:3 chany_bottom_in[1]:2 0.0045 +3 chany_bottom_in[1]:6 chany_bottom_in[1]:5 0.0045 +4 chany_bottom_in[1]:5 chany_bottom_in[1]:4 0.03578125 +5 chany_bottom_in[1]:10 chany_bottom_in[1]:9 0.00653125 +6 chany_bottom_in[1]:11 chany_bottom_in[1]:10 0.0045 +7 chany_bottom_in[1]:9 chany_bottom_in[1]:8 0.0003035715 +8 chany_bottom_in[1]:8 chany_bottom_in[1]:7 0.009446429 +9 chany_bottom_in[1]:7 chany_bottom_in[1]:6 0.0003035715 +10 chany_bottom_in[1]:4 chany_bottom_in[1]:3 0.0004107143 + +*END + +*D_NET chany_bottom_in[3] 0.008558974 //LENGTH 74.650 LUMPCC 0.002920426 DR + +*CONN +*P chany_bottom_in[3] I *L 0.29796 *C 88.320 1.290 +*I mux_left_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 76.820 63.580 +*N chany_bottom_in[3]:2 *C 76.820 63.580 +*N chany_bottom_in[3]:3 *C 76.820 63.535 +*N chany_bottom_in[3]:4 *C 76.820 62.617 +*N chany_bottom_in[3]:5 *C 76.828 62.560 +*N chany_bottom_in[3]:6 *C 88.312 62.560 +*N chany_bottom_in[3]:7 *C 88.320 62.503 +*N chany_bottom_in[3]:8 *C 88.320 51.290 + +*CAP +0 chany_bottom_in[3] 0.001738363 +1 mux_left_track_9\/mux_l1_in_0_:A1 1e-06 +2 chany_bottom_in[3]:2 3.367481e-05 +3 chany_bottom_in[3]:3 8.71463e-05 +4 chany_bottom_in[3]:4 8.71463e-05 +5 chany_bottom_in[3]:5 0.0004715569 +6 chany_bottom_in[3]:6 0.0004715569 +7 chany_bottom_in[3]:7 0.0005048698 +8 chany_bottom_in[3]:8 0.002243233 +9 chany_bottom_in[3] chany_bottom_in[19]:5 0.0005531673 +10 chany_bottom_in[3]:8 chany_bottom_in[19]:4 0.0005531673 +11 chany_bottom_in[3]:5 optlc_net_106:19 0.0005536271 +12 chany_bottom_in[3]:7 optlc_net_106:17 1.127267e-05 +13 chany_bottom_in[3]:6 optlc_net_106:18 0.0005536271 +14 chany_bottom_in[3]:8 optlc_net_106:16 1.127267e-05 +15 chany_bottom_in[3] mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002995134 +16 chany_bottom_in[3]:7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.263277e-05 +17 chany_bottom_in[3]:8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.263277e-05 +18 chany_bottom_in[3]:8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002995134 + +*RES +0 chany_bottom_in[3] chany_bottom_in[3]:8 0.04464286 +1 chany_bottom_in[3]:2 mux_left_track_9\/mux_l1_in_0_:A1 0.152 +2 chany_bottom_in[3]:3 chany_bottom_in[3]:2 0.0045 +3 chany_bottom_in[3]:4 chany_bottom_in[3]:3 0.0008191965 +4 chany_bottom_in[3]:5 chany_bottom_in[3]:4 0.00341 +5 chany_bottom_in[3]:7 chany_bottom_in[3]:6 0.00341 +6 chany_bottom_in[3]:6 chany_bottom_in[3]:5 0.001799316 +7 chany_bottom_in[3]:8 chany_bottom_in[3]:7 0.01001116 + +*END + +*D_NET chany_bottom_in[19] 0.006144048 //LENGTH 57.295 LUMPCC 0.001106335 DR + +*CONN +*P chany_bottom_in[19] I *L 0.29796 *C 78.660 1.290 +*I mux_left_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 88.880 47.260 +*N chany_bottom_in[19]:2 *C 88.843 47.260 +*N chany_bottom_in[19]:3 *C 87.445 47.260 +*N chany_bottom_in[19]:4 *C 87.400 47.215 +*N chany_bottom_in[19]:5 *C 87.400 6.505 +*N chany_bottom_in[19]:6 *C 87.355 6.460 +*N chany_bottom_in[19]:7 *C 78.705 6.460 +*N chany_bottom_in[19]:8 *C 78.660 6.415 + +*CAP +0 chany_bottom_in[19] 0.0002902753 +1 mux_left_track_1\/mux_l1_in_0_:A1 1e-06 +2 chany_bottom_in[19]:2 0.0001501278 +3 chany_bottom_in[19]:3 0.0001501278 +4 chany_bottom_in[19]:4 0.001582591 +5 chany_bottom_in[19]:5 0.001582591 +6 chany_bottom_in[19]:6 0.0004953628 +7 chany_bottom_in[19]:7 0.0004953628 +8 chany_bottom_in[19]:8 0.0002902753 +9 chany_bottom_in[19]:4 chany_bottom_in[3]:8 0.0005531673 +10 chany_bottom_in[19]:5 chany_bottom_in[3] 0.0005531673 + +*RES +0 chany_bottom_in[19] chany_bottom_in[19]:8 0.004575893 +1 chany_bottom_in[19]:2 mux_left_track_1\/mux_l1_in_0_:A1 0.152 +2 chany_bottom_in[19]:3 chany_bottom_in[19]:2 0.001247768 +3 chany_bottom_in[19]:4 chany_bottom_in[19]:3 0.0045 +4 chany_bottom_in[19]:6 chany_bottom_in[19]:5 0.0045 +5 chany_bottom_in[19]:5 chany_bottom_in[19]:4 0.03634822 +6 chany_bottom_in[19]:7 chany_bottom_in[19]:6 0.007723214 +7 chany_bottom_in[19]:8 chany_bottom_in[19]:7 0.0045 + +*END + +*D_NET bottom_right_grid_pin_1_[0] 0.01873076 //LENGTH 149.930 LUMPCC 0.001701228 DR + +*CONN +*P bottom_right_grid_pin_1_[0] I *L 0.29796 *C 110.860 1.325 +*I mux_bottom_track_9\/mux_l1_in_0_:A1 I *L 0.00198 *C 39.100 14.620 +*I mux_bottom_track_1\/mux_l1_in_0_:A1 I *L 0.00198 *C 27.045 34.340 +*I mux_bottom_track_25\/mux_l1_in_0_:A1 I *L 0.00198 *C 26.680 50.660 +*I mux_bottom_track_5\/mux_l1_in_0_:A1 I *L 0.00198 *C 31.380 41.820 +*N bottom_right_grid_pin_1_[0]:5 *C 26.718 50.660 +*N bottom_right_grid_pin_1_[0]:6 *C 29.440 50.660 +*N bottom_right_grid_pin_1_[0]:7 *C 29.440 50.320 +*N bottom_right_grid_pin_1_[0]:8 *C 31.235 50.320 +*N bottom_right_grid_pin_1_[0]:9 *C 31.280 50.275 +*N bottom_right_grid_pin_1_[0]:10 *C 31.280 41.865 +*N bottom_right_grid_pin_1_[0]:11 *C 31.280 41.820 +*N bottom_right_grid_pin_1_[0]:12 *C 31.348 41.480 +*N bottom_right_grid_pin_1_[0]:13 *C 39.515 41.480 +*N bottom_right_grid_pin_1_[0]:14 *C 39.560 41.435 +*N bottom_right_grid_pin_1_[0]:15 *C 27.045 34.340 +*N bottom_right_grid_pin_1_[0]:16 *C 27.140 34.680 +*N bottom_right_grid_pin_1_[0]:17 *C 39.515 34.680 +*N bottom_right_grid_pin_1_[0]:18 *C 39.560 34.680 +*N bottom_right_grid_pin_1_[0]:19 *C 39.138 14.620 +*N bottom_right_grid_pin_1_[0]:20 *C 39.515 14.620 +*N bottom_right_grid_pin_1_[0]:21 *C 39.560 14.665 +*N bottom_right_grid_pin_1_[0]:22 *C 39.560 14.280 +*N bottom_right_grid_pin_1_[0]:23 *C 39.568 14.280 +*N bottom_right_grid_pin_1_[0]:24 *C 89.395 14.280 +*N bottom_right_grid_pin_1_[0]:25 *C 108.553 14.280 +*N bottom_right_grid_pin_1_[0]:26 *C 108.560 14.223 +*N bottom_right_grid_pin_1_[0]:27 *C 108.560 8.840 +*N bottom_right_grid_pin_1_[0]:28 *C 110.860 8.840 + +*CAP +0 bottom_right_grid_pin_1_[0] 0.0003447218 +1 mux_bottom_track_9\/mux_l1_in_0_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_0_:A1 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_5\/mux_l1_in_0_:A1 1e-06 +5 bottom_right_grid_pin_1_[0]:5 0.0001720898 +6 bottom_right_grid_pin_1_[0]:6 0.0001955134 +7 bottom_right_grid_pin_1_[0]:7 0.0001806828 +8 bottom_right_grid_pin_1_[0]:8 0.0001572592 +9 bottom_right_grid_pin_1_[0]:9 0.0004324254 +10 bottom_right_grid_pin_1_[0]:10 0.0004324254 +11 bottom_right_grid_pin_1_[0]:11 7.23847e-05 +12 bottom_right_grid_pin_1_[0]:12 0.0006310887 +13 bottom_right_grid_pin_1_[0]:13 0.000594342 +14 bottom_right_grid_pin_1_[0]:14 0.0002939735 +15 bottom_right_grid_pin_1_[0]:15 6.210653e-05 +16 bottom_right_grid_pin_1_[0]:16 0.0009564288 +17 bottom_right_grid_pin_1_[0]:17 0.000926606 +18 bottom_right_grid_pin_1_[0]:18 0.001461089 +19 bottom_right_grid_pin_1_[0]:19 5.085845e-05 +20 bottom_right_grid_pin_1_[0]:20 5.085845e-05 +21 bottom_right_grid_pin_1_[0]:21 0.001153244 +22 bottom_right_grid_pin_1_[0]:22 5.501488e-05 +23 bottom_right_grid_pin_1_[0]:23 0.002954438 +24 bottom_right_grid_pin_1_[0]:24 0.003881698 +25 bottom_right_grid_pin_1_[0]:25 0.0009272604 +26 bottom_right_grid_pin_1_[0]:26 0.0002358335 +27 bottom_right_grid_pin_1_[0]:27 0.0003471499 +28 bottom_right_grid_pin_1_[0]:28 0.0004560381 +29 bottom_right_grid_pin_1_[0]:9 prog_clk[0]:98 3.983758e-08 +30 bottom_right_grid_pin_1_[0]:9 prog_clk[0]:141 4.118745e-06 +31 bottom_right_grid_pin_1_[0]:9 prog_clk[0]:147 2.979318e-05 +32 bottom_right_grid_pin_1_[0]:10 prog_clk[0]:99 3.983758e-08 +33 bottom_right_grid_pin_1_[0]:10 prog_clk[0]:147 4.118745e-06 +34 bottom_right_grid_pin_1_[0]:10 prog_clk[0]:201 2.979318e-05 +35 bottom_right_grid_pin_1_[0]:14 prog_clk[0]:170 0.0001288125 +36 bottom_right_grid_pin_1_[0]:23 prog_clk[0]:238 1.272876e-05 +37 bottom_right_grid_pin_1_[0]:23 prog_clk[0]:295 4.142351e-05 +38 bottom_right_grid_pin_1_[0]:23 prog_clk[0]:296 1.331153e-05 +39 bottom_right_grid_pin_1_[0]:23 prog_clk[0]:300 0.0003252033 +40 bottom_right_grid_pin_1_[0]:23 prog_clk[0]:310 5.406564e-06 +41 bottom_right_grid_pin_1_[0]:21 prog_clk[0]:171 7.320543e-05 +42 bottom_right_grid_pin_1_[0]:21 prog_clk[0]:213 2.629775e-08 +43 bottom_right_grid_pin_1_[0]:21 prog_clk[0]:214 4.132504e-08 +44 bottom_right_grid_pin_1_[0]:18 prog_clk[0]:170 7.320543e-05 +45 bottom_right_grid_pin_1_[0]:18 prog_clk[0]:171 0.0001288125 +46 bottom_right_grid_pin_1_[0]:18 prog_clk[0]:210 4.132504e-08 +47 bottom_right_grid_pin_1_[0]:18 prog_clk[0]:214 2.629775e-08 +48 bottom_right_grid_pin_1_[0]:24 prog_clk[0]:237 1.272876e-05 +49 bottom_right_grid_pin_1_[0]:24 prog_clk[0]:244 4.142351e-05 +50 bottom_right_grid_pin_1_[0]:24 prog_clk[0]:295 1.331153e-05 +51 bottom_right_grid_pin_1_[0]:24 prog_clk[0]:299 0.0003252033 +52 bottom_right_grid_pin_1_[0]:24 prog_clk[0]:306 5.406564e-06 +53 bottom_right_grid_pin_1_[0]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.322558e-05 +54 bottom_right_grid_pin_1_[0]:8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.995201e-06 +55 bottom_right_grid_pin_1_[0]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.52931e-05 +56 bottom_right_grid_pin_1_[0]:7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.995201e-06 +57 bottom_right_grid_pin_1_[0]:7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.067523e-06 +58 bottom_right_grid_pin_1_[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001262151 +59 bottom_right_grid_pin_1_[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001262151 + +*RES +0 bottom_right_grid_pin_1_[0] bottom_right_grid_pin_1_[0]:28 0.006709822 +1 bottom_right_grid_pin_1_[0]:5 mux_bottom_track_25\/mux_l1_in_0_:A1 0.152 +2 bottom_right_grid_pin_1_[0]:8 bottom_right_grid_pin_1_[0]:7 0.001602679 +3 bottom_right_grid_pin_1_[0]:9 bottom_right_grid_pin_1_[0]:8 0.0045 +4 bottom_right_grid_pin_1_[0]:11 bottom_right_grid_pin_1_[0]:10 0.0045 +5 bottom_right_grid_pin_1_[0]:11 mux_bottom_track_5\/mux_l1_in_0_:A1 0.152 +6 bottom_right_grid_pin_1_[0]:10 bottom_right_grid_pin_1_[0]:9 0.007508928 +7 bottom_right_grid_pin_1_[0]:13 bottom_right_grid_pin_1_[0]:12 0.007292411 +8 bottom_right_grid_pin_1_[0]:14 bottom_right_grid_pin_1_[0]:13 0.0045 +9 bottom_right_grid_pin_1_[0]:22 bottom_right_grid_pin_1_[0]:21 0.0001850962 +10 bottom_right_grid_pin_1_[0]:23 bottom_right_grid_pin_1_[0]:22 0.00341 +11 bottom_right_grid_pin_1_[0]:26 bottom_right_grid_pin_1_[0]:25 0.00341 +12 bottom_right_grid_pin_1_[0]:25 bottom_right_grid_pin_1_[0]:24 0.003001342 +13 bottom_right_grid_pin_1_[0]:20 bottom_right_grid_pin_1_[0]:19 0.0003370536 +14 bottom_right_grid_pin_1_[0]:21 bottom_right_grid_pin_1_[0]:20 0.0045 +15 bottom_right_grid_pin_1_[0]:21 bottom_right_grid_pin_1_[0]:18 0.01787054 +16 bottom_right_grid_pin_1_[0]:19 mux_bottom_track_9\/mux_l1_in_0_:A1 0.152 +17 bottom_right_grid_pin_1_[0]:17 bottom_right_grid_pin_1_[0]:16 0.01104911 +18 bottom_right_grid_pin_1_[0]:18 bottom_right_grid_pin_1_[0]:17 0.0045 +19 bottom_right_grid_pin_1_[0]:18 bottom_right_grid_pin_1_[0]:14 0.006031251 +20 bottom_right_grid_pin_1_[0]:15 mux_bottom_track_1\/mux_l1_in_0_:A1 0.152 +21 bottom_right_grid_pin_1_[0]:6 bottom_right_grid_pin_1_[0]:5 0.002430804 +22 bottom_right_grid_pin_1_[0]:16 bottom_right_grid_pin_1_[0]:15 0.0003035715 +23 bottom_right_grid_pin_1_[0]:7 bottom_right_grid_pin_1_[0]:6 0.0003035715 +24 bottom_right_grid_pin_1_[0]:12 bottom_right_grid_pin_1_[0]:11 0.0001847826 +25 bottom_right_grid_pin_1_[0]:27 bottom_right_grid_pin_1_[0]:26 0.004805804 +26 bottom_right_grid_pin_1_[0]:28 bottom_right_grid_pin_1_[0]:27 0.002053572 +27 bottom_right_grid_pin_1_[0]:24 bottom_right_grid_pin_1_[0]:23 0.007806308 + +*END + +*D_NET bottom_left_grid_pin_35_[0] 0.009365676 //LENGTH 72.035 LUMPCC 0.003249247 DR + +*CONN +*P bottom_left_grid_pin_35_[0] I *L 0.29796 *C 29.825 8.160 +*I mux_bottom_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 27.430 33.320 +*I mux_bottom_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 30.995 42.840 +*I mux_bottom_track_29\/mux_l1_in_0_:A1 I *L 0.00198 *C 27.965 66.980 +*I mux_bottom_track_13\/mux_l1_in_0_:A1 I *L 0.00198 *C 33.680 66.980 +*N bottom_left_grid_pin_35_[0]:5 *C 33.642 66.980 +*N bottom_left_grid_pin_35_[0]:6 *C 28.003 66.980 +*N bottom_left_grid_pin_35_[0]:7 *C 29.900 66.980 +*N bottom_left_grid_pin_35_[0]:8 *C 29.900 66.935 +*N bottom_left_grid_pin_35_[0]:9 *C 30.958 42.840 +*N bottom_left_grid_pin_35_[0]:10 *C 29.945 42.840 +*N bottom_left_grid_pin_35_[0]:11 *C 29.900 42.885 +*N bottom_left_grid_pin_35_[0]:12 *C 29.440 42.840 +*N bottom_left_grid_pin_35_[0]:13 *C 27.468 33.320 +*N bottom_left_grid_pin_35_[0]:14 *C 29.395 33.320 +*N bottom_left_grid_pin_35_[0]:15 *C 29.440 33.320 +*N bottom_left_grid_pin_35_[0]:16 *C 29.440 31.325 +*N bottom_left_grid_pin_35_[0]:17 *C 29.485 31.280 +*N bottom_left_grid_pin_35_[0]:18 *C 30.315 31.280 +*N bottom_left_grid_pin_35_[0]:19 *C 30.360 31.235 +*N bottom_left_grid_pin_35_[0]:20 *C 30.360 8.218 +*N bottom_left_grid_pin_35_[0]:21 *C 30.353 8.160 + +*CAP +0 bottom_left_grid_pin_35_[0] 3.416182e-05 +1 mux_bottom_track_1\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_5\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_29\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_13\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_35_[0]:5 0.0002481095 +6 bottom_left_grid_pin_35_[0]:6 0.0001214683 +7 bottom_left_grid_pin_35_[0]:7 0.000403327 +8 bottom_left_grid_pin_35_[0]:8 0.001220514 +9 bottom_left_grid_pin_35_[0]:9 0.0001090564 +10 bottom_left_grid_pin_35_[0]:10 0.0001090564 +11 bottom_left_grid_pin_35_[0]:11 0.001244728 +12 bottom_left_grid_pin_35_[0]:12 0.0004641639 +13 bottom_left_grid_pin_35_[0]:13 0.0001913629 +14 bottom_left_grid_pin_35_[0]:14 0.0001913629 +15 bottom_left_grid_pin_35_[0]:15 0.0005963134 +16 bottom_left_grid_pin_35_[0]:16 0.0001209353 +17 bottom_left_grid_pin_35_[0]:17 4.719395e-05 +18 bottom_left_grid_pin_35_[0]:18 4.719395e-05 +19 bottom_left_grid_pin_35_[0]:19 0.0004646593 +20 bottom_left_grid_pin_35_[0]:20 0.0004646593 +21 bottom_left_grid_pin_35_[0]:21 3.416182e-05 +22 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_36_[0] 2.06803e-05 +23 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_36_[0]:32 0.0003821441 +24 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_36_[0]:33 0.0001985315 +25 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_36_[0]:34 2.06803e-05 +26 bottom_left_grid_pin_35_[0]:19 bottom_left_grid_pin_36_[0]:29 0.0003821441 +27 bottom_left_grid_pin_35_[0]:19 bottom_left_grid_pin_36_[0]:32 0.0001985315 +28 bottom_left_grid_pin_35_[0]:8 bottom_left_grid_pin_36_[0]:7 1.734815e-05 +29 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_36_[0]:8 1.734815e-05 +30 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_37_[0]:29 0.000643748 +31 bottom_left_grid_pin_35_[0]:18 bottom_left_grid_pin_37_[0]:24 2.279782e-05 +32 bottom_left_grid_pin_35_[0]:18 bottom_left_grid_pin_37_[0]:27 2.279782e-05 +33 bottom_left_grid_pin_35_[0]:19 bottom_left_grid_pin_37_[0]:28 0.000643748 +34 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_37_[0]:27 2.279782e-05 +35 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_37_[0]:26 2.279782e-05 +36 bottom_left_grid_pin_35_[0]:16 bottom_left_grid_pin_37_[0]:29 1.608866e-05 +37 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_37_[0]:22 1.706607e-06 +38 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_37_[0]:28 1.608866e-05 +39 bottom_left_grid_pin_35_[0]:12 bottom_left_grid_pin_37_[0]:20 1.706607e-06 +40 bottom_left_grid_pin_35_[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001251719 +41 bottom_left_grid_pin_35_[0]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001251719 +42 bottom_left_grid_pin_35_[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.072064e-05 +43 bottom_left_grid_pin_35_[0]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.072064e-05 +44 bottom_left_grid_pin_35_[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001121003 +45 bottom_left_grid_pin_35_[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.078782e-05 +46 bottom_left_grid_pin_35_[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001121003 +47 bottom_left_grid_pin_35_[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.078782e-05 + +*RES +0 bottom_left_grid_pin_35_[0] bottom_left_grid_pin_35_[0]:21 8.264167e-05 +1 bottom_left_grid_pin_35_[0]:20 bottom_left_grid_pin_35_[0]:19 0.02055134 +2 bottom_left_grid_pin_35_[0]:21 bottom_left_grid_pin_35_[0]:20 0.00341 +3 bottom_left_grid_pin_35_[0]:18 bottom_left_grid_pin_35_[0]:17 0.0007410714 +4 bottom_left_grid_pin_35_[0]:19 bottom_left_grid_pin_35_[0]:18 0.0045 +5 bottom_left_grid_pin_35_[0]:17 bottom_left_grid_pin_35_[0]:16 0.0045 +6 bottom_left_grid_pin_35_[0]:16 bottom_left_grid_pin_35_[0]:15 0.00178125 +7 bottom_left_grid_pin_35_[0]:7 bottom_left_grid_pin_35_[0]:6 0.001694197 +8 bottom_left_grid_pin_35_[0]:7 bottom_left_grid_pin_35_[0]:5 0.003341518 +9 bottom_left_grid_pin_35_[0]:8 bottom_left_grid_pin_35_[0]:7 0.0045 +10 bottom_left_grid_pin_35_[0]:5 mux_bottom_track_13\/mux_l1_in_0_:A1 0.152 +11 bottom_left_grid_pin_35_[0]:10 bottom_left_grid_pin_35_[0]:9 0.0009040179 +12 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_35_[0]:10 0.0045 +13 bottom_left_grid_pin_35_[0]:11 bottom_left_grid_pin_35_[0]:8 0.02147322 +14 bottom_left_grid_pin_35_[0]:9 mux_bottom_track_5\/mux_l1_in_0_:A0 0.152 +15 bottom_left_grid_pin_35_[0]:6 mux_bottom_track_29\/mux_l1_in_0_:A1 0.152 +16 bottom_left_grid_pin_35_[0]:14 bottom_left_grid_pin_35_[0]:13 0.001720982 +17 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:14 0.0045 +18 bottom_left_grid_pin_35_[0]:15 bottom_left_grid_pin_35_[0]:12 0.0085 +19 bottom_left_grid_pin_35_[0]:13 mux_bottom_track_1\/mux_l1_in_0_:A0 0.152 +20 bottom_left_grid_pin_35_[0]:12 bottom_left_grid_pin_35_[0]:11 0.0004107143 + +*END + +*D_NET bottom_left_grid_pin_38_[0] 0.005752614 //LENGTH 44.257 LUMPCC 0.001210767 DR + +*CONN +*P bottom_left_grid_pin_38_[0] I *L 0.29796 *C 29.750 4.760 +*I mux_bottom_track_7\/mux_l1_in_1_:A1 I *L 0.00198 *C 35.060 18.020 +*I mux_bottom_track_3\/mux_l1_in_1_:A1 I *L 0.00198 *C 33.485 25.500 +*I mux_bottom_track_19\/mux_l1_in_0_:A1 I *L 0.00198 *C 38.180 34.340 +*I mux_bottom_track_35\/mux_l1_in_0_:A1 I *L 0.00198 *C 35.520 36.380 +*N bottom_left_grid_pin_38_[0]:5 *C 35.483 36.380 +*N bottom_left_grid_pin_38_[0]:6 *C 35.005 36.380 +*N bottom_left_grid_pin_38_[0]:7 *C 34.960 36.335 +*N bottom_left_grid_pin_38_[0]:8 *C 38.142 34.340 +*N bottom_left_grid_pin_38_[0]:9 *C 35.005 34.340 +*N bottom_left_grid_pin_38_[0]:10 *C 34.960 34.340 +*N bottom_left_grid_pin_38_[0]:11 *C 33.523 25.500 +*N bottom_left_grid_pin_38_[0]:12 *C 34.915 25.500 +*N bottom_left_grid_pin_38_[0]:13 *C 34.960 25.500 +*N bottom_left_grid_pin_38_[0]:14 *C 34.960 18.405 +*N bottom_left_grid_pin_38_[0]:15 *C 34.960 18.360 +*N bottom_left_grid_pin_38_[0]:16 *C 34.960 18.020 +*N bottom_left_grid_pin_38_[0]:17 *C 35.017 18.043 +*N bottom_left_grid_pin_38_[0]:18 *C 32.245 18.020 +*N bottom_left_grid_pin_38_[0]:19 *C 32.200 17.975 +*N bottom_left_grid_pin_38_[0]:20 *C 32.200 4.817 +*N bottom_left_grid_pin_38_[0]:21 *C 32.193 4.760 + +*CAP +0 bottom_left_grid_pin_38_[0] 0.0001553518 +1 mux_bottom_track_7\/mux_l1_in_1_:A1 1e-06 +2 mux_bottom_track_3\/mux_l1_in_1_:A1 1e-06 +3 mux_bottom_track_19\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_35\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_38_[0]:5 6.546342e-05 +6 bottom_left_grid_pin_38_[0]:6 6.546342e-05 +7 bottom_left_grid_pin_38_[0]:7 4.824699e-05 +8 bottom_left_grid_pin_38_[0]:8 0.0002787287 +9 bottom_left_grid_pin_38_[0]:9 0.0002787287 +10 bottom_left_grid_pin_38_[0]:10 0.0004730898 +11 bottom_left_grid_pin_38_[0]:11 0.0001165692 +12 bottom_left_grid_pin_38_[0]:12 0.0001165692 +13 bottom_left_grid_pin_38_[0]:13 0.0007558259 +14 bottom_left_grid_pin_38_[0]:14 0.0003360792 +15 bottom_left_grid_pin_38_[0]:15 6.755049e-05 +16 bottom_left_grid_pin_38_[0]:16 1.747905e-05 +17 bottom_left_grid_pin_38_[0]:17 0.0002250922 +18 bottom_left_grid_pin_38_[0]:18 0.0001777434 +19 bottom_left_grid_pin_38_[0]:19 0.000602257 +20 bottom_left_grid_pin_38_[0]:20 0.000602257 +21 bottom_left_grid_pin_38_[0]:21 0.0001553518 +22 bottom_left_grid_pin_38_[0] prog_clk[0]:311 1.601799e-06 +23 bottom_left_grid_pin_38_[0]:7 prog_clk[0]:147 9.073126e-08 +24 bottom_left_grid_pin_38_[0]:18 prog_clk[0]:218 1.84678e-05 +25 bottom_left_grid_pin_38_[0]:19 prog_clk[0]:218 0.0002241921 +26 bottom_left_grid_pin_38_[0]:19 prog_clk[0]:313 5.522529e-05 +27 bottom_left_grid_pin_38_[0]:20 prog_clk[0]:312 0.0002241921 +28 bottom_left_grid_pin_38_[0]:20 prog_clk[0]:316 5.522529e-05 +29 bottom_left_grid_pin_38_[0]:21 prog_clk[0]:310 1.601799e-06 +30 bottom_left_grid_pin_38_[0]:13 prog_clk[0]:207 1.573869e-06 +31 bottom_left_grid_pin_38_[0]:13 prog_clk[0]:210 2.658388e-05 +32 bottom_left_grid_pin_38_[0]:13 prog_clk[0]:214 9.344667e-06 +33 bottom_left_grid_pin_38_[0]:13 prog_clk[0]:217 9.443211e-07 +34 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:201 1.6646e-06 +35 bottom_left_grid_pin_38_[0]:10 prog_clk[0]:207 9.443211e-07 +36 bottom_left_grid_pin_38_[0]:17 prog_clk[0]:217 1.84678e-05 +37 bottom_left_grid_pin_38_[0]:14 prog_clk[0]:213 9.344667e-06 +38 bottom_left_grid_pin_38_[0]:14 prog_clk[0]:214 2.658388e-05 +39 bottom_left_grid_pin_38_[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.607319e-05 +40 bottom_left_grid_pin_38_[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 9.03309e-05 +41 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 9.03309e-05 +42 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.607319e-05 +43 bottom_left_grid_pin_38_[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 5.60732e-05 +44 bottom_left_grid_pin_38_[0]:13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 6.488196e-05 +45 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 5.60732e-05 +46 bottom_left_grid_pin_38_[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 6.488196e-05 + +*RES +0 bottom_left_grid_pin_38_[0] bottom_left_grid_pin_38_[0]:21 0.0003826583 +1 bottom_left_grid_pin_38_[0]:6 bottom_left_grid_pin_38_[0]:5 0.0004263393 +2 bottom_left_grid_pin_38_[0]:7 bottom_left_grid_pin_38_[0]:6 0.0045 +3 bottom_left_grid_pin_38_[0]:5 mux_bottom_track_35\/mux_l1_in_0_:A1 0.152 +4 bottom_left_grid_pin_38_[0]:18 bottom_left_grid_pin_38_[0]:17 0.002475447 +5 bottom_left_grid_pin_38_[0]:19 bottom_left_grid_pin_38_[0]:18 0.0045 +6 bottom_left_grid_pin_38_[0]:20 bottom_left_grid_pin_38_[0]:19 0.01174777 +7 bottom_left_grid_pin_38_[0]:21 bottom_left_grid_pin_38_[0]:20 0.00341 +8 bottom_left_grid_pin_38_[0]:12 bottom_left_grid_pin_38_[0]:11 0.001243304 +9 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:12 0.0045 +10 bottom_left_grid_pin_38_[0]:13 bottom_left_grid_pin_38_[0]:10 0.007892858 +11 bottom_left_grid_pin_38_[0]:11 mux_bottom_track_3\/mux_l1_in_1_:A1 0.152 +12 bottom_left_grid_pin_38_[0]:8 mux_bottom_track_19\/mux_l1_in_0_:A1 0.152 +13 bottom_left_grid_pin_38_[0]:9 bottom_left_grid_pin_38_[0]:8 0.00280134 +14 bottom_left_grid_pin_38_[0]:10 bottom_left_grid_pin_38_[0]:9 0.0045 +15 bottom_left_grid_pin_38_[0]:10 bottom_left_grid_pin_38_[0]:7 0.00178125 +16 bottom_left_grid_pin_38_[0]:17 mux_bottom_track_7\/mux_l1_in_1_:A1 0.152 +17 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_38_[0]:16 5.133928e-05 +18 bottom_left_grid_pin_38_[0]:17 bottom_left_grid_pin_38_[0]:15 0.0001725544 +19 bottom_left_grid_pin_38_[0]:15 bottom_left_grid_pin_38_[0]:14 0.0045 +20 bottom_left_grid_pin_38_[0]:14 bottom_left_grid_pin_38_[0]:13 0.006334822 + +*END + +*D_NET chanx_left_in[0] 0.01487781 //LENGTH 95.220 LUMPCC 0.006048317 DR + +*CONN +*P chanx_left_in[0] I *L 0.29796 *C 1.305 39.440 +*I mux_bottom_track_39\/mux_l1_in_0_:A0 I *L 0.001631 *C 82.055 26.520 +*N chanx_left_in[0]:2 *C 82.055 26.520 +*N chanx_left_in[0]:3 *C 81.880 26.520 +*N chanx_left_in[0]:4 *C 81.880 26.565 +*N chanx_left_in[0]:5 *C 81.880 33.263 +*N chanx_left_in[0]:6 *C 81.873 33.320 +*N chanx_left_in[0]:7 *C 64.407 33.320 +*N chanx_left_in[0]:8 *C 64.400 33.378 +*N chanx_left_in[0]:9 *C 64.400 38.703 +*N chanx_left_in[0]:10 *C 64.392 38.760 +*N chanx_left_in[0]:11 *C 51.230 38.760 +*N chanx_left_in[0]:12 *C 1.380 38.760 + +*CAP +0 chanx_left_in[0] 4.02044e-05 +1 mux_bottom_track_39\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[0]:2 5.826604e-05 +3 chanx_left_in[0]:3 6.302881e-05 +4 chanx_left_in[0]:4 0.0004675188 +5 chanx_left_in[0]:5 0.0004675188 +6 chanx_left_in[0]:6 0.0007291356 +7 chanx_left_in[0]:7 0.0007291356 +8 chanx_left_in[0]:8 0.0002962838 +9 chanx_left_in[0]:9 0.0002962838 +10 chanx_left_in[0]:10 0.0007933025 +11 chanx_left_in[0]:11 0.002820457 +12 chanx_left_in[0]:12 0.002067358 +13 chanx_left_in[0]:12 chany_bottom_in[15]:10 0.0004600522 +14 chanx_left_in[0]:11 chany_bottom_in[15]:11 0.0004600522 +15 chanx_left_in[0]:6 prog_clk[0]:248 0.00010292 +16 chanx_left_in[0]:6 prog_clk[0]:288 2.598099e-05 +17 chanx_left_in[0]:7 prog_clk[0]:288 0.00010292 +18 chanx_left_in[0]:7 prog_clk[0]:289 2.598099e-05 +19 chanx_left_in[0]:10 prog_clk[0]:156 0.0001577753 +20 chanx_left_in[0]:12 prog_clk[0]:157 0.0003061301 +21 chanx_left_in[0]:11 prog_clk[0]:156 0.0003061301 +22 chanx_left_in[0]:11 prog_clk[0]:157 0.0001577753 +23 chanx_left_in[0]:6 chanx_left_in[12]:6 0.0003756417 +24 chanx_left_in[0]:7 chanx_left_in[12]:7 0.0003756417 +25 chanx_left_in[0]:10 chanx_left_in[12]:6 2.794572e-05 +26 chanx_left_in[0]:10 chanx_left_in[12]:7 2.734665e-06 +27 chanx_left_in[0]:12 chanx_left_in[12]:8 1.804598e-06 +28 chanx_left_in[0]:11 chanx_left_in[12]:8 2.734665e-06 +29 chanx_left_in[0]:11 chanx_left_in[12]:7 2.975032e-05 +30 chanx_left_in[0]:12 chanx_left_in[18] 0.0001081598 +31 chanx_left_in[0]:12 chanx_left_in[18]:6 0.0001779517 +32 chanx_left_in[0]:11 chanx_left_in[18]:5 0.0001779517 +33 chanx_left_in[0]:11 chanx_left_in[18]:7 0.0001081598 +34 chanx_left_in[0] optlc_net_109:10 9.326922e-06 +35 chanx_left_in[0]:12 optlc_net_109:15 0.0007827498 +36 chanx_left_in[0]:12 optlc_net_109:9 9.326922e-06 +37 chanx_left_in[0]:12 optlc_net_109:20 0.0004849847 +38 chanx_left_in[0]:11 optlc_net_109:21 0.0004849847 +39 chanx_left_in[0]:11 optlc_net_109:20 0.0007827498 + +*RES +0 chanx_left_in[0] chanx_left_in[0]:12 0.0001065333 +1 chanx_left_in[0]:2 mux_bottom_track_39\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[0]:3 chanx_left_in[0]:2 9.51087e-05 +3 chanx_left_in[0]:4 chanx_left_in[0]:3 0.0045 +4 chanx_left_in[0]:5 chanx_left_in[0]:4 0.005979911 +5 chanx_left_in[0]:6 chanx_left_in[0]:5 0.00341 +6 chanx_left_in[0]:8 chanx_left_in[0]:7 0.00341 +7 chanx_left_in[0]:7 chanx_left_in[0]:6 0.002736183 +8 chanx_left_in[0]:9 chanx_left_in[0]:8 0.004754464 +9 chanx_left_in[0]:10 chanx_left_in[0]:9 0.00341 +10 chanx_left_in[0]:12 chanx_left_in[0]:11 0.007809833 +11 chanx_left_in[0]:11 chanx_left_in[0]:10 0.002062125 + +*END + +*D_NET chanx_left_in[1] 0.004681818 //LENGTH 25.890 LUMPCC 0.002422445 DR + +*CONN +*P chanx_left_in[1] I *L 0.29796 *C 1.230 42.160 +*I mux_bottom_track_1\/mux_l1_in_2_:A0 I *L 0.001631 *C 21.945 44.540 +*N chanx_left_in[1]:2 *C 21.945 44.540 +*N chanx_left_in[1]:3 *C 21.945 44.880 +*N chanx_left_in[1]:4 *C 22.495 44.880 +*N chanx_left_in[1]:5 *C 22.540 44.835 +*N chanx_left_in[1]:6 *C 22.540 42.218 +*N chanx_left_in[1]:7 *C 22.533 42.160 + +*CAP +0 chanx_left_in[1] 0.0008506981 +1 mux_bottom_track_1\/mux_l1_in_2_:A0 1e-06 +2 chanx_left_in[1]:2 5.808281e-05 +3 chanx_left_in[1]:3 8.810287e-05 +4 chanx_left_in[1]:4 5.988359e-05 +5 chanx_left_in[1]:5 0.0001754533 +6 chanx_left_in[1]:6 0.0001754533 +7 chanx_left_in[1]:7 0.0008506981 +8 chanx_left_in[1] chany_bottom_in[2]:6 0.0007104221 +9 chanx_left_in[1]:7 chany_bottom_in[2]:7 0.0007104221 +10 chanx_left_in[1] chany_bottom_in[14]:6 0.0005008007 +11 chanx_left_in[1]:7 chany_bottom_in[14]:7 0.0005008007 + +*RES +0 chanx_left_in[1] chanx_left_in[1]:7 0.003337391 +1 chanx_left_in[1]:6 chanx_left_in[1]:5 0.002337054 +2 chanx_left_in[1]:7 chanx_left_in[1]:6 0.00341 +3 chanx_left_in[1]:4 chanx_left_in[1]:3 0.0004910714 +4 chanx_left_in[1]:5 chanx_left_in[1]:4 0.0045 +5 chanx_left_in[1]:2 mux_bottom_track_1\/mux_l1_in_2_:A0 0.152 +6 chanx_left_in[1]:3 chanx_left_in[1]:2 0.0003035715 + +*END + +*D_NET chanx_left_in[4] 0.0138557 //LENGTH 75.815 LUMPCC 0.008714427 DR + +*CONN +*P chanx_left_in[4] I *L 0.29796 *C 1.230 50.320 +*I mux_bottom_track_7\/mux_l2_in_1_:A1 I *L 0.00198 *C 33.680 9.180 +*N chanx_left_in[4]:2 *C 33.642 9.180 +*N chanx_left_in[4]:3 *C 32.705 9.180 +*N chanx_left_in[4]:4 *C 32.660 9.225 +*N chanx_left_in[4]:5 *C 32.660 15.583 +*N chanx_left_in[4]:6 *C 32.653 15.640 +*N chanx_left_in[4]:7 *C 30.380 15.640 +*N chanx_left_in[4]:8 *C 30.360 15.648 +*N chanx_left_in[4]:9 *C 30.360 45.553 +*N chanx_left_in[4]:10 *C 30.340 45.560 +*N chanx_left_in[4]:11 *C 5.067 45.560 +*N chanx_left_in[4]:12 *C 5.060 45.617 +*N chanx_left_in[4]:13 *C 5.060 50.263 +*N chanx_left_in[4]:14 *C 5.053 50.320 + +*CAP +0 chanx_left_in[4] 0.0002869805 +1 mux_bottom_track_7\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[4]:2 8.4551e-05 +3 chanx_left_in[4]:3 8.4551e-05 +4 chanx_left_in[4]:4 0.000444408 +5 chanx_left_in[4]:5 0.000444408 +6 chanx_left_in[4]:6 0.000143804 +7 chanx_left_in[4]:7 0.000143804 +8 chanx_left_in[4]:8 0.000931953 +9 chanx_left_in[4]:9 0.000931953 +10 chanx_left_in[4]:10 0.0005153645 +11 chanx_left_in[4]:11 0.0005153645 +12 chanx_left_in[4]:12 0.0001630736 +13 chanx_left_in[4]:13 0.0001630736 +14 chanx_left_in[4]:14 0.0002869805 +15 chanx_left_in[4]:10 chany_bottom_in[6]:11 0.0003584802 +16 chanx_left_in[4]:12 chany_bottom_in[6]:5 4.844474e-05 +17 chanx_left_in[4]:11 chany_bottom_in[6]:10 0.0003584802 +18 chanx_left_in[4]:13 chany_bottom_in[6]:4 4.844474e-05 +19 chanx_left_in[4]:6 bottom_left_grid_pin_39_[0]:20 5.79113e-08 +20 chanx_left_in[4]:6 bottom_left_grid_pin_39_[0]:31 9.075043e-07 +21 chanx_left_in[4]:7 bottom_left_grid_pin_39_[0] 9.075043e-07 +22 chanx_left_in[4]:7 bottom_left_grid_pin_39_[0]:31 5.79113e-08 +23 chanx_left_in[4]:8 bottom_left_grid_pin_39_[0]:30 0.0008258556 +24 chanx_left_in[4]:9 bottom_left_grid_pin_39_[0]:29 0.0008258556 +25 chanx_left_in[4]:6 bottom_left_grid_pin_41_[0]:9 4.596844e-05 +26 chanx_left_in[4]:6 bottom_left_grid_pin_41_[0]:33 5.010757e-06 +27 chanx_left_in[4]:7 bottom_left_grid_pin_41_[0] 5.010757e-06 +28 chanx_left_in[4]:7 bottom_left_grid_pin_41_[0]:33 4.596844e-05 +29 chanx_left_in[4]:8 bottom_left_grid_pin_41_[0]:30 0.0009450339 +30 chanx_left_in[4]:10 bottom_left_grid_pin_41_[0]:22 0.0002470788 +31 chanx_left_in[4]:9 bottom_left_grid_pin_41_[0]:29 0.0009450339 +32 chanx_left_in[4]:11 bottom_left_grid_pin_41_[0]:21 0.0002470788 +33 chanx_left_in[4] chanx_left_in[5] 6.670006e-07 +34 chanx_left_in[4]:10 chanx_left_in[5]:8 0.001428168 +35 chanx_left_in[4]:11 chanx_left_in[5] 0.001428168 +36 chanx_left_in[4]:14 chanx_left_in[5]:8 6.670006e-07 +37 chanx_left_in[4]:12 ropt_net_129:7 0.0001295266 +38 chanx_left_in[4]:13 ropt_net_129:6 0.0001295266 +39 chanx_left_in[4]:10 ropt_net_130:10 0.0003220137 +40 chanx_left_in[4]:11 ropt_net_130:9 0.0003220137 + +*RES +0 chanx_left_in[4] chanx_left_in[4]:14 0.0005988582 +1 chanx_left_in[4]:2 mux_bottom_track_7\/mux_l2_in_1_:A1 0.152 +2 chanx_left_in[4]:3 chanx_left_in[4]:2 0.0008370536 +3 chanx_left_in[4]:4 chanx_left_in[4]:3 0.0045 +4 chanx_left_in[4]:5 chanx_left_in[4]:4 0.005676339 +5 chanx_left_in[4]:6 chanx_left_in[4]:5 0.00341 +6 chanx_left_in[4]:7 chanx_left_in[4]:6 0.000356025 +7 chanx_left_in[4]:8 chanx_left_in[4]:7 0.00341 +8 chanx_left_in[4]:10 chanx_left_in[4]:9 0.00341 +9 chanx_left_in[4]:9 chanx_left_in[4]:8 0.004685116 +10 chanx_left_in[4]:12 chanx_left_in[4]:11 0.00341 +11 chanx_left_in[4]:11 chanx_left_in[4]:10 0.003959358 +12 chanx_left_in[4]:13 chanx_left_in[4]:12 0.004147321 +13 chanx_left_in[4]:14 chanx_left_in[4]:13 0.00341 + +*END + +*D_NET chanx_left_in[8] 0.00546076 //LENGTH 49.645 LUMPCC 0.0002445703 DR + +*CONN +*P chanx_left_in[8] I *L 0.29796 *C 1.230 76.160 +*I mux_bottom_track_15\/mux_l1_in_0_:A0 I *L 0.001631 *C 32.800 60.860 +*N chanx_left_in[8]:2 *C 32.763 60.860 +*N chanx_left_in[8]:3 *C 24.425 60.860 +*N chanx_left_in[8]:4 *C 24.380 60.905 +*N chanx_left_in[8]:5 *C 24.380 76.782 +*N chanx_left_in[8]:6 *C 24.373 76.840 +*N chanx_left_in[8]:7 *C 5.520 76.840 +*N chanx_left_in[8]:8 *C 5.520 76.160 + +*CAP +0 chanx_left_in[8] 0.0003038458 +1 mux_bottom_track_15\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[8]:2 0.0004249949 +3 chanx_left_in[8]:3 0.0004249949 +4 chanx_left_in[8]:4 0.0008100354 +5 chanx_left_in[8]:5 0.0008100354 +6 chanx_left_in[8]:6 0.001011199 +7 chanx_left_in[8]:7 0.001068719 +8 chanx_left_in[8]:8 0.0003613663 +9 chanx_left_in[8]:5 mux_tree_tapbuf_size2_8_sram[1]:7 7.388297e-06 +10 chanx_left_in[8]:5 mux_tree_tapbuf_size2_8_sram[1]:11 2.124166e-07 +11 chanx_left_in[8]:3 mux_tree_tapbuf_size2_8_sram[1]:8 0.0001146844 +12 chanx_left_in[8]:4 mux_tree_tapbuf_size2_8_sram[1]:6 7.388297e-06 +13 chanx_left_in[8]:4 mux_tree_tapbuf_size2_8_sram[1]:10 2.124166e-07 +14 chanx_left_in[8]:2 mux_tree_tapbuf_size2_8_sram[1]:9 0.0001146844 + +*RES +0 chanx_left_in[8] chanx_left_in[8]:8 0.0006720999 +1 chanx_left_in[8]:5 chanx_left_in[8]:4 0.01417634 +2 chanx_left_in[8]:6 chanx_left_in[8]:5 0.00341 +3 chanx_left_in[8]:3 chanx_left_in[8]:2 0.007444196 +4 chanx_left_in[8]:4 chanx_left_in[8]:3 0.0045 +5 chanx_left_in[8]:2 mux_bottom_track_15\/mux_l1_in_0_:A0 0.152 +6 chanx_left_in[8]:8 chanx_left_in[8]:7 0.0001065333 +7 chanx_left_in[8]:7 chanx_left_in[8]:6 0.002953558 + +*END + +*D_NET chanx_left_in[12] 0.01401951 //LENGTH 107.000 LUMPCC 0.003678858 DR + +*CONN +*P chanx_left_in[12] I *L 0.29796 *C 1.230 32.640 +*I mux_bottom_track_23\/mux_l1_in_0_:A0 I *L 0.001631 *C 91.370 21.080 +*N chanx_left_in[12]:2 *C 91.370 21.080 +*N chanx_left_in[12]:3 *C 91.080 21.080 +*N chanx_left_in[12]:4 *C 91.080 21.125 +*N chanx_left_in[12]:5 *C 91.080 34.623 +*N chanx_left_in[12]:6 *C 91.073 34.680 +*N chanx_left_in[12]:7 *C 55.330 34.680 +*N chanx_left_in[12]:8 *C 5.540 34.680 +*N chanx_left_in[12]:9 *C 5.520 34.672 +*N chanx_left_in[12]:10 *C 5.520 32.648 +*N chanx_left_in[12]:11 *C 5.500 32.640 + +*CAP +0 chanx_left_in[12] 0.0002981937 +1 mux_bottom_track_23\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[12]:2 4.758951e-05 +3 chanx_left_in[12]:3 5.125635e-05 +4 chanx_left_in[12]:4 0.0006986137 +5 chanx_left_in[12]:5 0.0006986137 +6 chanx_left_in[12]:6 0.001942675 +7 chanx_left_in[12]:7 0.003911955 +8 chanx_left_in[12]:8 0.00196928 +9 chanx_left_in[12]:9 0.0002116397 +10 chanx_left_in[12]:10 0.0002116397 +11 chanx_left_in[12]:11 0.0002981937 +12 chanx_left_in[12]:6 prog_clk[0]:248 2.048434e-06 +13 chanx_left_in[12]:6 prog_clk[0]:275 2.568112e-05 +14 chanx_left_in[12]:6 prog_clk[0]:281 4.727429e-06 +15 chanx_left_in[12]:6 prog_clk[0]:288 4.278239e-06 +16 chanx_left_in[12]:8 prog_clk[0]:186 0.0001198588 +17 chanx_left_in[12]:8 prog_clk[0]:199 0.0001212759 +18 chanx_left_in[12]:8 prog_clk[0]:200 4.209299e-06 +19 chanx_left_in[12]:7 prog_clk[0]:172 4.209299e-06 +20 chanx_left_in[12]:7 prog_clk[0]:199 0.0001198588 +21 chanx_left_in[12]:7 prog_clk[0]:200 0.0001212759 +22 chanx_left_in[12]:7 prog_clk[0]:276 2.568112e-05 +23 chanx_left_in[12]:7 prog_clk[0]:282 4.727429e-06 +24 chanx_left_in[12]:7 prog_clk[0]:288 2.048434e-06 +25 chanx_left_in[12]:7 prog_clk[0]:289 4.278239e-06 +26 chanx_left_in[12]:6 chanx_left_in[0]:6 0.0003756417 +27 chanx_left_in[12]:6 chanx_left_in[0]:10 2.794572e-05 +28 chanx_left_in[12]:8 chanx_left_in[0]:11 2.734665e-06 +29 chanx_left_in[12]:8 chanx_left_in[0]:12 1.804598e-06 +30 chanx_left_in[12]:7 chanx_left_in[0]:7 0.0003756417 +31 chanx_left_in[12]:7 chanx_left_in[0]:10 2.734665e-06 +32 chanx_left_in[12]:7 chanx_left_in[0]:11 2.975032e-05 +33 chanx_left_in[12] chanx_left_in[10] 2.418709e-06 +34 chanx_left_in[12]:8 chanx_left_in[10] 0.0003329268 +35 chanx_left_in[12]:11 chanx_left_in[10]:6 2.418709e-06 +36 chanx_left_in[12]:7 chanx_left_in[10]:6 0.0003329268 +37 chanx_left_in[12]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0003908988 +38 chanx_left_in[12]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0003908988 +39 chanx_left_in[12]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0004229784 +40 chanx_left_in[12]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0004229784 + +*RES +0 chanx_left_in[12] chanx_left_in[12]:11 0.0006689666 +1 chanx_left_in[12]:2 mux_bottom_track_23\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[12]:3 chanx_left_in[12]:2 0.0001576087 +3 chanx_left_in[12]:4 chanx_left_in[12]:3 0.0045 +4 chanx_left_in[12]:5 chanx_left_in[12]:4 0.01205134 +5 chanx_left_in[12]:6 chanx_left_in[12]:5 0.00341 +6 chanx_left_in[12]:8 chanx_left_in[12]:7 0.007800432 +7 chanx_left_in[12]:9 chanx_left_in[12]:8 0.00341 +8 chanx_left_in[12]:11 chanx_left_in[12]:10 0.00341 +9 chanx_left_in[12]:10 chanx_left_in[12]:9 0.00031725 +10 chanx_left_in[12]:7 chanx_left_in[12]:6 0.005599658 + +*END + +*D_NET ccff_head[0] 0.00315617 //LENGTH 31.540 LUMPCC 0 DR + +*CONN +*P ccff_head[0] I *L 0.29796 *C 18.860 102.070 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 18.115 71.740 +*N ccff_head[0]:2 *C 18.152 71.740 +*N ccff_head[0]:3 *C 18.815 71.740 +*N ccff_head[0]:4 *C 18.860 71.785 + +*CAP +0 ccff_head[0] 0.001513756 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 ccff_head[0]:2 6.382902e-05 +3 ccff_head[0]:3 6.382902e-05 +4 ccff_head[0]:4 0.001513756 + +*RES +0 ccff_head[0] ccff_head[0]:4 0.02704018 +1 ccff_head[0]:2 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 ccff_head[0]:3 ccff_head[0]:2 0.0005915179 +3 ccff_head[0]:4 ccff_head[0]:3 0.0045 + +*END + +*D_NET ropt_net_122 0.0006470133 //LENGTH 5.645 LUMPCC 7.599637e-05 DR + +*CONN +*I mux_bottom_track_9\/BUFT_P_83:X O *L 0 *C 92.920 4.080 +*I ropt_mt_inst_737:A I *L 0.001766 *C 95.220 6.800 +*N ropt_net_122:2 *C 95.220 6.800 +*N ropt_net_122:3 *C 95.220 6.755 +*N ropt_net_122:4 *C 95.220 4.125 +*N ropt_net_122:5 *C 95.175 4.080 +*N ropt_net_122:6 *C 92.958 4.080 + +*CAP +0 mux_bottom_track_9\/BUFT_P_83:X 1e-06 +1 ropt_mt_inst_737:A 1e-06 +2 ropt_net_122:2 3.867609e-05 +3 ropt_net_122:3 0.0001192671 +4 ropt_net_122:4 0.0001192671 +5 ropt_net_122:5 0.0001459034 +6 ropt_net_122:6 0.0001459034 +7 ropt_net_122:3 chany_bottom_in[6]:13 3.799818e-05 +8 ropt_net_122:4 chany_bottom_in[6] 3.799818e-05 + +*RES +0 mux_bottom_track_9\/BUFT_P_83:X ropt_net_122:6 0.152 +1 ropt_net_122:2 ropt_mt_inst_737:A 0.152 +2 ropt_net_122:3 ropt_net_122:2 0.0045 +3 ropt_net_122:5 ropt_net_122:4 0.0045 +4 ropt_net_122:4 ropt_net_122:3 0.002348214 +5 ropt_net_122:6 ropt_net_122:5 0.001979911 + +*END + +*D_NET chany_bottom_out[13] 0.0006579565 //LENGTH 4.710 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 63.020 4.080 +*P chany_bottom_out[13] O *L 0.7423 *C 61.640 1.325 +*N chany_bottom_out[13]:2 *C 61.640 3.695 +*N chany_bottom_out[13]:3 *C 61.685 3.740 +*N chany_bottom_out[13]:4 *C 63.020 3.740 +*N chany_bottom_out[13]:5 *C 63.020 4.080 + +*CAP +0 mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[13] 0.0001609001 +2 chany_bottom_out[13]:2 0.0001609001 +3 chany_bottom_out[13]:3 0.0001261199 +4 chany_bottom_out[13]:4 0.0001534813 +5 chany_bottom_out[13]:5 5.55552e-05 + +*RES +0 mux_bottom_track_27\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[13]:5 0.152 +1 chany_bottom_out[13]:3 chany_bottom_out[13]:2 0.0045 +2 chany_bottom_out[13]:2 chany_bottom_out[13] 0.002116072 +3 chany_bottom_out[13]:5 chany_bottom_out[13]:4 0.0003035715 +4 chany_bottom_out[13]:4 chany_bottom_out[13]:3 0.001191964 + +*END + +*D_NET chanx_left_out[4] 0.0009982099 //LENGTH 7.310 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 5.005 61.200 +*P chanx_left_out[4] O *L 0.7423 *C 1.230 58.480 +*N chanx_left_out[4]:2 *C 3.673 58.480 +*N chanx_left_out[4]:3 *C 3.680 58.538 +*N chanx_left_out[4]:4 *C 3.680 61.155 +*N chanx_left_out[4]:5 *C 3.725 61.200 +*N chanx_left_out[4]:6 *C 4.968 61.200 + +*CAP +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[4] 0.0001854717 +2 chanx_left_out[4]:2 0.0001854717 +3 chanx_left_out[4]:3 0.0002254711 +4 chanx_left_out[4]:4 0.0002254711 +5 chanx_left_out[4]:5 8.766215e-05 +6 chanx_left_out[4]:6 8.766215e-05 + +*RES +0 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[4]:6 0.152 +1 chanx_left_out[4]:6 chanx_left_out[4]:5 0.001109375 +2 chanx_left_out[4]:5 chanx_left_out[4]:4 0.0045 +3 chanx_left_out[4]:4 chanx_left_out[4]:3 0.002337054 +4 chanx_left_out[4]:3 chanx_left_out[4]:2 0.00341 +5 chanx_left_out[4]:2 chanx_left_out[4] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[0] 0.00203123 //LENGTH 16.315 LUMPCC 0.000116908 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 41.245 53.040 +*I mux_bottom_track_33\/mux_l1_in_0_:S I *L 0.00357 *C 36.000 56.100 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 43.875 49.980 +*N mux_tree_tapbuf_size2_10_sram[0]:3 *C 43.875 49.980 +*N mux_tree_tapbuf_size2_10_sram[0]:4 *C 43.700 49.980 +*N mux_tree_tapbuf_size2_10_sram[0]:5 *C 43.700 50.025 +*N mux_tree_tapbuf_size2_10_sram[0]:6 *C 43.700 52.655 +*N mux_tree_tapbuf_size2_10_sram[0]:7 *C 43.655 52.700 +*N mux_tree_tapbuf_size2_10_sram[0]:8 *C 40.940 52.700 +*N mux_tree_tapbuf_size2_10_sram[0]:9 *C 36.038 56.100 +*N mux_tree_tapbuf_size2_10_sram[0]:10 *C 36.755 56.100 +*N mux_tree_tapbuf_size2_10_sram[0]:11 *C 36.800 56.055 +*N mux_tree_tapbuf_size2_10_sram[0]:12 *C 36.800 53.425 +*N mux_tree_tapbuf_size2_10_sram[0]:13 *C 36.845 53.380 +*N mux_tree_tapbuf_size2_10_sram[0]:14 *C 40.020 53.380 +*N mux_tree_tapbuf_size2_10_sram[0]:15 *C 40.020 53.040 +*N mux_tree_tapbuf_size2_10_sram[0]:16 *C 40.940 53.028 +*N mux_tree_tapbuf_size2_10_sram[0]:17 *C 41.218 52.995 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_33\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_10_sram[0]:3 4.713617e-05 +4 mux_tree_tapbuf_size2_10_sram[0]:4 5.136854e-05 +5 mux_tree_tapbuf_size2_10_sram[0]:5 0.0001625302 +6 mux_tree_tapbuf_size2_10_sram[0]:6 0.0001625302 +7 mux_tree_tapbuf_size2_10_sram[0]:7 0.0001800801 +8 mux_tree_tapbuf_size2_10_sram[0]:8 0.0002046934 +9 mux_tree_tapbuf_size2_10_sram[0]:9 5.775681e-05 +10 mux_tree_tapbuf_size2_10_sram[0]:10 5.775681e-05 +11 mux_tree_tapbuf_size2_10_sram[0]:11 0.0001307025 +12 mux_tree_tapbuf_size2_10_sram[0]:12 0.0001307025 +13 mux_tree_tapbuf_size2_10_sram[0]:13 0.0002103172 +14 mux_tree_tapbuf_size2_10_sram[0]:14 0.0002326471 +15 mux_tree_tapbuf_size2_10_sram[0]:15 0.0001011411 +16 mux_tree_tapbuf_size2_10_sram[0]:16 0.0001426921 +17 mux_tree_tapbuf_size2_10_sram[0]:17 3.926756e-05 +18 mux_tree_tapbuf_size2_10_sram[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 7.191766e-06 +19 mux_tree_tapbuf_size2_10_sram[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.191766e-06 +20 mux_tree_tapbuf_size2_10_sram[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.126222e-05 +21 mux_tree_tapbuf_size2_10_sram[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.126222e-05 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_10_sram[0]:17 0.152 +1 mux_tree_tapbuf_size2_10_sram[0]:9 mux_bottom_track_33\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_10_sram[0]:10 mux_tree_tapbuf_size2_10_sram[0]:9 0.000640625 +3 mux_tree_tapbuf_size2_10_sram[0]:11 mux_tree_tapbuf_size2_10_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size2_10_sram[0]:13 mux_tree_tapbuf_size2_10_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size2_10_sram[0]:12 mux_tree_tapbuf_size2_10_sram[0]:11 0.002348214 +6 mux_tree_tapbuf_size2_10_sram[0]:7 mux_tree_tapbuf_size2_10_sram[0]:6 0.0045 +7 mux_tree_tapbuf_size2_10_sram[0]:6 mux_tree_tapbuf_size2_10_sram[0]:5 0.002348214 +8 mux_tree_tapbuf_size2_10_sram[0]:4 mux_tree_tapbuf_size2_10_sram[0]:3 9.51087e-05 +9 mux_tree_tapbuf_size2_10_sram[0]:5 mux_tree_tapbuf_size2_10_sram[0]:4 0.0045 +10 mux_tree_tapbuf_size2_10_sram[0]:3 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size2_10_sram[0]:17 mux_tree_tapbuf_size2_10_sram[0]:16 0.0002477679 +12 mux_tree_tapbuf_size2_10_sram[0]:14 mux_tree_tapbuf_size2_10_sram[0]:13 0.002834822 +13 mux_tree_tapbuf_size2_10_sram[0]:15 mux_tree_tapbuf_size2_10_sram[0]:14 0.0003035715 +14 mux_tree_tapbuf_size2_10_sram[0]:16 mux_tree_tapbuf_size2_10_sram[0]:15 0.0008214286 +15 mux_tree_tapbuf_size2_10_sram[0]:16 mux_tree_tapbuf_size2_10_sram[0]:8 0.0002924107 +16 mux_tree_tapbuf_size2_10_sram[0]:8 mux_tree_tapbuf_size2_10_sram[0]:7 0.002424107 + +*END + +*D_NET mux_tree_tapbuf_size2_13_sram[1] 0.001946684 //LENGTH 14.205 LUMPCC 0.0004968737 DR + +*CONN +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 82.645 31.280 +*I mux_bottom_track_39\/mux_l2_in_0_:S I *L 0.00357 *C 85.200 25.840 +*I mem_bottom_track_39\/FTB_20__35:A I *L 0.001746 *C 82.800 36.720 +*N mux_tree_tapbuf_size2_13_sram[1]:3 *C 82.800 36.720 +*N mux_tree_tapbuf_size2_13_sram[1]:4 *C 82.800 36.675 +*N mux_tree_tapbuf_size2_13_sram[1]:5 *C 85.200 25.840 +*N mux_tree_tapbuf_size2_13_sram[1]:6 *C 85.100 26.520 +*N mux_tree_tapbuf_size2_13_sram[1]:7 *C 82.845 26.520 +*N mux_tree_tapbuf_size2_13_sram[1]:8 *C 82.800 26.565 +*N mux_tree_tapbuf_size2_13_sram[1]:9 *C 82.800 31.280 +*N mux_tree_tapbuf_size2_13_sram[1]:10 *C 82.800 31.280 +*N mux_tree_tapbuf_size2_13_sram[1]:11 *C 82.645 31.280 + +*CAP +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_39\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_39\/FTB_20__35:A 1e-06 +3 mux_tree_tapbuf_size2_13_sram[1]:3 3.387361e-05 +4 mux_tree_tapbuf_size2_13_sram[1]:4 0.0002130451 +5 mux_tree_tapbuf_size2_13_sram[1]:5 7.838476e-05 +6 mux_tree_tapbuf_size2_13_sram[1]:6 0.0002562464 +7 mux_tree_tapbuf_size2_13_sram[1]:7 0.0002068272 +8 mux_tree_tapbuf_size2_13_sram[1]:8 0.0001539883 +9 mux_tree_tapbuf_size2_13_sram[1]:9 0.0004007287 +10 mux_tree_tapbuf_size2_13_sram[1]:10 5.43764e-05 +11 mux_tree_tapbuf_size2_13_sram[1]:11 4.933911e-05 +12 mux_tree_tapbuf_size2_13_sram[1]:8 chany_bottom_in[0] 0.0001131313 +13 mux_tree_tapbuf_size2_13_sram[1]:9 chany_bottom_in[0]:11 2.119742e-06 +14 mux_tree_tapbuf_size2_13_sram[1]:9 chany_bottom_in[0]:14 0.0001131313 +15 mux_tree_tapbuf_size2_13_sram[1]:4 chany_bottom_in[0]:10 2.119742e-06 +16 mux_tree_tapbuf_size2_13_sram[1]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.569008e-05 +17 mux_tree_tapbuf_size2_13_sram[1]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.569008e-05 +18 mux_tree_tapbuf_size2_13_sram[1]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 7.749569e-05 +19 mux_tree_tapbuf_size2_13_sram[1]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 7.749569e-05 + +*RES +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_13_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_13_sram[1]:5 mux_bottom_track_39\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_13_sram[1]:7 mux_tree_tapbuf_size2_13_sram[1]:6 0.002013393 +3 mux_tree_tapbuf_size2_13_sram[1]:8 mux_tree_tapbuf_size2_13_sram[1]:7 0.0045 +4 mux_tree_tapbuf_size2_13_sram[1]:10 mux_tree_tapbuf_size2_13_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size2_13_sram[1]:9 mux_tree_tapbuf_size2_13_sram[1]:8 0.004209822 +6 mux_tree_tapbuf_size2_13_sram[1]:9 mux_tree_tapbuf_size2_13_sram[1]:4 0.004816965 +7 mux_tree_tapbuf_size2_13_sram[1]:11 mux_tree_tapbuf_size2_13_sram[1]:10 8.423914e-05 +8 mux_tree_tapbuf_size2_13_sram[1]:3 mem_bottom_track_39\/FTB_20__35:A 0.152 +9 mux_tree_tapbuf_size2_13_sram[1]:4 mux_tree_tapbuf_size2_13_sram[1]:3 0.0045 +10 mux_tree_tapbuf_size2_13_sram[1]:6 mux_tree_tapbuf_size2_13_sram[1]:5 0.0006071429 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[0] 0.004223339 //LENGTH 35.745 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 60.105 61.200 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 36.055 69.700 +*I mux_bottom_track_13\/mux_l1_in_0_:S I *L 0.00357 *C 34.400 67.320 +*N mux_tree_tapbuf_size2_1_sram[0]:3 *C 34.438 67.320 +*N mux_tree_tapbuf_size2_1_sram[0]:4 *C 36.055 69.700 +*N mux_tree_tapbuf_size2_1_sram[0]:5 *C 35.880 69.700 +*N mux_tree_tapbuf_size2_1_sram[0]:6 *C 35.880 69.655 +*N mux_tree_tapbuf_size2_1_sram[0]:7 *C 35.880 67.365 +*N mux_tree_tapbuf_size2_1_sram[0]:8 *C 35.880 67.320 +*N mux_tree_tapbuf_size2_1_sram[0]:9 *C 58.375 67.320 +*N mux_tree_tapbuf_size2_1_sram[0]:10 *C 58.420 67.275 +*N mux_tree_tapbuf_size2_1_sram[0]:11 *C 58.420 61.245 +*N mux_tree_tapbuf_size2_1_sram[0]:12 *C 58.465 61.200 +*N mux_tree_tapbuf_size2_1_sram[0]:13 *C 60.068 61.200 + +*CAP +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_13\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_1_sram[0]:3 0.0001196628 +4 mux_tree_tapbuf_size2_1_sram[0]:4 4.778815e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:5 5.318277e-05 +6 mux_tree_tapbuf_size2_1_sram[0]:6 0.000142152 +7 mux_tree_tapbuf_size2_1_sram[0]:7 0.000142152 +8 mux_tree_tapbuf_size2_1_sram[0]:8 0.001491165 +9 mux_tree_tapbuf_size2_1_sram[0]:9 0.001338835 +10 mux_tree_tapbuf_size2_1_sram[0]:10 0.0003225298 +11 mux_tree_tapbuf_size2_1_sram[0]:11 0.0003225298 +12 mux_tree_tapbuf_size2_1_sram[0]:12 0.000120171 +13 mux_tree_tapbuf_size2_1_sram[0]:13 0.000120171 + +*RES +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_1_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:7 0.0045 +2 mux_tree_tapbuf_size2_1_sram[0]:8 mux_tree_tapbuf_size2_1_sram[0]:3 0.001287946 +3 mux_tree_tapbuf_size2_1_sram[0]:7 mux_tree_tapbuf_size2_1_sram[0]:6 0.002044643 +4 mux_tree_tapbuf_size2_1_sram[0]:5 mux_tree_tapbuf_size2_1_sram[0]:4 9.51087e-05 +5 mux_tree_tapbuf_size2_1_sram[0]:6 mux_tree_tapbuf_size2_1_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size2_1_sram[0]:4 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_1_sram[0]:3 mux_bottom_track_13\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_1_sram[0]:9 mux_tree_tapbuf_size2_1_sram[0]:8 0.02008482 +9 mux_tree_tapbuf_size2_1_sram[0]:10 mux_tree_tapbuf_size2_1_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size2_1_sram[0]:12 mux_tree_tapbuf_size2_1_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size2_1_sram[0]:11 mux_tree_tapbuf_size2_1_sram[0]:10 0.005383929 +12 mux_tree_tapbuf_size2_1_sram[0]:13 mux_tree_tapbuf_size2_1_sram[0]:12 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[1] 0.00172079 //LENGTH 12.225 LUMPCC 0.0004283733 DR + +*CONN +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 69.305 17.340 +*I mux_bottom_track_21\/mux_l2_in_0_:S I *L 0.00357 *C 67.980 14.280 +*I mem_bottom_track_21\/FTB_12__27:A I *L 0.001746 *C 70.380 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:3 *C 70.380 9.520 +*N mux_tree_tapbuf_size2_5_sram[1]:4 *C 70.380 9.565 +*N mux_tree_tapbuf_size2_5_sram[1]:5 *C 68.017 14.280 +*N mux_tree_tapbuf_size2_5_sram[1]:6 *C 70.335 14.280 +*N mux_tree_tapbuf_size2_5_sram[1]:7 *C 70.380 14.280 +*N mux_tree_tapbuf_size2_5_sram[1]:8 *C 70.380 17.295 +*N mux_tree_tapbuf_size2_5_sram[1]:9 *C 70.335 17.340 +*N mux_tree_tapbuf_size2_5_sram[1]:10 *C 69.343 17.340 + +*CAP +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_21\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_21\/FTB_12__27:A 1e-06 +3 mux_tree_tapbuf_size2_5_sram[1]:3 3.296775e-05 +4 mux_tree_tapbuf_size2_5_sram[1]:4 0.0001858634 +5 mux_tree_tapbuf_size2_5_sram[1]:5 0.0002145459 +6 mux_tree_tapbuf_size2_5_sram[1]:6 0.0002145459 +7 mux_tree_tapbuf_size2_5_sram[1]:7 0.000345858 +8 mux_tree_tapbuf_size2_5_sram[1]:8 0.0001271706 +9 mux_tree_tapbuf_size2_5_sram[1]:9 8.423268e-05 +10 mux_tree_tapbuf_size2_5_sram[1]:10 8.423268e-05 +11 mux_tree_tapbuf_size2_5_sram[1]:8 chany_bottom_in[17]:21 8.300375e-05 +12 mux_tree_tapbuf_size2_5_sram[1]:7 chany_bottom_in[17] 8.300375e-05 +13 mux_tree_tapbuf_size2_5_sram[1]:7 chany_bottom_in[17]:21 0.0001311829 +14 mux_tree_tapbuf_size2_5_sram[1]:4 chany_bottom_in[17] 0.0001311829 + +*RES +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_5_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_5_sram[1]:9 mux_tree_tapbuf_size2_5_sram[1]:8 0.0045 +2 mux_tree_tapbuf_size2_5_sram[1]:8 mux_tree_tapbuf_size2_5_sram[1]:7 0.002691964 +3 mux_tree_tapbuf_size2_5_sram[1]:10 mux_tree_tapbuf_size2_5_sram[1]:9 0.0008861608 +4 mux_tree_tapbuf_size2_5_sram[1]:6 mux_tree_tapbuf_size2_5_sram[1]:5 0.002069197 +5 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_5_sram[1]:7 mux_tree_tapbuf_size2_5_sram[1]:4 0.004209822 +7 mux_tree_tapbuf_size2_5_sram[1]:5 mux_bottom_track_21\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_5_sram[1]:3 mem_bottom_track_21\/FTB_12__27:A 0.152 +9 mux_tree_tapbuf_size2_5_sram[1]:4 mux_tree_tapbuf_size2_5_sram[1]:3 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_10_ccff_tail[0] 0.000580609 //LENGTH 4.820 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_33\/FTB_17__32:X O *L 0 *C 36.585 39.100 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 41.115 39.100 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 *C 41.078 39.100 +*N mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 *C 36.623 39.100 + +*CAP +0 mem_bottom_track_33\/FTB_17__32:X 1e-06 +1 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 0.0002893045 +3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 0.0002893045 + +*RES +0 mem_bottom_track_33\/FTB_17__32:X mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 0.152 +1 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_10_ccff_tail[0]:2 0.003977679 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_2_ccff_tail[0] 0.000571065 //LENGTH 3.620 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_15\/FTB_9__24:X O *L 0 *C 43.880 58.140 +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 43.880 55.420 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 *C 43.880 55.420 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 *C 44.160 55.420 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 *C 44.160 55.465 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 *C 44.160 58.095 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 *C 44.160 58.140 +*N mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 *C 43.880 58.140 + +*CAP +0 mem_bottom_track_15\/FTB_9__24:X 1e-06 +1 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 6.491821e-05 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 6.642425e-05 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.0001622564 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0001622564 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 5.721549e-05 +7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 5.599433e-05 + +*RES +0 mem_bottom_track_15\/FTB_9__24:X mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:2 0.0001521739 +3 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:4 0.002348214 +6 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_2_ccff_tail[0]:6 0.0001521739 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[1] 0.001123867 //LENGTH 8.515 LUMPCC 0.0001593874 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.565 47.940 +*I mux_bottom_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 17.020 50.485 +*I mem_bottom_track_25\/FTB_6__21:A I *L 0.001746 *C 19.320 47.600 +*N mux_tree_tapbuf_size3_1_sram[1]:3 *C 19.297 47.628 +*N mux_tree_tapbuf_size3_1_sram[1]:4 *C 19.285 47.940 +*N mux_tree_tapbuf_size3_1_sram[1]:5 *C 17.020 50.485 +*N mux_tree_tapbuf_size3_1_sram[1]:6 *C 17.020 50.320 +*N mux_tree_tapbuf_size3_1_sram[1]:7 *C 17.020 50.275 +*N mux_tree_tapbuf_size3_1_sram[1]:8 *C 17.020 47.985 +*N mux_tree_tapbuf_size3_1_sram[1]:9 *C 17.020 47.940 +*N mux_tree_tapbuf_size3_1_sram[1]:10 *C 14.603 47.940 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_25\/FTB_6__21:A 1e-06 +3 mux_tree_tapbuf_size3_1_sram[1]:3 3.587707e-05 +4 mux_tree_tapbuf_size3_1_sram[1]:4 0.0001839464 +5 mux_tree_tapbuf_size3_1_sram[1]:5 4.272946e-05 +6 mux_tree_tapbuf_size3_1_sram[1]:6 4.721207e-05 +7 mux_tree_tapbuf_size3_1_sram[1]:7 0.0001451425 +8 mux_tree_tapbuf_size3_1_sram[1]:8 0.0001451425 +9 mux_tree_tapbuf_size3_1_sram[1]:9 0.000269842 +10 mux_tree_tapbuf_size3_1_sram[1]:10 9.158759e-05 +11 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 7.969369e-05 +12 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 7.969369e-05 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_1_sram[1]:10 0.152 +1 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:8 0.0045 +2 mux_tree_tapbuf_size3_1_sram[1]:9 mux_tree_tapbuf_size3_1_sram[1]:4 0.002022321 +3 mux_tree_tapbuf_size3_1_sram[1]:8 mux_tree_tapbuf_size3_1_sram[1]:7 0.002044643 +4 mux_tree_tapbuf_size3_1_sram[1]:6 mux_tree_tapbuf_size3_1_sram[1]:5 7.11207e-05 +5 mux_tree_tapbuf_size3_1_sram[1]:7 mux_tree_tapbuf_size3_1_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size3_1_sram[1]:5 mux_bottom_track_25\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size3_1_sram[1]:3 mem_bottom_track_25\/FTB_6__21:A 0.152 +8 mux_tree_tapbuf_size3_1_sram[1]:10 mux_tree_tapbuf_size3_1_sram[1]:9 0.002158482 +9 mux_tree_tapbuf_size3_1_sram[1]:4 mux_tree_tapbuf_size3_1_sram[1]:3 0.0002111487 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_0_ccff_tail[0] 0.0004634472 //LENGTH 2.600 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_3\/FTB_3__18:X O *L 0 *C 19.555 38.760 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 19.495 37.060 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 *C 19.495 37.060 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 *C 19.320 37.060 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 *C 19.320 37.105 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 *C 19.320 38.715 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 *C 19.320 38.760 +*N mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 *C 19.555 38.760 + +*CAP +0 mem_bottom_track_3\/FTB_3__18:X 1e-06 +1 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 5.391702e-05 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 5.659746e-05 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0001141514 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0001141514 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 6.266876e-05 +7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 5.996109e-05 + +*RES +0 mem_bottom_track_3\/FTB_3__18:X mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 0.0014375 +4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_0_ccff_tail[0]:2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[1] 0.004116567 //LENGTH 32.175 LUMPCC 0.0003890183 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 40.785 44.540 +*I mux_bottom_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 30.240 40.120 +*I mux_bottom_track_5\/mux_l2_in_1_:S I *L 0.00357 *C 27.960 40.120 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 35.135 28.220 +*N mux_tree_tapbuf_size6_1_sram[1]:4 *C 35.172 28.220 +*N mux_tree_tapbuf_size6_1_sram[1]:5 *C 35.835 28.220 +*N mux_tree_tapbuf_size6_1_sram[1]:6 *C 35.880 28.265 +*N mux_tree_tapbuf_size6_1_sram[1]:7 *C 27.998 40.120 +*N mux_tree_tapbuf_size6_1_sram[1]:8 *C 30.240 40.120 +*N mux_tree_tapbuf_size6_1_sram[1]:9 *C 32.100 40.120 +*N mux_tree_tapbuf_size6_1_sram[1]:10 *C 32.100 39.780 +*N mux_tree_tapbuf_size6_1_sram[1]:11 *C 35.835 39.780 +*N mux_tree_tapbuf_size6_1_sram[1]:12 *C 35.880 39.780 +*N mux_tree_tapbuf_size6_1_sram[1]:13 *C 36.340 39.780 +*N mux_tree_tapbuf_size6_1_sram[1]:14 *C 36.340 44.495 +*N mux_tree_tapbuf_size6_1_sram[1]:15 *C 36.385 44.540 +*N mux_tree_tapbuf_size6_1_sram[1]:16 *C 40.748 44.540 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:S 1e-06 +2 mux_bottom_track_5\/mux_l2_in_1_:S 1e-06 +3 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +4 mux_tree_tapbuf_size6_1_sram[1]:4 7.618011e-05 +5 mux_tree_tapbuf_size6_1_sram[1]:5 7.618011e-05 +6 mux_tree_tapbuf_size6_1_sram[1]:6 0.0005904965 +7 mux_tree_tapbuf_size6_1_sram[1]:7 0.0001381027 +8 mux_tree_tapbuf_size6_1_sram[1]:8 0.0003190339 +9 mux_tree_tapbuf_size6_1_sram[1]:9 0.0001803251 +10 mux_tree_tapbuf_size6_1_sram[1]:10 0.0003045455 +11 mux_tree_tapbuf_size6_1_sram[1]:11 0.0002760526 +12 mux_tree_tapbuf_size6_1_sram[1]:12 0.0006231332 +13 mux_tree_tapbuf_size6_1_sram[1]:13 0.0002987041 +14 mux_tree_tapbuf_size6_1_sram[1]:14 0.0002660674 +15 mux_tree_tapbuf_size6_1_sram[1]:15 0.0002873635 +16 mux_tree_tapbuf_size6_1_sram[1]:16 0.0002873635 +17 mux_tree_tapbuf_size6_1_sram[1]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.756438e-05 +18 mux_tree_tapbuf_size6_1_sram[1]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.756438e-05 +19 mux_tree_tapbuf_size6_1_sram[1]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 9.301902e-07 +20 mux_tree_tapbuf_size6_1_sram[1]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 1.312233e-06 +21 mux_tree_tapbuf_size6_1_sram[1]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001337402 +22 mux_tree_tapbuf_size6_1_sram[1]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 2.810556e-06 +23 mux_tree_tapbuf_size6_1_sram[1]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 1.312233e-06 +24 mux_tree_tapbuf_size6_1_sram[1]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 8.151542e-06 +25 mux_tree_tapbuf_size6_1_sram[1]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 2.810556e-06 +26 mux_tree_tapbuf_size6_1_sram[1]:12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0001337402 +27 mux_tree_tapbuf_size6_1_sram[1]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 9.301902e-07 +28 mux_tree_tapbuf_size6_1_sram[1]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 8.151542e-06 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size6_1_sram[1]:16 0.152 +1 mux_tree_tapbuf_size6_1_sram[1]:8 mux_bottom_track_5\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[1]:8 mux_tree_tapbuf_size6_1_sram[1]:7 0.002002232 +3 mux_tree_tapbuf_size6_1_sram[1]:5 mux_tree_tapbuf_size6_1_sram[1]:4 0.0005915179 +4 mux_tree_tapbuf_size6_1_sram[1]:6 mux_tree_tapbuf_size6_1_sram[1]:5 0.0045 +5 mux_tree_tapbuf_size6_1_sram[1]:4 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +6 mux_tree_tapbuf_size6_1_sram[1]:7 mux_bottom_track_5\/mux_l2_in_1_:S 0.152 +7 mux_tree_tapbuf_size6_1_sram[1]:15 mux_tree_tapbuf_size6_1_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size6_1_sram[1]:14 mux_tree_tapbuf_size6_1_sram[1]:13 0.004209821 +9 mux_tree_tapbuf_size6_1_sram[1]:16 mux_tree_tapbuf_size6_1_sram[1]:15 0.003895089 +10 mux_tree_tapbuf_size6_1_sram[1]:11 mux_tree_tapbuf_size6_1_sram[1]:10 0.003334822 +11 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:11 0.0045 +12 mux_tree_tapbuf_size6_1_sram[1]:12 mux_tree_tapbuf_size6_1_sram[1]:6 0.01028125 +13 mux_tree_tapbuf_size6_1_sram[1]:9 mux_tree_tapbuf_size6_1_sram[1]:8 0.001660714 +14 mux_tree_tapbuf_size6_1_sram[1]:10 mux_tree_tapbuf_size6_1_sram[1]:9 0.0003035715 +15 mux_tree_tapbuf_size6_1_sram[1]:13 mux_tree_tapbuf_size6_1_sram[1]:12 0.0004107143 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001491539 //LENGTH 10.340 LUMPCC 0.0007074292 DR + +*CONN +*I mux_bottom_track_5\/mux_l2_in_0_:X O *L 0 *C 32.945 39.100 +*I mux_bottom_track_5\/mux_l3_in_0_:A1 I *L 0.00198 *C 34.500 30.940 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 34.500 30.940 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 34.500 30.985 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 34.500 39.055 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 34.455 39.100 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 32.983 39.100 + +*CAP +0 mux_bottom_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.315814e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.000291564 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.000291564 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 8.291187e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 8.291187e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 bottom_left_grid_pin_38_[0]:7 5.607319e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 bottom_left_grid_pin_38_[0]:10 9.03309e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 bottom_left_grid_pin_38_[0]:10 5.607319e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 bottom_left_grid_pin_38_[0]:13 9.03309e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 chanx_left_in[10]:5 8.678927e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 chanx_left_in[10]:4 8.678927e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:9 6.686604e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:8 6.686604e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.895881e-05 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:5 4.696396e-06 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:4 4.696396e-06 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.895881e-05 + +*RES +0 mux_bottom_track_5\/mux_l2_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001314732 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.007205358 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_5\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001096345 //LENGTH 7.910 LUMPCC 0.000439161 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_1_:X O *L 0 *C 43.065 17.340 +*I mux_bottom_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 44.795 11.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 44.758 11.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 43.285 11.900 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 43.240 11.945 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 43.240 17.295 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 43.240 17.340 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 43.065 17.340 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001077924 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001077924 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001553717 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001553717 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.466747e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.418844e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[15]:13 0.0001505319 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[15]:12 0.0001505319 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 6.904863e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 6.904863e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_1_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.001314732 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004776786 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0] 0.00115279 //LENGTH 9.540 LUMPCC 0.0002194324 DR + +*CONN +*I mux_bottom_track_17\/mux_l1_in_0_:X O *L 0 *C 37.435 55.080 +*I mux_bottom_track_17\/mux_l2_in_0_:A1 I *L 0.00198 *C 36.340 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 36.340 47.260 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.340 47.305 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.340 55.035 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.385 55.080 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 37.398 55.080 + +*CAP +0 mux_bottom_track_17\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.173299e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003663595 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003663595 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.345266e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 8.345266e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_10_sram[0]:10 7.191766e-06 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_10_sram[0]:9 7.191766e-06 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_10_sram[0]:11 5.126222e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_10_sram[0]:12 5.126222e-05 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 5.126222e-05 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 5.126222e-05 + +*RES +0 mux_bottom_track_17\/mux_l1_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0009040179 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.006901787 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_17\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0007368234 //LENGTH 5.665 LUMPCC 8.967763e-05 DR + +*CONN +*I mux_bottom_track_27\/mux_l1_in_0_:X O *L 0 *C 15.925 51.000 +*I mux_bottom_track_27\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.960 52.700 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.922 52.700 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 17.065 52.700 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 17.020 52.655 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 17.020 51.045 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 16.975 51.000 +*N mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 15.963 51.000 + +*CAP +0 mux_bottom_track_27\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_27\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001046444 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001046444 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001048468 +5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001048468 +6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001130816 +7 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001130816 +8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_7_sram[1]:3 4.060302e-05 +9 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_7_sram[1]:4 4.060302e-05 +10 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_7_sram[1]:8 4.235795e-06 +11 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_7_sram[1]:5 4.235795e-06 + +*RES +0 mux_bottom_track_27\/mux_l1_in_0_:X mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_27\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001658482 +3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0014375 +6 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001047223 //LENGTH 6.895 LUMPCC 0.0001805766 DR + +*CONN +*I mux_bottom_track_31\/mux_l1_in_0_:X O *L 0 *C 24.205 51.000 +*I mux_bottom_track_31\/mux_l2_in_0_:A1 I *L 0.00198 *C 30.360 50.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 30.360 50.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 30.360 51.000 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 24.242 51.000 + +*CAP +0 mux_bottom_track_31\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_31\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.474469e-05 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000417892 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003920094 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_right_grid_pin_1_[0]:5 8.322558e-05 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_right_grid_pin_1_[0]:7 4.995201e-06 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 bottom_right_grid_pin_1_[0]:7 2.067523e-06 +8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_right_grid_pin_1_[0]:6 8.52931e-05 +9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_right_grid_pin_1_[0]:8 4.995201e-06 + +*RES +0 mux_bottom_track_31\/mux_l1_in_0_:X mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.152 +1 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.005462054 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_31\/mux_l2_in_0_:A1 0.152 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0003596409 //LENGTH 2.210 LUMPCC 0.0001371093 DR + +*CONN +*I mux_bottom_track_39\/mux_l1_in_0_:X O *L 0 *C 84.005 25.500 +*I mux_bottom_track_39\/mux_l2_in_0_:A1 I *L 0.00198 *C 85.925 25.500 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 85.888 25.500 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.043 25.500 + +*CAP +0 mux_bottom_track_39\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_39\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001102658 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001102658 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 bottom_left_grid_pin_40_[0]:12 6.855464e-05 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_left_grid_pin_40_[0]:13 6.855464e-05 + +*RES +0 mux_bottom_track_39\/mux_l1_in_0_:X mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_39\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.001647322 + +*END + +*D_NET mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0] 0.007777642 //LENGTH 59.815 LUMPCC 0.002230703 DR + +*CONN +*I mux_left_track_5\/mux_l2_in_0_:X O *L 0 *C 57.215 29.240 +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 5.805 31.445 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 5.843 31.340 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 6.395 31.280 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 6.440 31.235 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 6.440 29.978 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 6.448 29.920 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 13.340 29.920 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 13.340 27.880 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 57.953 27.880 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 57.960 27.938 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 57.960 29.195 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 57.915 29.240 +*N mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 57.253 29.240 + +*CAP +0 mux_left_track_5\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.136329e-05 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.136329e-05 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 8.496013e-05 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 8.496013e-05 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002495751 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003535495 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.002207979 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.002104005 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001111541 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001111541 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:12 6.743707e-05 +13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:13 6.743707e-05 +14 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chany_bottom_in[5]:7 0.0001051872 +15 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[5]:5 3.401814e-06 +16 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[5]:6 0.0003093706 +17 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[5]:4 3.401814e-06 +18 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[5]:7 0.0003093706 +19 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chany_bottom_in[5]:6 0.0001051872 +20 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 bottom_left_grid_pin_40_[0]:17 0.0001959889 +21 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 bottom_left_grid_pin_40_[0]:18 0.0001959889 +22 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_left_in[6]:6 0.0004667513 +23 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_left_in[6]:9 2.416321e-05 +24 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chanx_left_in[6]:10 1.048867e-05 +25 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chanx_left_in[6]:9 1.048867e-05 +26 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_left_in[6]:7 0.0004667513 +27 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_left_in[6]:10 2.416321e-05 + +*RES +0 mux_left_track_5\/mux_l2_in_0_:X mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.152 +1 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0005915179 +2 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0045 +3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001122768 +4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.006989291 +6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001122768 +7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004933036 +9 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +11 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001079825 +12 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003196 + +*END + +*D_NET ropt_net_147 0.0009028087 //LENGTH 6.345 LUMPCC 0.0003928274 DR + +*CONN +*I ropt_mt_inst_731:X O *L 0 *C 4.140 87.720 +*I ropt_mt_inst_766:A I *L 0.001766 *C 7.820 85.680 +*N ropt_net_147:2 *C 7.783 85.680 +*N ropt_net_147:3 *C 4.185 85.680 +*N ropt_net_147:4 *C 4.140 85.725 +*N ropt_net_147:5 *C 4.140 87.675 +*N ropt_net_147:6 *C 4.140 87.720 + +*CAP +0 ropt_mt_inst_731:X 1e-06 +1 ropt_mt_inst_766:A 1e-06 +2 ropt_net_147:2 0.0001380469 +3 ropt_net_147:3 0.0001380469 +4 ropt_net_147:4 0.000101103 +5 ropt_net_147:5 0.000101103 +6 ropt_net_147:6 2.968152e-05 +7 ropt_net_147:2 chany_bottom_in[7]:8 6.890805e-05 +8 ropt_net_147:3 chany_bottom_in[7]:7 6.890805e-05 +9 ropt_net_147:4 chany_bottom_in[7]:6 1.262475e-05 +10 ropt_net_147:5 chany_bottom_in[7]:5 1.262475e-05 +11 ropt_net_147:2 ropt_net_141:4 0.0001146721 +12 ropt_net_147:3 ropt_net_141:3 0.0001146721 +13 ropt_net_147:4 ropt_net_141:6 2.088178e-07 +14 ropt_net_147:5 ropt_net_141:5 2.088178e-07 + +*RES +0 ropt_mt_inst_731:X ropt_net_147:6 0.152 +1 ropt_net_147:2 ropt_mt_inst_766:A 0.152 +2 ropt_net_147:3 ropt_net_147:2 0.003212054 +3 ropt_net_147:4 ropt_net_147:3 0.0045 +4 ropt_net_147:6 ropt_net_147:5 0.0045 +5 ropt_net_147:5 ropt_net_147:4 0.001741072 + +*END + +*D_NET chanx_left_out[3] 0.001747406 //LENGTH 11.960 LUMPCC 0.0001997137 DR + +*CONN +*I ropt_mt_inst_746:X O *L 0 *C 11.695 49.640 +*P chanx_left_out[3] O *L 0.7423 *C 1.230 48.960 +*N chanx_left_out[3]:2 *C 4.593 48.960 +*N chanx_left_out[3]:3 *C 4.600 49.018 +*N chanx_left_out[3]:4 *C 4.600 49.595 +*N chanx_left_out[3]:5 *C 4.645 49.640 +*N chanx_left_out[3]:6 *C 11.658 49.640 + +*CAP +0 ropt_mt_inst_746:X 1e-06 +1 chanx_left_out[3] 0.0002717614 +2 chanx_left_out[3]:2 0.0002717614 +3 chanx_left_out[3]:3 7.265907e-05 +4 chanx_left_out[3]:4 7.265907e-05 +5 chanx_left_out[3]:5 0.0004289255 +6 chanx_left_out[3]:6 0.0004289255 +7 chanx_left_out[3]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.985684e-05 +8 chanx_left_out[3]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.985684e-05 + +*RES +0 ropt_mt_inst_746:X chanx_left_out[3]:6 0.152 +1 chanx_left_out[3]:6 chanx_left_out[3]:5 0.006261161 +2 chanx_left_out[3]:5 chanx_left_out[3]:4 0.0045 +3 chanx_left_out[3]:4 chanx_left_out[3]:3 0.000515625 +4 chanx_left_out[3]:3 chanx_left_out[3]:2 0.00341 +5 chanx_left_out[3]:2 chanx_left_out[3] 0.0005267916 + +*END + +*D_NET chanx_left_out[7] 0.0008972565 //LENGTH 7.235 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_750:X O *L 0 *C 4.140 51.000 +*P chanx_left_out[7] O *L 0.7423 *C 1.298 47.600 +*N chanx_left_out[7]:2 *C 1.380 47.600 +*N chanx_left_out[7]:3 *C 1.380 47.600 +*N chanx_left_out[7]:4 *C 2.300 47.600 +*N chanx_left_out[7]:5 *C 2.300 50.955 +*N chanx_left_out[7]:6 *C 2.345 51.000 +*N chanx_left_out[7]:7 *C 4.103 51.000 + +*CAP +0 ropt_mt_inst_750:X 1e-06 +1 chanx_left_out[7] 3.658236e-05 +2 chanx_left_out[7]:2 3.658236e-05 +3 chanx_left_out[7]:3 9.551602e-05 +4 chanx_left_out[7]:4 0.0002546858 +5 chanx_left_out[7]:5 0.0001958479 +6 chanx_left_out[7]:6 0.0001385211 +7 chanx_left_out[7]:7 0.0001385211 + +*RES +0 ropt_mt_inst_750:X chanx_left_out[7]:7 0.152 +1 chanx_left_out[7]:7 chanx_left_out[7]:6 0.001569197 +2 chanx_left_out[7]:6 chanx_left_out[7]:5 0.0045 +3 chanx_left_out[7]:5 chanx_left_out[7]:4 0.002995536 +4 chanx_left_out[7]:3 chanx_left_out[7]:2 0.00341 +5 chanx_left_out[7]:2 chanx_left_out[7] 2.35e-05 +6 chanx_left_out[7]:4 chanx_left_out[7]:3 0.0008214285 + +*END + +*D_NET chany_bottom_out[14] 0.0005416964 //LENGTH 4.115 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_755:X O *L 0 *C 97.520 3.740 +*P chany_bottom_out[14] O *L 0.7423 *C 97.520 1.290 +*N chany_bottom_out[14]:2 *C 97.520 2.040 +*N chany_bottom_out[14]:3 *C 97.060 2.040 +*N chany_bottom_out[14]:4 *C 97.060 3.695 +*N chany_bottom_out[14]:5 *C 97.105 3.740 +*N chany_bottom_out[14]:6 *C 97.483 3.740 + +*CAP +0 ropt_mt_inst_755:X 1e-06 +1 chany_bottom_out[14] 5.06605e-05 +2 chany_bottom_out[14]:2 7.782779e-05 +3 chany_bottom_out[14]:3 0.0001600663 +4 chany_bottom_out[14]:4 0.000132899 +5 chany_bottom_out[14]:5 5.962144e-05 +6 chany_bottom_out[14]:6 5.962144e-05 + +*RES +0 ropt_mt_inst_755:X chany_bottom_out[14]:6 0.152 +1 chany_bottom_out[14]:6 chany_bottom_out[14]:5 0.0003370536 +2 chany_bottom_out[14]:5 chany_bottom_out[14]:4 0.0045 +3 chany_bottom_out[14]:4 chany_bottom_out[14]:3 0.001477679 +4 chany_bottom_out[14]:3 chany_bottom_out[14]:2 0.0004107143 +5 chany_bottom_out[14]:2 chany_bottom_out[14] 0.0006696429 + +*END + +*D_NET ropt_net_131 0.002269426 //LENGTH 15.535 LUMPCC 0.0003102031 DR + +*CONN +*I ropt_mt_inst_744:X O *L 0 *C 16.280 52.700 +*I ropt_mt_inst_746:A I *L 0.001766 *C 7.820 50.320 +*N ropt_net_131:2 *C 7.783 50.320 +*N ropt_net_131:3 *C 7.405 50.320 +*N ropt_net_131:4 *C 7.360 50.275 +*N ropt_net_131:5 *C 7.360 49.698 +*N ropt_net_131:6 *C 7.360 49.640 +*N ropt_net_131:7 *C 11.033 49.640 +*N ropt_net_131:8 *C 11.040 49.698 +*N ropt_net_131:9 *C 11.040 52.315 +*N ropt_net_131:10 *C 11.085 52.360 +*N ropt_net_131:11 *C 15.180 52.360 +*N ropt_net_131:12 *C 15.180 52.700 +*N ropt_net_131:13 *C 16.242 52.700 + +*CAP +0 ropt_mt_inst_744:X 1e-06 +1 ropt_mt_inst_746:A 1e-06 +2 ropt_net_131:2 4.57669e-05 +3 ropt_net_131:3 4.57669e-05 +4 ropt_net_131:4 5.240314e-05 +5 ropt_net_131:5 5.240314e-05 +6 ropt_net_131:6 0.0002583821 +7 ropt_net_131:7 0.0002583821 +8 ropt_net_131:8 0.0001800359 +9 ropt_net_131:9 0.0001800359 +10 ropt_net_131:10 0.000318791 +11 ropt_net_131:11 0.0003442053 +12 ropt_net_131:12 0.0001232321 +13 ropt_net_131:13 9.781782e-05 +14 ropt_net_131:9 chany_bottom_in[15]:4 1.155373e-05 +15 ropt_net_131:8 chany_bottom_in[15]:5 1.155373e-05 +16 ropt_net_131:7 chany_bottom_in[15]:7 6.839067e-05 +17 ropt_net_131:6 chany_bottom_in[15]:6 6.839067e-05 +18 ropt_net_131:7 mux_tree_tapbuf_size3_1_sram[0]:17 6.665345e-05 +19 ropt_net_131:5 mux_tree_tapbuf_size3_1_sram[0]:7 6.134301e-06 +20 ropt_net_131:5 mux_tree_tapbuf_size3_1_sram[0]:12 2.369435e-06 +21 ropt_net_131:6 mux_tree_tapbuf_size3_1_sram[0]:13 6.665345e-05 +22 ropt_net_131:4 mux_tree_tapbuf_size3_1_sram[0]:6 6.134301e-06 +23 ropt_net_131:4 mux_tree_tapbuf_size3_1_sram[0]:8 2.369435e-06 + +*RES +0 ropt_mt_inst_744:X ropt_net_131:13 0.152 +1 ropt_net_131:13 ropt_net_131:12 0.0009486608 +2 ropt_net_131:10 ropt_net_131:9 0.0045 +3 ropt_net_131:9 ropt_net_131:8 0.002337054 +4 ropt_net_131:8 ropt_net_131:7 0.00341 +5 ropt_net_131:7 ropt_net_131:6 0.0005753583 +6 ropt_net_131:5 ropt_net_131:4 0.0005156251 +7 ropt_net_131:6 ropt_net_131:5 0.00341 +8 ropt_net_131:3 ropt_net_131:2 0.0003370536 +9 ropt_net_131:4 ropt_net_131:3 0.0045 +10 ropt_net_131:2 ropt_mt_inst_746:A 0.152 +11 ropt_net_131:11 ropt_net_131:10 0.00365625 +12 ropt_net_131:12 ropt_net_131:11 0.0003035715 + +*END + +*D_NET chany_bottom_in[5] 0.01388138 //LENGTH 103.585 LUMPCC 0.00485946 DR + +*CONN +*P chany_bottom_in[5] I *L 0.29796 *C 75.900 1.290 +*I BUFT_P_81:A I *L 0.001767 *C 6.900 34.000 +*N chany_bottom_in[5]:2 *C 6.938 34.000 +*N chany_bottom_in[5]:3 *C 8.235 34.000 +*N chany_bottom_in[5]:4 *C 8.280 33.955 +*N chany_bottom_in[5]:5 *C 8.280 30.658 +*N chany_bottom_in[5]:6 *C 8.287 30.600 +*N chany_bottom_in[5]:7 *C 38.620 30.600 +*N chany_bottom_in[5]:8 *C 38.640 30.593 +*N chany_bottom_in[5]:9 *C 38.640 3.408 +*N chany_bottom_in[5]:10 *C 38.660 3.400 +*N chany_bottom_in[5]:11 *C 75.892 3.400 +*N chany_bottom_in[5]:12 *C 75.900 3.343 + +*CAP +0 chany_bottom_in[5] 0.0001332995 +1 BUFT_P_81:A 1e-06 +2 chany_bottom_in[5]:2 9.12447e-05 +3 chany_bottom_in[5]:3 9.12447e-05 +4 chany_bottom_in[5]:4 0.0001646474 +5 chany_bottom_in[5]:5 0.0001646474 +6 chany_bottom_in[5]:6 0.0009602677 +7 chany_bottom_in[5]:7 0.0009602676 +8 chany_bottom_in[5]:8 0.001160139 +9 chany_bottom_in[5]:9 0.001160139 +10 chany_bottom_in[5]:10 0.00200086 +11 chany_bottom_in[5]:11 0.00200086 +12 chany_bottom_in[5]:12 0.0001332995 +13 chany_bottom_in[5]:8 chany_bottom_in[14]:8 0.0003682282 +14 chany_bottom_in[5]:10 chany_bottom_in[14]:11 0.0002895194 +15 chany_bottom_in[5]:10 chany_bottom_in[14]:13 0.0001792866 +16 chany_bottom_in[5]:9 chany_bottom_in[14]:9 0.0003682282 +17 chany_bottom_in[5]:11 chany_bottom_in[14]:14 0.0001792866 +18 chany_bottom_in[5]:11 chany_bottom_in[14]:12 0.0002895194 +19 chany_bottom_in[5]:4 prog_clk[0]:185 1.048278e-05 +20 chany_bottom_in[5]:4 prog_clk[0]:181 2.800092e-05 +21 chany_bottom_in[5]:5 prog_clk[0]:185 2.800092e-05 +22 chany_bottom_in[5]:5 prog_clk[0]:184 1.048278e-05 +23 chany_bottom_in[5]:6 prog_clk[0]:199 0.0003163583 +24 chany_bottom_in[5]:6 prog_clk[0]:200 0.0001369177 +25 chany_bottom_in[5]:6 prog_clk[0]:186 0.0002654975 +26 chany_bottom_in[5]:7 prog_clk[0]:199 0.0002654975 +27 chany_bottom_in[5]:7 prog_clk[0]:200 0.0003163583 +28 chany_bottom_in[5]:7 prog_clk[0]:172 0.0001369177 +29 chany_bottom_in[5]:6 bottom_left_grid_pin_34_[0]:16 0.0004174792 +30 chany_bottom_in[5]:7 bottom_left_grid_pin_34_[0]:17 0.0004174792 +31 chany_bottom_in[5]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.401814e-06 +32 chany_bottom_in[5]:5 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.401814e-06 +33 chany_bottom_in[5]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003093706 +34 chany_bottom_in[5]:6 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001051872 +35 chany_bottom_in[5]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001051872 +36 chany_bottom_in[5]:7 mux_left_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003093706 + +*RES +0 chany_bottom_in[5] chany_bottom_in[5]:12 0.001832589 +1 chany_bottom_in[5]:2 BUFT_P_81:A 0.152 +2 chany_bottom_in[5]:3 chany_bottom_in[5]:2 0.001158482 +3 chany_bottom_in[5]:4 chany_bottom_in[5]:3 0.0045 +4 chany_bottom_in[5]:5 chany_bottom_in[5]:4 0.002944197 +5 chany_bottom_in[5]:6 chany_bottom_in[5]:5 0.00341 +6 chany_bottom_in[5]:7 chany_bottom_in[5]:6 0.004752092 +7 chany_bottom_in[5]:8 chany_bottom_in[5]:7 0.00341 +8 chany_bottom_in[5]:10 chany_bottom_in[5]:9 0.00341 +9 chany_bottom_in[5]:9 chany_bottom_in[5]:8 0.004258983 +10 chany_bottom_in[5]:12 chany_bottom_in[5]:11 0.00341 +11 chany_bottom_in[5]:11 chany_bottom_in[5]:10 0.005833092 + +*END + +*D_NET bottom_left_grid_pin_41_[0] 0.01028581 //LENGTH 69.830 LUMPCC 0.002587625 DR + +*CONN +*P bottom_left_grid_pin_41_[0] I *L 0.29796 *C 29.825 14.280 +*I mux_bottom_track_5\/mux_l1_in_2_:A1 I *L 0.00198 *C 26.680 41.820 +*I mux_bottom_track_1\/mux_l1_in_2_:A1 I *L 0.00198 *C 21.525 45.220 +*I mux_bottom_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 26.470 49.640 +*I mux_bottom_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.815 15.300 +*N bottom_left_grid_pin_41_[0]:5 *C 38.778 15.300 +*N bottom_left_grid_pin_41_[0]:6 *C 35.925 15.300 +*N bottom_left_grid_pin_41_[0]:7 *C 35.880 15.255 +*N bottom_left_grid_pin_41_[0]:8 *C 35.880 14.338 +*N bottom_left_grid_pin_41_[0]:9 *C 35.873 14.280 +*N bottom_left_grid_pin_41_[0]:10 *C 26.433 49.640 +*N bottom_left_grid_pin_41_[0]:11 *C 23.965 49.640 +*N bottom_left_grid_pin_41_[0]:12 *C 23.920 49.595 +*N bottom_left_grid_pin_41_[0]:13 *C 26.643 41.820 +*N bottom_left_grid_pin_41_[0]:14 *C 21.665 41.820 +*N bottom_left_grid_pin_41_[0]:15 *C 21.620 41.865 +*N bottom_left_grid_pin_41_[0]:16 *C 21.620 45.175 +*N bottom_left_grid_pin_41_[0]:17 *C 21.665 45.220 +*N bottom_left_grid_pin_41_[0]:18 *C 23.875 45.220 +*N bottom_left_grid_pin_41_[0]:19 *C 23.920 45.265 +*N bottom_left_grid_pin_41_[0]:20 *C 23.920 44.880 +*N bottom_left_grid_pin_41_[0]:21 *C 23.928 44.880 +*N bottom_left_grid_pin_41_[0]:22 *C 28.053 44.880 +*N bottom_left_grid_pin_41_[0]:23 *C 28.060 44.823 +*N bottom_left_grid_pin_41_[0]:24 *C 28.060 41.820 +*N bottom_left_grid_pin_41_[0]:25 *C 28.520 41.820 +*N bottom_left_grid_pin_41_[0]:26 *C 28.520 36.098 +*N bottom_left_grid_pin_41_[0]:27 *C 28.527 36.040 +*N bottom_left_grid_pin_41_[0]:28 *C 29.420 36.040 +*N bottom_left_grid_pin_41_[0]:29 *C 29.440 36.032 +*N bottom_left_grid_pin_41_[0]:30 *C 29.440 14.960 +*N bottom_left_grid_pin_41_[0]:31 *C 30.360 14.960 +*N bottom_left_grid_pin_41_[0]:32 *C 30.360 14.288 +*N bottom_left_grid_pin_41_[0]:33 *C 30.360 14.280 + +*CAP +0 bottom_left_grid_pin_41_[0] 5.353939e-05 +1 mux_bottom_track_5\/mux_l1_in_2_:A1 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:A1 1e-06 +3 mux_bottom_track_25\/mux_l1_in_0_:A0 1e-06 +4 mux_bottom_track_9\/mux_l1_in_0_:A0 1e-06 +5 bottom_left_grid_pin_41_[0]:5 0.0001945998 +6 bottom_left_grid_pin_41_[0]:6 0.0001945998 +7 bottom_left_grid_pin_41_[0]:7 7.176289e-05 +8 bottom_left_grid_pin_41_[0]:8 7.176289e-05 +9 bottom_left_grid_pin_41_[0]:9 0.0004001589 +10 bottom_left_grid_pin_41_[0]:10 0.0001894096 +11 bottom_left_grid_pin_41_[0]:11 0.0001894096 +12 bottom_left_grid_pin_41_[0]:12 0.0002727736 +13 bottom_left_grid_pin_41_[0]:13 0.0003515026 +14 bottom_left_grid_pin_41_[0]:14 0.0003515026 +15 bottom_left_grid_pin_41_[0]:15 0.0002407426 +16 bottom_left_grid_pin_41_[0]:16 0.0002407426 +17 bottom_left_grid_pin_41_[0]:17 0.0002081128 +18 bottom_left_grid_pin_41_[0]:18 0.0002081128 +19 bottom_left_grid_pin_41_[0]:19 0.0002942545 +20 bottom_left_grid_pin_41_[0]:20 6.29779e-05 +21 bottom_left_grid_pin_41_[0]:21 0.0003284693 +22 bottom_left_grid_pin_41_[0]:22 0.0003284693 +23 bottom_left_grid_pin_41_[0]:23 0.0001939424 +24 bottom_left_grid_pin_41_[0]:24 0.0002257744 +25 bottom_left_grid_pin_41_[0]:25 0.000349821 +26 bottom_left_grid_pin_41_[0]:26 0.0003179889 +27 bottom_left_grid_pin_41_[0]:27 0.0001317878 +28 bottom_left_grid_pin_41_[0]:28 0.0001317878 +29 bottom_left_grid_pin_41_[0]:29 0.0006684179 +30 bottom_left_grid_pin_41_[0]:30 0.0007253506 +31 bottom_left_grid_pin_41_[0]:31 0.0001498219 +32 bottom_left_grid_pin_41_[0]:32 9.288926e-05 +33 bottom_left_grid_pin_41_[0]:33 0.0004536983 +34 bottom_left_grid_pin_41_[0] chanx_left_in[4]:7 5.010757e-06 +35 bottom_left_grid_pin_41_[0]:9 chanx_left_in[4]:6 4.596844e-05 +36 bottom_left_grid_pin_41_[0]:21 chanx_left_in[4]:11 0.0002470788 +37 bottom_left_grid_pin_41_[0]:22 chanx_left_in[4]:10 0.0002470788 +38 bottom_left_grid_pin_41_[0]:29 chanx_left_in[4]:9 0.0009450339 +39 bottom_left_grid_pin_41_[0]:33 chanx_left_in[4]:6 5.010757e-06 +40 bottom_left_grid_pin_41_[0]:33 chanx_left_in[4]:7 4.596844e-05 +41 bottom_left_grid_pin_41_[0]:30 chanx_left_in[4]:8 0.0009450339 +42 bottom_left_grid_pin_41_[0]:26 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.072064e-05 +43 bottom_left_grid_pin_41_[0]:25 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.072064e-05 + +*RES +0 bottom_left_grid_pin_41_[0] bottom_left_grid_pin_41_[0]:33 8.381667e-05 +1 bottom_left_grid_pin_41_[0]:10 mux_bottom_track_25\/mux_l1_in_0_:A0 0.152 +2 bottom_left_grid_pin_41_[0]:11 bottom_left_grid_pin_41_[0]:10 0.002203125 +3 bottom_left_grid_pin_41_[0]:12 bottom_left_grid_pin_41_[0]:11 0.0045 +4 bottom_left_grid_pin_41_[0]:18 bottom_left_grid_pin_41_[0]:17 0.001973214 +5 bottom_left_grid_pin_41_[0]:19 bottom_left_grid_pin_41_[0]:18 0.0045 +6 bottom_left_grid_pin_41_[0]:19 bottom_left_grid_pin_41_[0]:12 0.003866072 +7 bottom_left_grid_pin_41_[0]:8 bottom_left_grid_pin_41_[0]:7 0.0008191965 +8 bottom_left_grid_pin_41_[0]:9 bottom_left_grid_pin_41_[0]:8 0.00341 +9 bottom_left_grid_pin_41_[0]:6 bottom_left_grid_pin_41_[0]:5 0.002546875 +10 bottom_left_grid_pin_41_[0]:7 bottom_left_grid_pin_41_[0]:6 0.0045 +11 bottom_left_grid_pin_41_[0]:5 mux_bottom_track_9\/mux_l1_in_0_:A0 0.152 +12 bottom_left_grid_pin_41_[0]:20 bottom_left_grid_pin_41_[0]:19 0.0001850962 +13 bottom_left_grid_pin_41_[0]:21 bottom_left_grid_pin_41_[0]:20 0.00341 +14 bottom_left_grid_pin_41_[0]:23 bottom_left_grid_pin_41_[0]:22 0.00341 +15 bottom_left_grid_pin_41_[0]:22 bottom_left_grid_pin_41_[0]:21 0.00064625 +16 bottom_left_grid_pin_41_[0]:26 bottom_left_grid_pin_41_[0]:25 0.005109375 +17 bottom_left_grid_pin_41_[0]:27 bottom_left_grid_pin_41_[0]:26 0.00341 +18 bottom_left_grid_pin_41_[0]:28 bottom_left_grid_pin_41_[0]:27 0.000139825 +19 bottom_left_grid_pin_41_[0]:29 bottom_left_grid_pin_41_[0]:28 0.00341 +20 bottom_left_grid_pin_41_[0]:33 bottom_left_grid_pin_41_[0]:32 0.00341 +21 bottom_left_grid_pin_41_[0]:33 bottom_left_grid_pin_41_[0]:9 0.0008636249 +22 bottom_left_grid_pin_41_[0]:32 bottom_left_grid_pin_41_[0]:31 0.0001053583 +23 bottom_left_grid_pin_41_[0]:17 bottom_left_grid_pin_41_[0]:16 0.0045 +24 bottom_left_grid_pin_41_[0]:17 mux_bottom_track_1\/mux_l1_in_2_:A1 0.152 +25 bottom_left_grid_pin_41_[0]:16 bottom_left_grid_pin_41_[0]:15 0.002955357 +26 bottom_left_grid_pin_41_[0]:14 bottom_left_grid_pin_41_[0]:13 0.004444197 +27 bottom_left_grid_pin_41_[0]:15 bottom_left_grid_pin_41_[0]:14 0.0045 +28 bottom_left_grid_pin_41_[0]:13 mux_bottom_track_5\/mux_l1_in_2_:A1 0.152 +29 bottom_left_grid_pin_41_[0]:24 bottom_left_grid_pin_41_[0]:23 0.002680803 +30 bottom_left_grid_pin_41_[0]:25 bottom_left_grid_pin_41_[0]:24 0.0004107143 +31 bottom_left_grid_pin_41_[0]:30 bottom_left_grid_pin_41_[0]:29 0.003301358 +32 bottom_left_grid_pin_41_[0]:31 bottom_left_grid_pin_41_[0]:30 0.0001441333 + +*END + +*D_NET chanx_left_in[5] 0.01163227 //LENGTH 69.585 LUMPCC 0.005343532 DR + +*CONN +*P chanx_left_in[5] I *L 0.29796 *C 1.230 46.240 +*I mux_bottom_track_9\/mux_l1_in_1_:A1 I *L 0.00198 *C 41.500 18.020 +*N chanx_left_in[5]:2 *C 41.462 18.020 +*N chanx_left_in[5]:3 *C 40.985 18.020 +*N chanx_left_in[5]:4 *C 40.940 18.065 +*N chanx_left_in[5]:5 *C 40.940 39.440 +*N chanx_left_in[5]:6 *C 40.480 39.440 +*N chanx_left_in[5]:7 *C 40.480 46.183 +*N chanx_left_in[5]:8 *C 40.473 46.240 + +*CAP +0 chanx_left_in[5] 0.001434974 +1 mux_bottom_track_9\/mux_l1_in_1_:A1 1e-06 +2 chanx_left_in[5]:2 5.837558e-05 +3 chanx_left_in[5]:3 5.837558e-05 +4 chanx_left_in[5]:4 0.001233083 +5 chanx_left_in[5]:5 0.001263558 +6 chanx_left_in[5]:6 0.0004174332 +7 chanx_left_in[5]:7 0.0003869581 +8 chanx_left_in[5]:8 0.001434974 +9 chanx_left_in[5] chanx_left_in[4] 6.670006e-07 +10 chanx_left_in[5] chanx_left_in[4]:11 0.001428168 +11 chanx_left_in[5]:8 chanx_left_in[4]:10 0.001428168 +12 chanx_left_in[5]:8 chanx_left_in[4]:14 6.670006e-07 +13 chanx_left_in[5] mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001067668 +14 chanx_left_in[5]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001067668 +15 chanx_left_in[5] mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.000175263 +16 chanx_left_in[5]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000175263 + +*RES +0 chanx_left_in[5] chanx_left_in[5]:8 0.006147991 +1 chanx_left_in[5]:2 mux_bottom_track_9\/mux_l1_in_1_:A1 0.152 +2 chanx_left_in[5]:3 chanx_left_in[5]:2 0.0004263393 +3 chanx_left_in[5]:4 chanx_left_in[5]:3 0.0045 +4 chanx_left_in[5]:7 chanx_left_in[5]:6 0.00602009 +5 chanx_left_in[5]:8 chanx_left_in[5]:7 0.00341 +6 chanx_left_in[5]:6 chanx_left_in[5]:5 0.0004107143 +7 chanx_left_in[5]:5 chanx_left_in[5]:4 0.01908482 + +*END + +*D_NET chanx_left_in[9] 0.008831967 //LENGTH 83.875 LUMPCC 0.001154736 DR + +*CONN +*P chanx_left_in[9] I *L 0.29796 *C 1.230 99.280 +*I mux_bottom_track_17\/mux_l1_in_0_:A0 I *L 0.001631 *C 39.380 55.080 +*N chanx_left_in[9]:2 *C 39.343 55.080 +*N chanx_left_in[9]:3 *C 38.225 55.080 +*N chanx_left_in[9]:4 *C 38.180 55.125 +*N chanx_left_in[9]:5 *C 38.180 59.103 +*N chanx_left_in[9]:6 *C 38.172 59.160 +*N chanx_left_in[9]:7 *C 35.900 59.160 +*N chanx_left_in[9]:8 *C 35.880 59.168 +*N chanx_left_in[9]:9 *C 35.880 99.273 +*N chanx_left_in[9]:10 *C 35.860 99.280 + +*CAP +0 chanx_left_in[9] 0.001365317 +1 mux_bottom_track_17\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[9]:2 9.744275e-05 +3 chanx_left_in[9]:3 9.744275e-05 +4 chanx_left_in[9]:4 0.0002471271 +5 chanx_left_in[9]:5 0.0002471271 +6 chanx_left_in[9]:6 0.0002002892 +7 chanx_left_in[9]:7 0.0002002892 +8 chanx_left_in[9]:8 0.001927939 +9 chanx_left_in[9]:9 0.001927939 +10 chanx_left_in[9]:10 0.001365317 +11 chanx_left_in[9] chanx_left_out[10] 9.733783e-06 +12 chanx_left_in[9] chanx_left_out[10]:3 0.0005676344 +13 chanx_left_in[9]:10 chanx_left_out[10]:4 0.0005676344 +14 chanx_left_in[9]:10 chanx_left_out[10]:2 9.733783e-06 + +*RES +0 chanx_left_in[9] chanx_left_in[9]:10 0.005425367 +1 chanx_left_in[9]:2 mux_bottom_track_17\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[9]:3 chanx_left_in[9]:2 0.0009977679 +3 chanx_left_in[9]:4 chanx_left_in[9]:3 0.0045 +4 chanx_left_in[9]:5 chanx_left_in[9]:4 0.00355134 +5 chanx_left_in[9]:6 chanx_left_in[9]:5 0.00341 +6 chanx_left_in[9]:7 chanx_left_in[9]:6 0.0003560249 +7 chanx_left_in[9]:8 chanx_left_in[9]:7 0.00341 +8 chanx_left_in[9]:10 chanx_left_in[9]:9 0.00341 +9 chanx_left_in[9]:9 chanx_left_in[9]:8 0.006283116 + +*END + +*D_NET chanx_left_in[15] 0.005754117 //LENGTH 57.890 LUMPCC 0 DR + +*CONN +*P chanx_left_in[15] I *L 0.29796 *C 1.230 96.560 +*I mux_bottom_track_29\/mux_l1_in_0_:A0 I *L 0.001631 *C 28.350 66.300 +*N chanx_left_in[15]:2 *C 28.350 66.300 +*N chanx_left_in[15]:3 *C 28.060 66.300 +*N chanx_left_in[15]:4 *C 28.060 66.345 +*N chanx_left_in[15]:5 *C 28.060 96.502 +*N chanx_left_in[15]:6 *C 28.053 96.560 + +*CAP +0 chanx_left_in[15] 0.001379334 +1 mux_bottom_track_29\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[15]:2 4.668879e-05 +3 chanx_left_in[15]:3 5.026584e-05 +4 chanx_left_in[15]:4 0.001448747 +5 chanx_left_in[15]:5 0.001448747 +6 chanx_left_in[15]:6 0.001379334 + +*RES +0 chanx_left_in[15] chanx_left_in[15]:6 0.004202191 +1 chanx_left_in[15]:2 mux_bottom_track_29\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[15]:3 chanx_left_in[15]:2 0.0001576087 +3 chanx_left_in[15]:4 chanx_left_in[15]:3 0.0045 +4 chanx_left_in[15]:5 chanx_left_in[15]:4 0.02692634 +5 chanx_left_in[15]:6 chanx_left_in[15]:5 0.00341 + +*END + +*D_NET chanx_left_in[16] 0.004851252 //LENGTH 29.040 LUMPCC 0.002350212 DR + +*CONN +*P chanx_left_in[16] I *L 0.29796 *C 1.230 55.760 +*I mux_bottom_track_31\/mux_l1_in_0_:A0 I *L 0.001631 *C 22.255 49.980 +*N chanx_left_in[16]:2 *C 22.218 49.980 +*N chanx_left_in[16]:3 *C 18.905 49.980 +*N chanx_left_in[16]:4 *C 18.860 50.025 +*N chanx_left_in[16]:5 *C 18.860 50.943 +*N chanx_left_in[16]:6 *C 18.852 51.000 +*N chanx_left_in[16]:7 *C 11.060 51.000 +*N chanx_left_in[16]:8 *C 11.040 51.008 +*N chanx_left_in[16]:9 *C 11.040 52.352 +*N chanx_left_in[16]:10 *C 11.020 52.360 +*N chanx_left_in[16]:11 *C 2.780 52.360 +*N chanx_left_in[16]:12 *C 2.760 52.367 +*N chanx_left_in[16]:13 *C 2.760 55.753 +*N chanx_left_in[16]:14 *C 2.740 55.760 + +*CAP +0 chanx_left_in[16] 0.0001285903 +1 mux_bottom_track_31\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[16]:2 0.0001713743 +3 chanx_left_in[16]:3 0.0001713743 +4 chanx_left_in[16]:4 7.085447e-05 +5 chanx_left_in[16]:5 7.085447e-05 +6 chanx_left_in[16]:6 0.0001962655 +7 chanx_left_in[16]:7 0.0001962655 +8 chanx_left_in[16]:8 0.000113085 +9 chanx_left_in[16]:9 0.000113085 +10 chanx_left_in[16]:10 0.0003556997 +11 chanx_left_in[16]:11 0.0003556997 +12 chanx_left_in[16]:12 0.0002141508 +13 chanx_left_in[16]:13 0.0002141508 +14 chanx_left_in[16]:14 0.0001285903 +15 chanx_left_in[16]:6 chany_bottom_in[15]:7 0.0004552651 +16 chanx_left_in[16]:7 chany_bottom_in[15]:6 0.0004552651 +17 chanx_left_in[16]:10 chany_bottom_in[15]:7 5.597575e-06 +18 chanx_left_in[16]:11 chany_bottom_in[15]:6 5.597575e-06 +19 chanx_left_in[16]:6 chanx_left_in[17]:6 0.0001011207 +20 chanx_left_in[16]:7 chanx_left_in[17] 0.0001011207 +21 chanx_left_in[16]:10 chanx_left_in[17]:6 0.0004741175 +22 chanx_left_in[16]:11 chanx_left_in[17] 0.0004741175 +23 chanx_left_in[16]:2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.000139005 +24 chanx_left_in[16]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.000139005 + +*RES +0 chanx_left_in[16] chanx_left_in[16]:14 0.0002365667 +1 chanx_left_in[16]:2 mux_bottom_track_31\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[16]:3 chanx_left_in[16]:2 0.002957589 +3 chanx_left_in[16]:4 chanx_left_in[16]:3 0.0045 +4 chanx_left_in[16]:5 chanx_left_in[16]:4 0.0008191965 +5 chanx_left_in[16]:6 chanx_left_in[16]:5 0.00341 +6 chanx_left_in[16]:7 chanx_left_in[16]:6 0.001220825 +7 chanx_left_in[16]:8 chanx_left_in[16]:7 0.00341 +8 chanx_left_in[16]:10 chanx_left_in[16]:9 0.00341 +9 chanx_left_in[16]:9 chanx_left_in[16]:8 0.0002107167 +10 chanx_left_in[16]:11 chanx_left_in[16]:10 0.001290933 +11 chanx_left_in[16]:12 chanx_left_in[16]:11 0.00341 +12 chanx_left_in[16]:14 chanx_left_in[16]:13 0.00341 +13 chanx_left_in[16]:13 chanx_left_in[16]:12 0.0005303166 + +*END + +*D_NET chany_bottom_out[1] 0.001751435 //LENGTH 13.420 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 53.820 6.800 +*P chany_bottom_out[1] O *L 0.7423 *C 59.800 1.325 +*N chany_bottom_out[1]:2 *C 59.800 7.435 +*N chany_bottom_out[1]:3 *C 59.755 7.480 +*N chany_bottom_out[1]:4 *C 53.820 7.480 +*N chany_bottom_out[1]:5 *C 53.820 6.838 + +*CAP +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[1] 0.0003852794 +2 chany_bottom_out[1]:2 0.0003852794 +3 chany_bottom_out[1]:3 0.0004414272 +4 chany_bottom_out[1]:4 0.0004899381 +5 chany_bottom_out[1]:5 4.851097e-05 + +*RES +0 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[1]:5 0.152 +1 chany_bottom_out[1]:3 chany_bottom_out[1]:2 0.0045 +2 chany_bottom_out[1]:2 chany_bottom_out[1] 0.005455357 +3 chany_bottom_out[1]:5 chany_bottom_out[1]:4 0.0005736608 +4 chany_bottom_out[1]:4 chany_bottom_out[1]:3 0.005299107 + +*END + +*D_NET chany_bottom_out[3] 0.001194143 //LENGTH 9.390 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 65.320 6.460 +*P chany_bottom_out[3] O *L 0.7423 *C 69.000 1.325 +*N chany_bottom_out[3]:2 *C 69.000 6.075 +*N chany_bottom_out[3]:3 *C 68.955 6.120 +*N chany_bottom_out[3]:4 *C 65.320 6.120 +*N chany_bottom_out[3]:5 *C 65.320 6.460 + +*CAP +0 mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[3] 0.000275392 +2 chany_bottom_out[3]:2 0.000275392 +3 chany_bottom_out[3]:3 0.0002776909 +4 chany_bottom_out[3]:4 0.0003063029 +5 chany_bottom_out[3]:5 5.836543e-05 + +*RES +0 mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[3]:5 0.152 +1 chany_bottom_out[3]:3 chany_bottom_out[3]:2 0.0045 +2 chany_bottom_out[3]:2 chany_bottom_out[3] 0.004241071 +3 chany_bottom_out[3]:5 chany_bottom_out[3]:4 0.0003035715 +4 chany_bottom_out[3]:4 chany_bottom_out[3]:3 0.003245536 + +*END + +*D_NET chany_bottom_out[9] 0.0008002616 //LENGTH 5.955 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 51.580 4.080 +*P chany_bottom_out[9] O *L 0.7423 *C 54.280 1.290 +*N chany_bottom_out[9]:2 *C 54.280 4.035 +*N chany_bottom_out[9]:3 *C 54.235 4.080 +*N chany_bottom_out[9]:4 *C 51.617 4.080 + +*CAP +0 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[9] 0.0001761901 +2 chany_bottom_out[9]:2 0.0001761901 +3 chany_bottom_out[9]:3 0.0002234407 +4 chany_bottom_out[9]:4 0.0002234407 + +*RES +0 mux_bottom_track_19\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[9]:4 0.152 +1 chany_bottom_out[9]:4 chany_bottom_out[9]:3 0.002337054 +2 chany_bottom_out[9]:3 chany_bottom_out[9]:2 0.0045 +3 chany_bottom_out[9]:2 chany_bottom_out[9] 0.002450893 + +*END + +*D_NET ropt_net_111 0.001567837 //LENGTH 13.515 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_29\/BUFT_P_84:X O *L 0 *C 94.075 8.840 +*I ropt_mt_inst_726:A I *L 0.001766 *C 101.200 4.080 +*N ropt_net_111:2 *C 101.163 4.080 +*N ropt_net_111:3 *C 99.865 4.080 +*N ropt_net_111:4 *C 99.820 4.080 +*N ropt_net_111:5 *C 99.812 4.080 +*N ropt_net_111:6 *C 97.528 4.080 +*N ropt_net_111:7 *C 97.520 4.080 +*N ropt_net_111:8 *C 97.520 8.795 +*N ropt_net_111:9 *C 97.475 8.840 +*N ropt_net_111:10 *C 94.075 8.840 + +*CAP +0 mux_bottom_track_29\/BUFT_P_84:X 1e-06 +1 ropt_mt_inst_726:A 1e-06 +2 ropt_net_111:2 9.204364e-05 +3 ropt_net_111:3 9.204364e-05 +4 ropt_net_111:4 3.302292e-05 +5 ropt_net_111:5 0.0001427033 +6 ropt_net_111:6 0.0001427033 +7 ropt_net_111:7 0.0002958129 +8 ropt_net_111:8 0.0002645635 +9 ropt_net_111:9 0.0002376802 +10 ropt_net_111:10 0.0002652637 + +*RES +0 mux_bottom_track_29\/BUFT_P_84:X ropt_net_111:10 0.152 +1 ropt_net_111:10 ropt_net_111:9 0.003035714 +2 ropt_net_111:9 ropt_net_111:8 0.0045 +3 ropt_net_111:8 ropt_net_111:7 0.004209822 +4 ropt_net_111:7 ropt_net_111:6 0.00341 +5 ropt_net_111:6 ropt_net_111:5 0.0003579833 +6 ropt_net_111:4 ropt_net_111:3 0.0045 +7 ropt_net_111:5 ropt_net_111:4 0.00341 +8 ropt_net_111:3 ropt_net_111:2 0.001158482 +9 ropt_net_111:2 ropt_mt_inst_726:A 0.152 + +*END + +*D_NET chany_bottom_out[18] 0.0007739316 //LENGTH 6.600 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 74.980 4.420 +*P chany_bottom_out[18] O *L 0.7423 *C 73.140 1.325 +*N chany_bottom_out[18]:2 *C 73.140 3.060 +*N chany_bottom_out[18]:3 *C 72.680 3.060 +*N chany_bottom_out[18]:4 *C 72.680 4.375 +*N chany_bottom_out[18]:5 *C 72.725 4.420 +*N chany_bottom_out[18]:6 *C 74.943 4.420 + +*CAP +0 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[18] 0.0001121653 +2 chany_bottom_out[18]:2 0.0001422238 +3 chany_bottom_out[18]:3 0.000123773 +4 chany_bottom_out[18]:4 9.371456e-05 +5 chany_bottom_out[18]:5 0.0001505275 +6 chany_bottom_out[18]:6 0.0001505275 + +*RES +0 mux_bottom_track_37\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[18]:6 0.152 +1 chany_bottom_out[18]:5 chany_bottom_out[18]:4 0.0045 +2 chany_bottom_out[18]:4 chany_bottom_out[18]:3 0.001174107 +3 chany_bottom_out[18]:6 chany_bottom_out[18]:5 0.001979911 +4 chany_bottom_out[18]:3 chany_bottom_out[18]:2 0.0004107143 +5 chany_bottom_out[18]:2 chany_bottom_out[18] 0.001549107 + +*END + +*D_NET ropt_net_112 0.0008466667 //LENGTH 7.030 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/BUFT_RR_97:X O *L 0 *C 7.585 78.200 +*I ropt_mt_inst_727:A I *L 0.001767 *C 3.220 80.240 +*N ropt_net_112:2 *C 3.220 80.240 +*N ropt_net_112:3 *C 3.220 80.195 +*N ropt_net_112:4 *C 3.220 78.245 +*N ropt_net_112:5 *C 3.265 78.200 +*N ropt_net_112:6 *C 7.548 78.200 + +*CAP +0 mem_left_track_25\/BUFT_RR_97:X 1e-06 +1 ropt_mt_inst_727:A 1e-06 +2 ropt_net_112:2 3.026261e-05 +3 ropt_net_112:3 0.000120796 +4 ropt_net_112:4 0.000120796 +5 ropt_net_112:5 0.0002864061 +6 ropt_net_112:6 0.0002864061 + +*RES +0 mem_left_track_25\/BUFT_RR_97:X ropt_net_112:6 0.152 +1 ropt_net_112:6 ropt_net_112:5 0.003823661 +2 ropt_net_112:5 ropt_net_112:4 0.0045 +3 ropt_net_112:4 ropt_net_112:3 0.001741072 +4 ropt_net_112:2 ropt_mt_inst_727:A 0.152 +5 ropt_net_112:3 ropt_net_112:2 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[0] 0.002238618 //LENGTH 17.325 LUMPCC 0.0006454196 DR + +*CONN +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 46.765 39.100 +*I mux_bottom_track_35\/mux_l1_in_0_:S I *L 0.00357 *C 36.240 36.720 +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 47.095 33.660 +*N mux_tree_tapbuf_size2_11_sram[0]:3 *C 47.095 33.660 +*N mux_tree_tapbuf_size2_11_sram[0]:4 *C 46.920 33.660 +*N mux_tree_tapbuf_size2_11_sram[0]:5 *C 46.920 33.705 +*N mux_tree_tapbuf_size2_11_sram[0]:6 *C 36.278 36.720 +*N mux_tree_tapbuf_size2_11_sram[0]:7 *C 46.875 36.720 +*N mux_tree_tapbuf_size2_11_sram[0]:8 *C 46.920 36.720 +*N mux_tree_tapbuf_size2_11_sram[0]:9 *C 46.920 39.055 +*N mux_tree_tapbuf_size2_11_sram[0]:10 *C 46.920 39.100 +*N mux_tree_tapbuf_size2_11_sram[0]:11 *C 46.765 39.100 + +*CAP +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_35\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_11_sram[0]:3 5.21184e-05 +4 mux_tree_tapbuf_size2_11_sram[0]:4 5.682434e-05 +5 mux_tree_tapbuf_size2_11_sram[0]:5 0.0001251996 +6 mux_tree_tapbuf_size2_11_sram[0]:6 0.0004609832 +7 mux_tree_tapbuf_size2_11_sram[0]:7 0.0004609832 +8 mux_tree_tapbuf_size2_11_sram[0]:8 0.0002458028 +9 mux_tree_tapbuf_size2_11_sram[0]:9 9.147989e-05 +10 mux_tree_tapbuf_size2_11_sram[0]:10 5.065236e-05 +11 mux_tree_tapbuf_size2_11_sram[0]:11 4.61542e-05 +12 mux_tree_tapbuf_size2_11_sram[0]:5 optlc_net_108:18 8.288732e-05 +13 mux_tree_tapbuf_size2_11_sram[0]:8 optlc_net_108:18 6.856012e-05 +14 mux_tree_tapbuf_size2_11_sram[0]:8 optlc_net_108:19 8.288732e-05 +15 mux_tree_tapbuf_size2_11_sram[0]:9 optlc_net_108:19 6.856012e-05 +16 mux_tree_tapbuf_size2_11_sram[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001712623 +17 mux_tree_tapbuf_size2_11_sram[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001712623 + +*RES +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_11_sram[0]:11 0.152 +1 mux_tree_tapbuf_size2_11_sram[0]:4 mux_tree_tapbuf_size2_11_sram[0]:3 9.510871e-05 +2 mux_tree_tapbuf_size2_11_sram[0]:5 mux_tree_tapbuf_size2_11_sram[0]:4 0.0045 +3 mux_tree_tapbuf_size2_11_sram[0]:3 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size2_11_sram[0]:7 mux_tree_tapbuf_size2_11_sram[0]:6 0.009462054 +5 mux_tree_tapbuf_size2_11_sram[0]:8 mux_tree_tapbuf_size2_11_sram[0]:7 0.0045 +6 mux_tree_tapbuf_size2_11_sram[0]:8 mux_tree_tapbuf_size2_11_sram[0]:5 0.002691964 +7 mux_tree_tapbuf_size2_11_sram[0]:6 mux_bottom_track_35\/mux_l1_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_11_sram[0]:10 mux_tree_tapbuf_size2_11_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size2_11_sram[0]:9 mux_tree_tapbuf_size2_11_sram[0]:8 0.002084821 +10 mux_tree_tapbuf_size2_11_sram[0]:11 mux_tree_tapbuf_size2_11_sram[0]:10 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_13_sram[0] 0.002621513 //LENGTH 20.085 LUMPCC 0.000493861 DR + +*CONN +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 71.145 25.840 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 76.995 31.620 +*I mux_bottom_track_39\/mux_l1_in_0_:S I *L 0.00357 *C 83.160 25.840 +*N mux_tree_tapbuf_size2_13_sram[0]:3 *C 83.123 25.840 +*N mux_tree_tapbuf_size2_13_sram[0]:4 *C 76.995 31.620 +*N mux_tree_tapbuf_size2_13_sram[0]:5 *C 77.280 31.620 +*N mux_tree_tapbuf_size2_13_sram[0]:6 *C 77.280 31.575 +*N mux_tree_tapbuf_size2_13_sram[0]:7 *C 77.280 25.885 +*N mux_tree_tapbuf_size2_13_sram[0]:8 *C 77.280 25.840 +*N mux_tree_tapbuf_size2_13_sram[0]:9 *C 77.280 25.500 +*N mux_tree_tapbuf_size2_13_sram[0]:10 *C 72.220 25.500 +*N mux_tree_tapbuf_size2_13_sram[0]:11 *C 72.220 25.840 +*N mux_tree_tapbuf_size2_13_sram[0]:12 *C 71.183 25.840 + +*CAP +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_39\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_13_sram[0]:3 0.0002628439 +4 mux_tree_tapbuf_size2_13_sram[0]:4 4.680798e-05 +5 mux_tree_tapbuf_size2_13_sram[0]:5 5.214562e-05 +6 mux_tree_tapbuf_size2_13_sram[0]:6 0.0003172868 +7 mux_tree_tapbuf_size2_13_sram[0]:7 0.0003172868 +8 mux_tree_tapbuf_size2_13_sram[0]:8 0.0002864797 +9 mux_tree_tapbuf_size2_13_sram[0]:9 0.0003155826 +10 mux_tree_tapbuf_size2_13_sram[0]:10 0.0003204353 +11 mux_tree_tapbuf_size2_13_sram[0]:11 0.0001171357 +12 mux_tree_tapbuf_size2_13_sram[0]:12 8.864723e-05 +13 mux_tree_tapbuf_size2_13_sram[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0002319119 +14 mux_tree_tapbuf_size2_13_sram[0]:8 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0002319119 +15 mux_tree_tapbuf_size2_13_sram[0]:7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 4.163464e-06 +16 mux_tree_tapbuf_size2_13_sram[0]:6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 4.163464e-06 +17 mux_tree_tapbuf_size2_13_sram[0]:10 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.085518e-05 +18 mux_tree_tapbuf_size2_13_sram[0]:9 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.085518e-05 + +*RES +0 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_13_sram[0]:12 0.152 +1 mux_tree_tapbuf_size2_13_sram[0]:12 mux_tree_tapbuf_size2_13_sram[0]:11 0.0009263394 +2 mux_tree_tapbuf_size2_13_sram[0]:3 mux_bottom_track_39\/mux_l1_in_0_:S 0.152 +3 mux_tree_tapbuf_size2_13_sram[0]:8 mux_tree_tapbuf_size2_13_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size2_13_sram[0]:8 mux_tree_tapbuf_size2_13_sram[0]:3 0.005216518 +5 mux_tree_tapbuf_size2_13_sram[0]:7 mux_tree_tapbuf_size2_13_sram[0]:6 0.005080357 +6 mux_tree_tapbuf_size2_13_sram[0]:5 mux_tree_tapbuf_size2_13_sram[0]:4 0.0001548913 +7 mux_tree_tapbuf_size2_13_sram[0]:6 mux_tree_tapbuf_size2_13_sram[0]:5 0.0045 +8 mux_tree_tapbuf_size2_13_sram[0]:4 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +9 mux_tree_tapbuf_size2_13_sram[0]:11 mux_tree_tapbuf_size2_13_sram[0]:10 0.0003035715 +10 mux_tree_tapbuf_size2_13_sram[0]:10 mux_tree_tapbuf_size2_13_sram[0]:9 0.004517857 +11 mux_tree_tapbuf_size2_13_sram[0]:9 mux_tree_tapbuf_size2_13_sram[0]:8 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_17_sram[1] 0.001955989 //LENGTH 17.955 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 26.525 74.800 +*I mux_left_track_25\/mux_l2_in_0_:S I *L 0.00357 *C 16.200 79.560 +*I mem_left_track_25\/FTB_24__39:A I *L 0.001746 *C 14.260 77.520 +*N mux_tree_tapbuf_size2_17_sram[1]:3 *C 14.298 77.520 +*N mux_tree_tapbuf_size2_17_sram[1]:4 *C 16.100 79.560 +*N mux_tree_tapbuf_size2_17_sram[1]:5 *C 16.100 79.515 +*N mux_tree_tapbuf_size2_17_sram[1]:6 *C 16.100 77.565 +*N mux_tree_tapbuf_size2_17_sram[1]:7 *C 16.100 77.520 +*N mux_tree_tapbuf_size2_17_sram[1]:8 *C 26.175 77.520 +*N mux_tree_tapbuf_size2_17_sram[1]:9 *C 26.220 77.475 +*N mux_tree_tapbuf_size2_17_sram[1]:10 *C 26.220 74.845 +*N mux_tree_tapbuf_size2_17_sram[1]:11 *C 26.220 74.800 +*N mux_tree_tapbuf_size2_17_sram[1]:12 *C 26.525 74.800 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_25\/FTB_24__39:A 1e-06 +3 mux_tree_tapbuf_size2_17_sram[1]:3 0.0001036511 +4 mux_tree_tapbuf_size2_17_sram[1]:4 3.012959e-05 +5 mux_tree_tapbuf_size2_17_sram[1]:5 0.000116809 +6 mux_tree_tapbuf_size2_17_sram[1]:6 0.000116809 +7 mux_tree_tapbuf_size2_17_sram[1]:7 0.0006515755 +8 mux_tree_tapbuf_size2_17_sram[1]:8 0.0005177947 +9 mux_tree_tapbuf_size2_17_sram[1]:9 0.0001499412 +10 mux_tree_tapbuf_size2_17_sram[1]:10 0.0001499412 +11 mux_tree_tapbuf_size2_17_sram[1]:11 6.015485e-05 +12 mux_tree_tapbuf_size2_17_sram[1]:12 5.618301e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_17_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_17_sram[1]:8 mux_tree_tapbuf_size2_17_sram[1]:7 0.008995536 +2 mux_tree_tapbuf_size2_17_sram[1]:9 mux_tree_tapbuf_size2_17_sram[1]:8 0.0045 +3 mux_tree_tapbuf_size2_17_sram[1]:11 mux_tree_tapbuf_size2_17_sram[1]:10 0.0045 +4 mux_tree_tapbuf_size2_17_sram[1]:10 mux_tree_tapbuf_size2_17_sram[1]:9 0.002348214 +5 mux_tree_tapbuf_size2_17_sram[1]:12 mux_tree_tapbuf_size2_17_sram[1]:11 0.0001657609 +6 mux_tree_tapbuf_size2_17_sram[1]:3 mem_left_track_25\/FTB_24__39:A 0.152 +7 mux_tree_tapbuf_size2_17_sram[1]:7 mux_tree_tapbuf_size2_17_sram[1]:6 0.0045 +8 mux_tree_tapbuf_size2_17_sram[1]:7 mux_tree_tapbuf_size2_17_sram[1]:3 0.001609375 +9 mux_tree_tapbuf_size2_17_sram[1]:6 mux_tree_tapbuf_size2_17_sram[1]:5 0.001741072 +10 mux_tree_tapbuf_size2_17_sram[1]:4 mux_left_track_25\/mux_l2_in_0_:S 0.152 +11 mux_tree_tapbuf_size2_17_sram[1]:5 mux_tree_tapbuf_size2_17_sram[1]:4 0.0045 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[0] 0.002991268 //LENGTH 25.515 LUMPCC 0.0001014255 DR + +*CONN +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 44.465 75.140 +*I mux_bottom_track_15\/mux_l1_in_0_:S I *L 0.00357 *C 33.940 61.880 +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 42.955 64.260 +*N mux_tree_tapbuf_size2_2_sram[0]:3 *C 42.830 64.260 +*N mux_tree_tapbuf_size2_2_sram[0]:4 *C 33.977 61.880 +*N mux_tree_tapbuf_size2_2_sram[0]:5 *C 35.375 61.880 +*N mux_tree_tapbuf_size2_2_sram[0]:6 *C 35.420 61.925 +*N mux_tree_tapbuf_size2_2_sram[0]:7 *C 35.420 64.215 +*N mux_tree_tapbuf_size2_2_sram[0]:8 *C 35.465 64.260 +*N mux_tree_tapbuf_size2_2_sram[0]:9 *C 42.735 64.260 +*N mux_tree_tapbuf_size2_2_sram[0]:10 *C 42.780 64.305 +*N mux_tree_tapbuf_size2_2_sram[0]:11 *C 42.780 75.095 +*N mux_tree_tapbuf_size2_2_sram[0]:12 *C 42.825 75.140 +*N mux_tree_tapbuf_size2_2_sram[0]:13 *C 44.428 75.140 + +*CAP +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_15\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_2_sram[0]:3 2.435654e-05 +4 mux_tree_tapbuf_size2_2_sram[0]:4 0.0001446642 +5 mux_tree_tapbuf_size2_2_sram[0]:5 0.0001446642 +6 mux_tree_tapbuf_size2_2_sram[0]:6 0.0001423499 +7 mux_tree_tapbuf_size2_2_sram[0]:7 0.0001423499 +8 mux_tree_tapbuf_size2_2_sram[0]:8 0.0004603825 +9 mux_tree_tapbuf_size2_2_sram[0]:9 0.000484739 +10 mux_tree_tapbuf_size2_2_sram[0]:10 0.0005615025 +11 mux_tree_tapbuf_size2_2_sram[0]:11 0.0005615025 +12 mux_tree_tapbuf_size2_2_sram[0]:12 0.0001101654 +13 mux_tree_tapbuf_size2_2_sram[0]:13 0.0001101654 +14 mux_tree_tapbuf_size2_2_sram[0]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.205983e-05 +15 mux_tree_tapbuf_size2_2_sram[0]:8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.86529e-05 +16 mux_tree_tapbuf_size2_2_sram[0]:7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 1.205983e-05 +17 mux_tree_tapbuf_size2_2_sram[0]:9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.86529e-05 + +*RES +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_2_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_2_sram[0]:4 mux_bottom_track_15\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_2_sram[0]:5 mux_tree_tapbuf_size2_2_sram[0]:4 0.001247768 +3 mux_tree_tapbuf_size2_2_sram[0]:6 mux_tree_tapbuf_size2_2_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size2_2_sram[0]:8 mux_tree_tapbuf_size2_2_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size2_2_sram[0]:7 mux_tree_tapbuf_size2_2_sram[0]:6 0.002044643 +6 mux_tree_tapbuf_size2_2_sram[0]:3 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:8 0.006491072 +8 mux_tree_tapbuf_size2_2_sram[0]:9 mux_tree_tapbuf_size2_2_sram[0]:3 8.482143e-05 +9 mux_tree_tapbuf_size2_2_sram[0]:10 mux_tree_tapbuf_size2_2_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size2_2_sram[0]:12 mux_tree_tapbuf_size2_2_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size2_2_sram[0]:11 mux_tree_tapbuf_size2_2_sram[0]:10 0.009633929 +12 mux_tree_tapbuf_size2_2_sram[0]:13 mux_tree_tapbuf_size2_2_sram[0]:12 0.001430804 + +*END + +*D_NET mux_tree_tapbuf_size2_5_sram[0] 0.002366025 //LENGTH 17.035 LUMPCC 0.0004945782 DR + +*CONN +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 58.725 22.780 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 63.655 17.340 +*I mux_bottom_track_21\/mux_l1_in_0_:S I *L 0.00357 *C 66.600 20.110 +*N mux_tree_tapbuf_size2_5_sram[0]:3 *C 66.600 20.110 +*N mux_tree_tapbuf_size2_5_sram[0]:4 *C 66.600 19.720 +*N mux_tree_tapbuf_size2_5_sram[0]:5 *C 63.693 17.340 +*N mux_tree_tapbuf_size2_5_sram[0]:6 *C 65.275 17.340 +*N mux_tree_tapbuf_size2_5_sram[0]:7 *C 65.320 17.385 +*N mux_tree_tapbuf_size2_5_sram[0]:8 *C 65.320 19.675 +*N mux_tree_tapbuf_size2_5_sram[0]:9 *C 65.320 19.720 +*N mux_tree_tapbuf_size2_5_sram[0]:10 *C 59.385 19.720 +*N mux_tree_tapbuf_size2_5_sram[0]:11 *C 59.340 19.765 +*N mux_tree_tapbuf_size2_5_sram[0]:12 *C 59.340 22.735 +*N mux_tree_tapbuf_size2_5_sram[0]:13 *C 59.295 22.780 +*N mux_tree_tapbuf_size2_5_sram[0]:14 *C 58.763 22.780 + +*CAP +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_21\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_5_sram[0]:3 6.162733e-05 +4 mux_tree_tapbuf_size2_5_sram[0]:4 0.0001176304 +5 mux_tree_tapbuf_size2_5_sram[0]:5 0.0001274531 +6 mux_tree_tapbuf_size2_5_sram[0]:6 0.0001274531 +7 mux_tree_tapbuf_size2_5_sram[0]:7 0.0001607824 +8 mux_tree_tapbuf_size2_5_sram[0]:8 0.0001607824 +9 mux_tree_tapbuf_size2_5_sram[0]:9 0.0003898616 +10 mux_tree_tapbuf_size2_5_sram[0]:10 0.0002727471 +11 mux_tree_tapbuf_size2_5_sram[0]:11 0.0001764988 +12 mux_tree_tapbuf_size2_5_sram[0]:12 0.0001764988 +13 mux_tree_tapbuf_size2_5_sram[0]:13 4.855586e-05 +14 mux_tree_tapbuf_size2_5_sram[0]:14 4.855586e-05 +15 mux_tree_tapbuf_size2_5_sram[0]:9 bottom_left_grid_pin_39_[0]:12 0.0002249512 +16 mux_tree_tapbuf_size2_5_sram[0]:9 bottom_left_grid_pin_39_[0]:13 2.233782e-05 +17 mux_tree_tapbuf_size2_5_sram[0]:10 bottom_left_grid_pin_39_[0]:13 0.0002249512 +18 mux_tree_tapbuf_size2_5_sram[0]:4 bottom_left_grid_pin_39_[0]:12 2.233782e-05 + +*RES +0 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_5_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:8 0.0045 +2 mux_tree_tapbuf_size2_5_sram[0]:9 mux_tree_tapbuf_size2_5_sram[0]:4 0.001142857 +3 mux_tree_tapbuf_size2_5_sram[0]:8 mux_tree_tapbuf_size2_5_sram[0]:7 0.002044643 +4 mux_tree_tapbuf_size2_5_sram[0]:6 mux_tree_tapbuf_size2_5_sram[0]:5 0.001412946 +5 mux_tree_tapbuf_size2_5_sram[0]:7 mux_tree_tapbuf_size2_5_sram[0]:6 0.0045 +6 mux_tree_tapbuf_size2_5_sram[0]:5 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_5_sram[0]:10 mux_tree_tapbuf_size2_5_sram[0]:9 0.005299107 +8 mux_tree_tapbuf_size2_5_sram[0]:11 mux_tree_tapbuf_size2_5_sram[0]:10 0.0045 +9 mux_tree_tapbuf_size2_5_sram[0]:13 mux_tree_tapbuf_size2_5_sram[0]:12 0.0045 +10 mux_tree_tapbuf_size2_5_sram[0]:12 mux_tree_tapbuf_size2_5_sram[0]:11 0.002651786 +11 mux_tree_tapbuf_size2_5_sram[0]:14 mux_tree_tapbuf_size2_5_sram[0]:13 0.0004754465 +12 mux_tree_tapbuf_size2_5_sram[0]:3 mux_bottom_track_21\/mux_l1_in_0_:S 0.152 +13 mux_tree_tapbuf_size2_5_sram[0]:4 mux_tree_tapbuf_size2_5_sram[0]:3 0.0003482143 + +*END + +*D_NET mux_tree_tapbuf_size2_8_sram[1] 0.002244179 //LENGTH 17.460 LUMPCC 0.0006215772 DR + +*CONN +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 28.365 63.920 +*I mem_bottom_track_29\/FTB_15__30:A I *L 0.001746 *C 19.320 58.480 +*I mux_bottom_track_29\/mux_l2_in_0_:S I *L 0.00357 *C 27.040 58.480 +*N mux_tree_tapbuf_size2_8_sram[1]:3 *C 27.003 58.480 +*N mux_tree_tapbuf_size2_8_sram[1]:4 *C 19.358 58.480 +*N mux_tree_tapbuf_size2_8_sram[1]:5 *C 25.300 58.480 +*N mux_tree_tapbuf_size2_8_sram[1]:6 *C 25.300 58.525 +*N mux_tree_tapbuf_size2_8_sram[1]:7 *C 25.300 61.155 +*N mux_tree_tapbuf_size2_8_sram[1]:8 *C 25.345 61.200 +*N mux_tree_tapbuf_size2_8_sram[1]:9 *C 28.015 61.200 +*N mux_tree_tapbuf_size2_8_sram[1]:10 *C 28.060 61.245 +*N mux_tree_tapbuf_size2_8_sram[1]:11 *C 28.060 63.875 +*N mux_tree_tapbuf_size2_8_sram[1]:12 *C 28.060 63.920 +*N mux_tree_tapbuf_size2_8_sram[1]:13 *C 28.365 63.920 + +*CAP +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_29\/FTB_15__30:A 1e-06 +2 mux_bottom_track_29\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_8_sram[1]:3 9.214018e-05 +4 mux_tree_tapbuf_size2_8_sram[1]:4 0.000281397 +5 mux_tree_tapbuf_size2_8_sram[1]:5 0.0004085902 +6 mux_tree_tapbuf_size2_8_sram[1]:6 0.0001275055 +7 mux_tree_tapbuf_size2_8_sram[1]:7 0.0001275055 +8 mux_tree_tapbuf_size2_8_sram[1]:8 0.000101776 +9 mux_tree_tapbuf_size2_8_sram[1]:9 0.000101776 +10 mux_tree_tapbuf_size2_8_sram[1]:10 0.0001434173 +11 mux_tree_tapbuf_size2_8_sram[1]:11 0.0001434173 +12 mux_tree_tapbuf_size2_8_sram[1]:12 4.783253e-05 +13 mux_tree_tapbuf_size2_8_sram[1]:13 4.424475e-05 +14 mux_tree_tapbuf_size2_8_sram[1]:5 chany_bottom_in[17]:11 2.086405e-05 +15 mux_tree_tapbuf_size2_8_sram[1]:5 chany_bottom_in[17]:12 0.000100019 +16 mux_tree_tapbuf_size2_8_sram[1]:5 chany_bottom_in[17]:13 2.134946e-05 +17 mux_tree_tapbuf_size2_8_sram[1]:4 chany_bottom_in[17]:11 0.000100019 +18 mux_tree_tapbuf_size2_8_sram[1]:3 chany_bottom_in[17]:12 2.086405e-05 +19 mux_tree_tapbuf_size2_8_sram[1]:3 chany_bottom_in[17]:14 2.134946e-05 +20 mux_tree_tapbuf_size2_8_sram[1]:6 chanx_left_in[8]:4 7.388297e-06 +21 mux_tree_tapbuf_size2_8_sram[1]:8 chanx_left_in[8]:3 0.0001146844 +22 mux_tree_tapbuf_size2_8_sram[1]:7 chanx_left_in[8]:5 7.388297e-06 +23 mux_tree_tapbuf_size2_8_sram[1]:9 chanx_left_in[8]:2 0.0001146844 +24 mux_tree_tapbuf_size2_8_sram[1]:10 chanx_left_in[8]:4 2.124166e-07 +25 mux_tree_tapbuf_size2_8_sram[1]:11 chanx_left_in[8]:5 2.124166e-07 +26 mux_tree_tapbuf_size2_8_sram[1]:6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.403094e-05 +27 mux_tree_tapbuf_size2_8_sram[1]:7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 3.403094e-05 +28 mux_tree_tapbuf_size2_8_sram[1]:10 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 1.224006e-05 +29 mux_tree_tapbuf_size2_8_sram[1]:11 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 1.224006e-05 + +*RES +0 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_8_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_8_sram[1]:5 mux_tree_tapbuf_size2_8_sram[1]:4 0.005305804 +2 mux_tree_tapbuf_size2_8_sram[1]:5 mux_tree_tapbuf_size2_8_sram[1]:3 0.001520089 +3 mux_tree_tapbuf_size2_8_sram[1]:6 mux_tree_tapbuf_size2_8_sram[1]:5 0.0045 +4 mux_tree_tapbuf_size2_8_sram[1]:8 mux_tree_tapbuf_size2_8_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_8_sram[1]:7 mux_tree_tapbuf_size2_8_sram[1]:6 0.002348214 +6 mux_tree_tapbuf_size2_8_sram[1]:9 mux_tree_tapbuf_size2_8_sram[1]:8 0.002383929 +7 mux_tree_tapbuf_size2_8_sram[1]:10 mux_tree_tapbuf_size2_8_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size2_8_sram[1]:12 mux_tree_tapbuf_size2_8_sram[1]:11 0.0045 +9 mux_tree_tapbuf_size2_8_sram[1]:11 mux_tree_tapbuf_size2_8_sram[1]:10 0.002348214 +10 mux_tree_tapbuf_size2_8_sram[1]:13 mux_tree_tapbuf_size2_8_sram[1]:12 0.0001657609 +11 mux_tree_tapbuf_size2_8_sram[1]:4 mem_bottom_track_29\/FTB_15__30:A 0.152 +12 mux_tree_tapbuf_size2_8_sram[1]:3 mux_bottom_track_29\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_16_ccff_tail[0] 0.001732356 //LENGTH 16.465 LUMPCC 0.0001868145 DR + +*CONN +*I mem_left_track_9\/FTB_23__38:X O *L 0 *C 55.425 79.900 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 48.020 71.740 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 *C 48.020 71.740 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 *C 48.715 71.740 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 *C 48.760 71.785 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 *C 48.760 79.855 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 *C 48.805 79.900 +*N mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 *C 55.388 79.900 + +*CAP +0 mem_left_track_9\/FTB_23__38:X 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 9.997703e-05 +3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 6.511067e-05 +4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 0.0004176188 +5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 0.0004176188 +6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 0.0002716083 +7 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 0.0002716083 +8 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 left_top_grid_pin_1_[0]:26 9.340723e-05 +9 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 left_top_grid_pin_1_[0]:24 9.340723e-05 + +*RES +0 mem_left_track_9\/FTB_23__38:X mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:2 0.0006205357 +3 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:4 0.007205357 +6 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 0.005877232 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_3_ccff_tail[0] 0.001704687 //LENGTH 12.930 LUMPCC 0.0002321534 DR + +*CONN +*I mem_bottom_track_17\/FTB_10__25:X O *L 0 *C 64.175 46.920 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 56.755 42.500 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 *C 56.755 42.500 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 *C 56.580 42.500 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 *C 56.580 42.545 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 *C 56.580 46.875 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 *C 56.625 46.920 +*N mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 *C 64.138 46.920 + +*CAP +0 mem_bottom_track_17\/FTB_10__25:X 1e-06 +1 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 5.328196e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 5.558589e-05 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.0002173199 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0002173199 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.0004635127 +7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.0004635127 +8 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 chany_bottom_in[18] 5.234602e-05 +9 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 chany_bottom_in[18]:18 5.234602e-05 +10 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_3_sram[1]:6 3.441413e-05 +11 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_3_sram[1]:7 2.931656e-05 +12 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_3_sram[1]:3 2.931656e-05 +13 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_3_sram[1]:7 3.441413e-05 + +*RES +0 mem_bottom_track_17\/FTB_10__25:X mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:2 9.510869e-05 +3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:4 0.003866072 +6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 0.00670759 + +*END + +*D_NET mux_tree_tapbuf_size3_1_sram[0] 0.01191926 //LENGTH 90.960 LUMPCC 0.003418174 DR + +*CONN +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 77.125 42.500 +*I mux_bottom_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 25.400 50.320 +*I mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.915 47.940 +*I mux_bottom_track_25\/mux_l1_in_1_:S I *L 0.00357 *C 8.620 57.800 +*N mux_tree_tapbuf_size3_1_sram[0]:4 *C 8.582 57.800 +*N mux_tree_tapbuf_size3_1_sram[0]:5 *C 7.865 57.800 +*N mux_tree_tapbuf_size3_1_sram[0]:6 *C 7.820 57.755 +*N mux_tree_tapbuf_size3_1_sram[0]:7 *C 7.820 50.320 +*N mux_tree_tapbuf_size3_1_sram[0]:8 *C 8.280 50.320 +*N mux_tree_tapbuf_size3_1_sram[0]:9 *C 8.878 47.940 +*N mux_tree_tapbuf_size3_1_sram[0]:10 *C 8.325 47.940 +*N mux_tree_tapbuf_size3_1_sram[0]:11 *C 8.280 47.940 +*N mux_tree_tapbuf_size3_1_sram[0]:12 *C 8.280 48.338 +*N mux_tree_tapbuf_size3_1_sram[0]:13 *C 8.287 48.280 +*N mux_tree_tapbuf_size3_1_sram[0]:14 *C 25.300 50.320 +*N mux_tree_tapbuf_size3_1_sram[0]:15 *C 25.300 50.275 +*N mux_tree_tapbuf_size3_1_sram[0]:16 *C 25.300 48.338 +*N mux_tree_tapbuf_size3_1_sram[0]:17 *C 25.300 48.280 +*N mux_tree_tapbuf_size3_1_sram[0]:18 *C 75.433 48.280 +*N mux_tree_tapbuf_size3_1_sram[0]:19 *C 75.440 48.223 +*N mux_tree_tapbuf_size3_1_sram[0]:20 *C 75.440 42.545 +*N mux_tree_tapbuf_size3_1_sram[0]:21 *C 75.485 42.500 +*N mux_tree_tapbuf_size3_1_sram[0]:22 *C 77.088 42.500 + +*CAP +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_25\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size3_1_sram[0]:4 7.338002e-05 +5 mux_tree_tapbuf_size3_1_sram[0]:5 7.338002e-05 +6 mux_tree_tapbuf_size3_1_sram[0]:6 0.0004482785 +7 mux_tree_tapbuf_size3_1_sram[0]:7 0.0004777617 +8 mux_tree_tapbuf_size3_1_sram[0]:8 0.0001691951 +9 mux_tree_tapbuf_size3_1_sram[0]:9 5.915814e-05 +10 mux_tree_tapbuf_size3_1_sram[0]:10 5.915814e-05 +11 mux_tree_tapbuf_size3_1_sram[0]:11 5.434453e-05 +12 mux_tree_tapbuf_size3_1_sram[0]:12 0.0001604645 +13 mux_tree_tapbuf_size3_1_sram[0]:13 0.0009407612 +14 mux_tree_tapbuf_size3_1_sram[0]:14 3.336381e-05 +15 mux_tree_tapbuf_size3_1_sram[0]:15 0.0001308491 +16 mux_tree_tapbuf_size3_1_sram[0]:16 0.0001308491 +17 mux_tree_tapbuf_size3_1_sram[0]:17 0.002889399 +18 mux_tree_tapbuf_size3_1_sram[0]:18 0.001948638 +19 mux_tree_tapbuf_size3_1_sram[0]:19 0.0003129059 +20 mux_tree_tapbuf_size3_1_sram[0]:20 0.0003129059 +21 mux_tree_tapbuf_size3_1_sram[0]:21 0.0001111483 +22 mux_tree_tapbuf_size3_1_sram[0]:22 0.0001111483 +23 mux_tree_tapbuf_size3_1_sram[0]:15 prog_clk[0]:137 2.132515e-05 +24 mux_tree_tapbuf_size3_1_sram[0]:16 prog_clk[0]:138 2.132515e-05 +25 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:100 0.0001187712 +26 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:101 2.644241e-05 +27 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:135 5.307189e-07 +28 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:136 2.462536e-06 +29 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:139 0.0001549667 +30 mux_tree_tapbuf_size3_1_sram[0]:17 prog_clk[0]:269 9.976575e-05 +31 mux_tree_tapbuf_size3_1_sram[0]:13 prog_clk[0]:135 2.462536e-06 +32 mux_tree_tapbuf_size3_1_sram[0]:18 prog_clk[0]:86 0.0001187712 +33 mux_tree_tapbuf_size3_1_sram[0]:18 prog_clk[0]:100 2.644241e-05 +34 mux_tree_tapbuf_size3_1_sram[0]:18 prog_clk[0]:136 5.307189e-07 +35 mux_tree_tapbuf_size3_1_sram[0]:18 prog_clk[0]:140 0.0001549667 +36 mux_tree_tapbuf_size3_1_sram[0]:18 prog_clk[0]:268 9.976575e-05 +37 mux_tree_tapbuf_size3_1_sram[0]:17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.001036471 +38 mux_tree_tapbuf_size3_1_sram[0]:17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0001731943 +39 mux_tree_tapbuf_size3_1_sram[0]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 8.309686e-05 +40 mux_tree_tapbuf_size3_1_sram[0]:18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.009747e-05 +41 mux_tree_tapbuf_size3_1_sram[0]:18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.001036471 +42 mux_tree_tapbuf_size3_1_sram[0]:17 ropt_net_131:7 6.665345e-05 +43 mux_tree_tapbuf_size3_1_sram[0]:6 ropt_net_131:4 6.134301e-06 +44 mux_tree_tapbuf_size3_1_sram[0]:12 ropt_net_131:5 2.369435e-06 +45 mux_tree_tapbuf_size3_1_sram[0]:13 ropt_net_131:6 6.665345e-05 +46 mux_tree_tapbuf_size3_1_sram[0]:7 ropt_net_131:5 6.134301e-06 +47 mux_tree_tapbuf_size3_1_sram[0]:8 ropt_net_131:4 2.369435e-06 + +*RES +0 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_1_sram[0]:22 0.152 +1 mux_tree_tapbuf_size3_1_sram[0]:14 mux_bottom_track_25\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_1_sram[0]:15 mux_tree_tapbuf_size3_1_sram[0]:14 0.0045 +3 mux_tree_tapbuf_size3_1_sram[0]:16 mux_tree_tapbuf_size3_1_sram[0]:15 0.001729911 +4 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:16 0.00341 +5 mux_tree_tapbuf_size3_1_sram[0]:17 mux_tree_tapbuf_size3_1_sram[0]:13 0.002665292 +6 mux_tree_tapbuf_size3_1_sram[0]:4 mux_bottom_track_25\/mux_l1_in_1_:S 0.152 +7 mux_tree_tapbuf_size3_1_sram[0]:5 mux_tree_tapbuf_size3_1_sram[0]:4 0.000640625 +8 mux_tree_tapbuf_size3_1_sram[0]:6 mux_tree_tapbuf_size3_1_sram[0]:5 0.0045 +9 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:11 0.0001911058 +10 mux_tree_tapbuf_size3_1_sram[0]:12 mux_tree_tapbuf_size3_1_sram[0]:8 0.001770089 +11 mux_tree_tapbuf_size3_1_sram[0]:13 mux_tree_tapbuf_size3_1_sram[0]:12 0.00341 +12 mux_tree_tapbuf_size3_1_sram[0]:19 mux_tree_tapbuf_size3_1_sram[0]:18 0.00341 +13 mux_tree_tapbuf_size3_1_sram[0]:18 mux_tree_tapbuf_size3_1_sram[0]:17 0.007854091 +14 mux_tree_tapbuf_size3_1_sram[0]:21 mux_tree_tapbuf_size3_1_sram[0]:20 0.0045 +15 mux_tree_tapbuf_size3_1_sram[0]:20 mux_tree_tapbuf_size3_1_sram[0]:19 0.005069197 +16 mux_tree_tapbuf_size3_1_sram[0]:22 mux_tree_tapbuf_size3_1_sram[0]:21 0.001430804 +17 mux_tree_tapbuf_size3_1_sram[0]:10 mux_tree_tapbuf_size3_1_sram[0]:9 0.0004933036 +18 mux_tree_tapbuf_size3_1_sram[0]:11 mux_tree_tapbuf_size3_1_sram[0]:10 0.0045 +19 mux_tree_tapbuf_size3_1_sram[0]:9 mem_bottom_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +20 mux_tree_tapbuf_size3_1_sram[0]:7 mux_tree_tapbuf_size3_1_sram[0]:6 0.006638393 +21 mux_tree_tapbuf_size3_1_sram[0]:8 mux_tree_tapbuf_size3_1_sram[0]:7 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size5_mem_1_ccff_tail[0] 0.001271024 //LENGTH 9.150 LUMPCC 0.000349101 DR + +*CONN +*I mem_bottom_track_7\/FTB_4__19:X O *L 0 *C 45.315 6.460 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 40.195 9.860 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 *C 40.195 9.860 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 *C 40.480 9.860 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 *C 40.480 9.815 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 *C 40.480 6.505 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 *C 40.525 6.460 +*N mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 *C 45.278 6.460 + +*CAP +0 mem_bottom_track_7\/FTB_4__19:X 1e-06 +1 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 4.695109e-05 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 5.239235e-05 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.000194198 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.000194198 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.0002160919 +7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.0002160919 +8 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0001745505 +9 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0001745505 + +*RES +0 mem_bottom_track_7\/FTB_4__19:X mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.004243304 +2 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 0.002955357 +4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 0.0001548913 +5 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:2 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[2] 0.002784149 //LENGTH 15.910 LUMPCC 0.001197136 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 23.305 42.160 +*I mem_bottom_track_1\/FTB_1__16:A I *L 0.001746 *C 14.260 42.160 +*I mux_bottom_track_1\/mux_l3_in_0_:S I *L 0.00357 *C 23.820 39.735 +*N mux_tree_tapbuf_size6_0_sram[2]:3 *C 23.820 39.735 +*N mux_tree_tapbuf_size6_0_sram[2]:4 *C 23.920 40.120 +*N mux_tree_tapbuf_size6_0_sram[2]:5 *C 23.920 40.165 +*N mux_tree_tapbuf_size6_0_sram[2]:6 *C 14.298 42.160 +*N mux_tree_tapbuf_size6_0_sram[2]:7 *C 15.595 42.160 +*N mux_tree_tapbuf_size6_0_sram[2]:8 *C 15.640 42.115 +*N mux_tree_tapbuf_size6_0_sram[2]:9 *C 15.640 40.858 +*N mux_tree_tapbuf_size6_0_sram[2]:10 *C 15.648 40.800 +*N mux_tree_tapbuf_size6_0_sram[2]:11 *C 23.913 40.800 +*N mux_tree_tapbuf_size6_0_sram[2]:12 *C 23.920 40.800 +*N mux_tree_tapbuf_size6_0_sram[2]:13 *C 23.920 42.115 +*N mux_tree_tapbuf_size6_0_sram[2]:14 *C 23.875 42.160 +*N mux_tree_tapbuf_size6_0_sram[2]:15 *C 23.343 42.160 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_1\/FTB_1__16:A 1e-06 +2 mux_bottom_track_1\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_0_sram[2]:3 6.174569e-05 +4 mux_tree_tapbuf_size6_0_sram[2]:4 6.633112e-05 +5 mux_tree_tapbuf_size6_0_sram[2]:5 4.477527e-05 +6 mux_tree_tapbuf_size6_0_sram[2]:6 9.911027e-05 +7 mux_tree_tapbuf_size6_0_sram[2]:7 9.911027e-05 +8 mux_tree_tapbuf_size6_0_sram[2]:8 8.753076e-05 +9 mux_tree_tapbuf_size6_0_sram[2]:9 8.753076e-05 +10 mux_tree_tapbuf_size6_0_sram[2]:10 0.0003218773 +11 mux_tree_tapbuf_size6_0_sram[2]:11 0.0003218773 +12 mux_tree_tapbuf_size6_0_sram[2]:12 0.0001635956 +13 mux_tree_tapbuf_size6_0_sram[2]:13 8.12318e-05 +14 mux_tree_tapbuf_size6_0_sram[2]:14 7.464885e-05 +15 mux_tree_tapbuf_size6_0_sram[2]:15 7.464885e-05 +16 mux_tree_tapbuf_size6_0_sram[2]:8 chany_bottom_in[14]:4 3.123416e-06 +17 mux_tree_tapbuf_size6_0_sram[2]:9 chany_bottom_in[14]:5 3.123416e-06 +18 mux_tree_tapbuf_size6_0_sram[2]:10 chany_bottom_in[14]:6 0.0004723475 +19 mux_tree_tapbuf_size6_0_sram[2]:11 chany_bottom_in[14]:7 0.0004723475 +20 mux_tree_tapbuf_size6_0_sram[2]:10 chany_bottom_in[15]:10 0.0001230968 +21 mux_tree_tapbuf_size6_0_sram[2]:11 chany_bottom_in[15]:11 0.0001230968 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_0_sram[2]:15 0.152 +1 mux_tree_tapbuf_size6_0_sram[2]:6 mem_bottom_track_1\/FTB_1__16:A 0.152 +2 mux_tree_tapbuf_size6_0_sram[2]:7 mux_tree_tapbuf_size6_0_sram[2]:6 0.001158482 +3 mux_tree_tapbuf_size6_0_sram[2]:8 mux_tree_tapbuf_size6_0_sram[2]:7 0.0045 +4 mux_tree_tapbuf_size6_0_sram[2]:9 mux_tree_tapbuf_size6_0_sram[2]:8 0.001122768 +5 mux_tree_tapbuf_size6_0_sram[2]:10 mux_tree_tapbuf_size6_0_sram[2]:9 0.00341 +6 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:11 0.00341 +7 mux_tree_tapbuf_size6_0_sram[2]:12 mux_tree_tapbuf_size6_0_sram[2]:5 0.0005669643 +8 mux_tree_tapbuf_size6_0_sram[2]:11 mux_tree_tapbuf_size6_0_sram[2]:10 0.00129485 +9 mux_tree_tapbuf_size6_0_sram[2]:4 mux_tree_tapbuf_size6_0_sram[2]:3 0.00034375 +10 mux_tree_tapbuf_size6_0_sram[2]:5 mux_tree_tapbuf_size6_0_sram[2]:4 0.0045 +11 mux_tree_tapbuf_size6_0_sram[2]:3 mux_bottom_track_1\/mux_l3_in_0_:S 0.152 +12 mux_tree_tapbuf_size6_0_sram[2]:14 mux_tree_tapbuf_size6_0_sram[2]:13 0.0045 +13 mux_tree_tapbuf_size6_0_sram[2]:13 mux_tree_tapbuf_size6_0_sram[2]:12 0.001174107 +14 mux_tree_tapbuf_size6_0_sram[2]:15 mux_tree_tapbuf_size6_0_sram[2]:14 0.0004754465 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0004070788 //LENGTH 2.860 LUMPCC 0.0001664902 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_0_:X O *L 0 *C 25.475 34.340 +*I mux_bottom_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 22.905 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 22.943 34.340 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 25.438 34.340 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001192943 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001192943 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 7.935473e-05 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 3.890364e-06 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 3.890364e-06 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 7.935473e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002227679 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0] 0.01178861 //LENGTH 95.270 LUMPCC 0.001539446 DR + +*CONN +*I mux_bottom_track_1\/mux_l3_in_0_:X O *L 0 *C 24.665 38.760 +*I mux_bottom_track_1\/BUFT_P_82:A I *L 0.001776 *C 79.120 4.080 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 79.157 4.080 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 80.500 4.080 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 80.500 3.400 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 54.785 3.400 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 54.740 3.445 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 54.740 35.983 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 54.733 36.040 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 36.348 36.040 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 36.340 36.040 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 36.295 36.040 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 *C 24.885 36.040 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 *C 24.840 36.085 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 *C 24.840 38.715 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 *C 24.840 38.760 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 *C 24.665 38.760 + +*CAP +0 mux_bottom_track_1\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_1\/BUFT_P_82:A 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.0001002617 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0001448099 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.001710317 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.001665769 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.001420744 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.001420744 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0008600462 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0008600462 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 3.409842e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0008062337 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0008062337 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.0001565835 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0001565835 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 5.452863e-05 +16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 5.016095e-05 +17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 chanx_left_in[12]:7 0.0003908988 +18 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 chanx_left_in[12]:8 0.0003908988 +19 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.000148322 +20 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.000148322 +21 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.000230502 +22 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.000230502 + +*RES +0 mux_bottom_track_1\/mux_l3_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_1\/BUFT_P_82:A 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.02295982 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.02905134 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.00341 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.002880316 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0045 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.0101875 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:12 0.0045 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 0.0045 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:13 0.002348214 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:15 9.510869e-05 +14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0006071429 +15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001198661 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002457265 //LENGTH 19.395 LUMPCC 0.0005003981 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_1_:X O *L 0 *C 31.915 26.520 +*I mux_bottom_track_3\/mux_l2_in_0_:A0 I *L 0.001631 *C 19.110 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 19.148 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 20.195 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 20.240 31.575 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 20.240 28.945 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 20.240 28.900 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 20.240 28.560 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 31.695 28.560 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 31.740 28.515 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 31.740 26.565 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 31.740 26.520 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 31.915 26.520 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.427169e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.427169e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001653872 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001653872 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.538395e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005702459 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0005443746 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001067321 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001067321 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 5.646817e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.561233e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 bottom_left_grid_pin_36_[0]:32 6.276058e-06 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 bottom_left_grid_pin_36_[0]:28 0.0001279143 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 bottom_left_grid_pin_36_[0]:29 6.276058e-06 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_36_[0]:25 2.163672e-08 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 bottom_left_grid_pin_36_[0]:26 6.315898e-07 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_36_[0]:22 2.163672e-08 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 bottom_left_grid_pin_36_[0]:25 6.315898e-07 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 bottom_left_grid_pin_36_[0]:27 0.0001279143 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_tree_tapbuf_size5_0_sram[0]:6 1.113911e-06 +22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_tree_tapbuf_size5_0_sram[0]:7 1.113911e-06 +23 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_tree_tapbuf_size5_0_sram[0]:8 5.939749e-05 +24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_tree_tapbuf_size5_0_sram[0]:9 5.939749e-05 +25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size5_0_sram[0]:12 1.005085e-06 +26 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size5_0_sram[0]:14 5.383896e-05 +27 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size5_0_sram[0]:13 1.005085e-06 +28 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size5_0_sram[0]:18 5.383896e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 9.51087e-05 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.001741071 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.01022768 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002348215 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.000935268 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A0 0.152 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003035715 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0] 0.000663812 //LENGTH 4.850 LUMPCC 8.012723e-05 DR + +*CONN +*I mux_bottom_track_7\/mux_l2_in_1_:X O *L 0 *C 35.245 8.840 +*I mux_bottom_track_7\/mux_l3_in_0_:A0 I *L 0.001631 *C 36.975 6.460 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 36.975 6.460 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 36.800 6.460 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 36.800 6.505 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 36.800 8.795 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 36.755 8.840 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 35.282 8.840 + +*CAP +0 mux_bottom_track_7\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 5.163021e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 5.316135e-05 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001335664 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0001335664 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0001048802 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0001048802 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:7 5.444449e-06 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_tree_tapbuf_size5_1_sram[1]:11 3.461917e-05 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:8 5.444449e-06 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_tree_tapbuf_size5_1_sram[1]:10 3.461917e-05 + +*RES +0 mux_bottom_track_7\/mux_l2_in_1_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_7\/mux_l3_in_0_:A0 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:2 9.51087e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.002044643 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002740934 //LENGTH 19.945 LUMPCC 0.001221079 DR + +*CONN +*I mux_bottom_track_11\/mux_l1_in_0_:X O *L 0 *C 48.125 17.340 +*I mux_bottom_track_11\/mux_l2_in_0_:A1 I *L 0.00198 *C 58.980 9.180 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 58.943 9.180 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 58.465 9.180 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 58.420 9.225 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 58.420 17.295 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 58.375 17.340 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 48.163 17.340 + +*CAP +0 mux_bottom_track_11\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_11\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.350436e-05 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.350436e-05 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002662738 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002662738 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004491494 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004491494 +8 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[18] 0.0001016824 +9 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[18]:18 0.0001016824 +10 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_107:18 8.641549e-06 +11 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 optlc_net_107:17 5.462111e-06 +12 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_107:17 8.641549e-06 +13 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 optlc_net_107:16 5.462111e-06 +14 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_107:19 6.458754e-05 +15 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 optlc_net_107:23 4.2772e-05 +16 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 optlc_net_107:21 0.0003873938 +17 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_107:22 4.2772e-05 +18 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 optlc_net_107:24 6.458754e-05 +19 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 optlc_net_107:20 0.0003873938 + +*RES +0 mux_bottom_track_11\/mux_l1_in_0_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_11\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.007205358 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.009118304 + +*END + +*D_NET mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0] 0.008900755 //LENGTH 72.590 LUMPCC 0.0003584765 DR + +*CONN +*I mux_bottom_track_15\/mux_l2_in_0_:X O *L 0 *C 38.925 60.520 +*I mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 55.570 6.670 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 55.570 6.670 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 55.660 6.800 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 55.660 6.845 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 55.660 8.103 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 55.653 8.160 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 44.180 8.160 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 44.160 8.168 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 44.160 59.833 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 44.140 59.840 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 39.108 59.840 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 39.100 59.898 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 39.100 60.475 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 39.100 60.520 +*N mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 38.925 60.520 + +*CAP +0 mux_bottom_track_15\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.289698e-05 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.909738e-05 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 9.786994e-05 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.786994e-05 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005706385 +7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005706385 +8 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.003057822 +9 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.003057822 +10 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000379077 +11 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.000379077 +12 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.708699e-05 +13 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 5.708699e-05 +14 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 5.399728e-05 +15 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 4.929779e-05 +16 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_107:12 0.0001792383 +17 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_107:13 0.0001792383 + +*RES +0 mux_bottom_track_15\/mux_l2_in_0_:X mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.152 +1 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 9.51087e-05 +2 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0045 +3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.000515625 +4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000788425 +6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.008094183 +8 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001797358 +9 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +10 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001122768 +11 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +12 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.891305e-05 +13 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +14 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002059075 //LENGTH 16.620 LUMPCC 0.0004553426 DR + +*CONN +*I mux_bottom_track_23\/mux_l1_in_0_:X O *L 0 *C 89.415 19.720 +*I mux_bottom_track_23\/mux_l2_in_0_:A1 I *L 0.00198 *C 80.865 12.580 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 80.903 12.580 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 83.215 12.580 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 83.260 12.625 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 83.260 19.675 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 83.305 19.720 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 89.377 19.720 + +*CAP +0 mux_bottom_track_23\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001637326 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001637326 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002311087 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002311087 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0004060247 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0004060247 +8 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 chany_bottom_in[0] 9.707203e-05 +9 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 chany_bottom_in[0]:14 9.707203e-05 +10 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001305993 +11 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001305993 + +*RES +0 mux_bottom_track_23\/mux_l1_in_0_:X mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_23\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002064732 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.006294643 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.005421875 + +*END + +*D_NET mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01267644 //LENGTH 108.845 LUMPCC 0.002110144 DR + +*CONN +*I mux_bottom_track_29\/mux_l2_in_0_:X O *L 0 *C 27.885 59.160 +*I mux_bottom_track_29\/BUFT_RR_44:A I *L 0.001746 *C 88.780 14.960 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 88.818 14.960 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 89.655 14.960 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 89.700 15.005 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 89.700 55.703 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 89.693 55.760 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 60.268 55.760 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 60.260 55.818 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 60.260 58.775 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 60.215 58.820 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 41.400 58.820 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 41.400 59.160 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 27.923 59.160 + +*CAP +0 mux_bottom_track_29\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_29\/BUFT_RR_44:A 1e-06 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.55383e-05 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.55383e-05 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001609954 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001609954 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001788681 +7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001788681 +8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001707698 +9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001707698 +10 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0007276788 +11 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0007520189 +12 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0009195263 +13 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0008951862 +14 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_bottom_in[17]:14 8.567386e-06 +15 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_bottom_in[17]:16 0.0006651818 +16 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 chany_bottom_in[17]:13 3.917657e-05 +17 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 chany_bottom_in[17]:14 3.917657e-05 +18 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chany_bottom_in[17]:13 8.567386e-06 +19 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chany_bottom_in[17]:15 0.0006651818 +20 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[3] 0.0002995134 +21 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[3]:8 4.263277e-05 +22 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[3]:7 4.263277e-05 +23 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[3]:8 0.0002995134 + +*RES +0 mux_bottom_track_29\/mux_l2_in_0_:X mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.152 +1 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_29\/BUFT_RR_44:A 0.152 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0007477679 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.03633706 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.004609917 +8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.002640625 +10 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.01203348 +11 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0003035715 +12 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.01679911 + +*END + +*D_NET mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002914011 //LENGTH 23.310 LUMPCC 0.0007705602 DR + +*CONN +*I mux_bottom_track_39\/mux_l2_in_0_:X O *L 0 *C 84.355 26.180 +*I mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 76.120 12.080 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 76.120 12.080 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 75.900 12.240 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 75.900 12.285 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 75.900 26.135 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 75.945 26.180 +*N mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 84.318 26.180 + +*CAP +0 mux_bottom_track_39\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.824018e-05 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.645159e-05 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00059828 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00059828 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004150994 +7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004150994 +8 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_13_sram[0]:7 4.163464e-06 +9 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size2_13_sram[0]:8 0.0002319119 +10 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size2_13_sram[0]:10 1.085518e-05 +11 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_13_sram[0]:6 4.163464e-06 +12 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size2_13_sram[0]:3 0.0002319119 +13 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size2_13_sram[0]:9 1.085518e-05 +14 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001383496 +15 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001383496 + +*RES +0 mux_bottom_track_39\/mux_l2_in_0_:X mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001195652 +2 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +3 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.01236607 +5 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.007475447 +6 mux_bottom_track_39/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01046738 //LENGTH 83.880 LUMPCC 0.004215359 DR + +*CONN +*I mux_left_track_9\/mux_l2_in_0_:X O *L 0 *C 82.515 61.540 +*I mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 6.650 61.065 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 6.688 61.155 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 7.775 61.200 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 7.820 61.245 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 7.820 64.543 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 7.828 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 61.172 64.600 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 61.180 64.543 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 61.180 61.585 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 61.225 61.540 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 82.478 61.540 + +*CAP +0 mux_left_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.352093e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 7.352093e-05 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002006871 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002006871 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001477492 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001477492 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001721534 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001721534 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001201155 +11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.001201155 +12 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[4]:7 2.629714e-06 +13 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[4]:6 2.629714e-06 +14 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[4]:13 6.052656e-06 +15 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[4]:17 0.000242356 +16 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[4]:14 6.052656e-06 +17 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[4]:18 0.000242356 +18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[13]:7 0.001207659 +19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[13]:8 7.106716e-05 +20 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[13]:8 0.001207659 +21 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[13]:9 7.106716e-05 +22 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_106:19 0.0005779145 +23 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_106:18 0.0005779145 + +*RES +0 mux_left_track_9\/mux_l2_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_9\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009709822 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002944196 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.008357383 +8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.002640625 +10 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.01897545 + +*END + +*D_NET ropt_net_138 0.00126702 //LENGTH 9.460 LUMPCC 0.0002964044 DR + +*CONN +*I ropt_mt_inst_728:X O *L 0 *C 11.600 97.240 +*I ropt_mt_inst_754:A I *L 0.001767 *C 3.220 96.560 +*N ropt_net_138:2 *C 3.220 96.560 +*N ropt_net_138:3 *C 3.220 97.240 +*N ropt_net_138:4 *C 11.562 97.240 + +*CAP +0 ropt_mt_inst_728:X 1e-06 +1 ropt_mt_inst_754:A 1e-06 +2 ropt_net_138:2 7.50725e-05 +3 ropt_net_138:3 0.0004697617 +4 ropt_net_138:4 0.0004237819 +5 ropt_net_138:4 chany_bottom_in[9]:7 7.000229e-05 +6 ropt_net_138:3 chany_bottom_in[9]:6 7.000229e-05 +7 ropt_net_138:4 ropt_net_113:3 7.819988e-05 +8 ropt_net_138:3 ropt_net_113:4 7.819988e-05 + +*RES +0 ropt_mt_inst_728:X ropt_net_138:4 0.152 +1 ropt_net_138:4 ropt_net_138:3 0.007448661 +2 ropt_net_138:2 ropt_mt_inst_754:A 0.152 +3 ropt_net_138:3 ropt_net_138:2 0.0006071429 + +*END + +*D_NET ropt_net_143 0.0005920931 //LENGTH 4.930 LUMPCC 0.0001327094 DR + +*CONN +*I ropt_mt_inst_733:X O *L 0 *C 4.140 72.760 +*I ropt_mt_inst_762:A I *L 0.001766 *C 7.820 72.080 +*N ropt_net_143:2 *C 7.783 72.080 +*N ropt_net_143:3 *C 4.600 72.080 +*N ropt_net_143:4 *C 4.600 72.760 +*N ropt_net_143:5 *C 4.178 72.760 + +*CAP +0 ropt_mt_inst_733:X 1e-06 +1 ropt_mt_inst_762:A 1e-06 +2 ropt_net_143:2 0.0001515156 +3 ropt_net_143:3 0.0001923252 +4 ropt_net_143:4 7.717624e-05 +5 ropt_net_143:5 3.636664e-05 +6 ropt_net_143:2 chany_bottom_in[4]:5 5.926772e-05 +7 ropt_net_143:5 chany_bottom_in[4]:4 5.685497e-06 +8 ropt_net_143:4 chany_bottom_in[4]:3 1.401458e-06 +9 ropt_net_143:4 chany_bottom_in[4]:5 5.685497e-06 +10 ropt_net_143:3 chany_bottom_in[4]:4 6.066918e-05 + +*RES +0 ropt_mt_inst_733:X ropt_net_143:5 0.152 +1 ropt_net_143:2 ropt_mt_inst_762:A 0.152 +2 ropt_net_143:5 ropt_net_143:4 0.0003772322 +3 ropt_net_143:4 ropt_net_143:3 0.0006071429 +4 ropt_net_143:3 ropt_net_143:2 0.002841518 + +*END + +*D_NET ropt_net_142 0.0003848886 //LENGTH 3.510 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_738:X O *L 0 *C 4.600 69.360 +*I ropt_mt_inst_761:A I *L 0.001766 *C 7.820 69.360 +*N ropt_net_142:2 *C 7.783 69.360 +*N ropt_net_142:3 *C 4.638 69.360 + +*CAP +0 ropt_mt_inst_738:X 1e-06 +1 ropt_mt_inst_761:A 1e-06 +2 ropt_net_142:2 0.0001914443 +3 ropt_net_142:3 0.0001914443 + +*RES +0 ropt_mt_inst_738:X ropt_net_142:3 0.152 +1 ropt_net_142:3 ropt_net_142:2 0.002808036 +2 ropt_net_142:2 ropt_mt_inst_761:A 0.152 + +*END + +*D_NET chanx_left_out[11] 0.0005619759 //LENGTH 4.405 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_749:X O *L 0 *C 4.140 93.160 +*P chanx_left_out[11] O *L 0.7423 *C 1.230 92.480 +*N chanx_left_out[11]:2 *C 1.833 92.480 +*N chanx_left_out[11]:3 *C 1.840 92.538 +*N chanx_left_out[11]:4 *C 1.840 93.115 +*N chanx_left_out[11]:5 *C 1.885 93.160 +*N chanx_left_out[11]:6 *C 4.103 93.160 + +*CAP +0 ropt_mt_inst_749:X 1e-06 +1 chanx_left_out[11] 6.500853e-05 +2 chanx_left_out[11]:2 6.500853e-05 +3 chanx_left_out[11]:3 5.532809e-05 +4 chanx_left_out[11]:4 5.532809e-05 +5 chanx_left_out[11]:5 0.0001601514 +6 chanx_left_out[11]:6 0.0001601514 + +*RES +0 ropt_mt_inst_749:X chanx_left_out[11]:6 0.152 +1 chanx_left_out[11]:6 chanx_left_out[11]:5 0.001979911 +2 chanx_left_out[11]:5 chanx_left_out[11]:4 0.0045 +3 chanx_left_out[11]:4 chanx_left_out[11]:3 0.000515625 +4 chanx_left_out[11]:3 chanx_left_out[11]:2 0.00341 +5 chanx_left_out[11]:2 chanx_left_out[11] 9.439165e-05 + +*END + +*D_NET chanx_left_out[14] 0.0009726408 //LENGTH 8.500 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_752:X O *L 0 *C 4.140 74.120 +*P chanx_left_out[14] O *L 0.7423 *C 1.298 69.360 +*N chanx_left_out[14]:2 *C 1.380 69.360 +*N chanx_left_out[14]:3 *C 1.380 69.418 +*N chanx_left_out[14]:4 *C 1.380 74.075 +*N chanx_left_out[14]:5 *C 1.425 74.120 +*N chanx_left_out[14]:6 *C 4.103 74.120 + +*CAP +0 ropt_mt_inst_752:X 1e-06 +1 chanx_left_out[14] 3.095716e-05 +2 chanx_left_out[14]:2 3.095716e-05 +3 chanx_left_out[14]:3 0.0002621258 +4 chanx_left_out[14]:4 0.0002621258 +5 chanx_left_out[14]:5 0.0001927375 +6 chanx_left_out[14]:6 0.0001927375 + +*RES +0 ropt_mt_inst_752:X chanx_left_out[14]:6 0.152 +1 chanx_left_out[14]:6 chanx_left_out[14]:5 0.002390625 +2 chanx_left_out[14]:5 chanx_left_out[14]:4 0.0045 +3 chanx_left_out[14]:4 chanx_left_out[14]:3 0.004158482 +4 chanx_left_out[14]:3 chanx_left_out[14]:2 0.00341 +5 chanx_left_out[14]:2 chanx_left_out[14] 2.35e-05 + +*END + +*D_NET mem_left_track_25/net_net_59 0.0004076165 //LENGTH 3.535 LUMPCC 0 DR + +*CONN +*I mem_left_track_25\/FTB_24__39:X O *L 0 *C 11.265 76.840 +*I mem_left_track_25\/BUFT_RR_97:A I *L 0.001746 *C 10.580 77.520 +*N mem_left_track_25/net_net_59:2 *C 10.580 77.520 +*N mem_left_track_25/net_net_59:3 *C 10.580 77.180 +*N mem_left_track_25/net_net_59:4 *C 11.500 77.180 +*N mem_left_track_25/net_net_59:5 *C 11.500 76.875 +*N mem_left_track_25/net_net_59:6 *C 11.293 76.862 + +*CAP +0 mem_left_track_25\/FTB_24__39:X 1e-06 +1 mem_left_track_25\/BUFT_RR_97:A 1e-06 +2 mem_left_track_25/net_net_59:2 5.616562e-05 +3 mem_left_track_25/net_net_59:3 0.0001473446 +4 mem_left_track_25/net_net_59:4 0.0001471276 +5 mem_left_track_25/net_net_59:5 4.091073e-05 +6 mem_left_track_25/net_net_59:6 1.406797e-05 + +*RES +0 mem_left_track_25\/FTB_24__39:X mem_left_track_25/net_net_59:6 0.152 +1 mem_left_track_25/net_net_59:2 mem_left_track_25\/BUFT_RR_97:A 0.152 +2 mem_left_track_25/net_net_59:6 mem_left_track_25/net_net_59:5 0.0001402027 +3 mem_left_track_25/net_net_59:3 mem_left_track_25/net_net_59:2 0.0003035715 +4 mem_left_track_25/net_net_59:4 mem_left_track_25/net_net_59:3 0.0008214285 +5 mem_left_track_25/net_net_59:5 mem_left_track_25/net_net_59:4 0.0002723215 + +*END + +*D_NET chanx_left_out[13] 0.0005375068 //LENGTH 4.405 LUMPCC 8.643484e-05 DR + +*CONN +*I ropt_mt_inst_757:X O *L 0 *C 4.140 86.360 +*P chanx_left_out[13] O *L 0.7423 *C 1.230 87.040 +*N chanx_left_out[13]:2 *C 3.213 87.040 +*N chanx_left_out[13]:3 *C 3.220 86.983 +*N chanx_left_out[13]:4 *C 3.220 86.405 +*N chanx_left_out[13]:5 *C 3.265 86.360 +*N chanx_left_out[13]:6 *C 4.103 86.360 + +*CAP +0 ropt_mt_inst_757:X 1e-06 +1 chanx_left_out[13] 0.0001374688 +2 chanx_left_out[13]:2 0.0001374688 +3 chanx_left_out[13]:3 5.01221e-05 +4 chanx_left_out[13]:4 5.01221e-05 +5 chanx_left_out[13]:5 3.74451e-05 +6 chanx_left_out[13]:6 3.74451e-05 +7 chanx_left_out[13]:6 ropt_net_141:4 4.321742e-05 +8 chanx_left_out[13]:5 ropt_net_141:3 4.321742e-05 + +*RES +0 ropt_mt_inst_757:X chanx_left_out[13]:6 0.152 +1 chanx_left_out[13]:6 chanx_left_out[13]:5 0.000747768 +2 chanx_left_out[13]:5 chanx_left_out[13]:4 0.0045 +3 chanx_left_out[13]:4 chanx_left_out[13]:3 0.000515625 +4 chanx_left_out[13]:3 chanx_left_out[13]:2 0.00341 +5 chanx_left_out[13]:2 chanx_left_out[13] 0.0003105917 + +*END + +*D_NET chanx_left_out[8] 0.001822771 //LENGTH 12.465 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_766:X O *L 0 *C 11.695 85.000 +*P chanx_left_out[8] O *L 0.7423 *C 1.230 85.680 +*N chanx_left_out[8]:2 *C 1.840 85.680 +*N chanx_left_out[8]:3 *C 1.840 85.000 +*N chanx_left_out[8]:4 *C 11.953 85.000 +*N chanx_left_out[8]:5 *C 11.960 85.000 +*N chanx_left_out[8]:6 *C 11.960 85.000 +*N chanx_left_out[8]:7 *C 11.695 85.000 + +*CAP +0 ropt_mt_inst_766:X 1e-06 +1 chanx_left_out[8] 7.919085e-05 +2 chanx_left_out[8]:2 0.0001273192 +3 chanx_left_out[8]:3 0.0007568335 +4 chanx_left_out[8]:4 0.000708705 +5 chanx_left_out[8]:5 3.427242e-05 +6 chanx_left_out[8]:6 5.552989e-05 +7 chanx_left_out[8]:7 5.99203e-05 + +*RES +0 ropt_mt_inst_766:X chanx_left_out[8]:7 0.152 +1 chanx_left_out[8]:7 chanx_left_out[8]:6 0.0001440218 +2 chanx_left_out[8]:6 chanx_left_out[8]:5 0.0045 +3 chanx_left_out[8]:5 chanx_left_out[8]:4 0.00341 +4 chanx_left_out[8]:4 chanx_left_out[8]:3 0.001584292 +5 chanx_left_out[8]:2 chanx_left_out[8] 9.556665e-05 +6 chanx_left_out[8]:3 chanx_left_out[8]:2 0.0001065333 + +*END + +*D_NET chany_bottom_in[6] 0.01841626 //LENGTH 144.635 LUMPCC 0.005547573 DR + +*CONN +*P chany_bottom_in[6] I *L 0.29796 *C 94.300 1.290 +*I ropt_mt_inst_736:A I *L 0.001766 *C 3.220 53.040 +*N chany_bottom_in[6]:2 *C 3.258 53.040 +*N chany_bottom_in[6]:3 *C 4.095 53.040 +*N chany_bottom_in[6]:4 *C 4.140 52.995 +*N chany_bottom_in[6]:5 *C 4.140 45.265 +*N chany_bottom_in[6]:6 *C 4.185 45.220 +*N chany_bottom_in[6]:7 *C 8.235 45.220 +*N chany_bottom_in[6]:8 *C 8.280 45.175 +*N chany_bottom_in[6]:9 *C 8.280 44.258 +*N chany_bottom_in[6]:10 *C 8.287 44.200 +*N chany_bottom_in[6]:11 *C 58.115 44.200 +*N chany_bottom_in[6]:12 *C 94.293 44.200 +*N chany_bottom_in[6]:13 *C 94.300 44.143 + +*CAP +0 chany_bottom_in[6] 0.001916099 +1 ropt_mt_inst_736:A 1e-06 +2 chany_bottom_in[6]:2 8.489792e-05 +3 chany_bottom_in[6]:3 8.489792e-05 +4 chany_bottom_in[6]:4 0.0003975815 +5 chany_bottom_in[6]:5 0.0003975815 +6 chany_bottom_in[6]:6 0.0002197646 +7 chany_bottom_in[6]:7 0.0002197646 +8 chany_bottom_in[6]:8 7.219202e-05 +9 chany_bottom_in[6]:9 7.219202e-05 +10 chany_bottom_in[6]:10 0.001852339 +11 chany_bottom_in[6]:11 0.003743306 +12 chany_bottom_in[6]:12 0.001890966 +13 chany_bottom_in[6]:13 0.001916099 +14 chany_bottom_in[6]:8 chany_bottom_in[2]:4 2.241439e-06 +15 chany_bottom_in[6]:9 chany_bottom_in[2]:5 2.241439e-06 +16 chany_bottom_in[6]:10 chany_bottom_in[2]:6 0.00107314 +17 chany_bottom_in[6]:12 chany_bottom_in[2]:7 3.586666e-05 +18 chany_bottom_in[6]:12 chany_bottom_in[2]:8 0.0004679178 +19 chany_bottom_in[6]:11 chany_bottom_in[2]:6 3.586666e-05 +20 chany_bottom_in[6]:11 chany_bottom_in[2]:7 0.001541057 +21 chany_bottom_in[6]:4 chanx_left_in[4]:13 4.844474e-05 +22 chany_bottom_in[6]:5 chanx_left_in[4]:12 4.844474e-05 +23 chany_bottom_in[6]:10 chanx_left_in[4]:11 0.0003584802 +24 chany_bottom_in[6]:11 chanx_left_in[4]:10 0.0003584802 +25 chany_bottom_in[6] ropt_net_122:4 3.799818e-05 +26 chany_bottom_in[6]:13 ropt_net_122:3 3.799818e-05 +27 chany_bottom_in[6]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.000472595 +28 chany_bottom_in[6]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 1.89446e-05 +29 chany_bottom_in[6]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 1.89446e-05 +30 chany_bottom_in[6]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.000472595 +31 chany_bottom_in[6]:4 ropt_net_129:6 1.546417e-05 +32 chany_bottom_in[6]:6 ropt_net_129:8 9.45198e-05 +33 chany_bottom_in[6]:5 ropt_net_129:7 1.546417e-05 +34 chany_bottom_in[6]:7 ropt_net_129:9 9.45198e-05 +35 chany_bottom_in[6]:8 ropt_net_129:6 6.465518e-08 +36 chany_bottom_in[6]:9 ropt_net_129:7 6.465518e-08 +37 chany_bottom_in[6]:8 ropt_net_130:12 6.575148e-08 +38 chany_bottom_in[6]:9 ropt_net_130:11 6.575148e-08 +39 chany_bottom_in[6]:10 ropt_net_130:9 0.000148044 +40 chany_bottom_in[6]:11 ropt_net_130:10 0.000148044 + +*RES +0 chany_bottom_in[6] chany_bottom_in[6]:13 0.03826116 +1 chany_bottom_in[6]:2 ropt_mt_inst_736:A 0.152 +2 chany_bottom_in[6]:3 chany_bottom_in[6]:2 0.0007477679 +3 chany_bottom_in[6]:4 chany_bottom_in[6]:3 0.0045 +4 chany_bottom_in[6]:6 chany_bottom_in[6]:5 0.0045 +5 chany_bottom_in[6]:5 chany_bottom_in[6]:4 0.006901786 +6 chany_bottom_in[6]:7 chany_bottom_in[6]:6 0.003616072 +7 chany_bottom_in[6]:8 chany_bottom_in[6]:7 0.0045 +8 chany_bottom_in[6]:9 chany_bottom_in[6]:8 0.0008191965 +9 chany_bottom_in[6]:10 chany_bottom_in[6]:9 0.00341 +10 chany_bottom_in[6]:13 chany_bottom_in[6]:12 0.00341 +11 chany_bottom_in[6]:12 chany_bottom_in[6]:11 0.005667808 +12 chany_bottom_in[6]:11 chany_bottom_in[6]:10 0.007806308 + +*END + +*D_NET chany_bottom_out[5] 0.0008567512 //LENGTH 7.215 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 68.140 4.420 +*P chany_bottom_out[5] O *L 0.7423 *C 71.760 1.290 +*N chany_bottom_out[5]:2 *C 71.760 4.375 +*N chany_bottom_out[5]:3 *C 71.715 4.420 +*N chany_bottom_out[5]:4 *C 68.178 4.420 + +*CAP +0 mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[5] 0.000201382 +2 chany_bottom_out[5]:2 0.000201382 +3 chany_bottom_out[5]:3 0.0002264936 +4 chany_bottom_out[5]:4 0.0002264936 + +*RES +0 mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[5]:4 0.152 +1 chany_bottom_out[5]:4 chany_bottom_out[5]:3 0.003158482 +2 chany_bottom_out[5]:3 chany_bottom_out[5]:2 0.0045 +3 chany_bottom_out[5]:2 chany_bottom_out[5] 0.002754464 + +*END + +*D_NET chany_bottom_out[12] 0.002288806 //LENGTH 18.845 LUMPCC 0.000292517 DR + +*CONN +*I mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 85.100 14.960 +*P chany_bottom_out[12] O *L 0.7423 *C 80.500 1.290 +*N chany_bottom_out[12]:2 *C 80.500 14.235 +*N chany_bottom_out[12]:3 *C 80.545 14.280 +*N chany_bottom_out[12]:4 *C 85.100 14.280 +*N chany_bottom_out[12]:5 *C 85.100 14.960 + +*CAP +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[12] 0.0007002657 +2 chany_bottom_out[12]:2 0.0007002657 +3 chany_bottom_out[12]:3 0.0002384074 +4 chany_bottom_out[12]:4 0.0002833472 +5 chany_bottom_out[12]:5 7.300297e-05 +6 chany_bottom_out[12]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001462585 +7 chany_bottom_out[12]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001462585 + +*RES +0 mux_bottom_track_25\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[12]:5 0.152 +1 chany_bottom_out[12]:3 chany_bottom_out[12]:2 0.0045 +2 chany_bottom_out[12]:2 chany_bottom_out[12] 0.01155804 +3 chany_bottom_out[12]:5 chany_bottom_out[12]:4 0.0006071429 +4 chany_bottom_out[12]:4 chany_bottom_out[12]:3 0.004066965 + +*END + +*D_NET chanx_left_out[2] 0.0006881298 //LENGTH 6.050 LUMPCC 0 DR + +*CONN +*I mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 4.085 31.620 +*P chanx_left_out[2] O *L 0.7423 *C 1.230 34.000 +*N chanx_left_out[2]:2 *C 3.673 34.000 +*N chanx_left_out[2]:3 *C 3.680 33.943 +*N chanx_left_out[2]:4 *C 3.680 31.665 +*N chanx_left_out[2]:5 *C 3.703 31.620 +*N chanx_left_out[2]:6 *C 4.070 31.620 + +*CAP +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[2] 0.0001696874 +2 chanx_left_out[2]:2 0.0001696874 +3 chanx_left_out[2]:3 0.0001324264 +4 chanx_left_out[2]:4 0.0001324264 +5 chanx_left_out[2]:5 4.145112e-05 +6 chanx_left_out[2]:6 4.145112e-05 + +*RES +0 mux_left_track_5\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[2]:6 0.152 +1 chanx_left_out[2]:6 chanx_left_out[2]:5 0.0001997283 +2 chanx_left_out[2]:5 chanx_left_out[2]:4 0.0045 +3 chanx_left_out[2]:4 chanx_left_out[2]:3 0.002033482 +4 chanx_left_out[2]:3 chanx_left_out[2]:2 0.00341 +5 chanx_left_out[2]:2 chanx_left_out[2] 0.0003826583 + +*END + +*D_NET mux_tree_tapbuf_size2_0_sram[1] 0.002398562 //LENGTH 19.030 LUMPCC 0.0009447056 DR + +*CONN +*I mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 56.885 20.400 +*I mem_bottom_track_11\/FTB_7__22:A I *L 0.001746 *C 61.640 14.960 +*I mux_bottom_track_11\/mux_l2_in_0_:S I *L 0.00357 *C 59.700 8.840 +*N mux_tree_tapbuf_size2_0_sram[1]:3 *C 59.738 8.840 +*N mux_tree_tapbuf_size2_0_sram[1]:4 *C 61.135 8.840 +*N mux_tree_tapbuf_size2_0_sram[1]:5 *C 61.180 8.885 +*N mux_tree_tapbuf_size2_0_sram[1]:6 *C 61.603 14.960 +*N mux_tree_tapbuf_size2_0_sram[1]:7 *C 61.225 14.960 +*N mux_tree_tapbuf_size2_0_sram[1]:8 *C 61.180 14.960 +*N mux_tree_tapbuf_size2_0_sram[1]:9 *C 61.180 20.355 +*N mux_tree_tapbuf_size2_0_sram[1]:10 *C 61.135 20.400 +*N mux_tree_tapbuf_size2_0_sram[1]:11 *C 56.922 20.400 + +*CAP +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_11\/FTB_7__22:A 1e-06 +2 mux_bottom_track_11\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_0_sram[1]:3 0.0001428004 +4 mux_tree_tapbuf_size2_0_sram[1]:4 0.0001428004 +5 mux_tree_tapbuf_size2_0_sram[1]:5 0.00018729 +6 mux_tree_tapbuf_size2_0_sram[1]:6 4.895698e-05 +7 mux_tree_tapbuf_size2_0_sram[1]:7 4.895698e-05 +8 mux_tree_tapbuf_size2_0_sram[1]:8 0.0003817287 +9 mux_tree_tapbuf_size2_0_sram[1]:9 0.0001637952 +10 mux_tree_tapbuf_size2_0_sram[1]:10 0.0001672637 +11 mux_tree_tapbuf_size2_0_sram[1]:11 0.0001672637 +12 mux_tree_tapbuf_size2_0_sram[1]:8 chany_bottom_in[10]:14 8.038932e-05 +13 mux_tree_tapbuf_size2_0_sram[1]:8 chany_bottom_in[10]:15 7.25431e-05 +14 mux_tree_tapbuf_size2_0_sram[1]:9 chany_bottom_in[10]:14 7.25431e-05 +15 mux_tree_tapbuf_size2_0_sram[1]:5 chany_bottom_in[10]:15 8.038932e-05 +16 mux_tree_tapbuf_size2_0_sram[1]:10 bottom_left_grid_pin_39_[0]:12 0.0001687555 +17 mux_tree_tapbuf_size2_0_sram[1]:11 bottom_left_grid_pin_39_[0]:13 0.0001687555 +18 mux_tree_tapbuf_size2_0_sram[1]:8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.812175e-05 +19 mux_tree_tapbuf_size2_0_sram[1]:8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.25431e-05 +20 mux_tree_tapbuf_size2_0_sram[1]:9 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.25431e-05 +21 mux_tree_tapbuf_size2_0_sram[1]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.812175e-05 + +*RES +0 mem_bottom_track_11\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_0_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_0_sram[1]:7 mux_tree_tapbuf_size2_0_sram[1]:6 0.0003370536 +2 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:7 0.0045 +3 mux_tree_tapbuf_size2_0_sram[1]:8 mux_tree_tapbuf_size2_0_sram[1]:5 0.005424107 +4 mux_tree_tapbuf_size2_0_sram[1]:6 mem_bottom_track_11\/FTB_7__22:A 0.152 +5 mux_tree_tapbuf_size2_0_sram[1]:10 mux_tree_tapbuf_size2_0_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_0_sram[1]:9 mux_tree_tapbuf_size2_0_sram[1]:8 0.004816964 +7 mux_tree_tapbuf_size2_0_sram[1]:11 mux_tree_tapbuf_size2_0_sram[1]:10 0.003761161 +8 mux_tree_tapbuf_size2_0_sram[1]:4 mux_tree_tapbuf_size2_0_sram[1]:3 0.001247768 +9 mux_tree_tapbuf_size2_0_sram[1]:5 mux_tree_tapbuf_size2_0_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size2_0_sram[1]:3 mux_bottom_track_11\/mux_l2_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_15_sram[1] 0.008869194 //LENGTH 74.325 LUMPCC 0.001000874 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 76.205 58.995 +*I mux_left_track_5\/mux_l2_in_0_:S I *L 0.00357 *C 58.060 28.560 +*I mem_left_track_5\/FTB_22__37:A I *L 0.001746 *C 95.680 61.200 +*N mux_tree_tapbuf_size2_15_sram[1]:3 *C 95.680 61.200 +*N mux_tree_tapbuf_size2_15_sram[1]:4 *C 95.680 60.860 +*N mux_tree_tapbuf_size2_15_sram[1]:5 *C 77.325 60.860 +*N mux_tree_tapbuf_size2_15_sram[1]:6 *C 77.280 60.815 +*N mux_tree_tapbuf_size2_15_sram[1]:7 *C 77.280 58.865 +*N mux_tree_tapbuf_size2_15_sram[1]:8 *C 77.235 58.820 +*N mux_tree_tapbuf_size2_15_sram[1]:9 *C 58.098 28.560 +*N mux_tree_tapbuf_size2_15_sram[1]:10 *C 59.800 28.560 +*N mux_tree_tapbuf_size2_15_sram[1]:11 *C 59.800 28.220 +*N mux_tree_tapbuf_size2_15_sram[1]:12 *C 61.135 28.220 +*N mux_tree_tapbuf_size2_15_sram[1]:13 *C 61.180 28.265 +*N mux_tree_tapbuf_size2_15_sram[1]:14 *C 61.180 53.663 +*N mux_tree_tapbuf_size2_15_sram[1]:15 *C 61.188 53.720 +*N mux_tree_tapbuf_size2_15_sram[1]:16 *C 75.433 53.720 +*N mux_tree_tapbuf_size2_15_sram[1]:17 *C 75.440 53.778 +*N mux_tree_tapbuf_size2_15_sram[1]:18 *C 75.440 58.435 +*N mux_tree_tapbuf_size2_15_sram[1]:19 *C 75.485 58.480 +*N mux_tree_tapbuf_size2_15_sram[1]:20 *C 76.160 58.480 +*N mux_tree_tapbuf_size2_15_sram[1]:21 *C 76.205 58.525 +*N mux_tree_tapbuf_size2_15_sram[1]:22 *C 76.205 58.950 +*N mux_tree_tapbuf_size2_15_sram[1]:23 *C 76.243 58.885 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_left_track_5\/mux_l2_in_0_:S 1e-06 +2 mem_left_track_5\/FTB_22__37:A 1e-06 +3 mux_tree_tapbuf_size2_15_sram[1]:3 5.448369e-05 +4 mux_tree_tapbuf_size2_15_sram[1]:4 0.001093968 +5 mux_tree_tapbuf_size2_15_sram[1]:5 0.001067212 +6 mux_tree_tapbuf_size2_15_sram[1]:6 0.0001310272 +7 mux_tree_tapbuf_size2_15_sram[1]:7 0.0001310272 +8 mux_tree_tapbuf_size2_15_sram[1]:8 7.957726e-05 +9 mux_tree_tapbuf_size2_15_sram[1]:9 0.000136852 +10 mux_tree_tapbuf_size2_15_sram[1]:10 0.0001631447 +11 mux_tree_tapbuf_size2_15_sram[1]:11 0.0001304881 +12 mux_tree_tapbuf_size2_15_sram[1]:12 0.0001041955 +13 mux_tree_tapbuf_size2_15_sram[1]:13 0.0009748821 +14 mux_tree_tapbuf_size2_15_sram[1]:14 0.0009748821 +15 mux_tree_tapbuf_size2_15_sram[1]:15 0.0009820194 +16 mux_tree_tapbuf_size2_15_sram[1]:16 0.0009820194 +17 mux_tree_tapbuf_size2_15_sram[1]:17 0.0002627588 +18 mux_tree_tapbuf_size2_15_sram[1]:18 0.0002627588 +19 mux_tree_tapbuf_size2_15_sram[1]:19 6.114295e-05 +20 mux_tree_tapbuf_size2_15_sram[1]:20 6.114295e-05 +21 mux_tree_tapbuf_size2_15_sram[1]:21 6.608139e-05 +22 mux_tree_tapbuf_size2_15_sram[1]:22 6.608139e-05 +23 mux_tree_tapbuf_size2_15_sram[1]:23 7.957726e-05 +24 mux_tree_tapbuf_size2_15_sram[1]:14 chany_bottom_in[10]:13 2.758617e-05 +25 mux_tree_tapbuf_size2_15_sram[1]:14 chany_bottom_in[10]:14 0.000305486 +26 mux_tree_tapbuf_size2_15_sram[1]:13 chany_bottom_in[10]:14 2.758617e-05 +27 mux_tree_tapbuf_size2_15_sram[1]:13 chany_bottom_in[10]:15 0.000305486 +28 mux_tree_tapbuf_size2_15_sram[1]:14 mux_tree_tapbuf_size2_12_sram[0]:16 0.0001673648 +29 mux_tree_tapbuf_size2_15_sram[1]:13 mux_tree_tapbuf_size2_12_sram[0]:15 0.0001673648 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_15_sram[1]:23 0.152 +1 mux_tree_tapbuf_size2_15_sram[1]:23 mux_tree_tapbuf_size2_15_sram[1]:22 0.0045 +2 mux_tree_tapbuf_size2_15_sram[1]:23 mux_tree_tapbuf_size2_15_sram[1]:8 0.0008861608 +3 mux_tree_tapbuf_size2_15_sram[1]:22 mux_tree_tapbuf_size2_15_sram[1]:21 0.0003794643 +4 mux_tree_tapbuf_size2_15_sram[1]:20 mux_tree_tapbuf_size2_15_sram[1]:19 0.0006026786 +5 mux_tree_tapbuf_size2_15_sram[1]:21 mux_tree_tapbuf_size2_15_sram[1]:20 0.0045 +6 mux_tree_tapbuf_size2_15_sram[1]:19 mux_tree_tapbuf_size2_15_sram[1]:18 0.0045 +7 mux_tree_tapbuf_size2_15_sram[1]:18 mux_tree_tapbuf_size2_15_sram[1]:17 0.004158482 +8 mux_tree_tapbuf_size2_15_sram[1]:17 mux_tree_tapbuf_size2_15_sram[1]:16 0.00341 +9 mux_tree_tapbuf_size2_15_sram[1]:16 mux_tree_tapbuf_size2_15_sram[1]:15 0.002231717 +10 mux_tree_tapbuf_size2_15_sram[1]:14 mux_tree_tapbuf_size2_15_sram[1]:13 0.02267634 +11 mux_tree_tapbuf_size2_15_sram[1]:15 mux_tree_tapbuf_size2_15_sram[1]:14 0.00341 +12 mux_tree_tapbuf_size2_15_sram[1]:12 mux_tree_tapbuf_size2_15_sram[1]:11 0.001191964 +13 mux_tree_tapbuf_size2_15_sram[1]:13 mux_tree_tapbuf_size2_15_sram[1]:12 0.0045 +14 mux_tree_tapbuf_size2_15_sram[1]:9 mux_left_track_5\/mux_l2_in_0_:S 0.152 +15 mux_tree_tapbuf_size2_15_sram[1]:8 mux_tree_tapbuf_size2_15_sram[1]:7 0.0045 +16 mux_tree_tapbuf_size2_15_sram[1]:7 mux_tree_tapbuf_size2_15_sram[1]:6 0.001741072 +17 mux_tree_tapbuf_size2_15_sram[1]:5 mux_tree_tapbuf_size2_15_sram[1]:4 0.01638839 +18 mux_tree_tapbuf_size2_15_sram[1]:6 mux_tree_tapbuf_size2_15_sram[1]:5 0.0045 +19 mux_tree_tapbuf_size2_15_sram[1]:3 mem_left_track_5\/FTB_22__37:A 0.152 +20 mux_tree_tapbuf_size2_15_sram[1]:10 mux_tree_tapbuf_size2_15_sram[1]:9 0.001520089 +21 mux_tree_tapbuf_size2_15_sram[1]:11 mux_tree_tapbuf_size2_15_sram[1]:10 0.0003035715 +22 mux_tree_tapbuf_size2_15_sram[1]:4 mux_tree_tapbuf_size2_15_sram[1]:3 0.0003035714 + +*END + +*D_NET mux_tree_tapbuf_size2_3_sram[1] 0.003910583 //LENGTH 33.330 LUMPCC 0.0006314812 DR + +*CONN +*I mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 59.185 55.420 +*I mux_bottom_track_17\/mux_l2_in_0_:S I *L 0.00357 *C 37.160 47.260 +*I mem_bottom_track_17\/FTB_10__25:A I *L 0.001746 *C 61.180 47.600 +*N mux_tree_tapbuf_size2_3_sram[1]:3 *C 61.143 47.600 +*N mux_tree_tapbuf_size2_3_sram[1]:4 *C 37.160 47.260 +*N mux_tree_tapbuf_size2_3_sram[1]:5 *C 55.660 47.260 +*N mux_tree_tapbuf_size2_3_sram[1]:6 *C 55.660 47.600 +*N mux_tree_tapbuf_size2_3_sram[1]:7 *C 59.340 47.600 +*N mux_tree_tapbuf_size2_3_sram[1]:8 *C 59.340 47.645 +*N mux_tree_tapbuf_size2_3_sram[1]:9 *C 59.340 55.375 +*N mux_tree_tapbuf_size2_3_sram[1]:10 *C 59.340 55.420 +*N mux_tree_tapbuf_size2_3_sram[1]:11 *C 59.185 55.420 + +*CAP +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_17\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_17\/FTB_10__25:A 1e-06 +3 mux_tree_tapbuf_size2_3_sram[1]:3 8.681894e-05 +4 mux_tree_tapbuf_size2_3_sram[1]:4 0.000881875 +5 mux_tree_tapbuf_size2_3_sram[1]:5 0.0008711072 +6 mux_tree_tapbuf_size2_3_sram[1]:6 0.0002181766 +7 mux_tree_tapbuf_size2_3_sram[1]:7 0.0003144721 +8 mux_tree_tapbuf_size2_3_sram[1]:8 0.0004031885 +9 mux_tree_tapbuf_size2_3_sram[1]:9 0.0004031885 +10 mux_tree_tapbuf_size2_3_sram[1]:10 4.995568e-05 +11 mux_tree_tapbuf_size2_3_sram[1]:11 4.731896e-05 +12 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 2.931656e-05 +13 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 3.441413e-05 +14 mux_tree_tapbuf_size2_3_sram[1]:3 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:7 2.931656e-05 +15 mux_tree_tapbuf_size2_3_sram[1]:6 mux_tree_tapbuf_size2_mem_3_ccff_tail[0]:6 3.441413e-05 +16 mux_tree_tapbuf_size2_3_sram[1]:4 optlc_net_108:20 5.654363e-05 +17 mux_tree_tapbuf_size2_3_sram[1]:4 optlc_net_108:11 0.0001954663 +18 mux_tree_tapbuf_size2_3_sram[1]:5 optlc_net_108:20 0.0001954663 +19 mux_tree_tapbuf_size2_3_sram[1]:5 optlc_net_108:21 5.654363e-05 + +*RES +0 mem_bottom_track_17\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_3_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_3_sram[1]:4 mux_bottom_track_17\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:6 0.003285714 +3 mux_tree_tapbuf_size2_3_sram[1]:7 mux_tree_tapbuf_size2_3_sram[1]:3 0.001609375 +4 mux_tree_tapbuf_size2_3_sram[1]:8 mux_tree_tapbuf_size2_3_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size2_3_sram[1]:10 mux_tree_tapbuf_size2_3_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size2_3_sram[1]:9 mux_tree_tapbuf_size2_3_sram[1]:8 0.006901786 +7 mux_tree_tapbuf_size2_3_sram[1]:11 mux_tree_tapbuf_size2_3_sram[1]:10 8.423914e-05 +8 mux_tree_tapbuf_size2_3_sram[1]:3 mem_bottom_track_17\/FTB_10__25:A 0.152 +9 mux_tree_tapbuf_size2_3_sram[1]:5 mux_tree_tapbuf_size2_3_sram[1]:4 0.01651786 +10 mux_tree_tapbuf_size2_3_sram[1]:6 mux_tree_tapbuf_size2_3_sram[1]:5 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[1] 0.002024625 //LENGTH 16.260 LUMPCC 8.967763e-05 DR + +*CONN +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 19.405 60.520 +*I mem_bottom_track_27\/FTB_14__29:A I *L 0.001746 *C 14.720 58.480 +*I mux_bottom_track_27\/mux_l2_in_0_:S I *L 0.00357 *C 17.820 52.360 +*N mux_tree_tapbuf_size2_7_sram[1]:3 *C 17.783 52.360 +*N mux_tree_tapbuf_size2_7_sram[1]:4 *C 15.685 52.360 +*N mux_tree_tapbuf_size2_7_sram[1]:5 *C 15.640 52.405 +*N mux_tree_tapbuf_size2_7_sram[1]:6 *C 14.758 58.480 +*N mux_tree_tapbuf_size2_7_sram[1]:7 *C 15.595 58.480 +*N mux_tree_tapbuf_size2_7_sram[1]:8 *C 15.640 58.480 +*N mux_tree_tapbuf_size2_7_sram[1]:9 *C 15.640 60.475 +*N mux_tree_tapbuf_size2_7_sram[1]:10 *C 15.685 60.520 +*N mux_tree_tapbuf_size2_7_sram[1]:11 *C 19.367 60.520 + +*CAP +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_27\/FTB_14__29:A 1e-06 +2 mux_bottom_track_27\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_7_sram[1]:3 0.0001446035 +4 mux_tree_tapbuf_size2_7_sram[1]:4 0.0001446035 +5 mux_tree_tapbuf_size2_7_sram[1]:5 0.0003451816 +6 mux_tree_tapbuf_size2_7_sram[1]:6 7.262095e-05 +7 mux_tree_tapbuf_size2_7_sram[1]:7 7.262095e-05 +8 mux_tree_tapbuf_size2_7_sram[1]:8 0.0004987119 +9 mux_tree_tapbuf_size2_7_sram[1]:9 0.0001207251 +10 mux_tree_tapbuf_size2_7_sram[1]:10 0.0002664401 +11 mux_tree_tapbuf_size2_7_sram[1]:11 0.0002664401 +12 mux_tree_tapbuf_size2_7_sram[1]:3 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.060302e-05 +13 mux_tree_tapbuf_size2_7_sram[1]:4 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:3 4.060302e-05 +14 mux_tree_tapbuf_size2_7_sram[1]:5 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.235795e-06 +15 mux_tree_tapbuf_size2_7_sram[1]:8 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.235795e-06 + +*RES +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_7_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_7_sram[1]:3 mux_bottom_track_27\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_7_sram[1]:4 mux_tree_tapbuf_size2_7_sram[1]:3 0.001872768 +3 mux_tree_tapbuf_size2_7_sram[1]:5 mux_tree_tapbuf_size2_7_sram[1]:4 0.0045 +4 mux_tree_tapbuf_size2_7_sram[1]:10 mux_tree_tapbuf_size2_7_sram[1]:9 0.0045 +5 mux_tree_tapbuf_size2_7_sram[1]:9 mux_tree_tapbuf_size2_7_sram[1]:8 0.00178125 +6 mux_tree_tapbuf_size2_7_sram[1]:11 mux_tree_tapbuf_size2_7_sram[1]:10 0.003287947 +7 mux_tree_tapbuf_size2_7_sram[1]:7 mux_tree_tapbuf_size2_7_sram[1]:6 0.0007477679 +8 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:7 0.0045 +9 mux_tree_tapbuf_size2_7_sram[1]:8 mux_tree_tapbuf_size2_7_sram[1]:5 0.005424107 +10 mux_tree_tapbuf_size2_7_sram[1]:6 mem_bottom_track_27\/FTB_14__29:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_11_ccff_tail[0] 0.003336242 //LENGTH 28.350 LUMPCC 0.0009952905 DR + +*CONN +*I mem_bottom_track_35\/FTB_18__33:X O *L 0 *C 58.195 14.960 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 54.915 39.100 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 *C 54.953 39.100 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 *C 55.615 39.100 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 *C 55.660 39.055 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 *C 55.660 15.005 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 *C 55.705 14.960 +*N mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 *C 58.158 14.960 + +*CAP +0 mem_bottom_track_35\/FTB_18__33:X 1e-06 +1 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 6.688865e-05 +3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 6.688865e-05 +4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.0009941851 +5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.0009941851 +6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 0.0001084021 +7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 0.0001084021 +8 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 0.0001025664 +9 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0001025664 +10 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 7.200911e-06 +11 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 7.200911e-06 +12 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000230502 +13 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000230502 +14 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.000157376 +15 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.000157376 + +*RES +0 mem_bottom_track_35\/FTB_18__33:X mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 0.002189732 +2 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.02147322 +4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:2 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_4_ccff_tail[0] 0.0009225436 //LENGTH 5.320 LUMPCC 0.0004987792 DR + +*CONN +*I mem_bottom_track_19\/FTB_11__26:X O *L 0 *C 53.135 18.360 +*I mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 53.075 22.780 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 *C 53.075 22.780 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 *C 52.900 22.780 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 *C 52.900 22.735 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 *C 52.900 18.405 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 *C 52.900 18.360 +*N mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 *C 53.135 18.360 + +*CAP +0 mem_bottom_track_19\/FTB_11__26:X 1e-06 +1 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 4.749928e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 5.201415e-05 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0001010147 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0001010147 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 6.150387e-05 +7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 5.871776e-05 +8 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_11_sram[1]:7 0.0001246948 +9 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_11_sram[1]:5 0.0001246948 +10 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001246948 +11 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0001246948 + +*RES +0 mem_bottom_track_19\/FTB_11__26:X mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 mem_bottom_track_21\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:2 9.510871e-05 +3 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.003866071 +6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:6 0.0001277174 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[0] 0.005668893 //LENGTH 42.395 LUMPCC 0.0005262446 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 14.045 38.760 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 8.455 31.620 +*I mux_bottom_track_3\/mux_l1_in_0_:S I *L 0.00357 *C 23.100 30.600 +*I mux_bottom_track_3\/mux_l1_in_1_:S I *L 0.00357 *C 32.760 25.160 +*N mux_tree_tapbuf_size5_0_sram[0]:4 *C 32.797 25.160 +*N mux_tree_tapbuf_size5_0_sram[0]:5 *C 33.120 25.160 +*N mux_tree_tapbuf_size5_0_sram[0]:6 *C 33.120 25.500 +*N mux_tree_tapbuf_size5_0_sram[0]:7 *C 31.325 25.500 +*N mux_tree_tapbuf_size5_0_sram[0]:8 *C 31.280 25.545 +*N mux_tree_tapbuf_size5_0_sram[0]:9 *C 31.280 30.555 +*N mux_tree_tapbuf_size5_0_sram[0]:10 *C 31.235 30.600 +*N mux_tree_tapbuf_size5_0_sram[0]:11 *C 23.138 30.600 +*N mux_tree_tapbuf_size5_0_sram[0]:12 *C 23.000 30.645 +*N mux_tree_tapbuf_size5_0_sram[0]:13 *C 23.000 31.915 +*N mux_tree_tapbuf_size5_0_sram[0]:14 *C 22.955 31.960 +*N mux_tree_tapbuf_size5_0_sram[0]:15 *C 8.492 31.620 +*N mux_tree_tapbuf_size5_0_sram[0]:16 *C 9.200 31.620 +*N mux_tree_tapbuf_size5_0_sram[0]:17 *C 9.200 31.960 +*N mux_tree_tapbuf_size5_0_sram[0]:18 *C 14.720 31.960 +*N mux_tree_tapbuf_size5_0_sram[0]:19 *C 14.720 32.005 +*N mux_tree_tapbuf_size5_0_sram[0]:20 *C 14.720 38.715 +*N mux_tree_tapbuf_size5_0_sram[0]:21 *C 14.675 38.760 +*N mux_tree_tapbuf_size5_0_sram[0]:22 *C 14.083 38.760 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:S 1e-06 +3 mux_bottom_track_3\/mux_l1_in_1_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[0]:4 3.268351e-05 +5 mux_tree_tapbuf_size5_0_sram[0]:5 5.743419e-05 +6 mux_tree_tapbuf_size5_0_sram[0]:6 0.0001562183 +7 mux_tree_tapbuf_size5_0_sram[0]:7 0.0001314677 +8 mux_tree_tapbuf_size5_0_sram[0]:8 0.0003006843 +9 mux_tree_tapbuf_size5_0_sram[0]:9 0.0003006843 +10 mux_tree_tapbuf_size5_0_sram[0]:10 0.0006147203 +11 mux_tree_tapbuf_size5_0_sram[0]:11 0.0006147203 +12 mux_tree_tapbuf_size5_0_sram[0]:12 9.860784e-05 +13 mux_tree_tapbuf_size5_0_sram[0]:13 9.860784e-05 +14 mux_tree_tapbuf_size5_0_sram[0]:14 0.0005538333 +15 mux_tree_tapbuf_size5_0_sram[0]:15 6.422745e-05 +16 mux_tree_tapbuf_size5_0_sram[0]:16 8.723354e-05 +17 mux_tree_tapbuf_size5_0_sram[0]:17 0.0003884026 +18 mux_tree_tapbuf_size5_0_sram[0]:18 0.0009523241 +19 mux_tree_tapbuf_size5_0_sram[0]:19 0.0002939652 +20 mux_tree_tapbuf_size5_0_sram[0]:20 0.0002939652 +21 mux_tree_tapbuf_size5_0_sram[0]:21 4.943384e-05 +22 mux_tree_tapbuf_size5_0_sram[0]:22 4.943384e-05 +23 mux_tree_tapbuf_size5_0_sram[0]:22 mux_tree_tapbuf_size5_0_sram[2]:4 1.385133e-05 +24 mux_tree_tapbuf_size5_0_sram[0]:21 mux_tree_tapbuf_size5_0_sram[2]:3 1.385133e-05 +25 mux_tree_tapbuf_size5_0_sram[0]:20 mux_tree_tapbuf_size5_0_sram[2]:5 5.956148e-05 +26 mux_tree_tapbuf_size5_0_sram[0]:20 mux_tree_tapbuf_size5_0_sram[2]:9 7.435404e-05 +27 mux_tree_tapbuf_size5_0_sram[0]:19 mux_tree_tapbuf_size5_0_sram[2]:8 7.435404e-05 +28 mux_tree_tapbuf_size5_0_sram[0]:19 mux_tree_tapbuf_size5_0_sram[2]:9 5.956148e-05 +29 mux_tree_tapbuf_size5_0_sram[0]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.383896e-05 +30 mux_tree_tapbuf_size5_0_sram[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 5.939749e-05 +31 mux_tree_tapbuf_size5_0_sram[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:11 1.113911e-06 +32 mux_tree_tapbuf_size5_0_sram[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.939749e-05 +33 mux_tree_tapbuf_size5_0_sram[0]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.383896e-05 +34 mux_tree_tapbuf_size5_0_sram[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.005085e-06 +35 mux_tree_tapbuf_size5_0_sram[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.005085e-06 +36 mux_tree_tapbuf_size5_0_sram[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:12 1.113911e-06 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size5_0_sram[0]:22 0.152 +1 mux_tree_tapbuf_size5_0_sram[0]:15 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size5_0_sram[0]:22 mux_tree_tapbuf_size5_0_sram[0]:21 0.0005290179 +3 mux_tree_tapbuf_size5_0_sram[0]:21 mux_tree_tapbuf_size5_0_sram[0]:20 0.0045 +4 mux_tree_tapbuf_size5_0_sram[0]:20 mux_tree_tapbuf_size5_0_sram[0]:19 0.005991071 +5 mux_tree_tapbuf_size5_0_sram[0]:18 mux_tree_tapbuf_size5_0_sram[0]:17 0.004928571 +6 mux_tree_tapbuf_size5_0_sram[0]:18 mux_tree_tapbuf_size5_0_sram[0]:14 0.007352679 +7 mux_tree_tapbuf_size5_0_sram[0]:19 mux_tree_tapbuf_size5_0_sram[0]:18 0.0045 +8 mux_tree_tapbuf_size5_0_sram[0]:10 mux_tree_tapbuf_size5_0_sram[0]:9 0.0045 +9 mux_tree_tapbuf_size5_0_sram[0]:9 mux_tree_tapbuf_size5_0_sram[0]:8 0.004473215 +10 mux_tree_tapbuf_size5_0_sram[0]:7 mux_tree_tapbuf_size5_0_sram[0]:6 0.001602679 +11 mux_tree_tapbuf_size5_0_sram[0]:8 mux_tree_tapbuf_size5_0_sram[0]:7 0.0045 +12 mux_tree_tapbuf_size5_0_sram[0]:4 mux_bottom_track_3\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size5_0_sram[0]:11 mux_bottom_track_3\/mux_l1_in_0_:S 0.152 +14 mux_tree_tapbuf_size5_0_sram[0]:11 mux_tree_tapbuf_size5_0_sram[0]:10 0.007229911 +15 mux_tree_tapbuf_size5_0_sram[0]:14 mux_tree_tapbuf_size5_0_sram[0]:13 0.0045 +16 mux_tree_tapbuf_size5_0_sram[0]:13 mux_tree_tapbuf_size5_0_sram[0]:12 0.001133929 +17 mux_tree_tapbuf_size5_0_sram[0]:12 mux_tree_tapbuf_size5_0_sram[0]:11 0.0045 +18 mux_tree_tapbuf_size5_0_sram[0]:16 mux_tree_tapbuf_size5_0_sram[0]:15 0.0006316965 +19 mux_tree_tapbuf_size5_0_sram[0]:17 mux_tree_tapbuf_size5_0_sram[0]:16 0.0003035714 +20 mux_tree_tapbuf_size5_0_sram[0]:6 mux_tree_tapbuf_size5_0_sram[0]:5 0.0003035715 +21 mux_tree_tapbuf_size5_0_sram[0]:5 mux_tree_tapbuf_size5_0_sram[0]:4 0.0002879465 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_1_ccff_tail[0] 0.0006201158 //LENGTH 5.130 LUMPCC 9.243827e-05 DR + +*CONN +*I mem_bottom_track_5\/FTB_2__17:X O *L 0 *C 37.025 25.840 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 38.355 22.780 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 *C 38.355 22.780 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 *C 38.180 22.780 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 *C 38.180 22.825 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 *C 38.180 25.795 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 *C 38.135 25.840 +*N mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 *C 37.062 25.840 + +*CAP +0 mem_bottom_track_5\/FTB_2__17:X 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 5.091302e-05 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 5.548253e-05 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.0001293238 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0001293238 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 8.031722e-05 +7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 8.031722e-05 +8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 4.621913e-05 +9 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 4.621913e-05 + +*RES +0 mem_bottom_track_5\/FTB_2__17:X mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 0.0009575893 +2 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 9.51087e-05 +5 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:2 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0] 0.001343251 //LENGTH 9.855 LUMPCC 0.0002691459 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_1_:X O *L 0 *C 18.685 44.200 +*I mux_bottom_track_1\/mux_l3_in_0_:A0 I *L 0.001631 *C 22.700 39.100 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 22.663 39.100 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 18.905 39.100 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 18.860 39.145 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 18.860 44.155 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 18.860 44.200 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 18.685 44.200 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0002490456 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0002490456 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.0002247096 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0002247096 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.33289e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 6.126607e-05 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 prog_clk[0]:189 2.54239e-08 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:188 2.54239e-08 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:190 5.375418e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 prog_clk[0]:194 8.079335e-05 +12 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:194 5.375418e-05 +13 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 prog_clk[0]:197 8.079335e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 9.51087e-05 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.004473215 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.003354911 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A0 0.152 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0] 0.00428629 //LENGTH 37.775 LUMPCC 0.0004921104 DR + +*CONN +*I mux_bottom_track_5\/mux_l3_in_0_:X O *L 0 *C 36.165 30.600 +*I mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 46.205 4.275 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 *C 46.168 4.370 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 *C 44.205 4.420 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 *C 44.160 4.465 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 *C 44.160 22.383 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 *C 44.153 22.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 *C 37.267 22.440 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 *C 37.260 22.498 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 *C 37.260 30.555 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 *C 37.215 30.600 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 *C 36.203 30.600 + +*CAP +0 mux_bottom_track_5\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 9.079284e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 9.079284e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.0008360543 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.0008360543 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.0004676831 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.0004676831 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.0004077191 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0004077191 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 9.384e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 9.384e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 chany_bottom_in[15]:15 4.482516e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 chany_bottom_in[15]:14 4.482516e-05 +14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 chany_bottom_in[15]:13 8.59623e-05 +15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 chany_bottom_in[15]:12 8.59623e-05 +16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:4 4.621913e-05 +17 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_tree_tapbuf_size6_mem_1_ccff_tail[0]:5 4.621913e-05 +18 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.904863e-05 +19 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.904863e-05 + +*RES +0 mux_bottom_track_5\/mux_l3_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 mux_bottom_track_5\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:2 0.001752232 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:4 0.01599777 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:5 0.00341 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.00341 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.00107865 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 0.0045 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:8 0.007194197 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_5_X[0]:10 0.0009040179 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009330596 //LENGTH 7.325 LUMPCC 8.804171e-05 DR + +*CONN +*I mux_bottom_track_9\/mux_l1_in_0_:X O *L 0 *C 40.765 14.280 +*I mux_bottom_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 45.180 12.580 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 45.143 12.580 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 44.620 12.580 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 44.620 12.920 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 42.365 12.920 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 42.320 12.965 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 42.320 14.235 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 42.275 14.280 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 *C 40.803 14.280 + +*CAP +0 mux_bottom_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 4.723119e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.251761e-05 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001869074 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.000161621 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.16785e-05 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.16785e-05 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001256919 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.0001256919 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 chany_bottom_in[15]:13 4.402085e-05 +11 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 chany_bottom_in[15]:12 4.402085e-05 + +*RES +0 mux_bottom_track_9\/mux_l1_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_9\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002013393 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.001133929 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.001314732 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004665179 + +*END + +*D_NET mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0] 0.009562805 //LENGTH 86.900 LUMPCC 0.001273436 DR + +*CONN +*I mux_bottom_track_13\/mux_l2_in_0_:X O *L 0 *C 40.305 63.920 +*I mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 68.780 6.610 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 68.780 6.610 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 67.205 6.800 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 67.160 6.845 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 67.160 53.335 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 67.115 53.380 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 40.525 53.380 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 40.480 53.425 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 40.480 63.875 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 40.480 63.920 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 40.305 63.920 + +*CAP +0 mux_bottom_track_13\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001475877 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001144275 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.00197533 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00197533 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001403897 +7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001403897 +8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0005720402 +9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0005720402 +10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 5.973713e-05 +11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 6.308318e-05 +12 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:77 4.690485e-05 +13 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 prog_clk[0]:82 2.200487e-06 +14 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:264 3.166691e-05 +15 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 prog_clk[0]:271 3.98344e-05 +16 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:78 4.690485e-05 +17 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 prog_clk[0]:85 2.200487e-06 +18 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:263 3.166691e-05 +19 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 prog_clk[0]:270 3.98344e-05 +20 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:264 9.638077e-05 +21 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:271 0.0001150262 +22 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:279 6.210236e-06 +23 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:281 7.960399e-06 +24 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:283 9.122254e-05 +25 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:286 3.268994e-05 +26 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:290 8.192281e-08 +27 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:293 8.640926e-07 +28 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:270 9.638077e-05 +29 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:276 7.960399e-06 +30 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:280 6.210236e-06 +31 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:283 0.0001150262 +32 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:286 9.122254e-05 +33 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:287 3.268994e-05 +34 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:293 8.192281e-08 +35 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:294 8.640926e-07 +36 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001656752 +37 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001656752 + +*RES +0 mux_bottom_track_13\/mux_l2_in_0_:X mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 9.51087e-05 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.009330357 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.02374107 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.04150893 +8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00140625 +9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_13\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0] 0.006728569 //LENGTH 61.015 LUMPCC 0.0007301022 DR + +*CONN +*I mux_bottom_track_31\/mux_l2_in_0_:X O *L 0 *C 32.485 49.980 +*I mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 47.760 6.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 47.797 6.660 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 48.255 6.700 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 48.300 6.845 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 48.300 41.775 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 48.255 41.820 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 39.145 41.820 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 39.100 41.865 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 39.100 49.935 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 39.055 49.980 +*N mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 32.523 49.980 + +*CAP +0 mux_bottom_track_31\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.325431e-05 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.325431e-05 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001533492 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001533492 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005210271 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005210271 +8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0004737618 +9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0004737618 +10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0004166977 +11 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0004166977 +12 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_4_sram[1]:8 0.0001033839 +13 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_4_sram[1]:9 7.319375e-05 +14 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_4_sram[1]:5 0.0001033839 +15 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_4_sram[1]:8 7.319375e-05 +16 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_108:18 2.334331e-05 +17 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 optlc_net_108:19 0.0001651301 +18 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_108:14 2.334331e-05 +19 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 optlc_net_108:18 0.0001651301 + +*RES +0 mux_bottom_track_31\/mux_l2_in_0_:X mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.152 +1 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.005832589 +2 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.007205357 +4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.008133929 +5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0045 +6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +7 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0311875 +8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0004084822 +9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_31\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET optlc_net_109 0.009367608 //LENGTH 51.590 LUMPCC 0.004386015 DR + +*CONN +*I optlc_108:HI O *L 0 *C 34.500 42.160 +*I mux_bottom_track_5\/mux_l2_in_1_:A0 I *L 0.001631 *C 26.855 38.760 +*I mux_bottom_track_3\/mux_l2_in_1_:A0 I *L 0.001631 *C 4.775 39.100 +*I mux_bottom_track_1\/mux_l2_in_1_:A0 I *L 0.001631 *C 16.735 44.200 +*N optlc_net_109:4 *C 16.698 44.200 +*N optlc_net_109:5 *C 12.925 44.200 +*N optlc_net_109:6 *C 12.880 44.155 +*N optlc_net_109:7 *C 4.775 39.100 +*N optlc_net_109:8 *C 5.060 39.100 +*N optlc_net_109:9 *C 5.060 39.145 +*N optlc_net_109:10 *C 5.060 41.435 +*N optlc_net_109:11 *C 5.105 41.480 +*N optlc_net_109:12 *C 12.835 41.480 +*N optlc_net_109:13 *C 12.880 41.480 +*N optlc_net_109:14 *C 12.880 38.138 +*N optlc_net_109:15 *C 12.888 38.080 +*N optlc_net_109:16 *C 26.855 38.760 +*N optlc_net_109:17 *C 26.680 38.760 +*N optlc_net_109:18 *C 26.680 38.715 +*N optlc_net_109:19 *C 26.680 38.138 +*N optlc_net_109:20 *C 26.680 38.080 +*N optlc_net_109:21 *C 35.413 38.080 +*N optlc_net_109:22 *C 35.420 38.138 +*N optlc_net_109:23 *C 35.420 42.115 +*N optlc_net_109:24 *C 35.375 42.160 +*N optlc_net_109:25 *C 34.538 42.160 + +*CAP +0 optlc_108:HI 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A0 1e-06 +2 mux_bottom_track_3\/mux_l2_in_1_:A0 1e-06 +3 mux_bottom_track_1\/mux_l2_in_1_:A0 1e-06 +4 optlc_net_109:4 0.0002846435 +5 optlc_net_109:5 0.0002846435 +6 optlc_net_109:6 0.0001810283 +7 optlc_net_109:7 5.445853e-05 +8 optlc_net_109:8 6.024867e-05 +9 optlc_net_109:9 0.0001317356 +10 optlc_net_109:10 0.0001317356 +11 optlc_net_109:11 0.0005093206 +12 optlc_net_109:12 0.0005093206 +13 optlc_net_109:13 0.0004435735 +14 optlc_net_109:14 0.0002301895 +15 optlc_net_109:15 0.0002276796 +16 optlc_net_109:16 5.110115e-05 +17 optlc_net_109:17 5.554757e-05 +18 optlc_net_109:18 7.38243e-05 +19 optlc_net_109:19 7.38243e-05 +20 optlc_net_109:20 0.0005773528 +21 optlc_net_109:21 0.0003496732 +22 optlc_net_109:22 0.0002860483 +23 optlc_net_109:23 0.0002860483 +24 optlc_net_109:24 8.779726e-05 +25 optlc_net_109:25 8.779726e-05 +26 optlc_net_109:15 chanx_left_in[0]:12 0.0007827498 +27 optlc_net_109:21 chanx_left_in[0]:11 0.0004849847 +28 optlc_net_109:10 chanx_left_in[0] 9.326922e-06 +29 optlc_net_109:9 chanx_left_in[0]:12 9.326922e-06 +30 optlc_net_109:20 chanx_left_in[0]:11 0.0007827498 +31 optlc_net_109:20 chanx_left_in[0]:12 0.0004849847 +32 optlc_net_109:15 chanx_left_in[18]:6 0.0007827498 +33 optlc_net_109:21 chanx_left_in[18]:5 0.0001331963 +34 optlc_net_109:20 chanx_left_in[18]:5 0.0007827498 +35 optlc_net_109:20 chanx_left_in[18]:6 0.0001331963 + +*RES +0 optlc_108:HI optlc_net_109:25 0.152 +1 optlc_net_109:14 optlc_net_109:13 0.002984375 +2 optlc_net_109:15 optlc_net_109:14 0.00341 +3 optlc_net_109:22 optlc_net_109:21 0.00341 +4 optlc_net_109:21 optlc_net_109:20 0.001368092 +5 optlc_net_109:24 optlc_net_109:23 0.0045 +6 optlc_net_109:23 optlc_net_109:22 0.003551339 +7 optlc_net_109:25 optlc_net_109:24 0.0007477679 +8 optlc_net_109:12 optlc_net_109:11 0.006901786 +9 optlc_net_109:13 optlc_net_109:12 0.0045 +10 optlc_net_109:13 optlc_net_109:6 0.002388393 +11 optlc_net_109:11 optlc_net_109:10 0.0045 +12 optlc_net_109:10 optlc_net_109:9 0.002044643 +13 optlc_net_109:8 optlc_net_109:7 0.0001548913 +14 optlc_net_109:9 optlc_net_109:8 0.0045 +15 optlc_net_109:7 mux_bottom_track_3\/mux_l2_in_1_:A0 0.152 +16 optlc_net_109:19 optlc_net_109:18 0.000515625 +17 optlc_net_109:20 optlc_net_109:19 0.00341 +18 optlc_net_109:20 optlc_net_109:15 0.002160825 +19 optlc_net_109:17 optlc_net_109:16 9.510869e-05 +20 optlc_net_109:18 optlc_net_109:17 0.0045 +21 optlc_net_109:16 mux_bottom_track_5\/mux_l2_in_1_:A0 0.152 +22 optlc_net_109:5 optlc_net_109:4 0.003368304 +23 optlc_net_109:6 optlc_net_109:5 0.0045 +24 optlc_net_109:4 mux_bottom_track_1\/mux_l2_in_1_:A0 0.152 + +*END + +*D_NET mux_bottom_track_9/BUF_net_41 0.0008036047 //LENGTH 7.990 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/BUFT_RR_41:X O *L 0 *C 89.240 8.840 +*I mux_bottom_track_9\/BUFT_P_83:A I *L 0.001767 *C 91.540 4.080 +*N mux_bottom_track_9/BUF_net_41:2 *C 91.502 4.080 +*N mux_bottom_track_9/BUF_net_41:3 *C 90.665 4.080 +*N mux_bottom_track_9/BUF_net_41:4 *C 90.620 4.125 +*N mux_bottom_track_9/BUF_net_41:5 *C 90.620 8.795 +*N mux_bottom_track_9/BUF_net_41:6 *C 90.575 8.840 +*N mux_bottom_track_9/BUF_net_41:7 *C 89.278 8.840 + +*CAP +0 mux_bottom_track_9\/BUFT_RR_41:X 1e-06 +1 mux_bottom_track_9\/BUFT_P_83:A 1e-06 +2 mux_bottom_track_9/BUF_net_41:2 6.209759e-05 +3 mux_bottom_track_9/BUF_net_41:3 6.209759e-05 +4 mux_bottom_track_9/BUF_net_41:4 0.0002317906 +5 mux_bottom_track_9/BUF_net_41:5 0.0002317906 +6 mux_bottom_track_9/BUF_net_41:6 0.0001069141 +7 mux_bottom_track_9/BUF_net_41:7 0.0001069141 + +*RES +0 mux_bottom_track_9\/BUFT_RR_41:X mux_bottom_track_9/BUF_net_41:7 0.152 +1 mux_bottom_track_9/BUF_net_41:2 mux_bottom_track_9\/BUFT_P_83:A 0.152 +2 mux_bottom_track_9/BUF_net_41:3 mux_bottom_track_9/BUF_net_41:2 0.0007477679 +3 mux_bottom_track_9/BUF_net_41:4 mux_bottom_track_9/BUF_net_41:3 0.0045 +4 mux_bottom_track_9/BUF_net_41:6 mux_bottom_track_9/BUF_net_41:5 0.0045 +5 mux_bottom_track_9/BUF_net_41:5 mux_bottom_track_9/BUF_net_41:4 0.004169643 +6 mux_bottom_track_9/BUF_net_41:7 mux_bottom_track_9/BUF_net_41:6 0.001158482 + +*END + +*D_NET ropt_net_137 0.001089718 //LENGTH 8.635 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_740:X O *L 0 *C 7.095 76.840 +*I ropt_mt_inst_752:A I *L 0.001767 *C 3.220 74.800 +*N ropt_net_137:2 *C 3.258 74.800 +*N ropt_net_137:3 *C 4.555 74.800 +*N ropt_net_137:4 *C 4.600 74.755 +*N ropt_net_137:5 *C 4.600 74.165 +*N ropt_net_137:6 *C 4.645 74.120 +*N ropt_net_137:7 *C 6.855 74.120 +*N ropt_net_137:8 *C 6.900 74.165 +*N ropt_net_137:9 *C 6.900 76.795 +*N ropt_net_137:10 *C 6.900 76.840 +*N ropt_net_137:11 *C 7.095 76.840 + +*CAP +0 ropt_mt_inst_740:X 1e-06 +1 ropt_mt_inst_752:A 1e-06 +2 ropt_net_137:2 9.451796e-05 +3 ropt_net_137:3 9.451796e-05 +4 ropt_net_137:4 7.137142e-05 +5 ropt_net_137:5 7.137142e-05 +6 ropt_net_137:6 0.0001592081 +7 ropt_net_137:7 0.0001592081 +8 ropt_net_137:8 0.0001607995 +9 ropt_net_137:9 0.0001607995 +10 ropt_net_137:10 5.708457e-05 +11 ropt_net_137:11 5.883922e-05 + +*RES +0 ropt_mt_inst_740:X ropt_net_137:11 0.152 +1 ropt_net_137:11 ropt_net_137:10 0.0001059783 +2 ropt_net_137:10 ropt_net_137:9 0.0045 +3 ropt_net_137:9 ropt_net_137:8 0.002348214 +4 ropt_net_137:7 ropt_net_137:6 0.001973214 +5 ropt_net_137:8 ropt_net_137:7 0.0045 +6 ropt_net_137:6 ropt_net_137:5 0.0045 +7 ropt_net_137:5 ropt_net_137:4 0.0005267857 +8 ropt_net_137:3 ropt_net_137:2 0.001158482 +9 ropt_net_137:4 ropt_net_137:3 0.0045 +10 ropt_net_137:2 ropt_mt_inst_752:A 0.152 + +*END + +*D_NET chanx_left_out[5] 0.001900797 //LENGTH 13.475 LUMPCC 0.0005290707 DR + +*CONN +*I ropt_mt_inst_762:X O *L 0 *C 11.695 72.760 +*P chanx_left_out[5] O *L 0.7423 *C 1.230 70.720 +*N chanx_left_out[5]:2 *C 1.820 70.720 +*N chanx_left_out[5]:3 *C 1.840 70.728 +*N chanx_left_out[5]:4 *C 1.840 72.752 +*N chanx_left_out[5]:5 *C 1.860 72.760 +*N chanx_left_out[5]:6 *C 11.492 72.760 +*N chanx_left_out[5]:7 *C 11.500 72.760 +*N chanx_left_out[5]:8 *C 11.500 72.760 +*N chanx_left_out[5]:9 *C 11.695 72.760 + +*CAP +0 ropt_mt_inst_762:X 1e-06 +1 chanx_left_out[5] 2.972658e-05 +2 chanx_left_out[5]:2 2.972658e-05 +3 chanx_left_out[5]:3 0.0001365547 +4 chanx_left_out[5]:4 0.0001365547 +5 chanx_left_out[5]:5 0.0004516647 +6 chanx_left_out[5]:6 0.0004516647 +7 chanx_left_out[5]:7 3.041536e-05 +8 chanx_left_out[5]:8 5.442989e-05 +9 chanx_left_out[5]:9 4.998899e-05 +10 chanx_left_out[5] chanx_left_in[7]:7 5.621256e-05 +11 chanx_left_out[5]:6 chanx_left_in[7]:6 0.0002083228 +12 chanx_left_out[5]:5 chanx_left_in[7]:7 0.0002083228 +13 chanx_left_out[5]:2 chanx_left_in[7]:6 5.621256e-05 + +*RES +0 ropt_mt_inst_762:X chanx_left_out[5]:9 0.152 +1 chanx_left_out[5]:9 chanx_left_out[5]:8 0.0001059783 +2 chanx_left_out[5]:8 chanx_left_out[5]:7 0.0045 +3 chanx_left_out[5]:7 chanx_left_out[5]:6 0.00341 +4 chanx_left_out[5]:6 chanx_left_out[5]:5 0.001509092 +5 chanx_left_out[5]:5 chanx_left_out[5]:4 0.00341 +6 chanx_left_out[5]:4 chanx_left_out[5]:3 0.00031725 +7 chanx_left_out[5]:2 chanx_left_out[5] 9.243333e-05 +8 chanx_left_out[5]:3 chanx_left_out[5]:2 0.00341 + +*END + +*D_NET chany_bottom_in[7] 0.02033529 //LENGTH 174.830 LUMPCC 0.005007645 DR + +*CONN +*P chany_bottom_in[7] I *L 0.29796 *C 87.400 1.290 +*I ropt_mt_inst_731:A I *L 0.001767 *C 3.220 88.400 +*N chany_bottom_in[7]:2 *C 87.750 2.720 +*N chany_bottom_in[7]:3 *C 3.258 88.400 +*N chany_bottom_in[7]:4 *C 5.935 88.400 +*N chany_bottom_in[7]:5 *C 5.980 88.355 +*N chany_bottom_in[7]:6 *C 5.980 85.385 +*N chany_bottom_in[7]:7 *C 6.025 85.340 +*N chany_bottom_in[7]:8 *C 10.995 85.340 +*N chany_bottom_in[7]:9 *C 11.040 85.295 +*N chany_bottom_in[7]:10 *C 11.040 69.405 +*N chany_bottom_in[7]:11 *C 11.085 69.360 +*N chany_bottom_in[7]:12 *C 13.295 69.360 +*N chany_bottom_in[7]:13 *C 13.340 69.315 +*N chany_bottom_in[7]:14 *C 13.340 68.737 +*N chany_bottom_in[7]:15 *C 13.348 68.680 +*N chany_bottom_in[7]:16 *C 63.175 68.680 +*N chany_bottom_in[7]:17 *C 87.380 68.680 +*N chany_bottom_in[7]:18 *C 87.400 68.672 +*N chany_bottom_in[7]:19 *C 87.400 52.555 +*N chany_bottom_in[7]:20 *C 87.400 2.728 +*N chany_bottom_in[7]:21 *C 87.400 2.720 +*N chany_bottom_in[7]:22 *C 87.400 2.663 + +*CAP +0 chany_bottom_in[7] 9.347669e-05 +1 ropt_mt_inst_731:A 1e-06 +2 chany_bottom_in[7]:2 6.448054e-05 +3 chany_bottom_in[7]:3 0.0001614257 +4 chany_bottom_in[7]:4 0.0001614257 +5 chany_bottom_in[7]:5 0.0001632499 +6 chany_bottom_in[7]:6 0.0001632499 +7 chany_bottom_in[7]:7 0.000334032 +8 chany_bottom_in[7]:8 0.000334032 +9 chany_bottom_in[7]:9 0.0007839822 +10 chany_bottom_in[7]:10 0.0007839822 +11 chany_bottom_in[7]:11 0.0001593217 +12 chany_bottom_in[7]:12 0.0001593217 +13 chany_bottom_in[7]:13 3.044962e-05 +14 chany_bottom_in[7]:14 3.044962e-05 +15 chany_bottom_in[7]:15 0.00136992 +16 chany_bottom_in[7]:16 0.002320615 +17 chany_bottom_in[7]:17 0.0009506959 +18 chany_bottom_in[7]:18 0.000906691 +19 chany_bottom_in[7]:19 0.00355229 +20 chany_bottom_in[7]:20 0.002645599 +21 chany_bottom_in[7]:21 6.448054e-05 +22 chany_bottom_in[7]:22 9.347669e-05 +23 chany_bottom_in[7]:15 chany_bottom_in[13]:7 0.0004755738 +24 chany_bottom_in[7]:15 chany_bottom_in[13]:8 6.169865e-05 +25 chany_bottom_in[7]:17 chany_bottom_in[13]:9 6.679678e-05 +26 chany_bottom_in[7]:16 chany_bottom_in[13]:9 6.169865e-05 +27 chany_bottom_in[7]:16 chany_bottom_in[13]:8 0.0005423705 +28 chany_bottom_in[7]:9 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.132059e-06 +29 chany_bottom_in[7]:10 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.132059e-06 +30 chany_bottom_in[7]:13 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.780347e-05 +31 chany_bottom_in[7]:14 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.780347e-05 +32 chany_bottom_in[7]:15 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001218322 +33 chany_bottom_in[7]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0005578871 +34 chany_bottom_in[7]:17 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 1.207623e-05 +35 chany_bottom_in[7]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 1.207623e-05 +36 chany_bottom_in[7]:16 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001776209 +37 chany_bottom_in[7]:5 ropt_net_147:5 1.262475e-05 +38 chany_bottom_in[7]:7 ropt_net_147:3 6.890805e-05 +39 chany_bottom_in[7]:6 ropt_net_147:4 1.262475e-05 +40 chany_bottom_in[7]:8 ropt_net_147:2 6.890805e-05 + +*RES +0 chany_bottom_in[7] chany_bottom_in[7]:22 0.001225446 +1 chany_bottom_in[7]:3 ropt_mt_inst_731:A 0.152 +2 chany_bottom_in[7]:4 chany_bottom_in[7]:3 0.002390625 +3 chany_bottom_in[7]:5 chany_bottom_in[7]:4 0.0045 +4 chany_bottom_in[7]:7 chany_bottom_in[7]:6 0.0045 +5 chany_bottom_in[7]:6 chany_bottom_in[7]:5 0.002651786 +6 chany_bottom_in[7]:8 chany_bottom_in[7]:7 0.0044375 +7 chany_bottom_in[7]:9 chany_bottom_in[7]:8 0.0045 +8 chany_bottom_in[7]:11 chany_bottom_in[7]:10 0.0045 +9 chany_bottom_in[7]:10 chany_bottom_in[7]:9 0.0141875 +10 chany_bottom_in[7]:12 chany_bottom_in[7]:11 0.001973214 +11 chany_bottom_in[7]:13 chany_bottom_in[7]:12 0.0045 +12 chany_bottom_in[7]:14 chany_bottom_in[7]:13 0.000515625 +13 chany_bottom_in[7]:15 chany_bottom_in[7]:14 0.00341 +14 chany_bottom_in[7]:17 chany_bottom_in[7]:16 0.003792116 +15 chany_bottom_in[7]:18 chany_bottom_in[7]:17 0.00341 +16 chany_bottom_in[7]:21 chany_bottom_in[7]:20 0.00341 +17 chany_bottom_in[7]:21 chany_bottom_in[7]:2 5.140625e-05 +18 chany_bottom_in[7]:20 chany_bottom_in[7]:19 0.007806308 +19 chany_bottom_in[7]:22 chany_bottom_in[7]:21 0.00341 +20 chany_bottom_in[7]:16 chany_bottom_in[7]:15 0.007806308 +21 chany_bottom_in[7]:19 chany_bottom_in[7]:18 0.002525075 + +*END + +*D_NET bottom_left_grid_pin_39_[0] 0.01270905 //LENGTH 86.503 LUMPCC 0.004337117 DR + +*CONN +*P bottom_left_grid_pin_39_[0] I *L 0.29796 *C 29.750 11.560 +*I mux_bottom_track_5\/mux_l1_in_1_:A0 I *L 0.001631 *C 31.570 33.320 +*I mux_bottom_track_1\/mux_l1_in_1_:A0 I *L 0.001631 *C 29.270 31.960 +*I mux_bottom_track_37\/mux_l1_in_0_:A1 I *L 0.00198 *C 74.060 23.460 +*I mux_bottom_track_21\/mux_l1_in_0_:A1 I *L 0.00198 *C 65.880 20.060 +*N bottom_left_grid_pin_39_[0]:5 *C 74.060 23.460 +*N bottom_left_grid_pin_39_[0]:6 *C 74.060 23.120 +*N bottom_left_grid_pin_39_[0]:7 *C 73.140 23.120 +*N bottom_left_grid_pin_39_[0]:8 *C 73.140 22.780 +*N bottom_left_grid_pin_39_[0]:9 *C 65.825 22.780 +*N bottom_left_grid_pin_39_[0]:10 *C 65.780 22.735 +*N bottom_left_grid_pin_39_[0]:11 *C 65.780 20.105 +*N bottom_left_grid_pin_39_[0]:12 *C 65.793 20.060 +*N bottom_left_grid_pin_39_[0]:13 *C 55.245 20.060 +*N bottom_left_grid_pin_39_[0]:14 *C 55.200 20.015 +*N bottom_left_grid_pin_39_[0]:15 *C 55.200 17.738 +*N bottom_left_grid_pin_39_[0]:16 *C 55.193 17.680 +*N bottom_left_grid_pin_39_[0]:17 *C 47.860 17.680 +*N bottom_left_grid_pin_39_[0]:18 *C 47.840 17.672 +*N bottom_left_grid_pin_39_[0]:19 *C 47.840 11.568 +*N bottom_left_grid_pin_39_[0]:20 *C 47.820 11.560 +*N bottom_left_grid_pin_39_[0]:21 *C 29.308 31.960 +*N bottom_left_grid_pin_39_[0]:22 *C 30.315 31.960 +*N bottom_left_grid_pin_39_[0]:23 *C 30.360 32.005 +*N bottom_left_grid_pin_39_[0]:24 *C 31.533 33.320 +*N bottom_left_grid_pin_39_[0]:25 *C 30.405 33.320 +*N bottom_left_grid_pin_39_[0]:26 *C 30.360 33.320 +*N bottom_left_grid_pin_39_[0]:27 *C 30.367 33.320 +*N bottom_left_grid_pin_39_[0]:28 *C 31.260 33.320 +*N bottom_left_grid_pin_39_[0]:29 *C 31.280 33.312 +*N bottom_left_grid_pin_39_[0]:30 *C 31.280 11.568 +*N bottom_left_grid_pin_39_[0]:31 *C 31.280 11.560 + +*CAP +0 bottom_left_grid_pin_39_[0] 9.698884e-05 +1 mux_bottom_track_5\/mux_l1_in_1_:A0 1e-06 +2 mux_bottom_track_1\/mux_l1_in_1_:A0 1e-06 +3 mux_bottom_track_37\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_21\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_39_[0]:5 5.09011e-05 +6 bottom_left_grid_pin_39_[0]:6 7.408659e-05 +7 bottom_left_grid_pin_39_[0]:7 7.569705e-05 +8 bottom_left_grid_pin_39_[0]:8 0.0003614007 +9 bottom_left_grid_pin_39_[0]:9 0.0003380117 +10 bottom_left_grid_pin_39_[0]:10 0.0001892748 +11 bottom_left_grid_pin_39_[0]:11 0.0001892748 +12 bottom_left_grid_pin_39_[0]:12 0.0004395786 +13 bottom_left_grid_pin_39_[0]:13 0.0004395786 +14 bottom_left_grid_pin_39_[0]:14 0.0002007653 +15 bottom_left_grid_pin_39_[0]:15 0.0002007653 +16 bottom_left_grid_pin_39_[0]:16 0.0004979433 +17 bottom_left_grid_pin_39_[0]:17 0.0004979433 +18 bottom_left_grid_pin_39_[0]:18 0.0002471255 +19 bottom_left_grid_pin_39_[0]:19 0.0002471255 +20 bottom_left_grid_pin_39_[0]:20 0.001075589 +21 bottom_left_grid_pin_39_[0]:21 0.0001143284 +22 bottom_left_grid_pin_39_[0]:22 0.0001143284 +23 bottom_left_grid_pin_39_[0]:23 9.399729e-05 +24 bottom_left_grid_pin_39_[0]:24 0.0001246426 +25 bottom_left_grid_pin_39_[0]:25 0.0001246426 +26 bottom_left_grid_pin_39_[0]:26 0.000133935 +27 bottom_left_grid_pin_39_[0]:27 0.0001010947 +28 bottom_left_grid_pin_39_[0]:28 0.0001010947 +29 bottom_left_grid_pin_39_[0]:29 0.000532622 +30 bottom_left_grid_pin_39_[0]:30 0.000532622 +31 bottom_left_grid_pin_39_[0]:31 0.001172578 +32 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_34_[0] 1.806593e-05 +33 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_34_[0]:26 1.598291e-05 +34 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_34_[0]:28 3.923384e-06 +35 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_34_[0]:35 1.455569e-05 +36 bottom_left_grid_pin_39_[0]:29 bottom_left_grid_pin_34_[0]:18 0.0004535991 +37 bottom_left_grid_pin_39_[0]:29 bottom_left_grid_pin_34_[0]:20 2.498925e-05 +38 bottom_left_grid_pin_39_[0]:29 bottom_left_grid_pin_34_[0]:27 5.840218e-05 +39 bottom_left_grid_pin_39_[0]:29 bottom_left_grid_pin_34_[0]:33 1.406285e-05 +40 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_34_[0] 1.455569e-05 +41 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_34_[0]:27 1.598291e-05 +42 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_34_[0]:32 3.923384e-06 +43 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_34_[0]:35 1.806593e-05 +44 bottom_left_grid_pin_39_[0]:30 bottom_left_grid_pin_34_[0]:19 0.0004535991 +45 bottom_left_grid_pin_39_[0]:30 bottom_left_grid_pin_34_[0]:26 2.498925e-05 +46 bottom_left_grid_pin_39_[0]:30 bottom_left_grid_pin_34_[0]:33 5.840218e-05 +47 bottom_left_grid_pin_39_[0]:30 bottom_left_grid_pin_34_[0]:34 1.406285e-05 +48 bottom_left_grid_pin_39_[0] chanx_left_in[4]:7 9.075043e-07 +49 bottom_left_grid_pin_39_[0]:20 chanx_left_in[4]:6 5.79113e-08 +50 bottom_left_grid_pin_39_[0]:29 chanx_left_in[4]:9 0.0008258556 +51 bottom_left_grid_pin_39_[0]:31 chanx_left_in[4]:6 9.075043e-07 +52 bottom_left_grid_pin_39_[0]:31 chanx_left_in[4]:7 5.79113e-08 +53 bottom_left_grid_pin_39_[0]:30 chanx_left_in[4]:8 0.0008258556 +54 bottom_left_grid_pin_39_[0]:13 mux_tree_tapbuf_size2_0_sram[1]:11 0.0001687555 +55 bottom_left_grid_pin_39_[0]:12 mux_tree_tapbuf_size2_0_sram[1]:10 0.0001687555 +56 bottom_left_grid_pin_39_[0]:5 mux_tree_tapbuf_size2_12_sram[0]:6 1.395187e-06 +57 bottom_left_grid_pin_39_[0]:5 mux_tree_tapbuf_size2_12_sram[0]:4 4.902443e-06 +58 bottom_left_grid_pin_39_[0]:9 mux_tree_tapbuf_size2_12_sram[0]:8 0.0001455851 +59 bottom_left_grid_pin_39_[0]:9 mux_tree_tapbuf_size2_12_sram[0]:6 4.72327e-06 +60 bottom_left_grid_pin_39_[0]:8 mux_tree_tapbuf_size2_12_sram[0]:7 0.000149295 +61 bottom_left_grid_pin_39_[0]:8 mux_tree_tapbuf_size2_12_sram[0]:5 4.72327e-06 +62 bottom_left_grid_pin_39_[0]:7 mux_tree_tapbuf_size2_12_sram[0]:6 2.574111e-05 +63 bottom_left_grid_pin_39_[0]:7 mux_tree_tapbuf_size2_12_sram[0]:4 4.408386e-06 +64 bottom_left_grid_pin_39_[0]:6 mux_tree_tapbuf_size2_12_sram[0]:3 4.408386e-06 +65 bottom_left_grid_pin_39_[0]:6 mux_tree_tapbuf_size2_12_sram[0]:7 1.395187e-06 +66 bottom_left_grid_pin_39_[0]:6 mux_tree_tapbuf_size2_12_sram[0]:5 2.693359e-05 +67 bottom_left_grid_pin_39_[0]:13 mux_tree_tapbuf_size2_5_sram[0]:9 2.233782e-05 +68 bottom_left_grid_pin_39_[0]:13 mux_tree_tapbuf_size2_5_sram[0]:10 0.0002249512 +69 bottom_left_grid_pin_39_[0]:12 mux_tree_tapbuf_size2_5_sram[0]:9 0.0002249512 +70 bottom_left_grid_pin_39_[0]:12 mux_tree_tapbuf_size2_5_sram[0]:4 2.233782e-05 +71 bottom_left_grid_pin_39_[0]:19 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001346392 +72 bottom_left_grid_pin_39_[0]:17 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:11 7.167099e-07 +73 bottom_left_grid_pin_39_[0]:18 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001346392 +74 bottom_left_grid_pin_39_[0]:16 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:2 7.167099e-07 + +*RES +0 bottom_left_grid_pin_39_[0] bottom_left_grid_pin_39_[0]:31 0.0002397 +1 bottom_left_grid_pin_39_[0]:20 bottom_left_grid_pin_39_[0]:19 0.00341 +2 bottom_left_grid_pin_39_[0]:19 bottom_left_grid_pin_39_[0]:18 0.00095645 +3 bottom_left_grid_pin_39_[0]:17 bottom_left_grid_pin_39_[0]:16 0.001148758 +4 bottom_left_grid_pin_39_[0]:18 bottom_left_grid_pin_39_[0]:17 0.00341 +5 bottom_left_grid_pin_39_[0]:15 bottom_left_grid_pin_39_[0]:14 0.002033482 +6 bottom_left_grid_pin_39_[0]:16 bottom_left_grid_pin_39_[0]:15 0.00341 +7 bottom_left_grid_pin_39_[0]:13 bottom_left_grid_pin_39_[0]:12 0.009417411 +8 bottom_left_grid_pin_39_[0]:14 bottom_left_grid_pin_39_[0]:13 0.0045 +9 bottom_left_grid_pin_39_[0]:26 bottom_left_grid_pin_39_[0]:25 0.0045 +10 bottom_left_grid_pin_39_[0]:26 bottom_left_grid_pin_39_[0]:23 0.001174107 +11 bottom_left_grid_pin_39_[0]:27 bottom_left_grid_pin_39_[0]:26 0.00341 +12 bottom_left_grid_pin_39_[0]:28 bottom_left_grid_pin_39_[0]:27 0.000139825 +13 bottom_left_grid_pin_39_[0]:29 bottom_left_grid_pin_39_[0]:28 0.00341 +14 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_39_[0]:30 0.00341 +15 bottom_left_grid_pin_39_[0]:31 bottom_left_grid_pin_39_[0]:20 0.002591267 +16 bottom_left_grid_pin_39_[0]:30 bottom_left_grid_pin_39_[0]:29 0.003406717 +17 bottom_left_grid_pin_39_[0]:5 mux_bottom_track_37\/mux_l1_in_0_:A1 0.152 +18 bottom_left_grid_pin_39_[0]:9 bottom_left_grid_pin_39_[0]:8 0.006531251 +19 bottom_left_grid_pin_39_[0]:10 bottom_left_grid_pin_39_[0]:9 0.0045 +20 bottom_left_grid_pin_39_[0]:12 bottom_left_grid_pin_39_[0]:11 0.0045 +21 bottom_left_grid_pin_39_[0]:12 mux_bottom_track_21\/mux_l1_in_0_:A1 0.152 +22 bottom_left_grid_pin_39_[0]:11 bottom_left_grid_pin_39_[0]:10 0.002348214 +23 bottom_left_grid_pin_39_[0]:25 bottom_left_grid_pin_39_[0]:24 0.001006696 +24 bottom_left_grid_pin_39_[0]:24 mux_bottom_track_5\/mux_l1_in_1_:A0 0.152 +25 bottom_left_grid_pin_39_[0]:22 bottom_left_grid_pin_39_[0]:21 0.0008995536 +26 bottom_left_grid_pin_39_[0]:23 bottom_left_grid_pin_39_[0]:22 0.0045 +27 bottom_left_grid_pin_39_[0]:21 mux_bottom_track_1\/mux_l1_in_1_:A0 0.152 +28 bottom_left_grid_pin_39_[0]:8 bottom_left_grid_pin_39_[0]:7 0.0003035715 +29 bottom_left_grid_pin_39_[0]:7 bottom_left_grid_pin_39_[0]:6 0.0008214285 +30 bottom_left_grid_pin_39_[0]:6 bottom_left_grid_pin_39_[0]:5 0.0003035715 + +*END + +*D_NET chanx_left_in[17] 0.006147479 //LENGTH 36.855 LUMPCC 0.002612208 DR + +*CONN +*P chanx_left_in[17] I *L 0.29796 *C 1.230 53.040 +*I mux_bottom_track_33\/mux_l1_in_0_:A0 I *L 0.001631 *C 35.230 55.080 +*N chanx_left_in[17]:2 *C 35.193 55.080 +*N chanx_left_in[17]:3 *C 18.905 55.080 +*N chanx_left_in[17]:4 *C 18.860 55.035 +*N chanx_left_in[17]:5 *C 18.860 53.098 +*N chanx_left_in[17]:6 *C 18.852 53.040 + +*CAP +0 chanx_left_in[17] 0.0006236346 +1 mux_bottom_track_33\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[17]:2 0.001022223 +3 chanx_left_in[17]:3 0.001022223 +4 chanx_left_in[17]:4 0.0001212782 +5 chanx_left_in[17]:5 0.0001212782 +6 chanx_left_in[17]:6 0.0006236346 +7 chanx_left_in[17] chanx_left_in[16]:7 0.0001011207 +8 chanx_left_in[17] chanx_left_in[16]:11 0.0004741175 +9 chanx_left_in[17]:6 chanx_left_in[16]:6 0.0001011207 +10 chanx_left_in[17]:6 chanx_left_in[16]:10 0.0004741175 +11 chanx_left_in[17]:3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 8.712887e-05 +12 chanx_left_in[17]:2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 8.712887e-05 +13 chanx_left_in[17]:3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 9.920681e-05 +14 chanx_left_in[17]:2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 9.920681e-05 +15 chanx_left_in[17] optlc_net_106:37 0.0004438453 +16 chanx_left_in[17] optlc_net_106:44 8.55552e-05 +17 chanx_left_in[17]:5 optlc_net_106:43 9.345035e-06 +18 chanx_left_in[17]:6 optlc_net_106:44 0.0004438453 +19 chanx_left_in[17]:6 optlc_net_106:45 8.55552e-05 +20 chanx_left_in[17]:3 optlc_net_106:48 5.784504e-06 +21 chanx_left_in[17]:4 optlc_net_106:40 9.345035e-06 +22 chanx_left_in[17]:2 optlc_net_106:49 5.784504e-06 + +*RES +0 chanx_left_in[17] chanx_left_in[17]:6 0.002760858 +1 chanx_left_in[17]:5 chanx_left_in[17]:4 0.001729911 +2 chanx_left_in[17]:6 chanx_left_in[17]:5 0.00341 +3 chanx_left_in[17]:3 chanx_left_in[17]:2 0.01454241 +4 chanx_left_in[17]:4 chanx_left_in[17]:3 0.0045 +5 chanx_left_in[17]:2 mux_bottom_track_33\/mux_l1_in_0_:A0 0.152 + +*END + +*D_NET chany_bottom_out[7] 0.001394147 //LENGTH 10.445 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 57.100 6.800 +*P chany_bottom_out[7] O *L 0.7423 *C 60.720 1.290 +*N chany_bottom_out[7]:2 *C 60.720 7.095 +*N chany_bottom_out[7]:3 *C 60.675 7.140 +*N chany_bottom_out[7]:4 *C 57.040 7.140 +*N chany_bottom_out[7]:5 *C 57.100 6.800 + +*CAP +0 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[7] 0.0003684622 +2 chany_bottom_out[7]:2 0.0003684622 +3 chany_bottom_out[7]:3 0.0002845291 +4 chany_bottom_out[7]:4 0.0003132875 +5 chany_bottom_out[7]:5 5.840611e-05 + +*RES +0 mux_bottom_track_15\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[7]:5 0.152 +1 chany_bottom_out[7]:5 chany_bottom_out[7]:4 0.0003035715 +2 chany_bottom_out[7]:3 chany_bottom_out[7]:2 0.0045 +3 chany_bottom_out[7]:2 chany_bottom_out[7] 0.005183036 +4 chany_bottom_out[7]:4 chany_bottom_out[7]:3 0.003245536 + +*END + +*D_NET chany_bottom_out[16] 0.0009138145 //LENGTH 8.390 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 64.460 9.520 +*P chany_bottom_out[16] O *L 0.7423 *C 64.400 1.290 +*N chany_bottom_out[16]:2 *C 64.400 9.475 +*N chany_bottom_out[16]:3 *C 64.400 9.520 + +*CAP +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[16] 0.0004393516 +2 chany_bottom_out[16]:2 0.0004393516 +3 chany_bottom_out[16]:3 3.411134e-05 + +*RES +0 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[16]:3 0.152 +1 chany_bottom_out[16]:3 chany_bottom_out[16]:2 0.0045 +2 chany_bottom_out[16]:2 chany_bottom_out[16] 0.007308036 + +*END + +*D_NET chanx_left_out[12] 0.0009645586 //LENGTH 7.810 LUMPCC 0.0001943265 DR + +*CONN +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 8.235 82.620 +*P chanx_left_out[12] O *L 0.7423 *C 1.298 82.960 +*N chanx_left_out[12]:2 *C 1.380 82.960 +*N chanx_left_out[12]:3 *C 1.380 82.960 +*N chanx_left_out[12]:4 *C 1.380 82.620 +*N chanx_left_out[12]:5 *C 1.425 82.620 +*N chanx_left_out[12]:6 *C 8.197 82.620 + +*CAP +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chanx_left_out[12] 2.859775e-05 +2 chanx_left_out[12]:2 2.859775e-05 +3 chanx_left_out[12]:3 5.101482e-05 +4 chanx_left_out[12]:4 4.739646e-05 +5 chanx_left_out[12]:5 0.0003068126 +6 chanx_left_out[12]:6 0.0003068126 +7 chanx_left_out[12]:6 ropt_net_127:4 9.716326e-05 +8 chanx_left_out[12]:5 ropt_net_127:3 9.716326e-05 + +*RES +0 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:X chanx_left_out[12]:6 0.152 +1 chanx_left_out[12]:6 chanx_left_out[12]:5 0.006046875 +2 chanx_left_out[12]:5 chanx_left_out[12]:4 0.0045 +3 chanx_left_out[12]:4 chanx_left_out[12]:3 0.0001634615 +4 chanx_left_out[12]:3 chanx_left_out[12]:2 0.00341 +5 chanx_left_out[12]:2 chanx_left_out[12] 2.35e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_12_sram[0] 0.004302581 //LENGTH 33.795 LUMPCC 0.00104297 DR + +*CONN +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 60.565 39.100 +*I mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 67.795 33.660 +*I mux_bottom_track_37\/mux_l1_in_0_:S I *L 0.00357 *C 74.880 23.800 +*N mux_tree_tapbuf_size2_12_sram[0]:3 *C 74.843 23.800 +*N mux_tree_tapbuf_size2_12_sram[0]:4 *C 73.600 23.800 +*N mux_tree_tapbuf_size2_12_sram[0]:5 *C 73.600 23.460 +*N mux_tree_tapbuf_size2_12_sram[0]:6 *C 72.680 23.460 +*N mux_tree_tapbuf_size2_12_sram[0]:7 *C 72.680 23.120 +*N mux_tree_tapbuf_size2_12_sram[0]:8 *C 69.045 23.120 +*N mux_tree_tapbuf_size2_12_sram[0]:9 *C 69.000 23.165 +*N mux_tree_tapbuf_size2_12_sram[0]:10 *C 69.000 33.615 +*N mux_tree_tapbuf_size2_12_sram[0]:11 *C 68.955 33.660 +*N mux_tree_tapbuf_size2_12_sram[0]:12 *C 67.833 33.660 +*N mux_tree_tapbuf_size2_12_sram[0]:13 *C 67.620 33.320 +*N mux_tree_tapbuf_size2_12_sram[0]:14 *C 60.765 33.320 +*N mux_tree_tapbuf_size2_12_sram[0]:15 *C 60.720 33.365 +*N mux_tree_tapbuf_size2_12_sram[0]:16 *C 60.720 39.055 +*N mux_tree_tapbuf_size2_12_sram[0]:17 *C 60.720 39.100 +*N mux_tree_tapbuf_size2_12_sram[0]:18 *C 60.565 39.100 + +*CAP +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_37\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_12_sram[0]:3 0.0001062017 +4 mux_tree_tapbuf_size2_12_sram[0]:4 0.0001279562 +5 mux_tree_tapbuf_size2_12_sram[0]:5 6.981881e-05 +6 mux_tree_tapbuf_size2_12_sram[0]:6 6.82306e-05 +7 mux_tree_tapbuf_size2_12_sram[0]:7 0.0001541607 +8 mux_tree_tapbuf_size2_12_sram[0]:8 0.0001339944 +9 mux_tree_tapbuf_size2_12_sram[0]:9 0.000558636 +10 mux_tree_tapbuf_size2_12_sram[0]:10 0.000558636 +11 mux_tree_tapbuf_size2_12_sram[0]:11 9.53297e-05 +12 mux_tree_tapbuf_size2_12_sram[0]:12 0.0001190301 +13 mux_tree_tapbuf_size2_12_sram[0]:13 0.0004842241 +14 mux_tree_tapbuf_size2_12_sram[0]:14 0.0004605238 +15 mux_tree_tapbuf_size2_12_sram[0]:15 0.0001096517 +16 mux_tree_tapbuf_size2_12_sram[0]:16 0.0001096517 +17 mux_tree_tapbuf_size2_12_sram[0]:17 5.257921e-05 +18 mux_tree_tapbuf_size2_12_sram[0]:18 4.798672e-05 +19 mux_tree_tapbuf_size2_12_sram[0]:8 bottom_left_grid_pin_39_[0]:9 0.0001455851 +20 mux_tree_tapbuf_size2_12_sram[0]:3 bottom_left_grid_pin_39_[0]:6 4.408386e-06 +21 mux_tree_tapbuf_size2_12_sram[0]:7 bottom_left_grid_pin_39_[0]:6 1.395187e-06 +22 mux_tree_tapbuf_size2_12_sram[0]:7 bottom_left_grid_pin_39_[0]:8 0.000149295 +23 mux_tree_tapbuf_size2_12_sram[0]:6 bottom_left_grid_pin_39_[0]:5 1.395187e-06 +24 mux_tree_tapbuf_size2_12_sram[0]:6 bottom_left_grid_pin_39_[0]:7 2.574111e-05 +25 mux_tree_tapbuf_size2_12_sram[0]:6 bottom_left_grid_pin_39_[0]:9 4.72327e-06 +26 mux_tree_tapbuf_size2_12_sram[0]:5 bottom_left_grid_pin_39_[0]:6 2.693359e-05 +27 mux_tree_tapbuf_size2_12_sram[0]:5 bottom_left_grid_pin_39_[0]:8 4.72327e-06 +28 mux_tree_tapbuf_size2_12_sram[0]:4 bottom_left_grid_pin_39_[0]:5 4.902443e-06 +29 mux_tree_tapbuf_size2_12_sram[0]:4 bottom_left_grid_pin_39_[0]:7 4.408386e-06 +30 mux_tree_tapbuf_size2_12_sram[0]:15 mux_tree_tapbuf_size2_15_sram[1]:13 0.0001673648 +31 mux_tree_tapbuf_size2_12_sram[0]:16 mux_tree_tapbuf_size2_15_sram[1]:14 0.0001673648 +32 mux_tree_tapbuf_size2_12_sram[0]:15 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001673648 +33 mux_tree_tapbuf_size2_12_sram[0]:16 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001673648 + +*RES +0 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_12_sram[0]:18 0.152 +1 mux_tree_tapbuf_size2_12_sram[0]:11 mux_tree_tapbuf_size2_12_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size2_12_sram[0]:10 mux_tree_tapbuf_size2_12_sram[0]:9 0.009330357 +3 mux_tree_tapbuf_size2_12_sram[0]:8 mux_tree_tapbuf_size2_12_sram[0]:7 0.003245536 +4 mux_tree_tapbuf_size2_12_sram[0]:9 mux_tree_tapbuf_size2_12_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size2_12_sram[0]:3 mux_bottom_track_37\/mux_l1_in_0_:S 0.152 +6 mux_tree_tapbuf_size2_12_sram[0]:14 mux_tree_tapbuf_size2_12_sram[0]:13 0.006120536 +7 mux_tree_tapbuf_size2_12_sram[0]:15 mux_tree_tapbuf_size2_12_sram[0]:14 0.0045 +8 mux_tree_tapbuf_size2_12_sram[0]:17 mux_tree_tapbuf_size2_12_sram[0]:16 0.0045 +9 mux_tree_tapbuf_size2_12_sram[0]:16 mux_tree_tapbuf_size2_12_sram[0]:15 0.005080357 +10 mux_tree_tapbuf_size2_12_sram[0]:18 mux_tree_tapbuf_size2_12_sram[0]:17 8.423914e-05 +11 mux_tree_tapbuf_size2_12_sram[0]:12 mem_bottom_track_37\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size2_12_sram[0]:12 mux_tree_tapbuf_size2_12_sram[0]:11 0.001002232 +13 mux_tree_tapbuf_size2_12_sram[0]:13 mux_tree_tapbuf_size2_12_sram[0]:12 0.0003035715 +14 mux_tree_tapbuf_size2_12_sram[0]:7 mux_tree_tapbuf_size2_12_sram[0]:6 0.0003035715 +15 mux_tree_tapbuf_size2_12_sram[0]:6 mux_tree_tapbuf_size2_12_sram[0]:5 0.0008214285 +16 mux_tree_tapbuf_size2_12_sram[0]:5 mux_tree_tapbuf_size2_12_sram[0]:4 0.0003035714 +17 mux_tree_tapbuf_size2_12_sram[0]:4 mux_tree_tapbuf_size2_12_sram[0]:3 0.001109375 + +*END + +*D_NET mux_tree_tapbuf_size2_1_sram[1] 0.001778488 //LENGTH 16.800 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 41.705 69.700 +*I mux_bottom_track_13\/mux_l2_in_0_:S I *L 0.00357 *C 39.460 63.920 +*I mem_bottom_track_13\/FTB_8__23:A I *L 0.001746 *C 40.480 77.520 +*N mux_tree_tapbuf_size2_1_sram[1]:3 *C 40.480 77.520 +*N mux_tree_tapbuf_size2_1_sram[1]:4 *C 40.480 77.475 +*N mux_tree_tapbuf_size2_1_sram[1]:5 *C 39.460 63.920 +*N mux_tree_tapbuf_size2_1_sram[1]:6 *C 39.560 63.965 +*N mux_tree_tapbuf_size2_1_sram[1]:7 *C 39.560 69.700 +*N mux_tree_tapbuf_size2_1_sram[1]:8 *C 40.480 69.745 +*N mux_tree_tapbuf_size2_1_sram[1]:9 *C 40.525 69.700 +*N mux_tree_tapbuf_size2_1_sram[1]:10 *C 41.668 69.700 + +*CAP +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_13\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_13\/FTB_8__23:A 1e-06 +3 mux_tree_tapbuf_size2_1_sram[1]:3 2.745668e-05 +4 mux_tree_tapbuf_size2_1_sram[1]:4 0.0004081856 +5 mux_tree_tapbuf_size2_1_sram[1]:5 3.128585e-05 +6 mux_tree_tapbuf_size2_1_sram[1]:6 0.0003104803 +7 mux_tree_tapbuf_size2_1_sram[1]:7 0.0003678567 +8 mux_tree_tapbuf_size2_1_sram[1]:8 0.000465562 +9 mux_tree_tapbuf_size2_1_sram[1]:9 8.233033e-05 +10 mux_tree_tapbuf_size2_1_sram[1]:10 8.233033e-05 + +*RES +0 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_1_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_1_sram[1]:5 mux_bottom_track_13\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_1_sram[1]:6 mux_tree_tapbuf_size2_1_sram[1]:5 0.0045 +3 mux_tree_tapbuf_size2_1_sram[1]:9 mux_tree_tapbuf_size2_1_sram[1]:8 0.0045 +4 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:7 0.0008214285 +5 mux_tree_tapbuf_size2_1_sram[1]:8 mux_tree_tapbuf_size2_1_sram[1]:4 0.006901786 +6 mux_tree_tapbuf_size2_1_sram[1]:10 mux_tree_tapbuf_size2_1_sram[1]:9 0.001020089 +7 mux_tree_tapbuf_size2_1_sram[1]:3 mem_bottom_track_13\/FTB_8__23:A 0.152 +8 mux_tree_tapbuf_size2_1_sram[1]:4 mux_tree_tapbuf_size2_1_sram[1]:3 0.0045 +9 mux_tree_tapbuf_size2_1_sram[1]:7 mux_tree_tapbuf_size2_1_sram[1]:6 0.005120536 + +*END + +*D_NET mux_tree_tapbuf_size2_6_sram[1] 0.002915687 //LENGTH 23.275 LUMPCC 0.000533212 DR + +*CONN +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 79.885 17.680 +*I mux_bottom_track_23\/mux_l2_in_0_:S I *L 0.00357 *C 80.140 12.920 +*I mem_bottom_track_23\/FTB_13__28:A I *L 0.001746 *C 86.480 28.560 +*N mux_tree_tapbuf_size2_6_sram[1]:3 *C 86.443 28.560 +*N mux_tree_tapbuf_size2_6_sram[1]:4 *C 81.465 28.560 +*N mux_tree_tapbuf_size2_6_sram[1]:5 *C 81.420 28.515 +*N mux_tree_tapbuf_size2_6_sram[1]:6 *C 81.420 20.400 +*N mux_tree_tapbuf_size2_6_sram[1]:7 *C 80.040 20.400 +*N mux_tree_tapbuf_size2_6_sram[1]:8 *C 80.040 12.920 +*N mux_tree_tapbuf_size2_6_sram[1]:9 *C 80.040 12.965 +*N mux_tree_tapbuf_size2_6_sram[1]:10 *C 80.040 17.680 +*N mux_tree_tapbuf_size2_6_sram[1]:11 *C 80.040 17.680 +*N mux_tree_tapbuf_size2_6_sram[1]:12 *C 79.885 17.680 + +*CAP +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_23\/FTB_13__28:A 1e-06 +3 mux_tree_tapbuf_size2_6_sram[1]:3 0.0003245188 +4 mux_tree_tapbuf_size2_6_sram[1]:4 0.0003245188 +5 mux_tree_tapbuf_size2_6_sram[1]:5 0.0003517057 +6 mux_tree_tapbuf_size2_6_sram[1]:6 0.0003966255 +7 mux_tree_tapbuf_size2_6_sram[1]:7 0.0001686972 +8 mux_tree_tapbuf_size2_6_sram[1]:8 3.542053e-05 +9 mux_tree_tapbuf_size2_6_sram[1]:9 0.0002545416 +10 mux_tree_tapbuf_size2_6_sram[1]:10 0.0004085306 +11 mux_tree_tapbuf_size2_6_sram[1]:11 5.961871e-05 +12 mux_tree_tapbuf_size2_6_sram[1]:12 5.529738e-05 +13 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_12_sram[1]:8 0.0001285463 +14 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_12_sram[1]:9 4.071132e-06 +15 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_12_sram[1]:5 0.0001285463 +16 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_12_sram[1]:8 4.071132e-06 +17 mux_tree_tapbuf_size2_6_sram[1]:5 optlc_net_107:35 7.068236e-05 +18 mux_tree_tapbuf_size2_6_sram[1]:10 optlc_net_107:36 1.604548e-06 +19 mux_tree_tapbuf_size2_6_sram[1]:10 optlc_net_107:39 1.087347e-05 +20 mux_tree_tapbuf_size2_6_sram[1]:10 optlc_net_107:43 2.308879e-05 +21 mux_tree_tapbuf_size2_6_sram[1]:9 optlc_net_107:43 1.087347e-05 +22 mux_tree_tapbuf_size2_6_sram[1]:9 optlc_net_107:42 9.852629e-06 +23 mux_tree_tapbuf_size2_6_sram[1]:7 optlc_net_107:35 1.604548e-06 +24 mux_tree_tapbuf_size2_6_sram[1]:7 optlc_net_107:38 2.773932e-05 +25 mux_tree_tapbuf_size2_6_sram[1]:7 optlc_net_107:39 1.323616e-05 +26 mux_tree_tapbuf_size2_6_sram[1]:6 optlc_net_107:37 2.773932e-05 +27 mux_tree_tapbuf_size2_6_sram[1]:6 optlc_net_107:36 7.068236e-05 + +*RES +0 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_6_sram[1]:12 0.152 +1 mux_tree_tapbuf_size2_6_sram[1]:4 mux_tree_tapbuf_size2_6_sram[1]:3 0.004444197 +2 mux_tree_tapbuf_size2_6_sram[1]:5 mux_tree_tapbuf_size2_6_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_6_sram[1]:3 mem_bottom_track_23\/FTB_13__28:A 0.152 +4 mux_tree_tapbuf_size2_6_sram[1]:11 mux_tree_tapbuf_size2_6_sram[1]:10 0.0045 +5 mux_tree_tapbuf_size2_6_sram[1]:10 mux_tree_tapbuf_size2_6_sram[1]:9 0.004209822 +6 mux_tree_tapbuf_size2_6_sram[1]:10 mux_tree_tapbuf_size2_6_sram[1]:7 0.002428571 +7 mux_tree_tapbuf_size2_6_sram[1]:12 mux_tree_tapbuf_size2_6_sram[1]:11 8.423914e-05 +8 mux_tree_tapbuf_size2_6_sram[1]:8 mux_bottom_track_23\/mux_l2_in_0_:S 0.152 +9 mux_tree_tapbuf_size2_6_sram[1]:9 mux_tree_tapbuf_size2_6_sram[1]:8 0.0045 +10 mux_tree_tapbuf_size2_6_sram[1]:7 mux_tree_tapbuf_size2_6_sram[1]:6 0.001232143 +11 mux_tree_tapbuf_size2_6_sram[1]:6 mux_tree_tapbuf_size2_6_sram[1]:5 0.007245536 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_14_ccff_tail[0] 0.001546459 //LENGTH 14.220 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/FTB_21__36:X O *L 0 *C 78.885 53.040 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 68.255 55.420 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 *C 68.293 55.420 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 *C 68.955 55.420 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:4 *C 69.000 55.375 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:5 *C 69.000 53.425 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:6 *C 69.045 53.380 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:7 *C 77.280 53.380 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:8 *C 77.280 53.040 +*N mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:9 *C 78.848 53.040 + +*CAP +0 mem_left_track_1\/FTB_21__36:X 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 6.676035e-05 +3 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 6.676035e-05 +4 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:4 0.0001254506 +5 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:5 0.0001254506 +6 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:6 0.000453797 +7 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:7 0.0004789777 +8 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:8 0.0001262218 +9 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:9 0.0001010412 + +*RES +0 mem_left_track_1\/FTB_21__36:X mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:8 0.001399554 +2 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:2 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:6 0.007352679 +8 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_14_ccff_tail[0]:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_8_ccff_tail[0] 0.00114947 //LENGTH 7.810 LUMPCC 0.0003088053 DR + +*CONN +*I mem_bottom_track_29\/FTB_15__30:X O *L 0 *C 16.375 57.800 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 20.875 55.420 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 *C 20.838 55.420 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 *C 17.065 55.420 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 *C 17.020 55.465 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 *C 17.020 57.755 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 *C 16.975 57.800 +*N mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 *C 16.413 57.800 + +*CAP +0 mem_bottom_track_29\/FTB_15__30:X 1e-06 +1 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 0.0002496131 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 0.0002496131 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 0.0001078331 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 0.0001078331 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 6.188644e-05 +7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 6.188644e-05 +8 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 chanx_left_in[17]:3 8.712887e-05 +9 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 chanx_left_in[17]:2 8.712887e-05 +10 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 optlc_net_106:40 6.727377e-05 +11 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 optlc_net_106:43 6.727377e-05 + +*RES +0 mem_bottom_track_29\/FTB_15__30:X mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 0.0005022322 +2 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 0.002044643 +4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 0.003368304 +5 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:2 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[2] 0.001098216 //LENGTH 8.810 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 38.485 4.420 +*I mux_bottom_track_7\/mux_l3_in_0_:S I *L 0.00357 *C 38.080 7.480 +*I mem_bottom_track_7\/FTB_4__19:A I *L 0.001746 *C 42.320 6.800 +*N mux_tree_tapbuf_size5_1_sram[2]:3 *C 42.320 6.800 +*N mux_tree_tapbuf_size5_1_sram[2]:4 *C 42.320 7.140 +*N mux_tree_tapbuf_size5_1_sram[2]:5 *C 38.080 7.480 +*N mux_tree_tapbuf_size5_1_sram[2]:6 *C 38.180 7.140 +*N mux_tree_tapbuf_size5_1_sram[2]:7 *C 38.180 7.095 +*N mux_tree_tapbuf_size5_1_sram[2]:8 *C 38.180 4.465 +*N mux_tree_tapbuf_size5_1_sram[2]:9 *C 38.180 4.420 +*N mux_tree_tapbuf_size5_1_sram[2]:10 *C 38.485 4.420 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_7\/FTB_4__19:A 1e-06 +3 mux_tree_tapbuf_size5_1_sram[2]:3 6.033792e-05 +4 mux_tree_tapbuf_size5_1_sram[2]:4 0.0002866256 +5 mux_tree_tapbuf_size5_1_sram[2]:5 5.999972e-05 +6 mux_tree_tapbuf_size5_1_sram[2]:6 0.0002900304 +7 mux_tree_tapbuf_size5_1_sram[2]:7 0.000154466 +8 mux_tree_tapbuf_size5_1_sram[2]:8 0.000154466 +9 mux_tree_tapbuf_size5_1_sram[2]:9 4.548539e-05 +10 mux_tree_tapbuf_size5_1_sram[2]:10 4.380447e-05 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_1_sram[2]:10 0.152 +1 mux_tree_tapbuf_size5_1_sram[2]:6 mux_tree_tapbuf_size5_1_sram[2]:5 0.0001847826 +2 mux_tree_tapbuf_size5_1_sram[2]:6 mux_tree_tapbuf_size5_1_sram[2]:4 0.003696429 +3 mux_tree_tapbuf_size5_1_sram[2]:7 mux_tree_tapbuf_size5_1_sram[2]:6 0.0045 +4 mux_tree_tapbuf_size5_1_sram[2]:9 mux_tree_tapbuf_size5_1_sram[2]:8 0.0045 +5 mux_tree_tapbuf_size5_1_sram[2]:8 mux_tree_tapbuf_size5_1_sram[2]:7 0.002348215 +6 mux_tree_tapbuf_size5_1_sram[2]:10 mux_tree_tapbuf_size5_1_sram[2]:9 0.0001657609 +7 mux_tree_tapbuf_size5_1_sram[2]:3 mem_bottom_track_7\/FTB_4__19:A 0.152 +8 mux_tree_tapbuf_size5_1_sram[2]:5 mux_bottom_track_7\/mux_l3_in_0_:S 0.152 +9 mux_tree_tapbuf_size5_1_sram[2]:4 mux_tree_tapbuf_size5_1_sram[2]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[0] 0.003637775 //LENGTH 26.870 LUMPCC 0.0003236771 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 25.145 36.720 +*I mux_bottom_track_5\/mux_l1_in_2_:S I *L 0.00357 *C 27.960 41.870 +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 35.135 44.540 +*I mux_bottom_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 32.100 41.870 +*I mux_bottom_track_5\/mux_l1_in_1_:S I *L 0.00357 *C 30.460 34.000 +*N mux_tree_tapbuf_size6_1_sram[0]:5 *C 30.360 34.000 +*N mux_tree_tapbuf_size6_1_sram[0]:6 *C 30.360 34.045 +*N mux_tree_tapbuf_size6_1_sram[0]:7 *C 30.360 36.675 +*N mux_tree_tapbuf_size6_1_sram[0]:8 *C 30.315 36.720 +*N mux_tree_tapbuf_size6_1_sram[0]:9 *C 32.100 41.870 +*N mux_tree_tapbuf_size6_1_sram[0]:10 *C 35.098 44.540 +*N mux_tree_tapbuf_size6_1_sram[0]:11 *C 32.705 44.540 +*N mux_tree_tapbuf_size6_1_sram[0]:12 *C 32.660 44.495 +*N mux_tree_tapbuf_size6_1_sram[0]:13 *C 32.660 42.205 +*N mux_tree_tapbuf_size6_1_sram[0]:14 *C 32.615 42.160 +*N mux_tree_tapbuf_size6_1_sram[0]:15 *C 32.100 42.160 +*N mux_tree_tapbuf_size6_1_sram[0]:16 *C 28.035 42.160 +*N mux_tree_tapbuf_size6_1_sram[0]:17 *C 27.980 42.160 +*N mux_tree_tapbuf_size6_1_sram[0]:18 *C 27.960 41.870 +*N mux_tree_tapbuf_size6_1_sram[0]:19 *C 27.960 41.480 +*N mux_tree_tapbuf_size6_1_sram[0]:20 *C 27.185 41.480 +*N mux_tree_tapbuf_size6_1_sram[0]:21 *C 27.140 41.435 +*N mux_tree_tapbuf_size6_1_sram[0]:22 *C 27.140 36.765 +*N mux_tree_tapbuf_size6_1_sram[0]:23 *C 27.140 36.720 +*N mux_tree_tapbuf_size6_1_sram[0]:24 *C 25.183 36.720 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_5\/mux_l1_in_2_:S 1e-06 +2 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_bottom_track_5\/mux_l1_in_0_:S 1e-06 +4 mux_bottom_track_5\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_1_sram[0]:5 3.401345e-05 +6 mux_tree_tapbuf_size6_1_sram[0]:6 0.0001306961 +7 mux_tree_tapbuf_size6_1_sram[0]:7 0.0001306961 +8 mux_tree_tapbuf_size6_1_sram[0]:8 0.0002126761 +9 mux_tree_tapbuf_size6_1_sram[0]:9 6.139046e-05 +10 mux_tree_tapbuf_size6_1_sram[0]:10 0.0001976405 +11 mux_tree_tapbuf_size6_1_sram[0]:11 0.0001976405 +12 mux_tree_tapbuf_size6_1_sram[0]:12 0.0001747755 +13 mux_tree_tapbuf_size6_1_sram[0]:13 0.0001747755 +14 mux_tree_tapbuf_size6_1_sram[0]:14 2.527346e-05 +15 mux_tree_tapbuf_size6_1_sram[0]:15 0.0002834405 +16 mux_tree_tapbuf_size6_1_sram[0]:16 0.000264013 +17 mux_tree_tapbuf_size6_1_sram[0]:17 3.054349e-05 +18 mux_tree_tapbuf_size6_1_sram[0]:18 0.0001021112 +19 mux_tree_tapbuf_size6_1_sram[0]:19 9.932937e-05 +20 mux_tree_tapbuf_size6_1_sram[0]:20 7.38398e-05 +21 mux_tree_tapbuf_size6_1_sram[0]:21 0.000299089 +22 mux_tree_tapbuf_size6_1_sram[0]:22 0.000299089 +23 mux_tree_tapbuf_size6_1_sram[0]:23 0.0003837565 +24 mux_tree_tapbuf_size6_1_sram[0]:24 0.000134308 +25 mux_tree_tapbuf_size6_1_sram[0]:14 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 2.632982e-05 +26 mux_tree_tapbuf_size6_1_sram[0]:16 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.901487e-05 +27 mux_tree_tapbuf_size6_1_sram[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.901487e-05 +28 mux_tree_tapbuf_size6_1_sram[0]:15 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 2.632982e-05 +29 mux_tree_tapbuf_size6_1_sram[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.649387e-05 +30 mux_tree_tapbuf_size6_1_sram[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.649387e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_1_sram[0]:24 0.152 +1 mux_tree_tapbuf_size6_1_sram[0]:18 mux_bottom_track_5\/mux_l1_in_2_:S 0.152 +2 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[0]:17 0.0002589286 +3 mux_tree_tapbuf_size6_1_sram[0]:18 mux_tree_tapbuf_size6_1_sram[0]:16 0.0002589286 +4 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:22 0.0045 +5 mux_tree_tapbuf_size6_1_sram[0]:23 mux_tree_tapbuf_size6_1_sram[0]:8 0.002834822 +6 mux_tree_tapbuf_size6_1_sram[0]:22 mux_tree_tapbuf_size6_1_sram[0]:21 0.004169643 +7 mux_tree_tapbuf_size6_1_sram[0]:20 mux_tree_tapbuf_size6_1_sram[0]:19 0.0006919643 +8 mux_tree_tapbuf_size6_1_sram[0]:21 mux_tree_tapbuf_size6_1_sram[0]:20 0.0045 +9 mux_tree_tapbuf_size6_1_sram[0]:8 mux_tree_tapbuf_size6_1_sram[0]:7 0.0045 +10 mux_tree_tapbuf_size6_1_sram[0]:7 mux_tree_tapbuf_size6_1_sram[0]:6 0.002348214 +11 mux_tree_tapbuf_size6_1_sram[0]:5 mux_bottom_track_5\/mux_l1_in_1_:S 0.152 +12 mux_tree_tapbuf_size6_1_sram[0]:6 mux_tree_tapbuf_size6_1_sram[0]:5 0.0045 +13 mux_tree_tapbuf_size6_1_sram[0]:24 mux_tree_tapbuf_size6_1_sram[0]:23 0.001747768 +14 mux_tree_tapbuf_size6_1_sram[0]:14 mux_tree_tapbuf_size6_1_sram[0]:13 0.0045 +15 mux_tree_tapbuf_size6_1_sram[0]:13 mux_tree_tapbuf_size6_1_sram[0]:12 0.002044643 +16 mux_tree_tapbuf_size6_1_sram[0]:11 mux_tree_tapbuf_size6_1_sram[0]:10 0.002136161 +17 mux_tree_tapbuf_size6_1_sram[0]:12 mux_tree_tapbuf_size6_1_sram[0]:11 0.0045 +18 mux_tree_tapbuf_size6_1_sram[0]:10 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +19 mux_tree_tapbuf_size6_1_sram[0]:9 mux_bottom_track_5\/mux_l1_in_0_:S 0.152 +20 mux_tree_tapbuf_size6_1_sram[0]:19 mux_tree_tapbuf_size6_1_sram[0]:18 0.0003482143 +21 mux_tree_tapbuf_size6_1_sram[0]:16 mux_tree_tapbuf_size6_1_sram[0]:15 0.003629464 +22 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:14 0.0004598215 +23 mux_tree_tapbuf_size6_1_sram[0]:15 mux_tree_tapbuf_size6_1_sram[0]:9 0.000125 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0] 0.008545619 //LENGTH 65.070 LUMPCC 0.002920471 DR + +*CONN +*I mux_bottom_track_3\/mux_l3_in_0_:X O *L 0 *C 17.305 33.660 +*I mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 52.300 6.655 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 52.263 6.720 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 52.010 6.770 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 51.980 6.845 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 *C 51.980 10.822 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 *C 51.977 10.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 *C 51.535 10.880 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 *C 51.520 10.888 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 *C 51.520 33.312 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 *C 51.500 33.320 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 *C 32.668 33.320 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 *C 32.660 33.320 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 *C 32.660 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 *C 32.615 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 *C 24.840 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 *C 24.840 34.000 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 *C 20.240 34.000 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 *C 20.240 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 *C 17.343 33.660 + +*CAP +0 mux_bottom_track_3\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.268092e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 4.268092e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.000245508 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.000245508 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 4.797517e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 4.797517e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0006913259 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0006913259 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.0006744518 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.0006744518 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 5.182362e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 4.771849e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.00058958 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 0.0006166181 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.0002454034 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.000242899 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 0.0002248779 +19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 0.0002003441 +20 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 chany_bottom_in[8]:13 0.0003179639 +21 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 chany_bottom_in[8]:12 0.0003179639 +22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 prog_clk[0]:299 8.962366e-06 +23 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 prog_clk[0]:300 8.962366e-06 +24 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 prog_clk[0]:167 7.450996e-05 +25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 prog_clk[0]:172 0.0001678639 +26 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 prog_clk[0]:201 9.489823e-06 +27 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 prog_clk[0]:172 7.450996e-05 +28 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 prog_clk[0]:200 0.0001678639 +29 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 prog_clk[0]:147 9.489823e-06 +30 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 chanx_left_in[12]:7 0.0004229784 +31 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 chanx_left_in[12]:8 0.0004229784 +32 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 3.890364e-06 +33 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 7.935473e-05 +34 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.935473e-05 +35 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.890364e-06 +36 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 4.244555e-05 +37 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.211734e-05 +38 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.211734e-05 +39 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.244555e-05 +40 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 5.647006e-05 +41 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.647006e-05 +42 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.251165e-06 +43 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.251165e-06 +44 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0002569379 +45 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0002569379 + +*RES +0 mux_bottom_track_3\/mux_l3_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_3\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0001578125 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.003551339 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:5 0.00341 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:6 6.499219e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:7 0.00341 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.00341 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.00351325 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 0.00341 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:10 0.002950425 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 0.0045 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:12 0.0001634615 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 0.002587053 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 0.0003035715 +16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 0.004107143 +17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 0.0003035715 +18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 0.006941964 + +*END + +*D_NET mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0005577728 //LENGTH 3.450 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_23\/mux_l2_in_0_:X O *L 0 *C 79.380 11.560 +*I mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 80.150 9.675 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 80.150 9.675 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 79.625 9.520 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 79.580 9.565 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 79.580 11.515 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 79.580 11.560 +*N mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 79.380 11.560 + +*CAP +0 mux_bottom_track_23\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001039759 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 6.803776e-05 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001276485 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001276485 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.520226e-05 +7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.325985e-05 + +*RES +0 mux_bottom_track_23\/mux_l2_in_0_:X mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00046875 +3 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741072 +6 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_23/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001086957 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0] 0.01130006 //LENGTH 86.880 LUMPCC 0.003747299 DR + +*CONN +*I mux_bottom_track_33\/mux_l2_in_0_:X O *L 0 *C 30.185 44.880 +*I mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 62.840 9.690 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 62.840 9.690 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 63.020 9.520 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 63.020 9.565 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 63.020 52.983 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 63.013 53.040 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 38.188 53.040 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 38.180 52.983 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 38.180 50.705 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 38.135 50.660 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 31.740 50.660 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 31.740 50.320 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 31.740 50.275 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 31.740 44.925 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 31.695 44.880 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:16 *C 30.223 44.880 + +*CAP +0 mux_bottom_track_33\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.637389e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.258633e-05 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001611114 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001611114 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001076951 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001076951 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001412333 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001412333 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0004262057 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0004543138 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:12 6.06283e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.000294506 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.000294506 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.0001265195 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.0001265195 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_in[8]:10 0.0003757072 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_in[8]:11 0.0003757072 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[10]:13 1.677857e-05 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[10]:14 0.0004816456 +21 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[10]:14 1.677857e-05 +22 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[10]:15 0.0004816456 +23 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 prog_clk[0]:147 0.0001162507 +24 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 prog_clk[0]:201 3.744733e-06 +25 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 prog_clk[0]:141 0.0001162507 +26 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 prog_clk[0]:147 3.744733e-06 +27 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:290 3.808882e-05 +28 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:293 5.941193e-05 +29 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:297 0.0001365956 +30 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 prog_clk[0]:299 6.629905e-06 +31 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:238 6.629905e-06 +32 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:293 3.808882e-05 +33 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:294 5.941193e-05 +34 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 prog_clk[0]:298 0.0001365956 +35 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_tree_tapbuf_size2_10_sram[1]:12 4.221734e-06 +36 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_tree_tapbuf_size2_10_sram[1]:13 4.221734e-06 +37 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_tree_tapbuf_size2_10_sram[1]:14 0.0006345749 +38 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_tree_tapbuf_size2_10_sram[1]:15 0.0006345749 + +*RES +0 mux_bottom_track_33\/mux_l2_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:16 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.001314732 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.004776786 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0003035715 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0045 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0045 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.002033482 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00388925 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.03876563 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.00341 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.239131e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_33\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.005709821 + +*END + +*D_NET ropt_net_144 0.0006650526 //LENGTH 4.985 LUMPCC 7.730004e-05 DR + +*CONN +*I ropt_mt_inst_727:X O *L 0 *C 4.140 79.560 +*I ropt_mt_inst_763:A I *L 0.001766 *C 7.820 80.240 +*N ropt_net_144:2 *C 7.820 80.240 +*N ropt_net_144:3 *C 7.820 80.195 +*N ropt_net_144:4 *C 7.820 79.605 +*N ropt_net_144:5 *C 7.775 79.560 +*N ropt_net_144:6 *C 4.178 79.560 + +*CAP +0 ropt_mt_inst_727:X 1e-06 +1 ropt_mt_inst_763:A 1e-06 +2 ropt_net_144:2 3.70544e-05 +3 ropt_net_144:3 6.263437e-05 +4 ropt_net_144:4 6.263437e-05 +5 ropt_net_144:5 0.0002117147 +6 ropt_net_144:6 0.0002117147 +7 ropt_net_144:5 ccff_tail[0]:7 3.865002e-05 +8 ropt_net_144:6 ccff_tail[0]:6 3.865002e-05 + +*RES +0 ropt_mt_inst_727:X ropt_net_144:6 0.152 +1 ropt_net_144:2 ropt_mt_inst_763:A 0.152 +2 ropt_net_144:3 ropt_net_144:2 0.0045 +3 ropt_net_144:5 ropt_net_144:4 0.0045 +4 ropt_net_144:4 ropt_net_144:3 0.0005267857 +5 ropt_net_144:6 ropt_net_144:5 0.003212054 + +*END + +*D_NET chanx_left_out[6] 0.001169902 //LENGTH 7.585 LUMPCC 0.0001365237 DR + +*CONN +*I ropt_mt_inst_739:X O *L 0 *C 7.055 44.540 +*P chanx_left_out[6] O *L 0.7423 *C 1.305 43.520 +*N chanx_left_out[6]:2 *C 5.053 43.520 +*N chanx_left_out[6]:3 *C 5.060 43.578 +*N chanx_left_out[6]:4 *C 5.060 44.495 +*N chanx_left_out[6]:5 *C 5.105 44.540 +*N chanx_left_out[6]:6 *C 7.018 44.540 + +*CAP +0 ropt_mt_inst_739:X 1e-06 +1 chanx_left_out[6] 0.0003518044 +2 chanx_left_out[6]:2 0.0003518044 +3 chanx_left_out[6]:3 7.168866e-05 +4 chanx_left_out[6]:4 7.168866e-05 +5 chanx_left_out[6]:5 9.269606e-05 +6 chanx_left_out[6]:6 9.269606e-05 +7 chanx_left_out[6]:5 ropt_net_129:8 6.826186e-05 +8 chanx_left_out[6]:6 ropt_net_129:9 6.826186e-05 + +*RES +0 ropt_mt_inst_739:X chanx_left_out[6]:6 0.152 +1 chanx_left_out[6]:3 chanx_left_out[6]:2 0.00341 +2 chanx_left_out[6]:2 chanx_left_out[6] 0.0005871083 +3 chanx_left_out[6]:5 chanx_left_out[6]:4 0.0045 +4 chanx_left_out[6]:4 chanx_left_out[6]:3 0.0008191965 +5 chanx_left_out[6]:6 chanx_left_out[6]:5 0.001707589 + +*END + +*D_NET ropt_net_128 0.001575555 //LENGTH 11.770 LUMPCC 0.0004498491 DR + +*CONN +*I BUFT_RR_54:X O *L 0 *C 11.040 45.560 +*I ropt_mt_inst_743:A I *L 0.001766 *C 7.820 53.040 +*N ropt_net_128:2 *C 7.843 53.013 +*N ropt_net_128:3 *C 7.855 52.700 +*N ropt_net_128:4 *C 9.615 52.700 +*N ropt_net_128:5 *C 9.660 52.655 +*N ropt_net_128:6 *C 9.660 45.605 +*N ropt_net_128:7 *C 9.705 45.560 +*N ropt_net_128:8 *C 11.003 45.560 + +*CAP +0 BUFT_RR_54:X 1e-06 +1 ropt_mt_inst_743:A 1e-06 +2 ropt_net_128:2 3.242525e-05 +3 ropt_net_128:3 0.0001075676 +4 ropt_net_128:4 7.514237e-05 +5 ropt_net_128:5 0.000347952 +6 ropt_net_128:6 0.000347952 +7 ropt_net_128:7 0.0001063332 +8 ropt_net_128:8 0.0001063332 +9 ropt_net_128:5 chany_bottom_in[15]:4 6.357194e-05 +10 ropt_net_128:6 chany_bottom_in[15]:5 6.357194e-05 +11 ropt_net_128:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 2.047748e-08 +12 ropt_net_128:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.325229e-06 +13 ropt_net_128:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.598639e-05 +14 ropt_net_128:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.598639e-05 +15 ropt_net_128:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 2.047748e-08 +16 ropt_net_128:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.325229e-06 +17 ropt_net_128:2 ropt_net_129:3 1.081735e-06 +18 ropt_net_128:4 ropt_net_129:4 7.493876e-05 +19 ropt_net_128:3 ropt_net_129:4 1.081735e-06 +20 ropt_net_128:3 ropt_net_129:5 7.493876e-05 + +*RES +0 BUFT_RR_54:X ropt_net_128:8 0.152 +1 ropt_net_128:2 ropt_mt_inst_743:A 0.152 +2 ropt_net_128:4 ropt_net_128:3 0.001571429 +3 ropt_net_128:5 ropt_net_128:4 0.0045 +4 ropt_net_128:7 ropt_net_128:6 0.0045 +5 ropt_net_128:6 ropt_net_128:5 0.006294644 +6 ropt_net_128:8 ropt_net_128:7 0.001158482 +7 ropt_net_128:3 ropt_net_128:2 0.0002111487 + +*END + +*D_NET chanx_left_out[10] 0.002378449 //LENGTH 12.005 LUMPCC 0.001154736 DR + +*CONN +*I ropt_mt_inst_765:X O *L 0 *C 11.695 98.600 +*P chanx_left_out[10] O *L 0.7423 *C 1.230 97.920 +*N chanx_left_out[10]:2 *C 1.840 97.920 +*N chanx_left_out[10]:3 *C 1.840 98.600 +*N chanx_left_out[10]:4 *C 11.492 98.600 +*N chanx_left_out[10]:5 *C 11.500 98.600 +*N chanx_left_out[10]:6 *C 11.500 98.600 +*N chanx_left_out[10]:7 *C 11.695 98.600 + +*CAP +0 ropt_mt_inst_765:X 1e-06 +1 chanx_left_out[10] 5.226758e-05 +2 chanx_left_out[10]:2 9.563554e-05 +3 chanx_left_out[10]:3 0.0004928937 +4 chanx_left_out[10]:4 0.0004495258 +5 chanx_left_out[10]:5 2.933404e-05 +6 chanx_left_out[10]:6 5.19564e-05 +7 chanx_left_out[10]:7 5.109904e-05 +8 chanx_left_out[10] chanx_left_in[9] 9.733783e-06 +9 chanx_left_out[10]:4 chanx_left_in[9]:10 0.0005676344 +10 chanx_left_out[10]:2 chanx_left_in[9]:10 9.733783e-06 +11 chanx_left_out[10]:3 chanx_left_in[9] 0.0005676344 + +*RES +0 ropt_mt_inst_765:X chanx_left_out[10]:7 0.152 +1 chanx_left_out[10]:7 chanx_left_out[10]:6 0.0001059783 +2 chanx_left_out[10]:6 chanx_left_out[10]:5 0.0045 +3 chanx_left_out[10]:5 chanx_left_out[10]:4 0.00341 +4 chanx_left_out[10]:4 chanx_left_out[10]:3 0.001512225 +5 chanx_left_out[10]:2 chanx_left_out[10] 9.556666e-05 +6 chanx_left_out[10]:3 chanx_left_out[10]:2 0.0001065333 + +*END + +*D_NET chany_bottom_in[8] 0.01852559 //LENGTH 139.665 LUMPCC 0.004558994 DR + +*CONN +*P chany_bottom_in[8] I *L 0.29796 *C 77.740 1.290 +*I ropt_mt_inst_735:A I *L 0.001766 *C 3.220 63.920 +*N chany_bottom_in[8]:2 *C 3.258 63.920 +*N chany_bottom_in[8]:3 *C 4.095 63.920 +*N chany_bottom_in[8]:4 *C 4.140 63.875 +*N chany_bottom_in[8]:5 *C 4.140 56.485 +*N chany_bottom_in[8]:6 *C 4.185 56.440 +*N chany_bottom_in[8]:7 *C 7.315 56.440 +*N chany_bottom_in[8]:8 *C 7.360 56.395 +*N chany_bottom_in[8]:9 *C 7.360 54.458 +*N chany_bottom_in[8]:10 *C 7.368 54.400 +*N chany_bottom_in[8]:11 *C 54.260 54.400 +*N chany_bottom_in[8]:12 *C 54.280 54.393 +*N chany_bottom_in[8]:13 *C 54.280 9.527 +*N chany_bottom_in[8]:14 *C 54.300 9.520 +*N chany_bottom_in[8]:15 *C 77.733 9.520 +*N chany_bottom_in[8]:16 *C 77.740 9.463 + +*CAP +0 chany_bottom_in[8] 0.0003780968 +1 ropt_mt_inst_735:A 1e-06 +2 chany_bottom_in[8]:2 6.621351e-05 +3 chany_bottom_in[8]:3 6.621351e-05 +4 chany_bottom_in[8]:4 0.0004576736 +5 chany_bottom_in[8]:5 0.0004576736 +6 chany_bottom_in[8]:6 0.0002230793 +7 chany_bottom_in[8]:7 0.0002230793 +8 chany_bottom_in[8]:8 0.0001512219 +9 chany_bottom_in[8]:9 0.0001512219 +10 chany_bottom_in[8]:10 0.001822714 +11 chany_bottom_in[8]:11 0.001822714 +12 chany_bottom_in[8]:12 0.002423432 +13 chany_bottom_in[8]:13 0.002423432 +14 chany_bottom_in[8]:14 0.001460366 +15 chany_bottom_in[8]:15 0.001460366 +16 chany_bottom_in[8]:16 0.0003780968 +17 chany_bottom_in[8]:10 prog_clk[0]:73 9.750923e-05 +18 chany_bottom_in[8]:10 prog_clk[0]:74 0.0001319272 +19 chany_bottom_in[8]:10 prog_clk[0]:131 0.0001693078 +20 chany_bottom_in[8]:11 prog_clk[0]:73 0.0001319272 +21 chany_bottom_in[8]:11 prog_clk[0]:56 9.750923e-05 +22 chany_bottom_in[8]:11 prog_clk[0]:132 0.0001693078 +23 chany_bottom_in[8]:14 prog_clk[0]:300 3.909918e-05 +24 chany_bottom_in[8]:14 prog_clk[0]:238 1.150773e-05 +25 chany_bottom_in[8]:15 prog_clk[0]:299 3.909918e-05 +26 chany_bottom_in[8]:15 prog_clk[0]:237 1.150773e-05 +27 chany_bottom_in[8]:10 optlc_net_106:37 0.0004438453 +28 chany_bottom_in[8]:10 optlc_net_106:44 0.000616728 +29 chany_bottom_in[8]:11 optlc_net_106:44 0.0004438453 +30 chany_bottom_in[8]:11 optlc_net_106:45 0.000616728 +31 chany_bottom_in[8]:12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:9 0.0003179639 +32 chany_bottom_in[8]:13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:8 0.0003179639 +33 chany_bottom_in[8]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003757072 +34 chany_bottom_in[8]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003757072 +35 chany_bottom_in[8] mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.590173e-05 +36 chany_bottom_in[8]:16 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.590173e-05 + +*RES +0 chany_bottom_in[8] chany_bottom_in[8]:16 0.007296875 +1 chany_bottom_in[8]:2 ropt_mt_inst_735:A 0.152 +2 chany_bottom_in[8]:3 chany_bottom_in[8]:2 0.0007477679 +3 chany_bottom_in[8]:4 chany_bottom_in[8]:3 0.0045 +4 chany_bottom_in[8]:6 chany_bottom_in[8]:5 0.0045 +5 chany_bottom_in[8]:5 chany_bottom_in[8]:4 0.006598215 +6 chany_bottom_in[8]:7 chany_bottom_in[8]:6 0.002794643 +7 chany_bottom_in[8]:8 chany_bottom_in[8]:7 0.0045 +8 chany_bottom_in[8]:9 chany_bottom_in[8]:8 0.001729911 +9 chany_bottom_in[8]:10 chany_bottom_in[8]:9 0.00341 +10 chany_bottom_in[8]:11 chany_bottom_in[8]:10 0.007346491 +11 chany_bottom_in[8]:12 chany_bottom_in[8]:11 0.00341 +12 chany_bottom_in[8]:14 chany_bottom_in[8]:13 0.00341 +13 chany_bottom_in[8]:13 chany_bottom_in[8]:12 0.007028849 +14 chany_bottom_in[8]:16 chany_bottom_in[8]:15 0.00341 +15 chany_bottom_in[8]:15 chany_bottom_in[8]:14 0.003671091 + +*END + +*D_NET bottom_left_grid_pin_36_[0] 0.01191923 //LENGTH 88.500 LUMPCC 0.002249766 DR + +*CONN +*P bottom_left_grid_pin_36_[0] I *L 0.29796 *C 29.750 6.800 +*I mux_bottom_track_7\/mux_l1_in_0_:A0 I *L 0.001631 *C 33.295 15.300 +*I mux_bottom_track_3\/mux_l1_in_0_:A0 I *L 0.001631 *C 24.210 31.620 +*I mux_bottom_track_31\/mux_l1_in_0_:A1 I *L 0.00198 *C 22.080 50.660 +*I mux_bottom_track_15\/mux_l1_in_0_:A1 I *L 0.00198 *C 33.220 61.540 +*N bottom_left_grid_pin_36_[0]:5 *C 33.183 61.540 +*N bottom_left_grid_pin_36_[0]:6 *C 31.325 61.540 +*N bottom_left_grid_pin_36_[0]:7 *C 31.280 61.495 +*N bottom_left_grid_pin_36_[0]:8 *C 31.280 59.218 +*N bottom_left_grid_pin_36_[0]:9 *C 31.273 59.160 +*N bottom_left_grid_pin_36_[0]:10 *C 20.260 59.160 +*N bottom_left_grid_pin_36_[0]:11 *C 20.240 59.153 +*N bottom_left_grid_pin_36_[0]:12 *C 19.840 51.000 +*N bottom_left_grid_pin_36_[0]:13 *C 22.043 50.660 +*N bottom_left_grid_pin_36_[0]:14 *C 20.285 50.660 +*N bottom_left_grid_pin_36_[0]:15 *C 20.240 50.660 +*N bottom_left_grid_pin_36_[0]:16 *C 20.240 51.000 +*N bottom_left_grid_pin_36_[0]:17 *C 20.240 51.000 +*N bottom_left_grid_pin_36_[0]:18 *C 20.240 51.000 +*N bottom_left_grid_pin_36_[0]:19 *C 20.240 35.367 +*N bottom_left_grid_pin_36_[0]:20 *C 20.260 35.360 +*N bottom_left_grid_pin_36_[0]:21 *C 23.913 35.360 +*N bottom_left_grid_pin_36_[0]:22 *C 23.920 35.303 +*N bottom_left_grid_pin_36_[0]:23 *C 24.210 31.620 +*N bottom_left_grid_pin_36_[0]:24 *C 23.920 31.620 +*N bottom_left_grid_pin_36_[0]:25 *C 23.920 31.620 +*N bottom_left_grid_pin_36_[0]:26 *C 23.920 29.285 +*N bottom_left_grid_pin_36_[0]:27 *C 23.965 29.240 +*N bottom_left_grid_pin_36_[0]:28 *C 30.775 29.240 +*N bottom_left_grid_pin_36_[0]:29 *C 30.820 29.195 +*N bottom_left_grid_pin_36_[0]:30 *C 33.258 15.300 +*N bottom_left_grid_pin_36_[0]:31 *C 30.865 15.300 +*N bottom_left_grid_pin_36_[0]:32 *C 30.820 15.300 +*N bottom_left_grid_pin_36_[0]:33 *C 30.820 6.857 +*N bottom_left_grid_pin_36_[0]:34 *C 30.812 6.800 + +*CAP +0 bottom_left_grid_pin_36_[0] 6.365445e-05 +1 mux_bottom_track_7\/mux_l1_in_0_:A0 1e-06 +2 mux_bottom_track_3\/mux_l1_in_0_:A0 1e-06 +3 mux_bottom_track_31\/mux_l1_in_0_:A1 1e-06 +4 mux_bottom_track_15\/mux_l1_in_0_:A1 1e-06 +5 bottom_left_grid_pin_36_[0]:5 0.0001503868 +6 bottom_left_grid_pin_36_[0]:6 0.0001503868 +7 bottom_left_grid_pin_36_[0]:7 0.0001219372 +8 bottom_left_grid_pin_36_[0]:8 0.0001219372 +9 bottom_left_grid_pin_36_[0]:9 0.0007273161 +10 bottom_left_grid_pin_36_[0]:10 0.0007273161 +11 bottom_left_grid_pin_36_[0]:11 0.0005014056 +12 bottom_left_grid_pin_36_[0]:12 8.260165e-05 +13 bottom_left_grid_pin_36_[0]:13 9.4503e-05 +14 bottom_left_grid_pin_36_[0]:14 9.4503e-05 +15 bottom_left_grid_pin_36_[0]:15 5.187076e-05 +16 bottom_left_grid_pin_36_[0]:16 5.57889e-05 +17 bottom_left_grid_pin_36_[0]:17 8.260165e-05 +18 bottom_left_grid_pin_36_[0]:18 0.001577491 +19 bottom_left_grid_pin_36_[0]:19 0.001076085 +20 bottom_left_grid_pin_36_[0]:20 0.0003982374 +21 bottom_left_grid_pin_36_[0]:21 0.0003982374 +22 bottom_left_grid_pin_36_[0]:22 0.0002104037 +23 bottom_left_grid_pin_36_[0]:23 5.282154e-05 +24 bottom_left_grid_pin_36_[0]:24 5.666928e-05 +25 bottom_left_grid_pin_36_[0]:25 0.000387828 +26 bottom_left_grid_pin_36_[0]:26 0.0001443511 +27 bottom_left_grid_pin_36_[0]:27 0.0003515371 +28 bottom_left_grid_pin_36_[0]:28 0.0003515371 +29 bottom_left_grid_pin_36_[0]:29 0.0004102302 +30 bottom_left_grid_pin_36_[0]:30 0.0001678484 +31 bottom_left_grid_pin_36_[0]:31 0.0001678484 +32 bottom_left_grid_pin_36_[0]:32 0.0006310535 +33 bottom_left_grid_pin_36_[0]:33 0.0001934188 +34 bottom_left_grid_pin_36_[0]:34 6.365445e-05 +35 bottom_left_grid_pin_36_[0]:17 prog_clk[0]:135 1.277337e-05 +36 bottom_left_grid_pin_36_[0]:29 prog_clk[0]:201 1.137156e-07 +37 bottom_left_grid_pin_36_[0]:29 prog_clk[0]:207 2.978286e-05 +38 bottom_left_grid_pin_36_[0]:29 prog_clk[0]:218 8.521996e-05 +39 bottom_left_grid_pin_36_[0]:32 prog_clk[0]:207 1.137156e-07 +40 bottom_left_grid_pin_36_[0]:32 prog_clk[0]:217 2.978286e-05 +41 bottom_left_grid_pin_36_[0]:32 prog_clk[0]:218 7.764251e-05 +42 bottom_left_grid_pin_36_[0]:32 prog_clk[0]:312 8.521996e-05 +43 bottom_left_grid_pin_36_[0]:32 prog_clk[0]:313 8.136122e-05 +44 bottom_left_grid_pin_36_[0]:8 prog_clk[0]:98 3.856528e-06 +45 bottom_left_grid_pin_36_[0]:7 prog_clk[0]:95 3.856528e-06 +46 bottom_left_grid_pin_36_[0]:33 prog_clk[0]:312 7.764251e-05 +47 bottom_left_grid_pin_36_[0]:33 prog_clk[0]:316 8.136122e-05 +48 bottom_left_grid_pin_36_[0]:12 prog_clk[0]:136 1.277337e-05 +49 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_35_[0] 2.06803e-05 +50 bottom_left_grid_pin_36_[0]:29 bottom_left_grid_pin_35_[0]:19 0.0003821441 +51 bottom_left_grid_pin_36_[0]:32 bottom_left_grid_pin_35_[0]:19 0.0001985315 +52 bottom_left_grid_pin_36_[0]:32 bottom_left_grid_pin_35_[0]:20 0.0003821441 +53 bottom_left_grid_pin_36_[0]:8 bottom_left_grid_pin_35_[0]:11 1.734815e-05 +54 bottom_left_grid_pin_36_[0]:7 bottom_left_grid_pin_35_[0]:8 1.734815e-05 +55 bottom_left_grid_pin_36_[0]:33 bottom_left_grid_pin_35_[0]:20 0.0001985315 +56 bottom_left_grid_pin_36_[0]:34 bottom_left_grid_pin_35_[0]:21 2.06803e-05 +57 bottom_left_grid_pin_36_[0]:28 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001279143 +58 bottom_left_grid_pin_36_[0]:29 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:9 6.276058e-06 +59 bottom_left_grid_pin_36_[0]:27 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001279143 +60 bottom_left_grid_pin_36_[0]:26 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.315898e-07 +61 bottom_left_grid_pin_36_[0]:22 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.163672e-08 +62 bottom_left_grid_pin_36_[0]:32 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:10 6.276058e-06 +63 bottom_left_grid_pin_36_[0]:25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.163672e-08 +64 bottom_left_grid_pin_36_[0]:25 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.315898e-07 +65 bottom_left_grid_pin_36_[0]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 8.058533e-05 +66 bottom_left_grid_pin_36_[0]:14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.058533e-05 + +*RES +0 bottom_left_grid_pin_36_[0] bottom_left_grid_pin_36_[0]:34 0.0001664583 +1 bottom_left_grid_pin_36_[0]:13 mux_bottom_track_31\/mux_l1_in_0_:A1 0.152 +2 bottom_left_grid_pin_36_[0]:14 bottom_left_grid_pin_36_[0]:13 0.001569197 +3 bottom_left_grid_pin_36_[0]:15 bottom_left_grid_pin_36_[0]:14 0.0045 +4 bottom_left_grid_pin_36_[0]:16 bottom_left_grid_pin_36_[0]:15 0.0001634616 +5 bottom_left_grid_pin_36_[0]:17 bottom_left_grid_pin_36_[0]:16 0.00341 +6 bottom_left_grid_pin_36_[0]:17 bottom_left_grid_pin_36_[0]:12 5.69697e-05 +7 bottom_left_grid_pin_36_[0]:18 bottom_left_grid_pin_36_[0]:17 0.00341 +8 bottom_left_grid_pin_36_[0]:18 bottom_left_grid_pin_36_[0]:11 0.001277225 +9 bottom_left_grid_pin_36_[0]:28 bottom_left_grid_pin_36_[0]:27 0.006080357 +10 bottom_left_grid_pin_36_[0]:29 bottom_left_grid_pin_36_[0]:28 0.0045 +11 bottom_left_grid_pin_36_[0]:27 bottom_left_grid_pin_36_[0]:26 0.0045 +12 bottom_left_grid_pin_36_[0]:26 bottom_left_grid_pin_36_[0]:25 0.002084822 +13 bottom_left_grid_pin_36_[0]:20 bottom_left_grid_pin_36_[0]:19 0.00341 +14 bottom_left_grid_pin_36_[0]:19 bottom_left_grid_pin_36_[0]:18 0.002449092 +15 bottom_left_grid_pin_36_[0]:22 bottom_left_grid_pin_36_[0]:21 0.00341 +16 bottom_left_grid_pin_36_[0]:21 bottom_left_grid_pin_36_[0]:20 0.000572225 +17 bottom_left_grid_pin_36_[0]:31 bottom_left_grid_pin_36_[0]:30 0.002136161 +18 bottom_left_grid_pin_36_[0]:32 bottom_left_grid_pin_36_[0]:31 0.0045 +19 bottom_left_grid_pin_36_[0]:32 bottom_left_grid_pin_36_[0]:29 0.01240625 +20 bottom_left_grid_pin_36_[0]:30 mux_bottom_track_7\/mux_l1_in_0_:A0 0.152 +21 bottom_left_grid_pin_36_[0]:24 bottom_left_grid_pin_36_[0]:23 0.0001576087 +22 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_36_[0]:24 0.0045 +23 bottom_left_grid_pin_36_[0]:25 bottom_left_grid_pin_36_[0]:22 0.003287947 +24 bottom_left_grid_pin_36_[0]:23 mux_bottom_track_3\/mux_l1_in_0_:A0 0.152 +25 bottom_left_grid_pin_36_[0]:10 bottom_left_grid_pin_36_[0]:9 0.001725292 +26 bottom_left_grid_pin_36_[0]:11 bottom_left_grid_pin_36_[0]:10 0.00341 +27 bottom_left_grid_pin_36_[0]:8 bottom_left_grid_pin_36_[0]:7 0.002033482 +28 bottom_left_grid_pin_36_[0]:9 bottom_left_grid_pin_36_[0]:8 0.00341 +29 bottom_left_grid_pin_36_[0]:6 bottom_left_grid_pin_36_[0]:5 0.001658482 +30 bottom_left_grid_pin_36_[0]:7 bottom_left_grid_pin_36_[0]:6 0.0045 +31 bottom_left_grid_pin_36_[0]:5 mux_bottom_track_15\/mux_l1_in_0_:A1 0.152 +32 bottom_left_grid_pin_36_[0]:33 bottom_left_grid_pin_36_[0]:32 0.007537947 +33 bottom_left_grid_pin_36_[0]:34 bottom_left_grid_pin_36_[0]:33 0.00341 + +*END + +*D_NET chanx_left_in[2] 0.003827216 //LENGTH 32.965 LUMPCC 0.0001952721 DR + +*CONN +*P chanx_left_in[2] I *L 0.29796 *C 1.230 68.000 +*I mux_bottom_track_3\/mux_l2_in_1_:A1 I *L 0.00198 *C 5.160 39.780 +*N chanx_left_in[2]:2 *C 5.123 39.780 +*N chanx_left_in[2]:3 *C 3.265 39.780 +*N chanx_left_in[2]:4 *C 3.220 39.825 +*N chanx_left_in[2]:5 *C 3.220 67.943 +*N chanx_left_in[2]:6 *C 3.213 68.000 + +*CAP +0 chanx_left_in[2] 0.0001551386 +1 mux_bottom_track_3\/mux_l2_in_1_:A1 1e-06 +2 chanx_left_in[2]:2 0.0001380162 +3 chanx_left_in[2]:3 0.0001380162 +4 chanx_left_in[2]:4 0.001522317 +5 chanx_left_in[2]:5 0.001522317 +6 chanx_left_in[2]:6 0.0001551386 +7 chanx_left_in[2]:4 ropt_net_126:5 9.763606e-05 +8 chanx_left_in[2]:5 ropt_net_126:4 9.763606e-05 + +*RES +0 chanx_left_in[2] chanx_left_in[2]:6 0.0003105916 +1 chanx_left_in[2]:2 mux_bottom_track_3\/mux_l2_in_1_:A1 0.152 +2 chanx_left_in[2]:3 chanx_left_in[2]:2 0.001658482 +3 chanx_left_in[2]:4 chanx_left_in[2]:3 0.0045 +4 chanx_left_in[2]:5 chanx_left_in[2]:4 0.02510491 +5 chanx_left_in[2]:6 chanx_left_in[2]:5 0.00341 + +*END + +*D_NET chanx_left_in[7] 0.00501843 //LENGTH 38.810 LUMPCC 0.001472695 DR + +*CONN +*P chanx_left_in[7] I *L 0.29796 *C 1.305 72.080 +*I mux_bottom_track_13\/mux_l1_in_0_:A0 I *L 0.001631 *C 33.295 66.300 +*N chanx_left_in[7]:2 *C 33.258 66.300 +*N chanx_left_in[7]:3 *C 32.245 66.300 +*N chanx_left_in[7]:4 *C 32.200 66.345 +*N chanx_left_in[7]:5 *C 32.200 71.343 +*N chanx_left_in[7]:6 *C 32.193 71.400 +*N chanx_left_in[7]:7 *C 1.380 71.400 + +*CAP +0 chanx_left_in[7] 5.43524e-05 +1 mux_bottom_track_13\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[7]:2 7.922979e-05 +3 chanx_left_in[7]:3 7.922979e-05 +4 chanx_left_in[7]:4 0.0002721711 +5 chanx_left_in[7]:5 0.0002721711 +6 chanx_left_in[7]:6 0.001366614 +7 chanx_left_in[7]:7 0.001420967 +8 chanx_left_in[7]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0004718123 +9 chanx_left_in[7]:7 mux_left_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0004718123 +10 chanx_left_in[7]:6 chanx_left_out[5]:6 0.0002083228 +11 chanx_left_in[7]:6 chanx_left_out[5]:2 5.621256e-05 +12 chanx_left_in[7]:7 chanx_left_out[5] 5.621256e-05 +13 chanx_left_in[7]:7 chanx_left_out[5]:5 0.0002083228 + +*RES +0 chanx_left_in[7] chanx_left_in[7]:7 0.0001065333 +1 chanx_left_in[7]:2 mux_bottom_track_13\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[7]:3 chanx_left_in[7]:2 0.0009040179 +3 chanx_left_in[7]:4 chanx_left_in[7]:3 0.0045 +4 chanx_left_in[7]:5 chanx_left_in[7]:4 0.004462054 +5 chanx_left_in[7]:6 chanx_left_in[7]:5 0.00341 +6 chanx_left_in[7]:7 chanx_left_in[7]:6 0.004827292 + +*END + +*D_NET chanx_left_in[14] 0.004139232 //LENGTH 25.805 LUMPCC 0.001201981 DR + +*CONN +*P chanx_left_in[14] I *L 0.29796 *C 1.305 59.840 +*I mux_bottom_track_27\/mux_l1_in_0_:A0 I *L 0.001631 *C 13.975 49.640 +*N chanx_left_in[14]:2 *C 13.975 49.640 +*N chanx_left_in[14]:3 *C 13.800 49.640 +*N chanx_left_in[14]:4 *C 13.800 49.685 +*N chanx_left_in[14]:5 *C 13.800 53.335 +*N chanx_left_in[14]:6 *C 13.800 53.380 +*N chanx_left_in[14]:7 *C 10.625 53.380 +*N chanx_left_in[14]:8 *C 10.580 53.425 +*N chanx_left_in[14]:9 *C 10.580 60.463 +*N chanx_left_in[14]:10 *C 10.572 60.520 +*N chanx_left_in[14]:11 *C 1.380 60.520 + +*CAP +0 chanx_left_in[14] 5.863932e-05 +1 mux_bottom_track_27\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[14]:2 5.703267e-05 +3 chanx_left_in[14]:3 6.14994e-05 +4 chanx_left_in[14]:4 0.0002355461 +5 chanx_left_in[14]:5 0.0002355461 +6 chanx_left_in[14]:6 0.0002079998 +7 chanx_left_in[14]:7 0.0001750706 +8 chanx_left_in[14]:8 0.0004627796 +9 chanx_left_in[14]:9 0.0004627796 +10 chanx_left_in[14]:10 0.0004603592 +11 chanx_left_in[14]:11 0.0005189985 +12 chanx_left_in[14]:10 chanx_left_in[3]:10 0.0005244929 +13 chanx_left_in[14]:11 chanx_left_in[3] 0.0005244929 +14 chanx_left_in[14]:6 ropt_net_129:2 7.649747e-05 +15 chanx_left_in[14]:7 ropt_net_129:3 7.649747e-05 + +*RES +0 chanx_left_in[14] chanx_left_in[14]:11 0.0001065333 +1 chanx_left_in[14]:2 mux_bottom_track_27\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[14]:3 chanx_left_in[14]:2 9.51087e-05 +3 chanx_left_in[14]:4 chanx_left_in[14]:3 0.0045 +4 chanx_left_in[14]:6 chanx_left_in[14]:5 0.0045 +5 chanx_left_in[14]:5 chanx_left_in[14]:4 0.003258929 +6 chanx_left_in[14]:7 chanx_left_in[14]:6 0.002834822 +7 chanx_left_in[14]:8 chanx_left_in[14]:7 0.0045 +8 chanx_left_in[14]:9 chanx_left_in[14]:8 0.006283483 +9 chanx_left_in[14]:10 chanx_left_in[14]:9 0.00341 +10 chanx_left_in[14]:11 chanx_left_in[14]:10 0.001440158 + +*END + +*D_NET ropt_net_115 0.000866352 //LENGTH 6.430 LUMPCC 0.0003357144 DR + +*CONN +*I mux_bottom_track_1\/BUFT_P_82:X O *L 0 *C 81.420 4.420 +*I ropt_mt_inst_730:A I *L 0.001767 *C 86.940 4.080 +*N ropt_net_115:2 *C 86.903 4.080 +*N ropt_net_115:3 *C 83.720 4.080 +*N ropt_net_115:4 *C 83.720 4.420 +*N ropt_net_115:5 *C 81.458 4.420 + +*CAP +0 mux_bottom_track_1\/BUFT_P_82:X 1e-06 +1 ropt_mt_inst_730:A 1e-06 +2 ropt_net_115:2 9.698717e-05 +3 ropt_net_115:3 0.0001229187 +4 ropt_net_115:4 0.0001673316 +5 ropt_net_115:5 0.0001414001 +6 ropt_net_115:5 ropt_net_145:2 2.758281e-05 +7 ropt_net_115:5 ropt_net_145:6 2.230523e-06 +8 ropt_net_115:2 ropt_net_145:7 3.491754e-05 +9 ropt_net_115:4 ropt_net_145:3 2.758281e-05 +10 ropt_net_115:4 ropt_net_145:7 2.230523e-06 +11 ropt_net_115:3 ropt_net_145:6 3.491754e-05 +12 ropt_net_115:5 chany_bottom_out[0]:3 4.407281e-06 +13 ropt_net_115:2 chany_bottom_out[0]:4 9.871904e-05 +14 ropt_net_115:4 chany_bottom_out[0]:4 4.407281e-06 +15 ropt_net_115:3 chany_bottom_out[0]:3 9.871904e-05 + +*RES +0 mux_bottom_track_1\/BUFT_P_82:X ropt_net_115:5 0.152 +1 ropt_net_115:5 ropt_net_115:4 0.002020089 +2 ropt_net_115:2 ropt_mt_inst_730:A 0.152 +3 ropt_net_115:4 ropt_net_115:3 0.0003035715 +4 ropt_net_115:3 ropt_net_115:2 0.002841518 + +*END + +*D_NET chany_bottom_out[11] 0.001557955 //LENGTH 13.405 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 78.605 9.520 +*P chany_bottom_out[11] O *L 0.7423 *C 74.060 1.290 +*N chany_bottom_out[11]:2 *C 74.060 9.135 +*N chany_bottom_out[11]:3 *C 74.105 9.180 +*N chany_bottom_out[11]:4 *C 78.660 9.180 +*N chany_bottom_out[11]:5 *C 78.605 9.520 + +*CAP +0 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[11] 0.0004275385 +2 chany_bottom_out[11]:2 0.0004275385 +3 chany_bottom_out[11]:3 0.0003002536 +4 chany_bottom_out[11]:4 0.0003332784 +5 chany_bottom_out[11]:5 6.83461e-05 + +*RES +0 mux_bottom_track_23\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[11]:5 0.152 +1 chany_bottom_out[11]:5 chany_bottom_out[11]:4 0.0003035715 +2 chany_bottom_out[11]:3 chany_bottom_out[11]:2 0.0045 +3 chany_bottom_out[11]:2 chany_bottom_out[11] 0.007004464 +4 chany_bottom_out[11]:4 chany_bottom_out[11]:3 0.004066965 + +*END + +*D_NET chany_bottom_out[19] 0.001810936 //LENGTH 15.145 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 74.520 11.900 +*P chany_bottom_out[19] O *L 0.7423 *C 70.840 1.290 +*N chany_bottom_out[19]:2 *C 70.840 2.040 +*N chany_bottom_out[19]:3 *C 71.300 2.040 +*N chany_bottom_out[19]:4 *C 71.300 11.515 +*N chany_bottom_out[19]:5 *C 71.345 11.560 +*N chany_bottom_out[19]:6 *C 74.520 11.560 +*N chany_bottom_out[19]:7 *C 74.520 11.900 + +*CAP +0 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[19] 5.279488e-05 +2 chany_bottom_out[19]:2 8.32368e-05 +3 chany_bottom_out[19]:3 0.0005945615 +4 chany_bottom_out[19]:4 0.0005641196 +5 chany_bottom_out[19]:5 0.0002194937 +6 chany_bottom_out[19]:6 0.0002447781 +7 chany_bottom_out[19]:7 5.095125e-05 + +*RES +0 mux_bottom_track_39\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[19]:7 0.152 +1 chany_bottom_out[19]:5 chany_bottom_out[19]:4 0.0045 +2 chany_bottom_out[19]:4 chany_bottom_out[19]:3 0.008459822 +3 chany_bottom_out[19]:7 chany_bottom_out[19]:6 0.0003035715 +4 chany_bottom_out[19]:6 chany_bottom_out[19]:5 0.002834821 +5 chany_bottom_out[19]:2 chany_bottom_out[19] 0.0006696429 +6 chany_bottom_out[19]:3 chany_bottom_out[19]:2 0.0004107143 + +*END + +*D_NET mux_tree_tapbuf_size2_10_sram[1] 0.005885048 //LENGTH 40.045 LUMPCC 0.001970353 DR + +*CONN +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 49.525 50.320 +*I mux_bottom_track_33\/mux_l2_in_0_:S I *L 0.00357 *C 29.340 45.220 +*I mem_bottom_track_33\/FTB_17__32:A I *L 0.001746 *C 33.580 39.440 +*N mux_tree_tapbuf_size2_10_sram[1]:3 *C 33.617 39.440 +*N mux_tree_tapbuf_size2_10_sram[1]:4 *C 33.995 39.440 +*N mux_tree_tapbuf_size2_10_sram[1]:5 *C 34.040 39.485 +*N mux_tree_tapbuf_size2_10_sram[1]:6 *C 34.040 46.920 +*N mux_tree_tapbuf_size2_10_sram[1]:7 *C 29.340 45.220 +*N mux_tree_tapbuf_size2_10_sram[1]:8 *C 29.440 45.265 +*N mux_tree_tapbuf_size2_10_sram[1]:9 *C 29.440 46.875 +*N mux_tree_tapbuf_size2_10_sram[1]:10 *C 29.485 46.920 +*N mux_tree_tapbuf_size2_10_sram[1]:11 *C 33.535 46.920 +*N mux_tree_tapbuf_size2_10_sram[1]:12 *C 33.580 46.920 +*N mux_tree_tapbuf_size2_10_sram[1]:13 *C 33.580 52.303 +*N mux_tree_tapbuf_size2_10_sram[1]:14 *C 33.587 52.360 +*N mux_tree_tapbuf_size2_10_sram[1]:15 *C 49.213 52.360 +*N mux_tree_tapbuf_size2_10_sram[1]:16 *C 49.220 52.303 +*N mux_tree_tapbuf_size2_10_sram[1]:17 *C 49.220 50.365 +*N mux_tree_tapbuf_size2_10_sram[1]:18 *C 49.220 50.320 +*N mux_tree_tapbuf_size2_10_sram[1]:19 *C 49.525 50.320 + +*CAP +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_33\/FTB_17__32:A 1e-06 +3 mux_tree_tapbuf_size2_10_sram[1]:3 6.681401e-05 +4 mux_tree_tapbuf_size2_10_sram[1]:4 6.681401e-05 +5 mux_tree_tapbuf_size2_10_sram[1]:5 0.0004515613 +6 mux_tree_tapbuf_size2_10_sram[1]:6 0.0004870449 +7 mux_tree_tapbuf_size2_10_sram[1]:7 2.936919e-05 +8 mux_tree_tapbuf_size2_10_sram[1]:8 0.0001343641 +9 mux_tree_tapbuf_size2_10_sram[1]:9 0.0001343641 +10 mux_tree_tapbuf_size2_10_sram[1]:10 0.0002863028 +11 mux_tree_tapbuf_size2_10_sram[1]:11 0.0002863028 +12 mux_tree_tapbuf_size2_10_sram[1]:12 0.0003467424 +13 mux_tree_tapbuf_size2_10_sram[1]:13 0.0003112588 +14 mux_tree_tapbuf_size2_10_sram[1]:14 0.0004977886 +15 mux_tree_tapbuf_size2_10_sram[1]:15 0.0004977886 +16 mux_tree_tapbuf_size2_10_sram[1]:16 0.0001149908 +17 mux_tree_tapbuf_size2_10_sram[1]:17 0.0001149908 +18 mux_tree_tapbuf_size2_10_sram[1]:18 4.488334e-05 +19 mux_tree_tapbuf_size2_10_sram[1]:19 4.031395e-05 +20 mux_tree_tapbuf_size2_10_sram[1]:14 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003463801 +21 mux_tree_tapbuf_size2_10_sram[1]:15 mux_bottom_track_27/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003463801 +22 mux_tree_tapbuf_size2_10_sram[1]:12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:14 4.221734e-06 +23 mux_tree_tapbuf_size2_10_sram[1]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:13 4.221734e-06 +24 mux_tree_tapbuf_size2_10_sram[1]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0006345749 +25 mux_tree_tapbuf_size2_10_sram[1]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0006345749 + +*RES +0 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_10_sram[1]:19 0.152 +1 mux_tree_tapbuf_size2_10_sram[1]:4 mux_tree_tapbuf_size2_10_sram[1]:3 0.0003370536 +2 mux_tree_tapbuf_size2_10_sram[1]:5 mux_tree_tapbuf_size2_10_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_10_sram[1]:3 mem_bottom_track_33\/FTB_17__32:A 0.152 +4 mux_tree_tapbuf_size2_10_sram[1]:11 mux_tree_tapbuf_size2_10_sram[1]:10 0.003616072 +5 mux_tree_tapbuf_size2_10_sram[1]:12 mux_tree_tapbuf_size2_10_sram[1]:11 0.0045 +6 mux_tree_tapbuf_size2_10_sram[1]:12 mux_tree_tapbuf_size2_10_sram[1]:6 0.0004107143 +7 mux_tree_tapbuf_size2_10_sram[1]:10 mux_tree_tapbuf_size2_10_sram[1]:9 0.0045 +8 mux_tree_tapbuf_size2_10_sram[1]:9 mux_tree_tapbuf_size2_10_sram[1]:8 0.0014375 +9 mux_tree_tapbuf_size2_10_sram[1]:7 mux_bottom_track_33\/mux_l2_in_0_:S 0.152 +10 mux_tree_tapbuf_size2_10_sram[1]:8 mux_tree_tapbuf_size2_10_sram[1]:7 0.0045 +11 mux_tree_tapbuf_size2_10_sram[1]:13 mux_tree_tapbuf_size2_10_sram[1]:12 0.004805803 +12 mux_tree_tapbuf_size2_10_sram[1]:14 mux_tree_tapbuf_size2_10_sram[1]:13 0.00341 +13 mux_tree_tapbuf_size2_10_sram[1]:16 mux_tree_tapbuf_size2_10_sram[1]:15 0.00341 +14 mux_tree_tapbuf_size2_10_sram[1]:15 mux_tree_tapbuf_size2_10_sram[1]:14 0.002447917 +15 mux_tree_tapbuf_size2_10_sram[1]:18 mux_tree_tapbuf_size2_10_sram[1]:17 0.0045 +16 mux_tree_tapbuf_size2_10_sram[1]:17 mux_tree_tapbuf_size2_10_sram[1]:16 0.001729911 +17 mux_tree_tapbuf_size2_10_sram[1]:19 mux_tree_tapbuf_size2_10_sram[1]:18 0.0001331522 +18 mux_tree_tapbuf_size2_10_sram[1]:6 mux_tree_tapbuf_size2_10_sram[1]:5 0.006638393 + +*END + +*D_NET mux_tree_tapbuf_size2_15_sram[0] 0.003805504 //LENGTH 32.685 LUMPCC 0.0005448281 DR + +*CONN +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 73.905 55.420 +*I mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 70.555 58.820 +*I mux_left_track_5\/mux_l1_in_0_:S I *L 0.00357 *C 84.740 42.160 +*N mux_tree_tapbuf_size2_15_sram[0]:3 *C 84.703 42.160 +*N mux_tree_tapbuf_size2_15_sram[0]:4 *C 80.960 42.160 +*N mux_tree_tapbuf_size2_15_sram[0]:5 *C 80.960 42.500 +*N mux_tree_tapbuf_size2_15_sram[0]:6 *C 80.960 42.545 +*N mux_tree_tapbuf_size2_15_sram[0]:7 *C 80.960 55.375 +*N mux_tree_tapbuf_size2_15_sram[0]:8 *C 80.915 55.420 +*N mux_tree_tapbuf_size2_15_sram[0]:9 *C 70.555 58.820 +*N mux_tree_tapbuf_size2_15_sram[0]:10 *C 70.380 58.820 +*N mux_tree_tapbuf_size2_15_sram[0]:11 *C 70.380 58.775 +*N mux_tree_tapbuf_size2_15_sram[0]:12 *C 70.380 55.465 +*N mux_tree_tapbuf_size2_15_sram[0]:13 *C 70.425 55.420 +*N mux_tree_tapbuf_size2_15_sram[0]:14 *C 73.905 55.420 + +*CAP +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_5\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_15_sram[0]:3 0.000177648 +4 mux_tree_tapbuf_size2_15_sram[0]:4 0.0002052524 +5 mux_tree_tapbuf_size2_15_sram[0]:5 5.945794e-05 +6 mux_tree_tapbuf_size2_15_sram[0]:6 0.0005341346 +7 mux_tree_tapbuf_size2_15_sram[0]:7 0.0005341346 +8 mux_tree_tapbuf_size2_15_sram[0]:8 0.0003860397 +9 mux_tree_tapbuf_size2_15_sram[0]:9 4.56976e-05 +10 mux_tree_tapbuf_size2_15_sram[0]:10 4.973611e-05 +11 mux_tree_tapbuf_size2_15_sram[0]:11 0.0002095047 +12 mux_tree_tapbuf_size2_15_sram[0]:12 0.0002095047 +13 mux_tree_tapbuf_size2_15_sram[0]:13 0.0002162882 +14 mux_tree_tapbuf_size2_15_sram[0]:14 0.0006302777 +15 mux_tree_tapbuf_size2_15_sram[0]:6 chany_bottom_in[0]:11 0.0001698953 +16 mux_tree_tapbuf_size2_15_sram[0]:7 chany_bottom_in[0]:10 0.0001698953 +17 mux_tree_tapbuf_size2_15_sram[0]:3 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:11 0.0001025188 +18 mux_tree_tapbuf_size2_15_sram[0]:4 mux_left_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:10 0.0001025188 + +*RES +0 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_15_sram[0]:14 0.152 +1 mux_tree_tapbuf_size2_15_sram[0]:3 mux_left_track_5\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_15_sram[0]:5 mux_tree_tapbuf_size2_15_sram[0]:4 0.0003035715 +3 mux_tree_tapbuf_size2_15_sram[0]:6 mux_tree_tapbuf_size2_15_sram[0]:5 0.0045 +4 mux_tree_tapbuf_size2_15_sram[0]:8 mux_tree_tapbuf_size2_15_sram[0]:7 0.0045 +5 mux_tree_tapbuf_size2_15_sram[0]:7 mux_tree_tapbuf_size2_15_sram[0]:6 0.01145536 +6 mux_tree_tapbuf_size2_15_sram[0]:13 mux_tree_tapbuf_size2_15_sram[0]:12 0.0045 +7 mux_tree_tapbuf_size2_15_sram[0]:12 mux_tree_tapbuf_size2_15_sram[0]:11 0.002955357 +8 mux_tree_tapbuf_size2_15_sram[0]:10 mux_tree_tapbuf_size2_15_sram[0]:9 9.510871e-05 +9 mux_tree_tapbuf_size2_15_sram[0]:11 mux_tree_tapbuf_size2_15_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_15_sram[0]:9 mem_left_track_5\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +11 mux_tree_tapbuf_size2_15_sram[0]:14 mux_tree_tapbuf_size2_15_sram[0]:13 0.003107143 +12 mux_tree_tapbuf_size2_15_sram[0]:14 mux_tree_tapbuf_size2_15_sram[0]:8 0.006258929 +13 mux_tree_tapbuf_size2_15_sram[0]:4 mux_tree_tapbuf_size2_15_sram[0]:3 0.003341518 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[0] 0.00468455 //LENGTH 38.535 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 62.405 42.500 +*I mux_bottom_track_19\/mux_l1_in_0_:S I *L 0.00357 *C 39.460 34.000 +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 44.795 31.620 +*N mux_tree_tapbuf_size2_4_sram[0]:3 *C 44.795 31.620 +*N mux_tree_tapbuf_size2_4_sram[0]:4 *C 39.498 34.000 +*N mux_tree_tapbuf_size2_4_sram[0]:5 *C 40.480 34.000 +*N mux_tree_tapbuf_size2_4_sram[0]:6 *C 40.480 34.340 +*N mux_tree_tapbuf_size2_4_sram[0]:7 *C 41.815 34.340 +*N mux_tree_tapbuf_size2_4_sram[0]:8 *C 41.860 34.295 +*N mux_tree_tapbuf_size2_4_sram[0]:9 *C 41.860 32.005 +*N mux_tree_tapbuf_size2_4_sram[0]:10 *C 41.905 31.960 +*N mux_tree_tapbuf_size2_4_sram[0]:11 *C 44.620 31.960 +*N mux_tree_tapbuf_size2_4_sram[0]:12 *C 58.375 31.960 +*N mux_tree_tapbuf_size2_4_sram[0]:13 *C 58.420 32.005 +*N mux_tree_tapbuf_size2_4_sram[0]:14 *C 58.420 42.455 +*N mux_tree_tapbuf_size2_4_sram[0]:15 *C 58.465 42.500 +*N mux_tree_tapbuf_size2_4_sram[0]:16 *C 62.367 42.500 + +*CAP +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_19\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_4_sram[0]:3 6.32699e-05 +4 mux_tree_tapbuf_size2_4_sram[0]:4 9.190544e-05 +5 mux_tree_tapbuf_size2_4_sram[0]:5 0.0001178198 +6 mux_tree_tapbuf_size2_4_sram[0]:6 0.0001211591 +7 mux_tree_tapbuf_size2_4_sram[0]:7 9.524473e-05 +8 mux_tree_tapbuf_size2_4_sram[0]:8 0.0001580228 +9 mux_tree_tapbuf_size2_4_sram[0]:9 0.0001580228 +10 mux_tree_tapbuf_size2_4_sram[0]:10 0.000196934 +11 mux_tree_tapbuf_size2_4_sram[0]:11 0.001125475 +12 mux_tree_tapbuf_size2_4_sram[0]:12 0.0008998103 +13 mux_tree_tapbuf_size2_4_sram[0]:13 0.0005752113 +14 mux_tree_tapbuf_size2_4_sram[0]:14 0.0005752113 +15 mux_tree_tapbuf_size2_4_sram[0]:15 0.0002517312 +16 mux_tree_tapbuf_size2_4_sram[0]:16 0.0002517312 + +*RES +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_4_sram[0]:16 0.152 +1 mux_tree_tapbuf_size2_4_sram[0]:3 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size2_4_sram[0]:12 mux_tree_tapbuf_size2_4_sram[0]:11 0.01228125 +3 mux_tree_tapbuf_size2_4_sram[0]:13 mux_tree_tapbuf_size2_4_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size2_4_sram[0]:15 mux_tree_tapbuf_size2_4_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size2_4_sram[0]:14 mux_tree_tapbuf_size2_4_sram[0]:13 0.009330358 +6 mux_tree_tapbuf_size2_4_sram[0]:16 mux_tree_tapbuf_size2_4_sram[0]:15 0.003484375 +7 mux_tree_tapbuf_size2_4_sram[0]:10 mux_tree_tapbuf_size2_4_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size2_4_sram[0]:9 mux_tree_tapbuf_size2_4_sram[0]:8 0.002044643 +9 mux_tree_tapbuf_size2_4_sram[0]:7 mux_tree_tapbuf_size2_4_sram[0]:6 0.001191964 +10 mux_tree_tapbuf_size2_4_sram[0]:8 mux_tree_tapbuf_size2_4_sram[0]:7 0.0045 +11 mux_tree_tapbuf_size2_4_sram[0]:4 mux_bottom_track_19\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size2_4_sram[0]:5 mux_tree_tapbuf_size2_4_sram[0]:4 0.0008772322 +13 mux_tree_tapbuf_size2_4_sram[0]:6 mux_tree_tapbuf_size2_4_sram[0]:5 0.0003035715 +14 mux_tree_tapbuf_size2_4_sram[0]:11 mux_tree_tapbuf_size2_4_sram[0]:10 0.002424107 +15 mux_tree_tapbuf_size2_4_sram[0]:11 mux_tree_tapbuf_size2_4_sram[0]:3 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[1] 0.001305356 //LENGTH 9.240 LUMPCC 0.0002847959 DR + +*CONN +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 32.505 53.040 +*I mux_bottom_track_31\/mux_l2_in_0_:S I *L 0.00357 *C 31.640 51.000 +*I mem_bottom_track_31\/FTB_16__31:A I *L 0.001746 *C 29.900 55.760 +*N mux_tree_tapbuf_size2_9_sram[1]:3 *C 29.938 55.760 +*N mux_tree_tapbuf_size2_9_sram[1]:4 *C 30.360 55.760 +*N mux_tree_tapbuf_size2_9_sram[1]:5 *C 30.360 55.420 +*N mux_tree_tapbuf_size2_9_sram[1]:6 *C 31.235 55.420 +*N mux_tree_tapbuf_size2_9_sram[1]:7 *C 31.280 55.375 +*N mux_tree_tapbuf_size2_9_sram[1]:8 *C 31.625 51.000 +*N mux_tree_tapbuf_size2_9_sram[1]:9 *C 31.303 51.000 +*N mux_tree_tapbuf_size2_9_sram[1]:10 *C 31.280 51.045 +*N mux_tree_tapbuf_size2_9_sram[1]:11 *C 31.280 53.040 +*N mux_tree_tapbuf_size2_9_sram[1]:12 *C 31.325 53.040 +*N mux_tree_tapbuf_size2_9_sram[1]:13 *C 32.468 53.040 + +*CAP +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_31\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_31\/FTB_16__31:A 1e-06 +3 mux_tree_tapbuf_size2_9_sram[1]:3 4.714791e-05 +4 mux_tree_tapbuf_size2_9_sram[1]:4 7.193602e-05 +5 mux_tree_tapbuf_size2_9_sram[1]:5 0.0001066403 +6 mux_tree_tapbuf_size2_9_sram[1]:6 8.185224e-05 +7 mux_tree_tapbuf_size2_9_sram[1]:7 8.859385e-05 +8 mux_tree_tapbuf_size2_9_sram[1]:8 6.331504e-05 +9 mux_tree_tapbuf_size2_9_sram[1]:9 6.331504e-05 +10 mux_tree_tapbuf_size2_9_sram[1]:10 8.836303e-05 +11 mux_tree_tapbuf_size2_9_sram[1]:11 0.000208178 +12 mux_tree_tapbuf_size2_9_sram[1]:12 9.910918e-05 +13 mux_tree_tapbuf_size2_9_sram[1]:13 9.910918e-05 +14 mux_tree_tapbuf_size2_9_sram[1]:10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.763811e-05 +15 mux_tree_tapbuf_size2_9_sram[1]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 1.937161e-05 +16 mux_tree_tapbuf_size2_9_sram[1]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.538825e-05 +17 mux_tree_tapbuf_size2_9_sram[1]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.763811e-05 +18 mux_tree_tapbuf_size2_9_sram[1]:11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.538825e-05 +19 mux_tree_tapbuf_size2_9_sram[1]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 1.937161e-05 + +*RES +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_9_sram[1]:13 0.152 +1 mux_tree_tapbuf_size2_9_sram[1]:8 mux_bottom_track_31\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_9_sram[1]:9 mux_tree_tapbuf_size2_9_sram[1]:8 0.0001752718 +3 mux_tree_tapbuf_size2_9_sram[1]:10 mux_tree_tapbuf_size2_9_sram[1]:9 0.0045 +4 mux_tree_tapbuf_size2_9_sram[1]:3 mem_bottom_track_31\/FTB_16__31:A 0.152 +5 mux_tree_tapbuf_size2_9_sram[1]:6 mux_tree_tapbuf_size2_9_sram[1]:5 0.00078125 +6 mux_tree_tapbuf_size2_9_sram[1]:7 mux_tree_tapbuf_size2_9_sram[1]:6 0.0045 +7 mux_tree_tapbuf_size2_9_sram[1]:12 mux_tree_tapbuf_size2_9_sram[1]:11 0.0045 +8 mux_tree_tapbuf_size2_9_sram[1]:11 mux_tree_tapbuf_size2_9_sram[1]:10 0.00178125 +9 mux_tree_tapbuf_size2_9_sram[1]:11 mux_tree_tapbuf_size2_9_sram[1]:7 0.002084821 +10 mux_tree_tapbuf_size2_9_sram[1]:13 mux_tree_tapbuf_size2_9_sram[1]:12 0.001020089 +11 mux_tree_tapbuf_size2_9_sram[1]:4 mux_tree_tapbuf_size2_9_sram[1]:3 0.0003772322 +12 mux_tree_tapbuf_size2_9_sram[1]:5 mux_tree_tapbuf_size2_9_sram[1]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_7_ccff_tail[0] 0.001586983 //LENGTH 12.815 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_27\/FTB_14__29:X O *L 0 *C 11.750 58.820 +*I mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 15.810 66.300 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 *C 15.810 66.300 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 *C 15.810 65.960 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 *C 11.545 65.960 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 *C 11.500 65.915 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 *C 11.500 58.865 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 *C 11.500 58.820 +*N mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:8 *C 11.750 58.820 + +*CAP +0 mem_bottom_track_27\/FTB_14__29:X 1e-06 +1 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 5.186023e-05 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 0.0003259883 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.000300299 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.0003932774 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 0.0003932774 +7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 6.143907e-05 +8 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:8 5.884199e-05 + +*RES +0 mem_bottom_track_27\/FTB_14__29:X mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 0.0001358696 +2 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 0.006294643 +4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 0.003808036 +5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 mem_bottom_track_29\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_7_ccff_tail[0]:2 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[2] 0.001513275 //LENGTH 11.160 LUMPCC 0.0003767994 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 14.105 36.720 +*I mux_bottom_track_3\/mux_l3_in_0_:S I *L 0.00357 *C 16.460 34.000 +*I mem_bottom_track_3\/FTB_3__18:A I *L 0.001746 *C 16.560 39.440 +*N mux_tree_tapbuf_size5_0_sram[2]:3 *C 16.523 39.440 +*N mux_tree_tapbuf_size5_0_sram[2]:4 *C 14.305 39.440 +*N mux_tree_tapbuf_size5_0_sram[2]:5 *C 14.260 39.395 +*N mux_tree_tapbuf_size5_0_sram[2]:6 *C 16.422 34.000 +*N mux_tree_tapbuf_size5_0_sram[2]:7 *C 14.305 34.000 +*N mux_tree_tapbuf_size5_0_sram[2]:8 *C 14.260 34.045 +*N mux_tree_tapbuf_size5_0_sram[2]:9 *C 14.260 36.720 +*N mux_tree_tapbuf_size5_0_sram[2]:10 *C 14.260 36.720 +*N mux_tree_tapbuf_size5_0_sram[2]:11 *C 14.105 36.720 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:S 1e-06 +2 mem_bottom_track_3\/FTB_3__18:A 1e-06 +3 mux_tree_tapbuf_size5_0_sram[2]:3 0.0001286213 +4 mux_tree_tapbuf_size5_0_sram[2]:4 0.0001286213 +5 mux_tree_tapbuf_size5_0_sram[2]:5 0.0001136299 +6 mux_tree_tapbuf_size5_0_sram[2]:6 0.0001542537 +7 mux_tree_tapbuf_size5_0_sram[2]:7 0.0001542537 +8 mux_tree_tapbuf_size5_0_sram[2]:8 0.0001091829 +9 mux_tree_tapbuf_size5_0_sram[2]:9 0.0002524166 +10 mux_tree_tapbuf_size5_0_sram[2]:10 4.835583e-05 +11 mux_tree_tapbuf_size5_0_sram[2]:11 4.41408e-05 +12 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[0]:19 7.435404e-05 +13 mux_tree_tapbuf_size5_0_sram[2]:4 mux_tree_tapbuf_size5_0_sram[0]:22 1.385133e-05 +14 mux_tree_tapbuf_size5_0_sram[2]:5 mux_tree_tapbuf_size5_0_sram[0]:20 5.956148e-05 +15 mux_tree_tapbuf_size5_0_sram[2]:3 mux_tree_tapbuf_size5_0_sram[0]:21 1.385133e-05 +16 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[0]:19 5.956148e-05 +17 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[0]:20 7.435404e-05 +18 mux_tree_tapbuf_size5_0_sram[2]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 4.063283e-05 +19 mux_tree_tapbuf_size5_0_sram[2]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 4.063283e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size5_0_sram[2]:11 0.152 +1 mux_tree_tapbuf_size5_0_sram[2]:7 mux_tree_tapbuf_size5_0_sram[2]:6 0.001890625 +2 mux_tree_tapbuf_size5_0_sram[2]:8 mux_tree_tapbuf_size5_0_sram[2]:7 0.0045 +3 mux_tree_tapbuf_size5_0_sram[2]:6 mux_bottom_track_3\/mux_l3_in_0_:S 0.152 +4 mux_tree_tapbuf_size5_0_sram[2]:4 mux_tree_tapbuf_size5_0_sram[2]:3 0.001979911 +5 mux_tree_tapbuf_size5_0_sram[2]:5 mux_tree_tapbuf_size5_0_sram[2]:4 0.0045 +6 mux_tree_tapbuf_size5_0_sram[2]:3 mem_bottom_track_3\/FTB_3__18:A 0.152 +7 mux_tree_tapbuf_size5_0_sram[2]:10 mux_tree_tapbuf_size5_0_sram[2]:9 0.0045 +8 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:8 0.002388393 +9 mux_tree_tapbuf_size5_0_sram[2]:9 mux_tree_tapbuf_size5_0_sram[2]:5 0.002388393 +10 mux_tree_tapbuf_size5_0_sram[2]:11 mux_tree_tapbuf_size5_0_sram[2]:10 8.423914e-05 + +*END + +*D_NET optlc_net_105 0.0003993339 //LENGTH 3.680 LUMPCC 0 DR + +*CONN +*I optlc_100:HI O *L 0 *C 95.680 58.820 +*I mux_left_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 92.290 58.820 +*N optlc_net_105:2 *C 92.328 58.820 +*N optlc_net_105:3 *C 95.642 58.820 + +*CAP +0 optlc_100:HI 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A0 1e-06 +2 optlc_net_105:2 0.0001986669 +3 optlc_net_105:3 0.0001986669 + +*RES +0 optlc_100:HI optlc_net_105:3 0.152 +1 optlc_net_105:2 mux_left_track_1\/mux_l2_in_0_:A0 0.152 +2 optlc_net_105:3 optlc_net_105:2 0.002959821 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0] 0.0009683151 //LENGTH 6.995 LUMPCC 0.0001091258 DR + +*CONN +*I mux_bottom_track_1\/mux_l1_in_1_:X O *L 0 *C 27.315 31.280 +*I mux_bottom_track_1\/mux_l2_in_0_:A0 I *L 0.001631 *C 23.290 33.320 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 23.328 33.320 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 25.715 33.320 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 25.760 33.275 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 25.760 31.325 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 25.805 31.280 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 27.277 31.280 + +*CAP +0 mux_bottom_track_1\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_1\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001550025 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0001550025 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001365917 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001365917 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001370005 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001370005 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 1.211734e-05 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:15 4.244555e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:14 4.244555e-05 +11 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 1.211734e-05 + +*RES +0 mux_bottom_track_1\/mux_l1_in_1_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_1\/mux_l2_in_0_:A0 0.152 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.002131697 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741071 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001314732 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007672771 //LENGTH 5.015 LUMPCC 0.000230133 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_0_:X O *L 0 *C 17.195 31.620 +*I mux_bottom_track_3\/mux_l3_in_0_:A1 I *L 0.00198 *C 15.640 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 15.678 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 16.975 34.340 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 17.020 34.295 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 17.020 31.665 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 17.020 31.620 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 17.195 31.620 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 7.074609e-05 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 7.074609e-05 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0001357689 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0001357689 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.967277e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.244149e-05 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_0_sram[1]:15 2.800371e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_0_sram[1]:16 2.800371e-05 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_0_sram[1]:17 3.314298e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_tree_tapbuf_size5_0_sram[1]:19 1.328698e-05 +12 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_0_sram[1]:18 3.314298e-05 +13 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_tree_tapbuf_size5_0_sram[1]:5 1.328698e-05 +14 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size5_0_sram[2]:7 4.063283e-05 +15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size5_0_sram[2]:6 4.063283e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001158482 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.002348214 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0] 0.005443722 //LENGTH 44.235 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_9\/mux_l2_in_0_:X O *L 0 *C 46.745 11.560 +*I mux_bottom_track_9\/BUFT_RR_41:A I *L 0.001776 *C 86.940 9.520 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 86.940 9.520 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 86.940 9.180 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 79.120 9.180 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 79.120 9.860 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 69.045 9.860 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 69.000 9.905 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 *C 69.000 11.515 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 *C 68.955 11.560 +*N mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 *C 46.782 11.560 + +*CAP +0 mux_bottom_track_9\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_9\/BUFT_RR_41:A 1e-06 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 5.575599e-05 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0004854796 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0005031234 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0006671469 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0006220693 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.000106248 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.000106248 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.001447825 +10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.001447825 + +*RES +0 mux_bottom_track_9\/mux_l2_in_0_:X mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 0.152 +1 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_9\/BUFT_RR_41:A 0.152 +2 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.008995536 +3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:6 0.0045 +4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0045 +5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0014375 +6 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:10 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:9 0.01979688 +7 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0006071429 +8 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.006982144 +9 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_9/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0003035715 + +*END + +*D_NET optlc_net_107 0.0136808 //LENGTH 106.700 LUMPCC 0.001833766 DR + +*CONN +*I optlc_104:HI O *L 0 *C 78.200 15.300 +*I mux_bottom_track_23\/mux_l2_in_0_:A0 I *L 0.001631 *C 81.250 11.900 +*I mux_bottom_track_37\/mux_l2_in_0_:A0 I *L 0.001631 *C 82.630 22.780 +*I mux_bottom_track_39\/mux_l2_in_0_:A0 I *L 0.001631 *C 86.310 26.180 +*I mux_bottom_track_21\/mux_l2_in_0_:A0 I *L 0.001631 *C 66.875 15.640 +*I mux_bottom_track_9\/mux_l1_in_1_:A0 I *L 0.001631 *C 41.115 17.000 +*I mux_bottom_track_11\/mux_l2_in_0_:A0 I *L 0.001631 *C 58.595 9.860 +*I mux_bottom_track_7\/mux_l2_in_1_:A0 I *L 0.001631 *C 33.295 9.860 +*N optlc_net_107:8 *C 33.295 9.860 +*N optlc_net_107:9 *C 33.580 9.860 +*N optlc_net_107:10 *C 33.580 9.815 +*N optlc_net_107:11 *C 33.580 6.857 +*N optlc_net_107:12 *C 33.587 6.800 +*N optlc_net_107:13 *C 51.513 6.800 +*N optlc_net_107:14 *C 51.520 6.857 +*N optlc_net_107:15 *C 51.520 9.815 +*N optlc_net_107:16 *C 51.565 9.860 +*N optlc_net_107:17 *C 58.595 9.860 +*N optlc_net_107:18 *C 59.295 9.860 +*N optlc_net_107:19 *C 59.340 9.905 +*N optlc_net_107:20 *C 41.153 17.000 +*N optlc_net_107:21 *C 58.835 17.000 +*N optlc_net_107:22 *C 58.880 16.955 +*N optlc_net_107:23 *C 58.880 15.640 +*N optlc_net_107:24 *C 59.340 15.595 +*N optlc_net_107:25 *C 59.385 15.640 +*N optlc_net_107:26 *C 66.875 15.640 +*N optlc_net_107:27 *C 78.200 15.640 +*N optlc_net_107:28 *C 86.310 26.180 +*N optlc_net_107:29 *C 86.020 26.180 +*N optlc_net_107:30 *C 86.020 26.135 +*N optlc_net_107:31 *C 86.020 22.825 +*N optlc_net_107:32 *C 85.975 22.780 +*N optlc_net_107:33 *C 82.630 22.780 +*N optlc_net_107:34 *C 81.925 22.780 +*N optlc_net_107:35 *C 81.880 22.735 +*N optlc_net_107:36 *C 81.880 20.105 +*N optlc_net_107:37 *C 81.835 20.060 +*N optlc_net_107:38 *C 78.245 20.060 +*N optlc_net_107:39 *C 78.200 20.015 +*N optlc_net_107:40 *C 81.213 11.900 +*N optlc_net_107:41 *C 78.245 11.900 +*N optlc_net_107:42 *C 78.200 11.945 +*N optlc_net_107:43 *C 78.200 15.300 +*N optlc_net_107:44 *C 78.200 15.300 + +*CAP +0 optlc_104:HI 1e-06 +1 mux_bottom_track_23\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_37\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_39\/mux_l2_in_0_:A0 1e-06 +4 mux_bottom_track_21\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_track_9\/mux_l1_in_1_:A0 1e-06 +6 mux_bottom_track_11\/mux_l2_in_0_:A0 1e-06 +7 mux_bottom_track_7\/mux_l2_in_1_:A0 1e-06 +8 optlc_net_107:8 5.036746e-05 +9 optlc_net_107:9 5.713849e-05 +10 optlc_net_107:10 0.0001790893 +11 optlc_net_107:11 0.0001790893 +12 optlc_net_107:12 0.0009406023 +13 optlc_net_107:13 0.0009406023 +14 optlc_net_107:14 0.0001944801 +15 optlc_net_107:15 0.0001944801 +16 optlc_net_107:16 0.0004416685 +17 optlc_net_107:17 0.0005191079 +18 optlc_net_107:18 4.654507e-05 +19 optlc_net_107:19 0.0002659248 +20 optlc_net_107:20 0.001017421 +21 optlc_net_107:21 0.001017421 +22 optlc_net_107:22 6.484569e-05 +23 optlc_net_107:23 9.677779e-05 +24 optlc_net_107:24 0.000297857 +25 optlc_net_107:25 0.0005061937 +26 optlc_net_107:26 0.001167623 +27 optlc_net_107:27 0.0006627919 +28 optlc_net_107:28 4.770216e-05 +29 optlc_net_107:29 5.234519e-05 +30 optlc_net_107:30 0.0001861951 +31 optlc_net_107:31 0.0001861951 +32 optlc_net_107:32 0.0002082972 +33 optlc_net_107:33 0.0002931238 +34 optlc_net_107:34 5.465518e-05 +35 optlc_net_107:35 0.0001338338 +36 optlc_net_107:36 0.0001338338 +37 optlc_net_107:37 0.0002006305 +38 optlc_net_107:38 0.0002006305 +39 optlc_net_107:39 0.0002264822 +40 optlc_net_107:40 0.0002010043 +41 optlc_net_107:41 0.0002010043 +42 optlc_net_107:42 0.0001759225 +43 optlc_net_107:43 0.0004337322 +44 optlc_net_107:44 6.341506e-05 +45 optlc_net_107:35 mux_tree_tapbuf_size2_6_sram[1]:5 7.068236e-05 +46 optlc_net_107:35 mux_tree_tapbuf_size2_6_sram[1]:7 1.604548e-06 +47 optlc_net_107:37 mux_tree_tapbuf_size2_6_sram[1]:6 2.773932e-05 +48 optlc_net_107:36 mux_tree_tapbuf_size2_6_sram[1]:6 7.068236e-05 +49 optlc_net_107:36 mux_tree_tapbuf_size2_6_sram[1]:10 1.604548e-06 +50 optlc_net_107:38 mux_tree_tapbuf_size2_6_sram[1]:7 2.773932e-05 +51 optlc_net_107:39 mux_tree_tapbuf_size2_6_sram[1]:7 1.323616e-05 +52 optlc_net_107:39 mux_tree_tapbuf_size2_6_sram[1]:10 1.087347e-05 +53 optlc_net_107:43 mux_tree_tapbuf_size2_6_sram[1]:9 1.087347e-05 +54 optlc_net_107:43 mux_tree_tapbuf_size2_6_sram[1]:10 2.308879e-05 +55 optlc_net_107:42 mux_tree_tapbuf_size2_6_sram[1]:9 9.852629e-06 +56 optlc_net_107:21 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003873938 +57 optlc_net_107:22 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 4.2772e-05 +58 optlc_net_107:20 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0003873938 +59 optlc_net_107:18 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 8.641549e-06 +60 optlc_net_107:19 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 6.458754e-05 +61 optlc_net_107:24 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:5 6.458754e-05 +62 optlc_net_107:17 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.462111e-06 +63 optlc_net_107:17 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 8.641549e-06 +64 optlc_net_107:16 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.462111e-06 +65 optlc_net_107:23 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_0_X[0]:4 4.2772e-05 +66 optlc_net_107:13 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001792383 +67 optlc_net_107:12 mux_bottom_track_15/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001792383 +68 optlc_net_107:26 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 9.479914e-05 +69 optlc_net_107:27 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.479914e-05 + +*RES +0 optlc_104:HI optlc_net_107:44 0.152 +1 optlc_net_107:21 optlc_net_107:20 0.01578795 +2 optlc_net_107:22 optlc_net_107:21 0.0045 +3 optlc_net_107:20 mux_bottom_track_9\/mux_l1_in_1_:A0 0.152 +4 optlc_net_107:18 optlc_net_107:17 0.000625 +5 optlc_net_107:19 optlc_net_107:18 0.0045 +6 optlc_net_107:34 optlc_net_107:33 0.0006294643 +7 optlc_net_107:35 optlc_net_107:34 0.0045 +8 optlc_net_107:37 optlc_net_107:36 0.0045 +9 optlc_net_107:36 optlc_net_107:35 0.002348214 +10 optlc_net_107:38 optlc_net_107:37 0.003205357 +11 optlc_net_107:39 optlc_net_107:38 0.0045 +12 optlc_net_107:44 optlc_net_107:43 0.0045 +13 optlc_net_107:44 optlc_net_107:27 0.0003035715 +14 optlc_net_107:43 optlc_net_107:42 0.002995536 +15 optlc_net_107:43 optlc_net_107:39 0.004209822 +16 optlc_net_107:25 optlc_net_107:24 0.0045 +17 optlc_net_107:24 optlc_net_107:23 0.0004107143 +18 optlc_net_107:24 optlc_net_107:19 0.005080357 +19 optlc_net_107:41 optlc_net_107:40 0.002649554 +20 optlc_net_107:42 optlc_net_107:41 0.0045 +21 optlc_net_107:40 mux_bottom_track_23\/mux_l2_in_0_:A0 0.152 +22 optlc_net_107:26 mux_bottom_track_21\/mux_l2_in_0_:A0 0.152 +23 optlc_net_107:26 optlc_net_107:25 0.006687501 +24 optlc_net_107:32 optlc_net_107:31 0.0045 +25 optlc_net_107:31 optlc_net_107:30 0.002955357 +26 optlc_net_107:29 optlc_net_107:28 0.0001576087 +27 optlc_net_107:30 optlc_net_107:29 0.0045 +28 optlc_net_107:28 mux_bottom_track_39\/mux_l2_in_0_:A0 0.152 +29 optlc_net_107:33 mux_bottom_track_37\/mux_l2_in_0_:A0 0.152 +30 optlc_net_107:33 optlc_net_107:32 0.002986607 +31 optlc_net_107:17 mux_bottom_track_11\/mux_l2_in_0_:A0 0.152 +32 optlc_net_107:17 optlc_net_107:16 0.006276787 +33 optlc_net_107:16 optlc_net_107:15 0.0045 +34 optlc_net_107:15 optlc_net_107:14 0.002640625 +35 optlc_net_107:14 optlc_net_107:13 0.00341 +36 optlc_net_107:13 optlc_net_107:12 0.00280825 +37 optlc_net_107:11 optlc_net_107:10 0.002640625 +38 optlc_net_107:12 optlc_net_107:11 0.00341 +39 optlc_net_107:9 optlc_net_107:8 0.0001548913 +40 optlc_net_107:10 optlc_net_107:9 0.0045 +41 optlc_net_107:8 mux_bottom_track_7\/mux_l2_in_1_:A0 0.152 +42 optlc_net_107:27 optlc_net_107:26 0.01011161 +43 optlc_net_107:23 optlc_net_107:22 0.001174107 + +*END + +*D_NET mux_bottom_track_29/BUF_net_44 0.0006185588 //LENGTH 6.080 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_29\/BUFT_RR_44:X O *L 0 *C 91.775 14.280 +*I mux_bottom_track_29\/BUFT_P_84:A I *L 0.001746 *C 91.080 9.520 +*N mux_bottom_track_29/BUF_net_44:2 *C 91.080 9.520 +*N mux_bottom_track_29/BUF_net_44:3 *C 91.080 9.565 +*N mux_bottom_track_29/BUF_net_44:4 *C 91.080 14.235 +*N mux_bottom_track_29/BUF_net_44:5 *C 91.125 14.280 +*N mux_bottom_track_29/BUF_net_44:6 *C 91.738 14.280 + +*CAP +0 mux_bottom_track_29\/BUFT_RR_44:X 1e-06 +1 mux_bottom_track_29\/BUFT_P_84:A 1e-06 +2 mux_bottom_track_29/BUF_net_44:2 3.110532e-05 +3 mux_bottom_track_29/BUF_net_44:3 0.0002331173 +4 mux_bottom_track_29/BUF_net_44:4 0.0002331173 +5 mux_bottom_track_29/BUF_net_44:5 5.960941e-05 +6 mux_bottom_track_29/BUF_net_44:6 5.960941e-05 + +*RES +0 mux_bottom_track_29\/BUFT_RR_44:X mux_bottom_track_29/BUF_net_44:6 0.152 +1 mux_bottom_track_29/BUF_net_44:2 mux_bottom_track_29\/BUFT_P_84:A 0.152 +2 mux_bottom_track_29/BUF_net_44:3 mux_bottom_track_29/BUF_net_44:2 0.0045 +3 mux_bottom_track_29/BUF_net_44:5 mux_bottom_track_29/BUF_net_44:4 0.0045 +4 mux_bottom_track_29/BUF_net_44:4 mux_bottom_track_29/BUF_net_44:3 0.004169643 +5 mux_bottom_track_29/BUF_net_44:6 mux_bottom_track_29/BUF_net_44:5 0.000546875 + +*END + +*D_NET chanx_left_out[1] 0.000711999 //LENGTH 5.765 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_754:X O *L 0 *C 4.140 95.880 +*P chanx_left_out[1] O *L 0.7423 *C 1.230 93.840 +*N chanx_left_out[1]:2 *C 2.752 93.840 +*N chanx_left_out[1]:3 *C 2.760 93.898 +*N chanx_left_out[1]:4 *C 2.760 95.835 +*N chanx_left_out[1]:5 *C 2.805 95.880 +*N chanx_left_out[1]:6 *C 4.103 95.880 + +*CAP +0 ropt_mt_inst_754:X 1e-06 +1 chanx_left_out[1] 0.0001067403 +2 chanx_left_out[1]:2 0.0001067403 +3 chanx_left_out[1]:3 0.0001197582 +4 chanx_left_out[1]:4 0.0001197582 +5 chanx_left_out[1]:5 0.000129001 +6 chanx_left_out[1]:6 0.000129001 + +*RES +0 ropt_mt_inst_754:X chanx_left_out[1]:6 0.152 +1 chanx_left_out[1]:6 chanx_left_out[1]:5 0.001158482 +2 chanx_left_out[1]:5 chanx_left_out[1]:4 0.0045 +3 chanx_left_out[1]:4 chanx_left_out[1]:3 0.001729911 +4 chanx_left_out[1]:3 chanx_left_out[1]:2 0.00341 +5 chanx_left_out[1]:2 chanx_left_out[1] 0.000238525 + +*END + +*D_NET chany_bottom_out[0] 0.0008333169 //LENGTH 5.870 LUMPCC 0.0004779253 DR + +*CONN +*I ropt_mt_inst_764:X O *L 0 *C 86.215 3.740 +*P chany_bottom_out[0] O *L 0.7423 *C 83.260 1.290 +*N chany_bottom_out[0]:2 *C 83.260 3.695 +*N chany_bottom_out[0]:3 *C 83.305 3.740 +*N chany_bottom_out[0]:4 *C 86.178 3.740 + +*CAP +0 ropt_mt_inst_764:X 1e-06 +1 chany_bottom_out[0] 0.0001429199 +2 chany_bottom_out[0]:2 0.0001429199 +3 chany_bottom_out[0]:3 3.427594e-05 +4 chany_bottom_out[0]:4 3.427594e-05 +5 chany_bottom_out[0]:4 ropt_net_115:2 9.871904e-05 +6 chany_bottom_out[0]:4 ropt_net_115:4 4.407281e-06 +7 chany_bottom_out[0]:3 ropt_net_115:3 9.871904e-05 +8 chany_bottom_out[0]:3 ropt_net_115:5 4.407281e-06 +9 chany_bottom_out[0] ropt_net_145:5 1.728653e-05 +10 chany_bottom_out[0]:4 ropt_net_145:7 0.0001185498 +11 chany_bottom_out[0]:3 ropt_net_145:6 0.0001185498 +12 chany_bottom_out[0]:2 ropt_net_145:4 1.728653e-05 + +*RES +0 ropt_mt_inst_764:X chany_bottom_out[0]:4 0.152 +1 chany_bottom_out[0]:4 chany_bottom_out[0]:3 0.002564732 +2 chany_bottom_out[0]:3 chany_bottom_out[0]:2 0.0045 +3 chany_bottom_out[0]:2 chany_bottom_out[0] 0.002147322 + +*END + +*D_NET chany_bottom_in[9] 0.01906485 //LENGTH 186.545 LUMPCC 0.001939495 DR + +*CONN +*P chany_bottom_in[9] I *L 0.29796 *C 84.180 1.290 +*I ropt_mt_inst_734:A I *L 0.001767 *C 3.220 99.280 +*N chany_bottom_in[9]:2 *C 3.183 99.280 +*N chany_bottom_in[9]:3 *C 1.425 99.280 +*N chany_bottom_in[9]:4 *C 1.380 99.235 +*N chany_bottom_in[9]:5 *C 1.380 96.265 +*N chany_bottom_in[9]:6 *C 1.425 96.220 +*N chany_bottom_in[9]:7 *C 21.160 96.220 +*N chany_bottom_in[9]:8 *C 21.085 95.880 +*N chany_bottom_in[9]:9 *C 21.152 95.925 +*N chany_bottom_in[9]:10 *C 21.160 96.515 +*N chany_bottom_in[9]:11 *C 21.205 96.560 +*N chany_bottom_in[9]:12 *C 73.095 96.560 +*N chany_bottom_in[9]:13 *C 73.140 96.515 +*N chany_bottom_in[9]:14 *C 73.140 61.375 +*N chany_bottom_in[9]:15 *C 73.140 11.617 +*N chany_bottom_in[9]:16 *C 73.148 11.560 +*N chany_bottom_in[9]:17 *C 84.172 11.560 +*N chany_bottom_in[9]:18 *C 84.180 11.503 + +*CAP +0 chany_bottom_in[9] 0.0005588433 +1 ropt_mt_inst_734:A 1e-06 +2 chany_bottom_in[9]:2 0.0001055389 +3 chany_bottom_in[9]:3 0.0001055389 +4 chany_bottom_in[9]:4 0.0001642846 +5 chany_bottom_in[9]:5 0.0001642846 +6 chany_bottom_in[9]:6 0.001042852 +7 chany_bottom_in[9]:7 0.001067638 +8 chany_bottom_in[9]:8 5.300027e-05 +9 chany_bottom_in[9]:9 4.880275e-05 +10 chany_bottom_in[9]:10 4.880275e-05 +11 chany_bottom_in[9]:11 0.002517086 +12 chany_bottom_in[9]:12 0.002517086 +13 chany_bottom_in[9]:13 0.001413469 +14 chany_bottom_in[9]:14 0.003381589 +15 chany_bottom_in[9]:15 0.00196812 +16 chany_bottom_in[9]:16 0.0007042912 +17 chany_bottom_in[9]:17 0.0007042912 +18 chany_bottom_in[9]:18 0.0005588433 +19 chany_bottom_in[9]:13 chanx_left_in[19]:6 0.0001372452 +20 chany_bottom_in[9]:13 chanx_left_in[19]:5 0.0001451162 +21 chany_bottom_in[9]:15 chanx_left_in[19]:4 0.0005037216 +22 chany_bottom_in[9]:14 chanx_left_in[19]:4 0.0001451162 +23 chany_bottom_in[9]:14 chanx_left_in[19]:5 0.0006409668 +24 chany_bottom_in[9]:15 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:5 0.0001136622 +25 chany_bottom_in[9]:14 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:4 0.0001136622 +26 chany_bottom_in[9]:6 ropt_net_138:3 7.000229e-05 +27 chany_bottom_in[9]:7 ropt_net_138:4 7.000229e-05 + +*RES +0 chany_bottom_in[9] chany_bottom_in[9]:18 0.009118305 +1 chany_bottom_in[9]:2 ropt_mt_inst_734:A 0.152 +2 chany_bottom_in[9]:3 chany_bottom_in[9]:2 0.001569197 +3 chany_bottom_in[9]:4 chany_bottom_in[9]:3 0.0045 +4 chany_bottom_in[9]:6 chany_bottom_in[9]:5 0.0045 +5 chany_bottom_in[9]:5 chany_bottom_in[9]:4 0.002651786 +6 chany_bottom_in[9]:8 chany_bottom_in[9]:7 0.0003035715 +7 chany_bottom_in[9]:9 chany_bottom_in[9]:8 0.0045 +8 chany_bottom_in[9]:11 chany_bottom_in[9]:10 0.0045 +9 chany_bottom_in[9]:10 chany_bottom_in[9]:9 0.0005267857 +10 chany_bottom_in[9]:12 chany_bottom_in[9]:11 0.04633036 +11 chany_bottom_in[9]:13 chany_bottom_in[9]:12 0.0045 +12 chany_bottom_in[9]:15 chany_bottom_in[9]:14 0.04442634 +13 chany_bottom_in[9]:16 chany_bottom_in[9]:15 0.00341 +14 chany_bottom_in[9]:18 chany_bottom_in[9]:17 0.00341 +15 chany_bottom_in[9]:17 chany_bottom_in[9]:16 0.00172725 +16 chany_bottom_in[9]:7 chany_bottom_in[9]:6 0.01762054 +17 chany_bottom_in[9]:14 chany_bottom_in[9]:13 0.031375 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_12_ccff_tail[0] 0.001843619 //LENGTH 15.140 LUMPCC 0.0003863134 DR + +*CONN +*I mem_bottom_track_37\/FTB_19__34:X O *L 0 *C 77.045 28.560 +*I mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.495 26.180 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 *C 65.532 26.180 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 *C 66.195 26.180 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 *C 66.240 26.225 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 *C 66.240 28.175 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 *C 66.285 28.220 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 *C 76.360 28.220 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 *C 76.360 28.560 +*N mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 *C 77.008 28.560 + +*CAP +0 mem_bottom_track_37\/FTB_19__34:X 1e-06 +1 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 6.755284e-05 +3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 6.755284e-05 +4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 0.00013137 +5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 0.00013137 +6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 0.000462997 +7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 0.0004902751 +8 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 6.573298e-05 +9 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 3.845485e-05 +10 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 1.301526e-05 +11 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 0.0001801414 +12 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:7 0.0001801414 +13 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_6_ccff_tail[0]:6 1.301526e-05 + +*RES +0 mem_bottom_track_37\/FTB_19__34:X mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 0.152 +1 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:9 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 0.000578125 +2 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 0.0005915179 +5 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:2 mem_bottom_track_39\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:6 0.008995537 +8 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_12_ccff_tail[0]:7 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[0] 0.002687257 //LENGTH 21.020 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 45.845 9.860 +*I mux_bottom_track_9\/mux_l1_in_1_:S I *L 0.00357 *C 42.220 17.680 +*I mux_bottom_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 39.920 15.035 +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 48.935 9.860 +*N mux_tree_tapbuf_size3_0_sram[0]:4 *C 48.935 9.860 +*N mux_tree_tapbuf_size3_0_sram[0]:5 *C 48.760 10.200 +*N mux_tree_tapbuf_size3_0_sram[0]:6 *C 39.920 15.035 +*N mux_tree_tapbuf_size3_0_sram[0]:7 *C 42.183 17.680 +*N mux_tree_tapbuf_size3_0_sram[0]:8 *C 40.525 17.680 +*N mux_tree_tapbuf_size3_0_sram[0]:9 *C 40.480 17.635 +*N mux_tree_tapbuf_size3_0_sram[0]:10 *C 40.480 15.005 +*N mux_tree_tapbuf_size3_0_sram[0]:11 *C 40.480 14.960 +*N mux_tree_tapbuf_size3_0_sram[0]:12 *C 45.035 14.960 +*N mux_tree_tapbuf_size3_0_sram[0]:13 *C 45.080 14.915 +*N mux_tree_tapbuf_size3_0_sram[0]:14 *C 45.080 10.245 +*N mux_tree_tapbuf_size3_0_sram[0]:15 *C 45.125 10.200 +*N mux_tree_tapbuf_size3_0_sram[0]:16 *C 45.540 10.200 +*N mux_tree_tapbuf_size3_0_sram[0]:17 *C 45.540 9.895 +*N mux_tree_tapbuf_size3_0_sram[0]:18 *C 45.818 9.883 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_9\/mux_l1_in_1_:S 1e-06 +2 mux_bottom_track_9\/mux_l1_in_0_:S 1e-06 +3 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +4 mux_tree_tapbuf_size3_0_sram[0]:4 5.727234e-05 +5 mux_tree_tapbuf_size3_0_sram[0]:5 0.0002715038 +6 mux_tree_tapbuf_size3_0_sram[0]:6 0.0001059709 +7 mux_tree_tapbuf_size3_0_sram[0]:7 0.0001427438 +8 mux_tree_tapbuf_size3_0_sram[0]:8 0.0001427438 +9 mux_tree_tapbuf_size3_0_sram[0]:9 0.0001679985 +10 mux_tree_tapbuf_size3_0_sram[0]:10 0.0001679985 +11 mux_tree_tapbuf_size3_0_sram[0]:11 0.0003655348 +12 mux_tree_tapbuf_size3_0_sram[0]:12 0.0002809775 +13 mux_tree_tapbuf_size3_0_sram[0]:13 0.0002742072 +14 mux_tree_tapbuf_size3_0_sram[0]:14 0.0002742072 +15 mux_tree_tapbuf_size3_0_sram[0]:15 4.638054e-05 +16 mux_tree_tapbuf_size3_0_sram[0]:16 0.0003183286 +17 mux_tree_tapbuf_size3_0_sram[0]:17 4.661068e-05 +18 mux_tree_tapbuf_size3_0_sram[0]:18 2.077872e-05 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size3_0_sram[0]:18 0.152 +1 mux_tree_tapbuf_size3_0_sram[0]:4 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +2 mux_tree_tapbuf_size3_0_sram[0]:12 mux_tree_tapbuf_size3_0_sram[0]:11 0.004066965 +3 mux_tree_tapbuf_size3_0_sram[0]:13 mux_tree_tapbuf_size3_0_sram[0]:12 0.0045 +4 mux_tree_tapbuf_size3_0_sram[0]:15 mux_tree_tapbuf_size3_0_sram[0]:14 0.0045 +5 mux_tree_tapbuf_size3_0_sram[0]:14 mux_tree_tapbuf_size3_0_sram[0]:13 0.004169643 +6 mux_tree_tapbuf_size3_0_sram[0]:18 mux_tree_tapbuf_size3_0_sram[0]:17 0.0001875 +7 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:10 0.0045 +8 mux_tree_tapbuf_size3_0_sram[0]:11 mux_tree_tapbuf_size3_0_sram[0]:6 0.0005 +9 mux_tree_tapbuf_size3_0_sram[0]:10 mux_tree_tapbuf_size3_0_sram[0]:9 0.002348214 +10 mux_tree_tapbuf_size3_0_sram[0]:8 mux_tree_tapbuf_size3_0_sram[0]:7 0.001479911 +11 mux_tree_tapbuf_size3_0_sram[0]:9 mux_tree_tapbuf_size3_0_sram[0]:8 0.0045 +12 mux_tree_tapbuf_size3_0_sram[0]:7 mux_bottom_track_9\/mux_l1_in_1_:S 0.152 +13 mux_tree_tapbuf_size3_0_sram[0]:6 mux_bottom_track_9\/mux_l1_in_0_:S 0.152 +14 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:15 0.0003705357 +15 mux_tree_tapbuf_size3_0_sram[0]:16 mux_tree_tapbuf_size3_0_sram[0]:5 0.002875 +16 mux_tree_tapbuf_size3_0_sram[0]:5 mux_tree_tapbuf_size3_0_sram[0]:4 0.0003035715 +17 mux_tree_tapbuf_size3_0_sram[0]:17 mux_tree_tapbuf_size3_0_sram[0]:16 0.0002723215 + +*END + +*D_NET mux_tree_tapbuf_size6_0_sram[0] 0.006564302 //LENGTH 54.600 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 23.765 71.740 +*I mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 21.335 47.940 +*I mux_bottom_track_1\/mux_l1_in_2_:S I *L 0.00357 *C 20.800 45.175 +*I mux_bottom_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 26.320 34.295 +*I mux_bottom_track_1\/mux_l1_in_1_:S I *L 0.00357 *C 28.160 31.280 +*N mux_tree_tapbuf_size6_0_sram[0]:5 *C 28.060 31.280 +*N mux_tree_tapbuf_size6_0_sram[0]:6 *C 28.060 31.325 +*N mux_tree_tapbuf_size6_0_sram[0]:7 *C 28.060 33.955 +*N mux_tree_tapbuf_size6_0_sram[0]:8 *C 28.015 34.000 +*N mux_tree_tapbuf_size6_0_sram[0]:9 *C 26.320 34.295 +*N mux_tree_tapbuf_size6_0_sram[0]:10 *C 26.358 34.000 +*N mux_tree_tapbuf_size6_0_sram[0]:11 *C 26.220 34.045 +*N mux_tree_tapbuf_size6_0_sram[0]:12 *C 26.220 45.515 +*N mux_tree_tapbuf_size6_0_sram[0]:13 *C 26.175 45.560 +*N mux_tree_tapbuf_size6_0_sram[0]:14 *C 20.800 45.175 +*N mux_tree_tapbuf_size6_0_sram[0]:15 *C 20.800 45.560 +*N mux_tree_tapbuf_size6_0_sram[0]:16 *C 20.700 45.605 +*N mux_tree_tapbuf_size6_0_sram[0]:17 *C 20.700 47.895 +*N mux_tree_tapbuf_size6_0_sram[0]:18 *C 20.745 47.940 +*N mux_tree_tapbuf_size6_0_sram[0]:19 *C 21.335 47.940 +*N mux_tree_tapbuf_size6_0_sram[0]:20 *C 22.955 47.940 +*N mux_tree_tapbuf_size6_0_sram[0]:21 *C 23.000 47.985 +*N mux_tree_tapbuf_size6_0_sram[0]:22 *C 23.000 71.695 +*N mux_tree_tapbuf_size6_0_sram[0]:23 *C 23.045 71.740 +*N mux_tree_tapbuf_size6_0_sram[0]:24 *C 23.728 71.740 + +*CAP +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_bottom_track_1\/mux_l1_in_2_:S 1e-06 +3 mux_bottom_track_1\/mux_l1_in_0_:S 1e-06 +4 mux_bottom_track_1\/mux_l1_in_1_:S 1e-06 +5 mux_tree_tapbuf_size6_0_sram[0]:5 3.391005e-05 +6 mux_tree_tapbuf_size6_0_sram[0]:6 0.0001708077 +7 mux_tree_tapbuf_size6_0_sram[0]:7 0.0001708077 +8 mux_tree_tapbuf_size6_0_sram[0]:8 0.0001816549 +9 mux_tree_tapbuf_size6_0_sram[0]:9 6.818374e-05 +10 mux_tree_tapbuf_size6_0_sram[0]:10 0.0002184741 +11 mux_tree_tapbuf_size6_0_sram[0]:11 0.0006844541 +12 mux_tree_tapbuf_size6_0_sram[0]:12 0.0006844541 +13 mux_tree_tapbuf_size6_0_sram[0]:13 0.0004124222 +14 mux_tree_tapbuf_size6_0_sram[0]:14 6.306637e-05 +15 mux_tree_tapbuf_size6_0_sram[0]:15 0.0004462598 +16 mux_tree_tapbuf_size6_0_sram[0]:16 0.0001557032 +17 mux_tree_tapbuf_size6_0_sram[0]:17 0.0001557032 +18 mux_tree_tapbuf_size6_0_sram[0]:18 4.801346e-05 +19 mux_tree_tapbuf_size6_0_sram[0]:19 0.0001875639 +20 mux_tree_tapbuf_size6_0_sram[0]:20 0.0001108465 +21 mux_tree_tapbuf_size6_0_sram[0]:21 0.001326674 +22 mux_tree_tapbuf_size6_0_sram[0]:22 0.001326674 +23 mux_tree_tapbuf_size6_0_sram[0]:23 5.681474e-05 +24 mux_tree_tapbuf_size6_0_sram[0]:24 5.681474e-05 + +*RES +0 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size6_0_sram[0]:24 0.152 +1 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:9 0.0001271552 +2 mux_tree_tapbuf_size6_0_sram[0]:10 mux_tree_tapbuf_size6_0_sram[0]:8 0.001479911 +3 mux_tree_tapbuf_size6_0_sram[0]:11 mux_tree_tapbuf_size6_0_sram[0]:10 0.0045 +4 mux_tree_tapbuf_size6_0_sram[0]:13 mux_tree_tapbuf_size6_0_sram[0]:12 0.0045 +5 mux_tree_tapbuf_size6_0_sram[0]:12 mux_tree_tapbuf_size6_0_sram[0]:11 0.01024107 +6 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:14 0.0003437501 +7 mux_tree_tapbuf_size6_0_sram[0]:15 mux_tree_tapbuf_size6_0_sram[0]:13 0.004799108 +8 mux_tree_tapbuf_size6_0_sram[0]:16 mux_tree_tapbuf_size6_0_sram[0]:15 0.0045 +9 mux_tree_tapbuf_size6_0_sram[0]:18 mux_tree_tapbuf_size6_0_sram[0]:17 0.0045 +10 mux_tree_tapbuf_size6_0_sram[0]:17 mux_tree_tapbuf_size6_0_sram[0]:16 0.002044643 +11 mux_tree_tapbuf_size6_0_sram[0]:19 mem_bottom_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +12 mux_tree_tapbuf_size6_0_sram[0]:19 mux_tree_tapbuf_size6_0_sram[0]:18 0.0005267857 +13 mux_tree_tapbuf_size6_0_sram[0]:20 mux_tree_tapbuf_size6_0_sram[0]:19 0.001446429 +14 mux_tree_tapbuf_size6_0_sram[0]:21 mux_tree_tapbuf_size6_0_sram[0]:20 0.0045 +15 mux_tree_tapbuf_size6_0_sram[0]:23 mux_tree_tapbuf_size6_0_sram[0]:22 0.0045 +16 mux_tree_tapbuf_size6_0_sram[0]:22 mux_tree_tapbuf_size6_0_sram[0]:21 0.02116964 +17 mux_tree_tapbuf_size6_0_sram[0]:24 mux_tree_tapbuf_size6_0_sram[0]:23 0.000609375 +18 mux_tree_tapbuf_size6_0_sram[0]:14 mux_bottom_track_1\/mux_l1_in_2_:S 0.152 +19 mux_tree_tapbuf_size6_0_sram[0]:8 mux_tree_tapbuf_size6_0_sram[0]:7 0.0045 +20 mux_tree_tapbuf_size6_0_sram[0]:7 mux_tree_tapbuf_size6_0_sram[0]:6 0.002348214 +21 mux_tree_tapbuf_size6_0_sram[0]:5 mux_bottom_track_1\/mux_l1_in_1_:S 0.152 +22 mux_tree_tapbuf_size6_0_sram[0]:6 mux_tree_tapbuf_size6_0_sram[0]:5 0.0045 +23 mux_tree_tapbuf_size6_0_sram[0]:9 mux_bottom_track_1\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0006567106 //LENGTH 4.400 LUMPCC 0.000244287 DR + +*CONN +*I mux_bottom_track_3\/mux_l1_in_0_:X O *L 0 *C 22.255 31.280 +*I mux_bottom_track_3\/mux_l2_in_0_:A1 I *L 0.00198 *C 18.765 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 18.803 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 21.160 30.940 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 21.160 31.280 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 22.218 31.280 + +*CAP +0 mux_bottom_track_3\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_3\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001020166 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001235486 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001031952 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 8.166319e-05 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 bottom_left_grid_pin_34_[0]:9 9.985056e-05 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_34_[0]:10 5.399591e-06 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_34_[0]:12 1.49202e-05 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_left_grid_pin_34_[0]:10 0.0001018237 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_34_[0]:9 5.399591e-06 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_34_[0]:11 1.689334e-05 + +*RES +0 mux_bottom_track_3\/mux_l1_in_0_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_3\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0009441964 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002104911 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0] 0.003724932 //LENGTH 25.885 LUMPCC 0.000349101 DR + +*CONN +*I mux_bottom_track_7\/mux_l3_in_0_:X O *L 0 *C 38.925 6.120 +*I mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 63.865 6.635 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 *C 63.865 6.598 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 *C 63.865 6.120 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 *C 38.962 6.120 + +*CAP +0 mux_bottom_track_7\/mux_l3_in_0_:X 1e-06 +1 mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 4.261135e-05 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.001686915 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.001644304 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:6 0.0001745505 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_tree_tapbuf_size5_mem_1_ccff_tail[0]:7 0.0001745505 + +*RES +0 mux_bottom_track_7\/mux_l3_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 mux_bottom_track_7\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 0.02223438 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_4_X[0]:2 0.0004263392 + +*END + +*D_NET mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008270638 //LENGTH 7.145 LUMPCC 0.0001014254 DR + +*CONN +*I mux_bottom_track_13\/mux_l1_in_0_:X O *L 0 *C 35.245 66.300 +*I mux_bottom_track_13\/mux_l2_in_0_:A1 I *L 0.00198 *C 38.740 63.580 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 38.703 63.580 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 36.385 63.580 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 36.340 63.625 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 36.340 66.255 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 36.295 66.300 +*N mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 35.282 66.300 + +*CAP +0 mux_bottom_track_13\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_13\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0001338527 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001338527 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001492475 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001492475 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 7.871905e-05 +7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 7.871905e-05 +8 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_tree_tapbuf_size2_2_sram[0]:9 3.86529e-05 +9 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_2_sram[0]:8 3.86529e-05 +10 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_2_sram[0]:6 1.205983e-05 +11 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_2_sram[0]:7 1.205983e-05 + +*RES +0 mux_bottom_track_13\/mux_l1_in_0_:X mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_13\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.002069197 +3 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002348214 +6 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0009040179 + +*END + +*D_NET mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001056422 //LENGTH 8.355 LUMPCC 0.0003313504 DR + +*CONN +*I mux_bottom_track_21\/mux_l1_in_0_:X O *L 0 *C 67.445 20.740 +*I mux_bottom_track_21\/mux_l2_in_0_:A1 I *L 0.00198 *C 67.260 14.620 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 67.222 14.620 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 66.745 14.620 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 66.700 14.665 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 66.700 20.695 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 66.745 20.740 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 67.407 20.740 + +*CAP +0 mux_bottom_track_21\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_21\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.168116e-05 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.168116e-05 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002466945 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0002466945 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 6.316011e-05 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 6.316011e-05 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001656752 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_13/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001656752 + +*RES +0 mux_bottom_track_21\/mux_l1_in_0_:X mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_21\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0004263393 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0045 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005383929 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0005915179 + +*END + +*D_NET optlc_net_108 0.007595601 //LENGTH 61.620 LUMPCC 0.001454243 DR + +*CONN +*I optlc_106:HI O *L 0 *C 50.140 47.940 +*I mux_bottom_track_35\/mux_l2_in_0_:A0 I *L 0.001631 *C 51.235 27.880 +*I mux_left_track_5\/mux_l2_in_0_:A0 I *L 0.001631 *C 59.170 27.880 +*I mux_bottom_track_19\/mux_l2_in_0_:A0 I *L 0.001631 *C 46.175 26.180 +*I mux_bottom_track_17\/mux_l2_in_0_:A0 I *L 0.001631 *C 36.055 47.940 +*I mux_bottom_track_33\/mux_l2_in_0_:A0 I *L 0.001631 *C 28.235 44.540 +*N optlc_net_108:6 *C 28.235 44.540 +*N optlc_net_108:7 *C 28.520 44.540 +*N optlc_net_108:8 *C 28.520 44.585 +*N optlc_net_108:9 *C 28.520 47.895 +*N optlc_net_108:10 *C 28.565 47.940 +*N optlc_net_108:11 *C 36.055 47.940 +*N optlc_net_108:12 *C 46.213 26.180 +*N optlc_net_108:13 *C 47.335 26.180 +*N optlc_net_108:14 *C 47.380 26.225 +*N optlc_net_108:15 *C 59.133 27.880 +*N optlc_net_108:16 *C 51.235 27.880 +*N optlc_net_108:17 *C 47.425 27.880 +*N optlc_net_108:18 *C 47.380 27.880 +*N optlc_net_108:19 *C 47.380 47.895 +*N optlc_net_108:20 *C 47.380 47.940 +*N optlc_net_108:21 *C 50.102 47.940 + +*CAP +0 optlc_106:HI 1e-06 +1 mux_bottom_track_35\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_5\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_19\/mux_l2_in_0_:A0 1e-06 +4 mux_bottom_track_17\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_track_33\/mux_l2_in_0_:A0 1e-06 +6 optlc_net_108:6 5.559782e-05 +7 optlc_net_108:7 6.365332e-05 +8 optlc_net_108:8 0.0002176141 +9 optlc_net_108:9 0.0002176141 +10 optlc_net_108:10 0.0004418361 +11 optlc_net_108:11 0.0009300764 +12 optlc_net_108:12 9.604841e-05 +13 optlc_net_108:13 9.604841e-05 +14 optlc_net_108:14 7.481287e-05 +15 optlc_net_108:15 0.0004567887 +16 optlc_net_108:16 0.0007458334 +17 optlc_net_108:17 0.00026003 +18 optlc_net_108:18 0.000939495 +19 optlc_net_108:19 0.0008307721 +20 optlc_net_108:20 0.0005990436 +21 optlc_net_108:21 0.0001100939 +22 optlc_net_108:18 mux_tree_tapbuf_size2_11_sram[0]:5 8.288732e-05 +23 optlc_net_108:18 mux_tree_tapbuf_size2_11_sram[0]:8 6.856012e-05 +24 optlc_net_108:19 mux_tree_tapbuf_size2_11_sram[0]:8 8.288732e-05 +25 optlc_net_108:19 mux_tree_tapbuf_size2_11_sram[0]:9 6.856012e-05 +26 optlc_net_108:20 mux_tree_tapbuf_size2_3_sram[1]:4 5.654363e-05 +27 optlc_net_108:20 mux_tree_tapbuf_size2_3_sram[1]:5 0.0001954663 +28 optlc_net_108:21 mux_tree_tapbuf_size2_3_sram[1]:5 5.654363e-05 +29 optlc_net_108:11 mux_tree_tapbuf_size2_3_sram[1]:4 0.0001954663 +30 optlc_net_108:14 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 2.334331e-05 +31 optlc_net_108:18 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001651301 +32 optlc_net_108:18 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 2.334331e-05 +33 optlc_net_108:19 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001651301 +34 optlc_net_108:15 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001351905 +35 optlc_net_108:16 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001351905 + +*RES +0 optlc_106:HI optlc_net_108:21 0.152 +1 optlc_net_108:13 optlc_net_108:12 0.001002232 +2 optlc_net_108:14 optlc_net_108:13 0.0045 +3 optlc_net_108:12 mux_bottom_track_19\/mux_l2_in_0_:A0 0.152 +4 optlc_net_108:17 optlc_net_108:16 0.003401786 +5 optlc_net_108:18 optlc_net_108:17 0.0045 +6 optlc_net_108:18 optlc_net_108:14 0.001477679 +7 optlc_net_108:20 optlc_net_108:19 0.0045 +8 optlc_net_108:20 optlc_net_108:11 0.01011161 +9 optlc_net_108:19 optlc_net_108:18 0.01787054 +10 optlc_net_108:21 optlc_net_108:20 0.002430804 +11 optlc_net_108:15 mux_left_track_5\/mux_l2_in_0_:A0 0.152 +12 optlc_net_108:11 mux_bottom_track_17\/mux_l2_in_0_:A0 0.152 +13 optlc_net_108:11 optlc_net_108:10 0.0066875 +14 optlc_net_108:16 mux_bottom_track_35\/mux_l2_in_0_:A0 0.152 +15 optlc_net_108:16 optlc_net_108:15 0.007051339 +16 optlc_net_108:10 optlc_net_108:9 0.0045 +17 optlc_net_108:9 optlc_net_108:8 0.002955357 +18 optlc_net_108:7 optlc_net_108:6 0.0001548913 +19 optlc_net_108:8 optlc_net_108:7 0.0045 +20 optlc_net_108:6 mux_bottom_track_33\/mux_l2_in_0_:A0 0.152 + +*END + +*D_NET chany_bottom_in[10] 0.01660578 //LENGTH 151.685 LUMPCC 0.003951645 DR + +*CONN +*P chany_bottom_in[10] I *L 0.29796 *C 62.560 1.290 +*I ropt_mt_inst_725:A I *L 0.001766 *C 7.820 93.840 +*N chany_bottom_in[10]:2 *C 7.820 93.840 +*N chany_bottom_in[10]:3 *C 7.820 93.500 +*N chany_bottom_in[10]:4 *C 23.415 93.500 +*N chany_bottom_in[10]:5 *C 23.460 93.455 +*N chany_bottom_in[10]:6 *C 23.460 83.005 +*N chany_bottom_in[10]:7 *C 23.505 82.960 +*N chany_bottom_in[10]:8 *C 24.380 82.960 +*N chany_bottom_in[10]:9 *C 24.380 83.640 +*N chany_bottom_in[10]:10 *C 28.520 83.640 +*N chany_bottom_in[10]:11 *C 28.520 83.300 +*N chany_bottom_in[10]:12 *C 62.055 83.300 +*N chany_bottom_in[10]:13 *C 62.100 83.255 +*N chany_bottom_in[10]:14 *C 62.100 51.970 +*N chany_bottom_in[10]:15 *C 62.100 2.040 +*N chany_bottom_in[10]:16 *C 62.560 2.040 + +*CAP +0 chany_bottom_in[10] 5.632406e-05 +1 ropt_mt_inst_725:A 1e-06 +2 chany_bottom_in[10]:2 6.193396e-05 +3 chany_bottom_in[10]:3 0.0008026235 +4 chany_bottom_in[10]:4 0.0007725643 +5 chany_bottom_in[10]:5 0.0004483378 +6 chany_bottom_in[10]:6 0.0004483378 +7 chany_bottom_in[10]:7 5.810674e-05 +8 chany_bottom_in[10]:8 9.791397e-05 +9 chany_bottom_in[10]:9 0.0002940152 +10 chany_bottom_in[10]:10 0.0002830792 +11 chany_bottom_in[10]:11 0.001299944 +12 chany_bottom_in[10]:12 0.001271072 +13 chany_bottom_in[10]:13 0.001482886 +14 chany_bottom_in[10]:14 0.003321516 +15 chany_bottom_in[10]:15 0.001868394 +16 chany_bottom_in[10]:16 8.608729e-05 +17 chany_bottom_in[10]:5 chany_bottom_in[0]:4 3.89766e-05 +18 chany_bottom_in[10]:6 chany_bottom_in[0]:5 3.89766e-05 +19 chany_bottom_in[10]:12 chany_bottom_in[0]:9 0.0006577841 +20 chany_bottom_in[10]:9 chany_bottom_in[0]:6 3.254965e-05 +21 chany_bottom_in[10]:9 chany_bottom_in[0]:8 1.730588e-06 +22 chany_bottom_in[10]:10 chany_bottom_in[0]:7 3.254965e-05 +23 chany_bottom_in[10]:10 chany_bottom_in[0]:9 1.730588e-06 +24 chany_bottom_in[10]:11 chany_bottom_in[0]:8 0.0006577841 +25 chany_bottom_in[10]:15 mux_tree_tapbuf_size2_0_sram[1]:8 7.25431e-05 +26 chany_bottom_in[10]:15 mux_tree_tapbuf_size2_0_sram[1]:5 8.038932e-05 +27 chany_bottom_in[10]:14 mux_tree_tapbuf_size2_0_sram[1]:8 8.038932e-05 +28 chany_bottom_in[10]:14 mux_tree_tapbuf_size2_0_sram[1]:9 7.25431e-05 +29 chany_bottom_in[10]:13 mux_tree_tapbuf_size2_15_sram[1]:14 2.758617e-05 +30 chany_bottom_in[10]:15 mux_tree_tapbuf_size2_15_sram[1]:13 0.000305486 +31 chany_bottom_in[10]:14 mux_tree_tapbuf_size2_15_sram[1]:14 0.000305486 +32 chany_bottom_in[10]:14 mux_tree_tapbuf_size2_15_sram[1]:13 2.758617e-05 +33 chany_bottom_in[10]:13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 1.677857e-05 +34 chany_bottom_in[10]:15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0004816456 +35 chany_bottom_in[10]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004816456 +36 chany_bottom_in[10]:14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_1_X[0]:4 1.677857e-05 +37 chany_bottom_in[10]:2 ropt_net_134:4 6.78945e-08 +38 chany_bottom_in[10]:4 ropt_net_134:5 6.80357e-05 +39 chany_bottom_in[10]:3 ropt_net_134:3 6.78945e-08 +40 chany_bottom_in[10]:3 ropt_net_134:4 6.80357e-05 +41 chany_bottom_in[10]:4 ropt_net_132:11 0.0001922489 +42 chany_bottom_in[10]:3 ropt_net_132:10 0.0001922489 + +*RES +0 chany_bottom_in[10] chany_bottom_in[10]:16 0.0006696429 +1 chany_bottom_in[10]:2 ropt_mt_inst_725:A 0.152 +2 chany_bottom_in[10]:4 chany_bottom_in[10]:3 0.01392411 +3 chany_bottom_in[10]:5 chany_bottom_in[10]:4 0.0045 +4 chany_bottom_in[10]:7 chany_bottom_in[10]:6 0.0045 +5 chany_bottom_in[10]:6 chany_bottom_in[10]:5 0.009330357 +6 chany_bottom_in[10]:12 chany_bottom_in[10]:11 0.02994197 +7 chany_bottom_in[10]:13 chany_bottom_in[10]:12 0.0045 +8 chany_bottom_in[10]:3 chany_bottom_in[10]:2 0.0003035715 +9 chany_bottom_in[10]:8 chany_bottom_in[10]:7 0.00078125 +10 chany_bottom_in[10]:9 chany_bottom_in[10]:8 0.0006071429 +11 chany_bottom_in[10]:10 chany_bottom_in[10]:9 0.003696429 +12 chany_bottom_in[10]:11 chany_bottom_in[10]:10 0.0003035715 +13 chany_bottom_in[10]:15 chany_bottom_in[10]:14 0.04458036 +14 chany_bottom_in[10]:16 chany_bottom_in[10]:15 0.0004107143 +15 chany_bottom_in[10]:14 chany_bottom_in[10]:13 0.02793304 + +*END + +*D_NET chanx_left_in[13] 0.003084905 //LENGTH 25.585 LUMPCC 0.0001781511 DR + +*CONN +*P chanx_left_in[13] I *L 0.29796 *C 1.230 74.800 +*I mux_bottom_track_25\/mux_l1_in_1_:A1 I *L 0.00198 *C 9.200 58.140 +*N chanx_left_in[13]:2 *C 9.178 58.168 +*N chanx_left_in[13]:3 *C 9.165 58.480 +*N chanx_left_in[13]:4 *C 5.105 58.480 +*N chanx_left_in[13]:5 *C 5.060 58.525 +*N chanx_left_in[13]:6 *C 5.060 74.743 +*N chanx_left_in[13]:7 *C 5.053 74.800 + +*CAP +0 chanx_left_in[13] 0.0002683046 +1 mux_bottom_track_25\/mux_l1_in_1_:A1 1e-06 +2 chanx_left_in[13]:2 3.469087e-05 +3 chanx_left_in[13]:3 0.0003610883 +4 chanx_left_in[13]:4 0.0003263975 +5 chanx_left_in[13]:5 0.0008234839 +6 chanx_left_in[13]:6 0.0008234839 +7 chanx_left_in[13]:7 0.0002683046 +8 chanx_left_in[13]:6 ropt_net_125:4 8.907553e-05 +9 chanx_left_in[13]:5 ropt_net_125:5 8.907553e-05 + +*RES +0 chanx_left_in[13] chanx_left_in[13]:7 0.0005988583 +1 chanx_left_in[13]:6 chanx_left_in[13]:5 0.01447991 +2 chanx_left_in[13]:7 chanx_left_in[13]:6 0.00341 +3 chanx_left_in[13]:4 chanx_left_in[13]:3 0.003625 +4 chanx_left_in[13]:5 chanx_left_in[13]:4 0.0045 +5 chanx_left_in[13]:2 mux_bottom_track_25\/mux_l1_in_1_:A1 0.152 +6 chanx_left_in[13]:3 chanx_left_in[13]:2 0.0002111487 + +*END + +*D_NET chanx_left_in[18] 0.007717989 //LENGTH 35.655 LUMPCC 0.005434358 DR + +*CONN +*P chanx_left_in[18] I *L 0.29796 *C 1.230 38.080 +*I mux_bottom_track_35\/mux_l1_in_0_:A0 I *L 0.001631 *C 35.135 37.400 +*N chanx_left_in[18]:2 *C 35.098 37.400 +*N chanx_left_in[18]:3 *C 29.025 37.400 +*N chanx_left_in[18]:4 *C 28.980 37.400 +*N chanx_left_in[18]:5 *C 28.973 37.400 +*N chanx_left_in[18]:6 *C 2.760 37.400 +*N chanx_left_in[18]:7 *C 2.760 38.080 + +*CAP +0 chanx_left_in[18] 5.224034e-05 +1 mux_bottom_track_35\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[18]:2 0.0004275823 +3 chanx_left_in[18]:3 0.0004275823 +4 chanx_left_in[18]:4 3.914596e-05 +5 chanx_left_in[18]:5 0.000597445 +6 chanx_left_in[18]:6 0.0006419196 +7 chanx_left_in[18]:7 9.671506e-05 +8 chanx_left_in[18] chanx_left_in[0]:12 0.0001081598 +9 chanx_left_in[18]:5 chanx_left_in[0]:11 0.0001779517 +10 chanx_left_in[18]:7 chanx_left_in[0]:11 0.0001081598 +11 chanx_left_in[18]:6 chanx_left_in[0]:12 0.0001779517 +12 chanx_left_in[18] chanx_left_in[10] 2.742029e-05 +13 chanx_left_in[18]:5 chanx_left_in[10]:6 0.001487702 +14 chanx_left_in[18]:7 chanx_left_in[10]:6 2.742029e-05 +15 chanx_left_in[18]:6 chanx_left_in[10] 0.001487702 +16 chanx_left_in[18]:5 optlc_net_109:21 0.0001331963 +17 chanx_left_in[18]:5 optlc_net_109:20 0.0007827498 +18 chanx_left_in[18]:6 optlc_net_109:15 0.0007827498 +19 chanx_left_in[18]:6 optlc_net_109:20 0.0001331963 + +*RES +0 chanx_left_in[18] chanx_left_in[18]:7 0.0002397 +1 chanx_left_in[18]:2 mux_bottom_track_35\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[18]:3 chanx_left_in[18]:2 0.005421875 +3 chanx_left_in[18]:4 chanx_left_in[18]:3 0.0045 +4 chanx_left_in[18]:5 chanx_left_in[18]:4 0.00341 +5 chanx_left_in[18]:7 chanx_left_in[18]:6 0.0001065333 +6 chanx_left_in[18]:6 chanx_left_in[18]:5 0.004106625 + +*END + +*D_NET chany_bottom_out[8] 0.001076184 //LENGTH 8.470 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 60.720 6.460 +*P chany_bottom_out[8] O *L 0.7423 *C 63.480 1.325 +*N chany_bottom_out[8]:2 *C 63.480 6.460 +*N chany_bottom_out[8]:3 *C 63.020 6.460 +*N chany_bottom_out[8]:4 *C 62.975 6.460 +*N chany_bottom_out[8]:5 *C 60.758 6.460 + +*CAP +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[8] 0.0002844169 +2 chany_bottom_out[8]:2 0.0003149739 +3 chany_bottom_out[8]:3 5.909019e-05 +4 chany_bottom_out[8]:4 0.0002083513 +5 chany_bottom_out[8]:5 0.0002083513 + +*RES +0 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[8]:5 0.152 +1 chany_bottom_out[8]:4 chany_bottom_out[8]:3 0.0045 +2 chany_bottom_out[8]:3 chany_bottom_out[8]:2 0.0004107143 +3 chany_bottom_out[8]:5 chany_bottom_out[8]:4 0.001979911 +4 chany_bottom_out[8]:2 chany_bottom_out[8] 0.004584821 + +*END + +*D_NET chany_bottom_out[17] 0.0004876911 //LENGTH 4.115 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X O *L 0 *C 58.020 4.080 +*P chany_bottom_out[17] O *L 0.7423 *C 58.880 1.290 +*N chany_bottom_out[17]:2 *C 58.880 4.035 +*N chany_bottom_out[17]:3 *C 58.835 4.080 +*N chany_bottom_out[17]:4 *C 58.058 4.080 + +*CAP +0 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X 1e-06 +1 chany_bottom_out[17] 0.0001648283 +2 chany_bottom_out[17]:2 0.0001648283 +3 chany_bottom_out[17]:3 7.851723e-05 +4 chany_bottom_out[17]:4 7.851723e-05 + +*RES +0 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:X chany_bottom_out[17]:4 0.152 +1 chany_bottom_out[17]:4 chany_bottom_out[17]:3 0.0006941964 +2 chany_bottom_out[17]:3 chany_bottom_out[17]:2 0.0045 +3 chany_bottom_out[17]:2 chany_bottom_out[17] 0.002450893 + +*END + +*D_NET mux_tree_tapbuf_size2_11_sram[1] 0.002831072 //LENGTH 22.375 LUMPCC 0.0007271003 DR + +*CONN +*I mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 52.745 33.660 +*I mux_bottom_track_35\/mux_l2_in_0_:S I *L 0.00357 *C 52.340 28.560 +*I mem_bottom_track_35\/FTB_18__33:A I *L 0.001746 *C 55.200 14.960 +*N mux_tree_tapbuf_size2_11_sram[1]:3 *C 55.163 14.960 +*N mux_tree_tapbuf_size2_11_sram[1]:4 *C 52.485 14.960 +*N mux_tree_tapbuf_size2_11_sram[1]:5 *C 52.440 15.005 +*N mux_tree_tapbuf_size2_11_sram[1]:6 *C 52.340 28.560 +*N mux_tree_tapbuf_size2_11_sram[1]:7 *C 52.440 28.560 +*N mux_tree_tapbuf_size2_11_sram[1]:8 *C 52.440 33.615 +*N mux_tree_tapbuf_size2_11_sram[1]:9 *C 52.440 33.660 +*N mux_tree_tapbuf_size2_11_sram[1]:10 *C 52.745 33.660 + +*CAP +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_35\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_35\/FTB_18__33:A 1e-06 +3 mux_tree_tapbuf_size2_11_sram[1]:3 0.0001407751 +4 mux_tree_tapbuf_size2_11_sram[1]:4 0.0001407751 +5 mux_tree_tapbuf_size2_11_sram[1]:5 0.0005948406 +6 mux_tree_tapbuf_size2_11_sram[1]:6 3.347502e-05 +7 mux_tree_tapbuf_size2_11_sram[1]:7 0.0008591149 +8 mux_tree_tapbuf_size2_11_sram[1]:8 0.0002302316 +9 mux_tree_tapbuf_size2_11_sram[1]:9 5.448711e-05 +10 mux_tree_tapbuf_size2_11_sram[1]:10 4.727197e-05 +11 mux_tree_tapbuf_size2_11_sram[1]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 7.80306e-05 +12 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0001004734 +13 mux_tree_tapbuf_size2_11_sram[1]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 7.80306e-05 +14 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 6.035134e-05 +15 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.0001004734 +16 mux_tree_tapbuf_size2_11_sram[1]:8 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 6.035134e-05 +17 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0001246948 +18 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0001246948 + +*RES +0 mem_bottom_track_35\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_11_sram[1]:10 0.152 +1 mux_tree_tapbuf_size2_11_sram[1]:4 mux_tree_tapbuf_size2_11_sram[1]:3 0.002390625 +2 mux_tree_tapbuf_size2_11_sram[1]:5 mux_tree_tapbuf_size2_11_sram[1]:4 0.0045 +3 mux_tree_tapbuf_size2_11_sram[1]:3 mem_bottom_track_35\/FTB_18__33:A 0.152 +4 mux_tree_tapbuf_size2_11_sram[1]:6 mux_bottom_track_35\/mux_l2_in_0_:S 0.152 +5 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_11_sram[1]:6 0.0045 +6 mux_tree_tapbuf_size2_11_sram[1]:7 mux_tree_tapbuf_size2_11_sram[1]:5 0.01210268 +7 mux_tree_tapbuf_size2_11_sram[1]:9 mux_tree_tapbuf_size2_11_sram[1]:8 0.0045 +8 mux_tree_tapbuf_size2_11_sram[1]:8 mux_tree_tapbuf_size2_11_sram[1]:7 0.004513393 +9 mux_tree_tapbuf_size2_11_sram[1]:10 mux_tree_tapbuf_size2_11_sram[1]:9 0.0001657609 + +*END + +*D_NET mux_tree_tapbuf_size2_16_sram[0] 0.004198337 //LENGTH 34.085 LUMPCC 0.0004350144 DR + +*CONN +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 79.425 66.640 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 58.595 71.740 +*I mux_left_track_9\/mux_l1_in_0_:S I *L 0.00357 *C 77.640 63.630 +*N mux_tree_tapbuf_size2_16_sram[0]:3 *C 77.640 63.630 +*N mux_tree_tapbuf_size2_16_sram[0]:4 *C 77.670 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:5 *C 58.633 71.740 +*N mux_tree_tapbuf_size2_16_sram[0]:6 *C 59.340 71.740 +*N mux_tree_tapbuf_size2_16_sram[0]:7 *C 59.340 71.400 +*N mux_tree_tapbuf_size2_16_sram[0]:8 *C 75.395 71.400 +*N mux_tree_tapbuf_size2_16_sram[0]:9 *C 75.440 71.355 +*N mux_tree_tapbuf_size2_16_sram[0]:10 *C 75.440 63.965 +*N mux_tree_tapbuf_size2_16_sram[0]:11 *C 75.485 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:12 *C 77.583 63.920 +*N mux_tree_tapbuf_size2_16_sram[0]:13 *C 77.670 63.850 +*N mux_tree_tapbuf_size2_16_sram[0]:14 *C 77.785 63.990 +*N mux_tree_tapbuf_size2_16_sram[0]:15 *C 77.740 64.600 +*N mux_tree_tapbuf_size2_16_sram[0]:16 *C 79.075 64.600 +*N mux_tree_tapbuf_size2_16_sram[0]:17 *C 79.120 64.645 +*N mux_tree_tapbuf_size2_16_sram[0]:18 *C 79.120 66.595 +*N mux_tree_tapbuf_size2_16_sram[0]:19 *C 79.120 66.640 +*N mux_tree_tapbuf_size2_16_sram[0]:20 *C 79.425 66.640 + +*CAP +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_16_sram[0]:3 5.208658e-05 +4 mux_tree_tapbuf_size2_16_sram[0]:4 1.258798e-05 +5 mux_tree_tapbuf_size2_16_sram[0]:5 7.12125e-05 +6 mux_tree_tapbuf_size2_16_sram[0]:6 9.356611e-05 +7 mux_tree_tapbuf_size2_16_sram[0]:7 0.0008572088 +8 mux_tree_tapbuf_size2_16_sram[0]:8 0.0008348552 +9 mux_tree_tapbuf_size2_16_sram[0]:9 0.0004149203 +10 mux_tree_tapbuf_size2_16_sram[0]:10 0.0004149203 +11 mux_tree_tapbuf_size2_16_sram[0]:11 0.0001447314 +12 mux_tree_tapbuf_size2_16_sram[0]:12 0.0001823253 +13 mux_tree_tapbuf_size2_16_sram[0]:13 9.99706e-06 +14 mux_tree_tapbuf_size2_16_sram[0]:14 4.79129e-05 +15 mux_tree_tapbuf_size2_16_sram[0]:15 0.000150552 +16 mux_tree_tapbuf_size2_16_sram[0]:16 0.0001120176 +17 mux_tree_tapbuf_size2_16_sram[0]:17 0.0001247554 +18 mux_tree_tapbuf_size2_16_sram[0]:18 0.0001247554 +19 mux_tree_tapbuf_size2_16_sram[0]:19 5.811955e-05 +20 mux_tree_tapbuf_size2_16_sram[0]:20 5.379826e-05 +21 mux_tree_tapbuf_size2_16_sram[0]:8 mux_tree_tapbuf_size2_16_sram[1]:6 0.0002117465 +22 mux_tree_tapbuf_size2_16_sram[0]:8 mux_tree_tapbuf_size2_16_sram[1]:11 5.760693e-06 +23 mux_tree_tapbuf_size2_16_sram[0]:7 mux_tree_tapbuf_size2_16_sram[1]:12 5.760693e-06 +24 mux_tree_tapbuf_size2_16_sram[0]:7 mux_tree_tapbuf_size2_16_sram[1]:11 0.0002117465 + +*RES +0 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_16_sram[0]:20 0.152 +1 mux_tree_tapbuf_size2_16_sram[0]:11 mux_tree_tapbuf_size2_16_sram[0]:10 0.0045 +2 mux_tree_tapbuf_size2_16_sram[0]:10 mux_tree_tapbuf_size2_16_sram[0]:9 0.006598215 +3 mux_tree_tapbuf_size2_16_sram[0]:8 mux_tree_tapbuf_size2_16_sram[0]:7 0.01433482 +4 mux_tree_tapbuf_size2_16_sram[0]:9 mux_tree_tapbuf_size2_16_sram[0]:8 0.0045 +5 mux_tree_tapbuf_size2_16_sram[0]:5 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +6 mux_tree_tapbuf_size2_16_sram[0]:3 mux_left_track_9\/mux_l1_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_16_sram[0]:16 mux_tree_tapbuf_size2_16_sram[0]:15 0.001191964 +8 mux_tree_tapbuf_size2_16_sram[0]:17 mux_tree_tapbuf_size2_16_sram[0]:16 0.0045 +9 mux_tree_tapbuf_size2_16_sram[0]:19 mux_tree_tapbuf_size2_16_sram[0]:18 0.0045 +10 mux_tree_tapbuf_size2_16_sram[0]:18 mux_tree_tapbuf_size2_16_sram[0]:17 0.001741072 +11 mux_tree_tapbuf_size2_16_sram[0]:20 mux_tree_tapbuf_size2_16_sram[0]:19 0.0001657609 +12 mux_tree_tapbuf_size2_16_sram[0]:6 mux_tree_tapbuf_size2_16_sram[0]:5 0.0006316964 +13 mux_tree_tapbuf_size2_16_sram[0]:7 mux_tree_tapbuf_size2_16_sram[0]:6 0.0003035714 +14 mux_tree_tapbuf_size2_16_sram[0]:12 mux_tree_tapbuf_size2_16_sram[0]:11 0.001872768 +15 mux_tree_tapbuf_size2_16_sram[0]:12 mux_tree_tapbuf_size2_16_sram[0]:4 7.812501e-05 +16 mux_tree_tapbuf_size2_16_sram[0]:12 mux_tree_tapbuf_size2_16_sram[0]:3 0.000125 +17 mux_tree_tapbuf_size2_16_sram[0]:13 mux_tree_tapbuf_size2_16_sram[0]:12 3.017242e-05 +18 mux_tree_tapbuf_size2_16_sram[0]:14 mux_tree_tapbuf_size2_16_sram[0]:13 0.0001026786 +19 mux_tree_tapbuf_size2_16_sram[0]:15 mux_tree_tapbuf_size2_16_sram[0]:14 0.0005446429 + +*END + +*D_NET mux_tree_tapbuf_size2_7_sram[0] 0.002054878 //LENGTH 16.225 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 17.785 55.760 +*I mux_bottom_track_27\/mux_l1_in_0_:S I *L 0.00357 *C 15.080 50.660 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 13.975 60.860 +*N mux_tree_tapbuf_size2_7_sram[0]:3 *C 14.013 60.860 +*N mux_tree_tapbuf_size2_7_sram[0]:4 *C 14.675 60.860 +*N mux_tree_tapbuf_size2_7_sram[0]:5 *C 14.720 60.815 +*N mux_tree_tapbuf_size2_7_sram[0]:6 *C 15.065 50.660 +*N mux_tree_tapbuf_size2_7_sram[0]:7 *C 14.743 50.660 +*N mux_tree_tapbuf_size2_7_sram[0]:8 *C 14.720 50.705 +*N mux_tree_tapbuf_size2_7_sram[0]:9 *C 14.720 55.420 +*N mux_tree_tapbuf_size2_7_sram[0]:10 *C 14.765 55.420 +*N mux_tree_tapbuf_size2_7_sram[0]:11 *C 16.560 55.420 +*N mux_tree_tapbuf_size2_7_sram[0]:12 *C 16.560 55.760 +*N mux_tree_tapbuf_size2_7_sram[0]:13 *C 17.748 55.760 + +*CAP +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_27\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_7_sram[0]:3 7.446069e-05 +4 mux_tree_tapbuf_size2_7_sram[0]:4 7.446069e-05 +5 mux_tree_tapbuf_size2_7_sram[0]:5 0.0003083843 +6 mux_tree_tapbuf_size2_7_sram[0]:6 6.092709e-05 +7 mux_tree_tapbuf_size2_7_sram[0]:7 6.092709e-05 +8 mux_tree_tapbuf_size2_7_sram[0]:8 0.0002713182 +9 mux_tree_tapbuf_size2_7_sram[0]:9 0.0006137876 +10 mux_tree_tapbuf_size2_7_sram[0]:10 0.0001541254 +11 mux_tree_tapbuf_size2_7_sram[0]:11 0.0001807966 +12 mux_tree_tapbuf_size2_7_sram[0]:12 0.0001396806 +13 mux_tree_tapbuf_size2_7_sram[0]:13 0.0001130094 + +*RES +0 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_7_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_7_sram[0]:6 mux_bottom_track_27\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_7_sram[0]:7 mux_tree_tapbuf_size2_7_sram[0]:6 0.0001752718 +3 mux_tree_tapbuf_size2_7_sram[0]:8 mux_tree_tapbuf_size2_7_sram[0]:7 0.0045 +4 mux_tree_tapbuf_size2_7_sram[0]:4 mux_tree_tapbuf_size2_7_sram[0]:3 0.0005915179 +5 mux_tree_tapbuf_size2_7_sram[0]:5 mux_tree_tapbuf_size2_7_sram[0]:4 0.0045 +6 mux_tree_tapbuf_size2_7_sram[0]:3 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_7_sram[0]:10 mux_tree_tapbuf_size2_7_sram[0]:9 0.0045 +8 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:8 0.004209822 +9 mux_tree_tapbuf_size2_7_sram[0]:9 mux_tree_tapbuf_size2_7_sram[0]:5 0.004816964 +10 mux_tree_tapbuf_size2_7_sram[0]:13 mux_tree_tapbuf_size2_7_sram[0]:12 0.001060268 +11 mux_tree_tapbuf_size2_7_sram[0]:11 mux_tree_tapbuf_size2_7_sram[0]:10 0.001602679 +12 mux_tree_tapbuf_size2_7_sram[0]:12 mux_tree_tapbuf_size2_7_sram[0]:11 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_15_ccff_tail[0] 0.002702154 //LENGTH 24.480 LUMPCC 0 DR + +*CONN +*I mem_left_track_5\/FTB_22__37:X O *L 0 *C 92.685 61.880 +*I mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 73.775 66.300 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 *C 73.812 66.300 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 *C 92.875 66.300 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 *C 92.920 66.255 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 *C 92.920 61.925 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 *C 92.920 61.880 +*N mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 *C 92.685 61.880 + +*CAP +0 mem_left_track_5\/FTB_22__37:X 1e-06 +1 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 0.001098137 +3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 0.001098137 +4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 0.0002041542 +5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 0.0002041542 +6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 5.005686e-05 +7 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 4.551442e-05 + +*RES +0 mem_left_track_5\/FTB_22__37:X mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 0.0001277174 +2 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 0.003866072 +4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 0.01702009 +5 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_15_ccff_tail[0]:2 mem_left_track_9\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size3_0_sram[1] 0.001841055 //LENGTH 14.125 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 54.585 9.520 +*I mem_bottom_track_9\/FTB_5__20:A I *L 0.001746 *C 52.900 12.240 +*I mux_bottom_track_9\/mux_l2_in_0_:S I *L 0.00357 *C 45.900 12.240 +*N mux_tree_tapbuf_size3_0_sram[1]:3 *C 45.863 12.240 +*N mux_tree_tapbuf_size3_0_sram[1]:4 *C 45.540 12.240 +*N mux_tree_tapbuf_size3_0_sram[1]:5 *C 45.540 12.580 +*N mux_tree_tapbuf_size3_0_sram[1]:6 *C 52.900 12.580 +*N mux_tree_tapbuf_size3_0_sram[1]:7 *C 52.900 12.240 +*N mux_tree_tapbuf_size3_0_sram[1]:8 *C 52.900 12.195 +*N mux_tree_tapbuf_size3_0_sram[1]:9 *C 52.900 9.565 +*N mux_tree_tapbuf_size3_0_sram[1]:10 *C 52.945 9.520 +*N mux_tree_tapbuf_size3_0_sram[1]:11 *C 54.547 9.520 + +*CAP +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_9\/FTB_5__20:A 1e-06 +2 mux_bottom_track_9\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size3_0_sram[1]:3 2.39774e-05 +4 mux_tree_tapbuf_size3_0_sram[1]:4 4.980936e-05 +5 mux_tree_tapbuf_size3_0_sram[1]:5 0.0005268519 +6 mux_tree_tapbuf_size3_0_sram[1]:6 0.0005303016 +7 mux_tree_tapbuf_size3_0_sram[1]:7 6.375024e-05 +8 mux_tree_tapbuf_size3_0_sram[1]:8 0.0001602168 +9 mux_tree_tapbuf_size3_0_sram[1]:9 0.0001602168 +10 mux_tree_tapbuf_size3_0_sram[1]:10 0.0001614655 +11 mux_tree_tapbuf_size3_0_sram[1]:11 0.0001614655 + +*RES +0 mem_bottom_track_9\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size3_0_sram[1]:11 0.152 +1 mux_tree_tapbuf_size3_0_sram[1]:3 mux_bottom_track_9\/mux_l2_in_0_:S 0.152 +2 mux_tree_tapbuf_size3_0_sram[1]:7 mem_bottom_track_9\/FTB_5__20:A 0.152 +3 mux_tree_tapbuf_size3_0_sram[1]:7 mux_tree_tapbuf_size3_0_sram[1]:6 0.0003035715 +4 mux_tree_tapbuf_size3_0_sram[1]:8 mux_tree_tapbuf_size3_0_sram[1]:7 0.0045 +5 mux_tree_tapbuf_size3_0_sram[1]:10 mux_tree_tapbuf_size3_0_sram[1]:9 0.0045 +6 mux_tree_tapbuf_size3_0_sram[1]:9 mux_tree_tapbuf_size3_0_sram[1]:8 0.002348214 +7 mux_tree_tapbuf_size3_0_sram[1]:11 mux_tree_tapbuf_size3_0_sram[1]:10 0.001430804 +8 mux_tree_tapbuf_size3_0_sram[1]:4 mux_tree_tapbuf_size3_0_sram[1]:3 0.0002879465 +9 mux_tree_tapbuf_size3_0_sram[1]:5 mux_tree_tapbuf_size3_0_sram[1]:4 0.0003035715 +10 mux_tree_tapbuf_size3_0_sram[1]:6 mux_tree_tapbuf_size3_0_sram[1]:5 0.006571429 + +*END + +*D_NET mux_tree_tapbuf_size5_1_sram[1] 0.003380055 //LENGTH 28.955 LUMPCC 0.0004100455 DR + +*CONN +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 42.625 20.740 +*I mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 32.835 4.420 +*I mux_bottom_track_7\/mux_l2_in_1_:S I *L 0.00357 *C 34.400 8.840 +*I mux_bottom_track_7\/mux_l2_in_0_:S I *L 0.00357 *C 35.980 12.535 +*N mux_tree_tapbuf_size5_1_sram[1]:4 *C 35.980 12.535 +*N mux_tree_tapbuf_size5_1_sram[1]:5 *C 32.873 4.420 +*N mux_tree_tapbuf_size5_1_sram[1]:6 *C 34.455 4.420 +*N mux_tree_tapbuf_size5_1_sram[1]:7 *C 34.500 4.465 +*N mux_tree_tapbuf_size5_1_sram[1]:8 *C 34.500 8.795 +*N mux_tree_tapbuf_size5_1_sram[1]:9 *C 34.400 8.840 +*N mux_tree_tapbuf_size5_1_sram[1]:10 *C 34.500 9.180 +*N mux_tree_tapbuf_size5_1_sram[1]:11 *C 35.835 9.180 +*N mux_tree_tapbuf_size5_1_sram[1]:12 *C 35.880 9.225 +*N mux_tree_tapbuf_size5_1_sram[1]:13 *C 35.880 12.195 +*N mux_tree_tapbuf_size5_1_sram[1]:14 *C 36.038 12.240 +*N mux_tree_tapbuf_size5_1_sram[1]:15 *C 38.135 12.240 +*N mux_tree_tapbuf_size5_1_sram[1]:16 *C 38.180 12.285 +*N mux_tree_tapbuf_size5_1_sram[1]:17 *C 38.180 20.695 +*N mux_tree_tapbuf_size5_1_sram[1]:18 *C 38.225 20.740 +*N mux_tree_tapbuf_size5_1_sram[1]:19 *C 42.587 20.740 + +*CAP +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_7\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_track_7\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_1_sram[1]:4 6.431213e-05 +5 mux_tree_tapbuf_size5_1_sram[1]:5 0.0001167278 +6 mux_tree_tapbuf_size5_1_sram[1]:6 0.0001167278 +7 mux_tree_tapbuf_size5_1_sram[1]:7 0.0002023865 +8 mux_tree_tapbuf_size5_1_sram[1]:8 0.0002023865 +9 mux_tree_tapbuf_size5_1_sram[1]:9 6.602003e-05 +10 mux_tree_tapbuf_size5_1_sram[1]:10 0.0001010549 +11 mux_tree_tapbuf_size5_1_sram[1]:11 6.964349e-05 +12 mux_tree_tapbuf_size5_1_sram[1]:12 0.0001423728 +13 mux_tree_tapbuf_size5_1_sram[1]:13 0.0001423728 +14 mux_tree_tapbuf_size5_1_sram[1]:14 0.0001839471 +15 mux_tree_tapbuf_size5_1_sram[1]:15 0.0001492186 +16 mux_tree_tapbuf_size5_1_sram[1]:16 0.0004091024 +17 mux_tree_tapbuf_size5_1_sram[1]:17 0.0004091024 +18 mux_tree_tapbuf_size5_1_sram[1]:18 0.0002953169 +19 mux_tree_tapbuf_size5_1_sram[1]:19 0.0002953169 +20 mux_tree_tapbuf_size5_1_sram[1]:12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 3.192791e-06 +21 mux_tree_tapbuf_size5_1_sram[1]:14 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.375019e-05 +22 mux_tree_tapbuf_size5_1_sram[1]:13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 3.192791e-06 +23 mux_tree_tapbuf_size5_1_sram[1]:15 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.375019e-05 +24 mux_tree_tapbuf_size5_1_sram[1]:16 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:4 6.38551e-05 +25 mux_tree_tapbuf_size5_1_sram[1]:17 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_1_X[0]:5 6.38551e-05 +26 mux_tree_tapbuf_size5_1_sram[1]:12 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 2.978964e-05 +27 mux_tree_tapbuf_size5_1_sram[1]:13 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 2.978964e-05 +28 mux_tree_tapbuf_size5_1_sram[1]:8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 5.437142e-05 +29 mux_tree_tapbuf_size5_1_sram[1]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 5.437142e-05 +30 mux_tree_tapbuf_size5_1_sram[1]:11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:6 3.461917e-05 +31 mux_tree_tapbuf_size5_1_sram[1]:8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:5 5.444449e-06 +32 mux_tree_tapbuf_size5_1_sram[1]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:4 5.444449e-06 +33 mux_tree_tapbuf_size5_1_sram[1]:10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_3_X[0]:7 3.461917e-05 + +*RES +0 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_1_sram[1]:19 0.152 +1 mux_tree_tapbuf_size5_1_sram[1]:11 mux_tree_tapbuf_size5_1_sram[1]:10 0.001191964 +2 mux_tree_tapbuf_size5_1_sram[1]:12 mux_tree_tapbuf_size5_1_sram[1]:11 0.0045 +3 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:13 0.0045 +4 mux_tree_tapbuf_size5_1_sram[1]:14 mux_tree_tapbuf_size5_1_sram[1]:4 0.0001271552 +5 mux_tree_tapbuf_size5_1_sram[1]:13 mux_tree_tapbuf_size5_1_sram[1]:12 0.002651786 +6 mux_tree_tapbuf_size5_1_sram[1]:9 mux_tree_tapbuf_size5_1_sram[1]:8 0.0045 +7 mux_tree_tapbuf_size5_1_sram[1]:9 mux_bottom_track_7\/mux_l2_in_1_:S 0.152 +8 mux_tree_tapbuf_size5_1_sram[1]:8 mux_tree_tapbuf_size5_1_sram[1]:7 0.003866072 +9 mux_tree_tapbuf_size5_1_sram[1]:6 mux_tree_tapbuf_size5_1_sram[1]:5 0.001412946 +10 mux_tree_tapbuf_size5_1_sram[1]:7 mux_tree_tapbuf_size5_1_sram[1]:6 0.0045 +11 mux_tree_tapbuf_size5_1_sram[1]:5 mem_bottom_track_7\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +12 mux_tree_tapbuf_size5_1_sram[1]:15 mux_tree_tapbuf_size5_1_sram[1]:14 0.001872768 +13 mux_tree_tapbuf_size5_1_sram[1]:16 mux_tree_tapbuf_size5_1_sram[1]:15 0.0045 +14 mux_tree_tapbuf_size5_1_sram[1]:18 mux_tree_tapbuf_size5_1_sram[1]:17 0.0045 +15 mux_tree_tapbuf_size5_1_sram[1]:17 mux_tree_tapbuf_size5_1_sram[1]:16 0.007508929 +16 mux_tree_tapbuf_size5_1_sram[1]:19 mux_tree_tapbuf_size5_1_sram[1]:18 0.00389509 +17 mux_tree_tapbuf_size5_1_sram[1]:4 mux_bottom_track_7\/mux_l2_in_0_:S 0.152 +18 mux_tree_tapbuf_size5_1_sram[1]:10 mux_tree_tapbuf_size5_1_sram[1]:9 0.0003035714 + +*END + +*D_NET optlc_net_106 0.02089976 //LENGTH 140.955 LUMPCC 0.0084154 DR + +*CONN +*I optlc_102:HI O *L 0 *C 28.980 55.760 +*I mux_bottom_track_27\/mux_l2_in_0_:A0 I *L 0.001631 *C 18.535 53.720 +*I mux_left_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 17.310 80.580 +*I mux_bottom_track_25\/mux_l1_in_1_:A0 I *L 0.001631 *C 9.370 58.820 +*I mux_bottom_track_31\/mux_l2_in_0_:A0 I *L 0.001631 *C 30.545 49.980 +*I mux_bottom_track_15\/mux_l2_in_0_:A0 I *L 0.001631 *C 36.975 60.520 +*I mux_left_track_9\/mux_l2_in_0_:A0 I *L 0.001631 *C 84.470 60.520 +*I mux_bottom_track_13\/mux_l2_in_0_:A0 I *L 0.001631 *C 38.355 64.600 +*I mux_bottom_track_29\/mux_l2_in_0_:A0 I *L 0.001631 *C 25.935 58.820 +*N optlc_net_106:9 *C 25.973 58.820 +*N optlc_net_106:10 *C 28.520 58.820 +*N optlc_net_106:11 *C 38.318 64.600 +*N optlc_net_106:12 *C 37.765 64.600 +*N optlc_net_106:13 *C 37.720 64.555 +*N optlc_net_106:14 *C 84.508 60.520 +*N optlc_net_106:15 *C 86.435 60.520 +*N optlc_net_106:16 *C 86.480 60.565 +*N optlc_net_106:17 *C 86.480 63.183 +*N optlc_net_106:18 *C 86.473 63.240 +*N optlc_net_106:19 *C 37.727 63.240 +*N optlc_net_106:20 *C 37.720 63.240 +*N optlc_net_106:21 *C 37.720 60.565 +*N optlc_net_106:22 *C 37.675 60.520 +*N optlc_net_106:23 *C 36.975 60.520 +*N optlc_net_106:24 *C 35.925 60.520 +*N optlc_net_106:25 *C 35.880 60.475 +*N optlc_net_106:26 *C 35.880 58.525 +*N optlc_net_106:27 *C 35.835 58.480 +*N optlc_net_106:28 *C 28.520 58.480 +*N optlc_net_106:29 *C 28.520 58.435 +*N optlc_net_106:30 *C 30.508 49.980 +*N optlc_net_106:31 *C 28.565 49.980 +*N optlc_net_106:32 *C 28.520 50.025 +*N optlc_net_106:33 *C 9.370 58.820 +*N optlc_net_106:34 *C 9.660 58.480 +*N optlc_net_106:35 *C 9.660 58.435 +*N optlc_net_106:36 *C 9.660 53.778 +*N optlc_net_106:37 *C 9.668 53.720 +*N optlc_net_106:38 *C 17.310 80.580 +*N optlc_net_106:39 *C 17.480 80.580 +*N optlc_net_106:40 *C 17.480 80.535 +*N optlc_net_106:41 *C 18.498 53.720 +*N optlc_net_106:42 *C 17.525 53.720 +*N optlc_net_106:43 *C 17.480 53.720 +*N optlc_net_106:44 *C 17.480 53.720 +*N optlc_net_106:45 *C 28.513 53.720 +*N optlc_net_106:46 *C 28.520 53.720 +*N optlc_net_106:47 *C 28.520 55.760 +*N optlc_net_106:48 *C 28.565 55.760 +*N optlc_net_106:49 *C 28.943 55.760 + +*CAP +0 optlc_102:HI 1e-06 +1 mux_bottom_track_27\/mux_l2_in_0_:A0 1e-06 +2 mux_left_track_25\/mux_l2_in_0_:A0 1e-06 +3 mux_bottom_track_25\/mux_l1_in_1_:A0 1e-06 +4 mux_bottom_track_31\/mux_l2_in_0_:A0 1e-06 +5 mux_bottom_track_15\/mux_l2_in_0_:A0 1e-06 +6 mux_left_track_9\/mux_l2_in_0_:A0 1e-06 +7 mux_bottom_track_13\/mux_l2_in_0_:A0 1e-06 +8 mux_bottom_track_29\/mux_l2_in_0_:A0 1e-06 +9 optlc_net_106:9 0.0002319977 +10 optlc_net_106:10 0.0002586591 +11 optlc_net_106:11 7.674507e-05 +12 optlc_net_106:12 7.674507e-05 +13 optlc_net_106:13 7.77782e-05 +14 optlc_net_106:14 0.0001873232 +15 optlc_net_106:15 0.0001873232 +16 optlc_net_106:16 0.0001404866 +17 optlc_net_106:17 0.0001404866 +18 optlc_net_106:18 0.001795787 +19 optlc_net_106:19 0.001795787 +20 optlc_net_106:20 0.0002711121 +21 optlc_net_106:21 0.000158104 +22 optlc_net_106:22 5.871457e-05 +23 optlc_net_106:23 0.0001681391 +24 optlc_net_106:24 8.200275e-05 +25 optlc_net_106:25 0.000121831 +26 optlc_net_106:26 0.000121831 +27 optlc_net_106:27 0.0003123229 +28 optlc_net_106:28 0.0003389843 +29 optlc_net_106:29 0.0001543023 +30 optlc_net_106:30 0.000159504 +31 optlc_net_106:31 0.000159504 +32 optlc_net_106:32 0.0001797842 +33 optlc_net_106:33 5.905212e-05 +34 optlc_net_106:34 6.568736e-05 +35 optlc_net_106:35 0.0003351066 +36 optlc_net_106:36 0.0003351066 +37 optlc_net_106:37 0.0001405963 +38 optlc_net_106:38 4.518621e-05 +39 optlc_net_106:39 4.840724e-05 +40 optlc_net_106:40 0.001274942 +41 optlc_net_106:41 8.887517e-05 +42 optlc_net_106:42 8.887517e-05 +43 optlc_net_106:43 0.001310967 +44 optlc_net_106:44 0.000427642 +45 optlc_net_106:45 0.0002870458 +46 optlc_net_106:46 0.0003222665 +47 optlc_net_106:47 0.000295049 +48 optlc_net_106:48 4.76498e-05 +49 optlc_net_106:49 4.76498e-05 +50 optlc_net_106:43 chany_bottom_in[4]:16 2.731132e-05 +51 optlc_net_106:19 chany_bottom_in[4]:17 0.0006394541 +52 optlc_net_106:18 chany_bottom_in[4]:18 0.0006394541 +53 optlc_net_106:40 chany_bottom_in[4]:15 2.731132e-05 +54 optlc_net_106:37 chany_bottom_in[8]:10 0.0004438453 +55 optlc_net_106:44 chany_bottom_in[8]:10 0.000616728 +56 optlc_net_106:44 chany_bottom_in[8]:11 0.0004438453 +57 optlc_net_106:45 chany_bottom_in[8]:11 0.000616728 +58 optlc_net_106:33 chany_bottom_in[17]:9 1.594776e-06 +59 optlc_net_106:34 chany_bottom_in[17]:8 1.594776e-06 +60 optlc_net_106:28 chany_bottom_in[17]:13 0.0002855258 +61 optlc_net_106:9 chany_bottom_in[17]:13 3.87902e-06 +62 optlc_net_106:27 chany_bottom_in[17]:14 0.0002855258 +63 optlc_net_106:10 chany_bottom_in[17]:14 3.87902e-06 +64 optlc_net_106:43 prog_clk[0]:118 2.113989e-05 +65 optlc_net_106:43 prog_clk[0]:122 5.653628e-06 +66 optlc_net_106:43 prog_clk[0]:133 1.728138e-05 +67 optlc_net_106:43 prog_clk[0]:134 2.471987e-06 +68 optlc_net_106:44 prog_clk[0]:135 0.0003451954 +69 optlc_net_106:44 prog_clk[0]:139 4.113661e-07 +70 optlc_net_106:46 prog_clk[0]:101 1.534627e-05 +71 optlc_net_106:46 prog_clk[0]:137 4.895739e-06 +72 optlc_net_106:45 prog_clk[0]:136 0.0003451954 +73 optlc_net_106:45 prog_clk[0]:140 4.113661e-07 +74 optlc_net_106:21 prog_clk[0]:98 1.02036e-06 +75 optlc_net_106:13 prog_clk[0]:95 3.186329e-07 +76 optlc_net_106:20 prog_clk[0]:95 1.02036e-06 +77 optlc_net_106:20 prog_clk[0]:98 3.186329e-07 +78 optlc_net_106:19 prog_clk[0]:257 6.640946e-06 +79 optlc_net_106:19 prog_clk[0]:258 4.21817e-06 +80 optlc_net_106:18 prog_clk[0]:253 6.640946e-06 +81 optlc_net_106:18 prog_clk[0]:257 4.21817e-06 +82 optlc_net_106:26 prog_clk[0]:98 1.015093e-05 +83 optlc_net_106:25 prog_clk[0]:95 1.015093e-05 +84 optlc_net_106:40 prog_clk[0]:112 2.113989e-05 +85 optlc_net_106:40 prog_clk[0]:119 5.653628e-06 +86 optlc_net_106:40 prog_clk[0]:122 1.728138e-05 +87 optlc_net_106:40 prog_clk[0]:133 2.471987e-06 +88 optlc_net_106:32 prog_clk[0]:138 4.895739e-06 +89 optlc_net_106:32 prog_clk[0]:140 1.534627e-05 +90 optlc_net_106:19 chany_bottom_in[3]:5 0.0005536271 +91 optlc_net_106:17 chany_bottom_in[3]:7 1.127267e-05 +92 optlc_net_106:18 chany_bottom_in[3]:6 0.0005536271 +93 optlc_net_106:16 chany_bottom_in[3]:8 1.127267e-05 +94 optlc_net_106:37 chanx_left_in[17] 0.0004438453 +95 optlc_net_106:49 chanx_left_in[17]:2 5.784504e-06 +96 optlc_net_106:48 chanx_left_in[17]:3 5.784504e-06 +97 optlc_net_106:43 chanx_left_in[17]:5 9.345035e-06 +98 optlc_net_106:44 chanx_left_in[17] 8.55552e-05 +99 optlc_net_106:44 chanx_left_in[17]:6 0.0004438453 +100 optlc_net_106:45 chanx_left_in[17]:6 8.55552e-05 +101 optlc_net_106:40 chanx_left_in[17]:4 9.345035e-06 +102 optlc_net_106:43 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:4 6.727377e-05 +103 optlc_net_106:40 mux_tree_tapbuf_size2_mem_8_ccff_tail[0]:5 6.727377e-05 +104 optlc_net_106:19 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005779145 +105 optlc_net_106:18 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0005779145 + +*RES +0 optlc_102:HI optlc_net_106:49 0.152 +1 optlc_net_106:33 mux_bottom_track_25\/mux_l1_in_1_:A0 0.152 +2 optlc_net_106:34 optlc_net_106:33 0.0001847826 +3 optlc_net_106:35 optlc_net_106:34 0.0045 +4 optlc_net_106:36 optlc_net_106:35 0.004158482 +5 optlc_net_106:37 optlc_net_106:36 0.00341 +6 optlc_net_106:49 optlc_net_106:48 0.0003370536 +7 optlc_net_106:48 optlc_net_106:47 0.0045 +8 optlc_net_106:47 optlc_net_106:46 0.001821428 +9 optlc_net_106:47 optlc_net_106:29 0.002388393 +10 optlc_net_106:43 optlc_net_106:42 0.0045 +11 optlc_net_106:43 optlc_net_106:40 0.02394197 +12 optlc_net_106:44 optlc_net_106:43 0.00341 +13 optlc_net_106:44 optlc_net_106:37 0.001223958 +14 optlc_net_106:46 optlc_net_106:45 0.00341 +15 optlc_net_106:46 optlc_net_106:32 0.003299107 +16 optlc_net_106:45 optlc_net_106:44 0.001728425 +17 optlc_net_106:28 optlc_net_106:27 0.00653125 +18 optlc_net_106:28 optlc_net_106:10 0.0003035715 +19 optlc_net_106:29 optlc_net_106:28 0.0045 +20 optlc_net_106:22 optlc_net_106:21 0.0045 +21 optlc_net_106:21 optlc_net_106:20 0.002388393 +22 optlc_net_106:12 optlc_net_106:11 0.0004933036 +23 optlc_net_106:13 optlc_net_106:12 0.0045 +24 optlc_net_106:11 mux_bottom_track_13\/mux_l2_in_0_:A0 0.152 +25 optlc_net_106:41 mux_bottom_track_27\/mux_l2_in_0_:A0 0.152 +26 optlc_net_106:42 optlc_net_106:41 0.0008683036 +27 optlc_net_106:20 optlc_net_106:19 0.00341 +28 optlc_net_106:20 optlc_net_106:13 0.001174107 +29 optlc_net_106:19 optlc_net_106:18 0.007636716 +30 optlc_net_106:17 optlc_net_106:16 0.002337054 +31 optlc_net_106:18 optlc_net_106:17 0.00341 +32 optlc_net_106:15 optlc_net_106:14 0.001720982 +33 optlc_net_106:16 optlc_net_106:15 0.0045 +34 optlc_net_106:14 mux_left_track_9\/mux_l2_in_0_:A0 0.152 +35 optlc_net_106:9 mux_bottom_track_29\/mux_l2_in_0_:A0 0.152 +36 optlc_net_106:27 optlc_net_106:26 0.0045 +37 optlc_net_106:26 optlc_net_106:25 0.001741072 +38 optlc_net_106:24 optlc_net_106:23 0.0009375 +39 optlc_net_106:25 optlc_net_106:24 0.0045 +40 optlc_net_106:39 optlc_net_106:38 9.239131e-05 +41 optlc_net_106:40 optlc_net_106:39 0.0045 +42 optlc_net_106:38 mux_left_track_25\/mux_l2_in_0_:A0 0.152 +43 optlc_net_106:30 mux_bottom_track_31\/mux_l2_in_0_:A0 0.152 +44 optlc_net_106:31 optlc_net_106:30 0.001734375 +45 optlc_net_106:32 optlc_net_106:31 0.0045 +46 optlc_net_106:23 mux_bottom_track_15\/mux_l2_in_0_:A0 0.152 +47 optlc_net_106:23 optlc_net_106:22 0.000625 +48 optlc_net_106:10 optlc_net_106:9 0.002274554 + +*END + +*D_NET mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001035965 //LENGTH 8.770 LUMPCC 9.2542e-05 DR + +*CONN +*I mux_bottom_track_29\/mux_l1_in_0_:X O *L 0 *C 26.395 66.300 +*I mux_bottom_track_29\/mux_l2_in_0_:A1 I *L 0.00198 *C 26.220 58.140 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 26.220 58.140 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 26.220 58.185 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 26.220 66.255 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 26.220 66.300 +*N mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 26.395 66.300 + +*CAP +0 mux_bottom_track_29\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_29\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.220579e-05 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003997673 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0003997673 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 5.548457e-05 +6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 5.419797e-05 +7 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_8_sram[1]:7 3.403094e-05 +8 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_tree_tapbuf_size2_8_sram[1]:11 1.224006e-05 +9 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_8_sram[1]:6 3.403094e-05 +10 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_tree_tapbuf_size2_8_sram[1]:10 1.224006e-05 + +*RES +0 mux_bottom_track_29\/mux_l1_in_0_:X mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 9.51087e-05 +2 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.007205358 +4 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_29\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_29/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0008329597 //LENGTH 6.810 LUMPCC 0.0001633028 DR + +*CONN +*I mux_bottom_track_37\/mux_l1_in_0_:X O *L 0 *C 75.725 23.460 +*I mux_bottom_track_37\/mux_l2_in_0_:A1 I *L 0.00198 *C 82.245 23.460 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 82.208 23.460 +*N mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 75.763 23.460 + +*CAP +0 mux_bottom_track_37\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_37\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003338284 +3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003338284 +4 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:7 8.165141e-05 +5 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_1_X[0]:6 8.165141e-05 + +*RES +0 mux_bottom_track_37\/mux_l1_in_0_:X mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.152 +1 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_37\/mux_l2_in_0_:A1 0.152 +2 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_37/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.005754464 + +*END + +*D_NET mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001116853 //LENGTH 12.040 LUMPCC 0 DR + +*CONN +*I mux_left_track_1\/mux_l1_in_0_:X O *L 0 *C 90.445 48.280 +*I mux_left_track_1\/mux_l2_in_0_:A1 I *L 0.00198 *C 91.905 58.140 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 91.905 58.140 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 92.000 58.095 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 92.000 48.325 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 91.955 48.280 +*N mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 90.483 48.280 + +*CAP +0 mux_left_track_1\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_1\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.478604e-05 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004370382 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004370382 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001079952 +6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001079952 + +*RES +0 mux_left_track_1\/mux_l1_in_0_:X mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_1\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +3 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.008723214 +5 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_1/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.001314732 + +*END + +*D_NET mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0] 0.0009588926 //LENGTH 8.700 LUMPCC 0 DR + +*CONN +*I mux_left_track_9\/mux_l1_in_0_:X O *L 0 *C 78.485 63.920 +*I mux_left_track_9\/mux_l2_in_0_:A1 I *L 0.00198 *C 84.085 61.540 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 84.085 61.540 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 84.180 61.585 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 84.180 63.875 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 84.135 63.920 +*N mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 78.523 63.920 + +*CAP +0 mux_left_track_9\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_9\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 2.447991e-05 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001343768 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001343768 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003318295 +6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003318295 + +*RES +0 mux_left_track_9\/mux_l1_in_0_:X mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.152 +1 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.005011161 +2 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002044643 +4 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_9\/mux_l2_in_0_:A1 0.152 +5 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_9/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001009573 //LENGTH 8.300 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l2_in_0_:X O *L 0 *C 15.355 80.580 +*I mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 9.760 82.795 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 9.760 82.795 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 15.135 82.620 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 15.180 82.575 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 15.180 80.625 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 15.180 80.580 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 15.355 80.580 + +*CAP +0 mux_left_track_25\/mux_l2_in_0_:X 1e-06 +1 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0003548785 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0003236222 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001139509 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001139509 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 5.316216e-05 +7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.800814e-05 + +*RES +0 mux_left_track_25\/mux_l2_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_left_track_25\/sky130_fd_sc_hd__buf_4_0_:A 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.004799107 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.001741072 +6 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_left_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.51087e-05 + +*END + +*D_NET ropt_net_139 0.001348412 //LENGTH 11.005 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_726:X O *L 0 *C 105.075 3.400 +*I ropt_mt_inst_755:A I *L 0.001767 *C 96.600 4.080 +*N ropt_net_139:2 *C 96.562 4.080 +*N ropt_net_139:3 *C 96.185 4.080 +*N ropt_net_139:4 *C 96.140 4.035 +*N ropt_net_139:5 *C 96.140 3.445 +*N ropt_net_139:6 *C 96.185 3.400 +*N ropt_net_139:7 *C 105.038 3.400 + +*CAP +0 ropt_mt_inst_726:X 1e-06 +1 ropt_mt_inst_755:A 1e-06 +2 ropt_net_139:2 4.693005e-05 +3 ropt_net_139:3 4.693005e-05 +4 ropt_net_139:4 6.054586e-05 +5 ropt_net_139:5 6.054586e-05 +6 ropt_net_139:6 0.0005657303 +7 ropt_net_139:7 0.0005657303 + +*RES +0 ropt_mt_inst_726:X ropt_net_139:7 0.152 +1 ropt_net_139:2 ropt_mt_inst_755:A 0.152 +2 ropt_net_139:3 ropt_net_139:2 0.0003370536 +3 ropt_net_139:4 ropt_net_139:3 0.0045 +4 ropt_net_139:6 ropt_net_139:5 0.0045 +5 ropt_net_139:5 ropt_net_139:4 0.0005267857 +6 ropt_net_139:7 ropt_net_139:6 0.007904018 + +*END + +*D_NET ropt_net_132 0.002387337 //LENGTH 16.735 LUMPCC 0.0008898559 DR + +*CONN +*I ropt_mt_inst_732:X O *L 0 *C 16.280 93.160 +*I ropt_mt_inst_747:A I *L 0.001766 *C 7.820 88.400 +*N ropt_net_132:2 *C 7.783 88.400 +*N ropt_net_132:3 *C 6.945 88.400 +*N ropt_net_132:4 *C 6.900 88.445 +*N ropt_net_132:5 *C 6.900 91.743 +*N ropt_net_132:6 *C 6.900 91.800 +*N ropt_net_132:7 *C 11.492 91.800 +*N ropt_net_132:8 *C 11.500 91.858 +*N ropt_net_132:9 *C 11.500 93.115 +*N ropt_net_132:10 *C 11.545 93.160 +*N ropt_net_132:11 *C 16.242 93.160 + +*CAP +0 ropt_mt_inst_732:X 1e-06 +1 ropt_mt_inst_747:A 1e-06 +2 ropt_net_132:2 6.529553e-05 +3 ropt_net_132:3 6.529553e-05 +4 ropt_net_132:4 0.000202353 +5 ropt_net_132:5 0.000202353 +6 ropt_net_132:6 0.0001630826 +7 ropt_net_132:7 0.0001630826 +8 ropt_net_132:8 9.889639e-05 +9 ropt_net_132:9 9.889639e-05 +10 ropt_net_132:10 0.0002181129 +11 ropt_net_132:11 0.0002181129 +12 ropt_net_132:10 chany_bottom_in[10]:3 0.0001922489 +13 ropt_net_132:11 chany_bottom_in[10]:4 0.0001922489 +14 ropt_net_132:6 chanx_left_out[17] 0.000252679 +15 ropt_net_132:7 chanx_left_out[17]:2 0.000252679 + +*RES +0 ropt_mt_inst_732:X ropt_net_132:11 0.152 +1 ropt_net_132:2 ropt_mt_inst_747:A 0.152 +2 ropt_net_132:3 ropt_net_132:2 0.0007477679 +3 ropt_net_132:4 ropt_net_132:3 0.0045 +4 ropt_net_132:5 ropt_net_132:4 0.002944197 +5 ropt_net_132:6 ropt_net_132:5 0.00341 +6 ropt_net_132:8 ropt_net_132:7 0.00341 +7 ropt_net_132:7 ropt_net_132:6 0.0007194916 +8 ropt_net_132:10 ropt_net_132:9 0.0045 +9 ropt_net_132:9 ropt_net_132:8 0.001122768 +10 ropt_net_132:11 ropt_net_132:10 0.004194196 + +*END + +*D_NET chany_bottom_out[4] 0.0009133499 //LENGTH 7.755 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_737:X O *L 0 *C 99.095 6.120 +*P chany_bottom_out[4] O *L 0.7423 *C 96.600 1.325 +*N chany_bottom_out[4]:2 *C 96.600 6.075 +*N chany_bottom_out[4]:3 *C 96.645 6.120 +*N chany_bottom_out[4]:4 *C 99.058 6.120 + +*CAP +0 ropt_mt_inst_737:X 1e-06 +1 chany_bottom_out[4] 0.0002849075 +2 chany_bottom_out[4]:2 0.0002849075 +3 chany_bottom_out[4]:3 0.0001712675 +4 chany_bottom_out[4]:4 0.0001712675 + +*RES +0 ropt_mt_inst_737:X chany_bottom_out[4]:4 0.152 +1 chany_bottom_out[4]:4 chany_bottom_out[4]:3 0.002154018 +2 chany_bottom_out[4]:3 chany_bottom_out[4]:2 0.0045 +3 chany_bottom_out[4]:2 chany_bottom_out[4] 0.004241071 + +*END + +*D_NET chanx_left_out[17] 0.001766403 //LENGTH 13.245 LUMPCC 0.000505358 DR + +*CONN +*I ropt_mt_inst_747:X O *L 0 *C 11.695 89.080 +*P chanx_left_out[17] O *L 0.7423 *C 1.305 91.120 +*N chanx_left_out[17]:2 *C 11.033 91.120 +*N chanx_left_out[17]:3 *C 11.040 91.062 +*N chanx_left_out[17]:4 *C 11.040 89.125 +*N chanx_left_out[17]:5 *C 11.085 89.080 +*N chanx_left_out[17]:6 *C 11.658 89.080 + +*CAP +0 ropt_mt_inst_747:X 1e-06 +1 chanx_left_out[17] 0.0004395785 +2 chanx_left_out[17]:2 0.0004395785 +3 chanx_left_out[17]:3 0.000132557 +4 chanx_left_out[17]:4 0.000132557 +5 chanx_left_out[17]:5 5.788696e-05 +6 chanx_left_out[17]:6 5.788696e-05 +7 chanx_left_out[17] ropt_net_132:6 0.000252679 +8 chanx_left_out[17]:2 ropt_net_132:7 0.000252679 + +*RES +0 ropt_mt_inst_747:X chanx_left_out[17]:6 0.152 +1 chanx_left_out[17]:6 chanx_left_out[17]:5 0.0005111608 +2 chanx_left_out[17]:5 chanx_left_out[17]:4 0.0045 +3 chanx_left_out[17]:4 chanx_left_out[17]:3 0.001729911 +4 chanx_left_out[17]:3 chanx_left_out[17]:2 0.00341 +5 chanx_left_out[17]:2 chanx_left_out[17] 0.001523975 + +*END + +*D_NET chanx_left_out[16] 0.0006415688 //LENGTH 4.055 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_751:X O *L 0 *C 4.140 55.080 +*P chanx_left_out[16] O *L 0.7423 *C 1.230 54.400 +*N chanx_left_out[16]:2 *C 4.140 54.400 +*N chanx_left_out[16]:3 *C 4.140 55.073 +*N chanx_left_out[16]:4 *C 4.140 55.080 +*N chanx_left_out[16]:5 *C 4.140 55.080 + +*CAP +0 ropt_mt_inst_751:X 1e-06 +1 chanx_left_out[16] 0.000233098 +2 chanx_left_out[16]:2 0.0002868347 +3 chanx_left_out[16]:3 5.373669e-05 +4 chanx_left_out[16]:4 3.502793e-05 +5 chanx_left_out[16]:5 3.187161e-05 + +*RES +0 ropt_mt_inst_751:X chanx_left_out[16]:5 0.152 +1 chanx_left_out[16]:5 chanx_left_out[16]:4 0.0045 +2 chanx_left_out[16]:4 chanx_left_out[16]:3 0.00341 +3 chanx_left_out[16]:3 chanx_left_out[16]:2 0.0001053583 +4 chanx_left_out[16]:2 chanx_left_out[16] 0.0004559 + +*END + +*D_NET ropt_net_126 0.001386244 //LENGTH 10.300 LUMPCC 0.0004028749 DR + +*CONN +*I BUFT_RR_55:X O *L 0 *C 7.820 55.420 +*I ropt_mt_inst_741:A I *L 0.001766 *C 3.220 58.480 +*N ropt_net_126:2 *C 3.183 58.480 +*N ropt_net_126:3 *C 2.805 58.480 +*N ropt_net_126:4 *C 2.760 58.435 +*N ropt_net_126:5 *C 2.760 55.125 +*N ropt_net_126:6 *C 2.760 55.080 +*N ropt_net_126:7 *C 2.760 55.420 +*N ropt_net_126:8 *C 7.783 55.420 + +*CAP +0 BUFT_RR_55:X 1e-06 +1 ropt_mt_inst_741:A 1e-06 +2 ropt_net_126:2 4.274608e-05 +3 ropt_net_126:3 4.274608e-05 +4 ropt_net_126:4 9.315019e-05 +5 ropt_net_126:5 9.315019e-05 +6 ropt_net_126:6 6.253393e-05 +7 ropt_net_126:7 0.0003379585 +8 ropt_net_126:8 0.0003090845 +9 ropt_net_126:5 chanx_left_in[2]:4 9.763606e-05 +10 ropt_net_126:4 chanx_left_in[2]:5 9.763606e-05 +11 ropt_net_126:8 ropt_net_136:2 2.155877e-05 +12 ropt_net_126:5 ropt_net_136:4 6.916818e-05 +13 ropt_net_126:3 ropt_net_136:6 1.307443e-05 +14 ropt_net_126:4 ropt_net_136:5 6.916818e-05 +15 ropt_net_126:2 ropt_net_136:7 1.307443e-05 +16 ropt_net_126:7 ropt_net_136:3 2.155877e-05 + +*RES +0 BUFT_RR_55:X ropt_net_126:8 0.152 +1 ropt_net_126:8 ropt_net_126:7 0.004484375 +2 ropt_net_126:6 ropt_net_126:5 0.0045 +3 ropt_net_126:5 ropt_net_126:4 0.002955357 +4 ropt_net_126:3 ropt_net_126:2 0.0003370536 +5 ropt_net_126:4 ropt_net_126:3 0.0045 +6 ropt_net_126:2 ropt_mt_inst_741:A 0.152 +7 ropt_net_126:7 ropt_net_126:6 0.0003035715 + +*END + +*D_NET ropt_net_130 0.003819164 //LENGTH 22.575 LUMPCC 0.00115537 DR + +*CONN +*I ropt_mt_inst_743:X O *L 0 *C 11.695 52.700 +*I ropt_mt_inst_745:A I *L 0.001766 *C 3.220 47.600 +*N ropt_net_130:2 *C 2.970 47.600 +*N ropt_net_130:3 *C 3.258 47.600 +*N ropt_net_130:4 *C 3.635 47.600 +*N ropt_net_130:5 *C 3.680 47.600 +*N ropt_net_130:6 *C 3.678 47.600 +*N ropt_net_130:7 *C 3.680 47.593 +*N ropt_net_130:8 *C 3.680 44.888 +*N ropt_net_130:9 *C 3.700 44.880 +*N ropt_net_130:10 *C 10.572 44.880 +*N ropt_net_130:11 *C 10.580 44.938 +*N ropt_net_130:12 *C 10.580 50.275 +*N ropt_net_130:13 *C 10.625 50.320 +*N ropt_net_130:14 *C 11.915 50.320 +*N ropt_net_130:15 *C 11.960 50.365 +*N ropt_net_130:16 *C 11.960 52.655 +*N ropt_net_130:17 *C 11.960 52.700 +*N ropt_net_130:18 *C 11.695 52.700 + +*CAP +0 ropt_mt_inst_743:X 1e-06 +1 ropt_mt_inst_745:A 1e-06 +2 ropt_net_130:2 9.376013e-05 +3 ropt_net_130:3 4.17799e-05 +4 ropt_net_130:4 4.17799e-05 +5 ropt_net_130:5 3.667811e-05 +6 ropt_net_130:6 9.376013e-05 +7 ropt_net_130:7 0.0001972462 +8 ropt_net_130:8 0.0001972462 +9 ropt_net_130:9 0.0002631366 +10 ropt_net_130:10 0.0002631366 +11 ropt_net_130:11 0.0003497628 +12 ropt_net_130:12 0.0003497628 +13 ropt_net_130:13 0.0001370024 +14 ropt_net_130:14 0.0001370024 +15 ropt_net_130:15 0.0001631245 +16 ropt_net_130:16 0.0001631245 +17 ropt_net_130:17 6.546758e-05 +18 ropt_net_130:18 6.802237e-05 +19 ropt_net_130:12 chany_bottom_in[6]:8 6.575148e-08 +20 ropt_net_130:11 chany_bottom_in[6]:9 6.575148e-08 +21 ropt_net_130:10 chany_bottom_in[6]:11 0.000148044 +22 ropt_net_130:9 chany_bottom_in[6]:10 0.000148044 +23 ropt_net_130:10 chanx_left_in[4]:10 0.0003220137 +24 ropt_net_130:9 chanx_left_in[4]:11 0.0003220137 +25 ropt_net_130:10 chanx_left_out[15]:4 0.0001075617 +26 ropt_net_130:9 chanx_left_out[15]:3 0.0001075617 + +*RES +0 ropt_mt_inst_743:X ropt_net_130:18 0.152 +1 ropt_net_130:18 ropt_net_130:17 0.0001440218 +2 ropt_net_130:17 ropt_net_130:16 0.0045 +3 ropt_net_130:16 ropt_net_130:15 0.002044643 +4 ropt_net_130:14 ropt_net_130:13 0.001151786 +5 ropt_net_130:15 ropt_net_130:14 0.0045 +6 ropt_net_130:13 ropt_net_130:12 0.0045 +7 ropt_net_130:12 ropt_net_130:11 0.004765625 +8 ropt_net_130:11 ropt_net_130:10 0.00341 +9 ropt_net_130:10 ropt_net_130:9 0.001076692 +10 ropt_net_130:9 ropt_net_130:8 0.00341 +11 ropt_net_130:8 ropt_net_130:7 0.0004237833 +12 ropt_net_130:6 ropt_net_130:5 0.00341 +13 ropt_net_130:6 ropt_net_130:2 0.0001039141 +14 ropt_net_130:7 ropt_net_130:6 0.00341 +15 ropt_net_130:5 ropt_net_130:4 0.0045 +16 ropt_net_130:4 ropt_net_130:3 0.0003370536 +17 ropt_net_130:3 ropt_mt_inst_745:A 0.152 + +*END + +*D_NET ropt_net_113 0.002318155 //LENGTH 18.440 LUMPCC 0.0002621714 DR + +*CONN +*I BUFT_P_85:X O *L 0 *C 16.100 91.800 +*I ropt_mt_inst_728:A I *L 0.001766 *C 7.820 96.560 +*N ropt_net_113:2 *C 7.820 96.560 +*N ropt_net_113:3 *C 7.820 96.900 +*N ropt_net_113:4 *C 6.025 96.900 +*N ropt_net_113:5 *C 5.980 96.855 +*N ropt_net_113:6 *C 5.980 91.845 +*N ropt_net_113:7 *C 6.025 91.800 +*N ropt_net_113:8 *C 16.062 91.800 + +*CAP +0 BUFT_P_85:X 1e-06 +1 ropt_mt_inst_728:A 1e-06 +2 ropt_net_113:2 6.28383e-05 +3 ropt_net_113:3 0.0001160782 +4 ropt_net_113:4 8.561403e-05 +5 ropt_net_113:5 0.0002933488 +6 ropt_net_113:6 0.0002933488 +7 ropt_net_113:7 0.0006013779 +8 ropt_net_113:8 0.0006013779 +9 ropt_net_113:4 ropt_net_138:3 7.819988e-05 +10 ropt_net_113:3 ropt_net_138:4 7.819988e-05 +11 ropt_net_113:7 ropt_net_140:3 5.288581e-05 +12 ropt_net_113:8 ropt_net_140:4 5.288581e-05 + +*RES +0 BUFT_P_85:X ropt_net_113:8 0.152 +1 ropt_net_113:2 ropt_mt_inst_728:A 0.152 +2 ropt_net_113:4 ropt_net_113:3 0.001602679 +3 ropt_net_113:5 ropt_net_113:4 0.0045 +4 ropt_net_113:7 ropt_net_113:6 0.0045 +5 ropt_net_113:6 ropt_net_113:5 0.004473215 +6 ropt_net_113:8 ropt_net_113:7 0.008962054 +7 ropt_net_113:3 ropt_net_113:2 0.0003035715 + +*END + +*D_NET chany_bottom_in[12] 0.01744449 //LENGTH 162.115 LUMPCC 0.003331934 DR + +*CONN +*P chany_bottom_in[12] I *L 0.29796 *C 79.580 1.290 +*I BUFT_P_91:A I *L 0.001776 *C 12.880 82.960 +*N chany_bottom_in[12]:2 *C 12.880 82.960 +*N chany_bottom_in[12]:3 *C 12.880 83.005 +*N chany_bottom_in[12]:4 *C 12.880 85.635 +*N chany_bottom_in[12]:5 *C 12.835 85.680 +*N chany_bottom_in[12]:6 *C 9.705 85.680 +*N chany_bottom_in[12]:7 *C 9.660 85.680 +*N chany_bottom_in[12]:8 *C 9.668 85.680 +*N chany_bottom_in[12]:9 *C 59.495 85.680 +*N chany_bottom_in[12]:10 *C 73.580 85.680 +*N chany_bottom_in[12]:11 *C 73.600 85.672 +*N chany_bottom_in[12]:12 *C 73.600 53.915 +*N chany_bottom_in[12]:13 *C 73.600 4.088 +*N chany_bottom_in[12]:14 *C 73.620 4.080 +*N chany_bottom_in[12]:15 *C 79.573 4.080 +*N chany_bottom_in[12]:16 *C 79.580 4.022 + +*CAP +0 chany_bottom_in[12] 0.0001707995 +1 BUFT_P_91:A 1e-06 +2 chany_bottom_in[12]:2 3.803241e-05 +3 chany_bottom_in[12]:3 0.0001551351 +4 chany_bottom_in[12]:4 0.0001551351 +5 chany_bottom_in[12]:5 0.0001725476 +6 chany_bottom_in[12]:6 0.0001725476 +7 chany_bottom_in[12]:7 3.357418e-05 +8 chany_bottom_in[12]:8 0.002112696 +9 chany_bottom_in[12]:9 0.002699396 +10 chany_bottom_in[12]:10 0.0005867003 +11 chany_bottom_in[12]:11 0.001366352 +12 chany_bottom_in[12]:12 0.003350964 +13 chany_bottom_in[12]:13 0.001984611 +14 chany_bottom_in[12]:14 0.0004711327 +15 chany_bottom_in[12]:15 0.0004711327 +16 chany_bottom_in[12]:16 0.0001707995 +17 chany_bottom_in[12]:11 chany_bottom_in[16]:18 0.0002848014 +18 chany_bottom_in[12]:14 chany_bottom_in[16]:21 5.743482e-06 +19 chany_bottom_in[12]:13 chany_bottom_in[16]:20 0.0006709116 +20 chany_bottom_in[12]:13 chany_bottom_in[16]:19 3.003063e-05 +21 chany_bottom_in[12]:15 chany_bottom_in[16]:22 5.743482e-06 +22 chany_bottom_in[12]:12 chany_bottom_in[16]:18 3.003063e-05 +23 chany_bottom_in[12]:12 chany_bottom_in[16]:19 0.000955713 +24 chany_bottom_in[12]:8 chanx_left_in[19]:9 0.0003892162 +25 chany_bottom_in[12]:8 chanx_left_in[19]:8 3.363187e-05 +26 chany_bottom_in[12]:10 chanx_left_in[19]:7 0.0001177244 +27 chany_bottom_in[12]:9 chanx_left_in[19]:7 3.363187e-05 +28 chany_bottom_in[12]:9 chanx_left_in[19]:8 0.0005069406 +29 chany_bottom_in[12]:5 ropt_net_114:8 0.0001339077 +30 chany_bottom_in[12]:6 ropt_net_114:7 0.0001339077 + +*RES +0 chany_bottom_in[12] chany_bottom_in[12]:16 0.002439732 +1 chany_bottom_in[12]:2 BUFT_P_91:A 0.152 +2 chany_bottom_in[12]:3 chany_bottom_in[12]:2 0.0045 +3 chany_bottom_in[12]:5 chany_bottom_in[12]:4 0.0045 +4 chany_bottom_in[12]:4 chany_bottom_in[12]:3 0.002348214 +5 chany_bottom_in[12]:6 chany_bottom_in[12]:5 0.002794643 +6 chany_bottom_in[12]:7 chany_bottom_in[12]:6 0.0045 +7 chany_bottom_in[12]:8 chany_bottom_in[12]:7 0.00341 +8 chany_bottom_in[12]:10 chany_bottom_in[12]:9 0.00220665 +9 chany_bottom_in[12]:11 chany_bottom_in[12]:10 0.00341 +10 chany_bottom_in[12]:14 chany_bottom_in[12]:13 0.00341 +11 chany_bottom_in[12]:13 chany_bottom_in[12]:12 0.007806308 +12 chany_bottom_in[12]:16 chany_bottom_in[12]:15 0.00341 +13 chany_bottom_in[12]:15 chany_bottom_in[12]:14 0.0009325583 +14 chany_bottom_in[12]:9 chany_bottom_in[12]:8 0.007806308 +15 chany_bottom_in[12]:12 chany_bottom_in[12]:11 0.004975342 + +*END + +*D_NET mux_tree_tapbuf_size2_17_sram[0] 0.005125971 //LENGTH 43.885 LUMPCC 0.0001117822 DR + +*CONN +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 53.665 72.080 +*I mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 20.875 75.140 +*I mux_left_track_25\/mux_l1_in_0_:S I *L 0.00357 *C 29.080 79.560 +*N mux_tree_tapbuf_size2_17_sram[0]:3 *C 29.095 79.560 +*N mux_tree_tapbuf_size2_17_sram[0]:4 *C 29.418 79.560 +*N mux_tree_tapbuf_size2_17_sram[0]:5 *C 29.440 79.515 +*N mux_tree_tapbuf_size2_17_sram[0]:6 *C 20.913 75.140 +*N mux_tree_tapbuf_size2_17_sram[0]:7 *C 29.395 75.140 +*N mux_tree_tapbuf_size2_17_sram[0]:8 *C 29.440 75.185 +*N mux_tree_tapbuf_size2_17_sram[0]:9 *C 29.440 76.840 +*N mux_tree_tapbuf_size2_17_sram[0]:10 *C 29.485 76.840 +*N mux_tree_tapbuf_size2_17_sram[0]:11 *C 53.315 76.840 +*N mux_tree_tapbuf_size2_17_sram[0]:12 *C 53.360 76.795 +*N mux_tree_tapbuf_size2_17_sram[0]:13 *C 53.360 72.125 +*N mux_tree_tapbuf_size2_17_sram[0]:14 *C 53.360 72.080 +*N mux_tree_tapbuf_size2_17_sram[0]:15 *C 53.665 72.080 + +*CAP +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_25\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_17_sram[0]:3 5.343207e-05 +4 mux_tree_tapbuf_size2_17_sram[0]:4 5.343207e-05 +5 mux_tree_tapbuf_size2_17_sram[0]:5 0.0001428242 +6 mux_tree_tapbuf_size2_17_sram[0]:6 0.0005289823 +7 mux_tree_tapbuf_size2_17_sram[0]:7 0.0005289823 +8 mux_tree_tapbuf_size2_17_sram[0]:8 8.966638e-05 +9 mux_tree_tapbuf_size2_17_sram[0]:9 0.0002620523 +10 mux_tree_tapbuf_size2_17_sram[0]:10 0.001382183 +11 mux_tree_tapbuf_size2_17_sram[0]:11 0.001382183 +12 mux_tree_tapbuf_size2_17_sram[0]:12 0.0002429101 +13 mux_tree_tapbuf_size2_17_sram[0]:13 0.0002429101 +14 mux_tree_tapbuf_size2_17_sram[0]:14 4.993978e-05 +15 mux_tree_tapbuf_size2_17_sram[0]:15 5.169137e-05 +16 mux_tree_tapbuf_size2_17_sram[0]:10 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:7 5.589111e-05 +17 mux_tree_tapbuf_size2_17_sram[0]:11 mux_tree_tapbuf_size2_mem_1_ccff_tail[0]:6 5.589111e-05 + +*RES +0 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_17_sram[0]:15 0.152 +1 mux_tree_tapbuf_size2_17_sram[0]:7 mux_tree_tapbuf_size2_17_sram[0]:6 0.007573661 +2 mux_tree_tapbuf_size2_17_sram[0]:8 mux_tree_tapbuf_size2_17_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size2_17_sram[0]:6 mem_left_track_25\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +4 mux_tree_tapbuf_size2_17_sram[0]:10 mux_tree_tapbuf_size2_17_sram[0]:9 0.0045 +5 mux_tree_tapbuf_size2_17_sram[0]:9 mux_tree_tapbuf_size2_17_sram[0]:8 0.001477679 +6 mux_tree_tapbuf_size2_17_sram[0]:9 mux_tree_tapbuf_size2_17_sram[0]:5 0.002388393 +7 mux_tree_tapbuf_size2_17_sram[0]:11 mux_tree_tapbuf_size2_17_sram[0]:10 0.02127679 +8 mux_tree_tapbuf_size2_17_sram[0]:12 mux_tree_tapbuf_size2_17_sram[0]:11 0.0045 +9 mux_tree_tapbuf_size2_17_sram[0]:14 mux_tree_tapbuf_size2_17_sram[0]:13 0.0045 +10 mux_tree_tapbuf_size2_17_sram[0]:13 mux_tree_tapbuf_size2_17_sram[0]:12 0.004169643 +11 mux_tree_tapbuf_size2_17_sram[0]:15 mux_tree_tapbuf_size2_17_sram[0]:14 0.0001657609 +12 mux_tree_tapbuf_size2_17_sram[0]:4 mux_tree_tapbuf_size2_17_sram[0]:3 0.0001752718 +13 mux_tree_tapbuf_size2_17_sram[0]:5 mux_tree_tapbuf_size2_17_sram[0]:4 0.0045 +14 mux_tree_tapbuf_size2_17_sram[0]:3 mux_left_track_25\/mux_l1_in_0_:S 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_4_sram[1] 0.002312184 //LENGTH 18.920 LUMPCC 0.0005480403 DR + +*CONN +*I mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 50.445 31.280 +*I mux_bottom_track_19\/mux_l2_in_0_:S I *L 0.00357 *C 47.280 25.160 +*I mem_bottom_track_19\/FTB_11__26:A I *L 0.001746 *C 50.140 17.680 +*N mux_tree_tapbuf_size2_4_sram[1]:3 *C 50.102 17.680 +*N mux_tree_tapbuf_size2_4_sram[1]:4 *C 49.265 17.680 +*N mux_tree_tapbuf_size2_4_sram[1]:5 *C 49.220 17.725 +*N mux_tree_tapbuf_size2_4_sram[1]:6 *C 47.318 25.160 +*N mux_tree_tapbuf_size2_4_sram[1]:7 *C 49.175 25.160 +*N mux_tree_tapbuf_size2_4_sram[1]:8 *C 49.220 25.160 +*N mux_tree_tapbuf_size2_4_sram[1]:9 *C 49.220 31.235 +*N mux_tree_tapbuf_size2_4_sram[1]:10 *C 49.265 31.280 +*N mux_tree_tapbuf_size2_4_sram[1]:11 *C 50.407 31.280 + +*CAP +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mux_bottom_track_19\/mux_l2_in_0_:S 1e-06 +2 mem_bottom_track_19\/FTB_11__26:A 1e-06 +3 mux_tree_tapbuf_size2_4_sram[1]:3 0.0001016357 +4 mux_tree_tapbuf_size2_4_sram[1]:4 0.0001016357 +5 mux_tree_tapbuf_size2_4_sram[1]:5 0.0002563378 +6 mux_tree_tapbuf_size2_4_sram[1]:6 0.0001571345 +7 mux_tree_tapbuf_size2_4_sram[1]:7 0.0001571345 +8 mux_tree_tapbuf_size2_4_sram[1]:8 0.000544218 +9 mux_tree_tapbuf_size2_4_sram[1]:9 0.0002609633 +10 mux_tree_tapbuf_size2_4_sram[1]:10 9.104194e-05 +11 mux_tree_tapbuf_size2_4_sram[1]:11 9.104194e-05 +12 mux_tree_tapbuf_size2_4_sram[1]:9 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 2.357738e-05 +13 mux_tree_tapbuf_size2_4_sram[1]:7 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:14 1.141311e-05 +14 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:13 6.245199e-05 +15 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 2.357738e-05 +16 mux_tree_tapbuf_size2_4_sram[1]:6 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:15 1.141311e-05 +17 mux_tree_tapbuf_size2_4_sram[1]:5 mux_bottom_track_19/sky130_fd_sc_hd__mux2_1_1_X[0]:12 6.245199e-05 +18 mux_tree_tapbuf_size2_4_sram[1]:9 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 7.319375e-05 +19 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001033839 +20 mux_tree_tapbuf_size2_4_sram[1]:8 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 7.319375e-05 +21 mux_tree_tapbuf_size2_4_sram[1]:5 mux_bottom_track_31/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001033839 + +*RES +0 mem_bottom_track_19\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_4_sram[1]:11 0.152 +1 mux_tree_tapbuf_size2_4_sram[1]:10 mux_tree_tapbuf_size2_4_sram[1]:9 0.0045 +2 mux_tree_tapbuf_size2_4_sram[1]:9 mux_tree_tapbuf_size2_4_sram[1]:8 0.005424107 +3 mux_tree_tapbuf_size2_4_sram[1]:11 mux_tree_tapbuf_size2_4_sram[1]:10 0.001020089 +4 mux_tree_tapbuf_size2_4_sram[1]:7 mux_tree_tapbuf_size2_4_sram[1]:6 0.001658482 +5 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:7 0.0045 +6 mux_tree_tapbuf_size2_4_sram[1]:8 mux_tree_tapbuf_size2_4_sram[1]:5 0.006638394 +7 mux_tree_tapbuf_size2_4_sram[1]:6 mux_bottom_track_19\/mux_l2_in_0_:S 0.152 +8 mux_tree_tapbuf_size2_4_sram[1]:4 mux_tree_tapbuf_size2_4_sram[1]:3 0.0007477679 +9 mux_tree_tapbuf_size2_4_sram[1]:5 mux_tree_tapbuf_size2_4_sram[1]:4 0.0045 +10 mux_tree_tapbuf_size2_4_sram[1]:3 mem_bottom_track_19\/FTB_11__26:A 0.152 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_0_ccff_tail[0] 0.005877485 //LENGTH 52.970 LUMPCC 0.001243279 DR + +*CONN +*I mem_bottom_track_11\/FTB_7__22:X O *L 0 *C 58.645 15.300 +*I mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 54.445 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 *C 54.408 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 *C 53.360 60.860 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 *C 53.360 60.520 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 *C 53.360 60.475 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 *C 53.360 15.345 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 *C 53.405 15.300 +*N mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 *C 58.608 15.300 + +*CAP +0 mem_bottom_track_11\/FTB_7__22:X 1e-06 +1 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 7.580587e-05 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0001020603 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 5.650819e-05 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.001951447 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.001951447 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.0002474693 +8 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 0.0002474693 +9 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size2_11_sram[1]:3 7.80306e-05 +10 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_11_sram[1]:4 7.80306e-05 +11 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_11_sram[1]:5 0.0001004734 +12 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_11_sram[1]:7 6.035134e-05 +13 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_11_sram[1]:7 0.0001004734 +14 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_11_sram[1]:8 6.035134e-05 +15 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:7 0.0001025664 +16 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:6 0.0001025664 +17 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 7.200911e-06 +18 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 7.200911e-06 +19 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:5 0.0001246948 +20 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_4_ccff_tail[0]:4 0.0001246948 +21 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:6 0.000148322 +22 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_5_X[0]:7 0.000148322 + +*RES +0 mem_bottom_track_11\/FTB_7__22:X mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 0.152 +1 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:8 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 0.00464509 +2 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 0.0045 +3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 0.04029465 +4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 0.0003035715 +5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:4 0.0045 +6 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 mem_bottom_track_13\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +7 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_0_ccff_tail[0]:2 0.0009352679 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_9_ccff_tail[0] 0.0009530541 //LENGTH 5.965 LUMPCC 0.000300938 DR + +*CONN +*I mem_bottom_track_31\/FTB_16__31:X O *L 0 *C 32.870 55.420 +*I mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 35.605 53.380 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 *C 35.605 53.380 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 *C 35.880 53.380 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 *C 35.880 53.425 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 *C 35.880 55.375 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 *C 35.835 55.420 +*N mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 *C 32.907 55.420 + +*CAP +0 mem_bottom_track_31\/FTB_16__31:X 1e-06 +1 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 5.022355e-05 +3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 5.336736e-05 +4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 9.12541e-05 +5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 9.12541e-05 +6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 0.0001820084 +7 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 0.0001820084 +8 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 chanx_left_in[17]:3 9.920681e-05 +9 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 chanx_left_in[17]:2 9.920681e-05 +10 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:4 5.126222e-05 +11 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_0_X[0]:3 5.126222e-05 + +*RES +0 mem_bottom_track_31\/FTB_16__31:X mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 0.002613839 +2 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 0.001741071 +4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 0.0001277174 +5 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size2_mem_9_ccff_tail[0]:2 mem_bottom_track_33\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_tree_tapbuf_size5_0_sram[1] 0.003465524 //LENGTH 24.835 LUMPCC 0.0001488673 DR + +*CONN +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 14.105 31.280 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D I *L 0.001695 *C 8.455 37.060 +*I mux_bottom_track_3\/mux_l2_in_1_:S I *L 0.00357 *C 5.880 39.440 +*I mux_bottom_track_3\/mux_l2_in_0_:S I *L 0.00357 *C 18.040 30.990 +*N mux_tree_tapbuf_size5_0_sram[1]:4 *C 18.040 30.990 +*N mux_tree_tapbuf_size5_0_sram[1]:5 *C 18.003 31.280 +*N mux_tree_tapbuf_size5_0_sram[1]:6 *C 5.880 39.440 +*N mux_tree_tapbuf_size5_0_sram[1]:7 *C 5.980 39.440 +*N mux_tree_tapbuf_size5_0_sram[1]:8 *C 5.988 39.440 +*N mux_tree_tapbuf_size5_0_sram[1]:9 *C 8.732 39.440 +*N mux_tree_tapbuf_size5_0_sram[1]:10 *C 8.740 39.383 +*N mux_tree_tapbuf_size5_0_sram[1]:11 *C 8.455 37.060 +*N mux_tree_tapbuf_size5_0_sram[1]:12 *C 8.740 37.400 +*N mux_tree_tapbuf_size5_0_sram[1]:13 *C 8.740 37.400 +*N mux_tree_tapbuf_size5_0_sram[1]:14 *C 8.740 34.725 +*N mux_tree_tapbuf_size5_0_sram[1]:15 *C 8.785 34.680 +*N mux_tree_tapbuf_size5_0_sram[1]:16 *C 16.055 34.680 +*N mux_tree_tapbuf_size5_0_sram[1]:17 *C 16.100 34.635 +*N mux_tree_tapbuf_size5_0_sram[1]:18 *C 16.100 31.325 +*N mux_tree_tapbuf_size5_0_sram[1]:19 *C 16.100 31.280 +*N mux_tree_tapbuf_size5_0_sram[1]:20 *C 14.143 31.280 + +*CAP +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 1e-06 +2 mux_bottom_track_3\/mux_l2_in_1_:S 1e-06 +3 mux_bottom_track_3\/mux_l2_in_0_:S 1e-06 +4 mux_tree_tapbuf_size5_0_sram[1]:4 6.110189e-05 +5 mux_tree_tapbuf_size5_0_sram[1]:5 0.0001551217 +6 mux_tree_tapbuf_size5_0_sram[1]:6 3.047657e-05 +7 mux_tree_tapbuf_size5_0_sram[1]:7 3.626915e-05 +8 mux_tree_tapbuf_size5_0_sram[1]:8 0.0002968806 +9 mux_tree_tapbuf_size5_0_sram[1]:9 0.0002968806 +10 mux_tree_tapbuf_size5_0_sram[1]:10 0.0001166592 +11 mux_tree_tapbuf_size5_0_sram[1]:11 5.929793e-05 +12 mux_tree_tapbuf_size5_0_sram[1]:12 6.357036e-05 +13 mux_tree_tapbuf_size5_0_sram[1]:13 0.000306897 +14 mux_tree_tapbuf_size5_0_sram[1]:14 0.0001579678 +15 mux_tree_tapbuf_size5_0_sram[1]:15 0.0004806937 +16 mux_tree_tapbuf_size5_0_sram[1]:16 0.0004806937 +17 mux_tree_tapbuf_size5_0_sram[1]:17 0.0001724025 +18 mux_tree_tapbuf_size5_0_sram[1]:18 0.0001724025 +19 mux_tree_tapbuf_size5_0_sram[1]:19 0.0002880786 +20 mux_tree_tapbuf_size5_0_sram[1]:20 0.0001372627 +21 mux_tree_tapbuf_size5_0_sram[1]:19 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:6 1.328698e-05 +22 mux_tree_tapbuf_size5_0_sram[1]:18 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.314298e-05 +23 mux_tree_tapbuf_size5_0_sram[1]:16 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:3 2.800371e-05 +24 mux_tree_tapbuf_size5_0_sram[1]:17 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.314298e-05 +25 mux_tree_tapbuf_size5_0_sram[1]:15 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:2 2.800371e-05 +26 mux_tree_tapbuf_size5_0_sram[1]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_2_X[0]:7 1.328698e-05 + +*RES +0 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size5_0_sram[1]:20 0.152 +1 mux_tree_tapbuf_size5_0_sram[1]:20 mux_tree_tapbuf_size5_0_sram[1]:19 0.001747768 +2 mux_tree_tapbuf_size5_0_sram[1]:19 mux_tree_tapbuf_size5_0_sram[1]:18 0.0045 +3 mux_tree_tapbuf_size5_0_sram[1]:19 mux_tree_tapbuf_size5_0_sram[1]:5 0.001698661 +4 mux_tree_tapbuf_size5_0_sram[1]:18 mux_tree_tapbuf_size5_0_sram[1]:17 0.002955357 +5 mux_tree_tapbuf_size5_0_sram[1]:16 mux_tree_tapbuf_size5_0_sram[1]:15 0.006491072 +6 mux_tree_tapbuf_size5_0_sram[1]:17 mux_tree_tapbuf_size5_0_sram[1]:16 0.0045 +7 mux_tree_tapbuf_size5_0_sram[1]:15 mux_tree_tapbuf_size5_0_sram[1]:14 0.0045 +8 mux_tree_tapbuf_size5_0_sram[1]:14 mux_tree_tapbuf_size5_0_sram[1]:13 0.002388393 +9 mux_tree_tapbuf_size5_0_sram[1]:10 mux_tree_tapbuf_size5_0_sram[1]:9 0.00341 +10 mux_tree_tapbuf_size5_0_sram[1]:9 mux_tree_tapbuf_size5_0_sram[1]:8 0.00043005 +11 mux_tree_tapbuf_size5_0_sram[1]:7 mux_tree_tapbuf_size5_0_sram[1]:6 0.0045 +12 mux_tree_tapbuf_size5_0_sram[1]:8 mux_tree_tapbuf_size5_0_sram[1]:7 0.00341 +13 mux_tree_tapbuf_size5_0_sram[1]:6 mux_bottom_track_3\/mux_l2_in_1_:S 0.152 +14 mux_tree_tapbuf_size5_0_sram[1]:12 mux_tree_tapbuf_size5_0_sram[1]:11 0.0001847826 +15 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:12 0.0045 +16 mux_tree_tapbuf_size5_0_sram[1]:13 mux_tree_tapbuf_size5_0_sram[1]:10 0.001770089 +17 mux_tree_tapbuf_size5_0_sram[1]:11 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_2_:D 0.152 +18 mux_tree_tapbuf_size5_0_sram[1]:4 mux_bottom_track_3\/mux_l2_in_0_:S 0.152 +19 mux_tree_tapbuf_size5_0_sram[1]:5 mux_tree_tapbuf_size5_0_sram[1]:4 0.000125 + +*END + +*D_NET mux_tree_tapbuf_size6_mem_0_ccff_tail[0] 0.0008204328 //LENGTH 6.800 LUMPCC 0.0001458649 DR + +*CONN +*I mem_bottom_track_1\/FTB_1__16:X O *L 0 *C 11.265 42.160 +*I mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 8.455 39.100 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 *C 8.492 39.100 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 *C 10.075 39.100 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 *C 10.120 39.145 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 *C 10.120 42.115 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 *C 10.165 42.160 +*N mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 *C 11.228 42.160 + +*CAP +0 mem_bottom_track_1\/FTB_1__16:X 1e-06 +1 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 7.383368e-05 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 7.383368e-05 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.0001783222 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0001783222 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 8.412809e-05 +7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 8.412809e-05 +8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 7.293244e-05 +9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 7.293244e-05 + +*RES +0 mem_bottom_track_1\/FTB_1__16:X mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:7 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 0.0009486608 +2 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 0.0045 +3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 0.002651786 +4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 0.001412946 +5 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:4 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 0.0045 +6 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 mem_bottom_track_3\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 + +*END + +*D_NET mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001030609 //LENGTH 7.950 LUMPCC 0.0003928368 DR + +*CONN +*I mux_bottom_track_1\/mux_l2_in_0_:X O *L 0 *C 21.335 33.660 +*I mux_bottom_track_1\/mux_l3_in_0_:A1 I *L 0.00198 *C 22.540 39.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 22.540 39.780 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 22.540 39.735 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 22.540 33.705 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 22.495 33.660 +*N mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 21.373 33.660 + +*CAP +0 mux_bottom_track_1\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_1\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 3.275675e-05 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0002561299 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0002561299 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 4.537776e-05 +6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 4.537776e-05 +7 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_tree_tapbuf_size6_0_sram[1]:13 0.0001399483 +8 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_tree_tapbuf_size6_0_sram[1]:14 0.0001399483 +9 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:17 5.647006e-05 +10 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_4_X[0]:16 5.647006e-05 + +*RES +0 mux_bottom_track_1\/mux_l2_in_0_:X mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.152 +1 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.001002232 +2 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0045 +3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.005383928 +4 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_1\/mux_l3_in_0_:A1 0.152 +5 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_1/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0045 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0007161289 //LENGTH 4.355 LUMPCC 0.0002980113 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_2_:X O *L 0 *C 28.805 41.480 +*I mux_bottom_track_5\/mux_l2_in_1_:A1 I *L 0.00198 *C 27.240 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 27.277 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 28.935 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 28.980 39.825 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 28.980 41.435 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 28.980 41.480 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 28.805 41.480 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_2_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_1_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001076055 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001076055 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 3.857029e-05 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 3.857029e-05 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.844664e-05 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 6.531931e-05 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 bottom_left_grid_pin_35_[0]:15 5.072064e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 bottom_left_grid_pin_35_[0]:12 5.072064e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 bottom_left_grid_pin_41_[0]:26 5.072064e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 bottom_left_grid_pin_41_[0]:25 5.072064e-05 +12 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_tree_tapbuf_size6_1_sram[1]:7 4.756438e-05 +13 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_tree_tapbuf_size6_1_sram[1]:8 4.756438e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_2_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_5\/mux_l2_in_1_:A1 0.152 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.001479911 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.0014375 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0] 0.0009586371 //LENGTH 7.735 LUMPCC 0.0001683221 DR + +*CONN +*I mux_bottom_track_7\/mux_l2_in_0_:X O *L 0 *C 35.135 11.560 +*I mux_bottom_track_7\/mux_l3_in_0_:A1 I *L 0.00198 *C 37.360 7.140 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 *C 37.323 7.140 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 *C 35.005 7.140 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 *C 34.960 7.185 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 *C 34.960 11.515 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 *C 34.960 11.560 +*N mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 *C 35.135 11.560 + +*CAP +0 mux_bottom_track_7\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_7\/mux_l3_in_0_:A1 1e-06 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.0001523977 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0001523977 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.00018213 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.00018213 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 5.941989e-05 +7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 5.983977e-05 +8 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:7 5.437142e-05 +9 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_tree_tapbuf_size5_1_sram[1]:12 2.978964e-05 +10 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:8 5.437142e-05 +11 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_tree_tapbuf_size5_1_sram[1]:13 2.978964e-05 + +*RES +0 mux_bottom_track_7\/mux_l2_in_0_:X mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.152 +1 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 mux_bottom_track_7\/mux_l3_in_0_:A1 0.152 +2 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:2 0.002069197 +3 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:3 0.0045 +4 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 0.0045 +5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:5 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:4 0.003866072 +6 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:7 mux_bottom_track_7/sky130_fd_sc_hd__mux2_1_2_X[0]:6 9.51087e-05 + +*END + +*D_NET mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0] 0.001383643 //LENGTH 11.370 LUMPCC 0 DR + +*CONN +*I mux_bottom_track_11\/mux_l2_in_0_:X O *L 0 *C 60.545 9.180 +*I mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 66.485 4.255 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 66.485 4.255 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 66.240 4.420 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 66.240 4.465 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 66.240 9.135 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 66.195 9.180 +*N mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 60.583 9.180 + +*CAP +0 mux_bottom_track_11\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.095942e-05 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.24298e-05 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002551219 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002551219 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0003840053 +7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0003840053 + +*RES +0 mux_bottom_track_11\/mux_l2_in_0_:X mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001331522 +2 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +3 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.004169643 +5 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.005011161 +6 mux_bottom_track_11/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_11\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0] 0.008138612 //LENGTH 64.230 LUMPCC 0.002840791 DR + +*CONN +*I mux_bottom_track_17\/mux_l2_in_0_:X O *L 0 *C 38.005 46.920 +*I mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 59.160 6.650 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 58.480 8.160 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 59.160 6.650 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 58.910 6.770 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 58.880 6.845 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 58.880 8.103 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 58.880 8.160 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 58.880 8.168 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 58.880 45.553 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 58.860 45.560 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 37.727 45.560 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 37.720 45.617 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 37.720 46.875 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:14 *C 37.720 46.920 +*N mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:15 *C 38.005 46.920 + +*CAP +0 mux_bottom_track_17\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 6.29646e-05 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.068955e-05 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 5.070668e-05 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 9.073089e-05 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 9.073089e-05 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 6.29646e-05 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.001634856 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.001634856 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0006284547 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0006284547 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:12 9.710609e-05 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:13 9.710609e-05 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:14 6.345757e-05 +15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:15 6.274105e-05 +16 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chany_bottom_in[6]:10 0.000472595 +17 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chany_bottom_in[6]:11 1.89446e-05 +18 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_bottom_in[6]:11 0.000472595 +19 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chany_bottom_in[6]:12 1.89446e-05 +20 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 chanx_left_in[5] 0.000175263 +21 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 chanx_left_in[5]:8 0.000175263 +22 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 chanx_left_in[11]:8 0.0003567499 +23 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 chanx_left_in[11]:7 0.0003567499 +24 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:8 0.0003968434 +25 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_2_X[0]:7 0.0003968434 + +*RES +0 mux_bottom_track_17\/mux_l2_in_0_:X mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:15 0.152 +1 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:15 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:14 0.0001548913 +2 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.0045 +3 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.001122768 +4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.00341 +5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.003310758 +6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.005856983 +8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.00341 +9 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:2 5.69697e-05 +10 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +11 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.001122768 +12 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00015625 +13 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0045 +14 mux_bottom_track_17/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_17\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0] 0.002201327 //LENGTH 16.355 LUMPCC 0.0007830024 DR + +*CONN +*I mux_bottom_track_33\/mux_l1_in_0_:X O *L 0 *C 33.295 55.760 +*I mux_bottom_track_33\/mux_l2_in_0_:A1 I *L 0.00198 *C 28.620 45.220 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 28.620 45.220 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 28.520 45.560 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 30.775 45.560 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 30.820 45.605 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 30.820 55.715 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 30.865 55.760 +*N mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 *C 33.258 55.760 + +*CAP +0 mux_bottom_track_33\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_33\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 5.746839e-05 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0001937942 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0001655342 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003168324 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0003168324 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001829313 +8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.0001829313 +9 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_right_grid_pin_1_[0]:9 0.0001262151 +10 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_right_grid_pin_1_[0]:10 0.0001262151 +11 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 bottom_left_grid_pin_35_[0]:8 0.0001121003 +12 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 bottom_left_grid_pin_35_[0]:11 1.078782e-05 +13 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 bottom_left_grid_pin_35_[0]:11 0.0001121003 +14 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 bottom_left_grid_pin_35_[0]:12 1.078782e-05 +15 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_tree_tapbuf_size2_9_sram[1]:6 1.937161e-05 +16 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size2_9_sram[1]:5 1.937161e-05 +17 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_9_sram[1]:7 6.538825e-05 +18 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size2_9_sram[1]:11 5.763811e-05 +19 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_9_sram[1]:10 5.763811e-05 +20 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_tree_tapbuf_size2_9_sram[1]:11 6.538825e-05 + +*RES +0 mux_bottom_track_33\/mux_l1_in_0_:X mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 0.152 +1 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:8 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.002136161 +2 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0045 +3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.009026786 +4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.002013393 +5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0045 +6 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_33\/mux_l2_in_0_:A1 0.152 +7 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_33/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0003035715 + +*END + +*D_NET chany_bottom_in[13] 0.01568453 //LENGTH 128.620 LUMPCC 0.005997438 DR + +*CONN +*P chany_bottom_in[13] I *L 0.29796 *C 68.080 1.290 +*I BUFT_RR_53:A I *L 0.001776 *C 10.120 66.640 +*N chany_bottom_in[13]:2 *C 67.370 2.720 +*N chany_bottom_in[13]:3 *C 10.083 66.640 +*N chany_bottom_in[13]:4 *C 8.785 66.640 +*N chany_bottom_in[13]:5 *C 8.740 66.595 +*N chany_bottom_in[13]:6 *C 8.740 66.017 +*N chany_bottom_in[13]:7 *C 8.748 65.960 +*N chany_bottom_in[13]:8 *C 58.575 65.960 +*N chany_bottom_in[13]:9 *C 68.060 65.960 +*N chany_bottom_in[13]:10 *C 68.080 65.953 +*N chany_bottom_in[13]:11 *C 68.080 52.555 +*N chany_bottom_in[13]:12 *C 68.080 2.728 +*N chany_bottom_in[13]:13 *C 68.078 2.720 +*N chany_bottom_in[13]:14 *C 68.080 2.663 + +*CAP +0 chany_bottom_in[13] 9.514857e-05 +1 BUFT_RR_53:A 1e-06 +2 chany_bottom_in[13]:2 0.0001284224 +3 chany_bottom_in[13]:3 0.0001012 +4 chany_bottom_in[13]:4 0.0001012 +5 chany_bottom_in[13]:5 5.6811e-05 +6 chany_bottom_in[13]:6 5.6811e-05 +7 chany_bottom_in[13]:7 0.001426031 +8 chany_bottom_in[13]:8 0.001753096 +9 chany_bottom_in[13]:9 0.0003270646 +10 chany_bottom_in[13]:10 0.0005915746 +11 chany_bottom_in[13]:11 0.002708368 +12 chany_bottom_in[13]:12 0.002116794 +13 chany_bottom_in[13]:13 0.0001284224 +14 chany_bottom_in[13]:14 9.514857e-05 +15 chany_bottom_in[13] chany_bottom_in[4] 4.625613e-07 +16 chany_bottom_in[13]:10 chany_bottom_in[4]:19 0.0001222632 +17 chany_bottom_in[13]:10 chany_bottom_in[4]:20 2.038945e-05 +18 chany_bottom_in[13]:12 chany_bottom_in[4]:21 0.0006634632 +19 chany_bottom_in[13]:14 chany_bottom_in[4]:23 4.625613e-07 +20 chany_bottom_in[13]:11 chany_bottom_in[4]:20 0.0007857265 +21 chany_bottom_in[13]:11 chany_bottom_in[4]:21 2.038945e-05 +22 chany_bottom_in[13]:7 chany_bottom_in[7]:15 0.0004755738 +23 chany_bottom_in[13]:9 chany_bottom_in[7]:16 6.169865e-05 +24 chany_bottom_in[13]:9 chany_bottom_in[7]:17 6.679678e-05 +25 chany_bottom_in[13]:8 chany_bottom_in[7]:15 6.169865e-05 +26 chany_bottom_in[13]:8 chany_bottom_in[7]:16 0.0005423705 +27 chany_bottom_in[13]:7 prog_clk[0]:116 0.0002840011 +28 chany_bottom_in[13]:10 prog_clk[0]:251 1.147026e-05 +29 chany_bottom_in[13]:12 prog_clk[0]:276 1.387318e-05 +30 chany_bottom_in[13]:8 prog_clk[0]:117 0.0002840011 +31 chany_bottom_in[13]:11 prog_clk[0]:252 1.147026e-05 +32 chany_bottom_in[13]:11 prog_clk[0]:281 1.387318e-05 +33 chany_bottom_in[13]:7 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.001207659 +34 chany_bottom_in[13]:9 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 7.106716e-05 +35 chany_bottom_in[13]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:6 7.106716e-05 +36 chany_bottom_in[13]:8 mux_left_track_9/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.001207659 + +*RES +0 chany_bottom_in[13] chany_bottom_in[13]:14 0.001225446 +1 chany_bottom_in[13]:3 BUFT_RR_53:A 0.152 +2 chany_bottom_in[13]:4 chany_bottom_in[13]:3 0.001158482 +3 chany_bottom_in[13]:5 chany_bottom_in[13]:4 0.0045 +4 chany_bottom_in[13]:6 chany_bottom_in[13]:5 0.000515625 +5 chany_bottom_in[13]:7 chany_bottom_in[13]:6 0.00341 +6 chany_bottom_in[13]:9 chany_bottom_in[13]:8 0.001485983 +7 chany_bottom_in[13]:10 chany_bottom_in[13]:9 0.00341 +8 chany_bottom_in[13]:13 chany_bottom_in[13]:12 0.00341 +9 chany_bottom_in[13]:13 chany_bottom_in[13]:2 0.0001039141 +10 chany_bottom_in[13]:12 chany_bottom_in[13]:11 0.007806308 +11 chany_bottom_in[13]:14 chany_bottom_in[13]:13 0.00341 +12 chany_bottom_in[13]:8 chany_bottom_in[13]:7 0.007806308 +13 chany_bottom_in[13]:11 chany_bottom_in[13]:10 0.002098942 + +*END + +*D_NET chanx_left_in[10] 0.007007259 //LENGTH 41.000 LUMPCC 0.003874513 DR + +*CONN +*P chanx_left_in[10] I *L 0.29796 *C 1.230 36.720 +*I mux_bottom_track_19\/mux_l1_in_0_:A0 I *L 0.001631 *C 38.355 33.660 +*N chanx_left_in[10]:2 *C 38.318 33.660 +*N chanx_left_in[10]:3 *C 34.085 33.660 +*N chanx_left_in[10]:4 *C 34.040 33.705 +*N chanx_left_in[10]:5 *C 34.040 36.663 +*N chanx_left_in[10]:6 *C 34.032 36.720 + +*CAP +0 chanx_left_in[10] 0.001140603 +1 mux_bottom_track_19\/mux_l1_in_0_:A0 1e-06 +2 chanx_left_in[10]:2 0.0002972819 +3 chanx_left_in[10]:3 0.0002972819 +4 chanx_left_in[10]:4 0.0001279884 +5 chanx_left_in[10]:5 0.0001279884 +6 chanx_left_in[10]:6 0.001140603 +7 chanx_left_in[10] chanx_left_in[12] 2.418709e-06 +8 chanx_left_in[10] chanx_left_in[12]:8 0.0003329268 +9 chanx_left_in[10]:6 chanx_left_in[12]:11 2.418709e-06 +10 chanx_left_in[10]:6 chanx_left_in[12]:7 0.0003329268 +11 chanx_left_in[10] chanx_left_in[18] 2.742029e-05 +12 chanx_left_in[10] chanx_left_in[18]:6 0.001487702 +13 chanx_left_in[10]:6 chanx_left_in[18]:5 0.001487702 +14 chanx_left_in[10]:6 chanx_left_in[18]:7 2.742029e-05 +15 chanx_left_in[10]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:3 8.678927e-05 +16 chanx_left_in[10]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_3_X[0]:4 8.678927e-05 + +*RES +0 chanx_left_in[10] chanx_left_in[10]:6 0.005139058 +1 chanx_left_in[10]:2 mux_bottom_track_19\/mux_l1_in_0_:A0 0.152 +2 chanx_left_in[10]:3 chanx_left_in[10]:2 0.003779018 +3 chanx_left_in[10]:4 chanx_left_in[10]:3 0.0045 +4 chanx_left_in[10]:5 chanx_left_in[10]:4 0.002640625 +5 chanx_left_in[10]:6 chanx_left_in[10]:5 0.00341 + +*END + +*D_NET left_top_grid_pin_1_[0] 0.01645426 //LENGTH 152.365 LUMPCC 0.0001868145 DR + +*CONN +*P left_top_grid_pin_1_[0] I *L 0.29796 *C 2.300 102.035 +*I mux_left_track_25\/mux_l1_in_0_:A0 I *L 0.001631 *C 30.190 80.920 +*I mux_left_track_9\/mux_l1_in_0_:A0 I *L 0.001631 *C 76.535 64.260 +*I mux_left_track_5\/mux_l1_in_0_:A0 I *L 0.001631 *C 85.850 42.840 +*I mux_left_track_1\/mux_l1_in_0_:A0 I *L 0.001631 *C 88.495 47.940 +*N left_top_grid_pin_1_[0]:5 *C 88.458 47.940 +*N left_top_grid_pin_1_[0]:6 *C 87.860 47.940 +*N left_top_grid_pin_1_[0]:7 *C 87.860 47.600 +*N left_top_grid_pin_1_[0]:8 *C 85.888 42.840 +*N left_top_grid_pin_1_[0]:9 *C 86.435 42.840 +*N left_top_grid_pin_1_[0]:10 *C 86.480 42.885 +*N left_top_grid_pin_1_[0]:11 *C 86.480 47.555 +*N left_top_grid_pin_1_[0]:12 *C 86.480 47.600 +*N left_top_grid_pin_1_[0]:13 *C 86.480 48.280 +*N left_top_grid_pin_1_[0]:14 *C 76.405 48.280 +*N left_top_grid_pin_1_[0]:15 *C 76.360 48.325 +*N left_top_grid_pin_1_[0]:16 *C 76.360 50.660 +*N left_top_grid_pin_1_[0]:17 *C 76.820 50.660 +*N left_top_grid_pin_1_[0]:18 *C 76.820 59.500 +*N left_top_grid_pin_1_[0]:19 *C 76.360 59.500 +*N left_top_grid_pin_1_[0]:20 *C 76.535 64.260 +*N left_top_grid_pin_1_[0]:21 *C 76.360 64.260 +*N left_top_grid_pin_1_[0]:22 *C 76.360 64.260 +*N left_top_grid_pin_1_[0]:23 *C 76.360 80.875 +*N left_top_grid_pin_1_[0]:24 *C 76.315 80.920 +*N left_top_grid_pin_1_[0]:25 *C 30.190 80.920 +*N left_top_grid_pin_1_[0]:26 *C 30.405 80.920 +*N left_top_grid_pin_1_[0]:27 *C 30.360 80.965 +*N left_top_grid_pin_1_[0]:28 *C 30.360 101.615 +*N left_top_grid_pin_1_[0]:29 *C 30.360 101.660 +*N left_top_grid_pin_1_[0]:30 *C 30.360 102.000 +*N left_top_grid_pin_1_[0]:31 *C 9.660 102.000 +*N left_top_grid_pin_1_[0]:32 *C 9.660 101.660 +*N left_top_grid_pin_1_[0]:33 *C 2.345 101.660 +*N left_top_grid_pin_1_[0]:34 *C 2.300 101.705 + +*CAP +0 left_top_grid_pin_1_[0] 2.965148e-05 +1 mux_left_track_25\/mux_l1_in_0_:A0 1e-06 +2 mux_left_track_9\/mux_l1_in_0_:A0 1e-06 +3 mux_left_track_5\/mux_l1_in_0_:A0 1e-06 +4 mux_left_track_1\/mux_l1_in_0_:A0 1e-06 +5 left_top_grid_pin_1_[0]:5 6.03731e-05 +6 left_top_grid_pin_1_[0]:6 8.541642e-05 +7 left_top_grid_pin_1_[0]:7 0.0001356633 +8 left_top_grid_pin_1_[0]:8 5.844369e-05 +9 left_top_grid_pin_1_[0]:9 5.844369e-05 +10 left_top_grid_pin_1_[0]:10 0.0002729741 +11 left_top_grid_pin_1_[0]:11 0.0002729741 +12 left_top_grid_pin_1_[0]:12 0.0001548015 +13 left_top_grid_pin_1_[0]:13 0.000677913 +14 left_top_grid_pin_1_[0]:14 0.0006337315 +15 left_top_grid_pin_1_[0]:15 0.0001425989 +16 left_top_grid_pin_1_[0]:16 0.0001698619 +17 left_top_grid_pin_1_[0]:17 0.0005178865 +18 left_top_grid_pin_1_[0]:18 0.0005196776 +19 left_top_grid_pin_1_[0]:19 0.0002942284 +20 left_top_grid_pin_1_[0]:20 5.768551e-05 +21 left_top_grid_pin_1_[0]:21 5.996364e-05 +22 left_top_grid_pin_1_[0]:22 0.001111636 +23 left_top_grid_pin_1_[0]:23 0.0008153863 +24 left_top_grid_pin_1_[0]:24 0.002596779 +25 left_top_grid_pin_1_[0]:25 4.612091e-05 +26 left_top_grid_pin_1_[0]:26 0.002616744 +27 left_top_grid_pin_1_[0]:27 0.0009566144 +28 left_top_grid_pin_1_[0]:28 0.0009566144 +29 left_top_grid_pin_1_[0]:29 4.840012e-05 +30 left_top_grid_pin_1_[0]:30 0.001038944 +31 left_top_grid_pin_1_[0]:31 0.001037335 +32 left_top_grid_pin_1_[0]:32 0.0004141026 +33 left_top_grid_pin_1_[0]:33 0.0003928336 +34 left_top_grid_pin_1_[0]:34 2.965148e-05 +35 left_top_grid_pin_1_[0]:26 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:6 9.340723e-05 +36 left_top_grid_pin_1_[0]:24 mux_tree_tapbuf_size2_mem_16_ccff_tail[0]:7 9.340723e-05 + +*RES +0 left_top_grid_pin_1_[0] left_top_grid_pin_1_[0]:34 0.0002946429 +1 left_top_grid_pin_1_[0]:14 left_top_grid_pin_1_[0]:13 0.008995537 +2 left_top_grid_pin_1_[0]:15 left_top_grid_pin_1_[0]:14 0.0045 +3 left_top_grid_pin_1_[0]:33 left_top_grid_pin_1_[0]:32 0.00653125 +4 left_top_grid_pin_1_[0]:34 left_top_grid_pin_1_[0]:33 0.0045 +5 left_top_grid_pin_1_[0]:29 left_top_grid_pin_1_[0]:28 0.0045 +6 left_top_grid_pin_1_[0]:28 left_top_grid_pin_1_[0]:27 0.0184375 +7 left_top_grid_pin_1_[0]:26 left_top_grid_pin_1_[0]:25 0.0001168478 +8 left_top_grid_pin_1_[0]:26 left_top_grid_pin_1_[0]:24 0.04099108 +9 left_top_grid_pin_1_[0]:27 left_top_grid_pin_1_[0]:26 0.0045 +10 left_top_grid_pin_1_[0]:12 left_top_grid_pin_1_[0]:11 0.0045 +11 left_top_grid_pin_1_[0]:12 left_top_grid_pin_1_[0]:7 0.001232143 +12 left_top_grid_pin_1_[0]:11 left_top_grid_pin_1_[0]:10 0.004169643 +13 left_top_grid_pin_1_[0]:9 left_top_grid_pin_1_[0]:8 0.0004888393 +14 left_top_grid_pin_1_[0]:10 left_top_grid_pin_1_[0]:9 0.0045 +15 left_top_grid_pin_1_[0]:8 mux_left_track_5\/mux_l1_in_0_:A0 0.152 +16 left_top_grid_pin_1_[0]:21 left_top_grid_pin_1_[0]:20 9.51087e-05 +17 left_top_grid_pin_1_[0]:22 left_top_grid_pin_1_[0]:21 0.0045 +18 left_top_grid_pin_1_[0]:22 left_top_grid_pin_1_[0]:19 0.00425 +19 left_top_grid_pin_1_[0]:20 mux_left_track_9\/mux_l1_in_0_:A0 0.152 +20 left_top_grid_pin_1_[0]:5 mux_left_track_1\/mux_l1_in_0_:A0 0.152 +21 left_top_grid_pin_1_[0]:25 mux_left_track_25\/mux_l1_in_0_:A0 0.152 +22 left_top_grid_pin_1_[0]:24 left_top_grid_pin_1_[0]:23 0.0045 +23 left_top_grid_pin_1_[0]:23 left_top_grid_pin_1_[0]:22 0.01483482 +24 left_top_grid_pin_1_[0]:32 left_top_grid_pin_1_[0]:31 0.0003035715 +25 left_top_grid_pin_1_[0]:31 left_top_grid_pin_1_[0]:30 0.01848214 +26 left_top_grid_pin_1_[0]:30 left_top_grid_pin_1_[0]:29 0.0003035715 +27 left_top_grid_pin_1_[0]:13 left_top_grid_pin_1_[0]:12 0.0006071429 +28 left_top_grid_pin_1_[0]:7 left_top_grid_pin_1_[0]:6 0.0003035715 +29 left_top_grid_pin_1_[0]:6 left_top_grid_pin_1_[0]:5 0.0005334822 +30 left_top_grid_pin_1_[0]:16 left_top_grid_pin_1_[0]:15 0.002084821 +31 left_top_grid_pin_1_[0]:17 left_top_grid_pin_1_[0]:16 0.0004107143 +32 left_top_grid_pin_1_[0]:19 left_top_grid_pin_1_[0]:18 0.0004107143 +33 left_top_grid_pin_1_[0]:18 left_top_grid_pin_1_[0]:17 0.007892858 + +*END + +*D_NET mux_tree_tapbuf_size2_14_sram[0] 0.003167848 //LENGTH 25.485 LUMPCC 0 DR + +*CONN +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 84.485 39.100 +*I mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 76.535 49.980 +*I mux_left_track_1\/mux_l1_in_0_:S I *L 0.00357 *C 89.600 46.920 +*N mux_tree_tapbuf_size2_14_sram[0]:3 *C 89.562 46.920 +*N mux_tree_tapbuf_size2_14_sram[0]:4 *C 76.573 49.980 +*N mux_tree_tapbuf_size2_14_sram[0]:5 *C 77.235 49.980 +*N mux_tree_tapbuf_size2_14_sram[0]:6 *C 77.280 49.935 +*N mux_tree_tapbuf_size2_14_sram[0]:7 *C 77.280 46.965 +*N mux_tree_tapbuf_size2_14_sram[0]:8 *C 77.325 46.920 +*N mux_tree_tapbuf_size2_14_sram[0]:9 *C 84.640 46.920 +*N mux_tree_tapbuf_size2_14_sram[0]:10 *C 84.640 46.875 +*N mux_tree_tapbuf_size2_14_sram[0]:11 *C 84.640 39.145 +*N mux_tree_tapbuf_size2_14_sram[0]:12 *C 84.640 39.100 +*N mux_tree_tapbuf_size2_14_sram[0]:13 *C 84.485 39.100 + +*CAP +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +2 mux_left_track_1\/mux_l1_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_14_sram[0]:3 0.0003622062 +4 mux_tree_tapbuf_size2_14_sram[0]:4 6.305966e-05 +5 mux_tree_tapbuf_size2_14_sram[0]:5 6.305966e-05 +6 mux_tree_tapbuf_size2_14_sram[0]:6 0.0001808088 +7 mux_tree_tapbuf_size2_14_sram[0]:7 0.0001808088 +8 mux_tree_tapbuf_size2_14_sram[0]:8 0.0004520091 +9 mux_tree_tapbuf_size2_14_sram[0]:9 0.0008434855 +10 mux_tree_tapbuf_size2_14_sram[0]:10 0.0004608969 +11 mux_tree_tapbuf_size2_14_sram[0]:11 0.0004608969 +12 mux_tree_tapbuf_size2_14_sram[0]:12 5.09463e-05 +13 mux_tree_tapbuf_size2_14_sram[0]:13 4.66699e-05 + +*RES +0 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_14_sram[0]:13 0.152 +1 mux_tree_tapbuf_size2_14_sram[0]:3 mux_left_track_1\/mux_l1_in_0_:S 0.152 +2 mux_tree_tapbuf_size2_14_sram[0]:8 mux_tree_tapbuf_size2_14_sram[0]:7 0.0045 +3 mux_tree_tapbuf_size2_14_sram[0]:7 mux_tree_tapbuf_size2_14_sram[0]:6 0.002651786 +4 mux_tree_tapbuf_size2_14_sram[0]:5 mux_tree_tapbuf_size2_14_sram[0]:4 0.0005915179 +5 mux_tree_tapbuf_size2_14_sram[0]:6 mux_tree_tapbuf_size2_14_sram[0]:5 0.0045 +6 mux_tree_tapbuf_size2_14_sram[0]:4 mem_left_track_1\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +7 mux_tree_tapbuf_size2_14_sram[0]:9 mux_tree_tapbuf_size2_14_sram[0]:8 0.00653125 +8 mux_tree_tapbuf_size2_14_sram[0]:9 mux_tree_tapbuf_size2_14_sram[0]:3 0.00439509 +9 mux_tree_tapbuf_size2_14_sram[0]:10 mux_tree_tapbuf_size2_14_sram[0]:9 0.0045 +10 mux_tree_tapbuf_size2_14_sram[0]:12 mux_tree_tapbuf_size2_14_sram[0]:11 0.0045 +11 mux_tree_tapbuf_size2_14_sram[0]:11 mux_tree_tapbuf_size2_14_sram[0]:10 0.006901786 +12 mux_tree_tapbuf_size2_14_sram[0]:13 mux_tree_tapbuf_size2_14_sram[0]:12 8.423914e-05 + +*END + +*D_NET mux_tree_tapbuf_size2_2_sram[1] 0.002236889 //LENGTH 19.210 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q O *L 0 *C 48.605 64.260 +*I mem_bottom_track_15\/FTB_9__24:A I *L 0.001746 *C 40.940 58.480 +*I mux_bottom_track_15\/mux_l2_in_0_:S I *L 0.00357 *C 38.080 61.200 +*N mux_tree_tapbuf_size2_2_sram[1]:3 *C 38.117 61.200 +*N mux_tree_tapbuf_size2_2_sram[1]:4 *C 40.903 58.480 +*N mux_tree_tapbuf_size2_2_sram[1]:5 *C 40.065 58.480 +*N mux_tree_tapbuf_size2_2_sram[1]:6 *C 40.020 58.525 +*N mux_tree_tapbuf_size2_2_sram[1]:7 *C 40.020 61.155 +*N mux_tree_tapbuf_size2_2_sram[1]:8 *C 40.020 61.230 +*N mux_tree_tapbuf_size2_2_sram[1]:9 *C 40.020 61.540 +*N mux_tree_tapbuf_size2_2_sram[1]:10 *C 47.335 61.540 +*N mux_tree_tapbuf_size2_2_sram[1]:11 *C 47.380 61.585 +*N mux_tree_tapbuf_size2_2_sram[1]:12 *C 47.380 64.215 +*N mux_tree_tapbuf_size2_2_sram[1]:13 *C 47.425 64.260 +*N mux_tree_tapbuf_size2_2_sram[1]:14 *C 48.568 64.260 + +*CAP +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q 1e-06 +1 mem_bottom_track_15\/FTB_9__24:A 1e-06 +2 mux_bottom_track_15\/mux_l2_in_0_:S 1e-06 +3 mux_tree_tapbuf_size2_2_sram[1]:3 0.0001400981 +4 mux_tree_tapbuf_size2_2_sram[1]:4 9.81929e-05 +5 mux_tree_tapbuf_size2_2_sram[1]:5 9.81929e-05 +6 mux_tree_tapbuf_size2_2_sram[1]:6 0.0001961512 +7 mux_tree_tapbuf_size2_2_sram[1]:7 0.0001961512 +8 mux_tree_tapbuf_size2_2_sram[1]:8 0.0001704999 +9 mux_tree_tapbuf_size2_2_sram[1]:9 0.0004367166 +10 mux_tree_tapbuf_size2_2_sram[1]:10 0.0004063148 +11 mux_tree_tapbuf_size2_2_sram[1]:11 0.0001586915 +12 mux_tree_tapbuf_size2_2_sram[1]:12 0.0001586915 +13 mux_tree_tapbuf_size2_2_sram[1]:13 8.709446e-05 +14 mux_tree_tapbuf_size2_2_sram[1]:14 8.709446e-05 + +*RES +0 mem_bottom_track_15\/sky130_fd_sc_hd__dfxbp_1_1_:Q mux_tree_tapbuf_size2_2_sram[1]:14 0.152 +1 mux_tree_tapbuf_size2_2_sram[1]:10 mux_tree_tapbuf_size2_2_sram[1]:9 0.006531251 +2 mux_tree_tapbuf_size2_2_sram[1]:11 mux_tree_tapbuf_size2_2_sram[1]:10 0.0045 +3 mux_tree_tapbuf_size2_2_sram[1]:13 mux_tree_tapbuf_size2_2_sram[1]:12 0.0045 +4 mux_tree_tapbuf_size2_2_sram[1]:12 mux_tree_tapbuf_size2_2_sram[1]:11 0.002348214 +5 mux_tree_tapbuf_size2_2_sram[1]:14 mux_tree_tapbuf_size2_2_sram[1]:13 0.001020089 +6 mux_tree_tapbuf_size2_2_sram[1]:3 mux_bottom_track_15\/mux_l2_in_0_:S 0.152 +7 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:7 0.0045 +8 mux_tree_tapbuf_size2_2_sram[1]:8 mux_tree_tapbuf_size2_2_sram[1]:3 0.001698661 +9 mux_tree_tapbuf_size2_2_sram[1]:7 mux_tree_tapbuf_size2_2_sram[1]:6 0.002348214 +10 mux_tree_tapbuf_size2_2_sram[1]:5 mux_tree_tapbuf_size2_2_sram[1]:4 0.0007477679 +11 mux_tree_tapbuf_size2_2_sram[1]:6 mux_tree_tapbuf_size2_2_sram[1]:5 0.0045 +12 mux_tree_tapbuf_size2_2_sram[1]:4 mem_bottom_track_15\/FTB_9__24:A 0.152 +13 mux_tree_tapbuf_size2_2_sram[1]:9 mux_tree_tapbuf_size2_2_sram[1]:8 0.0002767857 + +*END + +*D_NET mux_tree_tapbuf_size2_9_sram[0] 0.001627677 //LENGTH 12.310 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q O *L 0 *C 26.530 55.420 +*I mux_bottom_track_31\/mux_l1_in_0_:S I *L 0.00357 *C 23.360 51.000 +*I mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D I *L 0.001695 *C 26.855 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:3 *C 26.730 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:4 *C 23.360 51.000 +*N mux_tree_tapbuf_size2_9_sram[0]:5 *C 23.460 50.660 +*N mux_tree_tapbuf_size2_9_sram[0]:6 *C 22.900 50.660 +*N mux_tree_tapbuf_size2_9_sram[0]:7 *C 22.878 51.000 +*N mux_tree_tapbuf_size2_9_sram[0]:8 *C 22.560 50.992 +*N mux_tree_tapbuf_size2_9_sram[0]:9 *C 22.540 51.045 +*N mux_tree_tapbuf_size2_9_sram[0]:10 *C 22.540 53.335 +*N mux_tree_tapbuf_size2_9_sram[0]:11 *C 22.585 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:12 *C 26.635 53.380 +*N mux_tree_tapbuf_size2_9_sram[0]:13 *C 26.680 53.425 +*N mux_tree_tapbuf_size2_9_sram[0]:14 *C 26.680 55.375 +*N mux_tree_tapbuf_size2_9_sram[0]:15 *C 26.680 55.420 +*N mux_tree_tapbuf_size2_9_sram[0]:16 *C 26.530 55.420 + +*CAP +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q 1e-06 +1 mux_bottom_track_31\/mux_l1_in_0_:S 1e-06 +2 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D 1e-06 +3 mux_tree_tapbuf_size2_9_sram[0]:3 2.340799e-05 +4 mux_tree_tapbuf_size2_9_sram[0]:4 5.918253e-05 +5 mux_tree_tapbuf_size2_9_sram[0]:5 8.355672e-05 +6 mux_tree_tapbuf_size2_9_sram[0]:6 6.745382e-05 +7 mux_tree_tapbuf_size2_9_sram[0]:7 6.214695e-05 +8 mux_tree_tapbuf_size2_9_sram[0]:8 4.950912e-05 +9 mux_tree_tapbuf_size2_9_sram[0]:9 0.0001697434 +10 mux_tree_tapbuf_size2_9_sram[0]:10 0.0001697434 +11 mux_tree_tapbuf_size2_9_sram[0]:11 0.0002736634 +12 mux_tree_tapbuf_size2_9_sram[0]:12 0.0002970714 +13 mux_tree_tapbuf_size2_9_sram[0]:13 0.0001296486 +14 mux_tree_tapbuf_size2_9_sram[0]:14 0.0001296486 +15 mux_tree_tapbuf_size2_9_sram[0]:15 5.69664e-05 +16 mux_tree_tapbuf_size2_9_sram[0]:16 5.293419e-05 + +*RES +0 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_0_:Q mux_tree_tapbuf_size2_9_sram[0]:16 0.152 +1 mux_tree_tapbuf_size2_9_sram[0]:16 mux_tree_tapbuf_size2_9_sram[0]:15 8.152174e-05 +2 mux_tree_tapbuf_size2_9_sram[0]:15 mux_tree_tapbuf_size2_9_sram[0]:14 0.0045 +3 mux_tree_tapbuf_size2_9_sram[0]:14 mux_tree_tapbuf_size2_9_sram[0]:13 0.001741071 +4 mux_tree_tapbuf_size2_9_sram[0]:12 mux_tree_tapbuf_size2_9_sram[0]:11 0.003616072 +5 mux_tree_tapbuf_size2_9_sram[0]:12 mux_tree_tapbuf_size2_9_sram[0]:3 8.482143e-05 +6 mux_tree_tapbuf_size2_9_sram[0]:13 mux_tree_tapbuf_size2_9_sram[0]:12 0.0045 +7 mux_tree_tapbuf_size2_9_sram[0]:8 mux_tree_tapbuf_size2_9_sram[0]:7 0.0001619898 +8 mux_tree_tapbuf_size2_9_sram[0]:9 mux_tree_tapbuf_size2_9_sram[0]:8 0.0045 +9 mux_tree_tapbuf_size2_9_sram[0]:11 mux_tree_tapbuf_size2_9_sram[0]:10 0.0045 +10 mux_tree_tapbuf_size2_9_sram[0]:10 mux_tree_tapbuf_size2_9_sram[0]:9 0.002044643 +11 mux_tree_tapbuf_size2_9_sram[0]:4 mux_bottom_track_31\/mux_l1_in_0_:S 0.152 +12 mux_tree_tapbuf_size2_9_sram[0]:3 mem_bottom_track_31\/sky130_fd_sc_hd__dfxbp_1_1_:D 0.152 +13 mux_tree_tapbuf_size2_9_sram[0]:7 mux_tree_tapbuf_size2_9_sram[0]:6 0.0003035715 +14 mux_tree_tapbuf_size2_9_sram[0]:6 mux_tree_tapbuf_size2_9_sram[0]:5 0.0005 +15 mux_tree_tapbuf_size2_9_sram[0]:5 mux_tree_tapbuf_size2_9_sram[0]:4 0.0003035715 + +*END + +*D_NET mux_tree_tapbuf_size2_mem_5_ccff_tail[0] 0.000587773 //LENGTH 4.220 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_21\/FTB_12__27:X O *L 0 *C 67.385 10.200 +*I mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 65.955 11.900 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 *C 65.955 11.900 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 *C 65.780 11.900 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 *C 65.780 11.855 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 *C 65.780 10.245 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 *C 65.825 10.200 +*N mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 *C 67.347 10.200 + +*CAP +0 mem_bottom_track_21\/FTB_12__27:X 1e-06 +1 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 5.73795e-05 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 6.293133e-05 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.0001066854 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0001066854 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.0001260457 +7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.0001260457 + +*RES +0 mem_bottom_track_21\/FTB_12__27:X mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 0.152 +1 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 mem_bottom_track_23\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +2 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:2 9.51087e-05 +3 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:3 0.0045 +4 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 0.0045 +5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:5 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:4 0.0014375 +6 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:7 mux_tree_tapbuf_size2_mem_5_ccff_tail[0]:6 0.001359375 + +*END + +*D_NET mux_tree_tapbuf_size3_mem_1_ccff_tail[0] 0.002749408 //LENGTH 20.080 LUMPCC 0.0004176837 DR + +*CONN +*I mem_bottom_track_25\/FTB_6__21:X O *L 0 *C 16.370 48.280 +*I mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D I *L 0.001695 *C 12.135 55.420 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 *C 12.098 55.420 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 *C 9.360 55.420 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 *C 9.325 55.080 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 *C 8.785 55.080 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 *C 8.740 55.035 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 *C 8.740 51.045 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 *C 8.785 51.000 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 *C 12.375 51.000 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:10 *C 12.420 50.955 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:11 *C 12.420 48.325 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 *C 12.465 48.280 +*N mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 *C 16.332 48.280 + +*CAP +0 mem_bottom_track_25\/FTB_6__21:X 1e-06 +1 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 1e-06 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.0002163657 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0002460732 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 8.966394e-05 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 5.995647e-05 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0001654756 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0001654756 +8 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 0.0002670671 +9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 0.0002670671 +10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:10 0.0001834129 +11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:11 0.0001834129 +12 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 0.0002428768 +13 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 0.0002428768 +14 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 mux_tree_tapbuf_size3_1_sram[1]:9 7.969369e-05 +15 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 mux_tree_tapbuf_size3_1_sram[1]:10 7.969369e-05 +16 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 1.305897e-05 +17 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 1.305897e-05 +18 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001160892 +19 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001160892 + +*RES +0 mem_bottom_track_25\/FTB_6__21:X mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 0.152 +1 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:13 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 0.003453125 +2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:12 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:11 0.0045 +3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:10 0.002348214 +4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 0.003205357 +5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 0.0045 +6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0045 +7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0035625 +8 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 0.0004821429 +9 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:5 0.0045 +10 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 mem_bottom_track_27\/sky130_fd_sc_hd__dfxbp_1_0_:D 0.152 +11 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 0.0002297297 +12 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:2 0.002444196 + +*END + +*D_NET mux_tree_tapbuf_size6_1_sram[2] 0.001656541 //LENGTH 12.405 LUMPCC 0 DR + +*CONN +*I mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q O *L 0 *C 40.785 28.560 +*I mem_bottom_track_5\/FTB_2__17:A I *L 0.001746 *C 40.020 25.840 +*I mux_bottom_track_5\/mux_l3_in_0_:S I *L 0.00357 *C 35.320 31.280 +*N mux_tree_tapbuf_size6_1_sram[2]:3 *C 35.358 31.280 +*N mux_tree_tapbuf_size6_1_sram[2]:4 *C 40.435 31.280 +*N mux_tree_tapbuf_size6_1_sram[2]:5 *C 40.480 31.235 +*N mux_tree_tapbuf_size6_1_sram[2]:6 *C 40.020 25.840 +*N mux_tree_tapbuf_size6_1_sram[2]:7 *C 40.020 25.885 +*N mux_tree_tapbuf_size6_1_sram[2]:8 *C 40.020 28.560 +*N mux_tree_tapbuf_size6_1_sram[2]:9 *C 40.480 28.605 +*N mux_tree_tapbuf_size6_1_sram[2]:10 *C 40.480 28.560 +*N mux_tree_tapbuf_size6_1_sram[2]:11 *C 40.785 28.560 + +*CAP +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q 1e-06 +1 mem_bottom_track_5\/FTB_2__17:A 1e-06 +2 mux_bottom_track_5\/mux_l3_in_0_:S 1e-06 +3 mux_tree_tapbuf_size6_1_sram[2]:3 0.0003129176 +4 mux_tree_tapbuf_size6_1_sram[2]:4 0.0003129176 +5 mux_tree_tapbuf_size6_1_sram[2]:5 0.0002106843 +6 mux_tree_tapbuf_size6_1_sram[2]:6 3.476549e-05 +7 mux_tree_tapbuf_size6_1_sram[2]:7 0.0001995236 +8 mux_tree_tapbuf_size6_1_sram[2]:8 0.0002355382 +9 mux_tree_tapbuf_size6_1_sram[2]:9 0.0002466989 +10 mux_tree_tapbuf_size6_1_sram[2]:10 5.104271e-05 +11 mux_tree_tapbuf_size6_1_sram[2]:11 4.945236e-05 + +*RES +0 mem_bottom_track_5\/sky130_fd_sc_hd__dfxbp_1_2_:Q mux_tree_tapbuf_size6_1_sram[2]:11 0.152 +1 mux_tree_tapbuf_size6_1_sram[2]:6 mem_bottom_track_5\/FTB_2__17:A 0.152 +2 mux_tree_tapbuf_size6_1_sram[2]:7 mux_tree_tapbuf_size6_1_sram[2]:6 0.0045 +3 mux_tree_tapbuf_size6_1_sram[2]:10 mux_tree_tapbuf_size6_1_sram[2]:9 0.0045 +4 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:8 0.0004107143 +5 mux_tree_tapbuf_size6_1_sram[2]:9 mux_tree_tapbuf_size6_1_sram[2]:5 0.002348214 +6 mux_tree_tapbuf_size6_1_sram[2]:11 mux_tree_tapbuf_size6_1_sram[2]:10 0.0001657609 +7 mux_tree_tapbuf_size6_1_sram[2]:4 mux_tree_tapbuf_size6_1_sram[2]:3 0.004533483 +8 mux_tree_tapbuf_size6_1_sram[2]:5 mux_tree_tapbuf_size6_1_sram[2]:4 0.0045 +9 mux_tree_tapbuf_size6_1_sram[2]:3 mux_bottom_track_5\/mux_l3_in_0_:S 0.152 +10 mux_tree_tapbuf_size6_1_sram[2]:8 mux_tree_tapbuf_size6_1_sram[2]:7 0.002388393 + +*END + +*D_NET mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001006242 //LENGTH 6.500 LUMPCC 0.0001906894 DR + +*CONN +*I mux_bottom_track_5\/mux_l1_in_0_:X O *L 0 *C 32.945 42.575 +*I mux_bottom_track_5\/mux_l2_in_0_:A1 I *L 0.00198 *C 30.820 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 30.820 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 30.820 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 30.360 39.780 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 30.360 42.455 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 *C 30.405 42.500 +*N mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 *C 32.945 42.575 + +*CAP +0 mux_bottom_track_5\/mux_l1_in_0_:X 1e-06 +1 mux_bottom_track_5\/mux_l2_in_0_:A1 1e-06 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 3.696696e-05 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 7.103827e-05 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0002209637 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0001846604 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.0001250647 +7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.0001748589 +8 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_1_sram[0]:14 2.632982e-05 +9 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_tree_tapbuf_size6_1_sram[0]:15 6.901487e-05 +10 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_1_sram[0]:15 2.632982e-05 +11 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_tree_tapbuf_size6_1_sram[0]:16 6.901487e-05 + +*RES +0 mux_bottom_track_5\/mux_l1_in_0_:X mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 0.152 +1 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:7 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 0.002267857 +2 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0045 +3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.002388393 +4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_bottom_track_5\/mux_l2_in_0_:A1 0.152 +5 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0045 +6 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_bottom_track_5/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0004107143 + +*END + +*D_NET mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0] 0.001862807 //LENGTH 14.940 LUMPCC 0.0001458649 DR + +*CONN +*I mux_bottom_track_3\/mux_l2_in_1_:X O *L 0 *C 6.725 38.760 +*I mux_bottom_track_3\/mux_l3_in_0_:A0 I *L 0.001631 *C 15.355 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 *C 15.318 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 *C 13.800 33.660 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 *C 13.800 34.000 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 *C 12.005 34.000 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 *C 11.960 34.045 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 *C 11.960 38.715 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 *C 11.915 38.760 +*N mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 *C 6.763 38.760 + +*CAP +0 mux_bottom_track_3\/mux_l2_in_1_:X 1e-06 +1 mux_bottom_track_3\/mux_l3_in_0_:A0 1e-06 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.0001207161 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0001481495 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.0001525144 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.000125081 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.0002698382 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0002698382 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.0003144022 +9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.0003144022 +10 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:2 7.293244e-05 +11 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_tree_tapbuf_size6_mem_0_ccff_tail[0]:3 7.293244e-05 + +*RES +0 mux_bottom_track_3\/mux_l2_in_1_:X mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 0.152 +1 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:9 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 0.004600447 +2 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 0.0045 +3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 0.004169643 +4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 0.001602679 +5 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:5 0.0045 +6 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 mux_bottom_track_3\/mux_l3_in_0_:A0 0.152 +7 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:4 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 0.0003035715 +8 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:3 mux_bottom_track_3/sky130_fd_sc_hd__mux2_1_3_X[0]:2 0.001354911 + +*END + +*D_NET mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003068884 //LENGTH 21.460 LUMPCC 0.0006286742 DR + +*CONN +*I mux_bottom_track_25\/mux_l1_in_1_:X O *L 0 *C 11.325 57.800 +*I mux_bottom_track_25\/mux_l2_in_0_:A0 I *L 0.001631 *C 18.125 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 18.088 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 9.245 49.980 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 9.200 50.025 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 9.200 55.760 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 8.740 55.760 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 8.688 56.383 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 *C 8.572 56.440 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 *C 11.033 56.440 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 *C 11.040 56.498 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 *C 11.040 57.755 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:12 *C 11.040 57.800 +*N mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:13 *C 11.325 57.800 + +*CAP +0 mux_bottom_track_25\/mux_l1_in_1_:X 1e-06 +1 mux_bottom_track_25\/mux_l2_in_0_:A0 1e-06 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00055591 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.00055591 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0002357141 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0002579659 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 6.849688e-05 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 4.624506e-05 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0001948295 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.0001948295 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.0001090916 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0001090916 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:12 5.615333e-05 +13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:13 5.397271e-05 +14 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:8 1.305897e-05 +15 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:7 0.0001160892 +16 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:9 1.305897e-05 +17 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size3_mem_1_ccff_tail[0]:6 0.0001160892 +18 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 chanx_left_out[3]:5 9.985684e-05 +19 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 chanx_left_out[3]:6 9.985684e-05 +20 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 ropt_net_128:3 2.047748e-08 +21 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 ropt_net_128:6 7.598639e-05 +22 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 ropt_net_128:4 2.047748e-08 +23 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 ropt_net_128:3 9.325229e-06 +24 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_128:4 9.325229e-06 +25 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 ropt_net_128:5 7.598639e-05 + +*RES +0 mux_bottom_track_25\/mux_l1_in_1_:X mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:13 0.152 +1 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:13 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:12 0.0001548913 +2 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 0.0045 +3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 0.001122768 +4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 0.00341 +5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 0.0003854 +6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0005558036 +7 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.00341 +8 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.00789509 +9 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +10 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_25\/mux_l2_in_0_:A0 0.152 +11 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0004107143 +12 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_25/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.005120536 + +*END + +*D_NET mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0] 0.002520303 //LENGTH 19.695 LUMPCC 0.0004821153 DR + +*CONN +*I mux_bottom_track_21\/mux_l2_in_0_:X O *L 0 *C 68.825 14.620 +*I mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 85.285 12.110 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 85.248 12.197 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 84.225 12.240 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 84.180 12.285 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 84.180 14.575 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 84.135 14.620 +*N mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 68.862 14.620 + +*CAP +0 mux_bottom_track_21\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 9.288451e-05 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 9.288451e-05 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0001540829 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0001540829 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0007711265 +7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0007711265 +8 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 chany_bottom_out[12]:3 0.0001462585 +9 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 chany_bottom_out[12]:4 0.0001462585 +10 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_107:26 9.479914e-05 +11 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_107:27 9.479914e-05 + +*RES +0 mux_bottom_track_21\/mux_l2_in_0_:X mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.01363616 +2 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.002044643 +4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0009129465 +5 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +6 mux_bottom_track_21/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_21\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0] 0.003402158 //LENGTH 28.110 LUMPCC 0.001192584 DR + +*CONN +*I mux_bottom_track_35\/mux_l2_in_0_:X O *L 0 *C 53.185 28.220 +*I mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A I *L 0.002576 *C 56.365 4.255 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 *C 56.365 4.255 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 *C 56.580 4.420 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 *C 56.580 4.465 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 *C 56.580 28.175 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 *C 56.535 28.220 +*N mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 *C 53.223 28.220 + +*CAP +0 mux_bottom_track_35\/mux_l2_in_0_:X 1e-06 +1 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A 1e-06 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 4.897145e-05 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 5.258603e-05 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.0008957934 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0008957934 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.0001572146 +7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.0001572146 +8 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 chany_bottom_in[18] 0.0003037257 +9 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 chany_bottom_in[18]:18 0.0003037257 +10 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:5 0.000157376 +11 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_tree_tapbuf_size2_mem_11_ccff_tail[0]:4 0.000157376 +12 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 optlc_net_108:15 0.0001351905 +13 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 optlc_net_108:16 0.0001351905 + +*RES +0 mux_bottom_track_35\/mux_l2_in_0_:X mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 0.152 +1 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 0.0001168478 +2 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:3 0.0045 +3 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 0.0045 +4 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:4 0.02116965 +5 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:7 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:6 0.002957589 +6 mux_bottom_track_35/sky130_fd_sc_hd__mux2_1_1_X[0]:2 mux_bottom_track_35\/sky130_fd_sc_hd__buf_4_0_:A 0.152 + +*END + +*D_NET mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0] 0.001434629 //LENGTH 12.220 LUMPCC 0 DR + +*CONN +*I mux_left_track_25\/mux_l1_in_0_:X O *L 0 *C 28.235 79.560 +*I mux_left_track_25\/mux_l2_in_0_:A1 I *L 0.00198 *C 16.925 79.900 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 *C 16.963 79.900 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 *C 22.080 79.900 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 *C 22.080 79.560 +*N mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 *C 28.198 79.560 + +*CAP +0 mux_left_track_25\/mux_l1_in_0_:X 1e-06 +1 mux_left_track_25\/mux_l2_in_0_:A1 1e-06 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.0002948301 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003171641 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.0004214845 +5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.0003991505 + +*RES +0 mux_left_track_25\/mux_l1_in_0_:X mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 0.152 +1 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 mux_left_track_25\/mux_l2_in_0_:A1 0.152 +2 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:5 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 0.005462054 +3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:2 0.004569197 +4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:4 mux_left_track_25/sky130_fd_sc_hd__mux2_1_0_X[0]:3 0.0003035715 + +*END + +*D_NET ropt_net_140 0.001107697 //LENGTH 9.215 LUMPCC 0.0001918381 DR + +*CONN +*I ropt_mt_inst_729:X O *L 0 *C 11.695 90.780 +*I ropt_mt_inst_756:A I *L 0.001767 *C 3.220 91.120 +*N ropt_net_140:2 *C 3.220 91.120 +*N ropt_net_140:3 *C 3.220 90.780 +*N ropt_net_140:4 *C 11.658 90.780 + +*CAP +0 ropt_mt_inst_729:X 1e-06 +1 ropt_mt_inst_756:A 1e-06 +2 ropt_net_140:2 5.57348e-05 +3 ropt_net_140:3 0.0004427495 +4 ropt_net_140:4 0.0004153742 +5 ropt_net_140:4 chanx_left_out[19]:6 4.303325e-05 +6 ropt_net_140:3 chanx_left_out[19]:5 4.303325e-05 +7 ropt_net_140:4 ropt_net_113:8 5.288581e-05 +8 ropt_net_140:3 ropt_net_113:7 5.288581e-05 + +*RES +0 ropt_mt_inst_729:X ropt_net_140:4 0.152 +1 ropt_net_140:2 ropt_mt_inst_756:A 0.152 +2 ropt_net_140:4 ropt_net_140:3 0.007533482 +3 ropt_net_140:3 ropt_net_140:2 0.0003035715 + +*END + +*D_NET ropt_net_146 0.0004883838 //LENGTH 4.760 LUMPCC 0 DR + +*CONN +*I ropt_mt_inst_734:X O *L 0 *C 4.140 99.960 +*I ropt_mt_inst_765:A I *L 0.001766 *C 7.820 99.280 +*N ropt_net_146:2 *C 7.783 99.280 +*N ropt_net_146:3 *C 4.140 99.280 +*N ropt_net_146:4 *C 4.140 99.960 + +*CAP +0 ropt_mt_inst_734:X 1e-06 +1 ropt_mt_inst_765:A 1e-06 +2 ropt_net_146:2 0.0001919735 +3 ropt_net_146:3 0.0002311732 +4 ropt_net_146:4 6.323709e-05 + +*RES +0 ropt_mt_inst_734:X ropt_net_146:4 0.152 +1 ropt_net_146:2 ropt_mt_inst_765:A 0.152 +2 ropt_net_146:4 ropt_net_146:3 0.0006071429 +3 ropt_net_146:3 ropt_net_146:2 0.003252232 + +*END + +*D_NET ropt_net_129 0.002684506 //LENGTH 18.570 LUMPCC 0.001058272 DR + +*CONN +*I BUFT_RR_46:X O *L 0 *C 7.820 44.880 +*I ropt_mt_inst_744:A I *L 0.001766 *C 12.420 53.040 +*N ropt_net_129:2 *C 12.383 53.040 +*N ropt_net_129:3 *C 10.120 53.040 +*N ropt_net_129:4 *C 10.120 52.360 +*N ropt_net_129:5 *C 5.565 52.360 +*N ropt_net_129:6 *C 5.520 52.315 +*N ropt_net_129:7 *C 5.520 44.925 +*N ropt_net_129:8 *C 5.565 44.880 +*N ropt_net_129:9 *C 7.783 44.880 + +*CAP +0 BUFT_RR_46:X 1e-06 +1 ropt_mt_inst_744:A 1e-06 +2 ropt_net_129:2 0.0001246811 +3 ropt_net_129:3 0.0001696777 +4 ropt_net_129:4 0.0002825437 +5 ropt_net_129:5 0.0002375471 +6 ropt_net_129:6 0.0003473188 +7 ropt_net_129:7 0.0003473188 +8 ropt_net_129:8 5.757354e-05 +9 ropt_net_129:9 5.757354e-05 +10 ropt_net_129:6 chany_bottom_in[6]:4 1.546417e-05 +11 ropt_net_129:6 chany_bottom_in[6]:8 6.465518e-08 +12 ropt_net_129:8 chany_bottom_in[6]:6 9.45198e-05 +13 ropt_net_129:7 chany_bottom_in[6]:5 1.546417e-05 +14 ropt_net_129:7 chany_bottom_in[6]:9 6.465518e-08 +15 ropt_net_129:9 chany_bottom_in[6]:7 9.45198e-05 +16 ropt_net_129:6 chanx_left_in[4]:13 0.0001295266 +17 ropt_net_129:7 chanx_left_in[4]:12 0.0001295266 +18 ropt_net_129:2 chanx_left_in[14]:6 7.649747e-05 +19 ropt_net_129:3 chanx_left_in[14]:7 7.649747e-05 +20 ropt_net_129:5 ropt_net_135:6 6.878073e-05 +21 ropt_net_129:4 ropt_net_135:7 6.878073e-05 +22 ropt_net_129:8 chanx_left_out[6]:5 6.826186e-05 +23 ropt_net_129:9 chanx_left_out[6]:6 6.826186e-05 +24 ropt_net_129:5 ropt_net_128:3 7.493876e-05 +25 ropt_net_129:4 ropt_net_128:4 7.493876e-05 +26 ropt_net_129:4 ropt_net_128:3 1.081735e-06 +27 ropt_net_129:3 ropt_net_128:2 1.081735e-06 + +*RES +0 BUFT_RR_46:X ropt_net_129:9 0.152 +1 ropt_net_129:2 ropt_mt_inst_744:A 0.152 +2 ropt_net_129:5 ropt_net_129:4 0.004066965 +3 ropt_net_129:6 ropt_net_129:5 0.0045 +4 ropt_net_129:8 ropt_net_129:7 0.0045 +5 ropt_net_129:7 ropt_net_129:6 0.006598215 +6 ropt_net_129:9 ropt_net_129:8 0.001979911 +7 ropt_net_129:4 ropt_net_129:3 0.0006071429 +8 ropt_net_129:3 ropt_net_129:2 0.002020089 + +*END + +*D_NET chanx_left_out[19] 0.0007013943 //LENGTH 5.780 LUMPCC 8.60665e-05 DR + +*CONN +*I ropt_mt_inst_756:X O *L 0 *C 4.140 90.440 +*P chanx_left_out[19] O *L 0.7423 *C 1.298 88.400 +*N chanx_left_out[19]:2 *C 1.380 88.400 +*N chanx_left_out[19]:3 *C 1.380 88.458 +*N chanx_left_out[19]:4 *C 1.380 90.395 +*N chanx_left_out[19]:5 *C 1.425 90.440 +*N chanx_left_out[19]:6 *C 4.103 90.440 + +*CAP +0 ropt_mt_inst_756:X 1e-06 +1 chanx_left_out[19] 3.180286e-05 +2 chanx_left_out[19]:2 3.180286e-05 +3 chanx_left_out[19]:3 0.0001183418 +4 chanx_left_out[19]:4 0.0001183418 +5 chanx_left_out[19]:5 0.0001570193 +6 chanx_left_out[19]:6 0.0001570193 +7 chanx_left_out[19]:6 ropt_net_140:4 4.303325e-05 +8 chanx_left_out[19]:5 ropt_net_140:3 4.303325e-05 + +*RES +0 ropt_mt_inst_756:X chanx_left_out[19]:6 0.152 +1 chanx_left_out[19]:6 chanx_left_out[19]:5 0.002390625 +2 chanx_left_out[19]:5 chanx_left_out[19]:4 0.0045 +3 chanx_left_out[19]:4 chanx_left_out[19]:3 0.001729911 +4 chanx_left_out[19]:3 chanx_left_out[19]:2 0.00341 +5 chanx_left_out[19]:2 chanx_left_out[19] 2.35e-05 + +*END + +*D_NET ropt_net_124 0.001998988 //LENGTH 19.320 LUMPCC 0 DR + +*CONN +*I BUFT_P_81:X O *L 0 *C 5.980 34.680 +*I ropt_mt_inst_739:A I *L 0.001766 *C 3.220 44.880 +*N ropt_net_124:2 *C 3.183 44.880 +*N ropt_net_124:3 *C 1.425 44.880 +*N ropt_net_124:4 *C 1.380 44.835 +*N ropt_net_124:5 *C 1.380 43.520 +*N ropt_net_124:6 *C 2.300 43.520 +*N ropt_net_124:7 *C 2.300 34.045 +*N ropt_net_124:8 *C 2.345 34.000 +*N ropt_net_124:9 *C 5.980 34.000 +*N ropt_net_124:10 *C 5.980 34.680 + +*CAP +0 BUFT_P_81:X 1e-06 +1 ropt_mt_inst_739:A 1e-06 +2 ropt_net_124:2 0.0001226156 +3 ropt_net_124:3 0.0001226156 +4 ropt_net_124:4 7.901777e-05 +5 ropt_net_124:5 0.0001297724 +6 ropt_net_124:6 0.0005286267 +7 ropt_net_124:7 0.0004778721 +8 ropt_net_124:8 0.0002050702 +9 ropt_net_124:9 0.00025301 +10 ropt_net_124:10 7.838786e-05 + +*RES +0 BUFT_P_81:X ropt_net_124:10 0.152 +1 ropt_net_124:10 ropt_net_124:9 0.0006071429 +2 ropt_net_124:8 ropt_net_124:7 0.0045 +3 ropt_net_124:7 ropt_net_124:6 0.008459821 +4 ropt_net_124:3 ropt_net_124:2 0.001569197 +5 ropt_net_124:4 ropt_net_124:3 0.0045 +6 ropt_net_124:2 ropt_mt_inst_739:A 0.152 +7 ropt_net_124:9 ropt_net_124:8 0.003245536 +8 ropt_net_124:5 ropt_net_124:4 0.001174107 +9 ropt_net_124:6 ropt_net_124:5 0.0008214285 + +*END + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v new file mode 100644 index 0000000..625f10a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v @@ -0,0 +1,1797 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v new file mode 100644 index 0000000..cc6b129 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -0,0 +1,3193 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x874000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x59800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v new file mode 100644 index 0000000..0b8683b --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -0,0 +1,1678 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( net_net_72 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , bottom_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_112 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( top_grid_pin_21_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_7 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_top_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_128 } ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( top_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_111 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_711 ( .A ( ropt_net_112 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_113 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_116 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_118 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_left_in[0] ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_125 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_126 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_127 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_128 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_129 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_130 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_131 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_132 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_134 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_135 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_89 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_95 ( .A ( BUF_net_58 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_161 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_102 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_138 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_142 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_143 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_147 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_165 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[6] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..ea0616f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -0,0 +1,1695 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..358db2d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -0,0 +1,3095 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x929200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x947600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..b89e109 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -0,0 +1,1583 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_75 ( .A ( net_net_75 ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_105 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_16_ , top_grid_pin_17_ , + top_grid_pin_18_ , top_grid_pin_19_ , top_grid_pin_20_ , + top_grid_pin_21_ , top_grid_pin_22_ , top_grid_pin_23_ , + top_grid_pin_24_ , top_grid_pin_25_ , top_grid_pin_26_ , + top_grid_pin_27_ , top_grid_pin_28_ , top_grid_pin_29_ , + top_grid_pin_30_ , top_grid_pin_31_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_16_ ; +output [0:0] top_grid_pin_17_ ; +output [0:0] top_grid_pin_18_ ; +output [0:0] top_grid_pin_19_ ; +output [0:0] top_grid_pin_20_ ; +output [0:0] top_grid_pin_21_ ; +output [0:0] top_grid_pin_22_ ; +output [0:0] top_grid_pin_23_ ; +output [0:0] top_grid_pin_24_ ; +output [0:0] top_grid_pin_25_ ; +output [0:0] top_grid_pin_26_ ; +output [0:0] top_grid_pin_27_ ; +output [0:0] top_grid_pin_28_ ; +output [0:0] top_grid_pin_29_ ; +output [0:0] top_grid_pin_30_ ; +output [0:0] top_grid_pin_31_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_134 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( top_grid_pin_17_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_4 mux_bottom_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( top_grid_pin_20_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_5 mux_bottom_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size10_6 mux_bottom_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( top_grid_pin_24_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10 mux_bottom_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( top_grid_pin_25_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( top_grid_pin_28_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size10_3 mux_bottom_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( top_grid_pin_29_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_bottom_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_bottom_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_bottom_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_bottom_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_bottom_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( top_grid_pin_18_ ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size8_5 mux_bottom_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( top_grid_pin_19_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_6 mux_bottom_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_135 } ) , + .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8 mux_bottom_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( top_grid_pin_23_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( top_grid_pin_26_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_1 mux_bottom_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[15] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( top_grid_pin_27_ ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_2 mux_bottom_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( top_grid_pin_30_ ) , .p0 ( optlc_net_127 ) ) ; +mux_tree_tapbuf_size8_3 mux_bottom_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , + chanx_left_in[19] , chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( top_grid_pin_31_ ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_bottom_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_bottom_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_bottom_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_bottom_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_bottom_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_bottom_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_bottom_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( top_grid_pin_16_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_143 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_172 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_148 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_70 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_149 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_150 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_151 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_153 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_155 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_157 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_158 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_161 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_179 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_180 ) , + .X ( top_grid_pin_21_[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_162 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_104 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_163 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_187 ) , + .X ( top_grid_pin_22_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_190 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[9] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v new file mode 100644 index 0000000..a865663 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -0,0 +1,307 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +// + +mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v new file mode 100644 index 0000000..5a8568a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -0,0 +1,1876 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail , VDD , + VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x947600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v new file mode 100644 index 0000000..8a8cee9 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -0,0 +1,300 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_125 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +// + +mux_tree_tapbuf_size10 mux_bottom_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_161 ) ) ; +mux_tree_tapbuf_size10_mem mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( { ropt_net_196 } ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_169 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_170 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_171 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_173 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_175 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_176 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_184 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_205 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_45 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_198 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_199 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_208 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_left_in[10] ) , + .X ( BUF_net_52 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_212 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_214 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_221 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_222 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_68 ( .A ( aps_rename_1_ ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_223 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_226 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_227 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_52 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_62 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_148 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_150 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_153 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_171 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v new file mode 100644 index 0000000..347a91d --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -0,0 +1,414 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v new file mode 100644 index 0000000..8d139a6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -0,0 +1,2151 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v new file mode 100644 index 0000000..8fc92cf --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -0,0 +1,400 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_142 ( .A ( net_net_76 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_144 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_145 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( { ropt_net_176 } ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_147 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_188 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_154 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_167 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_170 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_171 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_175 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_47 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_176 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_51 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_177 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_178 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_179 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_181 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_206 ) , + .X ( right_grid_pin_52_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_184 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_116 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_47 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_51 ) , + .X ( ropt_net_208 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..e8e284a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -0,0 +1,1769 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..6582866 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -0,0 +1,3483 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x96600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x59800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x64400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..d3401fd --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -0,0 +1,1650 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__56 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_120 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__40 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_52_ , left_grid_pin_0_ , + left_grid_pin_1_ , left_grid_pin_2_ , left_grid_pin_3_ , + left_grid_pin_4_ , left_grid_pin_5_ , left_grid_pin_6_ , + left_grid_pin_7_ , left_grid_pin_8_ , left_grid_pin_9_ , + left_grid_pin_10_ , left_grid_pin_11_ , left_grid_pin_12_ , + left_grid_pin_13_ , left_grid_pin_14_ , left_grid_pin_15_ , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:19] chany_top_in ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chany_top_out ; +output [0:0] right_grid_pin_52_ ; +output [0:0] left_grid_pin_0_ ; +output [0:0] left_grid_pin_1_ ; +output [0:0] left_grid_pin_2_ ; +output [0:0] left_grid_pin_3_ ; +output [0:0] left_grid_pin_4_ ; +output [0:0] left_grid_pin_5_ ; +output [0:0] left_grid_pin_6_ ; +output [0:0] left_grid_pin_7_ ; +output [0:0] left_grid_pin_8_ ; +output [0:0] left_grid_pin_9_ ; +output [0:0] left_grid_pin_10_ ; +output [0:0] left_grid_pin_11_ ; +output [0:0] left_grid_pin_12_ ; +output [0:0] left_grid_pin_13_ ; +output [0:0] left_grid_pin_14_ ; +output [0:0] left_grid_pin_15_ ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( right_grid_pin_52_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_2 mux_right_ipin_1 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( left_grid_pin_1_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , + chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , + chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( left_grid_pin_4_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_ipin_5 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , + chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( left_grid_pin_5_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_ipin_8 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( left_grid_pin_8_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10 mux_right_ipin_9 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[14] , + chany_top_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( left_grid_pin_9_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , + chany_top_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( left_grid_pin_12_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_4 mux_right_ipin_13 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[14] , chany_top_in[14] , chany_bottom_in[18] , + chany_top_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( { ropt_net_141 } ) , + .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( left_grid_pin_2_ ) , .p0 ( optlc_net_132 ) ) ; +mux_tree_tapbuf_size8_5 mux_right_ipin_3 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( left_grid_pin_3_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( left_grid_pin_6_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8 mux_right_ipin_7 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( left_grid_pin_7_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_0 mux_right_ipin_10 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[15] , chany_top_in[15] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( left_grid_pin_10_ ) , .p0 ( optlc_net_130 ) ) ; +mux_tree_tapbuf_size8_1 mux_right_ipin_11 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , + chany_bottom_in[16] , chany_top_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( left_grid_pin_11_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_ipin_14 ( + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , + chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[19] , chany_top_in[19] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( left_grid_pin_14_ ) , .p0 ( optlc_net_133 ) ) ; +mux_tree_tapbuf_size8_3 mux_right_ipin_15 ( + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , + chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , + chany_bottom_in[12] , chany_top_in[12] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( left_grid_pin_15_ ) , .p0 ( optlc_net_131 ) ) ; +mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_right_ipin_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_159 } ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_141 ) , + .X ( left_grid_pin_13_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_145 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_149 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[13] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_176 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_153 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_67 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_155 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_156 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_157 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_159 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_110 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_111 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_164 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_165 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_167 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_185 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[19] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v new file mode 100644 index 0000000..33bf84a --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -0,0 +1,1236 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v new file mode 100644 index 0000000..ca1e1eb --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -0,0 +1,3441 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v new file mode 100644 index 0000000..635c171 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -0,0 +1,1110 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__33 ( .A ( mem_out[1] ) , + .X ( net_aps_33 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( net_aps_33 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + right_bottom_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size2_8 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_24 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_113 ) ) ; +mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( { ropt_net_117 } ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size6_0 mux_right_track_0 ( + .in ( { chany_top_in[19] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; +mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_top_grid_pin_42_[0] , + right_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_116 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_117 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_119 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_146 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_57 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chanx_right_in[17] ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chanx_right_in[19] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_125 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_57 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_62 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( BUF_net_64 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_top_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_135 ) , + .X ( ropt_net_142 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v new file mode 100644 index 0000000..563ef38 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -0,0 +1,2164 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +// + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; +mux_tree_tapbuf_size5 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size2 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v new file mode 100644 index 0000000..8a91ddf --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -0,0 +1,4783 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x915400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v new file mode 100644 index 0000000..153ece4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -0,0 +1,1968 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__57 ( .A ( mem_out[1] ) , + .X ( net_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_168 ( .A ( net_net_101 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_147 ( .A ( BUF_net_66 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_top_grid_pin_42_ , right_top_grid_pin_43_ , + right_top_grid_pin_44_ , right_top_grid_pin_45_ , right_top_grid_pin_46_ , + right_top_grid_pin_47_ , right_top_grid_pin_48_ , right_top_grid_pin_49_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , + chanx_right_out , chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +// + +mux_tree_tapbuf_size6_4 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , + chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , + chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , + chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( { ropt_net_190 } ) , + .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .in ( { chany_top_in[2] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , + chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , + chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , + chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .out ( { ropt_net_194 } ) , + .p0 ( optlc_net_183 ) ) ; +mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; +mux_tree_tapbuf_size5 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , + chany_bottom_in[4] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , + chany_bottom_in[8] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( { ropt_net_192 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[7] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_191 } ) , + .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_5 mux_top_track_24 ( + .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , + chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4 mux_top_track_32 ( + .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[7] , chany_top_in[8] , right_top_grid_pin_42_[0] , + chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .in ( { chany_top_in[9] , chany_top_in[11] , right_top_grid_pin_43_[0] , + chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_44_[0] , + chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .in ( { chany_top_in[12] , chany_top_in[19] , right_top_grid_pin_45_[0] , + chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .in ( { chany_top_in[18] , right_top_grid_pin_42_[0] , + chany_bottom_in[18] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7 mux_right_track_6 ( + .in ( { chany_top_in[3] , chany_top_in[6] , right_top_grid_pin_43_[0] , + right_top_grid_pin_45_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_1 mux_right_track_16 ( + .in ( { chany_top_in[13] , right_top_grid_pin_46_[0] , + chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_186 ) ) ; +mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .in ( { chany_top_in[14] , right_top_grid_pin_47_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .in ( { chany_top_in[16] , right_top_grid_pin_48_[0] , + chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_187 ) ) ; +mux_tree_tapbuf_size3 mux_right_track_22 ( + .in ( { chany_top_in[17] , right_top_grid_pin_49_[0] , + chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_185 ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( { ropt_net_197 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size2 mux_right_track_26 ( + .in ( { right_top_grid_pin_43_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_184 ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_203 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_205 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_209 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_210 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_211 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[18] ) , + .X ( aps_rename_2_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_212 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_213 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chany_bottom_in[2] ) , + .X ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_214 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chany_bottom_in[5] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_215 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_848 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_850 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_99 ( .A ( aps_rename_2_ ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_232 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_216 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_217 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_853 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_854 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_235 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_238 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_239 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_860 ( .A ( ropt_net_240 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_242 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_158 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( BUF_net_86 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_161 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_162 ( .A ( BUF_net_89 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_164 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_210 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v new file mode 100644 index 0000000..e1ad319 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -0,0 +1,639 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size2_4 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v new file mode 100644 index 0000000..1513fc2 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -0,0 +1,2823 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size2_4 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1048800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1048800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v new file mode 100644 index 0000000..3fd2bd9 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -0,0 +1,583 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__39 ( .A ( mem_out[1] ) , + .X ( net_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( net_net_74 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , + chany_bottom_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +// + +mux_tree_tapbuf_size2_4 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_6 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_111 ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_112 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_139 } ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_142 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_146 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_115 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_148 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_118 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_122 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_124 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( + .A ( chany_bottom_in[15] ) , .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_129 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( + .A ( chany_bottom_in[12] ) , .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( .A ( chanx_right_in[0] ) , + .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_44 ( .A ( chanx_right_in[2] ) , + .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_45 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_48 ( .A ( chanx_right_in[7] ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_135 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_153 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( + .A ( chany_bottom_in[19] ) , .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_155 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_137 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_159 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_161 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_67 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_45 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( BUF_net_48 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_44 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_93 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_99 ( .A ( BUF_net_42 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_105 ( .A ( BUF_net_64 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( BUF_net_67 ) , + .X ( ropt_net_149 ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v new file mode 100644 index 0000000..3fa43e5 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -0,0 +1,2701 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v new file mode 100644 index 0000000..337d7ca --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -0,0 +1,5250 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , + VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1343200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1380000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1232800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1242000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1315600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1196000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1269600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1288000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1269600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1288000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1242000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1260400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1288000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1306400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1315600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1352400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1163800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1182200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1228200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1237400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1343200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1209800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1288000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1306400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1297200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1117800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1163800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1269600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1288000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1136200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1228200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1288000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1306400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1062600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1246600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1094800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1214400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1136200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1076400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1209800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1274200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1292600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1173000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1232800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1278800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1076400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1131600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1251200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1159200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x915400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1237400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1048800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1076400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1306400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1343200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1380000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v new file mode 100644 index 0000000..ab9c9e3 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -0,0 +1,2470 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__58 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , right_bottom_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size8 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size8_2 mux_right_track_8 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size8_0 mux_left_track_3 ( + .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size8_1 mux_left_track_9 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + chanx_right_in[6] , chanx_right_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_4 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_16 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_3 mux_right_track_24 ( + .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_25 ( + .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , + chanx_right_in[9] , chanx_right_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_121 ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[8] , + chanx_right_in[15] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_right_in[9] , + chanx_right_in[19] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_right_in[10] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_right_in[12] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_right_in[13] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_right_in[14] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_right_in[16] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[17] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , chanx_right_in[18] , + chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size3 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_7_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_126 ) ) ; +mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_125 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size9_0 mux_right_track_0 ( + .in ( { chany_top_in[6] , chany_top_in[13] , right_top_grid_pin_42_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_46_[0] , + right_top_grid_pin_48_[0] , right_bottom_grid_pin_1_[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size9 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size9_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + right_bottom_grid_pin_1_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_124 ) ) ; +mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + chanx_right_in[5] , chanx_right_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_right_track_32 ( + .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_45_[0] , right_top_grid_pin_49_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_122 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , + chanx_right_in[10] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_131 } ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , + chanx_right_in[2] , chanx_right_in[12] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_123 ) ) ; +mux_tree_tapbuf_size10_mem mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_35_[0] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_129 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_156 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_132 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_133 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_134 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_73 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_163 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_137 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_141 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_142 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_143 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_94 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_97 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_144 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_145 ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_146 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_147 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_148 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_149 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_154 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_164 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_168 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_170 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[6] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..a807632 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -0,0 +1,3159 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +// + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; +mux_tree_tapbuf_size7 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..896f0bf --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -0,0 +1,6084 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1030400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1209800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1246600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1283400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1320200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1357000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1393800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1242000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1315600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1352400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1297200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1214400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1246600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1283400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1320200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1242000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1311000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1242000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1315600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1168400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1186800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1306400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1177600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1186800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1306400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x984400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x993600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1306400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x975200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x993600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1076400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1292600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1140800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1159200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1251200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1260400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1186800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1196000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1094800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1159200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1246600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1117800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1232800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1370800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1177600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1292600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1265000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1140800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1159200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1136200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1265000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1274200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1145400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1191400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1200600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1191400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1209800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1324800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1334000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1370800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1131600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1320200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1357000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1393800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x929200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1196800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..bbd1faa --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -0,0 +1,2963 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_28__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__78 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__77 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__76 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__75 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__74 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__72 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__71 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__70 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__69 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__68 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__67 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__66 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__65 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__64 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__63 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__62 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__61 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:4] mem_out ; +output [0:4] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__60 ( .A ( mem_out[4] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__59 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__58 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , chanx_right_in , right_top_grid_pin_42_ , + right_top_grid_pin_43_ , right_top_grid_pin_44_ , right_top_grid_pin_45_ , + right_top_grid_pin_46_ , right_top_grid_pin_47_ , right_top_grid_pin_48_ , + right_top_grid_pin_49_ , chany_bottom_in , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_42_ ; +input [0:0] right_top_grid_pin_43_ ; +input [0:0] right_top_grid_pin_44_ ; +input [0:0] right_top_grid_pin_45_ ; +input [0:0] right_top_grid_pin_46_ ; +input [0:0] right_top_grid_pin_47_ ; +input [0:0] right_top_grid_pin_48_ ; +input [0:0] right_top_grid_pin_49_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:4] mux_tree_tapbuf_size16_0_sram ; +wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_1_sram ; +wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_2_sram ; +wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; +wire [0:4] mux_tree_tapbuf_size16_3_sram ; +wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +// + +mux_tree_tapbuf_size12_6 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , + chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , + chanx_left_in[13] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , + right_top_grid_pin_42_[0] , right_top_grid_pin_44_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , + chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , + right_top_grid_pin_43_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_47_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , + chanx_right_in[12] , chanx_right_in[15] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , + chanx_right_in[11] , chanx_right_in[13] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_149 ) ) ; +mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , + chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , + chany_bottom_in[12] , chany_bottom_in[19] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , + chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[4] , chany_bottom_in[13] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; +mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; +mux_tree_tapbuf_size16 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , + chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , + chanx_left_in[14] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size16_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , + right_top_grid_pin_42_[0] , right_top_grid_pin_43_[0] , + right_top_grid_pin_44_[0] , right_top_grid_pin_45_[0] , + right_top_grid_pin_46_[0] , right_top_grid_pin_47_[0] , + right_top_grid_pin_48_[0] , right_top_grid_pin_49_[0] , + chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , + chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_40_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[5] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size16_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , + chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[5] , chany_bottom_in[14] , left_top_grid_pin_42_[0] , + left_top_grid_pin_43_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_48_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size16_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; +mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; +mux_tree_tapbuf_size10 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , + chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[11] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_154 } ) , + .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; +mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , + right_top_grid_pin_42_[0] , right_top_grid_pin_46_[0] , + chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[6] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + right_top_grid_pin_43_[0] , right_top_grid_pin_47_[0] , + chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , + right_top_grid_pin_44_[0] , right_top_grid_pin_48_[0] , + chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , + chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[6] , chanx_left_in[11] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_152 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , + chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[8] , chanx_left_in[15] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , + chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[9] , chanx_left_in[18] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , + chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , + chany_bottom_in[6] , chany_bottom_in[16] , left_top_grid_pin_42_[0] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , + chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , + chany_bottom_in[8] , chany_bottom_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , + chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , + chany_bottom_in[11] , chany_bottom_in[18] , left_top_grid_pin_44_[0] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; +mux_tree_tapbuf_size7 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , + chanx_left_in[1] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .in ( { chany_top_in[10] , chany_top_in[15] , right_top_grid_pin_45_[0] , + right_top_grid_pin_49_[0] , chany_bottom_in[10] , + chany_bottom_in[19] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , + chany_bottom_in[10] , chany_bottom_in[15] , left_top_grid_pin_45_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_845 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_154 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_163 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_170 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_171 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( chanx_right_in[18] ) , + .X ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chany_bottom_in[4] ) , + .X ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_174 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_176 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_177 ) , + .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_178 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_179 ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_180 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_181 ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_859 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_125 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_127 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_89 ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_90 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_182 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_184 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_185 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_186 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_187 ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_189 ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_190 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_191 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_192 ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_193 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_195 ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_196 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_197 ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_198 ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_199 ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_200 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_202 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_203 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_869 ( .A ( ropt_net_223 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_871 ( .A ( ropt_net_224 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_225 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_873 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_876 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_879 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_880 ( .A ( ropt_net_232 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_235 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_884 ( .A ( ropt_net_236 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_885 ( .A ( ropt_net_237 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_238 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_239 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_241 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_242 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_243 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_244 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_245 ) , + .X ( chany_top_out[18] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v new file mode 100644 index 0000000..c15657f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -0,0 +1,2481 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +// + +mux_tree_tapbuf_size6_2 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v new file mode 100644 index 0000000..69f8ca4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -0,0 +1,5213 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size6_2 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x984400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x993600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1048800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1012000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1384600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1127000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1136200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1131600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1214400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1223600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1062600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1131600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1209800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1246600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1283400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1320200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1311000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1081000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1219000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1237400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1311000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1117800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1136200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1311000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1136200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1117800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1301800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1352400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1384600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1062600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1113200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1228200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1246600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1283400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1320200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1357000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1393800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1412200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1076400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1242000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1315600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1209800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1246600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1283400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1320200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1163800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1182200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1343200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1380000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1242000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1315600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x910800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1150000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1297200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1329400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1338600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1168400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1205200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1242000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1278800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1315600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1297200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1334000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1389200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1223600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1260400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1297200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1334000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1370800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1407600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1398400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v new file mode 100644 index 0000000..afe8248 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -0,0 +1,2243 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__59 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__54 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__53 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__52 ( .A ( mem_out[2] ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_98 ( .A ( net_net_98 ) , + .X ( net_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_148 ( .A ( net_net_97 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__50 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_136 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_72 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__44 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__43 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__42 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__41 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__40 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__39 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__36 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__35 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__34 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__33 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__32 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__31 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_132 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__30 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__29 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__28 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__27 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__26 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , + chany_bottom_in , bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chanx_right_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +// + +mux_tree_tapbuf_size6_2 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[5] , + chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_3 mux_right_track_4 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( { ropt_net_175 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6 mux_right_track_8 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_5 ( + .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , + chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_9 ( + .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , + chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_3 mem_right_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_5 mux_right_track_2 ( + .in ( { chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , + chanx_left_in[4] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_4 mux_right_track_16 ( + .in ( { chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , + chanx_left_in[8] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5 mux_right_track_24 ( + .in ( { chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , + chanx_left_in[9] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_1 ( + .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , + chany_bottom_in[13] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size5_3 mux_left_track_3 ( + .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , + chany_bottom_in[7] , chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .out ( { ropt_net_174 } ) , + .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_17 ( + .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , + chany_bottom_in[10] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_5_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_2 mux_left_track_25 ( + .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , + chany_bottom_in[11] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_6_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size5_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_5_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_6_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_right_track_32 ( + .in ( { chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( + .in ( { chanx_right_in[10] , bottom_left_grid_pin_36_[0] , + chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .in ( { chanx_right_in[12] , bottom_left_grid_pin_37_[0] , + chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_38_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_39_[0] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .in ( { chanx_right_in[16] , bottom_left_grid_pin_40_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_5 mux_bottom_track_23 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_163 ) ) ; +mux_tree_tapbuf_size3_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_5 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .in ( { chanx_right_in[2] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( { ropt_net_179 } ) , + .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7 mux_bottom_track_7 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_172 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size4_2 mux_bottom_track_9 ( + .in ( { chanx_right_in[8] , bottom_left_grid_pin_34_[0] , + chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_35_[0] , + chanx_left_in[9] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_168 ) ) ; +mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .in ( { chanx_right_in[18] , chanx_right_in[19] , + bottom_left_grid_pin_34_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size4 mux_left_track_33 ( + .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , + chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_164 ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( { ropt_net_194 } ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_27 ( + .in ( { chanx_right_in[15] , bottom_left_grid_pin_35_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_29 ( + .in ( { chanx_right_in[11] , bottom_left_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_167 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_31 ( + .in ( { chanx_right_in[7] , bottom_left_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_33 ( + .in ( { chanx_right_in[3] , bottom_left_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_35 ( + .in ( { chanx_right_in[1] , bottom_left_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_37 ( + .in ( { chanx_right_in[0] , bottom_left_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_166 ) ) ; +mux_tree_tapbuf_size2 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_41_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_165 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_172 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_175 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_176 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chanx_right_in[4] ) , + .X ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_206 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_209 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_211 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_213 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_214 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_215 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_217 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_194 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_195 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_76 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_196 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_219 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_147 ( .A ( BUF_net_91 ) , + .X ( chanx_right_out[13] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v new file mode 100644 index 0000000..5aadf12 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -0,0 +1,2182 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +// + +mux_tree_tapbuf_size6_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_8 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v new file mode 100644 index 0000000..749ac87 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -0,0 +1,4413 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size6_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_8 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v new file mode 100644 index 0000000..5cc0d98 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -0,0 +1,1944 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , + .X ( net_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( net_net_60 ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_43 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_88 ( .A ( BUF_net_43 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chanx_left_in , + left_top_grid_pin_42_ , left_top_grid_pin_43_ , left_top_grid_pin_44_ , + left_top_grid_pin_45_ , left_top_grid_pin_46_ , left_top_grid_pin_47_ , + left_top_grid_pin_48_ , left_top_grid_pin_49_ , left_bottom_grid_pin_1_ , + ccff_head , chany_top_out , chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +// + +mux_tree_tapbuf_size6_2 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_116 } ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size6 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size6_0 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_1 mux_left_track_5 ( + .in ( { chany_top_in[18] , left_top_grid_pin_42_[0] , + left_top_grid_pin_44_[0] , left_top_grid_pin_46_[0] , + left_top_grid_pin_48_[0] , left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size6_mem_2 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; +mux_tree_tapbuf_size5_2 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5 mux_top_track_6 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size5_0 mux_left_track_3 ( + .in ( { chany_top_in[19] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_1 mux_left_track_7 ( + .in ( { chany_top_in[17] , left_top_grid_pin_43_[0] , + left_top_grid_pin_45_[0] , left_top_grid_pin_47_[0] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5_mem_2 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem_1 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_34_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_9 ( + .in ( { chany_top_in[16] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_top_in[8] , left_top_grid_pin_42_[0] , + left_bottom_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_8 mux_top_track_10 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_9 mux_top_track_12 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_10 mux_top_track_14 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_110 ) ) ; +mux_tree_tapbuf_size2_11 mux_top_track_16 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_top_track_18 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_13 mux_top_track_20 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_14 mux_top_track_22 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_15 mux_top_track_26 ( + .in ( { top_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_16 mux_top_track_28 ( + .in ( { top_left_grid_pin_36_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_17 mux_top_track_30 ( + .in ( { top_left_grid_pin_37_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_18 mux_top_track_32 ( + .in ( { top_left_grid_pin_38_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_19 mux_top_track_34 ( + .in ( { top_left_grid_pin_39_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_20 mux_top_track_36 ( + .in ( { top_left_grid_pin_40_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_top_track_38 ( + .in ( { top_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .in ( { chany_top_in[15] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .in ( { chany_top_in[14] , left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .in ( { chany_top_in[13] , left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .in ( { chany_top_in[12] , left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .in ( { chany_top_in[11] , left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_5 mux_left_track_21 ( + .in ( { chany_top_in[10] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_left_track_23 ( + .in ( { chany_top_in[9] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_left_track_27 ( + .in ( { chany_top_in[7] , left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_top_track_14 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_top_track_18 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_top_track_20 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_top_track_22 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_top_track_26 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_top_track_28 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_17 mem_top_track_30 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_18 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_19 mem_top_track_34 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_20 mem_top_track_36 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_left_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_128 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_115 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_116 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_129 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_117 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_118 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_83 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_121 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[18] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v new file mode 100644 index 0000000..fc428e6 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -0,0 +1,2399 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +// + +mux_tree_tapbuf_size10 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v new file mode 100644 index 0000000..b713175 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -0,0 +1,4942 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size10 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size9 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x78200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x64400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1142400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y1169600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y1224000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y1251200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v new file mode 100644 index 0000000..7732476 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -0,0 +1,2210 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_112 ( .A ( net_net_83 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_117 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +input [0:13] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_34_ , + top_left_grid_pin_35_ , top_left_grid_pin_36_ , top_left_grid_pin_37_ , + top_left_grid_pin_38_ , top_left_grid_pin_39_ , top_left_grid_pin_40_ , + top_left_grid_pin_41_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_34_ , + bottom_left_grid_pin_35_ , bottom_left_grid_pin_36_ , + bottom_left_grid_pin_37_ , bottom_left_grid_pin_38_ , + bottom_left_grid_pin_39_ , bottom_left_grid_pin_40_ , + bottom_left_grid_pin_41_ , chanx_left_in , left_top_grid_pin_42_ , + left_top_grid_pin_43_ , left_top_grid_pin_44_ , left_top_grid_pin_45_ , + left_top_grid_pin_46_ , left_top_grid_pin_47_ , left_top_grid_pin_48_ , + left_top_grid_pin_49_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_top_in ; +input [0:0] top_left_grid_pin_34_ ; +input [0:0] top_left_grid_pin_35_ ; +input [0:0] top_left_grid_pin_36_ ; +input [0:0] top_left_grid_pin_37_ ; +input [0:0] top_left_grid_pin_38_ ; +input [0:0] top_left_grid_pin_39_ ; +input [0:0] top_left_grid_pin_40_ ; +input [0:0] top_left_grid_pin_41_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_42_ ; +input [0:0] left_top_grid_pin_43_ ; +input [0:0] left_top_grid_pin_44_ ; +input [0:0] left_top_grid_pin_45_ ; +input [0:0] left_top_grid_pin_46_ ; +input [0:0] left_top_grid_pin_47_ ; +input [0:0] left_top_grid_pin_48_ ; +input [0:0] left_top_grid_pin_49_ ; +input [0:0] ccff_head ; +output [0:19] chany_top_out ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size14_0_sram ; +wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size14_1_sram ; +wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +// + +mux_tree_tapbuf_size10 mux_top_track_0 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_36_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_40_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , + chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_35_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_39_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; +mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_39_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size8 mux_top_track_8 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_38_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; +mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; +mux_tree_tapbuf_size14 mux_top_track_4 ( + .in ( { top_left_grid_pin_34_[0] , top_left_grid_pin_35_[0] , + top_left_grid_pin_36_[0] , top_left_grid_pin_37_[0] , + top_left_grid_pin_38_[0] , top_left_grid_pin_39_[0] , + top_left_grid_pin_40_[0] , top_left_grid_pin_41_[0] , + top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , + chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size14_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , + bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_37_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_40_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size14_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; +mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_5 mux_top_track_16 ( + .in ( { top_left_grid_pin_35_[0] , top_left_grid_pin_39_[0] , + chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , + chanx_left_in[10] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7 mux_top_track_24 ( + .in ( { top_left_grid_pin_36_[0] , top_left_grid_pin_40_[0] , + chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , + chanx_left_in[9] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_38_[0] , chanx_left_in[5] , chanx_left_in[12] , + chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , + left_top_grid_pin_42_[0] , left_top_grid_pin_44_[0] , + left_top_grid_pin_46_[0] , left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , + left_top_grid_pin_43_[0] , left_top_grid_pin_45_[0] , + left_top_grid_pin_47_[0] , left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; +mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; +mux_tree_tapbuf_size6 mux_top_track_32 ( + .in ( { top_left_grid_pin_37_[0] , top_left_grid_pin_41_[0] , + chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_39_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .in ( { chany_top_in[10] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[0] , chanx_left_in[7] , + chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_137 ) ) ; +mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; +mux_tree_tapbuf_size9 mux_bottom_track_3 ( + .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_34_[0] , + bottom_left_grid_pin_36_[0] , bottom_left_grid_pin_38_[0] , + bottom_left_grid_pin_40_[0] , chanx_left_in[2] , chanx_left_in[9] , + chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; +mux_tree_tapbuf_size4 mux_left_track_9 ( + .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , + left_top_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_140 ) ) ; +mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , + left_top_grid_pin_44_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , + left_top_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; +mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_0 mux_left_track_17 ( + .in ( { chany_top_in[13] , chany_bottom_in[13] , + left_top_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .in ( { chany_top_in[14] , chany_bottom_in[14] , + left_top_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .in ( { chany_top_in[16] , chany_bottom_in[16] , + left_top_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .in ( { chany_top_in[17] , chany_bottom_in[17] , + left_top_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_139 ) ) ; +mux_tree_tapbuf_size3 mux_left_track_25 ( + .in ( { chany_top_in[18] , chany_bottom_in[18] , + left_top_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_138 ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_181 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_148 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_149 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__26 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( left_top_grid_pin_43_[0] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_154 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_155 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_157 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_158 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_186 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_159 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_160 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_161 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_163 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_164 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_165 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_166 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_167 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_169 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_170 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_108 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_109 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_171 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_172 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_69 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_173 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_174 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_189 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_176 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_177 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_178 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_194 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_195 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_197 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_201 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_202 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_206 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v new file mode 100644 index 0000000..21eaed4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -0,0 +1,1595 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) ) ; +endmodule + + +module const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v new file mode 100644 index 0000000..8d715ad --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -0,0 +1,3833 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; +// + +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1099400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1122400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +endmodule + + diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v new file mode 100644 index 0000000..78bc88f --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -0,0 +1,1427 @@ +// +// +// +// +// +// +module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__39 ( .A ( mem_out[1] ) , + .X ( net_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( net_net_59 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__38 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__37 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__36 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__35 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__34 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__33 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__28 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__24 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__23 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__22 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_44 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( .A ( BUF_net_44 ) , .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__21 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__20 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( BUF_net_41 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( BUF_net_41 ) , + .X ( out[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__19 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__18 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__17 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__16 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_34_ , bottom_left_grid_pin_35_ , + bottom_left_grid_pin_36_ , bottom_left_grid_pin_37_ , + bottom_left_grid_pin_38_ , bottom_left_grid_pin_39_ , + bottom_left_grid_pin_40_ , bottom_left_grid_pin_41_ , chanx_left_in , + left_top_grid_pin_1_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail ) ; +input [0:0] prog_clk ; +input [0:19] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_34_ ; +input [0:0] bottom_left_grid_pin_35_ ; +input [0:0] bottom_left_grid_pin_36_ ; +input [0:0] bottom_left_grid_pin_37_ ; +input [0:0] bottom_left_grid_pin_38_ ; +input [0:0] bottom_left_grid_pin_39_ ; +input [0:0] bottom_left_grid_pin_40_ ; +input [0:0] bottom_left_grid_pin_41_ ; +input [0:19] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:19] chany_bottom_out ; +output [0:19] chanx_left_out ; +output [0:0] ccff_tail ; + +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +// + +mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_115 } ) , + .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6 mux_bottom_track_5 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_35_[0] , + bottom_left_grid_pin_37_[0] , bottom_left_grid_pin_39_[0] , + bottom_left_grid_pin_41_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; +mux_tree_tapbuf_size6_mem mem_bottom_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; +mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_109 ) ) ; +mux_tree_tapbuf_size5 mux_bottom_track_7 ( + .in ( { bottom_left_grid_pin_34_[0] , bottom_left_grid_pin_36_[0] , + bottom_left_grid_pin_38_[0] , bottom_left_grid_pin_40_[0] , + chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; +mux_tree_tapbuf_size5_mem mem_bottom_track_7 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; +mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_41_[0] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; +mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_34_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .in ( { bottom_left_grid_pin_35_[0] , chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_9 mux_bottom_track_31 ( + .in ( { bottom_left_grid_pin_36_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_10 mux_bottom_track_33 ( + .in ( { bottom_left_grid_pin_37_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_11 mux_bottom_track_35 ( + .in ( { bottom_left_grid_pin_38_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2_12 mux_bottom_track_37 ( + .in ( { bottom_left_grid_pin_39_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_13 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_40_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_107 ) ) ; +mux_tree_tapbuf_size2_14 mux_left_track_1 ( + .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_105 ) ) ; +mux_tree_tapbuf_size2_16 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_108 ) ) ; +mux_tree_tapbuf_size2 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_15 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_106 ) ) ; +mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_9 mem_bottom_track_31 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_10 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_11 mem_bottom_track_35 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_12 mem_bottom_track_37 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_13 mem_bottom_track_39 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_14 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_16 mem_left_track_5 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; +mux_tree_tapbuf_size2_mem_15 mem_left_track_25 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( { ropt_net_112 } ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_130 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_111 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_115 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_53 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_54 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_137 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_122 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_125 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_126 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_127 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_129 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_85 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_113 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_143 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_144 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_145 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_91 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[8] ) ) ; +endmodule + +